From 8074e1e1adde7587d36eca6745342c14f1dcd8fb Mon Sep 17 00:00:00 2001 From: wuwentao Date: Fri, 14 Jun 2024 11:45:05 +0800 Subject: [PATCH] k230 sdk release v1.6 --- .gitlab-ci.yml | 25 +- Kconfig.board | 5 + Kconfig.wifi | 3 + Makefile | 6 +- .../dev_firmware/rtl8188fu/rtl8188fufw.bin | Bin 0 -> 21020 bytes .../gen_image_script/gen_image_comm_func.sh | 5 + configs/k230_canmv_01studio_defconfig | 4 +- ...onfig2 => k230_canmv_dongshanpi_defconfig} | 41 +- configs/k230_canmv_only_rtt_defconfig | 4 +- configs/k230_canmv_v2_only_rtt_defconfig | 2 +- configs/k230d_canmv_only_rtt_defconfig | 6 +- repo.mak | 12 +- .../mpp/include/comm/k_board_config_comm.h | 27 + src/big/mpp/include/comm/k_connector_comm.h | 1 + src/big/mpp/include/comm/k_dewarp_comm.h | 1 - src/big/mpp/include/comm/k_isp_comm.h | 1 + src/big/mpp/include/comm/k_sensor_comm.h | 5 + src/big/mpp/include/comm/k_vicap_comm.h | 21 + src/big/mpp/include/comm/k_video_comm.h | 3 + src/big/mpp/include/ioctl/k_sensor_ioctl.h | 5 +- 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.../rtl8188fu/hal/btc/HalBtc8192e1Ant.h | 255 + .../rtl8188fu/hal/btc/HalBtc8192e2Ant.c | 5028 + .../rtl8188fu/hal/btc/HalBtc8192e2Ant.h | 232 + .../rtl8188fu/hal/btc/HalBtc8703b1Ant.c | 5239 + .../rtl8188fu/hal/btc/HalBtc8703b1Ant.h | 387 + .../rtl8188fu/hal/btc/HalBtc8703b2Ant.c | 4865 + .../rtl8188fu/hal/btc/HalBtc8703b2Ant.h | 229 + .../rtl8188fu/hal/btc/HalBtc8723a1Ant.c | 1545 + .../rtl8188fu/hal/btc/HalBtc8723a1Ant.h | 172 + .../rtl8188fu/hal/btc/HalBtc8723a2Ant.c | 3747 + .../rtl8188fu/hal/btc/HalBtc8723a2Ant.h | 185 + .../rtl8188fu/hal/btc/HalBtc8723b1Ant.c | 5639 + .../rtl8188fu/hal/btc/HalBtc8723b1Ant.h | 338 + .../rtl8188fu/hal/btc/HalBtc8723b2Ant.c | 4934 + .../rtl8188fu/hal/btc/HalBtc8723b2Ant.h | 235 + .../rtl8188fu/hal/btc/HalBtc8812a1Ant.c | 3718 + .../rtl8188fu/hal/btc/HalBtc8812a1Ant.h | 259 + .../rtl8188fu/hal/btc/HalBtc8812a2Ant.c | 5435 + .../rtl8188fu/hal/btc/HalBtc8812a2Ant.h | 250 + .../rtl8188fu/hal/btc/HalBtc8821a1Ant.c | 3434 + .../rtl8188fu/hal/btc/HalBtc8821a1Ant.h | 214 + .../rtl8188fu/hal/btc/HalBtc8821a2Ant.c | 4859 + .../rtl8188fu/hal/btc/HalBtc8821a2Ant.h | 227 + .../rtl8188fu/hal/btc/HalBtc8821aCsr2Ant.c | 4344 + .../rtl8188fu/hal/btc/HalBtc8821aCsr2Ant.h | 208 + .../wireless/rtl8188fu/hal/btc/HalBtcOutSrc.h | 748 + .../wireless/rtl8188fu/hal/btc/Mp_Precomp.h | 89 + .../wireless/rtl8188fu/hal/efuse/efuse_mask.h | 81 + .../efuse/rtl8188f/HalEfuseMask8188F_SDIO.c | 103 + .../efuse/rtl8188f/HalEfuseMask8188F_SDIO.h | 41 + .../efuse/rtl8188f/HalEfuseMask8188F_USB.c | 101 + .../efuse/rtl8188f/HalEfuseMask8188F_USB.h | 42 + .../net/wireless/rtl8188fu/hal/hal_btcoex.c | 3690 + .../net/wireless/rtl8188fu/hal/hal_com.c | 4842 + .../net/wireless/rtl8188fu/hal/hal_com_c2h.h | 76 + .../wireless/rtl8188fu/hal/hal_com_phycfg.c | 4303 + .../net/wireless/rtl8188fu/hal/hal_dm.c | 197 + .../net/wireless/rtl8188fu/hal/hal_dm.h | 26 + .../wireless/rtl8188fu/hal/hal_hci/hal_usb.c | 499 + .../net/wireless/rtl8188fu/hal/hal_intf.c | 1086 + .../net/wireless/rtl8188fu/hal/hal_mp.c | 2164 + .../net/wireless/rtl8188fu/hal/hal_phy.c | 285 + .../wireless/rtl8188fu/hal/led/hal_usb_led.c | 5180 + .../wireless/rtl8188fu/hal/phydm/halhwimg.h | 124 + .../rtl8188fu/hal/phydm/halphyrf_ap.c | 2504 + .../rtl8188fu/hal/phydm/halphyrf_ap.h | 162 + .../rtl8188fu/hal/phydm/halphyrf_ce.c | 711 + .../rtl8188fu/hal/phydm/halphyrf_ce.h | 106 + .../rtl8188fu/hal/phydm/halphyrf_win.c | 716 + .../rtl8188fu/hal/phydm/halphyrf_win.h | 108 + .../wireless/rtl8188fu/hal/phydm/mp_precomp.h | 20 + .../net/wireless/rtl8188fu/hal/phydm/phydm.c | 2165 + .../net/wireless/rtl8188fu/hal/phydm/phydm.h | 1440 + .../wireless/rtl8188fu/hal/phydm/phydm_acs.c | 1306 + .../wireless/rtl8188fu/hal/phydm/phydm_acs.h | 129 + .../rtl8188fu/hal/phydm/phydm_adaptivity.c | 946 + .../rtl8188fu/hal/phydm/phydm_adaptivity.h | 172 + .../rtl8188fu/hal/phydm/phydm_antdect.c | 964 + .../rtl8188fu/hal/phydm/phydm_antdect.h | 98 + .../rtl8188fu/hal/phydm/phydm_antdiv.c | 4762 + .../rtl8188fu/hal/phydm/phydm_antdiv.h | 567 + .../rtl8188fu/hal/phydm/phydm_beamforming.c | 1940 + .../rtl8188fu/hal/phydm/phydm_beamforming.h | 366 + .../rtl8188fu/hal/phydm/phydm_cfotracking.c | 347 + .../rtl8188fu/hal/phydm/phydm_cfotracking.h | 68 + .../rtl8188fu/hal/phydm/phydm_debug.c | 2005 + .../rtl8188fu/hal/phydm/phydm_debug.h | 330 + .../wireless/rtl8188fu/hal/phydm/phydm_dig.c | 2086 + .../wireless/rtl8188fu/hal/phydm/phydm_dig.h | 327 + .../hal/phydm/phydm_dynamicbbpowersaving.c | 219 + .../hal/phydm/phydm_dynamicbbpowersaving.h | 63 + .../hal/phydm/phydm_dynamictxpower.c | 633 + .../hal/phydm/phydm_dynamictxpower.h | 98 + .../hal/phydm/phydm_edcaturbocheck.c | 835 + .../hal/phydm/phydm_edcaturbocheck.h | 100 + .../rtl8188fu/hal/phydm/phydm_features.h | 115 + .../rtl8188fu/hal/phydm/phydm_hwconfig.c | 3149 + .../rtl8188fu/hal/phydm/phydm_hwconfig.h | 499 + .../rtl8188fu/hal/phydm/phydm_interface.c | 1014 + .../rtl8188fu/hal/phydm/phydm_interface.h | 442 + .../rtl8188fu/hal/phydm/phydm_noisemonitor.c | 299 + .../rtl8188fu/hal/phydm/phydm_noisemonitor.h | 49 + .../rtl8188fu/hal/phydm/phydm_pathdiv.c | 2311 + .../rtl8188fu/hal/phydm/phydm_pathdiv.h | 324 + .../hal/phydm/phydm_powertracking_ap.c | 1050 + .../hal/phydm/phydm_powertracking_ap.h | 314 + .../hal/phydm/phydm_powertracking_ce.c | 670 + .../hal/phydm/phydm_powertracking_ce.h | 296 + .../hal/phydm/phydm_powertracking_win.c | 687 + .../hal/phydm/phydm_powertracking_win.h | 265 + .../rtl8188fu/hal/phydm/phydm_pre_define.h | 615 + .../rtl8188fu/hal/phydm/phydm_precomp.h | 320 + .../rtl8188fu/hal/phydm/phydm_rainfo.c | 2574 + .../rtl8188fu/hal/phydm/phydm_rainfo.h | 445 + .../wireless/rtl8188fu/hal/phydm/phydm_reg.h | 208 + .../rtl8188fu/hal/phydm/phydm_regdefine11ac.h | 90 + .../rtl8188fu/hal/phydm/phydm_regdefine11n.h | 199 + .../wireless/rtl8188fu/hal/phydm/phydm_rxhp.c | 1692 + .../wireless/rtl8188fu/hal/phydm/phydm_rxhp.h | 105 + .../rtl8188fu/hal/phydm/phydm_types.h | 259 + .../wireless/rtl8188fu/hal/phydm/rtchnlplan.c | 480 + .../wireless/rtl8188fu/hal/phydm/rtchnlplan.h | 699 + .../hal/phydm/rtl8188f/hal8188freg.h | 863 + .../hal/phydm/rtl8188f/halhwimg8188f_bb.c | 594 + .../hal/phydm/rtl8188f/halhwimg8188f_bb.h | 59 + .../hal/phydm/rtl8188f/halhwimg8188f_fw.c | 2683 + .../hal/phydm/rtl8188f/halhwimg8188f_fw.h | 39 + .../hal/phydm/rtl8188f/halhwimg8188f_mac.c | 288 + .../hal/phydm/rtl8188f/halhwimg8188f_mac.h | 39 + .../hal/phydm/rtl8188f/halhwimg8188f_rf.c | 1143 + .../hal/phydm/rtl8188f/halhwimg8188f_rf.h | 79 + .../hal/phydm/rtl8188f/halphyrf_8188f.c | 3590 + .../hal/phydm/rtl8188f/halphyrf_8188f.h | 135 + .../hal/phydm/rtl8188f/phydm_regconfig8188f.c | 233 + .../hal/phydm/rtl8188f/phydm_regconfig8188f.h | 96 + .../hal/phydm/rtl8188f/phydm_rtl8188f.c | 72 + .../hal/phydm/rtl8188f/phydm_rtl8188f.h | 29 + .../hal/phydm/rtl8188f/version_rtl8188f.h | 11 + .../rtl8188fu/hal/phydm/txbf/halcomtxbf.c | 552 + .../rtl8188fu/hal/phydm/txbf/halcomtxbf.h | 182 + .../rtl8188fu/hal/phydm/txbf/haltxbf8192e.c | 393 + .../rtl8188fu/hal/phydm/txbf/haltxbf8192e.h | 53 + .../rtl8188fu/hal/phydm/txbf/haltxbf8814a.c | 654 + .../rtl8188fu/hal/phydm/txbf/haltxbf8814a.h | 71 + .../rtl8188fu/hal/phydm/txbf/haltxbf8821b.c | 401 + .../rtl8188fu/hal/phydm/txbf/haltxbf8821b.h | 44 + .../rtl8188fu/hal/phydm/txbf/haltxbf8822b.c | 1100 + .../rtl8188fu/hal/phydm/txbf/haltxbf8822b.h | 54 + .../hal/phydm/txbf/haltxbfinterface.c | 1385 + .../hal/phydm/txbf/haltxbfinterface.h | 159 + .../rtl8188fu/hal/phydm/txbf/haltxbfjaguar.c | 528 + .../rtl8188fu/hal/phydm/txbf/haltxbfjaguar.h | 68 + .../rtl8188fu/hal/rtl8188f/Hal8188FPwrSeq.c | 100 + .../rtl8188fu/hal/rtl8188f/rtl8188f_cmd.c | 1299 + .../rtl8188fu/hal/rtl8188f/rtl8188f_dm.c | 619 + .../hal/rtl8188f/rtl8188f_hal_init.c | 7054 + .../rtl8188fu/hal/rtl8188f/rtl8188f_phycfg.c | 1487 + .../rtl8188fu/hal/rtl8188f/rtl8188f_rf6052.c | 292 + .../rtl8188fu/hal/rtl8188f/rtl8188f_rxdesc.c | 69 + .../rtl8188fu/hal/rtl8188f/rtl8188f_sreset.c | 109 + .../hal/rtl8188f/usb/rtl8188fu_led.c | 130 + .../hal/rtl8188f/usb/rtl8188fu_recv.c | 33 + .../hal/rtl8188f/usb/rtl8188fu_xmit.c | 932 + .../rtl8188fu/hal/rtl8188f/usb/usb_halinit.c | 2556 + .../rtl8188fu/hal/rtl8188f/usb/usb_ops.c | 555 + .../rtl8188fu/include/Hal8188FPhyCfg.h | 149 + .../rtl8188fu/include/Hal8188FPhyReg.h | 1171 + .../rtl8188fu/include/Hal8188FPwrSeq.h | 200 + .../wireless/rtl8188fu/include/HalPwrSeqCmd.h | 138 + .../wireless/rtl8188fu/include/HalVerDef.h | 200 + .../net/wireless/rtl8188fu/include/autoconf.h | 346 + .../wireless/rtl8188fu/include/basic_types.h | 385 + .../rtl8188fu/include/byteorder/big_endian.h | 88 + .../rtl8188fu/include/byteorder/generic.h | 213 + .../include/byteorder/little_endian.h | 90 + .../rtl8188fu/include/byteorder/swab.h | 141 + .../rtl8188fu/include/byteorder/swabb.h | 157 + .../net/wireless/rtl8188fu/include/circ_buf.h | 28 + .../wireless/rtl8188fu/include/cmd_osdep.h | 32 + .../wireless/rtl8188fu/include/custom_gpio.h | 33 + .../net/wireless/rtl8188fu/include/drv_conf.h | 201 + .../wireless/rtl8188fu/include/drv_types.h | 1307 + .../wireless/rtl8188fu/include/drv_types_ce.h | 93 + .../rtl8188fu/include/drv_types_gspi.h | 56 + .../rtl8188fu/include/drv_types_linux.h | 25 + .../rtl8188fu/include/drv_types_pci.h | 273 + .../wireless/rtl8188fu/include/drv_types_xp.h | 95 + .../net/wireless/rtl8188fu/include/ethernet.h | 42 + .../net/wireless/rtl8188fu/include/gspi_hal.h | 36 + .../net/wireless/rtl8188fu/include/gspi_ops.h | 185 + .../rtl8188fu/include/gspi_ops_linux.h | 24 + .../wireless/rtl8188fu/include/gspi_osintf.h | 31 + .../net/wireless/rtl8188fu/include/h2clbk.h | 32 + .../wireless/rtl8188fu/include/hal_btcoex.h | 97 + .../net/wireless/rtl8188fu/include/hal_com.h | 562 + .../wireless/rtl8188fu/include/hal_com_h2c.h | 314 + .../wireless/rtl8188fu/include/hal_com_led.h | 397 + .../rtl8188fu/include/hal_com_phycfg.h | 303 + .../wireless/rtl8188fu/include/hal_com_reg.h | 1784 + .../net/wireless/rtl8188fu/include/hal_data.h | 665 + .../net/wireless/rtl8188fu/include/hal_gspi.h | 32 + .../wireless/rtl8188fu/include/hal_ic_cfg.h | 93 + .../net/wireless/rtl8188fu/include/hal_intf.h | 673 + .../net/wireless/rtl8188fu/include/hal_pg.h | 650 + .../net/wireless/rtl8188fu/include/hal_phy.h | 247 + .../wireless/rtl8188fu/include/hal_phy_reg.h | 31 + .../wireless/rtl8188fu/include/ieee80211.h | 1841 + .../rtl8188fu/include/ieee80211_ext.h | 477 + .../net/wireless/rtl8188fu/include/if_ether.h | 113 + .../net/wireless/rtl8188fu/include/ip.h | 141 + .../rtl8188fu/include/linux/wireless.h | 97 + .../wireless/rtl8188fu/include/mlme_osdep.h | 37 + .../rtl8188fu/include/mp_custom_oid.h | 354 + .../net/wireless/rtl8188fu/include/nic_spec.h | 47 + .../wireless/rtl8188fu/include/osdep_intf.h | 170 + .../rtl8188fu/include/osdep_service.h | 637 + .../rtl8188fu/include/osdep_service_bsd.h | 749 + .../rtl8188fu/include/osdep_service_ce.h | 192 + .../rtl8188fu/include/osdep_service_linux.h | 459 + .../rtl8188fu/include/osdep_service_xp.h | 202 + .../net/wireless/rtl8188fu/include/pci_hal.h | 46 + .../net/wireless/rtl8188fu/include/pci_ops.h | 78 + .../wireless/rtl8188fu/include/pci_osintf.h | 32 + .../wireless/rtl8188fu/include/recv_osdep.h | 65 + .../wireless/rtl8188fu/include/rtl8188f_cmd.h | 221 + .../wireless/rtl8188fu/include/rtl8188f_dm.h | 48 + .../wireless/rtl8188fu/include/rtl8188f_hal.h | 264 + .../wireless/rtl8188fu/include/rtl8188f_led.h | 49 + .../rtl8188fu/include/rtl8188f_recv.h | 73 + .../wireless/rtl8188fu/include/rtl8188f_rf.h | 31 + .../rtl8188fu/include/rtl8188f_spec.h | 294 + .../rtl8188fu/include/rtl8188f_sreset.h | 30 + .../rtl8188fu/include/rtl8188f_xmit.h | 336 + .../net/wireless/rtl8188fu/include/rtw_ap.h | 80 + .../rtl8188fu/include/rtw_beamforming.h | 150 + .../wireless/rtl8188fu/include/rtw_br_ext.h | 76 + .../wireless/rtl8188fu/include/rtw_bt_mp.h | 295 + .../wireless/rtl8188fu/include/rtw_btcoex.h | 436 + .../rtl8188fu/include/rtw_byteorder.h | 39 + .../net/wireless/rtl8188fu/include/rtw_cmd.h | 1340 + .../wireless/rtl8188fu/include/rtw_debug.h | 583 + .../wireless/rtl8188fu/include/rtw_eeprom.h | 123 + .../wireless/rtl8188fu/include/rtw_efuse.h | 220 + .../wireless/rtl8188fu/include/rtw_event.h | 138 + .../net/wireless/rtl8188fu/include/rtw_ht.h | 221 + .../net/wireless/rtl8188fu/include/rtw_io.h | 578 + .../wireless/rtl8188fu/include/rtw_ioctl.h | 329 + .../rtl8188fu/include/rtw_ioctl_query.h | 33 + .../rtl8188fu/include/rtw_ioctl_rtl.h | 81 + .../rtl8188fu/include/rtw_ioctl_set.h | 76 + .../net/wireless/rtl8188fu/include/rtw_iol.h | 137 + .../net/wireless/rtl8188fu/include/rtw_mem.h | 42 + .../net/wireless/rtl8188fu/include/rtw_mlme.h | 1080 + .../wireless/rtl8188fu/include/rtw_mlme_ext.h | 1241 + .../net/wireless/rtl8188fu/include/rtw_mp.h | 979 + .../wireless/rtl8188fu/include/rtw_mp_ioctl.h | 591 + .../rtl8188fu/include/rtw_mp_phy_regdef.h | 1100 + .../net/wireless/rtl8188fu/include/rtw_odm.h | 55 + .../net/wireless/rtl8188fu/include/rtw_p2p.h | 179 + .../wireless/rtl8188fu/include/rtw_pwrctrl.h | 461 + .../net/wireless/rtl8188fu/include/rtw_qos.h | 35 + .../net/wireless/rtl8188fu/include/rtw_recv.h | 880 + .../net/wireless/rtl8188fu/include/rtw_rf.h | 271 + .../wireless/rtl8188fu/include/rtw_security.h | 486 + .../wireless/rtl8188fu/include/rtw_sreset.h | 61 + .../net/wireless/rtl8188fu/include/rtw_tdls.h | 175 + .../wireless/rtl8188fu/include/rtw_version.h | 2 + .../net/wireless/rtl8188fu/include/rtw_vht.h | 143 + .../net/wireless/rtl8188fu/include/rtw_wapi.h | 223 + .../rtl8188fu/include/rtw_wifi_regd.h | 27 + .../net/wireless/rtl8188fu/include/rtw_xmit.h | 866 + .../net/wireless/rtl8188fu/include/sta_info.h | 593 + .../net/wireless/rtl8188fu/include/usb_hal.h | 61 + .../net/wireless/rtl8188fu/include/usb_ops.h | 148 + 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src/little/linux/drivers/dma/k230_peridma.c create mode 100755 src/little/linux/drivers/net/wireless/rtl8188fu/Kconfig create mode 100755 src/little/linux/drivers/net/wireless/rtl8188fu/LICENSE create mode 100755 src/little/linux/drivers/net/wireless/rtl8188fu/Makefile create mode 100755 src/little/linux/drivers/net/wireless/rtl8188fu/README.md create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/efuse/rtw_efuse.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_ap.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_beamforming.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_br_ext.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_bt_mp.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_btcoex.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_cmd.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_debug.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_eeprom.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_ieee80211.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_io.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_ioctl_query.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_ioctl_rtl.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_ioctl_set.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_iol.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_mem.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_mlme.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_mlme_ext.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_mp.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_mp_ioctl.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_odm.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_p2p.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_pwrctrl.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_recv.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_rf.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_security.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_sreset.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_sta_mgt.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_tdls.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_vht.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_wapi.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_wapi_sms4.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_wlan_util.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_xmit.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/HalPwrSeqCmd.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8188c2Ant.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8188c2Ant.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8192d2Ant.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8192d2Ant.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8192e1Ant.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8192e1Ant.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8192e2Ant.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8192e2Ant.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8703b1Ant.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8703b1Ant.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8703b2Ant.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8703b2Ant.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723a1Ant.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723a1Ant.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723a2Ant.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723a2Ant.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723b1Ant.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723b1Ant.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723b2Ant.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723b2Ant.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8812a1Ant.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8812a1Ant.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8812a2Ant.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8812a2Ant.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8821a1Ant.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8821a1Ant.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8821a2Ant.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8821a2Ant.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8821aCsr2Ant.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8821aCsr2Ant.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtcOutSrc.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/Mp_Precomp.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/efuse/efuse_mask.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/efuse/rtl8188f/HalEfuseMask8188F_SDIO.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/efuse/rtl8188f/HalEfuseMask8188F_SDIO.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/efuse/rtl8188f/HalEfuseMask8188F_USB.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/efuse/rtl8188f/HalEfuseMask8188F_USB.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_btcoex.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_com.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_com_c2h.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_com_phycfg.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_dm.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_dm.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_hci/hal_usb.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_intf.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_mp.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_phy.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/led/hal_usb_led.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halhwimg.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halphyrf_ap.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halphyrf_ap.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halphyrf_ce.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halphyrf_ce.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halphyrf_win.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halphyrf_win.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/mp_precomp.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_acs.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_acs.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_adaptivity.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_adaptivity.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_antdect.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_antdect.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_antdiv.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_antdiv.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_beamforming.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_beamforming.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_cfotracking.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_cfotracking.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_debug.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_debug.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_dig.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_dig.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_dynamicbbpowersaving.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_dynamicbbpowersaving.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_dynamictxpower.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_dynamictxpower.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_edcaturbocheck.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_edcaturbocheck.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_features.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_hwconfig.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_hwconfig.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_interface.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_interface.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_noisemonitor.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_noisemonitor.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_pathdiv.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_pathdiv.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_powertracking_ap.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_powertracking_ap.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_powertracking_ce.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_powertracking_ce.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_powertracking_win.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_powertracking_win.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_pre_define.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_precomp.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_rainfo.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_rainfo.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_reg.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_regdefine11ac.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_regdefine11n.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_rxhp.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_rxhp.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_types.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtchnlplan.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtchnlplan.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/hal8188freg.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_bb.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_bb.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_fw.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_fw.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_mac.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_mac.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_rf.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_rf.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halphyrf_8188f.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halphyrf_8188f.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/phydm_regconfig8188f.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/phydm_regconfig8188f.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/phydm_rtl8188f.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/phydm_rtl8188f.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/version_rtl8188f.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/halcomtxbf.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/halcomtxbf.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8192e.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8192e.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8814a.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8814a.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8821b.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8821b.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8822b.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8822b.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbfinterface.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbfinterface.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbfjaguar.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbfjaguar.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/Hal8188FPwrSeq.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_cmd.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_dm.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_hal_init.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_phycfg.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_rf6052.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_rxdesc.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_sreset.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/usb/rtl8188fu_led.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/usb/rtl8188fu_recv.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/usb/rtl8188fu_xmit.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/usb/usb_halinit.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/usb/usb_ops.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/Hal8188FPhyCfg.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/Hal8188FPhyReg.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/Hal8188FPwrSeq.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/HalPwrSeqCmd.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/HalVerDef.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/autoconf.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/basic_types.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/byteorder/big_endian.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/byteorder/generic.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/byteorder/little_endian.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/byteorder/swab.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/byteorder/swabb.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/circ_buf.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/cmd_osdep.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/custom_gpio.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_conf.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_types.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_types_ce.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_types_gspi.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_types_linux.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_types_pci.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_types_xp.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/ethernet.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/gspi_hal.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/gspi_ops.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/gspi_ops_linux.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/gspi_osintf.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/h2clbk.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_btcoex.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_com.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_com_h2c.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_com_led.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_com_phycfg.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_com_reg.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_data.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_gspi.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_ic_cfg.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_intf.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_pg.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_phy.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_phy_reg.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/ieee80211.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/ieee80211_ext.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/if_ether.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/ip.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/linux/wireless.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/mlme_osdep.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/mp_custom_oid.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/nic_spec.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/osdep_intf.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/osdep_service.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/osdep_service_bsd.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/osdep_service_ce.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/osdep_service_linux.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/osdep_service_xp.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/pci_hal.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/pci_ops.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/pci_osintf.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/recv_osdep.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_cmd.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_dm.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_hal.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_led.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_recv.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_rf.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_spec.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_sreset.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_xmit.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_ap.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_beamforming.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_br_ext.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_bt_mp.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_btcoex.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_byteorder.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_cmd.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_debug.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_eeprom.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_efuse.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_event.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_ht.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_io.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_ioctl.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_ioctl_query.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_ioctl_rtl.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_ioctl_set.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_iol.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_mem.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_mlme.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_mlme_ext.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_mp.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_mp_ioctl.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_mp_phy_regdef.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_odm.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_p2p.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_pwrctrl.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_qos.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_recv.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_rf.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_security.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_sreset.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_tdls.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_version.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_vht.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_wapi.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_wifi_regd.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_xmit.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/sta_info.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/usb_hal.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/usb_ops.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/usb_ops_linux.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/usb_osintf.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/usb_vendor_req.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/wifi.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/wlan_bssdef.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/include/xmit_osdep.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/custom_gpio_linux.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/ioctl_cfg80211.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/ioctl_cfg80211.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/ioctl_linux.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/ioctl_mp.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/mlme_linux.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/os_intfs.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/recv_linux.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/rtw_proc.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/rtw_proc.h create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/usb_intf.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/usb_ops_linux.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/wifi_regd.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/xmit_linux.c create mode 100644 src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/osdep_service.c create mode 100644 src/little/linux/sound/soc/canaan/Kconfig create mode 100644 src/little/linux/sound/soc/canaan/Makefile create mode 100644 src/little/linux/sound/soc/canaan/audio_muxpin_ctrl.c create mode 100644 src/little/linux/sound/soc/canaan/audio_muxpin_ctrl.h create mode 100644 src/little/linux/sound/soc/canaan/canaan_k230_audio.c create mode 100644 src/little/linux/sound/soc/canaan/canaan_k230_audio.h create mode 100755 src/little/linux/sound/soc/canaan/canaan_k230_inno.c create mode 100644 src/little/linux/sound/soc/canaan/muxpin_reg_ctl.c create mode 100644 src/little/linux/sound/soc/canaan/muxpin_reg_ctl.h create mode 100644 src/little/linux/sound/soc/codecs/inno_k230.c create mode 100644 src/little/linux/sound/soc/codecs/inno_k230_reg.c create mode 100644 src/little/linux/sound/soc/codecs/inno_k230_reg.h create mode 100755 src/little/uboot/arch/riscv/dts/k230_canmv_dongshanpi.dts create mode 100755 src/little/uboot/board/canaan/k230_canmv_01studio/lpddr4_init_32_swap_1066.c create mode 100755 src/little/uboot/board/canaan/k230_canmv_01studio/lpddr4_init_32_swap_2667.c create mode 100755 src/little/uboot/board/canaan/k230_canmv_01studio/lpddr4_init_32_swap_3200.c create mode 100755 src/little/uboot/board/canaan/k230_canmv_dongshanpi/Kconfig create mode 100755 src/little/uboot/board/canaan/k230_canmv_dongshanpi/Makefile create mode 100755 src/little/uboot/board/canaan/k230_canmv_dongshanpi/board.c create mode 100755 src/little/uboot/board/canaan/k230_canmv_dongshanpi/k230pi_ddr_init_2133.c create mode 100755 src/little/uboot/configs/k230_canmv_dongshanpi_burntool_defconfig create mode 100755 src/little/uboot/configs/k230_canmv_dongshanpi_defconfig delete mode 100644 src/reference/ai_poc/bytetrack/vi_vo.h delete mode 100644 src/reference/ai_poc/distraction_reminder/vi_vo.h delete mode 100644 src/reference/ai_poc/dms_system/vi_vo.h delete mode 100644 src/reference/ai_poc/dynamic_gesture/vi_vo.h delete mode 100644 src/reference/ai_poc/eye_gaze/vi_vo.h delete mode 100644 src/reference/ai_poc/face_alignment/vi_vo.h delete mode 100644 src/reference/ai_poc/face_detection/vi_vo.h delete mode 100644 src/reference/ai_poc/face_emotion/vi_vo.h delete mode 100644 src/reference/ai_poc/face_gender/vi_vo.h delete mode 100644 src/reference/ai_poc/face_glasses/vi_vo.h delete mode 100644 src/reference/ai_poc/face_landmark/vi_vo.h delete mode 100644 src/reference/ai_poc/face_mask/vi_vo.h delete mode 100644 src/reference/ai_poc/face_mesh/vi_vo.h delete mode 100644 src/reference/ai_poc/face_parse/vi_vo.h delete mode 100644 src/reference/ai_poc/face_pose/vi_vo.h delete mode 100644 src/reference/ai_poc/face_verification/vi_vo.h delete mode 100644 src/reference/ai_poc/falldown_detect/vi_vo.h delete mode 100644 src/reference/ai_poc/finger_guessing/vi_vo.h delete mode 100644 src/reference/ai_poc/fitness/vi_vo.h delete mode 100644 src/reference/ai_poc/head_detection/vi_vo.h delete mode 100644 src/reference/ai_poc/helmet_detect/vi_vo.h delete mode 100644 src/reference/ai_poc/licence_det/vi_vo.h delete mode 100644 src/reference/ai_poc/licence_det_rec/vi_vo.h delete mode 100644 src/reference/ai_poc/nanotracker/vi_vo.h delete mode 100644 src/reference/ai_poc/object_detect_yolov8n/vi_vo.h delete mode 100644 src/reference/ai_poc/ocr/vi_vo.h delete mode 100644 src/reference/ai_poc/person_attr/vi_vo.h delete mode 100644 src/reference/ai_poc/person_detect/vi_vo.h delete mode 100644 src/reference/ai_poc/person_distance/vi_vo.h rename src/reference/ai_poc/pose_det_rtsp_plug/big/{vi_vo.h => vi_vo_rtsp.h} (87%) delete mode 100644 src/reference/ai_poc/pose_detect/vi_vo.h delete mode 100644 src/reference/ai_poc/pphumanseg/vi_vo.h delete mode 100644 src/reference/ai_poc/puzzle_game/vi_vo.h delete mode 100644 src/reference/ai_poc/segment_yolov8n/vi_vo.h delete mode 100644 src/reference/ai_poc/self_learning/vi_vo.h delete mode 100644 src/reference/ai_poc/smoke_detect/vi_vo.h delete mode 100644 src/reference/ai_poc/space_resize/vi_vo.h delete mode 100644 src/reference/ai_poc/sq_hand_det/vi_vo.h delete mode 100644 src/reference/ai_poc/sq_handkp_class/vi_vo.h delete mode 100644 src/reference/ai_poc/sq_handkp_det/vi_vo.h delete mode 100644 src/reference/ai_poc/sq_handkp_flower/vi_vo.h delete mode 100644 src/reference/ai_poc/sq_handkp_ocr/vi_vo.h delete mode 100644 src/reference/ai_poc/sq_handreco/vi_vo.h delete mode 100644 src/reference/ai_poc/traffic_light_detect/vi_vo.h delete mode 100644 src/reference/ai_poc/vehicle_attr/vi_vo.h rename src/reference/ai_poc/{anomaly_det => vi_vo}/vi_vo.h (79%) delete mode 100644 src/reference/ai_poc/virtual_keyboard/vi_vo.h delete mode 100644 src/reference/ai_poc/yolop_lane_seg/vi_vo.h delete mode 100755 src/reference/fancy_poc/ai_scale/src/ai_scale_ai_code/vi_vo.h delete mode 100755 src/reference/fancy_poc/face_recognition/src/face_recognition/vi_vo.h delete mode 100755 src/reference/fancy_poc/finger_reader/src/finger_reader_client/finger_reader_ai/vi_vo.h mode change 100644 => 100755 src/reference/fancy_poc/meta_hand/resource/address.jpg delete mode 100755 src/reference/fancy_poc/meta_hand/src/meta_hand/vi_vo.h mode change 100644 => 100755 src/reference/fancy_poc/meta_human/resource/pics/address.jpg delete mode 100755 src/reference/fancy_poc/meta_human/src/meta_human/vi_vo.h delete mode 100755 src/reference/fancy_poc/multimodal_chat_robot/src/multimodal_chat_robot_client/aiot_gpt/vi_vo.h rename src/reference/{ai_poc/crosswalk_detect => fancy_poc/vi_vo}/vi_vo.h (79%) mode change 100644 => 100755 diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 5e4a3dda4..31d239294 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -16,7 +16,15 @@ download_dir_release: - .setup_env - .release_download_dir -# sdk zip and image publish with tag +# k230_sdk.tar.gz github zip publish with tag +sdk_github_zip: + rules: + - if: $CI_PIPELINE_SOURCE == "push" && $CI_COMMIT_TAG =~ /^v\d+\.\d+.*$/ + extends: + - .setup_env + - .sync_sdk_github_zip + +# image publish with tag release_image_publish: rules: - if: $CI_PIPELINE_SOURCE == "push" && $CI_COMMIT_TAG =~ /^v\d+\.\d+.*$/ @@ -148,9 +156,9 @@ build-image: script: - cd $CI_PROJECT_DIR - ls -alht - - wget -qc https://ai.b-bug.org/k230/test_resources/ci/release/release_download_dir.sh -O ./release_download_dir.sh + - wget -qc https://ai.b-bug.org/k230/test_resources/ci/release/release_download_dir.sh -O ./release_download_dir.sh || exit 1 - chmod +x ./release_download_dir.sh - - time ./release_download_dir.sh || time ./release_download_dir.sh + - time ./release_download_dir.sh || time ./release_download_dir.sh || exit 1 - echo "all file synced" .sync_release_image: @@ -161,14 +169,14 @@ build-image: script: - cd $CI_PROJECT_DIR - ls -alht - - wget -qc https://ai.b-bug.org/k230/test_resources/ci/release/release_k230_sdk_image.sh -O ./release_k230_sdk_image.sh + - wget -qc https://ai.b-bug.org/k230/test_resources/ci/release/release_k230_sdk_image.sh -O ./release_k230_sdk_image.sh || exit 1 - chmod +x ./release_k230_sdk_image.sh - echo $CI_COMMIT_TAG || exit 1 - echo $CONF || exit 1 - - time ./release_k230_sdk_image.sh $CI_COMMIT_TAG $CONF || time ./release_k230_sdk_image.sh $CI_COMMIT_TAG $CONF + - time ./release_k230_sdk_image.sh $CI_COMMIT_TAG $CONF || time ./release_k230_sdk_image.sh $CI_COMMIT_TAG $CONF || exit 1 - echo "all release file synced" -.sync_github_zip: +.sync_sdk_github_zip: timeout: 60m retry: 2 tags: @@ -176,11 +184,10 @@ build-image: script: - cd $CI_PROJECT_DIR - ls -alht - - wget -qc https://ai.b-bug.org/k230/test_resources/ci/release/release_k230_sdk_github_zip.sh -O ./release_k230_sdk_github_zip.sh + - wget -qc https://ai.b-bug.org/k230/test_resources/ci/release/release_k230_sdk_github_zip.sh -O ./release_k230_sdk_github_zip.sh || exit 1 - chmod +x ./release_k230_sdk_github_zip.sh - echo $CI_COMMIT_TAG || exit 1 - - echo $CONF || exit 1 - - time ./release_k230_sdk_github_zip.sh $CI_COMMIT_TAG || time ./release_k230_sdk_github_zip.sh $CI_COMMIT_TAG + - time ./release_k230_sdk_github_zip.sh $CI_COMMIT_TAG || time ./release_k230_sdk_github_zip.sh $CI_COMMIT_TAG || exit 1 - echo "all release file synced" .generate_version: &generate_version diff --git a/Kconfig.board b/Kconfig.board index 9388c2620..1a8662415 100755 --- a/Kconfig.board +++ b/Kconfig.board @@ -38,6 +38,11 @@ config BOARD_K230_CANMV_01STUDIO bool "K230 CANMV(01STUDIO)" help "CANMV(01STUDIO)"; + +config BOARD_K230_CANMV_DONGSHANPI + bool "K230 CANMV(DONGSHANPI)" + help + "CANMV(DONGSHANPI)"; endchoice config BOARD_NAME diff --git a/Kconfig.wifi b/Kconfig.wifi index e7600d763..9e04c7577 100755 --- a/Kconfig.wifi +++ b/Kconfig.wifi @@ -9,6 +9,9 @@ config AP6256 bool "enable ap6256" default n +config RTL8188FU + bool "enable rtl8188fu" + default n endmenu diff --git a/Makefile b/Makefile index 47906a125..b4e1c46a5 100755 --- a/Makefile +++ b/Makefile @@ -112,8 +112,8 @@ prepare_sourcecode:prepare_toolchain #ai @echo "download nncase sdk" @rm -rf src/big/utils/; rm -rf src/big/ai; - @wget -q --show-progress $(DOWNLOAD_URL)/downloads/kmodel/kmodel_v2.8.1.tgz -O - | tar -xzC src/big/ - @wget -q --show-progress $(DOWNLOAD_URL)/downloads/nncase/nncase_k230_v2.8.1.tgz -O - | tar -xzC src/big/ + @wget -q --show-progress $(DOWNLOAD_URL)/downloads/kmodel/kmodel_v2.8.3.tgz -O - | tar -xzC src/big/ + @wget -q --show-progress $(DOWNLOAD_URL)/downloads/nncase/nncase_k230_v2.8.3.tgz -O - | tar -xzC src/big/ #big utils @echo "download big utils" @@ -220,7 +220,7 @@ mpp-apps:check_src mkdir -p userapps/sample/fastboot_elf; \ make -C userapps/sample || exit $?; \ mkdir -p $(RTSMART_SRC_DIR)/userapps/root/bin/; \ - source $(K230_SDK_ROOT)/.config; [ "$${CONFIG_BOARD_K230D_CANMV}" != "y" ] &&[ "$${CONFIG_BOARD_K230D}" != "y" ] && cp userapps/sample/fastboot_elf/* $(RTSMART_SRC_DIR)/userapps/root/bin/; \ + source $(K230_SDK_ROOT)/.config; [ "$${CONFIG_BOARD_K230D}" != "y" ] && cp userapps/sample/fastboot_elf/* $(RTSMART_SRC_DIR)/userapps/root/bin/; \ cp $(RTSMART_SRC_DIR)/init.sh $(RTSMART_SRC_DIR)/userapps/root/bin/; \ cd -; diff --git a/board/common/dev_firmware/rtl8188fu/rtl8188fufw.bin b/board/common/dev_firmware/rtl8188fu/rtl8188fufw.bin new file mode 100644 index 0000000000000000000000000000000000000000..0d7fbab5ce8aae0c562131b31065130e202d0d81 GIT binary patch literal 21020 zcmc(Hdwf$x+JDX@Y0^@987dSNC?PDaE7FSBU6rEM^$Lwf#Z^m?qJj!3q#~A*Q%XUo z+S4{w)?G!nt_ZGlyIZ{Msx1@+6tDqzy{wl5Bt?WaCu$IElk@vNbD9df@4oN5pWh!Z znlm%c+@G0w=DAIyk7k)HCX>nT7;$00i<#cM7>Sequ~n69$1NuTOeVH@!l~&U>rYAl zbAs)-Re;#mu|~M##eXjH@6+tjT(;&DCa+}jYPR8a)|}2>y_?BROkT_6-!S=ECO^;Q z7nr=B$s3vc3X}iHp1X|6uQK@!_UAL$>$}zhQEW$;X-8$K(X7l3106RoPfo8mk)0s^G36Ib%FV*}9MsJ(I6H^FXXTjib&Bt3 z`Z8v=SnR2(=^0s^r4Gp$nwiCMA}}sfmT8=6qN&(aZ|amLNCi@f=`qs|(`QnNbf5IJ zv`hM$F^fH&=Q{JR@jQ@o)_KJbKewY>k|c)znHkM8ONz~Ax7!UEzJSvgfe{+ztP;jx zO|b!2X4IqakN-xdSePl-z~=wKcWaBBIFGNe)N~Cg@3L=Hw>}nLOJa}h zee9@n)$#5(8T09#O;v4$rouf-%n!@MyY1c~TU)yG_nV7ykL_)-f70`HZI>gQu8(t8 z9nZAe+szig>EWvG{LnY1aC+yu;yi1*Z{_&(UA^pofzd7`3DZu_&an|l#hvSO7F#F#%B0d zo_oCeguOdg%p=}2*OQuhXynN6Q&Z({hYy!O?Zsp))+%ciMI2Px-hHBXb2{5lm79{% zEh>y0c_=mY`;qduqvcN`&XvczEyp91EErbfF?(cE<1xRSJkfJW{OHB~j?Tz$^xmfvJ-?10UEA;Y zs!n@hSFQHKIsJ#9pzj*32j8y|-~EyX_{3cokJsXdQR!nAHAmEq4qbc@n$vAtm+Q+ zc(ZzaT3Y=b^@C6m2dvACskT>|cH-|CAtZn=^e!=j3hf%%Z#<)rFStZk460 zk9`@Ehe)7GS$T!B@~A1aOltJJ*{r*#@js^8NFV_zQr;*k9I)TV6H)FzG}uDieHb=I~6vXVBen#8$+<;r^508 z{3qc?}0ShSLHuKaS|+gDr`K#zBv{46M}tvDr^G5`cH+Or74a5zL6M0 zn$M2!nX1y5KsXAaj&L-V!-Q}QLJ46WLWXcGLNh`KLJPui2(1W*_)f=nq>tiGz=k3m zk1zw_PY`AzoPaP3;aLc?(SM)XCJhJP8<+HB!-xeKB6g0HTYiRAer99&sQ&WNX~>Y4 zJjdsa6~I9GsG;Sftpd1_%^NGKo$m1WiTOoJB?o`*BF>KK(M1WjIo>;LnA_IZVUEs- ze#^V&b(#5w+Yw(>_O{aat`DPW{Lp99qBBrKY22ZqwZdk!BRqTyV z0a&NwQ=f^?AJ4<5H65kjL*yk1pO&7ojZ+mwlqvYU@G3s7XV7OHKF?i-&$OT7^WJ_` z+N?+&Y7tfs?JLq&I(8jw)m7!%880|5jx7(J-w>vKyzta)s(%H!Y!s;(WJNX&N5U6iYQ$bsx8U5AH)!0v`>; zT9^L|$ZuMf+PcyJXQ9#7-$&4Y=wXRl-g(#(Ek%CXKz_REr2I6IHB@A!qZjm>ta>`K za$8r3Hc=jG&qQs9Vx6Vxq5gQ{VLP{c{E}sZ zbz{oQHpS{Opbn)WP0dr;{%e(nS5=F~0~r>Oqy?JNFht#Kvxba#o2q+8AR1k&cCJ(E z7x0$)zPP`5nZ##J1z6RiFS>1sQsy!Ddb1#Hu|D>o>CheZaG6Di)Zt~fh- z1ApV9&}DStD*>tpK+9{<>v&5CeRf8#Q>>5Tbf7qvx@GT=(SQ6H4Gl(vV;mIsu~ieD zI1-Z+N@FKZEBa@vhGEj!7R++wt;j`#lgTz@080km=(xHw zr)%ygs6Z<23mzQjs4IDV<|eamOlMO`VVdj3P~7#b^Fz77H)Q}&ndkbg^HDj^H!}$+ z1fWaK^!W*p=X$Zy1Hg)S=zL3mcqR`Hi&d9v=3Z_+>!{Y;qk;W?Cg$l3*o)5$#b%YQ z>!|Knt~72}yOwuRITQGpcf2G7P$)-Wdej-8>!iA{>`c&*1b0M4cv=aD1O(bU>;lT>9JpCwf zLhWy3py>T-ytnK*F>BPKS@S5hJ?|Pdyr22#FwSMqSM+MIW=-d_t z1k`5$8MSZMXXv7(+$6?ueQZ1cjD-5)^=WaxH1(KYZ(T*(iO!w_cZnZ6DoxdK;XGf( z>u@C~fu)+qrsC#c&yNRnQoZN$;2$fdRW7Jci+-Z&%S;uPN~yJ>T^btwm0(>O(tQ#Z zFHot*E2dY)sZObc+QTs%UiTtSZ6<`s=W`;_yH!131v~FY1$jiIb6B35ZKSA+;>rbL zbOFEWDODQ&N*B;y)CHa^fhcufKq^E{nT|T$fwESgVGIXxwa*w)1`pn*VXpoe%Opnk zAPvbC(w|=iEdC|hBc>WHA#O=#(Oxl9t9N$rqKLOdz6~>1^-{CP3J%pfZ6Nb%f+Bqm zuUmpajG-n9)1rS@^-9yyr84hCw2$&CO(Yrgx0w0b-ueupLK|n}kXy zvF8@pE8FA<_C~x+chqMn4UcL+?#lX%*kZ9Q!;8h0^^4?o%U35vr>V}`WLoDN_eP>O zsuujPm}?+FZBDU7r-iUB_p1G9RplE$R3GqUh8Od$8;rBOnAiRh$vW^ay2sqkGQx|K z`!0m7{K{g#1k@@Gt7#9L^>$_jKezFFzvQSGQK{1o3Moxi4TqhO*<{lyf9cox+JlPq zxavKvS@mY)Hx$2A9y|;%LqCWrq#2rf(4A)CLY%dcs^ zP2(3Q&ua242}E3;gbpxiX+ZAn;+DhKPvomN;t2HOxVjx~3#zDsF%OZ7rgdJI%#O1_$+G;~tm4ehEoGy5ZPHCh4O1|aT2JvI|X z6P?5IRU5DSHs+C8ou_7INw{QRlc)Hs?2p`1yrqQCpNY@nOCl{LUQ6~moG%qEs2)p8 zN%lHxi5v{i^bXglfH#x3*YYK^_`AP%w`*>{=BSjC$ARtvkm|}J{{mN)(zp$xZfBd6 zs=D4Jfk3uV1jx!(#nv~j3C50v;&iq^RU0H+T*<})RcK7yW#V+5X`HT=TIGc<>VDz|Xez2WHkJfwyD-@4Fr0VAtXD>Cq0zw&A70Y;l z6ROAR`a_YdwOD<5lL*m7sofo#>ks%SO(s>}WcB5qJCFml$`i=X+dslBfwR{^HpZ)c zks@}zP8qlqt-kDJGd^AO{WO_S-QR1QEG<^!+y|;~sG3Z^bdbDCso+8-utG>MN?^HA zVX?&@56+-LpjBDX30f+Uae;x1C$-9-xco$FM!23rEBxnMc~^g)3YIdJq!8EhO5jQ0 zXhQZu*GhS`Yb8oipJ^KP_)kTn$CVZB&8pK+6I~vw#`e+0Q2l!LK^Rh$K!d8YJDYvn zK!pPwD5el-RB?L*gt)|tKk|(ooUTKShaUpd=d@CbRk3Qv;}1phyH78>#`QW>G)nyt zOugkHKH;*mUj*;+N%FP9Qi~QWEoI)(z769aicVGI-+7p9DZ56EyZ*w1zbLx~<(ND+ zSh^1!3RjN~eH&V!!e%9^t9gT#WoJUg!Qn>qnUTCqGwm&*;! z>YUl$tDDtWX*1~mRhpy2^{TnUCG_NiCo@$H$4ZYwjI^kP=f%Zd%qy!2{=VD^qlB;ub&m^4(_v815VuD1Q zJ1O=6T8Q0;*~~=?81a=M608k`l)7a-TfJR%XEv+vnL+Y@ubbEd~ieM`sB z9zeI+8L$GAmxbpj%l9|N=0!Xf>pbhc@SM&-df`~#TBBe9M@e`46OsHwDdBnN>X=b@ z-m`k$yzsnzfzw;&6*B+nNR%qow>Rqhlt7WX4kJ<(n7p^JUgscZ{B0Cu$4UYXJ|JGx*?VJO}*J6IOIf6HY& zxOdBC!K*?T$#p)ay*%%g*)4N7-N)Zw@WefJ_wwMiAlZ#g_l6pq?kP?Wx5drH9Jl^D5|4w{^JWGH~?|1w717C$I7tW z5x#juY>|jOU$@O|j`^aOVe3Y(72Sl(Zq)f^NIl{CwAIbAg}xic&*z)RgcoXI@0>;6 z3AAJ8^WXK70+2C>}pem%^ zc5uoL#WKd1r#Z4OQY=pB0l+9hbOs(EijJfKL%Z0kWuMKT`lMIOjI^1taLdc9P28M0 z{*FWh0vXgB)3PrjX&M5qKMtus;U1$jZg<6@n}u);)ntFKJ0C2A(zsKk3%7yBn4ze3 zfgaU;+vm0mqN6mvul;buZ6S^Wic7b&jU;2aV2#^99oo+ws(`pV0BE1CeeGdmSEC!% zJ;rs|t&%dqjGTTEq3aTfZ>iq9qMlntsV^xFb%Plf2C_ex9(96Mh&oC70u^f9r9!1o zVjQ@HPSsO@NgZ~YqrL7iP$?*l?-2*o2zmvjLU9fR|C{QTKT#dxW@wk+!>N%EC=F0- z*z|U58iYTvNAIFW2$`Z9^aG*-P^b4qW3lS+@^hjWfQ87IRe$}q|ALkV=r70DaO-}%l1{NX}`a4gi)9hhWH=vBF2hT7f z&d~W3FSOr2Pe_BsRb6^KuOdc5=dea>8OH2CIo1eEC4Nl#@%^L;_U2Z>Vc?Fb6kP z)KJbwycVA(50A7-7T2de8=S!Y}0gK|3s?AV$~3(2C5QTlIXo$pqDa2aR_-e=sNHAwwq=;PuaU|^$dmXInWAkeX1?eN5wm0}O=mz&Yvm8#0GVycEP|HWsV;xy zjjEadzGjBK{{D6;*?MU@RjI!pT$-rseb%Vkc51PcdQKmx?|oKuY4Miu-BDulZsm&; zvP+Eae_8qDsaZzwCEvXso9PT&{Bw$UAFS}MRJBBy@6{^kzNmHYJStnO%2E_AZ)Rc+B4Rixq4LjXbD!J znk8?-;sm{&PKpHf{QXMJn-I7j2+l1p85>-JzIgCw^3ae{^A@OWWueZOP7Qk9V=(3` zOE_s3MJ$J^88-spa`ZqRcPw zwSaH3>VRyq8iRN+IQPnug26%9Dhok-PwJixc5ev|rPkA;4|wuJ5cK5H{JpJ8O^4dX za`_{_3qB6@FQH4Xlw>n_ys~uJPAh;SkZ=oq4o&_Eje;tq(EgT(h=iRI>1FBBPf$C$ zi|?)%I4v)ca7BbmG>5+qWG0fNK}yrGh=$YGeX$@vv{}won!pD&<*0FFs{A+Cg_lo^ zUWg;5yEYRTS{bPR3O_&j%vPHHj8()52|8BXK@l9UDI%halLiCGl`4D*4lzjHp;$Q- zw5n$T-*&He9^c+kUM?9J%r>TEMhPI@%VOo>a?dq1^SlGB3@F&C7Qr@Hvj-w3i7&#q zLCGj5a|mo4h|Adm937biidfATngeR;-RdL^YY+7E<`OZzSnR_(R0q667OQdOLB4+zf~?Z@}Te5xN=FqPM>#2TKG! z+_gB(O{=g41}_sSqV>?3InpNCRNRXhIHgUJ>P*Bkk~U70-jY$!>AKD^ts)^q%WRlG zO%UWI{`l_;whv}gZM~q=FBKTKAz2KS0Bod3$b>oAaiHB$a0K3lgb%+JPHOC(!VtEF zY+7W#1Y>rR{gS}cP~E8p%-y06#P@iIRSE2-LXSTqU~j8>mz6*Kxu72*yj zaf_0o1v0nO&?!`F71vcR;7@+tF4+{zhdy1tMhR2{YgZSzQAaB~vWG9#sGnJ#F?h>@Br_5{dxXRlX6JTOG~<#!rgdG&N4zJZu~2 zTBw0uGASq|E-QgmloGBERs7Lm0$EgpRO?%Aqz#!stm?01S%r=qmeps9DT)4+z+JGa z)ir~;B!g|lI}S`3c#=HzbgEZW7_CPU@URVkQYSefoDg~AkN=ZR7Tf3F8f7W(U#zk& zT3zcLxa3O*rvQ?KvoRS{8JdrfJ-vX2PDXtFUuF6-l znn~g!Mu9ZTEVzlk`0J1!+&OFU08!;H;@16<**cjeB)f8g_=T2 zPipjjUJ;L0$##mg^VcSU)0Iac$0l-QtAIxziLM1ZFS-HyIt30(alaW}94T<Z-%%?nhfaO8=!JXOczOIWtlNyH=)f^Q0!*F8eA9z)~o_+ zDO$k{+B~SrTE?R)+^e7_?+ss zg*S&6K5YKopBveP;p>Hp3ddQ8XlJ9HK~TMOBgwrQqELQ}AO^acM(aW8BVDNi~rnv=nx}O^zM` z^X-8AxA>BFDN}$`qjTLhFP5|d^A>|j=0jHoMfcoystOQyn-J~s?4$hFazO# zmx&(P#J3Ee0dN+|%K0kf1V^a9=NzXg`?`>pezYz3Tc2rS_H__j+*3e*g|?%Q49-55 zjH_-<^O*-zuxa~-{FusuvK2=Kbsz_SiyM{ffK6OYz^H7JdZ8=#nI@e;0ayt;%%mAm z8oz@XEvdC5cUjhDhGGEKAtj$ul)S4C6YS@;LW_W^+1p~HjVkaW7v{JOI5Z>)YUB6l z-v8t>#_y3Mo@t7N#|w%yTwO{s-qFhw1s5reKVY)D5+_&oA0T$IfDro{zt7(0WaPlf zfAxFHapuB6fab2^w|=LvC$VP*Ngd#1iDe+&>)0-(@c>#nKt_VB;t7$0AY9S+i{}ws zY1~hT&v}qA)JRyRg1Ce~NIJ?NEFWzbJk&b^0i8Z4iUe^slLd~%MvMFpMgCqNd>m~enF$JNP5!K=%&t(I4|+=9M4E6^FnrN+zG=l)HpeaA#4VtN3nE3 zEt;!Jb1f)5lT0jP67Pyh*vO#rop*|Bu_miVk;zm9dx^5-K^Op`^O$pdj* z3T5_UE1?@68lnwq78WbfY?<9}DkgO!`h(806pn8zwg4mapVB}qm`N7x$!L#n|BCM_ z=M}%Lzp^X~di@$WiQ1uW(v2AUsK2j%6nG|ICdQ6>g>gUCE6;<5cef%vr?$n(CF#-0 z^}7{Q75rA>{wiv><7Z`0;FQ)p3zlI>r3s7Ku;eYC@!?MlPjTK#aorp9}|0NA`aVjuMTe@KW`1J~IvgZo8cXz#Wd)r3Y{Y3M*ze|&(a z&JbnNNp4aawhl1#eU8=>yduIcHS_llLrdH`y8dzu@XrGSOl2uwv>wGrF_~aai$hYX zpczSod1yO#Qne9O&2+Iq+Qo>o z`wsB(S9$r2Xqb1Thhl}Xsj(}{uasXY^cN%hm8pIg1y}fQqTovZ&Cq#b*YsiG_^#(5 zs(F6ViRr6>M`><>VTGB3-GgFS+U|>M@+g2?_26y$M4|IUAyeTtMS54wKlm0EN@xyD z_YY#aHA}W&Jz9_A11Dvyxl;3f4($^7yC^k5nj~xejPF@Zz81GFuS^%d#t0;&FmZ@f zcqdiU<@;QdGb4z!nXSGLNt0Tr`OhJBJFe1pD~j}?aq?rVf#cW82a#yTZfb^f0TH{| zXKVcoSs$Tiv^;n6fW9*Y(g*I|6zD*YlZcM{m;@J$tWR}Xl$y`QIB7PPfyJ{pFi^E;KMp@hYzbiyKJ6Ff@+xkuVSALX7Wa!rL> z1p3s!IQ%)wOl;{ozI&nHE@l^rQ{-}p@hO!T_$MGrcd9U+q~;&8LWq`A5cesX(Q;9i(K4>B&x;i+QhxXvtvP%xe%Il5J^IND z7i*64n^MYemdf4c@>}j!q>IBhA@gSZ-1yxBbV(uH4>-`^f{5k4K=XAFm4wZ?2NGIt z51bw7k!lEB)a#fx_Nd7*RQ>`}h1cUx>9l}9{3#e2RC-tS=90DD%bQj3Pyjpc5&SHg z_q&&+ z;;~M_f=CgR97X0t4+zZBf(6F=8u0|7Oau*eOrGyTfeLRUhipQ&YATfjo6*_o4`I|(%7ot7PFL;2Kazl z`Tc8UOYrvv73A6523!P2&|c;*)?hbB-0iOS!C;dDK~5!R*7YHlO|-E^)rH5`=!n~o zLidBpqFW0AkRNFhWR4zYX7xS@|u{$sq;_sKtaZ%nEiO=w<~+d}9q+ z2mSmvvJUPP6$ssmjrs;clB65tzP6 zo?PEiI0?%z5jHsZSbP5=JMmF!J^;M{1SfXjvaol&xgl zbkyGqd;Il;Pk04fPc{anVGk(t-3UKG2w|zA3!w*LP!o#{>ENhV?{&tD8BE?nNV334 zZRW2%R__JxpRc66jM+gS0}%nQubWjkwBZ(_qwzkrAhsxOkN4GtE}KvcZ(jC1FUA*q zWnkWS8S~Clo%J&pc&A4^HwaQ&sI?yEE%!pB$zQvWFtQ6yZgM^e53sPI=kfJ3Av2Cq ztc&oj1&&c=!n&V{jV7w$yOy^+Qhyr_TG-p`Zxe_p5+oJ_Y*r1a2bVH3I#nI*4yZq; zD$;E@eA1;p*hQt=RL`09)wJ_zQOprJ6U&h{AW^Zhs~zMGO>z`u9Ky4(9`C`@2q5_C zl@Ag+_TX(AXg9s28q-WVb6cy4oUD1IRf3Z>f2s#h=g4!q;TXAvz&dmqvF5NcIrwg< zsux5w9Lh>5Bs1eWC;#gF?rh@CW0e)GdAG#*27w~10d{V zEF+d(Y>DBb4jkL5Fx24igb~%q0sKtE1a9Wd12%BH{3Ba7q`hDs5dXf4B?MlKCmzPc zlkbaQ=@p1bK0~5P8WhpJ;?acR_D>rR^1TMvy$+m>*XGK<>dEh(N<)T;?<}HM!ruZ; z39!I}`kaYFg#ClAk+u-Wa`zK*4u5S>h_#atiyc0f)CMS(f5^sP`zn|xr-&s+MJTZb zE^3%-kPbqLVV$8l{s4Y!&T!`!L5CgqYZ)k z!zbzwcvGhCd%75BY&Sf&Yd%#wpE*a)?(BK`XMg~Jmn_&c>xgTjT-})#4?(c0`8>L4 zZJ{ONB!=&EfX5l&-2>op26!0`pYdFj>~{;iQpm%CuN-#AW%J=8hCyTJ?tA8FseIfA z4x;8G>I_a1U*N9@(8_>1DGhC4EBrQk8#1uBtbF|g9(bdGoLD082%&|BB7l|M3YQ6@ zEqe!O3sl^Kw%~D_pe=vH4J6hA4%N>KUh-*NRzJ~{73&3m4&8mI?+4=9S58v`QzDuN zSy)Cd-E-lsE$A$h0JueP3ManBe{);*^|&{10J-NbL=U9kNb-3P?ro9rhZ?rFh}w?x z{zrA$t(tEKE{zA?^xbNZcBK9r(oPKyYTv9Kw#xOmYkSa!4rfWx08Fl^5C8WrQhllC z8OOycc-kZy|2IdJufJ6sF*}{nbQycOL-nS_aXI0LCe2Sz_JVj2&z>MELTsGLH-(sV zXqc=wt3`PRpEfmVuOfP&G@Y)&act`Sc$$56j%Q&G;=}1P)oFo-x>lYdqRis@NIqW_J=gW5e6|3ZEw1-!QEHpi6=J&;C|Y%Asw!*mE+{2t~$BfRmawW(h08BRaZIIue)9b8|H8c zR@dNbk?p8-h!$L1sVwq|1uiNCQ#zil>&E+$N~aMHWJ5!v1fGIOYkI`A#H6e~1FE44 z{gLGqAB{L-Q`J|0-1k)tfkT) zJ=sSd?Dn2@`q5_-vIT-9dcNLJwnF<)e-LG0)B@&!^S>7b9Q>(Y;jM_B?!PpK=i^8U zdM*X%f`E_>VM39f#*3JuA(}r8+6X+RA{A_h-_!>GeDDj>S_s!5TG=Fd_|p=i#IIF% zzFwN;u|(SP%qRsxLy_+I6!`0~O4gDB&nWFiOw=o!IKAuAVR>5z@3FQZ3dTS-b-sQGrI9muGzNS^w=Z=pd10V5$@ z8c;dBDYOl+ki-qyoY0U?w;=oqfg2B_X*XqH%kVNc-3~hUbO{b(qyS$9D<#wl@U@Qf zd9NFa@Z?+vy)d&Rxr{Do-HrE+^OSZOAbyfdC%85U##u?1PNmTd zF-7Q9NSjiMA3fD0w#Y>r05{oQay@F;1DiPcITT(?7eAnI7~owyjO!n7F&fQs3Z)w@ zYN9jpEKD6(fSX7$JF$4U@9&d%R}uEVQu7Zw1@Qsf+&@&j0BKCY3y?;<^fTcv8yw=n zMjl*WJeqffvAJ&sPg#hw13o3-hRj4UoaoO7N}Wrkpl?D87y&f_FCnTEdNx_>mLF^F zMjPOFR1EAEg!_4LYap#KE#f=|=0pq0X`q821L#Ww8}bpxswR1oFOVQ^$4b+LX3v6y z2j*cCP3Q|KFw=_7LL>DBbm*F~;<&iyPImBZy9*~NHDA)y8zHe%bltT}kLhDQNBruvdLJ8mB&&@6hk?CjRcNo-Xgg5-Y)NoL2&Ay4WF@@%zm}lXfb@JaP z8TbP(#MsbVU!{q7xxhC>E$~tdA~yUZ`LFRj?O3nY4>E^WF)`SmvxHrN9@zsy-$6K@ zGfVhO(d!d;RENO|u8Gr0CW0F?ys1oA_UVzU>JAO0J|tTVqg>(-WE5RES(m zvEy&X#9f4|e#{ZC(Ghcr9gG2?kw7K#OeyrFN+&HJwnwLf9zWnuG{JMEWj33$mEQ7< cY6RIaS*RQcg$@3p*MKzR#U|u0)7-QFANUTBa{vGU literal 0 HcmV?d00001 diff --git a/board/common/gen_image_script/gen_image_comm_func.sh b/board/common/gen_image_script/gen_image_comm_func.sh index 13979c035..41c04c4cb 100755 --- a/board/common/gen_image_script/gen_image_comm_func.sh +++ b/board/common/gen_image_script/gen_image_comm_func.sh @@ -136,6 +136,11 @@ add_dev_firmware() if [ "${CONFIG_AP6256}" = "y" ] ; then cp -f ${K230_SDK_ROOT}/board/common/dev_firmware/ap6256/* ${BUILD_DIR}/images/little-core/rootfs/${dev_firmware}/ fi + + if [ "${CONFIG_RTL8188FU}" = "y" ] ; then + mkdir -p ${BUILD_DIR}/images/little-core/rootfs/lib/firmware/rtlwifi/ + cp -f ${K230_SDK_ROOT}/board/common/dev_firmware/rtl8188fu/* ${BUILD_DIR}/images/little-core/rootfs/lib/firmware/rtlwifi/ + fi } #add_firmHead xxx.bin "-n" diff --git a/configs/k230_canmv_01studio_defconfig b/configs/k230_canmv_01studio_defconfig index 843e146d0..9abcc6038 100644 --- a/configs/k230_canmv_01studio_defconfig +++ b/configs/k230_canmv_01studio_defconfig @@ -33,13 +33,13 @@ CONFIG_TOOLCHAIN_PATH_LINUX="/opt/toolchain/Xuantie-900-gcc-linux-5.10.4-glibc-x # # Memory configuration # -CONFIG_MEM_TOTAL_SIZE=0x20000000 +CONFIG_MEM_TOTAL_SIZE=0x40000000 CONFIG_MEM_IPCM_BASE=0x00100000 CONFIG_MEM_IPCM_SIZE=0x00100000 CONFIG_MEM_RTT_SYS_BASE=0x00200000 CONFIG_MEM_RTT_SYS_SIZE=0x07E00000 CONFIG_MEM_MMZ_BASE=0x10000000 -CONFIG_MEM_MMZ_SIZE=0x0FC00000 +CONFIG_MEM_MMZ_SIZE=0x2FC00000 CONFIG_MEM_LINUX_SYS_BASE=0x08000000 CONFIG_MEM_LINUX_SYS_SIZE=0x08000000 CONFIG_MEM_BOUNDARY_RESERVED_SIZE=0x00001000 diff --git a/configs/temp_config2 b/configs/k230_canmv_dongshanpi_defconfig similarity index 65% rename from configs/temp_config2 rename to configs/k230_canmv_dongshanpi_defconfig index 5e6bbfb56..1f9b10b22 100644 --- a/configs/temp_config2 +++ b/configs/k230_canmv_dongshanpi_defconfig @@ -6,18 +6,23 @@ # # board configuration # -CONFIG_BOARD_K230_EVB=y +# CONFIG_BOARD_K230_EVB is not set # CONFIG_BOARD_K230_FPGA is not set # CONFIG_BOARD_K230D is not set # CONFIG_BOARD_K230_CANMV is not set +# CONFIG_BOARD_K230_CANMV_V2 is not set +# CONFIG_BOARD_K230D_CANMV is not set +# CONFIG_BOARD_K230_CANMV_01STUDIO is not set +CONFIG_BOARD_K230_CANMV_DONGSHANPI=y CONFIG_BOARD_NAME="k230_evb" # CONFIG_QUICK_BOOT is not set -CONFIG_GEN_SECURITY_IMG=y -CONFIG_UBOOT_DEFCONFIG="k230_evb" -CONFIG_LINUX_DEFCONFIG="k230_evb" -CONFIG_LINUX_DTB="k230_evb" +# CONFIG_GEN_SECURITY_IMG is not set +CONFIG_UBOOT_DEFCONFIG="k230_canmv_dongshanpi" +CONFIG_LINUX_DEFCONFIG="k230_canmv_dongshanpi" +CONFIG_LINUX_DTB="k230_canmv_dongshanpi" # CONFIG_REMOTE_TEST_PLATFORM is not set CONFIG_GEN_IMG_SCRIPT="board/common/gen_image_script/gen_image.sh" +CONFIG_RTT_CONSOLE_ID=3 # # toolchain configurations @@ -31,29 +36,31 @@ CONFIG_TOOLCHAIN_PATH_LINUX="/opt/toolchain/Xuantie-900-gcc-linux-5.10.4-glibc-x # Memory configuration # CONFIG_MEM_TOTAL_SIZE=0x20000000 -CONFIG_MEM_PARAM_BASE=0x00000000 -CONFIG_MEM_PARAM_SIZE=0x00100000 CONFIG_MEM_IPCM_BASE=0x00100000 CONFIG_MEM_IPCM_SIZE=0x00100000 CONFIG_MEM_RTT_SYS_BASE=0x00200000 CONFIG_MEM_RTT_SYS_SIZE=0x07E00000 -CONFIG_MEM_AI_MODEL_BASE=0x1FC00000 -CONFIG_MEM_AI_MODEL_SIZE=0x00400000 -CONFIG_MEM_LINUX_SYS_BASE=0x08000000 -CONFIG_MEM_LINUX_SYS_SIZE=0x08000000 CONFIG_MEM_MMZ_BASE=0x10000000 CONFIG_MEM_MMZ_SIZE=0x0FC00000 +CONFIG_MEM_LINUX_SYS_BASE=0x08000000 +CONFIG_MEM_LINUX_SYS_SIZE=0x08000000 CONFIG_MEM_BOUNDARY_RESERVED_SIZE=0x00001000 # # storage configurations # -CONFIG_SPI_NOR=y -CONFIG_SPI_NOR_CFG="" +# CONFIG_SPI_NOR is not set # CONFIG_SPI_NAND is not set -CONFIG_SPI_NAND_CFG="" CONFIG_SDCAED=y -CONFIG_EMMC=y -CONFIG_SPI_EMMC_CFG="" + +# +# wifi configurations +# +# CONFIG_AP6212A is not set +# CONFIG_AP6256 is not set +CONFIG_RTL8188FU=y +CONFIG_SUPPORT_RTSMART=y CONFIG_SUPPORT_LINUX=y -CONFIG_SUPPORT_RTSMART=y \ No newline at end of file +CONFIG_LINUX_RUN_CORE_ID=0 +# CONFIG_BUILD_DEBUG_VER is not set +CONFIG_BUILD_RELEASE_VER=y diff --git a/configs/k230_canmv_only_rtt_defconfig b/configs/k230_canmv_only_rtt_defconfig index 8962eb2f2..9fc607e5d 100755 --- a/configs/k230_canmv_only_rtt_defconfig +++ b/configs/k230_canmv_only_rtt_defconfig @@ -11,7 +11,7 @@ # CONFIG_BOARD_K230D is not set CONFIG_BOARD_K230_CANMV=y CONFIG_BOARD_NAME="k230_evb" -# CONFIG_QUICK_BOOT is not set +CONFIG_QUICK_BOOT=y # CONFIG_GEN_SECURITY_IMG is not set CONFIG_UBOOT_DEFCONFIG="k230_canmv" CONFIG_LINUX_DEFCONFIG="k230_evb" @@ -35,7 +35,7 @@ CONFIG_TOOLCHAIN_PATH_LINUX="/opt/toolchain/Xuantie-900-gcc-linux-5.10.4-glibc-x CONFIG_MEM_TOTAL_SIZE=0x20000000 CONFIG_MEM_IPCM_BASE=0x0 CONFIG_MEM_IPCM_SIZE=0x0 -CONFIG_MEM_RTT_SYS_BASE=0x0 +CONFIG_MEM_RTT_SYS_BASE=0x00000000 CONFIG_MEM_RTT_SYS_SIZE=0x10000000 CONFIG_MEM_MMZ_BASE=0x10000000 CONFIG_MEM_MMZ_SIZE=0x10000000 diff --git a/configs/k230_canmv_v2_only_rtt_defconfig b/configs/k230_canmv_v2_only_rtt_defconfig index f33bd0eab..b43856650 100755 --- a/configs/k230_canmv_v2_only_rtt_defconfig +++ b/configs/k230_canmv_v2_only_rtt_defconfig @@ -37,7 +37,7 @@ CONFIG_TOOLCHAIN_PATH_LINUX="/opt/toolchain/Xuantie-900-gcc-linux-5.10.4-glibc-x CONFIG_MEM_TOTAL_SIZE=0x20000000 CONFIG_MEM_IPCM_BASE=0x0 CONFIG_MEM_IPCM_SIZE=0x0 -CONFIG_MEM_RTT_SYS_BASE=0x0 +CONFIG_MEM_RTT_SYS_BASE=0x00000000 CONFIG_MEM_RTT_SYS_SIZE=0x10000000 CONFIG_MEM_MMZ_BASE=0x10000000 CONFIG_MEM_MMZ_SIZE=0x10000000 diff --git a/configs/k230d_canmv_only_rtt_defconfig b/configs/k230d_canmv_only_rtt_defconfig index d569c0f73..55f236856 100755 --- a/configs/k230d_canmv_only_rtt_defconfig +++ b/configs/k230d_canmv_only_rtt_defconfig @@ -12,7 +12,7 @@ # CONFIG_BOARD_K230_CANMV is not set CONFIG_BOARD_K230D_CANMV=y CONFIG_BOARD_NAME="k230d_canmv" -# CONFIG_QUICK_BOOT is not set +CONFIG_QUICK_BOOT=y # CONFIG_GEN_SECURITY_IMG is not set CONFIG_UBOOT_DEFCONFIG="k230d_canmv" CONFIG_LINUX_DEFCONFIG="k230d_canmv" @@ -35,8 +35,8 @@ CONFIG_TOOLCHAIN_PATH_LINUX="/opt/toolchain/Xuantie-900-gcc-linux-5.10.4-glibc-x CONFIG_MEM_TOTAL_SIZE=0x8000000 CONFIG_MEM_IPCM_BASE=0x0 CONFIG_MEM_IPCM_SIZE=0x0 -CONFIG_MEM_RTT_SYS_BASE=0x0 -CONFIG_MEM_RTT_SYS_SIZE=0x3000000 +CONFIG_MEM_RTT_SYS_BASE=0x0000000 +CONFIG_MEM_RTT_SYS_SIZE=0x03000000 CONFIG_MEM_MMZ_BASE=0x3000000 CONFIG_MEM_MMZ_SIZE=0x5000000 CONFIG_MEM_BOUNDARY_RESERVED_SIZE=0x8 diff --git a/repo.mak b/repo.mak index b83925b5e..f4accccde 100755 --- a/repo.mak +++ b/repo.mak @@ -1,11 +1,11 @@ -RT-SMART_VERSION = "66ebe23e44fbbdf1681b18dfb187af1353d10adb" -MPP_VERSION = "cad767e0d43e2979bb460f7e9a63a02e75ce4b79" +RT-SMART_VERSION = "76c06358b3f90c4e4f873e7c891991c69a086a0b" +MPP_VERSION = "8d8ef53825b35799914006b54a941a0dd53389ea" UNITTEST_VERSION = "a07caf5e19a6a215605271cfeedce18111790e9d" OPENSBI_VERSION = "1f89326f7dc48d701dbed79f828b80fa28e5b34c" -BUILDROOT-EXT_VERSION = "1c97b30a3366f836f83eba20b8db76713055bfd3" -LINUX_VERSION = "e3fb062a4f21db9012b4ac05208d1c7fd15a547f" -CDK_VERSION = "786d3c8ca5bdbcd1ad5a623635f0139e94ff1089" -UBOOT_VERSION = "847dc0b16a8229a55b5c04449f16a48464ef0a5b" +BUILDROOT-EXT_VERSION = "dbfccc3652d0dd60b77d5f9f2d89b7ff4a919536" +LINUX_VERSION = "ed653c78ed111605198726c57060cafdf3105923" +CDK_VERSION = "4977a0619fd9512dc3403173d488ee4eaee967b6" +UBOOT_VERSION = "82cb727a100dd2f85cfed3d5329db53696f0b256" RT-SMART_SRC_PATH = src/big/rt-smart MPP_SRC_PATH = src/big/mpp diff --git a/src/big/mpp/include/comm/k_board_config_comm.h b/src/big/mpp/include/comm/k_board_config_comm.h index fed146647..a0ef8f3fb 100755 --- a/src/big/mpp/include/comm/k_board_config_comm.h +++ b/src/big/mpp/include/comm/k_board_config_comm.h @@ -188,6 +188,33 @@ extern "C" { #define LT9611_SLAVE_ADDR 0x3b #define LT9611_I2C_BUS "i2c3"//"i2c4" +#elif defined(CONFIG_BOARD_K230_CANMV_DONGSHANPI) +// usip evb gpio config +// display gpio +#define DISPLAY_LCD_RST_GPIO 22 +#define DISPLAY_LCD_BACKLIGHT_EN 25 + +// imx335 gpio config +#define VICAP_IMX335_RST_GPIO 46 +#define VICAP_IMX335_MASTER_GPIO 28 +//OV9286 gpio cinfig +#define VICAP_OV9286_RST_GPIO 20 + +#define OV5647_IIC "i2c0" +#define OV5647_CAM_PIN 61 + +#define OV5647_CSI1_IIC "i2c1" +#define OV5647_CSI2_IIC "i2c4" + +#define OV5647_CAM_PIN_CSI2 (21) +#define OV5647_CAM_PIN_CSI1 (60) + +#define OV9732_RST_PIN (28) + +#define LT9611_RESET_GPIO 24 //42 +#define LT9611_SLAVE_ADDR 0x3b +#define LT9611_I2C_BUS "i2c3"//"i2c4" + #else #define DISPLAY_LCD_RST_GPIO 9 diff --git a/src/big/mpp/include/comm/k_connector_comm.h b/src/big/mpp/include/comm/k_connector_comm.h index 16d6fa14c..5c02f88d6 100755 --- a/src/big/mpp/include/comm/k_connector_comm.h +++ b/src/big/mpp/include/comm/k_connector_comm.h @@ -54,6 +54,7 @@ typedef enum { LT9611_MIPI_4LAN_1920X1080_30FPS = 1, ST7701_V1_MIPI_2LAN_480X800_30FPS = 2, ST7701_V1_MIPI_2LAN_480X854_30FPS = 3, + ILI9806_MIPI_2LAN_480X800_30FPS = 4, LT9611_MIPI_ADAPT_RESOLUTION = 100, LT9611_MIPI_4LAN_1920X1080_60FPS, LT9611_MIPI_4LAN_1920X1080_50FPS, diff --git a/src/big/mpp/include/comm/k_dewarp_comm.h b/src/big/mpp/include/comm/k_dewarp_comm.h index cd38b84e9..23c3d1a99 100644 --- a/src/big/mpp/include/comm/k_dewarp_comm.h +++ b/src/big/mpp/include/comm/k_dewarp_comm.h @@ -38,7 +38,6 @@ #include "k_vb_comm.h" #include "k_video_comm.h" #include -#include #include #ifdef __cplusplus diff --git a/src/big/mpp/include/comm/k_isp_comm.h b/src/big/mpp/include/comm/k_isp_comm.h index 479f79b2b..6a792ff60 100755 --- a/src/big/mpp/include/comm/k_isp_comm.h +++ b/src/big/mpp/include/comm/k_isp_comm.h @@ -489,6 +489,7 @@ typedef struct { k_u32 buffer_size; k_u64 *vb_phys_addr; void **vb_virt_addr; + // k_vicap_mirror mirror; } k_isp_dev_attr; typedef struct { diff --git a/src/big/mpp/include/comm/k_sensor_comm.h b/src/big/mpp/include/comm/k_sensor_comm.h index bdeee065e..8c2eba68a 100755 --- a/src/big/mpp/include/comm/k_sensor_comm.h +++ b/src/big/mpp/include/comm/k_sensor_comm.h @@ -577,6 +577,11 @@ typedef struct { float exp_time[4]; } k_sensor_exposure_param; +typedef struct { + k_u8 otp_type; + k_u8 otp_date[20]; +} k_sensor_otp_date; + #ifdef __cplusplus } #endif /* __cplusplus */ diff --git a/src/big/mpp/include/comm/k_vicap_comm.h b/src/big/mpp/include/comm/k_vicap_comm.h index 6493ea90e..0bd13de40 100755 --- a/src/big/mpp/include/comm/k_vicap_comm.h +++ b/src/big/mpp/include/comm/k_vicap_comm.h @@ -405,6 +405,23 @@ typedef struct { k_u8 fps; // 0: original FPS } k_vicap_chn_attr; + +typedef enum { + VICAP_MIRROR_NONE = 0, + VICAP_MIRROR_HOR = 1, + VICAP_MIRROR_VER = 2, + VICAP_MIRROR_BOTH = 3, +} k_vicap_mirror; + + +typedef struct { + k_vicap_sensor_type sensor_type; + k_vicap_mirror mirror; +}k_vicap_mirror_mode; + + + + /** * @brief Defines the attributes of a VICAP device * @@ -421,6 +438,7 @@ typedef struct { k_bool dev_enable; k_u32 buffer_num; k_u32 buffer_size; + k_vicap_mirror mirror; } k_vicap_dev_attr; /** @@ -616,6 +634,9 @@ typedef struct #define K_ERR_VICAP_NOTREADY K_DEF_ERR(K_ID_VICAP, K_ERR_LEVEL_ERROR, K_ERR_NOTREADY) #define K_ERR_VICAP_BADADDR K_DEF_ERR(K_ID_VICAP, K_ERR_LEVEL_ERROR, K_ERR_BADADDR) #define K_ERR_VICAP_BUSY K_DEF_ERR(K_ID_VICAP, K_ERR_LEVEL_ERROR, K_ERR_BUSY) +#define K_ERR_VICAP_OPT_ALREADY_WRITE K_DEF_ERR(K_ID_VICAP, K_ERR_LEVEL_ERROR, K_ERR_OPT_ALREADY_WRITE) + + /** @} */ /** \n", error); cmd->err = -RT_ERROR; } - if ((cmd->flags & RESP_MASK) == RESP_R2) - { + if ((cmd->flags & RESP_MASK) == RESP_R2) { cmd->resp[3] = sdhci_command.response[0]; cmd->resp[2] = sdhci_command.response[1]; cmd->resp[1] = sdhci_command.response[2]; cmd->resp[0] = sdhci_command.response[3]; LOG_D(" resp 0x%08X 0x%08X 0x%08X 0x%08X\n", - cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); - } - else - { + cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); + } else { cmd->resp[0] = sdhci_command.response[0]; LOG_D(" resp 0x%08X\n", cmd->resp[0]); } @@ -774,48 +649,41 @@ static void kd_mmc_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) return; } -void kd_card_clk_enable(struct sdhci_host *host, uint32_t enable ) +void kd_card_clk_enable(struct sdhci_host* host, uint32_t enable) { - if(enable) - { - sdhci_writew(host,sdhci_readw(host, SDHCI_CLOCK_CONTROL)|SDHCI_CLOCK_CARD_EN|SDHCI_PROG_CLOCK_MODE,SDHCI_CLOCK_CONTROL); - } - else - { - sdhci_writew(host,sdhci_readw(host, SDHCI_CLOCK_CONTROL)&(~ SDHCI_CLOCK_CARD_EN), SDHCI_CLOCK_CONTROL); - } - + if (enable) { + sdhci_writew(host, sdhci_readw(host, SDHCI_CLOCK_CONTROL) | SDHCI_CLOCK_CARD_EN | SDHCI_PROG_CLOCK_MODE, SDHCI_CLOCK_CONTROL); + } else { + sdhci_writew(host, sdhci_readw(host, SDHCI_CLOCK_CONTROL) & (~SDHCI_CLOCK_CARD_EN), SDHCI_CLOCK_CONTROL); + } } -void kd_pll_clk_enable(struct sdhci_host *host, uint32_t enable ) +void kd_pll_clk_enable(struct sdhci_host* host, uint32_t enable) { - if(enable) - { - sdhci_writew(host,sdhci_readw(host, SDHCI_CLOCK_CONTROL)|SDHCI_CLOCK_PLL_EN, SDHCI_CLOCK_CONTROL); - } - else - { - sdhci_writew(host,sdhci_readw(host, SDHCI_CLOCK_CONTROL)&(~ SDHCI_CLOCK_PLL_EN), SDHCI_CLOCK_CONTROL); - } + if (enable) { + sdhci_writew(host, sdhci_readw(host, SDHCI_CLOCK_CONTROL) | SDHCI_CLOCK_PLL_EN, SDHCI_CLOCK_CONTROL); + } else { + sdhci_writew(host, sdhci_readw(host, SDHCI_CLOCK_CONTROL) & (~SDHCI_CLOCK_PLL_EN), SDHCI_CLOCK_CONTROL); + } } -void kd_mmc_clock_freq_change(struct sdhci_host *host, uint32_t clock) +void kd_mmc_clock_freq_change(struct sdhci_host* host, uint32_t clock) { uint32_t div = 0, clk = 0; - //Execute SD Clock Stop Sequence - kd_card_clk_enable(host,0); - //Set CLK_CTRL_R.PLL_ENABLE to 0 - kd_pll_clk_enable(host,0); - if(clock == 0) + // Execute SD Clock Stop Sequence + kd_card_clk_enable(host, 0); + // Set CLK_CTRL_R.PLL_ENABLE to 0 + kd_pll_clk_enable(host, 0); + if (clock == 0) return; if (host->max_clk <= clock) { div = 1; } else { for (div = 2; - div < SDHCI_MAX_DIV_SPEC_300; - div += 2) { + div < SDHCI_MAX_DIV_SPEC_300; + div += 2) { if ((host->max_clk / div) <= clock) break; } @@ -827,14 +695,14 @@ void kd_mmc_clock_freq_change(struct sdhci_host *host, uint32_t clock) sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); - kd_pll_clk_enable(host,1); - kd_card_clk_enable(host,1); - sdhci_writew(host,sdhci_readw(host, SDHCI_CLOCK_CONTROL)|SDHCI_CLOCK_INT_EN,SDHCI_CLOCK_CONTROL); + kd_pll_clk_enable(host, 1); + kd_card_clk_enable(host, 1); + sdhci_writew(host, sdhci_readw(host, SDHCI_CLOCK_CONTROL) | SDHCI_CLOCK_INT_EN, SDHCI_CLOCK_CONTROL); } -static void kd_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) +static void kd_set_iocfg(struct rt_mmcsd_host* host, struct rt_mmcsd_io_cfg* io_cfg) { - struct sdhci_host *mmcsd; + struct sdhci_host* mmcsd; unsigned int sdhci_clk; unsigned int bus_width; uint8_t ctrl = 0; @@ -842,109 +710,105 @@ static void kd_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_ RT_ASSERT(host->private_data != RT_NULL); RT_ASSERT(io_cfg != RT_NULL); - mmcsd = (struct sdhci_host *)host->private_data; + mmcsd = (struct sdhci_host*)host->private_data; sdhci_clk = io_cfg->clock; bus_width = io_cfg->bus_width; - /* ToDo : Use the Clock Framework */ + /* ToDo : Use the Clock Framework */ LOG_D("%s: sdhci_clk=%d, bus_width:%d\n", __func__, sdhci_clk, bus_width); kd_mmc_clock_freq_change(mmcsd, sdhci_clk); ctrl = sdhci_readb(mmcsd, SDHCI_HOST_CONTROL); - if (bus_width == 3) - { + if (bus_width == 3) { ctrl &= ~SDHCI_CTRL_4BITBUS; ctrl |= SDHCI_CTRL_8BITBUS; - } - else - { + } else { ctrl &= ~SDHCI_CTRL_8BITBUS; - if (bus_width == 2) - { + if (bus_width == 2) { ctrl |= SDHCI_CTRL_4BITBUS; - } - else - { + } else { ctrl &= ~SDHCI_CTRL_4BITBUS; } } sdhci_writeb(mmcsd, ctrl, SDHCI_HOST_CONTROL); } -static const struct rt_mmcsd_host_ops ops = -{ +static const struct rt_mmcsd_host_ops ops = { kd_mmc_request, kd_set_iocfg, - RT_NULL,//_mmc_get_card_status, - RT_NULL,//_mmc_enable_sdio_irq, + RT_NULL, //_mmc_get_card_status, + RT_NULL, //_mmc_enable_sdio_irq, }; -static int init_kd_mmc_core(struct sdhci_host *host) +static int init_kd_mmc_core(struct sdhci_host* host) { - if ((sdhci_readb(host, SDHCI_SOFTWARE_RESET) & SDHCI_RESET_ALL)) - { + if ((sdhci_readb(host, SDHCI_SOFTWARE_RESET) & SDHCI_RESET_ALL)) { LOG_E("%s: sd host controller reset error\n", __func__); return -1; } - return 0; + return 0; } static void kd_sdhci_clk_reset(void) { - static char *hi_sys_virt_addr; - static char *sysctl_virt_addr; - unsigned int data; - unsigned int hi_sys_config_addr = 0x91585000; - unsigned int sysctl_addr = 0x91101000; - - /*sdio:Hi_sys_config space,sdio write protect open */ - hi_sys_virt_addr = rt_ioremap((void *)hi_sys_config_addr,0x400); - sysctl_virt_addr = rt_ioremap((void *)sysctl_addr,0xb0); + static char* hi_sys_virt_addr; + static char* sysctl_virt_addr; + unsigned int data; + unsigned int hi_sys_config_addr = 0x91585000; + unsigned int sysctl_addr = 0x91101000; + + /*sdio:Hi_sys_config space,sdio write protect open */ + hi_sys_virt_addr = rt_ioremap((void*)hi_sys_config_addr, 0x400); + sysctl_virt_addr = rt_ioremap((void*)sysctl_addr, 0xb0); data = readl(hi_sys_virt_addr + 8); data |= 0x4; writel(data, hi_sys_virt_addr + 8); /*sysctl reset sdio1*/ writel(0x2, sysctl_virt_addr + 0x34); rt_thread_mdelay(1); - while(!(readl(sysctl_virt_addr + 0x34) & 0x20000000)); + while (!(readl(sysctl_virt_addr + 0x34) & 0x20000000)) + ; writel(0x20000000, sysctl_virt_addr + 0x34); rt_thread_mdelay(5); - + rt_iounmap(hi_sys_virt_addr); + rt_iounmap(sysctl_virt_addr); } rt_int32_t kd_sdhci_init(void) { #ifdef RT_USING_SDIO0 - struct sdhci_host *mmcsd1; + struct sdhci_host* mmcsd1; host1 = mmcsd_alloc_host(); - if (!host1) - { + if (!host1) { goto err; } mmcsd1 = rt_malloc(sizeof(struct sdhci_host)); - if (!mmcsd1) - { + if (!mmcsd1) { LOG_E("alloc mci failed\n"); goto err; } rt_memset(mmcsd1, 0, sizeof(struct sdhci_host)); - mmcsd1->mapbase = (void *)rt_ioremap((void *)SDEMMC0_BASE, 0x1000); - emmc0_base = (void *)mmcsd1->mapbase; + mmcsd1->mapbase = (void*)rt_ioremap((void*)SDEMMC0_BASE, 0x1000); + emmc0_base = (void*)mmcsd1->mapbase; mmcsd1->sdhci_data = RT_NULL; mmcsd1->sdhci_command = RT_NULL; mmcsd1->max_clk = 200000000; - strncpy(host1->name, "emmc", sizeof(host1->name)-1); + strncpy(host1->name, "sd", sizeof(host1->name) - 1); host1->ops = &ops; host1->freq_min = 400000; - host1->freq_max = 200000000; - host1->valid_ocr = VDD_165_195;//VDD_32_33 | VDD_33_34 ; - host1->flags = MMCSD_BUSWIDTH_8 | MMCSD_MUTBLKWRITE | \ - MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; - host1->max_seg_size = 65535; + host1->freq_max = 50000000; +#ifdef RT_SDIO0_SD + host1->valid_ocr = VDD_32_33 | VDD_33_34; + host1->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; +#else + host1->valid_ocr = VDD_165_195; + host1->flags = MMCSD_BUSWIDTH_8 | MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; +#endif + host1->max_seg_size = 512 * 512; host1->max_dma_segs = 1; host1->max_blk_size = 512; host1->max_blk_count = 4096; @@ -955,43 +819,39 @@ rt_int32_t kd_sdhci_init(void) _mmcsd_host_init(mmcsd1); host1->private_data = mmcsd1; - if (init_kd_mmc_core(mmcsd1)) - { + if (init_kd_mmc_core(mmcsd1)) { rt_free(mmcsd1); goto err; - } + } mmcsd_change(host1); #endif #ifdef RT_USING_SDIO1 - struct sdhci_host *mmcsd2; + struct sdhci_host* mmcsd2; host2 = mmcsd_alloc_host(); - if (!host2) - { + if (!host2) { goto err; } mmcsd2 = rt_malloc(sizeof(struct sdhci_host)); - if (!mmcsd2) - { + if (!mmcsd2) { LOG_E("alloc mci failed\n"); goto err; } rt_memset(mmcsd2, 0, sizeof(struct sdhci_host)); - mmcsd2->mapbase = (void *)rt_ioremap((void *)SDEMMC1_BASE, 0x1000); - emmc1_base = (void *)mmcsd2->mapbase; + mmcsd2->mapbase = (void*)rt_ioremap((void*)SDEMMC1_BASE, 0x1000); + emmc1_base = (void*)mmcsd2->mapbase; mmcsd2->sdhci_data = RT_NULL; mmcsd2->sdhci_command = RT_NULL; mmcsd2->max_clk = 100000000; - strncpy(host2->name, "sd", sizeof(host2->name)-1); + strncpy(host2->name, "sd", sizeof(host2->name) - 1); host2->ops = &ops; host2->freq_min = 375000; host2->freq_max = 50000000; - host2->valid_ocr = VDD_32_33 | VDD_33_34 ; - host2->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \ - MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; - host2->max_seg_size = 65535; + host2->valid_ocr = VDD_32_33 | VDD_33_34; + host2->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; + host2->max_seg_size = 512 * 512; host2->max_dma_segs = 1; host2->max_blk_size = 512; host2->max_blk_count = 4096; @@ -1004,17 +864,15 @@ rt_int32_t kd_sdhci_init(void) host2->private_data = mmcsd2; - if (init_kd_mmc_core(mmcsd2)) - { + if (init_kd_mmc_core(mmcsd2)) { rt_free(mmcsd2); goto err; - } + } mmcsd_change(host2); #endif mmcsd_mutex = rt_mutex_create("mmutex", RT_IPC_FLAG_FIFO); - if (mmcsd_mutex == RT_NULL) - { + if (mmcsd_mutex == RT_NULL) { LOG_E("create mmcsd mutex failed.\n"); goto err; } @@ -1034,5 +892,4 @@ rt_int32_t kd_sdhci_init(void) INIT_DEVICE_EXPORT(kd_sdhci_init); #endif /*defined(RT_USING_SDIO0) || defined(RT_USING_SDIO1)*/ -#endif/*defined(RT_USING_SDIO)*/ - +#endif /*defined(RT_USING_SDIO)*/ diff --git a/src/big/rt-smart/kernel/bsp/maix3/board/interdrv/uart_canaan/drv_uart.c b/src/big/rt-smart/kernel/bsp/maix3/board/interdrv/uart_canaan/drv_uart.c index 960cd68ca..066d781ee 100755 --- a/src/big/rt-smart/kernel/bsp/maix3/board/interdrv/uart_canaan/drv_uart.c +++ b/src/big/rt-smart/kernel/bsp/maix3/board/interdrv/uart_canaan/drv_uart.c @@ -35,7 +35,14 @@ #include #include #endif - +#define DBG_TAG "uart" +#ifdef RT_DEBUG +#define DBG_LVL DBG_LOG +#else +#define DBG_LVL DBG_WARNING +#endif +#define DBG_COLOR +#include #define UART_RBR (0x00) /* receive buffer register */ #define UART_THR (0x00) /* transmit holding register */ @@ -254,37 +261,26 @@ const static struct dfs_file_ops _uart_fops = static void kd_uart_init(volatile void *uart_base, int index) { - uint32_t value = 0; - uint32_t bdiv; - uint32_t dlf; - uint32_t dlh; - uint32_t dll; + float calc_baudrate; + float fdiv; + uint8_t frac; + uint16_t dl; uint32_t uart_clock; - switch (index) - { - case 1: - uart_clock = sysctl_clk_get_leaf_freq(SYSCTL_CLK_UART_1_CLK); - break; - case 2: - uart_clock = sysctl_clk_get_leaf_freq(SYSCTL_CLK_UART_2_CLK); - break; - case 4: - uart_clock = sysctl_clk_get_leaf_freq(SYSCTL_CLK_UART_4_CLK); - break; - default: - return; - } - - bdiv = uart_clock / DEFAULT_BAUDRATE; + sysctl_clk_set_leaf_div(SYSCTL_CLK_UART_0_CLK + index, 1, 1); + uart_clock = sysctl_clk_get_leaf_freq(SYSCTL_CLK_UART_0_CLK + index); - dlh = bdiv >> 12; - dll = (bdiv - (dlh << 12)) / 16; - dlf = bdiv - (dlh << 12) - dll * 16; - if(dlh == 0 && dll == 0) - { - dll = 1; - dlf = 0; + fdiv = 1.0f * uart_clock / DEFAULT_BAUDRATE; + dl = fdiv / 16; + frac = 0.5f + fdiv - dl * 16; + if (dl == 0) { + dl = 1; + frac = 0; + } + calc_baudrate = 1.0f * uart_clock / (dl * 16 + frac); + if ((calc_baudrate - DEFAULT_BAUDRATE) / DEFAULT_BAUDRATE > 0.02f) { + LOG_E("The baud rate error is too large, %u", (uint32_t)calc_baudrate); + return; } write32(uart_base + UART_LCR, 0x00); @@ -292,14 +288,12 @@ static void kd_uart_init(volatile void *uart_base, int index) write32(uart_base + UART_IER, 0x00); /* Enable DLAB */ write32(uart_base + UART_LCR, 0x80); - if (bdiv) { - /* Set divisor low byte */ - write32(uart_base + UART_DLL, dll); - /* Set divisor high byte */ - write32(uart_base + UART_DLH, dlh); - /* Set divisor fraction byte*/ - write32(uart_base + UART_DLF, dlf); - } + /* Set divisor low byte */ + write32(uart_base + UART_DLL, (uint8_t)dl); + /* Set divisor high byte */ + write32(uart_base + UART_DLH, (uint8_t)(dl >> 8)); + /* Set divisor fraction byte*/ + write32(uart_base + UART_DLF, frac); /* 8 bits, no parity, one stop bit */ write32(uart_base + UART_LCR, 0x03); /* Enable FIFO */ @@ -404,63 +398,32 @@ static rt_err_t uart_control(rt_device_t dev, int cmd, void *args) struct kd_uart_device *kd_uart_device = (struct kd_uart_device *)dev->user_data; volatile void *uart_base = kd_uart_device->base; int id = kd_uart_device->id; - - uint32_t bdiv; - uint32_t dlf; - uint32_t dlh; - uint32_t dll; + float calc_baudrate; + float fdiv; + uint8_t frac; + uint16_t dl; uint32_t uart_clock; - - uint32_t value = 0; + uint32_t value; struct uart_configure *config = (struct uart_configure*)args; if (cmd != IOC_SET_BAUDRATE) - { return -RT_EINVAL; - } if (config == RT_NULL || uart_base == RT_NULL) - { return -RT_EINVAL; - } - if (config->baud_rate > 3000000) - { - switch (id) - { - case 1: - sysctl_clk_set_leaf_div(SYSCTL_CLK_UART_1_CLK, 1, 1); - break; - case 2: - sysctl_clk_set_leaf_div(SYSCTL_CLK_UART_2_CLK, 1, 1); - break; - case 4: - sysctl_clk_set_leaf_div(SYSCTL_CLK_UART_4_CLK, 1, 1); - break; - } - } + uart_clock = sysctl_clk_get_leaf_freq(SYSCTL_CLK_UART_0_CLK + id); - switch (id) - { - case 1: - uart_clock = sysctl_clk_get_leaf_freq(SYSCTL_CLK_UART_1_CLK); - break; - case 2: - uart_clock = sysctl_clk_get_leaf_freq(SYSCTL_CLK_UART_2_CLK); - break; - case 4: - uart_clock = sysctl_clk_get_leaf_freq(SYSCTL_CLK_UART_4_CLK); - break; + fdiv = 1.0f * uart_clock / config->baud_rate; + dl = fdiv / 16; + frac = 0.5f + fdiv - dl * 16; + if (dl == 0) { + dl = 1; + frac = 0; } - - bdiv = uart_clock / config->baud_rate; - - dlh = bdiv >> 12; - dll = (bdiv - (dlh << 12)) / 16; - dlf = bdiv - (dlh << 12) - dll * 16; - if(dlh == 0 && dll == 0) - { - dll = 1; - dlf = 0; + calc_baudrate = 1.0f * uart_clock / (dl * 16 + frac); + if ((calc_baudrate - config->baud_rate) / config->baud_rate > 0.02f) { + LOG_E("The baud rate error is too large, %u", (uint32_t)calc_baudrate); + return -RT_EINVAL; } /* stop uart */ @@ -468,11 +431,9 @@ static rt_err_t uart_control(rt_device_t dev, int cmd, void *args) write32(uart_base + UART_IER, 0x00); write32(uart_base + UART_LCR, 0x80); /* caculate diciver */ - if (bdiv) { - write32(uart_base + UART_DLL, dll); - write32(uart_base + UART_DLH, dlh); - write32(uart_base + UART_DLF, dlf); - } + write32(uart_base + UART_DLL, (uint8_t)dl); + write32(uart_base + UART_DLH, (uint8_t)(dl >> 8)); + write32(uart_base + UART_DLF, frac); value = (config->data_bits - 5) | (config->stop_bits << 2) | (config->parity << 3); write32(uart_base + UART_LCR, value & ~0x80); diff --git a/src/big/rt-smart/kernel/bsp/maix3/board/ipcm/SConscript b/src/big/rt-smart/kernel/bsp/maix3/board/ipcm/SConscript index 2f26d5b59..634594101 100755 --- a/src/big/rt-smart/kernel/bsp/maix3/board/ipcm/SConscript +++ b/src/big/rt-smart/kernel/bsp/maix3/board/ipcm/SConscript @@ -18,7 +18,7 @@ for item in liblist: libname = libname + '-l' + item[3:-2] + ' ' LINKFLAGS = ' -Wl,--whole-archive ' + libname + ' -Wl,--no-whole-archive' -group = DefineGroup('Ipcm', src, depend = [''], CPPPATH = CPPPATH, LINKFLAGS = LINKFLAGS, LIBPATH=LIBPATH) +group = DefineGroup('Ipcm', src, depend = ['RT_USING_IPCM'], CPPPATH = CPPPATH, LINKFLAGS = LINKFLAGS, LIBPATH=LIBPATH) objs = [group] diff --git a/src/big/rt-smart/kernel/bsp/maix3/board/mpp/SConscript b/src/big/rt-smart/kernel/bsp/maix3/board/mpp/SConscript index 7bb13decb..19e7e97d6 100755 --- a/src/big/rt-smart/kernel/bsp/maix3/board/mpp/SConscript +++ b/src/big/rt-smart/kernel/bsp/maix3/board/mpp/SConscript @@ -18,7 +18,7 @@ for item in liblist: libname = libname + '-l' + item[3:-2] + ' ' LINKFLAGS = ' -Wl,--whole-archive ' + libname + ' -Wl,--no-whole-archive' -group = DefineGroup('Mpp', src, depend = [''], CPPPATH = CPPPATH, LINKFLAGS = LINKFLAGS, LIBPATH=LIBPATH) +group = DefineGroup('Mpp', src, depend = ['RT_USING_MPP'], CPPPATH = CPPPATH, LINKFLAGS = LINKFLAGS, LIBPATH=LIBPATH) objs = [group] diff --git a/src/big/rt-smart/kernel/bsp/maix3/board/sdk_kernel_init.c b/src/big/rt-smart/kernel/bsp/maix3/board/sdk_kernel_init.c index b0e475ee6..716451c6a 100644 --- a/src/big/rt-smart/kernel/bsp/maix3/board/sdk_kernel_init.c +++ b/src/big/rt-smart/kernel/bsp/maix3/board/sdk_kernel_init.c @@ -2,20 +2,19 @@ #include #include - - extern rt_int32_t ipcm_module_init(void); extern rt_int32_t mpp_init(void); /*sdk kernel space init*/ rt_int32_t sdk_kernel_init(void) { +#ifdef RT_USING_IPCM ipcm_module_init(); -#if 0 - interdrv_init(); - extdrv_init(); #endif + +#ifdef RT_USING_MPP mpp_init(); +#endif return RT_EOK; } diff --git a/src/big/rt-smart/kernel/bsp/maix3/configs/common_rttlinux.config b/src/big/rt-smart/kernel/bsp/maix3/configs/common_rttlinux.config new file mode 100644 index 000000000..28125824b --- /dev/null +++ b/src/big/rt-smart/kernel/bsp/maix3/configs/common_rttlinux.config @@ -0,0 +1,361 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 20 +#define RT_USING_SMART +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 16384 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 16384 +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +#define RT_USING_SIGNALS + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +#define RT_USING_MEMHEAP_AS_HEAP +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_DEVICE_OPS +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 256 +#define RT_CONSOLE_DEVICE_NAME "uart" +#define RT_VER_NUM 0x50000 +#define ARCH_CPU_64BIT +#define RT_USING_CACHE +#define ARCH_MM_MMU +#define RT_USING_USERSPACE +#define KERNEL_VADDR_START 0x150000000 +#define PV_OFFSET 0 +#define ARCH_RISCV +#define ARCH_RISCV64 + +/* Proc Object*/ +#define RT_USING_PROC + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 16384 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 81920 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 1024 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 100 +#define MSH_WAIT_LWP_FINISH + +/* Device virtual file system */ + +#define RT_USING_DFS +#define RT_USING_DFS_TMPFS +#define RT_USING_DFS_SHAREFS +#define RT_USING_DEV_BUS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 6 +#define DFS_FILESYSTEM_TYPES_MAX 6 +#define DFS_FD_MAX 64 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT +#define RT_USING_DFS_DEVFS +#define RT_USING_DFS_ROMFS +#define RT_USING_DFS_TMPFS + +#define RT_USING_DFS_PROCFS +/* Device Drivers */ + +#define RT_USING_GNNE +#define RT_USING_DEVMEM2 +#define RT_USING_USAGE +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_TTY +#define RT_USING_CPUTIME +#define RT_USING_CPUTIME_RISCV +#define RT_USING_NULL +#define RT_USING_ZERO +#define RT_USING_RANDOM +#define RT_USING_DEVMEM +#define RT_USING_RTC +// #define RT_USING_RTC_PMU +#define RT_USING_I2C +#define RT_USING_I2C0 +#define RT_USING_I2C1 +#define RT_USING_I2C3 +#define RT_USING_I2C4 +#define RT_USING_I2C_DUMP +#define RT_USING_ADC +#define RT_USING_OTP +#define RT_USING_TS +#define RT_USING_HWHASH +#define RT_USING_AES +#define RT_USING_SM4 +#define RT_USING_HARDLOCK +#define RT_USING_GPIO +#define RT_USING_SPI +#define RT_USING_WDT +#define RT_USING_PWM +#define RT_USING_HWTIMER +#define RT_USING_HW_TIMER0 +#define RT_USING_HW_TIMER1 +#define RT_USING_HW_TIMER2 +#define RT_SDIO_STACK_SIZE 512 +#define RT_SDIO_THREAD_PRIORITY 15 +#define RT_MMCSD_STACK_SIZE 4096 +#define RT_MMCSD_THREAD_PREORITY 22 +#define RT_MMCSD_MAX_PARTITION 16 +#define RT_USING_DEV_BUS +#define RT_USING_REGULATOR +/* canaan uart driver for uart1 uart2 uart4 */ +// #define RT_USING_CANAAN_UART +// #define RT_USING_UART1 +// #define RT_USING_UART2 +// #define RT_USING_UART4 +#define UART_BUFFER_SIZE (1024 * 1024) +#define POLLIN_SIZE (UART_BUFFER_SIZE / 2) +#define UART_TIMEOUT (1000) + +//#define PKG_USING_CHERRYUSB +//#define CONFIG_ENABLE_USB_DEVICE 1 +//#define PKG_CHERRYUSB_DEVICE_DWC2 +//#define PKG_CHERRYUSB_DEVICE_DWC2_PORT_HS +//#define PKG_CHERRYUSB_DEVICE +//#define PKG_CHERRYUSB_DEVICE_CDC +//#define PKG_CHERRYUSB_DEVICE_MSC +/* Using USB */ + +/*Using fast boot*/ +#define RT_FASTBOOT + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_MUSL +#define RT_USING_POSIX +#define RT_USING_POSIX_CLOCKTIME + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + +#define RT_USING_LWP +#define RT_LWP_MAX_NR 30 +#define LWP_TASK_STACK_SIZE 16384 +#define RT_CH_MSG_MAX_NR 1024 +#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024 +#define LWP_TID_MAX_NR 64 +#define RT_LWP_SHM_MAX_NR 64 + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* PainterEngine: A cross-platform graphics application framework written in C language */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* sensors drivers */ + + +/* touch drivers */ + + +/* Kendryte SDK */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + +/* Signal IO */ + + +/* Uncategorized */ + +/* Kernel Testcase */ + +#define UTEST_MEMHEAP_TC +#define UTEST_IRQ_TC +#define UTEST_SEMAPHORE_TC +#define UTEST_EVENT_TC +#define UTEST_TIMER_TC +#define UTEST_MESSAGEQUEUE_TC +#define UTEST_MUTEX_TC +#define UTEST_MAILBOX_TC +#define UTEST_THREAD_TC +#define UTEST_MMU_TC +#define UTEST_ADC +#define UTEST_SPI_NAND +#define UTEST_OTP +#define UTEST_WDT +#define UTEST_TS +// #define UTEST_RTC +// #define UTEST_HWTIMER +// #define UTEST_PWM +//#define UTEST_I2C_OV9282 +//#define UTEST_I2C_TMP103 +// #define UTEST_GPIO +#define BOARD_fpgac908 +#define ENABLE_FPU +#define ENABLE_VECTOR +#define __STACKSIZE__ 65536 + +#define RT_USING_MPP +#define RT_USING_IPCM +#endif diff --git a/src/big/rt-smart/kernel/bsp/maix3/configs/common_rttonly.config b/src/big/rt-smart/kernel/bsp/maix3/configs/common_rttonly.config new file mode 100644 index 000000000..651fd6f7f --- /dev/null +++ b/src/big/rt-smart/kernel/bsp/maix3/configs/common_rttonly.config @@ -0,0 +1,439 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 20 +#define RT_USING_SMART +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 16384 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 16384 +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +#define RT_USING_SIGNALS + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +#define RT_USING_MEMHEAP_AS_HEAP +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_DEVICE_OPS +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 256 +#define RT_CONSOLE_DEVICE_NAME "uart" +#define RT_VER_NUM 0x50000 +#define ARCH_CPU_64BIT +#define RT_USING_CACHE +#define ARCH_MM_MMU +#define RT_USING_USERSPACE +#define KERNEL_VADDR_START 0x150000000 +#define PV_OFFSET 0 +#define ARCH_RISCV +#define ARCH_RISCV64 + +/* Proc Object*/ +#define RT_USING_PROC + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 16384 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 81920 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 1024 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 100 +#define MSH_WAIT_LWP_FINISH + +/* Device virtual file system */ + +#define RT_USING_DFS +#define RT_USING_DFS_TMPFS +#define RT_USING_DFS_SHAREFS +#define RT_USING_DEV_BUS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 6 +#define DFS_FILESYSTEM_TYPES_MAX 6 +#define DFS_FD_MAX 64 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT +#define RT_USING_DFS_DEVFS +#define RT_USING_DFS_ROMFS +#define RT_USING_DFS_TMPFS + +#define RT_USING_DFS_PROCFS +#define RT_USING_DFS_NFS +#define RT_NFS_HOST_EXPORT "10.10.1.94:/home/jiangxiangbing/" + +/* Device Drivers */ + +#define RT_USING_GNNE +#define RT_USING_DEVMEM2 +#define RT_USING_USAGE +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 20480 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_TTY +#define RT_USING_CPUTIME +#define RT_USING_CPUTIME_RISCV +#define RT_USING_NULL +#define RT_USING_ZERO +#define RT_USING_RANDOM +#define RT_USING_DEVMEM +#define RT_USING_RTC +// #define RT_USING_RTC_PMU +#define RT_USING_I2C +#define RT_USING_I2C0 +#define RT_USING_I2C1 +#define RT_USING_I2C3 +#define RT_USING_I2C4 +#define RT_USING_I2C_DUMP +#define RT_USING_ADC +#define RT_USING_OTP +#define RT_USING_TS +#define RT_USING_HWHASH +#define RT_USING_AES +#define RT_USING_SM4 +#define RT_USING_HARDLOCK +#define RT_USING_GPIO +#define RT_USING_SPI +#define RT_USING_WDT +#define RT_USING_PWM +#define RT_USING_HWTIMER +#define RT_USING_HW_TIMER0 +#define RT_USING_HW_TIMER1 +#define RT_USING_HW_TIMER2 +#define RT_SDIO_STACK_SIZE 512 +#define RT_SDIO_THREAD_PRIORITY 15 +#define RT_MMCSD_STACK_SIZE 4096 +#define RT_MMCSD_THREAD_PREORITY 22 +#define RT_MMCSD_MAX_PARTITION 16 +#define RT_USING_DEV_BUS +#define RT_USING_REGULATOR +/* canaan uart driver for uart1 uart2 uart4 */ +// #define RT_USING_CANAAN_UART +// #define RT_USING_UART1 +// #define RT_USING_UART2 +// #define RT_USING_UART4 +#define UART_BUFFER_SIZE (1024 * 1024) +#define POLLIN_SIZE (UART_BUFFER_SIZE / 2) +#define UART_TIMEOUT (1000) + +/* Using USB */ +#define PKG_USING_CHERRYUSB + +#define PKG_CHERRYUSB_HOST +#define PKG_CHERRYUSB_HOST_DWC2_KENDRYTE +#define PKG_CHERRYUSB_HOST_RTL8152 +#define PKG_CHERRYUSB_HOST_TEMPLATE +#define CHERRYUSB_HOST_USING_USB1 + +#define PKG_CHERRYUSB_DEVICE +#define PKG_CHERRYUSB_DEVICE_HS +#define PKG_CHERRYUSB_DEVICE_DWC2_KENDRYTE +#define PKG_CHERRYUSB_DEVICE_CDC_ACM +#define PKG_CHERRYUSB_DEVICE_MSC +#define PKG_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM_MSC +#define CHERRYUSB_DEVICE_USING_USB0 + +/*Using fast boot*/ +#define RT_FASTBOOT + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_MUSL +#define RT_USING_POSIX +#define RT_USING_POSIX_CLOCKTIME + +/* Network */ + +/* Socket abstraction layer */ + +#define RT_USING_SAL + +/* protocol stack implement */ + +#define SAL_USING_LWIP +#define SAL_USING_POSIX +#define SAL_USING_AF_UNIX + +/* Network interface device */ + +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 + +/* light weight TCP/IP stack */ + +#define RT_USING_LWIP +#define RT_USING_LWIP212 +#define RT_LWIP_MEM_ALIGNMENT 8 +#define RT_LWIP_ICMP +#define RT_LWIP_DNS +#define RT_LWIP_DHCP +#define IP_SOF_BROADCAST 1 +#define IP_SOF_BROADCAST_RECV 1 + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.1.30" +#define RT_LWIP_GWADDR "192.168.1.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_LWIP_RAW +#define RT_MEMP_NUM_NETCONN 8 +#define RT_MEMP_NUM_TCPIP_MSG_API 16 +#define RT_MEMP_NUM_TCPIP_MSG_INPKT 16 +#define RT_LWIP_PBUF_NUM 16 +#define RT_LWIP_PBUF_STRUCT_NUM 16 +#define RT_LWIP_NETBUF_NUM 16 +#define RT_LWIP_RAW_PCB_NUM 8 +#define RT_LWIP_UDP_PCB_NUM 8 +#define RT_UDP_RECVMBOX_SIZE 16 +#define RT_RECV_BUFSIZE_DEFAULT 64 +#define RT_LWIP_TCP_PCB_NUM 8 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_TCP_RECVMBOX_SIZE 16 +#define RT_LWIP_TCPTHREAD_PRIORITY 10 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 10240 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 10240 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 +#define LWIP_NETIF_LOOPBACK 0 +#define RT_LWIP_USING_PING +// #define RT_LWIP_DEBUG +// #define RT_LWIP_SOCKETS_DEBUG +// #define RT_LWIP_PBUF_DEBUG +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + +#define RT_USING_LWP +#define RT_LWP_MAX_NR 30 +#define LWP_TASK_STACK_SIZE 16384 +#define RT_CH_MSG_MAX_NR 1024 +#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024 +#define LWP_TID_MAX_NR 64 +#define RT_LWP_SHM_MAX_NR 64 + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* PainterEngine: A cross-platform graphics application framework written in C language */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* sensors drivers */ + + +/* touch drivers */ + + +/* Kendryte SDK */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + +/* Signal IO */ + + +/* Uncategorized */ + +/* Kernel Testcase */ + +#define UTEST_MEMHEAP_TC +#define UTEST_IRQ_TC +#define UTEST_SEMAPHORE_TC +#define UTEST_EVENT_TC +#define UTEST_TIMER_TC +#define UTEST_MESSAGEQUEUE_TC +#define UTEST_MUTEX_TC +#define UTEST_MAILBOX_TC +#define UTEST_THREAD_TC +#define UTEST_MMU_TC +#define UTEST_ADC +#define UTEST_SPI_NAND +#define UTEST_OTP +#define UTEST_WDT +#define UTEST_TS +// #define UTEST_RTC +// #define UTEST_HWTIMER +// #define UTEST_PWM +//#define UTEST_I2C_OV9282 +//#define UTEST_I2C_TMP103 +// #define UTEST_GPIO +#define BOARD_fpgac908 +#define ENABLE_FPU +#define ENABLE_VECTOR +#define __STACKSIZE__ 65536 + +#define RT_USING_MPP +#define RT_USING_SDIO +#define RT_USING_SDIO1 +#endif diff --git a/src/big/rt-smart/kernel/bsp/maix3/configs/k230d_canmv_only_rtt.config b/src/big/rt-smart/kernel/bsp/maix3/configs/k230d_canmv_only_rtt.config new file mode 100755 index 000000000..c8e84d577 --- /dev/null +++ b/src/big/rt-smart/kernel/bsp/maix3/configs/k230d_canmv_only_rtt.config @@ -0,0 +1,439 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 20 +#define RT_USING_SMART +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 16384 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 16384 +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +#define RT_USING_SIGNALS + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_MEMHEAP +#define RT_USING_MEMHEAP_AS_HEAP +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_DEVICE_OPS +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 256 +#define RT_CONSOLE_DEVICE_NAME "uart" +#define RT_VER_NUM 0x50000 +#define ARCH_CPU_64BIT +#define RT_USING_CACHE +#define ARCH_MM_MMU +#define RT_USING_USERSPACE +#define KERNEL_VADDR_START 0x150000000 +#define PV_OFFSET 0 +#define ARCH_RISCV +#define ARCH_RISCV64 + +/* Proc Object*/ +#define RT_USING_PROC + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 16384 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 81920 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 1024 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 100 +#define MSH_WAIT_LWP_FINISH + +/* Device virtual file system */ + +#define RT_USING_DFS +#define RT_USING_DFS_TMPFS +#define RT_USING_DFS_SHAREFS +#define RT_USING_DEV_BUS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 6 +#define DFS_FILESYSTEM_TYPES_MAX 6 +#define DFS_FD_MAX 64 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT +#define RT_USING_DFS_DEVFS +#define RT_USING_DFS_ROMFS +#define RT_USING_DFS_TMPFS + +#define RT_USING_DFS_PROCFS +#define RT_USING_DFS_NFS +#define RT_NFS_HOST_EXPORT "10.10.1.94:/home/jiangxiangbing/" + +/* Device Drivers */ + +#define RT_USING_GNNE +#define RT_USING_DEVMEM2 +#define RT_USING_USAGE +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 20480 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_TTY +#define RT_USING_CPUTIME +#define RT_USING_CPUTIME_RISCV +#define RT_USING_NULL +#define RT_USING_ZERO +#define RT_USING_RANDOM +#define RT_USING_DEVMEM +#define RT_USING_RTC +// #define RT_USING_RTC_PMU +#define RT_USING_I2C +#define RT_USING_I2C0 +#define RT_USING_I2C1 +#define RT_USING_I2C3 +#define RT_USING_I2C4 +#define RT_USING_I2C_DUMP +#define RT_USING_ADC +#define RT_USING_OTP +#define RT_USING_TS +#define RT_USING_HWHASH +#define RT_USING_AES +#define RT_USING_SM4 +#define RT_USING_HARDLOCK +#define RT_USING_GPIO +#define RT_USING_SPI +#define RT_USING_WDT +#define RT_USING_PWM +#define RT_USING_HWTIMER +#define RT_USING_HW_TIMER0 +#define RT_USING_HW_TIMER1 +#define RT_USING_HW_TIMER2 +#define RT_SDIO_STACK_SIZE 512 +#define RT_SDIO_THREAD_PRIORITY 15 +#define RT_MMCSD_STACK_SIZE 4096 +#define RT_MMCSD_THREAD_PREORITY 22 +#define RT_MMCSD_MAX_PARTITION 16 +#define RT_USING_DEV_BUS +#define RT_USING_REGULATOR +/* canaan uart driver for uart1 uart2 uart4 */ +// #define RT_USING_CANAAN_UART +// #define RT_USING_UART1 +// #define RT_USING_UART2 +// #define RT_USING_UART4 +#define UART_BUFFER_SIZE (1024 * 1024) +#define POLLIN_SIZE (UART_BUFFER_SIZE / 2) +#define UART_TIMEOUT (1000) + +/* Using USB */ +#define PKG_USING_CHERRYUSB + +#define PKG_CHERRYUSB_HOST +#define PKG_CHERRYUSB_HOST_DWC2_KENDRYTE +#define PKG_CHERRYUSB_HOST_RTL8152 +#define PKG_CHERRYUSB_HOST_TEMPLATE +#define CHERRYUSB_HOST_USING_USB0 +/* +#define PKG_CHERRYUSB_DEVICE +#define PKG_CHERRYUSB_DEVICE_HS +#define PKG_CHERRYUSB_DEVICE_DWC2_KENDRYTE +#define PKG_CHERRYUSB_DEVICE_CDC_ACM +#define PKG_CHERRYUSB_DEVICE_MSC +#define PKG_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM_MSC +#define CHERRYUSB_DEVICE_USING_USB0 +*/ +/*Using fast boot*/ +#define RT_FASTBOOT + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_MUSL +#define RT_USING_POSIX +#define RT_USING_POSIX_CLOCKTIME + +/* Network */ + +/* Socket abstraction layer */ + +#define RT_USING_SAL + +/* protocol stack implement */ + +#define SAL_USING_LWIP +#define SAL_USING_POSIX +#define SAL_USING_AF_UNIX + +/* Network interface device */ + +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 + +/* light weight TCP/IP stack */ + +#define RT_USING_LWIP +#define RT_USING_LWIP212 +#define RT_LWIP_MEM_ALIGNMENT 8 +#define RT_LWIP_ICMP +#define RT_LWIP_DNS +#define RT_LWIP_DHCP +#define IP_SOF_BROADCAST 1 +#define IP_SOF_BROADCAST_RECV 1 + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.1.30" +#define RT_LWIP_GWADDR "192.168.1.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_LWIP_RAW +#define RT_MEMP_NUM_NETCONN 8 +#define RT_MEMP_NUM_TCPIP_MSG_API 16 +#define RT_MEMP_NUM_TCPIP_MSG_INPKT 16 +#define RT_LWIP_PBUF_NUM 16 +#define RT_LWIP_PBUF_STRUCT_NUM 16 +#define RT_LWIP_NETBUF_NUM 16 +#define RT_LWIP_RAW_PCB_NUM 8 +#define RT_LWIP_UDP_PCB_NUM 8 +#define RT_UDP_RECVMBOX_SIZE 16 +#define RT_RECV_BUFSIZE_DEFAULT 64 +#define RT_LWIP_TCP_PCB_NUM 8 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_TCP_RECVMBOX_SIZE 16 +#define RT_LWIP_TCPTHREAD_PRIORITY 10 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 10240 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 10240 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 +#define LWIP_NETIF_LOOPBACK 0 +#define RT_LWIP_USING_PING +// #define RT_LWIP_DEBUG +// #define RT_LWIP_SOCKETS_DEBUG +// #define RT_LWIP_PBUF_DEBUG +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + +#define RT_USING_LWP +#define RT_LWP_MAX_NR 30 +#define LWP_TASK_STACK_SIZE 16384 +#define RT_CH_MSG_MAX_NR 1024 +#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024 +#define LWP_TID_MAX_NR 64 +#define RT_LWP_SHM_MAX_NR 64 + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* PainterEngine: A cross-platform graphics application framework written in C language */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* sensors drivers */ + + +/* touch drivers */ + + +/* Kendryte SDK */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + +/* Signal IO */ + + +/* Uncategorized */ + +/* Kernel Testcase */ + +#define UTEST_MEMHEAP_TC +#define UTEST_IRQ_TC +#define UTEST_SEMAPHORE_TC +#define UTEST_EVENT_TC +#define UTEST_TIMER_TC +#define UTEST_MESSAGEQUEUE_TC +#define UTEST_MUTEX_TC +#define UTEST_MAILBOX_TC +#define UTEST_THREAD_TC +#define UTEST_MMU_TC +#define UTEST_ADC +#define UTEST_SPI_NAND +#define UTEST_OTP +#define UTEST_WDT +#define UTEST_TS +// #define UTEST_RTC +// #define UTEST_HWTIMER +// #define UTEST_PWM +//#define UTEST_I2C_OV9282 +//#define UTEST_I2C_TMP103 +// #define UTEST_GPIO +#define BOARD_fpgac908 +#define ENABLE_FPU +#define ENABLE_VECTOR +#define __STACKSIZE__ 65536 + +#define RT_USING_MPP +#define RT_USING_SDIO +#define RT_USING_SDIO1 +#endif diff --git a/src/big/rt-smart/kernel/bsp/maix3/link.lds b/src/big/rt-smart/kernel/bsp/maix3/link.lds index bc298cf40..aa4a92405 100644 --- a/src/big/rt-smart/kernel/bsp/maix3/link.lds +++ b/src/big/rt-smart/kernel/bsp/maix3/link.lds @@ -69,6 +69,11 @@ SECTIONS KEEP(*(UtestTcTab)) __rt_utest_tc_tab_end = .; + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + . = ALIGN(8); _etext = .; } > SRAM diff --git a/src/big/rt-smart/kernel/bsp/maix3/link_stacksize.lds b/src/big/rt-smart/kernel/bsp/maix3/link_stacksize.lds index 8685bc0f1..89ab4af21 100644 --- a/src/big/rt-smart/kernel/bsp/maix3/link_stacksize.lds +++ b/src/big/rt-smart/kernel/bsp/maix3/link_stacksize.lds @@ -1 +1 @@ -__STACKSIZE__ = 16384; \ No newline at end of file +__STACKSIZE__ = 65536; \ No newline at end of file diff --git a/src/big/rt-smart/kernel/bsp/maix3/rtconfig.h b/src/big/rt-smart/kernel/bsp/maix3/rtconfig.h index f6f130367..28125824b 100644 --- a/src/big/rt-smart/kernel/bsp/maix3/rtconfig.h +++ b/src/big/rt-smart/kernel/bsp/maix3/rtconfig.h @@ -354,9 +354,8 @@ #define BOARD_fpgac908 #define ENABLE_FPU #define ENABLE_VECTOR -#define __STACKSIZE__ 16384 +#define __STACKSIZE__ 65536 +#define RT_USING_MPP +#define RT_USING_IPCM #endif -#define RT_USING_UTEST -#define UTEST_THR_STACK_SIZE 16384 -#define UTEST_THR_PRIORITY 20 diff --git a/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/dfs_nfs.c b/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/dfs_nfs.c index fc296b6eb..15c360756 100644 --- a/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/dfs_nfs.c +++ b/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/dfs_nfs.c @@ -18,7 +18,6 @@ #include "mount.h" #include "nfs.h" -#define NAME_MAX 64 #define DFS_NFS_MAX_MTU 1024 #ifdef _WIN32 @@ -44,8 +43,8 @@ struct nfs_dir READDIR3res res; }; -#define HOST_LENGTH 32 -#define EXPORT_PATH_LENGTH 32 +#define HOST_LENGTH 256 +#define EXPORT_PATH_LENGTH 256 struct nfs_filesystem { @@ -236,7 +235,7 @@ static nfs_fh3 *get_dir_handle(nfs_filesystem *nfs, const char *name) if (nfsproc3_lookup_3(args, &res, nfs->nfs_client) != RPC_SUCCESS) { - rt_kprintf("Lookup failed\n"); + rt_kprintf("Lookup failed.\n"); rt_free(init); rt_free(handle); xdr_free((xdrproc_t)xdr_nfs_fh3, (char *)&args.what.dir); @@ -354,7 +353,7 @@ int nfs_create(nfs_filesystem *nfs, const char *name, mode_t mode) { args.where.name = (char *)name; } - args.how.mode = GUARDED; + args.how.mode = UNCHECKED; args.how.createhow3_u.obj_attributes.mode.set_it = TRUE; args.how.createhow3_u.obj_attributes.mode.set_mode3_u.mode = mode; @@ -562,10 +561,10 @@ int nfs_read(struct dfs_fd *file, void *buf, size_t count) if (file->fnode->type == FT_DIRECTORY) return -EISDIR; - RT_ASSERT(file->fnode->data != NULL); - struct dfs_filesystem *dfs_nfs = ((struct dfs_filesystem *)(file->fnode->data)); + RT_ASSERT(file->fnode->fs != NULL); + struct dfs_filesystem *dfs_nfs = ((struct dfs_filesystem *)(file->fnode->fs)); nfs = (struct nfs_filesystem *)(dfs_nfs->data); - fd = (nfs_file *)(nfs->data); + fd = (nfs_file *)(file->data); RT_ASSERT(fd != NULL); if (nfs->nfs_client == NULL) @@ -631,10 +630,10 @@ int nfs_write(struct dfs_fd *file, const void *buf, size_t count) if (file->fnode->type == FT_DIRECTORY) return -EISDIR; - RT_ASSERT(file->fnode->data != NULL); - struct dfs_filesystem *dfs_nfs = ((struct dfs_filesystem *)(file->fnode->data)); + RT_ASSERT(file->fnode->fs != NULL); + struct dfs_filesystem *dfs_nfs = ((struct dfs_filesystem *)(file->fnode->fs)); nfs = (struct nfs_filesystem *)(dfs_nfs->data); - fd = (nfs_file *)(nfs->data); + fd = (nfs_file *)(file->data); RT_ASSERT(fd != NULL); if (nfs->nfs_client == NULL) @@ -693,14 +692,17 @@ int nfs_lseek(struct dfs_fd *file, off_t offset) if (file->fnode->type == FT_DIRECTORY) return -EISDIR; - RT_ASSERT(file->fnode->data != NULL); - struct dfs_filesystem *dfs_nfs = ((struct dfs_filesystem *)(file->fnode->data)); + RT_ASSERT(file->fnode->fs != NULL); + struct dfs_filesystem *dfs_nfs = ((struct dfs_filesystem *)(file->fnode->fs)); nfs = (struct nfs_filesystem *)(dfs_nfs->data); - fd = (nfs_file *)(nfs->data); + fd = (nfs_file *)(file->data); RT_ASSERT(fd != NULL); if (offset <= fd->size) { + if (offset < fd->size) fd->eof = FALSE; + else fd->eof = TRUE; + fd->offset = offset; return offset; @@ -712,8 +714,8 @@ int nfs_lseek(struct dfs_fd *file, off_t offset) int nfs_close(struct dfs_fd *file) { nfs_filesystem *nfs; - RT_ASSERT(file->fnode->data != NULL); - struct dfs_filesystem *dfs_nfs = ((struct dfs_filesystem *)(file->fnode->data)); + RT_ASSERT(file->fnode->fs != NULL); + struct dfs_filesystem *dfs_nfs = ((struct dfs_filesystem *)(file->fnode->fs)); RT_ASSERT(file->fnode->ref_count > 0); if (file->fnode->ref_count > 1) @@ -727,7 +729,7 @@ int nfs_close(struct dfs_fd *file) { struct nfs_dir *dir; - dir = (struct nfs_dir *)nfs->data; + dir = (struct nfs_dir *)file->data; xdr_free((xdrproc_t)xdr_nfs_fh3, (char *)&dir->handle); xdr_free((xdrproc_t)xdr_READDIR3res, (char *)&dir->res); rt_free(dir); @@ -736,20 +738,20 @@ int nfs_close(struct dfs_fd *file) { struct nfs_file *fd; - fd = (struct nfs_file *)nfs->data; + fd = (struct nfs_file *)file->data; xdr_free((xdrproc_t)xdr_nfs_fh3, (char *)&fd->handle); rt_free(fd); } - nfs->data = NULL; + file->data = NULL; return 0; } int nfs_open(struct dfs_fd *file) { nfs_filesystem *nfs; - RT_ASSERT(file->fnode->data != NULL); + RT_ASSERT(file->fnode->fs != NULL); struct dfs_filesystem *dfs_nfs = file->fnode->fs; nfs = (struct nfs_filesystem *)(dfs_nfs->data); RT_ASSERT(nfs != NULL); @@ -785,7 +787,7 @@ int nfs_open(struct dfs_fd *file) return -ENOENT; } file->fnode->type = FT_DIRECTORY; - nfs->data = dir; + file->data = dir; } else { @@ -829,7 +831,7 @@ int nfs_open(struct dfs_fd *file) } /* set private file */ - nfs->data = fp; + file->data = fp; file->fnode->size = fp->size; file->fnode->type = FT_REGULAR; } @@ -1111,10 +1113,10 @@ int nfs_getdents(struct dfs_fd *file, struct dirent *dirp, uint32_t count) nfs_filesystem *nfs; char *name; - RT_ASSERT(file->fnode->data != NULL); - struct dfs_filesystem *dfs_nfs = ((struct dfs_filesystem *)(file->fnode->data)); + RT_ASSERT(file->fnode->fs != NULL); + struct dfs_filesystem *dfs_nfs = ((struct dfs_filesystem *)(file->fnode->fs)); nfs = (struct nfs_filesystem *)(dfs_nfs->data); - dir = (nfs_dir *)(nfs->data); + dir = (nfs_dir *)(file->data); RT_ASSERT(dir != NULL); /* make integer count */ diff --git a/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/nfs_xdr.c b/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/nfs_xdr.c index 33563976c..12b9f7615 100644 --- a/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/nfs_xdr.c +++ b/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/nfs_xdr.c @@ -35,17 +35,13 @@ xdr_int64(register XDR *xdrs, int64 *objp) bool_t xdr_uint32(register XDR *xdrs, uint32 *objp) { - if (!xdr_u_long(xdrs, objp)) - return (FALSE); - return (TRUE); + return (xdr_u_int(xdrs, objp)); } bool_t xdr_int32(register XDR *xdrs, int32 *objp) { - if (!xdr_long(xdrs, objp)) - return (FALSE); - return (TRUE); + return (xdr_int(xdrs, objp)); } bool_t diff --git a/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/rpc/clnt_udp.c b/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/rpc/clnt_udp.c index 6b4f7bfb1..550310456 100644 --- a/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/rpc/clnt_udp.c +++ b/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/rpc/clnt_udp.c @@ -226,7 +226,7 @@ static enum clnt_stat clntudp_call(CLIENT *cl, unsigned long proc, XDR reply_xdrs; bool_t ok; int nrefreshes = 2; /* number of times to refresh cred */ - + int ret; call_again: xdrs = &(cu->cu_outxdrs); xdrs->x_op = XDR_ENCODE; @@ -246,9 +246,9 @@ static enum clnt_stat clntudp_call(CLIENT *cl, unsigned long proc, outlen = (int) XDR_GETPOS(xdrs); send_again: - if (sendto(cu->cu_sock, cu->cu_outbuf, outlen, 0, - (struct sockaddr *) &(cu->cu_raddr), cu->cu_rlen) - != outlen) + ret = sendto(cu->cu_sock, cu->cu_outbuf, outlen, 0, + (struct sockaddr *) &(cu->cu_raddr), cu->cu_rlen); + if (ret != outlen) { cu->cu_error.re_errno = errno; cu->cu_error.re_status = RPC_CANTSEND; @@ -395,7 +395,7 @@ static void clntudp_destroy(CLIENT *cl) if (cu->cu_closeit) { - lwip_close(cu->cu_sock); + close(cu->cu_sock); } XDR_DESTROY(&(cu->cu_outxdrs)); diff --git a/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/rpc/pmap.c b/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/rpc/pmap.c index dc5a2ccb8..b505bdf6e 100644 --- a/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/rpc/pmap.c +++ b/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/rpc/pmap.c @@ -55,7 +55,7 @@ unsigned short pmap_getport(struct sockaddr_in *address, unsigned long program, CLNT_DESTROY(client); } - (void) lwip_close(socket); + (void) close(socket); address->sin_port = 0; return (port); diff --git a/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/rpc/types.h b/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/rpc/types.h index 5c02c07e3..b2e882230 100644 --- a/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/rpc/types.h +++ b/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/rpc/types.h @@ -57,8 +57,8 @@ typedef unsigned long u_long; #include #endif -typedef long long int64_t; -typedef unsigned long long uint64_t; +// typedef long long int64_t; +// typedef unsigned long long uint64_t; typedef int bool_t; typedef int enum_t; diff --git a/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/rpc/xdr.c b/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/rpc/xdr.c index a6b1b67af..4a9daf896 100644 --- a/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/rpc/xdr.c +++ b/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/rpc/xdr.c @@ -98,15 +98,12 @@ bool_t xdr_int(XDR* xdrs, int* ip) if (sizeof(int) == sizeof(long)) { return (xdr_long(xdrs, (long *) ip)); } else if (sizeof(int) < sizeof(long)) { - long l; switch (xdrs->x_op) { case XDR_ENCODE: - l = (long) *ip; - return XDR_PUTLONG(xdrs, &l); + return XDR_PUTINT32(xdrs, ip); case XDR_DECODE: - if (!XDR_GETLONG(xdrs, &l)) + if (!XDR_GETINT32(xdrs, ip)) return FALSE; - *ip = (int) l; case XDR_FREE: return TRUE; } @@ -128,9 +125,9 @@ bool_t xdr_u_int(XDR* xdrs, unsigned int* up) switch (xdrs->x_op) { case XDR_ENCODE: l = (unsigned long) *up; - return XDR_PUTLONG(xdrs, (long*)&l); + return XDR_PUTINT32(xdrs, (long*)&l); case XDR_DECODE: - if (!XDR_GETLONG(xdrs, (long*)&l)) + if (!XDR_GETINT32(xdrs, (long*)&l)) return FALSE; *up = (unsigned int) l; case XDR_FREE: @@ -337,16 +334,16 @@ bool_t xdr_u_char(XDR* xdrs, unsigned char* cp) */ bool_t xdr_bool(XDR *xdrs, bool_t *bp) { - long lb; + unsigned int lb; switch (xdrs->x_op) { case XDR_ENCODE: lb = *bp ? XDR_TRUE : XDR_FALSE; - return (XDR_PUTLONG(xdrs, &lb)); + return (XDR_PUTINT32(xdrs, &lb)); case XDR_DECODE: - if (!XDR_GETLONG(xdrs, &lb)) { + if (!XDR_GETINT32(xdrs, &lb)) { return (FALSE); } *bp = (lb == XDR_FALSE) ? FALSE : TRUE; @@ -363,10 +360,20 @@ bool_t xdr_bool(XDR *xdrs, bool_t *bp) */ bool_t xdr_enum(XDR *xdrs, enum_t *ep) { + enum sizecheck { SIZEVAL }; /* used to find the size of an enum */ + /* * enums are treated as ints */ - return (xdr_long(xdrs, (long *) ep)); + /* LINTED */ if (sizeof (enum sizecheck) == sizeof (long)) { + return (xdr_long(xdrs, (long *)(void *)ep)); + } else /* LINTED */ if (sizeof (enum sizecheck) == sizeof (int)) { + return (xdr_int(xdrs, (int *)(void *)ep)); + } else /* LINTED */ if (sizeof (enum sizecheck) == sizeof (short)) { + return (xdr_short(xdrs, (short *)(void *)ep)); + } else { + return (FALSE); + } } /* diff --git a/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/rpc/xdr.h b/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/rpc/xdr.h index fe38c4d12..2989ea115 100644 --- a/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/rpc/xdr.h +++ b/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/rpc/xdr.h @@ -292,8 +292,8 @@ extern bool_t xdr_long (XDR *__xdrs, long *__lp); extern bool_t xdr_u_long (XDR *__xdrs, unsigned long *__ulp); extern bool_t xdr_hyper (XDR *__xdrs, int64_t *__llp); extern bool_t xdr_u_hyper (XDR *__xdrs, uint64_t *__ullp); -extern bool_t xdr_longlong_t (XDR *__xdrs, int64_t *__llp); -extern bool_t xdr_u_longlong_t (XDR *__xdrs, uint64_t *__ullp); +extern bool_t xdr_longlong_t (XDR *__xdrs, long long *__llp); +extern bool_t xdr_u_longlong_t (XDR *__xdrs, unsigned long long *__ullp); extern bool_t xdr_int8_t (XDR *__xdrs, int8_t *__ip); extern bool_t xdr_uint8_t (XDR *__xdrs, uint8_t *__up); extern bool_t xdr_int16_t (XDR *__xdrs, int16_t *__ip); diff --git a/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/rpc/xdr_mem.c b/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/rpc/xdr_mem.c index ca69ed364..dac67ae3c 100644 --- a/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/rpc/xdr_mem.c +++ b/src/big/rt-smart/kernel/rt-thread/components/dfs/filesystems/nfs/rpc/xdr_mem.c @@ -57,6 +57,8 @@ static char sccsid[] = "@(#)xdr_mem.c 1.19 87/08/11 Copyr 1984 Sun Micro"; static bool_t xdrmem_getlong (XDR *, long *); static bool_t xdrmem_putlong (XDR *, const long *); +static bool_t xdrmem_getint32 (XDR *, unsigned int *); +static bool_t xdrmem_putint32 (XDR *, const unsigned int *); static bool_t xdrmem_getbytes (XDR *, char *, unsigned int); static bool_t xdrmem_putbytes (XDR *, const char *, unsigned int); static unsigned int xdrmem_getpos (const XDR *); @@ -73,8 +75,8 @@ static struct xdr_ops xdrmem_ops = { xdrmem_setpos, xdrmem_inline, xdrmem_destroy, - NULL, - NULL + xdrmem_getint32, + xdrmem_putint32 }; @@ -118,6 +120,28 @@ xdrmem_putlong (XDR *xdrs, const long *lp) return (TRUE); } +static bool_t +xdrmem_getint32 (XDR *xdrs, unsigned int *lp) +{ + if (xdrs->x_handy < sizeof(unsigned int)) return FALSE; + xdrs->x_handy -= sizeof(unsigned int); + + *lp = (unsigned int) ntohl((*((int32_t *) (xdrs->x_private)))); + xdrs->x_private += sizeof(unsigned int); + return TRUE; +} + +static bool_t +xdrmem_putint32 (XDR *xdrs, const unsigned int *lp) +{ + if (xdrs->x_handy < sizeof(unsigned int)) return FALSE; + xdrs->x_handy -= sizeof(unsigned int); + + *(int32_t *) xdrs->x_private = htonl(*lp); + xdrs->x_private += sizeof(unsigned int); + return (TRUE); +} + static bool_t xdrmem_getbytes (XDR *xdrs, char *addr, unsigned int len) { diff --git a/src/big/rt-smart/kernel/rt-thread/components/dfs/src/dfs.c b/src/big/rt-smart/kernel/rt-thread/components/dfs/src/dfs.c index ca2a16917..b83a718a3 100644 --- a/src/big/rt-smart/kernel/rt-thread/components/dfs/src/dfs.c +++ b/src/big/rt-smart/kernel/rt-thread/components/dfs/src/dfs.c @@ -912,6 +912,7 @@ MSH_CMD_EXPORT(lsof, list open files); */ int mount(int argc, char *argv[]) { + int ret = -1; if (argc == 1) /* display the mount history */ { struct dfs_filesystem *iter; @@ -936,7 +937,14 @@ int mount(int argc, char *argv[]) char *fstype = argv[3]; rt_kprintf("mount device %s(%s) onto %s ... ", device, fstype, path); - if (dfs_mount(device, path, fstype, 0, 0) == 0) +#ifdef RT_USING_DFS_NFS + if(strcmp(fstype, "nfs") == 0) + { + ret = dfs_mount(RT_NULL, path, fstype, 0, device); + } else +#endif + ret = dfs_mount(device, path, fstype, 0, 0); + if (ret == 0) { rt_kprintf("succeed!\n"); return 0; diff --git a/src/big/rt-smart/kernel/rt-thread/components/drivers/Kconfig b/src/big/rt-smart/kernel/rt-thread/components/drivers/Kconfig index 78df75ee6..b7dd8f233 100644 --- a/src/big/rt-smart/kernel/rt-thread/components/drivers/Kconfig +++ b/src/big/rt-smart/kernel/rt-thread/components/drivers/Kconfig @@ -226,6 +226,11 @@ config RT_USING_RTC endif endif + +config RT_USING_HARDLOCK + bool "Using hardlock drivers" + default y + config RT_USING_SDIO bool "Using SD/MMC device drivers" default n diff --git a/src/big/rt-smart/kernel/rt-thread/components/lwp/lwp.c b/src/big/rt-smart/kernel/rt-thread/components/lwp/lwp.c index 4cdde30c7..f7953eb3e 100644 --- a/src/big/rt-smart/kernel/rt-thread/components/lwp/lwp.c +++ b/src/big/rt-smart/kernel/rt-thread/components/lwp/lwp.c @@ -1050,16 +1050,24 @@ static void lwp_copy_stdio_fdt(struct rt_lwp *lwp) lwp_fdt = &lwp->fdt; /* init 4 fds */ - lwp_fdt->fds = rt_calloc(4, sizeof(void *)); + lwp_fdt->fds = rt_calloc(8, sizeof(void *)); if (lwp_fdt->fds) { - lwp_fdt->maxfd = 4; + lwp_fdt->maxfd = 8; d = fd_get(0); fd_associate(lwp_fdt, 0, d); d = fd_get(1); fd_associate(lwp_fdt, 1, d); d = fd_get(2); fd_associate(lwp_fdt, 2, d); + d = fd_get(3); + fd_associate(lwp_fdt, 3, d); + d = fd_get(4); + fd_associate(lwp_fdt, 4, d); + d = fd_get(5); + fd_associate(lwp_fdt, 5, d); + d = fd_get(6); + fd_associate(lwp_fdt, 6, d); } return; diff --git a/src/big/rt-smart/kernel/rt-thread/components/net/lwip-2.1.2/src/api/sockets.c b/src/big/rt-smart/kernel/rt-thread/components/net/lwip-2.1.2/src/api/sockets.c index 85e5ad1bc..a721a82a9 100644 --- a/src/big/rt-smart/kernel/rt-thread/components/net/lwip-2.1.2/src/api/sockets.c +++ b/src/big/rt-smart/kernel/rt-thread/components/net/lwip-2.1.2/src/api/sockets.c @@ -156,7 +156,7 @@ static void sockaddr_to_ipaddr_port(const struct sockaddr *sockaddr, ip_addr_t * IS_SOCK_ADDR_TYPE_VALID(name)) #define SOCK_ADDR_TYPE_MATCH_OR_UNSPEC(name, sock) (((name)->sa_family == AF_UNSPEC) || \ SOCK_ADDR_TYPE_MATCH(name, sock)) -#define IS_SOCK_ADDR_ALIGNED(name) ((((mem_ptr_t)(name)) % 4) == 0) +#define IS_SOCK_ADDR_ALIGNED(name) ((((mem_ptr_t)(name)) % 1) == 0) #define LWIP_SOCKOPT_CHECK_OPTLEN(sock, optlen, opttype) do { if ((optlen) < sizeof(opttype)) { done_socket(sock); return EINVAL; }}while(0) diff --git a/src/big/rt-smart/kernel/rt-thread/components/net/lwip-2.1.2/src/arch/sys_arch.c b/src/big/rt-smart/kernel/rt-thread/components/net/lwip-2.1.2/src/arch/sys_arch.c index 6d353d026..4f9796e49 100644 --- a/src/big/rt-smart/kernel/rt-thread/components/net/lwip-2.1.2/src/arch/sys_arch.c +++ b/src/big/rt-smart/kernel/rt-thread/components/net/lwip-2.1.2/src/arch/sys_arch.c @@ -731,12 +731,12 @@ void *mem_trim(void *mem, mem_size_t size) void *mem_malloc(mem_size_t size) { - return rt_malloc(size); + return rt_malloc_align(size, MEM_ALIGNMENT); } void mem_free(void *mem) { - rt_free(mem); + rt_free_align(mem); } #ifdef RT_LWIP_PPP diff --git a/src/big/rt-smart/kernel/rt-thread/components/net/lwip-2.1.2/src/lwipopts.h b/src/big/rt-smart/kernel/rt-thread/components/net/lwip-2.1.2/src/lwipopts.h index a0d9cad46..81355af65 100644 --- a/src/big/rt-smart/kernel/rt-thread/components/net/lwip-2.1.2/src/lwipopts.h +++ b/src/big/rt-smart/kernel/rt-thread/components/net/lwip-2.1.2/src/lwipopts.h @@ -661,5 +661,6 @@ #define TFTP_MAX_FILENAME_LEN 64 #endif - +#define MEMCPY(dst,src,len) rt_memcpy(dst,src,len) +#define SMEMCPY(dst,src,len) rt_memcpy(dst,src,len) #endif /* __LWIPOPTS_H__ */ diff --git a/src/big/rt-smart/kernel/rt-thread/components/net/sal_socket/socket/net_sockets.c b/src/big/rt-smart/kernel/rt-thread/components/net/sal_socket/socket/net_sockets.c index 1bdd983b1..e48edaf03 100644 --- a/src/big/rt-smart/kernel/rt-thread/components/net/sal_socket/socket/net_sockets.c +++ b/src/big/rt-smart/kernel/rt-thread/components/net/sal_socket/socket/net_sockets.c @@ -323,7 +323,7 @@ int closesocket(int s) error = -1; } - rt_free(d->fnode); + // rt_free(d->fnode); /* socket has been closed, delete it from file system fd */ fd_release(s); diff --git a/src/big/rt-smart/kernel/rt-thread/include/rthw.h b/src/big/rt-smart/kernel/rt-thread/include/rthw.h index 6f7bbd665..572569bc1 100644 --- a/src/big/rt-smart/kernel/rt-thread/include/rthw.h +++ b/src/big/rt-smart/kernel/rt-thread/include/rthw.h @@ -41,7 +41,7 @@ extern "C" { #endif #ifndef RT_CPU_CACHE_LINE_SZ -#define RT_CPU_CACHE_LINE_SZ 32 +#define RT_CPU_CACHE_LINE_SZ 64 #endif enum RT_HW_CACHE_OPS diff --git a/src/big/rt-smart/tools/mkromfs.py b/src/big/rt-smart/tools/mkromfs.py index d47474870..41b5785c3 100644 --- a/src/big/rt-smart/tools/mkromfs.py +++ b/src/big/rt-smart/tools/mkromfs.py @@ -67,6 +67,7 @@ def mkromfs_dir(dirname, is_root = False): mkromfs_output('const struct romfs_dirent _root_dirent[] = {\n') mkromfs_output(('#ifdef RT_USING_DFS_DEVFS\n\t{ROMFS_DIRENT_DIR, "dev", RT_NULL, 0},\n#endif\n')) mkromfs_output(('#ifdef RT_USING_SDIO\n\t{ROMFS_DIRENT_DIR, "sdcard", RT_NULL, 0},\n#endif\n')) + mkromfs_output(('#ifdef RT_USING_DFS_NFS\n\t{ROMFS_DIRENT_DIR, "nfs", RT_NULL, 0},\n#endif\n')) mkromfs_output(('#ifdef RT_USING_PROC\n\t{ROMFS_DIRENT_DIR, "proc", RT_NULL, 0},\n#endif\n')) mkromfs_output(('#ifdef RT_USING_DFS_SHAREFS\n\t{ROMFS_DIRENT_DIR, "sharefs", RT_NULL, 0},\n#endif\n')) else: diff --git a/src/big/rt-smart/userapps/sdk/rt-thread/include/rthw.h b/src/big/rt-smart/userapps/sdk/rt-thread/include/rthw.h index e5f04ce5f..12893d20e 100644 --- a/src/big/rt-smart/userapps/sdk/rt-thread/include/rthw.h +++ b/src/big/rt-smart/userapps/sdk/rt-thread/include/rthw.h @@ -44,7 +44,7 @@ extern "C" { int cacheflush(void *addr, int size, int cache); #ifndef RT_CPU_CACHE_LINE_SZ -#define RT_CPU_CACHE_LINE_SZ 32 +#define RT_CPU_CACHE_LINE_SZ 64 #endif enum RT_HW_CACHE_OPS diff --git a/src/common/cdk/user/component/datafifo/host/lib/libdatafifo.a b/src/common/cdk/user/component/datafifo/host/lib/libdatafifo.a index a0fa1a776b77d06977296593c28a20d0446ca2dd..69e50c2d1d67bbf1ec43e18dbd9ebc69c8398202 100644 GIT binary patch delta 49 ucmZo#FW9tRaDp_ug|V@Lg{8$tC3i*`ySad|y?_yfnShvidjTVhP#6GJMhv|G delta 49 ucmZo#FW9tRaDp_uv7woTse#ExC3i*`ySad|y?_yfnShvidjTVhP#6GGfDEMo diff --git a/src/common/cdk/user/component/datafifo/slave/lib/libdatafifo.a b/src/common/cdk/user/component/datafifo/slave/lib/libdatafifo.a index de8fea5fd3d09b9d516b398b9a39e87c4c29b125..45b86f7a85391c862f54cf39332abe473127c36b 100644 GIT binary patch delta 33 icmccggz?f7#tG8w7RJT~7M2zpmE0L&?9By?j|u?7v%g|V@Lg{8$trPoYQw)tcSO|i{d%=~IFfz1w@bJ<}kCoecJzWKMo Oym>Hz%?r*y5&{66h8Uy( delta 80 zcmZoV%G`96d4e>%v7woTse$oErPoX__GAZ5vCUe{{Aw_P%?_G#* @@ -181,5 +182,24 @@ k_s32 kd_mapi_sensor_exposure_time_get(k_s32 fd, k_sensor_intg_time *exp_time) printf("kd_mapi_sensor_exposure_time_get failed\n"); } memcpy(exp_time, &exp_opt.exp_time, sizeof(k_sensor_intg_time)); + return ret; +} + + +k_s32 kd_mapi_sensor_otpdata_get(k_s32 sensor_type, k_sensor_otp_date *otp_data) +{ + msg_sensor_otp_opt_t sensor_otp; + k_s32 ret = 0; + + sensor_otp.sensor_type = sensor_type; + memcpy(&sensor_otp.otp_data, otp_data, sizeof(k_sensor_otp_date)); + + ret = mapi_send_sync(MODFD(K_MAPI_MOD_SENSOR, 0, 0), MSG_CMD_MEDIA_SENSOR_OTP_GET, + &sensor_otp, sizeof(sensor_otp), NULL); + if(ret != K_SUCCESS) { + printf("kd_mpi_sensor_otpdata_get failed\n"); + } + memcpy(otp_data, &sensor_otp.otp_data, sizeof(k_sensor_otp_date)); + return ret; } \ No newline at end of file diff --git a/src/common/cdk/user/mapi/mediaserver/msg_server/msg_server_ao.c b/src/common/cdk/user/mapi/mediaserver/msg_server/msg_server_ao.c index 1e0779dae..e1f3f1075 100644 --- a/src/common/cdk/user/mapi/mediaserver/msg_server/msg_server_ao.c +++ b/src/common/cdk/user/mapi/mediaserver/msg_server/msg_server_ao.c @@ -180,6 +180,27 @@ k_s32 msg_ao_unmute(k_s32 id, k_ipcmsg_message_t *msg) k_s32 msg_ao_send_frame(k_s32 id, k_ipcmsg_message_t *msg) { + k_s32 ret; + k_ipcmsg_message_t *resp_msg; + k_msg_ao_frame_t* ao_frame = msg->pBody; + + ret = kd_mapi_ao_send_frame(ao_frame->ao_hdl,&ao_frame->audio_frame); + if(ret != K_SUCCESS) { + mapi_ao_error_trace("%s failed:0x%x\n",__FUNCTION__ ,ret); + } + + resp_msg = kd_ipcmsg_create_resp_message(msg, ret, NULL,0); + if(resp_msg == NULL) { + mapi_ao_error_trace("kd_ipcmsg_create_resp_message failed\n"); + return K_FAILED; + } + + ret = kd_ipcmsg_send_async(id, resp_msg, NULL); + if(ret != K_SUCCESS) { + mapi_ao_error_trace(" kd_ipcmsg_send_async failed:%x\n", ret); + } + kd_ipcmsg_destroy_message(resp_msg); + return K_SUCCESS; } diff --git a/src/common/cdk/user/mapi/mediaserver/msg_server/msg_server_sensor.c b/src/common/cdk/user/mapi/mediaserver/msg_server/msg_server_sensor.c index 9957fb35a..023534f23 100644 --- a/src/common/cdk/user/mapi/mediaserver/msg_server/msg_server_sensor.c +++ b/src/common/cdk/user/mapi/mediaserver/msg_server/msg_server_sensor.c @@ -179,6 +179,33 @@ k_s32 msg_sensor_exposure_time_get(k_s32 id, k_ipcmsg_message_t *msg) return K_SUCCESS; } + +k_s32 msg_sensor_otp_get(k_s32 id, k_ipcmsg_message_t *msg) +{ + k_s32 ret = 0; + k_ipcmsg_message_t *resp_msg; + msg_sensor_otp_opt_t *sensor_otp = msg->pBody; + + ret = kd_mapi_sensor_otpdata_get(sensor_otp->sensor_type, &sensor_otp->otp_data); + if(ret != K_SUCCESS) { + mapi_sensor_error_trace("msg_sensor_otp_get failed:0x%x\n", ret); + } + resp_msg = kd_ipcmsg_create_resp_message(msg, ret, msg->pBody, sizeof(msg_sensor_otp_opt_t)); + if(resp_msg == NULL) { + mapi_sensor_error_trace("kd_ipcmsg_create_resp_message failed\n"); + return K_FAILED; + } + + ret = kd_ipcmsg_send_async(id, resp_msg, NULL); + if(ret != K_SUCCESS) { + mapi_sensor_error_trace(" kd_ipcmsg_send_async failed:%x\n", ret); + } + kd_ipcmsg_destroy_message(resp_msg); + + return K_SUCCESS; +} + + static msg_module_cmd_t g_module_cmd_table[] = { {MSG_CMD_MEDIA_SENSOR_REG_READ, msg_sensor_reg_read}, {MSG_CMD_MEDIA_SENSOR_REG_WRITE, msg_sensor_reg_write}, @@ -186,6 +213,8 @@ static msg_module_cmd_t g_module_cmd_table[] = { {MSG_CMD_MEDIA_SENSOR_EXPOSURE_GET, msg_sensor_exposure_time_get}, {MSG_CMD_MEDIA_SENSOR_AGAIN_SET, msg_sensor_again_set}, {MSG_CMD_MEDIA_SENSOR_AGAIN_GET, msg_sensor_again_get}, + {MSG_CMD_MEDIA_SENSOR_OTP_GET, msg_sensor_otp_get}, + }; msg_server_module_t g_module_sensor = { diff --git a/src/common/cdk/user/mapi/mediaserver/sensor/mapi_sensor_server.c b/src/common/cdk/user/mapi/mediaserver/sensor/mapi_sensor_server.c index 1cbb55b7f..a8313d4c2 100644 --- a/src/common/cdk/user/mapi/mediaserver/sensor/mapi_sensor_server.c +++ b/src/common/cdk/user/mapi/mediaserver/sensor/mapi_sensor_server.c @@ -118,3 +118,36 @@ k_s32 kd_mapi_sensor_exposure_time_get(k_s32 fd, k_sensor_intg_time *exp_time) } return K_SUCCESS; } + + +k_s32 kd_mapi_sensor_otpdata_get(k_s32 sensor_type, k_sensor_otp_date *otp_data) +{ + k_s32 ret = 0; + k_s32 sensor_fd = -1; + k_sensor_mode mode; + k_vicap_sensor_info sensor_info; + k_sensor_otp_date read_otp_data; + + memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); + memcpy(&read_otp_data, otp_data, sizeof(k_sensor_otp_date)); + + CHECK_MAPI_SENSOR_NULL_PTR("otp_data", otp_data); + + ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); + + sensor_fd = kd_mpi_sensor_open(sensor_info.sensor_name); + if (sensor_fd < 0) { + printf("%s, sensor open failed.\n", __func__); + return -1; + } + + ret = kd_mpi_sensor_otpdata_get(sensor_fd, &read_otp_data); + if (ret) { + printf("%s, sensor stream on failed.\n", __func__); + return -1; + } + + memcpy(otp_data, &read_otp_data, sizeof(k_sensor_otp_date)); + + return 0; +} \ No newline at end of file diff --git a/src/common/cdk/user/mapi/sample/sample_audio/mapi_audio_sample.c b/src/common/cdk/user/mapi/sample/sample_audio/mapi_audio_sample.c index 15e169f15..5a5d222f1 100644 --- a/src/common/cdk/user/mapi/sample/sample_audio/mapi_audio_sample.c +++ b/src/common/cdk/user/mapi/sample/sample_audio/mapi_audio_sample.c @@ -962,5 +962,99 @@ k_s32 audio_mapi_sample_audio_double_loopback(k_u32 sample_rate,k_u32 channels,k return -1; } + return 0; +} + + +#include "pcm_data.h" +#include "wav_ctrl.h" +static k_s32 _get_audio_frame(k_audio_frame *audio_frame, int nSize) +{ + k_u32 pool_id; + kd_mapi_sys_get_vb_block(&pool_id,&audio_frame->phys_addr,nSize,NULL); + + audio_frame->virt_addr = _sys_mmap(audio_frame->phys_addr,nSize); + audio_frame->len = nSize; + + return K_SUCCESS; +} + +static k_s32 _release_audio_frame(k_audio_frame *audio_frame) +{ + kd_mapi_sys_release_vb_block(audio_frame->phys_addr, audio_frame->len); +#if 1 + _sys_munmap(audio_frame->phys_addr,audio_frame->virt_addr,audio_frame->len); +#endif + + return 0; +} + +k_s32 audio_mapi_sample_play_wav(const char* filename) +{ + k_s32 ret; + k_handle ao_hdl = 0; + int audio_channel = 0; + int audio_samplerate = 0; + int audio_bitpersample = 0; + + + if (0 != load_wav_info(filename, &audio_channel, &audio_samplerate, &audio_bitpersample)) + { + return -1; + } + + ret = _mapi_sample_vb_init(K_TRUE, 48000); + if (ret != K_SUCCESS) + { + printf("audio_sample_vb_init failed\n"); + return -1; + } + + k_audio_frame audio_frame; + if (32 == audio_bitpersample) + { + _get_audio_frame(&audio_frame, audio_samplerate * 4 * 2 / AUDIO_PERSEC_DIV_NUM); + } + else if (24 == audio_bitpersample) + { + _get_audio_frame(&audio_frame, audio_samplerate * 3 * 2 / AUDIO_PERSEC_DIV_NUM); + } + else if (16 == audio_bitpersample) + { + _get_audio_frame(&audio_frame, audio_samplerate * 2 * 2 / AUDIO_PERSEC_DIV_NUM); + } + + k_u32 *pDataBuf = (k_u32 *)audio_frame.virt_addr; + memset(pDataBuf, 0, audio_frame.len); + + g_enable_audio_codec = K_TRUE; + ret = _init_ao(KD_AUDIO_BIT_WIDTH_16,audio_samplerate,audio_channel,K_STANDARD_MODE,&ao_hdl); + if(ret != K_SUCCESS) { + printf("_init_ao error: %x\n", ret); + return -1; + } + + while (1) + { + // 获取音频数据 + if (get_pcm_data_from_file(pDataBuf, audio_frame.len / 4) < 0) + { + break; + } + + // 发送音频数据 + ret = kd_mapi_ao_send_frame(ao_hdl, &audio_frame); + } + usleep(1000*100); + + ret = _deinit_ao(ao_hdl); + if(ret != K_SUCCESS) { + printf("_deinit_ao error: %x\n", ret); + return -1; + } + + _release_audio_frame(&audio_frame); + + _mapi_sample_vb_deinit(); return 0; } \ No newline at end of file diff --git a/src/common/cdk/user/mapi/sample/sample_audio/mapi_audio_sample.h b/src/common/cdk/user/mapi/sample/sample_audio/mapi_audio_sample.h index 93fe6f785..7114cdb3a 100644 --- a/src/common/cdk/user/mapi/sample/sample_audio/mapi_audio_sample.h +++ b/src/common/cdk/user/mapi/sample/sample_audio/mapi_audio_sample.h @@ -36,6 +36,7 @@ k_s32 audio_mapi_sample_ai_aenc(k_u32 sample_rate,k_u32 channels,k_bool enable_a k_s32 audio_mapi_sample_adec_ao(k_u32 sample_rate,k_u32 channels,k_bool enable_audio_codec,const char* filename); k_s32 audio_mapi_sample_audio_loopback(k_u32 sample_rate,k_u32 channels); k_s32 audio_mapi_sample_audio_double_loopback(k_u32 sample_rate,k_u32 channels,k_bool enable_audio_codec); +k_s32 audio_mapi_sample_play_wav(const char* filename); #ifdef __cplusplus } diff --git a/src/common/cdk/user/mapi/sample/sample_audio/pcm_data.c b/src/common/cdk/user/mapi/sample/sample_audio/pcm_data.c new file mode 100644 index 000000000..0aa5ff11e --- /dev/null +++ b/src/common/cdk/user/mapi/sample/sample_audio/pcm_data.c @@ -0,0 +1,125 @@ +/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "pcm_data.h" +#include +#include +#include +#include "wav_ctrl.h" + +static k_u32 *g_pcm_file_data = NULL; +static k_u32 g_pcm_file_len = 0; +static k_u32 g_pcm_file_index = 0; + + +static int g_bitpersample = 0; +static int g_wav_headlen = 0; +static char g_wav_filename[256]; + + + +static k_s32 _load_file(const char*filename) +{ + unsigned char *pcm_file_data = NULL; + FILE *fp = fopen(filename, "rb"); + if (NULL == fp) + { + printf("open file:%s failed\n", filename); + return -1; + } + + fseek(fp, 0, SEEK_END); + int size = ftell(fp); + pcm_file_data = (unsigned char *)malloc(size); + if (pcm_file_data == NULL) + { + printf("malloc size %d failed\n", size); + return -1; + } + + fseek(fp, 0, SEEK_SET); + fread(pcm_file_data, size, 1, fp); + fclose(fp); + g_pcm_file_len = size - g_wav_headlen; + + g_pcm_file_data = (k_u32 *)(pcm_file_data + g_wav_headlen); + + printf("open file:%s ok,file size:%d,data size:%d,wav header size:%d\n", filename, size,g_pcm_file_len,(int)g_wav_headlen); + + return 0; +} + + +static k_s32 _get_bit_pcm_data_from_file(const char*filename,k_u32 *pdata, k_u32 data_len) +{ + if (g_pcm_file_index + data_len > g_pcm_file_len/4) + { + g_pcm_file_index = 0; + return -1; + } + + + for (unsigned int i = 0; i < data_len; i ++) + { + /*if (g_pcm_file_index == 0) + { + printf("========0x%x_0x%x_0x%x_0x%x_0x%x_0x%x_0x%x_0x%x_0x%x_0x%x\n",\ + g_pcm_file_data[0],g_pcm_file_data[1],g_pcm_file_data[2],g_pcm_file_data[3],g_pcm_file_data[4],\ + g_pcm_file_data[5],g_pcm_file_data[6],g_pcm_file_data[7],g_pcm_file_data[8],g_pcm_file_data[9]); + }*/ + pdata[i] = g_pcm_file_data[g_pcm_file_index++]; + if (g_pcm_file_index >= g_pcm_file_len / 4) + { + g_pcm_file_index = 0; + return -1; + } + } + return 0; +} + + +k_s32 load_wav_info(const char*filename,int* channel,int* samplerate,int* bitpersample) +{ + int header_len = 0; + int data_len = 0; + read_wav_header(filename,&header_len,&data_len,channel,samplerate,bitpersample); + printf("read_wav_info:headerlen:%d,channel:%d,samplerate:%d,bitpersample:%d\n",\ + header_len,*channel,*samplerate,*bitpersample); + + g_wav_headlen = header_len; + g_bitpersample = *bitpersample; + memcpy(g_wav_filename,filename,strlen(filename)+1); + + if (0 != _load_file(filename)) + { + return -1; + } + return 0; +} + +k_s32 get_pcm_data_from_file(k_u32 *pdata, k_u32 data_len) +{ + return _get_bit_pcm_data_from_file(g_wav_filename,pdata,data_len); +} \ No newline at end of file diff --git a/src/common/cdk/user/mapi/sample/sample_audio/pcm_data.h b/src/common/cdk/user/mapi/sample/sample_audio/pcm_data.h new file mode 100644 index 000000000..c1d91e06a --- /dev/null +++ b/src/common/cdk/user/mapi/sample/sample_audio/pcm_data.h @@ -0,0 +1,45 @@ +/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __AUDIO_PCM_32DATA_H__ +#define __AUDIO_PCM_32DATA_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* end of #ifdef __cplusplus */ + +#include "k_type.h" +#include "k_audio_comm.h" + +k_s32 load_wav_info(const char*filename,int* channel,int* samplerate,int* bitpersample); +k_s32 get_pcm_data_from_file(k_u32 *pdata, k_u32 data_len); + +#ifdef __cplusplus +} +#endif /* end of #ifdef __cplusplus */ + +#endif + + diff --git a/src/common/cdk/user/mapi/sample/sample_audio/sample_audio.c b/src/common/cdk/user/mapi/sample/sample_audio/sample_audio.c index f11e27a1a..ee06e3400 100755 --- a/src/common/cdk/user/mapi/sample/sample_audio/sample_audio.c +++ b/src/common/cdk/user/mapi/sample/sample_audio/sample_audio.c @@ -47,6 +47,7 @@ static void _help() printf(" type 0:sample ai->aenc module\n"); printf(" type 1:sample adec->ao module\n"); printf(" type 2:sample ai->aenc adec->ao loopback module\n"); + printf(" type 3:play wav\n"); //printf(" type 3:sample double loopback module\n"); printf("-samplerate: set audio sample(8000 ~ 192000)\n"); @@ -112,6 +113,10 @@ int main(int argc, char *argv[]) { audio_mapi_sample_audio_loopback(g_sample_rate,g_channels); } + else if (3 == g_type) + { + audio_mapi_sample_play_wav(g_file_name); + } #if 0 else if (3 == g_type) { diff --git a/src/common/cdk/user/mapi/sample/sample_audio/wav_ctrl.c b/src/common/cdk/user/mapi/sample/sample_audio/wav_ctrl.c new file mode 100644 index 000000000..5d380b099 --- /dev/null +++ b/src/common/cdk/user/mapi/sample/sample_audio/wav_ctrl.c @@ -0,0 +1,147 @@ +/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "wav_ctrl.h" +#include +#include +#include + + +#include +#include +#include + +int read_wav_header(const char *filename, int *header_len, int *data_len,int* channel,int* samplerate,int* bitpersample) { + FILE *fp = fopen(filename, "rb"); + if (!fp) { + fprintf(stderr, "Failed to open file: %s\n", filename); + return -1; + } + + char chunk_id[5]; + k_u32 chunk_size; + char format[5]; + + // 读取RIFF chunk + fread(chunk_id, 1, 4, fp); + chunk_id[4] = '\0'; + fread(&chunk_size, 4, 1, fp); + fread(format, 1, 4, fp); + format[4] = '\0'; + + // 读取fmt chunk + fread(chunk_id, 1, 4, fp); + fread(&chunk_size, 4, 1, fp); + k_u16 audio_format; + k_u16 num_channels; + k_u32 sample_rate; + k_u32 byte_rate; + k_u16 block_align; + k_u16 bits_per_sample; + fread(&audio_format, 2, 1, fp); + fread(&num_channels, 2, 1, fp); + fread(&sample_rate, 4, 1, fp); + fread(&byte_rate, 4, 1, fp); + fread(&block_align, 2, 1, fp); + fread(&bits_per_sample, 2, 1, fp); + + *channel = num_channels; + *samplerate = sample_rate; + *bitpersample = bits_per_sample; + + // 读取附加信息 + if (chunk_size > 16) { + fseek(fp, chunk_size - 16, SEEK_CUR); + } + + // 读取data chunk + while(1) + { + fread(chunk_id, 1, 4, fp); + if (strcmp(chunk_id,"data") !=0) + { + fseek(fp, -2L, SEEK_CUR); + continue; + } + fread(&chunk_size, 4, 1, fp); + // printf("chunk_id:%s,chunk_size:%d\n",chunk_id,chunk_size); + break; + } + + // 计算头信息长度和数据占用长度 + *header_len = ftell(fp); + *data_len = chunk_size; + + fclose(fp); + return 0; +} + + + +static WAV g_wav_head; +k_s32 load_wav_head(const char* filename,int* channel,int* samplerate,int* bitpersample,int* total_sample_size) +{ + FILE* file = fopen(filename, "rb"); + if (!file) { + printf("Could not open file %s\n", filename); + return -1; + } + fread(&g_wav_head, 1, sizeof(g_wav_head), file); + fclose(file); + + if (0 != memcmp(g_wav_head.riff.RIFF_type, "WAVE",sizeof(g_wav_head.riff.RIFF_type)) || 0 != memcmp(g_wav_head.riff.RIFF_id, "RIFF",sizeof(g_wav_head.riff.RIFF_id))) + { + printf("Error: WAV file format not recognized\n"); + return -1; + } + + *channel = g_wav_head.fmt.FMT_numChannels; + *samplerate = g_wav_head.fmt.FMT_sampleRate; + *bitpersample = g_wav_head.fmt.FMT_bitsPerSample; + *total_sample_size = g_wav_head.data.DATA_size; + return 0; +} + +void set_wav_head(int channel,int samplerate,int bitpersample,int total_sample_size,k_u8 *audio_header) +{ + memcpy(g_wav_head.riff.RIFF_id,"RIFF",sizeof(g_wav_head.riff.RIFF_id)); + memcpy(g_wav_head.riff.RIFF_type,"WAVE",sizeof(g_wav_head.riff.RIFF_type)); + //g_wav_head.riff.RIFF_size = total_sample_size; + g_wav_head.riff.RIFF_size = total_sample_size - 8; + + memcpy(g_wav_head.fmt.FMT_id,"fmt ",sizeof(g_wav_head.fmt.FMT_id)); + g_wav_head.fmt.FMT_size = 16; + g_wav_head.fmt.FMT_auioFormat = 1; + g_wav_head.fmt.FMT_numChannels = channel; + g_wav_head.fmt.FMT_sampleRate = samplerate; + g_wav_head.fmt.FMT_byteRate = samplerate*channel*bitpersample/8; + g_wav_head.fmt.FMT_blockAlign = channel*bitpersample/8; + g_wav_head.fmt.FMT_bitsPerSample = bitpersample; + + memcpy(g_wav_head.data.DATA_id,"data",sizeof(g_wav_head.data.DATA_id)); + g_wav_head.data.DATA_size = total_sample_size-sizeof(WAV); + + memcpy(audio_header,&g_wav_head,sizeof(g_wav_head)); +} diff --git a/src/common/cdk/user/mapi/sample/sample_audio/wav_ctrl.h b/src/common/cdk/user/mapi/sample/sample_audio/wav_ctrl.h new file mode 100644 index 000000000..8eae50b38 --- /dev/null +++ b/src/common/cdk/user/mapi/sample/sample_audio/wav_ctrl.h @@ -0,0 +1,76 @@ +/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __AUDIO_WAV_CTRL_H__ +#define __AUDIO_WAV_CTRL_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* end of #ifdef __cplusplus */ + +#include "k_type.h" +#include "k_audio_comm.h" + +typedef struct WAV_RIFF +{ + k_s8 RIFF_id[4]; + k_u32 RIFF_size; + k_s8 RIFF_type[4]; +} RIFF_t; + +typedef struct WAV_FMT +{ + k_s8 FMT_id[4]; + k_u32 FMT_size; + k_u16 FMT_auioFormat; + k_u16 FMT_numChannels; + k_u32 FMT_sampleRate; + k_u32 FMT_byteRate; + k_u16 FMT_blockAlign; + k_u16 FMT_bitsPerSample; +} FMT_t; + +typedef struct WAV_data +{ + k_s8 DATA_id[4]; + k_u32 DATA_size; +} Data_t; + + +typedef struct WAV_fotmat +{ + RIFF_t riff; + FMT_t fmt; + Data_t data; +} WAV; + +void set_wav_head(int channel,int samplerate,int bitpersample,int total_sample_size,k_u8 *audio_header); +k_s32 load_wav_head(const char* filename,int* channel,int* samplerate,int* bitpersample,int* total_sample_size); +int read_wav_header(const char *filename, int *header_len, int *data_len,int* channel,int* samplerate,int* bitpersample); +#ifdef __cplusplus +} +#endif /* end of #ifdef __cplusplus */ + +#endif diff --git a/src/common/cdk/user/mapi/sample/sample_dpu_uvc/sample_dpu.c b/src/common/cdk/user/mapi/sample/sample_dpu_uvc/sample_dpu.c index c07962440..757944668 100755 --- a/src/common/cdk/user/mapi/sample/sample_dpu_uvc/sample_dpu.c +++ b/src/common/cdk/user/mapi/sample/sample_dpu_uvc/sample_dpu.c @@ -796,6 +796,7 @@ static k_s32 sample_dpu_vicap_init(vicap_device_obj *dev_obj) static void do_transfer_frame_data(unsigned char* pdata,int len,unsigned int frame_number, unsigned long pts,float temperature,int frame_start_code,int frame_total_cnt,int frame_total_size,int cur_cnt) { + static int get_node_failed_cnt = 0; uvc_cache_t *uvc_cache = uvc_cache_get(); UVC_PRIVATE_DATA_HEAD_INFO private_head_info; int head_len = sizeof(UVC_PRIVATE_DATA_HEAD_INFO); @@ -823,6 +824,12 @@ static void do_transfer_frame_data(unsigned char* pdata,int len,unsigned int fra } else { + printf("get_node_from_queue failed cnt:%d\n",get_node_failed_cnt++); + if (get_node_failed_cnt > 100) + { + printf("restart the system ...\n"); + system("reboot"); + } return; } } diff --git a/src/common/cdk/user/mapi/sample/sample_vicap/sample_vicap.c b/src/common/cdk/user/mapi/sample/sample_vicap/sample_vicap.c index 4ea8eafec..7e504b6ff 100755 --- a/src/common/cdk/user/mapi/sample/sample_vicap/sample_vicap.c +++ b/src/common/cdk/user/mapi/sample/sample_vicap/sample_vicap.c @@ -179,6 +179,8 @@ static k_vicap_sensor_type get_sensor_type(k_u16 sensor) return IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_MCLK_7425_LINEAR; case 8: return IMX335_MIPI_4LANE_RAW12_2592X1944_30FPS_MCLK_7425_LINEAR; + case 9: + return OV_OV9286_MIPI_1280X720_30FPS_10BIT_MCLK_25M_LINEAR_SPECKLE_V2; default: printf("unsupport sensor type %d, use default IMX335_MIPI_2LANE_RAW12_1920X1080_30FPS_LINEAR\n", sensor); return IMX335_MIPI_2LANE_RAW12_1920X1080_30FPS_LINEAR; @@ -627,6 +629,12 @@ int main(int argc, char * const argv[]) printf("vicap start isp %d...\n", i); } } + // get optdate + // k_sensor_otp_date otp_date; + + // memset(&otp_date, 0, sizeof(otp_date)); + // kd_mapi_sensor_otpdata_get(OV_OV9286_MIPI_1280X720_30FPS_10BIT_MCLK_25M_LINEAR_SPECKLE_V2, &otp_date); + // printf("otp date is %s \n", otp_date.otp_date); // dump test k_video_frame dump_vf_info; diff --git a/src/little/buildroot-ext/Config.in b/src/little/buildroot-ext/Config.in index 4aa62e8fb..3b291bc55 100644 --- a/src/little/buildroot-ext/Config.in +++ b/src/little/buildroot-ext/Config.in @@ -20,3 +20,4 @@ source "$BR2_EXTERNAL_K230_PATH/package/crypto_test/Config.in" source "$BR2_EXTERNAL_K230_PATH/package/k230_timer/Config.in" source "$BR2_EXTERNAL_K230_PATH/package/ws2812/Config.in" source "$BR2_EXTERNAL_K230_PATH/package/mvx_player/Config.in" +#source "$BR2_EXTERNAL_K230_PATH/package/ffmpeg_canaan/Config.in" diff --git a/src/little/buildroot-ext/configs/k230_evb_defconfig b/src/little/buildroot-ext/configs/k230_evb_defconfig index 0bc05094a..9f484395a 100644 --- a/src/little/buildroot-ext/configs/k230_evb_defconfig +++ b/src/little/buildroot-ext/configs/k230_evb_defconfig @@ -87,4 +87,5 @@ BR2_PACKAGE_TOUCH_EMU=y BR2_PACKAGE_CRYPTO_TEST=y BR2_PACKAGE_K230_TIMER=y BR2_PACKAGE_MVX_PLAYER=y -BR2_PACKAGE_EVTEST=y \ No newline at end of file +# BR2_PACKAGE_FFMPEG_CANAAN=y +BR2_PACKAGE_EVTEST=y diff --git a/src/little/buildroot-ext/package/ffmpeg_canaan/0001-buildroot-ffmpeg.patch b/src/little/buildroot-ext/package/ffmpeg_canaan/0001-buildroot-ffmpeg.patch new file mode 100644 index 000000000..11be5d35e --- /dev/null +++ b/src/little/buildroot-ext/package/ffmpeg_canaan/0001-buildroot-ffmpeg.patch @@ -0,0 +1,102 @@ +Index: b/configure +=================================================================== +--- a/configure ++++ b/configure +@@ -3255,6 +3255,8 @@ hevc_vaapi_encoder_select="atsc_a53 cbs_ + hevc_v4l2m2m_decoder_deps="v4l2_m2m hevc_v4l2_m2m" + hevc_v4l2m2m_decoder_select="hevc_mp4toannexb_bsf" + hevc_v4l2m2m_encoder_deps="v4l2_m2m hevc_v4l2_m2m" ++mjpeg_v4l2m2m_decoder_deps="v4l2_m2m mjpeg_v4l2_m2m" ++mjpeg_v4l2m2m_encoder_deps="v4l2_m2m mjpeg_v4l2_m2m" + mjpeg_cuvid_decoder_deps="cuvid" + mjpeg_qsv_decoder_select="qsvdec" + mjpeg_qsv_encoder_deps="libmfx" +@@ -6988,6 +6990,7 @@ if enabled v4l2_m2m; then + check_cc h264_v4l2_m2m linux/videodev2.h "int i = V4L2_PIX_FMT_H264;" + check_cc vp8_v4l2_m2m linux/videodev2.h "int i = V4L2_PIX_FMT_VP8;" + check_cc vp9_v4l2_m2m linux/videodev2.h "int i = V4L2_PIX_FMT_VP9;" ++ check_cc mjpeg_v4l2_m2m linux/videodev2.h "int i = V4L2_PIX_FMT_MJPEG;" + fi + + check_headers sys/videoio.h +Index: b/libavcodec/allcodecs.c +=================================================================== +--- a/libavcodec/allcodecs.c ++++ b/libavcodec/allcodecs.c +@@ -867,6 +867,8 @@ extern const FFCodec ff_hevc_qsv_encoder + extern const FFCodec ff_hevc_v4l2m2m_encoder; + extern const FFCodec ff_hevc_vaapi_encoder; + extern const FFCodec ff_hevc_videotoolbox_encoder; ++extern const FFCodec ff_mjpeg_v4l2m2m_encoder; ++extern const FFCodec ff_mjpeg_v4l2m2m_decoder; + extern const FFCodec ff_libkvazaar_encoder; + extern const FFCodec ff_mjpeg_cuvid_decoder; + extern const FFCodec ff_mjpeg_qsv_encoder; +Index: b/libavcodec/v4l2_buffers.c +=================================================================== +--- a/libavcodec/v4l2_buffers.c ++++ b/libavcodec/v4l2_buffers.c +@@ -385,7 +385,7 @@ static int v4l2_buffer_swframe_to_buf(co + h = AV_CEIL_RSHIFT(h, desc->log2_chroma_h); + } + size = frame->linesize[i] * h; +- ret = v4l2_bufref_to_buf(out, 0, frame->data[i], size, offset); ++ ret = v4l2_bufref_to_buf(out, i, frame->data[i], size, 0); + if (ret) + return ret; + offset += size; +Index: b/libavcodec/v4l2_context.c +=================================================================== +--- a/libavcodec/v4l2_context.c ++++ b/libavcodec/v4l2_context.c +@@ -395,6 +395,18 @@ dequeue: + return NULL; + } + ++ if(!V4L2_TYPE_IS_OUTPUT(ctx->type) && ++ ctx->av_codec_id == AV_CODEC_ID_RAWVIDEO && ++ ((buf.flags & 0x30000000) == 0)) ++ { ++ ret = ioctl(ctx_to_m2mctx(ctx)->fd, VIDIOC_QBUF, &buf); ++ if (ret) { ++ av_log(logger(ctx), AV_LOG_DEBUG, "%s VIDIOC_QBUF, errno (%s)\n", ++ ctx->name, av_err2str(AVERROR(errno))); ++ } ++ goto start; ++ } ++ + if (ctx_to_m2mctx(ctx)->draining && !V4L2_TYPE_IS_OUTPUT(ctx->type)) { + int bytesused = V4L2_TYPE_IS_MULTIPLANAR(buf.type) ? + buf.m.planes[0].bytesused : buf.bytesused; +@@ -508,6 +520,11 @@ static int v4l2_get_raw_format(V4L2Conte + return AVERROR(EINVAL); + + pixfmt = ff_v4l2_format_v4l2_to_avfmt(fdesc.pixelformat, AV_CODEC_ID_RAWVIDEO); ++ if (pixfmt == AV_PIX_FMT_NONE){ ++ fdesc.index++; ++ continue; ++ } ++ + ret = v4l2_try_raw_format(ctx, pixfmt); + if (ret){ + fdesc.index++; +Index: b/libavcodec/v4l2_m2m_dec.c +=================================================================== +--- a/libavcodec/v4l2_m2m_dec.c ++++ b/libavcodec/v4l2_m2m_dec.c +@@ -266,3 +266,5 @@ M2MDEC(h263, "H.263", AV_CODEC_ID_H263, + M2MDEC(vc1 , "VC1", AV_CODEC_ID_VC1, NULL); + M2MDEC(vp8, "VP8", AV_CODEC_ID_VP8, NULL); + M2MDEC(vp9, "VP9", AV_CODEC_ID_VP9, NULL); ++M2MDEC(mjpeg, "MJPEG", AV_CODEC_ID_MJPEG, NULL); ++ +Index: b/libavcodec/v4l2_m2m_enc.c +=================================================================== +--- a/libavcodec/v4l2_m2m_enc.c ++++ b/libavcodec/v4l2_m2m_enc.c +@@ -443,3 +443,5 @@ M2MENC(h263, "H.263", options, AV_ + M2MENC(h264, "H.264", options, AV_CODEC_ID_H264); + M2MENC(hevc, "HEVC", options, AV_CODEC_ID_HEVC); + M2MENC(vp8, "VP8", options, AV_CODEC_ID_VP8); ++M2MENC(mjpeg, "MJPEG", options, AV_CODEC_ID_MJPEG); ++ diff --git a/src/little/buildroot-ext/package/ffmpeg_canaan/Config.in b/src/little/buildroot-ext/package/ffmpeg_canaan/Config.in new file mode 100755 index 000000000..26499950d --- /dev/null +++ b/src/little/buildroot-ext/package/ffmpeg_canaan/Config.in @@ -0,0 +1,177 @@ +config BR2_PACKAGE_FFMPEG_CANAAN + bool "ffmpeg app" + depends on BR2_riscv + help + k510 ffmpeg app + +menuconfig BR2_PACKAGE_FFMPEG_CANAAN + bool "ffmpeg" + depends on BR2_PACKAGE_FFMPEG_CANAAN_ARCH_SUPPORTS + help + FFmpeg is a complete, cross-platform solution to record, + convert and stream audio and video. + + http://www.ffmpeg.org + +if BR2_PACKAGE_FFMPEG_CANAAN + +config BR2_PACKAGE_FFMPEG_CANAAN_GPL + bool "Enable GPL code" + help + allow use of GPL code, the resulting libs and binaries will + be under GPL + +config BR2_PACKAGE_FFMPEG_CANAAN_NONFREE + bool "Enable nonfree code" + help + allow use of nonfree code, the resulting libs and binaries + will be unredistributable + +config BR2_PACKAGE_FFMPEG_CANAAN_FFMPEG_CANAAN + bool "Build ffmpeg (the command line application)" + default y + help + FFmpeg is a very fast video and audio converter. + It can also grab from a live audio/video source. + + It is not needed if you want to link the FFmpeg libraries + to your application. + +config BR2_PACKAGE_FFMPEG_CANAAN_FFPLAY + bool "Build ffplay" + depends on !BR2_STATIC_LIBS # sdl2 + select BR2_PACKAGE_FFMPEG_CANAAN_SWSCALE + select BR2_PACKAGE_SDL2 + help + FFplay is a very simple and portable media player using the + FFmpeg libraries and the SDL library. + It is mostly used as a testbed for the various FFmpeg APIs. + +comment "ffplay needs a toolchain w/ dynamic library" + depends on BR2_STATIC_LIBS + +config BR2_PACKAGE_FFMPEG_CANAAN_FFPROBE + bool "Build ffprobe" + help + FFprobe is a utility to determine the audio and video + characteristics of a container file. + +config BR2_PACKAGE_FFMPEG_CANAAN_XCBGRAB + bool "Build X11 screen grabbing" + depends on BR2_PACKAGE_XORG7 + select BR2_PACKAGE_LIBXCB + help + X11 screen grabbing using libxcb. + +config BR2_PACKAGE_FFMPEG_CANAAN_AVRESAMPLE + bool "Build libavresample" + help + Avresample is a audio conversion library for compatibility. + +config BR2_PACKAGE_FFMPEG_CANAAN_POSTPROC + bool "Build libpostproc" + depends on BR2_PACKAGE_FFMPEG_CANAAN_GPL + help + Postproc is a library of video postprocessing routines. + +config BR2_PACKAGE_FFMPEG_CANAAN_SWSCALE + bool "Build libswscale" + help + Swscale is a library of video scaling routines. + +config BR2_PACKAGE_FFMPEG_CANAAN_ENCODERS + string "Enabled encoders" + default "all" + help + Space-separated list of encoders to build in FFmpeg, + or "all" to build all of them. + + Run ./configure --list-encoders in the ffmpeg sources + directory to know the available options. + +config BR2_PACKAGE_FFMPEG_CANAAN_DECODERS + string "Enabled decoders" + default "all" + help + Space-separated list of decoders to build in FFmpeg, + or "all" to build all of them. + + Run ./configure --list-decoders in the ffmpeg sources + directory to know the available options. + +config BR2_PACKAGE_FFMPEG_CANAAN_MUXERS + string "Enabled muxers" + default "all" + help + Space-separated list of muxers to build in FFmpeg, + or "all" to build all of them. + + Run ./configure --list-muxers in the ffmpeg sources + directory to know the available options. + +config BR2_PACKAGE_FFMPEG_CANAAN_DEMUXERS + string "Enabled demuxers" + default "all" + help + Space-separated list of demuxers to build in FFmpeg, + or "all" to build all of them. + + Run ./configure --list-demuxers in the ffmpeg sources + directory to know the available options. + +config BR2_PACKAGE_FFMPEG_CANAAN_PARSERS + string "Enabled parsers" + default "all" + help + Space-separated list of parsers to build in FFmpeg, + or "all" to build all of them. + + Run ./configure --list-parsers in the ffmpeg sources + directory to know the available options. + +config BR2_PACKAGE_FFMPEG_CANAAN_BSFS + string "Enabled bitstreams" + default "all" + help + Space-separated list of bitstream filters to build in FFmpeg, + or "all" to build all of them. + + Run ./configure --list-bsfs in the ffmpeg sources + directory to know the available options. + +config BR2_PACKAGE_FFMPEG_CANAAN_PROTOCOLS + string "Enabled protocols" + default "all" + help + Space-separated list of protocols to build in FFmpeg, + or "all" to build all of them. + + Run ./configure --list-protocols in the ffmpeg sources + directory to know the available options. + +config BR2_PACKAGE_FFMPEG_CANAAN_FILTERS + string "Enabled filters" + default "all" + help + Space-separated list of filters to build in FFmpeg, + or "all" to build all of them. + + Run ./configure --list-filters in the ffmpeg sources + directory to know the available options. + +config BR2_PACKAGE_FFMPEG_CANAAN_INDEVS + bool "Enable input devices" + default y + +config BR2_PACKAGE_FFMPEG_CANAAN_OUTDEVS + bool "Enable output devices" + default y + +config BR2_PACKAGE_FFMPEG_CANAAN_EXTRACONF + string "Additional parameters for ./configure" + default "" + help + Extra parameters that will be appended to FFmpeg's + ./configure commandline. + +endif diff --git a/src/little/buildroot-ext/package/ffmpeg_canaan/ffmpeg.mk b/src/little/buildroot-ext/package/ffmpeg_canaan/ffmpeg.mk new file mode 100755 index 000000000..7b6d8814f --- /dev/null +++ b/src/little/buildroot-ext/package/ffmpeg_canaan/ffmpeg.mk @@ -0,0 +1,75 @@ +################################################################################ +# +# ffmpeg +# +################################################################################ + +FFMPEG_CANAAN_VERSION = 6.1 +FFMPEG_CANAAN_SOURCE = ffmpeg-$(FFMPEG_CANAAN_VERSION).tar.xz +FFMPEG_CANAAN_SITE = http://ffmpeg.org/releases +FFMPEG_CANAAN_INSTALL_STAGING = YES + +FFMPEG_CANAAN_LICENSE = LGPL-2.1+, libjpeg license +FFMPEG_CANAAN_LICENSE_FILES = LICENSE.md COPYING.LGPLv2.1 +ifeq ($(BR2_PACKAGE_FFMPEG_CANAAN_GPL),y) +FFMPEG_CANAAN_LICENSE += and GPL-2.0+ +FFMPEG_CANAAN_LICENSE_FILES += COPYING.GPLv2 +endif + +FFMPEG_CANAAN_DEPENDENCIES += host-pkgconf + +FFMPEG_CANAAN_CONF_ENV += CFLAGS="$(FFMPEG_CANAAN_CFLAGS)" +FFMPEG_CANAAN_CONF_OPTS += $(call qstrip,$(BR2_PACKAGE_FFMPEG_CANAAN_EXTRACONF)) + +# Override FFMPEG_CANAAN_CONFIGURE_CMDS: FFmpeg does not support --target and others +define FFMPEG_CANAAN_CONFIGURE_CMDS + (cd $(FFMPEG_CANAAN_SRCDIR) && rm -rf config.cache && \ + $(TARGET_CONFIGURE_OPTS) \ + $(TARGET_CONFIGURE_ARGS) \ + $(FFMPEG_CANAAN_CONF_ENV) \ + ./configure \ + --cross-prefix=riscv64-unknown-linux-gnu- \ + --enable-cross-compile \ + --target-os=linux \ + --cc="$(TARGET_CC)" \ + --arch=riscv64 \ + --libdir="/lib64/" \ + --disable-asm \ + --disable-x86asm \ + --disable-static \ + --enable-shared \ + --disable-autodetect \ + --disable-ffplay \ + --disable-ffprobe \ + --disable-doc \ + --disable-debug \ + --disable-symver \ + --disable-htmlpages \ + --disable-manpages \ + --disable-podpages \ + --disable-txtpages \ + --disable-postproc \ + --disable-encoders \ + --disable-decoders \ + --enable-v4l2_m2m \ + --enable-indev=v4l2 \ + --enable-encoder=h264_v4l2m2m \ + --enable-encoder=hevc_v4l2m2m \ + --enable-encoder=mjpeg_v4l2m2m \ + --enable-encoder=mpeg2video \ + --enable-encoder=aac \ + --enable-encoder=pcm_alaw \ + --enable-encoder=rawvideo \ + --enable-decoder=h264_v4l2m2m \ + --enable-decoder=hevc_v4l2m2m \ + --enable-decoder=mjpeg_v4l2m2m \ + --enable-decoder=mpeg2video \ + --enable-decoder=aac \ + --enable-decoder=pcm_alaw \ + --enable-decoder=rawvideo \ + ) +endef + +FFMPEG_CANAAN_POST_INSTALL_TARGET_HOOKS += FFMPEG_CANAAN_REMOVE_EXAMPLE_SRC_FILES + +$(eval $(autotools-package)) diff --git a/src/little/linux/arch/riscv/boot/dts/kendryte/clock_consumer.dtsi b/src/little/linux/arch/riscv/boot/dts/kendryte/clock_consumer.dtsi index 598d29f7a..441eaa8a6 100755 --- a/src/little/linux/arch/riscv/boot/dts/kendryte/clock_consumer.dtsi +++ b/src/little/linux/arch/riscv/boot/dts/kendryte/clock_consumer.dtsi @@ -87,3 +87,17 @@ clocks = <&audio_dev_clk>; clock-names = "i2sclk"; }; + +&i2s { + clocks = <&audio_dev_clk>; + clock-names = "i2sclk"; +}; + +&pdma { + clocks = <&pdma_aclk_gate>; +}; + +&inno_codec { + clocks = <&codec_adc_mclk>,<&codec_dac_mclk>; + clock-names = "adc", "dac"; +}; diff --git a/src/little/linux/arch/riscv/boot/dts/kendryte/k230.dtsi b/src/little/linux/arch/riscv/boot/dts/kendryte/k230.dtsi index 919fc7889..203a608a6 100755 --- a/src/little/linux/arch/riscv/boot/dts/kendryte/k230.dtsi +++ b/src/little/linux/arch/riscv/boot/dts/kendryte/k230.dtsi @@ -234,6 +234,39 @@ interrupts = <132>; }; + /* peri dma */ + pdma: pdma@80804000 { + #dma-cells = <4>; + dma-channels = <8>; + dma-requests = <35>; + status = "okay"; + compatible = "canaan,k230-pdma"; + reg = <0x0 0x80804000 0x0 0x400>; + interrupt-parent = <&intc>; + /*interrupts = <139>,<196>,<197>,<198>,<199>,<200>,<201>,<202>;*/ + interrupts = <203>; + }; + + i2s: i2s@0x9140f000 { + status = "okay"; + compatible = "snps,designware-i2s"; + reg = <0x0 0x9140f000 0x0 0x400>; + dmas = <&pdma 1 0xfff 0 0x14>, <&pdma 1 0xfff 0 0x15>; + dma-names = "tx", "rx"; + }; + + /* audio */ + audio: audio@0x9140f400 { + status = "okay"; + compatible = "canaan,k230-audio"; + reg = <0x0 0x9140f400 0x0 0xc00>; + }; + + inno_codec:inno_codec@0x9140e000{ + status = "okay"; + compatible = "k230,inno-codec"; + reg = <0x0 0x9140e000 0x0 0x1000>; + }; pmu_thead: pmu_thead { interrupt-parent = <&cpu0_intc>; diff --git a/src/little/linux/arch/riscv/boot/dts/kendryte/k230_canmv.dts b/src/little/linux/arch/riscv/boot/dts/kendryte/k230_canmv.dts index 4a42003f8..702592d34 100755 --- a/src/little/linux/arch/riscv/boot/dts/kendryte/k230_canmv.dts +++ b/src/little/linux/arch/riscv/boot/dts/kendryte/k230_canmv.dts @@ -26,6 +26,14 @@ linux,initrd-end = <0x0 0x0>; stdout-path = "serial0:115200"; }; + + sound { + status = "disable"; + compatible = "canaan,k230-audio-inno"; + canaan,model = "CANAAN_K230_I2S_INNO"; + canaan,k230-i2s-controller = <&i2s>; + canaan,k230-audio-codec = <&inno_codec>; + }; }; &ddr { reg = <0x0 0x8200000 0x0 0x7dff000>; /*linux memory config*/ @@ -104,7 +112,7 @@ &mmc_sd0{ status = "okay"; io_fixed_1v8; - rx_delay_line = <0x00>; + rx_delay_line = <0x0d>; tx_delay_line = <0x00>; bcmdhd_wlan { compatible = "android,bcmdhd_wlan"; diff --git a/src/little/linux/arch/riscv/boot/dts/kendryte/k230_canmv_01studio.dts b/src/little/linux/arch/riscv/boot/dts/kendryte/k230_canmv_01studio.dts index 344c7373e..22f2e34fd 100755 --- a/src/little/linux/arch/riscv/boot/dts/kendryte/k230_canmv_01studio.dts +++ b/src/little/linux/arch/riscv/boot/dts/kendryte/k230_canmv_01studio.dts @@ -44,7 +44,7 @@ status = "okay"; no-1-8-v; cap-sd-highspeed; - rx_delay_line = <0x00>; + rx_delay_line = <0x0d>; tx_delay_line = <0xb0>; }; @@ -66,7 +66,7 @@ &gpio23 { status = "okay"; }; - +/* // conflict with HDMI &i2c3 { status = "okay"; touchscreen@38 { @@ -77,3 +77,4 @@ reset-gpios = <&port22 0 GPIO_ACTIVE_LOW>; }; }; +*/ \ No newline at end of file diff --git a/src/little/linux/arch/riscv/boot/dts/kendryte/k230_canmv_dongshanpi.dts b/src/little/linux/arch/riscv/boot/dts/kendryte/k230_canmv_dongshanpi.dts new file mode 100755 index 000000000..d36691548 --- /dev/null +++ b/src/little/linux/arch/riscv/boot/dts/kendryte/k230_canmv_dongshanpi.dts @@ -0,0 +1,78 @@ +/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ +#include "k230.dtsi" +#include "clock_provider.dtsi" /* k230 soc clock tree */ +#include "clock_consumer.dtsi" /* k230 soc clock consumer */ +#include "reset_provider.dtsi" /* k230 soc reset provider */ +#include "reset_consumer.dtsi" /* k230 soc reset consumer */ +#include "power_provider.dtsi" /* k230 soc power provider */ +#include "power_consumer.dtsi" /* k230 soc power consumer */ +#include "gpio_provider.dtsi" /* k230 soc gpio provider */ +#include "gpio_consumer.dtsi" /* k230 soc gpio consumer */ + + +/ { + aliases { + serial0 = &uart0; + }; + + chosen { + bootargs = ""; + linux,initrd-start = <0x0 0xa100000>; + linux,initrd-end = <0x0 0x0>; + stdout-path = "serial0:115200"; + }; +}; +&ddr { + reg = <0x0 0x8200000 0x0 0x7dff000>; /*linux memory config*/ +}; + +&usbotg0 { + status = "okay"; +}; + +&usbotg1 { + dr_mode = "host"; + status = "okay"; +}; + +&mmc_sd0{ + status = "okay"; + io_fixed_1v8; + rx_delay_line = <0x0d>; + tx_delay_line = <0x40>; +}; + +&mmc_sd1{ + status = "okay"; + no-1-8-v; + cap-sd-highspeed; + mshc_ctrl_r = <0x00>; +}; + +&uart0 { + status = "okay"; +}; + +&gpio23 { + status = "okay"; +}; + +&gpio24 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + touchscreen@38 { + compatible = "edt,edt-ft5306"; + reg = <0x38>; + interrupt-parent = <&port23>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&port24 0 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/src/little/linux/arch/riscv/boot/dts/kendryte/k230_canmv_v2.dts b/src/little/linux/arch/riscv/boot/dts/kendryte/k230_canmv_v2.dts index 17c59ce1b..046b84e16 100755 --- a/src/little/linux/arch/riscv/boot/dts/kendryte/k230_canmv_v2.dts +++ b/src/little/linux/arch/riscv/boot/dts/kendryte/k230_canmv_v2.dts @@ -26,6 +26,14 @@ linux,initrd-end = <0x0 0x0>; stdout-path = "serial0:115200"; }; + + sound { + status = "disable"; + compatible = "canaan,k230-audio-inno"; + canaan,model = "CANAAN_K230_I2S_INNO"; + canaan,k230-i2s-controller = <&i2s>; + canaan,k230-audio-codec = <&inno_codec>; + }; }; &ddr { reg = <0x0 0x8200000 0x0 0x7dff000>; /*linux memory config*/ @@ -42,7 +50,7 @@ &mmc_sd0{ status = "okay"; - rx_delay_line = <0x00>; + rx_delay_line = <0x0d>; tx_delay_line = <0xc0>; }; diff --git a/src/little/linux/arch/riscv/boot/dts/kendryte/k230_evb.dts b/src/little/linux/arch/riscv/boot/dts/kendryte/k230_evb.dts index 25e8e1ca1..567a1ff47 100755 --- a/src/little/linux/arch/riscv/boot/dts/kendryte/k230_evb.dts +++ b/src/little/linux/arch/riscv/boot/dts/kendryte/k230_evb.dts @@ -26,6 +26,14 @@ linux,initrd-end = <0x0 0x0>; stdout-path = "serial0:115200"; }; + + sound { + status = "disable"; + compatible = "canaan,k230-audio-inno"; + canaan,model = "CANAAN_K230_I2S_INNO"; + canaan,k230-i2s-controller = <&i2s>; + canaan,k230-audio-codec = <&inno_codec>; + }; }; &ddr { reg = <0x0 0x8200000 0x0 0x7dff000>; /*linux memory config*/ diff --git a/src/little/linux/arch/riscv/boot/dts/kendryte/k230_evb_doorlock.dts b/src/little/linux/arch/riscv/boot/dts/kendryte/k230_evb_doorlock.dts index dfceef925..1b40de063 100755 --- a/src/little/linux/arch/riscv/boot/dts/kendryte/k230_evb_doorlock.dts +++ b/src/little/linux/arch/riscv/boot/dts/kendryte/k230_evb_doorlock.dts @@ -183,7 +183,7 @@ is_emmc; io_fixed_1v8; mmc-hs200-1_8v; - rx_delay_line = <0x00>; + rx_delay_line = <0x0d>; tx_delay_line = <0xc0>; }; diff --git a/src/little/linux/arch/riscv/boot/dts/kendryte/k230_peephole_device.dts b/src/little/linux/arch/riscv/boot/dts/kendryte/k230_peephole_device.dts index 05a2944a7..102754a18 100755 --- a/src/little/linux/arch/riscv/boot/dts/kendryte/k230_peephole_device.dts +++ b/src/little/linux/arch/riscv/boot/dts/kendryte/k230_peephole_device.dts @@ -183,7 +183,7 @@ is_emmc; io_fixed_1v8; mmc-hs200-1_8v; - rx_delay_line = <0x00>; + rx_delay_line = <0x0d>; tx_delay_line = <0xc0>; }; diff --git a/src/little/linux/arch/riscv/boot/dts/kendryte/k230d_canmv.dts b/src/little/linux/arch/riscv/boot/dts/kendryte/k230d_canmv.dts index ec4fe8c48..82e857c03 100755 --- a/src/little/linux/arch/riscv/boot/dts/kendryte/k230d_canmv.dts +++ b/src/little/linux/arch/riscv/boot/dts/kendryte/k230d_canmv.dts @@ -34,7 +34,7 @@ &mmc_sd0{ status = "okay"; - rx_delay_line = <0x00>; + rx_delay_line = <0x0d>; tx_delay_line = <0xc0>; }; diff --git a/src/little/linux/arch/riscv/configs/k230_canmv_dongshanpi_defconfig b/src/little/linux/arch/riscv/configs/k230_canmv_dongshanpi_defconfig new file mode 100755 index 000000000..e14b27f48 --- /dev/null +++ b/src/little/linux/arch/riscv/configs/k230_canmv_dongshanpi_defconfig @@ -0,0 +1,390 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_CGROUPS=y +CONFIG_CGROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUP_BPF=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +CONFIG_BPF_SYSCALL=y +CONFIG_PERF_EVENTS=y +CONFIG_SOC_THEAD=y +CONFIG_SMP=y +CONFIG_PM=y +CONFIG_KPROBES=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_ACORN_PARTITION=y +CONFIG_ACORN_PARTITION_CUMANA=y +CONFIG_ACORN_PARTITION_EESOX=y +CONFIG_ACORN_PARTITION_ICS=y +CONFIG_ACORN_PARTITION_ADFS=y +CONFIG_ACORN_PARTITION_POWERTEC=y +CONFIG_ACORN_PARTITION_RISCIX=y +CONFIG_AIX_PARTITION=y +CONFIG_OSF_PARTITION=y +CONFIG_AMIGA_PARTITION=y +CONFIG_ATARI_PARTITION=y +CONFIG_MAC_PARTITION=y +CONFIG_BSD_DISKLABEL=y +CONFIG_MINIX_SUBPARTITION=y +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_LDM_PARTITION=y +CONFIG_LDM_DEBUG=y +CONFIG_SGI_PARTITION=y +CONFIG_ULTRIX_PARTITION=y +CONFIG_SUN_PARTITION=y +CONFIG_KARMA_PARTITION=y +CONFIG_SYSV68_PARTITION=y +CONFIG_CMDLINE_PARTITION=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NETLINK_DIAG=y +CONFIG_CFG80211=y +# CONFIG_CFG80211_DEFAULT_PS is not set +# CONFIG_CFG80211_CRDA_SUPPORT is not set +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=y +CONFIG_NET_9P=y +CONFIG_NET_9P_VIRTIO=y +CONFIG_NET_9P_DEBUG=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_TESTS=m +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_SPI_NAND=y +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_VIRTIO_BLK=y +CONFIG_EEPROM_AT24=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_NETDEVICES=y +CONFIG_VIRTIO_NET=y +CONFIG_MACB=y +CONFIG_STMMAC_ETH=y +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_MARVELL_PHY=y +CONFIG_USB_CATC=y +CONFIG_USB_KAWETH=y +CONFIG_USB_PEGASUS=y +CONFIG_USB_RTL8150=y +CONFIG_USB_RTL8152=y +CONFIG_USB_LAN78XX=y +CONFIG_USB_USBNET=y +CONFIG_RTL8188FU=m +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_GOODIX=y +CONFIG_TOUCHSCREEN_EDT_FT5X06=y +# CONFIG_SERIO_SERPORT is not set +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=5 +CONFIG_SERIAL_8250_RUNTIME_UARTS=5 +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y +CONFIG_HVC_RISCV_SBI=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_VIRTIO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_DESIGNWARE_ICE=y +CONFIG_SPI=y +CONFIG_SPI_DEBUG=y +CONFIG_SPI_DESIGNWARE=y +CONFIG_SPI_DW_DMA=y +CONFIG_SPI_DW_MMIO=y +# CONFIG_PTP_1588_CLOCK is not set +CONFIG_GPIOLIB=y +CONFIG_DEBUG_GPIO=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_DWAPB=y +CONFIG_POWER_RESET=y +CONFIG_POWER_SUPPLY=y +# CONFIG_HWMON is not set +CONFIG_THERMAL=y +CONFIG_CANAAN_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_DW_WATCHDOG=y +# CONFIG_MEDIA_CEC_SUPPORT is not set +CONFIG_MEDIA_SUPPORT=y +# CONFIG_DVB_NET is not set +# CONFIG_DVB_DYNAMIC_MINORS is not set +# CONFIG_RADIO_ADAPTERS is not set +# CONFIG_CXD2880_SPI_DRV is not set +# CONFIG_MEDIA_TUNER_SIMPLE is not set +# CONFIG_MEDIA_TUNER_TDA18250 is not set +# CONFIG_MEDIA_TUNER_TDA8290 is not set +# CONFIG_MEDIA_TUNER_TDA827X is not set +# CONFIG_MEDIA_TUNER_TDA18271 is not set +# CONFIG_MEDIA_TUNER_TDA9887 is not set +# CONFIG_MEDIA_TUNER_TEA5761 is not set +# CONFIG_MEDIA_TUNER_TEA5767 is not set +# CONFIG_MEDIA_TUNER_MSI001 is not set +# CONFIG_MEDIA_TUNER_MT20XX is not set +# CONFIG_MEDIA_TUNER_MT2060 is not set +# CONFIG_MEDIA_TUNER_MT2063 is not set +# CONFIG_MEDIA_TUNER_MT2266 is not set +# CONFIG_MEDIA_TUNER_MT2131 is not set +# CONFIG_MEDIA_TUNER_QT1010 is not set +# CONFIG_MEDIA_TUNER_XC2028 is not set +# CONFIG_MEDIA_TUNER_XC5000 is not set +# CONFIG_MEDIA_TUNER_XC4000 is not set +# CONFIG_MEDIA_TUNER_MXL5005S is not set +# CONFIG_MEDIA_TUNER_MXL5007T is not set +# CONFIG_MEDIA_TUNER_MC44S803 is not set +# CONFIG_MEDIA_TUNER_MAX2165 is not set +# CONFIG_MEDIA_TUNER_TDA18218 is not set +# CONFIG_MEDIA_TUNER_FC0011 is not set +# CONFIG_MEDIA_TUNER_FC0012 is not set +# CONFIG_MEDIA_TUNER_FC0013 is not set +# CONFIG_MEDIA_TUNER_TDA18212 is not set +# CONFIG_MEDIA_TUNER_E4000 is not set +# CONFIG_MEDIA_TUNER_FC2580 is not set +# CONFIG_MEDIA_TUNER_M88RS6000T is not set +# CONFIG_MEDIA_TUNER_TUA9001 is not set +# CONFIG_MEDIA_TUNER_SI2157 is not set +# CONFIG_MEDIA_TUNER_IT913X is not set +# CONFIG_MEDIA_TUNER_R820T is not set +# CONFIG_MEDIA_TUNER_MXL301RF is not set +# CONFIG_MEDIA_TUNER_QM1D1C0042 is not set +# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set +# CONFIG_DVB_STB0899 is not set +# CONFIG_DVB_STB6100 is not set +# CONFIG_DVB_STV090x is not set +# CONFIG_DVB_STV0910 is not set +# CONFIG_DVB_STV6110x is not set +# CONFIG_DVB_STV6111 is not set +# CONFIG_DVB_MXL5XX is not set +# CONFIG_DVB_M88DS3103 is not set +# CONFIG_DVB_DRXK is not set +# CONFIG_DVB_TDA18271C2DD is not set +# CONFIG_DVB_SI2165 is not set +# CONFIG_DVB_MN88472 is not set +# CONFIG_DVB_MN88473 is not set +# CONFIG_DVB_CX24110 is not set +# CONFIG_DVB_CX24123 is not set +# CONFIG_DVB_MT312 is not set +# CONFIG_DVB_ZL10036 is not set +# CONFIG_DVB_ZL10039 is not set +# CONFIG_DVB_S5H1420 is not set +# CONFIG_DVB_STV0288 is not set +# CONFIG_DVB_STB6000 is not set +# CONFIG_DVB_STV0299 is not set +# CONFIG_DVB_STV6110 is not set +# CONFIG_DVB_STV0900 is not set +# CONFIG_DVB_TDA8083 is not set +# CONFIG_DVB_TDA10086 is not set +# CONFIG_DVB_TDA8261 is not set +# CONFIG_DVB_VES1X93 is not set +# CONFIG_DVB_TUNER_ITD1000 is not set +# CONFIG_DVB_TUNER_CX24113 is not set +# CONFIG_DVB_TDA826X is not set +# CONFIG_DVB_TUA6100 is not set +# CONFIG_DVB_CX24116 is not set +# CONFIG_DVB_CX24117 is not set +# CONFIG_DVB_CX24120 is not set +# CONFIG_DVB_SI21XX is not set +# CONFIG_DVB_TS2020 is not set +# CONFIG_DVB_DS3000 is not set +# CONFIG_DVB_MB86A16 is not set +# CONFIG_DVB_TDA10071 is not set +# CONFIG_DVB_SP8870 is not set +# CONFIG_DVB_SP887X is not set +# CONFIG_DVB_CX22700 is not set +# CONFIG_DVB_CX22702 is not set +# CONFIG_DVB_S5H1432 is not set +# CONFIG_DVB_DRXD is not set +# CONFIG_DVB_L64781 is not set +# CONFIG_DVB_TDA1004X is not set +# CONFIG_DVB_NXT6000 is not set +# CONFIG_DVB_MT352 is not set +# CONFIG_DVB_ZL10353 is not set +# CONFIG_DVB_DIB3000MB is not set +# CONFIG_DVB_DIB3000MC is not set +# CONFIG_DVB_DIB7000M is not set +# CONFIG_DVB_DIB7000P is not set +# CONFIG_DVB_DIB9000 is not set +# CONFIG_DVB_TDA10048 is not set +# CONFIG_DVB_AF9013 is not set +# CONFIG_DVB_EC100 is not set +# CONFIG_DVB_STV0367 is not set +# CONFIG_DVB_CXD2820R is not set +# CONFIG_DVB_CXD2841ER is not set +# CONFIG_DVB_RTL2830 is not set +# CONFIG_DVB_RTL2832 is not set +# CONFIG_DVB_RTL2832_SDR is not set +# CONFIG_DVB_SI2168 is not set +# CONFIG_DVB_ZD1301_DEMOD is not set +# CONFIG_DVB_CXD2880 is not set +# CONFIG_DVB_VES1820 is not set +# CONFIG_DVB_TDA10021 is not set +# CONFIG_DVB_TDA10023 is not set +# CONFIG_DVB_STV0297 is not set +# CONFIG_DVB_NXT200X is not set +# CONFIG_DVB_OR51211 is not set +# CONFIG_DVB_OR51132 is not set +# CONFIG_DVB_BCM3510 is not set +# CONFIG_DVB_LGDT330X is not set +# CONFIG_DVB_LGDT3305 is not set +# CONFIG_DVB_LGDT3306A is not set +# CONFIG_DVB_LG2160 is not set +# CONFIG_DVB_S5H1409 is not set +# CONFIG_DVB_AU8522_DTV is not set +# CONFIG_DVB_AU8522_V4L is not set +# CONFIG_DVB_S5H1411 is not set +# CONFIG_DVB_S921 is not set +# CONFIG_DVB_DIB8000 is not set +# CONFIG_DVB_MB86A20S is not set +# CONFIG_DVB_TC90522 is not set +# CONFIG_DVB_MN88443X is not set +# CONFIG_DVB_PLL is not set +# CONFIG_DVB_TUNER_DIB0070 is not set +# CONFIG_DVB_TUNER_DIB0090 is not set +# CONFIG_DVB_DRX39XYJ is not set +# CONFIG_DVB_LNBH25 is not set +# CONFIG_DVB_LNBH29 is not set +# CONFIG_DVB_LNBP21 is not set +# CONFIG_DVB_LNBP22 is not set +# CONFIG_DVB_ISL6405 is not set +# CONFIG_DVB_ISL6421 is not set +# CONFIG_DVB_ISL6423 is not set +# CONFIG_DVB_A8293 is not set +# CONFIG_DVB_LGS8GL5 is not set +# CONFIG_DVB_LGS8GXX is not set +# CONFIG_DVB_ATBM8830 is not set +# CONFIG_DVB_TDA665x is not set +# CONFIG_DVB_IX2505V is not set +# CONFIG_DVB_M88RS2000 is not set +# CONFIG_DVB_AF9033 is not set +# CONFIG_DVB_HORUS3A is not set +# CONFIG_DVB_ASCOT2E is not set +# CONFIG_DVB_HELENE is not set +# CONFIG_DVB_CXD2099 is not set +# CONFIG_DVB_SP2 is not set +CONFIG_DRM=y +CONFIG_DRM_PANEL_CANAAN_UNIVERSAL=y +CONFIG_DRM_CANAAN=y +CONFIG_DRM_CANAAN_DSI=y +CONFIG_VG_LITE=m +CONFIG_FB_VIRTUAL=m +CONFIG_FB_SIMPLE=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_VGA_CONSOLE is not set +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_STORAGE=y +CONFIG_USB_DWC2=y +CONFIG_USB_TEST=m +CONFIG_USB_GADGET=y +CONFIG_USB_SNP_UDC_PLAT=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_CONFIGFS_F_UVC=y +CONFIG_MMC=y +CONFIG_MMC_TEST=y +CONFIG_MMC_DEBUG=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_OF_KENDRYTE=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_DMADEVICES=y +CONFIG_DW_AXI_DMAC=y +CONFIG_DMATEST=y +CONFIG_VIRTIO_BALLOON=y +CONFIG_VIRTIO_MMIO=y +CONFIG_IIO=y +CONFIG_PWM=y +CONFIG_PWM_K230=y +CONFIG_SIFIVE_PLIC=y +CONFIG_GENERIC_PHY=y +CONFIG_RAS=y +CONFIG_NVMEM_KENDRYTE_K230_OTP=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_UTF8=y +CONFIG_EXFAT_FS=y +CONFIG_NTFS_FS=y +CONFIG_NTFS_RW=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_HFS_FS=y +CONFIG_HFSPLUS_FS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_NFS_FS=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_9P_FS=y +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_9P_FS_SECURITY=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_936=y +CONFIG_NLS_CODEPAGE_1250=y +CONFIG_NLS_CODEPAGE_1251=y +CONFIG_NLS_ISO8859_1=y +CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity" +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_USER_API_HASH=y +CONFIG_CRYPTO_USER_API_AEAD=y +CONFIG_CRYPTO_DEV_VIRTIO=y +CONFIG_CRYPTO_DEV_CANAAN=y +CONFIG_CRYPTO_DEV_KENDRYTE_CRYP=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_INFO=y +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=60 +CONFIG_DEBUG_ATOMIC_SLEEP=y +# CONFIG_RCU_TRACE is not set diff --git a/src/little/linux/arch/riscv/include/asm/cacheflush.h b/src/little/linux/arch/riscv/include/asm/cacheflush.h index a4d3ce5b9..5b2f0071d 100644 --- a/src/little/linux/arch/riscv/include/asm/cacheflush.h +++ b/src/little/linux/arch/riscv/include/asm/cacheflush.h @@ -44,7 +44,7 @@ void flush_icache_mm(struct mm_struct *mm, bool local); void dma_wbinv_range(unsigned long start, unsigned long end); void dma_wb_range(unsigned long start, unsigned long end); - +void dma_inv_range(unsigned long start, unsigned long end); /* * Bits in sys_riscv_flush_icache()'s flags argument. */ diff --git a/src/little/linux/arch/riscv/mm/cacheflush.c b/src/little/linux/arch/riscv/mm/cacheflush.c index 6fd79bd54..92bcff60f 100644 --- a/src/little/linux/arch/riscv/mm/cacheflush.c +++ b/src/little/linux/arch/riscv/mm/cacheflush.c @@ -117,6 +117,19 @@ void dma_wb_range(unsigned long start, unsigned long end) sync_is(); } +void dma_inv_range(unsigned long start, unsigned long end) +{ + register unsigned long i asm("a0") = start & ~(L1_CACHE_BYTES - 1); + + if (!thead_dma_init_flag) + return; + + for (; i < end; i += L1_CACHE_BYTES) + asm volatile (".long 0x02a5000b"); /* dcache.ipa a0 */ + + sync_is(); +} + #define THEAD_VENDOR_ID 0x5b7 static int __init thead_dma_init(void) diff --git a/src/little/linux/arch/riscv/mm/dma-mapping.c b/src/little/linux/arch/riscv/mm/dma-mapping.c index e8acdce7d..41f0480ea 100644 --- a/src/little/linux/arch/riscv/mm/dma-mapping.c +++ b/src/little/linux/arch/riscv/mm/dma-mapping.c @@ -51,7 +51,7 @@ void arch_sync_dma_for_cpu(phys_addr_t paddr, size_t size, return; case DMA_FROM_DEVICE: case DMA_BIDIRECTIONAL: - cache_op(paddr, size, dma_wbinv_range); + cache_op(paddr, size, dma_inv_range); break; default: BUG(); diff --git a/src/little/linux/drivers/clk/canaan/clk-k230.c b/src/little/linux/drivers/clk/canaan/clk-k230.c index cc5669270..8b64dcb1d 100755 --- a/src/little/linux/drivers/clk/canaan/clk-k230.c +++ b/src/little/linux/drivers/clk/canaan/clk-k230.c @@ -32,6 +32,10 @@ #define CLK_IS_BASIC BIT(5) #define K230_CLK_DEBUG +#define K230_CLK_AUDIO_CLKDIV_OFFSET 0x34 +#define K230_CLK_PDM_CLKDIV_OFFSET 0x40 +#define K230_CLK_CODEC_ADC_MCLKDIV_OFFSET 0x38 +#define K230_CLK_CODEC_DAC_MCLKDIV_OFFSET 0x3c #undef K230_CLK_DEBUG static DEFINE_SPINLOCK(k230_clk_spinlock); @@ -53,6 +57,7 @@ struct k230_clk_composite { struct clk_hw hw; struct clk_lookup *cl; /* clock lookup by clk_get() api, if don't regist, please use __clk_lookup*/ struct clk_ops *ops; + void __iomem *base_reg; /* gate */ void __iomem *gate_reg; @@ -107,7 +112,7 @@ struct k230_clk_composite { //calculate the frequency division factor: // 0: 1/12, 2/12, 3/12, ....... -// 1: 1/1, 1/2, 1/3, ....... +// 1: 1/1, 1/2, 1/3, ....... // 2: x/y, ....... static unsigned long k230_clk_composite_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -128,7 +133,7 @@ static unsigned long k230_clk_composite_recalc_rate(struct clk_hw *hw, unsigned case 0: { spin_lock_irqsave(k230_composite->composite_spinlock,flags); reg_div = (readl(k230_composite->rate_reg) >> k230_composite->rate_div_shift) & k230_composite->rate_div_mask; - spin_unlock_irqrestore(k230_composite->composite_spinlock,flags); + spin_unlock_irqrestore(k230_composite->composite_spinlock,flags); rate_mul = reg_div + 1; rate_div = k230_composite->rate_div_max; break; @@ -195,14 +200,14 @@ static unsigned long POW(int a, int n) { /* Find the approximate value based on the parent node and the current node */ static int k230_clk_find_approximate(struct k230_clk_composite *k230_composite, - uint32_t mul_min, - uint32_t mul_max, - uint32_t div_min, - uint32_t div_max, + uint32_t mul_min, + uint32_t mul_max, + uint32_t div_min, + uint32_t div_max, uint32_t method, - unsigned long rate, + unsigned long rate, unsigned long parent_rate, - uint32_t *div, + uint32_t *div, uint32_t *mul) { long abs_min; @@ -319,7 +324,9 @@ static int k230_clk_find_approximate(struct k230_clk_composite *k230_composite, } /* mul and div can be changeable. */ case 2: { - if((0x91100038 == (k230_composite->rate_reg)) || (0x9110003c == (k230_composite->rate_reg))) + //if((0x91100038 == (k230_composite->rate_reg)) || (0x9110003c == (k230_composite->rate_reg))) + if (K230_CLK_CODEC_ADC_MCLKDIV_OFFSET == k230_composite->rate_reg - k230_composite->base_reg || \ + K230_CLK_CODEC_DAC_MCLKDIV_OFFSET == k230_composite->rate_reg - k230_composite->base_reg) { for(j=0;j<9;j++) { @@ -330,7 +337,9 @@ static int k230_clk_find_approximate(struct k230_clk_composite *k230_composite, } } } - else if((0x91100034 == (k230_composite->rate_reg)) || (0x91100040 == (k230_composite->rate_reg))) + //else if((0x91100034 == (k230_composite->rate_reg)) || (/*0x91100040*/0xffffffd0040d9034 == (k230_composite->rate_reg))) + else if (K230_CLK_AUDIO_CLKDIV_OFFSET == k230_composite->rate_reg - k230_composite->base_reg || \ + K230_CLK_PDM_CLKDIV_OFFSET == k230_composite->rate_reg - k230_composite->base_reg) { for(j=0;j<20;j++) { @@ -381,9 +390,9 @@ static int k230_clk_composite_set_rate(struct clk_hw *hw, unsigned long rate, un return -1; } - if(k230_clk_find_approximate(k230_composite, - k230_composite->rate_mul_min, - k230_composite->rate_mul_max, + if(k230_clk_find_approximate(k230_composite, + k230_composite->rate_mul_min, + k230_composite->rate_mul_max, k230_composite->rate_div_min, k230_composite->rate_div_max, k230_composite->rate_calc_method, @@ -511,7 +520,7 @@ static int k230_clk_composite_enable(struct clk_hw *hw) spin_unlock_irqrestore(k230_composite->composite_spinlock, flags); pr_info("[K230_CLK]:enable clk %s addr 0x%08x reg_value 0x%0x", clk_hw_get_name(hw), - (int)(long)k230_composite->gate_reg, + (int)(long)k230_composite->gate_reg, composite_gate_value); #endif return 0; @@ -544,7 +553,7 @@ static void k230_clk_composite_disable(struct clk_hw *hw) spin_unlock_irqrestore(k230_composite->composite_spinlock, flags); pr_info("[K230_CLK]:disable clk %s addr 0x%08x reg_value 0x%0x", clk_hw_get_name(hw), - (int)(long)k230_composite->gate_reg, + (int)(long)k230_composite->gate_reg, composite_gate_value); #endif } @@ -568,7 +577,7 @@ static int k230_clk_composite_set_parent(struct clk_hw *hw, u8 index) #ifdef K230_CLK_DEBUG pr_info("[K230_CLK]:set parent %s clk mux addr 0x%08x value 0x%08x shift %d mask 0x%08x return %d", clk_hw_get_name(hw), - (int)(long)k230_composite->mux_reg, + (int)(long)k230_composite->mux_reg, (int)composite_mux_value, k230_composite->mux_shift, k230_composite->mux_mask, @@ -590,7 +599,7 @@ static u8 k230_clk_composite_get_parent(struct clk_hw *hw) #ifdef K230_CLK_DEBUG pr_info("[K230_CLK]:get parent %s clk mux addr 0x%08x value 0x%08x shift %d mask 0x%08x return %d", clk_hw_get_name(hw), - (int)(long)k230_composite->mux_reg, + (int)(long)k230_composite->mux_reg, (int)composite_mux_value, k230_composite->mux_shift, k230_composite->mux_mask, @@ -645,6 +654,7 @@ static struct clk *_of_cannan_k230_clk_composite_setup(struct device_node *node) pr_err("[canaan_clk_err]:Could not kzalloc sruct k230_clk_composite.\n"); goto out_unmap; } + k230_clk_composite->base_reg = base_reg; if(of_property_read_u32(node, "clk-parent-reg-offset", &composite_reg_offset)) { mux = false; @@ -681,7 +691,7 @@ static struct clk *_of_cannan_k230_clk_composite_setup(struct device_node *node) (of_property_read_u32(node, "clk-rate-reg-write-enable-bit_1", &k230_clk_composite->rate_write_enable_bit_1))) { pr_err("[canaan_clk_err]:Parse composite node %s rate error.\n", node->name); goto free_k230_clk_composite; - } + } } else { @@ -828,8 +838,8 @@ static int canaan_k230_clk_composite_probe(struct platform_device *pdev) platform_set_drvdata(pdev, clk); -#ifdef K230_CLK_DEBUG - pr_info("[K230_CLK]:k230_clk_composite_probe ok!"); +#ifdef K230_CLK_DEBUG + pr_info("[K230_CLK]:k230_clk_composite_probe ok!"); #endif return 0; @@ -1074,11 +1084,11 @@ static struct clk * _of_canaan_k230_pll_clk_setup(struct device_node *node) /* parse divide */ if((of_property_read_u32(node, "clk-divide-reg-offset", &pll_reg_offset)) || - (of_property_read_u32(node, "clk-divide-out-reg-value-shift", &k230_clk_pll->pll_out_div_shift)) || - (of_property_read_u32(node, "clk-divide-out-reg-value-mask", &k230_clk_pll->pll_out_div_mask)) || - (of_property_read_u32(node, "clk-divide-ref-reg-value-shift", &k230_clk_pll->pll_ref_div_shift)) || - (of_property_read_u32(node, "clk-divide-ref-reg-value-mask", &k230_clk_pll->pll_ref_div_mask)) || - (of_property_read_u32(node, "clk-divide-fb-reg-value-shift", &k230_clk_pll->pll_fb_div_shift)) || + (of_property_read_u32(node, "clk-divide-out-reg-value-shift", &k230_clk_pll->pll_out_div_shift)) || + (of_property_read_u32(node, "clk-divide-out-reg-value-mask", &k230_clk_pll->pll_out_div_mask)) || + (of_property_read_u32(node, "clk-divide-ref-reg-value-shift", &k230_clk_pll->pll_ref_div_shift)) || + (of_property_read_u32(node, "clk-divide-ref-reg-value-mask", &k230_clk_pll->pll_ref_div_mask)) || + (of_property_read_u32(node, "clk-divide-fb-reg-value-shift", &k230_clk_pll->pll_fb_div_shift)) || (of_property_read_u32(node, "clk-divide-fb-reg-value-mask", &k230_clk_pll->pll_fb_div_mask))) { pr_err("[canaan_clk_err]:parse k230 pll divider error.\n"); goto free_k230_clk_pll; @@ -1218,7 +1228,7 @@ arch_initcall(canaan_k230_clk_pll_init_driver); static struct dentry *canaan_clk_debug_dir = NULL; /*--------------------------------------------------------------- - * for composite clks debug + * for composite clks debug * gate/rate/mux/..... * * @@ -1394,7 +1404,7 @@ static int composite_show_register_show(struct seq_file *s, void *data) seq_printf(s, " clk_enable: %s\n",((reg_value & (0x1 << k230_composite->gate_bit)) ^ k230_composite->gate_bit_reverse) ? "YES":"NO"); } else { seq_printf(s, " does not support gate!\n"); - } + } seq_printf(s,"-------------------------------------------------------------------------------\n\n"); seq_printf(s, "2. mux info:\n"); @@ -1488,7 +1498,7 @@ static int k230_debugfs_clk_composite_init(struct clk_hw *hw) } /*--------------------------------------------------------------- - * for pll clks debug + * for pll clks debug * * gate/rate * @@ -1587,7 +1597,7 @@ static int pll_show_register_show(struct seq_file *s, void *data) seq_printf(s, " freq = 24M * (fb_div+1) / (ref_div+1) / (out_div+1) = %d\n",24000000*(fb_div+1)/(ref_div+1)/(out_div+1)); seq_printf(s,"-------------------------------------------------------------------------------\n\n"); - + seq_printf(s, "2. status info:\n"); seq_printf(s, "-------------------------------------------------------------------------------\n"); reg_value = readl(k230_pll->pll_reg_bypass); diff --git a/src/little/linux/drivers/dma/Kconfig b/src/little/linux/drivers/dma/Kconfig index 90284ffda..5cb9daadb 100644 --- a/src/little/linux/drivers/dma/Kconfig +++ b/src/little/linux/drivers/dma/Kconfig @@ -390,7 +390,7 @@ config MOXART_DMA select DMA_VIRTUAL_CHANNELS help Enable support for the MOXA ART SoC DMA controller. - + Say Y here if you enabled MMP ADMA, otherwise say N. config MPC512X_DMA @@ -708,6 +708,13 @@ config ZX_DMA help Support the DMA engine for ZTE ZX family platform devices. +config K230_PERIDMA + tristate "K230 Periphal DMA support" + depends on ARCH_RV64I + select DMA_ENGINE + select DMA_VIRTUAL_CHANNELS + help + Enable support for the Periphal DMA controller present in the K230 SoC. # driver files source "drivers/dma/bestcomm/Kconfig" diff --git a/src/little/linux/drivers/dma/Makefile b/src/little/linux/drivers/dma/Makefile index 948a8da05..9224da82f 100644 --- a/src/little/linux/drivers/dma/Makefile +++ b/src/little/linux/drivers/dma/Makefile @@ -82,6 +82,7 @@ obj-$(CONFIG_XGENE_DMA) += xgene-dma.o obj-$(CONFIG_ZX_DMA) += zx_dma.o obj-$(CONFIG_ST_FDMA) += st_fdma.o obj-$(CONFIG_FSL_DPAA2_QDMA) += fsl-dpaa2-qdma/ +obj-$(CONFIG_K230_PERIDMA) += k230_peridma.o obj-y += mediatek/ obj-y += qcom/ diff --git a/src/little/linux/drivers/dma/k230_peridma.c b/src/little/linux/drivers/dma/k230_peridma.c new file mode 100755 index 000000000..b6ebaef3b --- /dev/null +++ b/src/little/linux/drivers/dma/k230_peridma.c @@ -0,0 +1,1419 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +//#define DEBUG +//#define VERBOSE_DEBUG + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "virt-dma.h" + +#define PDMA_MAX_LINE_SIZE 0x3FFFFFFF + +/* interrupt mask */ +#define PDONE_INT 0x00000001 +#define PITEM_INT 0x00000100 +#define PPAUSE_INT 0x00010000 +#define PTOUT_INT 0x01000000 + +/* llt structure */ +typedef struct pdma_llt +{ + u32 line_size : 30; + u32 pause : 1; + u32 node_intr : 1; + u32 src_addr; + u32 dst_addr; + u32 next_llt_addr; +} pdma_llt_t; + +/* register structure */ +typedef struct pdma_ch_cfg +{ + u32 ch_src_type : 1; + u32 ch_dev_hsize : 2; + u32 reserved0 : 1; + u32 ch_dat_endian : 2; + u32 reserved1 : 2; + u32 ch_dev_blen : 4; + u32 ch_priority : 4; + u32 ch_dev_tout : 12; + u32 reserved2 : 4; +} pdma_ch_cfg_t; + + +/** + * @param TX: means transmitting data from system memory + * to external peripheral devices + * @param RX: means receiving data from peripheral devices + * to system memory + */ +typedef enum pdma_rxtx +{ + TX = 0, + RX = 1, +} pdma_rxtx_e; + +typedef enum pdma_ch +{ + PDMA_CH_0 = 0, + PDMA_CH_1 = 1, + PDMA_CH_2 = 2, + PDMA_CH_3 = 3, + PDMA_CH_4 = 4, + PDMA_CH_5 = 5, + PDMA_CH_6 = 6, + PDMA_CH_7 = 7, + PDMA_CH_MAX, +} pdma_ch_e; + + +typedef enum pdma_burst_len +{ + PBURST_LEN_1 = 0, + PBURST_LEN_2 = 1, + PBURST_LEN_3 = 2, + PBURST_LEN_4 = 3, + PBURST_LEN_5 = 4, + PBURST_LEN_6 = 5, + PBURST_LEN_7 = 6, + PBURST_LEN_8 = 7, + PBURST_LEN_9 = 8, + PBURST_LEN_10 = 9, + PBURST_LEN_11 = 10, + PBURST_LEN_12 = 11, + PBURST_LEN_13 = 12, + PBURST_LEN_14 = 13, + PBURST_LEN_15 = 14, + PBURST_LEN_16 = 15, +} pdma_burst_len_e; + + +/* Global register offsets */ +#define PDMA_CH_EN 0x0 +#define PDMA_INT_MASK 0x4 +#define PDMA_INT_STAT 0x8 + +/* Channel register offsets */ +#define CH_CTL 0x0 +#define CH_STAT 0x4 +#define CH_CFG 0x8 +#define CH_LLT_SADDR 0xc + + +#define CH_OFF 0x20 +#define CH0_BASE 0x20 + +#define CH_NUM 8 + +#define MAX_LINE_SIZE 0xffff +#define MAX_LINE_NUM 0x3ff +#define RECT_MAX_TRANS_LEN (MAX_LINE_SIZE*MAX_LINE_NUM) + + +#define CH_STAT_BUSY BIT(0) +#define CH_STAT_PAUSE BIT(1) + + +typedef enum ch_peri_dev_sel { + UART0_TX = 0, + UART0_RX = 1, + UART1_TX = 2, + UART1_RX = 3, + UART2_TX = 4, + UART2_RX = 5, + UART3_TX = 6, + UART3_RX = 7, + UART4_TX = 8, + UART4_RX = 9, + I2C0_TX = 10, + I2C0_RX = 11, + I2C1_TX = 12, + I2C1_RX = 13, + I2C2_TX = 14, + I2C2_RX = 15, + I2C3_TX = 16, + I2C3_RX = 17, + I2C4_TX = 18, + I2C4_RX = 19, + AUDIO_TX = 20, + AUDIO_RX = 21, + JAMLINK0_TX = 22, + JAMLINK0_RX = 23, + JAMLINK1_TX = 24, + JAMLINK1_RX = 25, + JAMLINK2_TX = 26, + JAMLINK2_RX = 27, + JAMLINK3_TX = 28, + JAMLINK3_RX = 29, + ADC0 = 30, + ADC1 = 31, + ADC2 = 32, + PDM_IN = 33, + PERI_DEV_SEL_MAX, +} ch_peri_dev_sel_t; + +/* usr pdma structure */ +typedef struct usr_pdma_cfg +{ + pdma_ch_e ch; + ch_peri_dev_sel_t device; + dma_addr_t src_addr; + dma_addr_t dst_addr; + u32 line_size; + pdma_ch_cfg_t pdma_ch_cfg; +} usr_pdma_cfg_t; + +typedef enum peridma_mode { + LINE_MODE, + RECT_MODE, + DMA_MODE_MAX +} peridma_mode_t; + +typedef enum ch_src_type { + SRC_TYPE_MEM, + SRC_TYPE_DEV, + SRC_TYPE_MAX +} ch_src_type_t; + +typedef enum ch_dat_endian { + DAT_ENDIAN_DEF, + DAT_ENDIAN_TWO_BYTE, + DAT_ENDIAN_FOUR_BYTE, + DAT_ENDIAN_EIGHT_BYTE, + DAT_ENDIAN_MAX +} ch_dat_endian_t; + +typedef enum ch_dev_hsize { + DEV_HSIZE_ONE_BYTE, + DEV_HSIZE_TWO_BYTE, + DEV_HSIZE_FOUR_BYTE, + DEV_HSIZE_INVALID +} ch_dev_hsize_t; + +/** DMA Driver **/ +struct k230_peridma_hwdesc { + usr_pdma_cfg_t usr_pdma_chn_cfg; + bool last; + struct list_head list; +}; + +struct k230_peridma_desc { + struct virt_dma_desc vd; + struct k230_peridma_vchan *vchan; + struct list_head xfer_list; + struct list_head completed_list; + struct k230_peridma_hwdesc *hwdesc; + atomic_t hwdesc_remain; + bool next; + struct k230_peridma_hwdesc *cyclic; + u32 remain; + u32 buf_len; +}; + + +struct k230_peridma_vchan { + struct k230_peridma_dev *pdev; + struct virt_dma_chan vchan; + struct dma_slave_config cfg; + struct k230_peridma_desc *desc; + struct k230_peridma_hwdesc *cur_hwdesc; + atomic_t descs_allocated; + struct k230_peridma_pchan *pchan; + enum dma_transfer_direction dir; + dma_addr_t dev_addr; + u32 priority; + u32 dev_tout; + ch_dat_endian_t dat_endian; + ch_peri_dev_sel_t dev_sel; + enum dma_status status; + bool is_paused; + +}; + +struct k230_peridma_pchan { + struct k230_peridma_dev *pdev; + /* Register base of channel */ + void __iomem *ch_regs; + u8 id; + struct k230_peridma_vchan *vchan; + bool is_paused; + +}; + +struct k230_peridma_dev { + DECLARE_BITMAP(pchans_used, CH_NUM); + struct device *dev; + struct dma_device slave; + struct k230_peridma_vchan *vchan; + struct k230_peridma_pchan *pchan; + u32 nr_channels; + u32 nr_requests; + void __iomem *base; + struct clk *clk; + int irq; + spinlock_t lock; +}; + + +typedef struct pdma_chn_llt +{ + dma_addr_t llt_list_p; + pdma_llt_t *llt_list_v; + bool use; +}pdma_chn_llt_t; +static pdma_chn_llt_t g_pdma_llt_list[CH_NUM]; + +static void free_pchan(struct k230_peridma_dev *pdev, struct k230_peridma_pchan *pchan); + +static struct k230_peridma_dev *to_k230_peridma_dev(struct dma_device *dev) +{ + return container_of(dev, struct k230_peridma_dev, slave); +} + +static struct k230_peridma_vchan *to_k230_peridma_vchan(struct dma_chan *chan) +{ + return container_of(chan, struct k230_peridma_vchan, vchan.chan); +} + +static struct device *vchan2dev(struct k230_peridma_vchan *vchan) +{ + return &vchan->vchan.chan.dev->device; +} + +static inline struct k230_peridma_desc *vd_to_k230_peridma_desc(struct virt_dma_desc *vd) +{ + return container_of(vd, struct k230_peridma_desc, vd); +} + +static inline struct k230_peridma_vchan *vc_to_k230_peridma_vchan(struct virt_dma_chan *vc) +{ + return container_of(vc, struct k230_peridma_vchan, vchan); +} + +static inline struct k230_peridma_vchan *dchan_to_k230_peridma_vchan(struct dma_chan *dchan) +{ + return vc_to_k230_peridma_vchan(to_virt_chan(dchan)); +} + +static inline const char *peridma_vchan_name(struct k230_peridma_vchan *vchan) +{ + return dma_chan_name(&vchan->vchan.chan); +} + +static inline bool peridma_pchan_is_busy(struct k230_peridma_pchan *pchan) +{ + u32 val; + + val = ioread32(pchan->ch_regs + CH_STAT); + + return (val & CH_STAT_BUSY); +} + +static inline bool peridma_pchan_is_idle(struct k230_peridma_pchan *pchan) +{ + return true; + //return !peridma_pchan_is_busy(pchan); +} + + +static inline bool peridma_pchan_is_paused(struct k230_peridma_pchan *pchan) +{ + u32 val; + + val = ioread32(pchan->ch_regs + CH_STAT); + + return (val & CH_STAT_PAUSE); +} + +static void k230_peridma_free_chan_resources(struct dma_chan *chan) +{ + struct k230_peridma_vchan *pvchan = to_k230_peridma_vchan(chan); + + vchan_free_chan_resources(&pvchan->vchan); +} + +static inline void peridma_pchan_irq_clear(struct k230_peridma_pchan *pchan) +{ + struct k230_peridma_dev *pdev = pchan->pdev; + u32 reg; + u32 ch_id = pchan->id; + u32 clear = PDONE_INT | PITEM_INT | PPAUSE_INT | PTOUT_INT; + + reg = ioread32(pdev->base + PDMA_INT_STAT); + reg |= (clear << ch_id); + iowrite32(reg, pdev->base + PDMA_INT_STAT); +} + +static inline void peridma_pchan_irq_enable(struct k230_peridma_pchan *pchan) +{ + struct k230_peridma_dev *pdev = pchan->pdev; + u32 reg; + u32 ch_id = pchan->id; + + reg = ioread32(pdev->base + PDMA_CH_EN); + reg |= (1 << ch_id); + iowrite32(reg, pdev->base + PDMA_CH_EN); +} + +static inline void peridma_pchan_irq_disable(struct k230_peridma_pchan *pchan) +{ + struct k230_peridma_dev *pdev = pchan->pdev; + u32 reg; + u32 ch_id = pchan->id; + + reg = ioread32(pdev->base + PDMA_CH_EN); + reg &= (~(1 << ch_id)); + iowrite32(reg, pdev->base + PDMA_CH_EN); +} + +static inline void peridma_pchan_start(struct k230_peridma_pchan *pchan) +{ + u32 reg = 0; + reg = 0x1; + iowrite32(reg, pchan->ch_regs + CH_CTL); +} + +static inline void peridma_pchan_stop(struct k230_peridma_pchan *pchan) +{ + u32 reg = 0; + reg = 0x2; + iowrite32(reg, pchan->ch_regs + CH_CTL); +} + +static inline void peridma_pchan_pause(struct k230_peridma_pchan *pchan) +{ + return ; +} + +static inline void peridma_pchan_resume(struct k230_peridma_pchan *pchan) +{ + u32 reg = 0; + reg = 0x4; + iowrite32(reg, pchan->ch_regs + CH_CTL); +} + +static void k230_peridma_hw_init(struct k230_peridma_dev *pdev) +{ + u32 i; + + iowrite32(0, pdev->base + PDMA_CH_EN); + iowrite32(0, pdev->base + PDMA_INT_MASK); + iowrite32(0, pdev->base + PDMA_INT_STAT); + + for (i = 0; i < pdev->nr_channels; i++) { + peridma_pchan_stop(&pdev->pchan[i]); + } +} + +static void peridma_desc_put(struct k230_peridma_desc *desc) +{ + struct k230_peridma_vchan *vchan = desc->vchan; + unsigned int descs_put = 1; + struct k230_peridma_hwdesc *hwdesc, *tmp; + +// vchan->desc = NULL; + + list_for_each_entry_safe(hwdesc, tmp, &desc->xfer_list, list) + kfree(hwdesc); + if(!desc->cyclic) + { + list_for_each_entry_safe(hwdesc, tmp, &desc->completed_list, list) + kfree(hwdesc); + } + + kfree(desc); + + atomic_sub(descs_put, &vchan->descs_allocated); + dev_vdbg(vchan2dev(vchan), ": %d descs put, %d still allocated\n", + descs_put, + atomic_read(&vchan->descs_allocated)); +} + +static void vchan_desc_put(struct virt_dma_desc *vdesc) +{ + peridma_desc_put(vd_to_k230_peridma_desc(vdesc)); +} + +static ch_dev_hsize_t slave_buswidth_to_hsize(enum dma_slave_buswidth buswidth) +{ + ch_dev_hsize_t hsize = DEV_HSIZE_INVALID; + + switch (buswidth) { + case DMA_SLAVE_BUSWIDTH_1_BYTE: + hsize = DEV_HSIZE_ONE_BYTE; + break; + + case DMA_SLAVE_BUSWIDTH_2_BYTES: + hsize = DEV_HSIZE_TWO_BYTE; + break; + + case DMA_SLAVE_BUSWIDTH_4_BYTES: + hsize = DEV_HSIZE_FOUR_BYTE; + break; + + default: + hsize = DEV_HSIZE_INVALID; + break; + } + + return hsize; +} + +static struct k230_peridma_hwdesc *generate_hwdesc( + struct k230_peridma_vchan *vchan, dma_addr_t src, dma_addr_t dest, + size_t len, struct dma_slave_config *sconfig, enum dma_transfer_direction dir) +{ + struct k230_peridma_hwdesc *hwdesc = NULL; + ch_dev_hsize_t hsize = DEV_HSIZE_INVALID; + + hwdesc = kzalloc(sizeof(*hwdesc), GFP_NOWAIT); + if(!hwdesc){ + dev_err(vchan2dev(vchan), "alloc hwdesc failure"); + return NULL; + } + + if (dir == DMA_MEM_TO_DEV) { + hsize = slave_buswidth_to_hsize(sconfig->dst_addr_width); + //printk("=======DMA_MEM_TO_DEV hsize:%d\n",hsize); + if(hsize == DEV_HSIZE_INVALID) + goto err_exit; + hwdesc->usr_pdma_chn_cfg.pdma_ch_cfg.ch_src_type = TX; + hwdesc->usr_pdma_chn_cfg.pdma_ch_cfg.ch_dev_hsize = hsize; + } else if(dir == DMA_DEV_TO_MEM){ + hsize = slave_buswidth_to_hsize(sconfig->src_addr_width); + //printk("=======DMA_DEV_TO_MEM hsize:%d\n",hsize); + if(hsize == DEV_HSIZE_INVALID) + goto err_exit; + hwdesc->usr_pdma_chn_cfg.pdma_ch_cfg.ch_src_type = RX; + hwdesc->usr_pdma_chn_cfg.pdma_ch_cfg.ch_dev_hsize = hsize; + } + hwdesc->usr_pdma_chn_cfg.pdma_ch_cfg.ch_dat_endian = 0; + hwdesc->usr_pdma_chn_cfg.pdma_ch_cfg.ch_dev_blen = PBURST_LEN_8; + hwdesc->usr_pdma_chn_cfg.pdma_ch_cfg.ch_priority = vchan->priority; + hwdesc->usr_pdma_chn_cfg.pdma_ch_cfg.ch_dev_tout = vchan->dev_tout; + + hwdesc->usr_pdma_chn_cfg.src_addr = src; + hwdesc->usr_pdma_chn_cfg.dst_addr = dest; + hwdesc->usr_pdma_chn_cfg.device = vchan->dev_sel; + hwdesc->usr_pdma_chn_cfg.line_size = len; + + //printk("=======dev_sel:%d,hsize:%d,src:0x%llx,dst:0x%llx,priority:%d,size:%d,tout:0x%x\n",vchan->dev_sel,hsize,src,dest,vchan->priority,len,vchan->dev_tout); + + //dev_vdbg(vchan2dev(vchan), "generate hwdesc(%px): ctl=%x, cfg0=%x, cfg1=%x, dev_tout=%x, dev_sel=%x, src_addr=%x, dst_addr=%x \n", hwdesc, hwdesc->ctl, hwdesc->cfg0, hwdesc->cfg1, hwdesc->dev_tout, hwdesc->dev_sel, hwdesc->src_addr, hwdesc->dst_addr); + + return hwdesc; + +err_exit: + kfree(hwdesc); + return NULL; + +} + +static struct dma_async_tx_descriptor *k230_peridma_prep_slave_sg( + struct dma_chan *chan, struct scatterlist *sgl, unsigned int sglen, + enum dma_transfer_direction dir, unsigned long flags, void *context) +{ + //printk("$$$$$$$$$$$k230_peridma_prep_slave_sg\n"); + struct k230_peridma_desc *desc = NULL; + struct k230_peridma_hwdesc *hwdesc = NULL; + struct k230_peridma_hwdesc *tmp = NULL; + struct k230_peridma_vchan *vchan = dchan_to_k230_peridma_vchan(chan); + struct dma_slave_config *sconfig = &vchan->cfg; + struct scatterlist *sg; + size_t xfer_size, avail, total = 0; + dma_addr_t addr, src = 0, dst = 0; + int i = 0; + + dev_vdbg(vchan2dev(vchan), ": prep_slave_sg: sgl: %px sglen: %zd flags: %#lx", + sgl, sglen, flags); +// printk("k230_peridma_prep_slave_sg: sgl: %px sglen: %zd flags: %#lx", +// sgl, sglen, flags); + + desc = kzalloc(sizeof(struct k230_peridma_desc), GFP_NOWAIT); + + if(!desc) + return NULL; + + desc->vchan = vchan; +// vchan->desc = desc; + INIT_LIST_HEAD(&desc->xfer_list); + INIT_LIST_HEAD(&desc->completed_list); +// atomic_set(&desc->hwdesc_remain, 0); + atomic_inc(&vchan->descs_allocated); +// desc->next = false; + + + for_each_sg(sgl, sg, sglen, i) { + addr = sg_dma_address(sg); + avail = sg_dma_len(sg); + + do { + xfer_size = min_t(size_t, avail, MAX_LINE_SIZE); + + if (dir == DMA_MEM_TO_DEV) { + src = addr; + dst = sconfig->dst_addr; + } else if (dir == DMA_DEV_TO_MEM) { + src = sconfig->src_addr; + dst = addr; + } + + dev_vdbg(vchan2dev(vchan), "dma_async_tx_descriptor: src=%x, dst=%x, xfer_size=%x \n", src, dst, xfer_size); + + hwdesc = generate_hwdesc(vchan, src, dst, xfer_size, sconfig, dir); + if(hwdesc) + list_add_tail(&hwdesc->list, &desc->xfer_list); + else { + list_for_each_entry_safe(hwdesc, tmp, &desc->xfer_list, list) + kfree(hwdesc); + + kfree(desc); + dev_err(vchan2dev(vchan), "dma_async_tx_descriptor: generate hwdesc failure \n"); + return NULL; + } +// atomic_inc(&desc->hwdesc_remain); + + addr += xfer_size; + avail -= xfer_size; + + }while(avail); + + } + + dev_vdbg(vchan2dev(vchan), "dma_async_tx_descriptor: prepare desc(%px) \n", desc); + + return vchan_tx_prep(&vchan->vchan, &desc->vd, flags); +} + +static struct dma_async_tx_descriptor *k230_peridma_prep_dma_cyclic( + struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, + size_t period_len, enum dma_transfer_direction dir, + unsigned long flags) +{ + //printk("$$$$$$$$$$$k230_peridma_prep_dma_cyclic buf_addr:0x%llx,buf_len:%d,period_len:%d,dir:%d,num_periods:%d\n",\ + buf_addr,buf_len,period_len,dir,buf_len / period_len); + struct k230_peridma_desc *desc = NULL; + struct k230_peridma_hwdesc *hwdesc = NULL; + struct k230_peridma_hwdesc *tmp = NULL; + struct k230_peridma_vchan *vchan = dchan_to_k230_peridma_vchan(chan); + struct dma_slave_config *sconfig = &vchan->cfg; + struct scatterlist *sg; + size_t xfer_size, avail, total = 0; + u32 num_periods; + dma_addr_t addr, src = 0, dst = 0; + int i = 0; + + desc = kzalloc(sizeof(struct k230_peridma_desc), GFP_NOWAIT); + + if(!desc) + return NULL; + + desc->vchan = vchan; + desc->buf_len = buf_len; + desc->remain = buf_len; + INIT_LIST_HEAD(&desc->xfer_list); + + atomic_inc(&vchan->descs_allocated); + + num_periods = buf_len / period_len; + for(i = 0; i < num_periods; i++) + { + addr = buf_addr + period_len*i; + avail = period_len; + + do { + xfer_size = min_t(size_t, avail, MAX_LINE_SIZE); + + if (dir == DMA_MEM_TO_DEV) { + src = addr; + dst = sconfig->dst_addr; + } else if (dir == DMA_DEV_TO_MEM) { + src = sconfig->src_addr; + dst = addr; + } + + dev_vdbg(vchan2dev(vchan), "dma_async_tx_descriptor: src=%x, dst=%x, xfer_size=%x \n", src, dst, xfer_size); + + hwdesc = generate_hwdesc(vchan, src, dst, xfer_size, sconfig, dir); + if(hwdesc) + { + list_add_tail(&hwdesc->list, &desc->xfer_list); + if(desc->cyclic == NULL) + desc->cyclic = hwdesc; + } + else { + list_for_each_entry_safe(hwdesc, tmp, &desc->xfer_list, list) + kfree(hwdesc); + + kfree(desc); + dev_vdbg(vchan2dev(vchan), "dma_async_tx_descriptor: generate hwdesc failure \n"); + return NULL; + } + + addr += xfer_size; + avail -= xfer_size; + if(avail == 0) + hwdesc->last = true; + } while(avail); + } + + return vchan_tx_prep(&vchan->vchan, &desc->vd, flags); +} + +static int k230_peridma_terminate_all(struct dma_chan *dchan) +{ + struct k230_peridma_vchan *vchan = dchan_to_k230_peridma_vchan(dchan); + unsigned long flags; + LIST_HEAD(head); + + spin_lock_irqsave(&vchan->vchan.lock, flags); + + if(vchan->pchan){ + dev_vdbg(vchan2dev(vchan), "k230_peridma_terminate_all: release pchan %x \n", vchan->pchan->id); + peridma_pchan_irq_disable(vchan->pchan); + peridma_pchan_stop(vchan->pchan); + free_pchan(vchan->pdev,vchan->pchan); + vchan->pchan = NULL; + } else + dev_vdbg(vchan2dev(vchan), "k230_peridma_terminate_all: vchan->pchan is NULL \n"); + + if(vchan->desc){ +// vchan_terminate_vdesc(&vchan->desc->vd); + vchan->desc = NULL; + } + + vchan->is_paused = false; + + vchan_get_all_descriptors(&vchan->vchan, &head); + + /* + * As vchan_dma_desc_free_list can access to desc_allocated list + * we need to call it in vc.lock context. + */ + vchan_dma_desc_free_list(&vchan->vchan, &head); + + spin_unlock_irqrestore(&vchan->vchan.lock, flags); + + dev_vdbg(vchan2dev(vchan), "terminated \n"); + + return 0; +} + +// 无论是cycle还是sg类型的buffer， +// 从desc的第一个hwdesc节点开始遍历到最后一个hwdesc，得到剩余下的需要传输数据长度 +static size_t k230_peridma_desc_residue(struct k230_peridma_vchan *chan, + struct k230_peridma_desc *desc) +{ + struct k230_peridma_hwdesc *hwdesc = NULL; + u32 residue = 0; + residue = desc->remain; + + return residue; +} + +static enum dma_status k230_peridma_tx_status(struct dma_chan *dchan, + dma_cookie_t cookie, + struct dma_tx_state *txstate) +{ + struct k230_peridma_vchan *vchan = dchan_to_k230_peridma_vchan(dchan); + enum dma_status ret; + struct virt_dma_desc *vdesc; + unsigned long flags; + u32 residue = 0; + + ret = dma_cookie_status(dchan, cookie, txstate); + if (ret == DMA_COMPLETE) + return ret; + + spin_lock_irqsave(&vchan->vchan.lock, flags); + ret = dma_cookie_status(dchan, cookie, txstate); + if (ret != DMA_COMPLETE) + { + vdesc = vchan_find_desc(&vchan->vchan, cookie); + if (vdesc) + { + residue = k230_peridma_desc_residue(vchan, + vd_to_k230_peridma_desc(vdesc)); + } + } + spin_unlock_irqrestore(&vchan->vchan.lock, flags); + dma_set_residue(txstate, residue); + + if (vchan->is_paused && ret == DMA_IN_PROGRESS) + ret = DMA_PAUSED; + + return ret; +} + + +static void free_pchan(struct k230_peridma_dev *pdev, struct k230_peridma_pchan *pchan) +{ + unsigned long flags; + int nr = pchan - pdev->pchan; + struct k230_peridma_vchan *vchan; + + spin_lock_irqsave(&pdev->lock, flags); + + vchan = pchan->vchan; + vchan->pchan = NULL; + pchan->vchan = NULL; + clear_bit(nr, pdev->pchans_used); + + spin_unlock_irqrestore(&pdev->lock, flags); + +} + +static struct k230_peridma_pchan *find_phy_chan(struct k230_peridma_dev *pdev, struct k230_peridma_vchan *vchan) +{ + struct k230_peridma_pchan *pchan = NULL, *pchans = pdev->pchan; + unsigned long flags; + int i=0, ch_num; + + spin_lock_irqsave(&pdev->lock, flags); + for_each_clear_bit_from(i, pdev->pchans_used, CH_NUM) { + pchan = &pchans[i]; + pchan->vchan = vchan; + pdev->pchan[i].vchan = vchan; + set_bit(i, pdev->pchans_used); + break; + } + spin_unlock_irqrestore(&pdev->lock, flags); + + return pchan; +} + +static u32* pdma_llt_cal(struct device *dev,struct k230_peridma_hwdesc *hwdesc,u8 chn) +{ + int i; + u32 list_num; + pdma_llt_t *llt_list; + dma_addr_t llt_list_hard; + + list_num = (hwdesc->usr_pdma_chn_cfg.line_size - 1) / PDMA_MAX_LINE_SIZE + 1; + + llt_list = g_pdma_llt_list[chn].llt_list_v; + g_pdma_llt_list[chn].use = true; + + for (i = 0; i < list_num; i++) { + llt_list[i].src_addr = ((u32)(uintptr_t)hwdesc->usr_pdma_chn_cfg.src_addr + PDMA_MAX_LINE_SIZE*i); + llt_list[i].dst_addr = ((u32)(uintptr_t)hwdesc->usr_pdma_chn_cfg.dst_addr + PDMA_MAX_LINE_SIZE*i); + + //printk("===pdma_llt_cal src_addr:0x%llx,dst_addr:0x%llx,list_num:%d\n",llt_list[i].src_addr,llt_list[i].dst_addr,list_num); + if (i == list_num -1) { + llt_list[i].line_size = hwdesc->usr_pdma_chn_cfg.line_size % PDMA_MAX_LINE_SIZE; + llt_list[i].next_llt_addr = 0; + } else { + llt_list[i].line_size = PDMA_MAX_LINE_SIZE; + llt_list[i].next_llt_addr = (u32)(uintptr_t)(&llt_list[i+1]); + } + } + + return (u32 *)g_pdma_llt_list[chn].llt_list_p; +} + +static void configure_pchan(struct k230_peridma_pchan *pchan, struct k230_peridma_hwdesc *hwdesc) +{ + struct k230_peridma_dev *pdev = pchan->pdev; + unsigned long flags; + + if (unlikely(!peridma_pchan_is_idle(pchan))) { + dev_err(vchan2dev(pchan->vchan), "pchan %d is non-idle!\n", + pchan->id); + + return; + } + + hwdesc->usr_pdma_chn_cfg.ch = (pdma_ch_e)pchan->id; + + u32 ch_cfg = *(u32*)&hwdesc->usr_pdma_chn_cfg.pdma_ch_cfg; + iowrite32(ch_cfg, pchan->ch_regs+CH_CFG); + iowrite32(hwdesc->usr_pdma_chn_cfg.device, pdev->base + 0x120 + pchan->id*4); + iowrite32((u32)(uintptr_t)pdma_llt_cal(pdev->dev,hwdesc,pchan->id),pchan->ch_regs+CH_LLT_SADDR); +} + +static void peridma_vchan_start_first_queued(struct k230_peridma_vchan *vchan) +{ + struct k230_peridma_desc *desc; + struct virt_dma_desc *vd; + struct k230_peridma_dev *pdev = vchan->pdev; + struct k230_peridma_pchan *pchan = NULL; + struct k230_peridma_hwdesc *hwdesc = NULL; + unsigned long flags; + + + if(vchan->desc) { + dev_err(vchan2dev(vchan), "%s already processing something \n", peridma_vchan_name(vchan)); + dump_stack(); + return; + } + + if(vchan->pchan) { + pchan = vchan->pchan; + dev_vdbg(vchan2dev(vchan), "%s already allocated phy channel \n", peridma_vchan_name(vchan)); + } else { + pchan = find_phy_chan(pdev, vchan); + if(pchan) + { + vchan->pchan = pchan; + //printk("============:vchan name:%s allocated phy channel:%d\n",peridma_vchan_name(vchan),vchan->pchan->id); + } + else + return; + } + + + + vd = vchan_next_desc(&vchan->vchan); + if (!vd) { + dev_vdbg(vchan2dev(vchan), "peridma_vchan_start_first_queued: no next vd found \n"); + goto freepchan; + } + + desc = vd_to_k230_peridma_desc(vd); + dev_vdbg(vchan2dev(vchan), "peridma_vchan_start_first_queued: desc %px \n", desc); + + if(!list_empty(&desc->xfer_list)){ + hwdesc = list_first_entry(&desc->xfer_list, struct k230_peridma_hwdesc, list); +// list_del(&hwdesc->list); +// atomic_sub(1, &desc->hwdesc_remain); + + //dev_vdbg(vchan2dev(vchan), "peridma_vchan_start_first_queued: hwdesc(%px) \n", hwdesc); + //dev_vdbg(vchan2dev(vchan), " ctl=%x, cfg0=%x, cfg1=%x, dev_tout=%x, dev_sel=%x, src_addr=%x, dst_addr=%x \n", hwdesc->ctl, hwdesc->cfg0, hwdesc->cfg1, hwdesc->dev_tout, hwdesc->dev_sel, hwdesc->src_addr, hwdesc->dst_addr); + vchan->desc = desc; + desc->hwdesc = hwdesc; + + peridma_pchan_irq_clear(vchan->pchan); + configure_pchan(vchan->pchan, desc->hwdesc); + peridma_pchan_irq_enable(vchan->pchan); + peridma_pchan_start(vchan->pchan); + + + return; + } + + +freepchan: +// dev_vdbg(vchan2dev(vchan), "peridma_vchan_start_first_queued: free_pchan \n"); +// free_pchan(pdev, pchan); + return; + +} + + +static void peridma_vchan_xfer_complete(struct k230_peridma_vchan *vchan) +{ + struct virt_dma_desc *vd; + unsigned long flags; + +// spin_lock_irqsave(&vchan->vchan.lock, flags); + + if (unlikely(!peridma_pchan_is_idle(vchan->pchan))) { + dev_err(vchan2dev(vchan), "BUG: %s caught chx_tr_done, but channel not idle!\n", + peridma_vchan_name(vchan)); + peridma_pchan_stop(vchan->pchan); + } + + /* The completed descriptor currently is in the head of vc list */ + vd = vchan_next_desc(&vchan->vchan); + + /* Remove the completed descriptor from issued list before completing */ + list_del(&vd->node); + vchan_cookie_complete(vd); + + /* Submit queued descriptors after processing the completed ones */ + peridma_vchan_start_first_queued(vchan); + +// spin_unlock_irqrestore(&vchan->vchan.lock, flags); +} + + +static void k230_peridma_issue_pending(struct dma_chan *dchan) +{ + struct k230_peridma_vchan *vchan = dchan_to_k230_peridma_vchan(dchan); + unsigned long flags; + + spin_lock_irqsave(&vchan->vchan.lock, flags); + + if (vchan_issue_pending(&vchan->vchan)){ + dev_vdbg(vchan2dev(vchan), "k230_peridma_issue_pending: 1 \n"); + peridma_vchan_start_first_queued(vchan); + } + dev_vdbg(vchan2dev(vchan), "k230_peridma_issue_pending: 2 \n"); + + spin_unlock_irqrestore(&vchan->vchan.lock, flags); +} + +static void _pdma_chn_state_clear(pdma_ch_e pdma_chn, u32* int_state) +{ + if (*int_state & (1 << pdma_chn)) + { + *int_state |= (PDONE_INT << pdma_chn); + + //free 链表 + } + if (*int_state & (1 << (8 + pdma_chn))) + { + *int_state |= (PITEM_INT << pdma_chn); + } + if (*int_state & (1 << (16 + pdma_chn))) + { + *int_state |= (PPAUSE_INT << pdma_chn); + } + if (*int_state & (1 << (24 + pdma_chn))) + { + *int_state |= (PTOUT_INT << pdma_chn); + } +} + +static irqreturn_t k230_peridma_interrupt(int irq, void *dev_id) +{ + + struct k230_peridma_dev *priv = dev_id; + struct k230_peridma_vchan *vchan; + struct k230_peridma_desc *desc = NULL; + struct k230_peridma_hwdesc *hwdesc = NULL; + int i; + u32 ch_id; + + u32 int_stat = 0; + int_stat = ioread32(priv->base + PDMA_INT_STAT); + for (i = 0;i < CH_NUM;i ++) + { + if ((int_stat >> i) & 0x1) + { + _pdma_chn_state_clear(i, &int_stat); + iowrite32(int_stat, priv->base + PDMA_INT_STAT); + g_pdma_llt_list[i].use = false; + } + else + { + continue; + } + ch_id = i; + vchan = priv->pchan[ch_id].vchan; + if (vchan == NULL) + { + return IRQ_HANDLED; + } + spin_lock(&vchan->vchan.lock); + //dev_vdbg(vchan2dev(vchan), "k230_peridma_interrupt: process Transfer done irq of phy ch%d, int_status(%x) \n", ch_id, int_stat0); + desc = vchan->desc; + //printk("========desc->cyclic:0x%llx\n",desc->cyclic); + if(desc->cyclic) + { + hwdesc = desc->cyclic; + //dev_vdbg(vchan2dev(vchan),"hwdesc(%px): last=%d ctl=%x, cfg0=%x, \n cfg1=%x, dev_tout=%x, dev_sel=%x, src_addr=%x, dst_addr=%x \n", hwdesc, hwdesc->last, hwdesc->ctl, hwdesc->cfg0, hwdesc->cfg1, hwdesc->dev_tout, hwdesc->dev_sel, hwdesc->src_addr, hwdesc->dst_addr); + desc->remain -= hwdesc->usr_pdma_chn_cfg.line_size; + if(desc->remain == 0) + desc->remain = desc->buf_len; + if(hwdesc->last) + vchan_cyclic_callback(&vchan->desc->vd); + + if(desc->cyclic->list.next == &(desc->xfer_list)) + desc->cyclic = list_entry(desc->xfer_list.next, typeof(*(desc->cyclic)), list); + else + desc->cyclic = list_next_entry(desc->hwdesc, list); + + hwdesc = desc->cyclic; + desc->hwdesc = hwdesc; + configure_pchan(vchan->pchan, hwdesc); + peridma_pchan_start(vchan->pchan); + } + else + { + list_del(&desc->hwdesc->list); + list_add_tail(&desc->hwdesc->list, &desc->completed_list); + + if(!list_empty(&desc->xfer_list)){ + hwdesc = list_first_entry(&desc->xfer_list, struct k230_peridma_hwdesc, list); + // list_del(&hwdesc->list); + // atomic_sub(1, &desc->hwdesc_remain); + + //dev_vdbg(vchan2dev(vchan), "hwdesc(%px): ctl=%x, cfg0=%x, cfg1=%x, dev_tout=%x, dev_sel=%x, src_addr=%x, dst_addr=%x \n", hwdesc, hwdesc->ctl, hwdesc->cfg0, hwdesc->cfg1, hwdesc->dev_tout, hwdesc->dev_sel, hwdesc->src_addr, hwdesc->dst_addr); + desc->hwdesc = hwdesc; + // desc->next = true; + configure_pchan(vchan->pchan, hwdesc); + peridma_pchan_start(vchan->pchan); + } else { + vchan->desc = NULL; + peridma_vchan_xfer_complete(vchan); + } + } + spin_unlock(&vchan->vchan.lock); + } + + return IRQ_HANDLED; +} + +static int k230_peridma_vchan_pause(struct dma_chan *dchan) +{ + struct k230_peridma_vchan *vchan = dchan_to_k230_peridma_vchan(dchan); + unsigned long flags; + unsigned int timeout = 20; /* timeout iterations */ + u32 val; + + if(!vchan->pchan){ + dev_err(vchan2dev(vchan), "k230_peridma_vchan_pause: vchan->pchan is NULL \n"); + dump_stack(); + return -EBUSY; + } + + spin_lock_irqsave(&vchan->vchan.lock, flags); + + if (!peridma_pchan_is_busy(vchan->pchan)) { + dev_err(vchan2dev(vchan), "%s is non-busy!\n", + peridma_vchan_name(vchan)); + + spin_unlock_irqrestore(&vchan->vchan.lock, flags); + + return -EBUSY; + } + + peridma_pchan_pause(vchan->pchan); + + do { + if (peridma_pchan_is_paused(vchan->pchan)) + break; + + udelay(2); + } while (--timeout); + + peridma_pchan_irq_disable(vchan->pchan); + + vchan->is_paused = true; + + spin_unlock_irqrestore(&vchan->vchan.lock, flags); + + return timeout ? 0 : -EAGAIN; +} + +static int k230_peridma_vchan_resume(struct dma_chan *dchan) +{ + struct k230_peridma_vchan *vchan = dchan_to_k230_peridma_vchan(dchan); + unsigned long flags; + + spin_lock_irqsave(&vchan->vchan.lock, flags); + + if (vchan->is_paused){ + peridma_pchan_irq_enable(vchan->pchan); + peridma_pchan_resume(vchan->pchan); + } + + vchan->is_paused = false; + + spin_unlock_irqrestore(&vchan->vchan.lock, flags); + + return 0; +} + + +static void k230_peridma_vchan_free_chan_resources(struct dma_chan *dchan) +{ + struct k230_peridma_vchan *vchan = dchan_to_k230_peridma_vchan(dchan); + + if(vchan->pchan) { + /* ASSERT: channel is idle */ + if (!peridma_pchan_is_idle(vchan->pchan)) { + dev_err(vchan2dev(vchan), "%s is non-idle!\n", + peridma_vchan_name(vchan)); + } + + peridma_pchan_stop(vchan->pchan); + peridma_pchan_irq_disable(vchan->pchan); + } + + + vchan_free_chan_resources(&vchan->vchan); + + dev_vdbg(vchan2dev(vchan), + "%s: free resources, descriptor still allocated: %u\n", + peridma_vchan_name(vchan), atomic_read(&vchan->descs_allocated)); + +} + +static int k230_peridma_config(struct dma_chan *chan, + struct dma_slave_config *config) +{ + //printk("$$$$$$$$$$$k230_peridma_config,src_addr:0x%llx,dst_addr:0x%llx,src_maxburst:%d,dst_maxburst:%d,src_addr_width:%d,dst_addr_width:%d,direction:%d\n" \ + ,config->src_addr,config->dst_addr,config->src_maxburst,config->dst_maxburst,config->src_addr_width,config->dst_addr_width,config->direction); + struct k230_peridma_vchan *vchan = to_k230_peridma_vchan(chan); + + memcpy(&vchan->cfg, config, sizeof(*config)); + + return 0; +} + + +static int parse_device_properties(struct k230_peridma_dev *pdev) +{ + struct device *dev = pdev->dev; + u32 tmp; + int ret; + + ret = device_property_read_u32(dev, "dma-channels", &tmp); + if (ret) + return ret; + + if (tmp == 0 || tmp > CH_NUM) + return -EINVAL; + + pdev->nr_channels = tmp; + + ret = device_property_read_u32(dev, "dma-requests", &tmp); + if (ret) + return ret; + + if (tmp == 0 || tmp > 35) + return -EINVAL; + + pdev->nr_requests = tmp; + + return 0; +} + +static struct dma_chan *k230_pdma_of_xlate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) +{ + //printk("==========k230_pdma_of_xlate before\n"); + struct k230_peridma_dev *priv = ofdma->of_dma_data; + struct k230_peridma_vchan *vchan; + struct dma_chan *chan; + unsigned int priority = dma_spec->args[0]; + unsigned int dev_tout = dma_spec->args[1]; + unsigned int dat_endian = dma_spec->args[2]; + unsigned int dev_sel = dma_spec->args[3]; + + dev_vdbg(priv->dev, "k230_pdma_of_xlate: priority=%x, dev_tout=%x, dat_endian=%x, dev_sel=%x \n", priority, dev_tout, dat_endian, dev_sel); + + if (dev_sel > (priv->nr_requests -1)) + return NULL; + + chan = dma_get_slave_channel(&(priv->vchan[dev_sel].vchan.chan)); + + if(!chan) + return NULL; + + vchan = to_k230_peridma_vchan(chan); + + vchan->priority = priority; + vchan->dev_tout = dev_tout; + vchan->dat_endian = dat_endian; + vchan->dev_sel = dev_sel; + + dev_vdbg(priv->dev, "k230_pdma_of_xlate: get vchan %s \n", peridma_vchan_name(vchan)); + return chan; +} + +static int k230_peridma_probe(struct platform_device *pdev) +{ + struct k230_peridma_dev *priv; + struct resource *res; + int i, j, ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->dev = &pdev->dev; + priv->slave.dev = &pdev->dev; + + priv->irq = platform_get_irq(pdev, 0); + if (priv->irq < 0) { + dev_err(&pdev->dev, "Cannot claim IRQ\n"); + return priv->irq; + } + + + priv->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(priv->clk)) { + dev_err(&pdev->dev, "No clock specified\n"); + return PTR_ERR(priv->clk); + } + + ret = parse_device_properties(priv); + if (ret) + return ret; + + //printk("=====k230_peridma_probe irq:%d,dma_channels:%d,requests:%d\n",priv->irq,priv->nr_channels,priv->nr_requests); + + /* Initialize physical channels */ + priv->pchan = devm_kcalloc(priv->dev, priv->nr_channels, + sizeof(struct k230_peridma_pchan), GFP_KERNEL); + if (!priv->pchan) + return -ENOMEM; + + for (i = 0; i < priv->nr_channels; i++) { + struct k230_peridma_pchan *pchan = &priv->pchan[i]; + + pchan->pdev = priv; + pchan->id = i; + pchan->ch_regs = priv->base + CH0_BASE + i * CH_OFF; + } + + /* Initialize virtual channels */ + priv->vchan = devm_kcalloc(priv->dev, priv->nr_requests, + sizeof(struct k230_peridma_vchan), GFP_KERNEL); + if (!priv->vchan) + return -ENOMEM; + + INIT_LIST_HEAD(&priv->slave.channels); + for (i = 0; i < priv->nr_requests; i++) { + struct k230_peridma_vchan *vchan = &priv->vchan[i]; + + vchan->pdev = priv; + vchan->desc = NULL; + atomic_set(&vchan->descs_allocated, 0); + + vchan->vchan.desc_free = vchan_desc_put; + vchan_init(&vchan->vchan, &priv->slave); + } + + platform_set_drvdata(pdev, priv); + spin_lock_init(&priv->lock); + + dma_cap_zero(priv->slave.cap_mask); + dma_cap_set(DMA_SLAVE, priv->slave.cap_mask); + +// priv->slave.chancnt = priv->nr_channels; +// priv->slave.src_addr_widths = DMA_SLAVE_BUSWIDTH_8_BYTES; +// priv->slave.dst_addr_widths = DMA_SLAVE_BUSWIDTH_8_BYTES; +// priv->slave.directions = BIT(DMA_MEM_TO_MEM); +// priv->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; + + priv->slave.directions = BIT(DMA_DEV_TO_MEM) | + BIT(DMA_MEM_TO_DEV); + priv->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; + priv->slave.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); + priv->slave.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | + BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | + BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); + + priv->slave.device_tx_status = k230_peridma_tx_status; + priv->slave.device_issue_pending = k230_peridma_issue_pending; + priv->slave.device_terminate_all = k230_peridma_terminate_all; + priv->slave.device_pause = k230_peridma_vchan_pause; + priv->slave.device_resume = k230_peridma_vchan_resume; + +// priv->slave.device_alloc_chan_resources = k230_peridma_vchan_alloc_chan_resources; + priv->slave.device_free_chan_resources = k230_peridma_vchan_free_chan_resources; + + priv->slave.device_prep_slave_sg = k230_peridma_prep_slave_sg; + priv->slave.device_prep_dma_cyclic = k230_peridma_prep_dma_cyclic; + priv->slave.device_config = k230_peridma_config; + + priv->slave.dev = &pdev->dev; + + ret = clk_prepare_enable(priv->clk); + if (ret) { + dev_err(&pdev->dev, "Couldn't enable the clock\n"); + return ret; + } + + /* + * Initialize peridma controller + */ + + k230_peridma_hw_init(priv); + + ret = devm_request_irq(&pdev->dev, priv->irq, k230_peridma_interrupt, + 0, dev_name(&pdev->dev), priv); + if (ret) { + dev_err(&pdev->dev, "Cannot request IRQ\n"); + goto err_clk_disable; + } + + ret = dma_async_device_register(&priv->slave); + if (ret) { + dev_warn(&pdev->dev, "Failed to register DMA engine device\n"); + goto err_clk_disable; + } + + ret = of_dma_controller_register(pdev->dev.of_node, k230_pdma_of_xlate, + priv); + if (ret) { + dev_err(&pdev->dev, "of_dma_controller_register failed\n"); + goto err_clk_disable; + } + + for (i =0;i < CH_NUM;i ++) + { + g_pdma_llt_list[i].llt_list_v = dma_alloc_coherent(&pdev->dev,sizeof(pdma_llt_t),&g_pdma_llt_list[i].llt_list_p,GFP_KERNEL); + g_pdma_llt_list[i].use = false; + //printk("===========g_pdma_llt_list[%d].llt_list_p:0x%llx\n",i,g_pdma_llt_list[i].llt_list_p); + } + + dev_vdbg(&pdev->dev, "Successfully probed K230 peridma controller, register mapped at %px(PHY %px) \n", priv->base ,res->start); + + return 0; + +err_clk_disable: + clk_disable_unprepare(priv->clk); + return ret; +} + +static int k230_peridma_remove(struct platform_device *pdev) +{ + int i =0; + struct k230_peridma_dev *priv = platform_get_drvdata(pdev); + + for (i =0;i < CH_NUM;i ++) + { + dma_free_coherent(&pdev->dev,sizeof(pdma_llt_t),g_pdma_llt_list[i].llt_list_v,g_pdma_llt_list[i].llt_list_p); + g_pdma_llt_list[i].llt_list_v = NULL; + } + + /* Disable IRQ so no more work is scheduled */ + disable_irq(priv->irq); + + of_dma_controller_free(pdev->dev.of_node); + dma_async_device_unregister(&priv->slave); + + clk_disable_unprepare(priv->clk); + + return 0; +} + +static const struct of_device_id k230_peridma_match[] = { + { .compatible = "canaan,k230-pdma" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, k230_peridma_match); + +static struct platform_driver k230_peridma_driver = { + .probe = k230_peridma_probe, + .remove = k230_peridma_remove, + .driver = { + .name = "k230-peridma", + .of_match_table = k230_peridma_match, + }, +}; + +module_platform_driver(k230_peridma_driver); + +MODULE_DESCRIPTION("K230 peridma driver"); +MODULE_LICENSE("GPL"); diff --git a/src/little/linux/drivers/mmc/host/sdhci-of-kendryte.c b/src/little/linux/drivers/mmc/host/sdhci-of-kendryte.c index 023fd6f87..10b320550 100755 --- a/src/little/linux/drivers/mmc/host/sdhci-of-kendryte.c +++ b/src/little/linux/drivers/mmc/host/sdhci-of-kendryte.c @@ -131,7 +131,7 @@ static void dwcmshc_phy_delay_config(struct sdhci_host *host) sdhci_writeb(host, 0x0, DWC_MSHC_SDCLKDL_CNFG); sdhci_writeb(host, priv->tx_delay_line, DWC_MSHC_SDCLKDL_DC); } - + sdhci_writeb(host, priv->rx_delay_line, DWC_MSHC_SMPLDL_CNFG); sdhci_writeb(host, 0xc, DWC_MSHC_ATDL_CNFG); sdhci_writel(host, (sdhci_readl(host, SDHCI_VENDER_AT_CTRL_REG) | \ BIT(16) | BIT(17) | BIT(19) | BIT(20)), SDHCI_VENDER_AT_CTRL_REG); @@ -353,11 +353,11 @@ static int dwcmshc_probe(struct platform_device *pdev) } err = device_property_read_u32(&pdev->dev, "tx_delay_line", &priv->tx_delay_line); if(err) - priv->tx_delay_line = 0; + priv->tx_delay_line = 0x40; err = device_property_read_u32(&pdev->dev, "rx_delay_line", &priv->rx_delay_line); if(err) - priv->rx_delay_line = 0; + priv->rx_delay_line = 0xd; } else { /*sdio:(fpga board) Launches CMD/DATA with respect to positive edge of cclk_tx */ diff --git a/src/little/linux/drivers/net/wireless/Kconfig b/src/little/linux/drivers/net/wireless/Kconfig index a10f90708..234ecd9b3 100755 --- a/src/little/linux/drivers/net/wireless/Kconfig +++ b/src/little/linux/drivers/net/wireless/Kconfig @@ -52,6 +52,7 @@ source "drivers/net/wireless/quantenna/Kconfig" source "drivers/net/wireless/bcmdhd/Kconfig" source "drivers/net/wireless/rtl8821cs/Kconfig" source "drivers/net/wireless/rtl8189fs/Kconfig" +source "drivers/net/wireless/rtl8188fu/Kconfig" config PCMCIA_RAYCS tristate "Aviator/Raytheon 2.4GHz wireless support" diff --git a/src/little/linux/drivers/net/wireless/Makefile b/src/little/linux/drivers/net/wireless/Makefile index ff5d76a84..6e9867146 100755 --- a/src/little/linux/drivers/net/wireless/Makefile +++ b/src/little/linux/drivers/net/wireless/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_WLAN_VENDOR_QUANTENNA) += quantenna/ obj-$(CONFIG_BCMDHD) += bcmdhd/ obj-$(CONFIG_RTL8821CS) += rtl8821cs/ obj-$(CONFIG_RTL8189FS) += rtl8189fs/ +obj-$(CONFIG_RTL8188FU) += rtl8188fu/ # 16-bit wireless PCMCIA client drivers obj-$(CONFIG_PCMCIA_RAYCS) += ray_cs.o diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/Kconfig b/src/little/linux/drivers/net/wireless/rtl8188fu/Kconfig new file mode 100755 index 000000000..1db20121d --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/Kconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +config RTL8188FU + tristate "Realtek 8188F USB WiFi" + depends on USB + help + Help message of RTL8818FU + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/LICENSE b/src/little/linux/drivers/net/wireless/rtl8188fu/LICENSE new file mode 100755 index 000000000..d159169d1 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/LICENSE @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. By contrast, the GNU General Public +License is intended to guarantee your freedom to share and change free +software--to make sure the software is free for all its users. This +General Public License applies to most of the Free Software +Foundation's software and to any other program whose authors commit to +using it. (Some other Free Software Foundation software is covered by +the GNU Lesser General Public License instead.) You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +this service if you wish), that you receive source code or can get it +if you want it, that you can change the software or use pieces of it +in new free programs; and that you know you can do these things. + + To protect your rights, we need to make restrictions that forbid +anyone to deny you these rights or to ask you to surrender the rights. +These restrictions translate to certain responsibilities for you if you +distribute copies of the software, or if you modify it. + + For example, if you distribute copies of such a program, whether +gratis or for a fee, you must give the recipients all the rights that +you have. You must make sure that they, too, receive or can get the +source code. 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It is safest +to attach them to the start of each source file to most effectively +convey the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License along + with this program; if not, write to the Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + +Also add information on how to contact you by electronic and paper mail. + +If the program is interactive, make it output a short notice like this +when it starts in an interactive mode: + + Gnomovision version 69, Copyright (C) year name of author + Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/Makefile b/src/little/linux/drivers/net/wireless/rtl8188fu/Makefile new file mode 100755 index 000000000..7e20d6fa8 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/Makefile @@ -0,0 +1,517 @@ +# SPDX-License-Identifier: GPL-2.0 +EXTRA_CFLAGS += $(USER_EXTRA_CFLAGS) +EXTRA_CFLAGS += -O1 +#EXTRA_CFLAGS += -O3 +#EXTRA_CFLAGS += -Wall +#EXTRA_CFLAGS += -Wextra +#EXTRA_CFLAGS += -Werror +#EXTRA_CFLAGS += -pedantic +#EXTRA_CFLAGS += -Wshadow -Wpointer-arith -Wcast-qual -Wstrict-prototypes -Wmissing-prototypes + +EXTRA_CFLAGS += -Wno-unused-variable +EXTRA_CFLAGS += -Wno-unused-value +EXTRA_CFLAGS += -Wno-unused-label +EXTRA_CFLAGS += -Wno-unused-parameter +EXTRA_CFLAGS += -Wno-unused-function +EXTRA_CFLAGS += -Wno-unused +#EXTRA_CFLAGS += -Wno-uninitialized +#EXTRA_CFLAGS += -Wno-error=date-time # Fix compile error on gcc 4.9 and later + +mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST))) +src := $(patsubst %Makefile, %, $(mkfile_path)) + +EXTRA_CFLAGS += -I$(src)/include +EXTRA_CFLAGS += -I$(src)/hal/phydm + +EXTRA_LDFLAGS += --strip-debug + +CONFIG_AUTOCFG_CP = n + +########################## WIFI IC ############################ +CONFIG_RTL8188E = n +CONFIG_RTL8812A = n +CONFIG_RTL8821A = n +CONFIG_RTL8192E = n +CONFIG_RTL8723B = n +CONFIG_RTL8814A = n +CONFIG_RTL8723C = n +CONFIG_RTL8188F = y +######################### Interface ########################### +CONFIG_USB_HCI = y +########################## Features ########################### +CONFIG_MP_INCLUDED = y +CONFIG_POWER_SAVING = y +CONFIG_USB_AUTOSUSPEND = n +CONFIG_HW_PWRP_DETECTION = n +CONFIG_WIFI_TEST = n +CONFIG_BT_COEXIST = n +CONFIG_INTEL_WIDI = n +CONFIG_WAPI_SUPPORT = n +CONFIG_EFUSE_CONFIG_FILE = n +CONFIG_EXT_CLK = n +CONFIG_TRAFFIC_PROTECT = y +CONFIG_LOAD_PHY_PARA_FROM_FILE = y +CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY = n +CONFIG_CALIBRATE_TX_POWER_TO_MAX = y +CONFIG_RTW_ADAPTIVITY_EN = disable +CONFIG_RTW_ADAPTIVITY_MODE = normal +CONFIG_SIGNAL_SCALE_MAPPING = n +CONFIG_80211W = n +CONFIG_REDUCE_TX_CPU_LOADING = n +CONFIG_BR_EXT = y +CONFIG_ANTENNA_DIVERSITY = n +CONFIG_TDLS = n +CONFIG_WIFI_MONITOR = n +######### Notify SDIO Host Keep Power During Syspend ########## +CONFIG_RTW_SDIO_PM_KEEP_POWER = y +###################### MP HW TX MODE FOR VHT ####################### +CONFIG_MP_VHT_HW_TX_MODE = n +###################### Platform Related ####################### +CONFIG_PLATFORM_I386_PC = n +CONFIG_PLATFORM_ANDROID_X86 = n +CONFIG_PLATFORM_ANDROID_INTEL_X86 = n +CONFIG_PLATFORM_JB_X86 = n +CONFIG_PLATFORM_ARM_S3C2K4 = n +CONFIG_PLATFORM_ARM_PXA2XX = n +CONFIG_PLATFORM_ARM_S3C6K4 = n +CONFIG_PLATFORM_MIPS_RMI = n +CONFIG_PLATFORM_RTD2880B = n +CONFIG_PLATFORM_MIPS_AR9132 = n +CONFIG_PLATFORM_RTK_DMP = n +CONFIG_PLATFORM_MIPS_PLM = n +CONFIG_PLATFORM_MSTAR389 = n +CONFIG_PLATFORM_MT53XX = n +CONFIG_PLATFORM_ARM_MX51_241H = n +CONFIG_PLATFORM_FS_MX61 = n +CONFIG_PLATFORM_ACTIONS_ATJ227X = n +CONFIG_PLATFORM_TEGRA3_CARDHU = n +CONFIG_PLATFORM_TEGRA4_DALMORE = n +CONFIG_PLATFORM_ARM_TCC8900 = n +CONFIG_PLATFORM_ARM_TCC8920 = n +CONFIG_PLATFORM_ARM_TCC8920_JB42 = n +CONFIG_PLATFORM_ARM_TCC8930_JB42 = n +CONFIG_PLATFORM_ARM_RK2818 = n +CONFIG_PLATFORM_ARM_RK3066 = n +CONFIG_PLATFORM_ARM_RK3188 = n +CONFIG_PLATFORM_ARM_URBETTER = n +CONFIG_PLATFORM_ARM_TI_PANDA = n +CONFIG_PLATFORM_MIPS_JZ4760 = n +CONFIG_PLATFORM_DMP_PHILIPS = n +CONFIG_PLATFORM_MSTAR_TITANIA12 = n +CONFIG_PLATFORM_MSTAR = n +CONFIG_PLATFORM_SZEBOOK = n +CONFIG_PLATFORM_ARM_SUNxI = n +CONFIG_PLATFORM_ARM_SUN6I = n +CONFIG_PLATFORM_ARM_SUN7I = n +CONFIG_PLATFORM_ARM_SUN8I_W3P1 = n +CONFIG_PLATFORM_ARM_SUN8I_W5P1 = n +CONFIG_PLATFORM_ACTIONS_ATM702X = n +CONFIG_PLATFORM_ACTIONS_ATV5201 = n +CONFIG_PLATFORM_ACTIONS_ATM705X = n +CONFIG_PLATFORM_ARM_SUN50IW1P1 = n +CONFIG_PLATFORM_ARM_RTD299X = n +CONFIG_PLATFORM_ARM_SPREADTRUM_6820 = n +CONFIG_PLATFORM_ARM_SPREADTRUM_8810 = n +CONFIG_PLATFORM_ARM_WMT = n +CONFIG_PLATFORM_TI_DM365 = n +CONFIG_PLATFORM_MOZART = n +CONFIG_PLATFORM_RTK119X = n +CONFIG_PLATFORM_NOVATEK_NT72668 = n +CONFIG_PLATFORM_HISILICON = n +CONFIG_PLATFORM_RISCV_K230 = y +############################################################### + +CONFIG_DRVEXT_MODULE = n + +export TopDIR ?= $(shell pwd) + +########### COMMON ################################# + +_OS_INTFS_FILES := os_dep/osdep_service.o \ + os_dep/linux/os_intfs.o \ + os_dep/linux/usb_intf.o \ + os_dep/linux/usb_ops_linux.o \ + os_dep/linux/ioctl_linux.o \ + os_dep/linux/xmit_linux.o \ + os_dep/linux/mlme_linux.o \ + os_dep/linux/recv_linux.o \ + os_dep/linux/ioctl_cfg80211.o \ + os_dep/linux/wifi_regd.o \ + os_dep/linux/rtw_proc.o + +ifeq ($(CONFIG_MP_INCLUDED), y) +_OS_INTFS_FILES += os_dep/linux/ioctl_mp.o +endif + +_HAL_INTFS_FILES := hal/hal_intf.o \ + hal/hal_com.o \ + hal/hal_com_phycfg.o \ + hal/hal_phy.o \ + hal/hal_dm.o \ + hal/hal_btcoex.o \ + hal/hal_mp.o \ + hal/hal_hci/hal_usb.o \ + hal/led/hal_usb_led.o + + +_OUTSRC_FILES := hal/phydm/phydm_debug.o \ + hal/phydm/phydm_antdiv.o\ + hal/phydm/phydm_antdect.o\ + hal/phydm/phydm_interface.o\ + hal/phydm/phydm_hwconfig.o\ + hal/phydm/phydm.o\ + hal/phydm/halphyrf_ce.o\ + hal/phydm/phydm_edcaturbocheck.o\ + hal/phydm/phydm_dig.o\ + hal/phydm/phydm_pathdiv.o\ + hal/phydm/phydm_rainfo.o\ + hal/phydm/phydm_dynamicbbpowersaving.o\ + hal/phydm/phydm_powertracking_ce.o\ + hal/phydm/phydm_dynamictxpower.o\ + hal/phydm/phydm_adaptivity.o\ + hal/phydm/phydm_cfotracking.o\ + hal/phydm/phydm_noisemonitor.o\ + hal/phydm/phydm_acs.o\ + hal/phydm/phydm_beamforming.o\ + hal/phydm/txbf/halcomtxbf.o\ + hal/phydm/txbf/haltxbfinterface.o + +ifeq ($(CONFIG_BT_COEXIST), y) +EXTRA_CFLAGS += -I$(src)/hal/btc +_OUTSRC_FILES += hal/btc/HalBtc8192e1Ant.o \ + hal/btc/HalBtc8192e2Ant.o \ + hal/btc/HalBtc8723b1Ant.o \ + hal/btc/HalBtc8723b2Ant.o \ + hal/btc/HalBtc8812a1Ant.o \ + hal/btc/HalBtc8812a2Ant.o \ + hal/btc/HalBtc8821a1Ant.o \ + hal/btc/HalBtc8821a2Ant.o \ + hal/btc/HalBtc8821aCsr2Ant.o \ + hal/btc/HalBtc8703b1Ant.o \ + hal/btc/HalBtc8703b2Ant.o +endif + +########### HAL_RTL8188F ################################# +ifeq ($(CONFIG_RTL8188F), y) + +EXTRA_CFLAGS += -DCONFIG_RTL8188F + +_HAL_INTFS_FILES += hal/HalPwrSeqCmd.o \ + hal/rtl8188f/Hal8188FPwrSeq.o\ + hal/rtl8188f/rtl8188f_sreset.o + +_HAL_INTFS_FILES += hal/rtl8188f/rtl8188f_hal_init.o \ + hal/rtl8188f/rtl8188f_phycfg.o \ + hal/rtl8188f/rtl8188f_rf6052.o \ + hal/rtl8188f/rtl8188f_dm.o \ + hal/rtl8188f/rtl8188f_rxdesc.o \ + hal/rtl8188f/rtl8188f_cmd.o \ + + +_HAL_INTFS_FILES += \ + hal/rtl8188f/usb/usb_halinit.o \ + hal/rtl8188f/usb/rtl8188fu_led.o \ + hal/rtl8188f/usb/rtl8188fu_xmit.o \ + hal/rtl8188f/usb/rtl8188fu_recv.o + +ifeq ($(CONFIG_PCI_HCI), y) +_HAL_INTFS_FILES += hal/rtl8188f/usb/usb_ops_linux.o +else +_HAL_INTFS_FILES += hal/rtl8188f/usb/usb_ops.o +endif + +ifeq ($(CONFIG_USB_HCI), y) +_HAL_INTFS_FILES +=hal/efuse/rtl8188f/HalEfuseMask8188F_USB.o +endif + +_OUTSRC_FILES += hal/phydm/rtl8188f/halhwimg8188f_bb.o\ + hal/phydm/rtl8188f/halhwimg8188f_mac.o\ + hal/phydm/rtl8188f/halhwimg8188f_rf.o\ + hal/phydm/rtl8188f/halhwimg8188f_fw.o\ + hal/phydm/rtl8188f/phydm_regconfig8188f.o\ + hal/phydm/rtl8188f/halphyrf_8188f.o \ + hal/phydm/rtl8188f/phydm_rtl8188f.o + +endif + +########### END OF PATH ################################# + + +ifeq ($(CONFIG_USB_HCI), y) +ifeq ($(CONFIG_USB_AUTOSUSPEND), y) +EXTRA_CFLAGS += -DCONFIG_USB_AUTOSUSPEND +endif +endif + +ifeq ($(CONFIG_MP_INCLUDED), y) +#MODULE_NAME := $(MODULE_NAME)_mp +EXTRA_CFLAGS += -DCONFIG_MP_INCLUDED +endif + +ifeq ($(CONFIG_POWER_SAVING), y) +EXTRA_CFLAGS += -DCONFIG_POWER_SAVING +endif + +ifeq ($(CONFIG_HW_PWRP_DETECTION), y) +EXTRA_CFLAGS += -DCONFIG_HW_PWRP_DETECTION +endif + +ifeq ($(CONFIG_WIFI_TEST), y) +EXTRA_CFLAGS += -DCONFIG_WIFI_TEST +endif + +ifeq ($(CONFIG_BT_COEXIST), y) +EXTRA_CFLAGS += -DCONFIG_BT_COEXIST +endif + +ifeq ($(CONFIG_INTEL_WIDI), y) +EXTRA_CFLAGS += -DCONFIG_INTEL_WIDI +endif + +ifeq ($(CONFIG_WAPI_SUPPORT), y) +EXTRA_CFLAGS += -DCONFIG_WAPI_SUPPORT +endif + + +ifeq ($(CONFIG_EFUSE_CONFIG_FILE), y) +EXTRA_CFLAGS += -DCONFIG_EFUSE_CONFIG_FILE + +#EFUSE_MAP_PATH +USER_EFUSE_MAP_PATH ?= +ifneq ($(USER_EFUSE_MAP_PATH),) +EXTRA_CFLAGS += -DEFUSE_MAP_PATH=\"$(USER_EFUSE_MAP_PATH)\" +else ifeq ($(MODULE_NAME), 8189es) +EXTRA_CFLAGS += -DEFUSE_MAP_PATH=\"/system/etc/wifi/wifi_efuse_8189e.map\" +else ifeq ($(MODULE_NAME), 8723bs) +EXTRA_CFLAGS += -DEFUSE_MAP_PATH=\"/system/etc/wifi/wifi_efuse_8723bs.map\" +else +EXTRA_CFLAGS += -DEFUSE_MAP_PATH=\"/system/etc/wifi/wifi_efuse_$(MODULE_NAME).map\" +endif + +#WIFIMAC_PATH +USER_WIFIMAC_PATH ?= +ifneq ($(USER_WIFIMAC_PATH),) +EXTRA_CFLAGS += -DWIFIMAC_PATH=\"$(USER_WIFIMAC_PATH)\" +else +EXTRA_CFLAGS += -DWIFIMAC_PATH=\"/data/wifimac.txt\" +endif + +endif + +ifeq ($(CONFIG_EXT_CLK), y) +EXTRA_CFLAGS += -DCONFIG_EXT_CLK +endif + +ifeq ($(CONFIG_TRAFFIC_PROTECT), y) +EXTRA_CFLAGS += -DCONFIG_TRAFFIC_PROTECT +endif + +ifeq ($(CONFIG_LOAD_PHY_PARA_FROM_FILE), y) +EXTRA_CFLAGS += -DCONFIG_LOAD_PHY_PARA_FROM_FILE +#EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER +#EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH=\"/lib/firmware/\" +EXTRA_CFLAGS += -DREALTEK_CONFIG_PATH=\"\" +endif + +ifeq ($(CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY), y) +EXTRA_CFLAGS += -DCONFIG_CALIBRATE_TX_POWER_BY_REGULATORY +endif + +ifeq ($(CONFIG_CALIBRATE_TX_POWER_TO_MAX), y) +EXTRA_CFLAGS += -DCONFIG_CALIBRATE_TX_POWER_TO_MAX +endif + +ifeq ($(CONFIG_RTW_ADAPTIVITY_EN), disable) +EXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_EN=0 +else ifeq ($(CONFIG_RTW_ADAPTIVITY_EN), enable) +EXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_EN=1 +endif + +ifeq ($(CONFIG_RTW_ADAPTIVITY_MODE), normal) +EXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_MODE=0 +else ifeq ($(CONFIG_RTW_ADAPTIVITY_MODE), carrier_sense) +EXTRA_CFLAGS += -DCONFIG_RTW_ADAPTIVITY_MODE=1 +endif + +ifeq ($(CONFIG_SIGNAL_SCALE_MAPPING), y) +EXTRA_CFLAGS += -DCONFIG_SIGNAL_SCALE_MAPPING +endif + +ifeq ($(CONFIG_80211W), y) +EXTRA_CFLAGS += -DCONFIG_IEEE80211W +endif + +ifeq ($(CONFIG_PNO_SUPPORT), y) +EXTRA_CFLAGS += -DCONFIG_PNO_SUPPORT +ifeq ($(CONFIG_PNO_SET_DEBUG), y) +EXTRA_CFLAGS += -DCONFIG_PNO_SET_DEBUG +endif +endif + +ifeq ($(CONFIG_GPIO_WAKEUP), y) +EXTRA_CFLAGS += -DCONFIG_GPIO_WAKEUP +ifeq ($(CONFIG_HIGH_ACTIVE), y) +EXTRA_CFLAGS += -DHIGH_ACTIVE=1 +else +EXTRA_CFLAGS += -DHIGH_ACTIVE=0 +endif +endif + +ifneq ($(CONFIG_WAKEUP_GPIO_IDX), default) +EXTRA_CFLAGS += -DWAKEUP_GPIO_IDX=$(CONFIG_WAKEUP_GPIO_IDX) +endif + +ifeq ($(CONFIG_RTW_SDIO_PM_KEEP_POWER), y) +ifeq ($(CONFIG_SDIO_HCI), y) +EXTRA_CFLAGS += -DCONFIG_RTW_SDIO_PM_KEEP_POWER +endif +endif + +ifeq ($(CONFIG_REDUCE_TX_CPU_LOADING), y) +EXTRA_CFLAGS += -DCONFIG_REDUCE_TX_CPU_LOADING +endif + +ifeq ($(CONFIG_BR_EXT), y) +BR_NAME = br0 +EXTRA_CFLAGS += -DCONFIG_BR_EXT +EXTRA_CFLAGS += '-DCONFIG_BR_EXT_BRNAME="'$(BR_NAME)'"' +endif + +ifeq ($(CONFIG_ANTENNA_DIVERSITY), y) +EXTRA_CFLAGS += -DCONFIG_ANTENNA_DIVERSITY +endif + +ifeq ($(CONFIG_TDLS), y) +EXTRA_CFLAGS += -DCONFIG_TDLS +endif + +ifeq ($(CONFIG_WIFI_MONITOR), y) +EXTRA_CFLAGS += -DCONFIG_WIFI_MONITOR +endif + +ifeq ($(CONFIG_MP_VHT_HW_TX_MODE), y) +EXTRA_CFLAGS += -DCONFIG_MP_VHT_HW_TX_MODE +ifeq ($(CONFIG_PLATFORM_I386_PC), y) +## For I386 X86 ToolChain use Hardware FLOATING +EXTRA_CFLAGS += -mhard-float +else +## For ARM ToolChain use Hardware FLOATING +EXTRA_CFLAGS += -mfloat-abi=hard +endif +endif + +EXTRA_CFLAGS += -DDM_ODM_SUPPORT_TYPE=0x04 + +ifeq ($(CONFIG_PLATFORM_I386_PC), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT +SUBARCH := $(shell uname -m | sed -e "s/i.86/i386/; s/ppc/powerpc/; s/armv.l/arm/; s/aarch64/arm64/;") +ARCH ?= $(SUBARCH) +CROSS_COMPILE ?= +KVER := $(shell uname -r) +KSRC := /lib/modules/$(KVER)/build +MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/ +INSTALL_PREFIX := +endif + +ifeq ($(CONFIG_PLATFORM_RISCV_K230), y) +EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN +EXTRA_CFLAGS += -DCONFIG_IOCTL_CFG80211 -DRTW_USE_CFG80211_STA_EVENT +endif + +ifneq ($(KERNELRELEASE),) + +rtk_core := core/rtw_cmd.o \ + core/rtw_security.o \ + core/rtw_debug.o \ + core/rtw_io.o \ + core/rtw_ioctl_query.o \ + core/rtw_ioctl_set.o \ + core/rtw_ieee80211.o \ + core/rtw_mlme.o \ + core/rtw_mlme_ext.o \ + core/rtw_wlan_util.o \ + core/rtw_vht.o \ + core/rtw_pwrctrl.o \ + core/rtw_rf.o \ + core/rtw_recv.o \ + core/rtw_sta_mgt.o \ + core/rtw_ap.o \ + core/rtw_xmit.o \ + core/rtw_p2p.o \ + core/rtw_tdls.o \ + core/rtw_br_ext.o \ + core/rtw_iol.o \ + core/rtw_sreset.o \ + core/rtw_btcoex.o \ + core/rtw_beamforming.o \ + core/rtw_odm.o \ + core/efuse/rtw_efuse.o + +rtl8188fu-y += $(rtk_core) + +rtl8188fu-$(CONFIG_INTEL_WIDI) += core/rtw_intel_widi.o + +rtl8188fu-$(CONFIG_WAPI_SUPPORT) += core/rtw_wapi.o \ + core/rtw_wapi_sms4.o + +rtl8188fu-y += $(_OS_INTFS_FILES) +rtl8188fu-y += $(_HAL_INTFS_FILES) +rtl8188fu-y += $(_OUTSRC_FILES) +rtl8188fu-y += $(_PLATFORM_FILES) + +rtl8188fu-$(CONFIG_MP_INCLUDED) += core/rtw_mp.o \ + core/rtw_mp_ioctl.o + +ifeq ($(CONFIG_RTL8723B), y) +rtl8188fu-$(CONFIG_MP_INCLUDED)+= core/rtw_bt_mp.o +endif + +obj-$(CONFIG_RTL8188FU) := rtl8188fu.o + +else + +export CONFIG_RTL8188FU = m + +all: modules + +modules: + $(MAKE) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) -C $(KSRC) M=$(shell pwd) modules + +strip: + $(CROSS_COMPILE)strip $(MODULE_NAME).ko --strip-unneeded + +installfw: + mkdir -p /lib/firmware/rtlwifi + cp -n firmware/* /lib/firmware/rtlwifi/. + +install: + install -p -m 644 $(MODULE_NAME).ko $(MODDESTDIR) + /sbin/depmod -a ${KVER} + +uninstall: + rm -f $(MODDESTDIR)/$(MODULE_NAME).ko + /sbin/depmod -a ${KVER} + +config_r: + @echo "make config" + /bin/bash script/Configure script/config.in + + +.PHONY: modules clean + +clean: + cd hal/phydm/ ; rm -fr */*.mod.c */*.mod */*.o */.*.cmd */*.ko + cd hal/phydm/ ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko + cd hal/led ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko + cd hal ; rm -fr */*/*.mod.c */*/*.mod */*/*.o */*/.*.cmd */*/*.ko + cd hal ; rm -fr */*.mod.c */*.mod */*.o */.*.cmd */*.ko + cd hal ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko + cd core/efuse ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko + cd core ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko + cd os_dep/linux ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko + cd os_dep ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko + rm -fr Module.symvers ; rm -fr Module.markers ; rm -fr modules.order + rm -fr *.mod.c *.mod *.o .*.cmd *.ko *~ + rm -fr .tmp_versions +endif diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/README.md b/src/little/linux/drivers/net/wireless/rtl8188fu/README.md new file mode 100755 index 000000000..6680124eb --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/README.md @@ -0,0 +1,51 @@ +rtl8188fu for linux +=================== + + +**PSA** public service announcement +------------------------------------- +This driver will only work with kernels <= v5.10 +.. there no use for a new kernel +.. sorry for that + +the purpose of this repository is to rip/strip unneeded parts from the vendor driver +because of .. + +rtl8188fu linux driver for wireless bgn device + +end of PSA +---------- + +Note: +This is an USB2 only adapter, +Source is ripped out of firefly source tree found at +https://gitlab.com/TeeFirefly/linux-kernel + +If one USB-ID is missing, please mail me. + +build/load/function tested with v4.19 + +Building and install driver +--------------------------- + +for building type +`make` + +for load the driver +`sudo modprobe cfg80211` +`sudo insmod rtl8188fu.ko` + +You need to install the needed fw with +`sudo make installfw` + +If you need to crosscompile use +`ARCH= CROSS_COMPILE= KSRC=` +while calling `make` i.e. + +`make ARCH="arm" CROSS_COMPILE=armv5tel-softfloat-linux-gnueabi- KSRC=/home/linux-master modules` + +Please use prefix **rtl8188fu** if you want to mail me +But please please don't, I have enough to do. +TIA + +Hans Ulli Kroll diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/efuse/rtw_efuse.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/efuse/rtw_efuse.c new file mode 100644 index 000000000..6e6c034e1 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/efuse/rtw_efuse.c @@ -0,0 +1,1766 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_EFUSE_C_ + +#include +#include + +#include "../hal/efuse/efuse_mask.h" + +/*------------------------Define local variable------------------------------*/ +u8 fakeEfuseBank=0; +u32 fakeEfuseUsedBytes=0; +u8 fakeEfuseContent[EFUSE_MAX_HW_SIZE]={0}; +u8 fakeEfuseInitMap[EFUSE_MAX_MAP_LEN]={0}; +u8 fakeEfuseModifiedMap[EFUSE_MAX_MAP_LEN]={0}; + +u32 BTEfuseUsedBytes=0; +u8 BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; +u8 BTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN]={0}; +u8 BTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN]={0}; + +u32 fakeBTEfuseUsedBytes=0; +u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; +u8 fakeBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN]={0}; +u8 fakeBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN]={0}; + +u8 maskfileBuffer[32]; +/*------------------------Define local variable------------------------------*/ + +//------------------------------------------------------------------------------ +#define REG_EFUSE_CTRL 0x0030 +#define EFUSE_CTRL REG_EFUSE_CTRL // E-Fuse Control. +//------------------------------------------------------------------------------ + +BOOLEAN +Efuse_Read1ByteFromFakeContent( + IN PADAPTER pAdapter, + IN u16 Offset, + IN OUT u8 *Value ); +BOOLEAN +Efuse_Read1ByteFromFakeContent( + IN PADAPTER pAdapter, + IN u16 Offset, + IN OUT u8 *Value ) +{ + if(Offset >= EFUSE_MAX_HW_SIZE) + { + return _FALSE; + } + //DbgPrint("Read fake content, offset = %d\n", Offset); + if(fakeEfuseBank == 0) + *Value = fakeEfuseContent[Offset]; + else + *Value = fakeBTEfuseContent[fakeEfuseBank-1][Offset]; + return _TRUE; +} + +BOOLEAN +Efuse_Write1ByteToFakeContent( + IN PADAPTER pAdapter, + IN u16 Offset, + IN u8 Value ); +BOOLEAN +Efuse_Write1ByteToFakeContent( + IN PADAPTER pAdapter, + IN u16 Offset, + IN u8 Value ) +{ + if(Offset >= EFUSE_MAX_HW_SIZE) + { + return _FALSE; + } + if(fakeEfuseBank == 0) + fakeEfuseContent[Offset] = Value; + else + { + fakeBTEfuseContent[fakeEfuseBank-1][Offset] = Value; + } + return _TRUE; +} + +/*----------------------------------------------------------------------------- + * Function: Efuse_PowerSwitch + * + * Overview: When we want to enable write operation, we should change to + * pwr on state. When we stop write, we should switch to 500k mode + * and disable LDO 2.5V. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/17/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +VOID +Efuse_PowerSwitch( + IN PADAPTER pAdapter, + IN u8 bWrite, + IN u8 PwrState) +{ + pAdapter->HalFunc.EfusePowerSwitch(pAdapter, bWrite, PwrState); +} + +VOID +BTEfuse_PowerSwitch( + IN PADAPTER pAdapter, + IN u8 bWrite, + IN u8 PwrState) +{ + if(pAdapter->HalFunc.BTEfusePowerSwitch) + pAdapter->HalFunc.BTEfusePowerSwitch(pAdapter, bWrite, PwrState); +} + +/*----------------------------------------------------------------------------- + * Function: efuse_GetCurrentSize + * + * Overview: Get current efuse size!!! + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/16/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +u16 +Efuse_GetCurrentSize( + IN PADAPTER pAdapter, + IN u8 efuseType, + IN BOOLEAN bPseudoTest) +{ + u16 ret=0; + + ret = pAdapter->HalFunc.EfuseGetCurrentSize(pAdapter, efuseType, bPseudoTest); + + return ret; +} + +/* 11/16/2008 MH Add description. Get current efuse area enabled word!!. */ +u8 +Efuse_CalculateWordCnts(IN u8 word_en) +{ + u8 word_cnts = 0; + if(!(word_en & BIT(0))) word_cnts++; // 0 : write enable + if(!(word_en & BIT(1))) word_cnts++; + if(!(word_en & BIT(2))) word_cnts++; + if(!(word_en & BIT(3))) word_cnts++; + return word_cnts; +} + +// +// Description: +// Execute E-Fuse read byte operation. +// Refered from SD1 Richard. +// +// Assumption: +// 1. Boot from E-Fuse and successfully auto-load. +// 2. PASSIVE_LEVEL (USB interface) +// +// Created by Roger, 2008.10.21. +// +VOID +ReadEFuseByte( + PADAPTER Adapter, + u16 _offset, + u8 *pbuf, + IN BOOLEAN bPseudoTest) +{ + u32 value32; + u8 readbyte; + u16 retry; + //u32 start=rtw_get_current_time(); + + if(bPseudoTest) + { + Efuse_Read1ByteFromFakeContent(Adapter, _offset, pbuf); + return; + } + if (IS_HARDWARE_TYPE_8723B(Adapter)) + { + // <20130121, Kordan> For SMIC S55 EFUSE specificatoin. + //0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) + PHY_SetMacReg(Adapter, EFUSE_TEST, BIT11, 0); + } + //Write Address + rtw_write8(Adapter, EFUSE_CTRL+1, (_offset & 0xff)); + readbyte = rtw_read8(Adapter, EFUSE_CTRL+2); + rtw_write8(Adapter, EFUSE_CTRL+2, ((_offset >> 8) & 0x03) | (readbyte & 0xfc)); + + //Write bit 32 0 + readbyte = rtw_read8(Adapter, EFUSE_CTRL+3); + rtw_write8(Adapter, EFUSE_CTRL+3, (readbyte & 0x7f)); + + //Check bit 32 read-ready + retry = 0; + value32 = rtw_read32(Adapter, EFUSE_CTRL); + //while(!(((value32 >> 24) & 0xff) & 0x80) && (retry<10)) + while(!(((value32 >> 24) & 0xff) & 0x80) && (retry<10000)) + { + value32 = rtw_read32(Adapter, EFUSE_CTRL); + retry++; + } + + // 20100205 Joseph: Add delay suggested by SD1 Victor. + // This fix the problem that Efuse read error in high temperature condition. + // Designer says that there shall be some delay after ready bit is set, or the + // result will always stay on last data we read. + rtw_udelay_os(50); + value32 = rtw_read32(Adapter, EFUSE_CTRL); + + *pbuf = (u8)(value32 & 0xff); + //DBG_871X("ReadEFuseByte _offset:%08u, in %d ms\n",_offset ,rtw_get_passing_time_ms(start)); + +} + +// +// Description: +// 1. Execute E-Fuse read byte operation according as map offset and +// save to E-Fuse table. +// 2. Refered from SD1 Richard. +// +// Assumption: +// 1. Boot from E-Fuse and successfully auto-load. +// 2. PASSIVE_LEVEL (USB interface) +// +// Created by Roger, 2008.10.21. +// +// 2008/12/12 MH 1. Reorganize code flow and reserve bytes. and add description. +// 2. Add efuse utilization collect. +// 2008/12/22 MH Read Efuse must check if we write section 1 data again!!! Sec1 +// write addr must be after sec5. +// + +VOID +efuse_ReadEFuse( + PADAPTER Adapter, + u8 efuseType, + u16 _offset, + u16 _size_byte, + u8 *pbuf, + IN BOOLEAN bPseudoTest + ); +VOID +efuse_ReadEFuse( + PADAPTER Adapter, + u8 efuseType, + u16 _offset, + u16 _size_byte, + u8 *pbuf, + IN BOOLEAN bPseudoTest + ) +{ + Adapter->HalFunc.ReadEFuse(Adapter, efuseType, _offset, _size_byte, pbuf, bPseudoTest); +} + +VOID +EFUSE_GetEfuseDefinition( + IN PADAPTER pAdapter, + IN u8 efuseType, + IN u8 type, + OUT void *pOut, + IN BOOLEAN bPseudoTest + ) +{ + pAdapter->HalFunc.EFUSEGetEfuseDefinition(pAdapter, efuseType, type, pOut, bPseudoTest); +} + +/*----------------------------------------------------------------------------- + * Function: EFUSE_Read1Byte + * + * Overview: Copy from WMAC fot EFUSE read 1 byte. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 09/23/2008 MHC Copy from WMAC. + * + *---------------------------------------------------------------------------*/ +u8 +EFUSE_Read1Byte( + IN PADAPTER Adapter, + IN u16 Address) +{ + u8 data; + u8 Bytetemp = {0x00}; + u8 temp = {0x00}; + u32 k=0; + u16 contentLen=0; + + EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI , TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&contentLen, _FALSE); + + if (Address < contentLen) //E-fuse 512Byte + { + //Write E-fuse Register address bit0~7 + temp = Address & 0xFF; + rtw_write8(Adapter, EFUSE_CTRL+1, temp); + Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+2); + //Write E-fuse Register address bit8~9 + temp = ((Address >> 8) & 0x03) | (Bytetemp & 0xFC); + rtw_write8(Adapter, EFUSE_CTRL+2, temp); + + //Write 0x30[31]=0 + Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3); + temp = Bytetemp & 0x7F; + rtw_write8(Adapter, EFUSE_CTRL+3, temp); + + //Wait Write-ready (0x30[31]=1) + Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3); + while(!(Bytetemp & 0x80)) + { + Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3); + k++; + if(k==1000) + { + k=0; + break; + } + } + data=rtw_read8(Adapter, EFUSE_CTRL); + return data; + } + else + return 0xFF; + +}/* EFUSE_Read1Byte */ + +/*----------------------------------------------------------------------------- + * Function: EFUSE_Write1Byte + * + * Overview: Copy from WMAC fot EFUSE write 1 byte. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 09/23/2008 MHC Copy from WMAC. + * + *---------------------------------------------------------------------------*/ + +void +EFUSE_Write1Byte( + IN PADAPTER Adapter, + IN u16 Address, + IN u8 Value); +void +EFUSE_Write1Byte( + IN PADAPTER Adapter, + IN u16 Address, + IN u8 Value) +{ + u8 Bytetemp = {0x00}; + u8 temp = {0x00}; + u32 k=0; + u16 contentLen=0; + + //RT_TRACE(COMP_EFUSE, DBG_LOUD, ("Addr=%x Data =%x\n", Address, Value)); + EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI , TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&contentLen, _FALSE); + + if( Address < contentLen) //E-fuse 512Byte + { + rtw_write8(Adapter, EFUSE_CTRL, Value); + + //Write E-fuse Register address bit0~7 + temp = Address & 0xFF; + rtw_write8(Adapter, EFUSE_CTRL+1, temp); + Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+2); + + //Write E-fuse Register address bit8~9 + temp = ((Address >> 8) & 0x03) | (Bytetemp & 0xFC); + rtw_write8(Adapter, EFUSE_CTRL+2, temp); + + //Write 0x30[31]=1 + Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3); + temp = Bytetemp | 0x80; + rtw_write8(Adapter, EFUSE_CTRL+3, temp); + + //Wait Write-ready (0x30[31]=0) + Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3); + while(Bytetemp & 0x80) + { + Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3); + k++; + if(k==100) + { + k=0; + break; + } + } + } +}/* EFUSE_Write1Byte */ + + +/* 11/16/2008 MH Read one byte from real Efuse. */ +u8 +efuse_OneByteRead( + IN PADAPTER pAdapter, + IN u16 addr, + IN u8 *data, + IN BOOLEAN bPseudoTest) +{ + u32 tmpidx = 0; + u8 bResult; + u8 readbyte; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + //DBG_871X("===> EFUSE_OneByteRead(), addr = %x\n", addr); + //DBG_871X("===> EFUSE_OneByteRead() start, 0x34 = 0x%X\n", rtw_read32(pAdapter, EFUSE_TEST)); + + if(bPseudoTest) + { + bResult = Efuse_Read1ByteFromFakeContent(pAdapter, addr, data); + return bResult; + } + + if( IS_HARDWARE_TYPE_8723B(pAdapter) || + (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->VersionID))) || + (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->VersionID)) + ) + { + // <20130121, Kordan> For SMIC EFUSE specificatoin. + //0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) + //PHY_SetMacReg(pAdapter, 0x34, BIT11, 0); + rtw_write16(pAdapter, 0x34, rtw_read16(pAdapter,0x34)& (~BIT11) ); + } + + // -----------------e-fuse reg ctrl --------------------------------- + //address + rtw_write8(pAdapter, EFUSE_CTRL+1, (u8)(addr&0xff)); + rtw_write8(pAdapter, EFUSE_CTRL+2, ((u8)((addr>>8) &0x03) ) | + (rtw_read8(pAdapter, EFUSE_CTRL+2)&0xFC )); + + //rtw_write8(pAdapter, EFUSE_CTRL+3, 0x72);//read cmd + //Write bit 32 0 + readbyte = rtw_read8(pAdapter, EFUSE_CTRL+3); + rtw_write8(pAdapter, EFUSE_CTRL+3, (readbyte & 0x7f)); + + while(!(0x80 &rtw_read8(pAdapter, EFUSE_CTRL+3))&&(tmpidx<1000)) + { + rtw_mdelay_os(1); + tmpidx++; + } + if(tmpidx<100) + { + *data=rtw_read8(pAdapter, EFUSE_CTRL); + bResult = _TRUE; + } + else + { + *data = 0xff; + bResult = _FALSE; + DBG_871X("%s: [ERROR] addr=0x%x bResult=%d time out 1s !!!\n", __FUNCTION__, addr, bResult); + DBG_871X("%s: [ERROR] EFUSE_CTRL =0x%08x !!!\n", __FUNCTION__, rtw_read32(pAdapter, EFUSE_CTRL)); + } + + return bResult; +} + +/* 11/16/2008 MH Write one byte to reald Efuse. */ +u8 +efuse_OneByteWrite( + IN PADAPTER pAdapter, + IN u16 addr, + IN u8 data, + IN BOOLEAN bPseudoTest) +{ + u8 tmpidx = 0; + u8 bResult=_FALSE; + u32 efuseValue = 0; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + //DBG_871X("===> EFUSE_OneByteWrite(), addr = %x data=%x\n", addr, data); + //DBG_871X("===> EFUSE_OneByteWrite() start, 0x34 = 0x%X\n", rtw_read32(pAdapter, EFUSE_TEST)); + + if(bPseudoTest) + { + bResult = Efuse_Write1ByteToFakeContent(pAdapter, addr, data); + return bResult; + } + + Efuse_PowerSwitch(pAdapter, _TRUE, _TRUE); + + // -----------------e-fuse reg ctrl --------------------------------- + //address + + + efuseValue = rtw_read32(pAdapter, EFUSE_CTRL); + efuseValue |= (BIT21|BIT31); + efuseValue &= ~(0x3FFFF); + efuseValue |= ((addr<<8 | data) & 0x3FFFF); + + // <20130227, Kordan> 8192E MP chip A-cut had better not set 0x34[11] until B-Cut. + if ( IS_HARDWARE_TYPE_8723B(pAdapter) || + (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->VersionID))) || + (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->VersionID)) + ) { + // <20130121, Kordan> For SMIC EFUSE specificatoin. + //0x34[11]: SW force PGMEN input of efuse to high. (for the bank selected by 0x34[9:8]) + //PHY_SetMacReg(pAdapter, 0x34, BIT11, 1); + rtw_write16(pAdapter, 0x34, rtw_read16(pAdapter,0x34)| (BIT11) ); + rtw_write32(pAdapter, EFUSE_CTRL, 0x90600000|((addr<<8 | data)) ); + } + else + { + rtw_write32(pAdapter, EFUSE_CTRL, efuseValue); + } + + while((0x80 & rtw_read8(pAdapter, EFUSE_CTRL+3)) && (tmpidx<100) ){ + rtw_mdelay_os(1); + tmpidx++; + } + + if(tmpidx<100) + { + bResult = _TRUE; + } + else + { + bResult = _FALSE; + DBG_871X("%s: [ERROR] addr=0x%x ,efuseValue=0x%x ,bResult=%d time out 1s !!! \n", + __FUNCTION__, addr, efuseValue, bResult); + DBG_871X("%s: [ERROR] EFUSE_CTRL =0x%08x !!!\n", __FUNCTION__, rtw_read32(pAdapter, EFUSE_CTRL)); + } + + // disable Efuse program enable + if ( IS_HARDWARE_TYPE_8723B(pAdapter) || + (IS_HARDWARE_TYPE_8192E(pAdapter) && (!IS_A_CUT(pHalData->VersionID))) || + (IS_VENDOR_8188E_I_CUT_SERIES(pAdapter)) || (IS_CHIP_VENDOR_SMIC(pHalData->VersionID)) + ) { + PHY_SetMacReg(pAdapter, EFUSE_TEST, BIT(11), 0); + } + + Efuse_PowerSwitch(pAdapter, _TRUE, _FALSE); + + return bResult; +} + +int +Efuse_PgPacketRead( IN PADAPTER pAdapter, + IN u8 offset, + IN u8 *data, + IN BOOLEAN bPseudoTest) +{ + int ret=0; + + ret = pAdapter->HalFunc.Efuse_PgPacketRead(pAdapter, offset, data, bPseudoTest); + + return ret; +} + +int +Efuse_PgPacketWrite(IN PADAPTER pAdapter, + IN u8 offset, + IN u8 word_en, + IN u8 *data, + IN BOOLEAN bPseudoTest) +{ + int ret; + + ret = pAdapter->HalFunc.Efuse_PgPacketWrite(pAdapter, offset, word_en, data, bPseudoTest); + + return ret; +} + + +int +Efuse_PgPacketWrite_BT(IN PADAPTER pAdapter, + IN u8 offset, + IN u8 word_en, + IN u8 *data, + IN BOOLEAN bPseudoTest) +{ + int ret; + + ret = pAdapter->HalFunc.Efuse_PgPacketWrite_BT(pAdapter, offset, word_en, data, bPseudoTest); + + return ret; +} + +/*----------------------------------------------------------------------------- + * Function: efuse_WordEnableDataRead + * + * Overview: Read allowed word in current efuse section data. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/16/2008 MHC Create Version 0. + * 11/21/2008 MHC Fix Write bug when we only enable late word. + * + *---------------------------------------------------------------------------*/ +void +efuse_WordEnableDataRead(IN u8 word_en, + IN u8 *sourdata, + IN u8 *targetdata) +{ + if (!(word_en&BIT(0))) + { + targetdata[0] = sourdata[0]; + targetdata[1] = sourdata[1]; + } + if (!(word_en&BIT(1))) + { + targetdata[2] = sourdata[2]; + targetdata[3] = sourdata[3]; + } + if (!(word_en&BIT(2))) + { + targetdata[4] = sourdata[4]; + targetdata[5] = sourdata[5]; + } + if (!(word_en&BIT(3))) + { + targetdata[6] = sourdata[6]; + targetdata[7] = sourdata[7]; + } +} + + +u8 +Efuse_WordEnableDataWrite( IN PADAPTER pAdapter, + IN u16 efuse_addr, + IN u8 word_en, + IN u8 *data, + IN BOOLEAN bPseudoTest) +{ + u8 ret=0; + + ret = pAdapter->HalFunc.Efuse_WordEnableDataWrite(pAdapter, efuse_addr, word_en, data, bPseudoTest); + + return ret; +} + +static u8 efuse_read8(PADAPTER padapter, u16 address, u8 *value) +{ + return efuse_OneByteRead(padapter,address, value, _FALSE); +} + +static u8 efuse_write8(PADAPTER padapter, u16 address, u8 *value) +{ + return efuse_OneByteWrite(padapter,address, *value, _FALSE); +} + +/* + * read/wirte raw efuse data + */ +u8 rtw_efuse_access(PADAPTER padapter, u8 bWrite, u16 start_addr, u16 cnts, u8 *data) +{ + int i = 0; + u16 real_content_len = 0, max_available_size = 0; + u8 res = _FAIL ; + u8 (*rw8)(PADAPTER, u16, u8*); + + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&real_content_len, _FALSE); + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE); + + if (start_addr > real_content_len) + return _FAIL; + + if (_TRUE == bWrite) { + if ((start_addr + cnts) > max_available_size) + return _FAIL; + rw8 = &efuse_write8; + } else + rw8 = &efuse_read8; + + Efuse_PowerSwitch(padapter, bWrite, _TRUE); + + // e-fuse one byte read / write + for (i = 0; i < cnts; i++) { + if (start_addr >= real_content_len) { + res = _FAIL; + break; + } + + res = rw8(padapter, start_addr++, data++); + if (_FAIL == res) break; + } + + Efuse_PowerSwitch(padapter, bWrite, _FALSE); + + return res; +} +//------------------------------------------------------------------------------ +u16 efuse_GetMaxSize(PADAPTER padapter) +{ + u16 max_size; + + max_size = 0; + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI , TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_size, _FALSE); + return max_size; +} +//------------------------------------------------------------------------------ +u8 efuse_GetCurrentSize(PADAPTER padapter, u16 *size) +{ + Efuse_PowerSwitch(padapter, _FALSE, _TRUE); + *size = Efuse_GetCurrentSize(padapter, EFUSE_WIFI, _FALSE); + Efuse_PowerSwitch(padapter, _FALSE, _FALSE); + + return _SUCCESS; +} +//------------------------------------------------------------------------------ +u16 efuse_bt_GetMaxSize(PADAPTER padapter) +{ + u16 max_size; + + max_size = 0; + EFUSE_GetEfuseDefinition(padapter, EFUSE_BT , TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_size, _FALSE); + return max_size; +} + +u8 efuse_bt_GetCurrentSize(PADAPTER padapter, u16 *size) +{ + Efuse_PowerSwitch(padapter, _FALSE, _TRUE); + *size = Efuse_GetCurrentSize(padapter, EFUSE_BT, _FALSE); + Efuse_PowerSwitch(padapter, _FALSE, _FALSE); + + return _SUCCESS; +} + +u8 rtw_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) +{ + u16 mapLen=0; + + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE); + + if ((addr + cnts) > mapLen) + return _FAIL; + + Efuse_PowerSwitch(padapter, _FALSE, _TRUE); + + efuse_ReadEFuse(padapter, EFUSE_WIFI, addr, cnts, data, _FALSE); + + Efuse_PowerSwitch(padapter, _FALSE, _FALSE); + + return _SUCCESS; +} + +u8 rtw_BT_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) +{ + u16 mapLen=0; + + EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE); + + if ((addr + cnts) > mapLen) + return _FAIL; + + Efuse_PowerSwitch(padapter, _FALSE, _TRUE); + + efuse_ReadEFuse(padapter, EFUSE_BT, addr, cnts, data, _FALSE); + + Efuse_PowerSwitch(padapter, _FALSE, _FALSE); + + return _SUCCESS; +} + +BOOLEAN rtw_file_efuse_IsMasked( + PADAPTER pAdapter, + u16 Offset + ) +{ + int r = Offset/16; + int c = (Offset%16) / 2; + int result = 0; + + if(pAdapter->registrypriv.boffefusemask) + return FALSE; + + //DBG_871X(" %s ,Offset=%x r= %d , c=%d , maskfileBuffer[r]= %x \n",__func__,Offset,r,c,maskfileBuffer[r]); + if (c < 4) // Upper double word + result = (maskfileBuffer[r] & (0x10 << c)); + else + result = (maskfileBuffer[r] & (0x01 << (c-4))); + + return (result > 0) ? 0 : 1; + +} + + +u8 rtw_efuse_file_read(PADAPTER padapter,u8 *filepatch,u8 *buf,u32 len) +{ + char *ptmp; + char *ptmpbuf=NULL; + u32 rtStatus; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + ptmpbuf = rtw_zmalloc(2048); + + if (ptmpbuf == NULL) + return _FALSE; + + _rtw_memset(ptmpbuf,'\0',2048); + + rtStatus = rtw_retrieve_from_file(filepatch, ptmpbuf, 2048); + + if( rtStatus > 100 ) + { + u32 i,j; + for(i=0,j=0;jregistrypriv.boffefusemask) + return FALSE; + +#if DEV_BUS_TYPE == RT_USB_INTERFACE +#if defined(CONFIG_RTL8188E) + if (IS_HARDWARE_TYPE_8188E(pAdapter)) + return (IS_MASKED(8188E,_MUSB,Offset)) ? TRUE : FALSE; +#endif +#if defined(CONFIG_RTL8812A) + if (IS_HARDWARE_TYPE_8812(pAdapter)) + return (IS_MASKED(8812A,_MUSB,Offset)) ? TRUE : FALSE; +#endif +#if defined(CONFIG_RTL8821A) + //if (IS_HARDWARE_TYPE_8811AU(pAdapter)) + // return (IS_MASKED(8811A,_MUSB,Offset)) ? TRUE : FALSE; + if (IS_HARDWARE_TYPE_8821(pAdapter)) + return (IS_MASKED(8821A,_MUSB,Offset)) ? TRUE : FALSE; +#endif +#if defined(CONFIG_RTL8192E) + if (IS_HARDWARE_TYPE_8192E(pAdapter)) + return (IS_MASKED(8192E,_MUSB,Offset)) ? TRUE : FALSE; +#endif +#if defined(CONFIG_RTL8723B) + if (IS_HARDWARE_TYPE_8723B(pAdapter)) + return (IS_MASKED(8723B,_MUSB,Offset)) ? TRUE : FALSE; +#endif +#if defined(CONFIG_RTL8703B) + if (IS_HARDWARE_TYPE_8703B(pAdapter)) + return (IS_MASKED(8703B, _MUSB, Offset)) ? TRUE : FALSE; +#endif +#if defined(CONFIG_RTL8814A) + if (IS_HARDWARE_TYPE_8814A(pAdapter)) + return (IS_MASKED(8814A, _MUSB, Offset)) ? TRUE : FALSE; +#endif +#if defined(CONFIG_RTL8188F) + if (IS_HARDWARE_TYPE_8188F(pAdapter)) + return (IS_MASKED(8188F, _MUSB, Offset)) ? TRUE : FALSE; +#endif +#elif DEV_BUS_TYPE == RT_PCI_INTERFACE +#if defined(CONFIG_RTL8188E) + if (IS_HARDWARE_TYPE_8188E(pAdapter)) + return (IS_MASKED(8188E,_MPCIE,Offset)) ? TRUE : FALSE; +#endif +#if defined(CONFIG_RTL8192E) + if (IS_HARDWARE_TYPE_8192E(pAdapter)) + return (IS_MASKED(8192E,_MPCIE,Offset)) ? TRUE : FALSE; +#endif +#if defined(CONFIG_RTL8812A) + if (IS_HARDWARE_TYPE_8812(pAdapter)) + return (IS_MASKED(8812A,_MPCIE,Offset)) ? TRUE : FALSE; +#endif +#if defined(CONFIG_RTL8821A) + if (IS_HARDWARE_TYPE_8821(pAdapter)) + return (IS_MASKED(8821A,_MPCIE,Offset)) ? TRUE : FALSE; +#endif +#if defined(CONFIG_RTL8723B) + if (IS_HARDWARE_TYPE_8723B(pAdapter)) + return (IS_MASKED(8723B,_MPCIE,Offset)) ? TRUE : FALSE; +#endif +#if defined(CONFIG_RTL8814A) + if (IS_HARDWARE_TYPE_8814A(pAdapter)) + return (IS_MASKED(8814A, _MPCIE, Offset)) ? TRUE : FALSE; +#endif + //else if (IS_HARDWARE_TYPE_8821B(pAdapter)) + // return (IS_MASKED(8821B,_MPCIE,Offset)) ? TRUE : FALSE; + +#elif DEV_BUS_TYPE == RT_SDIO_INTERFACE +#ifdef CONFIG_RTL8188E_SDIO + if (IS_HARDWARE_TYPE_8188E(pAdapter)) + return (IS_MASKED(8188E,_MSDIO,Offset)) ? TRUE : FALSE; +#endif +#ifdef CONFIG_RTL8188F_SDIO + if (IS_HARDWARE_TYPE_8188F(pAdapter)) + return (IS_MASKED(8188F, _MSDIO, Offset)) ? TRUE : FALSE; +#endif +#endif + + return FALSE; +} + +#define RT_ASSERT_RET(expr) \ + if (!(expr)) { \ + printk("Assertion failed! %s at ......\n", #expr); \ + printk(" ......%s,%s, line=%d\n",__FILE__, __FUNCTION__, __LINE__); \ + return _FAIL; \ + } + + +//------------------------------------------------------------------------------ +u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) +{ + u8 offset, word_en; + u8 *map; + u8 newdata[PGPKT_DATA_SIZE]; + s32 i, j, idx, chk_total_byte; + u8 ret = _SUCCESS; + u16 mapLen = 0, startAddr = 0, efuse_max_available_len = 0; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; + + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE); + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_max_available_len, _FALSE); + + if ((addr + cnts) > mapLen) + return _FAIL; + + RT_ASSERT_RET(PGPKT_DATA_SIZE == 8); /* have to be 8 byte alignment */ + RT_ASSERT_RET((mapLen & 0x7) == 0); /* have to be PGPKT_DATA_SIZE alignment for memcpy */ + + map = rtw_zmalloc(mapLen); + if (map == NULL) + return _FAIL; + + _rtw_memset(map, 0xFF, mapLen); + + ret = rtw_efuse_map_read(padapter, 0, mapLen, map); + if (ret == _FAIL) + goto exit; + + if (padapter->registrypriv.boffefusemask == 0) { + for (i = 0; i < cnts; i++) { + if (padapter->registrypriv.bFileMaskEfuse == _TRUE) { + if (rtw_file_efuse_IsMasked(padapter, addr + i)) /*use file efuse mask. */ + data[i] = map[addr + i]; + } else { + if (efuse_IsMasked(padapter, addr + i)) + data[i] = map[addr + i]; + } + DBG_871X("%s , data[%d] = %x, map[addr+i]= %x\n", __func__, i, data[i], map[addr + i]); + } + } + /*Efuse_PowerSwitch(padapter, _TRUE, _TRUE);*/ + + chk_total_byte = 0; + idx = 0; + offset = (addr >> 3); + + while (idx < cnts) { + word_en = 0xF; + j = (addr + idx) & 0x7; + for (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) { + if (data[idx] != map[addr + idx]) + word_en &= ~BIT(i >> 1); + } + + if (word_en != 0xF) { + chk_total_byte += Efuse_CalculateWordCnts(word_en) * 2; + + if (offset >= EFUSE_MAX_SECTION_BASE) /* Over EFUSE_MAX_SECTION 16 for 2 ByteHeader */ + chk_total_byte += 2; + else + chk_total_byte += 1; + } + + offset++; + } + + DBG_871X("Total PG bytes Count = %d\n", chk_total_byte); + rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&startAddr); + + if (startAddr == 0) { + startAddr = Efuse_GetCurrentSize(padapter, EFUSE_WIFI, _FALSE); + DBG_871X("%s: Efuse_GetCurrentSize startAddr=%#X\n", __func__, startAddr); + } + /* RTW_DBG("%s: startAddr=%#X\n", __func__, startAddr); */ + + if ((startAddr + chk_total_byte) >= efuse_max_available_len) { + DBG_871X("%s: startAddr(0x%X) + PG data len %d >= efuse_max_available_len(0x%X)\n", + __func__, startAddr, chk_total_byte, efuse_max_available_len); + ret = _FAIL; + goto exit; + } + + + idx = 0; + offset = (addr >> 3); + while (idx < cnts) { + word_en = 0xF; + j = (addr + idx) & 0x7; + _rtw_memcpy(newdata, &map[offset << 3], PGPKT_DATA_SIZE); + for (i = j; i < PGPKT_DATA_SIZE && idx < cnts; i++, idx++) { + if (data[idx] != map[addr + idx]) { + word_en &= ~BIT(i >> 1); + newdata[i] = data[idx]; +#ifdef CONFIG_RTL8723B + if (addr + idx == 0x8) { + if (IS_C_CUT(pHalData->VersionID) || IS_B_CUT(pHalData->VersionID)) { + if (pHalData->adjuseVoltageVal == 6) { + newdata[i] = map[addr + idx]; + DBG_871X(" %s ,\n adjuseVoltageVal = %d ,newdata[%d] = %x\n", __func__, pHalData->adjuseVoltageVal, i, newdata[i]); + } + } + } +#endif + } + } + + if (word_en != 0xF) { + ret = Efuse_PgPacketWrite(padapter, offset, word_en, newdata, _FALSE); + DBG_871X("offset=%x\n", offset); + DBG_871X("word_en=%x\n", word_en); + + for (i = 0; i < PGPKT_DATA_SIZE; i++) + DBG_871X("data=%x \t", newdata[i]); + if (ret == _FAIL) + break; + } + + offset++; + } + + /*Efuse_PowerSwitch(padapter, _TRUE, _FALSE);*/ + +exit: + + rtw_mfree(map, mapLen); + + return ret; +} + +u8 rtw_efuse_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) +{ + u8 ret = _SUCCESS; + u16 mapLen = 0, i = 0; + + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE); + + ret = rtw_efuse_map_read(padapter, addr, cnts , data); + + if (padapter->registrypriv.boffefusemask == 0) { + + for (i = 0; i < cnts; i++) { + if (padapter->registrypriv.bFileMaskEfuse == _TRUE) { + if (rtw_file_efuse_IsMasked(padapter, addr+i)) /*use file efuse mask.*/ + data[i] = 0xff; + } else { + /*DBG_8192C(" %s , data[%d] = %x\n", __func__, i, data[i]);*/ + if (efuse_IsMasked(padapter, addr+i)) { + data[i] = 0xff; + /*DBG_8192C(" %s ,mask data[%d] = %x\n", __func__, i, data[i]);*/ + } + } + } + + } + return ret; + +} + +u8 rtw_BT_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) +{ + u8 offset, word_en; + u8 *map; + u8 newdata[PGPKT_DATA_SIZE]; + s32 i=0, j=0, idx; + u8 ret = _SUCCESS; + u16 mapLen=0; + + EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE); + + if ((addr + cnts) > mapLen) + return _FAIL; + + RT_ASSERT_RET(PGPKT_DATA_SIZE == 8); // have to be 8 byte alignment + RT_ASSERT_RET((mapLen & 0x7) == 0); // have to be PGPKT_DATA_SIZE alignment for memcpy + + map = rtw_zmalloc(mapLen); + if(map == NULL){ + return _FAIL; + } + + ret = rtw_BT_efuse_map_read(padapter, 0, mapLen, map); + if (ret == _FAIL) goto exit; + DBG_871X("OFFSET\tVALUE(hex)\n"); + for (i=0; i<1024; i+=16) // set 512 because the iwpriv's extra size have limit 0x7FF + { + DBG_871X("0x%03x\t", i); + for (j=0; j<8; j++) { + DBG_871X("%02X ", map[i+j]); + } + DBG_871X("\t"); + for (; j<16; j++) { + DBG_871X("%02X ", map[i+j]); + } + DBG_871X("\n"); + } + DBG_871X("\n"); + Efuse_PowerSwitch(padapter, _TRUE, _TRUE); + + idx = 0; + offset = (addr >> 3); + while (idx < cnts) + { + word_en = 0xF; + j = (addr + idx) & 0x7; + _rtw_memcpy(newdata, &map[offset << 3], PGPKT_DATA_SIZE); + for (i = j; i> 1); + newdata[i] = data[idx]; + } + } + + if (word_en != 0xF) { + DBG_871X("offset=%x \n",offset); + DBG_871X("word_en=%x \n",word_en); + DBG_871X("%s: data=", __FUNCTION__); + for(i=0;iefuse_eeprom_data[Offset]; + +} // EFUSE_ShadowRead1Byte + +//---------------Read Two Bytes +static VOID +efuse_ShadowRead2Byte( + IN PADAPTER pAdapter, + IN u16 Offset, + IN OUT u16 *Value) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); + + *Value = pHalData->efuse_eeprom_data[Offset]; + *Value |= pHalData->efuse_eeprom_data[Offset+1]<<8; + +} // EFUSE_ShadowRead2Byte + +//---------------Read Four Bytes +static VOID +efuse_ShadowRead4Byte( + IN PADAPTER pAdapter, + IN u16 Offset, + IN OUT u32 *Value) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); + + *Value = pHalData->efuse_eeprom_data[Offset]; + *Value |= pHalData->efuse_eeprom_data[Offset+1]<<8; + *Value |= pHalData->efuse_eeprom_data[Offset+2]<<16; + *Value |= pHalData->efuse_eeprom_data[Offset+3]<<24; + +} // efuse_ShadowRead4Byte + + +/*----------------------------------------------------------------------------- + * Function: efuse_ShadowWrite1Byte + * efuse_ShadowWrite2Byte + * efuse_ShadowWrite4Byte + * + * Overview: Write efuse modify map by one/two/four byte. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/12/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +#ifdef PLATFORM +static VOID +efuse_ShadowWrite1Byte( + IN PADAPTER pAdapter, + IN u16 Offset, + IN u8 Value); +#endif //PLATFORM +static VOID +efuse_ShadowWrite1Byte( + IN PADAPTER pAdapter, + IN u16 Offset, + IN u8 Value) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); + + pHalData->efuse_eeprom_data[Offset] = Value; + +} // efuse_ShadowWrite1Byte + +//---------------Write Two Bytes +static VOID +efuse_ShadowWrite2Byte( + IN PADAPTER pAdapter, + IN u16 Offset, + IN u16 Value) +{ + + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); + + + pHalData->efuse_eeprom_data[Offset] = Value&0x00FF; + pHalData->efuse_eeprom_data[Offset+1] = Value>>8; + +} // efuse_ShadowWrite1Byte + +//---------------Write Four Bytes +static VOID +efuse_ShadowWrite4Byte( + IN PADAPTER pAdapter, + IN u16 Offset, + IN u32 Value) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); + + pHalData->efuse_eeprom_data[Offset] = (u8)(Value&0x000000FF); + pHalData->efuse_eeprom_data[Offset+1] = (u8)((Value>>8)&0x0000FF); + pHalData->efuse_eeprom_data[Offset+2] = (u8)((Value>>16)&0x00FF); + pHalData->efuse_eeprom_data[Offset+3] = (u8)((Value>>24)&0xFF); + +} // efuse_ShadowWrite1Byte + +/*----------------------------------------------------------------------------- + * Function: EFUSE_ShadowMapUpdate + * + * Overview: Transfer current EFUSE content to shadow init and modify map. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/13/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +void EFUSE_ShadowMapUpdate( + IN PADAPTER pAdapter, + IN u8 efuseType, + IN BOOLEAN bPseudoTest) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); + u16 mapLen=0; + + EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, bPseudoTest); + + if (pHalData->bautoload_fail_flag == _TRUE) + { + _rtw_memset(pHalData->efuse_eeprom_data, 0xFF, mapLen); + } + else + { + #ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE + if(_SUCCESS != retriveAdaptorInfoFile(pAdapter->registrypriv.adaptor_info_caching_file_path, pHalData->efuse_eeprom_data)) { + #endif + + Efuse_ReadAllMap(pAdapter, efuseType, pHalData->efuse_eeprom_data, bPseudoTest); + + #ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE + storeAdaptorInfoFile(pAdapter->registrypriv.adaptor_info_caching_file_path, pHalData->efuse_eeprom_data); + } + #endif + } + + //PlatformMoveMemory((PVOID)&pHalData->EfuseMap[EFUSE_MODIFY_MAP][0], + //(PVOID)&pHalData->EfuseMap[EFUSE_INIT_MAP][0], mapLen); +}// EFUSE_ShadowMapUpdate + + +/*----------------------------------------------------------------------------- + * Function: EFUSE_ShadowRead + * + * Overview: Read from efuse init map !!!!! + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/12/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +void +EFUSE_ShadowRead( + IN PADAPTER pAdapter, + IN u8 Type, + IN u16 Offset, + IN OUT u32 *Value ) +{ + if (Type == 1) + efuse_ShadowRead1Byte(pAdapter, Offset, (u8 *)Value); + else if (Type == 2) + efuse_ShadowRead2Byte(pAdapter, Offset, (u16 *)Value); + else if (Type == 4) + efuse_ShadowRead4Byte(pAdapter, Offset, (u32 *)Value); + +} // EFUSE_ShadowRead + +/*----------------------------------------------------------------------------- + * Function: EFUSE_ShadowWrite + * + * Overview: Write efuse modify map for later update operation to use!!!!! + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/12/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +VOID +EFUSE_ShadowWrite( + IN PADAPTER pAdapter, + IN u8 Type, + IN u16 Offset, + IN OUT u32 Value); +VOID +EFUSE_ShadowWrite( + IN PADAPTER pAdapter, + IN u8 Type, + IN u16 Offset, + IN OUT u32 Value) +{ +#if (MP_DRIVER == 0) + return; +#endif + if ( pAdapter->registrypriv.mp_mode == 0) + return; + + + if (Type == 1) + efuse_ShadowWrite1Byte(pAdapter, Offset, (u8)Value); + else if (Type == 2) + efuse_ShadowWrite2Byte(pAdapter, Offset, (u16)Value); + else if (Type == 4) + efuse_ShadowWrite4Byte(pAdapter, Offset, (u32)Value); + +} // EFUSE_ShadowWrite + +VOID +Efuse_InitSomeVar( + IN PADAPTER pAdapter + ); +VOID +Efuse_InitSomeVar( + IN PADAPTER pAdapter + ) +{ + u8 i; + + _rtw_memset((PVOID)&fakeEfuseContent[0], 0xff, EFUSE_MAX_HW_SIZE); + _rtw_memset((PVOID)&fakeEfuseInitMap[0], 0xff, EFUSE_MAX_MAP_LEN); + _rtw_memset((PVOID)&fakeEfuseModifiedMap[0], 0xff, EFUSE_MAX_MAP_LEN); + + for(i=0; i + + int isAdaptorInfoFileValid(void) +{ + return _TRUE; +} + +int storeAdaptorInfoFile(char *path, u8* efuse_data) +{ + int ret =_SUCCESS; + + if(path && efuse_data) { + ret = rtw_store_to_file(path, efuse_data, EEPROM_MAX_SIZE_512); + if(ret == EEPROM_MAX_SIZE) + ret = _SUCCESS; + else + ret = _FAIL; + } else { + DBG_871X("%s NULL pointer\n",__FUNCTION__); + ret = _FAIL; + } + return ret; +} + +int retriveAdaptorInfoFile(char *path, u8* efuse_data) +{ + int ret = _SUCCESS; +#ifdef set_fs + mm_segment_t oldfs; +#endif + struct file *fp; + + if(path && efuse_data) { + + ret = rtw_retrieve_from_file(path, efuse_data, EEPROM_MAX_SIZE); + + if(ret == EEPROM_MAX_SIZE) + ret = _SUCCESS; + else + ret = _FAIL; + + #if 0 + if(isAdaptorInfoFileValid()) { + return 0; + } else { + return _FAIL; + } + #endif + + } else { + DBG_871X("%s NULL pointer\n",__FUNCTION__); + ret = _FAIL; + } + return ret; +} +#endif /* CONFIG_ADAPTOR_INFO_CACHING_FILE */ + +#ifdef CONFIG_EFUSE_CONFIG_FILE +u32 rtw_read_efuse_from_file(const char *path, u8 *buf) +{ + u32 i; + u8 temp[3]; + u32 ret = _FAIL; + + struct file *fp; +#ifdef set_fs + mm_segment_t fs; +#endif + loff_t pos = 0; + + fp = filp_open(path, O_RDONLY, 0); + if (fp == NULL || IS_ERR(fp)) { + if (fp != NULL) + DBG_871X_LEVEL(_drv_always_, "%s open %s fail, err:%ld\n" + , __func__, path, PTR_ERR(fp)); + else + DBG_871X_LEVEL(_drv_always_, "%s open %s fail, fp is NULL\n" + , __func__, path); + + goto exit; + } + + temp[2] = 0; /* add end of string '\0' */ + +#ifdef set_fs + fs = get_fs(); + set_fs(KERNEL_DS); +#endif + + for (i = 0 ; i < HWSET_MAX_SIZE ; i++) { + vfs_read(fp, temp, 2, &pos); + if (sscanf(temp, "%hhx", &buf[i]) != 1) { + if (0) + DBG_871X_LEVEL(_drv_err_, "%s sscanf fail\n", __func__); + buf[i] = 0xFF; + } + if ((i % EFUSE_FILE_COLUMN_NUM) == (EFUSE_FILE_COLUMN_NUM - 1)) { + /* Filter the lates space char. */ + vfs_read(fp, temp, 1, &pos); + if (strchr(temp, ' ') == NULL) { + pos--; + vfs_read(fp, temp, 2, &pos); + } + } else { + pos += 1; /* Filter the space character */ + } + } + + set_fs(fs); + + DBG_871X_LEVEL(_drv_always_, "efuse file: %s\n", path); +#ifdef CONFIG_DEBUG + for (i = 0; i < HWSET_MAX_SIZE; i++) { + if (i % 16 == 0) + DBG_871X_SEL_NL(RTW_DBGDUMP, "0x%03x: ", i); + + DBG_871X_SEL(RTW_DBGDUMP, "%02X%s" + , buf[i] + , ((i + 1) % 16 == 0) ? "\n" : (((i + 1) % 8 == 0) ? " " : " ") + ); + } + DBG_871X_SEL(RTW_DBGDUMP, "\n"); +#endif + + ret = _SUCCESS; + +exit: + return ret; +} + +u32 rtw_read_macaddr_from_file(const char *path, u8 *buf) +{ + struct file *fp; +#ifdef set_fs + mm_segment_t fs; +#endif + loff_t pos = 0; + + u8 source_addr[18]; + u8 *head, *end; + int i; + u32 ret = _FAIL; + + _rtw_memset(source_addr, 0, 18); + + fp = filp_open(path, O_RDONLY, 0); + if (fp == NULL || IS_ERR(fp)) { + if (fp != NULL) + DBG_871X_LEVEL(_drv_always_, "%s open %s fail, err:%ld\n" + , __func__, path, PTR_ERR(fp)); + else + DBG_871X_LEVEL(_drv_always_, "%s open %s fail, fp is NULL\n" + , __func__, path); + + goto exit; + } + +#ifdef set_fs + fs = get_fs(); + set_fs(KERNEL_DS); +#endif + + vfs_read(fp, source_addr, 18, &pos); + source_addr[17] = ':'; + + head = end = source_addr; + for (i = 0; i < ETH_ALEN; i++) { + while (end && (*end != ':')) + end++; + + if (end && (*end == ':')) + *end = '\0'; + + if (sscanf(head, "%hhx", &buf[i]) != 1) { + if (0) + DBG_871X_LEVEL(_drv_err_, "%s sscanf fail\n", __func__); + buf[i] = 0xFF; + } + + if (end) { + end++; + head = end; + } + } + + set_fs(fs); + + DBG_871X_LEVEL(_drv_always_, "wifi_mac file: %s\n", path); +#ifdef CONFIG_DEBUG + DBG_871X(MAC_FMT"\n", MAC_ARG(buf)); +#endif + + ret = _SUCCESS; + +exit: + return ret; +} +#endif /* CONFIG_EFUSE_CONFIG_FILE */ + +#endif /* PLATFORM_LINUX */ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_ap.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_ap.c new file mode 100644 index 000000000..6fd0be96b --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_ap.c @@ -0,0 +1,4174 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_AP_C_ + +#include + + +#ifdef CONFIG_AP_MODE + +extern unsigned char RTW_WPA_OUI[]; +extern unsigned char WMM_OUI[]; +extern unsigned char WPS_OUI[]; +extern unsigned char P2P_OUI[]; +extern unsigned char WFD_OUI[]; + +void init_mlme_ap_info(_adapter *padapter) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sta_priv *pstapriv = &padapter->stapriv; + struct wlan_acl_pool *pacl_list = &pstapriv->acl_list; + + + _rtw_spinlock_init(&pmlmepriv->bcn_update_lock); + + //for ACL + _rtw_init_queue(&pacl_list->acl_node_q); + + //pmlmeext->bstart_bss = _FALSE; + + start_ap_mode(padapter); +} + +void free_mlme_ap_info(_adapter *padapter) +{ + _irqL irqL; + struct sta_info *psta=NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + //stop_ap_mode(padapter); + + pmlmepriv->update_bcn = _FALSE; + pmlmeext->bstart_bss = _FALSE; + + rtw_sta_flush(padapter, _TRUE); + + pmlmeinfo->state = _HW_STATE_NOLINK_; + + //free_assoc_sta_resources + rtw_free_all_stainfo(padapter); + + //free bc/mc sta_info + psta = rtw_get_bcmc_stainfo(padapter); + //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + rtw_free_stainfo(padapter, psta); + //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + + + _rtw_spinlock_free(&pmlmepriv->bcn_update_lock); + +} + +static void update_BCNTIM(_adapter *padapter) +{ + struct sta_priv *pstapriv = &padapter->stapriv; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork_mlmeext = &(pmlmeinfo->network); + unsigned char *pie = pnetwork_mlmeext->IEs; + +/* + //DBG_871X("%s\n", __FUNCTION__); + + //update TIM IE + //if(pstapriv->tim_bitmap) +*/ + if (_TRUE) { + u8 *p, *dst_ie, *premainder_ie = NULL, *pbackup_remainder_ie = NULL; + u16 tim_bitmap_le; + uint offset, tmp_len, tim_ielen, tim_ie_offset, remainder_ielen; + + tim_bitmap_le = cpu_to_le16(pstapriv->tim_bitmap); + + p = rtw_get_ie(pie + _FIXED_IE_LENGTH_, _TIM_IE_, &tim_ielen, pnetwork_mlmeext->IELength - _FIXED_IE_LENGTH_); + if (p != NULL && tim_ielen > 0) { + tim_ielen += 2; + + premainder_ie = p + tim_ielen; + + tim_ie_offset = (sint)(p -pie); + + remainder_ielen = pnetwork_mlmeext->IELength - tim_ie_offset - tim_ielen; + + /*append TIM IE from dst_ie offset*/ + dst_ie = p; + } else { + tim_ielen = 0; + + /*calculate head_len*/ + offset = _FIXED_IE_LENGTH_; + + /* get ssid_ie len */ + p = rtw_get_ie(pie + _BEACON_IE_OFFSET_, _SSID_IE_, &tmp_len, (pnetwork_mlmeext->IELength - _BEACON_IE_OFFSET_)); + if (p != NULL) + offset += tmp_len+2; + + /*get supported rates len*/ + p = rtw_get_ie(pie + _BEACON_IE_OFFSET_, _SUPPORTEDRATES_IE_, &tmp_len, (pnetwork_mlmeext->IELength - _BEACON_IE_OFFSET_)); + if (p != NULL) + { + offset += tmp_len+2; + } + + /*DS Parameter Set IE, len=3*/ + offset += 3; + + premainder_ie = pie + offset; + + remainder_ielen = pnetwork_mlmeext->IELength - offset - tim_ielen; + + /*append TIM IE from offset*/ + dst_ie = pie + offset; + + } + + if (remainder_ielen > 0) { + pbackup_remainder_ie = rtw_malloc(remainder_ielen); + if(pbackup_remainder_ie && premainder_ie) + _rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen); + } + + *dst_ie++=_TIM_IE_; + + if ((pstapriv->tim_bitmap&0xff00) && (pstapriv->tim_bitmap&0x00fe)) + tim_ielen = 5; + else + tim_ielen = 4; + + *dst_ie++ = tim_ielen; + + *dst_ie++ = 0;/*DTIM count*/ + *dst_ie++ = 1;/*DTIM period*/ + + if (pstapriv->tim_bitmap & BIT(0))/*for bc/mc frames*/ + *dst_ie++ = BIT(0);/*bitmap ctrl */ + else + *dst_ie++ = 0; + + if (tim_ielen == 4) { + u8 pvb = 0; + + if (pstapriv->tim_bitmap & 0x00fe) + pvb = (u8)tim_bitmap_le; + else if (pstapriv->tim_bitmap & 0xff00) + pvb = (u8)(tim_bitmap_le >> 8); + else + pvb = (u8)tim_bitmap_le; + + *dst_ie++ = pvb; + + } else if (tim_ielen == 5) { + _rtw_memcpy(dst_ie, &tim_bitmap_le, 2); + dst_ie += 2; + } + + /*copy remainder IE*/ + if (pbackup_remainder_ie) { + _rtw_memcpy(dst_ie, pbackup_remainder_ie, remainder_ielen); + + rtw_mfree(pbackup_remainder_ie, remainder_ielen); + } + + offset = (uint)(dst_ie - pie); + pnetwork_mlmeext->IELength = offset + remainder_ielen; + + } +} + +void rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len) +{ + PNDIS_802_11_VARIABLE_IEs pIE; + u8 bmatch = _FALSE; + u8 *pie = pnetwork->IEs; + u8 *p=NULL, *dst_ie=NULL, *premainder_ie=NULL, *pbackup_remainder_ie=NULL; + u32 i, offset, ielen, ie_offset, remainder_ielen = 0; + + for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pnetwork->IELength;) + { + pIE = (PNDIS_802_11_VARIABLE_IEs)(pnetwork->IEs + i); + + if (pIE->ElementID > index) + { + break; + } + else if(pIE->ElementID == index) // already exist the same IE + { + p = (u8 *)pIE; + ielen = pIE->Length; + bmatch = _TRUE; + break; + } + + p = (u8 *)pIE; + ielen = pIE->Length; + i += (pIE->Length + 2); + } + + if (p != NULL && ielen>0) + { + ielen += 2; + + premainder_ie = p+ielen; + + ie_offset = (sint)(p -pie); + + remainder_ielen = pnetwork->IELength - ie_offset - ielen; + + if(bmatch) + dst_ie = p; + else + dst_ie = (p+ielen); + } + + if(dst_ie == NULL) + return; + + if(remainder_ielen>0) + { + pbackup_remainder_ie = rtw_malloc(remainder_ielen); + if(pbackup_remainder_ie && premainder_ie) + _rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen); + } + + *dst_ie++=index; + *dst_ie++=len; + + _rtw_memcpy(dst_ie, data, len); + dst_ie+=len; + + //copy remainder IE + if(pbackup_remainder_ie) + { + _rtw_memcpy(dst_ie, pbackup_remainder_ie, remainder_ielen); + + rtw_mfree(pbackup_remainder_ie, remainder_ielen); + } + + offset = (uint)(dst_ie - pie); + pnetwork->IELength = offset + remainder_ielen; +} + +void rtw_remove_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index) +{ + u8 *p, *dst_ie=NULL, *premainder_ie=NULL, *pbackup_remainder_ie=NULL; + uint offset, ielen, ie_offset, remainder_ielen = 0; + u8 *pie = pnetwork->IEs; + + p = rtw_get_ie(pie + _FIXED_IE_LENGTH_, index, &ielen, pnetwork->IELength - _FIXED_IE_LENGTH_); + if (p != NULL && ielen>0) + { + ielen += 2; + + premainder_ie = p+ielen; + + ie_offset = (sint)(p -pie); + + remainder_ielen = pnetwork->IELength - ie_offset - ielen; + + dst_ie = p; + } + else { + return; + } + + if(remainder_ielen>0) + { + pbackup_remainder_ie = rtw_malloc(remainder_ielen); + if(pbackup_remainder_ie && premainder_ie) + _rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen); + } + + //copy remainder IE + if(pbackup_remainder_ie) + { + _rtw_memcpy(dst_ie, pbackup_remainder_ie, remainder_ielen); + + rtw_mfree(pbackup_remainder_ie, remainder_ielen); + } + + offset = (uint)(dst_ie - pie); + pnetwork->IELength = offset + remainder_ielen; +} + + +u8 chk_sta_is_alive(struct sta_info *psta); +u8 chk_sta_is_alive(struct sta_info *psta) +{ + u8 ret = _FALSE; + #ifdef DBG_EXPIRATION_CHK + DBG_871X("sta:"MAC_FMT", rssi:%d, rx:"STA_PKTS_FMT", expire_to:%u, %s%ssq_len:%u\n" + , MAC_ARG(psta->hwaddr) + , psta->rssi_stat.UndecoratedSmoothedPWDB + //, STA_RX_PKTS_ARG(psta) + , STA_RX_PKTS_DIFF_ARG(psta) + , psta->expire_to + , psta->state&WIFI_SLEEP_STATE?"PS, ":"" + , psta->state&WIFI_STA_ALIVE_CHK_STATE?"SAC, ":"" + , psta->sleepq_len + ); + #endif + + //if(sta_last_rx_pkts(psta) == sta_rx_pkts(psta)) + if((psta->sta_stats.last_rx_data_pkts + psta->sta_stats.last_rx_ctrl_pkts) == (psta->sta_stats.rx_data_pkts + psta->sta_stats.rx_ctrl_pkts)) + { + #if 0 + if(psta->state&WIFI_SLEEP_STATE) + ret = _TRUE; + #endif + } + else + { + ret = _TRUE; + } + + sta_update_last_rx_pkts(psta); + + return ret; +} + +void expire_timeout_chk(_adapter *padapter) +{ + _irqL irqL; + _list *phead, *plist; + u8 updated = _FALSE; + struct sta_info *psta=NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 chk_alive_num = 0; + char chk_alive_list[NUM_STA]; + int i; + + + _enter_critical_bh(&pstapriv->auth_list_lock, &irqL); + + phead = &pstapriv->auth_list; + plist = get_next(phead); + + //check auth_queue + #ifdef DBG_EXPIRATION_CHK + if (rtw_end_of_queue_search(phead, plist) == _FALSE) { + DBG_871X(FUNC_NDEV_FMT" auth_list, cnt:%u\n" + , FUNC_NDEV_ARG(padapter->pnetdev), pstapriv->auth_list_cnt); + } + #endif + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) + { + psta = LIST_CONTAINOR(plist, struct sta_info, auth_list); + + plist = get_next(plist); + + +#ifdef CONFIG_ATMEL_RC_PATCH + if (_TRUE == _rtw_memcmp((void *)(pstapriv->atmel_rc_pattern), (void *)(psta->hwaddr), ETH_ALEN)) + continue; + if (psta->flag_atmel_rc) + continue; +#endif + if(psta->expire_to>0) + { + psta->expire_to--; + if (psta->expire_to == 0) + { + rtw_list_delete(&psta->auth_list); + pstapriv->auth_list_cnt--; + + DBG_871X("auth expire %02X%02X%02X%02X%02X%02X\n", + psta->hwaddr[0],psta->hwaddr[1],psta->hwaddr[2],psta->hwaddr[3],psta->hwaddr[4],psta->hwaddr[5]); + + _exit_critical_bh(&pstapriv->auth_list_lock, &irqL); + + //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + rtw_free_stainfo(padapter, psta); + //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + + _enter_critical_bh(&pstapriv->auth_list_lock, &irqL); + } + } + + } + + _exit_critical_bh(&pstapriv->auth_list_lock, &irqL); + psta = NULL; + + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + phead = &pstapriv->asoc_list; + plist = get_next(phead); + + //check asoc_queue + #ifdef DBG_EXPIRATION_CHK + if (rtw_end_of_queue_search(phead, plist) == _FALSE) { + DBG_871X(FUNC_NDEV_FMT" asoc_list, cnt:%u\n" + , FUNC_NDEV_ARG(padapter->pnetdev), pstapriv->asoc_list_cnt); + } + #endif + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) + { + psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + plist = get_next(plist); +#ifdef CONFIG_ATMEL_RC_PATCH + DBG_871X("%s:%d psta=%p, %02x,%02x||%02x,%02x \n\n", __func__, __LINE__, + psta,pstapriv->atmel_rc_pattern[0], pstapriv->atmel_rc_pattern[5], psta->hwaddr[0], psta->hwaddr[5]); + if (_TRUE == _rtw_memcmp((void *)pstapriv->atmel_rc_pattern, (void *)(psta->hwaddr), ETH_ALEN)) + continue; + if (psta->flag_atmel_rc) + continue; + DBG_871X("%s: debug line:%d \n", __func__, __LINE__); +#endif +#ifdef CONFIG_AUTO_AP_MODE + if(psta->isrc) + continue; +#endif + if (chk_sta_is_alive(psta) || !psta->expire_to) { + psta->expire_to = pstapriv->expire_to; + psta->keep_alive_trycnt = 0; + #ifdef CONFIG_TX_MCAST2UNI + psta->under_exist_checking = 0; + #endif // CONFIG_TX_MCAST2UNI + } else { + psta->expire_to--; + } + +#ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK +#ifdef CONFIG_80211N_HT +#ifdef CONFIG_TX_MCAST2UNI + if ( (psta->flags & WLAN_STA_HT) && (psta->htpriv.agg_enable_bitmap || psta->under_exist_checking) ) { + // check sta by delba(addba) for 11n STA + // ToDo: use CCX report to check for all STAs + //DBG_871X("asoc check by DELBA/ADDBA! (pstapriv->expire_to=%d s)(psta->expire_to=%d s), [%02x, %d]\n", pstapriv->expire_to*2, psta->expire_to*2, psta->htpriv.agg_enable_bitmap, psta->under_exist_checking); + + if ( psta->expire_to <= (pstapriv->expire_to - 50 ) ) { + DBG_871X("asoc expire by DELBA/ADDBA! (%d s)\n", (pstapriv->expire_to-psta->expire_to)*2); + psta->under_exist_checking = 0; + psta->expire_to = 0; + } else if ( psta->expire_to <= (pstapriv->expire_to - 3) && (psta->under_exist_checking==0)) { + DBG_871X("asoc check by DELBA/ADDBA! (%d s)\n", (pstapriv->expire_to-psta->expire_to)*2); + psta->under_exist_checking = 1; + //tear down TX AMPDU + send_delba(padapter, 1, psta->hwaddr);// // originator + psta->htpriv.agg_enable_bitmap = 0x0;//reset + psta->htpriv.candidate_tid_bitmap = 0x0;//reset + } + } +#endif //CONFIG_TX_MCAST2UNI +#endif //CONFIG_80211N_HT +#endif //CONFIG_ACTIVE_KEEP_ALIVE_CHECK + + if (psta->expire_to <= 0) + { + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + if (padapter->registrypriv.wifi_spec == 1) + { + psta->expire_to = pstapriv->expire_to; + continue; + } + +#ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK +#ifdef CONFIG_80211N_HT + +#define KEEP_ALIVE_TRYCNT (3) + + if(psta->keep_alive_trycnt > 0 && psta->keep_alive_trycnt <= KEEP_ALIVE_TRYCNT) + { + if(psta->state & WIFI_STA_ALIVE_CHK_STATE) + psta->state ^= WIFI_STA_ALIVE_CHK_STATE; + else + psta->keep_alive_trycnt = 0; + + } + else if((psta->keep_alive_trycnt > KEEP_ALIVE_TRYCNT) && !(psta->state & WIFI_STA_ALIVE_CHK_STATE)) + { + psta->keep_alive_trycnt = 0; + } + if((psta->htpriv.ht_option==_TRUE) && (psta->htpriv.ampdu_enable==_TRUE)) + { + uint priority = 1; //test using BK + u8 issued=0; + + //issued = (psta->htpriv.agg_enable_bitmap>>priority)&0x1; + issued |= (psta->htpriv.candidate_tid_bitmap>>priority)&0x1; + + if(0==issued) + { + if (!(psta->state & WIFI_STA_ALIVE_CHK_STATE)) + { + psta->htpriv.candidate_tid_bitmap |= BIT((u8)priority); + + if (psta->state & WIFI_SLEEP_STATE) + psta->expire_to = 2; // 2x2=4 sec + else + psta->expire_to = 1; // 2 sec + + psta->state |= WIFI_STA_ALIVE_CHK_STATE; + + //add_ba_hdl(padapter, (u8*)paddbareq_parm); + + DBG_871X("issue addba_req to check if sta alive, keep_alive_trycnt=%d\n", psta->keep_alive_trycnt); + + issue_addba_req(padapter, psta->hwaddr, (u8)priority); + + _set_timer(&psta->addba_retry_timer, ADDBA_TO); + + psta->keep_alive_trycnt++; + + continue; + } + } + } + if(psta->keep_alive_trycnt > 0 && psta->state & WIFI_STA_ALIVE_CHK_STATE) + { + psta->keep_alive_trycnt = 0; + psta->state ^= WIFI_STA_ALIVE_CHK_STATE; + DBG_871X("change to another methods to check alive if staion is at ps mode\n"); + } + +#endif //CONFIG_80211N_HT +#endif //CONFIG_ACTIVE_KEEP_ALIVE_CHECK + if (psta->state & WIFI_SLEEP_STATE) { + if (!(psta->state & WIFI_STA_ALIVE_CHK_STATE)) { + //to check if alive by another methods if staion is at ps mode. + psta->expire_to = pstapriv->expire_to; + psta->state |= WIFI_STA_ALIVE_CHK_STATE; + + //DBG_871X("alive chk, sta:" MAC_FMT " is at ps mode!\n", MAC_ARG(psta->hwaddr)); + + //to update bcn with tim_bitmap for this station + pstapriv->tim_bitmap |= BIT(psta->aid); + update_beacon(padapter, _TIM_IE_, NULL, _TRUE); + + if(!pmlmeext->active_keep_alive_check) + continue; + } + } + #ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK + if (pmlmeext->active_keep_alive_check) { + int stainfo_offset; + + stainfo_offset = rtw_stainfo_offset(pstapriv, psta); + if (stainfo_offset_valid(stainfo_offset)) { + chk_alive_list[chk_alive_num++] = stainfo_offset; + } + + continue; + } + #endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ + rtw_list_delete(&psta->asoc_list); + pstapriv->asoc_list_cnt--; + DBG_871X("asoc expire "MAC_FMT", state=0x%x\n", MAC_ARG(psta->hwaddr), psta->state); + updated = ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_DEAUTH_LEAVING, _TRUE); + } + else + { + /* TODO: Aging mechanism to digest frames in sleep_q to avoid running out of xmitframe */ + if (psta->sleepq_len > (NR_XMITFRAME/pstapriv->asoc_list_cnt) + && padapter->xmitpriv.free_xmitframe_cnt < ((NR_XMITFRAME/pstapriv->asoc_list_cnt)/2) + ){ + DBG_871X("%s sta:"MAC_FMT", sleepq_len:%u, free_xmitframe_cnt:%u, asoc_list_cnt:%u, clear sleep_q\n", __func__ + , MAC_ARG(psta->hwaddr) + , psta->sleepq_len, padapter->xmitpriv.free_xmitframe_cnt, pstapriv->asoc_list_cnt); + wakeup_sta_to_xmit(padapter, psta); + } + } + } + + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + +#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK +if (chk_alive_num) { + + u8 backup_oper_channel=0; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + /* switch to correct channel of current network before issue keep-alive frames */ + if (rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) { + backup_oper_channel = rtw_get_oper_ch(padapter); + SelectChannel(padapter, pmlmeext->cur_channel); + } + + /* issue null data to check sta alive*/ + for (i = 0; i < chk_alive_num; i++) { + int ret = _FAIL; + + psta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]); +#ifdef CONFIG_ATMEL_RC_PATCH + if (_TRUE == _rtw_memcmp( pstapriv->atmel_rc_pattern, psta->hwaddr, ETH_ALEN)) + continue; + if (psta->flag_atmel_rc) + continue; +#endif + if(!(psta->state &_FW_LINKED)) + continue; + + if (psta->state & WIFI_SLEEP_STATE) + ret = issue_nulldata(padapter, psta->hwaddr, 0, 1, 50); + else + ret = issue_nulldata(padapter, psta->hwaddr, 0, 3, 50); + + psta->keep_alive_trycnt++; + if (ret == _SUCCESS) + { + DBG_871X("asoc check, sta(" MAC_FMT ") is alive\n", MAC_ARG(psta->hwaddr)); + psta->expire_to = pstapriv->expire_to; + psta->keep_alive_trycnt = 0; + continue; + } + else if (psta->keep_alive_trycnt <= 3) + { + DBG_871X("ack check for asoc expire, keep_alive_trycnt=%d\n", psta->keep_alive_trycnt); + psta->expire_to = 1; + continue; + } + + psta->keep_alive_trycnt = 0; + DBG_871X("asoc expire "MAC_FMT", state=0x%x\n", MAC_ARG(psta->hwaddr), psta->state); + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + if (rtw_is_list_empty(&psta->asoc_list)==_FALSE) { + rtw_list_delete(&psta->asoc_list); + pstapriv->asoc_list_cnt--; + updated = ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_DEAUTH_LEAVING, _TRUE); + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + } + + if (backup_oper_channel>0) /* back to the original operation channel */ + SelectChannel(padapter, backup_oper_channel); +} +#endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ + + associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL); +} + +void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level) +{ + int i; + u8 rf_type; + unsigned char sta_band = 0, shortGIrate = _FALSE; + u64 tx_ra_bitmap = 0; + struct ht_priv *psta_ht = NULL; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; + +#ifdef CONFIG_80211N_HT + if(psta) + psta_ht = &psta->htpriv; + else + return; +#endif //CONFIG_80211N_HT + + if(!(psta->state & _FW_LINKED)) + return; + +#if 0//gtest + if(get_rf_mimo_mode(padapter) == RTL8712_RF_2T2R) + { + //is this a 2r STA? + if((pstat->tx_ra_bitmap & 0x0ff00000) != 0 && !(priv->pshare->has_2r_sta & BIT(pstat->aid))) + { + priv->pshare->has_2r_sta |= BIT(pstat->aid); + if(rtw_read16(padapter, 0x102501f6) != 0xffff) + { + rtw_write16(padapter, 0x102501f6, 0xffff); + reset_1r_sta_RA(priv, 0xffff); + Switch_1SS_Antenna(priv, 3); + } + } + else// bg or 1R STA? + { + if((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) && pstat->ht_cap_len && priv->pshare->has_2r_sta == 0) + { + if(rtw_read16(padapter, 0x102501f6) != 0x7777) + { // MCS7 SGI + rtw_write16(padapter, 0x102501f6,0x7777); + reset_1r_sta_RA(priv, 0x7777); + Switch_1SS_Antenna(priv, 2); + } + } + } + + } + + if ((pstat->rssi_level < 1) || (pstat->rssi_level > 3)) + { + if (pstat->rssi >= priv->pshare->rf_ft_var.raGoDownUpper) + pstat->rssi_level = 1; + else if ((pstat->rssi >= priv->pshare->rf_ft_var.raGoDown20MLower) || + ((priv->pshare->is_40m_bw) && (pstat->ht_cap_len) && + (pstat->rssi >= priv->pshare->rf_ft_var.raGoDown40MLower) && + (pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_SUPPORT_CH_WDTH_)))) + pstat->rssi_level = 2; + else + pstat->rssi_level = 3; + } + + // rate adaptive by rssi + if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) && pstat->ht_cap_len) + { + if ((get_rf_mimo_mode(priv) == MIMO_1T2R) || (get_rf_mimo_mode(priv) == MIMO_1T1R)) + { + switch (pstat->rssi_level) { + case 1: + pstat->tx_ra_bitmap &= 0x100f0000; + break; + case 2: + pstat->tx_ra_bitmap &= 0x100ff000; + break; + case 3: + if (priv->pshare->is_40m_bw) + pstat->tx_ra_bitmap &= 0x100ff005; + else + pstat->tx_ra_bitmap &= 0x100ff001; + + break; + } + } + else + { + switch (pstat->rssi_level) { + case 1: + pstat->tx_ra_bitmap &= 0x1f0f0000; + break; + case 2: + pstat->tx_ra_bitmap &= 0x1f0ff000; + break; + case 3: + if (priv->pshare->is_40m_bw) + pstat->tx_ra_bitmap &= 0x000ff005; + else + pstat->tx_ra_bitmap &= 0x000ff001; + + break; + } + + // Don't need to mask high rates due to new rate adaptive parameters + //if (pstat->is_broadcom_sta) // use MCS12 as the highest rate vs. Broadcom sta + // pstat->tx_ra_bitmap &= 0x81ffffff; + + // NIC driver will report not supporting MCS15 and MCS14 in asoc req + //if (pstat->is_rtl8190_sta && !pstat->is_2t_mimo_sta) + // pstat->tx_ra_bitmap &= 0x83ffffff; // if Realtek 1x2 sta, don't use MCS15 and MCS14 + } + } + else if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11G) && isErpSta(pstat)) + { + switch (pstat->rssi_level) { + case 1: + pstat->tx_ra_bitmap &= 0x00000f00; + break; + case 2: + pstat->tx_ra_bitmap &= 0x00000ff0; + break; + case 3: + pstat->tx_ra_bitmap &= 0x00000ff5; + break; + } + } + else + { + pstat->tx_ra_bitmap &= 0x0000000d; + } + + // disable tx short GI when station cannot rx MCS15(AP is 2T2R) + // disable tx short GI when station cannot rx MCS7 (AP is 1T2R or 1T1R) + // if there is only 1r STA and we are 2T2R, DO NOT mask SGI rate + if ((!(pstat->tx_ra_bitmap & 0x8000000) && (priv->pshare->has_2r_sta > 0) && (get_rf_mimo_mode(padapter) == RTL8712_RF_2T2R)) || + (!(pstat->tx_ra_bitmap & 0x80000) && (get_rf_mimo_mode(padapter) != RTL8712_RF_2T2R))) + { + pstat->tx_ra_bitmap &= ~BIT(28); + } +#endif + + rtw_hal_update_sta_rate_mask(padapter, psta); + tx_ra_bitmap = psta->ra_mask; + + shortGIrate = query_ra_short_GI(psta); + + if ( pcur_network->Configuration.DSConfig > 14 ) { + + if (tx_ra_bitmap & 0xffff000) + sta_band |= WIRELESS_11_5N ; + + if (tx_ra_bitmap & 0xff0) + sta_band |= WIRELESS_11A; + + // 5G band + #ifdef CONFIG_80211AC_VHT + if (psta->vhtpriv.vht_option) { + sta_band = WIRELESS_11_5AC; + } + #endif + + } else { + if (tx_ra_bitmap & 0xffff000) + sta_band |= WIRELESS_11_24N; + + if (tx_ra_bitmap & 0xff0) + sta_band |= WIRELESS_11G; + + if (tx_ra_bitmap & 0x0f) + sta_band |= WIRELESS_11B; + } + + psta->wireless_mode = sta_band; + psta->raid = rtw_hal_networktype_to_raid(padapter, psta); + + if (psta->aid < NUM_STA) + { + u8 arg[4] = {0}; + + arg[0] = psta->mac_id; + arg[1] = psta->raid; + arg[2] = shortGIrate; + arg[3] = psta->init_rate; + + DBG_871X("%s=> mac_id:%d , raid:%d , shortGIrate=%d, tx_ra_bitmap:0x%016llx, networkType:0x%02x\n", + __FUNCTION__, psta->mac_id, psta->raid, shortGIrate, tx_ra_bitmap, psta->wireless_mode); + + rtw_hal_add_ra_tid(padapter, tx_ra_bitmap, arg, rssi_level); + } + else + { + DBG_871X("station aid %d exceed the max number\n", psta->aid); + } + +} + +void update_bmc_sta(_adapter *padapter) +{ + _irqL irqL; + unsigned char network_type; + int supportRateNum = 0; + u64 tx_ra_bitmap = 0; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; + struct sta_info *psta = rtw_get_bcmc_stainfo(padapter); + + if(psta) + { + psta->aid = 0;//default set to 0 + psta->qos_option = 0; +#ifdef CONFIG_80211N_HT + psta->htpriv.ht_option = _FALSE; +#endif //CONFIG_80211N_HT + + psta->ieee8021x_blocked = 0; + + _rtw_memset((void*)&psta->sta_stats, 0, sizeof(struct stainfo_stats)); + + //psta->dot118021XPrivacy = _NO_PRIVACY_;//!!! remove it, because it has been set before this. + + //prepare for add_RATid + supportRateNum = rtw_get_rateset_len((u8*)&pcur_network->SupportedRates); + network_type = rtw_check_network_type((u8*)&pcur_network->SupportedRates, supportRateNum, pcur_network->Configuration.DSConfig); + if (IsSupportedTxCCK(network_type)) { + network_type = WIRELESS_11B; + } + else if (network_type == WIRELESS_INVALID) { // error handling + if ( pcur_network->Configuration.DSConfig > 14 ) + network_type = WIRELESS_11A; + else + network_type = WIRELESS_11B; + } + update_sta_basic_rate(psta, network_type); + psta->wireless_mode = network_type; + + rtw_hal_update_sta_rate_mask(padapter, psta); + tx_ra_bitmap = psta->ra_mask; + + psta->raid = rtw_hal_networktype_to_raid(padapter,psta); + + //if(pHalData->fw_ractrl == _TRUE) + { + u8 arg[4] = {0}; + + arg[0] = psta->mac_id; + arg[1] = psta->raid; + arg[2] = 0; + arg[3] = psta->init_rate; + + DBG_871X("%s=> mac_id:%d , raid:%d , bitmap=0x%016llx\n", + __FUNCTION__ , psta->mac_id, psta->raid , tx_ra_bitmap); + + rtw_hal_add_ra_tid(padapter, tx_ra_bitmap, arg, 0); + } + + rtw_sta_media_status_rpt(padapter, psta, 1); + + _enter_critical_bh(&psta->lock, &irqL); + psta->state = _FW_LINKED; + _exit_critical_bh(&psta->lock, &irqL); + + } + else + { + DBG_871X("add_RATid_bmc_sta error!\n"); + } + +} + +//notes: +//AID: 1~MAX for sta and 0 for bc/mc in ap/adhoc mode +//MAC_ID = AID+1 for sta in ap/adhoc mode +//MAC_ID = 1 for bc/mc for sta/ap/adhoc +//MAC_ID = 0 for bssid for sta/ap/adhoc +//CAM_ID = //0~3 for default key, cmd_id=macid + 3, macid=aid+1; + +void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) +{ + _irqL irqL; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); +#ifdef CONFIG_80211N_HT + struct ht_priv *phtpriv_ap = &pmlmepriv->htpriv; + struct ht_priv *phtpriv_sta = &psta->htpriv; +#endif //CONFIG_80211N_HT + u8 cur_ldpc_cap=0, cur_stbc_cap=0, cur_beamform_cap=0; + //set intf_tag to if1 + //psta->intf_tag = 0; + + DBG_871X("%s\n",__FUNCTION__); + + //psta->mac_id = psta->aid+4; + //psta->mac_id = psta->aid+1;//alloc macid when call rtw_alloc_stainfo(), + //release macid when call rtw_free_stainfo() + + //ap mode + rtw_hal_set_odm_var(padapter,HAL_ODM_STA_INFO,psta,_TRUE); + + if(psecuritypriv->dot11AuthAlgrthm==dot11AuthAlgrthm_8021X) + psta->ieee8021x_blocked = _TRUE; + else + psta->ieee8021x_blocked = _FALSE; + + + //update sta's cap + + //ERP + VCS_update(padapter, psta); +#ifdef CONFIG_80211N_HT + //HT related cap + if(phtpriv_sta->ht_option) + { + //check if sta supports rx ampdu + phtpriv_sta->ampdu_enable = phtpriv_ap->ampdu_enable; + + phtpriv_sta->rx_ampdu_min_spacing = (phtpriv_sta->ht_cap.ampdu_params_info&IEEE80211_HT_CAP_AMPDU_DENSITY)>>2; + + // bwmode + if((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SUP_WIDTH)) + { + psta->bw_mode = CHANNEL_WIDTH_40; + } + else + { + psta->bw_mode = CHANNEL_WIDTH_20; + } + + if (psta->ht_40mhz_intolerant) + psta->bw_mode = CHANNEL_WIDTH_20; + + if(pmlmeext->cur_bwmode < psta->bw_mode) + { + psta->bw_mode = pmlmeext->cur_bwmode; + } + + phtpriv_sta->ch_offset = pmlmeext->cur_ch_offset; + + + //check if sta support s Short GI 20M + if((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_20)) + { + phtpriv_sta->sgi_20m = _TRUE; + } + + //check if sta support s Short GI 40M + if((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_40)) + { + if(psta->bw_mode == CHANNEL_WIDTH_40) //according to psta->bw_mode + phtpriv_sta->sgi_40m = _TRUE; + else + phtpriv_sta->sgi_40m = _FALSE; + } + + psta->qos_option = _TRUE; + + // B0 Config LDPC Coding Capability + if (TEST_FLAG(phtpriv_ap->ldpc_cap, LDPC_HT_ENABLE_TX) && + GET_HT_CAP_ELE_LDPC_CAP((u8 *)(&phtpriv_sta->ht_cap))) + { + SET_FLAG(cur_ldpc_cap, (LDPC_HT_ENABLE_TX | LDPC_HT_CAP_TX)); + DBG_871X("Enable HT Tx LDPC for STA(%d)\n",psta->aid); + } + + // B7 B8 B9 Config STBC setting + if (TEST_FLAG(phtpriv_ap->stbc_cap, STBC_HT_ENABLE_TX) && + GET_HT_CAP_ELE_RX_STBC((u8 *)(&phtpriv_sta->ht_cap))) + { + SET_FLAG(cur_stbc_cap, (STBC_HT_ENABLE_TX | STBC_HT_CAP_TX) ); + DBG_871X("Enable HT Tx STBC for STA(%d)\n",psta->aid); + } + +#ifdef CONFIG_BEAMFORMING + /*Config Tx beamforming setting*/ + if (TEST_FLAG(phtpriv_ap->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) && + GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP((u8 *)(&phtpriv_sta->ht_cap))) + { + SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE); + /*Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/ + SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS((u8 *)(&phtpriv_sta->ht_cap)) << 6); + } + + if (TEST_FLAG(phtpriv_ap->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) && + GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP((u8 *)(&phtpriv_sta->ht_cap))) + { + SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE); + /*Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/ + SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS((u8 *)(&phtpriv_sta->ht_cap)) << 4); + } + if (cur_beamform_cap) { + DBG_871X("Client STA(%d) HT Beamforming Cap = 0x%02X\n", psta->aid, cur_beamform_cap); + } +#endif /*CONFIG_BEAMFORMING*/ + } + else + { + phtpriv_sta->ampdu_enable = _FALSE; + + phtpriv_sta->sgi_20m = _FALSE; + phtpriv_sta->sgi_40m = _FALSE; + psta->bw_mode = CHANNEL_WIDTH_20; + phtpriv_sta->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + } + + phtpriv_sta->ldpc_cap = cur_ldpc_cap; + phtpriv_sta->stbc_cap = cur_stbc_cap; + phtpriv_sta->beamform_cap = cur_beamform_cap; + + //Rx AMPDU + send_delba(padapter, 0, psta->hwaddr);// recipient + + //TX AMPDU + send_delba(padapter, 1, psta->hwaddr);// // originator + phtpriv_sta->agg_enable_bitmap = 0x0;//reset + phtpriv_sta->candidate_tid_bitmap = 0x0;//reset +#endif //CONFIG_80211N_HT + +#ifdef CONFIG_80211AC_VHT + update_sta_vht_info_apmode(padapter, psta); +#endif + + update_ldpc_stbc_cap(psta); + + //todo: init other variables + + _rtw_memset((void*)&psta->sta_stats, 0, sizeof(struct stainfo_stats)); + + + //add ratid + //add_RATid(padapter, psta);//move to ap_sta_info_defer_update() + + + _enter_critical_bh(&psta->lock, &irqL); + psta->state |= _FW_LINKED; + _exit_critical_bh(&psta->lock, &irqL); + + +} + +static void update_ap_info(_adapter *padapter, struct sta_info *psta) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); +#ifdef CONFIG_80211N_HT + struct ht_priv *phtpriv_ap = &pmlmepriv->htpriv; +#endif //CONFIG_80211N_HT + + psta->wireless_mode = pmlmeext->cur_wireless_mode; + + psta->bssratelen = rtw_get_rateset_len(pnetwork->SupportedRates); + _rtw_memcpy(psta->bssrateset, pnetwork->SupportedRates, psta->bssratelen); + +#ifdef CONFIG_80211N_HT + //HT related cap + if(phtpriv_ap->ht_option) + { + //check if sta supports rx ampdu + //phtpriv_ap->ampdu_enable = phtpriv_ap->ampdu_enable; + + //check if sta support s Short GI 20M + if((phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_20)) + { + phtpriv_ap->sgi_20m = _TRUE; + } + //check if sta support s Short GI 40M + if((phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_40)) + { + phtpriv_ap->sgi_40m = _TRUE; + } + + psta->qos_option = _TRUE; + } + else + { + phtpriv_ap->ampdu_enable = _FALSE; + + phtpriv_ap->sgi_20m = _FALSE; + phtpriv_ap->sgi_40m = _FALSE; + } + + psta->bw_mode = pmlmeext->cur_bwmode; + phtpriv_ap->ch_offset = pmlmeext->cur_ch_offset; + + phtpriv_ap->agg_enable_bitmap = 0x0;//reset + phtpriv_ap->candidate_tid_bitmap = 0x0;//reset + + _rtw_memcpy(&psta->htpriv, &pmlmepriv->htpriv, sizeof(struct ht_priv)); + +#ifdef CONFIG_80211AC_VHT + _rtw_memcpy(&psta->vhtpriv, &pmlmepriv->vhtpriv, sizeof(struct vht_priv)); +#endif //CONFIG_80211AC_VHT + +#endif //CONFIG_80211N_HT + + psta->state |= WIFI_AP_STATE; /* Aries, add,fix bug of flush_cam_entry at STOP AP mode , 0724 */ +} + +static void rtw_set_hw_wmm_param(_adapter *padapter) +{ + u8 ACI, ACM, AIFS, ECWMin, ECWMax, aSifsTime; + u8 acm_mask; + u16 TXOP; + u32 acParm, i; + u32 edca[4], inx[4]; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct registry_priv *pregpriv = &padapter->registrypriv; + + acm_mask = 0; + + if (IsSupported5G(pmlmeext->cur_wireless_mode) || + (pmlmeext->cur_wireless_mode & WIRELESS_11_24N)) + aSifsTime = 16; + else + aSifsTime = 10; + + if (pmlmeinfo->WMM_enable == 0) { + padapter->mlmepriv.acm_mask = 0; + + AIFS = aSifsTime + (2 * pmlmeinfo->slotTime); + + if (pmlmeext->cur_wireless_mode & (WIRELESS_11G | WIRELESS_11A)) { + ECWMin = 4; + ECWMax = 10; + } else if (pmlmeext->cur_wireless_mode & WIRELESS_11B) { + ECWMin = 5; + ECWMax = 10; + } else { + ECWMin = 4; + ECWMax = 10; + } + + TXOP = 0; + acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm)); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm)); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm)); + + ECWMin = 2; + ECWMax = 3; + TXOP = 0x2f; + acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm)); + + } else { + edca[0] = edca[1] = edca[2] = edca[3] = 0; + + /*TODO:*/ + acm_mask = 0; + padapter->mlmepriv.acm_mask = acm_mask; + + /* + //BK + //AIFS = AIFSN * slot time + SIFS - r2t phy delay + */ + AIFS = (7 * pmlmeinfo->slotTime) + aSifsTime; + ECWMin = 4; + ECWMax = 10; + TXOP = 0; + acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm)); + edca[XMIT_BK_QUEUE] = acParm; + DBG_871X("WMM(BK): %x\n", acParm); + + /* BE */ + AIFS = (3 * pmlmeinfo->slotTime) + aSifsTime; + ECWMin = 4; + ECWMax = 6; + TXOP = 0; + acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm)); + edca[XMIT_BE_QUEUE] = acParm; + DBG_871X("WMM(BE): %x\n", acParm); + + /* VI */ + AIFS = (1 * pmlmeinfo->slotTime) + aSifsTime; + ECWMin = 3; + ECWMax = 4; + TXOP = 94; + acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm)); + edca[XMIT_VI_QUEUE] = acParm; + DBG_871X("WMM(VI): %x\n", acParm); + + /* VO */ + AIFS = (1 * pmlmeinfo->slotTime) + aSifsTime; + ECWMin = 2; + ECWMax = 3; + TXOP = 47; + acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm)); + edca[XMIT_VO_QUEUE] = acParm; + DBG_871X("WMM(VO): %x\n", acParm); + + + if (padapter->registrypriv.acm_method == 1) + rtw_hal_set_hwreg(padapter, HW_VAR_ACM_CTRL, (u8 *)(&acm_mask)); + else + padapter->mlmepriv.acm_mask = acm_mask; + + inx[0] = 0; inx[1] = 1; inx[2] = 2; inx[3] = 3; + + if (pregpriv->wifi_spec == 1) { + u32 j, tmp, change_inx = _FALSE; + + /* entry indx: 0->vo, 1->vi, 2->be, 3->bk. */ + for (i = 0 ; i < 4 ; i++) { + for (j = i+1 ; j < 4 ; j++) { + /* compare CW and AIFS */ + if ((edca[j] & 0xFFFF) < (edca[i] & 0xFFFF)) { + change_inx = _TRUE; + } else if ((edca[j] & 0xFFFF) == (edca[i] & 0xFFFF)) { + /* compare TXOP */ + if ((edca[j] >> 16) > (edca[i] >> 16)) + change_inx = _TRUE; + } + + if (change_inx) { + tmp = edca[i]; + edca[i] = edca[j]; + edca[j] = tmp; + + tmp = inx[i]; + inx[i] = inx[j]; + inx[j] = tmp; + + change_inx = _FALSE; + } + } + } + } + + for (i = 0 ; i < 4 ; i++) { + pxmitpriv->wmm_para_seq[i] = inx[i]; + DBG_871X("wmm_para_seq(%d): %d\n", i, pxmitpriv->wmm_para_seq[i]); + } + + } + +} + +static void update_hw_ht_param(_adapter *padapter) +{ + unsigned char max_AMPDU_len; + unsigned char min_MPDU_spacing; + struct registry_priv *pregpriv = &padapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + DBG_871X("%s\n", __FUNCTION__); + + + //handle A-MPDU parameter field + /* + AMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k + AMPDU_para [4:2]:Min MPDU Start Spacing + */ + max_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03; + + min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) >> 2; + + rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MIN_SPACE, (u8 *)(&min_MPDU_spacing)); + + rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&max_AMPDU_len)); + + // + // Config SM Power Save setting + // + pmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & 0x0C) >> 2; + if(pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC) + { + /*u8 i; + //update the MCS rates + for (i = 0; i < 16; i++) + { + pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i]; + }*/ + DBG_871X("%s(): WLAN_HT_CAP_SM_PS_STATIC\n",__FUNCTION__); + } + + // + // Config current HT Protection mode. + // + //pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3; + +} + +static void rtw_ap_check_scan(_adapter *padapter) +{ + _irqL irqL; + _list *plist, *phead; + u32 delta_time, lifetime; + struct wlan_network *pnetwork = NULL; + WLAN_BSSID_EX *pbss = NULL; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + _queue *queue = &(pmlmepriv->scanned_queue); + u8 do_scan = _FALSE; + + lifetime = SCANQUEUE_LIFETIME; /* 20 sec */ + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + phead = get_list_head(queue); + if (rtw_end_of_queue_search(phead, get_next(phead)) == _TRUE) + if (padapter->registrypriv.wifi_spec) + do_scan = _TRUE; + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + +#ifdef CONFIG_AUTO_CHNL_SEL_NHM + if (padapter->registrypriv.acs_auto_scan) { + do_scan = _TRUE; + rtw_acs_start(padapter, _TRUE); + } +#endif + + if (_TRUE == do_scan) { + DBG_871X("%s : drv scans by itself and wait_completed\n", __func__); + rtw_drv_scan_by_self(padapter); + rtw_scan_wait_completed(padapter); + } + +#ifdef CONFIG_AUTO_CHNL_SEL_NHM + if (padapter->registrypriv.acs_auto_scan) + rtw_acs_start(padapter, _FALSE); +#endif + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + while (1) { + + if (rtw_end_of_queue_search(phead, plist) == _TRUE) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + + if (rtw_ch_set_search_ch(padapter->mlmeextpriv.channel_set, pnetwork->network.Configuration.DSConfig) >= 0 + && rtw_mlme_band_check(padapter, pnetwork->network.Configuration.DSConfig) == _TRUE + && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid))) { + delta_time = (u32) rtw_get_passing_time_ms(pnetwork->last_scanned); + + if (delta_time < lifetime) { + + uint ie_len = 0; + u8 *pbuf = NULL; + u8 *ie = NULL; + + pbss = &pnetwork->network; + ie = pbss->IEs; + + /*check if HT CAP INFO IE exists or not*/ + pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pbss->IELength - _BEACON_IE_OFFSET_)); + if (pbuf == NULL) { + /* HT CAP INFO IE don't exist, it is b/g mode bss.*/ + + if (pmlmepriv->olbc == _FALSE) + pmlmepriv->olbc = _TRUE; + + if (pmlmepriv->olbc_ht == _FALSE) + pmlmepriv->olbc_ht = _TRUE; + } + } + } + + plist = get_next(plist); + + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + pmlmepriv->num_sta_no_ht = 0; /* reset to 0 after ap do scanning*/ + +} + +void rtw_start_bss_hdl_after_chbw_decided(_adapter *adapter) +{ + WLAN_BSSID_EX *pnetwork = &(adapter->mlmepriv.cur_network.network); + struct sta_info *sta = NULL; + + /* update cur_wireless_mode */ + update_wireless_mode(adapter); + + /* update RRSR and RTS_INIT_RATE register after set channel and bandwidth */ + UpdateBrateTbl(adapter, pnetwork->SupportedRates); + rtw_hal_set_hwreg(adapter, HW_VAR_BASIC_RATE, pnetwork->SupportedRates); + + /* update capability after cur_wireless_mode updated */ + update_capinfo(adapter, rtw_get_capability(pnetwork)); + + /* update bc/mc sta_info */ + update_bmc_sta(adapter); + + /* update AP's sta info */ + sta = rtw_get_stainfo(&adapter->stapriv, pnetwork->MacAddress); + if (!sta) { + DBG_871X(FUNC_ADPT_FMT" !sta for macaddr="MAC_FMT"\n", FUNC_ADPT_ARG(adapter), MAC_ARG(pnetwork->MacAddress)); + rtw_warn_on(1); + return; + } + + update_ap_info(adapter, sta); +} + +void start_bss_network(_adapter *padapter, struct createbss_parm *parm) +{ +#define DUMP_ADAPTERS_STATUS 0 + + u8 val8; + u16 bcn_interval; + u32 acparm; + struct registry_priv *pregpriv = &padapter->registrypriv; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct security_priv* psecuritypriv=&(padapter->securitypriv); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; /* used as input */ + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork_mlmeext = &(pmlmeinfo->network); + u8 req_ch, req_bw, req_offset; + bool ch_setting_changed = _FALSE; + u8 ch_to_set = 0, bw_to_set, offset_to_set; + u8 doiqk = _FALSE; + + if (parm->req_ch == 0) { + /* change to unspecificed ch, bw, offset, get from IE */ + goto get_cbhw_from_ie; + } else if (parm->req_ch > 0) { + /* change ch, bw, offset */ + req_ch = parm->req_ch; + req_bw = parm->req_bw; + req_offset = parm->req_offset; + goto change_chbw; + } + + bcn_interval = (u16)pnetwork->Configuration.BeaconPeriod; + + //check if there is wps ie, + //if there is wpsie in beacon, the hostapd will update beacon twice when stating hostapd, + //and at first time the security ie ( RSN/WPA IE) will not include in beacon. + if(NULL == rtw_get_wps_ie(pnetwork->IEs+_FIXED_IE_LENGTH_, pnetwork->IELength-_FIXED_IE_LENGTH_, NULL, NULL)) + { + pmlmeext->bstart_bss = _TRUE; + } + + //todo: update wmm, ht cap + //pmlmeinfo->WMM_enable; + //pmlmeinfo->HT_enable; + if(pmlmepriv->qospriv.qos_option) + pmlmeinfo->WMM_enable = _TRUE; +#ifdef CONFIG_80211N_HT + if(pmlmepriv->htpriv.ht_option) + { + pmlmeinfo->WMM_enable = _TRUE; + pmlmeinfo->HT_enable = _TRUE; + //pmlmeinfo->HT_info_enable = _TRUE; + //pmlmeinfo->HT_caps_enable = _TRUE; + + update_hw_ht_param(padapter); + } +#endif //#CONFIG_80211N_HT + +#ifdef CONFIG_80211AC_VHT + if(pmlmepriv->vhtpriv.vht_option) { + pmlmeinfo->VHT_enable = _TRUE; + update_hw_vht_param(padapter); + } +#endif //CONFIG_80211AC_VHT + + if(pmlmepriv->cur_network.join_res != _TRUE) //setting only at first time + { + //WEP Key will be set before this function, do not clear CAM. + if ((psecuritypriv->dot11PrivacyAlgrthm != _WEP40_) && (psecuritypriv->dot11PrivacyAlgrthm != _WEP104_)) + flush_all_cam_entry(padapter); //clear CAM + } + + //set MSR to AP_Mode + Set_MSR(padapter, _HW_STATE_AP_); + + //Set BSSID REG + rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pnetwork->MacAddress); + + //Set EDCA param reg +#ifdef CONFIG_CONCURRENT_MODE + acparm = 0x005ea42b; +#else + acparm = 0x002F3217; // VO +#endif + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acparm)); + acparm = 0x005E4317; // VI + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acparm)); + //acparm = 0x00105320; // BE + acparm = 0x005ea42b; + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm)); + acparm = 0x0000A444; // BK + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acparm)); + + //Set Security + val8 = (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)? 0xcc: 0xcf; + rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); + + //Beacon Control related register + rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&bcn_interval)); + +#if 0 + if(pmlmepriv->cur_network.join_res != _TRUE) //setting only at first time + { + //u32 initialgain; + + //initialgain = 0x1e; + + + //disable dynamic functions, such as high power, DIG + /*rtw_phydm_ability_backup(padapter);*/ + /*rtw_phydm_func_disable_all(padapter);*/ + + //turn on all dynamic functions + /* Switch_DM_Func(padapter, DYNAMIC_ALL_FUNC_ENABLE, _TRUE);*/ + + /*rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, _FALSE);*/ + + } +#endif + +get_cbhw_from_ie: + rtw_ies_get_chbw(pnetwork->IEs + sizeof(NDIS_802_11_FIXED_IEs) + , pnetwork->IELength - sizeof(NDIS_802_11_FIXED_IEs) + , &req_ch, &req_bw, &req_offset); + +change_chbw: + rtw_warn_on(req_ch == 0); + + ch_setting_changed = rtw_ap_chbw_decision(padapter, req_ch, req_bw, req_offset + , &ch_to_set, &bw_to_set, &offset_to_set); + + //let pnetwork_mlmeext == pnetwork_mlme. + _rtw_memcpy(pnetwork_mlmeext, pnetwork, pnetwork->Length); + + rtw_start_bss_hdl_after_chbw_decided(padapter); + + #if defined(CONFIG_DFS_MASTER) + rtw_dfs_master_status_apply(padapter, MLME_AP_STARTED); + #endif + + doiqk = _TRUE; + rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); + + if (ch_to_set != 0) + set_channel_bwmode(padapter, ch_to_set, offset_to_set, bw_to_set); + + doiqk = _FALSE; + rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); + if (DUMP_ADAPTERS_STATUS) { + DBG_871X(FUNC_ADPT_FMT" done\n", FUNC_ADPT_ARG(padapter)); + dump_adapters_status(RTW_DBGDUMP , adapter_to_dvobj(padapter)); + } + + if (_TRUE == pmlmeext->bstart_bss + && !check_fwstate(pmlmepriv, WIFI_SITE_MONITOR) + && !check_fwstate(pmlmepriv, WIFI_OP_CH_SWITCHING) + #ifdef CONFIG_CONCURRENT_MODE + && !check_buddy_fwstate(padapter, WIFI_SITE_MONITOR) + #endif + ) { + + if ((pmlmepriv->olbc == _TRUE) || (pmlmepriv->olbc_ht == _TRUE)) { + + /* AP is not starting a 40 MHz BSS in presence of an 802.11g BSS. */ + + pmlmepriv->ht_op_mode &= (~HT_INFO_OPERATION_MODE_OP_MODE_MASK); + pmlmepriv->ht_op_mode |= OP_MODE_MAY_BE_LEGACY_STAS; + update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _FALSE); + } + + update_beacon(padapter, _TIM_IE_, NULL, _TRUE); + + #if !defined(CONFIG_INTERRUPT_BASED_TXBCN) + #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + /* other case will tx beacon when bcn interrupt coming in. */ + if (send_beacon(padapter) == _FAIL) + DBG_871X("issue_beacon, fail!\n"); + #endif + #endif /* !defined(CONFIG_INTERRUPT_BASED_TXBCN) */ + } + + /*Set EDCA param reg after update cur_wireless_mode & update_capinfo*/ + if (pregpriv->wifi_spec == 1) + rtw_set_hw_wmm_param(padapter); + + /*pmlmeext->bstart_bss = _TRUE;*/ +} + +int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) +{ + int ret=_SUCCESS; + u8 *p; + u8 *pHT_caps_ie=NULL; + u8 *pHT_info_ie=NULL; + u16 cap, ht_cap=_FALSE; + uint ie_len = 0; + int group_cipher, pairwise_cipher; + u8 channel, network_type, supportRate[NDIS_802_11_LENGTH_RATES_EX]; + int supportRateNum = 0; + u8 OUI1[] = {0x00, 0x50, 0xf2,0x01}; + u8 wps_oui[4]={0x0,0x50,0xf2,0x04}; + u8 WMM_PARA_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01}; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + WLAN_BSSID_EX *pbss_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 *ie = pbss_network->IEs; + u8 vht_cap=_FALSE; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 rf_num = 0; + + /* SSID */ + /* Supported rates */ + /* DS Params */ + /* WLAN_EID_COUNTRY */ + /* ERP Information element */ + /* Extended supported rates */ + /* WPA/WPA2 */ + /* Wi-Fi Wireless Multimedia Extensions */ + /* ht_capab, ht_oper */ + /* WPS IE */ + + DBG_871X("%s, len=%d\n", __FUNCTION__, len); + + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + return _FAIL; + + + if(len>MAX_IE_SZ) + return _FAIL; + + pbss_network->IELength = len; + + _rtw_memset(ie, 0, MAX_IE_SZ); + + _rtw_memcpy(ie, pbuf, pbss_network->IELength); + + + if(pbss_network->InfrastructureMode!=Ndis802_11APMode) + return _FAIL; + + + rtw_ap_check_scan(padapter); + + + pbss_network->Rssi = 0; + + _rtw_memcpy(pbss_network->MacAddress, adapter_mac_addr(padapter), ETH_ALEN); + + //beacon interval + p = rtw_get_beacon_interval_from_ie(ie);//ie + 8; // 8: TimeStamp, 2: Beacon Interval 2:Capability + //pbss_network->Configuration.BeaconPeriod = le16_to_cpu(*(unsigned short*)p); + pbss_network->Configuration.BeaconPeriod = RTW_GET_LE16(p); + + //capability + //cap = *(unsigned short *)rtw_get_capability_from_ie(ie); + //cap = le16_to_cpu(cap); + cap = RTW_GET_LE16(ie); + + //SSID + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _SSID_IE_, &ie_len, (pbss_network->IELength -_BEACON_IE_OFFSET_)); + if(p && ie_len>0) + { + _rtw_memset(&pbss_network->Ssid, 0, sizeof(NDIS_802_11_SSID)); + _rtw_memcpy(pbss_network->Ssid.Ssid, (p + 2), ie_len); + pbss_network->Ssid.SsidLength = ie_len; + #ifdef CONFIG_P2P + _rtw_memcpy(padapter->wdinfo.p2p_group_ssid, pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength); + padapter->wdinfo.p2p_group_ssid_len = pbss_network->Ssid.SsidLength; + #endif + } + + //chnnel + channel = 0; + pbss_network->Configuration.Length = 0; + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _DSSET_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); + if(p && ie_len>0) + channel = *(p + 2); + + pbss_network->Configuration.DSConfig = channel; + + + _rtw_memset(supportRate, 0, NDIS_802_11_LENGTH_RATES_EX); + // get supported rates + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _SUPPORTEDRATES_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); + if (p != NULL) + { + _rtw_memcpy(supportRate, p+2, ie_len); + supportRateNum = ie_len; + } + + //get ext_supported rates + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EXT_SUPPORTEDRATES_IE_, &ie_len, pbss_network->IELength - _BEACON_IE_OFFSET_); + if (p != NULL) + { + _rtw_memcpy(supportRate+supportRateNum, p+2, ie_len); + supportRateNum += ie_len; + + } + + network_type = rtw_check_network_type(supportRate, supportRateNum, channel); + + rtw_set_supported_rate(pbss_network->SupportedRates, network_type); + + + //parsing ERP_IE + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _ERPINFO_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); + if(p && ie_len>0) + { + ERP_IE_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)p); + } + + //update privacy/security + if (cap & BIT(4)) + pbss_network->Privacy = 1; + else + pbss_network->Privacy = 0; + + psecuritypriv->wpa_psk = 0; + + //wpa2 + group_cipher = 0; pairwise_cipher = 0; + psecuritypriv->wpa2_group_cipher = _NO_PRIVACY_; + psecuritypriv->wpa2_pairwise_cipher = _NO_PRIVACY_; + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); + if(p && ie_len>0) + { + if(rtw_parse_wpa2_ie(p, ie_len+2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) + { + psecuritypriv->dot11AuthAlgrthm= dot11AuthAlgrthm_8021X; + + psecuritypriv->dot8021xalg = 1;//psk, todo:802.1x + psecuritypriv->wpa_psk |= BIT(1); + + psecuritypriv->wpa2_group_cipher = group_cipher; + psecuritypriv->wpa2_pairwise_cipher = pairwise_cipher; +#if 0 + switch(group_cipher) + { + case WPA_CIPHER_NONE: + psecuritypriv->wpa2_group_cipher = _NO_PRIVACY_; + break; + case WPA_CIPHER_WEP40: + psecuritypriv->wpa2_group_cipher = _WEP40_; + break; + case WPA_CIPHER_TKIP: + psecuritypriv->wpa2_group_cipher = _TKIP_; + break; + case WPA_CIPHER_CCMP: + psecuritypriv->wpa2_group_cipher = _AES_; + break; + case WPA_CIPHER_WEP104: + psecuritypriv->wpa2_group_cipher = _WEP104_; + break; + } + + switch(pairwise_cipher) + { + case WPA_CIPHER_NONE: + psecuritypriv->wpa2_pairwise_cipher = _NO_PRIVACY_; + break; + case WPA_CIPHER_WEP40: + psecuritypriv->wpa2_pairwise_cipher = _WEP40_; + break; + case WPA_CIPHER_TKIP: + psecuritypriv->wpa2_pairwise_cipher = _TKIP_; + break; + case WPA_CIPHER_CCMP: + psecuritypriv->wpa2_pairwise_cipher = _AES_; + break; + case WPA_CIPHER_WEP104: + psecuritypriv->wpa2_pairwise_cipher = _WEP104_; + break; + } +#endif + } + + } + + //wpa + ie_len = 0; + group_cipher = 0; pairwise_cipher = 0; + psecuritypriv->wpa_group_cipher = _NO_PRIVACY_; + psecuritypriv->wpa_pairwise_cipher = _NO_PRIVACY_; + for (p = ie + _BEACON_IE_OFFSET_; ;p += (ie_len + 2)) + { + p = rtw_get_ie(p, _SSN_IE_1_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2))); + if ((p) && (_rtw_memcmp(p+2, OUI1, 4))) + { + if(rtw_parse_wpa_ie(p, ie_len+2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) + { + psecuritypriv->dot11AuthAlgrthm= dot11AuthAlgrthm_8021X; + + psecuritypriv->dot8021xalg = 1;//psk, todo:802.1x + + psecuritypriv->wpa_psk |= BIT(0); + + psecuritypriv->wpa_group_cipher = group_cipher; + psecuritypriv->wpa_pairwise_cipher = pairwise_cipher; + +#if 0 + switch(group_cipher) + { + case WPA_CIPHER_NONE: + psecuritypriv->wpa_group_cipher = _NO_PRIVACY_; + break; + case WPA_CIPHER_WEP40: + psecuritypriv->wpa_group_cipher = _WEP40_; + break; + case WPA_CIPHER_TKIP: + psecuritypriv->wpa_group_cipher = _TKIP_; + break; + case WPA_CIPHER_CCMP: + psecuritypriv->wpa_group_cipher = _AES_; + break; + case WPA_CIPHER_WEP104: + psecuritypriv->wpa_group_cipher = _WEP104_; + break; + } + + switch(pairwise_cipher) + { + case WPA_CIPHER_NONE: + psecuritypriv->wpa_pairwise_cipher = _NO_PRIVACY_; + break; + case WPA_CIPHER_WEP40: + psecuritypriv->wpa_pairwise_cipher = _WEP40_; + break; + case WPA_CIPHER_TKIP: + psecuritypriv->wpa_pairwise_cipher = _TKIP_; + break; + case WPA_CIPHER_CCMP: + psecuritypriv->wpa_pairwise_cipher = _AES_; + break; + case WPA_CIPHER_WEP104: + psecuritypriv->wpa_pairwise_cipher = _WEP104_; + break; + } +#endif + } + + break; + + } + + if ((p == NULL) || (ie_len == 0)) + { + break; + } + + } + + //wmm + ie_len = 0; + pmlmepriv->qospriv.qos_option = 0; + if(pregistrypriv->wmm_enable) + { + for (p = ie + _BEACON_IE_OFFSET_; ;p += (ie_len + 2)) + { + p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2))); + if((p) && _rtw_memcmp(p+2, WMM_PARA_IE, 6)) + { + pmlmepriv->qospriv.qos_option = 1; + + *(p+8) |= BIT(7);//QoS Info, support U-APSD + + /* disable all ACM bits since the WMM admission control is not supported */ + *(p + 10) &= ~BIT(4); /* BE */ + *(p + 14) &= ~BIT(4); /* BK */ + *(p + 18) &= ~BIT(4); /* VI */ + *(p + 22) &= ~BIT(4); /* VO */ + + break; + } + + if ((p == NULL) || (ie_len == 0)) + { + break; + } + } + } +#ifdef CONFIG_80211N_HT + //parsing HT_CAP_IE + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); + if(p && ie_len>0) + { + u8 rf_type=0; + HT_CAP_AMPDU_FACTOR max_rx_ampdu_factor=MAX_AMPDU_FACTOR_64K; + struct rtw_ieee80211_ht_cap *pht_cap = (struct rtw_ieee80211_ht_cap *)(p+2); + + if (0) { + DBG_871X(FUNC_ADPT_FMT" HT_CAP_IE from upper layer:\n", FUNC_ADPT_ARG(padapter)); + dump_ht_cap_ie_content(RTW_DBGDUMP, p+2, ie_len); + } + + pHT_caps_ie=p; + + ht_cap = _TRUE; + network_type |= WIRELESS_11_24N; + + rtw_ht_use_default_setting(padapter); + + /* Update HT Capabilities Info field */ + if (pmlmepriv->htpriv.sgi_20m == _FALSE) + pht_cap->cap_info &= ~(IEEE80211_HT_CAP_SGI_20); + + if (pmlmepriv->htpriv.sgi_40m == _FALSE) + pht_cap->cap_info &= ~(IEEE80211_HT_CAP_SGI_40); + + if (!TEST_FLAG(pmlmepriv->htpriv.ldpc_cap, LDPC_HT_ENABLE_RX)) + { + pht_cap->cap_info &= ~(IEEE80211_HT_CAP_LDPC_CODING); + } + + if (!TEST_FLAG(pmlmepriv->htpriv.stbc_cap, STBC_HT_ENABLE_TX)) + { + pht_cap->cap_info &= ~(IEEE80211_HT_CAP_TX_STBC); + } + + if (!TEST_FLAG(pmlmepriv->htpriv.stbc_cap, STBC_HT_ENABLE_RX)) + { + pht_cap->cap_info &= ~(IEEE80211_HT_CAP_RX_STBC_3R); + } + + /* Update A-MPDU Parameters field */ + pht_cap->ampdu_params_info &= ~(IEEE80211_HT_CAP_AMPDU_FACTOR|IEEE80211_HT_CAP_AMPDU_DENSITY); + + if((psecuritypriv->wpa_pairwise_cipher & WPA_CIPHER_CCMP) || + (psecuritypriv->wpa2_pairwise_cipher & WPA_CIPHER_CCMP)) + { + pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY&(0x07<<2)); + } + else + { + pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY&0x00); + } + + rtw_hal_get_def_var(padapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor); + pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_FACTOR & max_rx_ampdu_factor); //set Max Rx AMPDU size to 64K + + _rtw_memcpy(&(pmlmeinfo->HT_caps), pht_cap, sizeof(struct HT_caps_element)); + + /* Update Supported MCS Set field */ + { + int i; + + rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + + /* RX MCS Bitmask */ + switch(rf_type) + { + case RF_1T1R: + case RF_1T2R: //? + set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_1R); + break; + case RF_2T2R: + set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_2R); + break; + case RF_3T3R: + set_mcs_rate_by_mask(HT_CAP_ELE_RX_MCS_MAP(pht_cap), MCS_RATE_3R); + break; + default: + DBG_871X("[warning] rf_type %d is not expected\n", rf_type); + } + for (i = 0; i < 10; i++) + *(HT_CAP_ELE_RX_MCS_MAP(pht_cap)+i) &= padapter->mlmeextpriv.default_supported_mcs_set[i]; + } + +#ifdef CONFIG_BEAMFORMING + // Use registry value to enable HT Beamforming. + // ToDo: use configure file to set these capability. + pht_cap->tx_BF_cap_info = 0; + + // HT Beamformer + if(TEST_FLAG(pmlmepriv->htpriv.beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) + { + // Transmit NDP Capable + SET_HT_CAP_TXBF_TRANSMIT_NDP_CAP(pht_cap, 1); + // Explicit Compressed Steering Capable + SET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pht_cap, 1); + // Compressed Steering Number Antennas + SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pht_cap, 1); + rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&rf_num); + SET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pht_cap, rf_num); + } + + // HT Beamformee + if(TEST_FLAG(pmlmepriv->htpriv.beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) + { + // Receive NDP Capable + SET_HT_CAP_TXBF_RECEIVE_NDP_CAP(pht_cap, 1); + // Explicit Compressed Beamforming Feedback Capable + SET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pht_cap, 2); + rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num); + SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pht_cap, rf_num); + } +#endif //CONFIG_BEAMFORMING + + _rtw_memcpy(&pmlmepriv->htpriv.ht_cap, p+2, ie_len); + + if (0) { + DBG_871X(FUNC_ADPT_FMT" HT_CAP_IE driver masked:\n", FUNC_ADPT_ARG(padapter)); + dump_ht_cap_ie_content(RTW_DBGDUMP, p+2, ie_len); + } + } + + //parsing HT_INFO_IE + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); + if(p && ie_len>0) + { + pHT_info_ie=p; + } +#endif //CONFIG_80211N_HT + switch(network_type) + { + case WIRELESS_11B: + pbss_network->NetworkTypeInUse = Ndis802_11DS; + break; + case WIRELESS_11G: + case WIRELESS_11BG: + case WIRELESS_11G_24N: + case WIRELESS_11BG_24N: + pbss_network->NetworkTypeInUse = Ndis802_11OFDM24; + break; + case WIRELESS_11A: + pbss_network->NetworkTypeInUse = Ndis802_11OFDM5; + break; + default : + pbss_network->NetworkTypeInUse = Ndis802_11OFDM24; + break; + } + + pmlmepriv->cur_network.network_type = network_type; + +#ifdef CONFIG_80211N_HT + pmlmepriv->htpriv.ht_option = _FALSE; + + if( (psecuritypriv->wpa2_pairwise_cipher&WPA_CIPHER_TKIP) || + (psecuritypriv->wpa_pairwise_cipher&WPA_CIPHER_TKIP)) + { + //todo: + //ht_cap = _FALSE; + } + + //ht_cap + if(pregistrypriv->ht_enable && ht_cap==_TRUE) + { + pmlmepriv->htpriv.ht_option = _TRUE; + pmlmepriv->qospriv.qos_option = 1; + + if(pregistrypriv->ampdu_enable==1) + { + pmlmepriv->htpriv.ampdu_enable = _TRUE; + } + + HT_caps_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)pHT_caps_ie); + + HT_info_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)pHT_info_ie); + } +#endif + +#ifdef CONFIG_80211AC_VHT + + //Parsing VHT CAP IE + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); + if(p && ie_len>0) + { + vht_cap = _TRUE; + } + //Parsing VHT OPERATION IE + + + pmlmepriv->vhtpriv.vht_option = _FALSE; + // if channel in 5G band, then add vht ie . + if ((pbss_network->Configuration.DSConfig > 14) + && (pmlmepriv->htpriv.ht_option == _TRUE) + && REGSTY_IS_11AC_ENABLE(pregistrypriv) + && hal_chk_proto_cap(padapter, PROTO_CAP_11AC) + && (!pmlmepriv->country_ent || COUNTRY_CHPLAN_EN_11AC(pmlmepriv->country_ent)) + ) { + if (vht_cap == _TRUE) + pmlmepriv->vhtpriv.vht_option = _TRUE; + else if (REGSTY_IS_11AC_AUTO(pregistrypriv)) { + u8 cap_len, operation_len; + + rtw_vht_use_default_setting(padapter); + + { + /* VHT Operation mode notifiy bit in Extended IE (127) */ + uint len = 0; + + SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(pmlmepriv->ext_capab_ie_data, 1); + pmlmepriv->ext_capab_ie_len = 10; + rtw_set_ie(pbss_network->IEs + pbss_network->IELength, EID_EXTCapability, 8, pmlmepriv->ext_capab_ie_data, &len); + pbss_network->IELength += pmlmepriv->ext_capab_ie_len; + } + + // VHT Capabilities element + cap_len = rtw_build_vht_cap_ie(padapter, pbss_network->IEs + pbss_network->IELength); + pbss_network->IELength += cap_len; + + // VHT Operation element + operation_len = rtw_build_vht_operation_ie(padapter, pbss_network->IEs + pbss_network->IELength, pbss_network->Configuration.DSConfig); + pbss_network->IELength += operation_len; + + pmlmepriv->vhtpriv.vht_option = _TRUE; + } + } +#endif //CONFIG_80211AC_VHT + + if(pbss_network->Configuration.DSConfig <= 14 && padapter->registrypriv.wifi_spec == 1) { + uint len = 0; + + SET_EXT_CAPABILITY_ELE_BSS_COEXIST(pmlmepriv->ext_capab_ie_data, 1); + pmlmepriv->ext_capab_ie_len = 10; + rtw_set_ie(pbss_network->IEs + pbss_network->IELength, EID_EXTCapability, 8, pmlmepriv->ext_capab_ie_data, &len); + pbss_network->IELength += pmlmepriv->ext_capab_ie_len; + } + + pbss_network->Length = get_WLAN_BSSID_EX_sz((WLAN_BSSID_EX *)pbss_network); + + rtw_ies_get_chbw(pbss_network->IEs + _BEACON_IE_OFFSET_, pbss_network->IELength - _BEACON_IE_OFFSET_ + , &pmlmepriv->ori_ch, &pmlmepriv->ori_bw, &pmlmepriv->ori_offset); + rtw_warn_on(pmlmepriv->ori_ch == 0); + +{ + /* alloc sta_info for ap itself */ + + struct sta_info *sta; + + sta = rtw_get_stainfo(&padapter->stapriv, pbss_network->MacAddress); + if (!sta) { + sta = rtw_alloc_stainfo(&padapter->stapriv, pbss_network->MacAddress); + if (sta == NULL) + return _FAIL; + } +} + + rtw_startbss_cmd(padapter, RTW_CMDF_WAIT_ACK); + + rtw_indicate_connect( padapter); + + pmlmepriv->cur_network.join_res = _TRUE;//for check if already set beacon + + //update bc/mc sta_info + //update_bmc_sta(padapter); + + return ret; + +} + +void rtw_set_macaddr_acl(_adapter *padapter, int mode) +{ + struct sta_priv *pstapriv = &padapter->stapriv; + struct wlan_acl_pool *pacl_list = &pstapriv->acl_list; + + DBG_871X("%s, mode=%d\n", __func__, mode); + + pacl_list->mode = mode; +} + +int rtw_acl_add_sta(_adapter *padapter, u8 *addr) +{ + _irqL irqL; + _list *plist, *phead; + u8 added = _FALSE; + int i, ret=0; + struct rtw_wlan_acl_node *paclnode; + struct sta_priv *pstapriv = &padapter->stapriv; + struct wlan_acl_pool *pacl_list = &pstapriv->acl_list; + _queue *pacl_node_q =&pacl_list->acl_node_q; + + DBG_871X("%s(acl_num=%d)=" MAC_FMT "\n", __func__, pacl_list->num, MAC_ARG(addr)); + + if((NUM_ACL-1) < pacl_list->num) + return (-1); + + + _enter_critical_bh(&(pacl_node_q->lock), &irqL); + + phead = get_list_head(pacl_node_q); + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) + { + paclnode = LIST_CONTAINOR(plist, struct rtw_wlan_acl_node, list); + plist = get_next(plist); + + if(_rtw_memcmp(paclnode->addr, addr, ETH_ALEN)) + { + if(paclnode->valid == _TRUE) + { + added = _TRUE; + DBG_871X("%s, sta has been added\n", __func__); + break; + } + } + } + + _exit_critical_bh(&(pacl_node_q->lock), &irqL); + + + if(added == _TRUE) + return ret; + + + _enter_critical_bh(&(pacl_node_q->lock), &irqL); + + for(i=0; i< NUM_ACL; i++) + { + paclnode = &pacl_list->aclnode[i]; + + if(paclnode->valid == _FALSE) + { + _rtw_init_listhead(&paclnode->list); + + _rtw_memcpy(paclnode->addr, addr, ETH_ALEN); + + paclnode->valid = _TRUE; + + rtw_list_insert_tail(&paclnode->list, get_list_head(pacl_node_q)); + + pacl_list->num++; + + break; + } + } + + DBG_871X("%s, acl_num=%d\n", __func__, pacl_list->num); + + _exit_critical_bh(&(pacl_node_q->lock), &irqL); + + return ret; +} + +int rtw_acl_remove_sta(_adapter *padapter, u8 *addr) +{ + _irqL irqL; + _list *plist, *phead; + int i, ret=0; + struct rtw_wlan_acl_node *paclnode; + struct sta_priv *pstapriv = &padapter->stapriv; + struct wlan_acl_pool *pacl_list = &pstapriv->acl_list; + _queue *pacl_node_q =&pacl_list->acl_node_q; + u8 baddr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; //Baddr is used for clearing acl_list + + DBG_871X("%s(acl_num=%d)=" MAC_FMT "\n", __func__, pacl_list->num, MAC_ARG(addr)); + + _enter_critical_bh(&(pacl_node_q->lock), &irqL); + + phead = get_list_head(pacl_node_q); + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) + { + paclnode = LIST_CONTAINOR(plist, struct rtw_wlan_acl_node, list); + plist = get_next(plist); + + if(_rtw_memcmp(paclnode->addr, addr, ETH_ALEN) || _rtw_memcmp(baddr, addr, ETH_ALEN)) + { + if(paclnode->valid == _TRUE) + { + paclnode->valid = _FALSE; + + rtw_list_delete(&paclnode->list); + + pacl_list->num--; + } + } + } + + _exit_critical_bh(&(pacl_node_q->lock), &irqL); + + DBG_871X("%s, acl_num=%d\n", __func__, pacl_list->num); + + return ret; + +} + +u8 rtw_ap_set_pairwise_key(_adapter *padapter, struct sta_info *psta) +{ + struct cmd_obj* ph2c; + struct set_stakey_parm *psetstakey_para; + struct cmd_priv *pcmdpriv=&padapter->cmdpriv; + u8 res=_SUCCESS; + + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if ( ph2c == NULL){ + res= _FAIL; + goto exit; + } + + psetstakey_para = (struct set_stakey_parm*)rtw_zmalloc(sizeof(struct set_stakey_parm)); + if(psetstakey_para==NULL){ + rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); + res=_FAIL; + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, _SetStaKey_CMD_); + + + psetstakey_para->algorithm = (u8)psta->dot118021XPrivacy; + + _rtw_memcpy(psetstakey_para->addr, psta->hwaddr, ETH_ALEN); + + _rtw_memcpy(psetstakey_para->key, &psta->dot118021x_UncstKey, 16); + + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + + return res; + +} + +static int rtw_ap_set_key(_adapter *padapter, u8 *key, u8 alg, int keyid, u8 set_tx) +{ + u8 keylen; + struct cmd_obj* pcmd; + struct setkey_parm *psetkeyparm; + struct cmd_priv *pcmdpriv=&(padapter->cmdpriv); + int res=_SUCCESS; + + //DBG_871X("%s\n", __FUNCTION__); + + pcmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(pcmd==NULL){ + res= _FAIL; + goto exit; + } + psetkeyparm=(struct setkey_parm*)rtw_zmalloc(sizeof(struct setkey_parm)); + if(psetkeyparm==NULL){ + rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj)); + res= _FAIL; + goto exit; + } + + _rtw_memset(psetkeyparm, 0, sizeof(struct setkey_parm)); + + psetkeyparm->keyid=(u8)keyid; + if (is_wep_enc(alg)) + padapter->securitypriv.key_mask |= BIT(psetkeyparm->keyid); + + psetkeyparm->algorithm = alg; + + psetkeyparm->set_tx = set_tx; + + switch(alg) + { + case _WEP40_: + keylen = 5; + break; + case _WEP104_: + keylen = 13; + break; + case _TKIP_: + case _TKIP_WTMIC_: + case _AES_: + default: + keylen = 16; + } + + _rtw_memcpy(&(psetkeyparm->key[0]), key, keylen); + + pcmd->cmdcode = _SetKey_CMD_; + pcmd->parmbuf = (u8 *)psetkeyparm; + pcmd->cmdsz = (sizeof(struct setkey_parm)); + pcmd->rsp = NULL; + pcmd->rspsz = 0; + + + _rtw_init_listhead(&pcmd->list); + + res = rtw_enqueue_cmd(pcmdpriv, pcmd); + +exit: + + return res; +} + +int rtw_ap_set_group_key(_adapter *padapter, u8 *key, u8 alg, int keyid) +{ + DBG_871X("%s\n", __FUNCTION__); + + return rtw_ap_set_key(padapter, key, alg, keyid, 1); +} + +int rtw_ap_set_wep_key(_adapter *padapter, u8 *key, u8 keylen, int keyid, u8 set_tx) +{ + u8 alg; + + switch(keylen) + { + case 5: + alg =_WEP40_; + break; + case 13: + alg =_WEP104_; + break; + default: + alg =_NO_PRIVACY_; + } + + DBG_871X("%s\n", __FUNCTION__); + + return rtw_ap_set_key(padapter, key, alg, keyid, set_tx); +} + +u8 rtw_ap_bmc_frames_hdl(_adapter *padapter) +{ +#define HIQ_XMIT_COUNTS (6) + _irqL irqL; + struct sta_info *psta_bmc; + _list *xmitframe_plist, *xmitframe_phead; + struct xmit_frame *pxmitframe = NULL; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct sta_priv *pstapriv = &padapter->stapriv; + bool update_tim = _FALSE; + + + if (padapter->registrypriv.wifi_spec != 1) + return H2C_SUCCESS; + + + psta_bmc = rtw_get_bcmc_stainfo(padapter); + if (!psta_bmc) + return H2C_SUCCESS; + + + _enter_critical_bh(&pxmitpriv->lock, &irqL); + + if ((pstapriv->tim_bitmap & BIT(0)) && (psta_bmc->sleepq_len > 0)) { + int tx_counts = 0; + + _update_beacon(padapter, _TIM_IE_, NULL, _FALSE, "update TIM with TIB=1"); + + DBG_871X("sleepq_len of bmc_sta = %d\n", psta_bmc->sleepq_len); + + xmitframe_phead = get_list_head(&psta_bmc->sleep_q); + xmitframe_plist = get_next(xmitframe_phead); + + while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) { + pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); + + xmitframe_plist = get_next(xmitframe_plist); + + rtw_list_delete(&pxmitframe->list); + + psta_bmc->sleepq_len--; + tx_counts++; + + if (psta_bmc->sleepq_len > 0) + pxmitframe->attrib.mdata = 1; + else + pxmitframe->attrib.mdata = 0; + + if (tx_counts == HIQ_XMIT_COUNTS) + pxmitframe->attrib.mdata = 0; + + pxmitframe->attrib.triggered = 1; + + if (xmitframe_hiq_filter(pxmitframe) == _TRUE) + pxmitframe->attrib.qsel = QSLT_HIGH;/*HIQ*/ + + rtw_hal_xmitframe_enqueue(padapter, pxmitframe); + + if (tx_counts == HIQ_XMIT_COUNTS) + break; + + } + + } else { + if (psta_bmc->sleepq_len == 0) { + + /*DBG_871X("sleepq_len of bmc_sta = %d\n", psta_bmc->sleepq_len);*/ + + if (pstapriv->tim_bitmap & BIT(0)) + update_tim = _TRUE; + + pstapriv->tim_bitmap &= ~BIT(0); + pstapriv->sta_dz_bitmap &= ~BIT(0); + + if (update_tim == _TRUE) { + DBG_871X("clear TIB\n"); + _update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "bmc sleepq and HIQ empty"); + } + } + } + + _exit_critical_bh(&pxmitpriv->lock, &irqL); + +/* + //HIQ Check + rtw_hal_get_hwreg(padapter, HW_VAR_CHK_HI_QUEUE_EMPTY, &empty); + + while (_FALSE == empty && rtw_get_passing_time_ms(start) < 3000) + { + rtw_msleep_os(100); + rtw_hal_get_hwreg(padapter, HW_VAR_CHK_HI_QUEUE_EMPTY, &empty); + } + + + printk("check if hiq empty=%d\n", empty); +*/ + + return H2C_SUCCESS; +} + +#ifdef CONFIG_NATIVEAP_MLME + +static void associated_stainfo_update(_adapter *padapter, struct sta_info *psta, u32 sta_info_type) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + DBG_871X("%s: "MAC_FMT", updated_type=0x%x\n", __func__, MAC_ARG(psta->hwaddr), sta_info_type); + + if (sta_info_type & STA_INFO_UPDATE_BW) { + + if ((psta->flags & WLAN_STA_HT) && !psta->ht_20mhz_set) { + if (pmlmepriv->sw_to_20mhz) { + psta->bw_mode = CHANNEL_WIDTH_20; + /*psta->htpriv.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;*/ + psta->htpriv.sgi_40m = _FALSE; + } else { + /*TODO: Switch back to 40MHZ?80MHZ*/ + } + } + } + +/* + if (sta_info_type & STA_INFO_UPDATE_RATE) { + + } +*/ + + if (sta_info_type & STA_INFO_UPDATE_PROTECTION_MODE) + VCS_update(padapter, psta); + +/* + if (sta_info_type & STA_INFO_UPDATE_CAP) { + + } + + if (sta_info_type & STA_INFO_UPDATE_HT_CAP) { + + } + + if (sta_info_type & STA_INFO_UPDATE_VHT_CAP) { + + } +*/ + +} + +static void update_bcn_ext_capab_ie(_adapter *padapter) +{ + sint ie_len = 0; + unsigned char *pbuf; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network); + u8 *ie = pnetwork->IEs; + u8 null_extcap_data[8] = {0}; + + pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EXT_CAP_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); + if (pbuf && ie_len > 0) + rtw_remove_bcn_ie(padapter, pnetwork, _EXT_CAP_IE_); + + if ((pmlmepriv->ext_capab_ie_len > 0) && + (_rtw_memcmp(pmlmepriv->ext_capab_ie_data, null_extcap_data, sizeof(null_extcap_data)) == _FALSE)) + rtw_add_bcn_ie(padapter, pnetwork, _EXT_CAP_IE_, pmlmepriv->ext_capab_ie_data, pmlmepriv->ext_capab_ie_len); + +} + +static void update_bcn_fixed_ie(_adapter *padapter) +{ + DBG_871X("%s\n", __FUNCTION__); + +} + +static void update_bcn_erpinfo_ie(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network); + unsigned char *p, *ie = pnetwork->IEs; + u32 len = 0; + + DBG_871X("%s, ERP_enable=%d\n", __FUNCTION__, pmlmeinfo->ERP_enable); + + if(!pmlmeinfo->ERP_enable) + return; + + //parsing ERP_IE + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _ERPINFO_IE_, &len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); + if(p && len>0) + { + PNDIS_802_11_VARIABLE_IEs pIE = (PNDIS_802_11_VARIABLE_IEs)p; + + if (pmlmepriv->num_sta_non_erp == 1) + pIE->data[0] |= RTW_ERP_INFO_NON_ERP_PRESENT|RTW_ERP_INFO_USE_PROTECTION; + else + pIE->data[0] &= ~(RTW_ERP_INFO_NON_ERP_PRESENT|RTW_ERP_INFO_USE_PROTECTION); + + if(pmlmepriv->num_sta_no_short_preamble > 0) + pIE->data[0] |= RTW_ERP_INFO_BARKER_PREAMBLE_MODE; + else + pIE->data[0] &= ~(RTW_ERP_INFO_BARKER_PREAMBLE_MODE); + + ERP_IE_handler(padapter, pIE); + } + +} + +static void update_bcn_htcap_ie(_adapter *padapter) +{ + DBG_871X("%s\n", __FUNCTION__); + +} + +static void update_bcn_htinfo_ie(_adapter *padapter) +{ + /* + u8 beacon_updated = _FALSE; + u32 sta_info_update_type = STA_INFO_UPDATE_NONE; + */ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network); + unsigned char *p, *ie = pnetwork->IEs; + u32 len = 0; + + if (pmlmepriv->htpriv.ht_option == _FALSE) + return; + + if (pmlmeinfo->HT_info_enable != 1) + return; + + + DBG_871X("%s current operation mode=0x%X\n", + __FUNCTION__, pmlmepriv->ht_op_mode); + + DBG_871X("num_sta_40mhz_intolerant(%d), 20mhz_width_req(%d), intolerant_ch_rpt(%d), olbc(%d)\n", + pmlmepriv->num_sta_40mhz_intolerant, pmlmepriv->ht_20mhz_width_req, pmlmepriv->ht_intolerant_ch_reported, pmlmepriv->olbc); + + /*parsing HT_INFO_IE, currently only update ht_op_mode - pht_info->infos[1] & pht_info->infos[2] for wifi logo test*/ + p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); + if (p && len > 0) { + struct HT_info_element *pht_info = NULL; + + pht_info = (struct HT_info_element *)(p + 2); + + /* for STA Channel Width/Secondary Channel Offset*/ + if ((pmlmepriv->sw_to_20mhz == 0) && (pmlmeext->cur_channel <= 14)) { + if ((pmlmepriv->num_sta_40mhz_intolerant > 0) || (pmlmepriv->ht_20mhz_width_req == _TRUE) + || (pmlmepriv->ht_intolerant_ch_reported == _TRUE) || (pmlmepriv->olbc == _TRUE)) { + SET_HT_OP_ELE_2ND_CHL_OFFSET(pht_info, 0); + SET_HT_OP_ELE_STA_CHL_WIDTH(pht_info, 0); + + pmlmepriv->sw_to_20mhz = 1; + /* + sta_info_update_type |= STA_INFO_UPDATE_BW; + beacon_updated = _TRUE; + */ + + DBG_871X("%s:switching to 20Mhz\n", __FUNCTION__); + + /*TODO : cur_bwmode/cur_ch_offset switches to 20Mhz*/ + } + } else { + + if ((pmlmepriv->num_sta_40mhz_intolerant == 0) && (pmlmepriv->ht_20mhz_width_req == _FALSE) + && (pmlmepriv->ht_intolerant_ch_reported == _FALSE) && (pmlmepriv->olbc == _FALSE)) { + + if (pmlmeext->cur_bwmode >= CHANNEL_WIDTH_40) { + + SET_HT_OP_ELE_STA_CHL_WIDTH(pht_info, 1); + + SET_HT_OP_ELE_2ND_CHL_OFFSET(pht_info, + (pmlmeext->cur_ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER) ? + HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE : HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW); + + pmlmepriv->sw_to_20mhz = 0; + /* + sta_info_update_type |= STA_INFO_UPDATE_BW; + beacon_updated = _TRUE; + */ + + DBG_871X("%s:switching back to 40Mhz\n", __FUNCTION__); + } + } + } + + /* to update ht_op_mode*/ + *(u16 *)(pht_info->infos + 1) = cpu_to_le16(pmlmepriv->ht_op_mode); + + } + + /*associated_clients_update(padapter, beacon_updated, sta_info_update_type);*/ + +} + +static void update_bcn_rsn_ie(_adapter *padapter) +{ + DBG_871X("%s\n", __FUNCTION__); + +} + +static void update_bcn_wpa_ie(_adapter *padapter) +{ + DBG_871X("%s\n", __FUNCTION__); + +} + +static void update_bcn_wmm_ie(_adapter *padapter) +{ + DBG_871X("%s\n", __FUNCTION__); + +} + +static void update_bcn_wps_ie(_adapter *padapter) +{ + u8 *pwps_ie=NULL, *pwps_ie_src, *premainder_ie, *pbackup_remainder_ie=NULL; + uint wps_ielen=0, wps_offset, remainder_ielen; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network); + unsigned char *ie = pnetwork->IEs; + u32 ielen = pnetwork->IELength; + + + DBG_871X("%s\n", __FUNCTION__); + + pwps_ie = rtw_get_wps_ie(ie+_FIXED_IE_LENGTH_, ielen-_FIXED_IE_LENGTH_, NULL, &wps_ielen); + + if(pwps_ie==NULL || wps_ielen==0) + return; + + pwps_ie_src = pmlmepriv->wps_beacon_ie; + if(pwps_ie_src == NULL) + return; + + wps_offset = (uint)(pwps_ie-ie); + + premainder_ie = pwps_ie + wps_ielen; + + remainder_ielen = ielen - wps_offset - wps_ielen; + + if(remainder_ielen>0) + { + pbackup_remainder_ie = rtw_malloc(remainder_ielen); + if(pbackup_remainder_ie) + _rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen); + } + + wps_ielen = (uint)pwps_ie_src[1];//to get ie data len + if((wps_offset+wps_ielen+2+remainder_ielen)<=MAX_IE_SZ) + { + _rtw_memcpy(pwps_ie, pwps_ie_src, wps_ielen+2); + pwps_ie += (wps_ielen+2); + + if(pbackup_remainder_ie) + _rtw_memcpy(pwps_ie, pbackup_remainder_ie, remainder_ielen); + + //update IELength + pnetwork->IELength = wps_offset + (wps_ielen+2) + remainder_ielen; + } + + if(pbackup_remainder_ie) + rtw_mfree(pbackup_remainder_ie, remainder_ielen); + + // deal with the case without set_tx_beacon_cmd() in update_beacon() +#if defined( CONFIG_INTERRUPT_BASED_TXBCN ) || defined( CONFIG_PCI_HCI ) + if( (pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) + { + u8 sr = 0; + rtw_get_wps_attr_content(pwps_ie_src, wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8*)(&sr), NULL); + + if( sr ) { + set_fwstate(pmlmepriv, WIFI_UNDER_WPS); + DBG_871X("%s, set WIFI_UNDER_WPS\n", __func__); + } + } +#endif +} + +static void update_bcn_p2p_ie(_adapter *padapter) +{ + +} + +static void update_bcn_vendor_spec_ie(_adapter *padapter, u8*oui) +{ + DBG_871X("%s\n", __FUNCTION__); + + if(_rtw_memcmp(RTW_WPA_OUI, oui, 4)) + { + update_bcn_wpa_ie(padapter); + } + else if(_rtw_memcmp(WMM_OUI, oui, 4)) + { + update_bcn_wmm_ie(padapter); + } + else if(_rtw_memcmp(WPS_OUI, oui, 4)) + { + update_bcn_wps_ie(padapter); + } + else if(_rtw_memcmp(P2P_OUI, oui, 4)) + { + update_bcn_p2p_ie(padapter); + } + else + { + DBG_871X("unknown OUI type!\n"); + } + + +} + +void _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, const char *tag) +{ + _irqL irqL; + struct mlme_priv *pmlmepriv; + struct mlme_ext_priv *pmlmeext; + //struct mlme_ext_info *pmlmeinfo; + + //DBG_871X("%s\n", __FUNCTION__); + + if(!padapter) + return; + + pmlmepriv = &(padapter->mlmepriv); + pmlmeext = &(padapter->mlmeextpriv); + //pmlmeinfo = &(pmlmeext->mlmext_info); + + if(_FALSE == pmlmeext->bstart_bss) + return; + + _enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL); + + switch(ie_id) + { + case 0xFF: + + update_bcn_fixed_ie(padapter);//8: TimeStamp, 2: Beacon Interval 2:Capability + + break; + + case _TIM_IE_: + + update_BCNTIM(padapter); + + break; + + case _ERPINFO_IE_: + + update_bcn_erpinfo_ie(padapter); + + break; + + case _HT_CAPABILITY_IE_: + + update_bcn_htcap_ie(padapter); + + break; + + case _RSN_IE_2_: + + update_bcn_rsn_ie(padapter); + + break; + + case _HT_ADD_INFO_IE_: + + update_bcn_htinfo_ie(padapter); + + break; + + case _EXT_CAP_IE_: + + update_bcn_ext_capab_ie(padapter); + + break; + + case _VENDOR_SPECIFIC_IE_: + + update_bcn_vendor_spec_ie(padapter, oui); + + break; + + default: + break; + } + + pmlmepriv->update_bcn = _TRUE; + + _exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL); + +#ifndef CONFIG_INTERRUPT_BASED_TXBCN +#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + if(tx) + { + //send_beacon(padapter);//send_beacon must execute on TSR level + if (0) + DBG_871X(FUNC_ADPT_FMT" ie_id:%u - %s\n", FUNC_ADPT_ARG(padapter), ie_id, tag); + set_tx_beacon_cmd(padapter); + } +#else + { + //PCI will issue beacon when BCN interrupt occurs. + } +#endif +#endif //!CONFIG_INTERRUPT_BASED_TXBCN + +} + +#ifdef CONFIG_80211N_HT + +void rtw_process_public_act_bsscoex(_adapter *padapter, u8 *pframe, uint frame_len) +{ + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 beacon_updated = _FALSE; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + uint frame_body_len = frame_len - sizeof(struct rtw_ieee80211_hdr_3addr); + u8 category, action; + + psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe)); + if (psta == NULL) + return; + + + category = frame_body[0]; + action = frame_body[1]; + + if (frame_body_len > 0) { + if ((frame_body[2] == EID_BSSCoexistence) && (frame_body[3] > 0)) { + u8 ie_data = frame_body[4]; + + if (ie_data & RTW_WLAN_20_40_BSS_COEX_40MHZ_INTOL) { + if (psta->ht_40mhz_intolerant == 0) { + psta->ht_40mhz_intolerant = 1; + pmlmepriv->num_sta_40mhz_intolerant++; + beacon_updated = _TRUE; + } + } else if (ie_data & RTW_WLAN_20_40_BSS_COEX_20MHZ_WIDTH_REQ) { + if (pmlmepriv->ht_20mhz_width_req == _FALSE) { + pmlmepriv->ht_20mhz_width_req = _TRUE; + beacon_updated = _TRUE; + } + } else + beacon_updated = _FALSE; + } + } + + if (frame_body_len > 8) { + /* if EID_BSSIntolerantChlReport ie exists */ + if ((frame_body[5] == EID_BSSIntolerantChlReport) && (frame_body[6] > 0)) { + /*todo:*/ + if (pmlmepriv->ht_intolerant_ch_reported == _FALSE) { + pmlmepriv->ht_intolerant_ch_reported = _TRUE; + beacon_updated = _TRUE; + } + } + } + + if (beacon_updated) { + + update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE); + + associated_stainfo_update(padapter, psta, STA_INFO_UPDATE_BW); + } + + + +} + +void rtw_process_ht_action_smps(_adapter *padapter, u8 *ta, u8 ctrl_field) +{ + u8 e_field, m_field; + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; + + psta = rtw_get_stainfo(pstapriv, ta); + if (psta == NULL) + return; + + e_field = (ctrl_field & BIT(0)) ? 1 : 0; + m_field = (ctrl_field & BIT(1)) ? 1 : 0; + + if (e_field) { + + /* enable */ + /* 0:static SMPS, 1:dynamic SMPS, 3:SMPS disabled, 2:reserved*/ + + if (m_field) /*mode*/ + psta->htpriv.smps_cap = 1; + else + psta->htpriv.smps_cap = 0; + } else { + /*disable*/ + psta->htpriv.smps_cap = 3; + } + + rtw_dm_ra_mask_wk_cmd(padapter, (u8 *)psta); + +} + +/* +op_mode +Set to 0 (HT pure) under the followign conditions + - all STAs in the BSS are 20/40 MHz HT in 20/40 MHz BSS or + - all STAs in the BSS are 20 MHz HT in 20 MHz BSS +Set to 1 (HT non-member protection) if there may be non-HT STAs + in both the primary and the secondary channel +Set to 2 if only HT STAs are associated in BSS, + however and at least one 20 MHz HT STA is associated +Set to 3 (HT mixed mode) when one or more non-HT STAs are associated + (currently non-GF HT station is considered as non-HT STA also) +*/ +static int rtw_ht_operation_update(_adapter *padapter) +{ + u16 cur_op_mode, new_op_mode; + int op_mode_changes = 0; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct ht_priv *phtpriv_ap = &pmlmepriv->htpriv; + + if (pmlmepriv->htpriv.ht_option == _FALSE) + return 0; + + /*if (!iface->conf->ieee80211n || iface->conf->ht_op_mode_fixed) + return 0;*/ + + DBG_871X("%s current operation mode=0x%X\n", + __FUNCTION__, pmlmepriv->ht_op_mode); + + if (!(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT) + && pmlmepriv->num_sta_ht_no_gf) { + pmlmepriv->ht_op_mode |= + HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT; + op_mode_changes++; + } else if ((pmlmepriv->ht_op_mode & + HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT) && + pmlmepriv->num_sta_ht_no_gf == 0) { + pmlmepriv->ht_op_mode &= + ~HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT; + op_mode_changes++; + } + + if (!(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT) && + (pmlmepriv->num_sta_no_ht || pmlmepriv->olbc_ht)) { + pmlmepriv->ht_op_mode |= HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT; + op_mode_changes++; + } else if ((pmlmepriv->ht_op_mode & + HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT) && + (pmlmepriv->num_sta_no_ht == 0 && !pmlmepriv->olbc_ht)) { + pmlmepriv->ht_op_mode &= + ~HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT; + op_mode_changes++; + } + + /* Note: currently we switch to the MIXED op mode if HT non-greenfield + * station is associated. Probably it's a theoretical case, since + * it looks like all known HT STAs support greenfield. + */ + new_op_mode = 0; + if (pmlmepriv->num_sta_no_ht /*|| + (pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT)*/) + new_op_mode = OP_MODE_MIXED; + else if ((phtpriv_ap->ht_cap.cap_info & IEEE80211_HT_CAP_SUP_WIDTH) + && pmlmepriv->num_sta_ht_20mhz) + new_op_mode = OP_MODE_20MHZ_HT_STA_ASSOCED; + else if (pmlmepriv->olbc_ht) + new_op_mode = OP_MODE_MAY_BE_LEGACY_STAS; + else + new_op_mode = OP_MODE_PURE; + + cur_op_mode = pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_OP_MODE_MASK; + if (cur_op_mode != new_op_mode) { + pmlmepriv->ht_op_mode &= ~HT_INFO_OPERATION_MODE_OP_MODE_MASK; + pmlmepriv->ht_op_mode |= new_op_mode; + op_mode_changes++; + } + + DBG_871X("%s new operation mode=0x%X changes=%d\n", + __FUNCTION__, pmlmepriv->ht_op_mode, op_mode_changes); + + return op_mode_changes; + +} + +#endif /* CONFIG_80211N_HT */ + +void associated_clients_update(_adapter *padapter, u8 updated, u32 sta_info_type) +{ + //update associcated stations cap. + if(updated == _TRUE) + { + _irqL irqL; + _list *phead, *plist; + struct sta_info *psta=NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + phead = &pstapriv->asoc_list; + plist = get_next(phead); + + //check asoc_queue + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) + { + psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + + plist = get_next(plist); + + associated_stainfo_update(padapter, psta, sta_info_type); + } + + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + } + +} + +/* called > TSR LEVEL for USB or SDIO Interface*/ +void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta) +{ + u8 beacon_updated = _FALSE; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + + +#if 0 + if (!(psta->capability & WLAN_CAPABILITY_SHORT_PREAMBLE) && + !psta->no_short_preamble_set) { + psta->no_short_preamble_set = 1; + pmlmepriv->num_sta_no_short_preamble++; + if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && + (pmlmepriv->num_sta_no_short_preamble == 1)) + ieee802_11_set_beacons(hapd->iface); + } +#endif + + + if(!(psta->flags & WLAN_STA_SHORT_PREAMBLE)) + { + if(!psta->no_short_preamble_set) + { + psta->no_short_preamble_set = 1; + + pmlmepriv->num_sta_no_short_preamble++; + + if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && + (pmlmepriv->num_sta_no_short_preamble == 1)) + { + beacon_updated = _TRUE; + update_beacon(padapter, 0xFF, NULL, _TRUE); + } + + } + } + else + { + if(psta->no_short_preamble_set) + { + psta->no_short_preamble_set = 0; + + pmlmepriv->num_sta_no_short_preamble--; + + if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && + (pmlmepriv->num_sta_no_short_preamble == 0)) + { + beacon_updated = _TRUE; + update_beacon(padapter, 0xFF, NULL, _TRUE); + } + + } + } + +#if 0 + if (psta->flags & WLAN_STA_NONERP && !psta->nonerp_set) { + psta->nonerp_set = 1; + pmlmepriv->num_sta_non_erp++; + if (pmlmepriv->num_sta_non_erp == 1) + ieee802_11_set_beacons(hapd->iface); + } +#endif + + if(psta->flags & WLAN_STA_NONERP) + { + if(!psta->nonerp_set) + { + psta->nonerp_set = 1; + + pmlmepriv->num_sta_non_erp++; + + if (pmlmepriv->num_sta_non_erp == 1) + { + beacon_updated = _TRUE; + update_beacon(padapter, _ERPINFO_IE_, NULL, _TRUE); + } + } + + } + else + { + if(psta->nonerp_set) + { + psta->nonerp_set = 0; + + pmlmepriv->num_sta_non_erp--; + + if (pmlmepriv->num_sta_non_erp == 0) + { + beacon_updated = _TRUE; + update_beacon(padapter, _ERPINFO_IE_, NULL, _TRUE); + } + } + + } + + +#if 0 + if (!(psta->capability & WLAN_CAPABILITY_SHORT_SLOT) && + !psta->no_short_slot_time_set) { + psta->no_short_slot_time_set = 1; + pmlmepriv->num_sta_no_short_slot_time++; + if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && + (pmlmepriv->num_sta_no_short_slot_time == 1)) + ieee802_11_set_beacons(hapd->iface); + } +#endif + + if(!(psta->capability & WLAN_CAPABILITY_SHORT_SLOT)) + { + if(!psta->no_short_slot_time_set) + { + psta->no_short_slot_time_set = 1; + + pmlmepriv->num_sta_no_short_slot_time++; + + if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && + (pmlmepriv->num_sta_no_short_slot_time == 1)) + { + beacon_updated = _TRUE; + update_beacon(padapter, 0xFF, NULL, _TRUE); + } + + } + } + else + { + if(psta->no_short_slot_time_set) + { + psta->no_short_slot_time_set = 0; + + pmlmepriv->num_sta_no_short_slot_time--; + + if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && + (pmlmepriv->num_sta_no_short_slot_time == 0)) + { + beacon_updated = _TRUE; + update_beacon(padapter, 0xFF, NULL, _TRUE); + } + } + } + +#ifdef CONFIG_80211N_HT + + if (psta->flags & WLAN_STA_HT) + { + u16 ht_capab = le16_to_cpu(psta->htpriv.ht_cap.cap_info); + + DBG_871X("HT: STA " MAC_FMT " HT Capabilities " + "Info: 0x%04x\n", MAC_ARG(psta->hwaddr), ht_capab); + + if (psta->no_ht_set) { + psta->no_ht_set = 0; + pmlmepriv->num_sta_no_ht--; + } + + if ((ht_capab & IEEE80211_HT_CAP_GRN_FLD) == 0) { + if (!psta->no_ht_gf_set) { + psta->no_ht_gf_set = 1; + pmlmepriv->num_sta_ht_no_gf++; + } + DBG_871X("%s STA " MAC_FMT " - no " + "greenfield, num of non-gf stations %d\n", + __FUNCTION__, MAC_ARG(psta->hwaddr), + pmlmepriv->num_sta_ht_no_gf); + } + + if ((ht_capab & IEEE80211_HT_CAP_SUP_WIDTH) == 0) { + if (!psta->ht_20mhz_set) { + psta->ht_20mhz_set = 1; + pmlmepriv->num_sta_ht_20mhz++; + } + DBG_871X("%s STA " MAC_FMT " - 20 MHz HT, " + "num of 20MHz HT STAs %d\n", + __FUNCTION__, MAC_ARG(psta->hwaddr), + pmlmepriv->num_sta_ht_20mhz); + } + + + } else { + if (!psta->no_ht_set) { + psta->no_ht_set = 1; + pmlmepriv->num_sta_no_ht++; + } + if(pmlmepriv->htpriv.ht_option == _TRUE) { + DBG_871X("%s STA " MAC_FMT + " - no HT, num of non-HT stations %d\n", + __FUNCTION__, MAC_ARG(psta->hwaddr), + pmlmepriv->num_sta_no_ht); + } + } + + if (rtw_ht_operation_update(padapter) > 0) { + update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE); + update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE); + /*beacon_updated = _TRUE;*/ + } + +#endif /* CONFIG_80211N_HT */ + + //update associcated stations cap. + associated_clients_update(padapter, beacon_updated, STA_INFO_UPDATE_ALL); + + DBG_871X("%s, updated=%d\n", __func__, beacon_updated); + +} + +u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta) +{ + u8 beacon_updated = _FALSE; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + + if(!psta) + return beacon_updated; + + if (psta->no_short_preamble_set) { + psta->no_short_preamble_set = 0; + pmlmepriv->num_sta_no_short_preamble--; + if (pmlmeext->cur_wireless_mode > WIRELESS_11B + && pmlmepriv->num_sta_no_short_preamble == 0) + { + beacon_updated = _TRUE; + update_beacon(padapter, 0xFF, NULL, _TRUE); + } + } + + if (psta->nonerp_set) { + psta->nonerp_set = 0; + pmlmepriv->num_sta_non_erp--; + if (pmlmepriv->num_sta_non_erp == 0) + { + beacon_updated = _TRUE; + update_beacon(padapter, _ERPINFO_IE_, NULL, _TRUE); + } + } + + if (psta->no_short_slot_time_set) { + psta->no_short_slot_time_set = 0; + pmlmepriv->num_sta_no_short_slot_time--; + if (pmlmeext->cur_wireless_mode > WIRELESS_11B + && pmlmepriv->num_sta_no_short_slot_time == 0) + { + beacon_updated = _TRUE; + update_beacon(padapter, 0xFF, NULL, _TRUE); + } + } + +#ifdef CONFIG_80211N_HT + + if (psta->no_ht_gf_set) { + psta->no_ht_gf_set = 0; + pmlmepriv->num_sta_ht_no_gf--; + } + + if (psta->no_ht_set) { + psta->no_ht_set = 0; + pmlmepriv->num_sta_no_ht--; + } + + if (psta->ht_20mhz_set) { + psta->ht_20mhz_set = 0; + pmlmepriv->num_sta_ht_20mhz--; + } + + + + if (rtw_ht_operation_update(padapter) > 0) { + update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE); + update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE); + } + +#endif /* CONFIG_80211N_HT */ + + /* update associated stations cap. + associated_clients_update(padapter, beacon_updated, STA_INFO_UPDATE_ALL); //move it to avoid deadlock + */ + + DBG_871X("%s, updated=%d\n", __func__, beacon_updated); + + return beacon_updated; + +} + +u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reason, bool enqueue) +{ + _irqL irqL; + u8 beacon_updated = _FALSE; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct sta_priv *pstapriv = &padapter->stapriv; + + if(!psta) + return beacon_updated; + + if (active == _TRUE) + { +#ifdef CONFIG_80211N_HT + //tear down Rx AMPDU + send_delba(padapter, 0, psta->hwaddr);// recipient + + //tear down TX AMPDU + send_delba(padapter, 1, psta->hwaddr);// // originator + +#endif //CONFIG_80211N_HT + + issue_deauth(padapter, psta->hwaddr, reason); + } + +#ifdef CONFIG_BEAMFORMING + beamforming_wk_cmd(padapter, BEAMFORMING_CTRL_LEAVE, psta->hwaddr, ETH_ALEN, 1); +#endif + + psta->htpriv.agg_enable_bitmap = 0x0;//reset + psta->htpriv.candidate_tid_bitmap = 0x0;//reset + + //clear cam entry / key + rtw_clearstakey_cmd(padapter, psta, enqueue); + + + _enter_critical_bh(&psta->lock, &irqL); + psta->state &= ~_FW_LINKED; + _exit_critical_bh(&psta->lock, &irqL); + + #ifdef CONFIG_IOCTL_CFG80211 + if (1) { + #ifdef COMPAT_KERNEL_RELEASE + rtw_cfg80211_indicate_sta_disassoc(padapter, psta->hwaddr, reason); + #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) + rtw_cfg80211_indicate_sta_disassoc(padapter, psta->hwaddr, reason); + #else //(LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) + /* will call rtw_cfg80211_indicate_sta_disassoc() in cmd_thread for old API context */ + #endif //(LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) + } else + #endif //CONFIG_IOCTL_CFG80211 + { + rtw_indicate_sta_disassoc_event(padapter, psta); + } + + report_del_sta_event(padapter, psta->hwaddr, reason, enqueue, _FALSE); + + beacon_updated = bss_cap_update_on_sta_leave(padapter, psta); + + //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + rtw_free_stainfo(padapter, psta); + //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + + + return beacon_updated; + +} + +int rtw_ap_inform_ch_switch(_adapter *padapter, u8 new_ch, u8 ch_offset) +{ + _irqL irqL; + _list *phead, *plist; + int ret=0; + struct sta_info *psta = NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff}; + + if((pmlmeinfo->state&0x03) != WIFI_FW_AP_STATE) + return ret; + + DBG_871X(FUNC_NDEV_FMT" with ch:%u, offset:%u\n", + FUNC_NDEV_ARG(padapter->pnetdev), new_ch, ch_offset); + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + phead = &pstapriv->asoc_list; + plist = get_next(phead); + + /* for each sta in asoc_queue */ + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) + { + psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + plist = get_next(plist); + + issue_action_spct_ch_switch(padapter, psta->hwaddr, new_ch, ch_offset); + psta->expire_to = ((pstapriv->expire_to * 2) > 5) ? 5 : (pstapriv->expire_to * 2); + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + issue_action_spct_ch_switch(padapter, bc_addr, new_ch, ch_offset); + + return ret; +} + +int rtw_sta_flush(_adapter *padapter, bool enqueue) +{ + _irqL irqL; + _list *phead, *plist; + int ret = 0; + struct sta_info *psta = NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff}; + u8 flush_num = 0; + char flush_list[NUM_STA]; + int i; + + if ((pmlmeinfo->state&0x03) != WIFI_FW_AP_STATE) + return ret; + + DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(padapter->pnetdev)); + + /* pick sta from sta asoc_queue */ + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + phead = &pstapriv->asoc_list; + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + int stainfo_offset; + + psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + plist = get_next(plist); + + rtw_list_delete(&psta->asoc_list); + pstapriv->asoc_list_cnt--; + + stainfo_offset = rtw_stainfo_offset(pstapriv, psta); + if (stainfo_offset_valid(stainfo_offset)) + flush_list[flush_num++] = stainfo_offset; + else + rtw_warn_on(1); + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + /* call ap_free_sta() for each sta picked */ + for (i = 0; i < flush_num; i++) { + psta = rtw_get_stainfo_by_offset(pstapriv, flush_list[i]); + ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, enqueue); + } + + issue_deauth(padapter, bc_addr, WLAN_REASON_DEAUTH_LEAVING); + + associated_clients_update(padapter, _TRUE, STA_INFO_UPDATE_ALL); + + return ret; +} + +/* called > TSR LEVEL for USB or SDIO Interface*/ +void sta_info_update(_adapter *padapter, struct sta_info *psta) +{ + int flags = psta->flags; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + + //update wmm cap. + if(WLAN_STA_WME&flags) + psta->qos_option = 1; + else + psta->qos_option = 0; + + if(pmlmepriv->qospriv.qos_option == 0) + psta->qos_option = 0; + + +#ifdef CONFIG_80211N_HT + //update 802.11n ht cap. + if(WLAN_STA_HT&flags) + { + psta->htpriv.ht_option = _TRUE; + psta->qos_option = 1; + + psta->htpriv.smps_cap = (psta->htpriv.ht_cap.cap_info & IEEE80211_HT_CAP_SM_PS)>>2; + } + else + { + psta->htpriv.ht_option = _FALSE; + } + + if(pmlmepriv->htpriv.ht_option == _FALSE) + psta->htpriv.ht_option = _FALSE; +#endif + +#ifdef CONFIG_80211AC_VHT + //update 802.11AC vht cap. + if(WLAN_STA_VHT&flags) + { + psta->vhtpriv.vht_option = _TRUE; + } + else + { + psta->vhtpriv.vht_option = _FALSE; + } + + if(pmlmepriv->vhtpriv.vht_option == _FALSE) + psta->vhtpriv.vht_option = _FALSE; +#endif + + + update_sta_info_apmode(padapter, psta); + + +} + +/* called >= TSR LEVEL for USB or SDIO Interface*/ +void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta) +{ + if (psta->state & _FW_LINKED) { + //add ratid + add_RATid(padapter, psta, 0);//DM_RATR_STA_INIT + } +} +/* restore hw setting from sw data structures */ +void rtw_ap_restore_network(_adapter *padapter) +{ + struct mlme_priv *mlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct sta_priv * pstapriv = &padapter->stapriv; + struct sta_info *psta; + struct security_priv* psecuritypriv=&(padapter->securitypriv); + _irqL irqL; + _list *phead, *plist; + u8 chk_alive_num = 0; + char chk_alive_list[NUM_STA]; + int i; + + rtw_setopmode_cmd(padapter, Ndis802_11APMode,_FALSE); + + set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); + + rtw_startbss_cmd(padapter, RTW_CMDF_DIRECTLY); + + if((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) || + (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) + { + /* restore group key, WEP keys is restored in ips_leave() */ + rtw_set_key(padapter, psecuritypriv, psecuritypriv->dot118021XGrpKeyid, 0,_FALSE); + } + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + phead = &pstapriv->asoc_list; + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + int stainfo_offset; + + psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + plist = get_next(plist); + + stainfo_offset = rtw_stainfo_offset(pstapriv, psta); + if (stainfo_offset_valid(stainfo_offset)) { + chk_alive_list[chk_alive_num++] = stainfo_offset; + } + } + + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + for (i = 0; i < chk_alive_num; i++) { + psta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]); + + if (psta == NULL) { + DBG_871X(FUNC_ADPT_FMT" sta_info is null\n", FUNC_ADPT_ARG(padapter)); + } else if (psta->state &_FW_LINKED) { + rtw_sta_media_status_rpt(padapter, psta, 1); + Update_RA_Entry(padapter, psta); + //pairwise key + /* per sta pairwise key and settings */ + if( (padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) || + (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) + { + rtw_setstakey_cmd(padapter, psta, UNICAST_KEY,_FALSE); + } + } + } + +} + +void start_ap_mode(_adapter *padapter) +{ + int i; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sta_priv *pstapriv = &padapter->stapriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct wlan_acl_pool *pacl_list = &pstapriv->acl_list; + + pmlmepriv->update_bcn = _FALSE; + + /*init_mlme_ap_info(padapter);*/ + + pmlmeext->bstart_bss = _FALSE; + + pmlmepriv->num_sta_non_erp = 0; + + pmlmepriv->num_sta_no_short_slot_time = 0; + + pmlmepriv->num_sta_no_short_preamble = 0; + + pmlmepriv->num_sta_ht_no_gf = 0; +#ifdef CONFIG_80211N_HT + pmlmepriv->num_sta_no_ht = 0; +#endif //CONFIG_80211N_HT + pmlmeinfo->HT_info_enable = 0; + pmlmeinfo->HT_caps_enable = 0; + pmlmeinfo->HT_enable = 0; + + pmlmepriv->num_sta_ht_20mhz = 0; + pmlmepriv->num_sta_40mhz_intolerant = 0; + pmlmepriv->olbc = _FALSE; + pmlmepriv->olbc_ht = _FALSE; + +#ifdef CONFIG_80211N_HT + pmlmepriv->ht_20mhz_width_req = _FALSE; + pmlmepriv->ht_intolerant_ch_reported = _FALSE; + pmlmepriv->ht_op_mode = 0; + pmlmepriv->sw_to_20mhz = 0; +#endif + + _rtw_memset(pmlmepriv->ext_capab_ie_data, 0, sizeof(pmlmepriv->ext_capab_ie_data)); + pmlmepriv->ext_capab_ie_len = 0; + + for (i = 0 ; i < NUM_STA ; i++) + pstapriv->sta_aid[i] = NULL; + + //for ACL + _rtw_init_listhead(&(pacl_list->acl_node_q.queue)); + pacl_list->num = 0; + pacl_list->mode = 0; + for(i = 0; i < NUM_ACL; i++) + { + _rtw_init_listhead(&pacl_list->aclnode[i].list); + pacl_list->aclnode[i].valid = _FALSE; + } + +} + +void stop_ap_mode(_adapter *padapter) +{ + _irqL irqL; + _list *phead, *plist; + struct rtw_wlan_acl_node *paclnode; + struct sta_info *psta=NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct wlan_acl_pool *pacl_list = &pstapriv->acl_list; + _queue *pacl_node_q =&pacl_list->acl_node_q; + + pmlmepriv->update_bcn = _FALSE; + pmlmeext->bstart_bss = _FALSE; + padapter->netif_up = _FALSE; + //_rtw_spinlock_free(&pmlmepriv->bcn_update_lock); + + //reset and init security priv , this can refine with rtw_reset_securitypriv + _rtw_memset((unsigned char *)&padapter->securitypriv, 0, sizeof (struct security_priv)); + padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen; + padapter->securitypriv.ndisencryptstatus = Ndis802_11WEPDisabled; + + #ifdef CONFIG_DFS_MASTER + rtw_dfs_master_status_apply(padapter, MLME_AP_STOPPED); + #endif + + /* free scan queue */ + rtw_free_network_queue(padapter, _TRUE); + + //for ACL + _enter_critical_bh(&(pacl_node_q->lock), &irqL); + phead = get_list_head(pacl_node_q); + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) + { + paclnode = LIST_CONTAINOR(plist, struct rtw_wlan_acl_node, list); + plist = get_next(plist); + + if(paclnode->valid == _TRUE) + { + paclnode->valid = _FALSE; + + rtw_list_delete(&paclnode->list); + + pacl_list->num--; + } + } + _exit_critical_bh(&(pacl_node_q->lock), &irqL); + + DBG_871X("%s, free acl_node_queue, num=%d\n", __func__, pacl_list->num); + + rtw_sta_flush(padapter, _TRUE); + + //free_assoc_sta_resources + rtw_free_all_stainfo(padapter); + + psta = rtw_get_bcmc_stainfo(padapter); + //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + rtw_free_stainfo(padapter, psta); + //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + + rtw_init_bcmc_stainfo(padapter); + + rtw_free_mlme_priv_ie_data(pmlmepriv); + +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_MediaStatusNotify(padapter, 0); //disconnect +#endif + +} + +#endif //CONFIG_NATIVEAP_MLME + +void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, u8 offset) +{ +#define UPDATE_VHT_CAP 1 +#define UPDATE_HT_CAP 1 + +#ifdef CONFIG_80211AC_VHT + { + struct vht_priv *vhtpriv = &adapter->mlmepriv.vhtpriv; + u8 *vht_cap_ie, *vht_op_ie; + int vht_cap_ielen, vht_op_ielen; + u8 center_freq; + + vht_cap_ie = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), EID_VHTCapability, &vht_cap_ielen, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs))); + vht_op_ie = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), EID_VHTOperation, &vht_op_ielen, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs))); + center_freq = rtw_get_center_ch(ch, bw, offset); + + /* update vht cap ie */ + if (vht_cap_ie && vht_cap_ielen) { + #if UPDATE_VHT_CAP + /* if ((bw == CHANNEL_WIDTH_160 || bw == CHANNEL_WIDTH_80_80) && pvhtpriv->sgi_160m) + SET_VHT_CAPABILITY_ELE_SHORT_GI160M(pvht_cap_ie + 2, 1); + else */ + SET_VHT_CAPABILITY_ELE_SHORT_GI160M(vht_cap_ie + 2, 0); + + if (bw >= CHANNEL_WIDTH_80 && vhtpriv->sgi_80m) + SET_VHT_CAPABILITY_ELE_SHORT_GI80M(vht_cap_ie + 2, 1); + else + SET_VHT_CAPABILITY_ELE_SHORT_GI80M(vht_cap_ie + 2, 0); + #endif + } + + /* update vht op ie */ + if (vht_op_ie && vht_op_ielen) { + if (bw < CHANNEL_WIDTH_80) { + SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2, 0); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op_ie + 2, 0); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op_ie + 2, 0); + } else if (bw == CHANNEL_WIDTH_80) { + SET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2, 1); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(vht_op_ie + 2, center_freq); + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(vht_op_ie + 2, 0); + } else { + DBG_871X_LEVEL(_drv_err_, FUNC_ADPT_FMT" unsupported BW:%u\n", FUNC_ADPT_ARG(adapter), bw); + rtw_warn_on(1); + } + } + } +#endif /* CONFIG_80211AC_VHT */ +#ifdef CONFIG_80211N_HT + { + struct ht_priv *htpriv = &adapter->mlmepriv.htpriv; + u8 *ht_cap_ie, *ht_op_ie; + int ht_cap_ielen, ht_op_ielen; + + ht_cap_ie = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), EID_HTCapability, &ht_cap_ielen, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs))); + ht_op_ie = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), EID_HTInfo, &ht_op_ielen, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs))); + + /* update ht cap ie */ + if (ht_cap_ie && ht_cap_ielen) { + #if UPDATE_HT_CAP + if (bw >= CHANNEL_WIDTH_40) + SET_HT_CAP_ELE_CHL_WIDTH(ht_cap_ie + 2, 1); + else + SET_HT_CAP_ELE_CHL_WIDTH(ht_cap_ie + 2, 0); + + if (bw >= CHANNEL_WIDTH_40 && htpriv->sgi_40m) + SET_HT_CAP_ELE_SHORT_GI40M(ht_cap_ie + 2, 1); + else + SET_HT_CAP_ELE_SHORT_GI40M(ht_cap_ie + 2, 0); + + if (htpriv->sgi_20m) + SET_HT_CAP_ELE_SHORT_GI20M(ht_cap_ie + 2, 1); + else + SET_HT_CAP_ELE_SHORT_GI20M(ht_cap_ie + 2, 0); + #endif + } + + /* update ht op ie */ + if (ht_op_ie && ht_op_ielen) { + SET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2, ch); + switch (offset) { + case HAL_PRIME_CHNL_OFFSET_LOWER: + SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2, SCA); + break; + case HAL_PRIME_CHNL_OFFSET_UPPER: + SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2, SCB); + break; + case HAL_PRIME_CHNL_OFFSET_DONT_CARE: + default: + SET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2, SCN); + break; + } + + if (bw >= CHANNEL_WIDTH_40) + SET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2, 1); + else + SET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2, 0); + } + } +#endif /* CONFIG_80211N_HT */ + +{ + u8 *p; + int ie_len; + u8 old_ch = bss->Configuration.DSConfig; + bool change_band = _FALSE; + + if ((ch <= 14 && old_ch >= 36) || (ch >= 36 && old_ch <= 14)) + change_band = _TRUE; + + /* update channel in IE */ + p = rtw_get_ie((bss->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _DSSET_IE_, &ie_len, (bss->IELength - sizeof(NDIS_802_11_FIXED_IEs))); + if (p && ie_len > 0) + *(p + 2) = ch; + + bss->Configuration.DSConfig = ch; + + /* band is changed, update ERP, support rate, ext support rate IE */ + if (change_band == _TRUE) + change_band_update_ie(adapter, bss, ch); +} + +} + +bool rtw_ap_chbw_decision(_adapter *adapter, u8 req_ch, u8 req_bw, u8 req_offset + , u8 *ch, u8 *bw, u8 *offset) +{ + u8 dec_ch, dec_bw, dec_offset; + u8 u_ch = 0, u_offset, u_bw; + bool changed = _FALSE; + struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv); + u8 sta_num; + u8 ld_sta_num; + u8 lg_sta_num; + u8 ap_num; + u8 ld_ap_num; + bool set_u_ch = _FALSE, set_dec_ch = _FALSE; + + dec_ch = req_ch; + dec_bw = req_bw; + dec_offset = req_offset; + + rtw_dev_iface_status_no_self(adapter, &sta_num, &ld_sta_num, &lg_sta_num, &ap_num, &ld_ap_num); + DBG_871X(FUNC_ADPT_FMT" ld_sta_num:%u, lg_sta_num%u, ap_num:%u\n" + , FUNC_ADPT_ARG(adapter), ld_sta_num, lg_sta_num, ap_num); + + if (ld_sta_num || ap_num) { + /* has linked STA or AP mode, follow */ + + rtw_warn_on(!rtw_get_ch_setting_union_no_self(adapter, &u_ch, &u_bw, &u_offset)); + + DBG_871X(FUNC_ADPT_FMT" union no self: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset); + DBG_871X(FUNC_ADPT_FMT" req: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), req_ch, req_bw, req_offset); + + rtw_adjust_chbw(adapter, u_ch, &dec_bw, &dec_offset); + + rtw_sync_chbw(&dec_ch, &dec_bw, &dec_offset + , &u_ch, &u_bw, &u_offset); + + rtw_ap_update_bss_chbw(adapter, &(adapter->mlmepriv.cur_network.network) + , dec_ch, dec_bw, dec_offset); + + set_u_ch = _TRUE; + } else if (lg_sta_num) { + /* has linking STA */ + + rtw_warn_on(!rtw_get_ch_setting_union_no_self(adapter, &u_ch, &u_bw, &u_offset)); + + DBG_871X(FUNC_ADPT_FMT" union no self: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset); + DBG_871X(FUNC_ADPT_FMT" req: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), req_ch, req_bw, req_offset); + + rtw_adjust_chbw(adapter, dec_ch, &dec_bw, &dec_offset); + + if (rtw_is_chbw_grouped(u_ch, u_bw, u_offset, dec_ch, dec_bw, dec_offset)) { + + rtw_sync_chbw(&dec_ch, &dec_bw, &dec_offset + , &u_ch, &u_bw, &u_offset); + + rtw_ap_update_bss_chbw(adapter, &(adapter->mlmepriv.cur_network.network) + , dec_ch, dec_bw, dec_offset); + + set_u_ch = _TRUE; + } else { + /* set this for possible ch change when join down*/ + set_fwstate(&adapter->mlmepriv, WIFI_OP_CH_SWITCHING); + } + } else { + /* single AP mode */ + + DBG_871X(FUNC_ADPT_FMT" req: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), req_ch, req_bw, req_offset); + rtw_adjust_chbw(adapter, dec_ch, &dec_bw, &dec_offset); + + #if defined(CONFIG_DFS_MASTER) + /* check NOL */ + if (rtw_chset_is_ch_non_ocp(mlmeext->channel_set, dec_ch, dec_bw, dec_offset)) { + /* choose 5G DFS channel for debug */ + if (adapter_to_rfctl(adapter)->dbg_dfs_master_choose_dfs_ch_first + && rtw_choose_available_chbw(adapter, req_bw, &dec_ch, &dec_bw, &dec_offset, RTW_CHF_2G|RTW_CHF_NON_DFS) == _TRUE) { + DBG_871X(FUNC_ADPT_FMT" choose 5G DFS channel for debug\n", FUNC_ADPT_ARG(adapter)); + } else + /* choose from 5G no DFS */ + if (rtw_choose_available_chbw(adapter, req_bw, &dec_ch, &dec_bw, &dec_offset, RTW_CHF_2G|RTW_CHF_DFS) == _FALSE) { + /* including 5G DFS, not long CAC */ + if (rtw_choose_available_chbw(adapter, req_bw, &dec_ch, &dec_bw, &dec_offset, RTW_CHF_2G|RTW_CHF_LONG_CAC) == _FALSE) { + /* including 5G DFS, long CAC */ + if (rtw_choose_available_chbw(adapter, req_bw, &dec_ch, &dec_bw, &dec_offset, RTW_CHF_2G) == _FALSE) { + /* including 2.4G channel */ + if (rtw_choose_available_chbw(adapter, req_bw, &dec_ch, &dec_bw, &dec_offset, RTW_CHF_5G) == _FALSE) { + DBG_871X(FUNC_ADPT_FMT" no available ch\n", FUNC_ADPT_ARG(adapter)); + rtw_warn_on(1); + } + } + } + } + } + #endif /* defined(CONFIG_DFS_MASTER) */ + + rtw_ap_update_bss_chbw(adapter, &(adapter->mlmepriv.cur_network.network) + , dec_ch, dec_bw, dec_offset); + + set_dec_ch = _TRUE; + } + + if (check_fwstate(&adapter->mlmepriv, _FW_UNDER_SURVEY) + #ifdef CONFIG_CONCURRENT_MODE + || check_buddy_fwstate(adapter, _FW_UNDER_SURVEY) + #endif + ) { + /* scanning, leave ch setting to scan state machine */ + set_u_ch = set_dec_ch = _FALSE; + } + + if (mlmeext->cur_channel != dec_ch + || mlmeext->cur_bwmode != dec_bw + || mlmeext->cur_ch_offset != dec_offset) + changed = _TRUE; + + if (changed == _TRUE && rtw_linked_check(adapter) == _TRUE) { + #ifdef CONFIG_SPCT_CH_SWITCH + if (1) + rtw_ap_inform_ch_switch(adapter, dec_ch, dec_offset); + else + #endif + rtw_sta_flush(adapter, _FALSE); + } + + mlmeext->cur_channel = dec_ch; + mlmeext->cur_bwmode = dec_bw; + mlmeext->cur_ch_offset = dec_offset; + + if (u_ch != 0) + DBG_871X(FUNC_ADPT_FMT" union: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset); + + DBG_871X(FUNC_ADPT_FMT" dec: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), dec_ch, dec_bw, dec_offset); + + if (set_u_ch == _TRUE) { + *ch = u_ch; + *bw = u_bw; + *offset = u_offset; + } else if (set_dec_ch == _TRUE) { + *ch = dec_ch; + *bw = dec_bw; + *offset = dec_offset; + } + + return changed; +} + +#endif //CONFIG_AP_MODE + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_beamforming.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_beamforming.c new file mode 100644 index 000000000..854f8ef08 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_beamforming.c @@ -0,0 +1,1244 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_BEAMFORMING_C_ + +#include +#include + +#ifdef CONFIG_BEAMFORMING + +#if (BEAMFORMING_SUPPORT == 0) /*for diver defined beamforming*/ +struct beamforming_entry *beamforming_get_entry_by_addr(struct mlme_priv *pmlmepriv, u8* ra,u8* idx) +{ + u8 i = 0; + struct beamforming_info *pBeamInfo = GET_BEAMFORM_INFO(pmlmepriv); + + for(i = 0; i < BEAMFORMING_ENTRY_NUM; i++) + { + if( pBeamInfo->beamforming_entry[i].bUsed && + (_rtw_memcmp(ra,pBeamInfo->beamforming_entry[i].mac_addr, ETH_ALEN))) + { + *idx = i; + return &(pBeamInfo->beamforming_entry[i]); + } + } + + return NULL; +} + +BEAMFORMING_CAP beamforming_get_entry_beam_cap_by_mac_id(PVOID pmlmepriv ,u8 mac_id) +{ + u8 i = 0; + struct beamforming_info *pBeamInfo = GET_BEAMFORM_INFO((struct mlme_priv *)pmlmepriv); + BEAMFORMING_CAP BeamformEntryCap = BEAMFORMING_CAP_NONE; + + for(i = 0; i < BEAMFORMING_ENTRY_NUM; i++) + { + if( pBeamInfo->beamforming_entry[i].bUsed && + (mac_id == pBeamInfo->beamforming_entry[i].mac_id)) + { + BeamformEntryCap = pBeamInfo->beamforming_entry[i].beamforming_entry_cap; + i = BEAMFORMING_ENTRY_NUM; + } + } + + return BeamformEntryCap; +} + +struct beamforming_entry *beamforming_get_free_entry(struct mlme_priv *pmlmepriv, u8* idx) +{ + u8 i = 0; + struct beamforming_info *pBeamInfo = GET_BEAMFORM_INFO(pmlmepriv); + + for(i = 0; i < BEAMFORMING_ENTRY_NUM; i++) + { + if(pBeamInfo->beamforming_entry[i].bUsed == _FALSE) + { + *idx = i; + return &(pBeamInfo->beamforming_entry[i]); + } + } + return NULL; +} + + +struct beamforming_entry *beamforming_add_entry(PADAPTER adapter, u8* ra, u16 aid, + u16 mac_id, CHANNEL_WIDTH bw, BEAMFORMING_CAP beamfrom_cap, u8* idx) +{ + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct beamforming_entry *pEntry = beamforming_get_free_entry(pmlmepriv, idx); + + if(pEntry != NULL) + { + pEntry->bUsed = _TRUE; + pEntry->aid = aid; + pEntry->mac_id = mac_id; + pEntry->sound_bw = bw; + if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) + { + u16 BSSID = ((*(adapter_mac_addr(adapter) + 5) & 0xf0) >> 4) ^ + (*(adapter_mac_addr(adapter) + 5) & 0xf); /* BSSID[44:47] xor BSSID[40:43] */ + pEntry->p_aid = (aid + BSSID * 32) & 0x1ff; // (dec(A) + dec(B)*32) mod 512 + pEntry->g_id = 63; + } + else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) + { + pEntry->p_aid = 0; + pEntry->g_id = 63; + } + else + { + pEntry->p_aid = ra[5]; // BSSID[39:47] + pEntry->p_aid = (pEntry->p_aid << 1) | (ra[4] >> 7 ); + pEntry->g_id = 0; + } + _rtw_memcpy(pEntry->mac_addr, ra, ETH_ALEN); + pEntry->bSound = _FALSE; + + //3 TODO SW/FW sound period + pEntry->sound_period = 200; + pEntry->beamforming_entry_cap = beamfrom_cap; + pEntry->beamforming_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; + + + pEntry->PreLogSeq = 0; /*Modified by Jeffery @2015-04-13*/ + pEntry->LogSeq = 0; /*Modified by Jeffery @2014-10-29*/ + pEntry->LogRetryCnt = 0; /*Modified by Jeffery @2014-10-29*/ + pEntry->LogSuccess = 0; /*LogSuccess is NOT needed to be accumulated, so LogSuccessCnt->LogSuccess, 2015-04-13, Jeffery*/ + pEntry->ClockResetTimes = 0; /*Modified by Jeffery @2015-04-13*/ + pEntry->LogStatusFailCnt = 0; + + return pEntry; + } + else + return NULL; +} + +BOOLEAN beamforming_remove_entry(struct mlme_priv *pmlmepriv, u8* ra, u8* idx) +{ + struct beamforming_entry *pEntry = beamforming_get_entry_by_addr(pmlmepriv, ra, idx); + + if(pEntry != NULL) + { + pEntry->bUsed = _FALSE; + pEntry->beamforming_entry_cap = BEAMFORMING_CAP_NONE; + pEntry->beamforming_entry_state = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; + return _TRUE; + } + else + return _FALSE; +} + +/* Used for BeamformingStart_V1 */ +void beamforming_dym_ndpa_rate(PADAPTER adapter) +{ + u16 NDPARate = MGN_6M; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); + + if(pHalData->MinUndecoratedPWDBForDM > 30) // link RSSI > 30% + NDPARate = MGN_24M; + else + NDPARate = MGN_6M; + + //BW = CHANNEL_WIDTH_20; + NDPARate = NDPARate << 8; + rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_RATE, (u8 *)&NDPARate); +} + +void beamforming_dym_period(PADAPTER Adapter) +{ + u8 Idx; + BOOLEAN bChangePeriod = _FALSE; + u16 SoundPeriod_SW, SoundPeriod_FW; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter); + struct beamforming_entry *pBeamformEntry; + struct beamforming_info *pBeamInfo = GET_BEAMFORM_INFO(( &Adapter->mlmepriv)); + struct sounding_info *pSoundInfo = &(pBeamInfo->sounding_info); + + //3 TODO per-client throughput caculation. + + if(pdvobjpriv->traffic_stat.cur_tx_tp + pdvobjpriv->traffic_stat.cur_rx_tp > 2) + { + SoundPeriod_SW = 32*20; + SoundPeriod_FW = 2; + } + else + { + SoundPeriod_SW = 32*2000; + SoundPeriod_FW = 200; + } + + for(Idx = 0; Idx < BEAMFORMING_ENTRY_NUM; Idx++) + { + pBeamformEntry = pBeamInfo->beamforming_entry+Idx; + if(pBeamformEntry->bDefaultCSI) + { + SoundPeriod_SW = 32*2000; + SoundPeriod_FW = 200; + } + + if(pBeamformEntry->beamforming_entry_cap & (BEAMFORMER_CAP_HT_EXPLICIT |BEAMFORMER_CAP_VHT_SU)) + { + if(pSoundInfo->sound_mode == SOUNDING_FW_VHT_TIMER || pSoundInfo->sound_mode == SOUNDING_FW_HT_TIMER) + { + if(pBeamformEntry->sound_period != SoundPeriod_FW) + { + pBeamformEntry->sound_period = SoundPeriod_FW; + bChangePeriod = _TRUE; // Only FW sounding need to send H2C packet to change sound period. + } + } + else if(pBeamformEntry->sound_period != SoundPeriod_SW) + { + pBeamformEntry->sound_period = SoundPeriod_SW; + } + } + } + + if(bChangePeriod) + rtw_hal_set_hwreg(Adapter, HW_VAR_SOUNDING_FW_NDPA, (u8 *)&Idx); +} + +BOOLEAN issue_ht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 qidx) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct rtw_ieee80211_hdr *pwlanhdr; + struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 ActionHdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c}; + u8 *pframe; + u16 *fctrl; + u16 duration = 0; + u8 aSifsTime = 0; + u8 NDPTxRate = 0; + + DBG_871X("%s: issue_ht_sw_ndpa_packet!\n", __func__); + + NDPTxRate = MGN_MCS8; + DBG_871X("%s: NDPTxRate =%d\n", __func__, NDPTxRate); + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + + if (pmgntframe == NULL) + return _FALSE; + + /*update attribute*/ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(Adapter, pattrib); + pattrib->qsel = QSLT_MGNT; + pattrib->rate = NDPTxRate; + pattrib->bwmode = bw; + pattrib->order = 1; + pattrib->subtype = WIFI_ACTION_NOACK; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &pwlanhdr->frame_ctl; + *(fctrl) = 0; + + SetOrderBit(pframe); + SetFrameSubType(pframe, WIFI_ACTION_NOACK); + + _rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(Adapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + if (pmlmeext->cur_wireless_mode == WIRELESS_11B) + aSifsTime = 10; + else + aSifsTime = 16; + + duration = 2*aSifsTime + 40; + + if (bw == CHANNEL_WIDTH_40) + duration += 87; + else + duration += 180; + + SetDuration(pframe, duration); + + /*HT control field*/ + SET_HT_CTRL_CSI_STEERING(pframe+24, 3); + SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe+24, 1); + + _rtw_memcpy(pframe+28, ActionHdr, 4); + + pattrib->pktlen = 32; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(Adapter, pmgntframe); + + return _TRUE; + + +} +BOOLEAN issue_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 qidx) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct rtw_ieee80211_hdr *pwlanhdr; + struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 ActionHdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c}; + u8 *pframe; + u16 *fctrl; + u16 duration = 0; + u8 aSifsTime = 0; + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + + if (pmgntframe == NULL) + return _FALSE; + + /*update attribute*/ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(Adapter, pattrib); + + if (qidx == BCN_QUEUE_INX) + pattrib->qsel = QSLT_BEACON; + pattrib->rate = MGN_MCS8; + pattrib->bwmode = bw; + pattrib->order = 1; + pattrib->subtype = WIFI_ACTION_NOACK; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + + pwlanhdr = (struct rtw_ieee80211_hdr*)pframe; + + fctrl = &pwlanhdr->frame_ctl; + *(fctrl) = 0; + + SetOrderBit(pframe); + SetFrameSubType(pframe, WIFI_ACTION_NOACK); + + _rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(Adapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + if( pmlmeext->cur_wireless_mode == WIRELESS_11B) + aSifsTime = 10; + else + aSifsTime = 16; + + duration = 2*aSifsTime + 40; + + if(bw == CHANNEL_WIDTH_40) + duration+= 87; + else + duration+= 180; + + SetDuration(pframe, duration); + + //HT control field + SET_HT_CTRL_CSI_STEERING(pframe+24, 3); + SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe+24, 1); + + _rtw_memcpy(pframe+28, ActionHdr, 4); + + pattrib->pktlen = 32; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(Adapter, pmgntframe); + + return _TRUE; +} + +BOOLEAN beamforming_send_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 qidx) +{ + return issue_ht_ndpa_packet(Adapter, ra, bw, qidx); +} +BOOLEAN issue_vht_sw_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDTH bw, u8 qidx) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct rtw_ieee80211_hdr *pwlanhdr; + struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + struct beamforming_info *pBeamInfo = GET_BEAMFORM_INFO(pmlmepriv); + struct rtw_ndpa_sta_info sta_info; + u8 NDPTxRate = 0; + + u8 *pframe; + u16 *fctrl; + u16 duration = 0; + u8 sequence = 0, aSifsTime = 0; + + DBG_871X("%s: issue_vht_sw_ndpa_packet!\n", __func__); + + + NDPTxRate = MGN_VHT2SS_MCS0; + DBG_871X("%s: NDPTxRate =%d\n", __func__, NDPTxRate); + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + + if (pmgntframe == NULL) { + DBG_871X("%s, alloc mgnt frame fail\n", __func__); + return _FALSE; + } + + /*update attribute*/ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(Adapter, pattrib); + pattrib->qsel = QSLT_MGNT; + pattrib->rate = NDPTxRate; + pattrib->bwmode = bw; + pattrib->subtype = WIFI_NDPA; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &pwlanhdr->frame_ctl; + *(fctrl) = 0; + + SetFrameSubType(pframe, WIFI_NDPA); + + _rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(Adapter), ETH_ALEN); + + if (IsSupported5G(pmlmeext->cur_wireless_mode) || IsSupportedHT(pmlmeext->cur_wireless_mode)) + aSifsTime = 16; + else + aSifsTime = 10; + + duration = 2*aSifsTime + 44; + + if (bw == CHANNEL_WIDTH_80) + duration += 40; + else if (bw == CHANNEL_WIDTH_40) + duration += 87; + else + duration += 180; + + SetDuration(pframe, duration); + + sequence = pBeamInfo->sounding_sequence << 2; + if (pBeamInfo->sounding_sequence >= 0x3f) + pBeamInfo->sounding_sequence = 0; + else + pBeamInfo->sounding_sequence++; + + _rtw_memcpy(pframe+16, &sequence, 1); + if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)) + aid = 0; + + sta_info.aid = aid; + sta_info.feedback_type = 0; + sta_info.nc_index = 0; + + _rtw_memcpy(pframe+17, (u8 *)&sta_info, 2); + + pattrib->pktlen = 19; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(Adapter, pmgntframe); + + + return _TRUE; + +} +BOOLEAN issue_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDTH bw, u8 qidx) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct rtw_ieee80211_hdr *pwlanhdr; + struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + struct beamforming_info *pBeamInfo = GET_BEAMFORM_INFO(pmlmepriv); + struct rtw_ndpa_sta_info sta_info; + u8 *pframe; + u16 *fctrl; + u16 duration = 0; + u8 sequence = 0, aSifsTime = 0; + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + return _FALSE; + + /*update attribute*/ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(Adapter, pattrib); + + if (qidx == BCN_QUEUE_INX) + pattrib->qsel = QSLT_BEACON; + pattrib->rate = MGN_VHT2SS_MCS0; + pattrib->bwmode = bw; + pattrib->subtype = WIFI_NDPA; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + + pwlanhdr = (struct rtw_ieee80211_hdr*)pframe; + + fctrl = &pwlanhdr->frame_ctl; + *(fctrl) = 0; + + SetFrameSubType(pframe, WIFI_NDPA); + + _rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(Adapter), ETH_ALEN); + + if (IsSupported5G(pmlmeext->cur_wireless_mode) || IsSupportedHT(pmlmeext->cur_wireless_mode)) + aSifsTime = 16; + else + aSifsTime = 10; + + duration = 2*aSifsTime + 44; + + if(bw == CHANNEL_WIDTH_80) + duration += 40; + else if(bw == CHANNEL_WIDTH_40) + duration+= 87; + else + duration+= 180; + + SetDuration(pframe, duration); + + sequence = pBeamInfo->sounding_sequence<< 2; + if (pBeamInfo->sounding_sequence >= 0x3f) + pBeamInfo->sounding_sequence = 0; + else + pBeamInfo->sounding_sequence++; + + _rtw_memcpy(pframe+16, &sequence,1); + + if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)) + aid = 0; + + sta_info.aid = aid; + sta_info.feedback_type = 0; + sta_info.nc_index= 0; + + _rtw_memcpy(pframe+17, (u8 *)&sta_info, 2); + + pattrib->pktlen = 19; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(Adapter, pmgntframe); + + return _TRUE; +} + +BOOLEAN beamforming_send_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDTH bw, u8 qidx) +{ + return issue_vht_ndpa_packet(Adapter, ra, aid, bw, qidx); +} + +BOOLEAN beamfomring_bSounding(struct beamforming_info *pBeamInfo) +{ + BOOLEAN bSounding = _FALSE; + + if(( beamforming_get_beamform_cap(pBeamInfo) & BEAMFORMER_CAP) == 0) + bSounding = _FALSE; + else + bSounding = _TRUE; + + return bSounding; +} + +u8 beamforming_sounding_idx(struct beamforming_info *pBeamInfo) +{ + u8 idx = 0; + u8 i; + + for(i = 0; i < BEAMFORMING_ENTRY_NUM; i++) + { + if (pBeamInfo->beamforming_entry[i].bUsed && + (_FALSE == pBeamInfo->beamforming_entry[i].bSound)) + { + idx = i; + break; + } + } + + return idx; +} + +SOUNDING_MODE beamforming_sounding_mode(struct beamforming_info *pBeamInfo, u8 idx) +{ + struct beamforming_entry BeamEntry = pBeamInfo->beamforming_entry[idx]; + SOUNDING_MODE mode; + + if(BeamEntry.beamforming_entry_cap & BEAMFORMER_CAP_VHT_SU) + { + mode = SOUNDING_FW_VHT_TIMER; + } + else if(BeamEntry.beamforming_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT) + { + mode = SOUNDING_FW_HT_TIMER; + } + else + { + mode = SOUNDING_STOP_All_TIMER; + } + + return mode; +} + +u16 beamforming_sounding_time(struct beamforming_info *pBeamInfo, SOUNDING_MODE mode, u8 idx) +{ + u16 sounding_time = 0xffff; + struct beamforming_entry BeamEntry = pBeamInfo->beamforming_entry[idx]; + + sounding_time = BeamEntry.sound_period; + + return sounding_time; +} + +CHANNEL_WIDTH beamforming_sounding_bw(struct beamforming_info *pBeamInfo, SOUNDING_MODE mode, u8 idx) +{ + CHANNEL_WIDTH sounding_bw = CHANNEL_WIDTH_20; + struct beamforming_entry BeamEntry = pBeamInfo->beamforming_entry[idx]; + + sounding_bw = BeamEntry.sound_bw; + + return sounding_bw; +} + +BOOLEAN beamforming_select_beam_entry(struct beamforming_info *pBeamInfo) +{ + struct sounding_info *pSoundInfo = &(pBeamInfo->sounding_info); + + pSoundInfo->sound_idx = beamforming_sounding_idx(pBeamInfo); + + if(pSoundInfo->sound_idx < BEAMFORMING_ENTRY_NUM) + pSoundInfo->sound_mode = beamforming_sounding_mode(pBeamInfo, pSoundInfo->sound_idx); + else + pSoundInfo->sound_mode = SOUNDING_STOP_All_TIMER; + + if(SOUNDING_STOP_All_TIMER == pSoundInfo->sound_mode) + { + return _FALSE; + } + else + { + pSoundInfo->sound_bw = beamforming_sounding_bw(pBeamInfo, pSoundInfo->sound_mode, pSoundInfo->sound_idx ); + pSoundInfo->sound_period = beamforming_sounding_time(pBeamInfo, pSoundInfo->sound_mode, pSoundInfo->sound_idx ); + return _TRUE; + } +} + +BOOLEAN beamforming_start_fw(PADAPTER adapter, u8 idx) +{ + u8 *RA = NULL; + struct beamforming_entry *pEntry; + BOOLEAN ret = _TRUE; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct beamforming_info *pBeamInfo = GET_BEAMFORM_INFO(pmlmepriv); + + pEntry = &(pBeamInfo->beamforming_entry[idx]); + if(pEntry->bUsed == _FALSE) + { + DBG_871X("Skip Beamforming, no entry for Idx =%d\n", idx); + return _FALSE; + } + + pEntry->beamforming_entry_state = BEAMFORMING_ENTRY_STATE_PROGRESSING; + pEntry->bSound = _TRUE; + rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_FW_NDPA, (u8 *)&idx); + + return _TRUE; +} + +void beamforming_end_fw(PADAPTER adapter) +{ + u8 idx = 0; + + rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_FW_NDPA, (u8 *)&idx); + + DBG_871X("%s\n", __FUNCTION__); +} + +BOOLEAN beamforming_start_period(PADAPTER adapter) +{ + BOOLEAN ret = _TRUE; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct beamforming_info *pBeamInfo = GET_BEAMFORM_INFO(pmlmepriv); + struct sounding_info *pSoundInfo = &(pBeamInfo->sounding_info); + + beamforming_dym_ndpa_rate(adapter); + + beamforming_select_beam_entry(pBeamInfo); + + if(pSoundInfo->sound_mode == SOUNDING_FW_VHT_TIMER || pSoundInfo->sound_mode == SOUNDING_FW_HT_TIMER) + { + ret = beamforming_start_fw(adapter, pSoundInfo->sound_idx); + } + else + { + ret = _FALSE; + } + + DBG_871X("%s Idx %d Mode %d BW %d Period %d\n", __FUNCTION__, + pSoundInfo->sound_idx, pSoundInfo->sound_mode, pSoundInfo->sound_bw, pSoundInfo->sound_period); + + return ret; +} + +void beamforming_end_period(PADAPTER adapter) +{ + u8 idx = 0; + struct beamforming_entry *pBeamformEntry; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct beamforming_info *pBeamInfo = GET_BEAMFORM_INFO(pmlmepriv); + struct sounding_info *pSoundInfo = &(pBeamInfo->sounding_info); + + + if(pSoundInfo->sound_mode == SOUNDING_FW_VHT_TIMER || pSoundInfo->sound_mode == SOUNDING_FW_HT_TIMER) + { + beamforming_end_fw(adapter); + } +} + +void beamforming_notify(PADAPTER adapter) +{ + BOOLEAN bSounding = _FALSE; + struct beamforming_info *pBeamInfo = GET_BEAMFORM_INFO(&(adapter->mlmepriv)); + + bSounding = beamfomring_bSounding(pBeamInfo); + + if(pBeamInfo->beamforming_state == BEAMFORMING_STATE_IDLE) + { + if(bSounding) + { + if(beamforming_start_period(adapter) == _TRUE) + pBeamInfo->beamforming_state = BEAMFORMING_STATE_START; + } + } + else if(pBeamInfo->beamforming_state == BEAMFORMING_STATE_START) + { + if(bSounding) + { + if(beamforming_start_period(adapter) == _FALSE) + pBeamInfo->beamforming_state = BEAMFORMING_STATE_END; + } + else + { + beamforming_end_period(adapter); + pBeamInfo->beamforming_state = BEAMFORMING_STATE_END; + } + } + else if(pBeamInfo->beamforming_state == BEAMFORMING_STATE_END) + { + if(bSounding) + { + if(beamforming_start_period(adapter) == _TRUE) + pBeamInfo->beamforming_state = BEAMFORMING_STATE_START; + } + } + else + { + DBG_871X("%s BeamformState %d\n", __FUNCTION__, pBeamInfo->beamforming_state); + } + + DBG_871X("%s BeamformState %d bSounding %d\n", __FUNCTION__, pBeamInfo->beamforming_state, bSounding); +} + +BOOLEAN beamforming_init_entry(PADAPTER adapter, struct sta_info *psta, u8* idx) +{ + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct ht_priv *phtpriv = &(pmlmepriv->htpriv); +#ifdef CONFIG_80211AC_VHT + struct vht_priv *pvhtpriv = &(pmlmepriv->vhtpriv); +#endif + struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct beamforming_entry *pBeamformEntry = NULL; + u8 *ra; + u16 aid, mac_id; + u8 wireless_mode; + CHANNEL_WIDTH bw = CHANNEL_WIDTH_20; + BEAMFORMING_CAP beamform_cap = BEAMFORMING_CAP_NONE; + + // The current setting does not support Beaforming + if (0 == phtpriv->beamform_cap +#ifdef CONFIG_80211AC_VHT + && 0 == pvhtpriv->beamform_cap +#endif + ) { + DBG_871X("The configuration disabled Beamforming! Skip...\n"); + return _FALSE; + } + + aid = psta->aid; + ra = psta->hwaddr; + mac_id = psta->mac_id; + wireless_mode = psta->wireless_mode; + bw = psta->bw_mode; + + if (IsSupportedHT(wireless_mode) || IsSupportedVHT(wireless_mode)) { + //3 // HT + u8 cur_beamform; + + cur_beamform = psta->htpriv.beamform_cap; + + // We are Beamformee because the STA is Beamformer + if(TEST_FLAG(cur_beamform, BEAMFORMING_HT_BEAMFORMER_ENABLE)) + beamform_cap =(BEAMFORMING_CAP)(beamform_cap |BEAMFORMEE_CAP_HT_EXPLICIT); + + // We are Beamformer because the STA is Beamformee + if(TEST_FLAG(cur_beamform, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) + beamform_cap =(BEAMFORMING_CAP)(beamform_cap | BEAMFORMER_CAP_HT_EXPLICIT); +#ifdef CONFIG_80211AC_VHT + if (IsSupportedVHT(wireless_mode)) { + //3 // VHT + cur_beamform = psta->vhtpriv.beamform_cap; + + // We are Beamformee because the STA is Beamformer + if(TEST_FLAG(cur_beamform, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) + beamform_cap =(BEAMFORMING_CAP)(beamform_cap |BEAMFORMEE_CAP_VHT_SU); + // We are Beamformer because the STA is Beamformee + if(TEST_FLAG(cur_beamform, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) + beamform_cap =(BEAMFORMING_CAP)(beamform_cap |BEAMFORMER_CAP_VHT_SU); + } +#endif //CONFIG_80211AC_VHT + + if(beamform_cap == BEAMFORMING_CAP_NONE) + return _FALSE; + + DBG_871X("Beamforming Config Capability = 0x%02X\n", beamform_cap); + + pBeamformEntry = beamforming_get_entry_by_addr(pmlmepriv, ra, idx); + if (pBeamformEntry == NULL) { + pBeamformEntry = beamforming_add_entry(adapter, ra, aid, mac_id, bw, beamform_cap, idx); + if(pBeamformEntry == NULL) + return _FALSE; + else + pBeamformEntry->beamforming_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZEING; + } else { + // Entry has been created. If entry is initialing or progressing then errors occur. + if (pBeamformEntry->beamforming_entry_state != BEAMFORMING_ENTRY_STATE_INITIALIZED && + pBeamformEntry->beamforming_entry_state != BEAMFORMING_ENTRY_STATE_PROGRESSED) { + DBG_871X("Error State of Beamforming"); + return _FALSE; + } else { + pBeamformEntry->beamforming_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZEING; + } + } + + pBeamformEntry->beamforming_entry_state = BEAMFORMING_ENTRY_STATE_INITIALIZED; + psta->txbf_paid = pBeamformEntry->p_aid; + psta->txbf_gid = pBeamformEntry->g_id; + + DBG_871X("%s Idx %d\n", __FUNCTION__, *idx); + } else { + return _FALSE; + } + + return _SUCCESS; +} + +void beamforming_deinit_entry(PADAPTER adapter, u8* ra) +{ + u8 idx = 0; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + + if(beamforming_remove_entry(pmlmepriv, ra, &idx) == _TRUE) + { + rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_LEAVE, (u8 *)&idx); + } + + DBG_871X("%s Idx %d\n", __FUNCTION__, idx); +} + +void beamforming_reset(PADAPTER adapter) +{ + u8 idx = 0; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct beamforming_info *pBeamInfo = GET_BEAMFORM_INFO(pmlmepriv); + + for(idx = 0; idx < BEAMFORMING_ENTRY_NUM; idx++) + { + if(pBeamInfo->beamforming_entry[idx].bUsed == _TRUE) + { + pBeamInfo->beamforming_entry[idx].bUsed = _FALSE; + pBeamInfo->beamforming_entry[idx].beamforming_entry_cap = BEAMFORMING_CAP_NONE; + pBeamInfo->beamforming_entry[idx].beamforming_entry_state= BEAMFORMING_ENTRY_STATE_UNINITIALIZE; + rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_LEAVE, (u8 *)&idx); + } + } + + DBG_871X("%s\n", __FUNCTION__); +} + +void beamforming_sounding_fail(PADAPTER Adapter) +{ + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + struct beamforming_info *pBeamInfo = GET_BEAMFORM_INFO(pmlmepriv); + struct beamforming_entry *pEntry = &(pBeamInfo->beamforming_entry[pBeamInfo->beamforming_cur_idx]); + + pEntry->bSound = _FALSE; + rtw_hal_set_hwreg(Adapter, HW_VAR_SOUNDING_FW_NDPA, (u8 *)&pBeamInfo->beamforming_cur_idx); + beamforming_deinit_entry(Adapter, pEntry->mac_addr); +} + +void beamforming_check_sounding_success(PADAPTER Adapter,BOOLEAN status) +{ + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + struct beamforming_info *pBeamInfo = GET_BEAMFORM_INFO(pmlmepriv); + struct beamforming_entry *pEntry = &(pBeamInfo->beamforming_entry[pBeamInfo->beamforming_cur_idx]); + + if(status == 1) + { + pEntry->LogStatusFailCnt = 0; + } + else + { + pEntry->LogStatusFailCnt++; + DBG_871X("%s LogStatusFailCnt %d\n", __FUNCTION__, pEntry->LogStatusFailCnt); + } + if(pEntry->LogStatusFailCnt > 20) + { + DBG_871X("%s LogStatusFailCnt > 20, Stop SOUNDING\n", __FUNCTION__); + //pEntry->bSound = _FALSE; + //rtw_hal_set_hwreg(Adapter, HW_VAR_SOUNDING_FW_NDPA, (u8 *)&pBeamInfo->beamforming_cur_idx); + //beamforming_deinit_entry(Adapter, pEntry->mac_addr); + beamforming_wk_cmd(Adapter, BEAMFORMING_CTRL_SOUNDING_FAIL, NULL, 0, 1); + } +} + +void beamforming_enter(PADAPTER adapter, PVOID psta) +{ + u8 idx = 0xff; + + if(beamforming_init_entry(adapter, (struct sta_info *)psta, &idx)) + rtw_hal_set_hwreg(adapter, HW_VAR_SOUNDING_ENTER, (u8 *)&idx); + + //DBG_871X("%s Idx %d\n", __FUNCTION__, idx); +} + +void beamforming_leave(PADAPTER adapter,u8* ra) +{ + if(ra == NULL) + beamforming_reset(adapter); + else + beamforming_deinit_entry(adapter, ra); + + beamforming_notify(adapter); +} + +BEAMFORMING_CAP beamforming_get_beamform_cap(struct beamforming_info *pBeamInfo) +{ + u8 i; + BOOLEAN bSelfBeamformer = _FALSE; + BOOLEAN bSelfBeamformee = _FALSE; + struct beamforming_entry beamforming_entry; + BEAMFORMING_CAP beamform_cap = BEAMFORMING_CAP_NONE; + + for(i = 0; i < BEAMFORMING_ENTRY_NUM; i++) + { + beamforming_entry = pBeamInfo->beamforming_entry[i]; + + if(beamforming_entry.bUsed) + { + if( (beamforming_entry.beamforming_entry_cap & BEAMFORMEE_CAP_VHT_SU) || + (beamforming_entry.beamforming_entry_cap & BEAMFORMEE_CAP_HT_EXPLICIT)) + bSelfBeamformee = _TRUE; + if( (beamforming_entry.beamforming_entry_cap & BEAMFORMER_CAP_VHT_SU) || + (beamforming_entry.beamforming_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT)) + bSelfBeamformer = _TRUE; + } + + if(bSelfBeamformer && bSelfBeamformee) + i = BEAMFORMING_ENTRY_NUM; + } + + if(bSelfBeamformer) + beamform_cap |= BEAMFORMER_CAP; + if(bSelfBeamformee) + beamform_cap |= BEAMFORMEE_CAP; + + return beamform_cap; +} + +void beamforming_watchdog(PADAPTER Adapter) +{ + struct beamforming_info *pBeamInfo = GET_BEAMFORM_INFO(( &(Adapter->mlmepriv))); + + if(pBeamInfo->beamforming_state != BEAMFORMING_STATE_START) + return; + + beamforming_dym_period(Adapter); + beamforming_dym_ndpa_rate(Adapter); +} +#endif/* #if (BEAMFORMING_SUPPORT ==0) - for diver defined beamforming*/ + +u32 beamforming_get_report_frame(PADAPTER Adapter, union recv_frame *precv_frame) +{ + u32 ret = _SUCCESS; +#if (BEAMFORMING_SUPPORT == 1) + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + + ret = Beamforming_GetReportFrame(pDM_Odm, precv_frame); + +#else /*(BEAMFORMING_SUPPORT == 0)- for drv beamfoming*/ + struct beamforming_entry *pBeamformEntry = NULL; + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + u8 *pframe = precv_frame->u.hdr.rx_data; + u32 frame_len = precv_frame->u.hdr.len; + u8 *ta; + u8 idx, offset; + + /*DBG_871X("beamforming_get_report_frame\n");*/ + + /*Memory comparison to see if CSI report is the same with previous one*/ + ta = GetAddr2Ptr(pframe); + pBeamformEntry = beamforming_get_entry_by_addr(pmlmepriv, ta, &idx); + if (pBeamformEntry->beamforming_entry_cap & BEAMFORMER_CAP_VHT_SU) + offset = 31; /*24+(1+1+3)+2 MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)*/ + else if (pBeamformEntry->beamforming_entry_cap & BEAMFORMER_CAP_HT_EXPLICIT) + offset = 34; /*24+(1+1+6)+2 MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)*/ + else + return ret; + + /*DBG_871X("%s MacId %d offset=%d\n", __FUNCTION__, pBeamformEntry->mac_id, offset);*/ + + if (_rtw_memcmp(pBeamformEntry->PreCsiReport + offset, pframe+offset, frame_len-offset) == _FALSE) + pBeamformEntry->DefaultCsiCnt = 0; + else + pBeamformEntry->DefaultCsiCnt++; + + _rtw_memcpy(&pBeamformEntry->PreCsiReport, pframe, frame_len); + + pBeamformEntry->bDefaultCSI = _FALSE; + + if (pBeamformEntry->DefaultCsiCnt > 20) + pBeamformEntry->bDefaultCSI = _TRUE; + else + pBeamformEntry->bDefaultCSI = _FALSE; +#endif + return ret; +} + +void beamforming_get_ndpa_frame(PADAPTER Adapter, union recv_frame *precv_frame) +{ +#if (BEAMFORMING_SUPPORT == 1) + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + + Beamforming_GetNDPAFrame(pDM_Odm, precv_frame); + +#else /*(BEAMFORMING_SUPPORT == 0)- for drv beamfoming*/ + u8 *ta; + u8 idx, Sequence; + u8 *pframe = precv_frame->u.hdr.rx_data; + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + struct beamforming_entry *pBeamformEntry = NULL; + + /*DBG_871X("beamforming_get_ndpa_frame\n");*/ + + if (IS_HARDWARE_TYPE_8812(Adapter) == _FALSE) + return; + else if (GetFrameSubType(pframe) != WIFI_NDPA) + return; + + ta = GetAddr2Ptr(pframe); + /*Remove signaling TA. */ + ta[0] = ta[0] & 0xFE; + + pBeamformEntry = beamforming_get_entry_by_addr(pmlmepriv, ta, &idx); + + if (pBeamformEntry == NULL) + return; + else if (!(pBeamformEntry->beamforming_entry_cap & BEAMFORMEE_CAP_VHT_SU)) + return; + /*LogSuccess: As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is NO LONGER needed !2015-04-10, Jeffery*/ + /*ClockResetTimes: While BFer entry always doesn't receive our CSI, clock will reset again and again.So ClockResetTimes is limited to 5 times.2015-04-13, Jeffery*/ + else if ((pBeamformEntry->LogSuccess == 1) || (pBeamformEntry->ClockResetTimes == 5)) { + DBG_871X("[%s] LogSeq=%d, PreLogSeq=%d\n", __func__, pBeamformEntry->LogSeq, pBeamformEntry->PreLogSeq); + return; + } + + Sequence = (pframe[16]) >> 2; + DBG_871X("[%s] Start, Sequence=%d, LogSeq=%d, PreLogSeq=%d, LogRetryCnt=%d, ClockResetTimes=%d, LogSuccess=%d\n", + __func__, Sequence, pBeamformEntry->LogSeq, pBeamformEntry->PreLogSeq, pBeamformEntry->LogRetryCnt, pBeamformEntry->ClockResetTimes, pBeamformEntry->LogSuccess); + + if ((pBeamformEntry->LogSeq != 0) && (pBeamformEntry->PreLogSeq != 0)) { + /*Success condition*/ + if ((pBeamformEntry->LogSeq != Sequence) && (pBeamformEntry->PreLogSeq != pBeamformEntry->LogSeq)) { + /* break option for clcok reset, 2015-03-30, Jeffery */ + pBeamformEntry->LogRetryCnt = 0; + /*As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is no longer needed.*/ + /*That is, LogSuccess is NOT needed to be reset to zero, 2015-04-13, Jeffery*/ + pBeamformEntry->LogSuccess = 1; + + } else {/*Fail condition*/ + + if (pBeamformEntry->LogRetryCnt == 5) { + pBeamformEntry->ClockResetTimes++; + pBeamformEntry->LogRetryCnt = 0; + + DBG_871X("[%s] Clock Reset!!! ClockResetTimes=%d\n", __func__, pBeamformEntry->ClockResetTimes); + beamforming_wk_cmd(Adapter, BEAMFORMING_CTRL_SOUNDING_CLK, NULL, 0, 1); + + } else + pBeamformEntry->LogRetryCnt++; + } + } + + /*Update LogSeq & PreLogSeq*/ + pBeamformEntry->PreLogSeq = pBeamformEntry->LogSeq; + pBeamformEntry->LogSeq = Sequence; + +#endif + +} + + + + +void beamforming_wk_hdl(_adapter *padapter, u8 type, u8 *pbuf) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); +_func_enter_; + +#if (BEAMFORMING_SUPPORT == 1) /*(BEAMFORMING_SUPPORT == 1)- for PHYDM beamfoming*/ + switch (type) { + case BEAMFORMING_CTRL_ENTER: + { + struct sta_info *psta = (PVOID)pbuf; + u16 staIdx = psta->mac_id; + + Beamforming_Enter(pDM_Odm, staIdx); + break; + } + case BEAMFORMING_CTRL_LEAVE: + Beamforming_Leave(pDM_Odm, pbuf); + break; + default: + break; + + } +#else /*(BEAMFORMING_SUPPORT == 0)- for drv beamfoming*/ + switch (type) { + case BEAMFORMING_CTRL_ENTER: + beamforming_enter(padapter, (PVOID)pbuf); + break; + + case BEAMFORMING_CTRL_LEAVE: + beamforming_leave(padapter, pbuf); + break; + + case BEAMFORMING_CTRL_SOUNDING_FAIL: + beamforming_sounding_fail(padapter); + break; + + case BEAMFORMING_CTRL_SOUNDING_CLK: + rtw_hal_set_hwreg(padapter, HW_VAR_SOUNDING_CLK, NULL); + break; + + default: + break; + } +#endif +_func_exit_; +} + +u8 beamforming_wk_cmd(_adapter*padapter, s32 type, u8 *pbuf, s32 size, u8 enqueue) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; + +_func_enter_; + + if(enqueue) + { + u8 *wk_buf; + + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(ph2c==NULL){ + res= _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if(pdrvextra_cmd_parm==NULL){ + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res= _FAIL; + goto exit; + } + + if (pbuf != NULL) { + wk_buf = rtw_zmalloc(size); + if(wk_buf==NULL){ + rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj)); + rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm)); + res= _FAIL; + goto exit; + } + + _rtw_memcpy(wk_buf, pbuf, size); + } else { + wk_buf = NULL; + size = 0; + } + + pdrvextra_cmd_parm->ec_id = BEAMFORMING_WK_CID; + pdrvextra_cmd_parm->type = type; + pdrvextra_cmd_parm->size = size; + pdrvextra_cmd_parm->pbuf = wk_buf; + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + } + else + { + beamforming_wk_hdl(padapter, type, pbuf); + } + +exit: + +_func_exit_; + + return res; +} + +void update_attrib_txbf_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta) +{ + if (psta) { + pattrib->txbf_g_id = psta->txbf_gid; + pattrib->txbf_p_aid = psta->txbf_paid; + } +} + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_br_ext.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_br_ext.c new file mode 100644 index 000000000..f3d27d649 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_br_ext.c @@ -0,0 +1,1706 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_BR_EXT_C_ + +#ifdef __KERNEL__ +#include +#include +#include +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(5, 14, 0)) +#include +#endif +#include +#include +#include +#endif + +#if 1 // rtw_wifi_driver +#include +#else // rtw_wifi_driver +#include "./8192cd_cfg.h" + +#ifndef __KERNEL__ +#include "./sys-support.h" +#endif + +#include "./8192cd.h" +#include "./8192cd_headers.h" +#include "./8192cd_br_ext.h" +#include "./8192cd_debug.h" +#endif // rtw_wifi_driver + +#ifdef CL_IPV6_PASS +#ifdef __KERNEL__ +#include +#include +#include +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24)) +#include +#else +#include +#endif +#endif +#endif + +#ifdef CONFIG_BR_EXT + +//#define BR_EXT_DEBUG + +#define NAT25_IPV4 01 +#define NAT25_IPV6 02 +#define NAT25_IPX 03 +#define NAT25_APPLE 04 +#define NAT25_PPPOE 05 + +#define RTL_RELAY_TAG_LEN (ETH_ALEN) +#define TAG_HDR_LEN 4 + +#define MAGIC_CODE 0x8186 +#define MAGIC_CODE_LEN 2 +#define WAIT_TIME_PPPOE 5 // waiting time for pppoe server in sec + +/*----------------------------------------------------------------- + How database records network address: + 0 1 2 3 4 5 6 7 8 9 10 + |----|----|----|----|----|----|----|----|----|----|----| + IPv4 |type| | IP addr | + IPX |type| Net addr | Node addr | + IPX |type| Net addr |Sckt addr| + Apple |type| Network |node| + PPPoE |type| SID | AC MAC | +-----------------------------------------------------------------*/ + + +//Find a tag in pppoe frame and return the pointer +static __inline__ unsigned char *__nat25_find_pppoe_tag(struct pppoe_hdr *ph, unsigned short type) +{ + unsigned char *cur_ptr, *start_ptr; + unsigned short tagLen, tagType; + + start_ptr = cur_ptr = (unsigned char *)ph->tag; + while((cur_ptr - start_ptr) < ntohs(ph->length)) { + // prevent un-alignment access + tagType = (unsigned short)((cur_ptr[0] << 8) + cur_ptr[1]); + tagLen = (unsigned short)((cur_ptr[2] << 8) + cur_ptr[3]); + if(tagType == type) + return cur_ptr; + cur_ptr = cur_ptr + TAG_HDR_LEN + tagLen; + } + return 0; +} + + +static __inline__ int __nat25_add_pppoe_tag(struct sk_buff *skb, struct pppoe_tag *tag) +{ + struct pppoe_hdr *ph = (struct pppoe_hdr *)(skb->data + ETH_HLEN); + int data_len; + + data_len = tag->tag_len + TAG_HDR_LEN; + if (skb_tailroom(skb) < data_len) { + _DEBUG_ERR("skb_tailroom() failed in add SID tag!\n"); + return -1; + } + + skb_put(skb, data_len); + // have a room for new tag + memmove(((unsigned char *)ph->tag + data_len), (unsigned char *)ph->tag, ntohs(ph->length)); + ph->length = htons(ntohs(ph->length) + data_len); + memcpy((unsigned char *)ph->tag, tag, data_len); + return data_len; +} + +static int skb_pull_and_merge(struct sk_buff *skb, unsigned char *src, int len) +{ + int tail_len; + unsigned long end, tail; + + if ((src+len) > skb_tail_pointer(skb) || skb->len < len) + return -1; + + tail = (unsigned long)skb_tail_pointer(skb); + end = (unsigned long)src+len; + if (tail < end) + return -1; + + tail_len = (int)(tail-end); + if (tail_len > 0) + memmove(src, src+len, tail_len); + + skb_trim(skb, skb->len-len); + return 0; +} + +static __inline__ unsigned long __nat25_timeout(_adapter *priv) +{ + unsigned long timeout; + + timeout = jiffies - NAT25_AGEING_TIME*HZ; + + return timeout; +} + + +static __inline__ int __nat25_has_expired(_adapter *priv, + struct nat25_network_db_entry *fdb) +{ + if(time_before_eq(fdb->ageing_timer, __nat25_timeout(priv))) + return 1; + + return 0; +} + + +static __inline__ void __nat25_generate_ipv4_network_addr(unsigned char *networkAddr, + unsigned int *ipAddr) +{ + memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); + + networkAddr[0] = NAT25_IPV4; + memcpy(networkAddr+7, (unsigned char *)ipAddr, 4); +} + + +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(5, 14, 0)) +static __inline__ void __nat25_generate_ipx_network_addr_with_node(unsigned char *networkAddr, + unsigned int *ipxNetAddr, unsigned char *ipxNodeAddr) +{ + memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); + + networkAddr[0] = NAT25_IPX; + memcpy(networkAddr+1, (unsigned char *)ipxNetAddr, 4); + memcpy(networkAddr+5, ipxNodeAddr, 6); +} + + +static __inline__ void __nat25_generate_ipx_network_addr_with_socket(unsigned char *networkAddr, + unsigned int *ipxNetAddr, unsigned short *ipxSocketAddr) +{ + memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); + + networkAddr[0] = NAT25_IPX; + memcpy(networkAddr+1, (unsigned char *)ipxNetAddr, 4); + memcpy(networkAddr+5, (unsigned char *)ipxSocketAddr, 2); +} + + +static __inline__ void __nat25_generate_apple_network_addr(unsigned char *networkAddr, + unsigned short *network, unsigned char *node) +{ + memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); + + networkAddr[0] = NAT25_APPLE; + memcpy(networkAddr+1, (unsigned char *)network, 2); + networkAddr[3] = *node; +} +#endif + + +static __inline__ void __nat25_generate_pppoe_network_addr(unsigned char *networkAddr, + unsigned char *ac_mac, unsigned short *sid) +{ + memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); + + networkAddr[0] = NAT25_PPPOE; + memcpy(networkAddr+1, (unsigned char *)sid, 2); + memcpy(networkAddr+3, (unsigned char *)ac_mac, 6); +} + + +#ifdef CL_IPV6_PASS +static void __nat25_generate_ipv6_network_addr(unsigned char *networkAddr, + unsigned int *ipAddr) +{ + memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); + + networkAddr[0] = NAT25_IPV6; + memcpy(networkAddr+1, (unsigned char *)ipAddr, 16); +} + + +static unsigned char *scan_tlv(unsigned char *data, int len, unsigned char tag, unsigned char len8b) +{ + while (len > 0) { + if (*data == tag && *(data+1) == len8b && len >= len8b*8) + return data+2; + + len -= (*(data+1))*8; + data += (*(data+1))*8; + } + return NULL; +} + + +static int update_nd_link_layer_addr(unsigned char *data, int len, unsigned char *replace_mac) +{ + struct icmp6hdr *icmphdr = (struct icmp6hdr *)data; + unsigned char *mac; + + if (icmphdr->icmp6_type == NDISC_ROUTER_SOLICITATION) { + if (len >= 8) { + mac = scan_tlv(&data[8], len-8, 1, 1); + if (mac) { + DBG_871X("Router Solicitation, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0],mac[1],mac[2],mac[3],mac[4],mac[5], + replace_mac[0],replace_mac[1],replace_mac[2],replace_mac[3],replace_mac[4],replace_mac[5]); + memcpy(mac, replace_mac, 6); + return 1; + } + } + } + else if (icmphdr->icmp6_type == NDISC_ROUTER_ADVERTISEMENT) { + if (len >= 16) { + mac = scan_tlv(&data[16], len-16, 1, 1); + if (mac) { + DBG_871X("Router Advertisement, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0],mac[1],mac[2],mac[3],mac[4],mac[5], + replace_mac[0],replace_mac[1],replace_mac[2],replace_mac[3],replace_mac[4],replace_mac[5]); + memcpy(mac, replace_mac, 6); + return 1; + } + } + } + else if (icmphdr->icmp6_type == NDISC_NEIGHBOUR_SOLICITATION) { + if (len >= 24) { + mac = scan_tlv(&data[24], len-24, 1, 1); + if (mac) { + DBG_871X("Neighbor Solicitation, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0],mac[1],mac[2],mac[3],mac[4],mac[5], + replace_mac[0],replace_mac[1],replace_mac[2],replace_mac[3],replace_mac[4],replace_mac[5]); + memcpy(mac, replace_mac, 6); + return 1; + } + } + } + else if (icmphdr->icmp6_type == NDISC_NEIGHBOUR_ADVERTISEMENT) { + if (len >= 24) { + mac = scan_tlv(&data[24], len-24, 2, 1); + if (mac) { + DBG_871X("Neighbor Advertisement, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0],mac[1],mac[2],mac[3],mac[4],mac[5], + replace_mac[0],replace_mac[1],replace_mac[2],replace_mac[3],replace_mac[4],replace_mac[5]); + memcpy(mac, replace_mac, 6); + return 1; + } + } + } + else if (icmphdr->icmp6_type == NDISC_REDIRECT) { + if (len >= 40) { + mac = scan_tlv(&data[40], len-40, 2, 1); + if (mac) { + DBG_871X("Redirect, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0],mac[1],mac[2],mac[3],mac[4],mac[5], + replace_mac[0],replace_mac[1],replace_mac[2],replace_mac[3],replace_mac[4],replace_mac[5]); + memcpy(mac, replace_mac, 6); + return 1; + } + } + } + return 0; +} + + +static void convert_ipv6_mac_to_mc(struct sk_buff *skb) +{ + struct ipv6hdr *iph = (struct ipv6hdr *)(skb->data + ETH_HLEN); + unsigned char *dst_mac = skb->data; + + //dst_mac[0] = 0xff; + //dst_mac[1] = 0xff; + /*modified by qinjunjie,ipv6 multicast address ix 0x33-33-xx-xx-xx-xx*/ + dst_mac[0] = 0x33; + dst_mac[1] = 0x33; + memcpy(&dst_mac[2], &iph->daddr.s6_addr32[3], 4); + #if defined(__LINUX_2_6__) + /*modified by qinjunjie,warning:should not remove next line*/ + skb->pkt_type = PACKET_MULTICAST; + #endif +} +#endif /* CL_IPV6_PASS */ + + +static __inline__ int __nat25_network_hash(unsigned char *networkAddr) +{ + if(networkAddr[0] == NAT25_IPV4) + { + unsigned long x; + + x = networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10]; + + return x & (NAT25_HASH_SIZE - 1); + } + else if(networkAddr[0] == NAT25_IPX) + { + unsigned long x; + + x = networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5] ^ + networkAddr[6] ^ networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10]; + + return x & (NAT25_HASH_SIZE - 1); + } + else if(networkAddr[0] == NAT25_APPLE) + { + unsigned long x; + + x = networkAddr[1] ^ networkAddr[2] ^ networkAddr[3]; + + return x & (NAT25_HASH_SIZE - 1); + } + else if(networkAddr[0] == NAT25_PPPOE) + { + unsigned long x; + + x = networkAddr[0] ^ networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5] ^ networkAddr[6] ^ networkAddr[7] ^ networkAddr[8]; + + return x & (NAT25_HASH_SIZE - 1); + } +#ifdef CL_IPV6_PASS + else if(networkAddr[0] == NAT25_IPV6) + { + unsigned long x; + + x = networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5] ^ + networkAddr[6] ^ networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10] ^ + networkAddr[11] ^ networkAddr[12] ^ networkAddr[13] ^ networkAddr[14] ^ networkAddr[15] ^ + networkAddr[16]; + + return x & (NAT25_HASH_SIZE - 1); + } +#endif + else + { + unsigned long x = 0; + int i; + + for (i=0; ibr_ext_lock, &irqL); + + ent->next_hash = priv->nethash[hash]; + if(ent->next_hash != NULL) + ent->next_hash->pprev_hash = &ent->next_hash; + priv->nethash[hash] = ent; + ent->pprev_hash = &priv->nethash[hash]; + + //_exit_critical_bh(&priv->br_ext_lock, &irqL); +} + + +static __inline__ void __network_hash_unlink(struct nat25_network_db_entry *ent) +{ + // Caller must _enter_critical_bh already! + //_irqL irqL; + //_enter_critical_bh(&priv->br_ext_lock, &irqL); + + *(ent->pprev_hash) = ent->next_hash; + if(ent->next_hash != NULL) + ent->next_hash->pprev_hash = ent->pprev_hash; + ent->next_hash = NULL; + ent->pprev_hash = NULL; + + //_exit_critical_bh(&priv->br_ext_lock, &irqL); +} + + +static int __nat25_db_network_lookup_and_replace(_adapter *priv, + struct sk_buff *skb, unsigned char *networkAddr) +{ + struct nat25_network_db_entry *db; + _irqL irqL; + _enter_critical_bh(&priv->br_ext_lock, &irqL); + + db = priv->nethash[__nat25_network_hash(networkAddr)]; + while (db != NULL) + { + if(!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) + { + if(!__nat25_has_expired(priv, db)) + { + // replace the destination mac address + memcpy(skb->data, db->macAddr, ETH_ALEN); + atomic_inc(&db->use_count); + +#ifdef CL_IPV6_PASS + DBG_871X("NAT25: Lookup M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x" + "%02x%02x%02x%02x%02x%02x\n", + db->macAddr[0], + db->macAddr[1], + db->macAddr[2], + db->macAddr[3], + db->macAddr[4], + db->macAddr[5], + db->networkAddr[0], + db->networkAddr[1], + db->networkAddr[2], + db->networkAddr[3], + db->networkAddr[4], + db->networkAddr[5], + db->networkAddr[6], + db->networkAddr[7], + db->networkAddr[8], + db->networkAddr[9], + db->networkAddr[10], + db->networkAddr[11], + db->networkAddr[12], + db->networkAddr[13], + db->networkAddr[14], + db->networkAddr[15], + db->networkAddr[16]); +#else + DBG_871X("NAT25: Lookup M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n", + db->macAddr[0], + db->macAddr[1], + db->macAddr[2], + db->macAddr[3], + db->macAddr[4], + db->macAddr[5], + db->networkAddr[0], + db->networkAddr[1], + db->networkAddr[2], + db->networkAddr[3], + db->networkAddr[4], + db->networkAddr[5], + db->networkAddr[6], + db->networkAddr[7], + db->networkAddr[8], + db->networkAddr[9], + db->networkAddr[10]); +#endif + } + _exit_critical_bh(&priv->br_ext_lock, &irqL); + return 1; + } + + db = db->next_hash; + } + + _exit_critical_bh(&priv->br_ext_lock, &irqL); + return 0; +} + + +static void __nat25_db_network_insert(_adapter *priv, + unsigned char *macAddr, unsigned char *networkAddr) +{ + struct nat25_network_db_entry *db; + int hash; + _irqL irqL; + _enter_critical_bh(&priv->br_ext_lock, &irqL); + + hash = __nat25_network_hash(networkAddr); + db = priv->nethash[hash]; + while (db != NULL) + { + if(!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) + { + memcpy(db->macAddr, macAddr, ETH_ALEN); + db->ageing_timer = jiffies; + _exit_critical_bh(&priv->br_ext_lock, &irqL); + return; + } + + db = db->next_hash; + } + + db = (struct nat25_network_db_entry *) rtw_malloc(sizeof(*db)); + if(db == NULL) { + _exit_critical_bh(&priv->br_ext_lock, &irqL); + return; + } + + memcpy(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN); + memcpy(db->macAddr, macAddr, ETH_ALEN); + atomic_set(&db->use_count, 1); + db->ageing_timer = jiffies; + + __network_hash_link(priv, db, hash); + + _exit_critical_bh(&priv->br_ext_lock, &irqL); +} + + +static void __nat25_db_print(_adapter *priv) +{ + _irqL irqL; + _enter_critical_bh(&priv->br_ext_lock, &irqL); + +#ifdef BR_EXT_DEBUG + static int counter = 0; + int i, j; + struct nat25_network_db_entry *db; + + counter++; + if((counter % 16) != 0) + return; + + for(i=0, j=0; inethash[i]; + + while (db != NULL) + { +#ifdef CL_IPV6_PASS + panic_printk("NAT25: DB(%d) H(%02d) C(%d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x" + "%02x%02x%02x%02x%02x%02x\n", + j, + i, + atomic_read(&db->use_count), + db->macAddr[0], + db->macAddr[1], + db->macAddr[2], + db->macAddr[3], + db->macAddr[4], + db->macAddr[5], + db->networkAddr[0], + db->networkAddr[1], + db->networkAddr[2], + db->networkAddr[3], + db->networkAddr[4], + db->networkAddr[5], + db->networkAddr[6], + db->networkAddr[7], + db->networkAddr[8], + db->networkAddr[9], + db->networkAddr[10], + db->networkAddr[11], + db->networkAddr[12], + db->networkAddr[13], + db->networkAddr[14], + db->networkAddr[15], + db->networkAddr[16]); +#else + panic_printk("NAT25: DB(%d) H(%02d) C(%d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n", + j, + i, + atomic_read(&db->use_count), + db->macAddr[0], + db->macAddr[1], + db->macAddr[2], + db->macAddr[3], + db->macAddr[4], + db->macAddr[5], + db->networkAddr[0], + db->networkAddr[1], + db->networkAddr[2], + db->networkAddr[3], + db->networkAddr[4], + db->networkAddr[5], + db->networkAddr[6], + db->networkAddr[7], + db->networkAddr[8], + db->networkAddr[9], + db->networkAddr[10]); +#endif + j++; + + db = db->next_hash; + } + } +#endif + + _exit_critical_bh(&priv->br_ext_lock, &irqL); +} + + + + +/* + * NAT2.5 interface + */ + +void nat25_db_cleanup(_adapter *priv) +{ + int i; + _irqL irqL; + _enter_critical_bh(&priv->br_ext_lock, &irqL); + + for(i=0; inethash[i]; + while (f != NULL) { + struct nat25_network_db_entry *g; + + g = f->next_hash; + if(priv->scdb_entry == f) + { + memset(priv->scdb_mac, 0, ETH_ALEN); + memset(priv->scdb_ip, 0, 4); + priv->scdb_entry = NULL; + } + __network_hash_unlink(f); + rtw_mfree((u8 *) f, sizeof(struct nat25_network_db_entry)); + + f = g; + } + } + + _exit_critical_bh(&priv->br_ext_lock, &irqL); +} + + +void nat25_db_expire(_adapter *priv) +{ + int i; + _irqL irqL; + _enter_critical_bh(&priv->br_ext_lock, &irqL); + + //if(!priv->ethBrExtInfo.nat25_disable) + { + for (i=0; inethash[i]; + + while (f != NULL) + { + struct nat25_network_db_entry *g; + g = f->next_hash; + + if(__nat25_has_expired(priv, f)) + { + if(atomic_dec_and_test(&f->use_count)) + { +#ifdef BR_EXT_DEBUG +#ifdef CL_IPV6_PASS + panic_printk("NAT25 Expire H(%02d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x" + "%02x%02x%02x%02x%02x%02x\n", + i, + f->macAddr[0], + f->macAddr[1], + f->macAddr[2], + f->macAddr[3], + f->macAddr[4], + f->macAddr[5], + f->networkAddr[0], + f->networkAddr[1], + f->networkAddr[2], + f->networkAddr[3], + f->networkAddr[4], + f->networkAddr[5], + f->networkAddr[6], + f->networkAddr[7], + f->networkAddr[8], + f->networkAddr[9], + f->networkAddr[10], + f->networkAddr[11], + f->networkAddr[12], + f->networkAddr[13], + f->networkAddr[14], + f->networkAddr[15], + f->networkAddr[16]); +#else + + panic_printk("NAT25 Expire H(%02d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n", + i, + f->macAddr[0], + f->macAddr[1], + f->macAddr[2], + f->macAddr[3], + f->macAddr[4], + f->macAddr[5], + f->networkAddr[0], + f->networkAddr[1], + f->networkAddr[2], + f->networkAddr[3], + f->networkAddr[4], + f->networkAddr[5], + f->networkAddr[6], + f->networkAddr[7], + f->networkAddr[8], + f->networkAddr[9], + f->networkAddr[10]); +#endif +#endif + if(priv->scdb_entry == f) + { + memset(priv->scdb_mac, 0, ETH_ALEN); + memset(priv->scdb_ip, 0, 4); + priv->scdb_entry = NULL; + } + __network_hash_unlink(f); + rtw_mfree((u8 *) f, sizeof(struct nat25_network_db_entry)); + } + } + + f = g; + } + } + } + + _exit_critical_bh(&priv->br_ext_lock, &irqL); +} + + +#ifdef SUPPORT_TX_MCAST2UNI +static int checkIPMcAndReplace(_adapter *priv, struct sk_buff *skb, unsigned int *dst_ip) +{ + struct stat_info *pstat; + struct list_head *phead, *plist; + int i; + + phead = &priv->asoc_list; + plist = phead->next; + + while (plist != phead) { + pstat = list_entry(plist, struct stat_info, asoc_list); + plist = plist->next; + + if (pstat->ipmc_num == 0) + continue; + + for (i=0; iipmc[i].used && !memcmp(&pstat->ipmc[i].mcmac[3], ((unsigned char *)dst_ip)+1, 3)) { + memcpy(skb->data, pstat->ipmc[i].mcmac, ETH_ALEN); + return 1; + } + } + } + return 0; +} +#endif + +int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method) +{ + unsigned short protocol; + unsigned char networkAddr[MAX_NETWORK_ADDR_LEN]; + + if(skb == NULL) + return -1; + + if((method <= NAT25_MIN) || (method >= NAT25_MAX)) + return -1; + + protocol = *((unsigned short *)(skb->data + 2 * ETH_ALEN)); + + /*---------------------------------------------------*/ + /* Handle IP frame */ + /*---------------------------------------------------*/ + if(protocol == __constant_htons(ETH_P_IP)) + { + struct iphdr* iph = (struct iphdr *)(skb->data + ETH_HLEN); + + if(((unsigned char*)(iph) + (iph->ihl<<2)) >= (skb->data + ETH_HLEN + skb->len)) + { + DEBUG_WARN("NAT25: malformed IP packet !\n"); + return -1; + } + + switch(method) + { + case NAT25_CHECK: + return -1; + + case NAT25_INSERT: + { + //some muticast with source IP is all zero, maybe other case is illegal + //in class A, B, C, host address is all zero or all one is illegal + if (iph->saddr == 0) + return 0; + DBG_871X("NAT25: Insert IP, SA=%08x, DA=%08x\n", iph->saddr, iph->daddr); + __nat25_generate_ipv4_network_addr(networkAddr, &iph->saddr); + //record source IP address and , source mac address into db + __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr); + + __nat25_db_print(priv); + } + return 0; + + case NAT25_LOOKUP: + { + DBG_871X("NAT25: Lookup IP, SA=%08x, DA=%08x\n", iph->saddr, iph->daddr); +#ifdef SUPPORT_TX_MCAST2UNI + if (priv->pshare->rf_ft_var.mc2u_disable || + ((((OPMODE & (WIFI_STATION_STATE|WIFI_ASOC_STATE)) + == (WIFI_STATION_STATE|WIFI_ASOC_STATE)) && + !checkIPMcAndReplace(priv, skb, &iph->daddr)) || + (OPMODE & WIFI_ADHOC_STATE))) +#endif + { + __nat25_generate_ipv4_network_addr(networkAddr, &iph->daddr); + + if (!__nat25_db_network_lookup_and_replace(priv, skb, networkAddr)) { + if (*((unsigned char *)&iph->daddr + 3) == 0xff) { + // L2 is unicast but L3 is broadcast, make L2 bacome broadcast + DBG_871X("NAT25: Set DA as boardcast\n"); + memset(skb->data, 0xff, ETH_ALEN); + } + else { + // forward unknow IP packet to upper TCP/IP + DBG_871X("NAT25: Replace DA with BR's MAC\n"); + if ( (*(u32 *)priv->br_mac) == 0 && (*(u16 *)(priv->br_mac+4)) == 0 ) { + void netdev_br_init(struct net_device *netdev); + printk("Re-init netdev_br_init() due to br_mac==0!\n"); + netdev_br_init(priv->pnetdev); + } + memcpy(skb->data, priv->br_mac, ETH_ALEN); + } + } + } + } + return 0; + + default: + return -1; + } + } + + /*---------------------------------------------------*/ + /* Handle ARP frame */ + /*---------------------------------------------------*/ + else if(protocol == __constant_htons(ETH_P_ARP)) + { + struct arphdr *arp = (struct arphdr *)(skb->data + ETH_HLEN); + unsigned char *arp_ptr = (unsigned char *)(arp + 1); + unsigned int *sender, *target; + + if(arp->ar_pro != __constant_htons(ETH_P_IP)) + { + DEBUG_WARN("NAT25: arp protocol unknown (%4x)!\n", htons(arp->ar_pro)); + return -1; + } + + switch(method) + { + case NAT25_CHECK: + return 0; // skb_copy for all ARP frame + + case NAT25_INSERT: + { + DBG_871X("NAT25: Insert ARP, MAC=%02x%02x%02x%02x%02x%02x\n", arp_ptr[0], + arp_ptr[1], arp_ptr[2], arp_ptr[3], arp_ptr[4], arp_ptr[5]); + + // change to ARP sender mac address to wlan STA address + memcpy(arp_ptr, GET_MY_HWADDR(priv), ETH_ALEN); + + arp_ptr += arp->ar_hln; + sender = (unsigned int *)arp_ptr; + + __nat25_generate_ipv4_network_addr(networkAddr, sender); + + __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr); + + __nat25_db_print(priv); + } + return 0; + + case NAT25_LOOKUP: + { + DBG_871X("NAT25: Lookup ARP\n"); + + arp_ptr += arp->ar_hln; + sender = (unsigned int *)arp_ptr; + arp_ptr += (arp->ar_hln + arp->ar_pln); + target = (unsigned int *)arp_ptr; + + __nat25_generate_ipv4_network_addr(networkAddr, target); + + __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); + + // change to ARP target mac address to Lookup result + arp_ptr = (unsigned char *)(arp + 1); + arp_ptr += (arp->ar_hln + arp->ar_pln); + memcpy(arp_ptr, skb->data, ETH_ALEN); + } + return 0; + + default: + return -1; + } + } + +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(5, 14, 0)) + /*---------------------------------------------------*/ + /* Handle IPX and Apple Talk frame */ + /*---------------------------------------------------*/ + else if((protocol == __constant_htons(ETH_P_IPX)) || + (protocol == __constant_htons(ETH_P_ATALK)) || + (protocol == __constant_htons(ETH_P_AARP))) + { + unsigned char ipx_header[2] = {0xFF, 0xFF}; + struct ipxhdr *ipx = NULL; + struct elapaarp *ea = NULL; + struct ddpehdr *ddp = NULL; + unsigned char *framePtr = skb->data + ETH_HLEN; + + if(protocol == __constant_htons(ETH_P_IPX)) + { + DBG_871X("NAT25: Protocol=IPX (Ethernet II)\n"); + ipx = (struct ipxhdr *)framePtr; + } + else //if(protocol <= __constant_htons(ETH_FRAME_LEN)) + { + if(!memcmp(ipx_header, framePtr, 2)) + { + DBG_871X("NAT25: Protocol=IPX (Ethernet 802.3)\n"); + ipx = (struct ipxhdr *)framePtr; + } + else + { + unsigned char ipx_8022_type = 0xE0; + unsigned char snap_8022_type = 0xAA; + + if(*framePtr == snap_8022_type) + { + unsigned char ipx_snap_id[5] = {0x0, 0x0, 0x0, 0x81, 0x37}; // IPX SNAP ID + unsigned char aarp_snap_id[5] = {0x00, 0x00, 0x00, 0x80, 0xF3}; // Apple Talk AARP SNAP ID + unsigned char ddp_snap_id[5] = {0x08, 0x00, 0x07, 0x80, 0x9B}; // Apple Talk DDP SNAP ID + + framePtr += 3; // eliminate the 802.2 header + + if(!memcmp(ipx_snap_id, framePtr, 5)) + { + framePtr += 5; // eliminate the SNAP header + + DBG_871X("NAT25: Protocol=IPX (Ethernet SNAP)\n"); + ipx = (struct ipxhdr *)framePtr; + } + else if(!memcmp(aarp_snap_id, framePtr, 5)) + { + framePtr += 5; // eliminate the SNAP header + + ea = (struct elapaarp *)framePtr; + } + else if(!memcmp(ddp_snap_id, framePtr, 5)) + { + framePtr += 5; // eliminate the SNAP header + + ddp = (struct ddpehdr *)framePtr; + } + else + { + DEBUG_WARN("NAT25: Protocol=Ethernet SNAP %02x%02x%02x%02x%02x\n", framePtr[0], + framePtr[1], framePtr[2], framePtr[3], framePtr[4]); + return -1; + } + } + else if(*framePtr == ipx_8022_type) + { + framePtr += 3; // eliminate the 802.2 header + + if(!memcmp(ipx_header, framePtr, 2)) + { + DBG_871X("NAT25: Protocol=IPX (Ethernet 802.2)\n"); + ipx = (struct ipxhdr *)framePtr; + } + else + return -1; + } + } + } + + /* IPX */ + if(ipx != NULL) + { + switch(method) + { + case NAT25_CHECK: + if(!memcmp(skb->data+ETH_ALEN, ipx->ipx_source.node, ETH_ALEN)) + { + DBG_871X("NAT25: Check IPX skb_copy\n"); + return 0; + } + return -1; + + case NAT25_INSERT: + { + DBG_871X("NAT25: Insert IPX, Dest=%08x,%02x%02x%02x%02x%02x%02x,%04x Source=%08x,%02x%02x%02x%02x%02x%02x,%04x\n", + ipx->ipx_dest.net, + ipx->ipx_dest.node[0], + ipx->ipx_dest.node[1], + ipx->ipx_dest.node[2], + ipx->ipx_dest.node[3], + ipx->ipx_dest.node[4], + ipx->ipx_dest.node[5], + ipx->ipx_dest.sock, + ipx->ipx_source.net, + ipx->ipx_source.node[0], + ipx->ipx_source.node[1], + ipx->ipx_source.node[2], + ipx->ipx_source.node[3], + ipx->ipx_source.node[4], + ipx->ipx_source.node[5], + ipx->ipx_source.sock); + + if(!memcmp(skb->data+ETH_ALEN, ipx->ipx_source.node, ETH_ALEN)) + { + DBG_871X("NAT25: Use IPX Net, and Socket as network addr\n"); + + __nat25_generate_ipx_network_addr_with_socket(networkAddr, &ipx->ipx_source.net, &ipx->ipx_source.sock); + + // change IPX source node addr to wlan STA address + memcpy(ipx->ipx_source.node, GET_MY_HWADDR(priv), ETH_ALEN); + } + else + { + __nat25_generate_ipx_network_addr_with_node(networkAddr, &ipx->ipx_source.net, ipx->ipx_source.node); + } + + __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr); + + __nat25_db_print(priv); + } + return 0; + + case NAT25_LOOKUP: + { + if(!memcmp(GET_MY_HWADDR(priv), ipx->ipx_dest.node, ETH_ALEN)) + { + DBG_871X("NAT25: Lookup IPX, Modify Destination IPX Node addr\n"); + + __nat25_generate_ipx_network_addr_with_socket(networkAddr, &ipx->ipx_dest.net, &ipx->ipx_dest.sock); + + __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); + + // replace IPX destination node addr with Lookup destination MAC addr + memcpy(ipx->ipx_dest.node, skb->data, ETH_ALEN); + } + else + { + __nat25_generate_ipx_network_addr_with_node(networkAddr, &ipx->ipx_dest.net, ipx->ipx_dest.node); + + __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); + } + } + return 0; + + default: + return -1; + } + } + + /* AARP */ + else if(ea != NULL) + { + /* Sanity check fields. */ + if(ea->hw_len != ETH_ALEN || ea->pa_len != AARP_PA_ALEN) + { + DEBUG_WARN("NAT25: Appletalk AARP Sanity check fail!\n"); + return -1; + } + + switch(method) + { + case NAT25_CHECK: + return 0; + + case NAT25_INSERT: + { + // change to AARP source mac address to wlan STA address + memcpy(ea->hw_src, GET_MY_HWADDR(priv), ETH_ALEN); + + DBG_871X("NAT25: Insert AARP, Source=%d,%d Destination=%d,%d\n", + ea->pa_src_net, + ea->pa_src_node, + ea->pa_dst_net, + ea->pa_dst_node); + + __nat25_generate_apple_network_addr(networkAddr, &ea->pa_src_net, &ea->pa_src_node); + + __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr); + + __nat25_db_print(priv); + } + return 0; + + case NAT25_LOOKUP: + { + DBG_871X("NAT25: Lookup AARP, Source=%d,%d Destination=%d,%d\n", + ea->pa_src_net, + ea->pa_src_node, + ea->pa_dst_net, + ea->pa_dst_node); + + __nat25_generate_apple_network_addr(networkAddr, &ea->pa_dst_net, &ea->pa_dst_node); + + __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); + + // change to AARP destination mac address to Lookup result + memcpy(ea->hw_dst, skb->data, ETH_ALEN); + } + return 0; + + default: + return -1; + } + } + + /* DDP */ + else if(ddp != NULL) + { + switch(method) + { + case NAT25_CHECK: + return -1; + + case NAT25_INSERT: + { + DBG_871X("NAT25: Insert DDP, Source=%d,%d Destination=%d,%d\n", + ddp->deh_snet, + ddp->deh_snode, + ddp->deh_dnet, + ddp->deh_dnode); + + __nat25_generate_apple_network_addr(networkAddr, &ddp->deh_snet, &ddp->deh_snode); + + __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr); + + __nat25_db_print(priv); + } + return 0; + + case NAT25_LOOKUP: + { + DBG_871X("NAT25: Lookup DDP, Source=%d,%d Destination=%d,%d\n", + ddp->deh_snet, + ddp->deh_snode, + ddp->deh_dnet, + ddp->deh_dnode); + + __nat25_generate_apple_network_addr(networkAddr, &ddp->deh_dnet, &ddp->deh_dnode); + + __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); + } + return 0; + + default: + return -1; + } + } + + return -1; + } +#endif + + /*---------------------------------------------------*/ + /* Handle PPPoE frame */ + /*---------------------------------------------------*/ + else if((protocol == __constant_htons(ETH_P_PPP_DISC)) || + (protocol == __constant_htons(ETH_P_PPP_SES))) + { + struct pppoe_hdr *ph = (struct pppoe_hdr *)(skb->data + ETH_HLEN); + unsigned short *pMagic; + + switch(method) + { + case NAT25_CHECK: + if (ph->sid == 0) + return 0; + return 1; + + case NAT25_INSERT: + if(ph->sid == 0) // Discovery phase according to tag + { + if(ph->code == PADI_CODE || ph->code == PADR_CODE) + { + if (priv->ethBrExtInfo.addPPPoETag) { + struct pppoe_tag *tag, *pOldTag; + unsigned char tag_buf[40]; + int old_tag_len=0; + + tag = (struct pppoe_tag *)tag_buf; + pOldTag = (struct pppoe_tag *)__nat25_find_pppoe_tag(ph, ntohs(PTT_RELAY_SID)); + if (pOldTag) { // if SID existed, copy old value and delete it + old_tag_len = ntohs(pOldTag->tag_len); + if (old_tag_len+TAG_HDR_LEN+MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN > sizeof(tag_buf)) { + DEBUG_ERR("SID tag length too long!\n"); + return -1; + } + + memcpy(tag->tag_data+MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN, + pOldTag->tag_data, old_tag_len); + + if (skb_pull_and_merge(skb, (unsigned char *)pOldTag, TAG_HDR_LEN+old_tag_len) < 0) { + DEBUG_ERR("call skb_pull_and_merge() failed in PADI/R packet!\n"); + return -1; + } + ph->length = htons(ntohs(ph->length)-TAG_HDR_LEN-old_tag_len); + } + + tag->tag_type = PTT_RELAY_SID; + tag->tag_len = htons(MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN+old_tag_len); + + // insert the magic_code+client mac in relay tag + pMagic = (unsigned short *)tag->tag_data; + *pMagic = htons(MAGIC_CODE); + memcpy(tag->tag_data+MAGIC_CODE_LEN, skb->data+ETH_ALEN, ETH_ALEN); + + //Add relay tag + if(__nat25_add_pppoe_tag(skb, tag) < 0) + return -1; + + DBG_871X("NAT25: Insert PPPoE, forward %s packet\n", + (ph->code == PADI_CODE ? "PADI" : "PADR")); + } + else { // not add relay tag + if (priv->pppoe_connection_in_progress && + memcmp(skb->data+ETH_ALEN, priv->pppoe_addr, ETH_ALEN)) { + DEBUG_ERR("Discard PPPoE packet due to another PPPoE connection is in progress!\n"); + return -2; + } + + if (priv->pppoe_connection_in_progress == 0) + memcpy(priv->pppoe_addr, skb->data+ETH_ALEN, ETH_ALEN); + + priv->pppoe_connection_in_progress = WAIT_TIME_PPPOE; + } + } + else + return -1; + } + else // session phase + { + DBG_871X("NAT25: Insert PPPoE, insert session packet to %s\n", skb->dev->name); + + __nat25_generate_pppoe_network_addr(networkAddr, skb->data, &(ph->sid)); + + __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr); + + __nat25_db_print(priv); + + if (!priv->ethBrExtInfo.addPPPoETag && + priv->pppoe_connection_in_progress && + !memcmp(skb->data+ETH_ALEN, priv->pppoe_addr, ETH_ALEN)) + priv->pppoe_connection_in_progress = 0; + } + return 0; + + case NAT25_LOOKUP: + if(ph->code == PADO_CODE || ph->code == PADS_CODE) + { + if (priv->ethBrExtInfo.addPPPoETag) { + struct pppoe_tag *tag; + unsigned char *ptr; + unsigned short tagType, tagLen; + int offset=0; + + if((ptr = __nat25_find_pppoe_tag(ph, ntohs(PTT_RELAY_SID))) == 0) { + DEBUG_ERR("Fail to find PTT_RELAY_SID in FADO!\n"); + return -1; + } + + tag = (struct pppoe_tag *)ptr; + tagType = (unsigned short)((ptr[0] << 8) + ptr[1]); + tagLen = (unsigned short)((ptr[2] << 8) + ptr[3]); + + if((tagType != ntohs(PTT_RELAY_SID)) || (tagLen < (MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN))) { + DEBUG_ERR("Invalid PTT_RELAY_SID tag length [%d]!\n", tagLen); + return -1; + } + + pMagic = (unsigned short *)tag->tag_data; + if (ntohs(*pMagic) != MAGIC_CODE) { + DEBUG_ERR("Can't find MAGIC_CODE in %s packet!\n", + (ph->code == PADO_CODE ? "PADO" : "PADS")); + return -1; + } + + memcpy(skb->data, tag->tag_data+MAGIC_CODE_LEN, ETH_ALEN); + + if (tagLen > MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN) + offset = TAG_HDR_LEN; + + if (skb_pull_and_merge(skb, ptr+offset, TAG_HDR_LEN+MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN-offset) < 0) { + DEBUG_ERR("call skb_pull_and_merge() failed in PADO packet!\n"); + return -1; + } + ph->length = htons(ntohs(ph->length)-(TAG_HDR_LEN+MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN-offset)); + if (offset > 0) + tag->tag_len = htons(tagLen-MAGIC_CODE_LEN-RTL_RELAY_TAG_LEN); + + DBG_871X("NAT25: Lookup PPPoE, forward %s Packet from %s\n", + (ph->code == PADO_CODE ? "PADO" : "PADS"), skb->dev->name); + } + else { // not add relay tag + if (!priv->pppoe_connection_in_progress) { + DEBUG_ERR("Discard PPPoE packet due to no connection in progresss!\n"); + return -1; + } + memcpy(skb->data, priv->pppoe_addr, ETH_ALEN); + priv->pppoe_connection_in_progress = WAIT_TIME_PPPOE; + } + } + else { + if(ph->sid != 0) + { + DBG_871X("NAT25: Lookup PPPoE, lookup session packet from %s\n", skb->dev->name); + __nat25_generate_pppoe_network_addr(networkAddr, skb->data+ETH_ALEN, &(ph->sid)); + + __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); + + __nat25_db_print(priv); + } + else + return -1; + + } + return 0; + + default: + return -1; + } + } + + /*---------------------------------------------------*/ + /* Handle EAP frame */ + /*---------------------------------------------------*/ + else if(protocol == __constant_htons(0x888e)) + { + switch(method) + { + case NAT25_CHECK: + return -1; + + case NAT25_INSERT: + return 0; + + case NAT25_LOOKUP: + return 0; + + default: + return -1; + } + } + + /*---------------------------------------------------*/ + /* Handle C-Media proprietary frame */ + /*---------------------------------------------------*/ + else if((protocol == __constant_htons(0xe2ae)) || + (protocol == __constant_htons(0xe2af))) + { + switch(method) + { + case NAT25_CHECK: + return -1; + + case NAT25_INSERT: + return 0; + + case NAT25_LOOKUP: + return 0; + + default: + return -1; + } + } + + /*---------------------------------------------------*/ + /* Handle IPV6 frame */ + /*---------------------------------------------------*/ +#ifdef CL_IPV6_PASS + else if(protocol == __constant_htons(ETH_P_IPV6)) + { + struct ipv6hdr *iph = (struct ipv6hdr *)(skb->data + ETH_HLEN); + + if (sizeof(*iph) >= (skb->len - ETH_HLEN)) + { + DEBUG_WARN("NAT25: malformed IPv6 packet !\n"); + return -1; + } + + switch(method) + { + case NAT25_CHECK: + if (skb->data[0] & 1) + return 0; + return -1; + + case NAT25_INSERT: + { + DBG_871X("NAT25: Insert IP, SA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x," + " DA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x\n", + iph->saddr.s6_addr16[0],iph->saddr.s6_addr16[1],iph->saddr.s6_addr16[2],iph->saddr.s6_addr16[3], + iph->saddr.s6_addr16[4],iph->saddr.s6_addr16[5],iph->saddr.s6_addr16[6],iph->saddr.s6_addr16[7], + iph->daddr.s6_addr16[0],iph->daddr.s6_addr16[1],iph->daddr.s6_addr16[2],iph->daddr.s6_addr16[3], + iph->daddr.s6_addr16[4],iph->daddr.s6_addr16[5],iph->daddr.s6_addr16[6],iph->daddr.s6_addr16[7]); + + if (memcmp(&iph->saddr, "\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0", 16)) { + __nat25_generate_ipv6_network_addr(networkAddr, (unsigned int *)&iph->saddr); + __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr); + __nat25_db_print(priv); + + if (iph->nexthdr == IPPROTO_ICMPV6 && + skb->len > (ETH_HLEN + sizeof(*iph) + 4)) { + if (update_nd_link_layer_addr(skb->data + ETH_HLEN + sizeof(*iph), + skb->len - ETH_HLEN - sizeof(*iph), GET_MY_HWADDR(priv))) { + struct icmp6hdr *hdr = (struct icmp6hdr *)(skb->data + ETH_HLEN + sizeof(*iph)); + hdr->icmp6_cksum = 0; + hdr->icmp6_cksum = csum_ipv6_magic(&iph->saddr, &iph->daddr, + iph->payload_len, + IPPROTO_ICMPV6, + csum_partial((__u8 *)hdr, iph->payload_len, 0)); + } + } + } + } + return 0; + + case NAT25_LOOKUP: + DBG_871X("NAT25: Lookup IP, SA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x," + " DA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x\n", + iph->saddr.s6_addr16[0],iph->saddr.s6_addr16[1],iph->saddr.s6_addr16[2],iph->saddr.s6_addr16[3], + iph->saddr.s6_addr16[4],iph->saddr.s6_addr16[5],iph->saddr.s6_addr16[6],iph->saddr.s6_addr16[7], + iph->daddr.s6_addr16[0],iph->daddr.s6_addr16[1],iph->daddr.s6_addr16[2],iph->daddr.s6_addr16[3], + iph->daddr.s6_addr16[4],iph->daddr.s6_addr16[5],iph->daddr.s6_addr16[6],iph->daddr.s6_addr16[7]); + + + __nat25_generate_ipv6_network_addr(networkAddr, (unsigned int *)&iph->daddr); + if (!__nat25_db_network_lookup_and_replace(priv, skb, networkAddr)) { +#ifdef SUPPORT_RX_UNI2MCAST + if (iph->daddr.s6_addr[0] == 0xff) + convert_ipv6_mac_to_mc(skb); +#endif + } + return 0; + + default: + return -1; + } + } +#endif // CL_IPV6_PASS + + return -1; +} + + +int nat25_handle_frame(_adapter *priv, struct sk_buff *skb) +{ +#ifdef BR_EXT_DEBUG + if((!priv->ethBrExtInfo.nat25_disable) && (!(skb->data[0] & 1))) + { + panic_printk("NAT25: Input Frame: DA=%02x%02x%02x%02x%02x%02x SA=%02x%02x%02x%02x%02x%02x\n", + skb->data[0], + skb->data[1], + skb->data[2], + skb->data[3], + skb->data[4], + skb->data[5], + skb->data[6], + skb->data[7], + skb->data[8], + skb->data[9], + skb->data[10], + skb->data[11]); + } +#endif + + if(!(skb->data[0] & 1)) + { + int is_vlan_tag=0, i, retval=0; + unsigned short vlan_hdr=0; + + if (*((unsigned short *)(skb->data+ETH_ALEN*2)) == __constant_htons(ETH_P_8021Q)) { + is_vlan_tag = 1; + vlan_hdr = *((unsigned short *)(skb->data+ETH_ALEN*2+2)); + for (i=0; i<6; i++) + *((unsigned short *)(skb->data+ETH_ALEN*2+2-i*2)) = *((unsigned short *)(skb->data+ETH_ALEN*2-2-i*2)); + skb_pull(skb, 4); + } + + if (!priv->ethBrExtInfo.nat25_disable) + { + _irqL irqL; + _enter_critical_bh(&priv->br_ext_lock, &irqL); + /* + * This function look up the destination network address from + * the NAT2.5 database. Return value = -1 means that the + * corresponding network protocol is NOT support. + */ + if (!priv->ethBrExtInfo.nat25sc_disable && + (*((unsigned short *)(skb->data+ETH_ALEN*2)) == __constant_htons(ETH_P_IP)) && + !memcmp(priv->scdb_ip, skb->data+ETH_HLEN+16, 4)) { + memcpy(skb->data, priv->scdb_mac, ETH_ALEN); + + _exit_critical_bh(&priv->br_ext_lock, &irqL); + } + else { + _exit_critical_bh(&priv->br_ext_lock, &irqL); + + retval = nat25_db_handle(priv, skb, NAT25_LOOKUP); + } + } + else { + if (((*((unsigned short *)(skb->data+ETH_ALEN*2)) == __constant_htons(ETH_P_IP)) && + !memcmp(priv->br_ip, skb->data+ETH_HLEN+16, 4)) || + ((*((unsigned short *)(skb->data+ETH_ALEN*2)) == __constant_htons(ETH_P_ARP)) && + !memcmp(priv->br_ip, skb->data+ETH_HLEN+24, 4))) { + // for traffic to upper TCP/IP + retval = nat25_db_handle(priv, skb, NAT25_LOOKUP); + } + } + + if (is_vlan_tag) { + skb_push(skb, 4); + for (i=0; i<6; i++) + *((unsigned short *)(skb->data+i*2)) = *((unsigned short *)(skb->data+4+i*2)); + *((unsigned short *)(skb->data+ETH_ALEN*2)) = __constant_htons(ETH_P_8021Q); + *((unsigned short *)(skb->data+ETH_ALEN*2+2)) = vlan_hdr; + } + + if(retval == -1) { + //DEBUG_ERR("NAT25: Lookup fail!\n"); + return -1; + } + } + + return 0; +} + +#if 0 +void mac_clone(_adapter *priv, unsigned char *addr) +{ + struct sockaddr sa; + + memcpy(sa.sa_data, addr, ETH_ALEN); + DBG_871X("MAC Clone: Addr=%02x%02x%02x%02x%02x%02x\n", + addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); + rtl8192cd_set_hwaddr(priv->dev, &sa); +} + + +int mac_clone_handle_frame(_adapter *priv, struct sk_buff *skb) +{ + if(priv->ethBrExtInfo.macclone_enable && !priv->macclone_completed) + { + if(!(skb->data[ETH_ALEN] & 1)) //// check any other particular MAC add + { + if(memcmp(skb->data+ETH_ALEN, GET_MY_HWADDR(priv), ETH_ALEN) && + ((priv->dev->br_port) && + memcmp(skb->data+ETH_ALEN, priv->br_mac, ETH_ALEN))) + { + mac_clone(priv, skb->data+ETH_ALEN); + priv->macclone_completed = 1; + } + } + } + + return 0; +} +#endif // 0 + +#define SERVER_PORT 67 +#define CLIENT_PORT 68 +#define DHCP_MAGIC 0x63825363 +#define BROADCAST_FLAG 0x8000 + +struct dhcpMessage { + u_int8_t op; + u_int8_t htype; + u_int8_t hlen; + u_int8_t hops; + u_int32_t xid; + u_int16_t secs; + u_int16_t flags; + u_int32_t ciaddr; + u_int32_t yiaddr; + u_int32_t siaddr; + u_int32_t giaddr; + u_int8_t chaddr[16]; + u_int8_t sname[64]; + u_int8_t file[128]; + u_int32_t cookie; + u_int8_t options[308]; /* 312 - cookie */ +}; + +void dhcp_flag_bcast(_adapter *priv, struct sk_buff *skb) +{ + if(skb == NULL) + return; + + if(!priv->ethBrExtInfo.dhcp_bcst_disable) + { + unsigned short protocol = *((unsigned short *)(skb->data + 2 * ETH_ALEN)); + + if(protocol == __constant_htons(ETH_P_IP)) // IP + { + struct iphdr* iph = (struct iphdr *)(skb->data + ETH_HLEN); + + if(iph->protocol == IPPROTO_UDP) // UDP + { + struct udphdr *udph = (struct udphdr *)((SIZE_PTR)iph + (iph->ihl << 2)); + + if((udph->source == __constant_htons(CLIENT_PORT)) + && (udph->dest == __constant_htons(SERVER_PORT))) // DHCP request + { + struct dhcpMessage *dhcph = + (struct dhcpMessage *)((SIZE_PTR)udph + sizeof(struct udphdr)); + + if(dhcph->cookie == __constant_htonl(DHCP_MAGIC)) // match magic word + { + if(!(dhcph->flags & htons(BROADCAST_FLAG))) // if not broadcast + { + register int sum = 0; + + DBG_871X("DHCP: change flag of DHCP request to broadcast.\n"); + // or BROADCAST flag + dhcph->flags |= htons(BROADCAST_FLAG); + // recalculate checksum + sum = ~(udph->check) & 0xffff; + sum += dhcph->flags; + while(sum >> 16) + sum = (sum & 0xffff) + (sum >> 16); + udph->check = ~sum; + } + } + } + } + } + } +} + + +void *scdb_findEntry(_adapter *priv, unsigned char *macAddr, + unsigned char *ipAddr) +{ + unsigned char networkAddr[MAX_NETWORK_ADDR_LEN]; + struct nat25_network_db_entry *db; + int hash; + //_irqL irqL; + //_enter_critical_bh(&priv->br_ext_lock, &irqL); + + __nat25_generate_ipv4_network_addr(networkAddr, (unsigned int *)ipAddr); + hash = __nat25_network_hash(networkAddr); + db = priv->nethash[hash]; + while (db != NULL) + { + if(!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) { + //_exit_critical_bh(&priv->br_ext_lock, &irqL); + return (void *)db; + } + + db = db->next_hash; + } + + //_exit_critical_bh(&priv->br_ext_lock, &irqL); + return NULL; +} + +#endif // CONFIG_BR_EXT + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_bt_mp.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_bt_mp.c new file mode 100644 index 000000000..338a5b315 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_bt_mp.c @@ -0,0 +1,1753 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#include +#include + +#if defined(CONFIG_RTL8723B) +#include +#endif + +#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8821A) +void MPh2c_timeout_handle(void *FunctionContext) +{ + PADAPTER pAdapter; + PMPT_CONTEXT pMptCtx; + + + DBG_8192C("[MPT], MPh2c_timeout_handle \n"); + + pAdapter = (PADAPTER)FunctionContext; + pMptCtx = &pAdapter->mppriv.MptCtx; + + pMptCtx->bMPh2c_timeout = _TRUE; + + if ((_FALSE == pMptCtx->MptH2cRspEvent) + || ((_TRUE == pMptCtx->MptH2cRspEvent) + && (_FALSE == pMptCtx->MptBtC2hEvent))) + { + _rtw_up_sema(&pMptCtx->MPh2c_Sema); + } +} + +u32 WaitC2Hevent(PADAPTER pAdapter, u8 *C2H_event, u32 delay_time) +{ + PMPT_CONTEXT pMptCtx=&(pAdapter->mppriv.MptCtx); + pMptCtx->bMPh2c_timeout=_FALSE; + + if( pAdapter->registrypriv.mp_mode == 0 ) + { + DBG_8192C("[MPT], Error!! WaitC2Hevent mp_mode == 0!!\n"); + return _FALSE; + } + + _set_timer( &pMptCtx->MPh2c_timeout_timer, delay_time ); + + _rtw_down_sema(&pMptCtx->MPh2c_Sema); + + if (pMptCtx->bMPh2c_timeout == _TRUE) + { + *C2H_event = _FALSE; + + return _FALSE; + } + + // for safty, cancel timer here again + _cancel_timer_ex(&pMptCtx->MPh2c_timeout_timer); + + return _TRUE; +} + +BT_CTRL_STATUS +mptbt_CheckC2hFrame( + PADAPTER Adapter, + PBT_H2C pH2c, + PBT_EXT_C2H pExtC2h + ) +{ + BT_CTRL_STATUS c2hStatus = BT_STATUS_C2H_SUCCESS; + + //DBG_8192C("[MPT], MPT rsp C2H hex: %x %x %x %x %x %x \n"), pExtC2h , pExtC2h+1 ,pExtC2h+2 ,pExtC2h+3 ,pExtC2h+4 ,pExtC2h+5); + + DBG_8192C("[MPT], statusCode = 0x%x\n", pExtC2h->statusCode); + DBG_8192C("[MPT], retLen = %d\n", pExtC2h->retLen); + DBG_8192C("[MPT], opCodeVer : req/rsp=%d/%d\n", pH2c->opCodeVer, pExtC2h->opCodeVer); + DBG_8192C("[MPT], reqNum : req/rsp=%d/%d\n", pH2c->reqNum, pExtC2h->reqNum); + if(pExtC2h->reqNum != pH2c->reqNum) + { + c2hStatus = BT_STATUS_C2H_REQNUM_MISMATCH; + DBG_8192C("[MPT], Error!! C2H reqNum Mismatch!!\n"); + } + else if(pExtC2h->opCodeVer != pH2c->opCodeVer) + { + c2hStatus = BT_STATUS_OPCODE_L_VERSION_MISMATCH; + DBG_8192C("[MPT], Error!! OPCode version L mismatch!!\n"); + } + + return c2hStatus; +} + +BT_CTRL_STATUS +mptbt_SendH2c( + PADAPTER Adapter, + PBT_H2C pH2c, + u2Byte h2cCmdLen + ) +{ + //KIRQL OldIrql = KeGetCurrentIrql(); + BT_CTRL_STATUS h2cStatus=BT_STATUS_H2C_SUCCESS; + PMPT_CONTEXT pMptCtx=&(Adapter->mppriv.MptCtx); + u1Byte i; + + DBG_8192C("[MPT], mptbt_SendH2c()=========>\n"); + + //PlatformResetEvent(&pMptCtx->MptH2cRspEvent); + //PlatformResetEvent(&pMptCtx->MptBtC2hEvent); + +// if(OldIrql == PASSIVE_LEVEL) +// { + //RTPRINT_DATA(FMPBT, FMPBT_H2C_CONTENT, ("[MPT], MPT H2C hex: \n"), pH2c, h2cCmdLen); + + for(i=0; iMptH2cRspEvent = _FALSE; + pMptCtx->MptBtC2hEvent = _FALSE; + +#if defined(CONFIG_RTL8723B) + rtl8723b_set_FwBtMpOper_cmd(Adapter, pH2c->opCode, pH2c->opCodeVer, pH2c->reqNum, pH2c->buf); +#endif + pMptCtx->h2cReqNum++; + pMptCtx->h2cReqNum %= 16; + + if(WaitC2Hevent(Adapter, &pMptCtx->MptH2cRspEvent, 100)) + { + DBG_8192C("[MPT], Received WiFi MptH2cRspEvent!!!\n"); + if(WaitC2Hevent(Adapter, &pMptCtx->MptBtC2hEvent, 400)) + { + DBG_8192C("[MPT], Received MptBtC2hEvent!!!\n"); + break; + } + else + { + DBG_8192C("[MPT], Error!!BT MptBtC2hEvent timeout!!\n"); + h2cStatus = BT_STATUS_H2C_BT_NO_RSP; + } + } + else + { + DBG_8192C("[MPT], Error!!WiFi MptH2cRspEvent timeout!!\n"); + h2cStatus = BT_STATUS_H2C_TIMTOUT; + } + } +// } +// else +// { +// RT_ASSERT(FALSE, ("[MPT], mptbt_SendH2c() can only run under PASSIVE_LEVEL!!\n")); +// h2cStatus = BT_STATUS_WRONG_LEVEL; +// } + + DBG_8192C("[MPT], mptbt_SendH2c()<=========\n"); + return h2cStatus; +} + + + +BT_CTRL_STATUS +mptbt_CheckBtRspStatus( + PADAPTER Adapter, + PBT_EXT_C2H pExtC2h + ) +{ + BT_CTRL_STATUS retStatus=BT_OP_STATUS_SUCCESS; + + switch(pExtC2h->statusCode) + { + case BT_OP_STATUS_SUCCESS: + retStatus = BT_STATUS_BT_OP_SUCCESS; + DBG_8192C("[MPT], BT status : BT_STATUS_SUCCESS\n"); + break; + case BT_OP_STATUS_VERSION_MISMATCH: + retStatus = BT_STATUS_OPCODE_L_VERSION_MISMATCH; + DBG_8192C("[MPT], BT status : BT_STATUS_OPCODE_L_VERSION_MISMATCH\n"); + break; + case BT_OP_STATUS_UNKNOWN_OPCODE: + retStatus = BT_STATUS_UNKNOWN_OPCODE_L; + DBG_8192C("[MPT], BT status : BT_STATUS_UNKNOWN_OPCODE_L\n"); + break; + case BT_OP_STATUS_ERROR_PARAMETER: + retStatus = BT_STATUS_PARAMETER_FORMAT_ERROR_L; + DBG_8192C("[MPT], BT status : BT_STATUS_PARAMETER_FORMAT_ERROR_L\n"); + break; + default: + retStatus = BT_STATUS_UNKNOWN_STATUS_L; + DBG_8192C("[MPT], BT status : BT_STATUS_UNKNOWN_STATUS_L\n"); + break; + } + + return retStatus; +} + + + +BT_CTRL_STATUS +mptbt_BtFwOpCodeProcess( + PADAPTER Adapter, + u1Byte btFwOpCode, + u1Byte opCodeVer, + pu1Byte pH2cPar, + u1Byte h2cParaLen + ) +{ + u1Byte H2C_Parameter[6] ={0}; + PBT_H2C pH2c=(PBT_H2C)&H2C_Parameter[0]; + PMPT_CONTEXT pMptCtx=&(Adapter->mppriv.MptCtx); + PBT_EXT_C2H pExtC2h=(PBT_EXT_C2H)&pMptCtx->c2hBuf[0]; + u2Byte paraLen=0,i; + BT_CTRL_STATUS h2cStatus=BT_STATUS_H2C_SUCCESS, c2hStatus=BT_STATUS_C2H_SUCCESS; + BT_CTRL_STATUS retStatus=BT_STATUS_H2C_BT_NO_RSP; + + if( Adapter->registrypriv.mp_mode == 0 ) + { + DBG_8192C("[MPT], Error!! mptbt_BtFwOpCodeProces mp_mode == 0!!\n"); + return _FALSE; + } + + pH2c->opCode = btFwOpCode; + pH2c->opCodeVer = opCodeVer; + pH2c->reqNum = pMptCtx->h2cReqNum; + //PlatformMoveMemory(&pH2c->buf[0], pH2cPar, h2cParaLen); + //_rtw_memcpy(&pH2c->buf[0], pH2cPar, h2cParaLen); + _rtw_memcpy(pH2c->buf, pH2cPar, h2cParaLen); + + DBG_8192C("[MPT], pH2c->opCode=%d\n", pH2c->opCode); + DBG_8192C("[MPT], pH2c->opCodeVer=%d\n", pH2c->opCodeVer); + DBG_8192C("[MPT], pH2c->reqNum=%d\n", pH2c->reqNum); + DBG_8192C("[MPT], h2c parameter length=%d\n", h2cParaLen); + for (i=0; ibuf[i]); + } + + h2cStatus = mptbt_SendH2c(Adapter, pH2c, h2cParaLen+2); + if(BT_STATUS_H2C_SUCCESS == h2cStatus) + { + // if reach here, it means H2C get the correct c2h response, + c2hStatus = mptbt_CheckC2hFrame(Adapter, pH2c, pExtC2h); + if(BT_STATUS_C2H_SUCCESS == c2hStatus) + { + retStatus = mptbt_CheckBtRspStatus(Adapter, pExtC2h); + } + else + { + DBG_8192C("[MPT], Error!! C2H failed for pH2c->opCode=%d\n", pH2c->opCode); + // check c2h status error, return error status code to upper layer. + retStatus = c2hStatus; + } + } + else + { + DBG_8192C("[MPT], Error!! H2C failed for pH2c->opCode=%d\n", pH2c->opCode); + // check h2c status error, return error status code to upper layer. + retStatus = h2cStatus; + } + + return retStatus; +} + + + + +u2Byte +mptbt_BtReady( + PADAPTER Adapter, + PBT_REQ_CMD pBtReq, + PBT_RSP_CMD pBtRsp + ) +{ + u1Byte h2cParaBuf[6] ={0}; + u1Byte h2cParaLen=0; + u2Byte paraLen=0; + u1Byte retStatus=BT_STATUS_BT_OP_SUCCESS; + u1Byte btOpcode; + u1Byte btOpcodeVer=0; + PMPT_CONTEXT pMptCtx=&(Adapter->mppriv.MptCtx); + PBT_EXT_C2H pExtC2h=(PBT_EXT_C2H)&pMptCtx->c2hBuf[0]; + u1Byte i; + u1Byte btFwVer=0, bdAddr[6]={0}; + u2Byte btRealFwVer=0; + pu2Byte pu2Tmp=NULL; + + // + // check upper layer parameters + // + + // 1. check upper layer opcode version + if(pBtReq->opCodeVer != 1) + { + DBG_8192C("[MPT], Error!! Upper OP code version not match!!!\n"); + pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH; + return paraLen; + } + + pBtRsp->pParamStart[0] = MP_BT_NOT_READY; + paraLen = 10; + // + // execute lower layer opcodes + // + + // Get BT FW version + // fill h2c parameters + btOpcode = BT_LO_OP_GET_BT_VERSION; + // execute h2c and check respond c2h from bt fw is correct or not + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + // ckeck bt return status. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + else + { + pu2Tmp = (pu2Byte)&pExtC2h->buf[0]; + btRealFwVer = *pu2Tmp; + btFwVer = pExtC2h->buf[1]; + DBG_8192C("[MPT], btRealFwVer=0x%x, btFwVer=0x%x\n", btRealFwVer, btFwVer); + } + + // Get BD Address + // fill h2c parameters + btOpcode = BT_LO_OP_GET_BD_ADDR_L; + // execute h2c and check respond c2h from bt fw is correct or not + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + // ckeck bt return status. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + else + { + bdAddr[5] = pExtC2h->buf[0]; + bdAddr[4] = pExtC2h->buf[1]; + bdAddr[3] = pExtC2h->buf[2]; + } + + // fill h2c parameters + btOpcode = BT_LO_OP_GET_BD_ADDR_H; + // execute h2c and check respond c2h from bt fw is correct or not + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + // ckeck bt return status. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + else + { + bdAddr[2] = pExtC2h->buf[0]; + bdAddr[1] = pExtC2h->buf[1]; + bdAddr[0] = pExtC2h->buf[2]; + } + DBG_8192C("[MPT], Local BDAddr:"); + for(i=0; i<6; i++) + { + DBG_8192C(" 0x%x ", bdAddr[i]); + } + pBtRsp->status = BT_STATUS_SUCCESS; + pBtRsp->pParamStart[0] = MP_BT_READY; + pu2Tmp = (pu2Byte)&pBtRsp->pParamStart[1]; + *pu2Tmp = btRealFwVer; + pBtRsp->pParamStart[3] = btFwVer; + for(i=0; i<6; i++) + { + pBtRsp->pParamStart[4+i] = bdAddr[5-i]; + } + + return paraLen; +} + +void mptbt_close_WiFiRF(PADAPTER Adapter) +{ + PHY_SetBBReg(Adapter, 0x824, 0xF, 0x0); + PHY_SetBBReg(Adapter, 0x824, 0x700000, 0x0); + PHY_SetRFReg(Adapter, RF_PATH_A, 0x0, 0xF0000, 0x0); +} + +void mptbt_open_WiFiRF(PADAPTER Adapter) +{ + PHY_SetBBReg(Adapter, 0x824, 0x700000, 0x3); + PHY_SetBBReg(Adapter, 0x824, 0xF, 0x2); + PHY_SetRFReg(Adapter, RF_PATH_A, 0x0, 0xF0000, 0x3); +} + +u4Byte mptbt_switch_RF(PADAPTER Adapter, u1Byte Enter) +{ + u2Byte tmp_2byte = 0; + + //Enter test mode + if (Enter) { + ////1>. close WiFi RF + mptbt_close_WiFiRF(Adapter); + + ////2>. change ant switch to BT + tmp_2byte = rtw_read16(Adapter, 0x860); + tmp_2byte = tmp_2byte | BIT(9); + tmp_2byte = tmp_2byte & (~BIT(8)); + rtw_write16(Adapter, 0x860, tmp_2byte); + rtw_write16(Adapter, 0x870, 0x300); + } else { + ////1>. Open WiFi RF + mptbt_open_WiFiRF(Adapter); + + ////2>. change ant switch back + tmp_2byte = rtw_read16(Adapter, 0x860); + tmp_2byte = tmp_2byte | BIT(8); + tmp_2byte = tmp_2byte & (~BIT(9)); + rtw_write16(Adapter, 0x860, tmp_2byte); + rtw_write16(Adapter, 0x870, 0x300); + } + + return 0; +} + +u2Byte +mptbt_BtSetMode( + PADAPTER Adapter, + PBT_REQ_CMD pBtReq, + PBT_RSP_CMD pBtRsp + ) +{ + u1Byte h2cParaBuf[6] ={0}; + u1Byte h2cParaLen=0; + u2Byte paraLen=0; + u1Byte retStatus=BT_STATUS_BT_OP_SUCCESS; + u1Byte btOpcode; + u1Byte btOpcodeVer=0; + u1Byte btModeToSet=0; + + // + // check upper layer parameters + // + // 1. check upper layer opcode version + if(pBtReq->opCodeVer != 1) + { + DBG_8192C("[MPT], Error!! Upper OP code version not match!!!\n"); + pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH; + return paraLen; + } + // 2. check upper layer parameter length + if(1 == pBtReq->paraLength) + { + btModeToSet = pBtReq->pParamStart[0]; + DBG_8192C("[MPT], BtTestMode=%d \n", btModeToSet); + } + else + { + DBG_8192C("[MPT], Error!! wrong parameter length=%d (should be 1)\n", pBtReq->paraLength); + pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U; + return paraLen; + } + + // + // execute lower layer opcodes + // + + // 1. fill h2c parameters + // check bt mode + btOpcode = BT_LO_OP_SET_BT_MODE; + if(btModeToSet >= MP_BT_MODE_MAX) + { + pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U; + return paraLen; + } + else + { + mptbt_switch_RF(Adapter, 1); + + h2cParaBuf[0] = btModeToSet; + h2cParaLen = 1; + // 2. execute h2c and check respond c2h from bt fw is correct or not + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + } + + // 3. construct respond status code and data. + if(BT_STATUS_BT_OP_SUCCESS == retStatus) + { + pBtRsp->status = BT_STATUS_SUCCESS; + } + else + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + } + + return paraLen; +} + + +VOID +MPTBT_FwC2hBtMpCtrl( + PADAPTER Adapter, + pu1Byte tmpBuf, + u1Byte length + ) +{ + u32 i; + PMPT_CONTEXT pMptCtx=&(Adapter->mppriv.MptCtx); + PBT_EXT_C2H pExtC2h=(PBT_EXT_C2H)tmpBuf; + + if(Adapter->bBTFWReady == _FALSE || Adapter->registrypriv.mp_mode == 0 ) + { + //DBG_8192C("Ignore C2H BT MP Info since not in MP mode \n"); + return; + } + if( length > 32 || length < 3 ) + { + DBG_8192C("\n [MPT], pExtC2h->buf hex: length=%d > 32 || < 3\n",length); + return; + } + + //cancel_timeout for h2c handle + _cancel_timer_ex(&pMptCtx->MPh2c_timeout_timer); + + for (i=0; iextendId=0x%x\n", pExtC2h->extendId); + + switch(pExtC2h->extendId) + { + case EXT_C2H_WIFI_FW_ACTIVE_RSP: + DBG_8192C("[MPT], EXT_C2H_WIFI_FW_ACTIVE_RSP\n"); +#if 0 + DBG_8192C("[MPT], pExtC2h->buf hex: \n"); + for (i=0; i<(length-3); i++) + { + DBG_8192C(" 0x%x ", pExtC2h->buf[i]); + } +#endif + if ((_FALSE == pMptCtx->bMPh2c_timeout) + && (_FALSE == pMptCtx->MptH2cRspEvent)) + { + pMptCtx->MptH2cRspEvent = _TRUE; + _rtw_up_sema(&pMptCtx->MPh2c_Sema); + } + break; + + case EXT_C2H_TRIG_BY_BT_FW: + DBG_8192C("[MPT], EXT_C2H_TRIG_BY_BT_FW\n"); + _rtw_memcpy(&pMptCtx->c2hBuf[0], tmpBuf, length); + DBG_8192C("[MPT], pExtC2h->statusCode=0x%x\n", pExtC2h->statusCode); + DBG_8192C("[MPT], pExtC2h->retLen=0x%x\n", pExtC2h->retLen); + DBG_8192C("[MPT], pExtC2h->opCodeVer=0x%x\n", pExtC2h->opCodeVer); + DBG_8192C("[MPT], pExtC2h->reqNum=0x%x\n", pExtC2h->reqNum); + for (i=0; i<(length-3); i++) + { + DBG_8192C("[MPT], pExtC2h->buf[%d]=0x%02x\n", i, pExtC2h->buf[i]); + } + + if ((_FALSE == pMptCtx->bMPh2c_timeout) + && (_TRUE == pMptCtx->MptH2cRspEvent) + && (_FALSE == pMptCtx->MptBtC2hEvent)) + { + pMptCtx->MptBtC2hEvent = _TRUE; + _rtw_up_sema(&pMptCtx->MPh2c_Sema); + } + break; + + default: + DBG_8192C("[MPT], EXT_C2H Target not found,pExtC2h->extendId =%d ,pExtC2h->reqNum=%d\n",pExtC2h->extendId,pExtC2h->reqNum); + break; + } + + + +} + + +u2Byte +mptbt_BtGetGeneral( + IN PADAPTER Adapter, + IN PBT_REQ_CMD pBtReq, + IN PBT_RSP_CMD pBtRsp + ) +{ + PMPT_CONTEXT pMptCtx=&(Adapter->mppriv.MptCtx); + PBT_EXT_C2H pExtC2h=(PBT_EXT_C2H)&pMptCtx->c2hBuf[0]; + u1Byte h2cParaBuf[6] ={0}; + u1Byte h2cParaLen=0; + u2Byte paraLen=0; + u1Byte retStatus=BT_STATUS_BT_OP_SUCCESS; + u1Byte btOpcode, bdAddr[6]={0}; + u1Byte btOpcodeVer=0; + u1Byte getType=0, i; + u2Byte getParaLen=0, validParaLen=0; + u1Byte regType=0, reportType=0; + u4Byte regAddr=0, regValue=0; + pu4Byte pu4Tmp; + pu2Byte pu2Tmp; + pu1Byte pu1Tmp; + + // + // check upper layer parameters + // + + // check upper layer opcode version + if(pBtReq->opCodeVer != 1) + { + DBG_8192C("[MPT], Error!! Upper OP code version not match!!!\n"); + pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH; + return paraLen; + } + // check upper layer parameter length + if(pBtReq->paraLength < 1) + { + DBG_8192C("[MPT], Error!! wrong parameter length=%d (should larger than 1)\n", pBtReq->paraLength); + pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U; + return paraLen; + } + getParaLen = pBtReq->paraLength - 1; + getType = pBtReq->pParamStart[0]; + + DBG_8192C("[MPT], getType=%d, getParaLen=%d\n", getType, getParaLen); + + // check parameter first + switch(getType) + { + case BT_GGET_REG: + DBG_8192C("[MPT], [BT_GGET_REG]\n"); + validParaLen = 5; + if(getParaLen == validParaLen) + { + btOpcode = BT_LO_OP_READ_REG; + regType = pBtReq->pParamStart[1]; + pu4Tmp = (pu4Byte)&pBtReq->pParamStart[2]; + regAddr = *pu4Tmp; + DBG_8192C("[MPT], BT_GGET_REG regType=0x%02x, regAddr=0x%08x!!\n", + regType, regAddr); + if(regType >= BT_REG_MAX) + { + pBtRsp->status = (btOpcode<<8)| BT_STATUS_PARAMETER_OUT_OF_RANGE_U; + return paraLen; + } + else + { + if( ((BT_REG_RF==regType)&&(regAddr>0x7f)) || + ((BT_REG_MODEM==regType)&&(regAddr>0x1ff)) || + ((BT_REG_BLUEWIZE==regType)&&(regAddr>0xfff)) || + ((BT_REG_VENDOR==regType)&&(regAddr>0xfff)) || + ((BT_REG_LE==regType)&&(regAddr>0xfff)) ) + { + pBtRsp->status = (btOpcode<<8)| BT_STATUS_PARAMETER_OUT_OF_RANGE_U; + return paraLen; + } + } + } + break; + case BT_GGET_STATUS: + DBG_8192C("[MPT], [BT_GGET_STATUS]\n"); + validParaLen = 0; + break; + case BT_GGET_REPORT: + DBG_8192C("[MPT], [BT_GGET_REPORT]\n"); + validParaLen = 1; + if(getParaLen == validParaLen) + { + reportType = pBtReq->pParamStart[1]; + DBG_8192C("[MPT], BT_GGET_REPORT reportType=0x%x!!\n", reportType); + if(reportType >= BT_REPORT_MAX) + { + pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U; + return paraLen; + } + } + break; + default: + { + DBG_8192C("[MPT], Error!! getType=%d, out of range\n", getType); + pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U; + return paraLen; + } + break; + } + if(getParaLen != validParaLen) + { + DBG_8192C("[MPT], Error!! wrong parameter length=%d for BT_GET_GEN_CMD cmd id=0x%x, paraLen should=0x%x\n", + getParaLen, getType, validParaLen); + pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U; + return paraLen; + } + + // + // execute lower layer opcodes + // + if(BT_GGET_REG == getType) + { + // fill h2c parameters + // here we should write reg value first then write the address, adviced by Austin + btOpcode = BT_LO_OP_READ_REG; + h2cParaBuf[0] = regType; + h2cParaBuf[1] = pBtReq->pParamStart[2]; + h2cParaBuf[2] = pBtReq->pParamStart[3]; + h2cParaLen = 3; + // execute h2c and check respond c2h from bt fw is correct or not + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + // construct respond status code and data. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + + pu2Tmp = (pu2Byte)&pExtC2h->buf[0]; + regValue = *pu2Tmp; + DBG_8192C("[MPT], read reg regType=0x%02x, regAddr=0x%08x, regValue=0x%04x\n", + regType, regAddr, regValue); + + pu4Tmp = (pu4Byte)&pBtRsp->pParamStart[0]; + *pu4Tmp = regValue; + paraLen = 4; + } + else if(BT_GGET_STATUS == getType) + { + btOpcode = BT_LO_OP_GET_BT_STATUS; + h2cParaLen = 0; + // execute h2c and check respond c2h from bt fw is correct or not + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + // construct respond status code and data. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + + pBtRsp->pParamStart[0] = pExtC2h->buf[0]; + pBtRsp->pParamStart[1] = pExtC2h->buf[1]; + DBG_8192C("[MPT], read bt status, testMode=0x%x, testStatus=0x%x\n", + pBtRsp->pParamStart[0], pBtRsp->pParamStart[1]); + paraLen = 2; + } + else if(BT_GGET_REPORT == getType) + { + switch(reportType) + { + case BT_REPORT_RX_PACKET_CNT: + { + DBG_8192C("[MPT], [Rx Packet Counts]\n"); + btOpcode = BT_LO_OP_GET_RX_PKT_CNT_L; + h2cParaLen = 0; + // execute h2c and check respond c2h from bt fw is correct or not + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + // construct respond status code and data. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + pBtRsp->pParamStart[0] = pExtC2h->buf[0]; + pBtRsp->pParamStart[1] = pExtC2h->buf[1]; + + btOpcode = BT_LO_OP_GET_RX_PKT_CNT_H; + h2cParaLen = 0; + // execute h2c and check respond c2h from bt fw is correct or not + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + // construct respond status code and data. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + pBtRsp->pParamStart[2] = pExtC2h->buf[0]; + pBtRsp->pParamStart[3] = pExtC2h->buf[1]; + paraLen = 4; + } + break; + case BT_REPORT_RX_ERROR_BITS: + { + DBG_8192C("[MPT], [Rx Error Bits]\n"); + btOpcode = BT_LO_OP_GET_RX_ERROR_BITS_L; + h2cParaLen = 0; + // execute h2c and check respond c2h from bt fw is correct or not + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + // construct respond status code and data. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + pBtRsp->pParamStart[0] = pExtC2h->buf[0]; + pBtRsp->pParamStart[1] = pExtC2h->buf[1]; + + btOpcode = BT_LO_OP_GET_RX_ERROR_BITS_H; + h2cParaLen = 0; + // execute h2c and check respond c2h from bt fw is correct or not + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + // construct respond status code and data. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + pBtRsp->pParamStart[2] = pExtC2h->buf[0]; + pBtRsp->pParamStart[3] = pExtC2h->buf[1]; + paraLen = 4; + } + break; + case BT_REPORT_RSSI: + { + DBG_8192C("[MPT], [RSSI]\n"); + btOpcode = BT_LO_OP_GET_RSSI; + h2cParaLen = 0; + // execute h2c and check respond c2h from bt fw is correct or not + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + // construct respond status code and data. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + pBtRsp->pParamStart[0] = pExtC2h->buf[0]; + pBtRsp->pParamStart[1] = pExtC2h->buf[1]; + paraLen = 2; + } + break; + case BT_REPORT_CFO_HDR_QUALITY: + { + DBG_8192C("[MPT], [CFO & Header Quality]\n"); + btOpcode = BT_LO_OP_GET_CFO_HDR_QUALITY_L; + h2cParaLen = 0; + // execute h2c and check respond c2h from bt fw is correct or not + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + // construct respond status code and data. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + pBtRsp->pParamStart[0] = pExtC2h->buf[0]; + pBtRsp->pParamStart[1] = pExtC2h->buf[1]; + + btOpcode = BT_LO_OP_GET_CFO_HDR_QUALITY_H; + h2cParaLen = 0; + // execute h2c and check respond c2h from bt fw is correct or not + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + // construct respond status code and data. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + pBtRsp->pParamStart[2] = pExtC2h->buf[0]; + pBtRsp->pParamStart[3] = pExtC2h->buf[1]; + paraLen = 4; + } + break; + case BT_REPORT_CONNECT_TARGET_BD_ADDR: + { + DBG_8192C("[MPT], [Connected Target BD ADDR]\n"); + btOpcode = BT_LO_OP_GET_TARGET_BD_ADDR_L; + h2cParaLen = 0; + // execute h2c and check respond c2h from bt fw is correct or not + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + // construct respond status code and data. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + bdAddr[5] = pExtC2h->buf[0]; + bdAddr[4] = pExtC2h->buf[1]; + bdAddr[3] = pExtC2h->buf[2]; + + btOpcode = BT_LO_OP_GET_TARGET_BD_ADDR_H; + h2cParaLen = 0; + // execute h2c and check respond c2h from bt fw is correct or not + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + // construct respond status code and data. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + bdAddr[2] = pExtC2h->buf[0]; + bdAddr[1] = pExtC2h->buf[1]; + bdAddr[0] = pExtC2h->buf[2]; + + DBG_8192C("[MPT], Connected Target BDAddr:%s", bdAddr); + for(i=0; i<6; i++) + { + pBtRsp->pParamStart[i] = bdAddr[5-i]; + } + paraLen = 6; + } + break; + default: + pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U; + return paraLen; + break; + } + } + + pBtRsp->status = BT_STATUS_SUCCESS; + return paraLen; +} + + + +u2Byte +mptbt_BtSetGeneral( + IN PADAPTER Adapter, + IN PBT_REQ_CMD pBtReq, + IN PBT_RSP_CMD pBtRsp + ) +{ + u1Byte h2cParaBuf[6] ={0}; + u1Byte h2cParaLen=0; + u2Byte paraLen=0; + u1Byte retStatus=BT_STATUS_BT_OP_SUCCESS; + u1Byte btOpcode; + u1Byte btOpcodeVer=0; + u1Byte setType=0; + u2Byte setParaLen=0, validParaLen=0; + u1Byte regType=0, bdAddr[6]={0}, calVal=0; + u4Byte regAddr=0, regValue=0; + pu4Byte pu4Tmp; + pu2Byte pu2Tmp; + pu1Byte pu1Tmp; + + // + // check upper layer parameters + // + + // check upper layer opcode version + if(pBtReq->opCodeVer != 1) + { + DBG_8192C("[MPT], Error!! Upper OP code version not match!!!\n"); + pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH; + return paraLen; + } + // check upper layer parameter length + if(pBtReq->paraLength < 1) + { + DBG_8192C("[MPT], Error!! wrong parameter length=%d (should larger than 1)\n", pBtReq->paraLength); + pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U; + return paraLen; + } + setParaLen = pBtReq->paraLength - 1; + setType = pBtReq->pParamStart[0]; + + DBG_8192C("[MPT], setType=%d, setParaLen=%d\n", setType, setParaLen); + + // check parameter first + switch(setType) + { + case BT_GSET_REG: + DBG_8192C ("[MPT], [BT_GSET_REG]\n"); + validParaLen = 9; + if(setParaLen == validParaLen) + { + btOpcode = BT_LO_OP_WRITE_REG_VALUE; + regType = pBtReq->pParamStart[1]; + pu4Tmp = (pu4Byte)&pBtReq->pParamStart[2]; + regAddr = *pu4Tmp; + pu4Tmp = (pu4Byte)&pBtReq->pParamStart[6]; + regValue = *pu4Tmp; + DBG_8192C("[MPT], BT_GSET_REG regType=0x%x, regAddr=0x%x, regValue=0x%x!!\n", + regType, regAddr, regValue); + if(regType >= BT_REG_MAX) + { + pBtRsp->status = (btOpcode<<8)| BT_STATUS_PARAMETER_OUT_OF_RANGE_U; + return paraLen; + } + else + { + if( ((BT_REG_RF==regType)&&(regAddr>0x7f)) || + ((BT_REG_MODEM==regType)&&(regAddr>0x1ff)) || + ((BT_REG_BLUEWIZE==regType)&&(regAddr>0xfff)) || + ((BT_REG_VENDOR==regType)&&(regAddr>0xfff)) || + ((BT_REG_LE==regType)&&(regAddr>0xfff)) ) + { + pBtRsp->status = (btOpcode<<8)| BT_STATUS_PARAMETER_OUT_OF_RANGE_U; + return paraLen; + } + } + } + break; + case BT_GSET_RESET: + DBG_8192C("[MPT], [BT_GSET_RESET]\n"); + validParaLen = 0; + break; + case BT_GSET_TARGET_BD_ADDR: + DBG_8192C("[MPT], [BT_GSET_TARGET_BD_ADDR]\n"); + validParaLen = 6; + if(setParaLen == validParaLen) + { + btOpcode = BT_LO_OP_SET_TARGET_BD_ADDR_H; + if( (pBtReq->pParamStart[1]==0) && + (pBtReq->pParamStart[2]==0) && + (pBtReq->pParamStart[3]==0) && + (pBtReq->pParamStart[4]==0) && + (pBtReq->pParamStart[5]==0) && + (pBtReq->pParamStart[6]==0) ) + { + DBG_8192C("[MPT], Error!! targetBDAddr=all zero\n"); + pBtRsp->status = (btOpcode<<8)|BT_STATUS_PARAMETER_OUT_OF_RANGE_U; + return paraLen; + } + if( (pBtReq->pParamStart[1]==0xff) && + (pBtReq->pParamStart[2]==0xff) && + (pBtReq->pParamStart[3]==0xff) && + (pBtReq->pParamStart[4]==0xff) && + (pBtReq->pParamStart[5]==0xff) && + (pBtReq->pParamStart[6]==0xff) ) + { + DBG_8192C("[MPT], Error!! targetBDAddr=all 0xf\n"); + pBtRsp->status = (btOpcode<<8)|BT_STATUS_PARAMETER_OUT_OF_RANGE_U; + return paraLen; + } + bdAddr[0] = pBtReq->pParamStart[6]; + bdAddr[1] = pBtReq->pParamStart[5]; + bdAddr[2] = pBtReq->pParamStart[4]; + bdAddr[3] = pBtReq->pParamStart[3]; + bdAddr[4] = pBtReq->pParamStart[2]; + bdAddr[5] = pBtReq->pParamStart[1]; + DBG_8192C ("[MPT], target BDAddr:%x,%x,%x,%x,%x,%x\n", + bdAddr[0],bdAddr[1],bdAddr[2],bdAddr[3],bdAddr[4],bdAddr[5]); + } + break; + case BT_GSET_TX_PWR_FINETUNE: + DBG_8192C("[MPT], [BT_GSET_TX_PWR_FINETUNE]\n"); + validParaLen = 1; + if(setParaLen == validParaLen) + { + btOpcode = BT_LO_OP_SET_TX_POWER_CALIBRATION; + calVal = pBtReq->pParamStart[1]; + if( (calVal<1) || (calVal>9) ) + { + pBtRsp->status = (btOpcode<<8)|BT_STATUS_PARAMETER_OUT_OF_RANGE_U; + return paraLen; + } + DBG_8192C ("[MPT], calVal=%d\n", calVal); + } + break; + case BT_SET_TRACKING_INTERVAL: + DBG_871X("[MPT], [BT_SET_TRACKING_INTERVAL] setParaLen =%d \n",setParaLen); + + validParaLen = 1; + if(setParaLen == validParaLen) + calVal = pBtReq->pParamStart[1]; + break; + case BT_SET_THERMAL_METER: + DBG_871X("[MPT], [BT_SET_THERMAL_METER] setParaLen =%d \n",setParaLen); + validParaLen = 1; + if(setParaLen == validParaLen) + calVal = pBtReq->pParamStart[1]; + break; + case BT_ENABLE_CFO_TRACKING: + DBG_871X("[MPT], [BT_ENABLE_CFO_TRACKING] setParaLen =%d \n",setParaLen); + validParaLen = 1; + if(setParaLen == validParaLen) + calVal = pBtReq->pParamStart[1]; + break; + case BT_GSET_UPDATE_BT_PATCH: + + break; + default: + { + DBG_8192C ("[MPT], Error!! setType=%d, out of range\n", setType); + pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U; + return paraLen; + } + break; + } + if(setParaLen != validParaLen) + { + DBG_8192C("[MPT], Error!! wrong parameter length=%d for BT_SET_GEN_CMD cmd id=0x%x, paraLen should=0x%x\n", + setParaLen, setType, validParaLen); + pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U; + return paraLen; + } + + // + // execute lower layer opcodes + // + if(BT_GSET_REG == setType) + { + // fill h2c parameters + // here we should write reg value first then write the address, adviced by Austin + btOpcode = BT_LO_OP_WRITE_REG_VALUE; + h2cParaBuf[0] = pBtReq->pParamStart[6]; + h2cParaBuf[1] = pBtReq->pParamStart[7]; + h2cParaBuf[2] = pBtReq->pParamStart[8]; + h2cParaLen = 3; + // execute h2c and check respond c2h from bt fw is correct or not + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + // construct respond status code and data. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + + // write reg address + btOpcode = BT_LO_OP_WRITE_REG_ADDR; + h2cParaBuf[0] = regType; + h2cParaBuf[1] = pBtReq->pParamStart[2]; + h2cParaBuf[2] = pBtReq->pParamStart[3]; + h2cParaLen = 3; + // execute h2c and check respond c2h from bt fw is correct or not + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + // construct respond status code and data. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + } + else if(BT_GSET_RESET == setType) + { + btOpcode = BT_LO_OP_RESET; + h2cParaLen = 0; + // execute h2c and check respond c2h from bt fw is correct or not + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + // construct respond status code and data. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + } + else if(BT_GSET_TARGET_BD_ADDR == setType) + { + // fill h2c parameters + btOpcode = BT_LO_OP_SET_TARGET_BD_ADDR_L; + h2cParaBuf[0] = pBtReq->pParamStart[1]; + h2cParaBuf[1] = pBtReq->pParamStart[2]; + h2cParaBuf[2] = pBtReq->pParamStart[3]; + h2cParaLen = 3; + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + // ckeck bt return status. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C ("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + + btOpcode = BT_LO_OP_SET_TARGET_BD_ADDR_H; + h2cParaBuf[0] = pBtReq->pParamStart[4]; + h2cParaBuf[1] = pBtReq->pParamStart[5]; + h2cParaBuf[2] = pBtReq->pParamStart[6]; + h2cParaLen = 3; + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + // ckeck bt return status. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C ("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + } + else if(BT_GSET_TX_PWR_FINETUNE == setType) + { + // fill h2c parameters + btOpcode = BT_LO_OP_SET_TX_POWER_CALIBRATION; + h2cParaBuf[0] = calVal; + h2cParaLen = 1; + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + // ckeck bt return status. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + } + else if(BT_SET_TRACKING_INTERVAL == setType) + { + // BT_LO_OP_SET_TRACKING_INTERVAL = 0x22, + // BT_LO_OP_SET_THERMAL_METER = 0x23, + // BT_LO_OP_ENABLE_CFO_TRACKING = 0x24, + btOpcode = BT_LO_OP_SET_TRACKING_INTERVAL; + h2cParaBuf[0] = calVal; + h2cParaLen = 1; + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + // ckeck bt return status. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C ("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + } + else if(BT_SET_THERMAL_METER == setType) + { + btOpcode = BT_LO_OP_SET_THERMAL_METER; + h2cParaBuf[0] = calVal; + h2cParaLen = 1; + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + // ckeck bt return status. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C ("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + } + else if(BT_ENABLE_CFO_TRACKING == setType) + { + btOpcode = BT_LO_OP_ENABLE_CFO_TRACKING; + h2cParaBuf[0] = calVal; + h2cParaLen = 1; + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + // ckeck bt return status. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C ("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + } + + pBtRsp->status = BT_STATUS_SUCCESS; + return paraLen; +} + + + +u2Byte +mptbt_BtSetTxRxPars( + IN PADAPTER Adapter, + IN PBT_REQ_CMD pBtReq, + IN PBT_RSP_CMD pBtRsp + ) +{ + u1Byte h2cParaBuf[6] ={0}; + u1Byte h2cParaLen=0; + u2Byte paraLen=0; + u1Byte retStatus=BT_STATUS_BT_OP_SUCCESS; + u1Byte btOpcode; + u1Byte btOpcodeVer=0; + PBT_TXRX_PARAMETERS pTxRxPars=(PBT_TXRX_PARAMETERS)&pBtReq->pParamStart[0]; + u2Byte lenTxRx=sizeof(BT_TXRX_PARAMETERS); + u1Byte i; + u1Byte bdAddr[6]={0}; + + // + // check upper layer parameters + // + + // 1. check upper layer opcode version + if(pBtReq->opCodeVer != 1) + { + DBG_8192C("[MPT], Error!! Upper OP code version not match!!!\n"); + pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH; + return paraLen; + } + // 2. check upper layer parameter length + if(pBtReq->paraLength == sizeof(BT_TXRX_PARAMETERS)) + { + DBG_8192C ("[MPT], pTxRxPars->txrxChannel=0x%x \n", pTxRxPars->txrxChannel); + DBG_8192C ("[MPT], pTxRxPars->txrxTxPktCnt=0x%8x \n", pTxRxPars->txrxTxPktCnt); + DBG_8192C ("[MPT], pTxRxPars->txrxTxPktInterval=0x%x \n", pTxRxPars->txrxTxPktInterval); + DBG_8192C ("[MPT], pTxRxPars->txrxPayloadType=0x%x \n", pTxRxPars->txrxPayloadType); + DBG_8192C ("[MPT], pTxRxPars->txrxPktType=0x%x \n", pTxRxPars->txrxPktType); + DBG_8192C ("[MPT], pTxRxPars->txrxPayloadLen=0x%x \n", pTxRxPars->txrxPayloadLen); + DBG_8192C ("[MPT], pTxRxPars->txrxPktHeader=0x%x \n", pTxRxPars->txrxPktHeader); + DBG_8192C ("[MPT], pTxRxPars->txrxWhitenCoeff=0x%x \n", pTxRxPars->txrxWhitenCoeff); + bdAddr[0] = pTxRxPars->txrxBdaddr[5]; + bdAddr[1] = pTxRxPars->txrxBdaddr[4]; + bdAddr[2] = pTxRxPars->txrxBdaddr[3]; + bdAddr[3] = pTxRxPars->txrxBdaddr[2]; + bdAddr[4] = pTxRxPars->txrxBdaddr[1]; + bdAddr[5] = pTxRxPars->txrxBdaddr[0]; + DBG_8192C ("[MPT], pTxRxPars->txrxBdaddr: %s", &bdAddr[0]); + DBG_8192C ("[MPT], pTxRxPars->txrxTxGainIndex=0x%x \n", pTxRxPars->txrxTxGainIndex); + } + else + { + DBG_8192C ("[MPT], Error!! pBtReq->paraLength=%d, correct Len=%d\n", pBtReq->paraLength, lenTxRx); + pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U; + return paraLen; + } + + // + // execute lower layer opcodes + // + + // fill h2c parameters + btOpcode = BT_LO_OP_SET_PKT_HEADER; + if(pTxRxPars->txrxPktHeader > 0x3ffff) + { + DBG_8192C ("[MPT], Error!! pTxRxPars->txrxPktHeader=0x%x is out of range, (should be between 0x0~0x3ffff)\n", pTxRxPars->txrxPktHeader); + pBtRsp->status = (btOpcode<<8)|BT_STATUS_PARAMETER_OUT_OF_RANGE_U; + return paraLen; + } + else + { + h2cParaBuf[0] = (u1Byte)(pTxRxPars->txrxPktHeader&0xff); + h2cParaBuf[1] = (u1Byte)((pTxRxPars->txrxPktHeader&0xff00)>>8); + h2cParaBuf[2] = (u1Byte)((pTxRxPars->txrxPktHeader&0xff0000)>>16); + h2cParaLen = 3; + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + } + + // ckeck bt return status. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C ("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + + // fill h2c parameters + btOpcode = BT_LO_OP_SET_PKT_TYPE_LEN; + { + u2Byte payloadLenLimit=0; + switch(pTxRxPars->txrxPktType) + { + case MP_BT_PKT_DH1: + payloadLenLimit = 27*8; + break; + case MP_BT_PKT_DH3: + payloadLenLimit = 183*8; + break; + case MP_BT_PKT_DH5: + payloadLenLimit = 339*8; + break; + case MP_BT_PKT_2DH1: + payloadLenLimit = 54*8; + break; + case MP_BT_PKT_2DH3: + payloadLenLimit = 367*8; + break; + case MP_BT_PKT_2DH5: + payloadLenLimit = 679*8; + break; + case MP_BT_PKT_3DH1: + payloadLenLimit = 83*8; + break; + case MP_BT_PKT_3DH3: + payloadLenLimit = 552*8; + break; + case MP_BT_PKT_3DH5: + payloadLenLimit = 1021*8; + break; + case MP_BT_PKT_LE: + payloadLenLimit = 39*8; + break; + default: + { + DBG_8192C ("[MPT], Error!! Unknown pTxRxPars->txrxPktType=0x%x\n", pTxRxPars->txrxPktType); + pBtRsp->status = (btOpcode<<8)|BT_STATUS_PARAMETER_OUT_OF_RANGE_U; + return paraLen; + } + break; + } + + if(pTxRxPars->txrxPayloadLen > payloadLenLimit) + { + DBG_8192C ("[MPT], Error!! pTxRxPars->txrxPayloadLen=0x%x, (should smaller than %d)\n", + pTxRxPars->txrxPayloadLen, payloadLenLimit); + pBtRsp->status = (btOpcode<<8)|BT_STATUS_PARAMETER_OUT_OF_RANGE_U; + return paraLen; + } + + h2cParaBuf[0] = pTxRxPars->txrxPktType; + h2cParaBuf[1] = (u1Byte)((pTxRxPars->txrxPayloadLen&0xff)); + h2cParaBuf[2] = (u1Byte)((pTxRxPars->txrxPayloadLen&0xff00)>>8); + h2cParaLen = 3; + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + } + + // ckeck bt return status. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C ("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + + // fill h2c parameters + btOpcode = BT_LO_OP_SET_PKT_CNT_L_PL_TYPE; + if(pTxRxPars->txrxPayloadType > MP_BT_PAYLOAD_MAX) + { + DBG_8192C ("[MPT], Error!! pTxRxPars->txrxPayloadType=0x%x, (should be between 0~4)\n", pTxRxPars->txrxPayloadType); + pBtRsp->status = (btOpcode<<8)|BT_STATUS_PARAMETER_OUT_OF_RANGE_U; + return paraLen; + } + else + { + h2cParaBuf[0] = (u1Byte)((pTxRxPars->txrxTxPktCnt&0xff)); + h2cParaBuf[1] = (u1Byte)((pTxRxPars->txrxTxPktCnt&0xff00)>>8); + h2cParaBuf[2] = pTxRxPars->txrxPayloadType; + h2cParaLen = 3; + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + } + + // ckeck bt return status. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C ("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + + // fill h2c parameters + btOpcode = BT_LO_OP_SET_PKT_CNT_H_PKT_INTV; + if(pTxRxPars->txrxTxPktInterval > 15) + { + DBG_8192C ("[MPT], Error!! pTxRxPars->txrxTxPktInterval=0x%x, (should be between 0~15)\n", pTxRxPars->txrxTxPktInterval); + pBtRsp->status = (btOpcode<<8)|BT_STATUS_PARAMETER_OUT_OF_RANGE_U; + return paraLen; + } + else + { + h2cParaBuf[0] = (u1Byte)((pTxRxPars->txrxTxPktCnt&0xff0000)>>16); + h2cParaBuf[1] = (u1Byte)((pTxRxPars->txrxTxPktCnt&0xff000000)>>24); + h2cParaBuf[2] = pTxRxPars->txrxTxPktInterval; + h2cParaLen = 3; + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + } + + // ckeck bt return status. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C ("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + + // fill h2c parameters + btOpcode = BT_LO_OP_SET_WHITENCOEFF; + { + h2cParaBuf[0] = pTxRxPars->txrxWhitenCoeff; + h2cParaLen = 1; + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + } + + // ckeck bt return status. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C ("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + + + // fill h2c parameters + btOpcode = BT_LO_OP_SET_CHNL_TX_GAIN; + if( (pTxRxPars->txrxChannel > 78) || + (pTxRxPars->txrxTxGainIndex > 7) ) + { + DBG_8192C ("[MPT], Error!! pTxRxPars->txrxChannel=0x%x, (should be between 0~78)\n", pTxRxPars->txrxChannel); + DBG_8192C ("[MPT], Error!! pTxRxPars->txrxTxGainIndex=0x%x, (should be between 0~7)\n", pTxRxPars->txrxTxGainIndex); + pBtRsp->status = (btOpcode<<8)|BT_STATUS_PARAMETER_OUT_OF_RANGE_U; + return paraLen; + } + else + { + h2cParaBuf[0] = pTxRxPars->txrxChannel; + h2cParaBuf[1] = pTxRxPars->txrxTxGainIndex; + h2cParaLen = 2; + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + } + + // ckeck bt return status. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C ("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + + // fill h2c parameters + btOpcode = BT_LO_OP_SET_BD_ADDR_L; + if( (pTxRxPars->txrxBdaddr[0]==0) && + (pTxRxPars->txrxBdaddr[1]==0) && + (pTxRxPars->txrxBdaddr[2]==0) && + (pTxRxPars->txrxBdaddr[3]==0) && + (pTxRxPars->txrxBdaddr[4]==0) && + (pTxRxPars->txrxBdaddr[5]==0) ) + { + DBG_8192C ("[MPT], Error!! pTxRxPars->txrxBdaddr=all zero\n"); + pBtRsp->status = (btOpcode<<8)|BT_STATUS_PARAMETER_OUT_OF_RANGE_U; + return paraLen; + } + if( (pTxRxPars->txrxBdaddr[0]==0xff) && + (pTxRxPars->txrxBdaddr[1]==0xff) && + (pTxRxPars->txrxBdaddr[2]==0xff) && + (pTxRxPars->txrxBdaddr[3]==0xff) && + (pTxRxPars->txrxBdaddr[4]==0xff) && + (pTxRxPars->txrxBdaddr[5]==0xff) ) + { + DBG_8192C ("[MPT], Error!! pTxRxPars->txrxBdaddr=all 0xf\n"); + pBtRsp->status = (btOpcode<<8)|BT_STATUS_PARAMETER_OUT_OF_RANGE_U; + return paraLen; + } + + { + h2cParaBuf[0] = pTxRxPars->txrxBdaddr[0]; + h2cParaBuf[1] = pTxRxPars->txrxBdaddr[1]; + h2cParaBuf[2] = pTxRxPars->txrxBdaddr[2]; + h2cParaLen = 3; + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + } + // ckeck bt return status. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C ("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + + btOpcode = BT_LO_OP_SET_BD_ADDR_H; + { + h2cParaBuf[0] = pTxRxPars->txrxBdaddr[3]; + h2cParaBuf[1] = pTxRxPars->txrxBdaddr[4]; + h2cParaBuf[2] = pTxRxPars->txrxBdaddr[5]; + h2cParaLen = 3; + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + } + // ckeck bt return status. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C ("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + + pBtRsp->status = BT_STATUS_SUCCESS; + return paraLen; +} + + + +u2Byte +mptbt_BtTestCtrl( + IN PADAPTER Adapter, + IN PBT_REQ_CMD pBtReq, + IN PBT_RSP_CMD pBtRsp + ) +{ + u1Byte h2cParaBuf[6] ={0}; + u1Byte h2cParaLen=0; + u2Byte paraLen=0; + u1Byte retStatus=BT_STATUS_BT_OP_SUCCESS; + u1Byte btOpcode; + u1Byte btOpcodeVer=0; + u1Byte testCtrl=0; + + // + // check upper layer parameters + // + + // 1. check upper layer opcode version + if(pBtReq->opCodeVer != 1) + { + DBG_8192C("[MPT], Error!! Upper OP code version not match!!!\n"); + pBtRsp->status = BT_STATUS_OPCODE_U_VERSION_MISMATCH; + return paraLen; + } + // 2. check upper layer parameter length + if(1 == pBtReq->paraLength) + { + testCtrl = pBtReq->pParamStart[0]; + DBG_8192C("[MPT], testCtrl=%d \n", testCtrl); + } + else + { + DBG_8192C("[MPT], Error!! wrong parameter length=%d (should be 1)\n", pBtReq->paraLength); + pBtRsp->status = BT_STATUS_PARAMETER_FORMAT_ERROR_U; + return paraLen; + } + + // + // execute lower layer opcodes + // + + // 1. fill h2c parameters + // check bt mode + btOpcode = BT_LO_OP_TEST_CTRL; + if(testCtrl >= MP_BT_TEST_MAX) + { + DBG_8192C("[MPT], Error!! testCtrl=0x%x, (should be between smaller or equal to 0x%x)\n", + testCtrl, MP_BT_TEST_MAX-1); + pBtRsp->status = BT_STATUS_PARAMETER_OUT_OF_RANGE_U; + return paraLen; + } + else + { + h2cParaBuf[0] = testCtrl; + h2cParaLen = 1; + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + } + + // 3. construct respond status code and data. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + + pBtRsp->status = BT_STATUS_SUCCESS; + return paraLen; +} + + +u2Byte +mptbt_TestBT( + IN PADAPTER Adapter, + IN PBT_REQ_CMD pBtReq, + IN PBT_RSP_CMD pBtRsp + ) +{ + + u1Byte h2cParaBuf[6] ={0}; + u1Byte h2cParaLen=0; + u2Byte paraLen=0; + u1Byte retStatus=BT_STATUS_BT_OP_SUCCESS; + u1Byte btOpcode; + u1Byte btOpcodeVer=0; + u1Byte testCtrl=0; + + // 1. fill h2c parameters + btOpcode = 0x11; + h2cParaBuf[0] = 0x11; + h2cParaBuf[1] = 0x0; + h2cParaBuf[2] = 0x0; + h2cParaBuf[3] = 0x0; + h2cParaBuf[4] = 0x0; + h2cParaLen = 1; + // retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, &h2cParaBuf[0], h2cParaLen); + retStatus = mptbt_BtFwOpCodeProcess(Adapter, btOpcode, btOpcodeVer, h2cParaBuf, h2cParaLen); + + + // 3. construct respond status code and data. + if(BT_STATUS_BT_OP_SUCCESS != retStatus) + { + pBtRsp->status = ((btOpcode<<8)|retStatus); + DBG_8192C("[MPT], Error!! status code=0x%x \n", pBtRsp->status); + return paraLen; + } + + pBtRsp->status = BT_STATUS_SUCCESS; + return paraLen; +} + +VOID +mptbt_BtControlProcess( + PADAPTER Adapter, + PVOID pInBuf + ) +{ + u1Byte H2C_Parameter[6] ={0}; + PBT_H2C pH2c=(PBT_H2C)&H2C_Parameter[0]; + PMPT_CONTEXT pMptCtx=&(Adapter->mppriv.MptCtx); + PBT_REQ_CMD pBtReq=(PBT_REQ_CMD)pInBuf; + PBT_RSP_CMD pBtRsp; + u1Byte i; + + + DBG_8192C("[MPT], mptbt_BtControlProcess()=========>\n"); + + DBG_8192C("[MPT], input opCodeVer=%d\n", pBtReq->opCodeVer); + DBG_8192C("[MPT], input OpCode=%d\n", pBtReq->OpCode); + DBG_8192C("[MPT], paraLength=%d \n", pBtReq->paraLength); + if(pBtReq->paraLength) + { + //DBG_8192C("[MPT], parameters(hex):0x%x %d \n",&pBtReq->pParamStart[0], pBtReq->paraLength); + } + + _rtw_memset((void*)pMptCtx->mptOutBuf, 0, 100); + pMptCtx->mptOutLen = 4; //length of (BT_RSP_CMD.status+BT_RSP_CMD.paraLength) + + pBtRsp = (PBT_RSP_CMD)pMptCtx->mptOutBuf; + pBtRsp->status = BT_STATUS_SUCCESS; + pBtRsp->paraLength = 0x0; + + // The following we should maintain the User OP codes sent by upper layer + switch(pBtReq->OpCode) + { + case BT_UP_OP_BT_READY: + DBG_8192C("[MPT], OPcode : [BT_READY]\n"); + pBtRsp->paraLength = mptbt_BtReady(Adapter, pBtReq, pBtRsp); + break; + case BT_UP_OP_BT_SET_MODE: + DBG_8192C("[MPT], OPcode : [BT_SET_MODE]\n"); + pBtRsp->paraLength = mptbt_BtSetMode(Adapter, pBtReq, pBtRsp); + break; + case BT_UP_OP_BT_SET_TX_RX_PARAMETER: + DBG_8192C("[MPT], OPcode : [BT_SET_TXRX_PARAMETER]\n"); + pBtRsp->paraLength = mptbt_BtSetTxRxPars(Adapter, pBtReq, pBtRsp); + break; + case BT_UP_OP_BT_SET_GENERAL: + DBG_8192C("[MPT], OPcode : [BT_SET_GENERAL]\n"); + pBtRsp->paraLength = mptbt_BtSetGeneral(Adapter, pBtReq, pBtRsp); + break; + case BT_UP_OP_BT_GET_GENERAL: + DBG_8192C("[MPT], OPcode : [BT_GET_GENERAL]\n"); + pBtRsp->paraLength = mptbt_BtGetGeneral(Adapter, pBtReq, pBtRsp); + break; + case BT_UP_OP_BT_TEST_CTRL: + DBG_8192C("[MPT], OPcode : [BT_TEST_CTRL]\n"); + pBtRsp->paraLength = mptbt_BtTestCtrl(Adapter, pBtReq, pBtRsp); + break; + case BT_UP_OP_TEST_BT: + DBG_8192C("[MPT], OPcode : [TEST_BT]\n"); + pBtRsp->paraLength = mptbt_TestBT(Adapter, pBtReq, pBtRsp); + break; + default: + DBG_8192C("[MPT], Error!! OPcode : UNDEFINED!!!!\n"); + pBtRsp->status = BT_STATUS_UNKNOWN_OPCODE_U; + pBtRsp->paraLength = 0x0; + break; + } + + pMptCtx->mptOutLen += pBtRsp->paraLength; + + DBG_8192C("[MPT], pMptCtx->mptOutLen=%d, pBtRsp->paraLength=%d\n", pMptCtx->mptOutLen, pBtRsp->paraLength); + DBG_8192C("[MPT], mptbt_BtControlProcess()<=========\n"); +} + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_btcoex.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_btcoex.c new file mode 100644 index 000000000..a3d249fbf --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_btcoex.c @@ -0,0 +1,1743 @@ +/****************************************************************************** + * + * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifdef CONFIG_BT_COEXIST + +#include +#include +#include + + +void rtw_btcoex_Initialize(PADAPTER padapter) +{ + hal_btcoex_Initialize(padapter); +} + +void rtw_btcoex_PowerOnSetting(PADAPTER padapter) +{ + hal_btcoex_PowerOnSetting(padapter); +} + +void rtw_btcoex_PreLoadFirmware(PADAPTER padapter) +{ + hal_btcoex_PreLoadFirmware(padapter); +} + +void rtw_btcoex_HAL_Initialize(PADAPTER padapter, u8 bWifiOnly) +{ + hal_btcoex_InitHwConfig(padapter, bWifiOnly); +} + +void rtw_btcoex_IpsNotify(PADAPTER padapter, u8 type) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + if (_FALSE == pHalData->EEPROMBluetoothCoexist) + return; + + hal_btcoex_IpsNotify(padapter, type); +} + +void rtw_btcoex_LpsNotify(PADAPTER padapter, u8 type) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + if (_FALSE == pHalData->EEPROMBluetoothCoexist) + return; + + hal_btcoex_LpsNotify(padapter, type); +} + +void rtw_btcoex_ScanNotify(PADAPTER padapter, u8 type) +{ + PHAL_DATA_TYPE pHalData; +#ifdef CONFIG_BT_COEXIST_SOCKET_TRX + struct bt_coex_info *pcoex_info = &padapter->coex_info; + PBT_MGNT pBtMgnt=&pcoex_info->BtMgnt; +#endif //CONFIG_BT_COEXIST_SOCKET_TRX + + pHalData = GET_HAL_DATA(padapter); + if (_FALSE == pHalData->EEPROMBluetoothCoexist) + return; + +#ifdef CONFIG_CONCURRENT_MODE + if ((_FALSE == type) && (padapter->pbuddy_adapter)) + { + PADAPTER pbuddy = padapter->pbuddy_adapter; + if (check_fwstate(&pbuddy->mlmepriv, WIFI_SITE_MONITOR) == _TRUE) + return; + } +#endif + +#ifdef CONFIG_BT_COEXIST_SOCKET_TRX + if(pBtMgnt->ExtConfig.bEnableWifiScanNotify) + rtw_btcoex_SendScanNotify(padapter, type); +#endif //CONFIG_BT_COEXIST_SOCKET_TRX + + hal_btcoex_ScanNotify(padapter, type); +} + +void rtw_btcoex_ConnectNotify(PADAPTER padapter, u8 action) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + if (_FALSE == pHalData->EEPROMBluetoothCoexist) + return; + +#ifdef DBG_CONFIG_ERROR_RESET + if (_TRUE == rtw_hal_sreset_inprogress(padapter)) + { + DBG_8192C(FUNC_ADPT_FMT ": [BTCoex] under reset, skip notify!\n", + FUNC_ADPT_ARG(padapter)); + return; + } +#endif // DBG_CONFIG_ERROR_RESET + +#ifdef CONFIG_CONCURRENT_MODE + if ((_FALSE == action) && (padapter->pbuddy_adapter)) + { + PADAPTER pbuddy = padapter->pbuddy_adapter; + if (check_fwstate(&pbuddy->mlmepriv, WIFI_UNDER_LINKING) == _TRUE) + return; + } +#endif + + hal_btcoex_ConnectNotify(padapter, action); +} + +void rtw_btcoex_MediaStatusNotify(PADAPTER padapter, u8 mediaStatus) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + if (_FALSE == pHalData->EEPROMBluetoothCoexist) + return; + +#ifdef DBG_CONFIG_ERROR_RESET + if (_TRUE == rtw_hal_sreset_inprogress(padapter)) + { + DBG_8192C(FUNC_ADPT_FMT ": [BTCoex] under reset, skip notify!\n", + FUNC_ADPT_ARG(padapter)); + return; + } +#endif // DBG_CONFIG_ERROR_RESET + +#ifdef CONFIG_CONCURRENT_MODE + if ((RT_MEDIA_DISCONNECT == mediaStatus) && (padapter->pbuddy_adapter)) + { + PADAPTER pbuddy = padapter->pbuddy_adapter; + if (check_fwstate(&pbuddy->mlmepriv, WIFI_ASOC_STATE) == _TRUE) + return; + } +#endif // CONFIG_CONCURRENT_MODE + + if ((RT_MEDIA_CONNECT == mediaStatus) + && (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE)) + { + rtw_hal_set_hwreg(padapter, HW_VAR_DL_RSVD_PAGE, NULL); + } + + hal_btcoex_MediaStatusNotify(padapter, mediaStatus); +} + +void rtw_btcoex_SpecialPacketNotify(PADAPTER padapter, u8 pktType) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + if (_FALSE == pHalData->EEPROMBluetoothCoexist) + return; + + hal_btcoex_SpecialPacketNotify(padapter, pktType); +} + +void rtw_btcoex_IQKNotify(PADAPTER padapter, u8 state) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + if (_FALSE == pHalData->EEPROMBluetoothCoexist) + return; + + hal_btcoex_IQKNotify(padapter, state); +} + +void rtw_btcoex_BtInfoNotify(PADAPTER padapter, u8 length, u8 *tmpBuf) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + if (_FALSE == pHalData->EEPROMBluetoothCoexist) + return; + + hal_btcoex_BtInfoNotify(padapter, length, tmpBuf); +} + +void rtw_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + if (_FALSE == pHalData->EEPROMBluetoothCoexist) + return; + + if (padapter->registrypriv.mp_mode == 1) + return; + + hal_btcoex_BtMpRptNotify(padapter, length, tmpBuf); +} + +void rtw_btcoex_SuspendNotify(PADAPTER padapter, u8 state) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + if (_FALSE == pHalData->EEPROMBluetoothCoexist) + return; + + hal_btcoex_SuspendNotify(padapter, state); +} + +void rtw_btcoex_HaltNotify(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + if (_FALSE == pHalData->EEPROMBluetoothCoexist) + return; + + if (_FALSE == padapter->bup) + { + DBG_871X(FUNC_ADPT_FMT ": bup=%d Skip!\n", + FUNC_ADPT_ARG(padapter), padapter->bup); + + return; + } + + if (rtw_is_surprise_removed(padapter)) { + DBG_871X(FUNC_ADPT_FMT ": bSurpriseRemoved=%s Skip!\n", + FUNC_ADPT_ARG(padapter), rtw_is_surprise_removed(padapter)?"True":"False"); + + return; + } + + hal_btcoex_HaltNotify(padapter); +} + +void rtw_btcoex_ScoreBoardStatusNotify(PADAPTER padapter, u8 length, u8 *tmpBuf) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + if (_FALSE == pHalData->EEPROMBluetoothCoexist) + return; + + hal_btcoex_ScoreBoardStatusNotify(padapter, length, tmpBuf); +} + +void rtw_btcoex_SwitchBtTRxMask(PADAPTER padapter) +{ + hal_btcoex_SwitchBtTRxMask(padapter); +} + +void rtw_btcoex_Switch(PADAPTER padapter, u8 enable) +{ + hal_btcoex_SetBTCoexist(padapter, enable); +} + +u8 rtw_btcoex_IsBtDisabled(PADAPTER padapter) +{ + return hal_btcoex_IsBtDisabled(padapter); +} + +void rtw_btcoex_Handler(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + + if (_FALSE == pHalData->EEPROMBluetoothCoexist) + return; + +#if defined(CONFIG_CONCURRENT_MODE) + if (padapter->adapter_type != PRIMARY_ADAPTER) + return; +#endif + + + + hal_btcoex_Hanlder(padapter); +} + +s32 rtw_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter) +{ + s32 coexctrl; + + coexctrl = hal_btcoex_IsBTCoexRejectAMPDU(padapter); + + return coexctrl; +} + +s32 rtw_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER padapter) +{ + s32 coexctrl; + + coexctrl = hal_btcoex_IsBTCoexCtrlAMPDUSize(padapter); + + return coexctrl; +} + +u32 rtw_btcoex_GetAMPDUSize(PADAPTER padapter) +{ + u32 size; + + size = hal_btcoex_GetAMPDUSize(padapter); + + return size; +} + +void rtw_btcoex_SetManualControl(PADAPTER padapter, u8 manual) +{ + if (_TRUE == manual) + { + hal_btcoex_SetManualControl(padapter, _TRUE); + } + else + { + hal_btcoex_SetManualControl(padapter, _FALSE); + } +} + +u8 rtw_btcoex_1Ant(PADAPTER padapter) +{ + return hal_btcoex_1Ant(padapter); +} + +u8 rtw_btcoex_IsBtControlLps(PADAPTER padapter) +{ + return hal_btcoex_IsBtControlLps(padapter); +} + +u8 rtw_btcoex_IsLpsOn(PADAPTER padapter) +{ + return hal_btcoex_IsLpsOn(padapter); +} + +u8 rtw_btcoex_RpwmVal(PADAPTER padapter) +{ + return hal_btcoex_RpwmVal(padapter); +} + +u8 rtw_btcoex_LpsVal(PADAPTER padapter) +{ + return hal_btcoex_LpsVal(padapter); +} + +void rtw_btcoex_SetBTCoexist(PADAPTER padapter, u8 bBtExist) +{ + hal_btcoex_SetBTCoexist(padapter, bBtExist); +} + +void rtw_btcoex_SetChipType(PADAPTER padapter, u8 chipType) +{ + hal_btcoex_SetChipType(padapter, chipType); +} + +void rtw_btcoex_SetPGAntNum(PADAPTER padapter, u8 antNum) +{ + hal_btcoex_SetPgAntNum(padapter, antNum); +} + +u8 rtw_btcoex_GetPGAntNum(PADAPTER padapter) +{ + return hal_btcoex_GetPgAntNum(padapter); +} + +void rtw_btcoex_SetSingleAntPath(PADAPTER padapter, u8 singleAntPath) +{ + hal_btcoex_SetSingleAntPath(padapter, singleAntPath); +} + +u32 rtw_btcoex_GetRaMask(PADAPTER padapter) +{ + return hal_btcoex_GetRaMask(padapter); +} + +void rtw_btcoex_RecordPwrMode(PADAPTER padapter, u8 *pCmdBuf, u8 cmdLen) +{ + hal_btcoex_RecordPwrMode(padapter, pCmdBuf, cmdLen); +} + +void rtw_btcoex_DisplayBtCoexInfo(PADAPTER padapter, u8 *pbuf, u32 bufsize) +{ + hal_btcoex_DisplayBtCoexInfo(padapter, pbuf, bufsize); +} + +void rtw_btcoex_SetDBG(PADAPTER padapter, u32 *pDbgModule) +{ + hal_btcoex_SetDBG(padapter, pDbgModule); +} + +u32 rtw_btcoex_GetDBG(PADAPTER padapter, u8 *pStrBuf, u32 bufSize) +{ + return hal_btcoex_GetDBG(padapter, pStrBuf, bufSize); +} + +u8 rtw_btcoex_IncreaseScanDeviceNum(PADAPTER padapter) +{ + return hal_btcoex_IncreaseScanDeviceNum(padapter); +} + +u8 rtw_btcoex_IsBtLinkExist(PADAPTER padapter) +{ + return hal_btcoex_IsBtLinkExist(padapter); +} + +void rtw_btcoex_SetBtPatchVersion(PADAPTER padapter,u16 btHciVer, u16 btPatchVer) +{ + hal_btcoex_SetBtPatchVersion(padapter,btHciVer,btPatchVer); +} + +void rtw_btcoex_SetHciVersion(PADAPTER padapter, u16 hciVersion) +{ + hal_btcoex_SetHciVersion(padapter, hciVersion); +} + +void rtw_btcoex_StackUpdateProfileInfo(void) +{ + hal_btcoex_StackUpdateProfileInfo(); +} + +void rtw_btcoex_BTOffOnNotify(PADAPTER padapter, u8 bBTON) +{ + hal_btcoex_BTOffOnNotify(padapter, bBTON); +} + +// ================================================== +// Below Functions are called by BT-Coex +// ================================================== +void rtw_btcoex_rx_ampdu_apply(PADAPTER padapter) +{ + rtw_rx_ampdu_apply(padapter); +} + +void rtw_btcoex_LPS_Enter(PADAPTER padapter) +{ + struct pwrctrl_priv *pwrpriv; + u8 lpsVal; + + + pwrpriv = adapter_to_pwrctl(padapter); + + pwrpriv->bpower_saving = _TRUE; + lpsVal = rtw_btcoex_LpsVal(padapter); + rtw_set_ps_mode(padapter, PS_MODE_MIN, 0, lpsVal, "BTCOEX"); +} + +void rtw_btcoex_LPS_Leave(PADAPTER padapter) +{ + struct pwrctrl_priv *pwrpriv; + + + pwrpriv = adapter_to_pwrctl(padapter); + + if (pwrpriv->pwr_mode != PS_MODE_ACTIVE) + { + rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "BTCOEX"); + LPS_RF_ON_check(padapter, 100); + pwrpriv->bpower_saving = _FALSE; + } +} + +u16 rtw_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data) +{ + return hal_btcoex_btreg_read(padapter, type, addr, data); +} + +u16 rtw_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val) +{ + return hal_btcoex_btreg_write(padapter, type, addr, val); +} + + +// ================================================== +// Below Functions are BT-Coex socket related function +// ================================================== + +#ifdef CONFIG_BT_COEXIST_SOCKET_TRX +_adapter *pbtcoexadapter = NULL; +u8 rtw_btcoex_btinfo_cmd(_adapter *adapter, u8 *buf, u16 len) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + u8 *btinfo; + struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + u8 res = _SUCCESS; + + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (pdrvextra_cmd_parm == NULL) { + rtw_mfree((u8*)ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + btinfo = rtw_zmalloc(len); + if (btinfo == NULL) { + rtw_mfree((u8*)ph2c, sizeof(struct cmd_obj)); + rtw_mfree((u8*)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm)); + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = BTINFO_WK_CID; + pdrvextra_cmd_parm->type = 0; + pdrvextra_cmd_parm->size = len; + pdrvextra_cmd_parm->pbuf = btinfo; + + _rtw_memcpy(btinfo, buf, len); + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + return res; +} + +u8 rtw_btcoex_send_event_to_BT(_adapter *padapter, u8 status, u8 event_code, u8 opcode_low, u8 opcode_high,u8 *dbg_msg) +{ + u8 localBuf[6] = ""; + u8 *pRetPar; + u8 len=0,tx_event_length = 0; + rtw_HCI_event *pEvent; + + pEvent = (rtw_HCI_event*)(&localBuf[0]); + + pEvent->EventCode = event_code; + pEvent->Data[0] = 0x1; //packet # + pEvent->Data[1] = opcode_low; + pEvent->Data[2] = opcode_high; + len = len + 3; + + // Return parameters starts from here + pRetPar = &pEvent->Data[len]; + pRetPar[0] = status; //status + + len++; + pEvent->Length = len; + + //total tx event length + EventCode length + sizeof(length) + tx_event_length = pEvent->Length + 2; +#if 0 + rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, dbg_msg); +#endif + status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE); + + return status; +} + +/* +Ref: +Realtek Wi-Fi Driver +Host Controller Interface for +Bluetooth 3.0 + HS V1.4 2013/02/07 + +Window team code & BT team code + */ + + +u8 rtw_btcoex_parse_BT_info_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen) +{ + #define BT_INFO_LENGTH 8 + + u8 curPollEnable = pcmd[0]; + u8 curPollTime = pcmd[1]; + u8 btInfoReason = pcmd[2]; + u8 btInfoLen = pcmd[3]; + u8 btinfo[BT_INFO_LENGTH]; + + u8 localBuf[6] = ""; + u8 *pRetPar; + u8 len=0,tx_event_length = 0; + RTW_HCI_STATUS status = HCI_STATUS_SUCCESS; + rtw_HCI_event *pEvent; + + /* DBG_871X("%s\n",__func__); + DBG_871X("current Poll Enable: %d, currrent Poll Time: %d\n",curPollEnable,curPollTime); + DBG_871X("BT Info reason: %d, BT Info length: %d\n",btInfoReason,btInfoLen); + DBG_871X("%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n" + ,pcmd[4],pcmd[5],pcmd[6],pcmd[7],pcmd[8],pcmd[9],pcmd[10],pcmd[11]);*/ + + _rtw_memset(btinfo, 0, BT_INFO_LENGTH); + +#if 1 + if(BT_INFO_LENGTH != btInfoLen) + { + status = HCI_STATUS_INVALID_HCI_CMD_PARA_VALUE; + DBG_871X("Error BT Info Length: %d\n",btInfoLen); + //return _FAIL; + } + else +#endif + { + if(0x1 == btInfoReason || 0x2 == btInfoReason) + { + _rtw_memcpy(btinfo, &pcmd[4], btInfoLen); + btinfo[0] = btInfoReason; + rtw_btcoex_btinfo_cmd(padapter,btinfo,btInfoLen); + } + else + { + DBG_871X("Other BT info reason\n"); + } + } + + //send complete event to BT + { + + pEvent = (rtw_HCI_event*)(&localBuf[0]); + + pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE; + pEvent->Data[0] = 0x1; //packet # + pEvent->Data[1] = HCIOPCODELOW(HCI_BT_INFO_NOTIFY, OGF_EXTENSION); + pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_INFO_NOTIFY, OGF_EXTENSION); + len = len + 3; + + // Return parameters starts from here + pRetPar = &pEvent->Data[len]; + pRetPar[0] = status; //status + + len++; + pEvent->Length = len; + + //total tx event length + EventCode length + sizeof(length) + tx_event_length = pEvent->Length + 2; +#if 0 + rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length,"BT_info_event"); +#endif + status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE); + + return status; + //bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); + } +} + +u8 rtw_btcoex_parse_BT_patch_ver_info_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen) +{ + RTW_HCI_STATUS status=HCI_STATUS_SUCCESS; + u16 btPatchVer=0x0, btHciVer=0x0; + //u16 *pU2tmp; + + u8 localBuf[6] = ""; + u8 *pRetPar; + u8 len=0, tx_event_length =0; + rtw_HCI_event *pEvent; + + btHciVer = pcmd[0] | pcmd[1]<<8; + btPatchVer = pcmd[2] | pcmd[3]<<8; + + + DBG_871X("%s, cmd:%02x %02x %02x %02x\n",__func__, pcmd[0] ,pcmd[1] ,pcmd[2] ,pcmd[3]); + DBG_871X("%s, HCI Ver:%d, Patch Ver:%d\n",__func__, btHciVer,btPatchVer); + + rtw_btcoex_SetBtPatchVersion(padapter,btHciVer,btPatchVer); + + + //send complete event to BT + { + pEvent = (rtw_HCI_event *)(&localBuf[0]); + + + pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE; + pEvent->Data[0] = 0x1; //packet # + pEvent->Data[1] = HCIOPCODELOW(HCI_BT_PATCH_VERSION_NOTIFY, OGF_EXTENSION); + pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_PATCH_VERSION_NOTIFY, OGF_EXTENSION); + len = len + 3; + + // Return parameters starts from here + pRetPar = &pEvent->Data[len]; + pRetPar[0] = status; //status + + len++; + pEvent->Length = len; + + //total tx event length + EventCode length + sizeof(length) + tx_event_length = pEvent->Length + 2; +#if 0 + rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length,"BT_patch_event"); +#endif + status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE); + return status; + //bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); + } +} + +u8 rtw_btcoex_parse_HCI_Ver_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen) +{ + RTW_HCI_STATUS status=HCI_STATUS_SUCCESS; + u16 hciver = pcmd[0] | pcmd[1] <<8; + + u8 localBuf[6] = ""; + u8 *pRetPar; + u8 len=0, tx_event_length =0; + rtw_HCI_event *pEvent; + + struct bt_coex_info *pcoex_info = &padapter->coex_info; + PBT_MGNT pBtMgnt=&pcoex_info->BtMgnt; + pBtMgnt->ExtConfig.HCIExtensionVer = hciver; + DBG_871X("%s, HCI Version: %d\n",__func__,pBtMgnt->ExtConfig.HCIExtensionVer); + if(pBtMgnt->ExtConfig.HCIExtensionVer < 4) + { + status = HCI_STATUS_INVALID_HCI_CMD_PARA_VALUE; + DBG_871X("%s, Version = %d, HCI Version < 4\n",__func__,pBtMgnt->ExtConfig.HCIExtensionVer ); + } + else + { + rtw_btcoex_SetHciVersion(padapter,hciver); + } + //send complete event to BT + { + pEvent = (rtw_HCI_event *)(&localBuf[0]); + + + pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE; + pEvent->Data[0] = 0x1; //packet # + pEvent->Data[1] = HCIOPCODELOW(HCI_EXTENSION_VERSION_NOTIFY, OGF_EXTENSION); + pEvent->Data[2] = HCIOPCODEHIGHT(HCI_EXTENSION_VERSION_NOTIFY, OGF_EXTENSION); + len = len + 3; + + // Return parameters starts from here + pRetPar = &pEvent->Data[len]; + pRetPar[0] = status; //status + + len++; + pEvent->Length = len; + + //total tx event length + EventCode length + sizeof(length) + tx_event_length = pEvent->Length + 2; + + status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE); + return status; + //bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); + } + +} + +u8 rtw_btcoex_parse_WIFI_scan_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen) +{ + RTW_HCI_STATUS status=HCI_STATUS_SUCCESS; + + u8 localBuf[6] = ""; + u8 *pRetPar; + u8 len=0, tx_event_length =0; + rtw_HCI_event *pEvent; + + struct bt_coex_info *pcoex_info = &padapter->coex_info; + PBT_MGNT pBtMgnt=&pcoex_info->BtMgnt; + pBtMgnt->ExtConfig.bEnableWifiScanNotify= pcmd[0]; + DBG_871X("%s, bEnableWifiScanNotify: %d\n",__func__,pBtMgnt->ExtConfig.bEnableWifiScanNotify); + + //send complete event to BT + { + pEvent = (rtw_HCI_event *)(&localBuf[0]); + + + pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE; + pEvent->Data[0] = 0x1; //packet # + pEvent->Data[1] = HCIOPCODELOW(HCI_ENABLE_WIFI_SCAN_NOTIFY, OGF_EXTENSION); + pEvent->Data[2] = HCIOPCODEHIGHT(HCI_ENABLE_WIFI_SCAN_NOTIFY, OGF_EXTENSION); + len = len + 3; + + // Return parameters starts from here + pRetPar = &pEvent->Data[len]; + pRetPar[0] = status; //status + + len++; + pEvent->Length = len; + + //total tx event length + EventCode length + sizeof(length) + tx_event_length = pEvent->Length + 2; + + status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE); + return status; + //bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); + } +} + +u8 rtw_btcoex_parse_HCI_link_status_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen) +{ + RTW_HCI_STATUS status=HCI_STATUS_SUCCESS; + struct bt_coex_info *pcoex_info=&padapter->coex_info; + PBT_MGNT pBtMgnt=&pcoex_info->BtMgnt; + //PBT_DBG pBtDbg=&padapter->MgntInfo.BtInfo.BtDbg; + u8 i, numOfHandle=0, numOfAcl=0; + u16 conHandle; + u8 btProfile, btCoreSpec, linkRole; + u8 *pTriple; + + u8 localBuf[6] = ""; + u8 *pRetPar; + u8 len=0, tx_event_length =0; + rtw_HCI_event *pEvent; + + //pBtDbg->dbgHciInfo.hciCmdCntLinkStatusNotify++; + //RT_DISP_DATA(FIOCTL, IOCTL_BT_HCICMD_EXT, "LinkStatusNotify, Hex Data :\n", + // &pHciCmd->Data[0], pHciCmd->Length); + + DBG_871X("BTLinkStatusNotify\n"); + + // Current only RTL8723 support this command. + //pBtMgnt->bSupportProfile = TRUE; + pBtMgnt->bSupportProfile = _FALSE; + + pBtMgnt->ExtConfig.NumberOfACL = 0; + pBtMgnt->ExtConfig.NumberOfSCO = 0; + + numOfHandle = pcmd[0]; + //RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, ("numOfHandle = 0x%x\n", numOfHandle)); + //RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, ("HCIExtensionVer = %d\n", pBtMgnt->ExtConfig.HCIExtensionVer)); + DBG_871X("numOfHandle = 0x%x\n", numOfHandle); + DBG_871X("HCIExtensionVer = %d\n", pBtMgnt->ExtConfig.HCIExtensionVer); + + pTriple = &pcmd[1]; + for(i=0; iExtConfig.HCIExtensionVer < 1) + { + conHandle = *((u8 *)&pTriple[0]); + btProfile = pTriple[2]; + btCoreSpec = pTriple[3]; + if(BT_PROFILE_SCO == btProfile) + { + pBtMgnt->ExtConfig.NumberOfSCO++; + } + else + { + pBtMgnt->ExtConfig.NumberOfACL++; + pBtMgnt->ExtConfig.aclLink[i].ConnectHandle = conHandle; + pBtMgnt->ExtConfig.aclLink[i].BTProfile = btProfile; + pBtMgnt->ExtConfig.aclLink[i].BTCoreSpec = btCoreSpec; + } + //RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, + // ("Connection_Handle=0x%x, BTProfile=%d, BTSpec=%d\n", + // conHandle, btProfile, btCoreSpec)); + DBG_871X("Connection_Handle=0x%x, BTProfile=%d, BTSpec=%d\n", conHandle, btProfile, btCoreSpec); + pTriple += 4; + } + else if(pBtMgnt->ExtConfig.HCIExtensionVer >= 1) + { + conHandle = *((pu2Byte)&pTriple[0]); + btProfile = pTriple[2]; + btCoreSpec = pTriple[3]; + linkRole = pTriple[4]; + if(BT_PROFILE_SCO == btProfile) + { + pBtMgnt->ExtConfig.NumberOfSCO++; + } + else + { + pBtMgnt->ExtConfig.NumberOfACL++; + pBtMgnt->ExtConfig.aclLink[i].ConnectHandle = conHandle; + pBtMgnt->ExtConfig.aclLink[i].BTProfile = btProfile; + pBtMgnt->ExtConfig.aclLink[i].BTCoreSpec = btCoreSpec; + pBtMgnt->ExtConfig.aclLink[i].linkRole = linkRole; + } + //RT_DISP(FIOCTL, IOCTL_BT_HCICMD_EXT, + DBG_871X("Connection_Handle=0x%x, BTProfile=%d, BTSpec=%d, LinkRole=%d\n", + conHandle, btProfile, btCoreSpec, linkRole); + pTriple += 5; + } + } + rtw_btcoex_StackUpdateProfileInfo(); + + //send complete event to BT + { + pEvent = (rtw_HCI_event *)(&localBuf[0]); + + + pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE; + pEvent->Data[0] = 0x1; //packet # + pEvent->Data[1] = HCIOPCODELOW(HCI_LINK_STATUS_NOTIFY, OGF_EXTENSION); + pEvent->Data[2] = HCIOPCODEHIGHT(HCI_LINK_STATUS_NOTIFY, OGF_EXTENSION); + len = len + 3; + + // Return parameters starts from here + pRetPar = &pEvent->Data[len]; + pRetPar[0] = status; //status + + len++; + pEvent->Length = len; + + //total tx event length + EventCode length + sizeof(length) + tx_event_length = pEvent->Length + 2; + + status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE); + return status; + //bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); + } + + +} + +u8 rtw_btcoex_parse_HCI_BT_coex_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen) +{ + u8 localBuf[6] = ""; + u8 *pRetPar; + u8 len=0, tx_event_length =0; + rtw_HCI_event *pEvent; + RTW_HCI_STATUS status=HCI_STATUS_SUCCESS; + + { + pEvent = (rtw_HCI_event *)(&localBuf[0]); + + + pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE; + pEvent->Data[0] = 0x1; //packet # + pEvent->Data[1] = HCIOPCODELOW(HCI_BT_COEX_NOTIFY, OGF_EXTENSION); + pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_COEX_NOTIFY, OGF_EXTENSION); + len = len + 3; + + // Return parameters starts from here + pRetPar = &pEvent->Data[len]; + pRetPar[0] = status; //status + + len++; + pEvent->Length = len; + + //total tx event length + EventCode length + sizeof(length) + tx_event_length = pEvent->Length + 2; + + status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE); + return status; + //bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); + } +} + +u8 rtw_btcoex_parse_HCI_BT_operation_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen) +{ + u8 localBuf[6] = ""; + u8 *pRetPar; + u8 len=0, tx_event_length =0; + rtw_HCI_event *pEvent; + RTW_HCI_STATUS status=HCI_STATUS_SUCCESS; + + DBG_871X("%s, OP code: %d\n",__func__,pcmd[0]); + + switch(pcmd[0]) + { + case HCI_BT_OP_NONE: + DBG_871X("[bt operation] : Operation None!!\n"); + break; + case HCI_BT_OP_INQUIRY_START: + DBG_871X("[bt operation] : Inquiry start!!\n"); + break; + case HCI_BT_OP_INQUIRY_FINISH: + DBG_871X("[bt operation] : Inquiry finished!!\n"); + break; + case HCI_BT_OP_PAGING_START: + DBG_871X("[bt operation] : Paging is started!!\n"); + break; + case HCI_BT_OP_PAGING_SUCCESS: + DBG_871X("[bt operation] : Paging complete successfully!!\n"); + break; + case HCI_BT_OP_PAGING_UNSUCCESS: + DBG_871X("[bt operation] : Paging complete unsuccessfully!!\n"); + break; + case HCI_BT_OP_PAIRING_START: + DBG_871X("[bt operation] : Pairing start!!\n"); + break; + case HCI_BT_OP_PAIRING_FINISH: + DBG_871X("[bt operation] : Pairing finished!!\n"); + break; + case HCI_BT_OP_BT_DEV_ENABLE: + DBG_871X("[bt operation] : BT Device is enabled!!\n"); + break; + case HCI_BT_OP_BT_DEV_DISABLE: + DBG_871X("[bt operation] : BT Device is disabled!!\n"); + break; + default: + DBG_871X("[bt operation] : Unknown, error!!\n"); + break; + } + + //send complete event to BT + { + pEvent = (rtw_HCI_event *)(&localBuf[0]); + + + pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE; + pEvent->Data[0] = 0x1; //packet # + pEvent->Data[1] = HCIOPCODELOW(HCI_BT_OPERATION_NOTIFY, OGF_EXTENSION); + pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_OPERATION_NOTIFY, OGF_EXTENSION); + len = len + 3; + + // Return parameters starts from here + pRetPar = &pEvent->Data[len]; + pRetPar[0] = status; //status + + len++; + pEvent->Length = len; + + //total tx event length + EventCode length + sizeof(length) + tx_event_length = pEvent->Length + 2; + + status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE); + return status; + //bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); + } +} + +u8 rtw_btcoex_parse_BT_AFH_MAP_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen) +{ + u8 localBuf[6] = ""; + u8 *pRetPar; + u8 len=0, tx_event_length =0; + rtw_HCI_event *pEvent; + RTW_HCI_STATUS status=HCI_STATUS_SUCCESS; + + { + pEvent = (rtw_HCI_event *)(&localBuf[0]); + + + pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE; + pEvent->Data[0] = 0x1; //packet # + pEvent->Data[1] = HCIOPCODELOW(HCI_BT_AFH_MAP_NOTIFY, OGF_EXTENSION); + pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_AFH_MAP_NOTIFY, OGF_EXTENSION); + len = len + 3; + + // Return parameters starts from here + pRetPar = &pEvent->Data[len]; + pRetPar[0] = status; //status + + len++; + pEvent->Length = len; + + //total tx event length + EventCode length + sizeof(length) + tx_event_length = pEvent->Length + 2; + + status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE); + return status; + //bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); + } +} + +u8 rtw_btcoex_parse_BT_register_val_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen) +{ + + u8 localBuf[6] = ""; + u8 *pRetPar; + u8 len=0, tx_event_length =0; + rtw_HCI_event *pEvent; + RTW_HCI_STATUS status=HCI_STATUS_SUCCESS; + + { + pEvent = (rtw_HCI_event *)(&localBuf[0]); + + + pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE; + pEvent->Data[0] = 0x1; //packet # + pEvent->Data[1] = HCIOPCODELOW(HCI_BT_REGISTER_VALUE_NOTIFY, OGF_EXTENSION); + pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_REGISTER_VALUE_NOTIFY, OGF_EXTENSION); + len = len + 3; + + // Return parameters starts from here + pRetPar = &pEvent->Data[len]; + pRetPar[0] = status; //status + + len++; + pEvent->Length = len; + + //total tx event length + EventCode length + sizeof(length) + tx_event_length = pEvent->Length + 2; + + status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE); + return status; + //bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); + } +} + +u8 rtw_btcoex_parse_HCI_BT_abnormal_notify_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen) +{ + u8 localBuf[6] = ""; + u8 *pRetPar; + u8 len=0, tx_event_length =0; + rtw_HCI_event *pEvent; + RTW_HCI_STATUS status=HCI_STATUS_SUCCESS; + + { + pEvent = (rtw_HCI_event *)(&localBuf[0]); + + + pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE; + pEvent->Data[0] = 0x1; //packet # + pEvent->Data[1] = HCIOPCODELOW(HCI_BT_ABNORMAL_NOTIFY, OGF_EXTENSION); + pEvent->Data[2] = HCIOPCODEHIGHT(HCI_BT_ABNORMAL_NOTIFY, OGF_EXTENSION); + len = len + 3; + + // Return parameters starts from here + pRetPar = &pEvent->Data[len]; + pRetPar[0] = status; //status + + len++; + pEvent->Length = len; + + //total tx event length + EventCode length + sizeof(length) + tx_event_length = pEvent->Length + 2; + + status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE); + return status; + //bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); + } +} + +u8 rtw_btcoex_parse_HCI_query_RF_status_cmd(_adapter *padapter, u8 *pcmd, u16 cmdlen) +{ + u8 localBuf[6] = ""; + u8 *pRetPar; + u8 len=0, tx_event_length =0; + rtw_HCI_event *pEvent; + RTW_HCI_STATUS status=HCI_STATUS_SUCCESS; + + { + pEvent = (rtw_HCI_event *)(&localBuf[0]); + + + pEvent->EventCode = HCI_EVENT_COMMAND_COMPLETE; + pEvent->Data[0] = 0x1; //packet # + pEvent->Data[1] = HCIOPCODELOW(HCI_QUERY_RF_STATUS, OGF_EXTENSION); + pEvent->Data[2] = HCIOPCODEHIGHT(HCI_QUERY_RF_STATUS, OGF_EXTENSION); + len = len + 3; + + // Return parameters starts from here + pRetPar = &pEvent->Data[len]; + pRetPar[0] = status; //status + + len++; + pEvent->Length = len; + + //total tx event length + EventCode length + sizeof(length) + tx_event_length = pEvent->Length + 2; + + status = rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE); + return status; + //bthci_IndicateEvent(Adapter, PPacketIrpEvent, len+2); + } +} + +/***************************************** +* HCI cmd format : +*| 15 - 0 | +*| OPcode (OCF|OGF<<10) | +*| 15 - 8 |7 - 0 | +*|Cmd para |Cmd para Length | +*|Cmd para...... | +******************************************/ + +//bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +// | OCF | OGF | +void rtw_btcoex_parse_hci_extend_cmd(_adapter *padapter, u8 *pcmd, u16 len,const u16 hci_OCF) +{ + + DBG_871X("%s: OCF: %x\n",__func__,hci_OCF); + switch(hci_OCF) + { + case HCI_EXTENSION_VERSION_NOTIFY: + DBG_871X("HCI_EXTENSION_VERSION_NOTIFY\n"); + rtw_btcoex_parse_HCI_Ver_notify_cmd(padapter,pcmd, len); + break; + case HCI_LINK_STATUS_NOTIFY: + DBG_871X("HCI_LINK_STATUS_NOTIFY\n"); + rtw_btcoex_parse_HCI_link_status_notify_cmd(padapter,pcmd, len); + break; + case HCI_BT_OPERATION_NOTIFY: + // only for 8723a 2ant + DBG_871X("HCI_BT_OPERATION_NOTIFY\n"); + rtw_btcoex_parse_HCI_BT_operation_notify_cmd(padapter,pcmd, len); + // + break; + case HCI_ENABLE_WIFI_SCAN_NOTIFY: + DBG_871X("HCI_ENABLE_WIFI_SCAN_NOTIFY\n"); + rtw_btcoex_parse_WIFI_scan_notify_cmd(padapter,pcmd, len); + break; + case HCI_QUERY_RF_STATUS: + // only for 8723b 2ant + DBG_871X("HCI_QUERY_RF_STATUS\n"); + rtw_btcoex_parse_HCI_query_RF_status_cmd(padapter,pcmd, len); + break; + case HCI_BT_ABNORMAL_NOTIFY: + DBG_871X("HCI_BT_ABNORMAL_NOTIFY\n"); + rtw_btcoex_parse_HCI_BT_abnormal_notify_cmd(padapter,pcmd, len); + break; + case HCI_BT_INFO_NOTIFY: + DBG_871X("HCI_BT_INFO_NOTIFY\n"); + rtw_btcoex_parse_BT_info_notify_cmd(padapter,pcmd, len); + break; + case HCI_BT_COEX_NOTIFY: + DBG_871X("HCI_BT_COEX_NOTIFY\n"); + rtw_btcoex_parse_HCI_BT_coex_notify_cmd(padapter,pcmd, len); + break; + case HCI_BT_PATCH_VERSION_NOTIFY: + DBG_871X("HCI_BT_PATCH_VERSION_NOTIFY\n"); + rtw_btcoex_parse_BT_patch_ver_info_cmd(padapter,pcmd, len); + break; + case HCI_BT_AFH_MAP_NOTIFY: + DBG_871X("HCI_BT_AFH_MAP_NOTIFY\n"); + rtw_btcoex_parse_BT_AFH_MAP_notify_cmd(padapter,pcmd, len); + break; + case HCI_BT_REGISTER_VALUE_NOTIFY: + DBG_871X("HCI_BT_REGISTER_VALUE_NOTIFY\n"); + rtw_btcoex_parse_BT_register_val_notify_cmd(padapter,pcmd, len); + break; + default: + DBG_871X("ERROR!!! Unknown OCF: %x\n",hci_OCF); + break; + + } +} + +void rtw_btcoex_parse_hci_cmd(_adapter *padapter, u8 *pcmd, u16 len) +{ + u16 opcode = pcmd[0] | pcmd[1]<<8; + u16 hci_OGF = HCI_OGF(opcode); + u16 hci_OCF = HCI_OCF(opcode); + u8 cmdlen = len -3; + u8 pare_len = pcmd[2]; + + DBG_871X("%s OGF: %x,OCF: %x\n", __func__, hci_OGF, hci_OCF); + switch(hci_OGF) + { + case OGF_EXTENSION: + DBG_871X("HCI_EXTENSION_CMD_OGF\n"); + rtw_btcoex_parse_hci_extend_cmd(padapter, &pcmd[3], cmdlen, hci_OCF); + break; + default: + DBG_871X("Other OGF: %x\n",hci_OGF); + break; + } +} + +u16 rtw_btcoex_parse_recv_data(u8 *msg, u8 msg_size) +{ + u8 cmp_msg1[32] = attend_ack; + u8 cmp_msg2[32] = leave_ack; + u8 cmp_msg3[32] = bt_leave; + u8 cmp_msg4[32] = invite_req; + u8 cmp_msg5[32] = attend_req; + u8 cmp_msg6[32] = invite_rsp; + u8 res = OTHER; + + if (_rtw_memcmp(cmp_msg1, msg, msg_size) == _TRUE) { + /*DBG_871X("%s, msg:%s\n",__func__,msg);*/ + res = RX_ATTEND_ACK; + } else if (_rtw_memcmp(cmp_msg2, msg, msg_size) == _TRUE) { + /*DBG_871X("%s, msg:%s\n",__func__,msg);*/ + res = RX_LEAVE_ACK; + } else if (_rtw_memcmp(cmp_msg3, msg, msg_size) == _TRUE) { + /*DBG_871X("%s, msg:%s\n",__func__,msg);*/ + res = RX_BT_LEAVE; + } else if (_rtw_memcmp(cmp_msg4, msg, msg_size) == _TRUE) { + /*DBG_871X("%s, msg:%s\n",__func__,msg);*/ + res = RX_INVITE_REQ; + } else if (_rtw_memcmp(cmp_msg5, msg, msg_size) == _TRUE) { + res = RX_ATTEND_REQ; + } else if (_rtw_memcmp(cmp_msg6, msg, msg_size) == _TRUE) { + res = RX_INVITE_RSP; + } else { + /*DBG_871X("%s, %s\n", __func__, msg);*/ + res = OTHER; + } + + /*DBG_871X("%s, res:%d\n", __func__, res);*/ + + return res; +} + +void rtw_btcoex_recvmsgbysocket(void *data) +{ + u8 recv_data[255]; + u8 tx_msg[255] = leave_ack; + u32 len = 0; + u16 recv_length = 0; + u16 parse_res = 0; +#if 0 + u8 para_len = 0, polling_enable = 0, poling_interval = 0, reason = 0, btinfo_len = 0; + u8 btinfo[BT_INFO_LEN] = {0}; +#endif + + struct bt_coex_info *pcoex_info = NULL; + struct sock *sk = NULL; + struct sk_buff *skb = NULL; + + /*DBG_871X("%s\n",__func__);*/ + + if (pbtcoexadapter == NULL) { + DBG_871X("%s: btcoexadapter NULL!\n", __func__); + return; + } + + pcoex_info = &pbtcoexadapter->coex_info; + sk = pcoex_info->sk_store; + + if (sk == NULL) { + DBG_871X("%s: critical error when receive socket data!\n", __func__); + return; + } + + len = skb_queue_len(&sk->sk_receive_queue); + while (len > 0) { + skb = skb_dequeue(&sk->sk_receive_queue); + + /*important: cut the udp header from skb->data! header length is 8 byte*/ + recv_length = skb->len-8; + _rtw_memset(recv_data, 0, sizeof(recv_data)); + _rtw_memcpy(recv_data, skb->data+8, recv_length); + + parse_res = rtw_btcoex_parse_recv_data(recv_data, recv_length); +/* + if (RX_ATTEND_ACK == parse_res) { + //attend ack + pcoex_info->BT_attend = _TRUE; + DBG_871X("RX_ATTEND_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend); + } else if (RX_ATTEND_REQ == parse_res) { + //attend req from BT + pcoex_info->BT_attend = _TRUE; + DBG_871X("RX_BT_ATTEND_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend); + rtw_btcoex_sendmsgbysocket(pbtcoexadapter, attend_ack, sizeof(attend_ack), _FALSE); + } else if (RX_INVITE_REQ == parse_res) { + //invite req from BT + pcoex_info->BT_attend = _TRUE; + DBG_871X("RX_INVITE_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend); + rtw_btcoex_sendmsgbysocket(pbtcoexadapter, invite_rsp, sizeof(invite_rsp), _FALSE); + } else if (RX_INVITE_RSP == parse_res) { + //invite rsp + pcoex_info->BT_attend = _TRUE; + DBG_871X("RX_INVITE_RSP!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend); + } else if (RX_LEAVE_ACK == parse_res) { + //mean BT know wifi will leave + pcoex_info->BT_attend = _FALSE; + DBG_871X("RX_LEAVE_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend); + } else if (RX_BT_LEAVE == parse_res) { + //BT leave + rtw_btcoex_sendmsgbysocket(pbtcoexadapter, leave_ack, sizeof(leave_ack), _FALSE); // no ack + pcoex_info->BT_attend = _FALSE; + DBG_871X("RX_BT_LEAVE!sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend); + } else { + //todo: check if recv data are really hci cmds + if (_TRUE == pcoex_info->BT_attend) + rtw_btcoex_parse_hci_cmd(pbtcoexadapter, recv_data, recv_length); + } +*/ + switch (parse_res) { + case RX_ATTEND_ACK: + /* attend ack */ + pcoex_info->BT_attend = _TRUE; + DBG_871X("RX_ATTEND_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend); + rtw_btcoex_BTOffOnNotify(pbtcoexadapter, pcoex_info->BT_attend); + break; + + case RX_ATTEND_REQ: + pcoex_info->BT_attend = _TRUE; + DBG_871X("RX_BT_ATTEND_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend); + rtw_btcoex_sendmsgbysocket(pbtcoexadapter, attend_ack, sizeof(attend_ack), _FALSE); + rtw_btcoex_BTOffOnNotify(pbtcoexadapter, pcoex_info->BT_attend); + break; + + case RX_INVITE_REQ: + /* invite req from BT */ + pcoex_info->BT_attend = _TRUE; + DBG_871X("RX_INVITE_REQ!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend); + rtw_btcoex_sendmsgbysocket(pbtcoexadapter, invite_rsp, sizeof(invite_rsp), _FALSE); + rtw_btcoex_BTOffOnNotify(pbtcoexadapter, pcoex_info->BT_attend); + break; + + case RX_INVITE_RSP: + /*invite rsp*/ + pcoex_info->BT_attend = _TRUE; + DBG_871X("RX_INVITE_RSP!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend); + rtw_btcoex_BTOffOnNotify(pbtcoexadapter, pcoex_info->BT_attend); + break; + + case RX_LEAVE_ACK: + /* mean BT know wifi will leave */ + pcoex_info->BT_attend = _FALSE; + DBG_871X("RX_LEAVE_ACK!,sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend); + rtw_btcoex_BTOffOnNotify(pbtcoexadapter, pcoex_info->BT_attend); + break; + + case RX_BT_LEAVE: + /* BT leave */ + rtw_btcoex_sendmsgbysocket(pbtcoexadapter, leave_ack, sizeof(leave_ack), _FALSE); /* no ack */ + pcoex_info->BT_attend = _FALSE; + DBG_871X("RX_BT_LEAVE!sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend); + rtw_btcoex_BTOffOnNotify(pbtcoexadapter, pcoex_info->BT_attend); + break; + + default: + if (_TRUE == pcoex_info->BT_attend) + rtw_btcoex_parse_hci_cmd(pbtcoexadapter, recv_data, recv_length); + else + DBG_871X("ERROR!! BT is UP\n"); + break; + + } + + len--; + kfree_skb(skb); + } +} + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 15, 0)) +void rtw_btcoex_recvmsg_init(struct sock *sk_in, s32 bytes) +#else +void rtw_btcoex_recvmsg_init(struct sock *sk_in) +#endif +{ + struct bt_coex_info *pcoex_info = NULL; + + if (pbtcoexadapter == NULL) { + DBG_871X("%s: btcoexadapter NULL\n", __func__); + return; + } + pcoex_info = &pbtcoexadapter->coex_info; + pcoex_info->sk_store = sk_in; + if (pcoex_info->btcoex_wq != NULL) + queue_delayed_work(pcoex_info->btcoex_wq, &pcoex_info->recvmsg_work, 0); + else + DBG_871X("%s: BTCOEX workqueue NULL\n", __func__); +} + +u8 rtw_btcoex_sendmsgbysocket(_adapter *padapter, u8 *msg, u8 msg_size, bool force) +{ + u8 error; + struct msghdr udpmsg; +#ifdef set_fs + mm_segment_t oldfs; +#endif + struct iovec iov; + struct bt_coex_info *pcoex_info = &padapter->coex_info; + + /* DBG_871X("%s: msg:%s, force:%s\n", __func__, msg, force == _TRUE?"TRUE":"FALSE"); */ + if (_FALSE == force) { + if (_FALSE == pcoex_info->BT_attend) { + DBG_871X("TX Blocked: WiFi-BT disconnected\n"); + return _FAIL; + } + } + + iov.iov_base = (void *)msg; + iov.iov_len = msg_size; + udpmsg.msg_name = &pcoex_info->bt_sockaddr; + udpmsg.msg_namelen = sizeof(struct sockaddr_in); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) + /* referece:sock_xmit in kernel code + * WRITE for sock_sendmsg, READ for sock_recvmsg + * third parameter for msg_iovlen + * last parameter for iov_len + */ + iov_iter_init(&udpmsg.msg_iter, WRITE, &iov, 1, msg_size); +#else + udpmsg.msg_iov = &iov; + udpmsg.msg_iovlen = 1; +#endif + udpmsg.msg_control = NULL; + udpmsg.msg_controllen = 0; + udpmsg.msg_flags = MSG_DONTWAIT | MSG_NOSIGNAL; +#ifdef set_fs + oldfs = get_fs(); + set_fs(KERNEL_DS); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) + error = sock_sendmsg(pcoex_info->udpsock, &udpmsg); +#else + error = sock_sendmsg(pcoex_info->udpsock, &udpmsg, msg_size); +#endif +#ifdef set_fs + set_fs(oldfs); +#endif + if (error < 0) { + DBG_871X("Error when sendimg msg, error:%d\n", error); + return _FAIL; + } else + return _SUCCESS; +} + +u8 rtw_btcoex_create_kernel_socket(_adapter *padapter) +{ + s8 kernel_socket_err; + u8 tx_msg[255] = attend_req; + struct bt_coex_info *pcoex_info = &padapter->coex_info; + s32 sock_reuse = 1; + u8 status = _FAIL; + + DBG_871X("%s CONNECT_PORT %d\n", __func__, CONNECT_PORT); + + if (NULL == pcoex_info) { + DBG_871X("coex_info: NULL\n"); + status = _FAIL; + } + + kernel_socket_err = sock_create(PF_INET, SOCK_DGRAM, 0, &pcoex_info->udpsock); + + if (kernel_socket_err < 0) { + DBG_871X("Error during creation of socket error:%d\n", kernel_socket_err); + status = _FAIL; + } else { + _rtw_memset(&(pcoex_info->wifi_sockaddr), 0, sizeof(pcoex_info->wifi_sockaddr)); + pcoex_info->wifi_sockaddr.sin_family = AF_INET; + pcoex_info->wifi_sockaddr.sin_port = htons(CONNECT_PORT); + pcoex_info->wifi_sockaddr.sin_addr.s_addr = htonl(INADDR_LOOPBACK); + + _rtw_memset(&(pcoex_info->bt_sockaddr), 0, sizeof(pcoex_info->bt_sockaddr)); + pcoex_info->bt_sockaddr.sin_family = AF_INET; + pcoex_info->bt_sockaddr.sin_port = htons(CONNECT_PORT_BT); + pcoex_info->bt_sockaddr.sin_addr.s_addr = htonl(INADDR_LOOPBACK); + + pcoex_info->sk_store = NULL; + kernel_socket_err = pcoex_info->udpsock->ops->bind(pcoex_info->udpsock, (struct sockaddr *)&pcoex_info->wifi_sockaddr, + sizeof(pcoex_info->wifi_sockaddr)); + if (kernel_socket_err == 0) { + DBG_871X("binding socket success\n"); + pcoex_info->udpsock->sk->sk_data_ready = rtw_btcoex_recvmsg_init; + pcoex_info->sock_open |= KERNEL_SOCKET_OK; + pcoex_info->BT_attend = _FALSE; + DBG_871X("WIFI sending attend_req\n"); + rtw_btcoex_sendmsgbysocket(padapter, attend_req, sizeof(attend_req), _TRUE); + status = _SUCCESS; + } else { + pcoex_info->BT_attend = _FALSE; + sock_release(pcoex_info->udpsock); /* bind fail release socket */ + DBG_871X("Error binding socket: %d\n", kernel_socket_err); + status = _FAIL; + } + + } + + return status; +} + +void rtw_btcoex_close_kernel_socket(_adapter *padapter) +{ + struct bt_coex_info *pcoex_info = &padapter->coex_info; + if (pcoex_info->sock_open & KERNEL_SOCKET_OK) { + DBG_871X("release kernel socket\n"); + sock_release(pcoex_info->udpsock); + pcoex_info->sock_open &= ~(KERNEL_SOCKET_OK); + if (_TRUE == pcoex_info->BT_attend) + pcoex_info->BT_attend = _FALSE; + + DBG_871X("sock_open:%d, BT_attend:%d\n", pcoex_info->sock_open, pcoex_info->BT_attend); + } +} + +void rtw_btcoex_init_socket(_adapter *padapter) +{ + + u8 is_invite = _FALSE; + struct bt_coex_info *pcoex_info = &padapter->coex_info; + DBG_871X("%s\n", __func__); + if (_FALSE == pcoex_info->is_exist) { + _rtw_memset(pcoex_info,0,sizeof(struct bt_coex_info)); + pcoex_info->btcoex_wq = create_workqueue("BTCOEX"); + INIT_DELAYED_WORK(&pcoex_info->recvmsg_work, + (void *)rtw_btcoex_recvmsgbysocket); + pbtcoexadapter = padapter; + /* We expect BT is off if BT don't send ack to wifi */ + DBG_871X("We expect BT is off if BT send ack to wifi\n"); + rtw_btcoex_BTOffOnNotify(pbtcoexadapter, _FALSE); + if (rtw_btcoex_create_kernel_socket(padapter) == _SUCCESS) { + pcoex_info->is_exist = _TRUE; + } else { + pcoex_info->is_exist = _FALSE; + pbtcoexadapter = NULL; + } + + DBG_871X("%s: pbtcoexadapter:%p, coex_info->is_exist: %s\n" + , __func__, pbtcoexadapter, pcoex_info->is_exist == _TRUE?"TRUE":"FALSE"); + } +} + +void rtw_btcoex_close_socket(_adapter *padapter) +{ + struct bt_coex_info *pcoex_info = &padapter->coex_info; + + DBG_871X("%s--coex_info->is_exist: %s, pcoex_info->BT_attend:%s\n" + , __func__, pcoex_info->is_exist == _TRUE?"TRUE":"FALSE", pcoex_info->BT_attend == _TRUE?"TRUE":"FALSE"); + + if (_TRUE == pcoex_info->is_exist) { + if (_TRUE == pcoex_info->BT_attend) { + /*inform BT wifi leave*/ + rtw_btcoex_sendmsgbysocket(padapter, wifi_leave, sizeof(wifi_leave), _FALSE); + msleep(50); + } + rtw_btcoex_close_kernel_socket(padapter); + pbtcoexadapter = NULL; + pcoex_info->is_exist = _FALSE; + } + if (pcoex_info->btcoex_wq != NULL) { + flush_workqueue(pcoex_info->btcoex_wq); + destroy_workqueue(pcoex_info->btcoex_wq); + } +} + +void rtw_btcoex_dump_tx_msg(u8 *tx_msg, u8 len, u8 *msg_name) +{ + u8 i = 0; + DBG_871X("======> Msg name: %s\n", msg_name); + for(i=0;iEventCode = HCI_EVENT_EXTENSION_RTK; + pEvent->Data[0] = HCI_EVENT_EXT_BT_COEX_CONTROL; //extension event code + len ++; + + // Return parameters starts from here + pRetPar = &pEvent->Data[len]; + _rtw_memcpy(&pRetPar[0], pData, dataLen); + + len += dataLen; + + pEvent->Length = len; + + //total tx event length + EventCode length + sizeof(length) + tx_event_length = pEvent->Length + 2; +#if 0 + rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "BT COEX CONTROL", _FALSE); +#endif + rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE); + +} + +/* Porting from Windows team */ +void rtw_btcoex_SendEventExtBtInfoControl(PADAPTER padapter, u8 dataLen, void *pData) +{ + rtw_HCI_event *pEvent; + u8 *pRetPar; + u8 len=0, tx_event_length = 0; + u8 localBuf[32] = ""; + + struct bt_coex_info *pcoex_info = &padapter->coex_info; + PBT_MGNT pBtMgnt = &pcoex_info->BtMgnt; + + /* DBG_871X("%s\n",__func__);*/ + if(pBtMgnt->ExtConfig.HCIExtensionVer < 4) //not support + { + DBG_871X("ERROR: HCIExtensionVer = %d, HCIExtensionVer<4 !!!!\n",pBtMgnt->ExtConfig.HCIExtensionVer); + return; + } + + pEvent = (rtw_HCI_event *)(&localBuf[0]); + + //len += bthci_ExtensionEventHeaderRtk(&localBuf[0], + // HCI_EVENT_EXT_BT_INFO_CONTROL); + pEvent->EventCode = HCI_EVENT_EXTENSION_RTK; + pEvent->Data[0] = HCI_EVENT_EXT_BT_INFO_CONTROL; //extension event code + len ++; + + // Return parameters starts from here + pRetPar = &pEvent->Data[len]; + _rtw_memcpy(&pRetPar[0], pData, dataLen); + + len += dataLen; + + pEvent->Length = len; + + //total tx event length + EventCode length + sizeof(length) + tx_event_length = pEvent->Length + 2; +#if 0 + rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "BT INFO CONTROL"); +#endif + rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE); + +} + +void rtw_btcoex_SendScanNotify(PADAPTER padapter, u8 scanType) +{ + u8 len=0, tx_event_length=0; + u8 localBuf[7] = ""; + u8 *pRetPar; + u8 *pu1Temp; + rtw_HCI_event *pEvent; + struct bt_coex_info *pcoex_info = &padapter->coex_info; + PBT_MGNT pBtMgnt = &pcoex_info->BtMgnt; + +// if(!pBtMgnt->BtOperationOn) +// return; + + pEvent = (rtw_HCI_event *)(&localBuf[0]); + +// len += bthci_ExtensionEventHeaderRtk(&localBuf[0], +// HCI_EVENT_EXT_WIFI_SCAN_NOTIFY); + + pEvent->EventCode = HCI_EVENT_EXTENSION_RTK; + pEvent->Data[0] = HCI_EVENT_EXT_WIFI_SCAN_NOTIFY; //extension event code + len ++; + + // Return parameters starts from here + //pRetPar = &PPacketIrpEvent->Data[len]; + //pu1Temp = (u8 *)&pRetPar[0]; + //*pu1Temp = scanType; + pEvent->Data[len] = scanType; + len += 1; + + pEvent->Length = len; + + //total tx event length + EventCode length + sizeof(length) + tx_event_length = pEvent->Length + 2; +#if 0 + rtw_btcoex_dump_tx_msg((u8 *)pEvent, tx_event_length, "WIFI SCAN OPERATION"); +#endif + rtw_btcoex_sendmsgbysocket(padapter, (u8 *)pEvent, tx_event_length, _FALSE); +} +#endif //CONFIG_BT_COEXIST_SOCKET_TRX +#endif // CONFIG_BT_COEXIST + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_cmd.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_cmd.c new file mode 100644 index 000000000..1dfb22ced --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_cmd.c @@ -0,0 +1,4888 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_CMD_C_ + +#include +#include + +#ifndef DBG_CMD_EXECUTE + #define DBG_CMD_EXECUTE 0 +#endif + +/* +Caller and the rtw_cmd_thread can protect cmd_q by spin_lock. +No irqsave is necessary. +*/ + +sint _rtw_init_cmd_priv (struct cmd_priv *pcmdpriv) +{ + sint res=_SUCCESS; + +_func_enter_; + + _rtw_init_sema(&(pcmdpriv->cmd_queue_sema), 0); + //_rtw_init_sema(&(pcmdpriv->cmd_done_sema), 0); + _rtw_init_sema(&(pcmdpriv->terminate_cmdthread_sema), 0); + + + _rtw_init_queue(&(pcmdpriv->cmd_queue)); + + //allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf + + pcmdpriv->cmd_seq = 1; + + pcmdpriv->cmd_allocated_buf = rtw_zmalloc(MAX_CMDSZ + CMDBUFF_ALIGN_SZ); + + if (pcmdpriv->cmd_allocated_buf == NULL){ + res= _FAIL; + goto exit; + } + + pcmdpriv->cmd_buf = pcmdpriv->cmd_allocated_buf + CMDBUFF_ALIGN_SZ - ( (SIZE_PTR)(pcmdpriv->cmd_allocated_buf) & (CMDBUFF_ALIGN_SZ-1)); + + pcmdpriv->rsp_allocated_buf = rtw_zmalloc(MAX_RSPSZ + 4); + + if (pcmdpriv->rsp_allocated_buf == NULL){ + res= _FAIL; + goto exit; + } + + pcmdpriv->rsp_buf = pcmdpriv->rsp_allocated_buf + 4 - ( (SIZE_PTR)(pcmdpriv->rsp_allocated_buf) & 3); + + pcmdpriv->cmd_issued_cnt = pcmdpriv->cmd_done_cnt = pcmdpriv->rsp_cnt = 0; + + _rtw_mutex_init(&pcmdpriv->sctx_mutex); +exit: + +_func_exit_; + + return res; + +} + +#ifdef CONFIG_C2H_WK +static void c2h_wk_callback(_workitem *work); +#endif +sint _rtw_init_evt_priv(struct evt_priv *pevtpriv) +{ + sint res=_SUCCESS; + +_func_enter_; + +#ifdef CONFIG_H2CLBK + _rtw_init_sema(&(pevtpriv->lbkevt_done), 0); + pevtpriv->lbkevt_limit = 0; + pevtpriv->lbkevt_num = 0; + pevtpriv->cmdevt_parm = NULL; +#endif + + //allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf + ATOMIC_SET(&pevtpriv->event_seq, 0); + pevtpriv->evt_done_cnt = 0; + +#ifdef CONFIG_EVENT_THREAD_MODE + + _rtw_init_sema(&(pevtpriv->evt_notify), 0); + _rtw_init_sema(&(pevtpriv->terminate_evtthread_sema), 0); + + pevtpriv->evt_allocated_buf = rtw_zmalloc(MAX_EVTSZ + 4); + if (pevtpriv->evt_allocated_buf == NULL){ + res= _FAIL; + goto exit; + } + pevtpriv->evt_buf = pevtpriv->evt_allocated_buf + 4 - ((unsigned int)(pevtpriv->evt_allocated_buf) & 3); + + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + pevtpriv->allocated_c2h_mem = rtw_zmalloc(C2H_MEM_SZ +4); + + if (pevtpriv->allocated_c2h_mem == NULL){ + res= _FAIL; + goto exit; + } + + pevtpriv->c2h_mem = pevtpriv->allocated_c2h_mem + 4\ + - ( (u32)(pevtpriv->allocated_c2h_mem) & 3); +#ifdef PLATFORM_OS_XP + pevtpriv->pc2h_mdl= IoAllocateMdl((u8 *)pevtpriv->c2h_mem, C2H_MEM_SZ , FALSE, FALSE, NULL); + + if(pevtpriv->pc2h_mdl == NULL){ + res= _FAIL; + goto exit; + } + MmBuildMdlForNonPagedPool(pevtpriv->pc2h_mdl); +#endif +#endif //end of CONFIG_SDIO_HCI + + _rtw_init_queue(&(pevtpriv->evt_queue)); + +exit: + +#endif //end of CONFIG_EVENT_THREAD_MODE + +#ifdef CONFIG_C2H_WK + _init_workitem(&pevtpriv->c2h_wk, c2h_wk_callback, NULL); + pevtpriv->c2h_wk_alive = _FALSE; + pevtpriv->c2h_queue = rtw_cbuf_alloc(C2H_QUEUE_MAX_LEN+1); +#endif + +_func_exit_; + + return res; +} + +void _rtw_free_evt_priv (struct evt_priv *pevtpriv) +{ +_func_enter_; + + RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("+_rtw_free_evt_priv \n")); + +#ifdef CONFIG_EVENT_THREAD_MODE + _rtw_free_sema(&(pevtpriv->evt_notify)); + _rtw_free_sema(&(pevtpriv->terminate_evtthread_sema)); + + + if (pevtpriv->evt_allocated_buf) + rtw_mfree(pevtpriv->evt_allocated_buf, MAX_EVTSZ + 4); +#endif + +#ifdef CONFIG_C2H_WK + _cancel_workitem_sync(&pevtpriv->c2h_wk); + while(pevtpriv->c2h_wk_alive) + rtw_msleep_os(10); + + while (!rtw_cbuf_empty(pevtpriv->c2h_queue)) { + void *c2h; + if ((c2h = rtw_cbuf_pop(pevtpriv->c2h_queue)) != NULL + && c2h != (void *)pevtpriv) { + rtw_mfree(c2h, 16); + } + } + rtw_cbuf_free(pevtpriv->c2h_queue); +#endif + + RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("-_rtw_free_evt_priv \n")); + +_func_exit_; + +} + +void _rtw_free_cmd_priv (struct cmd_priv *pcmdpriv) +{ +_func_enter_; + + if(pcmdpriv){ + _rtw_spinlock_free(&(pcmdpriv->cmd_queue.lock)); + _rtw_free_sema(&(pcmdpriv->cmd_queue_sema)); + //_rtw_free_sema(&(pcmdpriv->cmd_done_sema)); + _rtw_free_sema(&(pcmdpriv->terminate_cmdthread_sema)); + + if (pcmdpriv->cmd_allocated_buf) + rtw_mfree(pcmdpriv->cmd_allocated_buf, MAX_CMDSZ + CMDBUFF_ALIGN_SZ); + + if (pcmdpriv->rsp_allocated_buf) + rtw_mfree(pcmdpriv->rsp_allocated_buf, MAX_RSPSZ + 4); + + _rtw_mutex_free(&pcmdpriv->sctx_mutex); + } +_func_exit_; +} + +/* +Calling Context: + +rtw_enqueue_cmd can only be called between kernel thread, +since only spin_lock is used. + +ISR/Call-Back functions can't call this sub-function. + +*/ +#ifdef DBG_CMD_QUEUE +extern u8 dump_cmd_id; +#endif + +sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj, bool to_head) +{ + _irqL irqL; + +_func_enter_; + + if (obj == NULL) + goto exit; + + //_enter_critical_bh(&queue->lock, &irqL); + _enter_critical(&queue->lock, &irqL); + + if (to_head) + rtw_list_insert_head(&obj->list, &queue->queue); + else + rtw_list_insert_tail(&obj->list, &queue->queue); + + #ifdef DBG_CMD_QUEUE + if(dump_cmd_id){ + printk("%s===> cmdcode:0x%02x\n",__FUNCTION__,obj->cmdcode); + if(obj->cmdcode == GEN_CMD_CODE(_Set_MLME_EVT)){ + if(obj->parmbuf){ + struct C2HEvent_Header *pc2h_evt_hdr = (struct C2HEvent_Header *)(obj->parmbuf); + printk("pc2h_evt_hdr->ID:0x%02x(%d)\n",pc2h_evt_hdr->ID,pc2h_evt_hdr->ID); + } + } + if(obj->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra)){ + if(obj->parmbuf){ + struct drvextra_cmd_parm *pdrvextra_cmd_parm =(struct drvextra_cmd_parm*)(obj->parmbuf); + printk("pdrvextra_cmd_parm->ec_id:0x%02x\n",pdrvextra_cmd_parm->ec_id); + } + } + } + + if (queue->queue.prev->next != &queue->queue) + { + DBG_871X("[%d] head %p, tail %p, tail->prev->next %p[tail], tail->next %p[head]\n", __LINE__, + &queue->queue, queue->queue.prev, queue->queue.prev->prev->next, queue->queue.prev->next); + + DBG_871X("==========%s============\n",__FUNCTION__); + DBG_871X("head:%p,obj_addr:%p\n",&queue->queue,obj); + DBG_871X("padapter: %p\n",obj->padapter); + DBG_871X("cmdcode: 0x%02x\n",obj->cmdcode); + DBG_871X("res: %d\n",obj->res); + DBG_871X("parmbuf: %p\n",obj->parmbuf); + DBG_871X("cmdsz: %d\n",obj->cmdsz); + DBG_871X("rsp: %p\n",obj->rsp); + DBG_871X("rspsz: %d\n",obj->rspsz); + DBG_871X("sctx: %p\n",obj->sctx); + DBG_871X("list->next: %p\n",obj->list.next); + DBG_871X("list->prev: %p\n",obj->list.prev); + } + #endif //DBG_CMD_QUEUE + + //_exit_critical_bh(&queue->lock, &irqL); + _exit_critical(&queue->lock, &irqL); + +exit: + +_func_exit_; + + return _SUCCESS; +} + +struct cmd_obj *_rtw_dequeue_cmd(_queue *queue) +{ + _irqL irqL; + struct cmd_obj *obj; + +_func_enter_; + + //_enter_critical_bh(&(queue->lock), &irqL); + _enter_critical(&queue->lock, &irqL); + + #ifdef DBG_CMD_QUEUE + if (queue->queue.prev->next != &queue->queue) + { + DBG_871X("[%d] head %p, tail %p, tail->prev->next %p[tail], tail->next %p[head]\n", __LINE__, + &queue->queue, queue->queue.prev, queue->queue.prev->prev->next, queue->queue.prev->next); + } + #endif //DBG_CMD_QUEUE + + + if (rtw_is_list_empty(&(queue->queue))){ + obj = NULL; + } + else + { + obj = LIST_CONTAINOR(get_next(&(queue->queue)), struct cmd_obj, list); + + #ifdef DBG_CMD_QUEUE + if (queue->queue.prev->next != &queue->queue){ + DBG_871X("==========%s============\n",__FUNCTION__); + DBG_871X("head:%p,obj_addr:%p\n",&queue->queue,obj); + DBG_871X("padapter: %p\n",obj->padapter); + DBG_871X("cmdcode: 0x%02x\n",obj->cmdcode); + DBG_871X("res: %d\n",obj->res); + DBG_871X("parmbuf: %p\n",obj->parmbuf); + DBG_871X("cmdsz: %d\n",obj->cmdsz); + DBG_871X("rsp: %p\n",obj->rsp); + DBG_871X("rspsz: %d\n",obj->rspsz); + DBG_871X("sctx: %p\n",obj->sctx); + DBG_871X("list->next: %p\n",obj->list.next); + DBG_871X("list->prev: %p\n",obj->list.prev); + } + + if(dump_cmd_id){ + DBG_871X("%s===> cmdcode:0x%02x\n",__FUNCTION__,obj->cmdcode); + if(obj->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra)){ + if(obj->parmbuf){ + struct drvextra_cmd_parm *pdrvextra_cmd_parm =(struct drvextra_cmd_parm*)(obj->parmbuf); + printk("pdrvextra_cmd_parm->ec_id:0x%02x\n",pdrvextra_cmd_parm->ec_id); + } + } + + } + #endif //DBG_CMD_QUEUE + + rtw_list_delete(&obj->list); + } + + //_exit_critical_bh(&(queue->lock), &irqL); + _exit_critical(&queue->lock, &irqL); + +_func_exit_; + + return obj; +} + +u32 rtw_init_cmd_priv(struct cmd_priv *pcmdpriv) +{ + u32 res; +_func_enter_; + res = _rtw_init_cmd_priv (pcmdpriv); +_func_exit_; + return res; +} + +u32 rtw_init_evt_priv (struct evt_priv *pevtpriv) +{ + int res; +_func_enter_; + res = _rtw_init_evt_priv(pevtpriv); +_func_exit_; + return res; +} + +void rtw_free_evt_priv (struct evt_priv *pevtpriv) +{ +_func_enter_; + RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("rtw_free_evt_priv\n")); + _rtw_free_evt_priv(pevtpriv); +_func_exit_; +} + +void rtw_free_cmd_priv (struct cmd_priv *pcmdpriv) +{ +_func_enter_; + RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("rtw_free_cmd_priv\n")); + _rtw_free_cmd_priv(pcmdpriv); +_func_exit_; +} + +int rtw_cmd_filter(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj); +int rtw_cmd_filter(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj) +{ + u8 bAllow = _FALSE; //set to _TRUE to allow enqueuing cmd when hw_init_completed is _FALSE + + #ifdef SUPPORT_HW_RFOFF_DETECTED + //To decide allow or not + if( (adapter_to_pwrctl(pcmdpriv->padapter)->bHWPwrPindetect) + &&(!pcmdpriv->padapter->registrypriv.usbss_enable) + ) + { + if(cmd_obj->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra) ) + { + struct drvextra_cmd_parm *pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)cmd_obj->parmbuf; + if(pdrvextra_cmd_parm->ec_id == POWER_SAVING_CTRL_WK_CID) + { + //DBG_871X("==>enqueue POWER_SAVING_CTRL_WK_CID\n"); + bAllow = _TRUE; + } + } + } + #endif + +#ifndef CONFIG_C2H_PACKET_EN + /* C2H should be always allowed */ + if(cmd_obj->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra)) { + struct drvextra_cmd_parm *pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)cmd_obj->parmbuf; + if(pdrvextra_cmd_parm->ec_id == C2H_WK_CID) { + bAllow = _TRUE; + } + } +#endif + + if(cmd_obj->cmdcode == GEN_CMD_CODE(_SetChannelPlan)) + bAllow = _TRUE; + + if (cmd_obj->no_io) + bAllow = _TRUE; + + if ((!rtw_is_hw_init_completed(pcmdpriv->padapter) && (bAllow == _FALSE)) + || ATOMIC_READ(&(pcmdpriv->cmdthd_running)) == _FALSE //com_thread not running + ) { + if (DBG_CMD_EXECUTE) + DBG_871X(ADPT_FMT" drop "CMD_FMT" hw_init_completed:%u, cmdthd_running:%u\n", ADPT_ARG(cmd_obj->padapter) + , CMD_ARG(cmd_obj), rtw_get_hw_init_completed(cmd_obj->padapter), ATOMIC_READ(&pcmdpriv->cmdthd_running)); + if (0) + rtw_warn_on(1); + + return _FAIL; + } + return _SUCCESS; +} + + + +u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj) +{ + int res = _FAIL; + PADAPTER padapter = pcmdpriv->padapter; + +_func_enter_; + + if (cmd_obj == NULL) { + goto exit; + } + + cmd_obj->padapter = padapter; + +#ifdef CONFIG_CONCURRENT_MODE + //change pcmdpriv to primary's pcmdpriv + if (padapter->adapter_type != PRIMARY_ADAPTER && padapter->pbuddy_adapter) + pcmdpriv = &(padapter->pbuddy_adapter->cmdpriv); +#endif + + res = rtw_cmd_filter(pcmdpriv, cmd_obj); + if ((_FAIL == res) || (cmd_obj->cmdsz > MAX_CMDSZ)) { + if (cmd_obj->cmdsz > MAX_CMDSZ) { + DBG_871X("%s failed due to obj->cmdsz(%d) > MAX_CMDSZ(%d)\n", __func__, cmd_obj->cmdsz, MAX_CMDSZ); + rtw_warn_on(1); + } + + if (cmd_obj->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra)) { + struct drvextra_cmd_parm *extra_parm = (struct drvextra_cmd_parm *)cmd_obj->parmbuf; + + if (extra_parm->pbuf && extra_parm->size > 0) + rtw_mfree(extra_parm->pbuf, extra_parm->size); + } + rtw_free_cmd_obj(cmd_obj); + goto exit; + } + + res = _rtw_enqueue_cmd(&pcmdpriv->cmd_queue, cmd_obj, 0); + + if(res == _SUCCESS) + _rtw_up_sema(&pcmdpriv->cmd_queue_sema); + +exit: + +_func_exit_; + + return res; +} + +struct cmd_obj *rtw_dequeue_cmd(struct cmd_priv *pcmdpriv) +{ + struct cmd_obj *cmd_obj; + +_func_enter_; + + cmd_obj = _rtw_dequeue_cmd(&pcmdpriv->cmd_queue); + +_func_exit_; + return cmd_obj; +} + +void rtw_cmd_clr_isr(struct cmd_priv *pcmdpriv) +{ +_func_enter_; + pcmdpriv->cmd_done_cnt++; + //_rtw_up_sema(&(pcmdpriv->cmd_done_sema)); +_func_exit_; +} + +void rtw_free_cmd_obj(struct cmd_obj *pcmd) +{ + struct drvextra_cmd_parm *extra_parm = NULL; +_func_enter_; + + if (pcmd->parmbuf != NULL) { + /* free parmbuf in cmd_obj */ + rtw_mfree((unsigned char *)pcmd->parmbuf, pcmd->cmdsz); + } + if(pcmd->rsp!=NULL) + { + if(pcmd->rspsz!= 0) + { + //free rsp in cmd_obj + rtw_mfree((unsigned char*)pcmd->rsp, pcmd->rspsz); + } + } + + //free cmd_obj + rtw_mfree((unsigned char*)pcmd, sizeof(struct cmd_obj)); + +_func_exit_; +} + + +void rtw_stop_cmd_thread(_adapter *adapter) +{ + if(adapter->cmdThread && + ATOMIC_READ(&(adapter->cmdpriv.cmdthd_running)) == _TRUE && + adapter->cmdpriv.stop_req == 0) + { + adapter->cmdpriv.stop_req = 1; + _rtw_up_sema(&adapter->cmdpriv.cmd_queue_sema); + _rtw_down_sema(&adapter->cmdpriv.terminate_cmdthread_sema); + } +} + +thread_return rtw_cmd_thread(thread_context context) +{ + u8 ret; + struct cmd_obj *pcmd; + u8 *pcmdbuf, *prspbuf; + u32 cmd_start_time; + u32 cmd_process_time; + u8 (*cmd_hdl)(_adapter *padapter, u8* pbuf); + void (*pcmd_callback)(_adapter *dev, struct cmd_obj *pcmd); + PADAPTER padapter = (PADAPTER)context; + struct cmd_priv *pcmdpriv = &(padapter->cmdpriv); + struct drvextra_cmd_parm *extra_parm = NULL; + _irqL irqL; +_func_enter_; + + thread_enter("RTW_CMD_THREAD"); + + pcmdbuf = pcmdpriv->cmd_buf; + prspbuf = pcmdpriv->rsp_buf; + + pcmdpriv->stop_req = 0; + ATOMIC_SET(&(pcmdpriv->cmdthd_running), _TRUE); + _rtw_up_sema(&pcmdpriv->terminate_cmdthread_sema); + + RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("start r871x rtw_cmd_thread !!!!\n")); + + while (1) { + if (_rtw_down_sema(&pcmdpriv->cmd_queue_sema) == _FAIL) { + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" _rtw_down_sema(&pcmdpriv->cmd_queue_sema) return _FAIL, break\n", FUNC_ADPT_ARG(padapter)); + break; + } + + if (RTW_CANNOT_RUN(padapter)) { + DBG_871X_LEVEL(_drv_always_, "%s: DriverStopped(%s) SurpriseRemoved(%s) break at line %d\n", + __func__ + , rtw_is_drv_stopped(padapter)?"True":"False" + , rtw_is_surprise_removed(padapter)?"True":"False" + , __LINE__); + break; + } + + if (pcmdpriv->stop_req) { + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" stop_req:%u, break\n", FUNC_ADPT_ARG(padapter), pcmdpriv->stop_req); + break; + } + + _enter_critical(&pcmdpriv->cmd_queue.lock, &irqL); + if (rtw_is_list_empty(&(pcmdpriv->cmd_queue.queue))) { + //DBG_871X("%s: cmd queue is empty!\n", __func__); + _exit_critical(&pcmdpriv->cmd_queue.lock, &irqL); + continue; + } + _exit_critical(&pcmdpriv->cmd_queue.lock, &irqL); + +_next: + if (RTW_CANNOT_RUN(padapter)) { + DBG_871X_LEVEL(_drv_always_, "%s: DriverStopped(%s) SurpriseRemoved(%s) break at line %d\n", + __func__ + , rtw_is_drv_stopped(padapter)?"True":"False" + , rtw_is_surprise_removed(padapter)?"True":"False" + , __LINE__); + break; + } + + pcmd = rtw_dequeue_cmd(pcmdpriv); + if (!pcmd) { + #ifdef CONFIG_LPS_LCLK + rtw_unregister_cmd_alive(padapter); + #endif + continue; + } + + cmd_start_time = rtw_get_current_time(); + pcmdpriv->cmd_issued_cnt++; + + if (pcmd->cmdsz > MAX_CMDSZ) { + DBG_871X_LEVEL(_drv_err_, "%s cmdsz:%d > MAX_CMDSZ:%d\n", __func__, pcmd->cmdsz, MAX_CMDSZ); + pcmd->res = H2C_PARAMETERS_ERROR; + goto post_process; + } + + if (pcmd->cmdcode >= (sizeof(wlancmds) / sizeof(struct cmd_hdl))) { + DBG_871X_LEVEL(_drv_err_, "%s undefined cmdcode:%d\n", __func__, pcmd->cmdcode); + pcmd->res = H2C_PARAMETERS_ERROR; + goto post_process; + } + + cmd_hdl = wlancmds[pcmd->cmdcode].h2cfuns; + if (!cmd_hdl) { + DBG_871X_LEVEL(_drv_err_, "%s no cmd_hdl for cmdcode:%d\n", __func__, pcmd->cmdcode); + pcmd->res = H2C_PARAMETERS_ERROR; + goto post_process; + } + + if (_FAIL == rtw_cmd_filter(pcmdpriv, pcmd)) { + pcmd->res = H2C_DROPPED; + if (pcmd->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra)) { + extra_parm = (struct drvextra_cmd_parm *)pcmd->parmbuf; + if (extra_parm && extra_parm->pbuf && extra_parm->size > 0) + rtw_mfree(extra_parm->pbuf, extra_parm->size); + } + goto post_process; + } + + #ifdef CONFIG_LPS_LCLK + if (pcmd->no_io) { + rtw_unregister_cmd_alive(padapter); + } else { + if (rtw_register_cmd_alive(padapter) != _SUCCESS) { + if (DBG_CMD_EXECUTE) + DBG_871X_LEVEL(_drv_always_, "%s: wait to leave LPS_LCLK\n", __func__); + + pcmd->res = H2C_ENQ_HEAD; + ret = _rtw_enqueue_cmd(&pcmdpriv->cmd_queue, pcmd, 1); + if (ret == _SUCCESS) { + if (DBG_CMD_EXECUTE) + DBG_871X(ADPT_FMT" "CMD_FMT" ENQ_HEAD\n", ADPT_ARG(pcmd->padapter), CMD_ARG(pcmd)); + continue; + } + + DBG_871X(ADPT_FMT" "CMD_FMT" ENQ_HEAD_FAIL\n", ADPT_ARG(pcmd->padapter), CMD_ARG(pcmd)); + pcmd->res = H2C_ENQ_HEAD_FAIL; + rtw_warn_on(1); + } + } + #endif /* CONFIG_LPS_LCLK */ + + if (DBG_CMD_EXECUTE) + DBG_871X(ADPT_FMT" "CMD_FMT" %sexecute\n", ADPT_ARG(pcmd->padapter), CMD_ARG(pcmd) + , pcmd->res == H2C_ENQ_HEAD ? "ENQ_HEAD " : (pcmd->res == H2C_ENQ_HEAD_FAIL ? "ENQ_HEAD_FAIL " : "")); + + _rtw_memcpy(pcmdbuf, pcmd->parmbuf, pcmd->cmdsz); + ret = cmd_hdl(pcmd->padapter, pcmdbuf); + pcmd->res = ret; + + pcmdpriv->cmd_seq++; + +post_process: + + _enter_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL); + if (pcmd->sctx) { + if (0) + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" pcmd->sctx\n", + FUNC_ADPT_ARG(pcmd->padapter)); + if (pcmd->res == H2C_SUCCESS) + rtw_sctx_done(&pcmd->sctx); + else + rtw_sctx_done_err(&pcmd->sctx, RTW_SCTX_DONE_CMD_ERROR); + } + _exit_critical_mutex(&(pcmd->padapter->cmdpriv.sctx_mutex), NULL); + + cmd_process_time = rtw_get_passing_time_ms(cmd_start_time); + if (cmd_process_time > 1000) { + DBG_871X(ADPT_FMT" "CMD_FMT" process_time=%d\n", ADPT_ARG(pcmd->padapter), CMD_ARG(pcmd), cmd_process_time); + if (0) + rtw_warn_on(1); + } + + //call callback function for post-processed + if(pcmd->cmdcode < (sizeof(rtw_cmd_callback) /sizeof(struct _cmd_callback))) + { + pcmd_callback = rtw_cmd_callback[pcmd->cmdcode].callback; + if(pcmd_callback == NULL) + { + RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("mlme_cmd_hdl(): pcmd_callback=0x%p, cmdcode=0x%x\n", pcmd_callback, pcmd->cmdcode)); + rtw_free_cmd_obj(pcmd); + } + else + { + //todo: !!! fill rsp_buf to pcmd->rsp if (pcmd->rsp!=NULL) + pcmd_callback(pcmd->padapter, pcmd);//need conider that free cmd_obj in rtw_cmd_callback + } + } + else + { + RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("%s: cmdcode=0x%x callback not defined!\n", __FUNCTION__, pcmd->cmdcode)); + rtw_free_cmd_obj(pcmd); + } + + flush_signals_thread(); + + goto _next; + + } + +#ifdef CONFIG_LPS_LCLK + rtw_unregister_cmd_alive(padapter); +#endif + + /* to avoid enqueue cmd after free all cmd_obj */ + ATOMIC_SET(&(pcmdpriv->cmdthd_running), _FALSE); + + /* free all cmd_obj resources */ + do { + pcmd = rtw_dequeue_cmd(pcmdpriv); + if (pcmd == NULL) + break; + + if (0) + DBG_871X("%s: leaving... drop "CMD_FMT"\n", __func__, CMD_ARG(pcmd)); + + if (pcmd->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra)) { + extra_parm = (struct drvextra_cmd_parm *)pcmd->parmbuf; + if(extra_parm->pbuf && extra_parm->size > 0) { + rtw_mfree(extra_parm->pbuf, extra_parm->size); + } + } + + rtw_free_cmd_obj(pcmd); + } while (1); + + _rtw_up_sema(&pcmdpriv->terminate_cmdthread_sema); + +_func_exit_; + + thread_exit(); + +} + + +#ifdef CONFIG_EVENT_THREAD_MODE +u32 rtw_enqueue_evt(struct evt_priv *pevtpriv, struct evt_obj *obj) +{ + _irqL irqL; + int res; + _queue *queue = &pevtpriv->evt_queue; + +_func_enter_; + + res = _SUCCESS; + + if (obj == NULL) { + res = _FAIL; + goto exit; + } + + _enter_critical_bh(&queue->lock, &irqL); + + rtw_list_insert_tail(&obj->list, &queue->queue); + + _exit_critical_bh(&queue->lock, &irqL); + + //rtw_evt_notify_isr(pevtpriv); + +exit: + +_func_exit_; + + return res; +} + +struct evt_obj *rtw_dequeue_evt(_queue *queue) +{ + _irqL irqL; + struct evt_obj *pevtobj; + +_func_enter_; + + _enter_critical_bh(&queue->lock, &irqL); + + if (rtw_is_list_empty(&(queue->queue))) + pevtobj = NULL; + else + { + pevtobj = LIST_CONTAINOR(get_next(&(queue->queue)), struct evt_obj, list); + rtw_list_delete(&pevtobj->list); + } + + _exit_critical_bh(&queue->lock, &irqL); + +_func_exit_; + + return pevtobj; +} + +void rtw_free_evt_obj(struct evt_obj *pevtobj) +{ +_func_enter_; + + if(pevtobj->parmbuf) + rtw_mfree((unsigned char*)pevtobj->parmbuf, pevtobj->evtsz); + + rtw_mfree((unsigned char*)pevtobj, sizeof(struct evt_obj)); + +_func_exit_; +} + +void rtw_evt_notify_isr(struct evt_priv *pevtpriv) +{ +_func_enter_; + pevtpriv->evt_done_cnt++; + _rtw_up_sema(&(pevtpriv->evt_notify)); +_func_exit_; +} +#endif + + +/* +u8 rtw_setstandby_cmd(unsigned char *adapter) +*/ +u8 rtw_setstandby_cmd(_adapter *padapter, uint action) +{ + struct cmd_obj* ph2c; + struct usb_suspend_parm* psetusbsuspend; + struct cmd_priv *pcmdpriv=&padapter->cmdpriv; + + u8 ret = _SUCCESS; + +_func_enter_; + + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + ret = _FAIL; + goto exit; + } + + psetusbsuspend = (struct usb_suspend_parm*)rtw_zmalloc(sizeof(struct usb_suspend_parm)); + if (psetusbsuspend == NULL) { + rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); + ret = _FAIL; + goto exit; + } + + psetusbsuspend->action = action; + + init_h2fwcmd_w_parm_no_rsp(ph2c, psetusbsuspend, GEN_CMD_CODE(_SetUsbSuspend)); + + ret = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + +_func_exit_; + + return ret; +} + +/* +rtw_sitesurvey_cmd(~) + ### NOTE:#### (!!!!) + MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock +*/ +u8 rtw_sitesurvey_cmd(_adapter *padapter, NDIS_802_11_SSID *ssid, int ssid_num, + struct rtw_ieee80211_channel *ch, int ch_num) +{ + u8 res = _FAIL; + struct cmd_obj *ph2c; + struct sitesurvey_parm *psurveyPara; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); +#endif //CONFIG_P2P + +_func_enter_; + +#ifdef CONFIG_LPS + if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE){ + rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_SCAN, 1); + } +#endif + +#ifdef CONFIG_P2P_PS + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { + p2p_ps_wk_cmd(padapter, P2P_PS_SCAN, 1); + } +#endif //CONFIG_P2P_PS + + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) + return _FAIL; + + psurveyPara = (struct sitesurvey_parm*)rtw_zmalloc(sizeof(struct sitesurvey_parm)); + if (psurveyPara == NULL) { + rtw_mfree((unsigned char*) ph2c, sizeof(struct cmd_obj)); + return _FAIL; + } + + rtw_free_network_queue(padapter, _FALSE); + + RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("%s: flush network queue\n", __FUNCTION__)); + + init_h2fwcmd_w_parm_no_rsp(ph2c, psurveyPara, GEN_CMD_CODE(_SiteSurvey)); + + /* psurveyPara->bsslimit = 48; */ + psurveyPara->scan_mode = pmlmepriv->scan_mode; + + /* prepare ssid list */ + if (ssid) { + int i; + for (i=0; issid[i], &ssid[i], sizeof(NDIS_802_11_SSID)); + psurveyPara->ssid_num++; + if (0) + DBG_871X(FUNC_ADPT_FMT" ssid:(%s, %d)\n", FUNC_ADPT_ARG(padapter), + psurveyPara->ssid[i].Ssid, psurveyPara->ssid[i].SsidLength); + } + } + } + + /* prepare channel list */ + if (ch) { + int i; + for (i=0; ich[i], &ch[i], sizeof(struct rtw_ieee80211_channel)); + psurveyPara->ch_num++; + if (0) + DBG_871X(FUNC_ADPT_FMT" ch:%u\n", FUNC_ADPT_ARG(padapter), + psurveyPara->ch[i].hw_value); + } + } + } + + set_fwstate(pmlmepriv, _FW_UNDER_SURVEY); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + + if(res == _SUCCESS) { + + pmlmepriv->scan_start_time = rtw_get_current_time(); + +#ifdef CONFIG_SCAN_BACKOP + if((padapter->pbuddy_adapter->mlmeextpriv.mlmext_info.state&0x03) == WIFI_FW_AP_STATE) + { + if(IsSupported5G(padapter->registrypriv.wireless_mode) + && IsSupported24G(padapter->registrypriv.wireless_mode)) //dual band + mlme_set_scan_to_timer(pmlmepriv, CONC_SCANNING_TIMEOUT_DUAL_BAND); + else //single band + mlme_set_scan_to_timer(pmlmepriv, CONC_SCANNING_TIMEOUT_SINGLE_BAND); + } + else +#endif /* CONFIG_SCAN_BACKOP */ + mlme_set_scan_to_timer(pmlmepriv, SCANNING_TIMEOUT); + + rtw_led_control(padapter, LED_CTL_SITE_SURVEY); + } else { + _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY); + } + +_func_exit_; + + return res; +} + +u8 rtw_setdatarate_cmd(_adapter *padapter, u8 *rateset) +{ + struct cmd_obj* ph2c; + struct setdatarate_parm* pbsetdataratepara; + struct cmd_priv* pcmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; + +_func_enter_; + + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + pbsetdataratepara = (struct setdatarate_parm*)rtw_zmalloc(sizeof(struct setdatarate_parm)); + if (pbsetdataratepara == NULL) { + rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(ph2c, pbsetdataratepara, GEN_CMD_CODE(_SetDataRate)); +#ifdef MP_FIRMWARE_OFFLOAD + pbsetdataratepara->curr_rateidx = *(u32*)rateset; +// _rtw_memcpy(pbsetdataratepara, rateset, sizeof(u32)); +#else + pbsetdataratepara->mac_id = 5; + _rtw_memcpy(pbsetdataratepara->datarates, rateset, NumRates); +#endif + res = rtw_enqueue_cmd(pcmdpriv, ph2c); +exit: + +_func_exit_; + + return res; +} + +u8 rtw_setbasicrate_cmd(_adapter *padapter, u8 *rateset) +{ + struct cmd_obj* ph2c; + struct setbasicrate_parm* pssetbasicratepara; + struct cmd_priv* pcmdpriv=&padapter->cmdpriv; + u8 res = _SUCCESS; + +_func_enter_; + + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res= _FAIL; + goto exit; + } + pssetbasicratepara = (struct setbasicrate_parm*)rtw_zmalloc(sizeof(struct setbasicrate_parm)); + + if (pssetbasicratepara == NULL) { + rtw_mfree((u8*) ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(ph2c, pssetbasicratepara, _SetBasicRate_CMD_); + + _rtw_memcpy(pssetbasicratepara->basicrates, rateset, NumRates); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); +exit: + +_func_exit_; + + return res; +} + + +/* +unsigned char rtw_setphy_cmd(unsigned char *adapter) + +1. be called only after rtw_update_registrypriv_dev_network( ~) or mp testing program +2. for AdHoc/Ap mode or mp mode? + +*/ +u8 rtw_setphy_cmd(_adapter *padapter, u8 modem, u8 ch) +{ + struct cmd_obj* ph2c; + struct setphy_parm* psetphypara; + struct cmd_priv *pcmdpriv=&padapter->cmdpriv; +// struct mlme_priv *pmlmepriv = &padapter->mlmepriv; +// struct registry_priv* pregistry_priv = &padapter->registrypriv; + u8 res=_SUCCESS; + +_func_enter_; + + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(ph2c==NULL){ + res= _FAIL; + goto exit; + } + psetphypara = (struct setphy_parm*)rtw_zmalloc(sizeof(struct setphy_parm)); + + if(psetphypara==NULL){ + rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); + res= _FAIL; + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(ph2c, psetphypara, _SetPhy_CMD_); + + RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("CH=%d, modem=%d", ch, modem)); + + psetphypara->modem = modem; + psetphypara->rfchannel = ch; + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); +exit: +_func_exit_; + return res; +} + +u8 rtw_getmacreg_cmd(_adapter *padapter, u8 len, u32 addr) +{ + struct cmd_obj *ph2c; + struct readMAC_parm *preadmacparm; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; + +_func_enter_; + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + preadmacparm = (struct readMAC_parm *)rtw_zmalloc(sizeof(struct readMAC_parm)); + + if (preadmacparm == NULL) { + rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(ph2c, preadmacparm, GEN_CMD_CODE(_GetMACReg)); + + preadmacparm->len = len; + preadmacparm->addr = addr; + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: +_func_exit_; + return res; +} + +void rtw_usb_catc_trigger_cmd(_adapter *padapter, const char *caller) +{ + DBG_871X("%s caller:%s\n", __func__, caller); + rtw_getmacreg_cmd(padapter, 1, 0x1c4); +} + +u8 rtw_setbbreg_cmd(_adapter*padapter, u8 offset, u8 val) +{ + struct cmd_obj* ph2c; + struct writeBB_parm* pwritebbparm; + struct cmd_priv *pcmdpriv=&padapter->cmdpriv; + u8 res=_SUCCESS; +_func_enter_; + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(ph2c==NULL){ + res= _FAIL; + goto exit; + } + pwritebbparm = (struct writeBB_parm*)rtw_zmalloc(sizeof(struct writeBB_parm)); + + if(pwritebbparm==NULL){ + rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); + res= _FAIL; + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(ph2c, pwritebbparm, GEN_CMD_CODE(_SetBBReg)); + + pwritebbparm->offset = offset; + pwritebbparm->value = val; + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); +exit: +_func_exit_; + return res; +} + +u8 rtw_getbbreg_cmd(_adapter *padapter, u8 offset, u8 *pval) +{ + struct cmd_obj* ph2c; + struct readBB_parm* prdbbparm; + struct cmd_priv *pcmdpriv=&padapter->cmdpriv; + u8 res=_SUCCESS; + +_func_enter_; + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(ph2c==NULL){ + res=_FAIL; + goto exit; + } + prdbbparm = (struct readBB_parm*)rtw_zmalloc(sizeof(struct readBB_parm)); + + if(prdbbparm ==NULL){ + rtw_mfree((unsigned char *) ph2c, sizeof(struct cmd_obj)); + return _FAIL; + } + + _rtw_init_listhead(&ph2c->list); + ph2c->cmdcode =GEN_CMD_CODE(_GetBBReg); + ph2c->parmbuf = (unsigned char *)prdbbparm; + ph2c->cmdsz = sizeof(struct readBB_parm); + ph2c->rsp = pval; + ph2c->rspsz = sizeof(struct readBB_rsp); + + prdbbparm ->offset = offset; + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); +exit: +_func_exit_; + return res; +} + +u8 rtw_setrfreg_cmd(_adapter *padapter, u8 offset, u32 val) +{ + struct cmd_obj* ph2c; + struct writeRF_parm* pwriterfparm; + struct cmd_priv *pcmdpriv=&padapter->cmdpriv; + u8 res=_SUCCESS; +_func_enter_; + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(ph2c==NULL){ + res= _FAIL; + goto exit; + } + pwriterfparm = (struct writeRF_parm*)rtw_zmalloc(sizeof(struct writeRF_parm)); + + if(pwriterfparm==NULL){ + rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); + res= _FAIL; + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(ph2c, pwriterfparm, GEN_CMD_CODE(_SetRFReg)); + + pwriterfparm->offset = offset; + pwriterfparm->value = val; + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); +exit: +_func_exit_; + return res; +} + +u8 rtw_getrfreg_cmd(_adapter *padapter, u8 offset, u8 *pval) +{ + struct cmd_obj* ph2c; + struct readRF_parm* prdrfparm; + struct cmd_priv *pcmdpriv=&padapter->cmdpriv; + u8 res=_SUCCESS; + +_func_enter_; + + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(ph2c==NULL){ + res= _FAIL; + goto exit; + } + + prdrfparm = (struct readRF_parm*)rtw_zmalloc(sizeof(struct readRF_parm)); + if(prdrfparm ==NULL){ + rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); + res= _FAIL; + goto exit; + } + + _rtw_init_listhead(&ph2c->list); + ph2c->cmdcode =GEN_CMD_CODE(_GetRFReg); + ph2c->parmbuf = (unsigned char *)prdrfparm; + ph2c->cmdsz = sizeof(struct readRF_parm); + ph2c->rsp = pval; + ph2c->rspsz = sizeof(struct readRF_rsp); + + prdrfparm ->offset = offset; + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + +_func_exit_; + + return res; +} + +void rtw_getbbrfreg_cmdrsp_callback(_adapter* padapter, struct cmd_obj *pcmd) +{ + _func_enter_; + + //rtw_free_cmd_obj(pcmd); + rtw_mfree((unsigned char*) pcmd->parmbuf, pcmd->cmdsz); + rtw_mfree((unsigned char*) pcmd, sizeof(struct cmd_obj)); + +#ifdef CONFIG_MP_INCLUDED + if (padapter->registrypriv.mp_mode == 1) + padapter->mppriv.workparam.bcompleted= _TRUE; +#endif +_func_exit_; +} + +void rtw_readtssi_cmdrsp_callback(_adapter* padapter, struct cmd_obj *pcmd) +{ + _func_enter_; + + rtw_mfree((unsigned char*) pcmd->parmbuf, pcmd->cmdsz); + rtw_mfree((unsigned char*) pcmd, sizeof(struct cmd_obj)); + +#ifdef CONFIG_MP_INCLUDED + if (padapter->registrypriv.mp_mode == 1) + padapter->mppriv.workparam.bcompleted= _TRUE; +#endif + +_func_exit_; +} + +static u8 rtw_createbss_cmd(_adapter *adapter, int flags, bool adhoc + , s16 req_ch, u8 req_bw, u8 req_offset) +{ + struct cmd_obj *cmdobj; + struct createbss_parm *parm; + struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct submit_ctx sctx; + u8 res = _SUCCESS; + + /* prepare cmd parameter */ + parm = (struct createbss_parm *)rtw_zmalloc(sizeof(*parm)); + if (parm == NULL) { + res = _FAIL; + goto exit; + } + + if (adhoc) { + /* for now, adhoc doesn't support ch,bw,offset request */ + parm->adhoc = 1; + } else { + parm->adhoc = 0; + parm->req_ch = req_ch; + parm->req_bw = req_bw; + parm->req_offset = req_offset; + } + + if (flags & RTW_CMDF_DIRECTLY) { + /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ + if (H2C_SUCCESS != createbss_hdl(adapter, (u8 *)parm)) + res = _FAIL; + rtw_mfree((u8 *)parm, sizeof(*parm)); + } else { + /* need enqueue, prepare cmd_obj and enqueue */ + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj)); + if (cmdobj == NULL) { + res = _FAIL; + rtw_mfree((u8 *)parm, sizeof(*parm)); + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_CreateBss)); + + if (flags & RTW_CMDF_WAIT_ACK) { + cmdobj->sctx = &sctx; + rtw_sctx_init(&sctx, 2000); + } + + res = rtw_enqueue_cmd(pcmdpriv, cmdobj); + + if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { + rtw_sctx_wait(&sctx, __func__); + _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status == RTW_SCTX_SUBMITTED) + cmdobj->sctx = NULL; + _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + } + } + +exit: + return res; +} + +inline u8 rtw_create_ibss_cmd(_adapter *adapter, int flags) +{ + return rtw_createbss_cmd(adapter, flags + , 1 + , -1, 0, 0 /* for now, adhoc doesn't support ch,bw,offset request */ + ); +} + +inline u8 rtw_startbss_cmd(_adapter *adapter, int flags) +{ + return rtw_createbss_cmd(adapter, flags + , 0 + , -1, 0, 0 /* doesn't request ch, bw, offset */ + ); +} + +inline u8 rtw_change_bss_chbw_cmd(_adapter *adapter, int flags, u8 req_ch, u8 req_bw, u8 req_offset) +{ + return rtw_createbss_cmd(adapter, flags + , 0 + , req_ch, req_bw, req_offset + ); +} + +u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network* pnetwork) +{ + u8 *auth, res = _SUCCESS; + uint t_len = 0; + WLAN_BSSID_EX *psecnetwork; + struct cmd_obj *pcmd; + struct cmd_priv *pcmdpriv=&padapter->cmdpriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct qos_priv *pqospriv= &pmlmepriv->qospriv; + struct security_priv *psecuritypriv=&padapter->securitypriv; + struct registry_priv *pregistrypriv = &padapter->registrypriv; +#ifdef CONFIG_80211N_HT + struct ht_priv *phtpriv = &pmlmepriv->htpriv; +#endif //CONFIG_80211N_HT +#ifdef CONFIG_80211AC_VHT + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; +#endif //CONFIG_80211AC_VHT + NDIS_802_11_NETWORK_INFRASTRUCTURE ndis_network_mode = pnetwork->network.InfrastructureMode; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u32 tmp_len; + u8 *ptmp=NULL; +_func_enter_; + + rtw_led_control(padapter, LED_CTL_START_TO_LINK); + + if (pmlmepriv->assoc_ssid.SsidLength == 0){ + RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("+Join cmd: Any SSid\n")); + } else { + RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+Join cmd: SSid=[%s]\n", pmlmepriv->assoc_ssid.Ssid)); + } + + pcmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(pcmd==NULL){ + res=_FAIL; + RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("rtw_joinbss_cmd: memory allocate for cmd_obj fail!!!\n")); + goto exit; + } + /* // for IEs is pointer + t_len = sizeof (ULONG) + sizeof (NDIS_802_11_MAC_ADDRESS) + 2 + + sizeof (NDIS_802_11_SSID) + sizeof (ULONG) + + sizeof (NDIS_802_11_RSSI) + sizeof (NDIS_802_11_NETWORK_TYPE) + + sizeof (NDIS_802_11_CONFIGURATION) + + sizeof (NDIS_802_11_NETWORK_INFRASTRUCTURE) + + sizeof (NDIS_802_11_RATES_EX)+ sizeof(WLAN_PHY_INFO)+ sizeof (ULONG) + MAX_IE_SZ; + */ + //for IEs is fix buf size + t_len = sizeof(WLAN_BSSID_EX); + + + //for hidden ap to set fw_state here + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) != _TRUE) + { + switch(ndis_network_mode) + { + case Ndis802_11IBSS: + set_fwstate(pmlmepriv, WIFI_ADHOC_STATE); + break; + + case Ndis802_11Infrastructure: + set_fwstate(pmlmepriv, WIFI_STATION_STATE); + break; + + case Ndis802_11APMode: + case Ndis802_11AutoUnknown: + case Ndis802_11InfrastructureMax: + case Ndis802_11Monitor: + break; + + } + } + + pmlmeinfo->assoc_AP_vendor = check_assoc_AP(pnetwork->network.IEs, pnetwork->network.IELength); + + /* + Modified by Arvin 2015/05/13 + Solution for allocating a new WLAN_BSSID_EX to avoid race condition issue between disconnect and joinbss + */ + psecnetwork = (WLAN_BSSID_EX *)rtw_zmalloc(sizeof(WLAN_BSSID_EX)); + if(psecnetwork==NULL) + { + if(pcmd !=NULL) + rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj)); + + res=_FAIL; + + RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("rtw_joinbss_cmd :psecnetwork==NULL!!!\n")); + + goto exit; + } + + _rtw_memset(psecnetwork, 0, t_len); + + _rtw_memcpy(psecnetwork, &pnetwork->network, get_WLAN_BSSID_EX_sz(&pnetwork->network)); + + auth=&psecuritypriv->authenticator_ie[0]; + psecuritypriv->authenticator_ie[0]=(unsigned char)psecnetwork->IELength; + + if((psecnetwork->IELength-12) < (256-1)) { + _rtw_memcpy(&psecuritypriv->authenticator_ie[1], &psecnetwork->IEs[12], psecnetwork->IELength-12); + } else { + _rtw_memcpy(&psecuritypriv->authenticator_ie[1], &psecnetwork->IEs[12], (256-1)); + } + + psecnetwork->IELength = 0; + // Added by Albert 2009/02/18 + // If the the driver wants to use the bssid to create the connection. + // If not, we have to copy the connecting AP's MAC address to it so that + // the driver just has the bssid information for PMKIDList searching. + + if ( pmlmepriv->assoc_by_bssid == _FALSE ) + { + _rtw_memcpy( &pmlmepriv->assoc_bssid[ 0 ], &pnetwork->network.MacAddress[ 0 ], ETH_ALEN ); + } + + psecnetwork->IELength = rtw_restruct_sec_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], pnetwork->network.IELength); + + + pqospriv->qos_option = 0; + + if(pregistrypriv->wmm_enable) + { + tmp_len = rtw_restruct_wmm_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], pnetwork->network.IELength, psecnetwork->IELength); + + if (psecnetwork->IELength != tmp_len) + { + psecnetwork->IELength = tmp_len; + pqospriv->qos_option = 1; //There is WMM IE in this corresp. beacon + } + else + { + pqospriv->qos_option = 0;//There is no WMM IE in this corresp. beacon + } + } + +#ifdef CONFIG_80211N_HT + phtpriv->ht_option = _FALSE; + ptmp = rtw_get_ie(&pnetwork->network.IEs[12], _HT_CAPABILITY_IE_, &tmp_len, pnetwork->network.IELength-12); + if(pregistrypriv->ht_enable && ptmp && tmp_len>0) + { + // Added by Albert 2010/06/23 + // For the WEP mode, we will use the bg mode to do the connection to avoid some IOT issue. + // Especially for Realtek 8192u SoftAP. + if ( ( padapter->securitypriv.dot11PrivacyAlgrthm != _WEP40_ ) && + ( padapter->securitypriv.dot11PrivacyAlgrthm != _WEP104_ ) && + ( padapter->securitypriv.dot11PrivacyAlgrthm != _TKIP_ )) + { + rtw_ht_use_default_setting(padapter); + + rtw_build_wmm_ie_ht(padapter, &psecnetwork->IEs[0], &psecnetwork->IELength); + + //rtw_restructure_ht_ie + rtw_restructure_ht_ie(padapter, &pnetwork->network.IEs[12], &psecnetwork->IEs[0], + pnetwork->network.IELength-12, &psecnetwork->IELength, + pnetwork->network.Configuration.DSConfig); + } + } + +#ifdef CONFIG_80211AC_VHT + pvhtpriv->vht_option = _FALSE; + if (phtpriv->ht_option + && REGSTY_IS_11AC_ENABLE(pregistrypriv) + && hal_chk_proto_cap(padapter, PROTO_CAP_11AC) + && (!pmlmepriv->country_ent || COUNTRY_CHPLAN_EN_11AC(pmlmepriv->country_ent)) + ) { + rtw_restructure_vht_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], + pnetwork->network.IELength, &psecnetwork->IELength); + } +#endif + + rtw_append_exented_cap(padapter, &psecnetwork->IEs[0], &psecnetwork->IELength); + +#endif //CONFIG_80211N_HT + + #if 0 + psecuritypriv->supplicant_ie[0]=(u8)psecnetwork->IELength; + + if(psecnetwork->IELength < (256-1)) + { + _rtw_memcpy(&psecuritypriv->supplicant_ie[1], &psecnetwork->IEs[0], psecnetwork->IELength); + } + else + { + _rtw_memcpy(&psecuritypriv->supplicant_ie[1], &psecnetwork->IEs[0], (256-1)); + } + #endif + + pcmd->cmdsz = sizeof(WLAN_BSSID_EX); + +#ifdef CONFIG_RTL8712 + //wlan_network endian conversion + psecnetwork->Length = cpu_to_le32(psecnetwork->Length); + psecnetwork->Ssid.SsidLength= cpu_to_le32(psecnetwork->Ssid.SsidLength); + psecnetwork->Privacy = cpu_to_le32(psecnetwork->Privacy); + psecnetwork->Rssi = cpu_to_le32(psecnetwork->Rssi); + psecnetwork->NetworkTypeInUse = cpu_to_le32(psecnetwork->NetworkTypeInUse); + psecnetwork->Configuration.ATIMWindow = cpu_to_le32(psecnetwork->Configuration.ATIMWindow); + psecnetwork->Configuration.BeaconPeriod = cpu_to_le32(psecnetwork->Configuration.BeaconPeriod); + psecnetwork->Configuration.DSConfig = cpu_to_le32(psecnetwork->Configuration.DSConfig); + psecnetwork->Configuration.FHConfig.DwellTime=cpu_to_le32(psecnetwork->Configuration.FHConfig.DwellTime); + psecnetwork->Configuration.FHConfig.HopPattern=cpu_to_le32(psecnetwork->Configuration.FHConfig.HopPattern); + psecnetwork->Configuration.FHConfig.HopSet=cpu_to_le32(psecnetwork->Configuration.FHConfig.HopSet); + psecnetwork->Configuration.FHConfig.Length=cpu_to_le32(psecnetwork->Configuration.FHConfig.Length); + psecnetwork->Configuration.Length = cpu_to_le32(psecnetwork->Configuration.Length); + psecnetwork->InfrastructureMode = cpu_to_le32(psecnetwork->InfrastructureMode); + psecnetwork->IELength = cpu_to_le32(psecnetwork->IELength); +#endif + + _rtw_init_listhead(&pcmd->list); + pcmd->cmdcode = _JoinBss_CMD_;//GEN_CMD_CODE(_JoinBss) + pcmd->parmbuf = (unsigned char *)psecnetwork; + pcmd->rsp = NULL; + pcmd->rspsz = 0; + + res = rtw_enqueue_cmd(pcmdpriv, pcmd); + +exit: + +_func_exit_; + + return res; +} + +u8 rtw_disassoc_cmd(_adapter*padapter, u32 deauth_timeout_ms, bool enqueue) /* for sta_mode */ +{ + struct cmd_obj *cmdobj = NULL; + struct disconnect_parm *param = NULL; + struct cmd_priv *cmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; + +_func_enter_; + + RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_disassoc_cmd\n")); + + /* prepare cmd parameter */ + param = (struct disconnect_parm *)rtw_zmalloc(sizeof(*param)); + if (param == NULL) { + res = _FAIL; + goto exit; + } + param->deauth_timeout_ms = deauth_timeout_ms; + + if (enqueue) { + /* need enqueue, prepare cmd_obj and enqueue */ + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj)); + if (cmdobj == NULL) { + res = _FAIL; + rtw_mfree((u8 *)param, sizeof(*param)); + goto exit; + } + init_h2fwcmd_w_parm_no_rsp(cmdobj, param, _DisConnect_CMD_); + res = rtw_enqueue_cmd(cmdpriv, cmdobj); + } else { + /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ + if (H2C_SUCCESS != disconnect_hdl(padapter, (u8 *)param)) + res = _FAIL; + rtw_mfree((u8 *)param, sizeof(*param)); + } + +exit: + +_func_exit_; + + return res; +} + +u8 rtw_setopmode_cmd(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, bool enqueue) +{ + struct cmd_obj* ph2c; + struct setopmode_parm* psetop; + + struct cmd_priv *pcmdpriv= &padapter->cmdpriv; + u8 res=_SUCCESS; + +_func_enter_; + psetop = (struct setopmode_parm*)rtw_zmalloc(sizeof(struct setopmode_parm)); + + if(psetop==NULL){ + res=_FAIL; + goto exit; + } + psetop->mode = (u8)networktype; + + if(enqueue){ + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(ph2c==NULL){ + rtw_mfree((u8 *)psetop, sizeof(*psetop)); + res= _FAIL; + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(ph2c, psetop, _SetOpMode_CMD_); + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + } + else{ + setopmode_hdl(padapter, (u8 *)psetop); + rtw_mfree((u8 *)psetop, sizeof(*psetop)); + } +exit: + +_func_exit_; + + return res; +} + +u8 rtw_setstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 key_type, bool enqueue) +{ + struct cmd_obj* ph2c; + struct set_stakey_parm *psetstakey_para; + struct cmd_priv *pcmdpriv=&padapter->cmdpriv; + struct set_stakey_rsp *psetstakey_rsp = NULL; + + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + u8 res=_SUCCESS; + +_func_enter_; + + psetstakey_para = (struct set_stakey_parm*)rtw_zmalloc(sizeof(struct set_stakey_parm)); + if(psetstakey_para==NULL){ + res=_FAIL; + goto exit; + } + + _rtw_memcpy(psetstakey_para->addr, sta->hwaddr,ETH_ALEN); + + if(check_fwstate(pmlmepriv, WIFI_STATION_STATE)){ + psetstakey_para->algorithm =(unsigned char) psecuritypriv->dot11PrivacyAlgrthm; + }else{ + GET_ENCRY_ALGO(psecuritypriv, sta, psetstakey_para->algorithm, _FALSE); + } + + if (key_type == GROUP_KEY) { + _rtw_memcpy(&psetstakey_para->key, &psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey, 16); + } + else if (key_type == UNICAST_KEY) { + _rtw_memcpy(&psetstakey_para->key, &sta->dot118021x_UncstKey, 16); + } +#ifdef CONFIG_TDLS + else if(key_type == TDLS_KEY){ + _rtw_memcpy(&psetstakey_para->key, sta->tpk.tk, 16); + psetstakey_para->algorithm=(u8)sta->dot118021XPrivacy; + } +#endif /* CONFIG_TDLS */ + + //jeff: set this becasue at least sw key is ready + padapter->securitypriv.busetkipkey=_TRUE; + + if(enqueue) + { + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if ( ph2c == NULL){ + rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm)); + res= _FAIL; + goto exit; + } + + psetstakey_rsp = (struct set_stakey_rsp*)rtw_zmalloc(sizeof(struct set_stakey_rsp)); + if(psetstakey_rsp == NULL){ + rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); + rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm)); + res=_FAIL; + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, _SetStaKey_CMD_); + ph2c->rsp = (u8 *) psetstakey_rsp; + ph2c->rspsz = sizeof(struct set_stakey_rsp); + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + } + else{ + set_stakey_hdl(padapter, (u8 *)psetstakey_para); + rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm)); + } +exit: + +_func_exit_; + + return res; +} + +u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue) +{ + struct cmd_obj* ph2c; + struct set_stakey_parm *psetstakey_para; + struct cmd_priv *pcmdpriv=&padapter->cmdpriv; + struct set_stakey_rsp *psetstakey_rsp = NULL; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + s16 cam_id = 0; + u8 res=_SUCCESS; + +_func_enter_; + + if(!enqueue) + { + while ((cam_id = rtw_camid_search(padapter, sta->hwaddr, -1, -1)) >= 0) { + DBG_871X_LEVEL(_drv_always_, "clear key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(sta->hwaddr), cam_id); + clear_cam_entry(padapter, cam_id); + rtw_camid_free(padapter, cam_id); + } + } + else + { + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if ( ph2c == NULL){ + res= _FAIL; + goto exit; + } + + psetstakey_para = (struct set_stakey_parm*)rtw_zmalloc(sizeof(struct set_stakey_parm)); + if(psetstakey_para==NULL){ + rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); + res=_FAIL; + goto exit; + } + + psetstakey_rsp = (struct set_stakey_rsp*)rtw_zmalloc(sizeof(struct set_stakey_rsp)); + if(psetstakey_rsp == NULL){ + rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); + rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm)); + res=_FAIL; + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, _SetStaKey_CMD_); + ph2c->rsp = (u8 *) psetstakey_rsp; + ph2c->rspsz = sizeof(struct set_stakey_rsp); + + _rtw_memcpy(psetstakey_para->addr, sta->hwaddr, ETH_ALEN); + + psetstakey_para->algorithm = _NO_PRIVACY_; + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + + } + +exit: + +_func_exit_; + + return res; +} + +u8 rtw_setrttbl_cmd(_adapter *padapter, struct setratable_parm *prate_table) +{ + struct cmd_obj* ph2c; + struct setratable_parm * psetrttblparm; + struct cmd_priv *pcmdpriv=&padapter->cmdpriv; + u8 res=_SUCCESS; +_func_enter_; + + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(ph2c==NULL){ + res= _FAIL; + goto exit; + } + psetrttblparm = (struct setratable_parm*)rtw_zmalloc(sizeof(struct setratable_parm)); + + if(psetrttblparm==NULL){ + rtw_mfree((unsigned char *) ph2c, sizeof(struct cmd_obj)); + res= _FAIL; + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(ph2c, psetrttblparm, GEN_CMD_CODE(_SetRaTable)); + + _rtw_memcpy(psetrttblparm,prate_table,sizeof(struct setratable_parm)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); +exit: +_func_exit_; + return res; + +} + +u8 rtw_getrttbl_cmd(_adapter *padapter, struct getratable_rsp *pval) +{ + struct cmd_obj* ph2c; + struct getratable_parm * pgetrttblparm; + struct cmd_priv *pcmdpriv=&padapter->cmdpriv; + u8 res=_SUCCESS; +_func_enter_; + + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(ph2c==NULL){ + res= _FAIL; + goto exit; + } + pgetrttblparm = (struct getratable_parm*)rtw_zmalloc(sizeof(struct getratable_parm)); + + if(pgetrttblparm==NULL){ + rtw_mfree((unsigned char *) ph2c, sizeof(struct cmd_obj)); + res= _FAIL; + goto exit; + } + +// init_h2fwcmd_w_parm_no_rsp(ph2c, psetrttblparm, GEN_CMD_CODE(_SetRaTable)); + + _rtw_init_listhead(&ph2c->list); + ph2c->cmdcode =GEN_CMD_CODE(_GetRaTable); + ph2c->parmbuf = (unsigned char *)pgetrttblparm; + ph2c->cmdsz = sizeof(struct getratable_parm); + ph2c->rsp = (u8*)pval; + ph2c->rspsz = sizeof(struct getratable_rsp); + + pgetrttblparm ->rsvd = 0x0; + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); +exit: +_func_exit_; + return res; + +} + +u8 rtw_setassocsta_cmd(_adapter *padapter, u8 *mac_addr) +{ + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct cmd_obj* ph2c; + struct set_assocsta_parm *psetassocsta_para; + struct set_stakey_rsp *psetassocsta_rsp = NULL; + + u8 res=_SUCCESS; + +_func_enter_; + + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(ph2c==NULL){ + res= _FAIL; + goto exit; + } + + psetassocsta_para = (struct set_assocsta_parm*)rtw_zmalloc(sizeof(struct set_assocsta_parm)); + if(psetassocsta_para==NULL){ + rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); + res=_FAIL; + goto exit; + } + + psetassocsta_rsp = (struct set_stakey_rsp*)rtw_zmalloc(sizeof(struct set_assocsta_rsp)); + if(psetassocsta_rsp==NULL){ + rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); + rtw_mfree((u8 *) psetassocsta_para, sizeof(struct set_assocsta_parm)); + return _FAIL; + } + + init_h2fwcmd_w_parm_no_rsp(ph2c, psetassocsta_para, _SetAssocSta_CMD_); + ph2c->rsp = (u8 *) psetassocsta_rsp; + ph2c->rspsz = sizeof(struct set_assocsta_rsp); + + _rtw_memcpy(psetassocsta_para->addr, mac_addr,ETH_ALEN); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + +_func_exit_; + + return res; + } + +u8 rtw_addbareq_cmd(_adapter*padapter, u8 tid, u8 *addr) +{ + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct cmd_obj* ph2c; + struct addBaReq_parm *paddbareq_parm; + + u8 res=_SUCCESS; + +_func_enter_; + + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(ph2c==NULL){ + res= _FAIL; + goto exit; + } + + paddbareq_parm = (struct addBaReq_parm*)rtw_zmalloc(sizeof(struct addBaReq_parm)); + if(paddbareq_parm==NULL){ + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res= _FAIL; + goto exit; + } + + paddbareq_parm->tid = tid; + _rtw_memcpy(paddbareq_parm->addr, addr, ETH_ALEN); + + init_h2fwcmd_w_parm_no_rsp(ph2c, paddbareq_parm, GEN_CMD_CODE(_AddBAReq)); + + //DBG_871X("rtw_addbareq_cmd, tid=%d\n", tid); + + //rtw_enqueue_cmd(pcmdpriv, ph2c); + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + +_func_exit_; + + return res; +} + +u8 rtw_addbarsp_cmd(_adapter *padapter, u8 *addr, u16 tid, u8 status, u8 size, u16 start_seq) +{ + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct cmd_obj *ph2c; + struct addBaRsp_parm *paddBaRsp_parm; + u8 res = _SUCCESS; + +_func_enter_; + + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + paddBaRsp_parm = (struct addBaRsp_parm *)rtw_zmalloc(sizeof(struct addBaRsp_parm)); + + if (paddBaRsp_parm == NULL) { + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + _rtw_memcpy(paddBaRsp_parm->addr, addr, ETH_ALEN); + paddBaRsp_parm->tid = tid; + paddBaRsp_parm->status = status; + paddBaRsp_parm->size = size; + paddBaRsp_parm->start_seq = start_seq; + + init_h2fwcmd_w_parm_no_rsp(ph2c, paddBaRsp_parm, GEN_CMD_CODE(_AddBARsp)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + +_func_exit_; + + return res; +} +//add for CONFIG_IEEE80211W, none 11w can use it +u8 rtw_reset_securitypriv_cmd(_adapter*padapter) +{ + struct cmd_obj* ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv=&padapter->cmdpriv; + u8 res=_SUCCESS; + +_func_enter_; + + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(ph2c==NULL){ + res= _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if(pdrvextra_cmd_parm==NULL){ + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res= _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = RESET_SECURITYPRIV; + pdrvextra_cmd_parm->type = 0; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + + //rtw_enqueue_cmd(pcmdpriv, ph2c); + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + +_func_exit_; + + return res; + +} + +u8 rtw_free_assoc_resources_cmd(_adapter*padapter) +{ + struct cmd_obj* ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv=&padapter->cmdpriv; + u8 res=_SUCCESS; + +_func_enter_; + + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(ph2c==NULL){ + res= _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if(pdrvextra_cmd_parm==NULL){ + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res= _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = FREE_ASSOC_RESOURCES; + pdrvextra_cmd_parm->type = 0; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + + //rtw_enqueue_cmd(pcmdpriv, ph2c); + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + +_func_exit_; + + return res; + +} + +u8 rtw_dynamic_chk_wk_cmd(_adapter*padapter) +{ + struct cmd_obj* ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv=&padapter->cmdpriv; + u8 res=_SUCCESS; + +_func_enter_; + + //only primary padapter does this cmd +/* +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->adapter_type != PRIMARY_ADAPTER && padapter->pbuddy_adapter) + pcmdpriv = &(padapter->pbuddy_adapter->cmdpriv); +#endif +*/ + + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(ph2c==NULL){ + res= _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if(pdrvextra_cmd_parm==NULL){ + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res= _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = DYNAMIC_CHK_WK_CID; + pdrvextra_cmd_parm->type = 0; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + + //rtw_enqueue_cmd(pcmdpriv, ph2c); + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + +_func_exit_; + + return res; + +} + +u8 rtw_set_ch_cmd(_adapter*padapter, u8 ch, u8 bw, u8 ch_offset, u8 enqueue) +{ + struct cmd_obj *pcmdobj; + struct set_ch_parm *set_ch_parm; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + + u8 res=_SUCCESS; + +_func_enter_; + + DBG_871X(FUNC_NDEV_FMT" ch:%u, bw:%u, ch_offset:%u\n", + FUNC_NDEV_ARG(padapter->pnetdev), ch, bw, ch_offset); + + /* check input parameter */ + + /* prepare cmd parameter */ + set_ch_parm = (struct set_ch_parm *)rtw_zmalloc(sizeof(*set_ch_parm)); + if (set_ch_parm == NULL) { + res= _FAIL; + goto exit; + } + set_ch_parm->ch = ch; + set_ch_parm->bw = bw; + set_ch_parm->ch_offset = ch_offset; + + if (enqueue) { + /* need enqueue, prepare cmd_obj and enqueue */ + pcmdobj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(pcmdobj == NULL){ + rtw_mfree((u8 *)set_ch_parm, sizeof(*set_ch_parm)); + res=_FAIL; + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(pcmdobj, set_ch_parm, GEN_CMD_CODE(_SetChannel)); + res = rtw_enqueue_cmd(pcmdpriv, pcmdobj); + } else { + /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ + if( H2C_SUCCESS !=set_ch_hdl(padapter, (u8 *)set_ch_parm) ) + res = _FAIL; + + rtw_mfree((u8 *)set_ch_parm, sizeof(*set_ch_parm)); + } + + /* do something based on res... */ + +exit: + + DBG_871X(FUNC_NDEV_FMT" res:%u\n", FUNC_NDEV_ARG(padapter->pnetdev), res); + +_func_exit_; + + return res; +} + +u8 _rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, const struct country_chplan *country_ent, u8 swconfig) +{ + struct cmd_obj *cmdobj; + struct SetChannelPlan_param *parm; + struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct submit_ctx sctx; + u8 res = _SUCCESS; + +_func_enter_; + + /* check if allow software config */ + if (swconfig && rtw_hal_is_disable_sw_channel_plan(adapter) == _TRUE) { + res = _FAIL; + goto exit; + } + + /* if country_entry is provided, replace chplan */ + if (country_ent) + chplan = country_ent->chplan; + + /* check input parameter */ + if (!rtw_is_channel_plan_valid(chplan)) { + res = _FAIL; + goto exit; + } + + /* prepare cmd parameter */ + parm = (struct SetChannelPlan_param *)rtw_zmalloc(sizeof(*parm)); + if (parm == NULL) { + res = _FAIL; + goto exit; + } + parm->country_ent = country_ent; + parm->channel_plan = chplan; + + if (flags & RTW_CMDF_DIRECTLY) { + /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ + if (H2C_SUCCESS != set_chplan_hdl(adapter, (u8 *)parm)) + res = _FAIL; + rtw_mfree((u8 *)parm, sizeof(*parm)); + } else { + /* need enqueue, prepare cmd_obj and enqueue */ + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj)); + if (cmdobj == NULL) { + res = _FAIL; + rtw_mfree((u8 *)parm, sizeof(*parm)); + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_SetChannelPlan)); + + if (flags & RTW_CMDF_WAIT_ACK) { + cmdobj->sctx = &sctx; + rtw_sctx_init(&sctx, 2000); + } + + res = rtw_enqueue_cmd(pcmdpriv, cmdobj); + + if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { + rtw_sctx_wait(&sctx, __func__); + _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status == RTW_SCTX_SUBMITTED) + cmdobj->sctx = NULL; + _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + } + } + +exit: + +_func_exit_; + + return res; +} + +inline u8 rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, u8 swconfig) +{ + return _rtw_set_chplan_cmd(adapter, flags, chplan, NULL, swconfig); +} + +inline u8 rtw_set_country_cmd(_adapter *adapter, int flags, const char *country_code, u8 swconfig) +{ + const struct country_chplan *ent; + + if (is_alpha(country_code[0]) == _FALSE + || is_alpha(country_code[1]) == _FALSE + ) { + DBG_871X_LEVEL(_drv_always_, "%s input country_code is not alpha2\n", __func__); + return _FAIL; + } + + ent = rtw_get_chplan_from_country(country_code); + + if (ent == NULL) { + DBG_871X_LEVEL(_drv_always_, "%s unsupported country_code:\"%c%c\"\n", __func__, country_code[0], country_code[1]); + return _FAIL; + } + + DBG_871X_LEVEL(_drv_always_, "%s country_code:\"%c%c\" mapping to chplan:0x%02x\n", __func__, country_code[0], country_code[1], ent->chplan); + + return _rtw_set_chplan_cmd(adapter, flags, RTW_CHPLAN_MAX, ent, swconfig); +} + +u8 rtw_led_blink_cmd(_adapter*padapter, PVOID pLed) +{ + struct cmd_obj* pcmdobj; + struct LedBlink_param *ledBlink_param; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + + u8 res=_SUCCESS; + +_func_enter_; + + RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_led_blink_cmd\n")); + + pcmdobj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(pcmdobj == NULL){ + res=_FAIL; + goto exit; + } + + ledBlink_param = (struct LedBlink_param *)rtw_zmalloc(sizeof(struct LedBlink_param)); + if(ledBlink_param == NULL) { + rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj)); + res= _FAIL; + goto exit; + } + + ledBlink_param->pLed=pLed; + + init_h2fwcmd_w_parm_no_rsp(pcmdobj, ledBlink_param, GEN_CMD_CODE(_LedBlink)); + res = rtw_enqueue_cmd(pcmdpriv, pcmdobj); + +exit: + +_func_exit_; + + return res; +} + +u8 rtw_set_csa_cmd(_adapter*padapter, u8 new_ch_no) +{ + struct cmd_obj* pcmdobj; + struct SetChannelSwitch_param*setChannelSwitch_param; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + + u8 res=_SUCCESS; + +_func_enter_; + + RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_set_csa_cmd\n")); + + pcmdobj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(pcmdobj == NULL){ + res=_FAIL; + goto exit; + } + + setChannelSwitch_param = (struct SetChannelSwitch_param *)rtw_zmalloc(sizeof(struct SetChannelSwitch_param)); + if(setChannelSwitch_param == NULL) { + rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj)); + res= _FAIL; + goto exit; + } + + setChannelSwitch_param->new_ch_no=new_ch_no; + + init_h2fwcmd_w_parm_no_rsp(pcmdobj, setChannelSwitch_param, GEN_CMD_CODE(_SetChannelSwitch)); + res = rtw_enqueue_cmd(pcmdpriv, pcmdobj); + +exit: + +_func_exit_; + + return res; +} + +u8 rtw_tdls_cmd(_adapter *padapter, const u8 *addr, u8 option) +{ + struct cmd_obj* pcmdobj; + struct TDLSoption_param *TDLSoption; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + + u8 res=_SUCCESS; + +_func_enter_; + +#ifdef CONFIG_TDLS + + RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_set_tdls_cmd\n")); + + pcmdobj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(pcmdobj == NULL){ + res=_FAIL; + goto exit; + } + + TDLSoption= (struct TDLSoption_param *)rtw_zmalloc(sizeof(struct TDLSoption_param)); + if(TDLSoption == NULL) { + rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj)); + res= _FAIL; + goto exit; + } + + _rtw_spinlock(&(padapter->tdlsinfo.cmd_lock)); + if (addr != NULL) + _rtw_memcpy(TDLSoption->addr, addr, 6); + TDLSoption->option = option; + _rtw_spinunlock(&(padapter->tdlsinfo.cmd_lock)); + init_h2fwcmd_w_parm_no_rsp(pcmdobj, TDLSoption, GEN_CMD_CODE(_TDLS)); + res = rtw_enqueue_cmd(pcmdpriv, pcmdobj); + +#endif //CONFIG_TDLS + +exit: + + +_func_exit_; + + return res; +} + +u8 rtw_enable_hw_update_tsf_cmd(_adapter *padapter) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; + + + ph2c = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (pdrvextra_cmd_parm == NULL) { + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = EN_HW_UPDATE_TSF_WK_CID; + pdrvextra_cmd_parm->type = 0; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + return res; +} + + +static void collect_traffic_statistics(_adapter *padapter) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->adapter_type != PRIMARY_ADAPTER) + return; +#endif + + // Tx + pdvobjpriv->traffic_stat.tx_bytes = padapter->xmitpriv.tx_bytes; + pdvobjpriv->traffic_stat.tx_pkts = padapter->xmitpriv.tx_pkts; + pdvobjpriv->traffic_stat.tx_drop = padapter->xmitpriv.tx_drop; + + // Rx + pdvobjpriv->traffic_stat.rx_bytes = padapter->recvpriv.rx_bytes; + pdvobjpriv->traffic_stat.rx_pkts = padapter->recvpriv.rx_pkts; + pdvobjpriv->traffic_stat.rx_drop = padapter->recvpriv.rx_drop; + +#ifdef CONFIG_CONCURRENT_MODE + // Add secondary adapter statistics + if(rtw_buddy_adapter_up(padapter)) + { + // Tx + pdvobjpriv->traffic_stat.tx_bytes += padapter->pbuddy_adapter->xmitpriv.tx_bytes; + pdvobjpriv->traffic_stat.tx_pkts += padapter->pbuddy_adapter->xmitpriv.tx_pkts; + pdvobjpriv->traffic_stat.tx_drop += padapter->pbuddy_adapter->xmitpriv.tx_drop; + + // Rx + pdvobjpriv->traffic_stat.rx_bytes += padapter->pbuddy_adapter->recvpriv.rx_bytes; + pdvobjpriv->traffic_stat.rx_pkts += padapter->pbuddy_adapter->recvpriv.rx_pkts; + pdvobjpriv->traffic_stat.rx_drop += padapter->pbuddy_adapter->recvpriv.rx_drop; + } +#endif + + // Calculate throughput in last interval + pdvobjpriv->traffic_stat.cur_tx_bytes = pdvobjpriv->traffic_stat.tx_bytes - pdvobjpriv->traffic_stat.last_tx_bytes; + pdvobjpriv->traffic_stat.cur_rx_bytes = pdvobjpriv->traffic_stat.rx_bytes - pdvobjpriv->traffic_stat.last_rx_bytes; + pdvobjpriv->traffic_stat.last_tx_bytes = pdvobjpriv->traffic_stat.tx_bytes; + pdvobjpriv->traffic_stat.last_rx_bytes = pdvobjpriv->traffic_stat.rx_bytes; + + pdvobjpriv->traffic_stat.cur_tx_tp = (u32)(pdvobjpriv->traffic_stat.cur_tx_bytes *8/2/1024/1024); + pdvobjpriv->traffic_stat.cur_rx_tp = (u32)(pdvobjpriv->traffic_stat.cur_rx_bytes *8/2/1024/1024); +} + +//from_timer == 1 means driver is in LPS +u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer) +{ + u8 bEnterPS = _FALSE; + u16 BusyThresholdHigh; + u16 BusyThresholdLow; + u16 BusyThreshold; + u8 bBusyTraffic = _FALSE, bTxBusyTraffic = _FALSE, bRxBusyTraffic = _FALSE; + u8 bHigherBusyTraffic = _FALSE, bHigherBusyRxTraffic = _FALSE, bHigherBusyTxTraffic = _FALSE; + + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); +#ifdef CONFIG_TDLS + struct tdls_info *ptdlsinfo = &(padapter->tdlsinfo); + struct tdls_txmgmt txmgmt; + u8 baddr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; +#endif //CONFIG_TDLS + + RT_LINK_DETECT_T * link_detect = &pmlmepriv->LinkDetectInfo; + +#ifdef CONFIG_BT_COEXIST + if (padapter->registrypriv.wifi_spec != 1) { + BusyThresholdHigh = 25; + BusyThresholdLow = 10; + } else +#endif /* CONFIG_BT_COEXIST */ + { + BusyThresholdHigh = 100; + BusyThresholdLow = 75; + } + BusyThreshold = BusyThresholdHigh; + + collect_traffic_statistics(padapter); + + // + // Determine if our traffic is busy now + // + if((check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) + /*&& !MgntInitAdapterInProgress(pMgntInfo)*/) + { + // if we raise bBusyTraffic in last watchdog, using lower threshold. + if (pmlmepriv->LinkDetectInfo.bBusyTraffic) + BusyThreshold = BusyThresholdLow; + + if( pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > BusyThreshold || + pmlmepriv->LinkDetectInfo.NumTxOkInPeriod > BusyThreshold ) + { + bBusyTraffic = _TRUE; + + if (pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > pmlmepriv->LinkDetectInfo.NumTxOkInPeriod) + bRxBusyTraffic = _TRUE; + else + bTxBusyTraffic = _TRUE; + } + + // Higher Tx/Rx data. + if( pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > 4000 || + pmlmepriv->LinkDetectInfo.NumTxOkInPeriod > 4000 ) + { + bHigherBusyTraffic = _TRUE; + + if (pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > pmlmepriv->LinkDetectInfo.NumTxOkInPeriod) + bHigherBusyRxTraffic = _TRUE; + else + bHigherBusyTxTraffic = _TRUE; + } + +#ifdef CONFIG_TRAFFIC_PROTECT +#define TX_ACTIVE_TH 10 +#define RX_ACTIVE_TH 20 +#define TRAFFIC_PROTECT_PERIOD_MS 4500 + + if (link_detect->NumTxOkInPeriod > TX_ACTIVE_TH + || link_detect->NumRxUnicastOkInPeriod > RX_ACTIVE_TH) { + + DBG_871X_LEVEL(_drv_info_, FUNC_ADPT_FMT" acqiure wake_lock for %u ms(tx:%d,rx_unicast:%d)\n", + FUNC_ADPT_ARG(padapter), + TRAFFIC_PROTECT_PERIOD_MS, + link_detect->NumTxOkInPeriod, + link_detect->NumRxUnicastOkInPeriod); + + rtw_lock_traffic_suspend_timeout(TRAFFIC_PROTECT_PERIOD_MS); + } +#endif + +#ifdef CONFIG_TDLS +#ifdef CONFIG_TDLS_AUTOSETUP + /* TDLS_WATCHDOG_PERIOD * 2sec, periodically send */ + if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _TRUE) { + if ((ptdlsinfo->watchdog_count % TDLS_WATCHDOG_PERIOD) == 0) { + _rtw_memcpy(txmgmt.peer, baddr, ETH_ALEN); + issue_tdls_dis_req(padapter, &txmgmt); + } + ptdlsinfo->watchdog_count++; + } +#endif //CONFIG_TDLS_AUTOSETUP +#endif //CONFIG_TDLS + +#ifdef CONFIG_LPS + // check traffic for powersaving. + if( ((pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod + pmlmepriv->LinkDetectInfo.NumTxOkInPeriod) > 8 ) || +#ifdef CONFIG_LPS_SLOW_TRANSITION + (pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod > 2) +#else //CONFIG_LPS_SLOW_TRANSITION + (pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod > 4) +#endif //CONFIG_LPS_SLOW_TRANSITION + ) + { +#ifdef DBG_RX_COUNTER_DUMP + if( padapter->dump_rx_cnt_mode & DUMP_DRV_TRX_COUNTER_DATA) + DBG_871X("(-)Tx = %d, Rx = %d \n",pmlmepriv->LinkDetectInfo.NumTxOkInPeriod,pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod); +#endif + bEnterPS= _FALSE; +#ifdef CONFIG_LPS_SLOW_TRANSITION + if(bBusyTraffic == _TRUE) + { + if(pmlmepriv->LinkDetectInfo.TrafficTransitionCount <= 4) + pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 4; + + pmlmepriv->LinkDetectInfo.TrafficTransitionCount++; + + //DBG_871X("Set TrafficTransitionCount to %d\n", pmlmepriv->LinkDetectInfo.TrafficTransitionCount); + + if(pmlmepriv->LinkDetectInfo.TrafficTransitionCount > 30/*TrafficTransitionLevel*/) + { + pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 30; + } + } +#endif //CONFIG_LPS_SLOW_TRANSITION + + } + else + { +#ifdef DBG_RX_COUNTER_DUMP + if( padapter->dump_rx_cnt_mode & DUMP_DRV_TRX_COUNTER_DATA) + DBG_871X("(+)Tx = %d, Rx = %d \n",pmlmepriv->LinkDetectInfo.NumTxOkInPeriod,pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod); +#endif +#ifdef CONFIG_LPS_SLOW_TRANSITION + if(pmlmepriv->LinkDetectInfo.TrafficTransitionCount>=2) + pmlmepriv->LinkDetectInfo.TrafficTransitionCount -=2; + else + pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0; + + if(pmlmepriv->LinkDetectInfo.TrafficTransitionCount == 0) + bEnterPS= _TRUE; +#else //CONFIG_LPS_SLOW_TRANSITION + bEnterPS= _TRUE; +#endif //CONFIG_LPS_SLOW_TRANSITION + } + +#ifdef CONFIG_DYNAMIC_DTIM + if(pmlmepriv->LinkDetectInfo.LowPowerTransitionCount == 8) + bEnterPS= _FALSE; + + DBG_871X("LowPowerTransitionCount=%d\n", pmlmepriv->LinkDetectInfo.LowPowerTransitionCount); +#endif //CONFIG_DYNAMIC_DTIM + + // LeisurePS only work in infra mode. + if(bEnterPS) + { + if(!from_timer) + { +#ifdef CONFIG_DYNAMIC_DTIM + if(pmlmepriv->LinkDetectInfo.LowPowerTransitionCount < 8) + { + adapter_to_pwrctl(padapter)->dtim = 1; + } + else + { + adapter_to_pwrctl(padapter)->dtim = 3; + } +#endif //CONFIG_DYNAMIC_DTIM + LPS_Enter(padapter, "TRAFFIC_IDLE"); + } + else + { + //do this at caller + //rtw_lps_ctrl_wk_cmd(adapter, LPS_CTRL_ENTER, 1); + //rtw_hal_dm_watchdog_in_lps(padapter); + } +#ifdef CONFIG_DYNAMIC_DTIM + if (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode ==_TRUE ) + pmlmepriv->LinkDetectInfo.LowPowerTransitionCount++; +#endif //CONFIG_DYNAMIC_DTIM + } + else + { +#ifdef CONFIG_DYNAMIC_DTIM + if(pmlmepriv->LinkDetectInfo.LowPowerTransitionCount != 8) + pmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0; + else + pmlmepriv->LinkDetectInfo.LowPowerTransitionCount++; +#endif //CONFIG_DYNAMIC_DTIM + if(!from_timer) + { + LPS_Leave(padapter, "TRAFFIC_BUSY"); + } + else + { +#ifdef CONFIG_CONCURRENT_MODE + if(padapter->iface_type == IFACE_PORT0) +#endif + rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_TRAFFIC_BUSY, 1); + } + } + +#endif // CONFIG_LPS + } + else + { +#ifdef CONFIG_LPS + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + int n_assoc_iface = 0; + int i; + + for (i = 0; i < dvobj->iface_nums; i++) { + if (check_fwstate(&(dvobj->padapters[i]->mlmepriv), WIFI_ASOC_STATE)) + n_assoc_iface++; + } + + if(!from_timer && n_assoc_iface == 0) + LPS_Leave(padapter, "NON_LINKED"); +#endif + } + + session_tracker_chk_cmd(padapter, NULL); + + pmlmepriv->LinkDetectInfo.NumRxOkInPeriod = 0; + pmlmepriv->LinkDetectInfo.NumTxOkInPeriod = 0; + pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod = 0; + pmlmepriv->LinkDetectInfo.bBusyTraffic = bBusyTraffic; + pmlmepriv->LinkDetectInfo.bTxBusyTraffic = bTxBusyTraffic; + pmlmepriv->LinkDetectInfo.bRxBusyTraffic = bRxBusyTraffic; + pmlmepriv->LinkDetectInfo.bHigherBusyTraffic = bHigherBusyTraffic; + pmlmepriv->LinkDetectInfo.bHigherBusyRxTraffic = bHigherBusyRxTraffic; + pmlmepriv->LinkDetectInfo.bHigherBusyTxTraffic = bHigherBusyTxTraffic; + + return bEnterPS; + +} + +void dynamic_chk_wk_hdl(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv; + pmlmepriv = &(padapter->mlmepriv); + +#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK +#ifdef CONFIG_AP_MODE + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + { + expire_timeout_chk(padapter); + } +#endif +#endif //CONFIG_ACTIVE_KEEP_ALIVE_CHECK + +#ifdef DBG_CONFIG_ERROR_DETECT + rtw_hal_sreset_xmit_status_check(padapter); + rtw_hal_sreset_linked_status_check(padapter); +#endif + + //for debug purpose + _linked_info_dump(padapter); + + + //if(check_fwstate(pmlmepriv, _FW_UNDER_LINKING|_FW_UNDER_SURVEY)==_FALSE) + { + linked_status_chk(padapter, 0); + traffic_status_watchdog(padapter, 0); + #ifdef DBG_RX_COUNTER_DUMP + rtw_dump_rx_counters(padapter); + #endif + dm_DynamicUsbTxAgg(padapter, 0); + } + +#ifdef CONFIG_BEAMFORMING +#if (BEAMFORMING_SUPPORT == 0) /*for diver defined beamforming*/ + beamforming_watchdog(padapter); +#endif +#endif + + rtw_hal_dm_watchdog(padapter); + + //check_hw_pbc(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->type); + +#ifdef CONFIG_BT_COEXIST + // + // BT-Coexist + // + rtw_btcoex_Handler(padapter); +#endif + + +#ifdef CONFIG_IPS_CHECK_IN_WD + //always call rtw_ps_processor() at last one. + if (is_primary_adapter(padapter)) + rtw_ps_processor(padapter); +#endif +} + +#ifdef CONFIG_LPS + +void lps_ctrl_wk_hdl(_adapter *padapter, u8 lps_ctrl_type); +void lps_ctrl_wk_hdl(_adapter *padapter, u8 lps_ctrl_type) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u8 mstatus; + +_func_enter_; + + if((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) + || (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) + { + return; + } + + switch(lps_ctrl_type) + { + case LPS_CTRL_SCAN: + //DBG_871X("LPS_CTRL_SCAN \n"); +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_ScanNotify(padapter, _TRUE); +#endif // CONFIG_BT_COEXIST + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + { + // connect + LPS_Leave(padapter, "LPS_CTRL_SCAN"); + } + break; + case LPS_CTRL_JOINBSS: + //DBG_871X("LPS_CTRL_JOINBSS \n"); + LPS_Leave(padapter, "LPS_CTRL_JOINBSS"); + break; + case LPS_CTRL_CONNECT: + //DBG_871X("LPS_CTRL_CONNECT \n"); + mstatus = 1;//connect + // Reset LPS Setting + pwrpriv->LpsIdleCount = 0; + rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)(&mstatus)); +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_MediaStatusNotify(padapter, mstatus); +#endif // CONFIG_BT_COEXIST + break; + case LPS_CTRL_DISCONNECT: + //DBG_871X("LPS_CTRL_DISCONNECT \n"); + mstatus = 0;//disconnect +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_MediaStatusNotify(padapter, mstatus); +#endif // CONFIG_BT_COEXIST + LPS_Leave(padapter, "LPS_CTRL_DISCONNECT"); + rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)(&mstatus)); + break; + case LPS_CTRL_SPECIAL_PACKET: + //DBG_871X("LPS_CTRL_SPECIAL_PACKET \n"); + pwrpriv->DelayLPSLastTimeStamp = rtw_get_current_time(); +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_SpecialPacketNotify(padapter, PACKET_DHCP); +#endif // CONFIG_BT_COEXIST + LPS_Leave(padapter, "LPS_CTRL_SPECIAL_PACKET"); + break; + case LPS_CTRL_LEAVE: + LPS_Leave(padapter, "LPS_CTRL_LEAVE"); + break; + case LPS_CTRL_LEAVE_CFG80211_PWRMGMT: + LPS_Leave(padapter, "CFG80211_PWRMGMT"); + break; + case LPS_CTRL_TRAFFIC_BUSY: + LPS_Leave(padapter, "LPS_CTRL_TRAFFIC_BUSY"); + break; + case LPS_CTRL_TX_TRAFFIC_LEAVE: + LPS_Leave(padapter, "LPS_CTRL_TX_TRAFFIC_LEAVE"); + break; + case LPS_CTRL_RX_TRAFFIC_LEAVE: + LPS_Leave(padapter, "LPS_CTRL_RX_TRAFFIC_LEAVE"); + break; + case LPS_CTRL_ENTER: + LPS_Enter(padapter, "TRAFFIC_IDLE_1"); + break; + default: + break; + } + +_func_exit_; +} + +u8 rtw_lps_ctrl_wk_cmd(_adapter*padapter, u8 lps_ctrl_type, u8 enqueue) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + //struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + u8 res = _SUCCESS; + +_func_enter_; + + //if(!pwrctrlpriv->bLeisurePs) + // return res; + + if(enqueue) + { + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(ph2c==NULL){ + res= _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if(pdrvextra_cmd_parm==NULL){ + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res= _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = LPS_CTRL_WK_CID; + pdrvextra_cmd_parm->type = lps_ctrl_type; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + } + else + { + lps_ctrl_wk_hdl(padapter, lps_ctrl_type); + } + +exit: + +_func_exit_; + + return res; + +} + +void rtw_dm_in_lps_hdl(_adapter*padapter) +{ + rtw_hal_set_hwreg(padapter, HW_VAR_DM_IN_LPS, NULL); +} + +u8 rtw_dm_in_lps_wk_cmd(_adapter*padapter) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; + + + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(ph2c==NULL){ + res= _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if(pdrvextra_cmd_parm==NULL){ + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res= _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = DM_IN_LPS_WK_CID; + pdrvextra_cmd_parm->type = 0; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + + return res; + +} + +void rtw_lps_change_dtim_hdl(_adapter *padapter, u8 dtim) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + + if(dtim <=0 || dtim > 16) + return; + +#ifdef CONFIG_BT_COEXIST + if (rtw_btcoex_IsBtControlLps(padapter) == _TRUE) + return; +#endif + +#ifdef CONFIG_LPS_LCLK + _enter_pwrlock(&pwrpriv->lock); +#endif + + if(pwrpriv->dtim!=dtim) + { + DBG_871X("change DTIM from %d to %d, bFwCurrentInPSMode=%d, ps_mode=%d\n", pwrpriv->dtim, dtim, + pwrpriv->bFwCurrentInPSMode, pwrpriv->pwr_mode); + + pwrpriv->dtim = dtim; + } + + if((pwrpriv->bFwCurrentInPSMode ==_TRUE) && (pwrpriv->pwr_mode > PS_MODE_ACTIVE)) + { + u8 ps_mode = pwrpriv->pwr_mode; + + //DBG_871X("change DTIM from %d to %d, ps_mode=%d\n", pwrpriv->dtim, dtim, ps_mode); + + rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode)); + } + +#ifdef CONFIG_LPS_LCLK + _exit_pwrlock(&pwrpriv->lock); +#endif + +} + +#endif + +u8 rtw_lps_change_dtim_cmd(_adapter*padapter, u8 dtim) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; +/* +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->iface_type != IFACE_PORT0) + return res; +#endif +*/ + { + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(ph2c==NULL){ + res= _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if(pdrvextra_cmd_parm==NULL){ + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res= _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = LPS_CHANGE_DTIM_CID; + pdrvextra_cmd_parm->type = dtim; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + } + +exit: + + return res; + +} + +#if (RATE_ADAPTIVE_SUPPORT==1) +void rpt_timer_setting_wk_hdl(_adapter *padapter, u16 minRptTime) +{ + rtw_hal_set_hwreg(padapter, HW_VAR_RPT_TIMER_SETTING, (u8 *)(&minRptTime)); +} + +u8 rtw_rpt_timer_cfg_cmd(_adapter*padapter, u16 minRptTime) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + + u8 res = _SUCCESS; + +_func_enter_; + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(ph2c==NULL){ + res= _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if(pdrvextra_cmd_parm==NULL){ + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res= _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = RTP_TIMER_CFG_WK_CID; + pdrvextra_cmd_parm->type = minRptTime; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + res = rtw_enqueue_cmd(pcmdpriv, ph2c); +exit: + +_func_exit_; + + return res; + +} + +#endif + +#ifdef CONFIG_ANTENNA_DIVERSITY +void antenna_select_wk_hdl(_adapter *padapter, u8 antenna) +{ + rtw_hal_set_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &antenna, _TRUE); +} + +u8 rtw_antenna_select_cmd(_adapter*padapter, u8 antenna,u8 enqueue) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + u8 bSupportAntDiv = _FALSE; + u8 res = _SUCCESS; + int i; + +_func_enter_; + rtw_hal_get_def_var(padapter, HAL_DEF_IS_SUPPORT_ANT_DIV, &(bSupportAntDiv)); + if (_FALSE == bSupportAntDiv) + return _FAIL; + + for (i = 0; i < dvobj->iface_nums; i++) { + if (rtw_linked_check(dvobj->padapters[i])) + return _FAIL; + } + + if(_TRUE == enqueue) + { + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(ph2c==NULL){ + res= _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if(pdrvextra_cmd_parm==NULL){ + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res= _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = ANT_SELECT_WK_CID; + pdrvextra_cmd_parm->type = antenna; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + } + else{ + antenna_select_wk_hdl(padapter,antenna ); + } +exit: + +_func_exit_; + + return res; + +} +#endif + +void rtw_dm_ra_mask_hdl(_adapter *padapter, struct sta_info *psta) +{ + if (psta) { + set_sta_rate(padapter, psta); + } +} + +u8 rtw_dm_ra_mask_wk_cmd(_adapter*padapter, u8 *psta) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; + + + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(ph2c==NULL){ + res= _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if(pdrvextra_cmd_parm==NULL){ + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res= _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = DM_RA_MSK_WK_CID; + pdrvextra_cmd_parm->type = 0; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = psta; + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + + return res; + +} + +void power_saving_wk_hdl(_adapter *padapter) +{ + rtw_ps_processor(padapter); +} + +//add for CONFIG_IEEE80211W, none 11w can use it +void reset_securitypriv_hdl(_adapter *padapter) +{ + rtw_reset_securitypriv(padapter); +} + +void free_assoc_resources_hdl(_adapter *padapter) +{ + rtw_free_assoc_resources(padapter, 1); +} + +#ifdef CONFIG_P2P +u8 p2p_protocol_wk_cmd(_adapter*padapter, int intCmdType ) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; + +_func_enter_; + + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + { + return res; + } + + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(ph2c==NULL){ + res= _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if(pdrvextra_cmd_parm==NULL){ + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res= _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = P2P_PROTO_WK_CID; + pdrvextra_cmd_parm->type = intCmdType; // As the command tppe. + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; // Must be NULL here + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + +_func_exit_; + + return res; + +} +#endif //CONFIG_P2P + +u8 rtw_ps_cmd(_adapter*padapter) +{ + struct cmd_obj *ppscmd; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + + u8 res = _SUCCESS; +_func_enter_; + +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->adapter_type != PRIMARY_ADAPTER) + goto exit; +#endif + + ppscmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(ppscmd==NULL){ + res= _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if(pdrvextra_cmd_parm==NULL){ + rtw_mfree((unsigned char *)ppscmd, sizeof(struct cmd_obj)); + res= _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = POWER_SAVING_CTRL_WK_CID; + pdrvextra_cmd_parm->type = 0; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; + init_h2fwcmd_w_parm_no_rsp(ppscmd, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, ppscmd); + +exit: + +_func_exit_; + + return res; + +} + +#ifdef CONFIG_AP_MODE + +static void rtw_chk_hi_queue_hdl(_adapter *padapter) +{ + struct sta_info *psta_bmc; + struct sta_priv *pstapriv = &padapter->stapriv; + u32 start = rtw_get_current_time(); + u8 empty = _FALSE; + + psta_bmc = rtw_get_bcmc_stainfo(padapter); + if(!psta_bmc) + return; + + rtw_hal_get_hwreg(padapter, HW_VAR_CHK_HI_QUEUE_EMPTY, &empty); + + while(_FALSE == empty && rtw_get_passing_time_ms(start) < rtw_get_wait_hiq_empty_ms()) + { + rtw_msleep_os(100); + rtw_hal_get_hwreg(padapter, HW_VAR_CHK_HI_QUEUE_EMPTY, &empty); + } + + if(psta_bmc->sleepq_len==0) + { + if(empty == _SUCCESS) + { + bool update_tim = _FALSE; + + if (pstapriv->tim_bitmap & BIT(0)) + update_tim = _TRUE; + + pstapriv->tim_bitmap &= ~BIT(0); + pstapriv->sta_dz_bitmap &= ~BIT(0); + + if (update_tim == _TRUE) + _update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "bmc sleepq and HIQ empty"); + } + else //re check again + { + rtw_chk_hi_queue_cmd(padapter); + } + + } + +} + +u8 rtw_chk_hi_queue_cmd(_adapter*padapter) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; + + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(ph2c==NULL){ + res= _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if(pdrvextra_cmd_parm==NULL){ + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res= _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = CHECK_HIQ_WK_CID; + pdrvextra_cmd_parm->type = 0; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + + return res; + +} + +#ifdef CONFIG_DFS_MASTER +u8 rtw_dfs_master_hdl(_adapter *adapter) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + struct mlme_priv *mlme = &adapter->mlmepriv; + + if (!rfctl->dfs_master_enabled) + goto exit; + + if (rtw_get_on_cur_ch_time(adapter) == 0 + || rtw_get_passing_time_ms(rtw_get_on_cur_ch_time(adapter)) < 300 + ) { + /* offchannel , by pass radar detect */ + goto cac_status_chk; + } + + if (rfctl->dbg_dfs_master_fake_radar_detect_cnt + || rtw_odm_radar_detect(adapter) == _TRUE + ) { + if (rfctl->dbg_dfs_master_fake_radar_detect_cnt != 0) { + DBG_871X(FUNC_ADPT_FMT" fake radar detect, cnt:%d\n", FUNC_ADPT_ARG(adapter) + , rfctl->dbg_dfs_master_fake_radar_detect_cnt); + rfctl->dbg_dfs_master_fake_radar_detect_cnt--; + } + + if (rfctl->dbg_dfs_master_radar_detect_trigger_non) { + /* radar detect debug mode, trigger no mlme flow */ + DBG_871X(FUNC_ADPT_FMT" radar detected, trigger no mlme flow for debug\n", FUNC_ADPT_ARG(adapter)); + } else { + /* TODO: move timer to rfctl */ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + int i; + + for (i = 0; i < dvobj->iface_nums; i++) { + if (!dvobj->padapters[i]) + continue; + if (check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_AP_STATE) + && check_fwstate(&dvobj->padapters[i]->mlmepriv, WIFI_AP_STATE)) + break; + } + + if (i >= dvobj->iface_nums) { + /* what? */ + rtw_warn_on(1); + } else { + rtw_chset_update_non_ocp(dvobj->padapters[i]->mlmeextpriv.channel_set + , rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset); + + /* change op ch, inform ch switch */ + rtw_change_bss_chbw_cmd(dvobj->padapters[i], RTW_CMDF_DIRECTLY, 0, 0, 0); + } + + if (rfctl->dfs_master_enabled) + goto set_timer; + goto exit; + } + } + +cac_status_chk: + + if (!IS_UNDER_CAC(rfctl) && !IS_CAC_STOPPED(rfctl)) { + u8 pause = 0x00; + + rtw_hal_set_hwreg(adapter, HW_VAR_TXPAUSE, &pause); + rfctl->cac_end_time = RTW_CAC_STOPPED; + } + +set_timer: + _set_timer(&mlme->dfs_master_timer, DFS_MASTER_TIMER_MS); + +exit: + return H2C_SUCCESS; +} + +u8 rtw_dfs_master_cmd(_adapter *adapter, bool enqueue) +{ + struct cmd_obj *cmdobj; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + u8 res = _FAIL; + + if (enqueue) { + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmdobj == NULL) + goto exit; + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (pdrvextra_cmd_parm == NULL) { + rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj)); + goto exit; + } + + pdrvextra_cmd_parm->ec_id = DFS_MASTER_WK_CID; + pdrvextra_cmd_parm->type = 0; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; + + init_h2fwcmd_w_parm_no_rsp(cmdobj, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + res = rtw_enqueue_cmd(pcmdpriv, cmdobj); + } else { + rtw_dfs_master_hdl(adapter); + res = _SUCCESS; + } + +exit: + return res; +} + +void rtw_dfs_master_timer_hdl(RTW_TIMER_HDL_ARGS) +{ + _adapter *adapter = (_adapter *)FunctionContext; + + rtw_dfs_master_cmd(adapter, _TRUE); +} + +void rtw_dfs_master_enable(_adapter *adapter, u8 ch, u8 bw, u8 offset) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + + /* TODO: move timer to rfctl */ + adapter = GET_PRIMARY_ADAPTER(adapter); + + DBG_871X(FUNC_ADPT_FMT" on %u,%u,%u\n", FUNC_ADPT_ARG(adapter), ch, bw, offset); + + rfctl->pre_radar_detect_by_sta_link = rfctl->radar_detect_by_sta_link; + rfctl->radar_detect_by_sta_link = _FALSE; + + rfctl->pre_radar_detect_ch = rfctl->radar_detect_ch; + rfctl->pre_radar_detect_bw = rfctl->radar_detect_bw; + rfctl->pre_radar_detect_offset = rfctl->radar_detect_offset; + rfctl->radar_detect_ch = ch; + rfctl->radar_detect_bw = bw; + rfctl->radar_detect_offset = offset; + + if (rtw_is_cac_reset_needed(adapter) == _TRUE) + rtw_rfctl_reset_cac(adapter_to_rfctl(adapter)); + + if (!rfctl->dfs_master_enabled) { + DBG_871X(FUNC_ADPT_FMT" set dfs_master_enabled\n", FUNC_ADPT_ARG(adapter)); + rfctl->dfs_master_enabled = 1; + _set_timer(&adapter->mlmepriv.dfs_master_timer, DFS_MASTER_TIMER_MS); + + if (rtw_rfctl_overlap_radar_detect_ch(rfctl)) { + if (IS_UNDER_CAC(rfctl)) { + u8 pause = 0xFF; + + rtw_hal_set_hwreg(adapter, HW_VAR_TXPAUSE, &pause); + } + rtw_odm_radar_detect_enable(adapter); + } + } +} + +void rtw_dfs_master_disable(_adapter *adapter, bool ld_sta_in_dfs) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + + /* TODO: move timer to rfctl */ + adapter = GET_PRIMARY_ADAPTER(adapter); + + rfctl->pre_radar_detect_by_sta_link = rfctl->radar_detect_by_sta_link; + rfctl->radar_detect_by_sta_link = ld_sta_in_dfs; + + if (rfctl->dfs_master_enabled) { + bool overlap_radar_detect_ch = rtw_rfctl_overlap_radar_detect_ch(rfctl); + + DBG_871X(FUNC_ADPT_FMT" clear dfs_master_enabled\n", FUNC_ADPT_ARG(adapter)); + + rfctl->dfs_master_enabled = 0; + rfctl->radar_detect_ch = rfctl->pre_radar_detect_ch = 0; + rfctl->radar_detect_bw = rfctl->pre_radar_detect_bw = 0; + rfctl->radar_detect_offset = rfctl->pre_radar_detect_offset = 0; + rfctl->cac_end_time = RTW_CAC_STOPPED; + _cancel_timer_ex(&adapter->mlmepriv.dfs_master_timer); + + if (overlap_radar_detect_ch) { + u8 pause = 0x00; + + rtw_hal_set_hwreg(adapter, HW_VAR_TXPAUSE, &pause); + rtw_odm_radar_detect_disable(adapter); + } + } +} + +void rtw_dfs_master_status_apply(_adapter *adapter, u8 self_action) +{ + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + u8 ld_sta_num, lg_sta_num, ap_num; + u8 u_ch, u_bw, u_offset; + bool ld_sta_in_dfs = _FALSE; + bool sync_ch = _FALSE; /* _FALSE: asign channel directly */ + bool needed = _FALSE; + + rtw_dev_iface_status_no_self(adapter, NULL, &ld_sta_num, &lg_sta_num, &ap_num, NULL); + rtw_get_ch_setting_union_no_self(adapter, &u_ch, &u_bw, &u_offset); + if (u_ch != 0) + sync_ch = _TRUE; + + switch (self_action) { + case MLME_STA_CONNECTING: + lg_sta_num++; + break; + case MLME_STA_CONNECTED: + ld_sta_num++; + break; + case MLME_AP_STARTED: + ap_num++; + break; + case MLME_AP_STOPPED: + case MLME_STA_DISCONNECTED: + default: + break; + } + + if (sync_ch == _TRUE) { + if (!rtw_is_chbw_grouped(mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset, u_ch, u_bw, u_offset)) { + DBG_871X(FUNC_ADPT_FMT" can't sync %u,%u,%u with %u,%u,%u\n", FUNC_ADPT_ARG(adapter) + , mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset, u_ch, u_bw, u_offset); + goto apply; + } + + rtw_sync_chbw(&mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset + , &u_ch, &u_bw, &u_offset); + } else { + u_ch = mlmeext->cur_channel; + u_bw = mlmeext->cur_bwmode; + u_offset = mlmeext->cur_ch_offset; + } + + if (ld_sta_num > 0) { + /* rely on AP on which STA mode connects */ + if (rtw_is_dfs_ch(u_ch, u_bw, u_offset)) + ld_sta_in_dfs = _TRUE; + goto apply; + } + + if (lg_sta_num > 0) { + /* STA mode is linking */ + goto apply; + } + + if (ap_num == 0) { + /* No working AP mode */ + goto apply; + } + + if (rtw_is_dfs_ch(u_ch, u_bw, u_offset)) + needed = _TRUE; + +apply: + + DBG_871X(FUNC_ADPT_FMT" needed:%d, self_action:%u\n" + , FUNC_ADPT_ARG(adapter), needed, self_action); + DBG_871X(FUNC_ADPT_FMT" ld_sta_num:%u, lg_sta_num:%u, ap_num:%u, %u,%u,%u\n" + , FUNC_ADPT_ARG(adapter), ld_sta_num, lg_sta_num, ap_num, u_ch, u_bw, u_offset); + + if (needed == _TRUE) + rtw_dfs_master_enable(adapter, u_ch, u_bw, u_offset); + else + rtw_dfs_master_disable(adapter, ld_sta_in_dfs); +} +#endif /* CONFIG_DFS_MASTER */ + +#endif /* CONFIG_AP_MODE */ + +#ifdef CONFIG_BT_COEXIST +struct btinfo { + u8 cid; + u8 len; + + u8 bConnection:1; + u8 bSCOeSCO:1; + u8 bInQPage:1; + u8 bACLBusy:1; + u8 bSCOBusy:1; + u8 bHID:1; + u8 bA2DP:1; + u8 bFTP:1; + + u8 retry_cnt:4; + u8 rsvd_34:1; + u8 rsvd_35:1; + u8 rsvd_36:1; + u8 rsvd_37:1; + + u8 rssi; + + u8 rsvd_50:1; + u8 rsvd_51:1; + u8 rsvd_52:1; + u8 rsvd_53:1; + u8 rsvd_54:1; + u8 rsvd_55:1; + u8 eSCO_SCO:1; + u8 Master_Slave:1; + + u8 rsvd_6; + u8 rsvd_7; +}; + +void btinfo_evt_dump(void *sel, void *buf) +{ + struct btinfo *info = (struct btinfo *)buf; + + DBG_871X_SEL_NL(sel, "cid:0x%02x, len:%u\n", info->cid, info->len); + + if (info->len > 2) + DBG_871X_SEL_NL(sel, "byte2:%s%s%s%s%s%s%s%s\n" + , info->bConnection?"bConnection ":"" + , info->bSCOeSCO?"bSCOeSCO ":"" + , info->bInQPage?"bInQPage ":"" + , info->bACLBusy?"bACLBusy ":"" + , info->bSCOBusy?"bSCOBusy ":"" + , info->bHID?"bHID ":"" + , info->bA2DP?"bA2DP ":"" + , info->bFTP?"bFTP":"" + ); + + if (info->len > 3) + DBG_871X_SEL_NL(sel, "retry_cnt:%u\n", info->retry_cnt); + + if (info->len > 4) + DBG_871X_SEL_NL(sel, "rssi:%u\n", info->rssi); + + if (info->len > 5) + DBG_871X_SEL_NL(sel, "byte5:%s%s\n" + , info->eSCO_SCO?"eSCO_SCO ":"" + , info->Master_Slave?"Master_Slave ":"" + ); +} + +static void rtw_btinfo_hdl(_adapter *adapter, u8 *buf, u16 buf_len) +{ + #define BTINFO_WIFI_FETCH 0x23 + #define BTINFO_BT_AUTO_RPT 0x27 +#ifdef CONFIG_BT_COEXIST_SOCKET_TRX + struct btinfo_8761ATV *info = (struct btinfo_8761ATV *)buf; +#else //!CONFIG_BT_COEXIST_SOCKET_TRX + struct btinfo *info = (struct btinfo *)buf; +#endif //CONFIG_BT_COEXIST_SOCKET_TRX + u8 cmd_idx; + u8 len; + + cmd_idx = info->cid; + + if (info->len > buf_len-2) { + rtw_warn_on(1); + len = buf_len-2; + } else { + len = info->len; + } + +//#define DBG_PROC_SET_BTINFO_EVT +#ifdef DBG_PROC_SET_BTINFO_EVT +#ifdef CONFIG_BT_COEXIST_SOCKET_TRX + DBG_871X("%s: btinfo[0]=%x,btinfo[1]=%x,btinfo[2]=%x,btinfo[3]=%x btinfo[4]=%x,btinfo[5]=%x,btinfo[6]=%x,btinfo[7]=%x\n" + , __func__, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]); +#else//!CONFIG_BT_COEXIST_SOCKET_TRX + btinfo_evt_dump(RTW_DBGDUMP, info); +#endif //CONFIG_BT_COEXIST_SOCKET_TRX +#endif // DBG_PROC_SET_BTINFO_EVT + + /* transform BT-FW btinfo to WiFI-FW C2H format and notify */ + if (cmd_idx == BTINFO_WIFI_FETCH) + buf[1] = 0; + else if (cmd_idx == BTINFO_BT_AUTO_RPT) + buf[1] = 2; +#ifdef CONFIG_BT_COEXIST_SOCKET_TRX + else if(0x01 == cmd_idx || 0x02 == cmd_idx) + buf[1] = buf[0]; +#endif //CONFIG_BT_COEXIST_SOCKET_TRX + rtw_btcoex_BtInfoNotify(adapter ,len+1, &buf[1]); +} + +u8 rtw_btinfo_cmd(_adapter *adapter, u8 *buf, u16 len) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + u8 *btinfo; + struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + u8 res = _SUCCESS; + + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (pdrvextra_cmd_parm == NULL) { + rtw_mfree((u8*)ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + btinfo = rtw_zmalloc(len); + if (btinfo == NULL) { + rtw_mfree((u8*)ph2c, sizeof(struct cmd_obj)); + rtw_mfree((u8*)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm)); + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = BTINFO_WK_CID; + pdrvextra_cmd_parm->type = 0; + pdrvextra_cmd_parm->size = len; + pdrvextra_cmd_parm->pbuf = btinfo; + + _rtw_memcpy(btinfo, buf, len); + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + return res; +} +#endif //CONFIG_BT_COEXIST + +//#ifdef CONFIG_C2H_PACKET_EN +u8 rtw_c2h_packet_wk_cmd(PADAPTER padapter, u8 *pbuf, u16 length) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 *extra_cmd_buf; + u8 res = _SUCCESS; + + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (pdrvextra_cmd_parm == NULL) { + rtw_mfree((u8*)ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + extra_cmd_buf = rtw_zmalloc(length); + if (extra_cmd_buf == NULL) { + rtw_mfree((u8 *)ph2c, sizeof(struct cmd_obj)); + rtw_mfree((u8 *)pdrvextra_cmd_parm, sizeof(struct drvextra_cmd_parm)); + res = _FAIL; + goto exit; + } + + _rtw_memcpy(extra_cmd_buf, pbuf, length); + pdrvextra_cmd_parm->ec_id = C2H_WK_CID; + pdrvextra_cmd_parm->type = 0; + pdrvextra_cmd_parm->size = length; + pdrvextra_cmd_parm->pbuf = extra_cmd_buf; + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + return res; +} + +static s32 rtw_mp_cmd_hdl(_adapter *padapter, u8 mp_cmd_id) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + int ret = H2C_SUCCESS; + u8 rfreg0; + + if (mp_cmd_id == MP_START) { + if (padapter->registrypriv.mp_mode == 0) { + rtw_hal_deinit(padapter); + padapter->registrypriv.mp_mode = 1; +#ifdef CONFIG_RF_POWER_TRIM + if (!IS_HARDWARE_TYPE_8814A(padapter) && !IS_HARDWARE_TYPE_8822B(padapter)) { + padapter->registrypriv.RegPwrTrimEnable = 1; + rtw_hal_read_chip_info(padapter); + } +#endif /*CONFIG_RF_POWER_TRIM*/ + rtw_hal_init(padapter); + } + + if (padapter->registrypriv.mp_mode == 0) { + ret = H2C_REJECTED; + goto exit; + } + + if (padapter->mppriv.mode == MP_OFF) { + if (mp_start_test(padapter) == _FAIL) { + ret = H2C_REJECTED; + goto exit; + } + padapter->mppriv.mode = MP_ON; + MPT_PwrCtlDM(padapter, 0); + } + padapter->mppriv.bmac_filter = _FALSE; +#ifdef CONFIG_RTL8723B +#ifdef CONFIG_USB_HCI + rtw_write32(padapter, 0x765, 0x0000); + rtw_write32(padapter, 0x948, 0x0280); +#else + rtw_write32(padapter, 0x765, 0x0000); + rtw_write32(padapter, 0x948, 0x0000); +#endif +#ifdef CONFIG_FOR_RTL8723BS_VQ0 + rtw_write32(padapter, 0x765, 0x0000); + rtw_write32(padapter, 0x948, 0x0280); +#endif + rtw_write8(padapter, 0x66, 0x27); /*Open BT uart Log*/ + rtw_write8(padapter, 0xc50, 0x20); /*for RX init Gain*/ +#endif + ODM_Write_DIG(&pHalData->odmpriv, 0x20); + +#ifdef CONFIG_RTL8188F + DBG_871X("Set reg 0x88c, 0x58, 0x00\n"); + rfreg0 = PHY_QueryRFReg(padapter, RF_PATH_A, 0x0, 0x1f); + PHY_SetBBReg(padapter, 0x88c, BIT21|BIT20, 0x3); + PHY_SetRFReg(padapter, RF_PATH_A, 0x58, BIT1, 0x1); + PHY_SetRFReg(padapter, RF_PATH_A, 0x0, 0xF001f, 0x2001f); + rtw_msleep_os(200); + PHY_SetRFReg(padapter, RF_PATH_A, 0x0, 0xF001f, 0x30000 | rfreg0); + PHY_SetRFReg(padapter, RF_PATH_A, 0x58, BIT1, 0x0); + PHY_SetBBReg(padapter, 0x88c, BIT21|BIT20, 0x0); + rtw_msleep_os(1000); +#endif + + } else if (mp_cmd_id == MP_STOP) { + if (padapter->registrypriv.mp_mode == 1) { + MPT_DeInitAdapter(padapter); + rtw_hal_deinit(padapter); + padapter->registrypriv.mp_mode = 0; + rtw_hal_init(padapter); + } + + if (padapter->mppriv.mode != MP_OFF) { + mp_stop_test(padapter); + padapter->mppriv.mode = MP_OFF; + } + + } else { + DBG_871X(FUNC_ADPT_FMT"invalid id:%d\n", FUNC_ADPT_ARG(padapter), mp_cmd_id); + ret = H2C_PARAMETERS_ERROR; + rtw_warn_on(1); + } + +exit: + return ret; +} + +u8 rtw_mp_cmd(_adapter *adapter, u8 mp_cmd_id, u8 flags) +{ + struct cmd_obj *cmdobj; + struct drvextra_cmd_parm *parm; + struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct submit_ctx sctx; + u8 res = _SUCCESS; + + parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (parm == NULL) { + res = _FAIL; + goto exit; + } + + parm->ec_id = MP_CMD_WK_CID; + parm->type = mp_cmd_id; + parm->size = 0; + parm->pbuf = NULL; + + if (flags & RTW_CMDF_DIRECTLY) { + /* no need to enqueue, do the cmd hdl directly and free cmd parameter */ + if (H2C_SUCCESS != rtw_mp_cmd_hdl(adapter, mp_cmd_id)) + res = _FAIL; + rtw_mfree((u8 *)parm, sizeof(*parm)); + } else { + /* need enqueue, prepare cmd_obj and enqueue */ + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj)); + if (cmdobj == NULL) { + res = _FAIL; + rtw_mfree((u8 *)parm, sizeof(*parm)); + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + if (flags & RTW_CMDF_WAIT_ACK) { + cmdobj->sctx = &sctx; + rtw_sctx_init(&sctx, 10 * 1000); + } + + res = rtw_enqueue_cmd(pcmdpriv, cmdobj); + + if (res == _SUCCESS && (flags & RTW_CMDF_WAIT_ACK)) { + rtw_sctx_wait(&sctx, __func__); + _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status == RTW_SCTX_SUBMITTED) + cmdobj->sctx = NULL; + _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status != RTW_SCTX_DONE_SUCCESS) + res = _FAIL; + } + } + +exit: + return res; +} + +#ifdef CONFIG_RTW_CUSTOMER_STR +static s32 rtw_customer_str_cmd_hdl(_adapter *adapter, u8 write, const u8 *cstr) +{ + int ret = H2C_SUCCESS; + + if (write) + ret = rtw_hal_h2c_customer_str_write(adapter, cstr); + else + ret = rtw_hal_h2c_customer_str_req(adapter); + + return ret == _SUCCESS ? H2C_SUCCESS : H2C_REJECTED; +} + +static u8 rtw_customer_str_cmd(_adapter *adapter, u8 write, const u8 *cstr) +{ + struct cmd_obj *cmdobj; + struct drvextra_cmd_parm *parm; + u8 *str = NULL; + struct cmd_priv *pcmdpriv = &adapter->cmdpriv; + struct submit_ctx sctx; + u8 res = _SUCCESS; + + parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (parm == NULL) { + res = _FAIL; + goto exit; + } + + if (write) { + str = rtw_zmalloc(RTW_CUSTOMER_STR_LEN); + if (str == NULL) { + rtw_mfree((u8 *)parm, sizeof(struct drvextra_cmd_parm)); + res = _FAIL; + goto exit; + } + } + + parm->ec_id = CUSTOMER_STR_WK_CID; + parm->type = write; + parm->size = write ? RTW_CUSTOMER_STR_LEN : 0; + parm->pbuf = write ? str : NULL; + + if (write) + _rtw_memcpy(str, cstr, RTW_CUSTOMER_STR_LEN); + + /* need enqueue, prepare cmd_obj and enqueue */ + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(*cmdobj)); + if (cmdobj == NULL) { + res = _FAIL; + rtw_mfree((u8 *)parm, sizeof(*parm)); + if (write) + rtw_mfree(str, RTW_CUSTOMER_STR_LEN); + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(cmdobj, parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + cmdobj->sctx = &sctx; + rtw_sctx_init(&sctx, 2 * 1000); + + res = rtw_enqueue_cmd(pcmdpriv, cmdobj); + + if (res == _SUCCESS) { + rtw_sctx_wait(&sctx, __func__); + _enter_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status == RTW_SCTX_SUBMITTED) + cmdobj->sctx = NULL; + _exit_critical_mutex(&pcmdpriv->sctx_mutex, NULL); + if (sctx.status != RTW_SCTX_DONE_SUCCESS) + res = _FAIL; + } + +exit: + return res; +} + +inline u8 rtw_customer_str_req_cmd(_adapter *adapter) +{ + return rtw_customer_str_cmd(adapter, 0, NULL); +} + +inline u8 rtw_customer_str_write_cmd(_adapter *adapter, const u8 *cstr) +{ + return rtw_customer_str_cmd(adapter, 1, cstr); +} +#endif /* CONFIG_RTW_CUSTOMER_STR */ + +//#else //CONFIG_C2H_PACKET_EN +/* dont call R/W in this function, beucase SDIO interrupt have claim host */ +/* or deadlock will happen and cause special-systemserver-died in android */ + +u8 rtw_c2h_wk_cmd(PADAPTER padapter, u8 *c2h_evt) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; + + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if (ph2c == NULL) { + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (pdrvextra_cmd_parm == NULL) { + rtw_mfree((u8*)ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = C2H_WK_CID; + pdrvextra_cmd_parm->type = 0; + pdrvextra_cmd_parm->size = c2h_evt?16:0; + pdrvextra_cmd_parm->pbuf = c2h_evt; + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + + return res; +} +//#endif //CONFIG_C2H_PACKET_EN + +u8 rtw_run_in_thread_cmd(PADAPTER padapter, void (*func)(void*), void* context) +{ + struct cmd_priv *pcmdpriv; + struct cmd_obj *ph2c; + struct RunInThread_param *parm; + s32 res = _SUCCESS; + +_func_enter_; + + pcmdpriv = &padapter->cmdpriv; + + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if (NULL == ph2c) { + res = _FAIL; + goto exit; + } + + parm = (struct RunInThread_param*)rtw_zmalloc(sizeof(struct RunInThread_param)); + if (NULL == parm) { + rtw_mfree((u8*)ph2c, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + parm->func = func; + parm->context = context; + init_h2fwcmd_w_parm_no_rsp(ph2c, parm, GEN_CMD_CODE(_RunInThreadCMD)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); +exit: + +_func_exit_; + + return res; +} + +s32 c2h_evt_hdl(_adapter *adapter, u8 *c2h_evt, c2h_id_filter filter) +{ + s32 ret = _FAIL; + u8 buf[16]; + + if (!c2h_evt) { + /* No c2h event in cmd_obj, read c2h event before handling*/ + if (rtw_hal_c2h_evt_read(adapter, buf) == _SUCCESS) { + c2h_evt = buf; + + if (filter && filter(c2h_evt) == _FALSE) + goto exit; + + ret = rtw_hal_c2h_handler(adapter, c2h_evt); + } + } else { + + if (filter && filter(c2h_evt) == _FALSE) + goto exit; + + ret = rtw_hal_c2h_handler(adapter, c2h_evt); + } +exit: + return ret; +} + +#ifdef CONFIG_C2H_WK +static void c2h_wk_callback(_workitem *work) +{ + struct evt_priv *evtpriv = container_of(work, struct evt_priv, c2h_wk); + _adapter *adapter = container_of(evtpriv, _adapter, evtpriv); + u8 *c2h_evt; + c2h_id_filter ccx_id_filter = rtw_hal_c2h_id_filter_ccx(adapter); + + evtpriv->c2h_wk_alive = _TRUE; + + while (!rtw_cbuf_empty(evtpriv->c2h_queue)) { + if ((c2h_evt = (u8 *)rtw_cbuf_pop(evtpriv->c2h_queue)) != NULL) { + /* This C2H event is read, clear it */ + c2h_evt_clear(adapter); + } else if ((c2h_evt = (u8 *)rtw_malloc(16)) != NULL) { + /* This C2H event is not read, read & clear now */ + if (rtw_hal_c2h_evt_read(adapter, c2h_evt) != _SUCCESS) { + rtw_mfree(c2h_evt, 16); + continue; + } + } else { + rtw_warn_on(1); + continue; + } + + /* Special pointer to trigger c2h_evt_clear only */ + if ((void *)c2h_evt == (void *)evtpriv) + continue; + + if (!rtw_hal_c2h_valid(adapter, c2h_evt)) { + rtw_mfree(c2h_evt, 16); + continue; + } + + if (ccx_id_filter(c2h_evt) == _TRUE) { + /* Handle CCX report here */ + rtw_hal_c2h_handler(adapter, c2h_evt); + rtw_mfree(c2h_evt, 16); + } else { + /* Enqueue into cmd_thread for others */ + rtw_c2h_wk_cmd(adapter, c2h_evt); + } + } + + evtpriv->c2h_wk_alive = _FALSE; +} +#endif + +u8 session_tracker_cmd(_adapter *adapter, u8 cmd, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port) +{ + struct cmd_priv *cmdpriv = &adapter->cmdpriv; + struct cmd_obj *cmdobj; + struct drvextra_cmd_parm *cmd_parm; + struct st_cmd_parm *st_parm; + u8 res = _SUCCESS; + + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmdobj == NULL) { + res = _FAIL; + goto exit; + } + + cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (cmd_parm == NULL) { + rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + st_parm = (struct st_cmd_parm *)rtw_zmalloc(sizeof(struct st_cmd_parm)); + if (st_parm == NULL) { + rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj)); + rtw_mfree((u8 *)cmd_parm, sizeof(struct drvextra_cmd_parm)); + res = _FAIL; + goto exit; + } + + st_parm->cmd = cmd; + st_parm->sta = sta; + if (cmd != ST_CMD_CHK) { + _rtw_memcpy(&st_parm->local_naddr, local_naddr, 4); + _rtw_memcpy(&st_parm->local_port, local_port, 2); + _rtw_memcpy(&st_parm->remote_naddr, remote_naddr, 4); + _rtw_memcpy(&st_parm->remote_port, remote_port, 2); + } + + cmd_parm->ec_id = SESSION_TRACKER_WK_CID; + cmd_parm->type = 0; + cmd_parm->size = sizeof(struct st_cmd_parm); + cmd_parm->pbuf = (u8 *)st_parm; + init_h2fwcmd_w_parm_no_rsp(cmdobj, cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + cmdobj->no_io = 1; + + res = rtw_enqueue_cmd(cmdpriv, cmdobj); + +exit: + return res; +} + +inline u8 session_tracker_chk_cmd(_adapter *adapter, struct sta_info *sta) +{ + return session_tracker_cmd(adapter, ST_CMD_CHK, sta, NULL, NULL, NULL, NULL); +} + +inline u8 session_tracker_add_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port) +{ + return session_tracker_cmd(adapter, ST_CMD_ADD, sta, local_naddr, local_port, remote_naddr, remote_port); +} + +inline u8 session_tracker_del_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port) +{ + return session_tracker_cmd(adapter, ST_CMD_DEL, sta, local_naddr, local_port, remote_naddr, remote_port); +} + +void session_tracker_chk_for_sta(_adapter *adapter, struct sta_info *sta) +{ + struct st_ctl_t *st_ctl = &sta->st_ctl; + int i; + _irqL irqL; + _list *plist, *phead, *pnext; + _list dlist; + struct session_tracker *st = NULL; + u8 op_wfd_mode = MIRACAST_DISABLED; + + if (DBG_SESSION_TRACKER) + DBG_871X(FUNC_ADPT_FMT" sta:%p\n", FUNC_ADPT_ARG(adapter), sta); + + if (!(sta->state & _FW_LINKED)) + goto exit; + + for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++) { + if (st_ctl->reg[i].s_proto != 0) + break; + } + if (i >= SESSION_TRACKER_REG_ID_NUM) + goto chk_sta; + + _rtw_init_listhead(&dlist); + + _enter_critical_bh(&st_ctl->tracker_q.lock, &irqL); + + phead = &st_ctl->tracker_q.queue; + plist = get_next(phead); + pnext = get_next(plist); + while (rtw_end_of_queue_search(phead, plist) == _FALSE) { + st = LIST_CONTAINOR(plist, struct session_tracker, list); + plist = pnext; + pnext = get_next(pnext); + + if (st->status != ST_STATUS_ESTABLISH + && rtw_get_passing_time_ms(st->set_time) > ST_EXPIRE_MS + ) { + rtw_list_delete(&st->list); + rtw_list_insert_tail(&st->list, &dlist); + } + + /* TODO: check OS for status update */ + if (st->status == ST_STATUS_CHECK) + st->status = ST_STATUS_ESTABLISH; + + if (st->status != ST_STATUS_ESTABLISH) + continue; + + #ifdef CONFIG_WFD + if (0) + DBG_871X(FUNC_ADPT_FMT" local:%u, remote:%u, rtsp:%u, %u, %u\n", FUNC_ADPT_ARG(adapter) + , ntohs(st->local_port), ntohs(st->remote_port), adapter->wfd_info.rtsp_ctrlport, adapter->wfd_info.tdls_rtsp_ctrlport + , adapter->wfd_info.peer_rtsp_ctrlport); + if (ntohs(st->local_port) == adapter->wfd_info.rtsp_ctrlport) + op_wfd_mode |= MIRACAST_SINK; + if (ntohs(st->local_port) == adapter->wfd_info.tdls_rtsp_ctrlport) + op_wfd_mode |= MIRACAST_SINK; + if (ntohs(st->remote_port) == adapter->wfd_info.peer_rtsp_ctrlport) + op_wfd_mode |= MIRACAST_SOURCE; + #endif + } + + _exit_critical_bh(&st_ctl->tracker_q.lock, &irqL); + + plist = get_next(&dlist); + while (rtw_end_of_queue_search(&dlist, plist) == _FALSE) { + st = LIST_CONTAINOR(plist, struct session_tracker, list); + plist = get_next(plist); + rtw_mfree((u8 *)st, sizeof(struct session_tracker)); + } + +chk_sta: + if (STA_OP_WFD_MODE(sta) != op_wfd_mode) { + STA_SET_OP_WFD_MODE(sta, op_wfd_mode); + rtw_sta_media_status_rpt_cmd(adapter, sta, 1); + } + +exit: + return; +} + +void session_tracker_chk_for_adapter(_adapter *adapter) +{ + struct sta_priv *stapriv = &adapter->stapriv; + struct sta_info *sta; + int i; + _irqL irqL; + _list *plist, *phead; + u8 op_wfd_mode = MIRACAST_DISABLED; + + _enter_critical_bh(&stapriv->sta_hash_lock, &irqL); + + for (i = 0; i < NUM_STA; i++) { + phead = &(stapriv->sta_hash[i]); + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + sta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + plist = get_next(plist); + + session_tracker_chk_for_sta(adapter, sta); + + op_wfd_mode |= STA_OP_WFD_MODE(sta); + } + } + + _exit_critical_bh(&stapriv->sta_hash_lock, &irqL); + +#ifdef CONFIG_WFD + adapter->wfd_info.op_wfd_mode = MIRACAST_MODE_REVERSE(op_wfd_mode); +#endif +} + +void session_tracker_cmd_hdl(_adapter *adapter, struct st_cmd_parm *parm) +{ + u8 cmd = parm->cmd; + struct sta_info *sta = parm->sta; + + if (cmd == ST_CMD_CHK) { + if (sta) + session_tracker_chk_for_sta(adapter, sta); + else + session_tracker_chk_for_adapter(adapter); + + goto exit; + + } else if (cmd == ST_CMD_ADD || cmd == ST_CMD_DEL) { + struct st_ctl_t *st_ctl; + u32 local_naddr = parm->local_naddr; + u16 local_port = parm->local_port; + u32 remote_naddr = parm->remote_naddr; + u16 remote_port = parm->remote_port; + struct session_tracker *st = NULL; + _irqL irqL; + _list *plist, *phead; + u8 free_st = 0; + u8 alloc_st = 0; + + if (DBG_SESSION_TRACKER) + DBG_871X(FUNC_ADPT_FMT" cmd:%u, sta:%p, local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT"\n" + , FUNC_ADPT_ARG(adapter), cmd, sta + , IP_ARG(&local_naddr), PORT_ARG(&local_port) + , IP_ARG(&remote_naddr), PORT_ARG(&remote_port) + ); + + if (!(sta->state & _FW_LINKED)) + goto exit; + + st_ctl = &sta->st_ctl; + + _enter_critical_bh(&st_ctl->tracker_q.lock, &irqL); + + phead = &st_ctl->tracker_q.queue; + plist = get_next(phead); + while (rtw_end_of_queue_search(phead, plist) == _FALSE) { + st = LIST_CONTAINOR(plist, struct session_tracker, list); + + if (st->local_naddr == local_naddr + && st->local_port == local_port + && st->remote_naddr == remote_naddr + && st->remote_port == remote_port) + break; + + plist = get_next(plist); + } + + if (rtw_end_of_queue_search(phead, plist) == _TRUE) + st = NULL; + + switch (cmd) { + case ST_CMD_DEL: + if (st) { + rtw_list_delete(plist); + free_st = 1; + } + goto unlock; + case ST_CMD_ADD: + if (!st) + alloc_st = 1; + } + +unlock: + _exit_critical_bh(&st_ctl->tracker_q.lock, &irqL); + + if (free_st) { + rtw_mfree((u8 *)st, sizeof(struct session_tracker)); + goto exit; + } + + if (alloc_st) { + st = (struct session_tracker *)rtw_zmalloc(sizeof(struct session_tracker)); + if (!st) + goto exit; + + st->local_naddr = local_naddr; + st->local_port = local_port; + st->remote_naddr = remote_naddr; + st->remote_port = remote_port; + st->set_time = rtw_get_current_time(); + st->status = ST_STATUS_CHECK; + + _enter_critical_bh(&st_ctl->tracker_q.lock, &irqL); + rtw_list_insert_tail(&st->list, phead); + _exit_critical_bh(&st_ctl->tracker_q.lock, &irqL); + } + } + +exit: + return; +} + +u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf) +{ + int ret = H2C_SUCCESS; + struct drvextra_cmd_parm *pdrvextra_cmd; + + if(!pbuf) + return H2C_PARAMETERS_ERROR; + + pdrvextra_cmd = (struct drvextra_cmd_parm*)pbuf; + + switch (pdrvextra_cmd->ec_id) { + case STA_MSTATUS_RPT_WK_CID: + rtw_sta_media_status_rpt_cmd_hdl(padapter, (struct sta_media_status_rpt_cmd_parm *)pdrvextra_cmd->pbuf); + break; + + case DYNAMIC_CHK_WK_CID:/*only primary padapter go to this cmd, but execute dynamic_chk_wk_hdl() for two interfaces */ +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->pbuddy_adapter) + dynamic_chk_wk_hdl(padapter->pbuddy_adapter); +#endif + dynamic_chk_wk_hdl(padapter); + break; + case POWER_SAVING_CTRL_WK_CID: + power_saving_wk_hdl(padapter); + break; +#ifdef CONFIG_LPS + case LPS_CTRL_WK_CID: + lps_ctrl_wk_hdl(padapter, (u8)pdrvextra_cmd->type); + break; + case DM_IN_LPS_WK_CID: + rtw_dm_in_lps_hdl(padapter); + break; + case LPS_CHANGE_DTIM_CID: + rtw_lps_change_dtim_hdl(padapter, (u8)pdrvextra_cmd->type); + break; +#endif +#if (RATE_ADAPTIVE_SUPPORT==1) + case RTP_TIMER_CFG_WK_CID: + rpt_timer_setting_wk_hdl(padapter, pdrvextra_cmd->type); + break; +#endif +#ifdef CONFIG_ANTENNA_DIVERSITY + case ANT_SELECT_WK_CID: + antenna_select_wk_hdl(padapter, pdrvextra_cmd->type); + break; +#endif +#ifdef CONFIG_P2P_PS + case P2P_PS_WK_CID: + p2p_ps_wk_hdl(padapter, pdrvextra_cmd->type); + break; +#endif +#ifdef CONFIG_P2P + case P2P_PROTO_WK_CID: + /* + * Commented by Albert 2011/07/01 + * I used the type_size as the type command + */ + p2p_protocol_wk_hdl(padapter, pdrvextra_cmd->type); + break; +#endif +#ifdef CONFIG_AP_MODE + case CHECK_HIQ_WK_CID: + rtw_chk_hi_queue_hdl(padapter); + break; +#endif +#ifdef CONFIG_INTEL_WIDI + case INTEl_WIDI_WK_CID: + intel_widi_wk_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf); + break; +#endif + /* add for CONFIG_IEEE80211W, none 11w can use it */ + case RESET_SECURITYPRIV: + reset_securitypriv_hdl(padapter); + break; + case FREE_ASSOC_RESOURCES: + free_assoc_resources_hdl(padapter); + break; + case C2H_WK_CID: +#ifdef CONFIG_C2H_PACKET_EN + rtw_hal_set_hwreg_with_buf(padapter, HW_VAR_C2H_HANDLE, pdrvextra_cmd->pbuf, pdrvextra_cmd->size); +#else + c2h_evt_hdl(padapter, pdrvextra_cmd->pbuf, NULL); +#endif + break; +#ifdef CONFIG_BEAMFORMING + case BEAMFORMING_WK_CID: + beamforming_wk_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf); + break; +#endif + case DM_RA_MSK_WK_CID: + rtw_dm_ra_mask_hdl(padapter, (struct sta_info *)pdrvextra_cmd->pbuf); + break; +#ifdef CONFIG_BT_COEXIST + case BTINFO_WK_CID: + rtw_btinfo_hdl(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->size); + break; +#endif +#ifdef CONFIG_DFS_MASTER + case DFS_MASTER_WK_CID: + rtw_dfs_master_hdl(padapter); + break; +#endif + case SESSION_TRACKER_WK_CID: + session_tracker_cmd_hdl(padapter, (struct st_cmd_parm *)pdrvextra_cmd->pbuf); + break; + + case EN_HW_UPDATE_TSF_WK_CID: + rtw_hal_set_hwreg(padapter, HW_VAR_EN_HW_UPDATE_TSF, NULL); + break; + + case MP_CMD_WK_CID: + ret = rtw_mp_cmd_hdl(padapter, pdrvextra_cmd->type); + break; +#ifdef CONFIG_RTW_CUSTOMER_STR + case CUSTOMER_STR_WK_CID: + ret = rtw_customer_str_cmd_hdl(padapter, pdrvextra_cmd->type, pdrvextra_cmd->pbuf); + break; +#endif + + default: + break; + } + + if (pdrvextra_cmd->pbuf && pdrvextra_cmd->size>0) + { + rtw_mfree(pdrvextra_cmd->pbuf, pdrvextra_cmd->size); + } + + return ret; +} + +void rtw_survey_cmd_callback(_adapter* padapter , struct cmd_obj *pcmd) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + +_func_enter_; + + if(pcmd->res == H2C_DROPPED) + { + //TODO: cancel timer and do timeout handler directly... + //need to make timeout handlerOS independent + mlme_set_scan_to_timer(pmlmepriv, 1); + } + else if (pcmd->res != H2C_SUCCESS) { + mlme_set_scan_to_timer(pmlmepriv, 1); + RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\n ********Error: MgntActrtw_set_802_11_bssid_LIST_SCAN Fail ************\n\n.")); + } + + // free cmd + rtw_free_cmd_obj(pcmd); + +_func_exit_; +} +void rtw_disassoc_cmd_callback(_adapter* padapter, struct cmd_obj *pcmd) +{ + _irqL irqL; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + +_func_enter_; + + if (pcmd->res != H2C_SUCCESS) + { + _enter_critical_bh(&pmlmepriv->lock, &irqL); + set_fwstate(pmlmepriv, _FW_LINKED); + _exit_critical_bh(&pmlmepriv->lock, &irqL); + + RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\n ***Error: disconnect_cmd_callback Fail ***\n.")); + + goto exit; + } +#ifdef CONFIG_BR_EXT + else //clear bridge database + nat25_db_cleanup(padapter); +#endif //CONFIG_BR_EXT + + // free cmd + rtw_free_cmd_obj(pcmd); + +exit: + +_func_exit_; +} + + +void rtw_getmacreg_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd) +{ + +_func_enter_; + + rtw_free_cmd_obj(pcmd); + +_func_exit_; +} + +void rtw_joinbss_cmd_callback(_adapter* padapter, struct cmd_obj *pcmd) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + +_func_enter_; + + if(pcmd->res == H2C_DROPPED) + { + //TODO: cancel timer and do timeout handler directly... + //need to make timeout handlerOS independent + _set_timer(&pmlmepriv->assoc_timer, 1); + } + else if(pcmd->res != H2C_SUCCESS) + { + _set_timer(&pmlmepriv->assoc_timer, 1); + } + + rtw_free_cmd_obj(pcmd); + +_func_exit_; +} + +void rtw_create_ibss_post_hdl(_adapter *padapter, int status) +{ + _irqL irqL; + u8 timer_cancelled; + struct sta_info *psta = NULL; + struct wlan_network *pwlan = NULL; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + WLAN_BSSID_EX *pdev_network = &padapter->registrypriv.dev_network; + struct wlan_network *mlme_cur_network = &(pmlmepriv->cur_network); + + if (status != H2C_SUCCESS) + _set_timer(&pmlmepriv->assoc_timer, 1); + + _cancel_timer(&pmlmepriv->assoc_timer, &timer_cancelled); + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + { + _irqL irqL; + + pwlan = _rtw_alloc_network(pmlmepriv); + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + if (pwlan == NULL) { + pwlan = rtw_get_oldest_wlan_network(&pmlmepriv->scanned_queue); + if (pwlan == NULL) { + RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("Error: can't get pwlan in rtw_joinbss_event_callback\n")); + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + goto createbss_cmd_fail; + } + pwlan->last_scanned = rtw_get_current_time(); + } else { + rtw_list_insert_tail(&(pwlan->list), &pmlmepriv->scanned_queue.queue); + } + + pdev_network->Length = get_WLAN_BSSID_EX_sz(pdev_network); + _rtw_memcpy(&(pwlan->network), pdev_network, pdev_network->Length); + //pwlan->fixed = _TRUE; + + /* copy pdev_network information to pmlmepriv->cur_network */ + _rtw_memcpy(&mlme_cur_network->network, pdev_network, (get_WLAN_BSSID_EX_sz(pdev_network))); + + #if 0 + /* reset DSConfig */ + mlme_cur_network->network.Configuration.DSConfig = (u32)rtw_ch2freq(pdev_network->Configuration.DSConfig); + #endif + + _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + /* we will set _FW_LINKED when there is one more sat to join us (rtw_stassoc_event_callback) */ + } + +createbss_cmd_fail: + _exit_critical_bh(&pmlmepriv->lock, &irqL); +exit: + return; +} + + + +void rtw_setstaKey_cmdrsp_callback(_adapter* padapter , struct cmd_obj *pcmd) +{ + + struct sta_priv * pstapriv = &padapter->stapriv; + struct set_stakey_rsp* psetstakey_rsp = (struct set_stakey_rsp*) (pcmd->rsp); + struct sta_info* psta = rtw_get_stainfo(pstapriv, psetstakey_rsp->addr); + +_func_enter_; + + if(psta==NULL) + { + RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\nERROR: rtw_setstaKey_cmdrsp_callback => can't get sta_info \n\n")); + goto exit; + } + + //psta->aid = psta->mac_id = psetstakey_rsp->keyid; //CAM_ID(CAM_ENTRY) + +exit: + + rtw_free_cmd_obj(pcmd); + +_func_exit_; + +} +void rtw_setassocsta_cmdrsp_callback(_adapter* padapter, struct cmd_obj *pcmd) +{ + _irqL irqL; + struct sta_priv * pstapriv = &padapter->stapriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct set_assocsta_parm* passocsta_parm = (struct set_assocsta_parm*)(pcmd->parmbuf); + struct set_assocsta_rsp* passocsta_rsp = (struct set_assocsta_rsp*) (pcmd->rsp); + struct sta_info* psta = rtw_get_stainfo(pstapriv, passocsta_parm->addr); + +_func_enter_; + + if(psta==NULL) + { + RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\nERROR: setassocsta_cmdrsp_callbac => can't get sta_info \n\n")); + goto exit; + } + + psta->aid = psta->mac_id = passocsta_rsp->cam_id; + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) && (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE)) + _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); + + set_fwstate(pmlmepriv, _FW_LINKED); + _exit_critical_bh(&pmlmepriv->lock, &irqL); + +exit: + rtw_free_cmd_obj(pcmd); + +_func_exit_; +} + +void rtw_getrttbl_cmd_cmdrsp_callback(_adapter* padapter, struct cmd_obj *pcmd); +void rtw_getrttbl_cmd_cmdrsp_callback(_adapter* padapter, struct cmd_obj *pcmd) +{ +_func_enter_; + + rtw_free_cmd_obj(pcmd); +#ifdef CONFIG_MP_INCLUDED + if (padapter->registrypriv.mp_mode == 1) + padapter->mppriv.workparam.bcompleted=_TRUE; +#endif + +_func_exit_; + +} + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_debug.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_debug.c new file mode 100644 index 000000000..b7d8b18fb --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_debug.c @@ -0,0 +1,3842 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_DEBUG_C_ + +#include +#include + +u32 GlobalDebugLevel = _drv_err_; + +#ifdef CONFIG_DEBUG_RTL871X + + u64 GlobalDebugComponents = \ + _module_rtl871x_xmit_c_ | + _module_xmit_osdep_c_ | + _module_rtl871x_recv_c_ | + _module_recv_osdep_c_ | + _module_rtl871x_mlme_c_ | + _module_mlme_osdep_c_ | + _module_rtl871x_sta_mgt_c_ | + _module_rtl871x_cmd_c_ | + _module_cmd_osdep_c_ | + _module_rtl871x_io_c_ | + _module_io_osdep_c_ | + _module_os_intfs_c_| + _module_rtl871x_security_c_| + _module_rtl871x_eeprom_c_| + _module_hal_init_c_| + _module_hci_hal_init_c_| + _module_rtl871x_ioctl_c_| + _module_rtl871x_ioctl_set_c_| + _module_rtl871x_ioctl_query_c_| + _module_rtl871x_pwrctrl_c_| + _module_hci_intfs_c_| + _module_hci_ops_c_| + _module_hci_ops_os_c_| + _module_rtl871x_ioctl_os_c| + _module_rtl8712_cmd_c_| + _module_hal_xmit_c_| + _module_rtl8712_recv_c_ | + _module_mp_ | + _module_efuse_; + +#endif /* CONFIG_DEBUG_RTL871X */ + +#include + +#ifdef CONFIG_TDLS +#define TDLS_DBG_INFO_SPACE_BTWN_ITEM_AND_VALUE 41 +#endif + +void dump_drv_version(void *sel) +{ + DBG_871X_SEL_NL(sel, "%s %s\n", DRV_NAME, DRIVERVERSION); + //DBG_871X_SEL_NL(sel, "build time: %s %s\n", __DATE__, __TIME__); +} + +void dump_drv_cfg(void *sel) +{ + char *kernel_version = utsname()->release; + + DBG_871X_SEL_NL(sel, "\nKernel Version: %s\n", kernel_version); + DBG_871X_SEL_NL(sel, "Driver Version: %s\n", DRIVERVERSION); + DBG_871X_SEL_NL(sel, "------------------------------------------------\n"); +#ifdef CONFIG_IOCTL_CFG80211 + DBG_871X_SEL_NL(sel, "CFG80211\n"); + #ifdef RTW_USE_CFG80211_STA_EVENT + DBG_871X_SEL_NL(sel, "RTW_USE_CFG80211_STA_EVENT\n"); + #endif +#else + DBG_871X_SEL_NL(sel, "WEXT\n"); +#endif + + DBG_871X_SEL_NL(sel, "DBG:%d\n", DBG); +#ifdef CONFIG_DEBUG + DBG_871X_SEL_NL(sel, "CONFIG_DEBUG\n"); +#endif + +#ifdef CONFIG_CONCURRENT_MODE + DBG_871X_SEL_NL(sel, "CONFIG_CONCURRENT_MODE\n"); +#endif + +#ifdef CONFIG_POWER_SAVING + DBG_871X_SEL_NL(sel, "CONFIG_POWER_SAVING\n"); +#endif + +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + DBG_871X_SEL_NL(sel, "LOAD_PHY_PARA_FROM_FILE - REALTEK_CONFIG_PATH=%s\n", REALTEK_CONFIG_PATH); + #if defined(CONFIG_MULTIDRV) || defined(REALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER) + DBG_871X_SEL_NL(sel, "LOAD_PHY_PARA_FROM_FILE - REALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER\n"); + #endif + #ifdef CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY + DBG_871X_SEL_NL(sel, "CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY\n"); + #endif + #ifdef CONFIG_CALIBRATE_TX_POWER_TO_MAX + DBG_871X_SEL_NL(sel, "CONFIG_CALIBRATE_TX_POWER_TO_MAX\n"); + #endif +#endif + +#ifdef CONFIG_DISABLE_ODM + DBG_871X_SEL_NL(sel, "CONFIG_DISABLE_ODM\n"); +#endif + +#ifdef CONFIG_MINIMAL_MEMORY_USAGE + DBG_871X_SEL_NL(sel, "CONFIG_MINIMAL_MEMORY_USAGE\n"); +#endif + + DBG_871X_SEL_NL(sel, "CONFIG_RTW_ADAPTIVITY_EN = %d\n", CONFIG_RTW_ADAPTIVITY_EN); +#if (CONFIG_RTW_ADAPTIVITY_EN) + DBG_871X_SEL_NL(sel, "ADAPTIVITY_MODE = %s\n", (CONFIG_RTW_ADAPTIVITY_MODE) ? "carrier_sense" : "normal"); +#endif + +#ifdef CONFIG_TDLS + DBG_871X_SEL_NL(sel, "CONFIG_TDLS\n"); +#endif + +#ifdef CONFIG_USB_HCI + #ifdef CONFIG_SUPPORT_USB_INT + DBG_871X_SEL_NL(sel, "CONFIG_SUPPORT_USB_INT\n"); + #endif + #ifdef CONFIG_USB_INTERRUPT_IN_PIPE + DBG_871X_SEL_NL(sel, "CONFIG_USB_INTERRUPT_IN_PIPE\n"); + #endif + #ifdef CONFIG_USB_TX_AGGREGATION + DBG_871X_SEL_NL(sel, "CONFIG_USB_TX_AGGREGATION\n"); + #endif + #ifdef CONFIG_USB_RX_AGGREGATION + DBG_871X_SEL_NL(sel, "CONFIG_USB_RX_AGGREGATION\n"); + #endif + #ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX + DBG_871X_SEL_NL(sel, "CONFIG_USE_USB_BUFFER_ALLOC_TX\n"); + #endif + #ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX + DBG_871X_SEL_NL(sel, "CONFIG_USE_USB_BUFFER_ALLOC_RX\n"); + #endif + #ifdef CONFIG_PREALLOC_RECV_SKB + DBG_871X_SEL_NL(sel, "CONFIG_PREALLOC_RECV_SKB\n"); + #endif + #ifdef CONFIG_FIX_NR_BULKIN_BUFFER + DBG_871X_SEL_NL(sel, "CONFIG_FIX_NR_BULKIN_BUFFER\n"); + #endif +#endif /*CONFIG_USB_HCI*/ + +#ifdef CONFIG_SDIO_HCI + #ifdef CONFIG_TX_AGGREGATION + DBG_871X_SEL_NL(sel, "CONFIG_TX_AGGREGATION\n"); + #endif + #ifdef CONFIG_RX_AGGREGATION + DBG_871X_SEL_NL(sel, "CONFIG_RX_AGGREGATION\n"); + #endif +#endif /*CONFIG_SDIO_HCI*/ + +#ifdef CONFIG_PCI_HCI +#endif + + DBG_871X_SEL_NL(sel, "MAX_XMITBUF_SZ = %d\n", MAX_XMITBUF_SZ); + DBG_871X_SEL_NL(sel, "MAX_RECVBUF_SZ = %d\n", MAX_RECVBUF_SZ); + +} + +void dump_log_level(void *sel) +{ + DBG_871X_SEL_NL(sel, "log_level:%d\n", GlobalDebugLevel); +} + +#ifdef CONFIG_SDIO_HCI +void sd_f0_reg_dump(void *sel, _adapter *adapter) +{ + int i; + + for(i=0x0;i<=0xff;i++) + { + if(i%16==0) + DBG_871X_SEL_NL(sel, "0x%02x ",i); + + DBG_871X_SEL(sel, "%02x ", rtw_sd_f0_read8(adapter, i)); + + if(i%16==15) + DBG_871X_SEL(sel, "\n"); + else if(i%8==7) + DBG_871X_SEL(sel, "\t"); + } +} + +void sdio_local_reg_dump(void *sel, _adapter *adapter) +{ + int i, j = 1; + + for (i = 0x0; i < 0x100; i += 4) { + if (j % 4 == 1) + DBG_871X_SEL_NL(sel, "0x%02x", i); + DBG_871X_SEL(sel, " 0x%08x ", rtw_read32(adapter, (0x1025 << 16) | i)); + if ((j++) % 4 == 0) + DBG_871X_SEL(sel, "\n"); + } +} +#endif /* CONFIG_SDIO_HCI */ + +void mac_reg_dump(void *sel, _adapter *adapter) +{ + int i, j = 1; + + DBG_871X_SEL_NL(sel, "======= MAC REG =======\n"); + + for(i=0x0;i<0x800;i+=4) + { + if(j%4==1) + DBG_871X_SEL_NL(sel, "0x%03x",i); + DBG_871X_SEL(sel, " 0x%08x ", rtw_read32(adapter,i)); + if((j++)%4 == 0) + DBG_871X_SEL(sel, "\n"); + } + +#ifdef CONFIG_RTL8814A + { + for(i=0x1000;i<0x1650;i+=4) + { + if(j%4==1) + DBG_871X_SEL_NL(sel, "0x%03x",i); + DBG_871X_SEL(sel, " 0x%08x ", rtw_read32(adapter,i)); + if((j++)%4 == 0) + DBG_871X_SEL(sel, "\n"); + } + } +#endif /* CONFIG_RTL8814A */ +} + +void bb_reg_dump(void *sel, _adapter *adapter) +{ + int i, j = 1; + + DBG_871X_SEL_NL(sel, "======= BB REG =======\n"); + for(i=0x800;i<0x1000;i+=4) + { + if(j%4==1) + DBG_871X_SEL_NL(sel, "0x%03x",i); + DBG_871X_SEL(sel, " 0x%08x ", rtw_read32(adapter,i)); + if((j++)%4 == 0) + DBG_871X_SEL(sel, "\n"); + } +} + +void rf_reg_dump(void *sel, _adapter *adapter) +{ + int i, j = 1, path; + u32 value; + u8 rf_type = 0; + u8 path_nums = 0; + + rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + if((RF_1T2R == rf_type) ||(RF_1T1R ==rf_type )) + path_nums = 1; + else + path_nums = 2; + + DBG_871X_SEL_NL(sel, "======= RF REG =======\n"); + + for (path=0;pathrecvpriv); + if( precvpriv->sink_udpport > 0) + { + if(*((u16*)((pkt->data)+0x24)) == cpu_to_be16(precvpriv->sink_udpport)) + { + precvpriv->pre_rtp_rxseq= precvpriv->cur_rtp_rxseq; + precvpriv->cur_rtp_rxseq = be16_to_cpu(*((u16*)((pkt->data)+0x2C))); + if( precvpriv->pre_rtp_rxseq+1 != precvpriv->cur_rtp_rxseq) + DBG_871X("%s : RTP Seq num from %d to %d\n",__FUNCTION__,precvpriv->pre_rtp_rxseq,precvpriv->cur_rtp_rxseq); + } + } +} + +void sta_rx_reorder_ctl_dump(void *sel, struct sta_info *sta) +{ + struct recv_reorder_ctrl *reorder_ctl; + int i; + + for (i = 0; i < 16; i++) { + reorder_ctl = &sta->recvreorder_ctrl[i]; + if (reorder_ctl->ampdu_size != RX_AMPDU_SIZE_INVALID || reorder_ctl->indicate_seq != 0xFFFF) { + DBG_871X_SEL_NL(sel, "tid=%d, enable=%d, ampdu_size=%u, indicate_seq=%u\n" + , i, reorder_ctl->enable, reorder_ctl->ampdu_size, reorder_ctl->indicate_seq + ); + } + } +} + +void dump_adapters_status(void *sel, struct dvobj_priv *dvobj) +{ + struct rf_ctl_t *rfctl = dvobj_to_rfctl(dvobj); + int i; + _adapter *iface; + u8 u_ch, u_bw, u_offset; + + DBG_871X_SEL_NL(sel, "%-2s %-8s %-17s %-4s %-7s %s\n" + , "id", "ifname", "macaddr", "port", "ch", "status"); + + DBG_871X_SEL_NL(sel, "------------------------------------------\n"); + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (iface) { + DBG_871X_SEL_NL(sel, "%2d %-8s "MAC_FMT" %4hhu %3u,%u,%u "MLME_STATE_FMT" %s%s\n" + , i, ADPT_ARG(iface) + , MAC_ARG(adapter_mac_addr(iface)) + , get_iface_type(iface) + , iface->mlmeextpriv.cur_channel + , iface->mlmeextpriv.cur_bwmode + , iface->mlmeextpriv.cur_ch_offset + , MLME_STATE_ARG(iface) + , rtw_is_surprise_removed(iface)?" SR":"" + , rtw_is_drv_stopped(iface)?" DS":"" + ); + } + } + + DBG_871X_SEL_NL(sel, "------------------------------------------\n"); + + rtw_get_ch_setting_union(dvobj->padapters[IFACE_ID0], &u_ch, &u_bw, &u_offset); + DBG_871X_SEL_NL(sel, "%34s %3u,%u,%u\n" + , "union:" + , u_ch, u_bw, u_offset + ); + + DBG_871X_SEL_NL(sel, "%34s %3u,%u,%u\n" + , "oper:" + , dvobj->oper_channel + , dvobj->oper_bwmode + , dvobj->oper_ch_offset + ); + + #ifdef CONFIG_DFS_MASTER + if (rfctl->radar_detect_ch != 0) { + DBG_871X_SEL_NL(sel, "%34s %3u,%u,%u" + , "radar_detect:" + , rfctl->radar_detect_ch + , rfctl->radar_detect_bw + , rfctl->radar_detect_offset + ); + + if (IS_UNDER_CAC(rfctl)) + DBG_871X_SEL(sel, ", cac:%d\n", rtw_systime_to_ms(rfctl->cac_end_time - rtw_get_current_time())); + else + DBG_871X_SEL(sel, "\n"); + } + #endif +} + +#define SEC_CAM_ENT_ID_TITLE_FMT "%-2s" +#define SEC_CAM_ENT_ID_TITLE_ARG "id" +#define SEC_CAM_ENT_ID_VALUE_FMT "%2u" +#define SEC_CAM_ENT_ID_VALUE_ARG(id) (id) + +#define SEC_CAM_ENT_TITLE_FMT "%-6s %-17s %-32s %-3s %-7s %-2s %-2s %-5s" +#define SEC_CAM_ENT_TITLE_ARG "ctrl", "addr", "key", "kid", "type", "MK", "GK", "valid" +#define SEC_CAM_ENT_VALUE_FMT "0x%04x "MAC_FMT" "KEY_FMT" %3u %-7s %2u %2u %5u" +#define SEC_CAM_ENT_VALUE_ARG(ent) \ + (ent)->ctrl \ + , MAC_ARG((ent)->mac) \ + , KEY_ARG((ent)->key) \ + , ((ent)->ctrl) & 0x03 \ + , security_type_str((((ent)->ctrl) >> 2) & 0x07) \ + , (((ent)->ctrl) >> 5) & 0x01 \ + , (((ent)->ctrl) >> 6) & 0x01 \ + , (((ent)->ctrl) >> 15) & 0x01 + +void dump_sec_cam_ent(void *sel, struct sec_cam_ent *ent, int id) +{ + if (id >= 0) { + DBG_871X_SEL_NL(sel, SEC_CAM_ENT_ID_VALUE_FMT " " SEC_CAM_ENT_VALUE_FMT"\n" + , SEC_CAM_ENT_ID_VALUE_ARG(id), SEC_CAM_ENT_VALUE_ARG(ent)); + } else { + DBG_871X_SEL_NL(sel, SEC_CAM_ENT_VALUE_FMT"\n", SEC_CAM_ENT_VALUE_ARG(ent)); + } +} + +void dump_sec_cam_ent_title(void *sel, u8 has_id) +{ + if (has_id) { + DBG_871X_SEL_NL(sel, SEC_CAM_ENT_ID_TITLE_FMT " " SEC_CAM_ENT_TITLE_FMT"\n" + , SEC_CAM_ENT_ID_TITLE_ARG, SEC_CAM_ENT_TITLE_ARG); + } else { + DBG_871X_SEL_NL(sel, SEC_CAM_ENT_TITLE_FMT"\n", SEC_CAM_ENT_TITLE_ARG); + } +} + +void dump_sec_cam(void *sel, _adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + struct sec_cam_ent ent; + int i; + + DBG_871X_SEL_NL(sel, "HW sec cam:\n"); + dump_sec_cam_ent_title(sel, 1); + for (i = 0; i < cam_ctl->num; i++) { + rtw_sec_read_cam_ent(adapter, i, (u8 *)(&ent.ctrl), ent.mac, ent.key); + dump_sec_cam_ent(sel , &ent, i); + } +} + +#ifdef CONFIG_PROC_DEBUG +ssize_t proc_set_write_reg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u32 addr, val, len; + + if (count < 3) + { + DBG_871X("argument size is less than 3\n"); + return -EFAULT; + } + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%x %x %x", &addr, &val, &len); + + if (num != 3) { + DBG_871X("invalid write_reg parameter!\n"); + return count; + } + + switch(len) + { + case 1: + rtw_write8(padapter, addr, (u8)val); + break; + case 2: + rtw_write16(padapter, addr, (u16)val); + break; + case 4: + rtw_write32(padapter, addr, val); + break; + default: + DBG_871X("error write length=%d", len); + break; + } + + } + + return count; + +} + +static u32 proc_get_read_addr=0xeeeeeeee; +static u32 proc_get_read_len=0x4; + +int proc_get_read_reg(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + if (proc_get_read_addr==0xeeeeeeee) { + DBG_871X_SEL_NL(m, "address not initialized\n"); + return 0; + } + + switch(proc_get_read_len) + { + case 1: + DBG_871X_SEL_NL(m, "rtw_read8(0x%x)=0x%x\n", proc_get_read_addr, rtw_read8(padapter, proc_get_read_addr)); + break; + case 2: + DBG_871X_SEL_NL(m, "rtw_read16(0x%x)=0x%x\n", proc_get_read_addr, rtw_read16(padapter, proc_get_read_addr)); + break; + case 4: + DBG_871X_SEL_NL(m, "rtw_read32(0x%x)=0x%x\n", proc_get_read_addr, rtw_read32(padapter, proc_get_read_addr)); + break; + default: + DBG_871X_SEL_NL(m, "error read length=%d\n", proc_get_read_len); + break; + } + + return 0; +} + +ssize_t proc_set_read_reg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + char tmp[16]; + u32 addr, len; + + if (count < 2) + { + DBG_871X("argument size is less than 2\n"); + return -EFAULT; + } + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%x %x", &addr, &len); + + if (num != 2) { + DBG_871X("invalid read_reg parameter!\n"); + return count; + } + + proc_get_read_addr = addr; + + proc_get_read_len = len; + } + + return count; + +} + +int proc_get_fwstate(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + DBG_871X_SEL_NL(m, "fwstate=0x%x\n", get_fwstate(pmlmepriv)); + + return 0; +} + +int proc_get_sec_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct security_priv *sec = &padapter->securitypriv; + + DBG_871X_SEL_NL(m, "auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\n", + sec->dot11AuthAlgrthm, sec->dot11PrivacyAlgrthm, + sec->ndisauthtype, sec->ndisencryptstatus); + + DBG_871X_SEL_NL(m, "hw_decrypted=%d\n", sec->hw_decrypted); + +#ifdef DBG_SW_SEC_CNT + DBG_871X_SEL_NL(m, "wep_sw_enc_cnt=%llu, %llu, %llu\n" + , sec->wep_sw_enc_cnt_bc , sec->wep_sw_enc_cnt_mc, sec->wep_sw_enc_cnt_uc); + DBG_871X_SEL_NL(m, "wep_sw_dec_cnt=%llu, %llu, %llu\n" + , sec->wep_sw_dec_cnt_bc , sec->wep_sw_dec_cnt_mc, sec->wep_sw_dec_cnt_uc); + + DBG_871X_SEL_NL(m, "tkip_sw_enc_cnt=%llu, %llu, %llu\n" + , sec->tkip_sw_enc_cnt_bc , sec->tkip_sw_enc_cnt_mc, sec->tkip_sw_enc_cnt_uc); + DBG_871X_SEL_NL(m, "tkip_sw_dec_cnt=%llu, %llu, %llu\n" + , sec->tkip_sw_dec_cnt_bc , sec->tkip_sw_dec_cnt_mc, sec->tkip_sw_dec_cnt_uc); + + DBG_871X_SEL_NL(m, "aes_sw_enc_cnt=%llu, %llu, %llu\n" + , sec->aes_sw_enc_cnt_bc , sec->aes_sw_enc_cnt_mc, sec->aes_sw_enc_cnt_uc); + DBG_871X_SEL_NL(m, "aes_sw_dec_cnt=%llu, %llu, %llu\n" + , sec->aes_sw_dec_cnt_bc , sec->aes_sw_dec_cnt_mc, sec->aes_sw_dec_cnt_uc); +#endif /* DBG_SW_SEC_CNT */ + + return 0; +} + +int proc_get_mlmext_state(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + DBG_871X_SEL_NL(m, "pmlmeinfo->state=0x%x\n", pmlmeinfo->state); + + return 0; +} + +#ifdef CONFIG_LAYER2_ROAMING +int proc_get_roam_flags(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + DBG_871X_SEL_NL(m, "0x%02x\n", rtw_roam_flags(adapter)); + + return 0; +} + +ssize_t proc_set_roam_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + char tmp[32]; + u8 flags; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhx", &flags); + + if (num == 1) + rtw_assign_roam_flags(adapter, flags); + } + + return count; + +} + +int proc_get_roam_param(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *mlme = &adapter->mlmepriv; + + DBG_871X_SEL_NL(m, "%12s %12s %11s\n", "rssi_diff_th", "scanr_exp_ms", "scan_int_ms"); + DBG_871X_SEL_NL(m, "%-12u %-12u %-11u\n" + , mlme->roam_rssi_diff_th + , mlme->roam_scanr_exp_ms + , mlme->roam_scan_int_ms + ); + + return 0; +} + +ssize_t proc_set_roam_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *mlme = &adapter->mlmepriv; + + char tmp[32]; + u8 rssi_diff_th; + u32 scanr_exp_ms; + u32 scan_int_ms; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhu %u %u", &rssi_diff_th, &scanr_exp_ms, &scan_int_ms); + + if (num >= 1) + mlme->roam_rssi_diff_th = rssi_diff_th; + if (num >= 2) + mlme->roam_scanr_exp_ms = scanr_exp_ms; + if (num >= 3) + mlme->roam_scan_int_ms = scan_int_ms; + } + + return count; + +} + +ssize_t proc_set_roam_tgt_addr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + char tmp[32]; + u8 addr[ETH_ALEN]; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", addr, addr+1, addr+2, addr+3, addr+4, addr+5); + if (num == 6) + _rtw_memcpy(adapter->mlmepriv.roam_tgt_addr, addr, ETH_ALEN); + + DBG_871X("set roam_tgt_addr to "MAC_FMT"\n", MAC_ARG(adapter->mlmepriv.roam_tgt_addr)); + } + + return count; +} +#endif /* CONFIG_LAYER2_ROAMING */ + +int proc_get_qos_option(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + DBG_871X_SEL_NL(m, "qos_option=%d\n", pmlmepriv->qospriv.qos_option); + + return 0; +} + +int proc_get_ht_option(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + +#ifdef CONFIG_80211N_HT + DBG_871X_SEL_NL(m, "ht_option=%d\n", pmlmepriv->htpriv.ht_option); +#endif //CONFIG_80211N_HT + + return 0; +} + +int proc_get_rf_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + DBG_871X_SEL_NL(m, "cur_ch=%d, cur_bw=%d, cur_ch_offet=%d\n", + pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset); + + DBG_871X_SEL_NL(m, "oper_ch=%d, oper_bw=%d, oper_ch_offet=%d\n", + rtw_get_oper_ch(padapter), rtw_get_oper_bw(padapter), rtw_get_oper_choffset(padapter)); + + return 0; +} + +int proc_get_scan_param(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + struct ss_res *ss = &mlmeext->sitesurvey_res; + +#define SCAN_PARAM_TITLE_FMT "%10s" +#define SCAN_PARAM_VALUE_FMT "%-10u" +#define SCAN_PARAM_TITLE_ARG , "scan_ch_ms" +#define SCAN_PARAM_VALUE_ARG , ss->scan_ch_ms +#ifdef CONFIG_80211N_HT + #define SCAN_PARAM_TITLE_FMT_HT " %15s %13s" + #define SCAN_PARAM_VALUE_FMT_HT " %-15u %-13u" + #define SCAN_PARAM_TITLE_ARG_HT , "rx_ampdu_accept", "rx_ampdu_size" + #define SCAN_PARAM_VALUE_ARG_HT , ss->rx_ampdu_accept, ss->rx_ampdu_size +#else + #define SCAN_PARAM_TITLE_FMT_HT "" + #define SCAN_PARAM_VALUE_FMT_HT "" + #define SCAN_PARAM_TITLE_ARG_HT + #define SCAN_PARAM_VALUE_ARG_HT +#endif +#ifdef CONFIG_SCAN_BACKOP + #define SCAN_PARAM_TITLE_FMT_BACKOP " %9s %12s" + #define SCAN_PARAM_VALUE_FMT_BACKOP " %-9u %-12u" + #define SCAN_PARAM_TITLE_ARG_BACKOP , "backop_ms", "scan_cnt_max" + #define SCAN_PARAM_VALUE_ARG_BACKOP , ss->backop_ms, ss->scan_cnt_max +#else + #define SCAN_PARAM_TITLE_FMT_BACKOP "" + #define SCAN_PARAM_VALUE_FMT_BACKOP "" + #define SCAN_PARAM_TITLE_ARG_BACKOP + #define SCAN_PARAM_VALUE_ARG_BACKOP +#endif + + DBG_871X_SEL_NL(m, + SCAN_PARAM_TITLE_FMT + SCAN_PARAM_TITLE_FMT_HT + SCAN_PARAM_TITLE_FMT_BACKOP + "\n" + SCAN_PARAM_TITLE_ARG + SCAN_PARAM_TITLE_ARG_HT + SCAN_PARAM_TITLE_ARG_BACKOP + ); + + DBG_871X_SEL_NL(m, + SCAN_PARAM_VALUE_FMT + SCAN_PARAM_VALUE_FMT_HT + SCAN_PARAM_VALUE_FMT_BACKOP + "\n" + SCAN_PARAM_VALUE_ARG + SCAN_PARAM_VALUE_ARG_HT + SCAN_PARAM_VALUE_ARG_BACKOP + ); + + return 0; +} + +ssize_t proc_set_scan_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + struct ss_res *ss = &mlmeext->sitesurvey_res; + + char tmp[32] = {0}; + +u16 scan_ch_ms; +#define SCAN_PARAM_INPUT_FMT "%hu" +#define SCAN_PARAM_INPUT_ARG , &scan_ch_ms +#ifdef CONFIG_80211N_HT + u8 rx_ampdu_accept; + u8 rx_ampdu_size; + #define SCAN_PARAM_INPUT_FMT_HT " %hhu %hhu" + #define SCAN_PARAM_INPUT_ARG_HT , &rx_ampdu_accept, &rx_ampdu_size +#else + #define SCAN_PARAM_INPUT_FMT_HT "" + #define SCAN_PARAM_INPUT_ARG_HT +#endif +#ifdef CONFIG_SCAN_BACKOP + u16 backop_ms; + u8 scan_cnt_max; + #define SCAN_PARAM_INPUT_FMT_BACKOP " %hu %hhu" + #define SCAN_PARAM_INPUT_ARG_BACKOP , &backop_ms, &scan_cnt_max +#else + #define SCAN_PARAM_INPUT_FMT_BACKOP "" + #define SCAN_PARAM_INPUT_ARG_BACKOP +#endif + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, + SCAN_PARAM_INPUT_FMT + SCAN_PARAM_INPUT_FMT_HT + SCAN_PARAM_INPUT_FMT_BACKOP + SCAN_PARAM_INPUT_ARG + SCAN_PARAM_INPUT_ARG_HT + SCAN_PARAM_INPUT_ARG_BACKOP + ); + + if (num-- > 0) + ss->scan_ch_ms = scan_ch_ms; + #ifdef CONFIG_80211N_HT + if (num-- > 0) + ss->rx_ampdu_accept = rx_ampdu_accept; + if (num-- > 0) + ss->rx_ampdu_size = rx_ampdu_size; + #endif + #ifdef CONFIG_SCAN_BACKOP + if (num-- > 0) + ss->backop_ms = backop_ms; + if (num-- > 0) + ss->scan_cnt_max = scan_cnt_max; + #endif + } + + return count; +} + +int proc_get_scan_abort(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + u32 pass_ms; + + pass_ms = rtw_scan_abort_timeout(adapter, 10000); + + DBG_871X_SEL_NL(m, "%u\n", pass_ms); + + return 0; +} + +#ifdef CONFIG_SCAN_BACKOP +int proc_get_backop_flags_sta(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + + DBG_871X_SEL_NL(m, "0x%02x\n", mlmeext_scan_backop_flags_sta(mlmeext)); + + return 0; +} + +ssize_t proc_set_backop_flags_sta(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + + char tmp[32]; + u8 flags; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhx", &flags); + + if (num == 1) + mlmeext_assign_scan_backop_flags_sta(mlmeext, flags); + } + + return count; +} + +int proc_get_backop_flags_ap(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + + DBG_871X_SEL_NL(m, "0x%02x\n", mlmeext_scan_backop_flags_ap(mlmeext)); + + return 0; +} + +ssize_t proc_set_backop_flags_ap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + + char tmp[32]; + u8 flags; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhx", &flags); + + if (num == 1) + mlmeext_assign_scan_backop_flags_ap(mlmeext, flags); + } + + return count; +} + +#endif /* CONFIG_SCAN_BACKOP */ + +int proc_get_survey_info(struct seq_file *m, void *v) +{ + _irqL irqL; + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + _list *plist, *phead; + s32 notify_signal; + s16 notify_noise = 0; + u16 index = 0, ie_cap = 0; + unsigned char *ie_wpa = NULL, *ie_wpa2 = NULL, *ie_wps = NULL; + unsigned char *ie_p2p = NULL, *ssid = NULL; + char flag_str[64]; + int ielen = 0; + u32 wpsielen = 0; + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + phead = get_list_head(queue); + if(!phead) + return 0; + plist = get_next(phead); + if (!plist) + return 0; + + DBG_871X_SEL_NL(m, "%5s %-17s %3s %-3s %-4s %-4s %5s %32s %32s\n", "index", "bssid", "ch", "RSSI", "SdBm", "Noise", "age", "flag", "ssid"); + while(1) + { + if (rtw_end_of_queue_search(phead,plist)== _TRUE) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + if (!pnetwork) + break; + + if ( check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE && + is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) { + notify_signal = translate_percentage_to_dbm(padapter->recvpriv.signal_strength);//dbm + } else { + notify_signal = translate_percentage_to_dbm(pnetwork->network.PhyInfo.SignalStrength);//dbm + } + + #if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) + rtw_hal_get_odm_var(padapter, HAL_ODM_NOISE_MONITOR,&(pnetwork->network.Configuration.DSConfig), &(notify_noise)); + #endif + + ie_wpa = rtw_get_wpa_ie(&pnetwork->network.IEs[12], &ielen, pnetwork->network.IELength-12); + ie_wpa2 = rtw_get_wpa2_ie(&pnetwork->network.IEs[12], &ielen, pnetwork->network.IELength-12); + ie_cap = rtw_get_capability(&pnetwork->network); + ie_wps = rtw_get_wps_ie(&pnetwork->network.IEs[12], pnetwork->network.IELength-12, NULL, &wpsielen); + ie_p2p = rtw_get_p2p_ie(&pnetwork->network.IEs[12], pnetwork->network.IELength-12, NULL, &ielen); + ssid = pnetwork->network.Ssid.Ssid; + sprintf(flag_str, "%s%s%s%s%s%s%s", + (ie_wpa) ? "[WPA]":"", + (ie_wpa2) ? "[WPA2]":"", + (!ie_wpa && !ie_wpa && ie_cap & BIT(4)) ? "[WEP]":"", + (ie_wps) ? "[WPS]":"", + (pnetwork->network.InfrastructureMode == Ndis802_11IBSS) ? "[IBSS]":"", + (ie_cap & BIT(0)) ? "[ESS]":"", + (ie_p2p) ? "[P2P]":""); + DBG_871X_SEL_NL(m, "%5d "MAC_FMT" %3d %3d %4d %4d %5d %32s %32s\n", + ++index, + MAC_ARG(pnetwork->network.MacAddress), + pnetwork->network.Configuration.DSConfig, + (int)pnetwork->network.Rssi, + notify_signal, + notify_noise, + rtw_get_passing_time_ms((u32)pnetwork->last_scanned), + flag_str, + pnetwork->network.Ssid.Ssid); + plist = get_next(plist); + } + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + return 0; +} + +ssize_t proc_set_survey_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + _irqL irqL; + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + bool need_indicate_scan_done = _FALSE; + u8 _status = _FALSE; + NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; + + if (count < 1) + return -EFAULT; + +#ifdef CONFIG_MP_INCLUDED + if ((padapter->registrypriv.mp_mode == 1) +#ifdef CONFIG_CONCURRENT_MODE + || ((padapter->pbuddy_adapter) && (padapter->pbuddy_adapter->registrypriv.mp_mode == 1)) +#endif + ){ + DBG_871X(FUNC_ADPT_FMT ": MP mode block Scan request\n", FUNC_ADPT_ARG(padapter)); + goto exit; + } +#endif + rtw_ps_deny(padapter, PS_DENY_SCAN); + if (_FAIL == rtw_pwr_wakeup(padapter)) + goto exit; + + if (rtw_is_drv_stopped(padapter)) { + DBG_871X("scan abort!! bDriverStopped=_TRUE\n"); + goto exit; + } + + if (!padapter->bup) { + DBG_871X("scan abort!! bup=%d\n", padapter->bup); + goto exit; + } + + if (!rtw_is_hw_init_completed(padapter)) { + DBG_871X("scan abort!! hw_init_completed=FALSE\n"); + goto exit; + } + + if (rtw_is_scan_deny(padapter)) { + DBG_871X(FUNC_ADPT_FMT ": scan deny\n", FUNC_ADPT_ARG(padapter)); + goto exit; + } + + if ((pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE) +#ifdef CONFIG_CONCURRENT_MODE + || (rtw_get_buddy_bBusyTraffic(padapter) == _TRUE) +#endif + ) { + DBG_871X("scan abort!! BusyTraffic == _TRUE\n"); + goto exit; + } + + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE) { + DBG_8192C("scan abort!! fwstate=0x%x\n", pmlmepriv->fw_state); + goto exit; + } + +#ifdef CONFIG_CONCURRENT_MODE + if (check_buddy_fwstate(padapter, + _FW_UNDER_SURVEY|_FW_UNDER_LINKING|WIFI_UNDER_WPS) == _TRUE) { + DBG_871X("scan abort!! buddy_fwstate=0x%x\n", + get_fwstate(&(padapter->pbuddy_adapter->mlmepriv))); + goto exit; + } +#endif + _status = rtw_set_802_11_bssid_list_scan(padapter, NULL, 0); + +exit: + rtw_ps_deny_cancel(padapter, PS_DENY_SCAN); + return count; +} + +int proc_get_ap_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + struct sta_info *psta; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct wlan_network *cur_network = &(pmlmepriv->cur_network); + struct sta_priv *pstapriv = &padapter->stapriv; + + psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); + if(psta) + { + int i; + struct recv_reorder_ctrl *preorder_ctrl; + + DBG_871X_SEL_NL(m, "SSID=%s\n", cur_network->network.Ssid.Ssid); + DBG_871X_SEL_NL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr)); + DBG_871X_SEL_NL(m, "cur_channel=%d, cur_bwmode=%d, cur_ch_offset=%d\n", pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset); + DBG_871X_SEL_NL(m, "wireless_mode=0x%x, rtsen=%d, cts2slef=%d\n", psta->wireless_mode, psta->rtsen, psta->cts2self); + DBG_871X_SEL_NL(m, "state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid); +#ifdef CONFIG_80211N_HT + DBG_871X_SEL_NL(m, "qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); + DBG_871X_SEL_NL(m, "bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n", psta->bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m); + DBG_871X_SEL_NL(m, "ampdu_enable = %d\n", psta->htpriv.ampdu_enable); + DBG_871X_SEL_NL(m, "agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); + DBG_871X_SEL_NL(m, "ldpc_cap=0x%x, stbc_cap=0x%x, beamform_cap=0x%x\n", psta->htpriv.ldpc_cap, psta->htpriv.stbc_cap, psta->htpriv.beamform_cap); +#endif //CONFIG_80211N_HT +#ifdef CONFIG_80211AC_VHT + DBG_871X_SEL_NL(m, "vht_en=%d, vht_sgi_80m=%d\n", psta->vhtpriv.vht_option, psta->vhtpriv.sgi_80m); + DBG_871X_SEL_NL(m, "vht_ldpc_cap=0x%x, vht_stbc_cap=0x%x, vht_beamform_cap=0x%x\n", psta->vhtpriv.ldpc_cap, psta->vhtpriv.stbc_cap, psta->vhtpriv.beamform_cap); + DBG_871X_SEL_NL(m, "vht_mcs_map=0x%x, vht_highest_rate=0x%x, vht_ampdu_len=%d\n", *(u16*)psta->vhtpriv.vht_mcs_map, psta->vhtpriv.vht_highest_rate, psta->vhtpriv.ampdu_len); +#endif + + sta_rx_reorder_ctl_dump(m, psta); + } + else + { + DBG_871X_SEL_NL(m, "can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress)); + } + + return 0; +} + +ssize_t proc_reset_trx_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + char cmd[32] = {0}; + u8 cnt = 0; + + if (count > sizeof(cmd)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(cmd, buffer, count)) { + int num = sscanf(cmd, "%hhx", &cnt); + + if (0 == cnt) { + pdbgpriv->dbg_rx_ampdu_drop_count = 0; + pdbgpriv->dbg_rx_ampdu_forced_indicate_count = 0; + pdbgpriv->dbg_rx_ampdu_loss_count = 0; + pdbgpriv->dbg_rx_dup_mgt_frame_drop_count = 0; + pdbgpriv->dbg_rx_ampdu_window_shift_cnt = 0; + pdbgpriv->dbg_rx_conflic_mac_addr_cnt = 0; + } + } + + return count; +} + +int proc_get_trx_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + int i; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct recv_priv *precvpriv = &padapter->recvpriv; + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + struct hw_xmit *phwxmit; + + dump_os_queue(m, padapter); + + DBG_871X_SEL_NL(m, "free_xmitbuf_cnt=%d, free_xmitframe_cnt=%d\n" + , pxmitpriv->free_xmitbuf_cnt, pxmitpriv->free_xmitframe_cnt); + DBG_871X_SEL_NL(m, "free_ext_xmitbuf_cnt=%d, free_xframe_ext_cnt=%d\n" + , pxmitpriv->free_xmit_extbuf_cnt, pxmitpriv->free_xframe_ext_cnt); + DBG_871X_SEL_NL(m, "free_recvframe_cnt=%d\n" + , precvpriv->free_recvframe_cnt); + + for(i = 0; i < 4; i++) + { + phwxmit = pxmitpriv->hwxmits + i; + DBG_871X_SEL_NL(m, "%d, hwq.accnt=%d\n", i, phwxmit->accnt); + } + +#ifdef CONFIG_USB_HCI + DBG_871X_SEL_NL(m, "rx_urb_pending_cn=%d\n", ATOMIC_READ(&(precvpriv->rx_pending_cnt))); +#endif + + //Folowing are RX info + //Counts of packets whose seq_num is less than preorder_ctrl->indicate_seq, Ex delay, retransmission, redundant packets and so on + DBG_871X_SEL_NL(m,"Rx: Counts of Packets Whose Seq_Num Less Than Reorder Control Seq_Num: %llu\n",(unsigned long long)pdbgpriv->dbg_rx_ampdu_drop_count); + //How many times the Rx Reorder Timer is triggered. + DBG_871X_SEL_NL(m,"Rx: Reorder Time-out Trigger Counts: %llu\n",(unsigned long long)pdbgpriv->dbg_rx_ampdu_forced_indicate_count); + //Total counts of packets loss + DBG_871X_SEL_NL(m,"Rx: Packet Loss Counts: %llu\n",(unsigned long long)pdbgpriv->dbg_rx_ampdu_loss_count); + DBG_871X_SEL_NL(m,"Rx: Duplicate Management Frame Drop Count: %llu\n",(unsigned long long)pdbgpriv->dbg_rx_dup_mgt_frame_drop_count); + DBG_871X_SEL_NL(m,"Rx: AMPDU BA window shift Count: %llu\n",(unsigned long long)pdbgpriv->dbg_rx_ampdu_window_shift_cnt); + /*The same mac addr counts*/ + DBG_871X_SEL_NL(m, "Rx: Conflict MAC Address Frames Count: %llu\n", (unsigned long long)pdbgpriv->dbg_rx_conflic_mac_addr_cnt); + return 0; +} + +int proc_get_dis_pwt(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u8 dis_pwt = 0; + rtw_hal_get_def_var(padapter, HAL_DEF_DBG_DIS_PWT, &(dis_pwt)); + DBG_871X_SEL_NL(m, " Tx Power training mode:%s \n",(dis_pwt==_TRUE)?"Disable":"Enable"); + return 0; +} +ssize_t proc_set_dis_pwt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[4]={0}; + u8 dis_pwt = 0; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhx", &dis_pwt); + DBG_871X("Set Tx Power training mode:%s\n", (dis_pwt == _TRUE)?"Disable":"Enable"); + + if (num >= 1) + rtw_hal_set_def_var(padapter, HAL_DEF_DBG_DIS_PWT, &(dis_pwt)); + } + + return count; + +} + +int proc_get_rate_ctl(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + int i; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + u8 data_rate = 0, sgi=0, data_fb = 0; + + if (adapter->fix_rate != 0xff) { + data_rate = adapter->fix_rate & 0x7F; + sgi = adapter->fix_rate >>7; + data_fb = adapter->data_fb?1:0; + DBG_871X_SEL_NL(m, "FIXED %s%s%s\n" + , HDATA_RATE(data_rate) + , data_rate>DESC_RATE54M?(sgi?" SGI":" LGI"):"" + , data_fb?" FB":"" + ); + DBG_871X_SEL_NL(m, "0x%02x %u\n", adapter->fix_rate, adapter->data_fb); + } else { + DBG_871X_SEL_NL(m, "RA\n"); + } + + return 0; +} + +ssize_t proc_set_rate_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u8 fix_rate; + u8 data_fb; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhx %hhu", &fix_rate, &data_fb); + + if (num >= 1) + adapter->fix_rate = fix_rate; + if (num >= 2) + adapter->data_fb = data_fb?1:0; + } + + return count; +} +#ifdef DBG_RX_COUNTER_DUMP +int proc_get_rx_cnt_dump(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + int i; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + DBG_871X_SEL_NL(m, "BIT0- Dump RX counters of DRV \n"); + DBG_871X_SEL_NL(m, "BIT1- Dump RX counters of MAC \n"); + DBG_871X_SEL_NL(m, "BIT2- Dump RX counters of PHY \n"); + DBG_871X_SEL_NL(m, "BIT3- Dump TRX data frame of DRV \n"); + DBG_871X_SEL_NL(m, "dump_rx_cnt_mode = 0x%02x \n", adapter->dump_rx_cnt_mode); + + return 0; +} +ssize_t proc_set_rx_cnt_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u8 dump_rx_cnt_mode; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhx", &dump_rx_cnt_mode); + + rtw_dump_phy_rxcnts_preprocess(adapter,dump_rx_cnt_mode); + adapter->dump_rx_cnt_mode = dump_rx_cnt_mode; + + } + + return count; +} +#endif +ssize_t proc_set_fwdl_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + int num; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) + num = sscanf(tmp, "%hhu %hhu", &fwdl_test_chksum_fail, &fwdl_test_wintint_rdy_fail); + + return count; +} + +ssize_t proc_set_del_rx_ampdu_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + int num; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) + num = sscanf(tmp, "%hhu", &del_rx_ampdu_test_no_tx_fail); + + return count; +} + +#ifdef CONFIG_DFS_MASTER +int proc_get_dfs_master_test_case(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + + DBG_871X_SEL_NL(m, "%-24s %-19s\n", "radar_detect_trigger_non", "choose_dfs_ch_first"); + DBG_871X_SEL_NL(m, "%24hhu %19hhu\n" + , rfctl->dbg_dfs_master_radar_detect_trigger_non + , rfctl->dbg_dfs_master_choose_dfs_ch_first + ); + + return 0; +} + +ssize_t proc_set_dfs_master_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + char tmp[32]; + u8 radar_detect_trigger_non; + u8 choose_dfs_ch_first; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + int num = sscanf(tmp, "%hhu %hhu", &radar_detect_trigger_non, &choose_dfs_ch_first); + + if (num >= 1) + rfctl->dbg_dfs_master_radar_detect_trigger_non = radar_detect_trigger_non; + if (num >= 2) + rfctl->dbg_dfs_master_choose_dfs_ch_first = choose_dfs_ch_first; + } + + return count; +} +#endif /* CONFIG_DFS_MASTER */ + +ssize_t proc_set_wait_hiq_empty(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + int num; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) + num = sscanf(tmp, "%u", &g_wait_hiq_empty_ms); + + return count; +} + +int proc_get_suspend_resume_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = padapter->dvobj; + struct debug_priv *pdbgpriv = &dvobj->drv_dbg; + + DBG_871X_SEL_NL(m, "dbg_sdio_alloc_irq_cnt=%d\n", pdbgpriv->dbg_sdio_alloc_irq_cnt); + DBG_871X_SEL_NL(m, "dbg_sdio_free_irq_cnt=%d\n", pdbgpriv->dbg_sdio_free_irq_cnt); + DBG_871X_SEL_NL(m, "dbg_sdio_alloc_irq_error_cnt=%d\n",pdbgpriv->dbg_sdio_alloc_irq_error_cnt); + DBG_871X_SEL_NL(m, "dbg_sdio_free_irq_error_cnt=%d\n", pdbgpriv->dbg_sdio_free_irq_error_cnt); + DBG_871X_SEL_NL(m, "dbg_sdio_init_error_cnt=%d\n",pdbgpriv->dbg_sdio_init_error_cnt); + DBG_871X_SEL_NL(m, "dbg_sdio_deinit_error_cnt=%d\n", pdbgpriv->dbg_sdio_deinit_error_cnt); + DBG_871X_SEL_NL(m, "dbg_suspend_error_cnt=%d\n", pdbgpriv->dbg_suspend_error_cnt); + DBG_871X_SEL_NL(m, "dbg_suspend_cnt=%d\n",pdbgpriv->dbg_suspend_cnt); + DBG_871X_SEL_NL(m, "dbg_resume_cnt=%d\n", pdbgpriv->dbg_resume_cnt); + DBG_871X_SEL_NL(m, "dbg_resume_error_cnt=%d\n", pdbgpriv->dbg_resume_error_cnt); + DBG_871X_SEL_NL(m, "dbg_deinit_fail_cnt=%d\n",pdbgpriv->dbg_deinit_fail_cnt); + DBG_871X_SEL_NL(m, "dbg_carddisable_cnt=%d\n", pdbgpriv->dbg_carddisable_cnt); + DBG_871X_SEL_NL(m, "dbg_ps_insuspend_cnt=%d\n",pdbgpriv->dbg_ps_insuspend_cnt); + DBG_871X_SEL_NL(m, "dbg_dev_unload_inIPS_cnt=%d\n", pdbgpriv->dbg_dev_unload_inIPS_cnt); + DBG_871X_SEL_NL(m, "dbg_scan_pwr_state_cnt=%d\n", pdbgpriv->dbg_scan_pwr_state_cnt); + DBG_871X_SEL_NL(m, "dbg_downloadfw_pwr_state_cnt=%d\n", pdbgpriv->dbg_downloadfw_pwr_state_cnt); + DBG_871X_SEL_NL(m, "dbg_carddisable_error_cnt=%d\n", pdbgpriv->dbg_carddisable_error_cnt); + DBG_871X_SEL_NL(m, "dbg_fw_read_ps_state_fail_cnt=%d\n", pdbgpriv->dbg_fw_read_ps_state_fail_cnt); + DBG_871X_SEL_NL(m, "dbg_leave_ips_fail_cnt=%d\n", pdbgpriv->dbg_leave_ips_fail_cnt); + DBG_871X_SEL_NL(m, "dbg_leave_lps_fail_cnt=%d\n", pdbgpriv->dbg_leave_lps_fail_cnt); + DBG_871X_SEL_NL(m, "dbg_h2c_leave32k_fail_cnt=%d\n", pdbgpriv->dbg_h2c_leave32k_fail_cnt); + DBG_871X_SEL_NL(m, "dbg_diswow_dload_fw_fail_cnt=%d\n", pdbgpriv->dbg_diswow_dload_fw_fail_cnt); + DBG_871X_SEL_NL(m, "dbg_enwow_dload_fw_fail_cnt=%d\n", pdbgpriv->dbg_enwow_dload_fw_fail_cnt); + DBG_871X_SEL_NL(m, "dbg_ips_drvopen_fail_cnt=%d\n", pdbgpriv->dbg_ips_drvopen_fail_cnt); + DBG_871X_SEL_NL(m, "dbg_poll_fail_cnt=%d\n", pdbgpriv->dbg_poll_fail_cnt); + DBG_871X_SEL_NL(m, "dbg_rpwm_toogle_cnt=%d\n", pdbgpriv->dbg_rpwm_toogle_cnt); + DBG_871X_SEL_NL(m, "dbg_rpwm_timeout_fail_cnt=%d\n", pdbgpriv->dbg_rpwm_timeout_fail_cnt); + DBG_871X_SEL_NL(m, "dbg_sreset_cnt=%d\n", pdbgpriv->dbg_sreset_cnt); + + return 0; +} + +#ifdef CONFIG_DBG_COUNTER + +int proc_get_rx_logs(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct rx_logs *rx_logs = &padapter->rx_logs; + + DBG_871X_SEL_NL(m, + "intf_rx=%d\n" + "intf_rx_err_recvframe=%d\n" + "intf_rx_err_skb=%d\n" + "intf_rx_report=%d\n" + "core_rx=%d\n" + "core_rx_pre=%d\n" + "core_rx_pre_ver_err=%d\n" + "core_rx_pre_mgmt=%d\n" + "core_rx_pre_mgmt_err_80211w=%d\n" + "core_rx_pre_mgmt_err=%d\n" + "core_rx_pre_ctrl=%d\n" + "core_rx_pre_ctrl_err=%d\n" + "core_rx_pre_data=%d\n" + "core_rx_pre_data_wapi_seq_err=%d\n" + "core_rx_pre_data_wapi_key_err=%d\n" + "core_rx_pre_data_handled=%d\n" + "core_rx_pre_data_err=%d\n" + "core_rx_pre_data_unknown=%d\n" + "core_rx_pre_unknown=%d\n" + "core_rx_enqueue=%d\n" + "core_rx_dequeue=%d\n" + "core_rx_post=%d\n" + "core_rx_post_decrypt=%d\n" + "core_rx_post_decrypt_wep=%d\n" + "core_rx_post_decrypt_tkip=%d\n" + "core_rx_post_decrypt_aes=%d\n" + "core_rx_post_decrypt_wapi=%d\n" + "core_rx_post_decrypt_hw=%d\n" + "core_rx_post_decrypt_unknown=%d\n" + "core_rx_post_decrypt_err=%d\n" + "core_rx_post_defrag_err=%d\n" + "core_rx_post_portctrl_err=%d\n" + "core_rx_post_indicate=%d\n" + "core_rx_post_indicate_in_oder=%d\n" + "core_rx_post_indicate_reoder=%d\n" + "core_rx_post_indicate_err=%d\n" + "os_indicate=%d\n" + "os_indicate_ap_mcast=%d\n" + "os_indicate_ap_forward=%d\n" + "os_indicate_ap_self=%d\n" + "os_indicate_err=%d\n" + "os_netif_ok=%d\n" + "os_netif_err=%d\n", + rx_logs->intf_rx, + rx_logs->intf_rx_err_recvframe, + rx_logs->intf_rx_err_skb, + rx_logs->intf_rx_report, + rx_logs->core_rx, + rx_logs->core_rx_pre, + rx_logs->core_rx_pre_ver_err, + rx_logs->core_rx_pre_mgmt, + rx_logs->core_rx_pre_mgmt_err_80211w, + rx_logs->core_rx_pre_mgmt_err, + rx_logs->core_rx_pre_ctrl, + rx_logs->core_rx_pre_ctrl_err, + rx_logs->core_rx_pre_data, + rx_logs->core_rx_pre_data_wapi_seq_err, + rx_logs->core_rx_pre_data_wapi_key_err, + rx_logs->core_rx_pre_data_handled, + rx_logs->core_rx_pre_data_err, + rx_logs->core_rx_pre_data_unknown, + rx_logs->core_rx_pre_unknown, + rx_logs->core_rx_enqueue, + rx_logs->core_rx_dequeue, + rx_logs->core_rx_post, + rx_logs->core_rx_post_decrypt, + rx_logs->core_rx_post_decrypt_wep, + rx_logs->core_rx_post_decrypt_tkip, + rx_logs->core_rx_post_decrypt_aes, + rx_logs->core_rx_post_decrypt_wapi, + rx_logs->core_rx_post_decrypt_hw, + rx_logs->core_rx_post_decrypt_unknown, + rx_logs->core_rx_post_decrypt_err, + rx_logs->core_rx_post_defrag_err, + rx_logs->core_rx_post_portctrl_err, + rx_logs->core_rx_post_indicate, + rx_logs->core_rx_post_indicate_in_oder, + rx_logs->core_rx_post_indicate_reoder, + rx_logs->core_rx_post_indicate_err, + rx_logs->os_indicate, + rx_logs->os_indicate_ap_mcast, + rx_logs->os_indicate_ap_forward, + rx_logs->os_indicate_ap_self, + rx_logs->os_indicate_err, + rx_logs->os_netif_ok, + rx_logs->os_netif_err + ); + + return 0; +} + +int proc_get_tx_logs(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct tx_logs *tx_logs = &padapter->tx_logs; + + DBG_871X_SEL_NL(m, + "os_tx=%d\n" + "os_tx_err_up=%d\n" + "os_tx_err_xmit=%d\n" + "os_tx_m2u=%d\n" + "os_tx_m2u_ignore_fw_linked=%d\n" + "os_tx_m2u_ignore_self=%d\n" + "os_tx_m2u_entry=%d\n" + "os_tx_m2u_entry_err_xmit=%d\n" + "os_tx_m2u_entry_err_skb=%d\n" + "os_tx_m2u_stop=%d\n" + "core_tx=%d\n" + "core_tx_err_pxmitframe=%d\n" + "core_tx_err_brtx=%d\n" + "core_tx_upd_attrib=%d\n" + "core_tx_upd_attrib_adhoc=%d\n" + "core_tx_upd_attrib_sta=%d\n" + "core_tx_upd_attrib_ap=%d\n" + "core_tx_upd_attrib_unknown=%d\n" + "core_tx_upd_attrib_dhcp=%d\n" + "core_tx_upd_attrib_icmp=%d\n" + "core_tx_upd_attrib_active=%d\n" + "core_tx_upd_attrib_err_ucast_sta=%d\n" + "core_tx_upd_attrib_err_ucast_ap_link=%d\n" + "core_tx_upd_attrib_err_sta=%d\n" + "core_tx_upd_attrib_err_link=%d\n" + "core_tx_upd_attrib_err_sec=%d\n" + "core_tx_ap_enqueue_warn_fwstate=%d\n" + "core_tx_ap_enqueue_warn_sta=%d\n" + "core_tx_ap_enqueue_warn_nosta=%d\n" + "core_tx_ap_enqueue_warn_link=%d\n" + "core_tx_ap_enqueue_warn_trigger=%d\n" + "core_tx_ap_enqueue_mcast=%d\n" + "core_tx_ap_enqueue_ucast=%d\n" + "core_tx_ap_enqueue=%d\n" + "intf_tx=%d\n" + "intf_tx_pending_ac=%d\n" + "intf_tx_pending_fw_under_survey=%d\n" + "intf_tx_pending_fw_under_linking=%d\n" + "intf_tx_pending_xmitbuf=%d\n" + "intf_tx_enqueue=%d\n" + "core_tx_enqueue=%d\n" + "core_tx_enqueue_class=%d\n" + "core_tx_enqueue_class_err_sta=%d\n" + "core_tx_enqueue_class_err_nosta=%d\n" + "core_tx_enqueue_class_err_fwlink=%d\n" + "intf_tx_direct=%d\n" + "intf_tx_direct_err_coalesce=%d\n" + "intf_tx_dequeue=%d\n" + "intf_tx_dequeue_err_coalesce=%d\n" + "intf_tx_dump_xframe=%d\n" + "intf_tx_dump_xframe_err_txdesc=%d\n" + "intf_tx_dump_xframe_err_port=%d\n", + tx_logs->os_tx, + tx_logs->os_tx_err_up, + tx_logs->os_tx_err_xmit, + tx_logs->os_tx_m2u, + tx_logs->os_tx_m2u_ignore_fw_linked, + tx_logs->os_tx_m2u_ignore_self, + tx_logs->os_tx_m2u_entry, + tx_logs->os_tx_m2u_entry_err_xmit, + tx_logs->os_tx_m2u_entry_err_skb, + tx_logs->os_tx_m2u_stop, + tx_logs->core_tx, + tx_logs->core_tx_err_pxmitframe, + tx_logs->core_tx_err_brtx, + tx_logs->core_tx_upd_attrib, + tx_logs->core_tx_upd_attrib_adhoc, + tx_logs->core_tx_upd_attrib_sta, + tx_logs->core_tx_upd_attrib_ap, + tx_logs->core_tx_upd_attrib_unknown, + tx_logs->core_tx_upd_attrib_dhcp, + tx_logs->core_tx_upd_attrib_icmp, + tx_logs->core_tx_upd_attrib_active, + tx_logs->core_tx_upd_attrib_err_ucast_sta, + tx_logs->core_tx_upd_attrib_err_ucast_ap_link, + tx_logs->core_tx_upd_attrib_err_sta, + tx_logs->core_tx_upd_attrib_err_link, + tx_logs->core_tx_upd_attrib_err_sec, + tx_logs->core_tx_ap_enqueue_warn_fwstate, + tx_logs->core_tx_ap_enqueue_warn_sta, + tx_logs->core_tx_ap_enqueue_warn_nosta, + tx_logs->core_tx_ap_enqueue_warn_link, + tx_logs->core_tx_ap_enqueue_warn_trigger, + tx_logs->core_tx_ap_enqueue_mcast, + tx_logs->core_tx_ap_enqueue_ucast, + tx_logs->core_tx_ap_enqueue, + tx_logs->intf_tx, + tx_logs->intf_tx_pending_ac, + tx_logs->intf_tx_pending_fw_under_survey, + tx_logs->intf_tx_pending_fw_under_linking, + tx_logs->intf_tx_pending_xmitbuf, + tx_logs->intf_tx_enqueue, + tx_logs->core_tx_enqueue, + tx_logs->core_tx_enqueue_class, + tx_logs->core_tx_enqueue_class_err_sta, + tx_logs->core_tx_enqueue_class_err_nosta, + tx_logs->core_tx_enqueue_class_err_fwlink, + tx_logs->intf_tx_direct, + tx_logs->intf_tx_direct_err_coalesce, + tx_logs->intf_tx_dequeue, + tx_logs->intf_tx_dequeue_err_coalesce, + tx_logs->intf_tx_dump_xframe, + tx_logs->intf_tx_dump_xframe_err_txdesc, + tx_logs->intf_tx_dump_xframe_err_port + ); + + return 0; +} + +int proc_get_int_logs(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + DBG_871X_SEL_NL(m, + "all=%d\n" + "err=%d\n" + "tbdok=%d\n" + "tbder=%d\n" + "bcnderr=%d\n" + "bcndma=%d\n" + "bcndma_e=%d\n" + "rx=%d\n" + "rx_rdu=%d\n" + "rx_fovw=%d\n" + "txfovw=%d\n" + "mgntok=%d\n" + "highdok=%d\n" + "bkdok=%d\n" + "bedok=%d\n" + "vidok=%d\n" + "vodok=%d\n", + padapter->int_logs.all, + padapter->int_logs.err, + padapter->int_logs.tbdok, + padapter->int_logs.tbder, + padapter->int_logs.bcnderr, + padapter->int_logs.bcndma, + padapter->int_logs.bcndma_e, + padapter->int_logs.rx, + padapter->int_logs.rx_rdu, + padapter->int_logs.rx_fovw, + padapter->int_logs.txfovw, + padapter->int_logs.mgntok, + padapter->int_logs.highdok, + padapter->int_logs.bkdok, + padapter->int_logs.bedok, + padapter->int_logs.vidok, + padapter->int_logs.vodok + ); + + return 0; +} + +#endif // CONFIG_DBG_COUNTER + +int proc_get_hw_status(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = padapter->dvobj; + struct debug_priv *pdbgpriv = &dvobj->drv_dbg; + + if (pdbgpriv->dbg_rx_fifo_last_overflow == 1 + && pdbgpriv->dbg_rx_fifo_curr_overflow == 1 + && pdbgpriv->dbg_rx_fifo_diff_overflow == 1 + ) { + DBG_871X_SEL_NL(m, "RX FIFO full count: no implementation\n"); + } else { + DBG_871X_SEL_NL(m, "RX FIFO full count: last_time=%llu, current_time=%llu, differential=%llu\n" + , pdbgpriv->dbg_rx_fifo_last_overflow, pdbgpriv->dbg_rx_fifo_curr_overflow, pdbgpriv->dbg_rx_fifo_diff_overflow); + } + + return 0; +} +int proc_get_trx_info_debug(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + int i; + + + /*============ tx info ============ */ + rtw_hal_get_def_var(padapter, HW_DEF_RA_INFO_DUMP, m); + + /*============ rx info ============ */ + rtw_hal_set_odm_var(padapter, HAL_ODM_RX_INFO_DUMP, m, _FALSE); + + +return 0; +} + +int proc_get_rx_signal(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + DBG_871X_SEL_NL(m, "rssi:%d\n", padapter->recvpriv.rssi); + //DBG_871X_SEL_NL(m, "rxpwdb:%d\n", padapter->recvpriv.rxpwdb); + DBG_871X_SEL_NL(m, "signal_strength:%u\n", padapter->recvpriv.signal_strength); + DBG_871X_SEL_NL(m, "signal_qual:%u\n", padapter->recvpriv.signal_qual); + + rtw_get_noise(padapter); + DBG_871X_SEL_NL(m, "noise:%d\n", padapter->recvpriv.noise); + #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA + rtw_odm_get_perpkt_rssi(m,padapter); + rtw_get_raw_rssi_info(m,padapter); + #endif + return 0; +} + +ssize_t proc_set_rx_signal(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u32 is_signal_dbg, signal_strength; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%u %u", &is_signal_dbg, &signal_strength); + + is_signal_dbg = is_signal_dbg==0?0:1; + + if(is_signal_dbg && num!=2) + return count; + + signal_strength = signal_strength>100?100:signal_strength; + + padapter->recvpriv.is_signal_dbg = is_signal_dbg; + padapter->recvpriv.signal_strength_dbg=signal_strength; + + if(is_signal_dbg) + DBG_871X("set %s %u\n", "DBG_SIGNAL_STRENGTH", signal_strength); + else + DBG_871X("set %s\n", "HW_SIGNAL_STRENGTH"); + + } + + return count; + +} +#ifdef CONFIG_80211N_HT + +int proc_get_ht_enable(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + + if(pregpriv) + DBG_871X_SEL_NL(m, "%d\n", pregpriv->ht_enable); + + return 0; +} + +ssize_t proc_set_ht_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + char tmp[32]; + u32 mode; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%d ", &mode); + + if( pregpriv && mode < 2 ) + { + pregpriv->ht_enable= mode; + DBG_871X("ht_enable=%d\n", pregpriv->ht_enable); + } + } + + return count; + +} + +int proc_get_bw_mode(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + + if(pregpriv) + DBG_871X_SEL_NL(m, "0x%02x\n", pregpriv->bw_mode); + + return 0; +} + +ssize_t proc_set_bw_mode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + char tmp[32]; + u32 mode; + u8 bw_2g; + u8 bw_5g; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%x ", &mode); + bw_5g = mode >> 4; + bw_2g = mode & 0x0f; + + if (pregpriv && bw_2g <= 4 && bw_5g <= 4) { + + pregpriv->bw_mode = mode; + printk("bw_mode=0x%x\n", mode); + + } + } + + return count; + +} + +int proc_get_ampdu_enable(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + + if(pregpriv) + DBG_871X_SEL_NL(m, "%d\n", pregpriv->ampdu_enable); + + return 0; +} + +ssize_t proc_set_ampdu_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + char tmp[32]; + u32 mode; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%d ", &mode); + + if (pregpriv && mode < 2) { + pregpriv->ampdu_enable = mode; + printk("ampdu_enable=%d\n", mode); + } + + } + + return count; + +} + +int proc_get_mac_rptbuf(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u16 i; + u16 mac_id; + u32 shcut_addr = 0; + u32 read_addr = 0; +#ifdef CONFIG_RTL8814A + DBG_871X_SEL_NL(m, "TX ShortCut:\n"); + for (mac_id = 0; mac_id < 64; mac_id++) { + rtw_write16(padapter, 0x140, 0x662 | ((mac_id & BIT5)>>5)); + shcut_addr = 0x8000; + shcut_addr = shcut_addr | ((mac_id&0x1f) << 7); + DBG_871X_SEL_NL(m, "mac_id=%d, 0x140=%x =>\n", mac_id, 0x662 | ((mac_id & BIT5)>>5)); + for (i = 0; i < 30; i++) { + read_addr = 0; + read_addr = shcut_addr | (i<<2); + DBG_871X_SEL_NL(m, "i=%02d: MAC_%04x= %08x ", i, read_addr, rtw_read32(padapter, read_addr)); + if (!((i+1) % 4)) + DBG_871X_SEL_NL(m, "\n"); + if (i == 29) + DBG_871X_SEL_NL(m, "\n"); + } + } +#endif /* CONFIG_RTL8814A */ + return 0; +} + + +int proc_get_rx_ampdu(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + DBG_871X_SEL(m, "accept: "); + if (padapter->fix_rx_ampdu_accept == RX_AMPDU_ACCEPT_INVALID) + DBG_871X_SEL_NL(m, "%u%s\n", rtw_rx_ampdu_is_accept(padapter), "(auto)"); + else + DBG_871X_SEL_NL(m, "%u%s\n", padapter->fix_rx_ampdu_accept, "(fixed)"); + + DBG_871X_SEL(m, "size: "); + if (padapter->fix_rx_ampdu_size == RX_AMPDU_SIZE_INVALID) + DBG_871X_SEL_NL(m, "%u%s\n", rtw_rx_ampdu_size(padapter), "(auto)"); + else + DBG_871X_SEL_NL(m, "%u%s\n", padapter->fix_rx_ampdu_size, "(fixed)"); + + DBG_871X_SEL_NL(m, "%19s %17s\n", "fix_rx_ampdu_accept", "fix_rx_ampdu_size"); + + DBG_871X_SEL(m, "%-19d %-17u\n" + , padapter->fix_rx_ampdu_accept + , padapter->fix_rx_ampdu_size); + + return 0; +} + +ssize_t proc_set_rx_ampdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + char tmp[32]; + u8 accept; + u8 size; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhu %hhu", &accept, &size); + + if (num >= 1) + rtw_rx_ampdu_set_accept(padapter, accept, RX_AMPDU_DRV_FIXED); + if (num >= 2) + rtw_rx_ampdu_set_size(padapter, size, RX_AMPDU_DRV_FIXED); + + rtw_rx_ampdu_apply(padapter); + } + +exit: + return count; +} +int proc_get_rx_ampdu_factor(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + + if(padapter) + { + DBG_871X_SEL_NL(m,"rx ampdu factor = %x\n",padapter->driver_rx_ampdu_factor); + } + + return 0; +} + +ssize_t proc_set_rx_ampdu_factor(struct file *file, const char __user *buffer + , size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u32 factor; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%d ", &factor); + + if( padapter && (num == 1) ) + { + DBG_871X("padapter->driver_rx_ampdu_factor = %x\n", factor); + + if(factor > 0x03) + padapter->driver_rx_ampdu_factor = 0xFF; + else + padapter->driver_rx_ampdu_factor = factor; + } + } + + return count; +} + +int proc_get_rx_ampdu_density(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + + if(padapter) + { + DBG_871X_SEL_NL(m,"rx ampdu densityg = %x\n",padapter->driver_rx_ampdu_spacing); + } + + return 0; +} + +ssize_t proc_set_rx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u32 density; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%d ", &density); + + if( padapter && (num == 1) ) + { + DBG_871X("padapter->driver_rx_ampdu_spacing = %x\n", density); + + if(density > 0x07) + padapter->driver_rx_ampdu_spacing = 0xFF; + else + padapter->driver_rx_ampdu_spacing = density; + } + } + + return count; +} + +int proc_get_tx_ampdu_density(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + + if(padapter) + { + DBG_871X_SEL_NL(m,"tx ampdu density = %x\n",padapter->driver_ampdu_spacing); + } + + return 0; +} + +ssize_t proc_set_tx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u32 density; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%d ", &density); + + if( padapter && (num == 1) ) + { + DBG_871X("padapter->driver_ampdu_spacing = %x\n", density); + + if(density > 0x07) + padapter->driver_ampdu_spacing = 0xFF; + else + padapter->driver_ampdu_spacing = density; + } + } + + return count; +} +#endif //CONFIG_80211N_HT + +int proc_get_en_fwps(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if(pregpriv) + DBG_871X_SEL_NL(m, "check_fw_ps = %d , 1:enable get FW PS state , 0: disable get FW PS state\n" + , pregpriv->check_fw_ps); + + return 0; +} + +ssize_t proc_set_en_fwps(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + char tmp[32]; + u32 mode; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%d ", &mode); + + if( pregpriv && mode < 2 ) + { + pregpriv->check_fw_ps = mode; + DBG_871X("pregpriv->check_fw_ps=%d \n",pregpriv->check_fw_ps); + } + + } + + return count; +} + +/* +int proc_get_two_path_rssi(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + if(padapter) + DBG_871X_SEL_NL(m, "%d %d\n", + padapter->recvpriv.RxRssi[0], padapter->recvpriv.RxRssi[1]); + + return 0; +} +*/ +#ifdef CONFIG_80211N_HT +int proc_get_rx_stbc(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + + if(pregpriv) + DBG_871X_SEL_NL(m, "%d\n", pregpriv->rx_stbc); + + return 0; +} + +ssize_t proc_set_rx_stbc(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + char tmp[32]; + u32 mode; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%d ", &mode); + + if( pregpriv && (mode == 0 || mode == 1|| mode == 2|| mode == 3)) + { + pregpriv->rx_stbc= mode; + printk("rx_stbc=%d\n", mode); + } + } + + return count; + +} +#endif //CONFIG_80211N_HT + +/*int proc_get_rssi_disp(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + return 0; +} +*/ + +/*ssize_t proc_set_rssi_disp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u32 enable=0; + + if (count < 1) + { + DBG_8192C("argument size is less than 1\n"); + return -EFAULT; + } + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%x", &enable); + + if (num != 1) { + DBG_8192C("invalid set_rssi_disp parameter!\n"); + return count; + } + + if(enable) + { + DBG_8192C("Linked info Function Enable\n"); + padapter->bLinkInfoDump = enable ; + } + else + { + DBG_8192C("Linked info Function Disable\n"); + padapter->bLinkInfoDump = 0 ; + } + + } + + return count; + +} + +*/ +#ifdef CONFIG_AP_MODE + +int proc_get_all_sta_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _irqL irqL; + struct sta_info *psta; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct sta_priv *pstapriv = &padapter->stapriv; + int i; + _list *plist, *phead; + + DBG_871X_SEL_NL(m, "sta_dz_bitmap=0x%x, tim_bitmap=0x%x\n", pstapriv->sta_dz_bitmap, pstapriv->tim_bitmap); + + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + for(i=0; i< NUM_STA; i++) + { + phead = &(pstapriv->sta_hash[i]); + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) + { + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + + plist = get_next(plist); + + //if(extra_arg == psta->aid) + { + DBG_871X_SEL_NL(m, "==============================\n"); + DBG_871X_SEL_NL(m, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr)); + DBG_871X_SEL_NL(m, "rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self); + DBG_871X_SEL_NL(m, "state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid); +#ifdef CONFIG_80211N_HT + DBG_871X_SEL_NL(m, "qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); + DBG_871X_SEL_NL(m, "bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n", psta->bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m); + DBG_871X_SEL_NL(m, "ampdu_enable = %d\n", psta->htpriv.ampdu_enable); + DBG_871X_SEL_NL(m, "agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); +#endif //CONFIG_80211N_HT + DBG_871X_SEL_NL(m, "sleepq_len=%d\n", psta->sleepq_len); + DBG_871X_SEL_NL(m, "sta_xmitpriv.vo_q_qcnt=%d\n", psta->sta_xmitpriv.vo_q.qcnt); + DBG_871X_SEL_NL(m, "sta_xmitpriv.vi_q_qcnt=%d\n", psta->sta_xmitpriv.vi_q.qcnt); + DBG_871X_SEL_NL(m, "sta_xmitpriv.be_q_qcnt=%d\n", psta->sta_xmitpriv.be_q.qcnt); + DBG_871X_SEL_NL(m, "sta_xmitpriv.bk_q_qcnt=%d\n", psta->sta_xmitpriv.bk_q.qcnt); + + DBG_871X_SEL_NL(m, "capability=0x%x\n", psta->capability); + DBG_871X_SEL_NL(m, "flags=0x%x\n", psta->flags); + DBG_871X_SEL_NL(m, "wpa_psk=0x%x\n", psta->wpa_psk); + DBG_871X_SEL_NL(m, "wpa2_group_cipher=0x%x\n", psta->wpa2_group_cipher); + DBG_871X_SEL_NL(m, "wpa2_pairwise_cipher=0x%x\n", psta->wpa2_pairwise_cipher); + DBG_871X_SEL_NL(m, "qos_info=0x%x\n", psta->qos_info); + DBG_871X_SEL_NL(m, "dot118021XPrivacy=0x%x\n", psta->dot118021XPrivacy); + + sta_rx_reorder_ctl_dump(m, psta); + +#ifdef CONFIG_TDLS + DBG_871X_SEL_NL(m, "tdls_sta_state=0x%08x\n", psta->tdls_sta_state); + DBG_871X_SEL_NL(m, "PeerKey_Lifetime=%d\n", psta->TDLS_PeerKey_Lifetime); + DBG_871X_SEL_NL(m, "rx_data_pkts=%llu\n", psta->sta_stats.rx_data_pkts); + DBG_871X_SEL_NL(m, "rx_bytes=%llu\n", psta->sta_stats.rx_bytes); + DBG_871X_SEL_NL(m, "tx_data_pkts=%llu\n", psta->sta_stats.tx_pkts); + DBG_871X_SEL_NL(m, "tx_bytes=%llu\n", psta->sta_stats.tx_bytes); +#endif //CONFIG_TDLS + + dump_st_ctl(m, &psta->st_ctl); + + if (STA_OP_WFD_MODE(psta)) + DBG_871X_SEL_NL(m, "op_wfd_mode:0x%02x\n", STA_OP_WFD_MODE(psta)); + + DBG_871X_SEL_NL(m, "==============================\n"); + } + + } + + } + + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + return 0; +} + +#endif + +#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER +int proc_get_rtkm_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct recv_priv *precvpriv = &padapter->recvpriv; + struct recv_buf *precvbuf; + + precvbuf = (struct recv_buf *)precvpriv->precv_buf; + + DBG_871X_SEL_NL(m, "============[RTKM Info]============\n"); + DBG_871X_SEL_NL(m, "MAX_RTKM_NR_PREALLOC_RECV_SKB: %d\n", rtw_rtkm_get_nr_recv_skb()); + DBG_871X_SEL_NL(m, "MAX_RTKM_RECVBUF_SZ: %d\n", rtw_rtkm_get_buff_size()); + + DBG_871X_SEL_NL(m, "============[Driver Info]============\n"); + DBG_871X_SEL_NL(m, "NR_PREALLOC_RECV_SKB: %d\n", NR_PREALLOC_RECV_SKB); + DBG_871X_SEL_NL(m, "MAX_RECVBUF_SZ: %d\n", precvbuf->alloc_sz); + + return 0; +} +#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */ + +#ifdef DBG_MEMORY_LEAK +#include +extern atomic_t _malloc_cnt;; +extern atomic_t _malloc_size;; + +int proc_get_malloc_cnt(struct seq_file *m, void *v) +{ + DBG_871X_SEL_NL(m, "_malloc_cnt=%d\n", atomic_read(&_malloc_cnt)); + DBG_871X_SEL_NL(m, "_malloc_size=%d\n", atomic_read(&_malloc_size)); + + return 0; +} +#endif /* DBG_MEMORY_LEAK */ + +#ifdef CONFIG_FIND_BEST_CHANNEL +int proc_get_best_channel(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + u32 i, best_channel_24G = 1, best_channel_5G = 36, index_24G = 0, index_5G = 0; + + for (i=0; pmlmeext->channel_set[i].ChannelNum !=0; i++) { + if ( pmlmeext->channel_set[i].ChannelNum == 1) + index_24G = i; + if ( pmlmeext->channel_set[i].ChannelNum == 36) + index_5G = i; + } + + for (i=0; (i < MAX_CHANNEL_NUM) && (pmlmeext->channel_set[i].ChannelNum !=0) ; i++) { + // 2.4G + if ( pmlmeext->channel_set[i].ChannelNum == 6 ) { + if ( pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_24G].rx_count ) { + index_24G = i; + best_channel_24G = pmlmeext->channel_set[i].ChannelNum; + } + } + + // 5G + if ( pmlmeext->channel_set[i].ChannelNum >= 36 + && pmlmeext->channel_set[i].ChannelNum < 140 ) { + // Find primary channel + if ( (( pmlmeext->channel_set[i].ChannelNum - 36) % 8 == 0) + && (pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_5G].rx_count) ) { + index_5G = i; + best_channel_5G = pmlmeext->channel_set[i].ChannelNum; + } + } + + if ( pmlmeext->channel_set[i].ChannelNum >= 149 + && pmlmeext->channel_set[i].ChannelNum < 165) { + // find primary channel + if ( (( pmlmeext->channel_set[i].ChannelNum - 149) % 8 == 0) + && (pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_5G].rx_count) ) { + index_5G = i; + best_channel_5G = pmlmeext->channel_set[i].ChannelNum; + } + } +#if 1 // debug + DBG_871X_SEL_NL(m, "The rx cnt of channel %3d = %d\n", + pmlmeext->channel_set[i].ChannelNum, pmlmeext->channel_set[i].rx_count); +#endif + } + + DBG_871X_SEL_NL(m, "best_channel_5G = %d\n", best_channel_5G); + DBG_871X_SEL_NL(m, "best_channel_24G = %d\n", best_channel_24G); + + return 0; +} + +ssize_t proc_set_best_channel(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + char tmp[32]; + + if(count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + int i; + for(i = 0; pmlmeext->channel_set[i].ChannelNum != 0; i++) + { + pmlmeext->channel_set[i].rx_count = 0; + } + + DBG_871X("set %s\n", "Clean Best Channel Count"); + } + + return count; +} +#endif /* CONFIG_FIND_BEST_CHANNEL */ + +#ifdef CONFIG_BT_COEXIST +int proc_get_btcoex_dbg(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + PADAPTER padapter; + char buf[512] = {0}; + padapter = (PADAPTER)rtw_netdev_priv(dev); + + rtw_btcoex_GetDBG(padapter, buf, 512); + + DBG_871X_SEL(m, "%s", buf); + + return 0; +} + +ssize_t proc_set_btcoex_dbg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + PADAPTER padapter; + u8 tmp[80] = {0}; + u32 module[2] = {0}; + u32 num; + + padapter = (PADAPTER)rtw_netdev_priv(dev); + +// DBG_871X("+" FUNC_ADPT_FMT "\n", FUNC_ADPT_ARG(padapter)); + + if (NULL == buffer) + { + DBG_871X(FUNC_ADPT_FMT ": input buffer is NULL!\n", + FUNC_ADPT_ARG(padapter)); + + return -EFAULT; + } + + if (count < 1) + { + DBG_871X(FUNC_ADPT_FMT ": input length is 0!\n", + FUNC_ADPT_ARG(padapter)); + + return -EFAULT; + } + + num = count; + if (num > (sizeof(tmp) - 1)) + num = (sizeof(tmp) - 1); + + if (copy_from_user(tmp, buffer, num)) + { + DBG_871X(FUNC_ADPT_FMT ": copy buffer from user space FAIL!\n", + FUNC_ADPT_ARG(padapter)); + + return -EFAULT; + } + + num = sscanf(tmp, "%x %x", module, module+1); + if (1 == num) + { + if (0 == module[0]) + _rtw_memset(module, 0, sizeof(module)); + else + _rtw_memset(module, 0xFF, sizeof(module)); + } + else if (2 != num) + { + DBG_871X(FUNC_ADPT_FMT ": input(\"%s\") format incorrect!\n", + FUNC_ADPT_ARG(padapter), tmp); + + if (0 == num) + return -EFAULT; + } + + DBG_871X(FUNC_ADPT_FMT ": input 0x%08X 0x%08X\n", + FUNC_ADPT_ARG(padapter), module[0], module[1]); + rtw_btcoex_SetDBG(padapter, module); + + return count; +} + +int proc_get_btcoex_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + PADAPTER padapter; + const u32 bufsize = 30*100; + u8 *pbuf = NULL; + + padapter = (PADAPTER)rtw_netdev_priv(dev); + + pbuf = rtw_zmalloc(bufsize); + if (NULL == pbuf) { + return -ENOMEM; + } + + rtw_btcoex_DisplayBtCoexInfo(padapter, pbuf, bufsize); + + DBG_871X_SEL(m, "%s\n", pbuf); + + rtw_mfree(pbuf, bufsize); + + return 0; +} +#endif /* CONFIG_BT_COEXIST */ + +#if defined(DBG_CONFIG_ERROR_DETECT) +int proc_get_sreset(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + return 0; +} + +ssize_t proc_set_sreset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + s32 trigger_point; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%d", &trigger_point); + + if (trigger_point == SRESET_TGP_NULL) + rtw_hal_sreset_reset(padapter); + else + sreset_set_trigger_point(padapter, trigger_point); + } + + return count; + +} +#endif /* DBG_CONFIG_ERROR_DETECT */ + +#ifdef CONFIG_PCI_HCI + +int proc_get_rx_ring(struct seq_file *m, void *v) +{ + _irqL irqL; + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *) rtw_netdev_priv(dev); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct recv_priv *precvpriv = &padapter->recvpriv; + struct rtw_rx_ring *rx_ring = &precvpriv->rx_ring[RX_MPDU_QUEUE]; + int i, j; + + DBG_871X_SEL_NL(m, "rx ring (%p)\n", rx_ring); + DBG_871X_SEL_NL(m, " dma: 0x%08x\n", (int) rx_ring->dma); + DBG_871X_SEL_NL(m, " idx: %d\n", rx_ring->idx); + + _enter_critical(&pdvobjpriv->irq_th_lock, &irqL); + for (i=0; irxringcount; i++) + { + struct recv_stat *entry = &rx_ring->desc[i]; + struct sk_buff *skb = rx_ring->rx_buf[i]; + + DBG_871X_SEL_NL(m, " desc[%03d]: %p, rx_buf[%03d]: 0x%08x\n", + i, entry, i, cpu_to_le32(*((dma_addr_t *)skb->cb))); + + for (j=0; jirq_th_lock, &irqL); + + return 0; +} + +int proc_get_tx_ring(struct seq_file *m, void *v) +{ + _irqL irqL; + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *) rtw_netdev_priv(dev); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + int i, j, k; + + _enter_critical(&pdvobjpriv->irq_th_lock, &irqL); + for (i = 0; i < PCI_MAX_TX_QUEUE_COUNT; i++) + { + struct rtw_tx_ring *tx_ring = &pxmitpriv->tx_ring[i]; + + DBG_871X_SEL_NL(m, "tx ring[%d] (%p)\n", i, tx_ring); + DBG_871X_SEL_NL(m, " dma: 0x%08x\n", (int) tx_ring->dma); + DBG_871X_SEL_NL(m, " idx: %d\n", tx_ring->idx); + DBG_871X_SEL_NL(m, " entries: %d\n", tx_ring->entries); +// DBG_871X_SEL_NL(m, " queue: %d\n", tx_ring->queue); + DBG_871X_SEL_NL(m, " qlen: %d\n", tx_ring->qlen); + + for (j=0; j < pxmitpriv->txringcount[i]; j++) + { + struct tx_desc *entry = &tx_ring->desc[j]; + + DBG_871X_SEL_NL(m, " desc[%03d]: %p\n", j, entry); + for (k=0; k < sizeof(*entry)/4; k++) + { + if ((k % 4) == 0) + DBG_871X_SEL_NL(m, " 0x%03x", k); + + DBG_871X_SEL_NL(m, " 0x%08x ", ((int *) entry)[k]); + + if ((k % 4) == 3) + DBG_871X_SEL_NL(m, "\n"); + } + } + } + _exit_critical(&pdvobjpriv->irq_th_lock, &irqL); + + return 0; +} +#endif + +#ifdef CONFIG_GPIO_WAKEUP +int proc_get_wowlan_gpio_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + u8 val = pwrpriv->is_high_active; + + DBG_871X_SEL_NL(m, "wakeup_gpio_idx: %d\n", WAKEUP_GPIO_IDX); + DBG_871X_SEL_NL(m, "high_active: %d\n", val); + + return 0; +} + +ssize_t proc_set_wowlan_gpio_info(struct file *file, const char __user *buffer, + size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + char tmp[32] = {0}; + int num = 0; + u32 is_high_active = 0; + u8 val8 = 0; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + num = sscanf(tmp, "%u", &is_high_active); + + is_high_active = is_high_active == 0 ? 0 : 1; + + pwrpriv->is_high_active = is_high_active; + + rtw_ps_deny(padapter, PS_DENY_IOCTL); + LeaveAllPowerSaveModeDirect(padapter); + val8 = (pwrpriv->is_high_active == 0) ? 1 : 0; + rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, val8); + rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL); + + DBG_871X("set %s %d\n", "gpio_high_active", + pwrpriv->is_high_active); + DBG_871X("%s: set GPIO_%d %d as default.\n", + __func__, WAKEUP_GPIO_IDX, val8); + } + + return count; +} +#endif /* CONFIG_GPIO_WAKEUP */ + +int proc_get_new_bcn_max(struct seq_file *m, void *v) +{ + extern int new_bcn_max; + + DBG_871X_SEL_NL(m, "%d", new_bcn_max); + return 0; +} + +ssize_t proc_set_new_bcn_max(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + char tmp[32]; + extern int new_bcn_max; + + if(count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) + sscanf(tmp, "%d ", &new_bcn_max); + + return count; +} + +#ifdef CONFIG_POWER_SAVING +int proc_get_ps_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + u8 ips_mode = pwrpriv->ips_mode; + u8 lps_mode = pwrpriv->power_mgnt; + char *str = ""; + + DBG_871X_SEL_NL(m, "======Power Saving Info:======\n"); + DBG_871X_SEL_NL(m, "*IPS:\n"); + + if (ips_mode == IPS_NORMAL) { +#ifdef CONFIG_FWLPS_IN_IPS + str = "FW_LPS_IN_IPS"; +#else + str = "Card Disable"; +#endif + } else if (ips_mode == IPS_NONE) { + str = "NO IPS"; + } else if (ips_mode == IPS_LEVEL_2) { + str = "IPS_LEVEL_2"; + } else { + str = "invalid ips_mode"; + } + + DBG_871X_SEL_NL(m, " IPS mode: %s\n", str); + DBG_871X_SEL_NL(m, " IPS enter count:%d, IPS leave count:%d\n", + pwrpriv->ips_enter_cnts, pwrpriv->ips_leave_cnts); + DBG_871X_SEL_NL(m, "------------------------------\n"); + DBG_871X_SEL_NL(m, "*LPS:\n"); + + if (lps_mode == PS_MODE_ACTIVE) { + str = "NO LPS"; + } else if (lps_mode == PS_MODE_MIN) { + str = "MIN"; + } else if (lps_mode == PS_MODE_MAX) { + str = "MAX"; + } else if (lps_mode == PS_MODE_DTIM) { + str = "DTIM"; + } else { + sprintf(str, "%d", lps_mode); + } + + DBG_871X_SEL_NL(m, " LPS mode: %s\n", str); + + if (pwrpriv->dtim != 0) + DBG_871X_SEL_NL(m, " DTIM: %d\n", pwrpriv->dtim); + DBG_871X_SEL_NL(m, " LPS enter count:%d, LPS leave count:%d\n", + pwrpriv->lps_enter_cnts, pwrpriv->lps_leave_cnts); + DBG_871X_SEL_NL(m, "=============================\n"); + return 0; +} +#endif //CONFIG_POWER_SAVING + +#ifdef CONFIG_TDLS +static int proc_tdls_display_tdls_function_info(struct seq_file *m) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + u8 SpaceBtwnItemAndValue = TDLS_DBG_INFO_SPACE_BTWN_ITEM_AND_VALUE; + u8 SpaceBtwnItemAndValueTmp = 0; + BOOLEAN FirstMatchFound = _FALSE; + int j= 0; + + DBG_871X_SEL_NL(m, "============[TDLS Function Info]============\n"); + DBG_871X_SEL_NL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Prohibited", (ptdlsinfo->ap_prohibited == _TRUE) ? "_TRUE" : "_FALSE"); + DBG_871X_SEL_NL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Channel Switch Prohibited", (ptdlsinfo->ch_switch_prohibited == _TRUE) ? "_TRUE" : "_FALSE"); + DBG_871X_SEL_NL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Link Established", (ptdlsinfo->link_established == _TRUE) ? "_TRUE" : "_FALSE"); + DBG_871X_SEL_NL(m, "%-*s = %d/%d\n", SpaceBtwnItemAndValue, "TDLS STA Num (Linked/Allowed)", ptdlsinfo->sta_cnt, MAX_ALLOWED_TDLS_STA_NUM); + DBG_871X_SEL_NL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Allowed STA Num Reached", (ptdlsinfo->sta_maximum == _TRUE) ? "_TRUE" : "_FALSE"); + +#ifdef CONFIG_TDLS_CH_SW + DBG_871X_SEL_NL(m, "%-*s =", SpaceBtwnItemAndValue, "TDLS CH SW State"); + if (ptdlsinfo->chsw_info.ch_sw_state == TDLS_STATE_NONE) + { + DBG_871X_SEL_NL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_STATE_NONE"); + } + else + { + for (j = 0; j < 32; j++) + { + if (ptdlsinfo->chsw_info.ch_sw_state & BIT(j)) + { + if (FirstMatchFound == _FALSE) + { + SpaceBtwnItemAndValueTmp = 1; + FirstMatchFound = _TRUE; + } + else + { + SpaceBtwnItemAndValueTmp = SpaceBtwnItemAndValue + 3; + } + switch (BIT(j)) + { + case TDLS_INITIATOR_STATE: + DBG_871X_SEL_NL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_INITIATOR_STATE"); + break; + case TDLS_RESPONDER_STATE: + DBG_871X_SEL_NL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_RESPONDER_STATE"); + break; + case TDLS_LINKED_STATE: + DBG_871X_SEL_NL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_LINKED_STATE"); + break; + case TDLS_WAIT_PTR_STATE: + DBG_871X_SEL_NL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_WAIT_PTR_STATE"); + break; + case TDLS_ALIVE_STATE: + DBG_871X_SEL_NL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_ALIVE_STATE"); + break; + case TDLS_CH_SWITCH_ON_STATE: + DBG_871X_SEL_NL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_CH_SWITCH_ON_STATE"); + break; + case TDLS_PEER_AT_OFF_STATE: + DBG_871X_SEL_NL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_PEER_AT_OFF_STATE"); + break; + case TDLS_CH_SW_INITIATOR_STATE: + DBG_871X_SEL_NL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_CH_SW_INITIATOR_STATE"); + break; + case TDLS_WAIT_CH_RSP_STATE: + DBG_871X_SEL_NL(m, "%-*s%s\n", SpaceBtwnItemAndValue, " ", "TDLS_WAIT_CH_RSP_STATE"); + break; + default: + DBG_871X_SEL_NL(m, "%-*sBIT(%d)\n", SpaceBtwnItemAndValueTmp, " ", j); + break; + } + } + } + } + + DBG_871X_SEL_NL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS CH SW On", (ATOMIC_READ(&ptdlsinfo->chsw_info.chsw_on) == _TRUE) ? "_TRUE" : "_FALSE"); + DBG_871X_SEL_NL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "TDLS CH SW Off-Channel Num", ptdlsinfo->chsw_info.off_ch_num); + DBG_871X_SEL_NL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "TDLS CH SW Channel Offset", ptdlsinfo->chsw_info.ch_offset); + DBG_871X_SEL_NL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "TDLS CH SW Current Time", ptdlsinfo->chsw_info.cur_time); + DBG_871X_SEL_NL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS CH SW Delay Switch Back", (ptdlsinfo->chsw_info.delay_switch_back == _TRUE) ? "_TRUE" : "_FALSE"); + DBG_871X_SEL_NL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "TDLS CH SW Dump Back", ptdlsinfo->chsw_info.dump_stack); +#endif + + DBG_871X_SEL_NL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Device Discovered", (ptdlsinfo->dev_discovered == _TRUE) ? "_TRUE" : "_FALSE"); + DBG_871X_SEL_NL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Enable", (ptdlsinfo->tdls_enable == _TRUE) ? "_TRUE" : "_FALSE"); + DBG_871X_SEL_NL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "TDLS Driver Setup", (ptdlsinfo->driver_setup == _TRUE) ? "_TRUE" : "_FALSE"); + + return 0; +} + +static int proc_tdls_display_network_info(struct seq_file *m) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct wlan_network *cur_network = &(pmlmepriv->cur_network); + int i = 0; + u8 SpaceBtwnItemAndValue = TDLS_DBG_INFO_SPACE_BTWN_ITEM_AND_VALUE; + + /* Display the linked AP/GO info */ + DBG_871X_SEL_NL(m, "============[Associated AP/GO Info]============\n"); + + if ((pmlmepriv->fw_state & WIFI_STATION_STATE) && (pmlmepriv->fw_state & _FW_LINKED)) + { + DBG_871X_SEL_NL(m, "%-*s = %s\n", SpaceBtwnItemAndValue, "BSSID", cur_network->network.Ssid.Ssid); + DBG_871X_SEL_NL(m, "%-*s = "MAC_FMT"\n", SpaceBtwnItemAndValue, "Mac Address", MAC_ARG(cur_network->network.MacAddress)); + + DBG_871X_SEL_NL(m, "%-*s = ", SpaceBtwnItemAndValue, "Wireless Mode"); + for (i = 0; i < 8; i++) + { + if (pmlmeext->cur_wireless_mode & BIT(i)) + { + switch (BIT(i)) + { + case WIRELESS_11B: + DBG_871X_SEL_NL(m, "%4s", "11B "); + break; + case WIRELESS_11G: + DBG_871X_SEL_NL(m, "%4s", "11G "); + break; + case WIRELESS_11A: + DBG_871X_SEL_NL(m, "%4s", "11A "); + break; + case WIRELESS_11_24N: + DBG_871X_SEL_NL(m, "%7s", "11_24N "); + break; + case WIRELESS_11_5N: + DBG_871X_SEL_NL(m, "%6s", "11_5N "); + break; + case WIRELESS_AUTO: + DBG_871X_SEL_NL(m, "%5s", "AUTO "); + break; + case WIRELESS_11AC: + DBG_871X_SEL_NL(m, "%5s", "11AC "); + break; + } + } + } + DBG_871X_SEL_NL(m, "\n"); + + DBG_871X_SEL_NL(m, "%-*s = ", SpaceBtwnItemAndValue, "Privacy"); + switch (padapter->securitypriv.dot11PrivacyAlgrthm) + { + case _NO_PRIVACY_: + DBG_871X_SEL_NL(m, "%s\n", "NO PRIVACY"); + break; + case _WEP40_: + DBG_871X_SEL_NL(m, "%s\n", "WEP 40"); + break; + case _TKIP_: + DBG_871X_SEL_NL(m, "%s\n", "TKIP"); + break; + case _TKIP_WTMIC_: + DBG_871X_SEL_NL(m, "%s\n", "TKIP WTMIC"); + break; + case _AES_: + DBG_871X_SEL_NL(m, "%s\n", "AES"); + break; + case _WEP104_: + DBG_871X_SEL_NL(m, "%s\n", "WEP 104"); + break; + case _WEP_WPA_MIXED_: + DBG_871X_SEL_NL(m, "%s\n", "WEP/WPA Mixed"); + break; + case _SMS4_: + DBG_871X_SEL_NL(m, "%s\n", "SMS4"); + break; +#ifdef CONFIG_IEEE80211W + case _BIP_: + DBG_871X_SEL_NL(m, "%s\n", "BIP"); + break; +#endif //CONFIG_IEEE80211W + } + + DBG_871X_SEL_NL(m, "%-*s = %d\n", SpaceBtwnItemAndValue, "Channel", pmlmeext->cur_channel); + DBG_871X_SEL_NL(m, "%-*s = ", SpaceBtwnItemAndValue, "Channel Offset"); + switch (pmlmeext->cur_ch_offset) + { + case HAL_PRIME_CHNL_OFFSET_DONT_CARE: + DBG_871X_SEL_NL(m, "%s\n", "N/A"); + break; + case HAL_PRIME_CHNL_OFFSET_LOWER: + DBG_871X_SEL_NL(m, "%s\n", "Lower"); + break; + case HAL_PRIME_CHNL_OFFSET_UPPER: + DBG_871X_SEL_NL(m, "%s\n", "Upper"); + break; + } + + DBG_871X_SEL_NL(m, "%-*s = ", SpaceBtwnItemAndValue, "Bandwidth Mode"); + switch (pmlmeext->cur_bwmode) + { + case CHANNEL_WIDTH_20: + DBG_871X_SEL_NL(m, "%s\n", "20MHz"); + break; + case CHANNEL_WIDTH_40: + DBG_871X_SEL_NL(m, "%s\n", "40MHz"); + break; + case CHANNEL_WIDTH_80: + DBG_871X_SEL_NL(m, "%s\n", "80MHz"); + break; + case CHANNEL_WIDTH_160: + DBG_871X_SEL_NL(m, "%s\n", "160MHz"); + break; + case CHANNEL_WIDTH_80_80: + DBG_871X_SEL_NL(m, "%s\n", "80MHz + 80MHz"); + break; + } + } + else + { + DBG_871X_SEL_NL(m, "No association with AP/GO exists!\n"); + } + + return 0; +} + +static int proc_tdls_display_tdls_sta_info(struct seq_file *m) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct sta_priv *pstapriv = &padapter->stapriv; + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + struct sta_info *psta; + int i = 0, j = 0; + _irqL irqL; + _list *plist, *phead; + u8 SpaceBtwnItemAndValue = TDLS_DBG_INFO_SPACE_BTWN_ITEM_AND_VALUE; + u8 SpaceBtwnItemAndValueTmp = 0; + u8 NumOfTdlsStaToShow = 0; + BOOLEAN FirstMatchFound = _FALSE; + + /* Search for TDLS sta info to display */ + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + for (i=0; i< NUM_STA; i++) + { + phead = &(pstapriv->sta_hash[i]); + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) + { + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + plist = get_next(plist); + if (psta->tdls_sta_state != TDLS_STATE_NONE) + { + /* We got one TDLS sta info to show */ + DBG_871X_SEL_NL(m, "============[TDLS Peer STA Info: STA %d]============\n", ++NumOfTdlsStaToShow); + DBG_871X_SEL_NL(m, "%-*s = "MAC_FMT"\n", SpaceBtwnItemAndValue, "Mac Address", MAC_ARG(psta->hwaddr)); + DBG_871X_SEL_NL(m, "%-*s =", SpaceBtwnItemAndValue, "TDLS STA State"); + SpaceBtwnItemAndValueTmp = 0; + FirstMatchFound = _FALSE; + for (j = 0; j < 32; j++) + { + if (psta->tdls_sta_state & BIT(j)) + { + if (FirstMatchFound == _FALSE) + { + SpaceBtwnItemAndValueTmp = 1; + FirstMatchFound = _TRUE; + } + else + { + SpaceBtwnItemAndValueTmp = SpaceBtwnItemAndValue + 3; + } + switch (BIT(j)) + { + case TDLS_INITIATOR_STATE: + DBG_871X_SEL_NL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_INITIATOR_STATE"); + break; + case TDLS_RESPONDER_STATE: + DBG_871X_SEL_NL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_RESPONDER_STATE"); + break; + case TDLS_LINKED_STATE: + DBG_871X_SEL_NL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_LINKED_STATE"); + break; + case TDLS_WAIT_PTR_STATE: + DBG_871X_SEL_NL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_WAIT_PTR_STATE"); + break; + case TDLS_ALIVE_STATE: + DBG_871X_SEL_NL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_ALIVE_STATE"); + break; + case TDLS_CH_SWITCH_ON_STATE: + DBG_871X_SEL_NL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_CH_SWITCH_ON_STATE"); + break; + case TDLS_PEER_AT_OFF_STATE: + DBG_871X_SEL_NL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_PEER_AT_OFF_STATE"); + break; + case TDLS_CH_SW_INITIATOR_STATE: + DBG_871X_SEL_NL(m, "%-*s%s\n", SpaceBtwnItemAndValueTmp, " ", "TDLS_CH_SW_INITIATOR_STATE"); + break; + case TDLS_WAIT_CH_RSP_STATE: + DBG_871X_SEL_NL(m, "%-*s%s\n", SpaceBtwnItemAndValue, " ", "TDLS_WAIT_CH_RSP_STATE"); + break; + default: + DBG_871X_SEL_NL(m, "%-*sBIT(%d)\n", SpaceBtwnItemAndValueTmp, " ", j); + break; + } + } + } + + DBG_871X_SEL_NL(m, "%-*s = ", SpaceBtwnItemAndValue, "Wireless Mode"); + for (j = 0; j < 8; j++) + { + if (psta->wireless_mode & BIT(j)) + { + switch (BIT(j)) + { + case WIRELESS_11B: + DBG_871X_SEL_NL(m, "%4s", "11B "); + break; + case WIRELESS_11G: + DBG_871X_SEL_NL(m, "%4s", "11G "); + break; + case WIRELESS_11A: + DBG_871X_SEL_NL(m, "%4s", "11A "); + break; + case WIRELESS_11_24N: + DBG_871X_SEL_NL(m, "%7s", "11_24N "); + break; + case WIRELESS_11_5N: + DBG_871X_SEL_NL(m, "%6s", "11_5N "); + break; + case WIRELESS_AUTO: + DBG_871X_SEL_NL(m, "%5s", "AUTO "); + break; + case WIRELESS_11AC: + DBG_871X_SEL_NL(m, "%5s", "11AC "); + break; + } + } + } + DBG_871X_SEL_NL(m, "\n"); + + DBG_871X_SEL_NL(m, "%-*s = ", SpaceBtwnItemAndValue, "Bandwidth Mode"); + switch (psta->bw_mode) + { + case CHANNEL_WIDTH_20: + DBG_871X_SEL_NL(m, "%s\n", "20MHz"); + break; + case CHANNEL_WIDTH_40: + DBG_871X_SEL_NL(m, "%s\n", "40MHz"); + break; + case CHANNEL_WIDTH_80: + DBG_871X_SEL_NL(m, "%s\n", "80MHz"); + break; + case CHANNEL_WIDTH_160: + DBG_871X_SEL_NL(m, "%s\n", "160MHz"); + break; + case CHANNEL_WIDTH_80_80: + DBG_871X_SEL_NL(m, "%s\n", "80MHz + 80MHz"); + break; + } + + DBG_871X_SEL_NL(m, "%-*s = ", SpaceBtwnItemAndValue, "Privacy"); + switch (psta->dot118021XPrivacy) + { + case _NO_PRIVACY_: + DBG_871X_SEL_NL(m, "%s\n", "NO PRIVACY"); + break; + case _WEP40_: + DBG_871X_SEL_NL(m, "%s\n", "WEP 40"); + break; + case _TKIP_: + DBG_871X_SEL_NL(m, "%s\n", "TKIP"); + break; + case _TKIP_WTMIC_: + DBG_871X_SEL_NL(m, "%s\n", "TKIP WTMIC"); + break; + case _AES_: + DBG_871X_SEL_NL(m, "%s\n", "AES"); + break; + case _WEP104_: + DBG_871X_SEL_NL(m, "%s\n", "WEP 104"); + break; + case _WEP_WPA_MIXED_: + DBG_871X_SEL_NL(m, "%s\n", "WEP/WPA Mixed"); + break; + case _SMS4_: + DBG_871X_SEL_NL(m, "%s\n", "SMS4"); + break; +#ifdef CONFIG_IEEE80211W + case _BIP_: + DBG_871X_SEL_NL(m, "%s\n", "BIP"); + break; +#endif //CONFIG_IEEE80211W + } + + DBG_871X_SEL_NL(m, "%-*s = %d sec/%d sec\n", SpaceBtwnItemAndValue, "TPK Lifetime (Current/Expire)", psta->TPK_count, psta->TDLS_PeerKey_Lifetime); + DBG_871X_SEL_NL(m, "%-*s = %llu\n", SpaceBtwnItemAndValue, "Tx Packets Over Direct Link", psta->sta_stats.tx_pkts); + DBG_871X_SEL_NL(m, "%-*s = %llu\n", SpaceBtwnItemAndValue, "Rx Packets Over Direct Link", psta->sta_stats.rx_data_pkts); + } + } + } + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + if (NumOfTdlsStaToShow == 0) + { + DBG_871X_SEL_NL(m, "============[TDLS Peer STA Info]============\n"); + DBG_871X_SEL_NL(m, "No TDLS direct link exists!\n"); + } + + return 0; +} + +int proc_get_tdls_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct wlan_network *cur_network = &(pmlmepriv->cur_network); + struct sta_priv *pstapriv = &padapter->stapriv; + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + struct sta_info *psta; + int i = 0, j = 0; + _irqL irqL; + _list *plist, *phead; + u8 SpaceBtwnItemAndValue = 41; + u8 SpaceBtwnItemAndValueTmp = 0; + u8 NumOfTdlsStaToShow = 0; + BOOLEAN FirstMatchFound = _FALSE; + + if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) { + DBG_871X_SEL_NL(m, "No tdls info can be shown since hal doesn't support tdls\n"); + return 0; + } + + proc_tdls_display_tdls_function_info(m); + proc_tdls_display_network_info(m); + proc_tdls_display_tdls_sta_info(m); + + return 0; +} +#endif + +int proc_get_monitor(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + if (WIFI_MONITOR_STATE == get_fwstate(pmlmepriv)) { + DBG_871X_SEL_NL(m, "Monitor mode : Enable\n"); + + DBG_871X_SEL_NL(m, "ch=%d, ch_offset=%d, bw=%d\n", + rtw_get_oper_ch(padapter), rtw_get_oper_choffset(padapter), rtw_get_oper_bw(padapter)); + } else { + DBG_871X_SEL_NL(m, "Monitor mode : Disable\n"); + } + + return 0; +} + +ssize_t proc_set_monitor(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + char tmp[32]; + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u8 target_chan, target_offset, target_bw; + + if (count < 3) { + DBG_871X("argument size is less than 3\n"); + return -EFAULT; + } + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + int num = sscanf(tmp, "%hhu %hhu %hhu", &target_chan, &target_offset, &target_bw); + + if (num != 3) { + DBG_871X("invalid write_reg parameter!\n"); + return count; + } + + padapter->mlmeextpriv.cur_channel = target_chan; + set_channel_bwmode(padapter, target_chan, target_offset, target_bw); + } + + return count; +} + +#include +int proc_get_efuse_map(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; + int i, j; + u8 ips_mode = IPS_NUM; + int mapLen = EFUSE_MAP_SIZE; + + ips_mode = pwrctrlpriv->ips_mode; + rtw_pm_set_ips(padapter, IPS_NONE); + if (rtw_efuse_map_read(padapter, EFUSE_WIFI, mapLen, pEfuseHal->fakeEfuseInitMap) == _FAIL) + DBG_871X_SEL_NL(m, "WARN - Read Realmap Failed\n"); + + DBG_871X_SEL_NL(m, "\n"); + for (i = 0; i < EFUSE_MAP_SIZE; i += 16) { + DBG_871X_SEL_NL(m, "0x%02x\t", i); + for (j = 0; j < 8; j++) + DBG_871X_SEL_NL(m, "%02X ", pEfuseHal->fakeEfuseInitMap[i+j]); + + DBG_871X_SEL_NL(m, "\t"); + + for (; j < 16; j++) + DBG_871X_SEL_NL(m, "%02X ", pEfuseHal->fakeEfuseInitMap[i+j]); + + DBG_871X_SEL_NL(m, "\n"); + + } + rtw_pm_set_ips(padapter, ips_mode); + return 0; +} + +ssize_t proc_set_efuse_map(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ +#if 0 + char tmp[256] = {0}; + u32 addr, cnts; + u8 efuse_data; + + int jj, kk; + + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + u8 ips_mode = IPS_NUM; + + if (count < 3) { + DBG_871X("argument size is less than 3\n"); + return -EFAULT; + } + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%x %d %x", &addr, &cnts, &efuse_data); + + if (num != 3) { + DBG_871X("invalid write_reg parameter!\n"); + return count; + } + } + ips_mode = pwrctrlpriv->ips_mode; + rtw_pm_set_ips(padapter, IPS_NONE); + if (rtw_efuse_map_write(padapter, addr, cnts, &efuse_data) == _FAIL) + DBG_871X("WARN - rtw_efuse_map_write error!!\n"); + rtw_pm_set_ips(padapter, ips_mode); +#endif + return count; +} + +#ifdef CONFIG_IEEE80211W +ssize_t proc_set_tx_sa_query(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sta_priv *pstapriv = &padapter->stapriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + struct sta_info *psta; + _list *plist, *phead; + _irqL irqL; + char tmp[16]; + u8 mac_addr[NUM_STA][ETH_ALEN]; + u32 key_type; + u8 index; + + if (count > 2) { + DBG_871X("argument size is more than 2\n"); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) { + + int num = sscanf(tmp, "%x", &key_type); + + if (num != 1) { + DBG_871X("invalid read_reg parameter!\n"); + return count; + } + DBG_871X("0: set sa query request , key_type=%d\n", key_type); + } + + if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) + && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) && padapter->securitypriv.binstallBIPkey == _TRUE) { + DBG_871X("STA:"MAC_FMT"\n", MAC_ARG(get_my_bssid(&(pmlmeinfo->network)))); + /* TX unicast sa_query to AP */ + issue_action_SA_Query(padapter, get_my_bssid(&(pmlmeinfo->network)), 0, 0, (u8)key_type); + } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE && padapter->securitypriv.binstallBIPkey == _TRUE) { + /* TX unicast sa_query to every client STA */ + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + for (index = 0; index < NUM_STA; index++) { + psta = NULL; + + phead = &(pstapriv->sta_hash[index]); + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + plist = get_next(plist); + _rtw_memcpy(&mac_addr[psta->mac_id][0], psta->hwaddr, ETH_ALEN); + } + } + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + for (index = 0; index < macid_ctl->num && index < NUM_STA; index++) { + if (rtw_macid_is_used(macid_ctl, index) && !rtw_macid_is_bmc(macid_ctl, index)) { + if (!_rtw_memcmp(get_my_bssid(&(pmlmeinfo->network)), &mac_addr[index][0], ETH_ALEN) + && !IS_MCAST(&mac_addr[index][0])) { + issue_action_SA_Query(padapter, &mac_addr[index][0], 0, 0, (u8)key_type); + DBG_871X("STA[%u]:"MAC_FMT"\n", index , MAC_ARG(&mac_addr[index][0])); + } + } + } + } + + return count; +} + +int proc_get_tx_sa_query(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + DBG_871X_SEL_NL(m, "%s\n", __func__); + return 0; +} + +ssize_t proc_set_tx_deauth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sta_priv *pstapriv = &padapter->stapriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + struct sta_info *psta; + _list *plist, *phead; + _irqL irqL; + char tmp[16]; + u8 mac_addr[NUM_STA][ETH_ALEN]; + u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + u32 key_type; + u8 index; + + + if (count > 2) { + DBG_871X("argument size is more than 2\n"); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) { + + int num = sscanf(tmp, "%x", &key_type); + + if (num != 1) { + DBG_871X("invalid read_reg parameter!\n"); + return count; + } + DBG_871X("key_type=%d\n", key_type); + } + if (key_type < 0 || key_type > 4) + return count; + + if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) + && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) { + if (key_type == 3) /* key_type 3 only for AP mode */ + return count; + /* TX unicast deauth to AP */ + issue_deauth_11w(padapter, get_my_bssid(&(pmlmeinfo->network)), 0, (u8)key_type); + } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { + + if (key_type == 3) + issue_deauth_11w(padapter, bc_addr, 0, IEEE80211W_RIGHT_KEY); + + /* TX unicast deauth to every client STA */ + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + for (index = 0; index < NUM_STA; index++) { + psta = NULL; + + phead = &(pstapriv->sta_hash[index]); + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + plist = get_next(plist); + _rtw_memcpy(&mac_addr[psta->mac_id][0], psta->hwaddr, ETH_ALEN); + } + } + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + for (index = 0; index < macid_ctl->num && index < NUM_STA; index++) { + if (rtw_macid_is_used(macid_ctl, index) && !rtw_macid_is_bmc(macid_ctl, index)) { + if (!_rtw_memcmp(get_my_bssid(&(pmlmeinfo->network)), &mac_addr[index][0], ETH_ALEN)) { + if (key_type != 3) + issue_deauth_11w(padapter, &mac_addr[index][0], 0, (u8)key_type); + + psta = rtw_get_stainfo(pstapriv, &mac_addr[index][0]); + if (psta && key_type != IEEE80211W_WRONG_KEY && key_type != IEEE80211W_NO_KEY) { + u8 updated = _FALSE; + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) { + rtw_list_delete(&psta->asoc_list); + pstapriv->asoc_list_cnt--; + updated = ap_free_sta(padapter, psta, _FALSE, WLAN_REASON_PREV_AUTH_NOT_VALID, _TRUE); + + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL); + } + + DBG_871X("STA[%u]:"MAC_FMT"\n", index , MAC_ARG(&mac_addr[index][0])); + } + } + } + } + + return count; +} + +int proc_get_tx_deauth(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + DBG_871X_SEL_NL(m, "%s\n", __func__); + return 0; +} + +ssize_t proc_set_tx_auth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sta_priv *pstapriv = &padapter->stapriv; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + struct sta_info *psta; + _list *plist, *phead; + _irqL irqL; + char tmp[16]; + u8 mac_addr[NUM_STA][ETH_ALEN]; + u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + u32 tx_auth; + u8 index; + + + if (count > 2) { + DBG_871X("argument size is more than 2\n"); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) { + + int num = sscanf(tmp, "%x", &tx_auth); + + if (num != 1) { + DBG_871X("invalid read_reg parameter!\n"); + return count; + } + DBG_871X("1: setnd auth, 2: send assoc request. tx_auth=%d\n", tx_auth); + } + + if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) + && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)) { + if (tx_auth == 1) { + /* TX unicast auth to AP */ + issue_auth(padapter, NULL, 0); + } else if (tx_auth == 2) { + /* TX unicast auth to AP */ + issue_assocreq(padapter); + } + } + + return count; +} + +int proc_get_tx_auth(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + DBG_871X_SEL_NL(m, "%s\n", __func__); + return 0; +} +#endif /* CONFIG_IEEE80211W */ + +#endif /* CONFIG_PROC_DEBUG */ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_eeprom.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_eeprom.c new file mode 100644 index 000000000..e83c090ac --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_eeprom.c @@ -0,0 +1,423 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_EEPROM_C_ + +#include +#include +#include + +void up_clk(_adapter* padapter, u16 *x) +{ +_func_enter_; + *x = *x | _EESK; + rtw_write8(padapter, EE_9346CR, (u8)*x); + rtw_udelay_os(CLOCK_RATE); + +_func_exit_; + +} + +void down_clk(_adapter * padapter, u16 *x ) +{ +_func_enter_; + *x = *x & ~_EESK; + rtw_write8(padapter, EE_9346CR, (u8)*x); + rtw_udelay_os(CLOCK_RATE); +_func_exit_; +} + +void shift_out_bits(_adapter * padapter, u16 data, u16 count) +{ + u16 x,mask; +_func_enter_; + + if (rtw_is_surprise_removed(padapter)) { + RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE")); + goto out; + } + mask = 0x01 << (count - 1); + x = rtw_read8(padapter, EE_9346CR); + + x &= ~(_EEDO | _EEDI); + + do + { + x &= ~_EEDI; + if(data & mask) + x |= _EEDI; + if (rtw_is_surprise_removed(padapter)) { + RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE")); + goto out; + } + rtw_write8(padapter, EE_9346CR, (u8)x); + rtw_udelay_os(CLOCK_RATE); + up_clk(padapter, &x); + down_clk(padapter, &x); + mask = mask >> 1; + } while(mask); + if (rtw_is_surprise_removed(padapter)) { + RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE")); + goto out; + } + x &= ~_EEDI; + rtw_write8(padapter, EE_9346CR, (u8)x); +out: +_func_exit_; +} + +u16 shift_in_bits (_adapter * padapter) +{ + u16 x,d=0,i; +_func_enter_; + if (rtw_is_surprise_removed(padapter)) { + RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE")); + goto out; + } + x = rtw_read8(padapter, EE_9346CR); + + x &= ~( _EEDO | _EEDI); + d = 0; + + for(i=0; i<16; i++) + { + d = d << 1; + up_clk(padapter, &x); + if (rtw_is_surprise_removed(padapter)) { + RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE")); + goto out; + } + x = rtw_read8(padapter, EE_9346CR); + + x &= ~(_EEDI); + if(x & _EEDO) + d |= 1; + + down_clk(padapter, &x); + } +out: +_func_exit_; + + return d; +} + +void standby(_adapter * padapter ) +{ + u8 x; +_func_enter_; + x = rtw_read8(padapter, EE_9346CR); + + x &= ~(_EECS | _EESK); + rtw_write8(padapter, EE_9346CR,x); + + rtw_udelay_os(CLOCK_RATE); + x |= _EECS; + rtw_write8(padapter, EE_9346CR, x); + rtw_udelay_os(CLOCK_RATE); +_func_exit_; +} + +u16 wait_eeprom_cmd_done(_adapter* padapter) +{ + u8 x; + u16 i,res=_FALSE; +_func_enter_; + standby(padapter ); + for (i=0; i<200; i++) + { + x = rtw_read8(padapter, EE_9346CR); + if (x & _EEDO){ + res=_TRUE; + goto exit; + } + rtw_udelay_os(CLOCK_RATE); + } +exit: +_func_exit_; + return res; +} + +void eeprom_clean(_adapter * padapter) +{ + u16 x; +_func_enter_; + if (rtw_is_surprise_removed(padapter)) { + RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE")); + goto out; + } + x = rtw_read8(padapter, EE_9346CR); + if (rtw_is_surprise_removed(padapter)) { + RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE")); + goto out; + } + x &= ~(_EECS | _EEDI); + rtw_write8(padapter, EE_9346CR, (u8)x); + if (rtw_is_surprise_removed(padapter)) { + RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE")); + goto out; + } + up_clk(padapter, &x); + if (rtw_is_surprise_removed(padapter)) { + RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE")); + goto out; + } + down_clk(padapter, &x); +out: +_func_exit_; +} + +void eeprom_write16(_adapter * padapter, u16 reg, u16 data) +{ + u8 x; +#ifdef CONFIG_RTL8712 + u8 tmp8_ori,tmp8_new,tmp8_clk_ori,tmp8_clk_new; + tmp8_ori=rtw_read8(padapter, 0x102502f1); + tmp8_new=tmp8_ori & 0xf7; + if(tmp8_ori != tmp8_new){ + rtw_write8(padapter, 0x102502f1, tmp8_new); + RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x102502f1=====\n")); + } + tmp8_clk_ori=rtw_read8(padapter,0x10250003); + tmp8_clk_new=tmp8_clk_ori|0x20; + if(tmp8_clk_new!=tmp8_clk_ori){ + RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x10250003=====\n")); + rtw_write8(padapter, 0x10250003, tmp8_clk_new); + } +#endif +_func_enter_; + + x = rtw_read8(padapter, EE_9346CR); + + x &= ~(_EEDI | _EEDO | _EESK | _EEM0); + x |= _EEM1 | _EECS; + rtw_write8(padapter, EE_9346CR, x); + + shift_out_bits(padapter, EEPROM_EWEN_OPCODE, 5); + + if(padapter->EepromAddressSize==8) //CF+ and SDIO + shift_out_bits(padapter, 0, 6); + else //USB + shift_out_bits(padapter, 0, 4); + + standby( padapter); + +// Commented out by rcnjko, 2004.0 +// // Erase this particular word. Write the erase opcode and register +// // number in that order. The opcode is 3bits in length; reg is 6 bits long. +// shift_out_bits(Adapter, EEPROM_ERASE_OPCODE, 3); +// shift_out_bits(Adapter, reg, Adapter->EepromAddressSize); +// +// if (wait_eeprom_cmd_done(Adapter ) == FALSE) +// { +// return; +// } + + + standby(padapter ); + + // write the new word to the EEPROM + + // send the write opcode the EEPORM + shift_out_bits(padapter, EEPROM_WRITE_OPCODE, 3); + + // select which word in the EEPROM that we are writing to. + shift_out_bits(padapter, reg, padapter->EepromAddressSize); + + // write the data to the selected EEPROM word. + shift_out_bits(padapter, data, 16); + + if (wait_eeprom_cmd_done(padapter ) == _FALSE) + { + + goto exit; + } + + standby(padapter ); + + shift_out_bits(padapter, EEPROM_EWDS_OPCODE, 5); + shift_out_bits(padapter, reg, 4); + + eeprom_clean(padapter ); +exit: +#ifdef CONFIG_RTL8712 + if(tmp8_clk_new!=tmp8_clk_ori) + rtw_write8(padapter, 0x10250003, tmp8_clk_ori); + if(tmp8_new!=tmp8_ori) + rtw_write8(padapter, 0x102502f1, tmp8_ori); + +#endif +_func_exit_; + return; +} + +u16 eeprom_read16(_adapter * padapter, u16 reg) //ReadEEprom +{ + + u16 x; + u16 data=0; +#ifdef CONFIG_RTL8712 + u8 tmp8_ori,tmp8_new,tmp8_clk_ori,tmp8_clk_new; + tmp8_ori= rtw_read8(padapter, 0x102502f1); + tmp8_new = tmp8_ori & 0xf7; + if(tmp8_ori != tmp8_new){ + rtw_write8(padapter, 0x102502f1, tmp8_new); + RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x102502f1=====\n")); + } + tmp8_clk_ori=rtw_read8(padapter,0x10250003); + tmp8_clk_new=tmp8_clk_ori|0x20; + if(tmp8_clk_new!=tmp8_clk_ori){ + RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x10250003=====\n")); + rtw_write8(padapter, 0x10250003, tmp8_clk_new); + } +#endif +_func_enter_; + + if (rtw_is_surprise_removed(padapter)) { + RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE")); + goto out; + } + // select EEPROM, reset bits, set _EECS + x = rtw_read8(padapter, EE_9346CR); + + if (rtw_is_surprise_removed(padapter)) { + RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE")); + goto out; + } + + x &= ~(_EEDI | _EEDO | _EESK | _EEM0); + x |= _EEM1 | _EECS; + rtw_write8(padapter, EE_9346CR, (unsigned char)x); + + // write the read opcode and register number in that order + // The opcode is 3bits in length, reg is 6 bits long + shift_out_bits(padapter, EEPROM_READ_OPCODE, 3); + shift_out_bits(padapter, reg, padapter->EepromAddressSize); + + // Now read the data (16 bits) in from the selected EEPROM word + data = shift_in_bits(padapter); + + eeprom_clean(padapter); +out: +#ifdef CONFIG_RTL8712 + if(tmp8_clk_new!=tmp8_clk_ori) + rtw_write8(padapter, 0x10250003, tmp8_clk_ori); + if(tmp8_new!=tmp8_ori) + rtw_write8(padapter, 0x102502f1, tmp8_ori); + +#endif +_func_exit_; + return data; + + +} + + + + +//From even offset +void eeprom_read_sz(_adapter * padapter, u16 reg, u8* data, u32 sz) +{ + + u16 x, data16; + u32 i; +_func_enter_; + if (rtw_is_surprise_removed(padapter)) { + RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE")); + goto out; + } + // select EEPROM, reset bits, set _EECS + x = rtw_read8(padapter, EE_9346CR); + + if (rtw_is_surprise_removed(padapter)) { + RT_TRACE(_module_rtl871x_eeprom_c_, _drv_err_, ("padapter->bSurpriseRemoved==_TRUE")); + goto out; + } + + x &= ~(_EEDI | _EEDO | _EESK | _EEM0); + x |= _EEM1 | _EECS; + rtw_write8(padapter, EE_9346CR, (unsigned char)x); + + // write the read opcode and register number in that order + // The opcode is 3bits in length, reg is 6 bits long + shift_out_bits(padapter, EEPROM_READ_OPCODE, 3); + shift_out_bits(padapter, reg, padapter->EepromAddressSize); + + + for(i=0; i>8; + } + + eeprom_clean(padapter); +out: +_func_exit_; + + + +} + + +//addr_off : address offset of the entry in eeprom (not the tuple number of eeprom (reg); that is addr_off !=reg) +u8 eeprom_read(_adapter * padapter, u32 addr_off, u8 sz, u8* rbuf) +{ + u8 quotient, remainder, addr_2align_odd; + u16 reg, stmp , i=0, idx = 0; +_func_enter_; + reg = (u16)(addr_off >> 1); + addr_2align_odd = (u8)(addr_off & 0x1); + + if(addr_2align_odd) //read that start at high part: e.g 1,3,5,7,9,... + { + stmp = eeprom_read16(padapter, reg); + rbuf[idx++] = (u8) ((stmp>>8)&0xff); //return hogh-part of the short + reg++; sz--; + } + + quotient = sz >> 1; + remainder = sz & 0x1; + + for( i=0 ; i < quotient; i++) + { + stmp = eeprom_read16(padapter, reg+i); + rbuf[idx++] = (u8) (stmp&0xff); + rbuf[idx++] = (u8) ((stmp>>8)&0xff); + } + + reg = reg+i; + if(remainder){ //end of read at lower part of short : 0,2,4,6,... + stmp = eeprom_read16(padapter, reg); + rbuf[idx] = (u8)(stmp & 0xff); + } +_func_exit_; + return _TRUE; +} + + + +VOID read_eeprom_content(_adapter * padapter) +{ + +_func_enter_; + + +_func_exit_; +} + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_ieee80211.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_ieee80211.c new file mode 100644 index 000000000..ded4e1629 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_ieee80211.c @@ -0,0 +1,2836 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _IEEE80211_C + +#ifdef CONFIG_PLATFORM_INTEL_BYT +#include +#endif +#include + + +u8 RTW_WPA_OUI_TYPE[] = { 0x00, 0x50, 0xf2, 1 }; +u16 RTW_WPA_VERSION = 1; +u8 WPA_AUTH_KEY_MGMT_NONE[] = { 0x00, 0x50, 0xf2, 0 }; +u8 WPA_AUTH_KEY_MGMT_UNSPEC_802_1X[] = { 0x00, 0x50, 0xf2, 1 }; +u8 WPA_AUTH_KEY_MGMT_PSK_OVER_802_1X[] = { 0x00, 0x50, 0xf2, 2 }; +u8 WPA_CIPHER_SUITE_NONE[] = { 0x00, 0x50, 0xf2, 0 }; +u8 WPA_CIPHER_SUITE_WEP40[] = { 0x00, 0x50, 0xf2, 1 }; +u8 WPA_CIPHER_SUITE_TKIP[] = { 0x00, 0x50, 0xf2, 2 }; +u8 WPA_CIPHER_SUITE_WRAP[] = { 0x00, 0x50, 0xf2, 3 }; +u8 WPA_CIPHER_SUITE_CCMP[] = { 0x00, 0x50, 0xf2, 4 }; +u8 WPA_CIPHER_SUITE_WEP104[] = { 0x00, 0x50, 0xf2, 5 }; + +u16 RSN_VERSION_BSD = 1; +u8 RSN_AUTH_KEY_MGMT_UNSPEC_802_1X[] = { 0x00, 0x0f, 0xac, 1 }; +u8 RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X[] = { 0x00, 0x0f, 0xac, 2 }; +u8 RSN_CIPHER_SUITE_NONE[] = { 0x00, 0x0f, 0xac, 0 }; +u8 RSN_CIPHER_SUITE_WEP40[] = { 0x00, 0x0f, 0xac, 1 }; +u8 RSN_CIPHER_SUITE_TKIP[] = { 0x00, 0x0f, 0xac, 2 }; +u8 RSN_CIPHER_SUITE_WRAP[] = { 0x00, 0x0f, 0xac, 3 }; +u8 RSN_CIPHER_SUITE_CCMP[] = { 0x00, 0x0f, 0xac, 4 }; +u8 RSN_CIPHER_SUITE_WEP104[] = { 0x00, 0x0f, 0xac, 5 }; +//----------------------------------------------------------- +// for adhoc-master to generate ie and provide supported-rate to fw +//----------------------------------------------------------- + +static u8 WIFI_CCKRATES[] = +{(IEEE80211_CCK_RATE_1MB | IEEE80211_BASIC_RATE_MASK), + (IEEE80211_CCK_RATE_2MB | IEEE80211_BASIC_RATE_MASK), + (IEEE80211_CCK_RATE_5MB | IEEE80211_BASIC_RATE_MASK), + (IEEE80211_CCK_RATE_11MB | IEEE80211_BASIC_RATE_MASK)}; + +static u8 WIFI_OFDMRATES[] = +{(IEEE80211_OFDM_RATE_6MB), + (IEEE80211_OFDM_RATE_9MB), + (IEEE80211_OFDM_RATE_12MB), + (IEEE80211_OFDM_RATE_18MB), + (IEEE80211_OFDM_RATE_24MB), + IEEE80211_OFDM_RATE_36MB, + IEEE80211_OFDM_RATE_48MB, + IEEE80211_OFDM_RATE_54MB}; + +u8 mgn_rates_cck[4] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M}; +u8 mgn_rates_ofdm[8] = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M}; +u8 mgn_rates_mcs0_7[8] = {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7}; +u8 mgn_rates_mcs8_15[8] = {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15}; +u8 mgn_rates_mcs16_23[8] = {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19, MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23}; +u8 mgn_rates_mcs24_31[8] = {MGN_MCS24, MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29, MGN_MCS30, MGN_MCS31}; +u8 mgn_rates_vht1ss[10] = {MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4 + , MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9}; +u8 mgn_rates_vht2ss[10] = {MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4 + , MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9}; +u8 mgn_rates_vht3ss[10] = {MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4 + , MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9}; +u8 mgn_rates_vht4ss[10] = {MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4 + , MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9}; + +static const char * const _rate_section_str[] = { + "CCK", + "OFDM", + "HT_1SS", + "HT_2SS", + "HT_3SS", + "HT_4SS", + "VHT_1SS", + "VHT_2SS", + "VHT_3SS", + "VHT_4SS", + "RATE_SECTION_UNKNOWN", +}; + +const char *rate_section_str(u8 section) +{ + section = (section >= RATE_SECTION_NUM) ? RATE_SECTION_NUM : section; + return _rate_section_str[section]; +} + +struct rate_section_ent rates_by_sections[RATE_SECTION_NUM] = { + {RF_1TX, 4, mgn_rates_cck}, + {RF_1TX, 8, mgn_rates_ofdm}, + {RF_1TX, 8, mgn_rates_mcs0_7}, + {RF_2TX, 8, mgn_rates_mcs8_15}, + {RF_3TX, 8, mgn_rates_mcs16_23}, + {RF_4TX, 8, mgn_rates_mcs24_31}, + {RF_1TX, 10, mgn_rates_vht1ss}, + {RF_2TX, 10, mgn_rates_vht2ss}, + {RF_3TX, 10, mgn_rates_vht3ss}, + {RF_4TX, 10, mgn_rates_vht4ss}, +}; + +int rtw_get_bit_value_from_ieee_value(u8 val) +{ + unsigned char dot11_rate_table[]={2,4,11,22,12,18,24,36,48,72,96,108,0}; // last element must be zero!! + + int i=0; + while(dot11_rate_table[i] != 0) { + if (dot11_rate_table[i] == val) + return BIT(i); + i++; + } + return 0; +} + +uint rtw_is_cckrates_included(u8 *rate) +{ + u32 i = 0; + + while(rate[i]!=0) + { + if ( (((rate[i]) & 0x7f) == 2) || (((rate[i]) & 0x7f) == 4) || + (((rate[i]) & 0x7f) == 11) || (((rate[i]) & 0x7f) == 22) ) + return _TRUE; + i++; + } + + return _FALSE; +} + +uint rtw_is_cckratesonly_included(u8 *rate) +{ + u32 i = 0; + + + while(rate[i]!=0) + { + if ( (((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) && + (((rate[i]) & 0x7f) != 11) && (((rate[i]) & 0x7f) != 22) ) + return _FALSE; + + i++; + } + + return _TRUE; + +} + +int rtw_check_network_type(unsigned char *rate, int ratelen, int channel) +{ + if (channel > 14) + { + if ((rtw_is_cckrates_included(rate)) == _TRUE) + return WIRELESS_INVALID; + else + return WIRELESS_11A; + } + else // could be pure B, pure G, or B/G + { + if ((rtw_is_cckratesonly_included(rate)) == _TRUE) + return WIRELESS_11B; + else if((rtw_is_cckrates_included(rate)) == _TRUE) + return WIRELESS_11BG; + else + return WIRELESS_11G; + } + +} + +u8 *rtw_set_fixed_ie(unsigned char *pbuf, unsigned int len, unsigned char *source, + unsigned int *frlen) +{ + _rtw_memcpy((void *)pbuf, (void *)source, len); + *frlen = *frlen + len; + return (pbuf + len); +} + +// rtw_set_ie will update frame length +u8 *rtw_set_ie +( + u8 *pbuf, + sint index, + uint len, + u8 *source, + uint *frlen //frame length +) +{ + *pbuf = (u8)index; + + *(pbuf + 1) = (u8)len; + + if (len > 0) + _rtw_memcpy((void *)(pbuf + 2), (void *)source, len); + + *frlen = *frlen + (len + 2); + + return (pbuf + len + 2); +} + +inline u8 *rtw_set_ie_ch_switch(u8 *buf, u32 *buf_len, u8 ch_switch_mode, + u8 new_ch, u8 ch_switch_cnt) +{ + u8 ie_data[3]; + + ie_data[0] = ch_switch_mode; + ie_data[1] = new_ch; + ie_data[2] = ch_switch_cnt; + return rtw_set_ie(buf, WLAN_EID_CHANNEL_SWITCH, 3, ie_data, buf_len); +} + +inline u8 secondary_ch_offset_to_hal_ch_offset(u8 ch_offset) +{ + if (ch_offset == SCN) + return HAL_PRIME_CHNL_OFFSET_DONT_CARE; + else if(ch_offset == SCA) + return HAL_PRIME_CHNL_OFFSET_UPPER; + else if(ch_offset == SCB) + return HAL_PRIME_CHNL_OFFSET_LOWER; + + return HAL_PRIME_CHNL_OFFSET_DONT_CARE; +} + +inline u8 hal_ch_offset_to_secondary_ch_offset(u8 ch_offset) +{ + if (ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) + return SCN; + else if(ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER) + return SCB; + else if(ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER) + return SCA; + + return SCN; +} + +inline u8 *rtw_set_ie_secondary_ch_offset(u8 *buf, u32 *buf_len, u8 secondary_ch_offset) +{ + return rtw_set_ie(buf, WLAN_EID_SECONDARY_CHANNEL_OFFSET, 1, &secondary_ch_offset, buf_len); +} + +inline u8 *rtw_set_ie_mesh_ch_switch_parm(u8 *buf, u32 *buf_len, u8 ttl, + u8 flags, u16 reason, u16 precedence) +{ + u8 ie_data[6]; + + ie_data[0] = ttl; + ie_data[1] = flags; + RTW_PUT_LE16((u8*)&ie_data[2], reason); + RTW_PUT_LE16((u8*)&ie_data[4], precedence); + + return rtw_set_ie(buf, 0x118, 6, ie_data, buf_len); +} + +/*---------------------------------------------------------------------------- +index: the information element id index, limit is the limit for search +-----------------------------------------------------------------------------*/ +u8 *rtw_get_ie(u8 *pbuf, sint index, sint *len, sint limit) +{ + sint tmp,i; + u8 *p; +_func_enter_; + if (limit < 1){ + _func_exit_; + return NULL; + } + + p = pbuf; + i = 0; + *len = 0; + while(1) + { + if (*p == index) + { + *len = *(p + 1); + return (p); + } + else + { + tmp = *(p + 1); + p += (tmp + 2); + i += (tmp + 2); + } + if (i >= limit) + break; + } +_func_exit_; + return NULL; +} + +/** + * rtw_get_ie_ex - Search specific IE from a series of IEs + * @in_ie: Address of IEs to search + * @in_len: Length limit from in_ie + * @eid: Element ID to match + * @oui: OUI to match + * @oui_len: OUI length + * @ie: If not NULL and the specific IE is found, the IE will be copied to the buf starting from the specific IE + * @ielen: If not NULL and the specific IE is found, will set to the length of the entire IE + * + * Returns: The address of the specific IE found, or NULL + */ +u8 *rtw_get_ie_ex(u8 *in_ie, uint in_len, u8 eid, u8 *oui, u8 oui_len, u8 *ie, uint *ielen) +{ + uint cnt; + u8 *target_ie = NULL; + + + if(ielen) + *ielen = 0; + + if(!in_ie || in_len<=0) + return target_ie; + + cnt = 0; + + while(cnt 12) + break; + + i++; + } +_func_exit_; + return i; +} + +int rtw_generate_ie(struct registry_priv *pregistrypriv) +{ + u8 wireless_mode; + int sz = 0, rateLen; + WLAN_BSSID_EX* pdev_network = &pregistrypriv->dev_network; + u8* ie = pdev_network->IEs; + +_func_enter_; + + //timestamp will be inserted by hardware + sz += 8; + ie += sz; + + //beacon interval : 2bytes + *(u16*)ie = cpu_to_le16((u16)pdev_network->Configuration.BeaconPeriod);//BCN_INTERVAL; + sz += 2; + ie += 2; + + //capability info + *(u16*)ie = 0; + + *(u16*)ie |= cpu_to_le16(cap_IBSS); + + if(pregistrypriv->preamble == PREAMBLE_SHORT) + *(u16*)ie |= cpu_to_le16(cap_ShortPremble); + + if (pdev_network->Privacy) + *(u16*)ie |= cpu_to_le16(cap_Privacy); + + sz += 2; + ie += 2; + + //SSID + ie = rtw_set_ie(ie, _SSID_IE_, pdev_network->Ssid.SsidLength, pdev_network->Ssid.Ssid, &sz); + + //supported rates + if (pregistrypriv->wireless_mode == WIRELESS_11ABGN) { + if(pdev_network->Configuration.DSConfig > 14) + wireless_mode = WIRELESS_11A_5N; + else + wireless_mode = WIRELESS_11BG_24N; + } else if (pregistrypriv->wireless_mode == WIRELESS_MODE_MAX) { /* WIRELESS_11ABGN | WIRELESS_11AC */ + if (pdev_network->Configuration.DSConfig > 14) + wireless_mode = WIRELESS_11_5AC; + else + wireless_mode = WIRELESS_11BG_24N; + } else + wireless_mode = pregistrypriv->wireless_mode; + + rtw_set_supported_rate(pdev_network->SupportedRates, wireless_mode) ; + + rateLen = rtw_get_rateset_len(pdev_network->SupportedRates); + + if (rateLen > 8) + { + ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, 8, pdev_network->SupportedRates, &sz); + //ie = rtw_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), (pdev_network->SupportedRates + 8), &sz); + } + else + { + ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, rateLen, pdev_network->SupportedRates, &sz); + } + + //DS parameter set + ie = rtw_set_ie(ie, _DSSET_IE_, 1, (u8 *)&(pdev_network->Configuration.DSConfig), &sz); + + + //IBSS Parameter Set + + ie = rtw_set_ie(ie, _IBSS_PARA_IE_, 2, (u8 *)&(pdev_network->Configuration.ATIMWindow), &sz); + + if (rateLen > 8) + { + ie = rtw_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), (pdev_network->SupportedRates + 8), &sz); + } + +#ifdef CONFIG_80211N_HT + //HT Cap. + if(((pregistrypriv->wireless_mode&WIRELESS_11_5N)||(pregistrypriv->wireless_mode&WIRELESS_11_24N)) + && (pregistrypriv->ht_enable==_TRUE)) + { + //todo: + } +#endif //CONFIG_80211N_HT + + //pdev_network->IELength = sz; //update IELength + +_func_exit_; + + //return _SUCCESS; + + return sz; + +} + +unsigned char *rtw_get_wpa_ie(unsigned char *pie, int *wpa_ie_len, int limit) +{ + int len; + u16 val16; + unsigned char wpa_oui_type[] = {0x00, 0x50, 0xf2, 0x01}; + u8 *pbuf = pie; + int limit_new = limit; + + while(1) + { + pbuf = rtw_get_ie(pbuf, _WPA_IE_ID_, &len, limit_new); + + if (pbuf) { + + //check if oui matches... + if (_rtw_memcmp((pbuf + 2), wpa_oui_type, sizeof (wpa_oui_type)) == _FALSE) { + + goto check_next_ie; + } + + //check version... + _rtw_memcpy((u8 *)&val16, (pbuf + 6), sizeof(val16)); + + val16 = le16_to_cpu(val16); + if (val16 != 0x0001) + goto check_next_ie; + + *wpa_ie_len = *(pbuf + 1); + + return pbuf; + + } + else { + + *wpa_ie_len = 0; + return NULL; + } + +check_next_ie: + + limit_new = limit - (pbuf - pie) - 2 - len; + + if (limit_new <= 0) + break; + + pbuf += (2 + len); + + } + + *wpa_ie_len = 0; + + return NULL; + +} + +unsigned char *rtw_get_wpa2_ie(unsigned char *pie, int *rsn_ie_len, int limit) +{ + + return rtw_get_ie(pie, _WPA2_IE_ID_,rsn_ie_len, limit); + +} + +int rtw_get_wpa_cipher_suite(u8 *s) +{ + if (_rtw_memcmp(s, WPA_CIPHER_SUITE_NONE, WPA_SELECTOR_LEN) == _TRUE) + return WPA_CIPHER_NONE; + if (_rtw_memcmp(s, WPA_CIPHER_SUITE_WEP40, WPA_SELECTOR_LEN) == _TRUE) + return WPA_CIPHER_WEP40; + if (_rtw_memcmp(s, WPA_CIPHER_SUITE_TKIP, WPA_SELECTOR_LEN) == _TRUE) + return WPA_CIPHER_TKIP; + if (_rtw_memcmp(s, WPA_CIPHER_SUITE_CCMP, WPA_SELECTOR_LEN) == _TRUE) + return WPA_CIPHER_CCMP; + if (_rtw_memcmp(s, WPA_CIPHER_SUITE_WEP104, WPA_SELECTOR_LEN) == _TRUE) + return WPA_CIPHER_WEP104; + + return 0; +} + +int rtw_get_wpa2_cipher_suite(u8 *s) +{ + if (_rtw_memcmp(s, RSN_CIPHER_SUITE_NONE, RSN_SELECTOR_LEN) == _TRUE) + return WPA_CIPHER_NONE; + if (_rtw_memcmp(s, RSN_CIPHER_SUITE_WEP40, RSN_SELECTOR_LEN) == _TRUE) + return WPA_CIPHER_WEP40; + if (_rtw_memcmp(s, RSN_CIPHER_SUITE_TKIP, RSN_SELECTOR_LEN) == _TRUE) + return WPA_CIPHER_TKIP; + if (_rtw_memcmp(s, RSN_CIPHER_SUITE_CCMP, RSN_SELECTOR_LEN) == _TRUE) + return WPA_CIPHER_CCMP; + if (_rtw_memcmp(s, RSN_CIPHER_SUITE_WEP104, RSN_SELECTOR_LEN) == _TRUE) + return WPA_CIPHER_WEP104; + + return 0; +} + + +int rtw_parse_wpa_ie(u8* wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x) +{ + int i, ret=_SUCCESS; + int left, count; + u8 *pos; + u8 SUITE_1X[4] = {0x00, 0x50, 0xf2, 1}; + + if (wpa_ie_len <= 0) { + /* No WPA IE - fail silently */ + return _FAIL; + } + + + if ((*wpa_ie != _WPA_IE_ID_) || (*(wpa_ie+1) != (u8)(wpa_ie_len - 2)) || + (_rtw_memcmp(wpa_ie+2, RTW_WPA_OUI_TYPE, WPA_SELECTOR_LEN) != _TRUE) ) + { + return _FAIL; + } + + pos = wpa_ie; + + pos += 8; + left = wpa_ie_len - 8; + + + //group_cipher + if (left >= WPA_SELECTOR_LEN) { + + *group_cipher = rtw_get_wpa_cipher_suite(pos); + + pos += WPA_SELECTOR_LEN; + left -= WPA_SELECTOR_LEN; + + } + else if (left > 0) + { + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s: ie length mismatch, %u too much", __FUNCTION__, left)); + + return _FAIL; + } + + + //pairwise_cipher + if (left >= 2) + { + //count = le16_to_cpu(*(u16*)pos); + count = RTW_GET_LE16(pos); + pos += 2; + left -= 2; + + if (count == 0 || left < count * WPA_SELECTOR_LEN) { + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s: ie count botch (pairwise), " + "count %u left %u", __FUNCTION__, count, left)); + return _FAIL; + } + + for (i = 0; i < count; i++) + { + *pairwise_cipher |= rtw_get_wpa_cipher_suite(pos); + + pos += WPA_SELECTOR_LEN; + left -= WPA_SELECTOR_LEN; + } + + } + else if (left == 1) + { + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s: ie too short (for key mgmt)", __FUNCTION__)); + return _FAIL; + } + + if (is_8021x) { + if (left >= 6) { + pos += 2; + if (_rtw_memcmp(pos, SUITE_1X, 4) == 1) { + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("%s : there has 802.1x auth\n", __FUNCTION__)); + *is_8021x = 1; + } + } + } + + return ret; + +} + +int rtw_parse_wpa2_ie(u8* rsn_ie, int rsn_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x) +{ + int i, ret=_SUCCESS; + int left, count; + u8 *pos; + u8 SUITE_1X[4] = {0x00,0x0f, 0xac, 0x01}; + + if (rsn_ie_len <= 0) { + /* No RSN IE - fail silently */ + return _FAIL; + } + + + if ((*rsn_ie!= _WPA2_IE_ID_) || (*(rsn_ie+1) != (u8)(rsn_ie_len - 2))) + { + return _FAIL; + } + + pos = rsn_ie; + pos += 4; + left = rsn_ie_len - 4; + + //group_cipher + if (left >= RSN_SELECTOR_LEN) { + + *group_cipher = rtw_get_wpa2_cipher_suite(pos); + + pos += RSN_SELECTOR_LEN; + left -= RSN_SELECTOR_LEN; + + } else if (left > 0) { + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s: ie length mismatch, %u too much", __FUNCTION__, left)); + return _FAIL; + } + + //pairwise_cipher + if (left >= 2) + { + //count = le16_to_cpu(*(u16*)pos); + count = RTW_GET_LE16(pos); + pos += 2; + left -= 2; + + if (count == 0 || left < count * RSN_SELECTOR_LEN) { + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s: ie count botch (pairwise), " + "count %u left %u", __FUNCTION__, count, left)); + return _FAIL; + } + + for (i = 0; i < count; i++) + { + *pairwise_cipher |= rtw_get_wpa2_cipher_suite(pos); + + pos += RSN_SELECTOR_LEN; + left -= RSN_SELECTOR_LEN; + } + + } + else if (left == 1) + { + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s: ie too short (for key mgmt)", __FUNCTION__)); + + return _FAIL; + } + + if (is_8021x) { + if (left >= 6) { + pos += 2; + if (_rtw_memcmp(pos, SUITE_1X, 4) == 1) { + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("%s (): there has 802.1x auth\n", __FUNCTION__)); + *is_8021x = 1; + } + } + } + + return ret; + +} + +//#ifdef CONFIG_WAPI_SUPPORT +int rtw_get_wapi_ie(u8 *in_ie,uint in_len,u8 *wapi_ie,u16 *wapi_len) +{ + int len = 0; + u8 authmode, i; + uint cnt; + u8 wapi_oui1[4]={0x0,0x14,0x72,0x01}; + u8 wapi_oui2[4]={0x0,0x14,0x72,0x02}; + +_func_enter_; + + if(wapi_len) + *wapi_len = 0; + + if(!in_ie || in_len<=0) + return len; + + cnt = (_TIMESTAMP_ + _BEACON_ITERVAL_ + _CAPABILITY_); + + while(cnt found WPS_IE.....\n"); + *wps_ielen = ie_ptr[1]+2; + match=_TRUE; + } + return match; +} + +u8 *rtw_get_wps_ie_from_scan_queue(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen, u8 frame_type) +{ + u8* wps = NULL; + + DBG_871X( "[%s] frame_type = %d\n", __FUNCTION__, frame_type ); + switch( frame_type ) + { + case 1: + case 3: + { // Beacon or Probe Response + wps = rtw_get_wps_ie(in_ie + _PROBERSP_IE_OFFSET_, in_len - _PROBERSP_IE_OFFSET_, wps_ie, wps_ielen); + break; + } + case 2: + { // Probe Request + wps = rtw_get_wps_ie(in_ie + _PROBEREQ_IE_OFFSET_ , in_len - _PROBEREQ_IE_OFFSET_ , wps_ie, wps_ielen); + break; + } + } + return wps; +} + +/** + * rtw_get_wps_ie - Search WPS IE from a series of IEs + * @in_ie: Address of IEs to search + * @in_len: Length limit from in_ie + * @wps_ie: If not NULL and WPS IE is found, WPS IE will be copied to the buf starting from wps_ie + * @wps_ielen: If not NULL and WPS IE is found, will set to the length of the entire WPS IE + * + * Returns: The address of the WPS IE found, or NULL + */ +u8 *rtw_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen) +{ + uint cnt; + u8 *wpsie_ptr = NULL; + u8 eid, wps_oui[4] = {0x00, 0x50, 0xf2, 0x04}; + + if (wps_ielen) + *wps_ielen = 0; + + if (!in_ie) { + rtw_warn_on(1); + return wpsie_ptr; + } + + if (in_len <= 0) + return wpsie_ptr; + + cnt = 0; + + while (cnt + 1 + 4 < in_len) { + eid = in_ie[cnt]; + + if (cnt + 1 + 4 >= MAX_IE_SZ) { + rtw_warn_on(1); + return NULL; + } + + if (eid == WLAN_EID_VENDOR_SPECIFIC && _rtw_memcmp(&in_ie[cnt + 2], wps_oui, 4) == _TRUE) { + wpsie_ptr = in_ie + cnt; + + if (wps_ie) + _rtw_memcpy(wps_ie, &in_ie[cnt], in_ie[cnt + 1] + 2); + + if (wps_ielen) + *wps_ielen = in_ie[cnt + 1] + 2; + + break; + } else { + cnt += in_ie[cnt + 1] + 2; + } + + } + + return wpsie_ptr; +} + +/** + * rtw_get_wps_attr - Search a specific WPS attribute from a given WPS IE + * @wps_ie: Address of WPS IE to search + * @wps_ielen: Length limit from wps_ie + * @target_attr_id: The attribute ID of WPS attribute to search + * @buf_attr: If not NULL and the WPS attribute is found, WPS attribute will be copied to the buf starting from buf_attr + * @len_attr: If not NULL and the WPS attribute is found, will set to the length of the entire WPS attribute + * + * Returns: the address of the specific WPS attribute found, or NULL + */ +u8 *rtw_get_wps_attr(u8 *wps_ie, uint wps_ielen, u16 target_attr_id ,u8 *buf_attr, u32 *len_attr) +{ + u8 *attr_ptr = NULL; + u8 * target_attr_ptr = NULL; + u8 wps_oui[4]={0x00,0x50,0xF2,0x04}; + + if(len_attr) + *len_attr = 0; + + if ( ( wps_ie[0] != _VENDOR_SPECIFIC_IE_ ) || + ( _rtw_memcmp( wps_ie + 2, wps_oui , 4 ) != _TRUE ) ) + { + return attr_ptr; + } + + // 6 = 1(Element ID) + 1(Length) + 4(WPS OUI) + attr_ptr = wps_ie + 6; //goto first attr + + while(attr_ptr - wps_ie < wps_ielen) + { + // 4 = 2(Attribute ID) + 2(Length) + u16 attr_id = RTW_GET_BE16(attr_ptr); + u16 attr_data_len = RTW_GET_BE16(attr_ptr + 2); + u16 attr_len = attr_data_len + 4; + + //DBG_871X("%s attr_ptr:%p, id:%u, length:%u\n", __FUNCTION__, attr_ptr, attr_id, attr_data_len); + if( attr_id == target_attr_id ) + { + target_attr_ptr = attr_ptr; + + if(buf_attr) + _rtw_memcpy(buf_attr, attr_ptr, attr_len); + + if(len_attr) + *len_attr = attr_len; + + break; + } + else + { + attr_ptr += attr_len; //goto next + } + + } + + return target_attr_ptr; +} + +/** + * rtw_get_wps_attr_content - Search a specific WPS attribute content from a given WPS IE + * @wps_ie: Address of WPS IE to search + * @wps_ielen: Length limit from wps_ie + * @target_attr_id: The attribute ID of WPS attribute to search + * @buf_content: If not NULL and the WPS attribute is found, WPS attribute content will be copied to the buf starting from buf_content + * @len_content: If not NULL and the WPS attribute is found, will set to the length of the WPS attribute content + * + * Returns: the address of the specific WPS attribute content found, or NULL + */ +u8 *rtw_get_wps_attr_content(u8 *wps_ie, uint wps_ielen, u16 target_attr_id ,u8 *buf_content, uint *len_content) +{ + u8 *attr_ptr; + u32 attr_len; + + if(len_content) + *len_content = 0; + + attr_ptr = rtw_get_wps_attr(wps_ie, wps_ielen, target_attr_id, NULL, &attr_len); + + if(attr_ptr && attr_len) + { + if(buf_content) + _rtw_memcpy(buf_content, attr_ptr+4, attr_len-4); + + if(len_content) + *len_content = attr_len-4; + + return attr_ptr+4; + } + + return NULL; +} + +static int rtw_ieee802_11_parse_vendor_specific(u8 *pos, uint elen, + struct rtw_ieee802_11_elems *elems, + int show_errors) +{ + unsigned int oui; + + /* first 3 bytes in vendor specific information element are the IEEE + * OUI of the vendor. The following byte is used a vendor specific + * sub-type. */ + if (elen < 4) { + if (show_errors) { + DBG_871X("short vendor specific " + "information element ignored (len=%lu)\n", + (unsigned long) elen); + } + return -1; + } + + oui = RTW_GET_BE24(pos); + switch (oui) { + case OUI_MICROSOFT: + /* Microsoft/Wi-Fi information elements are further typed and + * subtyped */ + switch (pos[3]) { + case 1: + /* Microsoft OUI (00:50:F2) with OUI Type 1: + * real WPA information element */ + elems->wpa_ie = pos; + elems->wpa_ie_len = elen; + break; + case WME_OUI_TYPE: /* this is a Wi-Fi WME info. element */ + if (elen < 5) { + DBG_871X("short WME " + "information element ignored " + "(len=%lu)\n", + (unsigned long) elen); + return -1; + } + switch (pos[4]) { + case WME_OUI_SUBTYPE_INFORMATION_ELEMENT: + case WME_OUI_SUBTYPE_PARAMETER_ELEMENT: + elems->wme = pos; + elems->wme_len = elen; + break; + case WME_OUI_SUBTYPE_TSPEC_ELEMENT: + elems->wme_tspec = pos; + elems->wme_tspec_len = elen; + break; + default: + DBG_871X_LEVEL(_drv_warning_, "unknown WME " + "information element ignored " + "(subtype=%d len=%lu)\n", + pos[4], (unsigned long) elen); + return -1; + } + break; + case 4: + /* Wi-Fi Protected Setup (WPS) IE */ + elems->wps_ie = pos; + elems->wps_ie_len = elen; + break; + default: + DBG_871X_LEVEL(_drv_warning_, "Unknown Microsoft " + "information element ignored " + "(type=%d len=%lu)\n", + pos[3], (unsigned long) elen); + return -1; + } + break; + + case OUI_BROADCOM: + switch (pos[3]) { + case VENDOR_HT_CAPAB_OUI_TYPE: + elems->vendor_ht_cap = pos; + elems->vendor_ht_cap_len = elen; + break; + default: + DBG_871X_LEVEL(_drv_warning_, "Unknown Broadcom " + "information element ignored " + "(type=%d len=%lu)\n", + pos[3], (unsigned long) elen); + return -1; + } + break; + + default: + DBG_871X_LEVEL(_drv_warning_, "unknown vendor specific information " + "element ignored (vendor OUI %02x:%02x:%02x " + "len=%lu)\n", + pos[0], pos[1], pos[2], (unsigned long) elen); + return -1; + } + + return 0; + +} + +/** + * ieee802_11_parse_elems - Parse information elements in management frames + * @start: Pointer to the start of IEs + * @len: Length of IE buffer in octets + * @elems: Data structure for parsed elements + * @show_errors: Whether to show parsing errors in debug log + * Returns: Parsing result + */ +ParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len, + struct rtw_ieee802_11_elems *elems, + int show_errors) +{ + uint left = len; + u8 *pos = start; + int unknown = 0; + + _rtw_memset(elems, 0, sizeof(*elems)); + + while (left >= 2) { + u8 id, elen; + + id = *pos++; + elen = *pos++; + left -= 2; + + if (elen > left) { + if (show_errors) { + DBG_871X("IEEE 802.11 element " + "parse failed (id=%d elen=%d " + "left=%lu)\n", + id, elen, (unsigned long) left); + } + return ParseFailed; + } + + switch (id) { + case WLAN_EID_SSID: + elems->ssid = pos; + elems->ssid_len = elen; + break; + case WLAN_EID_SUPP_RATES: + elems->supp_rates = pos; + elems->supp_rates_len = elen; + break; + case WLAN_EID_FH_PARAMS: + elems->fh_params = pos; + elems->fh_params_len = elen; + break; + case WLAN_EID_DS_PARAMS: + elems->ds_params = pos; + elems->ds_params_len = elen; + break; + case WLAN_EID_CF_PARAMS: + elems->cf_params = pos; + elems->cf_params_len = elen; + break; + case WLAN_EID_TIM: + elems->tim = pos; + elems->tim_len = elen; + break; + case WLAN_EID_IBSS_PARAMS: + elems->ibss_params = pos; + elems->ibss_params_len = elen; + break; + case WLAN_EID_CHALLENGE: + elems->challenge = pos; + elems->challenge_len = elen; + break; + case WLAN_EID_ERP_INFO: + elems->erp_info = pos; + elems->erp_info_len = elen; + break; + case WLAN_EID_EXT_SUPP_RATES: + elems->ext_supp_rates = pos; + elems->ext_supp_rates_len = elen; + break; + case WLAN_EID_VENDOR_SPECIFIC: + if (rtw_ieee802_11_parse_vendor_specific(pos, elen, + elems, + show_errors)) + unknown++; + break; + case WLAN_EID_RSN: + elems->rsn_ie = pos; + elems->rsn_ie_len = elen; + break; + case WLAN_EID_PWR_CAPABILITY: + elems->power_cap = pos; + elems->power_cap_len = elen; + break; + case WLAN_EID_SUPPORTED_CHANNELS: + elems->supp_channels = pos; + elems->supp_channels_len = elen; + break; + case WLAN_EID_MOBILITY_DOMAIN: + elems->mdie = pos; + elems->mdie_len = elen; + break; + case WLAN_EID_FAST_BSS_TRANSITION: + elems->ftie = pos; + elems->ftie_len = elen; + break; + case WLAN_EID_TIMEOUT_INTERVAL: + elems->timeout_int = pos; + elems->timeout_int_len = elen; + break; + case WLAN_EID_HT_CAP: + elems->ht_capabilities = pos; + elems->ht_capabilities_len = elen; + break; + case WLAN_EID_HT_OPERATION: + elems->ht_operation = pos; + elems->ht_operation_len = elen; + break; + case WLAN_EID_VHT_CAPABILITY: + elems->vht_capabilities = pos; + elems->vht_capabilities_len = elen; + break; + case WLAN_EID_VHT_OPERATION: + elems->vht_operation = pos; + elems->vht_operation_len = elen; + break; + case WLAN_EID_VHT_OP_MODE_NOTIFY: + elems->vht_op_mode_notify = pos; + elems->vht_op_mode_notify_len = elen; + break; + default: + unknown++; + if (!show_errors) + break; + DBG_871X_LEVEL(_drv_warning_, + "IEEE 802.11 element parse " + "ignored unknown element (id=%d elen=%d)\n", + id, elen); + break; + } + + left -= elen; + pos += elen; + } + + if (left) + return ParseFailed; + + return unknown ? ParseUnknown : ParseOK; + +} + +static u8 key_char2num(u8 ch); +static u8 key_char2num(u8 ch) +{ + if((ch>='0')&&(ch<='9')) + return ch - '0'; + else if ((ch>='a')&&(ch<='f')) + return ch - 'a' + 10; + else if ((ch>='A')&&(ch<='F')) + return ch - 'A' + 10; + else + return 0xff; +} + +u8 str_2char2num(u8 hch, u8 lch); +u8 str_2char2num(u8 hch, u8 lch) +{ + return ((key_char2num(hch) * 10 ) + key_char2num(lch)); +} + +u8 key_2char2num(u8 hch, u8 lch); +u8 key_2char2num(u8 hch, u8 lch) +{ + return ((key_char2num(hch) << 4) | key_char2num(lch)); +} + +void macstr2num(u8 *dst, u8 *src); +void macstr2num(u8 *dst, u8 *src) +{ + int jj, kk; + for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3) + { + dst[jj] = key_2char2num(src[kk], src[kk + 1]); + } +} + +u8 convert_ip_addr(u8 hch, u8 mch, u8 lch) +{ + return ((key_char2num(hch) * 100) + (key_char2num(mch) * 10 ) + key_char2num(lch)); +} + +#ifdef CONFIG_PLATFORM_INTEL_BYT +#define MAC_ADDRESS_LEN 12 + +int rtw_get_mac_addr_intel(unsigned char *buf) +{ + int ret = 0; + int i; + struct file *fp = NULL; +#ifdef set_fs + mm_segment_t oldfs; +#endif + unsigned char c_mac[MAC_ADDRESS_LEN]; + char fname[]="/config/wifi/mac.txt"; + int jj,kk; + + DBG_871X("%s Enter\n", __FUNCTION__); + + ret = rtw_retrieve_from_file(fname, c_mac, MAC_ADDRESS_LEN); + if(ret < MAC_ADDRESS_LEN) + { + return -1; + } + + for( jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 2 ) + { + buf[jj] = key_2char2num(c_mac[kk], c_mac[kk+ 1]); + } + + DBG_871X("%s: read from file mac address: "MAC_FMT"\n", + __FUNCTION__, MAC_ARG(buf)); + + return 0; +} +#endif //CONFIG_PLATFORM_INTEL_BYT + +/* + * Description: + * rtw_check_invalid_mac_address: + * This is only used for checking mac address valid or not. + * + * Input: + * adapter: mac_address pointer. + * check_local_bit: check locally bit or not. + * + * Output: + * _TRUE: The mac address is invalid. + * _FALSE: The mac address is valid. + * + * Auther: Isaac.Li + */ +u8 rtw_check_invalid_mac_address(u8 *mac_addr, u8 check_local_bit) +{ + u8 null_mac_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0}; + u8 multi_mac_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + u8 res = _FALSE; + + if (_rtw_memcmp(mac_addr, null_mac_addr, ETH_ALEN)) { + res = _TRUE; + goto func_exit; + } + + if (_rtw_memcmp(mac_addr, multi_mac_addr, ETH_ALEN)) { + res = _TRUE; + goto func_exit; + } + + if (mac_addr[0] & BIT0) { + res = _TRUE; + goto func_exit; + } + + if (check_local_bit == _TRUE) { + if (mac_addr[0] & BIT1) { + res = _TRUE; + goto func_exit; + } + } + +func_exit: + return res; +} + +extern char* rtw_initmac; +/** + * rtw_macaddr_cfg - Decide the mac address used + * @out: buf to store mac address decided + * @hw_mac_addr: mac address from efuse/epprom + */ +void rtw_macaddr_cfg(u8 *out, const u8 *hw_mac_addr) +{ +#define DEFAULT_RANDOM_MACADDR 1 + u8 mac[ETH_ALEN]; + + if (out == NULL) { + rtw_warn_on(1); + return; + } + + /* Users specify the mac address */ + if (rtw_initmac) { + int jj,kk; + + for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3) + mac[jj] = key_2char2num(rtw_initmac[kk], rtw_initmac[kk + 1]); + + goto err_chk; + } + + /* platform specified */ +#ifdef CONFIG_PLATFORM_INTEL_BYT + if (rtw_get_mac_addr_intel(mac) == 0) + goto err_chk; +#endif + + /* Use the mac address stored in the Efuse */ + if (hw_mac_addr) { + _rtw_memcpy(mac, hw_mac_addr, ETH_ALEN); + goto err_chk; + } + +err_chk: + if (rtw_check_invalid_mac_address(mac, _TRUE) == _TRUE) { + #if DEFAULT_RANDOM_MACADDR + DBG_871X_LEVEL(_drv_err_, "invalid mac addr:"MAC_FMT", assign random MAC\n", MAC_ARG(mac)); + *((u32 *)(&mac[2])) = rtw_random32(); + mac[0] = 0x00; + mac[1] = 0xe0; + mac[2] = 0x4c; + #else + DBG_871X_LEVEL(_drv_err_, "invalid mac addr:"MAC_FMT", assign default one\n", MAC_ARG(mac)); + mac[0] = 0x00; + mac[1] = 0xe0; + mac[2] = 0x4c; + mac[3] = 0x87; + mac[4] = 0x00; + mac[5] = 0x00; + #endif + } + + _rtw_memcpy(out, mac, ETH_ALEN); + DBG_871X("%s mac addr:"MAC_FMT"\n", __func__, MAC_ARG(out)); +} + +#ifdef CONFIG_80211N_HT +void dump_ht_cap_ie_content(void *sel, u8 *buf, u32 buf_len) +{ + if (buf_len != 26) { + DBG_871X_SEL_NL(sel, "Invalid HT capability IE len:%d != %d\n", buf_len, 26); + return; + } + + DBG_871X_SEL_NL(sel, "HT Capabilities Info:%02x%02x\n", *(buf), *(buf+1)); + DBG_871X_SEL_NL(sel, "A-MPDU Parameters:"HT_AMPDU_PARA_FMT"\n" + , HT_AMPDU_PARA_ARG(HT_CAP_ELE_AMPDU_PARA(buf))); + DBG_871X_SEL_NL(sel, "Supported MCS Set:"HT_SUP_MCS_SET_FMT"\n" + , HT_SUP_MCS_SET_ARG(HT_CAP_ELE_SUP_MCS_SET(buf))); +} + +void dump_ht_cap_ie(void *sel, u8 *ie, u32 ie_len) +{ + u8* pos = (u8*)ie; + u16 id; + u16 len; + + u8 *ht_cap_ie; + sint ht_cap_ielen; + + ht_cap_ie = rtw_get_ie(ie, _HT_CAPABILITY_IE_, &ht_cap_ielen, ie_len); + if(!ie || ht_cap_ie != ie) + return; + + dump_ht_cap_ie_content(sel, ht_cap_ie+2, ht_cap_ielen); +} +#endif /* CONFIG_80211N_HT */ + +void dump_ies(void *sel, u8 *buf, u32 buf_len) +{ + u8* pos = (u8*)buf; + u8 id, len; + + while(pos-buf+1 0) + *ch = *(p + 2); + +#ifdef CONFIG_80211N_HT +{ + u8 *ht_cap_ie, *ht_op_ie; + int ht_cap_ielen, ht_op_ielen; + + ht_cap_ie = rtw_get_ie(ies, EID_HTCapability, &ht_cap_ielen, ies_len); + if (ht_cap_ie && ht_cap_ielen) { + if (GET_HT_CAP_ELE_CHL_WIDTH(ht_cap_ie + 2)) + *bw = CHANNEL_WIDTH_40; + } + + ht_op_ie = rtw_get_ie(ies, EID_HTInfo, &ht_op_ielen, ies_len); + if (ht_op_ie && ht_op_ielen) { + if (*ch == 0) { + *ch = GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2); + } else if (*ch != 0 && *ch != GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2)) { + DBG_871X("%s ch inconsistent, DSSS:%u, HT primary:%u\n" + , __func__, *ch, GET_HT_OP_ELE_PRI_CHL(ht_op_ie + 2)); + } + + if (!GET_HT_OP_ELE_STA_CHL_WIDTH(ht_op_ie + 2)) + *bw = CHANNEL_WIDTH_20; + + if (*bw == CHANNEL_WIDTH_40) { + switch (GET_HT_OP_ELE_2ND_CHL_OFFSET(ht_op_ie + 2)) { + case SCA: + *offset = HAL_PRIME_CHNL_OFFSET_LOWER; + break; + case SCB: + *offset = HAL_PRIME_CHNL_OFFSET_UPPER; + break; + } + } + } +} +#endif /* CONFIG_80211N_HT */ +#ifdef CONFIG_80211AC_VHT +{ + u8 *vht_op_ie; + int vht_op_ielen; + + vht_op_ie = rtw_get_ie(ies, EID_VHTOperation, &vht_op_ielen, ies_len); + if (vht_op_ie && vht_op_ielen) { + if (GET_VHT_OPERATION_ELE_CHL_WIDTH(vht_op_ie + 2) >= 1) + *bw = CHANNEL_WIDTH_80; + } +} +#endif +} + +void rtw_bss_get_chbw(WLAN_BSSID_EX *bss, u8 *ch, u8 *bw, u8 *offset) +{ + rtw_ies_get_chbw(bss->IEs + sizeof(NDIS_802_11_FIXED_IEs) + , bss->IELength - sizeof(NDIS_802_11_FIXED_IEs) + , ch, bw, offset); + + if (*ch == 0) { + *ch = bss->Configuration.DSConfig; + } else if (*ch != bss->Configuration.DSConfig) { + DBG_871X("inconsistent ch - ies:%u bss->Configuration.DSConfig:%u\n" + , *ch, bss->Configuration.DSConfig); + *ch = bss->Configuration.DSConfig; + rtw_warn_on(1); + } +} + +/** + * rtw_is_chbw_grouped - test if the two ch settings can be grouped together + * @ch_a: ch of set a + * @bw_a: bw of set a + * @offset_a: offset of set a + * @ch_b: ch of set b + * @bw_b: bw of set b + * @offset_b: offset of set b + */ +bool rtw_is_chbw_grouped(u8 ch_a, u8 bw_a, u8 offset_a + , u8 ch_b, u8 bw_b, u8 offset_b) +{ + bool is_grouped = _FALSE; + + if (ch_a != ch_b) { + /* ch is different */ + goto exit; + } else if ((bw_a == CHANNEL_WIDTH_40 || bw_a == CHANNEL_WIDTH_80) + && (bw_b == CHANNEL_WIDTH_40 || bw_b == CHANNEL_WIDTH_80) + ) { + if (offset_a != offset_b) + goto exit; + } + + is_grouped = _TRUE; + +exit: + return is_grouped; +} + +/** + * rtw_sync_chbw - obey g_ch, adjust g_bw, g_offset, bw, offset + * @req_ch: pointer of the request ch, may be modified further + * @req_bw: pointer of the request bw, may be modified further + * @req_offset: pointer of the request offset, may be modified further + * @g_ch: pointer of the ongoing group ch + * @g_bw: pointer of the ongoing group bw, may be modified further + * @g_offset: pointer of the ongoing group offset, may be modified further + */ +void rtw_sync_chbw(u8 *req_ch, u8 *req_bw, u8 *req_offset + , u8 *g_ch, u8 *g_bw, u8 *g_offset) +{ + + *req_ch = *g_ch; + + if (*req_bw == CHANNEL_WIDTH_80 && *g_ch <= 14) { + /*2.4G ch, downgrade to 40Mhz */ + *req_bw = CHANNEL_WIDTH_40; + } + + switch (*req_bw) { + case CHANNEL_WIDTH_80: + if (*g_bw == CHANNEL_WIDTH_40 || *g_bw == CHANNEL_WIDTH_80) + *req_offset = *g_offset; + else if (*g_bw == CHANNEL_WIDTH_20) + *req_offset = rtw_get_offset_by_ch(*req_ch); + + if (*req_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) { + DBG_871X_LEVEL(_drv_err_, "%s req 80MHz BW without offset, down to 20MHz\n", __func__); + rtw_warn_on(1); + *req_bw = CHANNEL_WIDTH_20; + } + break; + case CHANNEL_WIDTH_40: + if (*g_bw == CHANNEL_WIDTH_40 || *g_bw == CHANNEL_WIDTH_80) + *req_offset = *g_offset; + else if (*g_bw == CHANNEL_WIDTH_20) + *req_offset = rtw_get_offset_by_ch(*req_ch); + + if (*req_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) { + DBG_871X_LEVEL(_drv_err_, "%s req 40MHz BW without offset, down to 20MHz\n", __func__); + rtw_warn_on(1); + *req_bw = CHANNEL_WIDTH_20; + } + break; + case CHANNEL_WIDTH_20: + *req_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; + default: + DBG_871X_LEVEL(_drv_err_, "%s req unsupported BW:%u\n", __func__, *req_bw); + rtw_warn_on(1); + } + + if (*req_bw > *g_bw) { + *g_bw = *req_bw; + *g_offset = *req_offset; + } +} + +/** + * rtw_get_p2p_merged_len - Get merged ie length from muitiple p2p ies. + * @in_ie: Pointer of the first p2p ie + * @in_len: Total len of muiltiple p2p ies + * Returns: Length of merged p2p ie length + */ +u32 rtw_get_p2p_merged_ies_len(u8 *in_ie, u32 in_len) +{ + PNDIS_802_11_VARIABLE_IEs pIE; + u8 OUI[4] = { 0x50, 0x6f, 0x9a, 0x09 }; + int i=0; + int j=0, len=0; + + while( i < in_len) + { + pIE = (PNDIS_802_11_VARIABLE_IEs)(in_ie+ i); + + if( pIE->ElementID == _VENDOR_SPECIFIC_IE_ && _rtw_memcmp(pIE->data, OUI, 4) ) + { + len += pIE->Length-4; // 4 is P2P OUI length, don't count it in this loop + } + + i += (pIE->Length + 2); + } + + return len + 4; // Append P2P OUI length at last. +} + +/** + * rtw_p2p_merge_ies - Merge muitiple p2p ies into one + * @in_ie: Pointer of the first p2p ie + * @in_len: Total len of muiltiple p2p ies + * @merge_ie: Pointer of merged ie + * Returns: Length of merged p2p ie + */ +int rtw_p2p_merge_ies(u8 *in_ie, u32 in_len, u8 *merge_ie) +{ + PNDIS_802_11_VARIABLE_IEs pIE; + u8 len = 0; + u8 OUI[4] = { 0x50, 0x6f, 0x9a, 0x09 }; + u8 ELOUI[6] = { 0xDD, 0x00, 0x50, 0x6f, 0x9a, 0x09 }; //EID;Len;OUI, Len would copy at the end of function + int i=0; + + if( merge_ie != NULL) + { + //Set first P2P OUI + _rtw_memcpy(merge_ie, ELOUI, 6); + merge_ie += 6; + + while( i < in_len) + { + pIE = (PNDIS_802_11_VARIABLE_IEs)(in_ie+ i); + + // Take out the rest of P2P OUIs + if( pIE->ElementID == _VENDOR_SPECIFIC_IE_ && _rtw_memcmp(pIE->data, OUI, 4) ) + { + _rtw_memcpy( merge_ie, pIE->data +4, pIE->Length -4); + len += pIE->Length-4; + merge_ie += pIE->Length-4; + } + + i += (pIE->Length + 2); + } + + return len + 4; // 4 is for P2P OUI + + } + + return 0; +} + +void dump_p2p_ie(void *sel, u8 *ie, u32 ie_len) +{ + u8* pos = (u8*)ie; + u8 id; + u16 len; + + u8 *p2p_ie; + uint p2p_ielen; + + p2p_ie = rtw_get_p2p_ie(ie, ie_len, NULL, &p2p_ielen); + if (p2p_ie != ie || p2p_ielen == 0) + return; + + pos += 6; + while (pos - ie + 3 <= ie_len) { + id = *pos; + len = RTW_GET_LE16(pos + 1); + + DBG_871X_SEL_NL(sel, "%s ID:%u, LEN:%u%s\n", __func__, id, len + , ((pos - ie + 3 + len) <= ie_len) ? "" : "(exceed ie_len)"); + + pos += (3 + len); + } +} + +/** + * rtw_get_p2p_ie - Search P2P IE from a series of IEs + * @in_ie: Address of IEs to search + * @in_len: Length limit from in_ie + * @p2p_ie: If not NULL and P2P IE is found, P2P IE will be copied to the buf starting from p2p_ie + * @p2p_ielen: If not NULL and P2P IE is found, will set to the length of the entire P2P IE + * + * Returns: The address of the P2P IE found, or NULL + */ +u8 *rtw_get_p2p_ie(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen) +{ + uint cnt; + u8 *p2p_ie_ptr = NULL; + u8 eid, p2p_oui[4] = {0x50, 0x6F, 0x9A, 0x09}; + + if (p2p_ielen) + *p2p_ielen = 0; + + if (!in_ie || in_len < 0) { + rtw_warn_on(1); + return p2p_ie_ptr; + } + + if (in_len <= 0) + return p2p_ie_ptr; + + cnt = 0; + + while (cnt + 1 + 4 < in_len) { + eid = in_ie[cnt]; + + if (cnt + 1 + 4 >= MAX_IE_SZ) { + rtw_warn_on(1); + return NULL; + } + + if (eid == WLAN_EID_VENDOR_SPECIFIC && _rtw_memcmp(&in_ie[cnt + 2], p2p_oui, 4) == _TRUE) { + p2p_ie_ptr = in_ie + cnt; + + if (p2p_ie) + _rtw_memcpy(p2p_ie, &in_ie[cnt], in_ie[cnt + 1] + 2); + + if (p2p_ielen) + *p2p_ielen = in_ie[cnt + 1] + 2; + + break; + } else { + cnt += in_ie[cnt + 1] + 2; + } + + } + + return p2p_ie_ptr; +} + +/** + * rtw_get_p2p_attr - Search a specific P2P attribute from a given P2P IE + * @p2p_ie: Address of P2P IE to search + * @p2p_ielen: Length limit from p2p_ie + * @target_attr_id: The attribute ID of P2P attribute to search + * @buf_attr: If not NULL and the P2P attribute is found, P2P attribute will be copied to the buf starting from buf_attr + * @len_attr: If not NULL and the P2P attribute is found, will set to the length of the entire P2P attribute + * + * Returns: the address of the specific WPS attribute found, or NULL + */ +u8 *rtw_get_p2p_attr(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id ,u8 *buf_attr, u32 *len_attr) +{ + u8 *attr_ptr = NULL; + u8 *target_attr_ptr = NULL; + u8 p2p_oui[4] = {0x50, 0x6F, 0x9A, 0x09}; + + if (len_attr) + *len_attr = 0; + + if (!p2p_ie + || p2p_ielen <= 6 + || (p2p_ie[0] != WLAN_EID_VENDOR_SPECIFIC) + || (_rtw_memcmp(p2p_ie + 2, p2p_oui, 4) != _TRUE)) + return attr_ptr; + + /* 6 = 1(Element ID) + 1(Length) + 3 (OUI) + 1(OUI Type) */ + attr_ptr = p2p_ie + 6; /* goto first attr */ + + while ((attr_ptr - p2p_ie + 3) <= p2p_ielen) { + /* 3 = 1(Attribute ID) + 2(Length) */ + u8 attr_id = *attr_ptr; + u16 attr_data_len = RTW_GET_LE16(attr_ptr + 1); + u16 attr_len = attr_data_len + 3; + + if (0) + DBG_871X("%s attr_ptr:%p, id:%u, length:%u\n", __func__, attr_ptr, attr_id, attr_data_len); + + if ((attr_ptr - p2p_ie + attr_len) > p2p_ielen) + break; + + if (attr_id == target_attr_id) { + target_attr_ptr = attr_ptr; + + if (buf_attr) + _rtw_memcpy(buf_attr, attr_ptr, attr_len); + + if (len_attr) + *len_attr = attr_len; + + break; + } else { + attr_ptr += attr_len; + } + } + + return target_attr_ptr; +} + +/** + * rtw_get_p2p_attr_content - Search a specific P2P attribute content from a given P2P IE + * @p2p_ie: Address of P2P IE to search + * @p2p_ielen: Length limit from p2p_ie + * @target_attr_id: The attribute ID of P2P attribute to search + * @buf_content: If not NULL and the P2P attribute is found, P2P attribute content will be copied to the buf starting from buf_content + * @len_content: If not NULL and the P2P attribute is found, will set to the length of the P2P attribute content + * + * Returns: the address of the specific P2P attribute content found, or NULL + */ +u8 *rtw_get_p2p_attr_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id ,u8 *buf_content, uint *len_content) +{ + u8 *attr_ptr; + u32 attr_len; + + if (len_content) + *len_content = 0; + + attr_ptr = rtw_get_p2p_attr(p2p_ie, p2p_ielen, target_attr_id, NULL, &attr_len); + + if (attr_ptr && attr_len) { + if (buf_content) + _rtw_memcpy(buf_content, attr_ptr + 3, attr_len - 3); + + if (len_content) + *len_content = attr_len - 3; + + return attr_ptr + 3; + } + + return NULL; +} + +u32 rtw_set_p2p_attr_content(u8 *pbuf, u8 attr_id, u16 attr_len, u8 *pdata_attr) +{ + u32 a_len; + + *pbuf = attr_id; + + //*(u16*)(pbuf + 1) = cpu_to_le16(attr_len); + RTW_PUT_LE16(pbuf + 1, attr_len); + + if(pdata_attr) + _rtw_memcpy(pbuf + 3, pdata_attr, attr_len); + + a_len = attr_len + 3; + + return a_len; +} + +uint rtw_del_p2p_ie(u8 *ies, uint ies_len_ori, const char *msg) +{ +#define DBG_DEL_P2P_IE 0 + + u8 *target_ie; + u32 target_ie_len; + uint ies_len = ies_len_ori; + int index = 0; + + while (1) { + target_ie = rtw_get_p2p_ie(ies, ies_len, NULL, &target_ie_len); + if (target_ie && target_ie_len) { + u8 *next_ie = target_ie + target_ie_len; + uint remain_len = ies_len - (next_ie - ies); + + if (DBG_DEL_P2P_IE && msg) { + DBG_871X("%s %d before\n", __func__, index); + dump_ies(RTW_DBGDUMP, ies, ies_len); + + DBG_871X("ies:%p, ies_len:%u\n", ies, ies_len); + DBG_871X("target_ie:%p, target_ie_len:%u\n", target_ie, target_ie_len); + DBG_871X("next_ie:%p, remain_len:%u\n", next_ie, remain_len); + } + + _rtw_memmove(target_ie, next_ie, remain_len); + _rtw_memset(target_ie + remain_len, 0, target_ie_len); + ies_len -= target_ie_len; + + if (DBG_DEL_P2P_IE && msg) { + DBG_871X("%s %d after\n", __func__, index); + dump_ies(RTW_DBGDUMP, ies, ies_len); + } + + index++; + } else { + break; + } + } + + return ies_len; +} + +uint rtw_del_p2p_attr(u8 *ie, uint ielen_ori, u8 attr_id) +{ +#define DBG_DEL_P2P_ATTR 0 + + u8 *target_attr; + u32 target_attr_len; + uint ielen = ielen_ori; + int index = 0; + + while(1) { + target_attr = rtw_get_p2p_attr(ie, ielen, attr_id, NULL, &target_attr_len); + if (target_attr && target_attr_len) { + u8 *next_attr = target_attr + target_attr_len; + uint remain_len = ielen - (next_attr - ie); + + if (DBG_DEL_P2P_ATTR) { + DBG_871X("%s %d before\n", __func__, index); + dump_ies(RTW_DBGDUMP, ie, ielen); + + DBG_871X("ie:%p, ielen:%u\n", ie, ielen); + DBG_871X("target_attr:%p, target_attr_len:%u\n", target_attr, target_attr_len); + DBG_871X("next_attr:%p, remain_len:%u\n", next_attr, remain_len); + } + + _rtw_memmove(target_attr, next_attr, remain_len); + _rtw_memset(target_attr + remain_len, 0, target_attr_len); + *(ie + 1) -= target_attr_len; + ielen -= target_attr_len; + + if (DBG_DEL_P2P_ATTR) { + DBG_871X("%s %d after\n", __func__, index); + dump_ies(RTW_DBGDUMP, ie, ielen); + } + + index++; + } else { + break; + } + } + + return ielen; +} + +inline u8 *rtw_bss_ex_get_p2p_ie(WLAN_BSSID_EX *bss_ex, u8 *p2p_ie, uint *p2p_ielen) +{ + return rtw_get_p2p_ie(BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex), p2p_ie, p2p_ielen); +} + +void rtw_bss_ex_del_p2p_ie(WLAN_BSSID_EX *bss_ex) +{ +#define DBG_BSS_EX_DEL_P2P_IE 0 + + u8 *ies = BSS_EX_TLV_IES(bss_ex); + uint ies_len_ori = BSS_EX_TLV_IES_LEN(bss_ex); + uint ies_len; + + ies_len = rtw_del_p2p_ie(ies, ies_len_ori, DBG_BSS_EX_DEL_P2P_IE ? __func__ : NULL); + bss_ex->IELength -= ies_len_ori - ies_len; +} + +void rtw_bss_ex_del_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id) +{ +#define DBG_BSS_EX_DEL_P2P_ATTR 0 + + u8 *ies = BSS_EX_TLV_IES(bss_ex); + uint ies_len = BSS_EX_TLV_IES_LEN(bss_ex); + + u8 *ie; + uint ie_len, ie_len_ori; + + int index = 0; + + while (1) { + ie = rtw_get_p2p_ie(ies, ies_len, NULL, &ie_len_ori); + if (ie) { + u8 *next_ie_ori = ie + ie_len_ori; + uint remain_len = bss_ex->IELength - (next_ie_ori - bss_ex->IEs); + u8 has_target_attr = 0; + + if (DBG_BSS_EX_DEL_P2P_ATTR) { + if (rtw_get_p2p_attr(ie, ie_len_ori, attr_id, NULL, NULL)) { + DBG_871X("%s %d before\n", __func__, index); + dump_ies(RTW_DBGDUMP, BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex)); + + DBG_871X("ies:%p, ies_len:%u\n", ies, ies_len); + DBG_871X("ie:%p, ie_len_ori:%u\n", ie, ie_len_ori); + DBG_871X("next_ie_ori:%p, remain_len:%u\n", next_ie_ori, remain_len); + has_target_attr = 1; + } + } + + ie_len = rtw_del_p2p_attr(ie, ie_len_ori, attr_id); + if (ie_len != ie_len_ori) { + u8 *next_ie = ie + ie_len; + + _rtw_memmove(next_ie, next_ie_ori, remain_len); + _rtw_memset(next_ie + remain_len, 0, ie_len_ori - ie_len); + bss_ex->IELength -= ie_len_ori - ie_len; + + ies = next_ie; + } else { + ies = next_ie_ori; + } + + if (DBG_BSS_EX_DEL_P2P_ATTR) { + if (has_target_attr) { + DBG_871X("%s %d after\n", __func__, index); + dump_ies(RTW_DBGDUMP, BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex)); + } + } + + ies_len = remain_len; + + index++; + } else { + break; + } + } +} + +void dump_wfd_ie(void *sel, u8 *ie, u32 ie_len) +{ + u8* pos = (u8*)ie; + u8 id; + u16 len; + + u8 *wfd_ie; + uint wfd_ielen; + + wfd_ie = rtw_get_wfd_ie(ie, ie_len, NULL, &wfd_ielen); + if (wfd_ie != ie || wfd_ielen == 0) + return; + + pos += 6; + while (pos - ie + 3 <= ie_len) { + id = *pos; + len = RTW_GET_BE16(pos + 1); + + DBG_871X_SEL_NL(sel, "%s ID:%u, LEN:%u%s\n", __func__, id, len + , ((pos - ie + 3 + len) <= ie_len) ? "" : "(exceed ie_len)"); + + pos += (3 + len); + } +} + +/** + * rtw_get_wfd_ie - Search WFD IE from a series of IEs + * @in_ie: Address of IEs to search + * @in_len: Length limit from in_ie + * @wfd_ie: If not NULL and WFD IE is found, WFD IE will be copied to the buf starting from wfd_ie + * @wfd_ielen: If not NULL and WFD IE is found, will set to the length of the entire WFD IE + * + * Returns: The address of the P2P IE found, or NULL + */ +u8 *rtw_get_wfd_ie(u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen) +{ + uint cnt; + u8 *wfd_ie_ptr = NULL; + u8 eid, wfd_oui[4] = {0x50, 0x6F, 0x9A, 0x0A}; + + if (wfd_ielen) + *wfd_ielen = 0; + + if (!in_ie || in_len < 0) { + rtw_warn_on(1); + return wfd_ie_ptr; + } + + if (in_len <= 0) + return wfd_ie_ptr; + + cnt = 0; + + while (cnt + 1 + 4 < in_len) { + eid = in_ie[cnt]; + + if (cnt + 1 + 4 >= MAX_IE_SZ) { + rtw_warn_on(1); + return NULL; + } + + if (eid == WLAN_EID_VENDOR_SPECIFIC && _rtw_memcmp(&in_ie[cnt + 2], wfd_oui, 4) == _TRUE) { + wfd_ie_ptr = in_ie + cnt; + + if (wfd_ie) + _rtw_memcpy(wfd_ie, &in_ie[cnt], in_ie[cnt + 1] + 2); + + if (wfd_ielen) + *wfd_ielen = in_ie[cnt + 1] + 2; + + break; + } else { + cnt += in_ie[cnt + 1] + 2; + } + + } + + return wfd_ie_ptr; +} + +/** + * rtw_get_wfd_attr - Search a specific WFD attribute from a given WFD IE + * @wfd_ie: Address of WFD IE to search + * @wfd_ielen: Length limit from wfd_ie + * @target_attr_id: The attribute ID of WFD attribute to search + * @buf_attr: If not NULL and the WFD attribute is found, WFD attribute will be copied to the buf starting from buf_attr + * @len_attr: If not NULL and the WFD attribute is found, will set to the length of the entire WFD attribute + * + * Returns: the address of the specific WPS attribute found, or NULL + */ +u8 *rtw_get_wfd_attr(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_attr, u32 *len_attr) +{ + u8 *attr_ptr = NULL; + u8 *target_attr_ptr = NULL; + u8 wfd_oui[4] = {0x50, 0x6F, 0x9A, 0x0A}; + + if (len_attr) + *len_attr = 0; + + if (!wfd_ie + || wfd_ielen <= 6 + || (wfd_ie[0] != WLAN_EID_VENDOR_SPECIFIC) + || (_rtw_memcmp(wfd_ie + 2, wfd_oui, 4) != _TRUE)) + return attr_ptr; + + /* 6 = 1(Element ID) + 1(Length) + 3 (OUI) + 1(OUI Type) */ + attr_ptr = wfd_ie + 6; /* goto first attr */ + + while ((attr_ptr - wfd_ie + 3) <= wfd_ielen) { + /* 3 = 1(Attribute ID) + 2(Length) */ + u8 attr_id = *attr_ptr; + u16 attr_data_len = RTW_GET_BE16(attr_ptr + 1); + u16 attr_len = attr_data_len + 3; + + if (0) + DBG_871X("%s attr_ptr:%p, id:%u, length:%u\n", __func__, attr_ptr, attr_id, attr_data_len); + + if ((attr_ptr - wfd_ie + attr_len) > wfd_ielen) + break; + + if (attr_id == target_attr_id) { + target_attr_ptr = attr_ptr; + + if (buf_attr) + _rtw_memcpy(buf_attr, attr_ptr, attr_len); + + if (len_attr) + *len_attr = attr_len; + + break; + } else { + attr_ptr += attr_len; + } + } + + return target_attr_ptr; +} + +/** + * rtw_get_wfd_attr_content - Search a specific WFD attribute content from a given WFD IE + * @wfd_ie: Address of WFD IE to search + * @wfd_ielen: Length limit from wfd_ie + * @target_attr_id: The attribute ID of WFD attribute to search + * @buf_content: If not NULL and the WFD attribute is found, WFD attribute content will be copied to the buf starting from buf_content + * @len_content: If not NULL and the WFD attribute is found, will set to the length of the WFD attribute content + * + * Returns: the address of the specific WFD attribute content found, or NULL + */ +u8 *rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_content, uint *len_content) +{ + u8 *attr_ptr; + u32 attr_len; + + if (len_content) + *len_content = 0; + + attr_ptr = rtw_get_wfd_attr(wfd_ie, wfd_ielen, target_attr_id, NULL, &attr_len); + + if (attr_ptr && attr_len) { + if (buf_content) + _rtw_memcpy(buf_content, attr_ptr + 3, attr_len - 3); + + if (len_content) + *len_content = attr_len - 3; + + return attr_ptr + 3; + } + + return NULL; +} + +uint rtw_del_wfd_ie(u8 *ies, uint ies_len_ori, const char *msg) +{ +#define DBG_DEL_WFD_IE 0 + + u8 *target_ie; + u32 target_ie_len; + uint ies_len = ies_len_ori; + int index = 0; + + while (1) { + target_ie = rtw_get_wfd_ie(ies, ies_len, NULL, &target_ie_len); + if (target_ie && target_ie_len) { + u8 *next_ie = target_ie + target_ie_len; + uint remain_len = ies_len - (next_ie - ies); + + if (DBG_DEL_WFD_IE && msg) { + DBG_871X("%s %d before\n", __func__, index); + dump_ies(RTW_DBGDUMP, ies, ies_len); + + DBG_871X("ies:%p, ies_len:%u\n", ies, ies_len); + DBG_871X("target_ie:%p, target_ie_len:%u\n", target_ie, target_ie_len); + DBG_871X("next_ie:%p, remain_len:%u\n", next_ie, remain_len); + } + + _rtw_memmove(target_ie, next_ie, remain_len); + _rtw_memset(target_ie + remain_len, 0, target_ie_len); + ies_len -= target_ie_len; + + if (DBG_DEL_WFD_IE && msg) { + DBG_871X("%s %d after\n", __func__, index); + dump_ies(RTW_DBGDUMP, ies, ies_len); + } + + index++; + } else { + break; + } + } + + return ies_len; +} + +uint rtw_del_wfd_attr(u8 *ie, uint ielen_ori, u8 attr_id) +{ +#define DBG_DEL_WFD_ATTR 0 + + u8 *target_attr; + u32 target_attr_len; + uint ielen = ielen_ori; + int index = 0; + + while (1) { + target_attr = rtw_get_wfd_attr(ie, ielen, attr_id, NULL, &target_attr_len); + if (target_attr && target_attr_len) { + u8 *next_attr = target_attr + target_attr_len; + uint remain_len = ielen - (next_attr - ie); + + if (DBG_DEL_WFD_ATTR) { + DBG_871X("%s %d before\n", __func__, index); + dump_ies(RTW_DBGDUMP, ie, ielen); + + DBG_871X("ie:%p, ielen:%u\n", ie, ielen); + DBG_871X("target_attr:%p, target_attr_len:%u\n", target_attr, target_attr_len); + DBG_871X("next_attr:%p, remain_len:%u\n", next_attr, remain_len); + } + + _rtw_memmove(target_attr, next_attr, remain_len); + _rtw_memset(target_attr + remain_len, 0, target_attr_len); + *(ie + 1) -= target_attr_len; + ielen -= target_attr_len; + + if (DBG_DEL_WFD_ATTR) { + DBG_871X("%s %d after\n", __func__, index); + dump_ies(RTW_DBGDUMP, ie, ielen); + } + + index++; + } else { + break; + } + } + + return ielen; +} + +inline u8 *rtw_bss_ex_get_wfd_ie(WLAN_BSSID_EX *bss_ex, u8 *wfd_ie, uint *wfd_ielen) +{ + return rtw_get_wfd_ie(BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex), wfd_ie, wfd_ielen); +} + +void rtw_bss_ex_del_wfd_ie(WLAN_BSSID_EX *bss_ex) +{ +#define DBG_BSS_EX_DEL_WFD_IE 0 + u8 *ies = BSS_EX_TLV_IES(bss_ex); + uint ies_len_ori = BSS_EX_TLV_IES_LEN(bss_ex); + uint ies_len; + + ies_len = rtw_del_wfd_ie(ies, ies_len_ori, DBG_BSS_EX_DEL_WFD_IE ? __func__ : NULL); + bss_ex->IELength -= ies_len_ori - ies_len; +} + +void rtw_bss_ex_del_wfd_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id) +{ +#define DBG_BSS_EX_DEL_WFD_ATTR 0 + + u8 *ies = BSS_EX_TLV_IES(bss_ex); + uint ies_len = BSS_EX_TLV_IES_LEN(bss_ex); + + u8 *ie; + uint ie_len, ie_len_ori; + + int index = 0; + + while (1) { + ie = rtw_get_wfd_ie(ies, ies_len, NULL, &ie_len_ori); + if (ie) { + u8 *next_ie_ori = ie + ie_len_ori; + uint remain_len = bss_ex->IELength - (next_ie_ori - bss_ex->IEs); + u8 has_target_attr = 0; + + if (DBG_BSS_EX_DEL_WFD_ATTR) { + if (rtw_get_wfd_attr(ie, ie_len_ori, attr_id, NULL, NULL)) { + DBG_871X("%s %d before\n", __func__, index); + dump_ies(RTW_DBGDUMP, BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex)); + + DBG_871X("ies:%p, ies_len:%u\n", ies, ies_len); + DBG_871X("ie:%p, ie_len_ori:%u\n", ie, ie_len_ori); + DBG_871X("next_ie_ori:%p, remain_len:%u\n", next_ie_ori, remain_len); + has_target_attr = 1; + } + } + + ie_len = rtw_del_wfd_attr(ie, ie_len_ori, attr_id); + if (ie_len != ie_len_ori) { + u8 *next_ie = ie + ie_len; + + _rtw_memmove(next_ie, next_ie_ori, remain_len); + _rtw_memset(next_ie + remain_len, 0, ie_len_ori - ie_len); + bss_ex->IELength -= ie_len_ori - ie_len; + + ies = next_ie; + } else { + ies = next_ie_ori; + } + + if (DBG_BSS_EX_DEL_WFD_ATTR) { + if (has_target_attr) { + DBG_871X("%s %d after\n", __func__, index); + dump_ies(RTW_DBGDUMP, BSS_EX_TLV_IES(bss_ex), BSS_EX_TLV_IES_LEN(bss_ex)); + } + } + + ies_len = remain_len; + + index++; + } else { + break; + } + } +} + +//Baron adds to avoid FreeBSD warning +int ieee80211_is_empty_essid(const char *essid, int essid_len) +{ + /* Single white space is for Linksys APs */ + if (essid_len == 1 && essid[0] == ' ') + return 1; + + /* Otherwise, if the entire essid is 0, we assume it is hidden */ + while (essid_len) { + essid_len--; + if (essid[essid_len] != '\0') + return 0; + } + + return 1; +} + +int ieee80211_get_hdrlen(u16 fc) +{ + int hdrlen = 24; + + switch (WLAN_FC_GET_TYPE(fc)) { + case RTW_IEEE80211_FTYPE_DATA: + if (fc & RTW_IEEE80211_STYPE_QOS_DATA) + hdrlen += 2; + if ((fc & RTW_IEEE80211_FCTL_FROMDS) && (fc & RTW_IEEE80211_FCTL_TODS)) + hdrlen += 6; /* Addr4 */ + break; + case RTW_IEEE80211_FTYPE_CTL: + switch (WLAN_FC_GET_STYPE(fc)) { + case RTW_IEEE80211_STYPE_CTS: + case RTW_IEEE80211_STYPE_ACK: + hdrlen = 10; + break; + default: + hdrlen = 16; + break; + } + break; + } + + return hdrlen; +} + +int rtw_get_cipher_info(struct wlan_network *pnetwork) +{ + u32 wpa_ielen; + unsigned char *pbuf; + int group_cipher = 0, pairwise_cipher = 0, is8021x = 0; + int ret = _FAIL; + pbuf = rtw_get_wpa_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength-12); + + if(pbuf && (wpa_ielen>0)) { + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_get_cipher_info: wpa_ielen: %d", wpa_ielen)); + if (_SUCCESS == rtw_parse_wpa_ie(pbuf, wpa_ielen+2, &group_cipher, &pairwise_cipher, &is8021x)) { + + pnetwork->BcnInfo.pairwise_cipher = pairwise_cipher; + pnetwork->BcnInfo.group_cipher = group_cipher; + pnetwork->BcnInfo.is_8021x = is8021x; + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("%s: pnetwork->pairwise_cipher: %d, is_8021x is %d", + __func__, pnetwork->BcnInfo.pairwise_cipher, pnetwork->BcnInfo.is_8021x)); + ret = _SUCCESS; + } + } else { + + pbuf = rtw_get_wpa2_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength-12); + + if(pbuf && (wpa_ielen>0)) { + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("get RSN IE\n")); + if (_SUCCESS == rtw_parse_wpa2_ie(pbuf, wpa_ielen+2, &group_cipher, &pairwise_cipher, &is8021x)) { + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("get RSN IE OK!!!\n")); + pnetwork->BcnInfo.pairwise_cipher = pairwise_cipher; + pnetwork->BcnInfo.group_cipher = group_cipher; + pnetwork->BcnInfo.is_8021x = is8021x; + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("%s: pnetwork->pairwise_cipher: %d," + "pnetwork->group_cipher is %d, is_8021x is %d", __func__, pnetwork->BcnInfo.pairwise_cipher, + pnetwork->BcnInfo.group_cipher,pnetwork->BcnInfo.is_8021x)); + ret = _SUCCESS; + } + } + } + + return ret; +} + +void rtw_get_bcn_info(struct wlan_network *pnetwork) +{ + unsigned short cap = 0; + u8 bencrypt = 0; + //u8 wpa_ie[255],rsn_ie[255]; + u16 wpa_len=0,rsn_len=0; + struct HT_info_element *pht_info = NULL; + struct rtw_ieee80211_ht_cap *pht_cap = NULL; + unsigned int len; + unsigned char *p; + + _rtw_memcpy((u8 *)&cap, rtw_get_capability_from_ie(pnetwork->network.IEs), 2); + cap = le16_to_cpu(cap); + if (cap & WLAN_CAPABILITY_PRIVACY) { + bencrypt = 1; + pnetwork->network.Privacy = 1; + } else { + pnetwork->BcnInfo.encryp_protocol = ENCRYP_PROTOCOL_OPENSYS; + } + rtw_get_sec_ie(pnetwork->network.IEs ,pnetwork->network.IELength,NULL,&rsn_len,NULL,&wpa_len); + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_get_bcn_info: ssid=%s\n",pnetwork->network.Ssid.Ssid)); + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_get_bcn_info: wpa_len=%d rsn_len=%d\n",wpa_len,rsn_len)); + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_get_bcn_info: ssid=%s\n",pnetwork->network.Ssid.Ssid)); + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_get_bcn_info: wpa_len=%d rsn_len=%d\n",wpa_len,rsn_len)); + + if (rsn_len > 0) { + pnetwork->BcnInfo.encryp_protocol = ENCRYP_PROTOCOL_WPA2; + } else if (wpa_len > 0) { + pnetwork->BcnInfo.encryp_protocol = ENCRYP_PROTOCOL_WPA; + } else { + if (bencrypt) + pnetwork->BcnInfo.encryp_protocol = ENCRYP_PROTOCOL_WEP; + } + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_get_bcn_info: pnetwork->encryp_protocol is %x\n", + pnetwork->BcnInfo.encryp_protocol)); + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_get_bcn_info: pnetwork->encryp_protocol is %x\n", + pnetwork->BcnInfo.encryp_protocol)); + rtw_get_cipher_info(pnetwork); + + /* get bwmode and ch_offset */ + /* parsing HT_CAP_IE */ + p = rtw_get_ie(pnetwork->network.IEs + _FIXED_IE_LENGTH_, _HT_CAPABILITY_IE_, &len, pnetwork->network.IELength - _FIXED_IE_LENGTH_); + if(p && len>0) { + pht_cap = (struct rtw_ieee80211_ht_cap *)(p + 2); + pnetwork->BcnInfo.ht_cap_info = pht_cap->cap_info; + } else { + pnetwork->BcnInfo.ht_cap_info = 0; + } + /* parsing HT_INFO_IE */ + p = rtw_get_ie(pnetwork->network.IEs + _FIXED_IE_LENGTH_, _HT_ADD_INFO_IE_, &len, pnetwork->network.IELength - _FIXED_IE_LENGTH_); + if(p && len>0) { + pht_info = (struct HT_info_element *)(p + 2); + pnetwork->BcnInfo.ht_info_infos_0 = pht_info->infos[0]; + } else { + pnetwork->BcnInfo.ht_info_infos_0 = 0; + } +} + +u8 rtw_ht_mcsset_to_nss(u8 *supp_mcs_set) +{ + u8 nss = 1; + + if (supp_mcs_set[3]) + nss = 4; + else if (supp_mcs_set[2]) + nss = 3; + else if (supp_mcs_set[1]) + nss = 2; + else if (supp_mcs_set[0]) + nss = 1; + else + DBG_871X("%s,%d, warning! supp_mcs_set is zero\n", __func__, __LINE__); + /* DBG_871X("%s HT: %dSS\n", __FUNCTION__, nss); */ + return nss; +} + +//show MCS rate, unit: 100Kbps +u16 rtw_mcs_rate(u8 rf_type, u8 bw_40MHz, u8 short_GI, unsigned char * MCS_rate) +{ + u16 max_rate = 0; + + /*MCS_rate[2] = 3T3R , MCS_rate[1] = 2T2R , MCS_rate[0] = 1T1R*/ + if (MCS_rate[2]) { + if (MCS_rate[2] & BIT(7)) + max_rate = (bw_40MHz) ? ((short_GI)?4500:4050):((short_GI)?2167:1950); + else if (MCS_rate[2] & BIT(6)) + max_rate = (bw_40MHz) ? ((short_GI)?4050:3645):((short_GI)?1950:1750); + else if (MCS_rate[2] & BIT(5)) + max_rate = (bw_40MHz) ? ((short_GI)?3600:3240):((short_GI)?1733:1560); + else if (MCS_rate[2] & BIT(4)) + max_rate = (bw_40MHz) ? ((short_GI)?2700:2430):((short_GI)?1300:1170); + else if (MCS_rate[2] & BIT(3)) + max_rate = (bw_40MHz) ? ((short_GI)?1800:1620):((short_GI)?867:780); + else if (MCS_rate[2] & BIT(2)) + max_rate = (bw_40MHz) ? ((short_GI)?1350:1215):((short_GI)?650:585); + else if (MCS_rate[2] & BIT(1)) + max_rate = (bw_40MHz) ? ((short_GI)?900:810):((short_GI)?433:390); + else if (MCS_rate[2] & BIT(0)) + max_rate = (bw_40MHz) ? ((short_GI)?450:405):((short_GI)?217:195); + } else if (MCS_rate[1]) { + if(MCS_rate[1] & BIT(7)) + max_rate = (bw_40MHz) ? ((short_GI)?3000:2700):((short_GI)?1444:1300); + else if(MCS_rate[1] & BIT(6)) + max_rate = (bw_40MHz) ? ((short_GI)?2700:2430):((short_GI)?1300:1170); + else if(MCS_rate[1] & BIT(5)) + max_rate = (bw_40MHz) ? ((short_GI)?2400:2160):((short_GI)?1156:1040); + else if(MCS_rate[1] & BIT(4)) + max_rate = (bw_40MHz) ? ((short_GI)?1800:1620):((short_GI)?867:780); + else if(MCS_rate[1] & BIT(3)) + max_rate = (bw_40MHz) ? ((short_GI)?1200:1080):((short_GI)?578:520); + else if(MCS_rate[1] & BIT(2)) + max_rate = (bw_40MHz) ? ((short_GI)?900:810):((short_GI)?433:390); + else if(MCS_rate[1] & BIT(1)) + max_rate = (bw_40MHz) ? ((short_GI)?600:540):((short_GI)?289:260); + else if(MCS_rate[1] & BIT(0)) + max_rate = (bw_40MHz) ? ((short_GI)?300:270):((short_GI)?144:130); + } else { + if(MCS_rate[0] & BIT(7)) + max_rate = (bw_40MHz) ? ((short_GI)?1500:1350):((short_GI)?722:650); + else if(MCS_rate[0] & BIT(6)) + max_rate = (bw_40MHz) ? ((short_GI)?1350:1215):((short_GI)?650:585); + else if(MCS_rate[0] & BIT(5)) + max_rate = (bw_40MHz) ? ((short_GI)?1200:1080):((short_GI)?578:520); + else if(MCS_rate[0] & BIT(4)) + max_rate = (bw_40MHz) ? ((short_GI)?900:810):((short_GI)?433:390); + else if(MCS_rate[0] & BIT(3)) + max_rate = (bw_40MHz) ? ((short_GI)?600:540):((short_GI)?289:260); + else if(MCS_rate[0] & BIT(2)) + max_rate = (bw_40MHz) ? ((short_GI)?450:405):((short_GI)?217:195); + else if(MCS_rate[0] & BIT(1)) + max_rate = (bw_40MHz) ? ((short_GI)?300:270):((short_GI)?144:130); + else if(MCS_rate[0] & BIT(0)) + max_rate = (bw_40MHz) ? ((short_GI)?150:135):((short_GI)?72:65); + } + + return max_rate; +} + +int rtw_action_frame_parse(const u8 *frame, u32 frame_len, u8* category, u8 *action) +{ + const u8 *frame_body = frame + sizeof(struct rtw_ieee80211_hdr_3addr); + u16 fc; + u8 c; + u8 a = ACT_PUBLIC_MAX; + + fc = le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)frame)->frame_ctl); + + if ((fc & (RTW_IEEE80211_FCTL_FTYPE|RTW_IEEE80211_FCTL_STYPE)) + != (RTW_IEEE80211_FTYPE_MGMT|RTW_IEEE80211_STYPE_ACTION) + ) + { + return _FALSE; + } + + c = frame_body[0]; + + switch(c) { + case RTW_WLAN_CATEGORY_P2P: /* vendor-specific */ + break; + default: + a = frame_body[1]; + } + + if (category) + *category = c; + if (action) + *action = a; + + return _TRUE; +} + +static const char *_action_public_str[] = { + "ACT_PUB_BSSCOEXIST", + "ACT_PUB_DSE_ENABLE", + "ACT_PUB_DSE_DEENABLE", + "ACT_PUB_DSE_REG_LOCATION", + "ACT_PUB_EXT_CHL_SWITCH", + "ACT_PUB_DSE_MSR_REQ", + "ACT_PUB_DSE_MSR_RPRT", + "ACT_PUB_MP", + "ACT_PUB_DSE_PWR_CONSTRAINT", + "ACT_PUB_VENDOR", + "ACT_PUB_GAS_INITIAL_REQ", + "ACT_PUB_GAS_INITIAL_RSP", + "ACT_PUB_GAS_COMEBACK_REQ", + "ACT_PUB_GAS_COMEBACK_RSP", + "ACT_PUB_TDLS_DISCOVERY_RSP", + "ACT_PUB_LOCATION_TRACK", + "ACT_PUB_RSVD", +}; + +const char *action_public_str(u8 action) +{ + action = (action >= ACT_PUBLIC_MAX) ? ACT_PUBLIC_MAX : action; + return _action_public_str[action]; +} + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_io.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_io.c new file mode 100644 index 000000000..d08c16dac --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_io.c @@ -0,0 +1,737 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +/* + +The purpose of rtw_io.c + +a. provides the API + +b. provides the protocol engine + +c. provides the software interface between caller and the hardware interface + + +Compiler Flag Option: + +1. CONFIG_SDIO_HCI: + a. USE_SYNC_IRP: Only sync operations are provided. + b. USE_ASYNC_IRP:Both sync/async operations are provided. + +2. CONFIG_USB_HCI: + a. USE_ASYNC_IRP: Both sync/async operations are provided. + +3. CONFIG_CFIO_HCI: + b. USE_SYNC_IRP: Only sync operations are provided. + + +Only sync read/rtw_write_mem operations are provided. + +jackson@realtek.com.tw + +*/ + +#define _RTW_IO_C_ + +#include +#include + +#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) +#error "Shall be Linux or Windows, but not both!\n" +#endif + +#ifdef CONFIG_SDIO_HCI +#define rtw_le16_to_cpu(val) val +#define rtw_le32_to_cpu(val) val +#define rtw_cpu_to_le16(val) val +#define rtw_cpu_to_le32(val) val +#else +#define rtw_le16_to_cpu(val) le16_to_cpu(val) +#define rtw_le32_to_cpu(val) le32_to_cpu(val) +#define rtw_cpu_to_le16(val) cpu_to_le16(val) +#define rtw_cpu_to_le32(val) cpu_to_le32(val) +#endif + + +u8 _rtw_read8(_adapter *adapter, u32 addr) +{ + u8 r_val; + //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + u8 (*_read8)(struct intf_hdl *pintfhdl, u32 addr); + _func_enter_; + _read8 = pintfhdl->io_ops._read8; + + r_val = _read8(pintfhdl, addr); + _func_exit_; + return r_val; +} + +u16 _rtw_read16(_adapter *adapter, u32 addr) +{ + u16 r_val; + //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + u16 (*_read16)(struct intf_hdl *pintfhdl, u32 addr); + _func_enter_; + _read16 = pintfhdl->io_ops._read16; + + r_val = _read16(pintfhdl, addr); + _func_exit_; + return rtw_le16_to_cpu(r_val); +} + +u32 _rtw_read32(_adapter *adapter, u32 addr) +{ + u32 r_val; + //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + u32 (*_read32)(struct intf_hdl *pintfhdl, u32 addr); + _func_enter_; + _read32 = pintfhdl->io_ops._read32; + + r_val = _read32(pintfhdl, addr); + _func_exit_; + return rtw_le32_to_cpu(r_val); + +} + +int _rtw_write8(_adapter *adapter, u32 addr, u8 val) +{ + //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val); + int ret; + _func_enter_; + _write8 = pintfhdl->io_ops._write8; + + ret = _write8(pintfhdl, addr, val); + _func_exit_; + + return RTW_STATUS_CODE(ret); +} +int _rtw_write16(_adapter *adapter, u32 addr, u16 val) +{ + //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val); + int ret; + _func_enter_; + _write16 = pintfhdl->io_ops._write16; + + val = rtw_cpu_to_le16(val); + ret = _write16(pintfhdl, addr, val); + _func_exit_; + + return RTW_STATUS_CODE(ret); +} +int _rtw_write32(_adapter *adapter, u32 addr, u32 val) +{ + //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val); + int ret; + _func_enter_; + _write32 = pintfhdl->io_ops._write32; + + val = rtw_cpu_to_le32(val); + ret = _write32(pintfhdl, addr, val); + _func_exit_; + + return RTW_STATUS_CODE(ret); +} + +int _rtw_writeN(_adapter *adapter, u32 addr ,u32 length , u8 *pdata) +{ + //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = (struct intf_hdl*)(&(pio_priv->intf)); + int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr,u32 length, u8 *pdata); + int ret; + _func_enter_; + _writeN = pintfhdl->io_ops._writeN; + + ret = _writeN(pintfhdl, addr,length,pdata); + _func_exit_; + + return RTW_STATUS_CODE(ret); +} + +#ifdef CONFIG_SDIO_HCI +u8 _rtw_sd_f0_read8(_adapter *adapter, u32 addr) +{ + u8 r_val = 0x00; + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + u8 (*_sd_f0_read8)(struct intf_hdl *pintfhdl, u32 addr); + + _func_enter_; + _sd_f0_read8 = pintfhdl->io_ops._sd_f0_read8; + + if (_sd_f0_read8) + r_val = _sd_f0_read8(pintfhdl, addr); + else + DBG_871X_LEVEL(_drv_warning_, FUNC_ADPT_FMT" _sd_f0_read8 callback is NULL\n", FUNC_ADPT_ARG(adapter)); + + _func_exit_; + return r_val; +} + +#ifdef CONFIG_SDIO_INDIRECT_ACCESS +u8 _rtw_sd_iread8(_adapter *adapter, u32 addr) +{ + u8 r_val = 0x00; + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + u8 (*_sd_iread8)(struct intf_hdl *pintfhdl, u32 addr); + + _sd_iread8 = pintfhdl->io_ops._sd_iread8; + + if (_sd_iread8) + r_val = _sd_iread8(pintfhdl, addr); + else + DBG_871X_LEVEL(_drv_err_, FUNC_ADPT_FMT" _sd_iread8 callback is NULL\n", FUNC_ADPT_ARG(adapter)); + + return r_val; +} + +u16 _rtw_sd_iread16(_adapter *adapter, u32 addr) +{ + u16 r_val = 0x00; + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + u16 (*_sd_iread16)(struct intf_hdl *pintfhdl, u32 addr); + + _sd_iread16 = pintfhdl->io_ops._sd_iread16; + + if (_sd_iread16) + r_val = _sd_iread16(pintfhdl, addr); + else + DBG_871X_LEVEL(_drv_err_, FUNC_ADPT_FMT" _sd_iread16 callback is NULL\n", FUNC_ADPT_ARG(adapter)); + + return r_val; +} + +u32 _rtw_sd_iread32(_adapter *adapter, u32 addr) +{ + u32 r_val = 0x00; + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + u32 (*_sd_iread32)(struct intf_hdl *pintfhdl, u32 addr); + + _sd_iread32 = pintfhdl->io_ops._sd_iread32; + + if (_sd_iread32) + r_val = _sd_iread32(pintfhdl, addr); + else + DBG_871X_LEVEL(_drv_err_, FUNC_ADPT_FMT" _sd_iread32 callback is NULL\n", FUNC_ADPT_ARG(adapter)); + + return r_val; +} + +int _rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val) +{ + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + int (*_sd_iwrite8)(struct intf_hdl *pintfhdl, u32 addr, u8 val); + int ret = -1; + + _sd_iwrite8 = pintfhdl->io_ops._sd_iwrite8; + + if (_sd_iwrite8) + ret = _sd_iwrite8(pintfhdl, addr, val); + else + DBG_871X_LEVEL(_drv_err_, FUNC_ADPT_FMT" _sd_iwrite8 callback is NULL\n", FUNC_ADPT_ARG(adapter)); + + return RTW_STATUS_CODE(ret); +} + +int _rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val) +{ + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + int (*_sd_iwrite16)(struct intf_hdl *pintfhdl, u32 addr, u16 val); + int ret = -1; + + _sd_iwrite16 = pintfhdl->io_ops._sd_iwrite16; + + if (_sd_iwrite16) + ret = _sd_iwrite16(pintfhdl, addr, val); + else + DBG_871X_LEVEL(_drv_err_, FUNC_ADPT_FMT" _sd_iwrite16 callback is NULL\n", FUNC_ADPT_ARG(adapter)); + + return RTW_STATUS_CODE(ret); +} +int _rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val) +{ + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + int (*_sd_iwrite32)(struct intf_hdl *pintfhdl, u32 addr, u32 val); + int ret = -1; + + _sd_iwrite32 = pintfhdl->io_ops._sd_iwrite32; + + if (_sd_iwrite32) + ret = _sd_iwrite32(pintfhdl, addr, val); + else + DBG_871X_LEVEL(_drv_err_, FUNC_ADPT_FMT" _sd_iwrite32 callback is NULL\n", FUNC_ADPT_ARG(adapter)); + + return RTW_STATUS_CODE(ret); +} + +#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ + +#endif /* CONFIG_SDIO_HCI */ + +int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val) +{ + //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val); + int ret; + _func_enter_; + _write8_async = pintfhdl->io_ops._write8_async; + + ret = _write8_async(pintfhdl, addr, val); + _func_exit_; + + return RTW_STATUS_CODE(ret); +} +int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val) +{ + //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val); + int ret; + _func_enter_; + _write16_async = pintfhdl->io_ops._write16_async; + val = rtw_cpu_to_le16(val); + ret = _write16_async(pintfhdl, addr, val); + _func_exit_; + + return RTW_STATUS_CODE(ret); +} +int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val) +{ + //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val); + int ret; + _func_enter_; + _write32_async = pintfhdl->io_ops._write32_async; + val = rtw_cpu_to_le32(val); + ret = _write32_async(pintfhdl, addr, val); + _func_exit_; + + return RTW_STATUS_CODE(ret); +} + +void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem) +{ + void (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); + //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + + _func_enter_; + + if (RTW_CANNOT_RUN(adapter)) { + RT_TRACE(_module_rtl871x_io_c_, _drv_info_, ("rtw_read_mem:bDriverStopped(%s) OR bSurpriseRemoved(%s)" + , rtw_is_drv_stopped(adapter)?"True":"False" + , rtw_is_surprise_removed(adapter)?"True":"False")); + return; + } + + _read_mem = pintfhdl->io_ops._read_mem; + + _read_mem(pintfhdl, addr, cnt, pmem); + + _func_exit_; + +} + +void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem) +{ + void (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); + //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + + _func_enter_; + + _write_mem = pintfhdl->io_ops._write_mem; + + _write_mem(pintfhdl, addr, cnt, pmem); + + _func_exit_; + +} + +void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem) +{ + u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); + //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + + _func_enter_; + + if (RTW_CANNOT_RUN(adapter)) { + RT_TRACE(_module_rtl871x_io_c_, _drv_info_, ("rtw_read_port:bDriverStopped(%s) OR bSurpriseRemoved(%s)" + , rtw_is_drv_stopped(adapter)?"True":"False" + , rtw_is_surprise_removed(adapter)?"True":"False")); + return; + } + + _read_port = pintfhdl->io_ops._read_port; + + _read_port(pintfhdl, addr, cnt, pmem); + + _func_exit_; + +} + +void _rtw_read_port_cancel(_adapter *adapter) +{ + void (*_read_port_cancel)(struct intf_hdl *pintfhdl); + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + + _read_port_cancel = pintfhdl->io_ops._read_port_cancel; + + RTW_DISABLE_FUNC(adapter, DF_RX_BIT); + + if(_read_port_cancel) + _read_port_cancel(pintfhdl); +} + +u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem) +{ + u32 (*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); + //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + u32 ret = _SUCCESS; + + _func_enter_; + + _write_port = pintfhdl->io_ops._write_port; + + ret = _write_port(pintfhdl, addr, cnt, pmem); + + _func_exit_; + + return ret; +} + +u32 _rtw_write_port_and_wait(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int timeout_ms) +{ + int ret = _SUCCESS; + struct xmit_buf *pxmitbuf = (struct xmit_buf *)pmem; + struct submit_ctx sctx; + + rtw_sctx_init(&sctx, timeout_ms); + pxmitbuf->sctx = &sctx; + + ret = _rtw_write_port(adapter, addr, cnt, pmem); + + if (ret == _SUCCESS) + ret = rtw_sctx_wait(&sctx, __func__); + + return ret; +} + +void _rtw_write_port_cancel(_adapter *adapter) +{ + void (*_write_port_cancel)(struct intf_hdl *pintfhdl); + struct io_priv *pio_priv = &adapter->iopriv; + struct intf_hdl *pintfhdl = &(pio_priv->intf); + + _write_port_cancel = pintfhdl->io_ops._write_port_cancel; + + RTW_DISABLE_FUNC(adapter, DF_TX_BIT); + + if(_write_port_cancel) + _write_port_cancel(pintfhdl); +} +int rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(_adapter *padapter,struct _io_ops *pops)) +{ + struct io_priv *piopriv = &padapter->iopriv; + struct intf_hdl *pintf = &piopriv->intf; + + if (set_intf_ops == NULL) + return _FAIL; + + piopriv->padapter = padapter; + pintf->padapter = padapter; + pintf->pintf_dev = adapter_to_dvobj(padapter); + + set_intf_ops(padapter,&pintf->io_ops); + + return _SUCCESS; +} + +/* +* Increase and check if the continual_io_error of this @param dvobjprive is larger than MAX_CONTINUAL_IO_ERR +* @return _TRUE: +* @return _FALSE: +*/ +int rtw_inc_and_chk_continual_io_error(struct dvobj_priv *dvobj) +{ + int ret = _FALSE; + int value; + if( (value=ATOMIC_INC_RETURN(&dvobj->continual_io_error)) > MAX_CONTINUAL_IO_ERR) { + DBG_871X("[dvobj:%p][ERROR] continual_io_error:%d > %d\n", dvobj, value, MAX_CONTINUAL_IO_ERR); + ret = _TRUE; + } else { + //DBG_871X("[dvobj:%p] continual_io_error:%d\n", dvobj, value); + } + return ret; +} + +/* +* Set the continual_io_error of this @param dvobjprive to 0 +*/ +void rtw_reset_continual_io_error(struct dvobj_priv *dvobj) +{ + ATOMIC_SET(&dvobj->continual_io_error, 0); +} + +#ifdef DBG_IO + +u32 read_sniff_ranges[][2] = { + //{0x520, 0x523}, +}; + +u32 write_sniff_ranges[][2] = { + //{0x520, 0x523}, + //{0x4c, 0x4c}, +}; + +int read_sniff_num = sizeof(read_sniff_ranges)/sizeof(u32)/2; +int write_sniff_num = sizeof(write_sniff_ranges)/sizeof(u32)/2; + +bool match_read_sniff_ranges(u32 addr, u16 len) +{ + int i; + for (i = 0; i read_sniff_ranges[i][0] && addr <= read_sniff_ranges[i][1]) + return _TRUE; + } + + return _FALSE; +} + +bool match_write_sniff_ranges(u32 addr, u16 len) +{ + int i; + for (i = 0; i write_sniff_ranges[i][0] && addr <= write_sniff_ranges[i][1]) + return _TRUE; + } + + return _FALSE; +} + +struct rf_sniff_ent { + u8 path; + u16 reg; + u32 mask; +}; + +struct rf_sniff_ent rf_read_sniff_ranges[] = { + /* example for all path addr 0x55 with all RF Reg mask */ + /* {MAX_RF_PATH, 0x55, bRFRegOffsetMask}, */ +}; + +struct rf_sniff_ent rf_write_sniff_ranges[] = { + /* example for all path addr 0x55 with all RF Reg mask */ + /* {MAX_RF_PATH, 0x55, bRFRegOffsetMask}, */ +}; + +int rf_read_sniff_num = sizeof(rf_read_sniff_ranges)/sizeof(struct rf_sniff_ent); +int rf_write_sniff_num = sizeof(rf_write_sniff_ranges)/sizeof(struct rf_sniff_ent); + +bool match_rf_read_sniff_ranges(u8 path, u32 addr, u32 mask) +{ + int i; + + for (i = 0; i < rf_read_sniff_num; i++) { + if (rf_read_sniff_ranges[i].path == MAX_RF_PATH || rf_read_sniff_ranges[i].path == path) + if (addr == rf_read_sniff_ranges[i].reg && (mask & rf_read_sniff_ranges[i].mask)) + return _TRUE; + } + + return _FALSE; +} + +bool match_rf_write_sniff_ranges(u8 path, u32 addr, u32 mask) +{ + int i; + + for (i = 0; i < rf_write_sniff_num; i++) { + if (rf_write_sniff_ranges[i].path == MAX_RF_PATH || rf_write_sniff_ranges[i].path == path) + if (addr == rf_write_sniff_ranges[i].reg && (mask & rf_write_sniff_ranges[i].mask)) + return _TRUE; + } + + return _FALSE; +} + +u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line) +{ + u8 val = _rtw_read8(adapter, addr); + + if (match_read_sniff_ranges(addr, 1)) + DBG_871X("DBG_IO %s:%d rtw_read8(0x%04x) return 0x%02x\n", caller, line, addr, val); + + return val; +} + +u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line) +{ + u16 val = _rtw_read16(adapter, addr); + + if (match_read_sniff_ranges(addr, 2)) + DBG_871X("DBG_IO %s:%d rtw_read16(0x%04x) return 0x%04x\n", caller, line, addr, val); + + return val; +} + +u32 dbg_rtw_read32(_adapter *adapter, u32 addr, const char *caller, const int line) +{ + u32 val = _rtw_read32(adapter, addr); + + if (match_read_sniff_ranges(addr, 4)) + DBG_871X("DBG_IO %s:%d rtw_read32(0x%04x) return 0x%08x\n", caller, line, addr, val); + + return val; +} + +int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line) +{ + if (match_write_sniff_ranges(addr, 1)) + DBG_871X("DBG_IO %s:%d rtw_write8(0x%04x, 0x%02x)\n", caller, line, addr, val); + + return _rtw_write8(adapter, addr, val); +} +int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line) +{ + if (match_write_sniff_ranges(addr, 2)) + DBG_871X("DBG_IO %s:%d rtw_write16(0x%04x, 0x%04x)\n", caller, line, addr, val); + + return _rtw_write16(adapter, addr, val); +} +int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line) +{ + if (match_write_sniff_ranges(addr, 4)) + DBG_871X("DBG_IO %s:%d rtw_write32(0x%04x, 0x%08x)\n", caller, line, addr, val); + + return _rtw_write32(adapter, addr, val); +} +int dbg_rtw_writeN(_adapter *adapter, u32 addr ,u32 length , u8 *data, const char *caller, const int line) +{ + if (match_write_sniff_ranges(addr, length)) + DBG_871X("DBG_IO %s:%d rtw_writeN(0x%04x, %u)\n", caller, line, addr, length); + + return _rtw_writeN(adapter, addr, length, data); +} + +#ifdef CONFIG_SDIO_HCI +u8 dbg_rtw_sd_f0_read8(_adapter *adapter, u32 addr, const char *caller, const int line) +{ + u8 val = _rtw_sd_f0_read8(adapter, addr); + + #if 0 + if (match_read_sniff_ranges(addr, 1)) + DBG_871X("DBG_IO %s:%d rtw_sd_f0_read8(0x%04x) return 0x%02x\n", caller, line, addr, val); + #endif + + return val; +} + +#ifdef CONFIG_SDIO_INDIRECT_ACCESS +u8 dbg_rtw_sd_iread8(_adapter *adapter, u32 addr, const char *caller, const int line) +{ + u8 val = rtw_sd_iread8(adapter, addr); + + if (match_read_sniff_ranges(addr, 1)) + DBG_871X("DBG_IO %s:%d rtw_sd_iread8(0x%04x) return 0x%02x\n", caller, line, addr, val); + + return val; +} + +u16 dbg_rtw_sd_iread16(_adapter *adapter, u32 addr, const char *caller, const int line) +{ + u16 val = _rtw_sd_iread16(adapter, addr); + + if (match_read_sniff_ranges(addr, 2)) + DBG_871X("DBG_IO %s:%d rtw_sd_iread16(0x%04x) return 0x%04x\n", caller, line, addr, val); + + return val; +} + +u32 dbg_rtw_sd_iread32(_adapter *adapter, u32 addr, const char *caller, const int line) +{ + u32 val = _rtw_sd_iread32(adapter, addr); + + if (match_read_sniff_ranges(addr, 4)) + DBG_871X("DBG_IO %s:%d rtw_sd_iread32(0x%04x) return 0x%08x\n", caller, line, addr, val); + + return val; +} + +int dbg_rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line) +{ + if (match_write_sniff_ranges(addr, 1)) + DBG_871X("DBG_IO %s:%d rtw_sd_iwrite8(0x%04x, 0x%02x)\n", caller, line, addr, val); + + return _rtw_sd_iwrite8(adapter, addr, val); +} +int dbg_rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line) +{ + if (match_write_sniff_ranges(addr, 2)) + DBG_871X("DBG_IO %s:%d rtw_sd_iwrite16(0x%04x, 0x%04x)\n", caller, line, addr, val); + + return _rtw_sd_iwrite16(adapter, addr, val); +} +int dbg_rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line) +{ + if (match_write_sniff_ranges(addr, 4)) + DBG_871X("DBG_IO %s:%d rtw_sd_iwrite32(0x%04x, 0x%08x)\n", caller, line, addr, val); + + return _rtw_sd_iwrite32(adapter, addr, val); +} + +#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ + +#endif /* CONFIG_SDIO_HCI */ + +#endif + + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_ioctl_query.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_ioctl_query.c new file mode 100644 index 000000000..d7cd88590 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_ioctl_query.c @@ -0,0 +1,192 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_IOCTL_QUERY_C_ + +#include + + +#ifdef PLATFORM_WINDOWS +// +// Added for WPA2-PSK, by Annie, 2005-09-20. +// +u8 +query_802_11_capability( + _adapter* Adapter, + u8* pucBuf, + u32 * pulOutLen +) +{ + static NDIS_802_11_AUTHENTICATION_ENCRYPTION szAuthEnc[] = + { + {Ndis802_11AuthModeOpen, Ndis802_11EncryptionDisabled}, + {Ndis802_11AuthModeOpen, Ndis802_11Encryption1Enabled}, + {Ndis802_11AuthModeShared, Ndis802_11EncryptionDisabled}, + {Ndis802_11AuthModeShared, Ndis802_11Encryption1Enabled}, + {Ndis802_11AuthModeWPA, Ndis802_11Encryption2Enabled}, + {Ndis802_11AuthModeWPA, Ndis802_11Encryption3Enabled}, + {Ndis802_11AuthModeWPAPSK, Ndis802_11Encryption2Enabled}, + {Ndis802_11AuthModeWPAPSK, Ndis802_11Encryption3Enabled}, + {Ndis802_11AuthModeWPANone, Ndis802_11Encryption2Enabled}, + {Ndis802_11AuthModeWPANone, Ndis802_11Encryption3Enabled}, + {Ndis802_11AuthModeWPA2, Ndis802_11Encryption2Enabled}, + {Ndis802_11AuthModeWPA2, Ndis802_11Encryption3Enabled}, + {Ndis802_11AuthModeWPA2PSK, Ndis802_11Encryption2Enabled}, + {Ndis802_11AuthModeWPA2PSK, Ndis802_11Encryption3Enabled} + }; + static ULONG ulNumOfPairSupported = sizeof(szAuthEnc)/sizeof(NDIS_802_11_AUTHENTICATION_ENCRYPTION); + NDIS_802_11_CAPABILITY * pCap = (NDIS_802_11_CAPABILITY *)pucBuf; + u8* pucAuthEncryptionSupported = (u8*) pCap->AuthenticationEncryptionSupported; + + + pCap->Length = sizeof(NDIS_802_11_CAPABILITY); + if(ulNumOfPairSupported > 1 ) + pCap->Length += (ulNumOfPairSupported-1) * sizeof(NDIS_802_11_AUTHENTICATION_ENCRYPTION); + + pCap->Version = 2; + pCap->NoOfPMKIDs = NUM_PMKID_CACHE; + pCap->NoOfAuthEncryptPairsSupported = ulNumOfPairSupported; + + if( sizeof (szAuthEnc) <= 240 ) // 240 = 256 - 4*4 // SecurityInfo.szCapability: only 256 bytes in size. + { + _rtw_memcpy( pucAuthEncryptionSupported, (u8*)szAuthEnc, sizeof (szAuthEnc) ); + *pulOutLen = pCap->Length; + return _TRUE; + } + else + { + *pulOutLen = 0; + RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("_query_802_11_capability(): szAuthEnc size is too large.\n")); + return _FALSE; + } +} + +u8 query_802_11_association_information( _adapter *padapter,PNDIS_802_11_ASSOCIATION_INFORMATION pAssocInfo) +{ + struct wlan_network *tgt_network; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct security_priv *psecuritypriv=&(padapter->securitypriv); + WLAN_BSSID_EX *psecnetwork = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; + u8 * pDest = (u8 *)pAssocInfo + sizeof(NDIS_802_11_ASSOCIATION_INFORMATION); + unsigned char i,*auth_ie,*supp_ie; + + //NdisZeroMemory(pAssocInfo, sizeof(NDIS_802_11_ASSOCIATION_INFORMATION)); + _rtw_memset(pAssocInfo, 0, sizeof(NDIS_802_11_ASSOCIATION_INFORMATION)); + //pAssocInfo->Length = sizeof(NDIS_802_11_ASSOCIATION_INFORMATION); + + //------------------------------------------------------ + // Association Request related information + //------------------------------------------------------ + // Req_1. AvailableRequestFixedIEs + if(psecnetwork!=NULL){ + + pAssocInfo->AvailableRequestFixedIEs |= NDIS_802_11_AI_REQFI_CAPABILITIES|NDIS_802_11_AI_REQFI_CURRENTAPADDRESS; + pAssocInfo->RequestFixedIEs.Capabilities = (unsigned short)* & psecnetwork->IEs[10]; + _rtw_memcpy(pAssocInfo->RequestFixedIEs.CurrentAPAddress, + & psecnetwork->MacAddress, 6); + + pAssocInfo->OffsetRequestIEs = sizeof(NDIS_802_11_ASSOCIATION_INFORMATION); + + if(check_fwstate( pmlmepriv, _FW_UNDER_LINKING|_FW_LINKED)==_TRUE) + { + + if(psecuritypriv->ndisauthtype>=Ndis802_11AuthModeWPA2) + pDest[0] =48; //RSN Information Element + else + pDest[0] =221; //WPA(SSN) Information Element + + RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n Adapter->ndisauthtype==Ndis802_11AuthModeWPA)?0xdd:0x30 [%d]",pDest[0])); + supp_ie=&psecuritypriv->supplicant_ie[0]; + for(i=0;inetwork.IELength=%d\n\n", i,(int)psecnetwork->IELength)); + while((iRequestIELength += (2 + supp_ie[1+i]);// (2 + psecnetwork->IEs[1+i]+4); + + } + + + RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n psecnetwork != NULL,fwstate==_FW_UNDER_LINKING \n")); + + } + + + //------------------------------------------------------ + // Association Response related information + //------------------------------------------------------ + + if(check_fwstate( pmlmepriv, _FW_LINKED)==_TRUE) + { + tgt_network =&(pmlmepriv->cur_network); + if(tgt_network!=NULL){ + pAssocInfo->AvailableResponseFixedIEs = + NDIS_802_11_AI_RESFI_CAPABILITIES + |NDIS_802_11_AI_RESFI_ASSOCIATIONID + ; + + pAssocInfo->ResponseFixedIEs.Capabilities =(unsigned short)* & tgt_network->network.IEs[10]; + pAssocInfo->ResponseFixedIEs.StatusCode = 0; + pAssocInfo->ResponseFixedIEs.AssociationId =(unsigned short) tgt_network->aid; + + pDest = (u8 *)pAssocInfo + sizeof(NDIS_802_11_ASSOCIATION_INFORMATION)+pAssocInfo->RequestIELength; + auth_ie=&psecuritypriv->authenticator_ie[0]; + + for(i=0;i0){ + _rtw_memcpy((u8 *)&pDest[0],&auth_ie[1],i); + pAssocInfo->ResponseIELength =i; + } + + + pAssocInfo->OffsetResponseIEs = sizeof(NDIS_802_11_ASSOCIATION_INFORMATION) + pAssocInfo->RequestIELength; + + + RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n tgt_network != NULL,fwstate==_FW_LINKED \n")); + } + } + RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n exit query_802_11_association_information \n")); +_func_exit_; + + return _TRUE; +} +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_ioctl_rtl.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_ioctl_rtl.c new file mode 100644 index 000000000..998965975 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_ioctl_rtl.c @@ -0,0 +1,1021 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_IOCTL_RTL_C_ + +#include + +#ifdef CONFIG_MP_INCLUDED +#include +#endif + +struct oid_obj_priv oid_rtl_seg_01_01[] = +{ + {1, &oid_null_function}, //0x80 + {1, &oid_null_function}, //0x81 + {1, &oid_null_function}, //0x82 + {1, &oid_null_function}, //0x83//OID_RT_SET_SNIFFER_MODE + {1, &oid_rt_get_signal_quality_hdl}, //0x84 + {1, &oid_rt_get_small_packet_crc_hdl}, //0x85 + {1, &oid_rt_get_middle_packet_crc_hdl}, //0x86 + {1, &oid_rt_get_large_packet_crc_hdl}, //0x87 + {1, &oid_rt_get_tx_retry_hdl}, //0x88 + {1, &oid_rt_get_rx_retry_hdl}, //0x89 + {1, &oid_rt_pro_set_fw_dig_state_hdl}, //0x8A + {1, &oid_rt_pro_set_fw_ra_state_hdl} , //0x8B + {1, &oid_null_function}, //0x8C + {1, &oid_null_function}, //0x8D + {1, &oid_null_function}, //0x8E + {1, &oid_null_function}, //0x8F + {1, &oid_rt_get_rx_total_packet_hdl}, //0x90 + {1, &oid_rt_get_tx_beacon_ok_hdl}, //0x91 + {1, &oid_rt_get_tx_beacon_err_hdl}, //0x92 + {1, &oid_rt_get_rx_icv_err_hdl}, //0x93 + {1, &oid_rt_set_encryption_algorithm_hdl}, //0x94 + {1, &oid_null_function}, //0x95 + {1, &oid_rt_get_preamble_mode_hdl}, //0x96 + {1, &oid_null_function}, //0x97 + {1, &oid_rt_get_ap_ip_hdl}, //0x98 + {1, &oid_rt_get_channelplan_hdl}, //0x99 + {1, &oid_rt_set_preamble_mode_hdl}, //0x9A + {1, &oid_rt_set_bcn_intvl_hdl}, //0x9B + {1, &oid_null_function}, //0x9C + {1, &oid_rt_dedicate_probe_hdl}, //0x9D + {1, &oid_null_function}, //0x9E + {1, &oid_null_function}, //0x9F + {1, &oid_null_function}, //0xA0 + {1, &oid_null_function}, //0xA1 + {1, &oid_null_function}, //0xA2 + {1, &oid_null_function}, //0xA3 + {1, &oid_null_function}, //0xA4 + {1, &oid_null_function}, //0xA5 + {1, &oid_null_function}, //0xA6 + {1, &oid_rt_get_total_tx_bytes_hdl}, //0xA7 + {1, &oid_rt_get_total_rx_bytes_hdl}, //0xA8 + {1, &oid_rt_current_tx_power_level_hdl}, //0xA9 + {1, &oid_rt_get_enc_key_mismatch_count_hdl}, //0xAA + {1, &oid_rt_get_enc_key_match_count_hdl}, //0xAB + {1, &oid_rt_get_channel_hdl}, //0xAC + {1, &oid_rt_set_channelplan_hdl}, //0xAD + {1, &oid_rt_get_hardware_radio_off_hdl}, //0xAE + {1, &oid_null_function}, //0xAF + {1, &oid_null_function}, //0xB0 + {1, &oid_null_function}, //0xB1 + {1, &oid_null_function}, //0xB2 + {1, &oid_null_function}, //0xB3 + {1, &oid_rt_get_key_mismatch_hdl}, //0xB4 + {1, &oid_null_function}, //0xB5 + {1, &oid_null_function}, //0xB6 + {1, &oid_null_function}, //0xB7 + {1, &oid_null_function}, //0xB8 + {1, &oid_null_function}, //0xB9 + {1, &oid_null_function}, //0xBA + {1, &oid_rt_supported_wireless_mode_hdl}, //0xBB + {1, &oid_rt_get_channel_list_hdl}, //0xBC + {1, &oid_rt_get_scan_in_progress_hdl}, //0xBD + {1, &oid_null_function}, //0xBE + {1, &oid_null_function}, //0xBF + {1, &oid_null_function}, //0xC0 + {1, &oid_rt_forced_data_rate_hdl}, //0xC1 + {1, &oid_rt_wireless_mode_for_scan_list_hdl}, //0xC2 + {1, &oid_rt_get_bss_wireless_mode_hdl}, //0xC3 + {1, &oid_rt_scan_with_magic_packet_hdl}, //0xC4 + {1, &oid_null_function}, //0xC5 + {1, &oid_null_function}, //0xC6 + {1, &oid_null_function}, //0xC7 + {1, &oid_null_function}, //0xC8 + {1, &oid_null_function}, //0xC9 + {1, &oid_null_function}, //0xCA + {1, &oid_null_function}, //0xCB + {1, &oid_null_function}, //0xCC + {1, &oid_null_function}, //0xCD + {1, &oid_null_function}, //0xCE + {1, &oid_null_function}, //0xCF + +}; + +struct oid_obj_priv oid_rtl_seg_01_03[] = +{ + {1, &oid_rt_ap_get_associated_station_list_hdl}, //0x00 + {1, &oid_null_function}, //0x01 + {1, &oid_rt_ap_switch_into_ap_mode_hdl}, //0x02 + {1, &oid_null_function}, //0x03 + {1, &oid_rt_ap_supported_hdl}, //0x04 + {1, &oid_rt_ap_set_passphrase_hdl}, //0x05 + +}; + +struct oid_obj_priv oid_rtl_seg_01_11[] = +{ + {1, &oid_null_function}, //0xC0 OID_RT_PRO_RX_FILTER + {1, &oid_null_function}, //0xC1 OID_CE_USB_WRITE_REGISTRY + {1, &oid_null_function}, //0xC2 OID_CE_USB_READ_REGISTRY + {1, &oid_null_function}, //0xC3 OID_RT_PRO_SET_INITIAL_GAIN + {1, &oid_null_function}, //0xC4 OID_RT_PRO_SET_BB_RF_STANDBY_MODE + {1, &oid_null_function}, //0xC5 OID_RT_PRO_SET_BB_RF_SHUTDOWN_MODE + {1, &oid_null_function}, //0xC6 OID_RT_PRO_SET_TX_CHARGE_PUMP + {1, &oid_null_function}, //0xC7 OID_RT_PRO_SET_RX_CHARGE_PUMP + {1, &oid_rt_pro_rf_write_registry_hdl}, //0xC8 + {1, &oid_rt_pro_rf_read_registry_hdl}, //0xC9 + {1, &oid_null_function} //0xCA OID_RT_PRO_QUERY_RF_TYPE + +}; + +struct oid_obj_priv oid_rtl_seg_03_00[] = +{ + {1, &oid_null_function}, //0x00 + {1, &oid_rt_get_connect_state_hdl}, //0x01 + {1, &oid_null_function}, //0x02 + {1, &oid_null_function}, //0x03 + {1, &oid_rt_set_default_key_id_hdl}, //0x04 + + +}; + + +//************** oid_rtl_seg_01_01 section start ************** + +NDIS_STATUS oid_rt_pro_set_fw_dig_state_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; +#if 0 + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + _irqL oldirql; + + _func_enter_; + + if(poid_par_priv->type_of_oid != SET_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + _irqlevel_changed_(&oldirql,LOWER); + if(poid_par_priv->information_buf_len >= sizeof(struct setdig_parm)) + { + //DEBUG_ERR(("===> oid_rt_pro_set_fw_dig_state_hdl. type:0x%02x.\n",*((unsigned char*)poid_par_priv->information_buf ))); + if(!rtw_setfwdig_cmd(Adapter,*((unsigned char*)poid_par_priv->information_buf ))) + { + status = NDIS_STATUS_NOT_ACCEPTED; + } + + } + else{ + status = NDIS_STATUS_NOT_ACCEPTED; + } + _irqlevel_changed_(&oldirql,RAISE); + _func_exit_; +#endif + return status; +} +//----------------------------------------------------------------------------- +NDIS_STATUS oid_rt_pro_set_fw_ra_state_hdl(struct oid_par_priv* poid_par_priv) +{ + + NDIS_STATUS status = NDIS_STATUS_SUCCESS; +#if 0 + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + _irqL oldirql; + + _func_enter_; + if(poid_par_priv->type_of_oid != SET_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + + _irqlevel_changed_(&oldirql,LOWER); + + if(poid_par_priv->information_buf_len >= sizeof(struct setra_parm)) + { + //DEBUG_ERR(("===> oid_rt_pro_set_fw_ra_state_hdl. type:0x%02x.\n",*((unsigned char*)poid_par_priv->information_buf ))); + if(!rtw_setfwra_cmd(Adapter,*((unsigned char*)poid_par_priv->information_buf ))) + { + status = NDIS_STATUS_NOT_ACCEPTED; + } + + } + else{ + status = NDIS_STATUS_NOT_ACCEPTED; + } + _irqlevel_changed_(&oldirql,RAISE); + _func_exit_; +#endif + return status; +} +//----------------------------------------------------------------------------- +NDIS_STATUS oid_rt_get_signal_quality_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + //DEBUG_ERR(("<**********************oid_rt_get_signal_quality_hdl \n")); + if(poid_par_priv->type_of_oid != QUERY_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + +#if 0 + if(pMgntInfo->mAssoc || pMgntInfo->mIbss) + { + ulInfo = pAdapter->RxStats.SignalQuality; + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + } + else + { + ulInfo = 0xffffffff; // It stands for -1 in 4-byte integer. + } + break; +#endif + + return status; +} + +//------------------------------------------------------------------------------ + +NDIS_STATUS oid_rt_get_small_packet_crc_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + if(poid_par_priv->type_of_oid != QUERY_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + if(poid_par_priv->information_buf_len >= sizeof(ULONG) ) + { + *(ULONG *)poid_par_priv->information_buf = padapter->recvpriv.rx_smallpacket_crcerr; + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + } + else + { + status = NDIS_STATUS_INVALID_LENGTH; + } + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_get_middle_packet_crc_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + if(poid_par_priv->type_of_oid != QUERY_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + if(poid_par_priv->information_buf_len >= sizeof(ULONG) ) + { + *(ULONG *)poid_par_priv->information_buf = padapter->recvpriv.rx_middlepacket_crcerr; + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + } + else + { + status = NDIS_STATUS_INVALID_LENGTH; + } + + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_get_large_packet_crc_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + if(poid_par_priv->type_of_oid != QUERY_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + if(poid_par_priv->information_buf_len >= sizeof(ULONG) ) + { + *(ULONG *)poid_par_priv->information_buf = padapter->recvpriv.rx_largepacket_crcerr; + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + } + else + { + status = NDIS_STATUS_INVALID_LENGTH; + } + + + return status; +} + +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_get_tx_retry_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + if(poid_par_priv->type_of_oid != QUERY_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + return status; +} +NDIS_STATUS oid_rt_get_rx_retry_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + if(poid_par_priv->type_of_oid != QUERY_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_get_rx_total_packet_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + if(poid_par_priv->type_of_oid != QUERY_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + if(poid_par_priv->information_buf_len >= sizeof(ULONG) ) + { + *(u64 *)poid_par_priv->information_buf = padapter->recvpriv.rx_pkts + padapter->recvpriv.rx_drop; + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + } + else + { + status = NDIS_STATUS_INVALID_LENGTH; + } + + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_get_tx_beacon_ok_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + if(poid_par_priv->type_of_oid != QUERY_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + return status; +} +NDIS_STATUS oid_rt_get_tx_beacon_err_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + if(poid_par_priv->type_of_oid != QUERY_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_get_rx_icv_err_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + if(poid_par_priv->type_of_oid != QUERY_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + if(poid_par_priv->information_buf_len>= sizeof(u32)) + { + //_rtw_memcpy(*(uint *)poid_par_priv->information_buf,padapter->recvpriv.rx_icv_err,sizeof(u32)); + *(uint *)poid_par_priv->information_buf = padapter->recvpriv.rx_icv_err; + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + } + else + { + status = NDIS_STATUS_INVALID_LENGTH ; + } + + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_set_encryption_algorithm_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + if(poid_par_priv->type_of_oid != SET_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_get_preamble_mode_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + ULONG preamblemode = 0 ; + + if(poid_par_priv->type_of_oid != QUERY_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + if(poid_par_priv->information_buf_len>= sizeof(ULONG)) + { + if(padapter->registrypriv.preamble == PREAMBLE_LONG) + preamblemode = 0; + else if (padapter->registrypriv.preamble == PREAMBLE_AUTO) + preamblemode = 1; + else if (padapter->registrypriv.preamble == PREAMBLE_SHORT) + preamblemode = 2; + + + *(ULONG *)poid_par_priv->information_buf = preamblemode ; + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + } + else + { + status = NDIS_STATUS_INVALID_LENGTH ; + } + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_get_ap_ip_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + if(poid_par_priv->type_of_oid != QUERY_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + return status; +} + +NDIS_STATUS oid_rt_get_channelplan_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + if(poid_par_priv->type_of_oid != QUERY_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + *(u16 *)poid_par_priv->information_buf = padapter->mlmepriv.ChannelPlan ; + + return status; +} +NDIS_STATUS oid_rt_set_channelplan_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + if(poid_par_priv->type_of_oid != SET_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + padapter->mlmepriv.ChannelPlan = *(u16 *)poid_par_priv->information_buf ; + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_set_preamble_mode_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + ULONG preamblemode = 0; + if(poid_par_priv->type_of_oid != SET_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + if(poid_par_priv->information_buf_len>= sizeof(ULONG)) + { + preamblemode = *(ULONG *)poid_par_priv->information_buf ; + if( preamblemode == 0) + padapter->registrypriv.preamble = PREAMBLE_LONG; + else if (preamblemode==1 ) + padapter->registrypriv.preamble = PREAMBLE_AUTO; + else if ( preamblemode==2 ) + padapter->registrypriv.preamble = PREAMBLE_SHORT; + + *(ULONG *)poid_par_priv->information_buf = preamblemode ; + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + } + else + { + status = NDIS_STATUS_INVALID_LENGTH ; + } + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_set_bcn_intvl_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + if(poid_par_priv->type_of_oid != SET_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + return status; +} +NDIS_STATUS oid_rt_dedicate_probe_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_get_total_tx_bytes_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + if(poid_par_priv->type_of_oid != QUERY_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + if(poid_par_priv->information_buf_len>= sizeof(ULONG)) + { + *(u64 *)poid_par_priv->information_buf = padapter->xmitpriv.tx_bytes; + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + } + else + { + status = NDIS_STATUS_INVALID_LENGTH ; + } + + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_get_total_rx_bytes_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + if(poid_par_priv->type_of_oid != QUERY_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + if(poid_par_priv->information_buf_len>= sizeof(ULONG)) + { + //_rtw_memcpy(*(uint *)poid_par_priv->information_buf,padapter->recvpriv.rx_icv_err,sizeof(u32)); + *(u64 *)poid_par_priv->information_buf = padapter->recvpriv.rx_bytes; + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + } + else + { + status = NDIS_STATUS_INVALID_LENGTH ; + } + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_current_tx_power_level_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + return status; +} +NDIS_STATUS oid_rt_get_enc_key_mismatch_count_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + if(poid_par_priv->type_of_oid != QUERY_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + return status; +} +NDIS_STATUS oid_rt_get_enc_key_match_count_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + if(poid_par_priv->type_of_oid != QUERY_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + return status; +} +NDIS_STATUS oid_rt_get_channel_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + NDIS_802_11_CONFIGURATION *pnic_Config; + + ULONG channelnum; + + _func_enter_; + if(poid_par_priv->type_of_oid != QUERY_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + if ( (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) + pnic_Config = &pmlmepriv->cur_network.network.Configuration; + else + pnic_Config = &padapter->registrypriv.dev_network.Configuration; + + channelnum = pnic_Config->DSConfig; + *(ULONG *)poid_par_priv->information_buf = channelnum; + + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + + _func_exit_; + + + + return status; +} +NDIS_STATUS oid_rt_get_hardware_radio_off_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + if(poid_par_priv->type_of_oid != QUERY_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + return status; +} +NDIS_STATUS oid_rt_get_key_mismatch_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + if(poid_par_priv->type_of_oid != QUERY_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + return status; +} +NDIS_STATUS oid_rt_supported_wireless_mode_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + ULONG ulInfo = 0 ; + //DEBUG_ERR(("<**********************oid_rt_supported_wireless_mode_hdl \n")); + if(poid_par_priv->type_of_oid != QUERY_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + if(poid_par_priv->information_buf_len >= sizeof(ULONG)){ + ulInfo |= 0x0100; //WIRELESS_MODE_B + ulInfo |= 0x0200; //WIRELESS_MODE_G + ulInfo |= 0x0400; //WIRELESS_MODE_A + + *(ULONG *) poid_par_priv->information_buf = ulInfo; + //DEBUG_ERR(("<===oid_rt_supported_wireless_mode %x\n",ulInfo)); + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + } + else{ + status = NDIS_STATUS_INVALID_LENGTH; + } + + return status; +} +NDIS_STATUS oid_rt_get_channel_list_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + if(poid_par_priv->type_of_oid != QUERY_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + return status; +} +NDIS_STATUS oid_rt_get_scan_in_progress_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + if(poid_par_priv->type_of_oid != QUERY_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + return status; +} + + +NDIS_STATUS oid_rt_forced_data_rate_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + return status; +} +NDIS_STATUS oid_rt_wireless_mode_for_scan_list_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + return status; +} +NDIS_STATUS oid_rt_get_bss_wireless_mode_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + if(poid_par_priv->type_of_oid != QUERY_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + return status; +} + +NDIS_STATUS oid_rt_scan_with_magic_packet_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + return status; +} +//************** oid_rtl_seg_01_01 section end ************** + +//************** oid_rtl_seg_01_03 section start ************** +NDIS_STATUS oid_rt_ap_get_associated_station_list_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + if(poid_par_priv->type_of_oid != QUERY_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + return status; +} +NDIS_STATUS oid_rt_ap_switch_into_ap_mode_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + return status; +} +NDIS_STATUS oid_rt_ap_supported_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + return status; +} +NDIS_STATUS oid_rt_ap_set_passphrase_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + if(poid_par_priv->type_of_oid != SET_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + return status; +} + +//************** oid_rtl_seg_01_03 section end ************** + +//**************** oid_rtl_seg_01_11 section start **************** +NDIS_STATUS oid_rt_pro_rf_write_registry_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + _irqL oldirql; + _func_enter_; + //DEBUG_ERR(("<**********************oid_rt_pro_rf_write_registry_hdl \n")); + if(poid_par_priv->type_of_oid != SET_OID) //QUERY_OID + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + _irqlevel_changed_(&oldirql,LOWER); + if(poid_par_priv->information_buf_len== (sizeof(unsigned long)*3)) + { + //RegOffsetValue - The offset of RF register to write. + //RegDataWidth - The data width of RF register to write. + //RegDataValue - The value to write. + //RegOffsetValue = *((unsigned long*)InformationBuffer); + //RegDataWidth = *((unsigned long*)InformationBuffer+1); + //RegDataValue = *((unsigned long*)InformationBuffer+2); + if(!rtw_setrfreg_cmd(Adapter, + *(unsigned char*)poid_par_priv->information_buf, + (unsigned long)(*((unsigned long*)poid_par_priv->information_buf+2)))) + { + status = NDIS_STATUS_NOT_ACCEPTED; + } + + } + else{ + status = NDIS_STATUS_INVALID_LENGTH; + } + _irqlevel_changed_(&oldirql,RAISE); + _func_exit_; + + return status; +} + +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_rf_read_registry_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; +#if 0 + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + _irqL oldirql; + _func_enter_; + + //DEBUG_ERR(("<**********************oid_rt_pro_rf_read_registry_hdl \n")); + if(poid_par_priv->type_of_oid != SET_OID) //QUERY_OID + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + _irqlevel_changed_(&oldirql,LOWER); + if(poid_par_priv->information_buf_len== (sizeof(unsigned long)*3)) + { + if(Adapter->mppriv.act_in_progress == _TRUE) + { + status = NDIS_STATUS_NOT_ACCEPTED; + } + else + { + //init workparam + Adapter->mppriv.act_in_progress = _TRUE; + Adapter->mppriv.workparam.bcompleted= _FALSE; + Adapter->mppriv.workparam.act_type = MPT_READ_RF; + Adapter->mppriv.workparam.io_offset = *(unsigned long*)poid_par_priv->information_buf; + Adapter->mppriv.workparam.io_value = 0xcccccccc; + + //RegOffsetValue - The offset of RF register to read. + //RegDataWidth - The data width of RF register to read. + //RegDataValue - The value to read. + //RegOffsetValue = *((unsigned long*)InformationBuffer); + //RegDataWidth = *((unsigned long*)InformationBuffer+1); + //RegDataValue = *((unsigned long*)InformationBuffer+2); + if(!rtw_getrfreg_cmd(Adapter, + *(unsigned char*)poid_par_priv->information_buf, + (unsigned char*)&Adapter->mppriv.workparam.io_value)) + { + status = NDIS_STATUS_NOT_ACCEPTED; + } + } + + + } + else { + status = NDIS_STATUS_INVALID_LENGTH; + } + _irqlevel_changed_(&oldirql,RAISE); + _func_exit_; +#endif + return status; +} + +//**************** oid_rtl_seg_01_11 section end**************** + + +//************** oid_rtl_seg_03_00 section start ************** +enum _CONNECT_STATE_{ + CHECKINGSTATUS, + ASSOCIATED, + ADHOCMODE, + NOTASSOCIATED +}; + +NDIS_STATUS oid_rt_get_connect_state_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + ULONG ulInfo; + + if(poid_par_priv->type_of_oid != QUERY_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + // nStatus==0 CheckingStatus + // nStatus==1 Associated + // nStatus==2 AdHocMode + // nStatus==3 NotAssociated + + if(check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) + ulInfo = CHECKINGSTATUS; + else if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + ulInfo = ASSOCIATED; + else if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)== _TRUE) + ulInfo = ADHOCMODE; + else + ulInfo = NOTASSOCIATED ; + + *(ULONG *)poid_par_priv->information_buf = ulInfo; + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + +#if 0 + // Rearrange the order to let the UI still shows connection when scan is in progress + RT_TRACE(COMP_OID_QUERY, DBG_LOUD, ("===> Query OID_RT_GET_CONNECT_STATE.\n")); + if(pMgntInfo->mAssoc) + ulInfo = 1; + else if(pMgntInfo->mIbss) + ulInfo = 2; + else if(pMgntInfo->bScanInProgress) + ulInfo = 0; + else + ulInfo = 3; + ulInfoLen = sizeof(ULONG); + RT_TRACE(COMP_OID_QUERY, DBG_LOUD, ("<=== Query OID_RT_GET_CONNECT_STATE: %d\n", ulInfo)); +#endif + + return status; +} + +NDIS_STATUS oid_rt_set_default_key_id_hdl(struct oid_par_priv* poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + + if(poid_par_priv->type_of_oid != SET_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + return status; +} +//************** oid_rtl_seg_03_00 section end ************** + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_ioctl_set.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_ioctl_set.c new file mode 100644 index 000000000..25b168762 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_ioctl_set.c @@ -0,0 +1,1477 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_IOCTL_SET_C_ + +#include +#include + + +extern void indicate_wx_scan_complete_event(_adapter *padapter); + +#define IS_MAC_ADDRESS_BROADCAST(addr) \ +( \ + ( (addr[0] == 0xff) && (addr[1] == 0xff) && \ + (addr[2] == 0xff) && (addr[3] == 0xff) && \ + (addr[4] == 0xff) && (addr[5] == 0xff) ) ? _TRUE : _FALSE \ +) + +u8 rtw_validate_bssid(u8 *bssid) +{ + u8 ret = _TRUE; + + if (is_zero_mac_addr(bssid) + || is_broadcast_mac_addr(bssid) + || is_multicast_mac_addr(bssid) + ) { + ret = _FALSE; + } + + return ret; +} + +u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid) +{ + u8 i; + u8 ret=_TRUE; + +_func_enter_; + + if (ssid->SsidLength > 32) { + RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("ssid length >32\n")); + ret= _FALSE; + goto exit; + } + +#ifdef CONFIG_VALIDATE_SSID + for(i = 0; i < ssid->SsidLength; i++) + { + //wifi, printable ascii code must be supported + if(!( (ssid->Ssid[i] >= 0x20) && (ssid->Ssid[i] <= 0x7e) )){ + RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("ssid has nonprintabl ascii\n")); + ret= _FALSE; + break; + } + } +#endif /* CONFIG_VALIDATE_SSID */ + +exit: + +_func_exit_; + + return ret; +} + +u8 rtw_do_join(_adapter * padapter); +u8 rtw_do_join(_adapter * padapter) +{ + _irqL irqL; + _list *plist, *phead; + u8* pibss = NULL; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + _queue *queue = &(pmlmepriv->scanned_queue); + u8 ret=_SUCCESS; + +_func_enter_; + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + phead = get_list_head(queue); + plist = get_next(phead); + + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("\n rtw_do_join: phead = %p; plist = %p \n\n\n", phead, plist)); + + pmlmepriv->cur_network.join_res = -2; + + set_fwstate(pmlmepriv, _FW_UNDER_LINKING); + + pmlmepriv->pscanned = plist; + + pmlmepriv->to_join = _TRUE; + + if(_rtw_queue_empty(queue)== _TRUE) + { + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); + + //when set_ssid/set_bssid for rtw_do_join(), but scanning queue is empty + //we try to issue sitesurvey firstly + + if (pmlmepriv->LinkDetectInfo.bBusyTraffic ==_FALSE + || rtw_to_roam(padapter) > 0 + ) + { + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_do_join(): site survey if scanned_queue is empty\n.")); + // submit site_survey_cmd + if(_SUCCESS!=(ret=rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0)) ) { + pmlmepriv->to_join = _FALSE; + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("rtw_do_join(): site survey return error\n.")); + } + } + else + { + pmlmepriv->to_join = _FALSE; + ret = _FAIL; + } + + goto exit; + } + else + { + int select_ret; + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + if((select_ret=rtw_select_and_join_from_scanned_queue(pmlmepriv))==_SUCCESS) + { + pmlmepriv->to_join = _FALSE; + _set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT); + } + else + { + if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)==_TRUE) + { + // submit createbss_cmd to change to a ADHOC_MASTER + + //pmlmepriv->lock has been acquired by caller... + WLAN_BSSID_EX *pdev_network = &(padapter->registrypriv.dev_network); + + pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE; + + pibss = padapter->registrypriv.dev_network.MacAddress; + + _rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID)); + _rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID)); + + rtw_update_registrypriv_dev_network(padapter); + + rtw_generate_random_ibss(pibss); + + if (rtw_create_ibss_cmd(padapter, 0) != _SUCCESS) { + RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("***Error=>do_goin: rtw_create_ibss_cmd status FAIL***\n")); + ret = _FALSE; + goto exit; + } + + pmlmepriv->to_join = _FALSE; + + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("***Error=> rtw_select_and_join_from_scanned_queue FAIL under STA_Mode*** \n ")); + + } + else + { + // can't associate ; reset under-linking + _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); + +#if 0 + if((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)) + { + if(_rtw_memcmp(pmlmepriv->cur_network.network.Ssid.Ssid, pmlmepriv->assoc_ssid.Ssid, pmlmepriv->assoc_ssid.SsidLength)) + { + // for funk to do roaming + // funk will reconnect, but funk will not sitesurvey before reconnect + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("for funk to do roaming")); + if(pmlmepriv->sitesurveyctrl.traffic_busy==_FALSE) + rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0); + } + + } +#endif + + //when set_ssid/set_bssid for rtw_do_join(), but there are no desired bss in scanning queue + //we try to issue sitesurvey firstly + if(pmlmepriv->LinkDetectInfo.bBusyTraffic==_FALSE + || rtw_to_roam(padapter) > 0 + ) + { + //DBG_871X("rtw_do_join() when no desired bss in scanning queue \n"); + if( _SUCCESS!=(ret=rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1, NULL, 0)) ){ + pmlmepriv->to_join = _FALSE; + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("do_join(): site survey return error\n.")); + } + } + else + { + ret = _FAIL; + pmlmepriv->to_join = _FALSE; + } + } + + } + + } + +exit: + +_func_exit_; + + return ret; +} + +#ifdef PLATFORM_WINDOWS +u8 rtw_pnp_set_power_wakeup(_adapter* padapter) +{ + u8 res=_SUCCESS; + +_func_enter_; + + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("==>rtw_pnp_set_power_wakeup!!!\n")); + + res = rtw_setstandby_cmd(padapter, 0); + + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("<==rtw_pnp_set_power_wakeup!!!\n")); + +_func_exit_; + + return res; +} + +u8 rtw_pnp_set_power_sleep(_adapter* padapter) +{ + u8 res=_SUCCESS; + +_func_enter_; + + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("==>rtw_pnp_set_power_sleep!!!\n")); + //DbgPrint("+rtw_pnp_set_power_sleep\n"); + + res = rtw_setstandby_cmd(padapter, 1); + + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("<==rtw_pnp_set_power_sleep!!!\n")); + +_func_exit_; + + return res; +} + +u8 rtw_set_802_11_reload_defaults(_adapter * padapter, NDIS_802_11_RELOAD_DEFAULTS reloadDefaults) +{ +_func_enter_; + + switch( reloadDefaults) + { + case Ndis802_11ReloadWEPKeys: + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("SetInfo OID_802_11_RELOAD_DEFAULTS : Ndis802_11ReloadWEPKeys\n")); + break; + } + + // SecClearAllKeys(Adapter); + // 8711 CAM was not for En/Decrypt only + // so, we can't clear all keys. + // should we disable WPAcfg (ox0088) bit 1-2, instead of clear all CAM + + //TO DO... + +_func_exit_; + + return _TRUE; +} + +u8 set_802_11_test(_adapter* padapter, NDIS_802_11_TEST *test) +{ + u8 ret=_TRUE; + +_func_enter_; + + switch(test->Type) + { + case 1: + NdisMIndicateStatus(padapter->hndis_adapter, NDIS_STATUS_MEDIA_SPECIFIC_INDICATION, (PVOID)&test->AuthenticationEvent, test->Length - 8); + NdisMIndicateStatusComplete(padapter->hndis_adapter); + break; + + case 2: + NdisMIndicateStatus(padapter->hndis_adapter, NDIS_STATUS_MEDIA_SPECIFIC_INDICATION, (PVOID)&test->RssiTrigger, sizeof(NDIS_802_11_RSSI)); + NdisMIndicateStatusComplete(padapter->hndis_adapter); + break; + + default: + ret=_FALSE; + break; + } + +_func_exit_; + + return ret; +} + +u8 rtw_set_802_11_pmkid(_adapter* padapter, NDIS_802_11_PMKID *pmkid) +{ + u8 ret=_SUCCESS; + + return ret; +} + +#endif + +u8 rtw_set_802_11_bssid(_adapter* padapter, u8 *bssid) +{ + _irqL irqL; + u8 status=_SUCCESS; + + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + +_func_enter_; + + DBG_871X_LEVEL(_drv_always_, "set bssid:%pM\n", bssid); + + if ((bssid[0]==0x00 && bssid[1]==0x00 && bssid[2]==0x00 && bssid[3]==0x00 && bssid[4]==0x00 &&bssid[5]==0x00) || + (bssid[0]==0xFF && bssid[1]==0xFF && bssid[2]==0xFF && bssid[3]==0xFF && bssid[4]==0xFF &&bssid[5]==0xFF)) + { + status = _FAIL; + goto exit; + } + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + + DBG_871X("Set BSSID under fw_state=0x%08x\n", get_fwstate(pmlmepriv)); + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) { + goto handle_tkip_countermeasure; + } else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) { + goto release_mlme_lock; + } + + if (check_fwstate(pmlmepriv, _FW_LINKED|WIFI_ADHOC_MASTER_STATE) == _TRUE) + { + RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("set_bssid: _FW_LINKED||WIFI_ADHOC_MASTER_STATE\n")); + + if (_rtw_memcmp(&pmlmepriv->cur_network.network.MacAddress, bssid, ETH_ALEN) == _TRUE) + { + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE) + goto release_mlme_lock;//it means driver is in WIFI_ADHOC_MASTER_STATE, we needn't create bss again. + } else { + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("Set BSSID not the same bssid\n")); + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("set_bssid="MAC_FMT"\n", MAC_ARG(bssid) )); + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("cur_bssid="MAC_FMT"\n", MAC_ARG(pmlmepriv->cur_network.network.MacAddress) )); + + rtw_disassoc_cmd(padapter, 0, _TRUE); + + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + rtw_indicate_disconnect(padapter, 0, _FALSE); + + rtw_free_assoc_resources(padapter, 1); + + if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { + _clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE); + set_fwstate(pmlmepriv, WIFI_ADHOC_STATE); + } + } + } + +handle_tkip_countermeasure: + if (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) { + status = _FAIL; + goto release_mlme_lock; + } + + _rtw_memset(&pmlmepriv->assoc_ssid, 0, sizeof(NDIS_802_11_SSID)); + _rtw_memcpy(&pmlmepriv->assoc_bssid, bssid, ETH_ALEN); + pmlmepriv->assoc_by_bssid=_TRUE; + + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) { + pmlmepriv->to_join = _TRUE; + } + else { + status = rtw_do_join(padapter); + } + +release_mlme_lock: + _exit_critical_bh(&pmlmepriv->lock, &irqL); + +exit: + RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, + ("rtw_set_802_11_bssid: status=%d\n", status)); + +_func_exit_; + + return status; +} + +u8 rtw_set_802_11_ssid(_adapter* padapter, NDIS_802_11_SSID *ssid) +{ + _irqL irqL; + u8 status = _SUCCESS; + u32 cur_time = 0; + + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wlan_network *pnetwork = &pmlmepriv->cur_network; + +_func_enter_; + + DBG_871X_LEVEL(_drv_always_, "set ssid [%s] fw_state=0x%08x\n", + ssid->Ssid, get_fwstate(pmlmepriv)); + + if (!rtw_is_hw_init_completed(padapter)) { + RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, + ("set_ssid: hw_init_completed==_FALSE=>exit!!!\n")); + status = _FAIL; + goto exit; + } + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + DBG_871X("Set SSID under fw_state=0x%08x\n", get_fwstate(pmlmepriv)); + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) { + goto handle_tkip_countermeasure; + } else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) { + goto release_mlme_lock; + } + + if (check_fwstate(pmlmepriv, _FW_LINKED|WIFI_ADHOC_MASTER_STATE) == _TRUE) + { + RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, + ("set_ssid: _FW_LINKED||WIFI_ADHOC_MASTER_STATE\n")); + + if ((pmlmepriv->assoc_ssid.SsidLength == ssid->SsidLength) && + (_rtw_memcmp(&pmlmepriv->assoc_ssid.Ssid, ssid->Ssid, ssid->SsidLength) == _TRUE)) + { + if((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE)) + { + RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, + ("Set SSID is the same ssid, fw_state=0x%08x\n", + get_fwstate(pmlmepriv))); + + if(rtw_is_same_ibss(padapter, pnetwork) == _FALSE) + { + //if in WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE, create bss or rejoin again + rtw_disassoc_cmd(padapter, 0, _TRUE); + + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + rtw_indicate_disconnect(padapter, 0, _FALSE); + + rtw_free_assoc_resources(padapter, 1); + + if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) { + _clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE); + set_fwstate(pmlmepriv, WIFI_ADHOC_STATE); + } + } + else + { + goto release_mlme_lock;//it means driver is in WIFI_ADHOC_MASTER_STATE, we needn't create bss again. + } + } +#ifdef CONFIG_LPS + else { + rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_JOINBSS, 1); + } +#endif + } + else + { + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("Set SSID not the same ssid\n")); + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("set_ssid=[%s] len=0x%x\n", ssid->Ssid, (unsigned int)ssid->SsidLength)); + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("assoc_ssid=[%s] len=0x%x\n", pmlmepriv->assoc_ssid.Ssid, (unsigned int)pmlmepriv->assoc_ssid.SsidLength)); + + rtw_disassoc_cmd(padapter, 0, _TRUE); + + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + rtw_indicate_disconnect(padapter, 0, _FALSE); + + rtw_free_assoc_resources(padapter, 1); + + if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) { + _clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE); + set_fwstate(pmlmepriv, WIFI_ADHOC_STATE); + } + } + } + +handle_tkip_countermeasure: + if (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) { + status = _FAIL; + goto release_mlme_lock; + } + + if (rtw_validate_ssid(ssid) == _FALSE) { + status = _FAIL; + goto release_mlme_lock; + } + + _rtw_memcpy(&pmlmepriv->assoc_ssid, ssid, sizeof(NDIS_802_11_SSID)); + pmlmepriv->assoc_by_bssid=_FALSE; + + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) { + pmlmepriv->to_join = _TRUE; + } + else { + status = rtw_do_join(padapter); + } + +release_mlme_lock: + _exit_critical_bh(&pmlmepriv->lock, &irqL); + +exit: + RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, + ("-rtw_set_802_11_ssid: status=%d\n", status)); + +_func_exit_; + + return status; + +} + +u8 rtw_set_802_11_connect(_adapter* padapter, u8 *bssid, NDIS_802_11_SSID *ssid) +{ + _irqL irqL; + u8 status = _SUCCESS; + u32 cur_time = 0; + bool bssid_valid = _TRUE; + bool ssid_valid = _TRUE; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + +_func_enter_; + + if (!ssid || rtw_validate_ssid(ssid) == _FALSE) + ssid_valid = _FALSE; + + if (!bssid || rtw_validate_bssid(bssid) == _FALSE) + bssid_valid = _FALSE; + + if (ssid_valid == _FALSE && bssid_valid == _FALSE) { + DBG_871X(FUNC_ADPT_FMT" ssid:%p, ssid_valid:%d, bssid:%p, bssid_valid:%d\n", + FUNC_ADPT_ARG(padapter), ssid, ssid_valid, bssid, bssid_valid); + status = _FAIL; + goto exit; + } + + if (!rtw_is_hw_init_completed(padapter)) { + RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, + ("set_ssid: hw_init_completed==_FALSE=>exit!!!\n")); + status = _FAIL; + goto exit; + } + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" fw_state=0x%08x\n", + FUNC_ADPT_ARG(padapter), get_fwstate(pmlmepriv)); + + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) { + goto handle_tkip_countermeasure; + } else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) { + goto release_mlme_lock; + } + +handle_tkip_countermeasure: + if (rtw_handle_tkip_countermeasure(padapter, __func__) == _FAIL) { + status = _FAIL; + goto release_mlme_lock; + } + + if (ssid && ssid_valid) + _rtw_memcpy(&pmlmepriv->assoc_ssid, ssid, sizeof(NDIS_802_11_SSID)); + else + _rtw_memset(&pmlmepriv->assoc_ssid, 0, sizeof(NDIS_802_11_SSID)); + + if (bssid && bssid_valid) { + _rtw_memcpy(&pmlmepriv->assoc_bssid, bssid, ETH_ALEN); + pmlmepriv->assoc_by_bssid = _TRUE; + } else { + pmlmepriv->assoc_by_bssid = _FALSE; + } + + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) { + pmlmepriv->to_join = _TRUE; + } + else { + status = rtw_do_join(padapter); + } + +release_mlme_lock: + _exit_critical_bh(&pmlmepriv->lock, &irqL); + +exit: + +_func_exit_; + + return status; +} + +u8 rtw_set_802_11_infrastructure_mode(_adapter* padapter, + NDIS_802_11_NETWORK_INFRASTRUCTURE networktype) +{ + _irqL irqL; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wlan_network *cur_network = &pmlmepriv->cur_network; + NDIS_802_11_NETWORK_INFRASTRUCTURE* pold_state = &(cur_network->network.InfrastructureMode); + +_func_enter_; + + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_notice_, + ("+rtw_set_802_11_infrastructure_mode: old=%d new=%d fw_state=0x%08x\n", + *pold_state, networktype, get_fwstate(pmlmepriv))); + + if(*pold_state != networktype) + { + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,(" change mode!")); + //DBG_871X("change mode, old_mode=%d, new_mode=%d, fw_state=0x%x\n", *pold_state, networktype, get_fwstate(pmlmepriv)); + + if(*pold_state==Ndis802_11APMode) + { + //change to other mode from Ndis802_11APMode + cur_network->join_res = -1; + +#ifdef CONFIG_NATIVEAP_MLME + stop_ap_mode(padapter); +#endif + } + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + if((check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) ||(*pold_state==Ndis802_11IBSS)) + rtw_disassoc_cmd(padapter, 0, _TRUE); + + if((check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)== _TRUE) ) + rtw_free_assoc_resources(padapter, 1); + + if((*pold_state == Ndis802_11Infrastructure) ||(*pold_state == Ndis802_11IBSS)) + { + if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + { + rtw_indicate_disconnect(padapter, 0, _FALSE); /*will clr Linked_state; before this function, we must have checked whether issue dis-assoc_cmd or not*/ + } + } + + *pold_state = networktype; + + _clr_fwstate_(pmlmepriv, ~WIFI_NULL_STATE); + + switch(networktype) + { + case Ndis802_11IBSS: + set_fwstate(pmlmepriv, WIFI_ADHOC_STATE); + break; + + case Ndis802_11Infrastructure: + set_fwstate(pmlmepriv, WIFI_STATION_STATE); + break; + + case Ndis802_11APMode: + set_fwstate(pmlmepriv, WIFI_AP_STATE); +#ifdef CONFIG_NATIVEAP_MLME + start_ap_mode(padapter); + //rtw_indicate_connect(padapter); +#endif + + break; + + case Ndis802_11AutoUnknown: + case Ndis802_11InfrastructureMax: + break; + case Ndis802_11Monitor: + set_fwstate(pmlmepriv, WIFI_MONITOR_STATE); + break; + } + + //SecClearAllKeys(adapter); + + //RT_TRACE(COMP_OID_SET, DBG_LOUD, ("set_infrastructure: fw_state:%x after changing mode\n", + // get_fwstate(pmlmepriv) )); + + _exit_critical_bh(&pmlmepriv->lock, &irqL); + } + +_func_exit_; + + return _TRUE; +} + + +u8 rtw_set_802_11_disassociate(_adapter *padapter) +{ + _irqL irqL; + struct mlme_priv * pmlmepriv = &padapter->mlmepriv; + +_func_enter_; + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + { + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("MgntActrtw_set_802_11_disassociate: rtw_indicate_disconnect\n")); + + rtw_disassoc_cmd(padapter, 0, _TRUE); + rtw_indicate_disconnect(padapter, 0, _FALSE); + //modify for CONFIG_IEEE80211W, none 11w can use it + rtw_free_assoc_resources_cmd(padapter); + if (_FAIL == rtw_pwr_wakeup(padapter)) + DBG_871X("%s(): rtw_pwr_wakeup fail !!!\n",__FUNCTION__); + } + + _exit_critical_bh(&pmlmepriv->lock, &irqL); + +_func_exit_; + + return _TRUE; +} + +u8 rtw_set_802_11_bssid_list_scan(_adapter* padapter, NDIS_802_11_SSID *pssid, int ssid_max_num) +{ + _irqL irqL; + struct mlme_priv *pmlmepriv= &padapter->mlmepriv; + u8 res=_TRUE; + +_func_enter_; + + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("+rtw_set_802_11_bssid_list_scan(), fw_state=%x\n", get_fwstate(pmlmepriv))); + + if (padapter == NULL) { + res=_FALSE; + goto exit; + } + if (!rtw_is_hw_init_completed(padapter)) { + res = _FALSE; + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n===rtw_set_802_11_bssid_list_scan:hw_init_completed==_FALSE===\n")); + goto exit; + } + + if ((check_fwstate(pmlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE) || + (pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE)) + { + // Scan or linking is in progress, do nothing. + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("rtw_set_802_11_bssid_list_scan fail since fw_state = %x\n", get_fwstate(pmlmepriv))); + res = _TRUE; + + if(check_fwstate(pmlmepriv, (_FW_UNDER_SURVEY|_FW_UNDER_LINKING))== _TRUE){ + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n###_FW_UNDER_SURVEY|_FW_UNDER_LINKING\n\n")); + } else { + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n###pmlmepriv->sitesurveyctrl.traffic_busy==_TRUE\n\n")); + } + } else { + if (rtw_is_scan_deny(padapter)) { + DBG_871X(FUNC_ADPT_FMT": scan deny\n", FUNC_ADPT_ARG(padapter)); + indicate_wx_scan_complete_event(padapter); + return _SUCCESS; + } + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + res = rtw_sitesurvey_cmd(padapter, pssid, ssid_max_num, NULL, 0); + + _exit_critical_bh(&pmlmepriv->lock, &irqL); + } +exit: + +_func_exit_; + + return res; +} + +u8 rtw_set_802_11_authentication_mode(_adapter* padapter, NDIS_802_11_AUTHENTICATION_MODE authmode) +{ + struct security_priv *psecuritypriv = &padapter->securitypriv; + int res; + u8 ret; + +_func_enter_; + + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("set_802_11_auth.mode(): mode=%x\n", authmode)); + + psecuritypriv->ndisauthtype=authmode; + + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_authentication_mode:psecuritypriv->ndisauthtype=%d", psecuritypriv->ndisauthtype)); + + if(psecuritypriv->ndisauthtype>3) + psecuritypriv->dot11AuthAlgrthm=dot11AuthAlgrthm_8021X; + +#ifdef CONFIG_WAPI_SUPPORT + if(psecuritypriv->ndisauthtype == 6) + psecuritypriv->dot11AuthAlgrthm=dot11AuthAlgrthm_WAPI; +#endif + + res=rtw_set_auth(padapter,psecuritypriv); + + if(res==_SUCCESS) + ret=_TRUE; + else + ret=_FALSE; + +_func_exit_; + + return ret; +} + +u8 rtw_set_802_11_add_wep(_adapter* padapter, NDIS_802_11_WEP *wep){ + + u8 bdefaultkey; + u8 btransmitkey; + sint keyid,res; + struct security_priv* psecuritypriv=&(padapter->securitypriv); + u8 ret=_SUCCESS; + +_func_enter_; + + bdefaultkey=(wep->KeyIndex & 0x40000000) > 0 ? _FALSE : _TRUE; //for ??? + btransmitkey= (wep->KeyIndex & 0x80000000) > 0 ? _TRUE : _FALSE; //for ??? + keyid=wep->KeyIndex & 0x3fffffff; + + if(keyid>=4) + { + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("MgntActrtw_set_802_11_add_wep:keyid>4=>fail\n")); + ret=_FALSE; + goto exit; + } + + switch(wep->KeyLength) + { + case 5: + psecuritypriv->dot11PrivacyAlgrthm=_WEP40_; + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("MgntActrtw_set_802_11_add_wep:wep->KeyLength=5\n")); + break; + case 13: + psecuritypriv->dot11PrivacyAlgrthm=_WEP104_; + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("MgntActrtw_set_802_11_add_wep:wep->KeyLength=13\n")); + break; + default: + psecuritypriv->dot11PrivacyAlgrthm=_NO_PRIVACY_; + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("MgntActrtw_set_802_11_add_wep:wep->KeyLength!=5 or 13\n")); + break; + } + + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_add_wep:befor memcpy, wep->KeyLength=0x%x wep->KeyIndex=0x%x keyid =%x\n",wep->KeyLength,wep->KeyIndex,keyid)); + + _rtw_memcpy(&(psecuritypriv->dot11DefKey[keyid].skey[0]),&(wep->KeyMaterial),wep->KeyLength); + + psecuritypriv->dot11DefKeylen[keyid]=wep->KeyLength; + + psecuritypriv->dot11PrivacyKeyIndex=keyid; + + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_add_wep:security key material : %x %x %x %x %x %x %x %x %x %x %x %x %x \n", + psecuritypriv->dot11DefKey[keyid].skey[0],psecuritypriv->dot11DefKey[keyid].skey[1],psecuritypriv->dot11DefKey[keyid].skey[2], + psecuritypriv->dot11DefKey[keyid].skey[3],psecuritypriv->dot11DefKey[keyid].skey[4],psecuritypriv->dot11DefKey[keyid].skey[5], + psecuritypriv->dot11DefKey[keyid].skey[6],psecuritypriv->dot11DefKey[keyid].skey[7],psecuritypriv->dot11DefKey[keyid].skey[8], + psecuritypriv->dot11DefKey[keyid].skey[9],psecuritypriv->dot11DefKey[keyid].skey[10],psecuritypriv->dot11DefKey[keyid].skey[11], + psecuritypriv->dot11DefKey[keyid].skey[12])); + + res=rtw_set_key(padapter,psecuritypriv, keyid, 1, _TRUE); + + if(res==_FAIL) + ret= _FALSE; +exit: + +_func_exit_; + + return ret; + +} + +u8 rtw_set_802_11_remove_wep(_adapter* padapter, u32 keyindex){ + + u8 ret=_SUCCESS; + +_func_enter_; + + if (keyindex >= 0x80000000 || padapter == NULL){ + + ret=_FALSE; + goto exit; + + } + else + { + int res; + struct security_priv* psecuritypriv=&(padapter->securitypriv); + if( keyindex < 4 ){ + + _rtw_memset(&psecuritypriv->dot11DefKey[keyindex], 0, 16); + + res=rtw_set_key(padapter,psecuritypriv,keyindex, 0, _TRUE); + + psecuritypriv->dot11DefKeylen[keyindex]=0; + + if(res==_FAIL) + ret=_FAIL; + + } + else + { + ret=_FAIL; + } + + } + +exit: + +_func_exit_; + + return ret; + +} + +u8 rtw_set_802_11_add_key(_adapter* padapter, NDIS_802_11_KEY *key){ + + uint encryptionalgo; + u8 * pbssid; + struct sta_info *stainfo; + u8 bgroup = _FALSE; + u8 bgrouptkey = _FALSE;//can be remove later + u8 ret=_SUCCESS; + +_func_enter_; + + if (((key->KeyIndex & 0x80000000) == 0) && ((key->KeyIndex & 0x40000000) > 0)){ + + // It is invalid to clear bit 31 and set bit 30. If the miniport driver encounters this combination, + // it must fail the request and return NDIS_STATUS_INVALID_DATA. + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_add_key: ((key->KeyIndex & 0x80000000) == 0)[=%d] ",(int)(key->KeyIndex & 0x80000000) == 0)); + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_add_key:((key->KeyIndex & 0x40000000) > 0)[=%d]" , (int)(key->KeyIndex & 0x40000000) > 0)); + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_add_key: key->KeyIndex=%d \n" ,(int)key->KeyIndex)); + ret= _FAIL; + goto exit; + } + + if(key->KeyIndex & 0x40000000) + { + // Pairwise key + + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY: +++++ Pairwise key +++++\n")); + + pbssid=get_bssid(&padapter->mlmepriv); + stainfo=rtw_get_stainfo(&padapter->stapriv, pbssid); + + if((stainfo!=NULL)&&(padapter->securitypriv.dot11AuthAlgrthm==dot11AuthAlgrthm_8021X)){ + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY:( stainfo!=NULL)&&(Adapter->securitypriv.dot11AuthAlgrthm==dot11AuthAlgrthm_8021X)\n")); + encryptionalgo=stainfo->dot118021XPrivacy; + } + else{ + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY: stainfo==NULL)||(Adapter->securitypriv.dot11AuthAlgrthm!=dot11AuthAlgrthm_8021X)\n")); + encryptionalgo=padapter->securitypriv.dot11PrivacyAlgrthm; + } + + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("rtw_set_802_11_add_key: (encryptionalgo ==%d)!\n",encryptionalgo )); + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("rtw_set_802_11_add_key: (Adapter->securitypriv.dot11PrivacyAlgrthm ==%d)!\n",padapter->securitypriv.dot11PrivacyAlgrthm)); + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("rtw_set_802_11_add_key: (Adapter->securitypriv.dot11AuthAlgrthm ==%d)!\n",padapter->securitypriv.dot11AuthAlgrthm)); + + if((stainfo!=NULL)){ + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("rtw_set_802_11_add_key: (stainfo->dot118021XPrivacy ==%d)!\n", stainfo->dot118021XPrivacy)); + } + + if(key->KeyIndex & 0x000000FF){ + // The key index is specified in the lower 8 bits by values of zero to 255. + // The key index should be set to zero for a Pairwise key, and the driver should fail with + // NDIS_STATUS_INVALID_DATA if the lower 8 bits is not zero + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,(" key->KeyIndex & 0x000000FF.\n")); + ret= _FAIL; + goto exit; + } + + // check BSSID + if (IS_MAC_ADDRESS_BROADCAST(key->BSSID) == _TRUE){ + + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("MacAddr_isBcst(key->BSSID)\n")); + ret= _FALSE; + goto exit; + } + + // Check key length for TKIP. + //if(encryptionAlgorithm == RT_ENC_TKIP_ENCRYPTION && key->KeyLength != 32) + if((encryptionalgo== _TKIP_)&& (key->KeyLength != 32)){ + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("TKIP KeyLength:0x%x != 32\n", key->KeyLength)); + ret=_FAIL; + goto exit; + + } + + // Check key length for AES. + if((encryptionalgo== _AES_)&& (key->KeyLength != 16)) { + // For our supplicant, EAPPkt9x.vxd, cannot differentiate TKIP and AES case. + if(key->KeyLength == 32) { + key->KeyLength = 16; + } else { + ret= _FAIL; + goto exit; + } + } + + /* Check key length for WEP. For NDTEST, 2005.01.27, by rcnjko. -> modify checking condition*/ + if (((encryptionalgo == _WEP40_) && (key->KeyLength != 5)) || ((encryptionalgo == _WEP104_) && (key->KeyLength != 13))) { + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("WEP KeyLength:0x%x != 5 or 13\n", key->KeyLength)); + ret=_FAIL; + goto exit; + } + + bgroup = _FALSE; + + // Check the pairwise key. Added by Annie, 2005-07-06. + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("------------------------------------------\n")); + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("[Pairwise Key set]\n")); + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("------------------------------------------\n")); + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("key index: 0x%8x(0x%8x)\n", key->KeyIndex,(key->KeyIndex&0x3))); + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("key Length: %d\n", key->KeyLength)); + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("------------------------------------------\n")); + + } + else + { + // Group key - KeyIndex(BIT30==0) + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY: +++++ Group key +++++\n")); + + + // when add wep key through add key and didn't assigned encryption type before + if((padapter->securitypriv.ndisauthtype<=3)&&(padapter->securitypriv.dot118021XGrpPrivacy==0)) + { + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("keylen=%d( Adapter->securitypriv.dot11PrivacyAlgrthm=%x )padapter->securitypriv.dot118021XGrpPrivacy(%x)\n", key->KeyLength,padapter->securitypriv.dot11PrivacyAlgrthm,padapter->securitypriv.dot118021XGrpPrivacy)); + + switch(key->KeyLength) + { + case 5: + padapter->securitypriv.dot11PrivacyAlgrthm=_WEP40_; + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("Adapter->securitypriv.dot11PrivacyAlgrthm= %x key->KeyLength=%u\n", padapter->securitypriv.dot11PrivacyAlgrthm,key->KeyLength)); + break; + case 13: + padapter->securitypriv.dot11PrivacyAlgrthm=_WEP104_; + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("Adapter->securitypriv.dot11PrivacyAlgrthm= %x key->KeyLength=%u\n", padapter->securitypriv.dot11PrivacyAlgrthm,key->KeyLength)); + break; + default: + padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_; + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("Adapter->securitypriv.dot11PrivacyAlgrthm= %x key->KeyLength=%u \n", padapter->securitypriv.dot11PrivacyAlgrthm,key->KeyLength)); + break; + } + + encryptionalgo=padapter->securitypriv.dot11PrivacyAlgrthm; + + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,(" Adapter->securitypriv.dot11PrivacyAlgrthm=%x\n", padapter->securitypriv.dot11PrivacyAlgrthm)); + + } + else + { + encryptionalgo=padapter->securitypriv.dot118021XGrpPrivacy; + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("( Adapter->securitypriv.dot11PrivacyAlgrthm=%x )encryptionalgo(%x)=padapter->securitypriv.dot118021XGrpPrivacy(%x)keylen=%d\n", padapter->securitypriv.dot11PrivacyAlgrthm,encryptionalgo,padapter->securitypriv.dot118021XGrpPrivacy,key->KeyLength)); + + } + + if((check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE)==_TRUE) && (IS_MAC_ADDRESS_BROADCAST(key->BSSID) == _FALSE)) { + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,(" IBSS but BSSID is not Broadcast Address.\n")); + ret= _FAIL; + goto exit; + } + + // Check key length for TKIP + if((encryptionalgo== _TKIP_) && (key->KeyLength != 32)) { + + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,(" TKIP GTK KeyLength:%u != 32\n", key->KeyLength)); + ret= _FAIL; + goto exit; + + } else if(encryptionalgo== _AES_ && (key->KeyLength != 16 && key->KeyLength != 32) ) { + + // Check key length for AES + // For NDTEST, we allow keylen=32 in this case. 2005.01.27, by rcnjko. + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("<=== SetInfo, OID_802_11_ADD_KEY: AES GTK KeyLength:%u != 16 or 32\n", key->KeyLength)); + ret= _FAIL; + goto exit; + } + + // Change the key length for EAPPkt9x.vxd. Added by Annie, 2005-11-03. + if((encryptionalgo== _AES_) && (key->KeyLength == 32) ) { + key->KeyLength = 16; + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("AES key length changed: %u\n", key->KeyLength) ); + } + + if(key->KeyIndex & 0x8000000) {//error ??? 0x8000_0000 + bgrouptkey = _TRUE; + } + + if((check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE)==_TRUE)&&(check_fwstate(&padapter->mlmepriv, _FW_LINKED)==_TRUE)) + { + bgrouptkey = _TRUE; + } + + bgroup = _TRUE; + + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("------------------------------------------\n") ); + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("[Group Key set]\n") ); + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("------------------------------------------\n")) ; + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("key index: 0x%8x(0x%8x)\n", key->KeyIndex,(key->KeyIndex&0x3))); + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("key Length: %d\n", key->KeyLength)) ; + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("------------------------------------------\n")); + + } + + // If WEP encryption algorithm, just call rtw_set_802_11_add_wep(). + if((padapter->securitypriv.dot11AuthAlgrthm !=dot11AuthAlgrthm_8021X)&&(encryptionalgo== _WEP40_ || encryptionalgo== _WEP104_)) + { + u8 ret; + u32 keyindex; + u32 len = FIELD_OFFSET(NDIS_802_11_KEY, KeyMaterial) + key->KeyLength; + NDIS_802_11_WEP *wep = &padapter->securitypriv.ndiswep; + + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY: +++++ WEP key +++++\n")); + + wep->Length = len; + keyindex = key->KeyIndex&0x7fffffff; + wep->KeyIndex = keyindex ; + wep->KeyLength = key->KeyLength; + + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY:Before memcpy \n")); + + _rtw_memcpy(wep->KeyMaterial, key->KeyMaterial, key->KeyLength); + _rtw_memcpy(&(padapter->securitypriv.dot11DefKey[keyindex].skey[0]), key->KeyMaterial, key->KeyLength); + + padapter->securitypriv.dot11DefKeylen[keyindex]=key->KeyLength; + padapter->securitypriv.dot11PrivacyKeyIndex=keyindex; + + ret = rtw_set_802_11_add_wep(padapter, wep); + + goto exit; + + } + + if(key->KeyIndex & 0x20000000){ + // SetRSC + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY: +++++ SetRSC+++++\n")); + if(bgroup == _TRUE) + { + NDIS_802_11_KEY_RSC keysrc=key->KeyRSC & 0x00FFFFFFFFFFFFULL; + _rtw_memcpy(&padapter->securitypriv.dot11Grprxpn, &keysrc, 8); + } + else + { + NDIS_802_11_KEY_RSC keysrc=key->KeyRSC & 0x00FFFFFFFFFFFFULL; + _rtw_memcpy(&padapter->securitypriv.dot11Grptxpn, &keysrc, 8); + } + + } + + // Indicate this key idx is used for TX + // Save the key in KeyMaterial + if(bgroup == _TRUE) // Group transmit key + { + int res; + + if(bgrouptkey == _TRUE) + { + padapter->securitypriv.dot118021XGrpKeyid=(u8)key->KeyIndex; + } + + if((key->KeyIndex&0x3) == 0){ + ret = _FAIL; + goto exit; + } + + _rtw_memset(&padapter->securitypriv.dot118021XGrpKey[(u8)((key->KeyIndex) & 0x03)], 0, 16); + _rtw_memset(&padapter->securitypriv.dot118021XGrptxmickey[(u8)((key->KeyIndex) & 0x03)], 0, 16); + _rtw_memset(&padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)], 0, 16); + + if((key->KeyIndex & 0x10000000)) + { + _rtw_memcpy(&padapter->securitypriv.dot118021XGrptxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 16, 8); + _rtw_memcpy(&padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 24, 8); + + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n rtw_set_802_11_add_key:rx mic :0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n", + padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[0],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[1], + padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[2],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[3], + padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[4],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[5], + padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[6],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[7])); + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n rtw_set_802_11_add_key:set Group mic key!!!!!!!!\n")); + + } + else + { + _rtw_memcpy(&padapter->securitypriv.dot118021XGrptxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 24, 8); + _rtw_memcpy(&padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 16, 8); + + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n rtw_set_802_11_add_key:rx mic :0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n", + padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[0],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[1], + padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[2],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[3], + padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[4],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[5], + padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[6],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[7])); + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n rtw_set_802_11_add_key:set Group mic key!!!!!!!!\n")); + + } + + //set group key by index + _rtw_memcpy(&padapter->securitypriv.dot118021XGrpKey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial, key->KeyLength); + + key->KeyIndex=key->KeyIndex & 0x03; + + padapter->securitypriv.binstallGrpkey=_TRUE; + + padapter->securitypriv.bcheck_grpkey=_FALSE; + + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("reset group key")); + + res=rtw_set_key(padapter,&padapter->securitypriv, key->KeyIndex, 1, _TRUE); + + if(res==_FAIL) + ret= _FAIL; + + goto exit; + + } + else // Pairwise Key + { + u8 res; + + pbssid=get_bssid(&padapter->mlmepriv); + stainfo=rtw_get_stainfo(&padapter->stapriv , pbssid ); + + if(stainfo!=NULL) + { + _rtw_memset( &stainfo->dot118021x_UncstKey, 0, 16);// clear keybuffer + + _rtw_memcpy(&stainfo->dot118021x_UncstKey, key->KeyMaterial, 16); + + if(encryptionalgo== _TKIP_) + { + padapter->securitypriv.busetkipkey=_FALSE; + + //_set_timer(&padapter->securitypriv.tkip_timer, 50); + + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n ==========_set_timer\n")); + + // if TKIP, save the Receive/Transmit MIC key in KeyMaterial[128-255] + if((key->KeyIndex & 0x10000000)){ + _rtw_memcpy(&stainfo->dot11tkiptxmickey, key->KeyMaterial + 16, 8); + _rtw_memcpy(&stainfo->dot11tkiprxmickey, key->KeyMaterial + 24, 8); + + } else { + _rtw_memcpy(&stainfo->dot11tkiptxmickey, key->KeyMaterial + 24, 8); + _rtw_memcpy(&stainfo->dot11tkiprxmickey, key->KeyMaterial + 16, 8); + + } + + } + else if(encryptionalgo == _AES_) + { + + } + + + //Set key to CAM through H2C command + #if 0 + if(bgrouptkey)//never go to here + { + res=rtw_setstakey_cmd(padapter, stainfo, GROUP_KEY, _TRUE); + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n rtw_set_802_11_add_key:rtw_setstakey_cmd(group)\n")); + } + else{ + res=rtw_setstakey_cmd(padapter, stainfo, UNICAST_KEY, _TRUE); + RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n rtw_set_802_11_add_key:rtw_setstakey_cmd(unicast)\n")); + } + #else + + res = rtw_setstakey_cmd(padapter, stainfo, UNICAST_KEY, _TRUE); + RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("\n rtw_set_802_11_add_key:rtw_setstakey_cmd(unicast)\n")); + #endif + + if(res ==_FALSE) + ret= _FAIL; + + } + + } + +exit: + +_func_exit_; + + return ret; +} + +u8 rtw_set_802_11_remove_key(_adapter* padapter, NDIS_802_11_REMOVE_KEY *key){ + + uint encryptionalgo; + u8 * pbssid; + struct sta_info *stainfo; + u8 bgroup = (key->KeyIndex & 0x4000000) > 0 ? _FALSE: _TRUE; + u8 keyIndex = (u8)key->KeyIndex & 0x03; + u8 ret=_SUCCESS; + +_func_enter_; + + if ((key->KeyIndex & 0xbffffffc) > 0) { + ret=_FAIL; + goto exit; + } + + if (bgroup == _TRUE) { + encryptionalgo= padapter->securitypriv.dot118021XGrpPrivacy; + // clear group key by index + //NdisZeroMemory(Adapter->MgntInfo.SecurityInfo.KeyBuf[keyIndex], MAX_WEP_KEY_LEN); + //Adapter->MgntInfo.SecurityInfo.KeyLen[keyIndex] = 0; + + _rtw_memset(&padapter->securitypriv.dot118021XGrpKey[keyIndex], 0, 16); + + //! \todo Send a H2C Command to Firmware for removing this Key in CAM Entry. + + } else { + + pbssid=get_bssid(&padapter->mlmepriv); + stainfo=rtw_get_stainfo(&padapter->stapriv , pbssid ); + if(stainfo !=NULL){ + encryptionalgo=stainfo->dot118021XPrivacy; + + // clear key by BSSID + _rtw_memset(&stainfo->dot118021x_UncstKey, 0, 16); + + //! \todo Send a H2C Command to Firmware for disable this Key in CAM Entry. + + } + else{ + ret= _FAIL; + goto exit; + } + } + +exit: + +_func_exit_; + + return _TRUE; + +} + +/* +* rtw_get_cur_max_rate - +* @adapter: pointer to _adapter structure +* +* Return 0 or 100Kbps +*/ +u16 rtw_get_cur_max_rate(_adapter *adapter) +{ + int i = 0; + u16 rate = 0, max_rate = 0; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network; + struct sta_info *psta = NULL; + u8 short_GI=0; +#ifdef CONFIG_80211N_HT + u8 rf_type = 0; +#endif + +#ifdef CONFIG_MP_INCLUDED + if (adapter->registrypriv.mp_mode == 1) + { + if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) + return 0; + } +#endif + + if((check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) + && (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) != _TRUE)) + return 0; + + psta = rtw_get_stainfo(&adapter->stapriv, get_bssid(pmlmepriv)); + if (psta == NULL) + return 0; + + short_GI = query_ra_short_GI(psta); + +#ifdef CONFIG_80211N_HT + if (IsSupportedHT(psta->wireless_mode)) { + rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + + max_rate = rtw_mcs_rate( + rf_type, + ((psta->bw_mode == CHANNEL_WIDTH_40)?1:0), + short_GI, + psta->htpriv.ht_cap.supp_mcs_set + ); + } +#ifdef CONFIG_80211AC_VHT + else if (IsSupportedVHT(psta->wireless_mode)) { + max_rate = ((rtw_vht_mcs_to_data_rate(psta->bw_mode, short_GI, pmlmepriv->vhtpriv.vht_highest_rate) + 1) >> 1) * 10; + } +#endif //CONFIG_80211AC_VHT + else +#endif //CONFIG_80211N_HT + { + while( (pcur_bss->SupportedRates[i]!=0) && (pcur_bss->SupportedRates[i]!=0xFF)) + { + rate = pcur_bss->SupportedRates[i]&0x7F; + if(rate>max_rate) + max_rate = rate; + i++; + } + + max_rate = max_rate*10/2; + } + + return max_rate; +} + +/* +* rtw_set_scan_mode - +* @adapter: pointer to _adapter structure +* @scan_mode: +* +* Return _SUCCESS or _FAIL +*/ +int rtw_set_scan_mode(_adapter *adapter, RT_SCAN_TYPE scan_mode) +{ + if(scan_mode != SCAN_ACTIVE && scan_mode != SCAN_PASSIVE) + return _FAIL; + + adapter->mlmepriv.scan_mode = scan_mode; + + return _SUCCESS; +} + +/* +* rtw_set_channel_plan - +* @adapter: pointer to _adapter structure +* @channel_plan: +* +* Return _SUCCESS or _FAIL +*/ +int rtw_set_channel_plan(_adapter *adapter, u8 channel_plan) +{ + struct registry_priv *pregistrypriv = &adapter->registrypriv; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + + //handle by cmd_thread to sync with scan operation + return rtw_set_chplan_cmd(adapter, RTW_CMDF_WAIT_ACK, channel_plan, 1); +} + +/* +* rtw_set_country - +* @adapter: pointer to _adapter structure +* @country_code: string of country code +* +* Return _SUCCESS or _FAIL +*/ +int rtw_set_country(_adapter *adapter, const char *country_code) +{ +#ifdef CONFIG_RTW_IOCTL_SET_COUNTRY + return rtw_set_country_cmd(adapter, RTW_CMDF_WAIT_ACK, country_code, 1); +#else + return _FAIL; +#endif +} + +/* +* rtw_set_band - +* @adapter: pointer to _adapter structure +* @band: band to set +* +* Return _SUCCESS or _FAIL +*/ +int rtw_set_band(_adapter *adapter, u8 band) +{ + if (rtw_band_valid(band)) { + DBG_871X(FUNC_ADPT_FMT" band:%d\n", FUNC_ADPT_ARG(adapter), band); + adapter->setband = band; + return _SUCCESS; + } + + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" band:%d fail\n", FUNC_ADPT_ARG(adapter), band); + return _FAIL; +} + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_iol.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_iol.c new file mode 100644 index 000000000..3524e1c5a --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_iol.c @@ -0,0 +1,390 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include + +#ifdef CONFIG_IOL +struct xmit_frame *rtw_IOL_accquire_xmit_frame(ADAPTER *adapter) +{ + struct xmit_frame *xmit_frame; + struct xmit_buf *xmitbuf; + struct pkt_attrib *pattrib; + struct xmit_priv *pxmitpriv = &(adapter->xmitpriv); + +#if 1 + if ((xmit_frame = rtw_alloc_xmitframe(pxmitpriv)) == NULL) + { + DBG_871X("%s rtw_alloc_xmitframe return null\n", __FUNCTION__); + goto exit; + } + + if ((xmitbuf = rtw_alloc_xmitbuf(pxmitpriv)) == NULL) + { + DBG_871X("%s rtw_alloc_xmitbuf return null\n", __FUNCTION__); + rtw_free_xmitframe(pxmitpriv, xmit_frame); + xmit_frame=NULL; + goto exit; + } + + xmit_frame->frame_tag = MGNT_FRAMETAG; + xmit_frame->pxmitbuf = xmitbuf; + xmit_frame->buf_addr = xmitbuf->pbuf; + xmitbuf->priv_data = xmit_frame; + + pattrib = &xmit_frame->attrib; + update_mgntframe_attrib(adapter, pattrib); + pattrib->qsel = QSLT_BEACON;//Beacon + pattrib->subtype = WIFI_BEACON; + pattrib->pktlen = pattrib->last_txcmdsz = 0; + +#else + if ((xmit_frame = alloc_mgtxmitframe(pxmitpriv)) == NULL) + { + DBG_871X("%s alloc_mgtxmitframe return null\n", __FUNCTION__); + } + else { + pattrib = &xmit_frame->attrib; + update_mgntframe_attrib(adapter, pattrib); + pattrib->qsel = QSLT_BEACON; + pattrib->pktlen = pattrib->last_txcmdsz = 0; + } +#endif + +exit: + return xmit_frame; +} + + +int rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, u32 cmd_len) +{ + struct pkt_attrib *pattrib = &xmit_frame->attrib; + u16 buf_offset; + u32 ori_len; + + buf_offset = TXDESC_OFFSET; + ori_len = buf_offset+pattrib->pktlen; + + //check if the io_buf can accommodate new cmds + if(ori_len + cmd_len + 8 > MAX_XMITBUF_SZ) { + DBG_871X("%s %u is large than MAX_XMITBUF_SZ:%u, can't accommodate new cmds\n", __FUNCTION__ + , ori_len + cmd_len + 8, MAX_XMITBUF_SZ); + return _FAIL; + } + + _rtw_memcpy(xmit_frame->buf_addr + buf_offset + pattrib->pktlen, IOL_cmds, cmd_len); + pattrib->pktlen += cmd_len; + pattrib->last_txcmdsz += cmd_len; + + //DBG_871X("%s ori:%u + cmd_len:%u = %u\n", __FUNCTION__, ori_len, cmd_len, buf_offset+pattrib->pktlen); + + return _SUCCESS; +} + +bool rtw_IOL_applied(ADAPTER *adapter) +{ + if(1 == adapter->registrypriv.fw_iol) + return _TRUE; + +#ifdef CONFIG_USB_HCI + if((2 == adapter->registrypriv.fw_iol) && (IS_FULL_SPEED_USB(adapter))) + return _TRUE; +#endif + + return _FALSE; +} + +int rtw_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt) +{ + return rtw_hal_iol_cmd(adapter, xmit_frame, max_wating_ms,bndy_cnt); +} + +#ifdef CONFIG_IOL_NEW_GENERATION +int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary) +{ + return _SUCCESS; +} +int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, u8 mask) +{ + struct ioreg_cfg cmd = {8,IOREG_CMD_WB_REG,0x0, 0x0,0x0}; + + //RTW_PUT_LE16((u8*)&cmd.address, addr); + //RTW_PUT_LE32((u8*)&cmd.value, (u32)value); + cmd.address = cpu_to_le16(addr); + cmd.data = cpu_to_le32(value); + + if(mask!=0xFF) + { + cmd.length = 12; + //RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask); + cmd.mask = cpu_to_le32(mask); + } + + //DBG_871X("%s addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FUNCTION__, addr,value,mask); + + return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, cmd.length); + +} +int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, u16 mask) +{ + struct ioreg_cfg cmd = {8,IOREG_CMD_WW_REG,0x0, 0x0,0x0}; + + //RTW_PUT_LE16((u8*)&cmd.address, addr); + //RTW_PUT_LE32((u8*)&cmd.value, (u32)value); + cmd.address = cpu_to_le16(addr); + cmd.data = cpu_to_le32(value); + + if(mask!=0xFFFF) + { + cmd.length = 12; + //RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask); + cmd.mask = cpu_to_le32(mask); + } + + //DBG_871X("%s addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FUNCTION__, addr,value,mask); + + return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, cmd.length); + +} +int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, u32 mask) +{ + struct ioreg_cfg cmd = {8,IOREG_CMD_WD_REG,0x0, 0x0,0x0}; + + //RTW_PUT_LE16((u8*)&cmd.address, addr); + //RTW_PUT_LE32((u8*)&cmd.value, (u32)value); + cmd.address = cpu_to_le16(addr); + cmd.data = cpu_to_le32(value); + + if(mask!=0xFFFFFFFF) + { + cmd.length = 12; + //RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask); + cmd.mask = cpu_to_le32(mask); + } + + //DBG_871X("%s addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FU2NCTION__, addr,value,mask); + + return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, cmd.length); + +} + +int _rtw_IOL_append_WRF_cmd(struct xmit_frame *xmit_frame, u8 rf_path, u16 addr, u32 value, u32 mask) +{ + struct ioreg_cfg cmd = {8,IOREG_CMD_W_RF,0x0, 0x0,0x0}; + + //RTW_PUT_LE16((u8*)&cmd.address, addr); + //RTW_PUT_LE32((u8*)&cmd.value, (u32)value); + cmd.address = (rf_path<<8) |((addr) &0xFF); + cmd.data = cpu_to_le32(value); + + if(mask!=0x000FFFFF) + { + cmd.length = 12; + //RTW_PUT_LE32((u8*)&cmd.mask, (u32)mask); + cmd.mask = cpu_to_le32(mask); + } + + //DBG_871X("%s rf_path:0x%02x addr:0x%04x,value:0x%08x,mask:0x%08x\n", __FU2NCTION__,rf_path, addr,value,mask); + + return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, cmd.length); + +} + + + +int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us) +{ + struct ioreg_cfg cmd = {4,IOREG_CMD_DELAY_US,0x0, 0x0,0x0}; + //RTW_PUT_LE16((u8*)&cmd.address, us); + cmd.address = cpu_to_le16(us); + + //DBG_871X("%s %u\n", __FUNCTION__, us); + return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 4); +} + +int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms) +{ + struct ioreg_cfg cmd = {4,IOREG_CMD_DELAY_US,0x0, 0x0,0x0}; + + //RTW_PUT_LE16((u8*)&cmd.address, ms); + cmd.address = cpu_to_le16(ms); + + //DBG_871X("%s %u\n", __FUNCTION__, ms); + return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 4); +} +int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame) +{ + struct ioreg_cfg cmd = {4,IOREG_CMD_END,0xFFFF, 0xFF,0x0}; + return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 4); + +} + +u8 rtw_IOL_cmd_boundary_handle(struct xmit_frame *pxmit_frame) +{ + u8 is_cmd_bndy = _FALSE; + if(((pxmit_frame->attrib.pktlen+32)%256) + 8 >= 256){ + rtw_IOL_append_END_cmd(pxmit_frame); + pxmit_frame->attrib.pktlen = ((((pxmit_frame->attrib.pktlen+32)/256)+1)*256 ); + + //printk("==> %s, pktlen(%d)\n",__FUNCTION__,pxmit_frame->attrib.pktlen); + pxmit_frame->attrib.last_txcmdsz = pxmit_frame->attrib.pktlen; + is_cmd_bndy = _TRUE; + } + return is_cmd_bndy; +} + +void rtw_IOL_cmd_buf_dump(ADAPTER *Adapter,int buf_len,u8 *pbuf) +{ + int i; + int j=1; + + printk("###### %s ######\n",__FUNCTION__); + for(i=0;i< buf_len;i++){ + printk("%02x-",*(pbuf+i)); + + if(j%32 ==0) printk("\n");j++; + } + printk("\n"); + printk("============= ioreg_cmd len = %d =============== \n",buf_len); +} + + +#else //CONFIG_IOL_NEW_GENERATION +int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary) +{ + IOL_CMD cmd = {0x0, IOL_CMD_LLT, 0x0, 0x0}; + + RTW_PUT_BE32((u8*)&cmd.value, (u32)page_boundary); + + return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8); +} + +int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value) +{ + IOL_CMD cmd = {0x0, IOL_CMD_WB_REG, 0x0, 0x0}; + + RTW_PUT_BE16((u8*)&cmd.address, (u16)addr); + RTW_PUT_BE32((u8*)&cmd.value, (u32)value); + + return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8); +} + +int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value) +{ + IOL_CMD cmd = {0x0, IOL_CMD_WW_REG, 0x0, 0x0}; + + RTW_PUT_BE16((u8*)&cmd.address, (u16)addr); + RTW_PUT_BE32((u8*)&cmd.value, (u32)value); + + return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8); +} + +int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value) +{ + IOL_CMD cmd = {0x0, IOL_CMD_WD_REG, 0x0, 0x0}; + u8* pos = (u8 *)&cmd; + + RTW_PUT_BE16((u8*)&cmd.address, (u16)addr); + RTW_PUT_BE32((u8*)&cmd.value, (u32)value); + + return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8); +} + +#ifdef DBG_IO +int dbg_rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, const char *caller, const int line) +{ + if (match_write_sniff_ranges(addr, 1)) + DBG_871X("DBG_IO %s:%d IOL_WB(0x%04x, 0x%02x)\n", caller, line, addr, value); + + return _rtw_IOL_append_WB_cmd(xmit_frame, addr, value); +} + +int dbg_rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, const char *caller, const int line) +{ + if (match_write_sniff_ranges(addr, 2)) + DBG_871X("DBG_IO %s:%d IOL_WW(0x%04x, 0x%04x)\n", caller, line, addr, value); + + return _rtw_IOL_append_WW_cmd(xmit_frame, addr, value); +} + +int dbg_rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, const char *caller, const int line) +{ + if (match_write_sniff_ranges(addr, 4)) + DBG_871X("DBG_IO %s:%d IOL_WD(0x%04x, 0x%08x)\n", caller, line, addr, value); + + return _rtw_IOL_append_WD_cmd(xmit_frame, addr, value); +} +#endif + +int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us) +{ + IOL_CMD cmd = {0x0, IOL_CMD_DELAY_US, 0x0, 0x0}; + + RTW_PUT_BE32((u8*)&cmd.value, (u32)us); + + //DBG_871X("%s %u\n", __FUNCTION__, us); + + return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8); +} + +int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms) +{ + IOL_CMD cmd = {0x0, IOL_CMD_DELAY_MS, 0x0, 0x0}; + + RTW_PUT_BE32((u8*)&cmd.value, (u32)ms); + + //DBG_871X("%s %u\n", __FUNCTION__, ms); + + return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8); +} + +int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame) +{ + IOL_CMD end_cmd = {0x0, IOL_CMD_END, 0x0, 0x0}; + + + return rtw_IOL_append_cmds(xmit_frame, (u8*)&end_cmd, 8); + +} + +int rtw_IOL_exec_cmd_array_sync(PADAPTER adapter, u8 *IOL_cmds, u32 cmd_num, u32 max_wating_ms) +{ + struct xmit_frame *xmit_frame; + + if((xmit_frame=rtw_IOL_accquire_xmit_frame(adapter)) == NULL) + return _FAIL; + + if(rtw_IOL_append_cmds(xmit_frame, IOL_cmds, cmd_num<<3) == _FAIL) + return _FAIL; + + return rtw_IOL_exec_cmds_sync(adapter, xmit_frame, max_wating_ms,0); +} + +int rtw_IOL_exec_empty_cmds_sync(ADAPTER *adapter, u32 max_wating_ms) +{ + IOL_CMD end_cmd = {0x0, IOL_CMD_END, 0x0, 0x0}; + return rtw_IOL_exec_cmd_array_sync(adapter, (u8*)&end_cmd, 1, max_wating_ms); +} +#endif //CONFIG_IOL_NEW_GENERATION + + + + +#endif //CONFIG_IOL + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_mem.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_mem.c new file mode 100644 index 000000000..db371c1b8 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_mem.c @@ -0,0 +1,122 @@ + +#include +#include + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Realtek Wireless Lan Driver"); +MODULE_AUTHOR("Realtek Semiconductor Corp."); +MODULE_VERSION("DRIVERVERSION"); + +struct sk_buff_head rtk_skb_mem_q; +struct u8* rtk_buf_mem[NR_RECVBUFF]; + +struct u8 * rtw_get_buf_premem(int index) +{ + printk("%s, rtk_buf_mem index : %d\n", __func__, index); + return rtk_buf_mem[index]; +} + +u16 rtw_rtkm_get_buff_size(void) +{ + return MAX_RTKM_RECVBUF_SZ; +} +EXPORT_SYMBOL(rtw_rtkm_get_buff_size); + +u8 rtw_rtkm_get_nr_recv_skb(void) +{ + return MAX_RTKM_NR_PREALLOC_RECV_SKB; +} +EXPORT_SYMBOL(rtw_rtkm_get_nr_recv_skb); + +struct sk_buff *rtw_alloc_skb_premem(u16 in_size) +{ + struct sk_buff *skb = NULL; + + if (in_size > MAX_RTKM_RECVBUF_SZ) { + pr_info("warning %s: driver buffer size(%d) > rtkm buffer size(%d)\n", __func__, in_size, MAX_RTKM_RECVBUF_SZ); + WARN_ON(1); + return skb; + } + + skb = skb_dequeue(&rtk_skb_mem_q); + + printk("%s, rtk_skb_mem_q len : %d\n", __func__, skb_queue_len(&rtk_skb_mem_q)); + + return skb; +} +EXPORT_SYMBOL(rtw_alloc_skb_premem); + +int rtw_free_skb_premem(struct sk_buff *pskb) +{ + if(!pskb) + return -1; + + if (skb_queue_len(&rtk_skb_mem_q) >= MAX_RTKM_NR_PREALLOC_RECV_SKB) + return -1; + + skb_queue_tail(&rtk_skb_mem_q, pskb); + + printk("%s, rtk_skb_mem_q len : %d\n", __func__, skb_queue_len(&rtk_skb_mem_q)); + + return 0; +} +EXPORT_SYMBOL(rtw_free_skb_premem); + +static int __init rtw_mem_init(void) +{ + int i; + SIZE_PTR tmpaddr=0; + SIZE_PTR alignment=0; + struct sk_buff *pskb=NULL; + + printk("%s\n", __func__); + pr_info("MAX_RTKM_NR_PREALLOC_RECV_SKB: %d\n", MAX_RTKM_NR_PREALLOC_RECV_SKB); + pr_info("MAX_RTKM_RECVBUF_SZ: %d\n", MAX_RTKM_RECVBUF_SZ); + +#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX + for(i=0; idata; + alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1); + skb_reserve(pskb, (RECVBUFF_ALIGN_SZ - alignment)); + + skb_queue_tail(&rtk_skb_mem_q, pskb); + } + else + { + printk("%s, alloc skb memory fail!\n", __func__); + } + + pskb=NULL; + } + + printk("%s, rtk_skb_mem_q len : %d\n", __func__, skb_queue_len(&rtk_skb_mem_q)); + + return 0; + +} + +static void __exit rtw_mem_exit(void) +{ + if (skb_queue_len(&rtk_skb_mem_q)) { + printk("%s, rtk_skb_mem_q len : %d\n", __func__, skb_queue_len(&rtk_skb_mem_q)); + } + + skb_queue_purge(&rtk_skb_mem_q); + + printk("%s\n", __func__); +} + +module_init(rtw_mem_init); +module_exit(rtw_mem_exit); diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_mlme.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_mlme.c new file mode 100644 index 000000000..2e48bcf9c --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_mlme.c @@ -0,0 +1,4863 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_MLME_C_ + +#include + +extern void indicate_wx_scan_complete_event(_adapter *padapter); +extern u8 rtw_do_join(_adapter * padapter); + + +sint _rtw_init_mlme_priv (_adapter* padapter) +{ + sint i; + u8 *pbuf; + struct wlan_network *pnetwork; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + sint res = _SUCCESS; + +_func_enter_; + + // We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). + //_rtw_memset((u8 *)pmlmepriv, 0, sizeof(struct mlme_priv)); + + pmlmepriv->nic_hdl = (u8 *)padapter; + + pmlmepriv->pscanned = NULL; + pmlmepriv->fw_state = WIFI_STATION_STATE; // Must sync with rtw_wdev_alloc() + // wdev->iftype = NL80211_IFTYPE_STATION + pmlmepriv->cur_network.network.InfrastructureMode = Ndis802_11AutoUnknown; + pmlmepriv->scan_mode=SCAN_ACTIVE;// 1: active, 0: pasive. Maybe someday we should rename this varable to "active_mode" (Jeff) + + _rtw_spinlock_init(&(pmlmepriv->lock)); + _rtw_init_queue(&(pmlmepriv->free_bss_pool)); + _rtw_init_queue(&(pmlmepriv->scanned_queue)); + + set_scanned_network_val(pmlmepriv, 0); + + _rtw_memset(&pmlmepriv->assoc_ssid,0,sizeof(NDIS_802_11_SSID)); + + pbuf = rtw_zvmalloc(MAX_BSS_CNT * (sizeof(struct wlan_network))); + + if (pbuf == NULL){ + res=_FAIL; + goto exit; + } + pmlmepriv->free_bss_buf = pbuf; + + pnetwork = (struct wlan_network *)pbuf; + + for(i = 0; i < MAX_BSS_CNT; i++) + { + _rtw_init_listhead(&(pnetwork->list)); + + rtw_list_insert_tail(&(pnetwork->list), &(pmlmepriv->free_bss_pool.queue)); + + pnetwork++; + } + + //allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf + + rtw_clear_scan_deny(padapter); +#ifdef CONFIG_ARP_KEEP_ALIVE + pmlmepriv->bGetGateway = 0; +#endif + +#ifdef CONFIG_LAYER2_ROAMING + #define RTW_ROAM_SCAN_RESULT_EXP_MS 5*1000 + #define RTW_ROAM_RSSI_DIFF_TH 10 + #define RTW_ROAM_SCAN_INTERVAL_MS 10*1000 + + pmlmepriv->roam_flags = 0 + | RTW_ROAM_ON_EXPIRED + #ifdef CONFIG_LAYER2_ROAMING_RESUME + | RTW_ROAM_ON_RESUME + #endif + #ifdef CONFIG_LAYER2_ROAMING_ACTIVE + | RTW_ROAM_ACTIVE + #endif + ; + + pmlmepriv->roam_scanr_exp_ms = RTW_ROAM_SCAN_RESULT_EXP_MS; + pmlmepriv->roam_rssi_diff_th = RTW_ROAM_RSSI_DIFF_TH; + pmlmepriv->roam_scan_int_ms = RTW_ROAM_SCAN_INTERVAL_MS; +#endif /* CONFIG_LAYER2_ROAMING */ + + rtw_init_mlme_timer(padapter); + +exit: + +_func_exit_; + + return res; +} + +void rtw_mfree_mlme_priv_lock (struct mlme_priv *pmlmepriv); +void rtw_mfree_mlme_priv_lock (struct mlme_priv *pmlmepriv) +{ + _rtw_spinlock_free(&pmlmepriv->lock); + _rtw_spinlock_free(&(pmlmepriv->free_bss_pool.lock)); + _rtw_spinlock_free(&(pmlmepriv->scanned_queue.lock)); +} + +static void rtw_free_mlme_ie_data(u8 **ppie, u32 *plen) +{ + if(*ppie) + { + rtw_mfree(*ppie, *plen); + *plen = 0; + *ppie=NULL; + } +} + +void rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv) +{ +#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) + rtw_buf_free(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len); + rtw_buf_free(&pmlmepriv->assoc_rsp, &pmlmepriv->assoc_rsp_len); + rtw_free_mlme_ie_data(&pmlmepriv->wps_beacon_ie, &pmlmepriv->wps_beacon_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->wps_probe_req_ie, &pmlmepriv->wps_probe_req_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->wps_probe_resp_ie, &pmlmepriv->wps_probe_resp_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->wps_assoc_resp_ie, &pmlmepriv->wps_assoc_resp_ie_len); + + rtw_free_mlme_ie_data(&pmlmepriv->p2p_beacon_ie, &pmlmepriv->p2p_beacon_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->p2p_probe_req_ie, &pmlmepriv->p2p_probe_req_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->p2p_probe_resp_ie, &pmlmepriv->p2p_probe_resp_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->p2p_go_probe_resp_ie, &pmlmepriv->p2p_go_probe_resp_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->p2p_assoc_req_ie, &pmlmepriv->p2p_assoc_req_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->p2p_assoc_resp_ie, &pmlmepriv->p2p_assoc_resp_ie_len); +#endif + +#if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211) + rtw_free_mlme_ie_data(&pmlmepriv->wfd_beacon_ie, &pmlmepriv->wfd_beacon_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->wfd_probe_req_ie, &pmlmepriv->wfd_probe_req_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->wfd_probe_resp_ie, &pmlmepriv->wfd_probe_resp_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->wfd_go_probe_resp_ie, &pmlmepriv->wfd_go_probe_resp_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->wfd_assoc_req_ie, &pmlmepriv->wfd_assoc_req_ie_len); + rtw_free_mlme_ie_data(&pmlmepriv->wfd_assoc_resp_ie, &pmlmepriv->wfd_assoc_resp_ie_len); +#endif + +} + +#if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211) +int rtw_mlme_update_wfd_ie_data(struct mlme_priv *mlme, u8 type, u8 *ie, u32 ie_len) +{ + _adapter *adapter = mlme_to_adapter(mlme); + struct wifi_display_info *wfd_info = &adapter->wfd_info; + u8 clear = 0; + u8 **t_ie = NULL; + u32 *t_ie_len = NULL; + int ret = _FAIL; + + if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) + goto success; + + if (wfd_info->wfd_enable == _TRUE) + goto success; /* WFD IE is build by self */ + + if (!ie && !ie_len) { + clear = 1; + } else if (!ie || !ie_len) { + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" type:%u, ie:%p, ie_len:%u" + , FUNC_ADPT_ARG(adapter), type, ie, ie_len); + rtw_warn_on(1); + goto exit; + } + + switch (type) { + case MLME_BEACON_IE: + t_ie = &mlme->wfd_beacon_ie; + t_ie_len = &mlme->wfd_beacon_ie_len; + break; + case MLME_PROBE_REQ_IE: + t_ie = &mlme->wfd_probe_req_ie; + t_ie_len = &mlme->wfd_probe_req_ie_len; + break; + case MLME_PROBE_RESP_IE: + t_ie = &mlme->wfd_probe_resp_ie; + t_ie_len = &mlme->wfd_probe_resp_ie_len; + break; + case MLME_GO_PROBE_RESP_IE: + t_ie = &mlme->wfd_go_probe_resp_ie; + t_ie_len = &mlme->wfd_go_probe_resp_ie_len; + break; + case MLME_ASSOC_REQ_IE: + t_ie = &mlme->wfd_assoc_req_ie; + t_ie_len = &mlme->wfd_assoc_req_ie_len; + break; + case MLME_ASSOC_RESP_IE: + t_ie = &mlme->wfd_assoc_resp_ie; + t_ie_len = &mlme->wfd_assoc_resp_ie_len; + break; + default: + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" unsupported type:%u" + , FUNC_ADPT_ARG(adapter), type); + rtw_warn_on(1); + goto exit; + } + + if (*t_ie) { + u32 free_len = *t_ie_len; + *t_ie_len = 0; + rtw_mfree(*t_ie, free_len); + *t_ie = NULL; + } + + if (!clear) { + *t_ie = rtw_malloc(ie_len); + if (*t_ie == NULL) { + DBG_871X_LEVEL(_drv_err_, FUNC_ADPT_FMT" type:%u, rtw_malloc() fail\n" + , FUNC_ADPT_ARG(adapter), type); + goto exit; + } + _rtw_memcpy(*t_ie, ie, ie_len); + *t_ie_len = ie_len; + } + + if (*t_ie && *t_ie_len) { + u8 *attr_content; + u32 attr_contentlen = 0; + + attr_content = rtw_get_wfd_attr_content(*t_ie, *t_ie_len, WFD_ATTR_DEVICE_INFO, NULL, &attr_contentlen); + if (attr_content && attr_contentlen) { + if (RTW_GET_BE16(attr_content + 2) != wfd_info->rtsp_ctrlport) { + wfd_info->rtsp_ctrlport = RTW_GET_BE16(attr_content + 2); + DBG_871X(FUNC_ADPT_FMT" type:%u, RTSP CTRL port = %u\n" + , FUNC_ADPT_ARG(adapter), type, wfd_info->rtsp_ctrlport); + } + } + } + +success: + ret = _SUCCESS; + +exit: + return ret; +} +#endif /* defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211) */ + +void _rtw_free_mlme_priv (struct mlme_priv *pmlmepriv) +{ +_func_enter_; + if (NULL == pmlmepriv){ + rtw_warn_on(1); + goto exit; + } + rtw_free_mlme_priv_ie_data(pmlmepriv); + + if(pmlmepriv){ + rtw_mfree_mlme_priv_lock (pmlmepriv); + + if (pmlmepriv->free_bss_buf) { + rtw_vmfree(pmlmepriv->free_bss_buf, MAX_BSS_CNT * sizeof(struct wlan_network)); + } + } +exit: +_func_exit_; +} + +sint _rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork) +{ + _irqL irqL; + +_func_enter_; + + if (pnetwork == NULL) + goto exit; + + _enter_critical_bh(&queue->lock, &irqL); + + rtw_list_insert_tail(&pnetwork->list, &queue->queue); + + _exit_critical_bh(&queue->lock, &irqL); + +exit: + +_func_exit_; + + return _SUCCESS; +} + +/* +struct wlan_network *_rtw_dequeue_network(_queue *queue) +{ + _irqL irqL; + + struct wlan_network *pnetwork; + +_func_enter_; + + _enter_critical_bh(&queue->lock, &irqL); + + if (_rtw_queue_empty(queue) == _TRUE) + + pnetwork = NULL; + + else + { + pnetwork = LIST_CONTAINOR(get_next(&queue->queue), struct wlan_network, list); + + rtw_list_delete(&(pnetwork->list)); + } + + _exit_critical_bh(&queue->lock, &irqL); + +_func_exit_; + + return pnetwork; +} +*/ + +struct wlan_network *_rtw_alloc_network(struct mlme_priv *pmlmepriv )//(_queue *free_queue) +{ + _irqL irqL; + struct wlan_network *pnetwork; + _queue *free_queue = &pmlmepriv->free_bss_pool; + _list* plist = NULL; + +_func_enter_; + + _enter_critical_bh(&free_queue->lock, &irqL); + + if (_rtw_queue_empty(free_queue) == _TRUE) { + pnetwork=NULL; + goto exit; + } + plist = get_next(&(free_queue->queue)); + + pnetwork = LIST_CONTAINOR(plist , struct wlan_network, list); + + rtw_list_delete(&pnetwork->list); + + RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("_rtw_alloc_network: ptr=%p\n", plist)); + pnetwork->network_type = 0; + pnetwork->fixed = _FALSE; + pnetwork->last_scanned = rtw_get_current_time(); + pnetwork->aid=0; + pnetwork->join_res=0; + + pmlmepriv->num_of_scanned ++; + +exit: + _exit_critical_bh(&free_queue->lock, &irqL); + +_func_exit_; + + return pnetwork; +} + +void _rtw_free_network(struct mlme_priv *pmlmepriv ,struct wlan_network *pnetwork, u8 isfreeall) +{ + u32 delta_time; + u32 lifetime = SCANQUEUE_LIFETIME; + _irqL irqL; + _queue *free_queue = &(pmlmepriv->free_bss_pool); + +_func_enter_; + + if (pnetwork == NULL) + goto exit; + + if (pnetwork->fixed == _TRUE) + goto exit; + + if ( (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)==_TRUE ) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)==_TRUE ) ) + lifetime = 1; + + if(!isfreeall) + { + delta_time = (u32) rtw_get_passing_time_ms(pnetwork->last_scanned); + if(delta_time < lifetime)// unit:msec + goto exit; + } + + _enter_critical_bh(&free_queue->lock, &irqL); + + rtw_list_delete(&(pnetwork->list)); + + rtw_list_insert_tail(&(pnetwork->list),&(free_queue->queue)); + + pmlmepriv->num_of_scanned --; + + + //DBG_871X("_rtw_free_network:SSID=%s\n", pnetwork->network.Ssid.Ssid); + + _exit_critical_bh(&free_queue->lock, &irqL); + +exit: + +_func_exit_; + +} + +void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork) +{ + + _queue *free_queue = &(pmlmepriv->free_bss_pool); + +_func_enter_; + + if (pnetwork == NULL) + goto exit; + + if (pnetwork->fixed == _TRUE) + goto exit; + + //_enter_critical(&free_queue->lock, &irqL); + + rtw_list_delete(&(pnetwork->list)); + + rtw_list_insert_tail(&(pnetwork->list), get_list_head(free_queue)); + + pmlmepriv->num_of_scanned --; + + //_exit_critical(&free_queue->lock, &irqL); + +exit: + +_func_exit_; + +} + + +/* + return the wlan_network with the matching addr + + Shall be calle under atomic context... to avoid possible racing condition... +*/ +struct wlan_network *_rtw_find_network(_queue *scanned_queue, u8 *addr) +{ + + //_irqL irqL; + _list *phead, *plist; + struct wlan_network *pnetwork = NULL; + u8 zero_addr[ETH_ALEN] = {0,0,0,0,0,0}; + +_func_enter_; + + if(_rtw_memcmp(zero_addr, addr, ETH_ALEN)){ + pnetwork=NULL; + goto exit; + } + + //_enter_critical_bh(&scanned_queue->lock, &irqL); + + phead = get_list_head(scanned_queue); + plist = get_next(phead); + + while (plist != phead) + { + pnetwork = LIST_CONTAINOR(plist, struct wlan_network ,list); + + if (_rtw_memcmp(addr, pnetwork->network.MacAddress, ETH_ALEN) == _TRUE) + break; + + plist = get_next(plist); + } + + if(plist == phead) + pnetwork = NULL; + + //_exit_critical_bh(&scanned_queue->lock, &irqL); + +exit: + +_func_exit_; + + return pnetwork; + +} + + +void _rtw_free_network_queue(_adapter *padapter, u8 isfreeall) +{ + _irqL irqL; + _list *phead, *plist; + struct wlan_network *pnetwork; + struct mlme_priv* pmlmepriv = &padapter->mlmepriv; + _queue *scanned_queue = &pmlmepriv->scanned_queue; + +_func_enter_; + + + _enter_critical_bh(&scanned_queue->lock, &irqL); + + phead = get_list_head(scanned_queue); + plist = get_next(phead); + + while (rtw_end_of_queue_search(phead, plist) == _FALSE) + { + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + + plist = get_next(plist); + + _rtw_free_network(pmlmepriv,pnetwork, isfreeall); + + } + + _exit_critical_bh(&scanned_queue->lock, &irqL); + +_func_exit_; + +} + + + + +sint rtw_if_up(_adapter *padapter) { + + sint res; +_func_enter_; + + if (RTW_CANNOT_RUN(padapter) || + (check_fwstate(&padapter->mlmepriv, _FW_LINKED) == _FALSE)) { + RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_if_up:bDriverStopped(%s) OR bSurpriseRemoved(%s)" + , rtw_is_drv_stopped(padapter)?"True":"False" + , rtw_is_surprise_removed(padapter)?"True":"False")); + res=_FALSE; + } + else + res= _TRUE; + +_func_exit_; + return res; +} + + +void rtw_generate_random_ibss(u8* pibss) +{ + *((u32 *)(&pibss[2])) = rtw_random32(); + pibss[0] = 0x02; /* in ad-hoc mode local bit must set to 1 */ + pibss[1] = 0x11; + pibss[2] = 0x87; +} + +u8 *rtw_get_capability_from_ie(u8 *ie) +{ + return (ie + 8 + 2); +} + + +u16 rtw_get_capability(WLAN_BSSID_EX *bss) +{ + u16 val; +_func_enter_; + + _rtw_memcpy((u8 *)&val, rtw_get_capability_from_ie(bss->IEs), 2); + +_func_exit_; + return le16_to_cpu(val); +} + +u8 *rtw_get_timestampe_from_ie(u8 *ie) +{ + return (ie + 0); +} + +u8 *rtw_get_beacon_interval_from_ie(u8 *ie) +{ + return (ie + 8); +} + + +int rtw_init_mlme_priv (_adapter *padapter)//(struct mlme_priv *pmlmepriv) +{ + int res; +_func_enter_; + res = _rtw_init_mlme_priv(padapter);// (pmlmepriv); +_func_exit_; + return res; +} + +void rtw_free_mlme_priv (struct mlme_priv *pmlmepriv) +{ +_func_enter_; + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("rtw_free_mlme_priv\n")); + _rtw_free_mlme_priv (pmlmepriv); +_func_exit_; +} + +int rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork); +int rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork) +{ + int res; +_func_enter_; + res = _rtw_enqueue_network(queue, pnetwork); +_func_exit_; + return res; +} + +/* +static struct wlan_network *rtw_dequeue_network(_queue *queue) +{ + struct wlan_network *pnetwork; +_func_enter_; + pnetwork = _rtw_dequeue_network(queue); +_func_exit_; + return pnetwork; +} +*/ + +struct wlan_network *rtw_alloc_network(struct mlme_priv *pmlmepriv ); +struct wlan_network *rtw_alloc_network(struct mlme_priv *pmlmepriv )//(_queue *free_queue) +{ + struct wlan_network *pnetwork; +_func_enter_; + pnetwork = _rtw_alloc_network(pmlmepriv); +_func_exit_; + return pnetwork; +} + +void rtw_free_network(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork, u8 is_freeall); +void rtw_free_network(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork, u8 is_freeall)//(struct wlan_network *pnetwork, _queue *free_queue) +{ +_func_enter_; + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("rtw_free_network==> ssid = %s \n\n" , pnetwork->network.Ssid.Ssid)); + _rtw_free_network(pmlmepriv, pnetwork, is_freeall); +_func_exit_; +} + +void rtw_free_network_nolock(_adapter * padapter, struct wlan_network *pnetwork ); +void rtw_free_network_nolock(_adapter * padapter, struct wlan_network *pnetwork ) +{ +_func_enter_; + //RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("rtw_free_network==> ssid = %s \n\n" , pnetwork->network.Ssid.Ssid)); + _rtw_free_network_nolock(&(padapter->mlmepriv), pnetwork); +#ifdef CONFIG_IOCTL_CFG80211 + rtw_cfg80211_unlink_bss(padapter, pnetwork); +#endif //CONFIG_IOCTL_CFG80211 +_func_exit_; +} + + +void rtw_free_network_queue(_adapter* dev, u8 isfreeall) +{ +_func_enter_; + _rtw_free_network_queue(dev, isfreeall); +_func_exit_; +} + +/* + return the wlan_network with the matching addr + + Shall be calle under atomic context... to avoid possible racing condition... +*/ +struct wlan_network *rtw_find_network(_queue *scanned_queue, u8 *addr) +{ + struct wlan_network *pnetwork = _rtw_find_network(scanned_queue, addr); + + return pnetwork; +} + +int rtw_is_same_ibss(_adapter *adapter, struct wlan_network *pnetwork) +{ + int ret=_TRUE; + struct security_priv *psecuritypriv = &adapter->securitypriv; + + if ( (psecuritypriv->dot11PrivacyAlgrthm != _NO_PRIVACY_ ) && + ( pnetwork->network.Privacy == 0 ) ) + { + ret=_FALSE; + } + else if((psecuritypriv->dot11PrivacyAlgrthm == _NO_PRIVACY_ ) && + ( pnetwork->network.Privacy == 1 ) ) + { + ret=_FALSE; + } + else + { + ret=_TRUE; + } + + return ret; + +} + +inline int is_same_ess(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b) +{ + //RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("(%s,%d)(%s,%d)\n", + // a->Ssid.Ssid,a->Ssid.SsidLength,b->Ssid.Ssid,b->Ssid.SsidLength)); + return (a->Ssid.SsidLength == b->Ssid.SsidLength) + && _rtw_memcmp(a->Ssid.Ssid, b->Ssid.Ssid, a->Ssid.SsidLength)==_TRUE; +} + +int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst, u8 feature) +{ + u16 s_cap, d_cap; + +_func_enter_; + + if(rtw_bug_check(dst, src, &s_cap, &d_cap)==_FALSE) + return _FALSE; + + _rtw_memcpy((u8 *)&s_cap, rtw_get_capability_from_ie(src->IEs), 2); + _rtw_memcpy((u8 *)&d_cap, rtw_get_capability_from_ie(dst->IEs), 2); + + + s_cap = le16_to_cpu(s_cap); + d_cap = le16_to_cpu(d_cap); + +_func_exit_; + +#ifdef CONFIG_P2P + if ((feature == 1) && // 1: P2P supported + (_rtw_memcmp(src->MacAddress, dst->MacAddress, ETH_ALEN) == _TRUE) + ) { + return _TRUE; + } +#endif + + return ((src->Ssid.SsidLength == dst->Ssid.SsidLength) && + // (src->Configuration.DSConfig == dst->Configuration.DSConfig) && + ( (_rtw_memcmp(src->MacAddress, dst->MacAddress, ETH_ALEN)) == _TRUE) && + ( (_rtw_memcmp(src->Ssid.Ssid, dst->Ssid.Ssid, src->Ssid.SsidLength)) == _TRUE) && + ((s_cap & WLAN_CAPABILITY_IBSS) == + (d_cap & WLAN_CAPABILITY_IBSS)) && + ((s_cap & WLAN_CAPABILITY_BSS) == + (d_cap & WLAN_CAPABILITY_BSS))); + +} + +struct wlan_network *_rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network) +{ + _list *phead, *plist; + struct wlan_network *found = NULL; + + phead = get_list_head(scanned_queue); + plist = get_next(phead); + + while (plist != phead) { + found = LIST_CONTAINOR(plist, struct wlan_network ,list); + + if (is_same_network(&network->network, &found->network,0)) + break; + + plist = get_next(plist); + } + + if(plist == phead) + found = NULL; +exit: + return found; +} + +struct wlan_network *rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network) +{ + _irqL irqL; + struct wlan_network *found = NULL; + + if (scanned_queue == NULL || network == NULL) + goto exit; + + _enter_critical_bh(&scanned_queue->lock, &irqL); + found = _rtw_find_same_network(scanned_queue, network); + _exit_critical_bh(&scanned_queue->lock, &irqL); + +exit: + return found; +} + +struct wlan_network * rtw_get_oldest_wlan_network(_queue *scanned_queue) +{ + _list *plist, *phead; + + + struct wlan_network *pwlan = NULL; + struct wlan_network *oldest = NULL; +_func_enter_; + phead = get_list_head(scanned_queue); + + plist = get_next(phead); + + while(1) + { + + if (rtw_end_of_queue_search(phead,plist)== _TRUE) + break; + + pwlan= LIST_CONTAINOR(plist, struct wlan_network, list); + + if(pwlan->fixed!=_TRUE) + { + if (oldest == NULL ||time_after(oldest->last_scanned, pwlan->last_scanned)) + oldest = pwlan; + } + + plist = get_next(plist); + } +_func_exit_; + return oldest; + +} + +void update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src, + _adapter * padapter, bool update_ie) +{ + u8 ss_ori = dst->PhyInfo.SignalStrength; + u8 sq_ori = dst->PhyInfo.SignalQuality; + long rssi_ori = dst->Rssi; + + u8 ss_smp = src->PhyInfo.SignalStrength; + u8 sq_smp = src->PhyInfo.SignalQuality; + long rssi_smp = src->Rssi; + + u8 ss_final; + u8 sq_final; + long rssi_final; + +_func_enter_; + +#ifdef CONFIG_ANTENNA_DIVERSITY + rtw_hal_antdiv_rssi_compared(padapter, dst, src); //this will update src.Rssi, need consider again +#endif + + #if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) && 1 + if(strcmp(dst->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) { + DBG_871X(FUNC_ADPT_FMT" %s("MAC_FMT", ch%u) ss_ori:%3u, sq_ori:%3u, rssi_ori:%3ld, ss_smp:%3u, sq_smp:%3u, rssi_smp:%3ld\n" + , FUNC_ADPT_ARG(padapter) + , src->Ssid.Ssid, MAC_ARG(src->MacAddress), src->Configuration.DSConfig + ,ss_ori, sq_ori, rssi_ori + ,ss_smp, sq_smp, rssi_smp + ); + } + #endif + + /* The rule below is 1/5 for sample value, 4/5 for history value */ + if (check_fwstate(&padapter->mlmepriv, _FW_LINKED) && is_same_network(&(padapter->mlmepriv.cur_network.network), src, 0)) { + /* Take the recvpriv's value for the connected AP*/ + ss_final = padapter->recvpriv.signal_strength; + sq_final = padapter->recvpriv.signal_qual; + /* the rssi value here is undecorated, and will be used for antenna diversity */ + if(sq_smp != 101) /* from the right channel */ + rssi_final = (src->Rssi+dst->Rssi*4)/5; + else + rssi_final = rssi_ori; + } + else { + if(sq_smp != 101) { /* from the right channel */ + ss_final = ((u32)(src->PhyInfo.SignalStrength)+(u32)(dst->PhyInfo.SignalStrength)*4)/5; + sq_final = ((u32)(src->PhyInfo.SignalQuality)+(u32)(dst->PhyInfo.SignalQuality)*4)/5; + rssi_final = (src->Rssi+dst->Rssi*4)/5; + } else { + /* bss info not receving from the right channel, use the original RX signal infos */ + ss_final = dst->PhyInfo.SignalStrength; + sq_final = dst->PhyInfo.SignalQuality; + rssi_final = dst->Rssi; + } + + } + + if (update_ie) { + dst->Reserved[0] = src->Reserved[0]; + dst->Reserved[1] = src->Reserved[1]; + _rtw_memcpy((u8 *)dst, (u8 *)src, get_WLAN_BSSID_EX_sz(src)); + } + + dst->PhyInfo.SignalStrength = ss_final; + dst->PhyInfo.SignalQuality = sq_final; + dst->Rssi = rssi_final; + + #if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) && 1 + if(strcmp(dst->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) { + DBG_871X(FUNC_ADPT_FMT" %s("MAC_FMT"), SignalStrength:%u, SignalQuality:%u, RawRSSI:%ld\n" + , FUNC_ADPT_ARG(padapter) + , dst->Ssid.Ssid, MAC_ARG(dst->MacAddress), dst->PhyInfo.SignalStrength, dst->PhyInfo.SignalQuality, dst->Rssi); + } + #endif + +#if 0 // old codes, may be useful one day... +// DBG_871X("update_network: rssi=0x%lx dst->Rssi=%d ,dst->Rssi=0x%lx , src->Rssi=0x%lx",(dst->Rssi+src->Rssi)/2,dst->Rssi,dst->Rssi,src->Rssi); + if (check_fwstate(&padapter->mlmepriv, _FW_LINKED) && is_same_network(&(padapter->mlmepriv.cur_network.network), src)) + { + + //DBG_871X("b:ssid=%s update_network: src->rssi=0x%d padapter->recvpriv.ui_rssi=%d\n",src->Ssid.Ssid,src->Rssi,padapter->recvpriv.signal); + if(padapter->recvpriv.signal_qual_data.total_num++ >= PHY_LINKQUALITY_SLID_WIN_MAX) + { + padapter->recvpriv.signal_qual_data.total_num = PHY_LINKQUALITY_SLID_WIN_MAX; + last_evm = padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index]; + padapter->recvpriv.signal_qual_data.total_val -= last_evm; + } + padapter->recvpriv.signal_qual_data.total_val += query_rx_pwr_percentage(src->Rssi); + + padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = query_rx_pwr_percentage(src->Rssi); + if(padapter->recvpriv.signal_qual_data.index >= PHY_LINKQUALITY_SLID_WIN_MAX) + padapter->recvpriv.signal_qual_data.index = 0; + + //DBG_871X("Total SQ=%d pattrib->signal_qual= %d\n", padapter->recvpriv.signal_qual_data.total_val, src->Rssi); + + // <1> Showed on UI for user,in percentage. + tmpVal = padapter->recvpriv.signal_qual_data.total_val/padapter->recvpriv.signal_qual_data.total_num; + padapter->recvpriv.signal=(u8)tmpVal;//Link quality + + src->Rssi= translate_percentage_to_dbm(padapter->recvpriv.signal) ; + } + else{ +// DBG_871X("ELSE:ssid=%s update_network: src->rssi=0x%d dst->rssi=%d\n",src->Ssid.Ssid,src->Rssi,dst->Rssi); + src->Rssi=(src->Rssi +dst->Rssi)/2;//dBM + } + +// DBG_871X("a:update_network: src->rssi=0x%d padapter->recvpriv.ui_rssi=%d\n",src->Rssi,padapter->recvpriv.signal); + +#endif + +_func_exit_; +} + +static void update_current_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork) +{ + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + +_func_enter_; + + rtw_bug_check(&(pmlmepriv->cur_network.network), + &(pmlmepriv->cur_network.network), + &(pmlmepriv->cur_network.network), + &(pmlmepriv->cur_network.network)); + + if ( (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) && (is_same_network(&(pmlmepriv->cur_network.network), pnetwork, 0))) + { + //RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,"Same Network\n"); + + //if(pmlmepriv->cur_network.network.IELength<= pnetwork->IELength) + { + update_network(&(pmlmepriv->cur_network.network), pnetwork,adapter, _TRUE); + rtw_update_protection(adapter, (pmlmepriv->cur_network.network.IEs) + sizeof (NDIS_802_11_FIXED_IEs), + pmlmepriv->cur_network.network.IELength); + } + } + +_func_exit_; + +} + + +/* + +Caller must hold pmlmepriv->lock first. + + +*/ +void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) +{ + _irqL irqL; + _list *plist, *phead; + ULONG bssid_ex_sz; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo= &(adapter->wdinfo); +#endif // CONFIG_P2P + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + struct wlan_network *oldest = NULL; + int target_find = 0; + u8 feature = 0; + +_func_enter_; + + _enter_critical_bh(&queue->lock, &irqL); + phead = get_list_head(queue); + plist = get_next(phead); + +#ifdef CONFIG_P2P + if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + feature = 1; // p2p enable +#endif + + while(1) + { + if (rtw_end_of_queue_search(phead,plist)== _TRUE) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + + rtw_bug_check(pnetwork, pnetwork, pnetwork, pnetwork); + +#ifdef CONFIG_P2P + if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && + (_rtw_memcmp(pnetwork->network.MacAddress, target->MacAddress, ETH_ALEN) == _TRUE)) + { + target_find = 1; + break; + } +#endif + + if (is_same_network(&(pnetwork->network), target, feature)) + { + target_find = 1; + break; + } + + if (rtw_roam_flags(adapter)) { + /* TODO: don't select netowrk in the same ess as oldest if it's new enough*/ + } + + if (oldest == NULL || time_after(oldest->last_scanned, pnetwork->last_scanned)) + oldest = pnetwork; + + plist = get_next(plist); + + } + + + /* If we didn't find a match, then get a new network slot to initialize + * with this beacon's information */ + //if (rtw_end_of_queue_search(phead,plist)== _TRUE) { + if (!target_find) { + if (_rtw_queue_empty(&(pmlmepriv->free_bss_pool)) == _TRUE) { + /* If there are no more slots, expire the oldest */ + //list_del_init(&oldest->list); + pnetwork = oldest; + if(pnetwork==NULL){ + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n\n\nsomething wrong here\n\n\n")); + goto exit; + } +#ifdef CONFIG_ANTENNA_DIVERSITY + rtw_hal_get_odm_var(adapter, HAL_ODM_ANTDIV_SELECT, &(target->PhyInfo.Optimum_antenna), NULL); +#endif + _rtw_memcpy(&(pnetwork->network), target, get_WLAN_BSSID_EX_sz(target)); + //pnetwork->last_scanned = rtw_get_current_time(); + // variable initialize + pnetwork->fixed = _FALSE; + pnetwork->last_scanned = rtw_get_current_time(); + + pnetwork->network_type = 0; + pnetwork->aid=0; + pnetwork->join_res=0; + + /* bss info not receving from the right channel */ + if (pnetwork->network.PhyInfo.SignalQuality == 101) + pnetwork->network.PhyInfo.SignalQuality = 0; + } + else { + /* Otherwise just pull from the free list */ + + pnetwork = rtw_alloc_network(pmlmepriv); // will update scan_time + + if(pnetwork==NULL){ + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n\n\nsomething wrong here\n\n\n")); + goto exit; + } + + bssid_ex_sz = get_WLAN_BSSID_EX_sz(target); + target->Length = bssid_ex_sz; +#ifdef CONFIG_ANTENNA_DIVERSITY + rtw_hal_get_odm_var(adapter, HAL_ODM_ANTDIV_SELECT, &(target->PhyInfo.Optimum_antenna), NULL); +#endif + _rtw_memcpy(&(pnetwork->network), target, bssid_ex_sz ); + + pnetwork->last_scanned = rtw_get_current_time(); + + /* bss info not receving from the right channel */ + if (pnetwork->network.PhyInfo.SignalQuality == 101) + pnetwork->network.PhyInfo.SignalQuality = 0; + + rtw_list_insert_tail(&(pnetwork->list),&(queue->queue)); + + } + } + else { + /* we have an entry and we are going to update it. But this entry may + * be already expired. In this case we do the same as we found a new + * net and call the new_net handler + */ + bool update_ie = _TRUE; + + pnetwork->last_scanned = rtw_get_current_time(); + + //target.Reserved[0]==1, means that scaned network is a bcn frame. + if((pnetwork->network.IELength>target->IELength) && (target->Reserved[0]==1)) + update_ie = _FALSE; + + // probe resp(3) > beacon(1) > probe req(2) + if ((target->Reserved[0] != 2) && + (target->Reserved[0] >= pnetwork->network.Reserved[0]) + ) { + update_ie = _TRUE; + } + else { + update_ie = _FALSE; + } + + update_network(&(pnetwork->network), target,adapter, update_ie); + } + +exit: + _exit_critical_bh(&queue->lock, &irqL); + +_func_exit_; +} + +void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork); +void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork) +{ + _irqL irqL; + struct mlme_priv *pmlmepriv = &(((_adapter *)adapter)->mlmepriv); + //_queue *queue = &(pmlmepriv->scanned_queue); + +_func_enter_; + + //_enter_critical_bh(&queue->lock, &irqL); + + #if defined(CONFIG_P2P) && defined(CONFIG_P2P_REMOVE_GROUP_INFO) + if (adapter->registrypriv.wifi_spec == 0) + rtw_bss_ex_del_p2p_attr(pnetwork, P2P_ATTR_GROUP_INFO); + #endif + + if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) + rtw_bss_ex_del_wfd_ie(pnetwork); + + update_current_network(adapter, pnetwork); + + rtw_update_scanned_network(adapter, pnetwork); + + //_exit_critical_bh(&queue->lock, &irqL); + +_func_exit_; +} + +//select the desired network based on the capability of the (i)bss. +// check items: (1) security +// (2) network_type +// (3) WMM +// (4) HT +// (5) others +int rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork); +int rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork) +{ + struct security_priv *psecuritypriv = &adapter->securitypriv; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + u32 desired_encmode; + u32 privacy; + + //u8 wps_ie[512]; + uint wps_ielen; + + int bselected = _TRUE; + + desired_encmode = psecuritypriv->ndisencryptstatus; + privacy = pnetwork->network.Privacy; + + if(check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) + { + if(rtw_get_wps_ie(pnetwork->network.IEs+_FIXED_IE_LENGTH_, pnetwork->network.IELength-_FIXED_IE_LENGTH_, NULL, &wps_ielen)!=NULL) + { + return _TRUE; + } + else + { + return _FALSE; + } + } + if (adapter->registrypriv.wifi_spec == 1) //for correct flow of 8021X to do.... + { + u8 *p=NULL; + uint ie_len=0; + + if ((desired_encmode == Ndis802_11EncryptionDisabled) && (privacy != 0)) + bselected = _FALSE; + + if ( psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPA2PSK) { + p = rtw_get_ie(pnetwork->network.IEs + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, (pnetwork->network.IELength - _BEACON_IE_OFFSET_)); + if (p && ie_len>0) { + bselected = _TRUE; + } else { + bselected = _FALSE; + } + } + } + + + if ((desired_encmode != Ndis802_11EncryptionDisabled) && (privacy == 0)) { + DBG_871X("desired_encmode: %d, privacy: %d\n", desired_encmode, privacy); + bselected = _FALSE; + } + + if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) + { + if(pnetwork->network.InfrastructureMode != pmlmepriv->cur_network.network.InfrastructureMode) + bselected = _FALSE; + } + + + return bselected; +} + +/* TODO: Perry : For Power Management */ +void rtw_atimdone_event_callback(_adapter *adapter , u8 *pbuf) +{ + +_func_enter_; + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("receive atimdone_evet\n")); +_func_exit_; + return; +} + + +void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf) +{ + _irqL irqL; + u32 len; + WLAN_BSSID_EX *pnetwork; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + +_func_enter_; + + pnetwork = (WLAN_BSSID_EX *)pbuf; + + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_survey_event_callback, ssid=%s\n", pnetwork->Ssid.Ssid)); + +#ifdef CONFIG_RTL8712 + //endian_convert + pnetwork->Length = le32_to_cpu(pnetwork->Length); + pnetwork->Ssid.SsidLength = le32_to_cpu(pnetwork->Ssid.SsidLength); + pnetwork->Privacy =le32_to_cpu( pnetwork->Privacy); + pnetwork->Rssi = le32_to_cpu(pnetwork->Rssi); + pnetwork->NetworkTypeInUse =le32_to_cpu(pnetwork->NetworkTypeInUse); + pnetwork->Configuration.ATIMWindow = le32_to_cpu(pnetwork->Configuration.ATIMWindow); + pnetwork->Configuration.BeaconPeriod = le32_to_cpu(pnetwork->Configuration.BeaconPeriod); + pnetwork->Configuration.DSConfig =le32_to_cpu(pnetwork->Configuration.DSConfig); + pnetwork->Configuration.FHConfig.DwellTime=le32_to_cpu(pnetwork->Configuration.FHConfig.DwellTime); + pnetwork->Configuration.FHConfig.HopPattern=le32_to_cpu(pnetwork->Configuration.FHConfig.HopPattern); + pnetwork->Configuration.FHConfig.HopSet=le32_to_cpu(pnetwork->Configuration.FHConfig.HopSet); + pnetwork->Configuration.FHConfig.Length=le32_to_cpu(pnetwork->Configuration.FHConfig.Length); + pnetwork->Configuration.Length = le32_to_cpu(pnetwork->Configuration.Length); + pnetwork->InfrastructureMode = le32_to_cpu(pnetwork->InfrastructureMode); + pnetwork->IELength = le32_to_cpu(pnetwork->IELength); +#endif + + len = get_WLAN_BSSID_EX_sz(pnetwork); + if(len > (sizeof(WLAN_BSSID_EX))) + { + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n ****rtw_survey_event_callback: return a wrong bss ***\n")); + return; + } + + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + // update IBSS_network 's timestamp + if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) == _TRUE) + { + //RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,"rtw_survey_event_callback : WIFI_ADHOC_MASTER_STATE \n\n"); + if(_rtw_memcmp(&(pmlmepriv->cur_network.network.MacAddress), pnetwork->MacAddress, ETH_ALEN)) + { + struct wlan_network* ibss_wlan = NULL; + _irqL irqL; + + _rtw_memcpy(pmlmepriv->cur_network.network.IEs, pnetwork->IEs, 8); + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + ibss_wlan = rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->MacAddress); + if(ibss_wlan) + { + _rtw_memcpy(ibss_wlan->network.IEs , pnetwork->IEs, 8); + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + goto exit; + } + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + } + } + + // lock pmlmepriv->lock when you accessing network_q + if ((check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) == _FALSE) + { + if( pnetwork->Ssid.Ssid[0] == 0 ) + { + pnetwork->Ssid.SsidLength = 0; + } + rtw_add_network(adapter, pnetwork); + } + +exit: + + _exit_critical_bh(&pmlmepriv->lock, &irqL); + +_func_exit_; + + return; +} + +void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf) +{ + _irqL irqL; + u8 timer_cancelled; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + +#ifdef CONFIG_MLME_EXT + mlmeext_surveydone_event_callback(adapter); +#endif + +_func_enter_; + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + if (pmlmepriv->wps_probe_req_ie) { + u32 free_len = pmlmepriv->wps_probe_req_ie_len; + pmlmepriv->wps_probe_req_ie_len = 0; + rtw_mfree(pmlmepriv->wps_probe_req_ie, free_len); + pmlmepriv->wps_probe_req_ie = NULL; + } + + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_surveydone_event_callback: fw_state:%x\n\n", get_fwstate(pmlmepriv))); + + if (check_fwstate(pmlmepriv,_FW_UNDER_SURVEY) == _FALSE) { + DBG_871X(FUNC_ADPT_FMT" fw_state:0x%x\n", FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv)); + //rtw_warn_on(1); + } + + _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY); + _exit_critical_bh(&pmlmepriv->lock, &irqL); + + _cancel_timer(&pmlmepriv->scan_to_timer, &timer_cancelled); + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS + rtw_set_signal_stat_timer(&adapter->recvpriv); + #endif + + if(pmlmepriv->to_join == _TRUE) + { + if((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)==_TRUE) ) + { + if(check_fwstate(pmlmepriv, _FW_LINKED)==_FALSE) + { + set_fwstate(pmlmepriv, _FW_UNDER_LINKING); + + if(rtw_select_and_join_from_scanned_queue(pmlmepriv)==_SUCCESS) + { + _set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT); + } + else + { + WLAN_BSSID_EX *pdev_network = &(adapter->registrypriv.dev_network); + u8 *pibss = adapter->registrypriv.dev_network.MacAddress; + + //pmlmepriv->fw_state ^= _FW_UNDER_SURVEY;//because don't set assoc_timer + _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY); + + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("switching to adhoc master\n")); + + _rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID)); + _rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID)); + + rtw_update_registrypriv_dev_network(adapter); + rtw_generate_random_ibss(pibss); + + + pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE; + + if (rtw_create_ibss_cmd(adapter, 0) != _SUCCESS) + RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("Error=>rtw_create_ibss_cmd status FAIL\n")); + + pmlmepriv->to_join = _FALSE; + } + } + } + else + { + int s_ret; + set_fwstate(pmlmepriv, _FW_UNDER_LINKING); + pmlmepriv->to_join = _FALSE; + if(_SUCCESS == (s_ret=rtw_select_and_join_from_scanned_queue(pmlmepriv))) + { + _set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT); + } + else if(s_ret == 2)//there is no need to wait for join + { + _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); + rtw_indicate_connect(adapter); + } + else + { + DBG_871X("try_to_join, but select scanning queue fail, to_roam:%d\n", rtw_to_roam(adapter)); + + if (rtw_to_roam(adapter) != 0) { + if(rtw_dec_to_roam(adapter) == 0 + || _SUCCESS != rtw_sitesurvey_cmd(adapter, &pmlmepriv->assoc_ssid, 1, NULL, 0) + ) { + rtw_set_to_roam(adapter, 0); +#ifdef CONFIG_INTEL_WIDI + if(adapter->mlmepriv.widi_state == INTEL_WIDI_STATE_ROAMING) + { + _rtw_memset(pmlmepriv->sa_ext, 0x00, L2SDTA_SERVICE_VE_LEN); + intel_widi_wk_cmd(adapter, INTEL_WIDI_LISTEN_WK, NULL, 0); + DBG_871X("change to widi listen\n"); + } +#endif // CONFIG_INTEL_WIDI + rtw_free_assoc_resources(adapter, 1); + rtw_indicate_disconnect(adapter, 0, _FALSE); + } else { + pmlmepriv->to_join = _TRUE; + } + } + else + { + rtw_indicate_disconnect(adapter, 0, _FALSE); + } + _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); + } + } + } else { + if (rtw_chk_roam_flags(adapter, RTW_ROAM_ACTIVE)) { + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) + && check_fwstate(pmlmepriv, _FW_LINKED)) + { + if (rtw_select_roaming_candidate(pmlmepriv) == _SUCCESS) { + receive_disconnect(adapter, pmlmepriv->cur_network.network.MacAddress + , WLAN_REASON_ACTIVE_ROAM, _FALSE); + } + } + } + } + + //DBG_871X("scan complete in %dms\n",rtw_get_passing_time_ms(pmlmepriv->scan_start_time)); + + _exit_critical_bh(&pmlmepriv->lock, &irqL); + +#ifdef CONFIG_P2P_PS + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { + p2p_ps_wk_cmd(adapter, P2P_PS_SCAN_DONE, 0); + } +#endif // CONFIG_P2P_PS + + rtw_os_xmit_schedule(adapter); +#ifdef CONFIG_CONCURRENT_MODE + rtw_os_xmit_schedule(adapter->pbuddy_adapter); +#endif + +#ifdef CONFIG_DRVEXT_MODULE_WSC + drvext_surveydone_callback(&adapter->drvextpriv); +#endif + +#ifdef DBG_CONFIG_ERROR_DETECT + { + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + if(pmlmeext->sitesurvey_res.bss_cnt == 0){ + //rtw_hal_sreset_reset(adapter); + } + } +#endif + +#ifdef CONFIG_IOCTL_CFG80211 + rtw_cfg80211_surveydone_event_callback(adapter); +#endif //CONFIG_IOCTL_CFG80211 + + rtw_indicate_scan_done(adapter, _FALSE); + +#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_IOCTL_CFG80211) + if (adapter->pbuddy_adapter) { + _adapter *buddy_adapter = adapter->pbuddy_adapter; + struct mlme_priv *buddy_mlme = &(buddy_adapter->mlmepriv); + struct rtw_wdev_priv *buddy_wdev_priv = adapter_wdev_data(buddy_adapter); + bool indicate_buddy_scan = _FALSE; + + _enter_critical_bh(&buddy_wdev_priv->scan_req_lock, &irqL); + if (buddy_wdev_priv->scan_request && buddy_mlme->scanning_via_buddy_intf == _TRUE) { + buddy_mlme->scanning_via_buddy_intf = _FALSE; + clr_fwstate(buddy_mlme, _FW_UNDER_SURVEY); + indicate_buddy_scan = _TRUE; + } + _exit_critical_bh(&buddy_wdev_priv->scan_req_lock, &irqL); + + if (indicate_buddy_scan == _TRUE) { + #ifdef CONFIG_IOCTL_CFG80211 + rtw_cfg80211_surveydone_event_callback(buddy_adapter); + #endif + rtw_indicate_scan_done(buddy_adapter, _FALSE); + } + } +#endif /* CONFIG_CONCURRENT_MODE */ + +_func_exit_; + +} + +void rtw_dummy_event_callback(_adapter *adapter , u8 *pbuf) +{ + +} + +void rtw_fwdbg_event_callback(_adapter *adapter , u8 *pbuf) +{ + +} + +static void free_scanqueue(struct mlme_priv *pmlmepriv) +{ + _irqL irqL, irqL0; + _queue *free_queue = &pmlmepriv->free_bss_pool; + _queue *scan_queue = &pmlmepriv->scanned_queue; + _list *plist, *phead, *ptemp; + +_func_enter_; + + RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, ("+free_scanqueue\n")); + _enter_critical_bh(&scan_queue->lock, &irqL0); + _enter_critical_bh(&free_queue->lock, &irqL); + + phead = get_list_head(scan_queue); + plist = get_next(phead); + + while (plist != phead) + { + ptemp = get_next(plist); + rtw_list_delete(plist); + rtw_list_insert_tail(plist, &free_queue->queue); + plist =ptemp; + pmlmepriv->num_of_scanned --; + } + + _exit_critical_bh(&free_queue->lock, &irqL); + _exit_critical_bh(&scan_queue->lock, &irqL0); + +_func_exit_; +} + +void rtw_reset_rx_info(struct debug_priv *pdbgpriv){ + pdbgpriv->dbg_rx_ampdu_drop_count = 0; + pdbgpriv->dbg_rx_ampdu_forced_indicate_count = 0; + pdbgpriv->dbg_rx_ampdu_loss_count = 0; + pdbgpriv->dbg_rx_dup_mgt_frame_drop_count = 0; + pdbgpriv->dbg_rx_ampdu_window_shift_cnt = 0; +} + +/* +*rtw_free_assoc_resources: the caller has to lock pmlmepriv->lock +*/ +void rtw_free_assoc_resources(_adapter *adapter, int lock_scanned_queue) +{ + _irqL irqL; + struct wlan_network* pwlan = NULL; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct sta_priv *pstapriv = &adapter->stapriv; + struct wlan_network *tgt_network = &pmlmepriv->cur_network; + struct dvobj_priv *psdpriv = adapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + + +#ifdef CONFIG_TDLS + struct tdls_info *ptdlsinfo = &adapter->tdlsinfo; +#endif //CONFIG_TDLS +_func_enter_; + + RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, ("+rtw_free_assoc_resources\n")); + RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("tgt_network->network.MacAddress="MAC_FMT" ssid=%s\n", + MAC_ARG(tgt_network->network.MacAddress), tgt_network->network.Ssid.Ssid)); + + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { + struct sta_info* psta; + + psta = rtw_get_stainfo(&adapter->stapriv, tgt_network->network.MacAddress); + +#ifdef CONFIG_TDLS + if (ptdlsinfo->link_established == _TRUE) { + rtw_tdls_cmd(adapter, NULL, TDLS_RS_RCR); + rtw_reset_tdls_info(adapter); + rtw_free_all_stainfo(adapter); + //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + } + else +#endif //CONFIG_TDLS + { + //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + rtw_free_stainfo(adapter, psta); + } + + //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + + } + + if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE)) { + struct sta_info* psta; + + rtw_free_all_stainfo(adapter); + + psta = rtw_get_bcmc_stainfo(adapter); + //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + rtw_free_stainfo(adapter, psta); + //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + + rtw_init_bcmc_stainfo(adapter); + } + + if(lock_scanned_queue) + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + pwlan = _rtw_find_same_network(&pmlmepriv->scanned_queue, tgt_network); + if ((pwlan) && (!check_fwstate(pmlmepriv, WIFI_UNDER_WPS))) { + + pwlan->fixed = _FALSE; + + DBG_871X("free disconnecting network of scanned_queue\n"); + + rtw_free_network_nolock(adapter, pwlan); +#ifdef CONFIG_P2P + if(!rtw_p2p_chk_state(&adapter->wdinfo, P2P_STATE_NONE)) + { + rtw_set_scan_deny(adapter, 2000); + //rtw_clear_scan_deny(adapter); + } +#endif //CONFIG_P2P + } else { + if (pwlan == NULL) + DBG_871X("free disconnecting network of scanned_queue failed due to pwlan== NULL\n\n"); + if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) + DBG_871X("donot free disconnecting network of scanned_queue when WIFI_UNDER_WPS\n\n"); + + } + + + if((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) && (adapter->stapriv.asoc_sta_count== 1)) + /*||check_fwstate(pmlmepriv, WIFI_STATION_STATE)*/) + { + if (pwlan) + rtw_free_network_nolock(adapter, pwlan); + } + + if(lock_scanned_queue) + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + adapter->securitypriv.key_mask = 0; + + rtw_reset_rx_info(pdbgpriv); + +_func_exit_; + +} + +/* +*rtw_indicate_connect: the caller has to lock pmlmepriv->lock +*/ +void rtw_indicate_connect(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + +_func_enter_; + + RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("+rtw_indicate_connect\n")); + + pmlmepriv->to_join = _FALSE; + + if(!check_fwstate(&padapter->mlmepriv, _FW_LINKED)) + { + + set_fwstate(pmlmepriv, _FW_LINKED); + + rtw_led_control(padapter, LED_CTL_LINK); + + +#ifdef CONFIG_DRVEXT_MODULE + if(padapter->drvextpriv.enable_wpa) + { + indicate_l2_connect(padapter); + } + else +#endif + { + rtw_os_indicate_connect(padapter); + } + + } + + rtw_set_to_roam(padapter, 0); +#ifdef CONFIG_INTEL_WIDI + if(padapter->mlmepriv.widi_state == INTEL_WIDI_STATE_ROAMING) + { + _rtw_memset(pmlmepriv->sa_ext, 0x00, L2SDTA_SERVICE_VE_LEN); + intel_widi_wk_cmd(padapter, INTEL_WIDI_LISTEN_WK, NULL, 0); + DBG_871X("change to widi listen\n"); + } +#endif // CONFIG_INTEL_WIDI + + rtw_set_scan_deny(padapter, 3000); + + RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("-rtw_indicate_connect: fw_state=0x%08x\n", get_fwstate(pmlmepriv))); + +_func_exit_; + +} + + +/* +*rtw_indicate_disconnect: the caller has to lock pmlmepriv->lock +*/ +void rtw_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generated) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 *wps_ie=NULL; + uint wpsie_len=0; + +_func_enter_; + + RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("+rtw_indicate_disconnect\n")); + + _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING|WIFI_UNDER_WPS); + + // force to clear cur_network_scanned's SELECTED REGISTRAR + if (pmlmepriv->cur_network_scanned) { + WLAN_BSSID_EX *current_joined_bss = &(pmlmepriv->cur_network_scanned->network); + if (current_joined_bss) { + wps_ie=rtw_get_wps_ie(current_joined_bss->IEs +_FIXED_IE_LENGTH_, + current_joined_bss->IELength-_FIXED_IE_LENGTH_, NULL, &wpsie_len); + if (wps_ie && wpsie_len>0) { + u8 *attr = NULL; + u32 attr_len; + attr=rtw_get_wps_attr(wps_ie, wpsie_len, WPS_ATTR_SELECTED_REGISTRAR, + NULL, &attr_len); + if (attr) + *(attr + 4) = 0; + } + } + } + //DBG_871X("clear wps when %s\n", __func__); + + if(rtw_to_roam(padapter) > 0) + _clr_fwstate_(pmlmepriv, _FW_LINKED); + +#ifdef CONFIG_WAPI_SUPPORT + psta = rtw_get_stainfo(pstapriv,cur_network->MacAddress); + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) + { + rtw_wapi_return_one_sta_info(padapter, psta->hwaddr); + } + else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || + check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) + { + rtw_wapi_return_all_sta_info(padapter); + } +#endif + + if(check_fwstate(&padapter->mlmepriv, _FW_LINKED) + || (rtw_to_roam(padapter) <= 0) + ) + { + + rtw_os_indicate_disconnect(padapter, reason, locally_generated); + + //set ips_deny_time to avoid enter IPS before LPS leave + rtw_set_ips_deny(padapter, 3000); + + _clr_fwstate_(pmlmepriv, _FW_LINKED); + + rtw_led_control(padapter, LED_CTL_NO_LINK); + + rtw_clear_scan_deny(padapter); + } + +#ifdef CONFIG_P2P_PS + p2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1); +#endif // CONFIG_P2P_PS + +#ifdef CONFIG_LPS + rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_DISCONNECT, 1); +#endif + +#ifdef CONFIG_BEAMFORMING + beamforming_wk_cmd(padapter, BEAMFORMING_CTRL_LEAVE, cur_network->MacAddress, ETH_ALEN, 1); +#endif /*CONFIG_BEAMFORMING*/ + +_func_exit_; +} + +inline void rtw_indicate_scan_done( _adapter *padapter, bool aborted) +{ + DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + + rtw_os_indicate_scan_done(padapter, aborted); + +#ifdef CONFIG_IPS + if (is_primary_adapter(padapter) + && (_FALSE == adapter_to_pwrctl(padapter)->bInSuspend) + && (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE|WIFI_UNDER_LINKING) == _FALSE)) + { + struct pwrctrl_priv *pwrpriv; + + pwrpriv = adapter_to_pwrctl(padapter); + rtw_set_ips_deny(padapter, 0); +#ifdef CONFIG_IPS_CHECK_IN_WD + _set_timer(&padapter->mlmepriv.dynamic_chk_timer, 1); +#else // !CONFIG_IPS_CHECK_IN_WD + _rtw_set_pwr_state_check_timer(pwrpriv, 1); +#endif // !CONFIG_IPS_CHECK_IN_WD + } +#endif // CONFIG_IPS +} + +static u32 _rtw_wait_scan_done(_adapter *adapter, u8 abort, u32 timeout_ms) +{ + u32 start; + u32 pass_ms; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); + + start = rtw_get_current_time(); + + pmlmeext->scan_abort = abort; + + while (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) + && rtw_get_passing_time_ms(start) <= timeout_ms) { + + if (RTW_CANNOT_RUN(adapter)) + break; + + DBG_871X(FUNC_NDEV_FMT"fw_state=_FW_UNDER_SURVEY!\n", FUNC_NDEV_ARG(adapter->pnetdev)); + rtw_msleep_os(20); + } + + if (_TRUE == abort) { + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) { + if (!RTW_CANNOT_RUN(adapter)) + DBG_871X(FUNC_NDEV_FMT"waiting for scan_abort time out!\n", FUNC_NDEV_ARG(adapter->pnetdev)); + #ifdef CONFIG_PLATFORM_MSTAR + /*_clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY);*/ + set_survey_timer(pmlmeext, 0); + mlme_set_scan_to_timer(pmlmepriv, 50); + #endif + rtw_indicate_scan_done(adapter, _TRUE); + } + } + + pmlmeext->scan_abort = _FALSE; + pass_ms = rtw_get_passing_time_ms(start); + + return pass_ms; + +} + +void rtw_scan_wait_completed(_adapter *adapter) +{ + u32 scan_to = SCANNING_TIMEOUT; + +#ifdef CONFIG_SCAN_BACKOP + if (IsSupported5G(adapter->registrypriv.wireless_mode) + && IsSupported24G(adapter->registrypriv.wireless_mode)) /*dual band*/ + scan_to = CONC_SCANNING_TIMEOUT_DUAL_BAND; + else /*single band*/ + scan_to = CONC_SCANNING_TIMEOUT_SINGLE_BAND; +#endif /* CONFIG_SCAN_BACKOP */ + + _rtw_wait_scan_done(adapter, _FALSE, scan_to); +} + +u32 rtw_scan_abort_timeout(_adapter *adapter, u32 timeout_ms) +{ + return _rtw_wait_scan_done(adapter, _TRUE, timeout_ms); +} + +void rtw_scan_abort_no_wait(_adapter *adapter) +{ + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); + + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) + pmlmeext->scan_abort = _TRUE; +} + +void rtw_scan_abort(_adapter *adapter) +{ + rtw_scan_abort_timeout(adapter, 200); +} + +static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wlan_network *pnetwork) +{ + int i; + struct sta_info *bmc_sta, *psta=NULL; + struct recv_reorder_ctrl *preorder_ctrl; + struct sta_priv *pstapriv = &padapter->stapriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + psta = rtw_get_stainfo(pstapriv, pnetwork->network.MacAddress); + if(psta==NULL) { + psta = rtw_alloc_stainfo(pstapriv, pnetwork->network.MacAddress); + } + + if(psta) //update ptarget_sta + { + DBG_871X("%s\n", __FUNCTION__); + + psta->aid = pnetwork->join_res; + +#if 0 //alloc macid when call rtw_alloc_stainfo(), and release macid when call rtw_free_stainfo() +#ifdef CONFIG_CONCURRENT_MODE + + if(PRIMARY_ADAPTER == padapter->adapter_type) + psta->mac_id=0; + else + psta->mac_id=2; +#else + psta->mac_id=0; +#endif +#endif //removed + + update_sta_info(padapter, psta); + + //update station supportRate + psta->bssratelen = rtw_get_rateset_len(pnetwork->network.SupportedRates); + _rtw_memcpy(psta->bssrateset, pnetwork->network.SupportedRates, psta->bssratelen); + rtw_hal_update_sta_rate_mask(padapter, psta); + + psta->wireless_mode = pmlmeext->cur_wireless_mode; + psta->raid = rtw_hal_networktype_to_raid(padapter,psta); + + + //sta mode + rtw_hal_set_odm_var(padapter,HAL_ODM_STA_INFO,psta,_TRUE); + + //security related + if(padapter->securitypriv.dot11AuthAlgrthm== dot11AuthAlgrthm_8021X) + { + padapter->securitypriv.binstallGrpkey=_FALSE; + padapter->securitypriv.busetkipkey=_FALSE; + padapter->securitypriv.bgrpkey_handshake=_FALSE; + + psta->ieee8021x_blocked=_TRUE; + psta->dot118021XPrivacy=padapter->securitypriv.dot11PrivacyAlgrthm; + + _rtw_memset((u8 *)&psta->dot118021x_UncstKey, 0, sizeof (union Keytype)); + + _rtw_memset((u8 *)&psta->dot11tkiprxmickey, 0, sizeof (union Keytype)); + _rtw_memset((u8 *)&psta->dot11tkiptxmickey, 0, sizeof (union Keytype)); + + _rtw_memset((u8 *)&psta->dot11txpn, 0, sizeof (union pn48)); + psta->dot11txpn.val = psta->dot11txpn.val + 1; +#ifdef CONFIG_IEEE80211W + _rtw_memset((u8 *)&psta->dot11wtxpn, 0, sizeof (union pn48)); +#endif //CONFIG_IEEE80211W + _rtw_memset((u8 *)&psta->dot11rxpn, 0, sizeof (union pn48)); + } + + // Commented by Albert 2012/07/21 + // When doing the WPS, the wps_ie_len won't equal to 0 + // And the Wi-Fi driver shouldn't allow the data packet to be tramsmitted. + if ( padapter->securitypriv.wps_ie_len != 0 ) + { + psta->ieee8021x_blocked=_TRUE; + padapter->securitypriv.wps_ie_len = 0; + } + + + //for A-MPDU Rx reordering buffer control for bmc_sta & sta_info + //if A-MPDU Rx is enabled, reseting rx_ordering_ctrl wstart_b(indicate_seq) to default value=0xffff + //todo: check if AP can send A-MPDU packets + for(i=0; i < 16 ; i++) + { + //preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; + preorder_ctrl = &psta->recvreorder_ctrl[i]; + preorder_ctrl->enable = _FALSE; + preorder_ctrl->indicate_seq = 0xffff; + #ifdef DBG_RX_SEQ + DBG_871X("DBG_RX_SEQ %s:%d indicate_seq:%u \n", __FUNCTION__, __LINE__, + preorder_ctrl->indicate_seq); + #endif + preorder_ctrl->wend_b= 0xffff; + preorder_ctrl->wsize_b = 64;//max_ampdu_sz;//ex. 32(kbytes) -> wsize_b=32 + preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID; + } + + + bmc_sta = rtw_get_bcmc_stainfo(padapter); + if(bmc_sta) + { + for(i=0; i < 16 ; i++) + { + //preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; + preorder_ctrl = &bmc_sta->recvreorder_ctrl[i]; + preorder_ctrl->enable = _FALSE; + preorder_ctrl->indicate_seq = 0xffff; + #ifdef DBG_RX_SEQ + DBG_871X("DBG_RX_SEQ %s:%d indicate_seq:%u \n", __FUNCTION__, __LINE__, + preorder_ctrl->indicate_seq); + #endif + preorder_ctrl->wend_b= 0xffff; + preorder_ctrl->wsize_b = 64;//max_ampdu_sz;//ex. 32(kbytes) -> wsize_b=32 + preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID; + } + } + } + + return psta; + +} + +//pnetwork : returns from rtw_joinbss_event_callback +//ptarget_wlan: found from scanned_queue +static void rtw_joinbss_update_network(_adapter *padapter, struct wlan_network *ptarget_wlan, struct wlan_network *pnetwork) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct wlan_network *cur_network = &(pmlmepriv->cur_network); + + DBG_871X("%s\n", __FUNCTION__); + + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("\nfw_state:%x, BSSID:"MAC_FMT"\n" + ,get_fwstate(pmlmepriv), MAC_ARG(pnetwork->network.MacAddress))); + + + // why not use ptarget_wlan?? + _rtw_memcpy(&cur_network->network, &pnetwork->network, pnetwork->network.Length); + // some IEs in pnetwork is wrong, so we should use ptarget_wlan IEs + cur_network->network.IELength = ptarget_wlan->network.IELength; + _rtw_memcpy(&cur_network->network.IEs[0], &ptarget_wlan->network.IEs[0], MAX_IE_SZ); + + cur_network->aid = pnetwork->join_res; + + +#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS + rtw_set_signal_stat_timer(&padapter->recvpriv); +#endif + padapter->recvpriv.signal_strength = ptarget_wlan->network.PhyInfo.SignalStrength; + padapter->recvpriv.signal_qual = ptarget_wlan->network.PhyInfo.SignalQuality; + //the ptarget_wlan->network.Rssi is raw data, we use ptarget_wlan->network.PhyInfo.SignalStrength instead (has scaled) + padapter->recvpriv.rssi = translate_percentage_to_dbm(ptarget_wlan->network.PhyInfo.SignalStrength); + #if defined(DBG_RX_SIGNAL_DISPLAY_PROCESSING) && 1 + DBG_871X(FUNC_ADPT_FMT" signal_strength:%3u, rssi:%3d, signal_qual:%3u" + "\n" + , FUNC_ADPT_ARG(padapter) + , padapter->recvpriv.signal_strength + , padapter->recvpriv.rssi + , padapter->recvpriv.signal_qual + ); + #endif +#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS + rtw_set_signal_stat_timer(&padapter->recvpriv); +#endif + + //update fw_state //will clr _FW_UNDER_LINKING here indirectly + switch(pnetwork->network.InfrastructureMode) + { + case Ndis802_11Infrastructure: + + if(pmlmepriv->fw_state&WIFI_UNDER_WPS) + pmlmepriv->fw_state = WIFI_STATION_STATE|WIFI_UNDER_WPS; + else + pmlmepriv->fw_state = WIFI_STATION_STATE; + + break; + case Ndis802_11IBSS: + pmlmepriv->fw_state = WIFI_ADHOC_STATE; + break; + default: + pmlmepriv->fw_state = WIFI_NULL_STATE; + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Invalid network_mode\n")); + break; + } + + rtw_update_protection(padapter, (cur_network->network.IEs) + sizeof (NDIS_802_11_FIXED_IEs), + (cur_network->network.IELength)); + +#ifdef CONFIG_80211N_HT + rtw_update_ht_cap(padapter, cur_network->network.IEs, cur_network->network.IELength, (u8) cur_network->network.Configuration.DSConfig); +#endif +} + +//Notes: the fucntion could be > passive_level (the same context as Rx tasklet) +//pnetwork : returns from rtw_joinbss_event_callback +//ptarget_wlan: found from scanned_queue +//if join_res > 0, for (fw_state==WIFI_STATION_STATE), we check if "ptarget_sta" & "ptarget_wlan" exist. +//if join_res > 0, for (fw_state==WIFI_ADHOC_STATE), we only check if "ptarget_wlan" exist. +//if join_res > 0, update "cur_network->network" from "pnetwork->network" if (ptarget_wlan !=NULL). +// +//#define REJOIN +void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf) +{ + _irqL irqL,irqL2; + static u8 retry=0; + u8 timer_cancelled; + struct sta_info *ptarget_sta= NULL, *pcur_sta = NULL; + struct sta_priv *pstapriv = &adapter->stapriv; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct wlan_network *pnetwork = (struct wlan_network *)pbuf; + struct wlan_network *cur_network = &(pmlmepriv->cur_network); + struct wlan_network *pcur_wlan = NULL, *ptarget_wlan = NULL; + unsigned int the_same_macaddr = _FALSE; + +_func_enter_; + +#ifdef CONFIG_RTL8712 + //endian_convert + pnetwork->join_res = le32_to_cpu(pnetwork->join_res); + pnetwork->network_type = le32_to_cpu(pnetwork->network_type); + pnetwork->network.Length = le32_to_cpu(pnetwork->network.Length); + pnetwork->network.Ssid.SsidLength = le32_to_cpu(pnetwork->network.Ssid.SsidLength); + pnetwork->network.Privacy =le32_to_cpu( pnetwork->network.Privacy); + pnetwork->network.Rssi = le32_to_cpu(pnetwork->network.Rssi); + pnetwork->network.NetworkTypeInUse =le32_to_cpu(pnetwork->network.NetworkTypeInUse) ; + pnetwork->network.Configuration.ATIMWindow = le32_to_cpu(pnetwork->network.Configuration.ATIMWindow); + pnetwork->network.Configuration.BeaconPeriod = le32_to_cpu(pnetwork->network.Configuration.BeaconPeriod); + pnetwork->network.Configuration.DSConfig = le32_to_cpu(pnetwork->network.Configuration.DSConfig); + pnetwork->network.Configuration.FHConfig.DwellTime=le32_to_cpu(pnetwork->network.Configuration.FHConfig.DwellTime); + pnetwork->network.Configuration.FHConfig.HopPattern=le32_to_cpu(pnetwork->network.Configuration.FHConfig.HopPattern); + pnetwork->network.Configuration.FHConfig.HopSet=le32_to_cpu(pnetwork->network.Configuration.FHConfig.HopSet); + pnetwork->network.Configuration.FHConfig.Length=le32_to_cpu(pnetwork->network.Configuration.FHConfig.Length); + pnetwork->network.Configuration.Length = le32_to_cpu(pnetwork->network.Configuration.Length); + pnetwork->network.InfrastructureMode = le32_to_cpu(pnetwork->network.InfrastructureMode); + pnetwork->network.IELength = le32_to_cpu(pnetwork->network.IELength ); +#endif + + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("joinbss event call back received with res=%d\n", pnetwork->join_res)); + + rtw_get_encrypt_decrypt_from_registrypriv(adapter); + + + if (pmlmepriv->assoc_ssid.SsidLength == 0) + { + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("@@@@@ joinbss event call back for Any SSid\n")); + } + else + { + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("@@@@@ rtw_joinbss_event_callback for SSid:%s\n", pmlmepriv->assoc_ssid.Ssid)); + } + + the_same_macaddr = _rtw_memcmp(pnetwork->network.MacAddress, cur_network->network.MacAddress, ETH_ALEN); + + pnetwork->network.Length = get_WLAN_BSSID_EX_sz(&pnetwork->network); + if(pnetwork->network.Length > sizeof(WLAN_BSSID_EX)) + { + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n\n ***joinbss_evt_callback return a wrong bss ***\n\n")); + goto ignore_joinbss_callback; + } + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0; + pmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0; + + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("\n rtw_joinbss_event_callback !! _enter_critical \n")); + + if(pnetwork->join_res > 0) + { + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + retry = 0; + if (check_fwstate(pmlmepriv,_FW_UNDER_LINKING) ) + { + //s1. find ptarget_wlan + if(check_fwstate(pmlmepriv, _FW_LINKED) ) + { + if(the_same_macaddr == _TRUE) + { + ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress); + } + else + { + pcur_wlan = rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress); + if(pcur_wlan) pcur_wlan->fixed = _FALSE; + + pcur_sta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); + if(pcur_sta){ + //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); + rtw_free_stainfo(adapter, pcur_sta); + //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); + } + + ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->network.MacAddress); + if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE){ + if(ptarget_wlan) ptarget_wlan->fixed = _TRUE; + } + } + + } + else + { + ptarget_wlan = _rtw_find_same_network(&pmlmepriv->scanned_queue, pnetwork); + if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE){ + if(ptarget_wlan) ptarget_wlan->fixed = _TRUE; + } + } + + //s2. update cur_network + if(ptarget_wlan) + { + rtw_joinbss_update_network(adapter, ptarget_wlan, pnetwork); + } + else + { + DBG_871X_LEVEL(_drv_always_, "Can't find ptarget_wlan when joinbss_event callback\n"); + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + goto ignore_joinbss_callback; + } + + + //s3. find ptarget_sta & update ptarget_sta after update cur_network only for station mode + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) { + ptarget_sta = rtw_joinbss_update_stainfo(adapter, pnetwork); + if (ptarget_sta == NULL) { + DBG_871X_LEVEL(_drv_err_, "Can't update stainfo when joinbss_event callback\n"); + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + goto ignore_joinbss_callback; + } + } + + //s4. indicate connect + if (MLME_IS_STA(adapter) || MLME_IS_ADHOC(adapter)) { + pmlmepriv->cur_network_scanned = ptarget_wlan; + rtw_indicate_connect(adapter); + } + + //s5. Cancle assoc_timer + _cancel_timer(&pmlmepriv->assoc_timer, &timer_cancelled); + + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("Cancle assoc_timer \n")); + + } + else + { + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("rtw_joinbss_event_callback err: fw_state:%x", get_fwstate(pmlmepriv))); + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + goto ignore_joinbss_callback; + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + } + else if(pnetwork->join_res == -4) + { + rtw_reset_securitypriv(adapter); + _set_timer(&pmlmepriv->assoc_timer, 1); + + //rtw_free_assoc_resources(adapter, 1); + + if((check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) == _TRUE) + { + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("fail! clear _FW_UNDER_LINKING ^^^fw_state=%x\n", get_fwstate(pmlmepriv))); + _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); + } + + } + else //if join_res < 0 (join fails), then try again + { + + #ifdef REJOIN + res = _FAIL; + if(retry < 2) { + res = rtw_select_and_join_from_scanned_queue(pmlmepriv); + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("rtw_select_and_join_from_scanned_queue again! res:%d\n",res)); + } + + if(res == _SUCCESS) + { + //extend time of assoc_timer + _set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT); + retry++; + } + else if(res == 2)//there is no need to wait for join + { + _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); + rtw_indicate_connect(adapter); + } + else + { + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Set Assoc_Timer = 1; can't find match ssid in scanned_q \n")); + #endif + + _set_timer(&pmlmepriv->assoc_timer, 1); + //rtw_free_assoc_resources(adapter, 1); + _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); + + #ifdef REJOIN + retry = 0; + } + #endif + } + +ignore_joinbss_callback: + + _exit_critical_bh(&pmlmepriv->lock, &irqL); + _func_exit_; +} + +void rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf) +{ + struct wlan_network *pnetwork = (struct wlan_network *)pbuf; + +_func_enter_; + + mlmeext_joinbss_event_callback(adapter, pnetwork->join_res); + + rtw_os_xmit_schedule(adapter); + +#ifdef CONFIG_CONCURRENT_MODE + rtw_os_xmit_schedule(adapter->pbuddy_adapter); +#endif + +_func_exit_; +} + +void rtw_sta_media_status_rpt(_adapter *adapter, struct sta_info *sta, bool connected) +{ + struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; + bool miracast_enabled = 0; + bool miracast_sink = 0; + u8 role = H2C_MSR_ROLE_RSVD; + + if (sta == NULL) { + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" sta is NULL\n" + , FUNC_ADPT_ARG(adapter)); + rtw_warn_on(1); + return; + } + + if (sta->mac_id >= macid_ctl->num) { + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" invalid macid:%u\n" + , FUNC_ADPT_ARG(adapter), sta->mac_id); + rtw_warn_on(1); + return; + } + + if (!rtw_macid_is_used(macid_ctl, sta->mac_id)) { + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" macid:%u not is used, set connected to 0\n" + , FUNC_ADPT_ARG(adapter), sta->mac_id); + connected = 0; + rtw_warn_on(1); + } + + if (connected && !rtw_macid_is_bmc(macid_ctl, sta->mac_id)) { + miracast_enabled = STA_OP_WFD_MODE(sta) != 0 && is_miracast_enabled(adapter); + miracast_sink = miracast_enabled && (STA_OP_WFD_MODE(sta) & MIRACAST_SINK); + + #ifdef CONFIG_TDLS + if (sta->tdls_sta_state & TDLS_LINKED_STATE) + role = H2C_MSR_ROLE_TDLS; + else + #endif + if (MLME_IS_STA(adapter)) { + if (MLME_IS_GC(adapter)) + role = H2C_MSR_ROLE_GO; + else + role = H2C_MSR_ROLE_AP; + } else if (MLME_IS_AP(adapter)) { + if (MLME_IS_GO(adapter)) + role = H2C_MSR_ROLE_GC; + else + role = H2C_MSR_ROLE_STA; + } else if (MLME_IS_ADHOC(adapter) || MLME_IS_ADHOC_MASTER(adapter)) + role = H2C_MSR_ROLE_ADHOC; + + #ifdef CONFIG_WFD + if (role == H2C_MSR_ROLE_GC + || role == H2C_MSR_ROLE_GO + || role == H2C_MSR_ROLE_TDLS + ) { + if (adapter->wfd_info.rtsp_ctrlport + || adapter->wfd_info.tdls_rtsp_ctrlport + || adapter->wfd_info.peer_rtsp_ctrlport) + rtw_wfd_st_switch(sta, 1); + } + #endif + } + + rtw_hal_set_FwMediaStatusRpt_single_cmd(adapter + , connected + , miracast_enabled + , miracast_sink + , role + , sta->mac_id + ); +} + +u8 rtw_sta_media_status_rpt_cmd(_adapter *adapter, struct sta_info *sta, bool connected) +{ + struct cmd_priv *cmdpriv = &adapter->cmdpriv; + struct cmd_obj *cmdobj; + struct drvextra_cmd_parm *cmd_parm; + struct sta_media_status_rpt_cmd_parm *rpt_parm; + u8 res = _SUCCESS; + + cmdobj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmdobj == NULL) { + res = _FAIL; + goto exit; + } + + cmd_parm = (struct drvextra_cmd_parm *)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if (cmd_parm == NULL) { + rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj)); + res = _FAIL; + goto exit; + } + + rpt_parm = (struct sta_media_status_rpt_cmd_parm *)rtw_zmalloc(sizeof(struct sta_media_status_rpt_cmd_parm)); + if (rpt_parm == NULL) { + rtw_mfree((u8 *)cmdobj, sizeof(struct cmd_obj)); + rtw_mfree((u8 *)cmd_parm, sizeof(struct drvextra_cmd_parm)); + res = _FAIL; + goto exit; + } + + rpt_parm->sta = sta; + rpt_parm->connected = connected; + + cmd_parm->ec_id = STA_MSTATUS_RPT_WK_CID; + cmd_parm->type = 0; + cmd_parm->size = sizeof(struct sta_media_status_rpt_cmd_parm); + cmd_parm->pbuf = (u8 *)rpt_parm; + init_h2fwcmd_w_parm_no_rsp(cmdobj, cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(cmdpriv, cmdobj); + +exit: + return res; +} + +inline void rtw_sta_media_status_rpt_cmd_hdl(_adapter *adapter, struct sta_media_status_rpt_cmd_parm *parm) +{ + rtw_sta_media_status_rpt(adapter, parm->sta, parm->connected); +} + +void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf) +{ + _irqL irqL; + struct sta_info *psta; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct stassoc_event *pstassoc = (struct stassoc_event*)pbuf; + struct wlan_network *cur_network = &(pmlmepriv->cur_network); + struct wlan_network *ptarget_wlan = NULL; + +_func_enter_; + + if(rtw_access_ctrl(adapter, pstassoc->macaddr) == _FALSE) + return; + +#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) + if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) + { + psta = rtw_get_stainfo(&adapter->stapriv, pstassoc->macaddr); + if(psta) + { + u8 *passoc_req = NULL; + u32 assoc_req_len = 0; + + rtw_sta_media_status_rpt(adapter, psta, 1); + +#ifndef CONFIG_AUTO_AP_MODE + + ap_sta_info_defer_update(adapter, psta); + + //report to upper layer + DBG_871X("indicate_sta_assoc_event to upper layer - hostapd\n"); +#ifdef CONFIG_IOCTL_CFG80211 + _enter_critical_bh(&psta->lock, &irqL); + if(psta->passoc_req && psta->assoc_req_len>0) + { + passoc_req = rtw_zmalloc(psta->assoc_req_len); + if(passoc_req) + { + assoc_req_len = psta->assoc_req_len; + _rtw_memcpy(passoc_req, psta->passoc_req, assoc_req_len); + + rtw_mfree(psta->passoc_req , psta->assoc_req_len); + psta->passoc_req = NULL; + psta->assoc_req_len = 0; + } + } + _exit_critical_bh(&psta->lock, &irqL); + + if(passoc_req && assoc_req_len>0) + { + rtw_cfg80211_indicate_sta_assoc(adapter, passoc_req, assoc_req_len); + + rtw_mfree(passoc_req, assoc_req_len); + } +#else //!CONFIG_IOCTL_CFG80211 + rtw_indicate_sta_assoc_event(adapter, psta); +#endif //!CONFIG_IOCTL_CFG80211 +#endif //!CONFIG_AUTO_AP_MODE + +#ifdef CONFIG_BEAMFORMING + beamforming_wk_cmd(adapter, BEAMFORMING_CTRL_ENTER, (u8 *)psta, sizeof(struct sta_info), 0); +#endif/*CONFIG_BEAMFORMING*/ + } + goto exit; + } +#endif //defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) + + /* for AD-HOC mode */ + psta = rtw_get_stainfo(&adapter->stapriv, pstassoc->macaddr); + if (psta == NULL) { + DBG_871X_LEVEL(_drv_err_, FUNC_ADPT_FMT" get no sta_info with "MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(pstassoc->macaddr)); + rtw_warn_on(1); + goto exit; + } + + rtw_hal_set_odm_var(adapter,HAL_ODM_STA_INFO,psta,_TRUE); + + rtw_sta_media_status_rpt(adapter, psta, 1); + + if(adapter->securitypriv.dot11AuthAlgrthm==dot11AuthAlgrthm_8021X) + psta->dot118021XPrivacy = adapter->securitypriv.dot11PrivacyAlgrthm; + + + psta->ieee8021x_blocked = _FALSE; + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + if ( (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)==_TRUE ) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)==_TRUE ) ) + { + if(adapter->stapriv.asoc_sta_count== 2) + { + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress); + pmlmepriv->cur_network_scanned = ptarget_wlan; + if(ptarget_wlan) ptarget_wlan->fixed = _TRUE; + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + // a sta + bc/mc_stainfo (not Ibss_stainfo) + rtw_indicate_connect(adapter); + } + } + + _exit_critical_bh(&pmlmepriv->lock, &irqL); + + + mlmeext_sta_add_event_callback(adapter, psta); + +#ifdef CONFIG_RTL8711 + //submit SetStaKey_cmd to tell fw, fw will allocate an CAM entry for this sta + rtw_setstakey_cmd(adapter, psta, GROUP_KEY, _TRUE); +#endif + +exit: + +_func_exit_; + +} + +#ifdef CONFIG_IEEE80211W +void rtw_sta_timeout_event_callback(_adapter *adapter, u8 *pbuf) +{ + _irqL irqL; + struct sta_info *psta; + struct stadel_event *pstadel = (struct stadel_event *)pbuf; + struct sta_priv *pstapriv = &adapter->stapriv; + +_func_enter_; + + psta = rtw_get_stainfo(&adapter->stapriv, pstadel->macaddr); + + if (psta) { + u8 updated = _FALSE; + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + if (rtw_is_list_empty(&psta->asoc_list) == _FALSE) { + rtw_list_delete(&psta->asoc_list); + pstapriv->asoc_list_cnt--; + updated = ap_free_sta(adapter, psta, _TRUE, WLAN_REASON_PREV_AUTH_NOT_VALID, _TRUE); + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + associated_clients_update(adapter, updated, STA_INFO_UPDATE_ALL); + } + + +_func_exit_; + +} +#endif /* CONFIG_IEEE80211W */ + +static void rtw_sta_mstatus_disc_rpt(_adapter *adapter, u8 mac_id) +{ + struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; + + DBG_871X("%s "ADPT_FMT" - mac_id=%d\n", __func__, ADPT_ARG(adapter), mac_id); + + if (mac_id >= 0 && mac_id < macid_ctl->num) { + rtw_hal_set_FwMediaStatusRpt_single_cmd(adapter, 0, 0, 0, 0, mac_id); + /* + * For safety, prevent from keeping macid sleep. + * If we can sure all power mode enter/leave are paired, + * this check can be removed. + * Lucas@20131113 + */ + /* wakeup macid after disconnect. */ + /*if (MLME_IS_STA(adapter))*/ + rtw_hal_macid_wakeup(adapter, mac_id); + } else { + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" invalid macid:%u\n" + , FUNC_ADPT_ARG(adapter), mac_id); + rtw_warn_on(1); + } +} + +void rtw_sta_mstatus_report(_adapter *adapter) +{ + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct wlan_network *tgt_network = &pmlmepriv->cur_network; + struct sta_info *psta = NULL; + + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { + psta = rtw_get_stainfo(&adapter->stapriv, tgt_network->network.MacAddress); + if (psta) { + rtw_sta_mstatus_disc_rpt(adapter, psta->mac_id); + } else { + DBG_871X("%s "ADPT_FMT" - mac_addr: "MAC_FMT" psta == NULL\n", __func__, ADPT_ARG(adapter), MAC_ARG(tgt_network->network.MacAddress)); + rtw_warn_on(1); + } + } +} + +void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf) +{ + _irqL irqL,irqL2; + int mac_id = (-1); + struct sta_info *psta; + struct wlan_network* pwlan = NULL; + WLAN_BSSID_EX *pdev_network=NULL; + u8* pibss = NULL; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct stadel_event *pstadel = (struct stadel_event*)pbuf; + struct sta_priv *pstapriv = &adapter->stapriv; + struct wlan_network *tgt_network = &(pmlmepriv->cur_network); + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; + +_func_enter_; + + DBG_871X("%s(mac_id=%d)=" MAC_FMT "\n", __func__, pstadel->mac_id, MAC_ARG(pstadel->macaddr)); + rtw_sta_mstatus_disc_rpt(adapter, pstadel->mac_id); + + psta = rtw_get_stainfo(&adapter->stapriv, pstadel->macaddr); + + if (psta == NULL) { + DBG_871X("%s(mac_id=%d)=" MAC_FMT " psta == NULL\n", __func__, pstadel->mac_id, MAC_ARG(pstadel->macaddr)); + /*rtw_warn_on(1);*/ + } + + if (psta) + rtw_wfd_st_switch(psta, 0); + + + //if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) + if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) + { +#ifdef CONFIG_IOCTL_CFG80211 + #ifdef COMPAT_KERNEL_RELEASE + + #elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)) || defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) + rtw_cfg80211_indicate_sta_disassoc(adapter, pstadel->macaddr, *(u16*)pstadel->rsvd); + #endif //(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)) || defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) +#endif //CONFIG_IOCTL_CFG80211 + + return; + } + + + mlmeext_sta_del_event_callback(adapter); + + _enter_critical_bh(&pmlmepriv->lock, &irqL2); + + if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) ) + { + u16 reason = *((unsigned short *)(pstadel->rsvd)); + bool roam = _FALSE; + struct wlan_network *roam_target = NULL; + + #ifdef CONFIG_LAYER2_ROAMING + if(adapter->registrypriv.wifi_spec==1) { + roam = _FALSE; + } else if (reason == WLAN_REASON_EXPIRATION_CHK && rtw_chk_roam_flags(adapter, RTW_ROAM_ON_EXPIRED)) { + roam = _TRUE; + } else if (reason == WLAN_REASON_ACTIVE_ROAM && rtw_chk_roam_flags(adapter, RTW_ROAM_ACTIVE)) { + roam = _TRUE; + roam_target = pmlmepriv->roam_network; + } +#ifdef CONFIG_INTEL_WIDI + else if (adapter->mlmepriv.widi_state == INTEL_WIDI_STATE_CONNECTED) { + roam = _TRUE; + } +#endif // CONFIG_INTEL_WIDI + + if (roam == _TRUE) { + if (rtw_to_roam(adapter) > 0) + rtw_dec_to_roam(adapter); /* this stadel_event is caused by roaming, decrease to_roam */ + else if (rtw_to_roam(adapter) == 0) + rtw_set_to_roam(adapter, adapter->registrypriv.max_roaming_times); + } else { + rtw_set_to_roam(adapter, 0); + } + #endif /* CONFIG_LAYER2_ROAMING */ + + rtw_free_uc_swdec_pending_queue(adapter); + + rtw_free_assoc_resources(adapter, 1); + rtw_indicate_disconnect(adapter, *(u16 *)pstadel->rsvd, pstadel->locally_generated); + rtw_free_mlme_priv_ie_data(pmlmepriv); + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + // remove the network entry in scanned_queue + pwlan = rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress); + if (pwlan) { + pwlan->fixed = _FALSE; + rtw_free_network_nolock(adapter, pwlan); + } + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + +#ifdef CONFIG_INTEL_WIDI + if (!rtw_to_roam(adapter)) + process_intel_widi_disconnect(adapter, 1); +#endif // CONFIG_INTEL_WIDI + + _rtw_roaming(adapter, roam_target); + } + + if ( check_fwstate(pmlmepriv,WIFI_ADHOC_MASTER_STATE) || + check_fwstate(pmlmepriv,WIFI_ADHOC_STATE)) + { + + //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + rtw_free_stainfo(adapter, psta); + //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + + if(adapter->stapriv.asoc_sta_count== 1) //a sta + bc/mc_stainfo (not Ibss_stainfo) + { + //rtw_indicate_disconnect(adapter);//removed@20091105 + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + //free old ibss network + //pwlan = rtw_find_network(&pmlmepriv->scanned_queue, pstadel->macaddr); + pwlan = rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress); + if(pwlan) + { + pwlan->fixed = _FALSE; + rtw_free_network_nolock(adapter, pwlan); + } + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + //re-create ibss + pdev_network = &(adapter->registrypriv.dev_network); + pibss = adapter->registrypriv.dev_network.MacAddress; + + _rtw_memcpy(pdev_network, &tgt_network->network, get_WLAN_BSSID_EX_sz(&tgt_network->network)); + + _rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID)); + _rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID)); + + rtw_update_registrypriv_dev_network(adapter); + + rtw_generate_random_ibss(pibss); + + if(check_fwstate(pmlmepriv,WIFI_ADHOC_STATE)) + { + set_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE); + _clr_fwstate_(pmlmepriv, WIFI_ADHOC_STATE); + } + + if (rtw_create_ibss_cmd(adapter, 0) != _SUCCESS) + RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("***Error=>stadel_event_callback: rtw_create_ibss_cmd status FAIL***\n")); + + } + + } + + _exit_critical_bh(&pmlmepriv->lock, &irqL2); + +_func_exit_; + +} + + +void rtw_cpwm_event_callback(PADAPTER padapter, u8 *pbuf) +{ +#ifdef CONFIG_LPS_LCLK + struct reportpwrstate_parm *preportpwrstate; +#endif + +_func_enter_; + + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("+rtw_cpwm_event_callback !!!\n")); +#ifdef CONFIG_LPS_LCLK + preportpwrstate = (struct reportpwrstate_parm*)pbuf; + preportpwrstate->state |= (u8)(adapter_to_pwrctl(padapter)->cpwm_tog + 0x80); + cpwm_int_hdl(padapter, preportpwrstate); +#endif + +_func_exit_; + +} + + +void rtw_wmm_event_callback(PADAPTER padapter, u8 *pbuf) +{ +_func_enter_; + + WMMOnAssocRsp(padapter); + +_func_exit_; + +} + +/* +* _rtw_join_timeout_handler - Timeout/faliure handler for CMD JoinBss +* @adapter: pointer to _adapter structure +*/ +void _rtw_join_timeout_handler (_adapter *adapter) +{ + _irqL irqL; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + +#if 0 + if (rtw_is_drv_stopped(adapter)) { + _rtw_up_sema(&pmlmepriv->assoc_terminate); + return; + } +#endif + +_func_enter_; + + + DBG_871X("%s, fw_state=%x\n", __FUNCTION__, get_fwstate(pmlmepriv)); + + if (RTW_CANNOT_RUN(adapter)) + return; + + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + #ifdef CONFIG_LAYER2_ROAMING + if (rtw_to_roam(adapter) > 0) { /* join timeout caused by roaming */ + while(1) { + rtw_dec_to_roam(adapter); + if (rtw_to_roam(adapter) != 0) { /* try another */ + int do_join_r; + DBG_871X("%s try another roaming\n", __FUNCTION__); + if( _SUCCESS!=(do_join_r=rtw_do_join(adapter)) ) { + DBG_871X("%s roaming do_join return %d\n", __FUNCTION__ ,do_join_r); + continue; + } + break; + } else { +#ifdef CONFIG_INTEL_WIDI + if(adapter->mlmepriv.widi_state == INTEL_WIDI_STATE_ROAMING) + { + _rtw_memset(pmlmepriv->sa_ext, 0x00, L2SDTA_SERVICE_VE_LEN); + intel_widi_wk_cmd(adapter, INTEL_WIDI_LISTEN_WK, NULL, 0); + DBG_871X("change to widi listen\n"); + } +#endif // CONFIG_INTEL_WIDI + DBG_871X("%s We've try roaming but fail\n", __FUNCTION__); + rtw_indicate_disconnect(adapter, 0, _FALSE); + break; + } + } + + } else + #endif + { + rtw_indicate_disconnect(adapter, 0, _FALSE); + free_scanqueue(pmlmepriv);//??? + +#ifdef CONFIG_IOCTL_CFG80211 + //indicate disconnect for the case that join_timeout and check_fwstate != FW_LINKED + rtw_cfg80211_indicate_disconnect(adapter, 0, _FALSE); +#endif //CONFIG_IOCTL_CFG80211 + + } + + _exit_critical_bh(&pmlmepriv->lock, &irqL); + + +#ifdef CONFIG_DRVEXT_MODULE_WSC + drvext_assoc_fail_indicate(&adapter->drvextpriv); +#endif + + +_func_exit_; + +} + +/* +* rtw_scan_timeout_handler - Timeout/Faliure handler for CMD SiteSurvey +* @adapter: pointer to _adapter structure +*/ +void rtw_scan_timeout_handler (_adapter *adapter) +{ + _irqL irqL; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + DBG_871X(FUNC_ADPT_FMT" fw_state=%x\n", FUNC_ADPT_ARG(adapter), get_fwstate(pmlmepriv)); + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY); + + _exit_critical_bh(&pmlmepriv->lock, &irqL); + +#ifdef CONFIG_IOCTL_CFG80211 + rtw_cfg80211_surveydone_event_callback(adapter); +#endif //CONFIG_IOCTL_CFG80211 + + rtw_indicate_scan_done(adapter, _TRUE); + +#if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_IOCTL_CFG80211) + if (adapter->pbuddy_adapter) { + _adapter *buddy_adapter = adapter->pbuddy_adapter; + struct mlme_priv *buddy_mlme = &(buddy_adapter->mlmepriv); + struct rtw_wdev_priv *buddy_wdev_priv = adapter_wdev_data(buddy_adapter); + bool indicate_buddy_scan = _FALSE; + + _enter_critical_bh(&buddy_wdev_priv->scan_req_lock, &irqL); + if (buddy_wdev_priv->scan_request && buddy_mlme->scanning_via_buddy_intf == _TRUE) { + buddy_mlme->scanning_via_buddy_intf = _FALSE; + clr_fwstate(buddy_mlme, _FW_UNDER_SURVEY); + indicate_buddy_scan = _TRUE; + } + _exit_critical_bh(&buddy_wdev_priv->scan_req_lock, &irqL); + + if (indicate_buddy_scan == _TRUE) { + rtw_indicate_scan_done(buddy_adapter, _TRUE); + } + } +#endif /* CONFIG_CONCURRENT_MODE */ +} + +void rtw_mlme_reset_auto_scan_int(_adapter *adapter) +{ + struct mlme_priv *mlme = &adapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + +#ifdef CONFIG_P2P + if(!rtw_p2p_chk_state(&adapter->wdinfo, P2P_STATE_NONE)) { + mlme->auto_scan_int_ms = 0; /* disabled */ + goto exit; + } +#endif + +#ifdef CONFIG_TDLS + if (adapter->tdlsinfo.link_established == _TRUE) { + mlme->auto_scan_int_ms = 0; + goto exit; + } +#endif + + if(pmlmeinfo->VHT_enable) //disable auto scan when connect to 11AC AP + { + mlme->auto_scan_int_ms = 0; + } + else if(adapter->registrypriv.wifi_spec && is_client_associated_to_ap(adapter) == _TRUE) { + mlme->auto_scan_int_ms = 60*1000; +#ifdef CONFIG_LAYER2_ROAMING + } else if(rtw_chk_roam_flags(adapter, RTW_ROAM_ACTIVE)) { + if (check_fwstate(mlme, WIFI_STATION_STATE) && check_fwstate(mlme, _FW_LINKED)) + mlme->auto_scan_int_ms = mlme->roam_scan_int_ms; +#endif + } else { + mlme->auto_scan_int_ms = 0; /* disabled */ + } +exit: + return; +} + +void rtw_drv_scan_by_self(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + if (!padapter->registrypriv.wifi_spec) { + if (check_fwstate(pmlmepriv, (_FW_UNDER_SURVEY | _FW_UNDER_LINKING)) == _TRUE) { + DBG_871X(FUNC_ADPT_FMT" _FW_UNDER_SURVEY|_FW_UNDER_LINKING\n", FUNC_ADPT_ARG(padapter)); + goto exit; + } + + if (pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE) { + DBG_871X(FUNC_ADPT_FMT" exit BusyTraffic\n", FUNC_ADPT_ARG(padapter)); + goto exit; + } + } + +#ifdef CONFIG_CONCURRENT_MODE + if (rtw_buddy_adapter_up(padapter)) { + if ((check_buddy_fwstate(padapter, (_FW_UNDER_SURVEY | _FW_UNDER_LINKING)) == _TRUE) || + (padapter->pbuddy_adapter->mlmepriv.LinkDetectInfo.bBusyTraffic == _TRUE)) { + DBG_871X(FUNC_ADPT_FMT", but buddy_intf is under scanning or linking or BusyTraffic\n", FUNC_ADPT_ARG(padapter)); + goto exit; + } + } +#endif + + DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + + rtw_set_802_11_bssid_list_scan(padapter, NULL, 0); + +exit: + return; +} + +static void rtw_auto_scan_handler(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + rtw_mlme_reset_auto_scan_int(padapter); + + if (pmlmepriv->auto_scan_int_ms != 0 + && rtw_get_passing_time_ms(pmlmepriv->scan_start_time) > pmlmepriv->auto_scan_int_ms) + rtw_drv_scan_by_self(padapter); + +} + +void rtw_dynamic_check_timer_handlder(_adapter *adapter) +{ +#ifdef CONFIG_AP_MODE + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; +#endif //CONFIG_AP_MODE + struct registry_priv *pregistrypriv = &adapter->registrypriv; +#ifdef CONFIG_CONCURRENT_MODE + PADAPTER pbuddy_adapter = adapter->pbuddy_adapter; +#endif + + if(!adapter) + return; + + if (!rtw_is_hw_init_completed(adapter)) + return; + + if (RTW_CANNOT_RUN(adapter)) + return; + + +#ifdef CONFIG_CONCURRENT_MODE + if(pbuddy_adapter) + { + if(adapter->net_closed == _TRUE && pbuddy_adapter->net_closed == _TRUE) + { + return; + } + } + else +#endif //CONFIG_CONCURRENT_MODE + if(adapter->net_closed == _TRUE) + { + return; + } + +#ifdef CONFIG_BT_COEXIST + if (is_primary_adapter(adapter)) { + if (GET_HAL_DATA(adapter)->EEPROMBluetoothCoexist == 1) + DBG_871X("IsBtDisabled=%d, IsBtControlLps=%d\n" , rtw_btcoex_IsBtDisabled(adapter) , rtw_btcoex_IsBtControlLps(adapter)); + } +#endif + +#ifdef CONFIG_LPS_LCLK_WD_TIMER /* to avoid leaving lps 32k frequently*/ + if ((adapter_to_pwrctl(adapter)->bFwCurrentInPSMode ==_TRUE ) +#ifdef CONFIG_BT_COEXIST + && (rtw_btcoex_IsBtControlLps(adapter) == _FALSE) +#endif + ) + { + u8 bEnterPS; + + linked_status_chk(adapter, 1); + + bEnterPS = traffic_status_watchdog(adapter, 1); + if(bEnterPS) + { + //rtw_lps_ctrl_wk_cmd(adapter, LPS_CTRL_ENTER, 1); + rtw_hal_dm_watchdog_in_lps(adapter); + } + else + { + //call rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 1) in traffic_status_watchdog() + } + + } + else +#endif //CONFIG_LPS_LCLK_WD_TIMER + { + if(is_primary_adapter(adapter)) + { + rtw_dynamic_chk_wk_cmd(adapter); + } + } + + /* auto site survey */ + rtw_auto_scan_handler(adapter); + +#ifndef CONFIG_ACTIVE_KEEP_ALIVE_CHECK +#ifdef CONFIG_AP_MODE + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + { + expire_timeout_chk(adapter); + } +#endif +#endif //!CONFIG_ACTIVE_KEEP_ALIVE_CHECK + +#ifdef CONFIG_BR_EXT + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) + rcu_read_lock(); +#endif // (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) + +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) + if( adapter->pnetdev->br_port +#else // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) + if( rcu_dereference(adapter->pnetdev->rx_handler_data) +#endif // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) + && (check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) ) + { + // expire NAT2.5 entry + void nat25_db_expire(_adapter *priv); + nat25_db_expire(adapter); + + if (adapter->pppoe_connection_in_progress > 0) { + adapter->pppoe_connection_in_progress--; + } + + // due to rtw_dynamic_check_timer_handlder() is called every 2 seconds + if (adapter->pppoe_connection_in_progress > 0) { + adapter->pppoe_connection_in_progress--; + } + } + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) + rcu_read_unlock(); +#endif // (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) + +#endif // CONFIG_BR_EXT + +} + + +#ifdef CONFIG_SET_SCAN_DENY_TIMER +inline bool rtw_is_scan_deny(_adapter *adapter) +{ + struct mlme_priv *mlmepriv = &adapter->mlmepriv; + return (ATOMIC_READ(&mlmepriv->set_scan_deny) != 0) ? _TRUE : _FALSE; +} + +inline void rtw_clear_scan_deny(_adapter *adapter) +{ + struct mlme_priv *mlmepriv = &adapter->mlmepriv; + ATOMIC_SET(&mlmepriv->set_scan_deny, 0); + if (0) + DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); +} + +void rtw_set_scan_deny_timer_hdl(_adapter *adapter) +{ + rtw_clear_scan_deny(adapter); +} + +void rtw_set_scan_deny(_adapter *adapter, u32 ms) +{ + struct mlme_priv *mlmepriv = &adapter->mlmepriv; +#ifdef CONFIG_CONCURRENT_MODE + struct mlme_priv *b_mlmepriv; +#endif + + if (0) + DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter)); + ATOMIC_SET(&mlmepriv->set_scan_deny, 1); + _set_timer(&mlmepriv->set_scan_deny_timer, ms); + +#ifdef CONFIG_CONCURRENT_MODE + if (!adapter->pbuddy_adapter) + return; + + if (0) + DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(adapter->pbuddy_adapter)); + b_mlmepriv = &adapter->pbuddy_adapter->mlmepriv; + ATOMIC_SET(&b_mlmepriv->set_scan_deny, 1); + _set_timer(&b_mlmepriv->set_scan_deny_timer, ms); +#endif + +} +#endif + +#ifdef CONFIG_LAYER2_ROAMING +/* +* Select a new roaming candidate from the original @param candidate and @param competitor +* @return _TRUE: candidate is updated +* @return _FALSE: candidate is not updated +*/ +static int rtw_check_roaming_candidate(struct mlme_priv *mlme + , struct wlan_network **candidate, struct wlan_network *competitor) +{ + int updated = _FALSE; + _adapter *adapter = container_of(mlme, _adapter, mlmepriv); + + if(is_same_ess(&competitor->network, &mlme->cur_network.network) == _FALSE) + goto exit; + + if(rtw_is_desired_network(adapter, competitor) == _FALSE) + goto exit; + + DBG_871X("roam candidate:%s %s("MAC_FMT", ch%3u) rssi:%d, age:%5d\n", + (competitor == mlme->cur_network_scanned)?"*":" " , + competitor->network.Ssid.Ssid, + MAC_ARG(competitor->network.MacAddress), + competitor->network.Configuration.DSConfig, + (int)competitor->network.Rssi, + rtw_get_passing_time_ms(competitor->last_scanned) + ); + + /* got specific addr to roam */ + if (!is_zero_mac_addr(mlme->roam_tgt_addr)) { + if(_rtw_memcmp(mlme->roam_tgt_addr, competitor->network.MacAddress, ETH_ALEN) == _TRUE) + goto update; + else + goto exit; + } + #if 1 + if(rtw_get_passing_time_ms((u32)competitor->last_scanned) >= mlme->roam_scanr_exp_ms) + goto exit; + + if (competitor->network.Rssi - mlme->cur_network_scanned->network.Rssi < mlme->roam_rssi_diff_th) + goto exit; + + if(*candidate != NULL && (*candidate)->network.Rssi>=competitor->network.Rssi) + goto exit; + #else + goto exit; + #endif + +update: + *candidate = competitor; + updated = _TRUE; + +exit: + return updated; +} + +int rtw_select_roaming_candidate(struct mlme_priv *mlme) +{ + _irqL irqL; + int ret = _FAIL; + _list *phead; + _adapter *adapter; + _queue *queue = &(mlme->scanned_queue); + struct wlan_network *pnetwork = NULL; + struct wlan_network *candidate = NULL; + u8 bSupportAntDiv = _FALSE; + +_func_enter_; + + if (mlme->cur_network_scanned == NULL) { + rtw_warn_on(1); + goto exit; + } + + _enter_critical_bh(&(mlme->scanned_queue.lock), &irqL); + phead = get_list_head(queue); + adapter = (_adapter *)mlme->nic_hdl; + + mlme->pscanned = get_next(phead); + + while (!rtw_end_of_queue_search(phead, mlme->pscanned)) { + + pnetwork = LIST_CONTAINOR(mlme->pscanned, struct wlan_network, list); + if(pnetwork==NULL){ + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s return _FAIL:(pnetwork==NULL)\n", __FUNCTION__)); + ret = _FAIL; + goto exit; + } + + mlme->pscanned = get_next(mlme->pscanned); + + if (0) + DBG_871X("%s("MAC_FMT", ch%u) rssi:%d\n" + , pnetwork->network.Ssid.Ssid + , MAC_ARG(pnetwork->network.MacAddress) + , pnetwork->network.Configuration.DSConfig + , (int)pnetwork->network.Rssi); + + rtw_check_roaming_candidate(mlme, &candidate, pnetwork); + + } + + if(candidate == NULL) { + DBG_871X("%s: return _FAIL(candidate == NULL)\n", __FUNCTION__); + ret = _FAIL; + goto exit; + } else { + DBG_871X("%s: candidate: %s("MAC_FMT", ch:%u)\n", __FUNCTION__, + candidate->network.Ssid.Ssid, MAC_ARG(candidate->network.MacAddress), + candidate->network.Configuration.DSConfig); + + mlme->roam_network = candidate; + + if (_rtw_memcmp(candidate->network.MacAddress, mlme->roam_tgt_addr, ETH_ALEN) == _TRUE) + _rtw_memset(mlme->roam_tgt_addr,0, ETH_ALEN); + } + + ret = _SUCCESS; +exit: + _exit_critical_bh(&(mlme->scanned_queue.lock), &irqL); + + return ret; +} +#endif /* CONFIG_LAYER2_ROAMING */ + +/* +* Select a new join candidate from the original @param candidate and @param competitor +* @return _TRUE: candidate is updated +* @return _FALSE: candidate is not updated +*/ +static int rtw_check_join_candidate(struct mlme_priv *mlme + , struct wlan_network **candidate, struct wlan_network *competitor) +{ + int updated = _FALSE; + _adapter *adapter = container_of(mlme, _adapter, mlmepriv); + + + //check bssid, if needed + if(mlme->assoc_by_bssid==_TRUE) { + if(_rtw_memcmp(competitor->network.MacAddress, mlme->assoc_bssid, ETH_ALEN) ==_FALSE) + goto exit; + } + + //check ssid, if needed + if(mlme->assoc_ssid.Ssid[0] && mlme->assoc_ssid.SsidLength) { + if( competitor->network.Ssid.SsidLength != mlme->assoc_ssid.SsidLength + || _rtw_memcmp(competitor->network.Ssid.Ssid, mlme->assoc_ssid.Ssid, mlme->assoc_ssid.SsidLength) == _FALSE + ) + goto exit; + } + + if(rtw_is_desired_network(adapter, competitor) == _FALSE) + goto exit; + +#ifdef CONFIG_LAYER2_ROAMING + if(rtw_to_roam(adapter) > 0) { + if( rtw_get_passing_time_ms((u32)competitor->last_scanned) >= mlme->roam_scanr_exp_ms + || is_same_ess(&competitor->network, &mlme->cur_network.network) == _FALSE + ) + goto exit; + } +#endif + + if(*candidate == NULL ||(*candidate)->network.Rssinetwork.Rssi ) + { + *candidate = competitor; + updated = _TRUE; + } + + if(updated){ + DBG_871X("[by_bssid:%u][assoc_ssid:%s][to_roam:%u] " + "new candidate: %s("MAC_FMT", ch%u) rssi:%d\n", + mlme->assoc_by_bssid, + mlme->assoc_ssid.Ssid, + rtw_to_roam(adapter), + (*candidate)->network.Ssid.Ssid, + MAC_ARG((*candidate)->network.MacAddress), + (*candidate)->network.Configuration.DSConfig, + (int)(*candidate)->network.Rssi + ); + } + +exit: + return updated; +} + +/* +Calling context: +The caller of the sub-routine will be in critical section... + +The caller must hold the following spinlock + +pmlmepriv->lock + + +*/ + +int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv ) +{ + _irqL irqL; + int ret; + _list *phead; + _adapter *adapter; + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + struct wlan_network *candidate = NULL; + u8 bSupportAntDiv = _FALSE; + +_func_enter_; + + adapter = (_adapter *)pmlmepriv->nic_hdl; + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + #ifdef CONFIG_LAYER2_ROAMING + if (pmlmepriv->roam_network) { + candidate = pmlmepriv->roam_network; + pmlmepriv->roam_network = NULL; + goto candidate_exist; + } + #endif + + phead = get_list_head(queue); + pmlmepriv->pscanned = get_next(phead); + + while (!rtw_end_of_queue_search(phead, pmlmepriv->pscanned)) { + + pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list); + if(pnetwork==NULL){ + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s return _FAIL:(pnetwork==NULL)\n", __FUNCTION__)); + ret = _FAIL; + goto exit; + } + + pmlmepriv->pscanned = get_next(pmlmepriv->pscanned); + + if (0) + DBG_871X("%s("MAC_FMT", ch%u) rssi:%d\n" + , pnetwork->network.Ssid.Ssid + , MAC_ARG(pnetwork->network.MacAddress) + , pnetwork->network.Configuration.DSConfig + , (int)pnetwork->network.Rssi); + + rtw_check_join_candidate(pmlmepriv, &candidate, pnetwork); + + } + + if(candidate == NULL) { + DBG_871X("%s: return _FAIL(candidate == NULL)\n", __FUNCTION__); + ret = _FAIL; + goto exit; + } else { + DBG_871X("%s: candidate: %s("MAC_FMT", ch:%u)\n", __FUNCTION__, + candidate->network.Ssid.Ssid, MAC_ARG(candidate->network.MacAddress), + candidate->network.Configuration.DSConfig); + goto candidate_exist; + } + +candidate_exist: + + // check for situation of _FW_LINKED + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + { + DBG_871X("%s: _FW_LINKED while ask_for_joinbss!!!\n", __FUNCTION__); + + #if 0 // for WPA/WPA2 authentication, wpa_supplicant will expect authentication from AP, it is needed to reconnect AP... + if(is_same_network(&pmlmepriv->cur_network.network, &candidate->network)) + { + DBG_871X("%s: _FW_LINKED and is same network, it needn't join again\n", __FUNCTION__); + + rtw_indicate_connect(adapter);//rtw_indicate_connect again + + ret = 2; + goto exit; + } + else + #endif + { + rtw_disassoc_cmd(adapter, 0, _TRUE); + rtw_indicate_disconnect(adapter, 0, _FALSE); + rtw_free_assoc_resources(adapter, 0); + } + } + + #ifdef CONFIG_ANTENNA_DIVERSITY + rtw_hal_get_def_var(adapter, HAL_DEF_IS_SUPPORT_ANT_DIV, &(bSupportAntDiv)); + if(_TRUE == bSupportAntDiv) + { + u8 CurrentAntenna; + rtw_hal_get_odm_var(adapter, HAL_ODM_ANTDIV_SELECT, &(CurrentAntenna), NULL); + DBG_871X("#### Opt_Ant_(%s) , cur_Ant(%s)\n", + (MAIN_ANT == candidate->network.PhyInfo.Optimum_antenna) ? "MAIN_ANT":"AUX_ANT", + (MAIN_ANT == CurrentAntenna) ? "MAIN_ANT":"AUX_ANT" + ); + } + #endif + set_fwstate(pmlmepriv, _FW_UNDER_LINKING); + ret = rtw_joinbss_cmd(adapter, candidate); + +exit: + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + +_func_exit_; + + return ret; +} + +sint rtw_set_auth(_adapter * adapter,struct security_priv *psecuritypriv) +{ + struct cmd_obj* pcmd; + struct setauth_parm *psetauthparm; + struct cmd_priv *pcmdpriv=&(adapter->cmdpriv); + sint res=_SUCCESS; + +_func_enter_; + + pcmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(pcmd==NULL){ + res= _FAIL; //try again + goto exit; + } + + psetauthparm=(struct setauth_parm*)rtw_zmalloc(sizeof(struct setauth_parm)); + if(psetauthparm==NULL){ + rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj)); + res= _FAIL; + goto exit; + } + + _rtw_memset(psetauthparm, 0, sizeof(struct setauth_parm)); + psetauthparm->mode=(unsigned char)psecuritypriv->dot11AuthAlgrthm; + + pcmd->cmdcode = _SetAuth_CMD_; + pcmd->parmbuf = (unsigned char *)psetauthparm; + pcmd->cmdsz = (sizeof(struct setauth_parm)); + pcmd->rsp = NULL; + pcmd->rspsz = 0; + + + _rtw_init_listhead(&pcmd->list); + + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("after enqueue set_auth_cmd, auth_mode=%x\n", psecuritypriv->dot11AuthAlgrthm)); + + res = rtw_enqueue_cmd(pcmdpriv, pcmd); + +exit: + +_func_exit_; + + return res; + +} + + +sint rtw_set_key(_adapter * adapter,struct security_priv *psecuritypriv,sint keyid, u8 set_tx, bool enqueue) +{ + u8 keylen; + struct cmd_obj *pcmd; + struct setkey_parm *psetkeyparm; + struct cmd_priv *pcmdpriv = &(adapter->cmdpriv); + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + sint res=_SUCCESS; + +_func_enter_; + + psetkeyparm=(struct setkey_parm*)rtw_zmalloc(sizeof(struct setkey_parm)); + if(psetkeyparm==NULL){ + res= _FAIL; + goto exit; + } + _rtw_memset(psetkeyparm, 0, sizeof(struct setkey_parm)); + + if(psecuritypriv->dot11AuthAlgrthm ==dot11AuthAlgrthm_8021X){ + psetkeyparm->algorithm=(unsigned char)psecuritypriv->dot118021XGrpPrivacy; + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n rtw_set_key: psetkeyparm->algorithm=(unsigned char)psecuritypriv->dot118021XGrpPrivacy=%d \n", psetkeyparm->algorithm)); + } + else{ + psetkeyparm->algorithm=(u8)psecuritypriv->dot11PrivacyAlgrthm; + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n rtw_set_key: psetkeyparm->algorithm=(u8)psecuritypriv->dot11PrivacyAlgrthm=%d \n", psetkeyparm->algorithm)); + + } + psetkeyparm->keyid = (u8)keyid;//0~3 + psetkeyparm->set_tx = set_tx; + if (is_wep_enc(psetkeyparm->algorithm)) + adapter->securitypriv.key_mask |= BIT(psetkeyparm->keyid); + + DBG_871X("==> rtw_set_key algorithm(%x),keyid(%x),key_mask(%x)\n",psetkeyparm->algorithm,psetkeyparm->keyid, adapter->securitypriv.key_mask); + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n rtw_set_key: psetkeyparm->algorithm=%d psetkeyparm->keyid=(u8)keyid=%d \n",psetkeyparm->algorithm, keyid)); + + switch(psetkeyparm->algorithm){ + + case _WEP40_: + keylen=5; + _rtw_memcpy(&(psetkeyparm->key[0]), &(psecuritypriv->dot11DefKey[keyid].skey[0]), keylen); + break; + case _WEP104_: + keylen=13; + _rtw_memcpy(&(psetkeyparm->key[0]), &(psecuritypriv->dot11DefKey[keyid].skey[0]), keylen); + break; + case _TKIP_: + keylen=16; + _rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot118021XGrpKey[keyid], keylen); + psetkeyparm->grpkey=1; + break; + case _AES_: + keylen=16; + _rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot118021XGrpKey[keyid], keylen); + psetkeyparm->grpkey=1; + break; + default: + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n rtw_set_key:psecuritypriv->dot11PrivacyAlgrthm = %x (must be 1 or 2 or 4 or 5)\n",psecuritypriv->dot11PrivacyAlgrthm)); + res= _FAIL; + rtw_mfree((unsigned char *)psetkeyparm, sizeof(struct setkey_parm)); + goto exit; + } + + + if(enqueue){ + pcmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(pcmd==NULL){ + rtw_mfree((unsigned char *)psetkeyparm, sizeof(struct setkey_parm)); + res= _FAIL; //try again + goto exit; + } + + pcmd->cmdcode = _SetKey_CMD_; + pcmd->parmbuf = (u8 *)psetkeyparm; + pcmd->cmdsz = (sizeof(struct setkey_parm)); + pcmd->rsp = NULL; + pcmd->rspsz = 0; + + _rtw_init_listhead(&pcmd->list); + + //_rtw_init_sema(&(pcmd->cmd_sem), 0); + + res = rtw_enqueue_cmd(pcmdpriv, pcmd); + } + else{ + setkey_hdl(adapter, (u8 *)psetkeyparm); + rtw_mfree((u8 *) psetkeyparm, sizeof(struct setkey_parm)); + } +exit: +_func_exit_; + return res; + +} + + +//adjust IEs for rtw_joinbss_cmd in WMM +int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, uint initial_out_len) +{ + unsigned int ielength=0; + unsigned int i, j; + + i = 12; //after the fixed IE + while(i=0 :if there is pre-auth key, and return the entry id +// +// + +static int SecIsInPMKIDList(_adapter *Adapter, u8 *bssid) +{ + struct security_priv *psecuritypriv=&Adapter->securitypriv; + int i=0; + + do + { + if( ( psecuritypriv->PMKIDList[i].bUsed ) && + ( _rtw_memcmp( psecuritypriv->PMKIDList[i].Bssid, bssid, ETH_ALEN ) == _TRUE ) ) + { + break; + } + else + { + i++; + //continue; + } + + }while(isecuritypriv; + + if (ie[13] > 20) { + int i; + u16 pmkid_cnt = RTW_GET_LE16(ie+14+20); + if (pmkid_cnt == 1 && _rtw_memcmp(ie+14+20+2, &sec->PMKIDList[iEntry].PMKID, 16)) { + DBG_871X(FUNC_ADPT_FMT" has carried the same PMKID:"KEY_FMT"\n" + , FUNC_ADPT_ARG(adapter), KEY_ARG(&sec->PMKIDList[iEntry].PMKID)); + goto exit; + } + + DBG_871X(FUNC_ADPT_FMT" remove original PMKID, count:%u\n" + , FUNC_ADPT_ARG(adapter), pmkid_cnt); + + for (i=0;iPMKIDList[iEntry].PMKID)); + + RTW_PUT_LE16(&ie[ie_len], 1); + ie_len += 2; + + _rtw_memcpy(&ie[ie_len], &sec->PMKIDList[iEntry].PMKID, 16); + ie_len += 16; + + ie[13] += 18;//PMKID length = 2+16 + } + +exit: + return (ie_len); +} + +static int rtw_remove_pmkid(_adapter *adapter, u8 *ie, uint ie_len) +{ + struct security_priv *sec=&adapter->securitypriv; + int i; + u16 pmkid_cnt = RTW_GET_LE16(ie+14+20); + + if (ie[13] <= 20) + goto exit; + + DBG_871X(FUNC_ADPT_FMT" remove original PMKID, count:%u\n" + , FUNC_ADPT_ARG(adapter), pmkid_cnt); + + for (i=0;imlmepriv; + struct security_priv *psecuritypriv=&adapter->securitypriv; + uint ndisauthmode=psecuritypriv->ndisauthtype; + uint ndissecuritytype = psecuritypriv->ndisencryptstatus; + +_func_enter_; + + RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, + ("+rtw_restruct_sec_ie: ndisauthmode=%d ndissecuritytype=%d\n", + ndisauthmode, ndissecuritytype)); + + //copy fixed ie only + _rtw_memcpy(out_ie, in_ie,12); + ielength=12; + if((ndisauthmode==Ndis802_11AuthModeWPA)||(ndisauthmode==Ndis802_11AuthModeWPAPSK)) + authmode=_WPA_IE_ID_; + if((ndisauthmode==Ndis802_11AuthModeWPA2)||(ndisauthmode==Ndis802_11AuthModeWPA2PSK)) + authmode=_WPA2_IE_ID_; + + if(check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) + { + _rtw_memcpy(out_ie+ielength, psecuritypriv->wps_ie, psecuritypriv->wps_ie_len); + + ielength += psecuritypriv->wps_ie_len; + } + else if((authmode==_WPA_IE_ID_)||(authmode==_WPA2_IE_ID_)) + { + //copy RSN or SSN + _rtw_memcpy(&out_ie[ielength], &psecuritypriv->supplicant_ie[0], psecuritypriv->supplicant_ie[1]+2); + /* debug for CONFIG_IEEE80211W + { + int jj; + printk("supplicant_ie_length=%d &&&&&&&&&&&&&&&&&&&\n", psecuritypriv->supplicant_ie[1]+2); + for(jj=0; jj < psecuritypriv->supplicant_ie[1]+2; jj++) + printk(" %02x ", psecuritypriv->supplicant_ie[jj]); + printk("\n"); + }*/ + ielength+=psecuritypriv->supplicant_ie[1]+2; + rtw_report_sec_ie(adapter, authmode, psecuritypriv->supplicant_ie); + +#ifdef CONFIG_DRVEXT_MODULE + drvext_report_sec_ie(&adapter->drvextpriv, authmode, sec_ie); +#endif + } + + iEntry = SecIsInPMKIDList(adapter, pmlmepriv->assoc_bssid); + if(iEntry<0) + { + if(authmode == _WPA2_IE_ID_) + ielength = rtw_remove_pmkid(adapter, out_ie, ielength); + } + else + { + if(authmode == _WPA2_IE_ID_) + ielength=rtw_append_pmkid(adapter, iEntry, out_ie, ielength); + } + +_func_exit_; + + return ielength; +} + +void rtw_init_registrypriv_dev_network( _adapter* adapter) +{ + struct registry_priv* pregistrypriv = &adapter->registrypriv; + WLAN_BSSID_EX *pdev_network = &pregistrypriv->dev_network; + u8 *myhwaddr = adapter_mac_addr(adapter); + +_func_enter_; + + _rtw_memcpy(pdev_network->MacAddress, myhwaddr, ETH_ALEN); + + _rtw_memcpy(&pdev_network->Ssid, &pregistrypriv->ssid, sizeof(NDIS_802_11_SSID)); + + pdev_network->Configuration.Length=sizeof(NDIS_802_11_CONFIGURATION); + pdev_network->Configuration.BeaconPeriod = 100; + pdev_network->Configuration.FHConfig.Length = 0; + pdev_network->Configuration.FHConfig.HopPattern = 0; + pdev_network->Configuration.FHConfig.HopSet = 0; + pdev_network->Configuration.FHConfig.DwellTime = 0; + + +_func_exit_; + +} + +void rtw_update_registrypriv_dev_network(_adapter* adapter) +{ + int sz=0; + struct registry_priv* pregistrypriv = &adapter->registrypriv; + WLAN_BSSID_EX *pdev_network = &pregistrypriv->dev_network; + struct security_priv* psecuritypriv = &adapter->securitypriv; + struct wlan_network *cur_network = &adapter->mlmepriv.cur_network; + //struct xmit_priv *pxmitpriv = &adapter->xmitpriv; + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + +_func_enter_; + +#if 0 + pxmitpriv->vcs_setting = pregistrypriv->vrtl_carrier_sense; + pxmitpriv->vcs = pregistrypriv->vcs_type; + pxmitpriv->vcs_type = pregistrypriv->vcs_type; + //pxmitpriv->rts_thresh = pregistrypriv->rts_thresh; + pxmitpriv->frag_len = pregistrypriv->frag_thresh; + + adapter->qospriv.qos_option = pregistrypriv->wmm_enable; +#endif + + pdev_network->Privacy = (psecuritypriv->dot11PrivacyAlgrthm > 0 ? 1 : 0) ; // adhoc no 802.1x + + pdev_network->Rssi = 0; + + switch(pregistrypriv->wireless_mode) + { + case WIRELESS_11B: + pdev_network->NetworkTypeInUse = (Ndis802_11DS); + break; + case WIRELESS_11G: + case WIRELESS_11BG: + case WIRELESS_11_24N: + case WIRELESS_11G_24N: + case WIRELESS_11BG_24N: + pdev_network->NetworkTypeInUse = (Ndis802_11OFDM24); + break; + case WIRELESS_11A: + case WIRELESS_11A_5N: + pdev_network->NetworkTypeInUse = (Ndis802_11OFDM5); + break; + case WIRELESS_11ABGN: + if(pregistrypriv->channel > 14) + pdev_network->NetworkTypeInUse = (Ndis802_11OFDM5); + else + pdev_network->NetworkTypeInUse = (Ndis802_11OFDM24); + break; + default : + // TODO + break; + } + + pdev_network->Configuration.DSConfig = (pregistrypriv->channel); + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("pregistrypriv->channel=%d, pdev_network->Configuration.DSConfig=0x%x\n", pregistrypriv->channel, pdev_network->Configuration.DSConfig)); + + if (cur_network->network.InfrastructureMode == Ndis802_11IBSS) { + pdev_network->Configuration.ATIMWindow = (0); + + if (pmlmeext->cur_channel != 0) + pdev_network->Configuration.DSConfig = pmlmeext->cur_channel; + else + pdev_network->Configuration.DSConfig = 1; + } + + pdev_network->InfrastructureMode = (cur_network->network.InfrastructureMode); + + // 1. Supported rates + // 2. IE + + //rtw_set_supported_rate(pdev_network->SupportedRates, pregistrypriv->wireless_mode) ; // will be called in rtw_generate_ie + sz = rtw_generate_ie(pregistrypriv); + + pdev_network->IELength = sz; + + pdev_network->Length = get_WLAN_BSSID_EX_sz((WLAN_BSSID_EX *)pdev_network); + + //notes: translate IELength & Length after assign the Length to cmdsz in createbss_cmd(); + //pdev_network->IELength = cpu_to_le32(sz); + +_func_exit_; + +} + +void rtw_get_encrypt_decrypt_from_registrypriv(_adapter* adapter) +{ +_func_enter_; + + +_func_exit_; + +} + +//the fucntion is at passive_level +void rtw_joinbss_reset(_adapter *padapter) +{ + u8 threshold; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + //todo: if you want to do something io/reg/hw setting before join_bss, please add code here + +#ifdef CONFIG_80211N_HT + struct ht_priv *phtpriv = &pmlmepriv->htpriv; + + pmlmepriv->num_FortyMHzIntolerant = 0; + + pmlmepriv->num_sta_no_ht = 0; + + phtpriv->ampdu_enable = _FALSE;//reset to disabled + +#if defined( CONFIG_USB_HCI) || defined (CONFIG_SDIO_HCI) + // TH=1 => means that invalidate usb rx aggregation + // TH=0 => means that validate usb rx aggregation, use init value. + if(phtpriv->ht_option) + { + if(padapter->registrypriv.wifi_spec==1) + threshold = 1; + else + threshold = 0; + rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold)); + } + else + { + threshold = 1; + rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold)); + } +#endif//#if defined( CONFIG_USB_HCI) || defined (CONFIG_SDIO_HCI) + +#endif//#ifdef CONFIG_80211N_HT + +} + + +#ifdef CONFIG_80211N_HT +void rtw_ht_use_default_setting(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct ht_priv *phtpriv = &pmlmepriv->htpriv; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + BOOLEAN bHwLDPCSupport = _FALSE, bHwSTBCSupport = _FALSE; + BOOLEAN bHwSupportBeamformer = _FALSE, bHwSupportBeamformee = _FALSE; + + if (pregistrypriv->wifi_spec) + phtpriv->bss_coexist = 1; + else + phtpriv->bss_coexist = 0; + + phtpriv->sgi_40m = TEST_FLAG(pregistrypriv->short_gi, BIT1) ? _TRUE : _FALSE; + phtpriv->sgi_20m = TEST_FLAG(pregistrypriv->short_gi, BIT0) ? _TRUE : _FALSE; + + // LDPC support + rtw_hal_get_def_var(padapter, HAL_DEF_RX_LDPC, (u8 *)&bHwLDPCSupport); + CLEAR_FLAGS(phtpriv->ldpc_cap); + if(bHwLDPCSupport) + { + if(TEST_FLAG(pregistrypriv->ldpc_cap, BIT4)) + SET_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX); + } + rtw_hal_get_def_var(padapter, HAL_DEF_TX_LDPC, (u8 *)&bHwLDPCSupport); + if(bHwLDPCSupport) + { + if(TEST_FLAG(pregistrypriv->ldpc_cap, BIT5)) + SET_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX); + } + if (phtpriv->ldpc_cap) + DBG_871X("[HT] HAL Support LDPC = 0x%02X\n", phtpriv->ldpc_cap); + + // STBC + rtw_hal_get_def_var(padapter, HAL_DEF_TX_STBC, (u8 *)&bHwSTBCSupport); + CLEAR_FLAGS(phtpriv->stbc_cap); + if(bHwSTBCSupport) + { + if(TEST_FLAG(pregistrypriv->stbc_cap, BIT5)) + SET_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX); + } + rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)&bHwSTBCSupport); + if(bHwSTBCSupport) + { + if(TEST_FLAG(pregistrypriv->stbc_cap, BIT4)) + SET_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX); + } + if (phtpriv->stbc_cap) + DBG_871X("[HT] HAL Support STBC = 0x%02X\n", phtpriv->stbc_cap); + + // Beamforming setting + rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER, (u8 *)&bHwSupportBeamformer); + rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE, (u8 *)&bHwSupportBeamformee); + CLEAR_FLAGS(phtpriv->beamform_cap); + if(TEST_FLAG(pregistrypriv->beamform_cap, BIT4) && bHwSupportBeamformer) + { + SET_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE); + DBG_871X("[HT] HAL Support Beamformer\n"); + } + if(TEST_FLAG(pregistrypriv->beamform_cap, BIT5) && bHwSupportBeamformee) + { + SET_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE); + DBG_871X("[HT] HAL Support Beamformee\n"); + } +} +void rtw_build_wmm_ie_ht(_adapter *padapter, u8 *out_ie, uint *pout_len) +{ + unsigned char WMM_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01, 0x00}; + int out_len; + u8 *pframe; + + if(padapter->mlmepriv.qospriv.qos_option == 0) + { + out_len = *pout_len; + pframe = rtw_set_ie(out_ie+out_len, _VENDOR_SPECIFIC_IE_, + _WMM_IE_Length_, WMM_IE, pout_len); + + padapter->mlmepriv.qospriv.qos_option = 1; + } +} + +/* the fucntion is >= passive_level */ +unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, u8 channel) +{ + u32 ielen, out_len; + u32 rx_packet_offset, max_recvbuf_sz; + HT_CAP_AMPDU_FACTOR max_rx_ampdu_factor; + HT_CAP_AMPDU_DENSITY best_ampdu_density; + unsigned char *p, *pframe; + struct rtw_ieee80211_ht_cap ht_capie; + u8 cbw40_enable = 0, rf_type = 0, operation_bw = 0, rf_num = 0, rx_stbc_nss = 0; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct ht_priv *phtpriv = &pmlmepriv->htpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + phtpriv->ht_option = _FALSE; + + out_len = *pout_len; + + _rtw_memset(&ht_capie, 0, sizeof(struct rtw_ieee80211_ht_cap)); + + ht_capie.cap_info = IEEE80211_HT_CAP_DSSSCCK40; + + if (phtpriv->sgi_20m) + ht_capie.cap_info |= IEEE80211_HT_CAP_SGI_20; + + /* Get HT BW */ + if (in_ie == NULL) { + /* TDLS: TODO 20/40 issue */ + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { + operation_bw = padapter->mlmeextpriv.cur_bwmode; + if (operation_bw > CHANNEL_WIDTH_40) + operation_bw = CHANNEL_WIDTH_40; + } else + /* TDLS: TODO 40? */ + operation_bw = CHANNEL_WIDTH_40; + } else { + p = rtw_get_ie(in_ie, _HT_ADD_INFO_IE_, &ielen, in_len); + if (p && (ielen == sizeof(struct ieee80211_ht_addt_info))) { + struct HT_info_element *pht_info = (struct HT_info_element *)(p+2); + if (pht_info->infos[0] & BIT(2)) { + switch (pht_info->infos[0] & 0x3) { + case 1: + case 3: + operation_bw = CHANNEL_WIDTH_40; + break; + default: + operation_bw = CHANNEL_WIDTH_20; + break; + } + } else { + operation_bw = CHANNEL_WIDTH_20; + } + } + } + + /* to disable 40M Hz support while gd_bw_40MHz_en = 0 */ + if (hal_chk_bw_cap(padapter, BW_CAP_40M)) { + if (channel > 14) { + if (REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40)) + cbw40_enable = 1; + } else { + if (REGSTY_IS_BW_2G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40)) + cbw40_enable = 1; + } + } + + if ((cbw40_enable == 1) && (operation_bw == CHANNEL_WIDTH_40)) { + ht_capie.cap_info |= IEEE80211_HT_CAP_SUP_WIDTH; + if (phtpriv->sgi_40m) + ht_capie.cap_info |= IEEE80211_HT_CAP_SGI_40; + } + + /* todo: disable SM power save mode */ + ht_capie.cap_info |= IEEE80211_HT_CAP_SM_PS; + + /* RX LDPC */ + if (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX)) { + ht_capie.cap_info |= IEEE80211_HT_CAP_LDPC_CODING; + DBG_871X("[HT] Declare supporting RX LDPC\n"); + } + + /* TX STBC */ + if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX)) { + ht_capie.cap_info |= IEEE80211_HT_CAP_TX_STBC; + DBG_871X("[HT] Declare supporting TX STBC\n"); + } + + /* RX STBC */ + if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX)) { + if((pregistrypriv->rx_stbc == 0x3) || /* enable for 2.4/5 GHz */ + ((channel <= 14) && (pregistrypriv->rx_stbc == 0x1)) || /* enable for 2.4GHz */ + ((channel > 14) && (pregistrypriv->rx_stbc == 0x2)) || /* enable for 5GHz */ + (pregistrypriv->wifi_spec == 1)) { + /* HAL_DEF_RX_STBC means STBC RX spatial stream, todo: VHT 4 streams */ + rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)(&rx_stbc_nss)); + SET_HT_CAP_ELE_RX_STBC(&ht_capie, rx_stbc_nss); + DBG_871X("[HT] Declare supporting RX STBC = %d\n", rx_stbc_nss); + } + } + + //fill default supported_mcs_set + _rtw_memcpy(ht_capie.supp_mcs_set, pmlmeext->default_supported_mcs_set, 16); + + //update default supported_mcs_set + rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + + switch(rf_type) + { + case RF_1T1R: + set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_1R); + break; + + case RF_2T2R: + case RF_1T2R: + #ifdef CONFIG_DISABLE_MCS13TO15 + if(((cbw40_enable == 1) && (operation_bw == CHANNEL_WIDTH_40)) && (pregistrypriv->wifi_spec!=1)) + set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_2R_13TO15_OFF); + else + set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_2R); + #else //CONFIG_DISABLE_MCS13TO15 + set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_2R); + #endif //CONFIG_DISABLE_MCS13TO15 + break; + case RF_3T3R: + set_mcs_rate_by_mask(ht_capie.supp_mcs_set, MCS_RATE_3R); + break; + default: + DBG_871X("[warning] rf_type %d is not expected\n", rf_type); + } + + { + u32 rx_packet_offset, max_recvbuf_sz; + rtw_hal_get_def_var(padapter, HAL_DEF_RX_PACKET_OFFSET, &rx_packet_offset); + rtw_hal_get_def_var(padapter, HAL_DEF_MAX_RECVBUF_SZ, &max_recvbuf_sz); + if (max_recvbuf_sz-rx_packet_offset >= (8191-256)) { + DBG_871X("%s IEEE80211_HT_CAP_MAX_AMSDU is set\n", __FUNCTION__); + ht_capie.cap_info = ht_capie.cap_info | IEEE80211_HT_CAP_MAX_AMSDU; + } + } + /* + AMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k + AMPDU_para [4:2]:Min MPDU Start Spacing + */ + + /* + #if defined(CONFIG_RTL8188E )&& defined (CONFIG_SDIO_HCI) + ht_capie.ampdu_params_info = 2; + #else + ht_capie.ampdu_params_info = (IEEE80211_HT_CAP_AMPDU_FACTOR&0x03); + #endif + */ + + if(padapter->driver_rx_ampdu_factor != 0xFF) + max_rx_ampdu_factor = (HT_CAP_AMPDU_FACTOR)padapter->driver_rx_ampdu_factor; + else + rtw_hal_get_def_var(padapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor); + + //rtw_hal_get_def_var(padapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor); + ht_capie.ampdu_params_info = (max_rx_ampdu_factor&0x03); + + if(padapter->driver_rx_ampdu_spacing != 0xFF) + { + ht_capie.ampdu_params_info |= (( padapter->driver_rx_ampdu_spacing&0x07) <<2); + } + else + { + if (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_) { + /* + * Todo : Each chip must to ask DD , this chip best ampdu_density setting + * By yiwei.sun + */ + rtw_hal_get_def_var(padapter, HW_VAR_BEST_AMPDU_DENSITY, &best_ampdu_density); + + ht_capie.ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY & (best_ampdu_density << 2)); + + } else + ht_capie.ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY&0x00); + } +#ifdef CONFIG_BEAMFORMING + ht_capie.tx_BF_cap_info = 0; + + /* HT Beamformer*/ + if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE)) { + /* Transmit NDP Capable */ + SET_HT_CAP_TXBF_TRANSMIT_NDP_CAP(&ht_capie, 1); + /* Explicit Compressed Steering Capable */ + SET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(&ht_capie, 1); + /* Compressed Steering Number Antennas */ + SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(&ht_capie, 1); + rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&rf_num); + SET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(&ht_capie, rf_num); + } + + /* HT Beamformee */ + if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE)) { + /* Receive NDP Capable */ + SET_HT_CAP_TXBF_RECEIVE_NDP_CAP(&ht_capie, 1); + /* Explicit Compressed Beamforming Feedback Capable */ + SET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(&ht_capie, 2); + rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num); + SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(&ht_capie, rf_num); + } +#endif/*CONFIG_BEAMFORMING*/ + + pframe = rtw_set_ie(out_ie+out_len, _HT_CAPABILITY_IE_, + sizeof(struct rtw_ieee80211_ht_cap), (unsigned char*)&ht_capie, pout_len); + + phtpriv->ht_option = _TRUE; + + if(in_ie!=NULL) + { + p = rtw_get_ie(in_ie, _HT_ADD_INFO_IE_, &ielen, in_len); + if(p && (ielen==sizeof(struct ieee80211_ht_addt_info))) + { + out_len = *pout_len; + pframe = rtw_set_ie(out_ie+out_len, _HT_ADD_INFO_IE_, ielen, p+2 , pout_len); + } + } + + return (phtpriv->ht_option); + +} + +//the fucntion is > passive_level (in critical_section) +void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel) +{ + u8 *p, max_ampdu_sz; + int len; + //struct sta_info *bmc_sta, *psta; + struct rtw_ieee80211_ht_cap *pht_capie; + struct ieee80211_ht_addt_info *pht_addtinfo; + //struct recv_reorder_ctrl *preorder_ctrl; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct ht_priv *phtpriv = &pmlmepriv->htpriv; + //struct recv_priv *precvpriv = &padapter->recvpriv; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + //struct wlan_network *pcur_network = &(pmlmepriv->cur_network);; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 cbw40_enable=0; + + + if(!phtpriv->ht_option) + return; + + if ((!pmlmeinfo->HT_info_enable) || (!pmlmeinfo->HT_caps_enable)) + return; + + DBG_871X("+rtw_update_ht_cap()\n"); + + //maybe needs check if ap supports rx ampdu. + if((phtpriv->ampdu_enable==_FALSE) &&(pregistrypriv->ampdu_enable==1)) + { + if(pregistrypriv->wifi_spec==1) + { + //remove this part because testbed AP should disable RX AMPDU + //phtpriv->ampdu_enable = _FALSE; + phtpriv->ampdu_enable = _TRUE; + } + else + phtpriv->ampdu_enable = _TRUE; + } + + + //check Max Rx A-MPDU Size + len = 0; + p = rtw_get_ie(pie+sizeof (NDIS_802_11_FIXED_IEs), _HT_CAPABILITY_IE_, &len, ie_len-sizeof (NDIS_802_11_FIXED_IEs)); + if(p && len>0) + { + pht_capie = (struct rtw_ieee80211_ht_cap *)(p+2); + max_ampdu_sz = (pht_capie->ampdu_params_info & IEEE80211_HT_CAP_AMPDU_FACTOR); + max_ampdu_sz = 1 << (max_ampdu_sz+3); // max_ampdu_sz (kbytes); + + //DBG_871X("rtw_update_ht_cap(): max_ampdu_sz=%d\n", max_ampdu_sz); + phtpriv->rx_ampdu_maxlen = max_ampdu_sz; + + } + + + len=0; + p = rtw_get_ie(pie+sizeof (NDIS_802_11_FIXED_IEs), _HT_ADD_INFO_IE_, &len, ie_len-sizeof (NDIS_802_11_FIXED_IEs)); + if(p && len>0) + { + pht_addtinfo = (struct ieee80211_ht_addt_info *)(p+2); + //todo: + } + + if (hal_chk_bw_cap(padapter, BW_CAP_40M)) { + if (channel > 14) { + if (REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40)) + cbw40_enable = 1; + } else { + if (REGSTY_IS_BW_2G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40)) + cbw40_enable = 1; + } + } + + //update cur_bwmode & cur_ch_offset + if ((cbw40_enable) && + (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & BIT(1)) && + (pmlmeinfo->HT_info.infos[0] & BIT(2))) + { + int i; + u8 rf_type = RF_1T1R; + + rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + + //update the MCS set + for (i = 0; i < 16; i++) + pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= pmlmeext->default_supported_mcs_set[i]; + + //update the MCS rates + switch(rf_type) + { + case RF_1T1R: + case RF_1T2R: + set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_1R); + break; + case RF_2T2R: + #ifdef CONFIG_DISABLE_MCS13TO15 + if(pmlmeext->cur_bwmode == CHANNEL_WIDTH_40 && pregistrypriv->wifi_spec != 1 ) + set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R_13TO15_OFF); + else + set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R); +#else //CONFIG_DISABLE_MCS13TO15 + set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R); +#endif //CONFIG_DISABLE_MCS13TO15 + break; + case RF_3T3R: + set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_3R); + break; + default: + DBG_871X("[warning] rf_type %d is not expected\n", rf_type); + } + + //switch to the 40M Hz mode accoring to the AP + //pmlmeext->cur_bwmode = CHANNEL_WIDTH_40; + switch ((pmlmeinfo->HT_info.infos[0] & 0x3)) + { + case EXTCHNL_OFFSET_UPPER: + pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; + break; + + case EXTCHNL_OFFSET_LOWER: + pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; + break; + + default: + pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; + } + } + + // + // Config SM Power Save setting + // + pmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & 0x0C) >> 2; + if(pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC) + { + /*u8 i; + //update the MCS rates + for (i = 0; i < 16; i++) + { + pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i]; + }*/ + DBG_871X("%s(): WLAN_HT_CAP_SM_PS_STATIC\n",__FUNCTION__); + } + + // + // Config current HT Protection mode. + // + pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3; + + + +#if 0 //move to rtw_update_sta_info_client() + //for A-MPDU Rx reordering buffer control for bmc_sta & sta_info + //if A-MPDU Rx is enabled, reseting rx_ordering_ctrl wstart_b(indicate_seq) to default value=0xffff + //todo: check if AP can send A-MPDU packets + bmc_sta = rtw_get_bcmc_stainfo(padapter); + if(bmc_sta) + { + for(i=0; i < 16 ; i++) + { + //preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; + preorder_ctrl = &bmc_sta->recvreorder_ctrl[i]; + preorder_ctrl->enable = _FALSE; + preorder_ctrl->indicate_seq = 0xffff; + #ifdef DBG_RX_SEQ + DBG_871X("DBG_RX_SEQ %s:%d indicate_seq:%u \n", __FUNCTION__, __LINE__, + preorder_ctrl->indicate_seq); + #endif + preorder_ctrl->wend_b= 0xffff; + preorder_ctrl->wsize_b = 64;//max_ampdu_sz;//ex. 32(kbytes) -> wsize_b=32 + } + } + + psta = rtw_get_stainfo(&padapter->stapriv, pcur_network->network.MacAddress); + if(psta) + { + for(i=0; i < 16 ; i++) + { + //preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; + preorder_ctrl = &psta->recvreorder_ctrl[i]; + preorder_ctrl->enable = _FALSE; + preorder_ctrl->indicate_seq = 0xffff; + #ifdef DBG_RX_SEQ + DBG_871X("DBG_RX_SEQ %s:%d indicate_seq:%u \n", __FUNCTION__, __LINE__, + preorder_ctrl->indicate_seq); + #endif + preorder_ctrl->wend_b= 0xffff; + preorder_ctrl->wsize_b = 64;//max_ampdu_sz;//ex. 32(kbytes) -> wsize_b=32 + } + } +#endif + +} + +#ifdef CONFIG_TDLS +void rtw_issue_addbareq_cmd_tdls(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + struct pkt_attrib *pattrib =&pxmitframe->attrib; + struct sta_info *ptdls_sta = NULL; + u8 issued; + int priority; + struct ht_priv *phtpriv; + + priority = pattrib->priority; + + if (pattrib->direct_link == _TRUE) { + ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pattrib->dst); + if ((ptdls_sta != NULL) && (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)) { + phtpriv = &ptdls_sta->htpriv; + + if ((phtpriv->ht_option == _TRUE) && (phtpriv->ampdu_enable == _TRUE)) { + issued = (phtpriv->agg_enable_bitmap>>priority)&0x1; + issued |= (phtpriv->candidate_tid_bitmap>>priority)&0x1; + + if (0 == issued) { + DBG_871X("[%s], p=%d\n", __FUNCTION__, priority); + ptdls_sta->htpriv.candidate_tid_bitmap |= BIT((u8)priority); + rtw_addbareq_cmd(padapter,(u8)priority, pattrib->dst); + } + } + } + } +} +#endif //CONFIG_TDLS + +void rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + u8 issued; + int priority; + struct sta_info *psta=NULL; + struct ht_priv *phtpriv; + struct pkt_attrib *pattrib =&pxmitframe->attrib; + s32 bmcst = IS_MCAST(pattrib->ra); + + //if(bmcst || (padapter->mlmepriv.LinkDetectInfo.bTxBusyTraffic == _FALSE)) + if(bmcst || (padapter->mlmepriv.LinkDetectInfo.NumTxOkInPeriod<100)) + return; + + priority = pattrib->priority; + +#ifdef CONFIG_TDLS + rtw_issue_addbareq_cmd_tdls(padapter, pxmitframe); +#endif //CONFIG_TDLS + + psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); + if(pattrib->psta != psta) + { + DBG_871X("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta); + return; + } + + if(psta==NULL) + { + DBG_871X("%s, psta==NUL\n", __func__); + return; + } + + if(!(psta->state &_FW_LINKED)) + { + DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state); + return; + } + + + phtpriv = &psta->htpriv; + + if((phtpriv->ht_option==_TRUE) && (phtpriv->ampdu_enable==_TRUE)) + { + issued = (phtpriv->agg_enable_bitmap>>priority)&0x1; + issued |= (phtpriv->candidate_tid_bitmap>>priority)&0x1; + + if(0==issued) + { + DBG_871X("rtw_issue_addbareq_cmd, p=%d\n", priority); + psta->htpriv.candidate_tid_bitmap |= BIT((u8)priority); + rtw_addbareq_cmd(padapter,(u8) priority, pattrib->ra); + } + } + +} + +void rtw_append_exented_cap(_adapter *padapter, u8 *out_ie, uint *pout_len) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct ht_priv *phtpriv = &pmlmepriv->htpriv; +#ifdef CONFIG_80211AC_VHT + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; +#endif //CONFIG_80211AC_VHT + u8 cap_content[8] = { 0 }; + u8 *pframe; + u8 null_content[8] = {0}; + + if (phtpriv->bss_coexist) { + SET_EXT_CAPABILITY_ELE_BSS_COEXIST(cap_content, 1); + } + +#ifdef CONFIG_80211AC_VHT + if (pvhtpriv->vht_option) { + SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(cap_content, 1); + } +#endif //CONFIG_80211AC_VHT + /* + From 802.11 specification,if a STA does not support any of capabilities defined + in the Extended Capabilities element, then the STA is not required to + transmit the Extended Capabilities element. + */ + if (_FALSE == _rtw_memcmp(cap_content, null_content, 8)) + pframe = rtw_set_ie(out_ie + *pout_len, EID_EXTCapability, 8, cap_content , pout_len); +} +#endif + +#ifdef CONFIG_LAYER2_ROAMING +inline void rtw_set_to_roam(_adapter *adapter, u8 to_roam) +{ + if (to_roam == 0) + adapter->mlmepriv.to_join = _FALSE; + adapter->mlmepriv.to_roam = to_roam; +} + +inline u8 rtw_dec_to_roam(_adapter *adapter) +{ + adapter->mlmepriv.to_roam--; + return adapter->mlmepriv.to_roam; +} + +inline u8 rtw_to_roam(_adapter *adapter) +{ + return adapter->mlmepriv.to_roam; +} + +void rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network) +{ + _irqL irqL; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + _rtw_roaming(padapter, tgt_network); + _exit_critical_bh(&pmlmepriv->lock, &irqL); +} +void _rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wlan_network *cur_network = &pmlmepriv->cur_network; + int do_join_r; + + if(0 < rtw_to_roam(padapter)) { + DBG_871X("roaming from %s("MAC_FMT"), length:%d\n", + cur_network->network.Ssid.Ssid, MAC_ARG(cur_network->network.MacAddress), + cur_network->network.Ssid.SsidLength); + _rtw_memcpy(&pmlmepriv->assoc_ssid, &cur_network->network.Ssid, sizeof(NDIS_802_11_SSID)); + + pmlmepriv->assoc_by_bssid = _FALSE; + +#ifdef CONFIG_WAPI_SUPPORT + rtw_wapi_return_all_sta_info(padapter); +#endif + + while(1) { + if( _SUCCESS==(do_join_r=rtw_do_join(padapter)) ) { + break; + } else { + DBG_871X("roaming do_join return %d\n", do_join_r); + rtw_dec_to_roam(padapter); + + if(rtw_to_roam(padapter) > 0) { + continue; + } else { + DBG_871X("%s(%d) -to roaming fail, indicate_disconnect\n", __FUNCTION__,__LINE__); + rtw_indicate_disconnect(padapter, 0, _FALSE); + break; + } + } + } + } + +} +#endif /* CONFIG_LAYER2_ROAMING */ + +bool rtw_adjust_chbw(_adapter *adapter, u8 req_ch, u8 *req_bw, u8 *req_offset) +{ + struct registry_priv *regsty = adapter_to_regsty(adapter); + u8 allowed_bw; + + if (req_ch <= 14) + allowed_bw = REGSTY_BW_2G(regsty); + else + allowed_bw = REGSTY_BW_5G(regsty); + + allowed_bw = hal_largest_bw(adapter, allowed_bw); + + if (allowed_bw == CHANNEL_WIDTH_80 && *req_bw > CHANNEL_WIDTH_80) + *req_bw = CHANNEL_WIDTH_80; + else if (allowed_bw == CHANNEL_WIDTH_40 && *req_bw > CHANNEL_WIDTH_40) + *req_bw = CHANNEL_WIDTH_40; + else if (allowed_bw == CHANNEL_WIDTH_20 && *req_bw > CHANNEL_WIDTH_20) { + *req_bw = CHANNEL_WIDTH_20; + *req_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + } else + return _FALSE; + + return _TRUE; +} + +sint rtw_linked_check(_adapter *padapter) +{ + if( (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) || + (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == _TRUE)) + { + if(padapter->stapriv.asoc_sta_count > 2) + return _TRUE; + } + else + { //Station mode + if(check_fwstate(&padapter->mlmepriv, _FW_LINKED)== _TRUE) + return _TRUE; + } + return _FALSE; +} + +#ifdef CONFIG_CONCURRENT_MODE +sint rtw_buddy_adapter_up(_adapter *padapter) +{ + sint res = _FALSE; + + if(padapter == NULL) + return res; + + + if(padapter->pbuddy_adapter == NULL) + res = _FALSE; + else if (RTW_CANNOT_RUN(padapter) || + (padapter->pbuddy_adapter->bup == _FALSE) || (!rtw_is_hw_init_completed(padapter))) + res = _FALSE; + else + res = _TRUE; + + return res; + +} + +sint check_buddy_fwstate(_adapter *padapter, sint state) +{ + if(padapter == NULL) + return _FALSE; + + if(padapter->pbuddy_adapter == NULL) + return _FALSE; + + if ((state == WIFI_FW_NULL_STATE) && + (padapter->pbuddy_adapter->mlmepriv.fw_state == WIFI_FW_NULL_STATE)) + return _TRUE; + + if (padapter->pbuddy_adapter->mlmepriv.fw_state & state) + return _TRUE; + + return _FALSE; +} + +u8 rtw_get_buddy_bBusyTraffic(_adapter *padapter) +{ + if(padapter == NULL) + return _FALSE; + + if(padapter->pbuddy_adapter == NULL) + return _FALSE; + + return padapter->pbuddy_adapter->mlmepriv.LinkDetectInfo.bBusyTraffic; +} + +#endif //CONFIG_CONCURRENT_MODE + +bool is_miracast_enabled(_adapter *adapter) +{ + bool enabled = 0; +#ifdef CONFIG_WFD + struct wifi_display_info *wfdinfo = &adapter->wfd_info; + + enabled = (wfdinfo->stack_wfd_mode & (MIRACAST_SOURCE | MIRACAST_SINK)) + || (wfdinfo->op_wfd_mode & (MIRACAST_SOURCE | MIRACAST_SINK)); +#endif + + return enabled; +} + +bool rtw_chk_miracast_mode(_adapter *adapter, u8 mode) +{ + bool ret = 0; +#ifdef CONFIG_WFD + struct wifi_display_info *wfdinfo = &adapter->wfd_info; + + ret = (wfdinfo->stack_wfd_mode & mode) || (wfdinfo->op_wfd_mode & mode); +#endif + + return ret; +} + +const char *get_miracast_mode_str(int mode) +{ + if (mode == MIRACAST_SOURCE) + return "SOURCE"; + else if (mode == MIRACAST_SINK) + return "SINK"; + else if (mode == (MIRACAST_SOURCE | MIRACAST_SINK)) + return "SOURCE&SINK"; + else if (mode == MIRACAST_DISABLED) + return "DISABLED"; + else + return "INVALID"; +} + +#ifdef CONFIG_WFD +static bool wfd_st_match_rule(_adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port) +{ + struct wifi_display_info *wfdinfo = &adapter->wfd_info; + + if (ntohs(*((u16 *)local_port)) == wfdinfo->rtsp_ctrlport + || ntohs(*((u16 *)local_port)) == wfdinfo->tdls_rtsp_ctrlport + || ntohs(*((u16 *)remote_port)) == wfdinfo->peer_rtsp_ctrlport) + return _TRUE; + return _FALSE; +} + +static struct st_register wfd_st_reg = { + .s_proto = 0x06, + .rule = wfd_st_match_rule, +}; +#endif /* CONFIG_WFD */ + +inline void rtw_wfd_st_switch(struct sta_info *sta, bool on) +{ +#ifdef CONFIG_WFD + if (on) + rtw_st_ctl_register(&sta->st_ctl, SESSION_TRACKER_REG_ID_WFD, &wfd_st_reg); + else + rtw_st_ctl_unregister(&sta->st_ctl, SESSION_TRACKER_REG_ID_WFD); +#endif +} + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_mlme_ext.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_mlme_ext.c new file mode 100644 index 000000000..2137eb74c --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_mlme_ext.c @@ -0,0 +1,15622 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_MLME_EXT_C_ + +#include +#ifdef CONFIG_IOCTL_CFG80211 +#include +#endif //CONFIG_IOCTL_CFG80211 +#include + + +struct mlme_handler mlme_sta_tbl[]={ + {WIFI_ASSOCREQ, "OnAssocReq", &OnAssocReq}, + {WIFI_ASSOCRSP, "OnAssocRsp", &OnAssocRsp}, + {WIFI_REASSOCREQ, "OnReAssocReq", &OnAssocReq}, + {WIFI_REASSOCRSP, "OnReAssocRsp", &OnAssocRsp}, + {WIFI_PROBEREQ, "OnProbeReq", &OnProbeReq}, + {WIFI_PROBERSP, "OnProbeRsp", &OnProbeRsp}, + + /*---------------------------------------------------------- + below 2 are reserved + -----------------------------------------------------------*/ + {0, "DoReserved", &DoReserved}, + {0, "DoReserved", &DoReserved}, + {WIFI_BEACON, "OnBeacon", &OnBeacon}, + {WIFI_ATIM, "OnATIM", &OnAtim}, + {WIFI_DISASSOC, "OnDisassoc", &OnDisassoc}, + {WIFI_AUTH, "OnAuth", &OnAuthClient}, + {WIFI_DEAUTH, "OnDeAuth", &OnDeAuth}, + {WIFI_ACTION, "OnAction", &OnAction}, + {WIFI_ACTION_NOACK,"OnActionNoAck", &OnAction}, +}; + +#ifdef _CONFIG_NATIVEAP_MLME_ +struct mlme_handler mlme_ap_tbl[]={ + {WIFI_ASSOCREQ, "OnAssocReq", &OnAssocReq}, + {WIFI_ASSOCRSP, "OnAssocRsp", &OnAssocRsp}, + {WIFI_REASSOCREQ, "OnReAssocReq", &OnAssocReq}, + {WIFI_REASSOCRSP, "OnReAssocRsp", &OnAssocRsp}, + {WIFI_PROBEREQ, "OnProbeReq", &OnProbeReq}, + {WIFI_PROBERSP, "OnProbeRsp", &OnProbeRsp}, + + /*---------------------------------------------------------- + below 2 are reserved + -----------------------------------------------------------*/ + {0, "DoReserved", &DoReserved}, + {0, "DoReserved", &DoReserved}, + {WIFI_BEACON, "OnBeacon", &OnBeacon}, + {WIFI_ATIM, "OnATIM", &OnAtim}, + {WIFI_DISASSOC, "OnDisassoc", &OnDisassoc}, + {WIFI_AUTH, "OnAuth", &OnAuth}, + {WIFI_DEAUTH, "OnDeAuth", &OnDeAuth}, + {WIFI_ACTION, "OnAction", &OnAction}, + {WIFI_ACTION_NOACK,"OnActionNoAck", &OnAction}, +}; +#endif + +struct action_handler OnAction_tbl[]={ + {RTW_WLAN_CATEGORY_SPECTRUM_MGMT, "ACTION_SPECTRUM_MGMT", on_action_spct}, + {RTW_WLAN_CATEGORY_QOS, "ACTION_QOS", &OnAction_qos}, + {RTW_WLAN_CATEGORY_DLS, "ACTION_DLS", &OnAction_dls}, + {RTW_WLAN_CATEGORY_BACK, "ACTION_BACK", &OnAction_back}, + {RTW_WLAN_CATEGORY_PUBLIC, "ACTION_PUBLIC", on_action_public}, + {RTW_WLAN_CATEGORY_RADIO_MEASUREMENT, "ACTION_RADIO_MEASUREMENT", &DoReserved}, + {RTW_WLAN_CATEGORY_FT, "ACTION_FT", &DoReserved}, + {RTW_WLAN_CATEGORY_HT, "ACTION_HT", &OnAction_ht}, +#ifdef CONFIG_IEEE80211W + {RTW_WLAN_CATEGORY_SA_QUERY, "ACTION_SA_QUERY", &OnAction_sa_query}, +#else + {RTW_WLAN_CATEGORY_SA_QUERY, "ACTION_SA_QUERY", &DoReserved}, +#endif //CONFIG_IEEE80211W + //add for CONFIG_IEEE80211W + {RTW_WLAN_CATEGORY_UNPROTECTED_WNM, "ACTION_UNPROTECTED_WNM", &DoReserved}, + {RTW_WLAN_CATEGORY_SELF_PROTECTED, "ACTION_SELF_PROTECTED", &DoReserved}, + {RTW_WLAN_CATEGORY_WMM, "ACTION_WMM", &OnAction_wmm}, + {RTW_WLAN_CATEGORY_VHT, "ACTION_VHT", &OnAction_vht}, + {RTW_WLAN_CATEGORY_P2P, "ACTION_P2P", &OnAction_p2p}, +}; + + +u8 null_addr[ETH_ALEN]= {0,0,0,0,0,0}; + +/************************************************** +OUI definitions for the vendor specific IE +***************************************************/ +unsigned char RTW_WPA_OUI[] = {0x00, 0x50, 0xf2, 0x01}; +unsigned char WMM_OUI[] = {0x00, 0x50, 0xf2, 0x02}; +unsigned char WPS_OUI[] = {0x00, 0x50, 0xf2, 0x04}; +unsigned char P2P_OUI[] = {0x50,0x6F,0x9A,0x09}; +unsigned char WFD_OUI[] = {0x50,0x6F,0x9A,0x0A}; + +unsigned char WMM_INFO_OUI[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01}; +unsigned char WMM_PARA_OUI[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01}; + +unsigned char WPA_TKIP_CIPHER[4] = {0x00, 0x50, 0xf2, 0x02}; +unsigned char RSN_TKIP_CIPHER[4] = {0x00, 0x0f, 0xac, 0x02}; + +extern unsigned char REALTEK_96B_IE[]; + +#ifdef LEGACY_CHANNEL_PLAN_REF +/******************************************************** +ChannelPlan definitions +*********************************************************/ +static RT_CHANNEL_PLAN legacy_channel_plan[] = { + /* 0x00, RTW_CHPLAN_FCC */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165}, 32}, + /* 0x01, RTW_CHPLAN_IC */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 31}, + /* 0x02, RTW_CHPLAN_ETSI */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 32}, + /* 0x03, RTW_CHPLAN_SPAIN */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13}, + /* 0x04, RTW_CHPLAN_FRANCE */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13}, + /* 0x05, RTW_CHPLAN_MKK */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13}, + /* 0x06, RTW_CHPLAN_MKK1 */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13}, + /* 0x07, RTW_CHPLAN_ISRAEL */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48, 52, 56, 60, 64}, 21}, + /* 0x08, RTW_CHPLAN_TELEC */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 40, 44, 48, 52, 56, 60, 64}, 22}, + /* 0x09, RTW_CHPLAN_GLOBAL_DOAMIN */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14}, 14}, + /* 0x0A, RTW_CHPLAN_WORLD_WIDE_13 */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13}, + /* 0x0B, RTW_CHPLAN_TAIWAN */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 26}, + /* 0x0C, RTW_CHPLAN_CHINA */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 149, 153, 157, 161, 165}, 18}, + /* 0x0D, RTW_CHPLAN_SINGAPORE_INDIA_MEXICO */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165}, 24}, + /* 0x0E, RTW_CHPLAN_KOREA */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, 165}, 31}, + /* 0x0F, RTW_CHPLAN_TURKEY */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 52, 56, 60, 64}, 19}, + /* 0x10, RTW_CHPLAN_JAPAN */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 32}, + /* 0x11, RTW_CHPLAN_FCC_NO_DFS */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 36, 40, 44, 48, 149, 153, 157, 161, 165}, 20}, + /* 0x12, RTW_CHPLAN_JAPAN_NO_DFS */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48}, 17}, + /* 0x13, RTW_CHPLAN_WORLD_WIDE_5G */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165}, 37}, + /* 0x14, RTW_CHPLAN_TAIWAN_NO_DFS */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 56, 60, 64, 149, 153, 157, 161, 165}, 19}, +}; +#endif + +static RT_CHANNEL_PLAN_2G RTW_ChannelPlan2G[] = { + /* 0, RTW_RD_2G_NULL */ {{}, 0}, + /* 1, RTW_RD_2G_WORLD */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13}, + /* 2, RTW_RD_2G_ETSI1 */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13}, + /* 3, RTW_RD_2G_FCC1 */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11}, 11}, + /* 4, RTW_RD_2G_MKK1 */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14}, 14}, + /* 5, RTW_RD_2G_ETSI2 */ {{10, 11, 12, 13}, 4}, + /* 6, RTW_RD_2G_GLOBAL */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14}, 14}, + /* 7, RTW_RD_2G_MKK2 */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13}, + /* 8, RTW_RD_2G_FCC2 */ {{1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}, 13}, +}; + +static RT_CHANNEL_PLAN_5G RTW_ChannelPlan5G[] = { + /* 0, RTW_RD_5G_NULL */ {{}, 0}, + /* 1, RTW_RD_5G_ETSI1 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 19}, + /* 2, RTW_RD_5G_ETSI2 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165}, 24}, + /* 3, RTW_RD_5G_ETSI3 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 149, 153, 157, 161, 165}, 22}, + /* 4, RTW_RD_5G_FCC1 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165}, 24}, + /* 5, RTW_RD_5G_FCC2 */ {{36, 40, 44, 48, 149, 153, 157, 161, 165}, 9}, + /* 6, RTW_RD_5G_FCC3 */ {{36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165}, 13}, + /* 7, RTW_RD_5G_FCC4 */ {{36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161}, 12}, + /* 8, RTW_RD_5G_FCC5 */ {{149, 153, 157, 161, 165}, 5}, + /* 9, RTW_RD_5G_FCC6 */ {{36, 40, 44, 48, 52, 56, 60, 64}, 8}, + /* 10, RTW_RD_5G_FCC7 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165}, 21}, + /* 11, RTW_RD_5G_KCC1 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161}, 19}, + /* 12, RTW_RD_5G_MKK1 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 19}, + /* 13, RTW_RD_5G_MKK2 */ {{36, 40, 44, 48, 52, 56, 60, 64}, 8}, + /* 14, RTW_RD_5G_MKK3 */ {{100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 11}, + /* 15, RTW_RD_5G_NCC1 */ {{56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165}, 16}, + /* 16, RTW_RD_5G_NCC2 */ {{56, 60, 64, 149, 153, 157, 161, 165}, 8}, + /* 17, RTW_RD_5G_NCC3 */ {{149, 153, 157, 161, 165}, 5}, + /* 18, RTW_RD_5G_ETSI4 */ {{36, 40, 44, 48}, 4}, + /* 19, RTW_RD_5G_ETSI5 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165}, 21}, + /* 20, RTW_RD_5G_FCC8 */ {{149, 153, 157, 161}, 4}, + /* 21, RTW_RD_5G_ETSI6 */ {{36, 40, 44, 48, 52, 56, 60, 64}, 8}, + /* 22, RTW_RD_5G_ETSI7 */ {{36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165}, 13}, + /* 23, RTW_RD_5G_ETSI8 */ {{36, 40, 44, 48, 149, 153, 157, 161, 165}, 9}, + /* 24, RTW_RD_5G_ETSI9 */ {{100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}, 11}, + /* 25, RTW_RD_5G_ETSI10 */ {{149, 153, 157, 161, 165}, 5}, + /* 26, RTW_RD_5G_ETSI11 */ {{36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140, 149, 153, 157, 161, 165}, 16}, + /* 27, RTW_RD_5G_NCC4 */ {{52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165}, 17}, + /* 28, RTW_RD_5G_ETSI12 */ {{149, 153, 157, 161}, 4}, + /* 29, RTW_RD_5G_FCC9 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165}, 21}, + /* 30, RTW_RD_5G_ETSI13 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140}, 16}, + /* 31, RTW_RD_5G_FCC10 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161}, 20}, + /* 32, RTW_RD_5G_MKK4 */ {{36, 40, 44, 48}, 4}, + /* 33, RTW_RD_5G_ETSI14 */ {{36, 40, 44, 48, 52, 56, 60, 64, 132, 136, 140}, 11}, + + /* === Below are driver defined for legacy channel plan compatible, NO static index assigned ==== */ + /* RTW_RD_5G_OLD_FCC1 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 20}, + /* RTW_RD_5G_OLD_NCC1 */ {{56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165}, 15}, + /* RTW_RD_5G_OLD_KCC1 */ {{36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 149, 153, 157, 161, 165}, 20}, +}; + +static RT_CHANNEL_PLAN_MAP RTW_ChannelPlanMap[] = { + /* ===== 0x00 ~ 0x1F, legacy channel plan ===== */ + {RTW_RD_2G_FCC1, RTW_RD_5G_KCC1, TXPWR_LMT_FCC}, /* 0x00, RTW_CHPLAN_FCC */ + {RTW_RD_2G_FCC1, RTW_RD_5G_OLD_FCC1, TXPWR_LMT_FCC}, /* 0x01, RTW_CHPLAN_IC */ + {RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI1, TXPWR_LMT_ETSI}, /* 0x02, RTW_CHPLAN_ETSI */ + {RTW_RD_2G_ETSI1, RTW_RD_5G_NULL, TXPWR_LMT_ETSI}, /* 0x03, RTW_CHPLAN_SPAIN */ + {RTW_RD_2G_ETSI1, RTW_RD_5G_NULL, TXPWR_LMT_ETSI}, /* 0x04, RTW_CHPLAN_FRANCE */ + {RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_MKK}, /* 0x05, RTW_CHPLAN_MKK */ + {RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_MKK}, /* 0x06, RTW_CHPLAN_MKK1 */ + {RTW_RD_2G_ETSI1, RTW_RD_5G_FCC6, TXPWR_LMT_ETSI}, /* 0x07, RTW_CHPLAN_ISRAEL */ + {RTW_RD_2G_MKK1, RTW_RD_5G_FCC6, TXPWR_LMT_MKK}, /* 0x08, RTW_CHPLAN_TELEC */ + {RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x09, RTW_CHPLAN_GLOBAL_DOAMIN */ + {RTW_RD_2G_WORLD, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x0A, RTW_CHPLAN_WORLD_WIDE_13 */ + {RTW_RD_2G_FCC1, RTW_RD_5G_OLD_NCC1, TXPWR_LMT_FCC}, /* 0x0B, RTW_CHPLAN_TAIWAN */ + {RTW_RD_2G_ETSI1, RTW_RD_5G_FCC5, TXPWR_LMT_ETSI}, /* 0x0C, RTW_CHPLAN_CHINA */ + {RTW_RD_2G_FCC1, RTW_RD_5G_FCC3, TXPWR_LMT_WW}, /* 0x0D, RTW_CHPLAN_SINGAPORE_INDIA_MEXICO */ /* ETSI:Singapore, India. FCC:Mexico => WW */ + {RTW_RD_2G_FCC1, RTW_RD_5G_OLD_KCC1, TXPWR_LMT_ETSI}, /* 0x0E, RTW_CHPLAN_KOREA */ + {RTW_RD_2G_FCC1, RTW_RD_5G_FCC6, TXPWR_LMT_ETSI}, /* 0x0F, RTW_CHPLAN_TURKEY */ + {RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI1, TXPWR_LMT_MKK}, /* 0x10, RTW_CHPLAN_JAPAN */ + {RTW_RD_2G_FCC1, RTW_RD_5G_FCC2, TXPWR_LMT_FCC}, /* 0x11, RTW_CHPLAN_FCC_NO_DFS */ + {RTW_RD_2G_ETSI1, RTW_RD_5G_FCC7, TXPWR_LMT_MKK}, /* 0x12, RTW_CHPLAN_JAPAN_NO_DFS */ + {RTW_RD_2G_WORLD, RTW_RD_5G_FCC1, TXPWR_LMT_WW}, /* 0x13, RTW_CHPLAN_WORLD_WIDE_5G */ + {RTW_RD_2G_FCC1, RTW_RD_5G_NCC2, TXPWR_LMT_FCC}, /* 0x14, RTW_CHPLAN_TAIWAN_NO_DFS */ + {RTW_RD_2G_WORLD, RTW_RD_5G_FCC7, TXPWR_LMT_ETSI}, /* 0x15, RTW_CHPLAN_ETSI_NO_DFS */ + {RTW_RD_2G_WORLD, RTW_RD_5G_NCC1, TXPWR_LMT_ETSI}, /* 0x16, RTW_CHPLAN_KOREA_NO_DFS */ + {RTW_RD_2G_MKK1, RTW_RD_5G_FCC7, TXPWR_LMT_MKK}, /* 0x17, RTW_CHPLAN_JAPAN_NO_DFS */ + {RTW_RD_2G_NULL, RTW_RD_5G_FCC5, TXPWR_LMT_ETSI}, /* 0x18, RTW_CHPLAN_PAKISTAN_NO_DFS */ + {RTW_RD_2G_FCC1, RTW_RD_5G_FCC5, TXPWR_LMT_FCC}, /* 0x19, RTW_CHPLAN_TAIWAN2_NO_DFS */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x1A, */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x1B, */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x1C, */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x1D, */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x1E, */ + {RTW_RD_2G_NULL, RTW_RD_5G_FCC1, TXPWR_LMT_WW}, /* 0x1F, RTW_CHPLAN_WORLD_WIDE_ONLY_5G */ + + /* ===== 0x20 ~ 0x7F, new channel plan ===== */ + {RTW_RD_2G_WORLD, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x20, RTW_CHPLAN_WORLD_NULL */ + {RTW_RD_2G_ETSI1, RTW_RD_5G_NULL, TXPWR_LMT_ETSI}, /* 0x21, RTW_CHPLAN_ETSI1_NULL */ + {RTW_RD_2G_FCC1, RTW_RD_5G_NULL, TXPWR_LMT_FCC}, /* 0x22, RTW_CHPLAN_FCC1_NULL */ + {RTW_RD_2G_MKK1, RTW_RD_5G_NULL, TXPWR_LMT_MKK}, /* 0x23, RTW_CHPLAN_MKK1_NULL */ + {RTW_RD_2G_ETSI2, RTW_RD_5G_NULL, TXPWR_LMT_ETSI}, /* 0x24, RTW_CHPLAN_ETSI2_NULL */ + {RTW_RD_2G_FCC1, RTW_RD_5G_FCC1, TXPWR_LMT_FCC}, /* 0x25, RTW_CHPLAN_FCC1_FCC1 */ + {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI1, TXPWR_LMT_ETSI}, /* 0x26, RTW_CHPLAN_WORLD_ETSI1 */ + {RTW_RD_2G_MKK1, RTW_RD_5G_MKK1, TXPWR_LMT_MKK}, /* 0x27, RTW_CHPLAN_MKK1_MKK1 */ + {RTW_RD_2G_WORLD, RTW_RD_5G_KCC1, TXPWR_LMT_ETSI}, /* 0x28, RTW_CHPLAN_WORLD_KCC1 */ + {RTW_RD_2G_WORLD, RTW_RD_5G_FCC2, TXPWR_LMT_FCC}, /* 0x29, RTW_CHPLAN_WORLD_FCC2 */ + {RTW_RD_2G_FCC2, RTW_RD_5G_NULL, TXPWR_LMT_FCC}, /* 0x2A, RTW_CHPLAN_FCC2_NULL */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x2B, */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x2C, */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x2D, */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x2E, */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x2F, */ + {RTW_RD_2G_WORLD, RTW_RD_5G_FCC3, TXPWR_LMT_FCC}, /* 0x30, RTW_CHPLAN_WORLD_FCC3 */ + {RTW_RD_2G_WORLD, RTW_RD_5G_FCC4, TXPWR_LMT_FCC}, /* 0x31, RTW_CHPLAN_WORLD_FCC4 */ + {RTW_RD_2G_WORLD, RTW_RD_5G_FCC5, TXPWR_LMT_FCC}, /* 0x32, RTW_CHPLAN_WORLD_FCC5 */ + {RTW_RD_2G_WORLD, RTW_RD_5G_FCC6, TXPWR_LMT_FCC}, /* 0x33, RTW_CHPLAN_WORLD_FCC6 */ + {RTW_RD_2G_FCC1, RTW_RD_5G_FCC7, TXPWR_LMT_FCC}, /* 0x34, RTW_CHPLAN_FCC1_FCC7 */ + {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI2, TXPWR_LMT_ETSI}, /* 0x35, RTW_CHPLAN_WORLD_ETSI2 */ + {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI3, TXPWR_LMT_ETSI}, /* 0x36, RTW_CHPLAN_WORLD_ETSI3 */ + {RTW_RD_2G_MKK1, RTW_RD_5G_MKK2, TXPWR_LMT_MKK}, /* 0x37, RTW_CHPLAN_MKK1_MKK2 */ + {RTW_RD_2G_MKK1, RTW_RD_5G_MKK3, TXPWR_LMT_MKK}, /* 0x38, RTW_CHPLAN_MKK1_MKK3 */ + {RTW_RD_2G_FCC1, RTW_RD_5G_NCC1, TXPWR_LMT_FCC}, /* 0x39, RTW_CHPLAN_FCC1_NCC1 */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x3A, */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x3B, */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x3C, */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x3D, */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x3E, */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x3F, */ + {RTW_RD_2G_FCC1, RTW_RD_5G_NCC2, TXPWR_LMT_FCC}, /* 0x40, RTW_CHPLAN_FCC1_NCC2 */ + {RTW_RD_2G_GLOBAL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x41, RTW_CHPLAN_GLOBAL_NULL */ + {RTW_RD_2G_ETSI1, RTW_RD_5G_ETSI4, TXPWR_LMT_ETSI}, /* 0x42, RTW_CHPLAN_ETSI1_ETSI4 */ + {RTW_RD_2G_FCC1, RTW_RD_5G_FCC2, TXPWR_LMT_FCC}, /* 0x43, RTW_CHPLAN_FCC1_FCC2 */ + {RTW_RD_2G_FCC1, RTW_RD_5G_NCC3, TXPWR_LMT_FCC}, /* 0x44, RTW_CHPLAN_FCC1_NCC3 */ + {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI5, TXPWR_LMT_ETSI}, /* 0x45, RTW_CHPLAN_WORLD_ETSI5 */ + {RTW_RD_2G_FCC1, RTW_RD_5G_FCC8, TXPWR_LMT_FCC}, /* 0x46, RTW_CHPLAN_FCC1_FCC8 */ + {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI6, TXPWR_LMT_ETSI}, /* 0x47, RTW_CHPLAN_WORLD_ETSI6 */ + {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI7, TXPWR_LMT_ETSI}, /* 0x48, RTW_CHPLAN_WORLD_ETSI7 */ + {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI8, TXPWR_LMT_ETSI}, /* 0x49, RTW_CHPLAN_WORLD_ETSI8 */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x4A, */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x4B, */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x4C, */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x4D, */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x4E, */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x4F, */ + {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI9, TXPWR_LMT_ETSI}, /* 0x50, RTW_CHPLAN_WORLD_ETSI9 */ + {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI10, TXPWR_LMT_ETSI}, /* 0x51, RTW_CHPLAN_WORLD_ETSI10 */ + {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI11, TXPWR_LMT_ETSI}, /* 0x52, RTW_CHPLAN_WORLD_ETSI11 */ + {RTW_RD_2G_FCC1, RTW_RD_5G_NCC4, TXPWR_LMT_FCC}, /* 0x53, RTW_CHPLAN_FCC1_NCC4 */ + {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI12, TXPWR_LMT_ETSI}, /* 0x54, RTW_CHPLAN_WORLD_ETSI12 */ + {RTW_RD_2G_FCC1, RTW_RD_5G_FCC9, TXPWR_LMT_FCC}, /* 0x55, RTW_CHPLAN_FCC1_FCC9 */ + {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI13, TXPWR_LMT_ETSI}, /* 0x56, RTW_CHPLAN_WORLD_ETSI13 */ + {RTW_RD_2G_FCC1, RTW_RD_5G_FCC10, TXPWR_LMT_FCC}, /* 0x57, RTW_CHPLAN_FCC1_FCC10 */ + {RTW_RD_2G_MKK2, RTW_RD_5G_MKK4, TXPWR_LMT_MKK}, /* 0x58, RTW_CHPLAN_MKK2_MKK4 */ + {RTW_RD_2G_WORLD, RTW_RD_5G_ETSI14, TXPWR_LMT_ETSI}, /* 0x59, RTW_CHPLAN_WORLD_ETSI14 */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x5A, */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x5B, */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x5C, */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x5D, */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x5E, */ + {RTW_RD_2G_NULL, RTW_RD_5G_NULL, TXPWR_LMT_WW}, /* 0x5F, */ + {RTW_RD_2G_FCC1, RTW_RD_5G_FCC5, TXPWR_LMT_FCC}, /* 0x60, RTW_CHPLAN_FCC1_FCC5 */ +}; + +static RT_CHANNEL_PLAN_MAP RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE = { + RTW_RD_2G_WORLD, RTW_RD_5G_FCC1, TXPWR_LMT_FCC /* 0x7F, Realtek Define */ +}; + +bool rtw_chplan_is_empty(u8 id) +{ + RT_CHANNEL_PLAN_MAP *chplan_map; + + if (id == RTW_CHPLAN_REALTEK_DEFINE) + chplan_map = &RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE; + else + chplan_map = &RTW_ChannelPlanMap[id]; + + if (chplan_map->Index2G == RTW_RD_2G_NULL + && chplan_map->Index5G == RTW_RD_5G_NULL) + return _TRUE; + + return _FALSE; +} + +#ifdef CONFIG_DFS_MASTER +void rtw_rfctl_reset_cac(struct rf_ctl_t *rfctl) +{ + if (rtw_is_long_cac_ch(rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset)) + rfctl->cac_end_time = rtw_get_current_time() + rtw_ms_to_systime(CAC_TIME_CE_MS); + else + rfctl->cac_end_time = rtw_get_current_time() + rtw_ms_to_systime(CAC_TIME_MS); +} + +/* +* check if channel coverage includes new range and the new range is in DFS range +* called after radar_detect_ch,bw,offset is updated +*/ +bool rtw_is_cac_reset_needed(_adapter *adapter) +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + bool needed = _FALSE; + u32 pre_hi, pre_lo, hi, lo; + + if (0) + DBG_871X("pre_radar_detect_ch:%d, pre_radar_detect_by_sta_link:%d\n" + , rfctl->pre_radar_detect_ch, rfctl->pre_radar_detect_by_sta_link); + + if (rfctl->pre_radar_detect_by_sta_link == _TRUE) + goto exit; + + if (rfctl->pre_radar_detect_ch == 0) { + needed = _TRUE; + goto exit; + } + + if (rtw_chbw_to_freq_range(rfctl->radar_detect_ch, rfctl->radar_detect_bw, rfctl->radar_detect_offset, &hi, &lo) == _FALSE) + rtw_warn_on(1); + if (rtw_chbw_to_freq_range(rfctl->pre_radar_detect_ch, rfctl->pre_radar_detect_bw, rfctl->pre_radar_detect_offset, &pre_hi, &pre_lo) == _FALSE) + rtw_warn_on(1); + + if (!rtw_is_range_a_in_b(hi, lo, pre_hi, pre_lo)) { + if (rtw_is_range_a_in_b(pre_hi, pre_lo, hi, lo)) { + /* currrent is supper set of previous */ + if (rtw_is_dfs_range(hi, lo)) + needed = _TRUE; + } else if (rtw_is_range_overlap(hi, lo, pre_hi, pre_lo)) { + /* currrent is not supper set of previous, but has overlap */ + u32 new_hi, new_lo; + + if (lo < pre_lo) { + new_hi = pre_lo; + new_lo = lo; + if (hi <= pre_lo || hi >= pre_hi) { + DBG_871X_LEVEL(_drv_err_, "hi:%u, lo:%u, pre_hi:%u, pre_lo:%u\n" + , hi, lo, pre_hi, pre_lo); + rtw_warn_on(1); + goto exit; + } + } else if (hi > pre_hi) { + new_hi = hi; + new_lo = pre_hi; + if (lo >= pre_hi && lo <= pre_lo) { + DBG_871X_LEVEL(_drv_err_, "hi:%u, lo:%u, pre_hi:%u, pre_lo:%u\n" + , hi, lo, pre_hi, pre_lo); + rtw_warn_on(1); + goto exit; + } + } else { + DBG_871X_LEVEL(_drv_err_, "hi:%u, lo:%u, pre_hi:%u, pre_lo:%u\n" + , hi, lo, pre_hi, pre_lo); + rtw_warn_on(1); + goto exit; + } + + if (rtw_is_dfs_range(new_hi, new_lo)) + needed = _TRUE; + + } else { + /* no overlap */ + if (rtw_is_dfs_range(hi, lo)) + needed = _TRUE; + } + } + +exit: + return needed; +} + +bool _rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset) +{ + bool ret = _FALSE; + u32 hi = 0, lo = 0; + u32 r_hi = 0, r_lo = 0; + int i; + + if (rfctl->radar_detect_ch == 0) + goto exit; + + if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE) { + rtw_warn_on(1); + goto exit; + } + + if (rtw_chbw_to_freq_range(rfctl->radar_detect_ch + , rfctl->radar_detect_bw, rfctl->radar_detect_offset + , &r_hi, &r_lo) == _FALSE) { + rtw_warn_on(1); + goto exit; + } + + if (rtw_is_range_overlap(hi, lo, r_hi, r_lo)) + ret = _TRUE; + +exit: + return ret; +} + +bool rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl) +{ + return _rtw_rfctl_overlap_radar_detect_ch(rfctl + , rfctl_to_dvobj(rfctl)->oper_channel + , rfctl_to_dvobj(rfctl)->oper_bwmode + , rfctl_to_dvobj(rfctl)->oper_ch_offset); +} + +bool rtw_rfctl_is_tx_blocked_by_cac(struct rf_ctl_t *rfctl) +{ + return (rtw_rfctl_overlap_radar_detect_ch(rfctl) && IS_UNDER_CAC(rfctl)); +} + +bool rtw_chset_is_ch_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset) +{ + bool ret = _FALSE; + u32 hi = 0, lo = 0; + int i; + + if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE) + goto exit; + + for (i = 0; ch_set[i].ChannelNum != 0; i++) { + if (!rtw_ch2freq(ch_set[i].ChannelNum)) { + rtw_warn_on(1); + continue; + } + + if (!CH_IS_NON_OCP(&ch_set[i])) + continue; + + if (lo <= rtw_ch2freq(ch_set[i].ChannelNum) + && rtw_ch2freq(ch_set[i].ChannelNum) <= hi + ) { + ret = _TRUE; + break; + } + } + +exit: + return ret; +} + +/** + * rtw_chset_update_non_ocp - update non_ocp_end_time according to the given @ch, @bw, @offset into @ch_set + * @ch_set: the given channel set + * @ch: channel number on which radar is detected + * @bw: bandwidth on which radar is detected + * @offset: bandwidth offset on which radar is detected + * @ms: ms to add from now to update non_ocp_end_time, ms < 0 means use NON_OCP_TIME_MS + */ +static void _rtw_chset_update_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset, int ms) +{ + u32 hi = 0, lo = 0; + int i; + + if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE) + goto exit; + + for (i = 0; ch_set[i].ChannelNum != 0; i++) { + if (!rtw_ch2freq(ch_set[i].ChannelNum)) { + rtw_warn_on(1); + continue; + } + + if (lo <= rtw_ch2freq(ch_set[i].ChannelNum) + && rtw_ch2freq(ch_set[i].ChannelNum) <= hi + ) { + if (ms >= 0) + ch_set[i].non_ocp_end_time = rtw_get_current_time() + rtw_ms_to_systime(ms); + else + ch_set[i].non_ocp_end_time = rtw_get_current_time() + rtw_ms_to_systime(NON_OCP_TIME_MS); + } + } + +exit: + return; +} + +inline void rtw_chset_update_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset) +{ + _rtw_chset_update_non_ocp(ch_set, ch, bw, offset, -1); +} + +inline void rtw_chset_update_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset, int ms) +{ + _rtw_chset_update_non_ocp(ch_set, ch, bw, offset, ms); +} +#endif /* CONFIG_DFS_MASTER */ + +bool rtw_choose_available_chbw(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8 *dec_bw, u8 *dec_offset, u8 d_flags) +{ + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + int i; + + if (!dec_ch || !dec_bw || !dec_offset) { + rtw_warn_on(1); + return _FAIL; + } + + for (i = 0; i < mlmeext->max_chan_nums; i++) { + + *dec_ch = mlmeext->channel_set[i].ChannelNum; + *dec_bw = req_bw; + if (*dec_bw == CHANNEL_WIDTH_20) + *dec_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + else + *dec_offset = rtw_get_offset_by_ch(*dec_ch); + + if ((d_flags & RTW_CHF_2G) && *dec_ch <= 14) + continue; + + if ((d_flags & RTW_CHF_5G) && *dec_ch > 14) + continue; + + rtw_adjust_chbw(adapter, *dec_ch, dec_bw, dec_offset); + + if ((d_flags & RTW_CHF_DFS) && rtw_is_dfs_ch(*dec_ch, *dec_bw, *dec_offset)) + continue; + + if ((d_flags & RTW_CHF_LONG_CAC) && rtw_is_long_cac_ch(*dec_ch, *dec_bw, *dec_offset)) + continue; + + if ((d_flags & RTW_CHF_NON_DFS) && !rtw_is_dfs_ch(*dec_ch, *dec_bw, *dec_offset)) + continue; + + if ((d_flags & RTW_CHF_NON_LONG_CAC) && !rtw_is_long_cac_ch(*dec_ch, *dec_bw, *dec_offset)) + continue; + + if (!rtw_chset_is_ch_non_ocp(mlmeext->channel_set, *dec_ch, *dec_bw, *dec_offset)) + break; + } + + return (i < mlmeext->max_chan_nums)?_TRUE:_FALSE; +} + +void dump_country_chplan(void *sel, const struct country_chplan *ent) +{ + DBG_871X_SEL(sel, "\"%c%c\", 0x%02X%s\n" + , ent->alpha2[0], ent->alpha2[1], ent->chplan + , COUNTRY_CHPLAN_EN_11AC(ent) ? " ac" : "" + ); +} + +void dump_country_chplan_map(void *sel) +{ + const struct country_chplan *ent; + u8 code[2]; + +#if RTW_DEF_MODULE_REGULATORY_CERT + DBG_871X_SEL(sel, "RTW_DEF_MODULE_REGULATORY_CERT:0x%x\n", RTW_DEF_MODULE_REGULATORY_CERT); +#endif +#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP + DBG_871X_SEL(sel, "CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP\n"); +#endif + + for (code[0] = 'A'; code[0] <= 'Z'; code[0]++) { + for (code[1] = 'A'; code[1] <= 'Z'; code[1]++) { + ent = rtw_get_chplan_from_country(code); + if (!ent) + continue; + + dump_country_chplan(sel, ent); + } + } +} + +void dump_chplan_id_list(void *sel) +{ + int i; + + for (i = 0; i < RTW_CHPLAN_MAX; i++) { + if (!rtw_is_channel_plan_valid(i)) + continue; + + DBG_871X_SEL(sel, "0x%02X ", i); + } + + DBG_871X_SEL_NL(sel, "0x7F\n"); +} + +void dump_chplan_test(void *sel) +{ + int i, j; + + /* check invalid channel */ + for (i = 0; i < RTW_RD_2G_MAX; i++) { + for (j = 0; j < RTW_ChannelPlan2G[i].Len; j++) { + if (rtw_ch2freq(RTW_ChannelPlan2G[i].Channel[j]) == 0) + DBG_871X_SEL_NL(sel, "invalid ch:%u at (%d,%d)\n", RTW_ChannelPlan2G[i].Channel[j], i, j); + } + } + + for (i = 0; i < RTW_RD_5G_MAX; i++) { + for (j = 0; j < RTW_ChannelPlan5G[i].Len; j++) { + if (rtw_ch2freq(RTW_ChannelPlan5G[i].Channel[j]) == 0) + DBG_871X_SEL_NL(sel, "invalid ch:%u at (%d,%d)\n", RTW_ChannelPlan5G[i].Channel[j], i, j); + } + } +} + +void dump_chset(void *sel, RT_CHANNEL_INFO *ch_set) +{ + u8 i; + + for (i = 0; ch_set[i].ChannelNum != 0; i++) { + DBG_871X_SEL_NL(sel, "ch:%3u, freq:%u, scan_type:%d" + , ch_set[i].ChannelNum, rtw_ch2freq(ch_set[i].ChannelNum), ch_set[i].ScanType); + + #ifdef CONFIG_FIND_BEST_CHANNEL + DBG_871X_SEL(sel, ", rx_count:%u", ch_set[i].rx_count); + #endif + + #ifdef CONFIG_DFS_MASTER + if (rtw_is_dfs_ch(ch_set[i].ChannelNum, CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE)) { + if (CH_IS_NON_OCP(&ch_set[i])) + DBG_871X_SEL(sel, ", non_ocp:%d" + , rtw_systime_to_ms(ch_set[i].non_ocp_end_time - rtw_get_current_time())); + else + DBG_871X_SEL(sel, ", non_ocp:N/A"); + } + #endif + + DBG_871X_SEL(sel, "\n"); + } + + DBG_871X_SEL_NL(sel, "total ch number:%d\n", i); +} + +void dump_cur_chset(void *sel, _adapter *adapter) +{ + struct mlme_priv *mlme = &adapter->mlmepriv; + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + + if (mlme->country_ent) + dump_country_chplan(sel, mlme->country_ent); + else + DBG_871X_SEL_NL(sel, "chplan:0x%02X\n", mlme->ChannelPlan); + + DBG_871X_SEL_NL(sel, "2G_PLS:%u, 5G_PLS:%u\n" + , hal_data->Regulation2_4G, hal_data->Regulation5G); + dump_chset(sel, mlmeext->channel_set); +} + +/* + * Search the @param ch in given @param ch_set + * @ch_set: the given channel set + * @ch: the given channel number + * + * return the index of channel_num in channel_set, -1 if not found + */ +int rtw_ch_set_search_ch(RT_CHANNEL_INFO *ch_set, const u32 ch) +{ + int i; + for(i=0;ch_set[i].ChannelNum!=0;i++){ + if(ch == ch_set[i].ChannelNum) + break; + } + + if(i >= ch_set[i].ChannelNum) + return -1; + return i; +} + +/* + * Check the @param ch is fit with setband setting of @param adapter + * @adapter: the given adapter + * @ch: the given channel number + * + * return _TRUE when check valid, _FALSE not valid + */ +bool rtw_mlme_band_check(_adapter *adapter, const u32 ch) +{ + if (adapter->setband == WIFI_FREQUENCY_BAND_AUTO /* 2.4G and 5G */ + || (adapter->setband == WIFI_FREQUENCY_BAND_2GHZ && ch < 35) /* 2.4G only */ + || (adapter->setband == WIFI_FREQUENCY_BAND_5GHZ && ch > 35) /* 5G only */ + ) { + return _TRUE; + } + return _FALSE; +} + +/**************************************************************************** + +Following are the initialization functions for WiFi MLME + +*****************************************************************************/ + +int init_hw_mlme_ext(_adapter *padapter) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + //set_opmode_cmd(padapter, infra_client_with_mlme);//removed + + set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); + + return _SUCCESS; +} + +void init_mlme_default_rate_set(_adapter* padapter) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + unsigned char mixed_datarate[NumRates] = {_1M_RATE_, _2M_RATE_, _5M_RATE_, _11M_RATE_, _6M_RATE_,_9M_RATE_, _12M_RATE_, _18M_RATE_, _24M_RATE_, _36M_RATE_, _48M_RATE_, _54M_RATE_, 0xff}; + unsigned char mixed_basicrate[NumRates] ={_1M_RATE_, _2M_RATE_, _5M_RATE_, _11M_RATE_, _6M_RATE_, _12M_RATE_, _24M_RATE_, 0xff,}; + unsigned char supported_mcs_set[16] = {0xff, 0xff, 0xff, 0x00, 0x00, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; + + _rtw_memcpy(pmlmeext->datarate, mixed_datarate, NumRates); + _rtw_memcpy(pmlmeext->basicrate, mixed_basicrate, NumRates); + + _rtw_memcpy(pmlmeext->default_supported_mcs_set, supported_mcs_set, sizeof(pmlmeext->default_supported_mcs_set)); +} + +static void init_mlme_ext_priv_value(_adapter* padapter) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + ATOMIC_SET(&pmlmeext->event_seq, 0); + pmlmeext->mgnt_seq = 0;//reset to zero when disconnect at client mode +#ifdef CONFIG_IEEE80211W + pmlmeext->sa_query_seq = 0; + pmlmeext->mgnt_80211w_IPN=0; + pmlmeext->mgnt_80211w_IPN_rx=0; +#endif //CONFIG_IEEE80211W + pmlmeext->cur_channel = padapter->registrypriv.channel; + pmlmeext->cur_bwmode = CHANNEL_WIDTH_20; + pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + + pmlmeext->retry = 0; + + pmlmeext->cur_wireless_mode = padapter->registrypriv.wireless_mode; + + init_mlme_default_rate_set(padapter); + + if(pmlmeext->cur_channel > 14) + pmlmeext->tx_rate = IEEE80211_OFDM_RATE_6MB; + else + pmlmeext->tx_rate = IEEE80211_CCK_RATE_1MB; + + mlmeext_set_scan_state(pmlmeext, SCAN_DISABLE); + pmlmeext->sitesurvey_res.channel_idx = 0; + pmlmeext->sitesurvey_res.bss_cnt = 0; + pmlmeext->sitesurvey_res.scan_ch_ms = SURVEY_TO; + pmlmeext->sitesurvey_res.rx_ampdu_accept = RX_AMPDU_ACCEPT_INVALID; + pmlmeext->sitesurvey_res.rx_ampdu_size = RX_AMPDU_SIZE_INVALID; + #ifdef CONFIG_SCAN_BACKOP + mlmeext_assign_scan_backop_flags_sta(pmlmeext, /*SS_BACKOP_EN|*/SS_BACKOP_PS_ANNC|SS_BACKOP_TX_RESUME); + mlmeext_assign_scan_backop_flags_ap(pmlmeext, SS_BACKOP_EN|SS_BACKOP_PS_ANNC|SS_BACKOP_TX_RESUME); + pmlmeext->sitesurvey_res.scan_cnt = 0; + pmlmeext->sitesurvey_res.scan_cnt_max = RTW_SCAN_NUM_OF_CH; + pmlmeext->sitesurvey_res.backop_ms = RTW_BACK_OP_CH_MS; + #endif + #if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL) + pmlmeext->sitesurvey_res.is_sw_antdiv_bl_scan = 0; + #endif + pmlmeext->scan_abort = _FALSE; + + pmlmeinfo->state = WIFI_FW_NULL_STATE; + pmlmeinfo->reauth_count = 0; + pmlmeinfo->reassoc_count = 0; + pmlmeinfo->link_count = 0; + pmlmeinfo->auth_seq = 0; + pmlmeinfo->auth_algo = dot11AuthAlgrthm_Open; + pmlmeinfo->key_index = 0; + pmlmeinfo->iv = 0; + + pmlmeinfo->enc_algo = _NO_PRIVACY_; + pmlmeinfo->authModeToggle = 0; + + _rtw_memset(pmlmeinfo->chg_txt, 0, 128); + + pmlmeinfo->slotTime = SHORT_SLOT_TIME; + pmlmeinfo->preamble_mode = PREAMBLE_AUTO; + + pmlmeinfo->dialogToken = 0; + + pmlmeext->action_public_rxseq = 0xffff; + pmlmeext->action_public_dialog_token = 0xff; +} + +static int has_channel(RT_CHANNEL_INFO *channel_set, + u8 chanset_size, + u8 chan) { + int i; + + for (i = 0; i < chanset_size; i++) { + if (channel_set[i].ChannelNum == chan) { + return 1; + } + } + + return 0; +} + +static void init_channel_list(_adapter *padapter, RT_CHANNEL_INFO *channel_set, + u8 chanset_size, + struct p2p_channels *channel_list) { + struct registry_priv *regsty = adapter_to_regsty(padapter); + + struct p2p_oper_class_map op_class[] = { + { IEEE80211G, 81, 1, 13, 1, BW20 }, + { IEEE80211G, 82, 14, 14, 1, BW20 }, +#if 0 /* Do not enable HT40 on 2 GHz */ + { IEEE80211G, 83, 1, 9, 1, BW40PLUS }, + { IEEE80211G, 84, 5, 13, 1, BW40MINUS }, +#endif + { IEEE80211A, 115, 36, 48, 4, BW20 }, + { IEEE80211A, 116, 36, 44, 8, BW40PLUS }, + { IEEE80211A, 117, 40, 48, 8, BW40MINUS }, + { IEEE80211A, 124, 149, 161, 4, BW20 }, + { IEEE80211A, 125, 149, 169, 4, BW20 }, + { IEEE80211A, 126, 149, 157, 8, BW40PLUS }, + { IEEE80211A, 127, 153, 161, 8, BW40MINUS }, + { -1, 0, 0, 0, 0, BW20 } + }; + + int cla, op; + + cla = 0; + + for (op = 0; op_class[op].op_class; op++) { + u8 ch; + struct p2p_oper_class_map *o = &op_class[op]; + struct p2p_reg_class *reg = NULL; + + for (ch = o->min_chan; ch <= o->max_chan; ch += o->inc) { + if (!has_channel(channel_set, chanset_size, ch)) { + continue; + } + + if ((0 == padapter->registrypriv.ht_enable) && (8 == o->inc)) + continue; + + if ((REGSTY_IS_BW_5G_SUPPORT(regsty, CHANNEL_WIDTH_40)) && + ((BW40MINUS == o->bw) || (BW40PLUS == o->bw))) + continue; + + if (reg == NULL) { + reg = &channel_list->reg_class[cla]; + cla++; + reg->reg_class = o->op_class; + reg->channels = 0; + } + reg->channel[reg->channels] = ch; + reg->channels++; + } + } + channel_list->reg_classes = cla; + +} + +static u8 init_channel_set(_adapter* padapter, u8 ChannelPlan, RT_CHANNEL_INFO *channel_set) +{ + u8 index,chanset_size = 0; + u8 b5GBand = _FALSE, b2_4GBand = _FALSE; + u8 Index2G = 0, Index5G=0; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); + + if (!rtw_is_channel_plan_valid(ChannelPlan)) { + DBG_871X_LEVEL(_drv_err_, "ChannelPlan ID 0x%02X error !!!!!\n", ChannelPlan); + return chanset_size; + } + + _rtw_memset(channel_set, 0, sizeof(RT_CHANNEL_INFO)*MAX_CHANNEL_NUM); + + if (IsSupported24G(padapter->registrypriv.wireless_mode)) + b2_4GBand = _TRUE; + + if (IsSupported5G(padapter->registrypriv.wireless_mode)) + b5GBand = _TRUE; + + if (b2_4GBand) { + if (RTW_CHPLAN_REALTEK_DEFINE == ChannelPlan) + Index2G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.Index2G; + else + Index2G = RTW_ChannelPlanMap[ChannelPlan].Index2G; + + for (index = 0; index < RTW_ChannelPlan2G[Index2G].Len; index++) { + channel_set[chanset_size].ChannelNum = RTW_ChannelPlan2G[Index2G].Channel[index]; + + if (RTW_CHPLAN_GLOBAL_DOAMIN == ChannelPlan + || RTW_CHPLAN_GLOBAL_NULL == ChannelPlan + ) { + /* Channel 1~11 is active, and 12~14 is passive */ + if(channel_set[chanset_size].ChannelNum >= 1 && channel_set[chanset_size].ChannelNum <= 11) + channel_set[chanset_size].ScanType = SCAN_ACTIVE; + else if((channel_set[chanset_size].ChannelNum >= 12 && channel_set[chanset_size].ChannelNum <= 14)) + channel_set[chanset_size].ScanType = SCAN_PASSIVE; + } else if (RTW_CHPLAN_WORLD_WIDE_13 == ChannelPlan + || RTW_CHPLAN_WORLD_WIDE_5G == ChannelPlan + || RTW_RD_2G_WORLD == Index2G + ) { + /* channel 12~13, passive scan */ + if(channel_set[chanset_size].ChannelNum <= 11) + channel_set[chanset_size].ScanType = SCAN_ACTIVE; + else + channel_set[chanset_size].ScanType = SCAN_PASSIVE; + } else { + channel_set[chanset_size].ScanType = SCAN_ACTIVE; + } + + chanset_size++; + } + } + + if (b5GBand) { + if (RTW_CHPLAN_REALTEK_DEFINE == ChannelPlan) + Index5G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.Index5G; + else + Index5G = RTW_ChannelPlanMap[ChannelPlan].Index5G; + + for (index = 0; index < RTW_ChannelPlan5G[Index5G].Len; index++) { +#ifdef CONFIG_DFS + channel_set[chanset_size].ChannelNum = RTW_ChannelPlan5G[Index5G].Channel[index]; + if ( channel_set[chanset_size].ChannelNum <= 48 + || channel_set[chanset_size].ChannelNum >= 149 ) + { + if (RTW_CHPLAN_WORLD_WIDE_5G == ChannelPlan) /* passive scan for all 5G channels */ + channel_set[chanset_size].ScanType = SCAN_PASSIVE; + else + channel_set[chanset_size].ScanType = SCAN_ACTIVE; + } + else + { + channel_set[chanset_size].ScanType = SCAN_PASSIVE; + } + chanset_size++; +#else /* CONFIG_DFS */ + if (RTW_ChannelPlan5G[Index5G].Channel[index] <= 48 + || RTW_ChannelPlan5G[Index5G].Channel[index] >= 149 + ) { + channel_set[chanset_size].ChannelNum = RTW_ChannelPlan5G[Index5G].Channel[index]; + if (RTW_CHPLAN_WORLD_WIDE_5G == ChannelPlan) /* passive scan for all 5G channels */ + channel_set[chanset_size].ScanType = SCAN_PASSIVE; + else + channel_set[chanset_size].ScanType = SCAN_ACTIVE; + DBG_871X("%s(): channel_set[%d].ChannelNum = %d\n", __FUNCTION__, chanset_size, channel_set[chanset_size].ChannelNum); + chanset_size++; + } +#endif /* CONFIG_DFS */ + } + } + + if (RTW_CHPLAN_REALTEK_DEFINE == ChannelPlan) { + hal_data->Regulation2_4G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.regd; + hal_data->Regulation5G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.regd; + } else { + hal_data->Regulation2_4G = RTW_ChannelPlanMap[ChannelPlan].regd; + hal_data->Regulation5G = RTW_ChannelPlanMap[ChannelPlan].regd; + } + + DBG_871X(FUNC_ADPT_FMT" ChannelPlan ID:0x%02x, ch num:%d\n" + , FUNC_ADPT_ARG(padapter), ChannelPlan, chanset_size); + + return chanset_size; +} + +int init_mlme_ext_priv(_adapter* padapter) +{ + int res = _SUCCESS; + struct registry_priv* pregistrypriv = &padapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + // We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). + //_rtw_memset((u8 *)pmlmeext, 0, sizeof(struct mlme_ext_priv)); + + pmlmeext->padapter = padapter; + + //fill_fwpriv(padapter, &(pmlmeext->fwpriv)); + + init_mlme_ext_priv_value(padapter); + pmlmeinfo->bAcceptAddbaReq = pregistrypriv->bAcceptAddbaReq; + + init_mlme_ext_timer(padapter); + +#ifdef CONFIG_AP_MODE + init_mlme_ap_info(padapter); +#endif + + pmlmeext->max_chan_nums = init_channel_set(padapter, pmlmepriv->ChannelPlan,pmlmeext->channel_set); + init_channel_list(padapter, pmlmeext->channel_set, pmlmeext->max_chan_nums, &pmlmeext->channel_list); + pmlmeext->last_scan_time = 0; + pmlmeext->mlmeext_init = _TRUE; + + +#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK + pmlmeext->active_keep_alive_check = _TRUE; +#else + pmlmeext->active_keep_alive_check = _FALSE; +#endif + +#ifdef DBG_FIXED_CHAN + pmlmeext->fixed_chan = 0xFF; +#endif + + return res; + +} + +void free_mlme_ext_priv (struct mlme_ext_priv *pmlmeext) +{ + _adapter *padapter = pmlmeext->padapter; + + if (!padapter) + return; + + if (rtw_is_drv_stopped(padapter)) { + _cancel_timer_ex(&pmlmeext->survey_timer); + _cancel_timer_ex(&pmlmeext->link_timer); + //_cancel_timer_ex(&pmlmeext->ADDBA_timer); + } +} + +static u8 cmp_pkt_chnl_diff(_adapter *padapter,u8* pframe,uint packet_len) +{ // if the channel is same, return 0. else return channel differential + uint len; + u8 channel; + u8 *p; + p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_, _DSSET_IE_, &len, packet_len - _BEACON_IE_OFFSET_); + if (p) + { + channel = *(p + 2); + if(padapter->mlmeextpriv.cur_channel >= channel) + { + return (padapter->mlmeextpriv.cur_channel - channel); + } + else + { + return (channel-padapter->mlmeextpriv.cur_channel); + } + } + else + { + return 0; + } +} + +static void _mgt_dispatcher(_adapter *padapter, struct mlme_handler *ptable, union recv_frame *precv_frame) +{ + u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff}; + u8 *pframe = precv_frame->u.hdr.rx_data; + + if(ptable->func) + { + //receive the frames that ra(a1) is my address or ra(a1) is bc address. + if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_mac_addr(padapter), ETH_ALEN) && + !_rtw_memcmp(GetAddr1Ptr(pframe), bc_addr, ETH_ALEN)) + { + return; + } + + ptable->func(padapter, precv_frame); + } + +} + +void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame) +{ + int index; + struct mlme_handler *ptable; +#ifdef CONFIG_AP_MODE + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; +#endif //CONFIG_AP_MODE + u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff}; + u8 *pframe = precv_frame->u.hdr.rx_data; + struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, GetAddr2Ptr(pframe)); + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + + RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, + ("+mgt_dispatcher: type(0x%x) subtype(0x%x)\n", + GetFrameType(pframe), GetFrameSubType(pframe))); + +#if 0 + { + u8 *pbuf; + pbuf = GetAddr1Ptr(pframe); + DBG_871X("A1-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf+1), *(pbuf+2), *(pbuf+3), *(pbuf+4), *(pbuf+5)); + pbuf = GetAddr2Ptr(pframe); + DBG_871X("A2-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf+1), *(pbuf+2), *(pbuf+3), *(pbuf+4), *(pbuf+5)); + pbuf = GetAddr3Ptr(pframe); + DBG_871X("A3-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf+1), *(pbuf+2), *(pbuf+3), *(pbuf+4), *(pbuf+5)); + } +#endif + + if (GetFrameType(pframe) != WIFI_MGT_TYPE) + { + RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("mgt_dispatcher: type(0x%x) error!\n", GetFrameType(pframe))); + return; + } + + //receive the frames that ra(a1) is my address or ra(a1) is bc address. + if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_mac_addr(padapter), ETH_ALEN) && + !_rtw_memcmp(GetAddr1Ptr(pframe), bc_addr, ETH_ALEN)) + { + return; + } + + ptable = mlme_sta_tbl; + + index = GetFrameSubType(pframe) >> 4; + +#ifdef CONFIG_TDLS + if((index << 4)==WIFI_ACTION){ + /* category==public (4), action==TDLS_DISCOVERY_RESPONSE */ + if (*(pframe+24) == RTW_WLAN_CATEGORY_PUBLIC && *(pframe+25) == TDLS_DISCOVERY_RESPONSE) { + DBG_871X("[TDLS] Recv %s from "MAC_FMT"\n", rtw_tdls_action_txt(TDLS_DISCOVERY_RESPONSE), MAC_ARG(GetAddr2Ptr(pframe))); + On_TDLS_Dis_Rsp(padapter, precv_frame); + } + } +#endif //CONFIG_TDLS + + if (index >= (sizeof(mlme_sta_tbl) /sizeof(struct mlme_handler))) + { + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Currently we do not support reserved sub-fr-type=%d\n", index)); + return; + } + ptable += index; + +#if 1 + if (psta != NULL) + { + if (GetRetry(pframe)) + { + if (precv_frame->u.hdr.attrib.seq_num == psta->RxMgmtFrameSeqNum) + { + /* drop the duplicate management frame */ + pdbgpriv->dbg_rx_dup_mgt_frame_drop_count++; + DBG_871X("Drop duplicate management frame with seq_num = %d.\n", precv_frame->u.hdr.attrib.seq_num); + return; + } + } + psta->RxMgmtFrameSeqNum = precv_frame->u.hdr.attrib.seq_num; + } +#else + + if(GetRetry(pframe)) + { + //RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("drop due to decache!\n")); + //return; + } +#endif + +#ifdef CONFIG_AP_MODE + switch (GetFrameSubType(pframe)) + { + case WIFI_AUTH: + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + ptable->func = &OnAuth; + else + ptable->func = &OnAuthClient; +#if defined(fallthrough) + fallthrough; +#endif + case WIFI_ASSOCREQ: + case WIFI_REASSOCREQ: + _mgt_dispatcher(padapter, ptable, precv_frame); +#ifdef CONFIG_HOSTAPD_MLME + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + rtw_hostapd_mlme_rx(padapter, precv_frame); +#endif + break; + case WIFI_PROBEREQ: + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + { +#ifdef CONFIG_HOSTAPD_MLME + rtw_hostapd_mlme_rx(padapter, precv_frame); +#else + _mgt_dispatcher(padapter, ptable, precv_frame); +#endif + } + else + _mgt_dispatcher(padapter, ptable, precv_frame); + break; + case WIFI_BEACON: + _mgt_dispatcher(padapter, ptable, precv_frame); + break; + case WIFI_ACTION: + //if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + _mgt_dispatcher(padapter, ptable, precv_frame); + break; + default: + _mgt_dispatcher(padapter, ptable, precv_frame); + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + rtw_hostapd_mlme_rx(padapter, precv_frame); + break; + } +#else + + _mgt_dispatcher(padapter, ptable, precv_frame); + +#endif + +} + +#ifdef CONFIG_P2P +u32 p2p_listen_state_process(_adapter *padapter, unsigned char *da) +{ + bool response = _TRUE; + +#ifdef CONFIG_IOCTL_CFG80211 + if( padapter->wdinfo.driver_interface == DRIVER_CFG80211 ) + { + if(padapter->cfg80211_wdinfo.is_ro_ch == _FALSE + || rtw_get_oper_ch(padapter) != padapter->wdinfo.listen_channel + || adapter_wdev_data(padapter)->p2p_enabled == _FALSE + || padapter->mlmepriv.wps_probe_resp_ie == NULL + || padapter->mlmepriv.p2p_probe_resp_ie == NULL + ) + { +#ifdef CONFIG_DEBUG_CFG80211 + DBG_871X("DON'T issue_probersp_p2p: p2p_enabled:%d, wps_probe_resp_ie:%p, p2p_probe_resp_ie:%p, ", + adapter_wdev_data(padapter)->p2p_enabled, + padapter->mlmepriv.wps_probe_resp_ie, + padapter->mlmepriv.p2p_probe_resp_ie); + DBG_871X("is_ro_ch:%d, op_ch:%d, p2p_listen_channel:%d\n", + padapter->cfg80211_wdinfo.is_ro_ch, + rtw_get_oper_ch(padapter), + padapter->wdinfo.listen_channel); +#endif + response = _FALSE; + } + } + else +#endif //CONFIG_IOCTL_CFG80211 + if( padapter->wdinfo.driver_interface == DRIVER_WEXT ) + { + // do nothing if the device name is empty + if ( !padapter->wdinfo.device_name_len ) + { + response = _FALSE; + } + } + + if (response == _TRUE) + issue_probersp_p2p( padapter, da); + + return _SUCCESS; +} +#endif //CONFIG_P2P + + +/**************************************************************************** + +Following are the callback functions for each subtype of the management frames + +*****************************************************************************/ + +unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame) +{ + unsigned int ielen; + unsigned char *p; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur = &(pmlmeinfo->network); + u8 *pframe = precv_frame->u.hdr.rx_data; + uint len = precv_frame->u.hdr.len; + u8 is_valid_p2p_probereq = _FALSE; + +#ifdef CONFIG_ATMEL_RC_PATCH + u8 *target_ie=NULL, *wps_ie=NULL; + u8 *start; + uint search_len = 0, wps_ielen = 0, target_ielen = 0; + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; +#endif + + +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + u8 wifi_test_chk_rate = 1; + +#ifdef CONFIG_IOCTL_CFG80211 + if ((pwdinfo->driver_interface == DRIVER_CFG80211) + && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) + && (GET_CFG80211_REPORT_MGMT(adapter_wdev_data(padapter), IEEE80211_STYPE_PROBE_REQ) == _TRUE) + ) { + rtw_cfg80211_rx_probe_request(padapter, pframe, len); + return _SUCCESS; + } +#endif /* CONFIG_IOCTL_CFG80211 */ + + if ( !rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && + !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE) && + !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) && + !rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH) && + !rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) + ) + { + // Commented by Albert 2011/03/17 + // mcs_rate = 0 -> CCK 1M rate + // mcs_rate = 1 -> CCK 2M rate + // mcs_rate = 2 -> CCK 5.5M rate + // mcs_rate = 3 -> CCK 11M rate + // In the P2P mode, the driver should not support the CCK rate + + // Commented by Kurt 2012/10/16 + // IOT issue: Google Nexus7 use 1M rate to send p2p_probe_req after GO nego completed and Nexus7 is client + if (padapter->registrypriv.wifi_spec == 1) + { + if ( pattrib->data_rate <= 3 ) + { + wifi_test_chk_rate = 0; + } + } + + if( wifi_test_chk_rate == 1 ) + { + if((is_valid_p2p_probereq = process_probe_req_p2p_ie(pwdinfo, pframe, len)) == _TRUE) + { + if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)) + { + // FIXME + if( padapter->wdinfo.driver_interface == DRIVER_WEXT ) + report_survey_event(padapter, precv_frame); + + p2p_listen_state_process( padapter, get_sa(pframe)); + + return _SUCCESS; + } + + if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) + { + goto _continue; + } + } + } + } + +_continue: +#endif //CONFIG_P2P + + if(check_fwstate(pmlmepriv, WIFI_STATION_STATE)) + { + return _SUCCESS; + } + + if(check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE && + check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE|WIFI_AP_STATE)==_FALSE) + { + return _SUCCESS; + } + + + //DBG_871X("+OnProbeReq\n"); + + +#ifdef CONFIG_ATMEL_RC_PATCH + if ((wps_ie = rtw_get_wps_ie( + pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, + len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_, + NULL, &wps_ielen))) { + + target_ie = rtw_get_wps_attr_content( wps_ie, wps_ielen, WPS_ATTR_MANUFACTURER, NULL, &target_ielen); + } + if ((target_ie && (target_ielen == 4)) && (_TRUE ==_rtw_memcmp((void *)target_ie, "Ozmo",4 ))) { + //psta->flag_atmel_rc = 1; + unsigned char *sa_addr = get_sa(pframe); + printk("%s: Find Ozmo RC -- %02x:%02x:%02x:%02x:%02x:%02x \n\n", + __func__, *sa_addr, *(sa_addr+1), *(sa_addr+2), *(sa_addr+3), *(sa_addr+4), *(sa_addr+5)); + _rtw_memcpy( pstapriv->atmel_rc_pattern, get_sa(pframe), ETH_ALEN); + } +#endif + + +#ifdef CONFIG_AUTO_AP_MODE + if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE && + pmlmepriv->cur_network.join_res == _TRUE) + { + _irqL irqL; + struct sta_info *psta; + u8 *mac_addr, *peer_addr; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 RC_OUI[4]={0x00,0xE0,0x4C,0x0A}; + //EID[1] + EID_LEN[1] + RC_OUI[4] + MAC[6] + PairingID[2] + ChannelNum[2] + + p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _VENDOR_SPECIFIC_IE_, (int *)&ielen, + len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_); + + if(!p || ielen !=14) + goto _non_rc_device; + + if(!_rtw_memcmp(p+2, RC_OUI, sizeof(RC_OUI))) + goto _non_rc_device; + + if(!_rtw_memcmp(p+6, get_sa(pframe), ETH_ALEN)) + { + DBG_871X("%s, do rc pairing ("MAC_FMT"), but mac addr mismatch!("MAC_FMT")\n", __FUNCTION__, + MAC_ARG(get_sa(pframe)), MAC_ARG(p+6)); + + goto _non_rc_device; + } + + DBG_871X("%s, got the pairing device("MAC_FMT")\n", __FUNCTION__, MAC_ARG(get_sa(pframe))); + + //new a station + psta = rtw_get_stainfo(pstapriv, get_sa(pframe)); + if (psta == NULL) + { + // allocate a new one + DBG_871X("going to alloc stainfo for rc="MAC_FMT"\n", MAC_ARG(get_sa(pframe))); + psta = rtw_alloc_stainfo(pstapriv, get_sa(pframe)); + if (psta == NULL) + { + //TODO: + DBG_871X(" Exceed the upper limit of supported clients...\n"); + return _SUCCESS; + } + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + if (rtw_is_list_empty(&psta->asoc_list)) + { + psta->expire_to = pstapriv->expire_to; + rtw_list_insert_tail(&psta->asoc_list, &pstapriv->asoc_list); + pstapriv->asoc_list_cnt++; + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + //generate pairing ID + mac_addr = adapter_mac_addr(padapter); + peer_addr = psta->hwaddr; + psta->pid = (u16)(((mac_addr[4]<<8) + mac_addr[5]) + ((peer_addr[4]<<8) + peer_addr[5])); + + //update peer stainfo + psta->isrc = _TRUE; + //psta->aid = 0; + //psta->mac_id = 2; + + /* get a unique AID */ + if (psta->aid > 0) { + DBG_871X("old AID %d\n", psta->aid); + } else { + for (psta->aid = 1; psta->aid <= NUM_STA; psta->aid++) + if (pstapriv->sta_aid[psta->aid - 1] == NULL) + break; + + if (psta->aid > pstapriv->max_num_sta) { + psta->aid = 0; + DBG_871X("no room for more AIDs\n"); + return _SUCCESS; + } else { + pstapriv->sta_aid[psta->aid - 1] = psta; + DBG_871X("allocate new AID = (%d)\n", psta->aid); + } + } + + psta->qos_option = 1; + psta->bw_mode = CHANNEL_WIDTH_20; + psta->ieee8021x_blocked = _FALSE; +#ifdef CONFIG_80211N_HT + psta->htpriv.ht_option = _TRUE; + psta->htpriv.ampdu_enable = _FALSE; + psta->htpriv.sgi_20m = _FALSE; + psta->htpriv.sgi_40m = _FALSE; + psta->htpriv.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + psta->htpriv.agg_enable_bitmap = 0x0;//reset + psta->htpriv.candidate_tid_bitmap = 0x0;//reset +#endif + + rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _TRUE); + + _rtw_memset((void*)&psta->sta_stats, 0, sizeof(struct stainfo_stats)); + + _enter_critical_bh(&psta->lock, &irqL); + psta->state |= _FW_LINKED; + _exit_critical_bh(&psta->lock, &irqL); + + report_add_sta_event(padapter, psta->hwaddr); + + } + + issue_probersp(padapter, get_sa(pframe), _FALSE); + + return _SUCCESS; + + } + +_non_rc_device: + + return _SUCCESS; + +#endif //CONFIG_AUTO_AP_MODE + + +#ifdef CONFIG_CONCURRENT_MODE + if(((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) && + check_buddy_fwstate(padapter, _FW_UNDER_LINKING|_FW_UNDER_SURVEY)) + { + //don't process probe req + return _SUCCESS; + } +#endif + + p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SSID_IE_, (int *)&ielen, + len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_); + + + //check (wildcard) SSID + if (p != NULL) + { + if(is_valid_p2p_probereq == _TRUE) + { + goto _issue_probersp; + } + + if ( (ielen != 0 && _FALSE ==_rtw_memcmp((void *)(p+2), (void *)cur->Ssid.Ssid, cur->Ssid.SsidLength)) + || (ielen == 0 && pmlmeinfo->hidden_ssid_mode) + ) + { + return _SUCCESS; + } + +_issue_probersp: + if(((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE && + pmlmepriv->cur_network.join_res == _TRUE)) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) + { + //DBG_871X("+issue_probersp during ap mode\n"); + issue_probersp(padapter, get_sa(pframe), is_valid_p2p_probereq); + } + + } + + return _SUCCESS; + +} + +unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame) +{ + struct sta_info *psta; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct sta_priv *pstapriv = &padapter->stapriv; + u8 *pframe = precv_frame->u.hdr.rx_data; +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &padapter->wdinfo; +#endif + + +#ifdef CONFIG_P2P + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) + { + if ( _TRUE == pwdinfo->tx_prov_disc_info.benable ) + { + if( _rtw_memcmp( pwdinfo->tx_prov_disc_info.peerIFAddr, GetAddr2Ptr(pframe), ETH_ALEN ) ) + { + if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) + { + pwdinfo->tx_prov_disc_info.benable = _FALSE; + issue_p2p_provision_request( padapter, + pwdinfo->tx_prov_disc_info.ssid.Ssid, + pwdinfo->tx_prov_disc_info.ssid.SsidLength, + pwdinfo->tx_prov_disc_info.peerDevAddr ); + } + else if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) ) + { + pwdinfo->tx_prov_disc_info.benable = _FALSE; + issue_p2p_provision_request( padapter, + NULL, + 0, + pwdinfo->tx_prov_disc_info.peerDevAddr ); + } + } + } + return _SUCCESS; + } + else if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) + { + if ( _TRUE == pwdinfo->nego_req_info.benable ) + { + DBG_871X( "[%s] P2P State is GONEGO ING!\n", __FUNCTION__ ); + if( _rtw_memcmp( pwdinfo->nego_req_info.peerDevAddr, GetAddr2Ptr(pframe), ETH_ALEN ) ) + { + pwdinfo->nego_req_info.benable = _FALSE; + issue_p2p_GO_request( padapter, pwdinfo->nego_req_info.peerDevAddr); + } + } + } + else if( rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_INVITE_REQ ) ) + { + if ( _TRUE == pwdinfo->invitereq_info.benable ) + { + DBG_871X( "[%s] P2P_STATE_TX_INVITE_REQ!\n", __FUNCTION__ ); + if( _rtw_memcmp( pwdinfo->invitereq_info.peer_macaddr, GetAddr2Ptr(pframe), ETH_ALEN ) ) + { + pwdinfo->invitereq_info.benable = _FALSE; + issue_p2p_invitation_request( padapter, pwdinfo->invitereq_info.peer_macaddr ); + } + } + } +#endif + + + if (mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS)) { + report_survey_event(padapter, precv_frame); +#ifdef CONFIG_CONCURRENT_MODE + report_survey_event(padapter->pbuddy_adapter, precv_frame); +#endif + return _SUCCESS; + } + + #if 0 //move to validate_recv_mgnt_frame + if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)) + { + if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) + { + if ((psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe))) != NULL) + { + psta->sta_stats.rx_mgnt_pkts++; + } + } + } + #endif + + return _SUCCESS; + +} + +unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) +{ + struct sta_info *psta; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 *pframe = precv_frame->u.hdr.rx_data; + uint len = precv_frame->u.hdr.len; + WLAN_BSSID_EX *pbss; + int ret = _SUCCESS; + u8 *p = NULL; + u32 ielen = 0; +#ifdef CONFIG_TDLS + struct sta_info *ptdls_sta; + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; +#ifdef CONFIG_TDLS_CH_SW + struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info; +#endif +#endif /* CONFIG_TDLS */ + +#ifdef CONFIG_ATTEMPT_TO_FIX_AP_BEACON_ERROR + p = rtw_get_ie(pframe + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_, _EXT_SUPPORTEDRATES_IE_, &ielen, precv_frame->u.hdr.len -sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_); + if ((p != NULL) && (ielen > 0)) + { + if ((*(p + 1 + ielen) == 0x2D) && (*(p + 2 + ielen) != 0x2D)) + { + /* Invalid value 0x2D is detected in Extended Supported Rates (ESR) IE. Try to fix the IE length to avoid failed Beacon parsing. */ + DBG_871X("[WIFIDBG] Error in ESR IE is detected in Beacon of BSSID:"MAC_FMT". Fix the length of ESR IE to avoid failed Beacon parsing.\n", MAC_ARG(GetAddr3Ptr(pframe))); + *(p + 1) = ielen - 1; + } + } +#endif + + if (mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS)) { + report_survey_event(padapter, precv_frame); +#ifdef CONFIG_CONCURRENT_MODE + report_survey_event(padapter->pbuddy_adapter, precv_frame); +#endif + return _SUCCESS; + } + + if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)) + { + if (pmlmeinfo->state & WIFI_FW_AUTH_NULL) + { + //we should update current network before auth, or some IE is wrong + pbss = (WLAN_BSSID_EX*)rtw_malloc(sizeof(WLAN_BSSID_EX)); + if (pbss) { + if (collect_bss_info(padapter, precv_frame, pbss) == _SUCCESS) { + struct beacon_keys recv_beacon; + + update_network(&(pmlmepriv->cur_network.network), pbss, padapter, _TRUE); + rtw_get_bcn_info(&(pmlmepriv->cur_network)); + + // update bcn keys + if (rtw_get_bcn_keys(padapter, pframe, len, &recv_beacon) == _TRUE) { + DBG_871X("%s: beacon keys ready\n", __func__); + _rtw_memcpy(&pmlmepriv->cur_beacon_keys, + &recv_beacon, sizeof(recv_beacon)); + pmlmepriv->new_beacon_cnts = 0; + } + else { + DBG_871X_LEVEL(_drv_err_, "%s: get beacon keys failed\n", __func__); + _rtw_memset(&pmlmepriv->cur_beacon_keys, 0, sizeof(recv_beacon)); + pmlmepriv->new_beacon_cnts = 0; + } + } + rtw_mfree((u8*)pbss, sizeof(WLAN_BSSID_EX)); + } + + //check the vendor of the assoc AP + pmlmeinfo->assoc_AP_vendor = check_assoc_AP(pframe+sizeof(struct rtw_ieee80211_hdr_3addr), len-sizeof(struct rtw_ieee80211_hdr_3addr)); + + //update TSF Value + update_TSF(pmlmeext, pframe, len); + + //reset for adaptive_early_32k + pmlmeext->adaptive_tsf_done = _FALSE; + pmlmeext->DrvBcnEarly = 0xff; + pmlmeext->DrvBcnTimeOut = 0xff; + pmlmeext->bcn_cnt = 0; + _rtw_memset(pmlmeext->bcn_delay_cnt, 0, sizeof(pmlmeext->bcn_delay_cnt)); + _rtw_memset(pmlmeext->bcn_delay_ratio, 0, sizeof(pmlmeext->bcn_delay_ratio)); + +#ifdef CONFIG_P2P_PS + process_p2p_ps_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN)); +#endif //CONFIG_P2P_PS + +#if defined(CONFIG_P2P)&&defined(CONFIG_CONCURRENT_MODE) + if (padapter->registrypriv.wifi_spec) { + if (process_p2p_cross_connect_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN)) == _FALSE) { + if((padapter->pbuddy_adapter->mlmeextpriv.mlmext_info.state&0x03) == WIFI_FW_AP_STATE) { + DBG_871X_LEVEL(_drv_always_, "no issue auth, P2P cross-connect does not permit\n "); + return _SUCCESS; + } + } + } +#endif // CONFIG_P2P CONFIG_P2P and CONFIG_CONCURRENT_MODE + + //start auth + start_clnt_auth(padapter); + + return _SUCCESS; + } + + if(((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE) && (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) + { + if ((psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe))) != NULL) + { + #ifdef CONFIG_PATCH_JOIN_WRONG_CHANNEL + //Merge from 8712 FW code + if (cmp_pkt_chnl_diff(padapter,pframe,len) != 0) + { // join wrong channel, deauth and reconnect + issue_deauth(padapter, (&(pmlmeinfo->network))->MacAddress, WLAN_REASON_DEAUTH_LEAVING); + + report_del_sta_event(padapter, (&(pmlmeinfo->network))->MacAddress, WLAN_REASON_JOIN_WRONG_CHANNEL, _TRUE, _FALSE); + pmlmeinfo->state &= (~WIFI_FW_ASSOC_SUCCESS); + return _SUCCESS; + } + #endif //CONFIG_PATCH_JOIN_WRONG_CHANNEL + + ret = rtw_check_bcn_info(padapter, pframe, len); + if (!ret) { + DBG_871X_LEVEL(_drv_always_, "ap has changed, disconnect now\n "); + receive_disconnect(padapter, pmlmeinfo->network.MacAddress , 0, _FALSE); + return _SUCCESS; + } + //update WMM, ERP in the beacon + //todo: the timer is used instead of the number of the beacon received + if ((sta_rx_pkts(psta) & 0xf) == 0) + { + //DBG_871X("update_bcn_info\n"); + update_beacon_info(padapter, pframe, len, psta); + } + + adaptive_early_32k(pmlmeext, pframe, len); + +#ifdef CONFIG_TDLS +#ifdef CONFIG_TDLS_CH_SW + if (rtw_tdls_is_chsw_allowed(padapter) == _TRUE) + { + /* Send TDLS Channel Switch Request when receiving Beacon */ + if ((padapter->tdlsinfo.chsw_info.ch_sw_state & TDLS_CH_SW_INITIATOR_STATE) && (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE) + && (pmlmeext->cur_channel == rtw_get_oper_ch(padapter))) { + ptdls_sta = rtw_get_stainfo(&padapter->stapriv, padapter->tdlsinfo.chsw_info.addr); + if (ptdls_sta != NULL) { + if (ptdls_sta->tdls_sta_state | TDLS_LINKED_STATE) { + _set_timer(&ptdls_sta->stay_on_base_chnl_timer, TDLS_CH_SW_STAY_ON_BASE_CHNL_TIMEOUT); + } + } + } + } +#endif +#endif /* CONFIG_TDLS */ + +#ifdef CONFIG_DFS + process_csa_ie(padapter, pframe, len); //channel switch announcement +#endif //CONFIG_DFS + +#ifdef CONFIG_P2P_PS + process_p2p_ps_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN)); +#endif //CONFIG_P2P_PS + + if (pmlmeext->en_hw_update_tsf) + rtw_enable_hw_update_tsf_cmd(padapter); + + #if 0 //move to validate_recv_mgnt_frame + psta->sta_stats.rx_mgnt_pkts++; + #endif + } + + } else if ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) { + _irqL irqL; + u8 rate_set[16]; + u8 rate_num = 0; + + psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe)); + if (psta != NULL) { + /* + * update WMM, ERP in the beacon + * todo: the timer is used instead of the number of the beacon received + */ + if ((sta_rx_pkts(psta) & 0xf) == 0) + update_beacon_info(padapter, pframe, len, psta); + + if (pmlmeext->en_hw_update_tsf) + rtw_enable_hw_update_tsf_cmd(padapter); + + } else { + rtw_ies_get_supported_rate(pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_, len - WLAN_HDR_A3_LEN - _BEACON_IE_OFFSET_, rate_set, &rate_num); + if (rate_num == 0) { + DBG_871X(FUNC_ADPT_FMT" RX beacon with no supported rate\n", FUNC_ADPT_ARG(padapter)); + goto _END_ONBEACON_; + } + + psta = rtw_alloc_stainfo(pstapriv, GetAddr2Ptr(pframe)); + if (psta == NULL) { + DBG_871X(FUNC_ADPT_FMT" Exceed the upper limit of supported clients\n", FUNC_ADPT_ARG(padapter)); + goto _END_ONBEACON_; + } + + psta->expire_to = pstapriv->adhoc_expire_to; + + _rtw_memcpy(psta->bssrateset, rate_set, rate_num); + psta->bssratelen = rate_num; + + //update TSF Value + update_TSF(pmlmeext, pframe, len); + + //report sta add event + report_add_sta_event(padapter, GetAddr2Ptr(pframe)); + } + } + } + +_END_ONBEACON_: + + return _SUCCESS; + +} + +unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame) +{ +#ifdef CONFIG_AP_MODE + _irqL irqL; + unsigned int auth_mode, seq, ie_len; + unsigned char *sa, *p; + u16 algorithm; + int status; + static struct sta_info stat; + struct sta_info *pstat=NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 *pframe = precv_frame->u.hdr.rx_data; + uint len = precv_frame->u.hdr.len; + u8 offset = 0; + + +#ifdef CONFIG_CONCURRENT_MODE + if(((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) && + check_buddy_fwstate(padapter, _FW_UNDER_LINKING|_FW_UNDER_SURVEY)) + { + //don't process auth request; + return _SUCCESS; + } +#endif //CONFIG_CONCURRENT_MODE + + if((pmlmeinfo->state&0x03) != WIFI_FW_AP_STATE) + return _FAIL; + + DBG_871X("+OnAuth\n"); + + sa = GetAddr2Ptr(pframe); + + auth_mode = psecuritypriv->dot11AuthAlgrthm; + + if (GetPrivacy(pframe)) + { + u8 *iv; + struct rx_pkt_attrib *prxattrib = &(precv_frame->u.hdr.attrib); + + prxattrib->hdrlen = WLAN_HDR_A3_LEN; + prxattrib->encrypt = _WEP40_; + + iv = pframe+prxattrib->hdrlen; + prxattrib->key_index = ((iv[3]>>6)&0x3); + + prxattrib->iv_len = 4; + prxattrib->icv_len = 4; + + rtw_wep_decrypt(padapter, (u8 *)precv_frame); + + offset = 4; + } + + algorithm = le16_to_cpu(*(u16*)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset)); + seq = le16_to_cpu(*(u16*)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 2)); + + DBG_871X("auth alg=%x, seq=%X\n", algorithm, seq); + + if (auth_mode == 2 && + psecuritypriv->dot11PrivacyAlgrthm != _WEP40_ && + psecuritypriv->dot11PrivacyAlgrthm != _WEP104_) + auth_mode = 0; + + if ((algorithm > 0 && auth_mode == 0) || // rx a shared-key auth but shared not enabled + (algorithm == 0 && auth_mode == 1) ) // rx a open-system auth but shared-key is enabled + { + DBG_871X("auth rejected due to bad alg [alg=%d, auth_mib=%d] %02X%02X%02X%02X%02X%02X\n", + algorithm, auth_mode, sa[0], sa[1], sa[2], sa[3], sa[4], sa[5]); + + status = _STATS_NO_SUPP_ALG_; + + goto auth_fail; + } + +#if 0 //ACL control + phead = &priv->wlan_acl_list; + plist = phead->next; + //check sa + if (acl_mode == 1) // 1: positive check, only those on acl_list can be connected. + res = FAIL; + else + res = SUCCESS; + + while(plist != phead) + { + paclnode = list_entry(plist, struct rtw_wlan_acl_node, list); + plist = plist->next; + if (!memcmp((void *)sa, paclnode->addr, 6)) { + if (paclnode->mode & 2) { // deny + res = FAIL; + break; + } + else { + res = SUCCESS; + break; + } + } + } + + if (res != SUCCESS) { + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,"auth abort because ACL!\n"); + return FAIL; + } +#else + if(rtw_access_ctrl(padapter, sa) == _FALSE) + { + status = _STATS_UNABLE_HANDLE_STA_; + goto auth_fail; + } +#endif + + pstat = rtw_get_stainfo(pstapriv, sa); + if (pstat == NULL) + { + + // allocate a new one + DBG_871X("going to alloc stainfo for sa="MAC_FMT"\n", MAC_ARG(sa)); + pstat = rtw_alloc_stainfo(pstapriv, sa); + if (pstat == NULL) + { + DBG_871X(" Exceed the upper limit of supported clients...\n"); + status = _STATS_UNABLE_HANDLE_STA_; + goto auth_fail; + } + + pstat->state = WIFI_FW_AUTH_NULL; + pstat->auth_seq = 0; + + //pstat->flags = 0; + //pstat->capability = 0; + } else { +#ifdef CONFIG_IEEE80211W + if (pstat->bpairwise_key_installed != _TRUE && !(pstat->state & WIFI_FW_ASSOC_SUCCESS)) +#endif /* CONFIG_IEEE80211W */ + { + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + if (rtw_is_list_empty(&pstat->asoc_list) == _FALSE) { + rtw_list_delete(&pstat->asoc_list); + pstapriv->asoc_list_cnt--; + if (pstat->expire_to > 0) + ;/* TODO: STA re_auth within expire_to */ + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + if (seq == 1) + ; /* TODO: STA re_auth and auth timeout */ + + } + } + +#ifdef CONFIG_IEEE80211W + if (pstat->bpairwise_key_installed != _TRUE && !(pstat->state & WIFI_FW_ASSOC_SUCCESS)) +#endif /* CONFIG_IEEE80211W */ + { + _enter_critical_bh(&pstapriv->auth_list_lock, &irqL); + if (rtw_is_list_empty(&pstat->auth_list)) { + + rtw_list_insert_tail(&pstat->auth_list, &pstapriv->auth_list); + pstapriv->auth_list_cnt++; + } + _exit_critical_bh(&pstapriv->auth_list_lock, &irqL); + } + + if (pstat->auth_seq == 0) + pstat->expire_to = pstapriv->auth_to; + + + if ((pstat->auth_seq + 1) != seq) + { + DBG_871X("(1)auth rejected because out of seq [rx_seq=%d, exp_seq=%d]!\n", + seq, pstat->auth_seq+1); + status = _STATS_OUT_OF_AUTH_SEQ_; + goto auth_fail; + } + + if (algorithm==0 && (auth_mode == 0 || auth_mode == 2 || auth_mode == 3)) + { + if (seq == 1) + { +#ifdef CONFIG_IEEE80211W + if (pstat->bpairwise_key_installed != _TRUE && !(pstat->state & WIFI_FW_ASSOC_SUCCESS)) +#endif /* CONFIG_IEEE80211W */ + { + pstat->state &= ~WIFI_FW_AUTH_NULL; + pstat->state |= WIFI_FW_AUTH_SUCCESS; + pstat->expire_to = pstapriv->assoc_to; + } + pstat->authalg = algorithm; + } + else + { + DBG_871X("(2)auth rejected because out of seq [rx_seq=%d, exp_seq=%d]!\n", + seq, pstat->auth_seq+1); + status = _STATS_OUT_OF_AUTH_SEQ_; + goto auth_fail; + } + } + else // shared system or auto authentication + { + if (seq == 1) + { + //prepare for the challenging txt... + + //get_random_bytes((void *)pstat->chg_txt, 128);//TODO: + _rtw_memset((void *)pstat->chg_txt, 78, 128); +#ifdef CONFIG_IEEE80211W + if (pstat->bpairwise_key_installed != _TRUE && !(pstat->state & WIFI_FW_ASSOC_SUCCESS)) +#endif /* CONFIG_IEEE80211W */ + { + pstat->state &= ~WIFI_FW_AUTH_NULL; + pstat->state |= WIFI_FW_AUTH_STATE; + } + pstat->authalg = algorithm; + pstat->auth_seq = 2; + } + else if (seq == 3) + { + //checking for challenging txt... + DBG_871X("checking for challenging txt...\n"); + + p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + 4 + _AUTH_IE_OFFSET_ , _CHLGETXT_IE_, (int *)&ie_len, + len - WLAN_HDR_A3_LEN - _AUTH_IE_OFFSET_ - 4); + + if((p==NULL) || (ie_len<=0)) + { + DBG_871X("auth rejected because challenge failure!(1)\n"); + status = _STATS_CHALLENGE_FAIL_; + goto auth_fail; + } + + if (_rtw_memcmp((void *)(p + 2), pstat->chg_txt, 128)) + { +#ifdef CONFIG_IEEE80211W + if (pstat->bpairwise_key_installed != _TRUE && !(pstat->state & WIFI_FW_ASSOC_SUCCESS)) +#endif /* CONFIG_IEEE80211W */ + { + pstat->state &= (~WIFI_FW_AUTH_STATE); + pstat->state |= WIFI_FW_AUTH_SUCCESS; + /* challenging txt is correct... */ + pstat->expire_to = pstapriv->assoc_to; + } + } + else + { + DBG_871X("auth rejected because challenge failure!\n"); + status = _STATS_CHALLENGE_FAIL_; + goto auth_fail; + } + } + else + { + DBG_871X("(3)auth rejected because out of seq [rx_seq=%d, exp_seq=%d]!\n", + seq, pstat->auth_seq+1); + status = _STATS_OUT_OF_AUTH_SEQ_; + goto auth_fail; + } + } + + + // Now, we are going to issue_auth... + pstat->auth_seq = seq + 1; + +#ifdef CONFIG_NATIVEAP_MLME + issue_auth(padapter, pstat, (unsigned short)(_STATS_SUCCESSFUL_)); +#endif + + if ((pstat->state & WIFI_FW_AUTH_SUCCESS) || (pstat->state & WIFI_FW_ASSOC_SUCCESS)) + pstat->auth_seq = 0; + + + return _SUCCESS; + +auth_fail: + + if(pstat) + rtw_free_stainfo(padapter , pstat); + + pstat = &stat; + _rtw_memset((char *)pstat, '\0', sizeof(stat)); + pstat->auth_seq = 2; + _rtw_memcpy(pstat->hwaddr, sa, 6); + +#ifdef CONFIG_NATIVEAP_MLME + issue_auth(padapter, pstat, (unsigned short)status); +#endif + +#endif + return _FAIL; + +} + +unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame) +{ + unsigned int seq, len, status, algthm, offset; + unsigned char *p; + unsigned int go2asoc = 0; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 *pframe = precv_frame->u.hdr.rx_data; + uint pkt_len = precv_frame->u.hdr.len; + + DBG_871X("%s\n", __FUNCTION__); + + //check A1 matches or not + if (!_rtw_memcmp(adapter_mac_addr(padapter), get_da(pframe), ETH_ALEN)) + return _SUCCESS; + + if (!(pmlmeinfo->state & WIFI_FW_AUTH_STATE)) + return _SUCCESS; + + offset = (GetPrivacy(pframe))? 4: 0; + + algthm = le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset)); + seq = le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 2)); + status = le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 4)); + + if (status != 0) + { + DBG_871X("clnt auth fail, status: %d\n", status); + if(status == 13)//&& pmlmeinfo->auth_algo == dot11AuthAlgrthm_Auto) + { + if(pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared) + pmlmeinfo->auth_algo = dot11AuthAlgrthm_Open; + else + pmlmeinfo->auth_algo = dot11AuthAlgrthm_Shared; + //pmlmeinfo->reauth_count = 0; + } + + set_link_timer(pmlmeext, 1); + goto authclnt_fail; + } + + if (seq == 2) + { + if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared) + { + // legendary shared system + p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _AUTH_IE_OFFSET_, _CHLGETXT_IE_, (int *)&len, + pkt_len - WLAN_HDR_A3_LEN - _AUTH_IE_OFFSET_); + + if (p == NULL) + { + //DBG_871X("marc: no challenge text?\n"); + goto authclnt_fail; + } + + _rtw_memcpy((void *)(pmlmeinfo->chg_txt), (void *)(p + 2), len); + pmlmeinfo->auth_seq = 3; + issue_auth(padapter, NULL, 0); + set_link_timer(pmlmeext, REAUTH_TO); + + return _SUCCESS; + } + else + { + // open system + go2asoc = 1; + } + } + else if (seq == 4) + { + if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared) + { + go2asoc = 1; + } + else + { + goto authclnt_fail; + } + } + else + { + // this is also illegal + //DBG_871X("marc: clnt auth failed due to illegal seq=%x\n", seq); + goto authclnt_fail; + } + + if (go2asoc) + { + DBG_871X_LEVEL(_drv_always_, "auth success, start assoc\n"); + start_clnt_assoc(padapter); + return _SUCCESS; + } + +authclnt_fail: + + //pmlmeinfo->state &= ~(WIFI_FW_AUTH_STATE); + + return _FAIL; + +} + +unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) +{ +#ifdef CONFIG_AP_MODE + _irqL irqL; + u16 capab_info, listen_interval; + struct rtw_ieee802_11_elems elems; + struct sta_info *pstat; + unsigned char reassoc, *p, *pos, *wpa_ie; + unsigned char WMM_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01}; + int i, ie_len, wpa_ie_len, left; + u8 rate_set[16]; + u8 rate_num; + unsigned short status = _STATS_SUCCESSFUL_; + unsigned short frame_type, ie_offset=0; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur = &(pmlmeinfo->network); + struct sta_priv *pstapriv = &padapter->stapriv; + u8 *pframe = precv_frame->u.hdr.rx_data; + uint pkt_len = precv_frame->u.hdr.len; +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + u8 p2p_status_code = P2P_STATUS_SUCCESS; + u8 *p2pie; + u32 p2pielen = 0; +#endif //CONFIG_P2P + +#ifdef CONFIG_CONCURRENT_MODE + if(((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) && + check_buddy_fwstate(padapter, _FW_UNDER_LINKING|_FW_UNDER_SURVEY)) + { + //don't process assoc request; + return _SUCCESS; + } +#endif //CONFIG_CONCURRENT_MODE + + if((pmlmeinfo->state&0x03) != WIFI_FW_AP_STATE) + return _FAIL; + + frame_type = GetFrameSubType(pframe); + if (frame_type == WIFI_ASSOCREQ) + { + reassoc = 0; + ie_offset = _ASOCREQ_IE_OFFSET_; + } + else // WIFI_REASSOCREQ + { + reassoc = 1; + ie_offset = _REASOCREQ_IE_OFFSET_; + } + + + if (pkt_len < IEEE80211_3ADDR_LEN + ie_offset) { + DBG_871X("handle_assoc(reassoc=%d) - too short payload (len=%lu)" + "\n", reassoc, (unsigned long)pkt_len); + return _FAIL; + } + + pstat = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe)); + if (pstat == (struct sta_info *)NULL) + { + status = _RSON_CLS2_; + goto asoc_class2_error; + } + + capab_info = RTW_GET_LE16(pframe + WLAN_HDR_A3_LEN); + //capab_info = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); + //listen_interval = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN+2)); + listen_interval = RTW_GET_LE16(pframe + WLAN_HDR_A3_LEN+2); + + left = pkt_len - (IEEE80211_3ADDR_LEN + ie_offset); + pos = pframe + (IEEE80211_3ADDR_LEN + ie_offset); + + + DBG_871X("%s\n", __FUNCTION__); + + // check if this stat has been successfully authenticated/assocated + if (!((pstat->state) & WIFI_FW_AUTH_SUCCESS)) + { + if (!((pstat->state) & WIFI_FW_ASSOC_SUCCESS)) + { + status = _RSON_CLS2_; + goto asoc_class2_error; + } + else + { + pstat->state &= (~WIFI_FW_ASSOC_SUCCESS); + pstat->state |= WIFI_FW_ASSOC_STATE; + } + } + else + { + pstat->state &= (~WIFI_FW_AUTH_SUCCESS); + pstat->state |= WIFI_FW_ASSOC_STATE; + } + + +#if 0// todo:tkip_countermeasures + if (hapd->tkip_countermeasures) { + resp = WLAN_REASON_MICHAEL_MIC_FAILURE; + goto fail; + } +#endif + + pstat->capability = capab_info; + +#if 0//todo: + //check listen_interval + if (listen_interval > hapd->conf->max_listen_interval) { + hostapd_logger(hapd, mgmt->sa, HOSTAPD_MODULE_IEEE80211, + HOSTAPD_LEVEL_DEBUG, + "Too large Listen Interval (%d)", + listen_interval); + resp = WLAN_STATUS_ASSOC_DENIED_LISTEN_INT_TOO_LARGE; + goto fail; + } + + pstat->listen_interval = listen_interval; +#endif + + //now parse all ieee802_11 ie to point to elems + if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed || + !elems.ssid) { + DBG_871X("STA " MAC_FMT " sent invalid association request\n", + MAC_ARG(pstat->hwaddr)); + status = _STATS_FAILURE_; + goto OnAssocReqFail; + } + + + // now we should check all the fields... + // checking SSID + p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + ie_offset, _SSID_IE_, &ie_len, + pkt_len - WLAN_HDR_A3_LEN - ie_offset); + if (p == NULL) + { + status = _STATS_FAILURE_; + } + + if (ie_len == 0) // broadcast ssid, however it is not allowed in assocreq + status = _STATS_FAILURE_; + else + { + // check if ssid match + if (!_rtw_memcmp((void *)(p+2), cur->Ssid.Ssid, cur->Ssid.SsidLength)) + status = _STATS_FAILURE_; + + if (ie_len != cur->Ssid.SsidLength) + status = _STATS_FAILURE_; + } + + if(_STATS_SUCCESSFUL_ != status) + goto OnAssocReqFail; + + rtw_ies_get_supported_rate(pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset, rate_set, &rate_num); + if (rate_num == 0) { + DBG_871X(FUNC_ADPT_FMT" RX assoc-req with no supported rate\n", FUNC_ADPT_ARG(padapter)); + status = _STATS_FAILURE_; + goto OnAssocReqFail; + } + _rtw_memcpy(pstat->bssrateset, rate_set, rate_num); + pstat->bssratelen = rate_num; + UpdateBrateTblForSoftAP(pstat->bssrateset, pstat->bssratelen); + + //check RSN/WPA/WPS + pstat->dot8021xalg = 0; + pstat->wpa_psk = 0; + pstat->wpa_group_cipher = 0; + pstat->wpa2_group_cipher = 0; + pstat->wpa_pairwise_cipher = 0; + pstat->wpa2_pairwise_cipher = 0; + _rtw_memset(pstat->wpa_ie, 0, sizeof(pstat->wpa_ie)); + if((psecuritypriv->wpa_psk & BIT(1)) && elems.rsn_ie) { + + int group_cipher=0, pairwise_cipher=0; + + wpa_ie = elems.rsn_ie; + wpa_ie_len = elems.rsn_ie_len; + + if(rtw_parse_wpa2_ie(wpa_ie-2, wpa_ie_len+2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) + { + pstat->dot8021xalg = 1;//psk, todo:802.1x + pstat->wpa_psk |= BIT(1); + + pstat->wpa2_group_cipher = group_cipher&psecuritypriv->wpa2_group_cipher; + pstat->wpa2_pairwise_cipher = pairwise_cipher&psecuritypriv->wpa2_pairwise_cipher; + + if(!pstat->wpa2_group_cipher) + status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID; + + if(!pstat->wpa2_pairwise_cipher) + status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID; + } + else + { + status = WLAN_STATUS_INVALID_IE; + } + + } else if ((psecuritypriv->wpa_psk & BIT(0)) && elems.wpa_ie) { + + int group_cipher=0, pairwise_cipher=0; + + wpa_ie = elems.wpa_ie; + wpa_ie_len = elems.wpa_ie_len; + + if(rtw_parse_wpa_ie(wpa_ie-2, wpa_ie_len+2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) + { + pstat->dot8021xalg = 1;//psk, todo:802.1x + pstat->wpa_psk |= BIT(0); + + pstat->wpa_group_cipher = group_cipher&psecuritypriv->wpa_group_cipher; + pstat->wpa_pairwise_cipher = pairwise_cipher&psecuritypriv->wpa_pairwise_cipher; + + if(!pstat->wpa_group_cipher) + status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID; + + if(!pstat->wpa_pairwise_cipher) + status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID; + + } + else + { + status = WLAN_STATUS_INVALID_IE; + } + + } else { + wpa_ie = NULL; + wpa_ie_len = 0; + } + + if(_STATS_SUCCESSFUL_ != status) + goto OnAssocReqFail; + + pstat->flags &= ~(WLAN_STA_WPS | WLAN_STA_MAYBE_WPS); + //if (hapd->conf->wps_state && wpa_ie == NULL) { //todo: to check ap if supporting WPS + if(wpa_ie == NULL) { + if (elems.wps_ie) { + DBG_871X("STA included WPS IE in " + "(Re)Association Request - assume WPS is " + "used\n"); + pstat->flags |= WLAN_STA_WPS; + //wpabuf_free(sta->wps_ie); + //sta->wps_ie = wpabuf_alloc_copy(elems.wps_ie + 4, + // elems.wps_ie_len - 4); + } else { + DBG_871X("STA did not include WPA/RSN IE " + "in (Re)Association Request - possible WPS " + "use\n"); + pstat->flags |= WLAN_STA_MAYBE_WPS; + } + + + // AP support WPA/RSN, and sta is going to do WPS, but AP is not ready + // that the selected registrar of AP is _FLASE + if((psecuritypriv->wpa_psk >0) + && (pstat->flags & (WLAN_STA_WPS|WLAN_STA_MAYBE_WPS))) + { + if(pmlmepriv->wps_beacon_ie) + { + u8 selected_registrar = 0; + + rtw_get_wps_attr_content(pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len, WPS_ATTR_SELECTED_REGISTRAR , &selected_registrar, NULL); + + if(!selected_registrar) + { + DBG_871X("selected_registrar is _FALSE , or AP is not ready to do WPS\n"); + + status = _STATS_UNABLE_HANDLE_STA_; + + goto OnAssocReqFail; + } + } + } + + } + else + { + int copy_len; + + if(psecuritypriv->wpa_psk == 0) + { + DBG_871X("STA " MAC_FMT ": WPA/RSN IE in association " + "request, but AP don't support WPA/RSN\n", MAC_ARG(pstat->hwaddr)); + + status = WLAN_STATUS_INVALID_IE; + + goto OnAssocReqFail; + + } + + if (elems.wps_ie) { + DBG_871X("STA included WPS IE in " + "(Re)Association Request - WPS is " + "used\n"); + pstat->flags |= WLAN_STA_WPS; + copy_len=0; + } + else + { + copy_len = ((wpa_ie_len+2) > sizeof(pstat->wpa_ie)) ? (sizeof(pstat->wpa_ie)):(wpa_ie_len+2); + } + + + if(copy_len>0) + _rtw_memcpy(pstat->wpa_ie, wpa_ie-2, copy_len); + + } + + + // check if there is WMM IE & support WWM-PS + pstat->flags &= ~WLAN_STA_WME; + pstat->qos_option = 0; + pstat->qos_info = 0; + pstat->has_legacy_ac = _TRUE; + pstat->uapsd_vo = 0; + pstat->uapsd_vi = 0; + pstat->uapsd_be = 0; + pstat->uapsd_bk = 0; + if (pmlmepriv->qospriv.qos_option) + { + p = pframe + WLAN_HDR_A3_LEN + ie_offset; ie_len = 0; + for (;;) + { + p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &ie_len, pkt_len - WLAN_HDR_A3_LEN - ie_offset); + if (p != NULL) { + if (_rtw_memcmp(p+2, WMM_IE, 6)) { + + pstat->flags |= WLAN_STA_WME; + + pstat->qos_option = 1; + pstat->qos_info = *(p+8); + + pstat->max_sp_len = (pstat->qos_info>>5)&0x3; + + if((pstat->qos_info&0xf) !=0xf) + pstat->has_legacy_ac = _TRUE; + else + pstat->has_legacy_ac = _FALSE; + + if(pstat->qos_info&0xf) + { + if(pstat->qos_info&BIT(0)) + pstat->uapsd_vo = BIT(0)|BIT(1); + else + pstat->uapsd_vo = 0; + + if(pstat->qos_info&BIT(1)) + pstat->uapsd_vi = BIT(0)|BIT(1); + else + pstat->uapsd_vi = 0; + + if(pstat->qos_info&BIT(2)) + pstat->uapsd_bk = BIT(0)|BIT(1); + else + pstat->uapsd_bk = 0; + + if(pstat->qos_info&BIT(3)) + pstat->uapsd_be = BIT(0)|BIT(1); + else + pstat->uapsd_be = 0; + + } + + break; + } + } + else { + break; + } + p = p + ie_len + 2; + } + } + + +#ifdef CONFIG_80211N_HT + if (pmlmepriv->htpriv.ht_option == _FALSE) + goto bypass_ht_chk; + + /* save HT capabilities in the sta object */ + _rtw_memset(&pstat->htpriv.ht_cap, 0, sizeof(struct rtw_ieee80211_ht_cap)); + if (elems.ht_capabilities && elems.ht_capabilities_len >= sizeof(struct rtw_ieee80211_ht_cap)) + { + pstat->flags |= WLAN_STA_HT; + + pstat->flags |= WLAN_STA_WME; + + _rtw_memcpy(&pstat->htpriv.ht_cap, elems.ht_capabilities, sizeof(struct rtw_ieee80211_ht_cap)); + + } else + pstat->flags &= ~WLAN_STA_HT; +bypass_ht_chk: + + if ((pmlmepriv->htpriv.ht_option == _FALSE) && (pstat->flags&WLAN_STA_HT)) { + rtw_warn_on(1); + status = _STATS_FAILURE_; + goto OnAssocReqFail; + } +#endif /* CONFIG_80211N_HT */ + +#ifdef CONFIG_80211AC_VHT + if (pmlmepriv->vhtpriv.vht_option == _FALSE) + goto bypass_vht_chk; + + _rtw_memset(&pstat->vhtpriv, 0, sizeof(struct vht_priv)); + if (elems.vht_capabilities && elems.vht_capabilities_len == 12) { + pstat->flags |= WLAN_STA_VHT; + + _rtw_memcpy(pstat->vhtpriv.vht_cap, elems.vht_capabilities, 12); + + if (elems.vht_op_mode_notify && elems.vht_op_mode_notify_len == 1) { + _rtw_memcpy(&pstat->vhtpriv.vht_op_mode_notify, elems.vht_op_mode_notify, 1); + } + else // for Frame without Operating Mode notify ie; default: 80M + { + pstat->vhtpriv.vht_op_mode_notify = CHANNEL_WIDTH_80; + } + } + else { + pstat->flags &= ~WLAN_STA_VHT; + } +bypass_vht_chk: + + if ((pmlmepriv->vhtpriv.vht_option == _FALSE) && (pstat->flags&WLAN_STA_VHT)) { + rtw_warn_on(1); + status = _STATS_FAILURE_; + goto OnAssocReqFail; + } +#endif /* CONFIG_80211AC_VHT */ + + if (((pstat->flags & WLAN_STA_HT) || (pstat->flags & WLAN_STA_VHT)) && + ((pstat->wpa2_pairwise_cipher & WPA_CIPHER_TKIP) || + (pstat->wpa_pairwise_cipher & WPA_CIPHER_TKIP))) { + + DBG_871X("(V)HT: " MAC_FMT " tried to use TKIP with (V)HT association\n", MAC_ARG(pstat->hwaddr)); + + pstat->flags &= ~WLAN_STA_HT; + pstat->flags &= ~WLAN_STA_VHT; + /*status = WLAN_STATUS_CIPHER_REJECTED_PER_POLICY; + * goto OnAssocReqFail; + */ + } + + + // + //if (hapd->iface->current_mode->mode == HOSTAPD_MODE_IEEE80211G)//? + pstat->flags |= WLAN_STA_NONERP; + for (i = 0; i < pstat->bssratelen; i++) { + if ((pstat->bssrateset[i] & 0x7f) > 22) { + pstat->flags &= ~WLAN_STA_NONERP; + break; + } + } + + if (pstat->capability & WLAN_CAPABILITY_SHORT_PREAMBLE) + pstat->flags |= WLAN_STA_SHORT_PREAMBLE; + else + pstat->flags &= ~WLAN_STA_SHORT_PREAMBLE; + + + + if (status != _STATS_SUCCESSFUL_) + goto OnAssocReqFail; + +#ifdef CONFIG_P2P + pstat->is_p2p_device = _FALSE; + if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) + { + if( (p2pie=rtw_get_p2p_ie(pframe + WLAN_HDR_A3_LEN + ie_offset , pkt_len - WLAN_HDR_A3_LEN - ie_offset , NULL, &p2pielen))) + { + pstat->is_p2p_device = _TRUE; + if((p2p_status_code=(u8)process_assoc_req_p2p_ie(pwdinfo, pframe, pkt_len, pstat))>0) + { + pstat->p2p_status_code = p2p_status_code; + status = _STATS_CAP_FAIL_; + goto OnAssocReqFail; + } + } + #ifdef CONFIG_WFD + rtw_process_wfd_ies(padapter, pframe + WLAN_HDR_A3_LEN + ie_offset, pkt_len - WLAN_HDR_A3_LEN - ie_offset, __func__); + #endif + } + pstat->p2p_status_code = p2p_status_code; +#endif //CONFIG_P2P + + //TODO: identify_proprietary_vendor_ie(); + // Realtek proprietary IE + // identify if this is Broadcom sta + // identify if this is ralink sta + // Customer proprietary IE + + + + /* get a unique AID */ + if (pstat->aid > 0) { + DBG_871X(" old AID %d\n", pstat->aid); + } else { + for (pstat->aid = 1; pstat->aid <= NUM_STA; pstat->aid++) { + if (pstapriv->sta_aid[pstat->aid - 1] == NULL) { + if (pstat->aid > pstapriv->max_num_sta) { + pstat->aid = 0; + + DBG_871X(" no room for more AIDs\n"); + + status = WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA; + + goto OnAssocReqFail; + + + } else { + pstapriv->sta_aid[pstat->aid - 1] = pstat; + DBG_871X("allocate new AID = (%d)\n", pstat->aid); + break; + } + } + } + } + + + pstat->state &= (~WIFI_FW_ASSOC_STATE); + pstat->state |= WIFI_FW_ASSOC_SUCCESS; + /* DBG_871X("==================%s, %d, (%x), bpairwise_key_installed=%d, MAC:"MAC_FMT"\n" + , __func__, __LINE__, pstat->state, pstat->bpairwise_key_installed, MAC_ARG(pstat->hwaddr)); */ +#ifdef CONFIG_IEEE80211W + if (pstat->bpairwise_key_installed != _TRUE) +#endif /* CONFIG_IEEE80211W */ + { + _enter_critical_bh(&pstapriv->auth_list_lock, &irqL); + if (!rtw_is_list_empty(&pstat->auth_list)) { + rtw_list_delete(&pstat->auth_list); + pstapriv->auth_list_cnt--; + } + _exit_critical_bh(&pstapriv->auth_list_lock, &irqL); + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + if (rtw_is_list_empty(&pstat->asoc_list)) { + pstat->expire_to = pstapriv->expire_to; + rtw_list_insert_tail(&pstat->asoc_list, &pstapriv->asoc_list); + pstapriv->asoc_list_cnt++; + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + } + + // now the station is qualified to join our BSS... + if(pstat && (pstat->state & WIFI_FW_ASSOC_SUCCESS) && (_STATS_SUCCESSFUL_==status)) + { +#ifdef CONFIG_NATIVEAP_MLME +#ifdef CONFIG_IEEE80211W + if (pstat->bpairwise_key_installed != _TRUE) +#endif /* CONFIG_IEEE80211W */ + { + /* .1 bss_cap_update & sta_info_update */ + bss_cap_update_on_sta_join(padapter, pstat); + sta_info_update(padapter, pstat); + } +#ifdef CONFIG_IEEE80211W + if (pstat->bpairwise_key_installed == _TRUE) + status = _STATS_REFUSED_TEMPORARILY_; +#endif /* CONFIG_IEEE80211W */ + //.2 issue assoc rsp before notify station join event. + if (frame_type == WIFI_ASSOCREQ) + issue_asocrsp(padapter, status, pstat, WIFI_ASSOCRSP); + else + issue_asocrsp(padapter, status, pstat, WIFI_REASSOCRSP); + +#ifdef CONFIG_IOCTL_CFG80211 + _enter_critical_bh(&pstat->lock, &irqL); + if(pstat->passoc_req) + { + rtw_mfree(pstat->passoc_req, pstat->assoc_req_len); + pstat->passoc_req = NULL; + pstat->assoc_req_len = 0; + } + + pstat->passoc_req = rtw_zmalloc(pkt_len); + if(pstat->passoc_req) + { + _rtw_memcpy(pstat->passoc_req, pframe, pkt_len); + pstat->assoc_req_len = pkt_len; + } + _exit_critical_bh(&pstat->lock, &irqL); +#endif //CONFIG_IOCTL_CFG80211 +#ifdef CONFIG_IEEE80211W + if (pstat->bpairwise_key_installed != _TRUE) +#endif /* CONFIG_IEEE80211W */ + { + /* .3-(1) report sta add event */ + report_add_sta_event(padapter, pstat->hwaddr); + } +#ifdef CONFIG_IEEE80211W + if (pstat->bpairwise_key_installed == _TRUE && padapter->securitypriv.binstallBIPkey == _TRUE) { + DBG_871X(MAC_FMT"\n", MAC_ARG(pstat->hwaddr)); + issue_action_SA_Query(padapter, pstat->hwaddr, 0, 0, IEEE80211W_RIGHT_KEY); + } +#endif /* CONFIG_IEEE80211W */ +#endif //CONFIG_NATIVEAP_MLME + } + + return _SUCCESS; + +asoc_class2_error: + +#ifdef CONFIG_NATIVEAP_MLME + issue_deauth(padapter, (void *)GetAddr2Ptr(pframe), status); +#endif + + return _FAIL; + +OnAssocReqFail: + + +#ifdef CONFIG_NATIVEAP_MLME + pstat->aid = 0; + if (frame_type == WIFI_ASSOCREQ) + issue_asocrsp(padapter, status, pstat, WIFI_ASSOCRSP); + else + issue_asocrsp(padapter, status, pstat, WIFI_REASSOCRSP); +#endif + + +#endif /* CONFIG_AP_MODE */ + + return _FAIL; + +} + +unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame) +{ + uint i; + int res; + unsigned short status; + PNDIS_802_11_VARIABLE_IEs pIE; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + //WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + u8 *pframe = precv_frame->u.hdr.rx_data; + uint pkt_len = precv_frame->u.hdr.len; + PNDIS_802_11_VARIABLE_IEs pWapiIE = NULL; + + DBG_871X("%s\n", __FUNCTION__); + + //check A1 matches or not + if (!_rtw_memcmp(adapter_mac_addr(padapter), get_da(pframe), ETH_ALEN)) + return _SUCCESS; + + if (!(pmlmeinfo->state & (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE))) + return _SUCCESS; + + if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) + return _SUCCESS; + + _cancel_timer_ex(&pmlmeext->link_timer); + + //status + if ((status = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN + 2))) > 0) + { + DBG_871X("assoc reject, status code: %d\n", status); + pmlmeinfo->state = WIFI_FW_NULL_STATE; + res = -4; + goto report_assoc_result; + } + + //get capabilities + pmlmeinfo->capability = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); + + //set slot time + pmlmeinfo->slotTime = (pmlmeinfo->capability & BIT(10))? 9: 20; + + //AID + res = pmlmeinfo->aid = (int)(le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN + 4))&0x3fff); + + //following are moved to join event callback function + //to handle HT, WMM, rate adaptive, update MAC reg + //for not to handle the synchronous IO in the tasklet + for (i = (6 + WLAN_HDR_A3_LEN); i < pkt_len;) + { + pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i); + + switch (pIE->ElementID) + { + case _VENDOR_SPECIFIC_IE_: + if (_rtw_memcmp(pIE->data, WMM_PARA_OUI, 6)) //WMM + { + WMM_param_handler(padapter, pIE); + } +#if defined(CONFIG_P2P) && defined(CONFIG_WFD) + else if ( _rtw_memcmp(pIE->data, WFD_OUI, 4)) //WFD + { + rtw_process_wfd_ie(padapter, (u8 *)pIE, pIE->Length, __func__); + } +#endif + break; + +#ifdef CONFIG_WAPI_SUPPORT + case _WAPI_IE_: + pWapiIE = pIE; + break; +#endif + + case _HT_CAPABILITY_IE_: //HT caps + HT_caps_handler(padapter, pIE); + break; + + case _HT_EXTRA_INFO_IE_: //HT info + HT_info_handler(padapter, pIE); + break; + +#ifdef CONFIG_80211AC_VHT + case EID_VHTCapability: + VHT_caps_handler(padapter, pIE); + break; + + case EID_VHTOperation: + VHT_operation_handler(padapter, pIE); + break; +#endif + + case _ERPINFO_IE_: + ERP_IE_handler(padapter, pIE); + break; +#ifdef CONFIG_TDLS + case _EXT_CAP_IE_: + if (check_ap_tdls_prohibited(pIE->data, pIE->Length) == _TRUE) + padapter->tdlsinfo.ap_prohibited = _TRUE; + if (check_ap_tdls_ch_switching_prohibited(pIE->data, pIE->Length) == _TRUE) + padapter->tdlsinfo.ch_switch_prohibited = _TRUE; + break; +#endif /* CONFIG_TDLS */ + default: + break; + } + + i += (pIE->Length + 2); + } + +#ifdef CONFIG_WAPI_SUPPORT + rtw_wapi_on_assoc_ok(padapter, pIE); +#endif + + pmlmeinfo->state &= (~WIFI_FW_ASSOC_STATE); + pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS; + + //Update Basic Rate Table for spec, 2010-12-28 , by thomas + UpdateBrateTbl(padapter, pmlmeinfo->network.SupportedRates); + +report_assoc_result: + if (res > 0) { + rtw_buf_update(&pmlmepriv->assoc_rsp, &pmlmepriv->assoc_rsp_len, pframe, pkt_len); + } else { + rtw_buf_free(&pmlmepriv->assoc_rsp, &pmlmepriv->assoc_rsp_len); + } + + report_join_res(padapter, res); + + return _SUCCESS; +} + +unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame) +{ + unsigned short reason; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 *pframe = precv_frame->u.hdr.rx_data; +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); +#endif //CONFIG_P2P + + //check A3 + if (!(_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN))) + return _SUCCESS; + + DBG_871X(FUNC_ADPT_FMT" - Start to Disconnect\n", FUNC_ADPT_ARG(padapter)); + +#ifdef CONFIG_P2P + if ( pwdinfo->rx_invitereq_info.scan_op_ch_only ) + { + _cancel_timer_ex( &pwdinfo->reset_ch_sitesurvey ); + _set_timer( &pwdinfo->reset_ch_sitesurvey, 10 ); + } +#endif //CONFIG_P2P + + reason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); + + rtw_lock_rx_suspend_timeout(8000); + +#ifdef CONFIG_AP_MODE + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + { + _irqL irqL; + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; + + //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + //rtw_free_stainfo(padapter, psta); + //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" reason=%u, ta=%pM\n" + , FUNC_ADPT_ARG(padapter), reason, GetAddr2Ptr(pframe)); + + psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe)); + if(psta) + { + u8 updated = _FALSE; + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + if(rtw_is_list_empty(&psta->asoc_list)==_FALSE) + { + rtw_list_delete(&psta->asoc_list); + pstapriv->asoc_list_cnt--; + updated = ap_free_sta(padapter, psta, _FALSE, reason, _TRUE); + + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL); + } + + + return _SUCCESS; + } + else +#endif + { + int ignore_received_deauth = 0; + + // Commented by Albert 20130604 + // Before sending the auth frame to start the STA/GC mode connection with AP/GO, + // we will send the deauth first. + // However, the Win8.1 with BRCM Wi-Fi will send the deauth with reason code 6 to us after receieving our deauth. + // Added the following code to avoid this case. + if ( ( pmlmeinfo->state & WIFI_FW_AUTH_STATE ) || + ( pmlmeinfo->state & WIFI_FW_ASSOC_STATE ) ) + { + if ( reason == WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA ) + { + ignore_received_deauth = 1; + } else if (WLAN_REASON_PREV_AUTH_NOT_VALID == reason) { + // TODO: 802.11r + ignore_received_deauth = 1; + } + } + + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" reason=%u, ta=%pM, ignore=%d\n" + , FUNC_ADPT_ARG(padapter), reason, GetAddr2Ptr(pframe), ignore_received_deauth); + + if ( 0 == ignore_received_deauth ) + { + receive_disconnect(padapter, GetAddr2Ptr(pframe), reason, _FALSE); + } + } + pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE; + return _SUCCESS; + +} + +unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame) +{ + unsigned short reason; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 *pframe = precv_frame->u.hdr.rx_data; +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); +#endif //CONFIG_P2P + + //check A3 + if (!(_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN))) + return _SUCCESS; + + DBG_871X(FUNC_ADPT_FMT" - Start to Disconnect\n", FUNC_ADPT_ARG(padapter)); + +#ifdef CONFIG_P2P + if ( pwdinfo->rx_invitereq_info.scan_op_ch_only ) + { + _cancel_timer_ex( &pwdinfo->reset_ch_sitesurvey ); + _set_timer( &pwdinfo->reset_ch_sitesurvey, 10 ); + } +#endif //CONFIG_P2P + + reason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); + + rtw_lock_rx_suspend_timeout(8000); + +#ifdef CONFIG_AP_MODE + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + { + _irqL irqL; + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; + + //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + //rtw_free_stainfo(padapter, psta); + //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" reason=%u, ta=%pM\n" + , FUNC_ADPT_ARG(padapter), reason, GetAddr2Ptr(pframe)); + + psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe)); + if(psta) + { + u8 updated = _FALSE; + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + if(rtw_is_list_empty(&psta->asoc_list)==_FALSE) + { + rtw_list_delete(&psta->asoc_list); + pstapriv->asoc_list_cnt--; + updated = ap_free_sta(padapter, psta, _FALSE, reason, _TRUE); + + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL); + } + + return _SUCCESS; + } + else +#endif + { + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" reason=%u, ta=%pM\n" + , FUNC_ADPT_ARG(padapter), reason, GetAddr2Ptr(pframe)); + + receive_disconnect(padapter, GetAddr2Ptr(pframe), reason, _FALSE); + } + pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE; + return _SUCCESS; + +} + +unsigned int OnAtim(_adapter *padapter, union recv_frame *precv_frame) +{ + DBG_871X("%s\n", __FUNCTION__); + return _SUCCESS; +} + +unsigned int on_action_spct_ch_switch(_adapter *padapter, struct sta_info *psta, u8 *ies, uint ies_len) +{ + unsigned int ret = _FAIL; + struct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(mlmeext->mlmext_info); + + if (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) { + ret = _SUCCESS; + goto exit; + } + + if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) { + + int ch_switch_mode = -1, ch = -1, ch_switch_cnt = -1; + int ch_offset = -1; + u8 bwmode; + struct ieee80211_info_element *ie; + + DBG_871X(FUNC_NDEV_FMT" from "MAC_FMT"\n", + FUNC_NDEV_ARG(padapter->pnetdev), MAC_ARG(psta->hwaddr)); + + for_each_ie(ie, ies, ies_len) { + if (ie->id == WLAN_EID_CHANNEL_SWITCH) { + ch_switch_mode = ie->data[0]; + ch = ie->data[1]; + ch_switch_cnt = ie->data[2]; + DBG_871X("ch_switch_mode:%d, ch:%d, ch_switch_cnt:%d\n", + ch_switch_mode, ch, ch_switch_cnt); + } + else if (ie->id == WLAN_EID_SECONDARY_CHANNEL_OFFSET) { + ch_offset = secondary_ch_offset_to_hal_ch_offset(ie->data[0]); + DBG_871X("ch_offset:%d\n", ch_offset); + } + } + + if (ch == -1) + return _SUCCESS; + + if (ch_offset == -1) + bwmode = mlmeext->cur_bwmode; + else + bwmode = (ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) ? + CHANNEL_WIDTH_20 : CHANNEL_WIDTH_40; + + ch_offset = (ch_offset == -1) ? mlmeext->cur_ch_offset : ch_offset; + + /* todo: + * 1. the decision of channel switching + * 2. things after channel switching + */ + + ret = rtw_set_ch_cmd(padapter, ch, bwmode, ch_offset, _TRUE); + } + +exit: + return ret; +} + +unsigned int on_action_spct(_adapter *padapter, union recv_frame *precv_frame) +{ + unsigned int ret = _FAIL; + struct sta_info *psta = NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 *pframe = precv_frame->u.hdr.rx_data; + uint frame_len = precv_frame->u.hdr.len; + u8 *frame_body = (u8 *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + u8 category; + u8 action; + + DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(padapter->pnetdev)); + + psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe)); + + if (!psta) + goto exit; + + category = frame_body[0]; + if(category != RTW_WLAN_CATEGORY_SPECTRUM_MGMT) + goto exit; + + action = frame_body[1]; + switch (action) { + case RTW_WLAN_ACTION_SPCT_MSR_REQ: + case RTW_WLAN_ACTION_SPCT_MSR_RPRT: + case RTW_WLAN_ACTION_SPCT_TPC_REQ: + case RTW_WLAN_ACTION_SPCT_TPC_RPRT: + break; + case RTW_WLAN_ACTION_SPCT_CHL_SWITCH: + #ifdef CONFIG_SPCT_CH_SWITCH + ret = on_action_spct_ch_switch(padapter, psta, &frame_body[2], + frame_len-(frame_body-pframe)-2); + #endif + break; + default: + break; + } + +exit: + return ret; +} + +unsigned int OnAction_qos(_adapter *padapter, union recv_frame *precv_frame) +{ + return _SUCCESS; +} + +unsigned int OnAction_dls(_adapter *padapter, union recv_frame *precv_frame) +{ + return _SUCCESS; +} + +/** + * rtw_rx_ampdu_size - Get the target RX AMPDU buffer size for the specific @adapter + * @adapter: the adapter to get target RX AMPDU buffer size + * + * Returns: the target RX AMPDU buffer size + */ +u8 rtw_rx_ampdu_size(_adapter *adapter) +{ + u8 size; + HT_CAP_AMPDU_FACTOR max_rx_ampdu_factor; + + if (adapter->fix_rx_ampdu_size != RX_AMPDU_SIZE_INVALID) { + size = adapter->fix_rx_ampdu_size; + goto exit; + } + +#ifdef CONFIG_BT_COEXIST + if (rtw_btcoex_IsBTCoexCtrlAMPDUSize(adapter) == _TRUE) { + size = rtw_btcoex_GetAMPDUSize(adapter); + goto exit; + } +#endif + + /* for scan */ + if (!mlmeext_chk_scan_state(&adapter->mlmeextpriv, SCAN_DISABLE) + && !mlmeext_chk_scan_state(&adapter->mlmeextpriv, SCAN_COMPLETE) + && adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_size != RX_AMPDU_SIZE_INVALID + ) { + size = adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_size; + goto exit; + } + + /* default value based on max_rx_ampdu_factor */ + if (adapter->driver_rx_ampdu_factor != 0xFF) + max_rx_ampdu_factor = (HT_CAP_AMPDU_FACTOR)adapter->driver_rx_ampdu_factor; + else + rtw_hal_get_def_var(adapter, HW_VAR_MAX_RX_AMPDU_FACTOR, &max_rx_ampdu_factor); + + if (MAX_AMPDU_FACTOR_64K == max_rx_ampdu_factor) + size = 64; + else if (MAX_AMPDU_FACTOR_32K == max_rx_ampdu_factor) + size = 32; + else if (MAX_AMPDU_FACTOR_16K == max_rx_ampdu_factor) + size = 16; + else if (MAX_AMPDU_FACTOR_8K == max_rx_ampdu_factor) + size = 8; + else + size = 64; + +exit: + + if (size > 127) + size = 127; + + return size; +} + +/** + * rtw_rx_ampdu_is_accept - Get the permission if RX AMPDU should be set up for the specific @adapter + * @adapter: the adapter to get the permission if RX AMPDU should be set up + * + * Returns: accept or not + */ +bool rtw_rx_ampdu_is_accept(_adapter *adapter) +{ + bool accept; + + if (adapter->fix_rx_ampdu_accept != RX_AMPDU_ACCEPT_INVALID) { + accept = adapter->fix_rx_ampdu_accept; + goto exit; + } + +#ifdef CONFIG_BT_COEXIST + if (rtw_btcoex_IsBTCoexRejectAMPDU(adapter) == _TRUE) { + accept = _FALSE; + goto exit; + } +#endif + + /* for scan */ + if (!mlmeext_chk_scan_state(&adapter->mlmeextpriv, SCAN_DISABLE) + && !mlmeext_chk_scan_state(&adapter->mlmeextpriv, SCAN_COMPLETE) + && adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_accept != RX_AMPDU_ACCEPT_INVALID + ) { + accept = adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_accept; + goto exit; + } + + /* default value for other cases */ + accept = adapter->mlmeextpriv.mlmext_info.bAcceptAddbaReq; + +exit: + return accept; +} + +/** + * rtw_rx_ampdu_set_size - Set the target RX AMPDU buffer size for the specific @adapter and specific @reason + * @adapter: the adapter to set target RX AMPDU buffer size + * @size: the target RX AMPDU buffer size to set + * @reason: reason for the target RX AMPDU buffer size setting + * + * Returns: whether the target RX AMPDU buffer size is changed + */ +bool rtw_rx_ampdu_set_size(_adapter *adapter, u8 size, u8 reason) +{ + bool is_adj = _FALSE; + struct mlme_ext_priv *mlmeext; + struct mlme_ext_info *mlmeinfo; + + mlmeext = &adapter->mlmeextpriv; + mlmeinfo = &mlmeext->mlmext_info; + + if (reason == RX_AMPDU_DRV_FIXED) { + if (adapter->fix_rx_ampdu_size != size) { + adapter->fix_rx_ampdu_size = size; + is_adj = _TRUE; + DBG_871X(FUNC_ADPT_FMT" fix_rx_ampdu_size:%u\n", FUNC_ADPT_ARG(adapter), size); + } + } else if (reason == RX_AMPDU_DRV_SCAN) { + struct ss_res *ss = &adapter->mlmeextpriv.sitesurvey_res; + + if (ss->rx_ampdu_size != size) { + ss->rx_ampdu_size = size; + is_adj = _TRUE; + DBG_871X(FUNC_ADPT_FMT" ss.rx_ampdu_size:%u\n", FUNC_ADPT_ARG(adapter), size); + } + } + + return is_adj; +} + +/** + * rtw_rx_ampdu_set_accept - Set the permission if RX AMPDU should be set up for the specific @adapter and specific @reason + * @adapter: the adapter to set if RX AMPDU should be set up + * @accept: if RX AMPDU should be set up + * @reason: reason for the permission if RX AMPDU should be set up + * + * Returns: whether the permission if RX AMPDU should be set up is changed + */ +bool rtw_rx_ampdu_set_accept(_adapter *adapter, u8 accept, u8 reason) +{ + bool is_adj = _FALSE; + struct mlme_ext_priv *mlmeext; + struct mlme_ext_info *mlmeinfo; + + mlmeext = &adapter->mlmeextpriv; + mlmeinfo = &mlmeext->mlmext_info; + + if (reason == RX_AMPDU_DRV_FIXED) { + if (adapter->fix_rx_ampdu_accept != accept) { + adapter->fix_rx_ampdu_accept = accept; + is_adj = _TRUE; + DBG_871X(FUNC_ADPT_FMT" fix_rx_ampdu_accept:%u\n", FUNC_ADPT_ARG(adapter), accept); + } + } else if (reason == RX_AMPDU_DRV_SCAN) { + if (adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_accept != accept) { + adapter->mlmeextpriv.sitesurvey_res.rx_ampdu_accept = accept; + is_adj = _TRUE; + DBG_871X(FUNC_ADPT_FMT" ss.rx_ampdu_accept:%u\n", FUNC_ADPT_ARG(adapter), accept); + } + } + + return is_adj; +} + +/** + * rx_ampdu_apply_sta_tid - Apply RX AMPDU setting to the specific @sta and @tid + * @adapter: the adapter to which @sta belongs + * @sta: the sta to be checked + * @tid: the tid to be checked + * @accept: the target permission if RX AMPDU should be set up + * @size: the target RX AMPDU buffer size + * + * Returns: + * 0: no canceled + * 1: canceled by no permission + * 2: canceled by different buffer size + * 3: canceled by potential mismatched status + * + * Blocking function, may sleep + */ +u8 rx_ampdu_apply_sta_tid(_adapter *adapter, struct sta_info *sta, u8 tid, u8 accept, u8 size) +{ + u8 ret = 0; + struct recv_reorder_ctrl *reorder_ctl = &sta->recvreorder_ctrl[tid]; + + if (reorder_ctl->enable == _FALSE) { + if (reorder_ctl->ampdu_size != RX_AMPDU_SIZE_INVALID) { + send_delba_sta_tid_wait_ack(adapter, 0, sta, tid, 1); + ret = 3; + } + goto exit; + } + + if (accept == _FALSE) { + send_delba_sta_tid_wait_ack(adapter, 0, sta, tid, 0); + ret = 1; + } else if (reorder_ctl->ampdu_size != size) { + send_delba_sta_tid_wait_ack(adapter, 0, sta, tid, 0); + ret = 2; + } + +exit: + return ret; +} + +/** + * rx_ampdu_apply_sta - Apply RX AMPDU setting to the specific @sta + * @adapter: the adapter to which @sta belongs + * @sta: the sta to be checked + * @accept: the target permission if RX AMPDU should be set up + * @size: the target RX AMPDU buffer size + * + * Returns: number of the RX AMPDU assciation canceled for applying current target setting + * + * Blocking function, may sleep + */ +u8 rx_ampdu_apply_sta(_adapter *adapter, struct sta_info *sta, u8 accept, u8 size) +{ + u8 change_cnt = 0; + int i; + + for (i = 0; i < TID_NUM; i++) { + if (rx_ampdu_apply_sta_tid(adapter, sta, i, accept, size) != 0) + change_cnt++; + } + + return change_cnt; +} + +/** + * rtw_rx_ampdu_apply - Apply the current target RX AMPDU setting for the specific @adapter + * @adapter: the adapter to be applied + * + * Returns: number of the RX AMPDU assciation canceled for applying current target setting + */ +u16 rtw_rx_ampdu_apply(_adapter *adapter) +{ + u16 adj_cnt = 0; + struct mlme_ext_priv *mlmeext; + struct sta_info *sta; + u8 accept = rtw_rx_ampdu_is_accept(adapter); + u8 size = rtw_rx_ampdu_size(adapter); + + mlmeext = &adapter->mlmeextpriv; + + if (mlmeext_msr(mlmeext) == WIFI_FW_STATION_STATE) { + sta = rtw_get_stainfo(&adapter->stapriv, get_bssid(&adapter->mlmepriv)); + if (sta) + adj_cnt += rx_ampdu_apply_sta(adapter, sta, accept, size); + + } else if (mlmeext_msr(mlmeext) == WIFI_FW_AP_STATE) { + _irqL irqL; + _list *phead, *plist; + u8 peer_num = 0; + char peers[NUM_STA]; + struct sta_priv *pstapriv = &adapter->stapriv; + int i; + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + phead = &pstapriv->asoc_list; + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + int stainfo_offset; + + sta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + plist = get_next(plist); + + stainfo_offset = rtw_stainfo_offset(pstapriv, sta); + if (stainfo_offset_valid(stainfo_offset)) + peers[peer_num++] = stainfo_offset; + } + + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + for (i = 0; i < peer_num; i++) { + sta = rtw_get_stainfo_by_offset(pstapriv, peers[i]); + if (sta) + adj_cnt += rx_ampdu_apply_sta(adapter, sta, accept, size); + } + } + + return adj_cnt; +} + +unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame) +{ + u8 *addr; + struct sta_info *psta=NULL; + struct recv_reorder_ctrl *preorder_ctrl; + unsigned char *frame_body; + unsigned char category, action; + unsigned short tid, status, reason_code = 0; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 *pframe = precv_frame->u.hdr.rx_data; + struct sta_priv *pstapriv = &padapter->stapriv; +#ifdef CONFIG_80211N_HT + + DBG_871X("%s\n", __FUNCTION__); + + //check RA matches or not + if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN)) + return _SUCCESS; + +/* + //check A1 matches or not + if (!_rtw_memcmp(adapter_mac_addr(padapter), get_da(pframe), ETH_ALEN)) + return _SUCCESS; +*/ + + if((pmlmeinfo->state&0x03) != WIFI_FW_AP_STATE) + if (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) + return _SUCCESS; + + addr = GetAddr2Ptr(pframe); + psta = rtw_get_stainfo(pstapriv, addr); + + if(psta==NULL) + return _SUCCESS; + + frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + + category = frame_body[0]; + if (category == RTW_WLAN_CATEGORY_BACK)// representing Block Ack + { +#ifdef CONFIG_TDLS + if((psta->tdls_sta_state & TDLS_LINKED_STATE) && + (psta->htpriv.ht_option==_TRUE) && + (psta->htpriv.ampdu_enable==_TRUE)) + { + DBG_871X("Recv [%s] from direc link\n", __FUNCTION__); + } + else +#endif //CONFIG_TDLS + if (!pmlmeinfo->HT_enable) + { + return _SUCCESS; + } + + action = frame_body[1]; + DBG_871X("%s, action=%d\n", __FUNCTION__, action); + switch (action) + { + case RTW_WLAN_ACTION_ADDBA_REQ: //ADDBA request + + _rtw_memcpy(&(pmlmeinfo->ADDBA_req), &(frame_body[2]), sizeof(struct ADDBA_request)); + //process_addba_req(padapter, (u8*)&(pmlmeinfo->ADDBA_req), GetAddr3Ptr(pframe)); + process_addba_req(padapter, (u8*)&(pmlmeinfo->ADDBA_req), addr); + + break; + + case RTW_WLAN_ACTION_ADDBA_RESP: //ADDBA response + + //status = frame_body[3] | (frame_body[4] << 8); //endian issue + status = RTW_GET_LE16(&frame_body[3]); + tid = ((frame_body[5] >> 2) & 0x7); + + if (status == 0) + { //successful + DBG_871X("agg_enable for TID=%d\n", tid); + psta->htpriv.agg_enable_bitmap |= 1 << tid; + psta->htpriv.candidate_tid_bitmap &= ~BIT(tid); + } + else + { + psta->htpriv.agg_enable_bitmap &= ~BIT(tid); + } + + if(psta->state & WIFI_STA_ALIVE_CHK_STATE) + { + DBG_871X("%s alive check - rx ADDBA response\n", __func__); + psta->htpriv.agg_enable_bitmap &= ~BIT(tid); + psta->expire_to = pstapriv->expire_to; + psta->state ^= WIFI_STA_ALIVE_CHK_STATE; + } + + //DBG_871X("marc: ADDBA RSP: %x\n", pmlmeinfo->agg_enable_bitmap); + break; + + case RTW_WLAN_ACTION_DELBA: //DELBA + if ((frame_body[3] & BIT(3)) == 0) + { + psta->htpriv.agg_enable_bitmap &= ~(1 << ((frame_body[3] >> 4) & 0xf)); + psta->htpriv.candidate_tid_bitmap &= ~(1 << ((frame_body[3] >> 4) & 0xf)); + + //reason_code = frame_body[4] | (frame_body[5] << 8); + reason_code = RTW_GET_LE16(&frame_body[4]); + } + else if((frame_body[3] & BIT(3)) == BIT(3)) + { + tid = (frame_body[3] >> 4) & 0x0F; + + preorder_ctrl = &psta->recvreorder_ctrl[tid]; + preorder_ctrl->enable = _FALSE; + preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID; + } + + DBG_871X("%s(): DELBA: %x(%x)\n", __FUNCTION__,pmlmeinfo->agg_enable_bitmap, reason_code); + //todo: how to notify the host while receiving DELETE BA + break; + + default: + break; + } + } +#endif //CONFIG_80211N_HT + return _SUCCESS; +} + +#ifdef CONFIG_P2P + +static int get_reg_classes_full_count(struct p2p_channels channel_list) { + int cnt = 0; + int i; + + for (i = 0; i < channel_list.reg_classes; i++) { + cnt += channel_list.reg_class[i].channels; + } + + return cnt; +} + +static void get_channel_cnt_24g_5gl_5gh( struct mlme_ext_priv *pmlmeext, u8* p24g_cnt, u8* p5gl_cnt, u8* p5gh_cnt ) +{ + int i = 0; + + *p24g_cnt = 0; + *p5gl_cnt = 0; + *p5gh_cnt = 0; + + for( i = 0; i < pmlmeext->max_chan_nums; i++ ) + { + if ( pmlmeext->channel_set[ i ].ChannelNum <= 14 ) + { + (*p24g_cnt)++; + } + else if ( ( pmlmeext->channel_set[ i ].ChannelNum > 14 ) && ( pmlmeext->channel_set[ i ].ChannelNum <= 48 ) ) + { + // Just include the channel 36, 40, 44, 48 channels for 5G low + (*p5gl_cnt)++; + } + else if ( ( pmlmeext->channel_set[ i ].ChannelNum >= 149 ) && ( pmlmeext->channel_set[ i ].ChannelNum <= 161 ) ) + { + // Just include the channel 149, 153, 157, 161 channels for 5G high + (*p5gh_cnt)++; + } + } +} + +void issue_p2p_GO_request(_adapter *padapter, u8* raddr) +{ + + unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; + u8 action = P2P_PUB_ACTION_ACTION; + u32 p2poui = cpu_to_be32(P2POUI); + u8 oui_subtype = P2P_GO_NEGO_REQ; + u8 wpsie[ 255 ] = { 0x00 }, p2pie[ 255 ] = { 0x00 }; + u8 wpsielen = 0, p2pielen = 0, i; + u8 channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh = 0; + u16 len_channellist_attr = 0; +#ifdef CONFIG_WFD + u32 wfdielen = 0; +#endif + + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct wifidirect_info *pwdinfo = &( padapter->wdinfo); + + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + { + return; + } + + DBG_871X( "[%s] In\n", __FUNCTION__ ); + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); + pwdinfo->negotiation_dialog_token = 1; // Initialize the dialog value + pframe = rtw_set_fixed_ie(pframe, 1, &pwdinfo->negotiation_dialog_token, &(pattrib->pktlen)); + + + + // WPS Section + wpsielen = 0; + // WPS OUI + *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); + wpsielen += 4; + + // WPS version + // Type: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 ); + wpsielen += 2; + + // Length: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); + wpsielen += 2; + + // Value: + wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0 + + // Device Password ID + // Type: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_DEVICE_PWID ); + wpsielen += 2; + + // Length: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); + wpsielen += 2; + + // Value: + + if ( pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PEER_DISPLAY_PIN ) + { + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_DPID_USER_SPEC ); + } + else if ( pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_SELF_DISPLAY_PIN ) + { + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_DPID_REGISTRAR_SPEC ); + } + else if ( pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PBC ) + { + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_DPID_PBC ); + } + + wpsielen += 2; + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen ); + + + // P2P IE Section. + + // P2P OUI + p2pielen = 0; + p2pie[ p2pielen++ ] = 0x50; + p2pie[ p2pielen++ ] = 0x6F; + p2pie[ p2pielen++ ] = 0x9A; + p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 + + // Commented by Albert 20110306 + // According to the P2P Specification, the group negoitation request frame should contain 9 P2P attributes + // 1. P2P Capability + // 2. Group Owner Intent + // 3. Configuration Timeout + // 4. Listen Channel + // 5. Extended Listen Timing + // 6. Intended P2P Interface Address + // 7. Channel List + // 8. P2P Device Info + // 9. Operating Channel + + + // P2P Capability + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); + p2pielen += 2; + + // Value: + // Device Capability Bitmap, 1 byte + p2pie[ p2pielen++ ] = DMP_P2P_DEVCAP_SUPPORT; + + // Group Capability Bitmap, 1 byte + if ( pwdinfo->persistent_supported ) + { + p2pie[ p2pielen++ ] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP; + } + else + { + p2pie[ p2pielen++ ] = P2P_GRPCAP_CROSS_CONN; + } + + + // Group Owner Intent + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_GO_INTENT; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0001 ); + p2pielen += 2; + + // Value: + // Todo the tie breaker bit. + p2pie[ p2pielen++ ] = ( ( pwdinfo->intent << 1 ) & 0xFE ); + + // Configuration Timeout + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_CONF_TIMEOUT; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); + p2pielen += 2; + + // Value: + p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P GO + p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P Client + + + // Listen Channel + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_LISTEN_CH; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 ); + p2pielen += 2; + + // Value: + // Country String + p2pie[ p2pielen++ ] = 'X'; + p2pie[ p2pielen++ ] = 'X'; + + // The third byte should be set to 0x04. + // Described in the "Operating Channel Attribute" section. + p2pie[ p2pielen++ ] = 0x04; + + // Operating Class + p2pie[ p2pielen++ ] = 0x51; // Copy from SD7 + + // Channel Number + p2pie[ p2pielen++ ] = pwdinfo->listen_channel; // listening channel number + + + // Extended Listen Timing ATTR + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_EX_LISTEN_TIMING; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0004 ); + p2pielen += 2; + + // Value: + // Availability Period + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); + p2pielen += 2; + + // Availability Interval + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); + p2pielen += 2; + + + // Intended P2P Interface Address + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_INTENTED_IF_ADDR; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN ); + p2pielen += 2; + + // Value: + _rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN); + p2pielen += ETH_ALEN; + + + // Channel List + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_CH_LIST; + + // Length: + // Country String(3) + // + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) + // + number of channels in all classes + len_channellist_attr = 3 + + (1 + 1) * (u16)(pmlmeext->channel_list.reg_classes) + + get_reg_classes_full_count(pmlmeext->channel_list); + +#ifdef CONFIG_CONCURRENT_MODE + if (check_buddy_fwstate(padapter , _FW_LINKED) + && padapter->registrypriv.full_ch_in_p2p_handshake == 0) + { + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 5 + 1 ); + } + else + { + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( len_channellist_attr ); + } +#else + + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( len_channellist_attr ); + +#endif + p2pielen += 2; + + // Value: + // Country String + p2pie[ p2pielen++ ] = 'X'; + p2pie[ p2pielen++ ] = 'X'; + + // The third byte should be set to 0x04. + // Described in the "Operating Channel Attribute" section. + p2pie[ p2pielen++ ] = 0x04; + + // Channel Entry List + +#ifdef CONFIG_CONCURRENT_MODE + if (check_buddy_fwstate(padapter , _FW_LINKED) + && padapter->registrypriv.full_ch_in_p2p_handshake == 0) + { + _adapter *pbuddy_adapter = padapter->pbuddy_adapter; + struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; + + // Operating Class + if ( pbuddy_mlmeext->cur_channel > 14 ) + { + if ( pbuddy_mlmeext->cur_channel >= 149 ) + { + p2pie[ p2pielen++ ] = 0x7c; + } + else + { + p2pie[ p2pielen++ ] = 0x73; + } + } + else + { + p2pie[ p2pielen++ ] = 0x51; + } + + // Number of Channels + // Just support 1 channel and this channel is AP's channel + p2pie[ p2pielen++ ] = 1; + + // Channel List + p2pie[ p2pielen++ ] = pbuddy_mlmeext->cur_channel; + } + else + { + int i,j; + for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { + // Operating Class + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; + + // Number of Channels + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; + + // Channel List + for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) { + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; + } + } + } +#else // CONFIG_CONCURRENT_MODE + { + int i,j; + for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { + // Operating Class + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; + + // Number of Channels + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; + + // Channel List + for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) { + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; + } + } + } +#endif // CONFIG_CONCURRENT_MODE + + // Device Info + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO; + + // Length: + // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) + // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); + p2pielen += 2; + + // Value: + // P2P Device Address + _rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN); + p2pielen += ETH_ALEN; + + // Config Method + // This field should be big endian. Noted by P2P specification. + + *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->supported_wps_cm ); + + p2pielen += 2; + + // Primary Device Type + // Category ID + *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); + p2pielen += 2; + + // OUI + *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); + p2pielen += 4; + + // Sub Category ID + *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); + p2pielen += 2; + + // Number of Secondary Device Types + p2pie[ p2pielen++ ] = 0x00; // No Secondary Device Type List + + // Device Name + // Type: + *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); + p2pielen += 2; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); + p2pielen += 2; + + // Value: + _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_name , pwdinfo->device_name_len ); + p2pielen += pwdinfo->device_name_len; + + + // Operating Channel + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_OPERATING_CH; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 ); + p2pielen += 2; + + // Value: + // Country String + p2pie[ p2pielen++ ] = 'X'; + p2pie[ p2pielen++ ] = 'X'; + + // The third byte should be set to 0x04. + // Described in the "Operating Channel Attribute" section. + p2pie[ p2pielen++ ] = 0x04; + + // Operating Class + if ( pwdinfo->operating_channel <= 14 ) + { + // Operating Class + p2pie[ p2pielen++ ] = 0x51; + } + else if ( ( pwdinfo->operating_channel >= 36 ) && ( pwdinfo->operating_channel <= 48 ) ) + { + // Operating Class + p2pie[ p2pielen++ ] = 0x73; + } + else + { + // Operating Class + p2pie[ p2pielen++ ] = 0x7c; + } + + // Channel Number + p2pie[ p2pielen++ ] = pwdinfo->operating_channel; // operating channel number + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen ); + +#ifdef CONFIG_WFD + wfdielen = build_nego_req_wfd_ie(pwdinfo, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; +#endif + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + + return; + +} + + +void issue_p2p_GO_response(_adapter *padapter, u8* raddr, u8* frame_body,uint len, u8 result) +{ + + unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; + u8 action = P2P_PUB_ACTION_ACTION; + u32 p2poui = cpu_to_be32(P2POUI); + u8 oui_subtype = P2P_GO_NEGO_RESP; + u8 wpsie[ 255 ] = { 0x00 }, p2pie[ 255 ] = { 0x00 }; + u8 p2pielen = 0, i; + uint wpsielen = 0; + u16 wps_devicepassword_id = 0x0000; + uint wps_devicepassword_id_len = 0; + u8 channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh; + u16 len_channellist_attr = 0; + + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct wifidirect_info *pwdinfo = &( padapter->wdinfo); + +#ifdef CONFIG_WFD + u32 wfdielen = 0; +#endif + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + { + return; + } + + DBG_871X( "[%s] In, result = %d\n", __FUNCTION__, result ); + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); + pwdinfo->negotiation_dialog_token = frame_body[7]; // The Dialog Token of provisioning discovery request frame. + pframe = rtw_set_fixed_ie(pframe, 1, &(pwdinfo->negotiation_dialog_token), &(pattrib->pktlen)); + + // Commented by Albert 20110328 + // Try to get the device password ID from the WPS IE of group negotiation request frame + // WiFi Direct test plan 5.1.15 + rtw_get_wps_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, wpsie, &wpsielen); + rtw_get_wps_attr_content( wpsie, wpsielen, WPS_ATTR_DEVICE_PWID, (u8*) &wps_devicepassword_id, &wps_devicepassword_id_len); + wps_devicepassword_id = be16_to_cpu( wps_devicepassword_id ); + + _rtw_memset( wpsie, 0x00, 255 ); + wpsielen = 0; + + // WPS Section + wpsielen = 0; + // WPS OUI + *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); + wpsielen += 4; + + // WPS version + // Type: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 ); + wpsielen += 2; + + // Length: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); + wpsielen += 2; + + // Value: + wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0 + + // Device Password ID + // Type: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_DEVICE_PWID ); + wpsielen += 2; + + // Length: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); + wpsielen += 2; + + // Value: + if ( wps_devicepassword_id == WPS_DPID_USER_SPEC ) + { + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_DPID_REGISTRAR_SPEC ); + } + else if ( wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC ) + { + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_DPID_USER_SPEC ); + } + else + { + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_DPID_PBC ); + } + wpsielen += 2; + + // Commented by Kurt 20120113 + // If some device wants to do p2p handshake without sending prov_disc_req + // We have to get peer_req_cm from here. + if(_rtw_memcmp( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "000", 3) ) + { + if ( wps_devicepassword_id == WPS_DPID_USER_SPEC ) + { + _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "dis", 3 ); + } + else if ( wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC ) + { + _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pad", 3 ); + } + else + { + _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pbc", 3 ); + } + } + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen ); + + + // P2P IE Section. + + // P2P OUI + p2pielen = 0; + p2pie[ p2pielen++ ] = 0x50; + p2pie[ p2pielen++ ] = 0x6F; + p2pie[ p2pielen++ ] = 0x9A; + p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 + + // Commented by Albert 20100908 + // According to the P2P Specification, the group negoitation response frame should contain 9 P2P attributes + // 1. Status + // 2. P2P Capability + // 3. Group Owner Intent + // 4. Configuration Timeout + // 5. Operating Channel + // 6. Intended P2P Interface Address + // 7. Channel List + // 8. Device Info + // 9. Group ID ( Only GO ) + + + // ToDo: + + // P2P Status + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_STATUS; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0001 ); + p2pielen += 2; + + // Value: + p2pie[ p2pielen++ ] = result; + + // P2P Capability + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); + p2pielen += 2; + + // Value: + // Device Capability Bitmap, 1 byte + + if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) ) + { + // Commented by Albert 2011/03/08 + // According to the P2P specification + // if the sending device will be client, the P2P Capability should be reserved of group negotation response frame + p2pie[ p2pielen++ ] = 0; + } + else + { + // Be group owner or meet the error case + p2pie[ p2pielen++ ] = DMP_P2P_DEVCAP_SUPPORT; + } + + // Group Capability Bitmap, 1 byte + if ( pwdinfo->persistent_supported ) + { + p2pie[ p2pielen++ ] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP; + } + else + { + p2pie[ p2pielen++ ] = P2P_GRPCAP_CROSS_CONN; + } + + // Group Owner Intent + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_GO_INTENT; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0001 ); + p2pielen += 2; + + // Value: + if ( pwdinfo->peer_intent & 0x01 ) + { + // Peer's tie breaker bit is 1, our tie breaker bit should be 0 + p2pie[ p2pielen++ ] = ( pwdinfo->intent << 1 ); + } + else + { + // Peer's tie breaker bit is 0, our tie breaker bit should be 1 + p2pie[ p2pielen++ ] = ( ( pwdinfo->intent << 1 ) | BIT(0) ); + } + + + // Configuration Timeout + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_CONF_TIMEOUT; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); + p2pielen += 2; + + // Value: + p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P GO + p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P Client + + // Operating Channel + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_OPERATING_CH; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 ); + p2pielen += 2; + + // Value: + // Country String + p2pie[ p2pielen++ ] = 'X'; + p2pie[ p2pielen++ ] = 'X'; + + // The third byte should be set to 0x04. + // Described in the "Operating Channel Attribute" section. + p2pie[ p2pielen++ ] = 0x04; + + // Operating Class + if ( pwdinfo->operating_channel <= 14 ) + { + // Operating Class + p2pie[ p2pielen++ ] = 0x51; + } + else if ( ( pwdinfo->operating_channel >= 36 ) && ( pwdinfo->operating_channel <= 48 ) ) + { + // Operating Class + p2pie[ p2pielen++ ] = 0x73; + } + else + { + // Operating Class + p2pie[ p2pielen++ ] = 0x7c; + } + + // Channel Number + p2pie[ p2pielen++ ] = pwdinfo->operating_channel; // operating channel number + + // Intended P2P Interface Address + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_INTENTED_IF_ADDR; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN ); + p2pielen += 2; + + // Value: + _rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN); + p2pielen += ETH_ALEN; + + // Channel List + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_CH_LIST; + + // Country String(3) + // + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) + // + number of channels in all classes + len_channellist_attr = 3 + + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes + + get_reg_classes_full_count(pmlmeext->channel_list); + +#ifdef CONFIG_CONCURRENT_MODE + if (check_buddy_fwstate(padapter , _FW_LINKED) + && padapter->registrypriv.full_ch_in_p2p_handshake == 0) + { + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 5 + 1 ); + } + else + { + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( len_channellist_attr ); + } +#else + + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( len_channellist_attr ); + + #endif + p2pielen += 2; + + // Value: + // Country String + p2pie[ p2pielen++ ] = 'X'; + p2pie[ p2pielen++ ] = 'X'; + + // The third byte should be set to 0x04. + // Described in the "Operating Channel Attribute" section. + p2pie[ p2pielen++ ] = 0x04; + + // Channel Entry List + +#ifdef CONFIG_CONCURRENT_MODE + if (check_buddy_fwstate(padapter , _FW_LINKED) + && padapter->registrypriv.full_ch_in_p2p_handshake == 0) + { + _adapter *pbuddy_adapter = padapter->pbuddy_adapter; + struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; + + // Operating Class + if ( pbuddy_mlmeext->cur_channel > 14 ) + { + if ( pbuddy_mlmeext->cur_channel >= 149 ) + { + p2pie[ p2pielen++ ] = 0x7c; + } + else + { + p2pie[ p2pielen++ ] = 0x73; + } + } + else + { + p2pie[ p2pielen++ ] = 0x51; + } + + // Number of Channels + // Just support 1 channel and this channel is AP's channel + p2pie[ p2pielen++ ] = 1; + + // Channel List + p2pie[ p2pielen++ ] = pbuddy_mlmeext->cur_channel; + } + else + { + int i, j; + for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { + // Operating Class + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; + + // Number of Channels + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; + + // Channel List + for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) { + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; + } + } + } +#else // CONFIG_CONCURRENT_MODE + { + int i, j; + for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { + // Operating Class + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; + + // Number of Channels + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; + + // Channel List + for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) { + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; + } + } + } +#endif // CONFIG_CONCURRENT_MODE + + + // Device Info + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO; + + // Length: + // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) + // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); + p2pielen += 2; + + // Value: + // P2P Device Address + _rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN); + p2pielen += ETH_ALEN; + + // Config Method + // This field should be big endian. Noted by P2P specification. + + *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->supported_wps_cm ); + + p2pielen += 2; + + // Primary Device Type + // Category ID + *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); + p2pielen += 2; + + // OUI + *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); + p2pielen += 4; + + // Sub Category ID + *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); + p2pielen += 2; + + // Number of Secondary Device Types + p2pie[ p2pielen++ ] = 0x00; // No Secondary Device Type List + + // Device Name + // Type: + *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); + p2pielen += 2; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); + p2pielen += 2; + + // Value: + _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_name , pwdinfo->device_name_len ); + p2pielen += pwdinfo->device_name_len; + + if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) ) + { + // Group ID Attribute + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_GROUP_ID; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN + pwdinfo->nego_ssidlen ); + p2pielen += 2; + + // Value: + // p2P Device Address + _rtw_memcpy( p2pie + p2pielen , pwdinfo->device_addr, ETH_ALEN ); + p2pielen += ETH_ALEN; + + // SSID + _rtw_memcpy( p2pie + p2pielen, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen ); + p2pielen += pwdinfo->nego_ssidlen; + + } + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen ); + +#ifdef CONFIG_WFD + wfdielen = build_nego_resp_wfd_ie(pwdinfo, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; +#endif + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + + return; + +} + +void issue_p2p_GO_confirm(_adapter *padapter, u8* raddr, u8 result) +{ + + unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; + u8 action = P2P_PUB_ACTION_ACTION; + u32 p2poui = cpu_to_be32(P2POUI); + u8 oui_subtype = P2P_GO_NEGO_CONF; + u8 wpsie[ 255 ] = { 0x00 }, p2pie[ 255 ] = { 0x00 }; + u8 wpsielen = 0, p2pielen = 0; + + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct wifidirect_info *pwdinfo = &( padapter->wdinfo); +#ifdef CONFIG_WFD + u32 wfdielen = 0; +#endif + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + { + return; + } + + DBG_871X( "[%s] In\n", __FUNCTION__ ); + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(pwdinfo->negotiation_dialog_token), &(pattrib->pktlen)); + + + + // P2P IE Section. + + // P2P OUI + p2pielen = 0; + p2pie[ p2pielen++ ] = 0x50; + p2pie[ p2pielen++ ] = 0x6F; + p2pie[ p2pielen++ ] = 0x9A; + p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 + + // Commented by Albert 20110306 + // According to the P2P Specification, the group negoitation request frame should contain 5 P2P attributes + // 1. Status + // 2. P2P Capability + // 3. Operating Channel + // 4. Channel List + // 5. Group ID ( if this WiFi is GO ) + + // P2P Status + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_STATUS; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0001 ); + p2pielen += 2; + + // Value: + p2pie[ p2pielen++ ] = result; + + // P2P Capability + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); + p2pielen += 2; + + // Value: + // Device Capability Bitmap, 1 byte + p2pie[ p2pielen++ ] = DMP_P2P_DEVCAP_SUPPORT; + + // Group Capability Bitmap, 1 byte + if ( pwdinfo->persistent_supported ) + { + p2pie[ p2pielen++ ] = P2P_GRPCAP_CROSS_CONN | P2P_GRPCAP_PERSISTENT_GROUP; + } + else + { + p2pie[ p2pielen++ ] = P2P_GRPCAP_CROSS_CONN; + } + + + // Operating Channel + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_OPERATING_CH; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 ); + p2pielen += 2; + + // Value: + // Country String + p2pie[ p2pielen++ ] = 'X'; + p2pie[ p2pielen++ ] = 'X'; + + // The third byte should be set to 0x04. + // Described in the "Operating Channel Attribute" section. + p2pie[ p2pielen++ ] = 0x04; + + + if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) ) + { + if ( pwdinfo->peer_operating_ch <= 14 ) + { + // Operating Class + p2pie[ p2pielen++ ] = 0x51; + } + else if ( ( pwdinfo->peer_operating_ch >= 36 ) && ( pwdinfo->peer_operating_ch <= 48 ) ) + { + // Operating Class + p2pie[ p2pielen++ ] = 0x73; + } + else + { + // Operating Class + p2pie[ p2pielen++ ] = 0x7c; + } + + p2pie[ p2pielen++ ] = pwdinfo->peer_operating_ch; + } + else + { + if ( pwdinfo->operating_channel <= 14 ) + { + // Operating Class + p2pie[ p2pielen++ ] = 0x51; + } + else if ( ( pwdinfo->operating_channel >= 36 ) && ( pwdinfo->operating_channel <= 48 ) ) + { + // Operating Class + p2pie[ p2pielen++ ] = 0x73; + } + else + { + // Operating Class + p2pie[ p2pielen++ ] = 0x7c; + } + + // Channel Number + p2pie[ p2pielen++ ] = pwdinfo->operating_channel; // Use the listen channel as the operating channel + } + + + // Channel List + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_CH_LIST; + + *(u16*) ( p2pie + p2pielen ) = 6; + p2pielen += 2; + + // Country String + p2pie[ p2pielen++ ] = 'X'; + p2pie[ p2pielen++ ] = 'X'; + + // The third byte should be set to 0x04. + // Described in the "Operating Channel Attribute" section. + p2pie[ p2pielen++ ] = 0x04; + + // Value: + if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) ) + { + if ( pwdinfo->peer_operating_ch <= 14 ) + { + // Operating Class + p2pie[ p2pielen++ ] = 0x51; + } + else if ( ( pwdinfo->peer_operating_ch >= 36 ) && ( pwdinfo->peer_operating_ch <= 48 ) ) + { + // Operating Class + p2pie[ p2pielen++ ] = 0x73; + } + else + { + // Operating Class + p2pie[ p2pielen++ ] = 0x7c; + } + p2pie[ p2pielen++ ] = 1; + p2pie[ p2pielen++ ] = pwdinfo->peer_operating_ch; + } + else + { + if ( pwdinfo->operating_channel <= 14 ) + { + // Operating Class + p2pie[ p2pielen++ ] = 0x51; + } + else if ( ( pwdinfo->operating_channel >= 36 ) && ( pwdinfo->operating_channel <= 48 ) ) + { + // Operating Class + p2pie[ p2pielen++ ] = 0x73; + } + else + { + // Operating Class + p2pie[ p2pielen++ ] = 0x7c; + } + + // Channel Number + p2pie[ p2pielen++ ] = 1; + p2pie[ p2pielen++ ] = pwdinfo->operating_channel; // Use the listen channel as the operating channel + } + + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) ) + { + // Group ID Attribute + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_GROUP_ID; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN + pwdinfo->nego_ssidlen ); + p2pielen += 2; + + // Value: + // p2P Device Address + _rtw_memcpy( p2pie + p2pielen , pwdinfo->device_addr, ETH_ALEN ); + p2pielen += ETH_ALEN; + + // SSID + _rtw_memcpy( p2pie + p2pielen, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen ); + p2pielen += pwdinfo->nego_ssidlen; + } + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen ); + +#ifdef CONFIG_WFD + wfdielen = build_nego_confirm_wfd_ie(pwdinfo, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; +#endif + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + + return; + +} + +void issue_p2p_invitation_request(_adapter *padapter, u8* raddr ) +{ + + unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; + u8 action = P2P_PUB_ACTION_ACTION; + u32 p2poui = cpu_to_be32(P2POUI); + u8 oui_subtype = P2P_INVIT_REQ; + u8 p2pie[ 255 ] = { 0x00 }; + u8 p2pielen = 0, i; + u8 dialogToken = 3; + u8 channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh = 0; + u16 len_channellist_attr = 0; +#ifdef CONFIG_WFD + u32 wfdielen = 0; +#endif +#ifdef CONFIG_CONCURRENT_MODE + _adapter *pbuddy_adapter = padapter->pbuddy_adapter; + struct wifidirect_info *pbuddy_wdinfo = &pbuddy_adapter->wdinfo; + struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv; + struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; +#endif + + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct wifidirect_info *pwdinfo = &( padapter->wdinfo); + + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + { + return; + } + + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, raddr, ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); + + // P2P IE Section. + + // P2P OUI + p2pielen = 0; + p2pie[ p2pielen++ ] = 0x50; + p2pie[ p2pielen++ ] = 0x6F; + p2pie[ p2pielen++ ] = 0x9A; + p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 + + // Commented by Albert 20101011 + // According to the P2P Specification, the P2P Invitation request frame should contain 7 P2P attributes + // 1. Configuration Timeout + // 2. Invitation Flags + // 3. Operating Channel ( Only GO ) + // 4. P2P Group BSSID ( Should be included if I am the GO ) + // 5. Channel List + // 6. P2P Group ID + // 7. P2P Device Info + + // Configuration Timeout + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_CONF_TIMEOUT; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); + p2pielen += 2; + + // Value: + p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P GO + p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P Client + + // Invitation Flags + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_INVITATION_FLAGS; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0001 ); + p2pielen += 2; + + // Value: + p2pie[ p2pielen++ ] = P2P_INVITATION_FLAGS_PERSISTENT; + + + // Operating Channel + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_OPERATING_CH; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 ); + p2pielen += 2; + + // Value: + // Country String + p2pie[ p2pielen++ ] = 'X'; + p2pie[ p2pielen++ ] = 'X'; + + // The third byte should be set to 0x04. + // Described in the "Operating Channel Attribute" section. + p2pie[ p2pielen++ ] = 0x04; + + // Operating Class + if ( pwdinfo->invitereq_info.operating_ch <= 14 ) + p2pie[ p2pielen++ ] = 0x51; + else if ( ( pwdinfo->invitereq_info.operating_ch >= 36 ) && ( pwdinfo->invitereq_info.operating_ch <= 48 ) ) + p2pie[ p2pielen++ ] = 0x73; + else + p2pie[ p2pielen++ ] = 0x7c; + + // Channel Number + p2pie[ p2pielen++ ] = pwdinfo->invitereq_info.operating_ch; // operating channel number + + if (_rtw_memcmp(adapter_mac_addr(padapter), pwdinfo->invitereq_info.go_bssid, ETH_ALEN)) + { + // P2P Group BSSID + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_GROUP_BSSID; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN ); + p2pielen += 2; + + // Value: + // P2P Device Address for GO + _rtw_memcpy( p2pie + p2pielen, pwdinfo->invitereq_info.go_bssid, ETH_ALEN ); + p2pielen += ETH_ALEN; + } + + // Channel List + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_CH_LIST; + + + // Length: + // Country String(3) + // + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) + // + number of channels in all classes + len_channellist_attr = 3 + + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes + + get_reg_classes_full_count(pmlmeext->channel_list); + +#ifdef CONFIG_CONCURRENT_MODE + if (check_buddy_fwstate(padapter , _FW_LINKED) + && padapter->registrypriv.full_ch_in_p2p_handshake == 0) + { + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 5 + 1 ); + } + else + { + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( len_channellist_attr ); + } +#else + + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( len_channellist_attr ); + + #endif + p2pielen += 2; + + // Value: + // Country String + p2pie[ p2pielen++ ] = 'X'; + p2pie[ p2pielen++ ] = 'X'; + + // The third byte should be set to 0x04. + // Described in the "Operating Channel Attribute" section. + p2pie[ p2pielen++ ] = 0x04; + + // Channel Entry List +#ifdef CONFIG_CONCURRENT_MODE + if (check_buddy_fwstate(padapter, _FW_LINKED) + && padapter->registrypriv.full_ch_in_p2p_handshake == 0) + { + _adapter *pbuddy_adapter = padapter->pbuddy_adapter; + struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; + + // Operating Class + if ( pbuddy_mlmeext->cur_channel > 14 ) + { + if ( pbuddy_mlmeext->cur_channel >= 149 ) + { + p2pie[ p2pielen++ ] = 0x7c; + } + else + { + p2pie[ p2pielen++ ] = 0x73; + } + } + else + { + p2pie[ p2pielen++ ] = 0x51; + } + + // Number of Channels + // Just support 1 channel and this channel is AP's channel + p2pie[ p2pielen++ ] = 1; + + // Channel List + p2pie[ p2pielen++ ] = pbuddy_mlmeext->cur_channel; + } + else + { + int i, j; + for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { + // Operating Class + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; + + // Number of Channels + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; + + // Channel List + for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) { + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; + } + } + } +#else // CONFIG_CONCURRENT_MODE + { + int i, j; + for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { + // Operating Class + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; + + // Number of Channels + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; + + // Channel List + for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) { + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; + } + } + } +#endif // CONFIG_CONCURRENT_MODE + + + // P2P Group ID + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_GROUP_ID; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 6 + pwdinfo->invitereq_info.ssidlen ); + p2pielen += 2; + + // Value: + // P2P Device Address for GO + _rtw_memcpy( p2pie + p2pielen, pwdinfo->invitereq_info.go_bssid, ETH_ALEN ); + p2pielen += ETH_ALEN; + + // SSID + _rtw_memcpy( p2pie + p2pielen, pwdinfo->invitereq_info.go_ssid, pwdinfo->invitereq_info.ssidlen ); + p2pielen += pwdinfo->invitereq_info.ssidlen; + + + // Device Info + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO; + + // Length: + // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) + // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); + p2pielen += 2; + + // Value: + // P2P Device Address + _rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN); + p2pielen += ETH_ALEN; + + // Config Method + // This field should be big endian. Noted by P2P specification. + *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_DISPLAY ); + p2pielen += 2; + + // Primary Device Type + // Category ID + *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); + p2pielen += 2; + + // OUI + *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); + p2pielen += 4; + + // Sub Category ID + *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); + p2pielen += 2; + + // Number of Secondary Device Types + p2pie[ p2pielen++ ] = 0x00; // No Secondary Device Type List + + // Device Name + // Type: + *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); + p2pielen += 2; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); + p2pielen += 2; + + // Value: + _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len ); + p2pielen += pwdinfo->device_name_len; + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen ); + +#ifdef CONFIG_WFD + wfdielen = build_invitation_req_wfd_ie(pwdinfo, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; +#endif + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + + return; + +} + +void issue_p2p_invitation_response(_adapter *padapter, u8* raddr, u8 dialogToken, u8 status_code) +{ + + unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; + u8 action = P2P_PUB_ACTION_ACTION; + u32 p2poui = cpu_to_be32(P2POUI); + u8 oui_subtype = P2P_INVIT_RESP; + u8 p2pie[ 255 ] = { 0x00 }; + u8 p2pielen = 0, i; + u8 channel_cnt_24g = 0, channel_cnt_5gl = 0, channel_cnt_5gh = 0; + u16 len_channellist_attr = 0; +#ifdef CONFIG_CONCURRENT_MODE + _adapter *pbuddy_adapter = padapter->pbuddy_adapter; + struct wifidirect_info *pbuddy_wdinfo = &pbuddy_adapter->wdinfo; + struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv; + struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; +#endif +#ifdef CONFIG_WFD + u32 wfdielen = 0; +#endif + + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct wifidirect_info *pwdinfo = &( padapter->wdinfo); + + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + { + return; + } + + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, raddr, ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); + + // P2P IE Section. + + // P2P OUI + p2pielen = 0; + p2pie[ p2pielen++ ] = 0x50; + p2pie[ p2pielen++ ] = 0x6F; + p2pie[ p2pielen++ ] = 0x9A; + p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 + + // Commented by Albert 20101005 + // According to the P2P Specification, the P2P Invitation response frame should contain 5 P2P attributes + // 1. Status + // 2. Configuration Timeout + // 3. Operating Channel ( Only GO ) + // 4. P2P Group BSSID ( Only GO ) + // 5. Channel List + + // P2P Status + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_STATUS; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0001 ); + p2pielen += 2; + + // Value: + // When status code is P2P_STATUS_FAIL_INFO_UNAVAILABLE. + // Sent the event receiving the P2P Invitation Req frame to DMP UI. + // DMP had to compare the MAC address to find out the profile. + // So, the WiFi driver will send the P2P_STATUS_FAIL_INFO_UNAVAILABLE to NB. + // If the UI found the corresponding profile, the WiFi driver sends the P2P Invitation Req + // to NB to rebuild the persistent group. + p2pie[ p2pielen++ ] = status_code; + + // Configuration Timeout + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_CONF_TIMEOUT; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); + p2pielen += 2; + + // Value: + p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P GO + p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P Client + + if( status_code == P2P_STATUS_SUCCESS ) + { + if( rtw_p2p_chk_role( pwdinfo, P2P_ROLE_GO ) ) + { + // The P2P Invitation request frame asks this Wi-Fi device to be the P2P GO + // In this case, the P2P Invitation response frame should carry the two more P2P attributes. + // First one is operating channel attribute. + // Second one is P2P Group BSSID attribute. + + // Operating Channel + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_OPERATING_CH; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 ); + p2pielen += 2; + + // Value: + // Country String + p2pie[ p2pielen++ ] = 'X'; + p2pie[ p2pielen++ ] = 'X'; + + // The third byte should be set to 0x04. + // Described in the "Operating Channel Attribute" section. + p2pie[ p2pielen++ ] = 0x04; + + // Operating Class + p2pie[ p2pielen++ ] = 0x51; // Copy from SD7 + + // Channel Number + p2pie[ p2pielen++ ] = pwdinfo->operating_channel; // operating channel number + + + // P2P Group BSSID + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_GROUP_BSSID; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN ); + p2pielen += 2; + + // Value: + // P2P Device Address for GO + _rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN); + p2pielen += ETH_ALEN; + + } + + // Channel List + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_CH_LIST; + + // Length: + // Country String(3) + // + ( Operating Class (1) + Number of Channels(1) ) * Operation Classes (?) + // + number of channels in all classes + len_channellist_attr = 3 + + (1 + 1) * (u16)pmlmeext->channel_list.reg_classes + + get_reg_classes_full_count(pmlmeext->channel_list); + +#ifdef CONFIG_CONCURRENT_MODE + if (check_buddy_fwstate(padapter, _FW_LINKED) + && padapter->registrypriv.full_ch_in_p2p_handshake == 0) + { + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 5 + 1 ); + } + else + { + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( len_channellist_attr ); + } +#else + + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( len_channellist_attr ); + +#endif + p2pielen += 2; + + // Value: + // Country String + p2pie[ p2pielen++ ] = 'X'; + p2pie[ p2pielen++ ] = 'X'; + + // The third byte should be set to 0x04. + // Described in the "Operating Channel Attribute" section. + p2pie[ p2pielen++ ] = 0x04; + + // Channel Entry List +#ifdef CONFIG_CONCURRENT_MODE + if (check_buddy_fwstate(padapter , _FW_LINKED) + && padapter->registrypriv.full_ch_in_p2p_handshake == 0) + { + _adapter *pbuddy_adapter = padapter->pbuddy_adapter; + struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; + + // Operating Class + if ( pbuddy_mlmeext->cur_channel > 14 ) + { + if ( pbuddy_mlmeext->cur_channel >= 149 ) + { + p2pie[ p2pielen++ ] = 0x7c; + } + else + { + p2pie[ p2pielen++ ] = 0x73; + } + } + else + { + p2pie[ p2pielen++ ] = 0x51; + } + + // Number of Channels + // Just support 1 channel and this channel is AP's channel + p2pie[ p2pielen++ ] = 1; + + // Channel List + p2pie[ p2pielen++ ] = pbuddy_mlmeext->cur_channel; + } + else + { + int i, j; + for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { + // Operating Class + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; + + // Number of Channels + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; + + // Channel List + for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) { + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; + } + } + } +#else // CONFIG_CONCURRENT_MODE + { + int i, j; + for (j = 0; j < pmlmeext->channel_list.reg_classes; j++) { + // Operating Class + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].reg_class; + + // Number of Channels + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channels; + + // Channel List + for (i = 0; i < pmlmeext->channel_list.reg_class[j].channels; i++) { + p2pie[p2pielen++] = pmlmeext->channel_list.reg_class[j].channel[i]; + } + } + } +#endif // CONFIG_CONCURRENT_MODE + } + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen ); + +#ifdef CONFIG_WFD + wfdielen = build_invitation_resp_wfd_ie(pwdinfo, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; +#endif + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + + return; + +} + +void issue_p2p_provision_request(_adapter *padapter, u8* pssid, u8 ussidlen, u8* pdev_raddr ) +{ + unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; + u8 action = P2P_PUB_ACTION_ACTION; + u8 dialogToken = 1; + u32 p2poui = cpu_to_be32(P2POUI); + u8 oui_subtype = P2P_PROVISION_DISC_REQ; + u8 wpsie[ 100 ] = { 0x00 }; + u8 wpsielen = 0; + u32 p2pielen = 0; +#ifdef CONFIG_WFD + u32 wfdielen = 0; +#endif + + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + { + return; + } + + DBG_871X( "[%s] In\n", __FUNCTION__ ); + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, pdev_raddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, pdev_raddr, ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); + + p2pielen = build_prov_disc_request_p2p_ie( pwdinfo, pframe, pssid, ussidlen, pdev_raddr ); + + pframe += p2pielen; + pattrib->pktlen += p2pielen; + + wpsielen = 0; + // WPS OUI + *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); + wpsielen += 4; + + // WPS version + // Type: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 ); + wpsielen += 2; + + // Length: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); + wpsielen += 2; + + // Value: + wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0 + + // Config Method + // Type: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD ); + wpsielen += 2; + + // Length: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); + wpsielen += 2; + + // Value: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( pwdinfo->tx_prov_disc_info.wps_config_method_request ); + wpsielen += 2; + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen ); + + +#ifdef CONFIG_WFD + wfdielen = build_provdisc_req_wfd_ie(pwdinfo, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; +#endif + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + + return; + +} + + +u8 is_matched_in_profilelist( u8* peermacaddr, struct profile_info* profileinfo ) +{ + u8 i, match_result = 0; + + DBG_871X( "[%s] peermac = %.2X %.2X %.2X %.2X %.2X %.2X\n", __FUNCTION__, + peermacaddr[0], peermacaddr[1],peermacaddr[2],peermacaddr[3],peermacaddr[4],peermacaddr[5]); + + for( i = 0; i < P2P_MAX_PERSISTENT_GROUP_NUM; i++, profileinfo++ ) + { + DBG_871X( "[%s] profileinfo_mac = %.2X %.2X %.2X %.2X %.2X %.2X\n", __FUNCTION__, + profileinfo->peermac[0], profileinfo->peermac[1],profileinfo->peermac[2],profileinfo->peermac[3],profileinfo->peermac[4],profileinfo->peermac[5]); + if ( _rtw_memcmp( peermacaddr, profileinfo->peermac, ETH_ALEN ) ) + { + match_result = 1; + DBG_871X( "[%s] Match!\n", __FUNCTION__ ); + break; + } + } + + return (match_result ); +} + +void issue_probersp_p2p(_adapter *padapter, unsigned char *da) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + unsigned char *mac; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + //WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + u16 beacon_interval = 100; + u16 capInfo = 0; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + u8 wpsie[255] = { 0x00 }; + u32 wpsielen = 0, p2pielen = 0; +#ifdef CONFIG_WFD + u32 wfdielen = 0; +#endif +#ifdef CONFIG_INTEL_WIDI + u8 zero_array_check[L2SDTA_SERVICE_VE_LEN] = { 0x00 }; +#endif //CONFIG_INTEL_WIDI + + //DBG_871X("%s\n", __FUNCTION__); + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + { + return; + } + + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + mac = adapter_mac_addr(padapter); + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); + + // Use the device address for BSSID field. + _rtw_memcpy(pwlanhdr->addr3, mac, ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(fctrl, WIFI_PROBERSP); + + pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = pattrib->hdrlen; + pframe += pattrib->hdrlen; + + //timestamp will be inserted by hardware + pframe += 8; + pattrib->pktlen += 8; + + // beacon interval: 2 bytes + _rtw_memcpy(pframe, (unsigned char *) &beacon_interval, 2); + pframe += 2; + pattrib->pktlen += 2; + + // capability info: 2 bytes + // ESS and IBSS bits must be 0 (defined in the 3.1.2.1.1 of WiFi Direct Spec) + capInfo |= cap_ShortPremble; + capInfo |= cap_ShortSlot; + + _rtw_memcpy(pframe, (unsigned char *) &capInfo, 2); + pframe += 2; + pattrib->pktlen += 2; + + + // SSID + pframe = rtw_set_ie(pframe, _SSID_IE_, 7, pwdinfo->p2p_wildcard_ssid, &pattrib->pktlen); + + // supported rates... + // Use the OFDM rate in the P2P probe response frame. ( 6(B), 9(B), 12, 18, 24, 36, 48, 54 ) + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pwdinfo->support_rate, &pattrib->pktlen); + + // DS parameter set + pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&pwdinfo->listen_channel, &pattrib->pktlen); + +#ifdef CONFIG_IOCTL_CFG80211 + if(adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211 ) + { + if( pmlmepriv->wps_probe_resp_ie != NULL && pmlmepriv->p2p_probe_resp_ie != NULL ) + { + //WPS IE + _rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, pmlmepriv->wps_probe_resp_ie_len); + pattrib->pktlen += pmlmepriv->wps_probe_resp_ie_len; + pframe += pmlmepriv->wps_probe_resp_ie_len; + + //P2P IE + _rtw_memcpy(pframe, pmlmepriv->p2p_probe_resp_ie, pmlmepriv->p2p_probe_resp_ie_len); + pattrib->pktlen += pmlmepriv->p2p_probe_resp_ie_len; + pframe += pmlmepriv->p2p_probe_resp_ie_len; + } + } + else +#endif //CONFIG_IOCTL_CFG80211 + { + + // Todo: WPS IE + // Noted by Albert 20100907 + // According to the WPS specification, all the WPS attribute is presented by Big Endian. + + wpsielen = 0; + // WPS OUI + *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); + wpsielen += 4; + + // WPS version + // Type: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 ); + wpsielen += 2; + + // Length: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); + wpsielen += 2; + + // Value: + wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0 + +#ifdef CONFIG_INTEL_WIDI + // Commented by Kurt + // Appended WiDi info. only if we did issued_probereq_widi(), and then we saved ven. ext. in pmlmepriv->sa_ext. + if( _rtw_memcmp(pmlmepriv->sa_ext, zero_array_check, L2SDTA_SERVICE_VE_LEN) == _FALSE + || pmlmepriv->num_p2p_sdt != 0 ) + { + //Sec dev type + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_SEC_DEV_TYPE_LIST ); + wpsielen += 2; + + // Length: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0008 ); + wpsielen += 2; + + // Value: + // Category ID + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_PDT_CID_DISPLAYS ); + wpsielen += 2; + + // OUI + *(u32*) ( wpsie + wpsielen ) = cpu_to_be32( INTEL_DEV_TYPE_OUI ); + wpsielen += 4; + + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_PDT_SCID_WIDI_CONSUMER_SINK ); + wpsielen += 2; + + if( _rtw_memcmp(pmlmepriv->sa_ext, zero_array_check, L2SDTA_SERVICE_VE_LEN) == _FALSE ) + { + // Vendor Extension + _rtw_memcpy( wpsie + wpsielen, pmlmepriv->sa_ext, L2SDTA_SERVICE_VE_LEN ); + wpsielen += L2SDTA_SERVICE_VE_LEN; + } + } +#endif //CONFIG_INTEL_WIDI + + // WiFi Simple Config State + // Type: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_SIMPLE_CONF_STATE ); + wpsielen += 2; + + // Length: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); + wpsielen += 2; + + // Value: + wpsie[wpsielen++] = WPS_WSC_STATE_NOT_CONFIG; // Not Configured. + + // Response Type + // Type: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_RESP_TYPE ); + wpsielen += 2; + + // Length: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); + wpsielen += 2; + + // Value: + wpsie[wpsielen++] = WPS_RESPONSE_TYPE_8021X; + + // UUID-E + // Type: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_UUID_E ); + wpsielen += 2; + + // Length: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0010 ); + wpsielen += 2; + + // Value: + if (pwdinfo->external_uuid == 0) { + _rtw_memset( wpsie + wpsielen, 0x0, 16 ); + _rtw_memcpy(wpsie + wpsielen, mac, ETH_ALEN); + } else { + _rtw_memcpy( wpsie + wpsielen, pwdinfo->uuid, 0x10 ); + } + wpsielen += 0x10; + + // Manufacturer + // Type: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_MANUFACTURER ); + wpsielen += 2; + + // Length: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0007 ); + wpsielen += 2; + + // Value: + _rtw_memcpy( wpsie + wpsielen, "Realtek", 7 ); + wpsielen += 7; + + // Model Name + // Type: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_MODEL_NAME ); + wpsielen += 2; + + // Length: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0006 ); + wpsielen += 2; + + // Value: + _rtw_memcpy( wpsie + wpsielen, "8192CU", 6 ); + wpsielen += 6; + + // Model Number + // Type: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_MODEL_NUMBER ); + wpsielen += 2; + + // Length: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); + wpsielen += 2; + + // Value: + wpsie[ wpsielen++ ] = 0x31; // character 1 + + // Serial Number + // Type: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_SERIAL_NUMBER ); + wpsielen += 2; + + // Length: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( ETH_ALEN ); + wpsielen += 2; + + // Value: + _rtw_memcpy( wpsie + wpsielen, "123456" , ETH_ALEN ); + wpsielen += ETH_ALEN; + + // Primary Device Type + // Type: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_PRIMARY_DEV_TYPE ); + wpsielen += 2; + + // Length: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0008 ); + wpsielen += 2; + + // Value: + // Category ID + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); + wpsielen += 2; + + // OUI + *(u32*) ( wpsie + wpsielen ) = cpu_to_be32( WPSOUI ); + wpsielen += 4; + + // Sub Category ID + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); + wpsielen += 2; + + // Device Name + // Type: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); + wpsielen += 2; + + // Length: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( pwdinfo->device_name_len ); + wpsielen += 2; + + // Value: + _rtw_memcpy( wpsie + wpsielen, pwdinfo->device_name, pwdinfo->device_name_len ); + wpsielen += pwdinfo->device_name_len; + + // Config Method + // Type: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD ); + wpsielen += 2; + + // Length: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); + wpsielen += 2; + + // Value: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( pwdinfo->supported_wps_cm ); + wpsielen += 2; + + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen ); + + + p2pielen = build_probe_resp_p2p_ie(pwdinfo, pframe); + pframe += p2pielen; + pattrib->pktlen += p2pielen; + } + +#ifdef CONFIG_WFD + wfdielen = rtw_append_probe_resp_wfd_ie(padapter, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; +#endif + + pattrib->last_txcmdsz = pattrib->pktlen; + + + dump_mgntframe(padapter, pmgntframe); + + return; + +} + +int _issue_probereq_p2p(_adapter *padapter, u8 *da, int wait_ack) +{ + int ret = _FAIL; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + unsigned char *mac; + unsigned char bssrate[NumRates]; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + int bssrate_len = 0; + u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + u8 wpsie[255] = { 0x00 }, p2pie[ 255 ] = { 0x00 }; + u16 wpsielen = 0, p2pielen = 0; +#ifdef CONFIG_WFD + u32 wfdielen = 0; +#endif + + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + { + goto exit; + } + + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + mac = adapter_mac_addr(padapter); + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + if (da) { + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN); + } else { + if ( ( pwdinfo->p2p_info.scan_op_ch_only ) || ( pwdinfo->rx_invitereq_info.scan_op_ch_only ) ) + { + // This two flags will be set when this is only the P2P client mode. + _rtw_memcpy(pwlanhdr->addr1, pwdinfo->p2p_peer_interface_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, pwdinfo->p2p_peer_interface_addr, ETH_ALEN); + } + else + { + // broadcast probe request frame + _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, bc_addr, ETH_ALEN); + } + } + _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(pframe, WIFI_PROBEREQ); + + pframe += sizeof (struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof (struct rtw_ieee80211_hdr_3addr); + + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) + { + pframe = rtw_set_ie(pframe, _SSID_IE_, pwdinfo->tx_prov_disc_info.ssid.SsidLength, pwdinfo->tx_prov_disc_info.ssid.Ssid, &(pattrib->pktlen)); + } + else + { + pframe = rtw_set_ie(pframe, _SSID_IE_, P2P_WILDCARD_SSID_LEN, pwdinfo->p2p_wildcard_ssid, &(pattrib->pktlen)); + } + // Use the OFDM rate in the P2P probe request frame. ( 6(B), 9(B), 12(B), 24(B), 36, 48, 54 ) + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pwdinfo->support_rate, &pattrib->pktlen); + +#ifdef CONFIG_IOCTL_CFG80211 + if(adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211 ) + { + if( pmlmepriv->wps_probe_req_ie != NULL && pmlmepriv->p2p_probe_req_ie != NULL ) + { + //WPS IE + _rtw_memcpy(pframe, pmlmepriv->wps_probe_req_ie, pmlmepriv->wps_probe_req_ie_len); + pattrib->pktlen += pmlmepriv->wps_probe_req_ie_len; + pframe += pmlmepriv->wps_probe_req_ie_len; + + //P2P IE + _rtw_memcpy(pframe, pmlmepriv->p2p_probe_req_ie, pmlmepriv->p2p_probe_req_ie_len); + pattrib->pktlen += pmlmepriv->p2p_probe_req_ie_len; + pframe += pmlmepriv->p2p_probe_req_ie_len; + } + } + else +#endif //CONFIG_IOCTL_CFG80211 + { + + // WPS IE + // Noted by Albert 20110221 + // According to the WPS specification, all the WPS attribute is presented by Big Endian. + + wpsielen = 0; + // WPS OUI + *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); + wpsielen += 4; + + // WPS version + // Type: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 ); + wpsielen += 2; + + // Length: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); + wpsielen += 2; + + // Value: + wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0 + + if( pmlmepriv->wps_probe_req_ie == NULL ) + { + // UUID-E + // Type: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_UUID_E ); + wpsielen += 2; + + // Length: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0010 ); + wpsielen += 2; + + // Value: + if (pwdinfo->external_uuid == 0) { + _rtw_memset( wpsie + wpsielen, 0x0, 16 ); + _rtw_memcpy(wpsie + wpsielen, mac, ETH_ALEN); + } else { + _rtw_memcpy( wpsie + wpsielen, pwdinfo->uuid, 0x10 ); + } + wpsielen += 0x10; + + // Config Method + // Type: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD ); + wpsielen += 2; + + // Length: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); + wpsielen += 2; + + // Value: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( pwdinfo->supported_wps_cm ); + wpsielen += 2; + } + + // Device Name + // Type: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); + wpsielen += 2; + + // Length: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( pwdinfo->device_name_len ); + wpsielen += 2; + + // Value: + _rtw_memcpy( wpsie + wpsielen, pwdinfo->device_name, pwdinfo->device_name_len ); + wpsielen += pwdinfo->device_name_len; + + // Primary Device Type + // Type: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_PRIMARY_DEV_TYPE ); + wpsielen += 2; + + // Length: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0008 ); + wpsielen += 2; + + // Value: + // Category ID + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_PDT_CID_RTK_WIDI ); + wpsielen += 2; + + // OUI + *(u32*) ( wpsie + wpsielen ) = cpu_to_be32( WPSOUI ); + wpsielen += 4; + + // Sub Category ID + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_PDT_SCID_RTK_DMP ); + wpsielen += 2; + + // Device Password ID + // Type: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_DEVICE_PWID ); + wpsielen += 2; + + // Length: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); + wpsielen += 2; + + // Value: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_DPID_REGISTRAR_SPEC ); // Registrar-specified + wpsielen += 2; + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen ); + + // P2P OUI + p2pielen = 0; + p2pie[ p2pielen++ ] = 0x50; + p2pie[ p2pielen++ ] = 0x6F; + p2pie[ p2pielen++ ] = 0x9A; + p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 + + // Commented by Albert 20110221 + // According to the P2P Specification, the probe request frame should contain 5 P2P attributes + // 1. P2P Capability + // 2. P2P Device ID if this probe request wants to find the specific P2P device + // 3. Listen Channel + // 4. Extended Listen Timing + // 5. Operating Channel if this WiFi is working as the group owner now + + // P2P Capability + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); + p2pielen += 2; + + // Value: + // Device Capability Bitmap, 1 byte + p2pie[ p2pielen++ ] = DMP_P2P_DEVCAP_SUPPORT; + + // Group Capability Bitmap, 1 byte + if ( pwdinfo->persistent_supported ) + p2pie[ p2pielen++ ] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT; + else + p2pie[ p2pielen++ ] = DMP_P2P_GRPCAP_SUPPORT; + + // Listen Channel + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_LISTEN_CH; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 ); + p2pielen += 2; + + // Value: + // Country String + p2pie[ p2pielen++ ] = 'X'; + p2pie[ p2pielen++ ] = 'X'; + + // The third byte should be set to 0x04. + // Described in the "Operating Channel Attribute" section. + p2pie[ p2pielen++ ] = 0x04; + + // Operating Class + p2pie[ p2pielen++ ] = 0x51; // Copy from SD7 + + // Channel Number + p2pie[ p2pielen++ ] = pwdinfo->listen_channel; // listen channel + + + // Extended Listen Timing + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_EX_LISTEN_TIMING; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0004 ); + p2pielen += 2; + + // Value: + // Availability Period + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); + p2pielen += 2; + + // Availability Interval + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); + p2pielen += 2; + + if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) ) + { + // Operating Channel (if this WiFi is working as the group owner now) + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_OPERATING_CH; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 ); + p2pielen += 2; + + // Value: + // Country String + p2pie[ p2pielen++ ] = 'X'; + p2pie[ p2pielen++ ] = 'X'; + + // The third byte should be set to 0x04. + // Described in the "Operating Channel Attribute" section. + p2pie[ p2pielen++ ] = 0x04; + + // Operating Class + p2pie[ p2pielen++ ] = 0x51; // Copy from SD7 + + // Channel Number + p2pie[ p2pielen++ ] = pwdinfo->operating_channel; // operating channel number + + } + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen ); + + } + +#ifdef CONFIG_WFD + wfdielen = rtw_append_probe_req_wfd_ie(padapter, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; +#endif + + pattrib->last_txcmdsz = pattrib->pktlen; + + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("issuing probe_req, tx_len=%d\n", pattrib->last_txcmdsz)); + + if (wait_ack) { + ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); + } else { + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + } + +exit: + return ret; +} + +inline void issue_probereq_p2p(_adapter *adapter, u8 *da) +{ + _issue_probereq_p2p(adapter, da, _FALSE); +} + +/* + * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT + * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX + * try_cnt means the maximal TX count to try + */ +int issue_probereq_p2p_ex(_adapter *adapter, u8 *da, int try_cnt, int wait_ms) +{ + int ret; + int i = 0; + u32 start = rtw_get_current_time(); + + do + { + ret = _issue_probereq_p2p(adapter, da, wait_ms>0?_TRUE:_FALSE); + + i++; + + if (RTW_CANNOT_RUN(adapter)) + break; + + if(i < try_cnt && wait_ms > 0 && ret==_FAIL) + rtw_msleep_os(wait_ms); + + }while((iu.hdr.adapter; + struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv); + u8 *frame = rframe->u.hdr.rx_data; + u16 seq_ctrl = ((rframe->u.hdr.attrib.seq_num&0xffff) << 4) | (rframe->u.hdr.attrib.frag_num & 0xf); + u8 token = *(rframe->u.hdr.rx_data + sizeof(struct rtw_ieee80211_hdr_3addr) + token_offset); + + if (GetRetry(frame)) { + if ((seq_ctrl == mlmeext->action_public_rxseq) + && (token == mlmeext->action_public_dialog_token) + ) { + DBG_871X(FUNC_ADPT_FMT" seq_ctrl=0x%x, rxseq=0x%x, token:%d\n", + FUNC_ADPT_ARG(adapter), seq_ctrl, mlmeext->action_public_rxseq, token); + return _FAIL; + } + } + + /* TODO: per sta seq & token */ + mlmeext->action_public_rxseq = seq_ctrl; + mlmeext->action_public_dialog_token = token; + + return _SUCCESS; +} + +unsigned int on_action_public_p2p(union recv_frame *precv_frame) +{ + _adapter *padapter = precv_frame->u.hdr.adapter; + u8 *pframe = precv_frame->u.hdr.rx_data; + uint len = precv_frame->u.hdr.len; + u8 *frame_body; +#ifdef CONFIG_P2P + u8 *p2p_ie; + u32 p2p_ielen, wps_ielen; + struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); + u8 result = P2P_STATUS_SUCCESS; + u8 empty_addr[ETH_ALEN] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + u8 *merged_p2pie = NULL; + u32 merged_p2p_ielen= 0; +#endif //CONFIG_P2P + + frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + +#ifdef CONFIG_P2P + _cancel_timer_ex( &pwdinfo->reset_ch_sitesurvey ); +#ifdef CONFIG_IOCTL_CFG80211 + if(adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211) + { + rtw_cfg80211_rx_p2p_action_public(padapter, pframe, len); + } + else +#endif //CONFIG_IOCTL_CFG80211 + { + // Do nothing if the driver doesn't enable the P2P function. + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) + return _SUCCESS; + + len -= sizeof(struct rtw_ieee80211_hdr_3addr); + + switch( frame_body[ 6 ] )//OUI Subtype + { + case P2P_GO_NEGO_REQ: + { + DBG_871X( "[%s] Got GO Nego Req Frame\n", __FUNCTION__); + _rtw_memset( &pwdinfo->groupid_info, 0x00, sizeof( struct group_id_info ) ); + + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ)) + { + rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); + } + + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL)) + { + // Commented by Albert 20110526 + // In this case, this means the previous nego fail doesn't be reset yet. + _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer ); + // Restore the previous p2p state + rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); + DBG_871X( "[%s] Restore the previous p2p state to %d\n", __FUNCTION__, rtw_p2p_state(pwdinfo) ); + } +#ifdef CONFIG_CONCURRENT_MODE + if ( check_buddy_fwstate(padapter, _FW_LINKED ) ) + { + _cancel_timer_ex( &pwdinfo->ap_p2p_switch_timer ); + } +#endif // CONFIG_CONCURRENT_MODE + + // Commented by Kurt 20110902 + //Add if statement to avoid receiving duplicate prov disc req. such that pre_p2p_state would be covered. + if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) + rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); + + // Commented by Kurt 20120113 + // Get peer_dev_addr here if peer doesn't issue prov_disc frame. + if( _rtw_memcmp(pwdinfo->rx_prov_disc_info.peerDevAddr, empty_addr, ETH_ALEN) ) + _rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, GetAddr2Ptr(pframe), ETH_ALEN); + + result = process_p2p_group_negotation_req( pwdinfo, frame_body, len ); + issue_p2p_GO_response( padapter, GetAddr2Ptr(pframe), frame_body, len, result ); +#ifdef CONFIG_INTEL_WIDI + if (padapter->mlmepriv.widi_state == INTEL_WIDI_STATE_LISTEN) { + padapter->mlmepriv.widi_state = INTEL_WIDI_STATE_WFD_CONNECTION; + _cancel_timer_ex(&(padapter->mlmepriv.listen_timer)); + intel_widi_wk_cmd(padapter, INTEL_WIDI_LISTEN_STOP_WK, NULL, 0); + } +#endif //CONFIG_INTEL_WIDI + + // Commented by Albert 20110718 + // No matter negotiating or negotiation failure, the driver should set up the restore P2P state timer. +#ifdef CONFIG_CONCURRENT_MODE + // Commented by Albert 20120107 + _set_timer( &pwdinfo->restore_p2p_state_timer, 3000 ); +#else // CONFIG_CONCURRENT_MODE + _set_timer( &pwdinfo->restore_p2p_state_timer, 5000 ); +#endif // CONFIG_CONCURRENT_MODE + break; + } + case P2P_GO_NEGO_RESP: + { + DBG_871X( "[%s] Got GO Nego Resp Frame\n", __FUNCTION__); + + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) + { + // Commented by Albert 20110425 + // The restore timer is enabled when issuing the nego request frame of rtw_p2p_connect function. + _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer ); + pwdinfo->nego_req_info.benable = _FALSE; + result = process_p2p_group_negotation_resp( pwdinfo, frame_body, len); + issue_p2p_GO_confirm( pwdinfo->padapter, GetAddr2Ptr(pframe), result); + if ( P2P_STATUS_SUCCESS == result ) + { + if ( rtw_p2p_role(pwdinfo) == P2P_ROLE_CLIENT ) + { + pwdinfo->p2p_info.operation_ch[ 0 ] = pwdinfo->peer_operating_ch; + #ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH + pwdinfo->p2p_info.operation_ch[ 1 ] = 1; //Check whether GO is operating in channel 1; + pwdinfo->p2p_info.operation_ch[ 2 ] = 6; //Check whether GO is operating in channel 6; + pwdinfo->p2p_info.operation_ch[ 3 ] = 11; //Check whether GO is operating in channel 11; + #endif //CONFIG_P2P_OP_CHK_SOCIAL_CH + pwdinfo->p2p_info.scan_op_ch_only = 1; + _set_timer( &pwdinfo->reset_ch_sitesurvey2, P2P_RESET_SCAN_CH ); + } + } + + // Reset the dialog token for group negotiation frames. + pwdinfo->negotiation_dialog_token = 1; + + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL)) + { + _set_timer( &pwdinfo->restore_p2p_state_timer, 5000 ); + } + } + else + { + DBG_871X( "[%s] Skipped GO Nego Resp Frame (p2p_state != P2P_STATE_GONEGO_ING)\n", __FUNCTION__); + } + + break; + } + case P2P_GO_NEGO_CONF: + { + DBG_871X( "[%s] Got GO Nego Confirm Frame\n", __FUNCTION__); + result = process_p2p_group_negotation_confirm( pwdinfo, frame_body, len); + if ( P2P_STATUS_SUCCESS == result ) + { + if ( rtw_p2p_role(pwdinfo) == P2P_ROLE_CLIENT ) + { + pwdinfo->p2p_info.operation_ch[ 0 ] = pwdinfo->peer_operating_ch; + #ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH + pwdinfo->p2p_info.operation_ch[ 1 ] = 1; //Check whether GO is operating in channel 1; + pwdinfo->p2p_info.operation_ch[ 2 ] = 6; //Check whether GO is operating in channel 6; + pwdinfo->p2p_info.operation_ch[ 3 ] = 11; //Check whether GO is operating in channel 11; + #endif //CONFIG_P2P_OP_CHK_SOCIAL_CH + pwdinfo->p2p_info.scan_op_ch_only = 1; + _set_timer( &pwdinfo->reset_ch_sitesurvey2, P2P_RESET_SCAN_CH ); + } + } + break; + } + case P2P_INVIT_REQ: + { + // Added by Albert 2010/10/05 + // Received the P2P Invite Request frame. + + DBG_871X( "[%s] Got invite request frame!\n", __FUNCTION__ ); + if ( (p2p_ie=rtw_get_p2p_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen)) ) + { + // Parse the necessary information from the P2P Invitation Request frame. + // For example: The MAC address of sending this P2P Invitation Request frame. + u32 attr_contentlen = 0; + u8 status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE; + struct group_id_info group_id; + u8 invitation_flag = 0; + int j=0; + + merged_p2p_ielen = rtw_get_p2p_merged_ies_len(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_); + + merged_p2pie = rtw_zmalloc(merged_p2p_ielen + 2); // 2 is for EID and Length + if (merged_p2pie == NULL) + { + DBG_871X( "[%s] Malloc p2p ie fail\n", __FUNCTION__); + goto exit; + } + _rtw_memset(merged_p2pie, 0x00, merged_p2p_ielen); + + merged_p2p_ielen = rtw_p2p_merge_ies(frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, merged_p2pie); + + rtw_get_p2p_attr_content( merged_p2pie, merged_p2p_ielen, P2P_ATTR_INVITATION_FLAGS, &invitation_flag, &attr_contentlen); + if ( attr_contentlen ) + { + + rtw_get_p2p_attr_content( merged_p2pie, merged_p2p_ielen, P2P_ATTR_GROUP_BSSID, pwdinfo->p2p_peer_interface_addr, &attr_contentlen); + // Commented by Albert 20120510 + // Copy to the pwdinfo->p2p_peer_interface_addr. + // So that the WFD UI ( or Sigma ) can get the peer interface address by using the following command. + // #> iwpriv wlan0 p2p_get peer_ifa + // After having the peer interface address, the sigma can find the correct conf file for wpa_supplicant. + + if ( attr_contentlen ) + { + DBG_871X( "[%s] GO's BSSID = %.2X %.2X %.2X %.2X %.2X %.2X\n", __FUNCTION__, + pwdinfo->p2p_peer_interface_addr[0], pwdinfo->p2p_peer_interface_addr[1], + pwdinfo->p2p_peer_interface_addr[2], pwdinfo->p2p_peer_interface_addr[3], + pwdinfo->p2p_peer_interface_addr[4], pwdinfo->p2p_peer_interface_addr[5] ); + } + + if ( invitation_flag & P2P_INVITATION_FLAGS_PERSISTENT ) + { + // Re-invoke the persistent group. + + _rtw_memset( &group_id, 0x00, sizeof( struct group_id_info ) ); + rtw_get_p2p_attr_content( merged_p2pie, merged_p2p_ielen, P2P_ATTR_GROUP_ID, ( u8* ) &group_id, &attr_contentlen); + if ( attr_contentlen ) + { + if (_rtw_memcmp(group_id.go_device_addr, adapter_mac_addr(padapter), ETH_ALEN)) + { + // The p2p device sending this p2p invitation request wants this Wi-Fi device to be the persistent GO. + rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_GO ); + rtw_p2p_set_role( pwdinfo, P2P_ROLE_GO ); + status_code = P2P_STATUS_SUCCESS; + } + else + { + // The p2p device sending this p2p invitation request wants to be the persistent GO. + if ( is_matched_in_profilelist( pwdinfo->p2p_peer_interface_addr, &pwdinfo->profileinfo[ 0 ] ) ) + { + u8 operatingch_info[5] = { 0x00 }; + if ( rtw_get_p2p_attr_content(merged_p2pie, merged_p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen) ) + { + if( rtw_ch_set_search_ch(padapter->mlmeextpriv.channel_set, (u32)operatingch_info[4] ) >= 0 ) + { + // The operating channel is acceptable for this device. + pwdinfo->rx_invitereq_info.operation_ch[0]= operatingch_info[4]; + #ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH + pwdinfo->rx_invitereq_info.operation_ch[1]= 1; //Check whether GO is operating in channel 1; + pwdinfo->rx_invitereq_info.operation_ch[2]= 6; //Check whether GO is operating in channel 6; + pwdinfo->rx_invitereq_info.operation_ch[3]= 11; //Check whether GO is operating in channel 11; + #endif //CONFIG_P2P_OP_CHK_SOCIAL_CH + pwdinfo->rx_invitereq_info.scan_op_ch_only = 1; + _set_timer( &pwdinfo->reset_ch_sitesurvey, P2P_RESET_SCAN_CH ); + rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_MATCH ); + rtw_p2p_set_role( pwdinfo, P2P_ROLE_CLIENT ); + status_code = P2P_STATUS_SUCCESS; + } + else + { + // The operating channel isn't supported by this device. + rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_DISMATCH ); + rtw_p2p_set_role( pwdinfo, P2P_ROLE_DEVICE ); + status_code = P2P_STATUS_FAIL_NO_COMMON_CH; + _set_timer( &pwdinfo->restore_p2p_state_timer, 3000 ); + } + } + else + { + // Commented by Albert 20121130 + // Intel will use the different P2P IE to store the operating channel information + // Workaround for Intel WiDi 3.5 + rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_MATCH ); + rtw_p2p_set_role( pwdinfo, P2P_ROLE_CLIENT ); + status_code = P2P_STATUS_SUCCESS; + } + } + else + { + rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_DISMATCH ); + #ifdef CONFIG_INTEL_WIDI + _rtw_memcpy( pwdinfo->p2p_peer_device_addr, group_id.go_device_addr , ETH_ALEN ); + rtw_p2p_set_role( pwdinfo, P2P_ROLE_CLIENT ); + #endif //CONFIG_INTEL_WIDI + + status_code = P2P_STATUS_FAIL_UNKNOWN_P2PGROUP; + } + } + } + else + { + DBG_871X( "[%s] P2P Group ID Attribute NOT FOUND!\n", __FUNCTION__ ); + status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE; + } + } + else + { + // Received the invitation to join a P2P group. + + _rtw_memset( &group_id, 0x00, sizeof( struct group_id_info ) ); + rtw_get_p2p_attr_content( merged_p2pie, merged_p2p_ielen, P2P_ATTR_GROUP_ID, ( u8* ) &group_id, &attr_contentlen); + if ( attr_contentlen ) + { + if (_rtw_memcmp(group_id.go_device_addr, adapter_mac_addr(padapter), ETH_ALEN)) + { + // In this case, the GO can't be myself. + rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_DISMATCH ); + status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE; + } + else + { + // The p2p device sending this p2p invitation request wants to join an existing P2P group + // Commented by Albert 2012/06/28 + // In this case, this Wi-Fi device should use the iwpriv command to get the peer device address. + // The peer device address should be the destination address for the provisioning discovery request. + // Then, this Wi-Fi device should use the iwpriv command to get the peer interface address. + // The peer interface address should be the address for WPS mac address + _rtw_memcpy( pwdinfo->p2p_peer_device_addr, group_id.go_device_addr , ETH_ALEN ); + rtw_p2p_set_role( pwdinfo, P2P_ROLE_CLIENT ); + rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ_JOIN ); + status_code = P2P_STATUS_SUCCESS; + } + } + else + { + DBG_871X( "[%s] P2P Group ID Attribute NOT FOUND!\n", __FUNCTION__ ); + status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE; + } + } + } + else + { + DBG_871X( "[%s] P2P Invitation Flags Attribute NOT FOUND!\n", __FUNCTION__ ); + status_code = P2P_STATUS_FAIL_INFO_UNAVAILABLE; + } + + DBG_871X( "[%s] status_code = %d\n", __FUNCTION__, status_code ); + + pwdinfo->inviteresp_info.token = frame_body[ 7 ]; + issue_p2p_invitation_response( padapter, GetAddr2Ptr(pframe), pwdinfo->inviteresp_info.token, status_code ); + _set_timer( &pwdinfo->restore_p2p_state_timer, 3000 ); + } +#ifdef CONFIG_INTEL_WIDI + if (padapter->mlmepriv.widi_state == INTEL_WIDI_STATE_LISTEN) { + padapter->mlmepriv.widi_state = INTEL_WIDI_STATE_WFD_CONNECTION; + _cancel_timer_ex(&(padapter->mlmepriv.listen_timer)); + intel_widi_wk_cmd(padapter, INTEL_WIDI_LISTEN_STOP_WK, NULL, 0); + } +#endif //CONFIG_INTEL_WIDI + break; + } + case P2P_INVIT_RESP: + { + u8 attr_content = 0x00; + u32 attr_contentlen = 0; + + DBG_871X( "[%s] Got invite response frame!\n", __FUNCTION__ ); + _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer ); + if ( (p2p_ie=rtw_get_p2p_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen)) ) + { + rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen); + + if ( attr_contentlen == 1 ) + { + DBG_871X( "[%s] Status = %d\n", __FUNCTION__, attr_content ); + pwdinfo->invitereq_info.benable = _FALSE; + + if ( attr_content == P2P_STATUS_SUCCESS ) + { + if (_rtw_memcmp(pwdinfo->invitereq_info.go_bssid, adapter_mac_addr(padapter), ETH_ALEN)) + rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO ); + else + rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); + + rtw_p2p_set_state( pwdinfo, P2P_STATE_RX_INVITE_RESP_OK ); + } + else + { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); + rtw_p2p_set_state( pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL ); + } + } + else + { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); + rtw_p2p_set_state( pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL ); + } + } + else + { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); + rtw_p2p_set_state( pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL ); + } + + if ( rtw_p2p_chk_state( pwdinfo, P2P_STATE_RX_INVITE_RESP_FAIL ) ) + { + _set_timer( &pwdinfo->restore_p2p_state_timer, 5000 ); + } + break; + } + case P2P_DEVDISC_REQ: + + process_p2p_devdisc_req(pwdinfo, pframe, len); + + break; + + case P2P_DEVDISC_RESP: + + process_p2p_devdisc_resp(pwdinfo, pframe, len); + + break; + + case P2P_PROVISION_DISC_REQ: + DBG_871X( "[%s] Got Provisioning Discovery Request Frame\n", __FUNCTION__ ); + process_p2p_provdisc_req(pwdinfo, pframe, len); + _rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, GetAddr2Ptr(pframe), ETH_ALEN); + + //20110902 Kurt + //Add the following statement to avoid receiving duplicate prov disc req. such that pre_p2p_state would be covered. + if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ)) + rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); + + rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ); + _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT ); +#ifdef CONFIG_INTEL_WIDI + if (padapter->mlmepriv.widi_state == INTEL_WIDI_STATE_LISTEN) { + padapter->mlmepriv.widi_state = INTEL_WIDI_STATE_WFD_CONNECTION; + _cancel_timer_ex(&(padapter->mlmepriv.listen_timer)); + intel_widi_wk_cmd(padapter, INTEL_WIDI_LISTEN_STOP_WK, NULL, 0); + } +#endif //CONFIG_INTEL_WIDI + break; + + case P2P_PROVISION_DISC_RESP: + // Commented by Albert 20110707 + // Should we check the pwdinfo->tx_prov_disc_info.bsent flag here?? + DBG_871X( "[%s] Got Provisioning Discovery Response Frame\n", __FUNCTION__ ); + // Commented by Albert 20110426 + // The restore timer is enabled when issuing the provisioing request frame in rtw_p2p_prov_disc function. + _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer ); + rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_RSP); + process_p2p_provdisc_resp(pwdinfo, pframe); + _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT ); + break; + + } + } + + +exit: + + if(merged_p2pie) + { + rtw_mfree(merged_p2pie, merged_p2p_ielen + 2); + } +#endif //CONFIG_P2P + return _SUCCESS; +} + +unsigned int on_action_public_vendor(union recv_frame *precv_frame) +{ + unsigned int ret = _FAIL; + u8 *pframe = precv_frame->u.hdr.rx_data; + uint frame_len = precv_frame->u.hdr.len; + u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + + if (_rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE) { + if (rtw_action_public_decache(precv_frame, 7) == _FAIL) + goto exit; + + if (!hal_chk_wl_func(precv_frame->u.hdr.adapter, WL_FUNC_MIRACAST)) + rtw_rframe_del_wfd_ie(precv_frame, 8); + + ret = on_action_public_p2p(precv_frame); + } + +exit: + return ret; +} + +unsigned int on_action_public_default(union recv_frame *precv_frame, u8 action) +{ + unsigned int ret = _FAIL; + u8 *pframe = precv_frame->u.hdr.rx_data; + uint frame_len = precv_frame->u.hdr.len; + u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + u8 token; + _adapter *adapter = precv_frame->u.hdr.adapter; + int cnt = 0; + char msg[64]; + + token = frame_body[2]; + + if (rtw_action_public_decache(precv_frame, 2) == _FAIL) + goto exit; + + #ifdef CONFIG_IOCTL_CFG80211 + cnt += sprintf((msg+cnt), "%s(token:%u)", action_public_str(action), token); + rtw_cfg80211_rx_action(adapter, pframe, frame_len, msg); + #endif + + ret = _SUCCESS; + +exit: + return ret; +} + +unsigned int on_action_public(_adapter *padapter, union recv_frame *precv_frame) +{ + unsigned int ret = _FAIL; + u8 *pframe = precv_frame->u.hdr.rx_data; + uint frame_len = precv_frame->u.hdr.len; + u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + u8 category, action; + + /* check RA matches or not */ + if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN)) + goto exit; + + category = frame_body[0]; + if (category != RTW_WLAN_CATEGORY_PUBLIC) + goto exit; + + action = frame_body[1]; + switch (action) { + case ACT_PUBLIC_BSSCOEXIST: +#ifdef CONFIG_80211N_HT +#ifdef CONFIG_AP_MODE + /*20/40 BSS Coexistence Management frame is a Public Action frame*/ + if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) + rtw_process_public_act_bsscoex(padapter, pframe, frame_len); +#endif /*CONFIG_AP_MODE*/ +#endif /*CONFIG_80211N_HT*/ + break; + case ACT_PUBLIC_VENDOR: + ret = on_action_public_vendor(precv_frame); + break; + default: + ret = on_action_public_default(precv_frame, action); + break; + } + +exit: + return ret; +} + +unsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame) +{ + u8 *pframe = precv_frame->u.hdr.rx_data; + uint frame_len = precv_frame->u.hdr.len; + u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + u8 category, action; + + /* check RA matches or not */ + if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN)) + goto exit; + + category = frame_body[0]; + if (category != RTW_WLAN_CATEGORY_HT) + goto exit; + + action = frame_body[1]; + switch (action) { + case RTW_WLAN_ACTION_HT_SM_PS: +#ifdef CONFIG_80211N_HT +#ifdef CONFIG_AP_MODE + if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) + rtw_process_ht_action_smps(padapter, GetAddr2Ptr(pframe), frame_body[2]); +#endif /*CONFIG_AP_MODE*/ +#endif /*CONFIG_80211N_HT*/ + break; + case RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING: +#ifdef CONFIG_BEAMFORMING + /*DBG_871X("RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING\n");*/ + beamforming_get_report_frame(padapter, precv_frame); +#endif /*CONFIG_BEAMFORMING*/ + break; + default: + break; + } + +exit: + + return _SUCCESS; +} + +#ifdef CONFIG_IEEE80211W +unsigned int OnAction_sa_query(_adapter *padapter, union recv_frame *precv_frame) +{ + u8 *pframe = precv_frame->u.hdr.rx_data; + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u16 tid; + //Baron + + DBG_871X("OnAction_sa_query\n"); + + switch (pframe[WLAN_HDR_A3_LEN+1]) + { + case 0: //SA Query req + _rtw_memcpy(&tid, &pframe[WLAN_HDR_A3_LEN+2], sizeof(u16)); + DBG_871X("OnAction_sa_query request,action=%d, tid=%04x, pframe=%02x-%02x\n" + , pframe[WLAN_HDR_A3_LEN+1], tid, pframe[WLAN_HDR_A3_LEN+2], pframe[WLAN_HDR_A3_LEN+3]); + issue_action_SA_Query(padapter, GetAddr2Ptr(pframe), 1, tid, IEEE80211W_RIGHT_KEY); + break; + + case 1: //SA Query rsp + psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe)); + if (psta != NULL) + _cancel_timer_ex(&psta->dot11w_expire_timer); + + _rtw_memcpy(&tid, &pframe[WLAN_HDR_A3_LEN+2], sizeof(u16)); + DBG_871X("OnAction_sa_query response,action=%d, tid=%04x, cancel timer\n", pframe[WLAN_HDR_A3_LEN+1], tid); + break; + default: + break; + } + if(0) + { + int pp; + printk("pattrib->pktlen = %d =>", pattrib->pkt_len); + for(pp=0;pp< pattrib->pkt_len; pp++) + printk(" %02x ", pframe[pp]); + printk("\n"); + } + + return _SUCCESS; +} +#endif //CONFIG_IEEE80211W + +unsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame) +{ + return _SUCCESS; +} + +unsigned int OnAction_vht(_adapter *padapter, union recv_frame *precv_frame) +{ +#ifdef CONFIG_80211AC_VHT + struct rx_pkt_attrib *prxattrib = &precv_frame->u.hdr.attrib; + u8 *pframe = precv_frame->u.hdr.rx_data; + uint frame_len = precv_frame->u.hdr.len; + struct rtw_ieee80211_hdr_3addr *whdr = (struct rtw_ieee80211_hdr_3addr *)pframe; + u8 *frame_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + u8 category, action; + struct sta_info *psta = NULL; + + /* check RA matches or not */ + if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN)) + goto exit; + + category = frame_body[0]; + if(category != RTW_WLAN_CATEGORY_VHT) + goto exit; + + action = frame_body[1]; + switch (action) { + case RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING: +#ifdef CONFIG_BEAMFORMING + /*DBG_871X("RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING\n");*/ + beamforming_get_report_frame(padapter, precv_frame); +#endif /*CONFIG_BEAMFORMING*/ + break; + case RTW_WLAN_ACTION_VHT_OPMODE_NOTIFICATION: + // CategoryCode(1) + ActionCode(1) + OpModeNotification(1) + //DBG_871X("RTW_WLAN_ACTION_VHT_OPMODE_NOTIFICATION\n"); + psta = rtw_get_stainfo(&padapter->stapriv, whdr->addr2); + if (psta) + rtw_process_vht_op_mode_notify(padapter, &frame_body[2], psta); + break; + default: + break; + } + +exit: +#endif //CONFIG_80211AC_VHT + + return _SUCCESS; +} + +unsigned int OnAction_p2p(_adapter *padapter, union recv_frame *precv_frame) +{ +#ifdef CONFIG_P2P + u8 *frame_body; + u8 category, OUI_Subtype, dialogToken=0; + u8 *pframe = precv_frame->u.hdr.rx_data; + uint len = precv_frame->u.hdr.len; + struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); + + //check RA matches or not + if (!_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(pframe), ETH_ALEN)) + return _SUCCESS; + + frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + + category = frame_body[0]; + if(category != RTW_WLAN_CATEGORY_P2P) + return _SUCCESS; + + if ( cpu_to_be32( *( ( u32* ) ( frame_body + 1 ) ) ) != P2POUI ) + return _SUCCESS; + +#ifdef CONFIG_IOCTL_CFG80211 + if (adapter_wdev_data(padapter)->p2p_enabled + && pwdinfo->driver_interface == DRIVER_CFG80211 + ) { + rtw_cfg80211_rx_action_p2p(padapter, pframe, len); + return _SUCCESS; + } + else +#endif //CONFIG_IOCTL_CFG80211 + { + len -= sizeof(struct rtw_ieee80211_hdr_3addr); + OUI_Subtype = frame_body[5]; + dialogToken = frame_body[6]; + + switch(OUI_Subtype) + { + case P2P_NOTICE_OF_ABSENCE: + + break; + + case P2P_PRESENCE_REQUEST: + + process_p2p_presence_req(pwdinfo, pframe, len); + + break; + + case P2P_PRESENCE_RESPONSE: + + break; + + case P2P_GO_DISC_REQUEST: + + break; + + default: + break; + + } + } +#endif //CONFIG_P2P + + return _SUCCESS; + +} + +unsigned int OnAction(_adapter *padapter, union recv_frame *precv_frame) +{ + int i; + unsigned char category; + struct action_handler *ptable; + unsigned char *frame_body; + u8 *pframe = precv_frame->u.hdr.rx_data; + + frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + + category = frame_body[0]; + + for(i = 0; i < sizeof(OnAction_tbl)/sizeof(struct action_handler); i++) + { + ptable = &OnAction_tbl[i]; + + if(category == ptable->num) + ptable->func(padapter, precv_frame); + + } + + return _SUCCESS; + +} + +unsigned int DoReserved(_adapter *padapter, union recv_frame *precv_frame) +{ + + //DBG_871X("rcvd mgt frame(%x, %x)\n", (GetFrameSubType(pframe) >> 4), *(unsigned int *)GetAddr1Ptr(pframe)); + return _SUCCESS; +} + +struct xmit_frame *_alloc_mgtxmitframe(struct xmit_priv *pxmitpriv, bool once) +{ + struct xmit_frame *pmgntframe; + struct xmit_buf *pxmitbuf; + + if (once) + pmgntframe = rtw_alloc_xmitframe_once(pxmitpriv); + else + pmgntframe = rtw_alloc_xmitframe_ext(pxmitpriv); + + if (pmgntframe == NULL) { + DBG_871X(FUNC_ADPT_FMT" alloc xmitframe fail, once:%d\n", FUNC_ADPT_ARG(pxmitpriv->adapter), once); + goto exit; + } + + if ((pxmitbuf = rtw_alloc_xmitbuf_ext(pxmitpriv)) == NULL) { + DBG_871X(FUNC_ADPT_FMT" alloc xmitbuf fail\n", FUNC_ADPT_ARG(pxmitpriv->adapter)); + rtw_free_xmitframe(pxmitpriv, pmgntframe); + pmgntframe = NULL; + goto exit; + } + + pmgntframe->frame_tag = MGNT_FRAMETAG; + pmgntframe->pxmitbuf = pxmitbuf; + pmgntframe->buf_addr = pxmitbuf->pbuf; + pxmitbuf->priv_data = pmgntframe; + +exit: + return pmgntframe; + +} + +inline struct xmit_frame *alloc_mgtxmitframe(struct xmit_priv *pxmitpriv) +{ + return _alloc_mgtxmitframe(pxmitpriv, _FALSE); +} + +inline struct xmit_frame *alloc_mgtxmitframe_once(struct xmit_priv *pxmitpriv) +{ + return _alloc_mgtxmitframe(pxmitpriv, _TRUE); +} + + +/**************************************************************************** + +Following are some TX fuctions for WiFi MLME + +*****************************************************************************/ + +void update_mgnt_tx_rate(_adapter *padapter, u8 rate) +{ + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + + pmlmeext->tx_rate = rate; + //DBG_871X("%s(): rate = %x\n",__FUNCTION__, rate); +} + + +void update_monitor_frame_attrib(_adapter *padapter, struct pkt_attrib *pattrib) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8 wireless_mode; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct sta_info *psta = NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *pbcmc_sta = NULL; + + psta = rtw_get_stainfo(pstapriv, pattrib->ra); + pbcmc_sta = rtw_get_bcmc_stainfo(padapter); + + pattrib->hdrlen = 24; + pattrib->nr_frags = 1; + pattrib->priority = 7; + + if (pbcmc_sta) + pattrib->mac_id = pbcmc_sta->mac_id; + else { + pattrib->mac_id = 0; + DBG_871X("mgmt use mac_id 0 will affect RA\n"); + } + pattrib->qsel = QSLT_MGNT; + + pattrib->pktlen = 0; + + if (pmlmeext->tx_rate == IEEE80211_CCK_RATE_1MB) + wireless_mode = WIRELESS_11B; + else + wireless_mode = WIRELESS_11G; + + pattrib->raid = rtw_get_mgntframe_raid(padapter, wireless_mode); + #ifdef CONFIG_80211AC_VHT + if (pHalData->rf_type == RF_1T1R) + pattrib->raid = RATEID_IDX_VHT_1SS; + else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R) + pattrib->raid = RATEID_IDX_VHT_2SS; + else if (pHalData->rf_type == RF_3T3R) + pattrib->raid = RATEID_IDX_VHT_3SS; + else + pattrib->raid = RATEID_IDX_BGN_40M_1SS; + #endif + + #ifdef CONFIG_80211AC_VHT + pattrib->rate = MGN_VHT1SS_MCS9; + #else + pattrib->rate = MGN_MCS7; + #endif + + pattrib->encrypt = _NO_PRIVACY_; + pattrib->bswenc = _FALSE; + + pattrib->qos_en = _FALSE; + pattrib->ht_en = 1; + pattrib->bwmode = CHANNEL_WIDTH_20; + pattrib->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + pattrib->sgi = _FALSE; + + pattrib->seqnum = pmlmeext->mgnt_seq; + + pattrib->retry_ctrl = _TRUE; + + pattrib->mbssid = 0; + pattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no; + +} + + +void update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib) +{ + u8 wireless_mode; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct sta_info *psta = NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *pbcmc_sta = NULL; + //_rtw_memset((u8 *)(pattrib), 0, sizeof(struct pkt_attrib)); + + pbcmc_sta = rtw_get_bcmc_stainfo(padapter); + + pattrib->hdrlen = 24; + pattrib->nr_frags = 1; + pattrib->priority = 7; + + if (pbcmc_sta) + pattrib->mac_id = pbcmc_sta->mac_id; + else { + pattrib->mac_id = 0; + DBG_871X("mgmt use mac_id 0 will affect RA\n"); + } + pattrib->qsel = QSLT_MGNT; + + pattrib->pktlen = 0; + + if (pmlmeext->tx_rate == IEEE80211_CCK_RATE_1MB) + wireless_mode = WIRELESS_11B; + else + wireless_mode = WIRELESS_11G; + pattrib->raid = rtw_get_mgntframe_raid(padapter, wireless_mode); + pattrib->rate = pmlmeext->tx_rate; + + pattrib->encrypt = _NO_PRIVACY_; + pattrib->bswenc = _FALSE; + + pattrib->qos_en = _FALSE; + pattrib->ht_en = _FALSE; + pattrib->bwmode = CHANNEL_WIDTH_20; + pattrib->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + pattrib->sgi = _FALSE; + + pattrib->seqnum = pmlmeext->mgnt_seq; + + pattrib->retry_ctrl = _TRUE; + + pattrib->mbssid = 0; + pattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no; + + #ifdef CONFIG_BEAMFORMING + psta = rtw_get_stainfo(pstapriv, pattrib->ra); + if (psta) + update_attrib_txbf_info(padapter, pattrib, psta); + #endif + +} + +void update_mgntframe_attrib_addr(_adapter *padapter, struct xmit_frame *pmgntframe) +{ + u8 *pframe; + struct pkt_attrib *pattrib = &pmgntframe->attrib; + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + + _rtw_memcpy(pattrib->ra, GetAddr1Ptr(pframe), ETH_ALEN); + _rtw_memcpy(pattrib->ta, GetAddr2Ptr(pframe), ETH_ALEN); +} + +void dump_mgntframe(_adapter *padapter, struct xmit_frame *pmgntframe) +{ + if (RTW_CANNOT_RUN(padapter)) { + rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf); + rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe); + return; + } + + rtw_hal_mgnt_xmit(padapter, pmgntframe); +} + +s32 dump_mgntframe_and_wait(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms) +{ + s32 ret = _FAIL; + _irqL irqL; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct xmit_buf *pxmitbuf = pmgntframe->pxmitbuf; + struct submit_ctx sctx; + + if (RTW_CANNOT_RUN(padapter)) { + rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf); + rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe); + return ret; + } + + rtw_sctx_init(&sctx, timeout_ms); + pxmitbuf->sctx = &sctx; + + ret = rtw_hal_mgnt_xmit(padapter, pmgntframe); + + if (ret == _SUCCESS) + ret = rtw_sctx_wait(&sctx, __func__); + + _enter_critical(&pxmitpriv->lock_sctx, &irqL); + pxmitbuf->sctx = NULL; + _exit_critical(&pxmitpriv->lock_sctx, &irqL); + + return ret; +} + +s32 dump_mgntframe_and_wait_ack(_adapter *padapter, struct xmit_frame *pmgntframe) +{ +#ifdef CONFIG_XMIT_ACK + static u8 seq_no = 0; + s32 ret = _FAIL; + u32 timeout_ms = 500;// 500ms + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + #ifdef CONFIG_CONCURRENT_MODE + if (padapter->pbuddy_adapter && !padapter->isprimary) + pxmitpriv = &(padapter->pbuddy_adapter->xmitpriv); + #endif + + if (RTW_CANNOT_RUN(padapter)) { + rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf); + rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe); + return -1; + } + + _enter_critical_mutex(&pxmitpriv->ack_tx_mutex, NULL); + pxmitpriv->ack_tx = _TRUE; + pxmitpriv->seq_no = seq_no++; + pmgntframe->ack_report = 1; + rtw_sctx_init(&(pxmitpriv->ack_tx_ops), timeout_ms); + if (rtw_hal_mgnt_xmit(padapter, pmgntframe) == _SUCCESS) { +#ifdef CONFIG_XMIT_ACK_POLLING + ret = rtw_ack_tx_polling(pxmitpriv, timeout_ms); +#else + ret = rtw_sctx_wait(&(pxmitpriv->ack_tx_ops), __func__); +#endif + } + + pxmitpriv->ack_tx = _FALSE; + _exit_critical_mutex(&pxmitpriv->ack_tx_mutex, NULL); + + return ret; +#else //!CONFIG_XMIT_ACK + dump_mgntframe(padapter, pmgntframe); + rtw_msleep_os(50); + return _SUCCESS; +#endif //!CONFIG_XMIT_ACK +} + +s32 dump_mgntframe_and_wait_ack_timeout(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms) +{ +#ifdef CONFIG_XMIT_ACK + static u8 seq_no = 0; + s32 ret = _FAIL; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + #ifdef CONFIG_CONCURRENT_MODE + if (padapter->pbuddy_adapter && !padapter->isprimary) + pxmitpriv = &(padapter->pbuddy_adapter->xmitpriv); + #endif + + if (RTW_CANNOT_RUN(padapter)) { + rtw_free_xmitbuf(&padapter->xmitpriv, pmgntframe->pxmitbuf); + rtw_free_xmitframe(&padapter->xmitpriv, pmgntframe); + return -1; + } + + _enter_critical_mutex(&pxmitpriv->ack_tx_mutex, NULL); + pxmitpriv->ack_tx = _TRUE; + pxmitpriv->seq_no = seq_no++; + pmgntframe->ack_report = 1; + rtw_sctx_init(&(pxmitpriv->ack_tx_ops), timeout_ms); + if (rtw_hal_mgnt_xmit(padapter, pmgntframe) == _SUCCESS) { +#ifdef CONFIG_XMIT_ACK_POLLING + ret = rtw_ack_tx_polling(pxmitpriv, timeout_ms); +#else + ret = rtw_sctx_wait(&(pxmitpriv->ack_tx_ops), __func__); +#endif + } + + pxmitpriv->ack_tx = _FALSE; + _exit_critical_mutex(&pxmitpriv->ack_tx_mutex, NULL); + + return ret; +#else //!CONFIG_XMIT_ACK + dump_mgntframe(padapter, pmgntframe); + rtw_msleep_os(50); + return _SUCCESS; +#endif //!CONFIG_XMIT_ACK +} + +int update_hidden_ssid(u8 *ies, u32 ies_len, u8 hidden_ssid_mode) +{ + u8 *ssid_ie; + sint ssid_len_ori; + int len_diff = 0; + + ssid_ie = rtw_get_ie(ies, WLAN_EID_SSID, &ssid_len_ori, ies_len); + + //DBG_871X("%s hidden_ssid_mode:%u, ssid_ie:%p, ssid_len_ori:%d\n", __FUNCTION__, hidden_ssid_mode, ssid_ie, ssid_len_ori); + + if(ssid_ie && ssid_len_ori>0) + { + switch(hidden_ssid_mode) + { + case 1: + { + u8 *next_ie = ssid_ie + 2 + ssid_len_ori; + u32 remain_len = 0; + + remain_len = ies_len -(next_ie-ies); + + ssid_ie[1] = 0; + _rtw_memcpy(ssid_ie+2, next_ie, remain_len); + len_diff -= ssid_len_ori; + + break; + } + case 2: + _rtw_memset(&ssid_ie[2], 0, ssid_len_ori); + break; + default: + break; + } + } + + return len_diff; +} + +void issue_beacon(_adapter *padapter, int timeout_ms) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + unsigned int rate_len; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); +#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) + _irqL irqL; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); +#endif //#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); +#endif //CONFIG_P2P + + + //DBG_871X("%s\n", __FUNCTION__); + +#ifdef CONFIG_BCN_ICF + if ((pmgntframe = rtw_alloc_bcnxmitframe(pxmitpriv)) == NULL) +#else + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) +#endif + { + DBG_871X("%s, alloc mgnt frame fail\n", __FUNCTION__); + return; + } +#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) + _enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL); +#endif //#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) + + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + pattrib->qsel = QSLT_BEACON; + #ifdef CONFIG_CONCURRENT_MODE + if(padapter->iface_type == IFACE_PORT1) + pattrib->mbssid = 1; + #endif + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN); + + SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/); + //pmlmeext->mgnt_seq++; + SetFrameSubType(pframe, WIFI_BEACON); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof (struct rtw_ieee80211_hdr_3addr); + + if( (pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) + { + //DBG_871X("ie len=%d\n", cur_network->IELength); +#ifdef CONFIG_P2P + // for P2P : Primary Device Type & Device Name + u32 wpsielen=0, insert_len=0; + u8 *wpsie=NULL; + wpsie = rtw_get_wps_ie(cur_network->IEs+_FIXED_IE_LENGTH_, cur_network->IELength-_FIXED_IE_LENGTH_, NULL, &wpsielen); + + if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && wpsie && wpsielen>0) + { + uint wps_offset, remainder_ielen; + u8 *premainder_ie, *pframe_wscie; + + wps_offset = (uint)(wpsie - cur_network->IEs); + + premainder_ie = wpsie + wpsielen; + + remainder_ielen = cur_network->IELength - wps_offset - wpsielen; + +#ifdef CONFIG_IOCTL_CFG80211 + if(adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211 ) + { + if(pmlmepriv->wps_beacon_ie && pmlmepriv->wps_beacon_ie_len>0) + { + _rtw_memcpy(pframe, cur_network->IEs, wps_offset); + pframe += wps_offset; + pattrib->pktlen += wps_offset; + + _rtw_memcpy(pframe, pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len); + pframe += pmlmepriv->wps_beacon_ie_len; + pattrib->pktlen += pmlmepriv->wps_beacon_ie_len; + + //copy remainder_ie to pframe + _rtw_memcpy(pframe, premainder_ie, remainder_ielen); + pframe += remainder_ielen; + pattrib->pktlen += remainder_ielen; + } + else + { + _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength); + pframe += cur_network->IELength; + pattrib->pktlen += cur_network->IELength; + } + } + else +#endif //CONFIG_IOCTL_CFG80211 + { + pframe_wscie = pframe + wps_offset; + _rtw_memcpy(pframe, cur_network->IEs, wps_offset+wpsielen); + pframe += (wps_offset + wpsielen); + pattrib->pktlen += (wps_offset + wpsielen); + + //now pframe is end of wsc ie, insert Primary Device Type & Device Name + // Primary Device Type + // Type: + *(u16*) ( pframe + insert_len) = cpu_to_be16( WPS_ATTR_PRIMARY_DEV_TYPE ); + insert_len += 2; + + // Length: + *(u16*) ( pframe + insert_len ) = cpu_to_be16( 0x0008 ); + insert_len += 2; + + // Value: + // Category ID + *(u16*) ( pframe + insert_len ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); + insert_len += 2; + + // OUI + *(u32*) ( pframe + insert_len ) = cpu_to_be32( WPSOUI ); + insert_len += 4; + + // Sub Category ID + *(u16*) ( pframe + insert_len ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); + insert_len += 2; + + + // Device Name + // Type: + *(u16*) ( pframe + insert_len ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); + insert_len += 2; + + // Length: + *(u16*) ( pframe + insert_len ) = cpu_to_be16( pwdinfo->device_name_len ); + insert_len += 2; + + // Value: + _rtw_memcpy( pframe + insert_len, pwdinfo->device_name, pwdinfo->device_name_len ); + insert_len += pwdinfo->device_name_len; + + + //update wsc ie length + *(pframe_wscie+1) = (wpsielen -2) + insert_len; + + //pframe move to end + pframe+=insert_len; + pattrib->pktlen += insert_len; + + //copy remainder_ie to pframe + _rtw_memcpy(pframe, premainder_ie, remainder_ielen); + pframe += remainder_ielen; + pattrib->pktlen += remainder_ielen; + } + } + else +#endif //CONFIG_P2P + { + int len_diff; + _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength); + len_diff = update_hidden_ssid( + pframe+_BEACON_IE_OFFSET_ + , cur_network->IELength-_BEACON_IE_OFFSET_ + , pmlmeinfo->hidden_ssid_mode + ); + pframe += (cur_network->IELength+len_diff); + pattrib->pktlen += (cur_network->IELength+len_diff); + } + + { + u8 *wps_ie; + uint wps_ielen; + u8 sr = 0; + wps_ie = rtw_get_wps_ie(pmgntframe->buf_addr+TXDESC_OFFSET+sizeof (struct rtw_ieee80211_hdr_3addr)+_BEACON_IE_OFFSET_, + pattrib->pktlen-sizeof (struct rtw_ieee80211_hdr_3addr)-_BEACON_IE_OFFSET_, NULL, &wps_ielen); + if (wps_ie && wps_ielen>0) { + rtw_get_wps_attr_content(wps_ie, wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8*)(&sr), NULL); + } + if (sr != 0) + set_fwstate(pmlmepriv, WIFI_UNDER_WPS); + else + _clr_fwstate_(pmlmepriv, WIFI_UNDER_WPS); + } + +#ifdef CONFIG_P2P + if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) + { + u32 len; +#ifdef CONFIG_IOCTL_CFG80211 + if(adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211 ) + { + len = pmlmepriv->p2p_beacon_ie_len; + if(pmlmepriv->p2p_beacon_ie && len>0) + _rtw_memcpy(pframe, pmlmepriv->p2p_beacon_ie, len); + } + else +#endif //CONFIG_IOCTL_CFG80211 + { + len = build_beacon_p2p_ie(pwdinfo, pframe); + } + + pframe += len; + pattrib->pktlen += len; + + #ifdef CONFIG_WFD + len = rtw_append_beacon_wfd_ie(padapter, pframe); + pframe += len; + pattrib->pktlen += len; + #endif + } +#endif //CONFIG_P2P + + goto _issue_bcn; + + } + + //below for ad-hoc mode + + //timestamp will be inserted by hardware + pframe += 8; + pattrib->pktlen += 8; + + // beacon interval: 2 bytes + + _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2); + + pframe += 2; + pattrib->pktlen += 2; + + // capability info: 2 bytes + + _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); + + pframe += 2; + pattrib->pktlen += 2; + + // SSID + pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pattrib->pktlen); + + // supported rates... + rate_len = rtw_get_rateset_len(cur_network->SupportedRates); + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8)? 8: rate_len), cur_network->SupportedRates, &pattrib->pktlen); + + // DS parameter set + pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pattrib->pktlen); + + //if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) + { + u8 erpinfo=0; + u32 ATIMWindow; + // IBSS Parameter Set... + //ATIMWindow = cur->Configuration.ATIMWindow; + ATIMWindow = 0; + pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pattrib->pktlen); + + //ERP IE + pframe = rtw_set_ie(pframe, _ERPINFO_IE_, 1, &erpinfo, &pattrib->pktlen); + } + + + // EXTERNDED SUPPORTED RATE + if (rate_len > 8) + { + pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pattrib->pktlen); + } + + + //todo:HT for adhoc + +_issue_bcn: + +#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) + pmlmepriv->update_bcn = _FALSE; + + _exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL); +#endif //#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) + + if ((pattrib->pktlen + TXDESC_SIZE) > 512) + { + DBG_871X("beacon frame too large\n"); + return; + } + + pattrib->last_txcmdsz = pattrib->pktlen; + + //DBG_871X("issue bcn_sz=%d\n", pattrib->last_txcmdsz); + if(timeout_ms > 0) + dump_mgntframe_and_wait(padapter, pmgntframe, timeout_ms); + else + dump_mgntframe(padapter, pmgntframe); + +} + +void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probereq) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + unsigned char *mac, *bssid; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); +#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) + u8 *pwps_ie; + uint wps_ielen; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; +#endif //#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + unsigned int rate_len; +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); +#ifdef CONFIG_WFD + u32 wfdielen = 0; +#endif +#endif //CONFIG_P2P + + //DBG_871X("%s\n", __FUNCTION__); + + if(da == NULL) + return; + + if (rtw_rfctl_is_tx_blocked_by_cac(adapter_to_rfctl(padapter))) + return; + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + { + DBG_871X("%s, alloc mgnt frame fail\n", __FUNCTION__); + return; + } + + + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + mac = adapter_mac_addr(padapter); + bssid = cur_network->MacAddress; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(fctrl, WIFI_PROBERSP); + + pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = pattrib->hdrlen; + pframe += pattrib->hdrlen; + + + if(cur_network->IELength>MAX_IE_SZ) + return; + +#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) + if( (pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) + { + pwps_ie = rtw_get_wps_ie(cur_network->IEs+_FIXED_IE_LENGTH_, cur_network->IELength-_FIXED_IE_LENGTH_, NULL, &wps_ielen); + + //inerset & update wps_probe_resp_ie + if((pmlmepriv->wps_probe_resp_ie!=NULL) && pwps_ie && (wps_ielen>0)) + { + uint wps_offset, remainder_ielen; + u8 *premainder_ie; + + wps_offset = (uint)(pwps_ie - cur_network->IEs); + + premainder_ie = pwps_ie + wps_ielen; + + remainder_ielen = cur_network->IELength - wps_offset - wps_ielen; + + _rtw_memcpy(pframe, cur_network->IEs, wps_offset); + pframe += wps_offset; + pattrib->pktlen += wps_offset; + + wps_ielen = (uint)pmlmepriv->wps_probe_resp_ie[1];//to get ie data len + if((wps_offset+wps_ielen+2)<=MAX_IE_SZ) + { + _rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, wps_ielen+2); + pframe += wps_ielen+2; + pattrib->pktlen += wps_ielen+2; + } + + if((wps_offset+wps_ielen+2+remainder_ielen)<=MAX_IE_SZ) + { + _rtw_memcpy(pframe, premainder_ie, remainder_ielen); + pframe += remainder_ielen; + pattrib->pktlen += remainder_ielen; + } + } + else + { + _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength); + pframe += cur_network->IELength; + pattrib->pktlen += cur_network->IELength; + } + + /* retrieve SSID IE from cur_network->Ssid */ + { + u8 *ssid_ie; + sint ssid_ielen; + sint ssid_ielen_diff; + u8 buf[MAX_IE_SZ]; + u8 *ies = pmgntframe->buf_addr+TXDESC_OFFSET+sizeof(struct rtw_ieee80211_hdr_3addr); + + ssid_ie = rtw_get_ie(ies+_FIXED_IE_LENGTH_, _SSID_IE_, &ssid_ielen, + (pframe-ies)-_FIXED_IE_LENGTH_); + + ssid_ielen_diff = cur_network->Ssid.SsidLength - ssid_ielen; + + if (ssid_ie && cur_network->Ssid.SsidLength) { + uint remainder_ielen; + u8 *remainder_ie; + remainder_ie = ssid_ie+2; + remainder_ielen = (pframe-remainder_ie); + + if (remainder_ielen > MAX_IE_SZ) { + DBG_871X_LEVEL(_drv_warning_, FUNC_ADPT_FMT" remainder_ielen > MAX_IE_SZ\n", FUNC_ADPT_ARG(padapter)); + remainder_ielen = MAX_IE_SZ; + } + + _rtw_memcpy(buf, remainder_ie, remainder_ielen); + _rtw_memcpy(remainder_ie+ssid_ielen_diff, buf, remainder_ielen); + *(ssid_ie+1) = cur_network->Ssid.SsidLength; + _rtw_memcpy(ssid_ie+2, cur_network->Ssid.Ssid, cur_network->Ssid.SsidLength); + + pframe += ssid_ielen_diff; + pattrib->pktlen += ssid_ielen_diff; + } + } + } + else +#endif + { + + //timestamp will be inserted by hardware + pframe += 8; + pattrib->pktlen += 8; + + // beacon interval: 2 bytes + + _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2); + + pframe += 2; + pattrib->pktlen += 2; + + // capability info: 2 bytes + + _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); + + pframe += 2; + pattrib->pktlen += 2; + + //below for ad-hoc mode + + // SSID + pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pattrib->pktlen); + + // supported rates... + rate_len = rtw_get_rateset_len(cur_network->SupportedRates); + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8)? 8: rate_len), cur_network->SupportedRates, &pattrib->pktlen); + + // DS parameter set + pframe =rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pattrib->pktlen); + + if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) + { + u8 erpinfo=0; + u32 ATIMWindow; + // IBSS Parameter Set... + //ATIMWindow = cur->Configuration.ATIMWindow; + ATIMWindow = 0; + pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pattrib->pktlen); + + //ERP IE + pframe = rtw_set_ie(pframe, _ERPINFO_IE_, 1, &erpinfo, &pattrib->pktlen); + } + + + // EXTERNDED SUPPORTED RATE + if (rate_len > 8) + { + pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pattrib->pktlen); + } + + + //todo:HT for adhoc + + } + +#ifdef CONFIG_P2P + if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) + /* IOT issue, When wifi_spec is not set, send probe_resp with P2P IE even if probe_req has no P2P IE */ + && (is_valid_p2p_probereq || !padapter->registrypriv.wifi_spec)) + { + u32 len; +#ifdef CONFIG_IOCTL_CFG80211 + if(adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211 ) + { + //if pwdinfo->role == P2P_ROLE_DEVICE will call issue_probersp_p2p() + len = pmlmepriv->p2p_go_probe_resp_ie_len; + if(pmlmepriv->p2p_go_probe_resp_ie && len>0) + _rtw_memcpy(pframe, pmlmepriv->p2p_go_probe_resp_ie, len); + } + else +#endif //CONFIG_IOCTL_CFG80211 + { + len = build_probe_resp_p2p_ie(pwdinfo, pframe); + } + + pframe += len; + pattrib->pktlen += len; + + #ifdef CONFIG_WFD + len = rtw_append_probe_resp_wfd_ie(padapter, pframe); + pframe += len; + pattrib->pktlen += len; + #endif + } +#endif //CONFIG_P2P + + +#ifdef CONFIG_AUTO_AP_MODE +{ + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; + + DBG_871X("(%s)\n", __FUNCTION__); + + //check rc station + psta = rtw_get_stainfo(pstapriv, da); + if (psta && psta->isrc && psta->pid>0) + { + u8 RC_OUI[4]={0x00,0xE0,0x4C,0x0A}; + u8 RC_INFO[14] = {0}; + //EID[1] + EID_LEN[1] + RC_OUI[4] + MAC[6] + PairingID[2] + ChannelNum[2] + u16 cu_ch = (u16)cur_network->Configuration.DSConfig; + + DBG_871X("%s, reply rc(pid=0x%x) device "MAC_FMT" in ch=%d\n", __FUNCTION__, + psta->pid, MAC_ARG(psta->hwaddr), cu_ch); + + //append vendor specific ie + _rtw_memcpy(RC_INFO, RC_OUI, sizeof(RC_OUI)); + _rtw_memcpy(&RC_INFO[4], mac, ETH_ALEN); + _rtw_memcpy(&RC_INFO[10], (u8*)&psta->pid, 2); + _rtw_memcpy(&RC_INFO[12], (u8*)&cu_ch, 2); + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, sizeof(RC_INFO), RC_INFO, &pattrib->pktlen); + } +} +#endif //CONFIG_AUTO_AP_MODE + + + pattrib->last_txcmdsz = pattrib->pktlen; + + + dump_mgntframe(padapter, pmgntframe); + + return; + +} + +int _issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, u8 ch, bool append_wps, int wait_ack) +{ + int ret = _FAIL; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + unsigned char *mac; + unsigned char bssrate[NumRates]; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + int bssrate_len = 0; + u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + + if (rtw_rfctl_is_tx_blocked_by_cac(adapter_to_rfctl(padapter))) + goto exit; + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + { + goto exit; + } + + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + mac = adapter_mac_addr(padapter); + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + if (da) + { + // unicast probe request frame + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, da, ETH_ALEN); + } + else + { + // broadcast probe request frame + _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, bc_addr, ETH_ALEN); + } + + _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(pframe, WIFI_PROBEREQ); + + pframe += sizeof (struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof (struct rtw_ieee80211_hdr_3addr); + + if(pssid) + pframe = rtw_set_ie(pframe, _SSID_IE_, pssid->SsidLength, pssid->Ssid, &(pattrib->pktlen)); + else + pframe = rtw_set_ie(pframe, _SSID_IE_, 0, NULL, &(pattrib->pktlen)); + + get_rate_set(padapter, bssrate, &bssrate_len); + + if (bssrate_len > 8) + { + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen)); + pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen)); + } + else + { + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen)); + } + + if (ch) + pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, &ch, &pattrib->pktlen); + + if (append_wps) { + //add wps_ie for wps2.0 + if(pmlmepriv->wps_probe_req_ie_len>0 && pmlmepriv->wps_probe_req_ie) + { + _rtw_memcpy(pframe, pmlmepriv->wps_probe_req_ie, pmlmepriv->wps_probe_req_ie_len); + pframe += pmlmepriv->wps_probe_req_ie_len; + pattrib->pktlen += pmlmepriv->wps_probe_req_ie_len; + //pmlmepriv->wps_probe_req_ie_len = 0 ;//reset to zero + } + } + + pattrib->last_txcmdsz = pattrib->pktlen; + + RT_TRACE(_module_rtl871x_mlme_c_,_drv_notice_,("issuing probe_req, tx_len=%d\n", pattrib->last_txcmdsz)); + + if (wait_ack) { + ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); + } else { + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + } + +exit: + return ret; +} + +inline void issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da) +{ + _issue_probereq(padapter, pssid, da, 0, 1, _FALSE); +} + +/* + * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT + * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX + * try_cnt means the maximal TX count to try + */ +int issue_probereq_ex(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da, u8 ch, bool append_wps, + int try_cnt, int wait_ms) +{ + int ret = _FAIL; + int i = 0; + u32 start = rtw_get_current_time(); + + if (rtw_rfctl_is_tx_blocked_by_cac(adapter_to_rfctl(padapter))) + goto exit; + + do + { + ret = _issue_probereq(padapter, pssid, da, ch, append_wps, wait_ms>0?_TRUE:_FALSE); + + i++; + + if (RTW_CANNOT_RUN(padapter)) + break; + + if(i < try_cnt && wait_ms > 0 && ret==_FAIL) + rtw_msleep_os(wait_ms); + + }while((ixmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (rtw_rfctl_is_tx_blocked_by_cac(adapter_to_rfctl(padapter))) + return; + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + { + return; + } + + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(pframe, WIFI_AUTH); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + + if(psta)// for AP mode + { +#ifdef CONFIG_NATIVEAP_MLME + + _rtw_memcpy(pwlanhdr->addr1, psta->hwaddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN); + + + // setting auth algo number + val16 = (u16)psta->authalg; + + if(status != _STATS_SUCCESSFUL_) + val16 = 0; + + if (val16) { + val16 = cpu_to_le16(val16); + use_shared_key = 1; + } + + pframe = rtw_set_fixed_ie(pframe, _AUTH_ALGM_NUM_, (unsigned char *)&val16, &(pattrib->pktlen)); + + // setting auth seq number + val16 =(u16)psta->auth_seq; + val16 = cpu_to_le16(val16); + pframe = rtw_set_fixed_ie(pframe, _AUTH_SEQ_NUM_, (unsigned char *)&val16, &(pattrib->pktlen)); + + // setting status code... + val16 = status; + val16 = cpu_to_le16(val16); + pframe = rtw_set_fixed_ie(pframe, _STATUS_CODE_, (unsigned char *)&val16, &(pattrib->pktlen)); + + // added challenging text... + if ((psta->auth_seq == 2) && (psta->state & WIFI_FW_AUTH_STATE) && (use_shared_key==1)) + { + pframe = rtw_set_ie(pframe, _CHLGETXT_IE_, 128, psta->chg_txt, &(pattrib->pktlen)); + } +#endif + } + else + { + _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); + + // setting auth algo number + val16 = (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared)? 1: 0;// 0:OPEN System, 1:Shared key + if (val16) { + val16 = cpu_to_le16(val16); + use_shared_key = 1; + } + //DBG_871X("%s auth_algo= %s auth_seq=%d\n",__FUNCTION__,(pmlmeinfo->auth_algo==0)?"OPEN":"SHARED",pmlmeinfo->auth_seq); + + //setting IV for auth seq #3 + if ((pmlmeinfo->auth_seq == 3) && (pmlmeinfo->state & WIFI_FW_AUTH_STATE) && (use_shared_key==1)) + { + //DBG_871X("==> iv(%d),key_index(%d)\n",pmlmeinfo->iv,pmlmeinfo->key_index); + val32 = ((pmlmeinfo->iv++) | (pmlmeinfo->key_index << 30)); + val32 = cpu_to_le32(val32); + pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *)&val32, &(pattrib->pktlen)); + + pattrib->iv_len = 4; + } + + pframe = rtw_set_fixed_ie(pframe, _AUTH_ALGM_NUM_, (unsigned char *)&val16, &(pattrib->pktlen)); + + // setting auth seq number + val16 = pmlmeinfo->auth_seq; + val16 = cpu_to_le16(val16); + pframe = rtw_set_fixed_ie(pframe, _AUTH_SEQ_NUM_, (unsigned char *)&val16, &(pattrib->pktlen)); + + + // setting status code... + val16 = status; + val16 = cpu_to_le16(val16); + pframe = rtw_set_fixed_ie(pframe, _STATUS_CODE_, (unsigned char *)&val16, &(pattrib->pktlen)); + + // then checking to see if sending challenging text... + if ((pmlmeinfo->auth_seq == 3) && (pmlmeinfo->state & WIFI_FW_AUTH_STATE) && (use_shared_key==1)) + { + pframe = rtw_set_ie(pframe, _CHLGETXT_IE_, 128, pmlmeinfo->chg_txt, &(pattrib->pktlen)); + + SetPrivacy(fctrl); + + pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pattrib->encrypt = _WEP40_; + + pattrib->icv_len = 4; + + pattrib->pktlen += pattrib->icv_len; + + } + + } + + pattrib->last_txcmdsz = pattrib->pktlen; + + rtw_wep_encrypt(padapter, (u8 *)pmgntframe); + DBG_871X("%s\n", __FUNCTION__); + dump_mgntframe(padapter, pmgntframe); + + return; +} + + +void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *pstat, int pkt_type) +{ +#ifdef CONFIG_AP_MODE + struct xmit_frame *pmgntframe; + struct rtw_ieee80211_hdr *pwlanhdr; + struct pkt_attrib *pattrib; + unsigned char *pbuf, *pframe; + unsigned short val, ie_status; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network); + u8 *ie = pnetwork->IEs; +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); +#ifdef CONFIG_WFD + u32 wfdielen = 0; +#endif + +#endif //CONFIG_P2P + + if (rtw_rfctl_is_tx_blocked_by_cac(adapter_to_rfctl(padapter))) + return; + + DBG_871X("%s\n", __FUNCTION__); + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + { + return; + } + + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy((void *)GetAddr1Ptr(pwlanhdr), pstat->hwaddr, ETH_ALEN); + _rtw_memcpy((void *)GetAddr2Ptr(pwlanhdr), adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy((void *)GetAddr3Ptr(pwlanhdr), get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + if ((pkt_type == WIFI_ASSOCRSP) || (pkt_type == WIFI_REASSOCRSP)) + SetFrameSubType(pwlanhdr, pkt_type); + else + return; + + pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen += pattrib->hdrlen; + pframe += pattrib->hdrlen; + + //capability + val = *(unsigned short *)rtw_get_capability_from_ie(ie); + + pframe = rtw_set_fixed_ie(pframe, _CAPABILITY_ , (unsigned char *)&val, &(pattrib->pktlen)); + + ie_status = cpu_to_le16(status); + pframe = rtw_set_fixed_ie(pframe , _STATUS_CODE_ , (unsigned char *)&ie_status, &(pattrib->pktlen)); + + val = cpu_to_le16(pstat->aid | BIT(14) | BIT(15)); + pframe = rtw_set_fixed_ie(pframe, _ASOC_ID_ , (unsigned char *)&val, &(pattrib->pktlen)); + + if (pstat->bssratelen <= 8) + { + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, pstat->bssratelen, pstat->bssrateset, &(pattrib->pktlen)); + } + else + { + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pstat->bssrateset, &(pattrib->pktlen)); + pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (pstat->bssratelen-8), pstat->bssrateset+8, &(pattrib->pktlen)); + } + +#ifdef CONFIG_IEEE80211W + if (status == _STATS_REFUSED_TEMPORARILY_) { + u8 timeout_itvl[5]; + u32 timeout_interval = 3000; + /* Association Comeback time */ + timeout_itvl[0] = 0x03; + timeout_interval = cpu_to_le32(timeout_interval); + _rtw_memcpy(timeout_itvl+1, &timeout_interval, 4); + pframe = rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, 5, timeout_itvl, &(pattrib->pktlen)); + } +#endif /* CONFIG_IEEE80211W */ + +#ifdef CONFIG_80211N_HT + if ((pstat->flags & WLAN_STA_HT) && (pmlmepriv->htpriv.ht_option)) + { + uint ie_len=0; + + //FILL HT CAP INFO IE + //p = hostapd_eid_ht_capabilities_info(hapd, p); + pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); + if(pbuf && ie_len>0) + { + _rtw_memcpy(pframe, pbuf, ie_len+2); + pframe += (ie_len+2); + pattrib->pktlen +=(ie_len+2); + } + + //FILL HT ADD INFO IE + //p = hostapd_eid_ht_operation(hapd, p); + pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); + if(pbuf && ie_len>0) + { + _rtw_memcpy(pframe, pbuf, ie_len+2); + pframe += (ie_len+2); + pattrib->pktlen +=(ie_len+2); + } + + } +#endif + + /*adding EXT_CAPAB_IE */ + if (pmlmepriv->ext_capab_ie_len > 0) { + uint ie_len = 0; + + pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EXT_CAP_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); + if (pbuf && ie_len > 0) { + _rtw_memcpy(pframe, pbuf, ie_len+2); + pframe += (ie_len+2); + pattrib->pktlen += (ie_len+2); + } + } + +#ifdef CONFIG_80211AC_VHT + if ((pstat->flags & WLAN_STA_VHT) && (pmlmepriv->vhtpriv.vht_option) + && (pstat->wpa_pairwise_cipher != WPA_CIPHER_TKIP) + && (pstat->wpa2_pairwise_cipher != WPA_CIPHER_TKIP)) + { + u32 ie_len=0; + + //FILL VHT CAP IE + pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTCapability, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); + if(pbuf && ie_len>0) + { + _rtw_memcpy(pframe, pbuf, ie_len+2); + pframe += (ie_len+2); + pattrib->pktlen +=(ie_len+2); + } + + //FILL VHT OPERATION IE + pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, EID_VHTOperation, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); + if(pbuf && ie_len>0) + { + _rtw_memcpy(pframe, pbuf, ie_len+2); + pframe += (ie_len+2); + pattrib->pktlen +=(ie_len+2); + } + } +#endif //CONFIG_80211AC_VHT + + //FILL WMM IE + if ((pstat->flags & WLAN_STA_WME) && (pmlmepriv->qospriv.qos_option)) + { + uint ie_len=0; + unsigned char WMM_PARA_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01}; + + for (pbuf = ie + _BEACON_IE_OFFSET_; ;pbuf+= (ie_len + 2)) + { + pbuf = rtw_get_ie(pbuf, _VENDOR_SPECIFIC_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2))); + if(pbuf && _rtw_memcmp(pbuf+2, WMM_PARA_IE, 6)) + { + _rtw_memcpy(pframe, pbuf, ie_len+2); + pframe += (ie_len+2); + pattrib->pktlen +=(ie_len+2); + + break; + } + + if ((pbuf == NULL) || (ie_len == 0)) + { + break; + } + } + + } + + + if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_REALTEK) + { + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 6 , REALTEK_96B_IE, &(pattrib->pktlen)); + } + + //add WPS IE ie for wps 2.0 + if(pmlmepriv->wps_assoc_resp_ie && pmlmepriv->wps_assoc_resp_ie_len>0) + { + _rtw_memcpy(pframe, pmlmepriv->wps_assoc_resp_ie, pmlmepriv->wps_assoc_resp_ie_len); + + pframe += pmlmepriv->wps_assoc_resp_ie_len; + pattrib->pktlen += pmlmepriv->wps_assoc_resp_ie_len; + } + +#ifdef CONFIG_P2P + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && (pstat->is_p2p_device == _TRUE)) { + u32 len; + + if (padapter->wdinfo.driver_interface == DRIVER_CFG80211) { + len = 0; + if (pmlmepriv->p2p_assoc_resp_ie && pmlmepriv->p2p_assoc_resp_ie_len > 0) { + len = pmlmepriv->p2p_assoc_resp_ie_len; + _rtw_memcpy(pframe, pmlmepriv->p2p_assoc_resp_ie, len); + } + } else { + len = build_assoc_resp_p2p_ie(pwdinfo, pframe, pstat->p2p_status_code); + } + pframe += len; + pattrib->pktlen += len; + } + + #ifdef CONFIG_WFD + if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) { + wfdielen = rtw_append_assoc_resp_wfd_ie(padapter, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; + } + #endif + +#endif /* CONFIG_P2P */ + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + +#endif +} + +void issue_assocreq(_adapter *padapter) +{ + int ret = _FAIL; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe, *p; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + unsigned short val16; + unsigned int i, j, ie_len, index=0; + unsigned char rf_type, bssrate[NumRates], sta_bssrate[NumRates]; + PNDIS_802_11_VARIABLE_IEs pIE; + struct registry_priv *pregpriv = &padapter->registrypriv; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + int bssrate_len = 0, sta_bssrate_len = 0; + u8 vs_ie_length = 0; +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + u8 p2pie[ 255 ] = { 0x00 }; + u16 p2pielen = 0; +#ifdef CONFIG_WFD + u32 wfdielen = 0; +#endif +#endif //CONFIG_P2P + +#ifdef CONFIG_DFS + u16 cap; + + /* Dot H */ + u8 pow_cap_ele[2] = { 0x00 }; + u8 sup_ch[ 30 * 2 ] = {0x00 }, sup_ch_idx = 0, idx_5g = 2; //For supported channel +#endif //CONFIG_DFS + + if (rtw_rfctl_is_tx_blocked_by_cac(adapter_to_rfctl(padapter))) + goto exit; + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + goto exit; + + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(pframe, WIFI_ASSOCREQ); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + //caps + +#ifdef CONFIG_DFS + _rtw_memcpy(&cap, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2); + cap |= cap_SpecMgmt; + _rtw_memcpy(pframe, &cap, 2); +#else + _rtw_memcpy(pframe, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2); +#endif //CONFIG_DFS + + pframe += 2; + pattrib->pktlen += 2; + + //listen interval + //todo: listen interval for power saving + val16 = cpu_to_le16(3); + _rtw_memcpy(pframe ,(unsigned char *)&val16, 2); + pframe += 2; + pattrib->pktlen += 2; + + //SSID + pframe = rtw_set_ie(pframe, _SSID_IE_, pmlmeinfo->network.Ssid.SsidLength, pmlmeinfo->network.Ssid.Ssid, &(pattrib->pktlen)); + +#ifdef CONFIG_DFS + /* Dot H */ + if(pmlmeext->cur_channel > 14) + { + pow_cap_ele[0] = 13; // Minimum transmit power capability + pow_cap_ele[1] = 21; // Maximum transmit power capability + pframe = rtw_set_ie(pframe, EID_PowerCap, 2, pow_cap_ele, &(pattrib->pktlen)); + + //supported channels + do{ + if( pmlmeext->channel_set[sup_ch_idx].ChannelNum <= 14 ) + { + sup_ch[0] = 1; //First channel number + sup_ch[1] = pmlmeext->channel_set[sup_ch_idx].ChannelNum; //Number of channel + } + else + { + sup_ch[idx_5g++] = pmlmeext->channel_set[sup_ch_idx].ChannelNum; + sup_ch[idx_5g++] = 1; + } + sup_ch_idx++; + } + while( pmlmeext->channel_set[sup_ch_idx].ChannelNum != 0 ); + pframe = rtw_set_ie(pframe, EID_SupportedChannels, idx_5g, sup_ch, &(pattrib->pktlen)); + } +#endif //CONFIG_DFS + + //supported rate & extended supported rate + +#if 1 // Check if the AP's supported rates are also supported by STA. + get_rate_set(padapter, sta_bssrate, &sta_bssrate_len); + //DBG_871X("sta_bssrate_len=%d\n", sta_bssrate_len); + + if(pmlmeext->cur_channel == 14)// for JAPAN, channel 14 can only uses B Mode(CCK) + { + sta_bssrate_len = 4; + } + + + //for (i = 0; i < sta_bssrate_len; i++) { + // DBG_871X("sta_bssrate[%d]=%02X\n", i, sta_bssrate[i]); + //} + + for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) { + if (pmlmeinfo->network.SupportedRates[i] == 0) break; + DBG_871X("network.SupportedRates[%d]=%02X\n", i, pmlmeinfo->network.SupportedRates[i]); + } + + + for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) { + if (pmlmeinfo->network.SupportedRates[i] == 0) break; + + + // Check if the AP's supported rates are also supported by STA. + for (j=0; j < sta_bssrate_len; j++) { + // Avoid the proprietary data rate (22Mbps) of Handlink WSG-4000 AP + if ( (pmlmeinfo->network.SupportedRates[i]|IEEE80211_BASIC_RATE_MASK) + == (sta_bssrate[j]|IEEE80211_BASIC_RATE_MASK)) { + //DBG_871X("match i = %d, j=%d\n", i, j); + break; + } else { + //DBG_871X("not match: %02X != %02X\n", (pmlmeinfo->network.SupportedRates[i]|IEEE80211_BASIC_RATE_MASK), (sta_bssrate[j]|IEEE80211_BASIC_RATE_MASK)); + } + } + + if (j == sta_bssrate_len) { + // the rate is not supported by STA + DBG_871X("%s(): the rate[%d]=%02X is not supported by STA!\n",__FUNCTION__, i, pmlmeinfo->network.SupportedRates[i]); + } else { + // the rate is supported by STA + bssrate[index++] = pmlmeinfo->network.SupportedRates[i]; + } + } + + bssrate_len = index; + DBG_871X("bssrate_len = %d\n", bssrate_len); + +#else // Check if the AP's supported rates are also supported by STA. +#if 0 + get_rate_set(padapter, bssrate, &bssrate_len); +#else + for (bssrate_len = 0; bssrate_len < NumRates; bssrate_len++) { + if (pmlmeinfo->network.SupportedRates[bssrate_len] == 0) break; + + if (pmlmeinfo->network.SupportedRates[bssrate_len] == 0x2C) // Avoid the proprietary data rate (22Mbps) of Handlink WSG-4000 AP + break; + + bssrate[bssrate_len] = pmlmeinfo->network.SupportedRates[bssrate_len]; + } +#endif +#endif // Check if the AP's supported rates are also supported by STA. + + if ((bssrate_len == 0) && (pmlmeinfo->network.SupportedRates[0] != 0)) { + rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); + rtw_free_xmitframe(pxmitpriv, pmgntframe); + goto exit; //don't connect to AP if no joint supported rate + } + + + if (bssrate_len > 8) + { + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen)); + pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen)); + } + else if (bssrate_len > 0) + { + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen)); + } else { + DBG_871X("%s: Connect to AP without 11b and 11g data rate!\n",__FUNCTION__); + } + + //vendor specific IE, such as WPA, WMM, WPS + for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) + { + pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i); + + switch (pIE->ElementID) + { + case _VENDOR_SPECIFIC_IE_: + if ((_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4)) || + (_rtw_memcmp(pIE->data, WMM_OUI, 4)) || + (_rtw_memcmp(pIE->data, WPS_OUI, 4))) + { + vs_ie_length = pIE->Length; + if((!padapter->registrypriv.wifi_spec) && (_rtw_memcmp(pIE->data, WPS_OUI, 4))) + { + //Commented by Kurt 20110629 + //In some older APs, WPS handshake + //would be fail if we append vender extensions informations to AP + + vs_ie_length = 14; + } + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, vs_ie_length, pIE->data, &(pattrib->pktlen)); + } + break; + + case EID_WPA2: + pframe = rtw_set_ie(pframe, EID_WPA2, pIE->Length, pIE->data, &(pattrib->pktlen)); + break; +#ifdef CONFIG_80211N_HT + case EID_HTCapability: + if(padapter->mlmepriv.htpriv.ht_option==_TRUE) { + if (!(is_ap_in_tkip(padapter))) + { + _rtw_memcpy(&(pmlmeinfo->HT_caps), pIE->data, sizeof(struct HT_caps_element)); + + pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info = cpu_to_le16(pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info); + + pframe = rtw_set_ie(pframe, EID_HTCapability, pIE->Length , (u8 *)(&(pmlmeinfo->HT_caps)), &(pattrib->pktlen)); + } + } + break; + + case EID_EXTCapability: + if(padapter->mlmepriv.htpriv.ht_option==_TRUE) { + pframe = rtw_set_ie(pframe, EID_EXTCapability, pIE->Length, pIE->data, &(pattrib->pktlen)); + } + break; +#endif //CONFIG_80211N_HT +#ifdef CONFIG_80211AC_VHT + case EID_VHTCapability: + if (padapter->mlmepriv.vhtpriv.vht_option ==_TRUE) { + pframe = rtw_set_ie(pframe, EID_VHTCapability, pIE->Length, pIE->data, &(pattrib->pktlen)); + } + break; + + case EID_OpModeNotification: + if (padapter->mlmepriv.vhtpriv.vht_option ==_TRUE) { + pframe = rtw_set_ie(pframe, EID_OpModeNotification, pIE->Length, pIE->data, &(pattrib->pktlen)); + } + break; +#endif // CONFIG_80211AC_VHT + default: + break; + } + + i += (pIE->Length + 2); + } + + if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_REALTEK) + { + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 6 , REALTEK_96B_IE, &(pattrib->pktlen)); + } + + +#ifdef CONFIG_WAPI_SUPPORT + rtw_build_assoc_req_wapi_ie(padapter, pframe, pattrib); +#endif + + +#ifdef CONFIG_P2P + +#ifdef CONFIG_IOCTL_CFG80211 + if(adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->driver_interface == DRIVER_CFG80211 ) + { + if(pmlmepriv->p2p_assoc_req_ie && pmlmepriv->p2p_assoc_req_ie_len>0) + { + _rtw_memcpy(pframe, pmlmepriv->p2p_assoc_req_ie, pmlmepriv->p2p_assoc_req_ie_len); + pframe += pmlmepriv->p2p_assoc_req_ie_len; + pattrib->pktlen += pmlmepriv->p2p_assoc_req_ie_len; + } + } + else +#endif //CONFIG_IOCTL_CFG80211 + { + if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) + { + // Should add the P2P IE in the association request frame. + // P2P OUI + + p2pielen = 0; + p2pie[ p2pielen++ ] = 0x50; + p2pie[ p2pielen++ ] = 0x6F; + p2pie[ p2pielen++ ] = 0x9A; + p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 + + // Commented by Albert 20101109 + // According to the P2P Specification, the association request frame should contain 3 P2P attributes + // 1. P2P Capability + // 2. Extended Listen Timing + // 3. Device Info + // Commented by Albert 20110516 + // 4. P2P Interface + + // P2P Capability + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); + p2pielen += 2; + + // Value: + // Device Capability Bitmap, 1 byte + p2pie[ p2pielen++ ] = DMP_P2P_DEVCAP_SUPPORT; + + // Group Capability Bitmap, 1 byte + if ( pwdinfo->persistent_supported ) + p2pie[ p2pielen++ ] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT; + else + p2pie[ p2pielen++ ] = DMP_P2P_GRPCAP_SUPPORT; + + // Extended Listen Timing + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_EX_LISTEN_TIMING; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0004 ); + p2pielen += 2; + + // Value: + // Availability Period + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); + p2pielen += 2; + + // Availability Interval + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); + p2pielen += 2; + + // Device Info + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO; + + // Length: + // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) + // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); + p2pielen += 2; + + // Value: + // P2P Device Address + _rtw_memcpy(p2pie + p2pielen, adapter_mac_addr(padapter), ETH_ALEN); + p2pielen += ETH_ALEN; + + // Config Method + // This field should be big endian. Noted by P2P specification. + if ( ( pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PEER_DISPLAY_PIN ) || + ( pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_SELF_DISPLAY_PIN ) ) + { + *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_DISPLAY ); + } + else + { + *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_PBC ); + } + + p2pielen += 2; + + // Primary Device Type + // Category ID + *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); + p2pielen += 2; + + // OUI + *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); + p2pielen += 4; + + // Sub Category ID + *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); + p2pielen += 2; + + // Number of Secondary Device Types + p2pie[ p2pielen++ ] = 0x00; // No Secondary Device Type List + + // Device Name + // Type: + *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); + p2pielen += 2; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); + p2pielen += 2; + + // Value: + _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len ); + p2pielen += pwdinfo->device_name_len; + + // P2P Interface + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_INTERFACE; + + // Length: + *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x000D ); + p2pielen += 2; + + // Value: + _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN ); // P2P Device Address + p2pielen += ETH_ALEN; + + p2pie[ p2pielen++ ] = 1; // P2P Interface Address Count + + _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN ); // P2P Interface Address List + p2pielen += ETH_ALEN; + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen ); + } + } + +#endif //CONFIG_P2P + +#ifdef CONFIG_WFD + wfdielen = rtw_append_assoc_req_wfd_ie(padapter, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; +#endif + + pattrib->last_txcmdsz = pattrib->pktlen; + dump_mgntframe(padapter, pmgntframe); + + ret = _SUCCESS; + +exit: + if (ret == _SUCCESS) + rtw_buf_update(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len, (u8 *)pwlanhdr, pattrib->pktlen); + else + rtw_buf_free(&pmlmepriv->assoc_req, &pmlmepriv->assoc_req_len); + + return; +} + +//when wait_ack is ture, this function shoule be called at process context +static int _issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int wait_ack) +{ + int ret = _FAIL; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv; + struct mlme_ext_priv *pmlmeext; + struct mlme_ext_info *pmlmeinfo; + + //DBG_871X("%s:%d\n", __FUNCTION__, power_mode); + + if(!padapter) + goto exit; + + if (rtw_rfctl_is_tx_blocked_by_cac(adapter_to_rfctl(padapter))) + goto exit; + + pxmitpriv = &(padapter->xmitpriv); + pmlmeext = &(padapter->mlmeextpriv); + pmlmeinfo = &(pmlmeext->mlmext_info); + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + { + goto exit; + } + + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + pattrib->retry_ctrl = _FALSE; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) + { + SetFrDs(fctrl); + } + else if((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE) + { + SetToDs(fctrl); + } + + if (power_mode) + { + SetPwrMgt(fctrl); + } + + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(pframe, WIFI_DATA_NULL); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pattrib->last_txcmdsz = pattrib->pktlen; + + if(wait_ack) + { + ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); + } + else + { + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + } + +exit: + return ret; +} + +/* + * [IMPORTANT] Don't call this function in interrupt context + * + * When wait_ms > 0, this function should be called at process context + * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT + * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX + * try_cnt means the maximal TX count to try + * da == NULL for station mode + */ +int issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms) +{ + int ret = _FAIL; + int i = 0; + u32 start = rtw_get_current_time(); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct sta_info *psta; + + if (rtw_rfctl_is_tx_blocked_by_cac(adapter_to_rfctl(padapter))) + goto exit; + + /* da == NULL, assum it's null data for sta to ap*/ + if (da == NULL) + da = get_my_bssid(&(pmlmeinfo->network)); + + psta = rtw_get_stainfo(&padapter->stapriv, da); + if (psta) { + if (power_mode) + rtw_hal_macid_sleep(padapter, psta->mac_id); + else + rtw_hal_macid_wakeup(padapter, psta->mac_id); + } else { + DBG_871X(FUNC_ADPT_FMT ": Can't find sta info for " MAC_FMT ", skip macid %s!!\n", + FUNC_ADPT_ARG(padapter), MAC_ARG(da), power_mode?"sleep":"wakeup"); + rtw_warn_on(1); + } + + do { + ret = _issue_nulldata(padapter, da, power_mode, wait_ms>0?_TRUE:_FALSE); + + i++; + + if (RTW_CANNOT_RUN(padapter)) + break; + + if(i < try_cnt && wait_ms > 0 && ret==_FAIL) + rtw_msleep_os(wait_ms); + + }while((imlmeextpriv; + pmlmeinfo = &pmlmeext->mlmext_info; + + /* da == NULL, assum it's null data for sta to ap*/ + if (da == NULL) + da = get_my_bssid(&(pmlmeinfo->network)); + + ret = _issue_nulldata(padapter, da, power_mode, _FALSE); + + return ret; +} + +//when wait_ack is ture, this function shoule be called at process context +static int _issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, int wait_ack) +{ + int ret = _FAIL; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl, *qc; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (rtw_rfctl_is_tx_blocked_by_cac(adapter_to_rfctl(padapter))) + goto exit; + + DBG_871X("%s\n", __FUNCTION__); + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + { + goto exit; + } + + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + pattrib->hdrlen +=2; + pattrib->qos_en = _TRUE; + pattrib->eosp = 1; + pattrib->ack_policy = 0; + pattrib->mdata = 0; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) + { + SetFrDs(fctrl); + } + else if((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE) + { + SetToDs(fctrl); + } + + if(pattrib->mdata) + SetMData(fctrl); + + qc = (unsigned short *)(pframe + pattrib->hdrlen - 2); + + SetPriority(qc, tid); + + SetEOSP(qc, pattrib->eosp); + + SetAckpolicy(qc, pattrib->ack_policy); + + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(pframe, WIFI_QOS_DATA_NULL); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr_qos); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos); + + pattrib->last_txcmdsz = pattrib->pktlen; + + if(wait_ack) + { + ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); + } + else + { + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + } + +exit: + return ret; +} + +/* + * when wait_ms >0 , this function should be called at process context + * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT + * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX + * try_cnt means the maximal TX count to try + * da == NULL for station mode + */ +int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, int try_cnt, int wait_ms) +{ + int ret = _FAIL; + int i = 0; + u32 start = rtw_get_current_time(); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (rtw_rfctl_is_tx_blocked_by_cac(adapter_to_rfctl(padapter))) + goto exit; + + /* da == NULL, assum it's null data for sta to ap*/ + if (da == NULL) + da = get_my_bssid(&(pmlmeinfo->network)); + + do + { + ret = _issue_qos_nulldata(padapter, da, tid, wait_ms>0?_TRUE:_FALSE); + + i++; + + if (RTW_CANNOT_RUN(padapter)) + break; + + if(i < try_cnt && wait_ms > 0 && ret==_FAIL) + rtw_msleep_os(wait_ms); + + }while((ixmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + int ret = _FAIL; +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); +#endif //CONFIG_P2P + + //DBG_871X("%s to "MAC_FMT"\n", __func__, MAC_ARG(da)); + +#ifdef CONFIG_P2P + if ( !( rtw_p2p_chk_state( pwdinfo, P2P_STATE_NONE ) ) && ( pwdinfo->rx_invitereq_info.scan_op_ch_only ) ) + { + _cancel_timer_ex( &pwdinfo->reset_ch_sitesurvey ); + _set_timer( &pwdinfo->reset_ch_sitesurvey, 10 ); + } +#endif //CONFIG_P2P + + if (rtw_rfctl_is_tx_blocked_by_cac(adapter_to_rfctl(padapter))) + goto exit; + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + { + goto exit; + } + + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + pattrib->retry_ctrl = _FALSE; + pattrib->key_type = key_type; + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(pframe, WIFI_DEAUTH); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + reason = cpu_to_le16(reason); + pframe = rtw_set_fixed_ie(pframe, _RSON_CODE_ , (unsigned char *)&reason, &(pattrib->pktlen)); + + pattrib->last_txcmdsz = pattrib->pktlen; + + + if(wait_ack) + { + ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); + } + else + { + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + } + +exit: + return ret; +} + +int issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason) +{ + DBG_871X("%s to "MAC_FMT"\n", __func__, MAC_ARG(da)); + return _issue_deauth(padapter, da, reason, _FALSE, IEEE80211W_RIGHT_KEY); +} + +#ifdef CONFIG_IEEE80211W +int issue_deauth_11w(_adapter *padapter, unsigned char *da, unsigned short reason, u8 key_type) +{ + DBG_871X("%s to "MAC_FMT"\n", __func__, MAC_ARG(da)); + return _issue_deauth(padapter, da, reason, _FALSE, key_type); +} +#endif /* CONFIG_IEEE80211W */ + +/* + * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT + * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX + * try_cnt means the maximal TX count to try + */ +int issue_deauth_ex(_adapter *padapter, u8 *da, unsigned short reason, int try_cnt, + int wait_ms) +{ + int ret = _FAIL; + int i = 0; + u32 start = rtw_get_current_time(); + + if (rtw_rfctl_is_tx_blocked_by_cac(adapter_to_rfctl(padapter))) + goto exit; + + do + { + ret = _issue_deauth(padapter, da, reason, wait_ms > 0 ? _TRUE:_FALSE, IEEE80211W_RIGHT_KEY); + + i++; + + if (RTW_CANNOT_RUN(padapter)) + break; + + if(i < try_cnt && wait_ms > 0 && ret==_FAIL) + rtw_msleep_os(wait_ms); + + }while((ixmitpriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (rtw_rfctl_is_tx_blocked_by_cac(adapter_to_rfctl(padapter))) + return; + + DBG_871X(FUNC_NDEV_FMT" ra="MAC_FMT", ch:%u, offset:%u\n", + FUNC_NDEV_ARG(padapter->pnetdev), MAC_ARG(ra), new_ch, ch_offset); + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + return; + + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, ra, ETH_ALEN); /* RA */ + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); /* TA */ + _rtw_memcpy(pwlanhdr->addr3, ra, ETH_ALEN); /* DA = RA */ + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + /* category, action */ + { + u8 category, action; + category = RTW_WLAN_CATEGORY_SPECTRUM_MGMT; + action = RTW_WLAN_ACTION_SPCT_CHL_SWITCH; + + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + } + + pframe = rtw_set_ie_ch_switch(pframe, &(pattrib->pktlen), 0, new_ch, 0); + pframe = rtw_set_ie_secondary_ch_offset(pframe, &(pattrib->pktlen), + hal_ch_offset_to_secondary_ch_offset(ch_offset)); + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + +} + +#ifdef CONFIG_IEEE80211W +void issue_action_SA_Query(_adapter *padapter, unsigned char *raddr, unsigned char action, unsigned short tid, u8 key_type) +{ + u8 category = RTW_WLAN_CATEGORY_SA_QUERY; + u16 reason_code; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + u8 *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + u16 *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; + struct registry_priv *pregpriv = &padapter->registrypriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + if (rtw_rfctl_is_tx_blocked_by_cac(adapter_to_rfctl(padapter))) + return; + + DBG_871X("%s, %04x\n", __FUNCTION__, tid); + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + { + DBG_871X("%s: alloc_mgtxmitframe fail\n", __FUNCTION__); + return; + } + + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + pattrib->key_type = key_type; + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + if(raddr) + _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); + else + _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pframe = rtw_set_fixed_ie(pframe, 1, &category, &pattrib->pktlen); + pframe = rtw_set_fixed_ie(pframe, 1, &action, &pattrib->pktlen); + + switch (action) + { + case 0: //SA Query req + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)&pmlmeext->sa_query_seq, &pattrib->pktlen); + pmlmeext->sa_query_seq++; + /* send sa query request to AP, AP should reply sa query response in 1 second */ + if (pattrib->key_type == IEEE80211W_RIGHT_KEY) { + psta = rtw_get_stainfo(pstapriv, raddr); + if (psta != NULL) { + /* DBG_871X("%s, %d, set dot11w_expire_timer\n", __func__, __LINE__); */ + _set_timer(&psta->dot11w_expire_timer, 1000); + } + } + break; + + case 1: //SA Query rsp + tid = cpu_to_le16(tid); + /* DBG_871X("rtw_set_fixed_ie, %04x\n", tid); */ + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)&tid, &pattrib->pktlen); + break; + default: + break; + } + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); +} +#endif //CONFIG_IEEE80211W + +/** + * issue_action_ba - internal function to TX Block Ack action frame + * @padapter: the adapter to TX + * @raddr: receiver address + * @action: Block Ack Action + * @tid: tid + * @size: the announced AMPDU buffer size. used by ADDBA_RESP + * @status: status/reason code. used by ADDBA_RESP, DELBA + * @initiator: if we are the initiator of AMPDU association. used by DELBA + * @wait_ack: used xmit ack + * + * Returns: + * _SUCCESS: No xmit ack is used or acked + * _FAIL: not acked when using xmit ack + */ +static int issue_action_ba(_adapter *padapter, unsigned char *raddr, unsigned char action + , u8 tid, u8 size, u16 status, u8 initiator, int wait_ack) +{ + int ret = _FAIL; + u8 category = RTW_WLAN_CATEGORY_BACK; + u16 start_seq; + u16 BA_para_set; + u16 BA_timeout_value; + u16 BA_starting_seqctrl; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + u8 *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + u16 *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; + struct registry_priv *pregpriv = &padapter->registrypriv; + +#ifdef CONFIG_80211N_HT + + if (rtw_rfctl_is_tx_blocked_by_cac(adapter_to_rfctl(padapter))) + goto exit; + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + goto exit; + + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + //_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + + if (category == 3) + { + switch (action) + { + case RTW_WLAN_ACTION_ADDBA_REQ: + do { + pmlmeinfo->dialogToken++; + } while (pmlmeinfo->dialogToken == 0); + pframe = rtw_set_fixed_ie(pframe, 1, &(pmlmeinfo->dialogToken), &(pattrib->pktlen)); + + #if defined(CONFIG_RTL8188E) && defined(CONFIG_SDIO_HCI) + BA_para_set = (0x0802 | ((tid & 0xf) << 2)); /* immediate ack & 16 buffer size */ + #else + BA_para_set = (0x1002 | ((tid & 0xf) << 2)); /* immediate ack & 64 buffer size */ + #endif + + BA_para_set = cpu_to_le16(BA_para_set); + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen)); + + //BA_timeout_value = 0xffff;//max: 65535 TUs(~ 65 ms) + BA_timeout_value = 5000;//~ 5ms + BA_timeout_value = cpu_to_le16(BA_timeout_value); + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_timeout_value)), &(pattrib->pktlen)); + + //if ((psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress)) != NULL) + if ((psta = rtw_get_stainfo(pstapriv, raddr)) != NULL) + { + start_seq = (psta->sta_xmitpriv.txseq_tid[tid & 0x07]&0xfff) + 1; + + DBG_871X("BA_starting_seqctrl = %d for TID=%d\n", start_seq, tid & 0x07); + + psta->BA_starting_seqctrl[tid & 0x07] = start_seq; + + BA_starting_seqctrl = start_seq << 4; + } + + BA_starting_seqctrl = cpu_to_le16(BA_starting_seqctrl); + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_starting_seqctrl)), &(pattrib->pktlen)); + break; + + case RTW_WLAN_ACTION_ADDBA_RESP: + pframe = rtw_set_fixed_ie(pframe, 1, &(pmlmeinfo->ADDBA_req.dialog_token), &(pattrib->pktlen)); + status = cpu_to_le16(status); + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&status), &(pattrib->pktlen)); + + BA_para_set = le16_to_cpu(pmlmeinfo->ADDBA_req.BA_para_set); + + BA_para_set &= ~IEEE80211_ADDBA_PARAM_TID_MASK; + BA_para_set |= (tid << 2) & IEEE80211_ADDBA_PARAM_TID_MASK; + + BA_para_set &= ~RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK; + BA_para_set |= (size << 6) & RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK; + + if (!padapter->registrypriv.wifi_spec) { + if(pregpriv->ampdu_amsdu==0)//disabled + BA_para_set &= ~BIT(0); + else if(pregpriv->ampdu_amsdu==1)//enabled + BA_para_set |= BIT(0); + } + + BA_para_set = cpu_to_le16(BA_para_set); + + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(pmlmeinfo->ADDBA_req.BA_timeout_value)), &(pattrib->pktlen)); + break; + + case RTW_WLAN_ACTION_DELBA: + BA_para_set = 0; + BA_para_set |= (tid << 12) & IEEE80211_DELBA_PARAM_TID_MASK; + BA_para_set |= (initiator << 11) & IEEE80211_DELBA_PARAM_INITIATOR_MASK; + + BA_para_set = cpu_to_le16(BA_para_set); + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen)); + status = cpu_to_le16(status); + pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(status)), &(pattrib->pktlen)); + break; + default: + break; + } + } + + pattrib->last_txcmdsz = pattrib->pktlen; + + if (wait_ack) { + ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); + } else { + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + } + +exit: +#endif //CONFIG_80211N_HT + return ret; +} + +/** + * issue_addba_req - TX ADDBA_REQ + * @adapter: the adapter to TX + * @ra: receiver address + * @tid: tid + */ +inline void issue_addba_req(_adapter *adapter, unsigned char *ra, u8 tid) +{ + issue_action_ba(adapter, ra, RTW_WLAN_ACTION_ADDBA_REQ + , tid + , 0 /* unused */ + , 0 /* unused */ + , 0 /* unused */ + , _FALSE + ); + DBG_871X(FUNC_ADPT_FMT" ra="MAC_FMT" tid=%u\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), tid); + +} + +/** + * issue_addba_rsp - TX ADDBA_RESP + * @adapter: the adapter to TX + * @ra: receiver address + * @tid: tid + * @status: status code + * @size: the announced AMPDU buffer size + */ +inline void issue_addba_rsp(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size) +{ + issue_action_ba(adapter, ra, RTW_WLAN_ACTION_ADDBA_RESP + , tid + , size + , status + , 0 /* unused */ + , _FALSE + ); + DBG_871X(FUNC_ADPT_FMT" ra="MAC_FMT" status=%u, tid=%u, size=%u\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), status, tid, size); +} + +/** + * issue_addba_rsp_wait_ack - TX ADDBA_RESP and wait ack + * @adapter: the adapter to TX + * @ra: receiver address + * @tid: tid + * @status: status code + * @size: the announced AMPDU buffer size + * @try_cnt: the maximal TX count to try + * @wait_ms: == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT + * > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX + */ +inline u8 issue_addba_rsp_wait_ack(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size, int try_cnt, int wait_ms) +{ + int ret = _FAIL; + int i = 0; + u32 start = rtw_get_current_time(); + + if (rtw_rfctl_is_tx_blocked_by_cac(adapter_to_rfctl(adapter))) + goto exit; + + do { + ret = issue_action_ba(adapter, ra, RTW_WLAN_ACTION_ADDBA_RESP + , tid + , size + , status + , 0 /* unused */ + , _TRUE + ); + + i++; + + if (RTW_CANNOT_RUN(adapter)) + break; + + if (i < try_cnt && wait_ms > 0 && ret == _FAIL) + rtw_msleep_os(wait_ms); + + } while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0))); + + if (ret != _FAIL) { + ret = _SUCCESS; + #ifndef DBG_XMIT_ACK + /* goto exit; */ + #endif + } + + if (try_cnt && wait_ms) { + DBG_871X(FUNC_ADPT_FMT" ra="MAC_FMT" tid=%u%s, %d/%d in %u ms\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), tid + , ret == _SUCCESS?", acked":"", i, try_cnt, rtw_get_passing_time_ms(start)); + } + +exit: + return ret; +} + +/** + * issue_del_ba - TX DELBA + * @adapter: the adapter to TX + * @ra: receiver address + * @tid: tid + * @reason: reason code + * @initiator: if we are the initiator of AMPDU association. used by DELBA + */ +inline void issue_del_ba(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator) +{ + issue_action_ba(adapter, ra, RTW_WLAN_ACTION_DELBA + , tid + , 0 /* unused */ + , reason + , initiator + , _FALSE + ); + DBG_871X(FUNC_ADPT_FMT" ra="MAC_FMT" reason=%u, tid=%u, initiator=%u\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), reason, tid, initiator); +} + +/** + * issue_del_ba_ex - TX DELBA with xmit ack options + * @adapter: the adapter to TX + * @ra: receiver address + * @tid: tid + * @reason: reason code + * @initiator: if we are the initiator of AMPDU association. used by DELBA + * @try_cnt: the maximal TX count to try + * @wait_ms: == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT + * > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX + */ +int issue_del_ba_ex(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator + , int try_cnt, int wait_ms) +{ + int ret = _FAIL; + int i = 0; + u32 start = rtw_get_current_time(); + + if (rtw_rfctl_is_tx_blocked_by_cac(adapter_to_rfctl(adapter))) + goto exit; + + do { + ret = issue_action_ba(adapter, ra, RTW_WLAN_ACTION_DELBA + , tid + , 0 /* unused */ + , reason + , initiator + , wait_ms > 0?_TRUE:_FALSE + ); + + i++; + + if (RTW_CANNOT_RUN(adapter)) + break; + + if (i < try_cnt && wait_ms > 0 && ret == _FAIL) + rtw_msleep_os(wait_ms); + + } while ((i < try_cnt) && ((ret == _FAIL) || (wait_ms == 0))); + + if (ret != _FAIL) { + ret = _SUCCESS; + #ifndef DBG_XMIT_ACK + /* goto exit; */ + #endif + } + + if (try_cnt && wait_ms) { + DBG_871X(FUNC_ADPT_FMT" ra="MAC_FMT" reason=%u, tid=%u, initiator=%u%s, %d/%d in %u ms\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(ra), reason, tid, initiator + , ret == _SUCCESS?", acked":"", i, try_cnt, rtw_get_passing_time_ms(start)); + } +exit: + return ret; +} + +static void issue_action_BSSCoexistPacket(_adapter *padapter) +{ + _irqL irqL; + _list *plist, *phead; + unsigned char category, action; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + struct wlan_network *pnetwork = NULL; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + _queue *queue = &(pmlmepriv->scanned_queue); + u8 InfoContent[16] = {0}; + u8 ICS[8][15]; +#ifdef CONFIG_80211N_HT + if((pmlmepriv->num_FortyMHzIntolerant==0) || (pmlmepriv->num_sta_no_ht==0)) + return; + + if(_TRUE == pmlmeinfo->bwmode_updated) + return; + + if (rtw_rfctl_is_tx_blocked_by_cac(adapter_to_rfctl(padapter))) + return; + + DBG_871X("%s\n", __FUNCTION__); + + + category = RTW_WLAN_CATEGORY_PUBLIC; + action = ACT_PUBLIC_BSSCOEXIST; + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + { + return; + } + + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + + + // + if(pmlmepriv->num_FortyMHzIntolerant>0) + { + u8 iedata=0; + + iedata |= BIT(2);//20 MHz BSS Width Request + + pframe = rtw_set_ie(pframe, EID_BSSCoexistence, 1, &iedata, &(pattrib->pktlen)); + + } + + + // + _rtw_memset(ICS, 0, sizeof(ICS)); + if(pmlmepriv->num_sta_no_ht>0) + { + int i; + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + while(1) + { + int len; + u8 *p; + WLAN_BSSID_EX *pbss_network; + + if (rtw_end_of_queue_search(phead,plist)== _TRUE) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + + plist = get_next(plist); + + pbss_network = (WLAN_BSSID_EX *)&pnetwork->network; + + p = rtw_get_ie(pbss_network->IEs + _FIXED_IE_LENGTH_, _HT_CAPABILITY_IE_, &len, pbss_network->IELength - _FIXED_IE_LENGTH_); + if((p==NULL) || (len==0))//non-HT + { + if((pbss_network->Configuration.DSConfig<=0) || (pbss_network->Configuration.DSConfig>14)) + continue; + + ICS[0][pbss_network->Configuration.DSConfig]=1; + + if(ICS[0][0] == 0) + ICS[0][0] = 1; + } + + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + + for(i= 0;i<8;i++) + { + if(ICS[i][0] == 1) + { + int j, k = 0; + + InfoContent[k] = i; + //SET_BSS_INTOLERANT_ELE_REG_CLASS(InfoContent,i); + k++; + + for(j=1;j<=14;j++) + { + if(ICS[i][j]==1) + { + if(k<16) + { + InfoContent[k] = j; //channel number + //SET_BSS_INTOLERANT_ELE_CHANNEL(InfoContent+k, j); + k++; + } + } + } + + pframe = rtw_set_ie(pframe, EID_BSSIntolerantChlReport, k, InfoContent, &(pattrib->pktlen)); + + } + + } + + + } + + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); +#endif //CONFIG_80211N_HT +} + +// Spatial Multiplexing Powersave (SMPS) action frame +int _issue_action_SM_PS(_adapter *padapter , unsigned char *raddr , u8 NewMimoPsMode , u8 wait_ack) +{ + + int ret = _FAIL; + unsigned char category = RTW_WLAN_CATEGORY_HT; + u8 action = RTW_WLAN_ACTION_HT_SM_PS; + u8 sm_power_control=0; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + + if(NewMimoPsMode==WLAN_HT_CAP_SM_PS_DISABLED) + { + sm_power_control = sm_power_control & ~(BIT(0)); // SM Power Save Enable = 0 SM Power Save Disable + } + else if(NewMimoPsMode==WLAN_HT_CAP_SM_PS_STATIC) + { + sm_power_control = sm_power_control | BIT(0); // SM Power Save Enable = 1 SM Power Save Enable + sm_power_control = sm_power_control & ~(BIT(1)); // SM Mode = 0 Static Mode + } + else if(NewMimoPsMode==WLAN_HT_CAP_SM_PS_DYNAMIC) + { + sm_power_control = sm_power_control | BIT(0); // SM Power Save Enable = 1 SM Power Save Enable + sm_power_control = sm_power_control | BIT(1); // SM Mode = 1 Dynamic Mode + } + else + return ret; + + if (rtw_rfctl_is_tx_blocked_by_cac(adapter_to_rfctl(padapter))) + return ret; + + DBG_871X("%s, sm_power_control=%u, NewMimoPsMode=%u\n", __FUNCTION__ , sm_power_control , NewMimoPsMode ); + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + return ret; + + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); /* RA */ + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); /* TA */ + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); /* DA = RA */ + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + /* category, action */ + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + + pframe = rtw_set_fixed_ie(pframe, 1, &(sm_power_control), &(pattrib->pktlen)); + + pattrib->last_txcmdsz = pattrib->pktlen; + + if(wait_ack) + { + ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); + } + else + { + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + } + + if (ret != _SUCCESS) + DBG_8192C("%s, ack to\n", __func__); + + return ret; +} + +/* + * wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT + * wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX + * try_cnt means the maximal TX count to try + */ +int issue_action_SM_PS_wait_ack(_adapter *padapter, unsigned char *raddr, u8 NewMimoPsMode, int try_cnt, int wait_ms) +{ + int ret = _FAIL; + int i = 0; + u32 start = rtw_get_current_time(); + + if (rtw_rfctl_is_tx_blocked_by_cac(adapter_to_rfctl(padapter))) + goto exit; + + do { + ret = _issue_action_SM_PS(padapter, raddr, NewMimoPsMode , wait_ms>0?_TRUE:_FALSE ); + + i++; + + if (RTW_CANNOT_RUN(padapter)) + break; + + if(i < try_cnt && wait_ms > 0 && ret==_FAIL) + rtw_msleep_os(wait_ms); + + }while((irecvreorder_ctrl[tid].enable == _TRUE) { + u8 ampdu_size_bak = sta->recvreorder_ctrl[tid].ampdu_size; + + sta->recvreorder_ctrl[tid].enable = _FALSE; + sta->recvreorder_ctrl[tid].ampdu_size = RX_AMPDU_SIZE_INVALID; + + if (rtw_del_rx_ampdu_test_trigger_no_tx_fail()) + ret = _FAIL; + else if (wait_ack) + ret = issue_del_ba_ex(adapter, sta->hwaddr, tid, 37, initiator, 3, 1); + else + issue_del_ba(adapter, sta->hwaddr, tid, 37, initiator); + + if (ret == _FAIL && sta->recvreorder_ctrl[tid].enable == _FALSE) + sta->recvreorder_ctrl[tid].ampdu_size = ampdu_size_bak; + } + } else if (initiator == 1) { + /* originator */ +#ifdef CONFIG_80211N_HT + if (force || sta->htpriv.agg_enable_bitmap & BIT(tid)) { + sta->htpriv.agg_enable_bitmap &= ~BIT(tid); + sta->htpriv.candidate_tid_bitmap &= ~BIT(tid); + issue_del_ba(adapter, sta->hwaddr, tid, 37, initiator); + } +#endif + } + +exit: + return ret; +} + +inline unsigned int send_delba_sta_tid(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid + , u8 force) +{ + return _send_delba_sta_tid(adapter, initiator, sta, tid, force, 0); +} + +inline unsigned int send_delba_sta_tid_wait_ack(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid + , u8 force) +{ + return _send_delba_sta_tid(adapter, initiator, sta, tid, force, 1); +} + +unsigned int send_delba(_adapter *padapter, u8 initiator, u8 *addr) +{ + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta = NULL; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u16 tid; + + if ((pmlmeinfo->state&0x03) != WIFI_FW_AP_STATE) + if (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) + return _SUCCESS; + + psta = rtw_get_stainfo(pstapriv, addr); + if(psta==NULL) + return _SUCCESS; + + #if 0 + DBG_871X("%s:%s\n", __func__, (initiator == 0)?"RX_DIR":"TX_DIR"); + if (initiator == 1) /* originator */ + DBG_871X("tx agg_enable_bitmap(0x%08x)\n", psta->htpriv.agg_enable_bitmap); + #endif + + for (tid = 0; tid < TID_NUM; tid++) + send_delba_sta_tid(padapter, initiator, psta, tid, 0); + + return _SUCCESS; +} + +unsigned int send_beacon(_adapter *padapter) +{ + u8 bxmitok = _FALSE; + int issue=0; + int poll = 0; +#if defined(CONFIG_PCI_HCI) && defined(RTL8814AE_SW_BCN) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); +#endif +//#ifdef CONFIG_CONCURRENT_MODE + //struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + //struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + //_adapter *pbuddy_adapter = padapter->pbuddy_adapter; + //struct mlme_priv *pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv); +//#endif + +#ifdef CONFIG_PCI_HCI + //DBG_871X("%s\n", __FUNCTION__); + + rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL); + + /* 8192EE Port select for Beacon DL */ + rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL); + + issue_beacon(padapter, 0); + +#ifdef RTL8814AE_SW_BCN + if (pHalData->bCorrectBCN != 0) + DBG_871X("%s, line%d, Warnning, pHalData->bCorrectBCN != 0\n", __func__, __LINE__); + pHalData->bCorrectBCN = 1; +#endif + + return _SUCCESS; +#endif + +#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + u32 start = rtw_get_current_time(); + + rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL); + rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL); + do{ + issue_beacon(padapter, 100); + issue++; + do { + rtw_yield_os(); + rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8 *)(&bxmitok)); + poll++; + } while ((poll%10) != 0 && _FALSE == bxmitok && !RTW_CANNOT_RUN(padapter)); + + } while (_FALSE == bxmitok && issue < 100 && !RTW_CANNOT_RUN(padapter)); + + if (RTW_CANNOT_RUN(padapter)) + return _FAIL; + + + if(_FALSE == bxmitok) + { + DBG_871X("%s fail! %u ms\n", __FUNCTION__, rtw_get_passing_time_ms(start)); + return _FAIL; + } + else + { + u32 passing_time = rtw_get_passing_time_ms(start); + + if(passing_time > 100 || issue > 3) + DBG_871X("%s success, issue:%d, poll:%d, %u ms\n", __FUNCTION__, issue, poll, rtw_get_passing_time_ms(start)); + //else + // DBG_871X("%s success, issue:%d, poll:%d, %u ms\n", __FUNCTION__, issue, poll, rtw_get_passing_time_ms(start)); + + rtw_hal_fw_correct_bcn(padapter); + + return _SUCCESS; + } + +#endif + +} + +/**************************************************************************** + +Following are some utitity fuctions for WiFi MLME + +*****************************************************************************/ + +BOOLEAN IsLegal5GChannel( + IN PADAPTER Adapter, + IN u8 channel) +{ + + int i=0; + u8 Channel_5G[45] = {36,38,40,42,44,46,48,50,52,54,56,58, + 60,62,64,100,102,104,106,108,110,112,114,116,118,120,122, + 124,126,128,130,132,134,136,138,140,149,151,153,155,157,159, + 161,163,165}; + for(i=0;iu.hdr.rx_data; + u32 packet_len = precv_frame->u.hdr.len; + u8 ie_offset; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + len = packet_len - sizeof(struct rtw_ieee80211_hdr_3addr); + + if (len > MAX_IE_SZ) + { + //DBG_871X("IE too long for survey event\n"); + return _FAIL; + } + + _rtw_memset(bssid, 0, sizeof(WLAN_BSSID_EX)); + + subtype = GetFrameSubType(pframe); + + if(subtype==WIFI_BEACON) { + bssid->Reserved[0] = 1; + ie_offset = _BEACON_IE_OFFSET_; + } else { + // FIXME : more type + if (subtype == WIFI_PROBERSP) { + ie_offset = _PROBERSP_IE_OFFSET_; + bssid->Reserved[0] = 3; + } + else if (subtype == WIFI_PROBEREQ) { + ie_offset = _PROBEREQ_IE_OFFSET_; + bssid->Reserved[0] = 2; + } + else { + bssid->Reserved[0] = 0; + ie_offset = _FIXED_IE_LENGTH_; + } + } + + bssid->Length = sizeof(WLAN_BSSID_EX) - MAX_IE_SZ + len; + + //below is to copy the information element + bssid->IELength = len; + _rtw_memcpy(bssid->IEs, (pframe + sizeof(struct rtw_ieee80211_hdr_3addr)), bssid->IELength); + + //get the signal strength + //bssid->Rssi = precv_frame->u.hdr.attrib.SignalStrength; // 0-100 index. + bssid->Rssi = precv_frame->u.hdr.attrib.phy_info.RecvSignalPower; // in dBM.raw data + bssid->PhyInfo.SignalQuality = precv_frame->u.hdr.attrib.phy_info.SignalQuality;//in percentage + bssid->PhyInfo.SignalStrength = precv_frame->u.hdr.attrib.phy_info.SignalStrength;//in percentage +#ifdef CONFIG_ANTENNA_DIVERSITY + rtw_hal_get_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &(bssid->PhyInfo.Optimum_antenna), NULL); +#endif + + // checking SSID + if ((p = rtw_get_ie(bssid->IEs + ie_offset, _SSID_IE_, &len, bssid->IELength - ie_offset)) == NULL) + { + DBG_871X("marc: cannot find SSID for survey event\n"); + return _FAIL; + } + + if (*(p + 1)) + { + if (len > NDIS_802_11_LENGTH_SSID) + { + DBG_871X("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len); + return _FAIL; + } + _rtw_memcpy(bssid->Ssid.Ssid, (p + 2), *(p + 1)); + bssid->Ssid.SsidLength = *(p + 1); + } + else + { + bssid->Ssid.SsidLength = 0; + } + + _rtw_memset(bssid->SupportedRates, 0, NDIS_802_11_LENGTH_RATES_EX); + + //checking rate info... + i = 0; + p = rtw_get_ie(bssid->IEs + ie_offset, _SUPPORTEDRATES_IE_, &len, bssid->IELength - ie_offset); + if (p != NULL) + { + if (len > NDIS_802_11_LENGTH_RATES_EX) + { + DBG_871X("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len); + return _FAIL; + } + _rtw_memcpy(bssid->SupportedRates, (p + 2), len); + i = len; + } + + p = rtw_get_ie(bssid->IEs + ie_offset, _EXT_SUPPORTEDRATES_IE_, &len, bssid->IELength - ie_offset); + if (p != NULL) + { + if (len > (NDIS_802_11_LENGTH_RATES_EX-i)) + { + DBG_871X("%s()-%d: IE too long (%d) for survey event\n", __FUNCTION__, __LINE__, len); + return _FAIL; + } + _rtw_memcpy(bssid->SupportedRates + i, (p + 2), len); + } + + //todo: +#if 0 + if (judge_network_type(bssid->SupportedRates, (len + i)) == WIRELESS_11B) + { + bssid->NetworkTypeInUse = Ndis802_11DS; + } + else +#endif + { + bssid->NetworkTypeInUse = Ndis802_11OFDM24; + } + +#ifdef CONFIG_P2P + if (subtype == WIFI_PROBEREQ) + { + u8 *p2p_ie; + u32 p2p_ielen; + // Set Listion Channel + if ((p2p_ie = rtw_get_p2p_ie(bssid->IEs, bssid->IELength, NULL, &p2p_ielen))) + { + u32 attr_contentlen = 0; + u8 listen_ch[5] = { 0x00 }; + + rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, listen_ch, &attr_contentlen); + bssid->Configuration.DSConfig = listen_ch[4]; + } else + { // use current channel + bssid->Configuration.DSConfig = padapter->mlmeextpriv.cur_channel; + DBG_871X("%s()-%d: Cannot get p2p_ie. set DSconfig to op_ch(%d)\n", __FUNCTION__, __LINE__, bssid->Configuration.DSConfig); + } + + // FIXME + bssid->InfrastructureMode = Ndis802_11Infrastructure; + _rtw_memcpy(bssid->MacAddress, GetAddr2Ptr(pframe), ETH_ALEN); + bssid->Privacy = 1; + return _SUCCESS; + } +#endif //CONFIG_P2P + + if (bssid->IELength < 12) + return _FAIL; + + // Checking for DSConfig + p = rtw_get_ie(bssid->IEs + ie_offset, _DSSET_IE_, &len, bssid->IELength - ie_offset); + + bssid->Configuration.DSConfig = 0; + bssid->Configuration.Length = 0; + + if (p) + { + bssid->Configuration.DSConfig = *(p + 2); + } + else + {// In 5G, some ap do not have DSSET IE + // checking HT info for channel + p = rtw_get_ie(bssid->IEs + ie_offset, _HT_ADD_INFO_IE_, &len, bssid->IELength - ie_offset); + if(p) + { + struct HT_info_element *HT_info = (struct HT_info_element *)(p + 2); + bssid->Configuration.DSConfig = HT_info->primary_channel; + } + else + { // use current channel + bssid->Configuration.DSConfig = rtw_get_oper_ch(padapter); + } + } + + _rtw_memcpy(&bssid->Configuration.BeaconPeriod, rtw_get_beacon_interval_from_ie(bssid->IEs), 2); + bssid->Configuration.BeaconPeriod = le32_to_cpu(bssid->Configuration.BeaconPeriod); + + val16 = rtw_get_capability((WLAN_BSSID_EX *)bssid); + + if (val16 & BIT(0)) + { + bssid->InfrastructureMode = Ndis802_11Infrastructure; + _rtw_memcpy(bssid->MacAddress, GetAddr2Ptr(pframe), ETH_ALEN); + } + else + { + bssid->InfrastructureMode = Ndis802_11IBSS; + _rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN); + } + + if (val16 & BIT(4)) + bssid->Privacy = 1; + else + bssid->Privacy = 0; + + bssid->Configuration.ATIMWindow = 0; + + //20/40 BSS Coexistence check + if((pregistrypriv->wifi_spec==1) && (_FALSE == pmlmeinfo->bwmode_updated)) + { + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; +#ifdef CONFIG_80211N_HT + p = rtw_get_ie(bssid->IEs + ie_offset, _HT_CAPABILITY_IE_, &len, bssid->IELength - ie_offset); + if(p && len>0) + { + struct HT_caps_element *pHT_caps; + pHT_caps = (struct HT_caps_element *)(p + 2); + + if(pHT_caps->u.HT_cap_element.HT_caps_info&BIT(14)) + { + pmlmepriv->num_FortyMHzIntolerant++; + } + } + else + { + pmlmepriv->num_sta_no_ht++; + } +#endif //CONFIG_80211N_HT + + } + +#ifdef CONFIG_INTEL_WIDI + //process_intel_widi_query_or_tigger(padapter, bssid); + if(process_intel_widi_query_or_tigger(padapter, bssid)) + { + return _FAIL; + } +#endif // CONFIG_INTEL_WIDI + + #if defined(DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) & 1 + if(strcmp(bssid->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) { + DBG_871X("Receiving %s("MAC_FMT", DSConfig:%u) from ch%u with ss:%3u, sq:%3u, RawRSSI:%3ld\n" + , bssid->Ssid.Ssid, MAC_ARG(bssid->MacAddress), bssid->Configuration.DSConfig + , rtw_get_oper_ch(padapter) + , bssid->PhyInfo.SignalStrength, bssid->PhyInfo.SignalQuality, bssid->Rssi + ); + } + #endif + + // mark bss info receving from nearby channel as SignalQuality 101 + if(bssid->Configuration.DSConfig != rtw_get_oper_ch(padapter)) + { + bssid->PhyInfo.SignalQuality= 101; + } + + return _SUCCESS; +} + +void start_create_ibss(_adapter* padapter) +{ + unsigned short caps; + u8 val8; + u8 join_type; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network)); + u8 doiqk = _FALSE; + pmlmeext->cur_channel = (u8)pnetwork->Configuration.DSConfig; + pmlmeinfo->bcn_interval = get_beacon_interval(pnetwork); + + //update wireless mode + update_wireless_mode(padapter); + + //udpate capability + caps = rtw_get_capability((WLAN_BSSID_EX *)pnetwork); + update_capinfo(padapter, caps); + if(caps&cap_IBSS)//adhoc master + { + //set_opmode_cmd(padapter, adhoc);//removed + + val8 = 0xcf; + rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); + + doiqk = _TRUE; + rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); + + //switch channel + //SelectChannel(padapter, pmlmeext->cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE); + set_channel_bwmode(padapter, pmlmeext->cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + + doiqk = _FALSE; + rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); + + beacon_timing_control(padapter); + + //set msr to WIFI_FW_ADHOC_STATE + pmlmeinfo->state = WIFI_FW_ADHOC_STATE; + Set_MSR(padapter, (pmlmeinfo->state & 0x3)); + + //issue beacon + if(send_beacon(padapter)==_FAIL) + { + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("issuing beacon frame fail....\n")); + + report_join_res(padapter, -1); + pmlmeinfo->state = WIFI_FW_NULL_STATE; + } + else + { + rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress); + join_type = 0; + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); + + report_join_res(padapter, 1); + pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS; + rtw_indicate_connect(padapter); + } + } + else + { + DBG_871X("start_create_ibss, invalid cap:%x\n", caps); + return; + } + //update bc/mc sta_info + update_bmc_sta(padapter); + +} + +void start_clnt_join(_adapter* padapter) +{ + unsigned short caps; + u8 val8; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network)); + int beacon_timeout; + u8 ASIX_ID[]= {0x00, 0x0E, 0xC6}; + + //update wireless mode + update_wireless_mode(padapter); + + //udpate capability + caps = rtw_get_capability((WLAN_BSSID_EX *)pnetwork); + update_capinfo(padapter, caps); + + //check if sta is ASIX peer and fix IOT issue if it is. + if (_rtw_memcmp(get_my_bssid(&pmlmeinfo->network) ,ASIX_ID ,3)) { + u8 iot_flag = _TRUE; + rtw_hal_set_hwreg(padapter, HW_VAR_ASIX_IOT, (u8 *)(&iot_flag)); + } + + if (caps&cap_ESS) + { + Set_MSR(padapter, WIFI_FW_STATION_STATE); + + val8 = (pmlmeinfo->auth_algo == dot11AuthAlgrthm_8021X)? 0xcc: 0xcf; + +#ifdef CONFIG_WAPI_SUPPORT + if (padapter->wapiInfo.bWapiEnable && pmlmeinfo->auth_algo == dot11AuthAlgrthm_WAPI) + { + //Disable TxUseDefaultKey, RxUseDefaultKey, RxBroadcastUseDefaultKey. + val8 = 0x4c; + } +#endif + rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); + + #ifdef CONFIG_DEAUTH_BEFORE_CONNECT + // Because of AP's not receiving deauth before + // AP may: 1)not response auth or 2)deauth us after link is complete + // issue deauth before issuing auth to deal with the situation + + // Commented by Albert 2012/07/21 + // For the Win8 P2P connection, it will be hard to have a successful connection if this Wi-Fi doesn't connect to it. + { + #ifdef CONFIG_P2P + _queue *queue = &(padapter->mlmepriv.scanned_queue); + _list *head = get_list_head(queue); + _list *pos = get_next(head); + struct wlan_network *scanned = NULL; + u8 ie_offset = 0; + _irqL irqL; + bool has_p2p_ie = _FALSE; + + _enter_critical_bh(&(padapter->mlmepriv.scanned_queue.lock), &irqL); + + for (pos = get_next(head);!rtw_end_of_queue_search(head, pos); pos = get_next(pos)) { + + scanned = LIST_CONTAINOR(pos, struct wlan_network, list); + + if (_rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE + && _rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE + ) { + ie_offset = (scanned->network.Reserved[0] == 2? 0:12); + if (rtw_get_p2p_ie(scanned->network.IEs+ie_offset, scanned->network.IELength-ie_offset, NULL, NULL)) + has_p2p_ie = _TRUE; + break; + } + } + + _exit_critical_bh(&(padapter->mlmepriv.scanned_queue.lock), &irqL); + + if (scanned == NULL || rtw_end_of_queue_search(head, pos) || has_p2p_ie == _FALSE) + #endif /* CONFIG_P2P */ + //To avoid connecting to AP fail during resume process, change retry count from 5 to 1 + issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 1, 100); + } + #endif /* CONFIG_DEAUTH_BEFORE_CONNECT */ + + //here wait for receiving the beacon to start auth + //and enable a timer + beacon_timeout = decide_wait_for_beacon_timeout(pmlmeinfo->bcn_interval); + set_link_timer(pmlmeext, beacon_timeout); + _set_timer( &padapter->mlmepriv.assoc_timer, + (REAUTH_TO * REAUTH_LIMIT) + (REASSOC_TO*REASSOC_LIMIT) +beacon_timeout); + + pmlmeinfo->state = WIFI_FW_AUTH_NULL | WIFI_FW_STATION_STATE; + } + else if (caps&cap_IBSS) //adhoc client + { + Set_MSR(padapter, WIFI_FW_ADHOC_STATE); + + val8 = 0xcf; + rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); + + beacon_timing_control(padapter); + + pmlmeinfo->state = WIFI_FW_ADHOC_STATE; + + report_join_res(padapter, 1); + } + else + { + //DBG_871X("marc: invalid cap:%x\n", caps); + return; + } + +} + +void start_clnt_auth(_adapter* padapter) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + _cancel_timer_ex(&pmlmeext->link_timer); + + pmlmeinfo->state &= (~WIFI_FW_AUTH_NULL); + pmlmeinfo->state |= WIFI_FW_AUTH_STATE; + + pmlmeinfo->auth_seq = 1; + pmlmeinfo->reauth_count = 0; + pmlmeinfo->reassoc_count = 0; + pmlmeinfo->link_count = 0; + pmlmeext->retry = 0; + + + DBG_871X_LEVEL(_drv_always_, "start auth\n"); + issue_auth(padapter, NULL, 0); + + set_link_timer(pmlmeext, REAUTH_TO); + +} + + +void start_clnt_assoc(_adapter* padapter) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + _cancel_timer_ex(&pmlmeext->link_timer); + + pmlmeinfo->state &= (~(WIFI_FW_AUTH_NULL | WIFI_FW_AUTH_STATE)); + pmlmeinfo->state |= (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE); + + issue_assocreq(padapter); + + set_link_timer(pmlmeext, REASSOC_TO); +} + +unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, u8 locally_generated) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (!(_rtw_memcmp(MacAddr, get_my_bssid(&pmlmeinfo->network), ETH_ALEN))) + return _SUCCESS; + + DBG_871X("%s\n", __FUNCTION__); + + if((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE) + { + if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) { + if (report_del_sta_event(padapter, MacAddr, reason, _TRUE, locally_generated) != _FAIL) + pmlmeinfo->state = WIFI_FW_NULL_STATE; + } else if (pmlmeinfo->state & WIFI_FW_LINKING_STATE) { + if (report_join_res(padapter, -2) != _FAIL) + pmlmeinfo->state = WIFI_FW_NULL_STATE; + } else + DBG_871X(FUNC_ADPT_FMT" - End to Disconnect\n", FUNC_ADPT_ARG(padapter)); + } + + return _SUCCESS; +} + +#ifdef CONFIG_80211D +static void process_80211d(PADAPTER padapter, WLAN_BSSID_EX *bssid) +{ + struct registry_priv *pregistrypriv; + struct mlme_ext_priv *pmlmeext; + RT_CHANNEL_INFO *chplan_new; + u8 channel; + u8 i; + + + pregistrypriv = &padapter->registrypriv; + pmlmeext = &padapter->mlmeextpriv; + + // Adjust channel plan by AP Country IE + if (pregistrypriv->enable80211d && + (!pmlmeext->update_channel_plan_by_ap_done)) + { + u8 *ie, *p; + u32 len; + RT_CHANNEL_PLAN chplan_ap; + RT_CHANNEL_INFO chplan_sta[MAX_CHANNEL_NUM]; + u8 country[4]; + u8 fcn; // first channel number + u8 noc; // number of channel + u8 j, k; + + ie = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _COUNTRY_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_); + if (!ie) return; + if (len < 6) return; + + ie += 2; + p = ie; + ie += len; + + _rtw_memset(country, 0, 4); + _rtw_memcpy(country, p, 3); + p += 3; + RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, + ("%s: 802.11d country=%s\n", __FUNCTION__, country)); + + i = 0; + while ((ie - p) >= 3) + { + fcn = *(p++); + noc = *(p++); + p++; + + for (j = 0; j < noc; j++) + { + if (fcn <= 14) channel = fcn + j; // 2.4 GHz + else channel = fcn + j*4; // 5 GHz + + chplan_ap.Channel[i++] = channel; + } + } + chplan_ap.Len = i; + +#ifdef CONFIG_DEBUG_RTL871X + i = 0; + DBG_871X("%s: AP[%s] channel plan {", __FUNCTION__, bssid->Ssid.Ssid); + while ((i < chplan_ap.Len) && (chplan_ap.Channel[i] != 0)) + { + DBG_8192C("%02d,", chplan_ap.Channel[i]); + i++; + } + DBG_871X("}\n"); +#endif + + _rtw_memcpy(chplan_sta, pmlmeext->channel_set, sizeof(chplan_sta)); +#ifdef CONFIG_DEBUG_RTL871X + i = 0; + DBG_871X("%s: STA channel plan {", __FUNCTION__); + while ((i < MAX_CHANNEL_NUM) && (chplan_sta[i].ChannelNum != 0)) + { + DBG_871X("%02d(%c),", chplan_sta[i].ChannelNum, chplan_sta[i].ScanType==SCAN_PASSIVE?'p':'a'); + i++; + } + DBG_871X("}\n"); +#endif + + _rtw_memset(pmlmeext->channel_set, 0, sizeof(pmlmeext->channel_set)); + chplan_new = pmlmeext->channel_set; + + i = j = k = 0; + if (pregistrypriv->wireless_mode & WIRELESS_11G) + { + do { + if ((i == MAX_CHANNEL_NUM) || + (chplan_sta[i].ChannelNum == 0) || + (chplan_sta[i].ChannelNum > 14)) + break; + + if ((j == chplan_ap.Len) || (chplan_ap.Channel[j] > 14)) + break; + + if (chplan_sta[i].ChannelNum == chplan_ap.Channel[j]) + { + chplan_new[k].ChannelNum = chplan_ap.Channel[j]; + chplan_new[k].ScanType = SCAN_ACTIVE; + i++; + j++; + k++; + } + else if (chplan_sta[i].ChannelNum < chplan_ap.Channel[j]) + { + chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; +// chplan_new[k].ScanType = chplan_sta[i].ScanType; + chplan_new[k].ScanType = SCAN_PASSIVE; + i++; + k++; + } + else if (chplan_sta[i].ChannelNum > chplan_ap.Channel[j]) + { + chplan_new[k].ChannelNum = chplan_ap.Channel[j]; + chplan_new[k].ScanType = SCAN_ACTIVE; + j++; + k++; + } + } while (1); + + // change AP not support channel to Passive scan + while ((i < MAX_CHANNEL_NUM) && + (chplan_sta[i].ChannelNum != 0) && + (chplan_sta[i].ChannelNum <= 14)) + { + chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; +// chplan_new[k].ScanType = chplan_sta[i].ScanType; + chplan_new[k].ScanType = SCAN_PASSIVE; + i++; + k++; + } + + // add channel AP supported + while ((j < chplan_ap.Len) && (chplan_ap.Channel[j] <= 14)) + { + chplan_new[k].ChannelNum = chplan_ap.Channel[j]; + chplan_new[k].ScanType = SCAN_ACTIVE; + j++; + k++; + } + } + else + { + // keep original STA 2.4G channel plan + while ((i < MAX_CHANNEL_NUM) && + (chplan_sta[i].ChannelNum != 0) && + (chplan_sta[i].ChannelNum <= 14)) + { + chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; + chplan_new[k].ScanType = chplan_sta[i].ScanType; + i++; + k++; + } + + // skip AP 2.4G channel plan + while ((j < chplan_ap.Len) && (chplan_ap.Channel[j] <= 14)) + { + j++; + } + } + + if (pregistrypriv->wireless_mode & WIRELESS_11A) + { + do { + if ((i >= MAX_CHANNEL_NUM) || + (chplan_sta[i].ChannelNum == 0)) + break; + + if ((j == chplan_ap.Len) || (chplan_ap.Channel[j] == 0)) + break; + + if (chplan_sta[i].ChannelNum == chplan_ap.Channel[j]) + { + chplan_new[k].ChannelNum = chplan_ap.Channel[j]; + chplan_new[k].ScanType = SCAN_ACTIVE; + i++; + j++; + k++; + } + else if (chplan_sta[i].ChannelNum < chplan_ap.Channel[j]) + { + chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; +// chplan_new[k].ScanType = chplan_sta[i].ScanType; + chplan_new[k].ScanType = SCAN_PASSIVE; + i++; + k++; + } + else if (chplan_sta[i].ChannelNum > chplan_ap.Channel[j]) + { + chplan_new[k].ChannelNum = chplan_ap.Channel[j]; + chplan_new[k].ScanType = SCAN_ACTIVE; + j++; + k++; + } + } while (1); + + // change AP not support channel to Passive scan + while ((i < MAX_CHANNEL_NUM) && (chplan_sta[i].ChannelNum != 0)) + { + chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; +// chplan_new[k].ScanType = chplan_sta[i].ScanType; + chplan_new[k].ScanType = SCAN_PASSIVE; + i++; + k++; + } + + // add channel AP supported + while ((j < chplan_ap.Len) && (chplan_ap.Channel[j] != 0)) + { + chplan_new[k].ChannelNum = chplan_ap.Channel[j]; + chplan_new[k].ScanType = SCAN_ACTIVE; + j++; + k++; + } + } + else + { + // keep original STA 5G channel plan + while ((i < MAX_CHANNEL_NUM) && (chplan_sta[i].ChannelNum != 0)) + { + chplan_new[k].ChannelNum = chplan_sta[i].ChannelNum; + chplan_new[k].ScanType = chplan_sta[i].ScanType; + i++; + k++; + } + } + + pmlmeext->update_channel_plan_by_ap_done = 1; + +#ifdef CONFIG_DEBUG_RTL871X + k = 0; + DBG_871X("%s: new STA channel plan {", __FUNCTION__); + while ((k < MAX_CHANNEL_NUM) && (chplan_new[k].ChannelNum != 0)) + { + DBG_871X("%02d(%c),", chplan_new[k].ChannelNum, chplan_new[k].ScanType==SCAN_PASSIVE?'p':'c'); + k++; + } + DBG_871X("}\n"); +#endif + +#if 0 + // recover the right channel index + channel = chplan_sta[pmlmeext->sitesurvey_res.channel_idx].ChannelNum; + k = 0; + while ((k < MAX_CHANNEL_NUM) && (chplan_new[k].ChannelNum != 0)) + { + if (chplan_new[k].ChannelNum == channel) { + RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, + ("%s: change mlme_ext sitesurvey channel index from %d to %d\n", + __FUNCTION__, pmlmeext->sitesurvey_res.channel_idx, k)); + pmlmeext->sitesurvey_res.channel_idx = k; + break; + } + k++; + } +#endif + } + + // If channel is used by AP, set channel scan type to active + channel = bssid->Configuration.DSConfig; + chplan_new = pmlmeext->channel_set; + i = 0; + while ((i < MAX_CHANNEL_NUM) && (chplan_new[i].ChannelNum != 0)) + { + if (chplan_new[i].ChannelNum == channel) + { + if (chplan_new[i].ScanType == SCAN_PASSIVE) + { + //5G Bnad 2, 3 (DFS) doesn't change to active scan + if(channel >= 52 && channel <= 144) + break; + + chplan_new[i].ScanType = SCAN_ACTIVE; + RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, + ("%s: change channel %d scan type from passive to active\n", + __FUNCTION__, channel)); + } + break; + } + i++; + } +} +#endif + +/**************************************************************************** + +Following are the functions to report events + +*****************************************************************************/ + +void report_survey_event(_adapter *padapter, union recv_frame *precv_frame) +{ + struct cmd_obj *pcmd_obj; + u8 *pevtcmd; + u32 cmdsz; + struct survey_event *psurvey_evt; + struct C2HEvent_Header *pc2h_evt_hdr; + struct mlme_ext_priv *pmlmeext; + struct cmd_priv *pcmdpriv; + //u8 *pframe = precv_frame->u.hdr.rx_data; + //uint len = precv_frame->u.hdr.len; + + if(!padapter) + return; + + pmlmeext = &padapter->mlmeextpriv; + pcmdpriv = &padapter->cmdpriv; + + + if ((pcmd_obj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL) + { + return; + } + + cmdsz = (sizeof(struct survey_event) + sizeof(struct C2HEvent_Header)); + if ((pevtcmd = (u8*)rtw_zmalloc(cmdsz)) == NULL) + { + rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); + return; + } + + _rtw_init_listhead(&pcmd_obj->list); + + pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT); + pcmd_obj->cmdsz = cmdsz; + pcmd_obj->parmbuf = pevtcmd; + + pcmd_obj->rsp = NULL; + pcmd_obj->rspsz = 0; + + pc2h_evt_hdr = (struct C2HEvent_Header*)(pevtcmd); + pc2h_evt_hdr->len = sizeof(struct survey_event); + pc2h_evt_hdr->ID = GEN_EVT_CODE(_Survey); + pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); + + psurvey_evt = (struct survey_event*)(pevtcmd + sizeof(struct C2HEvent_Header)); + + if (collect_bss_info(padapter, precv_frame, (WLAN_BSSID_EX *)&psurvey_evt->bss) == _FAIL) + { + rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); + rtw_mfree((u8 *)pevtcmd, cmdsz); + return; + } + +#ifdef CONFIG_80211D + process_80211d(padapter, &psurvey_evt->bss); +#endif + + rtw_enqueue_cmd(pcmdpriv, pcmd_obj); + + pmlmeext->sitesurvey_res.bss_cnt++; + + return; + +} + +void report_surveydone_event(_adapter *padapter) +{ + struct cmd_obj *pcmd_obj; + u8 *pevtcmd; + u32 cmdsz; + struct surveydone_event *psurveydone_evt; + struct C2HEvent_Header *pc2h_evt_hdr; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + + if ((pcmd_obj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL) + { + return; + } + + cmdsz = (sizeof(struct surveydone_event) + sizeof(struct C2HEvent_Header)); + if ((pevtcmd = (u8*)rtw_zmalloc(cmdsz)) == NULL) + { + rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); + return; + } + + _rtw_init_listhead(&pcmd_obj->list); + + pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT); + pcmd_obj->cmdsz = cmdsz; + pcmd_obj->parmbuf = pevtcmd; + + pcmd_obj->rsp = NULL; + pcmd_obj->rspsz = 0; + + pc2h_evt_hdr = (struct C2HEvent_Header*)(pevtcmd); + pc2h_evt_hdr->len = sizeof(struct surveydone_event); + pc2h_evt_hdr->ID = GEN_EVT_CODE(_SurveyDone); + pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); + + psurveydone_evt = (struct surveydone_event*)(pevtcmd + sizeof(struct C2HEvent_Header)); + psurveydone_evt->bss_cnt = pmlmeext->sitesurvey_res.bss_cnt; + + DBG_871X("survey done event(%x) band:%d for "ADPT_FMT"\n", psurveydone_evt->bss_cnt, padapter->setband, ADPT_ARG(padapter)); + + rtw_enqueue_cmd(pcmdpriv, pcmd_obj); + + return; + +} + +u32 report_join_res(_adapter *padapter, int res) +{ + struct cmd_obj *pcmd_obj; + u8 *pevtcmd; + u32 cmdsz; + struct joinbss_event *pjoinbss_evt; + struct C2HEvent_Header *pc2h_evt_hdr; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u32 ret = _FAIL; + + if ((pcmd_obj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL) + goto exit; + + cmdsz = (sizeof(struct joinbss_event) + sizeof(struct C2HEvent_Header)); + pevtcmd = (u8 *)rtw_zmalloc(cmdsz); + if (pevtcmd == NULL) { + rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); + goto exit; + } + + _rtw_init_listhead(&pcmd_obj->list); + + pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT); + pcmd_obj->cmdsz = cmdsz; + pcmd_obj->parmbuf = pevtcmd; + + pcmd_obj->rsp = NULL; + pcmd_obj->rspsz = 0; + + pc2h_evt_hdr = (struct C2HEvent_Header*)(pevtcmd); + pc2h_evt_hdr->len = sizeof(struct joinbss_event); + pc2h_evt_hdr->ID = GEN_EVT_CODE(_JoinBss); + pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); + + pjoinbss_evt = (struct joinbss_event*)(pevtcmd + sizeof(struct C2HEvent_Header)); + _rtw_memcpy((unsigned char *)(&(pjoinbss_evt->network.network)), &(pmlmeinfo->network), sizeof(WLAN_BSSID_EX)); + pjoinbss_evt->network.join_res = pjoinbss_evt->network.aid = res; + + DBG_871X("report_join_res(%d)\n", res); + + + rtw_joinbss_event_prehandle(padapter, (u8 *)&pjoinbss_evt->network); + + + ret = rtw_enqueue_cmd(pcmdpriv, pcmd_obj); + +exit: + return ret; +} + +void report_wmm_edca_update(_adapter *padapter) +{ + struct cmd_obj *pcmd_obj; + u8 *pevtcmd; + u32 cmdsz; + struct wmm_event *pwmm_event; + struct C2HEvent_Header *pc2h_evt_hdr; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + + if ((pcmd_obj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL) + { + return; + } + + cmdsz = (sizeof(struct wmm_event) + sizeof(struct C2HEvent_Header)); + if ((pevtcmd = (u8*)rtw_zmalloc(cmdsz)) == NULL) + { + rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); + return; + } + + _rtw_init_listhead(&pcmd_obj->list); + + pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT); + pcmd_obj->cmdsz = cmdsz; + pcmd_obj->parmbuf = pevtcmd; + + pcmd_obj->rsp = NULL; + pcmd_obj->rspsz = 0; + + pc2h_evt_hdr = (struct C2HEvent_Header*)(pevtcmd); + pc2h_evt_hdr->len = sizeof(struct wmm_event); + pc2h_evt_hdr->ID = GEN_EVT_CODE(_WMM); + pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); + + pwmm_event = (struct wmm_event*)(pevtcmd + sizeof(struct C2HEvent_Header)); + pwmm_event->wmm =0; + + rtw_enqueue_cmd(pcmdpriv, pcmd_obj); + + return; + +} + +u32 report_del_sta_event(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, bool enqueue, u8 locally_generated) +{ + struct cmd_obj *pcmd_obj; + u8 *pevtcmd; + u32 cmdsz; + struct sta_info *psta; + int mac_id = -1; + struct stadel_event *pdel_sta_evt; + struct C2HEvent_Header *pc2h_evt_hdr; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; + + /* prepare cmd parameter */ + cmdsz = (sizeof(struct stadel_event) + sizeof(struct C2HEvent_Header)); + pevtcmd = (u8 *)rtw_zmalloc(cmdsz); + if (pevtcmd == NULL) { + res = _FAIL; + goto exit; + } + + pc2h_evt_hdr = (struct C2HEvent_Header*)(pevtcmd); + pc2h_evt_hdr->len = sizeof(struct stadel_event); + pc2h_evt_hdr->ID = GEN_EVT_CODE(_DelSTA); + pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); + + pdel_sta_evt = (struct stadel_event*)(pevtcmd + sizeof(struct C2HEvent_Header)); + _rtw_memcpy((unsigned char *)(&(pdel_sta_evt->macaddr)), MacAddr, ETH_ALEN); + _rtw_memcpy((unsigned char *)(pdel_sta_evt->rsvd),(unsigned char *)(&reason),2); + psta = rtw_get_stainfo(&padapter->stapriv, MacAddr); + if(psta) + mac_id = (int)psta->mac_id; + else + mac_id = (-1); + pdel_sta_evt->mac_id = mac_id; + pdel_sta_evt->locally_generated = locally_generated; + + if (!enqueue) { + /* do directly */ + rtw_stadel_event_callback(padapter, (u8 *)pdel_sta_evt); + rtw_mfree(pevtcmd, cmdsz); + } else { + pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (pcmd_obj == NULL) { + rtw_mfree(pevtcmd, cmdsz); + res = _FAIL; + goto exit; + } + + _rtw_init_listhead(&pcmd_obj->list); + pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT); + pcmd_obj->cmdsz = cmdsz; + pcmd_obj->parmbuf = pevtcmd; + + pcmd_obj->rsp = NULL; + pcmd_obj->rspsz = 0; + + res = rtw_enqueue_cmd(pcmdpriv, pcmd_obj); + } + +exit: + + DBG_871X(FUNC_ADPT_FMT" "MAC_FMT" mac_id=%d, enqueue:%d, res:%u\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(MacAddr), mac_id, enqueue, res); + + return res; +} + +void report_add_sta_event(_adapter *padapter, unsigned char *MacAddr) +{ + struct cmd_obj *pcmd_obj; + u8 *pevtcmd; + u32 cmdsz; + struct stassoc_event *padd_sta_evt; + struct C2HEvent_Header *pc2h_evt_hdr; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + + if ((pcmd_obj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL) + { + return; + } + + cmdsz = (sizeof(struct stassoc_event) + sizeof(struct C2HEvent_Header)); + if ((pevtcmd = (u8*)rtw_zmalloc(cmdsz)) == NULL) + { + rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); + return; + } + + _rtw_init_listhead(&pcmd_obj->list); + + pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT); + pcmd_obj->cmdsz = cmdsz; + pcmd_obj->parmbuf = pevtcmd; + + pcmd_obj->rsp = NULL; + pcmd_obj->rspsz = 0; + + pc2h_evt_hdr = (struct C2HEvent_Header*)(pevtcmd); + pc2h_evt_hdr->len = sizeof(struct stassoc_event); + pc2h_evt_hdr->ID = GEN_EVT_CODE(_AddSTA); + pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); + + padd_sta_evt = (struct stassoc_event*)(pevtcmd + sizeof(struct C2HEvent_Header)); + _rtw_memcpy((unsigned char *)(&(padd_sta_evt->macaddr)), MacAddr, ETH_ALEN); + + DBG_871X("report_add_sta_event: add STA\n"); + + rtw_enqueue_cmd(pcmdpriv, pcmd_obj); + + return; +} + + +bool rtw_port_switch_chk(_adapter *adapter) +{ + bool switch_needed = _FALSE; +#ifdef CONFIG_CONCURRENT_MODE +#ifdef CONFIG_RUNTIME_PORT_SWITCH + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct pwrctrl_priv *pwrctl = dvobj_to_pwrctl(dvobj); + _adapter *if_port0 = NULL; + _adapter *if_port1 = NULL; + struct mlme_ext_info *if_port0_mlmeinfo = NULL; + struct mlme_ext_info *if_port1_mlmeinfo = NULL; + int i; + + for (i = 0; i < dvobj->iface_nums; i++) { + if (get_iface_type(dvobj->padapters[i]) == IFACE_PORT0) { + if_port0 = dvobj->padapters[i]; + if_port0_mlmeinfo = &(if_port0->mlmeextpriv.mlmext_info); + } + else if (get_iface_type(dvobj->padapters[i]) == IFACE_PORT1) { + if_port1 = dvobj->padapters[i]; + if_port1_mlmeinfo = &(if_port1->mlmeextpriv.mlmext_info); + } + } + + if (if_port0 == NULL) { + rtw_warn_on(1); + goto exit; + } + + if (if_port1 == NULL) { + rtw_warn_on(1); + goto exit; + } + +#ifdef DBG_RUNTIME_PORT_SWITCH + DBG_871X(FUNC_ADPT_FMT" wowlan_mode:%u\n" + ADPT_FMT", port0, mlmeinfo->state:0x%08x, p2p_state:%d, %d\n" + ADPT_FMT", port1, mlmeinfo->state:0x%08x, p2p_state:%d, %d\n", + FUNC_ADPT_ARG(adapter), pwrctl->wowlan_mode, + ADPT_ARG(if_port0), if_port0_mlmeinfo->state, rtw_p2p_state(&if_port0->wdinfo), rtw_p2p_chk_state(&if_port0->wdinfo, P2P_STATE_NONE), + ADPT_ARG(if_port1), if_port1_mlmeinfo->state, rtw_p2p_state(&if_port1->wdinfo), rtw_p2p_chk_state(&if_port1->wdinfo, P2P_STATE_NONE)); +#endif /* DBG_RUNTIME_PORT_SWITCH */ + + + /* AP should use port0 for ctl frame's ack */ + if ((if_port1_mlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { + DBG_871X("%s "ADPT_FMT" is AP/GO\n", __func__, ADPT_ARG(if_port1)); + switch_needed = _TRUE; + goto exit; + } + + /* GC should use port0 for p2p ps */ + if (((if_port1_mlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE) + && (if_port1_mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) + && !rtw_p2p_chk_state(&if_port1->wdinfo, P2P_STATE_NONE) + && !check_fwstate(&if_port1->mlmepriv, WIFI_UNDER_WPS) + ) { + DBG_871X("%s "ADPT_FMT" is GC\n", __func__, ADPT_ARG(if_port1)); + switch_needed = _TRUE; + goto exit; + } + + /* port1 linked, but port0 not linked */ + if ((if_port1_mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) + && !(if_port0_mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) + && ((if_port0_mlmeinfo->state & 0x03) != WIFI_FW_AP_STATE) + ) { + DBG_871X("%s "ADPT_FMT" is SINGLE_LINK\n", __func__, ADPT_ARG(if_port1)); + switch_needed = _TRUE; + goto exit; + } + +exit: +#ifdef DBG_RUNTIME_PORT_SWITCH + DBG_871X(FUNC_ADPT_FMT" ret:%d\n", FUNC_ADPT_ARG(adapter), switch_needed); +#endif /* DBG_RUNTIME_PORT_SWITCH */ +#endif /* CONFIG_RUNTIME_PORT_SWITCH */ +#endif /* CONFIG_CONCURRENT_MODE */ + return switch_needed; +} + +/**************************************************************************** + +Following are the event callback functions + +*****************************************************************************/ + +//for sta/adhoc mode +void update_sta_info(_adapter *padapter, struct sta_info *psta) +{ + _irqL irqL; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + //ERP + VCS_update(padapter, psta); + +#ifdef CONFIG_80211N_HT + //HT + if(pmlmepriv->htpriv.ht_option) + { + psta->htpriv.ht_option = _TRUE; + + psta->htpriv.ampdu_enable = pmlmepriv->htpriv.ampdu_enable; + + psta->htpriv.rx_ampdu_min_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para&IEEE80211_HT_CAP_AMPDU_DENSITY)>>2; + + if (support_short_GI(padapter, &(pmlmeinfo->HT_caps), CHANNEL_WIDTH_20)) + psta->htpriv.sgi_20m = _TRUE; + + if (support_short_GI(padapter, &(pmlmeinfo->HT_caps), CHANNEL_WIDTH_40)) + psta->htpriv.sgi_40m = _TRUE; + + psta->qos_option = _TRUE; + + psta->htpriv.ldpc_cap = pmlmepriv->htpriv.ldpc_cap; + psta->htpriv.stbc_cap = pmlmepriv->htpriv.stbc_cap; + psta->htpriv.beamform_cap = pmlmepriv->htpriv.beamform_cap; + + _rtw_memcpy(&psta->htpriv.ht_cap, &pmlmeinfo->HT_caps, sizeof(struct rtw_ieee80211_ht_cap)); + } + else +#endif //CONFIG_80211N_HT + { +#ifdef CONFIG_80211N_HT + psta->htpriv.ht_option = _FALSE; + + psta->htpriv.ampdu_enable = _FALSE; + + psta->htpriv.sgi_20m = _FALSE; + psta->htpriv.sgi_40m = _FALSE; +#endif //CONFIG_80211N_HT + psta->qos_option = _FALSE; + + } + +#ifdef CONFIG_80211N_HT + psta->htpriv.ch_offset = pmlmeext->cur_ch_offset; + + psta->htpriv.agg_enable_bitmap = 0x0;//reset + psta->htpriv.candidate_tid_bitmap = 0x0;//reset +#endif //CONFIG_80211N_HT + + psta->bw_mode = pmlmeext->cur_bwmode; + + //QoS + if(pmlmepriv->qospriv.qos_option) + psta->qos_option = _TRUE; + +#ifdef CONFIG_80211AC_VHT + _rtw_memcpy(&psta->vhtpriv, &pmlmepriv->vhtpriv, sizeof(struct vht_priv)); +#endif //CONFIG_80211AC_VHT + + update_ldpc_stbc_cap(psta); + + _enter_critical_bh(&psta->lock, &irqL); + psta->state = _FW_LINKED; + _exit_critical_bh(&psta->lock, &irqL); + +} + +static void rtw_mlmeext_disconnect(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network)); + u8 state_backup = (pmlmeinfo->state&0x03); + u8 ASIX_ID[]= {0x00, 0x0E, 0xC6}; + + //set_opmode_cmd(padapter, infra_client_with_mlme); + + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_DISCONNECT, 0); + rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, null_addr); + + //set MSR to no link state -> infra. mode + Set_MSR(padapter, _HW_STATE_STATION_); + + //check if sta is ASIX peer and fix IOT issue if it is. + if (_rtw_memcmp(get_my_bssid(&pmlmeinfo->network) ,ASIX_ID ,3)) { + u8 iot_flag = _FALSE; + rtw_hal_set_hwreg(padapter, HW_VAR_ASIX_IOT, (u8 *)(&iot_flag)); + } + pmlmeinfo->state = WIFI_FW_NULL_STATE; + + if(state_backup == WIFI_FW_STATION_STATE) + { + if (rtw_port_switch_chk(padapter) == _TRUE) { + rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL); + #ifdef CONFIG_LPS + { + _adapter *port0_iface = dvobj_get_port0_adapter(adapter_to_dvobj(padapter)); + if (port0_iface) + rtw_lps_ctrl_wk_cmd(port0_iface, LPS_CTRL_CONNECT, 0); + } + #endif + } + } + + /* switch to the 20M Hz mode after disconnect */ + pmlmeext->cur_bwmode = CHANNEL_WIDTH_20; + pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + +#ifdef CONFIG_FCS_MODE + if (EN_FCS(padapter)) + rtw_hal_set_hwreg(padapter, HW_VAR_STOP_FCS_MODE, NULL); +#endif + +#ifdef CONFIG_DFS_MASTER + if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) + rtw_dfs_master_status_apply(padapter, MLME_AP_STOPPED); + else if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) + rtw_dfs_master_status_apply(padapter, MLME_STA_DISCONNECTED); +#endif + + { + u8 ch, bw, offset; + + if (rtw_get_ch_setting_union_no_self(padapter, &ch, &bw, &offset) != 0) + set_channel_bwmode(padapter, ch, offset, bw); + } + + flush_all_cam_entry(padapter); + + _cancel_timer_ex(&pmlmeext->link_timer); + + //pmlmepriv->LinkDetectInfo.TrafficBusyState = _FALSE; + pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0; + pmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0; + +#ifdef CONFIG_TDLS + padapter->tdlsinfo.ap_prohibited = _FALSE; + + /* For TDLS channel switch, currently we only allow it to work in wifi logo test mode */ + if (padapter->registrypriv.wifi_spec == 1) + { + padapter->tdlsinfo.ch_switch_prohibited = _FALSE; + } +#endif /* CONFIG_TDLS */ + +} + +void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res) +{ + struct sta_info *psta, *psta_bmc; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + struct sta_priv *pstapriv = &padapter->stapriv; + u8 join_type; +#ifdef CONFIG_ARP_KEEP_ALIVE + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; +#endif + struct security_priv *psecuritypriv = &padapter->securitypriv; + + if(join_res < 0) + { + join_type = 1; + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); + rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, null_addr); + + goto exit_mlmeext_joinbss_event_callback; + } +#ifdef CONFIG_ARP_KEEP_ALIVE + pmlmepriv->bGetGateway = 1; +#endif + + if((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) + { + //update bc/mc sta_info + update_bmc_sta(padapter); + } + + + //turn on dynamic functions + /* Switch_DM_Func(padapter, DYNAMIC_ALL_FUNC_ENABLE, _TRUE); */ + + // update IOT-releated issue + update_IOT_info(padapter); + + rtw_hal_set_hwreg(padapter, HW_VAR_BASIC_RATE, cur_network->SupportedRates); + + //BCN interval + rtw_hal_set_hwreg(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&pmlmeinfo->bcn_interval)); + + //udpate capability + update_capinfo(padapter, pmlmeinfo->capability); + + //WMM, Update EDCA param + WMMOnAssocRsp(padapter); + + //HT + HTOnAssocRsp(padapter); + +#ifdef CONFIG_80211AC_VHT + //VHT + VHTOnAssocRsp(padapter); +#endif + + psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress); + if (psta) //only for infra. mode + { + //DBG_871X("set_sta_rate\n"); + + psta->wireless_mode = pmlmeext->cur_wireless_mode; + + //set per sta rate after updating HT cap. + set_sta_rate(padapter, psta); + + rtw_sta_media_status_rpt(padapter, psta, 1); + + /* wakeup macid after join bss successfully to ensure + the subsequent data frames can be sent out normally */ + rtw_hal_macid_wakeup(padapter, psta->mac_id); + } + +#ifndef CONFIG_IOCTL_CFG80211 + if (is_wep_enc(psecuritypriv->dot11PrivacyAlgrthm)) + rtw_sec_restore_wep_key(padapter); +#endif /* CONFIG_IOCTL_CFG80211 */ + + if (rtw_port_switch_chk(padapter) == _TRUE) + rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL); + + join_type = 2; + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); + + if((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE) + { + // correcting TSF + correct_TSF(padapter, pmlmeext); + + //set_link_timer(pmlmeext, DISCONNECT_TO); + } + +#ifdef CONFIG_LPS + if(get_iface_type(padapter) == IFACE_PORT0) + rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_CONNECT, 0); +#endif + +#ifdef CONFIG_BEAMFORMING + if (psta) + beamforming_wk_cmd(padapter, BEAMFORMING_CTRL_ENTER, (u8 *)psta, sizeof(struct sta_info), 0); +#endif/*CONFIG_BEAMFORMING*/ + +exit_mlmeext_joinbss_event_callback: + + rtw_join_done_chk_ch(padapter, join_res); + + DBG_871X("=>%s - End to Connection without 4-way\n", __FUNCTION__); +} + +//currently only adhoc mode will go here +void mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta) +{ + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 join_type; + + DBG_871X("%s\n", __FUNCTION__); + + if((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) + { + if(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)//adhoc master or sta_count>1 + { + //nothing to do + } + else//adhoc client + { + //update TSF Value + //update_TSF(pmlmeext, pframe, len); + + // correcting TSF + correct_TSF(padapter, pmlmeext); + + //start beacon + if (send_beacon(padapter) == _FAIL) + rtw_warn_on(1); + + pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS; + } + + join_type = 2; + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); + } + + //update adhoc sta_info + update_sta_info(padapter, psta); + + rtw_hal_update_sta_rate_mask(padapter, psta); + + // ToDo: HT for Ad-hoc + psta->wireless_mode = rtw_check_network_type(psta->bssrateset, psta->bssratelen, pmlmeext->cur_channel); + psta->raid = rtw_hal_networktype_to_raid(padapter, psta); + + //rate radaptive + Update_RA_Entry(padapter, psta); +} + +void mlmeext_sta_del_event_callback(_adapter *padapter) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (is_client_associated_to_ap(padapter) || is_IBSS_empty(padapter)) + { + rtw_mlmeext_disconnect(padapter); + } + +} + +/**************************************************************************** + +Following are the functions for the timer handlers + +*****************************************************************************/ +void _linked_info_dump(_adapter *padapter) +{ + int i; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + HAL_DATA_TYPE *HalData = GET_HAL_DATA(padapter); + int UndecoratedSmoothedPWDB = 0; + + if(padapter->bLinkInfoDump){ + + DBG_871X("\n============["ADPT_FMT"] linked status check ===================\n",ADPT_ARG(padapter)); + + if((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE) + { + rtw_hal_get_def_var(padapter, HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, &UndecoratedSmoothedPWDB); + + DBG_871X("AP[" MAC_FMT "] - UndecoratedSmoothedPWDB:%d\n", + MAC_ARG(padapter->mlmepriv.cur_network.network.MacAddress),UndecoratedSmoothedPWDB); + } + else if((pmlmeinfo->state&0x03) == _HW_STATE_AP_) + { + _irqL irqL; + _list *phead, *plist; + + struct sta_info *psta=NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + phead = &pstapriv->asoc_list; + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) + { + psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + plist = get_next(plist); + + DBG_871X("STA[" MAC_FMT "]:UndecoratedSmoothedPWDB:%d\n", + MAC_ARG(psta->hwaddr),psta->rssi_stat.UndecoratedSmoothedPWDB); + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + } + + /*============ tx info ============ */ + rtw_hal_get_def_var(padapter, HW_DEF_RA_INFO_DUMP, RTW_DBGDUMP); + + rtw_hal_set_odm_var(padapter, HAL_ODM_RX_INFO_DUMP, RTW_DBGDUMP, _FALSE); + + } + + +} +void rtw_delba_check(_adapter *padapter, struct sta_info *psta, u8 from_timer) +{ + int i = 0; + int ret = _SUCCESS; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + /* + IOT issue,occur Broadcom ap(Buffalo WZR-D1800H,Netgear R6300). + AP is originator.AP does not transmit unicast packets when STA response its BAR. + This case probably occur ap issue BAR after AP builds BA. + + Follow 802.11 spec, STA shall maintain an inactivity timer for every negotiated Block Ack setup. + The inactivity timer is not reset when MPDUs corresponding to other TIDs are received. + */ + if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) { + for (i = 0; i < TID_NUM ; i++) { + if (sta_rx_data_qos_pkts(psta, i) == sta_last_rx_data_qos_pkts(psta, i)) { + if (_TRUE == rtw_inc_and_chk_continual_no_rx_packet(psta, i)) { + if (psta->recvreorder_ctrl[i].enable) { + /* send a DELBA frame to the peer STA with the Reason Code field set to TIMEOUT */ + if (!from_timer) + ret = issue_del_ba_ex(padapter, psta->hwaddr, i, 39, 0, 3, 1); + else + issue_del_ba(padapter, psta->hwaddr, i, 39, 0); + psta->recvreorder_ctrl[i].enable = _FALSE; + if (ret != _FAIL) + psta->recvreorder_ctrl[i].ampdu_size = RX_AMPDU_SIZE_INVALID; + rtw_reset_continual_no_rx_packet(psta, i); + } + } + } + else{ + /* The inactivity timer is reset when MPDUs to the TID is received. */ + rtw_reset_continual_no_rx_packet(psta, i); + } + } + } +} + +u8 chk_ap_is_alive(_adapter *padapter, struct sta_info *psta) +{ + u8 ret = _FALSE; + int i = 0; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + #ifdef DBG_EXPIRATION_CHK + DBG_871X(FUNC_ADPT_FMT" rx:"STA_PKTS_FMT", beacon:%llu, probersp_to_self:%llu" + /*", probersp_bm:%llu, probersp_uo:%llu, probereq:%llu, BI:%u"*/ + ", retry:%u\n" + , FUNC_ADPT_ARG(padapter) + , STA_RX_PKTS_DIFF_ARG(psta) + , psta->sta_stats.rx_beacon_pkts - psta->sta_stats.last_rx_beacon_pkts + , psta->sta_stats.rx_probersp_pkts - psta->sta_stats.last_rx_probersp_pkts + /*, psta->sta_stats.rx_probersp_bm_pkts - psta->sta_stats.last_rx_probersp_bm_pkts + , psta->sta_stats.rx_probersp_uo_pkts - psta->sta_stats.last_rx_probersp_uo_pkts + , psta->sta_stats.rx_probereq_pkts - psta->sta_stats.last_rx_probereq_pkts + , pmlmeinfo->bcn_interval*/ + , pmlmeext->retry + ); + + DBG_871X(FUNC_ADPT_FMT" tx_pkts:%llu, link_count:%u\n", FUNC_ADPT_ARG(padapter) + , padapter->xmitpriv.tx_pkts + , pmlmeinfo->link_count + ); + #endif + + if((sta_rx_data_pkts(psta) == sta_last_rx_data_pkts(psta)) + && sta_rx_beacon_pkts(psta) == sta_last_rx_beacon_pkts(psta) + && sta_rx_probersp_pkts(psta) == sta_last_rx_probersp_pkts(psta) + ) + { + ret = _FALSE; + } + else + { + ret = _TRUE; + } + + sta_update_last_rx_pkts(psta); + + /* + record last rx data packets for every tid. + */ + for (i = 0; i < TID_NUM; i++) + psta->sta_stats.last_rx_data_qos_pkts[i] = psta->sta_stats.rx_data_qos_pkts[i]; + + return ret; +} + +u8 chk_adhoc_peer_is_alive(struct sta_info *psta) +{ + u8 ret = _TRUE; + + #ifdef DBG_EXPIRATION_CHK + DBG_871X("sta:"MAC_FMT", rssi:%d, rx:"STA_PKTS_FMT", beacon:%llu, probersp_to_self:%llu" + /*", probersp_bm:%llu, probersp_uo:%llu, probereq:%llu, BI:%u"*/ + ", expire_to:%u\n" + , MAC_ARG(psta->hwaddr) + , psta->rssi_stat.UndecoratedSmoothedPWDB + , STA_RX_PKTS_DIFF_ARG(psta) + , psta->sta_stats.rx_beacon_pkts - psta->sta_stats.last_rx_beacon_pkts + , psta->sta_stats.rx_probersp_pkts - psta->sta_stats.last_rx_probersp_pkts + /*, psta->sta_stats.rx_probersp_bm_pkts - psta->sta_stats.last_rx_probersp_bm_pkts + , psta->sta_stats.rx_probersp_uo_pkts - psta->sta_stats.last_rx_probersp_uo_pkts + , psta->sta_stats.rx_probereq_pkts - psta->sta_stats.last_rx_probereq_pkts + , pmlmeinfo->bcn_interval*/ + , psta->expire_to + ); + #endif + + if (sta_rx_data_pkts(psta) == sta_last_rx_data_pkts(psta) + && sta_rx_beacon_pkts(psta) == sta_last_rx_beacon_pkts(psta) + && sta_rx_probersp_pkts(psta) == sta_last_rx_probersp_pkts(psta)) + ret = _FALSE; + + sta_update_last_rx_pkts(psta); + + return ret; +} + +#ifdef CONFIG_TDLS +u8 chk_tdls_peer_sta_is_alive(_adapter *padapter, struct sta_info *psta) +{ + if ((psta->sta_stats.rx_data_pkts == psta->sta_stats.last_rx_data_pkts) + && (psta->sta_stats.rx_tdls_disc_rsp_pkts == psta->sta_stats.last_rx_tdls_disc_rsp_pkts)) + return _FALSE; + + return _TRUE; +} + +void linked_status_chk_tdls(_adapter *padapter) +{ + struct candidate_pool { + struct sta_info *psta; + u8 addr[ETH_ALEN]; + }; + struct sta_priv *pstapriv = &padapter->stapriv; + _irqL irqL; + u8 ack_chk; + struct sta_info *psta; + int i, num_teardown=0, num_checkalive=0; + _list *plist, *phead; + struct tdls_txmgmt txmgmt; + struct candidate_pool checkalive[MAX_ALLOWED_TDLS_STA_NUM]; + struct candidate_pool teardown[MAX_ALLOWED_TDLS_STA_NUM]; + u8 tdls_sta_max = _FALSE; + +#define ALIVE_MIN 2 +#define ALIVE_MAX 5 + + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); + _rtw_memset(checkalive, 0x00, sizeof(checkalive)); + _rtw_memset(teardown, 0x00, sizeof(teardown)); + + if((padapter->tdlsinfo.link_established == _TRUE)){ + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + for(i=0; i< NUM_STA; i++) + { + phead = &(pstapriv->sta_hash[i]); + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) + { + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + plist = get_next(plist); + + if(psta->tdls_sta_state & TDLS_LINKED_STATE) + { + psta->alive_count++; + if(psta->alive_count >= ALIVE_MIN) + { + if (chk_tdls_peer_sta_is_alive(padapter, psta) == _FALSE) { + if (psta->alive_count < ALIVE_MAX) { + _rtw_memcpy(checkalive[num_checkalive].addr, psta->hwaddr, ETH_ALEN); + checkalive[num_checkalive].psta = psta; + num_checkalive++; + } + else + { + _rtw_memcpy(teardown[num_teardown].addr, psta->hwaddr, ETH_ALEN); + teardown[num_teardown].psta = psta; + num_teardown++; + } + } + else + { + psta->alive_count = 0; + } + } + psta->sta_stats.last_rx_data_pkts = psta->sta_stats.rx_data_pkts; + psta->sta_stats.last_rx_tdls_disc_rsp_pkts = psta->sta_stats.rx_tdls_disc_rsp_pkts; + + if ((num_checkalive >= MAX_ALLOWED_TDLS_STA_NUM) || (num_teardown >= MAX_ALLOWED_TDLS_STA_NUM)) { + tdls_sta_max = _TRUE; + break; + } + } + } + + if (tdls_sta_max == _TRUE) + break; + } + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + if (num_checkalive > 0) { + for (i = 0; i < num_checkalive; i++) { + _rtw_memcpy(txmgmt.peer, checkalive[i].addr, ETH_ALEN); + issue_tdls_dis_req(padapter, &txmgmt); + issue_tdls_dis_req(padapter, &txmgmt); + issue_tdls_dis_req(padapter, &txmgmt); + } + } + + if(num_teardown > 0) + { + for(i=0; i< num_teardown; i++) + { + DBG_871X("[%s %d] Send teardown to "MAC_FMT" \n", __FUNCTION__, __LINE__, MAC_ARG(teardown[i].addr)); + txmgmt.status_code = _RSON_TDLS_TEAR_TOOFAR_; + _rtw_memcpy(txmgmt.peer, teardown[i].addr, ETH_ALEN); + issue_tdls_teardown(padapter, &txmgmt, _FALSE); + } + } + } + +} +#endif //CONFIG_TDLS + +//from_timer == 1 means driver is in LPS +void linked_status_chk(_adapter *padapter, u8 from_timer) +{ + u32 i; + struct sta_info *psta; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct sta_priv *pstapriv = &padapter->stapriv; +#ifdef CONFIG_ARP_KEEP_ALIVE + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; +#endif + + + if (is_client_associated_to_ap(padapter)) + { + //linked infrastructure client mode + + int tx_chk = _SUCCESS, rx_chk = _SUCCESS; + int rx_chk_limit; + int link_count_limit; + + #if defined(DBG_ROAMING_TEST) + rx_chk_limit = 1; + #elif defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK) && !defined(CONFIG_LPS_LCLK_WD_TIMER) + rx_chk_limit = 4; + #else + rx_chk_limit = 8; + #endif +#ifdef CONFIG_ARP_KEEP_ALIVE + if (!from_timer && pmlmepriv->bGetGateway == 1) { + DBG_871X("do rtw_gw_addr_query()"); + if (rtw_gw_addr_query(padapter) == 0) { + pmlmepriv->bGetGateway = 0; + } else { + _rtw_memset(pmlmepriv->gw_ip, 0, 4); + _rtw_memset(pmlmepriv->gw_mac_addr, 0, 6); + } + } +#endif +#ifdef CONFIG_P2P + if (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE)) + { + if(!from_timer) + link_count_limit = 3; // 8 sec + else + link_count_limit = 15; // 32 sec + } + else +#endif // CONFIG_P2P + { + if(!from_timer) + link_count_limit = 7; // 16 sec + else + link_count_limit = 29; // 60 sec + } + +#ifdef CONFIG_TDLS +#ifdef CONFIG_TDLS_CH_SW + if (ATOMIC_READ(&padapter->tdlsinfo.chsw_info.chsw_on) == _TRUE) + return; +#endif /* CONFIG_TDLS_CH_SW */ + +#ifdef CONFIG_TDLS_AUTOCHECKALIVE + linked_status_chk_tdls(padapter); +#endif /* CONFIG_TDLS_AUTOCHECKALIVE */ +#endif /* CONFIG_TDLS */ + + if ((psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress)) != NULL) + { + bool is_p2p_enable = _FALSE; + #ifdef CONFIG_P2P + is_p2p_enable = !rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE); + #endif + + /*issue delba when ap does not tx data packet that is Broadcom ap */ + rtw_delba_check(padapter, psta, from_timer); + + if (chk_ap_is_alive(padapter, psta) == _FALSE) + rx_chk = _FAIL; + + if (pxmitpriv->last_tx_pkts == pxmitpriv->tx_pkts) + tx_chk = _FAIL; + + #if defined(CONFIG_ACTIVE_KEEP_ALIVE_CHECK) && !defined(CONFIG_LPS_LCLK_WD_TIMER) + if (pmlmeext->active_keep_alive_check && (rx_chk == _FAIL || tx_chk == _FAIL)) { + u8 backup_oper_channel=0; + + /* switch to correct channel of current network before issue keep-alive frames */ + if (rtw_get_oper_ch(padapter) != pmlmeext->cur_channel) { + backup_oper_channel = rtw_get_oper_ch(padapter); + SelectChannel(padapter, pmlmeext->cur_channel); + } + + if (rx_chk != _SUCCESS) + issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, psta->hwaddr, 0, 0, 3, 1); + + if ((tx_chk != _SUCCESS && pmlmeinfo->link_count++ == link_count_limit) || rx_chk != _SUCCESS) { + tx_chk = issue_nulldata(padapter, psta->hwaddr, 0, 3, 1); + /* if tx acked and p2p disabled, set rx_chk _SUCCESS to reset retry count */ + if (tx_chk == _SUCCESS && !is_p2p_enable) + rx_chk = _SUCCESS; + } + + /* back to the original operation channel */ + if(backup_oper_channel>0) + SelectChannel(padapter, backup_oper_channel); + + } + else + #endif /* CONFIG_ACTIVE_KEEP_ALIVE_CHECK */ + { + if (rx_chk != _SUCCESS) { + if (pmlmeext->retry == 0) { + #ifdef DBG_EXPIRATION_CHK + DBG_871X("issue_probereq to trigger probersp, retry=%d\n", pmlmeext->retry); + #endif + issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, 0); + issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, 0); + issue_probereq_ex(padapter, &pmlmeinfo->network.Ssid, pmlmeinfo->network.MacAddress, 0, 0, 0, 0); + } + } + + if (tx_chk != _SUCCESS && pmlmeinfo->link_count++ == link_count_limit) { + #ifdef DBG_EXPIRATION_CHK + DBG_871X("%s issue_nulldata(%d)\n", __FUNCTION__, from_timer?1:0); + #endif + tx_chk = issue_nulldata_in_interrupt(padapter, NULL, from_timer?1:0); + } + } + + if (rx_chk == _FAIL) { + pmlmeext->retry++; + if (pmlmeext->retry > rx_chk_limit) { + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" disconnect or roaming\n", + FUNC_ADPT_ARG(padapter)); + receive_disconnect(padapter, pmlmeinfo->network.MacAddress + , WLAN_REASON_EXPIRATION_CHK, _FALSE); + return; + } + } else { + pmlmeext->retry = 0; + } + + if (tx_chk == _FAIL) { + pmlmeinfo->link_count %= (link_count_limit+1); + } else { + pxmitpriv->last_tx_pkts = pxmitpriv->tx_pkts; + pmlmeinfo->link_count = 0; + } + + } //end of if ((psta = rtw_get_stainfo(pstapriv, passoc_res->network.MacAddress)) != NULL) + + } else if (is_client_associated_to_ibss(padapter)) { + _irqL irqL; + _list *phead, *plist, dlist; + + _rtw_init_listhead(&dlist); + + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + for (i = 0; i < NUM_STA; i++) { + + phead = &(pstapriv->sta_hash[i]); + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + plist = get_next(plist); + + if (is_broadcast_mac_addr(psta->hwaddr)) + continue; + + if (chk_adhoc_peer_is_alive(psta) || !psta->expire_to) + psta->expire_to = pstapriv->adhoc_expire_to; + else + psta->expire_to--; + + if (psta->expire_to <= 0) { + rtw_list_delete(&psta->list); + rtw_list_insert_tail(&psta->list, &dlist); + } + } + } + + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + plist = get_next(&dlist); + while (rtw_end_of_queue_search(&dlist, plist) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info, list); + plist = get_next(plist); + rtw_list_delete(&psta->list); + DBG_871X(FUNC_ADPT_FMT" ibss expire "MAC_FMT"\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(psta->hwaddr)); + report_del_sta_event(padapter, psta->hwaddr, WLAN_REASON_EXPIRATION_CHK, from_timer ? _TRUE : _FALSE, _FALSE); + } + } + +} + +void survey_timer_hdl(_adapter *padapter) +{ + struct cmd_obj *cmd; + struct sitesurvey_parm *psurveyPara; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); +#endif + + if (mlmeext_scan_state(pmlmeext) > SCAN_DISABLE) { + cmd = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (cmd == NULL) { + rtw_warn_on(1); + goto exit; + } + + psurveyPara = (struct sitesurvey_parm *)rtw_zmalloc(sizeof(struct sitesurvey_parm)); + if (psurveyPara == NULL) { + rtw_warn_on(1); + rtw_mfree((unsigned char *)cmd, sizeof(struct cmd_obj)); + goto exit; + } + + init_h2fwcmd_w_parm_no_rsp(cmd, psurveyPara, GEN_CMD_CODE(_SiteSurvey)); + rtw_enqueue_cmd(pcmdpriv, cmd); + } + +exit: + return; +} + +void link_timer_hdl(_adapter *padapter) +{ + //static unsigned int rx_pkt = 0; + //static u64 tx_cnt = 0; + //struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + //struct sta_priv *pstapriv = &padapter->stapriv; + + + if (pmlmeinfo->state & WIFI_FW_AUTH_NULL) + { + DBG_871X("link_timer_hdl:no beacon while connecting\n"); + pmlmeinfo->state = WIFI_FW_NULL_STATE; + report_join_res(padapter, -3); + } + else if (pmlmeinfo->state & WIFI_FW_AUTH_STATE) + { + //re-auth timer + if (++pmlmeinfo->reauth_count > REAUTH_LIMIT) + { + //if (pmlmeinfo->auth_algo != dot11AuthAlgrthm_Auto) + //{ + pmlmeinfo->state = 0; + report_join_res(padapter, -1); + return; + //} + //else + //{ + // pmlmeinfo->auth_algo = dot11AuthAlgrthm_Shared; + // pmlmeinfo->reauth_count = 0; + //} + } + + DBG_871X("link_timer_hdl: auth timeout and try again\n"); + pmlmeinfo->auth_seq = 1; + issue_auth(padapter, NULL, 0); + set_link_timer(pmlmeext, REAUTH_TO); + } + else if (pmlmeinfo->state & WIFI_FW_ASSOC_STATE) + { + //re-assoc timer + if (++pmlmeinfo->reassoc_count > REASSOC_LIMIT) + { + pmlmeinfo->state = WIFI_FW_NULL_STATE; + report_join_res(padapter, -2); + return; + } + + DBG_871X("link_timer_hdl: assoc timeout and try again\n"); + issue_assocreq(padapter); + set_link_timer(pmlmeext, REASSOC_TO); + } + + return; +} + +void addba_timer_hdl(struct sta_info *psta) +{ +#ifdef CONFIG_80211N_HT + struct ht_priv *phtpriv; + + if(!psta) + return; + + phtpriv = &psta->htpriv; + + if((phtpriv->ht_option==_TRUE) && (phtpriv->ampdu_enable==_TRUE)) + { + if(phtpriv->candidate_tid_bitmap) + phtpriv->candidate_tid_bitmap=0x0; + + } +#endif //CONFIG_80211N_HT +} + +#ifdef CONFIG_IEEE80211W +void report_sta_timeout_event(_adapter *padapter, u8 *MacAddr, unsigned short reason) +{ + struct cmd_obj *pcmd_obj; + u8 *pevtcmd; + u32 cmdsz; + struct sta_info *psta; + int mac_id; + struct stadel_event *pdel_sta_evt; + struct C2HEvent_Header *pc2h_evt_hdr; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + + pcmd_obj = (struct cmd_obj *)rtw_zmalloc(sizeof(struct cmd_obj)); + if (pcmd_obj == NULL) + return; + + cmdsz = (sizeof(struct stadel_event) + sizeof(struct C2HEvent_Header)); + pevtcmd = (u8 *)rtw_zmalloc(cmdsz); + if (pevtcmd == NULL) { + rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); + return; + } + + _rtw_init_listhead(&pcmd_obj->list); + + pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT); + pcmd_obj->cmdsz = cmdsz; + pcmd_obj->parmbuf = pevtcmd; + + pcmd_obj->rsp = NULL; + pcmd_obj->rspsz = 0; + + pc2h_evt_hdr = (struct C2HEvent_Header *)(pevtcmd); + pc2h_evt_hdr->len = sizeof(struct stadel_event); + pc2h_evt_hdr->ID = GEN_EVT_CODE(_TimeoutSTA); + pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); + + pdel_sta_evt = (struct stadel_event *)(pevtcmd + sizeof(struct C2HEvent_Header)); + _rtw_memcpy((unsigned char *)(&(pdel_sta_evt->macaddr)), MacAddr, ETH_ALEN); + _rtw_memcpy((unsigned char *)(pdel_sta_evt->rsvd), (unsigned char *)(&reason), 2); + + + psta = rtw_get_stainfo(&padapter->stapriv, MacAddr); + if (psta) + mac_id = (int)psta->mac_id; + else + mac_id = (-1); + + pdel_sta_evt->mac_id = mac_id; + + DBG_871X("report_del_sta_event: delete STA, mac_id=%d\n", mac_id); + + rtw_enqueue_cmd(pcmdpriv, pcmd_obj); + + return; +} + +void clnt_sa_query_timeout(_adapter *padapter) +{ + + rtw_disassoc_cmd(padapter, 0, _TRUE); + rtw_indicate_disconnect(padapter, 0, _FALSE); + rtw_free_assoc_resources(padapter, 1); + + DBG_871X("SA query timeout client disconnect\n"); +} + +void sa_query_timer_hdl(struct sta_info *psta) +{ + _adapter *padapter = psta->padapter; + _irqL irqL; + struct sta_priv *pstapriv = &padapter->stapriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE && + check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + clnt_sa_query_timeout(padapter); + else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + report_sta_timeout_event(padapter, psta->hwaddr, WLAN_REASON_PREV_AUTH_NOT_VALID); +} + +#endif //CONFIG_IEEE80211W + +u8 NULL_hdl(_adapter *padapter, u8 *pbuf) +{ + return H2C_SUCCESS; +} + +#ifdef CONFIG_AUTO_AP_MODE +void rtw_start_auto_ap(_adapter *adapter) +{ + DBG_871X("%s\n", __FUNCTION__); + + rtw_set_802_11_infrastructure_mode(adapter, Ndis802_11APMode); + + rtw_setopmode_cmd(adapter, Ndis802_11APMode,_TRUE); +} + +static int rtw_auto_ap_start_beacon(_adapter *adapter) +{ + int ret=0; + u8 *pbuf = NULL; + uint len; + u8 supportRate[16]; + int sz = 0, rateLen; + u8 * ie; + u8 wireless_mode, oper_channel; + u8 ssid[3] = {0}; //hidden ssid + u32 ssid_len = sizeof(ssid); + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + + + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + return -EINVAL; + + + len = 128; + pbuf = rtw_zmalloc(len); + if(!pbuf) + return -ENOMEM; + + + //generate beacon + ie = pbuf; + + //timestamp will be inserted by hardware + sz += 8; + ie += sz; + + //beacon interval : 2bytes + *(u16*)ie = cpu_to_le16((u16)100);//BCN_INTERVAL=100; + sz += 2; + ie += 2; + + //capability info + *(u16*)ie = 0; + *(u16*)ie |= cpu_to_le16(cap_ESS); + *(u16*)ie |= cpu_to_le16(cap_ShortPremble); + //*(u16*)ie |= cpu_to_le16(cap_Privacy); + sz += 2; + ie += 2; + + //SSID + ie = rtw_set_ie(ie, _SSID_IE_, ssid_len, ssid, &sz); + + //supported rates + wireless_mode = WIRELESS_11BG_24N; + rtw_set_supported_rate(supportRate, wireless_mode) ; + rateLen = rtw_get_rateset_len(supportRate); + if (rateLen > 8) + { + ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, 8, supportRate, &sz); + } + else + { + ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, rateLen, supportRate, &sz); + } + + + //DS parameter set + if(check_buddy_fwstate(adapter, _FW_LINKED) && + check_buddy_fwstate(adapter, WIFI_STATION_STATE)) + { + PADAPTER pbuddy_adapter = adapter->pbuddy_adapter; + struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; + + oper_channel = pbuddy_mlmeext->cur_channel; + } + else + { + oper_channel = adapter_to_dvobj(adapter)->oper_channel; + } + ie = rtw_set_ie(ie, _DSSET_IE_, 1, &oper_channel, &sz); + + //ext supported rates + if (rateLen > 8) + { + ie = rtw_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), (supportRate + 8), &sz); + } + + DBG_871X("%s, start auto ap beacon sz=%d\n", __FUNCTION__, sz); + + //lunch ap mode & start to issue beacon + if(rtw_check_beacon_data(adapter, pbuf, sz) == _SUCCESS) + { + + } + else + { + ret = -EINVAL; + } + + + rtw_mfree(pbuf, len); + + return ret; + +} +#endif//CONFIG_AUTO_AP_MODE + +u8 setopmode_hdl(_adapter *padapter, u8 *pbuf) +{ + u8 type; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct setopmode_parm *psetop = (struct setopmode_parm *)pbuf; + + if(psetop->mode == Ndis802_11APMode) + { + pmlmeinfo->state = WIFI_FW_AP_STATE; + type = _HW_STATE_AP_; +#ifdef CONFIG_NATIVEAP_MLME + //start_ap_mode(padapter); +#endif + } + else if(psetop->mode == Ndis802_11Infrastructure) + { + pmlmeinfo->state &= ~(BIT(0)|BIT(1));// clear state + pmlmeinfo->state |= WIFI_FW_STATION_STATE;//set to STATION_STATE + type = _HW_STATE_STATION_; + } + else if(psetop->mode == Ndis802_11IBSS) + { + type = _HW_STATE_ADHOC_; + } else if (psetop->mode == Ndis802_11Monitor) { + type = _HW_STATE_MONITOR_; + } + else + { + type = _HW_STATE_NOLINK_; + } + + rtw_hal_set_hwreg(padapter, HW_VAR_SET_OPMODE, (u8 *)(&type)); + //Set_NETYPE0_MSR(padapter, type); + + +#ifdef CONFIG_AUTO_AP_MODE + if(psetop->mode == Ndis802_11APMode) + rtw_auto_ap_start_beacon(padapter); +#endif + + if (rtw_port_switch_chk(padapter) == _TRUE) + { + rtw_hal_set_hwreg(padapter, HW_VAR_PORT_SWITCH, NULL); + + if(psetop->mode == Ndis802_11APMode) + adapter_to_pwrctl(padapter)->fw_psmode_iface_id = 0xff; //ap mode won't dowload rsvd pages + else if (psetop->mode == Ndis802_11Infrastructure) { + #ifdef CONFIG_LPS + _adapter *port0_iface = dvobj_get_port0_adapter(adapter_to_dvobj(padapter)); + if (port0_iface) + rtw_lps_ctrl_wk_cmd(port0_iface, LPS_CTRL_CONNECT, 0); + #endif + } + } + +#ifdef CONFIG_BT_COEXIST + if (psetop->mode == Ndis802_11APMode) + { + // Do this after port switch to + // prevent from downloading rsvd page to wrong port + rtw_btcoex_MediaStatusNotify(padapter, 1); //connect + } +#endif // CONFIG_BT_COEXIST + + return H2C_SUCCESS; + +} + +u8 createbss_hdl(_adapter *padapter, u8 *pbuf) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network)); + WLAN_BSSID_EX *pdev_network = &padapter->registrypriv.dev_network; + struct createbss_parm *parm = (struct createbss_parm *)pbuf; + u8 ret = H2C_SUCCESS; + //u8 initialgain; + +#ifdef CONFIG_AP_MODE + if (pmlmeinfo->state == WIFI_FW_AP_STATE) { + start_bss_network(padapter, parm); + goto exit; + } +#endif + + /* below is for ad-hoc master */ + if (parm->adhoc) { + rtw_warn_on(pdev_network->InfrastructureMode != Ndis802_11IBSS); + rtw_joinbss_reset(padapter); + + pmlmeext->cur_bwmode = CHANNEL_WIDTH_20; + pmlmeext->cur_ch_offset= HAL_PRIME_CHNL_OFFSET_DONT_CARE; + pmlmeinfo->ERP_enable = 0; + pmlmeinfo->WMM_enable = 0; + pmlmeinfo->HT_enable = 0; + pmlmeinfo->HT_caps_enable = 0; + pmlmeinfo->HT_info_enable = 0; + pmlmeinfo->agg_enable_bitmap = 0; + pmlmeinfo->candidate_tid_bitmap = 0; + + //config the initial gain under linking, need to write the BB registers + //initialgain = 0x1E; + /*rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, _FALSE);*/ + + //disable dynamic functions, such as high power, DIG + rtw_phydm_ability_backup(padapter); + rtw_phydm_func_disable_all(padapter); + + //cancel link timer + _cancel_timer_ex(&pmlmeext->link_timer); + + //clear CAM + flush_all_cam_entry(padapter); + + pdev_network->Length = get_WLAN_BSSID_EX_sz(pdev_network); + _rtw_memcpy(pnetwork, pdev_network, FIELD_OFFSET(WLAN_BSSID_EX, IELength)); + pnetwork->IELength = pdev_network->IELength; + + if (pnetwork->IELength > MAX_IE_SZ) { + ret = H2C_PARAMETERS_ERROR; + goto ibss_post_hdl; + } + + _rtw_memcpy(pnetwork->IEs, pdev_network->IEs, pnetwork->IELength); + start_create_ibss(padapter); + } else { + rtw_warn_on(1); + ret = H2C_PARAMETERS_ERROR; + } + +ibss_post_hdl: + rtw_create_ibss_post_hdl(padapter, ret); + +exit: + return ret; +} + +u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf) +{ + u8 join_type; + PNDIS_802_11_VARIABLE_IEs pIE; + struct registry_priv *pregpriv = &padapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network)); +#ifdef CONFIG_ANTENNA_DIVERSITY + struct joinbss_parm *pparm = (struct joinbss_parm *)pbuf; +#endif //CONFIG_ANTENNA_DIVERSITY + u32 i; + //u8 initialgain; + //u32 acparm; + u8 u_ch, u_bw, u_offset; + u8 doiqk = _FALSE; + + //check already connecting to AP or not + if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) + { + if (pmlmeinfo->state & WIFI_FW_STATION_STATE) + { + issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 1, 100); + } + pmlmeinfo->state = WIFI_FW_NULL_STATE; + + //clear CAM + flush_all_cam_entry(padapter); + + _cancel_timer_ex(&pmlmeext->link_timer); + + //set MSR to nolink -> infra. mode + //Set_MSR(padapter, _HW_STATE_NOLINK_); + Set_MSR(padapter, _HW_STATE_STATION_); + + + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_DISCONNECT, 0); + } + +#ifdef CONFIG_ANTENNA_DIVERSITY + rtw_antenna_select_cmd(padapter, pparm->network.PhyInfo.Optimum_antenna, _FALSE); +#endif + +#ifdef CONFIG_WAPI_SUPPORT + rtw_wapi_clear_all_cam_entry(padapter); +#endif + + rtw_joinbss_reset(padapter); + + pmlmeinfo->ERP_enable = 0; + pmlmeinfo->WMM_enable = 0; + pmlmeinfo->HT_enable = 0; + pmlmeinfo->HT_caps_enable = 0; + pmlmeinfo->HT_info_enable = 0; + pmlmeinfo->agg_enable_bitmap = 0; + pmlmeinfo->candidate_tid_bitmap = 0; + pmlmeinfo->bwmode_updated = _FALSE; + //pmlmeinfo->assoc_AP_vendor = HT_IOT_PEER_MAX; + pmlmeinfo->VHT_enable = 0; + + _rtw_memcpy(pnetwork, pbuf, FIELD_OFFSET(WLAN_BSSID_EX, IELength)); + pnetwork->IELength = ((WLAN_BSSID_EX *)pbuf)->IELength; + + if(pnetwork->IELength>MAX_IE_SZ)//Check pbuf->IELength + return H2C_PARAMETERS_ERROR; + + if (pnetwork->IELength < 2) { + report_join_res(padapter, (-4)); + return H2C_SUCCESS; + } + _rtw_memcpy(pnetwork->IEs, ((WLAN_BSSID_EX *)pbuf)->IEs, pnetwork->IELength); + + pmlmeinfo->bcn_interval = get_beacon_interval(pnetwork); + + //Check AP vendor to move rtw_joinbss_cmd() + //pmlmeinfo->assoc_AP_vendor = check_assoc_AP(pnetwork->IEs, pnetwork->IELength); + + //sizeof(NDIS_802_11_FIXED_IEs) + for (i = _FIXED_IE_LENGTH_ ; i < pnetwork->IELength - 2 ;) { + pIE = (PNDIS_802_11_VARIABLE_IEs)(pnetwork->IEs + i); + + switch (pIE->ElementID) + { + case _VENDOR_SPECIFIC_IE_://Get WMM IE. + if ( _rtw_memcmp(pIE->data, WMM_OUI, 4) ) + { + WMM_param_handler(padapter, pIE); + } + break; + +#ifdef CONFIG_80211N_HT + case _HT_CAPABILITY_IE_: //Get HT Cap IE. + pmlmeinfo->HT_caps_enable = 1; + break; + + case _HT_EXTRA_INFO_IE_: //Get HT Info IE. + pmlmeinfo->HT_info_enable = 1; + break; +#endif /* CONFIG_80211N_HT */ + +#ifdef CONFIG_80211AC_VHT + case EID_VHTCapability://Get VHT Cap IE. + pmlmeinfo->VHT_enable = 1; + break; + + case EID_VHTOperation://Get VHT Operation IE. + break; +#endif /* CONFIG_80211AC_VHT */ + default: + break; + } + + i += (pIE->Length + 2); + } + + rtw_bss_get_chbw(pnetwork + , &pmlmeext->cur_channel, &pmlmeext->cur_bwmode, &pmlmeext->cur_ch_offset); + + rtw_adjust_chbw(padapter, pmlmeext->cur_channel, &pmlmeext->cur_bwmode, &pmlmeext->cur_ch_offset); + +#if 0 + if (padapter->registrypriv.wifi_spec) { + // for WiFi test, follow WMM test plan spec + acparm = 0x002F431C; // VO + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acparm)); + acparm = 0x005E541C; // VI + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acparm)); + acparm = 0x0000A525; // BE + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm)); + acparm = 0x0000A549; // BK + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acparm)); + + // for WiFi test, mixed mode with intel STA under bg mode throughput issue + if (padapter->mlmepriv.htpriv.ht_option == _FALSE){ + acparm = 0x00004320; + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm)); + } + } + else { + acparm = 0x002F3217; // VO + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acparm)); + acparm = 0x005E4317; // VI + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acparm)); + acparm = 0x00105320; // BE + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm)); + acparm = 0x0000A444; // BK + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acparm)); + } +#endif + + /* check channel, bandwidth, offset and switch */ + if (rtw_chk_start_clnt_join(padapter, &u_ch, &u_bw, &u_offset) == _FAIL) { + report_join_res(padapter, (-4)); + return H2C_SUCCESS; + } + + //disable dynamic functions, such as high power, DIG + /*rtw_phydm_func_disable_all(padapter);*/ + + //config the initial gain under linking, need to write the BB registers + //initialgain = 0x1E; + /*rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, _FALSE);*/ + + rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress); + join_type = 0; + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); + doiqk = _TRUE; + rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); + + set_channel_bwmode(padapter, u_ch, u_offset, u_bw); + + doiqk = _FALSE; + rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); + + //cancel link timer + _cancel_timer_ex(&pmlmeext->link_timer); + + start_clnt_join(padapter); + + return H2C_SUCCESS; + +} + +u8 disconnect_hdl(_adapter *padapter, unsigned char *pbuf) +{ + struct disconnect_parm *param = (struct disconnect_parm *)pbuf; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network)); + u8 val8; + + if (is_client_associated_to_ap(padapter)) + { +#ifdef CONFIG_DFS + if(padapter->mlmepriv.handle_dfs == _FALSE) +#endif //CONFIG_DFS +#ifdef CONFIG_PLATFORM_ROCKCHIPS + //To avoid connecting to AP fail during resume process, change retry count from 5 to 1 + issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, 1, 100); +#else + issue_deauth_ex(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING, param->deauth_timeout_ms/100, 100); +#endif //CONFIG_PLATFORM_ROCKCHIPS + } + +#ifdef CONFIG_DFS + if( padapter->mlmepriv.handle_dfs == _TRUE ) + padapter->mlmepriv.handle_dfs = _FALSE; +#endif //CONFIG_DFS + + if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)) + { + //Stop BCN + val8 = 0; + rtw_hal_set_hwreg(padapter, HW_VAR_BCN_FUNC, (u8 *)(&val8)); + } + + rtw_mlmeext_disconnect(padapter); + + rtw_free_uc_swdec_pending_queue(padapter); + + return H2C_SUCCESS; +} + +static const char * const _scan_state_str[] = { + "SCAN_DISABLE", + "SCAN_START", + "SCAN_PS_ANNC_WAIT", + "SCAN_ENTER", + "SCAN_PROCESS", + "SCAN_BACKING_OP", + "SCAN_BACK_OP", + "SCAN_LEAVING_OP", + "SCAN_LEAVE_OP", + "SCAN_SW_ANTDIV_BL", + "SCAN_TO_P2P_LISTEN", + "SCAN_P2P_LISTEN", + "SCAN_COMPLETE", + "SCAN_STATE_MAX", +}; + +const char *scan_state_str(u8 state) +{ + state = (state >= SCAN_STATE_MAX) ? SCAN_STATE_MAX : state; + return _scan_state_str[state]; +} + +static bool scan_abort_hdl(_adapter *adapter) +{ + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct ss_res *ss = &pmlmeext->sitesurvey_res; +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &adapter->wdinfo; +#endif + bool ret = _FALSE; + + if (pmlmeext->scan_abort == _TRUE) { + #ifdef CONFIG_P2P + if (!rtw_p2p_chk_state(&adapter->wdinfo, P2P_STATE_NONE)) { + rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_MAX); + ss->channel_idx = 3; + DBG_871X("%s idx:%d, cnt:%u\n", __FUNCTION__ + , ss->channel_idx + , pwdinfo->find_phase_state_exchange_cnt + ); + } else + #endif + { + ss->channel_idx = ss->ch_num; + DBG_871X("%s idx:%d\n", __FUNCTION__ + , ss->channel_idx + ); + } + pmlmeext->scan_abort = _FALSE; + ret = _TRUE; + } + + return ret; +} + +u8 rtw_scan_sparse(_adapter *adapter, struct rtw_ieee80211_channel *ch, u8 ch_num) +{ +/* interval larger than this is treated as backgroud scan */ +#ifndef RTW_SCAN_SPARSE_BG_INTERVAL_MS +#define RTW_SCAN_SPARSE_BG_INTERVAL_MS 12000 +#endif + +#ifndef RTW_SCAN_SPARSE_CH_NUM_MIRACAST +#define RTW_SCAN_SPARSE_CH_NUM_MIRACAST 1 +#endif +#ifndef RTW_SCAN_SPARSE_CH_NUM_BG +#define RTW_SCAN_SPARSE_CH_NUM_BG 4 +#endif + +#define SCAN_SPARSE_CH_NUM_INVALID 255 + + static u8 token = 255; + u32 interval; + bool busy_traffic = _FALSE; + bool miracast_enabled = _FALSE; + bool bg_scan = _FALSE; + u8 max_allow_ch = SCAN_SPARSE_CH_NUM_INVALID; + u8 scan_division_num; + u8 ret_num = ch_num; + struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter)); + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + + if (regsty->wifi_spec) + goto exit; + + /* assume ch_num > 6 is normal scan */ + if (ch_num <= 6) + goto exit; + + if (mlmeext->last_scan_time == 0) + mlmeext->last_scan_time = rtw_get_current_time(); + + interval = rtw_get_passing_time_ms(mlmeext->last_scan_time); + + if (adapter->mlmepriv.LinkDetectInfo.bBusyTraffic == _TRUE + #ifdef CONFIG_CONCURRENT_MODE + || (adapter->pbuddy_adapter && adapter->pbuddy_adapter->mlmepriv.LinkDetectInfo.bBusyTraffic == _TRUE) + #endif + ) + busy_traffic = _TRUE; + + if (is_miracast_enabled(adapter) + #ifdef CONFIG_CONCURRENT_MODE + || (adapter->pbuddy_adapter && is_miracast_enabled(adapter->pbuddy_adapter)) + #endif + ) + miracast_enabled = _TRUE; + + if (interval > RTW_SCAN_SPARSE_BG_INTERVAL_MS) + bg_scan = _TRUE; + + /* max_allow_ch by conditions*/ + + #if RTW_SCAN_SPARSE_MIRACAST + if (miracast_enabled == _TRUE && busy_traffic == _TRUE) + max_allow_ch = rtw_min(max_allow_ch, RTW_SCAN_SPARSE_CH_NUM_MIRACAST); + #endif + + #if RTW_SCAN_SPARSE_BG + if (bg_scan == _TRUE) + max_allow_ch = rtw_min(max_allow_ch, RTW_SCAN_SPARSE_CH_NUM_BG); + #endif + + + if (max_allow_ch != SCAN_SPARSE_CH_NUM_INVALID) { + int i; + int k = 0; + + scan_division_num = (ch_num / max_allow_ch) + ((ch_num % max_allow_ch)?1:0); + token = (token + 1) % scan_division_num; + + if (0) + DBG_871X("scan_division_num:%u, token:%u\n", scan_division_num, token); + + for (i = 0; i < ch_num; i++) { + if (ch[i].hw_value && (i % scan_division_num) == token + ) { + if (i != k) + _rtw_memcpy(&ch[k], &ch[i], sizeof(struct rtw_ieee80211_channel)); + k++; + } + } + + _rtw_memset(&ch[k], 0, sizeof(struct rtw_ieee80211_channel)); + + ret_num = k; + mlmeext->last_scan_time = rtw_get_current_time(); + } + +exit: + return ret_num; +} + +static int rtw_scan_ch_decision(_adapter *padapter, struct rtw_ieee80211_channel *out, + u32 out_num, struct rtw_ieee80211_channel *in, u32 in_num) +{ + int i, j; + int scan_ch_num = 0; + int set_idx; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + /* clear first */ + _rtw_memset(out, 0, sizeof(struct rtw_ieee80211_channel)*out_num); + + /* acquire channels from in */ + j = 0; + for (i=0;ichannel_set, in[i].hw_value)) >=0 + && rtw_mlme_band_check(padapter, in[i].hw_value) == _TRUE + ) + { + if (j >= out_num) { + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" out_num:%u not enough\n", + FUNC_ADPT_ARG(padapter), out_num); + break; + } + + _rtw_memcpy(&out[j], &in[i], sizeof(struct rtw_ieee80211_channel)); + + if(pmlmeext->channel_set[set_idx].ScanType == SCAN_PASSIVE) + out[j].flags |= RTW_IEEE80211_CHAN_PASSIVE_SCAN; + + j++; + } + if(j>=out_num) + break; + } + + /* if out is empty, use channel_set as default */ + if(j == 0) { + for (i=0;imax_chan_nums;i++) { + + if (0) + DBG_871X(FUNC_ADPT_FMT" ch:%u\n", FUNC_ADPT_ARG(padapter), pmlmeext->channel_set[i].ChannelNum); + + if (rtw_mlme_band_check(padapter, pmlmeext->channel_set[i].ChannelNum) == _TRUE) { + + if (j >= out_num) { + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" out_num:%u not enough\n", + FUNC_ADPT_ARG(padapter), out_num); + break; + } + + out[j].hw_value = pmlmeext->channel_set[i].ChannelNum; + + if(pmlmeext->channel_set[i].ScanType == SCAN_PASSIVE) + out[j].flags |= RTW_IEEE80211_CHAN_PASSIVE_SCAN; + + j++; + } + } + } + + /* scan_sparse */ + j = rtw_scan_sparse(padapter, out, j); + + return j; +} + +static void sitesurvey_res_reset(_adapter *adapter, struct sitesurvey_parm *parm) +{ + struct ss_res *ss = &adapter->mlmeextpriv.sitesurvey_res; + int i; + + ss->bss_cnt = 0; + ss->channel_idx = 0; + ss->igi_scan = 0; + ss->igi_before_scan = 0; +#ifdef CONFIG_SCAN_BACKOP + ss->scan_cnt = 0; +#endif +#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL) + ss->is_sw_antdiv_bl_scan = 0; +#endif + + for (i = 0; i < RTW_SSID_SCAN_AMOUNT; i++) { + if (parm->ssid[i].SsidLength) { + _rtw_memcpy(ss->ssid[i].Ssid, parm->ssid[i].Ssid, IW_ESSID_MAX_SIZE); + ss->ssid[i].SsidLength = parm->ssid[i].SsidLength; + } else { + ss->ssid[i].SsidLength = 0; + } + } + + ss->ch_num = rtw_scan_ch_decision(adapter + , ss->ch, RTW_CHANNEL_SCAN_AMOUNT + , parm->ch, parm->ch_num + ); + + ss->scan_mode = parm->scan_mode; +} + +static u8 sitesurvey_pick_ch_behavior(_adapter *padapter, u8 *ch, RT_SCAN_TYPE *type) +{ + u8 next_state; + u8 scan_ch = 0; + RT_SCAN_TYPE scan_type = SCAN_PASSIVE; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + struct ss_res *ss = &pmlmeext->sitesurvey_res; + +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &padapter->wdinfo; +#endif + + /* handle scan abort request */ + scan_abort_hdl(padapter); + +#ifdef CONFIG_P2P + if (pwdinfo->rx_invitereq_info.scan_op_ch_only || pwdinfo->p2p_info.scan_op_ch_only) { + if (pwdinfo->rx_invitereq_info.scan_op_ch_only) + scan_ch = pwdinfo->rx_invitereq_info.operation_ch[ss->channel_idx]; + else + scan_ch = pwdinfo->p2p_info.operation_ch[ss->channel_idx]; + scan_type = SCAN_ACTIVE; + } else if (rtw_p2p_findphase_ex_is_social(pwdinfo)) { + /* + * Commented by Albert 2011/06/03 + * The driver is in the find phase, it should go through the social channel. + */ + int ch_set_idx; + + scan_ch = pwdinfo->social_chan[ss->channel_idx]; + ch_set_idx = rtw_ch_set_search_ch(pmlmeext->channel_set, scan_ch); + if (ch_set_idx >= 0) + scan_type = pmlmeext->channel_set[ch_set_idx].ScanType; + else + scan_type = SCAN_ACTIVE; + } else +#endif /* CONFIG_P2P */ + { + struct rtw_ieee80211_channel *ch; + + if (ss->channel_idx < ss->ch_num) { + ch = &ss->ch[ss->channel_idx]; + scan_ch = ch->hw_value; + scan_type = (ch->flags & RTW_IEEE80211_CHAN_PASSIVE_SCAN) ? SCAN_PASSIVE : SCAN_ACTIVE; + } + } + + if (scan_ch != 0) { + next_state = SCAN_PROCESS; + #ifdef CONFIG_SCAN_BACKOP + { + u8 sta_num; + u8 ld_sta_num; + u8 ap_num; + u8 ld_ap_num; + u8 backop_flags = 0; + + rtw_dev_iface_status(padapter, &sta_num, &ld_sta_num, NULL, &ap_num, &ld_ap_num); + + if ((ld_sta_num > 0 && mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN)) + || (sta_num > 0 && mlmeext_chk_scan_backop_flags_sta(pmlmeext, SS_BACKOP_EN_NL)) + ) { + backop_flags |= mlmeext_scan_backop_flags_sta(pmlmeext); + } + + if ((ld_ap_num > 0 && mlmeext_chk_scan_backop_flags_ap(pmlmeext, SS_BACKOP_EN)) + || (ap_num > 0 && mlmeext_chk_scan_backop_flags_ap(pmlmeext, SS_BACKOP_EN_NL)) + ) { + backop_flags |= mlmeext_scan_backop_flags_ap(pmlmeext); + } + + if (backop_flags) { + if (ss->scan_cnt < ss->scan_cnt_max) { + ss->scan_cnt++; + } else { + mlmeext_assign_scan_backop_flags(pmlmeext, backop_flags); + next_state = SCAN_BACKING_OP; + } + } + } + #endif /* CONFIG_SCAN_BACKOP */ + } else if (rtw_p2p_findphase_ex_is_needed(pwdinfo)) { + /* go p2p listen */ + next_state = SCAN_TO_P2P_LISTEN; + + #ifdef CONFIG_ANTENNA_DIVERSITY + } else if (rtw_hal_antdiv_before_linked(padapter)) { + /* go sw antdiv before link */ + next_state = SCAN_SW_ANTDIV_BL; + #endif + } else { + next_state = SCAN_COMPLETE; + + #if defined(DBG_SCAN_SW_ANTDIV_BL) + { + /* for SCAN_SW_ANTDIV_BL state testing */ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + int i; + bool is_linked = _FALSE; + + for (i = 0; i < dvobj->iface_nums; i++) { + if (rtw_linked_check(dvobj->padapters[i])) + is_linked = _TRUE; + } + + if (!is_linked) { + static bool fake_sw_antdiv_bl_state = 0; + + if (fake_sw_antdiv_bl_state == 0) { + next_state = SCAN_SW_ANTDIV_BL; + fake_sw_antdiv_bl_state = 1; + } else { + fake_sw_antdiv_bl_state = 0; + } + } + } + #endif /* defined(DBG_SCAN_SW_ANTDIV_BL) */ + } + + #ifdef CONFIG_SCAN_BACKOP + if (next_state != SCAN_PROCESS) + ss->scan_cnt = 0; + #endif + + +#ifdef DBG_FIXED_CHAN + if (pmlmeext->fixed_chan != 0xff && next_state == SCAN_PROCESS) + scan_ch = pmlmeext->fixed_chan; +#endif + + if (ch) + *ch = scan_ch; + if (type) + *type = scan_type; + + return next_state; +} + +void site_survey(_adapter *padapter, u8 survey_channel, RT_SCAN_TYPE ScanType) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); +#endif + + if (survey_channel != 0) { + set_channel_bwmode(padapter, survey_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + + #ifdef CONFIG_AUTO_CHNL_SEL_NHM + if (ACS_ENABLE == GET_ACS_STATE(padapter)) { + ACS_OP acs_op = ACS_RESET; + + rtw_hal_set_odm_var(padapter, HAL_ODM_AUTO_CHNL_SEL, &acs_op, _TRUE); + rtw_set_acs_channel(padapter, survey_channel); + #ifdef DBG_AUTO_CHNL_SEL_NHM + DBG_871X("[ACS-"ADPT_FMT"]-set ch:%u\n", + ADPT_ARG(padapter), rtw_get_acs_channel(padapter)); + #endif + } + #endif + + if (ScanType == SCAN_ACTIVE) { + #ifdef CONFIG_P2P + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) || + rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH) + ) { + issue_probereq_p2p(padapter, NULL); + issue_probereq_p2p(padapter, NULL); + issue_probereq_p2p(padapter, NULL); + } else + #endif /* CONFIG_P2P */ + { + int i; + + for (i = 0; i < RTW_SSID_SCAN_AMOUNT; i++) { + if (pmlmeext->sitesurvey_res.ssid[i].SsidLength) { + /* IOT issue, When wifi_spec is not set, send one probe req without WPS IE. */ + if (padapter->registrypriv.wifi_spec) + issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL); + else + issue_probereq_ex(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL, 0, 0, 0, 0); + issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]), NULL); + } + } + + if (pmlmeext->sitesurvey_res.scan_mode == SCAN_ACTIVE) { + /* IOT issue, When wifi_spec is not set, send one probe req without WPS IE. */ + if (padapter->registrypriv.wifi_spec) + issue_probereq(padapter, NULL, NULL); + else + issue_probereq_ex(padapter, NULL, NULL, 0, 0, 0, 0); + issue_probereq(padapter, NULL, NULL); + } + } + } + } else { + /* channel number is 0 or this channel is not valid. */ + rtw_warn_on(1); + } + + return; +} + +void survey_done_set_ch_bw(_adapter *padapter) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + u8 cur_channel = 0; + u8 cur_bwmode; + u8 cur_ch_offset; + + if (rtw_get_ch_setting_union(padapter, &cur_channel, &cur_bwmode, &cur_ch_offset) != 0) { + if (0) + DBG_871X(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n", + FUNC_ADPT_ARG(padapter), cur_channel, cur_bwmode, cur_ch_offset); + } else { + #ifdef CONFIG_P2P + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + _adapter *iface; + int i; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (!iface) + continue; + + #ifdef CONFIG_IOCTL_CFG80211 + if (iface->wdinfo.driver_interface == DRIVER_CFG80211 && !adapter_wdev_data(iface)->p2p_enabled) + continue; + #endif + + if (rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_LISTEN)) { + cur_channel = iface->wdinfo.listen_channel; + cur_bwmode = CHANNEL_WIDTH_20; + cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + if (0) + DBG_871X(FUNC_ADPT_FMT" back to "ADPT_FMT"'s listen ch - ch:%u, bw:%u, offset:%u\n", + FUNC_ADPT_ARG(padapter), ADPT_ARG(iface), cur_channel, cur_bwmode, cur_ch_offset); + break; + } + } + #endif /* CONFIG_P2P */ + + if (cur_channel == 0) { + cur_channel = pmlmeext->cur_channel; + cur_bwmode = pmlmeext->cur_bwmode; + cur_ch_offset = pmlmeext->cur_ch_offset; + if (0) + DBG_871X(FUNC_ADPT_FMT" back to ch:%u, bw:%u, offset:%u\n", + FUNC_ADPT_ARG(padapter), cur_channel, cur_bwmode, cur_ch_offset); + } + } + + set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode); +} + +/** + * sitesurvey_ps_annc - check and doing ps announcement for all the adapters of given @dvobj + * @dvobj: the dvobj to check + * @ps: power saving or not + * + * Returns: 0: no ps announcement is doing. 1: ps announcement is doing + */ +u8 sitesurvey_ps_annc(struct dvobj_priv *dvobj, bool ps) +{ + _adapter *adapter; + int i; + u8 ps_anc = 0; + + for (i = 0; i < dvobj->iface_nums; i++) { + adapter = dvobj->padapters[i]; + if (!adapter) + continue; + + if (ps) { + if (is_client_associated_to_ap(adapter) == _TRUE) { + /* TODO: TDLS peers */ + issue_nulldata(adapter, NULL, 1, 3, 500); + ps_anc = 1; + } + } else { + if (is_client_associated_to_ap(adapter) == _TRUE) { + /* TODO: TDLS peers */ + issue_nulldata(adapter, NULL, 0, 3, 500); + ps_anc = 1; + } + } + } + + return ps_anc; +} + +void sitesurvey_set_igi(_adapter *adapter) +{ + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + struct ss_res *ss = &mlmeext->sitesurvey_res; + u8 igi; +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &adapter->wdinfo; +#endif + + switch (mlmeext_scan_state(mlmeext)) { + case SCAN_ENTER: + #ifdef CONFIG_P2P + #ifdef CONFIG_IOCTL_CFG80211 + if (adapter_wdev_data(adapter)->p2p_enabled == _TRUE && pwdinfo->driver_interface == DRIVER_CFG80211) + igi = 0x30; + else + #endif /* CONFIG_IOCTL_CFG80211 */ + if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + igi = 0x28; + else + #endif /* CONFIG_P2P */ + igi = 0x1e; + + /* record IGI status */ + ss->igi_scan = igi; + rtw_hal_get_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &ss->igi_before_scan, NULL); + + /* disable DIG and set IGI for scan */ + rtw_hal_set_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &igi, _FALSE); + break; + case SCAN_COMPLETE: + case SCAN_TO_P2P_LISTEN: + /* enable DIG and restore IGI */ + igi = 0xff; + rtw_hal_set_odm_var(adapter, HAL_ODM_INITIAL_GAIN, &igi, _FALSE); + break; +#ifdef CONFIG_SCAN_BACKOP + case SCAN_BACKING_OP: + /* write IGI for op channel when DIG is not enabled */ + ODM_Write_DIG(GET_ODM(adapter), ss->igi_before_scan); + break; + case SCAN_LEAVE_OP: + /* write IGI for scan when DIG is not enabled */ + ODM_Write_DIG(GET_ODM(adapter), ss->igi_scan); + break; +#endif /* CONFIG_SCAN_BACKOP */ + default: + rtw_warn_on(1); + break; + } +} + + +u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) +{ + struct sitesurvey_parm *pparm = (struct sitesurvey_parm *)pbuf; + struct dvobj_priv *dvobj = padapter->dvobj; + struct debug_priv *pdbgpriv = &dvobj->drv_dbg; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct ss_res *ss = &pmlmeext->sitesurvey_res; + u8 val8; + +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &padapter->wdinfo; +#endif + +#ifdef DBG_CHECK_FW_PS_STATE + if (rtw_fw_ps_state(padapter) == _FAIL) { + DBG_871X("scan without leave 32k\n"); + pdbgpriv->dbg_scan_pwr_state_cnt++; + } +#endif /* DBG_CHECK_FW_PS_STATE */ + + /* increase channel idx */ + if (mlmeext_chk_scan_state(pmlmeext, SCAN_PROCESS)) + ss->channel_idx++; + + /* update scan state to next state (assigned by previous cmd hdl) */ + if (mlmeext_scan_state(pmlmeext) != mlmeext_scan_next_state(pmlmeext)) + mlmeext_set_scan_state(pmlmeext, mlmeext_scan_next_state(pmlmeext)); + +operation_by_state: + switch (mlmeext_scan_state(pmlmeext)) { + + case SCAN_DISABLE: + /* + * SW parameter initialization + */ + + sitesurvey_res_reset(padapter, pparm); + mlmeext_set_scan_state(pmlmeext, SCAN_START); + goto operation_by_state; + + case SCAN_START: + /* + * prepare to leave operating channel + */ + + /* apply rx ampdu setting */ + if (ss->rx_ampdu_accept != RX_AMPDU_ACCEPT_INVALID + || ss->rx_ampdu_size != RX_AMPDU_SIZE_INVALID + ) { + rtw_rx_ampdu_apply(padapter); + } + + /* clear HW TX queue before scan */ + rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0); + + /* power save state announcement */ + if (sitesurvey_ps_annc(adapter_to_dvobj(padapter), 1)) { + mlmeext_set_scan_state(pmlmeext, SCAN_PS_ANNC_WAIT); + mlmeext_set_scan_next_state(pmlmeext, SCAN_ENTER); + set_survey_timer(pmlmeext, 50); /* delay 50ms to protect nulldata(1) */ + } else { + mlmeext_set_scan_state(pmlmeext, SCAN_ENTER); + goto operation_by_state; + } + + break; + + case SCAN_ENTER: + /* + * HW register and DM setting for enter scan + */ + + rtw_phydm_ability_backup(padapter); + + sitesurvey_set_igi(padapter); + + /* config dynamic functions for off channel */ + rtw_phydm_func_for_offchannel(padapter); + /* set MSR to no link state */ + Set_MSR(padapter, _HW_STATE_NOLINK_); + val8 = 1; /* under site survey */ + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + + mlmeext_set_scan_state(pmlmeext, SCAN_PROCESS); + goto operation_by_state; + + case SCAN_PROCESS: + { + u8 scan_ch; + RT_SCAN_TYPE scan_type; + u8 next_state; + u32 scan_ms; + + #ifdef CONFIG_AUTO_CHNL_SEL_NHM + if ((ACS_ENABLE == GET_ACS_STATE(padapter)) && (0 != rtw_get_acs_channel(padapter))) { + ACS_OP acs_op = ACS_SELECT; + + rtw_hal_set_odm_var(padapter, HAL_ODM_AUTO_CHNL_SEL, &acs_op, _TRUE); + } + #endif + + next_state = sitesurvey_pick_ch_behavior(padapter, &scan_ch, &scan_type); + if (next_state != SCAN_PROCESS) { + #ifdef CONFIG_AUTO_CHNL_SEL_NHM + if (ACS_ENABLE == GET_ACS_STATE(padapter)) { + rtw_set_acs_channel(padapter, 0); + #ifdef DBG_AUTO_CHNL_SEL_NHM + DBG_871X("[ACS-"ADPT_FMT"]-set ch:%u\n", ADPT_ARG(padapter), rtw_get_acs_channel(padapter)); + #endif + } + #endif + + mlmeext_set_scan_state(pmlmeext, next_state); + goto operation_by_state; + } + + /* still SCAN_PROCESS state */ + if (0) + #ifdef CONFIG_P2P + DBG_871X(FUNC_ADPT_FMT" %s ch:%u (cnt:%u,idx:%d) at %dms, %c%c%c\n" + , FUNC_ADPT_ARG(padapter) + , mlmeext_scan_state_str(pmlmeext) + , scan_ch + , pwdinfo->find_phase_state_exchange_cnt, ss->channel_idx + , rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time) + , scan_type?'A':'P', ss->scan_mode?'A':'P' + , ss->ssid[0].SsidLength?'S':' ' + ); + #else + DBG_871X(FUNC_ADPT_FMT" %s ch:%u (idx:%d) at %dms, %c%c%c\n" + , FUNC_ADPT_ARG(padapter) + , mlmeext_scan_state_str(pmlmeext) + , scan_ch + , ss->channel_idx + , rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time) + , scan_type?'A':'P', ss->scan_mode?'A':'P' + , ss->ssid[0].SsidLength?'S':' ' + ); + #endif /* CONFIG_P2P */ + + #ifdef DBG_FIXED_CHAN + if (pmlmeext->fixed_chan != 0xff) + DBG_871X(FUNC_ADPT_FMT" fixed_chan:%u\n", pmlmeext->fixed_chan); + #endif + + site_survey(padapter, scan_ch, scan_type); + + #if defined(CONFIG_ATMEL_RC_PATCH) + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + scan_ms = 20; + else + scan_ms = 40; + #else + scan_ms = ss->scan_ch_ms; + #endif + + #if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL) + if (ss->is_sw_antdiv_bl_scan) + scan_ms = scan_ms/2; + #endif + + #if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) + { + struct noise_info info; + + info.bPauseDIG = _FALSE; + info.IGIValue = 0; + info.max_time = scan_ms/2; + info.chan = scan_ch; + rtw_hal_set_odm_var(padapter, HAL_ODM_NOISE_MONITOR, &info, _FALSE); + } + #endif + + set_survey_timer(pmlmeext, scan_ms); + break; + } + + #ifdef CONFIG_SCAN_BACKOP + case SCAN_BACKING_OP: + { + u8 back_ch, back_bw, back_ch_offset; + + if (rtw_get_ch_setting_union(padapter, &back_ch, &back_bw, &back_ch_offset) == 0) + rtw_warn_on(1); + + if (0) + DBG_871X(FUNC_ADPT_FMT" %s ch:%u, bw:%u, offset:%u at %dms\n" + , FUNC_ADPT_ARG(padapter) + , mlmeext_scan_state_str(pmlmeext) + , back_ch, back_bw, back_ch_offset + , rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time) + ); + + set_channel_bwmode(padapter, back_ch, back_ch_offset, back_bw); + + Set_MSR(padapter, (pmlmeinfo->state & 0x3)); + val8 = 0; /* survey done */ + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + + if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC)) { + sitesurvey_set_igi(padapter); + sitesurvey_ps_annc(adapter_to_dvobj(padapter), 0); + } + + mlmeext_set_scan_state(pmlmeext, SCAN_BACK_OP); + ss->backop_time = rtw_get_current_time(); + + if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_TX_RESUME)) { + int i; + + /* resume TX */ + for (i = 0; i < dvobj->iface_nums; i++) { + if (!dvobj->padapters[i]) + continue; + + rtw_os_xmit_schedule(dvobj->padapters[i]); + } + } + + goto operation_by_state; + } + + case SCAN_BACK_OP: + if (rtw_get_passing_time_ms(ss->backop_time) >= ss->backop_ms + || pmlmeext->scan_abort + ) { + mlmeext_set_scan_state(pmlmeext, SCAN_LEAVING_OP); + goto operation_by_state; + } + set_survey_timer(pmlmeext, 50); + break; + + case SCAN_LEAVING_OP: + /* + * prepare to leave operating channel + */ + + /* clear HW TX queue before scan */ + rtw_hal_set_hwreg(padapter, HW_VAR_CHECK_TXBUF, 0); + + if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC) + && sitesurvey_ps_annc(adapter_to_dvobj(padapter), 1) + ) { + mlmeext_set_scan_state(pmlmeext, SCAN_PS_ANNC_WAIT); + mlmeext_set_scan_next_state(pmlmeext, SCAN_LEAVE_OP); + set_survey_timer(pmlmeext, 50); /* delay 50ms to protect nulldata(1) */ + } else { + mlmeext_set_scan_state(pmlmeext, SCAN_LEAVE_OP); + goto operation_by_state; + } + + break; + + case SCAN_LEAVE_OP: + /* + * HW register and DM setting for enter scan + */ + + if (mlmeext_chk_scan_backop_flags(pmlmeext, SS_BACKOP_PS_ANNC)) + sitesurvey_set_igi(padapter); + + /* set MSR to no link state */ + Set_MSR(padapter, _HW_STATE_NOLINK_); + val8 = 1; //under site survey + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + + mlmeext_set_scan_state(pmlmeext, SCAN_PROCESS); + goto operation_by_state; + + #endif /* CONFIG_SCAN_BACKOP */ + + #if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL) + case SCAN_SW_ANTDIV_BL: + /* + * 20100721 + * For SW antenna diversity before link, it needs to switch to another antenna and scan again. + * It compares the scan result and select better one to do connection. + */ + ss->bss_cnt = 0; + ss->channel_idx = 0; + ss->is_sw_antdiv_bl_scan = 1; + + mlmeext_set_scan_next_state(pmlmeext, SCAN_PROCESS); + set_survey_timer(pmlmeext, ss->scan_ch_ms); + break; + #endif + + #ifdef CONFIG_P2P + case SCAN_TO_P2P_LISTEN: + /* + * Set the P2P State to the listen state of find phase + * and set the current channel to the listen channel + */ + set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_LISTEN); + + /* turn on phy-dynamic functions */ + rtw_phydm_ability_restore(padapter); + + sitesurvey_set_igi(padapter); + + mlmeext_set_scan_state(pmlmeext, SCAN_P2P_LISTEN); + _set_timer(&pwdinfo->find_phase_timer, (u32)((u32)pwdinfo->listen_dwell * 100)); + break; + + case SCAN_P2P_LISTEN: + mlmeext_set_scan_state(pmlmeext, SCAN_PROCESS); + ss->channel_idx = 0; + goto operation_by_state; + #endif /* CONFIG_P2P */ + + case SCAN_COMPLETE: + #ifdef CONFIG_P2P + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) + || rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH) + ) { + #ifdef CONFIG_CONCURRENT_MODE + if (pwdinfo->driver_interface == DRIVER_WEXT) { + if (check_buddy_fwstate(padapter, _FW_LINKED)) + _set_timer(&pwdinfo->ap_p2p_switch_timer, 500); + } + rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); + #else + rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); + #endif + } + rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE); + #endif /* CONFIG_P2P */ + + /* switch channel */ + survey_done_set_ch_bw(padapter); + + /* config MSR */ + Set_MSR(padapter, (pmlmeinfo->state & 0x3)); + val8 = 0; /* survey done */ + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + + /* turn on phy-dynamic functions */ + rtw_phydm_ability_restore(padapter); + + sitesurvey_set_igi(padapter); + + sitesurvey_ps_annc(adapter_to_dvobj(padapter), 0); + + /* apply rx ampdu setting */ + rtw_rx_ampdu_apply(padapter); + + mlmeext_set_scan_state(pmlmeext, SCAN_DISABLE); + + report_surveydone_event(padapter); + + issue_action_BSSCoexistPacket(padapter); + issue_action_BSSCoexistPacket(padapter); + issue_action_BSSCoexistPacket(padapter); + } + + return H2C_SUCCESS; +} + +u8 setauth_hdl(_adapter *padapter, unsigned char *pbuf) +{ + struct setauth_parm *pparm = (struct setauth_parm *)pbuf; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (pparm->mode < 4) + { + pmlmeinfo->auth_algo = pparm->mode; + } + + return H2C_SUCCESS; +} + +u8 setkey_hdl(_adapter *padapter, u8 *pbuf) +{ + u16 ctrl = 0; + s16 cam_id = 0; + struct setkey_parm *pparm = (struct setkey_parm *)pbuf; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + unsigned char null_addr[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + struct set_stakey_parm sta_pparm; + struct security_priv *psecuritypriv = &padapter->securitypriv; + u8 *addr; + bool used; + + //main tx key for wep. + if(pparm->set_tx) + pmlmeinfo->key_index = pparm->keyid; + + cam_id = rtw_camid_alloc(padapter, NULL, pparm->keyid, &used); + + if (cam_id < 0) + goto enable_mc; + + if (cam_id > 3) /* not default key, searched by A2 */ + addr = get_bssid(&padapter->mlmepriv); + else + addr = null_addr; + + #ifdef DYNAMIC_CAMID_ALLOC + /* cam entry searched is pairwise key */ + if (used == _TRUE && rtw_camid_is_gk(padapter, cam_id) == _FALSE) { + s16 camid_clr; + + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" group key with "MAC_FMT" id:%u the same key id as pairwise key\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(addr), pparm->keyid); + + /* HW has problem to distinguish this group key with existing pairwise key, stop HW enc and dec for BMC */ + rtw_camctl_set_flags(padapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH); + rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, NULL); + + /* clear group key */ + while ((camid_clr = rtw_camid_search(padapter, addr, -1, 1)) >= 0) { + DBG_871X_LEVEL(_drv_always_, "clear group key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(addr), camid_clr); + clear_cam_entry(padapter, camid_clr); + rtw_camid_free(padapter, camid_clr); + } + + goto enable_mc; + } + #endif + + ctrl = BIT(15) | BIT6 | ((pparm->algorithm) << 2) | pparm->keyid; + DBG_871X_LEVEL(_drv_always_, "set group key camid:%d, addr:"MAC_FMT", kid:%d, type:%s\n" + , cam_id, MAC_ARG(addr), pparm->keyid, security_type_str(pparm->algorithm)); + write_cam(padapter, cam_id, ctrl, addr, pparm->key); + + #ifdef DYNAMIC_CAMID_ALLOC + if (cam_id >=0 && cam_id <=3) + rtw_hal_set_hwreg(padapter, HW_VAR_SEC_DK_CFG, (u8*)_TRUE); + #endif + /* 8814au should set both broadcast and unicast CAM entry for WEP key in STA mode */ + if (_rtw_camctl_chk_cap(padapter, SEC_CAP_CHK_BMC) && is_wep_enc(psecuritypriv->dot11PrivacyAlgrthm)) { + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + sta_pparm.algorithm = pparm->algorithm; + sta_pparm.keyid = pparm->keyid; + _rtw_memcpy(sta_pparm.key, pparm->key, 16); + _rtw_memcpy(sta_pparm.addr, get_bssid(pmlmepriv), ETH_ALEN); + set_stakey_hdl(padapter, (u8 *) &sta_pparm); + } + +enable_mc: + //allow multicast packets to driver + rtw_hal_set_hwreg(padapter, HW_VAR_ON_RCR_AM, null_addr); + + return H2C_SUCCESS; +} + +u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf) +{ + u16 ctrl = 0; + s16 cam_id = 0; + bool used; + u8 ret = H2C_SUCCESS; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct set_stakey_parm *pparm = (struct set_stakey_parm *)pbuf; + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta; + + if(pparm->algorithm == _NO_PRIVACY_) + goto write_to_cam; + + psta = rtw_get_stainfo(pstapriv, pparm->addr); + if (!psta) { + DBG_871X_LEVEL(_drv_always_, "%s sta:"MAC_FMT" not found\n", __func__, MAC_ARG(pparm->addr)); + ret = H2C_REJECTED; + goto exit; + } + + pmlmeinfo->enc_algo = pparm->algorithm; + cam_id = rtw_camid_alloc(padapter, psta, 0, &used); + if (cam_id < 0) + goto exit; + + #ifdef DYNAMIC_CAMID_ALLOC + /* cam entry searched is group key */ + if (used == _TRUE && rtw_camid_is_gk(padapter, cam_id) == _TRUE) { + s16 camid_clr; + + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" pairwise key with "MAC_FMT" id:%u the same key id as group key\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(pparm->addr), pparm->keyid); + + /* HW has problem to distinguish this pairwise key with existing group key, stop HW enc and dec for BMC */ + rtw_camctl_set_flags(padapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH); + rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, NULL); + + /* clear group key */ + while ((camid_clr = rtw_camid_search(padapter, pparm->addr, -1, 1)) >= 0) { + DBG_871X_LEVEL(_drv_always_, "clear group key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(pparm->addr), camid_clr); + clear_cam_entry(padapter, camid_clr); + rtw_camid_free(padapter, camid_clr); + } + } + #endif + +write_to_cam: + if(pparm->algorithm == _NO_PRIVACY_) { + while ((cam_id = rtw_camid_search(padapter, pparm->addr, -1, -1)) >= 0) { + DBG_871X_LEVEL(_drv_always_, "clear key for addr:"MAC_FMT", camid:%d\n", MAC_ARG(pparm->addr), cam_id); + clear_cam_entry(padapter, cam_id); + rtw_camid_free(padapter,cam_id); + } + } else { + DBG_871X_LEVEL(_drv_always_, "set pairwise key camid:%d, addr:"MAC_FMT", kid:%d, type:%s\n", + cam_id, MAC_ARG(pparm->addr), pparm->keyid, security_type_str(pparm->algorithm)); + ctrl = BIT(15) | ((pparm->algorithm) << 2) | pparm->keyid; + write_cam(padapter, cam_id, ctrl, pparm->addr, pparm->key); + } + ret = H2C_SUCCESS_RSP; + +exit: + return ret; +} + +u8 add_ba_hdl(_adapter *padapter, unsigned char *pbuf) +{ + struct addBaReq_parm *pparm = (struct addBaReq_parm *)pbuf; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, pparm->addr); + + if(!psta) + return H2C_SUCCESS; + +#ifdef CONFIG_80211N_HT + if (((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && (pmlmeinfo->HT_enable)) || + ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)) + { + //pmlmeinfo->ADDBA_retry_count = 0; + //pmlmeinfo->candidate_tid_bitmap |= (0x1 << pparm->tid); + //psta->htpriv.candidate_tid_bitmap |= BIT(pparm->tid); + issue_addba_req(padapter, pparm->addr, (u8)pparm->tid); + //_set_timer(&pmlmeext->ADDBA_timer, ADDBA_TO); + _set_timer(&psta->addba_retry_timer, ADDBA_TO); + } +#ifdef CONFIG_TDLS + else if((psta->tdls_sta_state & TDLS_LINKED_STATE)&& + (psta->htpriv.ht_option==_TRUE) && + (psta->htpriv.ampdu_enable==_TRUE) ) + { + issue_addba_req(padapter, pparm->addr, (u8)pparm->tid); + _set_timer(&psta->addba_retry_timer, ADDBA_TO); + } +#endif //CONFIG + else + { + psta->htpriv.candidate_tid_bitmap &= ~BIT(pparm->tid); + } +#endif //CONFIG_80211N_HT + return H2C_SUCCESS; +} + + +u8 add_ba_rsp_hdl(_adapter *padapter, unsigned char *pbuf) +{ + struct addBaRsp_parm *pparm = (struct addBaRsp_parm *)pbuf; + u8 ret = _TRUE, i = 0, try_cnt = 3, wait_ms = 50; + struct recv_reorder_ctrl *preorder_ctrl; + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta; + + psta = rtw_get_stainfo(pstapriv, pparm->addr); + if (!psta) + goto exit; + + preorder_ctrl = &psta->recvreorder_ctrl[pparm->tid]; + ret = issue_addba_rsp_wait_ack(padapter, pparm->addr, pparm->tid, pparm->status, pparm->size, 3, 50); + + #ifdef CONFIG_UPDATE_INDICATE_SEQ_WHILE_PROCESS_ADDBA_REQ + /* status = 0 means accept this addba req, so update indicate seq = start_seq under this compile flag */ + if (pparm->status == 0) { + preorder_ctrl->indicate_seq = pparm->start_seq; + #ifdef DBG_RX_SEQ + DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, start_seq: %d\n", __func__, __LINE__, + preorder_ctrl->indicate_seq, pparm->start_seq); + #endif + } + #else + preorder_ctrl->indicate_seq = 0xffff; + #endif + + /* + * status = 0 means accept this addba req + * status = 37 means reject this addba req + */ + if (pparm->status == 0) { + preorder_ctrl->enable = _TRUE; + preorder_ctrl->ampdu_size = pparm->size; + } else if (pparm->status == 37) + preorder_ctrl->enable = _FALSE; + +exit: + return H2C_SUCCESS; +} + +u8 chk_bmc_sleepq_cmd(_adapter* padapter) +{ + struct cmd_obj *ph2c; + struct cmd_priv *pcmdpriv = &(padapter->cmdpriv); + u8 res = _SUCCESS; + +_func_enter_; + + if ((ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL) + { + res= _FAIL; + goto exit; + } + + init_h2fwcmd_w_parm_no_parm_rsp(ph2c, GEN_CMD_CODE(_ChkBMCSleepq)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + +exit: + +_func_exit_; + + return res; +} + +u8 set_tx_beacon_cmd(_adapter* padapter) +{ + struct cmd_obj *ph2c; + struct Tx_Beacon_param *ptxBeacon_parm; + struct cmd_priv *pcmdpriv = &(padapter->cmdpriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 res = _SUCCESS; + int len_diff = 0; + +_func_enter_; + + if ((ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL) + { + res= _FAIL; + goto exit; + } + + if ((ptxBeacon_parm = (struct Tx_Beacon_param *)rtw_zmalloc(sizeof(struct Tx_Beacon_param))) == NULL) + { + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res= _FAIL; + goto exit; + } + + _rtw_memcpy(&(ptxBeacon_parm->network), &(pmlmeinfo->network), sizeof(WLAN_BSSID_EX)); + + len_diff = update_hidden_ssid( + ptxBeacon_parm->network.IEs+_BEACON_IE_OFFSET_ + , ptxBeacon_parm->network.IELength-_BEACON_IE_OFFSET_ + , pmlmeinfo->hidden_ssid_mode + ); + ptxBeacon_parm->network.IELength += len_diff; + + init_h2fwcmd_w_parm_no_rsp(ph2c, ptxBeacon_parm, GEN_CMD_CODE(_TX_Beacon)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + + +exit: + +_func_exit_; + + return res; +} + + +u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf) +{ + u8 evt_code, evt_seq; + u16 evt_sz; + uint *peventbuf; + void (*event_callback)(_adapter *dev, u8 *pbuf); + struct evt_priv *pevt_priv = &(padapter->evtpriv); + + if (pbuf == NULL) + goto _abort_event_; + + peventbuf = (uint*)pbuf; + evt_sz = (u16)(*peventbuf&0xffff); + evt_seq = (u8)((*peventbuf>>24)&0x7f); + evt_code = (u8)((*peventbuf>>16)&0xff); + + + #ifdef CHECK_EVENT_SEQ + // checking event sequence... + if (evt_seq != (ATOMIC_READ(&pevt_priv->event_seq) & 0x7f) ) + { + RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("Evetn Seq Error! %d vs %d\n", (evt_seq & 0x7f), (ATOMIC_READ(&pevt_priv->event_seq) & 0x7f))); + + pevt_priv->event_seq = (evt_seq+1)&0x7f; + + goto _abort_event_; + } + #endif + + // checking if event code is valid + if (evt_code >= MAX_C2HEVT) + { + RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\nEvent Code(%d) mismatch!\n", evt_code)); + goto _abort_event_; + } + + // checking if event size match the event parm size + if ((wlanevents[evt_code].parmsize != 0) && + (wlanevents[evt_code].parmsize != evt_sz)) + { + + RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\nEvent(%d) Parm Size mismatch (%d vs %d)!\n", + evt_code, wlanevents[evt_code].parmsize, evt_sz)); + goto _abort_event_; + + } + + ATOMIC_INC(&pevt_priv->event_seq); + + peventbuf += 2; + + if(peventbuf) + { + event_callback = wlanevents[evt_code].event_callback; + event_callback(padapter, (u8*)peventbuf); + + pevt_priv->evt_done_cnt++; + } + + +_abort_event_: + + + return H2C_SUCCESS; + +} + +u8 h2c_msg_hdl(_adapter *padapter, unsigned char *pbuf) +{ + if(!pbuf) + return H2C_PARAMETERS_ERROR; + + return H2C_SUCCESS; +} + +u8 chk_bmc_sleepq_hdl(_adapter *padapter, unsigned char *pbuf) +{ +#ifdef CONFIG_AP_MODE + _irqL irqL; + struct sta_info *psta_bmc; + _list *xmitframe_plist, *xmitframe_phead; + struct xmit_frame *pxmitframe=NULL; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct sta_priv *pstapriv = &padapter->stapriv; + + //for BC/MC Frames + psta_bmc = rtw_get_bcmc_stainfo(padapter); + if(!psta_bmc) + return H2C_SUCCESS; + + if((pstapriv->tim_bitmap&BIT(0)) && (psta_bmc->sleepq_len>0)) + { +#ifndef CONFIG_PCI_HCI + rtw_msleep_os(10);// 10ms, ATIM(HIQ) Windows +#endif + //_enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL); + _enter_critical_bh(&pxmitpriv->lock, &irqL); + + xmitframe_phead = get_list_head(&psta_bmc->sleep_q); + xmitframe_plist = get_next(xmitframe_phead); + + while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) + { + pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); + + xmitframe_plist = get_next(xmitframe_plist); + + rtw_list_delete(&pxmitframe->list); + + psta_bmc->sleepq_len--; + if(psta_bmc->sleepq_len>0) + pxmitframe->attrib.mdata = 1; + else + pxmitframe->attrib.mdata = 0; + + pxmitframe->attrib.triggered=1; + + if (xmitframe_hiq_filter(pxmitframe) == _TRUE) + pxmitframe->attrib.qsel = QSLT_HIGH;//HIQ + + #if 0 + _exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL); + if(rtw_hal_xmit(padapter, pxmitframe) == _TRUE) + { + rtw_os_xmit_complete(padapter, pxmitframe); + } + _enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL); + #endif + rtw_hal_xmitframe_enqueue(padapter, pxmitframe); + } + + //_exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL); + _exit_critical_bh(&pxmitpriv->lock, &irqL); + + if (rtw_get_intf_type(padapter) != RTW_PCIE) { + /* check hi queue and bmc_sleepq */ + rtw_chk_hi_queue_cmd(padapter); + } + } +#endif + + return H2C_SUCCESS; +} + +u8 tx_beacon_hdl(_adapter *padapter, unsigned char *pbuf) +{ + if(send_beacon(padapter)==_FAIL) + { + DBG_871X("issue_beacon, fail!\n"); + return H2C_PARAMETERS_ERROR; + } + + + if (padapter->registrypriv.wifi_spec == 1) + return H2C_SUCCESS; + + /* tx bc/mc frames after update TIM */ + chk_bmc_sleepq_hdl(padapter, NULL); + + return H2C_SUCCESS; +} + +/* +* according to channel +* add/remove WLAN_BSSID_EX.IEs's ERP ie +* set WLAN_BSSID_EX.SupportedRates +* update WLAN_BSSID_EX.IEs's Supported Rate and Extended Supported Rate ie +*/ +void change_band_update_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 ch) +{ + u8 network_type,rate_len, total_rate_len,remainder_rate_len; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 erpinfo=0x4; + + if (ch >= 36) { + network_type = WIRELESS_11A; + total_rate_len = IEEE80211_NUM_OFDM_RATESLEN; + rtw_remove_bcn_ie(padapter, pnetwork, _ERPINFO_IE_); + } else { + network_type = WIRELESS_11BG; + total_rate_len = IEEE80211_CCK_RATE_LEN+IEEE80211_NUM_OFDM_RATESLEN; + rtw_add_bcn_ie(padapter, pnetwork, _ERPINFO_IE_, &erpinfo, 1); + } + + rtw_set_supported_rate(pnetwork->SupportedRates, network_type); + + UpdateBrateTbl(padapter, pnetwork->SupportedRates); + + if(total_rate_len > 8) + { + rate_len = 8; + remainder_rate_len = total_rate_len - 8; + } + else + { + rate_len = total_rate_len; + remainder_rate_len = 0; + } + + rtw_add_bcn_ie(padapter, pnetwork, _SUPPORTEDRATES_IE_, pnetwork->SupportedRates, rate_len); + + if(remainder_rate_len) + { + rtw_add_bcn_ie(padapter, pnetwork, _EXT_SUPPORTEDRATES_IE_, (pnetwork->SupportedRates+8), remainder_rate_len); + } + else + { + rtw_remove_bcn_ie(padapter, pnetwork, _EXT_SUPPORTEDRATES_IE_); + } + + pnetwork->Length = get_WLAN_BSSID_EX_sz(pnetwork); +} + +#ifdef CONFIG_CONCURRENT_MODE +sint check_buddy_mlmeinfo_state(_adapter *padapter, u32 state) +{ + PADAPTER pbuddy_adapter; + struct mlme_ext_priv *pbuddy_mlmeext; + struct mlme_ext_info *pbuddy_mlmeinfo; + + if(padapter == NULL) + return _FALSE; + + pbuddy_adapter = padapter->pbuddy_adapter; + + if(pbuddy_adapter == NULL) + return _FALSE; + + + pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; + pbuddy_mlmeinfo = &(pbuddy_mlmeext->mlmext_info); + + if((pbuddy_mlmeinfo->state&0x03) == state) + return _TRUE; + + return _FALSE; + +} +#endif /* CONFIG_CONCURRENT_MODE */ + +void rtw_join_done_chk_ch(_adapter *adapter, int join_res) +{ +#define DUMP_ADAPTERS_STATUS 0 + + struct dvobj_priv *dvobj; + _adapter *iface; + struct mlme_priv *mlme; + struct mlme_ext_priv *mlmeext; + u8 u_ch, u_offset, u_bw; + int i; + + dvobj = adapter_to_dvobj(adapter); + + if (DUMP_ADAPTERS_STATUS) { + DBG_871X(FUNC_ADPT_FMT" enter\n", FUNC_ADPT_ARG(adapter)); + dump_adapters_status(RTW_DBGDUMP , dvobj); + } + + if (join_res >= 0) { + if (rtw_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset) <= 0) { + dump_adapters_status(RTW_DBGDUMP , dvobj); + rtw_warn_on(1); + } + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + mlme = &iface->mlmepriv; + mlmeext = &iface->mlmeextpriv; + + if (!iface || iface == adapter) + continue; + + if (check_fwstate(mlme, WIFI_AP_STATE) + && check_fwstate(mlme, WIFI_ASOC_STATE) + ) { + bool is_grouped = rtw_is_chbw_grouped(u_ch, u_bw, u_offset + , mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset); + + if (is_grouped == _FALSE) { + /* handle AP which need to switch ch setting */ + + /* restore original bw, adjust bw by registry setting on target ch */ + mlmeext->cur_bwmode = mlme->ori_bw; + mlmeext->cur_channel = u_ch; + rtw_adjust_chbw(iface + , mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset); + + rtw_sync_chbw(&mlmeext->cur_channel, &mlmeext->cur_bwmode, &mlmeext->cur_ch_offset + , &u_ch, &u_bw, &u_offset); + + rtw_ap_update_bss_chbw(iface, &(mlmeext->mlmext_info.network) + , mlmeext->cur_channel, mlmeext->cur_bwmode, mlmeext->cur_ch_offset); + + _rtw_memcpy(&(mlme->cur_network.network), &(mlmeext->mlmext_info.network), sizeof(WLAN_BSSID_EX)); + + rtw_start_bss_hdl_after_chbw_decided(iface); + } + + update_beacon(iface, 0, NULL, _TRUE); + } + + clr_fwstate(mlme, WIFI_OP_CH_SWITCHING); + } + + #ifdef CONFIG_DFS_MASTER + rtw_dfs_master_status_apply(adapter, MLME_STA_CONNECTED); + #endif + } else { + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + mlme = &iface->mlmepriv; + mlmeext = &iface->mlmeextpriv; + + if (!iface || iface == adapter) + continue; + + if (check_fwstate(mlme, WIFI_AP_STATE) + && check_fwstate(mlme, WIFI_ASOC_STATE)) + update_beacon(iface, 0, NULL, _TRUE); + + clr_fwstate(mlme, WIFI_OP_CH_SWITCHING); + } + #ifdef CONFIG_DFS_MASTER + rtw_dfs_master_status_apply(adapter, MLME_STA_DISCONNECTED); + #endif + } + + if (rtw_get_ch_setting_union(adapter, &u_ch, &u_bw, &u_offset)) + set_channel_bwmode(adapter, u_ch, u_offset, u_bw); + + if (DUMP_ADAPTERS_STATUS) { + DBG_871X(FUNC_ADPT_FMT" exit\n", FUNC_ADPT_ARG(adapter)); + dump_adapters_status(RTW_DBGDUMP , dvobj); + } +} + +int rtw_chk_start_clnt_join(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset) +{ + bool chbw_allow = _TRUE; + bool connect_allow = _TRUE; + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + u8 cur_ch, cur_bw, cur_ch_offset; + u8 u_ch, u_offset, u_bw; + + u_ch = cur_ch = pmlmeext->cur_channel; + u_bw = cur_bw = pmlmeext->cur_bwmode; + u_offset = cur_ch_offset = pmlmeext->cur_ch_offset; + + if (!ch || !bw || !offset) { + connect_allow = _FALSE; + rtw_warn_on(1); + goto exit; + } + + if (cur_ch == 0) { + connect_allow = _FALSE; + DBG_871X_LEVEL(_drv_err_, FUNC_ADPT_FMT" cur_ch:%u\n" + , FUNC_ADPT_ARG(adapter), cur_ch); + rtw_warn_on(1); + goto exit; + } + DBG_871X(FUNC_ADPT_FMT" req: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset); + +#ifdef CONFIG_CONCURRENT_MODE +{ + struct dvobj_priv *dvobj; + _adapter *iface; + struct mlme_priv *mlme; + struct mlme_ext_priv *mlmeext; + u8 sta_num; + u8 ld_sta_num; + u8 lg_sta_num; + u8 ap_num; + u8 ld_ap_num; + int i; + + dvobj = adapter_to_dvobj(adapter); + + rtw_dev_iface_status_no_self(adapter, &sta_num, &ld_sta_num, &lg_sta_num, &ap_num, &ld_ap_num); + DBG_871X(FUNC_ADPT_FMT" ld_sta_num:%u, ap_num:%u\n" + , FUNC_ADPT_ARG(adapter), ld_sta_num, ap_num); + + if (!ld_sta_num && !ap_num) { + /* consider linking STA? */ + goto connect_allow_hdl; + } + + if (rtw_get_ch_setting_union_no_self(adapter, &u_ch, &u_bw, &u_offset) <= 0) { + dump_adapters_status(RTW_DBGDUMP , dvobj); + rtw_warn_on(1); + } + DBG_871X(FUNC_ADPT_FMT" union no self: %u,%u,%u\n" + , FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset); + + /* chbw_allow? */ + chbw_allow = rtw_is_chbw_grouped(pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset + , u_ch, u_bw, u_offset); + + DBG_871X(FUNC_ADPT_FMT" chbw_allow:%d\n" + , FUNC_ADPT_ARG(adapter), chbw_allow); + + if (chbw_allow == _TRUE) { + rtw_sync_chbw(&cur_ch, &cur_bw, &cur_ch_offset, &u_ch, &u_bw, &u_offset); + rtw_warn_on(cur_ch != pmlmeext->cur_channel); + rtw_warn_on(cur_bw != pmlmeext->cur_bwmode); + rtw_warn_on(cur_ch_offset != pmlmeext->cur_ch_offset); + goto connect_allow_hdl; + } + + /* chbw_allow is _FALSE, connect allow? */ + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + mlme = &iface->mlmepriv; + mlmeext = &iface->mlmeextpriv; + + #ifdef CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT + if (check_fwstate(mlme, WIFI_STATION_STATE) + && check_fwstate(mlme, WIFI_ASOC_STATE) + #if defined(CONFIG_P2P) + && rtw_p2p_chk_state(&(iface->wdinfo), P2P_STATE_NONE) + #endif + ) { + connect_allow = _FALSE; + break; + } + #endif /* CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT */ + } + DBG_871X(FUNC_ADPT_FMT" connect_allow:%d\n" + , FUNC_ADPT_ARG(adapter), connect_allow); + + if (connect_allow == _FALSE) + goto exit; + +connect_allow_hdl: + /* connect_allow == _TRUE */ + + #ifdef CONFIG_DFS_MASTER + rtw_dfs_master_status_apply(adapter, MLME_STA_CONNECTING); + #endif + + if (chbw_allow == _FALSE) { + u_ch = cur_ch; + u_bw = cur_bw; + u_offset = cur_ch_offset; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + mlme = &iface->mlmepriv; + mlmeext = &iface->mlmeextpriv; + + if (!iface || iface == adapter) + continue; + + if (check_fwstate(mlme, WIFI_AP_STATE) + && check_fwstate(mlme, WIFI_ASOC_STATE) + ) { + #ifdef CONFIG_SPCT_CH_SWITCH + if (1) + rtw_ap_inform_ch_switch(iface, pmlmeext->cur_channel , pmlmeext->cur_ch_offset); + else + #endif + rtw_sta_flush(iface, _FALSE); + + rtw_hal_set_hwreg(iface, HW_VAR_CHECK_TXBUF, 0); + set_fwstate(mlme, WIFI_OP_CH_SWITCHING); + } else if (check_fwstate(mlme, WIFI_STATION_STATE) + && check_fwstate(mlme, WIFI_ASOC_STATE) + ) { + rtw_disassoc_cmd(iface, 500, _FALSE); + rtw_indicate_disconnect(iface, 0, _FALSE); + rtw_free_assoc_resources(iface, 1); + } + } + } +} +#endif /* CONFIG_CONCURRENT_MODE */ + +exit: + + if (connect_allow == _TRUE) { + DBG_871X(FUNC_ADPT_FMT" union: %u,%u,%u\n", FUNC_ADPT_ARG(adapter), u_ch, u_bw, u_offset); + *ch = u_ch; + *bw = u_bw; + *offset = u_offset; + } + + return connect_allow == _TRUE ? _SUCCESS : _FAIL; +} + +/* Find union about ch, bw, ch_offset of all linked/linking interfaces */ +int _rtw_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset, bool include_self) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + _adapter *iface; + struct mlme_ext_priv *mlmeext; + int i; + u8 ch_ret = 0; + u8 bw_ret = CHANNEL_WIDTH_20; + u8 offset_ret = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + int num = 0; + + if (ch) *ch = 0; + if (bw) *bw = CHANNEL_WIDTH_20; + if (offset) *offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + + for (i = 0; iiface_nums; i++) { + iface = dvobj->padapters[i]; + mlmeext = &iface->mlmeextpriv; + + if (!check_fwstate(&iface->mlmepriv, _FW_LINKED|_FW_UNDER_LINKING)) + continue; + + if (check_fwstate(&iface->mlmepriv, WIFI_OP_CH_SWITCHING)) + continue; + + if (include_self == _FALSE && adapter == iface) + continue; + + if (num == 0) { + ch_ret = mlmeext->cur_channel; + bw_ret = mlmeext->cur_bwmode; + offset_ret = mlmeext->cur_ch_offset; + num++; + continue; + } + + if (ch_ret != mlmeext->cur_channel) { + num = 0; + break; + } + + if (bw_ret < mlmeext->cur_bwmode) { + bw_ret = mlmeext->cur_bwmode; + offset_ret = mlmeext->cur_ch_offset; + } else if (bw_ret == mlmeext->cur_bwmode && offset_ret != mlmeext->cur_ch_offset) { + num = 0; + break; + } + + num++; + } + + if (num) { + if (ch) *ch = ch_ret; + if (bw) *bw = bw_ret; + if (offset) *offset = offset_ret; + } + + return num; +} + +inline int rtw_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset) +{ + return _rtw_get_ch_setting_union(adapter, ch, bw, offset, 1); +} + +inline int rtw_get_ch_setting_union_no_self(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset) +{ + return _rtw_get_ch_setting_union(adapter, ch, bw, offset, 0); +} + +void _rtw_dev_iface_status(_adapter *adapter, u8 *sta_num, u8 *ld_sta_num, u8 *lg_sta_num + , u8 *ap_num, u8 *ld_ap_num, bool include_self) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + _adapter *iface; + struct mlme_ext_priv *mlmeext; + struct mlme_ext_info *mlmeextinfo; + int i; + u8 sta_num_ret = 0; + u8 ld_sta_num_ret = 0; + u8 lg_sta_num_ret = 0; + u8 ap_num_ret = 0; + u8 ld_ap_num_ret = 0; + + if (sta_num) + *sta_num = 0; + if (ld_sta_num) + *ld_sta_num = 0; + if (lg_sta_num) + *lg_sta_num = 0; + if (ap_num) + *ap_num = 0; + if (ld_ap_num) + *ld_ap_num = 0; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + + if (include_self == _FALSE && iface == adapter) + continue; + + mlmeext = &iface->mlmeextpriv; + + if (mlmeext_msr(mlmeext) == WIFI_FW_STATION_STATE) { + sta_num_ret++; + if (check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE) + ld_sta_num_ret++; + if (check_fwstate(&iface->mlmepriv, _FW_UNDER_LINKING) == _TRUE) + lg_sta_num_ret++; + } + + if (mlmeext_msr(mlmeext) == WIFI_FW_AP_STATE + && check_fwstate(&iface->mlmepriv, _FW_LINKED) == _TRUE + ) { + ap_num_ret++; + if (iface->stapriv.asoc_sta_count > 2) + ld_ap_num_ret++; + } + } + + if (sta_num) + *sta_num = sta_num_ret; + if (ld_sta_num) + *ld_sta_num = ld_sta_num_ret; + if (lg_sta_num) + *lg_sta_num = lg_sta_num_ret; + if (ap_num) + *ap_num = ap_num_ret; + if (ld_ap_num) + *ld_ap_num = ld_ap_num_ret; +} + +inline void rtw_dev_iface_status(_adapter *adapter, u8 *sta_num, u8 *ld_sta_num, u8 *lg_sta_num + , u8 *ap_num, u8 *ld_ap_num) +{ + return _rtw_dev_iface_status(adapter, sta_num, ld_sta_num, lg_sta_num, ap_num, ld_ap_num, 1); +} + +inline void rtw_dev_iface_status_no_self(_adapter *adapter, u8 *sta_num, u8 *ld_sta_num, u8 *lg_sta_num + , u8 *ap_num, u8 *ld_ap_num) +{ + return _rtw_dev_iface_status(adapter, sta_num, ld_sta_num, lg_sta_num, ap_num, ld_ap_num, 0); +} + +u8 set_ch_hdl(_adapter *padapter, u8 *pbuf) +{ + struct set_ch_parm *set_ch_parm; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + if(!pbuf) + return H2C_PARAMETERS_ERROR; + + set_ch_parm = (struct set_ch_parm *)pbuf; + + DBG_871X(FUNC_NDEV_FMT" ch:%u, bw:%u, ch_offset:%u\n", + FUNC_NDEV_ARG(padapter->pnetdev), + set_ch_parm->ch, set_ch_parm->bw, set_ch_parm->ch_offset); + + pmlmeext->cur_channel = set_ch_parm->ch; + pmlmeext->cur_ch_offset = set_ch_parm->ch_offset; + pmlmeext->cur_bwmode = set_ch_parm->bw; + + set_channel_bwmode(padapter, set_ch_parm->ch, set_ch_parm->ch_offset, set_ch_parm->bw); + + return H2C_SUCCESS; +} + +u8 set_chplan_hdl(_adapter *padapter, unsigned char *pbuf) +{ + struct SetChannelPlan_param *setChannelPlan_param; + struct mlme_priv *mlme = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + if(!pbuf) + return H2C_PARAMETERS_ERROR; + + setChannelPlan_param = (struct SetChannelPlan_param *)pbuf; + + if(!rtw_is_channel_plan_valid(setChannelPlan_param->channel_plan)) { + return H2C_PARAMETERS_ERROR; + } + + mlme->country_ent = setChannelPlan_param->country_ent; + mlme->ChannelPlan = setChannelPlan_param->channel_plan; + + pmlmeext->max_chan_nums = init_channel_set(padapter, setChannelPlan_param->channel_plan, pmlmeext->channel_set); + init_channel_list(padapter, pmlmeext->channel_set, pmlmeext->max_chan_nums, &pmlmeext->channel_list); + + rtw_hal_set_odm_var(padapter,HAL_ODM_REGULATION,NULL,_TRUE); + +#ifdef CONFIG_IOCTL_CFG80211 + if (padapter->rtw_wdev != NULL) + rtw_reg_notify_by_driver(padapter->rtw_wdev->wiphy); +#endif //CONFIG_IOCTL_CFG80211 + + return H2C_SUCCESS; +} + +u8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf) +{ + struct LedBlink_param *ledBlink_param; + + if(!pbuf) + return H2C_PARAMETERS_ERROR; + + ledBlink_param = (struct LedBlink_param *)pbuf; + + #ifdef CONFIG_LED_HANDLED_BY_CMD_THREAD + BlinkHandler((PLED_DATA)ledBlink_param->pLed); + #endif + + return H2C_SUCCESS; +} + +u8 set_csa_hdl(_adapter *padapter, unsigned char *pbuf) +{ +#ifdef CONFIG_DFS + struct SetChannelSwitch_param *setChannelSwitch_param; + u8 new_ch_no; + u8 gval8 = 0x00, sval8 = 0xff; + + if(!pbuf) + return H2C_PARAMETERS_ERROR; + + setChannelSwitch_param = (struct SetChannelSwitch_param *)pbuf; + new_ch_no = setChannelSwitch_param->new_ch_no; + + rtw_hal_get_hwreg(padapter, HW_VAR_TXPAUSE, &gval8); + + rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &sval8); + + DBG_871X("DFS detected! Swiching channel to %d!\n", new_ch_no); + SelectChannel(padapter, new_ch_no); + + rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &gval8); + + rtw_disassoc_cmd(padapter, 0, _FALSE); + rtw_indicate_disconnect(iface, 0, _FALSE); + rtw_free_assoc_resources(padapter, 1); + rtw_free_network_queue(padapter, _TRUE); + + if ( ((new_ch_no >= 52) && (new_ch_no <= 64)) ||((new_ch_no >= 100) && (new_ch_no <= 140)) ) { + DBG_871X("Switched to DFS band (ch %02x) again!!\n", new_ch_no); + } + + return H2C_SUCCESS; +#else + return H2C_REJECTED; +#endif //CONFIG_DFS + +} + +u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) +{ +#ifdef CONFIG_TDLS + _irqL irqL; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; +#ifdef CONFIG_TDLS_CH_SW + struct tdls_ch_switch *pchsw_info = &ptdlsinfo->chsw_info; +#endif + struct TDLSoption_param *TDLSoption; + struct sta_info *ptdls_sta = NULL; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + u8 survey_channel, i, min, option; + struct tdls_txmgmt txmgmt; + u32 setchtime, resp_sleep = 0, wait_time; + u8 zaddr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + u8 ret; + u8 doiqk; + + if (!pbuf) + return H2C_PARAMETERS_ERROR; + + TDLSoption = (struct TDLSoption_param *)pbuf; + option = TDLSoption->option; + + if (!_rtw_memcmp(TDLSoption->addr, zaddr, ETH_ALEN)) { + ptdls_sta = rtw_get_stainfo( &(padapter->stapriv), TDLSoption->addr ); + if (ptdls_sta == NULL) { + return H2C_REJECTED; + } + } else { + if (!(option == TDLS_RS_RCR)) + return H2C_REJECTED; + } + + //_enter_critical_bh(&(ptdlsinfo->hdl_lock), &irqL); + //DBG_871X("[%s] option:%d\n", __FUNCTION__, option); + + switch (option) { + case TDLS_ESTABLISHED: + { + /* As long as TDLS handshake success, we should set RCR_CBSSID_DATA bit to 0 */ + /* So we can receive all kinds of data frames. */ + u8 sta_band = 0; + + //leave ALL PS when TDLS is established + rtw_pwr_wakeup(padapter); + + rtw_hal_set_hwreg(padapter, HW_VAR_TDLS_WRCR, 0); + DBG_871X("Created Direct Link with "MAC_FMT"\n", MAC_ARG(ptdls_sta->hwaddr)); + + /* Set TDLS sta rate. */ + /* Update station supportRate */ + rtw_hal_update_sta_rate_mask(padapter, ptdls_sta); + if (pmlmeext->cur_channel > 14) { + if (ptdls_sta->ra_mask & 0xffff000) + sta_band |= WIRELESS_11_5N ; + + if (ptdls_sta->ra_mask & 0xff0) + sta_band |= WIRELESS_11A; + + /* 5G band */ + #ifdef CONFIG_80211AC_VHT + if (ptdls_sta->vhtpriv.vht_option) + sta_band = WIRELESS_11_5AC; + #endif + + } else { + if (ptdls_sta->ra_mask & 0xffff000) + sta_band |= WIRELESS_11_24N; + + if (ptdls_sta->ra_mask & 0xff0) + sta_band |= WIRELESS_11G; + + if (ptdls_sta->ra_mask & 0x0f) + sta_band |= WIRELESS_11B; + } + ptdls_sta->wireless_mode = sta_band; + ptdls_sta->raid = rtw_hal_networktype_to_raid(padapter,ptdls_sta); + set_sta_rate(padapter, ptdls_sta); + rtw_sta_media_status_rpt(padapter, ptdls_sta, 1); + /* Sta mode */ + rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, ptdls_sta,_TRUE); + break; + } + case TDLS_ISSUE_PTI: + ptdls_sta->tdls_sta_state |= TDLS_WAIT_PTR_STATE; + issue_tdls_peer_traffic_indication(padapter, ptdls_sta); + _set_timer(&ptdls_sta->pti_timer, TDLS_PTI_TIME); + break; +#ifdef CONFIG_TDLS_CH_SW + case TDLS_CH_SW_RESP: + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); + txmgmt.status_code = 0; + _rtw_memcpy(txmgmt.peer, ptdls_sta->hwaddr, ETH_ALEN); + + issue_nulldata(padapter, NULL, 1, 3, 3); + + DBG_871X("[TDLS ] issue tdls channel switch response\n"); + ret = issue_tdls_ch_switch_rsp(padapter, &txmgmt, _TRUE); + + /* If we receive TDLS_CH_SW_REQ at off channel which it's target is AP's channel */ + /* then we just SelectChannel to AP's channel*/ + if (padapter->mlmeextpriv.cur_channel == pchsw_info->off_ch_num) { + rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_END_TO_BASE_CHNL); + break; + } + + if (ret == _SUCCESS) + rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_TO_OFF_CHNL); + else + DBG_871X("[TDLS] issue_tdls_ch_switch_rsp wait ack fail !!!!!!!!!!\n"); + + break; + case TDLS_CH_SW_PREPARE: + pchsw_info->ch_sw_state |= TDLS_CH_SWITCH_PREPARE_STATE; + + /* to collect IQK info of off-chnl */ + doiqk = _TRUE; + rtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK, &doiqk); + set_channel_bwmode(padapter, pchsw_info->off_ch_num, pchsw_info->ch_offset, (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20); + doiqk = _FALSE; + rtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK, &doiqk); + + /* switch back to base-chnl */ + set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); + + rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_START); + + pchsw_info->ch_sw_state &= ~(TDLS_CH_SWITCH_PREPARE_STATE); + + break; + case TDLS_CH_SW_START: + rtw_tdls_set_ch_sw_oper_control(padapter, _TRUE); + break; + case TDLS_CH_SW_TO_OFF_CHNL: + issue_nulldata(padapter, NULL, 1, 3, 3); + + if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE)) + _set_timer(&ptdls_sta->ch_sw_timer, (u32)(ptdls_sta->ch_switch_timeout) /1000); + + if (rtw_tdls_do_ch_sw(padapter, ptdls_sta, TDLS_CH_SW_OFF_CHNL, pchsw_info->off_ch_num, + pchsw_info->ch_offset, (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20, ptdls_sta->ch_switch_time) == _SUCCESS) { + pchsw_info->ch_sw_state &= ~(TDLS_PEER_AT_OFF_STATE); + if (pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE) { + if (issue_nulldata_to_TDLS_peer_STA(ptdls_sta->padapter, ptdls_sta->hwaddr, 0, 1, 3) == _FAIL) + rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_TO_BASE_CHNL); + } + } + else { + u8 bcancelled; + + if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE)) + _cancel_timer(&ptdls_sta->ch_sw_timer,&bcancelled); + } + + + break; + case TDLS_CH_SW_END: + case TDLS_CH_SW_END_TO_BASE_CHNL: + rtw_tdls_set_ch_sw_oper_control(padapter, _FALSE); + _cancel_timer_ex(&ptdls_sta->ch_sw_timer); + _cancel_timer_ex(&ptdls_sta->stay_on_base_chnl_timer); + _cancel_timer_ex(&ptdls_sta->ch_sw_monitor_timer); +#if 0 + _rtw_memset(pHalData->tdls_ch_sw_iqk_info_base_chnl, 0x00, sizeof(pHalData->tdls_ch_sw_iqk_info_base_chnl)); + _rtw_memset(pHalData->tdls_ch_sw_iqk_info_off_chnl, 0x00, sizeof(pHalData->tdls_ch_sw_iqk_info_off_chnl)); +#endif + + if (option == TDLS_CH_SW_END_TO_BASE_CHNL) + rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_TO_BASE_CHNL); + + break; + case TDLS_CH_SW_TO_BASE_CHNL_UNSOLICITED: + case TDLS_CH_SW_TO_BASE_CHNL: + pchsw_info->ch_sw_state &= ~(TDLS_PEER_AT_OFF_STATE | TDLS_WAIT_CH_RSP_STATE); + + if (option == TDLS_CH_SW_TO_BASE_CHNL_UNSOLICITED) { + if (ptdls_sta != NULL) { + /* Send unsolicited channel switch rsp. to peer */ + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); + txmgmt.status_code = 0; + _rtw_memcpy(txmgmt.peer, ptdls_sta->hwaddr, ETH_ALEN); + issue_tdls_ch_switch_rsp(padapter, &txmgmt, _FALSE); + } + } + + if (rtw_tdls_do_ch_sw(padapter, ptdls_sta, TDLS_CH_SW_BASE_CHNL, pmlmeext->cur_channel, + pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode, ptdls_sta->ch_switch_time) == _SUCCESS) { + issue_nulldata(padapter, NULL, 0, 3, 3); + /* set ch sw monitor timer for responder */ + if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE)) + _set_timer(&ptdls_sta->ch_sw_monitor_timer, TDLS_CH_SW_MONITOR_TIMEOUT); + } + + break; +#endif + case TDLS_RS_RCR: + rtw_hal_set_hwreg(padapter, HW_VAR_TDLS_RS_RCR, 0); + DBG_871X("[TDLS] wirte REG_RCR, set bit6 on\n"); + break; + case TDLS_TEARDOWN_STA: + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); + txmgmt.status_code = 0; + _rtw_memcpy(txmgmt.peer, ptdls_sta->hwaddr, ETH_ALEN); + + issue_tdls_teardown(padapter, &txmgmt, _TRUE); + break; + case TDLS_TEARDOWN_STA_LOCALLY: +#ifdef CONFIG_TDLS_CH_SW + if (_rtw_memcmp(TDLSoption->addr, pchsw_info->addr, ETH_ALEN) == _TRUE) { + pchsw_info->ch_sw_state &= ~(TDLS_CH_SW_INITIATOR_STATE | + TDLS_CH_SWITCH_ON_STATE | + TDLS_PEER_AT_OFF_STATE); + rtw_tdls_set_ch_sw_oper_control(padapter, _FALSE); + _rtw_memset(pchsw_info->addr, 0x00, ETH_ALEN); + } +#endif + rtw_sta_media_status_rpt(padapter, ptdls_sta, 0); + free_tdls_sta(padapter, ptdls_sta); + break; + } + + //_exit_critical_bh(&(ptdlsinfo->hdl_lock), &irqL); + + return H2C_SUCCESS; +#else + return H2C_REJECTED; +#endif /* CONFIG_TDLS */ + +} + +u8 run_in_thread_hdl(_adapter *padapter, u8 *pbuf) +{ + struct RunInThread_param *p; + + + if (NULL == pbuf) + return H2C_PARAMETERS_ERROR; + p = (struct RunInThread_param*)pbuf; + + if (p->func) + p->func(p->context); + + return H2C_SUCCESS; +} + +u8 rtw_getmacreg_hdl(_adapter *padapter, u8 *pbuf) +{ + + struct readMAC_parm *preadmacparm = NULL; + u8 sz = 0; + u32 addr = 0; + u32 value = 0; + + if (!pbuf) + return H2C_PARAMETERS_ERROR; + + preadmacparm = (struct readMAC_parm *) pbuf; + sz = preadmacparm->len; + addr = preadmacparm->addr; + value = 0; + + switch (sz) { + case 1: + value = rtw_read8(padapter, addr); + break; + case 2: + value = rtw_read16(padapter, addr); + break; + case 4: + value = rtw_read32(padapter, addr); + break; + default: + DBG_871X("%s: Unknown size\n", __func__); + break; + } + DBG_871X("%s: addr:0x%02x valeu:0x%02x\n", __func__, addr, value); + + return H2C_SUCCESS; +} + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_mp.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_mp.c new file mode 100644 index 000000000..e1a91cf8b --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_mp.c @@ -0,0 +1,3506 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_MP_C_ +#include +#ifdef PLATFORM_FREEBSD +#include /* for RFHIGHPID */ +#endif + +#include "../hal/phydm/phydm_precomp.h" +#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8821A) +#include +#endif + +#ifdef CONFIG_MP_VHT_HW_TX_MODE +#define CEILING_POS(X) ((X - (int)(X)) > 0 ? (int)(X + 1) : (int)(X)) +#define CEILING_NEG(X) ((X - (int)(X)) < 0 ? (int)(X - 1) : (int)(X)) +#define ceil(X) (((X) > 0) ? CEILING_POS(X) : CEILING_NEG(X)) + +int rtfloor(float x) +{ +int i = x - 2; +while +(++i <= x - 1); +return i; +} +#endif + +#ifdef CONFIG_MP_INCLUDED + +u32 read_macreg(_adapter *padapter, u32 addr, u32 sz) +{ + u32 val = 0; + + switch(sz) + { + case 1: + val = rtw_read8(padapter, addr); + break; + case 2: + val = rtw_read16(padapter, addr); + break; + case 4: + val = rtw_read32(padapter, addr); + break; + default: + val = 0xffffffff; + break; + } + + return val; + +} + +void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz) +{ + switch(sz) + { + case 1: + rtw_write8(padapter, addr, (u8)val); + break; + case 2: + rtw_write16(padapter, addr, (u16)val); + break; + case 4: + rtw_write32(padapter, addr, val); + break; + default: + break; + } + +} + +u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask) +{ + return rtw_hal_read_bbreg(padapter, addr, bitmask); +} + +void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val) +{ + rtw_hal_write_bbreg(padapter, addr, bitmask, val); +} + +u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask) +{ + return rtw_hal_read_rfreg(padapter, rfpath, addr, bitmask); +} + +void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val) +{ + rtw_hal_write_rfreg(padapter, rfpath, addr, bitmask, val); +} + +u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr) +{ + return _read_rfreg(padapter, rfpath, addr, bRFRegOffsetMask); +} + +void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val) +{ + _write_rfreg(padapter, rfpath, addr, bRFRegOffsetMask, val); +} + +static void _init_mp_priv_(struct mp_priv *pmp_priv) +{ + WLAN_BSSID_EX *pnetwork; + + _rtw_memset(pmp_priv, 0, sizeof(struct mp_priv)); + + pmp_priv->mode = MP_OFF; + + pmp_priv->channel = 1; + pmp_priv->bandwidth = CHANNEL_WIDTH_20; + pmp_priv->prime_channel_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + pmp_priv->rateidx = RATE_1M; + pmp_priv->txpoweridx = 0x2A; + + pmp_priv->antenna_tx = ANTENNA_A; + pmp_priv->antenna_rx = ANTENNA_AB; + + pmp_priv->check_mp_pkt = 0; + + pmp_priv->tx_pktcount = 0; + + pmp_priv->rx_bssidpktcount=0; + pmp_priv->rx_pktcount = 0; + pmp_priv->rx_crcerrpktcount = 0; + + pmp_priv->network_macaddr[0] = 0x00; + pmp_priv->network_macaddr[1] = 0xE0; + pmp_priv->network_macaddr[2] = 0x4C; + pmp_priv->network_macaddr[3] = 0x87; + pmp_priv->network_macaddr[4] = 0x66; + pmp_priv->network_macaddr[5] = 0x55; + + pmp_priv->bSetRxBssid = _FALSE; + pmp_priv->bRTWSmbCfg = _FALSE; + pmp_priv->bloopback = _FALSE; + + pnetwork = &pmp_priv->mp_network.network; + _rtw_memcpy(pnetwork->MacAddress, pmp_priv->network_macaddr, ETH_ALEN); + + pnetwork->Ssid.SsidLength = 8; + _rtw_memcpy(pnetwork->Ssid.Ssid, "mp_871x", pnetwork->Ssid.SsidLength); + + pmp_priv->tx.payload = 2; +#ifdef CONFIG_80211N_HT + pmp_priv->tx.attrib.ht_en = 1; +#endif + +} + +#ifdef PLATFORM_WINDOWS +/* +void mp_wi_callback( + IN NDIS_WORK_ITEM* pwk_item, + IN PVOID cntx + ) +{ + _adapter* padapter =(_adapter *)cntx; + struct mp_priv *pmppriv=&padapter->mppriv; + struct mp_wi_cntx *pmp_wi_cntx=&pmppriv->wi_cntx; + + // Execute specified action. + if(pmp_wi_cntx->curractfunc != NULL) + { + LARGE_INTEGER cur_time; + ULONGLONG start_time, end_time; + NdisGetCurrentSystemTime(&cur_time); // driver version + start_time = cur_time.QuadPart/10; // The return value is in microsecond + + pmp_wi_cntx->curractfunc(padapter); + + NdisGetCurrentSystemTime(&cur_time); // driver version + end_time = cur_time.QuadPart/10; // The return value is in microsecond + + RT_TRACE(_module_mp_, _drv_info_, + ("WorkItemActType: %d, time spent: %I64d us\n", + pmp_wi_cntx->param.act_type, (end_time-start_time))); + } + + NdisAcquireSpinLock(&(pmp_wi_cntx->mp_wi_lock)); + pmp_wi_cntx->bmp_wi_progress= _FALSE; + NdisReleaseSpinLock(&(pmp_wi_cntx->mp_wi_lock)); + + if (pmp_wi_cntx->bmpdrv_unload) + { + NdisSetEvent(&(pmp_wi_cntx->mp_wi_evt)); + } + +} +*/ + +static int init_mp_priv_by_os(struct mp_priv *pmp_priv) +{ + struct mp_wi_cntx *pmp_wi_cntx; + + if (pmp_priv == NULL) return _FAIL; + + pmp_priv->rx_testcnt = 0; + pmp_priv->rx_testcnt1 = 0; + pmp_priv->rx_testcnt2 = 0; + + pmp_priv->tx_testcnt = 0; + pmp_priv->tx_testcnt1 = 0; + + pmp_wi_cntx = &pmp_priv->wi_cntx + pmp_wi_cntx->bmpdrv_unload = _FALSE; + pmp_wi_cntx->bmp_wi_progress = _FALSE; + pmp_wi_cntx->curractfunc = NULL; + + return _SUCCESS; +} +#endif + +#ifdef PLATFORM_LINUX +static int init_mp_priv_by_os(struct mp_priv *pmp_priv) +{ + int i, res; + struct mp_xmit_frame *pmp_xmitframe; + + if (pmp_priv == NULL) return _FAIL; + + _rtw_init_queue(&pmp_priv->free_mp_xmitqueue); + + pmp_priv->pallocated_mp_xmitframe_buf = NULL; + pmp_priv->pallocated_mp_xmitframe_buf = rtw_zmalloc(NR_MP_XMITFRAME * sizeof(struct mp_xmit_frame) + 4); + if (pmp_priv->pallocated_mp_xmitframe_buf == NULL) { + res = _FAIL; + goto _exit_init_mp_priv; + } + + pmp_priv->pmp_xmtframe_buf = pmp_priv->pallocated_mp_xmitframe_buf + 4 - ((SIZE_PTR) (pmp_priv->pallocated_mp_xmitframe_buf) & 3); + + pmp_xmitframe = (struct mp_xmit_frame*)pmp_priv->pmp_xmtframe_buf; + + for (i = 0; i < NR_MP_XMITFRAME; i++) + { + _rtw_init_listhead(&pmp_xmitframe->list); + rtw_list_insert_tail(&pmp_xmitframe->list, &pmp_priv->free_mp_xmitqueue.queue); + + pmp_xmitframe->pkt = NULL; + pmp_xmitframe->frame_tag = MP_FRAMETAG; + pmp_xmitframe->padapter = pmp_priv->papdater; + + pmp_xmitframe++; + } + + pmp_priv->free_mp_xmitframe_cnt = NR_MP_XMITFRAME; + + res = _SUCCESS; + +_exit_init_mp_priv: + + return res; +} +#endif + +static void mp_init_xmit_attrib(struct mp_tx *pmptx, PADAPTER padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + struct pkt_attrib *pattrib; + + // init xmitframe attribute + pattrib = &pmptx->attrib; + _rtw_memset(pattrib, 0, sizeof(struct pkt_attrib)); + _rtw_memset(pmptx->desc, 0, TXDESC_SIZE); + + pattrib->ether_type = 0x8712; + #if 0 + _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); + #endif + _rtw_memset(pattrib->dst, 0xFF, ETH_ALEN); + +// pattrib->dhcp_pkt = 0; +// pattrib->pktlen = 0; + pattrib->ack_policy = 0; +// pattrib->pkt_hdrlen = ETH_HLEN; + pattrib->hdrlen = WLAN_HDR_A3_LEN; + pattrib->subtype = WIFI_DATA; + pattrib->priority = 0; + pattrib->qsel = pattrib->priority; +// do_queue_select(padapter, pattrib); + pattrib->nr_frags = 1; + pattrib->encrypt = 0; + pattrib->bswenc = _FALSE; + pattrib->qos_en = _FALSE; + + pattrib->pktlen = 1500; + +#ifdef CONFIG_80211AC_VHT + if (pHalData->rf_type == RF_1T1R) + pattrib->raid = RATEID_IDX_VHT_1SS; + else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R) + pattrib->raid = RATEID_IDX_VHT_2SS; + else if (pHalData->rf_type == RF_3T3R) + pattrib->raid = RATEID_IDX_VHT_3SS; + else + pattrib->raid = RATEID_IDX_BGN_40M_1SS; +#endif +} + +s32 init_mp_priv(PADAPTER padapter) +{ + struct mp_priv *pmppriv = &padapter->mppriv; + PHAL_DATA_TYPE pHalData; + + pHalData = GET_HAL_DATA(padapter); + + _init_mp_priv_(pmppriv); + pmppriv->papdater = padapter; + pmppriv->mp_dm =0; + pmppriv->tx.stop = 1; + pmppriv->bSetTxPower = 0; /*for manually set tx power*/ + pmppriv->bTxBufCkFail = _FALSE; + pmppriv->pktInterval = 0; + pmppriv->pktLength = 1000; + + mp_init_xmit_attrib(&pmppriv->tx, padapter); + + switch (padapter->registrypriv.rf_config) { + case RF_1T1R: + pmppriv->antenna_tx = ANTENNA_A; + pmppriv->antenna_rx = ANTENNA_A; + break; + case RF_1T2R: + default: + pmppriv->antenna_tx = ANTENNA_A; + pmppriv->antenna_rx = ANTENNA_AB; + break; + case RF_2T2R: + case RF_2T2R_GREEN: + pmppriv->antenna_tx = ANTENNA_AB; + pmppriv->antenna_rx = ANTENNA_AB; + break; + case RF_2T4R: + pmppriv->antenna_tx = ANTENNA_BC; + pmppriv->antenna_rx = ANTENNA_ABCD; + break; + } + + pHalData->AntennaRxPath = pmppriv->antenna_rx; + pHalData->AntennaTxPath = pmppriv->antenna_tx; + + return _SUCCESS; +} + +void free_mp_priv(struct mp_priv *pmp_priv) +{ + if (pmp_priv->pallocated_mp_xmitframe_buf) { + rtw_mfree(pmp_priv->pallocated_mp_xmitframe_buf, 0); + pmp_priv->pallocated_mp_xmitframe_buf = NULL; + } + pmp_priv->pmp_xmtframe_buf = NULL; +} + + +static VOID PHY_IQCalibrate_default( + IN PADAPTER pAdapter, + IN BOOLEAN bReCovery + ) +{ + DBG_871X("%s\n", __func__); +} + +static VOID PHY_LCCalibrate_default( + IN PADAPTER pAdapter + ) +{ + DBG_871X("%s\n", __func__); +} + +static VOID PHY_SetRFPathSwitch_default( + IN PADAPTER pAdapter, + IN BOOLEAN bMain + ) +{ + DBG_871X("%s\n", __func__); +} + + +void mpt_InitHWConfig(PADAPTER Adapter) +{ + if (IS_HARDWARE_TYPE_8723B(Adapter)) { + // TODO: <20130114, Kordan> The following setting is only for DPDT and Fixed board type. + // TODO: A better solution is configure it according EFUSE during the run-time. + + PHY_SetMacReg(Adapter, 0x64, BIT20, 0x0); //0x66[4]=0 + PHY_SetMacReg(Adapter, 0x64, BIT24, 0x0); //0x66[8]=0 + PHY_SetMacReg(Adapter, 0x40, BIT4, 0x0); //0x40[4]=0 + PHY_SetMacReg(Adapter, 0x40, BIT3, 0x1); //0x40[3]=1 + PHY_SetMacReg(Adapter, 0x4C, BIT24, 0x1); //0x4C[24:23]=10 + PHY_SetMacReg(Adapter, 0x4C, BIT23, 0x0); //0x4C[24:23]=10 + PHY_SetBBReg(Adapter, 0x944, BIT1|BIT0, 0x3); //0x944[1:0]=11 + PHY_SetBBReg(Adapter, 0x930, bMaskByte0, 0x77); //0x930[7:0]=77 + PHY_SetMacReg(Adapter, 0x38, BIT11, 0x1); //0x38[11]=1 + + // TODO: <20130206, Kordan> The default setting is wrong, hard-coded here. + PHY_SetMacReg(Adapter, 0x778, 0x3, 0x3); // Turn off hardware PTA control (Asked by Scott) + PHY_SetMacReg(Adapter, 0x64, bMaskDWord, 0x36000000); //Fix BT S0/S1 + PHY_SetMacReg(Adapter, 0x948, bMaskDWord, 0x0); //Fix BT can't Tx + + /* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou) */ + PHY_SetBBReg(Adapter, 0xA00, BIT8, 0x0); /*0xA01[0] = 0*/ + } else if (IS_HARDWARE_TYPE_8821(Adapter)) { + /* <20131121, VincentL> Add for 8821AU DPDT setting and fix switching antenna issue (Asked by Rock) + <20131122, VincentL> Enable for all 8821A/8811AU (Asked by Alex)*/ + PHY_SetMacReg(Adapter, 0x4C, BIT23, 0x0); /*0x4C[23:22]=01*/ + PHY_SetMacReg(Adapter, 0x4C, BIT22, 0x1); /*0x4C[23:22]=01*/ + } else if (IS_HARDWARE_TYPE_8188ES(Adapter)) + PHY_SetMacReg(Adapter, 0x4C , BIT23, 0); /*select DPDT_P and DPDT_N as output pin*/ +#ifdef CONFIG_RTL8814A + else if (IS_HARDWARE_TYPE_8814A(Adapter)) + PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8814A, 0x2000); +#endif + /* + else if(IS_HARDWARE_TYPE_8822B(Adapter)) + { + PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8822B, 0x2000); + }*/ +} + +#ifdef CONFIG_RTL8188E +#define PHY_IQCalibrate(a,b) PHY_IQCalibrate_8188E(a,b) +#define PHY_LCCalibrate(a) PHY_LCCalibrate_8188E(&(GET_HAL_DATA(a)->odmpriv)) +#define PHY_SetRFPathSwitch(a,b) PHY_SetRFPathSwitch_8188E(a,b) +#endif + +#ifdef CONFIG_RTL8814A +#define PHY_IQCalibrate(a,b) PHY_IQCalibrate_8814A(&(GET_HAL_DATA(a)->odmpriv), b) +#define PHY_LCCalibrate(a) PHY_LCCalibrate_8814A(&(GET_HAL_DATA(a)->odmpriv)) +#define PHY_SetRFPathSwitch(a,b) PHY_SetRFPathSwitch_8814A(a,b) +#endif /* CONFIG_RTL8814A */ + +#ifdef CONFIG_RTL8812A +#define PHY_IQCalibrate(_Adapter, b) PHY_IQCalibrate_8812A(_Adapter, b) +#define PHY_LCCalibrate(_Adapter) PHY_LCCalibrate_8812A(&(GET_HAL_DATA(_Adapter)->odmpriv)) +#define PHY_SetRFPathSwitch(_Adapter, b) PHY_SetRFPathSwitch_8812A(_Adapter, b) +#endif + +#ifdef CONFIG_RTL8821A +#define PHY_IQCalibrate(_Adapter, b) PHY_IQCalibrate_8821A(&(GET_HAL_DATA(_Adapter)->odmpriv), b) +#define PHY_LCCalibrate(_Adapter) PHY_LCCalibrate_8821A(&(GET_HAL_DATA(_Adapter)->odmpriv)) +#define PHY_SetRFPathSwitch(_Adapter, b) PHY_SetRFPathSwitch_8812A(_Adapter, b) +#endif + +#ifdef CONFIG_RTL8192E +#define PHY_IQCalibrate(a,b) PHY_IQCalibrate_8192E(a,b) +#define PHY_LCCalibrate(a) PHY_LCCalibrate_8192E(&(GET_HAL_DATA(a)->odmpriv)) +#define PHY_SetRFPathSwitch(a,b) PHY_SetRFPathSwitch_8192E(a,b) +#endif //CONFIG_RTL8812A_8821A + +#ifdef CONFIG_RTL8723B +static void PHY_IQCalibrate(PADAPTER padapter, u8 bReCovery) +{ + PHAL_DATA_TYPE pHalData; + u8 b2ant; //false:1ant, true:2-ant + u8 RF_Path; //0:S1, 1:S0 + + pHalData = GET_HAL_DATA(padapter); + b2ant = pHalData->EEPROMBluetoothAntNum==Ant_x2?_TRUE:_FALSE; + + PHY_IQCalibrate_8723B(padapter, bReCovery, _FALSE, b2ant, pHalData->ant_path); +} + + +#define PHY_LCCalibrate(a) PHY_LCCalibrate_8723B(&(GET_HAL_DATA(a)->odmpriv)) +#define PHY_SetRFPathSwitch(a,b) PHY_SetRFPathSwitch_8723B(a,b) +#endif + +#ifdef CONFIG_RTL8703B +static void PHY_IQCalibrate(PADAPTER padapter, u8 bReCovery) +{ + PHY_IQCalibrate_8703B(padapter, bReCovery); +} + + +#define PHY_LCCalibrate(a) PHY_LCCalibrate_8703B(&(GET_HAL_DATA(a)->odmpriv)) +#define PHY_SetRFPathSwitch(a, b) +#endif + +#ifdef CONFIG_RTL8188F +static void PHY_IQCalibrate(PADAPTER padapter, u8 bReCovery) +{ + PHY_IQCalibrate_8188F(padapter, bReCovery, _FALSE); +} + + +#define PHY_LCCalibrate(a) PHY_LCCalibrate_8188F(&(GET_HAL_DATA(a)->odmpriv)) +#define PHY_SetRFPathSwitch(a, b) PHY_SetRFPathSwitch_8188F(a, b) +#endif + +s32 +MPT_InitializeAdapter( + IN PADAPTER pAdapter, + IN u8 Channel + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + s32 rtStatus = _SUCCESS; + PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx; + u32 ledsetting; + struct mlme_priv *pmlmepriv = &pAdapter->mlmepriv; + + pMptCtx->bMptDrvUnload = _FALSE; + pMptCtx->bMassProdTest = _FALSE; + pMptCtx->bMptIndexEven = _TRUE; //default gain index is -6.0db + pMptCtx->h2cReqNum = 0x0; + //init for BT MP +#if defined(CONFIG_RTL8723B) + pMptCtx->bMPh2c_timeout = _FALSE; + pMptCtx->MptH2cRspEvent = _FALSE; + pMptCtx->MptBtC2hEvent = _FALSE; + _rtw_init_sema(&pMptCtx->MPh2c_Sema, 0); + _init_timer( &pMptCtx->MPh2c_timeout_timer, pAdapter->pnetdev, MPh2c_timeout_handle, pAdapter ); +#endif + + mpt_InitHWConfig(pAdapter); + +#ifdef CONFIG_RTL8723B + rtl8723b_InitAntenna_Selection(pAdapter); + if (IS_HARDWARE_TYPE_8723B(pAdapter)) + { + + /* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou)*/ + PHY_SetBBReg(pAdapter, 0xA00, BIT8, 0x0); + PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /*default use Main*/ + /*<20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten. */ + if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)) + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E); + else + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E); + } + /*set ant to wifi side in mp mode*/ + rtw_write16(pAdapter, 0x870, 0x300); + rtw_write16(pAdapter, 0x860, 0x110); +#endif + + pMptCtx->bMptWorkItemInProgress = _FALSE; + pMptCtx->CurrMptAct = NULL; + pMptCtx->MptRfPath = ODM_RF_PATH_A; + //------------------------------------------------------------------------- + // Don't accept any packets + rtw_write32(pAdapter, REG_RCR, 0); + + //ledsetting = rtw_read32(pAdapter, REG_LEDCFG0); + //rtw_write32(pAdapter, REG_LEDCFG0, ledsetting & ~LED0DIS); + + //rtw_write32(pAdapter, REG_LEDCFG0, 0x08080); + ledsetting = rtw_read32(pAdapter, REG_LEDCFG0); + + + PHY_LCCalibrate(pAdapter); + PHY_IQCalibrate(pAdapter, _FALSE); + //dm_CheckTXPowerTracking(&pHalData->odmpriv); //trigger thermal meter + + PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); //default use Main + + pMptCtx->backup0xc50 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0); + pMptCtx->backup0xc58 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0); + pMptCtx->backup0xc30 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_RxDetector1, bMaskByte0); + pMptCtx->backup0x52_RF_A = (u1Byte)PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0); + pMptCtx->backup0x52_RF_B = (u1Byte)PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0); +#ifdef CONFIG_RTL8188E + rtw_write32(pAdapter, REG_MACID_NO_LINK_0, 0x0); + rtw_write32(pAdapter, REG_MACID_NO_LINK_1, 0x0); +#endif + return rtStatus; +} + +/*----------------------------------------------------------------------------- + * Function: MPT_DeInitAdapter() + * + * Overview: Extra DeInitialization for Mass Production Test. + * + * Input: PADAPTER pAdapter + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/08/2007 MHC Create Version 0. + * 05/18/2007 MHC Add normal driver MPHalt code. + * + *---------------------------------------------------------------------------*/ +VOID +MPT_DeInitAdapter( + IN PADAPTER pAdapter + ) +{ + PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx; + + pMptCtx->bMptDrvUnload = _TRUE; + #if defined(CONFIG_RTL8723B) + _rtw_free_sema(&(pMptCtx->MPh2c_Sema)); + _cancel_timer_ex( &pMptCtx->MPh2c_timeout_timer); + #endif + #if defined(CONFIG_RTL8723B) + PHY_SetBBReg(pAdapter,0xA01, BIT0, 1); ///suggestion by jerry for MP Rx. + #endif +#if 0 // for Windows + PlatformFreeWorkItem( &(pMptCtx->MptWorkItem) ); + + while(pMptCtx->bMptWorkItemInProgress) + { + if(NdisWaitEvent(&(pMptCtx->MptWorkItemEvent), 50)) + { + break; + } + } + NdisFreeSpinLock( &(pMptCtx->MptWorkItemSpinLock) ); +#endif +} + +static u8 mpt_ProStartTest(PADAPTER padapter) +{ + PMPT_CONTEXT pMptCtx = &padapter->mppriv.MptCtx; + + pMptCtx->bMassProdTest = _TRUE; + pMptCtx->bStartContTx = _FALSE; + pMptCtx->bCckContTx = _FALSE; + pMptCtx->bOfdmContTx = _FALSE; + pMptCtx->bSingleCarrier = _FALSE; + pMptCtx->bCarrierSuppression = _FALSE; + pMptCtx->bSingleTone = _FALSE; + pMptCtx->HWTxmode = PACKETS_TX; + + return _SUCCESS; +} + +/* + * General use + */ +s32 SetPowerTracking(PADAPTER padapter, u8 enable) +{ + + hal_mpt_SetPowerTracking(padapter, enable); + return 0; +} + +void GetPowerTracking(PADAPTER padapter, u8 *enable) +{ + hal_mpt_GetPowerTracking(padapter, enable); +} + +static void disable_dm(PADAPTER padapter) +{ + u8 v8; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + + //3 1. disable firmware dynamic mechanism + // disable Power Training, Rate Adaptive + v8 = rtw_read8(padapter, REG_BCN_CTRL); + v8 &= ~EN_BCN_FUNCTION; + rtw_write8(padapter, REG_BCN_CTRL, v8); + + //3 2. disable driver dynamic mechanism + rtw_phydm_func_disable_all(padapter); + + // enable APK, LCK and IQK but disable power tracking + pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _FALSE; + rtw_phydm_func_set(padapter, ODM_RF_CALIBRATION); + +//#ifdef CONFIG_BT_COEXIST +// rtw_btcoex_Switch(padapter, 0); //remove for BT MP Down. +//#endif +} + + +void MPT_PwrCtlDM(PADAPTER padapter, u32 bstart) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + + if (bstart==1){ + DBG_871X("in MPT_PwrCtlDM start\n"); + rtw_phydm_func_set(padapter, ODM_RF_TX_PWR_TRACK | ODM_RF_CALIBRATION); + + pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE; + padapter->mppriv.mp_dm =1; + + }else{ + DBG_871X("in MPT_PwrCtlDM stop \n"); + disable_dm(padapter); + pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _FALSE; + padapter->mppriv.mp_dm = 0; + { + TXPWRTRACK_CFG c; + u1Byte chnl =0 ; + _rtw_memset(&c, 0, sizeof(TXPWRTRACK_CFG)); + ConfigureTxpowerTrack(pDM_Odm, &c); + ODM_ClearTxPowerTrackingState(pDM_Odm); + if (*c.ODM_TxPwrTrackSetPwr) { + if (pDM_Odm->SupportICType == ODM_RTL8188F) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, chnl); + else { + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, ODM_RF_PATH_A, chnl); + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, ODM_RF_PATH_B, chnl); + } + } + } + } + +} + + +u32 mp_join(PADAPTER padapter,u8 mode) +{ + WLAN_BSSID_EX bssid; + struct sta_info *psta; + u32 length; + u8 val8; + _irqL irqL; + s32 res = _SUCCESS; + + struct mp_priv *pmppriv = &padapter->mppriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wlan_network *tgt_network = &pmlmepriv->cur_network; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network)); + +#ifdef CONFIG_IOCTL_CFG80211 + struct wireless_dev *pwdev = padapter->rtw_wdev; +#endif //#ifdef CONFIG_IOCTL_CFG80211 + // 1. initialize a new WLAN_BSSID_EX + _rtw_memset(&bssid, 0, sizeof(WLAN_BSSID_EX)); + DBG_8192C("%s ,pmppriv->network_macaddr=%x %x %x %x %x %x \n",__func__, + pmppriv->network_macaddr[0],pmppriv->network_macaddr[1],pmppriv->network_macaddr[2],pmppriv->network_macaddr[3],pmppriv->network_macaddr[4],pmppriv->network_macaddr[5]); + _rtw_memcpy(bssid.MacAddress, pmppriv->network_macaddr, ETH_ALEN); + + if( mode==WIFI_FW_ADHOC_STATE ){ + bssid.Ssid.SsidLength = strlen("mp_pseudo_adhoc"); + _rtw_memcpy(bssid.Ssid.Ssid, (u8*)"mp_pseudo_adhoc", bssid.Ssid.SsidLength); + bssid.InfrastructureMode = Ndis802_11IBSS; + bssid.NetworkTypeInUse = Ndis802_11DS; + bssid.IELength = 0; + bssid.Configuration.DSConfig=pmppriv->channel; + + }else if(mode==WIFI_FW_STATION_STATE){ + bssid.Ssid.SsidLength = strlen("mp_pseudo_STATION"); + _rtw_memcpy(bssid.Ssid.Ssid, (u8*)"mp_pseudo_STATION", bssid.Ssid.SsidLength); + bssid.InfrastructureMode = Ndis802_11Infrastructure; + bssid.NetworkTypeInUse = Ndis802_11DS; + bssid.IELength = 0; + } + + length = get_WLAN_BSSID_EX_sz(&bssid); + if (length % 4) + bssid.Length = ((length >> 2) + 1) << 2; //round up to multiple of 4 bytes. + else + bssid.Length = length; + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) + goto end_of_mp_start_test; + + //init mp_start_test status + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { + rtw_disassoc_cmd(padapter, 500, _TRUE); + rtw_indicate_disconnect(padapter, 0, _FALSE); + rtw_free_assoc_resources(padapter, 1); + } + pmppriv->prev_fw_state = get_fwstate(pmlmepriv); + pmlmepriv->fw_state = WIFI_MP_STATE; + + set_fwstate(pmlmepriv, _FW_UNDER_LINKING); + + //3 2. create a new psta for mp driver + //clear psta in the cur_network, if any + psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress); + if (psta) rtw_free_stainfo(padapter, psta); + + psta = rtw_alloc_stainfo(&padapter->stapriv, bssid.MacAddress); + if (psta == NULL) { + RT_TRACE(_module_mp_, _drv_err_, ("mp_start_test: Can't alloc sta_info!\n")); + pmlmepriv->fw_state = pmppriv->prev_fw_state; + res = _FAIL; + goto end_of_mp_start_test; + } + set_fwstate(pmlmepriv,WIFI_ADHOC_MASTER_STATE); + //3 3. join psudo AdHoc + tgt_network->join_res = 1; + tgt_network->aid = psta->aid = 1; + + _rtw_memcpy(&padapter->registrypriv.dev_network, &bssid, length); + rtw_update_registrypriv_dev_network(padapter); + _rtw_memcpy(&tgt_network->network,&padapter->registrypriv.dev_network, padapter->registrypriv.dev_network.Length); + _rtw_memcpy(pnetwork,&padapter->registrypriv.dev_network, padapter->registrypriv.dev_network.Length); + + rtw_indicate_connect(padapter); + _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); + set_fwstate(pmlmepriv,_FW_LINKED); + +end_of_mp_start_test: + + _exit_critical_bh(&pmlmepriv->lock, &irqL); + + if(1) //(res == _SUCCESS) + { + // set MSR to WIFI_FW_ADHOC_STATE + if( mode==WIFI_FW_ADHOC_STATE ){ + + val8 = rtw_read8(padapter, MSR) & 0xFC; // 0x0102 + val8 |= WIFI_FW_ADHOC_STATE; + rtw_write8(padapter, MSR, val8); // Link in ad hoc network + } + else { + Set_MSR(padapter, WIFI_FW_STATION_STATE); + + DBG_8192C("%s , pmppriv->network_macaddr =%x %x %x %x %x %x\n",__func__, + pmppriv->network_macaddr[0],pmppriv->network_macaddr[1],pmppriv->network_macaddr[2],pmppriv->network_macaddr[3],pmppriv->network_macaddr[4],pmppriv->network_macaddr[5]); + + rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmppriv->network_macaddr); + } + } + + return res; +} +//This function initializes the DUT to the MP test mode +s32 mp_start_test(PADAPTER padapter) +{ + struct mp_priv *pmppriv = &padapter->mppriv; + s32 res = _SUCCESS; + + padapter->registrypriv.mp_mode = 1; + + //3 disable dynamic mechanism + disable_dm(padapter); + #ifdef CONFIG_RTL8814A + rtl8814_InitHalDm(padapter); + #endif /* CONFIG_RTL8814A */ + #ifdef CONFIG_RTL8812A + rtl8812_InitHalDm(padapter); + #endif /* CONFIG_RTL8812A */ + #ifdef CONFIG_RTL8723B + rtl8723b_InitHalDm(padapter); + #endif /* CONFIG_RTL8723B */ + #ifdef CONFIG_RTL8703B + rtl8703b_InitHalDm(padapter); + #endif /* CONFIG_RTL8703B */ + #ifdef CONFIG_RTL8192E + rtl8192e_InitHalDm(padapter); + #endif + #ifdef CONFIG_RTL8188F + rtl8188f_InitHalDm(padapter); + #endif + + //3 0. update mp_priv + + if (padapter->registrypriv.rf_config == RF_MAX_TYPE) { +// switch (phal->rf_type) { + switch (GET_RF_TYPE(padapter)) { + case RF_1T1R: + pmppriv->antenna_tx = ANTENNA_A; + pmppriv->antenna_rx = ANTENNA_A; + break; + case RF_1T2R: + default: + pmppriv->antenna_tx = ANTENNA_A; + pmppriv->antenna_rx = ANTENNA_AB; + break; + case RF_2T2R: + case RF_2T2R_GREEN: + pmppriv->antenna_tx = ANTENNA_AB; + pmppriv->antenna_rx = ANTENNA_AB; + break; + case RF_2T4R: + pmppriv->antenna_tx = ANTENNA_AB; + pmppriv->antenna_rx = ANTENNA_ABCD; + break; + } + } + + mpt_ProStartTest(padapter); + + mp_join(padapter,WIFI_FW_ADHOC_STATE); + + return res; +} +//------------------------------------------------------------------------------ +//This function change the DUT from the MP test mode into normal mode +void mp_stop_test(PADAPTER padapter) +{ + struct mp_priv *pmppriv = &padapter->mppriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wlan_network *tgt_network = &pmlmepriv->cur_network; + struct sta_info *psta; + + _irqL irqL; + + if(pmppriv->mode==MP_ON) + { + pmppriv->bSetTxPower=0; + _enter_critical_bh(&pmlmepriv->lock, &irqL); + if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE) + goto end_of_mp_stop_test; + + //3 1. disconnect psudo AdHoc + rtw_indicate_disconnect(padapter, 0, _FALSE); + + //3 2. clear psta used in mp test mode. +// rtw_free_assoc_resources(padapter, 1); + psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress); + if (psta) rtw_free_stainfo(padapter, psta); + + //3 3. return to normal state (default:station mode) + pmlmepriv->fw_state = pmppriv->prev_fw_state; // WIFI_STATION_STATE; + + //flush the cur_network + _rtw_memset(tgt_network, 0, sizeof(struct wlan_network)); + + _clr_fwstate_(pmlmepriv, WIFI_MP_STATE); + +end_of_mp_stop_test: + + _exit_critical_bh(&pmlmepriv->lock, &irqL); + + #ifdef CONFIG_RTL8812A + rtl8812_InitHalDm(padapter); + #endif + #ifdef CONFIG_RTL8723B + rtl8723b_InitHalDm(padapter); + #endif + #ifdef CONFIG_RTL8703B + rtl8703b_InitHalDm(padapter); + #endif + #ifdef CONFIG_RTL8192E + rtl8192e_InitHalDm(padapter); + #endif + #ifdef CONFIG_RTL8188F + rtl8188f_InitHalDm(padapter); + #endif + } +} +/*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/ +#if 0 +//#ifdef CONFIG_USB_HCI +static VOID mpt_AdjustRFRegByRateByChan92CU(PADAPTER pAdapter, u8 RateIdx, u8 Channel, u8 BandWidthID) +{ + u8 eRFPath; + u32 rfReg0x26; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + + if (RateIdx < MPT_RATE_6M) { // CCK rate,for 88cu + rfReg0x26 = 0xf400; + } + else if ((RateIdx >= MPT_RATE_6M) && (RateIdx <= MPT_RATE_54M)) {// OFDM rate,for 88cu + if ((4 == Channel) || (8 == Channel) || (12 == Channel)) + rfReg0x26 = 0xf000; + else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel)) + rfReg0x26 = 0xf400; + else + rfReg0x26 = 0x4f200; + } + else if ((RateIdx >= MPT_RATE_MCS0) && (RateIdx <= MPT_RATE_MCS15)) {// MCS 20M ,for 88cu // MCS40M rate,for 88cu + + if (CHANNEL_WIDTH_20 == BandWidthID) { + if ((4 == Channel) || (8 == Channel)) + rfReg0x26 = 0xf000; + else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel)) + rfReg0x26 = 0xf400; + else + rfReg0x26 = 0x4f200; + } + else{ + if ((4 == Channel) || (8 == Channel)) + rfReg0x26 = 0xf000; + else if ((5 == Channel) || (7 == Channel)) + rfReg0x26 = 0xf400; + else + rfReg0x26 = 0x4f200; + } + } + +// RT_TRACE(COMP_CMD, DBG_LOUD, ("\n mpt_AdjustRFRegByRateByChan92CU():Chan:%d Rate=%d rfReg0x26:0x%08x\n",Channel, RateIdx,rfReg0x26)); + for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) { + write_rfreg(pAdapter, eRFPath, RF_SYN_G2, rfReg0x26); + } +} +#endif +/*----------------------------------------------------------------------------- + * Function: mpt_SwitchRfSetting + * + * Overview: Change RF Setting when we siwthc channel/rate/BW for MP. + * + * Input: IN PADAPTER pAdapter + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 01/08/2009 MHC Suggestion from SD3 Willis for 92S series. + * 01/09/2009 MHC Add CCK modification for 40MHZ. Suggestion from SD3. + * + *---------------------------------------------------------------------------*/ +static void mpt_SwitchRfSetting(PADAPTER pAdapter) +{ + hal_mpt_SwitchRfSetting(pAdapter); + } + +/*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/ +/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/ +static void MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14) +{ + hal_mpt_CCKTxPowerAdjust(Adapter, bInCH14); +} + +static void MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven) +{ + hal_mpt_CCKTxPowerAdjustbyIndex(pAdapter, beven); + } + +/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/ + +/* + * SetChannel + * Description + * Use H2C command to change channel, + * not only modify rf register, but also other setting need to be done. + */ +void SetChannel(PADAPTER pAdapter) +{ + hal_mpt_SetChannel(pAdapter); +} + +/* + * Notice + * Switch bandwitdth may change center frequency(channel) + */ +void SetBandwidth(PADAPTER pAdapter) +{ + hal_mpt_SetBandwidth(pAdapter); + +} + +void SetAntenna(PADAPTER pAdapter) +{ + hal_mpt_SetAntenna(pAdapter); +} + +int SetTxPower(PADAPTER pAdapter) +{ + + hal_mpt_SetTxPower(pAdapter); + return _TRUE; +} + +void SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset) +{ + u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D,tmpAGC; + + TxAGCOffset_B = (ulTxAGCOffset&0x000000ff); + TxAGCOffset_C = ((ulTxAGCOffset&0x0000ff00)>>8); + TxAGCOffset_D = ((ulTxAGCOffset&0x00ff0000)>>16); + + tmpAGC = (TxAGCOffset_D<<8 | TxAGCOffset_C<<4 | TxAGCOffset_B); + write_bbreg(pAdapter, rFPGA0_TxGainStage, + (bXBTxAGC|bXCTxAGC|bXDTxAGC), tmpAGC); +} + +void SetDataRate(PADAPTER pAdapter) +{ + hal_mpt_SetDataRate(pAdapter); +} + +void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter ,BOOLEAN bMain) +{ + + PHY_SetRFPathSwitch(pAdapter, bMain); + +} + + +s32 SetThermalMeter(PADAPTER pAdapter, u8 target_ther) +{ + return hal_mpt_SetThermalMeter(pAdapter, target_ther); +} + +static void TriggerRFThermalMeter(PADAPTER pAdapter) +{ + hal_mpt_TriggerRFThermalMeter(pAdapter); +} + +static u8 ReadRFThermalMeter(PADAPTER pAdapter) +{ + return hal_mpt_ReadRFThermalMeter(pAdapter); +} + +void GetThermalMeter(PADAPTER pAdapter, u8 *value) +{ + hal_mpt_GetThermalMeter(pAdapter, value); +} + +void SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart) +{ + PhySetTxPowerLevel(pAdapter); + hal_mpt_SetSingleCarrierTx(pAdapter, bStart); +} + +void SetSingleToneTx(PADAPTER pAdapter, u8 bStart) +{ + PhySetTxPowerLevel(pAdapter); + hal_mpt_SetSingleToneTx(pAdapter, bStart); +} + +void SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart) +{ + PhySetTxPowerLevel(pAdapter); + hal_mpt_SetCarrierSuppressionTx(pAdapter, bStart); +} + +void SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart) +{ + PhySetTxPowerLevel(pAdapter); + hal_mpt_SetCCKContinuousTx(pAdapter, bStart); +} + +void SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart) +{ + PhySetTxPowerLevel(pAdapter); + hal_mpt_SetOFDMContinuousTx(pAdapter, bStart); +}/* mpt_StartOfdmContTx */ + +void SetContinuousTx(PADAPTER pAdapter, u8 bStart) +{ + PhySetTxPowerLevel(pAdapter); + hal_mpt_SetContinuousTx(pAdapter, bStart); +} + + +void PhySetTxPowerLevel(PADAPTER pAdapter) +{ + struct mp_priv *pmp_priv = &pAdapter->mppriv; + + if (pmp_priv->bSetTxPower==0) // for NO manually set power index + { +#ifdef CONFIG_RTL8188E + PHY_SetTxPowerLevel8188E(pAdapter,pmp_priv->channel); +#endif +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) + PHY_SetTxPowerLevel8812(pAdapter,pmp_priv->channel); +#endif +#if defined(CONFIG_RTL8192E) + PHY_SetTxPowerLevel8192E(pAdapter,pmp_priv->channel); +#endif +#if defined(CONFIG_RTL8723B) + PHY_SetTxPowerLevel8723B(pAdapter,pmp_priv->channel); +#endif +#if defined(CONFIG_RTL8188F) + PHY_SetTxPowerLevel8188F(pAdapter, pmp_priv->channel); +#endif + mpt_ProQueryCalTxPower(pAdapter,pmp_priv->antenna_tx); + + } +} + +//------------------------------------------------------------------------------ +static void dump_mpframe(PADAPTER padapter, struct xmit_frame *pmpframe) +{ + rtw_hal_mgnt_xmit(padapter, pmpframe); +} + +static struct xmit_frame *alloc_mp_xmitframe(struct xmit_priv *pxmitpriv) +{ + struct xmit_frame *pmpframe; + struct xmit_buf *pxmitbuf; + + if ((pmpframe = rtw_alloc_xmitframe(pxmitpriv)) == NULL) + { + return NULL; + } + + if ((pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv)) == NULL) + { + rtw_free_xmitframe(pxmitpriv, pmpframe); + return NULL; + } + + pmpframe->frame_tag = MP_FRAMETAG; + + pmpframe->pxmitbuf = pxmitbuf; + + pmpframe->buf_addr = pxmitbuf->pbuf; + + pxmitbuf->priv_data = pmpframe; + + return pmpframe; + +} + +static thread_return mp_xmit_packet_thread(thread_context context) +{ + struct xmit_frame *pxmitframe; + struct mp_tx *pmptx; + struct mp_priv *pmp_priv; + struct xmit_priv *pxmitpriv; + PADAPTER padapter; + + pmp_priv = (struct mp_priv *)context; + pmptx = &pmp_priv->tx; + padapter = pmp_priv->papdater; + pxmitpriv = &(padapter->xmitpriv); + + thread_enter("RTW_MP_THREAD"); + + DBG_871X("%s:pkTx Start\n", __func__); + while (1) { + pxmitframe = alloc_mp_xmitframe(pxmitpriv); + if (pxmitframe == NULL) { + if (pmptx->stop || + RTW_CANNOT_RUN(padapter)) { + goto exit; + } + else { + rtw_usleep_os(10); + continue; + } + } + _rtw_memcpy((u8 *)(pxmitframe->buf_addr+TXDESC_OFFSET), pmptx->buf, pmptx->write_size); + _rtw_memcpy(&(pxmitframe->attrib), &(pmptx->attrib), sizeof(struct pkt_attrib)); + + + rtw_usleep_os(padapter->mppriv.pktInterval); + dump_mpframe(padapter, pxmitframe); + + pmptx->sended++; + pmp_priv->tx_pktcount++; + + if (pmptx->stop || + RTW_CANNOT_RUN(padapter)) + goto exit; + if ((pmptx->count != 0) && + (pmptx->count == pmptx->sended)) + goto exit; + + flush_signals_thread(); + } + +exit: + //DBG_871X("%s:pkTx Exit\n", __func__); + rtw_mfree(pmptx->pallocated_buf, pmptx->buf_size); + pmptx->pallocated_buf = NULL; + pmptx->stop = 1; + + thread_exit(); +} + +void fill_txdesc_for_mp(PADAPTER padapter, u8 *ptxdesc) +{ + struct mp_priv *pmp_priv = &padapter->mppriv; + _rtw_memcpy(ptxdesc, pmp_priv->tx.desc, TXDESC_SIZE); +} + +#if defined(CONFIG_RTL8188E) +void fill_tx_desc_8188e(PADAPTER padapter) +{ + struct mp_priv *pmp_priv = &padapter->mppriv; + struct tx_desc *desc = (struct tx_desc *)&(pmp_priv->tx.desc); + struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib); + u32 pkt_size = pattrib->last_txcmdsz; + s32 bmcast = IS_MCAST(pattrib->ra); +// offset 0 +#if !defined(CONFIG_RTL8188E_SDIO) && !defined(CONFIG_PCI_HCI) + desc->txdw0 |= cpu_to_le32(OWN | FSG | LSG); + desc->txdw0 |= cpu_to_le32(pkt_size & 0x0000FFFF); // packet size + desc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00FF0000); //32 bytes for TX Desc + if (bmcast) desc->txdw0 |= cpu_to_le32(BMC); // broadcast packet + + desc->txdw1 |= cpu_to_le32((0x01 << 26) & 0xff000000); +#endif + + desc->txdw1 |= cpu_to_le32((pattrib->mac_id) & 0x3F); //CAM_ID(MAC_ID) + desc->txdw1 |= cpu_to_le32((pattrib->qsel << QSEL_SHT) & 0x00001F00); // Queue Select, TID + desc->txdw1 |= cpu_to_le32((pattrib->raid << RATE_ID_SHT) & 0x000F0000); // Rate Adaptive ID + // offset 8 + // desc->txdw2 |= cpu_to_le32(AGG_BK);//AGG BK + + desc->txdw3 |= cpu_to_le32((pattrib->seqnum<<16)&0x0fff0000); + desc->txdw4 |= cpu_to_le32(HW_SSN); + + desc->txdw4 |= cpu_to_le32(USERATE); + desc->txdw4 |= cpu_to_le32(DISDATAFB); + + if( pmp_priv->preamble ){ + if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M) + desc->txdw4 |= cpu_to_le32(DATA_SHORT); // CCK Short Preamble + } + + if (pmp_priv->bandwidth == CHANNEL_WIDTH_40) + desc->txdw4 |= cpu_to_le32(DATA_BW); + + // offset 20 + desc->txdw5 |= cpu_to_le32(pmp_priv->rateidx & 0x0000001F); + + if( pmp_priv->preamble ){ + if (HwRateToMPTRate(pmp_priv->rateidx) > MPT_RATE_54M) + desc->txdw5 |= cpu_to_le32(SGI); // MCS Short Guard Interval + } + + desc->txdw5 |= cpu_to_le32(RTY_LMT_EN); // retry limit enable + desc->txdw5 |= cpu_to_le32(0x00180000); // DATA/RTS Rate Fallback Limit + + +} +#endif + +#if defined(CONFIG_RTL8814A) +void fill_tx_desc_8814a(PADAPTER padapter) +{ + struct mp_priv *pmp_priv = &padapter->mppriv; + u8 *pDesc = (u8 *)&(pmp_priv->tx.desc); + struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib); + + u32 pkt_size = pattrib->last_txcmdsz; + s32 bmcast = IS_MCAST(pattrib->ra); + u8 data_rate,pwr_status,offset; + + //SET_TX_DESC_FIRST_SEG_8814A(pDesc, 1); + SET_TX_DESC_LAST_SEG_8814A(pDesc, 1); + //SET_TX_DESC_OWN_(pDesc, 1); + + SET_TX_DESC_PKT_SIZE_8814A(pDesc, pkt_size); + + offset = TXDESC_SIZE + OFFSET_SZ; + + SET_TX_DESC_OFFSET_8814A(pDesc, offset); +#if defined(CONFIG_PCI_HCI) + SET_TX_DESC_PKT_OFFSET_8814A(pDesc, 0); /* 8814AE pkt_offset is 0 */ +#else + SET_TX_DESC_PKT_OFFSET_8814A(pDesc, 1); +#endif + + if (bmcast) { + SET_TX_DESC_BMC_8814A(pDesc, 1); + } + + SET_TX_DESC_MACID_8814A(pDesc, pattrib->mac_id); + SET_TX_DESC_RATE_ID_8814A(pDesc, pattrib->raid); + + //SET_TX_DESC_RATE_ID_8812(pDesc, RATEID_IDX_G); + SET_TX_DESC_QUEUE_SEL_8814A(pDesc, pattrib->qsel); + //SET_TX_DESC_QUEUE_SEL_8812(pDesc, QSLT_MGNT); + + if ( pmp_priv->preamble ){ + SET_TX_DESC_DATA_SHORT_8814A(pDesc, 1); + } + + if (!pattrib->qos_en) { + SET_TX_DESC_HWSEQ_EN_8814A(pDesc, 1); // Hw set sequence number + } else { + SET_TX_DESC_SEQ_8814A(pDesc, pattrib->seqnum); + } + + if (pmp_priv->bandwidth <= CHANNEL_WIDTH_160) { + SET_TX_DESC_DATA_BW_8814A(pDesc, pmp_priv->bandwidth); + } else { + DBG_871X("%s:Err: unknown bandwidth %d, use 20M\n", __func__,pmp_priv->bandwidth); + SET_TX_DESC_DATA_BW_8814A(pDesc, CHANNEL_WIDTH_20); + } + + SET_TX_DESC_DISABLE_FB_8814A(pDesc, 1); + SET_TX_DESC_USE_RATE_8814A(pDesc, 1); + SET_TX_DESC_TX_RATE_8814A(pDesc, pmp_priv->rateidx); + +} +#endif + +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) +void fill_tx_desc_8812a(PADAPTER padapter) +{ + struct mp_priv *pmp_priv = &padapter->mppriv; + u8 *pDesc = (u8 *)&(pmp_priv->tx.desc); + struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib); + + u32 pkt_size = pattrib->last_txcmdsz; + s32 bmcast = IS_MCAST(pattrib->ra); + u8 data_rate,pwr_status,offset; + + SET_TX_DESC_FIRST_SEG_8812(pDesc, 1); + SET_TX_DESC_LAST_SEG_8812(pDesc, 1); + SET_TX_DESC_OWN_8812(pDesc, 1); + + SET_TX_DESC_PKT_SIZE_8812(pDesc, pkt_size); + + offset = TXDESC_SIZE + OFFSET_SZ; + + SET_TX_DESC_OFFSET_8812(pDesc, offset); + +#if defined(CONFIG_PCI_HCI) + SET_TX_DESC_PKT_OFFSET_8812(pDesc, 0); +#else + SET_TX_DESC_PKT_OFFSET_8812(pDesc, 1); +#endif + if (bmcast) { + SET_TX_DESC_BMC_8812(pDesc, 1); + } + + SET_TX_DESC_MACID_8812(pDesc, pattrib->mac_id); + SET_TX_DESC_RATE_ID_8812(pDesc, pattrib->raid); + + //SET_TX_DESC_RATE_ID_8812(pDesc, RATEID_IDX_G); + SET_TX_DESC_QUEUE_SEL_8812(pDesc, pattrib->qsel); + //SET_TX_DESC_QUEUE_SEL_8812(pDesc, QSLT_MGNT); + + if (!pattrib->qos_en) { + SET_TX_DESC_HWSEQ_EN_8812(pDesc, 1); // Hw set sequence number + } else { + SET_TX_DESC_SEQ_8812(pDesc, pattrib->seqnum); + } + + if (pmp_priv->bandwidth <= CHANNEL_WIDTH_160) { + SET_TX_DESC_DATA_BW_8812(pDesc, pmp_priv->bandwidth); + } else { + DBG_871X("%s:Err: unknown bandwidth %d, use 20M\n", __func__,pmp_priv->bandwidth); + SET_TX_DESC_DATA_BW_8812(pDesc, CHANNEL_WIDTH_20); + } + + SET_TX_DESC_DISABLE_FB_8812(pDesc, 1); + SET_TX_DESC_USE_RATE_8812(pDesc, 1); + SET_TX_DESC_TX_RATE_8812(pDesc, pmp_priv->rateidx); + +} +#endif +#if defined(CONFIG_RTL8192E) +void fill_tx_desc_8192e(PADAPTER padapter) +{ + struct mp_priv *pmp_priv = &padapter->mppriv; + u8 *pDesc = (u8 *)&(pmp_priv->tx.desc); + struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib); + + u32 pkt_size = pattrib->last_txcmdsz; + s32 bmcast = IS_MCAST(pattrib->ra); + u8 data_rate,pwr_status,offset; + + + SET_TX_DESC_PKT_SIZE_92E(pDesc, pkt_size); + + offset = TXDESC_SIZE + OFFSET_SZ; + + SET_TX_DESC_OFFSET_92E(pDesc, offset); + #if defined(CONFIG_PCI_HCI) /* 8192EE */ + + SET_TX_DESC_PKT_OFFSET_92E(pDesc, 0); /* 8192EE pkt_offset is 0 */ + #else /* 8192EU 8192ES */ + SET_TX_DESC_PKT_OFFSET_92E(pDesc, 1); + #endif + + if (bmcast) { + SET_TX_DESC_BMC_92E(pDesc, 1); + } + + SET_TX_DESC_MACID_92E(pDesc, pattrib->mac_id); + SET_TX_DESC_RATE_ID_92E(pDesc, pattrib->raid); + + + SET_TX_DESC_QUEUE_SEL_92E(pDesc, pattrib->qsel); + //SET_TX_DESC_QUEUE_SEL_8812(pDesc, QSLT_MGNT); + + if (!pattrib->qos_en) { + SET_TX_DESC_EN_HWSEQ_92E(pDesc, 1);// Hw set sequence number + SET_TX_DESC_HWSEQ_SEL_92E(pDesc, pattrib->hw_ssn_sel); + } else { + SET_TX_DESC_SEQ_92E(pDesc, pattrib->seqnum); + } + + if ((pmp_priv->bandwidth == CHANNEL_WIDTH_20) || (pmp_priv->bandwidth == CHANNEL_WIDTH_40)) { + SET_TX_DESC_DATA_BW_92E(pDesc, pmp_priv->bandwidth); + } else { + DBG_871X("%s:Err: unknown bandwidth %d, use 20M\n", __func__,pmp_priv->bandwidth); + SET_TX_DESC_DATA_BW_92E(pDesc, CHANNEL_WIDTH_20); + } + + //SET_TX_DESC_DATA_SC_92E(pDesc, SCMapping_92E(padapter,pattrib)); + + SET_TX_DESC_DISABLE_FB_92E(pDesc, 1); + SET_TX_DESC_USE_RATE_92E(pDesc, 1); + SET_TX_DESC_TX_RATE_92E(pDesc, pmp_priv->rateidx); + +} +#endif + +#if defined(CONFIG_RTL8723B) +void fill_tx_desc_8723b(PADAPTER padapter) +{ + struct mp_priv *pmp_priv = &padapter->mppriv; + struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib); + u8 *ptxdesc = pmp_priv->tx.desc; + + SET_TX_DESC_AGG_BREAK_8723B(ptxdesc, 1); + SET_TX_DESC_MACID_8723B(ptxdesc, pattrib->mac_id); + SET_TX_DESC_QUEUE_SEL_8723B(ptxdesc, pattrib->qsel); + + SET_TX_DESC_RATE_ID_8723B(ptxdesc, pattrib->raid); + SET_TX_DESC_SEQ_8723B(ptxdesc, pattrib->seqnum); + SET_TX_DESC_HWSEQ_EN_8723B(ptxdesc, 1); + SET_TX_DESC_USE_RATE_8723B(ptxdesc, 1); + SET_TX_DESC_DISABLE_FB_8723B(ptxdesc, 1); + + if (pmp_priv->preamble) { + if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M) + SET_TX_DESC_DATA_SHORT_8723B(ptxdesc, 1); + } + + if (pmp_priv->bandwidth == CHANNEL_WIDTH_40) { + SET_TX_DESC_DATA_BW_8723B(ptxdesc, 1); + } + + SET_TX_DESC_TX_RATE_8723B(ptxdesc, pmp_priv->rateidx); + + SET_TX_DESC_DATA_RATE_FB_LIMIT_8723B(ptxdesc, 0x1F); + SET_TX_DESC_RTS_RATE_FB_LIMIT_8723B(ptxdesc, 0xF); +} +#endif + +#if defined(CONFIG_RTL8703B) +void fill_tx_desc_8703b(PADAPTER padapter) +{ + struct mp_priv *pmp_priv = &padapter->mppriv; + struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib); + u8 *ptxdesc = pmp_priv->tx.desc; + + SET_TX_DESC_AGG_BREAK_8703B(ptxdesc, 1); + SET_TX_DESC_MACID_8703B(ptxdesc, pattrib->mac_id); + SET_TX_DESC_QUEUE_SEL_8703B(ptxdesc, pattrib->qsel); + + SET_TX_DESC_RATE_ID_8703B(ptxdesc, pattrib->raid); + SET_TX_DESC_SEQ_8703B(ptxdesc, pattrib->seqnum); + SET_TX_DESC_HWSEQ_EN_8703B(ptxdesc, 1); + SET_TX_DESC_USE_RATE_8703B(ptxdesc, 1); + SET_TX_DESC_DISABLE_FB_8703B(ptxdesc, 1); + + if (pmp_priv->preamble) { + if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M) + SET_TX_DESC_DATA_SHORT_8703B(ptxdesc, 1); + } + + if (pmp_priv->bandwidth == CHANNEL_WIDTH_40) + SET_TX_DESC_DATA_BW_8703B(ptxdesc, 1); + + SET_TX_DESC_TX_RATE_8703B(ptxdesc, pmp_priv->rateidx); + + SET_TX_DESC_DATA_RATE_FB_LIMIT_8703B(ptxdesc, 0x1F); + SET_TX_DESC_RTS_RATE_FB_LIMIT_8703B(ptxdesc, 0xF); +} +#endif + +#if defined(CONFIG_RTL8188F) +void fill_tx_desc_8188f(PADAPTER padapter) +{ + struct mp_priv *pmp_priv = &padapter->mppriv; + struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib); + u8 *ptxdesc = pmp_priv->tx.desc; + + SET_TX_DESC_AGG_BREAK_8188F(ptxdesc, 1); + SET_TX_DESC_MACID_8188F(ptxdesc, pattrib->mac_id); + SET_TX_DESC_QUEUE_SEL_8188F(ptxdesc, pattrib->qsel); + + SET_TX_DESC_RATE_ID_8188F(ptxdesc, pattrib->raid); + SET_TX_DESC_SEQ_8188F(ptxdesc, pattrib->seqnum); + SET_TX_DESC_HWSEQ_EN_8188F(ptxdesc, 1); + SET_TX_DESC_USE_RATE_8188F(ptxdesc, 1); + SET_TX_DESC_DISABLE_FB_8188F(ptxdesc, 1); + + if (pmp_priv->preamble) + if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_54M) + SET_TX_DESC_DATA_SHORT_8188F(ptxdesc, 1); + + if (pmp_priv->bandwidth == CHANNEL_WIDTH_40) + SET_TX_DESC_DATA_BW_8188F(ptxdesc, 1); + + SET_TX_DESC_TX_RATE_8188F(ptxdesc, pmp_priv->rateidx); + + SET_TX_DESC_DATA_RATE_FB_LIMIT_8188F(ptxdesc, 0x1F); + SET_TX_DESC_RTS_RATE_FB_LIMIT_8188F(ptxdesc, 0xF); +} +#endif + +static void Rtw_MPSetMacTxEDCA(PADAPTER padapter) +{ + + rtw_write32(padapter, 0x508 , 0x00a422); //Disable EDCA BE Txop for MP pkt tx adjust Packet interval + //DBG_871X("%s:write 0x508~~~~~~ 0x%x\n", __func__,rtw_read32(padapter, 0x508)); + PHY_SetMacReg(padapter, 0x458 ,bMaskDWord , 0x0); + //DBG_8192C("%s()!!!!! 0x460 = 0x%x\n" ,__func__,PHY_QueryBBReg(padapter, 0x460, bMaskDWord)); + PHY_SetMacReg(padapter, 0x460 ,bMaskLWord , 0x0);//fast EDCA queue packet interval & time out vaule + //PHY_SetMacReg(padapter, ODM_EDCA_VO_PARAM ,bMaskLWord , 0x431C); + //PHY_SetMacReg(padapter, ODM_EDCA_BE_PARAM ,bMaskLWord , 0x431C); + //PHY_SetMacReg(padapter, ODM_EDCA_BK_PARAM ,bMaskLWord , 0x431C); + DBG_8192C("%s()!!!!! 0x460 = 0x%x\n" ,__func__,PHY_QueryBBReg(padapter, 0x460, bMaskDWord)); + +} + +void SetPacketTx(PADAPTER padapter) +{ + u8 *ptr, *pkt_start, *pkt_end,*fctrl; + u32 pkt_size,offset,startPlace,i; + struct rtw_ieee80211_hdr *hdr; + u8 payload; + s32 bmcast; + struct pkt_attrib *pattrib; + struct mp_priv *pmp_priv; + + pmp_priv = &padapter->mppriv; + + if (pmp_priv->tx.stop) return; + pmp_priv->tx.sended = 0; + pmp_priv->tx.stop = 0; + pmp_priv->tx_pktcount = 0; + + //3 1. update_attrib() + pattrib = &pmp_priv->tx.attrib; + _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); + _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); + bmcast = IS_MCAST(pattrib->ra); + if (bmcast) { + pattrib->mac_id = 1; + pattrib->psta = rtw_get_bcmc_stainfo(padapter); + } else { + pattrib->mac_id = 0; + pattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv)); + } + pattrib->mbssid = 0; + + pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen; + + //3 2. allocate xmit buffer + pkt_size = pattrib->last_txcmdsz; + + if (pmp_priv->tx.pallocated_buf) + rtw_mfree(pmp_priv->tx.pallocated_buf, pmp_priv->tx.buf_size); + pmp_priv->tx.write_size = pkt_size; + pmp_priv->tx.buf_size = pkt_size + XMITBUF_ALIGN_SZ; + pmp_priv->tx.pallocated_buf = rtw_zmalloc(pmp_priv->tx.buf_size); + if (pmp_priv->tx.pallocated_buf == NULL) { + DBG_871X("%s: malloc(%d) fail!!\n", __func__, pmp_priv->tx.buf_size); + return; + } + pmp_priv->tx.buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pmp_priv->tx.pallocated_buf), XMITBUF_ALIGN_SZ); + ptr = pmp_priv->tx.buf; + + _rtw_memset(pmp_priv->tx.desc, 0, TXDESC_SIZE); + pkt_start = ptr; + pkt_end = pkt_start + pkt_size; + + //3 3. init TX descriptor +#if defined(CONFIG_RTL8188E) + if(IS_HARDWARE_TYPE_8188E(padapter)) + fill_tx_desc_8188e(padapter); +#endif + +#if defined(CONFIG_RTL8814A) + if(IS_HARDWARE_TYPE_8814A(padapter)) + fill_tx_desc_8814a(padapter); +#endif /* defined(CONFIG_RTL8814A) */ + +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) + if(IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) + fill_tx_desc_8812a(padapter); +#endif + +#if defined(CONFIG_RTL8192E) + if(IS_HARDWARE_TYPE_8192E(padapter)) + fill_tx_desc_8192e(padapter); +#endif +#if defined(CONFIG_RTL8723B) + if(IS_HARDWARE_TYPE_8723B(padapter)) + fill_tx_desc_8723b(padapter); +#endif +#if defined(CONFIG_RTL8703B) + if (IS_HARDWARE_TYPE_8703B(padapter)) + fill_tx_desc_8703b(padapter); +#endif + +#if defined(CONFIG_RTL8188F) + if (IS_HARDWARE_TYPE_8188F(padapter)) + fill_tx_desc_8188f(padapter); +#endif + + //3 4. make wlan header, make_wlanhdr() + hdr = (struct rtw_ieee80211_hdr *)pkt_start; + SetFrameSubType(&hdr->frame_ctl, pattrib->subtype); + // + SetFrDs(&hdr->frame_ctl); + _rtw_memcpy(hdr->addr1, pattrib->dst, ETH_ALEN); // DA + _rtw_memcpy(hdr->addr2, pattrib->src, ETH_ALEN); // SA + _rtw_memcpy(hdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN); // RA, BSSID + + //3 5. make payload + ptr = pkt_start + pattrib->hdrlen; + + switch (pmp_priv->tx.payload) { + case 0: + payload = 0x00; + break; + case 1: + payload = 0x5a; + break; + case 2: + payload = 0xa5; + break; + case 3: + payload = 0xff; + break; + default: + payload = 0x00; + break; + } + pmp_priv->TXradomBuffer = rtw_zmalloc(4096); + if(pmp_priv->TXradomBuffer == NULL) + { + DBG_871X("mp create random buffer fail!\n"); + goto exit; + } + + + for(i=0;i<4096;i++) + pmp_priv->TXradomBuffer[i] = rtw_random32() %0xFF; + + //startPlace = (u32)(rtw_random32() % 3450); + _rtw_memcpy(ptr, pmp_priv->TXradomBuffer,pkt_end - ptr); + //_rtw_memset(ptr, payload, pkt_end - ptr); + rtw_mfree(pmp_priv->TXradomBuffer,4096); + + //3 6. start thread +#ifdef PLATFORM_LINUX + pmp_priv->tx.PktTxThread = kthread_run(mp_xmit_packet_thread, pmp_priv, "RTW_MP_THREAD"); + if (IS_ERR(pmp_priv->tx.PktTxThread)) + DBG_871X("Create PktTx Thread Fail !!!!!\n"); +#endif +#ifdef PLATFORM_FREEBSD +{ + struct proc *p; + struct thread *td; + pmp_priv->tx.PktTxThread = kproc_kthread_add(mp_xmit_packet_thread, pmp_priv, + &p, &td, RFHIGHPID, 0, "MPXmitThread", "MPXmitThread"); + + if (pmp_priv->tx.PktTxThread < 0) + DBG_871X("Create PktTx Thread Fail !!!!!\n"); +} +#endif + + Rtw_MPSetMacTxEDCA(padapter); +exit: + return; +} + +void SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); + struct mp_priv *pmppriv = &pAdapter->mppriv; + + + if (bStartRx) { +#ifdef CONFIG_RTL8723B + PHY_SetMacReg(pAdapter, 0xe70, BIT23|BIT22, 0x3);// Power on adc (in RX_WAIT_CCA state) + write_bbreg(pAdapter, 0xa01, BIT0, bDisable);// improve Rx performance by jerry +#endif + pHalData->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AMF | RCR_HTC_LOC_CTRL; + pHalData->ReceiveConfig |= RCR_ACRC32; + pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC; + + if (pmppriv->bSetRxBssid == _TRUE) { + DBG_8192C("%s: pmppriv->network_macaddr=" MAC_FMT "\n", __func__, + MAC_ARG(pmppriv->network_macaddr)); + + //Set_MSR(pAdapter, WIFI_FW_AP_STATE); + //rtw_hal_set_hwreg(pAdapter, HW_VAR_BSSID, pmppriv->network_macaddr); + //rtw_hal_set_hwreg(pAdapter, HW_VAR_SET_OPMODE, (u8 *)(&type)); + } else { + pHalData->ReceiveConfig |= RCR_ADF; + + /* Accept all data frames */ + rtw_write16(pAdapter, REG_RXFLTMAP2, 0xFFFF); + } + + if (bAB) + pHalData->ReceiveConfig |= RCR_AB; + } else { +#ifdef CONFIG_RTL8723B + PHY_SetMacReg(pAdapter, 0xe70, BIT23|BIT22, 0x00);// Power off adc (in RX_WAIT_CCA state) + write_bbreg(pAdapter, 0xa01, BIT0, bEnable);// improve Rx performance by jerry +#endif + pHalData->ReceiveConfig = 0; + } + + rtw_write32(pAdapter, REG_RCR, pHalData->ReceiveConfig); +} + +void ResetPhyRxPktCount(PADAPTER pAdapter) +{ + u32 i, phyrx_set = 0; + + for (i = 0; i <= 0xF; i++) { + phyrx_set = 0; + phyrx_set |= _RXERR_RPT_SEL(i); //select + phyrx_set |= RXERR_RPT_RST; // set counter to zero + rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set); + } +} + +static u32 GetPhyRxPktCounts(PADAPTER pAdapter, u32 selbit) +{ + //selection + u32 phyrx_set = 0, count = 0; + + phyrx_set = _RXERR_RPT_SEL(selbit & 0xF); + rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set); + + //Read packet count + count = rtw_read32(pAdapter, REG_RXERR_RPT) & RXERR_COUNTER_MASK; + + return count; +} + +u32 GetPhyRxPktReceived(PADAPTER pAdapter) +{ + u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0; + + OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_OK); + CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_OK); + HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_OK); + + return OFDM_cnt + CCK_cnt + HT_cnt; +} + +u32 GetPhyRxPktCRC32Error(PADAPTER pAdapter) +{ + u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0; + + OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_FAIL); + CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_FAIL); + HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_FAIL); + + return OFDM_cnt + CCK_cnt + HT_cnt; +} + +//reg 0x808[9:0]: FFT data x +//reg 0x808[22]: 0 --> 1 to get 1 FFT data y +//reg 0x8B4[15:0]: FFT data y report +static u32 rtw_GetPSDData(PADAPTER pAdapter, u32 point) +{ + u32 psd_val=0; + +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) + u16 psd_reg = 0x910; + u16 psd_regL= 0xF44; +#else + u16 psd_reg = 0x808; + u16 psd_regL= 0x8B4; +#endif + + psd_val = rtw_read32(pAdapter, psd_reg); + + psd_val &= 0xFFBFFC00; + psd_val |= point; + + rtw_write32(pAdapter, psd_reg, psd_val); + rtw_mdelay_os(1); + psd_val |= 0x00400000; + + rtw_write32(pAdapter, psd_reg, psd_val); + rtw_mdelay_os(1); + + psd_val = rtw_read32(pAdapter, psd_regL); + psd_val &= 0x0000FFFF; + + return psd_val; +} + +/* + * pts start_point_min stop_point_max + * 128 64 64 + 128 = 192 + * 256 128 128 + 256 = 384 + * 512 256 256 + 512 = 768 + * 1024 512 512 + 1024 = 1536 + * + */ +u32 mp_query_psd(PADAPTER pAdapter, u8 *data) +{ + u32 i, psd_pts=0, psd_start=0, psd_stop=0; + u32 psd_data=0; + + +#ifdef PLATFORM_LINUX + if (!netif_running(pAdapter->pnetdev)) { + RT_TRACE(_module_mp_, _drv_warning_, ("mp_query_psd: Fail! interface not opened!\n")); + return 0; + } +#endif + + if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) { + RT_TRACE(_module_mp_, _drv_warning_, ("mp_query_psd: Fail! not in MP mode!\n")); + return 0; + } + + if (strlen(data) == 0) { //default value + psd_pts = 128; + psd_start = 64; + psd_stop = 128; + } else { + sscanf(data, "pts=%d,start=%d,stop=%d", &psd_pts, &psd_start, &psd_stop); + } + + data[0]='\0'; + + i = psd_start; + while (i < psd_stop) + { + if (i >= psd_pts) { + psd_data = rtw_GetPSDData(pAdapter, i-psd_pts); + } else { + psd_data = rtw_GetPSDData(pAdapter, i); + } + sprintf(data, "%s%x ", data, psd_data); + i++; + } + + #ifdef CONFIG_LONG_DELAY_ISSUE + rtw_msleep_os(100); + #else + rtw_mdelay_os(100); + #endif + + return strlen(data)+1; +} + + +#if 0 +void _rtw_mp_xmit_priv (struct xmit_priv *pxmitpriv) +{ + int i,res; + _adapter *padapter = pxmitpriv->adapter; + struct xmit_frame *pxmitframe = (struct xmit_frame*) pxmitpriv->pxmit_frame_buf; + struct xmit_buf *pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf; + + u32 max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ; + u32 num_xmit_extbuf = NR_XMIT_EXTBUFF; + if(padapter->registrypriv.mp_mode ==0) + { + max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ; + num_xmit_extbuf = NR_XMIT_EXTBUFF; + } + else + { + max_xmit_extbuf_size = 6000; + num_xmit_extbuf = 8; + } + + pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf; + for(i=0; ipallocated_xmit_extbuf) { + rtw_vmfree(pxmitpriv->pallocated_xmit_extbuf, num_xmit_extbuf * sizeof(struct xmit_buf) + 4); + } + + if(padapter->registrypriv.mp_mode ==0) + { + max_xmit_extbuf_size = 6000; + num_xmit_extbuf = 8; + } + else + { + max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ; + num_xmit_extbuf = NR_XMIT_EXTBUFF; + } + + // Init xmit extension buff + _rtw_init_queue(&pxmitpriv->free_xmit_extbuf_queue); + + pxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(num_xmit_extbuf * sizeof(struct xmit_buf) + 4); + + if (pxmitpriv->pallocated_xmit_extbuf == NULL){ + RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("alloc xmit_extbuf fail!\n")); + res= _FAIL; + goto exit; + } + + pxmitpriv->pxmit_extbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmit_extbuf), 4); + + pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf; + + for (i = 0; i < num_xmit_extbuf; i++) + { + _rtw_init_listhead(&pxmitbuf->list); + + pxmitbuf->priv_data = NULL; + pxmitbuf->padapter = padapter; + pxmitbuf->buf_tag = XMITBUF_MGNT; + + if((res=rtw_os_xmit_resource_alloc(padapter, pxmitbuf,max_xmit_extbuf_size + XMITBUF_ALIGN_SZ, _TRUE)) == _FAIL) { + res= _FAIL; + goto exit; + } + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + pxmitbuf->phead = pxmitbuf->pbuf; + pxmitbuf->pend = pxmitbuf->pbuf + max_xmit_extbuf_size; + pxmitbuf->len = 0; + pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead; +#endif + + rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmit_extbuf_queue.queue)); + #ifdef DBG_XMIT_BUF_EXT + pxmitbuf->no=i; + #endif + pxmitbuf++; + + } + + pxmitpriv->free_xmit_extbuf_cnt = num_xmit_extbuf; + +exit: + ; +} +#endif + + +ULONG getPowerDiffByRate8188E( + IN PADAPTER pAdapter, + IN u1Byte CurrChannel, + IN ULONG RfPath + ) +{ + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + ULONG PwrGroup=0; + ULONG TxPower=0, Limit=0; + ULONG Pathmapping = (RfPath == ODM_RF_PATH_A?0:8); + + switch(pHalData->EEPROMRegulatory) + { + case 0: // driver-defined maximum power offset for longer communication range + // refer to power by rate table + PwrGroup = 0; + Limit = 0xff; + break; + case 1: // Power-limit table-defined maximum power offset range + // choosed by min(power by rate, power limit). + { + if(pHalData->pwrGroupCnt == 1) + PwrGroup = 0; + if(pHalData->pwrGroupCnt >= 3) + { + if(CurrChannel <= 3) + PwrGroup = 0; + else if(CurrChannel >= 4 && CurrChannel <= 9) + PwrGroup = 1; + else if(CurrChannel > 9) + PwrGroup = 2; + + if(pHalData->CurrentChannelBW == CHANNEL_WIDTH_20) + PwrGroup++; + else + PwrGroup+=4; + } + Limit = 0xff; + } + break; + case 2: // not support power offset by rate. + // don't increase any power diff + PwrGroup = 0; + Limit = 0; + break; + default: + PwrGroup = 0; + Limit = 0xff; + break; + } + + + { + switch(pMptCtx->MptRateIndex) + { + case MPT_RATE_1M: + case MPT_RATE_2M: + case MPT_RATE_55M: + case MPT_RATE_11M: + //CCK rates, don't add any tx power index. + //RT_DISP(FPHY, PHY_TXPWR,("CCK rates!\n")); + break; + case MPT_RATE_6M: //0xe00 [31:0] = 18M,12M,09M,06M + TxPower += ((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0+Pathmapping])&0xff); + //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x, OFDM 6M, TxPower = %d\n", + // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0], TxPower)); + break; + case MPT_RATE_9M: + TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0+Pathmapping])&0xff00)>>8); + //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x, OFDM 9M, TxPower = %d\n", + // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0], TxPower)); + break; + case MPT_RATE_12M: + TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0+Pathmapping])&0xff0000)>>16); + //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x, OFDM 12M, TxPower = %d\n", + // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0], TxPower)); + break; + case MPT_RATE_18M: + TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0+Pathmapping])&0xff000000)>>24); + //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x, OFDM 24M, TxPower = %d\n", + // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][0], TxPower)); + break; + case MPT_RATE_24M: //0xe04[31:0] = 54M,48M,36M,24M + TxPower += ((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1+Pathmapping])&0xff); + //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x, OFDM 24M, TxPower = %d\n", + // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1], TxPower)); + break; + case MPT_RATE_36M: + TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1+Pathmapping])&0xff00)>>8); + //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x, OFDM 36M, TxPower = %d\n", + // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1], TxPower)); + break; + case MPT_RATE_48M: + TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1+Pathmapping])&0xff0000)>>16); + //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x, OFDM 48M, TxPower = %d\n", + // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1], TxPower)); + break; + case MPT_RATE_54M: + TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1+Pathmapping])&0xff000000)>>24); + //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x, OFDM 54M, TxPower = %d\n", + // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][1], TxPower)); + break; + case MPT_RATE_MCS0: //0xe10[31:0]= MCS=03,02,01,00 + TxPower += ((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2+Pathmapping])&0xff); + //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x, MCS0, TxPower = %d\n", + // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2], TxPower)); + break; + case MPT_RATE_MCS1: + TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2+Pathmapping])&0xff00)>>8); + //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x, MCS1, TxPower = %d\n", + // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2], TxPower)); + break; + case MPT_RATE_MCS2: + TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2+Pathmapping])&0xff0000)>>16); + //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x, MCS2, TxPower = %d\n", + // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2], TxPower)); + break; + case MPT_RATE_MCS3: + TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2+Pathmapping])&0xff000000)>>24); + //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x, MCS3, TxPower = %d\n", + // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][2], TxPower)); + break; + case MPT_RATE_MCS4: //0xe14[31:0]= MCS=07,06,05,04 + TxPower += ((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3+Pathmapping])&0xff); + //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x, MCS4, TxPower = %d\n", + // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3], TxPower)); + break; + case MPT_RATE_MCS5: + TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3+Pathmapping])&0xff00)>>8); + //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x, MCS5, TxPower = %d\n", + // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3], TxPower)); + break; + case MPT_RATE_MCS6: + TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3+Pathmapping])&0xff0000)>>16); + //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x, MCS6, TxPower = %d\n", + // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3], TxPower)); + break; + case MPT_RATE_MCS7: + TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3+Pathmapping])&0xff000000)>>24); + //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x, MCS7, TxPower = %d\n", + // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][3], TxPower)); + break; + + case MPT_RATE_MCS8: //0xe18[31:0]= MCS=11,10,09,08 + TxPower += ((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4+Pathmapping])&0xff); + //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x, MCS8, TxPower = %d\n", + // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4], TxPower)); + break; + case MPT_RATE_MCS9: + TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4+Pathmapping])&0xff00)>>8); + //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x, MCS9, TxPower = %d\n", + // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4], TxPower)); + break; + case MPT_RATE_MCS10: + TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4+Pathmapping])&0xff0000)>>16); + //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x, MCS10, TxPower = %d\n", + // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4], TxPower)); + break; + case MPT_RATE_MCS11: + TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4+Pathmapping])&0xff000000)>>24); + //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x, MCS11, TxPower = %d\n", + // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][4], TxPower)); + break; + case MPT_RATE_MCS12: //0xe1c[31:0]= MCS=15,14,13,12 + TxPower += ((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5+Pathmapping])&0xff); + //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x, MCS12, TxPower = %d\n", + // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5], TxPower)); + break; + case MPT_RATE_MCS13: + TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5+Pathmapping])&0xff00)>>8); + //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x, MCS13, TxPower = %d\n", + // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5], TxPower)); + break; + case MPT_RATE_MCS14: + TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5+Pathmapping])&0xff0000)>>16); + //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x, MCS14, TxPower = %d\n", + // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5], TxPower)); + break; + case MPT_RATE_MCS15: + TxPower += (((pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5+Pathmapping])&0xff000000)>>24); + //RT_DISP(FPHY, PHY_TXPWR,("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x, MCS15, TxPower = %d\n", + // PwrGroup, pHalData->MCSTxPowerLevelOriginalOffset[PwrGroup][5], TxPower)); + break; + default: + break; + } + } + + if(TxPower > Limit) + TxPower = Limit; + + return TxPower; +} + + + +static ULONG +mpt_ProQueryCalTxPower_8188E( + IN PADAPTER pAdapter, + IN u1Byte RfPath + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + u1Byte TxCount=TX_1S, i = 0; //default set to 1S + //PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo); + ULONG TxPower = 1, PwrGroup=0, PowerDiffByRate=0; + ULONG TxPowerCCK = 1, TxPowerOFDM = 1, TxPowerBW20 = 1, TxPowerBW40 = 1 ; + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + u1Byte CurrChannel = pHalData->CurrentChannel; + u1Byte index = (CurrChannel -1); + u1Byte rf_path=(RfPath), rfPath; + u1Byte limit = 0, rate = 0; + + if(HAL_IsLegalChannel(pAdapter, CurrChannel) == FALSE) + { + CurrChannel = 1; + } + + if(pMptCtx->MptRateIndex <= MPT_RATE_11M ) + { + TxPower = pHalData->Index24G_CCK_Base[rf_path][index]; + } + else if(pMptCtx->MptRateIndex >= MPT_RATE_6M && + pMptCtx->MptRateIndex <= MPT_RATE_54M ) + { + TxPower = pHalData->Index24G_BW40_Base[rf_path][index]; + } + else if(pMptCtx->MptRateIndex >= MPT_RATE_MCS0 && + pMptCtx->MptRateIndex <= MPT_RATE_MCS7 ) + { + TxPower = pHalData->Index24G_BW40_Base[rf_path][index]; + } + + //RT_DISP(FPHY, PHY_TXPWR, ("HT40 rate(%d) Tx power(RF-%c) = 0x%x\n", pMptCtx->MptRateIndex, ((rf_path==0)?'A':'B'), TxPower)); + + + if(pMptCtx->MptRateIndex >= MPT_RATE_6M && + pMptCtx->MptRateIndex <= MPT_RATE_54M ) + { + TxPower += pHalData->OFDM_24G_Diff[rf_path][TxCount]; + ///RT_DISP(FPHY, PHY_TXPWR, ("+OFDM_PowerDiff(RF-%c) = 0x%x\n", ((rf_path==0)?'A':'B'), + // pHalData->OFDM_24G_Diff[rf_path][TxCount])); + } + + if(pMptCtx->MptRateIndex >= MPT_RATE_MCS0) + { + if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_20) + { + TxPower += pHalData->BW20_24G_Diff[rf_path][TxCount]; + // RT_DISP(FPHY, PHY_TXPWR, ("+HT20_PowerDiff(RF-%c) = 0x%x\n", ((rf_path==0)?'A':'B'), + // pHalData->BW20_24G_Diff[rf_path][TxCount])); + } + } + + +#ifdef ENABLE_POWER_BY_RATE + PowerDiffByRate = getPowerDiffByRate8188E(pAdapter, CurrChannel, RfPath); +#else + PowerDiffByRate = 0; +#endif + + // 2012/11/02 Awk: add power limit mechansim + if( pMptCtx->MptRateIndex <= MPT_RATE_11M ) + { + rate = MGN_1M; + } + else if(pMptCtx->MptRateIndex >= MPT_RATE_6M && + pMptCtx->MptRateIndex <= MPT_RATE_54M ) + { + rate = MGN_54M; + } + else if(pMptCtx->MptRateIndex >= MPT_RATE_MCS0 && + pMptCtx->MptRateIndex <= MPT_RATE_MCS7 ) + { + rate = MGN_MCS7; + } + + limit = (u8)PHY_GetTxPowerLimit(pAdapter, pMptCtx->RegTxPwrLimit, + pHalData->CurrentBandType, + pHalData->CurrentChannelBW,RfPath, + rate, CurrChannel); + + //RT_DISP(FPHY, PHY_TXPWR, ("+PowerDiffByRate(RF-%c) = 0x%x\n", ((rf_path==0)?'A':'B'), + // PowerDiffByRate)); + TxPower += PowerDiffByRate; + //RT_DISP(FPHY, PHY_TXPWR, ("PowerDiffByRate limit value(RF-%c) = %d\n", ((rf_path==0)?'A':'B'), + // limit)); + + TxPower += limit > (s8) PowerDiffByRate ? PowerDiffByRate : limit; + + return TxPower; +} + + +u8 +MptToMgntRate( + IN ULONG MptRateIdx + ) +{ +// Mapped to MGN_XXX defined in MgntGen.h + switch (MptRateIdx) + { + /* CCK rate. */ + case MPT_RATE_1M: return MGN_1M; + case MPT_RATE_2M: return MGN_2M; + case MPT_RATE_55M: return MGN_5_5M; + case MPT_RATE_11M: return MGN_11M; + + /* OFDM rate. */ + case MPT_RATE_6M: return MGN_6M; + case MPT_RATE_9M: return MGN_9M; + case MPT_RATE_12M: return MGN_12M; + case MPT_RATE_18M: return MGN_18M; + case MPT_RATE_24M: return MGN_24M; + case MPT_RATE_36M: return MGN_36M; + case MPT_RATE_48M: return MGN_48M; + case MPT_RATE_54M: return MGN_54M; + + /* HT rate. */ + case MPT_RATE_MCS0: return MGN_MCS0; + case MPT_RATE_MCS1: return MGN_MCS1; + case MPT_RATE_MCS2: return MGN_MCS2; + case MPT_RATE_MCS3: return MGN_MCS3; + case MPT_RATE_MCS4: return MGN_MCS4; + case MPT_RATE_MCS5: return MGN_MCS5; + case MPT_RATE_MCS6: return MGN_MCS6; + case MPT_RATE_MCS7: return MGN_MCS7; + case MPT_RATE_MCS8: return MGN_MCS8; + case MPT_RATE_MCS9: return MGN_MCS9; + case MPT_RATE_MCS10: return MGN_MCS10; + case MPT_RATE_MCS11: return MGN_MCS11; + case MPT_RATE_MCS12: return MGN_MCS12; + case MPT_RATE_MCS13: return MGN_MCS13; + case MPT_RATE_MCS14: return MGN_MCS14; + case MPT_RATE_MCS15: return MGN_MCS15; + case MPT_RATE_MCS16: return MGN_MCS16; + case MPT_RATE_MCS17: return MGN_MCS17; + case MPT_RATE_MCS18: return MGN_MCS18; + case MPT_RATE_MCS19: return MGN_MCS19; + case MPT_RATE_MCS20: return MGN_MCS20; + case MPT_RATE_MCS21: return MGN_MCS21; + case MPT_RATE_MCS22: return MGN_MCS22; + case MPT_RATE_MCS23: return MGN_MCS23; + case MPT_RATE_MCS24: return MGN_MCS24; + case MPT_RATE_MCS25: return MGN_MCS25; + case MPT_RATE_MCS26: return MGN_MCS26; + case MPT_RATE_MCS27: return MGN_MCS27; + case MPT_RATE_MCS28: return MGN_MCS28; + case MPT_RATE_MCS29: return MGN_MCS29; + case MPT_RATE_MCS30: return MGN_MCS30; + case MPT_RATE_MCS31: return MGN_MCS31; + + /* VHT rate. */ + case MPT_RATE_VHT1SS_MCS0: return MGN_VHT1SS_MCS0; + case MPT_RATE_VHT1SS_MCS1: return MGN_VHT1SS_MCS1; + case MPT_RATE_VHT1SS_MCS2: return MGN_VHT1SS_MCS2; + case MPT_RATE_VHT1SS_MCS3: return MGN_VHT1SS_MCS3; + case MPT_RATE_VHT1SS_MCS4: return MGN_VHT1SS_MCS4; + case MPT_RATE_VHT1SS_MCS5: return MGN_VHT1SS_MCS5; + case MPT_RATE_VHT1SS_MCS6: return MGN_VHT1SS_MCS6; + case MPT_RATE_VHT1SS_MCS7: return MGN_VHT1SS_MCS7; + case MPT_RATE_VHT1SS_MCS8: return MGN_VHT1SS_MCS8; + case MPT_RATE_VHT1SS_MCS9: return MGN_VHT1SS_MCS9; + case MPT_RATE_VHT2SS_MCS0: return MGN_VHT2SS_MCS0; + case MPT_RATE_VHT2SS_MCS1: return MGN_VHT2SS_MCS1; + case MPT_RATE_VHT2SS_MCS2: return MGN_VHT2SS_MCS2; + case MPT_RATE_VHT2SS_MCS3: return MGN_VHT2SS_MCS3; + case MPT_RATE_VHT2SS_MCS4: return MGN_VHT2SS_MCS4; + case MPT_RATE_VHT2SS_MCS5: return MGN_VHT2SS_MCS5; + case MPT_RATE_VHT2SS_MCS6: return MGN_VHT2SS_MCS6; + case MPT_RATE_VHT2SS_MCS7: return MGN_VHT2SS_MCS7; + case MPT_RATE_VHT2SS_MCS8: return MGN_VHT2SS_MCS8; + case MPT_RATE_VHT2SS_MCS9: return MGN_VHT2SS_MCS9; + case MPT_RATE_VHT3SS_MCS0: return MGN_VHT3SS_MCS0; + case MPT_RATE_VHT3SS_MCS1: return MGN_VHT3SS_MCS1; + case MPT_RATE_VHT3SS_MCS2: return MGN_VHT3SS_MCS2; + case MPT_RATE_VHT3SS_MCS3: return MGN_VHT3SS_MCS3; + case MPT_RATE_VHT3SS_MCS4: return MGN_VHT3SS_MCS4; + case MPT_RATE_VHT3SS_MCS5: return MGN_VHT3SS_MCS5; + case MPT_RATE_VHT3SS_MCS6: return MGN_VHT3SS_MCS6; + case MPT_RATE_VHT3SS_MCS7: return MGN_VHT3SS_MCS7; + case MPT_RATE_VHT3SS_MCS8: return MGN_VHT3SS_MCS8; + case MPT_RATE_VHT3SS_MCS9: return MGN_VHT3SS_MCS9; + case MPT_RATE_VHT4SS_MCS0: return MGN_VHT4SS_MCS0; + case MPT_RATE_VHT4SS_MCS1: return MGN_VHT4SS_MCS1; + case MPT_RATE_VHT4SS_MCS2: return MGN_VHT4SS_MCS2; + case MPT_RATE_VHT4SS_MCS3: return MGN_VHT4SS_MCS3; + case MPT_RATE_VHT4SS_MCS4: return MGN_VHT4SS_MCS4; + case MPT_RATE_VHT4SS_MCS5: return MGN_VHT4SS_MCS5; + case MPT_RATE_VHT4SS_MCS6: return MGN_VHT4SS_MCS6; + case MPT_RATE_VHT4SS_MCS7: return MGN_VHT4SS_MCS7; + case MPT_RATE_VHT4SS_MCS8: return MGN_VHT4SS_MCS8; + case MPT_RATE_VHT4SS_MCS9: return MGN_VHT4SS_MCS9; + + case MPT_RATE_LAST: // fully automatiMGN_VHT2SS_MCS1; + default: + DBG_871X("<===MptToMgntRate(), Invalid Rate: %d!!\n", MptRateIdx); + return 0x0; + } +} + + +u8 HwRateToMPTRate(u8 rate) +{ + u8 ret_rate = MGN_1M; + + switch (rate) { + case DESC_RATE1M: + ret_rate = MPT_RATE_1M; break; + case DESC_RATE2M: + ret_rate = MPT_RATE_2M; break; + case DESC_RATE5_5M: + ret_rate = MPT_RATE_55M; break; + case DESC_RATE11M: + ret_rate = MPT_RATE_11M; break; + case DESC_RATE6M: + ret_rate = MPT_RATE_6M; break; + case DESC_RATE9M: + ret_rate = MPT_RATE_9M; break; + case DESC_RATE12M: + ret_rate = MPT_RATE_12M; break; + case DESC_RATE18M: + ret_rate = MPT_RATE_18M; break; + case DESC_RATE24M: + ret_rate = MPT_RATE_24M; break; + case DESC_RATE36M: + ret_rate = MPT_RATE_36M; break; + case DESC_RATE48M: + ret_rate = MPT_RATE_48M; break; + case DESC_RATE54M: + ret_rate = MPT_RATE_54M; break; + case DESC_RATEMCS0: + ret_rate = MPT_RATE_MCS0; break; + case DESC_RATEMCS1: + ret_rate = MPT_RATE_MCS1; break; + case DESC_RATEMCS2: + ret_rate = MPT_RATE_MCS2; break; + case DESC_RATEMCS3: + ret_rate = MPT_RATE_MCS3; break; + case DESC_RATEMCS4: + ret_rate = MPT_RATE_MCS4; break; + case DESC_RATEMCS5: + ret_rate = MPT_RATE_MCS5; break; + case DESC_RATEMCS6: + ret_rate = MPT_RATE_MCS6; break; + case DESC_RATEMCS7: + ret_rate = MPT_RATE_MCS7; break; + case DESC_RATEMCS8: + ret_rate = MPT_RATE_MCS8; break; + case DESC_RATEMCS9: + ret_rate = MPT_RATE_MCS9; break; + case DESC_RATEMCS10: + ret_rate = MPT_RATE_MCS10; break; + case DESC_RATEMCS11: + ret_rate = MPT_RATE_MCS11; break; + case DESC_RATEMCS12: + ret_rate = MPT_RATE_MCS12; break; + case DESC_RATEMCS13: + ret_rate = MPT_RATE_MCS13; break; + case DESC_RATEMCS14: + ret_rate = MPT_RATE_MCS14; break; + case DESC_RATEMCS15: + ret_rate = MPT_RATE_MCS15; break; + case DESC_RATEMCS16: + ret_rate = MPT_RATE_MCS16; break; + case DESC_RATEMCS17: + ret_rate = MPT_RATE_MCS17; break; + case DESC_RATEMCS18: + ret_rate = MPT_RATE_MCS18; break; + case DESC_RATEMCS19: + ret_rate = MPT_RATE_MCS19; break; + case DESC_RATEMCS20: + ret_rate = MPT_RATE_MCS20; break; + case DESC_RATEMCS21: + ret_rate = MPT_RATE_MCS21; break; + case DESC_RATEMCS22: + ret_rate = MPT_RATE_MCS22; break; + case DESC_RATEMCS23: + ret_rate = MPT_RATE_MCS23; break; + case DESC_RATEMCS24: + ret_rate = MPT_RATE_MCS24; break; + case DESC_RATEMCS25: + ret_rate = MPT_RATE_MCS25; break; + case DESC_RATEMCS26: + ret_rate = MPT_RATE_MCS26; break; + case DESC_RATEMCS27: + ret_rate = MPT_RATE_MCS27; break; + case DESC_RATEMCS28: + ret_rate = MPT_RATE_MCS28; break; + case DESC_RATEMCS29: + ret_rate = MPT_RATE_MCS29; break; + case DESC_RATEMCS30: + ret_rate = MPT_RATE_MCS30; break; + case DESC_RATEMCS31: + ret_rate = MPT_RATE_MCS31; break; + case DESC_RATEVHTSS1MCS0: + ret_rate = MPT_RATE_VHT1SS_MCS0; break; + case DESC_RATEVHTSS1MCS1: + ret_rate = MPT_RATE_VHT1SS_MCS1; break; + case DESC_RATEVHTSS1MCS2: + ret_rate = MPT_RATE_VHT1SS_MCS2; break; + case DESC_RATEVHTSS1MCS3: + ret_rate = MPT_RATE_VHT1SS_MCS3; break; + case DESC_RATEVHTSS1MCS4: + ret_rate = MPT_RATE_VHT1SS_MCS4; break; + case DESC_RATEVHTSS1MCS5: + ret_rate = MPT_RATE_VHT1SS_MCS5; break; + case DESC_RATEVHTSS1MCS6: + ret_rate = MPT_RATE_VHT1SS_MCS6; break; + case DESC_RATEVHTSS1MCS7: + ret_rate = MPT_RATE_VHT1SS_MCS7; break; + case DESC_RATEVHTSS1MCS8: + ret_rate = MPT_RATE_VHT1SS_MCS8; break; + case DESC_RATEVHTSS1MCS9: + ret_rate = MPT_RATE_VHT1SS_MCS9; break; + case DESC_RATEVHTSS2MCS0: + ret_rate = MPT_RATE_VHT2SS_MCS0; break; + case DESC_RATEVHTSS2MCS1: + ret_rate = MPT_RATE_VHT2SS_MCS1; break; + case DESC_RATEVHTSS2MCS2: + ret_rate = MPT_RATE_VHT2SS_MCS2; break; + case DESC_RATEVHTSS2MCS3: + ret_rate = MPT_RATE_VHT2SS_MCS3; break; + case DESC_RATEVHTSS2MCS4: + ret_rate = MPT_RATE_VHT2SS_MCS4; break; + case DESC_RATEVHTSS2MCS5: + ret_rate = MPT_RATE_VHT2SS_MCS5; break; + case DESC_RATEVHTSS2MCS6: + ret_rate = MPT_RATE_VHT2SS_MCS6; break; + case DESC_RATEVHTSS2MCS7: + ret_rate = MPT_RATE_VHT2SS_MCS7; break; + case DESC_RATEVHTSS2MCS8: + ret_rate = MPT_RATE_VHT2SS_MCS8; break; + case DESC_RATEVHTSS2MCS9: + ret_rate = MPT_RATE_VHT2SS_MCS9; break; + case DESC_RATEVHTSS3MCS0: + ret_rate = MPT_RATE_VHT3SS_MCS0; break; + case DESC_RATEVHTSS3MCS1: + ret_rate = MPT_RATE_VHT3SS_MCS1; break; + case DESC_RATEVHTSS3MCS2: + ret_rate = MPT_RATE_VHT3SS_MCS2; break; + case DESC_RATEVHTSS3MCS3: + ret_rate = MPT_RATE_VHT3SS_MCS3; break; + case DESC_RATEVHTSS3MCS4: + ret_rate = MPT_RATE_VHT3SS_MCS4; break; + case DESC_RATEVHTSS3MCS5: + ret_rate = MPT_RATE_VHT3SS_MCS5; break; + case DESC_RATEVHTSS3MCS6: + ret_rate = MPT_RATE_VHT3SS_MCS6; break; + case DESC_RATEVHTSS3MCS7: + ret_rate = MPT_RATE_VHT3SS_MCS7; break; + case DESC_RATEVHTSS3MCS8: + ret_rate = MPT_RATE_VHT3SS_MCS8; break; + case DESC_RATEVHTSS3MCS9: + ret_rate = MPT_RATE_VHT3SS_MCS9; break; + case DESC_RATEVHTSS4MCS0: + ret_rate = MPT_RATE_VHT4SS_MCS0; break; + case DESC_RATEVHTSS4MCS1: + ret_rate = MPT_RATE_VHT4SS_MCS1; break; + case DESC_RATEVHTSS4MCS2: + ret_rate = MPT_RATE_VHT4SS_MCS2; break; + case DESC_RATEVHTSS4MCS3: + ret_rate = MPT_RATE_VHT4SS_MCS3; break; + case DESC_RATEVHTSS4MCS4: + ret_rate = MPT_RATE_VHT4SS_MCS4; break; + case DESC_RATEVHTSS4MCS5: + ret_rate = MPT_RATE_VHT4SS_MCS5; break; + case DESC_RATEVHTSS4MCS6: + ret_rate = MPT_RATE_VHT4SS_MCS6; break; + case DESC_RATEVHTSS4MCS7: + ret_rate = MPT_RATE_VHT4SS_MCS7; break; + case DESC_RATEVHTSS4MCS8: + ret_rate = MPT_RATE_VHT4SS_MCS8; break; + case DESC_RATEVHTSS4MCS9: + ret_rate = MPT_RATE_VHT4SS_MCS9; break; + + default: + DBG_871X("HwRateToMRate(): Non supported Rate [%x]!!!\n", rate); + break; + } + return ret_rate; +} + +u8 rtw_mpRateParseFunc(PADAPTER pAdapter, u8 *targetStr) +{ + u16 i=0; + u8* rateindex_Array[] = { "1M","2M","5.5M","11M","6M","9M","12M","18M","24M","36M","48M","54M", + "HTMCS0","HTMCS1","HTMCS2","HTMCS3","HTMCS4","HTMCS5","HTMCS6","HTMCS7", + "HTMCS8","HTMCS9","HTMCS10","HTMCS11","HTMCS12","HTMCS13","HTMCS14","HTMCS15", + "HTMCS16","HTMCS17","HTMCS18","HTMCS19","HTMCS20","HTMCS21","HTMCS22","HTMCS23", + "HTMCS24","HTMCS25","HTMCS26","HTMCS27","HTMCS28","HTMCS29","HTMCS30","HTMCS31", + "VHT1MCS0","VHT1MCS1","VHT1MCS2","VHT1MCS3","VHT1MCS4","VHT1MCS5","VHT1MCS6","VHT1MCS7","VHT1MCS8","VHT1MCS9", + "VHT2MCS0","VHT2MCS1","VHT2MCS2","VHT2MCS3","VHT2MCS4","VHT2MCS5","VHT2MCS6","VHT2MCS7","VHT2MCS8","VHT2MCS9", + "VHT3MCS0","VHT3MCS1","VHT3MCS2","VHT3MCS3","VHT3MCS4","VHT3MCS5","VHT3MCS6","VHT3MCS7","VHT3MCS8","VHT3MCS9", + "VHT4MCS0","VHT4MCS1","VHT4MCS2","VHT4MCS3","VHT4MCS4","VHT4MCS5","VHT4MCS6","VHT4MCS7","VHT4MCS8","VHT4MCS9"}; + + for(i=0;i<=83;i++){ + if(strcmp(targetStr, rateindex_Array[i]) == 0){ + DBG_871X("%s , index = %d \n",__func__ ,i); + return i; + } + } + + printk("%s ,please input a Data RATE String as:",__func__); + for(i=0;i<=83;i++){ + printk("%s ",rateindex_Array[i]); + if(i%10==0) + printk("\n"); + } + return _FAIL; +} + +ULONG mpt_ProQueryCalTxPower( + PADAPTER pAdapter, + u8 RfPath + ) +{ + + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + + ULONG TxPower = 1, PwrGroup=0, PowerDiffByRate=0; + u1Byte limit = 0, rate = 0; + u8 mgn_rate = MptToMgntRate(pMptCtx->MptRateIndex); + + #if defined(CONFIG_RTL8188E) + if (IS_HARDWARE_TYPE_8188E(pAdapter)) + TxPower = PHY_GetTxPowerIndex_8188E(pAdapter, RfPath, mgn_rate, pHalData->CurrentChannelBW, pHalData->CurrentChannel); + #endif + + #if defined(CONFIG_RTL8723B) + if (IS_HARDWARE_TYPE_8723B(pAdapter)) + TxPower = PHY_GetTxPowerIndex_8723B(pAdapter, RfPath, mgn_rate, pHalData->CurrentChannelBW, pHalData->CurrentChannel); + #endif + + #if defined(CONFIG_RTL8192E) + if (IS_HARDWARE_TYPE_8192E(pAdapter)) + TxPower = PHY_GetTxPowerIndex_8192E(pAdapter, RfPath, mgn_rate, pHalData->CurrentChannelBW, pHalData->CurrentChannel); + #endif + + #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) + if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) + TxPower = PHY_GetTxPowerIndex_8812A(pAdapter, RfPath, mgn_rate, pHalData->CurrentChannelBW, pHalData->CurrentChannel); + #endif + + #if defined(CONFIG_RTL8814A) + if (IS_HARDWARE_TYPE_8814A(pAdapter)) + TxPower = PHY_GetTxPowerIndex_8814A(pAdapter, RfPath, mgn_rate, pHalData->CurrentChannelBW, pHalData->CurrentChannel); + #endif + #if defined(CONFIG_RTL8703B) + if (IS_HARDWARE_TYPE_8703B(pAdapter)) + TxPower = PHY_GetTxPowerIndex_8703B(pAdapter, RfPath, mgn_rate, pHalData->CurrentChannelBW, pHalData->CurrentChannel); + #endif + + #if defined(CONFIG_RTL8188F) + if (IS_HARDWARE_TYPE_8188F(pAdapter)) + TxPower = PHY_GetTxPowerIndex_8188F(pAdapter, RfPath, mgn_rate, pHalData->CurrentChannelBW, pHalData->CurrentChannel); + #endif + + DBG_8192C("txPower=%d ,CurrentChannelBW=%d ,CurrentChannel=%d ,rate =%d\n", + TxPower, pHalData->CurrentChannelBW, pHalData->CurrentChannel, mgn_rate); + + pAdapter->mppriv.txpoweridx = (u8)TxPower; + pMptCtx->TxPwrLevel[ODM_RF_PATH_A] = (u8)TxPower; + pMptCtx->TxPwrLevel[ODM_RF_PATH_B] = (u8)TxPower; + pMptCtx->TxPwrLevel[ODM_RF_PATH_C] = (u8)TxPower; + pMptCtx->TxPwrLevel[ODM_RF_PATH_D] = (u8)TxPower; + hal_mpt_SetTxPower(pAdapter); + + return TxPower; +} + +#ifdef CONFIG_MP_VHT_HW_TX_MODE +static inline void dump_buf(u8 *buf, u32 len) +{ + u32 i; + + DBG_871X("-----------------Len %d----------------\n", len); + for (i = 0; i < len; i++) + DBG_871X("%2.2x-", *(buf + i)); + DBG_871X("\n"); +} + +void ByteToBit( + UCHAR *out, + bool *in, + UCHAR in_size) +{ + UCHAR i = 0, j = 0; + + for (i = 0; i < in_size; i++) { + for (j = 0; j < 8; j++) { + if (in[8*i+j]) + out[i] |= (1 << j); + } + } +} + + +void CRC16_generator( + bool *out, + bool *in, + UCHAR in_size +) +{ + UCHAR i = 0; + bool temp = 0, reg[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}; + + for (i = 0; i < in_size; i++) {/* take one's complement and bit reverse*/ + temp = in[i]^reg[15]; + reg[15] = reg[14]; + reg[14] = reg[13]; + reg[13] = reg[12]; + reg[12] = reg[11]; + reg[11] = reg[10]; + reg[10] = reg[9]; + reg[9] = reg[8]; + reg[8] = reg[7]; + + reg[7] = reg[6]; + reg[6] = reg[5]; + reg[5] = reg[4]; + reg[4] = reg[3]; + reg[3] = reg[2]; + reg[2] = reg[1]; + reg[1] = reg[0]; + reg[12] = reg[12] ^ temp; + reg[5] = reg[5] ^ temp; + reg[0] = temp; + } + for (i = 0; i < 16; i++) /* take one's complement and bit reverse*/ + out[i] = 1-reg[15-i]; +} + + + +/*======================================== + SFD SIGNAL SERVICE LENGTH CRC + 16 bit 8 bit 8 bit 16 bit 16 bit +========================================*/ +void CCK_generator( + PRT_PMAC_TX_INFO pPMacTxInfo, + PRT_PMAC_PKT_INFO pPMacPktInfo + ) +{ + double ratio = 0; + bool crc16_in[32] = {0}, crc16_out[16] = {0}; + bool LengthExtBit; + double LengthExact; + double LengthPSDU; + UCHAR i; + UINT PacketLength = pPMacTxInfo->PacketLength; + + if (pPMacTxInfo->bSPreamble) + pPMacTxInfo->SFD = 0x05CF; + else + pPMacTxInfo->SFD = 0xF3A0; + + switch (pPMacPktInfo->MCS) { + case 0: + pPMacTxInfo->SignalField = 0xA; + ratio = 8; + /*CRC16_in(1,0:7)=[0 1 0 1 0 0 0 0]*/ + crc16_in[1] = crc16_in[3] = 1; + break; + case 1: + pPMacTxInfo->SignalField = 0x14; + ratio = 4; + /*CRC16_in(1,0:7)=[0 0 1 0 1 0 0 0];*/ + crc16_in[2] = crc16_in[4] = 1; + break; + case 2: + pPMacTxInfo->SignalField = 0x37; + ratio = 8.0/5.5; + /*CRC16_in(1,0:7)=[1 1 1 0 1 1 0 0];*/ + crc16_in[0] = crc16_in[1] = crc16_in[2] = crc16_in[4] = crc16_in[5] = 1; + break; + case 3: + pPMacTxInfo->SignalField = 0x6E; + ratio = 8.0/11.0; + /*CRC16_in(1,0:7)=[0 1 1 1 0 1 1 0];*/ + crc16_in[1] = crc16_in[2] = crc16_in[3] = crc16_in[5] = crc16_in[6] = 1; + break; + } + + LengthExact = PacketLength*ratio; + LengthPSDU = ceil(LengthExact); + + if ((pPMacPktInfo->MCS == 3) && + ((LengthPSDU-LengthExact) >= 0.727 || (LengthPSDU-LengthExact) <= -0.727)) + LengthExtBit = 1; + else + LengthExtBit = 0; + + + pPMacTxInfo->LENGTH = (UINT)LengthPSDU; + /* CRC16_in(1,16:31) = LengthPSDU[0:15]*/ + for (i = 0; i < 16; i++) + crc16_in[i+16] = (pPMacTxInfo->LENGTH >> i) & 0x1; + + if (LengthExtBit == 0) { + pPMacTxInfo->ServiceField = 0x0; + /* CRC16_in(1,8:15) = [0 0 0 0 0 0 0 0];*/ + } else { + pPMacTxInfo->ServiceField = 0x80; + /*CRC16_in(1,8:15)=[0 0 0 0 0 0 0 1];*/ + crc16_in[15] = 1; + } + + CRC16_generator(crc16_out, crc16_in, 32); + + _rtw_memset(pPMacTxInfo->CRC16, 0, 2); + ByteToBit(pPMacTxInfo->CRC16, crc16_out, 2); + +} + + +void PMAC_Get_Pkt_Param( + PRT_PMAC_TX_INFO pPMacTxInfo, + PRT_PMAC_PKT_INFO pPMacPktInfo) +{ + + UCHAR TX_RATE_HEX = 0, MCS = 0; + UCHAR TX_RATE = pPMacTxInfo->TX_RATE; + + /* TX_RATE & Nss */ + if (MPT_IS_2SS_RATE(TX_RATE)) + pPMacPktInfo->Nss = 2; + else if (MPT_IS_3SS_RATE(TX_RATE)) + pPMacPktInfo->Nss = 3; + else if (MPT_IS_4SS_RATE(TX_RATE)) + pPMacPktInfo->Nss = 4; + else + pPMacPktInfo->Nss = 1; + + DBG_871X("PMacTxInfo.Nss =%d\n", pPMacPktInfo->Nss); + + /* MCS & TX_RATE_HEX*/ + if (MPT_IS_CCK_RATE(TX_RATE)) { + switch (TX_RATE) { + case MPT_RATE_1M: + TX_RATE_HEX = MCS = 0; break; + case MPT_RATE_2M: + TX_RATE_HEX = MCS = 1; break; + case MPT_RATE_55M: + TX_RATE_HEX = MCS = 2; break; + case MPT_RATE_11M: + TX_RATE_HEX = MCS = 3; break; + } + } else if (MPT_IS_OFDM_RATE(TX_RATE)) { + MCS = TX_RATE - MPT_RATE_6M; + TX_RATE_HEX = MCS + 4; + } else if (MPT_IS_HT_RATE(TX_RATE)) { + MCS = TX_RATE - MPT_RATE_MCS0; + TX_RATE_HEX = MCS + 12; + } else if (MPT_IS_VHT_RATE(TX_RATE)) { + TX_RATE_HEX = TX_RATE - MPT_RATE_VHT1SS_MCS0 + 44; + + if (MPT_IS_VHT_2S_RATE(TX_RATE)) + MCS = TX_RATE - MPT_RATE_VHT2SS_MCS0; + else if (MPT_IS_VHT_3S_RATE(TX_RATE)) + MCS = TX_RATE - MPT_RATE_VHT3SS_MCS0; + else if (MPT_IS_VHT_4S_RATE(TX_RATE)) + MCS = TX_RATE - MPT_RATE_VHT4SS_MCS0; + else + MCS = TX_RATE - MPT_RATE_VHT1SS_MCS0; + } + + pPMacPktInfo->MCS = MCS; + pPMacTxInfo->TX_RATE_HEX = TX_RATE_HEX; + + DBG_871X(" MCS=%d, TX_RATE_HEX =0x%x\n", MCS, pPMacTxInfo->TX_RATE_HEX); + /* mSTBC & Nsts*/ + pPMacPktInfo->Nsts = pPMacPktInfo->Nss; + if (pPMacTxInfo->bSTBC) { + if (pPMacPktInfo->Nss == 1) { + pPMacTxInfo->m_STBC = 2; + pPMacPktInfo->Nsts = pPMacPktInfo->Nss*2; + } else + pPMacTxInfo->m_STBC = 1; + } else + pPMacTxInfo->m_STBC = 1; +} + + +UINT LDPC_parameter_generator( + UINT N_pld_int, + UINT N_CBPSS, + UINT N_SS, + UINT R, + UINT m_STBC, + UINT N_TCB_int +) +{ + double CR = 0.; + double N_pld = (double)N_pld_int; + double N_TCB = (double)N_TCB_int; + double N_CW = 0., N_shrt = 0., N_spcw = 0., N_fshrt = 0.; + double L_LDPC = 0., K_LDPC = 0., L_LDPC_info = 0.; + double N_punc = 0., N_ppcw = 0., N_fpunc = 0., N_rep = 0., N_rpcw = 0., N_frep = 0.; + double R_eff = 0.; + UINT VHTSIGA2B3 = 0;/* extra symbol from VHT-SIG-A2 Bit 3*/ + + if (R == 0) + CR = 0.5; + else if (R == 1) + CR = 2./3.; + else if (R == 2) + CR = 3./4.; + else if (R == 3) + CR = 5./6.; + + if (N_TCB <= 648.) { + N_CW = 1.; + if (N_TCB >= N_pld+912.*(1.-CR)) + L_LDPC = 1296.; + else + L_LDPC = 648.; + } else if (N_TCB <= 1296.) { + N_CW = 1.; + if (N_TCB >= (double)N_pld + 1464.*(1.-CR)) + L_LDPC = 1944.; + else + L_LDPC = 1296.; + } else if (N_TCB <= 1944.) { + N_CW = 1.; + L_LDPC = 1944.; + } else if (N_TCB <= 2592.) { + N_CW = 2.; + if (N_TCB >= N_pld+2916.*(1.-CR)) + L_LDPC = 1944.; + else + L_LDPC = 1296.; + } else { + N_CW = ceil(N_pld/1944./CR); + L_LDPC = 1944.; + } + /* Number of information bits per CW*/ + K_LDPC = L_LDPC*CR; + /* Number of shortening bits max(0, (N_CW * L_LDPC * R) - N_pld)*/ + N_shrt = (N_CW*K_LDPC-N_pld) > 0. ? (N_CW*K_LDPC-N_pld) : 0.; + /* Number of shortening bits per CW N_spcw = rtfloor(N_shrt/N_CW)*/ + N_spcw = rtfloor(N_shrt/N_CW); + /* The first N_fshrt CWs shorten 1 bit more*/ + N_fshrt = (double)((int)N_shrt % (int)N_CW); + /* Number of data bits for the last N_CW-N_fshrt CWs*/ + L_LDPC_info = K_LDPC-N_spcw; + /* Number of puncturing bits*/ + N_punc = (N_CW*L_LDPC-N_TCB-N_shrt) > 0. ? (N_CW*L_LDPC-N_TCB-N_shrt) : 0.; + if (((N_punc > .1 * N_CW * L_LDPC * (1.-CR)) && (N_shrt < 1.2 * N_punc * CR/(1.-CR))) || + (N_punc > 0.3*N_CW*L_LDPC*(1.-CR))) { + /*cout << "*** N_TCB and N_punc are Recomputed ***" << endl;*/ + VHTSIGA2B3 = 1; + N_TCB += (double)N_CBPSS*N_SS*m_STBC; + N_punc = (N_CW*L_LDPC-N_TCB-N_shrt) > 0. ? (N_CW*L_LDPC-N_TCB-N_shrt) : 0.; + } else + VHTSIGA2B3 = 0; + + return VHTSIGA2B3; +} /* function end of LDPC_parameter_generator */ + +/*======================================== + Data field of PPDU + Get N_sym and SIGA2BB3 +========================================*/ +void PMAC_Nsym_generator( + PRT_PMAC_TX_INFO pPMacTxInfo, + PRT_PMAC_PKT_INFO pPMacPktInfo) +{ + UINT SIGA2B3 = 0; + UCHAR TX_RATE = pPMacTxInfo->TX_RATE; + + UINT R, R_list[10] = {0, 0, 2, 0, 2, 1, 2, 3, 2, 3}; + double CR = 0; + UINT N_SD, N_BPSC_list[10] = {1, 2, 2, 4, 4, 6, 6, 6, 8, 8}; + UINT N_BPSC = 0, N_CBPS = 0, N_DBPS = 0, N_ES = 0, N_SYM = 0, N_pld = 0, N_TCB = 0; + int D_R = 0; + + DBG_871X("TX_RATE = %d\n", TX_RATE); + /* N_SD*/ + if (pPMacTxInfo->BandWidth == 0) + N_SD = 52; + else if (pPMacTxInfo->BandWidth == 1) + N_SD = 108; + else + N_SD = 234; + + if (MPT_IS_HT_RATE(TX_RATE)) { + UCHAR MCS_temp; + + if (pPMacPktInfo->MCS > 23) + MCS_temp = pPMacPktInfo->MCS - 24; + else if (pPMacPktInfo->MCS > 15) + MCS_temp = pPMacPktInfo->MCS - 16; + else if (pPMacPktInfo->MCS > 7) + MCS_temp = pPMacPktInfo->MCS - 8; + else + MCS_temp = pPMacPktInfo->MCS; + + R = R_list[MCS_temp]; + + switch (R) { + case 0: + CR = .5; break; + case 1: + CR = 2./3.; break; + case 2: + CR = 3./4.; break; + case 3: + CR = 5./6.; break; + } + + N_BPSC = N_BPSC_list[MCS_temp]; + N_CBPS = N_BPSC*N_SD*pPMacPktInfo->Nss; + N_DBPS = (UINT)((double)N_CBPS*CR); + + if (pPMacTxInfo->bLDPC == FALSE) { + N_ES = (UINT)ceil((double)(N_DBPS * pPMacPktInfo->Nss)/4./300.); + DBG_871X("N_ES = %d\n", N_ES); + + /* N_SYM = m_STBC* (8*length+16+6*N_ES) / (m_STBC*N_DBPS)*/ + N_SYM = pPMacTxInfo->m_STBC*(UINT)ceil((double)(pPMacTxInfo->PacketLength*8+16+N_ES*6)/ + (double)(N_DBPS*pPMacTxInfo->m_STBC)); + + } else { + N_ES = 1; + /* N_pld = length * 8 + 16*/ + N_pld = pPMacTxInfo->PacketLength*8+16; + DBG_871X("N_pld = %d\n", N_pld); + N_SYM = pPMacTxInfo->m_STBC*(UINT)ceil((double)(N_pld)/ + (double)(N_DBPS*pPMacTxInfo->m_STBC)); + DBG_871X("N_SYM = %d\n", N_SYM); + /* N_avbits = N_CBPS *m_STBC *(N_pld/N_CBPS*R*m_STBC)*/ + N_TCB = N_CBPS*N_SYM; + DBG_871X("N_TCB = %d\n", N_TCB); + SIGA2B3 = LDPC_parameter_generator(N_pld, N_CBPS, pPMacPktInfo->Nss, R, pPMacTxInfo->m_STBC, N_TCB); + DBG_871X("SIGA2B3 = %d\n", SIGA2B3); + N_SYM = N_SYM + SIGA2B3*pPMacTxInfo->m_STBC; + DBG_871X("N_SYM = %d\n", N_SYM); + } + } else if (MPT_IS_VHT_RATE(TX_RATE)) { + R = R_list[pPMacPktInfo->MCS]; + + switch (R) { + case 0: + CR = .5; break; + case 1: + CR = 2./3.; break; + case 2: + CR = 3./4.; break; + case 3: + CR = 5./6.; break; + } + N_BPSC = N_BPSC_list[pPMacPktInfo->MCS]; + N_CBPS = N_BPSC*N_SD*pPMacPktInfo->Nss; + N_DBPS = (UINT)((double)N_CBPS*CR); + if (pPMacTxInfo->bLDPC == FALSE) { + if (pPMacTxInfo->bSGI) + N_ES = (UINT)ceil((double)(N_DBPS)/3.6/600.); + else + N_ES = (UINT)ceil((double)(N_DBPS)/4./600.); + /* N_SYM = m_STBC* (8*length+16+6*N_ES) / (m_STBC*N_DBPS)*/ + N_SYM = pPMacTxInfo->m_STBC*(UINT)ceil((double)(pPMacTxInfo->PacketLength*8+16+N_ES*6)/(double)(N_DBPS*pPMacTxInfo->m_STBC)); + SIGA2B3 = 0; + } else { + N_ES = 1; + /* N_SYM = m_STBC* (8*length+N_service) / (m_STBC*N_DBPS)*/ + N_SYM = pPMacTxInfo->m_STBC*(UINT)ceil((double)(pPMacTxInfo->PacketLength*8+16)/(double)(N_DBPS*pPMacTxInfo->m_STBC)); + /* N_avbits = N_sys_init * N_CBPS*/ + N_TCB = N_CBPS * N_SYM; + /* N_pld = N_sys_init * N_DBPS*/ + N_pld = N_SYM * N_DBPS; + SIGA2B3 = LDPC_parameter_generator(N_pld, N_CBPS, pPMacPktInfo->Nss, R, pPMacTxInfo->m_STBC, N_TCB); + N_SYM = N_SYM + SIGA2B3*pPMacTxInfo->m_STBC; + } + + switch (R) { + case 0: + D_R = 2; break; + case 1: + D_R = 3; break; + case 2: + D_R = 4; break; + case 3: + D_R = 6; break; + } + + if (((N_CBPS/N_ES)%D_R) != 0) { + DBG_871X("MCS= %d is not supported when Nss=%d and BW= %d !!\n", pPMacPktInfo->MCS, pPMacPktInfo->Nss, pPMacTxInfo->BandWidth); + return; + } + + DBG_871X("MCS= %d Nss=%d and BW= %d !!\n", pPMacPktInfo->MCS, pPMacPktInfo->Nss, pPMacTxInfo->BandWidth); + } + + pPMacPktInfo->N_sym = N_SYM; + pPMacPktInfo->SIGA2B3 = SIGA2B3; +} + +/*======================================== + L-SIG Rate R Length P Tail + 4b 1b 12b 1b 6b +========================================*/ + +void L_SIG_generator( + UINT N_SYM, /* Max: 750*/ + PRT_PMAC_TX_INFO pPMacTxInfo, + PRT_PMAC_PKT_INFO pPMacPktInfo) +{ + u8 sig_bi[24] = {0}; /* 24 BIT*/ + UINT mode, LENGTH; + int i; + + if (MPT_IS_OFDM_RATE(pPMacTxInfo->TX_RATE)) { + mode = pPMacPktInfo->MCS; + LENGTH = pPMacTxInfo->PacketLength; + } else { + UCHAR N_LTF; + double T_data; + UINT OFDM_symbol; + + mode = 0; + + /* Table 20-13 Num of HT-DLTFs request*/ + if (pPMacPktInfo->Nsts <= 2) + N_LTF = pPMacPktInfo->Nsts; + else + N_LTF = 4; + + if (pPMacTxInfo->bSGI) + T_data = 3.6; + else + T_data = 4.0; + + /*(L-SIG, HT-SIG, HT-STF, HT-LTF....HT-LTF, Data)*/ + if (MPT_IS_VHT_RATE(pPMacTxInfo->TX_RATE)) + OFDM_symbol = (UINT)ceil((double)(8+4+N_LTF*4+N_SYM*T_data+4)/4.); + else + OFDM_symbol = (UINT)ceil((double)(8+4+N_LTF*4+N_SYM*T_data)/4.); + + DBG_871X("%s , OFDM_symbol =%d\n", __func__, OFDM_symbol); + LENGTH = OFDM_symbol*3-3; + DBG_871X("%s , LENGTH =%d\n", __func__, LENGTH); + + } + /* Rate Field*/ + switch (mode) { + case 0: + sig_bi[0] = 1; sig_bi[1] = 1; sig_bi[2] = 0; sig_bi[3] = 1; + break; + case 1: + sig_bi[0] = 1; sig_bi[1] = 1; sig_bi[2] = 1; sig_bi[3] = 1; + break; + case 2: + sig_bi[0] = 0; sig_bi[1] = 1; sig_bi[2] = 0; sig_bi[3] = 1; + break; + case 3: + sig_bi[0] = 0; sig_bi[1] = 1; sig_bi[2] = 1; sig_bi[3] = 1; + break; + case 4: + sig_bi[0] = 1; sig_bi[1] = 0; sig_bi[2] = 0; sig_bi[3] = 1; + break; + case 5: + sig_bi[0] = 1; sig_bi[1] = 0; sig_bi[2] = 1; sig_bi[3] = 1; + break; + case 6: + sig_bi[0] = 0; sig_bi[1] = 0; sig_bi[2] = 0; sig_bi[3] = 1; + break; + case 7: + sig_bi[0] = 0; sig_bi[1] = 0; sig_bi[2] = 1; sig_bi[3] = 1; + break; + } + /*Reserved bit*/ + sig_bi[4] = 0; + + /* Length Field*/ + for (i = 0; i < 12; i++) + sig_bi[i+5] = (LENGTH>>i) & 1; + + /* Parity Bit*/ + sig_bi[17] = 0; + for (i = 0; i < 17; i++) + sig_bi[17] = sig_bi[17] + sig_bi[i]; + + sig_bi[17] %= 2; + + /* Tail Field*/ + for (i = 18; i < 24; i++) + sig_bi[i] = 0; + + /* dump_buf(sig_bi,24);*/ + _rtw_memset(pPMacTxInfo->LSIG, 0, 3); + ByteToBit(pPMacTxInfo->LSIG, (bool *)sig_bi, 3); +} + + +void CRC8_generator( + bool *out, + bool *in, + UCHAR in_size + ) +{ + UCHAR i = 0; + bool temp = 0, reg[] = {1, 1, 1, 1, 1, 1, 1, 1}; + + for (i = 0; i < in_size; i++) { /* take one's complement and bit reverse*/ + temp = in[i]^reg[7]; + reg[7] = reg[6]; + reg[6] = reg[5]; + reg[5] = reg[4]; + reg[4] = reg[3]; + reg[3] = reg[2]; + reg[2] = reg[1] ^ temp; + reg[1] = reg[0] ^ temp; + reg[0] = temp; + } + for (i = 0; i < 8; i++)/* take one's complement and bit reverse*/ + out[i] = reg[7-i]^1; + } + +/*/================================================================================ + HT-SIG1 MCS CW Length 24BIT + 24BIT + 7b 1b 16b + HT-SIG2 Smoothing Not sounding Rsvd AGG STBC FEC SGI N_ELTF CRC Tail + 1b 1b 1b 1b 2b 1b 1b 2b 8b 6b +================================================================================*/ +void HT_SIG_generator( + PRT_PMAC_TX_INFO pPMacTxInfo, + PRT_PMAC_PKT_INFO pPMacPktInfo + ) +{ + UINT i; + bool sig_bi[48] = {0}, crc8[8] = {0}; + /* MCS Field*/ + for (i = 0; i < 7; i++) + sig_bi[i] = (pPMacPktInfo->MCS >> i) & 0x1; + /* Packet BW Setting*/ + sig_bi[7] = pPMacTxInfo->BandWidth; + /* HT-Length Field*/ + for (i = 0; i < 16; i++) + sig_bi[i+8] = (pPMacTxInfo->PacketLength >> i) & 0x1; + /* Smoothing; 1->allow smoothing*/ + sig_bi[24] = 1; + /*Not Sounding*/ + sig_bi[25] = 1-pPMacTxInfo->NDP_sound; + /*Reserved bit*/ + sig_bi[26] = 1; + /*/Aggregate*/ + sig_bi[27] = 0; + /*STBC Field*/ + if (pPMacTxInfo->bSTBC) { + sig_bi[28] = 1; + sig_bi[29] = 0; + } else { + sig_bi[28] = 0; + sig_bi[29] = 0; + } + /*Advance Coding, 0: BCC, 1: LDPC*/ + sig_bi[30] = pPMacTxInfo->bLDPC; + /* Short GI*/ + sig_bi[31] = pPMacTxInfo->bSGI; + /* N_ELTFs*/ + if (pPMacTxInfo->NDP_sound == FALSE) { + sig_bi[32] = 0; + sig_bi[33] = 0; + } else { + int N_ELTF = pPMacTxInfo->Ntx - pPMacPktInfo->Nss; + + for (i = 0; i < 2; i++) + sig_bi[32+i] = (N_ELTF>>i)%2; + } + /* CRC-8*/ + CRC8_generator(crc8, sig_bi, 34); + + for (i = 0; i < 8; i++) + sig_bi[34+i] = crc8[i]; + + /*Tail*/ + for (i = 42; i < 48; i++) + sig_bi[i] = 0; + + _rtw_memset(pPMacTxInfo->HT_SIG, 0, 6); + ByteToBit(pPMacTxInfo->HT_SIG, sig_bi, 6); +} + + +/*====================================================================================== + VHT-SIG-A1 + BW Reserved STBC G_ID SU_Nsts P_AID TXOP_PS_NOT_ALLOW Reserved + 2b 1b 1b 6b 3b 9b 1b 2b 1b + VHT-SIG-A2 + SGI SGI_Nsym SU/MU coding LDPC_Extra SU_NCS Beamformed Reserved CRC Tail + 1b 1b 1b 1b 4b 1b 1b 8b 6b +======================================================================================*/ +void VHT_SIG_A_generator( + PRT_PMAC_TX_INFO pPMacTxInfo, + PRT_PMAC_PKT_INFO pPMacPktInfo) +{ + UINT i; + bool sig_bi[48], crc8[8]; + + _rtw_memset(sig_bi, 0, 48); + _rtw_memset(crc8, 0, 8); + + /* BW Setting*/ + for (i = 0; i < 2; i++) + sig_bi[i] = (pPMacTxInfo->BandWidth>>i) & 0x1; + /* Reserved Bit*/ + sig_bi[2] = 1; + /*STBC Field*/ + sig_bi[3] = pPMacTxInfo->bSTBC; + /*Group ID: Single User -> A value of 0 or 63 indicates an SU PPDU. */ + for (i = 0; i < 6; i++) + sig_bi[4+i] = 0; + /* N_STS/Partial AID*/ + for (i = 0; i < 12; i++) { + if (i < 3) + sig_bi[10+i] = ((pPMacPktInfo->Nsts - 1)>>i) & 0x1; + else + sig_bi[10+i] = 0; + } + /*TXOP_PS_NOT_ALLPWED*/ + sig_bi[22] = 0; + /*Reserved Bits*/ + sig_bi[23] = 1; + /*Short GI*/ + sig_bi[24] = pPMacTxInfo->bSGI; + if (pPMacTxInfo->bSGI > 0 && (pPMacPktInfo->N_sym%10) == 9) + sig_bi[25] = 1; + else + sig_bi[25] = 0; + /* SU/MU[0] Coding*/ + sig_bi[26] = pPMacTxInfo->bLDPC; /* 0:BCC, 1:LDPC */ + sig_bi[27] = pPMacPktInfo->SIGA2B3; /*/ Record Extra OFDM Symols is added or not when LDPC is used*/ + /*SU MCS/MU[1-3] Coding*/ + for (i = 0; i < 4; i++) + sig_bi[28+i] = (pPMacPktInfo->MCS>>i) & 0x1; + /*SU Beamform */ + sig_bi[32] = 0; /*packet.TXBF_en;*/ + /*Reserved Bit*/ + sig_bi[33] = 1; + /*CRC-8*/ + CRC8_generator(crc8, sig_bi, 34); + for (i = 0; i < 8; i++) + sig_bi[34+i] = crc8[i]; + /*Tail*/ + for (i = 42; i < 48; i++) + sig_bi[i] = 0; + + _rtw_memset(pPMacTxInfo->VHT_SIG_A, 0, 6); + ByteToBit(pPMacTxInfo->VHT_SIG_A, sig_bi, 6); +} + +/*====================================================================================== + VHT-SIG-B + Length Resesrved Trail + 17/19/21 BIT 3/2/2 BIT 6b +======================================================================================*/ +void VHT_SIG_B_generator( + PRT_PMAC_TX_INFO pPMacTxInfo) +{ + bool sig_bi[32], crc8_bi[8]; + UINT i, len, res, tail = 6, total_len, crc8_in_len; + UINT sigb_len; + + _rtw_memset(sig_bi, 0, 32); + _rtw_memset(crc8_bi, 0, 8); + + /*Sounding Packet*/ + if (pPMacTxInfo->NDP_sound == 1) { + if (pPMacTxInfo->BandWidth == 0) { + bool sigb_temp[26] = {0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0}; + + _rtw_memcpy(sig_bi, sigb_temp, 26); + } else if (pPMacTxInfo->BandWidth == 1) { + bool sigb_temp[27] = {1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0}; + + _rtw_memcpy(sig_bi, sigb_temp, 27); + } else if (pPMacTxInfo->BandWidth == 2) { + bool sigb_temp[29] = {0, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0}; + + _rtw_memcpy(sig_bi, sigb_temp, 29); + } + } else { /* Not NDP Sounding*/ + bool *sigb_temp[29] = {0}; + + if (pPMacTxInfo->BandWidth == 0) { + len = 17; res = 3; + } else if (pPMacTxInfo->BandWidth == 1) { + len = 19; res = 2; + } else if (pPMacTxInfo->BandWidth == 2) { + len = 21; res = 2; + } else { + len = 21; res = 2; + } + total_len = len+res+tail; + crc8_in_len = len+res; + + /*Length Field*/ + sigb_len = (pPMacTxInfo->PacketLength + 3) >> 2; + + for (i = 0; i < len; i++) + sig_bi[i] = (sigb_len>>i) & 0x1; + /*Reserved Field*/ + for (i = 0; i < res; i++) + sig_bi[len+i] = 1; + /* CRC-8*/ + CRC8_generator(crc8_bi, sig_bi, crc8_in_len); + + /* Tail */ + for (i = 0; i < tail; i++) + sig_bi[len+res+i] = 0; + } + + _rtw_memset(pPMacTxInfo->VHT_SIG_B, 0, 4); + ByteToBit(pPMacTxInfo->VHT_SIG_B, sig_bi, 4); + + pPMacTxInfo->VHT_SIG_B_CRC = 0; + ByteToBit(&(pPMacTxInfo->VHT_SIG_B_CRC), crc8_bi, 1); +} + +/*======================= + VHT Delimiter +=======================*/ +void VHT_Delimiter_generator( + PRT_PMAC_TX_INFO pPMacTxInfo + ) +{ + bool sig_bi[32] = {0}, crc8[8] = {0}; + UINT crc8_in_len = 16; + UINT PacketLength = pPMacTxInfo->PacketLength; + int j; + + /* Delimiter[0]: EOF*/ + sig_bi[0] = 1; + /* Delimiter[1]: Reserved*/ + sig_bi[1] = 0; + /* Delimiter[3:2]: MPDU Length High*/ + sig_bi[2] = ((PacketLength - 4) >> 12) % 2; + sig_bi[3] = ((PacketLength - 4) >> 13) % 2; + /* Delimiter[15:4]: MPDU Length Low*/ + for (j = 4; j < 16; j++) + sig_bi[j] = ((PacketLength - 4) >> (j-4)) % 2; + CRC8_generator(crc8, sig_bi, crc8_in_len); + for (j = 16; j < 24; j++) /* Delimiter[23:16]: CRC 8*/ + sig_bi[j] = crc8[j-16]; + for (j = 24; j < 32; j++) /* Delimiter[31:24]: Signature ('4E' in Hex, 78 in Dec)*/ + sig_bi[j] = (78 >> (j-24)) % 2; + + _rtw_memset(pPMacTxInfo->VHT_Delimiter, 0, 4); + ByteToBit(pPMacTxInfo->VHT_Delimiter, sig_bi, 4); +} + +#endif +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_mp_ioctl.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_mp_ioctl.c new file mode 100644 index 000000000..ff0c66b38 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_mp_ioctl.c @@ -0,0 +1,2946 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_MP_IOCTL_C_ + +#include +#include +#include "../hal/phydm/phydm_precomp.h" + +//**************** oid_rtl_seg_81_85 section start **************** +NDIS_STATUS oid_rt_wireless_mode_hdl(struct oid_par_priv *poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + if (poid_par_priv->information_buf_len < sizeof(u8)) + return NDIS_STATUS_INVALID_LENGTH; + + if (poid_par_priv->type_of_oid == SET_OID) { + Adapter->registrypriv.wireless_mode = *(u8*)poid_par_priv->information_buf; + } else if (poid_par_priv->type_of_oid == QUERY_OID) { + *(u8*)poid_par_priv->information_buf = Adapter->registrypriv.wireless_mode; + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + RT_TRACE(_module_mp_, _drv_info_, ("-query Wireless Mode=%d\n", Adapter->registrypriv.wireless_mode)); + } else { + status = NDIS_STATUS_NOT_ACCEPTED; + } + +_func_exit_; + + return status; +} +//**************** oid_rtl_seg_81_87_80 section start **************** +NDIS_STATUS oid_rt_pro_write_bb_reg_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + struct bb_reg_param *pbbreg; + u16 offset; + u32 value; + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_write_bb_reg_hdl\n")); + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + if (poid_par_priv->information_buf_len < sizeof(struct bb_reg_param)) + return NDIS_STATUS_INVALID_LENGTH; + + pbbreg = (struct bb_reg_param *)(poid_par_priv->information_buf); + + offset = (u16)(pbbreg->offset) & 0xFFF; //0ffset :0x800~0xfff + if (offset < BB_REG_BASE_ADDR) offset |= BB_REG_BASE_ADDR; + + value = pbbreg->value; + + RT_TRACE(_module_mp_, _drv_notice_, + ("oid_rt_pro_write_bb_reg_hdl: offset=0x%03X value=0x%08X\n", + offset, value)); + + _irqlevel_changed_(&oldirql, LOWER); + write_bbreg(Adapter, offset, 0xFFFFFFFF, value); + _irqlevel_changed_(&oldirql, RAISE); + +_func_exit_; + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_read_bb_reg_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + struct bb_reg_param *pbbreg; + u16 offset; + u32 value; + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_read_bb_reg_hdl\n")); + + if (poid_par_priv->type_of_oid != QUERY_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + if (poid_par_priv->information_buf_len < sizeof(struct bb_reg_param)) + return NDIS_STATUS_INVALID_LENGTH; + + pbbreg = (struct bb_reg_param *)(poid_par_priv->information_buf); + + offset = (u16)(pbbreg->offset) & 0xFFF; //0ffset :0x800~0xfff + if (offset < BB_REG_BASE_ADDR) offset |= BB_REG_BASE_ADDR; + + _irqlevel_changed_(&oldirql, LOWER); + value = read_bbreg(Adapter, offset, 0xFFFFFFFF); + _irqlevel_changed_(&oldirql, RAISE); + + pbbreg->value = value; + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + + RT_TRACE(_module_mp_, _drv_notice_, + ("-oid_rt_pro_read_bb_reg_hdl: offset=0x%03X value:0x%08X\n", + offset, value)); +_func_exit_; + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_write_rf_reg_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + struct rf_reg_param *pbbreg; + u8 path; + u8 offset; + u32 value; + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_write_rf_reg_hdl\n")); + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + if (poid_par_priv->information_buf_len < sizeof(struct rf_reg_param)) + return NDIS_STATUS_INVALID_LENGTH; + + pbbreg = (struct rf_reg_param *)(poid_par_priv->information_buf); + + if (pbbreg->path >= MAX_RF_PATH_NUMS) + return NDIS_STATUS_NOT_ACCEPTED; + if (pbbreg->offset > 0xFF) + return NDIS_STATUS_NOT_ACCEPTED; + if (pbbreg->value > 0xFFFFF) + return NDIS_STATUS_NOT_ACCEPTED; + + path = (u8)pbbreg->path; + offset = (u8)pbbreg->offset; + value = pbbreg->value; + + RT_TRACE(_module_mp_, _drv_notice_, + ("oid_rt_pro_write_rf_reg_hdl: path=%d offset=0x%02X value=0x%05X\n", + path, offset, value)); + + _irqlevel_changed_(&oldirql, LOWER); + write_rfreg(Adapter, path, offset, value); + _irqlevel_changed_(&oldirql, RAISE); + +_func_exit_; + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_read_rf_reg_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + struct rf_reg_param *pbbreg; + u8 path; + u8 offset; + u32 value; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_read_rf_reg_hdl\n")); + + if (poid_par_priv->type_of_oid != QUERY_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + if (poid_par_priv->information_buf_len < sizeof(struct rf_reg_param)) + return NDIS_STATUS_INVALID_LENGTH; + + pbbreg = (struct rf_reg_param *)(poid_par_priv->information_buf); + + if (pbbreg->path >= MAX_RF_PATH_NUMS) + return NDIS_STATUS_NOT_ACCEPTED; + if (pbbreg->offset > 0xFF) + return NDIS_STATUS_NOT_ACCEPTED; + + path = (u8)pbbreg->path; + offset = (u8)pbbreg->offset; + + _irqlevel_changed_(&oldirql, LOWER); + value = read_rfreg(Adapter, path, offset); + _irqlevel_changed_(&oldirql, RAISE); + + pbbreg->value = value; + + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + + RT_TRACE(_module_mp_, _drv_notice_, + ("-oid_rt_pro_read_rf_reg_hdl: path=%d offset=0x%02X value=0x%05X\n", + path, offset, value)); + +_func_exit_; + + return status; +} +//**************** oid_rtl_seg_81_87_00 section end**************** +//------------------------------------------------------------------------------ + +//**************** oid_rtl_seg_81_80_00 section start **************** +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_set_data_rate_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + u32 ratevalue;//4 + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_notice_, + ("+oid_rt_pro_set_data_rate_hdl\n")); + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + if (poid_par_priv->information_buf_len != sizeof(u32)) + return NDIS_STATUS_INVALID_LENGTH; + + ratevalue = *((u32*)poid_par_priv->information_buf);//4 + RT_TRACE(_module_mp_, _drv_notice_, + ("oid_rt_pro_set_data_rate_hdl: data rate idx=%d\n", ratevalue)); + if (ratevalue >= MPT_RATE_LAST) + return NDIS_STATUS_INVALID_DATA; + + Adapter->mppriv.rateidx = ratevalue; + + _irqlevel_changed_(&oldirql, LOWER); + SetDataRate(Adapter); + _irqlevel_changed_(&oldirql, RAISE); + +_func_exit_; + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_start_test_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + u32 mode; + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_start_test_hdl\n")); + + if (Adapter->registrypriv.mp_mode == 0) + return NDIS_STATUS_NOT_ACCEPTED; + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + _irqlevel_changed_(&oldirql, LOWER); + + //IQCalibrateBcut(Adapter); + + mode = *((u32*)poid_par_priv->information_buf); + Adapter->mppriv.mode = mode;// 1 for loopback + + if (mp_start_test(Adapter) == _FAIL) { + status = NDIS_STATUS_NOT_ACCEPTED; + goto exit; + } + +exit: + _irqlevel_changed_(&oldirql, RAISE); + + RT_TRACE(_module_mp_, _drv_notice_, ("-oid_rt_pro_start_test_hdl: mp_mode=%d\n", Adapter->mppriv.mode)); + +_func_exit_; + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_stop_test_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_notice_, ("+Set OID_RT_PRO_STOP_TEST\n")); + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + _irqlevel_changed_(&oldirql, LOWER); + mp_stop_test(Adapter); + _irqlevel_changed_(&oldirql, RAISE); + + RT_TRACE(_module_mp_, _drv_notice_, ("-Set OID_RT_PRO_STOP_TEST\n")); + +_func_exit_; + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_set_channel_direct_call_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + u32 Channel; + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_set_channel_direct_call_hdl\n")); + + if (poid_par_priv->information_buf_len != sizeof(u32)) + return NDIS_STATUS_INVALID_LENGTH; + + if (poid_par_priv->type_of_oid == QUERY_OID) { + *((u32*)poid_par_priv->information_buf) = Adapter->mppriv.channel; + return NDIS_STATUS_SUCCESS; + } + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + Channel = *((u32*)poid_par_priv->information_buf); + RT_TRACE(_module_mp_, _drv_notice_, ("oid_rt_pro_set_channel_direct_call_hdl: Channel=%d\n", Channel)); + if (Channel > 14) + return NDIS_STATUS_NOT_ACCEPTED; + Adapter->mppriv.channel = Channel; + + _irqlevel_changed_(&oldirql, LOWER); + SetChannel(Adapter); + _irqlevel_changed_(&oldirql, RAISE); + +_func_exit_; + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_set_bandwidth_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + u16 bandwidth; + u16 channel_offset; + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_info_, + ("+oid_rt_set_bandwidth_hdl\n")); + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + if (poid_par_priv->information_buf_len < sizeof(u32)) + return NDIS_STATUS_INVALID_LENGTH; + + bandwidth = *((u32*)poid_par_priv->information_buf);//4 + channel_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + + if (bandwidth != CHANNEL_WIDTH_40) + bandwidth = CHANNEL_WIDTH_20; + padapter->mppriv.bandwidth = (u8)bandwidth; + padapter->mppriv.prime_channel_offset = (u8)channel_offset; + + _irqlevel_changed_(&oldirql, LOWER); + SetBandwidth(padapter); + _irqlevel_changed_(&oldirql, RAISE); + + RT_TRACE(_module_mp_, _drv_notice_, + ("-oid_rt_set_bandwidth_hdl: bandwidth=%d channel_offset=%d\n", + bandwidth, channel_offset)); + +_func_exit_; + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_set_antenna_bb_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + u32 antenna; + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_set_antenna_bb_hdl\n")); + + if (poid_par_priv->information_buf_len != sizeof(u32)) + return NDIS_STATUS_INVALID_LENGTH; + + if (poid_par_priv->type_of_oid == SET_OID) + { + antenna = *(u32*)poid_par_priv->information_buf; + + Adapter->mppriv.antenna_tx = (u16)((antenna & 0xFFFF0000) >> 16); + Adapter->mppriv.antenna_rx = (u16)(antenna & 0x0000FFFF); + RT_TRACE(_module_mp_, _drv_notice_, + ("oid_rt_pro_set_antenna_bb_hdl: tx_ant=0x%04x rx_ant=0x%04x\n", + Adapter->mppriv.antenna_tx, Adapter->mppriv.antenna_rx)); + + _irqlevel_changed_(&oldirql, LOWER); + SetAntenna(Adapter); + _irqlevel_changed_(&oldirql, RAISE); + } else { + antenna = (Adapter->mppriv.antenna_tx << 16)|Adapter->mppriv.antenna_rx; + *(u32*)poid_par_priv->information_buf = antenna; + } + +_func_exit_; + + return status; +} + +NDIS_STATUS oid_rt_pro_set_tx_power_control_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + u32 tx_pwr_idx; + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_pro_set_tx_power_control_hdl\n")); + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + if (poid_par_priv->information_buf_len != sizeof(u32)) + return NDIS_STATUS_INVALID_LENGTH; + + tx_pwr_idx = *((u32*)poid_par_priv->information_buf); + if (tx_pwr_idx > MAX_TX_PWR_INDEX_N_MODE) + return NDIS_STATUS_NOT_ACCEPTED; + + Adapter->mppriv.txpoweridx = (u8)tx_pwr_idx; + + RT_TRACE(_module_mp_, _drv_notice_, + ("oid_rt_pro_set_tx_power_control_hdl: idx=0x%2x\n", + Adapter->mppriv.txpoweridx)); + + _irqlevel_changed_(&oldirql, LOWER); + SetTxPower(Adapter); + _irqlevel_changed_(&oldirql, RAISE); + +_func_exit_; + + return status; +} + +//------------------------------------------------------------------------------ +//**************** oid_rtl_seg_81_80_20 section start **************** +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_query_tx_packet_sent_hdl(struct oid_par_priv *poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + if (poid_par_priv->type_of_oid !=QUERY_OID) { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + if (poid_par_priv->information_buf_len == sizeof(ULONG)) { + *(ULONG*)poid_par_priv->information_buf = Adapter->mppriv.tx_pktcount; + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + } else { + status = NDIS_STATUS_INVALID_LENGTH; + } + +_func_exit_; + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_query_rx_packet_received_hdl(struct oid_par_priv *poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + if (poid_par_priv->type_of_oid != QUERY_OID) { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + RT_TRACE(_module_mp_, _drv_alert_, ("===> oid_rt_pro_query_rx_packet_received_hdl.\n")); + if (poid_par_priv->information_buf_len == sizeof(ULONG)) { + *(ULONG*)poid_par_priv->information_buf = Adapter->mppriv.rx_pktcount; + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + RT_TRACE(_module_mp_, _drv_alert_, ("recv_ok:%d \n",Adapter->mppriv.rx_pktcount)); + } else { + status = NDIS_STATUS_INVALID_LENGTH; + } + +_func_exit_; + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_query_rx_packet_crc32_error_hdl(struct oid_par_priv *poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + if (poid_par_priv->type_of_oid != QUERY_OID) { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + RT_TRACE(_module_mp_, _drv_alert_, ("===> oid_rt_pro_query_rx_packet_crc32_error_hdl.\n")); + if (poid_par_priv->information_buf_len == sizeof(ULONG)) { + *(ULONG*)poid_par_priv->information_buf = Adapter->mppriv.rx_crcerrpktcount; + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + RT_TRACE(_module_mp_, _drv_alert_, ("recv_err:%d \n",Adapter->mppriv.rx_crcerrpktcount)); + } else { + status = NDIS_STATUS_INVALID_LENGTH; + } + +_func_exit_; + + return status; +} +//------------------------------------------------------------------------------ + +NDIS_STATUS oid_rt_pro_reset_tx_packet_sent_hdl(struct oid_par_priv *poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + if (poid_par_priv->type_of_oid != SET_OID) { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + RT_TRACE(_module_mp_, _drv_alert_, ("===> oid_rt_pro_reset_tx_packet_sent_hdl.\n")); + Adapter->mppriv.tx_pktcount = 0; + +_func_exit_; + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_reset_rx_packet_received_hdl(struct oid_par_priv *poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + if (poid_par_priv->type_of_oid != SET_OID) + { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + if (poid_par_priv->information_buf_len == sizeof(ULONG)) { + Adapter->mppriv.rx_pktcount = 0; + Adapter->mppriv.rx_crcerrpktcount = 0; + } else { + status = NDIS_STATUS_INVALID_LENGTH; + } + +_func_exit_; + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_reset_phy_rx_packet_count_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + if (poid_par_priv->type_of_oid != SET_OID) { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + _irqlevel_changed_(&oldirql, LOWER); + ResetPhyRxPktCount(Adapter); + _irqlevel_changed_(&oldirql, RAISE); + +_func_exit_; + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_get_phy_rx_packet_received_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_get_phy_rx_packet_received_hdl\n")); + + if (poid_par_priv->type_of_oid != QUERY_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + if (poid_par_priv->information_buf_len != sizeof(ULONG)) + return NDIS_STATUS_INVALID_LENGTH; + + _irqlevel_changed_(&oldirql, LOWER); + *(ULONG*)poid_par_priv->information_buf = GetPhyRxPktReceived(Adapter); + _irqlevel_changed_(&oldirql, RAISE); + + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + + RT_TRACE(_module_mp_, _drv_notice_, ("-oid_rt_get_phy_rx_packet_received_hdl: recv_ok=%d\n", *(ULONG*)poid_par_priv->information_buf)); + +_func_exit_; + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_get_phy_rx_packet_crc32_error_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_get_phy_rx_packet_crc32_error_hdl\n")); + + if (poid_par_priv->type_of_oid != QUERY_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + + if (poid_par_priv->information_buf_len != sizeof(ULONG)) + return NDIS_STATUS_INVALID_LENGTH; + + _irqlevel_changed_(&oldirql, LOWER); + *(ULONG*)poid_par_priv->information_buf = GetPhyRxPktCRC32Error(Adapter); + _irqlevel_changed_(&oldirql, RAISE); + + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + + RT_TRACE(_module_mp_, _drv_info_, ("-oid_rt_get_phy_rx_packet_crc32_error_hdl: recv_err=%d\n", *(ULONG*)poid_par_priv->information_buf)); + +_func_exit_; + + return status; +} +//**************** oid_rtl_seg_81_80_20 section end **************** +NDIS_STATUS oid_rt_pro_set_continuous_tx_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + u32 bStartTest; + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_set_continuous_tx_hdl\n")); + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + bStartTest = *((u32*)poid_par_priv->information_buf); + + _irqlevel_changed_(&oldirql, LOWER); + SetContinuousTx(Adapter,(u8)bStartTest); + if (bStartTest) { + struct mp_priv *pmp_priv = &Adapter->mppriv; + if (pmp_priv->tx.stop == 0) { + pmp_priv->tx.stop = 1; + DBG_871X("%s: pkt tx is running...\n", __func__); + rtw_msleep_os(5); + } + pmp_priv->tx.stop = 0; + pmp_priv->tx.count = 1; + SetPacketTx(Adapter); + } + _irqlevel_changed_(&oldirql, RAISE); + +_func_exit_; + + return status; +} + +NDIS_STATUS oid_rt_pro_set_single_carrier_tx_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + u32 bStartTest; + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_alert_, ("+oid_rt_pro_set_single_carrier_tx_hdl\n")); + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + bStartTest = *((u32*)poid_par_priv->information_buf); + + _irqlevel_changed_(&oldirql, LOWER); + SetSingleCarrierTx(Adapter, (u8)bStartTest); + if (bStartTest) { + struct mp_priv *pmp_priv = &Adapter->mppriv; + if (pmp_priv->tx.stop == 0) { + pmp_priv->tx.stop = 1; + DBG_871X("%s: pkt tx is running...\n", __func__); + rtw_msleep_os(5); + } + pmp_priv->tx.stop = 0; + pmp_priv->tx.count = 1; + SetPacketTx(Adapter); + } + _irqlevel_changed_(&oldirql, RAISE); + +_func_exit_; + + return status; +} + +NDIS_STATUS oid_rt_pro_set_carrier_suppression_tx_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + u32 bStartTest; + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_set_carrier_suppression_tx_hdl\n")); + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + bStartTest = *((u32*)poid_par_priv->information_buf); + + _irqlevel_changed_(&oldirql, LOWER); + SetCarrierSuppressionTx(Adapter, (u8)bStartTest); + if (bStartTest) { + struct mp_priv *pmp_priv = &Adapter->mppriv; + if (pmp_priv->tx.stop == 0) { + pmp_priv->tx.stop = 1; + DBG_871X("%s: pkt tx is running...\n", __func__); + rtw_msleep_os(5); + } + pmp_priv->tx.stop = 0; + pmp_priv->tx.count = 1; + SetPacketTx(Adapter); + } + _irqlevel_changed_(&oldirql, RAISE); + +_func_exit_; + + return status; +} + +NDIS_STATUS oid_rt_pro_set_single_tone_tx_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + u32 bStartTest; + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_alert_, ("+oid_rt_pro_set_single_tone_tx_hdl\n")); + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + bStartTest = *((u32*)poid_par_priv->information_buf); + + _irqlevel_changed_(&oldirql, LOWER); + SetSingleToneTx(Adapter,(u8)bStartTest); + _irqlevel_changed_(&oldirql, RAISE); + +_func_exit_; + + return status; +} + +NDIS_STATUS oid_rt_pro_set_modulation_hdl(struct oid_par_priv* poid_par_priv) +{ + return 0; +} + +NDIS_STATUS oid_rt_pro_trigger_gpio_hdl(struct oid_par_priv *poid_par_priv) +{ + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + NDIS_STATUS status = NDIS_STATUS_SUCCESS; +_func_enter_; + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + _irqlevel_changed_(&oldirql, LOWER); + rtw_hal_set_hwreg(Adapter, HW_VAR_TRIGGER_GPIO_0, 0); + _irqlevel_changed_(&oldirql, RAISE); + +_func_exit_; + + return status; +} +//**************** oid_rtl_seg_81_80_00 section end **************** +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro8711_join_bss_hdl(struct oid_par_priv *poid_par_priv) +{ +#if 0 + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + + PNDIS_802_11_SSID pssid; + +_func_enter_; + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + *poid_par_priv->bytes_needed = (u32)sizeof(NDIS_802_11_SSID); + *poid_par_priv->bytes_rw = 0; + if (poid_par_priv->information_buf_len < *poid_par_priv->bytes_needed) + return NDIS_STATUS_INVALID_LENGTH; + + pssid = (PNDIS_802_11_SSID)poid_par_priv->information_buf; + + _irqlevel_changed_(&oldirql, LOWER); + + if (mp_start_joinbss(Adapter, pssid) == _FAIL) + status = NDIS_STATUS_NOT_ACCEPTED; + + _irqlevel_changed_(&oldirql, RAISE); + + *poid_par_priv->bytes_rw = sizeof(NDIS_802_11_SSID); + +_func_exit_; + + return status; +#else + return 0; +#endif +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_read_register_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + pRW_Reg RegRWStruct; + u32 offset, width; + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_info_, + ("+oid_rt_pro_read_register_hdl\n")); + + if (poid_par_priv->type_of_oid != QUERY_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + RegRWStruct = (pRW_Reg)poid_par_priv->information_buf; + offset = RegRWStruct->offset; + width = RegRWStruct->width; + + if (offset > 0xFFF) + return NDIS_STATUS_NOT_ACCEPTED; + + _irqlevel_changed_(&oldirql, LOWER); + + switch (width) { + case 1: + RegRWStruct->value = rtw_read8(Adapter, offset); + break; + case 2: + RegRWStruct->value = rtw_read16(Adapter, offset); + break; + default: + width = 4; + RegRWStruct->value = rtw_read32(Adapter, offset); + break; + } + RT_TRACE(_module_mp_, _drv_notice_, + ("oid_rt_pro_read_register_hdl: offset:0x%04X value:0x%X\n", + offset, RegRWStruct->value)); + + _irqlevel_changed_(&oldirql, RAISE); + + *poid_par_priv->bytes_rw = width; + +_func_exit_; + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_write_register_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + pRW_Reg RegRWStruct; + u32 offset, width, value; + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_info_, + ("+oid_rt_pro_write_register_hdl\n")); + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + RegRWStruct = (pRW_Reg)poid_par_priv->information_buf; + offset = RegRWStruct->offset; + width = RegRWStruct->width; + value = RegRWStruct->value; + + if (offset > 0xFFF) + return NDIS_STATUS_NOT_ACCEPTED; + + _irqlevel_changed_(&oldirql, LOWER); + + switch (RegRWStruct->width) + { + case 1: + if (value > 0xFF) { + status = NDIS_STATUS_NOT_ACCEPTED; + break; + } + rtw_write8(padapter, offset, (u8)value); + break; + case 2: + if (value > 0xFFFF) { + status = NDIS_STATUS_NOT_ACCEPTED; + break; + } + rtw_write16(padapter, offset, (u16)value); + break; + case 4: + rtw_write32(padapter, offset, value); + break; + default: + status = NDIS_STATUS_NOT_ACCEPTED; + break; + } + + _irqlevel_changed_(&oldirql, RAISE); + + RT_TRACE(_module_mp_, _drv_info_, + ("-oid_rt_pro_write_register_hdl: offset=0x%08X width=%d value=0x%X\n", + offset, width, value)); + +_func_exit_; + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_burst_read_register_hdl(struct oid_par_priv *poid_par_priv) +{ +#if 0 +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + pBurst_RW_Reg pBstRwReg; + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_burst_read_register_hdl\n")); + + if (poid_par_priv->type_of_oid != QUERY_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + pBstRwReg = (pBurst_RW_Reg)poid_par_priv->information_buf; + + _irqlevel_changed_(&oldirql, LOWER); + rtw_read_mem(padapter, pBstRwReg->offset, (u32)pBstRwReg->len, pBstRwReg->Data); + _irqlevel_changed_(&oldirql, RAISE); + + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + + RT_TRACE(_module_mp_, _drv_info_, ("-oid_rt_pro_burst_read_register_hdl\n")); + +_func_exit_; + + return status; +#else + return 0; +#endif +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_burst_write_register_hdl(struct oid_par_priv *poid_par_priv) +{ +#if 0 +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + pBurst_RW_Reg pBstRwReg; + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_burst_write_register_hdl\n")); + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + pBstRwReg = (pBurst_RW_Reg)poid_par_priv->information_buf; + + _irqlevel_changed_(&oldirql, LOWER); + rtw_write_mem(padapter, pBstRwReg->offset, (u32)pBstRwReg->len, pBstRwReg->Data); + _irqlevel_changed_(&oldirql, RAISE); + + RT_TRACE(_module_mp_, _drv_info_, ("-oid_rt_pro_burst_write_register_hdl\n")); + +_func_exit_; + + return status; +#else + return 0; +#endif +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_write_txcmd_hdl(struct oid_par_priv *poid_par_priv) +{ +#if 0 + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + + PADAPTER Adapter = (PADAPTER)( poid_par_priv->adapter_context); + +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + + TX_CMD_Desc *TxCmd_Info; + +_func_enter_; + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + RT_TRACE(_module_mp_, _drv_info_, ("+Set OID_RT_PRO_WRITE_TXCMD\n")); + + TxCmd_Info=(TX_CMD_Desc*)poid_par_priv->information_buf; + + RT_TRACE(_module_mp_, _drv_info_, ("WRITE_TXCMD:Addr=%.8X\n", TxCmd_Info->offset)); + RT_TRACE(_module_mp_, _drv_info_, ("WRITE_TXCMD:1.)%.8X\n", (ULONG)TxCmd_Info->TxCMD.value[0])); + RT_TRACE(_module_mp_, _drv_info_, ("WRITE_TXCMD:2.)%.8X\n", (ULONG)TxCmd_Info->TxCMD.value[1])); + RT_TRACE(_module_mp_, _drv_info_, (("WRITE_TXCMD:3.)%.8X\n", (ULONG)TxCmd_Info->TxCMD.value[2])); + RT_TRACE(_module_mp_, _drv_info_, ("WRITE_TXCMD:4.)%.8X\n", (ULONG)TxCmd_Info->TxCMD.value[3])); + + _irqlevel_changed_(&oldirql, LOWER); + + rtw_write32(Adapter, TxCmd_Info->offset + 0, (unsigned int)TxCmd_Info->TxCMD.value[0]); + rtw_write32(Adapter, TxCmd_Info->offset + 4, (unsigned int)TxCmd_Info->TxCMD.value[1]); + + _irqlevel_changed_(&oldirql, RAISE); + + RT_TRACE(_module_mp_, _drv_notice_, + ("-Set OID_RT_PRO_WRITE_TXCMD: status=0x%08X\n", status)); + +_func_exit_; + + return status; +#else + return 0; +#endif +} + +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_read16_eeprom_hdl(struct oid_par_priv *poid_par_priv) +{ +#if 0 +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + pEEPROM_RWParam pEEPROM; + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_info_, ("+Query OID_RT_PRO_READ16_EEPROM\n")); + + if (poid_par_priv->type_of_oid != QUERY_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + pEEPROM = (pEEPROM_RWParam)poid_par_priv->information_buf; + + _irqlevel_changed_(&oldirql, LOWER); + pEEPROM->value = eeprom_read16(padapter, (u16)(pEEPROM->offset >> 1)); + _irqlevel_changed_(&oldirql, RAISE); + + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + + RT_TRACE(_module_mp_, _drv_notice_, + ("-Query OID_RT_PRO_READ16_EEPROM: offset=0x%x value=0x%x\n", + pEEPROM->offset, pEEPROM->value)); + +_func_exit_; + + return status; +#else + return 0; +#endif +} + +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_write16_eeprom_hdl (struct oid_par_priv *poid_par_priv) +{ +#if 0 +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + pEEPROM_RWParam pEEPROM; + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_notice_, ("+Set OID_RT_PRO_WRITE16_EEPROM\n")); + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + pEEPROM = (pEEPROM_RWParam)poid_par_priv->information_buf; + + _irqlevel_changed_(&oldirql, LOWER); + eeprom_write16(padapter, (u16)(pEEPROM->offset >> 1), pEEPROM->value); + _irqlevel_changed_(&oldirql, RAISE); + + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + +_func_exit_; + + return status; +#else + return 0; +#endif +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro8711_wi_poll_hdl(struct oid_par_priv *poid_par_priv) +{ +#if 0 + PADAPTER Adapter = (PADAPTER)( poid_par_priv->adapter_context); + + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + + struct mp_wiparam *pwi_param; + +_func_enter_; + + if (poid_par_priv->type_of_oid != QUERY_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + if (poid_par_priv->information_buf_len < sizeof(struct mp_wiparam)) + return NDIS_STATUS_INVALID_LENGTH; + + if (Adapter->mppriv.workparam.bcompleted == _FALSE) + return NDIS_STATUS_NOT_ACCEPTED; + + pwi_param = (struct mp_wiparam *)poid_par_priv->information_buf; + + _rtw_memcpy(pwi_param, &Adapter->mppriv.workparam, sizeof(struct mp_wiparam)); + Adapter->mppriv.act_in_progress = _FALSE; +// RT_TRACE(_module_mp_, _drv_info_, ("rf:%x\n", pwiparam->IoValue)); + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + +_func_exit_; + + return status; +#else + return 0; +#endif +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro8711_pkt_loss_hdl(struct oid_par_priv *poid_par_priv) +{ +#if 0 + PADAPTER Adapter = (PADAPTER)( poid_par_priv->adapter_context); + + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro8711_pkt_loss_hdl\n")); + + if (poid_par_priv->type_of_oid != QUERY_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + if (poid_par_priv->information_buf_len < sizeof(uint)*2) { + RT_TRACE(_module_mp_, _drv_err_, ("-oid_rt_pro8711_pkt_loss_hdl: buf_len=%d\n", (int)poid_par_priv->information_buf_len)); + return NDIS_STATUS_INVALID_LENGTH; + } + + if (*(uint*)poid_par_priv->information_buf == 1)//init==1 + Adapter->mppriv.rx_pktloss = 0; + + *((uint*)poid_par_priv->information_buf+1) = Adapter->mppriv.rx_pktloss; + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + +_func_exit_; + + return status; +#else + return 0; +#endif +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_rd_attrib_mem_hdl(struct oid_par_priv *poid_par_priv) +{ +#if 0 + PADAPTER Adapter = (PADAPTER)( poid_par_priv->adapter_context); + struct io_queue *pio_queue = (struct io_queue *)Adapter->pio_queue; + struct intf_hdl *pintfhdl = &pio_queue->intf; + +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + +#ifdef CONFIG_SDIO_HCI + void (*_attrib_read)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); +#endif + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_notice_, ("+Query OID_RT_RD_ATTRIB_MEM\n")); + + if (poid_par_priv->type_of_oid != QUERY_OID) + return NDIS_STATUS_NOT_ACCEPTED; + +#ifdef CONFIG_SDIO_HCI + _irqlevel_changed_(&oldirql, LOWER); +{ + u32 *plmem = (u32*)poid_par_priv->information_buf+2; + _attrib_read = pintfhdl->io_ops._attrib_read; + _attrib_read(pintfhdl, *((u32*)poid_par_priv->information_buf), + *((u32*)poid_par_priv->information_buf+1), (u8*)plmem); + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; +} + _irqlevel_changed_(&oldirql, RAISE); +#endif + +_func_exit_; + + return status; +#else + return 0; +#endif +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_wr_attrib_mem_hdl (struct oid_par_priv *poid_par_priv) +{ +#if 0 + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + struct io_queue *pio_queue = (struct io_queue *)Adapter->pio_queue; + struct intf_hdl *pintfhdl = &pio_queue->intf; + +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + +#ifdef CONFIG_SDIO_HCI + void (*_attrib_write)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); +#endif + +_func_enter_; + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + +#ifdef CONFIG_SDIO_HCI + _irqlevel_changed_(&oldirql, LOWER); +{ + u32 *plmem = (u32*)poid_par_priv->information_buf + 2; + _attrib_write = pintfhdl->io_ops._attrib_write; + _attrib_write(pintfhdl, *(u32*)poid_par_priv->information_buf, + *((u32*)poid_par_priv->information_buf+1), (u8*)plmem); +} + _irqlevel_changed_(&oldirql, RAISE); +#endif + +_func_exit_; + + return status; +#else + return 0; +#endif +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_set_rf_intfs_hdl(struct oid_par_priv *poid_par_priv) +{ +#if 0 + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_notice_, ("+OID_RT_PRO_SET_RF_INTFS\n")); + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + _irqlevel_changed_(&oldirql, LOWER); + + if (rtw_setrfintfs_cmd(Adapter, *(unsigned char*)poid_par_priv->information_buf) == _FAIL) + status = NDIS_STATUS_NOT_ACCEPTED; + + _irqlevel_changed_(&oldirql, RAISE); + +_func_exit_; + + return status; +#else + return 0; +#endif +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_poll_rx_status_hdl(struct oid_par_priv *poid_par_priv) +{ +#if 0 + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + +_func_enter_; + + if (poid_par_priv->type_of_oid != QUERY_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + _rtw_memcpy(poid_par_priv->information_buf, (unsigned char*)&Adapter->mppriv.rxstat, sizeof(struct recv_stat)); + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + +_func_exit_; + + return status; +#else + return 0; +#endif +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_cfg_debug_message_hdl(struct oid_par_priv *poid_par_priv) +{ +#if 0 + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + + PCFG_DBG_MSG_STRUCT pdbg_msg; + +_func_enter_; + +// RT_TRACE(0xffffffffff,_drv_alert_,("===> oid_rt_pro_cfg_debug_message_hdl.\n")); + +#if 0//#ifdef CONFIG_DEBUG_RTL871X + + pdbg_msg = (PCFG_DBG_MSG_STRUCT)(poid_par_priv->information_buf); + + if (poid_par_priv->type_of_oid == SET_OID) { + RT_TRACE(0xffffffffff, _drv_alert_, + ("===>Set level :0x%08x, H32:0x%08x L32:0x%08x\n", + pdbg_msg->DebugLevel, pdbg_msg->DebugComponent_H32, pdbg_msg->DebugComponent_L32)); + + GlobalDebugLevel = pdbg_msg->DebugLevel; + GlobalDebugComponents = (pdbg_msg->DebugComponent_H32 << 32) | pdbg_msg->DebugComponent_L32; + RT_TRACE(0xffffffffff, _drv_alert_, + ("===> Set level :0x%08x, component:0x%016x\n", + GlobalDebugLevel, (u32)GlobalDebugComponents)); + } else { + pdbg_msg->DebugLevel = GlobalDebugLevel; + pdbg_msg->DebugComponent_H32 = (u32)(GlobalDebugComponents >> 32); + pdbg_msg->DebugComponent_L32 = (u32)GlobalDebugComponents; + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + + RT_TRACE(0xffffffffff, _drv_alert_, + ("===>Query level:0x%08x H32:0x%08x L32:0x%08x\n", + (u32)pdbg_msg->DebugLevel, (u32)pdbg_msg->DebugComponent_H32, (u32)pdbg_msg->DebugComponent_L32)); + } + +#endif + +_func_exit_; + + return status; +#else + return 0; +#endif +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_set_data_rate_ex_hdl(struct oid_par_priv *poid_par_priv) +{ + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_notice_, ("+OID_RT_PRO_SET_DATA_RATE_EX\n")); + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + _irqlevel_changed_(&oldirql, LOWER); + + if (rtw_setdatarate_cmd(Adapter, poid_par_priv->information_buf) !=_SUCCESS) + status = NDIS_STATUS_NOT_ACCEPTED; + + _irqlevel_changed_(&oldirql, RAISE); + +_func_exit_; + + return status; +} +//----------------------------------------------------------------------------- +NDIS_STATUS oid_rt_get_thermal_meter_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + u8 thermal = 0; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_get_thermal_meter_hdl\n")); + + if (poid_par_priv->type_of_oid != QUERY_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + if (poid_par_priv->information_buf_len < sizeof(u32)) + return NDIS_STATUS_INVALID_LENGTH; + + _irqlevel_changed_(&oldirql, LOWER); + GetThermalMeter(Adapter, &thermal); + _irqlevel_changed_(&oldirql, RAISE); + + *(u32*)poid_par_priv->information_buf = (u32)thermal; + *poid_par_priv->bytes_rw = sizeof(u32); + +_func_exit_; + + return status; +} +//----------------------------------------------------------------------------- +NDIS_STATUS oid_rt_pro_read_tssi_hdl(struct oid_par_priv *poid_par_priv) +{ +#if 0 + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_read_tssi_hdl\n")); + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + if (Adapter->mppriv.act_in_progress == _TRUE) + return NDIS_STATUS_NOT_ACCEPTED; + + if (poid_par_priv->information_buf_len < sizeof(u8)) + return NDIS_STATUS_INVALID_LENGTH; + + //init workparam + Adapter->mppriv.act_in_progress = _TRUE; + Adapter->mppriv.workparam.bcompleted = _FALSE; + Adapter->mppriv.workparam.act_type = MPT_READ_TSSI; + Adapter->mppriv.workparam.io_offset = 0; + Adapter->mppriv.workparam.io_value = 0xFFFFFFFF; + + _irqlevel_changed_(&oldirql, LOWER); + + if (!rtw_gettssi_cmd(Adapter,0, (u8*)&Adapter->mppriv.workparam.io_value)) + status = NDIS_STATUS_NOT_ACCEPTED; + + _irqlevel_changed_(&oldirql, RAISE); + +_func_exit_; + + return status; +#else + return 0; +#endif +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_set_power_tracking_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + + +_func_enter_; + +// if (poid_par_priv->type_of_oid != SET_OID) +// return NDIS_STATUS_NOT_ACCEPTED; + + if (poid_par_priv->information_buf_len < sizeof(u8)) + return NDIS_STATUS_INVALID_LENGTH; + + _irqlevel_changed_(&oldirql, LOWER); + if (poid_par_priv->type_of_oid == SET_OID) { + u8 enable; + + enable = *(u8*)poid_par_priv->information_buf; + RT_TRACE(_module_mp_, _drv_notice_, + ("+oid_rt_pro_set_power_tracking_hdl: enable=%d\n", enable)); + + SetPowerTracking(Adapter, enable); + } else { + GetPowerTracking(Adapter, (u8*)poid_par_priv->information_buf); + } + _irqlevel_changed_(&oldirql, RAISE); + +_func_exit_; + + return status; +} +//----------------------------------------------------------------------------- +NDIS_STATUS oid_rt_pro_set_basic_rate_hdl(struct oid_par_priv *poid_par_priv) +{ +#if 0 +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + u32 ratevalue; + u8 datarates[NumRates]; + int i; + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_info_, ("+OID_RT_PRO_SET_BASIC_RATE\n")); + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; +#if 0 + ratevalue = *((u32*)poid_par_priv->information_buf); + + for (i = 0; i < NumRates; i++) { + if (ratevalue == mpdatarate[i]) + datarates[i] = mpdatarate[i]; + else + datarates[i] = 0xff; + RT_TRACE(_module_rtl871x_ioctl_c_, _drv_info_, ("basicrate_inx=%d\n", datarates[i])); + } + + _irqlevel_changed_(&oldirql, LOWER); + + if (rtw_setbasicrate_cmd(padapter, datarates) != _SUCCESS) + status = NDIS_STATUS_NOT_ACCEPTED; + + _irqlevel_changed_(&oldirql, RAISE); +#endif + RT_TRACE(_module_mp_, _drv_notice_, + ("-OID_RT_PRO_SET_BASIC_RATE: status=0x%08X\n", status)); + +_func_exit_; + + return status; +#else + return 0; +#endif +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_qry_pwrstate_hdl(struct oid_par_priv *poid_par_priv) +{ +#if 0 + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + +_func_enter_; + + if (poid_par_priv->type_of_oid != QUERY_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + if (poid_par_priv->information_buf_len < 8) + return NDIS_STATUS_INVALID_LENGTH; + + *poid_par_priv->bytes_rw = 8; + _rtw_memcpy(poid_par_priv->information_buf, &(adapter_to_pwrctl(Adapter)->pwr_mode), 8); + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + + RT_TRACE(_module_mp_, _drv_notice_, + ("-oid_rt_pro_qry_pwrstate_hdl: pwr_mode=%d smart_ps=%d\n", + adapter_to_pwrctl(Adapter)->pwr_mode, adapter_to_pwrctl(Adapter)->smart_ps)); + +_func_exit_; + + return status; +#else + return 0; +#endif +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_set_pwrstate_hdl(struct oid_par_priv *poid_par_priv) +{ +#if 0 + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + + uint pwr_mode, smart_ps; + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_notice_, ("+Set OID_RT_PRO_SET_PWRSTATE\n")); + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + *poid_par_priv->bytes_rw = 0; + *poid_par_priv->bytes_needed = 8; + + if (poid_par_priv->information_buf_len < 8) + return NDIS_STATUS_INVALID_LENGTH; + + pwr_mode = *(uint *)(poid_par_priv->information_buf); + smart_ps = *(uint *)((int)poid_par_priv->information_buf + 4); + + *poid_par_priv->bytes_rw = 8; + +_func_exit_; + + return status; +#else + return 0; +#endif +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_h2c_set_rate_table_hdl(struct oid_par_priv *poid_par_priv) +{ +#if 0 + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + + struct setratable_parm *prate_table; + u8 res; + +_func_enter_; + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + *poid_par_priv->bytes_needed = sizeof(struct setratable_parm); + if (poid_par_priv->information_buf_len < sizeof(struct setratable_parm)) + return NDIS_STATUS_INVALID_LENGTH; + + prate_table = (struct setratable_parm*)poid_par_priv->information_buf; + + _irqlevel_changed_(&oldirql, LOWER); + res = rtw_setrttbl_cmd(Adapter, prate_table); + _irqlevel_changed_(&oldirql, RAISE); + + if (res == _FAIL) + status = NDIS_STATUS_FAILURE; + +_func_exit_; + + return status; +#else + return 0; +#endif +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_h2c_get_rate_table_hdl(struct oid_par_priv *poid_par_priv) +{ +#if 0 + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + +_func_enter_; + + if (poid_par_priv->type_of_oid != QUERY_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + #if 0 + struct mp_wi_cntx *pmp_wi_cntx=&(Adapter->mppriv.wi_cntx); + u8 res=_SUCCESS; + DEBUG_INFO(("===> Set OID_RT_PRO_H2C_GET_RATE_TABLE.\n")); + + if(pmp_wi_cntx->bmp_wi_progress ==_TRUE){ + DEBUG_ERR(("\n mp workitem is progressing, not allow to set another workitem right now!!!\n")); + Status = NDIS_STATUS_NOT_ACCEPTED; + break; + } + else{ + pmp_wi_cntx->bmp_wi_progress=_TRUE; + pmp_wi_cntx->param.bcompleted=_FALSE; + pmp_wi_cntx->param.act_type=MPT_GET_RATE_TABLE; + pmp_wi_cntx->param.io_offset=0x0; + pmp_wi_cntx->param.bytes_cnt=sizeof(struct getratable_rsp); + pmp_wi_cntx->param.io_value=0xffffffff; + + res=rtw_getrttbl_cmd(Adapter,(struct getratable_rsp *)pmp_wi_cntx->param.data); + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + if(res != _SUCCESS) + { + Status = NDIS_STATUS_NOT_ACCEPTED; + } + } + DEBUG_INFO(("\n <=== Set OID_RT_PRO_H2C_GET_RATE_TABLE.\n")); + #endif + +_func_exit_; + + return status; +#else + return 0; +#endif +} + +//**************** oid_rtl_seg_87_12_00 section start **************** +NDIS_STATUS oid_rt_pro_encryption_ctrl_hdl(struct oid_par_priv *poid_par_priv) +{ +#if 0 + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + struct security_priv *psecuritypriv = &Adapter->securitypriv; + + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + + ENCRY_CTRL_STATE encry_mode; + + + *poid_par_priv->bytes_needed = sizeof(u8); + if (poid_par_priv->information_buf_len < *poid_par_priv->bytes_needed) + return NDIS_STATUS_INVALID_LENGTH; + + if (poid_par_priv->type_of_oid == SET_OID) + { + encry_mode = *((u8*)poid_par_priv->information_buf); + switch (encry_mode) + { + case HW_CONTROL: + #if 0 + Adapter->registrypriv.software_decrypt=_FALSE; + Adapter->registrypriv.software_encrypt=_FALSE; + #else + psecuritypriv->sw_decrypt = _FALSE; + psecuritypriv->sw_encrypt = _FALSE; + #endif + break; + case SW_CONTROL: + #if 0 + Adapter->registrypriv.software_decrypt=_TRUE; + Adapter->registrypriv.software_encrypt=_TRUE; + #else + psecuritypriv->sw_decrypt = _TRUE; + psecuritypriv->sw_encrypt = _TRUE; + #endif + break; + case HW_ENCRY_SW_DECRY: + #if 0 + Adapter->registrypriv.software_decrypt=_TRUE; + Adapter->registrypriv.software_encrypt=_FALSE; + #else + psecuritypriv->sw_decrypt = _TRUE; + psecuritypriv->sw_encrypt = _FALSE; + #endif + break; + case SW_ENCRY_HW_DECRY: + #if 0 + Adapter->registrypriv.software_decrypt=_FALSE; + Adapter->registrypriv.software_encrypt=_TRUE; + #else + psecuritypriv->sw_decrypt = _FALSE; + psecuritypriv->sw_encrypt = _TRUE; + #endif + break; + } + + RT_TRACE(_module_rtl871x_ioctl_c_, _drv_notice_, + ("-oid_rt_pro_encryption_ctrl_hdl: SET encry_mode=0x%x sw_encrypt=0x%x sw_decrypt=0x%x\n", + encry_mode, psecuritypriv->sw_encrypt, psecuritypriv->sw_decrypt)); + } + else { + #if 0 + if (Adapter->registrypriv.software_encrypt == _FALSE) { + if (Adapter->registrypriv.software_decrypt == _FALSE) + encry_mode = HW_CONTROL; + else + encry_mode = HW_ENCRY_SW_DECRY; + } + else { + if (Adapter->registrypriv.software_decrypt == _FALSE) + encry_mode = SW_ENCRY_HW_DECRY; + else + encry_mode = SW_CONTROL; + } + #else + + if ((psecuritypriv->sw_encrypt == _FALSE) && (psecuritypriv->sw_decrypt == _FALSE)) + encry_mode = HW_CONTROL; + else if ((psecuritypriv->sw_encrypt == _FALSE) && (psecuritypriv->sw_decrypt == _TRUE)) + encry_mode = HW_ENCRY_SW_DECRY; + else if ((psecuritypriv->sw_encrypt == _TRUE) && (psecuritypriv->sw_decrypt == _FALSE)) + encry_mode = SW_ENCRY_HW_DECRY; + else if ((psecuritypriv->sw_encrypt == _TRUE) && (psecuritypriv->sw_decrypt == _TRUE)) + encry_mode = SW_CONTROL; + + #endif + + *(u8*)poid_par_priv->information_buf = encry_mode; + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + + RT_TRACE(_module_mp_, _drv_notice_, + ("-oid_rt_pro_encryption_ctrl_hdl: QUERY encry_mode=0x%x\n", + encry_mode)); + } + + return status; +#else + return 0; +#endif +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_add_sta_info_hdl(struct oid_par_priv *poid_par_priv) +{ +#if 0 + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + + struct sta_info *psta = NULL; + UCHAR *macaddr; + + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + *poid_par_priv->bytes_needed = ETH_ALEN; + if (poid_par_priv->information_buf_len < *poid_par_priv->bytes_needed) + return NDIS_STATUS_INVALID_LENGTH; + + macaddr = (UCHAR *) poid_par_priv->information_buf ; + + RT_TRACE(_module_rtl871x_ioctl_c_,_drv_notice_, + ("OID_RT_PRO_ADD_STA_INFO: addr="MAC_FMT"\n", MAC_ARG(macaddr) )); + + _irqlevel_changed_(&oldirql, LOWER); + + psta = rtw_get_stainfo(&Adapter->stapriv, macaddr); + + if (psta == NULL) { // the sta have been in sta_info_queue => do nothing + psta = rtw_alloc_stainfo(&Adapter->stapriv, macaddr); + + if (psta == NULL) { + RT_TRACE(_module_rtl871x_ioctl_c_,_drv_err_,("Can't alloc sta_info when OID_RT_PRO_ADD_STA_INFO\n")); + status = NDIS_STATUS_FAILURE; + } + } else { //(between drv has received this event before and fw have not yet to set key to CAM_ENTRY) + RT_TRACE(_module_rtl871x_ioctl_c_, _drv_err_, + ("Error: OID_RT_PRO_ADD_STA_INFO: sta has been in sta_hash_queue \n")); + } + + _irqlevel_changed_(&oldirql, RAISE); + + return status; +#else + return 0; +#endif +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_dele_sta_info_hdl(struct oid_par_priv *poid_par_priv) +{ +#if 0 + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + + struct sta_info *psta = NULL; + UCHAR *macaddr; + + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + *poid_par_priv->bytes_needed = ETH_ALEN; + if (poid_par_priv->information_buf_len < *poid_par_priv->bytes_needed) + return NDIS_STATUS_INVALID_LENGTH; + + macaddr = (UCHAR *) poid_par_priv->information_buf ; + RT_TRACE(_module_rtl871x_ioctl_c_,_drv_notice_, + ("+OID_RT_PRO_ADD_STA_INFO: addr="MAC_FMT"\n", MAC_ARG(macaddr) )); + + psta = rtw_get_stainfo(&Adapter->stapriv, macaddr); + if (psta != NULL) { + //_enter_critical(&(Adapter->stapriv.sta_hash_lock), &irqL); + rtw_free_stainfo(Adapter, psta); + //_exit_critical(&(Adapter->stapriv.sta_hash_lock), &irqL); + } + + return status; +#else + return 0; +#endif +} +//------------------------------------------------------------------------------ +#if 0 +static u32 mp_query_drv_var(_adapter *padapter, u8 offset, u32 var) +{ +#ifdef CONFIG_SDIO_HCI + + if (offset == 1) { + u16 tmp_blk_num; + tmp_blk_num = rtw_read16(padapter, SDIO_RX0_RDYBLK_NUM); + RT_TRACE(_module_mp_, _drv_err_, ("Query Information, mp_query_drv_var SDIO_RX0_RDYBLK_NUM=0x%x dvobj.rxblknum=0x%x\n", tmp_blk_num, adapter_to_dvobj(padapter)->rxblknum)); + if (adapter_to_dvobj(padapter)->rxblknum != tmp_blk_num) { + RT_TRACE(_module_mp_,_drv_err_, ("Query Information, mp_query_drv_var call recv rx\n")); + // sd_recv_rxfifo(padapter); + } + } + +#if 0 + if(offset <=100){ //For setting data rate and query data rate + if(offset==100){ //For query data rate + RT_TRACE(_module_mp_, _drv_emerg_, ("\n mp_query_drv_var: offset(%d): query rate=0x%.2x \n",offset,padapter->registrypriv.tx_rate)); + var=padapter->registrypriv.tx_rate; + + } + else if(offset<0x1d){ //For setting data rate + padapter->registrypriv.tx_rate=offset; + var=padapter->registrypriv.tx_rate; + padapter->registrypriv.use_rate=_TRUE; + RT_TRACE(_module_mp_, _drv_emerg_, ("\n mp_query_drv_var: offset(%d): set rate=0x%.2x \n",offset,padapter->registrypriv.tx_rate)); + } + else{ //not use the data rate + padapter->registrypriv.use_rate=_FALSE; + RT_TRACE(_module_mp_, _drv_emerg_, ("\n mp_query_drv_var: offset(%d) out of rate range\n",offset)); + } + } + else if (offset<=110){ //for setting debug level + RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var: offset(%d) for set debug level\n",offset)); + if(offset==110){ //For query data rate + RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var: offset(%d): query dbg level=0x%.2x \n",offset,padapter->registrypriv.dbg_level)); + padapter->registrypriv.dbg_level=GlobalDebugLevel; + var=padapter->registrypriv.dbg_level; + } + else if(offset<110 && offset>100){ + RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var: offset(%d): set dbg level=0x%.2x \n",offset,offset-100)); + padapter->registrypriv.dbg_level=GlobalDebugLevel=offset-100; + var=padapter->registrypriv.dbg_level; + RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var(_drv_emerg_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel)); + RT_TRACE(_module_mp_, _drv_alert_, (" mp_query_drv_var(_drv_alert_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel)); + RT_TRACE(_module_mp_, _drv_crit_, (" mp_query_drv_var(_drv_crit_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel)); + RT_TRACE(_module_mp_, _drv_err_, (" mp_query_drv_var(_drv_err_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel)); + RT_TRACE(_module_mp_, _drv_warning_, (" mp_query_drv_var(_drv_warning_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel)); + RT_TRACE(_module_mp_, _drv_notice_, (" mp_query_drv_var(_drv_notice_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel)); + RT_TRACE(_module_mp_, _drv_info_, (" mp_query_drv_var(_drv_info_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel)); + RT_TRACE(_module_mp_, _drv_debug_, (" mp_query_drv_var(_drv_debug_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel)); + + } + } + else if(offset >110 &&offset <116){ + if(115==offset){ + RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var(_drv_emerg_): offset(%d): query TRX access type: [tx_block_mode=%x,rx_block_mode=%x]\n",\ + offset, adapter_to_dvobj(padapter)->tx_block_mode, adapter_to_dvobj(padapter)->rx_block_mode)); + } + else { + switch(offset){ + case 111: + adapter_to_dvobj(padapter)->tx_block_mode=1; + adapter_to_dvobj(padapter)->rx_block_mode=1; + RT_TRACE(_module_mp_, _drv_emerg_, \ + (" mp_query_drv_var(_drv_emerg_): offset(%d): SET TRX access type:(TX block/RX block) [tx_block_mode=%x,rx_block_mode=%x]\n",\ + offset, adapter_to_dvobj(padapter)->tx_block_mode, adapter_to_dvobj(padapter)->rx_block_mode)); + break; + case 112: + adapter_to_dvobj(padapter)->tx_block_mode=1; + adapter_to_dvobj(padapter)->rx_block_mode=0; + RT_TRACE(_module_mp_, _drv_emerg_, \ + (" mp_query_drv_var(_drv_emerg_): offset(%d): SET TRX access type:(TX block/RX byte) [tx_block_mode=%x,rx_block_mode=%x]\n",\ + offset, adapter_to_dvobj(padapter)->tx_block_mode, adapter_to_dvobj(padapter)->rx_block_mode)); + break; + case 113: + adapter_to_dvobj(padapter)->tx_block_mode=0; + adapter_to_dvobj(padapter)->rx_block_mode=1; + RT_TRACE(_module_mp_, _drv_emerg_, \ + (" mp_query_drv_var(_drv_emerg_): offset(%d): SET TRX access type:(TX byte/RX block) [tx_block_mode=%x,rx_block_mode=%x]\n",\ + offset, adapter_to_dvobj(padapter)->tx_block_mode, adapter_to_dvobj(padapter)->rx_block_mode)); + break; + case 114: + adapter_to_dvobj(padapter)->tx_block_mode=0; + adapter_to_dvobj(padapter)->rx_block_mode=0; + RT_TRACE(_module_mp_, _drv_emerg_, \ + (" mp_query_drv_var(_drv_emerg_): offset(%d): SET TRX access type:(TX byte/RX byte) [tx_block_mode=%x,rx_block_mode=%x]\n",\ + offset, adapter_to_dvobj(padapter)->tx_block_mode, adapter_to_dvobj(padapter)->rx_block_mode)); + break; + default : + break; + + } + + } + + } + else if(offset>=127){ + u64 prnt_dbg_comp; + u8 chg_idx; + u64 tmp_dbg_comp; + chg_idx=offset-0x80; + tmp_dbg_comp=BIT(chg_idx); + prnt_dbg_comp=padapter->registrypriv.dbg_component= GlobalDebugComponents; + RT_TRACE(_module_mp_, _drv_emerg_, (" 1: mp_query_drv_var: offset(%d;0x%x):for dbg conpoment prnt_dbg_comp=0x%.16x GlobalDebugComponents=0x%.16x padapter->registrypriv.dbg_component=0x%.16x\n",offset,offset,prnt_dbg_comp,GlobalDebugComponents,padapter->registrypriv.dbg_component)); + if(offset==127){ + // prnt_dbg_comp=padapter->registrypriv.dbg_component= GlobalDebugComponents; + var=(u32)(padapter->registrypriv.dbg_component); + RT_TRACE(0xffffffff, _drv_emerg_, ("2: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h) \n",offset,offset,padapter->registrypriv.dbg_component,prnt_dbg_comp)); + prnt_dbg_comp=GlobalDebugComponents; + RT_TRACE(0xffffffff, _drv_emerg_, ("2-1: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h)\n",offset,offset,padapter->registrypriv.dbg_component,prnt_dbg_comp)); + prnt_dbg_comp=GlobalDebugComponents=padapter->registrypriv.dbg_component; + RT_TRACE(0xffffffff, _drv_emerg_, ("2-2: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h)\n",offset,offset,padapter->registrypriv.dbg_component,prnt_dbg_comp)); + + } + else{ + RT_TRACE(0xffffffff, _drv_emerg_, ("3: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h) chg_idx=%d\n",offset,offset,padapter->registrypriv.dbg_component,prnt_dbg_comp,chg_idx)); + prnt_dbg_comp=GlobalDebugComponents; + RT_TRACE(0xffffffff, _drv_emerg_,("3-1: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h) chg_idx=%d\n",offset,offset,padapter->registrypriv.dbg_component,prnt_dbg_comp,chg_idx));// ("3-1: mp_query_drv_var: offset(%d;0x%x):before set dbg conpoment=0x%x chg_idx=%d or0x%x BIT(chg_idx[%d]=0x%x)\n",offset,offset,prnt_dbg_comp,chg_idx,chg_idx,(chg_idx),tmp_dbg_comp) + prnt_dbg_comp=GlobalDebugComponents=padapter->registrypriv.dbg_component; + RT_TRACE(0xffffffff, _drv_emerg_, ("3-2: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h)\n",offset,offset,padapter->registrypriv.dbg_component,prnt_dbg_comp)); + + if(GlobalDebugComponents&tmp_dbg_comp){ + //this bit is already set, now clear it + GlobalDebugComponents=GlobalDebugComponents&(~tmp_dbg_comp); + } + else{ + //this bit is not set, now set it. + GlobalDebugComponents =GlobalDebugComponents|tmp_dbg_comp; + } + RT_TRACE(0xffffffff, _drv_emerg_, ("4: mp_query_drv_var: offset(%d;0x%x):before set dbg conpoment tmp_dbg_comp=0x%x GlobalDebugComponents=0x%x(l) 0x%x(h)",offset,offset,tmp_dbg_comp,prnt_dbg_comp)); + prnt_dbg_comp=GlobalDebugComponents; + RT_TRACE(0xffffffff, _drv_emerg_, ("4-1: mp_query_drv_var: offset(%d;0x%x):before set dbg conpoment tmp_dbg_comp=0x%x GlobalDebugComponents=0x%x(l) 0x%x(h)",offset,offset,tmp_dbg_comp,prnt_dbg_comp)); + + RT_TRACE(_module_rtl871x_xmit_c_, _drv_emerg_, ("0: mp_query_drv_var(_module_rtl871x_xmit_c_:0): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,prnt_dbg_comp)); + RT_TRACE(_module_xmit_osdep_c_, _drv_emerg_, ("1: mp_query_drv_var(_module_xmit_osdep_c_:1): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); + RT_TRACE(_module_rtl871x_recv_c_, _drv_emerg_, ("2: mp_query_drv_var(_module_rtl871x_recv_c_:2): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); + RT_TRACE(_module_recv_osdep_c_, _drv_emerg_, ("3: mp_query_drv_var(_module_recv_osdep_c_:3): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); + RT_TRACE(_module_rtl871x_mlme_c_, _drv_emerg_, ("4: mp_query_drv_var(_module_rtl871x_mlme_c_:4): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); + RT_TRACE(_module_mlme_osdep_c_, _drv_emerg_, (" 5:mp_query_drv_var(_module_mlme_osdep_c_:5): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); + RT_TRACE(_module_rtl871x_sta_mgt_c_, _drv_emerg_, ("6: mp_query_drv_var(_module_rtl871x_sta_mgt_c_:6): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); + RT_TRACE(_module_rtl871x_cmd_c_, _drv_emerg_, ("7: mp_query_drv_var(_module_rtl871x_cmd_c_:7): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); + RT_TRACE(_module_cmd_osdep_c_, _drv_emerg_, ("8: mp_query_drv_var(_module_cmd_osdep_c_:8): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); + RT_TRACE(_module_rtl871x_io_c_, _drv_emerg_, ("9: mp_query_drv_var(_module_rtl871x_io_c_:9): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); + RT_TRACE(_module_io_osdep_c_, _drv_emerg_, ("10: mp_query_drv_var(_module_io_osdep_c_:10): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); + RT_TRACE(_module_os_intfs_c_, _drv_emerg_, ("11: mp_query_drv_var(_module_os_intfs_c_:11): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); + RT_TRACE(_module_rtl871x_security_c_, _drv_emerg_, ("12: mp_query_drv_var(_module_rtl871x_security_c_:12): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); + RT_TRACE(_module_rtl871x_eeprom_c_, _drv_emerg_, ("13: mp_query_drv_var(_module_rtl871x_eeprom_c_:13): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); + RT_TRACE(_module_hal_init_c_, _drv_emerg_, ("14: mp_query_drv_var(_module_hal_init_c_:14): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); + RT_TRACE(_module_hci_hal_init_c_, _drv_emerg_, ("15: mp_query_drv_var(_module_hci_hal_init_c_:15): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); + RT_TRACE(_module_rtl871x_ioctl_c_, _drv_emerg_, ("16: mp_query_drv_var(_module_rtl871x_ioctl_c_:16): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); + RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_emerg_, ("17: mp_query_drv_var(_module_rtl871x_ioctl_set_c_:17): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); + RT_TRACE(_module_rtl871x_ioctl_query_c_, _drv_emerg_, ("18: mp_query_drv_var(_module_rtl871x_ioctl_query_c_:18): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); + RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_emerg_, ("19: mp_query_drv_var(_module_rtl871x_pwrctrl_c_:19): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); + RT_TRACE(_module_hci_intfs_c_, _drv_emerg_, ("20: mp_query_drv_var(_module_hci_intfs_c_:20): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); + RT_TRACE(_module_hci_ops_c_, _drv_emerg_, ("21: mp_query_drv_var(_module_hci_ops_c_:21): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); + RT_TRACE(_module_osdep_service_c_, _drv_emerg_, ("22: mp_query_drv_var(_module_osdep_service_c_:22): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); + RT_TRACE(_module_mp_, _drv_emerg_, ("23: mp_query_drv_var(_module_mp_:23): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); + RT_TRACE(_module_hci_ops_os_c_, _drv_emerg_, ("24: mp_query_drv_var(_module_hci_ops_os_c_:24): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); + var=(u32)(GlobalDebugComponents); + //GlobalDebugComponents=padapter->registrypriv.dbg_component; + RT_TRACE(0xffffffff, _drv_emerg_, (" ==mp_query_drv_var(_module_mp_): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); + + } + } + else{ + RT_TRACE(_module_mp_, _drv_emerg_, ("\n mp_query_drv_var: offset(%d) >110\n",offset)); + } +#endif +#endif + + return var; +} +#endif + +NDIS_STATUS oid_rt_pro_query_dr_variable_hdl(struct oid_par_priv *poid_par_priv) +{ +#if 0 + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + + DR_VARIABLE_STRUCT *pdrv_var; + + + if (poid_par_priv->type_of_oid != QUERY_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + *poid_par_priv->bytes_needed = sizeof(DR_VARIABLE_STRUCT); + if (poid_par_priv->information_buf_len < *poid_par_priv->bytes_needed) + return NDIS_STATUS_INVALID_LENGTH; + + RT_TRACE(_module_mp_, _drv_notice_, ("+Query Information, OID_RT_PRO_QUERY_DR_VARIABLE\n")); + + pdrv_var = (struct _DR_VARIABLE_STRUCT_ *)poid_par_priv->information_buf; + + _irqlevel_changed_(&oldirql, LOWER); + pdrv_var->variable = mp_query_drv_var(Adapter, pdrv_var->offset, pdrv_var->variable); + _irqlevel_changed_(&oldirql, RAISE); + + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + + RT_TRACE(_module_mp_, _drv_notice_, + ("-oid_rt_pro_query_dr_variable_hdl: offset=0x%x valule=0x%x\n", + pdrv_var->offset, pdrv_var->variable)); + + return status; +#else + return 0; +#endif +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_rx_packet_type_hdl(struct oid_par_priv *poid_par_priv) +{ +#if 0 + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + + RT_TRACE(_module_mp_, _drv_err_, ("oid_rt_pro_rx_packet_type_hdl...................\n")); + + if (poid_par_priv->information_buf_len < sizeof (UCHAR)) { + status = NDIS_STATUS_INVALID_LENGTH; + *poid_par_priv->bytes_needed = sizeof(UCHAR); + return status; + } + + if (poid_par_priv->type_of_oid == SET_OID) { + Adapter->mppriv.rx_with_status = *(UCHAR *) poid_par_priv->information_buf; + RT_TRACE(_module_rtl871x_ioctl_c_,_drv_err_, ("Query Information, OID_RT_PRO_RX_PACKET_TYPE:%d \n",\ + Adapter->mppriv.rx_with_status)); + + RT_TRACE(_module_rtl871x_ioctl_c_,_drv_err_,("MAC addr=0x%x:0x%x:0x%x:0x%x:0x%x:0x%x \n", + Adapter->eeprompriv.mac_addr[0],Adapter->eeprompriv.mac_addr[1],Adapter->eeprompriv.mac_addr[2],\ + Adapter->eeprompriv.mac_addr[3],Adapter->eeprompriv.mac_addr[4],Adapter->eeprompriv.mac_addr[5])); + + } + else { + *(UCHAR *) poid_par_priv->information_buf = Adapter->mppriv.rx_with_status; + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + + RT_TRACE(_module_rtl871x_ioctl_c_,_drv_err_, ("Query Information, OID_RT_PRO_RX_PACKET_TYPE:%d \n", \ + Adapter->mppriv.rx_with_status)); + + //*(u32 *)&Adapter->eeprompriv.mac_addr[0]=rtw_read32(Adapter, 0x10250050); + //*(u16 *)&Adapter->eeprompriv.mac_addr[4]=rtw_read16(Adapter, 0x10250054); + RT_TRACE(_module_rtl871x_ioctl_c_,_drv_err_,("MAC addr=0x%x:0x%x:0x%x:0x%x:0x%x:0x%x \n", + Adapter->eeprompriv.mac_addr[0],Adapter->eeprompriv.mac_addr[1],Adapter->eeprompriv.mac_addr[2],\ + Adapter->eeprompriv.mac_addr[3],Adapter->eeprompriv.mac_addr[4],Adapter->eeprompriv.mac_addr[5])); + } +#endif + + return NDIS_STATUS_SUCCESS; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_read_efuse_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + PEFUSE_ACCESS_STRUCT pefuse; + u8 *data; + u16 addr = 0, cnts = 0, max_available_size = 0; + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + if (poid_par_priv->type_of_oid != QUERY_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + if (poid_par_priv->information_buf_len < sizeof(EFUSE_ACCESS_STRUCT)) + return NDIS_STATUS_INVALID_LENGTH; + + pefuse = (PEFUSE_ACCESS_STRUCT)poid_par_priv->information_buf; + addr = pefuse->start_addr; + cnts = pefuse->cnts; + data = pefuse->data; + + RT_TRACE(_module_mp_, _drv_notice_, + ("+oid_rt_pro_read_efuse_hd: buf_len=%d addr=%d cnts=%d\n", + poid_par_priv->information_buf_len, addr, cnts)); + + EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE); + + if ((addr + cnts) > max_available_size) { + RT_TRACE(_module_mp_, _drv_err_, ("!oid_rt_pro_read_efuse_hdl: parameter error!\n")); + return NDIS_STATUS_NOT_ACCEPTED; + } + + _irqlevel_changed_(&oldirql, LOWER); + if (rtw_efuse_access(Adapter, _FALSE, addr, cnts, data) == _FAIL) { + RT_TRACE(_module_mp_, _drv_err_, ("!oid_rt_pro_read_efuse_hdl: rtw_efuse_access FAIL!\n")); + status = NDIS_STATUS_FAILURE; + } else + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + _irqlevel_changed_(&oldirql, RAISE); + +_func_exit_; + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_write_efuse_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + PEFUSE_ACCESS_STRUCT pefuse; + u8 *data; + u16 addr = 0, cnts = 0, max_available_size = 0; + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + + +_func_enter_; + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + pefuse = (PEFUSE_ACCESS_STRUCT)poid_par_priv->information_buf; + addr = pefuse->start_addr; + cnts = pefuse->cnts; + data = pefuse->data; + + RT_TRACE(_module_mp_, _drv_notice_, + ("+oid_rt_pro_write_efuse_hdl: buf_len=%d addr=0x%04x cnts=%d\n", + poid_par_priv->information_buf_len, addr, cnts)); + + EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE); + + if ((addr + cnts) > max_available_size) { + RT_TRACE(_module_mp_, _drv_err_, ("!oid_rt_pro_write_efuse_hdl: parameter error")); + return NDIS_STATUS_NOT_ACCEPTED; + } + + _irqlevel_changed_(&oldirql, LOWER); + if (rtw_efuse_access(Adapter, _TRUE, addr, cnts, data) == _FAIL) + status = NDIS_STATUS_FAILURE; + _irqlevel_changed_(&oldirql, RAISE); + +_func_exit_; + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_rw_efuse_pgpkt_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + PPGPKT_STRUCT ppgpkt; + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + +// RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_pro_rw_efuse_pgpkt_hdl\n")); + + *poid_par_priv->bytes_rw = 0; + + if (poid_par_priv->information_buf_len < sizeof(PGPKT_STRUCT)) + return NDIS_STATUS_INVALID_LENGTH; + + ppgpkt = (PPGPKT_STRUCT)poid_par_priv->information_buf; + + _irqlevel_changed_(&oldirql, LOWER); + + if (poid_par_priv->type_of_oid == QUERY_OID) + { + RT_TRACE(_module_mp_, _drv_notice_, + ("oid_rt_pro_rw_efuse_pgpkt_hdl: Read offset=0x%x\n",\ + ppgpkt->offset)); + + Efuse_PowerSwitch(Adapter, _FALSE, _TRUE); + if (Efuse_PgPacketRead(Adapter, ppgpkt->offset, ppgpkt->data, _FALSE) == _TRUE) + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + else + status = NDIS_STATUS_FAILURE; + Efuse_PowerSwitch(Adapter, _FALSE, _FALSE); + } else { + RT_TRACE(_module_mp_, _drv_notice_, + ("oid_rt_pro_rw_efuse_pgpkt_hdl: Write offset=0x%x word_en=0x%x\n",\ + ppgpkt->offset, ppgpkt->word_en)); + + Efuse_PowerSwitch(Adapter, _TRUE, _TRUE); + if (Efuse_PgPacketWrite(Adapter, ppgpkt->offset, ppgpkt->word_en, ppgpkt->data, _FALSE) == _TRUE) + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + else + status = NDIS_STATUS_FAILURE; + Efuse_PowerSwitch(Adapter, _TRUE, _FALSE); + } + + _irqlevel_changed_(&oldirql, RAISE); + + RT_TRACE(_module_mp_, _drv_info_, + ("-oid_rt_pro_rw_efuse_pgpkt_hdl: status=0x%08X\n", status)); + +_func_exit_; + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_get_efuse_current_size_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + u16 size; + u8 ret; + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + if (poid_par_priv->type_of_oid != QUERY_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + if (poid_par_priv->information_buf_len information_buf = size; + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + } else + status = NDIS_STATUS_FAILURE; + +_func_exit_; + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_get_efuse_max_size_hdl(struct oid_par_priv *poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + if (poid_par_priv->type_of_oid != QUERY_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + if (poid_par_priv->information_buf_len < sizeof(u32)) + return NDIS_STATUS_INVALID_LENGTH; + + *(u32*)poid_par_priv->information_buf = efuse_GetMaxSize(Adapter); + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; + + RT_TRACE(_module_mp_, _drv_info_, + ("-oid_rt_get_efuse_max_size_hdl: size=%d status=0x%08X\n", + *(int*)poid_par_priv->information_buf, status)); + +_func_exit_; + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_efuse_hdl(struct oid_par_priv *poid_par_priv) +{ + NDIS_STATUS status; + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_pro_efuse_hdl\n")); + + if (poid_par_priv->type_of_oid == QUERY_OID) + status = oid_rt_pro_read_efuse_hdl(poid_par_priv); + else + status = oid_rt_pro_write_efuse_hdl(poid_par_priv); + + RT_TRACE(_module_mp_, _drv_info_, ("-oid_rt_pro_efuse_hdl: status=0x%08X\n", status)); + +_func_exit_; + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_pro_efuse_map_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + u8 *data; + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + u16 mapLen=0; + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_efuse_map_hdl\n")); + + EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE); + + *poid_par_priv->bytes_rw = 0; + + if (poid_par_priv->information_buf_len < mapLen) + return NDIS_STATUS_INVALID_LENGTH; + + data = (u8*)poid_par_priv->information_buf; + + _irqlevel_changed_(&oldirql, LOWER); + + if (poid_par_priv->type_of_oid == QUERY_OID) + { + RT_TRACE(_module_mp_, _drv_info_, + ("oid_rt_pro_efuse_map_hdl: READ\n")); + + if (rtw_efuse_map_read(Adapter, 0, mapLen, data) == _SUCCESS) + *poid_par_priv->bytes_rw = mapLen; + else { + RT_TRACE(_module_mp_, _drv_err_, + ("oid_rt_pro_efuse_map_hdl: READ fail\n")); + status = NDIS_STATUS_FAILURE; + } + } else { + // SET_OID + RT_TRACE(_module_mp_, _drv_info_, + ("oid_rt_pro_efuse_map_hdl: WRITE\n")); + + if (rtw_efuse_map_write(Adapter, 0, mapLen, data) == _SUCCESS) + *poid_par_priv->bytes_rw = mapLen; + else { + RT_TRACE(_module_mp_, _drv_err_, + ("oid_rt_pro_efuse_map_hdl: WRITE fail\n")); + status = NDIS_STATUS_FAILURE; + } + } + + _irqlevel_changed_(&oldirql, RAISE); + + RT_TRACE(_module_mp_, _drv_info_, + ("-oid_rt_pro_efuse_map_hdl: status=0x%08X\n", status)); + +_func_exit_; + + return status; +} + +NDIS_STATUS oid_rt_set_crystal_cap_hdl(struct oid_par_priv *poid_par_priv) +{ + NDIS_STATUS status = NDIS_STATUS_SUCCESS; +#if 0 + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + + u32 crystal_cap = 0; + +_func_enter_; + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + if (poid_par_priv->information_buf_len information_buf);//4 + if (crystal_cap > 0xf) + return NDIS_STATUS_NOT_ACCEPTED; + + Adapter->mppriv.curr_crystalcap = crystal_cap; + + _irqlevel_changed_(&oldirql,LOWER); + SetCrystalCap(Adapter); + _irqlevel_changed_(&oldirql,RAISE); + +_func_exit_; + +#endif + return status; +} + +NDIS_STATUS oid_rt_set_rx_packet_type_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + u8 rx_pkt_type; +// u32 rcr_val32; + NDIS_STATUS status = NDIS_STATUS_SUCCESS; +// PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); + +_func_enter_; + + RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_set_rx_packet_type_hdl\n")); + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + if (poid_par_priv->information_buf_len < sizeof(u8)) + return NDIS_STATUS_INVALID_LENGTH; + + rx_pkt_type = *((u8*)poid_par_priv->information_buf);//4 + + RT_TRACE(_module_mp_, _drv_info_, ("rx_pkt_type: %x\n",rx_pkt_type )); +#if 0 + _irqlevel_changed_(&oldirql, LOWER); +#if 0 + rcr_val8 = rtw_read8(Adapter, 0x10250048);//RCR + rcr_val8 &= ~(RCR_AB|RCR_AM|RCR_APM|RCR_AAP); + + if(rx_pkt_type == RX_PKT_BROADCAST){ + rcr_val8 |= (RCR_AB | RCR_ACRC32 ); + } + else if(rx_pkt_type == RX_PKT_DEST_ADDR){ + rcr_val8 |= (RCR_AAP| RCR_AM |RCR_ACRC32); + } + else if(rx_pkt_type == RX_PKT_PHY_MATCH){ + rcr_val8 |= (RCR_APM|RCR_ACRC32); + } + else{ + rcr_val8 &= ~(RCR_AAP|RCR_APM|RCR_AM|RCR_AB|RCR_ACRC32); + } + rtw_write8(padapter, 0x10250048,rcr_val8); +#else + rcr_val32 = rtw_read32(padapter, RCR);//RCR = 0x10250048 + rcr_val32 &= ~(RCR_CBSSID|RCR_AB|RCR_AM|RCR_APM|RCR_AAP); +#if 0 + if(rx_pkt_type == RX_PKT_BROADCAST){ + rcr_val32 |= (RCR_AB|RCR_AM|RCR_APM|RCR_AAP|RCR_ACRC32); + } + else if(rx_pkt_type == RX_PKT_DEST_ADDR){ + //rcr_val32 |= (RCR_CBSSID|RCR_AAP|RCR_AM|RCR_ACRC32); + rcr_val32 |= (RCR_CBSSID|RCR_APM|RCR_ACRC32); + } + else if(rx_pkt_type == RX_PKT_PHY_MATCH){ + rcr_val32 |= (RCR_APM|RCR_ACRC32); + //rcr_val32 |= (RCR_AAP|RCR_ACRC32); + } + else{ + rcr_val32 &= ~(RCR_AAP|RCR_APM|RCR_AM|RCR_AB|RCR_ACRC32); + } +#else + switch (rx_pkt_type) + { + case RX_PKT_BROADCAST : + rcr_val32 |= (RCR_AB|RCR_AM|RCR_APM|RCR_AAP|RCR_ACRC32); + break; + case RX_PKT_DEST_ADDR : + rcr_val32 |= (RCR_AB|RCR_AM|RCR_APM|RCR_AAP|RCR_ACRC32); + break; + case RX_PKT_PHY_MATCH: + rcr_val32 |= (RCR_APM|RCR_ACRC32); + break; + default: + rcr_val32 &= ~(RCR_AAP|RCR_APM|RCR_AM|RCR_AB|RCR_ACRC32); + break; + } + + if (rx_pkt_type == RX_PKT_DEST_ADDR) { + padapter->mppriv.check_mp_pkt = 1; + } else { + padapter->mppriv.check_mp_pkt = 0; + } +#endif + rtw_write32(padapter, RCR, rcr_val32); + +#endif + _irqlevel_changed_(&oldirql, RAISE); +#endif +_func_exit_; + + return status; +} + +NDIS_STATUS oid_rt_pro_set_tx_agc_offset_hdl(struct oid_par_priv *poid_par_priv) +{ +#if 0 + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + + u32 txagc; + +_func_enter_; + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + if (poid_par_priv->information_buf_len < sizeof(u32)) + return NDIS_STATUS_INVALID_LENGTH; + + txagc = *(u32*)poid_par_priv->information_buf; + RT_TRACE(_module_mp_, _drv_info_, + ("oid_rt_pro_set_tx_agc_offset_hdl: 0x%08x\n", txagc)); + + _irqlevel_changed_(&oldirql, LOWER); + SetTxAGCOffset(Adapter, txagc); + _irqlevel_changed_(&oldirql, RAISE); + +_func_exit_; + + return status; +#else + return 0; +#endif +} + +NDIS_STATUS oid_rt_pro_set_pkt_test_mode_hdl(struct oid_par_priv *poid_par_priv) +{ +#if 0 + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); + + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + + struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; + struct mp_priv *pmppriv = &Adapter->mppriv; + u32 type; + +_func_enter_; + + if (poid_par_priv->type_of_oid != SET_OID) + return NDIS_STATUS_NOT_ACCEPTED; + + if (poid_par_priv->information_buf_len information_buf; + + if (_LOOPBOOK_MODE_ == type) { + pmppriv->mode = type; + set_fwstate(pmlmepriv, WIFI_MP_LPBK_STATE); //append txdesc + RT_TRACE(_module_mp_, _drv_info_, ("test mode change to loopback mode:0x%08x.\n", get_fwstate(pmlmepriv))); + } else if (_2MAC_MODE_ == type){ + pmppriv->mode = type; + _clr_fwstate_(pmlmepriv, WIFI_MP_LPBK_STATE); + RT_TRACE(_module_mp_, _drv_info_, ("test mode change to 2mac mode:0x%08x.\n", get_fwstate(pmlmepriv))); + } else + status = NDIS_STATUS_NOT_ACCEPTED; + +_func_exit_; + + return status; +#else + return 0; +#endif +} + +unsigned int mp_ioctl_xmit_packet_hdl(struct oid_par_priv *poid_par_priv) +{ + PMP_XMIT_PARM pparm; + PADAPTER padapter; + struct mp_priv *pmp_priv; + struct pkt_attrib *pattrib; + + RT_TRACE(_module_mp_, _drv_notice_, ("+%s\n", __func__)); + + pparm = (PMP_XMIT_PARM)poid_par_priv->information_buf; + padapter = (PADAPTER)poid_par_priv->adapter_context; + pmp_priv = &padapter->mppriv; + + if (poid_par_priv->type_of_oid == QUERY_OID) { + pparm->enable = !pmp_priv->tx.stop; + pparm->count = pmp_priv->tx.sended; + } else { + if (pparm->enable == 0) { + pmp_priv->tx.stop = 1; + } else if (pmp_priv->tx.stop == 1) { + pmp_priv->tx.stop = 0; + pmp_priv->tx.count = pparm->count; + pmp_priv->tx.payload = pparm->payload_type; + pattrib = &pmp_priv->tx.attrib; + pattrib->pktlen = pparm->length; + _rtw_memcpy(pattrib->dst, pparm->da, ETH_ALEN); + SetPacketTx(padapter); + } else + return NDIS_STATUS_FAILURE; + } + + return NDIS_STATUS_SUCCESS; +} + +#if 0 +unsigned int mp_ioctl_xmit_packet_hdl(struct oid_par_priv *poid_par_priv) +{ + unsigned char *pframe, *pmp_pkt; + struct ethhdr *pethhdr; + struct pkt_attrib *pattrib; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + int llc_sz, payload_len; + struct mp_xmit_frame *pxframe= NULL; + struct mp_xmit_packet *pmp_xmitpkt = (struct mp_xmit_packet*)param; + u8 addr3[] = {0x02, 0xE0, 0x4C, 0x87, 0x66, 0x55}; + +// DBG_871X("+mp_ioctl_xmit_packet_hdl\n"); + + pxframe = alloc_mp_xmitframe(&padapter->mppriv); + if (pxframe == NULL) + { + DEBUG_ERR(("Can't alloc pmpframe %d:%s\n", __LINE__, __FILE__)); + return -1; + } + + //mp_xmit_pkt + payload_len = pmp_xmitpkt->len - 14; + pmp_pkt = (unsigned char*)pmp_xmitpkt->mem; + pethhdr = (struct ethhdr *)pmp_pkt; + + //DBG_871X("payload_len=%d, pkt_mem=0x%x\n", pmp_xmitpkt->len, (void*)pmp_xmitpkt->mem); + + //DBG_871X("pxframe=0x%x\n", (void*)pxframe); + //DBG_871X("pxframe->mem=0x%x\n", (void*)pxframe->mem); + + //update attribute + pattrib = &pxframe->attrib; + memset((u8 *)(pattrib), 0, sizeof (struct pkt_attrib)); + pattrib->pktlen = pmp_xmitpkt->len; + pattrib->ether_type = ntohs(pethhdr->h_proto); + pattrib->hdrlen = 24; + pattrib->nr_frags = 1; + pattrib->priority = 0; +#ifndef CONFIG_MP_LINUX + if(IS_MCAST(pethhdr->h_dest)) + pattrib->mac_id = 4; + else + pattrib->mac_id = 5; +#else + pattrib->mac_id = 5; +#endif + + // + memset(pxframe->mem, 0 , WLANHDR_OFFSET); + pframe = (u8 *)(pxframe->mem) + WLANHDR_OFFSET; + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + SetFrameSubType(pframe, WIFI_DATA); + + _rtw_memcpy(pwlanhdr->addr1, pethhdr->h_dest, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pethhdr->h_source, ETH_ALEN); + + _rtw_memcpy(pwlanhdr->addr3, addr3, ETH_ALEN); + + pwlanhdr->seq_ctl = 0; + pframe += pattrib->hdrlen; + + llc_sz= rtw_put_snap(pframe, pattrib->ether_type); + pframe += llc_sz; + + _rtw_memcpy(pframe, (void*)(pmp_pkt+14), payload_len); + + pattrib->last_txcmdsz = pattrib->hdrlen + llc_sz + payload_len; + + DEBUG_INFO(("issuing mp_xmit_frame, tx_len=%d, ether_type=0x%x\n", pattrib->last_txcmdsz, pattrib->ether_type)); + xmit_mp_frame(padapter, pxframe); + + return _SUCCESS; +} +#endif +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_set_power_down_hdl(struct oid_par_priv *poid_par_priv) +{ +#ifdef PLATFORM_OS_XP + _irqL oldirql; +#endif + u8 bpwrup; + NDIS_STATUS status = NDIS_STATUS_SUCCESS; +#ifdef PLATFORM_LINUX +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); +#endif +#endif + +_func_enter_; + + if (poid_par_priv->type_of_oid != SET_OID) { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + + RT_TRACE(_module_mp_, _drv_info_, + ("\n ===> Setoid_rt_set_power_down_hdl.\n")); + + _irqlevel_changed_(&oldirql, LOWER); + + bpwrup = *(u8 *)poid_par_priv->information_buf; + //CALL the power_down function +#ifdef PLATFORM_LINUX +#if defined(CONFIG_RTL8712) //Linux MP insmod unknown symbol + dev_power_down(padapter,bpwrup); +#endif +#endif + _irqlevel_changed_(&oldirql, RAISE); + + //DEBUG_ERR(("\n <=== Query OID_RT_PRO_READ_REGISTER. + // Add:0x%08x Width:%d Value:0x%08x\n",RegRWStruct->offset,RegRWStruct->width,RegRWStruct->value)); + +_func_exit_; + + return status; +} +//------------------------------------------------------------------------------ +NDIS_STATUS oid_rt_get_power_mode_hdl(struct oid_par_priv *poid_par_priv) +{ +#if 0 + NDIS_STATUS status = NDIS_STATUS_SUCCESS; + PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); +//#ifdef PLATFORM_OS_XP +// _irqL oldirql; +//#endif + +_func_enter_; + + if (poid_par_priv->type_of_oid != QUERY_OID) { + status = NDIS_STATUS_NOT_ACCEPTED; + return status; + } + if (poid_par_priv->information_buf_len < sizeof(u32)) { + status = NDIS_STATUS_INVALID_LENGTH; + return status; + } + + RT_TRACE(_module_mp_, _drv_info_, + ("\n ===> oid_rt_get_power_mode_hdl.\n")); + +// _irqlevel_changed_(&oldirql, LOWER); + *(int*)poid_par_priv->information_buf = Adapter->registrypriv.low_power ? POWER_LOW : POWER_NORMAL; + *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; +// _irqlevel_changed_(&oldirql, RAISE); + +_func_exit_; + + return status; +#else + return 0; +#endif +} + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_odm.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_odm.c new file mode 100644 index 000000000..7b733a9a5 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_odm.c @@ -0,0 +1,461 @@ +/****************************************************************************** + * + * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include +#include + +const char *odm_comp_str[] = { + /* BIT0 */"ODM_COMP_DIG", + /* BIT1 */"ODM_COMP_RA_MASK", + /* BIT2 */"ODM_COMP_DYNAMIC_TXPWR", + /* BIT3 */"ODM_COMP_FA_CNT", + /* BIT4 */"ODM_COMP_RSSI_MONITOR", + /* BIT5 */"ODM_COMP_CCK_PD", + /* BIT6 */"ODM_COMP_ANT_DIV", + /* BIT7 */"ODM_COMP_PWR_SAVE", + /* BIT8 */"ODM_COMP_PWR_TRAIN", + /* BIT9 */"ODM_COMP_RATE_ADAPTIVE", + /* BIT10 */"ODM_COMP_PATH_DIV", + /* BIT11 */"ODM_COMP_PSD", + /* BIT12 */"ODM_COMP_DYNAMIC_PRICCA", + /* BIT13 */"ODM_COMP_RXHP", + /* BIT14 */"ODM_COMP_MP", + /* BIT15 */"ODM_COMP_CFO_TRACKING", + /* BIT16 */"ODM_COMP_ACS", + /* BIT17 */"PHYDM_COMP_ADAPTIVITY", + /* BIT18 */"PHYDM_COMP_RA_DBG", + /* BIT19 */"PHYDM_COMP_TXBF", + /* BIT20 */"ODM_COMP_EDCA_TURBO", + /* BIT21 */"ODM_COMP_EARLY_MODE", + /* BIT22 */"ODM_FW_DEBUG_TRACE", + /* BIT23 */NULL, + /* BIT24 */"ODM_COMP_TX_PWR_TRACK", + /* BIT25 */"ODM_COMP_RX_GAIN_TRACK", + /* BIT26 */"ODM_COMP_CALIBRATION", + /* BIT27 */NULL, + /* BIT28 */"ODM_PHY_CONFIG", + /* BIT29 */"BEAMFORMING_DEBUG", + /* BIT30 */"ODM_COMP_COMMON", + /* BIT31 */"ODM_COMP_INIT", + /* BIT32 */"ODM_COMP_NOISY_DETECT", +}; + +#define RTW_ODM_COMP_MAX 33 + +const char *odm_ability_str[] = { + /* BIT0 */"ODM_BB_DIG", + /* BIT1 */"ODM_BB_RA_MASK", + /* BIT2 */"ODM_BB_DYNAMIC_TXPWR", + /* BIT3 */"ODM_BB_FA_CNT", + /* BIT4 */"ODM_BB_RSSI_MONITOR", + /* BIT5 */"ODM_BB_CCK_PD", + /* BIT6 */"ODM_BB_ANT_DIV", + /* BIT7 */"ODM_BB_PWR_SAVE", + /* BIT8 */"ODM_BB_PWR_TRAIN", + /* BIT9 */"ODM_BB_RATE_ADAPTIVE", + /* BIT10 */"ODM_BB_PATH_DIV", + /* BIT11 */"ODM_BB_PSD", + /* BIT12 */"ODM_BB_RXHP", + /* BIT13 */"ODM_BB_ADAPTIVITY", + /* BIT14 */"ODM_BB_CFO_TRACKING", + /* BIT15 */"ODM_BB_NHM_CNT", + /* BIT16 */"ODM_BB_PRIMARY_CCA", + /* BIT17 */"ODM_BB_TXBF", + /* BIT18 */NULL, + /* BIT19 */NULL, + /* BIT20 */"ODM_MAC_EDCA_TURBO", + /* BIT21 */"ODM_MAC_EARLY_MODE", + /* BIT22 */NULL, + /* BIT23 */NULL, + /* BIT24 */"ODM_RF_TX_PWR_TRACK", + /* BIT25 */"ODM_RF_RX_GAIN_TRACK", + /* BIT26 */"ODM_RF_CALIBRATION", +}; + +#define RTW_ODM_ABILITY_MAX 27 + +const char *odm_dbg_level_str[] = { + NULL, + "ODM_DBG_OFF", + "ODM_DBG_SERIOUS", + "ODM_DBG_WARNING", + "ODM_DBG_LOUD", + "ODM_DBG_TRACE", +}; + +#define RTW_ODM_DBG_LEVEL_NUM 6 + +void rtw_odm_dbg_comp_msg(void *sel, _adapter *adapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); + DM_ODM_T *odm = &pHalData->odmpriv; + int cnt = 0; + u64 dbg_comp = 0; + int i; + + rtw_hal_get_odm_var(adapter, HAL_ODM_DBG_FLAG, &dbg_comp, NULL); + + DBG_871X_SEL_NL(sel, "odm.DebugComponents = 0x%016llx\n", dbg_comp); + for (i=0;iodmpriv; + int cnt = 0; + u32 dbg_level = 0; + int i; + + rtw_hal_get_odm_var(adapter, HAL_ODM_DBG_LEVEL, &dbg_level, NULL); + DBG_871X_SEL_NL(sel, "odm.DebugLevel = %u\n", dbg_level); + for (i=0;iodmpriv; + int cnt = 0; + u32 ability = 0; + int i; + + ability = rtw_phydm_ability_get(adapter); + DBG_871X_SEL_NL(sel, "odm.SupportAbility = 0x%08x\n", ability); + for (i=0;iodmpriv; + u4Byte ic_type = chip_type_to_odm_ic_type(rtw_get_chip_type(adapter)); + + rtw_warn_on(!ic_type); + + ODM_CmnInfoInit(odm, ODM_CMNINFO_IC_TYPE, ic_type); +} + +void rtw_odm_adaptivity_ver_msg(void *sel, _adapter *adapter) +{ + DBG_871X_SEL_NL(sel, "ADAPTIVITY_VERSION "ADAPTIVITY_VERSION"\n"); +} + +#define RTW_ADAPTIVITY_EN_DISABLE 0 +#define RTW_ADAPTIVITY_EN_ENABLE 1 + +void rtw_odm_adaptivity_en_msg(void *sel, _adapter *adapter) +{ + struct registry_priv *regsty = &adapter->registrypriv; + struct mlme_priv *mlme = &adapter->mlmepriv; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + DM_ODM_T *odm = &hal_data->odmpriv; + + DBG_871X_SEL_NL(sel, "RTW_ADAPTIVITY_EN_"); + + if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_DISABLE) { + DBG_871X_SEL(sel, "DISABLE\n"); + } else if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE) { + DBG_871X_SEL(sel, "ENABLE\n"); + } else { + DBG_871X_SEL(sel, "INVALID\n"); + } +} + +#define RTW_ADAPTIVITY_MODE_NORMAL 0 +#define RTW_ADAPTIVITY_MODE_CARRIER_SENSE 1 + +void rtw_odm_adaptivity_mode_msg(void *sel, _adapter *adapter) +{ + struct registry_priv *regsty = &adapter->registrypriv; + + DBG_871X_SEL_NL(sel, "RTW_ADAPTIVITY_MODE_"); + + if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_NORMAL) { + DBG_871X_SEL(sel, "NORMAL\n"); + } else if (regsty->adaptivity_mode == RTW_ADAPTIVITY_MODE_CARRIER_SENSE) { + DBG_871X_SEL(sel, "CARRIER_SENSE\n"); + } else { + DBG_871X_SEL(sel, "INVALID\n"); + } +} + +#define RTW_ADAPTIVITY_DML_DISABLE 0 +#define RTW_ADAPTIVITY_DML_ENABLE 1 + +void rtw_odm_adaptivity_dml_msg(void *sel, _adapter *adapter) +{ + struct registry_priv *regsty = &adapter->registrypriv; + + DBG_871X_SEL_NL(sel, "RTW_ADAPTIVITY_DML_"); + + if (regsty->adaptivity_dml == RTW_ADAPTIVITY_DML_DISABLE) { + DBG_871X_SEL(sel, "DISABLE\n"); + } else if (regsty->adaptivity_dml == RTW_ADAPTIVITY_DML_ENABLE) { + DBG_871X_SEL(sel, "ENABLE\n"); + } else { + DBG_871X_SEL(sel, "INVALID\n"); + } +} + +void rtw_odm_adaptivity_dc_backoff_msg(void *sel, _adapter *adapter) +{ + struct registry_priv *regsty = &adapter->registrypriv; + + DBG_871X_SEL_NL(sel, "RTW_ADAPTIVITY_DC_BACKOFF:%u\n", regsty->adaptivity_dc_backoff); +} + +void rtw_odm_adaptivity_config_msg(void *sel, _adapter *adapter) +{ + rtw_odm_adaptivity_ver_msg(sel, adapter); + rtw_odm_adaptivity_en_msg(sel, adapter); + rtw_odm_adaptivity_mode_msg(sel, adapter); + rtw_odm_adaptivity_dml_msg(sel, adapter); + rtw_odm_adaptivity_dc_backoff_msg(sel, adapter); +} + +bool rtw_odm_adaptivity_needed(_adapter *adapter) +{ + struct registry_priv *regsty = &adapter->registrypriv; + struct mlme_priv *mlme = &adapter->mlmepriv; + bool ret = _FALSE; + + if (regsty->adaptivity_en == RTW_ADAPTIVITY_EN_ENABLE) + ret = _TRUE; + + return ret; +} + +void rtw_odm_adaptivity_parm_msg(void *sel, _adapter *adapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); + DM_ODM_T *odm = &pHalData->odmpriv; + + rtw_odm_adaptivity_config_msg(sel, adapter); + + DBG_871X_SEL_NL(sel, "%10s %16s %16s %22s %12s\n" + , "TH_L2H_ini", "TH_EDCCA_HL_diff", "TH_L2H_ini_mode2", "TH_EDCCA_HL_diff_mode2", "EDCCA_enable"); + DBG_871X_SEL_NL(sel, "0x%-8x %-16d 0x%-14x %-22d %-12d\n" + , (u8)odm->TH_L2H_ini + , odm->TH_EDCCA_HL_diff + , (u8)odm->TH_L2H_ini_mode2 + , odm->TH_EDCCA_HL_diff_mode2 + , odm->EDCCA_enable + ); + + DBG_871X_SEL_NL(sel, "%15s %9s\n", "AdapEnableState", "Adap_Flag"); + DBG_871X_SEL_NL(sel, "%-15x %-9x\n" + , odm->Adaptivity_enable + , odm->adaptivity_flag + ); +} + +void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff, s8 TH_L2H_ini_mode2, s8 TH_EDCCA_HL_diff_mode2, u8 EDCCA_enable) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); + DM_ODM_T *odm = &pHalData->odmpriv; + + odm->TH_L2H_ini = TH_L2H_ini; + odm->TH_EDCCA_HL_diff = TH_EDCCA_HL_diff; + odm->TH_L2H_ini_mode2 = TH_L2H_ini_mode2; + odm->TH_EDCCA_HL_diff_mode2 = TH_EDCCA_HL_diff_mode2; + odm->EDCCA_enable = EDCCA_enable; +} + +void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + DM_ODM_T *odm = &(hal_data->odmpriv); + + DBG_871X_SEL_NL(sel,"RxRate = %s, RSSI_A = %d(%%), RSSI_B = %d(%%)\n", + HDATA_RATE(odm->RxRate), odm->RSSI_A, odm->RSSI_B); +} + + +void rtw_odm_acquirespinlock(_adapter *adapter, RT_SPINLOCK_TYPE type) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); + _irqL irqL; + + switch(type) + { + case RT_IQK_SPINLOCK: + _enter_critical_bh(&pHalData->IQKSpinLock, &irqL); + default: + break; + } +} + +void rtw_odm_releasespinlock(_adapter *adapter, RT_SPINLOCK_TYPE type) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); + _irqL irqL; + + switch(type) + { + case RT_IQK_SPINLOCK: + _exit_critical_bh(&pHalData->IQKSpinLock, &irqL); + default: + break; + } +} + +#ifdef CONFIG_DFS_MASTER +VOID rtw_odm_radar_detect_reset(_adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + PDM_ODM_T pDM_Odm = &(hal_data->odmpriv); + + if (pDM_Odm->SupportICType & ODM_RTL8192D) { + ODM_SetBBReg(pDM_Odm, 0xc84 , BIT25, 0); + ODM_SetBBReg(pDM_Odm, 0xc84 , BIT25, 1); + } else if (pDM_Odm->SupportICType & ODM_RTL8821) { + ODM_SetBBReg(pDM_Odm, 0x924 , BIT15, 0); + ODM_SetBBReg(pDM_Odm, 0x924 , BIT15, 1); + } else { + /* not supported yet */ + rtw_warn_on(1); + } +} + +VOID rtw_odm_radar_detect_disable(_adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + PDM_ODM_T pDM_Odm = &(hal_data->odmpriv); + + if (pDM_Odm->SupportICType & ODM_RTL8192D) + ODM_SetBBReg(pDM_Odm, 0xc84 , BIT25, 0); + else if (pDM_Odm->SupportICType & ODM_RTL8821) + ODM_SetBBReg(pDM_Odm, 0x924 , BIT15, 0); + else + rtw_warn_on(1); +} + +/* called after ch, bw is set, chance to adjust parameter for different ch conditions */ +VOID rtw_odm_radar_detect_enable(_adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + PDM_ODM_T pDM_Odm = &(hal_data->odmpriv); + + if (pDM_Odm->SupportICType & ODM_RTL8192D) { + ODM_SetBBReg(pDM_Odm, 0xc38, BIT23 | BIT22, 2); + ODM_SetBBReg(pDM_Odm, 0x814, bMaskDWord, 0x04cc4d10); + ODM_SetBBReg(pDM_Odm, 0xc8c, BIT23 | BIT22, 3); + ODM_SetBBReg(pDM_Odm, 0xc30, 0xf, 0xa); + ODM_SetBBReg(pDM_Odm, 0xcdc, 0xf0000, 4); + } else if (pDM_Odm->SupportICType & ODM_RTL8821) { + ODM_SetBBReg(pDM_Odm, 0x814, 0x3fffffff, 0x04cc4d10); + ODM_SetBBReg(pDM_Odm, 0x834, bMaskByte0, 0x06); + ODM_SetBBReg(pDM_Odm, 0x918, bMaskDWord, 0x1c16ecdf); + ODM_SetBBReg(pDM_Odm, 0x924, bMaskDWord, 0x0152a400); + ODM_SetBBReg(pDM_Odm, 0x91c, bMaskDWord, 0x0fa21a20); + ODM_SetBBReg(pDM_Odm, 0x920, bMaskDWord, 0xe0f57204); + } else { + /* not supported yet */ + rtw_warn_on(1); + } + + rtw_odm_radar_detect_reset(adapter); +} + +BOOLEAN rtw_odm_radar_detect(_adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + PDM_ODM_T pDM_Odm = &(hal_data->odmpriv); + BOOLEAN enable_DFS = FALSE; + BOOLEAN bypass = FALSE; + BOOLEAN radar_detected = FALSE; + + static u8Byte last_tx_unicast = 0; + static u8Byte last_rx_unicast = 0; + static u8Byte throughput = 0; + int tp_th = ((*pDM_Odm->pBandWidth == ODM_BW40M) ? 45 : 20); /*refer AP team's testing number*/ + + throughput = (*(pDM_Odm->pNumTxBytesUnicast) - last_tx_unicast) + (*(pDM_Odm->pNumRxBytesUnicast) - last_rx_unicast); + last_tx_unicast = *(pDM_Odm->pNumTxBytesUnicast); + last_rx_unicast = *(pDM_Odm->pNumRxBytesUnicast); + + if (throughput>>18 > tp_th) { + if (pDM_Odm->SupportICType & ODM_RTL8192D) + ODM_SetBBReg(pDM_Odm, 0xcdc, BIT8|BIT9, 0); + bypass = TRUE; + } else { + if (pDM_Odm->SupportICType & ODM_RTL8192D) + ODM_SetBBReg(pDM_Odm, 0xcdc, BIT8|BIT9, 1); + } + + if (pDM_Odm->SupportICType & ODM_RTL8192D) { + if (ODM_GetBBReg(pDM_Odm , 0xc84, BIT25)) + enable_DFS = TRUE; + } else if (pDM_Odm->SupportICType & ODM_RTL8821) { + if (ODM_GetBBReg(pDM_Odm , 0x924, BIT15)) + enable_DFS = TRUE; + } + + if (pDM_Odm->SupportICType & ODM_RTL8192D) { + if (ODM_GetBBReg(pDM_Odm , 0xcf8, BIT23)) + radar_detected = TRUE; + } else if (pDM_Odm->SupportICType & ODM_RTL8821) { + if (ODM_GetBBReg(pDM_Odm , 0xf98, BIT17)) + radar_detected = TRUE; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD + , ("Radar detect: enable_DFS:%d, radar_detected:%d, bypass:%d\n" + , enable_DFS, radar_detected, bypass)); + if (0) + DBG_871X("Radar detect: enable_DFS:%d, radar_detected:%d, bypass:%d(throughput:%llu, tp_th:%d)\n" + , enable_DFS, radar_detected, bypass, throughput, tp_th); + + if (enable_DFS && radar_detected) + rtw_odm_radar_detect_reset(adapter); + +exit: + return (enable_DFS && radar_detected && !bypass); +} +#endif /* CONFIG_DFS_MASTER */ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_p2p.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_p2p.c new file mode 100644 index 000000000..101487d87 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_p2p.c @@ -0,0 +1,5636 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_P2P_C_ + +#include + +#ifdef CONFIG_P2P + +int rtw_p2p_is_channel_list_ok( u8 desired_ch, u8* ch_list, u8 ch_cnt ) +{ + int found = 0, i = 0; + + for( i = 0; i < ch_cnt; i++ ) + { + if ( ch_list[ i ] == desired_ch ) + { + found = 1; + break; + } + } + return( found ); +} + +int is_any_client_associated(_adapter *padapter) +{ + return padapter->stapriv.asoc_list_cnt ? _TRUE : _FALSE; +} + +static u32 go_add_group_info_attr(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + _irqL irqL; + _list *phead, *plist; + u32 len=0; + u16 attr_len = 0; + u8 tmplen, *pdata_attr, *pstart, *pcur; + struct sta_info *psta = NULL; + _adapter *padapter = pwdinfo->padapter; + struct sta_priv *pstapriv = &padapter->stapriv; + + DBG_871X("%s\n", __FUNCTION__); + + pdata_attr = rtw_zmalloc(MAX_P2P_IE_LEN); + + if(NULL == pdata_attr){ + DBG_871X("%s pdata_attr malloc failed \n", __FUNCTION__); + goto _exit; + } + + pstart = pdata_attr; + pcur = pdata_attr; + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + phead = &pstapriv->asoc_list; + plist = get_next(phead); + + //look up sta asoc_queue + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) + { + psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + + plist = get_next(plist); + + + if(psta->is_p2p_device) + { + tmplen = 0; + + pcur++; + + //P2P device address + _rtw_memcpy(pcur, psta->dev_addr, ETH_ALEN); + pcur += ETH_ALEN; + + //P2P interface address + _rtw_memcpy(pcur, psta->hwaddr, ETH_ALEN); + pcur += ETH_ALEN; + + *pcur = psta->dev_cap; + pcur++; + + //*(u16*)(pcur) = cpu_to_be16(psta->config_methods); + RTW_PUT_BE16(pcur, psta->config_methods); + pcur += 2; + + _rtw_memcpy(pcur, psta->primary_dev_type, 8); + pcur += 8; + + *pcur = psta->num_of_secdev_type; + pcur++; + + _rtw_memcpy(pcur, psta->secdev_types_list, psta->num_of_secdev_type*8); + pcur += psta->num_of_secdev_type*8; + + if(psta->dev_name_len>0) + { + //*(u16*)(pcur) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); + RTW_PUT_BE16(pcur, WPS_ATTR_DEVICE_NAME); + pcur += 2; + + //*(u16*)(pcur) = cpu_to_be16( psta->dev_name_len ); + RTW_PUT_BE16(pcur, psta->dev_name_len); + pcur += 2; + + _rtw_memcpy(pcur, psta->dev_name, psta->dev_name_len); + pcur += psta->dev_name_len; + } + + + tmplen = (u8)(pcur-pstart); + + *pstart = (tmplen-1); + + attr_len += tmplen; + + //pstart += tmplen; + pstart = pcur; + + } + + + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + if(attr_len>0) + { + len = rtw_set_p2p_attr_content(pbuf, P2P_ATTR_GROUP_INFO, attr_len, pdata_attr); + } + + rtw_mfree(pdata_attr, MAX_P2P_IE_LEN); + +_exit: + return len; + +} + +static void issue_group_disc_req(struct wifidirect_info *pwdinfo, u8 *da) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + _adapter *padapter = pwdinfo->padapter; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + unsigned char category = RTW_WLAN_CATEGORY_P2P;//P2P action frame + u32 p2poui = cpu_to_be32(P2POUI); + u8 oui_subtype = P2P_GO_DISC_REQUEST; + u8 dialogToken=0; + + DBG_871X("[%s]\n", __FUNCTION__); + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + { + return; + } + + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pwdinfo->interface_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, pwdinfo->interface_addr, ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + //Build P2P action frame header + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); + + //there is no IE in this P2P action frame + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + +} + +static void issue_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *da, u8 status, u8 dialogToken) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + _adapter *padapter = pwdinfo->padapter; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; + u8 action = P2P_PUB_ACTION_ACTION; + u32 p2poui = cpu_to_be32(P2POUI); + u8 oui_subtype = P2P_DEVDISC_RESP; + u8 p2pie[8] = { 0x00 }; + u32 p2pielen = 0; + + DBG_871X("[%s]\n", __FUNCTION__); + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + { + return; + } + + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pwdinfo->device_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, pwdinfo->device_addr, ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + //Build P2P public action frame header + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); + + + //Build P2P IE + // P2P OUI + p2pielen = 0; + p2pie[ p2pielen++ ] = 0x50; + p2pie[ p2pielen++ ] = 0x6F; + p2pie[ p2pielen++ ] = 0x9A; + p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 + + // P2P_ATTR_STATUS + p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status); + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, p2pie, &pattrib->pktlen); + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + +} + +static void issue_p2p_provision_resp(struct wifidirect_info *pwdinfo, u8* raddr, u8* frame_body, u16 config_method) +{ + _adapter *padapter = pwdinfo->padapter; + unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; + u8 action = P2P_PUB_ACTION_ACTION; + u8 dialogToken = frame_body[7]; // The Dialog Token of provisioning discovery request frame. + u32 p2poui = cpu_to_be32(P2POUI); + u8 oui_subtype = P2P_PROVISION_DISC_RESP; + u8 wpsie[ 100 ] = { 0x00 }; + u8 wpsielen = 0; +#ifdef CONFIG_WFD + u32 wfdielen = 0; +#endif + + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + { + return; + } + + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); + + wpsielen = 0; + // WPS OUI + //*(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); + RTW_PUT_BE32(wpsie, WPSOUI); + wpsielen += 4; + +#if 0 + // WPS version + // Type: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 ); + wpsielen += 2; + + // Length: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); + wpsielen += 2; + + // Value: + wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0 +#endif + + // Config Method + // Type: + //*(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD ); + RTW_PUT_BE16(wpsie + wpsielen, WPS_ATTR_CONF_METHOD); + wpsielen += 2; + + // Length: + //*(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); + RTW_PUT_BE16(wpsie + wpsielen, 0x0002); + wpsielen += 2; + + // Value: + //*(u16*) ( wpsie + wpsielen ) = cpu_to_be16( config_method ); + RTW_PUT_BE16(wpsie + wpsielen, config_method); + wpsielen += 2; + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen ); + +#ifdef CONFIG_WFD + wfdielen = build_provdisc_resp_wfd_ie(pwdinfo, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; +#endif + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + + return; + +} + +static void issue_p2p_presence_resp(struct wifidirect_info *pwdinfo, u8 *da, u8 status, u8 dialogToken) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + _adapter *padapter = pwdinfo->padapter; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + unsigned char category = RTW_WLAN_CATEGORY_P2P;//P2P action frame + u32 p2poui = cpu_to_be32(P2POUI); + u8 oui_subtype = P2P_PRESENCE_RESPONSE; + u8 p2pie[ MAX_P2P_IE_LEN] = { 0x00 }; + u8 noa_attr_content[32] = { 0x00 }; + u32 p2pielen = 0; + + DBG_871X("[%s]\n", __FUNCTION__); + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + { + return; + } + + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pwdinfo->interface_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, pwdinfo->interface_addr, ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + //Build P2P action frame header + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); + + + //Add P2P IE header + // P2P OUI + p2pielen = 0; + p2pie[ p2pielen++ ] = 0x50; + p2pie[ p2pielen++ ] = 0x6F; + p2pie[ p2pielen++ ] = 0x9A; + p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 + + //Add Status attribute in P2P IE + p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status); + + //Add NoA attribute in P2P IE + noa_attr_content[0] = 0x1;//index + noa_attr_content[1] = 0x0;//CTWindow and OppPS Parameters + + //todo: Notice of Absence Descriptor(s) + + p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_NOA, 2, noa_attr_content); + + + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, p2pie, &(pattrib->pktlen)); + + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + +} + +u32 build_beacon_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u8 p2pie[ MAX_P2P_IE_LEN] = { 0x00 }; + u16 capability=0; + u32 len=0, p2pielen = 0; + + + // P2P OUI + p2pielen = 0; + p2pie[ p2pielen++ ] = 0x50; + p2pie[ p2pielen++ ] = 0x6F; + p2pie[ p2pielen++ ] = 0x9A; + p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 + + + // According to the P2P Specification, the beacon frame should contain 3 P2P attributes + // 1. P2P Capability + // 2. P2P Device ID + // 3. Notice of Absence ( NOA ) + + // P2P Capability ATTR + // Type: + // Length: + // Value: + // Device Capability Bitmap, 1 byte + // Be able to participate in additional P2P Groups and + // support the P2P Invitation Procedure + // Group Capability Bitmap, 1 byte + capability = P2P_DEVCAP_INVITATION_PROC|P2P_DEVCAP_CLIENT_DISCOVERABILITY; + capability |= ((P2P_GRPCAP_GO | P2P_GRPCAP_INTRABSS) << 8); + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING)) + capability |= (P2P_GRPCAP_GROUP_FORMATION<<8); + + capability = cpu_to_le16(capability); + + p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_CAPABILITY, 2, (u8*)&capability); + + + // P2P Device ID ATTR + p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_DEVICE_ID, ETH_ALEN, pwdinfo->device_addr); + + + // Notice of Absence ATTR + // Type: + // Length: + // Value: + + //go_add_noa_attr(pwdinfo); + + + pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len); + + + return len; + +} + +#ifdef CONFIG_WFD +u32 build_beacon_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; + u16 val16=0; + u32 len=0, wfdielen = 0; + _adapter *padapter = pwdinfo->padapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info; + + if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + goto exit; + + // WFD OUI + wfdielen = 0; + wfdie[ wfdielen++ ] = 0x50; + wfdie[ wfdielen++ ] = 0x6F; + wfdie[ wfdielen++ ] = 0x9A; + wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 + + // Commented by Albert 20110812 + // According to the WFD Specification, the beacon frame should contain 4 WFD attributes + // 1. WFD Device Information + // 2. Associated BSSID + // 3. Coupled Sink Information + + + // WFD Device Information ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + // Value1: + // WFD device information + + if ( P2P_ROLE_GO == pwdinfo->role ) + { + if ( is_any_client_associated( pwdinfo->padapter ) ) + { + // WFD primary sink + WiFi Direct mode + WSD (WFD Service Discovery) + val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD; + RTW_PUT_BE16(wfdie + wfdielen, val16); + } + else + { + // WFD primary sink + available for WFD session + WiFi Direct mode + WSD (WFD Service Discovery) + val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD; + RTW_PUT_BE16(wfdie + wfdielen, val16); + } + + } + else + { + // WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) + val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD; + RTW_PUT_BE16(wfdie + wfdielen, val16); + } + + wfdielen += 2; + + // Value2: + // Session Management Control Port + // Default TCP port for RTSP messages is 554 + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); + wfdielen += 2; + + // Value3: + // WFD Device Maximum Throughput + // 300Mbps is the maximum throughput + RTW_PUT_BE16(wfdie + wfdielen, 300); + wfdielen += 2; + + // Associated BSSID ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + // Value: + // Associated BSSID + if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) + { + _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); + } + else + { + _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); + } + + wfdielen += ETH_ALEN; + + // Coupled Sink Information ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0007); + wfdielen += 2; + + // Value: + // Coupled Sink Status bitmap + // Not coupled/available for Coupling + wfdie[ wfdielen++ ] = 0; + // MAC Addr. + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + + rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); + +exit: + return len; +} + +u32 build_probe_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; + u16 val16=0; + u32 len=0, wfdielen = 0; + _adapter *padapter = pwdinfo->padapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info; + + if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + goto exit; + + // WFD OUI + wfdielen = 0; + wfdie[ wfdielen++ ] = 0x50; + wfdie[ wfdielen++ ] = 0x6F; + wfdie[ wfdielen++ ] = 0x9A; + wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 + + // Commented by Albert 20110812 + // According to the WFD Specification, the probe request frame should contain 4 WFD attributes + // 1. WFD Device Information + // 2. Associated BSSID + // 3. Coupled Sink Information + + + // WFD Device Information ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + // Value1: + // WFD device information + + if ( 1 == pwdinfo->wfd_tdls_enable ) + { + // WFD primary sink + available for WFD session + WiFi TDLS mode + WSC ( WFD Service Discovery ) + val16 = pwfd_info->wfd_device_type | + WFD_DEVINFO_SESSION_AVAIL | + WFD_DEVINFO_WSD | + WFD_DEVINFO_PC_TDLS; + RTW_PUT_BE16(wfdie + wfdielen, val16 ); + } + else + { + // WFD primary sink + available for WFD session + WiFi Direct mode + WSC ( WFD Service Discovery ) + val16 = pwfd_info->wfd_device_type | + WFD_DEVINFO_SESSION_AVAIL | + WFD_DEVINFO_WSD; + RTW_PUT_BE16(wfdie + wfdielen, val16 ); + } + + wfdielen += 2; + + // Value2: + // Session Management Control Port + // Default TCP port for RTSP messages is 554 + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); + wfdielen += 2; + + // Value3: + // WFD Device Maximum Throughput + // 300Mbps is the maximum throughput + RTW_PUT_BE16(wfdie + wfdielen, 300); + wfdielen += 2; + + // Associated BSSID ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + // Value: + // Associated BSSID + if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) + { + _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); + } + else + { + _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); + } + + wfdielen += ETH_ALEN; + + // Coupled Sink Information ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0007); + wfdielen += 2; + + // Value: + // Coupled Sink Status bitmap + // Not coupled/available for Coupling + wfdie[ wfdielen++ ] = 0; + // MAC Addr. + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + + rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); + +exit: + return len; +} + +u32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 tunneled) +{ + u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; + u32 len=0, wfdielen = 0; + _adapter *padapter = pwdinfo->padapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info; + + if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + goto exit; + + // WFD OUI + wfdielen = 0; + wfdie[ wfdielen++ ] = 0x50; + wfdie[ wfdielen++ ] = 0x6F; + wfdie[ wfdielen++ ] = 0x9A; + wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 + + // Commented by Albert 20110812 + // According to the WFD Specification, the probe response frame should contain 4 WFD attributes + // 1. WFD Device Information + // 2. Associated BSSID + // 3. Coupled Sink Information + // 4. WFD Session Information + + + // WFD Device Information ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + // Value1: + // WFD device information + // WFD primary sink + available for WFD session + WiFi Direct mode + + if ( _TRUE == pwdinfo->session_available ) + { + if ( P2P_ROLE_GO == pwdinfo->role ) + { + if ( is_any_client_associated( pwdinfo->padapter ) ) + { + if ( pwdinfo->wfd_tdls_enable ) + { + // TDLS mode + WSD ( WFD Service Discovery ) + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT); + } + else + { + // WiFi Direct mode + WSD ( WFD Service Discovery ) + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT); + } + } + else + { + if ( pwdinfo->wfd_tdls_enable ) + { + // available for WFD session + TDLS mode + WSD ( WFD Service Discovery ) + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT); + } + else + { + // available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT); + } + } + } + else + { + if ( pwdinfo->wfd_tdls_enable ) + { + // available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT); + } + else + { + + // available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT); + } + } + } + else + { + if ( pwdinfo->wfd_tdls_enable ) + { + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD |WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_HDCP_SUPPORT); + } + else + { + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_HDCP_SUPPORT); + } + + } + + wfdielen += 2; + + // Value2: + // Session Management Control Port + // Default TCP port for RTSP messages is 554 + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); + wfdielen += 2; + + // Value3: + // WFD Device Maximum Throughput + // 300Mbps is the maximum throughput + RTW_PUT_BE16(wfdie + wfdielen, 300); + wfdielen += 2; + + // Associated BSSID ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + // Value: + // Associated BSSID + if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) + { + _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); + } + else + { + _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); + } + + wfdielen += ETH_ALEN; + + // Coupled Sink Information ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0007); + wfdielen += 2; + + // Value: + // Coupled Sink Status bitmap + // Not coupled/available for Coupling + wfdie[ wfdielen++ ] = 0; + // MAC Addr. + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + + if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) + { + // WFD Session Information ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_SESSION_INFO; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0000); + wfdielen += 2; + + // Todo: to add the list of WFD device info descriptor in WFD group. + + } +#ifdef CONFIG_CONCURRENT_MODE +#ifdef CONFIG_TDLS + if ( ( tunneled == 0 ) && ( padapter->pbuddy_adapter->wdinfo.wfd_tdls_enable == 1 ) ) + { + // Alternative MAC Address ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_ALTER_MAC; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, ETH_ALEN ); + wfdielen += 2; + + // Value: + // Alternative MAC Address + _rtw_memcpy(wfdie + wfdielen, adapter_mac_addr(padapter->pbuddy_adapter), ETH_ALEN); + // This mac address is used to make the WFD session when TDLS is enable. + + wfdielen += ETH_ALEN; + } +#endif // CONFIG_TDLS +#endif // CONFIG_CONCURRENT_MODE + + pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); + +exit: + return len; +} + +u32 build_assoc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; + u16 val16=0; + u32 len=0, wfdielen = 0; + _adapter *padapter = NULL; + struct mlme_priv *pmlmepriv = NULL; + struct wifi_display_info *pwfd_info = NULL; + + padapter = pwdinfo->padapter; + pmlmepriv = &padapter->mlmepriv; + pwfd_info = padapter->wdinfo.wfd_info; + + if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + goto exit; + + if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) + goto exit; + + /* WFD OUI */ + wfdielen = 0; + wfdie[ wfdielen++ ] = 0x50; + wfdie[ wfdielen++ ] = 0x6F; + wfdie[ wfdielen++ ] = 0x9A; + wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 + + // Commented by Albert 20110812 + // According to the WFD Specification, the probe request frame should contain 4 WFD attributes + // 1. WFD Device Information + // 2. Associated BSSID + // 3. Coupled Sink Information + + + // WFD Device Information ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + // Value1: + // WFD device information + // WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) + val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD; + RTW_PUT_BE16(wfdie + wfdielen, val16); + wfdielen += 2; + + // Value2: + // Session Management Control Port + // Default TCP port for RTSP messages is 554 + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); + wfdielen += 2; + + // Value3: + // WFD Device Maximum Throughput + // 300Mbps is the maximum throughput + RTW_PUT_BE16(wfdie + wfdielen, 300); + wfdielen += 2; + + // Associated BSSID ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + // Value: + // Associated BSSID + if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) + { + _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); + } + else + { + _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); + } + + wfdielen += ETH_ALEN; + + // Coupled Sink Information ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0007); + wfdielen += 2; + + // Value: + // Coupled Sink Status bitmap + // Not coupled/available for Coupling + wfdie[ wfdielen++ ] = 0; + // MAC Addr. + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + + rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); + +exit: + return len; +} + +u32 build_assoc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; + u32 len=0, wfdielen = 0; + u16 val16=0; + _adapter *padapter = pwdinfo->padapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info; + + if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + goto exit; + + // WFD OUI + wfdielen = 0; + wfdie[ wfdielen++ ] = 0x50; + wfdie[ wfdielen++ ] = 0x6F; + wfdie[ wfdielen++ ] = 0x9A; + wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 + + // Commented by Albert 20110812 + // According to the WFD Specification, the probe request frame should contain 4 WFD attributes + // 1. WFD Device Information + // 2. Associated BSSID + // 3. Coupled Sink Information + + + // WFD Device Information ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + // Value1: + // WFD device information + // WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) + val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD; + RTW_PUT_BE16(wfdie + wfdielen, val16); + wfdielen += 2; + + // Value2: + // Session Management Control Port + // Default TCP port for RTSP messages is 554 + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); + wfdielen += 2; + + // Value3: + // WFD Device Maximum Throughput + // 300Mbps is the maximum throughput + RTW_PUT_BE16(wfdie + wfdielen, 300); + wfdielen += 2; + + // Associated BSSID ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + // Value: + // Associated BSSID + if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) + { + _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); + } + else + { + _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); + } + + wfdielen += ETH_ALEN; + + // Coupled Sink Information ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0007); + wfdielen += 2; + + // Value: + // Coupled Sink Status bitmap + // Not coupled/available for Coupling + wfdie[ wfdielen++ ] = 0; + // MAC Addr. + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + + rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); + +exit: + return len; +} + +u32 build_nego_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; + u32 len=0, wfdielen = 0; + u16 val16=0; + _adapter *padapter = pwdinfo->padapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info; + + if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + goto exit; + + // WFD OUI + wfdielen = 0; + wfdie[ wfdielen++ ] = 0x50; + wfdie[ wfdielen++ ] = 0x6F; + wfdie[ wfdielen++ ] = 0x9A; + wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 + + // Commented by Albert 20110825 + // According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes + // 1. WFD Device Information + // 2. Associated BSSID ( Optional ) + // 3. Local IP Adress ( Optional ) + + + // WFD Device Information ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + // Value1: + // WFD device information + // WFD primary sink + WiFi Direct mode + WSD ( WFD Service Discovery ) + WFD Session Available + val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_SESSION_AVAIL; + RTW_PUT_BE16(wfdie + wfdielen, val16); + wfdielen += 2; + + // Value2: + // Session Management Control Port + // Default TCP port for RTSP messages is 554 + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); + wfdielen += 2; + + // Value3: + // WFD Device Maximum Throughput + // 300Mbps is the maximum throughput + RTW_PUT_BE16(wfdie + wfdielen, 300); + wfdielen += 2; + + // Associated BSSID ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + // Value: + // Associated BSSID + if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) + { + _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); + } + else + { + _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); + } + + wfdielen += ETH_ALEN; + + // Coupled Sink Information ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0007); + wfdielen += 2; + + // Value: + // Coupled Sink Status bitmap + // Not coupled/available for Coupling + wfdie[ wfdielen++ ] = 0; + // MAC Addr. + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + + rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); + +exit: + return len; +} + +u32 build_nego_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; + u32 len=0, wfdielen = 0; + u16 val16=0; + _adapter *padapter = pwdinfo->padapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info; + + if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + goto exit; + + // WFD OUI + wfdielen = 0; + wfdie[ wfdielen++ ] = 0x50; + wfdie[ wfdielen++ ] = 0x6F; + wfdie[ wfdielen++ ] = 0x9A; + wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 + + // Commented by Albert 20110825 + // According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes + // 1. WFD Device Information + // 2. Associated BSSID ( Optional ) + // 3. Local IP Adress ( Optional ) + + + // WFD Device Information ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + // Value1: + // WFD device information + // WFD primary sink + WiFi Direct mode + WSD ( WFD Service Discovery ) + WFD Session Available + val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_SESSION_AVAIL; + RTW_PUT_BE16(wfdie + wfdielen, val16); + wfdielen += 2; + + // Value2: + // Session Management Control Port + // Default TCP port for RTSP messages is 554 + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); + wfdielen += 2; + + // Value3: + // WFD Device Maximum Throughput + // 300Mbps is the maximum throughput + RTW_PUT_BE16(wfdie + wfdielen, 300); + wfdielen += 2; + + // Associated BSSID ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + // Value: + // Associated BSSID + if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) + { + _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); + } + else + { + _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); + } + + wfdielen += ETH_ALEN; + + // Coupled Sink Information ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0007); + wfdielen += 2; + + // Value: + // Coupled Sink Status bitmap + // Not coupled/available for Coupling + wfdie[ wfdielen++ ] = 0; + // MAC Addr. + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + + + rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); + +exit: + return len; +} + +u32 build_nego_confirm_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; + u32 len=0, wfdielen = 0; + u16 val16=0; + _adapter *padapter = pwdinfo->padapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info; + + if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + goto exit; + + // WFD OUI + wfdielen = 0; + wfdie[ wfdielen++ ] = 0x50; + wfdie[ wfdielen++ ] = 0x6F; + wfdie[ wfdielen++ ] = 0x9A; + wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 + + // Commented by Albert 20110825 + // According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes + // 1. WFD Device Information + // 2. Associated BSSID ( Optional ) + // 3. Local IP Adress ( Optional ) + + + // WFD Device Information ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + // Value1: + // WFD device information + // WFD primary sink + WiFi Direct mode + WSD ( WFD Service Discovery ) + WFD Session Available + val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_WSD | WFD_DEVINFO_SESSION_AVAIL; + RTW_PUT_BE16(wfdie + wfdielen, val16); + wfdielen += 2; + + // Value2: + // Session Management Control Port + // Default TCP port for RTSP messages is 554 + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); + wfdielen += 2; + + // Value3: + // WFD Device Maximum Throughput + // 300Mbps is the maximum throughput + RTW_PUT_BE16(wfdie + wfdielen, 300); + wfdielen += 2; + + // Associated BSSID ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + // Value: + // Associated BSSID + if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) + { + _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); + } + else + { + _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); + } + + wfdielen += ETH_ALEN; + + // Coupled Sink Information ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0007); + wfdielen += 2; + + // Value: + // Coupled Sink Status bitmap + // Not coupled/available for Coupling + wfdie[ wfdielen++ ] = 0; + // MAC Addr. + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + + + pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); + +exit: + return len; +} + +u32 build_invitation_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; + u32 len=0, wfdielen = 0; + u16 val16=0; + _adapter *padapter = pwdinfo->padapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info; + + if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + goto exit; + + // WFD OUI + wfdielen = 0; + wfdie[ wfdielen++ ] = 0x50; + wfdie[ wfdielen++ ] = 0x6F; + wfdie[ wfdielen++ ] = 0x9A; + wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 + + // Commented by Albert 20110825 + // According to the WFD Specification, the provision discovery request frame should contain 3 WFD attributes + // 1. WFD Device Information + // 2. Associated BSSID ( Optional ) + // 3. Local IP Adress ( Optional ) + + + // WFD Device Information ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + // Value1: + // WFD device information + // WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) + val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD; + RTW_PUT_BE16(wfdie + wfdielen, val16); + wfdielen += 2; + + // Value2: + // Session Management Control Port + // Default TCP port for RTSP messages is 554 + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); + wfdielen += 2; + + // Value3: + // WFD Device Maximum Throughput + // 300Mbps is the maximum throughput + RTW_PUT_BE16(wfdie + wfdielen, 300); + wfdielen += 2; + + // Associated BSSID ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + // Value: + // Associated BSSID + if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) + { + _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); + } + else + { + _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); + } + + wfdielen += ETH_ALEN; + + // Coupled Sink Information ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0007); + wfdielen += 2; + + // Value: + // Coupled Sink Status bitmap + // Not coupled/available for Coupling + wfdie[ wfdielen++ ] = 0; + // MAC Addr. + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + + if ( P2P_ROLE_GO == pwdinfo->role ) + { + // WFD Session Information ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_SESSION_INFO; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0000); + wfdielen += 2; + + // Todo: to add the list of WFD device info descriptor in WFD group. + + } + + rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); + +exit: + return len; +} + +u32 build_invitation_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; + u16 val16=0; + u32 len=0, wfdielen = 0; + _adapter *padapter = pwdinfo->padapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info; + + if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + goto exit; + + // WFD OUI + wfdielen = 0; + wfdie[ wfdielen++ ] = 0x50; + wfdie[ wfdielen++ ] = 0x6F; + wfdie[ wfdielen++ ] = 0x9A; + wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 + + // Commented by Albert 20110825 + // According to the WFD Specification, the provision discovery request frame should contain 3 WFD attributes + // 1. WFD Device Information + // 2. Associated BSSID ( Optional ) + // 3. Local IP Adress ( Optional ) + + + // WFD Device Information ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + // Value1: + // WFD device information + // WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) + val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD; + RTW_PUT_BE16(wfdie + wfdielen, val16); + wfdielen += 2; + + // Value2: + // Session Management Control Port + // Default TCP port for RTSP messages is 554 + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); + wfdielen += 2; + + // Value3: + // WFD Device Maximum Throughput + // 300Mbps is the maximum throughput + RTW_PUT_BE16(wfdie + wfdielen, 300); + wfdielen += 2; + + // Associated BSSID ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + // Value: + // Associated BSSID + if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) + { + _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); + } + else + { + _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); + } + + wfdielen += ETH_ALEN; + + // Coupled Sink Information ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0007); + wfdielen += 2; + + // Value: + // Coupled Sink Status bitmap + // Not coupled/available for Coupling + wfdie[ wfdielen++ ] = 0; + // MAC Addr. + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + + if ( P2P_ROLE_GO == pwdinfo->role ) + { + // WFD Session Information ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_SESSION_INFO; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0000); + wfdielen += 2; + + // Todo: to add the list of WFD device info descriptor in WFD group. + + } + + rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); + +exit: + return len; +} + +u32 build_provdisc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; + u32 len=0, wfdielen = 0; + u16 val16=0; + _adapter *padapter = pwdinfo->padapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info; + + if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + goto exit; + + // WFD OUI + wfdielen = 0; + wfdie[ wfdielen++ ] = 0x50; + wfdie[ wfdielen++ ] = 0x6F; + wfdie[ wfdielen++ ] = 0x9A; + wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 + + // Commented by Albert 20110825 + // According to the WFD Specification, the provision discovery request frame should contain 3 WFD attributes + // 1. WFD Device Information + // 2. Associated BSSID ( Optional ) + // 3. Local IP Adress ( Optional ) + + + // WFD Device Information ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + // Value1: + // WFD device information + // WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) + val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD; + RTW_PUT_BE16(wfdie + wfdielen, val16); + wfdielen += 2; + + // Value2: + // Session Management Control Port + // Default TCP port for RTSP messages is 554 + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); + wfdielen += 2; + + // Value3: + // WFD Device Maximum Throughput + // 300Mbps is the maximum throughput + RTW_PUT_BE16(wfdie + wfdielen, 300); + wfdielen += 2; + + // Associated BSSID ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + // Value: + // Associated BSSID + if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) + { + _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); + } + else + { + _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); + } + + wfdielen += ETH_ALEN; + + // Coupled Sink Information ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0007); + wfdielen += 2; + + // Value: + // Coupled Sink Status bitmap + // Not coupled/available for Coupling + wfdie[ wfdielen++ ] = 0; + // MAC Addr. + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + + + rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); + +exit: + return len; +} + +u32 build_provdisc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; + u32 len=0, wfdielen = 0; + u16 val16=0; + _adapter *padapter = pwdinfo->padapter; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wifi_display_info* pwfd_info = padapter->wdinfo.wfd_info; + + if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + goto exit; + + // WFD OUI + wfdielen = 0; + wfdie[ wfdielen++ ] = 0x50; + wfdie[ wfdielen++ ] = 0x6F; + wfdie[ wfdielen++ ] = 0x9A; + wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 + + // Commented by Albert 20110825 + // According to the WFD Specification, the provision discovery response frame should contain 3 WFD attributes + // 1. WFD Device Information + // 2. Associated BSSID ( Optional ) + // 3. Local IP Adress ( Optional ) + + + // WFD Device Information ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + // Value1: + // WFD device information + // WFD primary sink + available for WFD session + WiFi Direct mode + WSD ( WFD Service Discovery ) + val16 = pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL | WFD_DEVINFO_WSD; + RTW_PUT_BE16(wfdie + wfdielen, val16); + wfdielen += 2; + + // Value2: + // Session Management Control Port + // Default TCP port for RTSP messages is 554 + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); + wfdielen += 2; + + // Value3: + // WFD Device Maximum Throughput + // 300Mbps is the maximum throughput + RTW_PUT_BE16(wfdie + wfdielen, 300); + wfdielen += 2; + + // Associated BSSID ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + // Value: + // Associated BSSID + if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) + { + _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); + } + else + { + _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); + } + + wfdielen += ETH_ALEN; + + // Coupled Sink Information ATTR + // Type: + wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; + + // Length: + // Note: In the WFD specification, the size of length field is 2. + RTW_PUT_BE16(wfdie + wfdielen, 0x0007); + wfdielen += 2; + + // Value: + // Coupled Sink Status bitmap + // Not coupled/available for Coupling + wfdie[ wfdielen++ ] = 0; + // MAC Addr. + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + wfdie[ wfdielen++ ] = 0; + + rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); + +exit: + return len; +} +#endif /* CONFIG_WFD */ + +u32 build_probe_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u8 p2pie[ MAX_P2P_IE_LEN] = { 0x00 }; + u32 len=0, p2pielen = 0; +#ifdef CONFIG_INTEL_WIDI + struct mlme_priv *pmlmepriv = &(pwdinfo->padapter->mlmepriv); + u8 zero_array_check[L2SDTA_SERVICE_VE_LEN] = { 0x00 }; + u8 widi_version = 0, i = 0; + + if( _rtw_memcmp( pmlmepriv->sa_ext, zero_array_check, L2SDTA_SERVICE_VE_LEN ) == _FALSE ) + { + widi_version = 35; + } + else if( pmlmepriv->num_p2p_sdt != 0 ) + { + widi_version = 40; + } +#endif //CONFIG_INTEL_WIDI + + // P2P OUI + p2pielen = 0; + p2pie[ p2pielen++ ] = 0x50; + p2pie[ p2pielen++ ] = 0x6F; + p2pie[ p2pielen++ ] = 0x9A; + p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 + + // Commented by Albert 20100907 + // According to the P2P Specification, the probe response frame should contain 5 P2P attributes + // 1. P2P Capability + // 2. Extended Listen Timing + // 3. Notice of Absence ( NOA ) ( Only GO needs this ) + // 4. Device Info + // 5. Group Info ( Only GO need this ) + + // P2P Capability ATTR + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY; + + // Length: + //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); + RTW_PUT_LE16(p2pie + p2pielen, 0x0002); + p2pielen += 2; + + // Value: + // Device Capability Bitmap, 1 byte + p2pie[ p2pielen++ ] = DMP_P2P_DEVCAP_SUPPORT; + + // Group Capability Bitmap, 1 byte + if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) + { + p2pie[ p2pielen ] = (P2P_GRPCAP_GO | P2P_GRPCAP_INTRABSS); + + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING)) + p2pie[ p2pielen ] |= P2P_GRPCAP_GROUP_FORMATION; + + p2pielen++; + } + else if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) ) + { + // Group Capability Bitmap, 1 byte + if ( pwdinfo->persistent_supported ) + p2pie[ p2pielen++ ] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT; + else + p2pie[ p2pielen++ ] = DMP_P2P_GRPCAP_SUPPORT; + } + + // Extended Listen Timing ATTR + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_EX_LISTEN_TIMING; + + // Length: + //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0004 ); + RTW_PUT_LE16(p2pie + p2pielen, 0x0004); + p2pielen += 2; + + // Value: + // Availability Period + //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); + RTW_PUT_LE16(p2pie + p2pielen, 0xFFFF); + p2pielen += 2; + + // Availability Interval + //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); + RTW_PUT_LE16(p2pie + p2pielen, 0xFFFF); + p2pielen += 2; + + + // Notice of Absence ATTR + // Type: + // Length: + // Value: + if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) + { + //go_add_noa_attr(pwdinfo); + } + + // Device Info ATTR + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO; + + // Length: + // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) + // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) + //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); +#ifdef CONFIG_INTEL_WIDI + if( widi_version == 35 ) + { + RTW_PUT_LE16(p2pie + p2pielen, 21 + 8 + pwdinfo->device_name_len); + } + else if( widi_version == 40 ) + { + RTW_PUT_LE16(p2pie + p2pielen, 21 + 8 * pmlmepriv->num_p2p_sdt + pwdinfo->device_name_len); + } + else +#endif //CONFIG_INTEL_WIDI + RTW_PUT_LE16(p2pie + p2pielen, 21 + pwdinfo->device_name_len); + p2pielen += 2; + + // Value: + // P2P Device Address + _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN ); + p2pielen += ETH_ALEN; + + // Config Method + // This field should be big endian. Noted by P2P specification. + //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->supported_wps_cm ); + RTW_PUT_BE16(p2pie + p2pielen, pwdinfo->supported_wps_cm); + p2pielen += 2; + +#ifdef CONFIG_INTEL_WIDI + if( widi_version == 40 ) + { + // Primary Device Type + // Category ID + //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); + RTW_PUT_BE16(p2pie + p2pielen, pmlmepriv->p2p_pdt_cid ); + p2pielen += 2; + + // OUI + //*(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); + RTW_PUT_BE32(p2pie + p2pielen, WPSOUI); + p2pielen += 4; + + // Sub Category ID + //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); + RTW_PUT_BE16(p2pie + p2pielen, pmlmepriv->p2p_pdt_scid); + p2pielen += 2; + } + else +#endif //CONFIG_INTEL_WIDI + { + // Primary Device Type + // Category ID + //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); + RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_CID_MULIT_MEDIA); + p2pielen += 2; + + // OUI + //*(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); + RTW_PUT_BE32(p2pie + p2pielen, WPSOUI); + p2pielen += 4; + + // Sub Category ID + //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); + RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_SCID_MEDIA_SERVER); + p2pielen += 2; + } + + // Number of Secondary Device Types +#ifdef CONFIG_INTEL_WIDI + if( widi_version == 35 ) + { + p2pie[ p2pielen++ ] = 0x01; + + RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_CID_DISPLAYS); + p2pielen += 2; + + RTW_PUT_BE32(p2pie + p2pielen, INTEL_DEV_TYPE_OUI); + p2pielen += 4; + + RTW_PUT_BE16(p2pie + p2pielen, P2P_SCID_WIDI_CONSUMER_SINK); + p2pielen += 2; + } + else if( widi_version == 40 ) + { + p2pie[ p2pielen++ ] = pmlmepriv->num_p2p_sdt; + for( ; i < pmlmepriv->num_p2p_sdt; i++ ) + { + RTW_PUT_BE16(p2pie + p2pielen, pmlmepriv->p2p_sdt_cid[i]); + p2pielen += 2; + + RTW_PUT_BE32(p2pie + p2pielen, INTEL_DEV_TYPE_OUI); + p2pielen += 4; + + RTW_PUT_BE16(p2pie + p2pielen, pmlmepriv->p2p_sdt_scid[i]); + p2pielen += 2; + } + } + else +#endif //CONFIG_INTEL_WIDI + p2pie[ p2pielen++ ] = 0x00; // No Secondary Device Type List + + // Device Name + // Type: + //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); + RTW_PUT_BE16(p2pie + p2pielen, WPS_ATTR_DEVICE_NAME); + p2pielen += 2; + + // Length: + //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); + RTW_PUT_BE16(p2pie + p2pielen, pwdinfo->device_name_len); + p2pielen += 2; + + // Value: + _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len ); + p2pielen += pwdinfo->device_name_len; + + // Group Info ATTR + // Type: + // Length: + // Value: + if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) + { + p2pielen += go_add_group_info_attr(pwdinfo, p2pie + p2pielen); + } + + + pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len); + + + return len; + +} + +u32 build_prov_disc_request_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8* pssid, u8 ussidlen, u8* pdev_raddr ) +{ + u8 p2pie[ MAX_P2P_IE_LEN] = { 0x00 }; + u32 len=0, p2pielen = 0; + + // P2P OUI + p2pielen = 0; + p2pie[ p2pielen++ ] = 0x50; + p2pie[ p2pielen++ ] = 0x6F; + p2pie[ p2pielen++ ] = 0x9A; + p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 + + // Commented by Albert 20110301 + // According to the P2P Specification, the provision discovery request frame should contain 3 P2P attributes + // 1. P2P Capability + // 2. Device Info + // 3. Group ID ( When joining an operating P2P Group ) + + // P2P Capability ATTR + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY; + + // Length: + //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); + RTW_PUT_LE16(p2pie + p2pielen, 0x0002); + p2pielen += 2; + + // Value: + // Device Capability Bitmap, 1 byte + p2pie[ p2pielen++ ] = DMP_P2P_DEVCAP_SUPPORT; + + // Group Capability Bitmap, 1 byte + if ( pwdinfo->persistent_supported ) + p2pie[ p2pielen++ ] = P2P_GRPCAP_PERSISTENT_GROUP | DMP_P2P_GRPCAP_SUPPORT; + else + p2pie[ p2pielen++ ] = DMP_P2P_GRPCAP_SUPPORT; + + + // Device Info ATTR + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO; + + // Length: + // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) + // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) + //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); + RTW_PUT_LE16(p2pie + p2pielen, 21 + pwdinfo->device_name_len); + p2pielen += 2; + + // Value: + // P2P Device Address + _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN ); + p2pielen += ETH_ALEN; + + // Config Method + // This field should be big endian. Noted by P2P specification. + if ( pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PBC ) + { + //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_PBC ); + RTW_PUT_BE16(p2pie + p2pielen, WPS_CONFIG_METHOD_PBC); + } + else + { + //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_DISPLAY ); + RTW_PUT_BE16(p2pie + p2pielen, WPS_CONFIG_METHOD_DISPLAY); + } + + p2pielen += 2; + + // Primary Device Type + // Category ID + //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_MULIT_MEDIA ); + RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_CID_MULIT_MEDIA); + p2pielen += 2; + + // OUI + //*(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); + RTW_PUT_BE32(p2pie + p2pielen, WPSOUI); + p2pielen += 4; + + // Sub Category ID + //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_MEDIA_SERVER ); + RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_SCID_MEDIA_SERVER); + p2pielen += 2; + + // Number of Secondary Device Types + p2pie[ p2pielen++ ] = 0x00; // No Secondary Device Type List + + // Device Name + // Type: + //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); + RTW_PUT_BE16(p2pie + p2pielen, WPS_ATTR_DEVICE_NAME); + p2pielen += 2; + + // Length: + //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); + RTW_PUT_BE16(p2pie + p2pielen, pwdinfo->device_name_len); + p2pielen += 2; + + // Value: + _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len ); + p2pielen += pwdinfo->device_name_len; + + if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) ) + { + // Added by Albert 2011/05/19 + // In this case, the pdev_raddr is the device address of the group owner. + + // P2P Group ID ATTR + // Type: + p2pie[ p2pielen++ ] = P2P_ATTR_GROUP_ID; + + // Length: + //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN + ussidlen ); + RTW_PUT_LE16(p2pie + p2pielen, ETH_ALEN + ussidlen); + p2pielen += 2; + + // Value: + _rtw_memcpy( p2pie + p2pielen, pdev_raddr, ETH_ALEN ); + p2pielen += ETH_ALEN; + + _rtw_memcpy( p2pie + p2pielen, pssid, ussidlen ); + p2pielen += ussidlen; + + } + + pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len); + + + return len; + +} + + +u32 build_assoc_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 status_code) +{ + u8 p2pie[ MAX_P2P_IE_LEN] = { 0x00 }; + u32 len=0, p2pielen = 0; + + // P2P OUI + p2pielen = 0; + p2pie[ p2pielen++ ] = 0x50; + p2pie[ p2pielen++ ] = 0x6F; + p2pie[ p2pielen++ ] = 0x9A; + p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 + + // According to the P2P Specification, the Association response frame should contain 2 P2P attributes + // 1. Status + // 2. Extended Listen Timing (optional) + + + // Status ATTR + p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status_code); + + + // Extended Listen Timing ATTR + // Type: + // Length: + // Value: + + + pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len); + + return len; + +} + +u32 build_deauth_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) +{ + u32 len=0; + + return len; +} + +u32 process_probe_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) +{ + u8 *p; + u32 ret=_FALSE; + u8 *p2pie; + u32 p2pielen = 0; + int ssid_len=0, rate_cnt = 0; + + p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SUPPORTEDRATES_IE_, (int *)&rate_cnt, + len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_); + + if ( rate_cnt <= 4 ) + { + int i, g_rate =0; + + for( i = 0; i < rate_cnt; i++ ) + { + if ( ( ( *( p + 2 + i ) & 0xff ) != 0x02 ) && + ( ( *( p + 2 + i ) & 0xff ) != 0x04 ) && + ( ( *( p + 2 + i ) & 0xff ) != 0x0B ) && + ( ( *( p + 2 + i ) & 0xff ) != 0x16 ) ) + { + g_rate = 1; + } + } + + if ( g_rate == 0 ) + { + // There is no OFDM rate included in SupportedRates IE of this probe request frame + // The driver should response this probe request. + return ret; + } + } + else + { + // rate_cnt > 4 means the SupportRates IE contains the OFDM rate because the count of CCK rates are 4. + // We should proceed the following check for this probe request. + } + + // Added comments by Albert 20100906 + // There are several items we should check here. + // 1. This probe request frame must contain the P2P IE. (Done) + // 2. This probe request frame must contain the wildcard SSID. (Done) + // 3. Wildcard BSSID. (Todo) + // 4. Destination Address. ( Done in mgt_dispatcher function ) + // 5. Requested Device Type in WSC IE. (Todo) + // 6. Device ID attribute in P2P IE. (Todo) + + p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SSID_IE_, (int *)&ssid_len, + len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_); + + ssid_len &= 0xff; // Just last 1 byte is valid for ssid len of the probe request + if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) + { + if((p2pie=rtw_get_p2p_ie( pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_ , len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_ , NULL, &p2pielen))) + { + if ( (p != NULL) && _rtw_memcmp( ( void * ) ( p+2 ), ( void * ) pwdinfo->p2p_wildcard_ssid , 7 )) + { + //todo: + //Check Requested Device Type attributes in WSC IE. + //Check Device ID attribute in P2P IE + + ret = _TRUE; + } + else if ( (p != NULL) && ( ssid_len == 0 ) ) + { + ret = _TRUE; + } + } + else + { + //non -p2p device + } + + } + + + return ret; + +} + +u32 process_assoc_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len, struct sta_info *psta) +{ + u8 status_code = P2P_STATUS_SUCCESS; + u8 *pbuf, *pattr_content=NULL; + u32 attr_contentlen = 0; + u16 cap_attr=0; + unsigned short frame_type, ie_offset=0; + u8 * ies; + u32 ies_len; + u8 * p2p_ie; + u32 p2p_ielen = 0; + + if(!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) + return P2P_STATUS_FAIL_REQUEST_UNABLE; + + frame_type = GetFrameSubType(pframe); + if (frame_type == WIFI_ASSOCREQ) + { + ie_offset = _ASOCREQ_IE_OFFSET_; + } + else // WIFI_REASSOCREQ + { + ie_offset = _REASOCREQ_IE_OFFSET_; + } + + ies = pframe + WLAN_HDR_A3_LEN + ie_offset; + ies_len = len - WLAN_HDR_A3_LEN - ie_offset; + + p2p_ie = rtw_get_p2p_ie(ies , ies_len , NULL, &p2p_ielen); + + if ( !p2p_ie ) + { + DBG_8192C( "[%s] P2P IE not Found!!\n", __FUNCTION__ ); + status_code = P2P_STATUS_FAIL_INVALID_PARAM; + } + else + { + DBG_8192C( "[%s] P2P IE Found!!\n", __FUNCTION__ ); + } + + while ( p2p_ie ) + { + //Check P2P Capability ATTR + if( rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8*)&cap_attr, (uint*) &attr_contentlen) ) + { + DBG_8192C( "[%s] Got P2P Capability Attr!!\n", __FUNCTION__ ); + cap_attr = le16_to_cpu(cap_attr); + psta->dev_cap = cap_attr&0xff; + } + + //Check Extended Listen Timing ATTR + + + //Check P2P Device Info ATTR + if(rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO, NULL, (uint*)&attr_contentlen)) + { + DBG_8192C( "[%s] Got P2P DEVICE INFO Attr!!\n", __FUNCTION__ ); + pattr_content = pbuf = rtw_zmalloc(attr_contentlen); + if(pattr_content) + { + u8 num_of_secdev_type; + u16 dev_name_len; + + + rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO , pattr_content, (uint*)&attr_contentlen); + + _rtw_memcpy(psta->dev_addr, pattr_content, ETH_ALEN);//P2P Device Address + + pattr_content += ETH_ALEN; + + _rtw_memcpy(&psta->config_methods, pattr_content, 2);//Config Methods + psta->config_methods = be16_to_cpu(psta->config_methods); + + pattr_content += 2; + + _rtw_memcpy(psta->primary_dev_type, pattr_content, 8); + + pattr_content += 8; + + num_of_secdev_type = *pattr_content; + pattr_content += 1; + + if(num_of_secdev_type==0) + { + psta->num_of_secdev_type = 0; + } + else + { + u32 len; + + psta->num_of_secdev_type = num_of_secdev_type; + + len = (sizeof(psta->secdev_types_list)<(num_of_secdev_type*8)) ? (sizeof(psta->secdev_types_list)) : (num_of_secdev_type*8); + + _rtw_memcpy(psta->secdev_types_list, pattr_content, len); + + pattr_content += (num_of_secdev_type*8); + } + + + //dev_name_len = attr_contentlen - ETH_ALEN - 2 - 8 - 1 - (num_of_secdev_type*8); + psta->dev_name_len=0; + if(WPS_ATTR_DEVICE_NAME == be16_to_cpu(*(u16*)pattr_content)) + { + dev_name_len = be16_to_cpu(*(u16*)(pattr_content+2)); + + psta->dev_name_len = (sizeof(psta->dev_name)dev_name):dev_name_len; + + _rtw_memcpy(psta->dev_name, pattr_content+4, psta->dev_name_len); + } + + rtw_mfree(pbuf, attr_contentlen); + + } + + } + + //Get the next P2P IE + p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen); + + } + + return status_code; + +} + +u32 process_p2p_devdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) +{ + u8 *frame_body; + u8 status, dialogToken; + struct sta_info *psta = NULL; + _adapter *padapter = pwdinfo->padapter; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 *p2p_ie; + u32 p2p_ielen = 0; + + frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + + dialogToken = frame_body[7]; + status = P2P_STATUS_FAIL_UNKNOWN_P2PGROUP; + + if ( (p2p_ie=rtw_get_p2p_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen)) ) + { + u8 groupid[ 38 ] = { 0x00 }; + u8 dev_addr[ETH_ALEN] = { 0x00 }; + u32 attr_contentlen = 0; + + if(rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen)) + { + if(_rtw_memcmp(pwdinfo->device_addr, groupid, ETH_ALEN) && + _rtw_memcmp(pwdinfo->p2p_group_ssid, groupid+ETH_ALEN, pwdinfo->p2p_group_ssid_len)) + { + attr_contentlen=0; + if(rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_ID, dev_addr, &attr_contentlen)) + { + _irqL irqL; + _list *phead, *plist; + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + phead = &pstapriv->asoc_list; + plist = get_next(phead); + + //look up sta asoc_queue + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) + { + psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + + plist = get_next(plist); + + if(psta->is_p2p_device && (psta->dev_cap&P2P_DEVCAP_CLIENT_DISCOVERABILITY) && + _rtw_memcmp(psta->dev_addr, dev_addr, ETH_ALEN)) + { + + //_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + //issue GO Discoverability Request + issue_group_disc_req(pwdinfo, psta->hwaddr); + //_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + status = P2P_STATUS_SUCCESS; + + break; + } + else + { + status = P2P_STATUS_FAIL_INFO_UNAVAILABLE; + } + + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + } + else + { + status = P2P_STATUS_FAIL_INVALID_PARAM; + } + + } + else + { + status = P2P_STATUS_FAIL_INVALID_PARAM; + } + + } + + } + + + //issue Device Discoverability Response + issue_p2p_devdisc_resp(pwdinfo, GetAddr2Ptr(pframe), status, dialogToken); + + + return (status==P2P_STATUS_SUCCESS) ? _TRUE:_FALSE; + +} + +u32 process_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) +{ + return _TRUE; +} + +u8 process_p2p_provdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len ) +{ + u8 *frame_body; + u8 *wpsie; + uint wps_ielen = 0, attr_contentlen = 0; + u16 uconfig_method = 0; + + + frame_body = (pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + + if ( (wpsie=rtw_get_wps_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &wps_ielen)) ) + { + if ( rtw_get_wps_attr_content( wpsie, wps_ielen, WPS_ATTR_CONF_METHOD , ( u8* ) &uconfig_method, &attr_contentlen) ) + { + uconfig_method = be16_to_cpu( uconfig_method ); + switch( uconfig_method ) + { + case WPS_CM_DISPLYA: + { + _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "dis", 3 ); + break; + } + case WPS_CM_LABEL: + { + _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "lab", 3 ); + break; + } + case WPS_CM_PUSH_BUTTON: + { + _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pbc", 3 ); + break; + } + case WPS_CM_KEYPAD: + { + _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pad", 3 ); + break; + } + } + issue_p2p_provision_resp( pwdinfo, GetAddr2Ptr(pframe), frame_body, uconfig_method); + } + } + DBG_871X( "[%s] config method = %s\n", __FUNCTION__, pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req ); + return _TRUE; + +} + +u8 process_p2p_provdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe) +{ + + return _TRUE; +} + +u8 rtw_p2p_get_peer_ch_list(struct wifidirect_info *pwdinfo, u8 *ch_content, u8 ch_cnt, u8 *peer_ch_list) +{ + u8 i = 0, j = 0; + u8 temp = 0; + u8 ch_no = 0; + ch_content += 3; + ch_cnt -= 3; + + while( ch_cnt > 0) + { + ch_content += 1; + ch_cnt -= 1; + temp = *ch_content; + for( i = 0 ; i < temp ; i++, j++ ) + { + peer_ch_list[j] = *( ch_content + 1 + i ); + } + ch_content += (temp + 1); + ch_cnt -= (temp + 1); + ch_no += temp ; + } + + return ch_no; +} + +u8 rtw_p2p_check_peer_oper_ch(struct mlme_ext_priv *pmlmeext, u8 ch) +{ + u8 i = 0; + + for( i = 0; i < pmlmeext->max_chan_nums; i++ ) + { + if ( pmlmeext->channel_set[ i ].ChannelNum == ch ) + { + return _SUCCESS; + } + } + + return _FAIL; +} + +u8 rtw_p2p_ch_inclusion(struct mlme_ext_priv *pmlmeext, u8 *peer_ch_list, u8 peer_ch_num, u8 *ch_list_inclusioned) +{ + int i = 0, j = 0, temp = 0; + u8 ch_no = 0; + + for( i = 0; i < peer_ch_num; i++ ) + { + for( j = temp; j < pmlmeext->max_chan_nums; j++ ) + { + if( *( peer_ch_list + i ) == pmlmeext->channel_set[ j ].ChannelNum ) + { + ch_list_inclusioned[ ch_no++ ] = *( peer_ch_list + i ); + temp = j; + break; + } + } + } + + return ch_no; +} + +u8 process_p2p_group_negotation_req( struct wifidirect_info *pwdinfo, u8 *pframe, uint len ) +{ + _adapter *padapter = pwdinfo->padapter; + u8 result = P2P_STATUS_SUCCESS; + u32 p2p_ielen = 0, wps_ielen = 0; + u8 * ies; + u32 ies_len; + u8 *p2p_ie; + u8 *wpsie; + u16 wps_devicepassword_id = 0x0000; + uint wps_devicepassword_id_len = 0; +#ifdef CONFIG_WFD +#ifdef CONFIG_TDLS + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; +#endif // CONFIG_TDLS +#endif // CONFIG_WFD +#ifdef CONFIG_CONCURRENT_MODE + _adapter *pbuddy_adapter = pwdinfo->padapter->pbuddy_adapter; + struct wifidirect_info *pbuddy_wdinfo = &pbuddy_adapter->wdinfo; + struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv; + struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; +#endif + + if ( (wpsie=rtw_get_wps_ie( pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &wps_ielen)) ) + { + // Commented by Kurt 20120113 + // If some device wants to do p2p handshake without sending prov_disc_req + // We have to get peer_req_cm from here. + if(_rtw_memcmp( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "000", 3) ) + { + rtw_get_wps_attr_content( wpsie, wps_ielen, WPS_ATTR_DEVICE_PWID, (u8*) &wps_devicepassword_id, &wps_devicepassword_id_len); + wps_devicepassword_id = be16_to_cpu( wps_devicepassword_id ); + + if ( wps_devicepassword_id == WPS_DPID_USER_SPEC ) + { + _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "dis", 3 ); + } + else if ( wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC ) + { + _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pad", 3 ); + } + else + { + _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pbc", 3 ); + } + } + } + else + { + DBG_871X( "[%s] WPS IE not Found!!\n", __FUNCTION__ ); + result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM; + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); + return( result ); + } + + ies = pframe + _PUBLIC_ACTION_IE_OFFSET_; + ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; + + p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen ); + + if ( !p2p_ie ) + { + DBG_871X( "[%s] P2P IE not Found!!\n", __FUNCTION__ ); + result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM; + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); + } + + while ( p2p_ie ) + { + u8 attr_content = 0x00; + u32 attr_contentlen = 0; + u8 ch_content[100] = { 0x00 }; + uint ch_cnt = 0; + u8 peer_ch_list[100] = { 0x00 }; + u8 peer_ch_num = 0; + u8 ch_list_inclusioned[100] = { 0x00 }; + u8 ch_num_inclusioned = 0; + u16 cap_attr; + u8 listen_ch_attr[5] = { 0x00 }; + + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_ING); + + //Check P2P Capability ATTR + if(rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8*)&cap_attr, (uint*)&attr_contentlen) ) + { + cap_attr = le16_to_cpu(cap_attr); + +#if defined(CONFIG_WFD) && defined(CONFIG_TDLS) + if(!(cap_attr & P2P_GRPCAP_INTRABSS) ) + ptdlsinfo->ap_prohibited = _TRUE; +#endif //defined(CONFIG_WFD) && defined(CONFIG_TDLS) + } + + if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT , &attr_content, &attr_contentlen) ) + { + DBG_871X( "[%s] GO Intent = %d, tie = %d\n", __FUNCTION__, attr_content >> 1, attr_content & 0x01 ); + pwdinfo->peer_intent = attr_content; // include both intent and tie breaker values. + + if ( pwdinfo->intent == ( pwdinfo->peer_intent >> 1 ) ) + { + // Try to match the tie breaker value + if ( pwdinfo->intent == P2P_MAX_INTENT ) + { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); + result = P2P_STATUS_FAIL_BOTH_GOINTENT_15; + } + else + { + if ( attr_content & 0x01 ) + { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); + } + else + { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); + } + } + } + else if ( pwdinfo->intent > ( pwdinfo->peer_intent >> 1 ) ) + { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); + } + else + { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); + } + + if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) + { + // Store the group id information. + _rtw_memcpy( pwdinfo->groupid_info.go_device_addr, pwdinfo->device_addr, ETH_ALEN ); + _rtw_memcpy( pwdinfo->groupid_info.ssid, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen ); + } + } + + if (rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, (u8 *)listen_ch_attr, (uint *) &attr_contentlen) && attr_contentlen == 5) + pwdinfo->nego_req_info.peer_ch = listen_ch_attr[4]; + + DBG_871X(FUNC_ADPT_FMT" listen channel :%u\n", FUNC_ADPT_ARG(padapter), pwdinfo->nego_req_info.peer_ch); + + attr_contentlen = 0; + if ( rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_INTENTED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen ) ) + { + if ( attr_contentlen != ETH_ALEN ) + { + _rtw_memset( pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN ); + } + } + + if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, ch_content, &ch_cnt) ) + { + peer_ch_num = rtw_p2p_get_peer_ch_list(pwdinfo, ch_content, ch_cnt, peer_ch_list); + ch_num_inclusioned = rtw_p2p_ch_inclusion(&padapter->mlmeextpriv, peer_ch_list, peer_ch_num, ch_list_inclusioned); + + if( ch_num_inclusioned == 0) + { + DBG_871X( "[%s] No common channel in channel list!\n", __FUNCTION__ ); + result = P2P_STATUS_FAIL_NO_COMMON_CH; + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); + break; + } + + if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) + { + if ( !rtw_p2p_is_channel_list_ok( pwdinfo->operating_channel, + ch_list_inclusioned, ch_num_inclusioned) ) + { +#ifdef CONFIG_CONCURRENT_MODE + if (check_buddy_fwstate(padapter, _FW_LINKED) + && padapter->registrypriv.full_ch_in_p2p_handshake == 0) + { + DBG_871X( "[%s] desired channel NOT Found!\n", __FUNCTION__ ); + result = P2P_STATUS_FAIL_NO_COMMON_CH; + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); + break; + } + else +#endif //CONFIG_CONCURRENT_MODE + { + u8 operatingch_info[5] = { 0x00 }, peer_operating_ch = 0; + attr_contentlen = 0; + + if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen) ) + { + peer_operating_ch = operatingch_info[4]; + } + + if ( rtw_p2p_is_channel_list_ok( peer_operating_ch, + ch_list_inclusioned, ch_num_inclusioned) ) + { + /** + * Change our operating channel as peer's for compatibility. + */ + pwdinfo->operating_channel = peer_operating_ch; + DBG_871X( "[%s] Change op ch to %02x as peer's\n", __FUNCTION__, pwdinfo->operating_channel); + } + else + { + // Take first channel of ch_list_inclusioned as operating channel + pwdinfo->operating_channel = ch_list_inclusioned[0]; + DBG_871X( "[%s] Change op ch to %02x\n", __FUNCTION__, pwdinfo->operating_channel); + } + } + + } + } + } + + //Get the next P2P IE + p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen); + } + + if (pwdinfo->ui_got_wps_info == P2P_NO_WPSINFO) { + result = P2P_STATUS_FAIL_INFO_UNAVAILABLE; + rtw_p2p_set_state(pwdinfo, P2P_STATE_TX_INFOR_NOREADY); + return result; + } + + #ifdef CONFIG_WFD + rtw_process_wfd_ies(padapter, pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, __func__); + #endif + + return( result ); +} + +u8 process_p2p_group_negotation_resp( struct wifidirect_info *pwdinfo, u8 *pframe, uint len ) +{ + _adapter *padapter = pwdinfo->padapter; + u8 result = P2P_STATUS_SUCCESS; + u32 p2p_ielen, wps_ielen; + u8 * ies; + u32 ies_len; + u8 * p2p_ie; +#ifdef CONFIG_WFD +#ifdef CONFIG_TDLS + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; +#endif // CONFIG_TDLS +#endif // CONFIG_WFD + + ies = pframe + _PUBLIC_ACTION_IE_OFFSET_; + ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; + + // Be able to know which one is the P2P GO and which one is P2P client. + + if ( rtw_get_wps_ie( ies, ies_len, NULL, &wps_ielen) ) + { + + } + else + { + DBG_871X( "[%s] WPS IE not Found!!\n", __FUNCTION__ ); + result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM; + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); + } + + p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen ); + if ( !p2p_ie ) + { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); + result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM; + } + else + { + + u8 attr_content = 0x00; + u32 attr_contentlen = 0; + u8 operatingch_info[5] = { 0x00 }; + uint ch_cnt = 0; + u8 ch_content[100] = { 0x00 }; + u8 groupid[ 38 ]; + u16 cap_attr; + u8 peer_ch_list[100] = { 0x00 }; + u8 peer_ch_num = 0; + u8 ch_list_inclusioned[100] = { 0x00 }; + u8 ch_num_inclusioned = 0; + + while ( p2p_ie ) // Found the P2P IE. + { + + //Check P2P Capability ATTR + if(rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8*)&cap_attr, (uint*)&attr_contentlen) ) + { + cap_attr = le16_to_cpu(cap_attr); +#ifdef CONFIG_TDLS + if(!(cap_attr & P2P_GRPCAP_INTRABSS) ) + ptdlsinfo->ap_prohibited = _TRUE; +#endif // CONFIG_TDLS + } + + rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen); + if ( attr_contentlen == 1 ) + { + DBG_871X( "[%s] Status = %d\n", __FUNCTION__, attr_content ); + if ( attr_content == P2P_STATUS_SUCCESS ) + { + // Do nothing. + } + else + { + if ( P2P_STATUS_FAIL_INFO_UNAVAILABLE == attr_content ) { + rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_INFOR_NOREADY); + } else { + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); + } + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); + result = attr_content; + break; + } + } + + // Try to get the peer's interface address + attr_contentlen = 0; + if ( rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_INTENTED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen ) ) + { + if ( attr_contentlen != ETH_ALEN ) + { + _rtw_memset( pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN ); + } + } + + // Try to get the peer's intent and tie breaker value. + attr_content = 0x00; + attr_contentlen = 0; + if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT , &attr_content, &attr_contentlen) ) + { + DBG_871X( "[%s] GO Intent = %d, tie = %d\n", __FUNCTION__, attr_content >> 1, attr_content & 0x01 ); + pwdinfo->peer_intent = attr_content; // include both intent and tie breaker values. + + if ( pwdinfo->intent == ( pwdinfo->peer_intent >> 1 ) ) + { + // Try to match the tie breaker value + if ( pwdinfo->intent == P2P_MAX_INTENT ) + { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); + result = P2P_STATUS_FAIL_BOTH_GOINTENT_15; + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); + } + else + { + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); + rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK); + if ( attr_content & 0x01 ) + { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); + } + else + { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); + } + } + } + else if ( pwdinfo->intent > ( pwdinfo->peer_intent >> 1 ) ) + { + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); + rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK); + rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); + } + else + { + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); + rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK); + rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); + } + + if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) + { + // Store the group id information. + _rtw_memcpy( pwdinfo->groupid_info.go_device_addr, pwdinfo->device_addr, ETH_ALEN ); + _rtw_memcpy( pwdinfo->groupid_info.ssid, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen ); + + } + } + + // Try to get the operation channel information + + attr_contentlen = 0; + if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen)) + { + DBG_871X( "[%s] Peer's operating channel = %d\n", __FUNCTION__, operatingch_info[4] ); + pwdinfo->peer_operating_ch = operatingch_info[4]; + } + + // Try to get the channel list information + if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, pwdinfo->channel_list_attr, &pwdinfo->channel_list_attr_len ) ) + { + DBG_871X( "[%s] channel list attribute found, len = %d\n", __FUNCTION__, pwdinfo->channel_list_attr_len ); + + peer_ch_num = rtw_p2p_get_peer_ch_list(pwdinfo, pwdinfo->channel_list_attr, pwdinfo->channel_list_attr_len, peer_ch_list); + ch_num_inclusioned = rtw_p2p_ch_inclusion(&padapter->mlmeextpriv, peer_ch_list, peer_ch_num, ch_list_inclusioned); + + if( ch_num_inclusioned == 0) + { + DBG_871X( "[%s] No common channel in channel list!\n", __FUNCTION__ ); + result = P2P_STATUS_FAIL_NO_COMMON_CH; + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); + break; + } + + if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) + { + if ( !rtw_p2p_is_channel_list_ok( pwdinfo->operating_channel, + ch_list_inclusioned, ch_num_inclusioned) ) + { +#ifdef CONFIG_CONCURRENT_MODE + if (check_buddy_fwstate(padapter, _FW_LINKED) + && padapter->registrypriv.full_ch_in_p2p_handshake == 0) + { + DBG_871X( "[%s] desired channel NOT Found!\n", __FUNCTION__ ); + result = P2P_STATUS_FAIL_NO_COMMON_CH; + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); + break; + } + else +#endif //CONFIG_CONCURRENT_MODE + { + u8 operatingch_info[5] = { 0x00 }, peer_operating_ch = 0; + attr_contentlen = 0; + + if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen) ) + { + peer_operating_ch = operatingch_info[4]; + } + + if ( rtw_p2p_is_channel_list_ok( peer_operating_ch, + ch_list_inclusioned, ch_num_inclusioned) ) + { + /** + * Change our operating channel as peer's for compatibility. + */ + pwdinfo->operating_channel = peer_operating_ch; + DBG_871X( "[%s] Change op ch to %02x as peer's\n", __FUNCTION__, pwdinfo->operating_channel); + } + else + { + // Take first channel of ch_list_inclusioned as operating channel + pwdinfo->operating_channel = ch_list_inclusioned[0]; + DBG_871X( "[%s] Change op ch to %02x\n", __FUNCTION__, pwdinfo->operating_channel); + } + } + + } + } + + } + else + { + DBG_871X( "[%s] channel list attribute not found!\n", __FUNCTION__); + } + + // Try to get the group id information if peer is GO + attr_contentlen = 0; + _rtw_memset( groupid, 0x00, 38 ); + if ( rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen) ) + { + _rtw_memcpy( pwdinfo->groupid_info.go_device_addr, &groupid[0], ETH_ALEN ); + _rtw_memcpy( pwdinfo->groupid_info.ssid, &groupid[6], attr_contentlen - ETH_ALEN ); + } + + //Get the next P2P IE + p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen); + } + + } + + #ifdef CONFIG_WFD + rtw_process_wfd_ies(padapter, pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, __func__); + #endif + + return( result ); + +} + +u8 process_p2p_group_negotation_confirm( struct wifidirect_info *pwdinfo, u8 *pframe, uint len ) +{ + _adapter *padapter = pwdinfo->padapter; + u8 * ies; + u32 ies_len; + u8 * p2p_ie; + u32 p2p_ielen = 0; + u8 result = P2P_STATUS_SUCCESS; + ies = pframe + _PUBLIC_ACTION_IE_OFFSET_; + ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; + + p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen ); + while ( p2p_ie ) // Found the P2P IE. + { + u8 attr_content = 0x00, operatingch_info[5] = { 0x00 }; + u8 groupid[ 38 ] = { 0x00 }; + u32 attr_contentlen = 0; + + pwdinfo->negotiation_dialog_token = 1; + rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen); + if ( attr_contentlen == 1 ) + { + DBG_871X( "[%s] Status = %d\n", __FUNCTION__, attr_content ); + result = attr_content; + + if ( attr_content == P2P_STATUS_SUCCESS ) + { + u8 bcancelled = 0; + + _cancel_timer( &pwdinfo->restore_p2p_state_timer, &bcancelled ); + + // Commented by Albert 20100911 + // Todo: Need to handle the case which both Intents are the same. + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); + rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK); + if ( ( pwdinfo->intent ) > ( pwdinfo->peer_intent >> 1 ) ) + { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); + } + else if ( ( pwdinfo->intent ) < ( pwdinfo->peer_intent >> 1 ) ) + { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); + } + else + { + // Have to compare the Tie Breaker + if ( pwdinfo->peer_intent & 0x01 ) + { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); + } + else + { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); + } + } + +#ifdef CONFIG_CONCURRENT_MODE + if (check_buddy_fwstate(padapter , _FW_LINKED) + && padapter->registrypriv.full_ch_in_p2p_handshake == 0) + { + // Switch back to the AP channel soon. + _set_timer( &pwdinfo->ap_p2p_switch_timer, 100 ); + } +#endif + } + else + { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); + break; + } + } + + // Try to get the group id information + attr_contentlen = 0; + _rtw_memset( groupid, 0x00, 38 ); + if ( rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen) ) + { + DBG_871X( "[%s] Ssid = %s, ssidlen = %zu\n", __FUNCTION__, &groupid[ETH_ALEN], strlen(&groupid[ETH_ALEN]) ); + _rtw_memcpy( pwdinfo->groupid_info.go_device_addr, &groupid[0], ETH_ALEN ); + _rtw_memcpy( pwdinfo->groupid_info.ssid, &groupid[6], attr_contentlen - ETH_ALEN ); + } + + attr_contentlen = 0; + if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen) ) + { + DBG_871X( "[%s] Peer's operating channel = %d\n", __FUNCTION__, operatingch_info[4] ); + pwdinfo->peer_operating_ch = operatingch_info[4]; + } + + //Get the next P2P IE + p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen); + + } + + return( result ); +} + +u8 process_p2p_presence_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) +{ + u8 *frame_body; + u8 dialogToken=0; + u8 status = P2P_STATUS_SUCCESS; + + frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); + + dialogToken = frame_body[6]; + + //todo: check NoA attribute + + issue_p2p_presence_resp(pwdinfo, GetAddr2Ptr(pframe), status, dialogToken); + + return _TRUE; +} + +void find_phase_handler( _adapter* padapter ) +{ + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + NDIS_802_11_SSID ssid; + _irqL irqL; + u8 _status = 0; + +_func_enter_; + + _rtw_memset((unsigned char*)&ssid, 0, sizeof(NDIS_802_11_SSID)); + _rtw_memcpy(ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN ); + ssid.SsidLength = P2P_WILDCARD_SSID_LEN; + + rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH); + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + _status = rtw_sitesurvey_cmd(padapter, &ssid, 1, NULL, 0); + _exit_critical_bh(&pmlmepriv->lock, &irqL); + + +_func_exit_; +} + +void p2p_concurrent_handler( _adapter* padapter ); + +void restore_p2p_state_handler( _adapter* padapter ) +{ + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + +_func_enter_; + + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL)) + { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); + } + +#ifdef CONFIG_CONCURRENT_MODE + if ( check_buddy_fwstate(padapter, _FW_LINKED ) ) + { + _adapter *pbuddy_adapter = padapter->pbuddy_adapter; + struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv; + struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; + + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_RSP)) + { + set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode); + + issue_nulldata(pbuddy_adapter, NULL, 0, 3, 500); + } + } +#endif + + rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); + + if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)) + { +#ifdef CONFIG_CONCURRENT_MODE + p2p_concurrent_handler( padapter ); +#else + // In the P2P client mode, the driver should not switch back to its listen channel + // because this P2P client should stay at the operating channel of P2P GO. + set_channel_bwmode( padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); +#endif + } +_func_exit_; +} + +void pre_tx_invitereq_handler( _adapter* padapter ) +{ + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + u8 val8 = 1; +_func_enter_; + + set_channel_bwmode(padapter, pwdinfo->invitereq_info.peer_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + issue_probereq_p2p(padapter, NULL); + _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); + +_func_exit_; +} + +void pre_tx_provdisc_handler( _adapter* padapter ) +{ + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + u8 val8 = 1; +_func_enter_; + + set_channel_bwmode(padapter, pwdinfo->tx_prov_disc_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + issue_probereq_p2p(padapter, NULL); + _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); + +_func_exit_; +} + +void pre_tx_negoreq_handler( _adapter* padapter ) +{ + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + u8 val8 = 1; +_func_enter_; + + set_channel_bwmode(padapter, pwdinfo->nego_req_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + issue_probereq_p2p(padapter , NULL); + /* WIN Phone only accept unicast probe request when nego back */ + issue_probereq_p2p(padapter , pwdinfo->nego_req_info.peerDevAddr); + _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); + +_func_exit_; +} + +#ifdef CONFIG_CONCURRENT_MODE +void p2p_concurrent_handler( _adapter* padapter ) +{ + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + //_adapter *pbuddy_adapter = padapter->pbuddy_adapter; + //struct wifidirect_info *pbuddy_wdinfo = &pbuddy_adapter->wdinfo; + //struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv; + //struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; + u8 val8; +_func_enter_; + + if ( check_buddy_fwstate(padapter, _FW_LINKED ) ) + { + PADAPTER pbuddy_adapter = padapter->pbuddy_adapter; + struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; + + pwdinfo->operating_channel = pbuddy_mlmeext->cur_channel; + + if( pwdinfo->driver_interface == DRIVER_CFG80211 ) + { + DBG_871X("%s, switch ch back to buddy's cur_channel=%d\n", __func__, pbuddy_mlmeext->cur_channel); + + set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode); + + if (check_buddy_fwstate(padapter, WIFI_FW_STATION_STATE)) + issue_nulldata(pbuddy_adapter, NULL, 0, 3, 500); + } + else if( pwdinfo->driver_interface == DRIVER_WEXT ) + { + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) + { + // Now, the driver stays on the AP's channel. + // If the pwdinfo->ext_listen_period = 0, that means the P2P listen state is not available on listen channel. + if ( pwdinfo->ext_listen_period > 0 ) + { + DBG_8192C( "[%s] P2P_STATE_IDLE, ext_listen_period = %d\n", __FUNCTION__, pwdinfo->ext_listen_period ); + + if ( pbuddy_mlmeext->cur_channel != pwdinfo->listen_channel ) + { + // Will switch to listen channel so that need to send the NULL data with PW bit to AP. + issue_nulldata(pbuddy_adapter, NULL, 1, 3, 500); + set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + } + + rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN); + if(!check_buddy_mlmeinfo_state(padapter, WIFI_FW_AP_STATE) && + ((pmlmeinfo->state&0x03) != WIFI_FW_AP_STATE)) + { + val8 = 1; + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + } + // Todo: To check the value of pwdinfo->ext_listen_period is equal to 0 or not. + _set_timer( &pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_period ); + } + } + else if ( rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN) || + rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL) || + ( rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) && pwdinfo->nego_req_info.benable == _FALSE ) || + rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ) ) + { + // Now, the driver is in the listen state of P2P mode. + DBG_8192C( "[%s] P2P_STATE_IDLE, ext_listen_interval = %d\n", __FUNCTION__, pwdinfo->ext_listen_interval ); + + // Commented by Albert 2012/11/01 + // If the AP's channel is the same as the listen channel, we should still be in the listen state + // Other P2P device is still able to find this device out even this device is in the AP's channel. + // So, configure this device to be able to receive the probe request frame and set it to listen state. + if ( pbuddy_mlmeext->cur_channel != pwdinfo->listen_channel ) + { + set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode); + if (!check_buddy_mlmeinfo_state(padapter, WIFI_FW_AP_STATE) && ((pmlmeinfo->state&0x03) != WIFI_FW_AP_STATE)) + { + val8 = 0; + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + } + rtw_p2p_set_state(pwdinfo, P2P_STATE_IDLE); + issue_nulldata(pbuddy_adapter, NULL, 0, 3, 500); + } + + // Todo: To check the value of pwdinfo->ext_listen_interval is equal to 0 or not. + _set_timer( &pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_interval ); + } + else if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_OK)) + { + // The driver had finished the P2P handshake successfully. + val8 = 0; + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode); + issue_nulldata(pbuddy_adapter, NULL, 0, 3, 500); + } + else if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) + { + val8 = 1; + set_channel_bwmode(padapter, pwdinfo->tx_prov_disc_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + issue_probereq_p2p(padapter, NULL); + _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); + } + else if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING) && pwdinfo->nego_req_info.benable == _TRUE) + { + val8 = 1; + set_channel_bwmode(padapter, pwdinfo->nego_req_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + issue_probereq_p2p(padapter, NULL); + _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); + } + else if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_INVITE_REQ ) && pwdinfo->invitereq_info.benable == _TRUE) + { + /* + val8 = 1; + set_channel_bwmode(padapter, , HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); + issue_probereq_p2p(padapter, NULL); + _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); + */ + } + } + } + else + { + /* In p2p+softap. When in P2P_STATE_GONEGO_OK, not back to listen channel.*/ + if (!rtw_p2p_chk_state(pwdinfo , P2P_STATE_GONEGO_OK) || padapter->registrypriv.full_ch_in_p2p_handshake == 0) + set_channel_bwmode(padapter , pwdinfo->listen_channel , HAL_PRIME_CHNL_OFFSET_DONT_CARE , CHANNEL_WIDTH_20); + else + DBG_871X("%s, buddy not linked, go nego ok, not back to listen channel\n", __func__); + } + +_func_exit_; +} +#endif + +#ifdef CONFIG_IOCTL_CFG80211 +static void ro_ch_handler(_adapter *padapter) +{ + struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo; + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + u8 ch, bw, offset; +_func_enter_; + + if (rtw_get_ch_setting_union(padapter, &ch, &bw, &offset) != 0) { + if (0) + DBG_871X(FUNC_ADPT_FMT" back to linked/linking union - ch:%u, bw:%u, offset:%u\n", + FUNC_ADPT_ARG(padapter), ch, bw, offset); + } + else if (adapter_wdev_data(padapter)->p2p_enabled && pwdinfo->listen_channel) { + ch = pwdinfo->listen_channel; + bw = CHANNEL_WIDTH_20; + offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + if (0) + DBG_871X(FUNC_ADPT_FMT" back to listen ch - ch:%u, bw:%u, offset:%u\n", + FUNC_ADPT_ARG(padapter), ch, bw, offset); + } + else { + ch = pcfg80211_wdinfo->restore_channel; + bw = CHANNEL_WIDTH_20; + offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + if (0) + DBG_871X(FUNC_ADPT_FMT" back to restore ch - ch:%u, bw:%u, offset:%u\n", + FUNC_ADPT_ARG(padapter), ch, bw, offset); + } + + set_channel_bwmode(padapter, ch, offset, bw); + + rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); +#ifdef CONFIG_DEBUG_CFG80211 + DBG_871X("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo)); +#endif + + pcfg80211_wdinfo->is_ro_ch = _FALSE; + pcfg80211_wdinfo->last_ro_ch_time = rtw_get_current_time(); + + DBG_871X("cfg80211_remain_on_channel_expired cookie:0x%llx, ch=%d, bw=%d, offset=%d\n" + , pcfg80211_wdinfo->remain_on_ch_cookie + , rtw_get_oper_ch(padapter), rtw_get_oper_bw(padapter), rtw_get_oper_choffset(padapter)); + + rtw_cfg80211_remain_on_channel_expired(padapter, + pcfg80211_wdinfo->remain_on_ch_cookie, + &pcfg80211_wdinfo->remain_on_ch_channel, + pcfg80211_wdinfo->remain_on_ch_type, GFP_KERNEL); + +_func_exit_; +} + +static void ro_ch_timer_process (void *FunctionContext) +{ + _adapter *adapter = (_adapter *)FunctionContext; + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter); + + //printk("%s \n", __FUNCTION__); + +#ifdef CONFIG_CONCURRENT_MODE + ATOMIC_SET(&pwdev_priv->ro_ch_to, 1); +#endif + + p2p_protocol_wk_cmd( adapter, P2P_RO_CH_WK); +} + +static void rtw_change_p2pie_op_ch(_adapter *padapter, const u8 *frame_body, u32 len, u8 ch) +{ + u8 *ies, *p2p_ie; + u32 ies_len, p2p_ielen; + PADAPTER pbuddy_adapter = padapter->pbuddy_adapter; + struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; + + ies = (u8*)(frame_body + _PUBLIC_ACTION_IE_OFFSET_); + ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; + + p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen ); + + while ( p2p_ie ) { + u32 attr_contentlen = 0; + u8 *pattr = NULL; + + //Check P2P_ATTR_OPERATING_CH + attr_contentlen = 0; + pattr = NULL; + if((pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, (uint*)&attr_contentlen))!=NULL) + { + *(pattr+4) = ch; + } + + //Get the next P2P IE + p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen); + } +} + +static void rtw_change_p2pie_ch_list(_adapter *padapter, const u8 *frame_body, u32 len, u8 ch) +{ + u8 *ies, *p2p_ie; + u32 ies_len, p2p_ielen; + PADAPTER pbuddy_adapter = padapter->pbuddy_adapter; + struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; + + ies = (u8*)(frame_body + _PUBLIC_ACTION_IE_OFFSET_); + ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; + + p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen ); + + while (p2p_ie) { + u32 attr_contentlen = 0; + u8 *pattr = NULL; + + //Check P2P_ATTR_CH_LIST + if ((pattr=rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, (uint*)&attr_contentlen))!=NULL) { + int i; + u32 num_of_ch; + u8 *pattr_temp = pattr + 3 ; + + attr_contentlen -= 3; + + while (attr_contentlen>0) { + num_of_ch = *(pattr_temp+1); + + for(i=0; ipbuddy_adapter; + struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; + u8 buddy_ch = pbuddy_mlmeext->cur_channel; + + ies = (u8*)(frame_body + _PUBLIC_ACTION_IE_OFFSET_); + ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; + + p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen ); + + while (p2p_ie) { + u32 attr_contentlen = 0; + u8 *pattr = NULL; + + //Check P2P_ATTR_CH_LIST + if ((pattr=rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, (uint*)&attr_contentlen))!=NULL) { + int i; + u32 num_of_ch; + u8 *pattr_temp = pattr + 3 ; + + attr_contentlen -= 3; + + while (attr_contentlen>0) { + num_of_ch = *(pattr_temp+1); + + for(i=0; ipbuddy_adapter; + struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; + u8 buddy_ch = pbuddy_mlmeext->cur_channel; + + ies = (u8*)(frame_body + _PUBLIC_ACTION_IE_OFFSET_); + ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; + + p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen ); + + while (p2p_ie) { + u32 attr_contentlen = 0; + u8 *pattr = NULL; + + //Check P2P_ATTR_OPERATING_CH + attr_contentlen = 0; + pattr = NULL; + if((pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, (uint*)&attr_contentlen))!=NULL) { + if (*(pattr+4) == buddy_ch) { + DBG_871X(FUNC_ADPT_FMT" op_ch fit buddy_ch:%u\n", FUNC_ADPT_ARG(padapter), buddy_ch); + fit = _TRUE; + break; + } + } + + //Get the next P2P IE + p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen); + } +#endif + return fit; +} + +static void rtw_cfg80211_adjust_p2pie_channel(_adapter *padapter, const u8 *frame_body, u32 len) +{ +#ifdef CONFIG_CONCURRENT_MODE + u8 *ies, *p2p_ie; + u32 ies_len, p2p_ielen; + PADAPTER pbuddy_adapter = padapter->pbuddy_adapter; + struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; + + ies = (u8*)(frame_body + _PUBLIC_ACTION_IE_OFFSET_); + ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; + + p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen ); + + while ( p2p_ie ) + { + u32 attr_contentlen = 0; + u8 *pattr = NULL; + + //Check P2P_ATTR_CH_LIST + if((pattr=rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, (uint*)&attr_contentlen))!=NULL) + { + int i; + u32 num_of_ch; + u8 *pattr_temp = pattr + 3 ; + + attr_contentlen -= 3; + + while(attr_contentlen>0) + { + num_of_ch = *(pattr_temp+1); + + for(i=0; icur_channel;//forcing to the same channel + + pattr_temp += (2+num_of_ch); + attr_contentlen -= (2+num_of_ch); + } + } + + //Check P2P_ATTR_OPERATING_CH + attr_contentlen = 0; + pattr = NULL; + if((pattr = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, (uint*)&attr_contentlen))!=NULL) + { + *(pattr+4) = pbuddy_mlmeext->cur_channel;//forcing to the same channel + } + + //Get the next P2P IE + p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen); + + } + +#endif +} + +#ifdef CONFIG_WFD +u32 rtw_xframe_build_wfd_ie(struct xmit_frame *xframe) +{ + _adapter *adapter = xframe->padapter; + struct wifidirect_info *wdinfo = &adapter->wdinfo; + u8 *frame = xframe->buf_addr + TXDESC_OFFSET; + u8 *frame_body = frame + sizeof(struct rtw_ieee80211_hdr_3addr); + u8 *frame_tail = frame + xframe->attrib.pktlen; + u8 category, action, OUI_Subtype, dialogToken = 0; + u32 wfdielen = 0; + + category = frame_body[0]; + if (category == RTW_WLAN_CATEGORY_PUBLIC) { + action = frame_body[1]; + if (action == ACT_PUBLIC_VENDOR + && _rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE + ) { + OUI_Subtype = frame_body[6]; + dialogToken = frame_body[7]; + + switch (OUI_Subtype) { + case P2P_GO_NEGO_REQ: + wfdielen = build_nego_req_wfd_ie(wdinfo, frame_tail); + break; + case P2P_GO_NEGO_RESP: + wfdielen = build_nego_resp_wfd_ie(wdinfo, frame_tail); + break; + case P2P_GO_NEGO_CONF: + wfdielen = build_nego_confirm_wfd_ie(wdinfo, frame_tail); + break; + case P2P_INVIT_REQ: + wfdielen = build_invitation_req_wfd_ie(wdinfo, frame_tail); + break; + case P2P_INVIT_RESP: + wfdielen = build_invitation_resp_wfd_ie(wdinfo, frame_tail); + break; + case P2P_PROVISION_DISC_REQ: + wfdielen = build_provdisc_req_wfd_ie(wdinfo, frame_tail); + break; + case P2P_PROVISION_DISC_RESP: + wfdielen = build_provdisc_resp_wfd_ie(wdinfo, frame_tail); + break; + case P2P_DEVDISC_REQ: + case P2P_DEVDISC_RESP: + default: + break; + } + + } + } else if (category == RTW_WLAN_CATEGORY_P2P) { + OUI_Subtype = frame_body[5]; + dialogToken = frame_body[6]; + + #ifdef CONFIG_DEBUG_CFG80211 + DBG_871X("ACTION_CATEGORY_P2P: OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n" + , cpu_to_be32(*((u32 *)(frame_body + 1))), OUI_Subtype, dialogToken); + #endif + + switch (OUI_Subtype) { + case P2P_NOTICE_OF_ABSENCE: + break; + case P2P_PRESENCE_REQUEST: + break; + case P2P_PRESENCE_RESPONSE: + break; + case P2P_GO_DISC_REQUEST: + break; + default: + break; + } + } else { + DBG_871X("%s, action frame category=%d\n", __func__, category); + } + + xframe->attrib.pktlen += wfdielen; + + return wfdielen; +} +#endif /* CONFIG_WFD */ + +bool rtw_xframe_del_wfd_ie(struct xmit_frame *xframe) +{ +#define DBG_XFRAME_DEL_WFD_IE 0 + + _adapter *adapter = xframe->padapter; + u8 *frame = xframe->buf_addr + TXDESC_OFFSET; + u8 *frame_body = frame + sizeof(struct rtw_ieee80211_hdr_3addr); + u8 *frame_tail = frame + xframe->attrib.pktlen; + u8 category, action, OUI_Subtype; + u8 *ies = NULL; + uint ies_len_ori = 0; + uint ies_len = 0; + + category = frame_body[0]; + if (category == RTW_WLAN_CATEGORY_PUBLIC) { + action = frame_body[1]; + if (action == ACT_PUBLIC_VENDOR + && _rtw_memcmp(frame_body + 2, P2P_OUI, 4) == _TRUE + ) { + OUI_Subtype = frame_body[6]; + + switch (OUI_Subtype) { + case P2P_GO_NEGO_REQ: + case P2P_GO_NEGO_RESP: + case P2P_GO_NEGO_CONF: + case P2P_INVIT_REQ: + case P2P_INVIT_RESP: + case P2P_PROVISION_DISC_REQ: + case P2P_PROVISION_DISC_RESP: + ies = frame_body + 8; + ies_len_ori = frame_tail - (frame_body + 8); + break; + } + } + } + + if (ies && ies_len_ori) { + ies_len = rtw_del_wfd_ie(ies, ies_len_ori, DBG_XFRAME_DEL_WFD_IE ? __func__ : NULL); + xframe->attrib.pktlen -= (ies_len_ori - ies_len); + } + + return ies_len_ori != ies_len; +} + +/* +* rtw_xframe_chk_wfd_ie - +* +*/ +void rtw_xframe_chk_wfd_ie(struct xmit_frame *xframe) +{ + _adapter *adapter = xframe->padapter; + u8 *frame = xframe->buf_addr + TXDESC_OFFSET; + u8 *frame_body = frame + sizeof(struct rtw_ieee80211_hdr_3addr); + u8 *frame_tail = frame + xframe->attrib.pktlen; + + struct wifidirect_info *wdinfo = &adapter->wdinfo; + struct mlme_priv *mlme = &adapter->mlmepriv; + u8 build = 0; + u8 del = 0; + + if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) + del = 1; + +#ifdef CONFIG_IOCTL_CFG80211 + if (_TRUE == wdinfo->wfd_info->wfd_enable) +#endif + del = build = 1; + + if (del) + rtw_xframe_del_wfd_ie(xframe); + +#ifdef CONFIG_WFD + if (build) + rtw_xframe_build_wfd_ie(xframe); +#endif +} + +u8 *dump_p2p_attr_ch_list(u8 *p2p_ie, uint p2p_ielen, u8 *buf, u32 buf_len) +{ + uint attr_contentlen = 0; + u8 *pattr = NULL; + int w_sz = 0; + u8 ch_cnt = 0; + u8 ch_list[40]; + bool continuous = _FALSE; + + if ((pattr=rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, NULL, &attr_contentlen))!=NULL) { + int i, j; + u32 num_of_ch; + u8 *pattr_temp = pattr + 3 ; + + attr_contentlen -= 3; + + _rtw_memset(ch_list, 0, 40); + + while (attr_contentlen>0) { + num_of_ch = *(pattr_temp+1); + + for(i=0; i=ch_cnt) + ch_list[ch_cnt++] = *(pattr_temp+2+i); + + } + + pattr_temp += (2+num_of_ch); + attr_contentlen -= (2+num_of_ch); + } + + for (j=0;j>1 == resp >>1) + return req&0x01 ? _TRUE : _FALSE; + else if (req>>1 > resp>>1) + return _TRUE; + else + return _FALSE; +} + +int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) +{ + int is_p2p_frame = (-1); + unsigned char *frame_body; + u8 category, action, OUI_Subtype, dialogToken=0; + u8 *p2p_ie = NULL; + uint p2p_ielen = 0; + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); + int status = -1; + u8 ch_list_buf[128] = {'\0'}; + int op_ch = -1; + int listen_ch = -1; + u8 intent = 0; + + frame_body = (unsigned char *)(buf + sizeof(struct rtw_ieee80211_hdr_3addr)); + category = frame_body[0]; + //just for check + if(category == RTW_WLAN_CATEGORY_PUBLIC) + { + action = frame_body[1]; + if (action == ACT_PUBLIC_VENDOR + && _rtw_memcmp(frame_body+2, P2P_OUI, 4) == _TRUE + ) + { + OUI_Subtype = frame_body[6]; + dialogToken = frame_body[7]; + is_p2p_frame = OUI_Subtype; + #ifdef CONFIG_DEBUG_CFG80211 + DBG_871X("ACTION_CATEGORY_PUBLIC: ACT_PUBLIC_VENDOR, OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n", + cpu_to_be32( *( ( u32* ) ( frame_body + 2 ) ) ), OUI_Subtype, dialogToken); + #endif + + p2p_ie = rtw_get_p2p_ie( + (u8 *)buf+sizeof(struct rtw_ieee80211_hdr_3addr)+_PUBLIC_ACTION_IE_OFFSET_, + len-sizeof(struct rtw_ieee80211_hdr_3addr)-_PUBLIC_ACTION_IE_OFFSET_, + NULL, &p2p_ielen); + + switch( OUI_Subtype )//OUI Subtype + { + u8 *cont; + uint cont_len; + case P2P_GO_NEGO_REQ: + { + struct rtw_wdev_nego_info* nego_info = &pwdev_priv->nego_info; + + if (tx) { + #ifdef CONFIG_DRV_ISSUE_PROV_REQ // IOT FOR S2 + if(pwdev_priv->provdisc_req_issued == _FALSE) + rtw_cfg80211_issue_p2p_provision_request(padapter, buf, len); + #endif //CONFIG_DRV_ISSUE_PROV_REQ + + //pwdev_priv->provdisc_req_issued = _FALSE; + + #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) + if (check_buddy_fwstate(padapter , _FW_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) + rtw_cfg80211_adjust_p2pie_channel(padapter , frame_body , len-sizeof(struct rtw_ieee80211_hdr_3addr)); + #endif + } + + if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len))) + op_ch = *(cont+4); + if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, NULL, &cont_len))) + listen_ch = *(cont+4); + if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT, NULL, &cont_len))) + intent = *cont; + + if (nego_info->token != dialogToken) + rtw_wdev_nego_info_init(nego_info); + + _rtw_memcpy(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : GetAddr2Ptr(buf), ETH_ALEN); + nego_info->active = tx ? 1 : 0; + nego_info->token = dialogToken; + nego_info->req_op_ch = op_ch; + nego_info->req_listen_ch = listen_ch; + nego_info->req_intent = intent; + nego_info->state = 0; + + dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128); + DBG_871X("RTW_%s:P2P_GO_NEGO_REQ, dialogToken=%d, intent:%u%s, listen_ch:%d, op_ch:%d, ch_list:%s, full_ch_in_p2p_handshake:%d\n" , + (tx == _TRUE)?"Tx":"Rx" , dialogToken , (intent>>1) , intent&0x1 ? "+" : "-" , listen_ch , op_ch , ch_list_buf , padapter->registrypriv.full_ch_in_p2p_handshake); + + if (!tx) { + #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) + if (check_buddy_fwstate(padapter, _FW_LINKED) + && rtw_chk_p2pie_ch_list_with_buddy(padapter , frame_body , len-sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE + && padapter->registrypriv.full_ch_in_p2p_handshake == 0) + { + DBG_871X(FUNC_ADPT_FMT" ch_list has no intersect with buddy\n", FUNC_ADPT_ARG(padapter)); + rtw_change_p2pie_ch_list(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr), 0); + } + #endif + } + + break; + } + case P2P_GO_NEGO_RESP: + { + struct rtw_wdev_nego_info* nego_info = &pwdev_priv->nego_info; + + if (tx) { + #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) + if (check_buddy_fwstate(padapter , _FW_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) + rtw_cfg80211_adjust_p2pie_channel(padapter , frame_body , len-sizeof(struct rtw_ieee80211_hdr_3addr)); + #endif + } + + if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len))) + op_ch = *(cont+4); + if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT, NULL, &cont_len))) + intent = *cont; + if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len))) + status = *cont; + + if (nego_info->token == dialogToken && nego_info->state == 0 + && _rtw_memcmp(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : GetAddr2Ptr(buf), ETH_ALEN) == _TRUE + ) { + nego_info->status = (status==-1) ? 0xff : status; + nego_info->rsp_op_ch= op_ch; + nego_info->rsp_intent = intent; + nego_info->state = 1; + if (status != 0) + nego_info->token = 0; /* init */ + } + + dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128); + DBG_871X("RTW_%s:P2P_GO_NEGO_RESP, dialogToken=%d, intent:%u%s, status:%d, op_ch:%d, ch_list:%s\n", + (tx==_TRUE)?"Tx":"Rx", dialogToken, (intent>>1), intent&0x1 ? "+" : "-", status, op_ch, ch_list_buf); + + if (!tx) { + pwdev_priv->provdisc_req_issued = _FALSE; + #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) + if (check_buddy_fwstate(padapter, _FW_LINKED) + && rtw_chk_p2pie_ch_list_with_buddy(padapter , frame_body , len-sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE + && padapter->registrypriv.full_ch_in_p2p_handshake == 0) + { + DBG_871X(FUNC_ADPT_FMT" ch_list has no intersect with buddy\n", FUNC_ADPT_ARG(padapter)); + rtw_change_p2pie_ch_list(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr), 0); + } + #endif + } + + break; + } + case P2P_GO_NEGO_CONF: + { + struct rtw_wdev_nego_info* nego_info = &pwdev_priv->nego_info; + bool is_go = _FALSE; + + if (tx) { + #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) + if (check_buddy_fwstate(padapter, _FW_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) + rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr)); + #endif + } + + if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len))) + op_ch = *(cont+4); + if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len))) + status = *cont; + + if (nego_info->token == dialogToken && nego_info->state == 1 + && _rtw_memcmp(nego_info->peer_mac, tx ? GetAddr1Ptr(buf) : GetAddr2Ptr(buf), ETH_ALEN) == _TRUE + ) { + nego_info->status = (status==-1) ? 0xff : status; + nego_info->conf_op_ch = (op_ch==-1) ? 0 : op_ch; + nego_info->state = 2; + + if (status == 0) { + if (rtw_p2p_nego_intent_compare(nego_info->req_intent, nego_info->rsp_intent) ^ !tx) + is_go = _TRUE; + } + + nego_info->token = 0; /* init */ + } + + dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128); + DBG_871X("RTW_%s:P2P_GO_NEGO_CONF, dialogToken=%d, status:%d, op_ch:%d, ch_list:%s\n", + (tx==_TRUE)?"Tx":"Rx", dialogToken, status, op_ch, ch_list_buf); + + if (!tx) { + } + + break; + } + case P2P_INVIT_REQ: + { + struct rtw_wdev_invit_info* invit_info = &pwdev_priv->invit_info; + int flags = -1; + + if (tx) { + #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) + if (check_buddy_fwstate(padapter, _FW_LINKED) + && padapter->registrypriv.full_ch_in_p2p_handshake == 0) + rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr)); + #endif + } + + if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_INVITATION_FLAGS, NULL, &cont_len))) + flags = *cont; + if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len))) + op_ch = *(cont+4); + + if (invit_info->token != dialogToken) + rtw_wdev_invit_info_init(invit_info); + + _rtw_memcpy(invit_info->peer_mac, tx ? GetAddr1Ptr(buf) : GetAddr2Ptr(buf), ETH_ALEN); + invit_info->active = tx ? 1 : 0; + invit_info->token = dialogToken; + invit_info->flags = (flags==-1) ? 0x0 : flags; + invit_info->req_op_ch= op_ch; + invit_info->state = 0; + + dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128); + DBG_871X("RTW_%s:P2P_INVIT_REQ, dialogToken=%d, flags:0x%02x, op_ch:%d, ch_list:%s\n", + (tx==_TRUE)?"Tx":"Rx", dialogToken, flags, op_ch, ch_list_buf); + + if (!tx) { + #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) + if (check_buddy_fwstate(padapter , _FW_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) { + if (op_ch != -1 && rtw_chk_p2pie_op_ch_with_buddy(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE) { + DBG_871X(FUNC_ADPT_FMT" op_ch:%u has no intersect with buddy\n", FUNC_ADPT_ARG(padapter), op_ch); + rtw_change_p2pie_ch_list(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr), 0); + } else if (rtw_chk_p2pie_ch_list_with_buddy(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr)) == _FALSE) { + DBG_871X(FUNC_ADPT_FMT" ch_list has no intersect with buddy\n", FUNC_ADPT_ARG(padapter)); + rtw_change_p2pie_ch_list(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr), 0); + } + } + #endif + } + + break; + } + case P2P_INVIT_RESP: + { + struct rtw_wdev_invit_info* invit_info = &pwdev_priv->invit_info; + + if (tx) { + #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT) + if (check_buddy_fwstate(padapter , _FW_LINKED) && padapter->registrypriv.full_ch_in_p2p_handshake == 0) + rtw_cfg80211_adjust_p2pie_channel(padapter, frame_body, len-sizeof(struct rtw_ieee80211_hdr_3addr)); + #endif + } + + if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len))) + { +#ifdef CONFIG_P2P_INVITE_IOT + if(tx && *cont==7) + { + DBG_871X("TX_P2P_INVITE_RESP, status is no common channel, change to unknown group\n"); + *cont = 8; //unknow group status + } +#endif //CONFIG_P2P_INVITE_IOT + status = *cont; + } + if ((cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, NULL, &cont_len))) + op_ch = *(cont+4); + + if (invit_info->token == dialogToken && invit_info->state == 0 + && _rtw_memcmp(invit_info->peer_mac, tx ? GetAddr1Ptr(buf) : GetAddr2Ptr(buf), ETH_ALEN) == _TRUE + ) { + invit_info->status = (status==-1) ? 0xff : status; + invit_info->rsp_op_ch= op_ch; + invit_info->state = 1; + invit_info->token = 0; /* init */ + } + + dump_p2p_attr_ch_list(p2p_ie, p2p_ielen, ch_list_buf, 128); + DBG_871X("RTW_%s:P2P_INVIT_RESP, dialogToken=%d, status:%d, op_ch:%d, ch_list:%s\n", + (tx==_TRUE)?"Tx":"Rx", dialogToken, status, op_ch, ch_list_buf); + + if (!tx) { + } + + break; + } + case P2P_DEVDISC_REQ: + DBG_871X("RTW_%s:P2P_DEVDISC_REQ, dialogToken=%d\n", (tx==_TRUE)?"Tx":"Rx", dialogToken); + break; + case P2P_DEVDISC_RESP: + cont = rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, NULL, &cont_len); + DBG_871X("RTW_%s:P2P_DEVDISC_RESP, dialogToken=%d, status:%d\n", (tx==_TRUE)?"Tx":"Rx", dialogToken, cont?*cont:-1); + break; + case P2P_PROVISION_DISC_REQ: + { + size_t frame_body_len = len - sizeof(struct rtw_ieee80211_hdr_3addr); + u8 *p2p_ie; + uint p2p_ielen = 0; + uint contentlen = 0; + + DBG_871X("RTW_%s:P2P_PROVISION_DISC_REQ, dialogToken=%d\n", (tx==_TRUE)?"Tx":"Rx", dialogToken); + + //if(tx) + { + pwdev_priv->provdisc_req_issued = _FALSE; + + if( (p2p_ie=rtw_get_p2p_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, frame_body_len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen))) + { + + if(rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, NULL, &contentlen)) + { + pwdev_priv->provdisc_req_issued = _FALSE;//case: p2p_client join p2p GO + } + else + { + #ifdef CONFIG_DEBUG_CFG80211 + DBG_871X("provdisc_req_issued is _TRUE\n"); + #endif //CONFIG_DEBUG_CFG80211 + pwdev_priv->provdisc_req_issued = _TRUE;//case: p2p_devices connection before Nego req. + } + + } + } + } + break; + case P2P_PROVISION_DISC_RESP: + DBG_871X("RTW_%s:P2P_PROVISION_DISC_RESP, dialogToken=%d\n", (tx==_TRUE)?"Tx":"Rx", dialogToken); + break; + default: + DBG_871X("RTW_%s:OUI_Subtype=%d, dialogToken=%d\n", (tx==_TRUE)?"Tx":"Rx", OUI_Subtype, dialogToken); + break; + } + + } + + } + else if(category == RTW_WLAN_CATEGORY_P2P) + { + OUI_Subtype = frame_body[5]; + dialogToken = frame_body[6]; + + #ifdef CONFIG_DEBUG_CFG80211 + DBG_871X("ACTION_CATEGORY_P2P: OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n", + cpu_to_be32( *( ( u32* ) ( frame_body + 1 ) ) ), OUI_Subtype, dialogToken); + #endif + + is_p2p_frame = OUI_Subtype; + + switch(OUI_Subtype) + { + case P2P_NOTICE_OF_ABSENCE: + DBG_871X("RTW_%s:P2P_NOTICE_OF_ABSENCE, dialogToken=%d\n", (tx==_TRUE)?"TX":"RX", dialogToken); + break; + case P2P_PRESENCE_REQUEST: + DBG_871X("RTW_%s:P2P_PRESENCE_REQUEST, dialogToken=%d\n", (tx==_TRUE)?"TX":"RX", dialogToken); + break; + case P2P_PRESENCE_RESPONSE: + DBG_871X("RTW_%s:P2P_PRESENCE_RESPONSE, dialogToken=%d\n", (tx==_TRUE)?"TX":"RX", dialogToken); + break; + case P2P_GO_DISC_REQUEST: + DBG_871X("RTW_%s:P2P_GO_DISC_REQUEST, dialogToken=%d\n", (tx==_TRUE)?"TX":"RX", dialogToken); + break; + default: + DBG_871X("RTW_%s:OUI_Subtype=%d, dialogToken=%d\n", (tx==_TRUE)?"TX":"RX", OUI_Subtype, dialogToken); + break; + } + + } + else + { + DBG_871X("RTW_%s:action frame category=%d\n", (tx==_TRUE)?"TX":"RX", category); + } + + return is_p2p_frame; +} + +void rtw_init_cfg80211_wifidirect_info( _adapter* padapter) +{ + struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo; + + _rtw_memset(pcfg80211_wdinfo, 0x00, sizeof(struct cfg80211_wifidirect_info) ); + + _init_timer( &pcfg80211_wdinfo->remain_on_ch_timer, padapter->pnetdev, ro_ch_timer_process, padapter ); +} +#endif //CONFIG_IOCTL_CFG80211 + +void p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType) +{ + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); + +_func_enter_; + + switch(intCmdType) + { + case P2P_FIND_PHASE_WK: + { + find_phase_handler( padapter ); + break; + } + case P2P_RESTORE_STATE_WK: + { + restore_p2p_state_handler( padapter ); + break; + } + case P2P_PRE_TX_PROVDISC_PROCESS_WK: + { +#ifdef CONFIG_CONCURRENT_MODE + if ( check_buddy_fwstate(padapter, _FW_LINKED ) ) + { + p2p_concurrent_handler( padapter ); + } + else + { + pre_tx_provdisc_handler( padapter ); + } +#else + pre_tx_provdisc_handler( padapter ); +#endif + break; + } + case P2P_PRE_TX_INVITEREQ_PROCESS_WK: + { +#ifdef CONFIG_CONCURRENT_MODE + if ( check_buddy_fwstate(padapter, _FW_LINKED ) ) + { + p2p_concurrent_handler( padapter ); + } + else + { + pre_tx_invitereq_handler( padapter ); + } +#else + pre_tx_invitereq_handler( padapter ); +#endif + break; + } + case P2P_PRE_TX_NEGOREQ_PROCESS_WK: + { +#ifdef CONFIG_CONCURRENT_MODE + if ( check_buddy_fwstate(padapter, _FW_LINKED ) ) + { + p2p_concurrent_handler( padapter ); + } + else + { + pre_tx_negoreq_handler( padapter ); + } +#else + pre_tx_negoreq_handler( padapter ); +#endif + break; + } +#ifdef CONFIG_P2P +#ifdef CONFIG_CONCURRENT_MODE + case P2P_AP_P2P_CH_SWITCH_PROCESS_WK: + { + p2p_concurrent_handler( padapter ); + break; + } +#endif +#endif +#ifdef CONFIG_IOCTL_CFG80211 + case P2P_RO_CH_WK: + { + ro_ch_handler( padapter ); + break; + } +#endif //CONFIG_IOCTL_CFG80211 + + } + +_func_exit_; +} + +int process_p2p_cross_connect_ie(PADAPTER padapter, u8 *IEs, u32 IELength) +{ + int ret = _TRUE; + u8 * ies; + u32 ies_len; + u8 * p2p_ie; + u32 p2p_ielen = 0; + u8 p2p_attr[MAX_P2P_IE_LEN] = { 0x00 };// NoA length should be n*(13) + 2 + u32 attr_contentlen = 0; + + struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); + +_func_enter_; + + if(IELength <= _BEACON_IE_OFFSET_) + return ret; + + ies = IEs + _BEACON_IE_OFFSET_; + ies_len = IELength - _BEACON_IE_OFFSET_; + + p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen); + + while(p2p_ie) + { + // Get P2P Manageability IE. + if(rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_MANAGEABILITY, p2p_attr, &attr_contentlen)) + { + if ((p2p_attr[0]&(BIT(0)|BIT(1))) == 0x01) { + ret = _FALSE; + } + break; + } + //Get the next P2P IE + p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen); + } + +_func_exit_; + return ret; +} + +#ifdef CONFIG_P2P_PS +void process_p2p_ps_ie(PADAPTER padapter, u8 *IEs, u32 IELength) +{ + u8 * ies; + u32 ies_len; + u8 * p2p_ie; + u32 p2p_ielen = 0; + u8 noa_attr[MAX_P2P_IE_LEN] = { 0x00 };// NoA length should be n*(13) + 2 + u32 attr_contentlen = 0; + + struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); + u8 find_p2p = _FALSE, find_p2p_ps = _FALSE; + u8 noa_offset, noa_num, noa_index; + +_func_enter_; + + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + { + return; + } +#ifdef CONFIG_CONCURRENT_MODE + if(padapter->iface_type != IFACE_PORT0) + return; +#endif + if(IELength <= _BEACON_IE_OFFSET_) + return; + + ies = IEs + _BEACON_IE_OFFSET_; + ies_len = IELength - _BEACON_IE_OFFSET_; + + p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen); + + while(p2p_ie) + { + find_p2p = _TRUE; + // Get Notice of Absence IE. + if(rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_NOA, noa_attr, &attr_contentlen)) + { + find_p2p_ps = _TRUE; + noa_index = noa_attr[0]; + + if( (pwdinfo->p2p_ps_mode == P2P_PS_NONE) || + (noa_index != pwdinfo->noa_index) )// if index change, driver should reconfigure related setting. + { + pwdinfo->noa_index = noa_index; + pwdinfo->opp_ps = noa_attr[1] >> 7; + pwdinfo->ctwindow = noa_attr[1] & 0x7F; + + noa_offset = 2; + noa_num = 0; + // NoA length should be n*(13) + 2 + if(attr_contentlen > 2) + { + while(noa_offset < attr_contentlen) + { + //_rtw_memcpy(&wifidirect_info->noa_count[noa_num], &noa_attr[noa_offset], 1); + pwdinfo->noa_count[noa_num] = noa_attr[noa_offset]; + noa_offset += 1; + + _rtw_memcpy(&pwdinfo->noa_duration[noa_num], &noa_attr[noa_offset], 4); + noa_offset += 4; + + _rtw_memcpy(&pwdinfo->noa_interval[noa_num], &noa_attr[noa_offset], 4); + noa_offset += 4; + + _rtw_memcpy(&pwdinfo->noa_start_time[noa_num], &noa_attr[noa_offset], 4); + noa_offset += 4; + + noa_num++; + } + } + pwdinfo->noa_num = noa_num; + + if( pwdinfo->opp_ps == 1 ) + { + pwdinfo->p2p_ps_mode = P2P_PS_CTWINDOW; + // driver should wait LPS for entering CTWindow + if(adapter_to_pwrctl(padapter)->bFwCurrentInPSMode == _TRUE) + { + p2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 1); + } + } + else if( pwdinfo->noa_num > 0 ) + { + pwdinfo->p2p_ps_mode = P2P_PS_NOA; + p2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 1); + } + else if( pwdinfo->p2p_ps_mode > P2P_PS_NONE) + { + p2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1); + } + } + + break; // find target, just break. + } + + //Get the next P2P IE + p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen); + + } + + if(find_p2p == _TRUE) + { + if( (pwdinfo->p2p_ps_mode > P2P_PS_NONE) && (find_p2p_ps == _FALSE) ) + { + p2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1); + } + } + +_func_exit_; +} + +void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); + +_func_enter_; + + // Pre action for p2p state + switch(p2p_ps_state) + { + case P2P_PS_DISABLE: + pwdinfo->p2p_ps_state = p2p_ps_state; + + rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_P2P_PS_OFFLOAD, (u8 *)(&p2p_ps_state)); + + pwdinfo->noa_index = 0; + pwdinfo->ctwindow = 0; + pwdinfo->opp_ps = 0; + pwdinfo->noa_num = 0; + pwdinfo->p2p_ps_mode = P2P_PS_NONE; + if(pwrpriv->bFwCurrentInPSMode == _TRUE) + { + if(pwrpriv->smart_ps == 0) + { + pwrpriv->smart_ps = 2; + rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&(pwrpriv->pwr_mode))); + } + } + break; + case P2P_PS_ENABLE: + if (pwdinfo->p2p_ps_mode > P2P_PS_NONE) { + pwdinfo->p2p_ps_state = p2p_ps_state; + + if( pwdinfo->ctwindow > 0 ) + { + if(pwrpriv->smart_ps != 0) + { + pwrpriv->smart_ps = 0; + DBG_871X("%s(): Enter CTW, change SmartPS\n", __FUNCTION__); + rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&(pwrpriv->pwr_mode))); + } + } + rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_P2P_PS_OFFLOAD, (u8 *)(&p2p_ps_state)); + } + break; + case P2P_PS_SCAN: + case P2P_PS_SCAN_DONE: + case P2P_PS_ALLSTASLEEP: + if (pwdinfo->p2p_ps_mode > P2P_PS_NONE) { + pwdinfo->p2p_ps_state = p2p_ps_state; + rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_P2P_PS_OFFLOAD, (u8 *)(&p2p_ps_state)); + } + break; + default: + break; + } + +_func_exit_; +} + +u8 p2p_ps_wk_cmd(_adapter*padapter, u8 p2p_ps_state, u8 enqueue) +{ + struct cmd_obj *ph2c; + struct drvextra_cmd_parm *pdrvextra_cmd_parm; + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 res = _SUCCESS; + +_func_enter_; + + if ( rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) +#ifdef CONFIG_CONCURRENT_MODE + || (padapter->iface_type != IFACE_PORT0) +#endif + ) + { + return res; + } + + if(enqueue) + { + ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); + if(ph2c==NULL){ + res= _FAIL; + goto exit; + } + + pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); + if(pdrvextra_cmd_parm==NULL){ + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + res= _FAIL; + goto exit; + } + + pdrvextra_cmd_parm->ec_id = P2P_PS_WK_CID; + pdrvextra_cmd_parm->type = p2p_ps_state; + pdrvextra_cmd_parm->size = 0; + pdrvextra_cmd_parm->pbuf = NULL; + + init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); + + res = rtw_enqueue_cmd(pcmdpriv, ph2c); + } + else + { + p2p_ps_wk_hdl(padapter, p2p_ps_state); + } + +exit: + +_func_exit_; + + return res; + +} +#endif // CONFIG_P2P_PS + +static void reset_ch_sitesurvey_timer_process (void *FunctionContext) +{ + _adapter *adapter = (_adapter *)FunctionContext; + struct wifidirect_info *pwdinfo = &adapter->wdinfo; + + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + return; + + DBG_871X( "[%s] In\n", __FUNCTION__ ); + // Reset the operation channel information + pwdinfo->rx_invitereq_info.operation_ch[0] = 0; +#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH + pwdinfo->rx_invitereq_info.operation_ch[1] = 0; + pwdinfo->rx_invitereq_info.operation_ch[2] = 0; + pwdinfo->rx_invitereq_info.operation_ch[3] = 0; +#endif //CONFIG_P2P_OP_CHK_SOCIAL_CH + pwdinfo->rx_invitereq_info.scan_op_ch_only = 0; +} + +static void reset_ch_sitesurvey_timer_process2 (void *FunctionContext) +{ + _adapter *adapter = (_adapter *)FunctionContext; + struct wifidirect_info *pwdinfo = &adapter->wdinfo; + + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + return; + + DBG_871X( "[%s] In\n", __FUNCTION__ ); + // Reset the operation channel information + pwdinfo->p2p_info.operation_ch[0] = 0; +#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH + pwdinfo->p2p_info.operation_ch[1] = 0; + pwdinfo->p2p_info.operation_ch[2] = 0; + pwdinfo->p2p_info.operation_ch[3] = 0; +#endif //CONFIG_P2P_OP_CHK_SOCIAL_CH + pwdinfo->p2p_info.scan_op_ch_only = 0; +} + +static void restore_p2p_state_timer_process (void *FunctionContext) +{ + _adapter *adapter = (_adapter *)FunctionContext; + struct wifidirect_info *pwdinfo = &adapter->wdinfo; + + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + return; + + p2p_protocol_wk_cmd( adapter, P2P_RESTORE_STATE_WK ); +} + +static void pre_tx_scan_timer_process (void *FunctionContext) +{ + _adapter *adapter = (_adapter *) FunctionContext; + struct wifidirect_info *pwdinfo = &adapter->wdinfo; + _irqL irqL; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + u8 _status = 0; + + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + return; + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) + { + if ( _TRUE == pwdinfo->tx_prov_disc_info.benable ) // the provision discovery request frame is trigger to send or not + { + p2p_protocol_wk_cmd( adapter, P2P_PRE_TX_PROVDISC_PROCESS_WK ); + //issue_probereq_p2p(adapter, NULL); + //_set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); + } + } + else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) + { + if ( _TRUE == pwdinfo->nego_req_info.benable ) + { + p2p_protocol_wk_cmd( adapter, P2P_PRE_TX_NEGOREQ_PROCESS_WK ); + } + } + else if ( rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_INVITE_REQ ) ) + { + if ( _TRUE == pwdinfo->invitereq_info.benable ) + { + p2p_protocol_wk_cmd( adapter, P2P_PRE_TX_INVITEREQ_PROCESS_WK ); + } + } + else + { + DBG_8192C( "[%s] p2p_state is %d, ignore!!\n", __FUNCTION__, rtw_p2p_state(pwdinfo) ); + } + + _exit_critical_bh(&pmlmepriv->lock, &irqL); +} + +static void find_phase_timer_process (void *FunctionContext) +{ + _adapter *adapter = (_adapter *)FunctionContext; + struct wifidirect_info *pwdinfo = &adapter->wdinfo; + + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + return; + + adapter->wdinfo.find_phase_state_exchange_cnt++; + + p2p_protocol_wk_cmd( adapter, P2P_FIND_PHASE_WK ); +} + +#ifdef CONFIG_CONCURRENT_MODE +void ap_p2p_switch_timer_process (void *FunctionContext) +{ + _adapter *adapter = (_adapter *)FunctionContext; + struct wifidirect_info *pwdinfo = &adapter->wdinfo; +#ifdef CONFIG_IOCTL_CFG80211 + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter); +#endif + + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + return; + +#ifdef CONFIG_IOCTL_CFG80211 + ATOMIC_SET(&pwdev_priv->switch_ch_to, 1); +#endif + + p2p_protocol_wk_cmd( adapter, P2P_AP_P2P_CH_SWITCH_PROCESS_WK ); +} +#endif + +void reset_global_wifidirect_info( _adapter* padapter ) +{ + struct wifidirect_info *pwdinfo; + + pwdinfo = &padapter->wdinfo; + pwdinfo->persistent_supported = 0; + pwdinfo->session_available = _TRUE; + rtw_tdls_wfd_enable(padapter, 0); + pwdinfo->wfd_tdls_weaksec = _TRUE; +} + +#ifdef CONFIG_WFD +int rtw_init_wifi_display_info(_adapter* padapter) +{ + int res = _SUCCESS; + struct wifi_display_info *pwfd_info = &padapter->wfd_info; + + // Used in P2P and TDLS + pwfd_info->init_rtsp_ctrlport = 554; +#ifdef CONFIG_IOCTL_CFG80211 + pwfd_info->rtsp_ctrlport = 0; +#else + pwfd_info->rtsp_ctrlport = pwfd_info->init_rtsp_ctrlport; /* set non-zero value for legacy wfd */ +#endif + pwfd_info->tdls_rtsp_ctrlport = 0; + pwfd_info->peer_rtsp_ctrlport = 0; // Reset to 0 + pwfd_info->wfd_enable = _FALSE; + pwfd_info->wfd_device_type = WFD_DEVINFO_PSINK; + pwfd_info->scan_result_type = SCAN_RESULT_P2P_ONLY; + + // Used in P2P + pwfd_info->peer_session_avail = _TRUE; + pwfd_info->wfd_pc = _FALSE; + + // Used in TDLS + _rtw_memset( pwfd_info->ip_address, 0x00, 4 ); + _rtw_memset( pwfd_info->peer_ip_address, 0x00, 4 ); + return res; + +} + +inline void rtw_wfd_enable(_adapter *adapter, bool on) +{ + struct wifi_display_info *wfdinfo = &adapter->wfd_info; + + if (on) { + wfdinfo->rtsp_ctrlport = wfdinfo->init_rtsp_ctrlport; + wfdinfo->wfd_enable = _TRUE; + + } else { + wfdinfo->wfd_enable = _FALSE; + wfdinfo->rtsp_ctrlport = 0; + } +} + +inline void rtw_wfd_set_ctrl_port(_adapter *adapter, u16 port) +{ + struct wifi_display_info *wfdinfo = &adapter->wfd_info; + + wfdinfo->init_rtsp_ctrlport = port; + if (wfdinfo->wfd_enable == _TRUE) + wfdinfo->rtsp_ctrlport = port; + if (adapter->wdinfo.wfd_tdls_enable == 1) + wfdinfo->tdls_rtsp_ctrlport = port; +} + +inline void rtw_tdls_wfd_enable(_adapter *adapter, bool on) +{ + struct wifi_display_info *wfdinfo = &adapter->wfd_info; + + if (on) { + wfdinfo->tdls_rtsp_ctrlport = wfdinfo->init_rtsp_ctrlport; + adapter->wdinfo.wfd_tdls_enable = 1; + + } else { + adapter->wdinfo.wfd_tdls_enable = 0; + wfdinfo->tdls_rtsp_ctrlport = 0; + } +} + +u32 rtw_append_beacon_wfd_ie(_adapter *adapter, u8 *pbuf) +{ + struct wifidirect_info *wdinfo = &adapter->wdinfo; + struct mlme_priv *mlme = &adapter->mlmepriv; + u8 build_ie_by_self = 0; + u32 len = 0; + + if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) + goto exit; + +#ifdef CONFIG_IOCTL_CFG80211 + if (_TRUE == wdinfo->wfd_info->wfd_enable) +#endif + build_ie_by_self = 1; + + if (build_ie_by_self) + len = build_beacon_wfd_ie(wdinfo, pbuf); +#ifdef CONFIG_IOCTL_CFG80211 + else if (mlme->wfd_beacon_ie && mlme->wfd_beacon_ie_len > 0) { + len = mlme->wfd_beacon_ie_len; + _rtw_memcpy(pbuf, mlme->wfd_beacon_ie, len); + } +#endif + +exit: + return len; +} + +u32 rtw_append_probe_req_wfd_ie(_adapter *adapter, u8 *pbuf) +{ + struct wifidirect_info *wdinfo = &adapter->wdinfo; + struct mlme_priv *mlme = &adapter->mlmepriv; + u8 build_ie_by_self = 0; + u32 len = 0; + + if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) + goto exit; + +#ifdef CONFIG_IOCTL_CFG80211 + if (_TRUE == wdinfo->wfd_info->wfd_enable) +#endif + build_ie_by_self = 1; + + if (build_ie_by_self) + len = build_probe_req_wfd_ie(wdinfo, pbuf); +#ifdef CONFIG_IOCTL_CFG80211 + else if (mlme->wfd_probe_req_ie && mlme->wfd_probe_req_ie_len > 0) { + len = mlme->wfd_probe_req_ie_len; + _rtw_memcpy(pbuf, mlme->wfd_probe_req_ie, len); + } +#endif + +exit: + return len; +} + +u32 rtw_append_probe_resp_wfd_ie(_adapter *adapter, u8 *pbuf) +{ + struct wifidirect_info *wdinfo = &adapter->wdinfo; + struct mlme_priv *mlme = &adapter->mlmepriv; + u8 build_ie_by_self = 0; + u32 len = 0; + + if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) + goto exit; + +#ifdef CONFIG_IOCTL_CFG80211 + if (_TRUE == wdinfo->wfd_info->wfd_enable) +#endif + build_ie_by_self = 1; + + if (build_ie_by_self) + len = build_probe_resp_wfd_ie(wdinfo, pbuf, 0); +#ifdef CONFIG_IOCTL_CFG80211 + else if (mlme->wfd_probe_resp_ie && mlme->wfd_probe_resp_ie_len > 0) { + len = mlme->wfd_probe_resp_ie_len; + _rtw_memcpy(pbuf, mlme->wfd_probe_resp_ie, len); + } +#endif + +exit: + return len; +} + +u32 rtw_append_assoc_req_wfd_ie(_adapter *adapter, u8 *pbuf) +{ + struct wifidirect_info *wdinfo = &adapter->wdinfo; + struct mlme_priv *mlme = &adapter->mlmepriv; + u8 build_ie_by_self = 0; + u32 len = 0; + + if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) + goto exit; + +#ifdef CONFIG_IOCTL_CFG80211 + if (_TRUE == wdinfo->wfd_info->wfd_enable) +#endif + build_ie_by_self = 1; + + if (build_ie_by_self) + len = build_assoc_req_wfd_ie(wdinfo, pbuf); +#ifdef CONFIG_IOCTL_CFG80211 + else if (mlme->wfd_assoc_req_ie && mlme->wfd_assoc_req_ie_len > 0) { + len = mlme->wfd_assoc_req_ie_len; + _rtw_memcpy(pbuf, mlme->wfd_assoc_req_ie, len); + } +#endif + +exit: + return len; +} + +u32 rtw_append_assoc_resp_wfd_ie(_adapter *adapter, u8 *pbuf) +{ + struct wifidirect_info *wdinfo = &adapter->wdinfo; + struct mlme_priv *mlme = &adapter->mlmepriv; + u8 build_ie_by_self = 0; + u32 len = 0; + + if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) + goto exit; + +#ifdef CONFIG_IOCTL_CFG80211 + if (_TRUE == wdinfo->wfd_info->wfd_enable) +#endif + build_ie_by_self = 1; + + if (build_ie_by_self) + len = build_assoc_resp_wfd_ie(wdinfo, pbuf); +#ifdef CONFIG_IOCTL_CFG80211 + else if (mlme->wfd_assoc_resp_ie && mlme->wfd_assoc_resp_ie_len > 0) { + len = mlme->wfd_assoc_resp_ie_len; + _rtw_memcpy(pbuf, mlme->wfd_assoc_resp_ie, len); + } +#endif + +exit: + return len; +} + +#endif /* CONFIG_WFD */ + +void rtw_init_wifidirect_timers(_adapter* padapter) +{ + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + + _init_timer( &pwdinfo->find_phase_timer, padapter->pnetdev, find_phase_timer_process, padapter ); + _init_timer( &pwdinfo->restore_p2p_state_timer, padapter->pnetdev, restore_p2p_state_timer_process, padapter ); + _init_timer( &pwdinfo->pre_tx_scan_timer, padapter->pnetdev, pre_tx_scan_timer_process, padapter ); + _init_timer( &pwdinfo->reset_ch_sitesurvey, padapter->pnetdev, reset_ch_sitesurvey_timer_process, padapter ); + _init_timer( &pwdinfo->reset_ch_sitesurvey2, padapter->pnetdev, reset_ch_sitesurvey_timer_process2, padapter ); +#ifdef CONFIG_CONCURRENT_MODE + _init_timer( &pwdinfo->ap_p2p_switch_timer, padapter->pnetdev, ap_p2p_switch_timer_process, padapter ); +#endif +} + +void rtw_init_wifidirect_addrs(_adapter* padapter, u8 *dev_addr, u8 *iface_addr) +{ +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + + /*init device&interface address */ + if (dev_addr) { + _rtw_memcpy(pwdinfo->device_addr, dev_addr, ETH_ALEN); + } + if (iface_addr) { + _rtw_memcpy(pwdinfo->interface_addr, iface_addr, ETH_ALEN); + } +#endif +} + +void init_wifidirect_info( _adapter* padapter, enum P2P_ROLE role) +{ + struct wifidirect_info *pwdinfo; +#ifdef CONFIG_WFD + struct wifi_display_info *pwfd_info = &padapter->wfd_info; +#endif +#ifdef CONFIG_CONCURRENT_MODE + _adapter *pbuddy_adapter = padapter->pbuddy_adapter; + struct wifidirect_info *pbuddy_wdinfo = NULL; + struct mlme_priv *pbuddy_mlmepriv = NULL; + struct mlme_ext_priv *pbuddy_mlmeext = NULL; +#endif + + pwdinfo = &padapter->wdinfo; + + pwdinfo->padapter = padapter; + + // 1, 6, 11 are the social channel defined in the WiFi Direct specification. + pwdinfo->social_chan[0] = 1; + pwdinfo->social_chan[1] = 6; + pwdinfo->social_chan[2] = 11; + pwdinfo->social_chan[3] = 0; // channel 0 for scanning ending in site survey function. + +#ifdef CONFIG_CONCURRENT_MODE + if (pbuddy_adapter) { + pbuddy_wdinfo = &pbuddy_adapter->wdinfo; + pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv; + pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; + } + + if ( ( check_buddy_fwstate(padapter, _FW_LINKED ) == _TRUE ) && + ( ( pbuddy_mlmeext->cur_channel == 1) || ( pbuddy_mlmeext->cur_channel == 6 ) || ( pbuddy_mlmeext->cur_channel == 11 ) ) + ) + { + // Use the AP's channel as the listen channel + // This will avoid the channel switch between AP's channel and listen channel. + pwdinfo->listen_channel = pbuddy_mlmeext->cur_channel; + } + else +#endif //CONFIG_CONCURRENT_MODE + { + // Use the channel 11 as the listen channel + pwdinfo->listen_channel = 11; + } + + if (role == P2P_ROLE_DEVICE) + { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); + #ifdef CONFIG_CONCURRENT_MODE + if ( check_buddy_fwstate(padapter, _FW_LINKED ) == _TRUE ) + { + rtw_p2p_set_state(pwdinfo, P2P_STATE_IDLE); + } + else + #endif + { + rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN); + } + pwdinfo->intent = 1; + rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_LISTEN); + } + else if (role == P2P_ROLE_CLIENT) + { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); + pwdinfo->intent = 1; + rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK); + } + else if (role == P2P_ROLE_GO) + { + rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); + pwdinfo->intent = 15; + rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_GONEGO_OK); + } + +// Use the OFDM rate in the P2P probe response frame. ( 6(B), 9(B), 12, 18, 24, 36, 48, 54 ) + pwdinfo->support_rate[0] = 0x8c; // 6(B) + pwdinfo->support_rate[1] = 0x92; // 9(B) + pwdinfo->support_rate[2] = 0x18; // 12 + pwdinfo->support_rate[3] = 0x24; // 18 + pwdinfo->support_rate[4] = 0x30; // 24 + pwdinfo->support_rate[5] = 0x48; // 36 + pwdinfo->support_rate[6] = 0x60; // 48 + pwdinfo->support_rate[7] = 0x6c; // 54 + + _rtw_memcpy( ( void* ) pwdinfo->p2p_wildcard_ssid, "DIRECT-", 7 ); + + _rtw_memset( pwdinfo->device_name, 0x00, WPS_MAX_DEVICE_NAME_LEN ); + pwdinfo->device_name_len = 0; + + _rtw_memset( &pwdinfo->invitereq_info, 0x00, sizeof( struct tx_invite_req_info ) ); + pwdinfo->invitereq_info.token = 3; // Token used for P2P invitation request frame. + + _rtw_memset( &pwdinfo->inviteresp_info, 0x00, sizeof( struct tx_invite_resp_info ) ); + pwdinfo->inviteresp_info.token = 0; + + pwdinfo->profileindex = 0; + _rtw_memset( &pwdinfo->profileinfo[ 0 ], 0x00, sizeof( struct profile_info ) * P2P_MAX_PERSISTENT_GROUP_NUM ); + + rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE); + + pwdinfo->listen_dwell = ( u8 ) (( rtw_get_current_time() % 3 ) + 1); + //DBG_8192C( "[%s] listen_dwell time is %d00ms\n", __FUNCTION__, pwdinfo->listen_dwell ); + + _rtw_memset( &pwdinfo->tx_prov_disc_info, 0x00, sizeof( struct tx_provdisc_req_info ) ); + pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_NONE; + + _rtw_memset( &pwdinfo->nego_req_info, 0x00, sizeof( struct tx_nego_req_info ) ); + + pwdinfo->device_password_id_for_nego = WPS_DPID_PBC; + pwdinfo->negotiation_dialog_token = 1; + + _rtw_memset( pwdinfo->nego_ssid, 0x00, WLAN_SSID_MAXLEN ); + pwdinfo->nego_ssidlen = 0; + + pwdinfo->ui_got_wps_info = P2P_NO_WPSINFO; +#ifdef CONFIG_WFD + pwdinfo->supported_wps_cm = WPS_CONFIG_METHOD_DISPLAY | WPS_CONFIG_METHOD_PBC; + pwdinfo->wfd_info = pwfd_info; +#else + pwdinfo->supported_wps_cm = WPS_CONFIG_METHOD_DISPLAY | WPS_CONFIG_METHOD_PBC | WPS_CONFIG_METHOD_KEYPAD; +#endif //CONFIG_WFD + pwdinfo->channel_list_attr_len = 0; + _rtw_memset( pwdinfo->channel_list_attr, 0x00, 100 ); + + _rtw_memset( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, 0x00, 4 ); + _rtw_memset( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, '0', 3 ); + _rtw_memset( &pwdinfo->groupid_info, 0x00, sizeof( struct group_id_info ) ); +#ifdef CONFIG_CONCURRENT_MODE +#ifdef CONFIG_IOCTL_CFG80211 + pwdinfo->ext_listen_interval = 1000; //The interval to be available with legacy AP during p2p0-find/scan + pwdinfo->ext_listen_period = 3000; //The time period to be available for P2P during nego +#else //!CONFIG_IOCTL_CFG80211 + //pwdinfo->ext_listen_interval = 3000; + //pwdinfo->ext_listen_period = 400; + pwdinfo->ext_listen_interval = 1000; + pwdinfo->ext_listen_period = 1000; +#endif //!CONFIG_IOCTL_CFG80211 +#endif + +// Commented by Kurt 20130319 +// For WiDi purpose: Use CFG80211 interface but controled WFD/RDS frame by driver itself. +#ifdef CONFIG_IOCTL_CFG80211 + pwdinfo->driver_interface = DRIVER_CFG80211; +#else + pwdinfo->driver_interface = DRIVER_WEXT; +#endif //CONFIG_IOCTL_CFG80211 + + pwdinfo->wfd_tdls_enable = 0; + _rtw_memset( pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN ); + _rtw_memset( pwdinfo->p2p_peer_device_addr, 0x00, ETH_ALEN ); + + pwdinfo->rx_invitereq_info.operation_ch[0] = 0; + pwdinfo->rx_invitereq_info.operation_ch[1] = 0; // Used to indicate the scan end in site survey function +#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH + pwdinfo->rx_invitereq_info.operation_ch[2] = 0; + pwdinfo->rx_invitereq_info.operation_ch[3] = 0; + pwdinfo->rx_invitereq_info.operation_ch[4] = 0; +#endif //CONFIG_P2P_OP_CHK_SOCIAL_CH + pwdinfo->rx_invitereq_info.scan_op_ch_only = 0; + pwdinfo->p2p_info.operation_ch[0] = 0; + pwdinfo->p2p_info.operation_ch[1] = 0; // Used to indicate the scan end in site survey function +#ifdef CONFIG_P2P_OP_CHK_SOCIAL_CH + pwdinfo->p2p_info.operation_ch[2] = 0; + pwdinfo->p2p_info.operation_ch[3] = 0; + pwdinfo->p2p_info.operation_ch[4] = 0; +#endif //CONFIG_P2P_OP_CHK_SOCIAL_CH + pwdinfo->p2p_info.scan_op_ch_only = 0; +} + +#ifdef CONFIG_DBG_P2P + +/** + * rtw_p2p_role_txt - Get the p2p role name as a text string + * @role: P2P role + * Returns: The state name as a printable text string + */ +const char * rtw_p2p_role_txt(enum P2P_ROLE role) +{ + switch (role) { + case P2P_ROLE_DISABLE: + return "P2P_ROLE_DISABLE"; + case P2P_ROLE_DEVICE: + return "P2P_ROLE_DEVICE"; + case P2P_ROLE_CLIENT: + return "P2P_ROLE_CLIENT"; + case P2P_ROLE_GO: + return "P2P_ROLE_GO"; + default: + return "UNKNOWN"; + } +} + +/** + * rtw_p2p_state_txt - Get the p2p state name as a text string + * @state: P2P state + * Returns: The state name as a printable text string + */ +const char * rtw_p2p_state_txt(enum P2P_STATE state) +{ + switch (state) { + case P2P_STATE_NONE: + return "P2P_STATE_NONE"; + case P2P_STATE_IDLE: + return "P2P_STATE_IDLE"; + case P2P_STATE_LISTEN: + return "P2P_STATE_LISTEN"; + case P2P_STATE_SCAN: + return "P2P_STATE_SCAN"; + case P2P_STATE_FIND_PHASE_LISTEN: + return "P2P_STATE_FIND_PHASE_LISTEN"; + case P2P_STATE_FIND_PHASE_SEARCH: + return "P2P_STATE_FIND_PHASE_SEARCH"; + case P2P_STATE_TX_PROVISION_DIS_REQ: + return "P2P_STATE_TX_PROVISION_DIS_REQ"; + case P2P_STATE_RX_PROVISION_DIS_RSP: + return "P2P_STATE_RX_PROVISION_DIS_RSP"; + case P2P_STATE_RX_PROVISION_DIS_REQ: + return "P2P_STATE_RX_PROVISION_DIS_REQ"; + case P2P_STATE_GONEGO_ING: + return "P2P_STATE_GONEGO_ING"; + case P2P_STATE_GONEGO_OK: + return "P2P_STATE_GONEGO_OK"; + case P2P_STATE_GONEGO_FAIL: + return "P2P_STATE_GONEGO_FAIL"; + case P2P_STATE_RECV_INVITE_REQ_MATCH: + return "P2P_STATE_RECV_INVITE_REQ_MATCH"; + case P2P_STATE_PROVISIONING_ING: + return "P2P_STATE_PROVISIONING_ING"; + case P2P_STATE_PROVISIONING_DONE: + return "P2P_STATE_PROVISIONING_DONE"; + case P2P_STATE_TX_INVITE_REQ: + return "P2P_STATE_TX_INVITE_REQ"; + case P2P_STATE_RX_INVITE_RESP_OK: + return "P2P_STATE_RX_INVITE_RESP_OK"; + case P2P_STATE_RECV_INVITE_REQ_DISMATCH: + return "P2P_STATE_RECV_INVITE_REQ_DISMATCH"; + case P2P_STATE_RECV_INVITE_REQ_GO: + return "P2P_STATE_RECV_INVITE_REQ_GO"; + case P2P_STATE_RECV_INVITE_REQ_JOIN: + return "P2P_STATE_RECV_INVITE_REQ_JOIN"; + case P2P_STATE_RX_INVITE_RESP_FAIL: + return "P2P_STATE_RX_INVITE_RESP_FAIL"; + case P2P_STATE_RX_INFOR_NOREADY: + return "P2P_STATE_RX_INFOR_NOREADY"; + case P2P_STATE_TX_INFOR_NOREADY: + return "P2P_STATE_TX_INFOR_NOREADY"; + default: + return "UNKNOWN"; + } +} + +void dbg_rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line) +{ + if(!_rtw_p2p_chk_state(wdinfo, state)) { + enum P2P_STATE old_state = _rtw_p2p_state(wdinfo); + _rtw_p2p_set_state(wdinfo, state); + DBG_871X("[CONFIG_DBG_P2P]%s:%d set_state from %s to %s\n", caller, line + , rtw_p2p_state_txt(old_state), rtw_p2p_state_txt(_rtw_p2p_state(wdinfo)) + ); + } else { + DBG_871X("[CONFIG_DBG_P2P]%s:%d set_state to same state %s\n", caller, line + , rtw_p2p_state_txt(_rtw_p2p_state(wdinfo)) + ); + } +} +void dbg_rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line) +{ + if(_rtw_p2p_pre_state(wdinfo) != state) { + enum P2P_STATE old_state = _rtw_p2p_pre_state(wdinfo); + _rtw_p2p_set_pre_state(wdinfo, state); + DBG_871X("[CONFIG_DBG_P2P]%s:%d set_pre_state from %s to %s\n", caller, line + , rtw_p2p_state_txt(old_state), rtw_p2p_state_txt(_rtw_p2p_pre_state(wdinfo)) + ); + } else { + DBG_871X("[CONFIG_DBG_P2P]%s:%d set_pre_state to same state %s\n", caller, line + , rtw_p2p_state_txt(_rtw_p2p_pre_state(wdinfo)) + ); + } +} +#if 0 +void dbg_rtw_p2p_restore_state(struct wifidirect_info *wdinfo, const char *caller, int line) +{ + if(wdinfo->pre_p2p_state != -1) { + DBG_871X("[CONFIG_DBG_P2P]%s:%d restore from %s to %s\n", caller, line + , p2p_state_str[wdinfo->p2p_state], p2p_state_str[wdinfo->pre_p2p_state] + ); + _rtw_p2p_restore_state(wdinfo); + } else { + DBG_871X("[CONFIG_DBG_P2P]%s:%d restore no pre state, cur state %s\n", caller, line + , p2p_state_str[wdinfo->p2p_state] + ); + } +} +#endif +void dbg_rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role, const char *caller, int line) +{ + if(wdinfo->role != role) { + enum P2P_ROLE old_role = wdinfo->role; + _rtw_p2p_set_role(wdinfo, role); + DBG_871X("[CONFIG_DBG_P2P]%s:%d set_role from %s to %s\n", caller, line + , rtw_p2p_role_txt(old_role), rtw_p2p_role_txt(wdinfo->role) + ); + } else { + DBG_871X("[CONFIG_DBG_P2P]%s:%d set_role to same role %s\n", caller, line + , rtw_p2p_role_txt(wdinfo->role) + ); + } +} +#endif //CONFIG_DBG_P2P + + +int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role) +{ + int ret = _SUCCESS; + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); + + if (role == P2P_ROLE_DEVICE || role == P2P_ROLE_CLIENT|| role == P2P_ROLE_GO) + { + u8 channel, ch_offset; + u16 bwmode; + +#ifdef CONFIG_CONCURRENT_MODE + _adapter *pbuddy_adapter = padapter->pbuddy_adapter; + struct wifidirect_info *pbuddy_wdinfo = &pbuddy_adapter->wdinfo; + // Commented by Albert 2011/12/30 + // The driver just supports 1 P2P group operation. + // So, this function will do nothing if the buddy adapter had enabled the P2P function. + if(!rtw_p2p_chk_state(pbuddy_wdinfo, P2P_STATE_NONE)) + { + // The buddy adapter had enabled the P2P function. + return ret; + } +#endif //CONFIG_CONCURRENT_MODE + + //leave IPS/Autosuspend + if (_FAIL == rtw_pwr_wakeup(padapter)) { + ret = _FAIL; + goto exit; + } + + // Added by Albert 2011/03/22 + // In the P2P mode, the driver should not support the b mode. + // So, the Tx packet shouldn't use the CCK rate + update_tx_basic_rate(padapter, WIRELESS_11AGN); + + //Enable P2P function + init_wifidirect_info(padapter, role); + + rtw_hal_set_odm_var(padapter,HAL_ODM_P2P_STATE,NULL,_TRUE); + #ifdef CONFIG_WFD + if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + rtw_hal_set_odm_var(padapter, HAL_ODM_WIFI_DISPLAY_STATE, NULL, _TRUE); + #endif + + } + else if (role == P2P_ROLE_DISABLE) + { +#ifdef CONFIG_INTEL_WIDI + if( padapter->mlmepriv.p2p_reject_disable == _TRUE ) + return ret; +#endif //CONFIG_INTEL_WIDI + +#ifdef CONFIG_IOCTL_CFG80211 + if( padapter->wdinfo.driver_interface == DRIVER_CFG80211 ) + adapter_wdev_data(padapter)->p2p_enabled = _FALSE; +#endif //CONFIG_IOCTL_CFG80211 + + + //Disable P2P function + if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + { + _cancel_timer_ex( &pwdinfo->find_phase_timer ); + _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer ); + _cancel_timer_ex( &pwdinfo->pre_tx_scan_timer); + _cancel_timer_ex( &pwdinfo->reset_ch_sitesurvey); + _cancel_timer_ex( &pwdinfo->reset_ch_sitesurvey2); + reset_ch_sitesurvey_timer_process( padapter ); + reset_ch_sitesurvey_timer_process2( padapter ); + #ifdef CONFIG_CONCURRENT_MODE + _cancel_timer_ex( &pwdinfo->ap_p2p_switch_timer); + #endif + rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE); + rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_NONE); + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DISABLE); + _rtw_memset(&pwdinfo->rx_prov_disc_info, 0x00, sizeof(struct rx_provdisc_req_info)); + + /* Remove profiles in wifidirect_info structure. */ + _rtw_memset( &pwdinfo->profileinfo[ 0 ], 0x00, sizeof( struct profile_info ) * P2P_MAX_PERSISTENT_GROUP_NUM ); + pwdinfo->profileindex = 0; + } + + rtw_hal_set_odm_var(padapter,HAL_ODM_P2P_STATE,NULL,_FALSE); + #ifdef CONFIG_WFD + if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + rtw_hal_set_odm_var(padapter, HAL_ODM_WIFI_DISPLAY_STATE, NULL, _FALSE); + #endif + + if (_FAIL == rtw_pwr_wakeup(padapter)) { + ret = _FAIL; + goto exit; + } + + //Restore to initial setting. + update_tx_basic_rate(padapter, padapter->registrypriv.wireless_mode); + +#ifdef CONFIG_INTEL_WIDI + rtw_reset_widi_info(padapter); +#endif //CONFIG_INTEL_WIDI + + //For WiDi purpose. +#ifdef CONFIG_IOCTL_CFG80211 + pwdinfo->driver_interface = DRIVER_CFG80211; +#else + pwdinfo->driver_interface = DRIVER_WEXT; +#endif //CONFIG_IOCTL_CFG80211 + + } + +exit: + return ret; +} + +#endif //CONFIG_P2P + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_pwrctrl.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_pwrctrl.c new file mode 100644 index 000000000..e6715afae --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_pwrctrl.c @@ -0,0 +1,2629 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_PWRCTRL_C_ + +#include +#include +#include + +int rtw_fw_ps_state(PADAPTER padapter) +{ + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + int ret=_FAIL, dont_care=0; + u16 fw_ps_state=0; + u32 start_time; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct registry_priv *registry_par = &padapter->registrypriv; + + if(registry_par->check_fw_ps != 1) + return _SUCCESS; + + _enter_pwrlock(&pwrpriv->check_32k_lock); + + if (RTW_CANNOT_RUN(padapter)) { + DBG_871X("%s: bSurpriseRemoved=%s , hw_init_completed=%d, bDriverStopped=%s\n", __func__ + , rtw_is_surprise_removed(padapter)?"True":"False" + , rtw_get_hw_init_completed(padapter) + , rtw_is_drv_stopped(padapter)?"True":"False"); + goto exit_fw_ps_state; + } + rtw_hal_set_hwreg(padapter, HW_VAR_SET_REQ_FW_PS, (u8 *)&dont_care); + { + //4. if 0x88[7]=1, driver set cmd to leave LPS/IPS. + //Else, hw will keep in active mode. + //debug info: + //0x88[7] = 32kpermission, + //0x88[6:0] = current_ps_state + //0x89[7:0] = last_rpwm + + rtw_hal_get_hwreg(padapter, HW_VAR_FW_PS_STATE, (u8 *)&fw_ps_state); + + if((fw_ps_state & 0x80) == 0) + ret=_SUCCESS; + else + { + pdbgpriv->dbg_poll_fail_cnt++; + DBG_871X("%s: fw_ps_state=%04x \n", __FUNCTION__, fw_ps_state); + } + } + + +exit_fw_ps_state: + _exit_pwrlock(&pwrpriv->check_32k_lock); + return ret; +} + +#ifdef CONFIG_IPS +void _ips_enter(_adapter * padapter) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + + pwrpriv->bips_processing = _TRUE; + + // syn ips_mode with request + pwrpriv->ips_mode = pwrpriv->ips_mode_req; + + pwrpriv->ips_enter_cnts++; + DBG_871X("==>ips_enter cnts:%d\n",pwrpriv->ips_enter_cnts); + + if(rf_off == pwrpriv->change_rfpwrstate ) + { + pwrpriv->bpower_saving = _TRUE; + DBG_871X_LEVEL(_drv_always_, "nolinked power save enter\n"); + + if(pwrpriv->ips_mode == IPS_LEVEL_2) + pwrpriv->bkeepfwalive = _TRUE; + + rtw_ips_pwr_down(padapter); + pwrpriv->rf_pwrstate = rf_off; + } + pwrpriv->bips_processing = _FALSE; + +} + +void ips_enter(_adapter * padapter) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + + +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_IpsNotify(padapter, pwrpriv->ips_mode_req); +#endif // CONFIG_BT_COEXIST + + _enter_pwrlock(&pwrpriv->lock); + _ips_enter(padapter); + _exit_pwrlock(&pwrpriv->lock); +} + +int _ips_leave(_adapter * padapter) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + int result = _SUCCESS; + + if((pwrpriv->rf_pwrstate == rf_off) &&(!pwrpriv->bips_processing)) + { + pwrpriv->bips_processing = _TRUE; + pwrpriv->change_rfpwrstate = rf_on; + pwrpriv->ips_leave_cnts++; + DBG_871X("==>ips_leave cnts:%d\n",pwrpriv->ips_leave_cnts); + + if ((result = rtw_ips_pwr_up(padapter)) == _SUCCESS) { + pwrpriv->rf_pwrstate = rf_on; + } + DBG_871X_LEVEL(_drv_always_, "nolinked power save leave\n"); + + DBG_871X("==> ips_leave.....LED(0x%08x)...\n",rtw_read32(padapter,0x4c)); + pwrpriv->bips_processing = _FALSE; + + pwrpriv->bkeepfwalive = _FALSE; + pwrpriv->bpower_saving = _FALSE; + } + + return result; +} + +int ips_leave(_adapter * padapter) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + int ret; + + if(!is_primary_adapter(padapter)) + return _SUCCESS; + + _enter_pwrlock(&pwrpriv->lock); + ret = _ips_leave(padapter); +#ifdef DBG_CHECK_FW_PS_STATE + if(rtw_fw_ps_state(padapter) == _FAIL) + { + DBG_871X("ips leave doesn't leave 32k\n"); + pdbgpriv->dbg_leave_ips_fail_cnt++; + } +#endif //DBG_CHECK_FW_PS_STATE + _exit_pwrlock(&pwrpriv->lock); + + if (_SUCCESS == ret) + ODM_DMReset(&GET_HAL_DATA(padapter)->odmpriv); + +#ifdef CONFIG_BT_COEXIST + if (_SUCCESS == ret) + rtw_btcoex_IpsNotify(padapter, IPS_NONE); +#endif // CONFIG_BT_COEXIST + + return ret; +} +#endif /* CONFIG_IPS */ + +#ifdef CONFIG_AUTOSUSPEND +extern void autosuspend_enter(_adapter* padapter); +extern int autoresume_enter(_adapter* padapter); +#endif + +#ifdef SUPPORT_HW_RFOFF_DETECTED +int rtw_hw_suspend(_adapter *padapter ); +int rtw_hw_resume(_adapter *padapter); +#endif + +bool rtw_pwr_unassociated_idle(_adapter *adapter) +{ + _adapter *buddy = adapter->pbuddy_adapter; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct xmit_priv *pxmit_priv = &adapter->xmitpriv; +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &(adapter->wdinfo); +#ifdef CONFIG_IOCTL_CFG80211 + struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &adapter->cfg80211_wdinfo; +#endif +#endif + + bool ret = _FALSE; + + if (adapter_to_pwrctl(adapter)->bpower_saving ==_TRUE ) { + //DBG_871X("%s: already in LPS or IPS mode\n", __func__); + goto exit; + } + + if (adapter_to_pwrctl(adapter)->ips_deny_time >= rtw_get_current_time()) { + //DBG_871X("%s ips_deny_time\n", __func__); + goto exit; + } + + if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE|WIFI_SITE_MONITOR) + || check_fwstate(pmlmepriv, WIFI_UNDER_LINKING|WIFI_UNDER_WPS) + || check_fwstate(pmlmepriv, WIFI_AP_STATE) + || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE|WIFI_ADHOC_STATE) + #if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) + || pcfg80211_wdinfo->is_ro_ch + #elif defined(CONFIG_P2P) + || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE) + || rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN) + #endif + #if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) + || rtw_get_passing_time_ms(pcfg80211_wdinfo->last_ro_ch_time) < 3000 + #endif + ) { + goto exit; + } + + /* consider buddy, if exist */ + if (buddy) { + struct mlme_priv *b_pmlmepriv = &(buddy->mlmepriv); + #ifdef CONFIG_P2P + struct wifidirect_info *b_pwdinfo = &(buddy->wdinfo); + #ifdef CONFIG_IOCTL_CFG80211 + struct cfg80211_wifidirect_info *b_pcfg80211_wdinfo = &buddy->cfg80211_wdinfo; + #endif + #endif + + if (check_fwstate(b_pmlmepriv, WIFI_ASOC_STATE|WIFI_SITE_MONITOR) + || check_fwstate(b_pmlmepriv, WIFI_UNDER_LINKING|WIFI_UNDER_WPS) + || check_fwstate(b_pmlmepriv, WIFI_AP_STATE) + || check_fwstate(b_pmlmepriv, WIFI_ADHOC_MASTER_STATE|WIFI_ADHOC_STATE) + #if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) + || b_pcfg80211_wdinfo->is_ro_ch + #elif defined(CONFIG_P2P) + || rtw_p2p_chk_state(b_pwdinfo, P2P_STATE_IDLE) + || rtw_p2p_chk_state(b_pwdinfo, P2P_STATE_LISTEN) + #endif + #if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) + || rtw_get_passing_time_ms(b_pcfg80211_wdinfo->last_ro_ch_time) < 3000 + #endif + ) { + goto exit; + } + } + +#if (MP_DRIVER == 1) + if (adapter->registrypriv.mp_mode == 1) + goto exit; +#endif + +#ifdef CONFIG_INTEL_PROXIM + if(adapter->proximity.proxim_on==_TRUE){ + return; + } +#endif + + if (pxmit_priv->free_xmitbuf_cnt != NR_XMITBUFF || + pxmit_priv->free_xmit_extbuf_cnt != NR_XMIT_EXTBUFF) { + DBG_871X_LEVEL(_drv_always_, "There are some pkts to transmit\n"); + DBG_871X_LEVEL(_drv_always_, "free_xmitbuf_cnt: %d, free_xmit_extbuf_cnt: %d\n", + pxmit_priv->free_xmitbuf_cnt, pxmit_priv->free_xmit_extbuf_cnt); + goto exit; + } + + ret = _TRUE; + +exit: + return ret; +} + + +/* + * ATTENTION: + * rtw_ps_processor() doesn't handle LPS. + */ +void rtw_ps_processor(_adapter*padapter) +{ +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); +#endif //CONFIG_P2P + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; +#ifdef SUPPORT_HW_RFOFF_DETECTED + rt_rf_power_state rfpwrstate; +#endif //SUPPORT_HW_RFOFF_DETECTED + u32 ps_deny = 0; + + _enter_pwrlock(&adapter_to_pwrctl(padapter)->lock); + ps_deny = rtw_ps_deny_get(padapter); + _exit_pwrlock(&adapter_to_pwrctl(padapter)->lock); + if (ps_deny != 0) + { + DBG_871X(FUNC_ADPT_FMT ": ps_deny=0x%08X, skip power save!\n", + FUNC_ADPT_ARG(padapter), ps_deny); + goto exit; + } + + if(pwrpriv->bInSuspend == _TRUE){//system suspend or autosuspend + pdbgpriv->dbg_ps_insuspend_cnt++; + DBG_871X("%s, pwrpriv->bInSuspend == _TRUE ignore this process\n",__FUNCTION__); + return; + } + + pwrpriv->ps_processing = _TRUE; + +#ifdef SUPPORT_HW_RFOFF_DETECTED + if(pwrpriv->bips_processing == _TRUE) + goto exit; + + //DBG_871X("==> fw report state(0x%x)\n",rtw_read8(padapter,0x1ca)); + if(pwrpriv->bHWPwrPindetect) + { + #ifdef CONFIG_AUTOSUSPEND + if(padapter->registrypriv.usbss_enable) + { + if(pwrpriv->rf_pwrstate == rf_on) + { + if(padapter->net_closed == _TRUE) + pwrpriv->ps_flag = _TRUE; + + rfpwrstate = RfOnOffDetect(padapter); + DBG_871X("@@@@- #1 %s==> rfstate:%s \n",__FUNCTION__,(rfpwrstate==rf_on)?"rf_on":"rf_off"); + if(rfpwrstate!= pwrpriv->rf_pwrstate) + { + if(rfpwrstate == rf_off) + { + pwrpriv->change_rfpwrstate = rf_off; + + pwrpriv->bkeepfwalive = _TRUE; + pwrpriv->brfoffbyhw = _TRUE; + + autosuspend_enter(padapter); + } + } + } + } + else + #endif //CONFIG_AUTOSUSPEND + { + rfpwrstate = RfOnOffDetect(padapter); + DBG_871X("@@@@- #2 %s==> rfstate:%s \n",__FUNCTION__,(rfpwrstate==rf_on)?"rf_on":"rf_off"); + + if(rfpwrstate!= pwrpriv->rf_pwrstate) + { + if(rfpwrstate == rf_off) + { + pwrpriv->change_rfpwrstate = rf_off; + pwrpriv->brfoffbyhw = _TRUE; + rtw_hw_suspend(padapter ); + } + else + { + pwrpriv->change_rfpwrstate = rf_on; + rtw_hw_resume(padapter ); + } + DBG_871X("current rf_pwrstate(%s)\n",(pwrpriv->rf_pwrstate == rf_off)?"rf_off":"rf_on"); + } + } + pwrpriv->pwr_state_check_cnts ++; + } +#endif //SUPPORT_HW_RFOFF_DETECTED + + if (pwrpriv->ips_mode_req == IPS_NONE) + goto exit; + + if (rtw_pwr_unassociated_idle(padapter) == _FALSE) + goto exit; + + if((pwrpriv->rf_pwrstate == rf_on) && ((pwrpriv->pwr_state_check_cnts%4)==0)) + { + DBG_871X("==>%s .fw_state(%x)\n",__FUNCTION__,get_fwstate(pmlmepriv)); + #if defined (CONFIG_BT_COEXIST)&& defined (CONFIG_AUTOSUSPEND) + #else + pwrpriv->change_rfpwrstate = rf_off; + #endif + #ifdef CONFIG_AUTOSUSPEND + if(padapter->registrypriv.usbss_enable) + { + if(pwrpriv->bHWPwrPindetect) + pwrpriv->bkeepfwalive = _TRUE; + + if(padapter->net_closed == _TRUE) + pwrpriv->ps_flag = _TRUE; + + #if defined (CONFIG_BT_COEXIST)&& defined (CONFIG_AUTOSUSPEND) + if (_TRUE==pwrpriv->bInternalAutoSuspend) { + DBG_871X("<==%s .pwrpriv->bInternalAutoSuspend)(%x)\n",__FUNCTION__,pwrpriv->bInternalAutoSuspend); + } else { + pwrpriv->change_rfpwrstate = rf_off; + DBG_871X("<==%s .pwrpriv->bInternalAutoSuspend)(%x) call autosuspend_enter\n",__FUNCTION__,pwrpriv->bInternalAutoSuspend); + autosuspend_enter(padapter); + } + #else + autosuspend_enter(padapter); + #endif //if defined (CONFIG_BT_COEXIST)&& defined (CONFIG_AUTOSUSPEND) + } + else if(pwrpriv->bHWPwrPindetect) + { + } + else + #endif //CONFIG_AUTOSUSPEND + { + #if defined (CONFIG_BT_COEXIST)&& defined (CONFIG_AUTOSUSPEND) + pwrpriv->change_rfpwrstate = rf_off; + #endif //defined (CONFIG_BT_COEXIST)&& defined (CONFIG_AUTOSUSPEND) + + #ifdef CONFIG_IPS + ips_enter(padapter); + #endif + } + } +exit: +#ifndef CONFIG_IPS_CHECK_IN_WD + rtw_set_pwr_state_check_timer(pwrpriv); +#endif + pwrpriv->ps_processing = _FALSE; + return; +} + +void pwr_state_check_handler(RTW_TIMER_HDL_ARGS); +void pwr_state_check_handler(RTW_TIMER_HDL_ARGS) +{ + _adapter *padapter = (_adapter *)FunctionContext; + rtw_ps_cmd(padapter); +} + +#ifdef CONFIG_LPS +void traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets) +{ +#ifdef CONFIG_CHECK_LEAVE_LPS + static u32 start_time = 0; + static u32 xmit_cnt = 0; + u8 bLeaveLPS = _FALSE; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + + + if(tx) //from tx + { + xmit_cnt += tx_packets; + + if (start_time== 0) + start_time= rtw_get_current_time(); + + if (rtw_get_passing_time_ms(start_time) > 2000) // 2 sec == watch dog timer + { + if(xmit_cnt > 8) + { + if ((adapter_to_pwrctl(padapter)->bLeisurePs) + && (adapter_to_pwrctl(padapter)->pwr_mode != PS_MODE_ACTIVE) +#ifdef CONFIG_BT_COEXIST + && (rtw_btcoex_IsBtControlLps(padapter) == _FALSE) +#endif + ) + { + //DBG_871X("leave lps via Tx = %d\n", xmit_cnt); + bLeaveLPS = _TRUE; + } + } + + start_time= rtw_get_current_time(); + xmit_cnt = 0; + } + + } + else // from rx path + { + if(pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod > 4/*2*/) + { + if ((adapter_to_pwrctl(padapter)->bLeisurePs) + && (adapter_to_pwrctl(padapter)->pwr_mode != PS_MODE_ACTIVE) +#ifdef CONFIG_BT_COEXIST + && (rtw_btcoex_IsBtControlLps(padapter) == _FALSE) +#endif + ) + { + //DBG_871X("leave lps via Rx = %d\n", pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod); + bLeaveLPS = _TRUE; + } + } + } + + if(bLeaveLPS) + { + //DBG_871X("leave lps via %s, Tx = %d, Rx = %d \n", tx?"Tx":"Rx", pmlmepriv->LinkDetectInfo.NumTxOkInPeriod,pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod); + //rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 1); + rtw_lps_ctrl_wk_cmd(padapter, tx?LPS_CTRL_TX_TRAFFIC_LEAVE:LPS_CTRL_RX_TRAFFIC_LEAVE, tx?0:1); + } +#endif //CONFIG_CHECK_LEAVE_LPS +} + +/* + * Description: + * This function MUST be called under power lock protect + * + * Parameters + * padapter + * pslv power state level, only could be PS_STATE_S0 ~ PS_STATE_S4 + * + */ +void rtw_set_rpwm(PADAPTER padapter, u8 pslv) +{ + u8 rpwm; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); +#ifdef CONFIG_DETECT_CPWM_BY_POLLING + u8 cpwm_orig; +#endif // CONFIG_DETECT_CPWM_BY_POLLING + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; +_func_enter_; + + pslv = PS_STATE(pslv); + +#ifdef CONFIG_LPS_RPWM_TIMER + if (pwrpriv->brpwmtimeout == _TRUE) + { + DBG_871X("%s: RPWM timeout, force to set RPWM(0x%02X) again!\n", __FUNCTION__, pslv); + } + else +#endif // CONFIG_LPS_RPWM_TIMER + { + if ( (pwrpriv->rpwm == pslv) +#ifdef CONFIG_LPS_LCLK + || ((pwrpriv->rpwm >= PS_STATE_S2)&&(pslv >= PS_STATE_S2)) +#endif + ) + { + RT_TRACE(_module_rtl871x_pwrctrl_c_,_drv_err_, + ("%s: Already set rpwm[0x%02X], new=0x%02X!\n", __FUNCTION__, pwrpriv->rpwm, pslv)); + return; + } + } + + if (rtw_is_surprise_removed(padapter) || + (!rtw_is_hw_init_completed(padapter))) + { + RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_, + ("%s: SurpriseRemoved(%s) hw_init_completed(%s)\n" + , __func__ + , rtw_is_surprise_removed(padapter)?"True":"False" + , rtw_is_hw_init_completed(padapter)?"True":"False")); + + pwrpriv->cpwm = PS_STATE_S4; + + return; + } + + if (rtw_is_drv_stopped(padapter)) { + RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_, + ("%s: change power state(0x%02X) when DriverStopped\n", __FUNCTION__, pslv)); + + if (pslv < PS_STATE_S2) { + RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_, + ("%s: Reject to enter PS_STATE(0x%02X) lower than S2 when DriverStopped!!\n", __FUNCTION__, pslv)); + return; + } + } + + rpwm = pslv | pwrpriv->tog; +#ifdef CONFIG_LPS_LCLK + // only when from PS_STATE S0/S1 to S2 and higher needs ACK + if ((pwrpriv->cpwm < PS_STATE_S2) && (pslv >= PS_STATE_S2)) + rpwm |= PS_ACK; +#endif + RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, + ("rtw_set_rpwm: rpwm=0x%02x cpwm=0x%02x\n", rpwm, pwrpriv->cpwm)); + + pwrpriv->rpwm = pslv; + +#ifdef CONFIG_DETECT_CPWM_BY_POLLING + cpwm_orig = 0; + if (rpwm & PS_ACK) + { + rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig); + } +#endif + +#if defined(CONFIG_LPS_RPWM_TIMER) && !defined(CONFIG_DETECT_CPWM_BY_POLLING) + if (rpwm & PS_ACK) + _set_timer(&pwrpriv->pwr_rpwm_timer, LPS_RPWM_WAIT_MS); +#endif // CONFIG_LPS_RPWM_TIMER & !CONFIG_DETECT_CPWM_BY_POLLING + rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm)); + + pwrpriv->tog += 0x80; + +#ifdef CONFIG_LPS_LCLK + // No LPS 32K, No Ack + if (rpwm & PS_ACK) + { +#ifdef CONFIG_DETECT_CPWM_BY_POLLING + u32 start_time; + u8 cpwm_now; + u8 poll_cnt=0; + + start_time = rtw_get_current_time(); + + // polling cpwm + do { + rtw_msleep_os(1); + poll_cnt++; + cpwm_now = 0; + rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now); + if ((cpwm_orig ^ cpwm_now) & 0x80) + { + pwrpriv->cpwm = PS_STATE_S4; + pwrpriv->cpwm_tog = cpwm_now & PS_TOGGLE; +#ifdef DBG_CHECK_FW_PS_STATE + DBG_871X("%s: polling cpwm OK! poll_cnt=%d, cpwm_orig=%02x, cpwm_now=%02x , 0x100=0x%x\n" + , __FUNCTION__,poll_cnt, cpwm_orig, cpwm_now, rtw_read8(padapter, REG_CR)); + if(rtw_fw_ps_state(padapter) == _FAIL) + { + DBG_871X("leave 32k but fw state in 32k\n"); + pdbgpriv->dbg_rpwm_toogle_cnt++; + } +#endif //DBG_CHECK_FW_PS_STATE + break; + } + + if (rtw_get_passing_time_ms(start_time) > LPS_RPWM_WAIT_MS) + { + DBG_871X("%s: polling cpwm timeout! poll_cnt=%d, cpwm_orig=%02x, cpwm_now=%02x \n", __FUNCTION__,poll_cnt, cpwm_orig, cpwm_now); +#ifdef DBG_CHECK_FW_PS_STATE + if(rtw_fw_ps_state(padapter) == _FAIL) + { + DBG_871X("rpwm timeout and fw ps state in 32k\n"); + pdbgpriv->dbg_rpwm_timeout_fail_cnt++; + } +#endif //DBG_CHECK_FW_PS_STATE +#ifdef CONFIG_LPS_RPWM_TIMER + _set_timer(&pwrpriv->pwr_rpwm_timer, 1); +#endif // CONFIG_LPS_RPWM_TIMER + break; + } + } while (1); +#endif // CONFIG_DETECT_CPWM_BY_POLLING + } + else +#endif // CONFIG_LPS_LCLK + { + pwrpriv->cpwm = pslv; + } + +_func_exit_; +} + +u8 PS_RDY_CHECK(_adapter * padapter) +{ + u32 curr_time, delta_time; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); +#ifdef CONFIG_IOCTL_CFG80211 + struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo; +#endif /* CONFIG_IOCTL_CFG80211 */ +#endif /* CONFIG_P2P */ + + if(_TRUE == pwrpriv->bInSuspend ) + return _FALSE; + + curr_time = rtw_get_current_time(); + + delta_time = curr_time -pwrpriv->DelayLPSLastTimeStamp; + + if(delta_time < LPS_DELAY_TIME) + { + return _FALSE; + } + + if (check_fwstate(pmlmepriv, WIFI_SITE_MONITOR) + || check_fwstate(pmlmepriv, WIFI_UNDER_LINKING|WIFI_UNDER_WPS) + || check_fwstate(pmlmepriv, WIFI_AP_STATE) + || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE|WIFI_ADHOC_STATE) + #if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) + || pcfg80211_wdinfo->is_ro_ch + #endif + || rtw_is_scan_deny(padapter) +#ifdef CONFIG_TDLS + // TDLS link is established. + || ( padapter->tdlsinfo.link_established == _TRUE ) +#endif // CONFIG_TDLS + ) + return _FALSE; + + if( (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) && (padapter->securitypriv.binstallGrpkey == _FALSE) ) + { + DBG_871X("Group handshake still in progress !!!\n"); + return _FALSE; + } + +#ifdef CONFIG_IOCTL_CFG80211 + if (!rtw_cfg80211_pwr_mgmt(padapter)) + return _FALSE; +#endif + + return _TRUE; +} + +#if defined(CONFIG_FWLPS_IN_IPS) +void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + int cnt=0; + u32 start_time; + u8 val8 = 0; + u8 cpwm_orig = 0, cpwm_now = 0; + u8 parm[H2C_INACTIVE_PS_LEN]={0}; + + if (padapter->netif_up == _FALSE) { + DBG_871X("%s: ERROR, netif is down\n", __func__); + return; + } + + //u8 cmd_param; //BIT0:enable, BIT1:NoConnect32k + if (enable) { +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_IpsNotify(padapter, pwrpriv->ips_mode_req); +#endif + //Enter IPS + DBG_871X("%s: issue H2C to FW when entering IPS\n", __func__); + +#ifdef CONFIG_PNO_SUPPORT + parm[0] = 0x03; + parm[1] = pwrpriv->pnlo_info->fast_scan_iterations; + parm[2] = pwrpriv->pnlo_info->slow_scan_period; +#else + parm[0] = 0x03; + parm[1] = 0x0; + parm[2] = 0x0; +#endif//CONFIG_PNO_SUPPORT + + rtw_hal_fill_h2c_cmd(padapter, //H2C_FWLPS_IN_IPS_, + H2C_INACTIVE_PS_, + H2C_INACTIVE_PS_LEN, parm); + //poll 0x1cc to make sure H2C command already finished by FW; MAC_0x1cc=0 means H2C done by FW. + do{ + val8 = rtw_read8(padapter, REG_HMETFR); + cnt++; + DBG_871X("%s polling REG_HMETFR=0x%x, cnt=%d \n", + __func__, val8, cnt); + rtw_mdelay_os(10); + }while(cnt<100 && (val8!=0)); + + //H2C done, enter 32k + if (val8 == 0) { + //ser rpwm to enter 32k + val8 = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1); + DBG_871X("%s: read rpwm=%02x\n", __FUNCTION__, val8); + val8 += 0x80; + val8 |= BIT(0); + rtw_write8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1, val8); + DBG_871X("%s: write rpwm=%02x\n", __FUNCTION__, val8); + adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80; + cnt = val8 = 0; + if (parm[1] == 0 || parm[2] == 0) { + do { + val8 = rtw_read8(padapter, REG_CR); + cnt++; + DBG_871X("%s polling 0x100=0x%x, cnt=%d \n", + __func__, val8, cnt); + DBG_871X("%s 0x08:%02x, 0x03:%02x\n", + __func__, + rtw_read8(padapter, 0x08), + rtw_read8(padapter, 0x03)); + rtw_mdelay_os(10); + } while(cnt<20 && (val8!=0xEA)); + } + } + } else { + //Leave IPS + DBG_871X("%s: Leaving IPS in FWLPS state\n", __func__); + + //for polling cpwm + cpwm_orig = 0; + rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig); + + //ser rpwm + val8 = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1); + val8 &= 0x80; + val8 += 0x80; + val8 |= BIT(6); + rtw_write8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1, val8); + DBG_871X("%s: write rpwm=%02x\n", __FUNCTION__, val8); + adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80; + + //do polling cpwm + start_time = rtw_get_current_time(); + do { + + rtw_mdelay_os(1); + + rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now); + if ((cpwm_orig ^ cpwm_now) & 0x80) { + break; + } + + if (rtw_get_passing_time_ms(start_time) > 100) + { + DBG_871X("%s: polling cpwm timeout when leaving IPS in FWLPS state\n", __FUNCTION__); + break; + } + } while (1); + + parm[0] = 0x0; + parm[1] = 0x0; + parm[2] = 0x0; + rtw_hal_fill_h2c_cmd(padapter, H2C_INACTIVE_PS_, + H2C_INACTIVE_PS_LEN, parm); +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_IpsNotify(padapter, IPS_NONE); +#endif + } +} +#endif //CONFIG_PNO_SUPPORT + +void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode, const char *msg) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); +#endif //CONFIG_P2P +#ifdef CONFIG_TDLS + struct sta_priv *pstapriv = &padapter->stapriv; + _irqL irqL; + int i, j; + _list *plist, *phead; + struct sta_info *ptdls_sta; +#endif //CONFIG_TDLS + +_func_enter_; + + RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, + ("%s: PowerMode=%d Smart_PS=%d\n", + __FUNCTION__, ps_mode, smart_ps)); + + if(ps_mode > PM_Card_Disable) { + RT_TRACE(_module_rtl871x_pwrctrl_c_,_drv_err_,("ps_mode:%d error\n", ps_mode)); + return; + } + + if (pwrpriv->pwr_mode == ps_mode) + { + if (PS_MODE_ACTIVE == ps_mode) return; + +#ifndef CONFIG_BT_COEXIST + if ((pwrpriv->smart_ps == smart_ps) && + (pwrpriv->bcn_ant_mode == bcn_ant_mode)) + { + return; + } +#endif // !CONFIG_BT_COEXIST + } + +#ifdef CONFIG_LPS_LCLK + _enter_pwrlock(&pwrpriv->lock); +#endif + + //if(pwrpriv->pwr_mode == PS_MODE_ACTIVE) + if(ps_mode == PS_MODE_ACTIVE) + { + if (1 +#ifdef CONFIG_BT_COEXIST + && (((rtw_btcoex_IsBtControlLps(padapter) == _FALSE) +#ifdef CONFIG_P2P_PS + && (pwdinfo->opp_ps == 0) +#endif // CONFIG_P2P_PS + ) + || ((rtw_btcoex_IsBtControlLps(padapter) == _TRUE) + && (rtw_btcoex_IsLpsOn(padapter) == _FALSE)) + ) +#else // !CONFIG_BT_COEXIST +#ifdef CONFIG_P2P_PS + && (pwdinfo->opp_ps == 0) +#endif // CONFIG_P2P_PS +#endif // !CONFIG_BT_COEXIST + ) + { + DBG_871X(FUNC_ADPT_FMT" Leave 802.11 power save - %s\n", + FUNC_ADPT_ARG(padapter), msg); + + if (pwrpriv->lps_leave_cnts < UINT_MAX) + pwrpriv->lps_leave_cnts++; + else + pwrpriv->lps_leave_cnts = 0; +#ifdef CONFIG_TDLS + for(i=0; i< NUM_STA; i++) + { + phead = &(pstapriv->sta_hash[i]); + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) + { + ptdls_sta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + + if( ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE ) + issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->hwaddr, 0, 0, 0); + plist = get_next(plist); + } + } +#endif //CONFIG_TDLS + + pwrpriv->pwr_mode = ps_mode; + rtw_set_rpwm(padapter, PS_STATE_S4); + + rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode)); + pwrpriv->bFwCurrentInPSMode = _FALSE; + +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_LpsNotify(padapter, ps_mode); +#endif // CONFIG_BT_COEXIST + } + } + else + { + if ((PS_RDY_CHECK(padapter) && check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE)) +#ifdef CONFIG_BT_COEXIST + || ((rtw_btcoex_IsBtControlLps(padapter) == _TRUE) + && (rtw_btcoex_IsLpsOn(padapter) == _TRUE)) +#endif + ) + { + u8 pslv; + + DBG_871X(FUNC_ADPT_FMT" Enter 802.11 power save - %s\n", + FUNC_ADPT_ARG(padapter), msg); + + if (pwrpriv->lps_enter_cnts < UINT_MAX) + pwrpriv->lps_enter_cnts++; + else + pwrpriv->lps_enter_cnts = 0; +#ifdef CONFIG_TDLS + for(i=0; i< NUM_STA; i++) + { + phead = &(pstapriv->sta_hash[i]); + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) + { + ptdls_sta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + + if( ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE ) + issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->hwaddr, 1, 0, 0); + plist = get_next(plist); + } + } +#endif //CONFIG_TDLS + +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_LpsNotify(padapter, ps_mode); +#endif // CONFIG_BT_COEXIST + + pwrpriv->bFwCurrentInPSMode = _TRUE; + pwrpriv->pwr_mode = ps_mode; + pwrpriv->smart_ps = smart_ps; + pwrpriv->bcn_ant_mode = bcn_ant_mode; + rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode)); + +#ifdef CONFIG_P2P_PS + // Set CTWindow after LPS + if(pwdinfo->opp_ps == 1) + p2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 0); +#endif //CONFIG_P2P_PS + + pslv = PS_STATE_S2; +#ifdef CONFIG_LPS_LCLK + if (pwrpriv->alives == 0) + pslv = PS_STATE_S0; +#endif // CONFIG_LPS_LCLK + +#ifdef CONFIG_BT_COEXIST + if ((rtw_btcoex_IsBtDisabled(padapter) == _FALSE) + && (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)) + { + u8 val8; + + val8 = rtw_btcoex_LpsVal(padapter); + if (val8 & BIT(4)) + pslv = PS_STATE_S2; + + } +#endif // CONFIG_BT_COEXIST + + rtw_set_rpwm(padapter, pslv); + } + } + +#ifdef CONFIG_LPS_LCLK + _exit_pwrlock(&pwrpriv->lock); +#endif + +_func_exit_; +} + +/* + * Return: + * 0: Leave OK + * -1: Timeout + * -2: Other error + */ +s32 LPS_RF_ON_check(PADAPTER padapter, u32 delay_ms) +{ + u32 start_time; + u8 bAwake = _FALSE; + s32 err = 0; + + + start_time = rtw_get_current_time(); + while (1) + { + rtw_hal_get_hwreg(padapter, HW_VAR_FWLPS_RF_ON, &bAwake); + if (_TRUE == bAwake) + break; + + if (rtw_is_surprise_removed(padapter)) { + err = -2; + DBG_871X("%s: device surprise removed!!\n", __FUNCTION__); + break; + } + + if (rtw_get_passing_time_ms(start_time) > delay_ms) + { + err = -1; + DBG_871X("%s: Wait for FW LPS leave more than %u ms!!!\n", __FUNCTION__, delay_ms); + break; + } + rtw_usleep_os(100); + } + + return err; +} + +// +// Description: +// Enter the leisure power save mode. +// +void LPS_Enter(PADAPTER padapter, const char *msg) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + _adapter *buddy = padapter->pbuddy_adapter; + int n_assoc_iface = 0; + int i; + char buf[32] = {0}; + +_func_enter_; + +// DBG_871X("+LeisurePSEnter\n"); + +#ifdef CONFIG_BT_COEXIST + if (rtw_btcoex_IsBtControlLps(padapter) == _TRUE) + return; +#endif + + /* Skip lps enter request if number of assocated adapters is not 1 */ + for (i = 0; i < dvobj->iface_nums; i++) { + if (check_fwstate(&(dvobj->padapters[i]->mlmepriv), WIFI_ASOC_STATE)) + n_assoc_iface++; + } + if (n_assoc_iface != 1) + return; + + /* Skip lps enter request for adapter not port0 */ + if (get_iface_type(padapter) != IFACE_PORT0) + return; + + for (i = 0; i < dvobj->iface_nums; i++) { + if (PS_RDY_CHECK(dvobj->padapters[i]) == _FALSE) + return; + } + +#ifdef CONFIG_P2P_PS + if(padapter->wdinfo.p2p_ps_mode == P2P_PS_NOA) + { + return;//supporting p2p client ps NOA via H2C_8723B_P2P_PS_OFFLOAD + } +#endif //CONFIG_P2P_PS + + if (pwrpriv->bLeisurePs) + { + // Idle for a while if we connect to AP a while ago. + if (pwrpriv->LpsIdleCount >= 2) // 4 Sec + { + if(pwrpriv->pwr_mode == PS_MODE_ACTIVE) + { + sprintf(buf, "WIFI-%s", msg); + pwrpriv->bpower_saving = _TRUE; + rtw_set_ps_mode(padapter, pwrpriv->power_mgnt, padapter->registrypriv.smart_ps, 0, buf); + } + } + else + pwrpriv->LpsIdleCount++; + } + +// DBG_871X("-LeisurePSEnter\n"); + +_func_exit_; +} + +// +// Description: +// Leave the leisure power save mode. +// +void LPS_Leave(PADAPTER padapter, const char *msg) +{ +#define LPS_LEAVE_TIMEOUT_MS 100 + + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); + u32 start_time; + u8 bAwake = _FALSE; + char buf[32] = {0}; + struct debug_priv *pdbgpriv = &dvobj->drv_dbg; + +_func_enter_; + +// DBG_871X("+LeisurePSLeave\n"); + +#ifdef CONFIG_BT_COEXIST + if (rtw_btcoex_IsBtControlLps(padapter) == _TRUE) + return; +#endif + + if (pwrpriv->bLeisurePs) + { + if(pwrpriv->pwr_mode != PS_MODE_ACTIVE) + { + sprintf(buf, "WIFI-%s", msg); + rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, buf); + + if(pwrpriv->pwr_mode == PS_MODE_ACTIVE) + LPS_RF_ON_check(padapter, LPS_LEAVE_TIMEOUT_MS); + } + } + + pwrpriv->bpower_saving = _FALSE; +#ifdef DBG_CHECK_FW_PS_STATE + if(rtw_fw_ps_state(padapter) == _FAIL) + { + DBG_871X("leave lps, fw in 32k\n"); + pdbgpriv->dbg_leave_lps_fail_cnt++; + } +#endif //DBG_CHECK_FW_PS_STATE +// DBG_871X("-LeisurePSLeave\n"); + +_func_exit_; +} +#endif + +void LeaveAllPowerSaveModeDirect(PADAPTER Adapter) +{ + PADAPTER pri_padapter = GET_PRIMARY_ADAPTER(Adapter); + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(Adapter); + struct dvobj_priv *psdpriv = Adapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; +#ifndef CONFIG_DETECT_CPWM_BY_POLLING + u8 cpwm_orig, cpwm_now; + u32 start_time; +#endif // CONFIG_DETECT_CPWM_BY_POLLING + +_func_enter_; + + DBG_871X("%s.....\n",__FUNCTION__); + + if (rtw_is_surprise_removed(Adapter)) { + DBG_871X(FUNC_ADPT_FMT ": bSurpriseRemoved=_TRUE Skip!\n", FUNC_ADPT_ARG(Adapter)); + return; + } + + if ((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) +#ifdef CONFIG_CONCURRENT_MODE + || (check_buddy_fwstate(Adapter,_FW_LINKED) == _TRUE) +#endif + ) + { //connect + + if(pwrpriv->pwr_mode == PS_MODE_ACTIVE) { + DBG_871X("%s: Driver Already Leave LPS\n",__FUNCTION__); + return; + } + +#ifdef CONFIG_LPS_LCLK + _enter_pwrlock(&pwrpriv->lock); + +#ifndef CONFIG_DETECT_CPWM_BY_POLLING + cpwm_orig = 0; + rtw_hal_get_hwreg(Adapter, HW_VAR_CPWM, &cpwm_orig); +#endif //CONFIG_DETECT_CPWM_BY_POLLING + rtw_set_rpwm(Adapter, PS_STATE_S4); + +#ifndef CONFIG_DETECT_CPWM_BY_POLLING + + start_time = rtw_get_current_time(); + + // polling cpwm + do { + rtw_mdelay_os(1); + + rtw_hal_get_hwreg(Adapter, HW_VAR_CPWM, &cpwm_now); + if ((cpwm_orig ^ cpwm_now) & 0x80) + { + pwrpriv->cpwm = PS_STATE_S4; + pwrpriv->cpwm_tog = cpwm_now & PS_TOGGLE; +#ifdef DBG_CHECK_FW_PS_STATE + DBG_871X("%s: polling cpwm OK! cpwm_orig=%02x, cpwm_now=%02x, 0x100=0x%x \n" + , __FUNCTION__, cpwm_orig, cpwm_now, rtw_read8(Adapter, REG_CR)); + if(rtw_fw_ps_state(Adapter) == _FAIL) + { + DBG_871X("%s: leave 32k but fw state in 32k\n", __FUNCTION__); + pdbgpriv->dbg_rpwm_toogle_cnt++; + } +#endif //DBG_CHECK_FW_PS_STATE + break; + } + + if (rtw_get_passing_time_ms(start_time) > LPS_RPWM_WAIT_MS) + { + DBG_871X("%s: polling cpwm timeout! cpwm_orig=%02x, cpwm_now=%02x \n", __FUNCTION__, cpwm_orig, cpwm_now); +#ifdef DBG_CHECK_FW_PS_STATE + if(rtw_fw_ps_state(Adapter) == _FAIL) + { + DBG_871X("rpwm timeout and fw ps state in 32k\n"); + pdbgpriv->dbg_rpwm_timeout_fail_cnt++; + } +#endif //DBG_CHECK_FW_PS_STATE + break; + } + } while (1); +#endif // CONFIG_DETECT_CPWM_BY_POLLING + + _exit_pwrlock(&pwrpriv->lock); +#endif + +#ifdef CONFIG_P2P_PS + p2p_ps_wk_cmd(pri_padapter, P2P_PS_DISABLE, 0); +#endif //CONFIG_P2P_PS + +#ifdef CONFIG_LPS + rtw_lps_ctrl_wk_cmd(pri_padapter, LPS_CTRL_LEAVE, 0); +#endif + } + else + { + if(pwrpriv->rf_pwrstate== rf_off) + { + #ifdef CONFIG_AUTOSUSPEND + if(Adapter->registrypriv.usbss_enable) + { + #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) + usb_disable_autosuspend(adapter_to_dvobj(Adapter)->pusbdev); + #elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,22) && LINUX_VERSION_CODE<=KERNEL_VERSION(2,6,34)) + adapter_to_dvobj(Adapter)->pusbdev->autosuspend_disabled = Adapter->bDisableAutosuspend;//autosuspend disabled by the user + #endif + } + else + #endif + { +#if defined(CONFIG_FWLPS_IN_IPS) || defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_RTL8188E) + #ifdef CONFIG_IPS + if(_FALSE == ips_leave(pri_padapter)) + { + DBG_871X("======> ips_leave fail.............\n"); + } + #endif +#endif //CONFIG_SWLPS_IN_IPS || (CONFIG_PLATFORM_SPRD && CONFIG_RTL8188E) + } + } + } + +_func_exit_; +} + +// +// Description: Leave all power save mode: LPS, FwLPS, IPS if needed. +// Move code to function by tynli. 2010.03.26. +// +void LeaveAllPowerSaveMode(IN PADAPTER Adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(Adapter); + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + u8 enqueue = 0; + int n_assoc_iface = 0; + int i; + +_func_enter_; + + //DBG_871X("%s.....\n",__FUNCTION__); + + if (_FALSE == Adapter->bup) + { + DBG_871X(FUNC_ADPT_FMT ": bup=%d Skip!\n", + FUNC_ADPT_ARG(Adapter), Adapter->bup); + return; + } + + if (rtw_is_surprise_removed(Adapter)) { + DBG_871X(FUNC_ADPT_FMT ": bSurpriseRemoved=_TRUE Skip!\n", FUNC_ADPT_ARG(Adapter)); + return; + } + + for (i = 0; i < dvobj->iface_nums; i++) { + if (check_fwstate(&(dvobj->padapters[i]->mlmepriv), WIFI_ASOC_STATE)) + n_assoc_iface++; + } + + if (n_assoc_iface) + { //connect +#ifdef CONFIG_LPS_LCLK + enqueue = 1; +#endif + +#ifdef CONFIG_P2P_PS + p2p_ps_wk_cmd(Adapter, P2P_PS_DISABLE, enqueue); +#endif //CONFIG_P2P_PS + +#ifdef CONFIG_LPS + rtw_lps_ctrl_wk_cmd(Adapter, LPS_CTRL_LEAVE, enqueue); +#endif + +#ifdef CONFIG_LPS_LCLK + LPS_Leave_check(Adapter); +#endif + } + else + { + if(adapter_to_pwrctl(Adapter)->rf_pwrstate== rf_off) + { + #ifdef CONFIG_AUTOSUSPEND + if(Adapter->registrypriv.usbss_enable) + { + #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) + usb_disable_autosuspend(adapter_to_dvobj(Adapter)->pusbdev); + #elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,22) && LINUX_VERSION_CODE<=KERNEL_VERSION(2,6,34)) + adapter_to_dvobj(Adapter)->pusbdev->autosuspend_disabled = Adapter->bDisableAutosuspend;//autosuspend disabled by the user + #endif + } + else + #endif + { +#if defined(CONFIG_FWLPS_IN_IPS) || defined(CONFIG_SWLPS_IN_IPS) || (defined(CONFIG_PLATFORM_SPRD) && defined(CONFIG_RTL8188E)) + #ifdef CONFIG_IPS + if(_FALSE == ips_leave(Adapter)) + { + DBG_871X("======> ips_leave fail.............\n"); + } + #endif +#endif //CONFIG_SWLPS_IN_IPS || (CONFIG_PLATFORM_SPRD && CONFIG_RTL8188E) + } + } + } + +_func_exit_; +} + +#ifdef CONFIG_LPS_LCLK +void LPS_Leave_check( + PADAPTER padapter) +{ + struct pwrctrl_priv *pwrpriv; + u32 start_time; + u8 bReady; + +_func_enter_; + + pwrpriv = adapter_to_pwrctl(padapter); + + bReady = _FALSE; + start_time = rtw_get_current_time(); + + rtw_yield_os(); + + while(1) + { + _enter_pwrlock(&pwrpriv->lock); + + if (rtw_is_surprise_removed(padapter) + || (!rtw_is_hw_init_completed(padapter)) +#ifdef CONFIG_USB_HCI + || rtw_is_drv_stopped(padapter) +#endif + || (pwrpriv->pwr_mode == PS_MODE_ACTIVE) + ) + { + bReady = _TRUE; + } + + _exit_pwrlock(&pwrpriv->lock); + + if(_TRUE == bReady) + break; + + if(rtw_get_passing_time_ms(start_time)>100) + { + DBG_871X("Wait for cpwm event than 100 ms!!!\n"); + break; + } + rtw_msleep_os(1); + } + +_func_exit_; +} + +/* + * Caller:ISR handler... + * + * This will be called when CPWM interrupt is up. + * + * using to update cpwn of drv; and drv willl make a decision to up or down pwr level + */ +void cpwm_int_hdl( + PADAPTER padapter, + struct reportpwrstate_parm *preportpwrstate) +{ + struct pwrctrl_priv *pwrpriv; + +_func_enter_; + + pwrpriv = adapter_to_pwrctl(padapter); +#if 0 + if (pwrpriv->cpwm_tog == (preportpwrstate->state & PS_TOGGLE)) { + RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_err_, + ("cpwm_int_hdl: tog(old)=0x%02x cpwm(new)=0x%02x toggle bit didn't change!?\n", + pwrpriv->cpwm_tog, preportpwrstate->state)); + goto exit; + } +#endif + + _enter_pwrlock(&pwrpriv->lock); + +#ifdef CONFIG_LPS_RPWM_TIMER + if (pwrpriv->rpwm < PS_STATE_S2) + { + DBG_871X("%s: Redundant CPWM Int. RPWM=0x%02X CPWM=0x%02x\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm); + _exit_pwrlock(&pwrpriv->lock); + goto exit; + } +#endif // CONFIG_LPS_RPWM_TIMER + + pwrpriv->cpwm = PS_STATE(preportpwrstate->state); + pwrpriv->cpwm_tog = preportpwrstate->state & PS_TOGGLE; + + if (pwrpriv->cpwm >= PS_STATE_S2) + { + if (pwrpriv->alives & CMD_ALIVE) + _rtw_up_sema(&padapter->cmdpriv.cmd_queue_sema); + + if (pwrpriv->alives & XMIT_ALIVE) + _rtw_up_sema(&padapter->xmitpriv.xmit_sema); + } + + _exit_pwrlock(&pwrpriv->lock); + +exit: + RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, + ("cpwm_int_hdl: cpwm=0x%02x\n", pwrpriv->cpwm)); + +_func_exit_; +} + +static void cpwm_event_callback(struct work_struct *work) +{ + struct pwrctrl_priv *pwrpriv = container_of(work, struct pwrctrl_priv, cpwm_event); + struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv); + _adapter *adapter = dvobj->padapters[IFACE_ID0]; + struct reportpwrstate_parm report; + + //DBG_871X("%s\n",__FUNCTION__); + + report.state = PS_STATE_S2; + cpwm_int_hdl(adapter, &report); +} + +#ifdef CONFIG_LPS_RPWM_TIMER +static void rpwmtimeout_workitem_callback(struct work_struct *work) +{ + PADAPTER padapter; + struct dvobj_priv *dvobj; + struct pwrctrl_priv *pwrpriv; + + + pwrpriv = container_of(work, struct pwrctrl_priv, rpwmtimeoutwi); + dvobj = pwrctl_to_dvobj(pwrpriv); + padapter = dvobj->padapters[IFACE_ID0]; +// DBG_871X("+%s: rpwm=0x%02X cpwm=0x%02X\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm); + + _enter_pwrlock(&pwrpriv->lock); + if ((pwrpriv->rpwm == pwrpriv->cpwm) || (pwrpriv->cpwm >= PS_STATE_S2)) + { + DBG_871X("%s: rpwm=0x%02X cpwm=0x%02X CPWM done!\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm); + goto exit; + } + _exit_pwrlock(&pwrpriv->lock); + + if (rtw_read8(padapter, 0x100) != 0xEA) + { +#if 1 + struct reportpwrstate_parm report; + + report.state = PS_STATE_S2; + DBG_871X("\n%s: FW already leave 32K!\n\n", __func__); + cpwm_int_hdl(padapter, &report); +#else + DBG_871X("\n%s: FW already leave 32K!\n\n", __func__); + cpwm_event_callback(&pwrpriv->cpwm_event); +#endif + return; + } + + _enter_pwrlock(&pwrpriv->lock); + + if ((pwrpriv->rpwm == pwrpriv->cpwm) || (pwrpriv->cpwm >= PS_STATE_S2)) + { + DBG_871X("%s: cpwm=%d, nothing to do!\n", __func__, pwrpriv->cpwm); + goto exit; + } + pwrpriv->brpwmtimeout = _TRUE; + rtw_set_rpwm(padapter, pwrpriv->rpwm); + pwrpriv->brpwmtimeout = _FALSE; + +exit: + _exit_pwrlock(&pwrpriv->lock); +} + +/* + * This function is a timer handler, can't do any IO in it. + */ +static void pwr_rpwm_timeout_handler(void *FunctionContext) +{ + PADAPTER padapter; + struct pwrctrl_priv *pwrpriv; + + + padapter = (PADAPTER)FunctionContext; + pwrpriv = adapter_to_pwrctl(padapter); + DBG_871X("+%s: rpwm=0x%02X cpwm=0x%02X\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm); + + if ((pwrpriv->rpwm == pwrpriv->cpwm) || (pwrpriv->cpwm >= PS_STATE_S2)) + { + DBG_871X("+%s: cpwm=%d, nothing to do!\n", __func__, pwrpriv->cpwm); + return; + } + + _set_workitem(&pwrpriv->rpwmtimeoutwi); +} +#endif // CONFIG_LPS_RPWM_TIMER + +__inline static void register_task_alive(struct pwrctrl_priv *pwrctrl, u32 tag) +{ + pwrctrl->alives |= tag; +} + +__inline static void unregister_task_alive(struct pwrctrl_priv *pwrctrl, u32 tag) +{ + pwrctrl->alives &= ~tag; +} + + +/* + * Description: + * Check if the fw_pwrstate is okay for I/O. + * If not (cpwm is less than S2), then the sub-routine + * will raise the cpwm to be greater than or equal to S2. + * + * Calling Context: Passive + * + * Constraint: + * 1. this function will request pwrctrl->lock + * + * Return Value: + * _SUCCESS hardware is ready for I/O + * _FAIL can't I/O right now + */ +s32 rtw_register_task_alive(PADAPTER padapter, u32 task) +{ + s32 res; + struct pwrctrl_priv *pwrctrl; + u8 pslv; + +_func_enter_; + + res = _SUCCESS; + pwrctrl = adapter_to_pwrctl(padapter); + pslv = PS_STATE_S2; + + _enter_pwrlock(&pwrctrl->lock); + + register_task_alive(pwrctrl, task); + + if (pwrctrl->bFwCurrentInPSMode == _TRUE) + { + RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, + ("%s: task=0x%x cpwm=0x%02x alives=0x%08x\n", + __FUNCTION__, task, pwrctrl->cpwm, pwrctrl->alives)); + + if (pwrctrl->cpwm < pslv) + { + if (pwrctrl->cpwm < PS_STATE_S2) + res = _FAIL; + if (pwrctrl->rpwm < pslv) + rtw_set_rpwm(padapter, pslv); + } + } + + _exit_pwrlock(&pwrctrl->lock); + +#ifdef CONFIG_DETECT_CPWM_BY_POLLING + if (_FAIL == res) + { + if (pwrctrl->cpwm >= PS_STATE_S2) + res = _SUCCESS; + } +#endif // CONFIG_DETECT_CPWM_BY_POLLING + +_func_exit_; + + return res; +} + +/* + * Description: + * If task is done, call this func. to power down firmware again. + * + * Constraint: + * 1. this function will request pwrctrl->lock + * + * Return Value: + * none + */ +void rtw_unregister_task_alive(PADAPTER padapter, u32 task) +{ + struct pwrctrl_priv *pwrctrl; + u8 pslv; + +_func_enter_; + + pwrctrl = adapter_to_pwrctl(padapter); + pslv = PS_STATE_S0; + +#ifdef CONFIG_BT_COEXIST + if ((rtw_btcoex_IsBtDisabled(padapter) == _FALSE) + && (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)) + { + u8 val8; + + val8 = rtw_btcoex_LpsVal(padapter); + if (val8 & BIT(4)) + pslv = PS_STATE_S2; + + } +#endif // CONFIG_BT_COEXIST + + _enter_pwrlock(&pwrctrl->lock); + + unregister_task_alive(pwrctrl, task); + + if ((pwrctrl->pwr_mode != PS_MODE_ACTIVE) + && (pwrctrl->bFwCurrentInPSMode == _TRUE)) + { + RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, + ("%s: cpwm=0x%02x alives=0x%08x\n", + __FUNCTION__, pwrctrl->cpwm, pwrctrl->alives)); + + if (pwrctrl->cpwm > pslv) + { + if ((pslv >= PS_STATE_S2) || (pwrctrl->alives == 0)) + rtw_set_rpwm(padapter, pslv); + } + } + + _exit_pwrlock(&pwrctrl->lock); + +_func_exit_; +} + +/* + * Caller: rtw_xmit_thread + * + * Check if the fw_pwrstate is okay for xmit. + * If not (cpwm is less than S3), then the sub-routine + * will raise the cpwm to be greater than or equal to S3. + * + * Calling Context: Passive + * + * Return Value: + * _SUCCESS rtw_xmit_thread can write fifo/txcmd afterwards. + * _FAIL rtw_xmit_thread can not do anything. + */ +s32 rtw_register_tx_alive(PADAPTER padapter) +{ + s32 res; + struct pwrctrl_priv *pwrctrl; + u8 pslv; + +_func_enter_; + + res = _SUCCESS; + pwrctrl = adapter_to_pwrctl(padapter); + pslv = PS_STATE_S2; + + _enter_pwrlock(&pwrctrl->lock); + + register_task_alive(pwrctrl, XMIT_ALIVE); + + if (pwrctrl->bFwCurrentInPSMode == _TRUE) + { + RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, + ("rtw_register_tx_alive: cpwm=0x%02x alives=0x%08x\n", + pwrctrl->cpwm, pwrctrl->alives)); + + if (pwrctrl->cpwm < pslv) + { + if (pwrctrl->cpwm < PS_STATE_S2) + res = _FAIL; + if (pwrctrl->rpwm < pslv) + rtw_set_rpwm(padapter, pslv); + } + } + + _exit_pwrlock(&pwrctrl->lock); + +#ifdef CONFIG_DETECT_CPWM_BY_POLLING + if (_FAIL == res) + { + if (pwrctrl->cpwm >= PS_STATE_S2) + res = _SUCCESS; + } +#endif // CONFIG_DETECT_CPWM_BY_POLLING + +_func_exit_; + + return res; +} + +/* + * Caller: rtw_cmd_thread + * + * Check if the fw_pwrstate is okay for issuing cmd. + * If not (cpwm should be is less than S2), then the sub-routine + * will raise the cpwm to be greater than or equal to S2. + * + * Calling Context: Passive + * + * Return Value: + * _SUCCESS rtw_cmd_thread can issue cmds to firmware afterwards. + * _FAIL rtw_cmd_thread can not do anything. + */ +s32 rtw_register_cmd_alive(PADAPTER padapter) +{ + s32 res; + struct pwrctrl_priv *pwrctrl; + u8 pslv; + +_func_enter_; + + res = _SUCCESS; + pwrctrl = adapter_to_pwrctl(padapter); + pslv = PS_STATE_S2; + + _enter_pwrlock(&pwrctrl->lock); + + register_task_alive(pwrctrl, CMD_ALIVE); + + if (pwrctrl->bFwCurrentInPSMode == _TRUE) + { + RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_info_, + ("rtw_register_cmd_alive: cpwm=0x%02x alives=0x%08x\n", + pwrctrl->cpwm, pwrctrl->alives)); + + if (pwrctrl->cpwm < pslv) + { + if (pwrctrl->cpwm < PS_STATE_S2) + res = _FAIL; + if (pwrctrl->rpwm < pslv) + rtw_set_rpwm(padapter, pslv); + } + } + + _exit_pwrlock(&pwrctrl->lock); + +#ifdef CONFIG_DETECT_CPWM_BY_POLLING + if (_FAIL == res) + { + if (pwrctrl->cpwm >= PS_STATE_S2) + res = _SUCCESS; + } +#endif // CONFIG_DETECT_CPWM_BY_POLLING + +_func_exit_; + + return res; +} + +/* + * Caller: rx_isr + * + * Calling Context: Dispatch/ISR + * + * Return Value: + * _SUCCESS + * _FAIL + */ +s32 rtw_register_rx_alive(PADAPTER padapter) +{ + struct pwrctrl_priv *pwrctrl; + +_func_enter_; + + pwrctrl = adapter_to_pwrctl(padapter); + + _enter_pwrlock(&pwrctrl->lock); + + register_task_alive(pwrctrl, RECV_ALIVE); + RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, + ("rtw_register_rx_alive: cpwm=0x%02x alives=0x%08x\n", + pwrctrl->cpwm, pwrctrl->alives)); + + _exit_pwrlock(&pwrctrl->lock); + +_func_exit_; + + return _SUCCESS; +} + +/* + * Caller: evt_isr or evt_thread + * + * Calling Context: Dispatch/ISR or Passive + * + * Return Value: + * _SUCCESS + * _FAIL + */ +s32 rtw_register_evt_alive(PADAPTER padapter) +{ + struct pwrctrl_priv *pwrctrl; + +_func_enter_; + + pwrctrl = adapter_to_pwrctl(padapter); + + _enter_pwrlock(&pwrctrl->lock); + + register_task_alive(pwrctrl, EVT_ALIVE); + RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, + ("rtw_register_evt_alive: cpwm=0x%02x alives=0x%08x\n", + pwrctrl->cpwm, pwrctrl->alives)); + + _exit_pwrlock(&pwrctrl->lock); + +_func_exit_; + + return _SUCCESS; +} + +/* + * Caller: ISR + * + * If ISR's txdone, + * No more pkts for TX, + * Then driver shall call this fun. to power down firmware again. + */ +void rtw_unregister_tx_alive(PADAPTER padapter) +{ + struct pwrctrl_priv *pwrctrl; + u8 pslv; + +_func_enter_; + + pwrctrl = adapter_to_pwrctl(padapter); + pslv = PS_STATE_S0; + +#ifdef CONFIG_BT_COEXIST + if ((rtw_btcoex_IsBtDisabled(padapter) == _FALSE) + && (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)) + { + u8 val8; + + val8 = rtw_btcoex_LpsVal(padapter); + if (val8 & BIT(4)) + pslv = PS_STATE_S2; + + } +#endif // CONFIG_BT_COEXIST + +#ifdef CONFIG_P2P_PS + if(padapter->wdinfo.p2p_ps_mode > P2P_PS_NONE) + { + pslv = PS_STATE_S2; + } +#ifdef CONFIG_CONCURRENT_MODE + else if(rtw_buddy_adapter_up(padapter)) + { + if(padapter->pbuddy_adapter->wdinfo.p2p_ps_mode > P2P_PS_NONE) + pslv = PS_STATE_S2; + } +#endif +#endif + + _enter_pwrlock(&pwrctrl->lock); + + unregister_task_alive(pwrctrl, XMIT_ALIVE); + + if ((pwrctrl->pwr_mode != PS_MODE_ACTIVE) + && (pwrctrl->bFwCurrentInPSMode == _TRUE)) + { + RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, + ("%s: cpwm=0x%02x alives=0x%08x\n", + __FUNCTION__, pwrctrl->cpwm, pwrctrl->alives)); + + if (pwrctrl->cpwm > pslv) + { + if ((pslv >= PS_STATE_S2) || (pwrctrl->alives == 0)) + rtw_set_rpwm(padapter, pslv); + } + } + + _exit_pwrlock(&pwrctrl->lock); + +_func_exit_; +} + +/* + * Caller: ISR + * + * If all commands have been done, + * and no more command to do, + * then driver shall call this fun. to power down firmware again. + */ +void rtw_unregister_cmd_alive(PADAPTER padapter) +{ + struct pwrctrl_priv *pwrctrl; + u8 pslv; + +_func_enter_; + + pwrctrl = adapter_to_pwrctl(padapter); + pslv = PS_STATE_S0; + +#ifdef CONFIG_BT_COEXIST + if ((rtw_btcoex_IsBtDisabled(padapter) == _FALSE) + && (rtw_btcoex_IsBtControlLps(padapter) == _TRUE)) + { + u8 val8; + + val8 = rtw_btcoex_LpsVal(padapter); + if (val8 & BIT(4)) + pslv = PS_STATE_S2; + + } +#endif // CONFIG_BT_COEXIST + +#ifdef CONFIG_P2P_PS + if(padapter->wdinfo.p2p_ps_mode > P2P_PS_NONE) + { + pslv = PS_STATE_S2; + } +#ifdef CONFIG_CONCURRENT_MODE + else if(rtw_buddy_adapter_up(padapter)) + { + if(padapter->pbuddy_adapter->wdinfo.p2p_ps_mode > P2P_PS_NONE) + pslv = PS_STATE_S2; + } +#endif +#endif + + _enter_pwrlock(&pwrctrl->lock); + + unregister_task_alive(pwrctrl, CMD_ALIVE); + + if ((pwrctrl->pwr_mode != PS_MODE_ACTIVE) + && (pwrctrl->bFwCurrentInPSMode == _TRUE)) + { + RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_info_, + ("%s: cpwm=0x%02x alives=0x%08x\n", + __FUNCTION__, pwrctrl->cpwm, pwrctrl->alives)); + + if (pwrctrl->cpwm > pslv) + { + if ((pslv >= PS_STATE_S2) || (pwrctrl->alives == 0)) + rtw_set_rpwm(padapter, pslv); + } + } + + _exit_pwrlock(&pwrctrl->lock); + +_func_exit_; +} + +/* + * Caller: ISR + */ +void rtw_unregister_rx_alive(PADAPTER padapter) +{ + struct pwrctrl_priv *pwrctrl; + +_func_enter_; + + pwrctrl = adapter_to_pwrctl(padapter); + + _enter_pwrlock(&pwrctrl->lock); + + unregister_task_alive(pwrctrl, RECV_ALIVE); + + RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, + ("rtw_unregister_rx_alive: cpwm=0x%02x alives=0x%08x\n", + pwrctrl->cpwm, pwrctrl->alives)); + + _exit_pwrlock(&pwrctrl->lock); + +_func_exit_; +} + +void rtw_unregister_evt_alive(PADAPTER padapter) +{ + struct pwrctrl_priv *pwrctrl; + +_func_enter_; + + pwrctrl = adapter_to_pwrctl(padapter); + + unregister_task_alive(pwrctrl, EVT_ALIVE); + + RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_, + ("rtw_unregister_evt_alive: cpwm=0x%02x alives=0x%08x\n", + pwrctrl->cpwm, pwrctrl->alives)); + + _exit_pwrlock(&pwrctrl->lock); + +_func_exit_; +} +#endif /* CONFIG_LPS_LCLK */ + +#ifdef CONFIG_RESUME_IN_WORKQUEUE +static void resume_workitem_callback(struct work_struct *work); +#endif //CONFIG_RESUME_IN_WORKQUEUE + +void rtw_init_pwrctrl_priv(PADAPTER padapter) +{ + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + int i = 0; + u8 val8 = 0; + +#if defined(CONFIG_CONCURRENT_MODE) + if (padapter->adapter_type != PRIMARY_ADAPTER) + return; +#endif + +_func_enter_; + +#ifdef PLATFORM_WINDOWS + pwrctrlpriv->pnp_current_pwr_state=NdisDeviceStateD0; +#endif + + _init_pwrlock(&pwrctrlpriv->lock); + _init_pwrlock(&pwrctrlpriv->check_32k_lock); + pwrctrlpriv->rf_pwrstate = rf_on; + pwrctrlpriv->ips_enter_cnts=0; + pwrctrlpriv->ips_leave_cnts=0; + pwrctrlpriv->lps_enter_cnts=0; + pwrctrlpriv->lps_leave_cnts=0; + pwrctrlpriv->bips_processing = _FALSE; + + pwrctrlpriv->ips_mode = padapter->registrypriv.ips_mode; + pwrctrlpriv->ips_mode_req = padapter->registrypriv.ips_mode; + + pwrctrlpriv->pwr_state_check_interval = RTW_PWR_STATE_CHK_INTERVAL; + pwrctrlpriv->pwr_state_check_cnts = 0; + pwrctrlpriv->bInternalAutoSuspend = _FALSE; + pwrctrlpriv->bInSuspend = _FALSE; + pwrctrlpriv->bkeepfwalive = _FALSE; + +#ifdef CONFIG_AUTOSUSPEND +#ifdef SUPPORT_HW_RFOFF_DETECTED + pwrctrlpriv->pwr_state_check_interval = (pwrctrlpriv->bHWPwrPindetect) ?1000:2000; +#endif +#endif + + pwrctrlpriv->LpsIdleCount = 0; + //pwrctrlpriv->FWCtrlPSMode =padapter->registrypriv.power_mgnt;// PS_MODE_MIN; + if (padapter->registrypriv.mp_mode == 1) + pwrctrlpriv->power_mgnt =PS_MODE_ACTIVE ; + else + pwrctrlpriv->power_mgnt =padapter->registrypriv.power_mgnt;// PS_MODE_MIN; + pwrctrlpriv->bLeisurePs = (PS_MODE_ACTIVE != pwrctrlpriv->power_mgnt)?_TRUE:_FALSE; + + pwrctrlpriv->bFwCurrentInPSMode = _FALSE; + + pwrctrlpriv->rpwm = 0; + pwrctrlpriv->cpwm = PS_STATE_S4; + + pwrctrlpriv->pwr_mode = PS_MODE_ACTIVE; + pwrctrlpriv->smart_ps = padapter->registrypriv.smart_ps; + pwrctrlpriv->bcn_ant_mode = 0; + pwrctrlpriv->dtim = 0; + + pwrctrlpriv->tog = 0x80; + +#ifdef CONFIG_LPS_LCLK + rtw_hal_set_hwreg(padapter, HW_VAR_SET_RPWM, (u8 *)(&pwrctrlpriv->rpwm)); + + _init_workitem(&pwrctrlpriv->cpwm_event, cpwm_event_callback, NULL); + +#ifdef CONFIG_LPS_RPWM_TIMER + pwrctrlpriv->brpwmtimeout = _FALSE; + _init_workitem(&pwrctrlpriv->rpwmtimeoutwi, rpwmtimeout_workitem_callback, NULL); + _init_timer(&pwrctrlpriv->pwr_rpwm_timer, padapter->pnetdev, pwr_rpwm_timeout_handler, padapter); +#endif // CONFIG_LPS_RPWM_TIMER +#endif // CONFIG_LPS_LCLK + + rtw_init_timer(&pwrctrlpriv->pwr_state_check_timer, padapter, pwr_state_check_handler); + + pwrctrlpriv->wowlan_mode = _FALSE; + pwrctrlpriv->wowlan_ap_mode = _FALSE; + pwrctrlpriv->wowlan_p2p_mode = _FALSE; + + #ifdef CONFIG_RESUME_IN_WORKQUEUE + _init_workitem(&pwrctrlpriv->resume_work, resume_workitem_callback, NULL); + pwrctrlpriv->rtw_workqueue = create_singlethread_workqueue("rtw_workqueue"); + #endif //CONFIG_RESUME_IN_WORKQUEUE + + #if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER) + pwrctrlpriv->early_suspend.suspend = NULL; + rtw_register_early_suspend(pwrctrlpriv); + #endif //CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER + +#ifdef CONFIG_GPIO_WAKEUP + /*default low active*/ + pwrctrlpriv->is_high_active = HIGH_ACTIVE; + val8 = (pwrctrlpriv->is_high_active == 0) ? 1 : 0; + rtw_hal_switch_gpio_wl_ctrl(padapter, WAKEUP_GPIO_IDX, _TRUE); + rtw_hal_set_output_gpio(padapter, WAKEUP_GPIO_IDX, val8); + DBG_871X("%s: set GPIO_%d %d as default.\n", + __func__, WAKEUP_GPIO_IDX, val8); +#endif /* CONFIG_GPIO_WAKEUP */ + +_func_exit_; + +} + + +void rtw_free_pwrctrl_priv(PADAPTER adapter) +{ + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(adapter); + +#if defined(CONFIG_CONCURRENT_MODE) + if (adapter->adapter_type != PRIMARY_ADAPTER) + return; +#endif + +_func_enter_; + + //_rtw_memset((unsigned char *)pwrctrlpriv, 0, sizeof(struct pwrctrl_priv)); + + + #ifdef CONFIG_RESUME_IN_WORKQUEUE + if (pwrctrlpriv->rtw_workqueue) { + flush_workqueue(pwrctrlpriv->rtw_workqueue); + destroy_workqueue(pwrctrlpriv->rtw_workqueue); + } + #endif + + #if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER) + rtw_unregister_early_suspend(pwrctrlpriv); + #endif //CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER + + _free_pwrlock(&pwrctrlpriv->lock); + _free_pwrlock(&pwrctrlpriv->check_32k_lock); + +_func_exit_; +} + +#ifdef CONFIG_RESUME_IN_WORKQUEUE +extern int rtw_resume_process(_adapter *padapter); + +static void resume_workitem_callback(struct work_struct *work) +{ + struct pwrctrl_priv *pwrpriv = container_of(work, struct pwrctrl_priv, resume_work); + struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv); + _adapter *adapter = dvobj->padapters[IFACE_ID0]; + + DBG_871X("%s\n",__FUNCTION__); + + rtw_resume_process(adapter); + + rtw_resume_unlock_suspend(); +} + +void rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv) +{ + // accquire system's suspend lock preventing from falliing asleep while resume in workqueue + //rtw_lock_suspend(); + + rtw_resume_lock_suspend(); + + #if 1 + queue_work(pwrpriv->rtw_workqueue, &pwrpriv->resume_work); + #else + _set_workitem(&pwrpriv->resume_work); + #endif +} +#endif //CONFIG_RESUME_IN_WORKQUEUE + +#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER) +inline bool rtw_is_earlysuspend_registered(struct pwrctrl_priv *pwrpriv) +{ + return (pwrpriv->early_suspend.suspend) ? _TRUE : _FALSE; +} + +inline bool rtw_is_do_late_resume(struct pwrctrl_priv *pwrpriv) +{ + return (pwrpriv->do_late_resume) ? _TRUE : _FALSE; +} + +inline void rtw_set_do_late_resume(struct pwrctrl_priv *pwrpriv, bool enable) +{ + pwrpriv->do_late_resume = enable; +} +#endif + +#ifdef CONFIG_HAS_EARLYSUSPEND +extern int rtw_resume_process(_adapter *padapter); +static void rtw_early_suspend(struct early_suspend *h) +{ + struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend); + DBG_871X("%s\n",__FUNCTION__); + + rtw_set_do_late_resume(pwrpriv, _FALSE); +} + +static void rtw_late_resume(struct early_suspend *h) +{ + struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend); + struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv); + _adapter *adapter = dvobj->padapters[IFACE_ID0]; + + DBG_871X("%s\n",__FUNCTION__); + + if(pwrpriv->do_late_resume) { + rtw_set_do_late_resume(pwrpriv, _FALSE); + rtw_resume_process(adapter); + } +} + +void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv) +{ + DBG_871X("%s\n", __FUNCTION__); + + //jeff: set the early suspend level before blank screen, so we wll do late resume after scree is lit + pwrpriv->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN - 20; + pwrpriv->early_suspend.suspend = rtw_early_suspend; + pwrpriv->early_suspend.resume = rtw_late_resume; + register_early_suspend(&pwrpriv->early_suspend); + + +} + +void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv) +{ + DBG_871X("%s\n", __FUNCTION__); + + rtw_set_do_late_resume(pwrpriv, _FALSE); + + if (pwrpriv->early_suspend.suspend) + unregister_early_suspend(&pwrpriv->early_suspend); + + pwrpriv->early_suspend.suspend = NULL; + pwrpriv->early_suspend.resume = NULL; +} +#endif //CONFIG_HAS_EARLYSUSPEND + +#ifdef CONFIG_ANDROID_POWER +#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) +extern int rtw_resume_process(PADAPTER padapter); +#endif +static void rtw_early_suspend(android_early_suspend_t *h) +{ + struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend); + DBG_871X("%s\n",__FUNCTION__); + + rtw_set_do_late_resume(pwrpriv, _FALSE); +} + +static void rtw_late_resume(android_early_suspend_t *h) +{ + struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend); + struct dvobj_priv *dvobj = pwrctl_to_dvobj(pwrpriv); + _adapter *adapter = dvobj->padapters[IFACE_ID0]; + + DBG_871X("%s\n",__FUNCTION__); + if(pwrpriv->do_late_resume) { + #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + rtw_set_do_late_resume(pwrpriv, _FALSE); + rtw_resume_process(adapter); + #endif + } +} + +void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv) +{ + DBG_871X("%s\n", __FUNCTION__); + + //jeff: set the early suspend level before blank screen, so we wll do late resume after scree is lit + pwrpriv->early_suspend.level = ANDROID_EARLY_SUSPEND_LEVEL_BLANK_SCREEN - 20; + pwrpriv->early_suspend.suspend = rtw_early_suspend; + pwrpriv->early_suspend.resume = rtw_late_resume; + android_register_early_suspend(&pwrpriv->early_suspend); +} + +void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv) +{ + DBG_871X("%s\n", __FUNCTION__); + + rtw_set_do_late_resume(pwrpriv, _FALSE); + + if (pwrpriv->early_suspend.suspend) + android_unregister_early_suspend(&pwrpriv->early_suspend); + + pwrpriv->early_suspend.suspend = NULL; + pwrpriv->early_suspend.resume = NULL; +} +#endif //CONFIG_ANDROID_POWER + +u8 rtw_interface_ps_func(_adapter *padapter,HAL_INTF_PS_FUNC efunc_id,u8* val) +{ + u8 bResult = _TRUE; + rtw_hal_intf_ps_func(padapter,efunc_id,val); + + return bResult; +} + + +inline void rtw_set_ips_deny(_adapter *padapter, u32 ms) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ms); +} + +/* +* rtw_pwr_wakeup - Wake the NIC up from: 1)IPS. 2)USB autosuspend +* @adapter: pointer to _adapter structure +* @ips_deffer_ms: the ms wiil prevent from falling into IPS after wakeup +* Return _SUCCESS or _FAIL +*/ + +int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); + struct mlme_priv *pmlmepriv; + int ret = _SUCCESS; + int i; + u32 start = rtw_get_current_time(); + + /* for LPS */ + LeaveAllPowerSaveMode(padapter); + + /* IPS still bound with primary adapter */ + padapter = GET_PRIMARY_ADAPTER(padapter); + pmlmepriv = &padapter->mlmepriv; + + if (pwrpriv->ips_deny_time < rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms)) + pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms); + + + if (pwrpriv->ps_processing) { + DBG_871X("%s wait ps_processing...\n", __func__); + while (pwrpriv->ps_processing && rtw_get_passing_time_ms(start) <= 3000) + rtw_msleep_os(10); + if (pwrpriv->ps_processing) + DBG_871X("%s wait ps_processing timeout\n", __func__); + else + DBG_871X("%s wait ps_processing done\n", __func__); + } + +#ifdef DBG_CONFIG_ERROR_DETECT + if (rtw_hal_sreset_inprogress(padapter)) { + DBG_871X("%s wait sreset_inprogress...\n", __func__); + while (rtw_hal_sreset_inprogress(padapter) && rtw_get_passing_time_ms(start) <= 4000) + rtw_msleep_os(10); + if (rtw_hal_sreset_inprogress(padapter)) + DBG_871X("%s wait sreset_inprogress timeout\n", __func__); + else + DBG_871X("%s wait sreset_inprogress done\n", __func__); + } +#endif + + if (pwrpriv->bInternalAutoSuspend == _FALSE && pwrpriv->bInSuspend) { + DBG_871X("%s wait bInSuspend...\n", __func__); + while (pwrpriv->bInSuspend + && ((rtw_get_passing_time_ms(start) <= 3000 && !rtw_is_do_late_resume(pwrpriv)) + || (rtw_get_passing_time_ms(start) <= 500 && rtw_is_do_late_resume(pwrpriv))) + ) { + rtw_msleep_os(10); + } + if (pwrpriv->bInSuspend) + DBG_871X("%s wait bInSuspend timeout\n", __func__); + else + DBG_871X("%s wait bInSuspend done\n", __func__); + } + + //System suspend is not allowed to wakeup + if((pwrpriv->bInternalAutoSuspend == _FALSE) && (_TRUE == pwrpriv->bInSuspend )){ + ret = _FAIL; + goto exit; + } + + //block??? + if((pwrpriv->bInternalAutoSuspend == _TRUE) && (padapter->net_closed == _TRUE)) { + ret = _FAIL; + goto exit; + } + + //I think this should be check in IPS, LPS, autosuspend functions... + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + { +#if defined (CONFIG_BT_COEXIST)&& defined (CONFIG_AUTOSUSPEND) + if(_TRUE==pwrpriv->bInternalAutoSuspend){ + if(0==pwrpriv->autopm_cnt){ + #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,33)) + if (usb_autopm_get_interface(adapter_to_dvobj(padapter)->pusbintf) < 0) + { + DBG_871X( "can't get autopm: \n"); + } + #elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,20)) + usb_autopm_disable(adapter_to_dvobj(padapter)->pusbintf); + #else + usb_autoresume_device(adapter_to_dvobj(padapter)->pusbdev, 1); + #endif + pwrpriv->autopm_cnt++; + } +#endif //#if defined (CONFIG_BT_COEXIST)&& defined (CONFIG_AUTOSUSPEND) + ret = _SUCCESS; + goto exit; +#if defined (CONFIG_BT_COEXIST)&& defined (CONFIG_AUTOSUSPEND) + } +#endif //#if defined (CONFIG_BT_COEXIST)&& defined (CONFIG_AUTOSUSPEND) + } + + if(rf_off == pwrpriv->rf_pwrstate ) + { +#ifdef CONFIG_USB_HCI +#ifdef CONFIG_AUTOSUSPEND + if(pwrpriv->brfoffbyhw==_TRUE) + { + DBG_8192C("hw still in rf_off state ...........\n"); + ret = _FAIL; + goto exit; + } + else if(padapter->registrypriv.usbss_enable) + { + DBG_8192C("%s call autoresume_enter....\n",__FUNCTION__); + if(_FAIL == autoresume_enter(padapter)) + { + DBG_8192C("======> autoresume fail.............\n"); + ret = _FAIL; + goto exit; + } + } + else +#endif +#endif + { +#ifdef CONFIG_IPS + DBG_8192C("%s call ips_leave....\n",__FUNCTION__); + if(_FAIL == ips_leave(padapter)) + { + DBG_8192C("======> ips_leave fail.............\n"); + ret = _FAIL; + goto exit; + } +#endif + } + } + + //TODO: the following checking need to be merged... + if (rtw_is_drv_stopped(padapter) + || !padapter->bup + || !rtw_is_hw_init_completed(padapter) + ) { + DBG_8192C("%s: bDriverStopped=%s, bup=%d, hw_init_completed=%u\n" + , caller + , rtw_is_drv_stopped(padapter)?"True":"False" + , padapter->bup + , rtw_get_hw_init_completed(padapter)); + ret= _FALSE; + goto exit; + } + +exit: + if (pwrpriv->ips_deny_time < rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms)) + pwrpriv->ips_deny_time = rtw_get_current_time() + rtw_ms_to_systime(ips_deffer_ms); + return ret; + +} + +int rtw_pm_set_lps(_adapter *padapter, u8 mode) +{ + int ret = 0; + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + + if ( mode < PS_MODE_NUM ) + { + if(pwrctrlpriv->power_mgnt !=mode) + { + if(PS_MODE_ACTIVE == mode) + { + LeaveAllPowerSaveMode(padapter); + } + else + { + pwrctrlpriv->LpsIdleCount = 2; + } + pwrctrlpriv->power_mgnt = mode; + pwrctrlpriv->bLeisurePs = (PS_MODE_ACTIVE != pwrctrlpriv->power_mgnt)?_TRUE:_FALSE; + } + } + else + { + ret = -EINVAL; + } + + return ret; +} + +int rtw_pm_set_ips(_adapter *padapter, u8 mode) +{ + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + + if( mode == IPS_NORMAL || mode == IPS_LEVEL_2 ) { + rtw_ips_mode_req(pwrctrlpriv, mode); + DBG_871X("%s %s\n", __FUNCTION__, mode == IPS_NORMAL?"IPS_NORMAL":"IPS_LEVEL_2"); + return 0; + } + else if(mode ==IPS_NONE){ + rtw_ips_mode_req(pwrctrlpriv, mode); + DBG_871X("%s %s\n", __FUNCTION__, "IPS_NONE"); + if (!rtw_is_surprise_removed(padapter) && (_FAIL == rtw_pwr_wakeup(padapter))) + return -EFAULT; + } + else { + return -EINVAL; + } + return 0; +} + +/* + * ATTENTION: + * This function will request pwrctrl LOCK! + */ +void rtw_ps_deny(PADAPTER padapter, PS_DENY_REASON reason) +{ + struct pwrctrl_priv *pwrpriv; + s32 ret; + + +// DBG_871X("+" FUNC_ADPT_FMT ": Request PS deny for %d (0x%08X)\n", +// FUNC_ADPT_ARG(padapter), reason, BIT(reason)); + + pwrpriv = adapter_to_pwrctl(padapter); + + _enter_pwrlock(&pwrpriv->lock); + if (pwrpriv->ps_deny & BIT(reason)) + { + DBG_871X(FUNC_ADPT_FMT ": [WARNING] Reason %d had been set before!!\n", + FUNC_ADPT_ARG(padapter), reason); + } + pwrpriv->ps_deny |= BIT(reason); + _exit_pwrlock(&pwrpriv->lock); + +// DBG_871X("-" FUNC_ADPT_FMT ": Now PS deny for 0x%08X\n", +// FUNC_ADPT_ARG(padapter), pwrpriv->ps_deny); +} + +/* + * ATTENTION: + * This function will request pwrctrl LOCK! + */ +void rtw_ps_deny_cancel(PADAPTER padapter, PS_DENY_REASON reason) +{ + struct pwrctrl_priv *pwrpriv; + + +// DBG_871X("+" FUNC_ADPT_FMT ": Cancel PS deny for %d(0x%08X)\n", +// FUNC_ADPT_ARG(padapter), reason, BIT(reason)); + + pwrpriv = adapter_to_pwrctl(padapter); + + _enter_pwrlock(&pwrpriv->lock); + if ((pwrpriv->ps_deny & BIT(reason)) == 0) + { + DBG_871X(FUNC_ADPT_FMT ": [ERROR] Reason %d had been canceled before!!\n", + FUNC_ADPT_ARG(padapter), reason); + } + pwrpriv->ps_deny &= ~BIT(reason); + _exit_pwrlock(&pwrpriv->lock); + +// DBG_871X("-" FUNC_ADPT_FMT ": Now PS deny for 0x%08X\n", +// FUNC_ADPT_ARG(padapter), pwrpriv->ps_deny); +} + +/* + * ATTENTION: + * Before calling this function pwrctrl lock should be occupied already, + * otherwise it may return incorrect value. + */ +u32 rtw_ps_deny_get(PADAPTER padapter) +{ + u32 deny; + + + deny = adapter_to_pwrctl(padapter)->ps_deny; + + return deny; +} + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_recv.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_recv.c new file mode 100644 index 000000000..43d5e5bf0 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_recv.c @@ -0,0 +1,4980 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_RECV_C_ + +#include +#include + +#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) + +#error "Shall be Linux or Windows, but not both!\n" + +#endif + + +#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS +void rtw_signal_stat_timer_hdl(RTW_TIMER_HDL_ARGS); + +enum { + SIGNAL_STAT_CALC_PROFILE_0 = 0, + SIGNAL_STAT_CALC_PROFILE_1, + SIGNAL_STAT_CALC_PROFILE_MAX +}; + +u8 signal_stat_calc_profile[SIGNAL_STAT_CALC_PROFILE_MAX][2] = { + {4, 1}, /* Profile 0 => pre_stat : curr_stat = 4 : 1 */ + {3, 7} /* Profile 1 => pre_stat : curr_stat = 3 : 7 */ +}; + +#ifndef RTW_SIGNAL_STATE_CALC_PROFILE +#define RTW_SIGNAL_STATE_CALC_PROFILE SIGNAL_STAT_CALC_PROFILE_1 +#endif + +#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS + +void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv) +{ + + +_func_enter_; + + _rtw_memset((u8 *)psta_recvpriv, 0, sizeof (struct sta_recv_priv)); + + _rtw_spinlock_init(&psta_recvpriv->lock); + + //for(i=0; iblk_strms[i]); + + _rtw_init_queue(&psta_recvpriv->defrag_q); + +_func_exit_; + +} + +sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter) +{ + sint i; + + union recv_frame *precvframe; + + sint res=_SUCCESS; + +_func_enter_; + + // We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). + //_rtw_memset((unsigned char *)precvpriv, 0, sizeof (struct recv_priv)); + + _rtw_spinlock_init(&precvpriv->lock); + + _rtw_init_queue(&precvpriv->free_recv_queue); + _rtw_init_queue(&precvpriv->recv_pending_queue); + _rtw_init_queue(&precvpriv->uc_swdec_pending_queue); + + precvpriv->adapter = padapter; + + precvpriv->free_recvframe_cnt = NR_RECVFRAME; + + precvpriv->sink_udpport = 0; + precvpriv->pre_rtp_rxseq = 0; + precvpriv->cur_rtp_rxseq = 0; + + rtw_os_recv_resource_init(precvpriv, padapter); + + precvpriv->pallocated_frame_buf = rtw_zvmalloc(NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ); + + if(precvpriv->pallocated_frame_buf==NULL){ + res= _FAIL; + goto exit; + } + //_rtw_memset(precvpriv->pallocated_frame_buf, 0, NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ); + + precvpriv->precv_frame_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(precvpriv->pallocated_frame_buf), RXFRAME_ALIGN_SZ); + //precvpriv->precv_frame_buf = precvpriv->pallocated_frame_buf + RXFRAME_ALIGN_SZ - + // ((SIZE_PTR) (precvpriv->pallocated_frame_buf) &(RXFRAME_ALIGN_SZ-1)); + + precvframe = (union recv_frame*) precvpriv->precv_frame_buf; + + + for(i=0; i < NR_RECVFRAME ; i++) + { + _rtw_init_listhead(&(precvframe->u.list)); + + rtw_list_insert_tail(&(precvframe->u.list), &(precvpriv->free_recv_queue.queue)); + + res = rtw_os_recv_resource_alloc(padapter, precvframe); + + precvframe->u.hdr.len = 0; + + precvframe->u.hdr.adapter =padapter; + precvframe++; + + } + +#ifdef CONFIG_USB_HCI + + ATOMIC_SET(&(precvpriv->rx_pending_cnt), 1); + + _rtw_init_sema(&precvpriv->allrxreturnevt, 0); + +#endif + + res = rtw_hal_init_recv_priv(padapter); + +#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS + rtw_init_timer(&precvpriv->signal_stat_timer, padapter, RTW_TIMER_HDL_NAME(signal_stat)); + + precvpriv->signal_stat_sampling_interval = 2000; //ms + //precvpriv->signal_stat_converging_constant = 5000; //ms + + rtw_set_signal_stat_timer(precvpriv); +#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS + +exit: + +_func_exit_; + + return res; + +} + +void rtw_mfree_recv_priv_lock(struct recv_priv *precvpriv); +void rtw_mfree_recv_priv_lock(struct recv_priv *precvpriv) +{ + _rtw_spinlock_free(&precvpriv->lock); +#ifdef CONFIG_RECV_THREAD_MODE + _rtw_free_sema(&precvpriv->recv_sema); + _rtw_free_sema(&precvpriv->terminate_recvthread_sema); +#endif + + _rtw_spinlock_free(&precvpriv->free_recv_queue.lock); + _rtw_spinlock_free(&precvpriv->recv_pending_queue.lock); + + _rtw_spinlock_free(&precvpriv->free_recv_buf_queue.lock); + +#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX + _rtw_spinlock_free(&precvpriv->recv_buf_pending_queue.lock); +#endif // CONFIG_USE_USB_BUFFER_ALLOC_RX +} + +void _rtw_free_recv_priv (struct recv_priv *precvpriv) +{ + _adapter *padapter = precvpriv->adapter; + +_func_enter_; + + rtw_free_uc_swdec_pending_queue(padapter); + + rtw_mfree_recv_priv_lock(precvpriv); + + rtw_os_recv_resource_free(precvpriv); + + if(precvpriv->pallocated_frame_buf) { + rtw_vmfree(precvpriv->pallocated_frame_buf, NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ); + } + + rtw_hal_free_recv_priv(padapter); + +_func_exit_; + +} + +bool rtw_rframe_del_wfd_ie(union recv_frame *rframe, u8 ies_offset) +{ +#define DBG_RFRAME_DEL_WFD_IE 0 + u8 *ies = rframe->u.hdr.rx_data + sizeof(struct rtw_ieee80211_hdr_3addr) + ies_offset; + uint ies_len_ori = rframe->u.hdr.len - (ies - rframe->u.hdr.rx_data); + uint ies_len; + + ies_len = rtw_del_wfd_ie(ies, ies_len_ori, DBG_RFRAME_DEL_WFD_IE ? __func__ : NULL); + rframe->u.hdr.len -= ies_len_ori - ies_len; + + return ies_len_ori != ies_len; +} + +union recv_frame *_rtw_alloc_recvframe (_queue *pfree_recv_queue) +{ + + union recv_frame *precvframe; + _list *plist, *phead; + _adapter *padapter; + struct recv_priv *precvpriv; +_func_enter_; + + if(_rtw_queue_empty(pfree_recv_queue) == _TRUE) + { + precvframe = NULL; + } + else + { + phead = get_list_head(pfree_recv_queue); + + plist = get_next(phead); + + precvframe = LIST_CONTAINOR(plist, union recv_frame, u); + + rtw_list_delete(&precvframe->u.hdr.list); + padapter=precvframe->u.hdr.adapter; + if(padapter !=NULL){ + precvpriv=&padapter->recvpriv; + if(pfree_recv_queue == &precvpriv->free_recv_queue) + precvpriv->free_recvframe_cnt--; + } + } + +_func_exit_; + + return precvframe; + +} + +union recv_frame *rtw_alloc_recvframe (_queue *pfree_recv_queue) +{ + _irqL irqL; + union recv_frame *precvframe; + + _enter_critical_bh(&pfree_recv_queue->lock, &irqL); + + precvframe = _rtw_alloc_recvframe(pfree_recv_queue); + + _exit_critical_bh(&pfree_recv_queue->lock, &irqL); + + return precvframe; +} + +void rtw_init_recvframe(union recv_frame *precvframe, struct recv_priv *precvpriv) +{ + /* Perry: This can be removed */ + _rtw_init_listhead(&precvframe->u.hdr.list); + + precvframe->u.hdr.len=0; +} + +int rtw_free_recvframe(union recv_frame *precvframe, _queue *pfree_recv_queue) +{ + _irqL irqL; + _adapter *padapter=precvframe->u.hdr.adapter; + struct recv_priv *precvpriv = &padapter->recvpriv; + +_func_enter_; + +#ifdef CONFIG_CONCURRENT_MODE + if(padapter->adapter_type > PRIMARY_ADAPTER) + { + padapter = padapter->pbuddy_adapter;//get primary_padapter + precvpriv = &padapter->recvpriv; + pfree_recv_queue = &precvpriv->free_recv_queue; + precvframe->u.hdr.adapter = padapter; + } +#endif + + rtw_os_free_recvframe(precvframe); + + + _enter_critical_bh(&pfree_recv_queue->lock, &irqL); + + rtw_list_delete(&(precvframe->u.hdr.list)); + + precvframe->u.hdr.len = 0; + + rtw_list_insert_tail(&(precvframe->u.hdr.list), get_list_head(pfree_recv_queue)); + + if(padapter !=NULL){ + if(pfree_recv_queue == &precvpriv->free_recv_queue) + precvpriv->free_recvframe_cnt++; + } + + _exit_critical_bh(&pfree_recv_queue->lock, &irqL); + +_func_exit_; + + return _SUCCESS; + +} + + + + +sint _rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue) +{ + + _adapter *padapter=precvframe->u.hdr.adapter; + struct recv_priv *precvpriv = &padapter->recvpriv; + +_func_enter_; + + //_rtw_init_listhead(&(precvframe->u.hdr.list)); + rtw_list_delete(&(precvframe->u.hdr.list)); + + + rtw_list_insert_tail(&(precvframe->u.hdr.list), get_list_head(queue)); + + if (padapter != NULL) { + if (queue == &precvpriv->free_recv_queue) + precvpriv->free_recvframe_cnt++; + } + +_func_exit_; + + return _SUCCESS; +} + +sint rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue) +{ + sint ret; + _irqL irqL; + + //_spinlock(&pfree_recv_queue->lock); + _enter_critical_bh(&queue->lock, &irqL); + ret = _rtw_enqueue_recvframe(precvframe, queue); + //_rtw_spinunlock(&pfree_recv_queue->lock); + _exit_critical_bh(&queue->lock, &irqL); + + return ret; +} + +/* +sint rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue) +{ + return rtw_free_recvframe(precvframe, queue); +} +*/ + + + + +/* +caller : defrag ; recvframe_chk_defrag in recv_thread (passive) +pframequeue: defrag_queue : will be accessed in recv_thread (passive) + +using spinlock to protect + +*/ + +void rtw_free_recvframe_queue(_queue *pframequeue, _queue *pfree_recv_queue) +{ + union recv_frame *precvframe; + _list *plist, *phead; + +_func_enter_; + _rtw_spinlock(&pframequeue->lock); + + phead = get_list_head(pframequeue); + plist = get_next(phead); + + while(rtw_end_of_queue_search(phead, plist) == _FALSE) + { + precvframe = LIST_CONTAINOR(plist, union recv_frame, u); + + plist = get_next(plist); + + //rtw_list_delete(&precvframe->u.hdr.list); // will do this in rtw_free_recvframe() + + rtw_free_recvframe(precvframe, pfree_recv_queue); + } + + _rtw_spinunlock(&pframequeue->lock); + +_func_exit_; + +} + +u32 rtw_free_uc_swdec_pending_queue(_adapter *adapter) +{ + u32 cnt = 0; + union recv_frame *pending_frame; + while((pending_frame=rtw_alloc_recvframe(&adapter->recvpriv.uc_swdec_pending_queue))) { + rtw_free_recvframe(pending_frame, &adapter->recvpriv.free_recv_queue); + cnt++; + } + + if (cnt) + DBG_871X(FUNC_ADPT_FMT" dequeue %d\n", FUNC_ADPT_ARG(adapter), cnt); + + return cnt; +} + + +sint rtw_enqueue_recvbuf_to_head(struct recv_buf *precvbuf, _queue *queue) +{ + _irqL irqL; + + _enter_critical_bh(&queue->lock, &irqL); + + rtw_list_delete(&precvbuf->list); + rtw_list_insert_head(&precvbuf->list, get_list_head(queue)); + + _exit_critical_bh(&queue->lock, &irqL); + + return _SUCCESS; +} + +sint rtw_enqueue_recvbuf(struct recv_buf *precvbuf, _queue *queue) +{ + _irqL irqL; +#ifdef CONFIG_SDIO_HCI + _enter_critical_bh(&queue->lock, &irqL); +#else + _enter_critical_ex(&queue->lock, &irqL); +#endif/*#ifdef CONFIG_SDIO_HCI*/ + + rtw_list_delete(&precvbuf->list); + + rtw_list_insert_tail(&precvbuf->list, get_list_head(queue)); +#ifdef CONFIG_SDIO_HCI + _exit_critical_bh(&queue->lock, &irqL); +#else + _exit_critical_ex(&queue->lock, &irqL); +#endif/*#ifdef CONFIG_SDIO_HCI*/ + return _SUCCESS; + +} + +struct recv_buf *rtw_dequeue_recvbuf (_queue *queue) +{ + _irqL irqL; + struct recv_buf *precvbuf; + _list *plist, *phead; + +#ifdef CONFIG_SDIO_HCI + _enter_critical_bh(&queue->lock, &irqL); +#else + _enter_critical_ex(&queue->lock, &irqL); +#endif/*#ifdef CONFIG_SDIO_HCI*/ + + if(_rtw_queue_empty(queue) == _TRUE) + { + precvbuf = NULL; + } + else + { + phead = get_list_head(queue); + + plist = get_next(phead); + + precvbuf = LIST_CONTAINOR(plist, struct recv_buf, list); + + rtw_list_delete(&precvbuf->list); + + } + +#ifdef CONFIG_SDIO_HCI + _exit_critical_bh(&queue->lock, &irqL); +#else + _exit_critical_ex(&queue->lock, &irqL); +#endif/*#ifdef CONFIG_SDIO_HCI*/ + + return precvbuf; + +} + +sint recvframe_chkmic(_adapter *adapter, union recv_frame *precvframe); +sint recvframe_chkmic(_adapter *adapter, union recv_frame *precvframe){ + + sint i,res=_SUCCESS; + u32 datalen; + u8 miccode[8]; + u8 bmic_err=_FALSE,brpt_micerror = _TRUE; + u8 *pframe, *payload,*pframemic; + u8 *mickey; + //u8 *iv,rxdata_key_idx=0; + struct sta_info *stainfo; + struct rx_pkt_attrib *prxattrib=&precvframe->u.hdr.attrib; + struct security_priv *psecuritypriv=&adapter->securitypriv; + + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); +_func_enter_; + + stainfo=rtw_get_stainfo(&adapter->stapriv ,&prxattrib->ta[0]); + + if(prxattrib->encrypt ==_TKIP_) + { + RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n recvframe_chkmic:prxattrib->encrypt ==_TKIP_\n")); + RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n recvframe_chkmic:da=0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n", + prxattrib->ra[0],prxattrib->ra[1],prxattrib->ra[2],prxattrib->ra[3],prxattrib->ra[4],prxattrib->ra[5])); + + //calculate mic code + if(stainfo!= NULL) + { + if(IS_MCAST(prxattrib->ra)) + { + //mickey=&psecuritypriv->dot118021XGrprxmickey.skey[0]; + //iv = precvframe->u.hdr.rx_data+prxattrib->hdrlen; + //rxdata_key_idx =( ((iv[3])>>6)&0x3) ; + mickey=&psecuritypriv->dot118021XGrprxmickey[prxattrib->key_index].skey[0]; + + RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n recvframe_chkmic: bcmc key \n")); + //DBG_871X("\n recvframe_chkmic: bcmc key psecuritypriv->dot118021XGrpKeyid(%d),pmlmeinfo->key_index(%d) ,recv key_id(%d)\n", + // psecuritypriv->dot118021XGrpKeyid,pmlmeinfo->key_index,rxdata_key_idx); + + if(psecuritypriv->binstallGrpkey==_FALSE) + { + res=_FAIL; + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n recvframe_chkmic:didn't install group key!!!!!!!!!!\n")); + DBG_871X("\n recvframe_chkmic:didn't install group key!!!!!!!!!!\n"); + goto exit; + } + } + else{ + mickey=&stainfo->dot11tkiprxmickey.skey[0]; + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n recvframe_chkmic: unicast key \n")); + } + + datalen=precvframe->u.hdr.len-prxattrib->hdrlen-prxattrib->iv_len-prxattrib->icv_len-8;//icv_len included the mic code + pframe=precvframe->u.hdr.rx_data; + payload=pframe+prxattrib->hdrlen+prxattrib->iv_len; + + RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n prxattrib->iv_len=%d prxattrib->icv_len=%d\n",prxattrib->iv_len,prxattrib->icv_len)); + + //rtw_seccalctkipmic(&stainfo->dot11tkiprxmickey.skey[0],pframe,payload, datalen ,&miccode[0],(unsigned char)prxattrib->priority); //care the length of the data + + rtw_seccalctkipmic(mickey,pframe,payload, datalen ,&miccode[0],(unsigned char)prxattrib->priority); //care the length of the data + + pframemic=payload+datalen; + + bmic_err=_FALSE; + + for(i=0;i<8;i++){ + if(miccode[i] != *(pframemic+i)){ + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvframe_chkmic:miccode[%d](%02x) != *(pframemic+%d)(%02x) ",i,miccode[i],i,*(pframemic+i))); + bmic_err=_TRUE; + } + } + + + if(bmic_err==_TRUE){ + + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n *(pframemic-8)-*(pframemic-1)=0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n", + *(pframemic-8),*(pframemic-7),*(pframemic-6),*(pframemic-5),*(pframemic-4),*(pframemic-3),*(pframemic-2),*(pframemic-1))); + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n *(pframemic-16)-*(pframemic-9)=0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n", + *(pframemic-16),*(pframemic-15),*(pframemic-14),*(pframemic-13),*(pframemic-12),*(pframemic-11),*(pframemic-10),*(pframemic-9))); + + { + uint i; + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n ======demp packet (len=%d)======\n",precvframe->u.hdr.len)); + for(i=0;iu.hdr.len;i=i+8){ + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x", + *(precvframe->u.hdr.rx_data+i),*(precvframe->u.hdr.rx_data+i+1), + *(precvframe->u.hdr.rx_data+i+2),*(precvframe->u.hdr.rx_data+i+3), + *(precvframe->u.hdr.rx_data+i+4),*(precvframe->u.hdr.rx_data+i+5), + *(precvframe->u.hdr.rx_data+i+6),*(precvframe->u.hdr.rx_data+i+7))); + } + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n ======demp packet end [len=%d]======\n",precvframe->u.hdr.len)); + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n hrdlen=%d, \n",prxattrib->hdrlen)); + } + + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("ra=0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x psecuritypriv->binstallGrpkey=%d ", + prxattrib->ra[0],prxattrib->ra[1],prxattrib->ra[2], + prxattrib->ra[3],prxattrib->ra[4],prxattrib->ra[5],psecuritypriv->binstallGrpkey)); + + // double check key_index for some timing issue , + // cannot compare with psecuritypriv->dot118021XGrpKeyid also cause timing issue + if((IS_MCAST(prxattrib->ra)==_TRUE) && (prxattrib->key_index != pmlmeinfo->key_index )) + brpt_micerror = _FALSE; + + if((prxattrib->bdecrypted ==_TRUE)&& (brpt_micerror == _TRUE)) + { + rtw_handle_tkip_mic_err(adapter, stainfo, (u8)IS_MCAST(prxattrib->ra)); + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" mic error :prxattrib->bdecrypted=%d ",prxattrib->bdecrypted)); + DBG_871X(" mic error :prxattrib->bdecrypted=%d\n",prxattrib->bdecrypted); + } + else + { + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" mic error :prxattrib->bdecrypted=%d ",prxattrib->bdecrypted)); + DBG_871X(" mic error :prxattrib->bdecrypted=%d\n",prxattrib->bdecrypted); + } + + res=_FAIL; + + } + else{ + //mic checked ok + if((psecuritypriv->bcheck_grpkey ==_FALSE)&&(IS_MCAST(prxattrib->ra)==_TRUE)){ + psecuritypriv->bcheck_grpkey =_TRUE; + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("psecuritypriv->bcheck_grpkey =_TRUE")); + } + } + + } + else + { + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvframe_chkmic: rtw_get_stainfo==NULL!!!\n")); + } + + recvframe_pull_tail(precvframe, 8); + + } + +exit: + +_func_exit_; + + return res; + +} + +//decrypt and set the ivlen,icvlen of the recv_frame +union recv_frame * decryptor(_adapter *padapter,union recv_frame *precv_frame); +union recv_frame * decryptor(_adapter *padapter,union recv_frame *precv_frame) +{ + + struct rx_pkt_attrib *prxattrib = &precv_frame->u.hdr.attrib; + struct security_priv *psecuritypriv=&padapter->securitypriv; + union recv_frame *return_packet=precv_frame; + u32 res=_SUCCESS; + +_func_enter_; + + DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt); + + RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("prxstat->decrypted=%x prxattrib->encrypt = 0x%03x\n",prxattrib->bdecrypted,prxattrib->encrypt)); + + if(prxattrib->encrypt>0) + { + u8 *iv = precv_frame->u.hdr.rx_data+prxattrib->hdrlen; + prxattrib->key_index = ( ((iv[3])>>6)&0x3) ; + + if(prxattrib->key_index > WEP_KEYS) + { + DBG_871X("prxattrib->key_index(%d) > WEP_KEYS \n", prxattrib->key_index); + + switch(prxattrib->encrypt){ + case _WEP40_: + case _WEP104_: + prxattrib->key_index = psecuritypriv->dot11PrivacyKeyIndex; + break; + case _TKIP_: + case _AES_: + default: + prxattrib->key_index = psecuritypriv->dot118021XGrpKeyid; + break; + } + } + } + + if((prxattrib->encrypt>0) && ((prxattrib->bdecrypted==0) ||(psecuritypriv->sw_decrypt==_TRUE))) + { + +#ifdef CONFIG_CONCURRENT_MODE + if(!IS_MCAST(prxattrib->ra))//bc/mc packets use sw decryption for concurrent mode +#endif + psecuritypriv->hw_decrypted=_FALSE; + + #ifdef DBG_RX_DECRYPTOR + DBG_871X("[%s] %d:prxstat->bdecrypted:%d, prxattrib->encrypt:%d, Setting psecuritypriv->hw_decrypted = %d\n", + __FUNCTION__, + __LINE__, + prxattrib->bdecrypted, + prxattrib->encrypt, + psecuritypriv->hw_decrypted); + #endif + + switch(prxattrib->encrypt){ + case _WEP40_: + case _WEP104_: + DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_wep); + rtw_wep_decrypt(padapter, (u8 *)precv_frame); + break; + case _TKIP_: + DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_tkip); + res = rtw_tkip_decrypt(padapter, (u8 *)precv_frame); + break; + case _AES_: + DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_aes); + res = rtw_aes_decrypt(padapter, (u8 * )precv_frame); + break; +#ifdef CONFIG_WAPI_SUPPORT + case _SMS4_: + DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_wapi); + rtw_sms4_decrypt(padapter, (u8 * )precv_frame); + break; +#endif + default: + break; + } + } + else if(prxattrib->bdecrypted==1 + && prxattrib->encrypt >0 + && (psecuritypriv->busetkipkey==1 || prxattrib->encrypt !=_TKIP_ ) + ) + { +#if 0 + if((prxstat->icv==1)&&(prxattrib->encrypt!=_AES_)) + { + psecuritypriv->hw_decrypted=_FALSE; + + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("psecuritypriv->hw_decrypted=_FALSE")); + + rtw_free_recvframe(precv_frame, &padapter->recvpriv.free_recv_queue); + + return_packet=NULL; + + } + else +#endif + { + DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_hw); + + psecuritypriv->hw_decrypted=_TRUE; + #ifdef DBG_RX_DECRYPTOR + DBG_871X("[%s] %d:prxstat->bdecrypted:%d, prxattrib->encrypt:%d, Setting psecuritypriv->hw_decrypted = %d\n", + __FUNCTION__, + __LINE__, + prxattrib->bdecrypted, + prxattrib->encrypt, + psecuritypriv->hw_decrypted); + + #endif + } + } + else { + DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_unknown); + #ifdef DBG_RX_DECRYPTOR + DBG_871X("[%s] %d:prxstat->bdecrypted:%d, prxattrib->encrypt:%d, Setting psecuritypriv->hw_decrypted = %d\n", + __FUNCTION__, + __LINE__, + prxattrib->bdecrypted, + prxattrib->encrypt, + psecuritypriv->hw_decrypted); + #endif + } + + if(res == _FAIL) + { + rtw_free_recvframe(return_packet,&padapter->recvpriv.free_recv_queue); + return_packet = NULL; + } + else + { + prxattrib->bdecrypted = _TRUE; + } + //recvframe_chkmic(adapter, precv_frame); //move to recvframme_defrag function + +_func_exit_; + + return return_packet; + +} +//###set the security information in the recv_frame +union recv_frame * portctrl(_adapter *adapter,union recv_frame * precv_frame); +union recv_frame * portctrl(_adapter *adapter,union recv_frame * precv_frame) +{ + u8 *psta_addr = NULL; + u8 *ptr; + uint auth_alg; + struct recv_frame_hdr *pfhdr; + struct sta_info *psta; + struct sta_priv *pstapriv ; + union recv_frame *prtnframe; + u16 ether_type=0; + u16 eapol_type = 0x888e;//for Funia BD's WPA issue + struct rx_pkt_attrib *pattrib; + +_func_enter_; + + pstapriv = &adapter->stapriv; + + auth_alg = adapter->securitypriv.dot11AuthAlgrthm; + + ptr = get_recvframe_data(precv_frame); + pfhdr = &precv_frame->u.hdr; + pattrib = &pfhdr->attrib; + psta_addr = pattrib->ta; + + prtnframe = NULL; + + psta = rtw_get_stainfo(pstapriv, psta_addr); + + RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("########portctrl:adapter->securitypriv.dot11AuthAlgrthm=%d\n",adapter->securitypriv.dot11AuthAlgrthm)); + + if(auth_alg==2) + { + if ((psta!=NULL) && (psta->ieee8021x_blocked)) + { + //blocked + //only accept EAPOL frame + RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("########portctrl:psta->ieee8021x_blocked==1\n")); + + prtnframe=precv_frame; + + //get ether_type + ptr=ptr+pfhdr->attrib.hdrlen+pfhdr->attrib.iv_len+LLC_HEADER_SIZE; + _rtw_memcpy(ðer_type,ptr, 2); + ether_type= ntohs((unsigned short )ether_type); + + if (ether_type == eapol_type) { + prtnframe=precv_frame; + } + else { + //free this frame + rtw_free_recvframe(precv_frame, &adapter->recvpriv.free_recv_queue); + prtnframe=NULL; + } + } + else + { + //allowed + //check decryption status, and decrypt the frame if needed + RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("########portctrl:psta->ieee8021x_blocked==0\n")); + RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("portctrl:precv_frame->hdr.attrib.privacy=%x\n",precv_frame->u.hdr.attrib.privacy)); + + if (pattrib->bdecrypted == 0) + { + RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("portctrl:prxstat->decrypted=%x\n", pattrib->bdecrypted)); + } + + prtnframe=precv_frame; + //check is the EAPOL frame or not (Rekey) + //if(ether_type == eapol_type){ + // RT_TRACE(_module_rtl871x_recv_c_,_drv_notice_,("########portctrl:ether_type == 0x888e\n")); + //check Rekey + + // prtnframe=precv_frame; + //} + //else{ + // RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("########portctrl:ether_type=0x%04x\n", ether_type)); + //} + } + } + else + { + prtnframe=precv_frame; + } + +_func_exit_; + + return prtnframe; + +} + +sint recv_decache(union recv_frame *precv_frame, u8 bretry, struct stainfo_rxcache *prxcache); +sint recv_decache(union recv_frame *precv_frame, u8 bretry, struct stainfo_rxcache *prxcache) +{ + sint tid = precv_frame->u.hdr.attrib.priority; + + u16 seq_ctrl = ( (precv_frame->u.hdr.attrib.seq_num&0xffff) << 4) | + (precv_frame->u.hdr.attrib.frag_num & 0xf); + +_func_enter_; + + if(tid>15) + { + RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("recv_decache, (tid>15)! seq_ctrl=0x%x, tid=0x%x\n", seq_ctrl, tid)); + + return _FAIL; + } + + if(1)//if(bretry) + { + if(seq_ctrl == prxcache->tid_rxseq[tid]) + { + RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("recv_decache, seq_ctrl=0x%x, tid=0x%x, tid_rxseq=0x%x\n", seq_ctrl, tid, prxcache->tid_rxseq[tid])); + + return _FAIL; + } + } + + prxcache->tid_rxseq[tid] = seq_ctrl; + +_func_exit_; + + return _SUCCESS; + +} + +void process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame); +void process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame) +{ +#ifdef CONFIG_AP_MODE + unsigned char pwrbit; + u8 *ptr = precv_frame->u.hdr.rx_data; + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta=NULL; + + psta = rtw_get_stainfo(pstapriv, pattrib->src); + + pwrbit = GetPwrMgt(ptr); + + if(psta) + { + if(pwrbit) + { + if(!(psta->state & WIFI_SLEEP_STATE)) + { + //psta->state |= WIFI_SLEEP_STATE; + //pstapriv->sta_dz_bitmap |= BIT(psta->aid); + + stop_sta_xmit(padapter, psta); + + //DBG_871X("to sleep, sta_dz_bitmap=%x\n", pstapriv->sta_dz_bitmap); + } + } + else + { + if(psta->state & WIFI_SLEEP_STATE) + { + //psta->state ^= WIFI_SLEEP_STATE; + //pstapriv->sta_dz_bitmap &= ~BIT(psta->aid); + + wakeup_sta_to_xmit(padapter, psta); + + //DBG_871X("to wakeup, sta_dz_bitmap=%x\n", pstapriv->sta_dz_bitmap); + } + } + + } + +#endif +} + +void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame); +void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame) +{ +#ifdef CONFIG_AP_MODE + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta=NULL; + + psta = rtw_get_stainfo(pstapriv, pattrib->src); + + if(!psta) return; + +#ifdef CONFIG_TDLS + if( !(psta->tdls_sta_state & TDLS_LINKED_STATE ) ) + { +#endif //CONFIG_TDLS + + if(!psta->qos_option) + return; + + if(!(psta->qos_info&0xf)) + return; + +#ifdef CONFIG_TDLS + } +#endif //CONFIG_TDLS + + if(psta->state&WIFI_SLEEP_STATE) + { + u8 wmmps_ac=0; + + switch(pattrib->priority) + { + case 1: + case 2: + wmmps_ac = psta->uapsd_bk&BIT(1); + break; + case 4: + case 5: + wmmps_ac = psta->uapsd_vi&BIT(1); + break; + case 6: + case 7: + wmmps_ac = psta->uapsd_vo&BIT(1); + break; + case 0: + case 3: + default: + wmmps_ac = psta->uapsd_be&BIT(1); + break; + } + + if(wmmps_ac) + { + if(psta->sleepq_ac_len>0) + { + //process received triggered frame + xmit_delivery_enabled_frames(padapter, psta); + } + else + { + //issue one qos null frame with More data bit = 0 and the EOSP bit set (=1) + issue_qos_nulldata(padapter, psta->hwaddr, (u16)pattrib->priority, 0, 0); + } + } + + } + + +#endif + +} + +#ifdef CONFIG_TDLS +sint OnTDLS(_adapter *adapter, union recv_frame *precv_frame) +{ + struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib; + sint ret = _SUCCESS; + u8 *paction = get_recvframe_data(precv_frame); + u8 category_field = 1; +#ifdef CONFIG_WFD + u8 WFA_OUI[3] = { 0x50, 0x6f, 0x9a }; +#endif /* CONFIG_WFD */ + struct tdls_info *ptdlsinfo = &(adapter->tdlsinfo); + + /* point to action field */ + paction+=pattrib->hdrlen + + pattrib->iv_len + + SNAP_SIZE + + ETH_TYPE_LEN + + PAYLOAD_TYPE_LEN + + category_field; + + DBG_871X("[TDLS] Recv %s from "MAC_FMT" with SeqNum = %d \n", rtw_tdls_action_txt(*paction), MAC_ARG(pattrib->src), GetSequence(get_recvframe_data(precv_frame))); + + if (hal_chk_wl_func(adapter, WL_FUNC_TDLS) == _FALSE) { + DBG_871X("Ignore tdls frame since hal doesn't support tdls\n"); + ret = _FAIL; + return ret; + } + + if (ptdlsinfo->tdls_enable == _FALSE) { + DBG_871X("recv tdls frame, " + "but tdls haven't enabled\n"); + ret = _FAIL; + return ret; + } + + switch(*paction){ + case TDLS_SETUP_REQUEST: + ret=On_TDLS_Setup_Req(adapter, precv_frame); + break; + case TDLS_SETUP_RESPONSE: + ret=On_TDLS_Setup_Rsp(adapter, precv_frame); + break; + case TDLS_SETUP_CONFIRM: + ret=On_TDLS_Setup_Cfm(adapter, precv_frame); + break; + case TDLS_TEARDOWN: + ret=On_TDLS_Teardown(adapter, precv_frame); + break; + case TDLS_DISCOVERY_REQUEST: + ret=On_TDLS_Dis_Req(adapter, precv_frame); + break; + case TDLS_PEER_TRAFFIC_INDICATION: + ret=On_TDLS_Peer_Traffic_Indication(adapter, precv_frame); + break; + case TDLS_PEER_TRAFFIC_RESPONSE: + ret=On_TDLS_Peer_Traffic_Rsp(adapter, precv_frame); + break; +#ifdef CONFIG_TDLS_CH_SW + case TDLS_CHANNEL_SWITCH_REQUEST: + ret=On_TDLS_Ch_Switch_Req(adapter, precv_frame); + break; + case TDLS_CHANNEL_SWITCH_RESPONSE: + ret=On_TDLS_Ch_Switch_Rsp(adapter, precv_frame); + break; +#endif +#ifdef CONFIG_WFD + /* First byte of WFA OUI */ + case 0x50: + if (_rtw_memcmp(WFA_OUI, paction, 3)) { + /* Probe request frame */ + if (*(paction + 3) == 0x04) { + /* WFDTDLS: for sigma test, do not setup direct link automatically */ + ptdlsinfo->dev_discovered = _TRUE; + DBG_871X("recv tunneled probe request frame\n"); + issue_tunneled_probe_rsp(adapter, precv_frame); + } + /* Probe response frame */ + if (*(paction + 3) == 0x05) { + /* WFDTDLS: for sigma test, do not setup direct link automatically */ + ptdlsinfo->dev_discovered = _TRUE; + DBG_871X("recv tunneled probe response frame\n"); + } + } + break; +#endif /* CONFIG_WFD */ + default: + DBG_871X("receive TDLS frame %d but not support\n", *paction); + ret=_FAIL; + break; + } + +exit: + return ret; + +} +#endif /* CONFIG_TDLS */ + +void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_info*sta); +void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_info*sta) +{ + int sz; + struct sta_info *psta = NULL; + struct stainfo_stats *pstats = NULL; + struct rx_pkt_attrib *pattrib = & prframe->u.hdr.attrib; + struct recv_priv *precvpriv = &padapter->recvpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + sz = get_recvframe_len(prframe); + precvpriv->rx_bytes += sz; + + padapter->mlmepriv.LinkDetectInfo.NumRxOkInPeriod++; + + if( (!MacAddr_isBcst(pattrib->dst)) && (!IS_MCAST(pattrib->dst))){ + padapter->mlmepriv.LinkDetectInfo.NumRxUnicastOkInPeriod++; + } + + if(sta) + psta = sta; + else + psta = prframe->u.hdr.psta; + + if(psta) + { + pstats = &psta->sta_stats; + + pstats->rx_data_pkts++; + pstats->rx_bytes += sz; + + /*record rx packets for every tid*/ + pstats->rx_data_qos_pkts[pattrib->priority]++; + +#ifdef CONFIG_TDLS + if(psta->tdls_sta_state & TDLS_LINKED_STATE) + { + struct sta_info *pap_sta = NULL; + pap_sta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv)); + if(pap_sta) + { + pstats = &pap_sta->sta_stats; + pstats->rx_data_pkts++; + pstats->rx_bytes += sz; + } + } +#endif //CONFIG_TDLS + } + +#ifdef CONFIG_CHECK_LEAVE_LPS + traffic_check_for_leave_lps(padapter, _FALSE, 0); +#endif //CONFIG_LPS + +} + +sint sta2sta_data_frame( + _adapter *adapter, + union recv_frame *precv_frame, + struct sta_info**psta +); +sint sta2sta_data_frame( + _adapter *adapter, + union recv_frame *precv_frame, + struct sta_info**psta +) +{ + u8 *ptr = precv_frame->u.hdr.rx_data; + sint ret = _SUCCESS; + struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib; + struct sta_priv *pstapriv = &adapter->stapriv; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + u8 *mybssid = get_bssid(pmlmepriv); + u8 *myhwaddr = adapter_mac_addr(adapter); + u8 * sta_addr = NULL; + sint bmcast = IS_MCAST(pattrib->dst); + +#ifdef CONFIG_TDLS + struct tdls_info *ptdlsinfo = &adapter->tdlsinfo; +#ifdef CONFIG_TDLS_CH_SW + struct tdls_ch_switch *pchsw_info = &ptdlsinfo->chsw_info; +#endif + struct sta_info *ptdls_sta=NULL; + u8 *psnap_type=ptr+pattrib->hdrlen + pattrib->iv_len+SNAP_SIZE; + //frame body located after [+2]: ether-type, [+1]: payload type + u8 *pframe_body = psnap_type+2+1; +#endif + +_func_enter_; + + //DBG_871X("[%s] %d, seqnum:%d\n", __FUNCTION__, __LINE__, pattrib->seq_num); + + if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) + { + + // filter packets that SA is myself or multicast or broadcast + if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)){ + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" SA==myself \n")); + ret= _FAIL; + goto exit; + } + + if( (!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN)) && (!bmcast) ){ + ret= _FAIL; + goto exit; + } + + if( _rtw_memcmp(pattrib->bssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || + _rtw_memcmp(mybssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || + (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN)) ) { + ret= _FAIL; + goto exit; + } + + sta_addr = pattrib->src; + + } + else if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) + { +#ifdef CONFIG_TDLS + + /* direct link data transfer */ + if (ptdlsinfo->link_established == _TRUE) { + ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->src); + if (ptdls_sta == NULL) { + ret=_FAIL; + goto exit; + } else if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) { + /* filter packets that SA is myself or multicast or broadcast */ + if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)) { + ret= _FAIL; + goto exit; + } + /* da should be for me */ + if ((!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN)) && (!bmcast)) { + ret= _FAIL; + goto exit; + } + /* check BSSID */ + if (_rtw_memcmp(pattrib->bssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || + _rtw_memcmp(mybssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || + (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN))) { + ret= _FAIL; + goto exit; + } + +#ifdef CONFIG_TDLS_CH_SW + if(ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE) { + if (adapter->mlmeextpriv.cur_channel != rtw_get_oper_ch(adapter)) { + pchsw_info->ch_sw_state |= TDLS_PEER_AT_OFF_STATE; + if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE)) + _cancel_timer_ex(&ptdls_sta->ch_sw_timer); + /* On_TDLS_Peer_Traffic_Rsp(adapter, precv_frame); */ + } + } +#endif + + /* process UAPSD tdls sta */ + process_pwrbit_data(adapter, precv_frame); + + /* if NULL-frame, check pwrbit */ + if ((GetFrameSubType(ptr) & WIFI_DATA_NULL) == WIFI_DATA_NULL) { + /* NULL-frame with pwrbit=1, buffer_STA should buffer frames for sleep_STA */ + if (GetPwrMgt(ptr)) { + /* it would be triggered when we are off channel and receiving NULL DATA */ + /* we can confirm that peer STA is at off channel */ + DBG_871X("TDLS: recv peer null frame with pwr bit 1\n"); + //ptdls_sta->tdls_sta_state|=TDLS_PEER_SLEEP_STATE; + } + + /* TODO: Updated BSSID's seq. */ + //DBG_871X("drop Null Data\n"); + ptdls_sta->tdls_sta_state &= ~(TDLS_WAIT_PTR_STATE); + ret= _FAIL; + goto exit; + } + + /* receive some of all TDLS management frames, process it at ON_TDLS */ + if (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_TDLS, 2)) { + ret= OnTDLS(adapter, precv_frame); + goto exit; + } + + if ((GetFrameSubType(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) { + process_wmmps_data(adapter, precv_frame); + } + + ptdls_sta->tdls_sta_state &= ~(TDLS_WAIT_PTR_STATE); + + } + + sta_addr = pattrib->src; + + } + else +#endif /* CONFIG_TDLS */ + { + // For Station mode, sa and bssid should always be BSSID, and DA is my mac-address + if(!_rtw_memcmp(pattrib->bssid, pattrib->src, ETH_ALEN) ) + { + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("bssid != TA under STATION_MODE; drop pkt\n")); + ret= _FAIL; + goto exit; + } + + sta_addr = pattrib->bssid; + } + + } + else if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + { + if (bmcast) + { + // For AP mode, if DA == MCAST, then BSSID should be also MCAST + if (!IS_MCAST(pattrib->bssid)){ + ret= _FAIL; + goto exit; + } + } + else // not mc-frame + { + // For AP mode, if DA is non-MCAST, then it must be BSSID, and bssid == BSSID + if(!_rtw_memcmp(pattrib->bssid, pattrib->dst, ETH_ALEN)) { + ret= _FAIL; + goto exit; + } + + sta_addr = pattrib->src; + } + + } + else if(check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) + { + _rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->src, GetAddr2Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); + _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); + + sta_addr = mybssid; + } + else + { + ret = _FAIL; + } + + + + if(bmcast) + *psta = rtw_get_bcmc_stainfo(adapter); + else + *psta = rtw_get_stainfo(pstapriv, sta_addr); // get ap_info + +#ifdef CONFIG_TDLS + if(ptdls_sta != NULL) + { + *psta = ptdls_sta; + } +#endif //CONFIG_TDLS + + if (*psta == NULL) { + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("can't get psta under sta2sta_data_frame ; drop pkt\n")); +#ifdef CONFIG_MP_INCLUDED + if (adapter->registrypriv.mp_mode == 1) + { + if(check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) + adapter->mppriv.rx_pktloss++; + } +#endif + ret= _FAIL; + goto exit; + } + +exit: +_func_exit_; + return ret; + +} + +sint ap2sta_data_frame( + _adapter *adapter, + union recv_frame *precv_frame, + struct sta_info**psta ); +sint ap2sta_data_frame( + _adapter *adapter, + union recv_frame *precv_frame, + struct sta_info**psta ) +{ + u8 *ptr = precv_frame->u.hdr.rx_data; + struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib; + sint ret = _SUCCESS; + struct sta_priv *pstapriv = &adapter->stapriv; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + u8 *mybssid = get_bssid(pmlmepriv); + u8 *myhwaddr = adapter_mac_addr(adapter); + sint bmcast = IS_MCAST(pattrib->dst); + +_func_enter_; + + if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) + && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE + || check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE ) + ) + { + + // filter packets that SA is myself or multicast or broadcast + if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)){ + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" SA==myself \n")); + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s SA="MAC_FMT", myhwaddr="MAC_FMT"\n", + __FUNCTION__, MAC_ARG(pattrib->src), MAC_ARG(myhwaddr)); + #endif + ret= _FAIL; + goto exit; + } + + // da should be for me + if((!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN))&& (!bmcast)) + { + RT_TRACE(_module_rtl871x_recv_c_,_drv_info_, + (" ap2sta_data_frame: compare DA fail; DA="MAC_FMT"\n", MAC_ARG(pattrib->dst))); + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s DA="MAC_FMT"\n", __func__, MAC_ARG(pattrib->dst)); + #endif + ret= _FAIL; + goto exit; + } + + + // check BSSID + if( _rtw_memcmp(pattrib->bssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || + _rtw_memcmp(mybssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || + (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN)) ) + { + RT_TRACE(_module_rtl871x_recv_c_,_drv_info_, + (" ap2sta_data_frame: compare BSSID fail ; BSSID="MAC_FMT"\n", MAC_ARG(pattrib->bssid))); + RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("mybssid="MAC_FMT"\n", MAC_ARG(mybssid))); + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s BSSID="MAC_FMT", mybssid="MAC_FMT"\n", + __FUNCTION__, MAC_ARG(pattrib->bssid), MAC_ARG(mybssid)); + DBG_871X( "this adapter = %d, buddy adapter = %d\n", adapter->adapter_type, adapter->pbuddy_adapter->adapter_type ); + #endif + + if(!bmcast) + { + DBG_871X("issue_deauth to the nonassociated ap=" MAC_FMT " for the reason(7)\n", MAC_ARG(pattrib->bssid)); + issue_deauth(adapter, pattrib->bssid, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA); + } + + ret= _FAIL; + goto exit; + } + + if(bmcast) + *psta = rtw_get_bcmc_stainfo(adapter); + else + *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); // get ap_info + + if (*psta == NULL) { + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("ap2sta: can't get psta under STATION_MODE ; drop pkt\n")); + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s can't get psta under STATION_MODE ; drop pkt\n", __FUNCTION__); + #endif + ret= _FAIL; + goto exit; + } + + if ((GetFrameSubType(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) { + } + + if (GetFrameSubType(ptr) & BIT(6)) { + /* No data, will not indicate to upper layer, temporily count it here */ + count_rx_stats(adapter, precv_frame, *psta); + ret = RTW_RX_HANDLED; + goto exit; + } + + } + else if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) && + (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ) + { + _rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->src, GetAddr2Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); + _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); + + // + if(adapter->mppriv.bRTWSmbCfg==_FALSE) + _rtw_memcpy(pattrib->bssid, mybssid, ETH_ALEN); + + + *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); // get sta_info + if (*psta == NULL) { + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("can't get psta under MP_MODE ; drop pkt\n")); + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s can't get psta under WIFI_MP_STATE ; drop pkt\n", __FUNCTION__); + #endif + ret= _FAIL; + goto exit; + } + + + } + else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + { + /* Special case */ + ret = RTW_RX_HANDLED; + goto exit; + } + else + { + if(_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN)&& (!bmcast)) + { + *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); // get sta_info + if (*psta == NULL) + { + + //for AP multicast issue , modify by yiwei + static u32 send_issue_deauth_time=0; + + //DBG_871X("After send deauth , %u ms has elapsed.\n", rtw_get_passing_time_ms(send_issue_deauth_time)); + + if(rtw_get_passing_time_ms(send_issue_deauth_time) > 10000 || send_issue_deauth_time == 0 ) + { + send_issue_deauth_time = rtw_get_current_time(); + + DBG_871X("issue_deauth to the ap=" MAC_FMT " for the reason(7)\n", MAC_ARG(pattrib->bssid)); + + issue_deauth(adapter, pattrib->bssid, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA); + } + } + } + + ret = _FAIL; + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s fw_state:0x%x\n", __FUNCTION__, get_fwstate(pmlmepriv)); + #endif + } + +exit: + +_func_exit_; + + return ret; + +} + +sint sta2ap_data_frame( + _adapter *adapter, + union recv_frame *precv_frame, + struct sta_info**psta ); +sint sta2ap_data_frame( + _adapter *adapter, + union recv_frame *precv_frame, + struct sta_info**psta ) +{ + u8 *ptr = precv_frame->u.hdr.rx_data; + struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib; + struct sta_priv *pstapriv = &adapter->stapriv; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + unsigned char *mybssid = get_bssid(pmlmepriv); + sint ret=_SUCCESS; + +_func_enter_; + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + { + //For AP mode, RA=BSSID, TX=STA(SRC_ADDR), A3=DST_ADDR + if(!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN)) + { + ret= _FAIL; + goto exit; + } + + *psta = rtw_get_stainfo(pstapriv, pattrib->src); + if (*psta == NULL) + { + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("can't get psta under AP_MODE; drop pkt\n")); + DBG_871X("issue_deauth to sta=" MAC_FMT " for the reason(7)\n", MAC_ARG(pattrib->src)); + + issue_deauth(adapter, pattrib->src, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA); + + ret = RTW_RX_HANDLED; + goto exit; + } + + process_pwrbit_data(adapter, precv_frame); + + if ((GetFrameSubType(ptr) & WIFI_QOS_DATA_TYPE) == WIFI_QOS_DATA_TYPE) { + process_wmmps_data(adapter, precv_frame); + } + + if (GetFrameSubType(ptr) & BIT(6)) { + /* No data, will not indicate to upper layer, temporily count it here */ + count_rx_stats(adapter, precv_frame, *psta); + ret = RTW_RX_HANDLED; + goto exit; + } + } + else if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) && + (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ) + { + //DBG_871X("%s ,in WIFI_MP_STATE \n",__func__); + _rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->src, GetAddr2Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); + _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); + // + if(adapter->mppriv.bRTWSmbCfg == _FALSE) + _rtw_memcpy(pattrib->bssid, mybssid, ETH_ALEN); + + *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); // get sta_info + if (*psta == NULL) { + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("can't get psta under MP_MODE ; drop pkt\n")); + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s can't get psta under WIFI_MP_STATE ; drop pkt\n", __FUNCTION__); + #endif + ret= _FAIL; + goto exit; + } + + } + else { + u8 *myhwaddr = adapter_mac_addr(adapter); + if (!_rtw_memcmp(pattrib->ra, myhwaddr, ETH_ALEN)) { + ret = RTW_RX_HANDLED; + goto exit; + } + DBG_871X("issue_deauth to sta=" MAC_FMT " for the reason(7)\n", MAC_ARG(pattrib->src)); + issue_deauth(adapter, pattrib->src, WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA); + ret = RTW_RX_HANDLED; + goto exit; + } + +exit: + +_func_exit_; + + return ret; + +} + +sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame); +sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame) +{ + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 *pframe = precv_frame->u.hdr.rx_data; + struct sta_info *psta=NULL; + //uint len = precv_frame->u.hdr.len; + + //DBG_871X("+validate_recv_ctrl_frame\n"); + + if (GetFrameType(pframe) != WIFI_CTRL_TYPE) + { + return _FAIL; + } + + //receive the frames that ra(a1) is my address + if (!_rtw_memcmp(GetAddr1Ptr(pframe), adapter_mac_addr(padapter), ETH_ALEN)) + return _FAIL; + + psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe)); + if (psta==NULL) + { + return _FAIL; + } + + //for rx pkt statistics + psta->sta_stats.rx_ctrl_pkts++; + + //only handle ps-poll + if(GetFrameSubType(pframe) == WIFI_PSPOLL) + { +#ifdef CONFIG_AP_MODE + u16 aid; + u8 wmmps_ac=0; + + aid = GetAid(pframe); + if(psta->aid!=aid) + { + return _FAIL; + } + + switch(pattrib->priority) + { + case 1: + case 2: + wmmps_ac = psta->uapsd_bk&BIT(0); + break; + case 4: + case 5: + wmmps_ac = psta->uapsd_vi&BIT(0); + break; + case 6: + case 7: + wmmps_ac = psta->uapsd_vo&BIT(0); + break; + case 0: + case 3: + default: + wmmps_ac = psta->uapsd_be&BIT(0); + break; + } + + if(wmmps_ac) + return _FAIL; + + if(psta->state & WIFI_STA_ALIVE_CHK_STATE) + { + DBG_871X("%s alive check-rx ps-poll\n", __func__); + psta->expire_to = pstapriv->expire_to; + psta->state ^= WIFI_STA_ALIVE_CHK_STATE; + } + + if((psta->state&WIFI_SLEEP_STATE) && (pstapriv->sta_dz_bitmap&BIT(psta->aid))) + { + _irqL irqL; + _list *xmitframe_plist, *xmitframe_phead; + struct xmit_frame *pxmitframe=NULL; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + //_enter_critical_bh(&psta->sleep_q.lock, &irqL); + _enter_critical_bh(&pxmitpriv->lock, &irqL); + + xmitframe_phead = get_list_head(&psta->sleep_q); + xmitframe_plist = get_next(xmitframe_phead); + + if ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) + { + pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); + + xmitframe_plist = get_next(xmitframe_plist); + + rtw_list_delete(&pxmitframe->list); + + psta->sleepq_len--; + + if(psta->sleepq_len>0) + pxmitframe->attrib.mdata = 1; + else + pxmitframe->attrib.mdata = 0; + + pxmitframe->attrib.triggered = 1; + + //DBG_871X("handling ps-poll, q_len=%d, tim=%x\n", psta->sleepq_len, pstapriv->tim_bitmap); + +#if 0 + _exit_critical_bh(&psta->sleep_q.lock, &irqL); + if(rtw_hal_xmit(padapter, pxmitframe) == _TRUE) + { + rtw_os_xmit_complete(padapter, pxmitframe); + } + _enter_critical_bh(&psta->sleep_q.lock, &irqL); +#endif + rtw_hal_xmitframe_enqueue(padapter, pxmitframe); + + if(psta->sleepq_len==0) + { + pstapriv->tim_bitmap &= ~BIT(psta->aid); + + //DBG_871X("after handling ps-poll, tim=%x\n", pstapriv->tim_bitmap); + + //upate BCN for TIM IE + //update_BCNTIM(padapter); + update_beacon(padapter, _TIM_IE_, NULL, _TRUE); + } + + //_exit_critical_bh(&psta->sleep_q.lock, &irqL); + _exit_critical_bh(&pxmitpriv->lock, &irqL); + + } + else + { + //_exit_critical_bh(&psta->sleep_q.lock, &irqL); + _exit_critical_bh(&pxmitpriv->lock, &irqL); + + //DBG_871X("no buffered packets to xmit\n"); + if(pstapriv->tim_bitmap&BIT(psta->aid)) + { + if(psta->sleepq_len==0) + { + DBG_871X("no buffered packets to xmit\n"); + + //issue nulldata with More data bit = 0 to indicate we have no buffered packets + issue_nulldata_in_interrupt(padapter, psta->hwaddr, 0); + } + else + { + DBG_871X("error!psta->sleepq_len=%d\n", psta->sleepq_len); + psta->sleepq_len=0; + } + + pstapriv->tim_bitmap &= ~BIT(psta->aid); + + //upate BCN for TIM IE + //update_BCNTIM(padapter); + update_beacon(padapter, _TIM_IE_, NULL, _TRUE); + } + } + } +#endif //CONFIG_AP_MODE + } + else if(GetFrameSubType(pframe) == WIFI_NDPA) { +#ifdef CONFIG_BEAMFORMING + beamforming_get_ndpa_frame(padapter, precv_frame); +#endif/*CONFIG_BEAMFORMING*/ + } + + return _FAIL; + +} + +union recv_frame* recvframe_chk_defrag(PADAPTER padapter, union recv_frame *precv_frame); +sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame); +sint validate_recv_mgnt_frame(PADAPTER padapter, union recv_frame *precv_frame) +{ + //struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + + RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("+validate_recv_mgnt_frame\n")); + +#if 0 + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + { +#ifdef CONFIG_NATIVEAP_MLME + mgt_dispatcher(padapter, precv_frame); +#else + rtw_hostapd_mlme_rx(padapter, precv_frame); +#endif + } + else + { + mgt_dispatcher(padapter, precv_frame); + } +#endif + + precv_frame = recvframe_chk_defrag(padapter, precv_frame); + if (precv_frame == NULL) { + RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_,("%s: fragment packet\n",__FUNCTION__)); + return _SUCCESS; + } + + { + //for rx pkt statistics + struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, GetAddr2Ptr(precv_frame->u.hdr.rx_data)); + if (psta) { + psta->sta_stats.rx_mgnt_pkts++; + if (GetFrameSubType(precv_frame->u.hdr.rx_data) == WIFI_BEACON) + psta->sta_stats.rx_beacon_pkts++; + else if (GetFrameSubType(precv_frame->u.hdr.rx_data) == WIFI_PROBEREQ) + psta->sta_stats.rx_probereq_pkts++; + else if (GetFrameSubType(precv_frame->u.hdr.rx_data) == WIFI_PROBERSP) { + if (_rtw_memcmp(adapter_mac_addr(padapter), GetAddr1Ptr(precv_frame->u.hdr.rx_data), ETH_ALEN) == _TRUE) + psta->sta_stats.rx_probersp_pkts++; + else if (is_broadcast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data)) + || is_multicast_mac_addr(GetAddr1Ptr(precv_frame->u.hdr.rx_data))) + psta->sta_stats.rx_probersp_bm_pkts++; + else + psta->sta_stats.rx_probersp_uo_pkts++; + } + } + } + +#ifdef CONFIG_INTEL_PROXIM + if(padapter->proximity.proxim_on==_TRUE) + { + struct rx_pkt_attrib * pattrib=&precv_frame->u.hdr.attrib; + struct recv_stat* prxstat=( struct recv_stat * ) precv_frame->u.hdr.rx_head ; + u8 * pda,*psa,*pbssid,*ptr; + ptr=precv_frame->u.hdr.rx_data; + pda = get_da(ptr); + psa = get_sa(ptr); + pbssid = get_hdr_bssid(ptr); + + + _rtw_memcpy(pattrib->dst, pda, ETH_ALEN); + _rtw_memcpy(pattrib->src, psa, ETH_ALEN); + + _rtw_memcpy(pattrib->bssid, pbssid, ETH_ALEN); + + switch(pattrib->to_fr_ds) + { + case 0: + _rtw_memcpy(pattrib->ra, pda, ETH_ALEN); + _rtw_memcpy(pattrib->ta, psa, ETH_ALEN); + break; + + case 1: + _rtw_memcpy(pattrib->ra, pda, ETH_ALEN); + _rtw_memcpy(pattrib->ta, pbssid, ETH_ALEN); + break; + + case 2: + _rtw_memcpy(pattrib->ra, pbssid, ETH_ALEN); + _rtw_memcpy(pattrib->ta, psa, ETH_ALEN); + break; + + case 3: + _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->ta, GetAddr2Ptr(ptr), ETH_ALEN); + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" case 3\n")); + break; + + default: + break; + + } + pattrib->priority=0; + pattrib->hdrlen = pattrib->to_fr_ds==3 ? 30 : 24; + + padapter->proximity.proxim_rx(padapter,precv_frame); + } +#endif + mgt_dispatcher(padapter, precv_frame); + + return _SUCCESS; + +} + +sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame); +sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) +{ + u8 bretry; + u8 *psa, *pda, *pbssid; + struct sta_info *psta = NULL; + u8 *ptr = precv_frame->u.hdr.rx_data; + struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib; + struct sta_priv *pstapriv = &adapter->stapriv; + struct security_priv *psecuritypriv = &adapter->securitypriv; + sint ret = _SUCCESS; + +_func_enter_; + + bretry = GetRetry(ptr); + pda = get_da(ptr); + psa = get_sa(ptr); + pbssid = get_hdr_bssid(ptr); + + if(pbssid == NULL){ + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s pbssid == NULL\n", __func__); + #endif + ret= _FAIL; + goto exit; + } + + _rtw_memcpy(pattrib->dst, pda, ETH_ALEN); + _rtw_memcpy(pattrib->src, psa, ETH_ALEN); + + _rtw_memcpy(pattrib->bssid, pbssid, ETH_ALEN); + + switch(pattrib->to_fr_ds) + { + case 0: + _rtw_memcpy(pattrib->ra, pda, ETH_ALEN); + _rtw_memcpy(pattrib->ta, psa, ETH_ALEN); + ret = sta2sta_data_frame(adapter, precv_frame, &psta); + break; + + case 1: + _rtw_memcpy(pattrib->ra, pda, ETH_ALEN); + _rtw_memcpy(pattrib->ta, pbssid, ETH_ALEN); + ret = ap2sta_data_frame(adapter, precv_frame, &psta); + break; + + case 2: + _rtw_memcpy(pattrib->ra, pbssid, ETH_ALEN); + _rtw_memcpy(pattrib->ta, psa, ETH_ALEN); + ret = sta2ap_data_frame(adapter, precv_frame, &psta); + break; + + case 3: + _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->ta, GetAddr2Ptr(ptr), ETH_ALEN); + ret =_FAIL; + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" case 3\n")); + break; + + default: + ret =_FAIL; + break; + + } + + if(ret ==_FAIL){ + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s case:%d, res:%d\n", __FUNCTION__, pattrib->to_fr_ds, ret); + #endif + goto exit; + } else if (ret == RTW_RX_HANDLED) { + goto exit; + } + + + if(psta==NULL){ + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" after to_fr_ds_chk; psta==NULL \n")); + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s psta == NULL\n", __func__); + #endif + ret= _FAIL; + goto exit; + } + + //psta->rssi = prxcmd->rssi; + //psta->signal_quality= prxcmd->sq; + precv_frame->u.hdr.psta = psta; + + + pattrib->amsdu=0; + pattrib->ack_policy = 0; + //parsing QC field + if(pattrib->qos == 1) + { + pattrib->priority = GetPriority((ptr + 24)); + pattrib->ack_policy = GetAckpolicy((ptr + 24)); + pattrib->amsdu = GetAMsdu((ptr + 24)); + pattrib->hdrlen = pattrib->to_fr_ds==3 ? 32 : 26; + + if(pattrib->priority!=0 && pattrib->priority!=3) + adapter->recvpriv.bIsAnyNonBEPkts = _TRUE; + else + adapter->recvpriv.bIsAnyNonBEPkts = _FALSE; + } + else + { + pattrib->priority=0; + pattrib->hdrlen = pattrib->to_fr_ds==3 ? 30 : 24; + } + + + if(pattrib->order)//HT-CTRL 11n + { + pattrib->hdrlen += 4; + } + + precv_frame->u.hdr.preorder_ctrl = &psta->recvreorder_ctrl[pattrib->priority]; + + // decache, drop duplicate recv packets + if(recv_decache(precv_frame, bretry, &psta->sta_recvpriv.rxcache) == _FAIL) + { + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("decache : drop pkt\n")); + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s recv_decache return _FAIL\n", __func__); + #endif + ret= _FAIL; + goto exit; + } + + if(pattrib->privacy){ + + RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("validate_recv_data_frame:pattrib->privacy=%x\n", pattrib->privacy)); + RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n ^^^^^^^^^^^IS_MCAST(pattrib->ra(0x%02x))=%d^^^^^^^^^^^^^^^6\n", pattrib->ra[0],IS_MCAST(pattrib->ra))); + +#ifdef CONFIG_TDLS + if((psta->tdls_sta_state & TDLS_LINKED_STATE) && (psta->dot118021XPrivacy==_AES_)) + { + pattrib->encrypt=psta->dot118021XPrivacy; + } + else +#endif //CONFIG_TDLS + GET_ENCRY_ALGO(psecuritypriv, psta, pattrib->encrypt, IS_MCAST(pattrib->ra)); + + RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n pattrib->encrypt=%d\n",pattrib->encrypt)); + + SET_ICE_IV_LEN(pattrib->iv_len, pattrib->icv_len, pattrib->encrypt); + } + else + { + pattrib->encrypt = 0; + pattrib->iv_len = pattrib->icv_len = 0; + } + +exit: + +_func_exit_; + + return ret; +} + +#ifdef CONFIG_IEEE80211W +static sint validate_80211w_mgmt(_adapter *adapter, union recv_frame *precv_frame) +{ + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib; + u8 *ptr = precv_frame->u.hdr.rx_data; + struct sta_info *psta; + struct sta_priv *pstapriv = &adapter->stapriv; + u8 type; + u8 subtype; + + type = GetFrameType(ptr); + subtype = GetFrameSubType(ptr); //bit(7)~bit(2) + + if (adapter->securitypriv.binstallBIPkey == _TRUE) + { + //unicast management frame decrypt + if(pattrib->privacy && !(IS_MCAST(GetAddr1Ptr(ptr))) && + (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC || subtype == WIFI_ACTION)) + { + u8 *ppp, *mgmt_DATA; + u32 data_len=0; + ppp = GetAddr2Ptr(ptr); + + pattrib->bdecrypted = 0; + pattrib->encrypt = _AES_; + pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); + //set iv and icv length + SET_ICE_IV_LEN(pattrib->iv_len, pattrib->icv_len, pattrib->encrypt); + _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->ta, GetAddr2Ptr(ptr), ETH_ALEN); + //actual management data frame body + data_len = pattrib->pkt_len - pattrib->hdrlen - pattrib->iv_len - pattrib->icv_len; + mgmt_DATA = rtw_zmalloc(data_len); + if(mgmt_DATA == NULL) + { + DBG_871X("%s mgmt allocate fail !!!!!!!!!\n", __FUNCTION__); + goto validate_80211w_fail; + } + /* //dump the packet content before decrypt + { + int pp; + printk("pattrib->pktlen = %d =>", pattrib->pkt_len); + for(pp=0;pp< pattrib->pkt_len; pp++) + printk(" %02x ", ptr[pp]); + printk("\n"); + }*/ + + precv_frame = decryptor(adapter, precv_frame); + //save actual management data frame body + _rtw_memcpy(mgmt_DATA, ptr+pattrib->hdrlen+pattrib->iv_len, data_len); + //overwrite the iv field + _rtw_memcpy(ptr+pattrib->hdrlen, mgmt_DATA, data_len); + //remove the iv and icv length + pattrib->pkt_len = pattrib->pkt_len - pattrib->iv_len - pattrib->icv_len; + rtw_mfree(mgmt_DATA, data_len); + /* //print packet content after decryption + { + int pp; + printk("after decryption pattrib->pktlen = %d @@=>", pattrib->pkt_len); + for(pp=0;pp< pattrib->pkt_len; pp++) + printk(" %02x ", ptr[pp]); + printk("\n"); + }*/ + if(!precv_frame) + { + DBG_871X("%s mgmt descrypt fail !!!!!!!!!\n", __FUNCTION__); + goto validate_80211w_fail; + } + } + else if(IS_MCAST(GetAddr1Ptr(ptr)) && + (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC)) + { + sint BIP_ret = _SUCCESS; + //verify BIP MME IE of broadcast/multicast de-auth/disassoc packet + BIP_ret = rtw_BIP_verify(adapter, (u8 * )precv_frame); + if(BIP_ret == _FAIL) + { + //DBG_871X("802.11w BIP verify fail\n"); + goto validate_80211w_fail; + } + else if(BIP_ret == RTW_RX_HANDLED) + { + DBG_871X("802.11w recv none protected packet\n"); + //drop pkt, don't issue sa query request + /* issue_action_SA_Query(adapter, NULL, 0, 0, 0); */ + goto validate_80211w_fail; + } + }//802.11w protect + else + { + psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(ptr)); + + if (subtype == WIFI_ACTION && psta && psta->bpairwise_key_installed == _TRUE) { + //according 802.11-2012 standard, these five types are not robust types + if( ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_PUBLIC && + ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_HT && + ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_UNPROTECTED_WNM && + ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_SELF_PROTECTED && + ptr[WLAN_HDR_A3_LEN] != RTW_WLAN_CATEGORY_P2P) + { + DBG_871X("action frame category=%d should robust\n", ptr[WLAN_HDR_A3_LEN]); + goto validate_80211w_fail; + } + } + else if(subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC) + { + unsigned short reason; + reason = le16_to_cpu(*(unsigned short *)(ptr + WLAN_HDR_A3_LEN)); + DBG_871X("802.11w recv none protected packet, reason=%d\n", reason); + if(reason == 6 || reason == 7) + { + //issue sa query request + issue_action_SA_Query(adapter, NULL, 0, 0, IEEE80211W_RIGHT_KEY); + } + goto validate_80211w_fail; + } + } + } + return _SUCCESS; + +validate_80211w_fail: + return _FAIL; + +} +#endif //CONFIG_IEEE80211W + +static inline void dump_rx_packet(u8 *ptr) +{ + int i; + + DBG_871X("############################# \n"); + for(i=0; i<64;i=i+8) + DBG_871X("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:\n", *(ptr+i), + *(ptr+i+1), *(ptr+i+2) ,*(ptr+i+3) ,*(ptr+i+4),*(ptr+i+5), *(ptr+i+6), *(ptr+i+7)); + DBG_871X("############################# \n"); +} + +sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame); +sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) +{ + //shall check frame subtype, to / from ds, da, bssid + + //then call check if rx seq/frag. duplicated. + + u8 type; + u8 subtype; + sint retval = _SUCCESS; + + struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib; + + u8 *ptr = precv_frame->u.hdr.rx_data; + u8 ver =(unsigned char) (*ptr)&0x3 ; +#ifdef CONFIG_FIND_BEST_CHANNEL + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; +#endif + +#ifdef CONFIG_TDLS + struct tdls_info *ptdlsinfo = &adapter->tdlsinfo; +#endif //CONFIG_TDLS +#ifdef CONFIG_WAPI_SUPPORT + PRT_WAPI_T pWapiInfo = &adapter->wapiInfo; + struct recv_frame_hdr *phdr = &precv_frame->u.hdr; + u8 wai_pkt = 0; + u16 sc; + u8 external_len = 0; +#endif + +_func_enter_; + +#ifdef CONFIG_FIND_BEST_CHANNEL + if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) { + int ch_set_idx = rtw_ch_set_search_ch(pmlmeext->channel_set, rtw_get_oper_ch(adapter)); + if (ch_set_idx >= 0) + pmlmeext->channel_set[ch_set_idx].rx_count++; + } +#endif + +#ifdef CONFIG_TDLS + if(ptdlsinfo->ch_sensing==1 && ptdlsinfo->cur_channel !=0){ + ptdlsinfo->collect_pkt_num[ptdlsinfo->cur_channel-1]++; + } +#endif //CONFIG_TDLS + +#ifdef RTK_DMP_PLATFORM + if ( 0 ) + { + DBG_871X("++\n"); + { + int i; + for(i=0; i<64;i=i+8) + DBG_871X("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:", *(ptr+i), + *(ptr+i+1), *(ptr+i+2) ,*(ptr+i+3) ,*(ptr+i+4),*(ptr+i+5), *(ptr+i+6), *(ptr+i+7)); + + } + DBG_871X("--\n"); + } +#endif //RTK_DMP_PLATFORM + + //add version chk + if(ver!=0){ + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("validate_recv_data_frame fail! (ver!=0)\n")); + retval= _FAIL; + DBG_COUNTER(adapter->rx_logs.core_rx_pre_ver_err); + goto exit; + } + + type = GetFrameType(ptr); + subtype = GetFrameSubType(ptr); //bit(7)~bit(2) + + pattrib->to_fr_ds = get_tofr_ds(ptr); + + pattrib->frag_num = GetFragNum(ptr); + pattrib->seq_num = GetSequence(ptr); + + pattrib->pw_save = GetPwrMgt(ptr); + pattrib->mfrag = GetMFrag(ptr); + pattrib->mdata = GetMData(ptr); + pattrib->privacy = GetPrivacy(ptr); + pattrib->order = GetOrder(ptr); +#ifdef CONFIG_WAPI_SUPPORT + sc = (pattrib->seq_num<<4) | pattrib->frag_num; +#endif + +#if 1 //Dump rx packets +{ + u8 bDumpRxPkt = 0; + + rtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_RXPKT, &(bDumpRxPkt)); + if (bDumpRxPkt == 1) //dump all rx packets + dump_rx_packet(ptr); + else if ((bDumpRxPkt == 2) && (type == WIFI_MGT_TYPE)) + dump_rx_packet(ptr); + else if ((bDumpRxPkt == 3) && (type == WIFI_DATA_TYPE)) + dump_rx_packet(ptr); +} +#endif + switch (type) + { + case WIFI_MGT_TYPE: //mgnt + DBG_COUNTER(adapter->rx_logs.core_rx_pre_mgmt); +#ifdef CONFIG_IEEE80211W + if(validate_80211w_mgmt(adapter, precv_frame) == _FAIL) + { + retval = _FAIL; + DBG_COUNTER(adapter->rx_logs.core_rx_pre_mgmt_err_80211w); + break; + } +#endif //CONFIG_IEEE80211W + + retval = validate_recv_mgnt_frame(adapter, precv_frame); + if (retval == _FAIL) + { + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("validate_recv_mgnt_frame fail\n")); + DBG_COUNTER(adapter->rx_logs.core_rx_pre_mgmt_err); + } + retval = _FAIL; // only data frame return _SUCCESS + break; + case WIFI_CTRL_TYPE: //ctrl + DBG_COUNTER(adapter->rx_logs.core_rx_pre_ctrl); + retval = validate_recv_ctrl_frame(adapter, precv_frame); + if (retval == _FAIL) + { + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("validate_recv_ctrl_frame fail\n")); + DBG_COUNTER(adapter->rx_logs.core_rx_pre_ctrl_err); + } + retval = _FAIL; // only data frame return _SUCCESS + break; + case WIFI_DATA_TYPE: //data + DBG_COUNTER(adapter->rx_logs.core_rx_pre_data); +#ifdef CONFIG_WAPI_SUPPORT + if(pattrib->qos) + external_len = 2; + else + external_len= 0; + + wai_pkt = rtw_wapi_is_wai_packet(adapter,ptr); + + phdr->bIsWaiPacket = wai_pkt; + + if(wai_pkt !=0){ + if(sc != adapter->wapiInfo.wapiSeqnumAndFragNum) + { + adapter->wapiInfo.wapiSeqnumAndFragNum = sc; + } + else + { + retval = _FAIL; + DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_wapi_seq_err); + break; + } + } + else{ + + if(rtw_wapi_drop_for_key_absent(adapter,GetAddr2Ptr(ptr))){ + retval=_FAIL; + WAPI_TRACE(WAPI_RX,"drop for key absent for rx \n"); + DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_wapi_key_err); + break; + } + } + +#endif + + pattrib->qos = (subtype & BIT(7))? 1:0; + retval = validate_recv_data_frame(adapter, precv_frame); + if (retval == _FAIL) + { + struct recv_priv *precvpriv = &adapter->recvpriv; + //RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("validate_recv_data_frame fail\n")); + precvpriv->rx_drop++; + DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_err); + } + else if (retval == _SUCCESS) + { +#ifdef DBG_RX_DUMP_EAP + u8 bDumpRxPkt; + u16 eth_type; + + // dump eapol + rtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_RXPKT, &(bDumpRxPkt)); + // get ether_type + _rtw_memcpy(ð_type, ptr + pattrib->hdrlen + pattrib->iv_len + LLC_HEADER_SIZE, 2); + eth_type = ntohs((unsigned short) eth_type); + if ((bDumpRxPkt == 4) && (eth_type == 0x888e)) + dump_rx_packet(ptr); +#endif + } + else + { + DBG_COUNTER(adapter->rx_logs.core_rx_pre_data_handled); + } + break; + default: + DBG_COUNTER(adapter->rx_logs.core_rx_pre_unknown); + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("validate_recv_data_frame fail! type=0x%x\n", type)); + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME validate_recv_data_frame fail! type=0x%x\n", type); + #endif + retval = _FAIL; + break; + } + +exit: + +_func_exit_; + + return retval; +} + + +//remove the wlanhdr and add the eth_hdr +#if 1 + +sint wlanhdr_to_ethhdr ( union recv_frame *precvframe); +sint wlanhdr_to_ethhdr ( union recv_frame *precvframe) +{ + sint rmv_len; + u16 eth_type, len; + u8 bsnaphdr; + u8 *psnap_type; + struct ieee80211_snap_hdr *psnap; + + sint ret=_SUCCESS; + _adapter *adapter =precvframe->u.hdr.adapter; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + + u8 *ptr = get_recvframe_data(precvframe) ; // point to frame_ctrl field + struct rx_pkt_attrib *pattrib = & precvframe->u.hdr.attrib; + +_func_enter_; + + if(pattrib->encrypt){ + recvframe_pull_tail(precvframe, pattrib->icv_len); + } + + psnap=(struct ieee80211_snap_hdr *)(ptr+pattrib->hdrlen + pattrib->iv_len); + psnap_type=ptr+pattrib->hdrlen + pattrib->iv_len+SNAP_SIZE; + /* convert hdr + possible LLC headers into Ethernet header */ + //eth_type = (psnap_type[0] << 8) | psnap_type[1]; + if((_rtw_memcmp(psnap, rtw_rfc1042_header, SNAP_SIZE) && + (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_IPX, 2) == _FALSE) && + (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_APPLETALK_AARP, 2)==_FALSE) )|| + //eth_type != ETH_P_AARP && eth_type != ETH_P_IPX) || + _rtw_memcmp(psnap, rtw_bridge_tunnel_header, SNAP_SIZE)){ + /* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */ + bsnaphdr = _TRUE; + } + else { + /* Leave Ethernet header part of hdr and full payload */ + bsnaphdr = _FALSE; + } + + rmv_len = pattrib->hdrlen + pattrib->iv_len +(bsnaphdr?SNAP_SIZE:0); + len = precvframe->u.hdr.len - rmv_len; + + RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n===pattrib->hdrlen: %x, pattrib->iv_len:%x ===\n\n", pattrib->hdrlen, pattrib->iv_len)); + + _rtw_memcpy(ð_type, ptr+rmv_len, 2); + eth_type= ntohs((unsigned short )eth_type); //pattrib->ether_type + pattrib->eth_type = eth_type; + +#ifdef CONFIG_AUTO_AP_MODE + if (0x8899 == pattrib->eth_type) + { + struct sta_info *psta = precvframe->u.hdr.psta; + + DBG_871X("wlan rx: got eth_type=0x%x\n", pattrib->eth_type); + + if (psta && psta->isrc && psta->pid>0) + { + u16 rx_pid; + + rx_pid = *(u16*)(ptr+rmv_len+2); + + DBG_871X("wlan rx(pid=0x%x): sta("MAC_FMT") pid=0x%x\n", + rx_pid, MAC_ARG(psta->hwaddr), psta->pid); + + if(rx_pid == psta->pid) + { + int i; + u16 len = *(u16*)(ptr+rmv_len+4); + //u16 ctrl_type = *(u16*)(ptr+rmv_len+6); + + //DBG_871X("RC: len=0x%x, ctrl_type=0x%x\n", len, ctrl_type); + DBG_871X("RC: len=0x%x\n", len); + + for(i=0;idst, ETH_ALEN); + _rtw_memcpy(ptr+ETH_ALEN, pattrib->src, ETH_ALEN); + + if(!bsnaphdr) { + len = htons(len); + _rtw_memcpy(ptr+12, &len, 2); + } + } + +exiting: +_func_exit_; + return ret; + +} + +#else + +sint wlanhdr_to_ethhdr ( union recv_frame *precvframe) +{ + sint rmv_len; + u16 eth_type; + u8 bsnaphdr; + u8 *psnap_type; + struct ieee80211_snap_hdr *psnap; + + sint ret=_SUCCESS; + _adapter *adapter =precvframe->u.hdr.adapter; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + + u8* ptr = get_recvframe_data(precvframe) ; // point to frame_ctrl field + struct rx_pkt_attrib *pattrib = & precvframe->u.hdr.attrib; + struct _vlan *pvlan = NULL; + +_func_enter_; + + psnap=(struct ieee80211_snap_hdr *)(ptr+pattrib->hdrlen + pattrib->iv_len); + psnap_type=ptr+pattrib->hdrlen + pattrib->iv_len+SNAP_SIZE; + if (psnap->dsap==0xaa && psnap->ssap==0xaa && psnap->ctrl==0x03) + { + if (_rtw_memcmp(psnap->oui, oui_rfc1042, WLAN_IEEE_OUI_LEN)) + bsnaphdr=_TRUE;//wlan_pkt_format = WLAN_PKT_FORMAT_SNAP_RFC1042; + else if (_rtw_memcmp(psnap->oui, SNAP_HDR_APPLETALK_DDP, WLAN_IEEE_OUI_LEN) && + _rtw_memcmp(psnap_type, SNAP_ETH_TYPE_APPLETALK_DDP, 2) ) + bsnaphdr=_TRUE; //wlan_pkt_format = WLAN_PKT_FORMAT_APPLETALK; + else if (_rtw_memcmp( psnap->oui, oui_8021h, WLAN_IEEE_OUI_LEN)) + bsnaphdr=_TRUE; //wlan_pkt_format = WLAN_PKT_FORMAT_SNAP_TUNNEL; + else { + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("drop pkt due to invalid frame format!\n")); + ret= _FAIL; + goto exit; + } + + } else + bsnaphdr=_FALSE;//wlan_pkt_format = WLAN_PKT_FORMAT_OTHERS; + + rmv_len = pattrib->hdrlen + pattrib->iv_len +(bsnaphdr?SNAP_SIZE:0); + RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("===pattrib->hdrlen: %x, pattrib->iv_len:%x ===\n", pattrib->hdrlen, pattrib->iv_len)); + + if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) + { + ptr += rmv_len ; + *ptr = 0x87; + *(ptr+1) = 0x12; + + //back to original pointer + ptr -= rmv_len; + } + + ptr += rmv_len ; + + _rtw_memcpy(ð_type, ptr, 2); + eth_type= ntohs((unsigned short )eth_type); //pattrib->ether_type + ptr +=2; + + if(pattrib->encrypt){ + recvframe_pull_tail(precvframe, pattrib->icv_len); + } + + if(eth_type == 0x8100) //vlan + { + pvlan = (struct _vlan *) ptr; + + //eth_type = get_vlan_encap_proto(pvlan); + //eth_type = pvlan->h_vlan_encapsulated_proto;//? + rmv_len += 4; + ptr+=4; + } + + if(eth_type==0x0800)//ip + { + //struct iphdr* piphdr = (struct iphdr*) ptr; + //__u8 tos = (unsigned char)(pattrib->priority & 0xff); + + //piphdr->tos = tos; + + //if (piphdr->protocol == 0x06) + //{ + // RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("@@@===recv tcp len:%d @@@===\n", precvframe->u.hdr.len)); + //} + } + else if(eth_type==0x8712)// append rx status for mp test packets + { + //ptr -= 16; + //_rtw_memcpy(ptr, get_rxmem(precvframe), 16); + } + else + { +#ifdef PLATFORM_OS_XP + NDIS_PACKET_8021Q_INFO VlanPriInfo; + UINT32 UserPriority = precvframe->u.hdr.attrib.priority; + UINT32 VlanID = (pvlan!=NULL ? get_vlan_id(pvlan) : 0 ); + + VlanPriInfo.Value = // Get current value. + NDIS_PER_PACKET_INFO_FROM_PACKET(precvframe->u.hdr.pkt, Ieee8021QInfo); + + VlanPriInfo.TagHeader.UserPriority = UserPriority; + VlanPriInfo.TagHeader.VlanId = VlanID ; + + VlanPriInfo.TagHeader.CanonicalFormatId = 0; // Should be zero. + VlanPriInfo.TagHeader.Reserved = 0; // Should be zero. + NDIS_PER_PACKET_INFO_FROM_PACKET(precvframe->u.hdr.pkt, Ieee8021QInfo) = VlanPriInfo.Value; +#endif + } + + if(eth_type==0x8712)// append rx status for mp test packets + { + ptr = recvframe_pull(precvframe, (rmv_len-sizeof(struct ethhdr)+2)-24); + _rtw_memcpy(ptr, get_rxmem(precvframe), 24); + ptr+=24; + } + else + ptr = recvframe_pull(precvframe, (rmv_len-sizeof(struct ethhdr)+2)); + + _rtw_memcpy(ptr, pattrib->dst, ETH_ALEN); + _rtw_memcpy(ptr+ETH_ALEN, pattrib->src, ETH_ALEN); + + eth_type = htons((unsigned short)eth_type) ; + _rtw_memcpy(ptr+12, ð_type, 2); + +exit: + +_func_exit_; + + return ret; +} +#endif + + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) +#ifdef PLATFORM_LINUX +static void recvframe_expand_pkt( + PADAPTER padapter, + union recv_frame *prframe) +{ + struct recv_frame_hdr *pfhdr; + _pkt *ppkt; + u8 shift_sz; + u32 alloc_sz; + u8 *ptr; + + + pfhdr = &prframe->u.hdr; + + // 6 is for IP header 8 bytes alignment in QoS packet case. + if (pfhdr->attrib.qos) + shift_sz = 6; + else + shift_sz = 0; + + // for first fragment packet, need to allocate + // (1536 + RXDESC_SIZE + drvinfo_sz) to reassemble packet + // 8 is for skb->data 8 bytes alignment. +// alloc_sz = _RND(1536 + RXDESC_SIZE + pfhdr->attrib.drvinfosize + shift_sz + 8, 128); + alloc_sz = 1664; // round (1536 + 24 + 32 + shift_sz + 8) to 128 bytes alignment + + //3 1. alloc new skb + // prepare extra space for 4 bytes alignment + ppkt = rtw_skb_alloc(alloc_sz); + + if (!ppkt) return; // no way to expand + + //3 2. Prepare new skb to replace & release old skb + // force ppkt->data at 8-byte alignment address + skb_reserve(ppkt, 8 - ((SIZE_PTR)ppkt->data & 7)); + // force ip_hdr at 8-byte alignment address according to shift_sz + skb_reserve(ppkt, shift_sz); + + // copy data to new pkt + ptr = skb_put(ppkt, pfhdr->len); + if (ptr) + _rtw_memcpy(ptr, pfhdr->rx_data, pfhdr->len); + + rtw_skb_free(pfhdr->pkt); + + // attach new pkt to recvframe + pfhdr->pkt = ppkt; + pfhdr->rx_head = ppkt->head; + pfhdr->rx_data = ppkt->data; + pfhdr->rx_tail = skb_tail_pointer(ppkt); + pfhdr->rx_end = skb_end_pointer(ppkt); +} +#else +#warning "recvframe_expand_pkt not implement, defrag may crash system" +#endif +#endif + +//perform defrag +union recv_frame * recvframe_defrag(_adapter *adapter,_queue *defrag_q); +union recv_frame * recvframe_defrag(_adapter *adapter,_queue *defrag_q) +{ + _list *plist, *phead; + u8 *data,wlanhdr_offset; + u8 curfragnum; + struct recv_frame_hdr *pfhdr,*pnfhdr; + union recv_frame* prframe, *pnextrframe; + _queue *pfree_recv_queue; + +_func_enter_; + + curfragnum=0; + pfree_recv_queue=&adapter->recvpriv.free_recv_queue; + + phead = get_list_head(defrag_q); + plist = get_next(phead); + prframe = LIST_CONTAINOR(plist, union recv_frame, u); + pfhdr=&prframe->u.hdr; + rtw_list_delete(&(prframe->u.list)); + + if(curfragnum!=pfhdr->attrib.frag_num) + { + //the first fragment number must be 0 + //free the whole queue + rtw_free_recvframe(prframe, pfree_recv_queue); + rtw_free_recvframe_queue(defrag_q, pfree_recv_queue); + + return NULL; + } + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) +#ifndef CONFIG_SDIO_RX_COPY + recvframe_expand_pkt(adapter, prframe); +#endif +#endif + + curfragnum++; + + plist= get_list_head(defrag_q); + + plist = get_next(plist); + + data=get_recvframe_data(prframe); + + while(rtw_end_of_queue_search(phead, plist) == _FALSE) + { + pnextrframe = LIST_CONTAINOR(plist, union recv_frame , u); + pnfhdr=&pnextrframe->u.hdr; + + + //check the fragment sequence (2nd ~n fragment frame) + + if(curfragnum!=pnfhdr->attrib.frag_num) + { + //the fragment number must be increasing (after decache) + //release the defrag_q & prframe + rtw_free_recvframe(prframe, pfree_recv_queue); + rtw_free_recvframe_queue(defrag_q, pfree_recv_queue); + return NULL; + } + + curfragnum++; + + //copy the 2nd~n fragment frame's payload to the first fragment + //get the 2nd~last fragment frame's payload + + wlanhdr_offset = pnfhdr->attrib.hdrlen + pnfhdr->attrib.iv_len; + + recvframe_pull(pnextrframe, wlanhdr_offset); + + //append to first fragment frame's tail (if privacy frame, pull the ICV) + recvframe_pull_tail(prframe, pfhdr->attrib.icv_len); + + //memcpy + _rtw_memcpy(pfhdr->rx_tail, pnfhdr->rx_data, pnfhdr->len); + + recvframe_put(prframe, pnfhdr->len); + + pfhdr->attrib.icv_len=pnfhdr->attrib.icv_len; + plist = get_next(plist); + + }; + + //free the defrag_q queue and return the prframe + rtw_free_recvframe_queue(defrag_q, pfree_recv_queue); + + RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("Performance defrag!!!!!\n")); + +_func_exit_; + + return prframe; +} + +//check if need to defrag, if needed queue the frame to defrag_q +union recv_frame* recvframe_chk_defrag(PADAPTER padapter, union recv_frame *precv_frame) +{ + u8 ismfrag; + u8 fragnum; + u8 *psta_addr; + struct recv_frame_hdr *pfhdr; + struct sta_info *psta; + struct sta_priv *pstapriv; + _list *phead; + union recv_frame *prtnframe = NULL; + _queue *pfree_recv_queue, *pdefrag_q; + +_func_enter_; + + pstapriv = &padapter->stapriv; + + pfhdr = &precv_frame->u.hdr; + + pfree_recv_queue = &padapter->recvpriv.free_recv_queue; + + //need to define struct of wlan header frame ctrl + ismfrag = pfhdr->attrib.mfrag; + fragnum = pfhdr->attrib.frag_num; + + psta_addr = pfhdr->attrib.ta; + psta = rtw_get_stainfo(pstapriv, psta_addr); + if (psta == NULL) + { + u8 type = GetFrameType(pfhdr->rx_data); + if (type != WIFI_DATA_TYPE) { + psta = rtw_get_bcmc_stainfo(padapter); + pdefrag_q = &psta->sta_recvpriv.defrag_q; + } else + pdefrag_q = NULL; + } + else + pdefrag_q = &psta->sta_recvpriv.defrag_q; + + if ((ismfrag==0) && (fragnum==0)) + { + prtnframe = precv_frame;//isn't a fragment frame + } + + if (ismfrag==1) + { + //0~(n-1) fragment frame + //enqueue to defraf_g + if(pdefrag_q != NULL) + { + if(fragnum==0) + { + //the first fragment + if(_rtw_queue_empty(pdefrag_q) == _FALSE) + { + //free current defrag_q + rtw_free_recvframe_queue(pdefrag_q, pfree_recv_queue); + } + } + + + //Then enqueue the 0~(n-1) fragment into the defrag_q + + //_rtw_spinlock(&pdefrag_q->lock); + phead = get_list_head(pdefrag_q); + rtw_list_insert_tail(&pfhdr->list, phead); + //_rtw_spinunlock(&pdefrag_q->lock); + + RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("Enqueuq: ismfrag = %d, fragnum= %d\n", ismfrag,fragnum)); + + prtnframe=NULL; + + } + else + { + //can't find this ta's defrag_queue, so free this recv_frame + rtw_free_recvframe(precv_frame, pfree_recv_queue); + prtnframe=NULL; + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("Free because pdefrag_q ==NULL: ismfrag = %d, fragnum= %d\n", ismfrag, fragnum)); + } + + } + + if((ismfrag==0)&&(fragnum!=0)) + { + //the last fragment frame + //enqueue the last fragment + if(pdefrag_q != NULL) + { + //_rtw_spinlock(&pdefrag_q->lock); + phead = get_list_head(pdefrag_q); + rtw_list_insert_tail(&pfhdr->list,phead); + //_rtw_spinunlock(&pdefrag_q->lock); + + //call recvframe_defrag to defrag + RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("defrag: ismfrag = %d, fragnum= %d\n", ismfrag, fragnum)); + precv_frame = recvframe_defrag(padapter, pdefrag_q); + prtnframe=precv_frame; + + } + else + { + //can't find this ta's defrag_queue, so free this recv_frame + rtw_free_recvframe(precv_frame, pfree_recv_queue); + prtnframe=NULL; + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("Free because pdefrag_q ==NULL: ismfrag = %d, fragnum= %d\n", ismfrag,fragnum)); + } + + } + + + if((prtnframe!=NULL)&&(prtnframe->u.hdr.attrib.privacy)) + { + //after defrag we must check tkip mic code + if(recvframe_chkmic(padapter, prtnframe)==_FAIL) + { + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvframe_chkmic(padapter, prtnframe)==_FAIL\n")); + rtw_free_recvframe(prtnframe,pfree_recv_queue); + prtnframe=NULL; + } + } + +_func_exit_; + + return prtnframe; + +} + +int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe) +{ + int a_len, padding_len; + u16 nSubframe_Length; + u8 nr_subframes, i; + u8 *pdata; + _pkt *sub_pkt,*subframes[MAX_SUBFRAME_COUNT]; + struct recv_priv *precvpriv = &padapter->recvpriv; + _queue *pfree_recv_queue = &(precvpriv->free_recv_queue); + int ret = _SUCCESS; + + nr_subframes = 0; + + recvframe_pull(prframe, prframe->u.hdr.attrib.hdrlen); + + if(prframe->u.hdr.attrib.iv_len >0) + { + recvframe_pull(prframe, prframe->u.hdr.attrib.iv_len); + } + + a_len = prframe->u.hdr.len; + + pdata = prframe->u.hdr.rx_data; + + while(a_len > ETH_HLEN) { + + /* Offset 12 denote 2 mac address */ + nSubframe_Length = RTW_GET_BE16(pdata + 12); + + if( a_len < (ETHERNET_HEADER_SIZE + nSubframe_Length) ) { + DBG_871X("nRemain_Length is %d and nSubframe_Length is : %d\n",a_len,nSubframe_Length); + break; + } + + sub_pkt = rtw_os_alloc_msdu_pkt(prframe, nSubframe_Length, pdata); + if (sub_pkt == NULL) { + DBG_871X("%s(): allocate sub packet fail !!!\n",__FUNCTION__); + break; + } + + /* move the data point to data content */ + pdata += ETH_HLEN; + a_len -= ETH_HLEN; + + subframes[nr_subframes++] = sub_pkt; + + if(nr_subframes >= MAX_SUBFRAME_COUNT) { + DBG_871X("ParseSubframe(): Too many Subframes! Packets dropped!\n"); + break; + } + + pdata += nSubframe_Length; + a_len -= nSubframe_Length; + if(a_len != 0) { + padding_len = 4 - ((nSubframe_Length + ETH_HLEN) & (4-1)); + if(padding_len == 4) { + padding_len = 0; + } + + if(a_len < padding_len) { + DBG_871X("ParseSubframe(): a_len < padding_len !\n"); + break; + } + pdata += padding_len; + a_len -= padding_len; + } + } + + for(i=0; iu.hdr.attrib); + } + } + + prframe->u.hdr.len = 0; + rtw_free_recvframe(prframe, pfree_recv_queue);//free this recv_frame + + return ret; +} + +int check_indicate_seq(struct recv_reorder_ctrl *preorder_ctrl, u16 seq_num); +int check_indicate_seq(struct recv_reorder_ctrl *preorder_ctrl, u16 seq_num) +{ + PADAPTER padapter = preorder_ctrl->padapter; + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + u8 wsize = preorder_ctrl->wsize_b; + u16 wend = (preorder_ctrl->indicate_seq + wsize -1) & 0xFFF;//% 4096; + + // Rx Reorder initialize condition. + if (preorder_ctrl->indicate_seq == 0xFFFF) + { + preorder_ctrl->indicate_seq = seq_num; + #ifdef DBG_RX_SEQ + DBG_871X("DBG_RX_SEQ %s:%d init IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, + preorder_ctrl->indicate_seq, seq_num); + #endif + + //DbgPrint("check_indicate_seq, 1st->indicate_seq=%d\n", precvpriv->indicate_seq); + } + + //DbgPrint("enter->check_indicate_seq(): IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); + + // Drop out the packet which SeqNum is smaller than WinStart + if( SN_LESS(seq_num, preorder_ctrl->indicate_seq) ) + { + //RT_TRACE(COMP_RX_REORDER, DBG_LOUD, ("CheckRxTsIndicateSeq(): Packet Drop! IndicateSeq: %d, NewSeq: %d\n", pTS->RxIndicateSeq, NewSeqNum)); + //DbgPrint("CheckRxTsIndicateSeq(): Packet Drop! IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); + + #ifdef DBG_RX_DROP_FRAME + DBG_871X("%s IndicateSeq: %d > NewSeq: %d\n", __FUNCTION__, + preorder_ctrl->indicate_seq, seq_num); + #endif + + + return _FALSE; + } + + // + // Sliding window manipulation. Conditions includes: + // 1. Incoming SeqNum is equal to WinStart =>Window shift 1 + // 2. Incoming SeqNum is larger than the WinEnd => Window shift N + // + if( SN_EQUAL(seq_num, preorder_ctrl->indicate_seq) ) + { + preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) & 0xFFF; + + #ifdef DBG_RX_SEQ + DBG_871X("DBG_RX_SEQ %s:%d SN_EQUAL IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, + preorder_ctrl->indicate_seq, seq_num); + #endif + } + else if(SN_LESS(wend, seq_num)) + { + //RT_TRACE(COMP_RX_REORDER, DBG_LOUD, ("CheckRxTsIndicateSeq(): Window Shift! IndicateSeq: %d, NewSeq: %d\n", pTS->RxIndicateSeq, NewSeqNum)); + //DbgPrint("CheckRxTsIndicateSeq(): Window Shift! IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); + + // boundary situation, when seq_num cross 0xFFF + if(seq_num >= (wsize - 1)) + preorder_ctrl->indicate_seq = seq_num + 1 -wsize; + else + preorder_ctrl->indicate_seq = 0xFFF - (wsize - (seq_num + 1)) + 1; + pdbgpriv->dbg_rx_ampdu_window_shift_cnt++; + #ifdef DBG_RX_SEQ + DBG_871X("DBG_RX_SEQ %s:%d SN_LESS(wend, seq_num) IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, + preorder_ctrl->indicate_seq, seq_num); + #endif + } + + //DbgPrint("exit->check_indicate_seq(): IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); + + return _TRUE; +} + +int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, union recv_frame *prframe); +int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, union recv_frame *prframe) +{ + struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; + _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; + _list *phead, *plist; + union recv_frame *pnextrframe; + struct rx_pkt_attrib *pnextattrib; + + //DbgPrint("+enqueue_reorder_recvframe()\n"); + + //_enter_critical_ex(&ppending_recvframe_queue->lock, &irql); + //_rtw_spinlock_ex(&ppending_recvframe_queue->lock); + + + phead = get_list_head(ppending_recvframe_queue); + plist = get_next(phead); + + while(rtw_end_of_queue_search(phead, plist) == _FALSE) + { + pnextrframe = LIST_CONTAINOR(plist, union recv_frame, u); + pnextattrib = &pnextrframe->u.hdr.attrib; + + if(SN_LESS(pnextattrib->seq_num, pattrib->seq_num)) + { + plist = get_next(plist); + } + else if( SN_EQUAL(pnextattrib->seq_num, pattrib->seq_num)) + { + //Duplicate entry is found!! Do not insert current entry. + //RT_TRACE(COMP_RX_REORDER, DBG_TRACE, ("InsertRxReorderList(): Duplicate packet is dropped!! IndicateSeq: %d, NewSeq: %d\n", pTS->RxIndicateSeq, SeqNum)); + + //_exit_critical_ex(&ppending_recvframe_queue->lock, &irql); + + return _FALSE; + } + else + { + break; + } + + //DbgPrint("enqueue_reorder_recvframe():while\n"); + + } + + + //_enter_critical_ex(&ppending_recvframe_queue->lock, &irql); + //_rtw_spinlock_ex(&ppending_recvframe_queue->lock); + + rtw_list_delete(&(prframe->u.hdr.list)); + + rtw_list_insert_tail(&(prframe->u.hdr.list), plist); + + //_rtw_spinunlock_ex(&ppending_recvframe_queue->lock); + //_exit_critical_ex(&ppending_recvframe_queue->lock, &irql); + + + //RT_TRACE(COMP_RX_REORDER, DBG_TRACE, ("InsertRxReorderList(): Pkt insert into buffer!! IndicateSeq: %d, NewSeq: %d\n", pTS->RxIndicateSeq, SeqNum)); + return _TRUE; + +} + +void recv_indicatepkts_pkt_loss_cnt(struct debug_priv *pdbgpriv, u64 prev_seq, u64 current_seq); +void recv_indicatepkts_pkt_loss_cnt(struct debug_priv *pdbgpriv, u64 prev_seq, u64 current_seq) +{ + if(current_seq < prev_seq) + { + pdbgpriv->dbg_rx_ampdu_loss_count+= (4096 + current_seq - prev_seq); + + } + else + { + pdbgpriv->dbg_rx_ampdu_loss_count+= (current_seq - prev_seq); + } +} +int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *preorder_ctrl, int bforced); +int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *preorder_ctrl, int bforced) +{ + //_irqL irql; + //u8 bcancelled; + _list *phead, *plist; + union recv_frame *prframe; + struct rx_pkt_attrib *pattrib; + //u8 index = 0; + int bPktInBuf = _FALSE; + struct recv_priv *precvpriv = &padapter->recvpriv; + _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + + DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_in_oder); + + //DbgPrint("+recv_indicatepkts_in_order\n"); + + //_enter_critical_ex(&ppending_recvframe_queue->lock, &irql); + //_rtw_spinlock_ex(&ppending_recvframe_queue->lock); + + phead = get_list_head(ppending_recvframe_queue); + plist = get_next(phead); + +#if 0 + // Check if there is any other indication thread running. + if(pTS->RxIndicateState == RXTS_INDICATE_PROCESSING) + return; +#endif + + // Handling some condition for forced indicate case. + if(bforced==_TRUE) + { + pdbgpriv->dbg_rx_ampdu_forced_indicate_count++; + if(rtw_is_list_empty(phead)) + { + // _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); + //_rtw_spinunlock_ex(&ppending_recvframe_queue->lock); + return _TRUE; + } + + prframe = LIST_CONTAINOR(plist, union recv_frame, u); + pattrib = &prframe->u.hdr.attrib; + + #ifdef DBG_RX_SEQ + DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, + preorder_ctrl->indicate_seq, pattrib->seq_num); + #endif + recv_indicatepkts_pkt_loss_cnt(pdbgpriv,preorder_ctrl->indicate_seq,pattrib->seq_num); + preorder_ctrl->indicate_seq = pattrib->seq_num; + + } + + // Prepare indication list and indication. + // Check if there is any packet need indicate. + while(!rtw_is_list_empty(phead)) + { + + prframe = LIST_CONTAINOR(plist, union recv_frame, u); + pattrib = &prframe->u.hdr.attrib; + + if(!SN_LESS(preorder_ctrl->indicate_seq, pattrib->seq_num)) + { + RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, + ("recv_indicatepkts_in_order: indicate=%d seq=%d amsdu=%d\n", + preorder_ctrl->indicate_seq, pattrib->seq_num, pattrib->amsdu)); + +#if 0 + // This protect buffer from overflow. + if(index >= REORDER_WIN_SIZE) + { + RT_ASSERT(FALSE, ("IndicateRxReorderList(): Buffer overflow!! \n")); + bPktInBuf = TRUE; + break; + } +#endif + + plist = get_next(plist); + rtw_list_delete(&(prframe->u.hdr.list)); + + if(SN_EQUAL(preorder_ctrl->indicate_seq, pattrib->seq_num)) + { + preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) & 0xFFF; + #ifdef DBG_RX_SEQ + DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, + preorder_ctrl->indicate_seq, pattrib->seq_num); + #endif + } + +#if 0 + index++; + if(index==1) + { + //Cancel previous pending timer. + //PlatformCancelTimer(Adapter, &pTS->RxPktPendingTimer); + if(bforced!=_TRUE) + { + //DBG_871X("_cancel_timer(&preorder_ctrl->reordering_ctrl_timer, &bcancelled);\n"); + _cancel_timer(&preorder_ctrl->reordering_ctrl_timer, &bcancelled); + } + } +#endif + + //Set this as a lock to make sure that only one thread is indicating packet. + //pTS->RxIndicateState = RXTS_INDICATE_PROCESSING; + + // Indicate packets + //RT_ASSERT((index<=REORDER_WIN_SIZE), ("RxReorderIndicatePacket(): Rx Reorder buffer full!! \n")); + + + //indicate this recv_frame + //DbgPrint("recv_indicatepkts_in_order, indicate_seq=%d, seq_num=%d\n", precvpriv->indicate_seq, pattrib->seq_num); + if(!pattrib->amsdu) + { + //DBG_871X("recv_indicatepkts_in_order, amsdu!=1, indicate_seq=%d, seq_num=%d\n", preorder_ctrl->indicate_seq, pattrib->seq_num); + + if (!RTW_CANNOT_RUN(padapter)) + rtw_recv_indicatepkt(padapter, prframe);/*indicate this recv_frame*/ + + } + else if(pattrib->amsdu==1) + { + if(amsdu_to_msdu(padapter, prframe)!=_SUCCESS) + { + rtw_free_recvframe(prframe, &precvpriv->free_recv_queue); + } + } + else + { + //error condition; + } + + + //Update local variables. + bPktInBuf = _FALSE; + + } + else + { + bPktInBuf = _TRUE; + break; + } + + //DbgPrint("recv_indicatepkts_in_order():while\n"); + + } + + //_rtw_spinunlock_ex(&ppending_recvframe_queue->lock); + //_exit_critical_ex(&ppending_recvframe_queue->lock, &irql); + +/* + //Release the indication lock and set to new indication step. + if(bPktInBuf) + { + // Set new pending timer. + //pTS->RxIndicateState = RXTS_INDICATE_REORDER; + //PlatformSetTimer(Adapter, &pTS->RxPktPendingTimer, pHTInfo->RxReorderPendingTime); + //DBG_871X("_set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME)\n"); + _set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME); + } + else + { + //pTS->RxIndicateState = RXTS_INDICATE_IDLE; + } +*/ + //_exit_critical_ex(&ppending_recvframe_queue->lock, &irql); + + //return _TRUE; + return bPktInBuf; + +} + +int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe); +int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe) +{ + _irqL irql; + int retval = _SUCCESS; + struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; + struct recv_reorder_ctrl *preorder_ctrl = prframe->u.hdr.preorder_ctrl; + _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + + DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_reoder); + + if(!pattrib->amsdu) + { + //s1. + retval = wlanhdr_to_ethhdr(prframe); + if (retval != _SUCCESS) + { + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("wlanhdr_to_ethhdr: drop pkt \n")); + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s wlanhdr_to_ethhdr error!\n", __FUNCTION__); + #endif + return retval; + } + + //if ((pattrib->qos!=1) /*|| pattrib->priority!=0 || IS_MCAST(pattrib->ra)*/ + // || (pattrib->eth_type==0x0806) || (pattrib->ack_policy!=0)) + if (pattrib->qos!=1) + { + if (!RTW_CANNOT_RUN(padapter)) { + RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("@@@@ recv_indicatepkt_reorder -recv_func recv_indicatepkt\n" )); + + rtw_recv_indicatepkt(padapter, prframe); + return _SUCCESS; + + } + + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s pattrib->qos !=1\n", __FUNCTION__); + #endif + + return _FAIL; + + } + + if (preorder_ctrl->enable == _FALSE) + { + //indicate this recv_frame + preorder_ctrl->indicate_seq = pattrib->seq_num; + #ifdef DBG_RX_SEQ + DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, + preorder_ctrl->indicate_seq, pattrib->seq_num); + #endif + + rtw_recv_indicatepkt(padapter, prframe); + + preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1)%4096; + #ifdef DBG_RX_SEQ + DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, + preorder_ctrl->indicate_seq, pattrib->seq_num); + #endif + + return _SUCCESS; + } + +#ifndef CONFIG_RECV_REORDERING_CTRL + //indicate this recv_frame + rtw_recv_indicatepkt(padapter, prframe); + return _SUCCESS; +#endif + + } + else if(pattrib->amsdu==1) //temp filter -> means didn't support A-MSDUs in a A-MPDU + { + if (preorder_ctrl->enable == _FALSE) + { + preorder_ctrl->indicate_seq = pattrib->seq_num; + #ifdef DBG_RX_SEQ + DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, + preorder_ctrl->indicate_seq, pattrib->seq_num); + #endif + + retval = amsdu_to_msdu(padapter, prframe); + + preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1)%4096; + #ifdef DBG_RX_SEQ + DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, + preorder_ctrl->indicate_seq, pattrib->seq_num); + #endif + + if(retval != _SUCCESS){ + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s amsdu_to_msdu fail\n", __FUNCTION__); + #endif + } + + return retval; + } + } + else + { + + } + + _enter_critical_bh(&ppending_recvframe_queue->lock, &irql); + + RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, + ("recv_indicatepkt_reorder: indicate=%d seq=%d\n", + preorder_ctrl->indicate_seq, pattrib->seq_num)); + + //s2. check if winstart_b(indicate_seq) needs to been updated + if(!check_indicate_seq(preorder_ctrl, pattrib->seq_num)) + { + pdbgpriv->dbg_rx_ampdu_drop_count++; + //pHTInfo->RxReorderDropCounter++; + //ReturnRFDList(Adapter, pRfd); + //RT_TRACE(COMP_RX_REORDER, DBG_TRACE, ("RxReorderIndicatePacket() ==> Packet Drop!!\n")); + //_exit_critical_ex(&ppending_recvframe_queue->lock, &irql); + //return _FAIL; + + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s check_indicate_seq fail\n", __FUNCTION__); + #endif +#if 0 + rtw_recv_indicatepkt(padapter, prframe); + + _exit_critical_bh(&ppending_recvframe_queue->lock, &irql); + + goto _success_exit; +#else + goto _err_exit; +#endif + } + + + //s3. Insert all packet into Reorder Queue to maintain its ordering. + if(!enqueue_reorder_recvframe(preorder_ctrl, prframe)) + { + //DbgPrint("recv_indicatepkt_reorder, enqueue_reorder_recvframe fail!\n"); + //_exit_critical_ex(&ppending_recvframe_queue->lock, &irql); + //return _FAIL; + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s enqueue_reorder_recvframe fail\n", __FUNCTION__); + #endif + goto _err_exit; + } + + + //s4. + // Indication process. + // After Packet dropping and Sliding Window shifting as above, we can now just indicate the packets + // with the SeqNum smaller than latest WinStart and buffer other packets. + // + // For Rx Reorder condition: + // 1. All packets with SeqNum smaller than WinStart => Indicate + // 2. All packets with SeqNum larger than or equal to WinStart => Buffer it. + // + + //recv_indicatepkts_in_order(padapter, preorder_ctrl, _TRUE); + if(recv_indicatepkts_in_order(padapter, preorder_ctrl, _FALSE)==_TRUE) + { + if (!preorder_ctrl->bReorderWaiting) { + preorder_ctrl->bReorderWaiting = _TRUE; + _set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME); + } + _exit_critical_bh(&ppending_recvframe_queue->lock, &irql); + } + else + { + preorder_ctrl->bReorderWaiting = _FALSE; + _exit_critical_bh(&ppending_recvframe_queue->lock, &irql); + _cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer); + } + + +_success_exit: + + return _SUCCESS; + +_err_exit: + + _exit_critical_bh(&ppending_recvframe_queue->lock, &irql); + + return _FAIL; +} + + +void rtw_reordering_ctrl_timeout_handler(void *pcontext) +{ + _irqL irql; + struct recv_reorder_ctrl *preorder_ctrl = (struct recv_reorder_ctrl *)pcontext; + _adapter *padapter = preorder_ctrl->padapter; + _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; + + + if (RTW_CANNOT_RUN(padapter)) + return; + + //DBG_871X("+rtw_reordering_ctrl_timeout_handler()=>\n"); + + _enter_critical_bh(&ppending_recvframe_queue->lock, &irql); + + if (preorder_ctrl) { + preorder_ctrl->bReorderWaiting = _FALSE; + } + + if(recv_indicatepkts_in_order(padapter, preorder_ctrl, _TRUE)==_TRUE) + { + _set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME); + } + + _exit_critical_bh(&ppending_recvframe_queue->lock, &irql); + +} + +int process_recv_indicatepkts(_adapter *padapter, union recv_frame *prframe); +int process_recv_indicatepkts(_adapter *padapter, union recv_frame *prframe) +{ + int retval = _SUCCESS; + //struct recv_priv *precvpriv = &padapter->recvpriv; + //struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; +#ifdef CONFIG_TDLS + struct sta_info *psta = prframe->u.hdr.psta; +#endif //CONFIG_TDLS + +#ifdef CONFIG_80211N_HT + + struct ht_priv *phtpriv = &pmlmepriv->htpriv; + + DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate); + +#ifdef CONFIG_TDLS + if( (phtpriv->ht_option==_TRUE) || + ((psta->tdls_sta_state & TDLS_LINKED_STATE) && + (psta->htpriv.ht_option==_TRUE) && + (psta->htpriv.ampdu_enable==_TRUE))) //B/G/N Mode +#else + if(phtpriv->ht_option==_TRUE) //B/G/N Mode +#endif //CONFIG_TDLS + { + //prframe->u.hdr.preorder_ctrl = &precvpriv->recvreorder_ctrl[pattrib->priority]; + + if(recv_indicatepkt_reorder(padapter, prframe)!=_SUCCESS)// including perform A-MPDU Rx Ordering Buffer Control + { + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s recv_indicatepkt_reorder error!\n", __FUNCTION__); + #endif + + if (!RTW_CANNOT_RUN(padapter)) { + retval = _FAIL; + return retval; + } + } + } + else //B/G mode +#endif + { + retval=wlanhdr_to_ethhdr (prframe); + if(retval != _SUCCESS) + { + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("wlanhdr_to_ethhdr: drop pkt \n")); + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s wlanhdr_to_ethhdr error!\n", __FUNCTION__); + #endif + return retval; + } + + if (!RTW_CANNOT_RUN(padapter)) { + //indicate this recv_frame + RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("@@@@ process_recv_indicatepkts- recv_func recv_indicatepkt\n" )); + rtw_recv_indicatepkt(padapter, prframe); + } + else + { + RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("@@@@ process_recv_indicatepkts- recv_func free_indicatepkt\n" )); + + RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("recv_func:bDriverStopped(%s) OR bSurpriseRemoved(%s)" + , rtw_is_drv_stopped(padapter)?"True":"False" + , rtw_is_surprise_removed(padapter)?"True":"False")); + retval = _FAIL; + return retval; + } + + } + + return retval; + +} + +#ifdef CONFIG_MP_INCLUDED +int validate_mp_recv_frame(_adapter *adapter, union recv_frame *precv_frame) +{ + int ret = _SUCCESS; + u8 *ptr = precv_frame->u.hdr.rx_data; + u8 type,subtype; + struct mp_priv *pmppriv = &adapter->mppriv; + struct mp_tx *pmptx; + + pmptx = &pmppriv->tx; + +#if 0 + if (1){ + u8 bDumpRxPkt; + type = GetFrameType(ptr); + subtype = GetFrameSubType(ptr); //bit(7)~bit(2) + + rtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_RXPKT, &(bDumpRxPkt)); + if(bDumpRxPkt ==1){//dump all rx packets + int i; + DBG_871X("############ type:0x%02x subtype:0x%02x ################# \n",type,subtype); + + for(i=0; i<64;i=i+8) + DBG_871X("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:\n", *(ptr+i), + *(ptr+i+1), *(ptr+i+2) ,*(ptr+i+3) ,*(ptr+i+4),*(ptr+i+5), *(ptr+i+6), *(ptr+i+7)); + DBG_871X("#############################\n"); + } + } +#endif + if (pmppriv->bloopback) { + if (_rtw_memcmp(ptr + 24, pmptx->buf + 24, precv_frame->u.hdr.len - 24) == _FALSE) { + DBG_871X("Compare payload content Fail !!!\n"); + ret = _FAIL; + } + } + + if (!adapter->mppriv.bmac_filter) + return ret; + + if(_rtw_memcmp( GetAddr2Ptr(ptr), adapter->mppriv.mac_filter, ETH_ALEN) == _FALSE ) + ret = _FAIL; + + return ret; +} +#endif + +static sint MPwlanhdr_to_ethhdr ( union recv_frame *precvframe) +{ + sint rmv_len; + u16 eth_type, len; + u8 bsnaphdr; + u8 *psnap_type; + u8 mcastheadermac[]={0x01,0x00,0x5e}; + + struct ieee80211_snap_hdr *psnap; + + sint ret=_SUCCESS; + _adapter *adapter =precvframe->u.hdr.adapter; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + + u8 *ptr = get_recvframe_data(precvframe) ; // point to frame_ctrl field + struct rx_pkt_attrib *pattrib = & precvframe->u.hdr.attrib; + +_func_enter_; + + if(pattrib->encrypt){ + recvframe_pull_tail(precvframe, pattrib->icv_len); + } + + psnap=(struct ieee80211_snap_hdr *)(ptr+pattrib->hdrlen + pattrib->iv_len); + psnap_type=ptr+pattrib->hdrlen + pattrib->iv_len+SNAP_SIZE; + /* convert hdr + possible LLC headers into Ethernet header */ + //eth_type = (psnap_type[0] << 8) | psnap_type[1]; + if((_rtw_memcmp(psnap, rtw_rfc1042_header, SNAP_SIZE) && + (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_IPX, 2) == _FALSE) && + (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_APPLETALK_AARP, 2)==_FALSE) )|| + //eth_type != ETH_P_AARP && eth_type != ETH_P_IPX) || + _rtw_memcmp(psnap, rtw_bridge_tunnel_header, SNAP_SIZE)){ + /* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */ + bsnaphdr = _TRUE; + } + else { + /* Leave Ethernet header part of hdr and full payload */ + bsnaphdr = _FALSE; + } + + rmv_len = pattrib->hdrlen + pattrib->iv_len +(bsnaphdr?SNAP_SIZE:0); + len = precvframe->u.hdr.len - rmv_len; + + RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n===pattrib->hdrlen: %x, pattrib->iv_len:%x ===\n\n", pattrib->hdrlen, pattrib->iv_len)); + + _rtw_memcpy(ð_type, ptr+rmv_len, 2); + eth_type= ntohs((unsigned short )eth_type); //pattrib->ether_type + pattrib->eth_type = eth_type; + + { + ptr = recvframe_pull(precvframe, (rmv_len-sizeof(struct ethhdr)+ (bsnaphdr?2:0))); + } + + _rtw_memcpy(ptr, pattrib->dst, ETH_ALEN); + _rtw_memcpy(ptr+ETH_ALEN, pattrib->src, ETH_ALEN); + + if(!bsnaphdr) { + len = htons(len); + _rtw_memcpy(ptr+12, &len, 2); + } + + + len = htons(pattrib->seq_num); + //DBG_871X("wlan seq = %d ,seq_num =%x\n",len,pattrib->seq_num); + _rtw_memcpy(ptr+12,&len, 2); + if(adapter->mppriv.bRTWSmbCfg==_TRUE) + { +// if(_rtw_memcmp(mcastheadermac, pattrib->dst, 3) == _TRUE)//SimpleConfig Dest. +// _rtw_memcpy(ptr+ETH_ALEN, pattrib->bssid, ETH_ALEN); + + if(_rtw_memcmp(mcastheadermac, pattrib->bssid, 3) == _TRUE) //SimpleConfig Dest. + _rtw_memcpy(ptr, pattrib->bssid, ETH_ALEN); + + } + + +_func_exit_; + return ret; + +} + + +int mp_recv_frame(_adapter *padapter, union recv_frame *rframe) +{ + int ret = _SUCCESS; + struct rx_pkt_attrib *pattrib = &rframe->u.hdr.attrib; + struct recv_priv *precvpriv = &padapter->recvpriv; + _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue; +#ifdef CONFIG_MP_INCLUDED + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mp_priv *pmppriv = &padapter->mppriv; +#endif //CONFIG_MP_INCLUDED + u8 type; + u8 *ptr = rframe->u.hdr.rx_data; + u8 *psa, *pda, *pbssid; + struct sta_info *psta = NULL; + DBG_COUNTER(padapter->rx_logs.core_rx_pre); + + if ( (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) )//&&(padapter->mppriv.check_mp_pkt == 0)) + { + if (pattrib->crc_err == 1){ + padapter->mppriv.rx_crcerrpktcount++; + } + else{ + if(_SUCCESS == validate_mp_recv_frame(padapter, rframe)) + padapter->mppriv.rx_pktcount++; + else + padapter->mppriv.rx_pktcount_filter_out++; + } + + if(pmppriv->rx_bindicatePkt == _FALSE) + { + //RT_TRACE(_module_rtl871x_recv_c_, _drv_alert_, ("MP - Not in loopback mode , drop pkt \n")); + ret = _FAIL; + rtw_free_recvframe(rframe, pfree_recv_queue);//free this recv_frame + goto exit; + } + else + { + type = GetFrameType(ptr); + pattrib->to_fr_ds = get_tofr_ds(ptr); + pattrib->frag_num = GetFragNum(ptr); + pattrib->seq_num = GetSequence(ptr); + pattrib->pw_save = GetPwrMgt(ptr); + pattrib->mfrag = GetMFrag(ptr); + pattrib->mdata = GetMData(ptr); + pattrib->privacy = GetPrivacy(ptr); + pattrib->order = GetOrder(ptr); + + if(type ==WIFI_DATA_TYPE) + { + pda = get_da(ptr); + psa = get_sa(ptr); + pbssid = get_hdr_bssid(ptr); + + _rtw_memcpy(pattrib->dst, pda, ETH_ALEN); + _rtw_memcpy(pattrib->src, psa, ETH_ALEN); + _rtw_memcpy(pattrib->bssid, pbssid, ETH_ALEN); + + switch(pattrib->to_fr_ds) + { + case 0: + _rtw_memcpy(pattrib->ra, pda, ETH_ALEN); + _rtw_memcpy(pattrib->ta, psa, ETH_ALEN); + ret = sta2sta_data_frame(padapter, rframe, &psta); + break; + + case 1: + + _rtw_memcpy(pattrib->ra, pda, ETH_ALEN); + _rtw_memcpy(pattrib->ta, pbssid, ETH_ALEN); + ret = ap2sta_data_frame(padapter, rframe, &psta); + + break; + + case 2: + _rtw_memcpy(pattrib->ra, pbssid, ETH_ALEN); + _rtw_memcpy(pattrib->ta, psa, ETH_ALEN); + ret = sta2ap_data_frame(padapter, rframe, &psta); + break; + + case 3: + _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); + _rtw_memcpy(pattrib->ta, GetAddr2Ptr(ptr), ETH_ALEN); + ret =_FAIL; + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" case 3\n")); + break; + + default: + ret =_FAIL; + break; + } + + ret = MPwlanhdr_to_ethhdr (rframe); + + if (ret != _SUCCESS) + { + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("wlanhdr_to_ethhdr: drop pkt \n")); + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s wlanhdr_to_ethhdr: drop pkt\n", __FUNCTION__); + #endif + rtw_free_recvframe(rframe, pfree_recv_queue);//free this recv_frame + ret = _FAIL; + goto exit; + } + if (!RTW_CANNOT_RUN(padapter)) { + RT_TRACE(_module_rtl871x_recv_c_, _drv_alert_, ("@@@@ recv_func: recv_func rtw_recv_indicatepkt\n" )); + //indicate this recv_frame + ret = rtw_recv_indicatepkt(padapter, rframe); + if (ret != _SUCCESS) + { + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s rtw_recv_indicatepkt fail!\n", __FUNCTION__); + #endif + rtw_free_recvframe(rframe, pfree_recv_queue);//free this recv_frame + ret = _FAIL; + + goto exit; + } + } + else + { + RT_TRACE(_module_rtl871x_recv_c_, _drv_alert_, ("@@@@ recv_func: rtw_free_recvframe\n" )); + RT_TRACE(_module_rtl871x_recv_c_, _drv_debug_, ("recv_func:bDriverStopped(%s) OR bSurpriseRemoved(%s)" + , rtw_is_drv_stopped(padapter)?"True":"False" + , rtw_is_surprise_removed(padapter)?"True":"False")); + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s ecv_func:bDriverStopped(%s) OR bSurpriseRemoved(%s)\n", __func__, + rtw_is_drv_stopped(padapter)?"True":"False", + rtw_is_surprise_removed(padapter)?"True":"False"); + #endif + ret = _FAIL; + rtw_free_recvframe(rframe, pfree_recv_queue);//free this recv_frame + goto exit; + } + + } + } + + } + + RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("recv_func: validate_recv_frame fail! drop pkt\n")); + rtw_free_recvframe(rframe, pfree_recv_queue);//free this recv_frame + ret = _FAIL; + +exit: + return ret; + +} + +static sint fill_radiotap_hdr(_adapter *padapter, union recv_frame *precvframe, u8 *buf) +{ +#define CHAN2FREQ(a) ((a < 14)?(2407+5*a):(5000+5*a)) + +#if 0 +#define RTW_RX_RADIOTAP_PRESENT ( \ + (1 << IEEE80211_RADIOTAP_TSFT) | \ + (1 << IEEE80211_RADIOTAP_FLAGS) | \ + (1 << IEEE80211_RADIOTAP_RATE) | \ + (1 << IEEE80211_RADIOTAP_CHANNEL) | \ + (0 << IEEE80211_RADIOTAP_FHSS) | \ + (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \ + (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | \ + (0 << IEEE80211_RADIOTAP_LOCK_QUALITY) | \ + (0 << IEEE80211_RADIOTAP_TX_ATTENUATION) | \ + (0 << IEEE80211_RADIOTAP_DB_TX_ATTENUATION) | \ + (0 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \ + (1 << IEEE80211_RADIOTAP_ANTENNA) | \ + (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL) | \ + (0 << IEEE80211_RADIOTAP_DB_ANTNOISE) | \ + (0 << IEEE80211_RADIOTAP_RX_FLAGS) | \ + (0 << IEEE80211_RADIOTAP_TX_FLAGS) | \ + (0 << IEEE80211_RADIOTAP_RTS_RETRIES) | \ + (0 << IEEE80211_RADIOTAP_DATA_RETRIES) | \ + (0 << IEEE80211_RADIOTAP_MCS) | \ + (0 << IEEE80211_RADIOTAP_RADIOTAP_NAMESPACE)| \ + (0 << IEEE80211_RADIOTAP_VENDOR_NAMESPACE) | \ + (0 << IEEE80211_RADIOTAP_EXT) | \ + 0) + + /* (0 << IEEE80211_RADIOTAP_AMPDU_STATUS) | \ */ + /* (0 << IEEE80211_RADIOTAP_VHT) | \ */ +#endif +#ifndef IEEE80211_RADIOTAP_MCS +#define IEEE80211_RADIOTAP_MCS 19 +#endif +#ifndef IEEE80211_RADIOTAP_VHT +#define IEEE80211_RADIOTAP_VHT 21 +#endif + +#ifndef IEEE80211_RADIOTAP_F_BADFCS +#define IEEE80211_RADIOTAP_F_BADFCS 0x40 /* bad FCS */ +#endif + + sint ret = _SUCCESS; + _adapter *adapter = precvframe->u.hdr.adapter; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib; + + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + u16 tmp_16bit = 0; + + u8 data_rate[] = { + 2, 4, 11, 22, /* CCK */ + 12, 18, 24, 36, 48, 72, 93, 108, /* OFDM */ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, /* HT MCS index */ + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /* VHT Nss 1 */ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /* VHT Nss 2 */ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /* VHT Nss 3 */ + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, /* VHT Nss 4 */ + }; + + _pkt *pskb = NULL; + + struct ieee80211_radiotap_header *rtap_hdr = NULL; + u8 *ptr = NULL; + + u8 hdr_buf[64] = {0}; + u16 rt_len = 8; + + /* create header */ + rtap_hdr = (struct ieee80211_radiotap_header *)&hdr_buf[0]; + rtap_hdr->it_version = PKTHDR_RADIOTAP_VERSION; + + /* tsft */ + if (pattrib->tsfl) { + u64 tmp_64bit; + + rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_TSFT); + tmp_64bit = cpu_to_le64(pattrib->tsfl); + memcpy(&hdr_buf[rt_len], &tmp_64bit, 8); + rt_len += 8; + } + + /* flags */ + rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_FLAGS); + if (0) + hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_CFP; + + if (0) + hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_SHORTPRE; + + if ((pattrib->encrypt == 1) || (pattrib->encrypt == 5)) + hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_WEP; + + if (pattrib->mfrag) + hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_FRAG; + + /* always append FCS */ + hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_FCS; + + if (0) + hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_DATAPAD; + + if (pattrib->crc_err) + hdr_buf[rt_len] |= IEEE80211_RADIOTAP_F_BADFCS; + + if (pattrib->sgi) { + /* Currently unspecified but used */ + hdr_buf[rt_len] |= 0x80; + } + rt_len += 1; + + /* rate */ + if (pattrib->data_rate < 12) { + rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_RATE); + if (pattrib->data_rate < 4) { + /* CCK */ + hdr_buf[rt_len] = data_rate[pattrib->data_rate]; + } else { + /* OFDM */ + hdr_buf[rt_len] = data_rate[pattrib->data_rate]; + } + } + rt_len += 1; /* force padding 1 byte for aligned */ + + /* channel */ + tmp_16bit = 0; + rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_CHANNEL); + tmp_16bit = CHAN2FREQ(rtw_get_oper_ch(padapter)); + /*tmp_16bit = CHAN2FREQ(pHalData->CurrentChannel);*/ + memcpy(&hdr_buf[rt_len], &tmp_16bit, 2); + rt_len += 2; + + /* channel flags */ + tmp_16bit = 0; + if (pHalData->CurrentBandType == 0) + tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_2GHZ); + else + tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_5GHZ); + + if (pattrib->data_rate < 12) { + if (pattrib->data_rate < 4) { + /* CCK */ + tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_CCK); + } else { + /* OFDM */ + tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_OFDM); + } + } else { + tmp_16bit |= cpu_to_le16(IEEE80211_CHAN_DYN); + } + memcpy(&hdr_buf[rt_len], &tmp_16bit, 2); + rt_len += 2; + + /* dBm Antenna Signal */ + rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL); + hdr_buf[rt_len] = pattrib->phy_info.RecvSignalPower; + rt_len += 1; + +#if 0 + /* dBm Antenna Noise */ + rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE); + hdr_buf[rt_len] = 0; + rt_len += 1; + + /* Signal Quality */ + rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_LOCK_QUALITY); + hdr_buf[rt_len] = pattrib->phy_info.SignalQuality; + rt_len += 1; +#endif + + /* Antenna */ + rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_ANTENNA); + hdr_buf[rt_len] = 0; /* pHalData->rf_type; */ + rt_len += 1; + + /* RX flags */ + rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_RX_FLAGS); +#if 0 + tmp_16bit = cpu_to_le16(0); + memcpy(ptr, &tmp_16bit, 1); +#endif + rt_len += 2; + + /* MCS information */ + if (pattrib->data_rate >= 12 && pattrib->data_rate < 44) { + rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_MCS); + /* known, flag */ + hdr_buf[rt_len] |= BIT1; /* MCS index known */ + + /* bandwidth */ + hdr_buf[rt_len] |= BIT0; + hdr_buf[rt_len+1] |= (pattrib->bw & 0x03); + + /* guard interval */ + hdr_buf[rt_len] |= BIT2; + hdr_buf[rt_len+1] |= (pattrib->sgi & 0x01) << 2; + + /* STBC */ + hdr_buf[rt_len] |= BIT5; + hdr_buf[rt_len+1] |= (pattrib->stbc & 0x03) << 5; + + rt_len += 2; + + /* MCS rate index */ + hdr_buf[rt_len] = data_rate[pattrib->data_rate]; + rt_len += 1; + } + + /* VHT */ + if (pattrib->data_rate >= 44 && pattrib->data_rate < 84) { + rtap_hdr->it_present |= (1 << IEEE80211_RADIOTAP_VHT); + + /* known 16 bit, flag 8 bit */ + tmp_16bit = 0; + + /* Bandwidth */ + tmp_16bit |= BIT6; + + /* Group ID */ + tmp_16bit |= BIT7; + + /* Partial AID */ + tmp_16bit |= BIT8; + + /* STBC */ + tmp_16bit |= BIT0; + hdr_buf[rt_len+2] |= (pattrib->stbc & 0x01); + + /* Guard interval */ + tmp_16bit |= BIT2; + hdr_buf[rt_len+2] |= (pattrib->sgi & 0x01) << 2; + + /* LDPC extra OFDM symbol */ + tmp_16bit |= BIT4; + hdr_buf[rt_len+2] |= (pattrib->ldpc & 0x01) << 4; + + memcpy(&hdr_buf[rt_len], &tmp_16bit, 2); + rt_len += 3; + + /* bandwidth */ + if (pattrib->bw == 0) + hdr_buf[rt_len] |= 0; + else if (pattrib->bw == 1) + hdr_buf[rt_len] |= 1; + else if (pattrib->bw == 2) + hdr_buf[rt_len] |= 4; + else if (pattrib->bw == 3) + hdr_buf[rt_len] |= 11; + rt_len += 1; + + /* mcs_nss */ + if (pattrib->data_rate >= 44 && pattrib->data_rate < 54) { + hdr_buf[rt_len] |= 1; + hdr_buf[rt_len] |= data_rate[pattrib->data_rate] << 4; + } else if (pattrib->data_rate >= 54 && pattrib->data_rate < 64) { + hdr_buf[rt_len + 1] |= 2; + hdr_buf[rt_len + 1] |= data_rate[pattrib->data_rate] << 4; + } else if (pattrib->data_rate >= 64 && pattrib->data_rate < 74) { + hdr_buf[rt_len + 2] |= 3; + hdr_buf[rt_len + 2] |= data_rate[pattrib->data_rate] << 4; + } else if (pattrib->data_rate >= 74 && pattrib->data_rate < 84) { + hdr_buf[rt_len + 3] |= 4; + hdr_buf[rt_len + 3] |= data_rate[pattrib->data_rate] << 4; + } + rt_len += 4; + + /* coding */ + hdr_buf[rt_len] = 0; + rt_len += 1; + + /* group_id */ + hdr_buf[rt_len] = 0; + rt_len += 1; + + /* partial_aid */ + tmp_16bit = 0; + memcpy(&hdr_buf[rt_len], &tmp_16bit, 2); + rt_len += 2; + } + + /* push to skb */ + pskb = (_pkt *)buf; + if (skb_headroom(pskb) < rt_len) { + DBG_871X("%s:%d %s headroom is too small.\n", __FILE__, __LINE__, __func__); + ret = _FAIL; + return ret; + } + + ptr = skb_push(pskb, rt_len); + if (ptr) { + rtap_hdr->it_len = cpu_to_le16(rt_len); + memcpy(ptr, rtap_hdr, rt_len); + } else { + ret = _FAIL; + } + + return ret; + +} + +int recv_frame_monitor(_adapter *padapter, union recv_frame *rframe) +{ + int ret = _SUCCESS; + struct rx_pkt_attrib *pattrib = &rframe->u.hdr.attrib; + struct recv_priv *precvpriv = &padapter->recvpriv; + _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue; + _pkt *pskb = NULL; + + /* read skb information from recv frame */ + pskb = rframe->u.hdr.pkt; + pskb->len = rframe->u.hdr.len; + pskb->data = rframe->u.hdr.rx_data; + skb_set_tail_pointer(pskb, rframe->u.hdr.len); + + /* fill radiotap header */ + if (fill_radiotap_hdr(padapter, rframe, (u8 *)pskb) == _FAIL) { + ret = _FAIL; + rtw_free_recvframe(rframe, pfree_recv_queue); /* free this recv_frame */ + goto exit; + } + + /* write skb information to recv frame */ + skb_reset_mac_header(pskb); + rframe->u.hdr.len = pskb->len; + rframe->u.hdr.rx_data = pskb->data; + rframe->u.hdr.rx_head = pskb->head; + rframe->u.hdr.rx_tail = skb_tail_pointer(pskb); + rframe->u.hdr.rx_end = skb_end_pointer(pskb); + + if (!RTW_CANNOT_RUN(padapter)) { + /* indicate this recv_frame */ + ret = rtw_recv_monitor(padapter, rframe); + if (ret != _SUCCESS) { + ret = _FAIL; + rtw_free_recvframe(rframe, pfree_recv_queue); /* free this recv_frame */ + goto exit; + } + } else { + ret = _FAIL; + rtw_free_recvframe(rframe, pfree_recv_queue); /* free this recv_frame */ + goto exit; + } + +exit: + return ret; +} + +int recv_func_prehandle(_adapter *padapter, union recv_frame *rframe) +{ + int ret = _SUCCESS; + struct rx_pkt_attrib *pattrib = &rframe->u.hdr.attrib; + struct recv_priv *precvpriv = &padapter->recvpriv; + _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue; + +#ifdef DBG_RX_COUNTER_DUMP + if( padapter->dump_rx_cnt_mode & DUMP_DRV_RX_COUNTER ) + { + if (pattrib->crc_err == 1) + padapter->drv_rx_cnt_crcerror++; + else + padapter->drv_rx_cnt_ok++; + } +#endif + +#ifdef CONFIG_MP_INCLUDED + if (padapter->registrypriv.mp_mode == 1 || padapter->mppriv.bRTWSmbCfg ==_TRUE) + { + mp_recv_frame(padapter,rframe); + ret = _FAIL; + goto exit; + } + else +#endif + { + //check the frame crtl field and decache + ret = validate_recv_frame(padapter, rframe); + if (ret != _SUCCESS) + { + RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("recv_func: validate_recv_frame fail! drop pkt\n")); + rtw_free_recvframe(rframe, pfree_recv_queue);//free this recv_frame + goto exit; + } + } +exit: + return ret; +} + +int recv_func_posthandle(_adapter *padapter, union recv_frame *prframe) +{ + int ret = _SUCCESS; + union recv_frame *orig_prframe = prframe; + struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; + struct recv_priv *precvpriv = &padapter->recvpriv; + _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue; +#ifdef CONFIG_TDLS + u8 *psnap_type, *pcategory; +#endif //CONFIG_TDLS + + DBG_COUNTER(padapter->rx_logs.core_rx_post); + + // DATA FRAME + rtw_led_control(padapter, LED_CTL_RX); + + prframe = decryptor(padapter, prframe); + if (prframe == NULL) { + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("decryptor: drop pkt\n")); + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s decryptor: drop pkt\n", __FUNCTION__); + #endif + ret = _FAIL; + DBG_COUNTER(padapter->rx_logs.core_rx_post_decrypt_err); + goto _recv_data_drop; + } + +#if 0 + if ( padapter->adapter_type == PRIMARY_ADAPTER ) + { + DBG_871X("+++\n"); + { + int i; + u8 *ptr = get_recvframe_data(prframe); + for(i=0; i<140;i=i+8) + DBG_871X("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:", *(ptr+i), + *(ptr+i+1), *(ptr+i+2) ,*(ptr+i+3) ,*(ptr+i+4),*(ptr+i+5), *(ptr+i+6), *(ptr+i+7)); + + } + DBG_871X("---\n"); + } +#endif + +#ifdef CONFIG_TDLS + //check TDLS frame + psnap_type = get_recvframe_data(orig_prframe) + pattrib->hdrlen + pattrib->iv_len+SNAP_SIZE; + pcategory = psnap_type + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN; + + if((_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_TDLS, ETH_TYPE_LEN)) && + ((*pcategory==RTW_WLAN_CATEGORY_TDLS) || (*pcategory==RTW_WLAN_CATEGORY_P2P))){ + ret = OnTDLS(padapter, prframe); + if(ret == _FAIL) + goto _exit_recv_func; + } +#endif //CONFIG_TDLS + + prframe = recvframe_chk_defrag(padapter, prframe); + if(prframe==NULL) { + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvframe_chk_defrag: drop pkt\n")); + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s recvframe_chk_defrag: drop pkt\n", __FUNCTION__); + #endif + DBG_COUNTER(padapter->rx_logs.core_rx_post_defrag_err); + goto _recv_data_drop; + } + + prframe=portctrl(padapter, prframe); + if (prframe == NULL) { + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("portctrl: drop pkt \n")); + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s portctrl: drop pkt\n", __FUNCTION__); + #endif + ret = _FAIL; + DBG_COUNTER(padapter->rx_logs.core_rx_post_portctrl_err); + goto _recv_data_drop; + } + + count_rx_stats(padapter, prframe, NULL); + +#ifdef CONFIG_WAPI_SUPPORT + rtw_wapi_update_info(padapter, prframe); +#endif + +#ifdef CONFIG_80211N_HT + ret = process_recv_indicatepkts(padapter, prframe); + if (ret != _SUCCESS) + { + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recv_func: process_recv_indicatepkts fail! \n")); + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s process_recv_indicatepkts fail!\n", __FUNCTION__); + #endif + rtw_free_recvframe(orig_prframe, pfree_recv_queue);//free this recv_frame + DBG_COUNTER(padapter->rx_logs.core_rx_post_indicate_err); + goto _recv_data_drop; + } +#else // CONFIG_80211N_HT + if (!pattrib->amsdu) + { + ret = wlanhdr_to_ethhdr (prframe); + if (ret != _SUCCESS) + { + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("wlanhdr_to_ethhdr: drop pkt \n")); + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s wlanhdr_to_ethhdr: drop pkt\n", __FUNCTION__); + #endif + rtw_free_recvframe(orig_prframe, pfree_recv_queue);//free this recv_frame + goto _recv_data_drop; + } + + if (!RTW_CANNOT_RUN(padapter)) { + RT_TRACE(_module_rtl871x_recv_c_, _drv_alert_, ("@@@@ recv_func: recv_func rtw_recv_indicatepkt\n" )); + //indicate this recv_frame + ret = rtw_recv_indicatepkt(padapter, prframe); + if (ret != _SUCCESS) + { + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s rtw_recv_indicatepkt fail!\n", __FUNCTION__); + #endif + goto _recv_data_drop; + } + } + else + { + RT_TRACE(_module_rtl871x_recv_c_, _drv_alert_, ("@@@@ recv_func: rtw_free_recvframe\n" )); + RT_TRACE(_module_rtl871x_recv_c_, _drv_debug_, ("recv_func:bDriverStopped(%d) OR bSurpriseRemoved(%d)", padapter->bDriverStopped, padapter->bSurpriseRemoved)); + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s ecv_func:bDriverStopped(%s) OR bSurpriseRemoved(%s)\n", __func__ + , rtw_is_drv_stopped(padapter)?"True":"False" + , rtw_is_surprise_removed(padapter)?"True":"False"); + #endif + ret = _FAIL; + rtw_free_recvframe(orig_prframe, pfree_recv_queue); //free this recv_frame + } + + } + else if(pattrib->amsdu==1) + { + + ret = amsdu_to_msdu(padapter, prframe); + if(ret != _SUCCESS) + { + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s amsdu_to_msdu fail\n", __FUNCTION__); + #endif + rtw_free_recvframe(orig_prframe, pfree_recv_queue); + goto _recv_data_drop; + } + } + else + { + #ifdef DBG_RX_DROP_FRAME + DBG_871X("DBG_RX_DROP_FRAME %s what is this condition??\n", __FUNCTION__); + #endif + goto _recv_data_drop; + } +#endif // CONFIG_80211N_HT + +_exit_recv_func: + return ret; + +_recv_data_drop: + precvpriv->rx_drop++; + return ret; +} + + +int recv_func(_adapter *padapter, union recv_frame *rframe); +int recv_func(_adapter *padapter, union recv_frame *rframe) +{ + int ret; + struct rx_pkt_attrib *prxattrib = &rframe->u.hdr.attrib; + struct recv_priv *recvpriv = &padapter->recvpriv; + struct security_priv *psecuritypriv=&padapter->securitypriv; + struct mlme_priv *mlmepriv = &padapter->mlmepriv; + + if (check_fwstate(mlmepriv, WIFI_MONITOR_STATE)) { + /* monitor mode */ + recv_frame_monitor(padapter, rframe); + ret = _SUCCESS; + goto exit; + } else + + /* check if need to handle uc_swdec_pending_queue*/ + if (check_fwstate(mlmepriv, WIFI_STATION_STATE) && psecuritypriv->busetkipkey) + { + union recv_frame *pending_frame; + int cnt = 0; + + while((pending_frame=rtw_alloc_recvframe(&padapter->recvpriv.uc_swdec_pending_queue))) { + cnt++; + DBG_COUNTER(padapter->rx_logs.core_rx_dequeue); + recv_func_posthandle(padapter, pending_frame); + } + + if (cnt) + DBG_871X(FUNC_ADPT_FMT" dequeue %d from uc_swdec_pending_queue\n", + FUNC_ADPT_ARG(padapter), cnt); + } + + DBG_COUNTER(padapter->rx_logs.core_rx); + ret = recv_func_prehandle(padapter, rframe); + + if(ret == _SUCCESS) { + + /* check if need to enqueue into uc_swdec_pending_queue*/ + if (check_fwstate(mlmepriv, WIFI_STATION_STATE) && + !IS_MCAST(prxattrib->ra) && prxattrib->encrypt>0 && + (prxattrib->bdecrypted == 0 ||psecuritypriv->sw_decrypt == _TRUE) && + psecuritypriv->ndisauthtype == Ndis802_11AuthModeWPAPSK && + !psecuritypriv->busetkipkey) + { + DBG_COUNTER(padapter->rx_logs.core_rx_enqueue); + rtw_enqueue_recvframe(rframe, &padapter->recvpriv.uc_swdec_pending_queue); + //DBG_871X("%s: no key, enqueue uc_swdec_pending_queue\n", __func__); + + if (recvpriv->free_recvframe_cnt < NR_RECVFRAME/4) { + /* to prevent from recvframe starvation, get recvframe from uc_swdec_pending_queue to free_recvframe_cnt */ + rframe = rtw_alloc_recvframe(&padapter->recvpriv.uc_swdec_pending_queue); + if (rframe) + goto do_posthandle; + } + goto exit; + } + +do_posthandle: + ret = recv_func_posthandle(padapter, rframe); + } + +exit: + return ret; +} + + +s32 rtw_recv_entry(union recv_frame *precvframe) +{ + _adapter *padapter; + struct recv_priv *precvpriv; + s32 ret=_SUCCESS; + +_func_enter_; + +// RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("+rtw_recv_entry\n")); + + padapter = precvframe->u.hdr.adapter; + + precvpriv = &padapter->recvpriv; + + + if ((ret = recv_func(padapter, precvframe)) == _FAIL) + { + RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("rtw_recv_entry: recv_func return fail!!!\n")); + goto _recv_entry_drop; + } + + + precvpriv->rx_pkts++; + +_func_exit_; + + return ret; + +_recv_entry_drop: + +#ifdef CONFIG_MP_INCLUDED + if (padapter->registrypriv.mp_mode == 1) + padapter->mppriv.rx_pktloss = precvpriv->rx_drop; +#endif + + //RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("_recv_entry_drop\n")); + +_func_exit_; + + return ret; +} + +#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS +void rtw_signal_stat_timer_hdl(RTW_TIMER_HDL_ARGS){ + _adapter *adapter = (_adapter *)FunctionContext; + struct recv_priv *recvpriv = &adapter->recvpriv; + + u32 tmp_s, tmp_q; + u8 avg_signal_strength = 0; + u8 avg_signal_qual = 0; + u32 num_signal_strength = 0; + u32 num_signal_qual = 0; + u8 ratio_pre_stat = 0, ratio_curr_stat = 0, ratio_total = 0, ratio_profile = SIGNAL_STAT_CALC_PROFILE_0; + + if(adapter->recvpriv.is_signal_dbg) { + //update the user specific value, signal_strength_dbg, to signal_strength, rssi + adapter->recvpriv.signal_strength= adapter->recvpriv.signal_strength_dbg; + adapter->recvpriv.rssi=(s8)translate_percentage_to_dbm((u8)adapter->recvpriv.signal_strength_dbg); + } else { + + if(recvpriv->signal_strength_data.update_req == 0) {// update_req is clear, means we got rx + avg_signal_strength = recvpriv->signal_strength_data.avg_val; + num_signal_strength = recvpriv->signal_strength_data.total_num; + // after avg_vals are accquired, we can re-stat the signal values + recvpriv->signal_strength_data.update_req = 1; + } + + if(recvpriv->signal_qual_data.update_req == 0) {// update_req is clear, means we got rx + avg_signal_qual = recvpriv->signal_qual_data.avg_val; + num_signal_qual = recvpriv->signal_qual_data.total_num; + // after avg_vals are accquired, we can re-stat the signal values + recvpriv->signal_qual_data.update_req = 1; + } + + if (num_signal_strength == 0) { + if (rtw_get_on_cur_ch_time(adapter) == 0 + || rtw_get_passing_time_ms(rtw_get_on_cur_ch_time(adapter)) < 2 * adapter->mlmeextpriv.mlmext_info.bcn_interval + ) { + goto set_timer; + } + } + + if(check_fwstate(&adapter->mlmepriv, _FW_UNDER_SURVEY) == _TRUE + || check_fwstate(&adapter->mlmepriv, _FW_LINKED) == _FALSE + ) { + goto set_timer; + } + + #ifdef CONFIG_CONCURRENT_MODE + if (check_buddy_fwstate(adapter, _FW_UNDER_SURVEY) == _TRUE) + goto set_timer; + #endif + + if (RTW_SIGNAL_STATE_CALC_PROFILE < SIGNAL_STAT_CALC_PROFILE_MAX) + ratio_profile = RTW_SIGNAL_STATE_CALC_PROFILE; + + ratio_pre_stat = signal_stat_calc_profile[ratio_profile][0]; + ratio_curr_stat = signal_stat_calc_profile[ratio_profile][1]; + ratio_total = ratio_pre_stat + ratio_curr_stat; + + //update value of signal_strength, rssi, signal_qual + tmp_s = (ratio_curr_stat * avg_signal_strength + ratio_pre_stat * recvpriv->signal_strength); + if (tmp_s % ratio_total) + tmp_s = tmp_s / ratio_total + 1; + else + tmp_s = tmp_s / ratio_total; + if (tmp_s > 100) + tmp_s = 100; + + tmp_q = (ratio_curr_stat * avg_signal_qual + ratio_pre_stat * recvpriv->signal_qual); + if (tmp_q % ratio_total) + tmp_q = tmp_q / ratio_total + 1; + else + tmp_q = tmp_q / ratio_total; + if (tmp_q > 100) + tmp_q = 100; + + recvpriv->signal_strength = tmp_s; + recvpriv->rssi = (s8)translate_percentage_to_dbm(tmp_s); + recvpriv->signal_qual = tmp_q; + + #if defined(DBG_RX_SIGNAL_DISPLAY_PROCESSING) && 1 + DBG_871X(FUNC_ADPT_FMT" signal_strength:%3u, rssi:%3d, signal_qual:%3u" + ", num_signal_strength:%u, num_signal_qual:%u" + ", on_cur_ch_ms:%d" + "\n" + , FUNC_ADPT_ARG(adapter) + , recvpriv->signal_strength + , recvpriv->rssi + , recvpriv->signal_qual + , num_signal_strength, num_signal_qual + , rtw_get_on_cur_ch_time(adapter) ? rtw_get_passing_time_ms(rtw_get_on_cur_ch_time(adapter)) : 0 + ); + #endif + } + +set_timer: + rtw_set_signal_stat_timer(recvpriv); + +} +#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS + +static void rx_process_rssi(_adapter *padapter,union recv_frame *prframe) +{ + u32 last_rssi, tmp_val; + struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; +#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS + struct signal_stat * signal_stat = &padapter->recvpriv.signal_strength_data; +#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS + + //DBG_8192C("process_rssi=> pattrib->rssil(%d) signal_strength(%d)\n ",pattrib->RecvSignalPower,pattrib->signal_strength); + //if(pRfd->Status.bPacketToSelf || pRfd->Status.bPacketBeacon) + { + #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS + if(signal_stat->update_req) { + signal_stat->total_num = 0; + signal_stat->total_val = 0; + signal_stat->update_req = 0; + } + + signal_stat->total_num++; + signal_stat->total_val += pattrib->phy_info.SignalStrength; + signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num; + #else //CONFIG_NEW_SIGNAL_STAT_PROCESS + + //Adapter->RxStats.RssiCalculateCnt++; //For antenna Test + if(padapter->recvpriv.signal_strength_data.total_num++ >= PHY_RSSI_SLID_WIN_MAX) + { + padapter->recvpriv.signal_strength_data.total_num = PHY_RSSI_SLID_WIN_MAX; + last_rssi = padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index]; + padapter->recvpriv.signal_strength_data.total_val -= last_rssi; + } + padapter->recvpriv.signal_strength_data.total_val +=pattrib->phy_info.SignalStrength; + + padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index++] = pattrib->phy_info.SignalStrength; + if(padapter->recvpriv.signal_strength_data.index >= PHY_RSSI_SLID_WIN_MAX) + padapter->recvpriv.signal_strength_data.index = 0; + + + tmp_val = padapter->recvpriv.signal_strength_data.total_val/padapter->recvpriv.signal_strength_data.total_num; + + if(padapter->recvpriv.is_signal_dbg) { + padapter->recvpriv.signal_strength= padapter->recvpriv.signal_strength_dbg; + padapter->recvpriv.rssi=(s8)translate_percentage_to_dbm(padapter->recvpriv.signal_strength_dbg); + } else { + padapter->recvpriv.signal_strength= tmp_val; + padapter->recvpriv.rssi=(s8)translate_percentage_to_dbm(tmp_val); + } + + RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("UI RSSI = %d, ui_rssi.TotalVal = %d, ui_rssi.TotalNum = %d\n", tmp_val, padapter->recvpriv.signal_strength_data.total_val,padapter->recvpriv.signal_strength_data.total_num)); + #endif //CONFIG_NEW_SIGNAL_STAT_PROCESS + } +} + +static void rx_process_link_qual(_adapter *padapter,union recv_frame *prframe) +{ + u32 last_evm=0, tmpVal; + struct rx_pkt_attrib *pattrib; +#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS + struct signal_stat * signal_stat; +#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS + + if(prframe == NULL || padapter==NULL){ + return; + } + + pattrib = &prframe->u.hdr.attrib; +#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS + signal_stat = &padapter->recvpriv.signal_qual_data; +#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS + + //DBG_8192C("process_link_qual=> pattrib->signal_qual(%d)\n ",pattrib->signal_qual); + +#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS + if(signal_stat->update_req) { + signal_stat->total_num = 0; + signal_stat->total_val = 0; + signal_stat->update_req = 0; + } + + signal_stat->total_num++; + signal_stat->total_val += pattrib->phy_info.SignalQuality; + signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num; + +#else //CONFIG_NEW_SIGNAL_STAT_PROCESS + if(pattrib->phy_info.SignalQuality != 0) + { + // + // 1. Record the general EVM to the sliding window. + // + if(padapter->recvpriv.signal_qual_data.total_num++ >= PHY_LINKQUALITY_SLID_WIN_MAX) + { + padapter->recvpriv.signal_qual_data.total_num = PHY_LINKQUALITY_SLID_WIN_MAX; + last_evm = padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index]; + padapter->recvpriv.signal_qual_data.total_val -= last_evm; + } + padapter->recvpriv.signal_qual_data.total_val += pattrib->phy_info.SignalQuality; + + padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = pattrib->phy_info.SignalQuality; + if(padapter->recvpriv.signal_qual_data.index >= PHY_LINKQUALITY_SLID_WIN_MAX) + padapter->recvpriv.signal_qual_data.index = 0; + + RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("Total SQ=%d pattrib->signal_qual= %d\n", padapter->recvpriv.signal_qual_data.total_val, pattrib->phy_info.SignalQuality)); + + // <1> Showed on UI for user, in percentage. + tmpVal = padapter->recvpriv.signal_qual_data.total_val/padapter->recvpriv.signal_qual_data.total_num; + padapter->recvpriv.signal_qual=(u8)tmpVal; + + } + else + { + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" pattrib->signal_qual =%d\n", pattrib->phy_info.SignalQuality)); + } +#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS +} + +void rx_process_phy_info(_adapter *padapter, union recv_frame *rframe) +{ + /* Check RSSI */ + rx_process_rssi(padapter, rframe); + + /* Check PWDB */ + //process_PWDB(padapter, rframe); + + //UpdateRxSignalStatistics8192C(Adapter, pRfd); + + /* Check EVM */ + rx_process_link_qual(padapter, rframe); + #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA + rtw_store_phy_info( padapter, rframe); + #endif +} + +void rx_query_phy_status( + union recv_frame *precvframe, + u8 *pphy_status) +{ + PADAPTER padapter = precvframe->u.hdr.adapter; + struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + PODM_PHY_INFO_T pPHYInfo = (PODM_PHY_INFO_T)(&pattrib->phy_info); + u8 *wlanhdr; + ODM_PACKET_INFO_T pkt_info; + u8 *sa; + struct sta_priv *pstapriv; + struct sta_info *psta = NULL; + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + //_irqL irqL; + + pkt_info.bPacketMatchBSSID =_FALSE; + pkt_info.bPacketToSelf = _FALSE; + pkt_info.bPacketBeacon = _FALSE; + + wlanhdr = get_recvframe_data(precvframe); + + pkt_info.bPacketMatchBSSID = (!IsFrameTypeCtrl(wlanhdr)) + && (!pattrib->icv_err) && (!pattrib->crc_err) + && _rtw_memcmp(get_hdr_bssid(wlanhdr), get_bssid(&padapter->mlmepriv), ETH_ALEN); + + pkt_info.bToSelf = (!pattrib->icv_err) && (!pattrib->crc_err) + && _rtw_memcmp(get_ra(wlanhdr), adapter_mac_addr(padapter), ETH_ALEN); + + pkt_info.bPacketToSelf = pkt_info.bPacketMatchBSSID + && _rtw_memcmp(get_ra(wlanhdr), adapter_mac_addr(padapter), ETH_ALEN); + + pkt_info.bPacketBeacon = pkt_info.bPacketMatchBSSID + && (GetFrameSubType(wlanhdr) == WIFI_BEACON); + + sa = get_ta(wlanhdr); + + pkt_info.StationID = 0xFF; + + if (_rtw_memcmp(adapter_mac_addr(padapter), sa, ETH_ALEN) == _TRUE) { + static u32 start_time = 0; + +#if 0 /*For debug */ + if (IsFrameTypeCtrl(wlanhdr)) { + DBG_871X("-->Control frame: Y\n"); + DBG_871X("-->pkt_len: %d\n", pattrib->pkt_len); + DBG_871X("-->Sub Type = 0x%X\n", GetFrameSubType(wlanhdr)); + } + + /* Dump first 40 bytes of header */ + int i = 0; + + for (i = 0; i < 40; i++) + DBG_871X("%d: %X\n", i, *((u8 *)wlanhdr + i)); + + DBG_871X("\n"); +#endif + + if ((start_time == 0) || (rtw_get_passing_time_ms(start_time) > 5000)) { + DBG_871X_LEVEL(_drv_always_, "Warning!!! %s: Confilc mac addr!!\n", __func__); + start_time = rtw_get_current_time(); + } + pdbgpriv->dbg_rx_conflic_mac_addr_cnt++; + } else{ + pstapriv = &padapter->stapriv; + psta = rtw_get_stainfo(pstapriv, sa); + if (psta) + pkt_info.StationID = psta->mac_id; + } + + pkt_info.DataRate = pattrib->data_rate; + + //_enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); + ODM_PhyStatusQuery(&pHalData->odmpriv, pPHYInfo, pphy_status, &pkt_info); + if (psta) + psta->rssi = pattrib->phy_info.RecvSignalPower; + //_exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); + + { + precvframe->u.hdr.psta = NULL; + if (pkt_info.bPacketMatchBSSID + && (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) + ) { + if (psta) { + precvframe->u.hdr.psta = psta; + rx_process_phy_info(padapter, precvframe); + } + } else if (pkt_info.bPacketToSelf || pkt_info.bPacketBeacon) { + if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == _TRUE) { + if (psta) + precvframe->u.hdr.psta = psta; + } + rx_process_phy_info(padapter, precvframe); + } + } +} +/* +* Increase and check if the continual_no_rx_packet of this @param pmlmepriv is larger than MAX_CONTINUAL_NORXPACKET_COUNT +* @return _TRUE: +* @return _FALSE: +*/ +int rtw_inc_and_chk_continual_no_rx_packet(struct sta_info *sta, int tid_index) +{ + + int ret = _FALSE; + int value = ATOMIC_INC_RETURN(&sta->continual_no_rx_packet[tid_index]); + + if (value >= MAX_CONTINUAL_NORXPACKET_COUNT) + ret = _TRUE; + + return ret; +} + +/* +* Set the continual_no_rx_packet of this @param pmlmepriv to 0 +*/ +void rtw_reset_continual_no_rx_packet(struct sta_info *sta, int tid_index) +{ + ATOMIC_SET(&sta->continual_no_rx_packet[tid_index], 0); +} diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_rf.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_rf.c new file mode 100644 index 000000000..e97af16bb --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_rf.c @@ -0,0 +1,741 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_RF_C_ + +#include +#include + +u8 center_ch_5g_all[CENTER_CH_5G_ALL_NUM] = { + 36, 38, 40, 42, 44, 46, 48, /* Band 1 */ + 52, 54, 56, 58, 60, 62, 64, /* Band 2 */ + 100, 102, 104, 106, 108, 110, 112, /* Band 3 */ + 116, 118, 120, 122, 124, 126, 128, /* Band 3 */ + 132, 134, 136, 138, 140, 142, 144, /* Band 3 */ + 149, 151, 153, 155, 157, 159, 161, /* Band 4 */ + 165, 167, 169, 171, 173, 175, 177}; /* Band 4 */ + +u8 center_ch_5g_20m[CENTER_CH_5G_20M_NUM] = { + 36, 40, 44, 48, + 52, 56, 60, 64, + 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, + 149, 153, 157, 161, 165, 169, 173, 177 +}; + +u8 center_ch_5g_40m[CENTER_CH_5G_40M_NUM] = {38, 46, 54, 62, 102, 110, 118, 126, 134, 142, 151, 159, 167, 175}; + +u8 center_ch_5g_80m[CENTER_CH_5G_80M_NUM] = {42, 58, 106, 122, 138, 155, 171}; + +struct center_chs_ent { + u8 ch_num; + u8 *chs; +}; + +struct center_chs_ent center_chs_5g_by_bw[] = { + {CENTER_CH_5G_20M_NUM, center_ch_5g_20m}, + {CENTER_CH_5G_40M_NUM, center_ch_5g_40m}, + {CENTER_CH_5G_80M_NUM, center_ch_5g_80m}, +}; + +inline u8 center_chs_5g_num(u8 bw) +{ + if (bw >= CHANNEL_WIDTH_160) + return 0; + + return center_chs_5g_by_bw[bw].ch_num; +} + +inline u8 center_chs_5g(u8 bw, u8 id) +{ + if (bw >= CHANNEL_WIDTH_160) + return 0; + + if (id >= center_chs_5g_num(bw)) + return 0; + + return center_chs_5g_by_bw[bw].chs[id]; +} + +int rtw_ch2freq(int chan) +{ + /* see 802.11 17.3.8.3.2 and Annex J + * there are overlapping channel numbers in 5GHz and 2GHz bands */ + + /* + * RTK: don't consider the overlapping channel numbers: 5G channel <= 14, + * because we don't support it. simply judge from channel number + */ + + if (chan >= 1 && chan <= 14) { + if (chan == 14) + return 2484; + else if (chan < 14) + return 2407 + chan * 5; + } else if (chan >= 36 && chan <= 177) { + return 5000 + chan * 5; + } + + return 0; /* not supported */ +} + +int rtw_freq2ch(int freq) +{ + /* see 802.11 17.3.8.3.2 and Annex J */ + if (freq == 2484) + return 14; + else if (freq < 2484) + return (freq - 2407) / 5; + else if (freq >= 4910 && freq <= 4980) + return (freq - 4000) / 5; + else if (freq <= 45000) /* DMG band lower limit */ + return (freq - 5000) / 5; + else if (freq >= 58320 && freq <= 64800) + return (freq - 56160) / 2160; + else + return 0; +} + +bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo) +{ + u8 c_ch; + u32 freq; + u32 hi_ret = 0, lo_ret = 0; + int i; + bool valid = _FALSE; + + if (hi) + *hi = 0; + if (lo) + *lo = 0; + + c_ch = rtw_get_center_ch(ch, bw, offset); + freq = rtw_ch2freq(c_ch); + + if (!freq) { + rtw_warn_on(1); + goto exit; + } + + if (bw == CHANNEL_WIDTH_80) { + hi_ret = freq + 40; + lo_ret = freq - 40; + } else if (bw == CHANNEL_WIDTH_40) { + hi_ret = freq + 20; + lo_ret = freq - 20; + } else if (bw == CHANNEL_WIDTH_20) { + hi_ret = freq + 10; + lo_ret = freq - 10; + } else { + rtw_warn_on(1); + } + + if (hi) + *hi = hi_ret; + if (lo) + *lo = lo_ret; + + valid = _TRUE; + +exit: + return valid; +} + +const char * const _ch_width_str[] = { + "20MHz", + "40MHz", + "80MHz", + "160MHz", + "80_80MHz", + "CHANNEL_WIDTH_MAX", +}; + +const u8 _ch_width_to_bw_cap[] = { + BW_CAP_20M, + BW_CAP_40M, + BW_CAP_80M, + BW_CAP_160M, + BW_CAP_80_80M, + 0, +}; + +const char * const _band_str[] = { + "2.4G", + "5G", + "BOTH", + "BAND_MAX", +}; + +const u8 _band_to_band_cap[] = { + BAND_CAP_2G, + BAND_CAP_5G, + 0, + 0, +}; + +#ifdef CONFIG_80211AC_VHT +#define COUNTRY_CHPLAN_ASSIGN_EN_11AC(_val) , .en_11ac = (_val) +#else +#define COUNTRY_CHPLAN_ASSIGN_EN_11AC(_val) +#endif + +#if RTW_DEF_MODULE_REGULATORY_CERT +#define COUNTRY_CHPLAN_ASSIGN_DEF_MODULE_FLAGS(_val) , .def_module_flags = (_val) +#else +#define COUNTRY_CHPLAN_ASSIGN_DEF_MODULE_FLAGS(_val) +#endif + +/* has def_module_flags specified, used by common map and HAL dfference map */ +#define COUNTRY_CHPLAN_ENT(_alpha2, _chplan, _en_11ac, _def_module_flags) \ + {.alpha2 = (_alpha2), .chplan = (_chplan) \ + COUNTRY_CHPLAN_ASSIGN_EN_11AC(_en_11ac) \ + COUNTRY_CHPLAN_ASSIGN_DEF_MODULE_FLAGS(_def_module_flags) \ + } + +#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP + +#include "../platform/custom_country_chplan.h" + +#elif RTW_DEF_MODULE_REGULATORY_CERT + +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AE_HMC_M2) +static const struct country_chplan RTL8821AE_HMC_M2_country_chplan_map[] = { + COUNTRY_CHPLAN_ENT("CN", 0x51, 1, 0xFB), /* China */ + COUNTRY_CHPLAN_ENT("RU", 0x59, 0, 0xFB), /* Russia(fac/gost), Kaliningrad */ + COUNTRY_CHPLAN_ENT("UA", 0x26, 0, 0xFB), /* Ukraine */ +}; +static const u16 RTL8821AE_HMC_M2_country_chplan_map_sz = sizeof(RTL8821AE_HMC_M2_country_chplan_map)/sizeof(struct country_chplan); +#endif + +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8821AU) +static const struct country_chplan RTL8821AU_country_chplan_map[] = { + COUNTRY_CHPLAN_ENT("RU", 0x59, 0, 0xFB), /* Russia(fac/gost), Kaliningrad */ + COUNTRY_CHPLAN_ENT("UA", 0x26, 0, 0xFB), /* Ukraine */ +}; +static const u16 RTL8821AU_country_chplan_map_sz = sizeof(RTL8821AU_country_chplan_map)/sizeof(struct country_chplan); +#endif + +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AENF_NGFF) +static const struct country_chplan RTL8812AENF_NGFF_country_chplan_map[] = { +}; +static const u16 RTL8812AENF_NGFF_country_chplan_map_sz = sizeof(RTL8812AENF_NGFF_country_chplan_map)/sizeof(struct country_chplan); +#endif + +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8812AEBT_HMC) +static const struct country_chplan RTL8812AEBT_HMC_country_chplan_map[] = { +}; +static const u16 RTL8812AEBT_HMC_country_chplan_map_sz = sizeof(RTL8812AEBT_HMC_country_chplan_map)/sizeof(struct country_chplan); +#endif + +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8188EE_HMC_M2) +static const struct country_chplan RTL8188EE_HMC_M2_country_chplan_map[] = { +}; +static const u16 RTL8188EE_HMC_M2_country_chplan_map_sz = sizeof(RTL8188EE_HMC_M2_country_chplan_map)/sizeof(struct country_chplan); +#endif + +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BE_HMC_M2) +static const struct country_chplan RTL8723BE_HMC_M2_country_chplan_map[] = { +}; +static const u16 RTL8723BE_HMC_M2_country_chplan_map_sz = sizeof(RTL8723BE_HMC_M2_country_chplan_map)/sizeof(struct country_chplan); +#endif + +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8723BS_NGFF1216) +static const struct country_chplan RTL8723BS_NGFF1216_country_chplan_map[] = { +}; +static const u16 RTL8723BS_NGFF1216_country_chplan_map_sz = sizeof(RTL8723BS_NGFF1216_country_chplan_map)/sizeof(struct country_chplan); +#endif + +#if (RTW_DEF_MODULE_REGULATORY_CERT & RTW_MODULE_RTL8192EEBT_HMC_M2) +static const struct country_chplan RTL8192EEBT_HMC_M2_country_chplan_map[] = { +}; +static const u16 RTL8192EEBT_HMC_M2_country_chplan_map_sz = sizeof(RTL8192EEBT_HMC_M2_country_chplan_map)/sizeof(struct country_chplan); +#endif + +/** + * rtw_def_module_get_chplan_from_country - + * @country_code: string of country code + * @return: + * Return NULL for case referring to common map + */ +static const struct country_chplan *rtw_def_module_get_chplan_from_country(const char *country_code) +{ + const struct country_chplan *ent = NULL; + const struct country_chplan *hal_map = NULL; + u16 hal_map_sz = 0; + int i; + + /* TODO: runtime selection for multi driver */ +#if (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8821AE_HMC_M2) + hal_map = RTL8821AE_HMC_M2_country_chplan_map; + hal_map_sz = RTL8821AE_HMC_M2_country_chplan_map_sz; +#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8821AU) + hal_map = RTL8821AU_country_chplan_map; + hal_map_sz = RTL8821AU_country_chplan_map_sz; +#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8812AENF_NGFF) + hal_map = RTL8812AENF_NGFF_country_chplan_map; + hal_map_sz = RTL8812AENF_NGFF_country_chplan_map_sz; +#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8812AEBT_HMC) + hal_map = RTL8812AEBT_HMC_country_chplan_map; + hal_map_sz = RTL8812AEBT_HMC_country_chplan_map_sz; +#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8188EE_HMC_M2) + hal_map = RTL8188EE_HMC_M2_country_chplan_map; + hal_map_sz = RTL8188EE_HMC_M2_country_chplan_map_sz; +#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723BE_HMC_M2) + hal_map = RTL8723BE_HMC_M2_country_chplan_map; + hal_map_sz = RTL8723BE_HMC_M2_country_chplan_map_sz; +#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8723BS_NGFF1216) + hal_map = RTL8723BS_NGFF1216_country_chplan_map; + hal_map_sz = RTL8723BS_NGFF1216_country_chplan_map_sz; +#elif (RTW_DEF_MODULE_REGULATORY_CERT == RTW_MODULE_RTL8192EEBT_HMC_M2) + hal_map = RTL8192EEBT_HMC_M2_country_chplan_map; + hal_map_sz = RTL8192EEBT_HMC_M2_country_chplan_map_sz; +#endif + + if (hal_map == NULL || hal_map_sz == 0) + goto exit; + + for (i = 0; i < hal_map_sz; i++) { + if (strncmp(country_code, hal_map[i].alpha2, 2) == 0) { + ent = &hal_map[i]; + break; + } + } + +exit: + return ent; +} +#endif /* CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP or RTW_DEF_MODULE_REGULATORY_CERT */ + +static const struct country_chplan country_chplan_map[] = { + COUNTRY_CHPLAN_ENT("AD", 0x26, 1, 0x00), /* Andorra */ + COUNTRY_CHPLAN_ENT("AE", 0x26, 1, 0xFB), /* United Arab Emirates */ + COUNTRY_CHPLAN_ENT("AF", 0x42, 1, 0x00), /* Afghanistan */ + COUNTRY_CHPLAN_ENT("AG", 0x30, 1, 0x00), /* Antigua & Barbuda */ + COUNTRY_CHPLAN_ENT("AI", 0x26, 1, 0x00), /* Anguilla(UK) */ + COUNTRY_CHPLAN_ENT("AL", 0x26, 1, 0xF1), /* Albania */ + COUNTRY_CHPLAN_ENT("AM", 0x26, 1, 0xB0), /* Armenia */ + COUNTRY_CHPLAN_ENT("AO", 0x26, 1, 0xE0), /* Angola */ + COUNTRY_CHPLAN_ENT("AQ", 0x26, 1, 0x00), /* Antarctica */ + COUNTRY_CHPLAN_ENT("AR", 0x57, 1, 0xF3), /* Argentina */ + COUNTRY_CHPLAN_ENT("AS", 0x34, 1, 0x00), /* American Samoa */ + COUNTRY_CHPLAN_ENT("AT", 0x26, 1, 0xFB), /* Austria */ + COUNTRY_CHPLAN_ENT("AU", 0x45, 1, 0xFB), /* Australia */ + COUNTRY_CHPLAN_ENT("AW", 0x34, 1, 0xB0), /* Aruba */ + COUNTRY_CHPLAN_ENT("AZ", 0x26, 1, 0xF1), /* Azerbaijan */ + COUNTRY_CHPLAN_ENT("BA", 0x26, 1, 0xF1), /* Bosnia & Herzegovina */ + COUNTRY_CHPLAN_ENT("BB", 0x34, 1, 0x50), /* Barbados */ + COUNTRY_CHPLAN_ENT("BD", 0x26, 1, 0xF1), /* Bangladesh */ + COUNTRY_CHPLAN_ENT("BE", 0x26, 1, 0xFB), /* Belgium */ + COUNTRY_CHPLAN_ENT("BF", 0x26, 1, 0xB0), /* Burkina Faso */ + COUNTRY_CHPLAN_ENT("BG", 0x26, 1, 0xF1), /* Bulgaria */ + COUNTRY_CHPLAN_ENT("BH", 0x47, 1, 0xF1), /* Bahrain */ + COUNTRY_CHPLAN_ENT("BI", 0x26, 1, 0xB0), /* Burundi */ + COUNTRY_CHPLAN_ENT("BJ", 0x26, 1, 0xB0), /* Benin */ + COUNTRY_CHPLAN_ENT("BN", 0x47, 1, 0x10), /* Brunei */ + COUNTRY_CHPLAN_ENT("BO", 0x30, 1, 0xF1), /* Bolivia */ + COUNTRY_CHPLAN_ENT("BR", 0x34, 1, 0xF1), /* Brazil */ + COUNTRY_CHPLAN_ENT("BS", 0x34, 1, 0x20), /* Bahamas */ + COUNTRY_CHPLAN_ENT("BW", 0x26, 1, 0xF1), /* Botswana */ + COUNTRY_CHPLAN_ENT("BY", 0x26, 1, 0xF1), /* Belarus */ + COUNTRY_CHPLAN_ENT("BZ", 0x34, 1, 0x00), /* Belize */ + COUNTRY_CHPLAN_ENT("CA", 0x34, 1, 0xFB), /* Canada */ + COUNTRY_CHPLAN_ENT("CC", 0x26, 1, 0x00), /* Cocos (Keeling) Islands (Australia) */ + COUNTRY_CHPLAN_ENT("CD", 0x26, 1, 0xB0), /* Congo, Republic of the */ + COUNTRY_CHPLAN_ENT("CF", 0x26, 1, 0xB0), /* Central African Republic */ + COUNTRY_CHPLAN_ENT("CG", 0x26, 1, 0xB0), /* Congo, Democratic Republic of the. Zaire */ + COUNTRY_CHPLAN_ENT("CH", 0x26, 1, 0xFB), /* Switzerland */ + COUNTRY_CHPLAN_ENT("CI", 0x26, 1, 0xF1), /* Cote d'Ivoire */ + COUNTRY_CHPLAN_ENT("CK", 0x26, 1, 0x00), /* Cook Islands */ + COUNTRY_CHPLAN_ENT("CL", 0x30, 1, 0xF1), /* Chile */ + COUNTRY_CHPLAN_ENT("CM", 0x26, 1, 0xB0), /* Cameroon */ + COUNTRY_CHPLAN_ENT("CN", 0x48, 1, 0xFB), /* China */ + COUNTRY_CHPLAN_ENT("CO", 0x34, 1, 0xF1), /* Colombia */ + COUNTRY_CHPLAN_ENT("CR", 0x34, 1, 0xF1), /* Costa Rica */ + COUNTRY_CHPLAN_ENT("CV", 0x26, 1, 0xB0), /* Cape Verde */ + COUNTRY_CHPLAN_ENT("CX", 0x45, 1, 0x00), /* Christmas Island (Australia) */ + COUNTRY_CHPLAN_ENT("CY", 0x26, 1, 0xFB), /* Cyprus */ + COUNTRY_CHPLAN_ENT("CZ", 0x26, 1, 0xFB), /* Czech Republic */ + COUNTRY_CHPLAN_ENT("DE", 0x26, 1, 0xFB), /* Germany */ + COUNTRY_CHPLAN_ENT("DJ", 0x26, 1, 0x80), /* Djibouti */ + COUNTRY_CHPLAN_ENT("DK", 0x26, 1, 0xFB), /* Denmark */ + COUNTRY_CHPLAN_ENT("DM", 0x34, 1, 0x00), /* Dominica */ + COUNTRY_CHPLAN_ENT("DO", 0x34, 1, 0xF1), /* Dominican Republic */ + COUNTRY_CHPLAN_ENT("DZ", 0x26, 1, 0xF1), /* Algeria */ + COUNTRY_CHPLAN_ENT("EC", 0x34, 1, 0xF1), /* Ecuador */ + COUNTRY_CHPLAN_ENT("EE", 0x26, 1, 0xFB), /* Estonia */ + COUNTRY_CHPLAN_ENT("EG", 0x47, 0, 0xF1), /* Egypt */ + COUNTRY_CHPLAN_ENT("EH", 0x47, 1, 0x80), /* Western Sahara */ + COUNTRY_CHPLAN_ENT("ER", 0x26, 1, 0x00), /* Eritrea */ + COUNTRY_CHPLAN_ENT("ES", 0x26, 1, 0xFB), /* Spain, Canary Islands, Ceuta, Melilla */ + COUNTRY_CHPLAN_ENT("ET", 0x26, 1, 0xB0), /* Ethiopia */ + COUNTRY_CHPLAN_ENT("FI", 0x26, 1, 0xFB), /* Finland */ + COUNTRY_CHPLAN_ENT("FJ", 0x34, 1, 0x00), /* Fiji */ + COUNTRY_CHPLAN_ENT("FK", 0x26, 1, 0x00), /* Falkland Islands (Islas Malvinas) (UK) */ + COUNTRY_CHPLAN_ENT("FM", 0x34, 1, 0x00), /* Micronesia, Federated States of (USA) */ + COUNTRY_CHPLAN_ENT("FO", 0x26, 1, 0x00), /* Faroe Islands (Denmark) */ + COUNTRY_CHPLAN_ENT("FR", 0x26, 1, 0xFB), /* France */ + COUNTRY_CHPLAN_ENT("GA", 0x26, 1, 0xB0), /* Gabon */ + COUNTRY_CHPLAN_ENT("GB", 0x26, 1, 0xFB), /* Great Britain (United Kingdom; England) */ + COUNTRY_CHPLAN_ENT("GD", 0x34, 1, 0xB0), /* Grenada */ + COUNTRY_CHPLAN_ENT("GE", 0x26, 1, 0x00), /* Georgia */ + COUNTRY_CHPLAN_ENT("GF", 0x26, 1, 0x80), /* French Guiana */ + COUNTRY_CHPLAN_ENT("GG", 0x26, 1, 0x00), /* Guernsey (UK) */ + COUNTRY_CHPLAN_ENT("GH", 0x26, 1, 0xF1), /* Ghana */ + COUNTRY_CHPLAN_ENT("GI", 0x26, 1, 0x00), /* Gibraltar (UK) */ + COUNTRY_CHPLAN_ENT("GL", 0x26, 1, 0x00), /* Greenland (Denmark) */ + COUNTRY_CHPLAN_ENT("GM", 0x26, 1, 0xB0), /* Gambia */ + COUNTRY_CHPLAN_ENT("GN", 0x26, 1, 0x10), /* Guinea */ + COUNTRY_CHPLAN_ENT("GP", 0x26, 1, 0x00), /* Guadeloupe (France) */ + COUNTRY_CHPLAN_ENT("GQ", 0x26, 1, 0xB0), /* Equatorial Guinea */ + COUNTRY_CHPLAN_ENT("GR", 0x26, 1, 0xFB), /* Greece */ + COUNTRY_CHPLAN_ENT("GS", 0x26, 1, 0x00), /* South Georgia and the Sandwich Islands (UK) */ + COUNTRY_CHPLAN_ENT("GT", 0x34, 1, 0xF1), /* Guatemala */ + COUNTRY_CHPLAN_ENT("GU", 0x34, 1, 0x00), /* Guam (USA) */ + COUNTRY_CHPLAN_ENT("GW", 0x26, 1, 0xB0), /* Guinea-Bissau */ + COUNTRY_CHPLAN_ENT("GY", 0x44, 1, 0x00), /* Guyana */ + COUNTRY_CHPLAN_ENT("HK", 0x26, 1, 0xFB), /* Hong Kong */ + COUNTRY_CHPLAN_ENT("HM", 0x45, 1, 0x00), /* Heard and McDonald Islands (Australia) */ + COUNTRY_CHPLAN_ENT("HN", 0x32, 1, 0xF1), /* Honduras */ + COUNTRY_CHPLAN_ENT("HR", 0x26, 1, 0xF9), /* Croatia */ + COUNTRY_CHPLAN_ENT("HT", 0x34, 1, 0x50), /* Haiti */ + COUNTRY_CHPLAN_ENT("HU", 0x26, 1, 0xFB), /* Hungary */ + COUNTRY_CHPLAN_ENT("ID", 0x54, 0, 0xF3), /* Indonesia */ + COUNTRY_CHPLAN_ENT("IE", 0x26, 1, 0xFB), /* Ireland */ + COUNTRY_CHPLAN_ENT("IL", 0x47, 1, 0xF1), /* Israel */ + COUNTRY_CHPLAN_ENT("IM", 0x26, 1, 0x00), /* Isle of Man (UK) */ + COUNTRY_CHPLAN_ENT("IN", 0x47, 1, 0xF1), /* India */ + COUNTRY_CHPLAN_ENT("IQ", 0x26, 1, 0x00), /* Iraq */ + COUNTRY_CHPLAN_ENT("IR", 0x26, 0, 0x00), /* Iran */ + COUNTRY_CHPLAN_ENT("IS", 0x26, 1, 0xFB), /* Iceland */ + COUNTRY_CHPLAN_ENT("IT", 0x26, 1, 0xFB), /* Italy */ + COUNTRY_CHPLAN_ENT("JE", 0x26, 1, 0x00), /* Jersey (UK) */ + COUNTRY_CHPLAN_ENT("JM", 0x51, 1, 0xF1), /* Jamaica */ + COUNTRY_CHPLAN_ENT("JO", 0x49, 1, 0xFB), /* Jordan */ + COUNTRY_CHPLAN_ENT("JP", 0x27, 1, 0xFF), /* Japan- Telec */ + COUNTRY_CHPLAN_ENT("KE", 0x47, 1, 0xF9), /* Kenya */ + COUNTRY_CHPLAN_ENT("KG", 0x26, 1, 0xF1), /* Kyrgyzstan */ + COUNTRY_CHPLAN_ENT("KH", 0x26, 1, 0xF1), /* Cambodia */ + COUNTRY_CHPLAN_ENT("KI", 0x26, 1, 0x00), /* Kiribati */ + COUNTRY_CHPLAN_ENT("KN", 0x34, 1, 0x00), /* Saint Kitts and Nevis */ + COUNTRY_CHPLAN_ENT("KR", 0x28, 1, 0xFB), /* South Korea */ + COUNTRY_CHPLAN_ENT("KW", 0x47, 1, 0xFB), /* Kuwait */ + COUNTRY_CHPLAN_ENT("KY", 0x34, 1, 0x00), /* Cayman Islands (UK) */ + COUNTRY_CHPLAN_ENT("KZ", 0x26, 1, 0x00), /* Kazakhstan */ + COUNTRY_CHPLAN_ENT("LA", 0x26, 1, 0x00), /* Laos */ + COUNTRY_CHPLAN_ENT("LB", 0x26, 1, 0xF1), /* Lebanon */ + COUNTRY_CHPLAN_ENT("LC", 0x34, 1, 0x00), /* Saint Lucia */ + COUNTRY_CHPLAN_ENT("LI", 0x26, 1, 0xFB), /* Liechtenstein */ + COUNTRY_CHPLAN_ENT("LK", 0x26, 1, 0xF1), /* Sri Lanka */ + COUNTRY_CHPLAN_ENT("LR", 0x26, 1, 0xB0), /* Liberia */ + COUNTRY_CHPLAN_ENT("LS", 0x26, 1, 0xF1), /* Lesotho */ + COUNTRY_CHPLAN_ENT("LT", 0x26, 1, 0xFB), /* Lithuania */ + COUNTRY_CHPLAN_ENT("LU", 0x26, 1, 0xFB), /* Luxembourg */ + COUNTRY_CHPLAN_ENT("LV", 0x26, 1, 0xFB), /* Latvia */ + COUNTRY_CHPLAN_ENT("LY", 0x26, 1, 0x00), /* Libya */ + COUNTRY_CHPLAN_ENT("MA", 0x47, 1, 0xF1), /* Morocco */ + COUNTRY_CHPLAN_ENT("MC", 0x26, 1, 0xFB), /* Monaco */ + COUNTRY_CHPLAN_ENT("MD", 0x26, 1, 0xF1), /* Moldova */ + COUNTRY_CHPLAN_ENT("ME", 0x26, 1, 0xF1), /* Montenegro */ + COUNTRY_CHPLAN_ENT("MF", 0x34, 1, 0x00), /* Saint Martin */ + COUNTRY_CHPLAN_ENT("MG", 0x26, 1, 0x20), /* Madagascar */ + COUNTRY_CHPLAN_ENT("MH", 0x34, 1, 0x00), /* Marshall Islands (USA) */ + COUNTRY_CHPLAN_ENT("MK", 0x26, 1, 0xF1), /* Republic of Macedonia (FYROM) */ + COUNTRY_CHPLAN_ENT("ML", 0x26, 1, 0xB0), /* Mali */ + COUNTRY_CHPLAN_ENT("MM", 0x26, 1, 0x00), /* Burma (Myanmar) */ + COUNTRY_CHPLAN_ENT("MN", 0x26, 1, 0x00), /* Mongolia */ + COUNTRY_CHPLAN_ENT("MO", 0x26, 1, 0x00), /* Macau */ + COUNTRY_CHPLAN_ENT("MP", 0x34, 1, 0x00), /* Northern Mariana Islands (USA) */ + COUNTRY_CHPLAN_ENT("MQ", 0x26, 1, 0x40), /* Martinique (France) */ + COUNTRY_CHPLAN_ENT("MR", 0x26, 1, 0xA0), /* Mauritania */ + COUNTRY_CHPLAN_ENT("MS", 0x26, 1, 0x00), /* Montserrat (UK) */ + COUNTRY_CHPLAN_ENT("MT", 0x26, 1, 0xFB), /* Malta */ + COUNTRY_CHPLAN_ENT("MU", 0x26, 1, 0xB0), /* Mauritius */ + COUNTRY_CHPLAN_ENT("MV", 0x26, 1, 0x00), /* Maldives */ + COUNTRY_CHPLAN_ENT("MW", 0x26, 1, 0xB0), /* Malawi */ + COUNTRY_CHPLAN_ENT("MX", 0x34, 1, 0xF1), /* Mexico */ + COUNTRY_CHPLAN_ENT("MY", 0x47, 1, 0xF1), /* Malaysia */ + COUNTRY_CHPLAN_ENT("MZ", 0x26, 1, 0xF1), /* Mozambique */ + COUNTRY_CHPLAN_ENT("NA", 0x26, 0, 0x00), /* Namibia */ + COUNTRY_CHPLAN_ENT("NC", 0x26, 1, 0x00), /* New Caledonia */ + COUNTRY_CHPLAN_ENT("NE", 0x26, 1, 0xB0), /* Niger */ + COUNTRY_CHPLAN_ENT("NF", 0x45, 1, 0x00), /* Norfolk Island (Australia) */ + COUNTRY_CHPLAN_ENT("NG", 0x50, 1, 0xF9), /* Nigeria */ + COUNTRY_CHPLAN_ENT("NI", 0x34, 1, 0xF1), /* Nicaragua */ + COUNTRY_CHPLAN_ENT("NL", 0x26, 1, 0xFB), /* Netherlands */ + COUNTRY_CHPLAN_ENT("NO", 0x26, 1, 0xFB), /* Norway */ + COUNTRY_CHPLAN_ENT("NP", 0x47, 1, 0xF0), /* Nepal */ + COUNTRY_CHPLAN_ENT("NR", 0x26, 1, 0x00), /* Nauru */ + COUNTRY_CHPLAN_ENT("NU", 0x45, 1, 0x00), /* Niue */ + COUNTRY_CHPLAN_ENT("NZ", 0x45, 1, 0xFB), /* New Zealand */ + COUNTRY_CHPLAN_ENT("OM", 0x26, 1, 0xF9), /* Oman */ + COUNTRY_CHPLAN_ENT("PA", 0x34, 1, 0xF1), /* Panama */ + COUNTRY_CHPLAN_ENT("PE", 0x34, 1, 0xF1), /* Peru */ + COUNTRY_CHPLAN_ENT("PF", 0x26, 1, 0x00), /* French Polynesia (France) */ + COUNTRY_CHPLAN_ENT("PG", 0x26, 1, 0xF1), /* Papua New Guinea */ + COUNTRY_CHPLAN_ENT("PH", 0x26, 1, 0xF1), /* Philippines */ + COUNTRY_CHPLAN_ENT("PK", 0x51, 1, 0xF1), /* Pakistan */ + COUNTRY_CHPLAN_ENT("PL", 0x26, 1, 0xFB), /* Poland */ + COUNTRY_CHPLAN_ENT("PM", 0x26, 1, 0x00), /* Saint Pierre and Miquelon (France) */ + COUNTRY_CHPLAN_ENT("PR", 0x34, 1, 0xF1), /* Puerto Rico */ + COUNTRY_CHPLAN_ENT("PT", 0x26, 1, 0xFB), /* Portugal */ + COUNTRY_CHPLAN_ENT("PW", 0x34, 1, 0x00), /* Palau */ + COUNTRY_CHPLAN_ENT("PY", 0x34, 1, 0xF1), /* Paraguay */ + COUNTRY_CHPLAN_ENT("QA", 0x51, 1, 0xF9), /* Qatar */ + COUNTRY_CHPLAN_ENT("RE", 0x26, 1, 0x00), /* Reunion (France) */ + COUNTRY_CHPLAN_ENT("RO", 0x26, 1, 0xF1), /* Romania */ + COUNTRY_CHPLAN_ENT("RS", 0x26, 1, 0xF1), /* Serbia, Kosovo */ + COUNTRY_CHPLAN_ENT("RU", 0x59, 1, 0xFB), /* Russia(fac/gost), Kaliningrad */ + COUNTRY_CHPLAN_ENT("RW", 0x26, 1, 0xB0), /* Rwanda */ + COUNTRY_CHPLAN_ENT("SA", 0x26, 1, 0xFB), /* Saudi Arabia */ + COUNTRY_CHPLAN_ENT("SB", 0x26, 1, 0x00), /* Solomon Islands */ + COUNTRY_CHPLAN_ENT("SC", 0x34, 1, 0x90), /* Seychelles */ + COUNTRY_CHPLAN_ENT("SE", 0x26, 1, 0xFB), /* Sweden */ + COUNTRY_CHPLAN_ENT("SG", 0x47, 1, 0xFB), /* Singapore */ + COUNTRY_CHPLAN_ENT("SH", 0x26, 1, 0x00), /* Saint Helena (UK) */ + COUNTRY_CHPLAN_ENT("SI", 0x26, 1, 0xFB), /* Slovenia */ + COUNTRY_CHPLAN_ENT("SJ", 0x26, 1, 0x00), /* Svalbard (Norway) */ + COUNTRY_CHPLAN_ENT("SK", 0x26, 1, 0xFB), /* Slovakia */ + COUNTRY_CHPLAN_ENT("SL", 0x26, 1, 0xB0), /* Sierra Leone */ + COUNTRY_CHPLAN_ENT("SM", 0x26, 1, 0x00), /* San Marino */ + COUNTRY_CHPLAN_ENT("SN", 0x26, 1, 0xF1), /* Senegal */ + COUNTRY_CHPLAN_ENT("SO", 0x26, 1, 0x00), /* Somalia */ + COUNTRY_CHPLAN_ENT("SR", 0x34, 1, 0x00), /* Suriname */ + COUNTRY_CHPLAN_ENT("ST", 0x34, 1, 0x80), /* Sao Tome and Principe */ + COUNTRY_CHPLAN_ENT("SV", 0x30, 1, 0xF1), /* El Salvador */ + COUNTRY_CHPLAN_ENT("SX", 0x34, 1, 0x00), /* Sint Marteen */ + COUNTRY_CHPLAN_ENT("SZ", 0x26, 1, 0x20), /* Swaziland */ + COUNTRY_CHPLAN_ENT("TC", 0x26, 1, 0x00), /* Turks and Caicos Islands (UK) */ + COUNTRY_CHPLAN_ENT("TD", 0x26, 1, 0xB0), /* Chad */ + COUNTRY_CHPLAN_ENT("TF", 0x26, 1, 0x80), /* French Southern and Antarctic Lands (FR Southern Territories) */ + COUNTRY_CHPLAN_ENT("TG", 0x26, 1, 0xB0), /* Togo */ + COUNTRY_CHPLAN_ENT("TH", 0x26, 1, 0xF1), /* Thailand */ + COUNTRY_CHPLAN_ENT("TJ", 0x26, 1, 0x40), /* Tajikistan */ + COUNTRY_CHPLAN_ENT("TK", 0x45, 1, 0x00), /* Tokelau */ + COUNTRY_CHPLAN_ENT("TM", 0x26, 1, 0x00), /* Turkmenistan */ + COUNTRY_CHPLAN_ENT("TN", 0x47, 1, 0xF1), /* Tunisia */ + COUNTRY_CHPLAN_ENT("TO", 0x26, 1, 0x00), /* Tonga */ + COUNTRY_CHPLAN_ENT("TR", 0x26, 1, 0xF1), /* Turkey, Northern Cyprus */ + COUNTRY_CHPLAN_ENT("TT", 0x42, 1, 0xF1), /* Trinidad & Tobago */ + COUNTRY_CHPLAN_ENT("TW", 0x39, 1, 0xFF), /* Taiwan */ + COUNTRY_CHPLAN_ENT("TZ", 0x26, 1, 0xF0), /* Tanzania */ + COUNTRY_CHPLAN_ENT("UA", 0x26, 1, 0xFB), /* Ukraine */ + COUNTRY_CHPLAN_ENT("UG", 0x26, 1, 0xF1), /* Uganda */ + COUNTRY_CHPLAN_ENT("US", 0x34, 1, 0xFF), /* United States of America (USA) */ + COUNTRY_CHPLAN_ENT("UY", 0x34, 1, 0xF1), /* Uruguay */ + COUNTRY_CHPLAN_ENT("UZ", 0x47, 1, 0xF0), /* Uzbekistan */ + COUNTRY_CHPLAN_ENT("VA", 0x26, 1, 0x00), /* Holy See (Vatican City) */ + COUNTRY_CHPLAN_ENT("VC", 0x34, 1, 0x10), /* Saint Vincent and the Grenadines */ + COUNTRY_CHPLAN_ENT("VE", 0x30, 1, 0xF1), /* Venezuela */ + COUNTRY_CHPLAN_ENT("VI", 0x34, 1, 0x00), /* United States Virgin Islands (USA) */ + COUNTRY_CHPLAN_ENT("VN", 0x26, 1, 0xF1), /* Vietnam */ + COUNTRY_CHPLAN_ENT("VU", 0x26, 1, 0x00), /* Vanuatu */ + COUNTRY_CHPLAN_ENT("WF", 0x26, 1, 0x00), /* Wallis and Futuna (France) */ + COUNTRY_CHPLAN_ENT("WS", 0x34, 1, 0x00), /* Samoa */ + COUNTRY_CHPLAN_ENT("YE", 0x26, 1, 0x40), /* Yemen */ + COUNTRY_CHPLAN_ENT("YT", 0x26, 1, 0x80), /* Mayotte (France) */ + COUNTRY_CHPLAN_ENT("ZA", 0x26, 1, 0xF1), /* South Africa */ + COUNTRY_CHPLAN_ENT("ZM", 0x26, 1, 0xB0), /* Zambia */ + COUNTRY_CHPLAN_ENT("ZW", 0x26, 1, 0xF1), /* Zimbabwe */ +}; + +u16 const country_chplan_map_sz = sizeof(country_chplan_map)/sizeof(struct country_chplan); + +/* +* rtw_get_chplan_from_country - +* @country_code: string of country code +* +* Return pointer of struct country_chplan entry or NULL when unsupported country_code is given +*/ +const struct country_chplan *rtw_get_chplan_from_country(const char *country_code) +{ + const struct country_chplan *ent = NULL; + const struct country_chplan *map = NULL; + u16 map_sz = 0; + char code[2]; + int i; + + code[0] = alpha_to_upper(country_code[0]); + code[1] = alpha_to_upper(country_code[1]); + +#if !defined(CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP) && RTW_DEF_MODULE_REGULATORY_CERT + ent = rtw_def_module_get_chplan_from_country(code); + if (ent != NULL) + goto exit; +#endif + +#ifdef CONFIG_CUSTOMIZED_COUNTRY_CHPLAN_MAP + map = CUSTOMIZED_country_chplan_map; + map_sz = CUSTOMIZED_country_chplan_map_sz; +#else + map = country_chplan_map; + map_sz = country_chplan_map_sz; +#endif + + for (i = 0; i < map_sz; i++) { + if (strncmp(code, map[i].alpha2, 2) == 0) { + ent = &map[i]; + break; + } + } + +exit: + #if RTW_DEF_MODULE_REGULATORY_CERT + if (ent && !(COUNTRY_CHPLAN_DEF_MODULE_FALGS(ent) & RTW_DEF_MODULE_REGULATORY_CERT)) + ent = NULL; + #endif + + return ent; +} + +int rtw_ch_to_bb_gain_sel(int ch) +{ + int sel = -1; + + if (ch >= 1 && ch <= 14) + sel = BB_GAIN_2G; +#ifdef CONFIG_IEEE80211_BAND_5GHZ + else if (ch >= 36 && ch < 48) + sel = BB_GAIN_5GLB1; + else if (ch >= 52 && ch <= 64) + sel = BB_GAIN_5GLB2; + else if (ch >= 100 && ch <= 120) + sel = BB_GAIN_5GMB1; + else if (ch >= 124 && ch <= 144) + sel = BB_GAIN_5GMB2; + else if (ch >= 149 && ch <= 177) + sel = BB_GAIN_5GHB; +#endif + + return sel; +} + +s8 rtw_rf_get_kfree_tx_gain_offset(_adapter *padapter, u8 path, u8 ch) +{ + s8 kfree_offset = 0; + +#ifdef CONFIG_RF_POWER_TRIM + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); + struct kfree_data_t *kfree_data = GET_KFREE_DATA(padapter); + s8 bb_gain_sel = rtw_ch_to_bb_gain_sel(ch); + + if (bb_gain_sel < BB_GAIN_2G || bb_gain_sel >= BB_GAIN_NUM) { + rtw_warn_on(1); + goto exit; + } + + if (kfree_data->flag & KFREE_FLAG_ON) { + kfree_offset = kfree_data->bb_gain[bb_gain_sel][path]; + if (1) + DBG_871X("%s path:%u, ch:%u, bb_gain_sel:%d, kfree_offset:%d\n" + , __func__, path, ch, bb_gain_sel, kfree_offset); + } +exit: +#endif /* CONFIG_RF_POWER_TRIM */ + return kfree_offset; +} + +void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset) +{ + u8 write_value; + + DBG_871X("kfree gain_offset 0x55:0x%x ", rtw_hal_read_rfreg(adapter, path, 0x55, 0xffffffff)); + switch (rtw_get_chip_type(adapter)) { +#ifdef CONFIG_RTL8703B + case RTL8703B: + write_value = RF_TX_GAIN_OFFSET_8703B(offset); + rtw_hal_write_rfreg(adapter, path, 0x55, 0x0fc000, write_value); + break; +#endif /* CONFIG_RTL8703B */ +#ifdef CONFIG_RTL8188F + case RTL8188F: + write_value = RF_TX_GAIN_OFFSET_8188F(offset); + rtw_hal_write_rfreg(adapter, path, 0x55, 0x0fc000, write_value); + break; +#endif /* CONFIG_RTL8188F */ +#ifdef CONFIG_RTL8192E + case RTL8192E: + write_value = RF_TX_GAIN_OFFSET_8192E(offset); + rtw_hal_write_rfreg(adapter, path, 0x55, 0x0f8000, write_value); + break; +#endif /* CONFIG_RTL8188F */ + +#ifdef CONFIG_RTL8821A + case RTL8821: + write_value = RF_TX_GAIN_OFFSET_8821A(offset); + rtw_hal_write_rfreg(adapter, path, 0x55, 0x0f8000, write_value); + break; +#endif /* CONFIG_RTL8821A */ +#ifdef CONFIG_RTL8814A + case RTL8814A: + DBG_871X("\nkfree by PhyDM on the sw CH. path %d\n", path); + break; +#endif /* CONFIG_RTL8821A */ + + default: + rtw_warn_on(1); + break; + } + + DBG_871X(" after :0x%x\n", rtw_hal_read_rfreg(adapter, path, 0x55, 0xffffffff)); +} + +void rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + s8 kfree_offset = 0; + s8 tx_pwr_track_offset = 0; /* TODO: 8814A should consider tx pwr track when setting tx gain offset */ + s8 total_offset; + int i; + + for (i = 0; i < hal_data->NumTotalRFPath; i++) { + kfree_offset = rtw_rf_get_kfree_tx_gain_offset(adapter, i, ch); + total_offset = kfree_offset + tx_pwr_track_offset; + rtw_rf_set_tx_gain_offset(adapter, i, total_offset); + } +} + +bool rtw_is_dfs_range(u32 hi, u32 lo) +{ + return rtw_is_range_overlap(hi, lo, 5720 + 10, 5260 - 10)?_TRUE:_FALSE; +} + +bool rtw_is_dfs_ch(u8 ch, u8 bw, u8 offset) +{ + u32 hi, lo; + + if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE) + return _FALSE; + + return rtw_is_dfs_range(hi, lo)?_TRUE:_FALSE; +} + +bool rtw_is_long_cac_range(u32 hi, u32 lo) +{ + return rtw_is_range_overlap(hi, lo, 5660 + 10, 5600 - 10)?_TRUE:_FALSE; +} + +bool rtw_is_long_cac_ch(u8 ch, u8 bw, u8 offset) +{ + u32 hi, lo; + + if (rtw_chbw_to_freq_range(ch, bw, offset, &hi, &lo) == _FALSE) + return _FALSE; + + return rtw_is_long_cac_range(hi, lo)?_TRUE:_FALSE; +} + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_security.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_security.c new file mode 100644 index 000000000..ed5e9aff5 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_security.c @@ -0,0 +1,3280 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_SECURITY_C_ + +#include + +static const char *_security_type_str[] = { + "N/A", + "WEP40", + "TKIP", + "TKIP_WM", + "AES", + "WEP104", + "SMS4", + "WEP_WPA", + "BIP", +}; + +const char *security_type_str(u8 value) +{ +#ifdef CONFIG_IEEE80211W + if (value <= _BIP_) +#else + if (value <= _WEP_WPA_MIXED_) +#endif + return _security_type_str[value]; + return NULL; +} + +#ifdef DBG_SW_SEC_CNT +#define WEP_SW_ENC_CNT_INC(sec, ra) \ + if (is_broadcast_mac_addr(ra)) \ + sec->wep_sw_enc_cnt_bc++; \ + else if (is_multicast_mac_addr(ra)) \ + sec->wep_sw_enc_cnt_mc++; \ + else \ + sec->wep_sw_enc_cnt_uc++; + +#define WEP_SW_DEC_CNT_INC(sec, ra) \ + if (is_broadcast_mac_addr(ra)) \ + sec->wep_sw_dec_cnt_bc++; \ + else if (is_multicast_mac_addr(ra)) \ + sec->wep_sw_dec_cnt_mc++; \ + else \ + sec->wep_sw_dec_cnt_uc++; + +#define TKIP_SW_ENC_CNT_INC(sec, ra) \ + if (is_broadcast_mac_addr(ra)) \ + sec->tkip_sw_enc_cnt_bc++; \ + else if (is_multicast_mac_addr(ra)) \ + sec->tkip_sw_enc_cnt_mc++; \ + else \ + sec->tkip_sw_enc_cnt_uc++; + +#define TKIP_SW_DEC_CNT_INC(sec, ra) \ + if (is_broadcast_mac_addr(ra)) \ + sec->tkip_sw_dec_cnt_bc++; \ + else if (is_multicast_mac_addr(ra)) \ + sec->tkip_sw_dec_cnt_mc++; \ + else \ + sec->tkip_sw_dec_cnt_uc++; + +#define AES_SW_ENC_CNT_INC(sec, ra) \ + if (is_broadcast_mac_addr(ra)) \ + sec->aes_sw_enc_cnt_bc++; \ + else if (is_multicast_mac_addr(ra)) \ + sec->aes_sw_enc_cnt_mc++; \ + else \ + sec->aes_sw_enc_cnt_uc++; + +#define AES_SW_DEC_CNT_INC(sec, ra) \ + if (is_broadcast_mac_addr(ra)) \ + sec->aes_sw_dec_cnt_bc++; \ + else if (is_multicast_mac_addr(ra)) \ + sec->aes_sw_dec_cnt_mc++; \ + else \ + sec->aes_sw_dec_cnt_uc++; +#else +#define WEP_SW_ENC_CNT_INC(sec, ra) +#define WEP_SW_DEC_CNT_INC(sec, ra) +#define TKIP_SW_ENC_CNT_INC(sec, ra) +#define TKIP_SW_DEC_CNT_INC(sec, ra) +#define AES_SW_ENC_CNT_INC(sec, ra) +#define AES_SW_DEC_CNT_INC(sec, ra) +#endif /* DBG_SW_SEC_CNT */ + +//=====WEP related===== + +#define CRC32_POLY 0x04c11db7 + +struct arc4context +{ + u32 x; + u32 y; + u8 state[256]; +}; + + +static void arcfour_init(struct arc4context *parc4ctx, u8 * key,u32 key_len) +{ + u32 t, u; + u32 keyindex; + u32 stateindex; + u8 * state; + u32 counter; +_func_enter_; + state = parc4ctx->state; + parc4ctx->x = 0; + parc4ctx->y = 0; + for (counter = 0; counter < 256; counter++) + state[counter] = (u8)counter; + keyindex = 0; + stateindex = 0; + for (counter = 0; counter < 256; counter++) + { + t = state[counter]; + stateindex = (stateindex + key[keyindex] + t) & 0xff; + u = state[stateindex]; + state[stateindex] = (u8)t; + state[counter] = (u8)u; + if (++keyindex >= key_len) + keyindex = 0; + } +_func_exit_; +} +static u32 arcfour_byte( struct arc4context *parc4ctx) +{ + u32 x; + u32 y; + u32 sx, sy; + u8 * state; +_func_enter_; + state = parc4ctx->state; + x = (parc4ctx->x + 1) & 0xff; + sx = state[x]; + y = (sx + parc4ctx->y) & 0xff; + sy = state[y]; + parc4ctx->x = x; + parc4ctx->y = y; + state[y] = (u8)sx; + state[x] = (u8)sy; +_func_exit_; + return state[(sx + sy) & 0xff]; +} + + +static void arcfour_encrypt( struct arc4context *parc4ctx, + u8 * dest, + u8 * src, + u32 len) +{ + u32 i; +_func_enter_; + for (i = 0; i < len; i++) + dest[i] = src[i] ^ (unsigned char)arcfour_byte(parc4ctx); +_func_exit_; +} + +static sint bcrc32initialized = 0; +static u32 crc32_table[256]; + + +static u8 crc32_reverseBit( u8 data) +{ + return( (u8)((data<<7)&0x80) | ((data<<5)&0x40) | ((data<<3)&0x20) | ((data<<1)&0x10) | ((data>>1)&0x08) | ((data>>3)&0x04) | ((data>>5)&0x02) | ((data>>7)&0x01) ); +} + +static void crc32_init(void) +{ +_func_enter_; + if (bcrc32initialized == 1) + goto exit; + else{ + sint i, j; + u32 c; + u8 *p=(u8 *)&c, *p1; + u8 k; + + c = 0x12340000; + + for (i = 0; i < 256; ++i) + { + k = crc32_reverseBit((u8)i); + for (c = ((u32)k) << 24, j = 8; j > 0; --j){ + c = c & 0x80000000 ? (c << 1) ^ CRC32_POLY : (c << 1); + } + p1 = (u8 *)&crc32_table[i]; + + p1[0] = crc32_reverseBit(p[3]); + p1[1] = crc32_reverseBit(p[2]); + p1[2] = crc32_reverseBit(p[1]); + p1[3] = crc32_reverseBit(p[0]); + } + bcrc32initialized= 1; + } +exit: +_func_exit_; +} + +static u32 getcrc32(u8 *buf, sint len) +{ + u8 *p; + u32 crc; +_func_enter_; + if (bcrc32initialized == 0) crc32_init(); + + crc = 0xffffffff; /* preload shift register, per CRC-32 spec */ + + for (p = buf; len > 0; ++p, --len) + { + crc = crc32_table[ (crc ^ *p) & 0xff] ^ (crc >> 8); + } +_func_exit_; + return ~crc; /* transmit complement, per CRC-32 spec */ +} + + +/* + Need to consider the fragment situation +*/ +void rtw_wep_encrypt(_adapter *padapter, u8 *pxmitframe) +{ // exclude ICV + + unsigned char crc[4]; + struct arc4context mycontext; + + sint curfragnum,length; + u32 keylength; + + u8 *pframe, *payload,*iv; //,*wepkey + u8 wepkey[16]; + u8 hw_hdr_offset=0; + struct pkt_attrib *pattrib = &((struct xmit_frame*)pxmitframe)->attrib; + struct security_priv *psecuritypriv=&padapter->securitypriv; + struct xmit_priv *pxmitpriv=&padapter->xmitpriv; + +_func_enter_; + + + if(((struct xmit_frame*)pxmitframe)->buf_addr==NULL) + return; + +#ifdef CONFIG_USB_TX_AGGREGATION + hw_hdr_offset = TXDESC_SIZE + + (((struct xmit_frame*)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ); +#else + #ifdef CONFIG_TX_EARLY_MODE + hw_hdr_offset = TXDESC_OFFSET+EARLY_MODE_INFO_SIZE; + #else + hw_hdr_offset = TXDESC_OFFSET; + #endif +#endif + + pframe = ((struct xmit_frame*)pxmitframe)->buf_addr + hw_hdr_offset; + + //start to encrypt each fragment + if((pattrib->encrypt==_WEP40_)||(pattrib->encrypt==_WEP104_)) + { + keylength=psecuritypriv->dot11DefKeylen[psecuritypriv->dot11PrivacyKeyIndex]; + + for(curfragnum=0;curfragnumnr_frags;curfragnum++) + { + iv=pframe+pattrib->hdrlen; + _rtw_memcpy(&wepkey[0], iv, 3); + _rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[psecuritypriv->dot11PrivacyKeyIndex].skey[0],keylength); + payload=pframe+pattrib->iv_len+pattrib->hdrlen; + + if((curfragnum+1)==pattrib->nr_frags) + { //the last fragment + + length=pattrib->last_txcmdsz-pattrib->hdrlen-pattrib->iv_len- pattrib->icv_len; + + *((u32 *)crc)=cpu_to_le32(getcrc32(payload,length)); + + arcfour_init(&mycontext, wepkey,3+keylength); + arcfour_encrypt(&mycontext, payload, payload, length); + arcfour_encrypt(&mycontext, payload+length, crc, 4); + + } + else + { + length=pxmitpriv->frag_len-pattrib->hdrlen-pattrib->iv_len-pattrib->icv_len ; + *((u32 *)crc)=cpu_to_le32(getcrc32(payload,length)); + arcfour_init(&mycontext, wepkey,3+keylength); + arcfour_encrypt(&mycontext, payload, payload, length); + arcfour_encrypt(&mycontext, payload+length, crc, 4); + + pframe+=pxmitpriv->frag_len; + pframe=(u8 *)RND4((SIZE_PTR)(pframe)); + + } + + } + + WEP_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra); + } + +_func_exit_; + +} + +void rtw_wep_decrypt(_adapter *padapter, u8 *precvframe) +{ + // exclude ICV + u8 crc[4]; + struct arc4context mycontext; + sint length; + u32 keylength; + u8 *pframe, *payload,*iv,wepkey[16]; + u8 keyindex; + struct rx_pkt_attrib *prxattrib = &(((union recv_frame*)precvframe)->u.hdr.attrib); + struct security_priv *psecuritypriv=&padapter->securitypriv; + +_func_enter_; + + pframe=(unsigned char *)((union recv_frame*)precvframe)->u.hdr.rx_data; + + //start to decrypt recvframe + if((prxattrib->encrypt==_WEP40_)||(prxattrib->encrypt==_WEP104_)) + { + iv=pframe+prxattrib->hdrlen; + //keyindex=(iv[3]&0x3); + keyindex = prxattrib->key_index; + keylength=psecuritypriv->dot11DefKeylen[keyindex]; + _rtw_memcpy(&wepkey[0], iv, 3); + //_rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[psecuritypriv->dot11PrivacyKeyIndex].skey[0],keylength); + _rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[keyindex].skey[0],keylength); + length= ((union recv_frame *)precvframe)->u.hdr.len-prxattrib->hdrlen-prxattrib->iv_len; + + payload=pframe+prxattrib->iv_len+prxattrib->hdrlen; + + //decrypt payload include icv + arcfour_init(&mycontext, wepkey,3+keylength); + arcfour_encrypt(&mycontext, payload, payload, length); + + //calculate icv and compare the icv + *((u32 *)crc)=le32_to_cpu(getcrc32(payload,length-4)); + + if(crc[3]!=payload[length-1] || crc[2]!=payload[length-2] || crc[1]!=payload[length-3] || crc[0]!=payload[length-4]) + { + RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_wep_decrypt:icv error crc[3](%x)!=payload[length-1](%x) || crc[2](%x)!=payload[length-2](%x) || crc[1](%x)!=payload[length-3](%x) || crc[0](%x)!=payload[length-4](%x)\n", + crc[3],payload[length-1],crc[2],payload[length-2],crc[1],payload[length-3],crc[0],payload[length-4])); + } + + WEP_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra); + } + +_func_exit_; + + return; + +} + +//3 =====TKIP related===== + +static u32 secmicgetuint32( u8 * p ) +// Convert from Byte[] to Us4Byte32 in a portable way +{ + s32 i; + u32 res = 0; +_func_enter_; + for( i=0; i<4; i++ ) + { + res |= ((u32)(*p++)) << (8*i); + } +_func_exit_; + return res; +} + +static void secmicputuint32( u8 * p, u32 val ) +// Convert from Us4Byte32 to Byte[] in a portable way +{ + long i; +_func_enter_; + for( i=0; i<4; i++ ) + { + *p++ = (u8) (val & 0xff); + val >>= 8; + } +_func_exit_; +} + +static void secmicclear(struct mic_data *pmicdata) +{ +// Reset the state to the empty message. +_func_enter_; + pmicdata->L = pmicdata->K0; + pmicdata->R = pmicdata->K1; + pmicdata->nBytesInM = 0; + pmicdata->M = 0; +_func_exit_; +} + +void rtw_secmicsetkey(struct mic_data *pmicdata, u8 * key ) +{ + // Set the key +_func_enter_; + pmicdata->K0 = secmicgetuint32( key ); + pmicdata->K1 = secmicgetuint32( key + 4 ); + // and reset the message + secmicclear(pmicdata); +_func_exit_; +} + +void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b ) +{ +_func_enter_; + // Append the byte to our word-sized buffer + pmicdata->M |= ((unsigned long)b) << (8*pmicdata->nBytesInM); + pmicdata->nBytesInM++; + // Process the word if it is full. + if( pmicdata->nBytesInM >= 4 ) + { + pmicdata->L ^= pmicdata->M; + pmicdata->R ^= ROL32( pmicdata->L, 17 ); + pmicdata->L += pmicdata->R; + pmicdata->R ^= ((pmicdata->L & 0xff00ff00) >> 8) | ((pmicdata->L & 0x00ff00ff) << 8); + pmicdata->L += pmicdata->R; + pmicdata->R ^= ROL32( pmicdata->L, 3 ); + pmicdata->L += pmicdata->R; + pmicdata->R ^= ROR32( pmicdata->L, 2 ); + pmicdata->L += pmicdata->R; + // Clear the buffer + pmicdata->M = 0; + pmicdata->nBytesInM = 0; + } +_func_exit_; +} + +void rtw_secmicappend(struct mic_data *pmicdata, u8 * src, u32 nbytes ) +{ +_func_enter_; + // This is simple + while( nbytes > 0 ) + { + rtw_secmicappendbyte(pmicdata, *src++ ); + nbytes--; + } +_func_exit_; +} + +void rtw_secgetmic(struct mic_data *pmicdata, u8 * dst ) +{ +_func_enter_; + // Append the minimum padding + rtw_secmicappendbyte(pmicdata, 0x5a ); + rtw_secmicappendbyte(pmicdata, 0 ); + rtw_secmicappendbyte(pmicdata, 0 ); + rtw_secmicappendbyte(pmicdata, 0 ); + rtw_secmicappendbyte(pmicdata, 0 ); + // and then zeroes until the length is a multiple of 4 + while( pmicdata->nBytesInM != 0 ) + { + rtw_secmicappendbyte(pmicdata, 0 ); + } + // The appendByte function has already computed the result. + secmicputuint32( dst, pmicdata->L ); + secmicputuint32( dst+4, pmicdata->R ); + // Reset to the empty message. + secmicclear(pmicdata); +_func_exit_; +} + + +void rtw_seccalctkipmic(u8 * key,u8 *header,u8 *data,u32 data_len,u8 *mic_code, u8 pri) +{ + + struct mic_data micdata; + u8 priority[4]={0x0,0x0,0x0,0x0}; +_func_enter_; + rtw_secmicsetkey(&micdata, key); + priority[0]=pri; + + /* Michael MIC pseudo header: DA, SA, 3 x 0, Priority */ + if(header[1]&1){ //ToDS==1 + rtw_secmicappend(&micdata, &header[16], 6); //DA + if(header[1]&2) //From Ds==1 + rtw_secmicappend(&micdata, &header[24], 6); + else + rtw_secmicappend(&micdata, &header[10], 6); + } + else{ //ToDS==0 + rtw_secmicappend(&micdata, &header[4], 6); //DA + if(header[1]&2) //From Ds==1 + rtw_secmicappend(&micdata, &header[16], 6); + else + rtw_secmicappend(&micdata, &header[10], 6); + + } + rtw_secmicappend(&micdata, &priority[0], 4); + + + rtw_secmicappend(&micdata, data, data_len); + + rtw_secgetmic(&micdata,mic_code); +_func_exit_; +} + + + + +/* macros for extraction/creation of unsigned char/unsigned short values */ +#define RotR1(v16) ((((v16) >> 1) & 0x7FFF) ^ (((v16) & 1) << 15)) +#define Lo8(v16) ((u8)( (v16) & 0x00FF)) +#define Hi8(v16) ((u8)(((v16) >> 8) & 0x00FF)) +#define Lo16(v32) ((u16)( (v32) & 0xFFFF)) +#define Hi16(v32) ((u16)(((v32) >>16) & 0xFFFF)) +#define Mk16(hi,lo) ((lo) ^ (((u16)(hi)) << 8)) + +/* select the Nth 16-bit word of the temporal key unsigned char array TK[] */ +#define TK16(N) Mk16(tk[2*(N)+1],tk[2*(N)]) + +/* S-box lookup: 16 bits --> 16 bits */ +#define _S_(v16) (Sbox1[0][Lo8(v16)] ^ Sbox1[1][Hi8(v16)]) + +/* fixed algorithm "parameters" */ +#define PHASE1_LOOP_CNT 8 /* this needs to be "big enough" */ +#define TA_SIZE 6 /* 48-bit transmitter address */ +#define TK_SIZE 16 /* 128-bit temporal key */ +#define P1K_SIZE 10 /* 80-bit Phase1 key */ +#define RC4_KEY_SIZE 16 /* 128-bit RC4KEY (104 bits unknown) */ + + +/* 2-unsigned char by 2-unsigned char subset of the full AES S-box table */ +static const unsigned short Sbox1[2][256]= /* Sbox for hash (can be in ROM) */ +{ { + 0xC6A5,0xF884,0xEE99,0xF68D,0xFF0D,0xD6BD,0xDEB1,0x9154, + 0x6050,0x0203,0xCEA9,0x567D,0xE719,0xB562,0x4DE6,0xEC9A, + 0x8F45,0x1F9D,0x8940,0xFA87,0xEF15,0xB2EB,0x8EC9,0xFB0B, + 0x41EC,0xB367,0x5FFD,0x45EA,0x23BF,0x53F7,0xE496,0x9B5B, + 0x75C2,0xE11C,0x3DAE,0x4C6A,0x6C5A,0x7E41,0xF502,0x834F, + 0x685C,0x51F4,0xD134,0xF908,0xE293,0xAB73,0x6253,0x2A3F, + 0x080C,0x9552,0x4665,0x9D5E,0x3028,0x37A1,0x0A0F,0x2FB5, + 0x0E09,0x2436,0x1B9B,0xDF3D,0xCD26,0x4E69,0x7FCD,0xEA9F, + 0x121B,0x1D9E,0x5874,0x342E,0x362D,0xDCB2,0xB4EE,0x5BFB, + 0xA4F6,0x764D,0xB761,0x7DCE,0x527B,0xDD3E,0x5E71,0x1397, + 0xA6F5,0xB968,0x0000,0xC12C,0x4060,0xE31F,0x79C8,0xB6ED, + 0xD4BE,0x8D46,0x67D9,0x724B,0x94DE,0x98D4,0xB0E8,0x854A, + 0xBB6B,0xC52A,0x4FE5,0xED16,0x86C5,0x9AD7,0x6655,0x1194, + 0x8ACF,0xE910,0x0406,0xFE81,0xA0F0,0x7844,0x25BA,0x4BE3, + 0xA2F3,0x5DFE,0x80C0,0x058A,0x3FAD,0x21BC,0x7048,0xF104, + 0x63DF,0x77C1,0xAF75,0x4263,0x2030,0xE51A,0xFD0E,0xBF6D, + 0x814C,0x1814,0x2635,0xC32F,0xBEE1,0x35A2,0x88CC,0x2E39, + 0x9357,0x55F2,0xFC82,0x7A47,0xC8AC,0xBAE7,0x322B,0xE695, + 0xC0A0,0x1998,0x9ED1,0xA37F,0x4466,0x547E,0x3BAB,0x0B83, + 0x8CCA,0xC729,0x6BD3,0x283C,0xA779,0xBCE2,0x161D,0xAD76, + 0xDB3B,0x6456,0x744E,0x141E,0x92DB,0x0C0A,0x486C,0xB8E4, + 0x9F5D,0xBD6E,0x43EF,0xC4A6,0x39A8,0x31A4,0xD337,0xF28B, + 0xD532,0x8B43,0x6E59,0xDAB7,0x018C,0xB164,0x9CD2,0x49E0, + 0xD8B4,0xACFA,0xF307,0xCF25,0xCAAF,0xF48E,0x47E9,0x1018, + 0x6FD5,0xF088,0x4A6F,0x5C72,0x3824,0x57F1,0x73C7,0x9751, + 0xCB23,0xA17C,0xE89C,0x3E21,0x96DD,0x61DC,0x0D86,0x0F85, + 0xE090,0x7C42,0x71C4,0xCCAA,0x90D8,0x0605,0xF701,0x1C12, + 0xC2A3,0x6A5F,0xAEF9,0x69D0,0x1791,0x9958,0x3A27,0x27B9, + 0xD938,0xEB13,0x2BB3,0x2233,0xD2BB,0xA970,0x0789,0x33A7, + 0x2DB6,0x3C22,0x1592,0xC920,0x8749,0xAAFF,0x5078,0xA57A, + 0x038F,0x59F8,0x0980,0x1A17,0x65DA,0xD731,0x84C6,0xD0B8, + 0x82C3,0x29B0,0x5A77,0x1E11,0x7BCB,0xA8FC,0x6DD6,0x2C3A, + }, + + + { /* second half of table is unsigned char-reversed version of first! */ + 0xA5C6,0x84F8,0x99EE,0x8DF6,0x0DFF,0xBDD6,0xB1DE,0x5491, + 0x5060,0x0302,0xA9CE,0x7D56,0x19E7,0x62B5,0xE64D,0x9AEC, + 0x458F,0x9D1F,0x4089,0x87FA,0x15EF,0xEBB2,0xC98E,0x0BFB, + 0xEC41,0x67B3,0xFD5F,0xEA45,0xBF23,0xF753,0x96E4,0x5B9B, + 0xC275,0x1CE1,0xAE3D,0x6A4C,0x5A6C,0x417E,0x02F5,0x4F83, + 0x5C68,0xF451,0x34D1,0x08F9,0x93E2,0x73AB,0x5362,0x3F2A, + 0x0C08,0x5295,0x6546,0x5E9D,0x2830,0xA137,0x0F0A,0xB52F, + 0x090E,0x3624,0x9B1B,0x3DDF,0x26CD,0x694E,0xCD7F,0x9FEA, + 0x1B12,0x9E1D,0x7458,0x2E34,0x2D36,0xB2DC,0xEEB4,0xFB5B, + 0xF6A4,0x4D76,0x61B7,0xCE7D,0x7B52,0x3EDD,0x715E,0x9713, + 0xF5A6,0x68B9,0x0000,0x2CC1,0x6040,0x1FE3,0xC879,0xEDB6, + 0xBED4,0x468D,0xD967,0x4B72,0xDE94,0xD498,0xE8B0,0x4A85, + 0x6BBB,0x2AC5,0xE54F,0x16ED,0xC586,0xD79A,0x5566,0x9411, + 0xCF8A,0x10E9,0x0604,0x81FE,0xF0A0,0x4478,0xBA25,0xE34B, + 0xF3A2,0xFE5D,0xC080,0x8A05,0xAD3F,0xBC21,0x4870,0x04F1, + 0xDF63,0xC177,0x75AF,0x6342,0x3020,0x1AE5,0x0EFD,0x6DBF, + 0x4C81,0x1418,0x3526,0x2FC3,0xE1BE,0xA235,0xCC88,0x392E, + 0x5793,0xF255,0x82FC,0x477A,0xACC8,0xE7BA,0x2B32,0x95E6, + 0xA0C0,0x9819,0xD19E,0x7FA3,0x6644,0x7E54,0xAB3B,0x830B, + 0xCA8C,0x29C7,0xD36B,0x3C28,0x79A7,0xE2BC,0x1D16,0x76AD, + 0x3BDB,0x5664,0x4E74,0x1E14,0xDB92,0x0A0C,0x6C48,0xE4B8, + 0x5D9F,0x6EBD,0xEF43,0xA6C4,0xA839,0xA431,0x37D3,0x8BF2, + 0x32D5,0x438B,0x596E,0xB7DA,0x8C01,0x64B1,0xD29C,0xE049, + 0xB4D8,0xFAAC,0x07F3,0x25CF,0xAFCA,0x8EF4,0xE947,0x1810, + 0xD56F,0x88F0,0x6F4A,0x725C,0x2438,0xF157,0xC773,0x5197, + 0x23CB,0x7CA1,0x9CE8,0x213E,0xDD96,0xDC61,0x860D,0x850F, + 0x90E0,0x427C,0xC471,0xAACC,0xD890,0x0506,0x01F7,0x121C, + 0xA3C2,0x5F6A,0xF9AE,0xD069,0x9117,0x5899,0x273A,0xB927, + 0x38D9,0x13EB,0xB32B,0x3322,0xBBD2,0x70A9,0x8907,0xA733, + 0xB62D,0x223C,0x9215,0x20C9,0x4987,0xFFAA,0x7850,0x7AA5, + 0x8F03,0xF859,0x8009,0x171A,0xDA65,0x31D7,0xC684,0xB8D0, + 0xC382,0xB029,0x775A,0x111E,0xCB7B,0xFCA8,0xD66D,0x3A2C, + } +}; + + /* +********************************************************************** +* Routine: Phase 1 -- generate P1K, given TA, TK, IV32 +* +* Inputs: +* tk[] = temporal key [128 bits] +* ta[] = transmitter's MAC address [ 48 bits] +* iv32 = upper 32 bits of IV [ 32 bits] +* Output: +* p1k[] = Phase 1 key [ 80 bits] +* +* Note: +* This function only needs to be called every 2**16 packets, +* although in theory it could be called every packet. +* +********************************************************************** +*/ +static void phase1(u16 *p1k,const u8 *tk,const u8 *ta,u32 iv32) +{ + sint i; +_func_enter_; + /* Initialize the 80 bits of P1K[] from IV32 and TA[0..5] */ + p1k[0] = Lo16(iv32); + p1k[1] = Hi16(iv32); + p1k[2] = Mk16(ta[1],ta[0]); /* use TA[] as little-endian */ + p1k[3] = Mk16(ta[3],ta[2]); + p1k[4] = Mk16(ta[5],ta[4]); + + /* Now compute an unbalanced Feistel cipher with 80-bit block */ + /* size on the 80-bit block P1K[], using the 128-bit key TK[] */ + for (i=0; i < PHASE1_LOOP_CNT ;i++) + { /* Each add operation here is mod 2**16 */ + p1k[0] += _S_(p1k[4] ^ TK16((i&1)+0)); + p1k[1] += _S_(p1k[0] ^ TK16((i&1)+2)); + p1k[2] += _S_(p1k[1] ^ TK16((i&1)+4)); + p1k[3] += _S_(p1k[2] ^ TK16((i&1)+6)); + p1k[4] += _S_(p1k[3] ^ TK16((i&1)+0)); + p1k[4] += (unsigned short)i; /* avoid "slide attacks" */ + } +_func_exit_; +} + + +/* +********************************************************************** +* Routine: Phase 2 -- generate RC4KEY, given TK, P1K, IV16 +* +* Inputs: +* tk[] = Temporal key [128 bits] +* p1k[] = Phase 1 output key [ 80 bits] +* iv16 = low 16 bits of IV counter [ 16 bits] +* Output: +* rc4key[] = the key used to encrypt the packet [128 bits] +* +* Note: +* The value {TA,IV32,IV16} for Phase1/Phase2 must be unique +* across all packets using the same key TK value. Then, for a +* given value of TK[], this TKIP48 construction guarantees that +* the final RC4KEY value is unique across all packets. +* +* Suggested implementation optimization: if PPK[] is "overlaid" +* appropriately on RC4KEY[], there is no need for the final +* for loop below that copies the PPK[] result into RC4KEY[]. +* +********************************************************************** +*/ +static void phase2(u8 *rc4key,const u8 *tk,const u16 *p1k,u16 iv16) +{ + sint i; + u16 PPK[6]; /* temporary key for mixing */ +_func_enter_; + /* Note: all adds in the PPK[] equations below are mod 2**16 */ + for (i=0;i<5;i++) PPK[i]=p1k[i]; /* first, copy P1K to PPK */ + PPK[5] = p1k[4] +iv16; /* next, add in IV16 */ + + /* Bijective non-linear mixing of the 96 bits of PPK[0..5] */ + PPK[0] += _S_(PPK[5] ^ TK16(0)); /* Mix key in each "round" */ + PPK[1] += _S_(PPK[0] ^ TK16(1)); + PPK[2] += _S_(PPK[1] ^ TK16(2)); + PPK[3] += _S_(PPK[2] ^ TK16(3)); + PPK[4] += _S_(PPK[3] ^ TK16(4)); + PPK[5] += _S_(PPK[4] ^ TK16(5)); /* Total # S-box lookups == 6 */ + + /* Final sweep: bijective, "linear". Rotates kill LSB correlations */ + PPK[0] += RotR1(PPK[5] ^ TK16(6)); + PPK[1] += RotR1(PPK[0] ^ TK16(7)); /* Use all of TK[] in Phase2 */ + PPK[2] += RotR1(PPK[1]); + PPK[3] += RotR1(PPK[2]); + PPK[4] += RotR1(PPK[3]); + PPK[5] += RotR1(PPK[4]); + /* Note: At this point, for a given key TK[0..15], the 96-bit output */ + /* value PPK[0..5] is guaranteed to be unique, as a function */ + /* of the 96-bit "input" value {TA,IV32,IV16}. That is, P1K */ + /* is now a keyed permutation of {TA,IV32,IV16}. */ + + /* Set RC4KEY[0..3], which includes "cleartext" portion of RC4 key */ + rc4key[0] = Hi8(iv16); /* RC4KEY[0..2] is the WEP IV */ + rc4key[1] =(Hi8(iv16) | 0x20) & 0x7F; /* Help avoid weak (FMS) keys */ + rc4key[2] = Lo8(iv16); + rc4key[3] = Lo8((PPK[5] ^ TK16(0)) >> 1); + + + /* Copy 96 bits of PPK[0..5] to RC4KEY[4..15] (little-endian) */ + for (i=0;i<6;i++) + { + rc4key[4+2*i] = Lo8(PPK[i]); + rc4key[5+2*i] = Hi8(PPK[i]); + } +_func_exit_; +} + + +//The hlen isn't include the IV +u32 rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe) +{ // exclude ICV + u16 pnl; + u32 pnh; + u8 rc4key[16]; + u8 ttkey[16]; + u8 crc[4]; + u8 hw_hdr_offset = 0; + struct arc4context mycontext; + sint curfragnum,length; + u32 prwskeylen; + + u8 *pframe, *payload,*iv,*prwskey; + union pn48 dot11txpn; + //struct sta_info *stainfo; + struct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib; + struct security_priv *psecuritypriv=&padapter->securitypriv; + struct xmit_priv *pxmitpriv=&padapter->xmitpriv; + u32 res=_SUCCESS; +_func_enter_; + + if(((struct xmit_frame*)pxmitframe)->buf_addr==NULL) + return _FAIL; + +#ifdef CONFIG_USB_TX_AGGREGATION + hw_hdr_offset = TXDESC_SIZE + + (((struct xmit_frame*)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ); +#else + #ifdef CONFIG_TX_EARLY_MODE + hw_hdr_offset = TXDESC_OFFSET+EARLY_MODE_INFO_SIZE; + #else + hw_hdr_offset = TXDESC_OFFSET; + #endif +#endif + + pframe = ((struct xmit_frame*)pxmitframe)->buf_addr + hw_hdr_offset; + //4 start to encrypt each fragment + if(pattrib->encrypt==_TKIP_){ + +/* + if(pattrib->psta) + { + stainfo = pattrib->psta; + } + else + { + DBG_871X("%s, call rtw_get_stainfo()\n", __func__); + stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] ); + } +*/ + //if (stainfo!=NULL) + { +/* + if(!(stainfo->state &_FW_LINKED)) + { + DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, stainfo->state); + return _FAIL; + } +*/ + RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_tkip_encrypt: stainfo!=NULL!!!\n")); + + if(IS_MCAST(pattrib->ra)) + { + prwskey=psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; + } + else + { + //prwskey=&stainfo->dot118021x_UncstKey.skey[0]; + prwskey=pattrib->dot118021x_UncstKey.skey; + } + + prwskeylen=16; + + for(curfragnum=0;curfragnumnr_frags;curfragnum++){ + iv=pframe+pattrib->hdrlen; + payload=pframe+pattrib->iv_len+pattrib->hdrlen; + + GET_TKIP_PN(iv, dot11txpn); + + pnl=(u16)(dot11txpn.val); + pnh=(u32)(dot11txpn.val>>16); + + phase1((u16 *)&ttkey[0],prwskey,&pattrib->ta[0],pnh); + + phase2(&rc4key[0],prwskey,(u16 *)&ttkey[0],pnl); + + if((curfragnum+1)==pattrib->nr_frags){ //4 the last fragment + length=pattrib->last_txcmdsz-pattrib->hdrlen-pattrib->iv_len- pattrib->icv_len; + RT_TRACE(_module_rtl871x_security_c_,_drv_info_,("pattrib->iv_len =%x, pattrib->icv_len =%x\n", pattrib->iv_len,pattrib->icv_len)); + *((u32 *)crc)=cpu_to_le32(getcrc32(payload,length));/* modified by Amy*/ + + arcfour_init(&mycontext, rc4key,16); + arcfour_encrypt(&mycontext, payload, payload, length); + arcfour_encrypt(&mycontext, payload+length, crc, 4); + + } + else{ + length=pxmitpriv->frag_len-pattrib->hdrlen-pattrib->iv_len-pattrib->icv_len ; + *((u32 *)crc)=cpu_to_le32(getcrc32(payload,length));/* modified by Amy*/ + arcfour_init(&mycontext,rc4key,16); + arcfour_encrypt(&mycontext, payload, payload, length); + arcfour_encrypt(&mycontext, payload+length, crc, 4); + + pframe+=pxmitpriv->frag_len; + pframe=(u8 *)RND4((SIZE_PTR)(pframe)); + + } + } + + TKIP_SW_ENC_CNT_INC(psecuritypriv,pattrib->ra); + } +/* + else{ + RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_tkip_encrypt: stainfo==NULL!!!\n")); + DBG_871X("%s, psta==NUL\n", __func__); + res=_FAIL; + } +*/ + + } +_func_exit_; + return res; + +} + + +//The hlen isn't include the IV +u32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe) +{ // exclude ICV + u16 pnl; + u32 pnh; + u8 rc4key[16]; + u8 ttkey[16]; + u8 crc[4]; + struct arc4context mycontext; + sint length; + u32 prwskeylen; + + u8 *pframe, *payload,*iv,*prwskey; + union pn48 dot11txpn; + struct sta_info *stainfo; + struct rx_pkt_attrib *prxattrib = &((union recv_frame *)precvframe)->u.hdr.attrib; + struct security_priv *psecuritypriv=&padapter->securitypriv; +// struct recv_priv *precvpriv=&padapter->recvpriv; + u32 res=_SUCCESS; + +_func_enter_; + + pframe=(unsigned char *)((union recv_frame*)precvframe)->u.hdr.rx_data; + + //4 start to decrypt recvframe + if(prxattrib->encrypt==_TKIP_){ + + stainfo=rtw_get_stainfo(&padapter->stapriv ,&prxattrib->ta[0] ); + if (stainfo!=NULL){ + + if(IS_MCAST(prxattrib->ra)) + { + static u32 start = 0; + static u32 no_gkey_bc_cnt = 0; + static u32 no_gkey_mc_cnt = 0; + + if(psecuritypriv->binstallGrpkey==_FALSE) + { + res=_FAIL; + + if (start == 0) + start = rtw_get_current_time(); + + if (is_broadcast_mac_addr(prxattrib->ra)) + no_gkey_bc_cnt++; + else + no_gkey_mc_cnt++; + + if (rtw_get_passing_time_ms(start) > 1000) { + if (no_gkey_bc_cnt || no_gkey_mc_cnt) { + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n", + FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt); + } + start = rtw_get_current_time(); + no_gkey_bc_cnt = 0; + no_gkey_mc_cnt = 0; + } + goto exit; + } + + if (no_gkey_bc_cnt || no_gkey_mc_cnt) { + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" gkey installed. no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n", + FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt); + } + start = 0; + no_gkey_bc_cnt = 0; + no_gkey_mc_cnt = 0; + + //DBG_871X("rx bc/mc packets, to perform sw rtw_tkip_decrypt\n"); + //prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; + prwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey; + prwskeylen=16; + } + else + { + prwskey=&stainfo->dot118021x_UncstKey.skey[0]; + prwskeylen=16; + } + + iv=pframe+prxattrib->hdrlen; + payload=pframe+prxattrib->iv_len+prxattrib->hdrlen; + length= ((union recv_frame *)precvframe)->u.hdr.len-prxattrib->hdrlen-prxattrib->iv_len; + + GET_TKIP_PN(iv, dot11txpn); + + pnl=(u16)(dot11txpn.val); + pnh=(u32)(dot11txpn.val>>16); + + phase1((u16 *)&ttkey[0],prwskey,&prxattrib->ta[0],pnh); + phase2(&rc4key[0],prwskey,(unsigned short *)&ttkey[0],pnl); + + //4 decrypt payload include icv + + arcfour_init(&mycontext, rc4key,16); + arcfour_encrypt(&mycontext, payload, payload, length); + + *((u32 *)crc)=le32_to_cpu(getcrc32(payload,length-4)); + + if(crc[3]!=payload[length-1] || crc[2]!=payload[length-2] || crc[1]!=payload[length-3] || crc[0]!=payload[length-4]) + { + RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_wep_decrypt:icv error crc[3](%x)!=payload[length-1](%x) || crc[2](%x)!=payload[length-2](%x) || crc[1](%x)!=payload[length-3](%x) || crc[0](%x)!=payload[length-4](%x)\n", + crc[3],payload[length-1],crc[2],payload[length-2],crc[1],payload[length-3],crc[0],payload[length-4])); + res=_FAIL; + } + + TKIP_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra); + } + else{ + RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_tkip_decrypt: stainfo==NULL!!!\n")); + res=_FAIL; + } + + } +_func_exit_; +exit: + return res; + +} + + +//3 =====AES related===== + + + +#define MAX_MSG_SIZE 2048 +/*****************************/ +/******** SBOX Table *********/ +/*****************************/ + + static u8 sbox_table[256] = + { + 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, + 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76, + 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, + 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, + 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, + 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, + 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, + 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75, + 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, + 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84, + 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, + 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf, + 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, + 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, + 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, + 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, + 0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, + 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73, + 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, + 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb, + 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, + 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, + 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, + 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, + 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, + 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, + 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, + 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e, + 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, + 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, + 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, + 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16 + }; + +/*****************************/ +/**** Function Prototypes ****/ +/*****************************/ + +static void bitwise_xor(u8 *ina, u8 *inb, u8 *out); +static void construct_mic_iv( + u8 *mic_header1, + sint qc_exists, + sint a4_exists, + u8 *mpdu, + uint payload_length, + u8 * pn_vector, + uint frtype);// add for CONFIG_IEEE80211W, none 11w also can use +static void construct_mic_header1( + u8 *mic_header1, + sint header_length, + u8 *mpdu, + uint frtype);// add for CONFIG_IEEE80211W, none 11w also can use +static void construct_mic_header2( + u8 *mic_header2, + u8 *mpdu, + sint a4_exists, + sint qc_exists); +static void construct_ctr_preload( + u8 *ctr_preload, + sint a4_exists, + sint qc_exists, + u8 *mpdu, + u8 *pn_vector, + sint c, + uint frtype);// add for CONFIG_IEEE80211W, none 11w also can use +static void xor_128(u8 *a, u8 *b, u8 *out); +static void xor_32(u8 *a, u8 *b, u8 *out); +static u8 sbox(u8 a); +static void next_key(u8 *key, sint round); +static void byte_sub(u8 *in, u8 *out); +static void shift_row(u8 *in, u8 *out); +static void mix_column(u8 *in, u8 *out); +#ifndef PLATFORM_FREEBSD +static void add_round_key( u8 *shiftrow_in, + u8 *mcol_in, + u8 *block_in, + sint round, + u8 *out); +#endif //PLATFORM_FREEBSD +static void aes128k128d(u8 *key, u8 *data, u8 *ciphertext); + + +/****************************************/ +/* aes128k128d() */ +/* Performs a 128 bit AES encrypt with */ +/* 128 bit data. */ +/****************************************/ +static void xor_128(u8 *a, u8 *b, u8 *out) +{ + sint i; +_func_enter_; + for (i=0;i<16; i++) + { + out[i] = a[i] ^ b[i]; + } +_func_exit_; +} + + +static void xor_32(u8 *a, u8 *b, u8 *out) +{ + sint i; +_func_enter_; + for (i=0;i<4; i++) + { + out[i] = a[i] ^ b[i]; + } +_func_exit_; +} + + +static u8 sbox(u8 a) +{ + return sbox_table[(sint)a]; +} + + +static void next_key(u8 *key, sint round) +{ + u8 rcon; + u8 sbox_key[4]; + u8 rcon_table[12] = + { + 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, + 0x1b, 0x36, 0x36, 0x36 + }; +_func_enter_; + sbox_key[0] = sbox(key[13]); + sbox_key[1] = sbox(key[14]); + sbox_key[2] = sbox(key[15]); + sbox_key[3] = sbox(key[12]); + + rcon = rcon_table[round]; + + xor_32(&key[0], sbox_key, &key[0]); + key[0] = key[0] ^ rcon; + + xor_32(&key[4], &key[0], &key[4]); + xor_32(&key[8], &key[4], &key[8]); + xor_32(&key[12], &key[8], &key[12]); +_func_exit_; +} + + +static void byte_sub(u8 *in, u8 *out) +{ + sint i; +_func_enter_; + for (i=0; i< 16; i++) + { + out[i] = sbox(in[i]); + } +_func_exit_; +} + + +static void shift_row(u8 *in, u8 *out) +{ +_func_enter_; + out[0] = in[0]; + out[1] = in[5]; + out[2] = in[10]; + out[3] = in[15]; + out[4] = in[4]; + out[5] = in[9]; + out[6] = in[14]; + out[7] = in[3]; + out[8] = in[8]; + out[9] = in[13]; + out[10] = in[2]; + out[11] = in[7]; + out[12] = in[12]; + out[13] = in[1]; + out[14] = in[6]; + out[15] = in[11]; +_func_exit_; +} + + +static void mix_column(u8 *in, u8 *out) +{ + sint i; + u8 add1b[4]; + u8 add1bf7[4]; + u8 rotl[4]; + u8 swap_halfs[4]; + u8 andf7[4]; + u8 rotr[4]; + u8 temp[4]; + u8 tempb[4]; +_func_enter_; + for (i=0 ; i<4; i++) + { + if ((in[i] & 0x80)== 0x80) + add1b[i] = 0x1b; + else + add1b[i] = 0x00; + } + + swap_halfs[0] = in[2]; /* Swap halfs */ + swap_halfs[1] = in[3]; + swap_halfs[2] = in[0]; + swap_halfs[3] = in[1]; + + rotl[0] = in[3]; /* Rotate left 8 bits */ + rotl[1] = in[0]; + rotl[2] = in[1]; + rotl[3] = in[2]; + + andf7[0] = in[0] & 0x7f; + andf7[1] = in[1] & 0x7f; + andf7[2] = in[2] & 0x7f; + andf7[3] = in[3] & 0x7f; + + for (i = 3; i>0; i--) /* logical shift left 1 bit */ + { + andf7[i] = andf7[i] << 1; + if ((andf7[i-1] & 0x80) == 0x80) + { + andf7[i] = (andf7[i] | 0x01); + } + } + andf7[0] = andf7[0] << 1; + andf7[0] = andf7[0] & 0xfe; + + xor_32(add1b, andf7, add1bf7); + + xor_32(in, add1bf7, rotr); + + temp[0] = rotr[0]; /* Rotate right 8 bits */ + rotr[0] = rotr[1]; + rotr[1] = rotr[2]; + rotr[2] = rotr[3]; + rotr[3] = temp[0]; + + xor_32(add1bf7, rotr, temp); + xor_32(swap_halfs, rotl,tempb); + xor_32(temp, tempb, out); +_func_exit_; +} + + +static void aes128k128d(u8 *key, u8 *data, u8 *ciphertext) +{ + sint round; + sint i; + u8 intermediatea[16]; + u8 intermediateb[16]; + u8 round_key[16]; +_func_enter_; + for(i=0; i<16; i++) round_key[i] = key[i]; + + for (round = 0; round < 11; round++) + { + if (round == 0) + { + xor_128(round_key, data, ciphertext); + next_key(round_key, round); + } + else if (round == 10) + { + byte_sub(ciphertext, intermediatea); + shift_row(intermediatea, intermediateb); + xor_128(intermediateb, round_key, ciphertext); + } + else /* 1 - 9 */ + { + byte_sub(ciphertext, intermediatea); + shift_row(intermediatea, intermediateb); + mix_column(&intermediateb[0], &intermediatea[0]); + mix_column(&intermediateb[4], &intermediatea[4]); + mix_column(&intermediateb[8], &intermediatea[8]); + mix_column(&intermediateb[12], &intermediatea[12]); + xor_128(intermediatea, round_key, ciphertext); + next_key(round_key, round); + } + } +_func_exit_; +} + + +/************************************************/ +/* construct_mic_iv() */ +/* Builds the MIC IV from header fields and PN */ +/* Baron think the function is construct CCM */ +/* nonce */ +/************************************************/ +static void construct_mic_iv( + u8 *mic_iv, + sint qc_exists, + sint a4_exists, + u8 *mpdu, + uint payload_length, + u8 *pn_vector, + uint frtype// add for CONFIG_IEEE80211W, none 11w also can use + ) +{ + sint i; +_func_enter_; + mic_iv[0] = 0x59; + if (qc_exists && a4_exists) mic_iv[1] = mpdu[30] & 0x0f; /* QoS_TC */ + if (qc_exists && !a4_exists) mic_iv[1] = mpdu[24] & 0x0f; /* mute bits 7-4 */ + if (!qc_exists) mic_iv[1] = 0x00; +#ifdef CONFIG_IEEE80211W + //802.11w management frame should set management bit(4) + if(frtype == WIFI_MGT_TYPE) + mic_iv[1] |= BIT(4); +#endif //CONFIG_IEEE80211W + for (i = 2; i < 8; i++) + mic_iv[i] = mpdu[i + 8]; /* mic_iv[2:7] = A2[0:5] = mpdu[10:15] */ + #ifdef CONSISTENT_PN_ORDER + for (i = 8; i < 14; i++) + mic_iv[i] = pn_vector[i - 8]; /* mic_iv[8:13] = PN[0:5] */ + #else + for (i = 8; i < 14; i++) + mic_iv[i] = pn_vector[13 - i]; /* mic_iv[8:13] = PN[5:0] */ + #endif + mic_iv[14] = (unsigned char) (payload_length / 256); + mic_iv[15] = (unsigned char) (payload_length % 256); +_func_exit_; +} + + +/************************************************/ +/* construct_mic_header1() */ +/* Builds the first MIC header block from */ +/* header fields. */ +/* Build AAD SC,A1,A2 */ +/************************************************/ +static void construct_mic_header1( + u8 *mic_header1, + sint header_length, + u8 *mpdu, + uint frtype// add for CONFIG_IEEE80211W, none 11w also can use + ) +{ +_func_enter_; + mic_header1[0] = (u8)((header_length - 2) / 256); + mic_header1[1] = (u8)((header_length - 2) % 256); +#ifdef CONFIG_IEEE80211W + //802.11w management frame don't AND subtype bits 4,5,6 of frame control field + if(frtype == WIFI_MGT_TYPE) + mic_header1[2] = mpdu[0]; + else +#endif //CONFIG_IEEE80211W + mic_header1[2] = mpdu[0] & 0xcf; /* Mute CF poll & CF ack bits */ + + mic_header1[3] = mpdu[1] & 0xc7; /* Mute retry, more data and pwr mgt bits */ + mic_header1[4] = mpdu[4]; /* A1 */ + mic_header1[5] = mpdu[5]; + mic_header1[6] = mpdu[6]; + mic_header1[7] = mpdu[7]; + mic_header1[8] = mpdu[8]; + mic_header1[9] = mpdu[9]; + mic_header1[10] = mpdu[10]; /* A2 */ + mic_header1[11] = mpdu[11]; + mic_header1[12] = mpdu[12]; + mic_header1[13] = mpdu[13]; + mic_header1[14] = mpdu[14]; + mic_header1[15] = mpdu[15]; +_func_exit_; +} + + +/************************************************/ +/* construct_mic_header2() */ +/* Builds the last MIC header block from */ +/* header fields. */ +/************************************************/ +static void construct_mic_header2( + u8 *mic_header2, + u8 *mpdu, + sint a4_exists, + sint qc_exists + ) +{ + sint i; +_func_enter_; + for (i = 0; i<16; i++) mic_header2[i]=0x00; + + mic_header2[0] = mpdu[16]; /* A3 */ + mic_header2[1] = mpdu[17]; + mic_header2[2] = mpdu[18]; + mic_header2[3] = mpdu[19]; + mic_header2[4] = mpdu[20]; + mic_header2[5] = mpdu[21]; + + //mic_header2[6] = mpdu[22] & 0xf0; /* SC */ + mic_header2[6] = 0x00; + mic_header2[7] = 0x00; /* mpdu[23]; */ + + + if (!qc_exists && a4_exists) + { + for (i=0;i<6;i++) mic_header2[8+i] = mpdu[24+i]; /* A4 */ + + } + + if (qc_exists && !a4_exists) + { + mic_header2[8] = mpdu[24] & 0x0f; /* mute bits 15 - 4 */ + mic_header2[9] = mpdu[25] & 0x00; + } + + if (qc_exists && a4_exists) + { + for (i=0;i<6;i++) mic_header2[8+i] = mpdu[24+i]; /* A4 */ + + mic_header2[14] = mpdu[30] & 0x0f; + mic_header2[15] = mpdu[31] & 0x00; + } + +_func_exit_; +} + + +/************************************************/ +/* construct_mic_header2() */ +/* Builds the last MIC header block from */ +/* header fields. */ +/* Baron think the function is construct CCM */ +/* nonce */ +/************************************************/ +static void construct_ctr_preload( + u8 *ctr_preload, + sint a4_exists, + sint qc_exists, + u8 *mpdu, + u8 *pn_vector, + sint c, + uint frtype // add for CONFIG_IEEE80211W, none 11w also can use + ) +{ + sint i = 0; +_func_enter_; + for (i=0; i<16; i++) ctr_preload[i] = 0x00; + i = 0; + + ctr_preload[0] = 0x01; /* flag */ + if (qc_exists && a4_exists) + ctr_preload[1] = mpdu[30] & 0x0f; /* QoC_Control */ + if (qc_exists && !a4_exists) + ctr_preload[1] = mpdu[24] & 0x0f; +#ifdef CONFIG_IEEE80211W + //802.11w management frame should set management bit(4) + if(frtype == WIFI_MGT_TYPE) + ctr_preload[1] |= BIT(4); +#endif //CONFIG_IEEE80211W + for (i = 2; i < 8; i++) + ctr_preload[i] = mpdu[i + 8]; /* ctr_preload[2:7] = A2[0:5] = mpdu[10:15] */ + #ifdef CONSISTENT_PN_ORDER + for (i = 8; i < 14; i++) + ctr_preload[i] = pn_vector[i - 8]; /* ctr_preload[8:13] = PN[0:5] */ + #else + for (i = 8; i < 14; i++) + ctr_preload[i] = pn_vector[13 - i]; /* ctr_preload[8:13] = PN[5:0] */ + #endif + ctr_preload[14] = (unsigned char) (c / 256); /* Ctr */ + ctr_preload[15] = (unsigned char) (c % 256); +_func_exit_; +} + + +/************************************/ +/* bitwise_xor() */ +/* A 128 bit, bitwise exclusive or */ +/************************************/ +static void bitwise_xor(u8 *ina, u8 *inb, u8 *out) +{ + sint i; +_func_enter_; + for (i=0; i<16; i++) + { + out[i] = ina[i] ^ inb[i]; + } +_func_exit_; +} + + +static sint aes_cipher(u8 *key, uint hdrlen, + u8 *pframe, uint plen) +{ +// /*static*/ unsigned char message[MAX_MSG_SIZE]; + uint qc_exists, a4_exists, i, j, payload_remainder, + num_blocks, payload_index; + + u8 pn_vector[6]; + u8 mic_iv[16]; + u8 mic_header1[16]; + u8 mic_header2[16]; + u8 ctr_preload[16]; + + /* Intermediate Buffers */ + u8 chain_buffer[16]; + u8 aes_out[16]; + u8 padded_buffer[16]; + u8 mic[8]; +// uint offset = 0; + uint frtype = GetFrameType(pframe); + uint frsubtype = GetFrameSubType(pframe); + +_func_enter_; + frsubtype=frsubtype>>4; + + + _rtw_memset((void *)mic_iv, 0, 16); + _rtw_memset((void *)mic_header1, 0, 16); + _rtw_memset((void *)mic_header2, 0, 16); + _rtw_memset((void *)ctr_preload, 0, 16); + _rtw_memset((void *)chain_buffer, 0, 16); + _rtw_memset((void *)aes_out, 0, 16); + _rtw_memset((void *)padded_buffer, 0, 16); + + if ((hdrlen == WLAN_HDR_A3_LEN )||(hdrlen == WLAN_HDR_A3_QOS_LEN)) + a4_exists = 0; + else + a4_exists = 1; + + if ( + ((frtype|frsubtype) == WIFI_DATA_CFACK) || + ((frtype|frsubtype) == WIFI_DATA_CFPOLL)|| + ((frtype|frsubtype) == WIFI_DATA_CFACKPOLL)) + { + qc_exists = 1; + if(hdrlen != WLAN_HDR_A3_QOS_LEN){ + + hdrlen += 2; + } + } + // add for CONFIG_IEEE80211W, none 11w also can use + else if ((frtype == WIFI_DATA) && + ((frsubtype == 0x08) || + (frsubtype == 0x09)|| + (frsubtype == 0x0a)|| + (frsubtype == 0x0b))) + { + if(hdrlen != WLAN_HDR_A3_QOS_LEN){ + + hdrlen += 2; + } + qc_exists = 1; + } + else + qc_exists = 0; + + pn_vector[0]=pframe[hdrlen]; + pn_vector[1]=pframe[hdrlen+1]; + pn_vector[2]=pframe[hdrlen+4]; + pn_vector[3]=pframe[hdrlen+5]; + pn_vector[4]=pframe[hdrlen+6]; + pn_vector[5]=pframe[hdrlen+7]; + + construct_mic_iv( + mic_iv, + qc_exists, + a4_exists, + pframe, //message, + plen, + pn_vector, + frtype // add for CONFIG_IEEE80211W, none 11w also can use + ); + + construct_mic_header1( + mic_header1, + hdrlen, + pframe, //message + frtype // add for CONFIG_IEEE80211W, none 11w also can use + ); + construct_mic_header2( + mic_header2, + pframe, //message, + a4_exists, + qc_exists + ); + + + payload_remainder = plen % 16; + num_blocks = plen / 16; + + /* Find start of payload */ + payload_index = (hdrlen + 8); + + /* Calculate MIC */ + aes128k128d(key, mic_iv, aes_out); + bitwise_xor(aes_out, mic_header1, chain_buffer); + aes128k128d(key, chain_buffer, aes_out); + bitwise_xor(aes_out, mic_header2, chain_buffer); + aes128k128d(key, chain_buffer, aes_out); + + for (i = 0; i < num_blocks; i++) + { + bitwise_xor(aes_out, &pframe[payload_index], chain_buffer);//bitwise_xor(aes_out, &message[payload_index], chain_buffer); + + payload_index += 16; + aes128k128d(key, chain_buffer, aes_out); + } + + /* Add on the final payload block if it needs padding */ + if (payload_remainder > 0) + { + for (j = 0; j < 16; j++) padded_buffer[j] = 0x00; + for (j = 0; j < payload_remainder; j++) + { + padded_buffer[j] = pframe[payload_index++];//padded_buffer[j] = message[payload_index++]; + } + bitwise_xor(aes_out, padded_buffer, chain_buffer); + aes128k128d(key, chain_buffer, aes_out); + + } + + for (j = 0 ; j < 8; j++) mic[j] = aes_out[j]; + + /* Insert MIC into payload */ + for (j = 0; j < 8; j++) + pframe[payload_index+j] = mic[j]; //message[payload_index+j] = mic[j]; + + payload_index = hdrlen + 8; + for (i=0; i< num_blocks; i++) + { + construct_ctr_preload( + ctr_preload, + a4_exists, + qc_exists, + pframe, //message, + pn_vector, + i+1, + frtype); // add for CONFIG_IEEE80211W, none 11w also can use + aes128k128d(key, ctr_preload, aes_out); + bitwise_xor(aes_out, &pframe[payload_index], chain_buffer);//bitwise_xor(aes_out, &message[payload_index], chain_buffer); + for (j=0; j<16;j++) pframe[payload_index++] = chain_buffer[j];//for (j=0; j<16;j++) message[payload_index++] = chain_buffer[j]; + } + + if (payload_remainder > 0) /* If there is a short final block, then pad it,*/ + { /* encrypt it and copy the unpadded part back */ + construct_ctr_preload( + ctr_preload, + a4_exists, + qc_exists, + pframe, //message, + pn_vector, + num_blocks+1, + frtype); // add for CONFIG_IEEE80211W, none 11w also can use + + for (j = 0; j < 16; j++) padded_buffer[j] = 0x00; + for (j = 0; j < payload_remainder; j++) + { + padded_buffer[j] = pframe[payload_index+j];//padded_buffer[j] = message[payload_index+j]; + } + aes128k128d(key, ctr_preload, aes_out); + bitwise_xor(aes_out, padded_buffer, chain_buffer); + for (j=0; jattrib; + struct security_priv *psecuritypriv=&padapter->securitypriv; + struct xmit_priv *pxmitpriv=&padapter->xmitpriv; + +// uint offset = 0; + u32 res=_SUCCESS; +_func_enter_; + + if(((struct xmit_frame*)pxmitframe)->buf_addr==NULL) + return _FAIL; + +#ifdef CONFIG_USB_TX_AGGREGATION + hw_hdr_offset = TXDESC_SIZE + + (((struct xmit_frame*)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ); +#else + #ifdef CONFIG_TX_EARLY_MODE + hw_hdr_offset = TXDESC_OFFSET+EARLY_MODE_INFO_SIZE; + #else + hw_hdr_offset = TXDESC_OFFSET; + #endif +#endif + + pframe = ((struct xmit_frame*)pxmitframe)->buf_addr + hw_hdr_offset; + + //4 start to encrypt each fragment + if((pattrib->encrypt==_AES_)){ +/* + if(pattrib->psta) + { + stainfo = pattrib->psta; + } + else + { + DBG_871X("%s, call rtw_get_stainfo()\n", __func__); + stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] ); + } +*/ + //if (stainfo!=NULL) + { +/* + if(!(stainfo->state &_FW_LINKED)) + { + DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, stainfo->state); + return _FAIL; + } +*/ + RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_aes_encrypt: stainfo!=NULL!!!\n")); + + if(IS_MCAST(pattrib->ra)) + { + prwskey=psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; + } + else + { + //prwskey=&stainfo->dot118021x_UncstKey.skey[0]; + prwskey=pattrib->dot118021x_UncstKey.skey; + } + +#ifdef CONFIG_TDLS + { + /* Swencryption */ + struct sta_info *ptdls_sta; + ptdls_sta=rtw_get_stainfo(&padapter->stapriv ,&pattrib->dst[0] ); + if((ptdls_sta != NULL) && (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) ) + { + DBG_871X("[%s] for tdls link\n", __FUNCTION__); + prwskey=&ptdls_sta->tpk.tk[0]; + } + } +#endif //CONFIG_TDLS + + prwskeylen=16; + + for(curfragnum=0;curfragnumnr_frags;curfragnum++){ + + if((curfragnum+1)==pattrib->nr_frags){ //4 the last fragment + length=pattrib->last_txcmdsz-pattrib->hdrlen-pattrib->iv_len- pattrib->icv_len; + + aes_cipher(prwskey,pattrib->hdrlen,pframe, length); + } + else{ + length=pxmitpriv->frag_len-pattrib->hdrlen-pattrib->iv_len-pattrib->icv_len ; + + aes_cipher(prwskey,pattrib->hdrlen,pframe, length); + pframe+=pxmitpriv->frag_len; + pframe=(u8*)RND4((SIZE_PTR)(pframe)); + + } + } + + AES_SW_ENC_CNT_INC(psecuritypriv, pattrib->ra); + } +/* + else{ + RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_aes_encrypt: stainfo==NULL!!!\n")); + DBG_871X("%s, psta==NUL\n", __func__); + res=_FAIL; + } +*/ + } + + + +_func_exit_; + return res; +} + +static sint aes_decipher(u8 *key, uint hdrlen, + u8 *pframe, uint plen) +{ + static u8 message[MAX_MSG_SIZE]; + uint qc_exists, a4_exists, i, j, payload_remainder, + num_blocks, payload_index; + sint res = _SUCCESS; + u8 pn_vector[6]; + u8 mic_iv[16]; + u8 mic_header1[16]; + u8 mic_header2[16]; + u8 ctr_preload[16]; + + /* Intermediate Buffers */ + u8 chain_buffer[16]; + u8 aes_out[16]; + u8 padded_buffer[16]; + u8 mic[8]; + + +// uint offset = 0; + uint frtype = GetFrameType(pframe); + uint frsubtype = GetFrameSubType(pframe); +_func_enter_; + frsubtype=frsubtype>>4; + + + _rtw_memset((void *)mic_iv, 0, 16); + _rtw_memset((void *)mic_header1, 0, 16); + _rtw_memset((void *)mic_header2, 0, 16); + _rtw_memset((void *)ctr_preload, 0, 16); + _rtw_memset((void *)chain_buffer, 0, 16); + _rtw_memset((void *)aes_out, 0, 16); + _rtw_memset((void *)padded_buffer, 0, 16); + + //start to decrypt the payload + + num_blocks = (plen-8) / 16; //(plen including LLC, payload_length and mic ) + + payload_remainder = (plen-8) % 16; + + pn_vector[0] = pframe[hdrlen]; + pn_vector[1] = pframe[hdrlen+1]; + pn_vector[2] = pframe[hdrlen+4]; + pn_vector[3] = pframe[hdrlen+5]; + pn_vector[4] = pframe[hdrlen+6]; + pn_vector[5] = pframe[hdrlen+7]; + + if ((hdrlen == WLAN_HDR_A3_LEN )||(hdrlen == WLAN_HDR_A3_QOS_LEN)) + a4_exists = 0; + else + a4_exists = 1; + + if ( + ((frtype|frsubtype) == WIFI_DATA_CFACK) || + ((frtype|frsubtype) == WIFI_DATA_CFPOLL)|| + ((frtype|frsubtype) == WIFI_DATA_CFACKPOLL)) + { + qc_exists = 1; + if(hdrlen != WLAN_HDR_A3_QOS_LEN){ + + hdrlen += 2; + } + }//only for data packet . add for CONFIG_IEEE80211W, none 11w also can use + else if ((frtype == WIFI_DATA) && + ((frsubtype == 0x08) || + (frsubtype == 0x09)|| + (frsubtype == 0x0a)|| + (frsubtype == 0x0b))) + { + if(hdrlen != WLAN_HDR_A3_QOS_LEN){ + + hdrlen += 2; + } + qc_exists = 1; + } + else + qc_exists = 0; + + + // now, decrypt pframe with hdrlen offset and plen long + + payload_index = hdrlen + 8; // 8 is for extiv + + for (i=0; i< num_blocks; i++) + { + construct_ctr_preload( + ctr_preload, + a4_exists, + qc_exists, + pframe, + pn_vector, + i+1, + frtype // add for CONFIG_IEEE80211W, none 11w also can use + ); + + aes128k128d(key, ctr_preload, aes_out); + bitwise_xor(aes_out, &pframe[payload_index], chain_buffer); + + for (j=0; j<16;j++) pframe[payload_index++] = chain_buffer[j]; + } + + if (payload_remainder > 0) /* If there is a short final block, then pad it,*/ + { /* encrypt it and copy the unpadded part back */ + construct_ctr_preload( + ctr_preload, + a4_exists, + qc_exists, + pframe, + pn_vector, + num_blocks+1, + frtype // add for CONFIG_IEEE80211W, none 11w also can use + ); + + for (j = 0; j < 16; j++) padded_buffer[j] = 0x00; + for (j = 0; j < payload_remainder; j++) + { + padded_buffer[j] = pframe[payload_index+j]; + } + aes128k128d(key, ctr_preload, aes_out); + bitwise_xor(aes_out, padded_buffer, chain_buffer); + for (j=0; j 0) + { + for (j = 0; j < 16; j++) padded_buffer[j] = 0x00; + for (j = 0; j < payload_remainder; j++) + { + padded_buffer[j] = message[payload_index++]; + } + bitwise_xor(aes_out, padded_buffer, chain_buffer); + aes128k128d(key, chain_buffer, aes_out); + + } + + for (j = 0 ; j < 8; j++) mic[j] = aes_out[j]; + + /* Insert MIC into payload */ + for (j = 0; j < 8; j++) + message[payload_index+j] = mic[j]; + + payload_index = hdrlen + 8; + for (i=0; i< num_blocks; i++) + { + construct_ctr_preload( + ctr_preload, + a4_exists, + qc_exists, + message, + pn_vector, + i+1, + frtype); // add for CONFIG_IEEE80211W, none 11w also can use + aes128k128d(key, ctr_preload, aes_out); + bitwise_xor(aes_out, &message[payload_index], chain_buffer); + for (j=0; j<16;j++) message[payload_index++] = chain_buffer[j]; + } + + if (payload_remainder > 0) /* If there is a short final block, then pad it,*/ + { /* encrypt it and copy the unpadded part back */ + construct_ctr_preload( + ctr_preload, + a4_exists, + qc_exists, + message, + pn_vector, + num_blocks+1, + frtype); // add for CONFIG_IEEE80211W, none 11w also can use + + for (j = 0; j < 16; j++) padded_buffer[j] = 0x00; + for (j = 0; j < payload_remainder; j++) + { + padded_buffer[j] = message[payload_index+j]; + } + aes128k128d(key, ctr_preload, aes_out); + bitwise_xor(aes_out, padded_buffer, chain_buffer); + for (j=0; ju.hdr.attrib; + struct security_priv *psecuritypriv=&padapter->securitypriv; +// struct recv_priv *precvpriv=&padapter->recvpriv; + u32 res=_SUCCESS; +_func_enter_; + pframe=(unsigned char *)((union recv_frame*)precvframe)->u.hdr.rx_data; + //4 start to encrypt each fragment + if((prxattrib->encrypt==_AES_)){ + + stainfo=rtw_get_stainfo(&padapter->stapriv ,&prxattrib->ta[0] ); + if (stainfo!=NULL){ + RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_aes_decrypt: stainfo!=NULL!!!\n")); + + if(IS_MCAST(prxattrib->ra)) + { + static u32 start = 0; + static u32 no_gkey_bc_cnt = 0; + static u32 no_gkey_mc_cnt = 0; + + //DBG_871X("rx bc/mc packets, to perform sw rtw_aes_decrypt\n"); + //prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; + if(psecuritypriv->binstallGrpkey==_FALSE) + { + res=_FAIL; + + if (start == 0) + start = rtw_get_current_time(); + + if (is_broadcast_mac_addr(prxattrib->ra)) + no_gkey_bc_cnt++; + else + no_gkey_mc_cnt++; + + if (rtw_get_passing_time_ms(start) > 1000) { + if (no_gkey_bc_cnt || no_gkey_mc_cnt) { + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n", + FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt); + } + start = rtw_get_current_time(); + no_gkey_bc_cnt = 0; + no_gkey_mc_cnt = 0; + } + + goto exit; + } + + if (no_gkey_bc_cnt || no_gkey_mc_cnt) { + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" gkey installed. no_gkey_bc_cnt:%u, no_gkey_mc_cnt:%u\n", + FUNC_ADPT_ARG(padapter), no_gkey_bc_cnt, no_gkey_mc_cnt); + } + start = 0; + no_gkey_bc_cnt = 0; + no_gkey_mc_cnt = 0; + + prwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey; + if(psecuritypriv->dot118021XGrpKeyid != prxattrib->key_index) + { + DBG_871X("not match packet_index=%d, install_index=%d \n" + , prxattrib->key_index, psecuritypriv->dot118021XGrpKeyid); + res=_FAIL; + goto exit; + } + } + else + { + prwskey=&stainfo->dot118021x_UncstKey.skey[0]; + } + + length= ((union recv_frame *)precvframe)->u.hdr.len-prxattrib->hdrlen-prxattrib->iv_len; + /*// add for CONFIG_IEEE80211W, debug + if(0) + printk("@@@@@@@@@@@@@@@@@@ length=%d, prxattrib->hdrlen=%d, prxattrib->pkt_len=%d \n" + , length, prxattrib->hdrlen, prxattrib->pkt_len); + if(0) + { + int no; + //test print PSK + printk("PSK key below:\n"); + for(no=0;no<16;no++) + printk(" %02x ", prwskey[no]); + printk("\n"); + } + if(0) + { + int no; + //test print PSK + printk("frame:\n"); + for(no=0;nopkt_len;no++) + printk(" %02x ", pframe[no]); + printk("\n"); + }*/ + + res= aes_decipher(prwskey,prxattrib->hdrlen,pframe, length); + + AES_SW_DEC_CNT_INC(psecuritypriv, prxattrib->ra); + } + else{ + RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_aes_decrypt: stainfo==NULL!!!\n")); + res=_FAIL; + } + + } +_func_exit_; +exit: + return res; +} + +#ifdef CONFIG_IEEE80211W +u32 rtw_BIP_verify(_adapter *padapter, u8 *precvframe) +{ + struct rx_pkt_attrib *pattrib = &((union recv_frame *)precvframe)->u.hdr.attrib; + u8 *pframe; + u8 *BIP_AAD, *p; + u32 res=_FAIL; + uint len, ori_len; + struct rtw_ieee80211_hdr *pwlanhdr; + u8 mic[16]; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + ori_len = pattrib->pkt_len-WLAN_HDR_A3_LEN+BIP_AAD_SIZE; + BIP_AAD = rtw_zmalloc(ori_len); + + if(BIP_AAD == NULL) + { + DBG_871X("BIP AAD allocate fail\n"); + return _FAIL; + } + //PKT start + pframe=(unsigned char *)((union recv_frame*)precvframe)->u.hdr.rx_data; + //mapping to wlan header + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + //save the frame body + MME + _rtw_memcpy(BIP_AAD+BIP_AAD_SIZE, pframe+WLAN_HDR_A3_LEN, pattrib->pkt_len-WLAN_HDR_A3_LEN); + //find MME IE pointer + p = rtw_get_ie(BIP_AAD+BIP_AAD_SIZE, _MME_IE_, &len, pattrib->pkt_len-WLAN_HDR_A3_LEN); + //Baron + if(p) + { + u16 keyid=0; + u64 temp_ipn=0; + //save packet number + _rtw_memcpy(&temp_ipn, p+4, 6); + temp_ipn = le64_to_cpu(temp_ipn); + //BIP packet number should bigger than previous BIP packet + if (temp_ipn < pmlmeext->mgnt_80211w_IPN_rx) { + DBG_871X("replay BIP packet\n"); + goto BIP_exit; + } + //copy key index + _rtw_memcpy(&keyid, p+2, 2); + keyid = le16_to_cpu(keyid); + if(keyid != padapter->securitypriv.dot11wBIPKeyid) + { + DBG_871X("BIP key index error!\n"); + goto BIP_exit; + } + //clear the MIC field of MME to zero + _rtw_memset(p+2+len-8, 0, 8); + + //conscruct AAD, copy frame control field + _rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2); + ClearRetry(BIP_AAD); + ClearPwrMgt(BIP_AAD); + ClearMData(BIP_AAD); + //conscruct AAD, copy address 1 to address 3 + _rtw_memcpy(BIP_AAD+2, pwlanhdr->addr1, 18); + + if(omac1_aes_128(padapter->securitypriv.dot11wBIPKey[padapter->securitypriv.dot11wBIPKeyid].skey + , BIP_AAD, ori_len, mic)) + goto BIP_exit; + + /*//management packet content + { + int pp; + DBG_871X("pkt: "); + for(pp=0;pp< pattrib->pkt_len; pp++) + printk(" %02x ", pframe[pp]); + DBG_871X("\n"); + //BIP AAD + management frame body + MME(MIC is zero) + DBG_871X("AAD+PKT: "); + for(pp=0;pp< ori_len; pp++) + DBG_871X(" %02x ", BIP_AAD[pp]); + DBG_871X("\n"); + //show the MIC result + DBG_871X("mic: "); + for(pp=0;pp<16; pp++) + DBG_871X(" %02x ", mic[pp]); + DBG_871X("\n"); + } + */ + //MIC field should be last 8 bytes of packet (packet without FCS) + if(_rtw_memcmp(mic, pframe+pattrib->pkt_len-8, 8)) + { + pmlmeext->mgnt_80211w_IPN_rx = temp_ipn; + res=_SUCCESS; + } + else + DBG_871X("BIP MIC error!\n"); + + } + else + res = RTW_RX_HANDLED; +BIP_exit: + + rtw_mfree(BIP_AAD, ori_len); + return res; +} +#endif //CONFIG_IEEE80211W + +#ifndef PLATFORM_FREEBSD +/* compress 512-bits */ +static int sha256_compress(struct rtw_sha256_state *md, unsigned char *buf) +{ + u32 S[8], W[64], t0, t1; + u32 t; + int i; + + /* copy state into S */ + for (i = 0; i < 8; i++) { + S[i] = md->state[i]; + } + + /* copy the state into 512-bits into W[0..15] */ + for (i = 0; i < 16; i++) + W[i] = WPA_GET_BE32(buf + (4 * i)); + + /* fill W[16..63] */ + for (i = 16; i < 64; i++) { + W[i] = Gamma1(W[i - 2]) + W[i - 7] + Gamma0(W[i - 15]) + + W[i - 16]; + } + + /* Compress */ +#define RND(a,b,c,d,e,f,g,h,i) \ + t0 = h + Sigma1(e) + Ch(e, f, g) + K[i] + W[i]; \ + t1 = Sigma0(a) + Maj(a, b, c); \ + d += t0; \ + h = t0 + t1; + + for (i = 0; i < 64; ++i) { + RND(S[0], S[1], S[2], S[3], S[4], S[5], S[6], S[7], i); + t = S[7]; S[7] = S[6]; S[6] = S[5]; S[5] = S[4]; + S[4] = S[3]; S[3] = S[2]; S[2] = S[1]; S[1] = S[0]; S[0] = t; + } + + /* feedback */ + for (i = 0; i < 8; i++) { + md->state[i] = md->state[i] + S[i]; + } + return 0; +} + +/* Initialize the hash state */ +static void sha256_init(struct rtw_sha256_state *md) +{ + md->curlen = 0; + md->length = 0; + md->state[0] = 0x6A09E667UL; + md->state[1] = 0xBB67AE85UL; + md->state[2] = 0x3C6EF372UL; + md->state[3] = 0xA54FF53AUL; + md->state[4] = 0x510E527FUL; + md->state[5] = 0x9B05688CUL; + md->state[6] = 0x1F83D9ABUL; + md->state[7] = 0x5BE0CD19UL; +} + +/** + Process a block of memory though the hash + @param md The hash state + @param in The data to hash + @param inlen The length of the data (octets) + @return CRYPT_OK if successful +*/ +static int sha256_process(struct rtw_sha256_state *md, unsigned char *in, + unsigned long inlen) +{ + unsigned long n; +#define block_size 64 + + if (md->curlen > sizeof(md->buf)) + return -1; + + while (inlen > 0) { + if (md->curlen == 0 && inlen >= block_size) { + if (sha256_compress(md, (unsigned char *) in) < 0) + return -1; + md->length += block_size * 8; + in += block_size; + inlen -= block_size; + } else { + n = MIN(inlen, (block_size - md->curlen)); + _rtw_memcpy(md->buf + md->curlen, in, n); + md->curlen += n; + in += n; + inlen -= n; + if (md->curlen == block_size) { + if (sha256_compress(md, md->buf) < 0) + return -1; + md->length += 8 * block_size; + md->curlen = 0; + } + } + } + + return 0; +} + + +/** + Terminate the hash to get the digest + @param md The hash state + @param out [out] The destination of the hash (32 bytes) + @return CRYPT_OK if successful +*/ +static int sha256_done(struct rtw_sha256_state *md, unsigned char *out) +{ + int i; + + if (md->curlen >= sizeof(md->buf)) + return -1; + + /* increase the length of the message */ + md->length += md->curlen * 8; + + /* append the '1' bit */ + md->buf[md->curlen++] = (unsigned char) 0x80; + + /* if the length is currently above 56 bytes we append zeros + * then compress. Then we can fall back to padding zeros and length + * encoding like normal. + */ + if (md->curlen > 56) { + while (md->curlen < 64) { + md->buf[md->curlen++] = (unsigned char) 0; + } + sha256_compress(md, md->buf); + md->curlen = 0; + } + + /* pad upto 56 bytes of zeroes */ + while (md->curlen < 56) { + md->buf[md->curlen++] = (unsigned char) 0; + } + + /* store length */ + WPA_PUT_BE64(md->buf + 56, md->length); + sha256_compress(md, md->buf); + + /* copy output */ + for (i = 0; i < 8; i++) + WPA_PUT_BE32(out + (4 * i), md->state[i]); + + return 0; +} + +/** + * sha256_vector - SHA256 hash for data vector + * @num_elem: Number of elements in the data vector + * @addr: Pointers to the data areas + * @len: Lengths of the data blocks + * @mac: Buffer for the hash + * Returns: 0 on success, -1 of failure + */ +static int sha256_vector(size_t num_elem, u8 *addr[], size_t *len, + u8 *mac) +{ + struct rtw_sha256_state ctx; + size_t i; + + sha256_init(&ctx); + for (i = 0; i < num_elem; i++) + if (sha256_process(&ctx, addr[i], len[i])) + return -1; + if (sha256_done(&ctx, mac)) + return -1; + return 0; +} + +static u8 os_strlen(const char *s) +{ + const char *p = s; + while (*p) + p++; + return p - s; +} + +static int os_memcmp(void *s1, void *s2, u8 n) +{ + unsigned char *p1 = s1, *p2 = s2; + + if (n == 0) + return 0; + + while (*p1 == *p2) { + p1++; + p2++; + n--; + if (n == 0) + return 0; + } + + return *p1 - *p2; +} + +/** + * hmac_sha256_vector - HMAC-SHA256 over data vector (RFC 2104) + * @key: Key for HMAC operations + * @key_len: Length of the key in bytes + * @num_elem: Number of elements in the data vector + * @addr: Pointers to the data areas + * @len: Lengths of the data blocks + * @mac: Buffer for the hash (32 bytes) + */ +static void hmac_sha256_vector(u8 *key, size_t key_len, size_t num_elem, + u8 *addr[], size_t *len, u8 *mac) +{ + unsigned char k_pad[64]; /* padding - key XORd with ipad/opad */ + unsigned char tk[32]; + u8 *_addr[6]; + size_t _len[6], i; + + if (num_elem > 5) { + /* + * Fixed limit on the number of fragments to avoid having to + * allocate memory (which could fail). + */ + return; + } + + /* if key is longer than 64 bytes reset it to key = SHA256(key) */ + if (key_len > 64) { + sha256_vector(1, &key, &key_len, tk); + key = tk; + key_len = 32; + } + + /* the HMAC_SHA256 transform looks like: + * + * SHA256(K XOR opad, SHA256(K XOR ipad, text)) + * + * where K is an n byte key + * ipad is the byte 0x36 repeated 64 times + * opad is the byte 0x5c repeated 64 times + * and text is the data being protected */ + + /* start out by storing key in ipad */ + _rtw_memset(k_pad, 0, sizeof(k_pad)); + _rtw_memcpy(k_pad, key, key_len); + /* XOR key with ipad values */ + for (i = 0; i < 64; i++) + k_pad[i] ^= 0x36; + + /* perform inner SHA256 */ + _addr[0] = k_pad; + _len[0] = 64; + for (i = 0; i < num_elem; i++) { + _addr[i + 1] = addr[i]; + _len[i + 1] = len[i]; + } + sha256_vector(1 + num_elem, _addr, _len, mac); + + _rtw_memset(k_pad, 0, sizeof(k_pad)); + _rtw_memcpy(k_pad, key, key_len); + /* XOR key with opad values */ + for (i = 0; i < 64; i++) + k_pad[i] ^= 0x5c; + + /* perform outer SHA256 */ + _addr[0] = k_pad; + _len[0] = 64; + _addr[1] = mac; + _len[1] = 32; + sha256_vector(2, _addr, _len, mac); +} +#endif //PLATFORM_FREEBSD +/** + * sha256_prf - SHA256-based Pseudo-Random Function (IEEE 802.11r, 8.5.1.5.2) + * @key: Key for PRF + * @key_len: Length of the key in bytes + * @label: A unique label for each purpose of the PRF + * @data: Extra data to bind into the key + * @data_len: Length of the data + * @buf: Buffer for the generated pseudo-random key + * @buf_len: Number of bytes of key to generate + * + * This function is used to derive new, cryptographically separate keys from a + * given key. + */ +#ifndef PLATFORM_FREEBSD //Baron +static void sha256_prf(u8 *key, size_t key_len, char *label, + u8 *data, size_t data_len, u8 *buf, size_t buf_len) +{ + u16 counter = 1; + size_t pos, plen; + u8 hash[SHA256_MAC_LEN]; + u8 *addr[4]; + size_t len[4]; + u8 counter_le[2], length_le[2]; + + addr[0] = counter_le; + len[0] = 2; + addr[1] = (u8 *) label; + len[1] = os_strlen(label); + addr[2] = data; + len[2] = data_len; + addr[3] = length_le; + len[3] = sizeof(length_le); + + WPA_PUT_LE16(length_le, buf_len * 8); + pos = 0; + while (pos < buf_len) { + plen = buf_len - pos; + WPA_PUT_LE16(counter_le, counter); + if (plen >= SHA256_MAC_LEN) { + hmac_sha256_vector(key, key_len, 4, addr, len, + &buf[pos]); + pos += SHA256_MAC_LEN; + } else { + hmac_sha256_vector(key, key_len, 4, addr, len, hash); + _rtw_memcpy(&buf[pos], hash, plen); + break; + } + counter++; + } +} +#endif //PLATFORM_FREEBSD Baron + +/* AES tables*/ +const u32 Te0[256] = { + 0xc66363a5U, 0xf87c7c84U, 0xee777799U, 0xf67b7b8dU, + 0xfff2f20dU, 0xd66b6bbdU, 0xde6f6fb1U, 0x91c5c554U, + 0x60303050U, 0x02010103U, 0xce6767a9U, 0x562b2b7dU, + 0xe7fefe19U, 0xb5d7d762U, 0x4dababe6U, 0xec76769aU, + 0x8fcaca45U, 0x1f82829dU, 0x89c9c940U, 0xfa7d7d87U, + 0xeffafa15U, 0xb25959ebU, 0x8e4747c9U, 0xfbf0f00bU, + 0x41adadecU, 0xb3d4d467U, 0x5fa2a2fdU, 0x45afafeaU, + 0x239c9cbfU, 0x53a4a4f7U, 0xe4727296U, 0x9bc0c05bU, + 0x75b7b7c2U, 0xe1fdfd1cU, 0x3d9393aeU, 0x4c26266aU, + 0x6c36365aU, 0x7e3f3f41U, 0xf5f7f702U, 0x83cccc4fU, + 0x6834345cU, 0x51a5a5f4U, 0xd1e5e534U, 0xf9f1f108U, + 0xe2717193U, 0xabd8d873U, 0x62313153U, 0x2a15153fU, + 0x0804040cU, 0x95c7c752U, 0x46232365U, 0x9dc3c35eU, + 0x30181828U, 0x379696a1U, 0x0a05050fU, 0x2f9a9ab5U, + 0x0e070709U, 0x24121236U, 0x1b80809bU, 0xdfe2e23dU, + 0xcdebeb26U, 0x4e272769U, 0x7fb2b2cdU, 0xea75759fU, + 0x1209091bU, 0x1d83839eU, 0x582c2c74U, 0x341a1a2eU, + 0x361b1b2dU, 0xdc6e6eb2U, 0xb45a5aeeU, 0x5ba0a0fbU, + 0xa45252f6U, 0x763b3b4dU, 0xb7d6d661U, 0x7db3b3ceU, + 0x5229297bU, 0xdde3e33eU, 0x5e2f2f71U, 0x13848497U, + 0xa65353f5U, 0xb9d1d168U, 0x00000000U, 0xc1eded2cU, + 0x40202060U, 0xe3fcfc1fU, 0x79b1b1c8U, 0xb65b5bedU, + 0xd46a6abeU, 0x8dcbcb46U, 0x67bebed9U, 0x7239394bU, + 0x944a4adeU, 0x984c4cd4U, 0xb05858e8U, 0x85cfcf4aU, + 0xbbd0d06bU, 0xc5efef2aU, 0x4faaaae5U, 0xedfbfb16U, + 0x864343c5U, 0x9a4d4dd7U, 0x66333355U, 0x11858594U, + 0x8a4545cfU, 0xe9f9f910U, 0x04020206U, 0xfe7f7f81U, + 0xa05050f0U, 0x783c3c44U, 0x259f9fbaU, 0x4ba8a8e3U, + 0xa25151f3U, 0x5da3a3feU, 0x804040c0U, 0x058f8f8aU, + 0x3f9292adU, 0x219d9dbcU, 0x70383848U, 0xf1f5f504U, + 0x63bcbcdfU, 0x77b6b6c1U, 0xafdada75U, 0x42212163U, + 0x20101030U, 0xe5ffff1aU, 0xfdf3f30eU, 0xbfd2d26dU, + 0x81cdcd4cU, 0x180c0c14U, 0x26131335U, 0xc3ecec2fU, + 0xbe5f5fe1U, 0x359797a2U, 0x884444ccU, 0x2e171739U, + 0x93c4c457U, 0x55a7a7f2U, 0xfc7e7e82U, 0x7a3d3d47U, + 0xc86464acU, 0xba5d5de7U, 0x3219192bU, 0xe6737395U, + 0xc06060a0U, 0x19818198U, 0x9e4f4fd1U, 0xa3dcdc7fU, + 0x44222266U, 0x542a2a7eU, 0x3b9090abU, 0x0b888883U, + 0x8c4646caU, 0xc7eeee29U, 0x6bb8b8d3U, 0x2814143cU, + 0xa7dede79U, 0xbc5e5ee2U, 0x160b0b1dU, 0xaddbdb76U, + 0xdbe0e03bU, 0x64323256U, 0x743a3a4eU, 0x140a0a1eU, + 0x924949dbU, 0x0c06060aU, 0x4824246cU, 0xb85c5ce4U, + 0x9fc2c25dU, 0xbdd3d36eU, 0x43acacefU, 0xc46262a6U, + 0x399191a8U, 0x319595a4U, 0xd3e4e437U, 0xf279798bU, + 0xd5e7e732U, 0x8bc8c843U, 0x6e373759U, 0xda6d6db7U, + 0x018d8d8cU, 0xb1d5d564U, 0x9c4e4ed2U, 0x49a9a9e0U, + 0xd86c6cb4U, 0xac5656faU, 0xf3f4f407U, 0xcfeaea25U, + 0xca6565afU, 0xf47a7a8eU, 0x47aeaee9U, 0x10080818U, + 0x6fbabad5U, 0xf0787888U, 0x4a25256fU, 0x5c2e2e72U, + 0x381c1c24U, 0x57a6a6f1U, 0x73b4b4c7U, 0x97c6c651U, + 0xcbe8e823U, 0xa1dddd7cU, 0xe874749cU, 0x3e1f1f21U, + 0x964b4bddU, 0x61bdbddcU, 0x0d8b8b86U, 0x0f8a8a85U, + 0xe0707090U, 0x7c3e3e42U, 0x71b5b5c4U, 0xcc6666aaU, + 0x904848d8U, 0x06030305U, 0xf7f6f601U, 0x1c0e0e12U, + 0xc26161a3U, 0x6a35355fU, 0xae5757f9U, 0x69b9b9d0U, + 0x17868691U, 0x99c1c158U, 0x3a1d1d27U, 0x279e9eb9U, + 0xd9e1e138U, 0xebf8f813U, 0x2b9898b3U, 0x22111133U, + 0xd26969bbU, 0xa9d9d970U, 0x078e8e89U, 0x339494a7U, + 0x2d9b9bb6U, 0x3c1e1e22U, 0x15878792U, 0xc9e9e920U, + 0x87cece49U, 0xaa5555ffU, 0x50282878U, 0xa5dfdf7aU, + 0x038c8c8fU, 0x59a1a1f8U, 0x09898980U, 0x1a0d0d17U, + 0x65bfbfdaU, 0xd7e6e631U, 0x844242c6U, 0xd06868b8U, + 0x824141c3U, 0x299999b0U, 0x5a2d2d77U, 0x1e0f0f11U, + 0x7bb0b0cbU, 0xa85454fcU, 0x6dbbbbd6U, 0x2c16163aU, +}; +const u32 Td0[256] = { + 0x51f4a750U, 0x7e416553U, 0x1a17a4c3U, 0x3a275e96U, + 0x3bab6bcbU, 0x1f9d45f1U, 0xacfa58abU, 0x4be30393U, + 0x2030fa55U, 0xad766df6U, 0x88cc7691U, 0xf5024c25U, + 0x4fe5d7fcU, 0xc52acbd7U, 0x26354480U, 0xb562a38fU, + 0xdeb15a49U, 0x25ba1b67U, 0x45ea0e98U, 0x5dfec0e1U, + 0xc32f7502U, 0x814cf012U, 0x8d4697a3U, 0x6bd3f9c6U, + 0x038f5fe7U, 0x15929c95U, 0xbf6d7aebU, 0x955259daU, + 0xd4be832dU, 0x587421d3U, 0x49e06929U, 0x8ec9c844U, + 0x75c2896aU, 0xf48e7978U, 0x99583e6bU, 0x27b971ddU, + 0xbee14fb6U, 0xf088ad17U, 0xc920ac66U, 0x7dce3ab4U, + 0x63df4a18U, 0xe51a3182U, 0x97513360U, 0x62537f45U, + 0xb16477e0U, 0xbb6bae84U, 0xfe81a01cU, 0xf9082b94U, + 0x70486858U, 0x8f45fd19U, 0x94de6c87U, 0x527bf8b7U, + 0xab73d323U, 0x724b02e2U, 0xe31f8f57U, 0x6655ab2aU, + 0xb2eb2807U, 0x2fb5c203U, 0x86c57b9aU, 0xd33708a5U, + 0x302887f2U, 0x23bfa5b2U, 0x02036abaU, 0xed16825cU, + 0x8acf1c2bU, 0xa779b492U, 0xf307f2f0U, 0x4e69e2a1U, + 0x65daf4cdU, 0x0605bed5U, 0xd134621fU, 0xc4a6fe8aU, + 0x342e539dU, 0xa2f355a0U, 0x058ae132U, 0xa4f6eb75U, + 0x0b83ec39U, 0x4060efaaU, 0x5e719f06U, 0xbd6e1051U, + 0x3e218af9U, 0x96dd063dU, 0xdd3e05aeU, 0x4de6bd46U, + 0x91548db5U, 0x71c45d05U, 0x0406d46fU, 0x605015ffU, + 0x1998fb24U, 0xd6bde997U, 0x894043ccU, 0x67d99e77U, + 0xb0e842bdU, 0x07898b88U, 0xe7195b38U, 0x79c8eedbU, + 0xa17c0a47U, 0x7c420fe9U, 0xf8841ec9U, 0x00000000U, + 0x09808683U, 0x322bed48U, 0x1e1170acU, 0x6c5a724eU, + 0xfd0efffbU, 0x0f853856U, 0x3daed51eU, 0x362d3927U, + 0x0a0fd964U, 0x685ca621U, 0x9b5b54d1U, 0x24362e3aU, + 0x0c0a67b1U, 0x9357e70fU, 0xb4ee96d2U, 0x1b9b919eU, + 0x80c0c54fU, 0x61dc20a2U, 0x5a774b69U, 0x1c121a16U, + 0xe293ba0aU, 0xc0a02ae5U, 0x3c22e043U, 0x121b171dU, + 0x0e090d0bU, 0xf28bc7adU, 0x2db6a8b9U, 0x141ea9c8U, + 0x57f11985U, 0xaf75074cU, 0xee99ddbbU, 0xa37f60fdU, + 0xf701269fU, 0x5c72f5bcU, 0x44663bc5U, 0x5bfb7e34U, + 0x8b432976U, 0xcb23c6dcU, 0xb6edfc68U, 0xb8e4f163U, + 0xd731dccaU, 0x42638510U, 0x13972240U, 0x84c61120U, + 0x854a247dU, 0xd2bb3df8U, 0xaef93211U, 0xc729a16dU, + 0x1d9e2f4bU, 0xdcb230f3U, 0x0d8652ecU, 0x77c1e3d0U, + 0x2bb3166cU, 0xa970b999U, 0x119448faU, 0x47e96422U, + 0xa8fc8cc4U, 0xa0f03f1aU, 0x567d2cd8U, 0x223390efU, + 0x87494ec7U, 0xd938d1c1U, 0x8ccaa2feU, 0x98d40b36U, + 0xa6f581cfU, 0xa57ade28U, 0xdab78e26U, 0x3fadbfa4U, + 0x2c3a9de4U, 0x5078920dU, 0x6a5fcc9bU, 0x547e4662U, + 0xf68d13c2U, 0x90d8b8e8U, 0x2e39f75eU, 0x82c3aff5U, + 0x9f5d80beU, 0x69d0937cU, 0x6fd52da9U, 0xcf2512b3U, + 0xc8ac993bU, 0x10187da7U, 0xe89c636eU, 0xdb3bbb7bU, + 0xcd267809U, 0x6e5918f4U, 0xec9ab701U, 0x834f9aa8U, + 0xe6956e65U, 0xaaffe67eU, 0x21bccf08U, 0xef15e8e6U, + 0xbae79bd9U, 0x4a6f36ceU, 0xea9f09d4U, 0x29b07cd6U, + 0x31a4b2afU, 0x2a3f2331U, 0xc6a59430U, 0x35a266c0U, + 0x744ebc37U, 0xfc82caa6U, 0xe090d0b0U, 0x33a7d815U, + 0xf104984aU, 0x41ecdaf7U, 0x7fcd500eU, 0x1791f62fU, + 0x764dd68dU, 0x43efb04dU, 0xccaa4d54U, 0xe49604dfU, + 0x9ed1b5e3U, 0x4c6a881bU, 0xc12c1fb8U, 0x4665517fU, + 0x9d5eea04U, 0x018c355dU, 0xfa877473U, 0xfb0b412eU, + 0xb3671d5aU, 0x92dbd252U, 0xe9105633U, 0x6dd64713U, + 0x9ad7618cU, 0x37a10c7aU, 0x59f8148eU, 0xeb133c89U, + 0xcea927eeU, 0xb761c935U, 0xe11ce5edU, 0x7a47b13cU, + 0x9cd2df59U, 0x55f2733fU, 0x1814ce79U, 0x73c737bfU, + 0x53f7cdeaU, 0x5ffdaa5bU, 0xdf3d6f14U, 0x7844db86U, + 0xcaaff381U, 0xb968c43eU, 0x3824342cU, 0xc2a3405fU, + 0x161dc372U, 0xbce2250cU, 0x283c498bU, 0xff0d9541U, + 0x39a80171U, 0x080cb3deU, 0xd8b4e49cU, 0x6456c190U, + 0x7bcb8461U, 0xd532b670U, 0x486c5c74U, 0xd0b85742U, +}; +const u8 Td4s[256] = { + 0x52U, 0x09U, 0x6aU, 0xd5U, 0x30U, 0x36U, 0xa5U, 0x38U, + 0xbfU, 0x40U, 0xa3U, 0x9eU, 0x81U, 0xf3U, 0xd7U, 0xfbU, + 0x7cU, 0xe3U, 0x39U, 0x82U, 0x9bU, 0x2fU, 0xffU, 0x87U, + 0x34U, 0x8eU, 0x43U, 0x44U, 0xc4U, 0xdeU, 0xe9U, 0xcbU, + 0x54U, 0x7bU, 0x94U, 0x32U, 0xa6U, 0xc2U, 0x23U, 0x3dU, + 0xeeU, 0x4cU, 0x95U, 0x0bU, 0x42U, 0xfaU, 0xc3U, 0x4eU, + 0x08U, 0x2eU, 0xa1U, 0x66U, 0x28U, 0xd9U, 0x24U, 0xb2U, + 0x76U, 0x5bU, 0xa2U, 0x49U, 0x6dU, 0x8bU, 0xd1U, 0x25U, + 0x72U, 0xf8U, 0xf6U, 0x64U, 0x86U, 0x68U, 0x98U, 0x16U, + 0xd4U, 0xa4U, 0x5cU, 0xccU, 0x5dU, 0x65U, 0xb6U, 0x92U, + 0x6cU, 0x70U, 0x48U, 0x50U, 0xfdU, 0xedU, 0xb9U, 0xdaU, + 0x5eU, 0x15U, 0x46U, 0x57U, 0xa7U, 0x8dU, 0x9dU, 0x84U, + 0x90U, 0xd8U, 0xabU, 0x00U, 0x8cU, 0xbcU, 0xd3U, 0x0aU, + 0xf7U, 0xe4U, 0x58U, 0x05U, 0xb8U, 0xb3U, 0x45U, 0x06U, + 0xd0U, 0x2cU, 0x1eU, 0x8fU, 0xcaU, 0x3fU, 0x0fU, 0x02U, + 0xc1U, 0xafU, 0xbdU, 0x03U, 0x01U, 0x13U, 0x8aU, 0x6bU, + 0x3aU, 0x91U, 0x11U, 0x41U, 0x4fU, 0x67U, 0xdcU, 0xeaU, + 0x97U, 0xf2U, 0xcfU, 0xceU, 0xf0U, 0xb4U, 0xe6U, 0x73U, + 0x96U, 0xacU, 0x74U, 0x22U, 0xe7U, 0xadU, 0x35U, 0x85U, + 0xe2U, 0xf9U, 0x37U, 0xe8U, 0x1cU, 0x75U, 0xdfU, 0x6eU, + 0x47U, 0xf1U, 0x1aU, 0x71U, 0x1dU, 0x29U, 0xc5U, 0x89U, + 0x6fU, 0xb7U, 0x62U, 0x0eU, 0xaaU, 0x18U, 0xbeU, 0x1bU, + 0xfcU, 0x56U, 0x3eU, 0x4bU, 0xc6U, 0xd2U, 0x79U, 0x20U, + 0x9aU, 0xdbU, 0xc0U, 0xfeU, 0x78U, 0xcdU, 0x5aU, 0xf4U, + 0x1fU, 0xddU, 0xa8U, 0x33U, 0x88U, 0x07U, 0xc7U, 0x31U, + 0xb1U, 0x12U, 0x10U, 0x59U, 0x27U, 0x80U, 0xecU, 0x5fU, + 0x60U, 0x51U, 0x7fU, 0xa9U, 0x19U, 0xb5U, 0x4aU, 0x0dU, + 0x2dU, 0xe5U, 0x7aU, 0x9fU, 0x93U, 0xc9U, 0x9cU, 0xefU, + 0xa0U, 0xe0U, 0x3bU, 0x4dU, 0xaeU, 0x2aU, 0xf5U, 0xb0U, + 0xc8U, 0xebU, 0xbbU, 0x3cU, 0x83U, 0x53U, 0x99U, 0x61U, + 0x17U, 0x2bU, 0x04U, 0x7eU, 0xbaU, 0x77U, 0xd6U, 0x26U, + 0xe1U, 0x69U, 0x14U, 0x63U, 0x55U, 0x21U, 0x0cU, 0x7dU, +}; +const u8 rcons[] = { + 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1B, 0x36 + /* for 128-bit blocks, Rijndael never uses more than 10 rcon values */ +}; + +/** + * Expand the cipher key into the encryption key schedule. + * + * @return the number of rounds for the given cipher key size. + */ +#ifndef PLATFORM_FREEBSD //Baron +static void rijndaelKeySetupEnc(u32 rk[/*44*/], const u8 cipherKey[]) +{ + int i; + u32 temp; + + rk[0] = GETU32(cipherKey ); + rk[1] = GETU32(cipherKey + 4); + rk[2] = GETU32(cipherKey + 8); + rk[3] = GETU32(cipherKey + 12); + for (i = 0; i < 10; i++) { + temp = rk[3]; + rk[4] = rk[0] ^ + TE421(temp) ^ TE432(temp) ^ TE443(temp) ^ TE414(temp) ^ + RCON(i); + rk[5] = rk[1] ^ rk[4]; + rk[6] = rk[2] ^ rk[5]; + rk[7] = rk[3] ^ rk[6]; + rk += 4; + } +} + +static void rijndaelEncrypt(u32 rk[/*44*/], u8 pt[16], u8 ct[16]) +{ + u32 s0, s1, s2, s3, t0, t1, t2, t3; + int Nr = 10; +#ifndef FULL_UNROLL + int r; +#endif /* ?FULL_UNROLL */ + + /* + * map byte array block to cipher state + * and add initial round key: + */ + s0 = GETU32(pt ) ^ rk[0]; + s1 = GETU32(pt + 4) ^ rk[1]; + s2 = GETU32(pt + 8) ^ rk[2]; + s3 = GETU32(pt + 12) ^ rk[3]; + +#define ROUND(i,d,s) \ +d##0 = TE0(s##0) ^ TE1(s##1) ^ TE2(s##2) ^ TE3(s##3) ^ rk[4 * i]; \ +d##1 = TE0(s##1) ^ TE1(s##2) ^ TE2(s##3) ^ TE3(s##0) ^ rk[4 * i + 1]; \ +d##2 = TE0(s##2) ^ TE1(s##3) ^ TE2(s##0) ^ TE3(s##1) ^ rk[4 * i + 2]; \ +d##3 = TE0(s##3) ^ TE1(s##0) ^ TE2(s##1) ^ TE3(s##2) ^ rk[4 * i + 3] + +#ifdef FULL_UNROLL + + ROUND(1,t,s); + ROUND(2,s,t); + ROUND(3,t,s); + ROUND(4,s,t); + ROUND(5,t,s); + ROUND(6,s,t); + ROUND(7,t,s); + ROUND(8,s,t); + ROUND(9,t,s); + + rk += Nr << 2; + +#else /* !FULL_UNROLL */ + + /* Nr - 1 full rounds: */ + r = Nr >> 1; + for (;;) { + ROUND(1,t,s); + rk += 8; + if (--r == 0) + break; + ROUND(0,s,t); + } + +#endif /* ?FULL_UNROLL */ + +#undef ROUND + + /* + * apply last round and + * map cipher state to byte array block: + */ + s0 = TE41(t0) ^ TE42(t1) ^ TE43(t2) ^ TE44(t3) ^ rk[0]; + PUTU32(ct , s0); + s1 = TE41(t1) ^ TE42(t2) ^ TE43(t3) ^ TE44(t0) ^ rk[1]; + PUTU32(ct + 4, s1); + s2 = TE41(t2) ^ TE42(t3) ^ TE43(t0) ^ TE44(t1) ^ rk[2]; + PUTU32(ct + 8, s2); + s3 = TE41(t3) ^ TE42(t0) ^ TE43(t1) ^ TE44(t2) ^ rk[3]; + PUTU32(ct + 12, s3); +} + +static void * aes_encrypt_init(u8 *key, size_t len) +{ + u32 *rk; + if (len != 16) + return NULL; + rk = (u32*)rtw_malloc(AES_PRIV_SIZE); + if (rk == NULL) + return NULL; + rijndaelKeySetupEnc(rk, key); + return rk; +} + +static void aes_128_encrypt(void *ctx, u8 *plain, u8 *crypt) +{ + rijndaelEncrypt(ctx, plain, crypt); +} + + +static void gf_mulx(u8 *pad) +{ + int i, carry; + + carry = pad[0] & 0x80; + for (i = 0; i < AES_BLOCK_SIZE - 1; i++) + pad[i] = (pad[i] << 1) | (pad[i + 1] >> 7); + pad[AES_BLOCK_SIZE - 1] <<= 1; + if (carry) + pad[AES_BLOCK_SIZE - 1] ^= 0x87; +} + +static void aes_encrypt_deinit(void *ctx) +{ + _rtw_memset(ctx, 0, AES_PRIV_SIZE); + rtw_mfree(ctx, AES_PRIV_SIZE); +} + + +/** + * omac1_aes_128_vector - One-Key CBC MAC (OMAC1) hash with AES-128 + * @key: 128-bit key for the hash operation + * @num_elem: Number of elements in the data vector + * @addr: Pointers to the data areas + * @len: Lengths of the data blocks + * @mac: Buffer for MAC (128 bits, i.e., 16 bytes) + * Returns: 0 on success, -1 on failure + * + * This is a mode for using block cipher (AES in this case) for authentication. + * OMAC1 was standardized with the name CMAC by NIST in a Special Publication + * (SP) 800-38B. + */ +static int omac1_aes_128_vector(u8 *key, size_t num_elem, + u8 *addr[], size_t *len, u8 *mac) +{ + void *ctx; + u8 cbc[AES_BLOCK_SIZE], pad[AES_BLOCK_SIZE]; + u8 *pos, *end; + size_t i, e, left, total_len; + + ctx = aes_encrypt_init(key, 16); + if (ctx == NULL) + return -1; + _rtw_memset(cbc, 0, AES_BLOCK_SIZE); + + total_len = 0; + for (e = 0; e < num_elem; e++) + total_len += len[e]; + left = total_len; + + e = 0; + pos = addr[0]; + end = pos + len[0]; + + while (left >= AES_BLOCK_SIZE) { + for (i = 0; i < AES_BLOCK_SIZE; i++) { + cbc[i] ^= *pos++; + if (pos >= end) { + e++; + pos = addr[e]; + end = pos + len[e]; + } + } + if (left > AES_BLOCK_SIZE) + aes_128_encrypt(ctx, cbc, cbc); + left -= AES_BLOCK_SIZE; + } + + _rtw_memset(pad, 0, AES_BLOCK_SIZE); + aes_128_encrypt(ctx, pad, pad); + gf_mulx(pad); + + if (left || total_len == 0) { + for (i = 0; i < left; i++) { + cbc[i] ^= *pos++; + if (pos >= end) { + e++; + pos = addr[e]; + end = pos + len[e]; + } + } + cbc[left] ^= 0x80; + gf_mulx(pad); + } + + for (i = 0; i < AES_BLOCK_SIZE; i++) + pad[i] ^= cbc[i]; + aes_128_encrypt(ctx, pad, mac); + aes_encrypt_deinit(ctx); + return 0; +} + + +/** + * omac1_aes_128 - One-Key CBC MAC (OMAC1) hash with AES-128 (aka AES-CMAC) + * @key: 128-bit key for the hash operation + * @data: Data buffer for which a MAC is determined + * @data_len: Length of data buffer in bytes + * @mac: Buffer for MAC (128 bits, i.e., 16 bytes) + * Returns: 0 on success, -1 on failure + * + * This is a mode for using block cipher (AES in this case) for authentication. + * OMAC1 was standardized with the name CMAC by NIST in a Special Publication + * (SP) 800-38B. + */ //modify for CONFIG_IEEE80211W +int omac1_aes_128(u8 *key, u8 *data, size_t data_len, u8 *mac) +{ + return omac1_aes_128_vector(key, 1, &data, &data_len, mac); +} +#endif //PLATFORM_FREEBSD Baron + +#ifdef CONFIG_TDLS +void wpa_tdls_generate_tpk(_adapter *padapter, PVOID sta) +{ + struct sta_info *psta = (struct sta_info *)sta; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + u8 *SNonce = psta->SNonce; + u8 *ANonce = psta->ANonce; + + u8 key_input[SHA256_MAC_LEN]; + u8 *nonce[2]; + size_t len[2]; + u8 data[3 * ETH_ALEN]; + + /* IEEE Std 802.11z-2010 8.5.9.1: + * TPK-Key-Input = SHA-256(min(SNonce, ANonce) || max(SNonce, ANonce)) + */ + len[0] = 32; + len[1] = 32; + if (os_memcmp(SNonce, ANonce, 32) < 0) { + nonce[0] = SNonce; + nonce[1] = ANonce; + } else { + nonce[0] = ANonce; + nonce[1] = SNonce; + } + + sha256_vector(2, nonce, len, key_input); + + /* + * TPK-Key-Data = KDF-N_KEY(TPK-Key-Input, "TDLS PMK", + * min(MAC_I, MAC_R) || max(MAC_I, MAC_R) || BSSID || N_KEY) + * TODO: is N_KEY really included in KDF Context and if so, in which + * presentation format (little endian 16-bit?) is it used? It gets + * added by the KDF anyway.. + */ + + if (os_memcmp(adapter_mac_addr(padapter), psta->hwaddr, ETH_ALEN) < 0) { + _rtw_memcpy(data, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(data + ETH_ALEN, psta->hwaddr, ETH_ALEN); + } else { + _rtw_memcpy(data, psta->hwaddr, ETH_ALEN); + _rtw_memcpy(data + ETH_ALEN, adapter_mac_addr(padapter), ETH_ALEN); + } + _rtw_memcpy(data + 2 * ETH_ALEN, get_bssid(pmlmepriv), ETH_ALEN); + + sha256_prf(key_input, SHA256_MAC_LEN, "TDLS PMK", data, sizeof(data), (u8 *) &psta->tpk, sizeof(psta->tpk)); + + +} + +/** + * wpa_tdls_ftie_mic - Calculate TDLS FTIE MIC + * @kck: TPK-KCK + * @lnkid: Pointer to the beginning of Link Identifier IE + * @rsnie: Pointer to the beginning of RSN IE used for handshake + * @timeoutie: Pointer to the beginning of Timeout IE used for handshake + * @ftie: Pointer to the beginning of FT IE + * @mic: Pointer for writing MIC + * + * Calculate MIC for TDLS frame. + */ +int wpa_tdls_ftie_mic(u8 *kck, u8 trans_seq, + u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie, + u8 *mic) +{ + u8 *buf, *pos; + struct wpa_tdls_ftie *_ftie; + struct wpa_tdls_lnkid *_lnkid; + int ret; + int len = 2 * ETH_ALEN + 1 + 2 + lnkid[1] + 2 + rsnie[1] + + 2 + timeoutie[1] + 2 + ftie[1]; + buf = rtw_zmalloc(len); + if (!buf) { + DBG_871X("TDLS: No memory for MIC calculation\n"); + return -1; + } + + pos = buf; + _lnkid = (struct wpa_tdls_lnkid *) lnkid; + /* 1) TDLS initiator STA MAC address */ + _rtw_memcpy(pos, _lnkid->init_sta, ETH_ALEN); + pos += ETH_ALEN; + /* 2) TDLS responder STA MAC address */ + _rtw_memcpy(pos, _lnkid->resp_sta, ETH_ALEN); + pos += ETH_ALEN; + /* 3) Transaction Sequence number */ + *pos++ = trans_seq; + /* 4) Link Identifier IE */ + _rtw_memcpy(pos, lnkid, 2 + lnkid[1]); + pos += 2 + lnkid[1]; + /* 5) RSN IE */ + _rtw_memcpy(pos, rsnie, 2 + rsnie[1]); + pos += 2 + rsnie[1]; + /* 6) Timeout Interval IE */ + _rtw_memcpy(pos, timeoutie, 2 + timeoutie[1]); + pos += 2 + timeoutie[1]; + /* 7) FTIE, with the MIC field of the FTIE set to 0 */ + _rtw_memcpy(pos, ftie, 2 + ftie[1]); + _ftie = (struct wpa_tdls_ftie *) pos; + _rtw_memset(_ftie->mic, 0, TDLS_MIC_LEN); + pos += 2 + ftie[1]; + + ret = omac1_aes_128(kck, buf, pos - buf, mic); + rtw_mfree(buf, len); + return ret; + +} + +/** + * wpa_tdls_teardown_ftie_mic - Calculate TDLS TEARDOWN FTIE MIC + * @kck: TPK-KCK + * @lnkid: Pointer to the beginning of Link Identifier IE + * @reason: Reason code of TDLS Teardown + * @dialog_token: Dialog token that was used in the MIC calculation for TPK Handshake Message 3 + * @trans_seq: Transaction Sequence number (1 octet) which shall be set to the value 4 + * @ftie: Pointer to the beginning of FT IE + * @mic: Pointer for writing MIC + * + * Calculate MIC for TDLS TEARDOWN frame according to Section 10.22.5 in IEEE 802.11 - 2012. + */ +int wpa_tdls_teardown_ftie_mic(u8 *kck, u8 *lnkid, u16 reason, + u8 dialog_token, u8 trans_seq, u8 *ftie, u8 *mic) +{ + u8 *buf, *pos; + struct wpa_tdls_ftie *_ftie; + int ret; + int len = 2 + lnkid[1] + 2 + 1 + 1 + 2 + ftie[1]; + + buf = rtw_zmalloc(len); + if (!buf) { + DBG_871X("TDLS: No memory for MIC calculation\n"); + return -1; + } + + pos = buf; + /* 1) Link Identifier IE */ + _rtw_memcpy(pos, lnkid, 2 + lnkid[1]); + pos += 2 + lnkid[1]; + /* 2) Reason Code */ + _rtw_memcpy(pos, (u8 *)&reason, 2); + pos += 2; + /* 3) Dialog Token */ + *pos++ = dialog_token; + /* 4) Transaction Sequence number */ + *pos++ = trans_seq; + /* 5) FTIE, with the MIC field of the FTIE set to 0 */ + _rtw_memcpy(pos, ftie, 2 + ftie[1]); + _ftie = (struct wpa_tdls_ftie *) pos; + _rtw_memset(_ftie->mic, 0, TDLS_MIC_LEN); + pos += 2 + ftie[1]; + + ret = omac1_aes_128(kck, buf, pos - buf, mic); + rtw_mfree(buf, len); + return ret; + +} + +int tdls_verify_mic(u8 *kck, u8 trans_seq, + u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie) +{ + u8 *buf, *pos; + int len; + u8 mic[16]; + int ret; + u8 *rx_ftie, *tmp_ftie; + + if (lnkid == NULL || rsnie == NULL || + timeoutie == NULL || ftie == NULL){ + return _FAIL; + } + + len = 2 * ETH_ALEN + 1 + 2 + 18 + 2 + *(rsnie+1) + 2 + *(timeoutie+1) + 2 + *(ftie+1); + + buf = rtw_zmalloc(len); + if (buf == NULL) + return _FAIL; + + pos = buf; + /* 1) TDLS initiator STA MAC address */ + _rtw_memcpy(pos, lnkid + ETH_ALEN + 2, ETH_ALEN); + pos += ETH_ALEN; + /* 2) TDLS responder STA MAC address */ + _rtw_memcpy(pos, lnkid + 2 * ETH_ALEN + 2, ETH_ALEN); + pos += ETH_ALEN; + /* 3) Transaction Sequence number */ + *pos++ = trans_seq; + /* 4) Link Identifier IE */ + _rtw_memcpy(pos, lnkid, 2 + 18); + pos += 2 + 18; + /* 5) RSN IE */ + _rtw_memcpy(pos, rsnie, 2 + *(rsnie+1)); + pos += 2 + *(rsnie+1); + /* 6) Timeout Interval IE */ + _rtw_memcpy(pos, timeoutie, 2 + *(timeoutie+1)); + pos += 2 + *(timeoutie+1); + /* 7) FTIE, with the MIC field of the FTIE set to 0 */ + _rtw_memcpy(pos, ftie, 2 + *(ftie+1)); + pos += 2; + tmp_ftie = (u8 *) (pos+2); + _rtw_memset(tmp_ftie, 0, 16); + pos += *(ftie+1); + + ret = omac1_aes_128(kck, buf, pos - buf, mic); + rtw_mfree(buf, len); + if (ret) + return _FAIL; + rx_ftie = ftie+4; + + if (os_memcmp(mic, rx_ftie, 16) == 0) { + //Valid MIC + return _SUCCESS; + } + + //Invalid MIC + DBG_871X( "[%s] Invalid MIC\n", __FUNCTION__); + return _FAIL; + +} +#endif //CONFIG_TDLS + +void rtw_use_tkipkey_handler(RTW_TIMER_HDL_ARGS) +{ + _adapter *padapter = (_adapter *)FunctionContext; + +_func_enter_; + + RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("^^^rtw_use_tkipkey_handler ^^^\n")); + +/* + if (RTW_CANNOT_RUN(padapter)) { + RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("^^^rtw_use_tkipkey_handler (padapter->bDriverStopped %s)(padapter->bSurpriseRemoved %s)^^^\n" + , rtw_is_drv_stopped(padapter)?"True":"False" + , rtw_is_surprise_removed(padapter)?"True":"False")); + + return; + } + */ + + padapter->securitypriv.busetkipkey=_TRUE; + + RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("^^^rtw_use_tkipkey_handler padapter->securitypriv.busetkipkey=%d^^^\n",padapter->securitypriv.busetkipkey)); + +_func_exit_; + +} + +/* Restore HW wep key setting according to key_mask */ +void rtw_sec_restore_wep_key(_adapter *adapter) +{ + struct security_priv* securitypriv=&(adapter->securitypriv); + sint keyid; + + if((_WEP40_ == securitypriv->dot11PrivacyAlgrthm) ||(_WEP104_ == securitypriv->dot11PrivacyAlgrthm)) { + for(keyid=0;keyid<4;keyid++){ + if(securitypriv->key_mask & BIT(keyid)){ + if(keyid == securitypriv->dot11PrivacyKeyIndex) + rtw_set_key(adapter,securitypriv, keyid, 1, _FALSE); + else + rtw_set_key(adapter,securitypriv, keyid, 0, _FALSE); + } + } + } +} + +u8 rtw_handle_tkip_countermeasure(_adapter* adapter, const char *caller) +{ + struct security_priv* securitypriv=&(adapter->securitypriv); + u8 status = _SUCCESS; + + if (securitypriv->btkip_countermeasure == _TRUE) { + u32 passing_ms = rtw_get_passing_time_ms(securitypriv->btkip_countermeasure_time); + if (passing_ms > 60*1000) { + DBG_871X_LEVEL(_drv_always_, "%s("ADPT_FMT") countermeasure time:%ds > 60s \n", + caller, ADPT_ARG(adapter), passing_ms/1000); + securitypriv->btkip_countermeasure = _FALSE; + securitypriv->btkip_countermeasure_time = 0; + } else { + DBG_871X_LEVEL(_drv_always_, "%s("ADPT_FMT") countermeasure time:%ds < 60s \n", + caller, ADPT_ARG(adapter), passing_ms/1000); + status = _FAIL; + } + } + + return status; +} diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_sreset.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_sreset.c new file mode 100644 index 000000000..17a48ed19 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_sreset.c @@ -0,0 +1,369 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include +#include +#include + +void sreset_init_value(_adapter *padapter) +{ +#if defined(DBG_CONFIG_ERROR_DETECT) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct sreset_priv *psrtpriv = &pHalData->srestpriv; + + _rtw_mutex_init(&psrtpriv->silentreset_mutex); + psrtpriv->silent_reset_inprogress = _FALSE; + psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS; + psrtpriv->last_tx_time =0; + psrtpriv->last_tx_complete_time =0; +#endif +} +void sreset_reset_value(_adapter *padapter) +{ +#if defined(DBG_CONFIG_ERROR_DETECT) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct sreset_priv *psrtpriv = &pHalData->srestpriv; + + psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS; + psrtpriv->last_tx_time =0; + psrtpriv->last_tx_complete_time =0; +#endif +} + +u8 sreset_get_wifi_status(_adapter *padapter) +{ +#if defined(DBG_CONFIG_ERROR_DETECT) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct sreset_priv *psrtpriv = &pHalData->srestpriv; + + u8 status = WIFI_STATUS_SUCCESS; + u32 val32 = 0; + _irqL irqL; + if(psrtpriv->silent_reset_inprogress == _TRUE) + { + return status; + } + val32 =rtw_read32(padapter,REG_TXDMA_STATUS); + if(val32==0xeaeaeaea){ + psrtpriv->Wifi_Error_Status = WIFI_IF_NOT_EXIST; + } + else if(val32!=0){ + DBG_8192C("txdmastatu(%x)\n",val32); + psrtpriv->Wifi_Error_Status = WIFI_MAC_TXDMA_ERROR; + } + + if(WIFI_STATUS_SUCCESS !=psrtpriv->Wifi_Error_Status) + { + DBG_8192C("==>%s error_status(0x%x) \n",__FUNCTION__,psrtpriv->Wifi_Error_Status); + status = (psrtpriv->Wifi_Error_Status &( ~(USB_READ_PORT_FAIL|USB_WRITE_PORT_FAIL))); + } + DBG_8192C("==> %s wifi_status(0x%x)\n",__FUNCTION__,status); + + //status restore + psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS; + + return status; +#else + return WIFI_STATUS_SUCCESS; +#endif +} + +void sreset_set_wifi_error_status(_adapter *padapter, u32 status) +{ +#if defined(DBG_CONFIG_ERROR_DETECT) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + pHalData->srestpriv.Wifi_Error_Status = status; +#endif +} + +void sreset_set_trigger_point(_adapter *padapter, s32 tgp) +{ +#if defined(DBG_CONFIG_ERROR_DETECT) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + pHalData->srestpriv.dbg_trigger_point = tgp; +#endif +} + +bool sreset_inprogress(_adapter *padapter) +{ +#if defined(DBG_CONFIG_ERROR_RESET) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + return pHalData->srestpriv.silent_reset_inprogress; +#else + return _FALSE; +#endif +} + +void sreset_restore_security_station(_adapter *padapter) +{ + u8 EntryId = 0; + struct mlme_priv *mlmepriv = &padapter->mlmepriv; + struct sta_priv * pstapriv = &padapter->stapriv; + struct sta_info *psta; + struct security_priv* psecuritypriv=&(padapter->securitypriv); + struct mlme_ext_info *pmlmeinfo = &padapter->mlmeextpriv.mlmext_info; + + { + u8 val8; + + if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_8021X) { + val8 = 0xcc; + #ifdef CONFIG_WAPI_SUPPORT + } else if (padapter->wapiInfo.bWapiEnable && pmlmeinfo->auth_algo == dot11AuthAlgrthm_WAPI) { + //Disable TxUseDefaultKey, RxUseDefaultKey, RxBroadcastUseDefaultKey. + val8 = 0x4c; + #endif + } else { + val8 = 0xcf; + } + rtw_hal_set_hwreg(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); + } + + #if 0 + if ( ( padapter->securitypriv.dot11PrivacyAlgrthm == _WEP40_ ) || + ( padapter->securitypriv.dot11PrivacyAlgrthm == _WEP104_ )) + { + + for(EntryId=0; EntryId<4; EntryId++) + { + if(EntryId == psecuritypriv->dot11PrivacyKeyIndex) + rtw_set_key(padapter,&padapter->securitypriv, EntryId, 1,_FALSE); + else + rtw_set_key(padapter,&padapter->securitypriv, EntryId, 0,_FALSE); + } + + } + else + #endif + if((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) || + (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) + { + psta = rtw_get_stainfo(pstapriv, get_bssid(mlmepriv)); + if (psta == NULL) { + //DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail \n")); + } + else + { + //pairwise key + rtw_setstakey_cmd(padapter, psta, UNICAST_KEY,_FALSE); + //group key + rtw_set_key(padapter,&padapter->securitypriv,padapter->securitypriv.dot118021XGrpKeyid, 0,_FALSE); + } + } +} + +void sreset_restore_network_station(_adapter *padapter) +{ + struct mlme_priv *mlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 doiqk = _FALSE; + + #if 0 + { + //======================================================= + // reset related register of Beacon control + + //set MSR to nolink + Set_MSR(padapter, _HW_STATE_NOLINK_); + // reject all data frame + rtw_write16(padapter, REG_RXFLTMAP2,0x00); + //reset TSF + rtw_write8(padapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1))); + + // disable update TSF + SetBcnCtrlReg(padapter, BIT(4), 0); + + //======================================================= + } + #endif + + rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure,_FALSE); + + { + u8 threshold; + #ifdef CONFIG_USB_HCI + // TH=1 => means that invalidate usb rx aggregation + // TH=0 => means that validate usb rx aggregation, use init value. + if(mlmepriv->htpriv.ht_option) { + if(padapter->registrypriv.wifi_spec==1) + threshold = 1; + else + threshold = 0; + rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold)); + } else { + threshold = 1; + rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold)); + } + #endif + } + + doiqk = _TRUE; + rtw_hal_set_hwreg(padapter, HW_VAR_DO_IQK , &doiqk); + + set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); + + doiqk = _FALSE; + rtw_hal_set_hwreg(padapter , HW_VAR_DO_IQK , &doiqk); + //disable dynamic functions, such as high power, DIG + /*rtw_phydm_func_disable_all(padapter);*/ + + rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress); + + { + u8 join_type = 0; + rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); + } + + Set_MSR(padapter, (pmlmeinfo->state & 0x3)); + + mlmeext_joinbss_event_callback(padapter, 1); + //restore Sequence No. + rtw_hal_set_hwreg(padapter, HW_VAR_RESTORE_HW_SEQ, 0); + + sreset_restore_security_station(padapter); +} + + +void sreset_restore_network_status(_adapter *padapter) +{ + struct mlme_priv *mlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (check_fwstate(mlmepriv, WIFI_STATION_STATE)) { + DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); + sreset_restore_network_station(padapter); + } else if (check_fwstate(mlmepriv, WIFI_AP_STATE)) { + DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_AP_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); + rtw_ap_restore_network(padapter); + } else if (check_fwstate(mlmepriv, WIFI_ADHOC_STATE)) { + DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); + } else { + DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - ???\n", FUNC_ADPT_ARG(padapter), get_fwstate(mlmepriv)); + } +} + +void sreset_stop_adapter(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + if (padapter == NULL) + return; + + DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + + rtw_netif_stop_queue(padapter->pnetdev); + + rtw_cancel_all_timer(padapter); + + /* TODO: OS and HCI independent */ + #if defined(PLATFORM_LINUX) && defined(CONFIG_USB_HCI) + tasklet_kill(&pxmitpriv->xmit_tasklet); + #endif + + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) + rtw_scan_abort(padapter); + + if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) + { + rtw_set_to_roam(padapter, 0); + _rtw_join_timeout_handler(padapter); + } + +} + +void sreset_start_adapter(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + if (padapter == NULL) + return; + + DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + + if (check_fwstate(pmlmepriv, _FW_LINKED)) { + sreset_restore_network_status(padapter); + } + + /* TODO: OS and HCI independent */ + #if defined(PLATFORM_LINUX) && defined(CONFIG_USB_HCI) + tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); + #endif + + if (is_primary_adapter(padapter)) + _set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000); + + rtw_netif_wake_queue(padapter->pnetdev); +} + +void sreset_reset(_adapter *padapter) +{ +#ifdef DBG_CONFIG_ERROR_RESET + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct sreset_priv *psrtpriv = &pHalData->srestpriv; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + _irqL irqL; + u32 start = rtw_get_current_time(); + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + + DBG_871X("%s\n", __FUNCTION__); + + psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS; + + +#ifdef CONFIG_LPS + rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0, 0, "SRESET"); +#endif//#ifdef CONFIG_LPS + + _enter_pwrlock(&pwrpriv->lock); + + psrtpriv->silent_reset_inprogress = _TRUE; + pwrpriv->change_rfpwrstate = rf_off; + + sreset_stop_adapter(padapter); + #ifdef CONFIG_CONCURRENT_MODE + sreset_stop_adapter(padapter->pbuddy_adapter); + #endif + + #ifdef CONFIG_IPS + _ips_enter(padapter); + _ips_leave(padapter); + #endif + + sreset_start_adapter(padapter); + #ifdef CONFIG_CONCURRENT_MODE + sreset_start_adapter(padapter->pbuddy_adapter); + #endif + + psrtpriv->silent_reset_inprogress = _FALSE; + + _exit_pwrlock(&pwrpriv->lock); + + DBG_871X("%s done in %d ms\n", __FUNCTION__, rtw_get_passing_time_ms(start)); + pdbgpriv->dbg_sreset_cnt++; +#endif +} + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_sta_mgt.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_sta_mgt.c new file mode 100644 index 000000000..68eda779d --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_sta_mgt.c @@ -0,0 +1,1017 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_STA_MGT_C_ + +#include + +#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) + +#error "Shall be Linux or Windows, but not both!\n" + +#endif + + +bool test_st_match_rule(_adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port) +{ + if (ntohs(*((u16 *)local_port)) == 5001 || ntohs(*((u16 *)remote_port)) == 5001) + return _TRUE; + return _FALSE; +} + +struct st_register test_st_reg = { + .s_proto = 0x06, + .rule = test_st_match_rule, +}; + +inline void rtw_st_ctl_init(struct st_ctl_t *st_ctl) +{ + _rtw_memset(st_ctl->reg, 0 , sizeof(struct st_register) * SESSION_TRACKER_REG_ID_NUM); + _rtw_init_queue(&st_ctl->tracker_q); +} + +inline void rtw_st_ctl_clear_tracker_q(struct st_ctl_t *st_ctl) +{ + _irqL irqL; + _list *plist, *phead; + struct session_tracker *st; + + _enter_critical_bh(&st_ctl->tracker_q.lock, &irqL); + phead = &st_ctl->tracker_q.queue; + plist = get_next(phead); + while (rtw_end_of_queue_search(phead, plist) == _FALSE) { + st = LIST_CONTAINOR(plist, struct session_tracker, list); + plist = get_next(plist); + rtw_list_delete(&st->list); + rtw_mfree((u8 *)st, sizeof(struct session_tracker)); + } + _exit_critical_bh(&st_ctl->tracker_q.lock, &irqL); +} + +inline void rtw_st_ctl_deinit(struct st_ctl_t *st_ctl) +{ + rtw_st_ctl_clear_tracker_q(st_ctl); + _rtw_deinit_queue(&st_ctl->tracker_q); +} + +inline void rtw_st_ctl_register(struct st_ctl_t *st_ctl, u8 st_reg_id, struct st_register *reg) +{ + if (st_reg_id >= SESSION_TRACKER_REG_ID_NUM) { + rtw_warn_on(1); + return; + } + + st_ctl->reg[st_reg_id].s_proto = reg->s_proto; + st_ctl->reg[st_reg_id].rule = reg->rule; +} + +inline void rtw_st_ctl_unregister(struct st_ctl_t *st_ctl, u8 st_reg_id) +{ + int i; + + if (st_reg_id >= SESSION_TRACKER_REG_ID_NUM) { + rtw_warn_on(1); + return; + } + + st_ctl->reg[st_reg_id].s_proto = 0; + st_ctl->reg[st_reg_id].rule = NULL; + + /* clear tracker queue if no session trecker registered */ + for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++) + if (st_ctl->reg[i].s_proto != 0) + break; + if (i >= SESSION_TRACKER_REG_ID_NUM) + rtw_st_ctl_clear_tracker_q(st_ctl); +} + +inline bool rtw_st_ctl_chk_reg_s_proto(struct st_ctl_t *st_ctl, u8 s_proto) +{ + bool ret = _FALSE; + int i; + + for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++) { + if (st_ctl->reg[i].s_proto == s_proto) { + ret = _TRUE; + break; + } + } + + return ret; +} + +inline bool rtw_st_ctl_chk_reg_rule(struct st_ctl_t *st_ctl, _adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port) +{ + bool ret = _FALSE; + int i; + st_match_rule rule; + + for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++) { + rule = st_ctl->reg[i].rule; + if (rule && rule(adapter, local_naddr, local_port, remote_naddr, remote_port) == _TRUE) { + ret = _TRUE; + break; + } + } + + return ret; +} + +#define SESSION_TRACKER_FMT IP_FMT":"PORT_FMT" "IP_FMT":"PORT_FMT" %u %d" +#define SESSION_TRACKER_ARG(st) IP_ARG(&(st)->local_naddr), PORT_ARG(&(st)->local_port), IP_ARG(&(st)->remote_naddr), PORT_ARG(&(st)->remote_port), (st)->status, rtw_get_passing_time_ms((st)->set_time) + +void dump_st_ctl(void *sel, struct st_ctl_t *st_ctl) +{ + int i; + _irqL irqL; + _list *plist, *phead; + struct session_tracker *st; + + if (!DBG_SESSION_TRACKER) + return; + + for (i = 0; i < SESSION_TRACKER_REG_ID_NUM; i++) + DBG_871X_SEL_NL(sel, "reg%d: %u %p\n", i, st_ctl->reg[i].s_proto, st_ctl->reg[i].rule); + + _enter_critical_bh(&st_ctl->tracker_q.lock, &irqL); + phead = &st_ctl->tracker_q.queue; + plist = get_next(phead); + while (rtw_end_of_queue_search(phead, plist) == _FALSE) { + st = LIST_CONTAINOR(plist, struct session_tracker, list); + plist = get_next(plist); + + DBG_871X_SEL_NL(sel, SESSION_TRACKER_FMT"\n", SESSION_TRACKER_ARG(st)); + } + _exit_critical_bh(&st_ctl->tracker_q.lock, &irqL); + +} + +void _rtw_init_stainfo(struct sta_info *psta); +void _rtw_init_stainfo(struct sta_info *psta) +{ + +_func_enter_; + + _rtw_memset((u8 *)psta, 0, sizeof (struct sta_info)); + + _rtw_spinlock_init(&psta->lock); + _rtw_init_listhead(&psta->list); + _rtw_init_listhead(&psta->hash_list); + //_rtw_init_listhead(&psta->asoc_list); + //_rtw_init_listhead(&psta->sleep_list); + //_rtw_init_listhead(&psta->wakeup_list); + + _rtw_init_queue(&psta->sleep_q); + psta->sleepq_len = 0; + + _rtw_init_sta_xmit_priv(&psta->sta_xmitpriv); + _rtw_init_sta_recv_priv(&psta->sta_recvpriv); + +#ifdef CONFIG_AP_MODE + + _rtw_init_listhead(&psta->asoc_list); + + _rtw_init_listhead(&psta->auth_list); + + psta->expire_to = 0; + + psta->flags = 0; + + psta->capability = 0; + + psta->bpairwise_key_installed = _FALSE; + + +#ifdef CONFIG_NATIVEAP_MLME + psta->nonerp_set = 0; + psta->no_short_slot_time_set = 0; + psta->no_short_preamble_set = 0; + psta->no_ht_gf_set = 0; + psta->no_ht_set = 0; + psta->ht_20mhz_set = 0; + psta->ht_40mhz_intolerant = 0; +#endif + +#ifdef CONFIG_TX_MCAST2UNI + psta->under_exist_checking = 0; +#endif // CONFIG_TX_MCAST2UNI + + psta->keep_alive_trycnt = 0; + +#endif // CONFIG_AP_MODE + + rtw_st_ctl_init(&psta->st_ctl); + +_func_exit_; + +} + +u32 _rtw_init_sta_priv(struct sta_priv *pstapriv) +{ + struct sta_info *psta; + s32 i; + +_func_enter_; + + pstapriv->pallocated_stainfo_buf = rtw_zvmalloc (sizeof(struct sta_info) * NUM_STA+ 4); + + if(!pstapriv->pallocated_stainfo_buf) + return _FAIL; + + pstapriv->pstainfo_buf = pstapriv->pallocated_stainfo_buf + 4 - + ((SIZE_PTR)(pstapriv->pallocated_stainfo_buf ) & 3); + + _rtw_init_queue(&pstapriv->free_sta_queue); + + _rtw_spinlock_init(&pstapriv->sta_hash_lock); + + //_rtw_init_queue(&pstapriv->asoc_q); + pstapriv->asoc_sta_count = 0; + _rtw_init_queue(&pstapriv->sleep_q); + _rtw_init_queue(&pstapriv->wakeup_q); + + psta = (struct sta_info *)(pstapriv->pstainfo_buf); + + + for(i = 0; i < NUM_STA; i++) + { + _rtw_init_stainfo(psta); + + _rtw_init_listhead(&(pstapriv->sta_hash[i])); + + rtw_list_insert_tail(&psta->list, get_list_head(&pstapriv->free_sta_queue)); + + psta++; + } + + pstapriv->adhoc_expire_to = 4; /* 4 * 2 = 8 sec */ + +#ifdef CONFIG_AP_MODE + + pstapriv->sta_dz_bitmap = 0; + pstapriv->tim_bitmap = 0; + + _rtw_init_listhead(&pstapriv->asoc_list); + _rtw_init_listhead(&pstapriv->auth_list); + _rtw_spinlock_init(&pstapriv->asoc_list_lock); + _rtw_spinlock_init(&pstapriv->auth_list_lock); + pstapriv->asoc_list_cnt = 0; + pstapriv->auth_list_cnt = 0; + + pstapriv->auth_to = 3; // 3*2 = 6 sec + pstapriv->assoc_to = 3; + //pstapriv->expire_to = 900;// 900*2 = 1800 sec = 30 min, expire after no any traffic. + //pstapriv->expire_to = 30;// 30*2 = 60 sec = 1 min, expire after no any traffic. +#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK + pstapriv->expire_to = 3; // 3*2 = 6 sec +#else + pstapriv->expire_to = 60;// 60*2 = 120 sec = 2 min, expire after no any traffic. +#endif +#ifdef CONFIG_ATMEL_RC_PATCH + _rtw_memset( pstapriv->atmel_rc_pattern, 0, ETH_ALEN); +#endif + pstapriv->max_num_sta = NUM_STA; + +#endif + +_func_exit_; + + return _SUCCESS; + +} + +inline int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta) +{ + int offset = (((u8 *)sta) - stapriv->pstainfo_buf)/sizeof(struct sta_info); + + if (!stainfo_offset_valid(offset)) + DBG_871X("%s invalid offset(%d), out of range!!!", __func__, offset); + + return offset; +} + +inline struct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int offset) +{ + if (!stainfo_offset_valid(offset)) + DBG_871X("%s invalid offset(%d), out of range!!!", __func__, offset); + + return (struct sta_info *)(stapriv->pstainfo_buf + offset * sizeof(struct sta_info)); +} + +void _rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv); +void _rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv) +{ +_func_enter_; + + _rtw_spinlock_free(&psta_xmitpriv->lock); + + _rtw_spinlock_free(&(psta_xmitpriv->be_q.sta_pending.lock)); + _rtw_spinlock_free(&(psta_xmitpriv->bk_q.sta_pending.lock)); + _rtw_spinlock_free(&(psta_xmitpriv->vi_q.sta_pending.lock)); + _rtw_spinlock_free(&(psta_xmitpriv->vo_q.sta_pending.lock)); +_func_exit_; +} + +static void _rtw_free_sta_recv_priv_lock(struct sta_recv_priv *psta_recvpriv) +{ +_func_enter_; + + _rtw_spinlock_free(&psta_recvpriv->lock); + + _rtw_spinlock_free(&(psta_recvpriv->defrag_q.lock)); + +_func_exit_; + +} + +void rtw_mfree_stainfo(struct sta_info *psta); +void rtw_mfree_stainfo(struct sta_info *psta) +{ +_func_enter_; + + if(&psta->lock != NULL) + _rtw_spinlock_free(&psta->lock); + + _rtw_free_sta_xmit_priv_lock(&psta->sta_xmitpriv); + _rtw_free_sta_recv_priv_lock(&psta->sta_recvpriv); + +_func_exit_; +} + + +// this function is used to free the memory of lock || sema for all stainfos +void rtw_mfree_all_stainfo(struct sta_priv *pstapriv ); +void rtw_mfree_all_stainfo(struct sta_priv *pstapriv ) +{ + _irqL irqL; + _list *plist, *phead; + struct sta_info *psta = NULL; + +_func_enter_; + + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + phead = get_list_head(&pstapriv->free_sta_queue); + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) + { + psta = LIST_CONTAINOR(plist, struct sta_info ,list); + plist = get_next(plist); + + rtw_mfree_stainfo(psta); + } + + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + +_func_exit_; + +} + +void rtw_mfree_sta_priv_lock(struct sta_priv *pstapriv); +void rtw_mfree_sta_priv_lock(struct sta_priv *pstapriv) +{ +#ifdef CONFIG_AP_MODE + struct wlan_acl_pool *pacl_list = &pstapriv->acl_list; +#endif + + rtw_mfree_all_stainfo(pstapriv); //be done before free sta_hash_lock + + _rtw_spinlock_free(&pstapriv->free_sta_queue.lock); + + _rtw_spinlock_free(&pstapriv->sta_hash_lock); + _rtw_spinlock_free(&pstapriv->wakeup_q.lock); + _rtw_spinlock_free(&pstapriv->sleep_q.lock); + +#ifdef CONFIG_AP_MODE + _rtw_spinlock_free(&pstapriv->asoc_list_lock); + _rtw_spinlock_free(&pstapriv->auth_list_lock); + _rtw_spinlock_free(&pacl_list->acl_node_q.lock); +#endif + +} + +u32 _rtw_free_sta_priv(struct sta_priv *pstapriv) +{ + _irqL irqL; + _list *phead, *plist; + struct sta_info *psta = NULL; + struct recv_reorder_ctrl *preorder_ctrl; + int index; + +_func_enter_; + if(pstapriv){ + + /* delete all reordering_ctrl_timer */ + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + for(index = 0; index < NUM_STA; index++) + { + phead = &(pstapriv->sta_hash[index]); + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) + { + int i; + psta = LIST_CONTAINOR(plist, struct sta_info ,hash_list); + plist = get_next(plist); + + for(i=0; i < 16 ; i++) + { + preorder_ctrl = &psta->recvreorder_ctrl[i]; + _cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer); + } + } + } + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + /*===============================*/ + + rtw_mfree_sta_priv_lock(pstapriv); + + if(pstapriv->pallocated_stainfo_buf) { + rtw_vmfree(pstapriv->pallocated_stainfo_buf, sizeof(struct sta_info)*NUM_STA+4); + } + } + +_func_exit_; + return _SUCCESS; +} + + +//struct sta_info *rtw_alloc_stainfo(_queue *pfree_sta_queue, unsigned char *hwaddr) +struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr) +{ + _irqL irqL, irqL2; + uint tmp_aid; + s32 index; + _list *phash_list; + struct sta_info *psta; + _queue *pfree_sta_queue; + struct recv_reorder_ctrl *preorder_ctrl; + int i = 0; + u16 wRxSeqInitialValue = 0xffff; + +_func_enter_; + + pfree_sta_queue = &pstapriv->free_sta_queue; + + //_enter_critical_bh(&(pfree_sta_queue->lock), &irqL); + _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); + if (_rtw_queue_empty(pfree_sta_queue) == _TRUE) + { + //_exit_critical_bh(&(pfree_sta_queue->lock), &irqL); + _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); + psta = NULL; + } + else + { + psta = LIST_CONTAINOR(get_next(&pfree_sta_queue->queue), struct sta_info, list); + + rtw_list_delete(&(psta->list)); + + //_exit_critical_bh(&(pfree_sta_queue->lock), &irqL); + + tmp_aid = psta->aid; + + _rtw_init_stainfo(psta); + + psta->padapter = pstapriv->padapter; + + _rtw_memcpy(psta->hwaddr, hwaddr, ETH_ALEN); + + index = wifi_mac_hash(hwaddr); + + RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_info_,("rtw_alloc_stainfo: index = %x", index)); + + if(index >= NUM_STA){ + RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_err_,("ERROR=> rtw_alloc_stainfo: index >= NUM_STA")); + psta= NULL; + goto exit; + } + phash_list = &(pstapriv->sta_hash[index]); + + //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); + + rtw_list_insert_tail(&psta->hash_list, phash_list); + + pstapriv->asoc_sta_count ++ ; + + //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); + +// Commented by Albert 2009/08/13 +// For the SMC router, the sequence number of first packet of WPS handshake will be 0. +// In this case, this packet will be dropped by recv_decache function if we use the 0x00 as the default value for tid_rxseq variable. +// So, we initialize the tid_rxseq variable as the 0xffff. + + for( i = 0; i < 16; i++ ) + { + _rtw_memcpy( &psta->sta_recvpriv.rxcache.tid_rxseq[ i ], &wRxSeqInitialValue, 2 ); + } + + RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_info_,("alloc number_%d stainfo with hwaddr = %x %x %x %x %x %x \n", + pstapriv->asoc_sta_count , hwaddr[0], hwaddr[1], hwaddr[2],hwaddr[3],hwaddr[4],hwaddr[5])); + + init_addba_retry_timer(pstapriv->padapter, psta); +#ifdef CONFIG_IEEE80211W + init_dot11w_expire_timer(pstapriv->padapter, psta); +#endif /* CONFIG_IEEE80211W */ +#ifdef CONFIG_TDLS + rtw_init_tdls_timer(pstapriv->padapter, psta); +#endif //CONFIG_TDLS + + //for A-MPDU Rx reordering buffer control + for(i=0; i < 16 ; i++) + { + preorder_ctrl = &psta->recvreorder_ctrl[i]; + + preorder_ctrl->padapter = pstapriv->padapter; + + preorder_ctrl->enable = _FALSE; + + preorder_ctrl->indicate_seq = 0xffff; + #ifdef DBG_RX_SEQ + DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d\n", __FUNCTION__, __LINE__, + preorder_ctrl->indicate_seq); + #endif + preorder_ctrl->wend_b= 0xffff; + //preorder_ctrl->wsize_b = (NR_RECVBUFF-2); + preorder_ctrl->wsize_b = 64;//64; + preorder_ctrl->ampdu_size = RX_AMPDU_SIZE_INVALID; + + _rtw_init_queue(&preorder_ctrl->pending_recvframe_queue); + + rtw_init_recv_timer(preorder_ctrl); + } + + + //init for DM + psta->rssi_stat.UndecoratedSmoothedPWDB = (-1); + psta->rssi_stat.UndecoratedSmoothedCCK = (-1); +#ifdef CONFIG_ATMEL_RC_PATCH + psta->flag_atmel_rc = 0; +#endif + /* init for the sequence number of received management frame */ + psta->RxMgmtFrameSeqNum = 0xffff; + psta->ra_rpt_linked = _FALSE; + + //alloc mac id for non-bc/mc station, + rtw_alloc_macid(pstapriv->padapter, psta); + + } + +exit: + + _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); + +_func_exit_; + + return psta; + + +} + + +// using pstapriv->sta_hash_lock to protect +u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta) +{ + int i; + _irqL irqL0; + _queue *pfree_sta_queue; + struct recv_reorder_ctrl *preorder_ctrl; + struct sta_xmit_priv *pstaxmitpriv; + struct xmit_priv *pxmitpriv= &padapter->xmitpriv; + struct sta_priv *pstapriv = &padapter->stapriv; + struct hw_xmit *phwxmit; + int pending_qcnt[4]; + +_func_enter_; + + if (psta == NULL) + goto exit; + + _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0); + rtw_list_delete(&psta->hash_list); + RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_err_,("\n free number_%d stainfo with hwaddr = 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x \n",pstapriv->asoc_sta_count , psta->hwaddr[0], psta->hwaddr[1], psta->hwaddr[2],psta->hwaddr[3],psta->hwaddr[4],psta->hwaddr[5])); + pstapriv->asoc_sta_count --; + _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0); + + + _enter_critical_bh(&psta->lock, &irqL0); + psta->state &= ~_FW_LINKED; + _exit_critical_bh(&psta->lock, &irqL0); + + pfree_sta_queue = &pstapriv->free_sta_queue; + + + pstaxmitpriv = &psta->sta_xmitpriv; + + //rtw_list_delete(&psta->sleep_list); + + //rtw_list_delete(&psta->wakeup_list); + + _enter_critical_bh(&pxmitpriv->lock, &irqL0); + + rtw_free_xmitframe_queue(pxmitpriv, &psta->sleep_q); + psta->sleepq_len = 0; + + //vo + //_enter_critical_bh(&(pxmitpriv->vo_pending.lock), &irqL0); + rtw_free_xmitframe_queue( pxmitpriv, &pstaxmitpriv->vo_q.sta_pending); + rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending)); + phwxmit = pxmitpriv->hwxmits; + phwxmit->accnt -= pstaxmitpriv->vo_q.qcnt; + pending_qcnt[0] = pstaxmitpriv->vo_q.qcnt; + pstaxmitpriv->vo_q.qcnt = 0; + //_exit_critical_bh(&(pxmitpriv->vo_pending.lock), &irqL0); + + //vi + //_enter_critical_bh(&(pxmitpriv->vi_pending.lock), &irqL0); + rtw_free_xmitframe_queue( pxmitpriv, &pstaxmitpriv->vi_q.sta_pending); + rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending)); + phwxmit = pxmitpriv->hwxmits+1; + phwxmit->accnt -= pstaxmitpriv->vi_q.qcnt; + pending_qcnt[1] = pstaxmitpriv->vi_q.qcnt; + pstaxmitpriv->vi_q.qcnt = 0; + //_exit_critical_bh(&(pxmitpriv->vi_pending.lock), &irqL0); + + //be + //_enter_critical_bh(&(pxmitpriv->be_pending.lock), &irqL0); + rtw_free_xmitframe_queue( pxmitpriv, &pstaxmitpriv->be_q.sta_pending); + rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending)); + phwxmit = pxmitpriv->hwxmits+2; + phwxmit->accnt -= pstaxmitpriv->be_q.qcnt; + pending_qcnt[2] = pstaxmitpriv->be_q.qcnt; + pstaxmitpriv->be_q.qcnt = 0; + //_exit_critical_bh(&(pxmitpriv->be_pending.lock), &irqL0); + + //bk + //_enter_critical_bh(&(pxmitpriv->bk_pending.lock), &irqL0); + rtw_free_xmitframe_queue( pxmitpriv, &pstaxmitpriv->bk_q.sta_pending); + rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending)); + phwxmit = pxmitpriv->hwxmits+3; + phwxmit->accnt -= pstaxmitpriv->bk_q.qcnt; + pending_qcnt[3] = pstaxmitpriv->bk_q.qcnt; + pstaxmitpriv->bk_q.qcnt = 0; + //_exit_critical_bh(&(pxmitpriv->bk_pending.lock), &irqL0); + + rtw_os_wake_queue_at_free_stainfo(padapter, pending_qcnt); + + _exit_critical_bh(&pxmitpriv->lock, &irqL0); + + + // re-init sta_info; 20061114 // will be init in alloc_stainfo + //_rtw_init_sta_xmit_priv(&psta->sta_xmitpriv); + //_rtw_init_sta_recv_priv(&psta->sta_recvpriv); +#ifdef CONFIG_IEEE80211W + _cancel_timer_ex(&psta->dot11w_expire_timer); +#endif /* CONFIG_IEEE80211W */ + _cancel_timer_ex(&psta->addba_retry_timer); + +#ifdef CONFIG_TDLS + psta->tdls_sta_state = TDLS_STATE_NONE; + rtw_free_tdls_timer(psta); +#endif //CONFIG_TDLS + + //for A-MPDU Rx reordering buffer control, cancel reordering_ctrl_timer + for(i=0; i < 16 ; i++) + { + _irqL irqL; + _list *phead, *plist; + union recv_frame *prframe; + _queue *ppending_recvframe_queue; + _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue; + + preorder_ctrl = &psta->recvreorder_ctrl[i]; + + _cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer); + + + ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; + + _enter_critical_bh(&ppending_recvframe_queue->lock, &irqL); + + phead = get_list_head(ppending_recvframe_queue); + plist = get_next(phead); + + while(!rtw_is_list_empty(phead)) + { + prframe = LIST_CONTAINOR(plist, union recv_frame, u); + + plist = get_next(plist); + + rtw_list_delete(&(prframe->u.hdr.list)); + + rtw_free_recvframe(prframe, pfree_recv_queue); + } + + _exit_critical_bh(&ppending_recvframe_queue->lock, &irqL); + + } + + if (!(psta->state & WIFI_AP_STATE)) + rtw_hal_set_odm_var(padapter, HAL_ODM_STA_INFO, psta, _FALSE); + + + //release mac id for non-bc/mc station, + rtw_release_macid(pstapriv->padapter, psta); + +#ifdef CONFIG_AP_MODE + +/* + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL0); + rtw_list_delete(&psta->asoc_list); + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL0); +*/ + _enter_critical_bh(&pstapriv->auth_list_lock, &irqL0); + if (!rtw_is_list_empty(&psta->auth_list)) { + rtw_list_delete(&psta->auth_list); + pstapriv->auth_list_cnt--; + } + _exit_critical_bh(&pstapriv->auth_list_lock, &irqL0); + + psta->expire_to = 0; +#ifdef CONFIG_ATMEL_RC_PATCH + psta->flag_atmel_rc = 0; +#endif + psta->sleepq_ac_len = 0; + psta->qos_info = 0; + + psta->max_sp_len = 0; + psta->uapsd_bk = 0; + psta->uapsd_be = 0; + psta->uapsd_vi = 0; + psta->uapsd_vo = 0; + + psta->has_legacy_ac = 0; + +#ifdef CONFIG_NATIVEAP_MLME + + pstapriv->sta_dz_bitmap &=~BIT(psta->aid); + pstapriv->tim_bitmap &=~BIT(psta->aid); + + //rtw_indicate_sta_disassoc_event(padapter, psta); + + if ((psta->aid >0)&&(pstapriv->sta_aid[psta->aid - 1] == psta)) + { + pstapriv->sta_aid[psta->aid - 1] = NULL; + psta->aid = 0; + } + +#endif // CONFIG_NATIVEAP_MLME + +#ifdef CONFIG_TX_MCAST2UNI + psta->under_exist_checking = 0; +#endif // CONFIG_TX_MCAST2UNI + +#endif // CONFIG_AP_MODE + + rtw_st_ctl_deinit(&psta->st_ctl); + + _rtw_spinlock_free(&psta->lock); + + //_enter_critical_bh(&(pfree_sta_queue->lock), &irqL0); + _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL0); + rtw_list_insert_tail(&psta->list, get_list_head(pfree_sta_queue)); + _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL0); + //_exit_critical_bh(&(pfree_sta_queue->lock), &irqL0); + +exit: + +_func_exit_; + + return _SUCCESS; + +} + +// free all stainfo which in sta_hash[all] +void rtw_free_all_stainfo(_adapter *padapter) +{ + _irqL irqL; + _list *plist, *phead; + s32 index; + struct sta_info *psta = NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info* pbcmc_stainfo =rtw_get_bcmc_stainfo( padapter); + u8 free_sta_num = 0; + char free_sta_list[NUM_STA]; + int stainfo_offset; + +_func_enter_; + + if(pstapriv->asoc_sta_count==1) + goto exit; + + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + for(index=0; index< NUM_STA; index++) + { + phead = &(pstapriv->sta_hash[index]); + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) + { + psta = LIST_CONTAINOR(plist, struct sta_info ,hash_list); + + plist = get_next(plist); + + if(pbcmc_stainfo!=psta) + { + rtw_list_delete(&psta->hash_list); + //rtw_free_stainfo(padapter , psta); + stainfo_offset = rtw_stainfo_offset(pstapriv, psta); + if (stainfo_offset_valid(stainfo_offset)) { + free_sta_list[free_sta_num++] = stainfo_offset; + } + } + + } + } + + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + + for (index = 0; index < free_sta_num; index++) + { + psta = rtw_get_stainfo_by_offset(pstapriv, free_sta_list[index]); + rtw_free_stainfo(padapter , psta); + } + +exit: + +_func_exit_; + +} + +/* any station allocated can be searched by hash list */ +struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr) +{ + + _irqL irqL; + + _list *plist, *phead; + + struct sta_info *psta = NULL; + + u32 index; + + const u8 *addr; + + const u8 bc_addr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + +_func_enter_; + + if(hwaddr==NULL) + return NULL; + + if (IS_MCAST((unsigned char *)hwaddr)) + addr = bc_addr; + else + addr = hwaddr; + + index = wifi_mac_hash(addr); + + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + phead = &(pstapriv->sta_hash[index]); + plist = get_next(phead); + + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) + { + + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + + if ((_rtw_memcmp(psta->hwaddr, addr, ETH_ALEN))== _TRUE) + { // if found the matched address + break; + } + psta=NULL; + plist = get_next(plist); + } + + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); +_func_exit_; + return psta; + +} + +u32 rtw_init_bcmc_stainfo(_adapter* padapter) +{ + + struct sta_info *psta; + struct tx_servq *ptxservq; + u32 res=_SUCCESS; + NDIS_802_11_MAC_ADDRESS bcast_addr= {0xff,0xff,0xff,0xff,0xff,0xff}; + + struct sta_priv *pstapriv = &padapter->stapriv; + //_queue *pstapending = &padapter->xmitpriv.bm_pending; + +_func_enter_; + + psta = rtw_alloc_stainfo(pstapriv, bcast_addr); + + if(psta==NULL){ + res=_FAIL; + RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_err_,("rtw_alloc_stainfo fail")); + goto exit; + } +#ifdef CONFIG_BEAMFORMING + psta->txbf_gid = 63; + psta->txbf_paid = 0; +#endif + ptxservq= &(psta->sta_xmitpriv.be_q); + +/* + _enter_critical(&pstapending->lock, &irqL0); + + if (rtw_is_list_empty(&ptxservq->tx_pending)) + rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(pstapending)); + + _exit_critical(&pstapending->lock, &irqL0); +*/ + +exit: +_func_exit_; + return _SUCCESS; + +} + + +struct sta_info* rtw_get_bcmc_stainfo(_adapter* padapter) +{ + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff}; +_func_enter_; + psta = rtw_get_stainfo(pstapriv, bc_addr); +_func_exit_; + return psta; + +} + +u8 rtw_access_ctrl(_adapter *padapter, u8 *mac_addr) +{ + u8 res = _TRUE; +#ifdef CONFIG_AP_MODE + _irqL irqL; + _list *plist, *phead; + struct rtw_wlan_acl_node *paclnode; + u8 match = _FALSE; + struct sta_priv *pstapriv = &padapter->stapriv; + struct wlan_acl_pool *pacl_list = &pstapriv->acl_list; + _queue *pacl_node_q =&pacl_list->acl_node_q; + + _enter_critical_bh(&(pacl_node_q->lock), &irqL); + phead = get_list_head(pacl_node_q); + plist = get_next(phead); + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) + { + paclnode = LIST_CONTAINOR(plist, struct rtw_wlan_acl_node, list); + plist = get_next(plist); + + if(_rtw_memcmp(paclnode->addr, mac_addr, ETH_ALEN)) + { + if(paclnode->valid == _TRUE) + { + match = _TRUE; + break; + } + } + } + _exit_critical_bh(&(pacl_node_q->lock), &irqL); + + + if(pacl_list->mode == 1)//accept unless in deny list + { + res = (match == _TRUE) ? _FALSE:_TRUE; + } + else if(pacl_list->mode == 2)//deny unless in accept list + { + res = (match == _TRUE) ? _TRUE:_FALSE; + } + else + { + res = _TRUE; + } + +#endif + + return res; + +} + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_tdls.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_tdls.c new file mode 100644 index 000000000..984fd259d --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_tdls.c @@ -0,0 +1,3368 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_TDLS_C_ + +#include +#include + +#ifdef CONFIG_TDLS +#define ONE_SEC 1000 /* 1000 ms */ + +extern unsigned char MCS_rate_2R[16]; +extern unsigned char MCS_rate_1R[16]; +extern void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame); + +void rtw_reset_tdls_info(_adapter* padapter) +{ + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + + ptdlsinfo->ap_prohibited = _FALSE; + + /* For TDLS channel switch, currently we only allow it to work in wifi logo test mode */ + if (padapter->registrypriv.wifi_spec == 1) + { + ptdlsinfo->ch_switch_prohibited = _FALSE; + } + else + { + ptdlsinfo->ch_switch_prohibited = _TRUE; + } + + ptdlsinfo->link_established = _FALSE; + ptdlsinfo->sta_cnt = 0; + ptdlsinfo->sta_maximum = _FALSE; + +#ifdef CONFIG_TDLS_CH_SW + ptdlsinfo->chsw_info.ch_sw_state = TDLS_STATE_NONE; + ATOMIC_SET(&ptdlsinfo->chsw_info.chsw_on, _FALSE); + ptdlsinfo->chsw_info.off_ch_num = 0; + ptdlsinfo->chsw_info.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + ptdlsinfo->chsw_info.cur_time = 0; + ptdlsinfo->chsw_info.delay_switch_back = _FALSE; + ptdlsinfo->chsw_info.dump_stack = _FALSE; +#endif + + ptdlsinfo->ch_sensing = 0; + ptdlsinfo->watchdog_count = 0; + ptdlsinfo->dev_discovered = _FALSE; + +#ifdef CONFIG_WFD + ptdlsinfo->wfd_info = &padapter->wfd_info; +#endif +} + +int rtw_init_tdls_info(_adapter* padapter) +{ + int res = _SUCCESS; + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + + rtw_reset_tdls_info(padapter); + + ptdlsinfo->tdls_enable = _TRUE; +#ifdef CONFIG_TDLS_DRIVER_SETUP + ptdlsinfo->driver_setup = _TRUE; +#else + ptdlsinfo->driver_setup = _FALSE; +#endif /* CONFIG_TDLS_DRIVER_SETUP */ + + _rtw_spinlock_init(&ptdlsinfo->cmd_lock); + _rtw_spinlock_init(&ptdlsinfo->hdl_lock); + + return res; + +} + +void rtw_free_tdls_info(struct tdls_info *ptdlsinfo) +{ + _rtw_spinlock_free(&ptdlsinfo->cmd_lock); + _rtw_spinlock_free(&ptdlsinfo->hdl_lock); + + _rtw_memset(ptdlsinfo, 0, sizeof(struct tdls_info) ); + +} + +int check_ap_tdls_prohibited(u8 *pframe, u8 pkt_len) +{ + u8 tdls_prohibited_bit = 0x40; /* bit(38); TDLS_prohibited */ + + if (pkt_len < 5) { + return _FALSE; + } + + pframe += 4; + if ((*pframe) & tdls_prohibited_bit) + return _TRUE; + + return _FALSE; +} + +int check_ap_tdls_ch_switching_prohibited(u8 *pframe, u8 pkt_len) +{ + u8 tdls_ch_swithcing_prohibited_bit = 0x80; /* bit(39); TDLS_channel_switching prohibited */ + + if (pkt_len < 5) { + return _FALSE; + } + + pframe += 4; + if ((*pframe) & tdls_ch_swithcing_prohibited_bit) + return _TRUE; + + return _FALSE; +} + +u8 rtw_tdls_is_setup_allowed(_adapter *padapter) +{ + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + + if (ptdlsinfo->ap_prohibited == _TRUE) + return _FALSE; + + return _TRUE; +} + +#ifdef CONFIG_TDLS_CH_SW +u8 rtw_tdls_is_chsw_allowed(_adapter *padapter) +{ + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + + if (ptdlsinfo->ch_switch_prohibited == _TRUE) + return _FALSE; + + if (padapter->registrypriv.wifi_spec == 0) + return _FALSE; + + return _TRUE; +} +#endif + +int _issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsigned int power_mode, int wait_ack) +{ + int ret = _FAIL; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl, *qc; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + goto exit; + + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + pattrib->hdrlen +=2; + pattrib->qos_en = _TRUE; + pattrib->eosp = 1; + pattrib->ack_policy = 0; + pattrib->mdata = 0; + pattrib->retry_ctrl = _FALSE; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + if (power_mode) + SetPwrMgt(fctrl); + + qc = (unsigned short *)(pframe + pattrib->hdrlen - 2); + + SetPriority(qc, 7); /* Set priority to VO */ + + SetEOSP(qc, pattrib->eosp); + + SetAckpolicy(qc, pattrib->ack_policy); + + _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(pframe, WIFI_QOS_DATA_NULL); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr_qos); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos); + + pattrib->last_txcmdsz = pattrib->pktlen; + + if (wait_ack) + ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); + else { + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + } + +exit: + return ret; + +} + +/* + *wait_ms == 0 means that there is no need to wait ack through C2H_CCX_TX_RPT + *wait_ms > 0 means you want to wait ack through C2H_CCX_TX_RPT, and the value of wait_ms means the interval between each TX + *try_cnt means the maximal TX count to try + */ +int issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms) +{ + int ret; + int i = 0; + u32 start = rtw_get_current_time(); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + #if 0 + psta = rtw_get_stainfo(&padapter->stapriv, da); + if (psta) { + if (power_mode) + rtw_hal_macid_sleep(padapter, psta->mac_id); + else + rtw_hal_macid_wakeup(padapter, psta->mac_id); + } else { + DBG_871X(FUNC_ADPT_FMT ": Can't find sta info for " MAC_FMT ", skip macid %s!!\n", + FUNC_ADPT_ARG(padapter), MAC_ARG(da), power_mode?"sleep":"wakeup"); + rtw_warn_on(1); + } + #endif + + do { + ret = _issue_nulldata_to_TDLS_peer_STA(padapter, da, power_mode, wait_ms>0 ? _TRUE : _FALSE); + + i++; + + if (RTW_CANNOT_RUN(padapter)) + break; + + if (i < try_cnt && wait_ms > 0 && ret == _FAIL) + rtw_msleep_os(wait_ms); + + } while ((i < try_cnt) && (ret==_FAIL || wait_ms==0)); + + if (ret != _FAIL) { + ret = _SUCCESS; + #ifndef DBG_XMIT_ACK + goto exit; + #endif + } + + if (try_cnt && wait_ms) { + if (da) + DBG_871X(FUNC_ADPT_FMT" to "MAC_FMT", ch:%u%s, %d/%d in %u ms\n", + FUNC_ADPT_ARG(padapter), MAC_ARG(da), rtw_get_oper_ch(padapter), + ret==_SUCCESS?", acked":"", i, try_cnt, rtw_get_passing_time_ms(start)); + else + DBG_871X(FUNC_ADPT_FMT", ch:%u%s, %d/%d in %u ms\n", + FUNC_ADPT_ARG(padapter), rtw_get_oper_ch(padapter), + ret==_SUCCESS?", acked":"", i, try_cnt, rtw_get_passing_time_ms(start)); + } +exit: + return ret; +} + +void free_tdls_sta(_adapter *padapter, struct sta_info *ptdls_sta) +{ + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + struct sta_priv *pstapriv = &padapter->stapriv; + _irqL irqL; + + /* free peer sta_info */ + _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + if (ptdlsinfo->sta_cnt != 0) + ptdlsinfo->sta_cnt--; + _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + /* -2: AP + BC/MC sta, -4: default key */ + if (ptdlsinfo->sta_cnt < MAX_ALLOWED_TDLS_STA_NUM) { + ptdlsinfo->sta_maximum = _FALSE; + _rtw_memset( &ptdlsinfo->ss_record, 0x00, sizeof(struct tdls_ss_record) ); + } + + /* clear cam */ + rtw_clearstakey_cmd(padapter, ptdls_sta, _TRUE); + + if (ptdlsinfo->sta_cnt == 0) { + rtw_tdls_cmd(padapter, NULL, TDLS_RS_RCR); + ptdlsinfo->link_established = _FALSE; + } + else + DBG_871X("Remain tdls sta:%02x\n", ptdlsinfo->sta_cnt); + + rtw_free_stainfo(padapter, ptdls_sta); + +} + + +/* TDLS encryption(if needed) will always be CCMP */ +void rtw_tdls_set_key(_adapter *padapter, struct sta_info *ptdls_sta) +{ + ptdls_sta->dot118021XPrivacy=_AES_; + rtw_setstakey_cmd(padapter, ptdls_sta, TDLS_KEY, _TRUE); +} + +#ifdef CONFIG_80211N_HT +void rtw_tdls_process_ht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct ht_priv *phtpriv = &pmlmepriv->htpriv; + u8 max_AMPDU_len, min_MPDU_spacing; + u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, cur_beamform_cap = 0; + + /* Save HT capabilities in the sta object */ + _rtw_memset(&ptdls_sta->htpriv.ht_cap, 0, sizeof(struct rtw_ieee80211_ht_cap)); + if (data && Length >= sizeof(struct rtw_ieee80211_ht_cap)) { + ptdls_sta->flags |= WLAN_STA_HT; + ptdls_sta->flags |= WLAN_STA_WME; + + _rtw_memcpy(&ptdls_sta->htpriv.ht_cap, data, sizeof(struct rtw_ieee80211_ht_cap)); + } else + ptdls_sta->flags &= ~WLAN_STA_HT; + + if (ptdls_sta->flags & WLAN_STA_HT) { + if (padapter->registrypriv.ht_enable == _TRUE) { + ptdls_sta->htpriv.ht_option = _TRUE; + ptdls_sta->qos_option = _TRUE; + } else { + ptdls_sta->htpriv.ht_option = _FALSE; + ptdls_sta->qos_option = _FALSE; + } + } + + /* HT related cap */ + if (ptdls_sta->htpriv.ht_option) { + /* Check if sta supports rx ampdu */ + if (padapter->registrypriv.ampdu_enable == 1) + ptdls_sta->htpriv.ampdu_enable = _TRUE; + + /* AMPDU Parameters field */ + /* Get MIN of MAX AMPDU Length Exp */ + if ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3) > (data[2] & 0x3)) + max_AMPDU_len = (data[2] & 0x3); + else + max_AMPDU_len = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3); + /* Get MAX of MIN MPDU Start Spacing */ + if ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) > (data[2] & 0x1c)) + min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c); + else + min_MPDU_spacing = (data[2] & 0x1c); + ptdls_sta->htpriv.rx_ampdu_min_spacing = max_AMPDU_len | min_MPDU_spacing; + + /* Check if sta support s Short GI 20M */ + if (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SGI_20)) + ptdls_sta->htpriv.sgi_20m = _TRUE; + + /* Check if sta support s Short GI 40M */ + if (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SGI_40)) + ptdls_sta->htpriv.sgi_40m = _TRUE; + + /* Bwmode would still followed AP's setting */ + if (ptdls_sta->htpriv.ht_cap.cap_info & cpu_to_le16(IEEE80211_HT_CAP_SUP_WIDTH)) { + if (padapter->mlmeextpriv.cur_bwmode >= CHANNEL_WIDTH_40) + ptdls_sta->bw_mode = CHANNEL_WIDTH_40; + ptdls_sta->htpriv.ch_offset = padapter->mlmeextpriv.cur_ch_offset; + } + + /* Config LDPC Coding Capability */ + if (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX) && GET_HT_CAP_ELE_LDPC_CAP(data)) { + SET_FLAG(cur_ldpc_cap, (LDPC_HT_ENABLE_TX | LDPC_HT_CAP_TX)); + DBG_871X("Enable HT Tx LDPC!\n"); + } + ptdls_sta->htpriv.ldpc_cap = cur_ldpc_cap; + + /* Config STBC setting */ + if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_RX_STBC(data)) { + SET_FLAG(cur_stbc_cap, (STBC_HT_ENABLE_TX | STBC_HT_CAP_TX)); + DBG_871X("Enable HT Tx STBC!\n"); + } + ptdls_sta->htpriv.stbc_cap = cur_stbc_cap; + +#ifdef CONFIG_BEAMFORMING + /* Config Tx beamforming setting */ + if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) && + GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(data)) { + SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE); + } + + if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) && + GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(data)) { + SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE); + } + ptdls_sta->htpriv.beamform_cap = cur_beamform_cap; + if (cur_beamform_cap) + DBG_871X("Client HT Beamforming Cap = 0x%02X\n", cur_beamform_cap); +#endif /* CONFIG_BEAMFORMING */ + } + +} + +u8 *rtw_tdls_set_ht_cap(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib) +{ + rtw_ht_use_default_setting(padapter); + + rtw_restructure_ht_ie(padapter, NULL, pframe, 0, &(pattrib->pktlen), padapter->mlmeextpriv.cur_channel); + + return pframe + pattrib->pktlen; +} +#endif + +#ifdef CONFIG_80211AC_VHT +void rtw_tdls_process_vht_cap(_adapter *padapter, struct sta_info *ptdls_sta, u8 *data, u8 Length) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, cur_beamform_cap = 0, rf_type = RF_1T1R; + u8 *pcap_mcs; + u8 vht_mcs[2]; + + _rtw_memset(&ptdls_sta->vhtpriv, 0, sizeof(struct vht_priv)); + if (data && Length == 12) { + ptdls_sta->flags |= WLAN_STA_VHT; + + _rtw_memcpy(ptdls_sta->vhtpriv.vht_cap, data, 12); + +#if 0 + if (elems.vht_op_mode_notify && elems.vht_op_mode_notify_len == 1) { + _rtw_memcpy(&pstat->vhtpriv.vht_op_mode_notify, elems.vht_op_mode_notify, 1); + } else /* for Frame without Operating Mode notify ie; default: 80M */ { + pstat->vhtpriv.vht_op_mode_notify = CHANNEL_WIDTH_80; + } +#else + ptdls_sta->vhtpriv.vht_op_mode_notify = CHANNEL_WIDTH_80; +#endif + } else + ptdls_sta->flags &= ~WLAN_STA_VHT; + + if (ptdls_sta->flags & WLAN_STA_VHT) { + if (REGSTY_IS_11AC_ENABLE(&padapter->registrypriv) + && hal_chk_proto_cap(padapter, PROTO_CAP_11AC) + && (!pmlmepriv->country_ent || COUNTRY_CHPLAN_EN_11AC(pmlmepriv->country_ent))) + ptdls_sta->vhtpriv.vht_option = _TRUE; + else + ptdls_sta->vhtpriv.vht_option = _FALSE; + } + + /* B4 Rx LDPC */ + if (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX) && + GET_VHT_CAPABILITY_ELE_RX_LDPC(data)) { + SET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX)); + DBG_871X("Current VHT LDPC Setting = %02X\n", cur_ldpc_cap); + } + ptdls_sta->vhtpriv.ldpc_cap = cur_ldpc_cap; + + /* B5 Short GI for 80 MHz */ + ptdls_sta->vhtpriv.sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(data) & pvhtpriv->sgi_80m) ? _TRUE : _FALSE; + + /* B8 B9 B10 Rx STBC */ + if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX) && + GET_VHT_CAPABILITY_ELE_RX_STBC(data)) { + SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX)); + DBG_871X("Current VHT STBC Setting = %02X\n", cur_stbc_cap); + } + ptdls_sta->vhtpriv.stbc_cap = cur_stbc_cap; + + /* B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee */ + if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) && + GET_VHT_CAPABILITY_ELE_SU_BFEE(data)) { + SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE); + } + + /* B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer */ + if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) && + GET_VHT_CAPABILITY_ELE_SU_BFER(data)) { + SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE); + } + ptdls_sta->vhtpriv.beamform_cap = cur_beamform_cap; + if (cur_beamform_cap) + DBG_871X("Current VHT Beamforming Setting = %02X\n", cur_beamform_cap); + + /* B23 B24 B25 Maximum A-MPDU Length Exponent */ + ptdls_sta->vhtpriv.ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(data); + + pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(data); + _rtw_memcpy(vht_mcs, pcap_mcs, 2); + + rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + if ((rf_type == RF_1T1R) || (rf_type == RF_1T2R)) + vht_mcs[0] |= 0xfc; + else if (rf_type == RF_2T2R) + vht_mcs[0] |= 0xf0; + else if (rf_type == RF_3T3R) + vht_mcs[0] |= 0xc0; + + _rtw_memcpy(ptdls_sta->vhtpriv.vht_mcs_map, vht_mcs, 2); + + ptdls_sta->vhtpriv.vht_highest_rate = rtw_get_vht_highest_rate(ptdls_sta->vhtpriv.vht_mcs_map); +} + +u8 *rtw_tdls_set_aid(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib) +{ + return rtw_set_ie(pframe, EID_AID, 2, (u8 *)&(padapter->mlmepriv.cur_network.aid), &(pattrib->pktlen)); +} + +u8 *rtw_tdls_set_vht_cap(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib) +{ + u32 ie_len = 0; + + rtw_vht_use_default_setting(padapter); + + ie_len = rtw_build_vht_cap_ie(padapter, pframe); + pattrib->pktlen += ie_len; + + return pframe + ie_len; +} + +u8 *rtw_tdls_set_vht_operation(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib, u8 channel) +{ + u32 ie_len = 0; + + ie_len = rtw_build_vht_operation_ie(padapter, pframe, channel); + pattrib->pktlen += ie_len; + + return pframe + ie_len; +} + +u8 *rtw_tdls_set_vht_op_mode_notify(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib, u8 bw) +{ + u32 ie_len = 0; + + ie_len = rtw_build_vht_op_mode_notify_ie(padapter, pframe, bw); + pattrib->pktlen += ie_len; + + return pframe + ie_len; +} +#endif + + +u8 *rtw_tdls_set_sup_ch(struct mlme_ext_priv *pmlmeext, u8 *pframe, struct pkt_attrib *pattrib) +{ + u8 sup_ch[30 * 2] = {0x00}, ch_set_idx = 0, sup_ch_idx = 2; + + do { + if (pmlmeext->channel_set[ch_set_idx].ChannelNum <= 14) { + sup_ch[0] = 1; /* First channel number */ + sup_ch[1] = pmlmeext->channel_set[ch_set_idx].ChannelNum; /* Number of channel */ + } else { + sup_ch[sup_ch_idx++] = pmlmeext->channel_set[ch_set_idx].ChannelNum; + sup_ch[sup_ch_idx++] = 1; + } + ch_set_idx++; + } while (pmlmeext->channel_set[ch_set_idx].ChannelNum != 0 && ch_set_idx < MAX_CHANNEL_NUM); + + return rtw_set_ie(pframe, _SUPPORTED_CH_IE_, sup_ch_idx, sup_ch, &(pattrib->pktlen)); +} + +u8 *rtw_tdls_set_rsnie(struct tdls_txmgmt *ptxmgmt, u8 *pframe, struct pkt_attrib *pattrib, int init, struct sta_info *ptdls_sta) +{ + u8 *p = NULL; + int len = 0; + + if (ptxmgmt->len > 0) + p = rtw_get_ie(ptxmgmt->buf, _RSN_IE_2_, &len, ptxmgmt->len); + + if (p != NULL) + return rtw_set_ie(pframe, _RSN_IE_2_, len, p+2, &(pattrib->pktlen)); + else + if (init == _TRUE) + return rtw_set_ie(pframe, _RSN_IE_2_, sizeof(TDLS_RSNIE), TDLS_RSNIE, &(pattrib->pktlen)); + else + return rtw_set_ie(pframe, _RSN_IE_2_, sizeof(ptdls_sta->TDLS_RSNIE), ptdls_sta->TDLS_RSNIE, &(pattrib->pktlen)); +} + +u8 *rtw_tdls_set_ext_cap(u8 *pframe, struct pkt_attrib *pattrib) +{ + return rtw_set_ie(pframe, _EXT_CAP_IE_ , sizeof(TDLS_EXT_CAPIE), TDLS_EXT_CAPIE, &(pattrib->pktlen)); +} + +u8 *rtw_tdls_set_qos_cap(u8 *pframe, struct pkt_attrib *pattrib) +{ + return rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, sizeof(TDLS_WMMIE), TDLS_WMMIE, &(pattrib->pktlen)); +} + +u8 *rtw_tdls_set_ftie(struct tdls_txmgmt *ptxmgmt, u8 *pframe, struct pkt_attrib *pattrib, u8 *ANonce, u8 *SNonce) +{ + struct wpa_tdls_ftie FTIE = {0}; + u8 *p = NULL; + int len = 0; + + if (ptxmgmt->len > 0) + p = rtw_get_ie(ptxmgmt->buf, _FTIE_, &len, ptxmgmt->len); + + if (p != NULL) + return rtw_set_ie(pframe, _FTIE_, len, p+2, &(pattrib->pktlen)); + else { + if (ANonce != NULL) + _rtw_memcpy(FTIE.Anonce, ANonce, WPA_NONCE_LEN); + if (SNonce != NULL) + _rtw_memcpy(FTIE.Snonce, SNonce, WPA_NONCE_LEN); + return rtw_set_ie(pframe, _FTIE_ , 82, (u8 *)FTIE.mic_ctrl, &(pattrib->pktlen)); + } +} + +u8 *rtw_tdls_set_timeout_interval(struct tdls_txmgmt *ptxmgmt, u8 *pframe, struct pkt_attrib *pattrib, int init, struct sta_info *ptdls_sta) +{ + u8 timeout_itvl[5]; /* set timeout interval to maximum value */ + u32 timeout_interval= TDLS_TPK_RESEND_COUNT; + u8 *p = NULL; + int len = 0; + + if (ptxmgmt->len > 0) + p = rtw_get_ie(ptxmgmt->buf, _TIMEOUT_ITVL_IE_, &len, ptxmgmt->len); + + if (p != NULL) + return rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, len, p+2, &(pattrib->pktlen)); + else { + /* Timeout interval */ + timeout_itvl[0]=0x02; + if (init == _TRUE) + _rtw_memcpy(timeout_itvl+1, &timeout_interval, 4); + else + _rtw_memcpy(timeout_itvl+1, (u8 *)(&ptdls_sta->TDLS_PeerKey_Lifetime), 4); + + return rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, 5, timeout_itvl, &(pattrib->pktlen)); + } +} + +u8 *rtw_tdls_set_bss_coexist(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib) +{ + u8 iedata=0; + + if (padapter->mlmepriv.num_FortyMHzIntolerant > 0) + iedata |= BIT(2); /* 20 MHz BSS Width Request */ + + /* Information Bit should be set by TDLS test plan 5.9 */ + iedata |= BIT(0); + return rtw_set_ie(pframe, EID_BSSCoexistence, 1, &iedata, &(pattrib->pktlen)); +} + +u8 *rtw_tdls_set_payload_type(u8 *pframe, struct pkt_attrib *pattrib) +{ + u8 payload_type = 0x02; + return rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen)); +} + +u8 *rtw_tdls_set_category(u8 *pframe, struct pkt_attrib *pattrib, u8 category) +{ + return rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); +} + +u8 *rtw_tdls_set_action(u8 *pframe, struct pkt_attrib *pattrib, struct tdls_txmgmt *ptxmgmt) +{ + return rtw_set_fixed_ie(pframe, 1, &(ptxmgmt->action_code), &(pattrib->pktlen)); +} + +u8 *rtw_tdls_set_status_code(u8 *pframe, struct pkt_attrib *pattrib, struct tdls_txmgmt *ptxmgmt) +{ + return rtw_set_fixed_ie(pframe, 2, (u8 *)&(ptxmgmt->status_code), &(pattrib->pktlen)); +} + +u8 *rtw_tdls_set_dialog(u8 *pframe, struct pkt_attrib *pattrib, struct tdls_txmgmt *ptxmgmt) +{ + u8 dialogtoken = 1; + if (ptxmgmt->dialog_token) + return rtw_set_fixed_ie(pframe, 1, &(ptxmgmt->dialog_token), &(pattrib->pktlen)); + else + return rtw_set_fixed_ie(pframe, 1, &(dialogtoken), &(pattrib->pktlen)); +} + +u8 *rtw_tdls_set_reg_class(u8 *pframe, struct pkt_attrib *pattrib, struct sta_info *ptdls_sta) +{ + u8 reg_class = 22; + return rtw_set_fixed_ie(pframe, 1, &(reg_class), &(pattrib->pktlen)); +} + +u8 *rtw_tdls_set_second_channel_offset(u8 *pframe, struct pkt_attrib *pattrib, u8 ch_offset) +{ + return rtw_set_ie(pframe, EID_SecondaryChnlOffset , 1, &ch_offset, &(pattrib->pktlen)); +} + +u8 *rtw_tdls_set_capability(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + u8 cap_from_ie[2] = {0}; + + _rtw_memcpy(cap_from_ie, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2); + + return rtw_set_fixed_ie(pframe, 2, cap_from_ie, &(pattrib->pktlen)); +} + +u8 *rtw_tdls_set_supported_rate(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib) +{ + u8 bssrate[NDIS_802_11_LENGTH_RATES_EX]; + int bssrate_len = 0; + u8 more_supportedrates = 0; + + rtw_set_supported_rate(bssrate, (padapter->registrypriv.wireless_mode == WIRELESS_MODE_MAX) ? padapter->mlmeextpriv.cur_wireless_mode : padapter->registrypriv.wireless_mode); + bssrate_len = rtw_get_rateset_len(bssrate); + + if (bssrate_len > 8) { + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen)); + more_supportedrates = 1; + } else { + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen)); + } + + /* extended supported rates */ + if (more_supportedrates == 1) { + pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen)); + } + + return pframe; +} + +u8 *rtw_tdls_set_sup_reg_class(u8 *pframe, struct pkt_attrib *pattrib) +{ + return rtw_set_ie(pframe, _SRC_IE_ , sizeof(TDLS_SRC), TDLS_SRC, &(pattrib->pktlen)); +} + +u8 *rtw_tdls_set_linkid(u8 *pframe, struct pkt_attrib *pattrib, u8 init) +{ + u8 link_id_addr[18] = {0}; + if (init == _TRUE) { + _rtw_memcpy(link_id_addr, pattrib->ra, 6); + _rtw_memcpy((link_id_addr+6), pattrib->src, 6); + _rtw_memcpy((link_id_addr+12), pattrib->dst, 6); + } else { + _rtw_memcpy(link_id_addr, pattrib->ra, 6); + _rtw_memcpy((link_id_addr+6), pattrib->dst, 6); + _rtw_memcpy((link_id_addr+12), pattrib->src, 6); + } + return rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen)); +} + +#ifdef CONFIG_TDLS_CH_SW +u8 *rtw_tdls_set_target_ch(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib) +{ + u8 target_ch = 1; + if (padapter->tdlsinfo.chsw_info.off_ch_num) + return rtw_set_fixed_ie(pframe, 1, &(padapter->tdlsinfo.chsw_info.off_ch_num), &(pattrib->pktlen)); + else + return rtw_set_fixed_ie(pframe, 1, &(target_ch), &(pattrib->pktlen)); +} + +u8 *rtw_tdls_set_ch_sw(u8 *pframe, struct pkt_attrib *pattrib, struct sta_info *ptdls_sta) +{ + u8 ch_switch_timing[4] = {0}; + u16 switch_time = (ptdls_sta->ch_switch_time >= TDLS_CH_SWITCH_TIME * 1000) ? + ptdls_sta->ch_switch_time : TDLS_CH_SWITCH_TIME; + u16 switch_timeout = (ptdls_sta->ch_switch_timeout >= TDLS_CH_SWITCH_TIMEOUT * 1000) ? + ptdls_sta->ch_switch_timeout : TDLS_CH_SWITCH_TIMEOUT; + + _rtw_memcpy(ch_switch_timing, &switch_time, 2); + _rtw_memcpy(ch_switch_timing + 2, &switch_timeout, 2); + + return rtw_set_ie(pframe, _CH_SWITCH_TIMING_, 4, ch_switch_timing, &(pattrib->pktlen)); +} + +void rtw_tdls_set_ch_sw_oper_control(_adapter *padapter, u8 enable) +{ + if (ATOMIC_READ(&padapter->tdlsinfo.chsw_info.chsw_on) != enable) + ATOMIC_SET(&padapter->tdlsinfo.chsw_info.chsw_on, enable); + + rtw_hal_set_hwreg(padapter, HW_VAR_TDLS_BCN_EARLY_C2H_RPT, &enable); + DBG_871X("[TDLS] %s Bcn Early C2H Report\n", (enable == _TRUE) ? "Start" : "Stop"); +} + +void rtw_tdls_ch_sw_back_to_base_chnl(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv; + struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info; + + pmlmepriv = &padapter->mlmepriv; + + if ((ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE) && + /* Sometimes we receive multiple interrupts in very little time period, use the follow condition test to filter */ + //(pchsw_info->cur_time - last_time > padapter->mlmeextpriv.mlmext_info.bcn_interval - 5) && + (padapter->mlmeextpriv.cur_channel != rtw_get_oper_ch(padapter))) { + //if(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE) + rtw_tdls_cmd(padapter, pchsw_info->addr, TDLS_CH_SW_TO_BASE_CHNL_UNSOLICITED); + } +} + +static void rtw_tdls_chsw_oper_init(_adapter* padapter, u32 timeout_ms) +{ + struct submit_ctx *chsw_sctx = &padapter->tdlsinfo.chsw_info.chsw_sctx; + + rtw_sctx_init(chsw_sctx, timeout_ms); +} + +static int rtw_tdls_chsw_oper_wait(_adapter* padapter) +{ + struct submit_ctx *chsw_sctx = &padapter->tdlsinfo.chsw_info.chsw_sctx; + + return rtw_sctx_wait(chsw_sctx, __func__); +} + +void rtw_tdls_chsw_oper_done(_adapter* padapter) +{ + struct submit_ctx *chsw_sctx = &padapter->tdlsinfo.chsw_info.chsw_sctx; + + rtw_sctx_done(&chsw_sctx); +} + +s32 rtw_tdls_do_ch_sw(_adapter *padapter, struct sta_info *ptdls_sta, u8 chnl_type, u8 channel, u8 channel_offset, u16 bwmode, u16 ch_switch_time) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8 center_ch, chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + u32 ch_sw_time_start, ch_sw_time_spent, wait_time; + u8 take_care_iqk; + s32 ret = _FAIL; + + ch_sw_time_start = rtw_systime_to_ms(rtw_get_current_time()); + + rtw_tdls_chsw_oper_init(padapter, TDLS_CH_SWITCH_OPER_OFFLOAD_TIMEOUT); + + /* set mac_id sleep before channel switch */ + rtw_hal_macid_sleep(padapter, ptdls_sta->mac_id); + + /* channel switch IOs offload to FW */ + if (rtw_hal_ch_sw_oper_offload(padapter, channel, channel_offset, bwmode) == _SUCCESS) { + if (rtw_tdls_chsw_oper_wait(padapter) == _SUCCESS) { + /* set channel and bw related variables in driver */ + _enter_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL); + + rtw_set_oper_ch(padapter, channel); + rtw_set_oper_choffset(padapter, channel_offset); + rtw_set_oper_bw(padapter, bwmode); + + center_ch = rtw_get_center_ch(channel, bwmode, channel_offset); + pHalData->CurrentChannel = center_ch; + pHalData->CurrentCenterFrequencyIndex1 = center_ch; + pHalData->CurrentChannelBW = bwmode; + pHalData->nCur40MhzPrimeSC = channel_offset; + + if (bwmode == CHANNEL_WIDTH_80) { + if (center_ch > channel) + chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER; + else if (center_ch < channel) + chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER; + else + chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + } + pHalData->nCur80MhzPrimeSC = chnl_offset80; + + pHalData->CurrentCenterFrequencyIndex1 = center_ch; + + _exit_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL); + + rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk); + if (take_care_iqk == _TRUE) + rtw_hal_ch_sw_iqk_info_restore(padapter, CH_SW_USE_CASE_TDLS); + + ch_sw_time_spent = rtw_systime_to_ms(rtw_get_current_time()) - ch_sw_time_start; + + if (chnl_type == TDLS_CH_SW_OFF_CHNL) { + if ((u32)ch_switch_time /1000 > ch_sw_time_spent) + wait_time = (u32)ch_switch_time /1000 - ch_sw_time_spent; + else + wait_time = 0; + + if (wait_time > 0) + rtw_msleep_os(wait_time); + } + + ret = _SUCCESS; + } else + DBG_871X("[TDLS] chsw oper wait fail !!\n"); + } + + /* set mac_id wakeup after channel switch */ + rtw_hal_macid_wakeup(padapter, ptdls_sta->mac_id); + + return ret; +} +#endif + +u8 *rtw_tdls_set_wmm_params(_adapter *padapter, u8 *pframe, struct pkt_attrib *pattrib) +{ + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 wmm_param_ele[24] = {0}; + + if (&pmlmeinfo->WMM_param) { + _rtw_memcpy(wmm_param_ele, WMM_PARA_OUI, 6); + if (_rtw_memcmp(&pmlmeinfo->WMM_param, &wmm_param_ele[6], 18) == _TRUE) + /* Use default WMM Param */ + _rtw_memcpy(wmm_param_ele + 6, (u8 *)&TDLS_WMM_PARAM_IE, sizeof(TDLS_WMM_PARAM_IE)); + else + _rtw_memcpy(wmm_param_ele + 6, (u8 *)&pmlmeinfo->WMM_param, sizeof(pmlmeinfo->WMM_param)); + return rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 24, wmm_param_ele, &(pattrib->pktlen)); + } + else + return pframe; +} + +#ifdef CONFIG_WFD +void rtw_tdls_process_wfd_ie(struct tdls_info *ptdlsinfo, u8 *ptr, u8 length) +{ + u8 *wfd_ie; + u32 wfd_ielen = 0; + + if (!hal_chk_wl_func(tdls_info_to_adapter(ptdlsinfo), WL_FUNC_MIRACAST)) + return; + + /* Try to get the TCP port information when receiving the negotiation response. */ + + wfd_ie = rtw_get_wfd_ie(ptr, length, NULL, &wfd_ielen); + while (wfd_ie) { + u8 *attr_content; + u32 attr_contentlen = 0; + int i; + + DBG_871X( "[%s] WFD IE Found!!\n", __FUNCTION__ ); + attr_content = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &attr_contentlen); + if (attr_content && attr_contentlen) { + ptdlsinfo->wfd_info->peer_rtsp_ctrlport = RTW_GET_BE16( attr_content + 2 ); + DBG_871X( "[%s] Peer PORT NUM = %d\n", __FUNCTION__, ptdlsinfo->wfd_info->peer_rtsp_ctrlport ); + } + + attr_content = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_LOCAL_IP_ADDR, NULL, &attr_contentlen); + if (attr_content && attr_contentlen) { + _rtw_memcpy(ptdlsinfo->wfd_info->peer_ip_address, ( attr_content + 1 ), 4); + DBG_871X("[%s] Peer IP = %02u.%02u.%02u.%02u\n", __FUNCTION__, + ptdlsinfo->wfd_info->peer_ip_address[0], ptdlsinfo->wfd_info->peer_ip_address[1], + ptdlsinfo->wfd_info->peer_ip_address[2], ptdlsinfo->wfd_info->peer_ip_address[3]); + } + + wfd_ie = rtw_get_wfd_ie(wfd_ie + wfd_ielen, (ptr + length) - (wfd_ie + wfd_ielen), NULL, &wfd_ielen); + } +} + +int issue_tunneled_probe_req(_adapter *padapter) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + u8 baddr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + struct tdls_txmgmt txmgmt; + int ret = _FAIL; + + DBG_871X("[%s]\n", __FUNCTION__); + + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); + txmgmt.action_code = TUNNELED_PROBE_REQ; + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + goto exit; + + pattrib = &pmgntframe->attrib; + + pmgntframe->frame_tag = DATA_FRAMETAG; + pattrib->ether_type = 0x890d; + + _rtw_memcpy(pattrib->dst, baddr, ETH_ALEN); + _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); + + update_tdls_attrib(padapter, pattrib); + pattrib->qsel = pattrib->priority; + if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, &txmgmt) != _SUCCESS) { + rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); + rtw_free_xmitframe(pxmitpriv, pmgntframe); + goto exit; + } + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; +exit: + + return ret; +} + +int issue_tunneled_probe_rsp(_adapter *padapter, union recv_frame *precv_frame) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct tdls_txmgmt txmgmt; + int ret = _FAIL; + + DBG_871X("[%s]\n", __FUNCTION__); + + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); + txmgmt.action_code = TUNNELED_PROBE_RSP; + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + goto exit; + + pattrib = &pmgntframe->attrib; + + pmgntframe->frame_tag = DATA_FRAMETAG; + pattrib->ether_type = 0x890d; + + _rtw_memcpy(pattrib->dst, precv_frame->u.hdr.attrib.src, ETH_ALEN); + _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); + + update_tdls_attrib(padapter, pattrib); + pattrib->qsel = pattrib->priority; + if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, &txmgmt) != _SUCCESS) { + rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); + rtw_free_xmitframe(pxmitpriv, pmgntframe); + goto exit; + } + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; +exit: + + return ret; +} +#endif /* CONFIG_WFD */ + +int issue_tdls_setup_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wait_ack) +{ + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *ptdls_sta= NULL; + _irqL irqL; + int ret = _FAIL; + /* Retry timer should be set at least 301 sec, using TPK_count counting 301 times. */ + u32 timeout_interval= TDLS_TPK_RESEND_COUNT; + + DBG_871X("[TDLS] %s\n", __FUNCTION__); + + ptxmgmt->action_code = TDLS_SETUP_REQUEST; + if (rtw_tdls_is_setup_allowed(padapter) == _FALSE) + goto exit; + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + goto exit; + + pattrib = &pmgntframe->attrib; + pmgntframe->frame_tag = DATA_FRAMETAG; + pattrib->ether_type = 0x890d; + + _rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN); + _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); + + update_tdls_attrib(padapter, pattrib); + + /* init peer sta_info */ + ptdls_sta = rtw_get_stainfo(pstapriv, ptxmgmt->peer); + if (ptdls_sta == NULL) { + ptdls_sta = rtw_alloc_stainfo(pstapriv, ptxmgmt->peer); + if (ptdls_sta == NULL) { + DBG_871X("[%s] rtw_alloc_stainfo fail\n", __FUNCTION__); + rtw_free_xmitbuf(pxmitpriv,pmgntframe->pxmitbuf); + rtw_free_xmitframe(pxmitpriv, pmgntframe); + goto exit; + } + } + + if(!(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)) + ptdlsinfo->sta_cnt++; + + if (ptdlsinfo->sta_cnt == MAX_ALLOWED_TDLS_STA_NUM) + ptdlsinfo->sta_maximum = _TRUE; + + ptdls_sta->tdls_sta_state |= TDLS_RESPONDER_STATE; + + if (rtw_tdls_is_driver_setup(padapter) == _TRUE) { + ptdls_sta->TDLS_PeerKey_Lifetime = timeout_interval; + _set_timer(&ptdls_sta->handshake_timer, TDLS_HANDSHAKE_TIME); + } + + pattrib->qsel = pattrib->priority; + + if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) !=_SUCCESS) { + rtw_free_xmitbuf(pxmitpriv,pmgntframe->pxmitbuf); + rtw_free_xmitframe(pxmitpriv, pmgntframe); + goto exit; + } + + if (wait_ack) { + ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); + } else { + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + } + +exit: + + return ret; +} + +int _issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 wait_ack) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *ptdls_sta=NULL; + _irqL irqL; + int ret = _FAIL; + + DBG_871X("[TDLS] %s\n", __FUNCTION__); + + ptxmgmt->action_code = TDLS_TEARDOWN; + ptdls_sta = rtw_get_stainfo(pstapriv, ptxmgmt->peer); + if (ptdls_sta == NULL) { + DBG_871X("Np tdls_sta for tearing down\n"); + goto exit; + } + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + goto exit; + + rtw_set_scan_deny(padapter, 550); + + rtw_scan_abort(padapter); +#ifdef CONFIG_CONCURRENT_MODE + if (rtw_buddy_adapter_up(padapter)) + rtw_scan_abort(padapter->pbuddy_adapter); +#endif /* CONFIG_CONCURRENT_MODE */ + + pattrib = &pmgntframe->attrib; + + pmgntframe->frame_tag = DATA_FRAMETAG; + pattrib->ether_type = 0x890d; + + _rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN); + _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); + + update_tdls_attrib(padapter, pattrib); + pattrib->qsel = pattrib->priority; + if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) { + rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); + rtw_free_xmitframe(pxmitpriv, pmgntframe); + goto exit; + } + + if (rtw_tdls_is_driver_setup(padapter) == _TRUE) + if(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) + if (pattrib->encrypt) + _cancel_timer_ex(&ptdls_sta->TPK_timer); + + if (wait_ack) { + ret = dump_mgntframe_and_wait_ack(padapter, pmgntframe); + } else { + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + } + + if (rtw_tdls_is_driver_setup(padapter)) + rtw_tdls_cmd(padapter, ptxmgmt->peer, TDLS_TEARDOWN_STA_LOCALLY); + +exit: + + return ret; +} + +int issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 wait_ack) +{ + int ret = _FAIL; + + ret = _issue_tdls_teardown(padapter, ptxmgmt, wait_ack); + if ((ptxmgmt->status_code == _RSON_TDLS_TEAR_UN_RSN_) && (ret == _FAIL)) { + /* Change status code and send teardown again via AP */ + ptxmgmt->status_code = _RSON_TDLS_TEAR_TOOFAR_; + ret = _issue_tdls_teardown(padapter, ptxmgmt, wait_ack); + } + + return ret; +} + +int issue_tdls_dis_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + int ret = _FAIL; + + DBG_871X("[TDLS] %s\n", __FUNCTION__); + + ptxmgmt->action_code = TDLS_DISCOVERY_REQUEST; + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + goto exit; + + pattrib = &pmgntframe->attrib; + pmgntframe->frame_tag = DATA_FRAMETAG; + pattrib->ether_type = 0x890d; + + _rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN); + _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); + + update_tdls_attrib(padapter, pattrib); + pattrib->qsel = pattrib->priority; + if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) { + rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); + rtw_free_xmitframe(pxmitpriv, pmgntframe); + goto exit; + } + dump_mgntframe(padapter, pmgntframe); + DBG_871X("issue tdls dis req\n"); + + ret = _SUCCESS; +exit: + + return ret; +} + +int issue_tdls_setup_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + int ret = _FAIL; + + DBG_871X("[TDLS] %s\n", __FUNCTION__); + + ptxmgmt->action_code = TDLS_SETUP_RESPONSE; + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + goto exit; + + pattrib = &pmgntframe->attrib; + pmgntframe->frame_tag = DATA_FRAMETAG; + pattrib->ether_type = 0x890d; + + _rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN); + _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pattrib->ra, get_bssid(&(padapter->mlmepriv)), ETH_ALEN); + _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); + + update_tdls_attrib(padapter, pattrib); + pattrib->qsel = pattrib->priority; + if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) { + rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); + rtw_free_xmitframe(pxmitpriv, pmgntframe); + goto exit; + } + + dump_mgntframe(padapter, pmgntframe); + + ret = _SUCCESS; +exit: + + return ret; + +} + +int issue_tdls_setup_cfm(_adapter *padapter, struct tdls_txmgmt *ptxmgmt) +{ + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + int ret = _FAIL; + + DBG_871X("[TDLS] %s\n", __FUNCTION__); + + ptxmgmt->action_code = TDLS_SETUP_CONFIRM; + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + goto exit; + + pattrib = &pmgntframe->attrib; + pmgntframe->frame_tag = DATA_FRAMETAG; + pattrib->ether_type = 0x890d; + + _rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN); + _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pattrib->ra, get_bssid(&padapter->mlmepriv), ETH_ALEN); + _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); + + update_tdls_attrib(padapter, pattrib); + pattrib->qsel = pattrib->priority; + if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) != _SUCCESS) { + rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); + rtw_free_xmitframe(pxmitpriv, pmgntframe); + goto exit; + } + + dump_mgntframe(padapter, pmgntframe); + + ret = _SUCCESS; +exit: + + return ret; + +} + +/* TDLS Discovery Response frame is a management action frame */ +int issue_tdls_dis_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 privacy) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + int ret = _FAIL; + + DBG_871X("[TDLS] %s\n", __FUNCTION__); + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + goto exit; + + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + /* unicast probe request frame */ + _rtw_memcpy(pwlanhdr->addr1, ptxmgmt->peer, ETH_ALEN); + _rtw_memcpy(pattrib->dst, pwlanhdr->addr1, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pattrib->src, pwlanhdr->addr2, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN); + _rtw_memcpy(pattrib->ra, pwlanhdr->addr3, ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(pframe, WIFI_ACTION); + + pframe += sizeof (struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof (struct rtw_ieee80211_hdr_3addr); + + rtw_build_tdls_dis_rsp_ies(padapter, pmgntframe, pframe, ptxmgmt, privacy); + + pattrib->nr_frags = 1; + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + +exit: + return ret; +} + +int issue_tdls_peer_traffic_rsp(_adapter *padapter, struct sta_info *ptdls_sta, struct tdls_txmgmt *ptxmgmt) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + int ret = _FAIL; + + DBG_871X("[TDLS] %s\n", __FUNCTION__); + + ptxmgmt->action_code = TDLS_PEER_TRAFFIC_RESPONSE; + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + goto exit; + + pattrib = &pmgntframe->attrib; + + pmgntframe->frame_tag = DATA_FRAMETAG; + pattrib->ether_type = 0x890d; + + _rtw_memcpy(pattrib->dst, ptdls_sta->hwaddr, ETH_ALEN); + _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); + + update_tdls_attrib(padapter, pattrib); + pattrib->qsel = pattrib->priority; + + if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) !=_SUCCESS) { + rtw_free_xmitbuf(pxmitpriv,pmgntframe->pxmitbuf); + rtw_free_xmitframe(pxmitpriv, pmgntframe); + goto exit; + } + + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + +exit: + + return ret; +} + +int issue_tdls_peer_traffic_indication(_adapter *padapter, struct sta_info *ptdls_sta) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct tdls_txmgmt txmgmt; + int ret = _FAIL; + + DBG_871X("[TDLS] %s\n", __FUNCTION__); + + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); + txmgmt.action_code = TDLS_PEER_TRAFFIC_INDICATION; + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + goto exit; + + pattrib = &pmgntframe->attrib; + + pmgntframe->frame_tag = DATA_FRAMETAG; + pattrib->ether_type = 0x890d; + + _rtw_memcpy(pattrib->dst, ptdls_sta->hwaddr, ETH_ALEN); + _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); + + /* PTI frame's priority should be AC_VO */ + pattrib->priority = 7; + + update_tdls_attrib(padapter, pattrib); + pattrib->qsel = pattrib->priority; + if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, &txmgmt) != _SUCCESS) { + rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); + rtw_free_xmitframe(pxmitpriv, pmgntframe); + goto exit; + } + + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + +exit: + + return ret; +} + +#ifdef CONFIG_TDLS_CH_SW +int issue_tdls_ch_switch_req(_adapter *padapter, struct sta_info *ptdls_sta) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct tdls_txmgmt txmgmt; + int ret = _FAIL; + + DBG_871X("[TDLS] %s\n", __FUNCTION__); + + if (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) + { DBG_871X("[TDLS] Ignore %s since channel switch is not allowed\n", __FUNCTION__); + goto exit; + } + + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); + txmgmt.action_code = TDLS_CHANNEL_SWITCH_REQUEST; + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + goto exit; + + pattrib = &pmgntframe->attrib; + + pmgntframe->frame_tag = DATA_FRAMETAG; + pattrib->ether_type = 0x890d; + + _rtw_memcpy(pattrib->dst, ptdls_sta->hwaddr, ETH_ALEN); + _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); + + update_tdls_attrib(padapter, pattrib); + pattrib->qsel = pattrib->priority; + if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, &txmgmt) !=_SUCCESS) { + rtw_free_xmitbuf(pxmitpriv,pmgntframe->pxmitbuf); + rtw_free_xmitframe(pxmitpriv, pmgntframe); + goto exit; + } + + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; +exit: + + return ret; +} + +int issue_tdls_ch_switch_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wait_ack) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + int ret = _FAIL; + + DBG_871X("[TDLS] %s\n", __FUNCTION__); + + if (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) + { DBG_871X("[TDLS] Ignore %s since channel switch is not allowed\n", __FUNCTION__); + goto exit; + } + + ptxmgmt->action_code = TDLS_CHANNEL_SWITCH_RESPONSE; + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + goto exit; + + pattrib = &pmgntframe->attrib; + + pmgntframe->frame_tag = DATA_FRAMETAG; + pattrib->ether_type = 0x890d; + + _rtw_memcpy(pattrib->dst, ptxmgmt->peer, ETH_ALEN); + _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pattrib->ra, ptxmgmt->peer, ETH_ALEN); + _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); + + update_tdls_attrib(padapter, pattrib); + pattrib->qsel = pattrib->priority; +/* + _enter_critical_bh(&pxmitpriv->lock, &irqL); + if(xmitframe_enqueue_for_tdls_sleeping_sta(padapter, pmgntframe)==_TRUE){ + _exit_critical_bh(&pxmitpriv->lock, &irqL); + return _FALSE; + } +*/ + if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, ptxmgmt) !=_SUCCESS) { + rtw_free_xmitbuf(pxmitpriv,pmgntframe->pxmitbuf); + rtw_free_xmitframe(pxmitpriv, pmgntframe); + goto exit; + } + + if (wait_ack) { + ret = dump_mgntframe_and_wait_ack_timeout(padapter, pmgntframe, 10); + } else { + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + } +exit: + + return ret; +} +#endif + +int On_TDLS_Dis_Rsp(_adapter *padapter, union recv_frame *precv_frame) +{ + struct sta_info *ptdls_sta = NULL, *psta = rtw_get_stainfo(&(padapter->stapriv), get_bssid(&(padapter->mlmepriv))); + struct recv_priv *precvpriv = &(padapter->recvpriv); + u8 *ptr = precv_frame->u.hdr.rx_data, *psa; + struct rx_pkt_attrib *pattrib = &(precv_frame->u.hdr.attrib); + struct tdls_info *ptdlsinfo = &(padapter->tdlsinfo); + u8 empty_addr[ETH_ALEN] = { 0x00 }; + int UndecoratedSmoothedPWDB; + struct tdls_txmgmt txmgmt; + int ret = _SUCCESS; + + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); + /* WFDTDLS: for sigma test, not to setup direct link automatically */ + ptdlsinfo->dev_discovered = _TRUE; + + psa = get_sa(ptr); + ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), psa); + if (ptdls_sta != NULL) + ptdls_sta->sta_stats.rx_tdls_disc_rsp_pkts++; + +#ifdef CONFIG_TDLS_AUTOSETUP + if (ptdls_sta != NULL) { + /* Record the tdls sta with lowest signal strength */ + if (ptdlsinfo->sta_maximum == _TRUE && ptdls_sta->alive_count >= 1 ) { + if (_rtw_memcmp(ptdlsinfo->ss_record.macaddr, empty_addr, ETH_ALEN)) { + _rtw_memcpy(ptdlsinfo->ss_record.macaddr, psa, ETH_ALEN); + ptdlsinfo->ss_record.RxPWDBAll = pattrib->phy_info.RxPWDBAll; + } else { + if (ptdlsinfo->ss_record.RxPWDBAll < pattrib->phy_info.RxPWDBAll) { + _rtw_memcpy(ptdlsinfo->ss_record.macaddr, psa, ETH_ALEN); + ptdlsinfo->ss_record.RxPWDBAll = pattrib->phy_info.RxPWDBAll; + } + } + } + } else { + if (ptdlsinfo->sta_maximum == _TRUE) { + if (_rtw_memcmp( ptdlsinfo->ss_record.macaddr, empty_addr, ETH_ALEN)) { + /* All traffics are busy, do not set up another direct link. */ + ret = _FAIL; + goto exit; + } else { + if (pattrib->phy_info.RxPWDBAll > ptdlsinfo->ss_record.RxPWDBAll) { + _rtw_memcpy(txmgmt.peer, ptdlsinfo->ss_record.macaddr, ETH_ALEN); + /* issue_tdls_teardown(padapter, ptdlsinfo->ss_record.macaddr, _FALSE); */ + } else { + ret = _FAIL; + goto exit; + } + } + } + + rtw_hal_get_def_var(padapter, HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, &UndecoratedSmoothedPWDB); + + if (pattrib->phy_info.RxPWDBAll + TDLS_SIGNAL_THRESH >= UndecoratedSmoothedPWDB) { + DBG_871X("pattrib->RxPWDBAll=%d, pdmpriv->UndecoratedSmoothedPWDB=%d\n", pattrib->phy_info.RxPWDBAll, UndecoratedSmoothedPWDB); + _rtw_memcpy(txmgmt.peer, psa, ETH_ALEN); + issue_tdls_setup_req(padapter, &txmgmt, _FALSE); + } + } +#endif /* CONFIG_TDLS_AUTOSETUP */ + +exit: + return ret; + +} + +sint On_TDLS_Setup_Req(_adapter *padapter, union recv_frame *precv_frame) +{ + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + u8 *psa, *pmyid; + struct sta_info *ptdls_sta= NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 *ptr = precv_frame->u.hdr.rx_data; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct security_priv *psecuritypriv = &padapter->securitypriv; + _irqL irqL; + struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; + u8 *prsnie, *ppairwise_cipher; + u8 i, k; + u8 ccmp_included=0, rsnie_included=0; + u16 j, pairwise_count; + u8 SNonce[32]; + u32 timeout_interval = TDLS_TPK_RESEND_COUNT; + sint parsing_length; /* Frame body length, without icv_len */ + PNDIS_802_11_VARIABLE_IEs pIE; + u8 FIXED_IE = 5; + unsigned char supportRate[16]; + int supportRateNum = 0; + struct tdls_txmgmt txmgmt; + + if (rtw_tdls_is_setup_allowed(padapter) == _FALSE) + goto exit; + + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); + psa = get_sa(ptr); + ptdls_sta = rtw_get_stainfo(pstapriv, psa); + + pmyid = adapter_mac_addr(padapter); + ptr +=prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len+LLC_HEADER_SIZE+ETH_TYPE_LEN+PAYLOAD_TYPE_LEN; + parsing_length= ((union recv_frame *)precv_frame)->u.hdr.len + -prx_pkt_attrib->hdrlen + -prx_pkt_attrib->iv_len + -prx_pkt_attrib->icv_len + -LLC_HEADER_SIZE + -ETH_TYPE_LEN + -PAYLOAD_TYPE_LEN + -FIXED_IE; + + if (ptdls_sta == NULL) { + ptdls_sta = rtw_alloc_stainfo(pstapriv, psa); + } else { + if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) { + /* If the direct link is already set up */ + /* Process as re-setup after tear down */ + DBG_871X("re-setup a direct link\n"); + } + /* Already receiving TDLS setup request */ + else if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) { + DBG_871X("receive duplicated TDLS setup request frame in handshaking\n"); + goto exit; + } + /* When receiving and sending setup_req to the same link at the same time */ + /* STA with higher MAC_addr would be initiator */ + else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) { + DBG_871X("receive setup_req after sending setup_req\n"); + for (i=0;i<6;i++){ + if(*(pmyid+i)==*(psa+i)){ + } + else if(*(pmyid+i)>*(psa+i)){ + ptdls_sta->tdls_sta_state = TDLS_INITIATOR_STATE; + break; + }else if(*(pmyid+i)<*(psa+i)){ + goto exit; + } + } + } + } + + if (ptdls_sta) { + txmgmt.dialog_token = *(ptr+2); /* Copy dialog token */ + txmgmt.status_code = _STATS_SUCCESSFUL_; + + /* Parsing information element */ + for (j=FIXED_IE; jElementID) { + case _SUPPORTEDRATES_IE_: + _rtw_memcpy(supportRate, pIE->data, pIE->Length); + supportRateNum = pIE->Length; + break; + case _COUNTRY_IE_: + break; + case _EXT_SUPPORTEDRATES_IE_: + if (supportRateNum<=sizeof(supportRate)) { + _rtw_memcpy(supportRate+supportRateNum, pIE->data, pIE->Length); + supportRateNum += pIE->Length; + } + break; + case _SUPPORTED_CH_IE_: + break; + case _RSN_IE_2_: + rsnie_included=1; + if (prx_pkt_attrib->encrypt) { + prsnie=(u8*)pIE; + /* Check CCMP pairwise_cipher presence. */ + ppairwise_cipher=prsnie+10; + _rtw_memcpy(ptdls_sta->TDLS_RSNIE, pIE->data, pIE->Length); + pairwise_count = *(u16*)(ppairwise_cipher-2); + for (k=0; kencrypt) + _rtw_memcpy(SNonce, (ptr+j+52), 32); + break; + case _TIMEOUT_ITVL_IE_: + if (prx_pkt_attrib->encrypt) + timeout_interval = cpu_to_le32(*(u32*)(ptr+j+3)); + break; + case _RIC_Descriptor_IE_: + break; +#ifdef CONFIG_80211N_HT + case _HT_CAPABILITY_IE_: + rtw_tdls_process_ht_cap(padapter, ptdls_sta, pIE->data, pIE->Length); + break; +#endif +#ifdef CONFIG_80211AC_VHT + case EID_AID: + break; + case EID_VHTCapability: + rtw_tdls_process_vht_cap(padapter, ptdls_sta, pIE->data, pIE->Length); + break; +#endif + case EID_BSSCoexistence: + break; + case _LINK_ID_IE_: + if (_rtw_memcmp(get_bssid(pmlmepriv), pIE->data, 6) == _FALSE) + txmgmt.status_code=_STATS_NOT_IN_SAME_BSS_; + break; + default: + break; + } + + j += (pIE->Length + 2); + + } + + /* Check status code */ + /* If responder STA has/hasn't security on AP, but request hasn't/has RSNIE, it should reject */ + if (txmgmt.status_code == _STATS_SUCCESSFUL_) { + if (rsnie_included && prx_pkt_attrib->encrypt == 0) + txmgmt.status_code = _STATS_SEC_DISABLED_; + else if (rsnie_included==0 && prx_pkt_attrib->encrypt) + txmgmt.status_code = _STATS_INVALID_PARAMETERS_; + +#ifdef CONFIG_WFD + /* WFD test plan version 0.18.2 test item 5.1.5 */ + /* SoUT does not use TDLS if AP uses weak security */ + if (padapter->wdinfo.wfd_tdls_enable && (rsnie_included && prx_pkt_attrib->encrypt != _AES_)) + txmgmt.status_code = _STATS_SEC_DISABLED_; +#endif /* CONFIG_WFD */ + } + + ptdls_sta->tdls_sta_state|= TDLS_INITIATOR_STATE; + if (prx_pkt_attrib->encrypt) { + _rtw_memcpy(ptdls_sta->SNonce, SNonce, 32); + + if (timeout_interval <= 300) + ptdls_sta->TDLS_PeerKey_Lifetime = TDLS_TPK_RESEND_COUNT; + else + ptdls_sta->TDLS_PeerKey_Lifetime = timeout_interval; + } + + /* Update station supportRate */ + ptdls_sta->bssratelen = supportRateNum; + _rtw_memcpy(ptdls_sta->bssrateset, supportRate, supportRateNum); + + if (!(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)) + ptdlsinfo->sta_cnt++; + /* -2: AP + BC/MC sta, -4: default key */ + if (ptdlsinfo->sta_cnt == MAX_ALLOWED_TDLS_STA_NUM) + ptdlsinfo->sta_maximum = _TRUE; + +#ifdef CONFIG_WFD + rtw_tdls_process_wfd_ie(ptdlsinfo, ptr + FIXED_IE, parsing_length); +#endif + + }else { + goto exit; + } + + _rtw_memcpy(txmgmt.peer, prx_pkt_attrib->src, ETH_ALEN); + + if (rtw_tdls_is_driver_setup(padapter)) { + issue_tdls_setup_rsp(padapter, &txmgmt); + + if (txmgmt.status_code==_STATS_SUCCESSFUL_) { + _set_timer( &ptdls_sta->handshake_timer, TDLS_HANDSHAKE_TIME); + }else { + free_tdls_sta(padapter, ptdls_sta); + } + } + +exit: + + return _SUCCESS; +} + +int On_TDLS_Setup_Rsp(_adapter *padapter, union recv_frame *precv_frame) +{ + struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + struct sta_info *ptdls_sta= NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 *ptr = precv_frame->u.hdr.rx_data; + _irqL irqL; + struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; + u8 *psa; + u16 status_code=0; + sint parsing_length; /* Frame body length, without icv_len */ + PNDIS_802_11_VARIABLE_IEs pIE; + u8 FIXED_IE =7; + u8 ANonce[32]; + u8 *pftie=NULL, *ptimeout_ie=NULL, *plinkid_ie=NULL, *prsnie=NULL, *pftie_mic=NULL, *ppairwise_cipher=NULL; + u16 pairwise_count, j, k; + u8 verify_ccmp=0; + unsigned char supportRate[16]; + int supportRateNum = 0; + struct tdls_txmgmt txmgmt; + int ret = _SUCCESS; + u32 timeout_interval = TDLS_TPK_RESEND_COUNT; + + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); + psa = get_sa(ptr); + ptdls_sta = rtw_get_stainfo(pstapriv, psa); + + if (ptdls_sta == NULL) { + DBG_871X("[%s] Direct Link Peer = "MAC_FMT" not found\n", __FUNCTION__, MAC_ARG(psa)); + ret = _FAIL; + goto exit; + } + + ptr +=prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len+LLC_HEADER_SIZE+ETH_TYPE_LEN+PAYLOAD_TYPE_LEN; + parsing_length= ((union recv_frame *)precv_frame)->u.hdr.len + -prx_pkt_attrib->hdrlen + -prx_pkt_attrib->iv_len + -prx_pkt_attrib->icv_len + -LLC_HEADER_SIZE + -ETH_TYPE_LEN + -PAYLOAD_TYPE_LEN + -FIXED_IE; + + _rtw_memcpy(&status_code, ptr+2, 2); + + if (status_code != 0) { + DBG_871X( "[TDLS] %s status_code = %d, free_tdls_sta\n", __FUNCTION__, status_code ); + free_tdls_sta(padapter, ptdls_sta); + ret = _FAIL; + goto exit; + } + + status_code = 0; + + /* parsing information element */ + for (j = FIXED_IE; jElementID) { + case _SUPPORTEDRATES_IE_: + _rtw_memcpy(supportRate, pIE->data, pIE->Length); + supportRateNum = pIE->Length; + break; + case _COUNTRY_IE_: + break; + case _EXT_SUPPORTEDRATES_IE_: + if (supportRateNum<=sizeof(supportRate)) { + _rtw_memcpy(supportRate+supportRateNum, pIE->data, pIE->Length); + supportRateNum += pIE->Length; + } + break; + case _SUPPORTED_CH_IE_: + break; + case _RSN_IE_2_: + prsnie=(u8*)pIE; + /* Check CCMP pairwise_cipher presence. */ + ppairwise_cipher=prsnie+10; + _rtw_memcpy(&pairwise_count, (u16*)(ppairwise_cipher-2), 2); + for (k=0;kwmm_enable == _TRUE) || (padapter->mlmepriv.htpriv.ht_option == _TRUE)) + ptdls_sta->qos_option = _TRUE; + } + break; + case _FTIE_: + pftie=(u8*)pIE; + _rtw_memcpy(ANonce, (ptr+j+20), 32); + break; + case _TIMEOUT_ITVL_IE_: + ptimeout_ie=(u8*)pIE; + timeout_interval = cpu_to_le32(*(u32*)(ptimeout_ie+3)); + break; + case _RIC_Descriptor_IE_: + break; +#ifdef CONFIG_80211N_HT + case _HT_CAPABILITY_IE_: + rtw_tdls_process_ht_cap(padapter, ptdls_sta, pIE->data, pIE->Length); + break; +#endif +#ifdef CONFIG_80211AC_VHT + case EID_AID: + /* todo in the future if necessary */ + break; + case EID_VHTCapability: + rtw_tdls_process_vht_cap(padapter, ptdls_sta, pIE->data, pIE->Length); + break; + case EID_OpModeNotification: + rtw_process_vht_op_mode_notify(padapter, pIE->data, ptdls_sta); + break; +#endif + case EID_BSSCoexistence: + break; + case _LINK_ID_IE_: + plinkid_ie=(u8*)pIE; + break; + default: + break; + } + + j += (pIE->Length + 2); + + } + + ptdls_sta->bssratelen = supportRateNum; + _rtw_memcpy(ptdls_sta->bssrateset, supportRate, supportRateNum); + _rtw_memcpy(ptdls_sta->ANonce, ANonce, 32); + +#ifdef CONFIG_WFD + rtw_tdls_process_wfd_ie(ptdlsinfo, ptr + FIXED_IE, parsing_length); +#endif + + if (status_code != _STATS_SUCCESSFUL_) { + txmgmt.status_code = status_code; + } else { + if (prx_pkt_attrib->encrypt) { + if (verify_ccmp == 1) { + txmgmt.status_code = _STATS_SUCCESSFUL_; + if (rtw_tdls_is_driver_setup(padapter) == _TRUE) { + wpa_tdls_generate_tpk(padapter, ptdls_sta); + if (tdls_verify_mic(ptdls_sta->tpk.kck, 2, plinkid_ie, prsnie, ptimeout_ie, pftie) == _FAIL) { + DBG_871X( "[TDLS] %s tdls_verify_mic fail, free_tdls_sta\n", __FUNCTION__); + free_tdls_sta(padapter, ptdls_sta); + ret = _FAIL; + goto exit; + } + ptdls_sta->TDLS_PeerKey_Lifetime = timeout_interval; + } + } + else + { + txmgmt.status_code = _STATS_INVALID_RSNIE_; + } + + }else{ + txmgmt.status_code = _STATS_SUCCESSFUL_; + } + } + + if (rtw_tdls_is_driver_setup(padapter) == _TRUE) { + _rtw_memcpy(txmgmt.peer, prx_pkt_attrib->src, ETH_ALEN); + issue_tdls_setup_cfm(padapter, &txmgmt); + + if (txmgmt.status_code == _STATS_SUCCESSFUL_) { + ptdlsinfo->link_established = _TRUE; + + if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) { + ptdls_sta->tdls_sta_state |= TDLS_LINKED_STATE; + ptdls_sta->state |= _FW_LINKED; + _cancel_timer_ex( &ptdls_sta->handshake_timer); + } + + if (prx_pkt_attrib->encrypt) + rtw_tdls_set_key(padapter, ptdls_sta); + + rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_ESTABLISHED); + + } + } + +exit: + if (rtw_tdls_is_driver_setup(padapter) == _TRUE) + return ret; + else + return _SUCCESS; + +} + +int On_TDLS_Setup_Cfm(_adapter *padapter, union recv_frame *precv_frame) +{ + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + struct sta_info *ptdls_sta= NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 *ptr = precv_frame->u.hdr.rx_data; + _irqL irqL; + struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; + u8 *psa; + u16 status_code=0; + sint parsing_length; + PNDIS_802_11_VARIABLE_IEs pIE; + u8 FIXED_IE =5; + u8 *pftie=NULL, *ptimeout_ie=NULL, *plinkid_ie=NULL, *prsnie=NULL, *pftie_mic=NULL, *ppairwise_cipher=NULL; + u16 j, pairwise_count; + int ret = _SUCCESS; + + psa = get_sa(ptr); + ptdls_sta = rtw_get_stainfo(pstapriv, psa); + + if (ptdls_sta == NULL) { + DBG_871X("[%s] Direct Link Peer = "MAC_FMT" not found\n", __FUNCTION__, MAC_ARG(psa)); + ret = _FAIL; + goto exit; + } + + ptr +=prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len+LLC_HEADER_SIZE+ETH_TYPE_LEN+PAYLOAD_TYPE_LEN; + parsing_length= ((union recv_frame *)precv_frame)->u.hdr.len + -prx_pkt_attrib->hdrlen + -prx_pkt_attrib->iv_len + -prx_pkt_attrib->icv_len + -LLC_HEADER_SIZE + -ETH_TYPE_LEN + -PAYLOAD_TYPE_LEN + -FIXED_IE; + + _rtw_memcpy(&status_code, ptr+2, 2); + + if (status_code!= 0) { + DBG_871X("[%s] status_code = %d\n, free_tdls_sta", __FUNCTION__, status_code); + free_tdls_sta(padapter, ptdls_sta); + ret = _FAIL; + goto exit; + } + + /* Parsing information element */ + for (j = FIXED_IE; j < parsing_length;) { + + pIE = (PNDIS_802_11_VARIABLE_IEs)(ptr + j); + + switch (pIE->ElementID) { + case _RSN_IE_2_: + prsnie = (u8 *)pIE; + break; + case _VENDOR_SPECIFIC_IE_: + if (_rtw_memcmp((u8 *)pIE + 2, WMM_PARA_OUI, 6) == _TRUE) { + /* WMM Parameter ID and OUI */ + ptdls_sta->qos_option = _TRUE; + } + break; + case _FTIE_: + pftie = (u8 *)pIE; + break; + case _TIMEOUT_ITVL_IE_: + ptimeout_ie = (u8 *)pIE; + break; +#ifdef CONFIG_80211N_HT + case _HT_EXTRA_INFO_IE_: + break; +#endif +#ifdef CONFIG_80211AC_VHT + case EID_VHTOperation: + break; + case EID_OpModeNotification: + rtw_process_vht_op_mode_notify(padapter, pIE->data, ptdls_sta); + break; +#endif + case _LINK_ID_IE_: + plinkid_ie = (u8 *)pIE; + break; + default: + break; + } + + j += (pIE->Length + 2); + + } + + if (prx_pkt_attrib->encrypt) { + /* Verify mic in FTIE MIC field */ + if (rtw_tdls_is_driver_setup(padapter) && + (tdls_verify_mic(ptdls_sta->tpk.kck, 3, plinkid_ie, prsnie, ptimeout_ie, pftie) == _FAIL)) { + free_tdls_sta(padapter, ptdls_sta); + ret = _FAIL; + goto exit; + } + } + + if (rtw_tdls_is_driver_setup(padapter)) { + ptdlsinfo->link_established = _TRUE; + + if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) { + ptdls_sta->tdls_sta_state|=TDLS_LINKED_STATE; + ptdls_sta->state |= _FW_LINKED; + _cancel_timer_ex(&ptdls_sta->handshake_timer); + } + + if (prx_pkt_attrib->encrypt) { + rtw_tdls_set_key(padapter, ptdls_sta); + + /* Start TPK timer */ + ptdls_sta->TPK_count = 0; + _set_timer(&ptdls_sta->TPK_timer, ONE_SEC); + } + + rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_ESTABLISHED); + } + +exit: + return ret; + +} + +int On_TDLS_Dis_Req(_adapter *padapter, union recv_frame *precv_frame) +{ + struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta_ap; + u8 *ptr = precv_frame->u.hdr.rx_data; + sint parsing_length; /* Frame body length, without icv_len */ + PNDIS_802_11_VARIABLE_IEs pIE; + u8 FIXED_IE = 3, *dst; + u16 j; + struct tdls_txmgmt txmgmt; + int ret = _SUCCESS; + + if (rtw_tdls_is_driver_setup(padapter) == _FALSE) + goto exit; + + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); + ptr +=prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len+LLC_HEADER_SIZE+ETH_TYPE_LEN+PAYLOAD_TYPE_LEN; + txmgmt.dialog_token = *(ptr+2); + _rtw_memcpy(&txmgmt.peer, precv_frame->u.hdr.attrib.src, ETH_ALEN); + txmgmt.action_code = TDLS_DISCOVERY_RESPONSE; + parsing_length= ((union recv_frame *)precv_frame)->u.hdr.len + -prx_pkt_attrib->hdrlen + -prx_pkt_attrib->iv_len + -prx_pkt_attrib->icv_len + -LLC_HEADER_SIZE + -ETH_TYPE_LEN + -PAYLOAD_TYPE_LEN + -FIXED_IE; + + /* Parsing information element */ + for (j=FIXED_IE; jElementID) { + case _LINK_ID_IE_: + psta_ap = rtw_get_stainfo(pstapriv, pIE->data); + if (psta_ap == NULL) + goto exit; + dst = pIE->data + 12; + if (MacAddr_isBcst(dst) == _FALSE && (_rtw_memcmp(adapter_mac_addr(padapter), dst, 6) == _FALSE)) + goto exit; + break; + default: + break; + } + + j += (pIE->Length + 2); + + } + + issue_tdls_dis_rsp(padapter, &txmgmt, prx_pkt_attrib->privacy); + +exit: + return ret; + +} + +int On_TDLS_Teardown(_adapter *padapter, union recv_frame *precv_frame) +{ + u8 *psa; + u8 *ptr = precv_frame->u.hdr.rx_data; + struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *ptdls_sta= NULL; + _irqL irqL; + u8 reason; + + reason = *(ptr + prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE + ETH_TYPE_LEN + PAYLOAD_TYPE_LEN + 2); + DBG_871X("[TDLS] %s Reason code(%d)\n", __FUNCTION__,reason); + + psa = get_sa(ptr); + + ptdls_sta = rtw_get_stainfo(pstapriv, psa); + if (ptdls_sta != NULL) { + if (rtw_tdls_is_driver_setup(padapter)) + rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_TEARDOWN_STA_LOCALLY); + } + + return _SUCCESS; + +} + +#if 0 +u8 TDLS_check_ch_state(uint state){ + if (state & TDLS_CH_SWITCH_ON_STATE && + state & TDLS_PEER_AT_OFF_STATE) { + if (state & TDLS_PEER_SLEEP_STATE) + return 2; /* U-APSD + ch. switch */ + else + return 1; /* ch. switch */ + }else + return 0; +} +#endif + +int On_TDLS_Peer_Traffic_Indication(_adapter *padapter, union recv_frame *precv_frame) +{ + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + struct sta_info *ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pattrib->src); + u8 *ptr = precv_frame->u.hdr.rx_data; + struct tdls_txmgmt txmgmt; + + ptr +=pattrib->hdrlen + pattrib->iv_len+LLC_HEADER_SIZE+ETH_TYPE_LEN+PAYLOAD_TYPE_LEN; + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); + + if (ptdls_sta != NULL) { + txmgmt.dialog_token = *(ptr+2); + issue_tdls_peer_traffic_rsp(padapter, ptdls_sta, &txmgmt); + //issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->hwaddr, 0, 0, 0); + } else { + DBG_871X("from unknown sta:"MAC_FMT"\n", MAC_ARG(pattrib->src)); + return _FAIL; + } + + return _SUCCESS; +} + +/* We process buffered data for 1. U-APSD, 2. ch. switch, 3. U-APSD + ch. switch here */ +int On_TDLS_Peer_Traffic_Rsp(_adapter *padapter, union recv_frame *precv_frame) +{ + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib; + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->src); + u8 wmmps_ac=0; + /* u8 state=TDLS_check_ch_state(ptdls_sta->tdls_sta_state); */ + int i; + + ptdls_sta->sta_stats.rx_data_pkts++; + + ptdls_sta->tdls_sta_state &= ~(TDLS_WAIT_PTR_STATE); + + /* Check 4-AC queue bit */ + if (ptdls_sta->uapsd_vo || ptdls_sta->uapsd_vi || ptdls_sta->uapsd_be || ptdls_sta->uapsd_bk) + wmmps_ac=1; + + /* If it's a direct link and have buffered frame */ + if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) { + if (wmmps_ac) { + _irqL irqL; + _list *xmitframe_plist, *xmitframe_phead; + struct xmit_frame *pxmitframe=NULL; + + _enter_critical_bh(&ptdls_sta->sleep_q.lock, &irqL); + + xmitframe_phead = get_list_head(&ptdls_sta->sleep_q); + xmitframe_plist = get_next(xmitframe_phead); + + /* transmit buffered frames */ + while (rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist) == _FALSE) { + pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); + xmitframe_plist = get_next(xmitframe_plist); + rtw_list_delete(&pxmitframe->list); + + ptdls_sta->sleepq_len--; + ptdls_sta->sleepq_ac_len--; + if (ptdls_sta->sleepq_len>0) { + pxmitframe->attrib.mdata = 1; + pxmitframe->attrib.eosp = 0; + } else { + pxmitframe->attrib.mdata = 0; + pxmitframe->attrib.eosp = 1; + } + pxmitframe->attrib.triggered = 1; + + rtw_hal_xmitframe_enqueue(padapter, pxmitframe); + } + + if (ptdls_sta->sleepq_len==0) + DBG_871X("no buffered packets for tdls to xmit\n"); + else { + DBG_871X("error!psta->sleepq_len=%d\n", ptdls_sta->sleepq_len); + ptdls_sta->sleepq_len=0; + } + + _exit_critical_bh(&ptdls_sta->sleep_q.lock, &irqL); + + } + + } + + return _SUCCESS; +} + +#ifdef CONFIG_TDLS_CH_SW +sint On_TDLS_Ch_Switch_Req(_adapter *padapter, union recv_frame *precv_frame) +{ + struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info; + struct sta_info *ptdls_sta= NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 *ptr = precv_frame->u.hdr.rx_data; + struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; + u8 *psa; + sint parsing_length; + PNDIS_802_11_VARIABLE_IEs pIE; + u8 FIXED_IE = 4; + u16 j; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct tdls_txmgmt txmgmt; + u8 zaddr[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + u16 switch_time= TDLS_CH_SWITCH_TIME * 1000, switch_timeout=TDLS_CH_SWITCH_TIMEOUT * 1000; + u8 take_care_iqk; + + if (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) + { DBG_871X("[TDLS] Ignore %s since channel switch is not allowed\n", __FUNCTION__); + return _FAIL; + } + + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); + psa = get_sa(ptr); + ptdls_sta = rtw_get_stainfo(pstapriv, psa); + + if (ptdls_sta == NULL) { + DBG_871X("[%s] Direct Link Peer = "MAC_FMT" not found\n", __FUNCTION__, MAC_ARG(psa)); + return _FAIL; + } + + ptdls_sta->ch_switch_time=switch_time; + ptdls_sta->ch_switch_timeout=switch_timeout; + + ptr +=prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len+LLC_HEADER_SIZE+ETH_TYPE_LEN+PAYLOAD_TYPE_LEN; + parsing_length= ((union recv_frame *)precv_frame)->u.hdr.len + -prx_pkt_attrib->hdrlen + -prx_pkt_attrib->iv_len + -prx_pkt_attrib->icv_len + -LLC_HEADER_SIZE + -ETH_TYPE_LEN + -PAYLOAD_TYPE_LEN + -FIXED_IE; + + pchsw_info->off_ch_num = *(ptr + 2); + + if ((*(ptr + 2) == 2) && (hal_is_band_support(padapter, BAND_ON_5G))) { + pchsw_info->off_ch_num = 44; + } + + if (pchsw_info->off_ch_num != pmlmeext->cur_channel) { + pchsw_info->delay_switch_back = _FALSE; + } + + /* Parsing information element */ + for (j=FIXED_IE; jElementID) { + case EID_SecondaryChnlOffset: + switch (*(pIE->data)) + { + case EXTCHNL_OFFSET_UPPER: + pchsw_info->ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; + break; + + case EXTCHNL_OFFSET_LOWER: + pchsw_info->ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; + break; + + default: + pchsw_info->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; + } + break; + case _LINK_ID_IE_: + break; + case _CH_SWITCH_TIMING_: + ptdls_sta->ch_switch_time = (RTW_GET_LE16(pIE->data) >= TDLS_CH_SWITCH_TIME * 1000) ? + RTW_GET_LE16(pIE->data) : TDLS_CH_SWITCH_TIME * 1000; + ptdls_sta->ch_switch_timeout = (RTW_GET_LE16(pIE->data + 2) >= TDLS_CH_SWITCH_TIMEOUT * 1000) ? + RTW_GET_LE16(pIE->data + 2) : TDLS_CH_SWITCH_TIMEOUT * 1000; + DBG_871X("[TDLS] %s ch_switch_time:%d, ch_switch_timeout:%d\n" + , __FUNCTION__, RTW_GET_LE16(pIE->data), RTW_GET_LE16(pIE->data + 2)); + default: + break; + } + + j += (pIE->Length + 2); + } + + rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk); + if (take_care_iqk == _TRUE) { + u8 central_chnl; + u8 bw_mode; + + bw_mode = (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20; + central_chnl = rtw_get_center_ch(pchsw_info->off_ch_num, bw_mode, pchsw_info->ch_offset); + if (rtw_hal_ch_sw_iqk_info_search(padapter, central_chnl, bw_mode) < 0) { + if (!(pchsw_info->ch_sw_state & TDLS_CH_SWITCH_PREPARE_STATE)) + rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_PREPARE); + + return _FAIL; + } + } + + /* cancel ch sw monitor timer for responder */ + if (!(pchsw_info->ch_sw_state & TDLS_CH_SW_INITIATOR_STATE)) + _cancel_timer_ex(&ptdls_sta->ch_sw_monitor_timer); + + /* Todo: check status */ + txmgmt.status_code = 0; + _rtw_memcpy(txmgmt.peer, psa, ETH_ALEN); + + if (_rtw_memcmp(pchsw_info->addr, zaddr, ETH_ALEN) == _TRUE) + _rtw_memcpy(pchsw_info->addr, ptdls_sta->hwaddr, ETH_ALEN); + + if (ATOMIC_READ(&pchsw_info->chsw_on) == _FALSE) + rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_START); + + rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_RESP); + + return _SUCCESS; +} + +sint On_TDLS_Ch_Switch_Rsp(_adapter *padapter, union recv_frame *precv_frame) +{ + struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info; + struct sta_info *ptdls_sta= NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 *ptr = precv_frame->u.hdr.rx_data; + struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; + u8 *psa; + sint parsing_length; + PNDIS_802_11_VARIABLE_IEs pIE; + u8 FIXED_IE = 4; + u16 status_code, j, switch_time, switch_timeout; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + int ret = _SUCCESS; + + if (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) + { DBG_871X("[TDLS] Ignore %s since channel switch is not allowed\n", __FUNCTION__); + return _SUCCESS; + } + + psa = get_sa(ptr); + ptdls_sta = rtw_get_stainfo(pstapriv, psa); + + if (ptdls_sta == NULL) { + DBG_871X("[%s] Direct Link Peer = "MAC_FMT" not found\n", __FUNCTION__, MAC_ARG(psa)); + return _FAIL; + } + + /* If we receive Unsolicited TDLS Channel Switch Response when channel switch is running, */ + /* we will go back to base channel and terminate this channel switch procedure */ + if (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE) { + if (pmlmeext->cur_channel != rtw_get_oper_ch(padapter)) { + DBG_871X("[TDLS] Rx unsolicited channel switch response \n"); + rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_TO_BASE_CHNL); + goto exit; + } + } + + ptr +=prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE+ETH_TYPE_LEN+PAYLOAD_TYPE_LEN; + parsing_length = ((union recv_frame *)precv_frame)->u.hdr.len + -prx_pkt_attrib->hdrlen + -prx_pkt_attrib->iv_len + -prx_pkt_attrib->icv_len + -LLC_HEADER_SIZE + -ETH_TYPE_LEN + -PAYLOAD_TYPE_LEN + -FIXED_IE; + + _rtw_memcpy(&status_code, ptr+2, 2); + + if (status_code != 0) { + DBG_871X("[TDLS] %s status_code:%d\n", __FUNCTION__, status_code); + pchsw_info->ch_sw_state &= ~(TDLS_CH_SW_INITIATOR_STATE); + rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_END); + ret = _FAIL; + goto exit; + } + + /* Parsing information element */ + for (j = FIXED_IE; j < parsing_length;) { + pIE = (PNDIS_802_11_VARIABLE_IEs)(ptr+ j); + + switch (pIE->ElementID) { + case _LINK_ID_IE_: + break; + case _CH_SWITCH_TIMING_: + _rtw_memcpy(&switch_time, pIE->data, 2); + if (switch_time > ptdls_sta->ch_switch_time) + _rtw_memcpy(&ptdls_sta->ch_switch_time, &switch_time, 2); + + _rtw_memcpy(&switch_timeout, pIE->data + 2, 2); + if (switch_timeout > ptdls_sta->ch_switch_timeout) + _rtw_memcpy(&ptdls_sta->ch_switch_timeout, &switch_timeout, 2); + break; + default: + break; + } + + j += (pIE->Length + 2); + } + + if ((pmlmeext->cur_channel == rtw_get_oper_ch(padapter)) && + (pchsw_info->ch_sw_state & TDLS_WAIT_CH_RSP_STATE)) { + if (ATOMIC_READ(&pchsw_info->chsw_on) == _TRUE) + rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_TO_OFF_CHNL); + } + +exit: + return ret; +} +#endif /* CONFIG_TDLS_CH_SW */ + +#ifdef CONFIG_WFD +void wfd_ie_tdls(_adapter * padapter, u8 *pframe, u32 *pktlen ) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wifi_display_info *pwfd_info = padapter->tdlsinfo.wfd_info; + u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; + u32 wfdielen = 0; + + if (!hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) + return; + + /* WFD OUI */ + wfdielen = 0; + wfdie[ wfdielen++ ] = 0x50; + wfdie[ wfdielen++ ] = 0x6F; + wfdie[ wfdielen++ ] = 0x9A; + wfdie[ wfdielen++ ] = 0x0A; /* WFA WFD v1.0 */ + + /* + * Commented by Albert 20110825 + * According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes + * 1. WFD Device Information + * 2. Associated BSSID ( Optional ) + * 3. Local IP Adress ( Optional ) + */ + + /* WFD Device Information ATTR */ + /* Type: */ + wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + /* Value1: */ + /* WFD device information */ + /* available for WFD session + Preferred TDLS + WSD ( WFD Service Discovery ) */ + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->wfd_device_type | WFD_DEVINFO_SESSION_AVAIL + | WFD_DEVINFO_PC_TDLS | WFD_DEVINFO_WSD); + wfdielen += 2; + + /* Value2: */ + /* Session Management Control Port */ + /* Default TCP port for RTSP messages is 554 */ + RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->tdls_rtsp_ctrlport); + wfdielen += 2; + + /* Value3: */ + /* WFD Device Maximum Throughput */ + /* 300Mbps is the maximum throughput */ + RTW_PUT_BE16(wfdie + wfdielen, 300); + wfdielen += 2; + + /* Associated BSSID ATTR */ + /* Type: */ + wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0006); + wfdielen += 2; + + /* Value: */ + /* Associated BSSID */ + if (check_fwstate( pmlmepriv, _FW_LINKED) == _TRUE) + _rtw_memcpy(wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN); + else + _rtw_memset(wfdie + wfdielen, 0x00, ETH_ALEN); + + /* Local IP Address ATTR */ + wfdie[ wfdielen++ ] = WFD_ATTR_LOCAL_IP_ADDR; + + /* Length: */ + /* Note: In the WFD specification, the size of length field is 2. */ + RTW_PUT_BE16(wfdie + wfdielen, 0x0005); + wfdielen += 2; + + /* Version: */ + /* 0x01: Version1;IPv4 */ + wfdie[ wfdielen++ ] = 0x01; + + /* IPv4 Address */ + _rtw_memcpy( wfdie + wfdielen, pwfd_info->ip_address, 4 ); + wfdielen += 4; + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, pktlen); + +} +#endif /* CONFIG_WFD */ + +void rtw_build_tdls_setup_req_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +{ + struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct sta_info *ptdls_sta=rtw_get_stainfo( (&padapter->stapriv) , pattrib->dst); + + int i = 0 ; + u32 time; + u8 *pframe_head; + + /* SNonce */ + if (pattrib->encrypt) { + for (i=0;i<8;i++) { + time=rtw_get_current_time(); + _rtw_memcpy(&ptdls_sta->SNonce[4*i], (u8 *)&time, 4); + } + } + + pframe_head = pframe; /* For rtw_tdls_set_ht_cap() */ + + pframe = rtw_tdls_set_payload_type(pframe, pattrib); + pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS); + pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt); + pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt); + + pframe = rtw_tdls_set_capability(padapter, pframe, pattrib); + pframe = rtw_tdls_set_supported_rate(padapter, pframe, pattrib); + pframe = rtw_tdls_set_sup_ch(&(padapter->mlmeextpriv), pframe, pattrib); + pframe = rtw_tdls_set_sup_reg_class(pframe, pattrib); + + if (pattrib->encrypt) + pframe = rtw_tdls_set_rsnie(ptxmgmt, pframe, pattrib, _TRUE, ptdls_sta); + + pframe = rtw_tdls_set_ext_cap(pframe, pattrib); + + if (pattrib->encrypt) { + pframe = rtw_tdls_set_ftie(ptxmgmt + , pframe + , pattrib + , NULL + , ptdls_sta->SNonce); + + pframe = rtw_tdls_set_timeout_interval(ptxmgmt, pframe, pattrib, _TRUE, ptdls_sta); + } + +#ifdef CONFIG_80211N_HT + /* Sup_reg_classes(optional) */ + if (pregistrypriv->ht_enable == _TRUE) + pframe = rtw_tdls_set_ht_cap(padapter, pframe_head, pattrib); +#endif + + pframe = rtw_tdls_set_bss_coexist(padapter, pframe, pattrib); + + pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE); + + if ((pregistrypriv->wmm_enable == _TRUE) || (padapter->mlmepriv.htpriv.ht_option == _TRUE)) + pframe = rtw_tdls_set_qos_cap(pframe, pattrib); + +#ifdef CONFIG_80211AC_VHT + if ((padapter->mlmepriv.htpriv.ht_option == _TRUE) && (pmlmeext->cur_channel > 14) + && REGSTY_IS_11AC_ENABLE(pregistrypriv) + && hal_chk_proto_cap(padapter, PROTO_CAP_11AC) + && (!padapter->mlmepriv.country_ent || COUNTRY_CHPLAN_EN_11AC(padapter->mlmepriv.country_ent)) + ) { + pframe = rtw_tdls_set_aid(padapter, pframe, pattrib); + pframe = rtw_tdls_set_vht_cap(padapter, pframe, pattrib); + } +#endif + +#ifdef CONFIG_WFD + if (padapter->wdinfo.wfd_tdls_enable == 1) + wfd_ie_tdls(padapter, pframe, &(pattrib->pktlen)); +#endif + +} + +void rtw_build_tdls_setup_rsp_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +{ + struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct sta_info *ptdls_sta; + u8 k; /* for random ANonce */ + u8 *pftie=NULL, *ptimeout_ie = NULL, *plinkid_ie = NULL, *prsnie = NULL, *pftie_mic = NULL; + u32 time; + u8 *pframe_head; + + ptdls_sta = rtw_get_stainfo( &(padapter->stapriv) , pattrib->dst); + + if (ptdls_sta == NULL) + DBG_871X("[%s] %d ptdls_sta is NULL\n", __FUNCTION__, __LINE__); + + if (pattrib->encrypt && ptdls_sta != NULL) { + for (k=0;k<8;k++) { + time = rtw_get_current_time(); + _rtw_memcpy(&ptdls_sta->ANonce[4*k], (u8*)&time, 4); + } + } + + pframe_head = pframe; + + pframe = rtw_tdls_set_payload_type(pframe, pattrib); + pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS); + pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt); + pframe = rtw_tdls_set_status_code(pframe, pattrib, ptxmgmt); + + if (ptxmgmt->status_code != 0) { + DBG_871X("[%s] status_code:%04x \n", __FUNCTION__, ptxmgmt->status_code); + return; + } + + pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt); + pframe = rtw_tdls_set_capability(padapter, pframe, pattrib); + pframe = rtw_tdls_set_supported_rate(padapter, pframe, pattrib); + pframe = rtw_tdls_set_sup_ch(&(padapter->mlmeextpriv), pframe, pattrib); + pframe = rtw_tdls_set_sup_reg_class(pframe, pattrib); + + if (pattrib->encrypt) { + prsnie = pframe; + pframe = rtw_tdls_set_rsnie(ptxmgmt, pframe, pattrib, _FALSE, ptdls_sta); + } + + pframe = rtw_tdls_set_ext_cap(pframe, pattrib); + + if (pattrib->encrypt) { + if (rtw_tdls_is_driver_setup(padapter) == _TRUE) + wpa_tdls_generate_tpk(padapter, ptdls_sta); + + pftie = pframe; + pftie_mic = pframe+4; + pframe = rtw_tdls_set_ftie(ptxmgmt + , pframe + , pattrib + , ptdls_sta->ANonce + , ptdls_sta->SNonce); + + ptimeout_ie = pframe; + pframe = rtw_tdls_set_timeout_interval(ptxmgmt, pframe, pattrib, _FALSE, ptdls_sta); + } + +#ifdef CONFIG_80211N_HT + /* Sup_reg_classes(optional) */ + if (pregistrypriv->ht_enable == _TRUE) + pframe = rtw_tdls_set_ht_cap(padapter, pframe_head, pattrib); +#endif + + pframe = rtw_tdls_set_bss_coexist(padapter, pframe, pattrib); + + plinkid_ie = pframe; + pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE); + + /* Fill FTIE mic */ + if (pattrib->encrypt && rtw_tdls_is_driver_setup(padapter) == _TRUE) + wpa_tdls_ftie_mic(ptdls_sta->tpk.kck, 2, plinkid_ie, prsnie, ptimeout_ie, pftie, pftie_mic); + + if ((pregistrypriv->wmm_enable == _TRUE) || (padapter->mlmepriv.htpriv.ht_option == _TRUE)) + pframe = rtw_tdls_set_qos_cap(pframe, pattrib); + +#ifdef CONFIG_80211AC_VHT + if ((padapter->mlmepriv.htpriv.ht_option == _TRUE) && (pmlmeext->cur_channel > 14) + && REGSTY_IS_11AC_ENABLE(pregistrypriv) + && hal_chk_proto_cap(padapter, PROTO_CAP_11AC) + && (!padapter->mlmepriv.country_ent || COUNTRY_CHPLAN_EN_11AC(padapter->mlmepriv.country_ent)) + ) { + pframe = rtw_tdls_set_aid(padapter, pframe, pattrib); + pframe = rtw_tdls_set_vht_cap(padapter, pframe, pattrib); + pframe = rtw_tdls_set_vht_op_mode_notify(padapter, pframe, pattrib, pmlmeext->cur_bwmode); + } +#endif + +#ifdef CONFIG_WFD + if (padapter->wdinfo.wfd_tdls_enable) + wfd_ie_tdls(padapter, pframe, &(pattrib->pktlen)); +#endif + +} + +void rtw_build_tdls_setup_cfm_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +{ + struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct sta_info *ptdls_sta=rtw_get_stainfo( (&padapter->stapriv) , pattrib->dst); + + unsigned int ie_len; + unsigned char *p; + u8 wmm_param_ele[24] = {0}; + u8 *pftie=NULL, *ptimeout_ie=NULL, *plinkid_ie=NULL, *prsnie=NULL, *pftie_mic=NULL; + + pframe = rtw_tdls_set_payload_type(pframe, pattrib); + pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS); + pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt); + pframe = rtw_tdls_set_status_code(pframe, pattrib, ptxmgmt); + pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt); + + if (ptxmgmt->status_code!=0) + return; + + if (pattrib->encrypt) { + prsnie = pframe; + pframe = rtw_tdls_set_rsnie(ptxmgmt, pframe, pattrib, _TRUE, ptdls_sta); + } + + if (pattrib->encrypt) { + pftie = pframe; + pftie_mic = pframe+4; + pframe = rtw_tdls_set_ftie(ptxmgmt + , pframe + , pattrib + , ptdls_sta->ANonce + , ptdls_sta->SNonce); + + ptimeout_ie = pframe; + pframe = rtw_tdls_set_timeout_interval(ptxmgmt, pframe, pattrib, _TRUE, ptdls_sta); + + if (rtw_tdls_is_driver_setup(padapter) == _TRUE) { + /* Start TPK timer */ + ptdls_sta->TPK_count=0; + _set_timer(&ptdls_sta->TPK_timer, ONE_SEC); + } + } + + /* HT operation; todo */ + + plinkid_ie = pframe; + pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE); + + if (pattrib->encrypt && (rtw_tdls_is_driver_setup(padapter) == _TRUE)) + wpa_tdls_ftie_mic(ptdls_sta->tpk.kck, 3, plinkid_ie, prsnie, ptimeout_ie, pftie, pftie_mic); + + if (ptdls_sta->qos_option == _TRUE) + pframe = rtw_tdls_set_wmm_params(padapter, pframe, pattrib); + +#ifdef CONFIG_80211AC_VHT + if ((padapter->mlmepriv.htpriv.ht_option == _TRUE) + && (ptdls_sta->vhtpriv.vht_option == _TRUE) && (pmlmeext->cur_channel > 14) + && REGSTY_IS_11AC_ENABLE(pregistrypriv) + && hal_chk_proto_cap(padapter, PROTO_CAP_11AC) + && (!padapter->mlmepriv.country_ent || COUNTRY_CHPLAN_EN_11AC(padapter->mlmepriv.country_ent)) + ) { + pframe = rtw_tdls_set_vht_operation(padapter, pframe, pattrib, pmlmeext->cur_channel); + pframe = rtw_tdls_set_vht_op_mode_notify(padapter, pframe, pattrib, pmlmeext->cur_bwmode); + } +#endif +} + +void rtw_build_tdls_teardown_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +{ + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct sta_info *ptdls_sta = rtw_get_stainfo( &(padapter->stapriv) , pattrib->dst); + u8 *pftie = NULL, *pftie_mic = NULL, *plinkid_ie = NULL; + + pframe = rtw_tdls_set_payload_type(pframe, pattrib); + pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS); + pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt); + pframe = rtw_tdls_set_status_code(pframe, pattrib, ptxmgmt); + + if (pattrib->encrypt) { + pftie = pframe; + pftie_mic = pframe + 4; + pframe = rtw_tdls_set_ftie(ptxmgmt + , pframe + , pattrib + , ptdls_sta->ANonce + , ptdls_sta->SNonce); + } + + plinkid_ie = pframe; + if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) + pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE); + else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) + pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE); + + if (pattrib->encrypt && (rtw_tdls_is_driver_setup(padapter) == _TRUE)) + wpa_tdls_teardown_ftie_mic(ptdls_sta->tpk.kck, plinkid_ie, ptxmgmt->status_code, 1, 4, pftie, pftie_mic); +} + +void rtw_build_tdls_dis_req_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +{ + struct pkt_attrib *pattrib = &pxmitframe->attrib; + + pframe = rtw_tdls_set_payload_type(pframe, pattrib); + pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS); + pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt); + pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt); + pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE); + +} + +void rtw_build_tdls_dis_rsp_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, u8 privacy) +{ + struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + u8 *pframe_head, pktlen_index; + + pktlen_index = pattrib->pktlen; + pframe_head = pframe; + + pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_PUBLIC); + pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt); + pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt); + pframe = rtw_tdls_set_capability(padapter, pframe, pattrib); + + pframe = rtw_tdls_set_supported_rate(padapter, pframe, pattrib); + + pframe = rtw_tdls_set_sup_ch(pmlmeext, pframe, pattrib); + + if (privacy) + pframe = rtw_tdls_set_rsnie(ptxmgmt, pframe, pattrib, _TRUE, NULL); + + pframe = rtw_tdls_set_ext_cap(pframe, pattrib); + + if (privacy) { + pframe = rtw_tdls_set_ftie(ptxmgmt, pframe, pattrib, NULL, NULL); + pframe = rtw_tdls_set_timeout_interval(ptxmgmt, pframe, pattrib, _TRUE, NULL); + } + +#ifdef CONFIG_80211N_HT + if (pregistrypriv->ht_enable == _TRUE) + pframe = rtw_tdls_set_ht_cap(padapter, pframe_head - pktlen_index, pattrib); +#endif + + pframe = rtw_tdls_set_bss_coexist(padapter, pframe, pattrib); + pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE); + +} + + +void rtw_build_tdls_peer_traffic_indication_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +{ + + struct pkt_attrib *pattrib = &pxmitframe->attrib; + u8 AC_queue=0; + struct sta_info *ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pattrib->dst); + + pframe = rtw_tdls_set_payload_type(pframe, pattrib); + pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS); + pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt); + pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt); + + if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) + pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE); + else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) + pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE); + + /* PTI control */ + /* PU buffer status */ + if (ptdls_sta->uapsd_bk & BIT(1)) + AC_queue=BIT(0); + if (ptdls_sta->uapsd_be & BIT(1)) + AC_queue=BIT(1); + if (ptdls_sta->uapsd_vi & BIT(1)) + AC_queue=BIT(2); + if (ptdls_sta->uapsd_vo & BIT(1)) + AC_queue=BIT(3); + pframe = rtw_set_ie(pframe, _PTI_BUFFER_STATUS_, 1, &AC_queue, &(pattrib->pktlen)); + +} + +void rtw_build_tdls_peer_traffic_rsp_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +{ + + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct sta_info *ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pattrib->dst); + + pframe = rtw_tdls_set_payload_type(pframe, pattrib); + pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS); + pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt); + pframe = rtw_tdls_set_dialog(pframe, pattrib, ptxmgmt); + + if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) + pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE); + else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) + pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE); +} + +#ifdef CONFIG_TDLS_CH_SW +void rtw_build_tdls_ch_switch_req_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +{ + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst); + u16 switch_time= TDLS_CH_SWITCH_TIME * 1000, switch_timeout=TDLS_CH_SWITCH_TIMEOUT * 1000; + + ptdls_sta->ch_switch_time=switch_time; + ptdls_sta->ch_switch_timeout=switch_timeout; + + pframe = rtw_tdls_set_payload_type(pframe, pattrib); + pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS); + pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt); + pframe = rtw_tdls_set_target_ch(padapter, pframe, pattrib); + pframe = rtw_tdls_set_reg_class(pframe, pattrib, ptdls_sta); + + if (ptdlsinfo->chsw_info.ch_offset != HAL_PRIME_CHNL_OFFSET_DONT_CARE) { + switch (ptdlsinfo->chsw_info.ch_offset) + { + case HAL_PRIME_CHNL_OFFSET_LOWER: + pframe = rtw_tdls_set_second_channel_offset(pframe, pattrib, SCA); + break; + case HAL_PRIME_CHNL_OFFSET_UPPER: + pframe = rtw_tdls_set_second_channel_offset(pframe, pattrib, SCB); + break; + } + } + + if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) + pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE); + else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) + pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE); + + pframe = rtw_tdls_set_ch_sw(pframe, pattrib, ptdls_sta); + +} + +void rtw_build_tdls_ch_switch_rsp_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +{ + + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst); + + pframe = rtw_tdls_set_payload_type(pframe, pattrib); + pframe = rtw_tdls_set_category(pframe, pattrib, RTW_WLAN_CATEGORY_TDLS); + pframe = rtw_tdls_set_action(pframe, pattrib, ptxmgmt); + pframe = rtw_tdls_set_status_code(pframe, pattrib, ptxmgmt); + + if (ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE) + pframe = rtw_tdls_set_linkid(pframe, pattrib, _FALSE); + else if (ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE) + pframe = rtw_tdls_set_linkid(pframe, pattrib, _TRUE); + + pframe = rtw_tdls_set_ch_sw(pframe, pattrib, ptdls_sta); +} +#endif + +#ifdef CONFIG_WFD +void rtw_build_tunneled_probe_req_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe) +{ + + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + struct wifidirect_info *pbuddy_wdinfo = &padapter->pbuddy_adapter->wdinfo; + u8 category = RTW_WLAN_CATEGORY_P2P; + u8 WFA_OUI[3] = { 0x50, 0x6f, 0x9a}; + u8 probe_req = 4; + u8 wfdielen = 0; + + pframe = rtw_tdls_set_payload_type(pframe, pattrib); + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 3, WFA_OUI, &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(probe_req), &(pattrib->pktlen)); + + if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { + wfdielen = build_probe_req_wfd_ie(pwdinfo, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; + } else if (!rtw_p2p_chk_state(pbuddy_wdinfo, P2P_STATE_NONE)) { + wfdielen = build_probe_req_wfd_ie(pbuddy_wdinfo, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; + } + +} + +void rtw_build_tunneled_probe_rsp_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe) +{ + + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + struct wifidirect_info *pbuddy_wdinfo = &padapter->pbuddy_adapter->wdinfo; + u8 category = RTW_WLAN_CATEGORY_P2P; + u8 WFA_OUI[3] = { 0x50, 0x6f, 0x9a}; + u8 probe_rsp = 5; + u8 wfdielen = 0; + + pframe = rtw_tdls_set_payload_type(pframe, pattrib); + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 3, WFA_OUI, &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(probe_rsp), &(pattrib->pktlen)); + + if (!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) { + wfdielen = build_probe_resp_wfd_ie(pwdinfo, pframe, 1); + pframe += wfdielen; + pattrib->pktlen += wfdielen; + } else if (!rtw_p2p_chk_state(pbuddy_wdinfo, P2P_STATE_NONE)) { + wfdielen = build_probe_resp_wfd_ie(pbuddy_wdinfo, pframe, 1); + pframe += wfdielen; + pattrib->pktlen += wfdielen; + } + +} +#endif /* CONFIG_WFD */ + +void _tdls_tpk_timer_hdl(void *FunctionContext) +{ + struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext; + struct tdls_txmgmt txmgmt; + + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); + ptdls_sta->TPK_count++; + /* TPK_timer expired in a second */ + /* Retry timer should set at least 301 sec. */ + if (ptdls_sta->TPK_count >= (ptdls_sta->TDLS_PeerKey_Lifetime - 3)) { + DBG_871X("[TDLS] %s, Re-Setup TDLS link with "MAC_FMT" since TPK lifetime expires!\n", __FUNCTION__, MAC_ARG(ptdls_sta->hwaddr)); + ptdls_sta->TPK_count=0; + _rtw_memcpy(txmgmt.peer, ptdls_sta->hwaddr, ETH_ALEN); + issue_tdls_setup_req(ptdls_sta->padapter, &txmgmt, _FALSE); + } + + _set_timer(&ptdls_sta->TPK_timer, ONE_SEC); +} + +#ifdef CONFIG_TDLS_CH_SW +void _tdls_ch_switch_timer_hdl(void *FunctionContext) +{ + struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext; + _adapter *padapter = ptdls_sta->padapter; + struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info; + + rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_END_TO_BASE_CHNL); + DBG_871X("[TDLS] %s, can't get traffic from op_ch:%d\n", __FUNCTION__, rtw_get_oper_ch(padapter)); +} + +void _tdls_delay_timer_hdl(void *FunctionContext) +{ + struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext; + _adapter *padapter = ptdls_sta->padapter; + struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info; + + DBG_871X("[TDLS] %s, op_ch:%d, tdls_state:0x%08x\n", __FUNCTION__, rtw_get_oper_ch(padapter), ptdls_sta->tdls_sta_state); + pchsw_info->delay_switch_back = _TRUE; +} + +void _tdls_stay_on_base_chnl_timer_hdl(void *FunctionContext) +{ + struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext; + _adapter *padapter = ptdls_sta->padapter; + struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info; + + if (ptdls_sta != NULL) { + issue_tdls_ch_switch_req(padapter, ptdls_sta); + pchsw_info->ch_sw_state |= TDLS_WAIT_CH_RSP_STATE; + } +} + +void _tdls_ch_switch_monitor_timer_hdl(void *FunctionContext) +{ + struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext; + _adapter *padapter = ptdls_sta->padapter; + struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info; + + rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_END); + DBG_871X("[TDLS] %s, does not receive ch sw req\n", __FUNCTION__); +} + +#endif + +void _tdls_handshake_timer_hdl(void *FunctionContext) +{ + struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext; + _adapter *padapter = ptdls_sta->padapter; + struct tdls_txmgmt txmgmt; + + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); + _rtw_memcpy(txmgmt.peer, ptdls_sta->hwaddr, ETH_ALEN); + txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_; + + if (ptdls_sta != NULL) { + DBG_871X("[TDLS] Handshake time out\n"); + if (ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) + { + rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_TEARDOWN_STA); + } + else + { + rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_TEARDOWN_STA_LOCALLY); + } + } +} + +void _tdls_pti_timer_hdl(void *FunctionContext) +{ + struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext; + _adapter *padapter = ptdls_sta->padapter; + struct tdls_txmgmt txmgmt; + + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); + _rtw_memcpy(txmgmt.peer, ptdls_sta->hwaddr, ETH_ALEN); + txmgmt.status_code = _RSON_TDLS_TEAR_TOOFAR_; + + if (ptdls_sta != NULL) { + if (ptdls_sta->tdls_sta_state & TDLS_WAIT_PTR_STATE) { + DBG_871X("[TDLS] Doesn't receive PTR from peer dev:"MAC_FMT"; " + "Send TDLS Tear Down\n", MAC_ARG(ptdls_sta->hwaddr)); + issue_tdls_teardown(padapter, &txmgmt, _FALSE); + } + } +} + +void rtw_init_tdls_timer(_adapter *padapter, struct sta_info *psta) +{ + psta->padapter=padapter; + _init_timer(&psta->TPK_timer, padapter->pnetdev, _tdls_tpk_timer_hdl, psta); +#ifdef CONFIG_TDLS_CH_SW + _init_timer(&psta->ch_sw_timer, padapter->pnetdev, _tdls_ch_switch_timer_hdl, psta); + _init_timer(&psta->delay_timer, padapter->pnetdev, _tdls_delay_timer_hdl, psta); + _init_timer(&psta->stay_on_base_chnl_timer, padapter->pnetdev, _tdls_stay_on_base_chnl_timer_hdl, psta); + _init_timer(&psta->ch_sw_monitor_timer, padapter->pnetdev, _tdls_ch_switch_monitor_timer_hdl, psta); +#endif + _init_timer(&psta->handshake_timer, padapter->pnetdev, _tdls_handshake_timer_hdl, psta); + _init_timer(&psta->pti_timer, padapter->pnetdev, _tdls_pti_timer_hdl, psta); +} + +void rtw_free_tdls_timer(struct sta_info *psta) +{ + _cancel_timer_ex(&psta->TPK_timer); +#ifdef CONFIG_TDLS_CH_SW + _cancel_timer_ex(&psta->ch_sw_timer); + _cancel_timer_ex(&psta->delay_timer); + _cancel_timer_ex(&psta->stay_on_base_chnl_timer); + _cancel_timer_ex(&psta->ch_sw_monitor_timer); +#endif + _cancel_timer_ex(&psta->handshake_timer); + _cancel_timer_ex(&psta->pti_timer); +} + +u8 update_sgi_tdls(_adapter *padapter, struct sta_info *psta) +{ + return query_ra_short_GI(psta); +} + +u32 update_mask_tdls(_adapter *padapter, struct sta_info *psta) +{ + unsigned char sta_band = 0; + unsigned int tx_ra_bitmap=0; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; + + rtw_hal_update_sta_rate_mask(padapter, psta); + tx_ra_bitmap = psta->ra_mask; + + if (pcur_network->Configuration.DSConfig > 14) { + if (tx_ra_bitmap & 0xffff000) + sta_band |= WIRELESS_11_5N | WIRELESS_11A; + else + sta_band |= WIRELESS_11A; + } else { + if (tx_ra_bitmap & 0xffff000) + sta_band |= WIRELESS_11_24N | WIRELESS_11G | WIRELESS_11B; + else if (tx_ra_bitmap & 0xff0) + sta_band |= WIRELESS_11G |WIRELESS_11B; + else + sta_band |= WIRELESS_11B; + } + + psta->wireless_mode = sta_band; + + psta->raid = rtw_hal_networktype_to_raid(padapter,psta); + tx_ra_bitmap |= ((psta->raid<<28)&0xf0000000); + return tx_ra_bitmap; +} + +int rtw_tdls_is_driver_setup(_adapter *padapter) +{ + return padapter->tdlsinfo.driver_setup; +} + +const char * rtw_tdls_action_txt(enum TDLS_ACTION_FIELD action) +{ + switch (action) { + case TDLS_SETUP_REQUEST: + return "TDLS_SETUP_REQUEST"; + case TDLS_SETUP_RESPONSE: + return "TDLS_SETUP_RESPONSE"; + case TDLS_SETUP_CONFIRM: + return "TDLS_SETUP_CONFIRM"; + case TDLS_TEARDOWN: + return "TDLS_TEARDOWN"; + case TDLS_PEER_TRAFFIC_INDICATION: + return "TDLS_PEER_TRAFFIC_INDICATION"; + case TDLS_CHANNEL_SWITCH_REQUEST: + return "TDLS_CHANNEL_SWITCH_REQUEST"; + case TDLS_CHANNEL_SWITCH_RESPONSE: + return "TDLS_CHANNEL_SWITCH_RESPONSE"; + case TDLS_PEER_PSM_REQUEST: + return "TDLS_PEER_PSM_REQUEST"; + case TDLS_PEER_PSM_RESPONSE: + return "TDLS_PEER_PSM_RESPONSE"; + case TDLS_PEER_TRAFFIC_RESPONSE: + return "TDLS_PEER_TRAFFIC_RESPONSE"; + case TDLS_DISCOVERY_REQUEST: + return "TDLS_DISCOVERY_REQUEST"; + case TDLS_DISCOVERY_RESPONSE: + return "TDLS_DISCOVERY_RESPONSE"; + default: + return "UNKNOWN"; + } +} + +#endif /* CONFIG_TDLS */ diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_vht.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_vht.c new file mode 100644 index 000000000..18a4d7a63 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_vht.c @@ -0,0 +1,819 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_VHT_C + +#include + +#ifdef CONFIG_80211AC_VHT +// 20/40/80, ShortGI, MCS Rate +const u16 VHT_MCS_DATA_RATE[3][2][30] = + { { {13, 26, 39, 52, 78, 104, 117, 130, 156, 156, + 26, 52, 78, 104, 156, 208, 234, 260, 312, 312, + 39, 78, 117, 156, 234, 312, 351, 390, 468, 520}, // Long GI, 20MHz + {14, 29, 43, 58, 87, 116, 130, 144, 173, 173, + 29, 58, 87, 116, 173, 231, 260, 289, 347, 347, + 43, 87, 130, 173, 260, 347,390, 433, 520, 578} }, // Short GI, 20MHz + { {27, 54, 81, 108, 162, 216, 243, 270, 324, 360, + 54, 108, 162, 216, 324, 432, 486, 540, 648, 720, + 81, 162, 243, 324, 486, 648, 729, 810, 972, 1080}, // Long GI, 40MHz + {30, 60, 90, 120, 180, 240, 270, 300,360, 400, + 60, 120, 180, 240, 360, 480, 540, 600, 720, 800, + 90, 180, 270, 360, 540, 720, 810, 900, 1080, 1200}}, // Short GI, 40MHz + { {59, 117, 176, 234, 351, 468, 527, 585, 702, 780, + 117, 234, 351, 468, 702, 936, 1053, 1170, 1404, 1560, + 176, 351, 527, 702, 1053, 1404, 1580, 1755, 2106, 2340}, /* Long GI, 80MHz */ + {65, 130, 195, 260, 390, 520, 585, 650, 780, 867, + 130, 260, 390, 520, 780, 1040, 1170, 1300, 1560,1734, + 195, 390, 585, 780, 1170, 1560, 1755, 1950, 2340, 2600} } /* Short GI, 80MHz */ + }; + +u8 rtw_get_vht_highest_rate(u8 *pvht_mcs_map) +{ + u8 i, j; + u8 bit_map; + u8 vht_mcs_rate = 0; + + for(i = 0; i < 2; i++) + { + if(pvht_mcs_map[i] != 0xff) + { + for(j = 0; j < 8; j += 2) + { + bit_map = (pvht_mcs_map[i] >> j) & 3; + + if(bit_map != 3) + vht_mcs_rate = MGN_VHT1SS_MCS7 + 10*j/2 + i*40 + bit_map; //VHT rate indications begin from 0x90 + } + } + } + + /* DBG_871X("HighestVHTMCSRate is %x\n", vht_mcs_rate); */ + return vht_mcs_rate; +} + +u8 rtw_vht_mcsmap_to_nss(u8 *pvht_mcs_map) +{ + u8 i, j; + u8 bit_map; + u8 nss = 0; + + for(i = 0; i < 2; i++) + { + if(pvht_mcs_map[i] != 0xff) + { + for(j = 0; j < 8; j += 2) + { + bit_map = (pvht_mcs_map[i] >> j) & 3; + + if(bit_map != 3) + nss++; + } + } + } + + /* DBG_871X("%s : %dSS\n", __FUNCTION__, nss); */ + return nss; +} + +void rtw_vht_nss_to_mcsmap(u8 nss, u8 *target_mcs_map, u8 *cur_mcs_map) +{ + u8 i, j; + u8 cur_rate, target_rate; + + for(i = 0; i < 2; i++) + { + target_mcs_map[i] = 0; + for(j = 0; j < 8; j+=2) + { + cur_rate = (cur_mcs_map[i] >> j) & 3; + if(cur_rate == 3) //0x3 indicates not supported that num of SS + target_rate = 3; + else if(nss <= ((j/2)+i*4)) + target_rate = 3; + else + target_rate = cur_rate; + + target_mcs_map[i] |= (target_rate << j); + } + } + + //DBG_871X("%s : %dSS\n", __FUNCTION__, nss); +} + +u16 rtw_vht_mcs_to_data_rate(u8 bw, u8 short_GI, u8 vht_mcs_rate) +{ + if(vht_mcs_rate > MGN_VHT3SS_MCS9) + vht_mcs_rate = MGN_VHT3SS_MCS9; + /* DBG_871X("bw=%d, short_GI=%d, ((vht_mcs_rate - MGN_VHT1SS_MCS0)&0x3f)=%d\n", bw, short_GI, ((vht_mcs_rate - MGN_VHT1SS_MCS0)&0x3f)); */ + return VHT_MCS_DATA_RATE[bw][short_GI][((vht_mcs_rate - MGN_VHT1SS_MCS0)&0x3f)]; +} + +void rtw_vht_use_default_setting(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + BOOLEAN bHwLDPCSupport = _FALSE, bHwSTBCSupport = _FALSE; + BOOLEAN bHwSupportBeamformer = _FALSE, bHwSupportBeamformee = _FALSE; + u8 rf_type = 0; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + pvhtpriv->sgi_80m = TEST_FLAG(pregistrypriv->short_gi, BIT2) ? _TRUE : _FALSE; + + // LDPC support + rtw_hal_get_def_var(padapter, HAL_DEF_RX_LDPC, (u8 *)&bHwLDPCSupport); + CLEAR_FLAGS(pvhtpriv->ldpc_cap); + if(bHwLDPCSupport) + { + if(TEST_FLAG(pregistrypriv->ldpc_cap, BIT0)) + SET_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX); + } + rtw_hal_get_def_var(padapter, HAL_DEF_TX_LDPC, (u8 *)&bHwLDPCSupport); + if(bHwLDPCSupport) + { + if(TEST_FLAG(pregistrypriv->ldpc_cap, BIT1)) + SET_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX); + } + if (pvhtpriv->ldpc_cap) + DBG_871X("[VHT] Support LDPC = 0x%02X\n", pvhtpriv->ldpc_cap); + + // STBC + rtw_hal_get_def_var(padapter, HAL_DEF_TX_STBC, (u8 *)&bHwSTBCSupport); + CLEAR_FLAGS(pvhtpriv->stbc_cap); + if(bHwSTBCSupport) + { + if(TEST_FLAG(pregistrypriv->stbc_cap, BIT1)) + SET_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX); + } + rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)&bHwSTBCSupport); + if(bHwSTBCSupport) + { + if(TEST_FLAG(pregistrypriv->stbc_cap, BIT0)) + SET_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX); + } + if (pvhtpriv->stbc_cap) + DBG_871X("[VHT] Support STBC = 0x%02X\n", pvhtpriv->stbc_cap); + + // Beamforming setting + rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMER, (u8 *)&bHwSupportBeamformer); + rtw_hal_get_def_var(padapter, HAL_DEF_EXPLICIT_BEAMFORMEE, (u8 *)&bHwSupportBeamformee); + CLEAR_FLAGS(pvhtpriv->beamform_cap); + if (TEST_FLAG(pregistrypriv->beamform_cap, BIT0) && bHwSupportBeamformer) { + #ifdef CONFIG_CONCURRENT_MODE + if ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) { + SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE); + DBG_871X("[VHT] CONCURRENT AP Support Beamformer\n"); + } else + DBG_871X("[VHT] CONCURRENT not AP ;not allow Support Beamformer\n"); + #else + SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE); + DBG_871X("[VHT] Support Beamformer\n"); + #endif + } + if(TEST_FLAG(pregistrypriv->beamform_cap, BIT1) && bHwSupportBeamformee) + { + SET_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE); + DBG_871X("[VHT] Support Beamformee\n"); + } + + pvhtpriv->ampdu_len = pregistrypriv->ampdu_factor; + + rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + + if (rf_type == RF_3T3R) + pvhtpriv->vht_mcs_map[0] = 0xea; /* support 1SS MCS 0~9 2SS MCS 0~9 3SS MCS 0~9 */ + else if(rf_type == RF_2T2R) + pvhtpriv->vht_mcs_map[0] = 0xfa; /* support 1SS MCS 0~9 2SS MCS 0~9 */ + else + pvhtpriv->vht_mcs_map[0] = 0xfe; /* Only support 1SS MCS 0~9; */ + pvhtpriv->vht_mcs_map[1] = 0xff; + + if(pregistrypriv->vht_rate_sel == 1) + { + pvhtpriv->vht_mcs_map[0] = 0xfc; // support 1SS MCS 0~7 + } + else if(pregistrypriv->vht_rate_sel == 2) + { + pvhtpriv->vht_mcs_map[0] = 0xfd; // Support 1SS MCS 0~8 + } + else if(pregistrypriv->vht_rate_sel == 3) + { + pvhtpriv->vht_mcs_map[0] = 0xfe; // Support 1SS MCS 0~9 + } + else if(pregistrypriv->vht_rate_sel == 4) + { + pvhtpriv->vht_mcs_map[0] = 0xf0; // support 1SS MCS 0~7 2SS MCS 0~7 + } + else if(pregistrypriv->vht_rate_sel == 5) + { + pvhtpriv->vht_mcs_map[0] = 0xf5; // support 1SS MCS 0~8 2SS MCS 0~8 + } + else if(pregistrypriv->vht_rate_sel == 6) + { + pvhtpriv->vht_mcs_map[0] = 0xfa; // support 1SS MCS 0~9 2SS MCS 0~9 + } + else if(pregistrypriv->vht_rate_sel == 7) + { + pvhtpriv->vht_mcs_map[0] = 0xf8; // support 1SS MCS 0-7 2SS MCS 0~9 + } + else if(pregistrypriv->vht_rate_sel == 8) + { + pvhtpriv->vht_mcs_map[0] = 0xf9; // support 1SS MCS 0-8 2SS MCS 0~9 + } + else if(pregistrypriv->vht_rate_sel == 9) + { + pvhtpriv->vht_mcs_map[0] = 0xf4; // support 1SS MCS 0-7 2SS MCS 0~8 + } + + pvhtpriv->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv->vht_mcs_map); +} + +u64 rtw_vht_rate_to_bitmap(u8 *pVHTRate) +{ + + u8 i,j , tmpRate; + u64 RateBitmap = 0; + u8 Bits_3ss = 6; + + for(i = j= 0; i < Bits_3ss; i+=2, j+=10) + { + /* every two bits means single sptial stream */ + tmpRate = (pVHTRate[0] >> i) & 3; + + switch(tmpRate){ + case 2: + RateBitmap = RateBitmap | (0x03ff << j); + break; + case 1: + RateBitmap = RateBitmap | (0x01ff << j); + break; + + case 0: + RateBitmap = RateBitmap | (0x00ff << j); + break; + + default: + break; + } + } + DBG_871X("RateBitmap=%016llx , pVHTRate[0]=%02x, pVHTRate[1]=%02x\n", RateBitmap, pVHTRate[0], pVHTRate[1]); + return RateBitmap; +} + +void update_sta_vht_info_apmode(_adapter *padapter, PVOID sta) +{ + struct sta_info *psta = (struct sta_info *)sta; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct vht_priv *pvhtpriv_ap = &pmlmepriv->vhtpriv; + struct vht_priv *pvhtpriv_sta = &psta->vhtpriv; + struct ht_priv *phtpriv_sta = &psta->htpriv; + u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, bw_mode = 0; + u16 cur_beamform_cap = 0; + u8 *pcap_mcs; + + if (pvhtpriv_sta->vht_option == _FALSE) { + return; + } + + bw_mode = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&pvhtpriv_sta->vht_op_mode_notify); + + //if (bw_mode > psta->bw_mode) + psta->bw_mode = bw_mode; + + // B4 Rx LDPC + if (TEST_FLAG(pvhtpriv_ap->ldpc_cap, LDPC_VHT_ENABLE_TX) && + GET_VHT_CAPABILITY_ELE_RX_LDPC(pvhtpriv_sta->vht_cap)) + { + SET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX)); + DBG_871X("Current STA(%d) VHT LDPC = %02X\n", psta->aid, cur_ldpc_cap); + } + pvhtpriv_sta->ldpc_cap = cur_ldpc_cap; + + if (psta->bw_mode > pmlmeext->cur_bwmode) + psta->bw_mode = pmlmeext->cur_bwmode; + + if (psta->bw_mode == CHANNEL_WIDTH_80) { + // B5 Short GI for 80 MHz + pvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE; + //DBG_871X("Current STA ShortGI80MHz = %d\n", pvhtpriv_sta->sgi_80m); + } else if (psta->bw_mode >= CHANNEL_WIDTH_160) { + // B5 Short GI for 80 MHz + pvhtpriv_sta->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI160M(pvhtpriv_sta->vht_cap) & pvhtpriv_ap->sgi_80m) ? _TRUE : _FALSE; + //DBG_871X("Current STA ShortGI160MHz = %d\n", pvhtpriv_sta->sgi_80m); + } + + // B8 B9 B10 Rx STBC + if (TEST_FLAG(pvhtpriv_ap->stbc_cap, STBC_VHT_ENABLE_TX) && + GET_VHT_CAPABILITY_ELE_RX_STBC(pvhtpriv_sta->vht_cap)) + { + SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX)); + DBG_871X("Current STA(%d) VHT STBC = %02X\n", psta->aid, cur_stbc_cap); + } + pvhtpriv_sta->stbc_cap = cur_stbc_cap; + +#ifdef CONFIG_BEAMFORMING + // B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee + if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) && + GET_VHT_CAPABILITY_ELE_SU_BFEE(pvhtpriv_sta->vht_cap)) + { + SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE); + /*Shift to BEAMFORMING_VHT_BEAMFORMER_STS_CAP*/ + SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pvhtpriv_sta->vht_cap)<<8); + } + + // B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer + if (TEST_FLAG(pvhtpriv_ap->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) && + GET_VHT_CAPABILITY_ELE_SU_BFER(pvhtpriv_sta->vht_cap)) + { + SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE); + /*Shit to BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM*/ + SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pvhtpriv_sta->vht_cap)<<12); + } + pvhtpriv_sta->beamform_cap = cur_beamform_cap; + if (cur_beamform_cap) { + DBG_871X("Current STA(%d) VHT Beamforming Setting = %02X\n", psta->aid, cur_beamform_cap); + } + #endif + + // B23 B24 B25 Maximum A-MPDU Length Exponent + pvhtpriv_sta->ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pvhtpriv_sta->vht_cap); + + pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pvhtpriv_sta->vht_cap); + _rtw_memcpy(pvhtpriv_sta->vht_mcs_map, pcap_mcs, 2); + + pvhtpriv_sta->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv_sta->vht_mcs_map); + +} + +void update_hw_vht_param(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 ht_AMPDU_len; + + ht_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03; + + if(pvhtpriv->ampdu_len > ht_AMPDU_len) + rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&pvhtpriv->ampdu_len)); +} + +void VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 cur_ldpc_cap = 0, cur_stbc_cap = 0, rf_type = RF_1T1R; + u16 cur_beamform_cap = 0; + u8 *pcap_mcs; + u8 vht_mcs[2]; + + if(pIE==NULL) return; + + if(pvhtpriv->vht_option == _FALSE) return; + + pmlmeinfo->VHT_enable = 1; + + // B4 Rx LDPC + if (TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_TX) && + GET_VHT_CAPABILITY_ELE_RX_LDPC(pIE->data)) + { + SET_FLAG(cur_ldpc_cap, (LDPC_VHT_ENABLE_TX | LDPC_VHT_CAP_TX)); + DBG_871X("Current VHT LDPC Setting = %02X\n", cur_ldpc_cap); + } + pvhtpriv->ldpc_cap = cur_ldpc_cap; + + // B5 Short GI for 80 MHz + pvhtpriv->sgi_80m = (GET_VHT_CAPABILITY_ELE_SHORT_GI80M(pIE->data) & pvhtpriv->sgi_80m) ? _TRUE : _FALSE; + //DBG_871X("Current ShortGI80MHz = %d\n", pvhtpriv->sgi_80m); + + // B8 B9 B10 Rx STBC + if (TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX) && + GET_VHT_CAPABILITY_ELE_RX_STBC(pIE->data)) + { + SET_FLAG(cur_stbc_cap, (STBC_VHT_ENABLE_TX | STBC_VHT_CAP_TX)); + DBG_871X("Current VHT STBC Setting = %02X\n", cur_stbc_cap); + } + pvhtpriv->stbc_cap = cur_stbc_cap; +#ifdef CONFIG_BEAMFORMING + // B11 SU Beamformer Capable, the target supports Beamformer and we are Beamformee + if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE) && + GET_VHT_CAPABILITY_ELE_SU_BFEE(pIE->data)) + { + SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE); + /*Shift to BEAMFORMING_VHT_BEAMFORMER_STS_CAP*/ + SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(pIE->data)<<8); + } + + // B12 SU Beamformee Capable, the target supports Beamformee and we are Beamformer + if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) && + GET_VHT_CAPABILITY_ELE_SU_BFER(pIE->data)) + { + SET_FLAG(cur_beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE); + /*Shit to BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM*/ + SET_FLAG(cur_beamform_cap, GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(pIE->data)<<12); + + } + pvhtpriv->beamform_cap = cur_beamform_cap; + if (cur_beamform_cap) { + DBG_871X("Current VHT Beamforming Setting = %02X\n", cur_beamform_cap); + } + #endif + // B23 B24 B25 Maximum A-MPDU Length Exponent + pvhtpriv->ampdu_len = GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pIE->data); + + pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pIE->data); + _rtw_memcpy(vht_mcs, pcap_mcs, 2); + + rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + if ((rf_type == RF_1T1R) || (rf_type == RF_1T2R)) + vht_mcs[0] |= 0xfc; + else if (rf_type == RF_2T2R) + vht_mcs[0] |= 0xf0; + else if (rf_type == RF_3T3R) + vht_mcs[0] |= 0xc0; + + _rtw_memcpy(pvhtpriv->vht_mcs_map, vht_mcs, 2); + + pvhtpriv->vht_highest_rate = rtw_get_vht_highest_rate(pvhtpriv->vht_mcs_map); +} + +void VHT_operation_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + + if(pIE==NULL) return; + + if(pvhtpriv->vht_option == _FALSE) return; +} + +void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, PVOID sta) +{ + struct sta_info *psta = (struct sta_info *)sta; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct registry_priv *regsty = adapter_to_regsty(padapter); + u8 target_bw; + u8 target_rxss, current_rxss; + u8 update_ra = _FALSE; + u8 vht_mcs_map[2] = {}; + + if(pvhtpriv->vht_option == _FALSE) + return; + + target_bw = GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(pframe); + target_rxss = (GET_VHT_OPERATING_MODE_FIELD_RX_NSS(pframe)+1); + + if (target_bw != psta->bw_mode) { + if (hal_is_bw_support(padapter, target_bw) + && REGSTY_IS_BW_5G_SUPPORT(regsty, target_bw) + ) { + update_ra = _TRUE; + psta->bw_mode = target_bw; + } + } + + current_rxss = rtw_vht_mcsmap_to_nss(psta->vhtpriv.vht_mcs_map); + if (target_rxss != current_rxss) { + update_ra = _TRUE; + + rtw_vht_nss_to_mcsmap(target_rxss, vht_mcs_map, psta->vhtpriv.vht_mcs_map); + _rtw_memcpy(psta->vhtpriv.vht_mcs_map, vht_mcs_map, 2); + + rtw_hal_update_sta_rate_mask(padapter, psta); + } + + if (update_ra) { + rtw_dm_ra_mask_wk_cmd(padapter, (u8 *)psta); + } +} + +u32 rtw_build_vht_operation_ie(_adapter *padapter, u8 *pbuf, u8 channel) +{ + struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + //struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + u8 ChnlWidth, center_freq, bw_mode, rf_type = 0; + u32 len = 0; + u8 operation[5]; + + rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + + _rtw_memset(operation, 0, 5); + + bw_mode = REGSTY_BW_5G(pregistrypriv); /* TODO: control op bw with other info */ + + if (hal_chk_bw_cap(padapter, BW_CAP_80M | BW_CAP_160M) + && REGSTY_BW_5G(pregistrypriv) >= CHANNEL_WIDTH_80 + ) { + center_freq = rtw_get_center_ch(channel, bw_mode, HAL_PRIME_CHNL_OFFSET_LOWER); + ChnlWidth = 1; + } else { + center_freq = 0; + ChnlWidth = 0; + } + + + SET_VHT_OPERATION_ELE_CHL_WIDTH(operation, ChnlWidth); + //center frequency + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(operation, center_freq);//Todo: need to set correct center channel + SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(operation,0); + + if (padapter->registrypriv.rf_config != RF_MAX_TYPE) + rf_type = padapter->registrypriv.rf_config; + + switch (rf_type) { + case RF_1T1R: + operation[3] = 0xfe; + operation[4] = 0xff; + break; + case RF_1T2R: + case RF_2T2R: + case RF_2T2R_GREEN: + operation[3] = 0xfa; + operation[4] = 0xff; + break; + case RF_2T3R: + case RF_2T4R: + case RF_3T3R: + case RF_3T4R: + operation[3] = 0xea; + operation[4] = 0xff; + break; + case RF_4T4R: + operation[3] = 0xaa; + operation[4] = 0xff; + break; + default: + DBG_871X("%s, %d, unknown rf type\n", __func__, __LINE__); + } + + rtw_set_ie(pbuf, EID_VHTOperation, 5, operation, &len); + + return len; +} + +u32 rtw_build_vht_op_mode_notify_ie(_adapter *padapter, u8 *pbuf, u8 bw) +{ + //struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + u32 len = 0; + u8 opmode = 0, rf_type = 0; + u8 chnl_width, rx_nss; + + chnl_width = bw; + + rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + if(rf_type == RF_3T3R) + rx_nss = 3; + else if(rf_type == RF_2T2R) + rx_nss = 2; + else + rx_nss = 1; + + SET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(&opmode, chnl_width); + SET_VHT_OPERATING_MODE_FIELD_RX_NSS(&opmode, (rx_nss-1)); + SET_VHT_OPERATING_MODE_FIELD_RX_NSS_TYPE(&opmode, 0); //Todo + + pvhtpriv->vht_op_mode_notify = opmode; + + pbuf = rtw_set_ie(pbuf, EID_OpModeNotification, 1, &opmode, &len); + + return len; +} + +u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf) +{ + u8 bw, rf_type, rf_num, rx_stbc_nss = 0; + u16 HighestRate; + u8 *pcap, *pcap_mcs; + u32 len = 0; + u32 rx_packet_offset, max_recvbuf_sz; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + + pcap = pvhtpriv->vht_cap; + _rtw_memset(pcap, 0, 32); + + /* B0 B1 Maximum MPDU Length */ + rtw_hal_get_def_var(padapter, HAL_DEF_RX_PACKET_OFFSET, &rx_packet_offset); + rtw_hal_get_def_var(padapter, HAL_DEF_MAX_RECVBUF_SZ, &max_recvbuf_sz); + + RTW_DBG("%s, line%d, Available RX buf size = %d bytes\n.", __FUNCTION__, __LINE__, max_recvbuf_sz - rx_packet_offset); + + if ((max_recvbuf_sz - rx_packet_offset) >= 11454) { + SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 2); + RTW_INFO("%s, line%d, Set MAX MPDU len = 11454 bytes\n.", __FUNCTION__, __LINE__); + } else if ((max_recvbuf_sz - rx_packet_offset) >= 7991) { + SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 1); + RTW_INFO("%s, line%d, Set MAX MPDU len = 7991 bytes\n.", __FUNCTION__, __LINE__); + } else if ((max_recvbuf_sz - rx_packet_offset) >= 3895) { + SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(pcap, 0); + RTW_INFO("%s, line%d, Set MAX MPDU len = 3895 bytes\n.", __FUNCTION__, __LINE__); + } else + RTW_ERR("%s, line%d, Error!! Available RX buf size < 3895 bytes\n.", __FUNCTION__, __LINE__); + + /* B2 B3 Supported Channel Width Set */ + if (hal_chk_bw_cap(padapter, BW_CAP_160M) && REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_160)) { + if (hal_chk_bw_cap(padapter, BW_CAP_80_80M) && REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_80_80)) + SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 2); + else + SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 1); + } else { + SET_VHT_CAPABILITY_ELE_CHL_WIDTH(pcap, 0); + } + + // B4 Rx LDPC + if(TEST_FLAG(pvhtpriv->ldpc_cap, LDPC_VHT_ENABLE_RX)) + { + SET_VHT_CAPABILITY_ELE_RX_LDPC(pcap, 1); + } + + // B5 ShortGI for 80MHz + SET_VHT_CAPABILITY_ELE_SHORT_GI80M(pcap, pvhtpriv->sgi_80m? 1 : 0); // We can receive Short GI of 80M + + // B6 ShortGI for 160MHz + //SET_VHT_CAPABILITY_ELE_SHORT_GI160M(pcap, pvhtpriv->sgi_80m? 1 : 0); + + // B7 Tx STBC + if(TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_TX)) + { + SET_VHT_CAPABILITY_ELE_TX_STBC(pcap, 1); + } + + // B8 B9 B10 Rx STBC + if(TEST_FLAG(pvhtpriv->stbc_cap, STBC_VHT_ENABLE_RX)) + { + rtw_hal_get_def_var(padapter, HAL_DEF_RX_STBC, (u8 *)(&rx_stbc_nss)); + + SET_VHT_CAPABILITY_ELE_RX_STBC(pcap, rx_stbc_nss); + } + + // B11 SU Beamformer Capable + if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) { + SET_VHT_CAPABILITY_ELE_SU_BFER(pcap, 1); + // B16 17 18 Number of Sounding Dimensions + rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMER_CAP, (u8 *)&rf_num); + SET_VHT_CAPABILITY_ELE_SOUNDING_DIMENSIONS(pcap, rf_num); + } + + // B12 SU Beamformee Capable + if (TEST_FLAG(pvhtpriv->beamform_cap, BEAMFORMING_VHT_BEAMFORMEE_ENABLE)) { + SET_VHT_CAPABILITY_ELE_SU_BFEE(pcap, 1); + // B13 14 15 Compressed Steering Number of Beamformer Antennas Supported + rtw_hal_get_def_var(padapter, HAL_DEF_BEAMFORMEE_CAP, (u8 *)&rf_num); + SET_VHT_CAPABILITY_ELE_BFER_ANT_SUPP(pcap, rf_num); + } + + // B19 MU Beamformer Capable + SET_VHT_CAPABILITY_ELE_MU_BFER(pcap, 0); //HW don't support mu bfee/bfer + // B20 MU Beamformee Capable + SET_VHT_CAPABILITY_ELE_MU_BFEE(pcap, 0); + // B21 VHT TXOP PS + SET_VHT_CAPABILITY_ELE_TXOP_PS(pcap, 0); + // B22 +HTC-VHT Capable + SET_VHT_CAPABILITY_ELE_HTC_VHT(pcap, 1); + // B23 24 25 Maximum A-MPDU Length Exponent + if (pregistrypriv->ampdu_factor != 0xFE) + { + SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pcap, pregistrypriv->ampdu_factor); + } + else + { + SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(pcap, 7); + } + // B26 27 VHT Link Adaptation Capable + SET_VHT_CAPABILITY_ELE_LINK_ADAPTION(pcap, 0); + + pcap_mcs = GET_VHT_CAPABILITY_ELE_RX_MCS(pcap); + _rtw_memcpy(pcap_mcs, pvhtpriv->vht_mcs_map, 2); + + pcap_mcs = GET_VHT_CAPABILITY_ELE_TX_MCS(pcap); + _rtw_memcpy(pcap_mcs, pvhtpriv->vht_mcs_map, 2); + + /* find the largest bw supported by both registry and hal */ + bw = hal_largest_bw(padapter, REGSTY_BW_5G(pregistrypriv)); + + HighestRate = VHT_MCS_DATA_RATE[bw][pvhtpriv->sgi_80m][((pvhtpriv->vht_highest_rate - MGN_VHT1SS_MCS0)&0x3f)]; + HighestRate = (HighestRate+1) >> 1; + + SET_VHT_CAPABILITY_ELE_MCS_RX_HIGHEST_RATE(pcap, HighestRate); //indicate we support highest rx rate is 600Mbps. + SET_VHT_CAPABILITY_ELE_MCS_TX_HIGHEST_RATE(pcap, HighestRate); //indicate we support highest tx rate is 600Mbps. + + pbuf = rtw_set_ie(pbuf, EID_VHTCapability, 12, pcap, &len); + + return len; +} + +u32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len) +{ + u32 ielen=0, out_len=0; + u8 cap_len=0, notify_len=0, notify_bw=0, operation_bw=0, supported_chnl_width=0; + u8 *p, *pframe; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + + rtw_vht_use_default_setting(padapter); + + p = rtw_get_ie(in_ie+12, EID_VHTCapability, &ielen, in_len-12); + if (p && ielen>0) { + supported_chnl_width = GET_VHT_CAPABILITY_ELE_CHL_WIDTH(p+2); + + // VHT Capabilities element + cap_len = rtw_build_vht_cap_ie(padapter, out_ie+*pout_len); + *pout_len += cap_len; + + // Get HT BW + p = rtw_get_ie(in_ie+12, _HT_EXTRA_INFO_IE_, &ielen, in_len-12); + if (p && ielen>0) { + struct HT_info_element *pht_info = (struct HT_info_element *)(p+2); + if (pht_info->infos[0] & BIT(2)) + operation_bw = CHANNEL_WIDTH_40; + else + operation_bw = CHANNEL_WIDTH_20; + } + + // VHT Operation element + p = rtw_get_ie(in_ie+12, EID_VHTOperation, &ielen, in_len-12); + if (p && ielen>0) { + out_len = *pout_len; + if (GET_VHT_OPERATION_ELE_CHL_WIDTH(p+2) >= 1) { + if (supported_chnl_width == 2) + operation_bw = CHANNEL_WIDTH_80_80; + else if (supported_chnl_width == 1) + operation_bw = CHANNEL_WIDTH_160; + else + operation_bw = CHANNEL_WIDTH_80; + } + pframe = rtw_set_ie(out_ie+out_len, EID_VHTOperation, ielen, p+2 , pout_len); + } + + /* find the largest bw supported by both registry and hal */ + notify_bw = hal_largest_bw(padapter, REGSTY_BW_5G(pregistrypriv)); + + if (notify_bw > operation_bw) + notify_bw = operation_bw; + + // Operating Mode Notification element + notify_len = rtw_build_vht_op_mode_notify_ie(padapter, out_ie+*pout_len, notify_bw); + *pout_len += notify_len; + + pvhtpriv->vht_option = _TRUE; + } + + return (pvhtpriv->vht_option); + +} + +void VHTOnAssocRsp(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct vht_priv *pvhtpriv = &pmlmepriv->vhtpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 ht_AMPDU_len; + + DBG_871X("%s\n", __FUNCTION__); + + if (!pmlmeinfo->HT_enable) + return; + + if (!pmlmeinfo->VHT_enable) + return; + + ht_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03; + + if(pvhtpriv->ampdu_len > ht_AMPDU_len) + rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&pvhtpriv->ampdu_len)); + + rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MAX_TIME, (u8 *)(&pvhtpriv->vht_highest_rate)); +} + +#endif //CONFIG_80211AC_VHT + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_wapi.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_wapi.c new file mode 100644 index 000000000..b74115790 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_wapi.c @@ -0,0 +1,1327 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifdef CONFIG_WAPI_SUPPORT + +#include +#include +#include +#include + + +u32 wapi_debug_component = +// WAPI_INIT | +// WAPI_API | +// WAPI_TX | +// WAPI_RX | + WAPI_ERR ; //always open err flags on + +void WapiFreeAllStaInfo(_adapter *padapter) +{ + PRT_WAPI_T pWapiInfo; + PRT_WAPI_STA_INFO pWapiStaInfo; + PRT_WAPI_BKID pWapiBkid; + + WAPI_TRACE(WAPI_INIT, "===========> %s\n", __FUNCTION__); + pWapiInfo = &padapter->wapiInfo; + + //Pust to Idle List + rtw_wapi_return_all_sta_info(padapter); + + //Sta Info List + while(!list_empty(&(pWapiInfo->wapiSTAIdleList))) + { + pWapiStaInfo = (PRT_WAPI_STA_INFO)list_entry(pWapiInfo->wapiSTAIdleList.next, RT_WAPI_STA_INFO, list); + list_del_init(&pWapiStaInfo->list); + } + + //BKID List + while(!list_empty(&(pWapiInfo->wapiBKIDIdleList))) + { + pWapiBkid = (PRT_WAPI_BKID)list_entry(pWapiInfo->wapiBKIDIdleList.next, RT_WAPI_BKID, list); + list_del_init(&pWapiBkid->list); + } + WAPI_TRACE(WAPI_INIT, "<=========== %s\n", __FUNCTION__); + return; +} + +void WapiSetIE(_adapter *padapter) +{ + PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo); + //PRT_WAPI_BKID pWapiBkid; + u16 protocolVer = 1; + u16 akmCnt = 1; + u16 suiteCnt = 1; + u16 capability = 0; + u8 OUI[3]; + + OUI[0] = 0x00; + OUI[1] = 0x14; + OUI[2] = 0x72; + + pWapiInfo->wapiIELength = 0; +//protocol version + memcpy(pWapiInfo->wapiIE+pWapiInfo->wapiIELength, &protocolVer, 2); + pWapiInfo->wapiIELength +=2; +//akm + memcpy(pWapiInfo->wapiIE+pWapiInfo->wapiIELength, &akmCnt, 2); + pWapiInfo->wapiIELength +=2; + + if(pWapiInfo->bWapiPSK){ + memcpy(pWapiInfo->wapiIE+pWapiInfo->wapiIELength,OUI, 3); + pWapiInfo->wapiIELength +=3; + pWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x2; + pWapiInfo->wapiIELength +=1; + }else{ + memcpy(pWapiInfo->wapiIE+pWapiInfo->wapiIELength,OUI, 3); + pWapiInfo->wapiIELength +=3; + pWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x1; + pWapiInfo->wapiIELength +=1; + } + +//usk + memcpy(pWapiInfo->wapiIE+pWapiInfo->wapiIELength, &suiteCnt, 2); + pWapiInfo->wapiIELength +=2; + memcpy(pWapiInfo->wapiIE+pWapiInfo->wapiIELength,OUI, 3); + pWapiInfo->wapiIELength +=3; + pWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x1; + pWapiInfo->wapiIELength +=1; + +//msk + memcpy(pWapiInfo->wapiIE+pWapiInfo->wapiIELength,OUI, 3); + pWapiInfo->wapiIELength +=3; + pWapiInfo->wapiIE[pWapiInfo->wapiIELength] = 0x1; + pWapiInfo->wapiIELength +=1; + +//Capbility + memcpy(pWapiInfo->wapiIE+pWapiInfo->wapiIELength, &capability, 2); + pWapiInfo->wapiIELength +=2; +} + + +/* PN1 > PN2, return 1, + * else return 0. + */ +u32 WapiComparePN(u8 *PN1, u8 *PN2) +{ + char i; + + if ((NULL == PN1) || (NULL == PN2)) + return 1; + + // overflow case + if ((PN2[15] - PN1[15]) & 0x80) + return 1; + + for (i=16; i>0; i--) + { + if(PN1[i-1] == PN2[i-1]) + continue; + else if(PN1[i-1] > PN2[i-1]) + return 1; + else + return 0; + } + + return 0; +} + +u8 +WapiGetEntryForCamWrite(_adapter *padapter,u8 *pMacAddr,u8 KID,BOOLEAN IsMsk) +{ + PRT_WAPI_T pWapiInfo=NULL; + //PRT_WAPI_CAM_ENTRY pEntry=NULL; + u8 i=0; + u8 ret = 0xff; + + WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__); + + pWapiInfo = &padapter->wapiInfo; + + //exist? + for(i=0;iwapiCamEntry[i].IsUsed + && (_rtw_memcmp(pMacAddr, pWapiInfo->wapiCamEntry[i].PeerMacAddr, ETH_ALEN) == _TRUE) + && pWapiInfo->wapiCamEntry[i].keyidx == KID + && pWapiInfo->wapiCamEntry[i].type == IsMsk) + { + ret = pWapiInfo->wapiCamEntry[i].entry_idx; //cover it + break; + } + } + + if(i == WAPI_CAM_ENTRY_NUM) //not found + { + for(i=0;iwapiCamEntry[i].IsUsed == 0) + { + pWapiInfo->wapiCamEntry[i].IsUsed = 1; + pWapiInfo->wapiCamEntry[i].type = IsMsk; + pWapiInfo->wapiCamEntry[i].keyidx = KID; + _rtw_memcpy(pWapiInfo->wapiCamEntry[i].PeerMacAddr, pMacAddr,ETH_ALEN); + ret = pWapiInfo->wapiCamEntry[i].entry_idx; + break; + } + } + } + + WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__); + return ret; + +/* + if(RTIsListEmpty(&pWapiInfo->wapiCamIdleList)){ + RT_TRACE(COMP_SEC,DBG_LOUD,("No Entry for wapi!!!\n")); + return 0; + } + + pEntry = (PRT_WAPI_CAM_ENTRY)RTRemoveHeadList(&pWapiInfo->wapiCamIdleList); + RTInsertTailList(&pWapiInfo->wapiCamUsedList, &pEntry->list); + + RT_TRACE(COMP_SEC,DBG_LOUD,("<====WapiGetCamEntry(),Get Entry Idx:%d.but we just return 4 for test\n",pEntry->entry_idx)); + + return pEntry->entry_idx;*/ +} + +u8 WapiGetEntryForCamClear(_adapter *padapter,u8 *pPeerMac,u8 keyid,u8 IsMsk) +{ + PRT_WAPI_T pWapiInfo=NULL; + u8 i=0; + + WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__); + + pWapiInfo = &padapter->wapiInfo; + + for(i=0;iwapiCamEntry[i].IsUsed + && (_rtw_memcmp(pPeerMac, pWapiInfo->wapiCamEntry[i].PeerMacAddr, ETH_ALEN) == _TRUE) + && pWapiInfo->wapiCamEntry[i].keyidx == keyid + && pWapiInfo->wapiCamEntry[i].type == IsMsk) + { + pWapiInfo->wapiCamEntry[i].IsUsed = 0; + pWapiInfo->wapiCamEntry[i].keyidx = 2; + _rtw_memset(pWapiInfo->wapiCamEntry[i].PeerMacAddr,0,ETH_ALEN); + + WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__); + return pWapiInfo->wapiCamEntry[i].entry_idx; + } + } + + WAPI_TRACE(WAPI_API,"<====WapiGetReturnCamEntry(), No this cam entry.\n"); + return 0xff; +/* + if(RTIsListEmpty(&pWapiInfo->wapiCamUsedList)){ + RT_TRACE(COMP_SEC,DBG_LOUD,("No Entry for wapi!!!\n")); + return FALSE; + } + + pList = &pWapiInfo->wapiCamUsedList; + while(pList->Flink != &pWapiInfo->wapiCamUsedList) + { + pEntry = (PRT_WAPI_CAM_ENTRY)pList->Flink; + if(PlatformCompareMemory(pPeerMac,pEntry->PeerMacAddr, ETHER_ADDRLEN)== 0 + && keyid == pEntry->keyidx) + { + RTRemoveEntryList(pList); + RTInsertHeadList(&pWapiInfo->wapiCamIdleList, pList); + return pEntry->entry_idx; + } + pList = pList->Flink; + } + + return 0; +*/ +} + +void +WapiResetAllCamEntry(_adapter *padapter) +{ + PRT_WAPI_T pWapiInfo; + int i; + + WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__); + + pWapiInfo = &padapter->wapiInfo; + + for (i=0;iwapiCamEntry[i].PeerMacAddr, 0, ETH_ALEN); + pWapiInfo->wapiCamEntry[i].IsUsed = 0; + pWapiInfo->wapiCamEntry[i].keyidx = 2; //invalid + pWapiInfo->wapiCamEntry[i].entry_idx = 4+i*2; + } + + WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__); + + return; +} + +u8 WapiWriteOneCamEntry( + _adapter *padapter, + u8 *pMacAddr, + u8 KeyId, + u8 EntryId, + u8 EncAlg, + u8 bGroupKey, + u8 *pKey +) +{ + u8 retVal = 0; + u16 usConfig = 0; + + WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__); + + if(EntryId >= 32) + { + WAPI_TRACE(WAPI_ERR, "<=== CamAddOneEntry(): ulKeyId exceed!\n"); + return retVal; + } + + usConfig=usConfig|(0x01<<15)|((u16)(EncAlg)<<2)|(KeyId); + + if(EncAlg == _SMS4_ ) + { + if(bGroupKey == 1) + usConfig |= (0x01<<6); + if((EntryId % 2)==1) // ==0 sec key; == 1mic key + usConfig |= (0x01<<5); + } + + write_cam(padapter, EntryId, usConfig, pMacAddr, pKey); + + WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__); + return 1; +} + +void rtw_wapi_init(_adapter *padapter) +{ + PRT_WAPI_T pWapiInfo; + int i; + + WAPI_TRACE(WAPI_INIT, "===========> %s\n", __FUNCTION__); + RT_ASSERT_RET(padapter); + + if (!padapter->WapiSupport) + { + WAPI_TRACE(WAPI_INIT, "<========== %s, WAPI not supported!\n", __FUNCTION__); + return; + } + + pWapiInfo = &padapter->wapiInfo; + pWapiInfo->bWapiEnable = false; + + //Init BKID List + INIT_LIST_HEAD(&pWapiInfo->wapiBKIDIdleList); + INIT_LIST_HEAD(&pWapiInfo->wapiBKIDStoreList); + for(i=0;iwapiBKID[i].list, &pWapiInfo->wapiBKIDIdleList); + } + + //Init STA List + INIT_LIST_HEAD(&pWapiInfo->wapiSTAIdleList); + INIT_LIST_HEAD(&pWapiInfo->wapiSTAUsedList); + for(i=0;iwapiSta[i].list, &pWapiInfo->wapiSTAIdleList); + } + + for (i=0;iwapiCamEntry[i].IsUsed = 0; + pWapiInfo->wapiCamEntry[i].keyidx = 2; //invalid + pWapiInfo->wapiCamEntry[i].entry_idx = 4+i*2; + } + + WAPI_TRACE(WAPI_INIT, "<========== %s\n", __FUNCTION__); +} + +void rtw_wapi_free(_adapter *padapter) +{ + WAPI_TRACE(WAPI_INIT, "===========> %s\n", __FUNCTION__); + RT_ASSERT_RET(padapter); + + if (!padapter->WapiSupport) + { + WAPI_TRACE(WAPI_INIT, "<========== %s, WAPI not supported!\n", __FUNCTION__); + return; + } + + WapiFreeAllStaInfo(padapter); + + WAPI_TRACE(WAPI_INIT, "<========== %s\n", __FUNCTION__); +} + +void rtw_wapi_disable_tx(_adapter *padapter) +{ + WAPI_TRACE(WAPI_INIT, "===========> %s\n", __FUNCTION__); + RT_ASSERT_RET(padapter); + + if (!padapter->WapiSupport) + { + WAPI_TRACE(WAPI_INIT, "<========== %s, WAPI not supported!\n", __FUNCTION__); + return; + } + + padapter->wapiInfo.wapiTxMsk.bTxEnable = false; + padapter->wapiInfo.wapiTxMsk.bSet = false; + + WAPI_TRACE(WAPI_INIT, "<========== %s\n", __FUNCTION__); +} + +u8 rtw_wapi_is_wai_packet(_adapter* padapter,u8 *pkt_data) +{ + PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + PRT_WAPI_STA_INFO pWapiSta = NULL; + u8 WaiPkt = 0, *pTaddr, bFind = false; + u8 Offset_TypeWAI = 0 ; // (mac header len + llc length) + + WAPI_TRACE(WAPI_TX|WAPI_RX, "===========> %s\n", __FUNCTION__); + + if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) + { + WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__); + return 0; + } + + Offset_TypeWAI = 24 + 6 ; + + //YJ,add,091103. Data frame may also have skb->data[30]=0x88 and skb->data[31]=0xb4. + if ((pkt_data[1]&0x40) !=0) + { + //DBG_871X("data is privacy \n"); + return 0; + } + + pTaddr = GetAddr2Ptr(pkt_data); + if(list_empty(&pWapiInfo->wapiSTAUsedList)){ + bFind = false; + }else{ + list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list){ + if (_rtw_memcmp(pTaddr, pWapiSta->PeerMacAddr, 6) == _TRUE) { + bFind = true; + break; + } + } + } + + WAPI_TRACE(WAPI_TX|WAPI_RX, "%s: bFind=%d pTaddr="MAC_FMT"\n", __FUNCTION__, bFind, MAC_ARG(pTaddr)); + + if (pkt_data[0] == WIFI_QOS_DATA_TYPE) + { + Offset_TypeWAI += 2; + } + + // 88b4? + if( (pkt_data[Offset_TypeWAI]==0x88) && (pkt_data[Offset_TypeWAI+1]==0xb4) ){ + WaiPkt = pkt_data[Offset_TypeWAI+5]; + + psecuritypriv->hw_decrypted = _TRUE; + }else{ + WAPI_TRACE(WAPI_TX|WAPI_RX, "%s(): non wai packet\n",__FUNCTION__); + } + + WAPI_TRACE(WAPI_TX|WAPI_RX, "%s(): Recvd WAI frame. IsWAIPkt(%d)\n",__FUNCTION__, WaiPkt); + + return WaiPkt; +} + + +void rtw_wapi_update_info(_adapter *padapter, union recv_frame *precv_frame) +{ + PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo); + struct recv_frame_hdr *precv_hdr; + u8 *ptr; + u8 *pTA; + u8 *pRecvPN; + + + WAPI_TRACE(WAPI_RX, "===========> %s\n", __FUNCTION__); + + if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) + { + WAPI_TRACE(WAPI_RX, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__); + return; + } + + precv_hdr = &precv_frame->u.hdr; + ptr = precv_hdr->rx_data; + + if (precv_hdr->attrib.qos == 1) + { + precv_hdr->UserPriority = GetTid(ptr); + } + else + { + precv_hdr->UserPriority = 0; + } + + pTA = GetAddr2Ptr(ptr); + _rtw_memcpy((u8 *)precv_hdr->WapiSrcAddr, pTA, 6); + pRecvPN = ptr + precv_hdr->attrib.hdrlen + 2; + _rtw_memcpy((u8 *)precv_hdr->WapiTempPN, pRecvPN, 16); + + WAPI_TRACE(WAPI_RX, "<========== %s\n", __FUNCTION__); +} + +/**************************************************************************** +TRUE-----------------Drop +FALSE---------------- handle +add to support WAPI to N-mode +*****************************************************************************/ +u8 rtw_wapi_check_for_drop( + _adapter *padapter, + union recv_frame *precv_frame +) +{ + PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo); + u8 *pLastRecvPN = NULL; + u8 bFind = false; + PRT_WAPI_STA_INFO pWapiSta = NULL; + u8 bDrop = false; + struct recv_frame_hdr *precv_hdr = &precv_frame->u.hdr; + u8 WapiAEPNInitialValueSrc[16] = {0x37,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; + u8 WapiAEMultiCastPNInitialValueSrc[16] = {0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; + u8 *ptr = precv_frame->u.hdr.rx_data; + int i; + + WAPI_TRACE(WAPI_RX, "===========> %s\n", __FUNCTION__); + + if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) + { + WAPI_TRACE(WAPI_RX, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__); + return false; + } + + if(precv_hdr->bIsWaiPacket !=0) + { + if(precv_hdr->bIsWaiPacket== 0x8) + { + + DBG_871X("rtw_wapi_check_for_drop: dump packet \n"); + for(i=0;i<50;i++) + { + DBG_871X("%02X ",ptr[i]); + if((i+1) %8 ==0) + DBG_871X("\n"); + } + DBG_871X("\n rtw_wapi_check_for_drop: dump packet \n"); + + for(i=0;i<16;i++) + { + if(ptr[i+27] !=0) + break; + } + + if(i== 16) + { + WAPI_TRACE(WAPI_RX,"rtw_wapi_check_for_drop: drop with zero BKID \n"); + return true; + } + else + { + return false; + } + } + else + return false; + } + + if(list_empty(&pWapiInfo->wapiSTAUsedList)){ + bFind = false; + }else{ + list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { + if (_rtw_memcmp(precv_hdr->WapiSrcAddr, pWapiSta->PeerMacAddr, ETH_ALEN) == _TRUE) { + bFind = true; + break; + } + } + } + WAPI_TRACE(WAPI_RX, "%s: bFind=%d prxb->WapiSrcAddr="MAC_FMT"\n", __FUNCTION__, bFind, MAC_ARG(precv_hdr->WapiSrcAddr)); + + if(bFind) + { + if(IS_MCAST(precv_hdr->attrib.ra)) + { + WAPI_TRACE(WAPI_RX,"rtw_wapi_check_for_drop: multicast case \n"); + pLastRecvPN = pWapiSta->lastRxMulticastPN; + } + else + { + WAPI_TRACE(WAPI_RX,"rtw_wapi_check_for_drop: unicast case \n"); + switch(precv_hdr->UserPriority) + { + case 0: + case 3: + pLastRecvPN = pWapiSta->lastRxUnicastPNBEQueue; + break; + case 1: + case 2: + pLastRecvPN = pWapiSta->lastRxUnicastPNBKQueue; + break; + case 4: + case 5: + pLastRecvPN = pWapiSta->lastRxUnicastPNVIQueue; + break; + case 6: + case 7: + pLastRecvPN = pWapiSta->lastRxUnicastPNVOQueue; + break; + default: + WAPI_TRACE(WAPI_ERR,"%s: Unknown TID \n",__FUNCTION__); + break; + } + } + + if(!WapiComparePN(precv_hdr->WapiTempPN,pLastRecvPN)) + { + WAPI_TRACE(WAPI_RX,"%s: Equal PN!!\n",__FUNCTION__); + if(IS_MCAST(precv_hdr->attrib.ra)) + _rtw_memcpy(pLastRecvPN,WapiAEMultiCastPNInitialValueSrc,16); + else + _rtw_memcpy(pLastRecvPN,WapiAEPNInitialValueSrc,16); + bDrop = true; + } + else + { + _rtw_memcpy(pLastRecvPN,precv_hdr->WapiTempPN,16); + } + } + + WAPI_TRACE(WAPI_RX, "<========== %s\n", __FUNCTION__); + return bDrop; +} + +void rtw_build_probe_resp_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib) +{ + PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo); + u8 WapiIELength = 0; + + WAPI_TRACE(WAPI_MLME, "===========> %s\n", __FUNCTION__); + + if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) + { + WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported!\n", __FUNCTION__); + return; + } + + WapiSetIE(padapter); + WapiIELength = pWapiInfo->wapiIELength; + pframe[0] = _WAPI_IE_; + pframe[1] = WapiIELength; + _rtw_memcpy(pframe+2, pWapiInfo->wapiIE, WapiIELength); + pframe += WapiIELength+2; + pattrib->pktlen += WapiIELength+2; + + WAPI_TRACE(WAPI_MLME, "<========== %s\n", __FUNCTION__); +} + +void rtw_build_beacon_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib) +{ + PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo); + u8 WapiIELength = 0; + WAPI_TRACE(WAPI_MLME, "===========> %s\n", __FUNCTION__); + + if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) + { + WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported!\n", __FUNCTION__); + return; + } + + WapiSetIE(padapter); + WapiIELength = pWapiInfo->wapiIELength; + pframe[0] = _WAPI_IE_; + pframe[1] = WapiIELength; + _rtw_memcpy(pframe+2, pWapiInfo->wapiIE, WapiIELength); + pframe += WapiIELength+2; + pattrib->pktlen += WapiIELength+2; + + WAPI_TRACE(WAPI_MLME, "<========== %s\n", __FUNCTION__); +} + +void rtw_build_assoc_req_wapi_ie(_adapter *padapter, unsigned char *pframe, struct pkt_attrib *pattrib) +{ + PRT_WAPI_BKID pWapiBKID; + u16 bkidNum; + PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo); + u8 WapiIELength = 0; + + WAPI_TRACE(WAPI_MLME, "===========> %s\n", __FUNCTION__); + + if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) + { + WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported!\n", __FUNCTION__); + return; + } + + WapiSetIE(padapter); + WapiIELength = pWapiInfo->wapiIELength; + bkidNum = 0; + if(!list_empty(&(pWapiInfo->wapiBKIDStoreList))){ + list_for_each_entry(pWapiBKID, &pWapiInfo->wapiBKIDStoreList, list) { + bkidNum ++; + _rtw_memcpy(pWapiInfo->wapiIE+WapiIELength+2, pWapiBKID->bkid,16); + WapiIELength += 16; + } + } + _rtw_memcpy(pWapiInfo->wapiIE+WapiIELength, &bkidNum, 2); + WapiIELength += 2; + + pframe[0] = _WAPI_IE_; + pframe[1] = WapiIELength; + _rtw_memcpy(pframe+2, pWapiInfo->wapiIE, WapiIELength); + pframe += WapiIELength+2; + pattrib->pktlen += WapiIELength+2; + WAPI_TRACE(WAPI_MLME, "<========== %s\n", __FUNCTION__); +} + +void rtw_wapi_on_assoc_ok(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) +{ + PRT_WAPI_T pWapiInfo = &(padapter->wapiInfo); + PRT_WAPI_STA_INFO pWapiSta; + u8 WapiAEPNInitialValueSrc[16] = {0x37,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; + //u8 WapiASUEPNInitialValueSrc[16] = {0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; + u8 WapiAEMultiCastPNInitialValueSrc[16] = {0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; + + WAPI_TRACE(WAPI_MLME, "===========> %s\n", __FUNCTION__); + + if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) + { + WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__); + return; + } + + pWapiSta =(PRT_WAPI_STA_INFO)list_entry(pWapiInfo->wapiSTAIdleList.next, RT_WAPI_STA_INFO, list); + list_del_init(&pWapiSta->list); + list_add_tail(&pWapiSta->list, &pWapiInfo->wapiSTAUsedList); + _rtw_memcpy(pWapiSta->PeerMacAddr,padapter->mlmeextpriv.mlmext_info.network.MacAddress,6); + _rtw_memcpy(pWapiSta->lastRxMulticastPN, WapiAEMultiCastPNInitialValueSrc, 16); + _rtw_memcpy(pWapiSta->lastRxUnicastPN, WapiAEPNInitialValueSrc, 16); + + //For chenk PN error with Qos Data after s3: add by ylb 20111114 + _rtw_memcpy(pWapiSta->lastRxUnicastPNBEQueue,WapiAEPNInitialValueSrc,16); + _rtw_memcpy(pWapiSta->lastRxUnicastPNBKQueue,WapiAEPNInitialValueSrc,16); + _rtw_memcpy(pWapiSta->lastRxUnicastPNVIQueue,WapiAEPNInitialValueSrc,16); + _rtw_memcpy(pWapiSta->lastRxUnicastPNVOQueue,WapiAEPNInitialValueSrc,16); + + WAPI_TRACE(WAPI_MLME, "<========== %s\n", __FUNCTION__); +} + + +void rtw_wapi_return_one_sta_info(_adapter *padapter, u8 *MacAddr) +{ + PRT_WAPI_T pWapiInfo; + PRT_WAPI_STA_INFO pWapiStaInfo = NULL; + PRT_WAPI_BKID pWapiBkid = NULL; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + pWapiInfo = &padapter->wapiInfo; + + WAPI_TRACE(WAPI_API, "==========> %s\n", __FUNCTION__); + + if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) + { + WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__); + return; + } + + if(check_fwstate(pmlmepriv, WIFI_STATION_STATE)) + { + while(!list_empty(&(pWapiInfo->wapiBKIDStoreList))) + { + pWapiBkid = (PRT_WAPI_BKID)list_entry(pWapiInfo->wapiBKIDStoreList.next, RT_WAPI_BKID, list); + list_del_init(&pWapiBkid->list); + _rtw_memset(pWapiBkid->bkid,0,16); + list_add_tail(&pWapiBkid->list, &pWapiInfo->wapiBKIDIdleList); + } + } + + + WAPI_TRACE(WAPI_API, " %s: after clear bkid \n", __FUNCTION__); + + + //Remove STA info + if(list_empty(&(pWapiInfo->wapiSTAUsedList))){ + WAPI_TRACE(WAPI_API, " %s: wapiSTAUsedList is null \n", __FUNCTION__); + return; + }else{ + + WAPI_TRACE(WAPI_API, " %s: wapiSTAUsedList is not null \n", __FUNCTION__); +#if 0 + pWapiStaInfo=(PRT_WAPI_STA_INFO)list_entry((pWapiInfo->wapiSTAUsedList.next),RT_WAPI_STA_INFO,list); + + list_for_each_entry(pWapiStaInfo, &(pWapiInfo->wapiSTAUsedList), list) { + + DBG_871X("MAC Addr %02x-%02x-%02x-%02x-%02x-%02x \n",MacAddr[0],MacAddr[1],MacAddr[2],MacAddr[3],MacAddr[4],MacAddr[5]); + + + DBG_871X("peer Addr %02x-%02x-%02x-%02x-%02x-%02x \n",pWapiStaInfo->PeerMacAddr[0],pWapiStaInfo->PeerMacAddr[1],pWapiStaInfo->PeerMacAddr[2],pWapiStaInfo->PeerMacAddr[3],pWapiStaInfo->PeerMacAddr[4],pWapiStaInfo->PeerMacAddr[5]); + + if(pWapiStaInfo == NULL) + { + WAPI_TRACE(WAPI_API, " %s: pWapiStaInfo == NULL Case \n", __FUNCTION__); + return; + } + + if(pWapiStaInfo->PeerMacAddr == NULL) + { + WAPI_TRACE(WAPI_API, " %s: pWapiStaInfo->PeerMacAddr == NULL Case \n", __FUNCTION__); + return; + } + + if(MacAddr == NULL) + { + WAPI_TRACE(WAPI_API, " %s: MacAddr == NULL Case \n", __FUNCTION__); + return; + } + + if (_rtw_memcmp(pWapiStaInfo->PeerMacAddr, MacAddr, ETH_ALEN) == _TRUE) { + pWapiStaInfo->bAuthenticateInProgress = false; + pWapiStaInfo->bSetkeyOk = false; + _rtw_memset(pWapiStaInfo->PeerMacAddr,0,ETH_ALEN); + list_del_init(&pWapiStaInfo->list); + list_add_tail(&pWapiStaInfo->list, &pWapiInfo->wapiSTAIdleList); + break; + } + + } +#endif + + while(!list_empty(&(pWapiInfo->wapiSTAUsedList))) + { + pWapiStaInfo = (PRT_WAPI_STA_INFO)list_entry(pWapiInfo->wapiSTAUsedList.next, RT_WAPI_STA_INFO, list); + + DBG_871X("peer Addr %02x-%02x-%02x-%02x-%02x-%02x \n",pWapiStaInfo->PeerMacAddr[0],pWapiStaInfo->PeerMacAddr[1],pWapiStaInfo->PeerMacAddr[2],pWapiStaInfo->PeerMacAddr[3],pWapiStaInfo->PeerMacAddr[4],pWapiStaInfo->PeerMacAddr[5]); + + list_del_init(&pWapiStaInfo->list); + memset(pWapiStaInfo->PeerMacAddr,0,ETH_ALEN); + pWapiStaInfo->bSetkeyOk = 0; + list_add_tail(&pWapiStaInfo->list, &pWapiInfo->wapiSTAIdleList); + } + + } + + WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__); + return; +} + +void rtw_wapi_return_all_sta_info(_adapter *padapter) +{ + PRT_WAPI_T pWapiInfo; + PRT_WAPI_STA_INFO pWapiStaInfo; + PRT_WAPI_BKID pWapiBkid; + WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__); + + pWapiInfo = &padapter->wapiInfo; + + if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) + { + WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__); + return; + } + + //Sta Info List + while(!list_empty(&(pWapiInfo->wapiSTAUsedList))) + { + pWapiStaInfo = (PRT_WAPI_STA_INFO)list_entry(pWapiInfo->wapiSTAUsedList.next, RT_WAPI_STA_INFO, list); + list_del_init(&pWapiStaInfo->list); + memset(pWapiStaInfo->PeerMacAddr,0,ETH_ALEN); + pWapiStaInfo->bSetkeyOk = 0; + list_add_tail(&pWapiStaInfo->list, &pWapiInfo->wapiSTAIdleList); + } + + //BKID List + while(!list_empty(&(pWapiInfo->wapiBKIDStoreList))) + { + pWapiBkid = (PRT_WAPI_BKID)list_entry(pWapiInfo->wapiBKIDStoreList.next, RT_WAPI_BKID, list); + list_del_init(&pWapiBkid->list); + memset(pWapiBkid->bkid,0,16); + list_add_tail(&pWapiBkid->list, &pWapiInfo->wapiBKIDIdleList); + } + WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__); +} + +void rtw_wapi_clear_cam_entry(_adapter *padapter, u8 *pMacAddr) +{ + u8 UcIndex = 0; + + WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__); + + if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) + { + WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__); + return; + } + + UcIndex = WapiGetEntryForCamClear(padapter, pMacAddr, 0, 0); + if(UcIndex != 0xff){ + //CAM_mark_invalid(Adapter, UcIndex); + CAM_empty_entry(padapter, UcIndex); + } + + UcIndex = WapiGetEntryForCamClear(padapter, pMacAddr, 1, 0); + if(UcIndex != 0xff){ + //CAM_mark_invalid(Adapter, UcIndex); + CAM_empty_entry(padapter, UcIndex); + } + + UcIndex = WapiGetEntryForCamClear(padapter, pMacAddr, 0, 1); + if(UcIndex != 0xff){ + //CAM_mark_invalid(Adapter, UcIndex); + CAM_empty_entry(padapter, UcIndex); + } + + UcIndex = WapiGetEntryForCamClear(padapter, pMacAddr, 1, 1); + if(UcIndex != 0xff){ + //CAM_mark_invalid(padapter, UcIndex); + CAM_empty_entry(padapter, UcIndex); + } + + WAPI_TRACE(WAPI_API, "<========== %s\n", __FUNCTION__); +} + +void rtw_wapi_clear_all_cam_entry(_adapter *padapter) +{ + WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__); + + if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) + { + WAPI_TRACE(WAPI_MLME, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__); + return; + } + + invalidate_cam_all(padapter); // is this ok? + WapiResetAllCamEntry(padapter); + + WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__); +} + +void rtw_wapi_set_key(_adapter *padapter, RT_WAPI_KEY *pWapiKey, RT_WAPI_STA_INFO *pWapiSta, u8 bGroupKey, u8 bUseDefaultKey) +{ + PRT_WAPI_T pWapiInfo = &padapter->wapiInfo; + u8 *pMacAddr = pWapiSta->PeerMacAddr; + u32 EntryId = 0; + BOOLEAN IsPairWise = false ; + u8 EncAlgo; + + WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__); + + if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) + { + WAPI_TRACE(WAPI_API, "<========== %s, WAPI not supported or not enabled!\n", __FUNCTION__); + return; + } + + EncAlgo = _SMS4_; + + //For Tx bc/mc pkt,use defualt key entry + if(bUseDefaultKey) + { + // when WAPI update key, keyid will be 0 or 1 by turns. + if (pWapiKey->keyId == 0) + EntryId = 0; + else + EntryId = 2; + } + else + { + // tx/rx unicast pkt, or rx broadcast, find the key entry by peer's MacAddr + EntryId = WapiGetEntryForCamWrite(padapter,pMacAddr,pWapiKey->keyId,bGroupKey); + } + + if(EntryId == 0xff){ + WAPI_TRACE(WAPI_API, "===>No entry for WAPI setkey! !!\n"); + return; + } + + //EntryId is also used to diff Sec key and Mic key + //Sec Key + WapiWriteOneCamEntry(padapter, + pMacAddr, + pWapiKey->keyId, //keyid + EntryId, //entry + EncAlgo, //type + bGroupKey, //pairwise or group key + pWapiKey->dataKey); + //MIC key + WapiWriteOneCamEntry(padapter, + pMacAddr, + pWapiKey->keyId, //keyid + EntryId+1, //entry + EncAlgo, //type + bGroupKey, //pairwise or group key + pWapiKey->micKey); + + WAPI_TRACE(WAPI_API, "Set Wapi Key :KeyId:%d,EntryId:%d,PairwiseKey:%d.\n",pWapiKey->keyId,EntryId,!bGroupKey); + WAPI_TRACE(WAPI_API, "===========> %s\n", __FUNCTION__); + +} + +#if 0 +//YJ,test,091013 +void wapi_test_set_key(struct _adapter *padapter, u8* buf) +{ /*Data: keyType(1) + bTxEnable(1) + bAuthenticator(1) + bUpdate(1) + PeerAddr(6) + DataKey(16) + MicKey(16) + KeyId(1)*/ + PRT_WAPI_T pWapiInfo = &padapter->wapiInfo; + PRT_WAPI_BKID pWapiBkid; + PRT_WAPI_STA_INFO pWapiSta; + u8 data[43]; + bool bTxEnable; + bool bUpdate; + bool bAuthenticator; + u8 PeerAddr[6]; + u8 WapiAEPNInitialValueSrc[16] = {0x37,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; + u8 WapiASUEPNInitialValueSrc[16] = {0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; + u8 WapiAEMultiCastPNInitialValueSrc[16] = {0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; + + WAPI_TRACE(WAPI_INIT, "===========>%s\n", __FUNCTION__); + + if (!padapter->WapiSupport){ + return; + } + + copy_from_user(data, buf, 43); + bTxEnable = data[1]; + bAuthenticator = data[2]; + bUpdate = data[3]; + memcpy(PeerAddr,data+4,6); + + if(data[0] == 0x3){ + if(!list_empty(&(pWapiInfo->wapiBKIDIdleList))){ + pWapiBkid = (PRT_WAPI_BKID)list_entry(pWapiInfo->wapiBKIDIdleList.next, RT_WAPI_BKID, list); + list_del_init(&pWapiBkid->list); + memcpy(pWapiBkid->bkid, data+10, 16); + WAPI_DATA(WAPI_INIT, "SetKey - BKID", pWapiBkid->bkid, 16); + list_add_tail(&pWapiBkid->list, &pWapiInfo->wapiBKIDStoreList); + } + }else{ + list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { + if(!memcmp(pWapiSta->PeerMacAddr,PeerAddr,6)){ + pWapiSta->bAuthenticatorInUpdata = false; + switch(data[0]){ + case 1: //usk + if(bAuthenticator){ //authenticator + memcpy(pWapiSta->lastTxUnicastPN,WapiAEPNInitialValueSrc,16); + if(!bUpdate) { //first + WAPI_TRACE(WAPI_INIT,"AE fisrt set usk \n"); + pWapiSta->wapiUsk.bSet = true; + memcpy(pWapiSta->wapiUsk.dataKey,data+10,16); + memcpy(pWapiSta->wapiUsk.micKey,data+26,16); + pWapiSta->wapiUsk.keyId = *(data+42); + pWapiSta->wapiUsk.bTxEnable = true; + WAPI_DATA(WAPI_INIT, "SetKey - AE USK Data Key", pWapiSta->wapiUsk.dataKey, 16); + WAPI_DATA(WAPI_INIT, "SetKey - AE USK Mic Key", pWapiSta->wapiUsk.micKey, 16); + } + else //update + { + WAPI_TRACE(WAPI_INIT, "AE update usk \n"); + pWapiSta->wapiUskUpdate.bSet = true; + pWapiSta->bAuthenticatorInUpdata = true; + memcpy(pWapiSta->wapiUskUpdate.dataKey,data+10,16); + memcpy(pWapiSta->wapiUskUpdate.micKey,data+26,16); + memcpy(pWapiSta->lastRxUnicastPNBEQueue,WapiASUEPNInitialValueSrc,16); + memcpy(pWapiSta->lastRxUnicastPNBKQueue,WapiASUEPNInitialValueSrc,16); + memcpy(pWapiSta->lastRxUnicastPNVIQueue,WapiASUEPNInitialValueSrc,16); + memcpy(pWapiSta->lastRxUnicastPNVOQueue,WapiASUEPNInitialValueSrc,16); + memcpy(pWapiSta->lastRxUnicastPN,WapiASUEPNInitialValueSrc,16); + pWapiSta->wapiUskUpdate.keyId = *(data+42); + pWapiSta->wapiUskUpdate.bTxEnable = true; + } + } + else{ + if(!bUpdate){ + WAPI_TRACE(WAPI_INIT,"ASUE fisrt set usk \n"); + if(bTxEnable){ + pWapiSta->wapiUsk.bTxEnable = true; + memcpy(pWapiSta->lastTxUnicastPN,WapiASUEPNInitialValueSrc,16); + }else{ + pWapiSta->wapiUsk.bSet = true; + memcpy(pWapiSta->wapiUsk.dataKey,data+10,16); + memcpy(pWapiSta->wapiUsk.micKey,data+26,16); + pWapiSta->wapiUsk.keyId = *(data+42); + pWapiSta->wapiUsk.bTxEnable = false; + } + }else{ + WAPI_TRACE(WAPI_INIT,"ASUE update usk \n"); + if(bTxEnable){ + pWapiSta->wapiUskUpdate.bTxEnable = true; + if(pWapiSta->wapiUskUpdate.bSet){ + memcpy(pWapiSta->wapiUsk.dataKey,pWapiSta->wapiUskUpdate.dataKey,16); + memcpy(pWapiSta->wapiUsk.micKey,pWapiSta->wapiUskUpdate.micKey,16); + pWapiSta->wapiUsk.keyId=pWapiSta->wapiUskUpdate.keyId; + memcpy(pWapiSta->lastRxUnicastPNBEQueue,WapiASUEPNInitialValueSrc,16); + memcpy(pWapiSta->lastRxUnicastPNBKQueue,WapiASUEPNInitialValueSrc,16); + memcpy(pWapiSta->lastRxUnicastPNVIQueue,WapiASUEPNInitialValueSrc,16); + memcpy(pWapiSta->lastRxUnicastPNVOQueue,WapiASUEPNInitialValueSrc,16); + memcpy(pWapiSta->lastRxUnicastPN,WapiASUEPNInitialValueSrc,16); + pWapiSta->wapiUskUpdate.bTxEnable = false; + pWapiSta->wapiUskUpdate.bSet = false; + } + memcpy(pWapiSta->lastTxUnicastPN,WapiASUEPNInitialValueSrc,16); + }else{ + pWapiSta->wapiUskUpdate.bSet = true; + memcpy(pWapiSta->wapiUskUpdate.dataKey,data+10,16); + memcpy(pWapiSta->wapiUskUpdate.micKey,data+26,16); + pWapiSta->wapiUskUpdate.keyId = *(data+42); + pWapiSta->wapiUskUpdate.bTxEnable = false; + } + } + } + break; + case 2: //msk + if(bAuthenticator){ //authenticator + pWapiInfo->wapiTxMsk.bSet = true; + memcpy(pWapiInfo->wapiTxMsk.dataKey,data+10,16); + memcpy(pWapiInfo->wapiTxMsk.micKey,data+26,16); + pWapiInfo->wapiTxMsk.keyId = *(data+42); + pWapiInfo->wapiTxMsk.bTxEnable = true; + memcpy(pWapiInfo->lastTxMulticastPN,WapiAEMultiCastPNInitialValueSrc,16); + + if(!bUpdate){ //first + WAPI_TRACE(WAPI_INIT, "AE fisrt set msk \n"); + if(!pWapiSta->bSetkeyOk) + pWapiSta->bSetkeyOk = true; + pWapiInfo->bFirstAuthentiateInProgress= false; + }else{ //update + WAPI_TRACE(WAPI_INIT,"AE update msk \n"); + } + + WAPI_DATA(WAPI_INIT, "SetKey - AE MSK Data Key", pWapiInfo->wapiTxMsk.dataKey, 16); + WAPI_DATA(WAPI_INIT, "SetKey - AE MSK Mic Key", pWapiInfo->wapiTxMsk.micKey, 16); + } + else{ + if(!bUpdate){ + WAPI_TRACE(WAPI_INIT,"ASUE fisrt set msk \n"); + pWapiSta->wapiMsk.bSet = true; + memcpy(pWapiSta->wapiMsk.dataKey,data+10,16); + memcpy(pWapiSta->wapiMsk.micKey,data+26,16); + pWapiSta->wapiMsk.keyId = *(data+42); + pWapiSta->wapiMsk.bTxEnable = false; + if(!pWapiSta->bSetkeyOk) + pWapiSta->bSetkeyOk = true; + pWapiInfo->bFirstAuthentiateInProgress= false; + WAPI_DATA(WAPI_INIT, "SetKey - ASUE MSK Data Key", pWapiSta->wapiMsk.dataKey, 16); + WAPI_DATA(WAPI_INIT, "SetKey - ASUE MSK Mic Key", pWapiSta->wapiMsk.micKey, 16); + }else{ + WAPI_TRACE(WAPI_INIT,"ASUE update msk \n"); + pWapiSta->wapiMskUpdate.bSet = true; + memcpy(pWapiSta->wapiMskUpdate.dataKey,data+10,16); + memcpy(pWapiSta->wapiMskUpdate.micKey,data+26,16); + pWapiSta->wapiMskUpdate.keyId = *(data+42); + pWapiSta->wapiMskUpdate.bTxEnable = false; + } + } + break; + default: + WAPI_TRACE(WAPI_ERR,"Unknown Flag \n"); + break; + } + } + } + } + WAPI_TRACE(WAPI_INIT, "<===========%s\n", __FUNCTION__); +} + + +void wapi_test_init(struct _adapter *padapter) +{ + u8 keybuf[100]; + u8 mac_addr[6]={0x00,0xe0,0x4c,0x72,0x04,0x70}; + u8 UskDataKey[16]={0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f}; + u8 UskMicKey[16]={0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f}; + u8 UskId = 0; + u8 MskDataKey[16]={0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f}; + u8 MskMicKey[16]={0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f}; + u8 MskId = 0; + + WAPI_TRACE(WAPI_INIT, "===========>%s\n", __FUNCTION__); + + //Enable Wapi + WAPI_TRACE(WAPI_INIT, "%s: Enable wapi!!!!\n", __FUNCTION__); + padapter->wapiInfo.bWapiEnable = true; + padapter->pairwise_key_type = KEY_TYPE_SMS4; + ieee->group_key_type = KEY_TYPE_SMS4; + padapter->wapiInfo.extra_prefix_len = WAPI_EXT_LEN; + padapter->wapiInfo.extra_postfix_len = SMS4_MIC_LEN; + + //set usk + WAPI_TRACE(WAPI_INIT, "%s: Set USK!!!!\n", __FUNCTION__); + memset(keybuf,0,100); + keybuf[0] = 1; //set usk + keybuf[1] = 1; //enable tx + keybuf[2] = 1; //AE + keybuf[3] = 0; //not update + + memcpy(keybuf+4,mac_addr,6); + memcpy(keybuf+10,UskDataKey,16); + memcpy(keybuf+26,UskMicKey,16); + keybuf[42]=UskId; + wapi_test_set_key(padapter, keybuf); + + memset(keybuf,0,100); + keybuf[0] = 1; //set usk + keybuf[1] = 1; //enable tx + keybuf[2] = 0; //AE + keybuf[3] = 0; //not update + + memcpy(keybuf+4,mac_addr,6); + memcpy(keybuf+10,UskDataKey,16); + memcpy(keybuf+26,UskMicKey,16); + keybuf[42]=UskId; + wapi_test_set_key(padapter, keybuf); + + //set msk + WAPI_TRACE(WAPI_INIT, "%s: Set MSK!!!!\n", __FUNCTION__); + memset(keybuf,0,100); + keybuf[0] = 2; //set msk + keybuf[1] = 1; //Enable TX + keybuf[2] = 1; //AE + keybuf[3] = 0; //not update + memcpy(keybuf+4,mac_addr,6); + memcpy(keybuf+10,MskDataKey,16); + memcpy(keybuf+26,MskMicKey,16); + keybuf[42] = MskId; + wapi_test_set_key(padapter, keybuf); + + memset(keybuf,0,100); + keybuf[0] = 2; //set msk + keybuf[1] = 1; //Enable TX + keybuf[2] = 0; //AE + keybuf[3] = 0; //not update + memcpy(keybuf+4,mac_addr,6); + memcpy(keybuf+10,MskDataKey,16); + memcpy(keybuf+26,MskMicKey,16); + keybuf[42] = MskId; + wapi_test_set_key(padapter, keybuf); + WAPI_TRACE(WAPI_INIT, "<===========%s\n", __FUNCTION__); +} +#endif + +void rtw_wapi_get_iv(_adapter *padapter,u8 *pRA, u8*IV) +{ + PWLAN_HEADER_WAPI_EXTENSION pWapiExt = NULL; + PRT_WAPI_T pWapiInfo = &padapter->wapiInfo; + bool bPNOverflow = false; + bool bFindMatchPeer = false; + PRT_WAPI_STA_INFO pWapiSta = NULL; + + pWapiExt = (PWLAN_HEADER_WAPI_EXTENSION)IV; + + WAPI_DATA(WAPI_RX,"wapi_get_iv: pra",pRA,6); + + if(IS_MCAST(pRA)){ + if(!pWapiInfo->wapiTxMsk.bTxEnable){ + WAPI_TRACE(WAPI_ERR,"%s: bTxEnable = 0!!\n",__FUNCTION__); + return; + } + + if(pWapiInfo->wapiTxMsk.keyId <= 1){ + pWapiExt->KeyIdx = pWapiInfo->wapiTxMsk.keyId; + pWapiExt->Reserved = 0; + bPNOverflow = WapiIncreasePN(pWapiInfo->lastTxMulticastPN, 1); + memcpy(pWapiExt->PN, pWapiInfo->lastTxMulticastPN, 16); + } + } + else + { + if(list_empty(&pWapiInfo->wapiSTAUsedList)){ + WAPI_TRACE(WAPI_RX,"rtw_wapi_get_iv: list is empty \n"); + _rtw_memset(IV,10,18); + return; + } + else{ + list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list){ + WAPI_DATA(WAPI_RX,"rtw_wapi_get_iv: peermacaddr ",pWapiSta->PeerMacAddr,6); + if (_rtw_memcmp((u8*)pWapiSta->PeerMacAddr, pRA, 6) == _TRUE) { + bFindMatchPeer = true; + break; + } + } + + WAPI_TRACE(WAPI_RX,"bFindMatchPeer: %d \n",bFindMatchPeer); + WAPI_DATA(WAPI_RX,"Addr",pRA,6); + + if (bFindMatchPeer){ + if((!pWapiSta->wapiUskUpdate.bTxEnable) && (!pWapiSta->wapiUsk.bTxEnable)) + return; + + if (pWapiSta->wapiUsk.keyId <= 1){ + if(pWapiSta->wapiUskUpdate.bTxEnable) + pWapiExt->KeyIdx = pWapiSta->wapiUskUpdate.keyId; + else + pWapiExt->KeyIdx = pWapiSta->wapiUsk.keyId; + + pWapiExt->Reserved = 0; + bPNOverflow = WapiIncreasePN(pWapiSta->lastTxUnicastPN, 2); + _rtw_memcpy(pWapiExt->PN, pWapiSta->lastTxUnicastPN, 16); + + } + } + } + + } + +} + +bool rtw_wapi_drop_for_key_absent(_adapter *padapter,u8 *pRA) +{ + PRT_WAPI_T pWapiInfo = &padapter->wapiInfo; + bool bFindMatchPeer = false; + bool bDrop = false; + PRT_WAPI_STA_INFO pWapiSta = NULL; + struct security_priv *psecuritypriv = &padapter->securitypriv; + + WAPI_DATA(WAPI_RX,"rtw_wapi_drop_for_key_absent: ra ",pRA,6); + + if(psecuritypriv->dot11PrivacyAlgrthm == _SMS4_) + { + if ((!padapter->WapiSupport) || (!pWapiInfo->bWapiEnable)) + return true; + + if(IS_MCAST(pRA)){ + if(!pWapiInfo->wapiTxMsk.bTxEnable){ + bDrop = true; + WAPI_TRACE(WAPI_RX,"rtw_wapi_drop_for_key_absent: multicast key is absent \n"); + return bDrop; + } + } + else{ + if(!list_empty(&pWapiInfo->wapiSTAUsedList)){ + list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list){ + WAPI_DATA(WAPI_RX,"rtw_wapi_drop_for_key_absent: pWapiSta->PeerMacAddr ",pWapiSta->PeerMacAddr,6); + if (_rtw_memcmp(pRA, pWapiSta->PeerMacAddr, 6) == _TRUE){ + bFindMatchPeer = true; + break; + } + } + if (bFindMatchPeer) { + if (!pWapiSta->wapiUsk.bTxEnable){ + bDrop = true; + WAPI_TRACE(WAPI_RX,"rtw_wapi_drop_for_key_absent: unicast key is absent \n"); + return bDrop; + } + } + else{ + bDrop = true; + WAPI_TRACE(WAPI_RX,"rtw_wapi_drop_for_key_absent: no peer find \n"); + return bDrop; + } + + } + else{ + bDrop = true; + WAPI_TRACE(WAPI_RX,"rtw_wapi_drop_for_key_absent: no sta exist \n"); + return bDrop; + } + } + } + else + { + return bDrop; + } + + return bDrop; +} + +#endif diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_wapi_sms4.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_wapi_sms4.c new file mode 100644 index 000000000..0119cc244 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_wapi_sms4.c @@ -0,0 +1,924 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifdef CONFIG_WAPI_SUPPORT + +#include +#include +#include +#include + + +#ifdef CONFIG_WAPI_SW_SMS4 + +#define WAPI_LITTLE_ENDIAN +//#define BIG_ENDIAN +#define ENCRYPT 0 +#define DECRYPT 1 + + +/********************************************************** + **********************************************************/ +const u8 Sbox[256] = { +0xd6,0x90,0xe9,0xfe,0xcc,0xe1,0x3d,0xb7,0x16,0xb6,0x14,0xc2,0x28,0xfb,0x2c,0x05, +0x2b,0x67,0x9a,0x76,0x2a,0xbe,0x04,0xc3,0xaa,0x44,0x13,0x26,0x49,0x86,0x06,0x99, +0x9c,0x42,0x50,0xf4,0x91,0xef,0x98,0x7a,0x33,0x54,0x0b,0x43,0xed,0xcf,0xac,0x62, +0xe4,0xb3,0x1c,0xa9,0xc9,0x08,0xe8,0x95,0x80,0xdf,0x94,0xfa,0x75,0x8f,0x3f,0xa6, +0x47,0x07,0xa7,0xfc,0xf3,0x73,0x17,0xba,0x83,0x59,0x3c,0x19,0xe6,0x85,0x4f,0xa8, +0x68,0x6b,0x81,0xb2,0x71,0x64,0xda,0x8b,0xf8,0xeb,0x0f,0x4b,0x70,0x56,0x9d,0x35, +0x1e,0x24,0x0e,0x5e,0x63,0x58,0xd1,0xa2,0x25,0x22,0x7c,0x3b,0x01,0x21,0x78,0x87, +0xd4,0x00,0x46,0x57,0x9f,0xd3,0x27,0x52,0x4c,0x36,0x02,0xe7,0xa0,0xc4,0xc8,0x9e, +0xea,0xbf,0x8a,0xd2,0x40,0xc7,0x38,0xb5,0xa3,0xf7,0xf2,0xce,0xf9,0x61,0x15,0xa1, +0xe0,0xae,0x5d,0xa4,0x9b,0x34,0x1a,0x55,0xad,0x93,0x32,0x30,0xf5,0x8c,0xb1,0xe3, +0x1d,0xf6,0xe2,0x2e,0x82,0x66,0xca,0x60,0xc0,0x29,0x23,0xab,0x0d,0x53,0x4e,0x6f, +0xd5,0xdb,0x37,0x45,0xde,0xfd,0x8e,0x2f,0x03,0xff,0x6a,0x72,0x6d,0x6c,0x5b,0x51, +0x8d,0x1b,0xaf,0x92,0xbb,0xdd,0xbc,0x7f,0x11,0xd9,0x5c,0x41,0x1f,0x10,0x5a,0xd8, +0x0a,0xc1,0x31,0x88,0xa5,0xcd,0x7b,0xbd,0x2d,0x74,0xd0,0x12,0xb8,0xe5,0xb4,0xb0, +0x89,0x69,0x97,0x4a,0x0c,0x96,0x77,0x7e,0x65,0xb9,0xf1,0x09,0xc5,0x6e,0xc6,0x84, +0x18,0xf0,0x7d,0xec,0x3a,0xdc,0x4d,0x20,0x79,0xee,0x5f,0x3e,0xd7,0xcb,0x39,0x48 +}; + +const u32 CK[32] = { + 0x00070e15, 0x1c232a31, 0x383f464d, 0x545b6269, + 0x70777e85, 0x8c939aa1, 0xa8afb6bd, 0xc4cbd2d9, + 0xe0e7eef5, 0xfc030a11, 0x181f262d, 0x343b4249, + 0x50575e65, 0x6c737a81, 0x888f969d, 0xa4abb2b9, + 0xc0c7ced5, 0xdce3eaf1, 0xf8ff060d, 0x141b2229, + 0x30373e45, 0x4c535a61, 0x686f767d, 0x848b9299, + 0xa0a7aeb5, 0xbcc3cad1, 0xd8dfe6ed, 0xf4fb0209, + 0x10171e25, 0x2c333a41, 0x484f565d, 0x646b7279 }; + +#define Rotl(_x, _y) (((_x) << (_y)) | ((_x) >> (32 - (_y)))) + +#define ByteSub(_A) (Sbox[(_A) >> 24 & 0xFF] << 24 | \ + Sbox[(_A) >> 16 & 0xFF] << 16 | \ + Sbox[(_A) >> 8 & 0xFF] << 8 | \ + Sbox[(_A) & 0xFF]) + +#define L1(_B) ((_B) ^ Rotl(_B, 2) ^ Rotl(_B, 10) ^ Rotl(_B, 18) ^ Rotl(_B, 24)) +#define L2(_B) ((_B) ^ Rotl(_B, 13) ^ Rotl(_B, 23)) + +static void +xor_block(void *dst, void *src1, void *src2) +/* 128-bit xor: *dst = *src1 xor *src2. Pointers must be 32-bit aligned */ +{ + ((u32 *)dst)[0] = ((u32 *)src1)[0] ^ ((u32 *)src2)[0]; + ((u32 *)dst)[1] = ((u32 *)src1)[1] ^ ((u32 *)src2)[1]; + ((u32 *)dst)[2] = ((u32 *)src1)[2] ^ ((u32 *)src2)[2]; + ((u32 *)dst)[3] = ((u32 *)src1)[3] ^ ((u32 *)src2)[3]; +} + + +void SMS4Crypt(u8 *Input, u8 *Output, u32 *rk) +{ + u32 r, mid, x0, x1, x2, x3, *p; + p = (u32 *)Input; + x0 = p[0]; + x1 = p[1]; + x2 = p[2]; + x3 = p[3]; +#ifdef WAPI_LITTLE_ENDIAN + x0 = Rotl(x0, 16); x0 = ((x0 & 0x00FF00FF) << 8) | ((x0 & 0xFF00FF00) >> 8); + x1 = Rotl(x1, 16); x1 = ((x1 & 0x00FF00FF) << 8) | ((x1 & 0xFF00FF00) >> 8); + x2 = Rotl(x2, 16); x2 = ((x2 & 0x00FF00FF) << 8) | ((x2 & 0xFF00FF00) >> 8); + x3 = Rotl(x3, 16); x3 = ((x3 & 0x00FF00FF) << 8) | ((x3 & 0xFF00FF00) >> 8); +#endif + for (r = 0; r < 32; r += 4) + { + mid = x1 ^ x2 ^ x3 ^ rk[r + 0]; + mid = ByteSub(mid); + x0 ^= L1(mid); + mid = x2 ^ x3 ^ x0 ^ rk[r + 1]; + mid = ByteSub(mid); + x1 ^= L1(mid); + mid = x3 ^ x0 ^ x1 ^ rk[r + 2]; + mid = ByteSub(mid); + x2 ^= L1(mid); + mid = x0 ^ x1 ^ x2 ^ rk[r + 3]; + mid = ByteSub(mid); + x3 ^= L1(mid); + } +#ifdef WAPI_LITTLE_ENDIAN + x0 = Rotl(x0, 16); x0 = ((x0 & 0x00FF00FF) << 8) | ((x0 & 0xFF00FF00) >> 8); + x1 = Rotl(x1, 16); x1 = ((x1 & 0x00FF00FF) << 8) | ((x1 & 0xFF00FF00) >> 8); + x2 = Rotl(x2, 16); x2 = ((x2 & 0x00FF00FF) << 8) | ((x2 & 0xFF00FF00) >> 8); + x3 = Rotl(x3, 16); x3 = ((x3 & 0x00FF00FF) << 8) | ((x3 & 0xFF00FF00) >> 8); +#endif + p = (u32 *)Output; + p[0] = x3; + p[1] = x2; + p[2] = x1; + p[3] = x0; +} + + + +void SMS4KeyExt(u8 *Key, u32 *rk, u32 CryptFlag) +{ + u32 r, mid, x0, x1, x2, x3, *p; + + p = (u32 *)Key; + x0 = p[0]; + x1 = p[1]; + x2 = p[2]; + x3 = p[3]; +#ifdef WAPI_LITTLE_ENDIAN + x0 = Rotl(x0, 16); x0 = ((x0 & 0xFF00FF) << 8) | ((x0 & 0xFF00FF00) >> 8); + x1 = Rotl(x1, 16); x1 = ((x1 & 0xFF00FF) << 8) | ((x1 & 0xFF00FF00) >> 8); + x2 = Rotl(x2, 16); x2 = ((x2 & 0xFF00FF) << 8) | ((x2 & 0xFF00FF00) >> 8); + x3 = Rotl(x3, 16); x3 = ((x3 & 0xFF00FF) << 8) | ((x3 & 0xFF00FF00) >> 8); +#endif + + x0 ^= 0xa3b1bac6; + x1 ^= 0x56aa3350; + x2 ^= 0x677d9197; + x3 ^= 0xb27022dc; + for (r = 0; r < 32; r += 4) + { + mid = x1 ^ x2 ^ x3 ^ CK[r + 0]; + mid = ByteSub(mid); + rk[r + 0] = x0 ^= L2(mid); + mid = x2 ^ x3 ^ x0 ^ CK[r + 1]; + mid = ByteSub(mid); + rk[r + 1] = x1 ^= L2(mid); + mid = x3 ^ x0 ^ x1 ^ CK[r + 2]; + mid = ByteSub(mid); + rk[r + 2] = x2 ^= L2(mid); + mid = x0 ^ x1 ^ x2 ^ CK[r + 3]; + mid = ByteSub(mid); + rk[r + 3] = x3 ^= L2(mid); + } + if (CryptFlag == DECRYPT) + { + for (r = 0; r < 16; r++) + mid = rk[r], rk[r] = rk[31 - r], rk[31 - r] = mid; + } +} + + +void WapiSMS4Cryption(u8 *Key, u8 *IV, u8 *Input, u16 InputLength, + u8 *Output, u16 *OutputLength, u32 CryptFlag) +{ + u32 blockNum,i,j, rk[32]; + u16 remainder; + u8 blockIn[16],blockOut[16], tempIV[16], k; + + *OutputLength = 0; + remainder = InputLength & 0x0F; + blockNum = InputLength >> 4; + if(remainder !=0) + blockNum++; + else + remainder = 16; + + for(k=0;k<16;k++) + tempIV[k] = IV[15-k]; + + memcpy(blockIn, tempIV, 16); + + SMS4KeyExt((u8 *)Key, rk,CryptFlag); + + for(i=0; i> 4; + + for(k=0;k<16;k++) + tempIV[k] = IV[15-k]; + + memcpy(BlockIn, tempIV, 16); + + SMS4KeyExt((u8 *)Key, rk, ENCRYPT); + + SMS4Crypt((u8 *)BlockIn, BlockOut, rk); + + for(i=0; i> 4; + + for(i=0; i%s\n", __FUNCTION__); + + header = (struct ieee80211_hdr_3addr_qos *)pHeader; + memset(TempBuf, 0, 34); + memcpy(TempBuf, pHeader, 2); //FrameCtrl + pTemp = (u16*)TempBuf; + *pTemp &= 0xc78f; //bit4,5,6,11,12,13 + + memcpy((TempBuf+2), (pHeader+4), 12); //Addr1, Addr2 + memcpy((TempBuf+14), (pHeader+22), 2); // SeqCtrl + pTemp = (u16*)(TempBuf + 14); + *pTemp &= 0x000f; + + memcpy((TempBuf+16), (pHeader+16), 6); //Addr3 + + fc = le16_to_cpu(header->frame_ctl); + + + + if (GetFrDs((u16*)&fc) && GetToDs((u16 *)&fc)) + { + memcpy((TempBuf+22), (pHeader+24), 6); + QosOffset = 30; + }else{ + memset((TempBuf+22), 0, 6); + QosOffset = 24; + } + + if((fc & 0x0088) == 0x0088){ + memcpy((TempBuf+28), (pHeader+QosOffset), 2); + TempLen += 2; + //IV = pHeader + QosOffset + 2 + SNAP_SIZE + sizeof(u16) + 2; + IV = pHeader + QosOffset + 2 + 2; + }else{ + IV = pHeader + QosOffset + 2; + //IV = pHeader + QosOffset + SNAP_SIZE + sizeof(u16) + 2; + } + + TempBuf[TempLen-1] = (u8)(DataLen & 0xff); + TempBuf[TempLen-2] = (u8)((DataLen & 0xff00)>>8); + TempBuf[TempLen-4] = KeyIdx; + + WAPI_DATA(WAPI_TX, "CalculateMic - KEY", MicKey, 16); + WAPI_DATA(WAPI_TX, "CalculateMic - IV", IV, 16); + WAPI_DATA(WAPI_TX, "CalculateMic - TempBuf", TempBuf, TempLen); + WAPI_DATA(WAPI_TX, "CalculateMic - pData", pData, DataLen); + + WapiSMS4CalculateMic(MicKey, IV, TempBuf, TempLen, + pData, DataLen, MicBuffer, &MicLen); + + if (MicLen != 16) + WAPI_TRACE(WAPI_ERR,"%s: MIC Length Error!!\n",__FUNCTION__); + + WAPI_TRACE(WAPI_TX|WAPI_RX, "<=========%s\n", __FUNCTION__); +#endif +} + +/* AddCount: 1 or 2. + * If overflow, return 1, + * else return 0. + */ +u8 WapiIncreasePN(u8 *PN, u8 AddCount) +{ + u8 i; + + if (NULL == PN) + return 1; + //YJ,test,091102 + /* + if(AddCount == 2){ + DBG_8192C("############################%s(): PN[0]=0x%x\n", __FUNCTION__, PN[0]); + if(PN[0] == 0x48){ + PN[0] += AddCount; + return 1; + }else{ + PN[0] += AddCount; + return 0; + } + } + */ + //YJ,test,091102,end + + for (i=0; i<16; i++) + { + if (PN[i] + AddCount <= 0xff) + { + PN[i] += AddCount; + return 0; + } + else + { + PN[i] += AddCount; + AddCount = 1; + } + } + return 1; +} + + +void WapiGetLastRxUnicastPNForQoSData( + u8 UserPriority, + PRT_WAPI_STA_INFO pWapiStaInfo, + u8 *PNOut +) +{ + WAPI_TRACE(WAPI_RX, "===========> %s\n", __FUNCTION__); + switch(UserPriority) + { + case 0: + case 3: + memcpy(PNOut,pWapiStaInfo->lastRxUnicastPNBEQueue,16); + break; + case 1: + case 2: + memcpy(PNOut,pWapiStaInfo->lastRxUnicastPNBKQueue,16); + break; + case 4: + case 5: + memcpy(PNOut,pWapiStaInfo->lastRxUnicastPNVIQueue,16); + break; + case 6: + case 7: + memcpy(PNOut,pWapiStaInfo->lastRxUnicastPNVOQueue,16); + break; + default: + WAPI_TRACE(WAPI_ERR, "%s: Unknown TID \n", __FUNCTION__); + break; + } + WAPI_TRACE(WAPI_RX, "<=========== %s\n", __FUNCTION__); +} + + +void WapiSetLastRxUnicastPNForQoSData( + u8 UserPriority, + u8 *PNIn, + PRT_WAPI_STA_INFO pWapiStaInfo +) +{ + WAPI_TRACE(WAPI_RX, "===========> %s\n", __FUNCTION__); + switch(UserPriority) + { + case 0: + case 3: + memcpy(pWapiStaInfo->lastRxUnicastPNBEQueue,PNIn,16); + break; + case 1: + case 2: + memcpy(pWapiStaInfo->lastRxUnicastPNBKQueue,PNIn,16); + break; + case 4: + case 5: + memcpy(pWapiStaInfo->lastRxUnicastPNVIQueue,PNIn,16); + break; + case 6: + case 7: + memcpy(pWapiStaInfo->lastRxUnicastPNVOQueue,PNIn,16); + break; + default: + WAPI_TRACE(WAPI_ERR, "%s: Unknown TID \n", __FUNCTION__); + break; + } + WAPI_TRACE(WAPI_RX, "<=========== %s\n", __FUNCTION__); +} + + +/**************************************************************************** + FALSE not RX-Reorder + TRUE do RX Reorder +add to support WAPI to N-mode +*****************************************************************************/ +u8 WapiCheckPnInSwDecrypt( + _adapter *padapter, + struct sk_buff *pskb +) +{ + u8 ret = false; + +#if 0 + struct ieee80211_hdr_3addr_qos *header; + u16 fc; + u8 *pDaddr, *pTaddr, *pRaddr; + + header = (struct ieee80211_hdr_3addr_qos *)pskb->data; + pTaddr = header->addr2; + pRaddr = header->addr1; + fc = le16_to_cpu(header->frame_ctl); + + if(GetToDs(&fc)) + pDaddr = header->addr3; + else + pDaddr = header->addr1; + + if ((_rtw_memcmp(pRaddr, padapter->pnetdev->dev_addr, ETH_ALEN) == 0) + && ! (pDaddr) + && (GetFrameType(&fc) == WIFI_QOS_DATA_TYPE)) + //&& ieee->pHTInfo->bCurrentHTSupport && + //ieee->pHTInfo->bCurRxReorderEnable) + ret = false; + else + ret = true; +#endif + WAPI_TRACE(WAPI_RX, "%s: return %d\n", __FUNCTION__, ret); + return ret; +} + +int SecSMS4HeaderFillIV(_adapter *padapter, u8 *pxmitframe) +{ + struct pkt_attrib *pattrib = &((struct xmit_frame*)pxmitframe)->attrib; + u8 * frame = ((struct xmit_frame *)pxmitframe)->buf_addr + TXDESC_OFFSET; + u8 *pSecHeader = NULL, *pos = NULL, *pRA = NULL; + u8 bPNOverflow = false, bFindMatchPeer = false, hdr_len = 0; + PWLAN_HEADER_WAPI_EXTENSION pWapiExt = NULL; + PRT_WAPI_T pWapiInfo = &padapter->wapiInfo; + PRT_WAPI_STA_INFO pWapiSta = NULL; + int ret = 0; + + WAPI_TRACE(WAPI_TX, "=========>%s\n", __FUNCTION__); + + return ret; +#if 0 + hdr_len = sMacHdrLng; + if (GetFrameType(pskb->data) == WIFI_QOS_DATA_TYPE) + { + hdr_len += 2; + } + //hdr_len += SNAP_SIZE + sizeof(u16); + + pos = skb_push(pskb, padapter->wapiInfo.extra_prefix_len); + memmove(pos, pos+padapter->wapiInfo.extra_prefix_len, hdr_len); + + pSecHeader = pskb->data + hdr_len; + pWapiExt = (PWLAN_HEADER_WAPI_EXTENSION)pSecHeader; + pRA = pskb->data + 4; + + WAPI_DATA(WAPI_TX, "FillIV - Before Fill IV", pskb->data, pskb->len); + + //Address 1 is always receiver's address + if( IS_MCAST(pRA) ){ + if(!pWapiInfo->wapiTxMsk.bTxEnable){ + WAPI_TRACE(WAPI_ERR,"%s: bTxEnable = 0!!\n",__FUNCTION__); + return -2; + } + if(pWapiInfo->wapiTxMsk.keyId <= 1){ + pWapiExt->KeyIdx = pWapiInfo->wapiTxMsk.keyId; + pWapiExt->Reserved = 0; + bPNOverflow = WapiIncreasePN(pWapiInfo->lastTxMulticastPN, 1); + memcpy(pWapiExt->PN, pWapiInfo->lastTxMulticastPN, 16); + if (bPNOverflow){ + // Update MSK Notification. + WAPI_TRACE(WAPI_ERR,"===============>%s():multicast PN overflow\n",__FUNCTION__); + rtw_wapi_app_event_handler(padapter,NULL,0,pRA, false, false, true, 0, false); + } + }else{ + WAPI_TRACE(WAPI_ERR,"%s: Invalid Wapi Multicast KeyIdx!!\n",__FUNCTION__); + ret = -3; + } + } + else{ + list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { + if(!memcmp(pWapiSta->PeerMacAddr,pRA,6)){ + bFindMatchPeer = true; + break; + } + } + if (bFindMatchPeer){ + if((!pWapiSta->wapiUskUpdate.bTxEnable) && (!pWapiSta->wapiUsk.bTxEnable)){ + WAPI_TRACE(WAPI_ERR,"%s: bTxEnable = 0!!\n",__FUNCTION__); + return -4; + } + if (pWapiSta->wapiUsk.keyId <= 1){ + if(pWapiSta->wapiUskUpdate.bTxEnable) + pWapiExt->KeyIdx = pWapiSta->wapiUskUpdate.keyId; + else + pWapiExt->KeyIdx = pWapiSta->wapiUsk.keyId; + + pWapiExt->Reserved = 0; + bPNOverflow = WapiIncreasePN(pWapiSta->lastTxUnicastPN, 2); + memcpy(pWapiExt->PN, pWapiSta->lastTxUnicastPN, 16); + if (bPNOverflow){ + // Update USK Notification. + WAPI_TRACE(WAPI_ERR,"===============>%s():unicast PN overflow\n",__FUNCTION__); + rtw_wapi_app_event_handler(padapter,NULL,0,pWapiSta->PeerMacAddr, false, true, false, 0, false); + } + }else{ + WAPI_TRACE(WAPI_ERR,"%s: Invalid Wapi Unicast KeyIdx!!\n",__FUNCTION__); + ret = -5; + } + } + else{ + WAPI_TRACE(WAPI_ERR,"%s: Can not find Peer Sta "MAC_FMT"!!\n",__FUNCTION__, MAC_ARG(pRA)); + ret = -6; + } + } + + WAPI_DATA(WAPI_TX, "FillIV - After Fill IV", pskb->data, pskb->len); + WAPI_TRACE(WAPI_TX, "<=========%s\n", __FUNCTION__); + return ret; +#endif +} + +// WAPI SW Enc: must have done Coalesce! +void SecSWSMS4Encryption( + _adapter *padapter, + u8 * pxmitframe + ) +{ + PRT_WAPI_T pWapiInfo = &padapter->wapiInfo; + PRT_WAPI_STA_INFO pWapiSta = NULL; + u8 *pframe = ((struct xmit_frame*)pxmitframe)->buf_addr + TXDESC_SIZE; + struct pkt_attrib *pattrib = &((struct xmit_frame*)pxmitframe)->attrib; + + u8 *SecPtr = NULL, *pRA, *pMicKey = NULL, *pDataKey = NULL, *pIV = NULL; + u8 IVOffset, DataOffset, bFindMatchPeer = false, KeyIdx = 0, MicBuffer[16]; + u16 OutputLength; + + WAPI_TRACE(WAPI_TX, "=========>%s\n", __FUNCTION__); + + WAPI_TRACE(WAPI_TX,"hdrlen: %d \n",pattrib->hdrlen); + + return; + + DataOffset = pattrib->hdrlen + pattrib->iv_len; + + pRA = pframe + 4; + + + if( IS_MCAST(pRA) ){ + KeyIdx = pWapiInfo->wapiTxMsk.keyId; + pIV = pWapiInfo->lastTxMulticastPN; + pMicKey = pWapiInfo->wapiTxMsk.micKey; + pDataKey = pWapiInfo->wapiTxMsk.dataKey; + }else{ + if (!list_empty(&(pWapiInfo->wapiSTAUsedList))){ + list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { + if (0 == memcmp(pWapiSta->PeerMacAddr, pRA, 6)){ + bFindMatchPeer = true; + break; + } + } + + if (bFindMatchPeer){ + if (pWapiSta->wapiUskUpdate.bTxEnable){ + KeyIdx = pWapiSta->wapiUskUpdate.keyId; + WAPI_TRACE(WAPI_TX, "%s(): Use update USK!! KeyIdx=%d\n", __FUNCTION__, KeyIdx); + pIV = pWapiSta->lastTxUnicastPN; + pMicKey = pWapiSta->wapiUskUpdate.micKey; + pDataKey = pWapiSta->wapiUskUpdate.dataKey; + }else{ + KeyIdx = pWapiSta->wapiUsk.keyId; + WAPI_TRACE(WAPI_TX, "%s(): Use USK!! KeyIdx=%d\n", __FUNCTION__, KeyIdx); + pIV = pWapiSta->lastTxUnicastPN; + pMicKey = pWapiSta->wapiUsk.micKey; + pDataKey = pWapiSta->wapiUsk.dataKey; + } + }else{ + WAPI_TRACE(WAPI_ERR,"%s: Can not find Peer Sta!!\n",__FUNCTION__); + return; + } + }else{ + WAPI_TRACE(WAPI_ERR,"%s: wapiSTAUsedList is empty!!\n",__FUNCTION__); + return; + } + } + + SecPtr = pframe; + SecCalculateMicSMS4(KeyIdx, pMicKey, SecPtr, (SecPtr+DataOffset), pattrib->pktlen, MicBuffer); + + WAPI_DATA(WAPI_TX, "Encryption - MIC", MicBuffer, padapter->wapiInfo.extra_postfix_len); + + memcpy(pframe+pattrib->hdrlen+pattrib->iv_len+pattrib->pktlen-pattrib->icv_len, + (u8 *)MicBuffer, + padapter->wapiInfo.extra_postfix_len + ); + + + WapiSMS4Encryption(pDataKey, pIV, (SecPtr+DataOffset),pattrib->pktlen+pattrib->icv_len, (SecPtr+DataOffset), &OutputLength); + + WAPI_DATA(WAPI_TX, "Encryption - After SMS4 encryption",pframe,pattrib->hdrlen+pattrib->iv_len+pattrib->pktlen); + + WAPI_TRACE(WAPI_TX, "<=========%s\n", __FUNCTION__); +} + +u8 SecSWSMS4Decryption( + _adapter *padapter, + u8 *precv_frame, + struct recv_priv *precv_priv + ) +{ + PRT_WAPI_T pWapiInfo = &padapter->wapiInfo; + struct recv_frame_hdr *precv_hdr; + PRT_WAPI_STA_INFO pWapiSta = NULL; + u8 IVOffset, DataOffset, bFindMatchPeer = false, bUseUpdatedKey = false; + u8 KeyIdx, MicBuffer[16], lastRxPNforQoS[16]; + u8 *pRA, *pTA, *pMicKey, *pDataKey, *pLastRxPN, *pRecvPN, *pSecData, *pRecvMic, *pos; + u8 TID = 0; + u16 OutputLength, DataLen; + u8 bQosData; + struct sk_buff * pskb; + + WAPI_TRACE(WAPI_RX, "=========>%s\n", __FUNCTION__); + + return 0; + + precv_hdr = &((union recv_frame*)precv_frame)->u.hdr; + pskb = (struct sk_buff *)(precv_hdr->rx_data); + precv_hdr->bWapiCheckPNInDecrypt = WapiCheckPnInSwDecrypt(padapter, pskb); + WAPI_TRACE(WAPI_RX, "=========>%s: check PN %d\n", __FUNCTION__,precv_hdr->bWapiCheckPNInDecrypt); + WAPI_DATA(WAPI_RX, "Decryption - Before decryption", pskb->data, pskb->len); + + IVOffset = sMacHdrLng; + bQosData = GetFrameType(pskb->data) == WIFI_QOS_DATA_TYPE; + if (bQosData){ + IVOffset += 2; + } + + //if(GetHTC()) + // IVOffset += 4; + + //IVOffset += SNAP_SIZE + sizeof(u16); + + DataOffset = IVOffset + padapter->wapiInfo.extra_prefix_len; + + pRA = pskb->data + 4; + pTA = pskb->data + 10; + KeyIdx = *(pskb->data + IVOffset); + pRecvPN = pskb->data + IVOffset + 2; + pSecData = pskb->data + DataOffset; + DataLen = pskb->len - DataOffset; + pRecvMic = pskb->data + pskb->len - padapter->wapiInfo.extra_postfix_len; + TID = GetTid(pskb->data); + + if (!list_empty(&(pWapiInfo->wapiSTAUsedList))){ + list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { + if (0 == memcmp(pWapiSta->PeerMacAddr, pTA, 6)){ + bFindMatchPeer = true; + break; + } + } + } + + if (!bFindMatchPeer){ + WAPI_TRACE(WAPI_ERR, "%s: Can not find Peer Sta "MAC_FMT" for Key Info!!!\n", __FUNCTION__, MAC_ARG(pTA)); + return false; + } + + if( IS_MCAST(pRA) ){ + WAPI_TRACE(WAPI_RX, "%s: Multicast decryption !!!\n", __FUNCTION__); + if (pWapiSta->wapiMsk.keyId == KeyIdx && pWapiSta->wapiMsk.bSet){ + pLastRxPN = pWapiSta->lastRxMulticastPN; + if (!WapiComparePN(pRecvPN, pLastRxPN)){ + WAPI_TRACE(WAPI_ERR, "%s: MSK PN is not larger than last, Dropped!!!\n", __FUNCTION__); + WAPI_DATA(WAPI_ERR, "pRecvPN:", pRecvPN, 16); + WAPI_DATA(WAPI_ERR, "pLastRxPN:", pLastRxPN, 16); + return false; + } + + memcpy(pLastRxPN, pRecvPN, 16); + pMicKey = pWapiSta->wapiMsk.micKey; + pDataKey = pWapiSta->wapiMsk.dataKey; + }else if (pWapiSta->wapiMskUpdate.keyId == KeyIdx && pWapiSta->wapiMskUpdate.bSet){ + WAPI_TRACE(WAPI_RX, "%s: Use Updated MSK for Decryption !!!\n", __FUNCTION__); + bUseUpdatedKey = true; + memcpy(pWapiSta->lastRxMulticastPN, pRecvPN, 16); + pMicKey = pWapiSta->wapiMskUpdate.micKey; + pDataKey = pWapiSta->wapiMskUpdate.dataKey; + }else{ + WAPI_TRACE(WAPI_ERR, "%s: Can not find MSK with matched KeyIdx(%d), Dropped !!!\n", __FUNCTION__,KeyIdx); + return false; + } + } + else{ + WAPI_TRACE(WAPI_RX, "%s: Unicast decryption !!!\n", __FUNCTION__); + if (pWapiSta->wapiUsk.keyId == KeyIdx && pWapiSta->wapiUsk.bSet){ + WAPI_TRACE(WAPI_RX, "%s: Use USK for Decryption!!!\n", __FUNCTION__); + if(precv_hdr->bWapiCheckPNInDecrypt){ + if(GetFrameType(pskb->data) == WIFI_QOS_DATA_TYPE){ + WapiGetLastRxUnicastPNForQoSData(TID, pWapiSta, lastRxPNforQoS); + pLastRxPN = lastRxPNforQoS; + }else{ + pLastRxPN = pWapiSta->lastRxUnicastPN; + } + if (!WapiComparePN(pRecvPN, pLastRxPN)){ + return false; + } + if(bQosData){ + WapiSetLastRxUnicastPNForQoSData(TID, pRecvPN, pWapiSta); + }else{ + memcpy(pWapiSta->lastRxUnicastPN, pRecvPN, 16); + } + }else{ + memcpy(precv_hdr->WapiTempPN,pRecvPN,16); + } + + if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE)) + { + if ((pRecvPN[0] & 0x1) == 0){ + WAPI_TRACE(WAPI_ERR, "%s: Rx USK PN is not odd when Infra STA mode, Dropped !!!\n", __FUNCTION__); + return false; + } + } + + pMicKey = pWapiSta->wapiUsk.micKey; + pDataKey = pWapiSta->wapiUsk.dataKey; + } + else if (pWapiSta->wapiUskUpdate.keyId == KeyIdx && pWapiSta->wapiUskUpdate.bSet ){ + WAPI_TRACE(WAPI_RX, "%s: Use Updated USK for Decryption!!!\n", __FUNCTION__); + if(pWapiSta->bAuthenticatorInUpdata) + bUseUpdatedKey = true; + else + bUseUpdatedKey = false; + + if(bQosData){ + WapiSetLastRxUnicastPNForQoSData(TID, pRecvPN, pWapiSta); + }else{ + memcpy(pWapiSta->lastRxUnicastPN, pRecvPN, 16); + } + pMicKey = pWapiSta->wapiUskUpdate.micKey; + pDataKey = pWapiSta->wapiUskUpdate.dataKey; + }else{ + WAPI_TRACE(WAPI_ERR, "%s: No valid USK!!!KeyIdx=%d pWapiSta->wapiUsk.keyId=%d pWapiSta->wapiUskUpdate.keyId=%d\n", __FUNCTION__, KeyIdx, pWapiSta->wapiUsk.keyId, pWapiSta->wapiUskUpdate.keyId); + //dump_buf(pskb->data,pskb->len); + return false; + } + } + + WAPI_DATA(WAPI_RX, "Decryption - DataKey", pDataKey, 16); + WAPI_DATA(WAPI_RX, "Decryption - IV", pRecvPN, 16); + WapiSMS4Decryption(pDataKey, pRecvPN, pSecData, DataLen, pSecData, &OutputLength); + + if (OutputLength != DataLen) + WAPI_TRACE(WAPI_ERR, "%s: Output Length Error!!!!\n", __FUNCTION__); + + WAPI_DATA(WAPI_RX, "Decryption - After decryption", pskb->data, pskb->len); + + DataLen -= padapter->wapiInfo.extra_postfix_len; + + SecCalculateMicSMS4(KeyIdx, pMicKey, pskb->data, pSecData, DataLen, MicBuffer); + + WAPI_DATA(WAPI_RX, "Decryption - MIC received", pRecvMic, SMS4_MIC_LEN); + WAPI_DATA(WAPI_RX, "Decryption - MIC calculated", MicBuffer, SMS4_MIC_LEN); + + if (0 == memcmp(MicBuffer, pRecvMic, padapter->wapiInfo.extra_postfix_len)){ + WAPI_TRACE(WAPI_RX, "%s: Check MIC OK!!\n", __FUNCTION__); + if (bUseUpdatedKey){ + // delete the old key + if ( IS_MCAST(pRA) ){ + WAPI_TRACE(WAPI_API, "%s(): AE use new update MSK!!\n", __FUNCTION__); + pWapiSta->wapiMsk.keyId = pWapiSta->wapiMskUpdate.keyId; + memcpy(pWapiSta->wapiMsk.dataKey, pWapiSta->wapiMskUpdate.dataKey, 16); + memcpy(pWapiSta->wapiMsk.micKey, pWapiSta->wapiMskUpdate.micKey, 16); + pWapiSta->wapiMskUpdate.bTxEnable = pWapiSta->wapiMskUpdate.bSet = false; + }else{ + WAPI_TRACE(WAPI_API, "%s(): AE use new update USK!!\n", __FUNCTION__); + pWapiSta->wapiUsk.keyId = pWapiSta->wapiUskUpdate.keyId; + memcpy(pWapiSta->wapiUsk.dataKey, pWapiSta->wapiUskUpdate.dataKey, 16); + memcpy(pWapiSta->wapiUsk.micKey, pWapiSta->wapiUskUpdate.micKey, 16); + pWapiSta->wapiUskUpdate.bTxEnable = pWapiSta->wapiUskUpdate.bSet = false; + } + } + }else{ + WAPI_TRACE(WAPI_ERR, "%s: Check MIC Error, Dropped !!!!\n", __FUNCTION__); + return false; + } + + pos = pskb->data; + memmove(pos+padapter->wapiInfo.extra_prefix_len, pos, IVOffset); + skb_pull(pskb, padapter->wapiInfo.extra_prefix_len); + + WAPI_TRACE(WAPI_RX, "<=========%s\n", __FUNCTION__); + + return true; +} + +u32 rtw_sms4_encrypt(_adapter *padapter, u8 *pxmitframe) +{ + + u8 *pframe; + u32 res = _SUCCESS; + + WAPI_TRACE(WAPI_TX, "=========>%s\n", __FUNCTION__); + + if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) + { + WAPI_TRACE(WAPI_TX, "<========== %s, WAPI not supported or enabled!\n", __FUNCTION__); + return _FAIL; + } + + if(((struct xmit_frame*)pxmitframe)->buf_addr==NULL) + return _FAIL; + + pframe = ((struct xmit_frame*)pxmitframe)->buf_addr + TXDESC_OFFSET; + + SecSWSMS4Encryption(padapter, pxmitframe); + + WAPI_TRACE(WAPI_TX, "<=========%s\n", __FUNCTION__); + return res; +} + +u32 rtw_sms4_decrypt(_adapter *padapter, u8 *precvframe) +{ + u8 *pframe; + u32 res = _SUCCESS; + + WAPI_TRACE(WAPI_RX, "=========>%s\n", __FUNCTION__); + + if ((!padapter->WapiSupport) || (!padapter->wapiInfo.bWapiEnable)) + { + WAPI_TRACE(WAPI_RX, "<========== %s, WAPI not supported or enabled!\n", __FUNCTION__); + return _FAIL; + } + + + //drop packet when hw decrypt fail + //return tempraily + return _FAIL; + + //pframe=(unsigned char *)((union recv_frame*)precvframe)->u.hdr.rx_data; + + if (false == SecSWSMS4Decryption(padapter, precvframe, &padapter->recvpriv)) + { + WAPI_TRACE(WAPI_ERR, "%s():SMS4 decrypt frame error\n",__FUNCTION__); + return _FAIL; + } + + WAPI_TRACE(WAPI_RX, "<=========%s\n", __FUNCTION__); + return res; +} + +#else + +u32 rtw_sms4_encrypt(_adapter *padapter, u8 *pxmitframe) +{ + WAPI_TRACE(WAPI_TX, "=========>Dummy %s\n", __FUNCTION__); + WAPI_TRACE(WAPI_TX, "<=========Dummy %s\n", __FUNCTION__); + return _SUCCESS; +} + +u32 rtw_sms4_decrypt(_adapter *padapter, u8 *precvframe) +{ + WAPI_TRACE(WAPI_RX, "=========>Dummy %s\n", __FUNCTION__); + WAPI_TRACE(WAPI_RX, "<=========Dummy %s\n", __FUNCTION__); + return _SUCCESS; +} + +#endif + +#endif diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_wlan_util.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_wlan_util.c new file mode 100644 index 000000000..7ddbb1a22 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_wlan_util.c @@ -0,0 +1,4400 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_WLAN_UTIL_C_ + +#include + +unsigned char ARTHEROS_OUI1[] = {0x00, 0x03, 0x7f}; +unsigned char ARTHEROS_OUI2[] = {0x00, 0x13, 0x74}; + +unsigned char BROADCOM_OUI1[] = {0x00, 0x10, 0x18}; +unsigned char BROADCOM_OUI2[] = {0x00, 0x0a, 0xf7}; +unsigned char BROADCOM_OUI3[] = {0x00, 0x05, 0xb5}; + + +unsigned char CISCO_OUI[] = {0x00, 0x40, 0x96}; +unsigned char MARVELL_OUI[] = {0x00, 0x50, 0x43}; +unsigned char RALINK_OUI[] = {0x00, 0x0c, 0x43}; +unsigned char REALTEK_OUI[] = {0x00, 0xe0, 0x4c}; +unsigned char AIRGOCAP_OUI[] = {0x00, 0x0a, 0xf5}; + +unsigned char REALTEK_96B_IE[] = {0x00, 0xe0, 0x4c, 0x02, 0x01, 0x20}; + +extern unsigned char RTW_WPA_OUI[]; +extern unsigned char WPA_TKIP_CIPHER[4]; +extern unsigned char RSN_TKIP_CIPHER[4]; + +#define R2T_PHY_DELAY (0) + +//#define WAIT_FOR_BCN_TO_MIN (3000) +#define WAIT_FOR_BCN_TO_MIN (6000) +#define WAIT_FOR_BCN_TO_MAX (20000) + +#define DISCONNECT_BY_CHK_BCN_FAIL_OBSERV_PERIOD_IN_MS 1000 +#define DISCONNECT_BY_CHK_BCN_FAIL_THRESHOLD 3 + +static u8 rtw_basic_rate_cck[4] = { + IEEE80211_CCK_RATE_1MB|IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_2MB|IEEE80211_BASIC_RATE_MASK, + IEEE80211_CCK_RATE_5MB|IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_11MB|IEEE80211_BASIC_RATE_MASK +}; + +static u8 rtw_basic_rate_ofdm[3] = { + IEEE80211_OFDM_RATE_6MB|IEEE80211_BASIC_RATE_MASK, IEEE80211_OFDM_RATE_12MB|IEEE80211_BASIC_RATE_MASK, + IEEE80211_OFDM_RATE_24MB|IEEE80211_BASIC_RATE_MASK +}; + +static u8 rtw_basic_rate_mix[7] = { + IEEE80211_CCK_RATE_1MB|IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_2MB|IEEE80211_BASIC_RATE_MASK, + IEEE80211_CCK_RATE_5MB|IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_11MB|IEEE80211_BASIC_RATE_MASK, + IEEE80211_OFDM_RATE_6MB|IEEE80211_BASIC_RATE_MASK, IEEE80211_OFDM_RATE_12MB|IEEE80211_BASIC_RATE_MASK, + IEEE80211_OFDM_RATE_24MB|IEEE80211_BASIC_RATE_MASK +}; + +int new_bcn_max = 3; + +int cckrates_included(unsigned char *rate, int ratelen) +{ + int i; + + for(i = 0; i < ratelen; i++) + { + if ( (((rate[i]) & 0x7f) == 2) || (((rate[i]) & 0x7f) == 4) || + (((rate[i]) & 0x7f) == 11) || (((rate[i]) & 0x7f) == 22) ) + return _TRUE; + } + + return _FALSE; + +} + +int cckratesonly_included(unsigned char *rate, int ratelen) +{ + int i; + + for(i = 0; i < ratelen; i++) + { + if ( (((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) && + (((rate[i]) & 0x7f) != 11) && (((rate[i]) & 0x7f) != 22) ) + return _FALSE; + } + + return _TRUE; +} + +s8 rtw_get_tx_nss(_adapter *adapter, struct sta_info *psta) +{ + u8 rf_type = RF_1T1R, custom_rf_type, vht_mcs[2]; + s8 nss = 1; + + custom_rf_type = adapter->registrypriv.rf_config; + rtw_hal_get_hwreg(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + + if (!psta) + return nss; + + /* rf_config is dependent on efuse or sw config */ + if (custom_rf_type != RF_MAX_TYPE) + rf_type = custom_rf_type; + +#ifdef CONFIG_80211AC_VHT + if (psta->vhtpriv.vht_option) { + u8 vht_mcs[2]; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + struct vht_priv *pvhtpriv_ap = &pmlmepriv->vhtpriv; + + _rtw_memcpy(vht_mcs, psta->vhtpriv.vht_mcs_map, 2); + /* doesn't support 5~8 SS so far */ + vht_mcs[1] = 0xff; + switch (rf_type) { + case RF_1T1R: + case RF_1T2R: + vht_mcs[0] |= 0xfc; + break; + case RF_2T2R: + case RF_2T4R: + case RF_2T2R_GREEN: + case RF_2T3R: + vht_mcs[0] |= 0xf0; + break; + case RF_3T3R: + case RF_3T4R: + vht_mcs[0] |= 0xc0; + break; + default: + DBG_871X("%s,%d, unknown rf type\n", __func__, __LINE__); + break; + } + nss = rtw_vht_mcsmap_to_nss(vht_mcs); + } else +#endif /* CONFIG_80211AC_VHT */ + if (psta->htpriv.ht_option) { + u8 supp_mcs_set[4]; + + _rtw_memcpy(supp_mcs_set, psta->htpriv.ht_cap.supp_mcs_set, 4); + + switch (rf_type) { + case RF_1T1R: + case RF_1T2R: + supp_mcs_set[1] = supp_mcs_set[2] = supp_mcs_set[3] = 0; + break; + case RF_2T2R: + case RF_2T4R: + case RF_2T2R_GREEN: + case RF_2T3R: + supp_mcs_set[2] = supp_mcs_set[3] = 0; + break; + case RF_3T3R: + case RF_3T4R: + supp_mcs_set[3] = 0; + break; + default: + DBG_871X("%s,%d, unknown rf type\n", __func__, __LINE__); + break; + } + nss = rtw_ht_mcsset_to_nss(supp_mcs_set); + } + + DBG_871X("%s: %d SS, rf_type=%d\n", __func__, nss, rf_type); + return nss; +} + +u8 networktype_to_raid(_adapter *adapter,struct sta_info *psta) +{ + unsigned char raid; + switch(psta->wireless_mode) + { + case WIRELESS_11B: + raid = RATR_INX_WIRELESS_B; + break; + case WIRELESS_11A: + case WIRELESS_11G: + raid = RATR_INX_WIRELESS_G; + break; + case WIRELESS_11BG: + raid = RATR_INX_WIRELESS_GB; + break; + case WIRELESS_11_24N: + case WIRELESS_11_5N: + raid = RATR_INX_WIRELESS_N; + break; + case WIRELESS_11A_5N: + case WIRELESS_11G_24N: + raid = RATR_INX_WIRELESS_NG; + break; + case WIRELESS_11BG_24N: + raid = RATR_INX_WIRELESS_NGB; + break; + default: + raid = RATR_INX_WIRELESS_GB; + break; + + } + return raid; + +} + +u8 networktype_to_raid_ex(_adapter *adapter, struct sta_info *psta) +{ + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + u8 raid = RATEID_IDX_BGN_40M_1SS, cur_rf_type, rf_type, custom_rf_type; + s8 tx_nss; + + tx_nss = rtw_get_tx_nss(adapter, psta); + + switch(psta->wireless_mode) + { + case WIRELESS_11B: + raid = RATEID_IDX_B; + break; + case WIRELESS_11A: + case WIRELESS_11G: + raid = RATEID_IDX_G; + break; + case WIRELESS_11BG: + raid = RATEID_IDX_BG; + break; + case WIRELESS_11_24N: + case WIRELESS_11_5N: + case WIRELESS_11A_5N: + case WIRELESS_11G_24N: + if (tx_nss == 1) + raid = RATEID_IDX_GN_N1SS; + else if (tx_nss == 2) + raid = RATEID_IDX_GN_N2SS; + else if (tx_nss == 3) + raid = RATEID_IDX_BGN_3SS; + else + DBG_871X("tx_nss error!(tx_nss=%d)\n", tx_nss); + break; + case WIRELESS_11B_24N: + case WIRELESS_11BG_24N: + if (psta->bw_mode == CHANNEL_WIDTH_20) { + if (tx_nss == 1) + raid = RATEID_IDX_BGN_20M_1SS_BN; + else if (tx_nss == 2) + raid = RATEID_IDX_BGN_20M_2SS_BN; + else if (tx_nss == 3) + raid = RATEID_IDX_BGN_3SS; + else + DBG_871X("tx_nss error!(tx_nss=%d)\n", tx_nss); + } else { + if (tx_nss == 1) + raid = RATEID_IDX_BGN_40M_1SS; + else if (tx_nss == 2) + raid = RATEID_IDX_BGN_40M_2SS; + else if (tx_nss == 3) + raid = RATEID_IDX_BGN_3SS; + else + DBG_871X("tx_nss error!(tx_nss=%d)\n", tx_nss); + } + break; +#ifdef CONFIG_80211AC_VHT + case WIRELESS_11_5AC: + if (tx_nss == 1) + raid = RATEID_IDX_VHT_1SS; + else if (tx_nss == 2) + raid = RATEID_IDX_VHT_2SS; + else if (tx_nss == 3) + raid = RATEID_IDX_VHT_3SS; + else + DBG_871X("tx_nss error!(tx_nss=%d)\n", tx_nss); + break; + case WIRELESS_11_24AC: + if (psta->bw_mode >= CHANNEL_WIDTH_80) + { + if (tx_nss == 1) + raid = RATEID_IDX_VHT_1SS; + else if (tx_nss == 2) + raid = RATEID_IDX_VHT_2SS; + else if (tx_nss == 3) + raid = RATEID_IDX_VHT_3SS; + else + DBG_871X("tx_nss error!(tx_nss=%d)\n", tx_nss); + } + else + { + if (tx_nss == 1) + raid = RATEID_IDX_MIX1; + else if (tx_nss == 2) + raid = RATEID_IDX_MIX2; + else if (tx_nss == 3) + raid = RATEID_IDX_VHT_3SS; + else + DBG_871X("tx_nss error!(tx_nss=%d)\n", tx_nss); + } + break; +#endif + default: + DBG_871X("unexpected wireless mode!(psta->wireless_mode=%x)\n", psta->wireless_mode); + break; + + } + + /* DBG_871X("psta->wireless_mode=%x, tx_nss=%d\n", psta->wireless_mode, tx_nss); */ + + return raid; + +} + +u8 judge_network_type(_adapter *padapter, unsigned char *rate, int ratelen) +{ + u8 network_type = 0; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + + if(pmlmeext->cur_channel > 14) + { + if (pmlmeinfo->VHT_enable) + network_type = WIRELESS_11AC; + else if (pmlmeinfo->HT_enable) + network_type = WIRELESS_11_5N; + + network_type |= WIRELESS_11A; + } + else + { + if (pmlmeinfo->HT_enable) + { + network_type = WIRELESS_11_24N; + } + + if ((cckratesonly_included(rate, ratelen)) == _TRUE) + { + network_type |= WIRELESS_11B; + } + else if((cckrates_included(rate, ratelen)) == _TRUE) + { + network_type |= WIRELESS_11BG; + } + else + { + network_type |= WIRELESS_11G; + } + } + + return network_type; +} + +unsigned char ratetbl_val_2wifirate(unsigned char rate); +unsigned char ratetbl_val_2wifirate(unsigned char rate) +{ + unsigned char val = 0; + + switch (rate & 0x7f) + { + case 0: + val = IEEE80211_CCK_RATE_1MB; + break; + + case 1: + val = IEEE80211_CCK_RATE_2MB; + break; + + case 2: + val = IEEE80211_CCK_RATE_5MB; + break; + + case 3: + val = IEEE80211_CCK_RATE_11MB; + break; + + case 4: + val = IEEE80211_OFDM_RATE_6MB; + break; + + case 5: + val = IEEE80211_OFDM_RATE_9MB; + break; + + case 6: + val = IEEE80211_OFDM_RATE_12MB; + break; + + case 7: + val = IEEE80211_OFDM_RATE_18MB; + break; + + case 8: + val = IEEE80211_OFDM_RATE_24MB; + break; + + case 9: + val = IEEE80211_OFDM_RATE_36MB; + break; + + case 10: + val = IEEE80211_OFDM_RATE_48MB; + break; + + case 11: + val = IEEE80211_OFDM_RATE_54MB; + break; + + } + + return val; + +} + +int is_basicrate(_adapter *padapter, unsigned char rate); +int is_basicrate(_adapter *padapter, unsigned char rate) +{ + int i; + unsigned char val; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + for(i = 0; i < NumRates; i++) + { + val = pmlmeext->basicrate[i]; + + if ((val != 0xff) && (val != 0xfe)) + { + if (rate == ratetbl_val_2wifirate(val)) + { + return _TRUE; + } + } + } + + return _FALSE; +} + +unsigned int ratetbl2rateset(_adapter *padapter, unsigned char *rateset); +unsigned int ratetbl2rateset(_adapter *padapter, unsigned char *rateset) +{ + int i; + unsigned char rate; + unsigned int len = 0; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + for (i = 0; i < NumRates; i++) + { + rate = pmlmeext->datarate[i]; + + switch (rate) + { + case 0xff: + return len; + + case 0xfe: + continue; + + default: + rate = ratetbl_val_2wifirate(rate); + + if (is_basicrate(padapter, rate) == _TRUE) + { + rate |= IEEE80211_BASIC_RATE_MASK; + } + + rateset[len] = rate; + len++; + break; + } + } + return len; +} + +void get_rate_set(_adapter *padapter, unsigned char *pbssrate, int *bssrate_len) +{ + unsigned char supportedrates[NumRates]; + + _rtw_memset(supportedrates, 0, NumRates); + *bssrate_len = ratetbl2rateset(padapter, supportedrates); + _rtw_memcpy(pbssrate, supportedrates, *bssrate_len); +} + +void set_mcs_rate_by_mask(u8 *mcs_set, u32 mask) +{ + u8 mcs_rate_1r = (u8)(mask&0xff); + u8 mcs_rate_2r = (u8)((mask>>8)&0xff); + u8 mcs_rate_3r = (u8)((mask>>16)&0xff); + u8 mcs_rate_4r = (u8)((mask>>24)&0xff); + + mcs_set[0] &= mcs_rate_1r; + mcs_set[1] &= mcs_rate_2r; + mcs_set[2] &= mcs_rate_3r; + mcs_set[3] &= mcs_rate_4r; +} + +void UpdateBrateTbl( + IN PADAPTER Adapter, + IN u8 *mBratesOS +) +{ + u8 i; + u8 rate; + + // 1M, 2M, 5.5M, 11M, 6M, 12M, 24M are mandatory. + for(i=0;iiface_type == IFACE_PORT1) + { + Set_NETYPE1_MSR(padapter, type); + } + else +#endif + { + Set_NETYPE0_MSR(padapter, type); + } +} + +inline u8 rtw_get_oper_ch(_adapter *adapter) +{ + return adapter_to_dvobj(adapter)->oper_channel; +} + +inline void rtw_set_oper_ch(_adapter *adapter, u8 ch) +{ +#ifdef DBG_CH_SWITCH + const int len = 128; + char msg[128] = {0}; + int cnt = 0; + int i = 0; +#endif /* DBG_CH_SWITCH */ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + + if (dvobj->oper_channel != ch) { + dvobj->on_oper_ch_time = rtw_get_current_time(); + +#ifdef DBG_CH_SWITCH + cnt += snprintf(msg+cnt, len-cnt, "switch to ch %3u", ch); + + for (i = 0; i < dvobj->iface_nums; i++) { + _adapter *iface = dvobj->padapters[i]; + cnt += snprintf(msg+cnt, len-cnt, " ["ADPT_FMT":", ADPT_ARG(iface)); + if (iface->mlmeextpriv.cur_channel == ch) + cnt += snprintf(msg+cnt, len-cnt, "C"); + else + cnt += snprintf(msg+cnt, len-cnt, "_"); + if (iface->wdinfo.listen_channel == ch && !rtw_p2p_chk_state(&iface->wdinfo, P2P_STATE_NONE)) + cnt += snprintf(msg+cnt, len-cnt, "L"); + else + cnt += snprintf(msg+cnt, len-cnt, "_"); + cnt += snprintf(msg+cnt, len-cnt, "]"); + } + + DBG_871X(FUNC_ADPT_FMT" %s\n", FUNC_ADPT_ARG(adapter), msg); +#endif /* DBG_CH_SWITCH */ + } + + dvobj->oper_channel = ch; +} + +inline u8 rtw_get_oper_bw(_adapter *adapter) +{ + return adapter_to_dvobj(adapter)->oper_bwmode; +} + +inline void rtw_set_oper_bw(_adapter *adapter, u8 bw) +{ + adapter_to_dvobj(adapter)->oper_bwmode = bw; +} + +inline u8 rtw_get_oper_choffset(_adapter *adapter) +{ + return adapter_to_dvobj(adapter)->oper_ch_offset; +} + +inline void rtw_set_oper_choffset(_adapter *adapter, u8 offset) +{ + adapter_to_dvobj(adapter)->oper_ch_offset = offset; +} + +u8 rtw_get_offset_by_ch(u8 channel) +{ + u8 offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + + if(channel>=1 && channel<=4) + { + offset = HAL_PRIME_CHNL_OFFSET_LOWER; + } + else if(channel>=5 && channel<=14) + { + offset = HAL_PRIME_CHNL_OFFSET_UPPER; + } + else + { + switch(channel) + { + case 36: + case 44: + case 52: + case 60: + case 100: + case 108: + case 116: + case 124: + case 132: + case 149: + case 157: + offset = HAL_PRIME_CHNL_OFFSET_LOWER; + break; + case 40: + case 48: + case 56: + case 64: + case 104: + case 112: + case 120: + case 128: + case 136: + case 153: + case 161: + offset = HAL_PRIME_CHNL_OFFSET_UPPER; + break; + default: + offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; + } + + } + + return offset; + +} + +u8 rtw_get_center_ch(u8 channel, u8 chnl_bw, u8 chnl_offset) +{ + u8 center_ch = channel; + + if(chnl_bw == CHANNEL_WIDTH_80) + { + if((channel == 36) || (channel == 40) || (channel == 44) || (channel == 48) ) + center_ch = 42; + if((channel == 52) || (channel == 56) || (channel == 60) || (channel == 64) ) + center_ch = 58; + if((channel == 100) || (channel == 104) || (channel == 108) || (channel == 112) ) + center_ch = 106; + if((channel == 116) || (channel == 120) || (channel == 124) || (channel == 128) ) + center_ch = 122; + if((channel == 132) || (channel == 136) || (channel == 140) || (channel == 144) ) + center_ch = 138; + if((channel == 149) || (channel == 153) || (channel == 157) || (channel == 161) ) + center_ch = 155; + else if(channel <= 14) + center_ch = 7; + } + else if(chnl_bw == CHANNEL_WIDTH_40) + { + if (chnl_offset == HAL_PRIME_CHNL_OFFSET_LOWER) + center_ch = channel + 2; + else + center_ch = channel - 2; + } + + return center_ch; +} + +inline u32 rtw_get_on_oper_ch_time(_adapter *adapter) +{ + return adapter_to_dvobj(adapter)->on_oper_ch_time; +} + +inline u32 rtw_get_on_cur_ch_time(_adapter *adapter) +{ + if (adapter->mlmeextpriv.cur_channel == adapter_to_dvobj(adapter)->oper_channel) + return adapter_to_dvobj(adapter)->on_oper_ch_time; + else + return 0; +} + +void SelectChannel(_adapter *padapter, unsigned char channel) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + _enter_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL); + +#ifdef CONFIG_DFS_MASTER +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); + bool ori_overlap_radar_detect_ch = rtw_rfctl_overlap_radar_detect_ch(rfctl); + bool new_overlap_radar_detect_ch = _rtw_rfctl_overlap_radar_detect_ch(rfctl, channel + , adapter_to_dvobj(padapter)->oper_bwmode, adapter_to_dvobj(padapter)->oper_ch_offset); + + if (!ori_overlap_radar_detect_ch && new_overlap_radar_detect_ch) + rtw_odm_radar_detect_enable(padapter); + + if (new_overlap_radar_detect_ch && IS_UNDER_CAC(rfctl)) { + u8 pause = 0xFF; + + rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &pause); + } +#endif /* CONFIG_DFS_MASTER */ + + //saved channel info + rtw_set_oper_ch(padapter, channel); + + rtw_hal_set_chan(padapter, channel); + +#ifdef CONFIG_DFS_MASTER + if (ori_overlap_radar_detect_ch && !new_overlap_radar_detect_ch) { + u8 pause = 0x00; + + rtw_odm_radar_detect_disable(padapter); + rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &pause); + } +} +#endif /* CONFIG_DFS_MASTER */ + + _exit_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL); + +} + +void SetBWMode(_adapter *padapter, unsigned short bwmode, unsigned char channel_offset) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + _enter_critical_mutex(&(adapter_to_dvobj(padapter)->setbw_mutex), NULL); + +#ifdef CONFIG_DFS_MASTER +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); + bool ori_overlap_radar_detect_ch = rtw_rfctl_overlap_radar_detect_ch(rfctl); + bool new_overlap_radar_detect_ch = _rtw_rfctl_overlap_radar_detect_ch(rfctl + , adapter_to_dvobj(padapter)->oper_channel, bwmode, channel_offset); + + if (!ori_overlap_radar_detect_ch && new_overlap_radar_detect_ch) + rtw_odm_radar_detect_enable(padapter); + + if (new_overlap_radar_detect_ch && IS_UNDER_CAC(rfctl)) { + u8 pause = 0xFF; + + rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &pause); + } +#endif /* CONFIG_DFS_MASTER */ + + //saved bw info + rtw_set_oper_bw(padapter, bwmode); + rtw_set_oper_choffset(padapter, channel_offset); + + rtw_hal_set_bwmode(padapter, (CHANNEL_WIDTH)bwmode, channel_offset); + +#ifdef CONFIG_DFS_MASTER + if (ori_overlap_radar_detect_ch && !new_overlap_radar_detect_ch) { + u8 pause = 0x00; + + rtw_odm_radar_detect_disable(padapter); + rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &pause); + } +} +#endif /* CONFIG_DFS_MASTER */ + + _exit_critical_mutex(&(adapter_to_dvobj(padapter)->setbw_mutex), NULL); +} + +void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char channel_offset, unsigned short bwmode) +{ + u8 center_ch, chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; +#if (defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)) || defined(CONFIG_MCC_MODE) + u8 iqk_info_backup = _FALSE; +#endif + + if ( padapter->bNotifyChannelChange ) + { + DBG_871X( "[%s] ch = %d, offset = %d, bwmode = %d\n", __FUNCTION__, channel, channel_offset, bwmode ); + } + + center_ch = rtw_get_center_ch(channel, bwmode, channel_offset); + + if(bwmode == CHANNEL_WIDTH_80) + { + if(center_ch > channel) + chnl_offset80 = HAL_PRIME_CHNL_OFFSET_LOWER; + else if(center_ch < channel) + chnl_offset80 = HAL_PRIME_CHNL_OFFSET_UPPER; + else + chnl_offset80 = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + } + _enter_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL); + +#ifdef CONFIG_DFS_MASTER +{ + struct rf_ctl_t *rfctl = adapter_to_rfctl(padapter); + bool ori_overlap_radar_detect_ch = rtw_rfctl_overlap_radar_detect_ch(rfctl); + bool new_overlap_radar_detect_ch = _rtw_rfctl_overlap_radar_detect_ch(rfctl, channel, bwmode, channel_offset); + + if (!ori_overlap_radar_detect_ch && new_overlap_radar_detect_ch) + rtw_odm_radar_detect_enable(padapter); + + if (new_overlap_radar_detect_ch && IS_UNDER_CAC(rfctl)) { + u8 pause = 0xFF; + + rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &pause); + } +#endif /* CONFIG_DFS_MASTER */ + + //set Channel + //saved channel/bw info + rtw_set_oper_ch(padapter, channel); + rtw_set_oper_bw(padapter, bwmode); + rtw_set_oper_choffset(padapter, channel_offset); + +#if (defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)) || defined(CONFIG_MCC_MODE) + /* To check if we need to backup iqk info after switch chnl & bw */ + { + u8 take_care_iqk, do_iqk; + + rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk); + rtw_hal_get_hwreg(padapter, HW_VAR_DO_IQK, &do_iqk); + if ((take_care_iqk == _TRUE) && (do_iqk == _TRUE)) + iqk_info_backup = _TRUE; + } +#endif + + rtw_hal_set_chnl_bw(padapter, center_ch, bwmode, channel_offset, chnl_offset80); // set center channel + +#if (defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW)) || defined(CONFIG_MCC_MODE) + if (iqk_info_backup == _TRUE) + rtw_hal_ch_sw_iqk_info_backup(padapter); +#endif + +#ifdef CONFIG_DFS_MASTER + if (ori_overlap_radar_detect_ch && !new_overlap_radar_detect_ch) { + u8 pause = 0x00; + + rtw_odm_radar_detect_disable(padapter); + rtw_hal_set_hwreg(padapter, HW_VAR_TXPAUSE, &pause); + } +} +#endif /* CONFIG_DFS_MASTER */ + + _exit_critical_mutex(&(adapter_to_dvobj(padapter)->setch_mutex), NULL); +} + +int get_bsstype(unsigned short capability) +{ + if (capability & BIT(0)) + { + return WIFI_FW_AP_STATE; + } + else if (capability & BIT(1)) + { + return WIFI_FW_ADHOC_STATE; + } + else + { + return 0; + } +} + +__inline u8 *get_my_bssid(WLAN_BSSID_EX *pnetwork) +{ + return (pnetwork->MacAddress); +} + +u16 get_beacon_interval(WLAN_BSSID_EX *bss) +{ + unsigned short val; + _rtw_memcpy((unsigned char *)&val, rtw_get_beacon_interval_from_ie(bss->IEs), 2); + + return le16_to_cpu(val); + +} + +int is_client_associated_to_ap(_adapter *padapter) +{ + struct mlme_ext_priv *pmlmeext; + struct mlme_ext_info *pmlmeinfo; + + if(!padapter) + return _FAIL; + + pmlmeext = &padapter->mlmeextpriv; + pmlmeinfo = &(pmlmeext->mlmext_info); + + if ((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && ((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE)) + { + return _TRUE; + } + else + { + return _FAIL; + } +} + +int is_client_associated_to_ibss(_adapter *padapter) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if ((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)) + { + return _TRUE; + } + else + { + return _FAIL; + } +} + +int is_IBSS_empty(_adapter *padapter) +{ + int i; + struct macid_ctl_t *macid_ctl = &padapter->dvobj->macid_ctl; + + for (i = 0; i < macid_ctl->num; i++) { + if (!rtw_macid_is_used(macid_ctl, i)) + continue; + if (rtw_macid_get_if_g(macid_ctl, i) != padapter->iface_id) + continue; + if (!GET_H2CCMD_MSRRPT_PARM_OPMODE(&macid_ctl->h2c_msr[i])) + continue; + if (GET_H2CCMD_MSRRPT_PARM_ROLE(&macid_ctl->h2c_msr[i]) == H2C_MSR_ROLE_ADHOC) + return _FAIL; + } + + return _TRUE; +} + +unsigned int decide_wait_for_beacon_timeout(unsigned int bcn_interval) +{ + if ((bcn_interval << 2) < WAIT_FOR_BCN_TO_MIN) + { + return WAIT_FOR_BCN_TO_MIN; + } + else if ((bcn_interval << 2) > WAIT_FOR_BCN_TO_MAX) + { + return WAIT_FOR_BCN_TO_MAX; + } + else + { + return ((bcn_interval << 2)); + } +} + +void CAM_empty_entry( + PADAPTER Adapter, + u8 ucIndex +) +{ + rtw_hal_set_hwreg(Adapter, HW_VAR_CAM_EMPTY_ENTRY, (u8 *)(&ucIndex)); +} + +void invalidate_cam_all(_adapter *padapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + _irqL irqL; + u8 val8 = 0; + + rtw_hal_set_hwreg(padapter, HW_VAR_CAM_INVALID_ALL, &val8); + + _enter_critical_bh(&cam_ctl->lock, &irqL); + rtw_sec_cam_map_clr_all(&cam_ctl->used); + _rtw_memset(dvobj->cam_cache, 0, sizeof(struct sec_cam_ent) * SEC_CAM_ENT_NUM_SW_LIMIT); + _exit_critical_bh(&cam_ctl->lock, &irqL); +} + +void _clear_cam_entry(_adapter *padapter, u8 entry) +{ + unsigned char null_sta[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + unsigned char null_key[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,0x00, 0x00, 0x00, 0x00,0x00, 0x00, 0x00, 0x00}; + + rtw_sec_write_cam_ent(padapter, entry, 0, null_sta, null_key); +} + +inline void write_cam(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key) +{ +#ifdef CONFIG_WRITE_CACHE_ONLY + write_cam_cache(adapter, id ,ctrl, mac, key); +#else + rtw_sec_write_cam_ent(adapter, id, ctrl, mac, key); + write_cam_cache(adapter, id ,ctrl, mac, key); +#endif +} + +inline void clear_cam_entry(_adapter *adapter, u8 id) +{ + _clear_cam_entry(adapter, id); + clear_cam_cache(adapter, id); +} + +inline void write_cam_from_cache(_adapter *adapter, u8 id) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + _irqL irqL; + struct sec_cam_ent cache; + + _enter_critical_bh(&cam_ctl->lock, &irqL); + _rtw_memcpy(&cache, &dvobj->cam_cache[id], sizeof(struct sec_cam_ent)); + _exit_critical_bh(&cam_ctl->lock, &irqL); + + rtw_sec_write_cam_ent(adapter, id, cache.ctrl, cache.mac, cache.key); +} + +void write_cam_cache(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + _irqL irqL; + + _enter_critical_bh(&cam_ctl->lock, &irqL); + + dvobj->cam_cache[id].ctrl = ctrl; + _rtw_memcpy(dvobj->cam_cache[id].mac, mac, ETH_ALEN); + _rtw_memcpy(dvobj->cam_cache[id].key, key, 16); + + _exit_critical_bh(&cam_ctl->lock, &irqL); +} + +void clear_cam_cache(_adapter *adapter, u8 id) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + _irqL irqL; + + _enter_critical_bh(&cam_ctl->lock, &irqL); + + _rtw_memset(&(dvobj->cam_cache[id]), 0, sizeof(struct sec_cam_ent)); + + _exit_critical_bh(&cam_ctl->lock, &irqL); +} + +s16 rtw_get_camid(_adapter *adapter, struct sta_info *sta, s16 kid) +{ + u8 macid; + s16 camid; + + //cam_entry: + //0~3 for default key + + //for concurrent mode (ap+sta, sta+sta): + //default key is disable, using sw encrypt/decrypt + //camid 0, 1, 2, 3 is default entry for default key/group key + //macid = 1 is for bc/mc stainfo, no mapping to camid + //macid = 0 mapping to camid 4 + //for macid >=2, camid = macid+3; + + if (sta) { + struct mlme_ext_info *mlmeinfo = &adapter->mlmeextpriv.mlmext_info; + macid = sta->mac_id; + + if((mlmeinfo->state&0x03) == WIFI_FW_AP_STATE) { + if((macid == 1) || (macid>(NUM_STA-4))){ + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" failed, mac_id=%d\n", FUNC_ADPT_ARG(adapter), macid); + camid = -1; + goto exit; + } + } + + if(macid==0) + camid = 4; + else if(macid >=2) + camid = macid + 3; + else + camid = 4; + } + else { + /* default key is disabled */ + camid = -1; + } + +exit: + return (s16)camid; +} + +inline bool _rtw_camctl_chk_cap(_adapter *adapter, u8 cap) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + + if (cam_ctl->sec_cap & cap) + return _TRUE; + return _FALSE; +} + +inline void _rtw_camctl_set_flags(_adapter *adapter, u32 flags) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + + cam_ctl->flags |= flags; +} + +inline void rtw_camctl_set_flags(_adapter *adapter, u32 flags) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + _irqL irqL; + + _enter_critical_bh(&cam_ctl->lock, &irqL); + _rtw_camctl_set_flags(adapter, flags); + _exit_critical_bh(&cam_ctl->lock, &irqL); +} + +inline void _rtw_camctl_clr_flags(_adapter *adapter, u32 flags) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + + cam_ctl->flags &= ~flags; +} + +inline void rtw_camctl_clr_flags(_adapter *adapter, u32 flags) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + _irqL irqL; + + _enter_critical_bh(&cam_ctl->lock, &irqL); + _rtw_camctl_clr_flags(adapter, flags); + _exit_critical_bh(&cam_ctl->lock, &irqL); +} + +inline bool _rtw_camctl_chk_flags(_adapter *adapter, u32 flags) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + + if (cam_ctl->flags & flags) + return _TRUE; + return _FALSE; +} + +void dump_sec_cam_map(void *sel, struct sec_cam_bmp *map, u8 max_num) +{ + DBG_871X_SEL_NL(sel, "0x%08x\n", map->m0); +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32) + if (max_num && max_num > 32) + DBG_871X_SEL_NL(sel, "0x%08x\n", map->m1); +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64) + if (max_num && max_num > 64) + DBG_871X_SEL_NL(sel, "0x%08x\n", map->m2); +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96) + if (max_num && max_num > 96) + DBG_871X_SEL_NL(sel, "0x%08x\n", map->m3); +#endif +} + +inline bool rtw_sec_camid_is_set(struct sec_cam_bmp *map, u8 id) +{ + if (id < 32) + return (map->m0 & BIT(id)); +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32) + else if (id < 64) + return (map->m1 & BIT(id - 32)); +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64) + else if (id < 96) + return (map->m2 & BIT(id - 64)); +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96) + else if (id < 128) + return (map->m3 & BIT(id - 96)); +#endif + else + rtw_warn_on(1); + + return 0; +} + +inline void rtw_sec_cam_map_set(struct sec_cam_bmp *map, u8 id) +{ + if (id < 32) + map->m0 |= BIT(id); +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32) + else if (id < 64) + map->m1 |= BIT(id - 32); +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64) + else if (id < 96) + map->m2 |= BIT(id - 64); +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96) + else if (id < 128) + map->m3 |= BIT(id - 96); +#endif + else + rtw_warn_on(1); +} + +inline void rtw_sec_cam_map_clr(struct sec_cam_bmp *map, u8 id) +{ + if (id < 32) + map->m0 &= ~BIT(id); +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32) + else if (id < 64) + map->m1 &= ~BIT(id-32); +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64) + else if (id < 96) + map->m2 &= ~BIT(id-64); +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96) + else if (id < 128) + map->m3 &= ~BIT(id-96); +#endif + else + rtw_warn_on(1); +} + +inline void rtw_sec_cam_map_clr_all(struct sec_cam_bmp *map) +{ + map->m0 = 0; +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32) + map->m1 = 0; +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64) + map->m2 = 0; +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96) + map->m3 = 0; +#endif +} + +inline bool rtw_sec_camid_is_drv_forbid(struct cam_ctl_t *cam_ctl, u8 id) +{ + struct sec_cam_bmp forbid_map; + + forbid_map.m0 = 0x00000ff0; +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32) + forbid_map.m1 = 0x00000000; +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64) + forbid_map.m2 = 0x00000000; +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96) + forbid_map.m3 = 0x00000000; +#endif + + if (id < 32) + return (forbid_map.m0 & BIT(id)); +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32) + else if (id < 64) + return (forbid_map.m1 & BIT(id - 32)); +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64) + else if (id < 96) + return (forbid_map.m2 & BIT(id - 64)); +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96) + else if (id < 128) + return (forbid_map.m3 & BIT(id - 96)); +#endif + else + rtw_warn_on(1); + + return 1; +} + +bool _rtw_sec_camid_is_used(struct cam_ctl_t *cam_ctl, u8 id) +{ + bool ret = _FALSE; + + if (id >= cam_ctl->num) { + rtw_warn_on(1); + goto exit; + } + + #if 0 /* for testing */ + if (rtw_sec_camid_is_drv_forbid(cam_ctl, id)) { + ret = _TRUE; + goto exit; + } + #endif + + ret = rtw_sec_camid_is_set(&cam_ctl->used, id); + +exit: + return ret; +} + +inline bool rtw_sec_camid_is_used(struct cam_ctl_t *cam_ctl, u8 id) +{ + _irqL irqL; + bool ret; + + _enter_critical_bh(&cam_ctl->lock, &irqL); + ret = _rtw_sec_camid_is_used(cam_ctl, id); + _exit_critical_bh(&cam_ctl->lock, &irqL); + + return ret; +} + +inline bool _rtw_camid_is_gk(_adapter *adapter, u8 cam_id) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + bool ret = _FALSE; + + if (cam_id >= cam_ctl->num) { + rtw_warn_on(1); + goto exit; + } + + if (_rtw_sec_camid_is_used(cam_ctl, cam_id) == _FALSE) + goto exit; + + ret = (dvobj->cam_cache[cam_id].ctrl&BIT6)?_TRUE:_FALSE; + +exit: + return ret; +} + +inline bool rtw_camid_is_gk(_adapter *adapter, u8 cam_id) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + _irqL irqL; + bool ret; + + _enter_critical_bh(&cam_ctl->lock, &irqL); + ret = _rtw_camid_is_gk(adapter, cam_id); + _exit_critical_bh(&cam_ctl->lock, &irqL); + + return ret; +} + +bool cam_cache_chk(_adapter *adapter, u8 id, u8 *addr, s16 kid, s8 gk) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + bool ret = _FALSE; + + if (addr && _rtw_memcmp(dvobj->cam_cache[id].mac, addr, ETH_ALEN) == _FALSE) + goto exit; + if (kid >= 0 && kid != (dvobj->cam_cache[id].ctrl&0x03)) + goto exit; + if (gk != -1 && (gk?_TRUE:_FALSE) != _rtw_camid_is_gk(adapter, id)) + goto exit; + + ret = _TRUE; + +exit: + return ret; +} + +s16 _rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + int i; + s16 cam_id = -1; + + for (i = 0; i < cam_ctl->num; i++) { + if (cam_cache_chk(adapter, i, addr, kid, gk)) { + cam_id = i; + break; + } + } + + if (0) { + if (addr) + DBG_871X(FUNC_ADPT_FMT" addr:"MAC_FMT" kid:%d, gk:%d, return cam_id:%d\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(addr), kid, gk, cam_id); + else + DBG_871X(FUNC_ADPT_FMT" addr:%p kid:%d, gk:%d, return cam_id:%d\n" + , FUNC_ADPT_ARG(adapter), addr, kid, gk, cam_id); + } + + return cam_id; +} + +s16 rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + _irqL irqL; + s16 cam_id = -1; + + _enter_critical_bh(&cam_ctl->lock, &irqL); + cam_id = _rtw_camid_search(adapter, addr, kid, gk); + _exit_critical_bh(&cam_ctl->lock, &irqL); + + return cam_id; +} + +s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, bool *used) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + _irqL irqL; + s16 cam_id = -1; + + *used = _FALSE; + + _enter_critical_bh(&cam_ctl->lock, &irqL); + +#ifdef DYNAMIC_CAMID_ALLOC + { + struct mlme_ext_info *mlmeinfo = &adapter->mlmeextpriv.mlmext_info; + + if((((mlmeinfo->state&0x03) == WIFI_FW_AP_STATE) || ((mlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)) + && !sta) { + /* AP/Ad-hoc mode group key: static alloction to default key by key ID */ + if (kid > 3) { + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" group key with invalid key id:%u\n" + , FUNC_ADPT_ARG(adapter), kid); + rtw_warn_on(1); + goto bitmap_handle; + } + cam_id = kid; + } + else { + int i; + u8 *addr = sta?sta->hwaddr:NULL; + #if 0 /* for testing */ + static u8 start_id = 0; + #else + u8 start_id = 0; + #endif + + if(!sta) { + if (!(mlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) { + /* bypass STA mode group key setting before connected(ex:WEP) because bssid is not ready */ + goto bitmap_handle; + } + + addr = get_bssid(&adapter->mlmepriv); + } + + /* find cam entry which has the same addr, kid (, gk bit) */ + if (_rtw_camctl_chk_cap(adapter, SEC_CAP_CHK_BMC) == _TRUE) + i = _rtw_camid_search(adapter, addr, kid, sta?_FALSE:_TRUE); + else + i = _rtw_camid_search(adapter, addr, kid, -1); + + if (i >= 0) { + cam_id = i; + goto bitmap_handle; + } + + for (i = 0; i < cam_ctl->num; i++) { + /* bypass default key which is allocated statically */ + if (((i + start_id) % cam_ctl->num) < 4) + continue; + + if (_rtw_sec_camid_is_used(cam_ctl, ((i + start_id) % cam_ctl->num)) == _FALSE) + break; + } + + if (i == cam_ctl->num) { + if (sta) + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" pairwise key with "MAC_FMT" id:%u no room\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(addr), kid); + else + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" group key with "MAC_FMT" id:%u no room\n" + , FUNC_ADPT_ARG(adapter), MAC_ARG(addr), kid); + rtw_warn_on(1); + goto bitmap_handle; + } + + cam_id = ((i + start_id) % cam_ctl->num); + start_id = ((i + start_id + 1) % cam_ctl->num); + } + } +#else + cam_id = rtw_get_camid(adapter, sta, kid); +#endif /* DYNAMIC_CAMID_ALLOC */ + +bitmap_handle: + if (cam_id >= 0) { + *used = _rtw_sec_camid_is_used(cam_ctl, cam_id); + rtw_sec_cam_map_set(&cam_ctl->used, cam_id); + } + + _exit_critical_bh(&cam_ctl->lock, &irqL); + + return cam_id; +} + +void rtw_camid_free(_adapter *adapter, u8 cam_id) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + _irqL irqL; + + _enter_critical_bh(&cam_ctl->lock, &irqL); + + if (cam_id < cam_ctl->num) + rtw_sec_cam_map_clr(&cam_ctl->used, cam_id); + + _exit_critical_bh(&cam_ctl->lock, &irqL); +} + +void flush_all_cam_entry(_adapter *padapter) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + +#ifdef CONFIG_CONCURRENT_MODE + if(check_buddy_fwstate(padapter, _FW_LINKED) == _TRUE) + { + if(check_fwstate(pmlmepriv, WIFI_STATION_STATE)) + { + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta; + + psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress); + if(psta) { + if(psta->state & WIFI_AP_STATE) + {} //clear cam when ap free per sta_info + else { + rtw_clearstakey_cmd(padapter, psta, _FALSE); + } + } + } + else if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + { + /* clear default key */ + int i, cam_id; + u8 null_addr[ETH_ALEN]= {0,0,0,0,0,0}; + + for (i=0;i<4;i++) { + cam_id = rtw_camid_search(padapter, null_addr, i, -1); + if (cam_id >= 0) { + clear_cam_entry(padapter, cam_id); + rtw_camid_free(padapter, cam_id); + } + } + + /* clear default key related key search setting */ + #ifdef DYNAMIC_CAMID_ALLOC + rtw_hal_set_hwreg(padapter, HW_VAR_SEC_DK_CFG, (u8*)_FALSE); + #endif + + /* leave pairwise key when ap free per sta_info */ + } + } + else +#endif //CONFIG_CONCURRENT_MODE + { + invalidate_cam_all(padapter); + /* clear default key related key search setting */ + #ifdef DYNAMIC_CAMID_ALLOC + rtw_hal_set_hwreg(padapter, HW_VAR_SEC_DK_CFG, (u8*)_FALSE); + #endif + } +} + +#if defined(CONFIG_P2P) && defined(CONFIG_WFD) +void rtw_process_wfd_ie(_adapter *adapter, u8 *wfd_ie, u8 wfd_ielen, const char *tag) +{ + struct wifidirect_info *wdinfo = &adapter->wdinfo; + + u8 *attr_content; + u32 attr_contentlen = 0; + + if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) + return; + + DBG_871X("[%s] Found WFD IE\n", tag); + attr_content = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &attr_contentlen); + if (attr_content && attr_contentlen) { + wdinfo->wfd_info->peer_rtsp_ctrlport = RTW_GET_BE16(attr_content + 2); + DBG_871X("[%s] Peer PORT NUM = %d\n", tag, wdinfo->wfd_info->peer_rtsp_ctrlport); + } +} + +void rtw_process_wfd_ies(_adapter *adapter, u8 *ies, u8 ies_len, const char *tag) +{ + u8 *wfd_ie; + u32 wfd_ielen; + + if (!hal_chk_wl_func(adapter, WL_FUNC_MIRACAST)) + return; + + wfd_ie = rtw_get_wfd_ie(ies, ies_len, NULL, &wfd_ielen); + while (wfd_ie) { + rtw_process_wfd_ie(adapter, wfd_ie, wfd_ielen, tag); + wfd_ie = rtw_get_wfd_ie(wfd_ie + wfd_ielen, (ies + ies_len) - (wfd_ie + wfd_ielen), NULL, &wfd_ielen); + } +} +#endif /* defined(CONFIG_P2P) && defined(CONFIG_WFD) */ + +int WMM_param_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) +{ + //struct registry_priv *pregpriv = &padapter->registrypriv; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if(pmlmepriv->qospriv.qos_option==0) + { + pmlmeinfo->WMM_enable = 0; + return _FALSE; + } + + if(_rtw_memcmp(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element))) + { + return _FALSE; + } + else + { + _rtw_memcpy(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element)); + } + pmlmeinfo->WMM_enable = 1; + return _TRUE; + + /*if (pregpriv->wifi_spec == 1) + { + if (pmlmeinfo->WMM_enable == 1) + { + //todo: compare the parameter set count & decide wheher to update or not + return _FAIL; + } + else + { + pmlmeinfo->WMM_enable = 1; + _rtw_rtw_memcpy(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element)); + return _TRUE; + } + } + else + { + pmlmeinfo->WMM_enable = 0; + return _FAIL; + }*/ + +} + +void WMMOnAssocRsp(_adapter *padapter) +{ + u8 ACI, ACM, AIFS, ECWMin, ECWMax, aSifsTime; + u8 acm_mask; + u16 TXOP; + u32 acParm, i; + u32 edca[4], inx[4]; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct registry_priv *pregpriv = &padapter->registrypriv; + + acm_mask = 0; + + if (IsSupported5G(pmlmeext->cur_wireless_mode) || + (pmlmeext->cur_wireless_mode & WIRELESS_11_24N) ) + aSifsTime = 16; + else + aSifsTime = 10; + + if (pmlmeinfo->WMM_enable == 0) + { + padapter->mlmepriv.acm_mask = 0; + + AIFS = aSifsTime + (2 * pmlmeinfo->slotTime); + + if (pmlmeext->cur_wireless_mode & (WIRELESS_11G |WIRELESS_11A)) { + ECWMin = 4; + ECWMax = 10; + } else if (pmlmeext->cur_wireless_mode & WIRELESS_11B) { + ECWMin = 5; + ECWMax = 10; + } else { + ECWMin = 4; + ECWMax = 10; + } + + TXOP = 0; + acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm)); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm)); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm)); + + ECWMin = 2; + ECWMax = 3; + TXOP = 0x2f; + acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm)); + } + else + { + edca[0] = edca[1] = edca[2] = edca[3] = 0; + + for (i = 0; i < 4; i++) + { + ACI = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN >> 5) & 0x03; + ACM = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN >> 4) & 0x01; + + //AIFS = AIFSN * slot time + SIFS - r2t phy delay + AIFS = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN & 0x0f) * pmlmeinfo->slotTime + aSifsTime; + + ECWMin = (pmlmeinfo->WMM_param.ac_param[i].CW & 0x0f); + ECWMax = (pmlmeinfo->WMM_param.ac_param[i].CW & 0xf0) >> 4; + TXOP = le16_to_cpu(pmlmeinfo->WMM_param.ac_param[i].TXOP_limit); + + acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); + + switch (ACI) + { + case 0x0: + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm)); + acm_mask |= (ACM? BIT(1):0); + edca[XMIT_BE_QUEUE] = acParm; + break; + + case 0x1: + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm)); + //acm_mask |= (ACM? BIT(0):0); + edca[XMIT_BK_QUEUE] = acParm; + break; + + case 0x2: + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm)); + acm_mask |= (ACM? BIT(2):0); + edca[XMIT_VI_QUEUE] = acParm; + break; + + case 0x3: + rtw_hal_set_hwreg(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm)); + acm_mask |= (ACM? BIT(3):0); + edca[XMIT_VO_QUEUE] = acParm; + break; + } + + DBG_871X("WMM(%x): %x, %x\n", ACI, ACM, acParm); + } + + if(padapter->registrypriv.acm_method == 1) + rtw_hal_set_hwreg(padapter, HW_VAR_ACM_CTRL, (u8 *)(&acm_mask)); + else + padapter->mlmepriv.acm_mask = acm_mask; + + inx[0] = 0; inx[1] = 1; inx[2] = 2; inx[3] = 3; + + if(pregpriv->wifi_spec==1) + { + u32 j, tmp, change_inx=_FALSE; + + //entry indx: 0->vo, 1->vi, 2->be, 3->bk. + for(i=0; i<4; i++) + { + for(j=i+1; j<4; j++) + { + //compare CW and AIFS + if((edca[j] & 0xFFFF) < (edca[i] & 0xFFFF)) + { + change_inx = _TRUE; + } + else if((edca[j] & 0xFFFF) == (edca[i] & 0xFFFF)) + { + //compare TXOP + if((edca[j] >> 16) > (edca[i] >> 16)) + change_inx = _TRUE; + } + + if(change_inx) + { + tmp = edca[i]; + edca[i] = edca[j]; + edca[j] = tmp; + + tmp = inx[i]; + inx[i] = inx[j]; + inx[j] = tmp; + + change_inx = _FALSE; + } + } + } + } + + for(i=0; i<4; i++) { + pxmitpriv->wmm_para_seq[i] = inx[i]; + DBG_871X("wmm_para_seq(%d): %d\n", i, pxmitpriv->wmm_para_seq[i]); + } + } +} + +static void bwmode_update_check(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) +{ +#ifdef CONFIG_80211N_HT + unsigned char new_bwmode; + unsigned char new_ch_offset; + struct HT_info_element *pHT_info; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct ht_priv *phtpriv = &pmlmepriv->htpriv; + u8 cbw40_enable=0; + + if(!pIE) + return; + + if(phtpriv->ht_option == _FALSE) return; + + if(pmlmeext->cur_bwmode >= CHANNEL_WIDTH_80) return; + + if(pIE->Length > sizeof(struct HT_info_element)) + return; + + pHT_info = (struct HT_info_element *)pIE->data; + + if (hal_chk_bw_cap(padapter, BW_CAP_40M)) { + if (pmlmeext->cur_channel > 14) { + if (REGSTY_IS_BW_5G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40)) + cbw40_enable = 1; + } else { + if (REGSTY_IS_BW_2G_SUPPORT(pregistrypriv, CHANNEL_WIDTH_40)) + cbw40_enable = 1; + } + } + + if((pHT_info->infos[0] & BIT(2)) && cbw40_enable) + { + new_bwmode = CHANNEL_WIDTH_40; + + switch (pHT_info->infos[0] & 0x3) + { + case 1: + new_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; + break; + + case 3: + new_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; + break; + + default: + new_bwmode = CHANNEL_WIDTH_20; + new_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; + } + } + else + { + new_bwmode = CHANNEL_WIDTH_20; + new_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + } + + + if ((new_bwmode != pmlmeext->cur_bwmode || new_ch_offset != pmlmeext->cur_ch_offset) + && new_bwmode < pmlmeext->cur_bwmode + ) { + pmlmeinfo->bwmode_updated = _TRUE; + + pmlmeext->cur_bwmode = new_bwmode; + pmlmeext->cur_ch_offset = new_ch_offset; + + //update HT info also + HT_info_handler(padapter, pIE); + } + else + { + pmlmeinfo->bwmode_updated = _FALSE; + } + + + if(_TRUE == pmlmeinfo->bwmode_updated) + { + struct sta_info *psta; + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + struct sta_priv *pstapriv = &padapter->stapriv; + + //set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); + + + //update ap's stainfo + psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress); + if(psta) + { + struct ht_priv *phtpriv_sta = &psta->htpriv; + + if(phtpriv_sta->ht_option) + { + // bwmode + psta->bw_mode = pmlmeext->cur_bwmode; + phtpriv_sta->ch_offset = pmlmeext->cur_ch_offset; + } + else + { + psta->bw_mode = CHANNEL_WIDTH_20; + phtpriv_sta->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + } + + rtw_dm_ra_mask_wk_cmd(padapter, (u8 *)psta); + } + + //pmlmeinfo->bwmode_updated = _FALSE;//bwmode_updated done, reset it! + } +#endif //CONFIG_80211N_HT +} + +void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) +{ +#ifdef CONFIG_80211N_HT + unsigned int i; + u8 rf_type = RF_1T1R; + u8 max_AMPDU_len, min_MPDU_spacing; + u8 cur_ldpc_cap=0, cur_stbc_cap=0, cur_beamform_cap=0; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct ht_priv *phtpriv = &pmlmepriv->htpriv; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + + if(pIE==NULL) return; + + if(phtpriv->ht_option == _FALSE) return; + + pmlmeinfo->HT_caps_enable = 1; + + for (i = 0; i < (pIE->Length); i++) + { + if (i != 2) + { + // Commented by Albert 2010/07/12 + // Got the endian issue here. + pmlmeinfo->HT_caps.u.HT_cap[i] &= (pIE->data[i]); + } + else + { + /* AMPDU Parameters field */ + + /* Get MIN of MAX AMPDU Length Exp */ + if ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3) > (pIE->data[i] & 0x3)) + { + max_AMPDU_len = (pIE->data[i] & 0x3); + } + else + { + max_AMPDU_len = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x3); + } + + /* Get MAX of MIN MPDU Start Spacing */ + if ((pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) > (pIE->data[i] & 0x1c)) + { + min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c); + } + else + { + min_MPDU_spacing = (pIE->data[i] & 0x1c); + } + + pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para = max_AMPDU_len | min_MPDU_spacing; + } + } + + // Commented by Albert 2010/07/12 + // Have to handle the endian issue after copying. + // HT_ext_caps didn't be used yet. + pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info = le16_to_cpu( pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info ); + pmlmeinfo->HT_caps.u.HT_cap_element.HT_ext_caps = le16_to_cpu( pmlmeinfo->HT_caps.u.HT_cap_element.HT_ext_caps ); + + rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + + + //update the MCS set + for (i = 0; i < 16; i++) + pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate[i] &= pmlmeext->default_supported_mcs_set[i]; + + //update the MCS rates + switch(rf_type) + { + case RF_1T1R: + case RF_1T2R: + set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_1R); + break; + case RF_2T2R: + #ifdef CONFIG_DISABLE_MCS13TO15 + if(pmlmeext->cur_bwmode == CHANNEL_WIDTH_40 && pregistrypriv->wifi_spec != 1 ) + set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R_13TO15_OFF); + else + set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R); +#else //CONFIG_DISABLE_MCS13TO15 + set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_2R); +#endif //CONFIG_DISABLE_MCS13TO15 + break; + case RF_3T3R: + set_mcs_rate_by_mask(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_RATE_3R); + break; + default: + DBG_871X("[warning] rf_type %d is not expected\n", rf_type); + } + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + // Config STBC setting + if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_TX_STBC(pIE->data)) + { + SET_FLAG(cur_stbc_cap, STBC_HT_ENABLE_TX); + DBG_871X("Enable HT Tx STBC !\n"); + } + phtpriv->stbc_cap = cur_stbc_cap; + +#ifdef CONFIG_BEAMFORMING + // Config Tx beamforming setting + if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) && + GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pIE->data)) + { + SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE); + /* Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/ + SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pIE->data) << 6); + } + + if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) && + GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pIE->data)) + { + SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE); + /* Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/ + SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pIE->data) << 4); + } + phtpriv->beamform_cap = cur_beamform_cap; + if (cur_beamform_cap) { + DBG_871X("AP HT Beamforming Cap = 0x%02X\n", cur_beamform_cap); + } +#endif /*CONFIG_BEAMFORMING*/ + } else { + /*WIFI_STATION_STATEorI_ADHOC_STATE or WIFI_ADHOC_MASTER_STATE*/ + // Config LDPC Coding Capability + if (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_TX) && GET_HT_CAP_ELE_LDPC_CAP(pIE->data)) + { + SET_FLAG(cur_ldpc_cap, (LDPC_HT_ENABLE_TX | LDPC_HT_CAP_TX)); + DBG_871X("Enable HT Tx LDPC!\n"); + } + phtpriv->ldpc_cap = cur_ldpc_cap; + + // Config STBC setting + if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX) && GET_HT_CAP_ELE_RX_STBC(pIE->data)) + { + SET_FLAG(cur_stbc_cap, (STBC_HT_ENABLE_TX | STBC_HT_CAP_TX) ); + DBG_871X("Enable HT Tx STBC!\n"); + } + phtpriv->stbc_cap = cur_stbc_cap; + +#ifdef CONFIG_BEAMFORMING + // Config Tx beamforming setting + if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE) && + GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(pIE->data)) + { + SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE); + /* Shift to BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP*/ + SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(pIE->data) << 6); + } + + if (TEST_FLAG(phtpriv->beamform_cap, BEAMFORMING_HT_BEAMFORMER_ENABLE) && + GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(pIE->data)) + { + SET_FLAG(cur_beamform_cap, BEAMFORMING_HT_BEAMFORMEE_ENABLE); + /* Shift to BEAMFORMING_HT_BEAMFORMER_STEER_NUM*/ + SET_FLAG(cur_beamform_cap, GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(pIE->data) << 4); + } + phtpriv->beamform_cap = cur_beamform_cap; + if (cur_beamform_cap) { + DBG_871X("Client HT Beamforming Cap = 0x%02X\n", cur_beamform_cap); + } +#endif /*CONFIG_BEAMFORMING*/ + } + +#endif //CONFIG_80211N_HT +} + +void HT_info_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) +{ +#ifdef CONFIG_80211N_HT + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct ht_priv *phtpriv = &pmlmepriv->htpriv; + + if(pIE==NULL) return; + + if(phtpriv->ht_option == _FALSE) return; + + + if(pIE->Length > sizeof(struct HT_info_element)) + return; + + pmlmeinfo->HT_info_enable = 1; + _rtw_memcpy(&(pmlmeinfo->HT_info), pIE->data, pIE->Length); +#endif //CONFIG_80211N_HT + return; +} + +void HTOnAssocRsp(_adapter *padapter) +{ + unsigned char max_AMPDU_len; + unsigned char min_MPDU_spacing; + //struct registry_priv *pregpriv = &padapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + DBG_871X("%s\n", __FUNCTION__); + + if ((pmlmeinfo->HT_info_enable) && (pmlmeinfo->HT_caps_enable)) + { + pmlmeinfo->HT_enable = 1; + } + else + { + pmlmeinfo->HT_enable = 0; + //set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); + return; + } + + //handle A-MPDU parameter field + /* + AMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k + AMPDU_para [4:2]:Min MPDU Start Spacing + */ + max_AMPDU_len = pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x03; + + min_MPDU_spacing = (pmlmeinfo->HT_caps.u.HT_cap_element.AMPDU_para & 0x1c) >> 2; + + rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_MIN_SPACE, (u8 *)(&min_MPDU_spacing)); + + rtw_hal_set_hwreg(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&max_AMPDU_len)); + +#if 0 //move to rtw_update_ht_cap() + if ((pregpriv->bw_mode > 0) && + (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & BIT(1)) && + (pmlmeinfo->HT_info.infos[0] & BIT(2))) + { + //switch to the 40M Hz mode accoring to the AP + pmlmeext->cur_bwmode = CHANNEL_WIDTH_40; + switch ((pmlmeinfo->HT_info.infos[0] & 0x3)) + { + case EXTCHNL_OFFSET_UPPER: + pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; + break; + + case EXTCHNL_OFFSET_LOWER: + pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; + break; + + default: + pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; + } + + //SelectChannel(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset); + } +#endif + + //set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); + +#if 0 //move to rtw_update_ht_cap() + // + // Config SM Power Save setting + // + pmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info & 0x0C) >> 2; + if(pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC) + { + /*u8 i; + //update the MCS rates + for (i = 0; i < 16; i++) + { + pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i]; + }*/ + DBG_871X("%s(): WLAN_HT_CAP_SM_PS_STATIC\n",__FUNCTION__); + } + + // + // Config current HT Protection mode. + // + pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3; +#endif + +} + +void ERP_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if(pIE->Length>1) + return; + + pmlmeinfo->ERP_enable = 1; + _rtw_memcpy(&(pmlmeinfo->ERP_IE), pIE->data, pIE->Length); +} + +void VCS_update(_adapter *padapter, struct sta_info *psta) +{ + struct registry_priv *pregpriv = &padapter->registrypriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + switch (pregpriv->vrtl_carrier_sense)/* 0:off 1:on 2:auto */ + { + case 0: //off + psta->rtsen = 0; + psta->cts2self = 0; + break; + + case 1: //on + if (pregpriv->vcs_type == 1) /* 1:RTS/CTS 2:CTS to self */ + { + psta->rtsen = 1; + psta->cts2self = 0; + } + else + { + psta->rtsen = 0; + psta->cts2self = 1; + } + break; + + case 2: //auto + default: + if (((pmlmeinfo->ERP_enable) && (pmlmeinfo->ERP_IE & BIT(1))) + /*||(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT)*/ + ) { + if (pregpriv->vcs_type == 1) { + psta->rtsen = 1; + psta->cts2self = 0; + } else { + psta->rtsen = 0; + psta->cts2self = 1; + } + } else { + psta->rtsen = 0; + psta->cts2self = 0; + } + break; + } +} + +void update_ldpc_stbc_cap(struct sta_info *psta) +{ +#ifdef CONFIG_80211N_HT + +#ifdef CONFIG_80211AC_VHT + if (psta->vhtpriv.vht_option) { + if(TEST_FLAG(psta->vhtpriv.ldpc_cap, LDPC_VHT_ENABLE_TX)) + psta->ldpc = 1; + + if(TEST_FLAG(psta->vhtpriv.stbc_cap, STBC_VHT_ENABLE_TX)) + psta->stbc = 1; + } + else +#endif //CONFIG_80211AC_VHT + if (psta->htpriv.ht_option) { + if(TEST_FLAG(psta->htpriv.ldpc_cap, LDPC_HT_ENABLE_TX)) + psta->ldpc = 1; + + if(TEST_FLAG(psta->htpriv.stbc_cap, STBC_HT_ENABLE_TX)) + psta->stbc = 1; + } else { + psta->ldpc = 0; + psta->stbc = 0; + } + +#endif //CONFIG_80211N_HT +} + + +/* + * rtw_get_bcn_keys: get beacon keys from recv frame + * + * TODO: + * WLAN_EID_COUNTRY + * WLAN_EID_ERP_INFO + * WLAN_EID_CHANNEL_SWITCH + * WLAN_EID_PWR_CONSTRAINT + */ +int rtw_get_bcn_keys(ADAPTER *Adapter, u8 *pframe, u32 packet_len, + struct beacon_keys *recv_beacon) +{ + int left; + u16 capability; + unsigned char *pos; + struct rtw_ieee802_11_elems elems; + struct rtw_ieee80211_ht_cap *pht_cap = NULL; + struct HT_info_element *pht_info = NULL; + + _rtw_memset(recv_beacon, 0, sizeof(*recv_beacon)); + + /* checking capabilities */ + capability = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN + 10)); + + /* checking IEs */ + left = packet_len - sizeof(struct rtw_ieee80211_hdr_3addr) - _BEACON_IE_OFFSET_; + pos = pframe + sizeof(struct rtw_ieee80211_hdr_3addr) + _BEACON_IE_OFFSET_; + if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed) + return _FALSE; + + /* check bw and channel offset */ + if (elems.ht_capabilities) { + if (elems.ht_capabilities_len != sizeof(*pht_cap)) + return _FALSE; + + pht_cap = (struct rtw_ieee80211_ht_cap *) elems.ht_capabilities; + recv_beacon->ht_cap_info = pht_cap->cap_info; + } + + if (elems.ht_operation) { + if (elems.ht_operation_len != sizeof(*pht_info)) + return _FALSE; + + pht_info = (struct HT_info_element *) elems.ht_operation; + recv_beacon->ht_info_infos_0_sco = pht_info->infos[0] & 0x03; + } + + /* Checking for channel */ + if (elems.ds_params && elems.ds_params_len == sizeof(recv_beacon->bcn_channel)) + _rtw_memcpy(&recv_beacon->bcn_channel, elems.ds_params, + sizeof(recv_beacon->bcn_channel)); + else if (pht_info) + /* In 5G, some ap do not have DSSET IE checking HT info for channel */ + recv_beacon->bcn_channel = pht_info->primary_channel; + else { + /* we don't find channel IE, so don't check it */ + //DBG_871X("Oops: %s we don't find channel IE, so don't check it \n", __func__); + recv_beacon->bcn_channel = Adapter->mlmeextpriv.cur_channel; + } + + /* checking SSID */ + if (elems.ssid) { + if (elems.ssid_len > sizeof(recv_beacon->ssid)) + return _FALSE; + + _rtw_memcpy(recv_beacon->ssid, elems.ssid, elems.ssid_len); + recv_beacon->ssid_len = elems.ssid_len; + } else; // means hidden ssid + + /* checking RSN first */ + if (elems.rsn_ie && elems.rsn_ie_len) { + recv_beacon->encryp_protocol = ENCRYP_PROTOCOL_WPA2; + rtw_parse_wpa2_ie(elems.rsn_ie - 2, elems.rsn_ie_len + 2, + &recv_beacon->group_cipher, &recv_beacon->pairwise_cipher, + &recv_beacon->is_8021x); + } + /* checking WPA secon */ + else if (elems.wpa_ie && elems.wpa_ie_len) { + recv_beacon->encryp_protocol = ENCRYP_PROTOCOL_WPA; + rtw_parse_wpa_ie(elems.wpa_ie - 2, elems.wpa_ie_len + 2, + &recv_beacon->group_cipher, &recv_beacon->pairwise_cipher, + &recv_beacon->is_8021x); + } + else if (capability & BIT(4)) { + recv_beacon->encryp_protocol = ENCRYP_PROTOCOL_WEP; + } + + return _TRUE; +} + +void rtw_dump_bcn_keys(struct beacon_keys *recv_beacon) +{ + int i; + char *p; + u8 ssid[IW_ESSID_MAX_SIZE + 1]; + + _rtw_memcpy(ssid, recv_beacon->ssid, recv_beacon->ssid_len); + ssid[recv_beacon->ssid_len] = '\0'; + + DBG_871X("%s: ssid = %s\n", __func__, ssid); + DBG_871X("%s: channel = %x\n", __func__, recv_beacon->bcn_channel); + DBG_871X("%s: ht_cap = %x\n", __func__, recv_beacon->ht_cap_info); + DBG_871X("%s: ht_info_infos_0_sco = %x\n", __func__, recv_beacon->ht_info_infos_0_sco); + DBG_871X("%s: sec=%d, group = %x, pair = %x, 8021X = %x\n", __func__, + recv_beacon->encryp_protocol, recv_beacon->group_cipher, + recv_beacon->pairwise_cipher, recv_beacon->is_8021x); +} + +int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len) +{ +#if 0 + unsigned int len; + unsigned char *p; + unsigned short val16, subtype; + struct wlan_network *cur_network = &(Adapter->mlmepriv.cur_network); + //u8 wpa_ie[255],rsn_ie[255]; + u16 wpa_len=0,rsn_len=0; + u8 encryp_protocol = 0; + WLAN_BSSID_EX *bssid; + int group_cipher = 0, pairwise_cipher = 0, is_8021x = 0; + unsigned char *pbuf; + u32 wpa_ielen = 0; + u8 *pbssid = GetAddr3Ptr(pframe); + u32 hidden_ssid = 0; + u8 cur_network_type, network_type=0; + struct HT_info_element *pht_info = NULL; + struct rtw_ieee80211_ht_cap *pht_cap = NULL; + u32 bcn_channel; + unsigned short ht_cap_info; + unsigned char ht_info_infos_0; +#endif + unsigned int len; + u8 *pbssid = GetAddr3Ptr(pframe); + struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; + struct wlan_network *cur_network = &(Adapter->mlmepriv.cur_network); + struct beacon_keys recv_beacon; + + if (is_client_associated_to_ap(Adapter) == _FALSE) + return _TRUE; + + len = packet_len - sizeof(struct rtw_ieee80211_hdr_3addr); + + if (len > MAX_IE_SZ) { + DBG_871X("%s IE too long for survey event\n", __func__); + return _FAIL; + } + + if (_rtw_memcmp(cur_network->network.MacAddress, pbssid, 6) == _FALSE) { + DBG_871X("Oops: rtw_check_network_encrypt linked but recv other bssid bcn\n" MAC_FMT MAC_FMT, + MAC_ARG(pbssid), MAC_ARG(cur_network->network.MacAddress)); + return _TRUE; + } + + if (rtw_get_bcn_keys(Adapter, pframe, packet_len, &recv_beacon) == _FALSE) + return _TRUE; // parsing failed => broken IE + + // don't care hidden ssid, use current beacon ssid directly + if (recv_beacon.ssid_len == 0) { + _rtw_memcpy(recv_beacon.ssid, pmlmepriv->cur_beacon_keys.ssid, + pmlmepriv->cur_beacon_keys.ssid_len); + recv_beacon.ssid_len = pmlmepriv->cur_beacon_keys.ssid_len; + } + + if (_rtw_memcmp(&recv_beacon, &pmlmepriv->cur_beacon_keys, sizeof(recv_beacon)) == _TRUE) + { + pmlmepriv->new_beacon_cnts = 0; + } + else if ((pmlmepriv->new_beacon_cnts == 0) || + _rtw_memcmp(&recv_beacon, &pmlmepriv->new_beacon_keys, sizeof(recv_beacon)) == _FALSE) + { + DBG_871X_LEVEL(_drv_err_, "%s: start new beacon (seq=%d)\n", __func__, GetSequence(pframe)); + + if (pmlmepriv->new_beacon_cnts == 0) { + DBG_871X_LEVEL(_drv_err_, "%s: cur beacon key\n", __func__); + DBG_871X_EXP(_drv_err_, rtw_dump_bcn_keys(&pmlmepriv->cur_beacon_keys)); + } + + DBG_871X_LEVEL(_drv_err_, "%s: new beacon key\n", __func__); + DBG_871X_EXP(_drv_err_, rtw_dump_bcn_keys(&recv_beacon)); + + memcpy(&pmlmepriv->new_beacon_keys, &recv_beacon, sizeof(recv_beacon)); + pmlmepriv->new_beacon_cnts = 1; + } + else + { + DBG_871X_LEVEL(_drv_err_, "%s: new beacon again (seq=%d)\n", __func__, GetSequence(pframe)); + pmlmepriv->new_beacon_cnts++; + } + + // if counter >= max, it means beacon is changed really + if (pmlmepriv->new_beacon_cnts >= new_bcn_max) + { + DBG_871X_LEVEL(_drv_err_, "%s: new beacon occur!!\n", __func__); + + // check bw mode change only? + pmlmepriv->cur_beacon_keys.ht_cap_info = recv_beacon.ht_cap_info; + pmlmepriv->cur_beacon_keys.ht_info_infos_0_sco = recv_beacon.ht_info_infos_0_sco; + + if (_rtw_memcmp(&recv_beacon, &pmlmepriv->cur_beacon_keys, + sizeof(recv_beacon)) == _FALSE) { + // beacon is changed, have to do disconnect/connect + return _FAIL; + } + + DBG_871X("%s bw mode change\n", __func__); + DBG_871X("%s bcn now: ht_cap_info:%x ht_info_infos_0:%x\n", __func__, + cur_network->BcnInfo.ht_cap_info, + cur_network->BcnInfo.ht_info_infos_0); + + cur_network->BcnInfo.ht_cap_info = recv_beacon.ht_cap_info; + cur_network->BcnInfo.ht_info_infos_0 = + (cur_network->BcnInfo.ht_info_infos_0 & (~0x03)) | + recv_beacon.ht_info_infos_0_sco; + + DBG_871X("%s bcn link: ht_cap_info:%x ht_info_infos_0:%x\n", __func__, + cur_network->BcnInfo.ht_cap_info, + cur_network->BcnInfo.ht_info_infos_0); + + memcpy(&pmlmepriv->cur_beacon_keys, &recv_beacon, sizeof(recv_beacon)); + pmlmepriv->new_beacon_cnts = 0; + } + + return _SUCCESS; + +#if 0 + bssid = (WLAN_BSSID_EX *)rtw_zmalloc(sizeof(WLAN_BSSID_EX)); + if (bssid == NULL) { + DBG_871X("%s rtw_zmalloc fail !!!\n", __func__); + return _TRUE; + } + + if ((pmlmepriv->timeBcnInfoChkStart != 0) && (rtw_get_passing_time_ms(pmlmepriv->timeBcnInfoChkStart) > DISCONNECT_BY_CHK_BCN_FAIL_OBSERV_PERIOD_IN_MS)) + { + pmlmepriv->timeBcnInfoChkStart = 0; + pmlmepriv->NumOfBcnInfoChkFail = 0; + } + + subtype = GetFrameSubType(pframe) >> 4; + + if(subtype==WIFI_BEACON) + bssid->Reserved[0] = 1; + + bssid->Length = sizeof(WLAN_BSSID_EX) - MAX_IE_SZ + len; + + /* below is to copy the information element */ + bssid->IELength = len; + _rtw_memcpy(bssid->IEs, (pframe + sizeof(struct rtw_ieee80211_hdr_3addr)), bssid->IELength); + + /* check bw and channel offset */ + /* parsing HT_CAP_IE */ + p = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _HT_CAPABILITY_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_); + if(p && len>0) { + pht_cap = (struct rtw_ieee80211_ht_cap *)(p + 2); + ht_cap_info = pht_cap->cap_info; + } else { + ht_cap_info = 0; + } + /* parsing HT_INFO_IE */ + p = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _HT_ADD_INFO_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_); + if(p && len>0) { + pht_info = (struct HT_info_element *)(p + 2); + ht_info_infos_0 = pht_info->infos[0]; + } else { + ht_info_infos_0 = 0; + } + if (ht_cap_info != cur_network->BcnInfo.ht_cap_info || + ((ht_info_infos_0&0x03) != (cur_network->BcnInfo.ht_info_infos_0&0x03))) { + DBG_871X("%s bcn now: ht_cap_info:%x ht_info_infos_0:%x\n", __func__, + ht_cap_info, ht_info_infos_0); + DBG_871X("%s bcn link: ht_cap_info:%x ht_info_infos_0:%x\n", __func__, + cur_network->BcnInfo.ht_cap_info, cur_network->BcnInfo.ht_info_infos_0); + DBG_871X("%s bw mode change\n", __func__); + { + //bcn_info_update + cur_network->BcnInfo.ht_cap_info = ht_cap_info; + cur_network->BcnInfo.ht_info_infos_0 = ht_info_infos_0; + //to do : need to check that whether modify related register of BB or not + } + //goto _mismatch; + } + + /* Checking for channel */ + p = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _DSSET_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_); + if (p) { + bcn_channel = *(p + 2); + } else {/* In 5G, some ap do not have DSSET IE checking HT info for channel */ + rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _HT_ADD_INFO_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_); + if(pht_info) { + bcn_channel = pht_info->primary_channel; + } else { /* we don't find channel IE, so don't check it */ + //DBG_871X("Oops: %s we don't find channel IE, so don't check it \n", __func__); + bcn_channel = Adapter->mlmeextpriv.cur_channel; + } + } + if (bcn_channel != Adapter->mlmeextpriv.cur_channel) { + DBG_871X("%s beacon channel:%d cur channel:%d disconnect\n", __func__, + bcn_channel, Adapter->mlmeextpriv.cur_channel); + goto _mismatch; + } + + /* checking SSID */ + if ((p = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _SSID_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_)) == NULL) { + DBG_871X("%s marc: cannot find SSID for survey event\n", __func__); + hidden_ssid = _TRUE; + } else { + hidden_ssid = _FALSE; + } + + if((NULL != p) && (_FALSE == hidden_ssid && (*(p + 1)))) { + _rtw_memcpy(bssid->Ssid.Ssid, (p + 2), *(p + 1)); + bssid->Ssid.SsidLength = *(p + 1); + } else { + bssid->Ssid.SsidLength = 0; + bssid->Ssid.Ssid[0] = '\0'; + } + + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("%s bssid.Ssid.Ssid:%s bssid.Ssid.SsidLength:%d " + "cur_network->network.Ssid.Ssid:%s len:%d\n", __func__, bssid->Ssid.Ssid, + bssid->Ssid.SsidLength, cur_network->network.Ssid.Ssid, + cur_network->network.Ssid.SsidLength)); + + if (_rtw_memcmp(bssid->Ssid.Ssid, cur_network->network.Ssid.Ssid, 32) == _FALSE || + bssid->Ssid.SsidLength != cur_network->network.Ssid.SsidLength) { + if (bssid->Ssid.Ssid[0] != '\0' && bssid->Ssid.SsidLength != 0) { /* not hidden ssid */ + DBG_871X("%s(), SSID is not match\n", __func__); + goto _mismatch; + } + } + + /* check encryption info */ + val16 = rtw_get_capability((WLAN_BSSID_EX *)bssid); + + if (val16 & BIT(4)) + bssid->Privacy = 1; + else + bssid->Privacy = 0; + + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_, + ("%s(): cur_network->network.Privacy is %d, bssid.Privacy is %d\n", + __func__, cur_network->network.Privacy,bssid->Privacy)); + if (cur_network->network.Privacy != bssid->Privacy) { + DBG_871X("%s(), privacy is not match\n",__func__); + goto _mismatch; + } + + rtw_get_sec_ie(bssid->IEs, bssid->IELength, NULL,&rsn_len,NULL,&wpa_len); + + if (rsn_len > 0) { + encryp_protocol = ENCRYP_PROTOCOL_WPA2; + } else if (wpa_len > 0) { + encryp_protocol = ENCRYP_PROTOCOL_WPA; + } else { + if (bssid->Privacy) + encryp_protocol = ENCRYP_PROTOCOL_WEP; + } + + if (cur_network->BcnInfo.encryp_protocol != encryp_protocol) { + DBG_871X("%s(): enctyp is not match\n",__func__); + goto _mismatch; + } + + if (encryp_protocol == ENCRYP_PROTOCOL_WPA || encryp_protocol == ENCRYP_PROTOCOL_WPA2) { + pbuf = rtw_get_wpa_ie(&bssid->IEs[12], &wpa_ielen, bssid->IELength-12); + if(pbuf && (wpa_ielen>0)) { + if (_SUCCESS == rtw_parse_wpa_ie(pbuf, wpa_ielen+2, &group_cipher, &pairwise_cipher, &is_8021x)) { + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_, + ("%s pnetwork->pairwise_cipher: %d, group_cipher is %d, is_8021x is %d\n", __func__, + pairwise_cipher, group_cipher, is_8021x)); + } + } else { + pbuf = rtw_get_wpa2_ie(&bssid->IEs[12], &wpa_ielen, bssid->IELength-12); + + if(pbuf && (wpa_ielen>0)) { + if (_SUCCESS == rtw_parse_wpa2_ie(pbuf, wpa_ielen+2, &group_cipher, &pairwise_cipher, &is_8021x)) { + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_, + ("%s pnetwork->pairwise_cipher: %d, pnetwork->group_cipher is %d, is_802x is %d\n", + __func__, pairwise_cipher, group_cipher, is_8021x)); + } + } + } + + RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_, + ("%s cur_network->group_cipher is %d: %d\n",__func__, cur_network->BcnInfo.group_cipher, group_cipher)); + if (pairwise_cipher != cur_network->BcnInfo.pairwise_cipher || group_cipher != cur_network->BcnInfo.group_cipher) { + DBG_871X("%s pairwise_cipher(%x:%x) or group_cipher(%x:%x) is not match\n",__func__, + pairwise_cipher, cur_network->BcnInfo.pairwise_cipher, + group_cipher, cur_network->BcnInfo.group_cipher); + goto _mismatch; + } + + if (is_8021x != cur_network->BcnInfo.is_8021x) { + DBG_871X("%s authentication is not match\n", __func__); + goto _mismatch; + } + } + + rtw_mfree((u8 *)bssid, sizeof(WLAN_BSSID_EX)); + return _SUCCESS; + +_mismatch: + rtw_mfree((u8 *)bssid, sizeof(WLAN_BSSID_EX)); + + if (pmlmepriv->NumOfBcnInfoChkFail == 0) + { + pmlmepriv->timeBcnInfoChkStart = rtw_get_current_time(); + } + + pmlmepriv->NumOfBcnInfoChkFail++; + DBG_871X("%s by "ADPT_FMT" - NumOfChkFail = %d (SeqNum of this Beacon frame = %d).\n", __func__, ADPT_ARG(Adapter), pmlmepriv->NumOfBcnInfoChkFail, GetSequence(pframe)); + + if ((pmlmepriv->timeBcnInfoChkStart != 0) && (rtw_get_passing_time_ms(pmlmepriv->timeBcnInfoChkStart) <= DISCONNECT_BY_CHK_BCN_FAIL_OBSERV_PERIOD_IN_MS) + && (pmlmepriv->NumOfBcnInfoChkFail >= DISCONNECT_BY_CHK_BCN_FAIL_THRESHOLD)) + { + DBG_871X("%s by "ADPT_FMT" - NumOfChkFail = %d >= threshold : %d (in %d ms), return FAIL.\n", __func__, ADPT_ARG(Adapter), pmlmepriv->NumOfBcnInfoChkFail, + DISCONNECT_BY_CHK_BCN_FAIL_THRESHOLD, rtw_get_passing_time_ms(pmlmepriv->timeBcnInfoChkStart)); + pmlmepriv->timeBcnInfoChkStart = 0; + pmlmepriv->NumOfBcnInfoChkFail = 0; + return _FAIL; + } + + return _SUCCESS; +#endif +} + +void update_beacon_info(_adapter *padapter, u8 *pframe, uint pkt_len, struct sta_info *psta) +{ + unsigned int i; + unsigned int len; + PNDIS_802_11_VARIABLE_IEs pIE; + +#ifdef CONFIG_TDLS + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + u8 tdls_prohibited[] = { 0x00, 0x00, 0x00, 0x00, 0x10 }; //bit(38): TDLS_prohibited +#endif //CONFIG_TDLS + + len = pkt_len - (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN); + + for (i = 0; i < len;) + { + pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN) + i); + + switch (pIE->ElementID) + { + case _VENDOR_SPECIFIC_IE_: + //to update WMM paramter set while receiving beacon + if (_rtw_memcmp(pIE->data, WMM_PARA_OUI, 6) && pIE->Length == WLAN_WMM_LEN) //WMM + { + (WMM_param_handler(padapter, pIE))? report_wmm_edca_update(padapter): 0; + } + + break; + + case _HT_EXTRA_INFO_IE_: //HT info + //HT_info_handler(padapter, pIE); + bwmode_update_check(padapter, pIE); + break; +#ifdef CONFIG_80211AC_VHT + case EID_OpModeNotification: + rtw_process_vht_op_mode_notify(padapter, pIE->data, psta); + break; +#endif //CONFIG_80211AC_VHT + case _ERPINFO_IE_: + ERP_IE_handler(padapter, pIE); + VCS_update(padapter, psta); + break; + +#ifdef CONFIG_TDLS + case _EXT_CAP_IE_: + if( check_ap_tdls_prohibited(pIE->data, pIE->Length) == _TRUE ) + ptdlsinfo->ap_prohibited = _TRUE; + if (check_ap_tdls_ch_switching_prohibited(pIE->data, pIE->Length) == _TRUE) + ptdlsinfo->ch_switch_prohibited = _TRUE; + break; +#endif //CONFIG_TDLS + default: + break; + } + + i += (pIE->Length + 2); + } +} + +#ifdef CONFIG_DFS +void process_csa_ie(_adapter *padapter, u8 *pframe, uint pkt_len) +{ + unsigned int i; + unsigned int len; + PNDIS_802_11_VARIABLE_IEs pIE; + u8 new_ch_no = 0; + + if(padapter->mlmepriv.handle_dfs == _TRUE ) + return; + + len = pkt_len - (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN); + + for (i = 0; i < len;) + { + pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN) + i); + + switch (pIE->ElementID) + { + case _CH_SWTICH_ANNOUNCE_: + padapter->mlmepriv.handle_dfs = _TRUE; + _rtw_memcpy(&new_ch_no, pIE->data+1, 1); + rtw_set_csa_cmd(padapter, new_ch_no); + break; + default: + break; + } + + i += (pIE->Length + 2); + } +} +#endif //CONFIG_DFS + +unsigned int is_ap_in_tkip(_adapter *padapter) +{ + u32 i; + PNDIS_802_11_VARIABLE_IEs pIE; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + + if (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY) + { + for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) + { + pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i); + + switch (pIE->ElementID) + { + case _VENDOR_SPECIFIC_IE_: + if ((_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4)) && (_rtw_memcmp((pIE->data + 12), WPA_TKIP_CIPHER, 4))) + { + return _TRUE; + } + break; + + case _RSN_IE_2_: + if (_rtw_memcmp((pIE->data + 8), RSN_TKIP_CIPHER, 4)) + { + return _TRUE; + } + + default: + break; + } + + i += (pIE->Length + 2); + } + + return _FALSE; + } + else + { + return _FALSE; + } + +} + +unsigned int should_forbid_n_rate(_adapter * padapter) +{ + u32 i; + PNDIS_802_11_VARIABLE_IEs pIE; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + WLAN_BSSID_EX *cur_network = &pmlmepriv->cur_network.network; + + if (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY) + { + for (i = sizeof(NDIS_802_11_FIXED_IEs); i < cur_network->IELength;) + { + pIE = (PNDIS_802_11_VARIABLE_IEs)(cur_network->IEs + i); + + switch (pIE->ElementID) + { + case _VENDOR_SPECIFIC_IE_: + if (_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4) && + ((_rtw_memcmp((pIE->data + 12), WPA_CIPHER_SUITE_CCMP, 4)) || + (_rtw_memcmp((pIE->data + 16), WPA_CIPHER_SUITE_CCMP, 4)))) + return _FALSE; + break; + + case _RSN_IE_2_: + if ((_rtw_memcmp((pIE->data + 8), RSN_CIPHER_SUITE_CCMP, 4)) || + (_rtw_memcmp((pIE->data + 12), RSN_CIPHER_SUITE_CCMP, 4))) + return _FALSE; + + default: + break; + } + + i += (pIE->Length + 2); + } + + return _TRUE; + } + else + { + return _FALSE; + } + +} + + +unsigned int is_ap_in_wep(_adapter *padapter) +{ + u32 i; + PNDIS_802_11_VARIABLE_IEs pIE; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + + if (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY) + { + for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) + { + pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i); + + switch (pIE->ElementID) + { + case _VENDOR_SPECIFIC_IE_: + if (_rtw_memcmp(pIE->data, RTW_WPA_OUI, 4)) + return _FALSE; + break; + + case _RSN_IE_2_: + return _FALSE; + + default: + break; + } + + i += (pIE->Length + 2); + } + + return _TRUE; + } + else + { + return _FALSE; + } + +} + +int wifirate2_ratetbl_inx(unsigned char rate); +int wifirate2_ratetbl_inx(unsigned char rate) +{ + int inx = 0; + rate = rate & 0x7f; + + switch (rate) + { + case 54*2: + inx = 11; + break; + + case 48*2: + inx = 10; + break; + + case 36*2: + inx = 9; + break; + + case 24*2: + inx = 8; + break; + + case 18*2: + inx = 7; + break; + + case 12*2: + inx = 6; + break; + + case 9*2: + inx = 5; + break; + + case 6*2: + inx = 4; + break; + + case 11*2: + inx = 3; + break; + case 11: + inx = 2; + break; + + case 2*2: + inx = 1; + break; + + case 1*2: + inx = 0; + break; + + } + return inx; +} + +unsigned int update_basic_rate(unsigned char *ptn, unsigned int ptn_sz) +{ + unsigned int i, num_of_rate; + unsigned int mask = 0; + + num_of_rate = (ptn_sz > NumRates)? NumRates: ptn_sz; + + for (i = 0; i < num_of_rate; i++) + { + if ((*(ptn + i)) & 0x80) + { + mask |= 0x1 << wifirate2_ratetbl_inx(*(ptn + i)); + } + } + return mask; +} + +unsigned int update_supported_rate(unsigned char *ptn, unsigned int ptn_sz) +{ + unsigned int i, num_of_rate; + unsigned int mask = 0; + + num_of_rate = (ptn_sz > NumRates)? NumRates: ptn_sz; + + for (i = 0; i < num_of_rate; i++) + { + mask |= 0x1 << wifirate2_ratetbl_inx(*(ptn + i)); + } + + return mask; +} + +unsigned int update_MCS_rate(struct HT_caps_element *pHT_caps) +{ + unsigned int mask = 0; + + mask = ((pHT_caps->u.HT_cap_element.MCS_rate[0] << 12) | (pHT_caps->u.HT_cap_element.MCS_rate[1] << 20)); + + return mask; +} + +int support_short_GI(_adapter *padapter, struct HT_caps_element *pHT_caps, u8 bwmode) +{ + unsigned char bit_offset; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if (!(pmlmeinfo->HT_enable)) + return _FAIL; + + bit_offset = (bwmode & CHANNEL_WIDTH_40)? 6: 5; + + if (pHT_caps->u.HT_cap_element.HT_caps_info & (0x1 << bit_offset)) + { + return _SUCCESS; + } + else + { + return _FAIL; + } +} + +unsigned char get_highest_rate_idx(u32 mask) +{ + int i; + unsigned char rate_idx=0; + + for(i=31; i>=0; i--) + { + if(mask & BIT(i)) + { + rate_idx = i; + break; + } + } + + return rate_idx; +} + +unsigned char get_highest_mcs_rate(struct HT_caps_element *pHT_caps); +unsigned char get_highest_mcs_rate(struct HT_caps_element *pHT_caps) +{ + int i, mcs_rate; + + mcs_rate = (pHT_caps->u.HT_cap_element.MCS_rate[0] | (pHT_caps->u.HT_cap_element.MCS_rate[1] << 8)); + + for (i = 15; i >= 0; i--) + { + if (mcs_rate & (0x1 << i)) + { + break; + } + } + + return i; +} + +void Update_RA_Entry(_adapter *padapter, struct sta_info *psta) +{ + rtw_hal_update_ra_mask(psta, psta->rssi_level); +} + +void enable_rate_adaptive(_adapter *padapter, struct sta_info *psta); +void enable_rate_adaptive(_adapter *padapter, struct sta_info *psta) +{ + Update_RA_Entry(padapter, psta); +} + +void set_sta_rate(_adapter *padapter, struct sta_info *psta) +{ + //rate adaptive + enable_rate_adaptive(padapter, psta); +} + +// Update RRSR and Rate for USERATE +void update_tx_basic_rate(_adapter *padapter, u8 wirelessmode) +{ + NDIS_802_11_RATES_EX supported_rates; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; +#ifdef CONFIG_P2P + struct wifidirect_info* pwdinfo = &padapter->wdinfo; + + // Added by Albert 2011/03/22 + // In the P2P mode, the driver should not support the b mode. + // So, the Tx packet shouldn't use the CCK rate + if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + return; +#endif //CONFIG_P2P +#ifdef CONFIG_INTEL_WIDI + if (padapter->mlmepriv.widi_state != INTEL_WIDI_STATE_NONE) + return; +#endif //CONFIG_INTEL_WIDI + + _rtw_memset(supported_rates, 0, NDIS_802_11_LENGTH_RATES_EX); + + //clear B mod if current channel is in 5G band, avoid tx cck rate in 5G band. + if(pmlmeext->cur_channel > 14) + wirelessmode &= ~(WIRELESS_11B); + + if ((wirelessmode & WIRELESS_11B) && (wirelessmode == WIRELESS_11B)) { + _rtw_memcpy(supported_rates, rtw_basic_rate_cck, 4); + } else if (wirelessmode & WIRELESS_11B) { + _rtw_memcpy(supported_rates, rtw_basic_rate_mix, 7); + } else { + _rtw_memcpy(supported_rates, rtw_basic_rate_ofdm, 3); + } + + if (wirelessmode & WIRELESS_11B) + update_mgnt_tx_rate(padapter, IEEE80211_CCK_RATE_1MB); + else + update_mgnt_tx_rate(padapter, IEEE80211_OFDM_RATE_6MB); + + rtw_hal_set_hwreg(padapter, HW_VAR_BASIC_RATE, supported_rates); +} + +unsigned char check_assoc_AP(u8 *pframe, uint len) +{ + unsigned int i; + PNDIS_802_11_VARIABLE_IEs pIE; + + for (i = sizeof(NDIS_802_11_FIXED_IEs); i < len;) + { + pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i); + + switch (pIE->ElementID) + { + case _VENDOR_SPECIFIC_IE_: + if ((_rtw_memcmp(pIE->data, ARTHEROS_OUI1, 3)) || (_rtw_memcmp(pIE->data, ARTHEROS_OUI2, 3))) + { + DBG_871X("link to Artheros AP\n"); + return HT_IOT_PEER_ATHEROS; + } + else if ( (_rtw_memcmp(pIE->data, BROADCOM_OUI1, 3)) + || (_rtw_memcmp(pIE->data, BROADCOM_OUI2, 3)) + || (_rtw_memcmp(pIE->data, BROADCOM_OUI3, 3))) + { + DBG_871X("link to Broadcom AP\n"); + return HT_IOT_PEER_BROADCOM; + } + else if (_rtw_memcmp(pIE->data, MARVELL_OUI, 3)) + { + DBG_871X("link to Marvell AP\n"); + return HT_IOT_PEER_MARVELL; + } + else if (_rtw_memcmp(pIE->data, RALINK_OUI, 3)) + { + DBG_871X("link to Ralink AP\n"); + return HT_IOT_PEER_RALINK; + } + else if (_rtw_memcmp(pIE->data, CISCO_OUI, 3)) + { + DBG_871X("link to Cisco AP\n"); + return HT_IOT_PEER_CISCO; + } + else if (_rtw_memcmp(pIE->data, REALTEK_OUI, 3)) + { + u32 Vender = HT_IOT_PEER_REALTEK; + + if(pIE->Length >= 5) { + if(pIE->data[4]==1) + { + //if(pIE->data[5] & RT_HT_CAP_USE_LONG_PREAMBLE) + // bssDesc->BssHT.RT2RT_HT_Mode |= RT_HT_CAP_USE_LONG_PREAMBLE; + + if(pIE->data[5] & RT_HT_CAP_USE_92SE) + { + //bssDesc->BssHT.RT2RT_HT_Mode |= RT_HT_CAP_USE_92SE; + Vender = HT_IOT_PEER_REALTEK_92SE; + } + } + + if(pIE->data[5] & RT_HT_CAP_USE_SOFTAP) + Vender = HT_IOT_PEER_REALTEK_SOFTAP; + + if(pIE->data[4] == 2) + { + if(pIE->data[6] & RT_HT_CAP_USE_JAGUAR_BCUT) { + Vender = HT_IOT_PEER_REALTEK_JAGUAR_BCUTAP; + DBG_871X("link to Realtek JAGUAR_BCUTAP\n"); + } + if(pIE->data[6] & RT_HT_CAP_USE_JAGUAR_CCUT) { + Vender = HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP; + DBG_871X("link to Realtek JAGUAR_CCUTAP\n"); + } + } + } + + DBG_871X("link to Realtek AP\n"); + return Vender; + } + else if (_rtw_memcmp(pIE->data, AIRGOCAP_OUI,3)) + { + DBG_871X("link to Airgo Cap\n"); + return HT_IOT_PEER_AIRGO; + } + else + { + break; + } + + default: + break; + } + + i += (pIE->Length + 2); + } + + DBG_871X("link to new AP\n"); + return HT_IOT_PEER_UNKNOWN; +} + +void update_capinfo(PADAPTER Adapter, u16 updateCap) +{ + struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + BOOLEAN ShortPreamble; + + // Check preamble mode, 2005.01.06, by rcnjko. + // Mark to update preamble value forever, 2008.03.18 by lanhsin + //if( pMgntInfo->RegPreambleMode == PREAMBLE_AUTO ) + { + + if(updateCap & cShortPreamble) + { // Short Preamble + if(pmlmeinfo->preamble_mode != PREAMBLE_SHORT) // PREAMBLE_LONG or PREAMBLE_AUTO + { + ShortPreamble = _TRUE; + pmlmeinfo->preamble_mode = PREAMBLE_SHORT; + rtw_hal_set_hwreg( Adapter, HW_VAR_ACK_PREAMBLE, (u8 *)&ShortPreamble ); + } + } + else + { // Long Preamble + if(pmlmeinfo->preamble_mode != PREAMBLE_LONG) // PREAMBLE_SHORT or PREAMBLE_AUTO + { + ShortPreamble = _FALSE; + pmlmeinfo->preamble_mode = PREAMBLE_LONG; + rtw_hal_set_hwreg( Adapter, HW_VAR_ACK_PREAMBLE, (u8 *)&ShortPreamble ); + } + } + } + + if ( updateCap & cIBSS ) { + //Filen: See 802.11-2007 p.91 + pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME; + } + else + { + //Filen: See 802.11-2007 p.90 + if( pmlmeext->cur_wireless_mode & (WIRELESS_11_24N | WIRELESS_11A | WIRELESS_11_5N | WIRELESS_11AC)) + { + pmlmeinfo->slotTime = SHORT_SLOT_TIME; + } + else if( pmlmeext->cur_wireless_mode & (WIRELESS_11G)) + { + if( (updateCap & cShortSlotTime) /* && (!(pMgntInfo->pHTInfo->RT2RT_HT_Mode & RT_HT_CAP_USE_LONG_PREAMBLE)) */) + { // Short Slot Time + pmlmeinfo->slotTime = SHORT_SLOT_TIME; + } + else + { // Long Slot Time + pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME; + } + } + else + { + //B Mode + pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME; + } + } + + rtw_hal_set_hwreg( Adapter, HW_VAR_SLOT_TIME, &pmlmeinfo->slotTime ); + +} + +/* +* set adapter.mlmeextpriv.mlmext_info.HT_enable +* set adapter.mlmeextpriv.cur_wireless_mode +* set SIFS register +* set mgmt tx rate +*/ +void update_wireless_mode(_adapter *padapter) +{ + int ratelen, network_type = 0; + u32 SIFS_Timer; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + unsigned char *rate = cur_network->SupportedRates; +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); +#endif //CONFIG_P2P + + ratelen = rtw_get_rateset_len(cur_network->SupportedRates); + + if ((pmlmeinfo->HT_info_enable) && (pmlmeinfo->HT_caps_enable)) + { + pmlmeinfo->HT_enable = 1; + } + + if(pmlmeext->cur_channel > 14) + { + if (pmlmeinfo->VHT_enable) + network_type = WIRELESS_11AC; + else if (pmlmeinfo->HT_enable) + network_type = WIRELESS_11_5N; + + network_type |= WIRELESS_11A; + } + else + { + if (pmlmeinfo->VHT_enable) + network_type = WIRELESS_11AC; + else if (pmlmeinfo->HT_enable) + network_type = WIRELESS_11_24N; + + if ((cckratesonly_included(rate, ratelen)) == _TRUE) + { + network_type |= WIRELESS_11B; + } + else if((cckrates_included(rate, ratelen)) == _TRUE) + { + network_type |= WIRELESS_11BG; + } + else + { + network_type |= WIRELESS_11G; + } + } + + pmlmeext->cur_wireless_mode = network_type & padapter->registrypriv.wireless_mode; + /* DBG_871X("network_type=%02x, padapter->registrypriv.wireless_mode=%02x\n", network_type, padapter->registrypriv.wireless_mode); */ +/* + if((pmlmeext->cur_wireless_mode==WIRELESS_11G) || + (pmlmeext->cur_wireless_mode==WIRELESS_11BG))//WIRELESS_MODE_G) + SIFS_Timer = 0x0a0a;//CCK + else + SIFS_Timer = 0x0e0e;//pHalData->SifsTime; //OFDM +*/ + + SIFS_Timer = 0x0a0a0808; //0x0808 -> for CCK, 0x0a0a -> for OFDM + //change this value if having IOT issues. + + rtw_hal_set_hwreg( padapter, HW_VAR_RESP_SIFS, (u8 *)&SIFS_Timer); + + rtw_hal_set_hwreg( padapter, HW_VAR_WIRELESS_MODE, (u8 *)&(pmlmeext->cur_wireless_mode)); + + if ((pmlmeext->cur_wireless_mode & WIRELESS_11B) +#ifdef CONFIG_P2P + && rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) +#endif /* CONFIG_P2P */ + ) + update_mgnt_tx_rate(padapter, IEEE80211_CCK_RATE_1MB); + else + update_mgnt_tx_rate(padapter, IEEE80211_OFDM_RATE_6MB); +} + +void fire_write_MAC_cmd(_adapter *padapter, unsigned int addr, unsigned int value); +void fire_write_MAC_cmd(_adapter *padapter, unsigned int addr, unsigned int value) +{ +#if 0 + struct cmd_obj *ph2c; + struct reg_rw_parm *pwriteMacPara; + struct cmd_priv *pcmdpriv = &(padapter->cmdpriv); + + if ((ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL) + { + return; + } + + if ((pwriteMacPara = (struct reg_rw_parm*)rtw_malloc(sizeof(struct reg_rw_parm))) == NULL) + { + rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); + return; + } + + pwriteMacPara->rw = 1; + pwriteMacPara->addr = addr; + pwriteMacPara->value = value; + + init_h2fwcmd_w_parm_no_rsp(ph2c, pwriteMacPara, GEN_CMD_CODE(_Write_MACREG)); + rtw_enqueue_cmd(pcmdpriv, ph2c); +#endif +} + +void update_sta_basic_rate(struct sta_info *psta, u8 wireless_mode) +{ + if(IsSupportedTxCCK(wireless_mode)) + { + // Only B, B/G, and B/G/N AP could use CCK rate + _rtw_memcpy(psta->bssrateset, rtw_basic_rate_cck, 4); + psta->bssratelen = 4; + } + else + { + _rtw_memcpy(psta->bssrateset, rtw_basic_rate_ofdm, 3); + psta->bssratelen = 3; + } +} + +int rtw_ies_get_supported_rate(u8 *ies, uint ies_len, u8 *rate_set, u8 *rate_num) +{ + u8 *ie; + unsigned int ie_len; + + if (!rate_set || !rate_num) + return _FALSE; + + *rate_num = 0; + + ie = rtw_get_ie(ies, _SUPPORTEDRATES_IE_, &ie_len, ies_len); + if (ie == NULL) + goto ext_rate; + + _rtw_memcpy(rate_set, ie + 2, ie_len); + *rate_num = ie_len; + +ext_rate: + ie = rtw_get_ie(ies, _EXT_SUPPORTEDRATES_IE_, &ie_len, ies_len); + if (ie) { + _rtw_memcpy(rate_set + *rate_num, ie + 2, ie_len); + *rate_num += ie_len; + } + + if (*rate_num == 0) + return _FAIL; + + if (0) { + int i; + + for (i = 0; i < *rate_num; i++) + DBG_871X("rate:0x%02x\n", *(rate_set + i)); + } + + return _SUCCESS; +} + +void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr) +{ + struct sta_info *psta; + u16 tid, start_seq, param; + struct sta_priv *pstapriv = &padapter->stapriv; + struct ADDBA_request *preq = (struct ADDBA_request*)paddba_req; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u8 size, accept = _FALSE; + + psta = rtw_get_stainfo(pstapriv, addr); + if (!psta) + goto exit; + + start_seq = le16_to_cpu(preq->BA_starting_seqctrl) >> 4; + + param = le16_to_cpu(preq->BA_para_set); + tid = (param>>2)&0x0f; + + + accept = rtw_rx_ampdu_is_accept(padapter); + size = rtw_rx_ampdu_size(padapter); + + if (accept == _TRUE) + rtw_addbarsp_cmd(padapter, addr, tid, 0, size, start_seq); + else + rtw_addbarsp_cmd(padapter, addr, tid, 37, size, start_seq); /* reject ADDBA Req */ + +exit: + return; +} + +void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len) +{ + u8* pIE; + u32 *pbuf; + + pIE = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + pbuf = (u32*)pIE; + + pmlmeext->TSFValue = le32_to_cpu(*(pbuf+1)); + + pmlmeext->TSFValue = pmlmeext->TSFValue << 32; + + pmlmeext->TSFValue |= le32_to_cpu(*pbuf); +} + +void correct_TSF(_adapter *padapter, struct mlme_ext_priv *pmlmeext) +{ + rtw_hal_set_hwreg(padapter, HW_VAR_CORRECT_TSF, 0); +} + +void adaptive_early_32k(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len) +{ + int i; + u8* pIE; + u32 *pbuf; + u64 tsf=0; + u32 delay_ms; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + + pmlmeext->bcn_cnt++; + + pIE = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + pbuf = (u32*)pIE; + + tsf = le32_to_cpu(*(pbuf+1)); + tsf = tsf << 32; + tsf |= le32_to_cpu(*pbuf); + + //DBG_871X("%s(): tsf_upper= 0x%08x, tsf_lower=0x%08x\n", __func__, (u32)(tsf>>32), (u32)tsf); + + //delay = (timestamp mod 1024*100)/1000 (unit: ms) + //delay_ms = do_div(tsf, (pmlmeinfo->bcn_interval*1024))/1000; + delay_ms = rtw_modular64(tsf, (pmlmeinfo->bcn_interval*1024)); + delay_ms = delay_ms/1000; + + if(delay_ms >= 8) + { + pmlmeext->bcn_delay_cnt[8]++; + //pmlmeext->bcn_delay_ratio[8] = (pmlmeext->bcn_delay_cnt[8] * 100) /pmlmeext->bcn_cnt; + } + else + { + pmlmeext->bcn_delay_cnt[delay_ms]++; + //pmlmeext->bcn_delay_ratio[delay_ms] = (pmlmeext->bcn_delay_cnt[delay_ms] * 100) /pmlmeext->bcn_cnt; + } + +/* + DBG_871X("%s(): (a)bcn_cnt = %d\n", __func__, pmlmeext->bcn_cnt); + + + for(i=0; i<9; i++) + { + DBG_871X("%s():bcn_delay_cnt[%d]=%d, bcn_delay_ratio[%d]=%d\n", __func__, i, + pmlmeext->bcn_delay_cnt[i] , i, pmlmeext->bcn_delay_ratio[i]); + } +*/ + + //dump for adaptive_early_32k + if(pmlmeext->bcn_cnt > 100 && (pmlmeext->adaptive_tsf_done==_TRUE)) + { + u8 ratio_20_delay, ratio_80_delay; + u8 DrvBcnEarly, DrvBcnTimeOut; + + ratio_20_delay = 0; + ratio_80_delay = 0; + DrvBcnEarly = 0xff; + DrvBcnTimeOut = 0xff; + + DBG_871X("%s(): bcn_cnt = %d\n", __func__, pmlmeext->bcn_cnt); + + for(i=0; i<9; i++) + { + pmlmeext->bcn_delay_ratio[i] = (pmlmeext->bcn_delay_cnt[i] * 100) /pmlmeext->bcn_cnt; + + + //DBG_871X("%s():bcn_delay_cnt[%d]=%d, bcn_delay_ratio[%d]=%d\n", __func__, i, + // pmlmeext->bcn_delay_cnt[i] , i, pmlmeext->bcn_delay_ratio[i]); + + ratio_20_delay += pmlmeext->bcn_delay_ratio[i]; + ratio_80_delay += pmlmeext->bcn_delay_ratio[i]; + + if(ratio_20_delay > 20 && DrvBcnEarly == 0xff) + { + DrvBcnEarly = i; + //DBG_871X("%s(): DrvBcnEarly = %d\n", __func__, DrvBcnEarly); + } + + if(ratio_80_delay > 80 && DrvBcnTimeOut == 0xff) + { + DrvBcnTimeOut = i; + //DBG_871X("%s(): DrvBcnTimeOut = %d\n", __func__, DrvBcnTimeOut); + } + + //reset adaptive_early_32k cnt + pmlmeext->bcn_delay_cnt[i] = 0; + pmlmeext->bcn_delay_ratio[i] = 0; + } + + pmlmeext->DrvBcnEarly = DrvBcnEarly; + pmlmeext->DrvBcnTimeOut = DrvBcnTimeOut; + + pmlmeext->bcn_cnt = 0; + } + +} + + +void beacon_timing_control(_adapter *padapter) +{ + rtw_hal_bcn_related_reg_setting(padapter); +} + +#define CONFIG_SHARED_BMC_MACID + +void dump_macid_map(void *sel, struct macid_bmp *map, u8 max_num) +{ + DBG_871X_SEL_NL(sel, "0x%08x\n", map->m0); +#if (MACID_NUM_SW_LIMIT > 32) + if (max_num && max_num > 32) + DBG_871X_SEL_NL(sel, "0x%08x\n", map->m1); +#endif +#if (MACID_NUM_SW_LIMIT > 64) + if (max_num && max_num > 64) + DBG_871X_SEL_NL(sel, "0x%08x\n", map->m2); +#endif +#if (MACID_NUM_SW_LIMIT > 96) + if (max_num && max_num > 96) + DBG_871X_SEL_NL(sel, "0x%08x\n", map->m3); +#endif +} + +inline bool rtw_macid_is_set(struct macid_bmp *map, u8 id) +{ + if (id < 32) + return (map->m0 & BIT(id)); +#if (MACID_NUM_SW_LIMIT > 32) + else if (id < 64) + return (map->m1 & BIT(id-32)); +#endif +#if (MACID_NUM_SW_LIMIT > 64) + else if (id < 96) + return (map->m2 & BIT(id-64)); +#endif +#if (MACID_NUM_SW_LIMIT > 96) + else if (id < 128) + return (map->m3 & BIT(id-96)); +#endif + else + rtw_warn_on(1); + + return 0; +} + +inline void rtw_macid_map_set(struct macid_bmp *map, u8 id) +{ + if (id < 32) + map->m0 |= BIT(id); +#if (MACID_NUM_SW_LIMIT > 32) + else if (id < 64) + map->m1 |= BIT(id-32); +#endif +#if (MACID_NUM_SW_LIMIT > 64) + else if (id < 96) + map->m2 |= BIT(id-64); +#endif +#if (MACID_NUM_SW_LIMIT > 96) + else if (id < 128) + map->m3 |= BIT(id-96); +#endif + else + rtw_warn_on(1); +} + +inline void rtw_macid_map_clr(struct macid_bmp *map, u8 id) +{ + if (id < 32) + map->m0 &= ~BIT(id); +#if (MACID_NUM_SW_LIMIT > 32) + else if (id < 64) + map->m1 &= ~BIT(id-32); +#endif +#if (MACID_NUM_SW_LIMIT > 64) + else if (id < 96) + map->m2 &= ~BIT(id-64); +#endif +#if (MACID_NUM_SW_LIMIT > 96) + else if (id < 128) + map->m3 &= ~BIT(id-96); +#endif + else + rtw_warn_on(1); +} + +inline bool rtw_macid_is_used(struct macid_ctl_t *macid_ctl, u8 id) +{ + return rtw_macid_is_set(&macid_ctl->used, id); +} + +inline bool rtw_macid_is_bmc(struct macid_ctl_t *macid_ctl, u8 id) +{ + return rtw_macid_is_set(&macid_ctl->bmc, id); +} + +inline s8 rtw_macid_get_if_g(struct macid_ctl_t *macid_ctl, u8 id) +{ + int i; + +#ifdef CONFIG_SHARED_BMC_MACID + if (rtw_macid_is_bmc(macid_ctl,id)) + return -1; +#endif + + for (i=0;iif_g[i], id)) + return i; + } + return -1; +} + +inline s8 rtw_macid_get_ch_g(struct macid_ctl_t *macid_ctl, u8 id) +{ + int i; + + for (i=0;i<2;i++) { + if (rtw_macid_is_set(&macid_ctl->ch_g[i], id)) + return i; + } + return -1; +} + +void rtw_alloc_macid(_adapter *padapter, struct sta_info *psta) +{ + int i; + _irqL irqL; + u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff}; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + struct macid_bmp *used_map = &macid_ctl->used; + //static u8 last_id = 0; /* for testing */ + u8 last_id = 0; + + if (_rtw_memcmp(psta->hwaddr, adapter_mac_addr(padapter), ETH_ALEN)) { + psta->mac_id = macid_ctl->num; + return; + } + +#ifdef CONFIG_SHARED_BMC_MACID + if(_rtw_memcmp(psta->hwaddr, bc_addr, ETH_ALEN)) { + /* use shared broadcast & multicast macid 1 */ + _enter_critical_bh(&macid_ctl->lock, &irqL); + rtw_macid_map_set(used_map, 1); + rtw_macid_map_set(&macid_ctl->bmc, 1); + for (i=0;iif_g[padapter->iface_id], 1); + macid_ctl->sta[1] = psta; + /* TODO ch_g? */ + _exit_critical_bh(&macid_ctl->lock, &irqL); + i = 1; + goto assigned; + } +#endif + + _enter_critical_bh(&macid_ctl->lock, &irqL); + + for (i=last_id;inum;i++) { + #ifdef CONFIG_SHARED_BMC_MACID + if (i == 1) + continue; + #endif + if (!rtw_macid_is_used(macid_ctl, i)) + break; + } + + if (i < macid_ctl->num) { + + rtw_macid_map_set(used_map, i); + + if(_rtw_memcmp(psta->hwaddr, bc_addr, ETH_ALEN)) + rtw_macid_map_set(&macid_ctl->bmc, i); + + rtw_macid_map_set(&macid_ctl->if_g[padapter->iface_id], i); + macid_ctl->sta[i] = psta; + + /* TODO ch_g? */ + + last_id++; + last_id %= macid_ctl->num; + } + + _exit_critical_bh(&macid_ctl->lock, &irqL); + + if (i >= macid_ctl->num) { + psta->mac_id = macid_ctl->num; + DBG_871X_LEVEL(_drv_err_, FUNC_ADPT_FMT" if%u, hwaddr:"MAC_FMT" no available macid\n" + , FUNC_ADPT_ARG(padapter), padapter->iface_id+1, MAC_ARG(psta->hwaddr)); + rtw_warn_on(1); + goto exit; + } else { + goto assigned; + } + +assigned: + psta->mac_id = i; + DBG_871X(FUNC_ADPT_FMT" if%u, hwaddr:"MAC_FMT" macid:%u\n" + , FUNC_ADPT_ARG(padapter), padapter->iface_id+1, MAC_ARG(psta->hwaddr), psta->mac_id); + +exit: + return; +} + +void rtw_release_macid(_adapter *padapter, struct sta_info *psta) +{ + _irqL irqL; + u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff}; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + + if (_rtw_memcmp(psta->hwaddr, adapter_mac_addr(padapter), ETH_ALEN)) + return; + +#ifdef CONFIG_SHARED_BMC_MACID + if(_rtw_memcmp(psta->hwaddr, bc_addr, ETH_ALEN)) + return; + + if (psta->mac_id == 1) { + DBG_871X_LEVEL(_drv_err_, FUNC_ADPT_FMT" if%u, hwaddr:"MAC_FMT" with macid:%u\n" + , FUNC_ADPT_ARG(padapter), padapter->iface_id+1, MAC_ARG(psta->hwaddr), psta->mac_id); + rtw_warn_on(1); + return; + } +#endif + + _enter_critical_bh(&macid_ctl->lock, &irqL); + + if (psta->mac_id < macid_ctl->num) { + int i; + + if (!rtw_macid_is_used(macid_ctl, psta->mac_id)) { + DBG_871X_LEVEL(_drv_err_, FUNC_ADPT_FMT" if%u, hwaddr:"MAC_FMT" macid:%u not used\n" + , FUNC_ADPT_ARG(padapter), padapter->iface_id+1, MAC_ARG(psta->hwaddr), psta->mac_id); + rtw_warn_on(1); + } + + rtw_macid_map_clr(&macid_ctl->used, psta->mac_id); + rtw_macid_map_clr(&macid_ctl->bmc, psta->mac_id); + for (i=0;iif_g[i], psta->mac_id); + for (i=0;i<2;i++) + rtw_macid_map_clr(&macid_ctl->ch_g[i], psta->mac_id); + macid_ctl->sta[psta->mac_id] = NULL; + } + + _exit_critical_bh(&macid_ctl->lock, &irqL); + + psta->mac_id = macid_ctl->num; +} + +//For 8188E RA +u8 rtw_search_max_mac_id(_adapter *padapter) +{ + u8 max_mac_id=0; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + int i; + _irqL irqL; + + /* TODO: Only search for connected macid? */ + + _enter_critical_bh(&macid_ctl->lock, &irqL); + for(i=(macid_ctl->num-1); i>0 ; i--) { + if (!rtw_macid_is_used(macid_ctl, i)) + break; + } + _exit_critical_bh(&macid_ctl->lock, &irqL); + max_mac_id = i; + + return max_mac_id; +} + +inline void rtw_macid_ctl_set_h2c_msr(struct macid_ctl_t *macid_ctl, u8 id, u8 h2c_msr) +{ + if (id >= macid_ctl->num) { + rtw_warn_on(1); + return; + } + + macid_ctl->h2c_msr[id] = h2c_msr; + if (0) + DBG_871X("macid:%u, h2c_msr:"H2C_MSR_FMT"\n", id, H2C_MSR_ARG(&macid_ctl->h2c_msr[id])); +} + +inline void rtw_macid_ctl_init(struct macid_ctl_t *macid_ctl) +{ + _rtw_spinlock_init(&macid_ctl->lock); +} + +inline void rtw_macid_ctl_deinit(struct macid_ctl_t *macid_ctl) +{ + _rtw_spinlock_free(&macid_ctl->lock); +} + +#if 0 +unsigned int setup_beacon_frame(_adapter *padapter, unsigned char *beacon_frame) +{ + unsigned short ATIMWindow; + unsigned char *pframe; + struct tx_desc *ptxdesc; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + unsigned int rate_len, len = 0; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + + _rtw_memset(beacon_frame, 0, 256); + + pframe = beacon_frame + TXDESC_SIZE; + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN); + + SetFrameSubType(pframe, WIFI_BEACON); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + len = sizeof(struct rtw_ieee80211_hdr_3addr); + + //timestamp will be inserted by hardware + pframe += 8; + len += 8; + + // beacon interval: 2 bytes + _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2); + + pframe += 2; + len += 2; + + // capability info: 2 bytes + _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); + + pframe += 2; + len += 2; + + // SSID + pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &len); + + // supported rates... + rate_len = rtw_get_rateset_len(cur_network->SupportedRates); + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8)? 8: rate_len), cur_network->SupportedRates, &len); + + // DS parameter set + pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &len); + + // IBSS Parameter Set... + //ATIMWindow = cur->Configuration.ATIMWindow; + ATIMWindow = 0; + pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &len); + + //todo: ERP IE + + // EXTERNDED SUPPORTED RATE + if (rate_len > 8) + { + pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &len); + } + + if ((len + TXDESC_SIZE) > 256) + { + //DBG_871X("marc: beacon frame too large\n"); + return 0; + } + + //fill the tx descriptor + ptxdesc = (struct tx_desc *)beacon_frame; + + //offset 0 + ptxdesc->txdw0 |= cpu_to_le32(len & 0x0000ffff); + ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00ff0000); //default = 32 bytes for TX Desc + + //offset 4 + ptxdesc->txdw1 |= cpu_to_le32((0x10 << QSEL_SHT) & 0x00001f00); + + //offset 8 + ptxdesc->txdw2 |= cpu_to_le32(BMC); + ptxdesc->txdw2 |= cpu_to_le32(BK); + + //offset 16 + ptxdesc->txdw4 = 0x80000000; + + //offset 20 + ptxdesc->txdw5 = 0x00000000; //1M + + return (len + TXDESC_SIZE); +} +#endif + +_adapter *dvobj_get_port0_adapter(struct dvobj_priv *dvobj) +{ + _adapter *port0_iface = NULL; + int i; + for (i=0;iiface_nums;i++) { + if (get_iface_type(dvobj->padapters[i]) == IFACE_PORT0) + break; + } + + if (i<0 || i>=dvobj->iface_nums) + rtw_warn_on(1); + else + port0_iface = dvobj->padapters[i]; + + return port0_iface; +} + +#ifdef CONFIG_PNO_SUPPORT +#define CSCAN_TLV_TYPE_SSID_IE 'S' +#define CIPHER_IE "key_mgmt=" +#define CIPHER_NONE "NONE" +#define CIPHER_WPA_PSK "WPA-PSK" +#define CIPHER_WPA_EAP "WPA-EAP IEEE8021X" +/* + * SSIDs list parsing from cscan tlv list + */ +int rtw_parse_ssid_list_tlv(char** list_str, pno_ssid_t* ssid, + int max, int *bytes_left) { + char* str; + + int idx = 0; + + if ((list_str == NULL) || (*list_str == NULL) || (*bytes_left < 0)) { + DBG_871X("%s error paramters\n", __func__); + return -1; + } + + str = *list_str; + while (*bytes_left > 0) { + + if (str[0] != CSCAN_TLV_TYPE_SSID_IE) { + *list_str = str; + DBG_871X("nssid=%d left_parse=%d %d\n", idx, *bytes_left, str[0]); + return idx; + } + + /* Get proper CSCAN_TLV_TYPE_SSID_IE */ + *bytes_left -= 1; + str += 1; + + if (str[0] == 0) { + /* Broadcast SSID */ + ssid[idx].SSID_len = 0; + memset((char*)ssid[idx].SSID, 0x0, WLAN_SSID_MAXLEN); + *bytes_left -= 1; + str += 1; + + DBG_871X("BROADCAST SCAN left=%d\n", *bytes_left); + } + else if (str[0] <= WLAN_SSID_MAXLEN) { + /* Get proper SSID size */ + ssid[idx].SSID_len = str[0]; + *bytes_left -= 1; + str += 1; + + /* Get SSID */ + if (ssid[idx].SSID_len > *bytes_left) { + DBG_871X("%s out of memory range len=%d but left=%d\n", + __func__, ssid[idx].SSID_len, *bytes_left); + return -1; + } + + memcpy((char*)ssid[idx].SSID, str, ssid[idx].SSID_len); + + *bytes_left -= ssid[idx].SSID_len; + str += ssid[idx].SSID_len; + + DBG_871X("%s :size=%d left=%d\n", + (char*)ssid[idx].SSID, ssid[idx].SSID_len, *bytes_left); + } + else { + DBG_871X("### SSID size more that %d\n", str[0]); + return -1; + } + + if (idx++ > max) { + DBG_871X("%s number of SSIDs more that %d\n", __func__, idx); + return -1; + } + } + + *list_str = str; + return idx; +} + +int rtw_parse_cipher_list(struct pno_nlo_info *nlo_info, char* list_str) { + + char *pch, *pnext, *pend; + u8 key_len = 0, index = 0; + + pch = list_str; + + if (nlo_info == NULL || list_str == NULL) { + DBG_871X("%s error paramters\n", __func__); + return -1; + } + + while (strlen(pch) != 0) { + pnext = strstr(pch, "key_mgmt="); + if (pnext != NULL) { + pch = pnext + strlen(CIPHER_IE); + pend = strstr(pch, "}"); + if (strncmp(pch, CIPHER_NONE, + strlen(CIPHER_NONE)) == 0) { + nlo_info->ssid_cipher_info[index] = 0x00; + } else if (strncmp(pch, CIPHER_WPA_PSK, + strlen(CIPHER_WPA_PSK)) == 0) { + nlo_info->ssid_cipher_info[index] = 0x66; + } else if (strncmp(pch, CIPHER_WPA_EAP, + strlen(CIPHER_WPA_EAP)) == 0) { + nlo_info->ssid_cipher_info[index] = 0x01; + } + index ++; + pch = pend + 1; + } else { + break; + } + } + return 0; +} + +int rtw_dev_nlo_info_set(struct pno_nlo_info *nlo_info, pno_ssid_t* ssid, + int num, int pno_time, int pno_repeat, int pno_freq_expo_max) { + + int i = 0; + struct file *fp; +#ifdef set_fs + mm_segment_t fs; +#endif + loff_t pos = 0; + u8 *source = NULL; + long len = 0; + + DBG_871X("+%s+\n", __func__); + + nlo_info->fast_scan_period = pno_time; + nlo_info->ssid_num = num & BIT_LEN_MASK_32(8); + nlo_info->hidden_ssid_num = num & BIT_LEN_MASK_32(8); + nlo_info->slow_scan_period = (pno_time * 2); + nlo_info->fast_scan_iterations = 5; + + if (nlo_info->hidden_ssid_num > 8) + nlo_info->hidden_ssid_num = 8; + + //TODO: channel list and probe index is all empty. + for (i = 0 ; i < num ; i++) { + nlo_info->ssid_length[i] + = ssid[i].SSID_len; + } + + /* cipher array */ + fp = filp_open("/data/misc/wifi/wpa_supplicant.conf", O_RDONLY, 0644); + if (IS_ERR(fp)) { + DBG_871X("Error, wpa_supplicant.conf doesn't exist.\n"); + DBG_871X("Error, cipher array using default value.\n"); + return 0; + } + + len = i_size_read(fp->f_path.dentry->d_inode); + if (len < 0 || len > 2048) { + DBG_871X("Error, file size is bigger than 2048.\n"); + DBG_871X("Error, cipher array using default value.\n"); + return 0; + } + +#ifdef set_fs + fs = get_fs(); + set_fs(KERNEL_DS); +#endif + + source = rtw_zmalloc(2048); + + if (source != NULL) { + len = vfs_read(fp, source, len, &pos); + rtw_parse_cipher_list(nlo_info, source); + rtw_mfree(source, 2048); + } + +#ifdef set_fs + set_fs(fs); +#endif + filp_close(fp, NULL); + + DBG_871X("-%s-\n", __func__); + return 0; +} + +int rtw_dev_ssid_list_set(struct pno_ssid_list *pno_ssid_list, + pno_ssid_t* ssid, u8 num) { + + int i = 0; + if(num > MAX_PNO_LIST_COUNT) + num = MAX_PNO_LIST_COUNT; + + for (i = 0 ; i < num ; i++) { + _rtw_memcpy(&pno_ssid_list->node[i].SSID, + ssid[i].SSID, ssid[i].SSID_len); + pno_ssid_list->node[i].SSID_len = ssid[i].SSID_len; + } + return 0; +} + +int rtw_dev_scan_info_set(_adapter *padapter, pno_ssid_t* ssid, + unsigned char ch, unsigned char ch_offset, unsigned short bw_mode) { + + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); + struct pno_scan_info *scan_info = pwrctl->pscan_info; + int i; + + scan_info->channel_num = MAX_SCAN_LIST_COUNT; + scan_info->orig_ch = ch; + scan_info->orig_bw = bw_mode; + scan_info->orig_40_offset = ch_offset; + + for(i = 0 ; i < scan_info->channel_num ; i++) { + if (i < 11) + scan_info->ssid_channel_info[i].active = 1; + else + scan_info->ssid_channel_info[i].active = 0; + + scan_info->ssid_channel_info[i].timeout = 100; + + scan_info->ssid_channel_info[i].tx_power = + PHY_GetTxPowerIndex(padapter, 0, 0x02, bw_mode, i+1); + + scan_info->ssid_channel_info[i].channel = i+1; + } + + DBG_871X("%s, channel_num: %d, orig_ch: %d, orig_bw: %d orig_40_offset: %d\n", + __func__, scan_info->channel_num, scan_info->orig_ch, + scan_info->orig_bw, scan_info->orig_40_offset); + return 0; +} + +int rtw_dev_pno_set(struct net_device *net, pno_ssid_t* ssid, int num, + int pno_time, int pno_repeat, int pno_freq_expo_max) { + + _adapter *padapter = (_adapter *)rtw_netdev_priv(net); + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + int ret = -1; + + if (num == 0) { + DBG_871X("%s, nssid is zero, no need to setup pno ssid list\n", __func__); + return 0; + } + + if (pwrctl == NULL) { + DBG_871X("%s, ERROR: pwrctl is NULL\n", __func__); + return -1; + } else { + pwrctl->pnlo_info = + (pno_nlo_info_t*)rtw_zmalloc(sizeof(pno_nlo_info_t)); + pwrctl->pno_ssid_list = + (pno_ssid_list_t*)rtw_zmalloc(sizeof(pno_ssid_list_t)); + pwrctl->pscan_info = + (pno_scan_info_t*)rtw_zmalloc(sizeof(pno_scan_info_t)); + } + + if (pwrctl->pnlo_info == NULL || + pwrctl->pscan_info == NULL || + pwrctl->pno_ssid_list == NULL){ + DBG_871X("%s, ERROR: alloc nlo_info, ssid_list, scan_info fail\n", __func__); + goto failing; + } + + pwrctl->pno_in_resume = _FALSE; + + pwrctl->pno_inited = _TRUE; + /* NLO Info */ + ret = rtw_dev_nlo_info_set(pwrctl->pnlo_info, ssid, num, + pno_time, pno_repeat, pno_freq_expo_max); + + /* SSID Info */ + ret = rtw_dev_ssid_list_set(pwrctl->pno_ssid_list, ssid, num); + + /* SCAN Info */ + ret = rtw_dev_scan_info_set(padapter, ssid, pmlmeext->cur_channel, + pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); + + DBG_871X("+%s num: %d, pno_time: %d, pno_repeat:%d, pno_freq_expo_max:%d+\n", + __func__, num, pno_time, pno_repeat, pno_freq_expo_max); + + return 0; + +failing: + if (pwrctl->pnlo_info) { + rtw_mfree((u8 *)pwrctl->pnlo_info, sizeof(pno_nlo_info_t)); + pwrctl->pnlo_info = NULL; + } + if (pwrctl->pno_ssid_list) { + rtw_mfree((u8 *)pwrctl->pno_ssid_list, sizeof(pno_ssid_list_t)); + pwrctl->pno_ssid_list = NULL; + } + if (pwrctl->pscan_info) { + rtw_mfree((u8 *)pwrctl->pscan_info, sizeof(pno_scan_info_t)); + pwrctl->pscan_info = NULL; + } + + return -1; +} + +#ifdef CONFIG_PNO_SET_DEBUG +void rtw_dev_pno_debug(struct net_device *net) { + _adapter *padapter = (_adapter *)rtw_netdev_priv(net); + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); + int i = 0, j = 0; + + DBG_871X("*******NLO_INFO********\n"); + DBG_871X("ssid_num: %d\n", pwrctl->pnlo_info->ssid_num); + DBG_871X("fast_scan_iterations: %d\n", + pwrctl->pnlo_info->fast_scan_iterations); + DBG_871X("fast_scan_period: %d\n", pwrctl->pnlo_info->fast_scan_period); + DBG_871X("slow_scan_period: %d\n", pwrctl->pnlo_info->slow_scan_period); + DBG_871X("ssid_length: "); + for (i = 0 ; i < MAX_PNO_LIST_COUNT ; i++) { + printk("%d, ", pwrctl->pnlo_info->ssid_length[i]); + } + DBG_871X("\n"); + + DBG_871X("cipher_info: "); + for (i = 0 ; i < MAX_PNO_LIST_COUNT ; i++) { + DBG_871X("%d, ", pwrctl->pnlo_info->ssid_cipher_info[i]); + } + DBG_871X("\n"); + + DBG_871X("channel_info: "); + for (i = 0 ; i < MAX_PNO_LIST_COUNT ; i++) { + DBG_871X("%d, ", pwrctl->pnlo_info->ssid_channel_info[i]); + } + DBG_871X("\n"); + + DBG_871X("******SSID_LISD******\n"); + for (i = 0 ; i < MAX_PNO_LIST_COUNT ; i++) { + DBG_871X("[%d]SSID: %s \n", i, + pwrctl->pno_ssid_list->node[i].SSID); + } + + DBG_871X("******SCAN_INFO******\n"); + DBG_871X("ch_num: %d\n", pwrctl->pscan_info->channel_num); + DBG_871X("orig_ch: %d\n", pwrctl->pscan_info->orig_ch); + DBG_871X("orig bw: %d\n", pwrctl->pscan_info->orig_bw); + DBG_871X("orig 40 offset: %d\n", pwrctl->pscan_info->orig_40_offset); + for(i = 0 ; i < MAX_SCAN_LIST_COUNT ; i++) { + DBG_871X("[%02d] avtive:%d, timeout:%d, tx_power:%d, ch:%02d\n", + i, pwrctl->pscan_info->ssid_channel_info[i].active, + pwrctl->pscan_info->ssid_channel_info[i].timeout, + pwrctl->pscan_info->ssid_channel_info[i].tx_power, + pwrctl->pscan_info->ssid_channel_info[i].channel); + } + DBG_871X("*****************\n"); +} +#endif //CONFIG_PNO_SET_DEBUG +#endif //CONFIG_PNO_SUPPORT diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_xmit.c b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_xmit.c new file mode 100644 index 000000000..c7f7f797d --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/core/rtw_xmit.c @@ -0,0 +1,5066 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTW_XMIT_C_ + +#include + +#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) +#error "Shall be Linux or Windows, but not both!\n" +#endif + + +static u8 P802_1H_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0xf8 }; +static u8 RFC1042_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0x00 }; + +static void _init_txservq(struct tx_servq *ptxservq) +{ +_func_enter_; + _rtw_init_listhead(&ptxservq->tx_pending); + _rtw_init_queue(&ptxservq->sta_pending); + ptxservq->qcnt = 0; +_func_exit_; +} + + +void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv) +{ + +_func_enter_; + + _rtw_memset((unsigned char *)psta_xmitpriv, 0, sizeof (struct sta_xmit_priv)); + + _rtw_spinlock_init(&psta_xmitpriv->lock); + + //for(i = 0 ; i < MAX_NUMBLKS; i++) + // _init_txservq(&(psta_xmitpriv->blk_q[i])); + + _init_txservq(&psta_xmitpriv->be_q); + _init_txservq(&psta_xmitpriv->bk_q); + _init_txservq(&psta_xmitpriv->vi_q); + _init_txservq(&psta_xmitpriv->vo_q); + _rtw_init_listhead(&psta_xmitpriv->legacy_dz); + _rtw_init_listhead(&psta_xmitpriv->apsd); + +_func_exit_; + +} + +s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) +{ + int i; + struct xmit_buf *pxmitbuf; + struct xmit_frame *pxframe; + sint res=_SUCCESS; + +_func_enter_; + + // We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). + //_rtw_memset((unsigned char *)pxmitpriv, 0, sizeof(struct xmit_priv)); + + _rtw_spinlock_init(&pxmitpriv->lock); + _rtw_spinlock_init(&pxmitpriv->lock_sctx); + _rtw_init_sema(&pxmitpriv->xmit_sema, 0); + _rtw_init_sema(&pxmitpriv->terminate_xmitthread_sema, 0); + + /* + Please insert all the queue initializaiton using _rtw_init_queue below + */ + + pxmitpriv->adapter = padapter; + + //for(i = 0 ; i < MAX_NUMBLKS; i++) + // _rtw_init_queue(&pxmitpriv->blk_strms[i]); + + _rtw_init_queue(&pxmitpriv->be_pending); + _rtw_init_queue(&pxmitpriv->bk_pending); + _rtw_init_queue(&pxmitpriv->vi_pending); + _rtw_init_queue(&pxmitpriv->vo_pending); + _rtw_init_queue(&pxmitpriv->bm_pending); + + //_rtw_init_queue(&pxmitpriv->legacy_dz_queue); + //_rtw_init_queue(&pxmitpriv->apsd_queue); + + _rtw_init_queue(&pxmitpriv->free_xmit_queue); + + /* + Please allocate memory with the sz = (struct xmit_frame) * NR_XMITFRAME, + and initialize free_xmit_frame below. + Please also apply free_txobj to link_up all the xmit_frames... + */ + + pxmitpriv->pallocated_frame_buf = rtw_zvmalloc(NR_XMITFRAME * sizeof(struct xmit_frame) + 4); + + if (pxmitpriv->pallocated_frame_buf == NULL){ + pxmitpriv->pxmit_frame_buf =NULL; + RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("alloc xmit_frame fail!\n")); + res= _FAIL; + goto exit; + } + pxmitpriv->pxmit_frame_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_frame_buf), 4); + //pxmitpriv->pxmit_frame_buf = pxmitpriv->pallocated_frame_buf + 4 - + // ((SIZE_PTR) (pxmitpriv->pallocated_frame_buf) &3); + + pxframe = (struct xmit_frame*) pxmitpriv->pxmit_frame_buf; + + for (i = 0; i < NR_XMITFRAME; i++) + { + _rtw_init_listhead(&(pxframe->list)); + + pxframe->padapter = padapter; + pxframe->frame_tag = NULL_FRAMETAG; + + pxframe->pkt = NULL; + + pxframe->buf_addr = NULL; + pxframe->pxmitbuf = NULL; + + rtw_list_insert_tail(&(pxframe->list), &(pxmitpriv->free_xmit_queue.queue)); + + pxframe++; + } + + pxmitpriv->free_xmitframe_cnt = NR_XMITFRAME; + + pxmitpriv->frag_len = MAX_FRAG_THRESHOLD; + + + //init xmit_buf + _rtw_init_queue(&pxmitpriv->free_xmitbuf_queue); + _rtw_init_queue(&pxmitpriv->pending_xmitbuf_queue); + + pxmitpriv->pallocated_xmitbuf = rtw_zvmalloc(NR_XMITBUFF * sizeof(struct xmit_buf) + 4); + + if (pxmitpriv->pallocated_xmitbuf == NULL){ + RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("alloc xmit_buf fail!\n")); + res= _FAIL; + goto exit; + } + + pxmitpriv->pxmitbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmitbuf), 4); + //pxmitpriv->pxmitbuf = pxmitpriv->pallocated_xmitbuf + 4 - + // ((SIZE_PTR) (pxmitpriv->pallocated_xmitbuf) &3); + + pxmitbuf = (struct xmit_buf*)pxmitpriv->pxmitbuf; + + for (i = 0; i < NR_XMITBUFF; i++) + { + _rtw_init_listhead(&pxmitbuf->list); + + pxmitbuf->priv_data = NULL; + pxmitbuf->padapter = padapter; + pxmitbuf->buf_tag = XMITBUF_DATA; + + /* Tx buf allocation may fail sometimes, so sleep and retry. */ + if((res=rtw_os_xmit_resource_alloc(padapter, pxmitbuf,(MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ), _TRUE)) == _FAIL) { + rtw_msleep_os(10); + res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf,(MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ), _TRUE); + if (res == _FAIL) { + goto exit; + } + } + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + pxmitbuf->phead = pxmitbuf->pbuf; + pxmitbuf->pend = pxmitbuf->pbuf + MAX_XMITBUF_SZ; + pxmitbuf->len = 0; + pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead; +#endif + + pxmitbuf->flags = XMIT_VO_QUEUE; + + rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmitbuf_queue.queue)); + #ifdef DBG_XMIT_BUF + pxmitbuf->no=i; + #endif + + pxmitbuf++; + + } + + pxmitpriv->free_xmitbuf_cnt = NR_XMITBUFF; + + /* init xframe_ext queue, the same count as extbuf */ + _rtw_init_queue(&pxmitpriv->free_xframe_ext_queue); + + pxmitpriv->xframe_ext_alloc_addr = rtw_zvmalloc(NR_XMIT_EXTBUFF * sizeof(struct xmit_frame) + 4); + + if (pxmitpriv->xframe_ext_alloc_addr == NULL){ + pxmitpriv->xframe_ext = NULL; + RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("alloc xframe_ext fail!\n")); + res= _FAIL; + goto exit; + } + pxmitpriv->xframe_ext = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->xframe_ext_alloc_addr), 4); + pxframe = (struct xmit_frame*)pxmitpriv->xframe_ext; + + for (i = 0; i < NR_XMIT_EXTBUFF; i++) { + _rtw_init_listhead(&(pxframe->list)); + + pxframe->padapter = padapter; + pxframe->frame_tag = NULL_FRAMETAG; + + pxframe->pkt = NULL; + + pxframe->buf_addr = NULL; + pxframe->pxmitbuf = NULL; + + pxframe->ext_tag = 1; + + rtw_list_insert_tail(&(pxframe->list), &(pxmitpriv->free_xframe_ext_queue.queue)); + + pxframe++; + } + pxmitpriv->free_xframe_ext_cnt = NR_XMIT_EXTBUFF; + + // Init xmit extension buff + _rtw_init_queue(&pxmitpriv->free_xmit_extbuf_queue); + + pxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(NR_XMIT_EXTBUFF * sizeof(struct xmit_buf) + 4); + + if (pxmitpriv->pallocated_xmit_extbuf == NULL){ + RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("alloc xmit_extbuf fail!\n")); + res= _FAIL; + goto exit; + } + + pxmitpriv->pxmit_extbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmit_extbuf), 4); + + pxmitbuf = (struct xmit_buf*)pxmitpriv->pxmit_extbuf; + + for (i = 0; i < NR_XMIT_EXTBUFF; i++) + { + _rtw_init_listhead(&pxmitbuf->list); + + pxmitbuf->priv_data = NULL; + pxmitbuf->padapter = padapter; + pxmitbuf->buf_tag = XMITBUF_MGNT; + + if((res=rtw_os_xmit_resource_alloc(padapter, pxmitbuf,MAX_XMIT_EXTBUF_SZ + XMITBUF_ALIGN_SZ, _TRUE)) == _FAIL) { + res= _FAIL; + goto exit; + } + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + pxmitbuf->phead = pxmitbuf->pbuf; + pxmitbuf->pend = pxmitbuf->pbuf + MAX_XMIT_EXTBUF_SZ; + pxmitbuf->len = 0; + pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead; +#endif + + rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmit_extbuf_queue.queue)); + #ifdef DBG_XMIT_BUF_EXT + pxmitbuf->no=i; + #endif + pxmitbuf++; + + } + + pxmitpriv->free_xmit_extbuf_cnt = NR_XMIT_EXTBUFF; + + for (i = 0; ipcmd_xmitbuf[i]; + if (pxmitbuf) { + _rtw_init_listhead(&pxmitbuf->list); + + pxmitbuf->priv_data = NULL; + pxmitbuf->padapter = padapter; + pxmitbuf->buf_tag = XMITBUF_CMD; + + if((res=rtw_os_xmit_resource_alloc(padapter, pxmitbuf, MAX_CMDBUF_SZ+XMITBUF_ALIGN_SZ, _TRUE)) == _FAIL) { + res= _FAIL; + goto exit; + } + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + pxmitbuf->phead = pxmitbuf->pbuf; + pxmitbuf->pend = pxmitbuf->pbuf + MAX_CMDBUF_SZ; + pxmitbuf->len = 0; + pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead; +#endif + pxmitbuf->alloc_sz = MAX_CMDBUF_SZ+XMITBUF_ALIGN_SZ; + } + } + + rtw_alloc_hwxmits(padapter); + rtw_init_hwxmits(pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry); + + for (i = 0; i < 4; i ++) + { + pxmitpriv->wmm_para_seq[i] = i; + } + +#ifdef CONFIG_USB_HCI + pxmitpriv->txirp_cnt=1; + + _rtw_init_sema(&(pxmitpriv->tx_retevt), 0); + + //per AC pending irp + pxmitpriv->beq_cnt = 0; + pxmitpriv->bkq_cnt = 0; + pxmitpriv->viq_cnt = 0; + pxmitpriv->voq_cnt = 0; +#endif + + +#ifdef CONFIG_XMIT_ACK + pxmitpriv->ack_tx = _FALSE; + _rtw_mutex_init(&pxmitpriv->ack_tx_mutex); + rtw_sctx_init(&pxmitpriv->ack_tx_ops, 0); +#endif + + rtw_hal_init_xmit_priv(padapter); + +exit: + +_func_exit_; + + return res; +} + +void rtw_mfree_xmit_priv_lock (struct xmit_priv *pxmitpriv); +void rtw_mfree_xmit_priv_lock (struct xmit_priv *pxmitpriv) +{ + _rtw_spinlock_free(&pxmitpriv->lock); + _rtw_free_sema(&pxmitpriv->xmit_sema); + _rtw_free_sema(&pxmitpriv->terminate_xmitthread_sema); + + _rtw_spinlock_free(&pxmitpriv->be_pending.lock); + _rtw_spinlock_free(&pxmitpriv->bk_pending.lock); + _rtw_spinlock_free(&pxmitpriv->vi_pending.lock); + _rtw_spinlock_free(&pxmitpriv->vo_pending.lock); + _rtw_spinlock_free(&pxmitpriv->bm_pending.lock); + + //_rtw_spinlock_free(&pxmitpriv->legacy_dz_queue.lock); + //_rtw_spinlock_free(&pxmitpriv->apsd_queue.lock); + + _rtw_spinlock_free(&pxmitpriv->free_xmit_queue.lock); + _rtw_spinlock_free(&pxmitpriv->free_xmitbuf_queue.lock); + _rtw_spinlock_free(&pxmitpriv->pending_xmitbuf_queue.lock); +} + + +void _rtw_free_xmit_priv (struct xmit_priv *pxmitpriv) +{ + int i; + _adapter *padapter = pxmitpriv->adapter; + struct xmit_frame *pxmitframe = (struct xmit_frame*) pxmitpriv->pxmit_frame_buf; + struct xmit_buf *pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf; + + _func_enter_; + + rtw_hal_free_xmit_priv(padapter); + + rtw_mfree_xmit_priv_lock(pxmitpriv); + + if(pxmitpriv->pxmit_frame_buf==NULL) + goto out; + + for(i=0; ipallocated_frame_buf) { + rtw_vmfree(pxmitpriv->pallocated_frame_buf, NR_XMITFRAME * sizeof(struct xmit_frame) + 4); + } + + + if(pxmitpriv->pallocated_xmitbuf) { + rtw_vmfree(pxmitpriv->pallocated_xmitbuf, NR_XMITBUFF * sizeof(struct xmit_buf) + 4); + } + + /* free xframe_ext queue, the same count as extbuf */ + if ((pxmitframe = (struct xmit_frame*)pxmitpriv->xframe_ext)) { + for (i=0; ixframe_ext_alloc_addr) + rtw_vmfree(pxmitpriv->xframe_ext_alloc_addr, NR_XMIT_EXTBUFF * sizeof(struct xmit_frame) + 4); + _rtw_spinlock_free(&pxmitpriv->free_xframe_ext_queue.lock); + + // free xmit extension buff + _rtw_spinlock_free(&pxmitpriv->free_xmit_extbuf_queue.lock); + + pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf; + for(i=0; ipallocated_xmit_extbuf) { + rtw_vmfree(pxmitpriv->pallocated_xmit_extbuf, NR_XMIT_EXTBUFF * sizeof(struct xmit_buf) + 4); + } + + for (i=0; ipcmd_xmitbuf[i]; + if(pxmitbuf!=NULL) + rtw_os_xmit_resource_free(padapter, pxmitbuf, MAX_CMDBUF_SZ+XMITBUF_ALIGN_SZ , _TRUE); + } + + rtw_free_hwxmits(padapter); + +#ifdef CONFIG_XMIT_ACK + _rtw_mutex_free(&pxmitpriv->ack_tx_mutex); +#endif + +out: + +_func_exit_; + +} + +u8 query_ra_short_GI(struct sta_info *psta) +{ + u8 sgi = _FALSE, sgi_20m = _FALSE, sgi_40m = _FALSE, sgi_80m = _FALSE; + +#ifdef CONFIG_80211N_HT +#ifdef CONFIG_80211AC_VHT + if (psta->vhtpriv.vht_option) { + sgi_80m= psta->vhtpriv.sgi_80m; + } +#endif //CONFIG_80211AC_VHT + { + sgi_20m = psta->htpriv.sgi_20m; + sgi_40m = psta->htpriv.sgi_40m; + } +#endif + + switch(psta->bw_mode){ + case CHANNEL_WIDTH_80: + sgi = sgi_80m; + break; + case CHANNEL_WIDTH_40: + sgi = sgi_40m; + break; + case CHANNEL_WIDTH_20: + default: + sgi = sgi_20m; + break; + } + + return sgi; +} + +static void update_attrib_vcs_info(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + u32 sz; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + //struct sta_info *psta = pattrib->psta; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + +/* + if(pattrib->psta) + { + psta = pattrib->psta; + } + else + { + DBG_871X("%s, call rtw_get_stainfo()\n", __func__); + psta=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] ); + } + + if(psta==NULL) + { + DBG_871X("%s, psta==NUL\n", __func__); + return; + } + + if(!(psta->state &_FW_LINKED)) + { + DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state); + return; + } +*/ + + if (pattrib->nr_frags != 1) + { + sz = padapter->xmitpriv.frag_len; + } + else //no frag + { + sz = pattrib->last_txcmdsz; + } + + // (1) RTS_Threshold is compared to the MPDU, not MSDU. + // (2) If there are more than one frag in this MSDU, only the first frag uses protection frame. + // Other fragments are protected by previous fragment. + // So we only need to check the length of first fragment. + if(pmlmeext->cur_wireless_mode < WIRELESS_11_24N || padapter->registrypriv.wifi_spec) + { + if(sz > padapter->registrypriv.rts_thresh) + { + pattrib->vcs_mode = RTS_CTS; + } + else + { + if(pattrib->rtsen) + pattrib->vcs_mode = RTS_CTS; + else if(pattrib->cts2self) + pattrib->vcs_mode = CTS_TO_SELF; + else + pattrib->vcs_mode = NONE_VCS; + } + } + else + { + while (_TRUE) + { +#if 0 //Todo + //check IOT action + if(pHTInfo->IOTAction & HT_IOT_ACT_FORCED_CTS2SELF) + { + pattrib->vcs_mode = CTS_TO_SELF; + pattrib->rts_rate = MGN_24M; + break; + } + else if(pHTInfo->IOTAction & (HT_IOT_ACT_FORCED_RTS|HT_IOT_ACT_PURE_N_MODE)) + { + pattrib->vcs_mode = RTS_CTS; + pattrib->rts_rate = MGN_24M; + break; + } +#endif + + //IOT action + if((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS) && (pattrib->ampdu_en==_TRUE) && + (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_ )) + { + pattrib->vcs_mode = CTS_TO_SELF; + break; + } + + + //check ERP protection + if(pattrib->rtsen || pattrib->cts2self) + { + if(pattrib->rtsen) + pattrib->vcs_mode = RTS_CTS; + else if(pattrib->cts2self) + pattrib->vcs_mode = CTS_TO_SELF; + + break; + } + + //check HT op mode + if(pattrib->ht_en) + { + u8 HTOpMode = pmlmeinfo->HT_protection; + if((pmlmeext->cur_bwmode && (HTOpMode == 2 || HTOpMode == 3)) || + (!pmlmeext->cur_bwmode && HTOpMode == 3) ) + { + pattrib->vcs_mode = RTS_CTS; + break; + } + } + + //check rts + if(sz > padapter->registrypriv.rts_thresh) + { + pattrib->vcs_mode = RTS_CTS; + break; + } + + //to do list: check MIMO power save condition. + + //check AMPDU aggregation for TXOP + if((pattrib->ampdu_en==_TRUE) && (!IS_HARDWARE_TYPE_8812(padapter))) + { + pattrib->vcs_mode = RTS_CTS; + break; + } + + pattrib->vcs_mode = NONE_VCS; + break; + } + } + + //for debug : force driver control vrtl_carrier_sense. + if(padapter->driver_vcs_en==1) + { + //u8 driver_vcs_en; //Enable=1, Disable=0 driver control vrtl_carrier_sense. + //u8 driver_vcs_type;//force 0:disable VCS, 1:RTS-CTS, 2:CTS-to-self when vcs_en=1. + pattrib->vcs_mode = padapter->driver_vcs_type; + } + +} + +static void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta) +{ + struct mlme_ext_priv *mlmeext = &padapter->mlmeextpriv; + + pattrib->rtsen = psta->rtsen; + pattrib->cts2self = psta->cts2self; + + pattrib->mdata = 0; + pattrib->eosp = 0; + pattrib->triggered=0; + pattrib->ampdu_spacing = 0; + + //qos_en, ht_en, init rate, ,bw, ch_offset, sgi + pattrib->qos_en = psta->qos_option; + + pattrib->raid = psta->raid; + + if (mlmeext->cur_bwmode < psta->bw_mode) + pattrib->bwmode = mlmeext->cur_bwmode; + else + pattrib->bwmode = psta->bw_mode; + + pattrib->sgi = query_ra_short_GI(psta); + + pattrib->ldpc = psta->ldpc; + pattrib->stbc = psta->stbc; + +#ifdef CONFIG_80211N_HT + pattrib->ht_en = psta->htpriv.ht_option; + pattrib->ch_offset = psta->htpriv.ch_offset; + pattrib->ampdu_en = _FALSE; + + if(padapter->driver_ampdu_spacing != 0xFF) //driver control AMPDU Density for peer sta's rx + pattrib->ampdu_spacing = padapter->driver_ampdu_spacing; + else + pattrib->ampdu_spacing = psta->htpriv.rx_ampdu_min_spacing; +#endif //CONFIG_80211N_HT + //if(pattrib->ht_en && psta->htpriv.ampdu_enable) + //{ + // if(psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) + // pattrib->ampdu_en = _TRUE; + //} + +#ifdef CONFIG_TDLS + if (pattrib->direct_link==_TRUE) { + psta = pattrib->ptdls_sta; + + pattrib->raid = psta->raid; +#ifdef CONFIG_80211N_HT + pattrib->bwmode = psta->bw_mode; + pattrib->ht_en = psta->htpriv.ht_option; + pattrib->ch_offset = psta->htpriv.ch_offset; + pattrib->sgi= query_ra_short_GI(psta); +#endif /* CONFIG_80211N_HT */ + } +#endif /* CONFIG_TDLS */ + + pattrib->retry_ctrl = _FALSE; + +#ifdef CONFIG_AUTO_AP_MODE + if(psta->isrc && psta->pid>0) + pattrib->pctrl = _TRUE; +#endif + +} + +static s32 update_attrib_sec_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta) +{ + sint res = _SUCCESS; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + sint bmcast = IS_MCAST(pattrib->ra); + + _rtw_memset(pattrib->dot118021x_UncstKey.skey, 0, 16); + _rtw_memset(pattrib->dot11tkiptxmickey.skey, 0, 16); + pattrib->mac_id = psta->mac_id; + + if (psta->ieee8021x_blocked == _TRUE) + { + RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("\n psta->ieee8021x_blocked == _TRUE \n")); + + pattrib->encrypt = 0; + + if((pattrib->ether_type != 0x888e) && (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE)) + { + RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("\npsta->ieee8021x_blocked == _TRUE, pattrib->ether_type(%.4x) != 0x888e\n",pattrib->ether_type)); + #ifdef DBG_TX_DROP_FRAME + DBG_871X("DBG_TX_DROP_FRAME %s psta->ieee8021x_blocked == _TRUE, pattrib->ether_type(%04x) != 0x888e\n", __FUNCTION__,pattrib->ether_type); + #endif + res = _FAIL; + goto exit; + } + } + else + { + GET_ENCRY_ALGO(psecuritypriv, psta, pattrib->encrypt, bmcast); + +#ifdef CONFIG_WAPI_SUPPORT + if(pattrib->ether_type == 0x88B4) + pattrib->encrypt=_NO_PRIVACY_; +#endif + + switch(psecuritypriv->dot11AuthAlgrthm) + { + case dot11AuthAlgrthm_Open: + case dot11AuthAlgrthm_Shared: + case dot11AuthAlgrthm_Auto: + pattrib->key_idx = (u8)psecuritypriv->dot11PrivacyKeyIndex; + break; + case dot11AuthAlgrthm_8021X: + if(bmcast) + pattrib->key_idx = (u8)psecuritypriv->dot118021XGrpKeyid; + else + pattrib->key_idx = 0; + break; + default: + pattrib->key_idx = 0; + break; + } + + //For WPS 1.0 WEP, driver should not encrypt EAPOL Packet for WPS handshake. + if (((pattrib->encrypt ==_WEP40_)||(pattrib->encrypt ==_WEP104_)) && (pattrib->ether_type == 0x888e)) + pattrib->encrypt=_NO_PRIVACY_; + + } + +#ifdef CONFIG_TDLS + if (pattrib->direct_link == _TRUE) { + if (pattrib->encrypt > 0) + pattrib->encrypt = _AES_; + } +#endif + + switch (pattrib->encrypt) + { + case _WEP40_: + case _WEP104_: + pattrib->iv_len = 4; + pattrib->icv_len = 4; + WEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); + break; + + case _TKIP_: + pattrib->iv_len = 8; + pattrib->icv_len = 4; + + if(psecuritypriv->busetkipkey==_FAIL) + { + #ifdef DBG_TX_DROP_FRAME + DBG_871X("DBG_TX_DROP_FRAME %s psecuritypriv->busetkipkey(%d)==_FAIL drop packet\n", __FUNCTION__, psecuritypriv->busetkipkey); + #endif + res =_FAIL; + goto exit; + } + + if(bmcast) + TKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); + else + TKIP_IV(pattrib->iv, psta->dot11txpn, 0); + + + _rtw_memcpy(pattrib->dot11tkiptxmickey.skey, psta->dot11tkiptxmickey.skey, 16); + + break; + + case _AES_: + + pattrib->iv_len = 8; + pattrib->icv_len = 8; + + if(bmcast) + AES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); + else + AES_IV(pattrib->iv, psta->dot11txpn, 0); + + break; + +#ifdef CONFIG_WAPI_SUPPORT + case _SMS4_: + pattrib->iv_len = 18; + pattrib->icv_len = 16; + rtw_wapi_get_iv(padapter,pattrib->ra,pattrib->iv); + break; +#endif + default: + pattrib->iv_len = 0; + pattrib->icv_len = 0; + break; + } + + if(pattrib->encrypt>0) + _rtw_memcpy(pattrib->dot118021x_UncstKey.skey, psta->dot118021x_UncstKey.skey, 16); + + RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, + ("update_attrib: encrypt=%d securitypriv.sw_encrypt=%d\n", + pattrib->encrypt, padapter->securitypriv.sw_encrypt)); + + if (pattrib->encrypt && + ((padapter->securitypriv.sw_encrypt == _TRUE) || (psecuritypriv->hw_decrypted == _FALSE))) + { + pattrib->bswenc = _TRUE; + RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_, + ("update_attrib: encrypt=%d securitypriv.hw_decrypted=%d bswenc=_TRUE\n", + pattrib->encrypt, padapter->securitypriv.sw_encrypt)); + } else { + pattrib->bswenc = _FALSE; + RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("update_attrib: bswenc=_FALSE\n")); + } + +#if defined(CONFIG_CONCURRENT_MODE) && !defined(DYNAMIC_CAMID_ALLOC) + if((pattrib->encrypt && bmcast) || (pattrib->encrypt ==_WEP40_) || (pattrib->encrypt ==_WEP104_)) + { + pattrib->bswenc = _TRUE;//force using sw enc. + } +#endif +#ifdef DYNAMIC_CAMID_ALLOC + if (pattrib->encrypt && bmcast && _rtw_camctl_chk_flags(padapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH)) + pattrib->bswenc = _TRUE; +#endif + +#ifdef CONFIG_WAPI_SUPPORT + if(pattrib->encrypt == _SMS4_) + pattrib->bswenc = _FALSE; +#endif + +exit: + + return res; + +} + +u8 qos_acm(u8 acm_mask, u8 priority) +{ + u8 change_priority = priority; + + switch (priority) + { + case 0: + case 3: + if(acm_mask & BIT(1)) + change_priority = 1; + break; + case 1: + case 2: + break; + case 4: + case 5: + if(acm_mask & BIT(2)) + change_priority = 0; + break; + case 6: + case 7: + if(acm_mask & BIT(3)) + change_priority = 5; + break; + default: + DBG_871X("qos_acm(): invalid pattrib->priority: %d!!!\n", priority); + break; + } + + return change_priority; +} + +static void set_qos(struct pkt_file *ppktfile, struct pkt_attrib *pattrib) +{ + struct ethhdr etherhdr; + struct iphdr ip_hdr; + s32 UserPriority = 0; + + + _rtw_open_pktfile(ppktfile->pkt, ppktfile); + _rtw_pktfile_read(ppktfile, (unsigned char*)ðerhdr, ETH_HLEN); + + // get UserPriority from IP hdr + if (pattrib->ether_type == 0x0800) { + _rtw_pktfile_read(ppktfile, (u8*)&ip_hdr, sizeof(ip_hdr)); +// UserPriority = (ntohs(ip_hdr.tos) >> 5) & 0x3; + UserPriority = ip_hdr.tos >> 5; + } +/* + else if (pattrib->ether_type == 0x888e) { + // "When priority processing of data frames is supported, + // a STA's SME should send EAPOL-Key frames at the highest priority." + UserPriority = 7; + } +*/ + pattrib->priority = UserPriority; + pattrib->hdrlen = WLAN_HDR_A3_QOS_LEN; + pattrib->subtype = WIFI_QOS_DATA_TYPE; +} + +#ifdef CONFIG_TDLS +u8 rtw_check_tdls_established(_adapter *padapter, struct pkt_attrib *pattrib) +{ + pattrib->ptdls_sta = NULL; + + pattrib->direct_link = _FALSE; + if (padapter->tdlsinfo.link_established == _TRUE) { + pattrib->ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pattrib->dst); +#if 1 + if((pattrib->ptdls_sta!=NULL)&& + (pattrib->ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)&& + (pattrib->ether_type!=0x0806)){ + pattrib->direct_link = _TRUE; + //DBG_871X("send ptk to "MAC_FMT" using direct link\n", MAC_ARG(pattrib->dst)); + } +#else + if (pattrib->ptdls_sta != NULL && + pattrib->ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) { + pattrib->direct_link = _TRUE; + #if 0 + DBG_871X("send ptk to "MAC_FMT" using direct link\n", MAC_ARG(pattrib->dst)); + #endif + } + + /* ARP frame may be helped by AP*/ + if (pattrib->ether_type != 0x0806) { + pattrib->direct_link = _FALSE; + } +#endif + } + + return pattrib->direct_link; +} + +s32 update_tdls_attrib(_adapter *padapter, struct pkt_attrib *pattrib) +{ + + struct sta_info *psta = NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct qos_priv *pqospriv= &pmlmepriv->qospriv; + + s32 res=_SUCCESS; + + psta = rtw_get_stainfo(pstapriv, pattrib->ra); + if (psta == NULL) { + res =_FAIL; + goto exit; + } + + pattrib->mac_id = psta->mac_id; + pattrib->psta = psta; + pattrib->ack_policy = 0; + // get ether_hdr_len + pattrib->pkt_hdrlen = ETH_HLEN; + + // [TDLS] TODO: setup req/rsp should be AC_BK + if (pqospriv->qos_option && psta->qos_option) { + pattrib->priority = 4; //tdls management frame should be AC_VI + pattrib->hdrlen = WLAN_HDR_A3_QOS_LEN; + pattrib->subtype = WIFI_QOS_DATA_TYPE; + } else { + pattrib->priority = 0; + pattrib->hdrlen = WLAN_HDR_A3_LEN; + pattrib->subtype = WIFI_DATA_TYPE; + } + + //TODO:_lock + if(update_attrib_sec_info(padapter, pattrib, psta) == _FAIL) + { + res = _FAIL; + goto exit; + } + + update_attrib_phy_info(padapter, pattrib, psta); + + +exit: + + return res; +} + +#endif //CONFIG_TDLS + +//get non-qos hw_ssn control register,mapping to REG_HW_SEQ0,1,2,3 +inline u8 rtw_get_hwseq_no(_adapter *padapter) +{ + u8 hwseq_num = 0; +#ifdef CONFIG_CONCURRENT_MODE + if(padapter->adapter_type == SECONDARY_ADAPTER) + hwseq_num = 1; + //else + // hwseq_num = 2; +#endif //CONFIG_CONCURRENT_MODE + return hwseq_num; +} +static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattrib) +{ + uint i; + struct pkt_file pktfile; + struct sta_info *psta = NULL; + struct ethhdr etherhdr; + + sint bmcast; + struct sta_priv *pstapriv = &padapter->stapriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct qos_priv *pqospriv= &pmlmepriv->qospriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + sint res = _SUCCESS; + + _func_enter_; + + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib); + + _rtw_open_pktfile(pkt, &pktfile); + i = _rtw_pktfile_read(&pktfile, (u8*)ðerhdr, ETH_HLEN); + + pattrib->ether_type = ntohs(etherhdr.h_proto); + + + _rtw_memcpy(pattrib->dst, ðerhdr.h_dest, ETH_ALEN); + _rtw_memcpy(pattrib->src, ðerhdr.h_source, ETH_ALEN); + + + if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { + _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); + _rtw_memcpy(pattrib->ta, adapter_mac_addr(padapter), ETH_ALEN); + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_adhoc); + } + else if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { +#ifdef CONFIG_TDLS + if (rtw_check_tdls_established(padapter, pattrib) == _TRUE) + _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); /* For TDLS direct link Tx, set ra to be same to dst */ + else +#endif + _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pattrib->ta, adapter_mac_addr(padapter), ETH_ALEN); + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_sta); + } + else if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); + _rtw_memcpy(pattrib->ta, get_bssid(pmlmepriv), ETH_ALEN); + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_ap); + } + else + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_unknown); + + bmcast = IS_MCAST(pattrib->ra); + if (bmcast) { + psta = rtw_get_bcmc_stainfo(padapter); + if (psta == NULL) { /* if we cannot get psta => drop the pkt */ + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_sta); + RT_TRACE(_module_rtl871x_xmit_c_, _drv_alert_, ("\nupdate_attrib => get sta_info fail, ra:" MAC_FMT "\n", MAC_ARG(pattrib->ra))); + #ifdef DBG_TX_DROP_FRAME + DBG_871X("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __func__, MAC_ARG(pattrib->ra)); + #endif + res = _FAIL; + goto exit; + } + } else { + psta = rtw_get_stainfo(pstapriv, pattrib->ra); + if (psta == NULL) { /* if we cannot get psta => drop the pkt */ + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_ucast_sta); + RT_TRACE(_module_rtl871x_xmit_c_, _drv_alert_, ("\nupdate_attrib => get sta_info fail, ra:" MAC_FMT"\n", MAC_ARG(pattrib->ra))); + #ifdef DBG_TX_DROP_FRAME + DBG_871X("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __func__, MAC_ARG(pattrib->ra)); + #endif + res = _FAIL; + goto exit; + } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE && !(psta->state & _FW_LINKED)) { + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_ucast_ap_link); + res = _FAIL; + goto exit; + } + } + + if (!(psta->state & _FW_LINKED)) { + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_link); + DBG_871X("%s, psta("MAC_FMT")->state(0x%x) != _FW_LINKED\n", __func__, MAC_ARG(psta->hwaddr), psta->state); + res = _FAIL; + goto exit; + } + + pattrib->pktlen = pktfile.pkt_len; + + /* TODO: 802.1Q VLAN header */ + /* TODO: IPV6 */ + + if (ETH_P_IP == pattrib->ether_type) { + u8 ip[20]; + + _rtw_pktfile_read(&pktfile, ip, 20); + + if (GET_IPV4_IHL(ip) * 4 > 20) + _rtw_pktfile_read(&pktfile, NULL, GET_IPV4_IHL(ip) - 20); + + pattrib->icmp_pkt = 0; + pattrib->dhcp_pkt = 0; + + if (GET_IPV4_PROTOCOL(ip) == 0x01) { /* ICMP */ + pattrib->icmp_pkt = 1; + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_icmp); + + } else if (GET_IPV4_PROTOCOL(ip) == 0x11) { /* UDP */ + u8 udp[8]; + + _rtw_pktfile_read(&pktfile, udp, 8); + + if ((GET_UDP_SRC(udp) == 68 && GET_UDP_DST(udp) == 67) + || (GET_UDP_SRC(udp) == 67 && GET_UDP_DST(udp) == 68) + ) { + /* 67 : UDP BOOTP server, 68 : UDP BOOTP client */ + if (pattrib->pktlen > 282) { /* MINIMUM_DHCP_PACKET_SIZE */ + pattrib->dhcp_pkt = 1; + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_dhcp); + if (0) + DBG_871X("send DHCP packet\n"); + } + } + + } else if (GET_IPV4_PROTOCOL(ip) == 0x06 /* TCP */ + && rtw_st_ctl_chk_reg_s_proto(&psta->st_ctl, 0x06) == _TRUE + ) { + u8 tcp[20]; + + _rtw_pktfile_read(&pktfile, tcp, 20); + + if (rtw_st_ctl_chk_reg_rule(&psta->st_ctl, padapter, IPV4_SRC(ip), TCP_SRC(tcp), IPV4_DST(ip), TCP_DST(tcp)) == _TRUE) { + if (GET_TCP_SYN(tcp) && GET_TCP_ACK(tcp)) { + session_tracker_add_cmd(padapter, psta + , IPV4_SRC(ip), TCP_SRC(tcp) + , IPV4_SRC(ip), TCP_DST(tcp)); + if (DBG_SESSION_TRACKER) + DBG_871X(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" SYN-ACK\n" + , FUNC_ADPT_ARG(padapter) + , IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp)) + , IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp))); + } + if (GET_TCP_FIN(tcp)) { + session_tracker_del_cmd(padapter, psta + , IPV4_SRC(ip), TCP_SRC(tcp) + , IPV4_SRC(ip), TCP_DST(tcp)); + if (DBG_SESSION_TRACKER) + DBG_871X(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" FIN\n" + , FUNC_ADPT_ARG(padapter) + , IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp)) + , IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp))); + } + } + } + + } else if (0x888e == pattrib->ether_type) { + DBG_871X_LEVEL(_drv_always_, "send eapol packet\n"); + } + + if ((pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1)) + rtw_set_scan_deny(padapter, 3000); + +#ifdef CONFIG_LPS + // If EAPOL , ARP , OR DHCP packet, driver must be in active mode. +#ifdef CONFIG_WAPI_SUPPORT + if ( (pattrib->ether_type == 0x88B4) || (pattrib->ether_type == 0x0806) || (pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1) ) +#else //!CONFIG_WAPI_SUPPORT +#if 0 + if ( (pattrib->ether_type == 0x0806) || (pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1) ) +#else // only ICMP/DHCP packets is as SPECIAL_PACKET, and leave LPS when tx IMCP/DHCP packets. + //if ((pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1) ) + if (pattrib->icmp_pkt==1) + { + rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 1); + } + else if(pattrib->dhcp_pkt==1) +#endif +#endif + { + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_active); + rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_SPECIAL_PACKET, 1); + } +#endif //CONFIG_LPS + +#ifdef CONFIG_BEAMFORMING + update_attrib_txbf_info(padapter, pattrib, psta); +#endif + + //TODO:_lock + if(update_attrib_sec_info(padapter, pattrib, psta) == _FAIL) + { + DBG_COUNTER(padapter->tx_logs.core_tx_upd_attrib_err_sec); + res = _FAIL; + goto exit; + } + + update_attrib_phy_info(padapter, pattrib, psta); + + //DBG_8192C("%s ==> mac_id(%d)\n",__FUNCTION__,pattrib->mac_id ); + + pattrib->psta = psta; + //TODO:_unlock + + pattrib->pctrl = 0; + + pattrib->ack_policy = 0; + // get ether_hdr_len + pattrib->pkt_hdrlen = ETH_HLEN;//(pattrib->ether_type == 0x8100) ? (14 + 4 ): 14; //vlan tag + + pattrib->hdrlen = WLAN_HDR_A3_LEN; + pattrib->subtype = WIFI_DATA_TYPE; + pattrib->priority = 0; + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE|WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE)) + { + if(pattrib->qos_en) + set_qos(&pktfile, pattrib); + } + else + { +#ifdef CONFIG_TDLS + if (pattrib->direct_link == _TRUE) { + if (pattrib->qos_en) + set_qos(&pktfile, pattrib); + } else +#endif + { + if (pqospriv->qos_option) { + set_qos(&pktfile, pattrib); + + if (pmlmepriv->acm_mask != 0) + pattrib->priority = qos_acm(pmlmepriv->acm_mask, pattrib->priority); + } + } + } + + //pattrib->priority = 5; //force to used VI queue, for testing + pattrib->hw_ssn_sel = pxmitpriv->hw_ssn_seq_no; + rtw_set_tx_chksum_offload(pkt, pattrib); + +exit: + +_func_exit_; + + return res; +} + +static s32 xmitframe_addmic(_adapter *padapter, struct xmit_frame *pxmitframe){ + sint curfragnum,length; + u8 *pframe, *payload,mic[8]; + struct mic_data micdata; + //struct sta_info *stainfo; + struct qos_priv *pqospriv= &(padapter->mlmepriv.qospriv); + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct security_priv *psecuritypriv=&padapter->securitypriv; + struct xmit_priv *pxmitpriv=&padapter->xmitpriv; + u8 priority[4]={0x0,0x0,0x0,0x0}; + u8 hw_hdr_offset = 0; + sint bmcst = IS_MCAST(pattrib->ra); + +/* + if(pattrib->psta) + { + stainfo = pattrib->psta; + } + else + { + DBG_871X("%s, call rtw_get_stainfo()\n", __func__); + stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0]); + } + + if(stainfo==NULL) + { + DBG_871X("%s, psta==NUL\n", __func__); + return _FAIL; + } + + if(!(stainfo->state &_FW_LINKED)) + { + DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, stainfo->state); + return _FAIL; + } +*/ + +_func_enter_; + +#ifdef CONFIG_USB_TX_AGGREGATION + hw_hdr_offset = TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ);; +#else + #ifdef CONFIG_TX_EARLY_MODE + hw_hdr_offset = TXDESC_OFFSET+ EARLY_MODE_INFO_SIZE; + #else + hw_hdr_offset = TXDESC_OFFSET; + #endif +#endif + + if(pattrib->encrypt ==_TKIP_)//if(psecuritypriv->dot11PrivacyAlgrthm==_TKIP_PRIVACY_) + { + //encode mic code + //if(stainfo!= NULL) + { + u8 null_key[16]={0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}; + + pframe = pxmitframe->buf_addr + hw_hdr_offset; + + if(bmcst) + { + if(_rtw_memcmp(psecuritypriv->dot118021XGrptxmickey[psecuritypriv->dot118021XGrpKeyid].skey, null_key, 16)==_TRUE){ + //DbgPrint("\nxmitframe_addmic:stainfo->dot11tkiptxmickey==0\n"); + //rtw_msleep_os(10); + return _FAIL; + } + //start to calculate the mic code + rtw_secmicsetkey(&micdata, psecuritypriv->dot118021XGrptxmickey[psecuritypriv->dot118021XGrpKeyid].skey); + } + else + { + if(_rtw_memcmp(&pattrib->dot11tkiptxmickey.skey[0],null_key, 16)==_TRUE){ + //DbgPrint("\nxmitframe_addmic:stainfo->dot11tkiptxmickey==0\n"); + //rtw_msleep_os(10); + return _FAIL; + } + //start to calculate the mic code + rtw_secmicsetkey(&micdata, &pattrib->dot11tkiptxmickey.skey[0]); + } + + if(pframe[1]&1){ //ToDS==1 + rtw_secmicappend(&micdata, &pframe[16], 6); //DA + if(pframe[1]&2) //From Ds==1 + rtw_secmicappend(&micdata, &pframe[24], 6); + else + rtw_secmicappend(&micdata, &pframe[10], 6); + } + else{ //ToDS==0 + rtw_secmicappend(&micdata, &pframe[4], 6); //DA + if(pframe[1]&2) //From Ds==1 + rtw_secmicappend(&micdata, &pframe[16], 6); + else + rtw_secmicappend(&micdata, &pframe[10], 6); + + } + + //if(pqospriv->qos_option==1) + if(pattrib->qos_en) + priority[0]=(u8)pxmitframe->attrib.priority; + + + rtw_secmicappend(&micdata, &priority[0], 4); + + payload=pframe; + + for(curfragnum=0;curfragnumnr_frags;curfragnum++){ + payload=(u8 *)RND4((SIZE_PTR)(payload)); + RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("===curfragnum=%d, pframe= 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x,!!!\n", + curfragnum,*payload, *(payload+1),*(payload+2),*(payload+3),*(payload+4),*(payload+5),*(payload+6),*(payload+7))); + + payload=payload+pattrib->hdrlen+pattrib->iv_len; + RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("curfragnum=%d pattrib->hdrlen=%d pattrib->iv_len=%d",curfragnum,pattrib->hdrlen,pattrib->iv_len)); + if((curfragnum+1)==pattrib->nr_frags){ + length=pattrib->last_txcmdsz-pattrib->hdrlen-pattrib->iv_len-( (pattrib->bswenc) ? pattrib->icv_len : 0); + rtw_secmicappend(&micdata, payload,length); + payload=payload+length; + } + else{ + length=pxmitpriv->frag_len-pattrib->hdrlen-pattrib->iv_len-( (pattrib->bswenc) ? pattrib->icv_len : 0); + rtw_secmicappend(&micdata, payload, length); + payload=payload+length+pattrib->icv_len; + RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("curfragnum=%d length=%d pattrib->icv_len=%d",curfragnum,length,pattrib->icv_len)); + } + } + rtw_secgetmic(&micdata,&(mic[0])); + RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("xmitframe_addmic: before add mic code!!!\n")); + RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("xmitframe_addmic: pattrib->last_txcmdsz=%d!!!\n",pattrib->last_txcmdsz)); + RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("xmitframe_addmic: mic[0]=0x%.2x ,mic[1]=0x%.2x ,mic[2]=0x%.2x ,mic[3]=0x%.2x \n\ + mic[4]=0x%.2x ,mic[5]=0x%.2x ,mic[6]=0x%.2x ,mic[7]=0x%.2x !!!!\n", + mic[0],mic[1],mic[2],mic[3],mic[4],mic[5],mic[6],mic[7])); + //add mic code and add the mic code length in last_txcmdsz + + _rtw_memcpy(payload, &(mic[0]),8); + pattrib->last_txcmdsz+=8; + + RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("\n ========last pkt========\n")); + payload=payload-pattrib->last_txcmdsz+8; + for(curfragnum=0;curfragnumlast_txcmdsz;curfragnum=curfragnum+8) + RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,(" %.2x, %.2x, %.2x, %.2x, %.2x, %.2x, %.2x, %.2x ", + *(payload+curfragnum), *(payload+curfragnum+1), *(payload+curfragnum+2),*(payload+curfragnum+3), + *(payload+curfragnum+4),*(payload+curfragnum+5),*(payload+curfragnum+6),*(payload+curfragnum+7))); + } +/* + else{ + RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("xmitframe_addmic: rtw_get_stainfo==NULL!!!\n")); + } +*/ + } + +_func_exit_; + + return _SUCCESS; +} + +static s32 xmitframe_swencrypt(_adapter *padapter, struct xmit_frame *pxmitframe){ + + struct pkt_attrib *pattrib = &pxmitframe->attrib; + //struct security_priv *psecuritypriv=&padapter->securitypriv; + +_func_enter_; + + //if((psecuritypriv->sw_encrypt)||(pattrib->bswenc)) + if(pattrib->bswenc) + { + //DBG_871X("start xmitframe_swencrypt\n"); + RT_TRACE(_module_rtl871x_xmit_c_,_drv_alert_,("### xmitframe_swencrypt\n")); + switch(pattrib->encrypt){ + case _WEP40_: + case _WEP104_: + rtw_wep_encrypt(padapter, (u8 *)pxmitframe); + break; + case _TKIP_: + rtw_tkip_encrypt(padapter, (u8 *)pxmitframe); + break; + case _AES_: + rtw_aes_encrypt(padapter, (u8 * )pxmitframe); + break; +#ifdef CONFIG_WAPI_SUPPORT + case _SMS4_: + rtw_sms4_encrypt(padapter, (u8 * )pxmitframe); +#endif + default: + break; + } + + } else { + RT_TRACE(_module_rtl871x_xmit_c_,_drv_notice_,("### xmitframe_hwencrypt\n")); + } + +_func_exit_; + + return _SUCCESS; +} + +s32 rtw_make_wlanhdr (_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib) +{ + u16 *qc; + + struct rtw_ieee80211_hdr *pwlanhdr = (struct rtw_ieee80211_hdr *)hdr; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct qos_priv *pqospriv = &pmlmepriv->qospriv; + u8 qos_option = _FALSE; + sint res = _SUCCESS; + u16 *fctrl = &pwlanhdr->frame_ctl; + + //struct sta_info *psta; + + //sint bmcst = IS_MCAST(pattrib->ra); + +_func_enter_; + +/* + psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); + if(pattrib->psta != psta) + { + DBG_871X("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta); + return; + } + + if(psta==NULL) + { + DBG_871X("%s, psta==NUL\n", __func__); + return _FAIL; + } + + if(!(psta->state &_FW_LINKED)) + { + DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state); + return _FAIL; + } +*/ + + _rtw_memset(hdr, 0, WLANHDR_OFFSET); + + SetFrameSubType(fctrl, pattrib->subtype); + + if (pattrib->subtype & WIFI_DATA_TYPE) + { + if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)) { +#ifdef CONFIG_TDLS + if(pattrib->direct_link == _TRUE){ + //TDLS data transfer, ToDS=0, FrDs=0 + _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN); + + if (pattrib->qos_en) + qos_option = _TRUE; + } + else +#endif //CONFIG_TDLS + { + //to_ds = 1, fr_ds = 0; + // 1.Data transfer to AP + // 2.Arp pkt will relayed by AP + SetToDs(fctrl); + _rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pattrib->ta, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN); + + if (pqospriv->qos_option) + qos_option = _TRUE; + } + } + else if ((check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ) { + //to_ds = 0, fr_ds = 1; + SetFrDs(fctrl); + _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, pattrib->src, ETH_ALEN); + + if(pattrib->qos_en) + qos_option = _TRUE; + } + else if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { + _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pattrib->ta, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN); + + if(pattrib->qos_en) + qos_option = _TRUE; + } + else { + RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("fw_state:%x is not allowed to xmit frame\n", get_fwstate(pmlmepriv))); + res = _FAIL; + goto exit; + } + + if(pattrib->mdata) + SetMData(fctrl); + + if (pattrib->encrypt) + SetPrivacy(fctrl); + + if (qos_option) + { + qc = (unsigned short *)(hdr + pattrib->hdrlen - 2); + + if (pattrib->priority) + SetPriority(qc, pattrib->priority); + + SetEOSP(qc, pattrib->eosp); + + SetAckpolicy(qc, pattrib->ack_policy); + } + + //TODO: fill HT Control Field + + //Update Seq Num will be handled by f/w + { + struct sta_info *psta; + psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); + if(pattrib->psta != psta) + { + DBG_871X("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta); + return _FAIL; + } + + if(psta==NULL) + { + DBG_871X("%s, psta==NUL\n", __func__); + return _FAIL; + } + + if(!(psta->state &_FW_LINKED)) + { + DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state); + return _FAIL; + } + + + if(psta) + { + psta->sta_xmitpriv.txseq_tid[pattrib->priority]++; + psta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF; + pattrib->seqnum = psta->sta_xmitpriv.txseq_tid[pattrib->priority]; + + SetSeqNum(hdr, pattrib->seqnum); + +#ifdef CONFIG_80211N_HT + //check if enable ampdu + if(pattrib->ht_en && psta->htpriv.ampdu_enable) + { + if(psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) + pattrib->ampdu_en = _TRUE; + } + + //re-check if enable ampdu by BA_starting_seqctrl + if(pattrib->ampdu_en == _TRUE) + { + u16 tx_seq; + + tx_seq = psta->BA_starting_seqctrl[pattrib->priority & 0x0f]; + + //check BA_starting_seqctrl + if(SN_LESS(pattrib->seqnum, tx_seq)) + { + //DBG_871X("tx ampdu seqnum(%d) < tx_seq(%d)\n", pattrib->seqnum, tx_seq); + pattrib->ampdu_en = _FALSE;//AGG BK + } + else if(SN_EQUAL(pattrib->seqnum, tx_seq)) + { + psta->BA_starting_seqctrl[pattrib->priority & 0x0f] = (tx_seq+1)&0xfff; + + pattrib->ampdu_en = _TRUE;//AGG EN + } + else + { + //DBG_871X("tx ampdu over run\n"); + psta->BA_starting_seqctrl[pattrib->priority & 0x0f] = (pattrib->seqnum+1)&0xfff; + pattrib->ampdu_en = _TRUE;//AGG EN + } + + } +#endif //CONFIG_80211N_HT + } + } + + } + else + { + + } + +exit: + +_func_exit_; + + return res; +} + +s32 rtw_txframes_pending(_adapter *padapter) +{ + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + return ((_rtw_queue_empty(&pxmitpriv->be_pending) == _FALSE) || + (_rtw_queue_empty(&pxmitpriv->bk_pending) == _FALSE) || + (_rtw_queue_empty(&pxmitpriv->vi_pending) == _FALSE) || + (_rtw_queue_empty(&pxmitpriv->vo_pending) == _FALSE)); +} + +s32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib) +{ + struct sta_info *psta; + struct tx_servq *ptxservq; + int priority = pattrib->priority; +/* + if(pattrib->psta) + { + psta = pattrib->psta; + } + else + { + DBG_871X("%s, call rtw_get_stainfo()\n", __func__); + psta=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0]); + } +*/ + psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); + if(pattrib->psta != psta) + { + DBG_871X("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta); + return 0; + } + + if(psta==NULL) + { + DBG_871X("%s, psta==NUL\n", __func__); + return 0; + } + + if(!(psta->state &_FW_LINKED)) + { + DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state); + return 0; + } + + switch(priority) + { + case 1: + case 2: + ptxservq = &(psta->sta_xmitpriv.bk_q); + break; + case 4: + case 5: + ptxservq = &(psta->sta_xmitpriv.vi_q); + break; + case 6: + case 7: + ptxservq = &(psta->sta_xmitpriv.vo_q); + break; + case 0: + case 3: + default: + ptxservq = &(psta->sta_xmitpriv.be_q); + break; + + } + + return ptxservq->qcnt; +} + +#ifdef CONFIG_TDLS + +int rtw_build_tdls_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt) +{ + int res=_SUCCESS; + + switch(ptxmgmt->action_code){ + case TDLS_SETUP_REQUEST: + rtw_build_tdls_setup_req_ies(padapter, pxmitframe, pframe, ptxmgmt); + break; + case TDLS_SETUP_RESPONSE: + rtw_build_tdls_setup_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt); + break; + case TDLS_SETUP_CONFIRM: + rtw_build_tdls_setup_cfm_ies(padapter, pxmitframe, pframe, ptxmgmt); + break; + case TDLS_TEARDOWN: + rtw_build_tdls_teardown_ies(padapter, pxmitframe, pframe, ptxmgmt); + break; + case TDLS_DISCOVERY_REQUEST: + rtw_build_tdls_dis_req_ies(padapter, pxmitframe, pframe, ptxmgmt); + break; + case TDLS_PEER_TRAFFIC_INDICATION: + rtw_build_tdls_peer_traffic_indication_ies(padapter, pxmitframe, pframe, ptxmgmt); + break; +#ifdef CONFIG_TDLS_CH_SW + case TDLS_CHANNEL_SWITCH_REQUEST: + rtw_build_tdls_ch_switch_req_ies(padapter, pxmitframe, pframe, ptxmgmt); + break; + case TDLS_CHANNEL_SWITCH_RESPONSE: + rtw_build_tdls_ch_switch_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt); + break; +#endif + case TDLS_PEER_TRAFFIC_RESPONSE: + rtw_build_tdls_peer_traffic_rsp_ies(padapter, pxmitframe, pframe, ptxmgmt); + break; +#ifdef CONFIG_WFD + case TUNNELED_PROBE_REQ: + rtw_build_tunneled_probe_req_ies(padapter, pxmitframe, pframe); + break; + case TUNNELED_PROBE_RSP: + rtw_build_tunneled_probe_rsp_ies(padapter, pxmitframe, pframe); + break; +#endif //CONFIG_WFD + default: + res=_FAIL; + break; + } + + return res; +} + +s32 rtw_make_tdls_wlanhdr (_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib, struct tdls_txmgmt *ptxmgmt) +{ + u16 *qc; + struct rtw_ieee80211_hdr *pwlanhdr = (struct rtw_ieee80211_hdr *)hdr; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct qos_priv *pqospriv = &pmlmepriv->qospriv; + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta=NULL, *ptdls_sta=NULL; + u8 tdls_seq=0, baddr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; + + sint res = _SUCCESS; + u16 *fctrl = &pwlanhdr->frame_ctl; + +_func_enter_; + + _rtw_memset(hdr, 0, WLANHDR_OFFSET); + + SetFrameSubType(fctrl, pattrib->subtype); + + switch(ptxmgmt->action_code){ + case TDLS_SETUP_REQUEST: + case TDLS_SETUP_RESPONSE: + case TDLS_SETUP_CONFIRM: + case TDLS_PEER_TRAFFIC_INDICATION: + case TDLS_PEER_PSM_REQUEST: + case TUNNELED_PROBE_REQ: + case TUNNELED_PROBE_RSP: + case TDLS_DISCOVERY_REQUEST: + SetToDs(fctrl); + _rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN); + break; + case TDLS_CHANNEL_SWITCH_REQUEST: + case TDLS_CHANNEL_SWITCH_RESPONSE: + case TDLS_PEER_PSM_RESPONSE: + case TDLS_PEER_TRAFFIC_RESPONSE: + _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN); + tdls_seq=1; + break; + case TDLS_TEARDOWN: + if(ptxmgmt->status_code == _RSON_TDLS_TEAR_UN_RSN_) + { + _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN); + tdls_seq=1; + } + else + { + SetToDs(fctrl); + _rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN); + } + break; + } + + if (pattrib->encrypt) + SetPrivacy(fctrl); + + if(ptxmgmt->action_code == TDLS_PEER_TRAFFIC_RESPONSE) + { + SetPwrMgt(fctrl); + } + + if (pqospriv->qos_option) + { + qc = (unsigned short *)(hdr + pattrib->hdrlen - 2); + if (pattrib->priority) + SetPriority(qc, pattrib->priority); + SetAckpolicy(qc, pattrib->ack_policy); + } + + psta = pattrib->psta; + + // 1. update seq_num per link by sta_info + // 2. rewrite encrypt to _AES_, also rewrite iv_len, icv_len + if(tdls_seq==1){ + ptdls_sta=rtw_get_stainfo(pstapriv, pattrib->dst); + if(ptdls_sta){ + ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority]++; + ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF; + pattrib->seqnum = ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority]; + SetSeqNum(hdr, pattrib->seqnum); + + if (pattrib->encrypt){ + pattrib->encrypt= _AES_; + pattrib->iv_len=8; + pattrib->icv_len=8; + pattrib->bswenc = _FALSE; + } + pattrib->mac_id = ptdls_sta->mac_id; + }else{ + res=_FAIL; + goto exit; + } + }else if(psta){ + psta->sta_xmitpriv.txseq_tid[pattrib->priority]++; + psta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF; + pattrib->seqnum = psta->sta_xmitpriv.txseq_tid[pattrib->priority]; + SetSeqNum(hdr, pattrib->seqnum); + } + + +exit: + +_func_exit_; + + return res; +} + +s32 rtw_xmit_tdls_coalesce(_adapter * padapter, struct xmit_frame * pxmitframe, struct tdls_txmgmt *ptxmgmt) +{ + s32 llc_sz; + + u8 *pframe, *mem_start; + + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + u8 *pbuf_start; + s32 bmcst = IS_MCAST(pattrib->ra); + s32 res = _SUCCESS; + +_func_enter_; + + if (pattrib->psta) { + psta = pattrib->psta; + } else { + if(bmcst) { + psta = rtw_get_bcmc_stainfo(padapter); + } else { + psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); + } + } + + if (psta==NULL) { + res = _FAIL; + goto exit; + } + + if (pxmitframe->buf_addr == NULL) { + res = _FAIL; + goto exit; + } + + pbuf_start = pxmitframe->buf_addr; + mem_start = pbuf_start + TXDESC_OFFSET; + + if (rtw_make_tdls_wlanhdr(padapter, mem_start, pattrib, ptxmgmt) == _FAIL) { + res = _FAIL; + goto exit; + } + + pframe = mem_start; + pframe += pattrib->hdrlen; + + //adding icv, if necessary... + if (pattrib->iv_len) + { + if (psta != NULL) + { + switch(pattrib->encrypt) + { + case _WEP40_: + case _WEP104_: + WEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); + break; + case _TKIP_: + if(bmcst) + TKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); + else + TKIP_IV(pattrib->iv, psta->dot11txpn, 0); + break; + case _AES_: + if(bmcst) + AES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); + else + AES_IV(pattrib->iv, psta->dot11txpn, 0); + break; + } + } + + _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); + pframe += pattrib->iv_len; + + } + + llc_sz = rtw_put_snap(pframe, pattrib->ether_type); + pframe += llc_sz; + + //pattrib->pktlen will be counted in rtw_build_tdls_ies + pattrib->pktlen = 0; + + rtw_build_tdls_ies(padapter, pxmitframe, pframe, ptxmgmt); + + if ((pattrib->icv_len >0 )&& (pattrib->bswenc)) { + pframe += pattrib->pktlen; + _rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len); + pframe += pattrib->icv_len; + } + + pattrib->nr_frags = 1; + pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len + llc_sz + + ((pattrib->bswenc) ? pattrib->icv_len : 0) + pattrib->pktlen; + + if (xmitframe_addmic(padapter, pxmitframe) == _FAIL) + { + res = _FAIL; + goto exit; + } + + xmitframe_swencrypt(padapter, pxmitframe); + + update_attrib_vcs_info(padapter, pxmitframe); + +exit: + +_func_exit_; + + return res; +} +#endif //CONFIG_TDLS + +/* + * Calculate wlan 802.11 packet MAX size from pkt_attrib + * This function doesn't consider fragment case + */ +u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib) +{ + u32 len = 0; + + len = pattrib->hdrlen + pattrib->iv_len; // WLAN Header and IV + len += SNAP_SIZE + sizeof(u16); // LLC + len += pattrib->pktlen; + if (pattrib->encrypt == _TKIP_) len += 8; // MIC + len += ((pattrib->bswenc) ? pattrib->icv_len : 0); // ICV + + return len; +} + +/* + +This sub-routine will perform all the following: + +1. remove 802.3 header. +2. create wlan_header, based on the info in pxmitframe +3. append sta's iv/ext-iv +4. append LLC +5. move frag chunk from pframe to pxmitframe->mem +6. apply sw-encrypt, if necessary. + +*/ +s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe) +{ + struct pkt_file pktfile; + + s32 frg_inx, frg_len, mpdu_len, llc_sz, mem_sz; + + SIZE_PTR addr; + + u8 *pframe, *mem_start; + u8 hw_hdr_offset; + + //struct sta_info *psta; + //struct sta_priv *pstapriv = &padapter->stapriv; + //struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + struct pkt_attrib *pattrib = &pxmitframe->attrib; + + u8 *pbuf_start; + + s32 bmcst = IS_MCAST(pattrib->ra); + s32 res = _SUCCESS; + +_func_enter_; + +/* + if (pattrib->psta) + { + psta = pattrib->psta; + } else + { + DBG_871X("%s, call rtw_get_stainfo()\n", __func__); + psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); + } + + if(psta==NULL) + { + + DBG_871X("%s, psta==NUL\n", __func__); + return _FAIL; + } + + + if(!(psta->state &_FW_LINKED)) + { + DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state); + return _FAIL; + } +*/ + if (pxmitframe->buf_addr == NULL){ + DBG_8192C("==> %s buf_addr==NULL \n",__FUNCTION__); + return _FAIL; + } + + pbuf_start = pxmitframe->buf_addr; + +#ifdef CONFIG_USB_TX_AGGREGATION + hw_hdr_offset = TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ); +#else + #ifdef CONFIG_TX_EARLY_MODE //for SDIO && Tx Agg + hw_hdr_offset = TXDESC_OFFSET + EARLY_MODE_INFO_SIZE; + #else + hw_hdr_offset = TXDESC_OFFSET; + #endif +#endif + + mem_start = pbuf_start + hw_hdr_offset; + + if (rtw_make_wlanhdr(padapter, mem_start, pattrib) == _FAIL) { + RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("rtw_xmitframe_coalesce: rtw_make_wlanhdr fail; drop pkt\n")); + DBG_8192C("rtw_xmitframe_coalesce: rtw_make_wlanhdr fail; drop pkt\n"); + res = _FAIL; + goto exit; + } + + _rtw_open_pktfile(pkt, &pktfile); + _rtw_pktfile_read(&pktfile, NULL, pattrib->pkt_hdrlen); + + frg_inx = 0; + frg_len = pxmitpriv->frag_len - 4;//2346-4 = 2342 + + while (1) + { + llc_sz = 0; + + mpdu_len = frg_len; + + pframe = mem_start; + + SetMFrag(mem_start); + + pframe += pattrib->hdrlen; + mpdu_len -= pattrib->hdrlen; + + //adding icv, if necessary... + if (pattrib->iv_len) + { +/* + //if (check_fwstate(pmlmepriv, WIFI_MP_STATE)) + // psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); + //else + // psta = rtw_get_stainfo(pstapriv, pattrib->ra); + + if (psta != NULL) + { + switch(pattrib->encrypt) + { + case _WEP40_: + case _WEP104_: + WEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); + break; + case _TKIP_: + if(bmcst) + TKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); + else + TKIP_IV(pattrib->iv, psta->dot11txpn, 0); + break; + case _AES_: + if(bmcst) + AES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); + else + AES_IV(pattrib->iv, psta->dot11txpn, 0); + break; +#ifdef CONFIG_WAPI_SUPPORT + case _SMS4_: + rtw_wapi_get_iv(padapter,pattrib->ra,pattrib->iv); + break; +#endif + } + } +*/ + _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); + + RT_TRACE(_module_rtl871x_xmit_c_, _drv_notice_, + ("rtw_xmitframe_coalesce: keyid=%d pattrib->iv[3]=%.2x pframe=%.2x %.2x %.2x %.2x\n", + padapter->securitypriv.dot11PrivacyKeyIndex, pattrib->iv[3], *pframe, *(pframe+1), *(pframe+2), *(pframe+3))); + + pframe += pattrib->iv_len; + + mpdu_len -= pattrib->iv_len; + } + + if (frg_inx == 0) { + llc_sz = rtw_put_snap(pframe, pattrib->ether_type); + pframe += llc_sz; + mpdu_len -= llc_sz; + } + + if ((pattrib->icv_len >0) && (pattrib->bswenc)) { + mpdu_len -= pattrib->icv_len; + } + + + if (bmcst) { + // don't do fragment to broadcat/multicast packets + mem_sz = _rtw_pktfile_read(&pktfile, pframe, pattrib->pktlen); + } else { + mem_sz = _rtw_pktfile_read(&pktfile, pframe, mpdu_len); + } + + pframe += mem_sz; + + if ((pattrib->icv_len >0 )&& (pattrib->bswenc)) { + _rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len); + pframe += pattrib->icv_len; + } + + frg_inx++; + + if (bmcst || (rtw_endofpktfile(&pktfile) == _TRUE)) + { + pattrib->nr_frags = frg_inx; + + pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len + ((pattrib->nr_frags==1)? llc_sz:0) + + ((pattrib->bswenc) ? pattrib->icv_len : 0) + mem_sz; + + ClearMFrag(mem_start); + + break; + } else { + RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("%s: There're still something in packet!\n", __FUNCTION__)); + } + + addr = (SIZE_PTR)(pframe); + + mem_start = (unsigned char *)RND4(addr) + hw_hdr_offset; + _rtw_memcpy(mem_start, pbuf_start + hw_hdr_offset, pattrib->hdrlen); + + } + + if (xmitframe_addmic(padapter, pxmitframe) == _FAIL) + { + RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("xmitframe_addmic(padapter, pxmitframe)==_FAIL\n")); + DBG_8192C("xmitframe_addmic(padapter, pxmitframe)==_FAIL\n"); + res = _FAIL; + goto exit; + } + + xmitframe_swencrypt(padapter, pxmitframe); + + if(bmcst == _FALSE) + update_attrib_vcs_info(padapter, pxmitframe); + else + pattrib->vcs_mode = NONE_VCS; + +exit: + +_func_exit_; + + return res; +} + +#ifdef CONFIG_IEEE80211W +//broadcast or multicast management pkt use BIP, unicast management pkt use CCMP encryption +s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe) +{ + struct pkt_file pktfile; + s32 frg_inx, frg_len, mpdu_len, llc_sz, mem_sz; + SIZE_PTR addr; + u8 *pframe, *mem_start = NULL, *tmp_buf=NULL; + u8 hw_hdr_offset, subtype ; + struct sta_info *psta = NULL; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + u8 *pbuf_start; + s32 bmcst = IS_MCAST(pattrib->ra); + s32 res = _FAIL; + u8 *BIP_AAD=NULL; + u8 *MGMT_body=NULL; + + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct rtw_ieee80211_hdr *pwlanhdr; + u8 MME[_MME_IE_LENGTH_]; + + _irqL irqL; + u32 ori_len; + mem_start = pframe = (u8 *)(pxmitframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + +_func_enter_; + ori_len = BIP_AAD_SIZE+pattrib->pktlen; + tmp_buf = BIP_AAD = rtw_zmalloc(ori_len); + subtype = GetFrameSubType(pframe); //bit(7)~bit(2) + + if(BIP_AAD == NULL) + return _FAIL; + + _enter_critical_bh(&padapter->security_key_mutex, &irqL); + + + //IGTK key is not install, it may not support 802.11w + if(padapter->securitypriv.binstallBIPkey != _TRUE) + { + DBG_871X("no instll BIP key\n"); + goto xmitframe_coalesce_success; + } + //station mode doesn't need TX BIP, just ready the code + if(bmcst) + { + int frame_body_len; + u8 mic[16]; + + _rtw_memset(MME, 0, _MME_IE_LENGTH_); + + //other types doesn't need the BIP + if(GetFrameSubType(pframe) != WIFI_DEAUTH && GetFrameSubType(pframe) != WIFI_DISASSOC) + goto xmitframe_coalesce_fail; + + MGMT_body = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); + pframe += pattrib->pktlen; + + //octent 0 and 1 is key index ,BIP keyid is 4 or 5, LSB only need octent 0 + MME[0]=padapter->securitypriv.dot11wBIPKeyid; + //copy packet number + _rtw_memcpy(&MME[2], &pmlmeext->mgnt_80211w_IPN, 6); + //increase the packet number + pmlmeext->mgnt_80211w_IPN++; + + //add MME IE with MIC all zero, MME string doesn't include element id and length + pframe = rtw_set_ie(pframe, _MME_IE_ , 16 , MME, &(pattrib->pktlen)); + pattrib->last_txcmdsz = pattrib->pktlen; + // total frame length - header length + frame_body_len = pattrib->pktlen - sizeof(struct rtw_ieee80211_hdr_3addr); + + //conscruct AAD, copy frame control field + _rtw_memcpy(BIP_AAD, &pwlanhdr->frame_ctl, 2); + ClearRetry(BIP_AAD); + ClearPwrMgt(BIP_AAD); + ClearMData(BIP_AAD); + //conscruct AAD, copy address 1 to address 3 + _rtw_memcpy(BIP_AAD+2, pwlanhdr->addr1, 18); + //copy management fram body + _rtw_memcpy(BIP_AAD+BIP_AAD_SIZE, MGMT_body, frame_body_len); + /*//dump total packet include MME with zero MIC + { + int i; + printk("Total packet: "); + for(i=0; i < BIP_AAD_SIZE+frame_body_len; i++) + printk(" %02x ", BIP_AAD[i]); + printk("\n"); + }*/ + //calculate mic + if(omac1_aes_128(padapter->securitypriv.dot11wBIPKey[padapter->securitypriv.dot11wBIPKeyid].skey + , BIP_AAD, BIP_AAD_SIZE+frame_body_len, mic)) + goto xmitframe_coalesce_fail; + + /*//dump calculated mic result + { + int i; + printk("Calculated mic result: "); + for(i=0; i<16; i++) + printk(" %02x ", mic[i]); + printk("\n"); + }*/ + //copy right BIP mic value, total is 128bits, we use the 0~63 bits + _rtw_memcpy(pframe-8, mic, 8); + /*/dump all packet after mic ok + { + int pp; + printk("pattrib->pktlen = %d \n", pattrib->pktlen); + for(pp=0;pp< pattrib->pktlen; pp++) + printk(" %02x ", mem_start[pp]); + printk("\n"); + }*/ + } + else //unicast mgmt frame TX + { + //start to encrypt mgmt frame + if(subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC || + subtype == WIFI_REASSOCREQ || subtype == WIFI_ACTION) + { + if (pattrib->psta) + psta = pattrib->psta; + else + { + psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); + } + + if(psta==NULL) + { + + DBG_871X("%s, psta==NUL\n", __func__); + goto xmitframe_coalesce_fail; + } + + if (pxmitframe->buf_addr == NULL) { + DBG_871X("%s, pxmitframe->buf_addr\n", __func__); + goto xmitframe_coalesce_fail; + } + + //DBG_871X("%s, action frame category=%d \n", __func__, pframe[WLAN_HDR_A3_LEN]); + //according 802.11-2012 standard, these five types are not robust types + if(subtype == WIFI_ACTION && + (pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_PUBLIC || + pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_HT || + pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_UNPROTECTED_WNM || + pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_SELF_PROTECTED || + pframe[WLAN_HDR_A3_LEN] == RTW_WLAN_CATEGORY_P2P)) + goto xmitframe_coalesce_fail; + //before encrypt dump the management packet content + /*{ + int i; + printk("Management pkt: "); + for(i=0; ipktlen; i++) + printk(" %02x ", pframe[i]); + printk("=======\n"); + }*/ + if(pattrib->encrypt>0) + _rtw_memcpy(pattrib->dot118021x_UncstKey.skey, psta->dot118021x_UncstKey.skey, 16); + + /* To use wrong key */ + if (pattrib->key_type == IEEE80211W_WRONG_KEY) { + DBG_871X("use wrong key\n"); + pattrib->dot118021x_UncstKey.skey[0] = 0xff; + } + + //bakeup original management packet + _rtw_memcpy(tmp_buf, pframe, pattrib->pktlen); + //move to data portion + pframe += pattrib->hdrlen; + + //802.11w unicast management packet must be _AES_ + pattrib->iv_len = 8; + //it's MIC of AES + pattrib->icv_len = 8; + + switch(pattrib->encrypt) + { + case _AES_: + //set AES IV header + AES_IV(pattrib->iv, psta->dot11wtxpn, 0); + break; + default: + goto xmitframe_coalesce_fail; + } + //insert iv header into management frame + _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); + pframe += pattrib->iv_len; + //copy mgmt data portion after CCMP header + _rtw_memcpy(pframe, tmp_buf+pattrib->hdrlen, pattrib->pktlen-pattrib->hdrlen); + //move pframe to end of mgmt pkt + pframe += pattrib->pktlen-pattrib->hdrlen; + //add 8 bytes CCMP IV header to length + pattrib->pktlen += pattrib->iv_len; + /*//dump management packet include AES IV header + { + int i; + printk("Management pkt + IV: "); + //for(i=0; ipktlen; i++) + //printk(" %02x ", mem_start[i]); + printk("@@@@@@@@@@@@@\n"); + }*/ + + if ((pattrib->icv_len >0 )&& (pattrib->bswenc)) { + _rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len); + pframe += pattrib->icv_len; + } + //add 8 bytes MIC + pattrib->pktlen += pattrib->icv_len; + //set final tx command size + pattrib->last_txcmdsz = pattrib->pktlen; + + //set protected bit must be beofre SW encrypt + SetPrivacy(mem_start); + /*//dump management packet include AES header + { + int i; + printk("prepare to enc Management pkt + IV: "); + for(i=0; ipktlen; i++) + printk(" %02x ", mem_start[i]); + printk("@@@@@@@@@@@@@\n"); + }*/ + //software encrypt + xmitframe_swencrypt(padapter, pxmitframe); + } + } + +xmitframe_coalesce_success: + _exit_critical_bh(&padapter->security_key_mutex, &irqL); + rtw_mfree(BIP_AAD, ori_len); +_func_exit_; + return _SUCCESS; + +xmitframe_coalesce_fail: + _exit_critical_bh(&padapter->security_key_mutex, &irqL); + rtw_mfree(BIP_AAD, ori_len); +_func_exit_; + + return _FAIL; +} +#endif //CONFIG_IEEE80211W + +/* Logical Link Control(LLC) SubNetwork Attachment Point(SNAP) header + * IEEE LLC/SNAP header contains 8 octets + * First 3 octets comprise the LLC portion + * SNAP portion, 5 octets, is divided into two fields: + * Organizationally Unique Identifier(OUI), 3 octets, + * type, defined by that organization, 2 octets. + */ +s32 rtw_put_snap(u8 *data, u16 h_proto) +{ + struct ieee80211_snap_hdr *snap; + u8 *oui; + +_func_enter_; + + snap = (struct ieee80211_snap_hdr *)data; + snap->dsap = 0xaa; + snap->ssap = 0xaa; + snap->ctrl = 0x03; + + if (h_proto == 0x8137 || h_proto == 0x80f3) + oui = P802_1H_OUI; + else + oui = RFC1042_OUI; + + snap->oui[0] = oui[0]; + snap->oui[1] = oui[1]; + snap->oui[2] = oui[2]; + + *(u16 *)(data + SNAP_SIZE) = htons(h_proto); + +_func_exit_; + + return SNAP_SIZE + sizeof(u16); +} + +void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len) +{ + + uint protection; + u8 *perp; + sint erp_len; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct registry_priv *pregistrypriv = &padapter->registrypriv; + +_func_enter_; + + switch(pxmitpriv->vcs_setting) + { + case DISABLE_VCS: + pxmitpriv->vcs = NONE_VCS; + break; + + case ENABLE_VCS: + break; + + case AUTO_VCS: + default: + perp = rtw_get_ie(ie, _ERPINFO_IE_, &erp_len, ie_len); + if(perp == NULL) + { + pxmitpriv->vcs = NONE_VCS; + } + else + { + protection = (*(perp + 2)) & BIT(1); + if (protection) + { + if(pregistrypriv->vcs_type == RTS_CTS) + pxmitpriv->vcs = RTS_CTS; + else + pxmitpriv->vcs = CTS_TO_SELF; + } + else + pxmitpriv->vcs = NONE_VCS; + } + + break; + + } + +_func_exit_; + +} + +void rtw_count_tx_stats(PADAPTER padapter, struct xmit_frame *pxmitframe, int sz) +{ + struct sta_info *psta = NULL; + struct stainfo_stats *pstats = NULL; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + u8 pkt_num = 1; + + if ((pxmitframe->frame_tag&0x0f) == DATA_FRAMETAG) + { +#if defined(CONFIG_USB_TX_AGGREGATION) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + pkt_num = pxmitframe->agg_num; +#endif + pmlmepriv->LinkDetectInfo.NumTxOkInPeriod += pkt_num; + + pxmitpriv->tx_pkts += pkt_num; + + pxmitpriv->tx_bytes += sz; + + psta = pxmitframe->attrib.psta; + if (psta) + { + pstats = &psta->sta_stats; + + pstats->tx_pkts += pkt_num; + + pstats->tx_bytes += sz; +#ifdef CONFIG_TDLS + if(pxmitframe->attrib.ptdls_sta != NULL) + { + pstats = &(pxmitframe->attrib.ptdls_sta->sta_stats); + pstats->tx_pkts += pkt_num; + pstats->tx_bytes += sz; + } +#endif //CONFIG_TDLS + } + +#ifdef CONFIG_CHECK_LEAVE_LPS + //traffic_check_for_leave_lps(padapter, _TRUE); +#endif //CONFIG_LPS + + } +} + +static struct xmit_buf *__rtw_alloc_cmd_xmitbuf(struct xmit_priv *pxmitpriv, + enum cmdbuf_type buf_type) +{ + struct xmit_buf *pxmitbuf = NULL; + +_func_enter_; + + pxmitbuf = &pxmitpriv->pcmd_xmitbuf[buf_type]; + if (pxmitbuf != NULL) { + pxmitbuf->priv_data = NULL; + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + pxmitbuf->len = 0; + pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead; + pxmitbuf->agg_num = 0; + pxmitbuf->pg_num = 0; +#endif +#ifdef CONFIG_PCI_HCI + pxmitbuf->len = 0; + pxmitbuf->desc = NULL; +#endif + + if (pxmitbuf->sctx) { + DBG_871X("%s pxmitbuf->sctx is not NULL\n", __func__); + rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC); + } + } else { + DBG_871X("%s fail, no xmitbuf available !!!\n", __func__); + } + +exit: + +_func_exit_; + + return pxmitbuf; +} + +struct xmit_frame *__rtw_alloc_cmdxmitframe(struct xmit_priv *pxmitpriv, + enum cmdbuf_type buf_type) +{ + struct xmit_frame *pcmdframe; + struct xmit_buf *pxmitbuf; + + if ((pcmdframe = rtw_alloc_xmitframe(pxmitpriv)) == NULL) + { + DBG_871X("%s, alloc xmitframe fail\n", __FUNCTION__); + return NULL; + } + + if ((pxmitbuf = __rtw_alloc_cmd_xmitbuf(pxmitpriv, buf_type)) == NULL) { + DBG_871X("%s, alloc xmitbuf fail\n", __FUNCTION__); + rtw_free_xmitframe(pxmitpriv, pcmdframe); + return NULL; + } + + pcmdframe->frame_tag = MGNT_FRAMETAG; + + pcmdframe->pxmitbuf = pxmitbuf; + + pcmdframe->buf_addr = pxmitbuf->pbuf; + + pxmitbuf->priv_data = pcmdframe; + + return pcmdframe; + +} + +struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv) +{ + _irqL irqL; + struct xmit_buf *pxmitbuf = NULL; + _list *plist, *phead; + _queue *pfree_queue = &pxmitpriv->free_xmit_extbuf_queue; + +_func_enter_; + + _enter_critical(&pfree_queue->lock, &irqL); + + if(_rtw_queue_empty(pfree_queue) == _TRUE) { + pxmitbuf = NULL; + } else { + + phead = get_list_head(pfree_queue); + + plist = get_next(phead); + + pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list); + + rtw_list_delete(&(pxmitbuf->list)); + } + + if (pxmitbuf != NULL) + { + pxmitpriv->free_xmit_extbuf_cnt--; + #ifdef DBG_XMIT_BUF_EXT + DBG_871X("DBG_XMIT_BUF_EXT ALLOC no=%d, free_xmit_extbuf_cnt=%d\n",pxmitbuf->no, pxmitpriv->free_xmit_extbuf_cnt); + #endif + + + pxmitbuf->priv_data = NULL; + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + pxmitbuf->len = 0; + pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead; + pxmitbuf->agg_num = 1; +#endif +#ifdef CONFIG_PCI_HCI + pxmitbuf->len = 0; + pxmitbuf->desc = NULL; +#endif + + if (pxmitbuf->sctx) { + DBG_871X("%s pxmitbuf->sctx is not NULL\n", __func__); + rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC); + } + + } + + _exit_critical(&pfree_queue->lock, &irqL); + +_func_exit_; + + return pxmitbuf; +} + +s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) +{ + _irqL irqL; + _queue *pfree_queue = &pxmitpriv->free_xmit_extbuf_queue; + +_func_enter_; + + if(pxmitbuf==NULL) + { + return _FAIL; + } + + _enter_critical(&pfree_queue->lock, &irqL); + + rtw_list_delete(&pxmitbuf->list); + + rtw_list_insert_tail(&(pxmitbuf->list), get_list_head(pfree_queue)); + pxmitpriv->free_xmit_extbuf_cnt++; + #ifdef DBG_XMIT_BUF_EXT + DBG_871X("DBG_XMIT_BUF_EXT FREE no=%d, free_xmit_extbuf_cnt=%d\n",pxmitbuf->no ,pxmitpriv->free_xmit_extbuf_cnt); + #endif + + _exit_critical(&pfree_queue->lock, &irqL); + +_func_exit_; + + return _SUCCESS; +} + +struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv) +{ + _irqL irqL; + struct xmit_buf *pxmitbuf = NULL; + _list *plist, *phead; + _queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue; + +_func_enter_; + + //DBG_871X("+rtw_alloc_xmitbuf\n"); + + _enter_critical(&pfree_xmitbuf_queue->lock, &irqL); + + if(_rtw_queue_empty(pfree_xmitbuf_queue) == _TRUE) { + pxmitbuf = NULL; + } else { + + phead = get_list_head(pfree_xmitbuf_queue); + + plist = get_next(phead); + + pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list); + + rtw_list_delete(&(pxmitbuf->list)); + } + + if (pxmitbuf != NULL) + { + pxmitpriv->free_xmitbuf_cnt--; + #ifdef DBG_XMIT_BUF + DBG_871X("DBG_XMIT_BUF ALLOC no=%d, free_xmitbuf_cnt=%d\n",pxmitbuf->no, pxmitpriv->free_xmitbuf_cnt); + #endif + //DBG_871X("alloc, free_xmitbuf_cnt=%d\n", pxmitpriv->free_xmitbuf_cnt); + + pxmitbuf->priv_data = NULL; + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + pxmitbuf->len = 0; + pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead; + pxmitbuf->agg_num = 0; + pxmitbuf->pg_num = 0; +#endif +#ifdef CONFIG_PCI_HCI + pxmitbuf->len = 0; + pxmitbuf->desc = NULL; +#endif + + if (pxmitbuf->sctx) { + DBG_871X("%s pxmitbuf->sctx is not NULL\n", __func__); + rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_ALLOC); + } + } + #ifdef DBG_XMIT_BUF + else + { + DBG_871X("DBG_XMIT_BUF rtw_alloc_xmitbuf return NULL\n"); + } + #endif + + _exit_critical(&pfree_xmitbuf_queue->lock, &irqL); + +_func_exit_; + + return pxmitbuf; +} + +s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) +{ + _irqL irqL; + _queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue; + +_func_enter_; + + //DBG_871X("+rtw_free_xmitbuf\n"); + + if(pxmitbuf==NULL) + { + return _FAIL; + } + + if (pxmitbuf->sctx) { + DBG_871X("%s pxmitbuf->sctx is not NULL\n", __func__); + rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_BUF_FREE); + } + + if(pxmitbuf->buf_tag == XMITBUF_CMD) { + } + else if(pxmitbuf->buf_tag == XMITBUF_MGNT) { + rtw_free_xmitbuf_ext(pxmitpriv, pxmitbuf); + } + else + { + _enter_critical(&pfree_xmitbuf_queue->lock, &irqL); + + rtw_list_delete(&pxmitbuf->list); + + rtw_list_insert_tail(&(pxmitbuf->list), get_list_head(pfree_xmitbuf_queue)); + + pxmitpriv->free_xmitbuf_cnt++; + //DBG_871X("FREE, free_xmitbuf_cnt=%d\n", pxmitpriv->free_xmitbuf_cnt); + #ifdef DBG_XMIT_BUF + DBG_871X("DBG_XMIT_BUF FREE no=%d, free_xmitbuf_cnt=%d\n",pxmitbuf->no ,pxmitpriv->free_xmitbuf_cnt); + #endif + _exit_critical(&pfree_xmitbuf_queue->lock, &irqL); + } + +_func_exit_; + + return _SUCCESS; +} + +void rtw_init_xmitframe(struct xmit_frame *pxframe) +{ + if (pxframe != NULL)//default value setting + { + pxframe->buf_addr = NULL; + pxframe->pxmitbuf = NULL; + + _rtw_memset(&pxframe->attrib, 0, sizeof(struct pkt_attrib)); + //pxframe->attrib.psta = NULL; + + pxframe->frame_tag = DATA_FRAMETAG; + +#ifdef CONFIG_USB_HCI + pxframe->pkt = NULL; +#ifdef USB_PACKET_OFFSET_SZ + pxframe->pkt_offset = (PACKET_OFFSET_SZ/8); +#else + pxframe->pkt_offset = 1;//default use pkt_offset to fill tx desc +#endif + +#ifdef CONFIG_USB_TX_AGGREGATION + pxframe->agg_num = 1; +#endif + +#endif //#ifdef CONFIG_USB_HCI + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + pxframe->pg_num = 1; + pxframe->agg_num = 1; +#endif + +#ifdef CONFIG_XMIT_ACK + pxframe->ack_report = 0; +#endif + + } +} + +/* +Calling context: +1. OS_TXENTRY +2. RXENTRY (rx_thread or RX_ISR/RX_CallBack) + +If we turn on USE_RXTHREAD, then, no need for critical section. +Otherwise, we must use _enter/_exit critical to protect free_xmit_queue... + +Must be very very cautious... + +*/ +struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv)//(_queue *pfree_xmit_queue) +{ + /* + Please remember to use all the osdep_service api, + and lock/unlock or _enter/_exit critical to protect + pfree_xmit_queue + */ + + _irqL irqL; + struct xmit_frame *pxframe = NULL; + _list *plist, *phead; + _queue *pfree_xmit_queue = &pxmitpriv->free_xmit_queue; + +_func_enter_; + + _enter_critical_bh(&pfree_xmit_queue->lock, &irqL); + + if (_rtw_queue_empty(pfree_xmit_queue) == _TRUE) { + RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_alloc_xmitframe:%d\n", pxmitpriv->free_xmitframe_cnt)); + pxframe = NULL; + } else { + phead = get_list_head(pfree_xmit_queue); + + plist = get_next(phead); + + pxframe = LIST_CONTAINOR(plist, struct xmit_frame, list); + + rtw_list_delete(&(pxframe->list)); + pxmitpriv->free_xmitframe_cnt--; + RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_alloc_xmitframe():free_xmitframe_cnt=%d\n", pxmitpriv->free_xmitframe_cnt)); + } + + _exit_critical_bh(&pfree_xmit_queue->lock, &irqL); + + rtw_init_xmitframe(pxframe); + +_func_exit_; + + return pxframe; +} + +struct xmit_frame *rtw_alloc_xmitframe_ext(struct xmit_priv *pxmitpriv) +{ + _irqL irqL; + struct xmit_frame *pxframe = NULL; + _list *plist, *phead; + _queue *queue = &pxmitpriv->free_xframe_ext_queue; + +_func_enter_; + + _enter_critical_bh(&queue->lock, &irqL); + + if (_rtw_queue_empty(queue) == _TRUE) { + RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_alloc_xmitframe_ext:%d\n", pxmitpriv->free_xframe_ext_cnt)); + pxframe = NULL; + } else { + phead = get_list_head(queue); + plist = get_next(phead); + pxframe = LIST_CONTAINOR(plist, struct xmit_frame, list); + + rtw_list_delete(&(pxframe->list)); + pxmitpriv->free_xframe_ext_cnt--; + RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_alloc_xmitframe_ext():free_xmitframe_cnt=%d\n", pxmitpriv->free_xframe_ext_cnt)); + } + + _exit_critical_bh(&queue->lock, &irqL); + + rtw_init_xmitframe(pxframe); + +_func_exit_; + + return pxframe; +} + +struct xmit_frame *rtw_alloc_xmitframe_once(struct xmit_priv *pxmitpriv) +{ + struct xmit_frame *pxframe = NULL; + u8 *alloc_addr; + + alloc_addr = rtw_zmalloc(sizeof(struct xmit_frame) + 4); + + if (alloc_addr == NULL) + goto exit; + + pxframe = (struct xmit_frame *)N_BYTE_ALIGMENT((SIZE_PTR)(alloc_addr), 4); + pxframe->alloc_addr = alloc_addr; + + pxframe->padapter = pxmitpriv->adapter; + pxframe->frame_tag = NULL_FRAMETAG; + + pxframe->pkt = NULL; + + pxframe->buf_addr = NULL; + pxframe->pxmitbuf = NULL; + + rtw_init_xmitframe(pxframe); + + DBG_871X("################## %s ##################\n", __func__); + +exit: + return pxframe; +} + +s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe) +{ + _irqL irqL; + _queue *queue = NULL; + _adapter *padapter = pxmitpriv->adapter; + _pkt *pndis_pkt = NULL; + +_func_enter_; + + if (pxmitframe == NULL) { + RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("======rtw_free_xmitframe():pxmitframe==NULL!!!!!!!!!!\n")); + goto exit; + } + + if (pxmitframe->pkt){ + pndis_pkt = pxmitframe->pkt; + pxmitframe->pkt = NULL; + } + + if (pxmitframe->alloc_addr) { + DBG_871X("################## %s with alloc_addr ##################\n", __func__); + rtw_mfree(pxmitframe->alloc_addr, sizeof(struct xmit_frame) + 4); + goto check_pkt_complete; + } + + if (pxmitframe->ext_tag == 0) + queue = &pxmitpriv->free_xmit_queue; + else if(pxmitframe->ext_tag == 1) + queue = &pxmitpriv->free_xframe_ext_queue; + else + rtw_warn_on(1); + + _enter_critical_bh(&queue->lock, &irqL); + + rtw_list_delete(&pxmitframe->list); + rtw_list_insert_tail(&pxmitframe->list, get_list_head(queue)); + if (pxmitframe->ext_tag == 0) { + pxmitpriv->free_xmitframe_cnt++; + RT_TRACE(_module_rtl871x_xmit_c_, _drv_debug_, ("rtw_free_xmitframe():free_xmitframe_cnt=%d\n", pxmitpriv->free_xmitframe_cnt)); + } else if(pxmitframe->ext_tag == 1) { + pxmitpriv->free_xframe_ext_cnt++; + RT_TRACE(_module_rtl871x_xmit_c_, _drv_debug_, ("rtw_free_xmitframe():free_xframe_ext_cnt=%d\n", pxmitpriv->free_xframe_ext_cnt)); + } else { + } + + _exit_critical_bh(&queue->lock, &irqL); + +check_pkt_complete: + + if(pndis_pkt) + rtw_os_pkt_complete(padapter, pndis_pkt); + +exit: + +_func_exit_; + + return _SUCCESS; +} + +void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue) +{ + _irqL irqL; + _list *plist, *phead; + struct xmit_frame *pxmitframe; + +_func_enter_; + + _enter_critical_bh(&(pframequeue->lock), &irqL); + + phead = get_list_head(pframequeue); + plist = get_next(phead); + + while (rtw_end_of_queue_search(phead, plist) == _FALSE) + { + + pxmitframe = LIST_CONTAINOR(plist, struct xmit_frame, list); + + plist = get_next(plist); + + rtw_free_xmitframe(pxmitpriv,pxmitframe); + + } + _exit_critical_bh(&(pframequeue->lock), &irqL); + +_func_exit_; +} + +s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + DBG_COUNTER(padapter->tx_logs.core_tx_enqueue); + if (rtw_xmit_classifier(padapter, pxmitframe) == _FAIL) + { + RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, + ("rtw_xmitframe_enqueue: drop xmit pkt for classifier fail\n")); +// pxmitframe->pkt = NULL; + return _FAIL; + } + + return _SUCCESS; +} + +static struct xmit_frame *dequeue_one_xmitframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit, struct tx_servq *ptxservq, _queue *pframe_queue) +{ + _list *xmitframe_plist, *xmitframe_phead; + struct xmit_frame *pxmitframe=NULL; + + xmitframe_phead = get_list_head(pframe_queue); + xmitframe_plist = get_next(xmitframe_phead); + + while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) + { + pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); + + /* xmitframe_plist = get_next(xmitframe_plist); */ + +/*#ifdef RTK_DMP_PLATFORM +#ifdef CONFIG_USB_TX_AGGREGATION + if((ptxservq->qcnt>0) && (ptxservq->qcnt<=2)) + { + pxmitframe = NULL; + + tasklet_schedule(&pxmitpriv->xmit_tasklet); + + break; + } +#endif +#endif*/ + rtw_list_delete(&pxmitframe->list); + + ptxservq->qcnt--; + + //rtw_list_insert_tail(&pxmitframe->list, &phwxmit->pending); + + //ptxservq->qcnt--; + + break; + + //pxmitframe = NULL; + + } + + return pxmitframe; +} + +struct xmit_frame* rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, sint entry) +{ + _irqL irqL0; + _list *sta_plist, *sta_phead; + struct hw_xmit *phwxmit; + struct tx_servq *ptxservq = NULL; + _queue *pframe_queue = NULL; + struct xmit_frame *pxmitframe = NULL; + _adapter *padapter = pxmitpriv->adapter; + struct registry_priv *pregpriv = &padapter->registrypriv; + int i, inx[4]; +#ifdef CONFIG_USB_HCI +// int j, tmp, acirp_cnt[4]; +#endif + +_func_enter_; + + inx[0] = 0; inx[1] = 1; inx[2] = 2; inx[3] = 3; + + if(pregpriv->wifi_spec==1) + { + int j, tmp, acirp_cnt[4]; +#if 0 + if(flagswmm_para_seq[j]; +#endif + } + + _enter_critical_bh(&pxmitpriv->lock, &irqL0); + + for(i = 0; i < entry; i++) + { + phwxmit = phwxmit_i + inx[i]; + + //_enter_critical_ex(&phwxmit->sta_queue->lock, &irqL0); + + sta_phead = get_list_head(phwxmit->sta_queue); + sta_plist = get_next(sta_phead); + + while ((rtw_end_of_queue_search(sta_phead, sta_plist)) == _FALSE) + { + + ptxservq= LIST_CONTAINOR(sta_plist, struct tx_servq, tx_pending); + + pframe_queue = &ptxservq->sta_pending; + + pxmitframe = dequeue_one_xmitframe(pxmitpriv, phwxmit, ptxservq, pframe_queue); + + if(pxmitframe) + { + phwxmit->accnt--; + + //Remove sta node when there is no pending packets. + if(_rtw_queue_empty(pframe_queue)) //must be done after get_next and before break + rtw_list_delete(&ptxservq->tx_pending); + + //_exit_critical_ex(&phwxmit->sta_queue->lock, &irqL0); + + goto exit; + } + + sta_plist = get_next(sta_plist); + + } + + //_exit_critical_ex(&phwxmit->sta_queue->lock, &irqL0); + + } + +exit: + + _exit_critical_bh(&pxmitpriv->lock, &irqL0); + +_func_exit_; + + return pxmitframe; +} + +#if 1 +struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, sint up, u8 *ac) +{ + struct tx_servq *ptxservq=NULL; + +_func_enter_; + + switch (up) + { + case 1: + case 2: + ptxservq = &(psta->sta_xmitpriv.bk_q); + *(ac) = 3; + RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : BK \n")); + break; + + case 4: + case 5: + ptxservq = &(psta->sta_xmitpriv.vi_q); + *(ac) = 1; + RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : VI\n")); + break; + + case 6: + case 7: + ptxservq = &(psta->sta_xmitpriv.vo_q); + *(ac) = 0; + RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : VO \n")); + break; + + case 0: + case 3: + default: + ptxservq = &(psta->sta_xmitpriv.be_q); + *(ac) = 2; + RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : BE \n")); + break; + + } + +_func_exit_; + + return ptxservq; +} +#else +__inline static struct tx_servq *rtw_get_sta_pending + (_adapter *padapter, _queue **ppstapending, struct sta_info *psta, sint up) +{ + struct tx_servq *ptxservq; + struct hw_xmit *phwxmits = padapter->xmitpriv.hwxmits; + +_func_enter_; + +#ifdef CONFIG_RTL8711 + + if(IS_MCAST(psta->hwaddr)) + { + ptxservq = &(psta->sta_xmitpriv.be_q); // we will use be_q to queue bc/mc frames in BCMC_stainfo + *ppstapending = &padapter->xmitpriv.bm_pending; + } + else +#endif + { + switch (up) + { + case 1: + case 2: + ptxservq = &(psta->sta_xmitpriv.bk_q); + *ppstapending = &padapter->xmitpriv.bk_pending; + (phwxmits+3)->accnt++; + RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : BK \n")); + break; + + case 4: + case 5: + ptxservq = &(psta->sta_xmitpriv.vi_q); + *ppstapending = &padapter->xmitpriv.vi_pending; + (phwxmits+1)->accnt++; + RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : VI\n")); + break; + + case 6: + case 7: + ptxservq = &(psta->sta_xmitpriv.vo_q); + *ppstapending = &padapter->xmitpriv.vo_pending; + (phwxmits+0)->accnt++; + RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : VO \n")); + break; + + case 0: + case 3: + default: + ptxservq = &(psta->sta_xmitpriv.be_q); + *ppstapending = &padapter->xmitpriv.be_pending; + (phwxmits+2)->accnt++; + RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : BE \n")); + break; + + } + + } + +_func_exit_; + + return ptxservq; +} +#endif + +/* + * Will enqueue pxmitframe to the proper queue, + * and indicate it to xx_pending list..... + */ +s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + //_irqL irqL0; + u8 ac_index; + struct sta_info *psta; + struct tx_servq *ptxservq; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct sta_priv *pstapriv = &padapter->stapriv; + struct hw_xmit *phwxmits = padapter->xmitpriv.hwxmits; + sint res = _SUCCESS; + +_func_enter_; + + DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class); + +/* + if (pattrib->psta) { + psta = pattrib->psta; + } else { + DBG_871X("%s, call rtw_get_stainfo()\n", __func__); + psta = rtw_get_stainfo(pstapriv, pattrib->ra); + } +*/ + + psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); + if(pattrib->psta != psta) + { + DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_sta); + DBG_871X("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta); + return _FAIL; + } + + if (psta == NULL) { + DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_nosta); + res = _FAIL; + DBG_8192C("rtw_xmit_classifier: psta == NULL\n"); + RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("rtw_xmit_classifier: psta == NULL\n")); + goto exit; + } + + if(!(psta->state &_FW_LINKED)) + { + DBG_COUNTER(padapter->tx_logs.core_tx_enqueue_class_err_fwlink); + DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state); + return _FAIL; + } + + ptxservq = rtw_get_sta_pending(padapter, psta, pattrib->priority, (u8 *)(&ac_index)); + + //_enter_critical(&pstapending->lock, &irqL0); + + if (rtw_is_list_empty(&ptxservq->tx_pending)) { + rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(phwxmits[ac_index].sta_queue)); + } + + //_enter_critical(&ptxservq->sta_pending.lock, &irqL1); + + rtw_list_insert_tail(&pxmitframe->list, get_list_head(&ptxservq->sta_pending)); + ptxservq->qcnt++; + phwxmits[ac_index].accnt++; + + //_exit_critical(&ptxservq->sta_pending.lock, &irqL1); + + //_exit_critical(&pstapending->lock, &irqL0); + +exit: + +_func_exit_; + + return res; +} + +void rtw_alloc_hwxmits(_adapter *padapter) +{ + struct hw_xmit *hwxmits; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + pxmitpriv->hwxmit_entry = HWXMIT_ENTRY; + + pxmitpriv->hwxmits = NULL; + + pxmitpriv->hwxmits = (struct hw_xmit *)rtw_zmalloc(sizeof (struct hw_xmit) * pxmitpriv->hwxmit_entry); + + if(pxmitpriv->hwxmits == NULL) + { + DBG_871X("alloc hwxmits fail!...\n"); + return; + } + + hwxmits = pxmitpriv->hwxmits; + + if(pxmitpriv->hwxmit_entry == 5) + { + //pxmitpriv->bmc_txqueue.head = 0; + //hwxmits[0] .phwtxqueue = &pxmitpriv->bmc_txqueue; + hwxmits[0] .sta_queue = &pxmitpriv->bm_pending; + + //pxmitpriv->vo_txqueue.head = 0; + //hwxmits[1] .phwtxqueue = &pxmitpriv->vo_txqueue; + hwxmits[1] .sta_queue = &pxmitpriv->vo_pending; + + //pxmitpriv->vi_txqueue.head = 0; + //hwxmits[2] .phwtxqueue = &pxmitpriv->vi_txqueue; + hwxmits[2] .sta_queue = &pxmitpriv->vi_pending; + + //pxmitpriv->bk_txqueue.head = 0; + //hwxmits[3] .phwtxqueue = &pxmitpriv->bk_txqueue; + hwxmits[3] .sta_queue = &pxmitpriv->bk_pending; + + //pxmitpriv->be_txqueue.head = 0; + //hwxmits[4] .phwtxqueue = &pxmitpriv->be_txqueue; + hwxmits[4] .sta_queue = &pxmitpriv->be_pending; + + } + else if(pxmitpriv->hwxmit_entry == 4) + { + + //pxmitpriv->vo_txqueue.head = 0; + //hwxmits[0] .phwtxqueue = &pxmitpriv->vo_txqueue; + hwxmits[0] .sta_queue = &pxmitpriv->vo_pending; + + //pxmitpriv->vi_txqueue.head = 0; + //hwxmits[1] .phwtxqueue = &pxmitpriv->vi_txqueue; + hwxmits[1] .sta_queue = &pxmitpriv->vi_pending; + + //pxmitpriv->be_txqueue.head = 0; + //hwxmits[2] .phwtxqueue = &pxmitpriv->be_txqueue; + hwxmits[2] .sta_queue = &pxmitpriv->be_pending; + + //pxmitpriv->bk_txqueue.head = 0; + //hwxmits[3] .phwtxqueue = &pxmitpriv->bk_txqueue; + hwxmits[3] .sta_queue = &pxmitpriv->bk_pending; + } + else + { + + + } + + +} + +void rtw_free_hwxmits(_adapter *padapter) +{ + struct hw_xmit *hwxmits; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + hwxmits = pxmitpriv->hwxmits; + if(hwxmits) + rtw_mfree((u8 *)hwxmits, (sizeof (struct hw_xmit) * pxmitpriv->hwxmit_entry)); +} + +void rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry) +{ + sint i; +_func_enter_; + for(i = 0; i < entry; i++, phwxmit++) + { + //_rtw_spinlock_init(&phwxmit->xmit_lock); + //_rtw_init_listhead(&phwxmit->pending); + //phwxmit->txcmdcnt = 0; + phwxmit->accnt = 0; + } +_func_exit_; +} + +#ifdef CONFIG_BR_EXT +int rtw_br_client_tx(_adapter *padapter, struct sk_buff **pskb) +{ + struct sk_buff *skb = *pskb; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + _irqL irqL; + //if(check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) + { + void dhcp_flag_bcast(_adapter *priv, struct sk_buff *skb); + int res, is_vlan_tag=0, i, do_nat25=1; + unsigned short vlan_hdr=0; + void *br_port = NULL; + + //mac_clone_handle_frame(priv, skb); + +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) + br_port = padapter->pnetdev->br_port; +#else // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) + rcu_read_lock(); + br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); + rcu_read_unlock(); +#endif // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) + _enter_critical_bh(&padapter->br_ext_lock, &irqL); + if ( !(skb->data[0] & 1) && + br_port && + memcmp(skb->data+MACADDRLEN, padapter->br_mac, MACADDRLEN) && + *((unsigned short *)(skb->data+MACADDRLEN*2)) != __constant_htons(ETH_P_8021Q) && + *((unsigned short *)(skb->data+MACADDRLEN*2)) == __constant_htons(ETH_P_IP) && + !memcmp(padapter->scdb_mac, skb->data+MACADDRLEN, MACADDRLEN) && padapter->scdb_entry) { + memcpy(skb->data+MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN); + padapter->scdb_entry->ageing_timer = jiffies; + _exit_critical_bh(&padapter->br_ext_lock, &irqL); + } + else + //if (!priv->pmib->ethBrExtInfo.nat25_disable) + { +// if (priv->dev->br_port && +// !memcmp(skb->data+MACADDRLEN, priv->br_mac, MACADDRLEN)) { +#if 1 + if (*((unsigned short *)(skb->data+MACADDRLEN*2)) == __constant_htons(ETH_P_8021Q)) { + is_vlan_tag = 1; + vlan_hdr = *((unsigned short *)(skb->data+MACADDRLEN*2+2)); + for (i=0; i<6; i++) + *((unsigned short *)(skb->data+MACADDRLEN*2+2-i*2)) = *((unsigned short *)(skb->data+MACADDRLEN*2-2-i*2)); + skb_pull(skb, 4); + } + //if SA == br_mac && skb== IP => copy SIP to br_ip ?? why + if (!memcmp(skb->data+MACADDRLEN, padapter->br_mac, MACADDRLEN) && + (*((unsigned short *)(skb->data+MACADDRLEN*2)) == __constant_htons(ETH_P_IP))) + memcpy(padapter->br_ip, skb->data+WLAN_ETHHDR_LEN+12, 4); + + if (*((unsigned short *)(skb->data+MACADDRLEN*2)) == __constant_htons(ETH_P_IP)) { + if (memcmp(padapter->scdb_mac, skb->data+MACADDRLEN, MACADDRLEN)) { + void *scdb_findEntry(_adapter *priv, unsigned char *macAddr, unsigned char *ipAddr); + + if ((padapter->scdb_entry = (struct nat25_network_db_entry *)scdb_findEntry(padapter, + skb->data+MACADDRLEN, skb->data+WLAN_ETHHDR_LEN+12)) != NULL) { + memcpy(padapter->scdb_mac, skb->data+MACADDRLEN, MACADDRLEN); + memcpy(padapter->scdb_ip, skb->data+WLAN_ETHHDR_LEN+12, 4); + padapter->scdb_entry->ageing_timer = jiffies; + do_nat25 = 0; + } + } + else { + if (padapter->scdb_entry) { + padapter->scdb_entry->ageing_timer = jiffies; + do_nat25 = 0; + } + else { + memset(padapter->scdb_mac, 0, MACADDRLEN); + memset(padapter->scdb_ip, 0, 4); + } + } + } + _exit_critical_bh(&padapter->br_ext_lock, &irqL); +#endif // 1 + if (do_nat25) + { + int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method); + if (nat25_db_handle(padapter, skb, NAT25_CHECK) == 0) { + struct sk_buff *newskb; + + if (is_vlan_tag) { + skb_push(skb, 4); + for (i=0; i<6; i++) + *((unsigned short *)(skb->data+i*2)) = *((unsigned short *)(skb->data+4+i*2)); + *((unsigned short *)(skb->data+MACADDRLEN*2)) = __constant_htons(ETH_P_8021Q); + *((unsigned short *)(skb->data+MACADDRLEN*2+2)) = vlan_hdr; + } + + newskb = rtw_skb_copy(skb); + if (newskb == NULL) { + //priv->ext_stats.tx_drops++; + DEBUG_ERR("TX DROP: rtw_skb_copy fail!\n"); + //goto stop_proc; + return -1; + } + rtw_skb_free(skb); + + *pskb = skb = newskb; + if (is_vlan_tag) { + vlan_hdr = *((unsigned short *)(skb->data+MACADDRLEN*2+2)); + for (i=0; i<6; i++) + *((unsigned short *)(skb->data+MACADDRLEN*2+2-i*2)) = *((unsigned short *)(skb->data+MACADDRLEN*2-2-i*2)); + skb_pull(skb, 4); + } + } + + if (skb_is_nonlinear(skb)) + DEBUG_ERR("%s(): skb_is_nonlinear!!\n", __FUNCTION__); + + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) + res = skb_linearize(skb, GFP_ATOMIC); +#else // (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) + res = skb_linearize(skb); +#endif // (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) + if (res < 0) { + DEBUG_ERR("TX DROP: skb_linearize fail!\n"); + //goto free_and_stop; + return -1; + } + + res = nat25_db_handle(padapter, skb, NAT25_INSERT); + if (res < 0) { + if (res == -2) { + //priv->ext_stats.tx_drops++; + DEBUG_ERR("TX DROP: nat25_db_handle fail!\n"); + //goto free_and_stop; + return -1; + + } + // we just print warning message and let it go + //DEBUG_WARN("%s()-%d: nat25_db_handle INSERT Warning!\n", __FUNCTION__, __LINE__); + //return -1; // return -1 will cause system crash on 2011/08/30! + return 0; + } + } + + memcpy(skb->data+MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN); + + dhcp_flag_bcast(padapter, skb); + + if (is_vlan_tag) { + skb_push(skb, 4); + for (i=0; i<6; i++) + *((unsigned short *)(skb->data+i*2)) = *((unsigned short *)(skb->data+4+i*2)); + *((unsigned short *)(skb->data+MACADDRLEN*2)) = __constant_htons(ETH_P_8021Q); + *((unsigned short *)(skb->data+MACADDRLEN*2+2)) = vlan_hdr; + } + } +#if 0 + else{ + if (*((unsigned short *)(skb->data+MACADDRLEN*2)) == __constant_htons(ETH_P_8021Q)) { + is_vlan_tag = 1; + } + + if(is_vlan_tag){ + if(ICMPV6_MCAST_MAC(skb->data) && ICMPV6_PROTO1A_VALN(skb->data)){ + memcpy(skb->data+MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN); + } + }else + { + if(ICMPV6_MCAST_MAC(skb->data) && ICMPV6_PROTO1A(skb->data)){ + memcpy(skb->data+MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN); + } + } + } +#endif // 0 + + // check if SA is equal to our MAC + if (memcmp(skb->data+MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN)) { + //priv->ext_stats.tx_drops++; + DEBUG_ERR("TX DROP: untransformed frame SA:%02X%02X%02X%02X%02X%02X!\n", + skb->data[6],skb->data[7],skb->data[8],skb->data[9],skb->data[10],skb->data[11]); + //goto free_and_stop; + return -1; + } + } + return 0; +} +#endif // CONFIG_BR_EXT + +u32 rtw_get_ff_hwaddr(struct xmit_frame *pxmitframe) +{ + u32 addr; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + + switch(pattrib->qsel) + { + case 0: + case 3: + addr = BE_QUEUE_INX; + break; + case 1: + case 2: + addr = BK_QUEUE_INX; + break; + case 4: + case 5: + addr = VI_QUEUE_INX; + break; + case 6: + case 7: + addr = VO_QUEUE_INX; + break; + case 0x10: + addr = BCN_QUEUE_INX; + break; + case 0x11://BC/MC in PS (HIQ) + addr = HIGH_QUEUE_INX; + break; + case 0x12: + default: + addr = MGT_QUEUE_INX; + break; + + } + + return addr; + +} + +static void do_queue_select(_adapter *padapter, struct pkt_attrib *pattrib) +{ + u8 qsel; + + qsel = pattrib->priority; + RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("### do_queue_select priority=%d ,qsel = %d\n",pattrib->priority ,qsel)); + +#ifdef CONFIG_CONCURRENT_MODE +// if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) +// qsel = 7;// +#endif + + pattrib->qsel = qsel; +} + +/* + * The main transmit(tx) entry + * + * Return + * 1 enqueue + * 0 success, hardware will handle this xmit frame(packet) + * <0 fail + */ +s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev) +{ + int ret = 0; + int rtap_len; + int qos_len = 0; + int dot11_hdr_len = 24; + int snap_len = 6; + unsigned char *pdata; + u16 frame_ctl; + unsigned char src_mac_addr[6]; + unsigned char dst_mac_addr[6]; + struct rtw_ieee80211_hdr *dot11_hdr; + struct ieee80211_radiotap_header *rtap_hdr; + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + + if (skb) + rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, skb->truesize); + + if (unlikely(skb->len < sizeof(struct ieee80211_radiotap_header))) + goto fail; + + rtap_hdr = (struct ieee80211_radiotap_header *)skb->data; + if (unlikely(rtap_hdr->it_version)) + goto fail; + + rtap_len = ieee80211_get_radiotap_len(skb->data); + if (unlikely(skb->len < rtap_len)) + goto fail; + + if (rtap_len != 12) { + DBG_8192C("radiotap len (should be 14): %d\n", rtap_len); + goto fail; + } + + /* Skip the ratio tap header */ + skb_pull(skb, rtap_len); + + dot11_hdr = (struct rtw_ieee80211_hdr *)skb->data; + frame_ctl = le16_to_cpu(dot11_hdr->frame_ctl); + /* Check if the QoS bit is set */ + + if ((frame_ctl & RTW_IEEE80211_FCTL_FTYPE) == RTW_IEEE80211_FTYPE_DATA) { + + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + u8 *buf = skb->data; + u32 len = skb->len; + u8 category, action; + int type = -1; + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) { + rtw_udelay_os(500); + goto fail; + } + pattrib = &pmgntframe->attrib; + + update_monitor_frame_attrib(padapter, pattrib); + + pattrib->retry_ctrl = _FALSE; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + + _rtw_memcpy(pframe, (void *)buf, len); + + pattrib->pktlen = len; + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + if (is_broadcast_mac_addr(pwlanhdr->addr3) || is_broadcast_mac_addr(pwlanhdr->addr1)) + pattrib->rate = MGN_24M; + + pmlmeext->mgnt_seq = GetSequence(pwlanhdr); + pattrib->seqnum = pmlmeext->mgnt_seq; + pmlmeext->mgnt_seq++; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + + } else { + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + u8 *buf = skb->data; + u32 len = skb->len; + u8 category, action; + int type = -1; + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + if (pmgntframe == NULL) + goto fail; + + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + pattrib->retry_ctrl = _FALSE; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + + _rtw_memcpy(pframe, (void *)buf, len); + + pattrib->pktlen = len; + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + pmlmeext->mgnt_seq = GetSequence(pwlanhdr); + pattrib->seqnum = pmlmeext->mgnt_seq; + pmlmeext->mgnt_seq++; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + + } + +fail: + + rtw_skb_free(skb); + + return 0; +} + +/* + * The main transmit(tx) entry + * + * Return + * 1 enqueue + * 0 success, hardware will handle this xmit frame(packet) + * <0 fail + */ +s32 rtw_xmit(_adapter *padapter, _pkt **ppkt) +{ + static u32 start = 0; + static u32 drop_cnt = 0; +#ifdef CONFIG_AP_MODE + _irqL irqL0; +#endif + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct xmit_frame *pxmitframe = NULL; +#ifdef CONFIG_BR_EXT + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + void *br_port = NULL; +#endif // CONFIG_BR_EXT + + s32 res; + + DBG_COUNTER(padapter->tx_logs.core_tx); + + if (start == 0) + start = rtw_get_current_time(); + + pxmitframe = rtw_alloc_xmitframe(pxmitpriv); + + if (rtw_get_passing_time_ms(start) > 2000) { + if (drop_cnt) + DBG_871X("DBG_TX_DROP_FRAME %s no more pxmitframe, drop_cnt:%u\n", __FUNCTION__, drop_cnt); + start = rtw_get_current_time(); + drop_cnt = 0; + } + + if (pxmitframe == NULL) { + drop_cnt ++; + RT_TRACE(_module_xmit_osdep_c_, _drv_err_, ("rtw_xmit: no more pxmitframe\n")); + DBG_COUNTER(padapter->tx_logs.core_tx_err_pxmitframe); + return -1; + } + +#ifdef CONFIG_BR_EXT + +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) + br_port = padapter->pnetdev->br_port; +#else // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) + rcu_read_lock(); + br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); + rcu_read_unlock(); +#endif // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) + + if( br_port && check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) + { + res = rtw_br_client_tx(padapter, ppkt); + if (res == -1) + { + rtw_free_xmitframe(pxmitpriv, pxmitframe); + DBG_COUNTER(padapter->tx_logs.core_tx_err_brtx); + return -1; + } + } + +#endif // CONFIG_BR_EXT + + res = update_attrib(padapter, *ppkt, &pxmitframe->attrib); + +#ifdef CONFIG_WAPI_SUPPORT + if(pxmitframe->attrib.ether_type != 0x88B4) + { + if(rtw_wapi_drop_for_key_absent(padapter, pxmitframe->attrib.ra)) + { + WAPI_TRACE(WAPI_RX,"drop for key absend when tx \n"); + res = _FAIL; + } + } +#endif + if (res == _FAIL) { + RT_TRACE(_module_xmit_osdep_c_, _drv_err_, ("rtw_xmit: update attrib fail\n")); + #ifdef DBG_TX_DROP_FRAME + DBG_871X("DBG_TX_DROP_FRAME %s update attrib fail\n", __FUNCTION__); + #endif + rtw_free_xmitframe(pxmitpriv, pxmitframe); + return -1; + } + pxmitframe->pkt = *ppkt; + + rtw_led_control(padapter, LED_CTL_TX); + + do_queue_select(padapter, &pxmitframe->attrib); + +#ifdef CONFIG_AP_MODE + _enter_critical_bh(&pxmitpriv->lock, &irqL0); + if(xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe) == _TRUE) + { + _exit_critical_bh(&pxmitpriv->lock, &irqL0); + DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue); + return 1; + } + _exit_critical_bh(&pxmitpriv->lock, &irqL0); +#endif + + //pre_xmitframe + if (rtw_hal_xmit(padapter, pxmitframe) == _FALSE) + return 1; + + return 0; +} + +#ifdef CONFIG_TDLS +sint xmitframe_enqueue_for_tdls_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + sint ret=_FALSE; + + _irqL irqL; + struct sta_info *ptdls_sta=NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + int i; + + ptdls_sta=rtw_get_stainfo(pstapriv, pattrib->dst); + if(ptdls_sta==NULL){ + return ret; + }else if(ptdls_sta->tdls_sta_state&TDLS_LINKED_STATE){ + + if(pattrib->triggered==1) + { + ret = _TRUE; + return ret; + } + + _enter_critical_bh(&ptdls_sta->sleep_q.lock, &irqL); + + if(ptdls_sta->state&WIFI_SLEEP_STATE) + { + rtw_list_delete(&pxmitframe->list); + + //_enter_critical_bh(&psta->sleep_q.lock, &irqL); + + rtw_list_insert_tail(&pxmitframe->list, get_list_head(&ptdls_sta->sleep_q)); + + ptdls_sta->sleepq_len++; + ptdls_sta->sleepq_ac_len++; + + //indicate 4-AC queue bit in TDLS peer traffic indication + switch(pattrib->priority) + { + case 1: + case 2: + ptdls_sta->uapsd_bk |= BIT(1); + break; + case 4: + case 5: + ptdls_sta->uapsd_vi |= BIT(1); + break; + case 6: + case 7: + ptdls_sta->uapsd_vo |= BIT(1); + break; + case 0: + case 3: + default: + ptdls_sta->uapsd_be |= BIT(1); + break; + } + + /* Transmit TDLS PTI via AP */ + if(ptdls_sta->sleepq_len==1) + rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_ISSUE_PTI); + + ret = _TRUE; + } + + _exit_critical_bh(&ptdls_sta->sleep_q.lock, &irqL); + } + + return ret; + +} +#endif //CONFIG_TDLS + +#define RTW_HIQ_FILTER_ALLOW_ALL 0 +#define RTW_HIQ_FILTER_ALLOW_SPECIAL 1 +#define RTW_HIQ_FILTER_DENY_ALL 2 + +inline bool xmitframe_hiq_filter(struct xmit_frame *xmitframe) +{ + bool allow = _FALSE; + _adapter *adapter = xmitframe->padapter; + struct registry_priv *registry = &adapter->registrypriv; + +if (rtw_get_intf_type(adapter) != RTW_PCIE) { + + if (adapter->registrypriv.wifi_spec == 1) { + allow = _TRUE; + } else if (registry->hiq_filter == RTW_HIQ_FILTER_ALLOW_SPECIAL) { + + struct pkt_attrib *attrib = &xmitframe->attrib; + + if (attrib->ether_type == 0x0806 + || attrib->ether_type == 0x888e + #ifdef CONFIG_WAPI_SUPPORT + || attrib->ether_type == 0x88B4 + #endif + || attrib->dhcp_pkt + ) { + if (0) + DBG_871X(FUNC_ADPT_FMT" ether_type:0x%04x%s\n", FUNC_ADPT_ARG(xmitframe->padapter) + , attrib->ether_type, attrib->dhcp_pkt?" DHCP":""); + allow = _TRUE; + } + } + else if (registry->hiq_filter == RTW_HIQ_FILTER_ALLOW_ALL) { + allow = _TRUE; + } + else if (registry->hiq_filter == RTW_HIQ_FILTER_DENY_ALL) { + } + else { + rtw_warn_on(1); + } +} + return allow; +} + +#if defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS) + +sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + _irqL irqL; + sint ret=_FALSE; + struct sta_info *psta=NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + sint bmcst = IS_MCAST(pattrib->ra); + bool update_tim = _FALSE; +#ifdef CONFIG_TDLS + + if( padapter->tdlsinfo.link_established == _TRUE ) + { + ret = xmitframe_enqueue_for_tdls_sleeping_sta(padapter, pxmitframe); + } +#endif //CONFIG_TDLS + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _FALSE) + { + DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_fwstate); + return ret; + } +/* + if(pattrib->psta) + { + psta = pattrib->psta; + } + else + { + DBG_871X("%s, call rtw_get_stainfo()\n", __func__); + psta=rtw_get_stainfo(pstapriv, pattrib->ra); + } +*/ + psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); + if(pattrib->psta != psta) + { + DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_sta); + DBG_871X("%s, pattrib->psta(%p) != psta(%p)\n", __func__, pattrib->psta, psta); + return _FALSE; + } + + if(psta==NULL) + { + DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_nosta); + DBG_871X("%s, psta==NUL\n", __func__); + return _FALSE; + } + + if(!(psta->state &_FW_LINKED)) + { + DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_link); + DBG_871X("%s, psta->state(0x%x) != _FW_LINKED\n", __func__, psta->state); + return _FALSE; + } + + if(pattrib->triggered==1) + { + DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_warn_trigger); + //DBG_871X("directly xmit pspoll_triggered packet\n"); + + //pattrib->triggered=0; + if (bmcst && xmitframe_hiq_filter(pxmitframe) == _TRUE) + pattrib->qsel = QSLT_HIGH;//HIQ + + return ret; + } + + + if(bmcst) + { + _enter_critical_bh(&psta->sleep_q.lock, &irqL); + + if(pstapriv->sta_dz_bitmap)//if anyone sta is in ps mode + { + //pattrib->qsel = QSLT_HIGH;//HIQ + + rtw_list_delete(&pxmitframe->list); + + /*_enter_critical_bh(&psta->sleep_q.lock, &irqL);*/ + + rtw_list_insert_tail(&pxmitframe->list, get_list_head(&psta->sleep_q)); + + psta->sleepq_len++; + + if (!(pstapriv->tim_bitmap & BIT(0))) + update_tim = _TRUE; + + pstapriv->tim_bitmap |= BIT(0);// + pstapriv->sta_dz_bitmap |= BIT(0); + + //DBG_871X("enqueue, sq_len=%d, tim=%x\n", psta->sleepq_len, pstapriv->tim_bitmap); + if (update_tim == _TRUE) { + if (is_broadcast_mac_addr(pattrib->ra)) + _update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "buffer BC"); + else + _update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "buffer MC"); + } else { + chk_bmc_sleepq_cmd(padapter); + } + + /*_exit_critical_bh(&psta->sleep_q.lock, &irqL);*/ + + ret = _TRUE; + + DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_mcast); + + } + + _exit_critical_bh(&psta->sleep_q.lock, &irqL); + + return ret; + + } + + + _enter_critical_bh(&psta->sleep_q.lock, &irqL); + + if(psta->state&WIFI_SLEEP_STATE) + { + u8 wmmps_ac=0; + + if(pstapriv->sta_dz_bitmap&BIT(psta->aid)) + { + rtw_list_delete(&pxmitframe->list); + + //_enter_critical_bh(&psta->sleep_q.lock, &irqL); + + rtw_list_insert_tail(&pxmitframe->list, get_list_head(&psta->sleep_q)); + + psta->sleepq_len++; + + switch(pattrib->priority) + { + case 1: + case 2: + wmmps_ac = psta->uapsd_bk&BIT(0); + break; + case 4: + case 5: + wmmps_ac = psta->uapsd_vi&BIT(0); + break; + case 6: + case 7: + wmmps_ac = psta->uapsd_vo&BIT(0); + break; + case 0: + case 3: + default: + wmmps_ac = psta->uapsd_be&BIT(0); + break; + } + + if(wmmps_ac) + psta->sleepq_ac_len++; + + if(((psta->has_legacy_ac) && (!wmmps_ac)) ||((!psta->has_legacy_ac)&&(wmmps_ac))) + { + if (!(pstapriv->tim_bitmap & BIT(psta->aid))) + update_tim = _TRUE; + + pstapriv->tim_bitmap |= BIT(psta->aid); + + //DBG_871X("enqueue, sq_len=%d, tim=%x\n", psta->sleepq_len, pstapriv->tim_bitmap); + + if(update_tim == _TRUE) + { + //DBG_871X("sleepq_len==1, update BCNTIM\n"); + //upate BCN for TIM IE + _update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "buffer UC"); + } + } + + //_exit_critical_bh(&psta->sleep_q.lock, &irqL); + + //if(psta->sleepq_len > (NR_XMITFRAME>>3)) + //{ + // wakeup_sta_to_xmit(padapter, psta); + //} + + ret = _TRUE; + + DBG_COUNTER(padapter->tx_logs.core_tx_ap_enqueue_ucast); + } + + } + + _exit_critical_bh(&psta->sleep_q.lock, &irqL); + + return ret; + +} + +static void dequeue_xmitframes_to_sleeping_queue(_adapter *padapter, struct sta_info *psta, _queue *pframequeue) +{ + sint ret; + _list *plist, *phead; + u8 ac_index; + struct tx_servq *ptxservq; + struct pkt_attrib *pattrib; + struct xmit_frame *pxmitframe; + struct hw_xmit *phwxmits = padapter->xmitpriv.hwxmits; + + phead = get_list_head(pframequeue); + plist = get_next(phead); + + while (rtw_end_of_queue_search(phead, plist) == _FALSE) + { + pxmitframe = LIST_CONTAINOR(plist, struct xmit_frame, list); + + plist = get_next(plist); + + pattrib = &pxmitframe->attrib; + + pattrib->triggered = 0; + + ret = xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe); + + if(_TRUE == ret) + { + ptxservq = rtw_get_sta_pending(padapter, psta, pattrib->priority, (u8 *)(&ac_index)); + + ptxservq->qcnt--; + phwxmits[ac_index].accnt--; + } + else + { + //DBG_871X("xmitframe_enqueue_for_sleeping_sta return _FALSE\n"); + } + + } + +} + +void stop_sta_xmit(_adapter *padapter, struct sta_info *psta) +{ + _irqL irqL0; + struct sta_info *psta_bmc; + struct sta_xmit_priv *pstaxmitpriv; + struct sta_priv *pstapriv = &padapter->stapriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + pstaxmitpriv = &psta->sta_xmitpriv; + + //for BC/MC Frames + psta_bmc = rtw_get_bcmc_stainfo(padapter); + + + _enter_critical_bh(&pxmitpriv->lock, &irqL0); + + psta->state |= WIFI_SLEEP_STATE; + +#ifdef CONFIG_TDLS + if( !(psta->tdls_sta_state & TDLS_LINKED_STATE) ) +#endif //CONFIG_TDLS + pstapriv->sta_dz_bitmap |= BIT(psta->aid); + + + + dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->vo_q.sta_pending); + rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending)); + + + dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->vi_q.sta_pending); + rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending)); + + + dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->be_q.sta_pending); + rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending)); + + + dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->bk_q.sta_pending); + rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending)); + +#ifdef CONFIG_TDLS + if (!(psta->tdls_sta_state & TDLS_LINKED_STATE) && (psta_bmc != NULL)) { +#endif //CONFIG_TDLS + + + //for BC/MC Frames + pstaxmitpriv = &psta_bmc->sta_xmitpriv; + dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->be_q.sta_pending); + rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending)); + + +#ifdef CONFIG_TDLS + } +#endif //CONFIG_TDLS + _exit_critical_bh(&pxmitpriv->lock, &irqL0); + + +} + +void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta) +{ + _irqL irqL; + u8 update_mask=0, wmmps_ac=0; + struct sta_info *psta_bmc; + _list *xmitframe_plist, *xmitframe_phead; + struct xmit_frame *pxmitframe=NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + psta_bmc = rtw_get_bcmc_stainfo(padapter); + + + //_enter_critical_bh(&psta->sleep_q.lock, &irqL); + _enter_critical_bh(&pxmitpriv->lock, &irqL); + + xmitframe_phead = get_list_head(&psta->sleep_q); + xmitframe_plist = get_next(xmitframe_phead); + + while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) + { + pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); + + xmitframe_plist = get_next(xmitframe_plist); + + rtw_list_delete(&pxmitframe->list); + + switch(pxmitframe->attrib.priority) + { + case 1: + case 2: + wmmps_ac = psta->uapsd_bk&BIT(1); + break; + case 4: + case 5: + wmmps_ac = psta->uapsd_vi&BIT(1); + break; + case 6: + case 7: + wmmps_ac = psta->uapsd_vo&BIT(1); + break; + case 0: + case 3: + default: + wmmps_ac = psta->uapsd_be&BIT(1); + break; + } + + psta->sleepq_len--; + if(psta->sleepq_len>0) + pxmitframe->attrib.mdata = 1; + else + pxmitframe->attrib.mdata = 0; + + if(wmmps_ac) + { + psta->sleepq_ac_len--; + if(psta->sleepq_ac_len>0) + { + pxmitframe->attrib.mdata = 1; + pxmitframe->attrib.eosp = 0; + } + else + { + pxmitframe->attrib.mdata = 0; + pxmitframe->attrib.eosp = 1; + } + } + + pxmitframe->attrib.triggered = 1; + +/* + _exit_critical_bh(&psta->sleep_q.lock, &irqL); + if(rtw_hal_xmit(padapter, pxmitframe) == _TRUE) + { + rtw_os_xmit_complete(padapter, pxmitframe); + } + _enter_critical_bh(&psta->sleep_q.lock, &irqL); +*/ + rtw_hal_xmitframe_enqueue(padapter, pxmitframe); + + + } + + if(psta->sleepq_len==0) + { +#ifdef CONFIG_TDLS + if( psta->tdls_sta_state & TDLS_LINKED_STATE ) + { + if(psta->state&WIFI_SLEEP_STATE) + psta->state ^= WIFI_SLEEP_STATE; + + _exit_critical_bh(&pxmitpriv->lock, &irqL); + return; + } +#endif //CONFIG_TDLS + + if (pstapriv->tim_bitmap & BIT(psta->aid)) { + //DBG_871X("wakeup to xmit, qlen==0, update_BCNTIM, tim=%x\n", pstapriv->tim_bitmap); + //upate BCN for TIM IE + //update_BCNTIM(padapter); + update_mask = BIT(0); + } + + pstapriv->tim_bitmap &= ~BIT(psta->aid); + + if(psta->state&WIFI_SLEEP_STATE) + psta->state ^= WIFI_SLEEP_STATE; + + if(psta->state & WIFI_STA_ALIVE_CHK_STATE) + { + DBG_871X("%s alive check\n", __func__); + psta->expire_to = pstapriv->expire_to; + psta->state ^= WIFI_STA_ALIVE_CHK_STATE; + } + + pstapriv->sta_dz_bitmap &= ~BIT(psta->aid); + } + + //for BC/MC Frames + if(!psta_bmc) + goto _exit; + + if((pstapriv->sta_dz_bitmap&0xfffe) == 0x0)//no any sta in ps mode + { + xmitframe_phead = get_list_head(&psta_bmc->sleep_q); + xmitframe_plist = get_next(xmitframe_phead); + + while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) + { + pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); + + xmitframe_plist = get_next(xmitframe_plist); + + rtw_list_delete(&pxmitframe->list); + + psta_bmc->sleepq_len--; + if(psta_bmc->sleepq_len>0) + pxmitframe->attrib.mdata = 1; + else + pxmitframe->attrib.mdata = 0; + + + pxmitframe->attrib.triggered = 1; +/* + _exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL); + if(rtw_hal_xmit(padapter, pxmitframe) == _TRUE) + { + rtw_os_xmit_complete(padapter, pxmitframe); + } + _enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL); + +*/ + rtw_hal_xmitframe_enqueue(padapter, pxmitframe); + + } + + if(psta_bmc->sleepq_len==0) + { + if (pstapriv->tim_bitmap & BIT(0)) { + //DBG_871X("wakeup to xmit, qlen==0, update_BCNTIM, tim=%x\n", pstapriv->tim_bitmap); + //upate BCN for TIM IE + //update_BCNTIM(padapter); + update_mask |= BIT(1); + } + pstapriv->tim_bitmap &= ~BIT(0); + pstapriv->sta_dz_bitmap &= ~BIT(0); + } + + } + +_exit: + + //_exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL); + _exit_critical_bh(&pxmitpriv->lock, &irqL); + + if(update_mask) + { + //update_BCNTIM(padapter); + if ((update_mask & (BIT(0)|BIT(1))) == (BIT(0)|BIT(1))) + _update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "clear UC&BMC"); + else if ((update_mask & BIT(1)) == BIT(1)) + _update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "clear BMC"); + else + _update_beacon(padapter, _TIM_IE_, NULL, _TRUE, "clear UC"); + } + +} + +void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta) +{ + _irqL irqL; + u8 wmmps_ac=0; + _list *xmitframe_plist, *xmitframe_phead; + struct xmit_frame *pxmitframe=NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + + //_enter_critical_bh(&psta->sleep_q.lock, &irqL); + _enter_critical_bh(&pxmitpriv->lock, &irqL); + + xmitframe_phead = get_list_head(&psta->sleep_q); + xmitframe_plist = get_next(xmitframe_phead); + + while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) + { + pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); + + xmitframe_plist = get_next(xmitframe_plist); + + switch(pxmitframe->attrib.priority) + { + case 1: + case 2: + wmmps_ac = psta->uapsd_bk&BIT(1); + break; + case 4: + case 5: + wmmps_ac = psta->uapsd_vi&BIT(1); + break; + case 6: + case 7: + wmmps_ac = psta->uapsd_vo&BIT(1); + break; + case 0: + case 3: + default: + wmmps_ac = psta->uapsd_be&BIT(1); + break; + } + + if(!wmmps_ac) + continue; + + rtw_list_delete(&pxmitframe->list); + + psta->sleepq_len--; + psta->sleepq_ac_len--; + + if(psta->sleepq_ac_len>0) + { + pxmitframe->attrib.mdata = 1; + pxmitframe->attrib.eosp = 0; + } + else + { + pxmitframe->attrib.mdata = 0; + pxmitframe->attrib.eosp = 1; + } + + pxmitframe->attrib.triggered = 1; + rtw_hal_xmitframe_enqueue(padapter, pxmitframe); + + if((psta->sleepq_ac_len==0) && (!psta->has_legacy_ac) && (wmmps_ac)) + { +#ifdef CONFIG_TDLS + if(psta->tdls_sta_state & TDLS_LINKED_STATE ) + { + //_exit_critical_bh(&psta->sleep_q.lock, &irqL); + goto exit; + } +#endif //CONFIG_TDLS + pstapriv->tim_bitmap &= ~BIT(psta->aid); + + //DBG_871X("wakeup to xmit, qlen==0, update_BCNTIM, tim=%x\n", pstapriv->tim_bitmap); + //upate BCN for TIM IE + //update_BCNTIM(padapter); + update_beacon(padapter, _TIM_IE_, NULL, _TRUE); + //update_mask = BIT(0); + } + + } + +exit: + //_exit_critical_bh(&psta->sleep_q.lock, &irqL); + _exit_critical_bh(&pxmitpriv->lock, &irqL); + + return; +} + +#endif /* defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS) */ + +#ifdef CONFIG_XMIT_THREAD_MODE +void enqueue_pending_xmitbuf( + struct xmit_priv *pxmitpriv, + struct xmit_buf *pxmitbuf) +{ + _irqL irql; + _queue *pqueue; + _adapter *pri_adapter = pxmitpriv->adapter; + + pqueue = &pxmitpriv->pending_xmitbuf_queue; + + _enter_critical_bh(&pqueue->lock, &irql); + rtw_list_delete(&pxmitbuf->list); + rtw_list_insert_tail(&pxmitbuf->list, get_list_head(pqueue)); + _exit_critical_bh(&pqueue->lock, &irql); + + + +#if defined(CONFIG_SDIO_HCI) && defined(CONFIG_CONCURRENT_MODE) + if (pri_adapter->adapter_type > PRIMARY_ADAPTER) + pri_adapter = pri_adapter->pbuddy_adapter; +#endif //SDIO_HCI + CONCURRENT + _rtw_up_sema(&(pri_adapter->xmitpriv.xmit_sema)); + +} + +void enqueue_pending_xmitbuf_to_head( + struct xmit_priv *pxmitpriv, + struct xmit_buf *pxmitbuf) +{ + _irqL irql; + _queue *pqueue; + _adapter *pri_adapter = pxmitpriv->adapter; + + pqueue = &pxmitpriv->pending_xmitbuf_queue; + + _enter_critical_bh(&pqueue->lock, &irql); + rtw_list_delete(&pxmitbuf->list); + rtw_list_insert_head(&pxmitbuf->list, get_list_head(pqueue)); + _exit_critical_bh(&pqueue->lock, &irql); +} + +struct xmit_buf* dequeue_pending_xmitbuf( + struct xmit_priv *pxmitpriv) +{ + _irqL irql; + struct xmit_buf *pxmitbuf; + _queue *pqueue; + + + pxmitbuf = NULL; + pqueue = &pxmitpriv->pending_xmitbuf_queue; + + _enter_critical_bh(&pqueue->lock, &irql); + + if (_rtw_queue_empty(pqueue) == _FALSE) + { + _list *plist, *phead; + + phead = get_list_head(pqueue); + plist = get_next(phead); + pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list); + rtw_list_delete(&pxmitbuf->list); + } + + _exit_critical_bh(&pqueue->lock, &irql); + + return pxmitbuf; +} + +struct xmit_buf* dequeue_pending_xmitbuf_under_survey( + struct xmit_priv *pxmitpriv) +{ + _irqL irql; + struct xmit_buf *pxmitbuf; +#ifdef CONFIG_USB_HCI + struct xmit_frame *pxmitframe; +#endif + _queue *pqueue; + + + pxmitbuf = NULL; + pqueue = &pxmitpriv->pending_xmitbuf_queue; + + _enter_critical_bh(&pqueue->lock, &irql); + + if (_rtw_queue_empty(pqueue) == _FALSE) + { + _list *plist, *phead; + u8 type; + + phead = get_list_head(pqueue); + plist = phead; + do { + plist = get_next(plist); + if (plist == phead) break; + + pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list); + +#ifdef CONFIG_USB_HCI + pxmitframe = (struct xmit_frame*)pxmitbuf->priv_data; + if(pxmitframe) + { + type = GetFrameSubType(pxmitbuf->pbuf + TXDESC_SIZE + pxmitframe->pkt_offset * PACKET_OFFSET_SZ); + } + else + { + DBG_871X("%s, !!!ERROR!!! For USB, TODO ITEM \n", __FUNCTION__); + } +#else + type = GetFrameSubType(pxmitbuf->pbuf + TXDESC_OFFSET); +#endif + + if ((type == WIFI_PROBEREQ) || + (type == WIFI_DATA_NULL) || + (type == WIFI_QOS_DATA_NULL)) + { + rtw_list_delete(&pxmitbuf->list); + break; + } + pxmitbuf = NULL; + } while (1); + } + + _exit_critical_bh(&pqueue->lock, &irql); + + return pxmitbuf; +} + +sint check_pending_xmitbuf( + struct xmit_priv *pxmitpriv) +{ + _irqL irql; + _queue *pqueue; + sint ret = _FALSE; + + pqueue = &pxmitpriv->pending_xmitbuf_queue; + + _enter_critical_bh(&pqueue->lock, &irql); + + if(_rtw_queue_empty(pqueue) == _FALSE) + ret = _TRUE; + + _exit_critical_bh(&pqueue->lock, &irql); + + return ret; +} + +thread_return rtw_xmit_thread(thread_context context) +{ + s32 err; + PADAPTER padapter; + + + err = _SUCCESS; + padapter = (PADAPTER)context; + + thread_enter("RTW_XMIT_THREAD"); + + do { + err = rtw_hal_xmit_thread_handler(padapter); + flush_signals_thread(); + } while (_SUCCESS == err); + + _rtw_up_sema(&padapter->xmitpriv.terminate_xmitthread_sema); + + thread_exit(); +} +#endif + +bool rtw_xmit_ac_blocked(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + _adapter *iface; + struct mlme_ext_priv *mlmeext; + struct mlme_ext_info *mlmeextinfo; + bool blocked = _FALSE; + int i; + + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + mlmeext = &iface->mlmeextpriv; + + /* check scan state */ + if (mlmeext_scan_state(mlmeext) != SCAN_DISABLE + && mlmeext_scan_state(mlmeext) != SCAN_BACK_OP + ) { + blocked = _TRUE; + goto exit; + } + + if (mlmeext_scan_state(mlmeext) == SCAN_BACK_OP + && !mlmeext_chk_scan_backop_flags(mlmeext, SS_BACKOP_TX_RESUME) + ) { + blocked = _TRUE; + goto exit; + } + } + +exit: + return blocked; +} + +void rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms) +{ + sctx->timeout_ms = timeout_ms; + sctx->submit_time= rtw_get_current_time(); +#ifdef PLATFORM_LINUX /* TODO: add condition wating interface for other os */ + init_completion(&sctx->done); +#endif + sctx->status = RTW_SCTX_SUBMITTED; +} + +int rtw_sctx_wait(struct submit_ctx *sctx, const char *msg) +{ + int ret = _FAIL; + unsigned long expire; + int status = 0; + +#ifdef PLATFORM_LINUX + expire= sctx->timeout_ms ? msecs_to_jiffies(sctx->timeout_ms) : MAX_SCHEDULE_TIMEOUT; + if (!wait_for_completion_timeout(&sctx->done, expire)) { + /* timeout, do something?? */ + status = RTW_SCTX_DONE_TIMEOUT; + DBG_871X("%s timeout: %s\n", __func__, msg); + } else { + status = sctx->status; + } +#endif + + if (status == RTW_SCTX_DONE_SUCCESS) { + ret = _SUCCESS; + } + + return ret; +} + +bool rtw_sctx_chk_waring_status(int status) +{ + switch(status) { + case RTW_SCTX_DONE_UNKNOWN: + case RTW_SCTX_DONE_BUF_ALLOC: + case RTW_SCTX_DONE_BUF_FREE: + + case RTW_SCTX_DONE_DRV_STOP: + case RTW_SCTX_DONE_DEV_REMOVE: + return _TRUE; + default: + return _FALSE; + } +} + +void rtw_sctx_done_err(struct submit_ctx **sctx, int status) +{ + if (*sctx) { + if (rtw_sctx_chk_waring_status(status)) + DBG_871X("%s status:%d\n", __func__, status); + (*sctx)->status = status; + #ifdef PLATFORM_LINUX + complete(&((*sctx)->done)); + #endif + *sctx = NULL; + } +} + +void rtw_sctx_done(struct submit_ctx **sctx) +{ + rtw_sctx_done_err(sctx, RTW_SCTX_DONE_SUCCESS); +} + +#ifdef CONFIG_XMIT_ACK + +#ifdef CONFIG_XMIT_ACK_POLLING +s32 c2h_evt_hdl(_adapter *adapter, u8 *c2h_evt, c2h_id_filter filter); + +/** + * rtw_ack_tx_polling - + * @pxmitpriv: xmit_priv to address ack_tx_ops + * @timeout_ms: timeout msec + * + * Init ack_tx_ops and then do c2h_evt_hdl() and polling ack_tx_ops repeatedly + * till tx report or timeout + * Returns: _SUCCESS if TX report ok, _FAIL for others + */ +int rtw_ack_tx_polling(struct xmit_priv *pxmitpriv, u32 timeout_ms) +{ + int ret = _FAIL; + struct submit_ctx *pack_tx_ops = &pxmitpriv->ack_tx_ops; + _adapter *adapter = container_of(pxmitpriv, _adapter, xmitpriv); + + pack_tx_ops->submit_time = rtw_get_current_time(); + pack_tx_ops->timeout_ms = timeout_ms; + pack_tx_ops->status = RTW_SCTX_SUBMITTED; + + do { + c2h_evt_hdl(adapter, NULL, rtw_hal_c2h_id_filter_ccx(adapter)); + if (pack_tx_ops->status != RTW_SCTX_SUBMITTED) + break; + + if (rtw_is_drv_stopped(adapter)) { + pack_tx_ops->status = RTW_SCTX_DONE_DRV_STOP; + break; + } + if (rtw_is_surprise_removed(adapter)) { + pack_tx_ops->status = RTW_SCTX_DONE_DEV_REMOVE; + break; + } + + rtw_msleep_os(10); + } while (rtw_get_passing_time_ms(pack_tx_ops->submit_time) < timeout_ms); + + if (pack_tx_ops->status == RTW_SCTX_SUBMITTED) { + pack_tx_ops->status = RTW_SCTX_DONE_TIMEOUT; + DBG_871X("%s timeout\n", __func__); + } + + if (pack_tx_ops->status == RTW_SCTX_DONE_SUCCESS) + ret = _SUCCESS; + + return ret; +} +#endif + +int rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms) +{ +#ifdef CONFIG_XMIT_ACK_POLLING + return rtw_ack_tx_polling(pxmitpriv, timeout_ms); +#else + struct submit_ctx *pack_tx_ops = &pxmitpriv->ack_tx_ops; + + pack_tx_ops->submit_time = rtw_get_current_time(); + pack_tx_ops->timeout_ms = timeout_ms; + pack_tx_ops->status = RTW_SCTX_SUBMITTED; + + return rtw_sctx_wait(pack_tx_ops, __func__); +#endif +} + +void rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status) +{ + struct submit_ctx *pack_tx_ops = &pxmitpriv->ack_tx_ops; + + if (pxmitpriv->ack_tx) { + rtw_sctx_done_err(&pack_tx_ops, status); + } else { + DBG_871X("%s ack_tx not set\n", __func__); + } +} +#endif //CONFIG_XMIT_ACK + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/HalPwrSeqCmd.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/HalPwrSeqCmd.c new file mode 100644 index 000000000..6d063aa98 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/HalPwrSeqCmd.c @@ -0,0 +1,183 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + HalPwrSeqCmd.c + +Abstract: + Implement HW Power sequence configuration CMD handling routine for Realtek devices. + +Major Change History: + When Who What + ---------- --------------- ------------------------------- + 2011-10-26 Lucas Modify to be compatible with SD4-CE driver. + 2011-07-07 Roger Create. + +--*/ +#include + + +// +// Description: +// This routine deal with the Power Configuration CMDs parsing for RTL8723/RTL8188E Series IC. +// +// Assumption: +// We should follow specific format which was released from HW SD. +// +// 2011.07.07, added by Roger. +// +u8 HalPwrSeqCmdParsing( + PADAPTER padapter, + u8 CutVersion, + u8 FabVersion, + u8 InterfaceType, + WLAN_PWR_CFG PwrSeqCmd[]) +{ + WLAN_PWR_CFG PwrCfgCmd = {0}; + u8 bPollingBit = _FALSE; + u32 AryIdx = 0; + u8 value = 0; + u32 offset = 0; + u32 pollingCount = 0; // polling autoload done. + u32 maxPollingCnt = 5000; + + do { + PwrCfgCmd = PwrSeqCmd[AryIdx]; + + RT_TRACE(_module_hal_init_c_ , _drv_info_, + ("HalPwrSeqCmdParsing: offset(%#x) cut_msk(%#x) fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) msk(%#x) value(%#x)\n", + GET_PWR_CFG_OFFSET(PwrCfgCmd), + GET_PWR_CFG_CUT_MASK(PwrCfgCmd), + GET_PWR_CFG_FAB_MASK(PwrCfgCmd), + GET_PWR_CFG_INTF_MASK(PwrCfgCmd), + GET_PWR_CFG_BASE(PwrCfgCmd), + GET_PWR_CFG_CMD(PwrCfgCmd), + GET_PWR_CFG_MASK(PwrCfgCmd), + GET_PWR_CFG_VALUE(PwrCfgCmd))); + + //2 Only Handle the command whose FAB, CUT, and Interface are matched + if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) && + (GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) && + (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)) + { + switch (GET_PWR_CFG_CMD(PwrCfgCmd)) + { + case PWR_CMD_READ: + RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_READ\n")); + break; + + case PWR_CMD_WRITE: + RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_WRITE\n")); + offset = GET_PWR_CFG_OFFSET(PwrCfgCmd); + +#ifdef CONFIG_SDIO_HCI + // + // We should deal with interface specific address mapping for some interfaces, e.g., SDIO interface + // 2011.07.07. + // + if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) + { + // Read Back SDIO Local value + value = SdioLocalCmd52Read1Byte(padapter, offset); + + value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd)); + value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)); + + // Write Back SDIO Local value + SdioLocalCmd52Write1Byte(padapter, offset, value); + } + else +#endif + { +#ifdef CONFIG_GSPI_HCI + if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) + offset = SPI_LOCAL_OFFSET | offset; +#endif + // Read the value from system register + value = rtw_read8(padapter, offset); + + value=value&(~(GET_PWR_CFG_MASK(PwrCfgCmd))); + value=value|(GET_PWR_CFG_VALUE(PwrCfgCmd)&GET_PWR_CFG_MASK(PwrCfgCmd)); + + // Write the value back to sytem register + rtw_write8(padapter, offset, value); + } + break; + + case PWR_CMD_POLLING: + RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_POLLING\n")); + + bPollingBit = _FALSE; + offset = GET_PWR_CFG_OFFSET(PwrCfgCmd); +#ifdef CONFIG_GSPI_HCI + if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) + offset = SPI_LOCAL_OFFSET | offset; +#endif + do { +#ifdef CONFIG_SDIO_HCI + if (GET_PWR_CFG_BASE(PwrCfgCmd) == PWR_BASEADDR_SDIO) + value = SdioLocalCmd52Read1Byte(padapter, offset); + else +#endif + value = rtw_read8(padapter, offset); + + value=value&GET_PWR_CFG_MASK(PwrCfgCmd); + if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd))) + bPollingBit = _TRUE; + else + rtw_udelay_os(10); + + if (pollingCount++ > maxPollingCnt) { + DBG_871X_LEVEL(_drv_err_, "HalPwrSeqCmdParsing: Fail to polling Offset[%#x]=%02x\n", offset, value); + return _FALSE; + } + } while (!bPollingBit); + + break; + + case PWR_CMD_DELAY: + RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_DELAY\n")); + if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US) + rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd)); + else + rtw_udelay_os(GET_PWR_CFG_OFFSET(PwrCfgCmd)*1000); + break; + + case PWR_CMD_END: + // When this command is parsed, end the process + RT_TRACE(_module_hal_init_c_ , _drv_info_, ("HalPwrSeqCmdParsing: PWR_CMD_END\n")); + return _TRUE; + break; + + default: + RT_TRACE(_module_hal_init_c_ , _drv_err_, ("HalPwrSeqCmdParsing: Unknown CMD!!\n")); + break; + } + } + + AryIdx++;//Add Array Index + }while(1); + + return _TRUE; +} + + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8188c2Ant.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8188c2Ant.c new file mode 100644 index 000000000..fb9139538 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8188c2Ant.c @@ -0,0 +1,1988 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//============================================================ +// Description: +// +// This file is for 92CE/92CU BT 1 Antenna Co-exist mechanism +// +// By cosa 02/11/2011 +// +//============================================================ + +//============================================================ +// include files +//============================================================ +#include "Mp_Precomp.h" + +#if WPP_SOFTWARE_TRACE +#include "HalBtc8188c2Ant.tmh" +#endif + +#if(BT_30_SUPPORT == 1) +//============================================================ +// Global variables, these are static variables +//============================================================ +static COEX_DM_8188C_2ANT GLCoexDm8188c2Ant; +static PCOEX_DM_8188C_2ANT pCoexDm=&GLCoexDm8188c2Ant; +static COEX_STA_8188C_2ANT GLCoexSta8188c2Ant; +static PCOEX_STA_8188C_2ANT pCoexSta=&GLCoexSta8188c2Ant; + +//============================================================ +// local function start with btdm_ +//============================================================ +u1Byte +halbtc8188c2ant_WifiRssiState( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte index, + IN u1Byte levelNum, + IN u1Byte rssiThresh, + IN u1Byte rssiThresh1 + ) +{ + s4Byte wifiRssi=0; + u1Byte wifiRssiState=pCoexSta->preWifiRssiState[index]; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); + + if(levelNum == 2) + { + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8188C_2ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else + { + if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + else if(levelNum == 3) + { + if(rssiThresh > rssiThresh1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi RSSI thresh error!!\n")); + return pCoexSta->preWifiRssiState[index]; + } + + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8188C_2ANT)) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_MEDIUM) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_MEDIUM)) + { + if(wifiRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8188C_2ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_MEDIUM; + } + } + else + { + if(wifiRssi < rssiThresh1) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + + pCoexSta->preWifiRssiState[index] = wifiRssiState; + + return wifiRssiState; +} + +u1Byte +halbtc8188c2ant_ActionAlgorithm( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + u1Byte algorithm=BT_8188C_2ANT_COEX_ALGO_UNDEFINED; + u1Byte numOfDiffProfile=0; + + if(!pStackInfo->bBtLinkExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], No profile exists!!!\n")); + return algorithm; + } + + if(pStackInfo->bScoExist) + numOfDiffProfile++; + if(pStackInfo->bHidExist) + numOfDiffProfile++; + if(pStackInfo->bPanExist) + numOfDiffProfile++; + if(pStackInfo->bA2dpExist) + numOfDiffProfile++; + + if(pStackInfo->bScoExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO algorithm\n")); + algorithm = BT_8188C_2ANT_COEX_ALGO_SCO; + } + else + { + if(numOfDiffProfile == 1) + { + if(pStackInfo->bHidExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID only\n")); + algorithm = BT_8188C_2ANT_COEX_ALGO_HID; + } + else if(pStackInfo->bA2dpExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP only\n")); + algorithm = BT_8188C_2ANT_COEX_ALGO_A2DP; + } + else if(pStackInfo->bPanExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN only\n")); + algorithm = BT_8188C_2ANT_COEX_ALGO_PAN; + } + } + else + { + if( pStackInfo->bHidExist && + pStackInfo->bA2dpExist ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP\n")); + algorithm = BT_8188C_2ANT_COEX_ALGO_HID_A2DP; + } + else if( pStackInfo->bHidExist && + pStackInfo->bPanExist ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + PAN\n")); + algorithm = BT_8188C_2ANT_COEX_ALGO_HID_PAN; + } + else if( pStackInfo->bPanExist && + pStackInfo->bA2dpExist ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN + A2DP\n")); + algorithm = BT_8188C_2ANT_COEX_ALGO_PAN_A2DP; + } + } + } + return algorithm; +} + +VOID +halbtc8188c2ant_SetFwBalance( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bBalanceOn, + IN u1Byte ms0, + IN u1Byte ms1 + ) +{ + u1Byte H2C_Parameter[3] ={0}; + + if(bBalanceOn) + { + H2C_Parameter[2] = 1; + H2C_Parameter[1] = ms1; + H2C_Parameter[0] = ms0; + } + else + { + H2C_Parameter[2] = 0; + H2C_Parameter[1] = 0; + H2C_Parameter[0] = 0; + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Balance=[%s:%dms:%dms], write 0xc=0x%x\n", + bBalanceOn?"ON":"OFF", ms0, ms1, + H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0xc, 3, H2C_Parameter); +} + +VOID +halbtc8188c2ant_Balance( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bBalanceOn, + IN u1Byte ms0, + IN u1Byte ms1 + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Balance %s\n", + (bForceExec? "force to":""), (bBalanceOn? "ON":"OFF"))); + pCoexDm->bCurBalanceOn = bBalanceOn; + + if(!bForceExec) + { + if(pCoexDm->bPreBalanceOn == pCoexDm->bCurBalanceOn) + return; + } + halbtc8188c2ant_SetFwBalance(pBtCoexist, bBalanceOn, ms0, ms1); + + pCoexDm->bPreBalanceOn = pCoexDm->bCurBalanceOn; +} + +VOID +halbtc8188c2ant_SetFwDiminishWifi( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bDacOn, + IN BOOLEAN bInterruptOn, + IN u1Byte fwDacSwingLvl, + IN BOOLEAN bNavOn + ) +{ + u1Byte H2C_Parameter[3] ={0}; + + if((pBtCoexist->stackInfo.minBtRssi <= -5) && (fwDacSwingLvl == 0x20)) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], DiminishWiFi 0x20 original, but set 0x18 for Low RSSI!\n")); + fwDacSwingLvl = 0x18; + } + + H2C_Parameter[2] = 0; + H2C_Parameter[1] = fwDacSwingLvl; + H2C_Parameter[0] = 0; + if(bDacOn) + { + H2C_Parameter[2] |= 0x01; //BIT0 + if(bInterruptOn) + { + H2C_Parameter[2] |= 0x02; //BIT1 + } + } + if(bNavOn) + { + H2C_Parameter[2] |= 0x08; //BIT3 + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], bDacOn=%s, bInterruptOn=%s, bNavOn=%s, write 0xe=0x%x\n", + (bDacOn?"ON":"OFF"), (bInterruptOn?"ON":"OFF"), (bNavOn?"ON":"OFF"), + (H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2]))); + pBtCoexist->fBtcFillH2c(pBtCoexist, 0xe, 3, H2C_Parameter); +} + +VOID +halbtc8188c2ant_DiminishWifi( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bDacOn, + IN BOOLEAN bInterruptOn, + IN u1Byte fwDacSwingLvl, + IN BOOLEAN bNavOn + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s set Diminish Wifi, bDacOn=%s, bInterruptOn=%s, fwDacSwingLvl=%d, bNavOn=%s\n", + (bForceExec? "force to":""), (bDacOn? "ON":"OFF"), (bInterruptOn? "ON":"OFF"), fwDacSwingLvl, (bNavOn? "ON":"OFF"))); + + pCoexDm->bCurDacOn = bDacOn; + pCoexDm->bCurInterruptOn = bInterruptOn; + pCoexDm->curFwDacSwingLvl = fwDacSwingLvl; + pCoexDm->bCurNavOn = bNavOn; + + if(!bForceExec) + { + if( (pCoexDm->bPreDacOn==pCoexDm->bCurDacOn) && + (pCoexDm->bPreInterruptOn==pCoexDm->bCurInterruptOn) && + (pCoexDm->preFwDacSwingLvl==pCoexDm->curFwDacSwingLvl) && + (pCoexDm->bPreNavOn==pCoexDm->bCurNavOn) ) + return; + } + halbtc8188c2ant_SetFwDiminishWifi(pBtCoexist, bDacOn, bInterruptOn, fwDacSwingLvl, bNavOn); + + pCoexDm->bPreDacOn = pCoexDm->bCurDacOn; + pCoexDm->bPreInterruptOn = pCoexDm->bCurInterruptOn; + pCoexDm->preFwDacSwingLvl = pCoexDm->curFwDacSwingLvl; + pCoexDm->bPreNavOn = pCoexDm->bCurNavOn; +} + +VOID +halbtc8188c2ant_SetSwRfRxLpfCorner( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bRxRfShrinkOn + ) +{ + if(bRxRfShrinkOn) + { + //Shrink RF Rx LPF corner + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Shrink RF Rx LPF corner!!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xf0, 0xf); + } + else + { + //Resume RF Rx LPF corner + // After initialized, we can use pCoexDm->btRf0x1eBackup + if(pBtCoexist->bInitilized) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Resume RF Rx LPF corner!!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xf0, pCoexDm->btRf0x1eBackup); + } + } +} + +VOID +halbtc8188c2ant_RfShrink( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bRxRfShrinkOn + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Rx RF Shrink = %s\n", + (bForceExec? "force to":""), ((bRxRfShrinkOn)? "ON":"OFF"))); + pCoexDm->bCurRfRxLpfShrink = bRxRfShrinkOn; + + if(!bForceExec) + { + if(pCoexDm->bPreRfRxLpfShrink == pCoexDm->bCurRfRxLpfShrink) + return; + } + halbtc8188c2ant_SetSwRfRxLpfCorner(pBtCoexist, pCoexDm->bCurRfRxLpfShrink); + + pCoexDm->bPreRfRxLpfShrink = pCoexDm->bCurRfRxLpfShrink; +} + +VOID +halbtc8188c2ant_SetSwPenaltyTxRateAdaptive( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bLowPenaltyRa + ) +{ + u1Byte tmpU1; + + tmpU1 = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4fd); + if(bLowPenaltyRa) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set low penalty!!\n")); + tmpU1 &= ~BIT2; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set normal!!\n")); + tmpU1 |= BIT2; + } + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x4fd, tmpU1); +} + +VOID +halbtc8188c2ant_LowPenaltyRa( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bLowPenaltyRa + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn LowPenaltyRA = %s\n", + (bForceExec? "force to":""), ((bLowPenaltyRa)? "ON":"OFF"))); + pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa; + + if(!bForceExec) + { + if(pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa) + return; + } + halbtc8188c2ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa); + + pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa; +} + +VOID +halbtc8188c2ant_SetSwFullTimeDacSwing( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bSwDacSwingOn, + IN u4Byte swDacSwingLvl + ) +{ + u4Byte dacSwingLvl; + + if(bSwDacSwingOn) + { + if((pBtCoexist->stackInfo.minBtRssi <= -5) && (swDacSwingLvl == 0x20)) + { + dacSwingLvl = 0x18; + } + else + { + dacSwingLvl = swDacSwingLvl; + } + pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xfc000000, dacSwingLvl); + } + else + { + pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xfc000000, 0x30); + } +} + +VOID +halbtc8188c2ant_DacSwing( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bDacSwingOn, + IN u4Byte dacSwingLvl + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn DacSwing=%s, dacSwingLvl=0x%x\n", + (bForceExec? "force to":""), ((bDacSwingOn)? "ON":"OFF"), dacSwingLvl)); + pCoexDm->bCurDacSwingOn = bDacSwingOn; + pCoexDm->curDacSwingLvl = dacSwingLvl; + + if(!bForceExec) + { + if( (pCoexDm->bPreDacSwingOn == pCoexDm->bCurDacSwingOn) && + (pCoexDm->preDacSwingLvl == pCoexDm->curDacSwingLvl) ) + return; + } + delay_ms(30); + halbtc8188c2ant_SetSwFullTimeDacSwing(pBtCoexist, bDacSwingOn, dacSwingLvl); + + pCoexDm->bPreDacSwingOn = pCoexDm->bCurDacSwingOn; + pCoexDm->preDacSwingLvl = pCoexDm->curDacSwingLvl; +} + +VOID +halbtc8188c2ant_SetAdcBackOff( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bAdcBackOff + ) +{ + if(bAdcBackOff) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level On!\n")); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc04,0x3a07611); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level Off!\n")); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc04,0x3a05611); + } +} + +VOID +halbtc8188c2ant_AdcBackOff( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bAdcBackOff + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn AdcBackOff = %s\n", + (bForceExec? "force to":""), ((bAdcBackOff)? "ON":"OFF"))); + pCoexDm->bCurAdcBackOff = bAdcBackOff; + + if(!bForceExec) + { + if(pCoexDm->bPreAdcBackOff == pCoexDm->bCurAdcBackOff) + return; + } + halbtc8188c2ant_SetAdcBackOff(pBtCoexist, pCoexDm->bCurAdcBackOff); + + pCoexDm->bPreAdcBackOff = pCoexDm->bCurAdcBackOff; +} + +VOID +halbtc8188c2ant_SetAgcTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bAgcTableEn + ) +{ + u1Byte rssiAdjustVal=0; + + if(bAgcTableEn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table On!\n")); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4e1c0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4d1d0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4c1e0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4b1f0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4a200001); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xdc000); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x90000); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x51000); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x12000); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1a, 0xfffff, 0x00255); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table Off!\n")); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x641c0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x631d0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x621e0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x611f0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x60200001); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x32000); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x71000); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xb0000); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xfc000); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1a, 0xfffff, 0x10255); + } + + // set rssiAdjustVal for wifi module. + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, &rssiAdjustVal); +} + + +VOID +halbtc8188c2ant_AgcTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bAgcTableEn + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s %s Agc Table\n", + (bForceExec? "force to":""), ((bAgcTableEn)? "Enable":"Disable"))); + pCoexDm->bCurAgcTableEn = bAgcTableEn; + + if(!bForceExec) + { + if(pCoexDm->bPreAgcTableEn == pCoexDm->bCurAgcTableEn) + return; + } + halbtc8188c2ant_SetAgcTable(pBtCoexist, bAgcTableEn); + + pCoexDm->bPreAgcTableEn = pCoexDm->bCurAgcTableEn; +} + +VOID +halbtc8188c2ant_SetCoexTable( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte val0x6c4, + IN u4Byte val0x6c8, + IN u4Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], set coex table, set 0x6c4=0x%x\n", val0x6c4)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c4, val0x6c4); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, val0x6c8); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6cc, val0x6cc); +} + +VOID +halbtc8188c2ant_CoexTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u4Byte val0x6c4, + IN u4Byte val0x6c8, + IN u4Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s write Coex Table 0x6c4=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n", + (bForceExec? "force to":""), val0x6c4, val0x6c8, val0x6cc)); + pCoexDm->curVal0x6c4 = val0x6c4; + pCoexDm->curVal0x6c8 = val0x6c8; + pCoexDm->curVal0x6cc = val0x6cc; + + if(!bForceExec) + { + if( (pCoexDm->preVal0x6c4 == pCoexDm->curVal0x6c4) && + (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) && + (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) ) + return; + } + halbtc8188c2ant_SetCoexTable(pBtCoexist, val0x6c4, val0x6c8, val0x6cc); + + pCoexDm->preVal0x6c4 = pCoexDm->curVal0x6c4; + pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8; + pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc; +} + +VOID +halbtc8188c2ant_CoexAllOff( + IN PBTC_COEXIST pBtCoexist + ) +{ + // fw mechanism + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); + + // sw mechanism + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); +} +VOID +halbtc8188c2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ +} + + +VOID +halbtc8188c2ant_MonitorBtState( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN stateChange=FALSE; + u4Byte BT_Polling, Ratio_Act, Ratio_STA; + u4Byte BT_Active, BT_State; + u4Byte regBTActive=0, regBTState=0, regBTPolling=0; + u4Byte btBusyThresh=0; + u4Byte fwVer=0; + static BOOLEAN bBtBusyTraffic=FALSE; + BOOLEAN bRejApAggPkt=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], FirmwareVersion = 0x%x(%d)\n", fwVer, fwVer)); + if(fwVer < 62) + { + regBTActive = 0x488; + regBTState = 0x48c; + regBTPolling = 0x490; + } + else + { + regBTActive = 0x444; + regBTState = 0x448; + if(fwVer >= 74) + regBTPolling = 0x44c; + else + regBTPolling = 0x700; + } + btBusyThresh = 60; + + BT_Active = pBtCoexist->fBtcRead4Byte(pBtCoexist, regBTActive); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT_Active(0x%x)=0x%x\n", regBTActive, BT_Active)); + BT_Active = BT_Active & 0x00ffffff; + + BT_State = pBtCoexist->fBtcRead4Byte(pBtCoexist, regBTState); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT_State(0x%x)=0x%x\n", regBTState, BT_State)); + BT_State = BT_State & 0x00ffffff; + + BT_Polling = pBtCoexist->fBtcRead4Byte(pBtCoexist, regBTPolling); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT_Polling(0x%x)=0x%x\n", regBTPolling, BT_Polling)); + + if(BT_Active==0xffffffff && BT_State==0xffffffff && BT_Polling==0xffffffff ) + return; + + // 2011/05/04 MH For Slim combo test meet a problem. Surprise remove and WLAN is running + // DHCP process. At the same time, the register read value might be zero. And cause BSOD 0x7f + // EXCEPTION_DIVIDED_BY_ZERO. In This case, the stack content may always be wrong due to + // HW divide trap. + if (BT_Polling==0) + return; + + Ratio_Act = BT_Active*1000/BT_Polling; + Ratio_STA = BT_State*1000/BT_Polling; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Ratio_Act=%d\n", Ratio_Act)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Ratio_STA=%d\n", Ratio_STA)); + + if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) + { + if(Ratio_STA < 60) // BT PAN idle + { + } + else + { + // Check if BT PAN (under BT 2.1) is uplink or downlink + if((Ratio_Act/Ratio_STA) < 2) + { // BT PAN Uplink + pCoexSta->bBtUplink = TRUE; + } + else + { // BT PAN downlink + pCoexSta->bBtUplink = FALSE; + } + } + } + + // Check BT is idle or not + if(!pBtCoexist->stackInfo.bBtLinkExist) + { + pCoexSta->bBtBusy = FALSE; + } + else + { + if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) + { + if(Ratio_Act<20) + { + pCoexSta->bBtBusy = FALSE; + } + else + { + pCoexSta->bBtBusy = TRUE; + } + } + else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) + { + if(Ratio_STA < btBusyThresh) + { + pCoexSta->bBtBusy = FALSE; + } + else + { + pCoexSta->bBtBusy = TRUE; + } + + if( (Ratio_STA < btBusyThresh) || + (Ratio_Act<180 && Ratio_STA<130) ) + { + pCoexSta->bA2dpBusy = FALSE; + } + else + { + pCoexSta->bA2dpBusy = TRUE; + } + } + } + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &pCoexSta->bBtBusy); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_LIMITED_DIG, &pCoexSta->bBtBusy); + + if(bBtBusyTraffic != pCoexSta->bBtBusy) + { // BT idle or BT non-idle + bBtBusyTraffic = pCoexSta->bBtBusy; + stateChange = TRUE; + } + + if(stateChange) + { + if(!pCoexSta->bBtBusy) + { + halbtc8188c2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_CoexAllOff(pBtCoexist); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0); + } + else + { + halbtc8188c2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8188c2ant_RfShrink(pBtCoexist, NORMAL_EXEC, TRUE); + } + } + + if(stateChange) + { + bRejApAggPkt = pCoexSta->bBtBusy; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, &bRejApAggPkt); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); + } +} + +VOID +halbtc8188c2ant_ActionA2dpBc4( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState; + u4Byte wifiBw, wifiTrafficDir; + + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); + + if(pCoexSta->bBtBusy) + { + if(BTC_WIFI_BW_HT40 == wifiBw) + { + // fw mechanism first + if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) + { + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0xc, 0x18); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x20, FALSE); + } + else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) + { + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); + } + + // sw mechanism + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20); + } + else + { + wifiRssiState = halbtc8188c2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0); + + if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) + { + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0xc, 0x18); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x20, FALSE); + } + else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) + { + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); + } + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20); + } + else + { + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20); + } + } + } + else + { + halbtc8188c2ant_CoexAllOff(pBtCoexist); + } +} + +VOID +halbtc8188c2ant_ActionA2dpBc8( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState; + u4Byte wifiBw, wifiTrafficDir; + BOOLEAN bWifiBusy=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + if(pCoexSta->bA2dpBusy && bWifiBusy) + { + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); + wifiRssiState = halbtc8188c2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0); + + // fw mechanism first + if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) + { + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0xc, 0x18); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); + } + else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) + { + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x10, 0x18); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); + } + + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + else + { + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + } + } + else if(pCoexSta->bA2dpBusy) + { + // fw mechanism first + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, TRUE, 0x18, FALSE); + + // sw mechanism + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + else + { + halbtc8188c2ant_CoexAllOff(pBtCoexist); + } +} + +VOID +halbtc8188c2ant_ActionA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) + { + halbtc8188c2ant_ActionA2dpBc4(pBtCoexist); + } + else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) + { + halbtc8188c2ant_ActionA2dpBc8(pBtCoexist); + } +} + +VOID +halbtc8188c2ant_ActionPanBc4( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0); + if(bBtHsOn) + { + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); + } + else + { + if(pCoexSta->bBtBusy && bWifiBusy) + { + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x10); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); + } + else + { + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); + } + } + // sw mechanism + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); +} + +VOID +halbtc8188c2ant_ActionPanBc8( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE; + u1Byte wifiRssiState; + u4Byte wifiBw, wifiTrafficDir; + s4Byte wifiRssi; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); + + if(bBtHsOn) + { + halbtc8188c2ant_CoexAllOff(pBtCoexist); + } + else + { + wifiRssiState = halbtc8188c2ant_WifiRssiState(pBtCoexist, 0, 3, 25, 50); + + if(pCoexSta->bBtBusy && bWifiBusy) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + // fw mechanism first + if(pCoexSta->bBtUplink) + { + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x20); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); + } + else + { + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); + } + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + } + else + { + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); + } + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + if(pCoexSta->bBtUplink) + { + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + else + { + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20); + } + } + else if( (wifiRssiState == BTC_RSSI_STATE_MEDIUM) || + (wifiRssiState == BTC_RSSI_STATE_STAY_MEDIUM) ) + { + // fw mechanism first + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x20); + + if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) + { + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); + } + else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) + { + if(BTC_WIFI_BW_HT40 == wifiBw) + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);//BT_FW_NAV_ON); + else + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); + } + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + } + else + { + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); + } + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + else + { + // fw mechanism first + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x20); + + if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) + { + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); + } + else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) + { + if(pCoexSta->bBtUplink) + { + if(BTC_WIFI_BW_HT40 == wifiBw) + { + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);//BT_FW_NAV_ON); + } + else + { + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); + } + } + else + { + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); + } + } + // sw mechanism + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + } + else if(pCoexSta->bBtBusy && !bWifiBusy && (wifiRssi < 30)) + { + // fw mechanism first + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x0a, 0x20); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); + // sw mechanism + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + else + { + halbtc8188c2ant_CoexAllOff(pBtCoexist); + } + } +} + +VOID +halbtc8188c2ant_ActionPan( + IN PBTC_COEXIST pBtCoexist + ) +{ + if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) + { + halbtc8188c2ant_ActionPanBc4(pBtCoexist); + } + else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) + { + halbtc8188c2ant_ActionPanBc8(pBtCoexist); + } +} + +VOID +halbtc8188c2ant_ActionHid( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte wifiBw, wifiTrafficDir; + BOOLEAN bWifiBusy=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); + if(BTC_WIFI_BW_LEGACY == wifiBw) + { + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); + + halbtc8188c2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0); + } + else if(!bWifiBusy) + { + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0); + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); + } + else if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) + { + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); + + halbtc8188c2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0); + } + else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) + { + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0); + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); + } + // sw mechanism + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); +} + + +VOID +halbtc8188c2ant_ActionSco( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState; + u4Byte wifiBw; + + if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) + { + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0); + + // fw mechanism + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); + + // sw mechanism + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) + { + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + // fw mechanism first + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); + + // sw mechanism + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + else + { + wifiRssiState = halbtc8188c2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0); + // fw mechanism first + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + else + { + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + } + } +} + +VOID +halbtc8188c2ant_ActionHidA2dpBc4( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState; + u4Byte wifiBw, wifiTrafficDir; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); + + if(pCoexSta->bBtBusy) + { + if(BTC_WIFI_BW_HT40 == wifiBw) + { + // fw mechanism first + if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) + { + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x7, 0x20); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x20, FALSE); + } + else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) + { + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); + } + + // sw mechanism + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); + } + else + { + wifiRssiState = halbtc8188c2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0); + // fw mechanism first + if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) + { + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x7, 0x20); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x20, FALSE); + } + else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) + { + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); + } + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); + } + else + { + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); + } + } + } + else + { + halbtc8188c2ant_CoexAllOff(pBtCoexist); + } +} +VOID +halbtc8188c2ant_ActionHidA2dpBc8( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState; + u4Byte wifiBw; + + if(pCoexSta->bBtBusy) + { + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + // fw mechanism first + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); + + // sw mechanism + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); + } + else + { + wifiRssiState = halbtc8188c2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0); + // fw mechanism + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); + } + else + { + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); + } + } + } + else + { + halbtc8188c2ant_CoexAllOff(pBtCoexist); + } +} + +VOID +halbtc8188c2ant_ActionHidA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) + { + halbtc8188c2ant_ActionHidA2dpBc4(pBtCoexist); + } + else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) + { + halbtc8188c2ant_ActionHidA2dpBc8(pBtCoexist); + } +} + +VOID +halbtc8188c2ant_ActionHidPanBc4( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE; + u4Byte wifiBw, wifiTrafficDir; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + if(bBtHsOn) + { + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); + + halbtc8188c2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0); + } + else + { + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); + if(BTC_WIFI_BW_LEGACY == wifiBw) + { + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); + + halbtc8188c2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0); + } + else if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) + { + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); + + halbtc8188c2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0); + } + else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) + { + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0); + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x10); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); + } + else if(!bWifiBusy) + { + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0); + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); + } + } + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); +} +VOID +halbtc8188c2ant_ActionHidPanBc8( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE; + u1Byte wifiRssiState; + u4Byte wifiBw, wifiTrafficDir; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + if(!bBtHsOn) + { + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + wifiRssiState = halbtc8188c2ant_WifiRssiState(pBtCoexist, 0, 2, 25, 0); + if((pCoexSta->bBtBusy && bWifiBusy)) + { + // fw mechanism first + if(pCoexSta->bBtUplink) + { + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x15, 0x20); + } + else + { + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x10, 0x20); + } + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + else + { + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + } + else + { + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + } + else + { + halbtc8188c2ant_CoexAllOff(pBtCoexist); + } + } + else + { + if(BTC_INTF_USB == pBtCoexist->chipInterface) + { + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); + if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) + { + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); + + halbtc8188c2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); + } + else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) + { + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); + } + } + else + { + if(pCoexSta->bBtBusy) + { + // fw mechanism + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); + + // sw mechanism + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20); + } + else + { + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + } + } +} + +VOID +halbtc8188c2ant_ActionHidPan( + IN PBTC_COEXIST pBtCoexist + ) +{ + if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) + { + halbtc8188c2ant_ActionHidPanBc4(pBtCoexist); + } + else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) + { + halbtc8188c2ant_ActionHidPanBc8(pBtCoexist); + } +} + +VOID +halbtc8188c2ant_ActionPanA2dpBc4( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE; + u1Byte wifiRssiState; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0); + if(bBtHsOn) + { + if(pCoexSta->bBtBusy) + { + // fw mechanism + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); + + // sw mechanism + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20); + } + else + { + halbtc8188c2ant_CoexAllOff(pBtCoexist); + } + } + else + { + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + if(pCoexSta->bBtBusy && bWifiBusy) + { + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x10); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); + } + else + { + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); + } + // sw mechanism + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } +} +VOID +halbtc8188c2ant_ActionPanA2dpBc8( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE; + u1Byte wifiRssiState; + u4Byte wifiBw; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + if(!bBtHsOn) + { + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + wifiRssiState = halbtc8188c2ant_WifiRssiState(pBtCoexist, 0, 2, 25, 0); + if((pCoexSta->bBtBusy && bWifiBusy)) + { + // fw mechanism first + if(pCoexSta->bBtUplink) + { + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x15, 0x20); + } + else + { + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x10, 0x20); + } + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + else + { + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + } + else + { + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + } + else + { + halbtc8188c2ant_CoexAllOff(pBtCoexist); + } + } + else + { + if(pCoexSta->bBtBusy) + { + // fw mechanism + halbtc8188c2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8188c2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); + + // sw mechanism + halbtc8188c2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20); + } + else + { + halbtc8188c2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + } +} + +VOID +halbtc8188c2ant_ActionPanA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) + { + halbtc8188c2ant_ActionPanA2dpBc4(pBtCoexist); + } + else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) + { + halbtc8188c2ant_ActionPanA2dpBc8(pBtCoexist); + } +} + +//============================================================ +// extern function start with EXhalbtc8188c2ant_ +//============================================================ +VOID +EXhalbtc8188c2ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ) +{ +} + +VOID +EXhalbtc8188c2ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ) +{ + u1Byte u1Tmp=0; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 2Ant Init HW Config!!\n")); + + // backup rf 0x1e value + pCoexDm->btRf0x1eBackup = + pBtCoexist->fBtcGetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xf0); + + if( (BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) || + (BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) ) + { + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4fd) & BIT0; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x4fd, u1Tmp); + + halbtc8188c2ant_CoexTable(pBtCoexist, FORCE_EXEC, 0xaaaa9aaa, 0xffbd0040, 0x40000010); + } +} + +VOID +EXhalbtc8188c2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Coex Mechanism Init!!\n")); + + halbtc8188c2ant_InitCoexDm(pBtCoexist); +} + +VOID +EXhalbtc8188c2ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + pu1Byte cliBuf=pBtCoexist->cliBuf; + u1Byte u1Tmp[4], i, btInfoExt, psTdmaCase=0; + u4Byte u4Tmp[4]; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:", \ + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum); + CL_PRINTF(cliBuf); + + if(pBtCoexist->bManualControl) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "[Action Manual control]!!"); + CL_PRINTF(cliBuf); + } + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \ + ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion); + CL_PRINTF(cliBuf); + + // wifi status + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Wifi Status]============"); + CL_PRINTF(cliBuf); + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[BT Status]============"); + CL_PRINTF(cliBuf); + + if(pStackInfo->bProfileNotified) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP", \ + pStackInfo->bScoExist, pStackInfo->bHidExist, pStackInfo->bPanExist, pStackInfo->bA2dpExist); + CL_PRINTF(cliBuf); + + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO); + } + + // Sw mechanism + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============"); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", \ + pCoexDm->bCurAgcTableEn, pCoexDm->bCurAdcBackOff, pCoexDm->bCurDacSwingOn, pCoexDm->curDacSwingLvl); + CL_PRINTF(cliBuf); + + // Fw mechanism + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============"); + CL_PRINTF(cliBuf); + + // Hw setting + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "RF-A, 0x1e initVal", \ + pCoexDm->btRf0x1eBackup); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x40); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x40", \ + u1Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc50); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", \ + u4Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c4); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c8); + u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6cc); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x6c4/0x6c8/0x6cc(coexTable)", \ + u4Tmp[0], u4Tmp[1], u4Tmp[2]); + CL_PRINTF(cliBuf); + + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + + +VOID +EXhalbtc8188c2ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_IPS_ENTER == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS ENTER notify\n")); + halbtc8188c2ant_CoexAllOff(pBtCoexist); + } + else if(BTC_IPS_LEAVE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS LEAVE notify\n")); + //halbtc8188c2ant_InitCoexDm(pBtCoexist); + } +} + +VOID +EXhalbtc8188c2ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_LPS_ENABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS ENABLE notify\n")); + halbtc8188c2ant_CoexAllOff(pBtCoexist); + } + else if(BTC_LPS_DISABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS DISABLE notify\n")); + halbtc8188c2ant_InitCoexDm(pBtCoexist); + } +} + +VOID +EXhalbtc8188c2ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_SCAN_START == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n")); + } + else if(BTC_SCAN_FINISH == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n")); + } +} + +VOID +EXhalbtc8188c2ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_ASSOCIATE_START == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n")); + } + else if(BTC_ASSOCIATE_FINISH == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n")); + } +} + +VOID +EXhalbtc8188c2ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_MEDIA_CONNECT == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA connect notify\n")); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA disconnect notify\n")); + } + +} + +VOID +EXhalbtc8188c2ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(type == BTC_PACKET_DHCP) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], DHCP Packet notify\n")); + } +} + +VOID +EXhalbtc8188c2ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ) +{ +} + +VOID +EXhalbtc8188c2ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Halt notify\n")); + + EXhalbtc8188c2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); +} + +VOID +EXhalbtc8188c2ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte algorithm; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 2Ant Periodical!!\n")); + + // NOTE: + // sw mechanism must be done after fw mechanism + // + + if((BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) || + (BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) ) + { + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_GET_BT_RSSI, NULL); + + halbtc8188c2ant_MonitorBtState(pBtCoexist); + algorithm = halbtc8188c2ant_ActionAlgorithm(pBtCoexist); + pCoexDm->curAlgorithm = algorithm; + switch(pCoexDm->curAlgorithm) + { + case BT_8188C_2ANT_COEX_ALGO_SCO: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = SCO\n")); + halbtc8188c2ant_ActionSco(pBtCoexist); + break; + case BT_8188C_2ANT_COEX_ALGO_HID: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID\n")); + halbtc8188c2ant_ActionHid(pBtCoexist); + break; + case BT_8188C_2ANT_COEX_ALGO_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = A2DP\n")); + halbtc8188c2ant_ActionA2dp(pBtCoexist); + break; + case BT_8188C_2ANT_COEX_ALGO_PAN: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN\n")); + halbtc8188c2ant_ActionPan(pBtCoexist); + break; + case BT_8188C_2ANT_COEX_ALGO_HID_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP\n")); + halbtc8188c2ant_ActionHidA2dp(pBtCoexist); + break; + case BT_8188C_2ANT_COEX_ALGO_HID_PAN: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN+HID\n")); + halbtc8188c2ant_ActionHidPan(pBtCoexist); + break; + case BT_8188C_2ANT_COEX_ALGO_PAN_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN+A2DP\n")); + halbtc8188c2ant_ActionPanA2dp(pBtCoexist); + break; + default: + break; + } + } +} + + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8188c2Ant.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8188c2Ant.h new file mode 100644 index 000000000..79d0ebc35 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8188c2Ant.h @@ -0,0 +1,150 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//=========================================== +// The following is for 8188C 2Ant BT Co-exist definition +//=========================================== +#define BTC_RSSI_COEX_THRESH_TOL_8188C_2ANT 6 + +typedef enum _BT_INFO_SRC_8188C_2ANT{ + BT_INFO_SRC_8188C_2ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8188C_2ANT_BT_RSP = 0x1, + BT_INFO_SRC_8188C_2ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8188C_2ANT_MAX +}BT_INFO_SRC_8188C_2ANT,*PBT_INFO_SRC_8188C_2ANT; + +typedef enum _BT_8188C_2ANT_BT_STATUS{ + BT_8188C_2ANT_BT_STATUS_IDLE = 0x0, + BT_8188C_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8188C_2ANT_BT_STATUS_NON_IDLE = 0x2, + BT_8188C_2ANT_BT_STATUS_MAX +}BT_8188C_2ANT_BT_STATUS,*PBT_8188C_2ANT_BT_STATUS; + +typedef enum _BT_8188C_2ANT_COEX_ALGO{ + BT_8188C_2ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8188C_2ANT_COEX_ALGO_SCO = 0x1, + BT_8188C_2ANT_COEX_ALGO_HID = 0x2, + BT_8188C_2ANT_COEX_ALGO_A2DP = 0x3, + BT_8188C_2ANT_COEX_ALGO_PAN = 0x4, + BT_8188C_2ANT_COEX_ALGO_HID_A2DP = 0x5, + BT_8188C_2ANT_COEX_ALGO_HID_PAN = 0x6, + BT_8188C_2ANT_COEX_ALGO_PAN_A2DP = 0x7, + BT_8188C_2ANT_COEX_ALGO_MAX +}BT_8188C_2ANT_COEX_ALGO,*PBT_8188C_2ANT_COEX_ALGO; + +typedef struct _COEX_DM_8188C_2ANT{ + // fw mechanism + BOOLEAN bPreBalanceOn; + BOOLEAN bCurBalanceOn; + + // diminishWifi + BOOLEAN bPreDacOn; + BOOLEAN bCurDacOn; + BOOLEAN bPreInterruptOn; + BOOLEAN bCurInterruptOn; + u1Byte preFwDacSwingLvl; + u1Byte curFwDacSwingLvl; + BOOLEAN bPreNavOn; + BOOLEAN bCurNavOn; + + // sw mechanism + BOOLEAN bPreRfRxLpfShrink; + BOOLEAN bCurRfRxLpfShrink; + u4Byte btRf0x1eBackup; + BOOLEAN bPreLowPenaltyRa; + BOOLEAN bCurLowPenaltyRa; + BOOLEAN bPreDacSwingOn; + u4Byte preDacSwingLvl; + BOOLEAN bCurDacSwingOn; + u4Byte curDacSwingLvl; + BOOLEAN bPreAdcBackOff; + BOOLEAN bCurAdcBackOff; + BOOLEAN bPreAgcTableEn; + BOOLEAN bCurAgcTableEn; + //u4Byte preVal0x6c0; + //u4Byte curVal0x6c0; + u4Byte preVal0x6c4; + u4Byte curVal0x6c4; + u4Byte preVal0x6c8; + u4Byte curVal0x6c8; + u4Byte preVal0x6cc; + u4Byte curVal0x6cc; + //BOOLEAN bLimitedDig; + + // algorithm related + u1Byte preAlgorithm; + u1Byte curAlgorithm; + //u1Byte btStatus; + //u1Byte wifiChnlInfo[3]; +} COEX_DM_8188C_2ANT, *PCOEX_DM_8188C_2ANT; + +typedef struct _COEX_STA_8188C_2ANT{ + u1Byte preWifiRssiState[4]; + BOOLEAN bBtBusy; + BOOLEAN bBtUplink; + BOOLEAN bBtDownLink; + BOOLEAN bA2dpBusy; +}COEX_STA_8188C_2ANT, *PCOEX_STA_8188C_2ANT; + +//=========================================== +// The following is interface which will notify coex module. +//=========================================== +VOID +EXhalbtc8188c2ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8188c2ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ); +VOID +EXhalbtc8188c2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8188c2ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8188c2ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8188c2ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8188c2ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8188c2ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8188c2ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8188c2ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8188c2ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8188c2ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ); +VOID +EXhalbtc8188c2ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ); diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8192d2Ant.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8192d2Ant.c new file mode 100644 index 000000000..c81127756 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8192d2Ant.c @@ -0,0 +1,1993 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//============================================================ +// Description: +// +// This file is for 92D BT 2 Antenna Co-exist mechanism +// +// By cosa 02/11/2011 +// +//============================================================ + +//============================================================ +// include files +//============================================================ +#include "Mp_Precomp.h" + +#if WPP_SOFTWARE_TRACE +#include "HalBtc8192d2Ant.tmh" +#endif + +#if(BT_30_SUPPORT == 1) +//============================================================ +// Global variables, these are static variables +//============================================================ +static COEX_DM_8192D_2ANT GLCoexDm8192d2Ant; +static PCOEX_DM_8192D_2ANT pCoexDm=&GLCoexDm8192d2Ant; +static COEX_STA_8192D_2ANT GLCoexSta8192d2Ant; +static PCOEX_STA_8192D_2ANT pCoexSta=&GLCoexSta8192d2Ant; + +//============================================================ +// local function start with btdm_ +//============================================================ +u1Byte +halbtc8192d2ant_WifiRssiState( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte index, + IN u1Byte levelNum, + IN u1Byte rssiThresh, + IN u1Byte rssiThresh1 + ) +{ + s4Byte wifiRssi=0; + u1Byte wifiRssiState=pCoexSta->preWifiRssiState[index]; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); + + if(levelNum == 2) + { + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8192D_2ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else + { + if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + else if(levelNum == 3) + { + if(rssiThresh > rssiThresh1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi RSSI thresh error!!\n")); + return pCoexSta->preWifiRssiState[index]; + } + + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8192D_2ANT)) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_MEDIUM) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_MEDIUM)) + { + if(wifiRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8192D_2ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_MEDIUM; + } + } + else + { + if(wifiRssi < rssiThresh1) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + + pCoexSta->preWifiRssiState[index] = wifiRssiState; + + return wifiRssiState; +} + +u1Byte +halbtc8192d2ant_ActionAlgorithm( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + BOOLEAN bBtHsOn=FALSE; + u1Byte algorithm=BT_8192D_2ANT_COEX_ALGO_UNDEFINED; + u1Byte numOfDiffProfile=0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + if(!pStackInfo->bBtLinkExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], No profile exists!!!\n")); + return algorithm; + } + + if(pStackInfo->bScoExist) + numOfDiffProfile++; + if(pStackInfo->bHidExist) + numOfDiffProfile++; + if(pStackInfo->bPanExist) + numOfDiffProfile++; + if(pStackInfo->bA2dpExist) + numOfDiffProfile++; + + if(pStackInfo->bScoExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO algorithm\n")); + algorithm = BT_8192D_2ANT_COEX_ALGO_SCO; + } + else + { + if(numOfDiffProfile == 1) + { + if(pStackInfo->bHidExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID only\n")); + algorithm = BT_8192D_2ANT_COEX_ALGO_HID; + } + else if(pStackInfo->bA2dpExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP only\n")); + algorithm = BT_8192D_2ANT_COEX_ALGO_A2DP; + } + else if(pStackInfo->bPanExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN only\n")); + algorithm = BT_8192D_2ANT_COEX_ALGO_PAN; + } + } + else + { + if( pStackInfo->bHidExist && + pStackInfo->bA2dpExist ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP\n")); + algorithm = BT_8192D_2ANT_COEX_ALGO_HID_A2DP; + } + else if( pStackInfo->bHidExist && + pStackInfo->bPanExist ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + PAN\n")); + algorithm = BT_8192D_2ANT_COEX_ALGO_HID_PAN; + } + else if( pStackInfo->bPanExist && + pStackInfo->bA2dpExist ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN + A2DP\n")); + algorithm = BT_8192D_2ANT_COEX_ALGO_PAN_A2DP; + } + } + } + return algorithm; +} + +VOID +halbtc8192d2ant_SetFwBalance( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bBalanceOn, + IN u1Byte ms0, + IN u1Byte ms1 + ) +{ + u1Byte H2C_Parameter[3] ={0}; + + if(bBalanceOn) + { + H2C_Parameter[2] = 1; + H2C_Parameter[1] = ms1; + H2C_Parameter[0] = ms0; + } + else + { + H2C_Parameter[2] = 0; + H2C_Parameter[1] = 0; + H2C_Parameter[0] = 0; + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Balance=[%s:%dms:%dms], write 0xc=0x%x\n", + bBalanceOn?"ON":"OFF", ms0, ms1, + H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0xc, 3, H2C_Parameter); +} + +VOID +halbtc8192d2ant_Balance( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bBalanceOn, + IN u1Byte ms0, + IN u1Byte ms1 + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Balance %s\n", + (bForceExec? "force to":""), (bBalanceOn? "ON":"OFF"))); + pCoexDm->bCurBalanceOn = bBalanceOn; + + if(!bForceExec) + { + if(pCoexDm->bPreBalanceOn == pCoexDm->bCurBalanceOn) + return; + } + halbtc8192d2ant_SetFwBalance(pBtCoexist, bBalanceOn, ms0, ms1); + + pCoexDm->bPreBalanceOn = pCoexDm->bCurBalanceOn; +} + +VOID +halbtc8192d2ant_SetFwDiminishWifi( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bDacOn, + IN BOOLEAN bInterruptOn, + IN u1Byte fwDacSwingLvl, + IN BOOLEAN bNavOn + ) +{ + u1Byte H2C_Parameter[3] ={0}; + + if((pBtCoexist->stackInfo.minBtRssi <= -5) && (fwDacSwingLvl == 0x20)) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], DiminishWiFi 0x20 original, but set 0x18 for Low RSSI!\n")); + fwDacSwingLvl = 0x18; + } + + H2C_Parameter[2] = 0; + H2C_Parameter[1] = fwDacSwingLvl; + H2C_Parameter[0] = 0; + if(bDacOn) + { + H2C_Parameter[2] |= 0x01; //BIT0 + if(bInterruptOn) + { + H2C_Parameter[2] |= 0x02; //BIT1 + } + } + if(bNavOn) + { + H2C_Parameter[2] |= 0x08; //BIT3 + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], bDacOn=%s, bInterruptOn=%s, bNavOn=%s, write 0x12=0x%x\n", + (bDacOn?"ON":"OFF"), (bInterruptOn?"ON":"OFF"), (bNavOn?"ON":"OFF"), + (H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2]))); + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x12, 3, H2C_Parameter); +} + + +VOID +halbtc8192d2ant_DiminishWifi( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bDacOn, + IN BOOLEAN bInterruptOn, + IN u1Byte fwDacSwingLvl, + IN BOOLEAN bNavOn + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s set Diminish Wifi, bDacOn=%s, bInterruptOn=%s, fwDacSwingLvl=%d, bNavOn=%s\n", + (bForceExec? "force to":""), (bDacOn? "ON":"OFF"), (bInterruptOn? "ON":"OFF"), fwDacSwingLvl, (bNavOn? "ON":"OFF"))); + + pCoexDm->bCurDacOn = bDacOn; + pCoexDm->bCurInterruptOn = bInterruptOn; + pCoexDm->curFwDacSwingLvl = fwDacSwingLvl; + pCoexDm->bCurNavOn = bNavOn; + + if(!bForceExec) + { + if( (pCoexDm->bPreDacOn==pCoexDm->bCurDacOn) && + (pCoexDm->bPreInterruptOn==pCoexDm->bCurInterruptOn) && + (pCoexDm->preFwDacSwingLvl==pCoexDm->curFwDacSwingLvl) && + (pCoexDm->bPreNavOn==pCoexDm->bCurNavOn) ) + return; + } + halbtc8192d2ant_SetFwDiminishWifi(pBtCoexist, bDacOn, bInterruptOn, fwDacSwingLvl, bNavOn); + + pCoexDm->bPreDacOn = pCoexDm->bCurDacOn; + pCoexDm->bPreInterruptOn = pCoexDm->bCurInterruptOn; + pCoexDm->preFwDacSwingLvl = pCoexDm->curFwDacSwingLvl; + pCoexDm->bPreNavOn = pCoexDm->bCurNavOn; +} + +VOID +halbtc8192d2ant_SetSwRfRxLpfCorner( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bRxRfShrinkOn + ) +{ + if(bRxRfShrinkOn) + { + //Shrink RF Rx LPF corner + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Shrink RF Rx LPF corner!!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, 0xf2ff7); + } + else + { + //Resume RF Rx LPF corner + // After initialized, we can use pCoexDm->btRf0x1eBackup + if(pBtCoexist->bInitilized) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Resume RF Rx LPF corner!!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, pCoexDm->btRf0x1eBackup); + } + } +} + + +VOID +halbtc8192d2ant_RfShrink( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bRxRfShrinkOn + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Rx RF Shrink = %s\n", + (bForceExec? "force to":""), ((bRxRfShrinkOn)? "ON":"OFF"))); + pCoexDm->bCurRfRxLpfShrink = bRxRfShrinkOn; + + if(!bForceExec) + { + if(pCoexDm->bPreRfRxLpfShrink == pCoexDm->bCurRfRxLpfShrink) + return; + } + halbtc8192d2ant_SetSwRfRxLpfCorner(pBtCoexist, pCoexDm->bCurRfRxLpfShrink); + + pCoexDm->bPreRfRxLpfShrink = pCoexDm->bCurRfRxLpfShrink; +} + +VOID +halbtc8192d2ant_SetSwPenaltyTxRateAdaptive( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bLowPenaltyRa + ) +{ + u1Byte tmpU1; + + tmpU1 = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4fd); + if(bLowPenaltyRa) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set low penalty!!\n")); + tmpU1 &= ~BIT2; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set normal!!\n")); + tmpU1 |= BIT2; + } + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x4fd, tmpU1); +} + +VOID +halbtc8192d2ant_LowPenaltyRa( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bLowPenaltyRa + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn LowPenaltyRA = %s\n", + (bForceExec? "force to":""), ((bLowPenaltyRa)? "ON":"OFF"))); + pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa; + + if(!bForceExec) + { + if(pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa) + return; + } + halbtc8192d2ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa); + + pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa; +} + +VOID +halbtc8192d2ant_SetSwFullTimeDacSwing( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bSwDacSwingOn, + IN u4Byte swDacSwingLvl + ) +{ + u4Byte dacSwingLvl; + + if(bSwDacSwingOn) + { + if((pBtCoexist->stackInfo.minBtRssi <= -5) && (swDacSwingLvl == 0x20)) + { + dacSwingLvl = 0x18; + } + else + { + dacSwingLvl = swDacSwingLvl; + } + pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xfc000000, dacSwingLvl); + } + else + { + pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xfc000000, 0x30); + } +} + +VOID +halbtc8192d2ant_DacSwing( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bDacSwingOn, + IN u4Byte dacSwingLvl + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn DacSwing=%s, dacSwingLvl=0x%x\n", + (bForceExec? "force to":""), ((bDacSwingOn)? "ON":"OFF"), dacSwingLvl)); + pCoexDm->bCurDacSwingOn = bDacSwingOn; + pCoexDm->curDacSwingLvl = dacSwingLvl; + + if(!bForceExec) + { + if( (pCoexDm->bPreDacSwingOn == pCoexDm->bCurDacSwingOn) && + (pCoexDm->preDacSwingLvl == pCoexDm->curDacSwingLvl) ) + return; + } + delay_ms(30); + halbtc8192d2ant_SetSwFullTimeDacSwing(pBtCoexist, bDacSwingOn, dacSwingLvl); + + pCoexDm->bPreDacSwingOn = pCoexDm->bCurDacSwingOn; + pCoexDm->preDacSwingLvl = pCoexDm->curDacSwingLvl; +} + +VOID +halbtc8192d2ant_SetAdcBackOff( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bAdcBackOff + ) +{ + if(bAdcBackOff) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level On!\n")); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc04,0x3a07611); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level Off!\n")); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc04,0x3a05611); + } +} + +VOID +halbtc8192d2ant_AdcBackOff( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bAdcBackOff + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn AdcBackOff = %s\n", + (bForceExec? "force to":""), ((bAdcBackOff)? "ON":"OFF"))); + pCoexDm->bCurAdcBackOff = bAdcBackOff; + + if(!bForceExec) + { + if(pCoexDm->bPreAdcBackOff == pCoexDm->bCurAdcBackOff) + return; + } + halbtc8192d2ant_SetAdcBackOff(pBtCoexist, pCoexDm->bCurAdcBackOff); + + pCoexDm->bPreAdcBackOff = pCoexDm->bCurAdcBackOff; +} + +VOID +halbtc8192d2ant_SetAgcTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bAgcTableEn + ) +{ + u1Byte rssiAdjustVal=0; + + if(bAgcTableEn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table On!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1a, 0xfffff, 0xa99); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xd4000); + + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b000001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b010001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b020001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b030001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b040001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b050001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b060001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b070001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b080001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b090001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b0A0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7b0B0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7a0C0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x790D0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x780E0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x770F0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x76100001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x75110001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x74120001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x73130001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x72140001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x71150001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x70160001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6f170001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6e180001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6d190001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6c1A0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6b1B0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6a1C0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x691D0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x4f1E0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x4e1F0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x4d200001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x4c210001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x4b220001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x4a230001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x49240001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x48250001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x47260001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x46270001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x45280001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x44290001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x432A0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x422B0001); + + rssiAdjustVal = 12; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table Off!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1a, 0xfffff, 0x30a99); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xdc000); + + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B000001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B010001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B020001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B030001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B040001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B050001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7B060001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x7A070001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x79080001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x78090001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x770A0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x760B0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x750C0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x740D0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x730E0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x720F0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x71100001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x70110001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6F120001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6E130001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6D140001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6C150001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6B160001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6A170001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x69180001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x68190001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x671A0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x661B0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x651C0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x641D0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x631E0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x621F0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x61200001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x60210001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x49220001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x48230001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x47240001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x46250001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x45260001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x44270001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x43280001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x42290001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x412A0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x402B0001); + } + + // set rssiAdjustVal for wifi module. + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, &rssiAdjustVal); +} + + + +VOID +halbtc8192d2ant_AgcTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bAgcTableEn + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s %s Agc Table\n", + (bForceExec? "force to":""), ((bAgcTableEn)? "Enable":"Disable"))); + pCoexDm->bCurAgcTableEn = bAgcTableEn; + + if(!bForceExec) + { + if(pCoexDm->bPreAgcTableEn == pCoexDm->bCurAgcTableEn) + return; + } + halbtc8192d2ant_SetAgcTable(pBtCoexist, bAgcTableEn); + + pCoexDm->bPreAgcTableEn = pCoexDm->bCurAgcTableEn; +} + +VOID +halbtc8192d2ant_SetCoexTable( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte val0x6c4, + IN u4Byte val0x6c8, + IN u4Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], set coex table, set 0x6c4=0x%x\n", val0x6c4)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c4, val0x6c4); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, val0x6c8); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6cc, val0x6cc); +} + +VOID +halbtc8192d2ant_CoexTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u4Byte val0x6c4, + IN u4Byte val0x6c8, + IN u4Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s write Coex Table 0x6c4=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n", + (bForceExec? "force to":""), val0x6c4, val0x6c8, val0x6cc)); + pCoexDm->curVal0x6c4 = val0x6c4; + pCoexDm->curVal0x6c8 = val0x6c8; + pCoexDm->curVal0x6cc = val0x6cc; + + if(!bForceExec) + { + if( (pCoexDm->preVal0x6c4 == pCoexDm->curVal0x6c4) && + (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) && + (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) ) + return; + } + halbtc8192d2ant_SetCoexTable(pBtCoexist, val0x6c4, val0x6c8, val0x6cc); + + pCoexDm->preVal0x6c4 = pCoexDm->curVal0x6c4; + pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8; + pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc; +} + +VOID +halbtc8192d2ant_CoexAllOff( + IN PBTC_COEXIST pBtCoexist + ) +{ + // fw mechanism + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); + + // sw mechanism + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); +} +VOID +halbtc8192d2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ +} + +VOID +halbtc8192d2ant_MonitorBtEnableDisable( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte btActive + ) +{ + static BOOLEAN bPreBtDisabled=FALSE; + static u4Byte btDisableCnt=0; + BOOLEAN bBtDisabled=FALSE, bForceToRoam=FALSE; + u4Byte u4Tmp=0; + + // This function check if bt is disabled + if(btActive) + { + btDisableCnt = 0; + bBtDisabled = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is enabled !!\n")); + } + else + { + btDisableCnt++; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], bt all counters=0, %d times!!\n", + btDisableCnt)); + if(btDisableCnt >= 2) + { + bBtDisabled = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is disabled !!\n")); + } + } + if(bPreBtDisabled != bBtDisabled) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is from %s to %s!!\n", + (bPreBtDisabled ? "disabled":"enabled"), + (bBtDisabled ? "disabled":"enabled"))); + + bForceToRoam = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_FORCE_TO_ROAM, &bForceToRoam); + + bPreBtDisabled = bBtDisabled; + } +} + +VOID +halbtc8192d2ant_MonitorBtState( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN stateChange=FALSE; + u4Byte BT_Polling, Ratio_Act, Ratio_STA; + u4Byte BT_Active, BT_State; + u4Byte regBTActive=0, regBTState=0, regBTPolling=0; + u4Byte btBusyThresh=0; + u4Byte fwVer=0; + static BOOLEAN bBtBusyTraffic=FALSE; + BOOLEAN bRejApAggPkt=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], FirmwareVersion = 0x%x(%d)\n", fwVer, fwVer)); + + regBTActive = 0x444; + regBTState = 0x448; + regBTPolling = 0x44c; + + btBusyThresh = 40; + + BT_Active = pBtCoexist->fBtcRead4Byte(pBtCoexist, regBTActive); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT_Active(0x%x)=0x%x\n", regBTActive, BT_Active)); + BT_Active = BT_Active & 0x00ffffff; + + BT_State = pBtCoexist->fBtcRead4Byte(pBtCoexist, regBTState); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT_State(0x%x)=0x%x\n", regBTState, BT_State)); + BT_State = BT_State & 0x00ffffff; + + BT_Polling = pBtCoexist->fBtcRead4Byte(pBtCoexist, regBTPolling); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT_Polling(0x%x)=0x%x\n", regBTPolling, BT_Polling)); + + if(BT_Active==0xffffffff && BT_State==0xffffffff && BT_Polling==0xffffffff ) + return; + + // 2011/05/04 MH For Slim combo test meet a problem. Surprise remove and WLAN is running + // DHCP process. At the same time, the register read value might be zero. And cause BSOD 0x7f + // EXCEPTION_DIVIDED_BY_ZERO. In This case, the stack content may always be wrong due to + // HW divide trap. + if (BT_Polling==0) + return; + + halbtc8192d2ant_MonitorBtEnableDisable(pBtCoexist, BT_Active); + + Ratio_Act = BT_Active*1000/BT_Polling; + Ratio_STA = BT_State*1000/BT_Polling; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Ratio_Act=%d\n", Ratio_Act)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Ratio_STA=%d\n", Ratio_STA)); + + if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) + { + if(Ratio_STA < 60) // BT PAN idle + { + } + else + { + // Check if BT PAN (under BT 2.1) is uplink or downlink + if((Ratio_Act/Ratio_STA) < 2) + { // BT PAN Uplink + pCoexSta->bBtUplink = TRUE; + } + else + { // BT PAN downlink + pCoexSta->bBtUplink = FALSE; + } + } + } + + // Check BT is idle or not + if(!pBtCoexist->stackInfo.bBtLinkExist) + { + pCoexSta->bBtBusy = FALSE; + } + else + { + if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) + { + if(Ratio_Act<20) + { + pCoexSta->bBtBusy = FALSE; + } + else + { + pCoexSta->bBtBusy = TRUE; + } + } + else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) + { + if(Ratio_STA < btBusyThresh) + { + pCoexSta->bBtBusy = FALSE; + } + else + { + pCoexSta->bBtBusy = TRUE; + } + + if( (Ratio_STA < btBusyThresh) || + (Ratio_Act<180 && Ratio_STA<130) ) + { + pCoexSta->bA2dpBusy = FALSE; + } + else + { + pCoexSta->bA2dpBusy = TRUE; + } + } + } + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &pCoexSta->bBtBusy); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_LIMITED_DIG, &pCoexSta->bBtBusy); + + if(bBtBusyTraffic != pCoexSta->bBtBusy) + { // BT idle or BT non-idle + bBtBusyTraffic = pCoexSta->bBtBusy; + stateChange = TRUE; + } + + if(stateChange) + { + if(!pCoexSta->bBtBusy) + { + halbtc8192d2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_CoexAllOff(pBtCoexist); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0); + } + else + { + halbtc8192d2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8192d2ant_RfShrink(pBtCoexist, NORMAL_EXEC, TRUE); + } + } + + if(stateChange) + { + bRejApAggPkt = pCoexSta->bBtBusy; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, &bRejApAggPkt); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); + } +} + +VOID +halbtc8192d2ant_ActionA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1=BTC_RSSI_STATE_HIGH; + u4Byte wifiBw, wifiTrafficDir; + BOOLEAN bWifiBusy=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); + + wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0); + if(pCoexSta->bA2dpBusy && bWifiBusy) + { + if(BTC_WIFI_BW_HT40 == wifiBw) + { + wifiRssiState1 = halbtc8192d2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0); + } + else + { + if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) + { + wifiRssiState1 = halbtc8192d2ant_WifiRssiState(pBtCoexist, 1, 2, 25, 0); + } + else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) + { + wifiRssiState1 = halbtc8192d2ant_WifiRssiState(pBtCoexist, 1, 2, 40, 0); + } + } + + // fw mechanism first + if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) + { + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0xc, 0x18); + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); + } + else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) + { + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x10, 0x18); + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); + } + + // sw mechanism + if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) || + (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); + } + else + { + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + } + + if(BTC_WIFI_BW_HT40 == wifiBw) + { + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + else + { + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + } + } + else if(pCoexSta->bA2dpBusy) + { + // fw mechanism first + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, TRUE, 0x18, FALSE); + + // sw mechanism + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + else + { + halbtc8192d2ant_CoexAllOff(pBtCoexist); + } +} + +VOID +halbtc8192d2ant_ActionPan( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE; + u1Byte wifiRssiState, wifiRssiState1; + u4Byte wifiBw, wifiTrafficDir; + s4Byte wifiRssi; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); + + if(bBtHsOn) + { + halbtc8192d2ant_CoexAllOff(pBtCoexist); + } + else + { + wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 3, 25, 50); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + wifiRssiState1 = halbtc8192d2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0); + } + else + { + wifiRssiState1 = halbtc8192d2ant_WifiRssiState(pBtCoexist, 1, 2, 25, 0); + } + + if(pCoexSta->bBtBusy && bWifiBusy) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + // fw mechanism first + if(pCoexSta->bBtUplink) + { + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x20); + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); + } + else + { + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); + } + // sw mechanism + if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) || + (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); + } + else + { + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + } + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + if(pCoexSta->bBtUplink) + { + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + else + { + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20); + } + } + else if( (wifiRssiState == BTC_RSSI_STATE_MEDIUM) || + (wifiRssiState == BTC_RSSI_STATE_STAY_MEDIUM) ) + { + // fw mechanism first + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x20); + + if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) + { + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); + } + else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) + { + if(BTC_WIFI_BW_HT40 == wifiBw) + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);//BT_FW_NAV_ON); + else + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); + } + // sw mechanism + if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) || + (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); + } + else + { + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + } + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + else + { + // fw mechanism first + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x20); + + if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) + { + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); + } + else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) + { + if(pCoexSta->bBtUplink) + { + if(BTC_WIFI_BW_HT40 == wifiBw) + { + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE);//BT_FW_NAV_ON); + } + else + { + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); + } + } + else + { + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); + } + } + // sw mechanism + if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) || + (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); + } + else + { + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + } + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + } + else if(pCoexSta->bBtBusy && + !bWifiBusy && + (wifiRssi < 30)) + { + // fw mechanism first + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x0a, 0x20); + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); + // sw mechanism + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + else + { + halbtc8192d2ant_CoexAllOff(pBtCoexist); + } + } +} + + +VOID +halbtc8192d2ant_ActionHid( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiTrafficDir; + BOOLEAN bWifiBusy=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); + if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) + { + wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 45, 0); + } + else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) + { + wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 20, 0); + } + + if(pCoexSta->bBtBusy && bWifiBusy) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + // fw mechanism first + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); + + // sw mechanism + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20); + } + else + { + // fw mechanism first + if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) + { + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, TRUE, 0x18, FALSE); + } + else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) + { + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x15, 0x15); + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x30, FALSE); + } + // sw mechanism + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + } + else + { + halbtc8192d2ant_CoexAllOff(pBtCoexist); + } +} + + + +VOID +halbtc8192d2ant_ActionSco( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState; + u4Byte wifiBw; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0); + + if(BTC_WIFI_BW_HT40 == wifiBw) + { + // fw mechanism first + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); + + // sw mechanism + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + else + { + // fw mechanism first + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + else + { + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + } +} + +VOID +halbtc8192d2ant_ActionHidA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1; + u4Byte wifiBw; + + if(pCoexSta->bBtBusy) + { + wifiRssiState1 = halbtc8192d2ant_WifiRssiState(pBtCoexist, 1, 2, 35, 0); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + // fw mechanism first + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); + + + // sw mechanism + if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) || + (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); + } + else + { + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + } + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); + } + else + { + wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0); + // fw mechanism + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); + + // sw mechanism + if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) || + (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); + } + else + { + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + } + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); + } + else + { + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); + } + } + } + else + { + halbtc8192d2ant_CoexAllOff(pBtCoexist); + } +} + + +VOID +halbtc8192d2ant_ActionHidPanBc4( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE; + u4Byte wifiBw, wifiTrafficDir; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + if(bBtHsOn) + { + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); + + halbtc8192d2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0); + } + else + { + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); + if(BTC_WIFI_BW_LEGACY == wifiBw) + { + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); + + halbtc8192d2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0); + } + else if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) + { + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); + + halbtc8192d2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0); + } + else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) + { + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0); + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x10); + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); + } + else if(!bWifiBusy) + { + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0); + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); + } + } + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); +} +VOID +halbtc8192d2ant_ActionHidPanBc8( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE; + u1Byte wifiRssiState; + u4Byte wifiBw, wifiTrafficDir; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + if(!bBtHsOn) + { + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 25, 0); + if((pCoexSta->bBtBusy && bWifiBusy)) + { + // fw mechanism first + if(pCoexSta->bBtUplink) + { + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x15, 0x20); + } + else + { + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x10, 0x20); + } + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + else + { + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + } + else + { + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + } + else + { + halbtc8192d2ant_CoexAllOff(pBtCoexist); + } + } + else + { + if(BTC_INTF_USB == pBtCoexist->chipInterface) + { + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); + if(BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) + { + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); + + halbtc8192d2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x000000f0, 0x40000010); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0xa0); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); + } + else if(BTC_WIFI_TRAFFIC_RX == wifiTrafficDir) + { + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); + } + } + else + { + if(pCoexSta->bBtBusy) + { + // fw mechanism + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); + + // sw mechanism + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20); + } + else + { + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + } + } +} + +VOID +halbtc8192d2ant_ActionHidPan( + IN PBTC_COEXIST pBtCoexist + ) +{ + if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) + { + halbtc8192d2ant_ActionHidPanBc4(pBtCoexist); + } + else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) + { + halbtc8192d2ant_ActionHidPanBc8(pBtCoexist); + } +} + +VOID +halbtc8192d2ant_ActionPanA2dpBc4( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE; + u1Byte wifiRssiState; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x0); + if(bBtHsOn) + { + if(pCoexSta->bBtBusy) + { + // fw mechanism + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); + + // sw mechanism + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20); + } + else + { + halbtc8192d2ant_CoexAllOff(pBtCoexist); + } + } + else + { + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + if(pCoexSta->bBtBusy && bWifiBusy) + { + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x20, 0x10); + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); + } + else + { + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x0, FALSE); + } + // sw mechanism + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } +} +VOID +halbtc8192d2ant_ActionPanA2dpBc8( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bBtHsOn=FALSE, bWifiBusy=FALSE; + u1Byte wifiRssiState; + u4Byte wifiBw; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + if(!bBtHsOn) + { + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + wifiRssiState = halbtc8192d2ant_WifiRssiState(pBtCoexist, 0, 2, 25, 0); + if((pCoexSta->bBtBusy && bWifiBusy)) + { + // fw mechanism first + if(pCoexSta->bBtUplink) + { + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x15, 0x20); + } + else + { + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, TRUE, 0x10, 0x20); + } + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x20, FALSE); + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + else + { + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + } + else + { + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + } + else + { + halbtc8192d2ant_CoexAllOff(pBtCoexist); + } + } + else + { + if(pCoexSta->bBtBusy) + { + // fw mechanism + halbtc8192d2ant_Balance(pBtCoexist, NORMAL_EXEC, FALSE, 0, 0); + halbtc8192d2ant_DiminishWifi(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0, FALSE); + + // sw mechanism + halbtc8192d2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x20); + } + else + { + halbtc8192d2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0x30); + } + } +} + +VOID +halbtc8192d2ant_ActionPanA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + if(BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) + { + halbtc8192d2ant_ActionPanA2dpBc4(pBtCoexist); + } + else if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) + { + halbtc8192d2ant_ActionPanA2dpBc8(pBtCoexist); + } +} + +BOOLEAN +halbtc8192d2ant_IsBtCoexistEnter( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte macPhyMode; + BOOLEAN bRet=TRUE; + BOOLEAN bWifiUnder5G=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_MAC_PHY_MODE, &macPhyMode); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_5G, &bWifiUnder5G); + + if(BTC_SMSP != macPhyMode) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Only support single mac single phy!!\n")); + bRet = FALSE; + } + + if(bWifiUnder5G) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi is under 5G or A band\n")); + halbtc8192d2ant_CoexAllOff(pBtCoexist); + bRet = FALSE; + } + + return bRet; +} + +//============================================================ +// extern function start with EXhalbtc8192d2ant_ +//============================================================ +VOID +EXhalbtc8192d2ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ) +{ +} + +VOID +EXhalbtc8192d2ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ) +{ + u1Byte u1Tmp=0; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 2Ant Init HW Config!!\n")); + + // backup rf 0x1e value + pCoexDm->btRf0x1eBackup = + pBtCoexist->fBtcGetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff); + + if( (BTC_CHIP_CSR_BC4 == pBtCoexist->boardInfo.btChipType) || + (BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) ) + { + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4fd) & BIT0; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x4fd, u1Tmp); + + halbtc8192d2ant_CoexTable(pBtCoexist, FORCE_EXEC, 0xaaaa9aaa, 0xffbd0040, 0x40000010); + + // switch control, here we set pathA to control + // 0x878[13] = 1, 0:pathB, 1:pathA(default) + pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x878, BIT13, 0x1); + + // antsel control, here we use phy0 and enable antsel. + // 0x87c[16:15] = b'11, enable antsel, antsel output pin + // 0x87c[30] = 0, 0: phy0, 1:phy 1 + pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x87c, bMaskDWord, 0x1fff8); + + // antsel to Bt or Wifi, it depends Bt on/off. + // 0x860[9:8] = 'b10, b10:Bt On, WL2G off(default), b01:Bt off, WL2G on. + pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x860, BIT9|BIT8, 0x2); + + // sw/hw control switch, here we set sw control + // 0x870[9:8] = 'b11 sw control, 'b00 hw control + pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x870, BIT9|BIT8, 0x3); + } +} + +VOID +EXhalbtc8192d2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Coex Mechanism Init!!\n")); + + halbtc8192d2ant_InitCoexDm(pBtCoexist); +} + +VOID +EXhalbtc8192d2ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + pu1Byte cliBuf=pBtCoexist->cliBuf; + u1Byte u1Tmp[4], i, btInfoExt, psTdmaCase=0; + u4Byte u4Tmp[4]; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:", \ + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum); + CL_PRINTF(cliBuf); + + if(pBtCoexist->bManualControl) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "[Action Manual control]!!"); + CL_PRINTF(cliBuf); + } + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \ + ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion); + CL_PRINTF(cliBuf); + + // wifi status + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Wifi Status]============"); + CL_PRINTF(cliBuf); + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[BT Status]============"); + CL_PRINTF(cliBuf); + + if(pStackInfo->bProfileNotified) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP", \ + pStackInfo->bScoExist, pStackInfo->bHidExist, pStackInfo->bPanExist, pStackInfo->bA2dpExist); + CL_PRINTF(cliBuf); + + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO); + } + + // Sw mechanism + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============"); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", \ + pCoexDm->bCurAgcTableEn, pCoexDm->bCurAdcBackOff, pCoexDm->bCurDacSwingOn, pCoexDm->curDacSwingLvl); + CL_PRINTF(cliBuf); + + // Fw mechanism + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============"); + CL_PRINTF(cliBuf); + + // Hw setting + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "RF-A, 0x1e initVal", \ + pCoexDm->btRf0x1eBackup); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x40); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x40", \ + u1Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc50); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", \ + u4Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c4); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c8); + u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6cc); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x6c4/0x6c8/0x6cc(coexTable)", \ + u4Tmp[0], u4Tmp[1], u4Tmp[2]); + CL_PRINTF(cliBuf); + + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + + +VOID +EXhalbtc8192d2ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_IPS_ENTER == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS ENTER notify\n")); + halbtc8192d2ant_CoexAllOff(pBtCoexist); + } + else if(BTC_IPS_LEAVE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS LEAVE notify\n")); + //halbtc8192d2ant_InitCoexDm(pBtCoexist); + } +} + +VOID +EXhalbtc8192d2ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_LPS_ENABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS ENABLE notify\n")); + halbtc8192d2ant_CoexAllOff(pBtCoexist); + } + else if(BTC_LPS_DISABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS DISABLE notify\n")); + halbtc8192d2ant_InitCoexDm(pBtCoexist); + } +} + +VOID +EXhalbtc8192d2ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_SCAN_START == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n")); + } + else if(BTC_SCAN_FINISH == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n")); + } +} + +VOID +EXhalbtc8192d2ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_ASSOCIATE_START == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n")); + } + else if(BTC_ASSOCIATE_FINISH == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n")); + } +} + +VOID +EXhalbtc8192d2ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_MEDIA_CONNECT == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA connect notify\n")); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA disconnect notify\n")); + } +} + +VOID +EXhalbtc8192d2ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(type == BTC_PACKET_DHCP) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], DHCP Packet notify\n")); + } +} + +VOID +EXhalbtc8192d2ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ) +{ +} + +VOID +EXhalbtc8192d2ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Halt notify\n")); + + EXhalbtc8192d2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); +} + +VOID +EXhalbtc8192d2ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte algorithm; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 2Ant Periodical!!\n")); + + // NOTE: + // sw mechanism must be done after fw mechanism + // + if(!halbtc8192d2ant_IsBtCoexistEnter(pBtCoexist)) + return; + + if(BTC_CHIP_CSR_BC8 == pBtCoexist->boardInfo.btChipType) + { + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_GET_BT_RSSI, NULL); + + halbtc8192d2ant_MonitorBtState(pBtCoexist); + algorithm = halbtc8192d2ant_ActionAlgorithm(pBtCoexist); + pCoexDm->curAlgorithm = algorithm; + switch(pCoexDm->curAlgorithm) + { + case BT_8192D_2ANT_COEX_ALGO_SCO: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = SCO\n")); + halbtc8192d2ant_ActionSco(pBtCoexist); + break; + case BT_8192D_2ANT_COEX_ALGO_HID: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID\n")); + halbtc8192d2ant_ActionHid(pBtCoexist); + break; + case BT_8192D_2ANT_COEX_ALGO_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = A2DP\n")); + halbtc8192d2ant_ActionA2dp(pBtCoexist); + break; + case BT_8192D_2ANT_COEX_ALGO_PAN: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN\n")); + halbtc8192d2ant_ActionPan(pBtCoexist); + break; + case BT_8192D_2ANT_COEX_ALGO_HID_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP\n")); + halbtc8192d2ant_ActionHidA2dp(pBtCoexist); + break; + case BT_8192D_2ANT_COEX_ALGO_HID_PAN: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN+HID\n")); + halbtc8192d2ant_ActionHidPan(pBtCoexist); + break; + case BT_8192D_2ANT_COEX_ALGO_PAN_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN+A2DP\n")); + halbtc8192d2ant_ActionPanA2dp(pBtCoexist); + break; + default: + break; + } + } +} + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8192d2Ant.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8192d2Ant.h new file mode 100644 index 000000000..459c22d75 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8192d2Ant.h @@ -0,0 +1,171 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//=========================================== +// The following is for 8192D 2Ant BT Co-exist definition +//=========================================== +#define BTC_RSSI_COEX_THRESH_TOL_8192D_2ANT 6 + +typedef enum _BT_INFO_SRC_8192D_2ANT{ + BT_INFO_SRC_8192D_2ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8192D_2ANT_BT_RSP = 0x1, + BT_INFO_SRC_8192D_2ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8192D_2ANT_MAX +}BT_INFO_SRC_8192D_2ANT,*PBT_INFO_SRC_8192D_2ANT; + +typedef enum _BT_8192D_2ANT_BT_STATUS{ + BT_8192D_2ANT_BT_STATUS_IDLE = 0x0, + BT_8192D_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8192D_2ANT_BT_STATUS_NON_IDLE = 0x2, + BT_8192D_2ANT_BT_STATUS_MAX +}BT_8192D_2ANT_BT_STATUS,*PBT_8192D_2ANT_BT_STATUS; + +typedef enum _BT_8192D_2ANT_COEX_ALGO{ + BT_8192D_2ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8192D_2ANT_COEX_ALGO_SCO = 0x1, + BT_8192D_2ANT_COEX_ALGO_HID = 0x2, + BT_8192D_2ANT_COEX_ALGO_A2DP = 0x3, + BT_8192D_2ANT_COEX_ALGO_PAN = 0x4, + BT_8192D_2ANT_COEX_ALGO_HID_A2DP = 0x5, + BT_8192D_2ANT_COEX_ALGO_HID_PAN = 0x6, + BT_8192D_2ANT_COEX_ALGO_PAN_A2DP = 0x7, + BT_8192D_2ANT_COEX_ALGO_MAX +}BT_8192D_2ANT_COEX_ALGO,*PBT_8192D_2ANT_COEX_ALGO; + +typedef struct _COEX_DM_8192D_2ANT{ + // fw mechanism + BOOLEAN bPreBalanceOn; + BOOLEAN bCurBalanceOn; + + // diminishWifi + BOOLEAN bPreDacOn; + BOOLEAN bCurDacOn; + BOOLEAN bPreInterruptOn; + BOOLEAN bCurInterruptOn; + u1Byte preFwDacSwingLvl; + u1Byte curFwDacSwingLvl; + BOOLEAN bPreNavOn; + BOOLEAN bCurNavOn; + + + + + + //BOOLEAN bPreDecBtPwr; + //BOOLEAN bCurDecBtPwr; + + //u1Byte preFwDacSwingLvl; + //u1Byte curFwDacSwingLvl; + //BOOLEAN bCurIgnoreWlanAct; + //BOOLEAN bPreIgnoreWlanAct; + //u1Byte prePsTdma; + //u1Byte curPsTdma; + //u1Byte psTdmaPara[5]; + //u1Byte psTdmaDuAdjType; + //BOOLEAN bResetTdmaAdjust; + //BOOLEAN bPrePsTdmaOn; + //BOOLEAN bCurPsTdmaOn; + //BOOLEAN bPreBtAutoReport; + //BOOLEAN bCurBtAutoReport; + + // sw mechanism + BOOLEAN bPreRfRxLpfShrink; + BOOLEAN bCurRfRxLpfShrink; + u4Byte btRf0x1eBackup; + BOOLEAN bPreLowPenaltyRa; + BOOLEAN bCurLowPenaltyRa; + BOOLEAN bPreDacSwingOn; + u4Byte preDacSwingLvl; + BOOLEAN bCurDacSwingOn; + u4Byte curDacSwingLvl; + BOOLEAN bPreAdcBackOff; + BOOLEAN bCurAdcBackOff; + BOOLEAN bPreAgcTableEn; + BOOLEAN bCurAgcTableEn; + //u4Byte preVal0x6c0; + //u4Byte curVal0x6c0; + u4Byte preVal0x6c4; + u4Byte curVal0x6c4; + u4Byte preVal0x6c8; + u4Byte curVal0x6c8; + u4Byte preVal0x6cc; + u4Byte curVal0x6cc; + //BOOLEAN bLimitedDig; + + // algorithm related + u1Byte preAlgorithm; + u1Byte curAlgorithm; + //u1Byte btStatus; + //u1Byte wifiChnlInfo[3]; +} COEX_DM_8192D_2ANT, *PCOEX_DM_8192D_2ANT; + +typedef struct _COEX_STA_8192D_2ANT{ + u1Byte preWifiRssiState[4]; + BOOLEAN bBtBusy; + BOOLEAN bBtUplink; + BOOLEAN bBtDownLink; + BOOLEAN bA2dpBusy; +}COEX_STA_8192D_2ANT, *PCOEX_STA_8192D_2ANT; + +//=========================================== +// The following is interface which will notify coex module. +//=========================================== +VOID +EXhalbtc8192d2ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8192d2ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ); +VOID +EXhalbtc8192d2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8192d2ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8192d2ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8192d2ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8192d2ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8192d2ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8192d2ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8192d2ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8192d2ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8192d2ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ); +VOID +EXhalbtc8192d2ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ); diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8192e1Ant.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8192e1Ant.c new file mode 100644 index 000000000..e3ebe3a4b --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8192e1Ant.c @@ -0,0 +1,3739 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//============================================================ +// Description: +// +// This file is for RTL8192E Co-exist mechanism +// +// History +// 2012/11/15 Cosa first check in. +// +//============================================================ + +//============================================================ +// include files +//============================================================ +#include "Mp_Precomp.h" + +#if WPP_SOFTWARE_TRACE +#include "HalBtc8192e1Ant.tmh" +#endif + +#if(BT_30_SUPPORT == 1) +//============================================================ +// Global variables, these are static variables +//============================================================ +static COEX_DM_8192E_1ANT GLCoexDm8192e1Ant; +static PCOEX_DM_8192E_1ANT pCoexDm=&GLCoexDm8192e1Ant; +static COEX_STA_8192E_1ANT GLCoexSta8192e1Ant; +static PCOEX_STA_8192E_1ANT pCoexSta=&GLCoexSta8192e1Ant; + +const char *const GLBtInfoSrc8192e1Ant[]={ + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; + +u4Byte GLCoexVerDate8192e1Ant=20140527; +u4Byte GLCoexVer8192e1Ant=0x4f; + +//============================================================ +// local function proto type if needed +//============================================================ +//============================================================ +// local function start with halbtc8192e1ant_ +//============================================================ +u1Byte +halbtc8192e1ant_BtRssiState( + u1Byte levelNum, + u1Byte rssiThresh, + u1Byte rssiThresh1 + ) +{ + s4Byte btRssi=0; + u1Byte btRssiState=pCoexSta->preBtRssiState; + + btRssi = pCoexSta->btRssi; + + if(levelNum == 2) + { + if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW)) + { + if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT)) + { + btRssiState = BTC_RSSI_STATE_HIGH; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else + { + if(btRssi < rssiThresh) + { + btRssiState = BTC_RSSI_STATE_LOW; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + else if(levelNum == 3) + { + if(rssiThresh > rssiThresh1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Rssi thresh error!!\n")); + return pCoexSta->preBtRssiState; + } + + if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW)) + { + if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT)) + { + btRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_MEDIUM) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_MEDIUM)) + { + if(btRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT)) + { + btRssiState = BTC_RSSI_STATE_HIGH; + } + else if(btRssi < rssiThresh) + { + btRssiState = BTC_RSSI_STATE_LOW; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_MEDIUM; + } + } + else + { + if(btRssi < rssiThresh1) + { + btRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + + pCoexSta->preBtRssiState = btRssiState; + + return btRssiState; +} + +u1Byte +halbtc8192e1ant_WifiRssiState( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte index, + IN u1Byte levelNum, + IN u1Byte rssiThresh, + IN u1Byte rssiThresh1 + ) +{ + s4Byte wifiRssi=0; + u1Byte wifiRssiState=pCoexSta->preWifiRssiState[index]; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); + + if(levelNum == 2) + { + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else + { + if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + else if(levelNum == 3) + { + if(rssiThresh > rssiThresh1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi RSSI thresh error!!\n")); + return pCoexSta->preWifiRssiState[index]; + } + + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT)) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_MEDIUM) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_MEDIUM)) + { + if(wifiRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_MEDIUM; + } + } + else + { + if(wifiRssi < rssiThresh1) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + + pCoexSta->preWifiRssiState[index] = wifiRssiState; + + return wifiRssiState; +} + +VOID +halbtc8192e1ant_UpdateRaMask( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u4Byte disRateMask + ) +{ + pCoexDm->curRaMask = disRateMask; + + if( bForceExec || (pCoexDm->preRaMask != pCoexDm->curRaMask)) + { + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_UPDATE_RAMASK, &pCoexDm->curRaMask); + } + pCoexDm->preRaMask = pCoexDm->curRaMask; +} + +VOID +halbtc8192e1ant_AutoRateFallbackRetry( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + BOOLEAN bWifiUnderBMode=FALSE; + + pCoexDm->curArfrType = type; + + if( bForceExec || (pCoexDm->preArfrType != pCoexDm->curArfrType)) + { + switch(pCoexDm->curArfrType) + { + case 0: // normal mode + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x430, pCoexDm->backupArfrCnt1); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x434, pCoexDm->backupArfrCnt2); + break; + case 1: + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, &bWifiUnderBMode); + if(bWifiUnderBMode) + { + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x430, 0x0); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x434, 0x01010101); + } + else + { + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x430, 0x0); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x434, 0x04030201); + } + break; + default: + break; + } + } + + pCoexDm->preArfrType = pCoexDm->curArfrType; +} + +VOID +halbtc8192e1ant_RetryLimit( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + pCoexDm->curRetryLimitType = type; + + if( bForceExec || (pCoexDm->preRetryLimitType != pCoexDm->curRetryLimitType)) + { + switch(pCoexDm->curRetryLimitType) + { + case 0: // normal mode + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x42a, pCoexDm->backupRetryLimit); + break; + case 1: // retry limit=8 + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x42a, 0x0808); + break; + default: + break; + } + } + + pCoexDm->preRetryLimitType = pCoexDm->curRetryLimitType; +} + +VOID +halbtc8192e1ant_AmpduMaxTime( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + pCoexDm->curAmpduTimeType = type; + + if( bForceExec || (pCoexDm->preAmpduTimeType != pCoexDm->curAmpduTimeType)) + { + switch(pCoexDm->curAmpduTimeType) + { + case 0: // normal mode + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x456, pCoexDm->backupAmpduMaxTime); + break; + case 1: // AMPDU timw = 0x38 * 32us + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x456, 0x38); + break; + default: + break; + } + } + + pCoexDm->preAmpduTimeType = pCoexDm->curAmpduTimeType; +} + +VOID +halbtc8192e1ant_LimitedTx( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte raMaskType, + IN u1Byte arfrType, + IN u1Byte retryLimitType, + IN u1Byte ampduTimeType + ) +{ + switch(raMaskType) + { + case 0: // normal mode + halbtc8192e1ant_UpdateRaMask(pBtCoexist, bForceExec, 0x0); + break; + case 1: // disable cck 1/2 + halbtc8192e1ant_UpdateRaMask(pBtCoexist, bForceExec, 0x00000003); + break; + case 2: // disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 + halbtc8192e1ant_UpdateRaMask(pBtCoexist, bForceExec, 0x0001f1f7); + break; + default: + break; + } + + halbtc8192e1ant_AutoRateFallbackRetry(pBtCoexist, bForceExec, arfrType); + halbtc8192e1ant_RetryLimit(pBtCoexist, bForceExec, retryLimitType); + halbtc8192e1ant_AmpduMaxTime(pBtCoexist, bForceExec, ampduTimeType); +} + +VOID +halbtc8192e1ant_LimitedRx( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bRejApAggPkt, + IN BOOLEAN bBtCtrlAggBufSize, + IN u1Byte aggBufSize + ) +{ + BOOLEAN bRejectRxAgg=bRejApAggPkt; + BOOLEAN bBtCtrlRxAggSize=bBtCtrlAggBufSize; + u1Byte rxAggSize=aggBufSize; + + //============================================ + // Rx Aggregation related setting + //============================================ + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, &bRejectRxAgg); + // decide BT control aggregation buf size or not + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, &bBtCtrlRxAggSize); + // aggregation buf size, only work when BT control Rx aggregation size. + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_AGG_BUF_SIZE, &rxAggSize); + // real update aggregation setting + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); + + +} + +VOID +halbtc8192e1ant_QueryBtInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + pCoexSta->bC2hBtInfoReqSent = TRUE; + + H2C_Parameter[0] |= BIT0; // trigger + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Query Bt Info, FW write 0x61=0x%x\n", + H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x61, 1, H2C_Parameter); +} + +VOID +halbtc8192e1ant_MonitorBtCtr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte regHPTxRx, regLPTxRx, u4Tmp, u4Tmp1; + u4Byte regHPTx=0, regHPRx=0, regLPTx=0, regLPRx=0; + u1Byte u1Tmp, u1Tmp1; + s4Byte wifiRssi; + static u1Byte NumOfBtCounterChk = 0; + + //to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS + //if (! (pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x76e) & 0x8) ) + + if (pCoexSta->bUnderIps) + { + pCoexSta->highPriorityTx = 65535; + pCoexSta->highPriorityRx = 65535; + pCoexSta->lowPriorityTx = 65535; + pCoexSta->lowPriorityRx = 65535; + return; + } + + regHPTxRx = 0x770; + regLPTxRx = 0x774; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regHPTxRx); + regHPTx = u4Tmp & bMaskLWord; + regHPRx = (u4Tmp & bMaskHWord)>>16; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regLPTxRx); + regLPTx = u4Tmp & bMaskLWord; + regLPRx = (u4Tmp & bMaskHWord)>>16; + + pCoexSta->highPriorityTx = regHPTx; + pCoexSta->highPriorityRx = regHPRx; + pCoexSta->lowPriorityTx = regLPTx; + pCoexSta->lowPriorityRx = regLPRx; + + if( (pCoexSta->lowPriorityTx >= 1050) && (!pCoexSta->bC2hBtInquiryPage)) + pCoexSta->popEventCnt++; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n", + regHPRx, regHPTx, regLPRx, regLPTx)); + + // reset counter + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0xc); + + if ((regHPTx == 0) && (regHPRx ==0) && (regLPTx == 0) && (regLPRx == 0)) + { + NumOfBtCounterChk++; + if (NumOfBtCounterChk >= 3) + { + halbtc8192e1ant_QueryBtInfo(pBtCoexist); + NumOfBtCounterChk = 0; + } + } +} + + +VOID +halbtc8192e1ant_MonitorWiFiCtr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte u4Tmp; + u2Byte u2Tmp[3]; + s4Byte wifiRssi=0; + BOOLEAN bWifiBusy = FALSE, bWifiUnderBMode = FALSE; + static u1Byte nCCKLockCounter = 0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, &bWifiUnderBMode); + + if (pCoexSta->bUnderIps) + { + pCoexSta->nCRCOK_CCK = 0; + pCoexSta->nCRCOK_11g = 0; + pCoexSta->nCRCOK_11n = 0; + pCoexSta->nCRCOK_11nAgg = 0; + + pCoexSta->nCRCErr_CCK = 0; + pCoexSta->nCRCErr_11g = 0; + pCoexSta->nCRCErr_11n = 0; + pCoexSta->nCRCErr_11nAgg = 0; + } + else + { + pCoexSta->nCRCOK_CCK = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xf88); + pCoexSta->nCRCOK_11g = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf94); + pCoexSta->nCRCOK_11n = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf90); + pCoexSta->nCRCOK_11nAgg= pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xfb8); + + pCoexSta->nCRCErr_CCK = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xf84); + pCoexSta->nCRCErr_11g = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf96); + pCoexSta->nCRCErr_11n = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf92); + pCoexSta->nCRCErr_11nAgg = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xfba); + } + + + //reset counter + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xf16, 0x1, 0x1); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xf16, 0x1, 0x0); + + if ( (bWifiBusy) && (wifiRssi >= 30) && (!bWifiUnderBMode)) + { + if ( (pCoexDm->btStatus == BT_8192E_1ANT_BT_STATUS_ACL_BUSY) || + (pCoexDm->btStatus == BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY) || + (pCoexDm->btStatus == BT_8192E_1ANT_BT_STATUS_SCO_BUSY) ) + { + if (pCoexSta->nCRCOK_CCK >(pCoexSta->nCRCOK_11g + pCoexSta->nCRCOK_11n + + pCoexSta->nCRCOK_11nAgg) ) + { + if (nCCKLockCounter < 5) + nCCKLockCounter++; + } + else + { + if (nCCKLockCounter > 0) + nCCKLockCounter--; + } + + } + else + { + if (nCCKLockCounter > 0) + nCCKLockCounter--; + } + } + else + { + if (nCCKLockCounter > 0) + nCCKLockCounter--; + } + + if (!pCoexSta->bPreCCKLock) + { + + if (nCCKLockCounter >= 5) + pCoexSta->bCCKLock = TRUE; + else + pCoexSta->bCCKLock = FALSE; + } + else + { + if (nCCKLockCounter == 0) + pCoexSta->bCCKLock = FALSE; + else + pCoexSta->bCCKLock = TRUE; + } + + pCoexSta->bPreCCKLock = pCoexSta->bCCKLock; + + +} + +BOOLEAN +halbtc8192e1ant_IsWifiStatusChanged( + IN PBTC_COEXIST pBtCoexist + ) +{ + static BOOLEAN bPreWifiBusy=FALSE, bPreUnder4way=FALSE, bPreBtHsOn=FALSE; + BOOLEAN bWifiBusy=FALSE, bUnder4way=FALSE, bBtHsOn=FALSE; + BOOLEAN bWifiConnected=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &bUnder4way); + + if(bWifiConnected) + { + if(bWifiBusy != bPreWifiBusy) + { + bPreWifiBusy = bWifiBusy; + return TRUE; + } + if(bUnder4way != bPreUnder4way) + { + bPreUnder4way = bUnder4way; + return TRUE; + } + if(bBtHsOn != bPreBtHsOn) + { + bPreBtHsOn = bBtHsOn; + return TRUE; + } + } + + return FALSE; +} + +VOID +halbtc8192e1ant_UpdateBtLinkInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bBtHsOn=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + pBtLinkInfo->bBtLinkExist = pCoexSta->bBtLinkExist; + pBtLinkInfo->bScoExist = pCoexSta->bScoExist; + pBtLinkInfo->bA2dpExist = pCoexSta->bA2dpExist; + pBtLinkInfo->bPanExist = pCoexSta->bPanExist; + pBtLinkInfo->bHidExist = pCoexSta->bHidExist; + + // work around for HS mode. + if(bBtHsOn) + { + pBtLinkInfo->bPanExist = TRUE; + pBtLinkInfo->bBtLinkExist = TRUE; + } + + // check if Sco only + if( pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bScoOnly = TRUE; + else + pBtLinkInfo->bScoOnly = FALSE; + + // check if A2dp only + if( !pBtLinkInfo->bScoExist && + pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bA2dpOnly = TRUE; + else + pBtLinkInfo->bA2dpOnly = FALSE; + + // check if Pan only + if( !pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bPanOnly = TRUE; + else + pBtLinkInfo->bPanOnly = FALSE; + + // check if Hid only + if( !pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + pBtLinkInfo->bHidExist ) + pBtLinkInfo->bHidOnly = TRUE; + else + pBtLinkInfo->bHidOnly = FALSE; +} + +u1Byte +halbtc8192e1ant_ActionAlgorithm( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bBtHsOn=FALSE; + u1Byte algorithm=BT_8192E_1ANT_COEX_ALGO_UNDEFINED; + u1Byte numOfDiffProfile=0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + if(!pBtLinkInfo->bBtLinkExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], No BT link exists!!!\n")); + return algorithm; + } + + if(pBtLinkInfo->bScoExist) + numOfDiffProfile++; + if(pBtLinkInfo->bHidExist) + numOfDiffProfile++; + if(pBtLinkInfo->bPanExist) + numOfDiffProfile++; + if(pBtLinkInfo->bA2dpExist) + numOfDiffProfile++; + + if(numOfDiffProfile == 1) + { + if(pBtLinkInfo->bScoExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO only\n")); + algorithm = BT_8192E_1ANT_COEX_ALGO_SCO; + } + else + { + if(pBtLinkInfo->bHidExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID only\n")); + algorithm = BT_8192E_1ANT_COEX_ALGO_HID; + } + else if(pBtLinkInfo->bA2dpExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = A2DP only\n")); + algorithm = BT_8192E_1ANT_COEX_ALGO_A2DP; + } + else if(pBtLinkInfo->bPanExist) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = PAN(HS) only\n")); + algorithm = BT_8192E_1ANT_COEX_ALGO_PANHS; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = PAN(EDR) only\n")); + algorithm = BT_8192E_1ANT_COEX_ALGO_PANEDR; + } + } + } + } + else if(numOfDiffProfile == 2) + { + if(pBtLinkInfo->bScoExist) + { + if(pBtLinkInfo->bHidExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + HID\n")); + algorithm = BT_8192E_1ANT_COEX_ALGO_HID; + } + else if(pBtLinkInfo->bA2dpExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + A2DP ==> SCO\n")); + algorithm = BT_8192E_1ANT_COEX_ALGO_SCO; + } + else if(pBtLinkInfo->bPanExist) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + PAN(HS)\n")); + algorithm = BT_8192E_1ANT_COEX_ALGO_SCO; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + PAN(EDR)\n")); + algorithm = BT_8192E_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } + else + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bA2dpExist ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID + A2DP\n")); + algorithm = BT_8192E_1ANT_COEX_ALGO_HID_A2DP; + } + else if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID + PAN(HS)\n")); + algorithm = BT_8192E_1ANT_COEX_ALGO_HID_A2DP; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID + PAN(EDR)\n")); + algorithm = BT_8192E_1ANT_COEX_ALGO_PANEDR_HID; + } + } + else if( pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = A2DP + PAN(HS)\n")); + algorithm = BT_8192E_1ANT_COEX_ALGO_A2DP_PANHS; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = A2DP + PAN(EDR)\n")); + algorithm = BT_8192E_1ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } + } + else if(numOfDiffProfile == 3) + { + if(pBtLinkInfo->bScoExist) + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bA2dpExist ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n")); + algorithm = BT_8192E_1ANT_COEX_ALGO_HID; + } + else if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + HID + PAN(HS)\n")); + algorithm = BT_8192E_1ANT_COEX_ALGO_HID_A2DP; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n")); + algorithm = BT_8192E_1ANT_COEX_ALGO_PANEDR_HID; + } + } + else if( pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n")); + algorithm = BT_8192E_1ANT_COEX_ALGO_SCO; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n")); + algorithm = BT_8192E_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } + else + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n")); + algorithm = BT_8192E_1ANT_COEX_ALGO_HID_A2DP; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n")); + algorithm = BT_8192E_1ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } + else if(numOfDiffProfile >= 3) + { + if(pBtLinkInfo->bScoExist) + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n")); + + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n")); + algorithm = BT_8192E_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } + } + + return algorithm; +} + +VOID +halbtc8192e1ant_SetBtAutoReport( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bEnableAutoReport + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + H2C_Parameter[0] = 0; + + if(bEnableAutoReport) + { + H2C_Parameter[0] |= BIT0; + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], BT FW auto report : %s, FW write 0x68=0x%x\n", + (bEnableAutoReport? "Enabled!!":"Disabled!!"), H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x68, 1, H2C_Parameter); +} + +VOID +halbtc8192e1ant_BtAutoReport( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bEnableAutoReport + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s BT Auto report = %s\n", + (bForceExec? "force to":""), ((bEnableAutoReport)? "Enabled":"Disabled"))); + pCoexDm->bCurBtAutoReport = bEnableAutoReport; + + if(!bForceExec) + { + if(pCoexDm->bPreBtAutoReport == pCoexDm->bCurBtAutoReport) + return; + } + halbtc8192e1ant_SetBtAutoReport(pBtCoexist, pCoexDm->bCurBtAutoReport); + + pCoexDm->bPreBtAutoReport = pCoexDm->bCurBtAutoReport; +} + +VOID +halbtc8192e1ant_SetSwPenaltyTxRateAdaptive( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bLowPenaltyRa + ) +{ + u1Byte H2C_Parameter[6] ={0}; + + H2C_Parameter[0] = 0x6; // opCode, 0x6= Retry_Penalty + + if(bLowPenaltyRa) + { + H2C_Parameter[1] |= BIT0; + H2C_Parameter[2] = 0x00; //normal rate except MCS7/6/5, OFDM54/48/36 + H2C_Parameter[3] = 0xf7; //MCS7 or OFDM54 + H2C_Parameter[4] = 0xf8; //MCS6 or OFDM48 + H2C_Parameter[5] = 0xf9; //MCS5 or OFDM36 + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set WiFi Low-Penalty Retry: %s", + (bLowPenaltyRa? "ON!!":"OFF!!") )); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x69, 6, H2C_Parameter); +} + +VOID +halbtc8192e1ant_LowPenaltyRa( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bLowPenaltyRa + ) +{ + pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa; + + if(!bForceExec) + { + if(pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa) + return; + } + halbtc8192e1ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa); + + pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa; +} + +VOID +halbtc8192e1ant_SetCoexTable( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte val0x6c0, + IN u4Byte val0x6c4, + IN u4Byte val0x6c8, + IN u1Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c0=0x%x\n", val0x6c0)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c0, val0x6c0); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c4=0x%x\n", val0x6c4)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c4, val0x6c4); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, val0x6c8); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc)); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cc, val0x6cc); +} + +VOID +halbtc8192e1ant_CoexTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u4Byte val0x6c0, + IN u4Byte val0x6c4, + IN u4Byte val0x6c8, + IN u1Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s write Coex Table 0x6c0=0x%x, 0x6c4=0x%x, 0x6cc=0x%x\n", + (bForceExec? "force to":""), val0x6c0, val0x6c4, val0x6cc)); + pCoexDm->curVal0x6c0 = val0x6c0; + pCoexDm->curVal0x6c4 = val0x6c4; + pCoexDm->curVal0x6c8 = val0x6c8; + pCoexDm->curVal0x6cc = val0x6cc; + + if(!bForceExec) + { + if( (pCoexDm->preVal0x6c0 == pCoexDm->curVal0x6c0) && + (pCoexDm->preVal0x6c4 == pCoexDm->curVal0x6c4) && + (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) && + (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) ) + return; + } + halbtc8192e1ant_SetCoexTable(pBtCoexist, val0x6c0, val0x6c4, val0x6c8, val0x6cc); + + pCoexDm->preVal0x6c0 = pCoexDm->curVal0x6c0; + pCoexDm->preVal0x6c4 = pCoexDm->curVal0x6c4; + pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8; + pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc; +} + +VOID +halbtc8192e1ant_CoexTableWithType( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ********** CoexTable(%d) **********\n", type)); + + pCoexSta->nCoexTableType = type; + + switch(type) + { + case 0: + halbtc8192e1ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x55555555, 0xffffff, 0x3); + break; + case 1: + halbtc8192e1ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 2: + halbtc8192e1ant_CoexTable(pBtCoexist, bForceExec, 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 3: + halbtc8192e1ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 4: + halbtc8192e1ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0xaaaa5a5a, 0xffffff, 0x3); + break; + case 5: + halbtc8192e1ant_CoexTable(pBtCoexist, bForceExec, 0x5a5a5a5a, 0xaa5a5a5a, 0xffffff, 0x3); + break; + case 6: + halbtc8192e1ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0xaaaaaaaa, 0xffffff, 0x3); + break; + case 7: + halbtc8192e1ant_CoexTable(pBtCoexist, bForceExec, 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3); + break; + default: + break; + } +} + +VOID +halbtc8192e1ant_SetFwIgnoreWlanAct( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bEnable + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + if(bEnable) + { + H2C_Parameter[0] |= BIT0; // function enable + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set FW for BT Ignore Wlan_Act, FW write 0x63=0x%x\n", + H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x63, 1, H2C_Parameter); +} + +VOID +halbtc8192e1ant_IgnoreWlanAct( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bEnable + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Ignore WlanAct %s\n", + (bForceExec? "force to":""), (bEnable? "ON":"OFF"))); + pCoexDm->bCurIgnoreWlanAct = bEnable; + + if(!bForceExec) + { + if(pCoexDm->bPreIgnoreWlanAct == pCoexDm->bCurIgnoreWlanAct) + return; + } + halbtc8192e1ant_SetFwIgnoreWlanAct(pBtCoexist, bEnable); + + pCoexDm->bPreIgnoreWlanAct = pCoexDm->bCurIgnoreWlanAct; +} + +VOID +halbtc8192e1ant_SetLpsRpwm( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + u1Byte lps=lpsVal; + u1Byte rpwm=rpwmVal; + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_LPS_VAL, &lps); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RPWM_VAL, &rpwm); +} + +VOID +halbtc8192e1ant_LpsRpwm( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + BOOLEAN bForceExecPwrCmd=FALSE; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s set lps/rpwm=0x%x/0x%x \n", + (bForceExec? "force to":""), lpsVal, rpwmVal)); + pCoexDm->curLps = lpsVal; + pCoexDm->curRpwm = rpwmVal; + + if(!bForceExec) + { + if( (pCoexDm->preLps == pCoexDm->curLps) && + (pCoexDm->preRpwm == pCoexDm->curRpwm) ) + { + return; + } + } + halbtc8192e1ant_SetLpsRpwm(pBtCoexist, lpsVal, rpwmVal); + + pCoexDm->preLps = pCoexDm->curLps; + pCoexDm->preRpwm = pCoexDm->curRpwm; +} + +VOID +halbtc8192e1ant_SwMechanism( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bLowPenaltyRA + ) +{ + halbtc8192e1ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, bLowPenaltyRA); +} + +VOID +halbtc8192e1ant_SetAntPath( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte antPosType, + IN BOOLEAN bInitHwCfg, + IN BOOLEAN bWifiOff + ) +{ + u4Byte u4Tmp=0; + + if(bInitHwCfg) + { + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x944, 0x24); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x930, 0x700700); + if(pBtCoexist->chipInterface == BTC_INTF_USB) + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x64, 0x30430004); + else + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x64, 0x30030004); + + // 0x4c[27][24]='00', Set Antenna to BB + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x4c); + u4Tmp &= ~BIT24; + u4Tmp &= ~BIT27; + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x4c, u4Tmp); + } + else if(bWifiOff) + { + if(pBtCoexist->chipInterface == BTC_INTF_USB) + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x64, 0x30430004); + else + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x64, 0x30030004); + + // 0x4c[27][24]='11', Set Antenna to BT, 0x64[8:7]=0, 0x64[2]=1 + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x4c); + u4Tmp |= BIT24; + u4Tmp |= BIT27; + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x4c, u4Tmp); + } + + // ext switch setting + switch(antPosType) + { + case BTC_ANT_PATH_WIFI: + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x92c, 0x4); + break; + case BTC_ANT_PATH_BT: + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x92c, 0x20); + break; + default: + case BTC_ANT_PATH_PTA: + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x92c, 0x4); + break; + } +} + +VOID +halbtc8192e1ant_SetFwPstdma( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte byte1, + IN u1Byte byte2, + IN u1Byte byte3, + IN u1Byte byte4, + IN u1Byte byte5 + ) +{ + u1Byte H2C_Parameter[5] ={0}; + u1Byte realByte1=byte1, realByte5=byte5; + BOOLEAN bApEnable=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + + if(bApEnable) + { + if(byte1&BIT4 && !(byte1&BIT5)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], FW for 1Ant AP mode\n")); + realByte1 &= ~BIT4; + realByte1 |= BIT5; + + realByte5 |= BIT5; + realByte5 &= ~BIT6; + } + } + + H2C_Parameter[0] = realByte1; + H2C_Parameter[1] = byte2; + H2C_Parameter[2] = byte3; + H2C_Parameter[3] = byte4; + H2C_Parameter[4] = realByte5; + + pCoexDm->psTdmaPara[0] = realByte1; + pCoexDm->psTdmaPara[1] = byte2; + pCoexDm->psTdmaPara[2] = byte3; + pCoexDm->psTdmaPara[3] = byte4; + pCoexDm->psTdmaPara[4] = realByte5; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], PS-TDMA H2C cmd =0x%x%08x\n", + H2C_Parameter[0], + H2C_Parameter[1]<<24|H2C_Parameter[2]<<16|H2C_Parameter[3]<<8|H2C_Parameter[4])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x60, 5, H2C_Parameter); +} + + +VOID +halbtc8192e1ant_PsTdma( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bTurnOn, + IN u1Byte type + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bTurnOnByCnt=FALSE, bWifiBusy=FALSE, bWiFiNoisy=FALSE; + u1Byte psTdmaTypeByCnt=0, rssiAdjustVal=0; + u1Byte psTdmaByte4Val = 0x50, psTdmaByte0Val = 0x51, psTdmaByte3Val = 0x10; + s1Byte nWiFiDurationAdjust = 0x0; + + pCoexDm->bCurPsTdmaOn = bTurnOn; + pCoexDm->curPsTdma = type; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + + if (pCoexDm->bCurPsTdmaOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ********** TDMA(on, %d) **********\n", + pCoexDm->curPsTdma)); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ********** TDMA(off, %d) **********\n", + pCoexDm->curPsTdma)); + } + + if(!bForceExec) + { + if( (pCoexDm->bPrePsTdmaOn == pCoexDm->bCurPsTdmaOn) && + (pCoexDm->prePsTdma == pCoexDm->curPsTdma) ) + return; + } + + if (pCoexSta->nScanAPNum <= 5) + nWiFiDurationAdjust = 5; + else if (pCoexSta->nScanAPNum >= 40) + nWiFiDurationAdjust = -15; + else if (pCoexSta->nScanAPNum >= 20) + nWiFiDurationAdjust = -10; + + if (!pCoexSta->bForceLpsOn) //only for A2DP-only case 1/2/9/11 while wifi noisy threshold > 30 + { + psTdmaByte0Val = 0x61; //no null-pkt + psTdmaByte3Val = 0x11; // no tx-pause at BT-slot + psTdmaByte4Val = 0x10; // 0x778 = d/1 toggle + } + + if ( (type == 3) || (type == 13) || (type == 14) ) + psTdmaByte4Val = psTdmaByte4Val & 0xbf; //no dynamic slot for multi-profile + + if (pBtLinkInfo->bSlaveRole == TRUE) + psTdmaByte4Val = psTdmaByte4Val | 0x1; //0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) + + if(bTurnOn) + { + switch(type) + { + default: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x51, 0x1a, 0x1a, 0x0, psTdmaByte4Val); + break; + case 1: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x3a+nWiFiDurationAdjust, 0x03, psTdmaByte3Val, psTdmaByte4Val); + break; + case 2: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x2d+nWiFiDurationAdjust, 0x03, psTdmaByte3Val, psTdmaByte4Val); + break; + case 3: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x51, 0x1d, 0x1d, 0x0, psTdmaByte4Val); + break; + case 4: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x93, 0x15, 0x3, 0x14, 0x0); + break; + case 5: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x61, 0x15, 0x3, 0x11, 0x11); + break; + case 6: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x61, 0x20, 0x3, 0x11, 0x11); + break; + case 7: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x13, 0xc, 0x5, 0x0, 0x0); + break; + case 8: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x93, 0x25, 0x3, 0x10, 0x0); + break; + case 9: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x21, 0x3, psTdmaByte3Val, psTdmaByte4Val); + break; + case 10: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x13, 0xa, 0xa, 0x0, 0x40); + break; + case 11: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x21, 0x03, psTdmaByte3Val, psTdmaByte4Val); + break; + case 12: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x51, 0x0a, 0x0a, 0x0, 0x50); + break; + case 13: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x51, 0x12, 0x12, 0x0, psTdmaByte4Val); + break; + case 14: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x51, 0x21, 0x3, 0x10, psTdmaByte4Val); + break; + case 15: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x13, 0xa, 0x3, 0x8, 0x0); + break; + case 16: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x93, 0x15, 0x3, 0x10, 0x0); + break; + case 18: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x93, 0x25, 0x3, 0x10, 0x0); + break; + case 20: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x61, 0x3f, 0x03, 0x11, 0x10); + break; + case 21: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x61, 0x25, 0x03, 0x11, 0x11); + break; + case 22: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x61, 0x25, 0x03, 0x11, 0x10); + break; + case 23: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x3, 0x31, 0x18); + break; + case 24: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0xe3, 0x15, 0x3, 0x31, 0x18); + break; + case 25: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0x3, 0x31, 0x18); + break; + case 26: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0x3, 0x31, 0x18); + break; + case 27: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x3, 0x31, 0x98); + break; + case 28: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x69, 0x25, 0x3, 0x31, 0x0); + break; + case 29: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0xab, 0x1a, 0x1a, 0x1, 0x10); + break; + case 30: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x51, 0x30, 0x3, 0x10, 0x10); + break; + case 31: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0xd3, 0x1a, 0x1a, 0, 0x58); + break; + case 32: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x61, 0x35, 0x3, 0x11, 0x11); + break; + case 33: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0xa3, 0x25, 0x3, 0x30, 0x90); + break; + case 34: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x53, 0x1a, 0x1a, 0x0, 0x10); + break; + case 35: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x63, 0x1a, 0x1a, 0x0, 0x10); + break; + case 36: + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0xd3, 0x12, 0x3, 0x14, 0x50); + break; + case 40: // SoftAP only with no sta associated,BT disable ,TDMA mode for power saving + /* here softap mode screen off will cost 70-80mA for phone */ + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x23, 0x18, 0x00, 0x10, 0x24); + break; + } + } + else + { + + // disable PS tdma + switch(type) + { + case 8: //PTA Control + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x8, 0x0, 0x0, 0x0, 0x0); + halbtc8192e1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, FALSE, FALSE); + break; + case 0: + default: //Software control, Antenna at BT side + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x0, 0x0); + halbtc8192e1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FALSE, FALSE); + break; + case 9: //Software control, Antenna at WiFi side + halbtc8192e1ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x0, 0x0); + halbtc8192e1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_WIFI, FALSE, FALSE); + break; + } + } + rssiAdjustVal =0; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, &rssiAdjustVal); + + + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n", + pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x948), pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x765), pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x67))); + + // update pre state + pCoexDm->bPrePsTdmaOn = pCoexDm->bCurPsTdmaOn; + pCoexDm->prePsTdma = pCoexDm->curPsTdma; +} + +VOID +halbtc8192e1ant_CoexAllOff( + IN PBTC_COEXIST pBtCoexist + ) +{ + // sw all off + halbtc8192e1ant_SwMechanism(pBtCoexist, FALSE); + + // hw all off + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); +} + +BOOLEAN +halbtc8192e1ant_IsCommonAction( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bCommon=FALSE, bWifiConnected=FALSE, bWifiBusy=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + + if(!bWifiConnected && + BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n")); + + //halbtc8192e1ant_SwMechanism(pBtCoexist, FALSE); + + bCommon = TRUE; + } + else if(bWifiConnected && + (BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi connected + BT non connected-idle!!\n")); + + //halbtc8192e1ant_SwMechanism(pBtCoexist, FALSE); + + bCommon = TRUE; + } + else if(!bWifiConnected && + (BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non connected-idle + BT connected-idle!!\n")); + + //halbtc8192e1ant_SwMechanism(pBtCoexist, FALSE); + + bCommon = TRUE; + } + else if(bWifiConnected && + (BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi connected + BT connected-idle!!\n")); + + //halbtc8192e1ant_SwMechanism(pBtCoexist, FALSE); + + bCommon = TRUE; + } + else if(!bWifiConnected && + (BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE != pCoexDm->btStatus) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non connected-idle + BT Busy!!\n")); + + //halbtc8192e1ant_SwMechanism(pBtCoexist, FALSE); + + bCommon = TRUE; + } + else + { + if (bWifiBusy) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi Connected-Busy + BT Busy!!\n")); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi Connected-Idle + BT Busy!!\n")); + } + + bCommon = FALSE; + } + + return bCommon; +} + + +VOID +halbtc8192e1ant_TdmaDurationAdjustForAcl( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte wifiStatus + ) +{ + static s4Byte up,dn,m,n,WaitCount; + s4Byte result; //0: no change, +1: increase WiFi duration, -1: decrease WiFi duration + u1Byte retryCount=0, btInfoExt; + static BOOLEAN bPreWifiBusy=FALSE; + BOOLEAN bWifiBusy = FALSE; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TdmaDurationAdjustForAcl()\n")); + + if(BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY == wifiStatus) + bWifiBusy = TRUE; + else + bWifiBusy = FALSE; + + if( (BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN == wifiStatus) || + (BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN == wifiStatus) || + (BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT == wifiStatus) ) + { + if( pCoexDm->curPsTdma != 1 && + pCoexDm->curPsTdma != 2 && + pCoexDm->curPsTdma != 3 && + pCoexDm->curPsTdma != 9 ) + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + + up = 0; + dn = 0; + m = 1; + n= 3; + result = 0; + WaitCount = 0; + } + return; + } + + if(!pCoexDm->bAutoTdmaAdjust) + { + pCoexDm->bAutoTdmaAdjust = TRUE; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], first run TdmaDurationAdjust()!!\n")); + + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + //============ + up = 0; + dn = 0; + m = 1; + n= 3; + result = 0; + WaitCount = 0; + } + else + { + //accquire the BT TRx retry count from BT_Info byte2 + retryCount = pCoexSta->btRetryCnt; + btInfoExt = pCoexSta->btInfoExt; + + if ( (pCoexSta->lowPriorityTx) > 1050 || (pCoexSta->lowPriorityRx) > 1250 ) + retryCount++; + + result = 0; + WaitCount++; + + if(retryCount == 0) // no retry in the last 2-second duration + { + up++; + dn--; + + if (dn <= 0) + dn = 0; + + if(up >= n) // if s n 2 retry count0, hռeWiFi duration + { + WaitCount = 0; + n = 3; + up = 0; + dn = 0; + result = 1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Increase wifi duration!!\n")); + } + } + else if (retryCount <= 3) // <=3 retry in the last 2-second duration + { + up--; + dn++; + + if (up <= 0) + up = 0; + + if (dn == 2) // if s 2 2 retry count< 3, hկWiFi duration + { + if (WaitCount <= 2) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter<3!!\n")); + } + } + else //retry count > 3, un1 retry count > 3, hկWiFi duration + { + if (WaitCount == 1) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter>3!!\n")); + } + + if(result == -1) + { + if( (BT_INFO_8192E_1ANT_A2DP_BASIC_RATE(btInfoExt)) && + ((pCoexDm->curPsTdma == 1) ||(pCoexDm->curPsTdma == 2)) ) + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(pCoexDm->curPsTdma == 1) + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + } + else if(result == 1) + { + if( (BT_INFO_8192E_1ANT_A2DP_BASIC_RATE(btInfoExt)) && + ((pCoexDm->curPsTdma == 1) ||(pCoexDm->curPsTdma == 2)) ) + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + } + else //no change + { + /* Bryant Modify + if(bWifiBusy != bPreWifiBusy) //if busy / idle change + { + bPreWifiBusy = bWifiBusy; + halbtc8192e1ant_PsTdma(pBtCoexist, FORCE_EXEC, TRUE, pCoexDm->curPsTdma); + } + */ + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], ********** TDMA(on, %d) **********\n", + pCoexDm->curPsTdma)); + } + + if( pCoexDm->curPsTdma != 1 && + pCoexDm->curPsTdma != 2 && + pCoexDm->curPsTdma != 9 && + pCoexDm->curPsTdma != 11 ) + { + // recover to previous adjust type + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, pCoexDm->psTdmaDuAdjType); + } + } +} + +VOID +halbtc8192e1ant_PsTdmaCheckForPowerSaveState( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bNewPsState + ) +{ + u1Byte lpsMode=0x0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_LPS_MODE, &lpsMode); + + if(lpsMode) // already under LPS state + { + if(bNewPsState) + { + // keep state under LPS, do nothing. + } + else + { + // will leave LPS state, turn off psTdma first + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + } + } + else // NO PS state + { + if(bNewPsState) + { + // will enter LPS state, turn off psTdma first + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + } + else + { + // keep state under NO PS state, do nothing. + } + } +} + +VOID +halbtc8192e1ant_PowerSaveState( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte psType, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + BOOLEAN bLowPwrDisable=FALSE; + + switch(psType) + { + case BTC_PS_WIFI_NATIVE: + // recover to original 32k low power setting + bLowPwrDisable = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_NORMAL_LPS, NULL); + pCoexSta->bForceLpsOn = FALSE; + break; + case BTC_PS_LPS_ON: + halbtc8192e1ant_PsTdmaCheckForPowerSaveState(pBtCoexist, TRUE); + halbtc8192e1ant_LpsRpwm(pBtCoexist, NORMAL_EXEC, lpsVal, rpwmVal); + // when coex force to enter LPS, do not enter 32k low power. + bLowPwrDisable = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + // power save must executed before psTdma. + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_ENTER_LPS, NULL); + pCoexSta->bForceLpsOn = TRUE; + break; + case BTC_PS_LPS_OFF: + halbtc8192e1ant_PsTdmaCheckForPowerSaveState(pBtCoexist, FALSE); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_LEAVE_LPS, NULL); + pCoexSta->bForceLpsOn = FALSE; + break; + default: + break; + } +} + +VOID +halbtc8192e1ant_ActionWifiOnly( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 9); +} + +VOID +halbtc8192e1ant_MonitorBtEnableDisable( + IN PBTC_COEXIST pBtCoexist + ) +{ + static BOOLEAN bPreBtDisabled=FALSE; + static u4Byte btDisableCnt=0; + BOOLEAN bBtActive=TRUE, bBtDisabled=FALSE; + + // This function check if bt is disabled + + if( pCoexSta->highPriorityTx == 0 && + pCoexSta->highPriorityRx == 0 && + pCoexSta->lowPriorityTx == 0 && + pCoexSta->lowPriorityRx == 0) + { + bBtActive = FALSE; + } + if( pCoexSta->highPriorityTx == 0xffff && + pCoexSta->highPriorityRx == 0xffff && + pCoexSta->lowPriorityTx == 0xffff && + pCoexSta->lowPriorityRx == 0xffff) + { + bBtActive = FALSE; + } + if(bBtActive) + { + btDisableCnt = 0; + bBtDisabled = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is enabled !!\n")); + } + else + { + btDisableCnt++; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], bt all counters=0, %d times!!\n", + btDisableCnt)); + if(btDisableCnt >= 2) + { + bBtDisabled = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is disabled !!\n")); + halbtc8192e1ant_ActionWifiOnly(pBtCoexist); + } + } + if(bPreBtDisabled != bBtDisabled) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is from %s to %s!!\n", + (bPreBtDisabled ? "disabled":"enabled"), + (bBtDisabled ? "disabled":"enabled"))); + bPreBtDisabled = bBtDisabled; + if(!bBtDisabled) + { + } + else + { + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_LEAVE_LPS, NULL); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_NORMAL_LPS, NULL); + } + } +} + +//============================================= +// +// Software Coex Mechanism start +// +//============================================= + +// SCO only or SCO+PAN(HS) + +/* +VOID +halbtc8192e1ant_ActionSco( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8192e1ant_SwMechanism(pBtCoexist, TRUE); +} + + +VOID +halbtc8192e1ant_ActionHid( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8192e1ant_SwMechanism(pBtCoexist, TRUE); +} + +//A2DP only / PAN(EDR) only/ A2DP+PAN(HS) +VOID +halbtc8192e1ant_ActionA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8192e1ant_SwMechanism(pBtCoexist, FALSE); +} + +VOID +halbtc8192e1ant_ActionA2dpPanHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8192e1ant_SwMechanism(pBtCoexist, FALSE); +} + +VOID +halbtc8192e1ant_ActionPanEdr( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8192e1ant_SwMechanism(pBtCoexist, FALSE); +} + +//PAN(HS) only +VOID +halbtc8192e1ant_ActionPanHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8192e1ant_SwMechanism(pBtCoexist, FALSE); +} + +//PAN(EDR)+A2DP +VOID +halbtc8192e1ant_ActionPanEdrA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8192e1ant_SwMechanism(pBtCoexist, FALSE); +} + +VOID +halbtc8192e1ant_ActionPanEdrHid( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8192e1ant_SwMechanism(pBtCoexist, TRUE); +} + +// HID+A2DP+PAN(EDR) +VOID +halbtc8192e1ant_ActionHidA2dpPanEdr( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8192e1ant_SwMechanism(pBtCoexist, TRUE); +} + +VOID +halbtc8192e1ant_ActionHidA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8192e1ant_SwMechanism(pBtCoexist, TRUE); +} + +*/ + +//============================================= +// +// Non-Software Coex Mechanism start +// +//============================================= +VOID +halbtc8192e1ant_ActionWifiMultiPort( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); +} + +VOID +halbtc8192e1ant_ActionHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); +} + +VOID +halbtc8192e1ant_ActionBtInquiry( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bWifiConnected=FALSE, bApEnable=FALSE, bWifiBusy=FALSE, bBtBusy=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bBtBusy); + + if((!bWifiConnected) && (!pCoexSta->bWiFiIsHighPriTask)) + { + halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + else if((pBtLinkInfo->bScoExist) || (pBtLinkInfo->bHidExist) || (pBtLinkInfo->bA2dpExist)) + { + // SCO/HID/A2DP busy + halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else if ((pBtLinkInfo->bPanExist) || (bWifiBusy)) + { + halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 20); + + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else + { + halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } +} + +VOID +halbtc8192e1ant_ActionBtScoHidOnlyBusy( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte wifiStatus + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bWifiConnected=FALSE; + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + + // tdma and coex table + + if(pBtLinkInfo->bScoExist) + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 5); + } + else //HID + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 5); + } +} + +VOID +halbtc8192e1ant_ActionWifiConnectedBtAclBusy( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte wifiStatus + ) +{ + u1Byte btRssiState; + + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + btRssiState = halbtc8192e1ant_BtRssiState(2, 28, 0); + + if ( (pCoexSta->lowPriorityRx >= 1000) && (pCoexSta->lowPriorityRx != 65535) ) + { + pBtLinkInfo->bSlaveRole = TRUE; + } + else + { + pBtLinkInfo->bSlaveRole = FALSE; + } + + if(pBtLinkInfo->bHidOnly) //HID + { + halbtc8192e1ant_ActionBtScoHidOnlyBusy(pBtCoexist, wifiStatus); + pCoexDm->bAutoTdmaAdjust = FALSE; + return; + } + else if(pBtLinkInfo->bA2dpOnly) //A2DP + { + if(BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifiStatus) + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + pCoexDm->bAutoTdmaAdjust = FALSE; + } + else + { + halbtc8192e1ant_TdmaDurationAdjustForAcl(pBtCoexist, wifiStatus); +#if 0 + if (pCoexSta->bCCKLock) + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 3); + else +#endif + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + pCoexDm->bAutoTdmaAdjust = TRUE; + } + } + else if ( ((pBtLinkInfo->bA2dpExist) && (pBtLinkInfo->bPanExist)) || + (pBtLinkInfo->bHidExist&&pBtLinkInfo->bA2dpExist&&pBtLinkInfo->bPanExist) ) //A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + pCoexDm->bAutoTdmaAdjust = FALSE; + } + else if(pBtLinkInfo->bHidExist&&pBtLinkInfo->bA2dpExist) //HID+A2DP + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->bAutoTdmaAdjust = FALSE; + + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 3); + } + else if( (pBtLinkInfo->bPanOnly) || (pBtLinkInfo->bHidExist&&pBtLinkInfo->bPanExist) ) //PAN(OPP,FTP), HID+PAN(OPP,FTP) + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + pCoexDm->bAutoTdmaAdjust = FALSE; + } + else + { + //BT no-profile busy (0x9) + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + pCoexDm->bAutoTdmaAdjust = FALSE; + } +} + +VOID +halbtc8192e1ant_ActionWifiNotConnected( + IN PBTC_COEXIST pBtCoexist + ) +{ + // power save state + halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + halbtc8192e1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8); + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); +} + +VOID +halbtc8192e1ant_ActionWifiNotConnectedScan( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + + halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + if(BT_8192E_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) + { + if (pBtLinkInfo->bA2dpExist) + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else if (pBtLinkInfo->bA2dpExist && pBtLinkInfo->bPanExist) + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 22); + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 20); + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + } + else if( (BT_8192E_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + halbtc8192e1ant_ActionBtScoHidOnlyBusy(pBtCoexist, + BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN); + } + else + { + //Bryant Add + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + } +} + +VOID +halbtc8192e1ant_ActionWifiNotConnectedAssoAuth( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + + halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + if( (pBtLinkInfo->bScoExist) || (pBtLinkInfo->bHidExist) || (pBtLinkInfo->bA2dpExist) ) + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else if (pBtLinkInfo->bPanExist) + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 20); + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + } +} + +VOID +halbtc8192e1ant_ActionWifiConnectedScan( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + + halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + if(BT_8192E_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) + { + if (pBtLinkInfo->bA2dpExist) + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else if (pBtLinkInfo->bA2dpExist && pBtLinkInfo->bPanExist) + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 22); + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 20); + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + } + else if( (BT_8192E_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + halbtc8192e1ant_ActionBtScoHidOnlyBusy(pBtCoexist, + BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN); + } + else + { + //Bryant Add + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + } +} + +VOID +halbtc8192e1ant_ActionWifiConnectedSpecialPacket( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + + halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + if((pBtLinkInfo->bScoExist) || (pBtLinkInfo->bHidExist) || (pBtLinkInfo->bA2dpExist)) + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else if(pBtLinkInfo->bPanExist) + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 20); + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + } +} + +VOID +halbtc8192e1ant_ActionWifiConnected( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bWifiBusy=FALSE; + BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE; + BOOLEAN bUnder4way=FALSE, bApEnable=FALSE; + u4Byte wifiBw; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CoexForWifiConnect()===>\n")); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &bUnder4way); + if(bUnder4way) + { + halbtc8192e1ant_ActionWifiConnectedSpecialPacket(pBtCoexist); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n")); + return; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + if(bScan || bLink || bRoam) + { + if(bScan) + halbtc8192e1ant_ActionWifiConnectedScan(pBtCoexist); + else + halbtc8192e1ant_ActionWifiConnectedSpecialPacket(pBtCoexist); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n")); + return; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + + // power save state + if(!bApEnable && BT_8192E_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus && !pBtCoexist->btLinkInfo.bHidOnly) + { + if(pBtCoexist->btLinkInfo.bA2dpOnly) //A2DP + { + if(!bWifiBusy) + halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else //busy + { + if (pCoexSta->nScanAPNum >= BT_8192E_1ANT_WIFI_NOISY_THRESH) //no force LPS, no PS-TDMA, use pure TDMA + { + halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } + else + { + halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + } + } + } + else if ((pCoexSta->bPanExist == FALSE) && (pCoexSta->bA2dpExist == FALSE) && (pCoexSta->bHidExist == FALSE)) + halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else + halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + } + else + halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + if(!bWifiBusy) + { + if(BT_8192E_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) + { + halbtc8192e1ant_ActionWifiConnectedBtAclBusy(pBtCoexist, + BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE); + } + else if( (BT_8192E_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + halbtc8192e1ant_ActionBtScoHidOnlyBusy(pBtCoexist, + BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE); + } + else + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + + if ( (pCoexSta->highPriorityTx) + (pCoexSta->highPriorityRx) <= 60 ) + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + } + else + { + if(BT_8192E_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) + { + halbtc8192e1ant_ActionWifiConnectedBtAclBusy(pBtCoexist, + BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY); + } + else if( (BT_8192E_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + halbtc8192e1ant_ActionBtScoHidOnlyBusy(pBtCoexist, + BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY); + } + else + { + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + + if ( (pCoexSta->highPriorityTx) + (pCoexSta->highPriorityRx) <= 60 ) + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + } +} + +VOID +halbtc8192e1ant_RunSwCoexistMechanism( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte algorithm=0; + + algorithm = halbtc8192e1ant_ActionAlgorithm(pBtCoexist); + pCoexDm->curAlgorithm = algorithm; + + if(halbtc8192e1ant_IsCommonAction(pBtCoexist)) + { + + } + else + { + switch(pCoexDm->curAlgorithm) + { + case BT_8192E_1ANT_COEX_ALGO_SCO: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = SCO.\n")); + //halbtc8192e1ant_ActionSco(pBtCoexist); + break; + case BT_8192E_1ANT_COEX_ALGO_HID: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = HID.\n")); + //halbtc8192e1ant_ActionHid(pBtCoexist); + break; + case BT_8192E_1ANT_COEX_ALGO_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = A2DP.\n")); + //halbtc8192e1ant_ActionA2dp(pBtCoexist); + break; + case BT_8192E_1ANT_COEX_ALGO_A2DP_PANHS: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = A2DP+PAN(HS).\n")); + //halbtc8192e1ant_ActionA2dpPanHs(pBtCoexist); + break; + case BT_8192E_1ANT_COEX_ALGO_PANEDR: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = PAN(EDR).\n")); + //halbtc8192e1ant_ActionPanEdr(pBtCoexist); + break; + case BT_8192E_1ANT_COEX_ALGO_PANHS: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = HS mode.\n")); + //halbtc8192e1ant_ActionPanHs(pBtCoexist); + break; + case BT_8192E_1ANT_COEX_ALGO_PANEDR_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = PAN+A2DP.\n")); + //halbtc8192e1ant_ActionPanEdrA2dp(pBtCoexist); + break; + case BT_8192E_1ANT_COEX_ALGO_PANEDR_HID: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = PAN(EDR)+HID.\n")); + //halbtc8192e1ant_ActionPanEdrHid(pBtCoexist); + break; + case BT_8192E_1ANT_COEX_ALGO_HID_A2DP_PANEDR: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = HID+A2DP+PAN.\n")); + //halbtc8192e1ant_ActionHidA2dpPanEdr(pBtCoexist); + break; + case BT_8192E_1ANT_COEX_ALGO_HID_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = HID+A2DP.\n")); + //halbtc8192e1ant_ActionHidA2dp(pBtCoexist); + break; + default: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = coexist All Off!!\n")); + //halbtc8192e1ant_CoexAllOff(pBtCoexist); + break; + } + pCoexDm->preAlgorithm = pCoexDm->curAlgorithm; + } +} + +VOID +halbtc8192e1ant_RunCoexistMechanism( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bWifiConnected=FALSE, bBtHsOn=FALSE; + BOOLEAN bIncreaseScanDevNum=FALSE; + BOOLEAN bBtCtrlAggBufSize=FALSE; + BOOLEAN bMiracastPlusBt=FALSE; + u1Byte aggBufSize=5; + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiLinkStatus=0; + u4Byte numOfWifiLink=0; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism()===>\n")); + + if(pBtCoexist->bManualControl) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n")); + return; + } + + if(pBtCoexist->bStopCoexDm) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n")); + return; + } + + if(pCoexSta->bUnderIps) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi is under IPS !!!\n")); + return; + } + + if( (BT_8192E_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) || + (BT_8192E_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + bIncreaseScanDevNum = TRUE; + } + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, &bIncreaseScanDevNum); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_LINK_STATUS, &wifiLinkStatus); + numOfWifiLink = wifiLinkStatus>>16; + + if((numOfWifiLink>=2) || (wifiLinkStatus&WIFI_P2P_GO_CONNECTED)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], Multi-Port numOfWifiLink = %d, wifiLinkStatus = 0x%x\n", numOfWifiLink,wifiLinkStatus) ); + + if(pBtLinkInfo->bBtLinkExist) + { + halbtc8192e1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 1, 1, 0, 1); + bMiracastPlusBt = TRUE; + } + else + { + halbtc8192e1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + bMiracastPlusBt = FALSE; + } + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_MIRACAST_PLUS_BT, &bMiracastPlusBt); + halbtc8192e1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, bBtCtrlAggBufSize, aggBufSize); + + if ( (pBtLinkInfo->bA2dpExist) && (pCoexSta->bC2hBtInquiryPage) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], BT Is Inquirying \n") ); + halbtc8192e1ant_ActionBtInquiry(pBtCoexist); + } + else + halbtc8192e1ant_ActionWifiMultiPort(pBtCoexist); + + return; + } + else + { + bMiracastPlusBt = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_MIRACAST_PLUS_BT, &bMiracastPlusBt); + } + + if ( (pBtLinkInfo->bBtLinkExist) && (bWifiConnected) ) + { + halbtc8192e1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 1, 1, 0, 1); + + if(pBtLinkInfo->bScoExist) + halbtc8192e1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, TRUE, 0x5); + else + halbtc8192e1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, TRUE, 0x8); + + halbtc8192e1ant_SwMechanism(pBtCoexist, TRUE); + halbtc8192e1ant_RunSwCoexistMechanism(pBtCoexist); //just print debug message + } + else + { + halbtc8192e1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + + halbtc8192e1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x5); + + halbtc8192e1ant_SwMechanism(pBtCoexist, FALSE); + halbtc8192e1ant_RunSwCoexistMechanism(pBtCoexist); ////just print debug message + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + if(pCoexSta->bC2hBtInquiryPage) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], BT Is Inquirying \n") ); + halbtc8192e1ant_ActionBtInquiry(pBtCoexist); + return; + } + else if(bBtHsOn) + { + halbtc8192e1ant_ActionHs(pBtCoexist); + return; + } + + + if(!bWifiConnected) + { + BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi is non connected-idle !!!\n")); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + + if(bScan || bLink || bRoam) + { + if (bScan) + halbtc8192e1ant_ActionWifiNotConnectedScan(pBtCoexist); + else + halbtc8192e1ant_ActionWifiNotConnectedAssoAuth(pBtCoexist); + } + else + halbtc8192e1ant_ActionWifiNotConnected(pBtCoexist); + } + else // wifi LPS/Busy + { + halbtc8192e1ant_ActionWifiConnected(pBtCoexist); + } +} + +VOID +halbtc8192e1ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + // force to reset coex mechanism + + // sw all off + halbtc8192e1ant_SwMechanism(pBtCoexist, FALSE); + + //halbtc8192e1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8); + halbtc8192e1ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 0); + + pCoexSta->popEventCnt = 0; +} + +VOID +halbtc8192e1ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ) +{ + u4Byte u4Tmp=0; + u2Byte u2Tmp=0; + u1Byte u1Tmp=0; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 1Ant Init HW Config!!\n")); + + // antenna sw ctrl to bt + halbtc8192e1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, TRUE, FALSE); + + halbtc8192e1ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 0); + + // antenna switch control parameter + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x858, 0x55555555); + + // coex parameters + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x778, 0x1); + // 0x790[5:0]=0x5 + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x790); + u1Tmp &= 0xc0; + u1Tmp |= 0x5; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x790, u1Tmp); + + // enable counter statistics + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0x4); + + // enable PTA + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x20); + // enable mailbox interface + u2Tmp = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0x40); + u2Tmp |= BIT9; + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x40, u2Tmp); + + // enable PTA I2C mailbox + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x101); + u1Tmp |= BIT4; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x101, u1Tmp); + + // enable bt clock when wifi is disabled. + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x93); + u1Tmp |= BIT0; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x93, u1Tmp); + // enable bt clock when suspend. + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x7); + u1Tmp |= BIT0; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x7, u1Tmp); +} + + +/* +VOID +halbtc8192e1ant_WifiOffHwCfg( + IN PBTC_COEXIST pBtCoexist + ) +{ + // set wlan_act to low + //pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0x4); +} +*/ + +//============================================================ +// work around function start with wa_halbtc8192e1ant_ +//============================================================ +//============================================================ +// extern function start with EXhalbtc8192e1ant_ +//============================================================ +VOID +EXhalbtc8192e1ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ) +{ +#if 0 + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + u1Byte u1Tmp=0x0; + u2Byte u2Tmp=0x0; + + pBtCoexist->bStopCoexDm = TRUE; + + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x67, 0x20); + + // enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. + u2Tmp = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0x2); + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x2, u2Tmp|BIT0|BIT1); + + // set GRAN_BT = 1 + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x765, 0x18); + // set WLAN_ACT = 0 + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0x4); + + // + // S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) + // Local setting bit define + // BIT0: "0" for no antenna inverse; "1" for antenna inverse + // BIT1: "0" for internal switch; "1" for external switch + // BIT2: "0" for one antenna; "1" for two antenna + // NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 + if(pBtCoexist->chipInterface == BTC_INTF_USB) + { + // fixed at S0 for USB interface + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x0); + + u1Tmp |= 0x1; // antenna inverse + pBtCoexist->fBtcWriteLocalReg1Byte(pBtCoexist, 0xfe08, u1Tmp); + + pBoardInfo->btdmAntPos = BTC_ANTENNA_AT_AUX_PORT; + } + else + { + // for PCIE and SDIO interface, we check efuse 0xc3[6] + if(pBoardInfo->singleAntPath == 0) + { + // set to S1 + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x280); + pBoardInfo->btdmAntPos = BTC_ANTENNA_AT_MAIN_PORT; + } + else if(pBoardInfo->singleAntPath == 1) + { + // set to S0 + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x0); + u1Tmp |= 0x1; // antenna inverse + pBoardInfo->btdmAntPos = BTC_ANTENNA_AT_AUX_PORT; + } + + if(pBtCoexist->chipInterface == BTC_INTF_PCI) + { + pBtCoexist->fBtcWriteLocalReg1Byte(pBtCoexist, 0x384, u1Tmp); + } + else if(pBtCoexist->chipInterface == BTC_INTF_SDIO) + { + pBtCoexist->fBtcWriteLocalReg1Byte(pBtCoexist, 0x60, u1Tmp); + } + } +#endif +} + +VOID +EXhalbtc8192e1ant_PreLoadFirmware( + IN PBTC_COEXIST pBtCoexist + ) +{ +} + +VOID +EXhalbtc8192e1ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ) +{ + halbtc8192e1ant_InitHwConfig(pBtCoexist, bWifiOnly); + pBtCoexist->bStopCoexDm = FALSE; +} + +VOID +EXhalbtc8192e1ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Coex Mechanism Init!!\n")); + + pBtCoexist->bStopCoexDm = FALSE; + + halbtc8192e1ant_InitCoexDm(pBtCoexist); + + halbtc8192e1ant_QueryBtInfo(pBtCoexist); +} + +VOID +EXhalbtc8192e1ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + pu1Byte cliBuf=pBtCoexist->cliBuf; + u1Byte u1Tmp[4], i, btInfoExt, psTdmaCase=0; + u4Byte u4Tmp[4]; + u4Byte fwVer=0, btPatchVer=0; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cliBuf); + + if(pBtCoexist->bManualControl) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[Under Manual Control]============"); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n =========================================="); + CL_PRINTF(cliBuf); + } + if(pBtCoexist->bStopCoexDm) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[Coex is STOPPED]============"); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n =========================================="); + CL_PRINTF(cliBuf); + } + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:", \ + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \ + ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion); + CL_PRINTF(cliBuf); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_BT_PATCH_VER, &btPatchVer); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)", "CoexVer/ FwVer/ PatchVer", \ + GLCoexVerDate8192e1Ant, GLCoexVer8192e1Ant, fwVer, btPatchVer, btPatchVer); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", "Wifi channel informed to BT", \ + pCoexDm->wifiChnlInfo[0], pCoexDm->wifiChnlInfo[1], + pCoexDm->wifiChnlInfo[2]); + CL_PRINTF(cliBuf); + + // wifi status + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Wifi Status]============"); + CL_PRINTF(cliBuf); + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[BT Status]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", "BT [status/ rssi/ retryCnt]", \ + ((pBtCoexist->btInfo.bBtDisabled)? ("disabled"): ((pCoexSta->bC2hBtInquiryPage)?("inquiry/page scan"):((BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus)? "non-connected idle": + ( (BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus)? "connected-idle":"busy")))), + pCoexSta->btRssi, pCoexSta->btRetryCnt); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP", \ + pBtLinkInfo->bScoExist, pBtLinkInfo->bHidExist, pBtLinkInfo->bPanExist, pBtLinkInfo->bA2dpExist); + CL_PRINTF(cliBuf); + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO); + + btInfoExt = pCoexSta->btInfoExt; + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Info A2DP rate", \ + (btInfoExt&BIT0)? "Basic rate":"EDR rate"); + CL_PRINTF(cliBuf); + + for(i=0; ibtInfoC2hCnt[i]) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", GLBtInfoSrc8192e1Ant[i], \ + pCoexSta->btInfoC2h[i][0], pCoexSta->btInfoC2h[i][1], + pCoexSta->btInfoC2h[i][2], pCoexSta->btInfoC2h[i][3], + pCoexSta->btInfoC2h[i][4], pCoexSta->btInfoC2h[i][5], + pCoexSta->btInfoC2h[i][6], pCoexSta->btInfoC2hCnt[i]); + CL_PRINTF(cliBuf); + } + } + + if(!pBtCoexist->bManualControl) + { + // Sw mechanism + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %d ", "DelBA/ BtCtrlAgg/ AggSize", \ + (pBtCoexist->btInfo.bRejectAggPkt? "Yes":"No"), (pBtCoexist->btInfo.bBtCtrlAggBufSize? "Yes":"No"), + pBtCoexist->btInfo.aggBufSize); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "Rate Mask", \ + pBtCoexist->btInfo.raMask); + CL_PRINTF(cliBuf); + + // Fw mechanism + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============"); + CL_PRINTF(cliBuf); + + psTdmaCase = pCoexDm->curPsTdma; + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)", "PS TDMA", \ + pCoexDm->psTdmaPara[0], pCoexDm->psTdmaPara[1], + pCoexDm->psTdmaPara[2], pCoexDm->psTdmaPara[3], + pCoexDm->psTdmaPara[4], psTdmaCase, pCoexDm->bAutoTdmaAdjust); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "Latest error condition(should be 0)", \ + pCoexDm->errorCondition); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ", "IgnWlanAct", \ + pCoexDm->bCurIgnoreWlanAct); + CL_PRINTF(cliBuf); + } + + // Hw setting + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============"); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc04); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xd04); + u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x90c); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0xc04/ 0xd04/ 0x90c", \ + u4Tmp[0], u4Tmp[1], u4Tmp[2]); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x778); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x778", \ + u1Tmp[0]); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x92c); + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x930); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x92c/ 0x930", \ + (u1Tmp[0]), u4Tmp[0]); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x40); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4f); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x40/ 0x4f", \ + u1Tmp[0], u1Tmp[1]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x550); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x522); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x550(bcn ctrl)/0x522", \ + u4Tmp[0], u1Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc50); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", \ + u4Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c0); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c4); + u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c8); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x6cc); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", \ + u4Tmp[0], u4Tmp[1], u4Tmp[2], u1Tmp[0]); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x770(hp rx[31:16]/tx[15:0])", \ + pCoexSta->highPriorityRx, pCoexSta->highPriorityTx); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x774(lp rx[31:16]/tx[15:0])", \ + pCoexSta->lowPriorityRx, pCoexSta->lowPriorityTx); + CL_PRINTF(cliBuf); +#if(BT_AUTO_REPORT_ONLY_8192E_1ANT == 1) + halbtc8192e1ant_MonitorBtCtr(pBtCoexist); +#endif + + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + +VOID +EXhalbtc8192e1ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + u4Byte u4Tmp=0; + + if(pBtCoexist->bManualControl || pBtCoexist->bStopCoexDm) + return; + + if(BTC_IPS_ENTER == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS ENTER notify\n")); + pCoexSta->bUnderIps = TRUE; + + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + halbtc8192e1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FALSE, TRUE); + } + else if(BTC_IPS_LEAVE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS LEAVE notify\n")); + pCoexSta->bUnderIps = FALSE; + + halbtc8192e1ant_InitHwConfig(pBtCoexist, FALSE); + halbtc8192e1ant_InitCoexDm(pBtCoexist); + halbtc8192e1ant_QueryBtInfo(pBtCoexist); + } +} + +VOID +EXhalbtc8192e1ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(pBtCoexist->bManualControl || pBtCoexist->bStopCoexDm) + return; + + if(BTC_LPS_ENABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS ENABLE notify\n")); + pCoexSta->bUnderLps = TRUE; + } + else if(BTC_LPS_DISABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS DISABLE notify\n")); + pCoexSta->bUnderLps = FALSE; + } +} + +VOID +EXhalbtc8192e1ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + BOOLEAN bWifiConnected=FALSE, bBtHsOn=FALSE; + u4Byte wifiLinkStatus=0; + u4Byte numOfWifiLink=0; + BOOLEAN bBtCtrlAggBufSize=FALSE; + u1Byte aggBufSize=5; + + u1Byte u1Tmpa, u1Tmpb; + u4Byte u4Tmp; + + if(pBtCoexist->bManualControl || + pBtCoexist->bStopCoexDm ) + return; + + if(BTC_SCAN_START == type) + { + pCoexSta->bWiFiIsHighPriTask = TRUE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n")); + + halbtc8192e1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8); //Force antenna setup for no scan result issue + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x948); + u1Tmpa = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x765); + u1Tmpb = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x67); + + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n", + u4Tmp, u1Tmpa, u1Tmpb)); + } + else + { + pCoexSta->bWiFiIsHighPriTask = FALSE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n")); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_AP_NUM, &pCoexSta->nScanAPNum); + } + + if(pBtCoexist->btInfo.bBtDisabled) + return; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + + halbtc8192e1ant_QueryBtInfo(pBtCoexist); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_LINK_STATUS, &wifiLinkStatus); + numOfWifiLink = wifiLinkStatus>>16; + if(numOfWifiLink >= 2) + { + halbtc8192e1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8192e1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, bBtCtrlAggBufSize, aggBufSize); + halbtc8192e1ant_ActionWifiMultiPort(pBtCoexist); + return; + } + + if(pCoexSta->bC2hBtInquiryPage) + { + halbtc8192e1ant_ActionBtInquiry(pBtCoexist); + return; + } + else if(bBtHsOn) + { + halbtc8192e1ant_ActionHs(pBtCoexist); + return; + } + + if(BTC_SCAN_START == type) + { + //RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n")); + if(!bWifiConnected) // non-connected scan + { + halbtc8192e1ant_ActionWifiNotConnectedScan(pBtCoexist); + } + else // wifi is connected + { + halbtc8192e1ant_ActionWifiConnectedScan(pBtCoexist); + } + } + else if(BTC_SCAN_FINISH == type) + { + //RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n")); + if(!bWifiConnected) // non-connected scan + { + halbtc8192e1ant_ActionWifiNotConnected(pBtCoexist); + } + else + { + halbtc8192e1ant_ActionWifiConnected(pBtCoexist); + } + } +} + +VOID +EXhalbtc8192e1ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + BOOLEAN bWifiConnected=FALSE, bBtHsOn=FALSE; + u4Byte wifiLinkStatus=0; + u4Byte numOfWifiLink=0; + BOOLEAN bBtCtrlAggBufSize=FALSE; + u1Byte aggBufSize=5; + + if(pBtCoexist->bManualControl || + pBtCoexist->bStopCoexDm || + pBtCoexist->btInfo.bBtDisabled ) + return; + + if(BTC_ASSOCIATE_START == type) + { + pCoexSta->bWiFiIsHighPriTask = TRUE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n")); + pCoexDm->nArpCnt = 0; + } + else + { + pCoexSta->bWiFiIsHighPriTask = FALSE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n")); + //pCoexDm->nArpCnt = 0; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_LINK_STATUS, &wifiLinkStatus); + numOfWifiLink = wifiLinkStatus>>16; + if(numOfWifiLink >= 2) + { + halbtc8192e1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8192e1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, bBtCtrlAggBufSize, aggBufSize); + halbtc8192e1ant_ActionWifiMultiPort(pBtCoexist); + return; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + if(pCoexSta->bC2hBtInquiryPage) + { + halbtc8192e1ant_ActionBtInquiry(pBtCoexist); + return; + } + else if(bBtHsOn) + { + halbtc8192e1ant_ActionHs(pBtCoexist); + return; + } + + if(BTC_ASSOCIATE_START == type) + { + //RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n")); + halbtc8192e1ant_ActionWifiNotConnectedAssoAuth(pBtCoexist); + } + else if(BTC_ASSOCIATE_FINISH == type) + { + //RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n")); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + if(!bWifiConnected) // non-connected scan + { + halbtc8192e1ant_ActionWifiNotConnected(pBtCoexist); + } + else + { + halbtc8192e1ant_ActionWifiConnected(pBtCoexist); + } + } +} + +VOID +EXhalbtc8192e1ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + u1Byte H2C_Parameter[3] ={0}; + u4Byte wifiBw; + u1Byte wifiCentralChnl; + BOOLEAN bWifiUnderBMode = FALSE; + + if(pBtCoexist->bManualControl || + pBtCoexist->bStopCoexDm || + pBtCoexist->btInfo.bBtDisabled ) + return; + + if(BTC_MEDIA_CONNECT == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA connect notify\n")); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, &bWifiUnderBMode); + + //Set CCK Tx/Rx high Pri except 11b mode + if (bWifiUnderBMode) + { + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cd, 0x00); //CCK Tx + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cf, 0x00); //CCK Rx + } + else + { + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cd, 0x10); //CCK Tx + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cf, 0x10); //CCK Rx + } + + pCoexDm->backupArfrCnt1 = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x430); + pCoexDm->backupArfrCnt2 = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x434); + pCoexDm->backupRetryLimit = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0x42a); + pCoexDm->backupAmpduMaxTime = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x456); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA disconnect notify\n")); + pCoexDm->nArpCnt = 0; + + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cd, 0x0); //CCK Tx + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cf, 0x0); //CCK Rx + } + + // only 2.4G we need to inform bt the chnl mask + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, &wifiCentralChnl); + if( (BTC_MEDIA_CONNECT == type) && + (wifiCentralChnl <= 14) ) + { + //H2C_Parameter[0] = 0x1; + H2C_Parameter[0] = 0x0; + H2C_Parameter[1] = wifiCentralChnl; + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + H2C_Parameter[2] = 0x30; + else + H2C_Parameter[2] = 0x20; + } + + pCoexDm->wifiChnlInfo[0] = H2C_Parameter[0]; + pCoexDm->wifiChnlInfo[1] = H2C_Parameter[1]; + pCoexDm->wifiChnlInfo[2] = H2C_Parameter[2]; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x66=0x%x\n", + H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x66, 3, H2C_Parameter); +} + +VOID +EXhalbtc8192e1ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + BOOLEAN bBtHsOn=FALSE; + u4Byte wifiLinkStatus=0; + u4Byte numOfWifiLink=0; + BOOLEAN bBtCtrlAggBufSize=FALSE; + u1Byte aggBufSize=5; + + if(pBtCoexist->bManualControl || + pBtCoexist->bStopCoexDm || + pBtCoexist->btInfo.bBtDisabled ) + return; + + if( BTC_PACKET_DHCP == type || + BTC_PACKET_EAPOL == type || + BTC_PACKET_ARP == type ) + { + if(BTC_PACKET_ARP == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], special Packet ARP notify\n")); + + pCoexDm->nArpCnt++; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ARP Packet Count = %d\n", pCoexDm->nArpCnt)); + + if(pCoexDm->nArpCnt >= 10) // if APR PKT > 10 after connect, do not go to ActionWifiConnectedSpecialPacket(pBtCoexist) + { + pCoexSta->bWiFiIsHighPriTask = FALSE; + } + else + { + pCoexSta->bWiFiIsHighPriTask = TRUE; + } + } + else + { + pCoexSta->bWiFiIsHighPriTask = TRUE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], special Packet DHCP or EAPOL notify\n")); + } + } + else + { + pCoexSta->bWiFiIsHighPriTask = FALSE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], special Packet [Type = %d] notify\n", type)); + } + + pCoexSta->specialPktPeriodCnt = 0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_LINK_STATUS, &wifiLinkStatus); + numOfWifiLink = wifiLinkStatus>>16; + if(numOfWifiLink >= 2) + { + halbtc8192e1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8192e1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, bBtCtrlAggBufSize, aggBufSize); + halbtc8192e1ant_ActionWifiMultiPort(pBtCoexist); + return; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + if(pCoexSta->bC2hBtInquiryPage) + { + halbtc8192e1ant_ActionBtInquiry(pBtCoexist); + return; + } + else if(bBtHsOn) + { + halbtc8192e1ant_ActionHs(pBtCoexist); + return; + } + + if( BTC_PACKET_DHCP == type || + BTC_PACKET_EAPOL == type || + ( (BTC_PACKET_ARP == type ) && (pCoexSta->bWiFiIsHighPriTask) ) ) + { + halbtc8192e1ant_ActionWifiConnectedSpecialPacket(pBtCoexist); + } +} + +VOID +EXhalbtc8192e1ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + u1Byte btInfo=0; + u1Byte i, rspSource=0; + BOOLEAN bWifiConnected=FALSE; + BOOLEAN bBtBusy=FALSE; + + pCoexSta->bC2hBtInfoReqSent = FALSE; + + rspSource = tmpBuf[0]&0xf; + if(rspSource >= BT_INFO_SRC_8192E_1ANT_MAX) + rspSource = BT_INFO_SRC_8192E_1ANT_WIFI_FW; + pCoexSta->btInfoC2hCnt[rspSource]++; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Bt info[%d], length=%d, hex data=[", rspSource, length)); + for(i=0; ibtInfoC2h[rspSource][i] = tmpBuf[i]; + if(i == 1) + btInfo = tmpBuf[i]; + if(i == length-1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x]\n", tmpBuf[i])); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x, ", tmpBuf[i])); + } + } + + if(BT_INFO_SRC_8192E_1ANT_WIFI_FW != rspSource) + { + pCoexSta->btRetryCnt = // [3:0] + pCoexSta->btInfoC2h[rspSource][2]&0xf; + + if (pCoexSta->btRetryCnt >= 1) + pCoexSta->popEventCnt++; + + if (pCoexSta->btInfoC2h[rspSource][2]&0x20) + pCoexSta->bC2hBtPage = TRUE; + else + pCoexSta->bC2hBtPage = FALSE; + + pCoexSta->btRssi = + pCoexSta->btInfoC2h[rspSource][3]*2-90; + //pCoexSta->btInfoC2h[rspSource][3]*2+10; + + pCoexSta->btInfoExt = + pCoexSta->btInfoC2h[rspSource][4]; + + pCoexSta->bBtTxRxMask = (pCoexSta->btInfoC2h[rspSource][2]&0x40); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TX_RX_MASK, &pCoexSta->bBtTxRxMask); + if(!pCoexSta->bBtTxRxMask) + { + /* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x15\n")); + pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x3c, 0x15); + } + + // Here we need to resend some wifi info to BT + // because bt is reset and loss of the info. + if(pCoexSta->btInfoExt & BIT1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n")); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + if(bWifiConnected) + { + EXhalbtc8192e1ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_CONNECT); + } + else + { + EXhalbtc8192e1ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); + } + } + + if(pCoexSta->btInfoExt & BIT3) + { + if(!pBtCoexist->bManualControl && !pBtCoexist->bStopCoexDm) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n")); + halbtc8192e1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE); + } + } + else + { + // BT already NOT ignore Wlan active, do nothing here. + } +#if(BT_AUTO_REPORT_ONLY_8192E_1ANT == 0) + if( (pCoexSta->btInfoExt & BIT4) ) + { + // BT auto report already enabled, do nothing + } + else + { + halbtc8192e1ant_BtAutoReport(pBtCoexist, FORCE_EXEC, TRUE); + } +#endif + } + + // check BIT2 first ==> check if bt is under inquiry or page scan + if(btInfo & BT_INFO_8192E_1ANT_B_INQ_PAGE) + pCoexSta->bC2hBtInquiryPage = TRUE; + else + pCoexSta->bC2hBtInquiryPage = FALSE; + + // set link exist status + if(!(btInfo&BT_INFO_8192E_1ANT_B_CONNECTION)) + { + pCoexSta->bBtLinkExist = FALSE; + pCoexSta->bPanExist = FALSE; + pCoexSta->bA2dpExist = FALSE; + pCoexSta->bHidExist = FALSE; + pCoexSta->bScoExist = FALSE; + } + else // connection exists + { + pCoexSta->bBtLinkExist = TRUE; + if(btInfo & BT_INFO_8192E_1ANT_B_FTP) + pCoexSta->bPanExist = TRUE; + else + pCoexSta->bPanExist = FALSE; + if(btInfo & BT_INFO_8192E_1ANT_B_A2DP) + pCoexSta->bA2dpExist = TRUE; + else + pCoexSta->bA2dpExist = FALSE; + if(btInfo & BT_INFO_8192E_1ANT_B_HID) + pCoexSta->bHidExist = TRUE; + else + pCoexSta->bHidExist = FALSE; + if(btInfo & BT_INFO_8192E_1ANT_B_SCO_ESCO) + pCoexSta->bScoExist = TRUE; + else + pCoexSta->bScoExist = FALSE; + } + + halbtc8192e1ant_UpdateBtLinkInfo(pBtCoexist); + + btInfo = btInfo & 0x1f; //mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) + + if(!(btInfo&BT_INFO_8192E_1ANT_B_CONNECTION)) + { + pCoexDm->btStatus = BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n")); + } + else if(btInfo == BT_INFO_8192E_1ANT_B_CONNECTION) // connection exists but no busy + { + pCoexDm->btStatus = BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n")); + } + else if((btInfo&BT_INFO_8192E_1ANT_B_SCO_ESCO) || + (btInfo&BT_INFO_8192E_1ANT_B_SCO_BUSY)) + { + pCoexDm->btStatus = BT_8192E_1ANT_BT_STATUS_SCO_BUSY; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT SCO busy!!!\n")); + } + else if(btInfo&BT_INFO_8192E_1ANT_B_ACL_BUSY) + { + if(BT_8192E_1ANT_BT_STATUS_ACL_BUSY != pCoexDm->btStatus) + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->btStatus = BT_8192E_1ANT_BT_STATUS_ACL_BUSY; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT ACL busy!!!\n")); + } + else + { + pCoexDm->btStatus = BT_8192E_1ANT_BT_STATUS_MAX; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n")); + } + + if( (BT_8192E_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) || + (BT_8192E_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + bBtBusy = TRUE; + else + bBtBusy = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bBtBusy); + + halbtc8192e1ant_RunCoexistMechanism(pBtCoexist); +} + +VOID +EXhalbtc8192e1ant_RfStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + u4Byte u4Tmp; + u1Byte u1Tmpa,u1Tmpb, u1Tmpc; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RF Status notify\n")); + + if(BTC_RF_ON == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RF is turned ON!!\n")); + pBtCoexist->bStopCoexDm = FALSE; + } + else if(BTC_RF_OFF == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RF is turned OFF!!\n")); + + halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); + halbtc8192e1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FALSE, TRUE); + + halbtc8192e1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE); + pBtCoexist->bStopCoexDm = TRUE; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x948); + u1Tmpa = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x765); + u1Tmpb = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x67); + u1Tmpc = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x76e); + + + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x, 0x76e=0x%x\n", + u4Tmp, u1Tmpa, u1Tmpb, u1Tmpc)); + + } +} + +VOID +EXhalbtc8192e1ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte u4Tmp; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Halt notify\n")); + + halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); + halbtc8192e1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FALSE, TRUE); + + halbtc8192e1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE); + + EXhalbtc8192e1ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); + + pBtCoexist->bStopCoexDm = TRUE; +} + +VOID +EXhalbtc8192e1ant_PnpNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte pnpState + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Pnp notify\n")); + + if(BTC_WIFI_PNP_SLEEP == pnpState) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Pnp notify to SLEEP\n")); + + halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + halbtc8192e1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + halbtc8192e1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FALSE, TRUE); + + pBtCoexist->bStopCoexDm = TRUE; + } + else if(BTC_WIFI_PNP_WAKE_UP == pnpState) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Pnp notify to WAKE UP\n")); + pBtCoexist->bStopCoexDm = FALSE; + halbtc8192e1ant_InitHwConfig(pBtCoexist, FALSE); + halbtc8192e1ant_InitCoexDm(pBtCoexist); + halbtc8192e1ant_QueryBtInfo(pBtCoexist); + } +} + +VOID +EXhalbtc8192e1ant_CoexDmReset( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], *****************Coex DM Reset*****************\n")); + + halbtc8192e1ant_InitHwConfig(pBtCoexist, FALSE); + //pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + //pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x2, 0xfffff, 0x0); + halbtc8192e1ant_InitCoexDm(pBtCoexist); +} + +VOID +EXhalbtc8192e1ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ) +{ + static u1Byte disVerInfoCnt=0; + u4Byte fwVer=0, btPatchVer=0; + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ==========================Periodical===========================\n")); + + if(disVerInfoCnt <= 5) + { + disVerInfoCnt += 1; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ****************************************************************\n")); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Ant PG Num/ Ant Mech/ Ant Pos = %d/ %d/ %d\n", + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum, pBoardInfo->btdmAntPos)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT stack/ hci ext ver = %s / %d\n", + ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion)); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_BT_PATCH_VER, &btPatchVer); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CoexVer/ FwVer/ PatchVer = %d_%x/ 0x%x/ 0x%x(%d)\n", + GLCoexVerDate8192e1Ant, GLCoexVer8192e1Ant, fwVer, btPatchVer, btPatchVer)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ****************************************************************\n")); + } + +#if(BT_AUTO_REPORT_ONLY_8192E_1ANT == 0) + halbtc8192e1ant_QueryBtInfo(pBtCoexist); + halbtc8192e1ant_MonitorBtEnableDisable(pBtCoexist); +#else + halbtc8192e1ant_MonitorBtCtr(pBtCoexist); + halbtc8192e1ant_MonitorWiFiCtr(pBtCoexist); + + if( halbtc8192e1ant_IsWifiStatusChanged(pBtCoexist) || + pCoexDm->bAutoTdmaAdjust ) + { + + halbtc8192e1ant_RunCoexistMechanism(pBtCoexist); + } + + pCoexSta->specialPktPeriodCnt++; +#endif +} + + +VOID +EXhalbtc8192e1ant_DbgControl( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte opCode, + IN u1Byte opLen, + IN pu1Byte pData + ) +{ + switch(opCode) + { + case BTC_DBG_SET_COEX_NORMAL: + pBtCoexist->bManualControl = FALSE; + halbtc8192e1ant_InitCoexDm(pBtCoexist); + break; + case BTC_DBG_SET_COEX_WIFI_ONLY: + pBtCoexist->bManualControl = TRUE; + halbtc8192e1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 9); + break; + case BTC_DBG_SET_COEX_BT_ONLY: + // todo + break; + default: + break; + } +} + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8192e1Ant.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8192e1Ant.h new file mode 100644 index 000000000..8c06cff12 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8192e1Ant.h @@ -0,0 +1,255 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//=========================================== +// The following is for 8192E 1ANT BT Co-exist definition +//=========================================== +#define BT_AUTO_REPORT_ONLY_8192E_1ANT 1 + +#define BT_INFO_8192E_1ANT_B_FTP BIT7 +#define BT_INFO_8192E_1ANT_B_A2DP BIT6 +#define BT_INFO_8192E_1ANT_B_HID BIT5 +#define BT_INFO_8192E_1ANT_B_SCO_BUSY BIT4 +#define BT_INFO_8192E_1ANT_B_ACL_BUSY BIT3 +#define BT_INFO_8192E_1ANT_B_INQ_PAGE BIT2 +#define BT_INFO_8192E_1ANT_B_SCO_ESCO BIT1 +#define BT_INFO_8192E_1ANT_B_CONNECTION BIT0 + +#define BT_INFO_8192E_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ + (((_BT_INFO_EXT_&BIT0))? TRUE:FALSE) + +#define BTC_RSSI_COEX_THRESH_TOL_8192E_1ANT 2 + +#define BT_8192E_1ANT_WIFI_NOISY_THRESH 30 //max: 255 + +typedef enum _BT_INFO_SRC_8192E_1ANT{ + BT_INFO_SRC_8192E_1ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8192E_1ANT_BT_RSP = 0x1, + BT_INFO_SRC_8192E_1ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8192E_1ANT_MAX +}BT_INFO_SRC_8192E_1ANT,*PBT_INFO_SRC_8192E_1ANT; + +typedef enum _BT_8192E_1ANT_BT_STATUS{ + BT_8192E_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8192E_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8192E_1ANT_BT_STATUS_INQ_PAGE = 0x2, + BT_8192E_1ANT_BT_STATUS_ACL_BUSY = 0x3, + BT_8192E_1ANT_BT_STATUS_SCO_BUSY = 0x4, + BT_8192E_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, + BT_8192E_1ANT_BT_STATUS_MAX +}BT_8192E_1ANT_BT_STATUS,*PBT_8192E_1ANT_BT_STATUS; + +typedef enum _BT_8192E_1ANT_WIFI_STATUS{ + BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8192E_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1, + BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2, + BT_8192E_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3, + BT_8192E_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4, + BT_8192E_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5, + BT_8192E_1ANT_WIFI_STATUS_MAX +}BT_8192E_1ANT_WIFI_STATUS,*PBT_8192E_1ANT_WIFI_STATUS; + +typedef enum _BT_8192E_1ANT_COEX_ALGO{ + BT_8192E_1ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8192E_1ANT_COEX_ALGO_SCO = 0x1, + BT_8192E_1ANT_COEX_ALGO_HID = 0x2, + BT_8192E_1ANT_COEX_ALGO_A2DP = 0x3, + BT_8192E_1ANT_COEX_ALGO_A2DP_PANHS = 0x4, + BT_8192E_1ANT_COEX_ALGO_PANEDR = 0x5, + BT_8192E_1ANT_COEX_ALGO_PANHS = 0x6, + BT_8192E_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7, + BT_8192E_1ANT_COEX_ALGO_PANEDR_HID = 0x8, + BT_8192E_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, + BT_8192E_1ANT_COEX_ALGO_HID_A2DP = 0xa, + BT_8192E_1ANT_COEX_ALGO_MAX = 0xb, +}BT_8192E_1ANT_COEX_ALGO,*PBT_8192E_1ANT_COEX_ALGO; + +typedef struct _COEX_DM_8192E_1ANT{ + // fw mechanism + BOOLEAN bCurIgnoreWlanAct; + BOOLEAN bPreIgnoreWlanAct; + u1Byte prePsTdma; + u1Byte curPsTdma; + u1Byte psTdmaPara[5]; + u1Byte psTdmaDuAdjType; + BOOLEAN bAutoTdmaAdjust; + BOOLEAN bPrePsTdmaOn; + BOOLEAN bCurPsTdmaOn; + BOOLEAN bPreBtAutoReport; + BOOLEAN bCurBtAutoReport; + u1Byte preLps; + u1Byte curLps; + u1Byte preRpwm; + u1Byte curRpwm; + + // sw mechanism + BOOLEAN bPreLowPenaltyRa; + BOOLEAN bCurLowPenaltyRa; + u4Byte preVal0x6c0; + u4Byte curVal0x6c0; + u4Byte preVal0x6c4; + u4Byte curVal0x6c4; + u4Byte preVal0x6c8; + u4Byte curVal0x6c8; + u1Byte preVal0x6cc; + u1Byte curVal0x6cc; + BOOLEAN bLimitedDig; + + u4Byte backupArfrCnt1; // Auto Rate Fallback Retry cnt + u4Byte backupArfrCnt2; // Auto Rate Fallback Retry cnt + u2Byte backupRetryLimit; + u1Byte backupAmpduMaxTime; + + // algorithm related + u1Byte preAlgorithm; + u1Byte curAlgorithm; + u1Byte btStatus; + u1Byte wifiChnlInfo[3]; + + u4Byte preRaMask; + u4Byte curRaMask; + u1Byte preArfrType; + u1Byte curArfrType; + u1Byte preRetryLimitType; + u1Byte curRetryLimitType; + u1Byte preAmpduTimeType; + u1Byte curAmpduTimeType; + u4Byte nArpCnt; + + u1Byte errorCondition; +} COEX_DM_8192E_1ANT, *PCOEX_DM_8192E_1ANT; + +typedef struct _COEX_STA_8192E_1ANT{ + BOOLEAN bBtLinkExist; + BOOLEAN bScoExist; + BOOLEAN bA2dpExist; + BOOLEAN bHidExist; + BOOLEAN bPanExist; + + BOOLEAN bUnderLps; + BOOLEAN bUnderIps; + u4Byte specialPktPeriodCnt; + u4Byte highPriorityTx; + u4Byte highPriorityRx; + u4Byte lowPriorityTx; + u4Byte lowPriorityRx; + s1Byte btRssi; + BOOLEAN bBtTxRxMask; + u1Byte preBtRssiState; + u1Byte preWifiRssiState[4]; + BOOLEAN bC2hBtInfoReqSent; + u1Byte btInfoC2h[BT_INFO_SRC_8192E_1ANT_MAX][10]; + u4Byte btInfoC2hCnt[BT_INFO_SRC_8192E_1ANT_MAX]; + BOOLEAN bC2hBtInquiryPage; + BOOLEAN bC2hBtPage; //Add for win8.1 page out issue + BOOLEAN bWiFiIsHighPriTask; //Add for win8.1 page out issue + u1Byte btRetryCnt; + u1Byte btInfoExt; + u4Byte popEventCnt; + u1Byte nScanAPNum; + + u4Byte nCRCOK_CCK; + u4Byte nCRCOK_11g; + u4Byte nCRCOK_11n; + u4Byte nCRCOK_11nAgg; + + u4Byte nCRCErr_CCK; + u4Byte nCRCErr_11g; + u4Byte nCRCErr_11n; + u4Byte nCRCErr_11nAgg; + + BOOLEAN bCCKLock; + BOOLEAN bPreCCKLock; + u1Byte nCoexTableType; + + BOOLEAN bForceLpsOn; +}COEX_STA_8192E_1ANT, *PCOEX_STA_8192E_1ANT; + +//=========================================== +// The following is interface which will notify coex module. +//=========================================== +VOID +EXhalbtc8192e1ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8192e1ant_PreLoadFirmware( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8192e1ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ); +VOID +EXhalbtc8192e1ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8192e1ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8192e1ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8192e1ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8192e1ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8192e1ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8192e1ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8192e1ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ); +VOID +EXhalbtc8192e1ant_RfStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8192e1ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8192e1ant_PnpNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte pnpState + ); +VOID +EXhalbtc8192e1ant_CoexDmReset( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8192e1ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8192e1ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8192e1ant_DbgControl( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte opCode, + IN u1Byte opLen, + IN pu1Byte pData + ); + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8192e2Ant.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8192e2Ant.c new file mode 100644 index 000000000..481e87768 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8192e2Ant.c @@ -0,0 +1,5028 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//============================================================ +// Description: +// +// This file is for RTL8192E Co-exist mechanism +// +// History +// 2012/11/15 Cosa first check in. +// +//============================================================ + +//============================================================ +// include files +//============================================================ +#include "Mp_Precomp.h" +#if(BT_30_SUPPORT == 1) +//============================================================ +// Global variables, these are static variables +//============================================================ +static COEX_DM_8192E_2ANT GLCoexDm8192e2Ant; +static PCOEX_DM_8192E_2ANT pCoexDm=&GLCoexDm8192e2Ant; +static COEX_STA_8192E_2ANT GLCoexSta8192e2Ant; +static PCOEX_STA_8192E_2ANT pCoexSta=&GLCoexSta8192e2Ant; + +const char *const GLBtInfoSrc8192e2Ant[]={ + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; + +u4Byte GLCoexVerDate8192e2Ant=20150615; +u4Byte GLCoexVer8192e2Ant=0x41; + +//============================================================ +// local function proto type if needed +//============================================================ +//============================================================ +// local function start with halbtc8192e2ant_ +//============================================================ +u1Byte +halbtc8192e2ant_BtRssiState( + u1Byte levelNum, + u1Byte rssiThresh, + u1Byte rssiThresh1 + ) +{ + s4Byte btRssi=0; + u1Byte btRssiState=pCoexSta->preBtRssiState; + + btRssi = pCoexSta->btRssi; + + if(levelNum == 2) + { + if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW)) + { + if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) + { + btRssiState = BTC_RSSI_STATE_HIGH; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else + { + if(btRssi < rssiThresh) + { + btRssiState = BTC_RSSI_STATE_LOW; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + else if(levelNum == 3) + { + if(rssiThresh > rssiThresh1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Rssi thresh error!!\n")); + return pCoexSta->preBtRssiState; + } + + if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW)) + { + if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) + { + btRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_MEDIUM) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_MEDIUM)) + { + if(btRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) + { + btRssiState = BTC_RSSI_STATE_HIGH; + } + else if(btRssi < rssiThresh) + { + btRssiState = BTC_RSSI_STATE_LOW; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_MEDIUM; + } + } + else + { + if(btRssi < rssiThresh1) + { + btRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + + pCoexSta->preBtRssiState = btRssiState; + + return btRssiState; +} + +u1Byte +halbtc8192e2ant_WifiRssiState( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte index, + IN u1Byte levelNum, + IN u1Byte rssiThresh, + IN u1Byte rssiThresh1 + ) +{ + s4Byte wifiRssi=0; + u1Byte wifiRssiState=pCoexSta->preWifiRssiState[index]; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); + + if(levelNum == 2) + { + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else + { + if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + else if(levelNum == 3) + { + if(rssiThresh > rssiThresh1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi RSSI thresh error!!\n")); + return pCoexSta->preWifiRssiState[index]; + } + + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_MEDIUM) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_MEDIUM)) + { + if(wifiRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_MEDIUM; + } + } + else + { + if(wifiRssi < rssiThresh1) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + + pCoexSta->preWifiRssiState[index] = wifiRssiState; + + return wifiRssiState; +} + +VOID +halbtc8192e2ant_MonitorBtEnableDisable( + IN PBTC_COEXIST pBtCoexist + ) +{ + static BOOLEAN bPreBtDisabled=FALSE; + static u4Byte btDisableCnt=0; + BOOLEAN bBtActive=TRUE, bBtDisabled=FALSE; + + // This function check if bt is disabled + + if( pCoexSta->highPriorityTx == 0 && + pCoexSta->highPriorityRx == 0 && + pCoexSta->lowPriorityTx == 0 && + pCoexSta->lowPriorityRx == 0) + { + bBtActive = FALSE; + } + if( pCoexSta->highPriorityTx == 0xffff && + pCoexSta->highPriorityRx == 0xffff && + pCoexSta->lowPriorityTx == 0xffff && + pCoexSta->lowPriorityRx == 0xffff) + { + bBtActive = FALSE; + } + if(bBtActive) + { + btDisableCnt = 0; + bBtDisabled = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is enabled !!\n")); + } + else + { + btDisableCnt++; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], bt all counters=0, %d times!!\n", + btDisableCnt)); + if(btDisableCnt >= 2) + { + bBtDisabled = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is disabled !!\n")); + } + } + if(bPreBtDisabled != bBtDisabled) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is from %s to %s!!\n", + (bPreBtDisabled ? "disabled":"enabled"), + (bBtDisabled ? "disabled":"enabled"))); + bPreBtDisabled = bBtDisabled; + if(!bBtDisabled) + { + } + else + { + } + } +} + +u4Byte +halbtc8192e2ant_DecideRaMask( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte ssType, + IN u4Byte raMaskType + ) +{ + u4Byte disRaMask=0x0; + + switch(raMaskType) + { + case 0: // normal mode + if(ssType == 2) + disRaMask = 0x0; // enable 2ss + else + disRaMask = 0xfff00000; // disable 2ss + break; + case 1: // disable cck 1/2 + if(ssType == 2) + disRaMask = 0x00000003; // enable 2ss + else + disRaMask = 0xfff00003; // disable 2ss + break; + case 2: // disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 + if(ssType == 2) + disRaMask = 0x0001f1f7; // enable 2ss + else + disRaMask = 0xfff1f1f7; // disable 2ss + break; + default: + break; + } + + return disRaMask; +} + +VOID +halbtc8192e2ant_UpdateRaMask( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u4Byte disRateMask + ) +{ + pCoexDm->curRaMask = disRateMask; + + if( bForceExec || (pCoexDm->preRaMask != pCoexDm->curRaMask)) + { + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_UPDATE_RAMASK, &pCoexDm->curRaMask); + } + pCoexDm->preRaMask = pCoexDm->curRaMask; +} + +VOID +halbtc8192e2ant_AutoRateFallbackRetry( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + BOOLEAN bWifiUnderBMode=FALSE; + + pCoexDm->curArfrType = type; + + if( bForceExec || (pCoexDm->preArfrType != pCoexDm->curArfrType)) + { + switch(pCoexDm->curArfrType) + { + case 0: // normal mode + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x430, pCoexDm->backupArfrCnt1); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x434, pCoexDm->backupArfrCnt2); + break; + case 1: + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, &bWifiUnderBMode); + if(bWifiUnderBMode) + { + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x430, 0x0); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x434, 0x01010101); + } + else + { + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x430, 0x0); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x434, 0x04030201); + } + break; + default: + break; + } + } + + pCoexDm->preArfrType = pCoexDm->curArfrType; +} + +VOID +halbtc8192e2ant_RetryLimit( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + pCoexDm->curRetryLimitType = type; + + if( bForceExec || (pCoexDm->preRetryLimitType != pCoexDm->curRetryLimitType)) + { + switch(pCoexDm->curRetryLimitType) + { + case 0: // normal mode + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x42a, pCoexDm->backupRetryLimit); + break; + case 1: // retry limit=8 + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x42a, 0x0808); + break; + default: + break; + } + } + + pCoexDm->preRetryLimitType = pCoexDm->curRetryLimitType; +} + +VOID +halbtc8192e2ant_AmpduMaxTime( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + pCoexDm->curAmpduTimeType = type; + + if( bForceExec || (pCoexDm->preAmpduTimeType != pCoexDm->curAmpduTimeType)) + { + switch(pCoexDm->curAmpduTimeType) + { + case 0: // normal mode + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x456, pCoexDm->backupAmpduMaxTime); + break; + case 1: // AMPDU timw = 0x38 * 32us + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x456, 0x38); + break; + default: + break; + } + } + + pCoexDm->preAmpduTimeType = pCoexDm->curAmpduTimeType; +} + +VOID +halbtc8192e2ant_LimitedTx( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte raMaskType, + IN u1Byte arfrType, + IN u1Byte retryLimitType, + IN u1Byte ampduTimeType + ) +{ + u4Byte disRaMask=0x0; + + pCoexDm->curRaMaskType = raMaskType; + disRaMask = halbtc8192e2ant_DecideRaMask(pBtCoexist, pCoexDm->curSsType, raMaskType); + halbtc8192e2ant_UpdateRaMask(pBtCoexist, bForceExec, disRaMask); + + halbtc8192e2ant_AutoRateFallbackRetry(pBtCoexist, bForceExec, arfrType); + halbtc8192e2ant_RetryLimit(pBtCoexist, bForceExec, retryLimitType); + halbtc8192e2ant_AmpduMaxTime(pBtCoexist, bForceExec, ampduTimeType); +} + +VOID +halbtc8192e2ant_LimitedRx( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bRejApAggPkt, + IN BOOLEAN bBtCtrlAggBufSize, + IN u1Byte aggBufSize + ) +{ + BOOLEAN bRejectRxAgg=bRejApAggPkt; + BOOLEAN bBtCtrlRxAggSize=bBtCtrlAggBufSize; + u1Byte rxAggSize=aggBufSize; + + //============================================ + // Rx Aggregation related setting + //============================================ + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, &bRejectRxAgg); + // decide BT control aggregation buf size or not + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, &bBtCtrlRxAggSize); + // aggregation buf size, only work when BT control Rx aggregation size. + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_AGG_BUF_SIZE, &rxAggSize); + // real update aggregation setting + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); + + +} + +VOID +halbtc8192e2ant_MonitorBtCtr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte regHPTxRx, regLPTxRx, u4Tmp; + u4Byte regHPTx=0, regHPRx=0, regLPTx=0, regLPRx=0; + u1Byte u1Tmp; + + regHPTxRx = 0x770; + regLPTxRx = 0x774; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regHPTxRx); + regHPTx = u4Tmp & bMaskLWord; + regHPRx = (u4Tmp & bMaskHWord)>>16; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regLPTxRx); + regLPTx = u4Tmp & bMaskLWord; + regLPRx = (u4Tmp & bMaskHWord)>>16; + + pCoexSta->highPriorityTx = regHPTx; + pCoexSta->highPriorityRx = regHPRx; + pCoexSta->lowPriorityTx = regLPTx; + pCoexSta->lowPriorityRx = regLPRx; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", + regHPTxRx, regHPTx, regHPTx, regHPRx, regHPRx)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", + regLPTxRx, regLPTx, regLPTx, regLPRx, regLPRx)); + + // reset counter + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0xc); +} + +VOID +halbtc8192e2ant_QueryBtInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + pCoexSta->bC2hBtInfoReqSent = TRUE; + + H2C_Parameter[0] |= BIT0; // trigger + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Query Bt Info, FW write 0x61=0x%x\n", + H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x61, 1, H2C_Parameter); +} + +BOOLEAN +halbtc8192e2ant_IsWifiStatusChanged( + IN PBTC_COEXIST pBtCoexist + ) +{ + static BOOLEAN bPreWifiBusy=FALSE, bPreUnder4way=FALSE, bPreBtHsOn=FALSE; + BOOLEAN bWifiBusy=FALSE, bUnder4way=FALSE, bBtHsOn=FALSE; + BOOLEAN bWifiConnected=FALSE; + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH; + + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &bUnder4way); + + if(bWifiConnected) + { + if(bWifiBusy != bPreWifiBusy) + { + bPreWifiBusy = bWifiBusy; + return TRUE; + } + if(bUnder4way != bPreUnder4way) + { + bPreUnder4way = bUnder4way; + return TRUE; + } + if(bBtHsOn != bPreBtHsOn) + { + bPreBtHsOn = bBtHsOn; + return TRUE; + } + + + wifiRssiState = halbtc8192e2ant_WifiRssiState(pBtCoexist,3, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + + if ( (BTC_RSSI_STATE_HIGH ==wifiRssiState ) || (BTC_RSSI_STATE_LOW ==wifiRssiState )) + { + return TRUE; + } + + } + + return FALSE; +} + +VOID +halbtc8192e2ant_UpdateBtLinkInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bBtHsOn=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + pBtLinkInfo->bBtLinkExist = pCoexSta->bBtLinkExist; + pBtLinkInfo->bScoExist = pCoexSta->bScoExist; + pBtLinkInfo->bA2dpExist = pCoexSta->bA2dpExist; + pBtLinkInfo->bPanExist = pCoexSta->bPanExist; + pBtLinkInfo->bHidExist = pCoexSta->bHidExist; + + // work around for HS mode. + if(bBtHsOn) + { + pBtLinkInfo->bPanExist = TRUE; + pBtLinkInfo->bBtLinkExist = TRUE; + } + + // check if Sco only + if( pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bScoOnly = TRUE; + else + pBtLinkInfo->bScoOnly = FALSE; + + // check if A2dp only + if( !pBtLinkInfo->bScoExist && + pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bA2dpOnly = TRUE; + else + pBtLinkInfo->bA2dpOnly = FALSE; + + // check if Pan only + if( !pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bPanOnly = TRUE; + else + pBtLinkInfo->bPanOnly = FALSE; + + // check if Hid only + if( !pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + pBtLinkInfo->bHidExist ) + pBtLinkInfo->bHidOnly = TRUE; + else + pBtLinkInfo->bHidOnly = FALSE; +} + +u1Byte +halbtc8192e2ant_ActionAlgorithm( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + BOOLEAN bBtHsOn=FALSE; + u1Byte algorithm=BT_8192E_2ANT_COEX_ALGO_UNDEFINED; + u1Byte numOfDiffProfile=0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + if(!pBtLinkInfo->bBtLinkExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], No BT link exists!!!\n")); + return algorithm; + } + + if(pBtLinkInfo->bScoExist) + numOfDiffProfile++; + if(pBtLinkInfo->bHidExist) + numOfDiffProfile++; + if(pBtLinkInfo->bPanExist) + numOfDiffProfile++; + if(pBtLinkInfo->bA2dpExist) + numOfDiffProfile++; + + + if(numOfDiffProfile == 1) + { + if(pBtLinkInfo->bScoExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO only\n")); + algorithm = BT_8192E_2ANT_COEX_ALGO_SCO; + } + else + { + if(pBtLinkInfo->bHidExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID only\n")); + algorithm = BT_8192E_2ANT_COEX_ALGO_HID; + } + else if(pBtLinkInfo->bA2dpExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP only\n")); + algorithm = BT_8192E_2ANT_COEX_ALGO_A2DP; + } + else if(pBtLinkInfo->bPanExist) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN(HS) only\n")); + algorithm = BT_8192E_2ANT_COEX_ALGO_PANHS; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN(EDR) only\n")); + algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR; + } + } + } + } + else if(numOfDiffProfile == 2) + { + if(pBtLinkInfo->bScoExist) + { + if(pBtLinkInfo->bHidExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID\n")); + algorithm = BT_8192E_2ANT_COEX_ALGO_SCO; + } + else if(pBtLinkInfo->bA2dpExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + A2DP ==> SCO\n")); + algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_HID; + } + else if(pBtLinkInfo->bPanExist) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + PAN(HS)\n")); + algorithm = BT_8192E_2ANT_COEX_ALGO_SCO; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + PAN(EDR)\n")); + algorithm = BT_8192E_2ANT_COEX_ALGO_SCO_PAN; + } + } + } + else + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bA2dpExist ) + { + if(pStackInfo->numOfHid >= 2) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID*2 + A2DP\n")); + algorithm = BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP\n")); + algorithm = BT_8192E_2ANT_COEX_ALGO_HID_A2DP; + } + } + else if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + PAN(HS)\n")); + algorithm = BT_8192E_2ANT_COEX_ALGO_HID; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + PAN(EDR)\n")); + algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_HID; + } + } + else if( pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP + PAN(HS)\n")); + algorithm = BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP + PAN(EDR)\n")); + algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } + } + else if(numOfDiffProfile == 3) + { + if(pBtLinkInfo->bScoExist) + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bA2dpExist ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + A2DP ==> HID\n")); + algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_HID; + } + else if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + PAN(HS)\n")); + algorithm = BT_8192E_2ANT_COEX_ALGO_SCO; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + PAN(EDR)\n")); + algorithm = BT_8192E_2ANT_COEX_ALGO_SCO_PAN; + } + } + else if( pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + A2DP + PAN(HS)\n")); + algorithm = BT_8192E_2ANT_COEX_ALGO_SCO; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n")); + algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_HID; + } + } + } + else + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP + PAN(HS)\n")); + algorithm = BT_8192E_2ANT_COEX_ALGO_HID_A2DP; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP + PAN(EDR)\n")); + algorithm = BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } + else if(numOfDiffProfile >= 3) + { + if(pBtLinkInfo->bScoExist) + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n")); + + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n")); + algorithm = BT_8192E_2ANT_COEX_ALGO_PANEDR_HID; + } + } + } + } + + return algorithm; +} + +VOID +halbtc8192e2ant_SetFwDacSwingLevel( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte dacSwingLvl + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + // There are several type of dacswing + // 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 + H2C_Parameter[0] = dacSwingLvl; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Set Dac Swing Level=0x%x\n", dacSwingLvl)); + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x64=0x%x\n", H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x64, 1, H2C_Parameter); +} + +VOID +halbtc8192e2ant_SetFwDecBtPwr( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte decBtPwrLvl + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + H2C_Parameter[0] = decBtPwrLvl; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], decrease Bt Power level = %d, FW write 0x62=0x%x\n", + decBtPwrLvl, H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x62, 1, H2C_Parameter); +} + +VOID +halbtc8192e2ant_DecBtPwr( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte decBtPwrLvl + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s Dec BT power level = %d\n", + (bForceExec? "force to":""), decBtPwrLvl)); + pCoexDm->curBtDecPwrLvl = decBtPwrLvl; + + if(!bForceExec) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], preBtDecPwrLvl=%d, curBtDecPwrLvl=%d\n", + pCoexDm->preBtDecPwrLvl, pCoexDm->curBtDecPwrLvl)); +#if 0 // work around, avoid h2c command fail. + if(pCoexDm->preBtDecPwrLvl == pCoexDm->curBtDecPwrLvl) + return; +#endif + } + halbtc8192e2ant_SetFwDecBtPwr(pBtCoexist, pCoexDm->curBtDecPwrLvl); + + pCoexDm->preBtDecPwrLvl = pCoexDm->curBtDecPwrLvl; +} + +VOID +halbtc8192e2ant_SetBtAutoReport( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bEnableAutoReport + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + H2C_Parameter[0] = 0; + + if(bEnableAutoReport) + { + H2C_Parameter[0] |= BIT0; + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], BT FW auto report : %s, FW write 0x68=0x%x\n", + (bEnableAutoReport? "Enabled!!":"Disabled!!"), H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x68, 1, H2C_Parameter); +} + +VOID +halbtc8192e2ant_BtAutoReport( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bEnableAutoReport + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s BT Auto report = %s\n", + (bForceExec? "force to":""), ((bEnableAutoReport)? "Enabled":"Disabled"))); + pCoexDm->bCurBtAutoReport = bEnableAutoReport; + + if(!bForceExec) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], bPreBtAutoReport=%d, bCurBtAutoReport=%d\n", + pCoexDm->bPreBtAutoReport, pCoexDm->bCurBtAutoReport)); + + if(pCoexDm->bPreBtAutoReport == pCoexDm->bCurBtAutoReport) + return; + } + halbtc8192e2ant_SetBtAutoReport(pBtCoexist, pCoexDm->bCurBtAutoReport); + + pCoexDm->bPreBtAutoReport = pCoexDm->bCurBtAutoReport; +} + +VOID +halbtc8192e2ant_FwDacSwingLvl( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte fwDacSwingLvl + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s set FW Dac Swing level = %d\n", + (bForceExec? "force to":""), fwDacSwingLvl)); + pCoexDm->curFwDacSwingLvl = fwDacSwingLvl; + + if(!bForceExec) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], preFwDacSwingLvl=%d, curFwDacSwingLvl=%d\n", + pCoexDm->preFwDacSwingLvl, pCoexDm->curFwDacSwingLvl)); + + if(pCoexDm->preFwDacSwingLvl == pCoexDm->curFwDacSwingLvl) + return; + } + + halbtc8192e2ant_SetFwDacSwingLevel(pBtCoexist, pCoexDm->curFwDacSwingLvl); + + pCoexDm->preFwDacSwingLvl = pCoexDm->curFwDacSwingLvl; +} + +VOID +halbtc8192e2ant_SetSwRfRxLpfCorner( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bRxRfShrinkOn + ) +{ + if(bRxRfShrinkOn) + { + //Shrink RF Rx LPF corner + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Shrink RF Rx LPF corner!!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, 0xffffc); + } + else + { + //Resume RF Rx LPF corner + // After initialized, we can use pCoexDm->btRf0x1eBackup + if(pBtCoexist->bInitilized) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Resume RF Rx LPF corner!!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, pCoexDm->btRf0x1eBackup); + } + } +} + +VOID +halbtc8192e2ant_RfShrink( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bRxRfShrinkOn + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Rx RF Shrink = %s\n", + (bForceExec? "force to":""), ((bRxRfShrinkOn)? "ON":"OFF"))); + pCoexDm->bCurRfRxLpfShrink = bRxRfShrinkOn; + + if(!bForceExec) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], bPreRfRxLpfShrink=%d, bCurRfRxLpfShrink=%d\n", + pCoexDm->bPreRfRxLpfShrink, pCoexDm->bCurRfRxLpfShrink)); + + if(pCoexDm->bPreRfRxLpfShrink == pCoexDm->bCurRfRxLpfShrink) + return; + } + halbtc8192e2ant_SetSwRfRxLpfCorner(pBtCoexist, pCoexDm->bCurRfRxLpfShrink); + + pCoexDm->bPreRfRxLpfShrink = pCoexDm->bCurRfRxLpfShrink; +} + +VOID +halbtc8192e2ant_SetSwPenaltyTxRateAdaptive( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bLowPenaltyRa + ) +{ + u1Byte H2C_Parameter[6] ={0}; + + H2C_Parameter[0] = 0x6; // opCode, 0x6= Retry_Penalty + + if(bLowPenaltyRa) + { + H2C_Parameter[1] |= BIT0; + H2C_Parameter[2] = 0x00; //normal rate except MCS7/6/5, OFDM54/48/36 + H2C_Parameter[3] = 0xf7; //MCS7 or OFDM54 + H2C_Parameter[4] = 0xf8; //MCS6 or OFDM48 + H2C_Parameter[5] = 0xf9; //MCS5 or OFDM36 + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set WiFi Low-Penalty Retry: %s", + (bLowPenaltyRa? "ON!!":"OFF!!")) ); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x69, 6, H2C_Parameter); +} + +VOID +halbtc8192e2ant_LowPenaltyRa( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bLowPenaltyRa + ) +{ + //return; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn LowPenaltyRA = %s\n", + (bForceExec? "force to":""), ((bLowPenaltyRa)? "ON":"OFF"))); + pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa; + + if(!bForceExec) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], bPreLowPenaltyRa=%d, bCurLowPenaltyRa=%d\n", + pCoexDm->bPreLowPenaltyRa, pCoexDm->bCurLowPenaltyRa)); + + if(pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa) + return; + } + halbtc8192e2ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa); + + pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa; +} + +VOID +halbtc8192e2ant_SetDacSwingReg( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte level + ) +{ + u1Byte val=(u1Byte)level; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Write SwDacSwing = 0x%x\n", level)); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x883, 0x3e, val); +} + +VOID +halbtc8192e2ant_SetSwFullTimeDacSwing( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bSwDacSwingOn, + IN u4Byte swDacSwingLvl + ) +{ + if(bSwDacSwingOn) + { + halbtc8192e2ant_SetDacSwingReg(pBtCoexist, swDacSwingLvl); + } + else + { + halbtc8192e2ant_SetDacSwingReg(pBtCoexist, 0x18); + } +} + + +VOID +halbtc8192e2ant_DacSwing( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bDacSwingOn, + IN u4Byte dacSwingLvl + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn DacSwing=%s, dacSwingLvl=0x%x\n", + (bForceExec? "force to":""), ((bDacSwingOn)? "ON":"OFF"), dacSwingLvl)); + pCoexDm->bCurDacSwingOn = bDacSwingOn; + pCoexDm->curDacSwingLvl = dacSwingLvl; + + if(!bForceExec) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], bPreDacSwingOn=%d, preDacSwingLvl=0x%x, bCurDacSwingOn=%d, curDacSwingLvl=0x%x\n", + pCoexDm->bPreDacSwingOn, pCoexDm->preDacSwingLvl, + pCoexDm->bCurDacSwingOn, pCoexDm->curDacSwingLvl)); + + if( (pCoexDm->bPreDacSwingOn == pCoexDm->bCurDacSwingOn) && + (pCoexDm->preDacSwingLvl == pCoexDm->curDacSwingLvl) ) + return; + } + delay_ms(30); + halbtc8192e2ant_SetSwFullTimeDacSwing(pBtCoexist, bDacSwingOn, dacSwingLvl); + + pCoexDm->bPreDacSwingOn = pCoexDm->bCurDacSwingOn; + pCoexDm->preDacSwingLvl = pCoexDm->curDacSwingLvl; +} + +VOID +halbtc8192e2ant_SetAdcBackOff( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bAdcBackOff + ) +{ + if(bAdcBackOff) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level On!\n")); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xc05, 0x30, 0x3); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level Off!\n")); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xc05, 0x30, 0x1); + } +} + +VOID +halbtc8192e2ant_AdcBackOff( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bAdcBackOff + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn AdcBackOff = %s\n", + (bForceExec? "force to":""), ((bAdcBackOff)? "ON":"OFF"))); + pCoexDm->bCurAdcBackOff = bAdcBackOff; + + if(!bForceExec) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], bPreAdcBackOff=%d, bCurAdcBackOff=%d\n", + pCoexDm->bPreAdcBackOff, pCoexDm->bCurAdcBackOff)); + + if(pCoexDm->bPreAdcBackOff == pCoexDm->bCurAdcBackOff) + return; + } + halbtc8192e2ant_SetAdcBackOff(pBtCoexist, pCoexDm->bCurAdcBackOff); + + pCoexDm->bPreAdcBackOff = pCoexDm->bCurAdcBackOff; +} + +VOID +halbtc8192e2ant_SetAgcTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bAgcTableEn + ) +{ + u1Byte rssiAdjustVal=0; + + //=================BB AGC Gain Table + if(bAgcTableEn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB Agc Table On!\n")); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x0a1A0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x091B0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x081C0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x071D0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x061E0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x051F0001); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB Agc Table Off!\n")); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xaa1A0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa91B0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa81C0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa71D0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa61E0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa51F0001); + } + +#if 0 + //=================RF Gain + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000); + if(bAgcTableEn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table On!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x38fff); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x38ffe); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table Off!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x380c3); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x28ce6); + } + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xef, 0xfffff, 0x0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xed, 0xfffff, 0x1); + if(bAgcTableEn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table On!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x40, 0xfffff, 0x38fff); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x40, 0xfffff, 0x38ffe); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table Off!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x40, 0xfffff, 0x380c3); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x40, 0xfffff, 0x28ce6); + } + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xed, 0xfffff, 0x0); + + // set rssiAdjustVal for wifi module. + if(bAgcTableEn) + { + rssiAdjustVal = 8; + } + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, &rssiAdjustVal); +#endif + +} + +VOID +halbtc8192e2ant_AgcTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bAgcTableEn + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s %s Agc Table\n", + (bForceExec? "force to":""), ((bAgcTableEn)? "Enable":"Disable"))); + pCoexDm->bCurAgcTableEn = bAgcTableEn; + + if(!bForceExec) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], bPreAgcTableEn=%d, bCurAgcTableEn=%d\n", + pCoexDm->bPreAgcTableEn, pCoexDm->bCurAgcTableEn)); + + if(pCoexDm->bPreAgcTableEn == pCoexDm->bCurAgcTableEn) + return; + } + halbtc8192e2ant_SetAgcTable(pBtCoexist, bAgcTableEn); + + pCoexDm->bPreAgcTableEn = pCoexDm->bCurAgcTableEn; +} + +VOID +halbtc8192e2ant_SetCoexTable( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte val0x6c0, + IN u4Byte val0x6c4, + IN u4Byte val0x6c8, + IN u1Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c0=0x%x\n", val0x6c0)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c0, val0x6c0); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c4=0x%x\n", val0x6c4)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c4, val0x6c4); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, val0x6c8); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc)); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cc, val0x6cc); +} + +VOID +halbtc8192e2ant_CoexTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u4Byte val0x6c0, + IN u4Byte val0x6c4, + IN u4Byte val0x6c8, + IN u1Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s write Coex Table 0x6c0=0x%x, 0x6c4=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n", + (bForceExec? "force to":""), val0x6c0, val0x6c4, val0x6c8, val0x6cc)); + pCoexDm->curVal0x6c0 = val0x6c0; + pCoexDm->curVal0x6c4 = val0x6c4; + pCoexDm->curVal0x6c8 = val0x6c8; + pCoexDm->curVal0x6cc = val0x6cc; + + if(!bForceExec) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], preVal0x6c0=0x%x, preVal0x6c4=0x%x, preVal0x6c8=0x%x, preVal0x6cc=0x%x !!\n", + pCoexDm->preVal0x6c0, pCoexDm->preVal0x6c4, pCoexDm->preVal0x6c8, pCoexDm->preVal0x6cc)); + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], curVal0x6c0=0x%x, curVal0x6c4=0x%x, curVal0x6c8=0x%x, curVal0x6cc=0x%x !!\n", + pCoexDm->curVal0x6c0, pCoexDm->curVal0x6c4, pCoexDm->curVal0x6c8, pCoexDm->curVal0x6cc)); + + if( (pCoexDm->preVal0x6c0 == pCoexDm->curVal0x6c0) && + (pCoexDm->preVal0x6c4 == pCoexDm->curVal0x6c4) && + (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) && + (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) ) + return; + } + halbtc8192e2ant_SetCoexTable(pBtCoexist, val0x6c0, val0x6c4, val0x6c8, val0x6cc); + + pCoexDm->preVal0x6c0 = pCoexDm->curVal0x6c0; + pCoexDm->preVal0x6c4 = pCoexDm->curVal0x6c4; + pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8; + pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc; +} + +VOID +halbtc8192e2ant_CoexTableWithType( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + pCoexSta->nCoexTableType = type; + + switch(type) + { + case 0: + halbtc8192e2ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 1: + halbtc8192e2ant_CoexTable(pBtCoexist, bForceExec, 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 2: + halbtc8192e2ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x5ffb5ffb, 0xffffff, 0x3); + break; + case 3: + halbtc8192e2ant_CoexTable(pBtCoexist, bForceExec, 0x5fdf5fdf, 0x5fdb5fdb, 0xffffff, 0x3); + break; + case 4: + halbtc8192e2ant_CoexTable(pBtCoexist, bForceExec, 0xdfffdfff, 0x5ffb5ffb, 0xffffff, 0x3); + break; + case 5: + halbtc8192e2ant_CoexTable(pBtCoexist, bForceExec, 0x5ddd5ddd, 0x5fdb5fdb, 0xffffff, 0x3); + break; + case 6: + halbtc8192e2ant_CoexTable(pBtCoexist, bForceExec, 0x5fff5fff, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 7: + if(pCoexSta->nScanAPNum <= NOISY_AP_NUM_THRESH) + halbtc8192e2ant_CoexTable(pBtCoexist, bForceExec, 0xffffffff, 0xfafafafa, 0xffffff, 0x3); + else + halbtc8192e2ant_CoexTable(pBtCoexist, bForceExec, 0xffffffff, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 8: + halbtc8192e2ant_CoexTable(pBtCoexist, bForceExec, 0x5f5f5f5f, 0x5a5a5a5a, 0xffffff, 0x3); + break; + default: + break; + } +} + +VOID +halbtc8192e2ant_SetFwIgnoreWlanAct( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bEnable + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + if(bEnable) + { + H2C_Parameter[0] |= BIT0; // function enable + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set FW for BT Ignore Wlan_Act, FW write 0x63=0x%x\n", + H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x63, 1, H2C_Parameter); +} + + +VOID +halbtc8192e2ant_IgnoreWlanAct( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bEnable + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Ignore WlanAct %s\n", + (bForceExec? "force to":""), (bEnable? "ON":"OFF"))); + pCoexDm->bCurIgnoreWlanAct = bEnable; + + if(!bForceExec) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], bPreIgnoreWlanAct = %d, bCurIgnoreWlanAct = %d!!\n", + pCoexDm->bPreIgnoreWlanAct, pCoexDm->bCurIgnoreWlanAct)); + + if(pCoexDm->bPreIgnoreWlanAct == pCoexDm->bCurIgnoreWlanAct) + return; + } + halbtc8192e2ant_SetFwIgnoreWlanAct(pBtCoexist, bEnable); + + pCoexDm->bPreIgnoreWlanAct = pCoexDm->bCurIgnoreWlanAct; +} + + +VOID +halbtc8192e2ant_SetLpsRpwm( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + u1Byte lps=lpsVal; + u1Byte rpwm=rpwmVal; + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_LPS_VAL, &lps); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RPWM_VAL, &rpwm); +} + + +VOID +halbtc8192e2ant_LpsRpwm( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + BOOLEAN bForceExecPwrCmd=FALSE; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s set lps/rpwm=0x%x/0x%x \n", + (bForceExec? "force to":""), lpsVal, rpwmVal)); + pCoexDm->curLps = lpsVal; + pCoexDm->curRpwm = rpwmVal; + + if(!bForceExec) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], preLps/curLps=0x%x/0x%x, preRpwm/curRpwm=0x%x/0x%x!!\n", + pCoexDm->preLps, pCoexDm->curLps, pCoexDm->preRpwm, pCoexDm->curRpwm)); + + if( (pCoexDm->preLps == pCoexDm->curLps) && + (pCoexDm->preRpwm == pCoexDm->curRpwm) ) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], LPS-RPWM_Last=0x%x , LPS-RPWM_Now=0x%x!!\n", + pCoexDm->preRpwm, pCoexDm->curRpwm)); + + return; + } + } + halbtc8192e2ant_SetLpsRpwm(pBtCoexist, lpsVal, rpwmVal); + + pCoexDm->preLps = pCoexDm->curLps; + pCoexDm->preRpwm = pCoexDm->curRpwm; +} + + + +VOID +halbtc8192e2ant_SetFwPstdma( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte byte1, + IN u1Byte byte2, + IN u1Byte byte3, + IN u1Byte byte4, + IN u1Byte byte5 + ) +{ + u1Byte H2C_Parameter[5] ={0}; + u1Byte realByte1=byte1, realByte5=byte5; + BOOLEAN bApEnable=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + + if(bApEnable) + { + if(byte1&BIT4 && !(byte1&BIT5)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], FW for 1Ant AP mode\n")); + realByte1 &= ~BIT4; + realByte1 |= BIT5; + + realByte5 |= BIT5; + realByte5 &= ~BIT6; + } + } + + H2C_Parameter[0] = realByte1; + H2C_Parameter[1] = byte2; + H2C_Parameter[2] = byte3; + H2C_Parameter[3] = byte4; + H2C_Parameter[4] = realByte5; + + pCoexDm->psTdmaPara[0] = realByte1; + pCoexDm->psTdmaPara[1] = byte2; + pCoexDm->psTdmaPara[2] = byte3; + pCoexDm->psTdmaPara[3] = byte4; + pCoexDm->psTdmaPara[4] = realByte5; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], PS-TDMA H2C cmd =0x%x%08x\n", + H2C_Parameter[0], + H2C_Parameter[1]<<24|H2C_Parameter[2]<<16|H2C_Parameter[3]<<8|H2C_Parameter[4])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x60, 5, H2C_Parameter); +} + + +VOID +halbtc8192e2ant_SwMechanism1( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bShrinkRxLPF, + IN BOOLEAN bLowPenaltyRA, + IN BOOLEAN bLimitedDIG, + IN BOOLEAN bBTLNAConstrain + ) +{ + /* + u4Byte wifiBw; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if(BTC_WIFI_BW_HT40 != wifiBw) //only shrink RF Rx LPF for HT40 + { + if (bShrinkRxLPF) + bShrinkRxLPF = FALSE; + } + */ + + halbtc8192e2ant_RfShrink(pBtCoexist, NORMAL_EXEC, bShrinkRxLPF); + //halbtc8192e2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, bLowPenaltyRA); +} + +VOID +halbtc8192e2ant_SwMechanism2( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bAGCTableShift, + IN BOOLEAN bADCBackOff, + IN BOOLEAN bSWDACSwing, + IN u4Byte dacSwingLvl + ) +{ + halbtc8192e2ant_AgcTable(pBtCoexist, NORMAL_EXEC, bAGCTableShift); + //halbtc8192e2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, bADCBackOff); + halbtc8192e2ant_DacSwing(pBtCoexist, NORMAL_EXEC, bSWDACSwing, dacSwingLvl); +} + +VOID +halbtc8192e2ant_SetAntPath( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte antPosType, + IN BOOLEAN bInitHwCfg, + IN BOOLEAN bWifiOff + ) +{ + u4Byte u4Tmp=0; + + if(bInitHwCfg) + { + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x944, 0x24); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x930, 0x700700); + if(pBtCoexist->chipInterface == BTC_INTF_USB) + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x64, 0x30430004); + else + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x64, 0x30030004); + + // 0x4c[27][24]='00', Set Antenna to BB + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x4c); + u4Tmp &= ~BIT24; + u4Tmp &= ~BIT27; + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x4c, u4Tmp); + } + else if(bWifiOff) + { + if(pBtCoexist->chipInterface == BTC_INTF_USB) + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x64, 0x30430004); + else + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x64, 0x30030004); + + // 0x4c[27][24]='11', Set Antenna to BT, 0x64[8:7]=0, 0x64[2]=1 + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x4c); + u4Tmp |= BIT24; + u4Tmp |= BIT27; + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x4c, u4Tmp); + } + + // ext switch setting + switch(antPosType) + { + case BTC_ANT_PATH_WIFI: + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x92c, 0x4); + break; + case BTC_ANT_PATH_BT: + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x92c, 0x20); + break; + default: + case BTC_ANT_PATH_PTA: + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x92c, 0x4); + break; + } +} + +VOID +halbtc8192e2ant_PsTdma( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bTurnOn, + IN u1Byte type + ) +{ + BOOLEAN bTurnOnByCnt=FALSE; + u1Byte psTdmaTypeByCnt=0; + s1Byte nWiFiDurationAdjust = 0x0; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn %s PS TDMA, type=%d\n", + (bForceExec? "force to":""), (bTurnOn? "ON":"OFF"), type)); + pCoexDm->bCurPsTdmaOn = bTurnOn; + pCoexDm->curPsTdma = type; + + if(!bForceExec) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], bPrePsTdmaOn = %d, bCurPsTdmaOn = %d!!\n", + pCoexDm->bPrePsTdmaOn, pCoexDm->bCurPsTdmaOn)); + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], prePsTdma = %d, curPsTdma = %d!!\n", + pCoexDm->prePsTdma, pCoexDm->curPsTdma)); + + if( (pCoexDm->bPrePsTdmaOn == pCoexDm->bCurPsTdmaOn) && + (pCoexDm->prePsTdma == pCoexDm->curPsTdma) ) + return; + } + + if (pCoexSta->nScanAPNum >= 40) + nWiFiDurationAdjust = -15; + else if (pCoexSta->nScanAPNum >= 20) + nWiFiDurationAdjust = -10; + +/* + if (!pCoexSta->bForceLpsOn) //only for A2DP-only case 1/2/9/11 while wifi noisy threshold > 30 + { + psTdmaByte0Val = 0x61; //no null-pkt + psTdmaByte3Val = 0x11; // no tx-pause at BT-slot + psTdmaByte4Val = 0x10; // 0x778 = d/1 toggle + } + + + if ( (type == 3) || (type == 13) || (type == 14) ) + { + psTdmaByte4Val = psTdmaByte4Val & 0xbf; //no dynamic slot for multi-profile + + if (!bWifiBusy) + psTdmaByte4Val = psTdmaByte4Val | 0x1; //0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) + } + + if (pBtLinkInfo->bSlaveRole == TRUE) + psTdmaByte4Val = psTdmaByte4Val | 0x1; //0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) + +*/ + if(bTurnOn) + { + switch(type) + { + case 1: + default: //d1,wb + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x3c, 0x03, 0x11, 0x10); + break; + case 2: + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x32, 0x03, 0x11, 0x10); + break; + case 3: + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x28, 0x03, 0x11, 0x10); + break; + case 4: + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1e, 0x03, 0x11, 0x10); + break; + case 5: //d1,pb,TXpause + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0x63, 0x3c, 0x03, 0x90, 0x10); + break; + case 6: + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0x63, 0x32, 0x03, 0x90, 0x10); + break; + case 7: + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0x63, 0x28, 0x03, 0x90, 0x10); + break; + case 8: + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0x63, 0x1e, 0x03, 0x90, 0x10); + break; + case 9: //d1,bb + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x3c, 0x03, 0x31, 0x10); + break; + case 10: + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x32, 0x03, 0x31, 0x10); + break; + case 11: + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x28, 0x03, 0x31, 0x10); + break; + case 12: + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1e, 0x03, 0x31, 0x10); + break; + case 13: //d1,bb,TXpause + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x3c, 0x03, 0x30, 0x10); + break; + case 14: + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x32, 0x03, 0x30, 0x10); + break; + case 15: + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x28, 0x03, 0x30, 0x10); + break; + case 16: + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1e, 0x03, 0x30, 0x10); + break; + case 17: + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0x61, 0x20, 0x03, 0x10, 0x10); + break; + case 18: + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0xe1, 0x90); + break; + case 19: + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x25, 0xe1, 0x90); + break; + case 20: + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x25, 0x60, 0x90); + break; + case 21: + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0x61, 0x35, 0x03, 0x11, 0x11); + break; + case 71: + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); + break; + + // following cases is for wifi rssi low // bad antenna isolation, started from 81 + case 80: + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0x53, 0x3c, 0x3, 0x90, 0x50); + break; + case 81: + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0x53, 0x3a+nWiFiDurationAdjust, 0x3, 0x90, 0x50); + break; + case 82: + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0x53, 0x30+nWiFiDurationAdjust, 0x03, 0x90, 0x50); + break; + case 83: + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0x53, 0x21, 0x03, 0x90, 0x50); + break; + case 84: + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0x53, 0x15, 0x3, 0x90, 0x50); + break; + case 85: + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0x53, 0x3a, 0x03, 0x90, 0x50); + break; + case 86: + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0x53, 0x21, 0x03, 0x90, 0x50); + break; + + } + } + else + { + // disable PS tdma + switch(type) + { + default: + case 0: //ANT2PTA, 0x778=1 + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0x8, 0x0, 0x0, 0x0, 0x0); + halbtc8192e2ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, FALSE, FALSE); + break; + case 1: //ANT2BT, 0x778=3 + halbtc8192e2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x8, 0x0); + delay_ms(5); + halbtc8192e2ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FALSE, FALSE); + break; + + } + } + + // update pre state + pCoexDm->bPrePsTdmaOn = pCoexDm->bCurPsTdmaOn; + pCoexDm->prePsTdma = pCoexDm->curPsTdma; +} + +VOID +halbtc8192e2ant_SetSwitchSsType( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte ssType + ) +{ + u1Byte mimoPs=BTC_MIMO_PS_DYNAMIC; + u4Byte disRaMask=0x0; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], REAL set SS Type = %d\n", ssType)); + + disRaMask = halbtc8192e2ant_DecideRaMask(pBtCoexist, ssType, pCoexDm->curRaMaskType); + halbtc8192e2ant_UpdateRaMask(pBtCoexist, FORCE_EXEC, disRaMask); + + if(ssType == 1) + { + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); + // switch ofdm path + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0xc04, 0x11); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0xd04, 0x1); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x90c, 0x81111111); + // switch cck patch + //pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xe77, 0x4, 0x1); + //pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0xa07, 0x81); + mimoPs=BTC_MIMO_PS_STATIC; + } + else if(ssType == 2) + { + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0xc04, 0x33); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0xd04, 0x3); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x90c, 0x81121313); + // remove, if 0xe77[2]=0x0 then CCK will fail, advised by Jenyu + //pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xe77, 0x4, 0x0); + //pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0xa07, 0x41); + mimoPs=BTC_MIMO_PS_DYNAMIC; + } + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_SEND_MIMO_PS, &mimoPs); // set rx 1ss or 2ss +} + +VOID +halbtc8192e2ant_SwitchSsType( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte newSsType + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], %s Switch SS Type = %d\n", + (bForceExec? "force to":""), newSsType)); + pCoexDm->curSsType = newSsType; + + if(!bForceExec) + { + if(pCoexDm->preSsType == pCoexDm->curSsType) + return; + } + halbtc8192e2ant_SetSwitchSsType(pBtCoexist, pCoexDm->curSsType); + + pCoexDm->preSsType = pCoexDm->curSsType; +} + +VOID +halbtc8192e2ant_PsTdmaCheckForPowerSaveState( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bNewPsState + ) +{ + u1Byte lpsMode=0x0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_LPS_MODE, &lpsMode); + + if(lpsMode) // already under LPS state + { + if(bNewPsState) + { + // keep state under LPS, do nothing. + } + else + { + // will leave LPS state, turn off psTdma first + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + } + } + else // NO PS state + { + if(bNewPsState) + { + // will enter LPS state, turn off psTdma first + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + } + else + { + // keep state under NO PS state, do nothing. + } + } +} + +VOID +halbtc8192e2ant_PowerSaveState( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte psType, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + BOOLEAN bLowPwrDisable=FALSE; + BOOLEAN bApEnable=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + + if(bApEnable) + { + psType = BTC_PS_WIFI_NATIVE; + lpsVal = 0x0; + rpwmVal = 0x0; + } + + switch(psType) + { + case BTC_PS_WIFI_NATIVE: + // recover to original 32k low power setting + bLowPwrDisable = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_NORMAL_LPS, NULL); + pCoexSta->bForceLpsOn = FALSE; + break; + case BTC_PS_LPS_ON: + halbtc8192e2ant_PsTdmaCheckForPowerSaveState(pBtCoexist, TRUE); + halbtc8192e2ant_LpsRpwm(pBtCoexist, NORMAL_EXEC, lpsVal, rpwmVal); + // when coex force to enter LPS, do not enter 32k low power. + bLowPwrDisable = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + // power save must executed before psTdma. + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_ENTER_LPS, NULL); + pCoexSta->bForceLpsOn = TRUE; + break; + case BTC_PS_LPS_OFF: + halbtc8192e2ant_PsTdmaCheckForPowerSaveState(pBtCoexist, FALSE); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_LEAVE_LPS, NULL); + pCoexSta->bForceLpsOn = FALSE; + break; + default: + break; + } +} + + +VOID +halbtc8192e2ant_CoexAllOff( + IN PBTC_COEXIST pBtCoexist + ) +{ + // fw all off + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + halbtc8192e2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + // sw all off + halbtc8192e2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + // hw all off + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); +} + +VOID +halbtc8192e2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + // force to reset coex mechanism + + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); + halbtc8192e2ant_FwDacSwingLvl(pBtCoexist, FORCE_EXEC, 6); + halbtc8192e2ant_DecBtPwr(pBtCoexist, FORCE_EXEC, 0); + + halbtc8192e2ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 0); + halbtc8192e2ant_SwitchSsType(pBtCoexist, FORCE_EXEC, 2); + + halbtc8192e2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); +} + +VOID +halbtc8192e2ant_ActionBtInquiry( + IN PBTC_COEXIST pBtCoexist + ) +{ +// BOOLEAN bLowPwrDisable=TRUE; + +// pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + +// halbtc8192e2ant_SwitchSsType(pBtCoexist, NORMAL_EXEC, 1); + + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 21); + halbtc8192e2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8192e2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); +} + +VOID +halbtc8192e2ant_ActionWiFiLinkProcess( + IN PBTC_COEXIST pBtCoexist + ) +{ + +} + +BOOLEAN +halbtc8192e2ant_IsCommonAction( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bCommon=FALSE, bWifiConnected=FALSE, bWifiBusy=FALSE; + BOOLEAN bBtHsOn=FALSE, bLowPwrDisable=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + + if(pBtLinkInfo->bScoExist || pBtLinkInfo->bHidExist) + { + halbtc8192e2ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 1, 0, 0, 0); + } + else + { + halbtc8192e2ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + } + + if(!bWifiConnected) + { +// bLowPwrDisable = FALSE; +// pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non-connected idle!!\n")); + + if( (BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus) || + (BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) ) + { +// halbtc8192e2ant_SwitchSsType(pBtCoexist, NORMAL_EXEC, 2); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 1); + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + } + else + { +// halbtc8192e2ant_SwitchSsType(pBtCoexist, NORMAL_EXEC, 1); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + } + + halbtc8192e2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8192e2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + bCommon = TRUE; + } + else + { + if(BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus) + { +// bLowPwrDisable = FALSE; +// pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi connected + BT non connected-idle!!\n")); + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); +// halbtc8192e2ant_SwitchSsType(pBtCoexist, NORMAL_EXEC, 2); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + halbtc8192e2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8192e2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + bCommon = TRUE; + } + else if(BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) + { +// bLowPwrDisable = TRUE; +// pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + + if(bBtHsOn) + return FALSE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi connected + BT connected-idle!!\n")); + + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); +// halbtc8192e2ant_SwitchSsType(pBtCoexist, NORMAL_EXEC, 2); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + halbtc8192e2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8192e2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + bCommon = TRUE; + } + else + { +// bLowPwrDisable = TRUE; +// pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + + if(bWifiBusy) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi Connected-Busy + BT Busy!!\n")); + bCommon = FALSE; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi Connected-Idle + BT Busy!!\n")); + + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); +// halbtc8192e2ant_SwitchSsType(pBtCoexist, NORMAL_EXEC, 1); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 21); + halbtc8192e2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + halbtc8192e2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + bCommon = TRUE; + } + } + } + + return bCommon; +} + + +VOID +halbtc8192e2ant_TdmaDurationAdjust( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bScoHid, + IN BOOLEAN bTxPause, + IN u1Byte maxInterval + ) +{ + static s4Byte up,dn,m,n,WaitCount; + s4Byte result; //0: no change, +1: increase WiFi duration, -1: decrease WiFi duration + u1Byte retryCount=0; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TdmaDurationAdjust()\n")); + + if(!pCoexDm->bAutoTdmaAdjust) + { + pCoexDm->bAutoTdmaAdjust = TRUE; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], first run TdmaDurationAdjust()!!\n")); + { + if(bScoHid) + { + if(bTxPause) + { + if(maxInterval == 1) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + pCoexDm->psTdmaDuAdjType = 13; + } + else if(maxInterval == 2) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(maxInterval == 3) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + } + else + { + if(maxInterval == 1) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(maxInterval == 2) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(maxInterval == 3) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + } + } + else + { + if(bTxPause) + { + if(maxInterval == 1) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + pCoexDm->psTdmaDuAdjType = 5; + } + else if(maxInterval == 2) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(maxInterval == 3) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + } + else + { + if(maxInterval == 1) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + else if(maxInterval == 2) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(maxInterval == 3) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + } + } + } + //============ + up = 0; + dn = 0; + m = 1; + n= 3; + result = 0; + WaitCount = 0; + } + else + { + //accquire the BT TRx retry count from BT_Info byte2 + retryCount = pCoexSta->btRetryCnt; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], retryCount = %d\n", retryCount)); + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], up=%d, dn=%d, m=%d, n=%d, WaitCount=%d\n", + up, dn, m, n, WaitCount)); + result = 0; + WaitCount++; + + if(retryCount == 0) // no retry in the last 2-second duration + { + up++; + dn--; + + if (dn <= 0) + dn = 0; + + if(up >= n) // if s n 2 retry count0, hռeWiFi duration + { + WaitCount = 0; + n = 3; + up = 0; + dn = 0; + result = 1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Increase wifi duration!!\n")); + } + } + else if (retryCount <= 3) // <=3 retry in the last 2-second duration + { + up--; + dn++; + + if (up <= 0) + up = 0; + + if (dn == 2) // if s 2 2 retry count< 3, hկWiFi duration + { + if (WaitCount <= 2) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter<3!!\n")); + } + } + else //retry count > 3, un1 retry count > 3, hկWiFi duration + { + if (WaitCount == 1) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter>3!!\n")); + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], max Interval = %d\n", maxInterval)); + if(maxInterval == 1) + { + if(bTxPause) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 1\n")); + + if(pCoexDm->curPsTdma == 1) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + pCoexDm->psTdmaDuAdjType = 5; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 4) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + if(pCoexDm->curPsTdma == 9) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + pCoexDm->psTdmaDuAdjType = 13; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + + if(result == -1) + { + if(pCoexDm->curPsTdma == 5) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + else if(pCoexDm->curPsTdma == 13) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 8) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + pCoexDm->psTdmaDuAdjType = 5; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + pCoexDm->psTdmaDuAdjType = 13; + } + } + } + else + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 0\n")); + if(pCoexDm->curPsTdma == 5) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 8) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + if(pCoexDm->curPsTdma == 13) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + + if(result == -1) + { + if(pCoexDm->curPsTdma == 1) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 4) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + } + } + } + else if(maxInterval == 2) + { + if(bTxPause) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 1\n")); + if(pCoexDm->curPsTdma == 1) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 4) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + if(pCoexDm->curPsTdma == 9) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 5) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + else if(pCoexDm->curPsTdma == 13) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 8) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + } + } + else + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 0\n")); + if(pCoexDm->curPsTdma == 5) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 8) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + if(pCoexDm->curPsTdma == 13) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 1) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 4) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + } + } + } + else if(maxInterval == 3) + { + if(bTxPause) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 1\n")); + if(pCoexDm->curPsTdma == 1) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 4) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + if(pCoexDm->curPsTdma == 9) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 5) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + else if(pCoexDm->curPsTdma == 13) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 8) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + } + } + else + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 0\n")); + if(pCoexDm->curPsTdma == 5) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 8) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + if(pCoexDm->curPsTdma == 13) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 1) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 4) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + } + } + } + } + + // if current PsTdma not match with the recorded one (when scan, dhcp...), + // then we have to adjust it back to the previous record one. + if(pCoexDm->curPsTdma != pCoexDm->psTdmaDuAdjType) + { + BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PsTdma type dismatch!!!, curPsTdma=%d, recordPsTdma=%d\n", + pCoexDm->curPsTdma, pCoexDm->psTdmaDuAdjType)); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + + if( !bScan && !bLink && !bRoam) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, pCoexDm->psTdmaDuAdjType); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n")); + } + } +} + +VOID +halbtc8192e2ant_TdmaDurationAdjustForWifiRssiLow( + IN PBTC_COEXIST pBtCoexist//, + //IN u1Byte wifiStatus + ) +{ + static s4Byte up,dn,m,n,WaitCount; + s4Byte result; //0: no change, +1: increase WiFi duration, -1: decrease WiFi duration + u1Byte retryCount=0, btInfoExt; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], halbtc8192e2ant_TdmaDurationAdjustForWifiRssiLow()\n")); +#if 0 + if( (BT_8192E_2ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN == wifiStatus) || + (BT_8192E_2ANT_WIFI_STATUS_CONNECTED_SCAN == wifiStatus) || + (BT_8192E_2ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT == wifiStatus) ) + { + if( pCoexDm->curPsTdma != 81 && + pCoexDm->curPsTdma != 82 && + pCoexDm->curPsTdma != 83 && + pCoexDm->curPsTdma != 84 ) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 82); + pCoexDm->psTdmaDuAdjType = 82; + + up = 0; + dn = 0; + m = 1; + n= 3; + result = 0; + WaitCount = 0; + } + return; + } +#endif + pCoexDm->bAutoTdmaAdjust = FALSE; + + retryCount = pCoexSta->btRetryCnt; + btInfoExt = pCoexSta->btInfoExt; + + if(!pCoexDm->bAutoTdmaAdjustLowRssi) + { + pCoexDm->bAutoTdmaAdjustLowRssi = TRUE; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], first run TdmaDurationAdjustForWifiRssiLow()!!\n")); + +/* + if(BT_INFO_8192E_2ANT_A2DP_BASIC_RATE(btInfoExt)) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 83); + pCoexDm->psTdmaDuAdjType = 83; + } + else +*/ + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 81); + pCoexDm->psTdmaDuAdjType = 81; + } + //============ + up = 0; + dn = 0; + m = 1; + n= 3; + result = 0; + WaitCount = 0; + } + else + { + //accquire the BT TRx retry count from BT_Info byte2 +// retryCount = pCoexSta->btRetryCnt; +// btInfoExt = pCoexSta->btInfoExt; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], retryCount = %d\n", retryCount)); + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], up=%d, dn=%d, m=%d, n=%d, WaitCount=%d\n", + up, dn, m, n, WaitCount)); + result = 0; + WaitCount++; + + if ( (pCoexSta->lowPriorityTx) > 1050 || (pCoexSta->lowPriorityRx) > 1250 ) + retryCount++; + + if(retryCount == 0) // no retry in the last 2-second duration + { + up++; + dn--; + + if (dn <= 0) + dn = 0; + + if(up >= n) // if s n 2 retry count0, hռeWiFi duration + { + WaitCount = 0; + n = 3; + up = 0; + dn = 0; + result = 1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Increase wifi duration!!\n")); + } + } + else if (retryCount <= 3) // <=3 retry in the last 2-second duration + { + up--; + dn++; + + if (up <= 0) + up = 0; + + if (dn == 2) // if s 2 2 retry count< 3, hկWiFi duration + { + if (WaitCount <= 2) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter<3!!\n")); + } + } + else //retry count > 3, un1 retry count > 3, hկWiFi duration + { + if (WaitCount == 1) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter>3!!\n")); + } + + if(result == -1) + { +/* + if( (BT_INFO_8192E_2ANT_A2DP_BASIC_RATE(btInfoExt)) && + ((pCoexDm->curPsTdma == 81) ||(pCoexDm->curPsTdma == 82)) ) + if( (BT_INFO_8192E_2ANT_A2DP_BASIC_RATE(btInfoExt)) && + ((pCoexDm->curPsTdma == 81) ||(pCoexDm->curPsTdma == 82)) ) + + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 84); + pCoexDm->psTdmaDuAdjType = 84; + } +*/ + if(pCoexDm->curPsTdma == 80) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 81); + pCoexDm->psTdmaDuAdjType = 81; + } + else if(pCoexDm->curPsTdma == 81) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 82); + pCoexDm->psTdmaDuAdjType = 82; + } + else if(pCoexDm->curPsTdma == 82) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 83); + pCoexDm->psTdmaDuAdjType = 83; + } + else if(pCoexDm->curPsTdma == 83) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 84); + pCoexDm->psTdmaDuAdjType = 84; + } + } + else if(result == 1) + { +/* + if( (BT_INFO_8192E_2ANT_A2DP_BASIC_RATE(btInfoExt)) && + ((pCoexDm->curPsTdma == 81) ||(pCoexDm->curPsTdma == 82)) ) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 83); + pCoexDm->psTdmaDuAdjType = 83; + } +*/ + if(pCoexDm->curPsTdma == 84) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 83); + pCoexDm->psTdmaDuAdjType = 83; + } + else if(pCoexDm->curPsTdma == 83) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 82); + pCoexDm->psTdmaDuAdjType = 82; + } + else if(pCoexDm->curPsTdma == 82) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 81); + pCoexDm->psTdmaDuAdjType = 81; + } + else if((pCoexDm->curPsTdma == 81)&&((pCoexSta->nScanAPNum <= NOISY_AP_NUM_THRESH))) + { + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 80); + pCoexDm->psTdmaDuAdjType = 80; + } + + } + + if( pCoexDm->curPsTdma != 80 && + pCoexDm->curPsTdma != 81 && + pCoexDm->curPsTdma != 82 && + pCoexDm->curPsTdma != 83 && + pCoexDm->curPsTdma != 84 ) + { + // recover to previous adjust type + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, pCoexDm->psTdmaDuAdjType); + } + } +} + +VOID +halbtc8192e2ant_GetBtRssiThreshold( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte pThres0, + IN pu1Byte pThres1 + ) +{ + u1Byte antType, btThreshold=0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_ANT_TYPE, &antType); + + switch(antType) + { + case BTC_ANT_TYPE_0: // 92E with SPDT + *pThres0 = 100; + *pThres1 = 100; + break; + case BTC_ANT_TYPE_1: //92E without SPDT, poor antenna isolation + *pThres0 = 34; + *pThres1 = 42; + break; + case BTC_ANT_TYPE_2: //92E without SPDT, normal antenna isolation + *pThres0 = 34; //92E with coupler, goodl antenna isolation + *pThres1 = 42; + break; + case BTC_ANT_TYPE_3: + *pThres0 = 34; + *pThres1 = 42; + break; + case BTC_ANT_TYPE_4: + *pThres0 = 34; + *pThres1 = 42; + break; + default: + break; + } +} + + +//undefined +VOID +halbtc8192e2ant_ActionUndefined( + IN PBTC_COEXIST pBtCoexist + ) +{ + // power save state + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // coex table + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + // pstdma + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + + // decrease BT power + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + // limited Rx + halbtc8192e2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + // fw dac swing level + halbtc8192e2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + // sw mechanism + halbtc8192e2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); +} + + +// SCO only or SCO+PAN(HS) +VOID +halbtc8192e2ant_ActionSco( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH, btRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiBw; + u1Byte btThresh0=0, btThresh1=0; + BOOLEAN bApEnable=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + + halbtc8192e2ant_GetBtRssiThreshold(pBtCoexist, &btThresh0, &btThresh1); + btRssiState = halbtc8192e2ant_BtRssiState(3, btThresh0, btThresh1); + + wifiRssiState = halbtc8192e2ant_WifiRssiState(pBtCoexist, 0, 2, 34, 0); + // btRssiState = halbtc8192e2ant_BtRssiState(3, 34, 42); + + // power save state + if((bApEnable == TRUE) || (BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)))) + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + // halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, TRUE, 0x50, 0x4); + + // coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + else + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + // pstdma + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + else + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + + // decrease BT power + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + // limited Rx + halbtc8192e2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + // fw dac swing level + halbtc8192e2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + // sw mechanism + halbtc8192e2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); +} + +VOID +halbtc8192e2ant_ActionScoPan( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH, btRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiBw; + u1Byte btThresh0=0, btThresh1=0; + BOOLEAN bApEnable=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + + halbtc8192e2ant_GetBtRssiThreshold(pBtCoexist, &btThresh0, &btThresh1); + btRssiState = halbtc8192e2ant_BtRssiState(3, btThresh0, btThresh1); + + wifiRssiState = halbtc8192e2ant_WifiRssiState(pBtCoexist, 0, 2, 34, 0); + // btRssiState = halbtc8192e2ant_BtRssiState(3, 34, 42); + + // power save state + if((bApEnable == TRUE) || (BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)))) + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + + // coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + else + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + + // pstdm + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH)) + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); //shielding room + else if (BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH)) + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, TRUE, 10); //open space //antenna at BT + else //low RSSI + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 86); + + +/* + // decrease BT power + if(BTC_RSSI_LOW(btRssiState)) + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + else if(BTC_RSSI_MEDIUM(btRssiState)) + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else if (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH) // BT HIGH RSSI & shielding room + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 4); +*/ + + // limited Rx + halbtc8192e2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + // fw dac swing level + halbtc8192e2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + // sw mechanism + halbtc8192e2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH)) + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); //shielding room + else if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH)) + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); //open space + else //low RSSI + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); +} + +VOID +halbtc8192e2ant_ActionHid( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH, btRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiBw; + u1Byte anttype=0; + BOOLEAN bApEnable=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_ANT_TYPE, &anttype); + +// halbtc8192e2ant_GetBtRssiThreshold(pBtCoexist, &btThresh0, &btThresh1); +// btRssiState = halbtc8192e2ant_BtRssiState(3, btThresh0, btThresh1); + + wifiRssiState = halbtc8192e2ant_WifiRssiState(pBtCoexist, 0, 2, 34, 0); + btRssiState = halbtc8192e2ant_BtRssiState(3, 34, 42); + + if(anttype == 0)//ANTTYPE = 0 92E 2ant with SPDT + { + // power save state & pstdma & coex table + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + else if(anttype == 1) //92E 2ant with coupler and bad ant. isolation, 92E 3ant with bad ant. isolation + { + // power save state & pstdma & coex table + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + else if(anttype == 2)//ANTTYPE = 2, 92E 2ant with coupler and normal/good ant. isolation, 92E 3ant with normal ant. isolation + { + // power save state & pstdma & coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH)) + { //WIFI RSSI = high & BT RSSI = high & shielding room + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, TRUE, 9); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 3); + } + else if (BTC_RSSI_HIGH(wifiRssiState)&&(!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH)) + { //WIFI RSSI = high & BT RSSI = high & noisy enviroment + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, TRUE, 9); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 3); + } + else //WIFI RSSI || BT RSSI == low + { + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, TRUE, 9); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 3); + } + } + else if(anttype == 3) //ANTTYPE = 3, 92E 3ant with good ant. isolation + { + // power save state & pstdma & coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH)) + { //WIFI RSSI = high & BT RSSI = high & shielding room + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + } + else if (BTC_RSSI_HIGH(wifiRssiState)&&(!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH)) + { //WIFI RSSI = high & BT RSSI = high & noisy enviroment + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + } + else //WIFI RSSI || BT RSSI == low + { + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + } + else //ANTTYPE = 4 for test + { + // power save state & pstdma & coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH)) + { //WIFI RSSI = high & BT RSSI = high & shielding room + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8192e2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + else if (BTC_RSSI_HIGH(wifiRssiState)&&(!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH)) + { //WIFI RSSI = high & BT RSSI = high & noisy enviroment + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8192e2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + else //WIFI RSSI || BT RSSI == low + { + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8192e2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + } + + // power save state + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // coex table + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + // pstdma + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + + // decrease BT power + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + // limited Rx + halbtc8192e2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + // fw dac swing level + halbtc8192e2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + // sw mechanism + halbtc8192e2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); +} + +//A2DP only / PAN(EDR) only/ A2DP+PAN(HS) +VOID +halbtc8192e2ant_ActionA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH, btRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiBw; + u1Byte anttype=0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_ANT_TYPE, &anttype); + +// halbtc8192e2ant_GetBtRssiThreshold(pBtCoexist, &btThresh0, &btThresh1); +// btRssiState = halbtc8192e2ant_BtRssiState(3, btThresh0, btThresh1); + + wifiRssiState = halbtc8192e2ant_WifiRssiState(pBtCoexist, 0, 2, 34, 0); + btRssiState = halbtc8192e2ant_BtRssiState(3, 34, 42); + +// anttype = 4; + + if(anttype == 0)//ANTTYPE = 0 92E 2ant with SPDT + { + // power save state & pstdma & coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH)) + { //WIFI RSSI = high & BT RSSI = high & shielding room + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8192e2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + else if (BTC_RSSI_HIGH(wifiRssiState)&&(!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH)) + { //WIFI RSSI = high & BT RSSI = high & noisy enviroment + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8192e2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + else //WIFI RSSI || BT RSSI == low + { + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8192e2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + } + else if(anttype == 1) //92E 2ant with coupler and bad ant. isolation, 92E 3ant with bad ant. isolation + { + // power save state & pstdma & coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH)) + { //WIFI RSSI = high & BT RSSI = high & shielding room + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 1); //shielding room + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + else if (BTC_RSSI_HIGH(wifiRssiState)&&(!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH)) + { //WIFI RSSI = high & BT RSSI = high & noisy enviroment + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + else //WIFI RSSI || BT RSSI == low + { + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8192e2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + + } + else if(anttype == 2)//ANTTYPE = 2, 92E 2ant with coupler and normal/good ant. isolation, 92E 3ant with normal ant. isolation + { + // power save state & pstdma & coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH)) + { //WIFI RSSI = high & BT RSSI = high & shielding room + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 1); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 5); + } + else if (BTC_RSSI_HIGH(wifiRssiState)&&(!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH)) + { //WIFI RSSI = high & BT RSSI = high & noisy enviroment + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + else //WIFI RSSI || BT RSSI == low + { + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8192e2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + } + else if(anttype == 3) //ANTTYPE = 3, 92E 3ant with good ant. isolation + { + // power save state & pstdma & coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH)) + { //WIFI RSSI = high & BT RSSI = high & shielding room + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + } + else if (BTC_RSSI_HIGH(wifiRssiState)&&(!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH)) + { //WIFI RSSI = high & BT RSSI = high & noisy enviroment + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + } + else //WIFI RSSI || BT RSSI == low + { + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + } + else //ANTTYPE = 4 for test + { + // power save state & pstdma & coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH)) + { //WIFI RSSI = high & BT RSSI = high & shielding room + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8192e2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + else if (BTC_RSSI_HIGH(wifiRssiState)&&(!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH)) + { //WIFI RSSI = high & BT RSSI = high & noisy enviroment + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8192e2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + else //WIFI RSSI || BT RSSI == low + { + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8192e2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + } + +/* + // decrease BT power + if(BTC_RSSI_LOW(btRssiState)) + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + else if(BTC_RSSI_MEDIUM(btRssiState)) + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else if (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH) // BT HIGH RSSI & shielding room + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 4); +*/ + // limited Rx + halbtc8192e2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + // fw dac swing level + halbtc8192e2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + // sw mechanism + halbtc8192e2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH)) + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); //shielding room + else if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH)) + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,TRUE,0x06); //open space + else //low RSSI + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); +} + +VOID +halbtc8192e2ant_ActionA2dpPanHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, btRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiBw; + + wifiRssiState = halbtc8192e2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + btRssiState = halbtc8192e2ant_BtRssiState(3, 34, 42); + +// halbtc8192e2ant_SwitchSsType(pBtCoexist, NORMAL_EXEC, 1); + halbtc8192e2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8192e2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + + if( (btRssiState == BTC_RSSI_STATE_LOW) || + (btRssiState == BTC_RSSI_STATE_STAY_LOW) ) + { + halbtc8192e2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 2); + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + } + else if( (btRssiState == BTC_RSSI_STATE_MEDIUM) || + (btRssiState == BTC_RSSI_STATE_STAY_MEDIUM) ) + { + halbtc8192e2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 2); + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + } + else if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8192e2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 2); + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 4); + } + + // sw mechanism + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + halbtc8192e2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); +} + +VOID +halbtc8192e2ant_ActionPanEdr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH, btRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiBw; + u1Byte btThresh0=0, btThresh1=0; + + halbtc8192e2ant_GetBtRssiThreshold(pBtCoexist, &btThresh0, &btThresh1); + btRssiState = halbtc8192e2ant_BtRssiState(3, btThresh0, btThresh1); + + wifiRssiState = halbtc8192e2ant_WifiRssiState(pBtCoexist, 0, 2, 34, 0); + // btRssiState = halbtc8192e2ant_BtRssiState(3, 34, 42); + + // power save state + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + + // coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + // pstdma + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH)) + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); //shielding room + else if (BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH)) + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); //open space //antenna at BT + else //low RSSI + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 85); + +/* + // decrease BT power + if(BTC_RSSI_LOW(btRssiState)) + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + else if(BTC_RSSI_MEDIUM(btRssiState)) + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else if (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH) // BT HIGH RSSI & shielding room + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 4); +*/ + + // limited Rx + halbtc8192e2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + // fw dac swing level + halbtc8192e2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + // sw mechanism + halbtc8192e2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH)) + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); //shielding room + else if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH)) + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); //open space + else //low RSSI + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); +} + +//PAN(HS) only +VOID +halbtc8192e2ant_ActionPanHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, btRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiBw; + + wifiRssiState = halbtc8192e2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + btRssiState = halbtc8192e2ant_BtRssiState(3, 34, 42); + +// halbtc8192e2ant_SwitchSsType(pBtCoexist, NORMAL_EXEC, 1); + halbtc8192e2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + + if( (btRssiState == BTC_RSSI_STATE_LOW) || + (btRssiState == BTC_RSSI_STATE_STAY_LOW) ) + { + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + } + else if( (btRssiState == BTC_RSSI_STATE_MEDIUM) || + (btRssiState == BTC_RSSI_STATE_STAY_MEDIUM) ) + { + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + } + else if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 4); + } + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + halbtc8192e2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); +} + +//PAN(EDR)+A2DP +VOID +halbtc8192e2ant_ActionPanEdrA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH, btRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiBw; + u1Byte btThresh0=0, btThresh1=0; + + halbtc8192e2ant_GetBtRssiThreshold(pBtCoexist, &btThresh0, &btThresh1); + btRssiState = halbtc8192e2ant_BtRssiState(3, btThresh0, btThresh1); + + wifiRssiState = halbtc8192e2ant_WifiRssiState(pBtCoexist, 0, 2, 34, 0); + // btRssiState = halbtc8192e2ant_BtRssiState(3, 34, 42); + + // power save state + if((BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)))) + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + + // coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + // pstdma + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH)) + halbtc8192e2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 3); //shielding room + else if (BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH)) + halbtc8192e2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 3); //open space //antenna at BT + else //low RSSI +{ + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 86); +} + +/* + // decrease BT power + if(BTC_RSSI_LOW(btRssiState)) + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + else if(BTC_RSSI_MEDIUM(btRssiState)) + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else if (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH) // BT HIGH RSSI & shielding room + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 4); +*/ + + // limited Rx + halbtc8192e2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + // fw dac swing level + halbtc8192e2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + // sw mechanism + halbtc8192e2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH)) + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); //shielding room + else if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH)) + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); //open space + else //low RSSI + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); +} + +VOID +halbtc8192e2ant_ActionPanEdrHid( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH, btRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiBw; + u1Byte btThresh0=0, btThresh1=0; + + halbtc8192e2ant_GetBtRssiThreshold(pBtCoexist, &btThresh0, &btThresh1); + btRssiState = halbtc8192e2ant_BtRssiState(3, btThresh0, btThresh1); + + wifiRssiState = halbtc8192e2ant_WifiRssiState(pBtCoexist, 0, 2, 34, 0); + // btRssiState = halbtc8192e2ant_BtRssiState(3, 34, 42); + + // power save state + if((BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)))) + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + + // coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 3); + else + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + // pstdm + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH)) + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); //shielding room + else if (BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH)) + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); //open space //antenna at BT + else //low RSSI + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 86); + +/* + // decrease BT power + if(BTC_RSSI_LOW(btRssiState)) + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + else if(BTC_RSSI_MEDIUM(btRssiState)) + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else if (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH) // BT HIGH RSSI & shielding room + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 4); +*/ + + // limited Rx + halbtc8192e2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + // fw dac swing level + halbtc8192e2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + // sw mechanism + halbtc8192e2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH)) + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); //shielding room + else if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH)) + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); //open space + else //low RSSI + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); +} + +// HID+A2DP+PAN(EDR) +VOID +halbtc8192e2ant_ActionHidA2dpPanEdr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH, btRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiBw; + u1Byte btThresh0=0, btThresh1=0; + + halbtc8192e2ant_GetBtRssiThreshold(pBtCoexist, &btThresh0, &btThresh1); + btRssiState = halbtc8192e2ant_BtRssiState(3, btThresh0, btThresh1); + + wifiRssiState = halbtc8192e2ant_WifiRssiState(pBtCoexist, 0, 2, 34, 0); + // btRssiState = halbtc8192e2ant_BtRssiState(3, 34, 42); + + // power save state + if((BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)))) + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + + // coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 3); + else + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); //6 + + // pstdma + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH)) + halbtc8192e2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 3); //shielding room + else if (BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH)) + halbtc8192e2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 3); //open space //antenna at BT + else //low RSSI + { + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8192e2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 86); + } + +/* + // decrease BT power + if(BTC_RSSI_LOW(btRssiState)) + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + else if(BTC_RSSI_MEDIUM(btRssiState)) + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else if (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH) // BT HIGH RSSI & shielding room + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 4); +*/ + // limited Rx + halbtc8192e2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + // fw dac swing level + halbtc8192e2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + // sw mechanism + halbtc8192e2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH)) + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); //shielding room + else if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH)) + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); //open space + else //low RSSI + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); +} + +VOID +halbtc8192e2ant_ActionHidA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH, btRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiBw; + u1Byte btThresh0=0, btThresh1=0, anttype=0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_ANT_TYPE, &anttype); + + // halbtc8192e2ant_GetBtRssiThreshold(pBtCoexist, &btThresh0, &btThresh1); + // btRssiState = halbtc8192e2ant_BtRssiState(3, btThresh0, btThresh1); + + wifiRssiState = halbtc8192e2ant_WifiRssiState(pBtCoexist, 0, 2, 34, 0); + btRssiState = halbtc8192e2ant_BtRssiState(3, 34, 42); + + if(anttype == 0)//ANTTYPE = 0 92E 2ant with SPDT + { + // power save state & pstdma & coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH)) + { + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, TRUE, 83); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 8); + + } + else if (BTC_RSSI_HIGH(wifiRssiState)&&(!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH)) + { + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + else + { + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, TRUE, 83); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 8); + } + } + else if(anttype == 1) //92E 2ant with coupler and bad ant. isolation, 92E 3ant with bad ant. isolation + { + // power save state & pstdma & coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH)) + { + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 2); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 8); + } + else if (BTC_RSSI_HIGH(wifiRssiState)&&(!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH)) + { + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + else + { + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, TRUE, 83); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 8); + } + } + else if(anttype == 2)//ANTTYPE = 2, 92E 2ant with coupler and normal/good ant. isolation, 92E 3ant with normal ant. isolation + { + // power save state & pstdma & coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH)) + { //WIFI RSSI = high & BT RSSI = high & shielding room + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 2); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 8); + } + else if (BTC_RSSI_HIGH(wifiRssiState)&&(!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH)) + { //WIFI RSSI = high & BT RSSI = high & noisy enviroment + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 8); + } + else //WIFI RSSI || BT RSSI == low + { + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, TRUE, 83); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 8); + } + } + else if(anttype == 3) //ANTTYPE = 3, 92E 3ant with good ant. isolation + { + // power save state & pstdma & coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH)) + { //WIFI RSSI = high & BT RSSI = high & shielding room + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + } + else if (BTC_RSSI_HIGH(wifiRssiState)&&(!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH)) + { //WIFI RSSI = high & BT RSSI = high & noisy enviroment + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + } + else //WIFI RSSI || BT RSSI == low + { + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8192e2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + } + else //ANTTYPE = 4 for test + { + // power save state & pstdma & coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH)) + { //WIFI RSSI = high & BT RSSI = high & shielding room + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8192e2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + else if (BTC_RSSI_HIGH(wifiRssiState)&&(!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH)) + { //WIFI RSSI = high & BT RSSI = high & noisy enviroment + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8192e2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + else //WIFI RSSI || BT RSSI == low + { + halbtc8192e2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8192e2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8192e2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + } + +/* + // decrease BT power + if(BTC_RSSI_LOW(btRssiState)) + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + else if(BTC_RSSI_MEDIUM(btRssiState)) + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else if (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH) // BT HIGH RSSI & shielding room + halbtc8192e2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 4); +*/ + + // limited Rx + halbtc8192e2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + // fw dac swing level + halbtc8192e2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + // sw mechanism + halbtc8192e2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH)) + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); //shielding room + else if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH)) + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,TRUE,0x06); //open space + else //low RSSI + halbtc8192e2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); +} + +VOID +halbtc8192e2ant_ActionBtWhckTest( + IN PBTC_COEXIST pBtCoexist + ) +{ + +} + +VOID +halbtc8192e2ant_ActionWifiMultiPort( + IN PBTC_COEXIST pBtCoexist + ) +{ + +} + +VOID +halbtc8192e2ant_RunCoexistMechanism( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bWifiUnder5G=FALSE; + u1Byte btInfoOriginal=0, btRetryCnt=0; + u1Byte algorithm=0; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], RunCoexistMechanism()===>\n")); + + if(pBtCoexist->bManualControl) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n")); + return; + } + + if(pCoexSta->bUnderIps) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi is under IPS !!!\n")); + return; + } + + algorithm = halbtc8192e2ant_ActionAlgorithm(pBtCoexist); + if(pCoexSta->bC2hBtInquiryPage && (BT_8192E_2ANT_COEX_ALGO_PANHS!=algorithm)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is under inquiry/page scan !!\n")); + halbtc8192e2ant_ActionBtInquiry(pBtCoexist); + return; + } + + pCoexDm->curAlgorithm = algorithm; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Algorithm = %d \n", pCoexDm->curAlgorithm)); + + if(halbtc8192e2ant_IsCommonAction(pBtCoexist)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant common.\n")); + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + } + else + { + if(pCoexDm->curAlgorithm != pCoexDm->preAlgorithm) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], preAlgorithm=%d, curAlgorithm=%d\n", + pCoexDm->preAlgorithm, pCoexDm->curAlgorithm)); + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + } + switch(pCoexDm->curAlgorithm) + { + case BT_8192E_2ANT_COEX_ALGO_SCO: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = SCO.\n")); + halbtc8192e2ant_ActionSco(pBtCoexist); + break; + case BT_8192E_2ANT_COEX_ALGO_SCO_PAN: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = SCO+PAN(EDR).\n")); + halbtc8192e2ant_ActionScoPan(pBtCoexist); + break; + case BT_8192E_2ANT_COEX_ALGO_HID: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID.\n")); + halbtc8192e2ant_ActionHid(pBtCoexist); + break; + case BT_8192E_2ANT_COEX_ALGO_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = A2DP.\n")); + halbtc8192e2ant_ActionA2dp(pBtCoexist); + break; + case BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n")); + halbtc8192e2ant_ActionA2dpPanHs(pBtCoexist); + break; + case BT_8192E_2ANT_COEX_ALGO_PANEDR: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n")); + halbtc8192e2ant_ActionPanEdr(pBtCoexist); + break; + case BT_8192E_2ANT_COEX_ALGO_PANHS: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HS mode.\n")); + halbtc8192e2ant_ActionPanHs(pBtCoexist); + break; + case BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n")); + halbtc8192e2ant_ActionPanEdrA2dp(pBtCoexist); + break; + case BT_8192E_2ANT_COEX_ALGO_PANEDR_HID: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n")); + halbtc8192e2ant_ActionPanEdrHid(pBtCoexist); + break; + case BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n")); + halbtc8192e2ant_ActionHidA2dpPanEdr(pBtCoexist); + break; + case BT_8192E_2ANT_COEX_ALGO_HID_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n")); + halbtc8192e2ant_ActionHidA2dp(pBtCoexist); + break; + default: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = undefined!!\n")); + halbtc8192e2ant_ActionUndefined(pBtCoexist); + break; + } + pCoexDm->preAlgorithm = pCoexDm->curAlgorithm; + } +} + +VOID +halbtc8192e2ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bBackUp + ) +{ + u4Byte u4Tmp=0; + u2Byte u2Tmp=0; + u1Byte u1Tmp=0; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 2Ant Init HW Config!!\n")); + + if(bBackUp) + { + // backup rf 0x1e value + pCoexDm->btRf0x1eBackup = + pBtCoexist->fBtcGetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff); + + pCoexDm->backupArfrCnt1 = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x430); + pCoexDm->backupArfrCnt2 = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x434); + pCoexDm->backupRetryLimit = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0x42a); + pCoexDm->backupAmpduMaxTime = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x456); + } + + // antenna sw ctrl to bt + halbtc8192e2ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, TRUE, FALSE); + + halbtc8192e2ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 0); + + // antenna switch control parameter + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x858, 0x55555555); + + // coex parameters + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x778, 0x3); + // 0x790[5:0]=0x5 + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x790); + u1Tmp &= 0xc0; + u1Tmp |= 0x5; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x790, u1Tmp); + + // enable counter statistics + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0x4); + + // enable PTA + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x20); + // enable mailbox interface + u2Tmp = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0x40); + u2Tmp |= BIT9; + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x40, u2Tmp); + + // enable PTA I2C mailbox + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x101); + u1Tmp |= BIT4; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x101, u1Tmp); + + // enable bt clock when wifi is disabled. + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x93); + u1Tmp |= BIT0; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x93, u1Tmp); + // enable bt clock when suspend. + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x7); + u1Tmp |= BIT0; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x7, u1Tmp); +} + +//============================================================ +// work around function start with wa_halbtc8192e2ant_ +//============================================================ +//============================================================ +// extern function start with EXhalbtc8192e2ant_ +//============================================================ +VOID +EXhalbtc8192e2ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ) +{ +} + +VOID +EXhalbtc8192e2ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ) +{ + halbtc8192e2ant_InitHwConfig(pBtCoexist, TRUE); +} + +VOID +EXhalbtc8192e2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Coex Mechanism Init!!\n")); + + halbtc8192e2ant_InitCoexDm(pBtCoexist); +} + +VOID +EXhalbtc8192e2ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + pu1Byte cliBuf=pBtCoexist->cliBuf; + u1Byte u1Tmp[4], i, btInfoExt, psTdmaCase=0; + u2Byte u2Tmp[4]; + u4Byte u4Tmp[4]; + u4Byte faOfdm, faCck; + u4Byte fwVer=0, btPatchVer=0; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cliBuf); + + if(pBtCoexist->bManualControl) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[Under Manual Control]============"); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n =========================================="); + CL_PRINTF(cliBuf); + } + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:", \ + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "Antenna type:", \ + pBoardInfo->antType); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \ + ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion); + CL_PRINTF(cliBuf); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_BT_PATCH_VER, &btPatchVer); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)", "CoexVer/ FwVer/ PatchVer", \ + GLCoexVerDate8192e2Ant, GLCoexVer8192e2Ant, fwVer, btPatchVer, btPatchVer); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", "Wifi channel informed to BT", \ + pCoexDm->wifiChnlInfo[0], pCoexDm->wifiChnlInfo[1], + pCoexDm->wifiChnlInfo[2]); + CL_PRINTF(cliBuf); + + // wifi status + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Wifi Status]============"); + CL_PRINTF(cliBuf); + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[BT Status]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", "BT [status/ rssi/ retryCnt]", \ + ((pBtCoexist->btInfo.bBtDisabled)? ("disabled"): ((pCoexSta->bC2hBtInquiryPage)?("inquiry/page scan"):((BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus)? "non-connected idle": + ( (BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus)? "connected-idle":"busy")))), + pCoexSta->btRssi, pCoexSta->btRetryCnt); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP", \ + pStackInfo->bScoExist, pStackInfo->bHidExist, pStackInfo->bPanExist, pStackInfo->bA2dpExist); + CL_PRINTF(cliBuf); + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO); + + btInfoExt = pCoexSta->btInfoExt; + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Info A2DP rate", \ + (btInfoExt&BIT0)? "Basic rate":"EDR rate"); + CL_PRINTF(cliBuf); + + for(i=0; ibtInfoC2hCnt[i]) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", GLBtInfoSrc8192e2Ant[i], \ + pCoexSta->btInfoC2h[i][0], pCoexSta->btInfoC2h[i][1], + pCoexSta->btInfoC2h[i][2], pCoexSta->btInfoC2h[i][3], + pCoexSta->btInfoC2h[i][4], pCoexSta->btInfoC2h[i][5], + pCoexSta->btInfoC2h[i][6], pCoexSta->btInfoC2hCnt[i]); + CL_PRINTF(cliBuf); + } + } +/* + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "SS Type", \ + pCoexDm->curSsType); + CL_PRINTF(cliBuf); +*/ + // Sw mechanism + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============"); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", "SM1[ShRf/ LpRA/ LimDig]", \ + pCoexDm->bCurRfRxLpfShrink, pCoexDm->bCurLowPenaltyRa, pCoexDm->bLimitedDig); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", \ + pCoexDm->bCurAgcTableEn, pCoexDm->bCurAdcBackOff, pCoexDm->bCurDacSwingOn, pCoexDm->curDacSwingLvl); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "Rate Mask", \ + pBtCoexist->btInfo.raMask); + CL_PRINTF(cliBuf); + + // Fw mechanism + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============"); + CL_PRINTF(cliBuf); + + psTdmaCase = pCoexDm->curPsTdma; + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)", "PS TDMA", \ + pCoexDm->psTdmaPara[0], pCoexDm->psTdmaPara[1], + pCoexDm->psTdmaPara[2], pCoexDm->psTdmaPara[3], + pCoexDm->psTdmaPara[4], psTdmaCase, pCoexDm->bAutoTdmaAdjust); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "DecBtPwr/ IgnWlanAct", \ + pCoexDm->curBtDecPwrLvl, pCoexDm->bCurIgnoreWlanAct); + CL_PRINTF(cliBuf); + + // Hw setting + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "RF-A, 0x1e initVal", \ + pCoexDm->btRf0x1eBackup); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", "backup ARFR1/ARFR2/RL/AMaxTime", \ + pCoexDm->backupArfrCnt1, pCoexDm->backupArfrCnt2, pCoexDm->backupRetryLimit, pCoexDm->backupAmpduMaxTime); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x430); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x434); + u2Tmp[0] = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0x42a); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x456); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", "0x430/0x434/0x42a/0x456", \ + u4Tmp[0], u4Tmp[1], u2Tmp[0], u1Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc04); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xd04); + u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x90c); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0xc04/ 0xd04/ 0x90c", \ + u4Tmp[0], u4Tmp[1], u4Tmp[2]); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x778); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x778", \ + u1Tmp[0]); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x92c); + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x930); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x92c/ 0x930", \ + (u1Tmp[0]), u4Tmp[0]); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x40); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4f); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x40/ 0x4f", \ + u1Tmp[0], u1Tmp[1]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x550); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x522); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x550(bcn ctrl)/0x522", \ + u4Tmp[0], u1Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc50); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", \ + u4Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c0); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c4); + u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c8); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x6cc); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", \ + u4Tmp[0], u4Tmp[1], u4Tmp[2], u1Tmp[0]); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x770(hp rx[31:16]/tx[15:0])", \ + pCoexSta->highPriorityRx, pCoexSta->highPriorityTx); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x774(lp rx[31:16]/tx[15:0])", \ + pCoexSta->lowPriorityRx, pCoexSta->lowPriorityTx); + CL_PRINTF(cliBuf); +#if(BT_AUTO_REPORT_ONLY_8192E_2ANT == 1) + halbtc8192e2ant_MonitorBtCtr(pBtCoexist); +#endif + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + + +VOID +EXhalbtc8192e2ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_IPS_ENTER == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS ENTER notify\n")); + pCoexSta->bUnderIps = TRUE; + halbtc8192e2ant_CoexAllOff(pBtCoexist); + halbtc8192e2ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FALSE, TRUE); + } + else if(BTC_IPS_LEAVE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS LEAVE notify\n")); + pCoexSta->bUnderIps = FALSE; + } +} + +VOID +EXhalbtc8192e2ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_LPS_ENABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS ENABLE notify\n")); + pCoexSta->bUnderLps = TRUE; + } + else if(BTC_LPS_DISABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS DISABLE notify\n")); + pCoexSta->bUnderLps = FALSE; + } +} + +VOID +EXhalbtc8192e2ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_SCAN_START == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n")); + } + else if(BTC_SCAN_FINISH == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n")); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_AP_NUM, &pCoexSta->nScanAPNum); + + } +} + +VOID +EXhalbtc8192e2ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_ASSOCIATE_START == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n")); + } + else if(BTC_ASSOCIATE_FINISH == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n")); + } +} + +VOID +EXhalbtc8192e2ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + u1Byte H2C_Parameter[3] ={0}; + u4Byte wifiBw; + u1Byte wifiCentralChnl; + + if(pBtCoexist->bManualControl || + pBtCoexist->bStopCoexDm || + pBtCoexist->btInfo.bBtDisabled ) + return; + + if(BTC_MEDIA_CONNECT == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA connect notify\n")); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA disconnect notify\n")); + } + + + // only 2.4G we need to inform bt the chnl mask + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, &wifiCentralChnl); + if( (BTC_MEDIA_CONNECT == type) && + (wifiCentralChnl <= 14) ) + { + H2C_Parameter[0] = 0x1; + H2C_Parameter[1] = wifiCentralChnl; + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + H2C_Parameter[2] = 0x30; + else + H2C_Parameter[2] = 0x20; + } + + pCoexDm->wifiChnlInfo[0] = H2C_Parameter[0]; + pCoexDm->wifiChnlInfo[1] = H2C_Parameter[1]; + pCoexDm->wifiChnlInfo[2] = H2C_Parameter[2]; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x66=0x%x\n", + H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x66, 3, H2C_Parameter); +} + +VOID +EXhalbtc8192e2ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(type == BTC_PACKET_DHCP) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], DHCP Packet notify\n")); + } +} + +VOID +EXhalbtc8192e2ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + u1Byte btInfo=0; + u1Byte i, rspSource=0; + BOOLEAN bBtBusy=FALSE, bLimitedDig=FALSE; + BOOLEAN bWifiConnected=FALSE; + + pCoexSta->bC2hBtInfoReqSent = FALSE; + + rspSource = tmpBuf[0]&0xf; + if(rspSource >= BT_INFO_SRC_8192E_2ANT_MAX) + rspSource = BT_INFO_SRC_8192E_2ANT_WIFI_FW; + pCoexSta->btInfoC2hCnt[rspSource]++; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Bt info[%d], length=%d, hex data=[", rspSource, length)); + for(i=0; ibtInfoC2h[rspSource][i] = tmpBuf[i]; + if(i == 1) + btInfo = tmpBuf[i]; + if(i == length-1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x]\n", tmpBuf[i])); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x, ", tmpBuf[i])); + } + } + + if(BT_INFO_SRC_8192E_2ANT_WIFI_FW != rspSource) + { + pCoexSta->btRetryCnt = // [3:0] + pCoexSta->btInfoC2h[rspSource][2]&0xf; + + pCoexSta->btRssi = + pCoexSta->btInfoC2h[rspSource][3]*2+10; + + pCoexSta->btInfoExt = + pCoexSta->btInfoC2h[rspSource][4]; + + // Here we need to resend some wifi info to BT + // because bt is reset and loss of the info. + if( (pCoexSta->btInfoExt & BIT1) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n")); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + + if(bWifiConnected) + { + EXhalbtc8192e2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_CONNECT); + } + else + { + EXhalbtc8192e2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); + } + } + + if( (pCoexSta->btInfoExt & BIT3) ) + { + if(!pBtCoexist->bManualControl && !pBtCoexist->bStopCoexDm) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n")); + halbtc8192e2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE); + } + } + else + { + // BT already NOT ignore Wlan active, do nothing here. + } + +#if(BT_AUTO_REPORT_ONLY_8192E_2ANT == 0) + if( (pCoexSta->btInfoExt & BIT4) ) + { + // BT auto report already enabled, do nothing + } + else + { + halbtc8192e2ant_BtAutoReport(pBtCoexist, FORCE_EXEC, TRUE); + } +#endif + } + + // check BIT2 first ==> check if bt is under inquiry or page scan + if(btInfo & BT_INFO_8192E_2ANT_B_INQ_PAGE) + pCoexSta->bC2hBtInquiryPage = TRUE; + else + pCoexSta->bC2hBtInquiryPage = FALSE; + + // set link exist status + if(!(btInfo&BT_INFO_8192E_2ANT_B_CONNECTION)) + { + pCoexSta->bBtLinkExist = FALSE; + pCoexSta->bPanExist = FALSE; + pCoexSta->bA2dpExist = FALSE; + pCoexSta->bHidExist = FALSE; + pCoexSta->bScoExist = FALSE; + } + else // connection exists + { + pCoexSta->bBtLinkExist = TRUE; + if(btInfo & BT_INFO_8192E_2ANT_B_FTP) + pCoexSta->bPanExist = TRUE; + else + pCoexSta->bPanExist = FALSE; + if(btInfo & BT_INFO_8192E_2ANT_B_A2DP) + pCoexSta->bA2dpExist = TRUE; + else + pCoexSta->bA2dpExist = FALSE; + if(btInfo & BT_INFO_8192E_2ANT_B_HID) + pCoexSta->bHidExist = TRUE; + else + pCoexSta->bHidExist = FALSE; + if(btInfo & BT_INFO_8192E_2ANT_B_SCO_ESCO) + pCoexSta->bScoExist = TRUE; + else + pCoexSta->bScoExist = FALSE; + } + + halbtc8192e2ant_UpdateBtLinkInfo(pBtCoexist); + + if(!(btInfo&BT_INFO_8192E_2ANT_B_CONNECTION)) + { + pCoexDm->btStatus = BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n")); + } + else if(btInfo == BT_INFO_8192E_2ANT_B_CONNECTION) // connection exists but no busy + { + pCoexDm->btStatus = BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n")); + } + else if((btInfo&BT_INFO_8192E_2ANT_B_SCO_ESCO) || + (btInfo&BT_INFO_8192E_2ANT_B_SCO_BUSY)) + { + pCoexDm->btStatus = BT_8192E_2ANT_BT_STATUS_SCO_BUSY; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT SCO busy!!!\n")); + } + else if(btInfo&BT_INFO_8192E_2ANT_B_ACL_BUSY) + { + pCoexDm->btStatus = BT_8192E_2ANT_BT_STATUS_ACL_BUSY; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT ACL busy!!!\n")); + } + else + { + pCoexDm->btStatus = BT_8192E_2ANT_BT_STATUS_MAX; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n")); + } + + if( (BT_8192E_2ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) || + (BT_8192E_2ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8192E_2ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + bBtBusy = TRUE; + bLimitedDig = TRUE; + } + else + { + bBtBusy = FALSE; + bLimitedDig = FALSE; + } + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bBtBusy); + + pCoexDm->bLimitedDig = bLimitedDig; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_LIMITED_DIG, &bLimitedDig); + + halbtc8192e2ant_RunCoexistMechanism(pBtCoexist); +} + +VOID +EXhalbtc8192e2ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Halt notify\n")); + + halbtc8192e2ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FALSE, TRUE); + halbtc8192e2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE); + EXhalbtc8192e2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); +} + +VOID +EXhalbtc8192e2ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ) +{ + static u1Byte disVerInfoCnt=0; + u4Byte fwVer=0, btPatchVer=0; + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ==========================Periodical===========================\n")); + + if(disVerInfoCnt <= 5) + { + disVerInfoCnt += 1; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ****************************************************************\n")); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Ant PG Num/ Ant Mech/ Ant Pos = %d/ %d/ %d\n", + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum, pBoardInfo->btdmAntPos)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT stack/ hci ext ver = %s / %d\n", + ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion)); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_BT_PATCH_VER, &btPatchVer); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CoexVer/ FwVer/ PatchVer = %d_%x/ 0x%x/ 0x%x(%d)\n", + GLCoexVerDate8192e2Ant, GLCoexVer8192e2Ant, fwVer, btPatchVer, btPatchVer)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ****************************************************************\n")); + } + +#if(BT_AUTO_REPORT_ONLY_8192E_2ANT == 0) + halbtc8192e2ant_QueryBtInfo(pBtCoexist); + halbtc8192e2ant_MonitorBtCtr(pBtCoexist); + halbtc8192e2ant_MonitorBtEnableDisable(pBtCoexist); +#else + if( halbtc8192e2ant_IsWifiStatusChanged(pBtCoexist) || + pCoexDm->bAutoTdmaAdjust) + { + halbtc8192e2ant_RunCoexistMechanism(pBtCoexist); + } +#endif +} + + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8192e2Ant.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8192e2Ant.h new file mode 100644 index 000000000..d8e66140e --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8192e2Ant.h @@ -0,0 +1,232 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//=========================================== +// The following is for 8192E 2Ant BT Co-exist definition +//=========================================== +#define BT_AUTO_REPORT_ONLY_8192E_2ANT 0 + +#define BT_INFO_8192E_2ANT_B_FTP BIT7 +#define BT_INFO_8192E_2ANT_B_A2DP BIT6 +#define BT_INFO_8192E_2ANT_B_HID BIT5 +#define BT_INFO_8192E_2ANT_B_SCO_BUSY BIT4 +#define BT_INFO_8192E_2ANT_B_ACL_BUSY BIT3 +#define BT_INFO_8192E_2ANT_B_INQ_PAGE BIT2 +#define BT_INFO_8192E_2ANT_B_SCO_ESCO BIT1 +#define BT_INFO_8192E_2ANT_B_CONNECTION BIT0 + +#define BT_INFO_8192E_2ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ + (((_BT_INFO_EXT_&BIT0))? TRUE:FALSE) + +#define BTC_RSSI_COEX_THRESH_TOL_8192E_2ANT 2 +#define NOISY_AP_NUM_THRESH 5 + +typedef enum _BT_INFO_SRC_8192E_2ANT{ + BT_INFO_SRC_8192E_2ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8192E_2ANT_BT_RSP = 0x1, + BT_INFO_SRC_8192E_2ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8192E_2ANT_MAX +}BT_INFO_SRC_8192E_2ANT,*PBT_INFO_SRC_8192E_2ANT; + +typedef enum _BT_8192E_2ANT_BT_STATUS{ + BT_8192E_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8192E_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8192E_2ANT_BT_STATUS_INQ_PAGE = 0x2, + BT_8192E_2ANT_BT_STATUS_ACL_BUSY = 0x3, + BT_8192E_2ANT_BT_STATUS_SCO_BUSY = 0x4, + BT_8192E_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, + BT_8192E_2ANT_BT_STATUS_MAX +}BT_8192E_2ANT_BT_STATUS,*PBT_8192E_2ANT_BT_STATUS; + +typedef enum _BT_8192E_2ANT_COEX_ALGO{ + BT_8192E_2ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8192E_2ANT_COEX_ALGO_SCO = 0x1, + BT_8192E_2ANT_COEX_ALGO_SCO_PAN = 0x2, + BT_8192E_2ANT_COEX_ALGO_HID = 0x3, + BT_8192E_2ANT_COEX_ALGO_A2DP = 0x4, + BT_8192E_2ANT_COEX_ALGO_A2DP_PANHS = 0x5, + BT_8192E_2ANT_COEX_ALGO_PANEDR = 0x6, + BT_8192E_2ANT_COEX_ALGO_PANHS = 0x7, + BT_8192E_2ANT_COEX_ALGO_PANEDR_A2DP = 0x8, + BT_8192E_2ANT_COEX_ALGO_PANEDR_HID = 0x9, + BT_8192E_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0xa, + BT_8192E_2ANT_COEX_ALGO_HID_A2DP = 0xb, + BT_8192E_2ANT_COEX_ALGO_MAX = 0xc +}BT_8192E_2ANT_COEX_ALGO,*PBT_8192E_2ANT_COEX_ALGO; + +typedef struct _COEX_DM_8192E_2ANT{ + // fw mechanism + u1Byte preBtDecPwrLvl; + u1Byte curBtDecPwrLvl; + u1Byte preFwDacSwingLvl; + u1Byte curFwDacSwingLvl; + BOOLEAN bCurIgnoreWlanAct; + BOOLEAN bPreIgnoreWlanAct; + u1Byte prePsTdma; + u1Byte curPsTdma; + u1Byte psTdmaPara[5]; + u1Byte psTdmaDuAdjType; + BOOLEAN bResetTdmaAdjust; + BOOLEAN bAutoTdmaAdjust; + BOOLEAN bAutoTdmaAdjustLowRssi; + BOOLEAN bPrePsTdmaOn; + BOOLEAN bCurPsTdmaOn; + BOOLEAN bPreBtAutoReport; + BOOLEAN bCurBtAutoReport; + u1Byte preLps; + u1Byte curLps; + u1Byte preRpwm; + u1Byte curRpwm; + + // sw mechanism + BOOLEAN bPreRfRxLpfShrink; + BOOLEAN bCurRfRxLpfShrink; + u4Byte btRf0x1eBackup; + BOOLEAN bPreLowPenaltyRa; + BOOLEAN bCurLowPenaltyRa; + BOOLEAN bPreDacSwingOn; + u4Byte preDacSwingLvl; + BOOLEAN bCurDacSwingOn; + u4Byte curDacSwingLvl; + BOOLEAN bPreAdcBackOff; + BOOLEAN bCurAdcBackOff; + BOOLEAN bPreAgcTableEn; + BOOLEAN bCurAgcTableEn; + u4Byte preVal0x6c0; + u4Byte curVal0x6c0; + u4Byte preVal0x6c4; + u4Byte curVal0x6c4; + u4Byte preVal0x6c8; + u4Byte curVal0x6c8; + u1Byte preVal0x6cc; + u1Byte curVal0x6cc; + BOOLEAN bLimitedDig; + + u4Byte backupArfrCnt1; // Auto Rate Fallback Retry cnt + u4Byte backupArfrCnt2; // Auto Rate Fallback Retry cnt + u2Byte backupRetryLimit; + u1Byte backupAmpduMaxTime; + + // algorithm related + u1Byte preAlgorithm; + u1Byte curAlgorithm; + u1Byte btStatus; + u1Byte wifiChnlInfo[3]; + + u1Byte preSsType; + u1Byte curSsType; + + u4Byte preRaMask; + u4Byte curRaMask; + u1Byte curRaMaskType; + u1Byte preArfrType; + u1Byte curArfrType; + u1Byte preRetryLimitType; + u1Byte curRetryLimitType; + u1Byte preAmpduTimeType; + u1Byte curAmpduTimeType; +} COEX_DM_8192E_2ANT, *PCOEX_DM_8192E_2ANT; + +typedef struct _COEX_STA_8192E_2ANT{ + BOOLEAN bBtLinkExist; + BOOLEAN bScoExist; + BOOLEAN bA2dpExist; + BOOLEAN bHidExist; + BOOLEAN bPanExist; + + BOOLEAN bUnderLps; + BOOLEAN bUnderIps; + u4Byte highPriorityTx; + u4Byte highPriorityRx; + u4Byte lowPriorityTx; + u4Byte lowPriorityRx; + u1Byte btRssi; + u1Byte preBtRssiState; + u1Byte preWifiRssiState[4]; + BOOLEAN bC2hBtInfoReqSent; + u1Byte btInfoC2h[BT_INFO_SRC_8192E_2ANT_MAX][10]; + u4Byte btInfoC2hCnt[BT_INFO_SRC_8192E_2ANT_MAX]; + BOOLEAN bC2hBtInquiryPage; + u1Byte btRetryCnt; + u1Byte btInfoExt; + u1Byte nScanAPNum; + + u4Byte nCRCOK_CCK; + u4Byte nCRCOK_11g; + u4Byte nCRCOK_11n; + u4Byte nCRCOK_11nAgg; + + u4Byte nCRCErr_CCK; + u4Byte nCRCErr_11g; + u4Byte nCRCErr_11n; + u4Byte nCRCErr_11nAgg; + + u1Byte nCoexTableType; + BOOLEAN bForceLpsOn; + + u1Byte disVerInfoCnt; +}COEX_STA_8192E_2ANT, *PCOEX_STA_8192E_2ANT; + +//=========================================== +// The following is interface which will notify coex module. +//=========================================== +VOID +EXhalbtc8192e2ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8192e2ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ); +VOID +EXhalbtc8192e2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8192e2ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8192e2ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8192e2ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8192e2ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8192e2ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8192e2ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8192e2ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ); +VOID +EXhalbtc8192e2ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8192e2ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8192e2ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ); + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8703b1Ant.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8703b1Ant.c new file mode 100644 index 000000000..766da8ac9 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8703b1Ant.c @@ -0,0 +1,5239 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//============================================================ +// Description: +// +// This file is for RTL8703B Co-exist mechanism +// +// History +// 2012/11/15 Cosa first check in. +// +//============================================================ + +//============================================================ +// include files +//============================================================ +#include "Mp_Precomp.h" + +#if WPP_SOFTWARE_TRACE +#include "HalBtc8703b1Ant.tmh" +#endif + +#if (RTL8703B_SUPPORT == 1) + +#if(BT_30_SUPPORT == 1) +//============================================================ +// Global variables, these are static variables +//============================================================ +static COEX_DM_8703B_1ANT GLCoexDm8703b1Ant; +static PCOEX_DM_8703B_1ANT pCoexDm=&GLCoexDm8703b1Ant; +static COEX_STA_8703B_1ANT GLCoexSta8703b1Ant; +static PCOEX_STA_8703B_1ANT pCoexSta=&GLCoexSta8703b1Ant; +static PSDSCAN_STA_8703B_1ANT GLPsdScan8703b1Ant; +static PPSDSCAN_STA_8703B_1ANT pPsdScan = &GLPsdScan8703b1Ant; + + +const char *const GLBtInfoSrc8703b1Ant[]={ + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; + +u4Byte GLCoexVerDate8703b1Ant=20150904; +u4Byte GLCoexVer8703b1Ant=0x04; + +//============================================================ +// local function proto type if needed +//============================================================ +//============================================================ +// local function start with halbtc8703b1ant_ +//============================================================ +u1Byte +halbtc8703b1ant_BtRssiState( + u1Byte levelNum, + u1Byte rssiThresh, + u1Byte rssiThresh1 + ) +{ + s4Byte btRssi=0; + u1Byte btRssiState=pCoexSta->preBtRssiState; + + btRssi = pCoexSta->btRssi; + + if(levelNum == 2) + { + if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW)) + { + if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT)) + { + btRssiState = BTC_RSSI_STATE_HIGH; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else + { + if(btRssi < rssiThresh) + { + btRssiState = BTC_RSSI_STATE_LOW; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + else if(levelNum == 3) + { + if(rssiThresh > rssiThresh1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Rssi thresh error!!\n")); + return pCoexSta->preBtRssiState; + } + + if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW)) + { + if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT)) + { + btRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_MEDIUM) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_MEDIUM)) + { + if(btRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT)) + { + btRssiState = BTC_RSSI_STATE_HIGH; + } + else if(btRssi < rssiThresh) + { + btRssiState = BTC_RSSI_STATE_LOW; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_MEDIUM; + } + } + else + { + if(btRssi < rssiThresh1) + { + btRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + + pCoexSta->preBtRssiState = btRssiState; + + return btRssiState; +} + +u1Byte +halbtc8703b1ant_WifiRssiState( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte index, + IN u1Byte levelNum, + IN u1Byte rssiThresh, + IN u1Byte rssiThresh1 + ) +{ + s4Byte wifiRssi=0; + u1Byte wifiRssiState=pCoexSta->preWifiRssiState[index]; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); + + if(levelNum == 2) + { + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else + { + if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + else if(levelNum == 3) + { + if(rssiThresh > rssiThresh1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi RSSI thresh error!!\n")); + return pCoexSta->preWifiRssiState[index]; + } + + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT)) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_MEDIUM) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_MEDIUM)) + { + if(wifiRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_MEDIUM; + } + } + else + { + if(wifiRssi < rssiThresh1) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + + pCoexSta->preWifiRssiState[index] = wifiRssiState; + + return wifiRssiState; +} + +VOID +halbtc8703b1ant_UpdateRaMask( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u4Byte disRateMask + ) +{ + pCoexDm->curRaMask = disRateMask; + + if( bForceExec || (pCoexDm->preRaMask != pCoexDm->curRaMask)) + { + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_UPDATE_RAMASK, &pCoexDm->curRaMask); + } + pCoexDm->preRaMask = pCoexDm->curRaMask; +} + +VOID +halbtc8703b1ant_AutoRateFallbackRetry( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + BOOLEAN bWifiUnderBMode=FALSE; + + pCoexDm->curArfrType = type; + + if( bForceExec || (pCoexDm->preArfrType != pCoexDm->curArfrType)) + { + switch(pCoexDm->curArfrType) + { + case 0: // normal mode + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x430, pCoexDm->backupArfrCnt1); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x434, pCoexDm->backupArfrCnt2); + break; + case 1: + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, &bWifiUnderBMode); + if(bWifiUnderBMode) + { + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x430, 0x0); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x434, 0x01010101); + } + else + { + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x430, 0x0); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x434, 0x04030201); + } + break; + default: + break; + } + } + + pCoexDm->preArfrType = pCoexDm->curArfrType; +} + +VOID +halbtc8703b1ant_RetryLimit( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + pCoexDm->curRetryLimitType = type; + + if( bForceExec || (pCoexDm->preRetryLimitType != pCoexDm->curRetryLimitType)) + { + switch(pCoexDm->curRetryLimitType) + { + case 0: // normal mode + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x42a, pCoexDm->backupRetryLimit); + break; + case 1: // retry limit=8 + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x42a, 0x0808); + break; + default: + break; + } + } + + pCoexDm->preRetryLimitType = pCoexDm->curRetryLimitType; +} + +VOID +halbtc8703b1ant_AmpduMaxTime( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + pCoexDm->curAmpduTimeType = type; + + if( bForceExec || (pCoexDm->preAmpduTimeType != pCoexDm->curAmpduTimeType)) + { + switch(pCoexDm->curAmpduTimeType) + { + case 0: // normal mode + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x456, pCoexDm->backupAmpduMaxTime); + break; + case 1: // AMPDU timw = 0x38 * 32us + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x456, 0x38); + break; + default: + break; + } + } + + pCoexDm->preAmpduTimeType = pCoexDm->curAmpduTimeType; +} + +VOID +halbtc8703b1ant_LimitedTx( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte raMaskType, + IN u1Byte arfrType, + IN u1Byte retryLimitType, + IN u1Byte ampduTimeType + ) +{ + switch(raMaskType) + { + case 0: // normal mode + halbtc8703b1ant_UpdateRaMask(pBtCoexist, bForceExec, 0x0); + break; + case 1: // disable cck 1/2 + halbtc8703b1ant_UpdateRaMask(pBtCoexist, bForceExec, 0x00000003); + break; + case 2: // disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 + halbtc8703b1ant_UpdateRaMask(pBtCoexist, bForceExec, 0x0001f1f7); + break; + default: + break; + } + + halbtc8703b1ant_AutoRateFallbackRetry(pBtCoexist, bForceExec, arfrType); + halbtc8703b1ant_RetryLimit(pBtCoexist, bForceExec, retryLimitType); + halbtc8703b1ant_AmpduMaxTime(pBtCoexist, bForceExec, ampduTimeType); +} + +VOID +halbtc8703b1ant_LimitedRx( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bRejApAggPkt, + IN BOOLEAN bBtCtrlAggBufSize, + IN u1Byte aggBufSize + ) +{ + BOOLEAN bRejectRxAgg=bRejApAggPkt; + BOOLEAN bBtCtrlRxAggSize=bBtCtrlAggBufSize; + u1Byte rxAggSize=aggBufSize; + + //============================================ + // Rx Aggregation related setting + //============================================ + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, &bRejectRxAgg); + // decide BT control aggregation buf size or not + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, &bBtCtrlRxAggSize); + // aggregation buf size, only work when BT control Rx aggregation size. + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_AGG_BUF_SIZE, &rxAggSize); + // real update aggregation setting + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); + + +} + +VOID +halbtc8703b1ant_QueryBtInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + pCoexSta->bC2hBtInfoReqSent = TRUE; + + H2C_Parameter[0] |= BIT0; // trigger + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Query Bt Info, FW write 0x61=0x%x\n", + H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x61, 1, H2C_Parameter); +} + +VOID +halbtc8703b1ant_MonitorBtCtr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte regHPTxRx, regLPTxRx, u4Tmp, u4Tmp1; + u4Byte regHPTx=0, regHPRx=0, regLPTx=0, regLPRx=0; + u1Byte u1Tmp, u1Tmp1; + s4Byte wifiRssi; + static u1Byte NumOfBtCounterChk = 0; + + //to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS + //if (! (pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x76e) & 0x8) ) + + if (pCoexSta->bUnderIps) + { + //pCoexSta->highPriorityTx = 65535; + //pCoexSta->highPriorityRx = 65535; + //pCoexSta->lowPriorityTx = 65535; + //pCoexSta->lowPriorityRx = 65535; + //return; + } + + regHPTxRx = 0x770; + regLPTxRx = 0x774; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regHPTxRx); + regHPTx = u4Tmp & bMaskLWord; + regHPRx = (u4Tmp & bMaskHWord)>>16; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regLPTxRx); + regLPTx = u4Tmp & bMaskLWord; + regLPRx = (u4Tmp & bMaskHWord)>>16; + + pCoexSta->highPriorityTx = regHPTx; + pCoexSta->highPriorityRx = regHPRx; + pCoexSta->lowPriorityTx = regLPTx; + pCoexSta->lowPriorityRx = regLPRx; + + if( (pCoexSta->lowPriorityTx > 1150) && (!pCoexSta->bC2hBtInquiryPage)) + pCoexSta->popEventCnt++; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n", + regHPRx, regHPTx, regLPRx, regLPTx)); + + // reset counter + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0xc); + + if ((regHPTx == 0) && (regHPRx ==0) && (regLPTx == 0) && (regLPRx == 0)) + { + NumOfBtCounterChk++; + if (NumOfBtCounterChk >= 3) + { + halbtc8703b1ant_QueryBtInfo(pBtCoexist); + NumOfBtCounterChk = 0; + } + } +} + + +VOID +halbtc8703b1ant_MonitorWiFiCtr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte u4Tmp; + u2Byte u2Tmp[3]; + s4Byte wifiRssi=0; + BOOLEAN bWifiBusy = FALSE, bWifiUnderBMode = FALSE; + static u1Byte nCCKLockCounter = 0; + u4Byte TotalCnt; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, &bWifiUnderBMode); + + if (pCoexSta->bUnderIps) + { + pCoexSta->nCRCOK_CCK = 0; + pCoexSta->nCRCOK_11g = 0; + pCoexSta->nCRCOK_11n = 0; + pCoexSta->nCRCOK_11nAgg = 0; + + pCoexSta->nCRCErr_CCK = 0; + pCoexSta->nCRCErr_11g = 0; + pCoexSta->nCRCErr_11n = 0; + pCoexSta->nCRCErr_11nAgg = 0; + } + else + { + pCoexSta->nCRCOK_CCK = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xf88); + pCoexSta->nCRCOK_11g = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf94); + pCoexSta->nCRCOK_11n = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf90); + pCoexSta->nCRCOK_11nAgg= pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xfb8); + + pCoexSta->nCRCErr_CCK = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xf84); + pCoexSta->nCRCErr_11g = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf96); + pCoexSta->nCRCErr_11n = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf92); + pCoexSta->nCRCErr_11nAgg = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xfba); + } + + + //reset counter + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xf16, 0x1, 0x1); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xf16, 0x1, 0x0); + + if ( (bWifiBusy) && (wifiRssi >= 30) && (!bWifiUnderBMode)) + { + TotalCnt = pCoexSta->nCRCOK_CCK + pCoexSta->nCRCOK_11g + pCoexSta->nCRCOK_11n + + pCoexSta->nCRCOK_11nAgg; + + if ( (pCoexDm->btStatus == BT_8703B_1ANT_BT_STATUS_ACL_BUSY) || + (pCoexDm->btStatus == BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY) || + (pCoexDm->btStatus == BT_8703B_1ANT_BT_STATUS_SCO_BUSY) ) + { + if (pCoexSta->nCRCOK_CCK >(TotalCnt -pCoexSta->nCRCOK_CCK)) + { + if (nCCKLockCounter < 3) + nCCKLockCounter++; + } + else + { + if (nCCKLockCounter > 0) + nCCKLockCounter--; + } + + } + else + { + if (nCCKLockCounter > 0) + nCCKLockCounter--; + } + } + else + { + if (nCCKLockCounter > 0) + nCCKLockCounter--; + } + + if (!pCoexSta->bPreCCKLock) + { + + if (nCCKLockCounter >= 3) + pCoexSta->bCCKLock = TRUE; + else + pCoexSta->bCCKLock = FALSE; + } + else + { + if (nCCKLockCounter == 0) + pCoexSta->bCCKLock = FALSE; + else + pCoexSta->bCCKLock = TRUE; + } + + if (pCoexSta->bCCKLock) + pCoexSta->bCCKEverLock = TRUE; + + pCoexSta->bPreCCKLock = pCoexSta->bCCKLock; + + +} + +BOOLEAN +halbtc8703b1ant_IsWifiStatusChanged( + IN PBTC_COEXIST pBtCoexist + ) +{ + static BOOLEAN bPreWifiBusy=FALSE, bPreUnder4way=FALSE, bPreBtHsOn=FALSE; + BOOLEAN bWifiBusy=FALSE, bUnder4way=FALSE, bBtHsOn=FALSE; + BOOLEAN bWifiConnected=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &bUnder4way); + + if(bWifiConnected) + { + if(bWifiBusy != bPreWifiBusy) + { + bPreWifiBusy = bWifiBusy; + return TRUE; + } + if(bUnder4way != bPreUnder4way) + { + bPreUnder4way = bUnder4way; + return TRUE; + } + if(bBtHsOn != bPreBtHsOn) + { + bPreBtHsOn = bBtHsOn; + return TRUE; + } + } + + return FALSE; +} + +VOID +halbtc8703b1ant_UpdateBtLinkInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bBtHsOn=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + pBtLinkInfo->bBtLinkExist = pCoexSta->bBtLinkExist; + pBtLinkInfo->bScoExist = pCoexSta->bScoExist; + pBtLinkInfo->bA2dpExist = pCoexSta->bA2dpExist; + pBtLinkInfo->bPanExist = pCoexSta->bPanExist; + pBtLinkInfo->bHidExist = pCoexSta->bHidExist; + pBtLinkInfo->bBtHiPriLinkExist = pCoexSta->bBtHiPriLinkExist; + + // work around for HS mode. + if(bBtHsOn) + { + pBtLinkInfo->bPanExist = TRUE; + pBtLinkInfo->bBtLinkExist = TRUE; + } + + // check if Sco only + if( pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bScoOnly = TRUE; + else + pBtLinkInfo->bScoOnly = FALSE; + + // check if A2dp only + if( !pBtLinkInfo->bScoExist && + pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bA2dpOnly = TRUE; + else + pBtLinkInfo->bA2dpOnly = FALSE; + + // check if Pan only + if( !pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bPanOnly = TRUE; + else + pBtLinkInfo->bPanOnly = FALSE; + + // check if Hid only + if( !pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + pBtLinkInfo->bHidExist ) + pBtLinkInfo->bHidOnly = TRUE; + else + pBtLinkInfo->bHidOnly = FALSE; +} + +VOID +halbtc8703b1ant_UpdateWifiChannelInfo( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + u1Byte H2C_Parameter[3] ={0}; + u4Byte wifiBw; + u1Byte wifiCentralChnl; + BOOLEAN bWifiUnderBMode = FALSE; + + // only 2.4G we need to inform bt the chnl mask + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, &wifiCentralChnl); + if( (BTC_MEDIA_CONNECT == type) && + (wifiCentralChnl <= 14) ) + { + H2C_Parameter[0] = 0x1; //enable BT AFH skip WL channel for 8703b because BT Rx LO interference + //H2C_Parameter[0] = 0x0; + H2C_Parameter[1] = wifiCentralChnl; + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + H2C_Parameter[2] = 0x30; + else + H2C_Parameter[2] = 0x20; + } + + pCoexDm->wifiChnlInfo[0] = H2C_Parameter[0]; + pCoexDm->wifiChnlInfo[1] = H2C_Parameter[1]; + pCoexDm->wifiChnlInfo[2] = H2C_Parameter[2]; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x66=0x%x\n", + H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x66, 3, H2C_Parameter); + +} + +u1Byte +halbtc8703b1ant_ActionAlgorithm( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bBtHsOn=FALSE; + u1Byte algorithm=BT_8703B_1ANT_COEX_ALGO_UNDEFINED; + u1Byte numOfDiffProfile=0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + if(!pBtLinkInfo->bBtLinkExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], No BT link exists!!!\n")); + return algorithm; + } + + if(pBtLinkInfo->bScoExist) + numOfDiffProfile++; + if(pBtLinkInfo->bHidExist) + numOfDiffProfile++; + if(pBtLinkInfo->bPanExist) + numOfDiffProfile++; + if(pBtLinkInfo->bA2dpExist) + numOfDiffProfile++; + + if(numOfDiffProfile == 1) + { + if(pBtLinkInfo->bScoExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO only\n")); + algorithm = BT_8703B_1ANT_COEX_ALGO_SCO; + } + else + { + if(pBtLinkInfo->bHidExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID only\n")); + algorithm = BT_8703B_1ANT_COEX_ALGO_HID; + } + else if(pBtLinkInfo->bA2dpExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = A2DP only\n")); + algorithm = BT_8703B_1ANT_COEX_ALGO_A2DP; + } + else if(pBtLinkInfo->bPanExist) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = PAN(HS) only\n")); + algorithm = BT_8703B_1ANT_COEX_ALGO_PANHS; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = PAN(EDR) only\n")); + algorithm = BT_8703B_1ANT_COEX_ALGO_PANEDR; + } + } + } + } + else if(numOfDiffProfile == 2) + { + if(pBtLinkInfo->bScoExist) + { + if(pBtLinkInfo->bHidExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + HID\n")); + algorithm = BT_8703B_1ANT_COEX_ALGO_HID; + } + else if(pBtLinkInfo->bA2dpExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + A2DP ==> SCO\n")); + algorithm = BT_8703B_1ANT_COEX_ALGO_SCO; + } + else if(pBtLinkInfo->bPanExist) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + PAN(HS)\n")); + algorithm = BT_8703B_1ANT_COEX_ALGO_SCO; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + PAN(EDR)\n")); + algorithm = BT_8703B_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } + else + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bA2dpExist ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID + A2DP\n")); + algorithm = BT_8703B_1ANT_COEX_ALGO_HID_A2DP; + } + else if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID + PAN(HS)\n")); + algorithm = BT_8703B_1ANT_COEX_ALGO_HID_A2DP; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID + PAN(EDR)\n")); + algorithm = BT_8703B_1ANT_COEX_ALGO_PANEDR_HID; + } + } + else if( pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = A2DP + PAN(HS)\n")); + algorithm = BT_8703B_1ANT_COEX_ALGO_A2DP_PANHS; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = A2DP + PAN(EDR)\n")); + algorithm = BT_8703B_1ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } + } + else if(numOfDiffProfile == 3) + { + if(pBtLinkInfo->bScoExist) + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bA2dpExist ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n")); + algorithm = BT_8703B_1ANT_COEX_ALGO_HID; + } + else if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + HID + PAN(HS)\n")); + algorithm = BT_8703B_1ANT_COEX_ALGO_HID_A2DP; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n")); + algorithm = BT_8703B_1ANT_COEX_ALGO_PANEDR_HID; + } + } + else if( pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n")); + algorithm = BT_8703B_1ANT_COEX_ALGO_SCO; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n")); + algorithm = BT_8703B_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } + else + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n")); + algorithm = BT_8703B_1ANT_COEX_ALGO_HID_A2DP; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n")); + algorithm = BT_8703B_1ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } + else if(numOfDiffProfile >= 3) + { + if(pBtLinkInfo->bScoExist) + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n")); + + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n")); + algorithm = BT_8703B_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } + } + + return algorithm; +} + +VOID +halbtc8703b1ant_SetBtAutoReport( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bEnableAutoReport + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + H2C_Parameter[0] = 0; + + if(bEnableAutoReport) + { + H2C_Parameter[0] |= BIT0; + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], BT FW auto report : %s, FW write 0x68=0x%x\n", + (bEnableAutoReport? "Enabled!!":"Disabled!!"), H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x68, 1, H2C_Parameter); +} + +VOID +halbtc8703b1ant_BtAutoReport( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bEnableAutoReport + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s BT Auto report = %s\n", + (bForceExec? "force to":""), ((bEnableAutoReport)? "Enabled":"Disabled"))); + pCoexDm->bCurBtAutoReport = bEnableAutoReport; + + if(!bForceExec) + { + if(pCoexDm->bPreBtAutoReport == pCoexDm->bCurBtAutoReport) + return; + } + halbtc8703b1ant_SetBtAutoReport(pBtCoexist, pCoexDm->bCurBtAutoReport); + + pCoexDm->bPreBtAutoReport = pCoexDm->bCurBtAutoReport; +} + +VOID halbtc8703b1ant_WriteScoreBoard( + IN PBTC_COEXIST pBtCoexist, + IN u2Byte scoreboardval + ) +{ + u2Byte val; + + val = (scoreboardval & 0x7fff) | 0x8000; + + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0xaa, val); + +#if 0 + u1Byte H2C_Parameter[3] ={0,0,0}; + + + // write "Set Status" + H2C_Parameter[0] = 0x2; + + // write score board 15-bit value to H2C parameter + H2C_Parameter[1] = scoreboardval & 0xff; + H2C_Parameter[2] = (scoreboardval & 0x7f00) >> 8; + + // Set Interrupt to BT + H2C_Parameter[2] = H2C_Parameter[2] | 0x80; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Write BT Scoreboard: H2C 0x71[1:0]= %02x%02x\n", + H2C_Parameter[2], H2C_Parameter[1])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x71, 3, H2C_Parameter); + +#endif +} + +VOID halbtc8703b1ant_ReadScoreBoard( + IN PBTC_COEXIST pBtCoexist, + IN u2Byte* uScoreBoardVal + ) +{ + + *uScoreBoardVal = (pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xaa)) & 0x7fff; + + + +#if 0 + u1Byte H2C_Parameter[3] ={0,0,0}; + + // write "Get Status" + H2C_Parameter[0] = 0x1; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Read BT Scoreboard!!\n")); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x71, 3, H2C_Parameter); + + //the BT Scoreboard will be returned by C2H from EXhalbtc8703b1ant_ScoreBoardStatusNotify() +#endif +} + +VOID halbtc8703b1ant_PostActiveStateToBT( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiActive + ) +{ + + if(bWifiActive) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Post WL = Active in Scoreboard!!\n")); + halbtc8703b1ant_WriteScoreBoard(pBtCoexist, 0x0001); + } + else + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Post WL = Non-Active in Scoreboard!!\n")); + halbtc8703b1ant_WriteScoreBoard(pBtCoexist, 0x0000); + } + + // The BT should set "No Shunt-down" mode if WL = Active for BT Synthesizer on/off interference WL Lo issue at 8703b b-cut. + +} + +VOID +halbtc8703b1ant_SetSwPenaltyTxRateAdaptive( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bLowPenaltyRa + ) +{ + u1Byte H2C_Parameter[6] ={0}; + + H2C_Parameter[0] = 0x6; // opCode, 0x6= Retry_Penalty + + if(bLowPenaltyRa) + { + H2C_Parameter[1] |= BIT0; + H2C_Parameter[2] = 0x00; //normal rate except MCS7/6/5, OFDM54/48/36 + H2C_Parameter[3] = 0xf7; //MCS7 or OFDM54 + H2C_Parameter[4] = 0xf8; //MCS6 or OFDM48 + H2C_Parameter[5] = 0xf9; //MCS5 or OFDM36 + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set WiFi Low-Penalty Retry: %s", + (bLowPenaltyRa? "ON!!":"OFF!!") )); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x69, 6, H2C_Parameter); +} + +VOID +halbtc8703b1ant_LowPenaltyRa( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bLowPenaltyRa + ) +{ + pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa; + + if(!bForceExec) + { + if(pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa) + return; + } + halbtc8703b1ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa); + + pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa; +} + +u4Byte +halbtc8703b1ant_LTECoex_InDirectReadReg( +IN PBTC_COEXIST pBtCoexist, +IN u2Byte RegAddr +) +{ + u4Byte j =0; + + + //wait for ready bit before access 0x7c0 + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x7c0, 0x800F0000|RegAddr); + + do + { + j++; + }while( ((pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x7c3) & BIT5) ==0) && (j fBtcRead4Byte(pBtCoexist, 0x7c8)); //get read data + +} + +VOID +halbtc8703b1ant_LTECoex_InDirectWriteReg( +IN PBTC_COEXIST pBtCoexist, +IN u2Byte RegAddr, +IN u4Byte BitMask, +IN u4Byte RegValue +) +{ + u4Byte val, i=0, j=0, bitpos = 0; + + + if (BitMask == 0x0) + return; + if (BitMask == 0xffffffff) + { + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x7c4, RegValue); //put write data + + //wait for ready bit before access 0x7c0 + do + { + j++; + }while( ((pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x7c3) & BIT5) ==0) && (j fBtcWrite4Byte(pBtCoexist, 0x7c0, 0xc00F0000|RegAddr); + } + else + { + for(i=0; i<=31; i++) + { + if ( ((BitMask >> i) & 0x1) == 0x1) + { + bitpos = i; + break; + } + } + + //read back register value before write + val = halbtc8703b1ant_LTECoex_InDirectReadReg(pBtCoexist, RegAddr); + val = (val & (~BitMask)) | (RegValue << bitpos); + + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x7c4, val); //put write data + + //wait for ready bit before access 0x7c0 + do + { + j++; + }while( ((pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x7c3) & BIT5) ==0) && (j fBtcWrite4Byte(pBtCoexist, 0x7c0, 0xc00F0000|RegAddr); + + } + +} + +void +halbtc8703b1ant_LTECoex_Enable( +IN PBTC_COEXIST pBtCoexist, +IN BOOLEAN bEnable +) +{ + u1Byte val; + + val = (bEnable)? 1 : 0; + halbtc8703b1ant_LTECoex_InDirectWriteReg(pBtCoexist, 0x38, 0x80, val); //0x38[7] + +} + +void +halbtc8703b1ant_LTECoex_PathControlOwner( +IN PBTC_COEXIST pBtCoexist, +IN BOOLEAN bWiFiControl +) +{ + u1Byte val; + + val = (bWiFiControl)? 1 : 0; + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x73, 0x4, val); //0x70[26] + +} + +void +halbtc8703b1ant_LTECoex_Set_GNT_BT( +IN PBTC_COEXIST pBtCoexist, +IN u1Byte nControlBlock, +IN BOOLEAN bSWControl, +IN u1Byte nState +) +{ + u4Byte val=0, BitMask; + + nState = nState & 0x1; + val = (bSWControl)? ((nState<<1) | 0x1) : 0; + + switch(nControlBlock) + { + case BT_8703B_1ANT_GNT_BLOCK_RFC_BB: + default: + BitMask = 0xc000; + halbtc8703b1ant_LTECoex_InDirectWriteReg(pBtCoexist, 0x38, BitMask, val); // 0x38[15:14] + BitMask = 0x0c00; + halbtc8703b1ant_LTECoex_InDirectWriteReg(pBtCoexist, 0x38, BitMask, val); // 0x38[11:10] + break; + case BT_8703B_1ANT_GNT_BLOCK_RFC: + BitMask = 0xc000; + halbtc8703b1ant_LTECoex_InDirectWriteReg(pBtCoexist, 0x38, BitMask, val); // 0x38[15:14] + break; + case BT_8703B_1ANT_GNT_BLOCK_BB: + BitMask = 0x0c00; + halbtc8703b1ant_LTECoex_InDirectWriteReg(pBtCoexist, 0x38, BitMask, val); // 0x38[11:10] + break; + + } + +} + +void +halbtc8703b1ant_LTECoex_Set_GNT_WL( +IN PBTC_COEXIST pBtCoexist, +IN u1Byte nControlBlock, +IN BOOLEAN bSWControl, +IN u1Byte nState +) +{ + u4Byte val=0, BitMask; + + nState = nState & 0x1; + val = (bSWControl)? ((nState<<1) | 0x1) : 0; + + switch(nControlBlock) + { + case BT_8703B_1ANT_GNT_BLOCK_RFC_BB: + default: + BitMask = 0x3000; + halbtc8703b1ant_LTECoex_InDirectWriteReg(pBtCoexist, 0x38, BitMask, val); // 0x38[13:12] + BitMask = 0x0300; + halbtc8703b1ant_LTECoex_InDirectWriteReg(pBtCoexist, 0x38, BitMask, val); // 0x38[9:8] + break; + case BT_8703B_1ANT_GNT_BLOCK_RFC: + BitMask = 0x3000; + halbtc8703b1ant_LTECoex_InDirectWriteReg(pBtCoexist, 0x38, BitMask, val); // 0x38[13:12] + break; + case BT_8703B_1ANT_GNT_BLOCK_BB: + BitMask = 0x0300; + halbtc8703b1ant_LTECoex_InDirectWriteReg(pBtCoexist, 0x38, BitMask, val); // 0x38[9:8] + break; + + } + +} + +void +halbtc8703b1ant_LTECoex_Set_CoexTable( +IN PBTC_COEXIST pBtCoexist, +IN u1Byte nTableType, +IN u2Byte nTableContent +) +{ + u2Byte RegAddr = 0x0000; + + switch(nTableType) + { + case BT_8703B_1ANT_CTT_WL_VS_LTE: + RegAddr = 0xa0; + break; + case BT_8703B_1ANT_CTT_BT_VS_LTE: + RegAddr = 0xa4; + break; + } + + if (RegAddr != 0x0000) + halbtc8703b1ant_LTECoex_InDirectWriteReg(pBtCoexist, RegAddr, 0xffff, nTableContent); // 0xa0[15:0] or 0xa4[15:0] + + +} + + +void +halbtc8703b1ant_LTECoex_Set_BreakTable( +IN PBTC_COEXIST pBtCoexist, +IN u1Byte nTableType, +IN u1Byte nTableContent +) +{ + u2Byte RegAddr = 0x0000; + + switch(nTableType) + { + case BT_8703B_1ANT_LBTT_WL_BREAK_LTE: + RegAddr = 0xa8; + break; + case BT_8703B_1ANT_LBTT_BT_BREAK_LTE: + RegAddr = 0xac; + break; + case BT_8703B_1ANT_LBTT_LTE_BREAK_WL: + RegAddr = 0xb0; + break; + case BT_8703B_1ANT_LBTT_LTE_BREAK_BT: + RegAddr = 0xb4; + break; + } + + if (RegAddr != 0x0000) + halbtc8703b1ant_LTECoex_InDirectWriteReg(pBtCoexist, RegAddr, 0xff, nTableContent); // 0xa8[15:0] or 0xb4[15:0] + + +} + +VOID +halbtc8703b1ant_SetCoexTable( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte val0x6c0, + IN u4Byte val0x6c4, + IN u4Byte val0x6c8, + IN u1Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c0=0x%x\n", val0x6c0)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c0, val0x6c0); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c4=0x%x\n", val0x6c4)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c4, val0x6c4); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, val0x6c8); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc)); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cc, val0x6cc); +} + +VOID +halbtc8703b1ant_CoexTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u4Byte val0x6c0, + IN u4Byte val0x6c4, + IN u4Byte val0x6c8, + IN u1Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s write Coex Table 0x6c0=0x%x, 0x6c4=0x%x, 0x6cc=0x%x\n", + (bForceExec? "force to":""), val0x6c0, val0x6c4, val0x6cc)); + pCoexDm->curVal0x6c0 = val0x6c0; + pCoexDm->curVal0x6c4 = val0x6c4; + pCoexDm->curVal0x6c8 = val0x6c8; + pCoexDm->curVal0x6cc = val0x6cc; + + if(!bForceExec) + { + if( (pCoexDm->preVal0x6c0 == pCoexDm->curVal0x6c0) && + (pCoexDm->preVal0x6c4 == pCoexDm->curVal0x6c4) && + (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) && + (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) ) + return; + } + halbtc8703b1ant_SetCoexTable(pBtCoexist, val0x6c0, val0x6c4, val0x6c8, val0x6cc); + + pCoexDm->preVal0x6c0 = pCoexDm->curVal0x6c0; + pCoexDm->preVal0x6c4 = pCoexDm->curVal0x6c4; + pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8; + pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc; +} + +VOID +halbtc8703b1ant_CoexTableWithType( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + + u4Byte nBreakTable; + u1Byte nSelectTable; + + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], ********** CoexTable(%d) **********\n", type)); + + pCoexSta->nCoexTableType = type; + + if (pCoexSta->bConCurrentRxModeOn == TRUE) + { + nBreakTable = 0xf0ffffff; //set WL hi-pri can break BT + nSelectTable = 0xb; //set Tx response = Hi-Pri (ex: Transmitting ACK,BA,CTS) + } + else + { + nBreakTable = 0xffffff; + nSelectTable = 0x3; + } + + switch(type) + { + case 0: + halbtc8703b1ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x55555555, nBreakTable, nSelectTable); + break; + case 1: + halbtc8703b1ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x5a5a5a5a, nBreakTable, nSelectTable); + break; + case 2: + halbtc8703b1ant_CoexTable(pBtCoexist, bForceExec, 0xaa5a5a5a, 0xaa5a5a5a, nBreakTable, nSelectTable); + break; + case 3: + halbtc8703b1ant_CoexTable(pBtCoexist, bForceExec, 0xaa555555, 0xaa5a5a5a, nBreakTable, nSelectTable); + break; + case 4: + //if ( (pCoexSta->bCCKEverLock) && (pCoexSta->nScanAPNum <= 5) ) + // halbtc8703b1ant_CoexTable(pBtCoexist, bForceExec, 0xaa555555, 0xaaaa5a5a, nBreakTable, nSelectTable); + //else + halbtc8703b1ant_CoexTable(pBtCoexist, bForceExec, 0xaa555555, 0xaa5a5a5a, nBreakTable, nSelectTable); + break; + case 5: + //if ( (pCoexSta->bCCKEverLock) && (pCoexSta->nScanAPNum <= 5) ) + // halbtc8703b1ant_CoexTable(pBtCoexist, bForceExec, 0xaa555555, 0xaaaa5a5a, nBreakTable, nSelectTable); + //else + halbtc8703b1ant_CoexTable(pBtCoexist, bForceExec, 0x5a5a5a5a, 0x5a5a5a5a, nBreakTable, nSelectTable); + break; + case 6: + halbtc8703b1ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0xaaaaaaaa, nBreakTable, nSelectTable); + break; + case 7: + halbtc8703b1ant_CoexTable(pBtCoexist, bForceExec, 0xaaaaaaaa, 0xaaaaaaaa, nBreakTable, nSelectTable); + break; + case 8: + halbtc8703b1ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, nBreakTable, nSelectTable); + break; + case 9: + halbtc8703b1ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, nBreakTable, nSelectTable); + break; + case 10: + halbtc8703b1ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, nBreakTable, nSelectTable); + break; + case 11: + halbtc8703b1ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, nBreakTable, nSelectTable); + break; + case 12: + halbtc8703b1ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, nBreakTable, nSelectTable); + break; + case 13: + halbtc8703b1ant_CoexTable(pBtCoexist, bForceExec, 0x5fff5fff, 0xaaaaaaaa, nBreakTable, nSelectTable); + break; + case 14: + halbtc8703b1ant_CoexTable(pBtCoexist, bForceExec, 0x5fff5fff, 0x5ada5ada, nBreakTable, nSelectTable); + break; + case 15: + halbtc8703b1ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0xaaaaaaaa, nBreakTable, nSelectTable); + break; + default: + break; + } +} + +VOID +halbtc8703b1ant_SetFwIgnoreWlanAct( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bEnable + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + if(bEnable) + { + H2C_Parameter[0] |= BIT0; // function enable + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set FW for BT Ignore Wlan_Act, FW write 0x63=0x%x\n", + H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x63, 1, H2C_Parameter); +} + +VOID +halbtc8703b1ant_IgnoreWlanAct( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bEnable + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Ignore WlanAct %s\n", + (bForceExec? "force to":""), (bEnable? "ON":"OFF"))); + pCoexDm->bCurIgnoreWlanAct = bEnable; + + if(!bForceExec) + { + if(pCoexDm->bPreIgnoreWlanAct == pCoexDm->bCurIgnoreWlanAct) + return; + } + halbtc8703b1ant_SetFwIgnoreWlanAct(pBtCoexist, bEnable); + + pCoexDm->bPreIgnoreWlanAct = pCoexDm->bCurIgnoreWlanAct; +} + +VOID +halbtc8703b1ant_SetLpsRpwm( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + u1Byte lps=lpsVal; + u1Byte rpwm=rpwmVal; + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_LPS_VAL, &lps); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RPWM_VAL, &rpwm); +} + +VOID +halbtc8703b1ant_LpsRpwm( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + BOOLEAN bForceExecPwrCmd=FALSE; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s set lps/rpwm=0x%x/0x%x \n", + (bForceExec? "force to":""), lpsVal, rpwmVal)); + pCoexDm->curLps = lpsVal; + pCoexDm->curRpwm = rpwmVal; + + if(!bForceExec) + { + if( (pCoexDm->preLps == pCoexDm->curLps) && + (pCoexDm->preRpwm == pCoexDm->curRpwm) ) + { + return; + } + } + halbtc8703b1ant_SetLpsRpwm(pBtCoexist, lpsVal, rpwmVal); + + pCoexDm->preLps = pCoexDm->curLps; + pCoexDm->preRpwm = pCoexDm->curRpwm; +} + +VOID +halbtc8703b1ant_SwMechanism( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bLowPenaltyRA + ) +{ + halbtc8703b1ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, bLowPenaltyRA); +} + +VOID +halbtc8703b1ant_SetAntPath( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte antPosType, + IN BOOLEAN bForceExec, + IN BOOLEAN bInitHwCfg, + IN BOOLEAN bWifiOff + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + u4Byte fwVer=0, u4Tmp=0, cntBtCalChk=0; + BOOLEAN bPgExtSwitch=FALSE; + BOOLEAN bUseExtSwitch=FALSE; + BOOLEAN bIsInMpMode = FALSE; + u1Byte H2C_Parameter[2] ={0}, u1Tmp = 0; + u4Byte u4Tmp1=0, u4Tmp2=0; + + pCoexDm->curAntPosType = antPosType; + +#if 1 + u4Tmp1 = halbtc8703b1ant_LTECoex_InDirectReadReg(pBtCoexist, 0x38); + u4Tmp2 = halbtc8703b1ant_LTECoex_InDirectReadReg(pBtCoexist, 0x54); + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x73); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ********** (Before Setup) 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n", u1Tmp, u4Tmp1, u4Tmp2)); +#endif + + if(bInitHwCfg) + { + //Disable LTE Coex Function in WiFi side (this should be on if LTE coex is required) + halbtc8703b1ant_LTECoex_Enable(pBtCoexist, 0x0); + + //GNT_WL_LTE always = 1 (this should be config if LTE coex is required) + halbtc8703b1ant_LTECoex_Set_CoexTable(pBtCoexist, BT_8703B_1ANT_CTT_WL_VS_LTE, 0xffff); + + //GNT_BT_LTE always = 1 (this should be config if LTE coex is required) + halbtc8703b1ant_LTECoex_Set_CoexTable(pBtCoexist, BT_8703B_1ANT_CTT_BT_VS_LTE, 0xffff); + + // Wait If BT IQK running, because Path control owner is at BT during BT IQK (setup by WiFi firmware) + while(cntBtCalChk <= 20) + { + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x49d); + cntBtCalChk++; + if(u1Tmp & BIT0) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n", cntBtCalChk)); + delay_ms(50); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n", cntBtCalChk)); + break; + } + } + + //set Path control owner to WL at initial step + halbtc8703b1ant_LTECoex_PathControlOwner(pBtCoexist, BT_8703B_1ANT_PCO_WLSIDE); + } + else if(bWifiOff) + { + //Disable LTE Coex Function in WiFi side + halbtc8703b1ant_LTECoex_Enable(pBtCoexist, 0x0); + + //if MP mode + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_IS_IN_MP_MODE, &bIsInMpMode); + if(bIsInMpMode) + halbtc8703b1ant_LTECoex_PathControlOwner(pBtCoexist, BT_8703B_1ANT_PCO_WLSIDE); //set Path control owner to WiFI + else + halbtc8703b1ant_LTECoex_PathControlOwner(pBtCoexist, BT_8703B_1ANT_PCO_BTSIDE);//set Path control owner to BT + } + else + { + halbtc8703b1ant_LTECoex_PathControlOwner(pBtCoexist, BT_8703B_1ANT_PCO_WLSIDE); + } + + + if(bForceExec || (pCoexDm->curAntPosType != pCoexDm->preAntPosType) || bInitHwCfg || bWifiOff) + { + // internal switch setting + switch(antPosType) + { + case BTC_ANT_PATH_WIFI: + // set GNT_BT to low + halbtc8703b1ant_LTECoex_Set_GNT_BT(pBtCoexist, BT_8703B_1ANT_GNT_BLOCK_RFC_BB, BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, BT_8703B_1ANT_SIG_STA_SET_TO_LOW); + //Set GNT_WL to high + halbtc8703b1ant_LTECoex_Set_GNT_WL(pBtCoexist, BT_8703B_1ANT_GNT_BLOCK_RFC_BB, BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, BT_8703B_1ANT_SIG_STA_SET_TO_HIGH); + break; + case BTC_ANT_PATH_BT: + // set GNT_BT to high + halbtc8703b1ant_LTECoex_Set_GNT_BT(pBtCoexist, BT_8703B_1ANT_GNT_BLOCK_RFC_BB, BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, BT_8703B_1ANT_SIG_STA_SET_TO_HIGH); + //Set GNT_WL to low + halbtc8703b1ant_LTECoex_Set_GNT_WL(pBtCoexist, BT_8703B_1ANT_GNT_BLOCK_RFC_BB, BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, BT_8703B_1ANT_SIG_STA_SET_TO_LOW); + break; + default: + case BTC_ANT_PATH_PTA: + // set GNT_BT to PTA + halbtc8703b1ant_LTECoex_Set_GNT_BT(pBtCoexist, BT_8703B_1ANT_GNT_BLOCK_RFC_BB, BT_8703B_1ANT_GNT_TYPE_CTRL_BY_PTA, BT_8703B_1ANT_SIG_STA_SET_BY_HW); + //Set GNT_WL to PTA + halbtc8703b1ant_LTECoex_Set_GNT_WL(pBtCoexist, BT_8703B_1ANT_GNT_BLOCK_RFC_BB, BT_8703B_1ANT_GNT_TYPE_CTRL_BY_PTA, BT_8703B_1ANT_SIG_STA_SET_BY_HW); + break; + } + } + +#if 1 + u4Tmp1 = halbtc8703b1ant_LTECoex_InDirectReadReg(pBtCoexist, 0x38); + u4Tmp2 = halbtc8703b1ant_LTECoex_InDirectReadReg(pBtCoexist, 0x54); + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x73); + + if(bInitHwCfg) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ********** (After Init) 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n", u1Tmp, u4Tmp1, u4Tmp2)); + } + else if (bWifiOff) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ********** (After WiFi off) 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n", u1Tmp, u4Tmp1, u4Tmp2)); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ********** (After Run time) 0x73 = 0x%x, 0x38= 0x%x, 0x54= 0x%x**********\n", u1Tmp, u4Tmp1, u4Tmp2)); + } +#endif + + pCoexDm->preAntPosType = pCoexDm->curAntPosType; +} + + +VOID +halbtc8703b1ant_SetFwPstdma( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte byte1, + IN u1Byte byte2, + IN u1Byte byte3, + IN u1Byte byte4, + IN u1Byte byte5 + ) +{ + u1Byte H2C_Parameter[5] ={0}; + u1Byte realByte1=byte1, realByte5=byte5; + BOOLEAN bApEnable=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + + if(bApEnable) + { + if(byte1&BIT4 && !(byte1&BIT5)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], FW for 1Ant AP mode\n")); + realByte1 &= ~BIT4; + realByte1 |= BIT5; + + realByte5 |= BIT5; + realByte5 &= ~BIT6; + } + } + + H2C_Parameter[0] = realByte1; + H2C_Parameter[1] = byte2; + H2C_Parameter[2] = byte3; + H2C_Parameter[3] = byte4; + H2C_Parameter[4] = realByte5; + + pCoexDm->psTdmaPara[0] = realByte1; + pCoexDm->psTdmaPara[1] = byte2; + pCoexDm->psTdmaPara[2] = byte3; + pCoexDm->psTdmaPara[3] = byte4; + pCoexDm->psTdmaPara[4] = realByte5; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], PS-TDMA H2C cmd =0x%x%08x\n", + H2C_Parameter[0], + H2C_Parameter[1]<<24|H2C_Parameter[2]<<16|H2C_Parameter[3]<<8|H2C_Parameter[4])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x60, 5, H2C_Parameter); +} + + +VOID +halbtc8703b1ant_PsTdma( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bTurnOn, + IN u1Byte type + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bTurnOnByCnt=FALSE, bWifiBusy=FALSE, bWiFiNoisy=FALSE; + u1Byte psTdmaTypeByCnt=0, rssiAdjustVal=0; + u1Byte psTdmaByte4Val = 0x50, psTdmaByte0Val = 0x51, psTdmaByte3Val = 0x10; + s1Byte nWiFiDurationAdjust = 0x0; + static BOOLEAN bPreWifiBusy=FALSE; + + pCoexDm->bCurPsTdmaOn = bTurnOn; + pCoexDm->curPsTdma = type; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + + if (bWifiBusy != bPreWifiBusy) + { + bForceExec = TRUE; + bPreWifiBusy = bWifiBusy; + } + + if (pCoexDm->bCurPsTdmaOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ********** TDMA(on, %d) **********\n", + pCoexDm->curPsTdma)); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ********** TDMA(off, %d) **********\n", + pCoexDm->curPsTdma)); + } + + if(!bForceExec) + { + if( (pCoexDm->bPrePsTdmaOn == pCoexDm->bCurPsTdmaOn) && + (pCoexDm->prePsTdma == pCoexDm->curPsTdma) ) + return; + } + + // Adjust WiFi slot by AP number + if (pCoexSta->nScanAPNum <= 5) + nWiFiDurationAdjust = 5; + else if (pCoexSta->nScanAPNum >= 40) + nWiFiDurationAdjust = -15; + else if (pCoexSta->nScanAPNum >= 20) + nWiFiDurationAdjust = -10; + + // for A2DP only case, PS-TDMA/ TDMA + if ((type == 1) || (type == 2) || (type == 9) || (type == 11) || (type == 101) + || (type == 102) || (type == 109) || (type == 101) || (type == 7) ) + { + if (!pCoexSta->bForceLpsOn) //Native power save TDMA, only for A2DP-only case 1/2/9/11 while wifi noisy threshold > 30 + { + psTdmaByte0Val = 0x61; //no null-pkt (TDMA) + psTdmaByte3Val = 0x11; // no tx-pause at BT-slot + + if (type == 7) + psTdmaByte4Val = 0x14; //BT-Auto-Slot + else + psTdmaByte4Val = 0x10; // 0x778 = d/1 toggle, no dynamic slot + } + else + { + psTdmaByte0Val = 0x51; //null-pkt (PS-TDMA) + psTdmaByte3Val = 0x10; //tx-pause at BT-slot + + if (type == 7) + psTdmaByte4Val = 0x14; //BT-Auto-Slot + else + psTdmaByte4Val = 0x50; // 0x778 = d/1 toggle, dynamic slot + } + } + else if ((type == 3) ||(type == 4) || (type == 13) || (type == 14) || (type == 103) || (type == 113) || (type == 114)) + { + psTdmaByte0Val = 0x51; //null-pkt (PS-TDMA) + psTdmaByte3Val = 0x10; //tx-pause at BT-slot + psTdmaByte4Val = 0x10; // 0x778 = d/1 toggle, no dynamic slot + } + else //native power save case + { + psTdmaByte0Val = 0x61; //no null-pkt (TDMA) + psTdmaByte3Val = 0x11; // no tx-pause at BT-slot + psTdmaByte4Val = 0x11; // 0x778 = d/1 toggle, no dynamic slot + //psTdmaByte4Va is not defne for 0x778 = d/1, 1/1 case + } + + // for A2DP slave + if ((pBtLinkInfo->bSlaveRole == TRUE) && (pBtLinkInfo->bA2dpExist)) + psTdmaByte4Val = psTdmaByte4Val | 0x1; //0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) + + // (for Antenna Detection Mechanism) + if (type > 100) + { + psTdmaByte0Val = psTdmaByte0Val | 0x82; //set antenna control by SW + psTdmaByte3Val = psTdmaByte3Val | 0x60; //set antenna no toggle, control by antenna diversity + } + + + if(bTurnOn) + { + switch(type) + { + default: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, 0x51, 0x1a, 0x1a, 0x0, psTdmaByte4Val); + break; + case 1: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x3a+nWiFiDurationAdjust, 0x03, psTdmaByte3Val, psTdmaByte4Val); + break; + case 2: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x2d+nWiFiDurationAdjust, 0x03, psTdmaByte3Val, psTdmaByte4Val); + break; + case 3: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x3a, 0x03, psTdmaByte3Val, psTdmaByte4Val); + break; + case 4: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x21, 0x03, psTdmaByte3Val, psTdmaByte4Val); + break; + case 5: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x15, 0x3, psTdmaByte3Val, 0x11); + break; + case 6: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x20, 0x3, psTdmaByte3Val, 0x11); + break; + case 7: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x1e, 0x03, psTdmaByte3Val, psTdmaByte4Val); + break; + case 8: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, 0x51, 0x1e, 0x3, 0x10, 0x14); + break; + case 9: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x21, 0x3, psTdmaByte3Val, psTdmaByte4Val); + break; + case 10: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, 0x13, 0xa, 0xa, 0x0, 0x40); + break; + case 11: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x21, 0x03, psTdmaByte3Val, psTdmaByte4Val); + break; + case 12: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, 0x51, 0x0a, 0x0a, 0x0, 0x50); + break; + case 13: + if (pCoexSta->nScanAPNum <= 3) // for Lenovo CPT test A2DP + OPP + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x3a, 0x3, psTdmaByte3Val, psTdmaByte4Val); + else + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x21, 0x3, psTdmaByte3Val, psTdmaByte4Val); + break; + case 14: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x21, 0x3, psTdmaByte3Val, psTdmaByte4Val); + break; + case 15: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, 0x13, 0xa, 0x3, 0x8, 0x0); + break; + case 16: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, 0x93, 0x15, 0x3, 0x10, 0x0); + break; + case 18: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, 0x93, 0x25, 0x3, 0x10, 0x0); + break; + case 20: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x3f, 0x03, psTdmaByte3Val, 0x10); + break; + case 21: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, 0x61, 0x25, 0x03, 0x11, 0x11); + break; + case 22: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x25, 0x03, psTdmaByte3Val, 0x10); + break; + case 23: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x3, 0x31, 0x18); + break; + case 24: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, 0xe3, 0x15, 0x3, 0x31, 0x18); + break; + case 25: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0x3, 0x31, 0x18); + break; + case 26: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0x3, 0x31, 0x18); + break; + case 27: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x3, 0x31, 0x98); + break; + case 28: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, 0x69, 0x25, 0x3, 0x31, 0x0); + break; + case 29: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, 0xab, 0x1a, 0x1a, 0x1, 0x10); + break; + case 30: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, 0x51, 0x30, 0x3, 0x10, 0x10); + break; + case 31: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, 0xd3, 0x1a, 0x1a, 0, 0x58); + break; + case 32: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x35, 0x3, psTdmaByte3Val, psTdmaByte4Val); + break; + case 33: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x35, 0x3, psTdmaByte3Val, 0x10); + break; + case 34: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, 0x53, 0x1a, 0x1a, 0x0, 0x10); + break; + case 35: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, 0x63, 0x1a, 0x1a, 0x0, 0x10); + break; + case 36: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, 0xd3, 0x12, 0x3, 0x14, 0x50); + break; + case 40: // SoftAP only with no sta associated,BT disable ,TDMA mode for power saving + /* here softap mode screen off will cost 70-80mA for phone */ + halbtc8703b1ant_SetFwPstdma(pBtCoexist, 0x23, 0x18, 0x00, 0x10, 0x24); + break; + + // 1-Ant translate to 2-Ant (for Antenna Detection Mechanism) + case 101: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x3a+nWiFiDurationAdjust, 0x03, psTdmaByte3Val, psTdmaByte4Val); + break; + case 102: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x2d+nWiFiDurationAdjust, 0x03, psTdmaByte3Val, psTdmaByte4Val); + break; + case 103: + //halbtc8703b1ant_SetFwPstdma(pBtCoexist, 0x51, 0x1d, 0x1d, 0x0, psTdmaByte4Val); + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x3a, 0x03, psTdmaByte3Val, psTdmaByte4Val); + break; + case 105: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x15, 0x3, psTdmaByte3Val, 0x11); + break; + case 106: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x20, 0x3, psTdmaByte3Val, 0x11); + break; + case 109: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x21, 0x3, psTdmaByte3Val, psTdmaByte4Val); + break; + case 111: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x21, 0x03, psTdmaByte3Val, psTdmaByte4Val); + break; + case 113: + //halbtc8703b1ant_SetFwPstdma(pBtCoexist, 0x51, 0x12, 0x12, 0x0, psTdmaByte4Val); + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x21, 0x3, psTdmaByte3Val, psTdmaByte4Val); + break; + case 114: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x21, 0x3, psTdmaByte3Val, psTdmaByte4Val); + break; + case 120: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x3f, 0x03, psTdmaByte3Val, 0x10); + break; + case 122: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x25, 0x03, psTdmaByte3Val, 0x10); + break; + case 132: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x25, 0x03, psTdmaByte3Val, psTdmaByte4Val); + break; + case 133: + halbtc8703b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x25, 0x03, psTdmaByte3Val, 0x11); + break; + + } + } + else + { + + // disable PS tdma + switch(type) + { + case 8: //PTA Control + halbtc8703b1ant_SetFwPstdma(pBtCoexist, 0x8, 0x0, 0x0, 0x0, 0x0); + break; + case 0: + default: //Software control, Antenna at BT side + halbtc8703b1ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x0, 0x0); + break; + case 1: // 2-Ant, 0x778=3, antenna control by antenna diversity + halbtc8703b1ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x48, 0x0); + break; +#if 0 + case 9: //Software control, Antenna at WiFi side + halbtc8703b1ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x0, 0x0); + halbtc8703b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_WIFI, FALSE, FALSE); + break; +#endif + } + } + rssiAdjustVal =0; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, &rssiAdjustVal); + + + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n", + pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x948), pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x765), pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x67))); + + // update pre state + pCoexDm->bPrePsTdmaOn = pCoexDm->bCurPsTdmaOn; + pCoexDm->prePsTdma = pCoexDm->curPsTdma; +} + +BOOLEAN +halbtc8703b1ant_IsCommonAction( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bCommon=FALSE, bWifiConnected=FALSE, bWifiBusy=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + + if(!bWifiConnected && + BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n")); + + //halbtc8703b1ant_SwMechanism(pBtCoexist, FALSE); + + bCommon = TRUE; + } + else if(bWifiConnected && + (BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi connected + BT non connected-idle!!\n")); + + //halbtc8703b1ant_SwMechanism(pBtCoexist, FALSE); + + bCommon = TRUE; + } + else if(!bWifiConnected && + (BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non connected-idle + BT connected-idle!!\n")); + + //halbtc8703b1ant_SwMechanism(pBtCoexist, FALSE); + + bCommon = TRUE; + } + else if(bWifiConnected && + (BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi connected + BT connected-idle!!\n")); + + //halbtc8703b1ant_SwMechanism(pBtCoexist, FALSE); + + bCommon = TRUE; + } + else if(!bWifiConnected && + (BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE != pCoexDm->btStatus) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non connected-idle + BT Busy!!\n")); + + //halbtc8703b1ant_SwMechanism(pBtCoexist, FALSE); + + bCommon = TRUE; + } + else + { + if (bWifiBusy) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi Connected-Busy + BT Busy!!\n")); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi Connected-Idle + BT Busy!!\n")); + } + + bCommon = FALSE; + } + + return bCommon; +} + + +VOID +halbtc8703b1ant_TdmaDurationAdjustForAcl( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte wifiStatus + ) +{ + static s4Byte up,dn,m,n,WaitCount; + s4Byte result; //0: no change, +1: increase WiFi duration, -1: decrease WiFi duration + u1Byte retryCount=0, btInfoExt; + static BOOLEAN bPreWifiBusy=FALSE; + BOOLEAN bWifiBusy = FALSE; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TdmaDurationAdjustForAcl()\n")); + + if(BT_8703B_1ANT_WIFI_STATUS_CONNECTED_BUSY == wifiStatus) + bWifiBusy = TRUE; + else + bWifiBusy = FALSE; + + if( (BT_8703B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN == wifiStatus) || + (BT_8703B_1ANT_WIFI_STATUS_CONNECTED_SCAN == wifiStatus) || + (BT_8703B_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT == wifiStatus) ) + { + if( pCoexDm->curPsTdma != 1 && + pCoexDm->curPsTdma != 2 && + pCoexDm->curPsTdma != 3 && + pCoexDm->curPsTdma != 9 ) + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + + up = 0; + dn = 0; + m = 1; + n= 3; + result = 0; + WaitCount = 0; + } + return; + } + + if(!pCoexDm->bAutoTdmaAdjust) + { + pCoexDm->bAutoTdmaAdjust = TRUE; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], first run TdmaDurationAdjust()!!\n")); + + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + //============ + up = 0; + dn = 0; + m = 1; + n= 3; + result = 0; + WaitCount = 0; + } + else + { + //accquire the BT TRx retry count from BT_Info byte2 + retryCount = pCoexSta->btRetryCnt; + btInfoExt = pCoexSta->btInfoExt; + + if ( (pCoexSta->lowPriorityTx) > 1050 || (pCoexSta->lowPriorityRx) > 1250 ) + retryCount++; + + result = 0; + WaitCount++; + + if(retryCount == 0) // no retry in the last 2-second duration + { + up++; + dn--; + + if (dn <= 0) + dn = 0; + + if(up >= n) // if s n 2 retry count0, hռeWiFi duration + { + WaitCount = 0; + n = 3; + up = 0; + dn = 0; + result = 1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Increase wifi duration!!\n")); + } + } + else if (retryCount <= 3) // <=3 retry in the last 2-second duration + { + up--; + dn++; + + if (up <= 0) + up = 0; + + if (dn == 2) // if s 2 2 retry count< 3, hկWiFi duration + { + if (WaitCount <= 2) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter<3!!\n")); + } + } + else //retry count > 3, un1 retry count > 3, hկWiFi duration + { + if (WaitCount == 1) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter>3!!\n")); + } + + if(result == -1) + { +/* if( (BT_INFO_8703B_1ANT_A2DP_BASIC_RATE(btInfoExt)) && + ((pCoexDm->curPsTdma == 1) ||(pCoexDm->curPsTdma == 2)) ) + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else */ if(pCoexDm->curPsTdma == 1) + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + } + else if(result == 1) + { +/* if( (BT_INFO_8703B_1ANT_A2DP_BASIC_RATE(btInfoExt)) && + ((pCoexDm->curPsTdma == 1) ||(pCoexDm->curPsTdma == 2)) ) + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else */ if(pCoexDm->curPsTdma == 11) + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + } + else //no change + { + /* Bryant Modify + if(bWifiBusy != bPreWifiBusy) //if busy / idle change + { + bPreWifiBusy = bWifiBusy; + halbtc8703b1ant_PsTdma(pBtCoexist, FORCE_EXEC, TRUE, pCoexDm->curPsTdma); + } + */ + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], ********** TDMA(on, %d) **********\n", + pCoexDm->curPsTdma)); + } + + if( pCoexDm->curPsTdma != 1 && + pCoexDm->curPsTdma != 2 && + pCoexDm->curPsTdma != 9 && + pCoexDm->curPsTdma != 11 ) + { + // recover to previous adjust type + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, pCoexDm->psTdmaDuAdjType); + } + } +} + +VOID +halbtc8703b1ant_PsTdmaCheckForPowerSaveState( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bNewPsState + ) +{ + u1Byte lpsMode=0x0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_LPS_MODE, &lpsMode); + + if(lpsMode) // already under LPS state + { + if(bNewPsState) + { + // keep state under LPS, do nothing. + } + else + { + // will leave LPS state, turn off psTdma first + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + } + } + else // NO PS state + { + if(bNewPsState) + { + // will enter LPS state, turn off psTdma first + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + } + else + { + // keep state under NO PS state, do nothing. + } + } +} + +VOID +halbtc8703b1ant_PowerSaveState( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte psType, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + BOOLEAN bLowPwrDisable=FALSE; + + switch(psType) + { + case BTC_PS_WIFI_NATIVE: + // recover to original 32k low power setting + pCoexSta->bForceLpsOn = FALSE; + bLowPwrDisable = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_NORMAL_LPS, NULL); + + break; + case BTC_PS_LPS_ON: + pCoexSta->bForceLpsOn = TRUE; + halbtc8703b1ant_PsTdmaCheckForPowerSaveState(pBtCoexist, TRUE); + halbtc8703b1ant_LpsRpwm(pBtCoexist, NORMAL_EXEC, lpsVal, rpwmVal); + // when coex force to enter LPS, do not enter 32k low power. + bLowPwrDisable = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + // power save must executed before psTdma. + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_ENTER_LPS, NULL); + + break; + case BTC_PS_LPS_OFF: + pCoexSta->bForceLpsOn = FALSE; + halbtc8703b1ant_PsTdmaCheckForPowerSaveState(pBtCoexist, FALSE); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_LEAVE_LPS, NULL); + + break; + default: + break; + } +} + +VOID +halbtc8703b1ant_ActionWifiOnly( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8703b1ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 0); + halbtc8703b1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8); + halbtc8703b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, FORCE_EXEC, FALSE, FALSE); +} + +VOID +halbtc8703b1ant_MonitorBtEnableDisable( + IN PBTC_COEXIST pBtCoexist + ) +{ + static BOOLEAN bPreBtDisabled=FALSE; + static u4Byte btDisableCnt=0; + BOOLEAN bBtActive=TRUE, bBtDisabled=FALSE; + + // This function check if bt is disabled + + if( pCoexSta->highPriorityTx == 0 && + pCoexSta->highPriorityRx == 0 && + pCoexSta->lowPriorityTx == 0 && + pCoexSta->lowPriorityRx == 0) + { + bBtActive = FALSE; + } + if( pCoexSta->highPriorityTx == 0xffff && + pCoexSta->highPriorityRx == 0xffff && + pCoexSta->lowPriorityTx == 0xffff && + pCoexSta->lowPriorityRx == 0xffff) + { + bBtActive = FALSE; + } + if(bBtActive) + { + btDisableCnt = 0; + bBtDisabled = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is enabled !!\n")); + } + else + { + btDisableCnt++; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], bt all counters=0, %d times!!\n", + btDisableCnt)); + if(btDisableCnt >= 2) + { + bBtDisabled = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is disabled !!\n")); + halbtc8703b1ant_ActionWifiOnly(pBtCoexist); + } + } + if(bPreBtDisabled != bBtDisabled) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is from %s to %s!!\n", + (bPreBtDisabled ? "disabled":"enabled"), + (bBtDisabled ? "disabled":"enabled"))); + bPreBtDisabled = bBtDisabled; + if(!bBtDisabled) + { + } + else + { + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_LEAVE_LPS, NULL); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_NORMAL_LPS, NULL); + } + } +} + +//============================================= +// +// Software Coex Mechanism start +// +//============================================= + +// SCO only or SCO+PAN(HS) + +/* +VOID +halbtc8703b1ant_ActionSco( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8703b1ant_SwMechanism(pBtCoexist, TRUE); +} + + +VOID +halbtc8703b1ant_ActionHid( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8703b1ant_SwMechanism(pBtCoexist, TRUE); +} + +//A2DP only / PAN(EDR) only/ A2DP+PAN(HS) +VOID +halbtc8703b1ant_ActionA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8703b1ant_SwMechanism(pBtCoexist, FALSE); +} + +VOID +halbtc8703b1ant_ActionA2dpPanHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8703b1ant_SwMechanism(pBtCoexist, FALSE); +} + +VOID +halbtc8703b1ant_ActionPanEdr( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8703b1ant_SwMechanism(pBtCoexist, FALSE); +} + +//PAN(HS) only +VOID +halbtc8703b1ant_ActionPanHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8703b1ant_SwMechanism(pBtCoexist, FALSE); +} + +//PAN(EDR)+A2DP +VOID +halbtc8703b1ant_ActionPanEdrA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8703b1ant_SwMechanism(pBtCoexist, FALSE); +} + +VOID +halbtc8703b1ant_ActionPanEdrHid( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8703b1ant_SwMechanism(pBtCoexist, TRUE); +} + +// HID+A2DP+PAN(EDR) +VOID +halbtc8703b1ant_ActionHidA2dpPanEdr( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8703b1ant_SwMechanism(pBtCoexist, TRUE); +} + +VOID +halbtc8703b1ant_ActionHidA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8703b1ant_SwMechanism(pBtCoexist, TRUE); +} + +*/ + +//============================================= +// +// Non-Software Coex Mechanism start +// +//============================================= +VOID +halbtc8703b1ant_ActionBtWhckTest( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8703b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8703b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); +} + +VOID +halbtc8703b1ant_ActionWifiMultiPort( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8703b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8703b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); +} + +VOID +halbtc8703b1ant_ActionHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); +} + +VOID +halbtc8703b1ant_ActionBtInquiry( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bWifiConnected=FALSE, bApEnable=FALSE, bWifiBusy=FALSE, bBtBusy=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bBtBusy); + + if ( (!bWifiConnected) && (!pCoexSta->bWiFiIsHighPriTask) ) + { + halbtc8703b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8703b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + else if( (pBtLinkInfo->bScoExist) || (pBtLinkInfo->bHidExist) || (pBtLinkInfo->bA2dpExist) ) + { + // SCO/HID/A2DP busy + halbtc8703b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else if ( (pBtLinkInfo->bPanExist) || (bWifiBusy) ) + { + halbtc8703b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + //for BT inquiry/page fail after S4 resume + //halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 20); + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else + { + halbtc8703b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8703b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + + + //halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + //halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } +} + +VOID +halbtc8703b1ant_ActionBtScoHidOnlyBusy( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte wifiStatus + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bWifiConnected=FALSE; + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + + // tdma and coex table + + if(pBtLinkInfo->bScoExist) + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 5); + } + else //HID + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 5); + } +} + +VOID +halbtc8703b1ant_ActionWifiConnectedBtAclBusy( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte wifiStatus + ) +{ + u1Byte btRssiState; + + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + btRssiState = halbtc8703b1ant_BtRssiState(2, 28, 0); + + if ( (pCoexSta->lowPriorityRx >= 950) && (!pCoexSta->bUnderIps) + && (pCoexSta->lowPriorityRx >= pCoexSta->lowPriorityTx) && (!pCoexSta->bC2hBtInquiryPage)) + { + pBtLinkInfo->bSlaveRole = TRUE; + } + else + { + pBtLinkInfo->bSlaveRole = FALSE; + } + + if(pBtLinkInfo->bHidOnly) //HID + { + halbtc8703b1ant_ActionBtScoHidOnlyBusy(pBtCoexist, wifiStatus); + pCoexDm->bAutoTdmaAdjust = FALSE; + return; + } + else if(pBtLinkInfo->bA2dpOnly) //A2DP + { + if(BT_8703B_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifiStatus) + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + pCoexDm->bAutoTdmaAdjust = FALSE; + } + else + { + //halbtc8703b1ant_TdmaDurationAdjustForAcl(pBtCoexist, wifiStatus); + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + pCoexDm->bAutoTdmaAdjust = TRUE; + } + } + else if ( ((pBtLinkInfo->bA2dpExist) && (pBtLinkInfo->bPanExist)) || + (pBtLinkInfo->bHidExist&&pBtLinkInfo->bA2dpExist&&pBtLinkInfo->bPanExist) ) //A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + pCoexDm->bAutoTdmaAdjust = FALSE; + } + else if(pBtLinkInfo->bHidExist&&pBtLinkInfo->bA2dpExist) //HID+A2DP + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->bAutoTdmaAdjust = FALSE; + + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else if( (pBtLinkInfo->bPanOnly) || (pBtLinkInfo->bHidExist&&pBtLinkInfo->bPanExist) ) //PAN(OPP,FTP), HID+PAN(OPP,FTP) + { + if(BT_8703B_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifiStatus) + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + else + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + pCoexDm->bAutoTdmaAdjust = FALSE; + } + else + { + //BT no-profile busy (0x9) + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 33); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + pCoexDm->bAutoTdmaAdjust = FALSE; + } +} + +VOID +halbtc8703b1ant_ActionWifiNotConnected( + IN PBTC_COEXIST pBtCoexist + ) +{ + // power save state + halbtc8703b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + halbtc8703b1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8); + halbtc8703b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); +} + +VOID +halbtc8703b1ant_ActionWifiNotConnectedScan( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + + halbtc8703b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + if(BT_8703B_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) + { + if (pBtLinkInfo->bA2dpExist) + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else if (pBtLinkInfo->bA2dpExist && pBtLinkInfo->bPanExist) + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 22); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 20); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + } + else if( (BT_8703B_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + halbtc8703b1ant_ActionBtScoHidOnlyBusy(pBtCoexist, + BT_8703B_1ANT_WIFI_STATUS_CONNECTED_SCAN); + } + else + { + //Bryant Add + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8703b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + } +} + +VOID +halbtc8703b1ant_ActionWifiNotConnectedAssoAuth( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + + halbtc8703b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + if( (pBtLinkInfo->bScoExist) || (pBtLinkInfo->bHidExist) || (pBtLinkInfo->bA2dpExist) ) + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 4); + } + else if (pBtLinkInfo->bPanExist) + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 20); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 4); + } + else + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8703b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 2); + } +} + +VOID +halbtc8703b1ant_ActionWifiConnectedScan( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + + halbtc8703b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + if(BT_8703B_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) + { + if (pBtLinkInfo->bA2dpExist) + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else if (pBtLinkInfo->bA2dpExist && pBtLinkInfo->bPanExist) + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 22); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 20); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + } + else if( (BT_8703B_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + halbtc8703b1ant_ActionBtScoHidOnlyBusy(pBtCoexist, + BT_8703B_1ANT_WIFI_STATUS_CONNECTED_SCAN); + } + else + { + //Bryant Add + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8703b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + } +} + +VOID +halbtc8703b1ant_ActionWifiConnectedSpecialPacket( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bWifiBusy = FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + + //no special packet process for both WiFi and BT very busy + if ((bWifiBusy) && ((pBtLinkInfo->bPanExist) || (pCoexSta->nNumOfProfile >= 2))) + return; + + halbtc8703b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + if((pBtLinkInfo->bScoExist) || (pBtLinkInfo->bHidExist)) + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 5); + } + else if (pBtLinkInfo->bA2dpExist) + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else if(pBtLinkInfo->bPanExist) + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 20); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8703b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + } +} + +VOID +halbtc8703b1ant_ActionWifiConnected( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bWifiBusy=FALSE; + BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE; + BOOLEAN bUnder4way=FALSE, bApEnable=FALSE; + u4Byte wifiBw; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CoexForWifiConnect()===>\n")); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &bUnder4way); + if(bUnder4way) + { + halbtc8703b1ant_ActionWifiConnectedSpecialPacket(pBtCoexist); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n")); + return; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + if(bScan || bLink || bRoam) + { + if(bScan) + halbtc8703b1ant_ActionWifiConnectedScan(pBtCoexist); + else + halbtc8703b1ant_ActionWifiConnectedSpecialPacket(pBtCoexist); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n")); + return; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + + // power save state + if(!bApEnable && BT_8703B_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus && !pBtCoexist->btLinkInfo.bHidOnly) + { + if(pBtCoexist->btLinkInfo.bA2dpOnly) //A2DP + { + if(!bWifiBusy) + halbtc8703b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else //busy + { + if (pCoexSta->nScanAPNum >= BT_8703B_1ANT_WIFI_NOISY_THRESH) //no force LPS, no PS-TDMA, use pure TDMA + { + halbtc8703b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } + else + { + halbtc8703b1ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + } + } + } + else if ((pCoexSta->bPanExist == FALSE) && (pCoexSta->bA2dpExist == FALSE) && (pCoexSta->bHidExist == FALSE)) + halbtc8703b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else + halbtc8703b1ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + } + else + halbtc8703b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + if(!bWifiBusy) + { + if(BT_8703B_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) + { + halbtc8703b1ant_ActionWifiConnectedBtAclBusy(pBtCoexist, + BT_8703B_1ANT_WIFI_STATUS_CONNECTED_IDLE); + } + else if( (BT_8703B_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + halbtc8703b1ant_ActionBtScoHidOnlyBusy(pBtCoexist, + BT_8703B_1ANT_WIFI_STATUS_CONNECTED_IDLE); + } + else + { + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8703b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + } + } + else + { + if(BT_8703B_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) + { + halbtc8703b1ant_ActionWifiConnectedBtAclBusy(pBtCoexist, + BT_8703B_1ANT_WIFI_STATUS_CONNECTED_BUSY); + } + else if( (BT_8703B_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + halbtc8703b1ant_ActionBtScoHidOnlyBusy(pBtCoexist, + BT_8703B_1ANT_WIFI_STATUS_CONNECTED_BUSY); + } + else + { + //halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8703b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + //halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + } +} + +VOID +halbtc8703b1ant_RunSwCoexistMechanism( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte algorithm=0; + + algorithm = halbtc8703b1ant_ActionAlgorithm(pBtCoexist); + pCoexDm->curAlgorithm = algorithm; + + if(halbtc8703b1ant_IsCommonAction(pBtCoexist)) + { + + } + else + { + switch(pCoexDm->curAlgorithm) + { + case BT_8703B_1ANT_COEX_ALGO_SCO: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = SCO.\n")); + //halbtc8703b1ant_ActionSco(pBtCoexist); + break; + case BT_8703B_1ANT_COEX_ALGO_HID: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = HID.\n")); + //halbtc8703b1ant_ActionHid(pBtCoexist); + break; + case BT_8703B_1ANT_COEX_ALGO_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = A2DP.\n")); + //halbtc8703b1ant_ActionA2dp(pBtCoexist); + break; + case BT_8703B_1ANT_COEX_ALGO_A2DP_PANHS: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = A2DP+PAN(HS).\n")); + //halbtc8703b1ant_ActionA2dpPanHs(pBtCoexist); + break; + case BT_8703B_1ANT_COEX_ALGO_PANEDR: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = PAN(EDR).\n")); + //halbtc8703b1ant_ActionPanEdr(pBtCoexist); + break; + case BT_8703B_1ANT_COEX_ALGO_PANHS: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = HS mode.\n")); + //halbtc8703b1ant_ActionPanHs(pBtCoexist); + break; + case BT_8703B_1ANT_COEX_ALGO_PANEDR_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = PAN+A2DP.\n")); + //halbtc8703b1ant_ActionPanEdrA2dp(pBtCoexist); + break; + case BT_8703B_1ANT_COEX_ALGO_PANEDR_HID: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = PAN(EDR)+HID.\n")); + //halbtc8703b1ant_ActionPanEdrHid(pBtCoexist); + break; + case BT_8703B_1ANT_COEX_ALGO_HID_A2DP_PANEDR: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = HID+A2DP+PAN.\n")); + //halbtc8703b1ant_ActionHidA2dpPanEdr(pBtCoexist); + break; + case BT_8703B_1ANT_COEX_ALGO_HID_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = HID+A2DP.\n")); + //halbtc8703b1ant_ActionHidA2dp(pBtCoexist); + break; + default: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = coexist All Off!!\n")); + //halbtc8703b1ant_CoexAllOff(pBtCoexist); + break; + } + pCoexDm->preAlgorithm = pCoexDm->curAlgorithm; + } +} + +VOID +halbtc8703b1ant_RunCoexistMechanism( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bWifiConnected=FALSE, bBtHsOn=FALSE; + BOOLEAN bIncreaseScanDevNum=FALSE; + BOOLEAN bBtCtrlAggBufSize=FALSE; + BOOLEAN bMiracastPlusBt=FALSE; + u1Byte aggBufSize=5; + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiLinkStatus=0; + u4Byte numOfWifiLink=0, wifiBw; + u1Byte iotPeer=BTC_IOT_PEER_UNKNOWN; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism()===>\n")); + + if(pBtCoexist->bManualControl) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n")); + return; + } + + if(pBtCoexist->bStopCoexDm) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n")); + return; + } + + if(pCoexSta->bUnderIps) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi is under IPS !!!\n")); + return; + } + + if(pCoexSta->bBtWhckTest) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is under WHCK TEST!!!\n")); + halbtc8703b1ant_ActionBtWhckTest(pBtCoexist); + return; + } + + if( (BT_8703B_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) || + (BT_8703B_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + bIncreaseScanDevNum = TRUE; + } + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, &bIncreaseScanDevNum); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_LINK_STATUS, &wifiLinkStatus); + numOfWifiLink = wifiLinkStatus>>16; + + if((numOfWifiLink>=2) || (wifiLinkStatus&WIFI_P2P_GO_CONNECTED)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], Multi-Port numOfWifiLink = %d, wifiLinkStatus = 0x%x\n", numOfWifiLink,wifiLinkStatus) ); + + if(pBtLinkInfo->bBtLinkExist) + { + halbtc8703b1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 1, 1, 0, 1); + bMiracastPlusBt = TRUE; + } + else + { + halbtc8703b1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + bMiracastPlusBt = FALSE; + } + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_MIRACAST_PLUS_BT, &bMiracastPlusBt); + halbtc8703b1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, bBtCtrlAggBufSize, aggBufSize); + + if ( (pBtLinkInfo->bA2dpExist) && (pCoexSta->bC2hBtInquiryPage) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], BT Is Inquirying \n") ); + halbtc8703b1ant_ActionBtInquiry(pBtCoexist); + } + else + halbtc8703b1ant_ActionWifiMultiPort(pBtCoexist); + + return; + } + else + { + bMiracastPlusBt = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_MIRACAST_PLUS_BT, &bMiracastPlusBt); + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if ( (pBtLinkInfo->bBtLinkExist) && (bWifiConnected) ) + { + halbtc8703b1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 1, 1, 0, 1); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_IOT_PEER, &iotPeer); + + if(BTC_IOT_PEER_CISCO != iotPeer) + { + if(pBtLinkInfo->bScoExist)//if (pBtLinkInfo->bBtHiPriLinkExist) + halbtc8703b1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x5); + else + halbtc8703b1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x5); + } + else + { + if(pBtLinkInfo->bScoExist) + halbtc8703b1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x5); + else + { + if (BTC_WIFI_BW_HT40==wifiBw) + halbtc8703b1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, TRUE, 0x10); + else + halbtc8703b1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, TRUE, 0x8); + } + } + + halbtc8703b1ant_SwMechanism(pBtCoexist, TRUE); + halbtc8703b1ant_RunSwCoexistMechanism(pBtCoexist); //just print debug message + } + else + { + halbtc8703b1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + + halbtc8703b1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x5); + + halbtc8703b1ant_SwMechanism(pBtCoexist, FALSE); + halbtc8703b1ant_RunSwCoexistMechanism(pBtCoexist); ////just print debug message + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + if(pCoexSta->bC2hBtInquiryPage) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], BT Is Inquirying \n") ); + halbtc8703b1ant_ActionBtInquiry(pBtCoexist); + return; + } + else if(bBtHsOn) + { + halbtc8703b1ant_ActionHs(pBtCoexist); + return; + } + + + if(!bWifiConnected) + { + BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi is non connected-idle !!!\n")); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + + if(bScan || bLink || bRoam) + { + if (bScan) + halbtc8703b1ant_ActionWifiNotConnectedScan(pBtCoexist); + else + halbtc8703b1ant_ActionWifiNotConnectedAssoAuth(pBtCoexist); + } + else + halbtc8703b1ant_ActionWifiNotConnected(pBtCoexist); + } + else // wifi LPS/Busy + { + halbtc8703b1ant_ActionWifiConnected(pBtCoexist); + } +} + +u4Byte +halbtc8703b1ant_PSD_Log2Base( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte val + + ) +{ + u1Byte i,j; + u4Byte tmp, tmp2, val_integerdB=0, tindex, shiftcount=0; + u4Byte result,val_fractiondB=0,Table_fraction[21]= {0,432, 332, 274, 232, 200, + 174, 151,132,115,100,86,74,62,51,42, + 32,23,15,7,0}; + + if (val == 0) + return 0; + + tmp = val; + + while(1) + { + if (tmp == 1) + break; + else + { + tmp = (tmp >> 1); + shiftcount++; + } + } + + + val_integerdB = shiftcount+1; + + tmp2=1; + for (j=1; j<= val_integerdB;j++) + tmp2 = tmp2*2; + + tmp = (val*100) /tmp2; + tindex = tmp/5; + + if (tindex > 20) + tindex = 20; + + val_fractiondB = Table_fraction[tindex]; + + result = val_integerdB*100 - val_fractiondB; + + return (result); + + +} + +VOID +halbtc8703b1ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + // force to reset coex mechanism + + // sw all off + halbtc8703b1ant_SwMechanism(pBtCoexist, FALSE); + + //halbtc8703b1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8); + //halbtc8703b1ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 0); + + pCoexSta->popEventCnt = 0; +} + +VOID +halbtc8703b1ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bBackUp, + IN BOOLEAN bWifiOnly + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + u4Byte u4Tmp=0;//, fwVer; + u2Byte u2Tmp=0; + u1Byte u1Tmp=0, u1Tmpa=0, u1Tmpb=0; + u1Byte H2C_Parameter[2] ={0}; + + u4Byte u4Tmp1=0, u4Tmp2=0; + + + u4Tmp1 = halbtc8703b1ant_LTECoex_InDirectReadReg(pBtCoexist, 0x38); + u4Tmp2 = halbtc8703b1ant_LTECoex_InDirectReadReg(pBtCoexist, 0x54); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ********** (Before Init HW config) 0x38= 0x%x, 0x54= 0x%x**********\n", u4Tmp1, u4Tmp2)); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 1Ant Init HW Config!!\n")); + + + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x550, 0x8, 0x1); //enable TBTT nterrupt + + //BT report packet sample rate + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x790, 0x5); + + // Enable BT counter statistics + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x778, 0x1); + + //Enable PTA (3-wire function form BT side) + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x40, 0x20, 0x1); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x41, 0x02, 0x1); + + //Enable PTA (tx/rx signal form WiFi side) + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x4c6, 0x10, 0x1); + + //enable GNT_WL/GNT_BT debug signal to GPIO14/15 + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x73, 0x8, 0x1); + + //enable GNT_WL + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x4e, 0x40, 0x0); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x67, 0x1, 0x0); + + halbtc8703b1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8); + + //Antenna config + if(bWifiOnly) + { + pCoexSta->bConCurrentRxModeOn = FALSE; + halbtc8703b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_WIFI, FORCE_EXEC, TRUE, FALSE); + halbtc8703b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_WIFI, FORCE_EXEC, FALSE, FALSE); + } + else + { + pCoexSta->bConCurrentRxModeOn = TRUE; + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x953, 0x2, 0x1); + //RF 0x1[0] = 0 -> Set GNT_WL_RF_Rx always = 1 for con-current Rx + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0x1, 0x0); + halbtc8703b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FORCE_EXEC, TRUE, FALSE); + } + + // PTA parameter + halbtc8703b1ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 0); + +} + + + +VOID +halbtc8703b1ant_PSD_ShowData( + IN PBTC_COEXIST pBtCoexist + ) +{ + pu1Byte cliBuf=pBtCoexist->cliBuf; + u4Byte nDeltaFreqPerPoint; + u4Byte freq,freq1,freq2,n=0,i=0, j=0, m=0, PsdRep1, PsdRep2; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n\n============[PSD info] (%d)============\n", + pPsdScan->nPSDGenCount); + CL_PRINTF(cliBuf); + + if (pPsdScan->nPSDGenCount == 0) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n No Data !!\n"); + CL_PRINTF(cliBuf); + return; + } + + if (pPsdScan->nPSDPoint == 0) + nDeltaFreqPerPoint = 0; + else + nDeltaFreqPerPoint = pPsdScan->nPSDBandWidth/pPsdScan->nPSDPoint; + + //if (pPsdScan->bIsPSDShowMaxOnly) + if (0) + { + PsdRep1 = pPsdScan->nPSDMaxValue/100; + PsdRep2 = pPsdScan->nPSDMaxValue - PsdRep1 * 100; + + freq = ((pPsdScan->nRealCentFreq-20) * 1000000 + pPsdScan->nPSDMaxValuePoint * nDeltaFreqPerPoint); + freq1 = freq/1000000; + freq2 = freq/1000 - freq1 * 1000; + + if (freq2 < 100) + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n Freq = %d.0%d MHz", + freq1, freq2); + else + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n Freq = %d.%d MHz", + freq1, freq2); + + if (PsdRep2 < 10) + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, ", Value = %d.0%d dB, (%d) \n", + PsdRep1, PsdRep2, pPsdScan->nPSDMaxValue); + else + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, ", Value = %d.%d dB, (%d)\n", + PsdRep1, PsdRep2, pPsdScan->nPSDMaxValue); + + CL_PRINTF(cliBuf); + } + else + { + m = pPsdScan->nPSDStartPoint; + n = pPsdScan->nPSDStartPoint; + i = 1; + j = 1; + + while(1) + { + do + { + freq = ((pPsdScan->nRealCentFreq-20) * 1000000 + m * nDeltaFreqPerPoint); + freq1 = freq/1000000; + freq2 = freq/1000 - freq1 * 1000; + + if (i ==1) + { + if (freq2 == 0) + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n Freq%6d.000", freq1); + else if (freq2 < 100) + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n Freq%6d.0%2d", freq1,freq2); + else + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n Freq%6d.%3d", freq1,freq2); + } + else if ( (i%8 == 0) || (m == pPsdScan->nPSDStopPoint) ) + { + if (freq2 == 0) + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "%6d.000\n", freq1); + else if (freq2 < 100) + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "%6d.0%2d\n", freq1,freq2); + else + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "%6d.%3d\n", freq1,freq2); + } + else + { + if (freq2 == 0) + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "%6d.000", freq1); + else if (freq2 < 100) + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "%6d.0%2d", freq1,freq2); + else + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "%6d.%3d", freq1,freq2); + } + + i++; + m++; + CL_PRINTF(cliBuf); + + }while( (i <= 8) && (m <= pPsdScan->nPSDStopPoint)); + + + do + { + PsdRep1 = pPsdScan->nPSDReport_MaxHold[n]/100; + PsdRep2 = pPsdScan->nPSDReport_MaxHold[n] - PsdRep1 * 100; + + if (j ==1) + { + if (PsdRep2 <10) + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n Val %7d.0%d", PsdRep1,PsdRep2); + else + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n Val %7d.%d", PsdRep1,PsdRep2); + } + else if ( (j%8 == 0) || (n == pPsdScan->nPSDStopPoint) ) + { + if (PsdRep2 <10) + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "%7d.0%d\n", PsdRep1,PsdRep2); + else + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "%7d.%d\n", PsdRep1,PsdRep2); + } + else + { + if (PsdRep2 <10) + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "%7d.0%d", PsdRep1,PsdRep2); + else + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "%7d.%d", PsdRep1,PsdRep2); + } + + j++; + n++; + CL_PRINTF(cliBuf); + + } while( (j <= 8) && (n <= pPsdScan->nPSDStopPoint)); + + if ( (m > pPsdScan->nPSDStopPoint) || (n > pPsdScan->nPSDStopPoint) ) + break; + else + { + i = 1; + j = 1; + } + + } + } + + +} + +VOID +halbtc8703b1ant_PSD_MaxHoldData( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte GenCount + ) +{ + u4Byte i=0, i_max=0, val_max=0, j; + + if (GenCount== 1) + { + memcpy(pPsdScan->nPSDReport_MaxHold, pPsdScan->nPSDReport, BT_8703B_1ANT_ANTDET_PSD_POINTS*sizeof(u4Byte)); + + for (i= pPsdScan->nPSDStartPoint; i<=pPsdScan->nPSDStopPoint; i++) + { + //RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx SweepPSDPoint(), Max_Hold i = %d, PSDReport = %d dB\n", i, pPsdScan->nPSDReport_MaxHold[i])); + } + + pPsdScan->nPSDMaxValuePoint = 0; + pPsdScan->nPSDMaxValue = 0; + + } + else + { + for (i= pPsdScan->nPSDStartPoint; i<=pPsdScan->nPSDStopPoint; i++) + { + if (pPsdScan->nPSDReport[i] > pPsdScan->nPSDReport_MaxHold[i]) + pPsdScan->nPSDReport_MaxHold[i] = pPsdScan->nPSDReport[i]; + + //search Max Value + if (i ==pPsdScan->nPSDStartPoint ) + { + i_max = i; + val_max = pPsdScan->nPSDReport_MaxHold[i]; + } + else + { + if (pPsdScan->nPSDReport_MaxHold[i] > val_max) + { + i_max = i; + val_max = pPsdScan->nPSDReport_MaxHold[i]; + } + } + + //RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx SweepPSDPoint(), Max_Hold i = %d, PSDReport = %d dB\n", i, pPsdScan->nPSDReport_MaxHold[i])); + + } + + pPsdScan->nPSDMaxValuePoint = i_max; + pPsdScan->nPSDMaxValue = val_max; + + //RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx SweepPSDPoint(), Max_Hold i_Max = %d, PSDReport_Max = %d dB\n", pPsdScan->nPSDMaxValuePoint + // ,pPsdScan->nPSDMaxValue)); + } + + +} + +u4Byte +halbtc8703b1ant_PSD_GetData( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte nPoint + ) +{ + //reg 0x808[9:0]: FFT data x + //reg 0x808[22]: 0-->1 to get 1 FFT data y + //reg 0x8b4[15:0]: FFT data y report + + u4Byte val = 0, psd_report =0; + + val = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x808); + + val &= 0xffbffc00; + val |= nPoint; + + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x808, val); + + val |= 0x00400000; + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x808, val); + + + val = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x8b4); + + psd_report = val & 0x0000ffff; + + return psd_report; +} + + +VOID +halbtc8703b1ant_PSD_SweepPoint( +IN PBTC_COEXIST pBtCoexist, + IN u4Byte centFreq, + IN s4Byte offset, + IN u4Byte span, + IN u4Byte points, + IN u4Byte avgnum + ) +{ + u4Byte i,val,n,k=0; + u4Byte nPoints=0, psd_report=0; + u4Byte nStartP=0, nStopP=0, nDeltaFreqPerPoint=156250; + u4Byte nPSDCenterFreq=20*10^6, freq,freq1,freq2; + BOOLEAN outloop = FALSE; + u1Byte flag = 0; + u4Byte tmp, PsdRep1, PsdRep2; + u4Byte WiFi_OriginalChannel = 1; + + pPsdScan->bIsPSDRunning = TRUE; + + do + { + switch(flag) + { + case 0: //Get PSD parameters + default: + //RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx SweepPSDPoint(), centFreq=0x%x, offset=0x%x, span=0x%x\n", + // centFreq, offset, span)); + + pPsdScan->nPSDBandWidth = 40*1000000; + pPsdScan->nPSDPoint = points; + pPsdScan->nPSDStartBase = points/2; + pPsdScan->nPSDAvgNum = avgnum; + pPsdScan->nRealCentFreq = centFreq; + pPsdScan->nRealOffset = offset; + pPsdScan->nRealSpan = span; + + + nPoints = pPsdScan->nPSDPoint; + nDeltaFreqPerPoint = pPsdScan->nPSDBandWidth/pPsdScan->nPSDPoint; + + //PSD point setup + val = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x808); + val &= 0xffff0fff; + + switch(pPsdScan->nPSDPoint) + { + case 128: + val |= 0x0; + break; + case 256: + default: + val |=0x00004000; + break; + case 512: + val |= 0x00008000; + break; + case 1024: + val |= 0x0000c000; + break; + } + + switch(pPsdScan->nPSDAvgNum) + { + case 1: + val |= 0x0; + break; + case 8: + val |=0x00001000; + break; + case 16: + val |= 0x00002000; + break; + case 32: + default: + val |= 0x00003000; + break; + } + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x808, val); + + //RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx SweepPSDPoint(), PSD BW= %d, DeltaFreq=%d\n" + // , pPsdScan->nPSDBandWidth, nDeltaFreqPerPoint)); + flag = 1; + break; + case 1: //calculate the PSD point index from freq/offset/span + nPSDCenterFreq = pPsdScan->nPSDBandWidth /2 +offset*(1000000); + //RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx SweepPSDPoint(), PSD Center Freq = %d\n", (centFreq + offset))); + + nStartP = pPsdScan->nPSDStartBase + (nPSDCenterFreq - span *(1000000)/2) /nDeltaFreqPerPoint; + pPsdScan->nPSDStartPoint = nStartP - pPsdScan->nPSDStartBase; + //RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx SweepPSDPoint(), Start PSD Poin Matrix Index = %d\n", pPsdScan->nPSDStartPoint)); + + nStopP = pPsdScan->nPSDStartBase + (nPSDCenterFreq + span *(1000000)/2) /nDeltaFreqPerPoint; + pPsdScan->nPSDStopPoint = nStopP - pPsdScan->nPSDStartBase-1; + //RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx SweepPSDPoint(), Stop PSD Poin Matrix Index = %d\n",pPsdScan->nPSDStopPoint)); + + flag = 2; + break; + case 2: //set RF channel/BW/Mode + + //set 3-wire off + val = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x88c); + val |= 0x00300000; + pBtCoexist->fBtcWrite4Byte(pBtCoexist,0x88c,val); + + //CCK off + val = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x800); + val &= 0xfeffffff; + pBtCoexist->fBtcWrite4Byte(pBtCoexist,0x800,val); + + //store WiFi original channel + WiFi_OriginalChannel = pBtCoexist->fBtcGetRfReg(pBtCoexist, BTC_RF_A, 0x18, 0x3ff); + + //Set RF channel + if (centFreq == 2484) + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x18, 0x3ff, 0xe); + else + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x18, 0x3ff, (centFreq-2412)/5 + 1); //WiFi TRx Mask on + + //Set RF mode = Rx, RF Gain = 0x8a0 + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x0, 0xfffff, 0x308a0); + + //Set RF Rx filter corner + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, 0x3e4); + + //Set TRx mask off + //un-lock TRx Mask setup + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xdd, 0x80, 0x1); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xdf, 0x1, 0x1); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + flag = 3; + break; + case 3: + memset(pPsdScan->nPSDReport,0, pPsdScan->nPSDPoint*sizeof(u4Byte)); + nStartP = pPsdScan->nPSDStartPoint + pPsdScan->nPSDStartBase; + nStopP = pPsdScan->nPSDStopPoint + pPsdScan->nPSDStartBase + 1; + + i = nStartP; + + while (i < nStopP) + { + if (i >= nPoints) + { + psd_report = halbtc8703b1ant_PSD_GetData(pBtCoexist,i-nPoints); + } + else + { + psd_report = halbtc8703b1ant_PSD_GetData(pBtCoexist,i); + } + + if (psd_report == 0) + tmp = 0; + else + //tmp = 20*log10((double)psd_report); + //20*log2(x)/log2(10), log2Base return theresult of the psd_report*100 + tmp = 6 * halbtc8703b1ant_PSD_Log2Base(pBtCoexist, psd_report); + + n = i-pPsdScan->nPSDStartBase; + pPsdScan->nPSDReport[n] = tmp; + PsdRep1 = pPsdScan->nPSDReport[n] /100; + PsdRep2 = pPsdScan->nPSDReport[n] - PsdRep1 * 100; + + freq = ((centFreq-20) * 1000000 + n * nDeltaFreqPerPoint); + freq1 = freq/1000000; + freq2 = freq/1000 - freq1 * 1000; +/* + if (freq2 < 100) + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx SweepPSDPoint(), i = %d (%d.0%d MHz)", n, freq1, freq2)); + else + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx SweepPSDPoint(), i = %d (%d.%d MHz)", n, freq1, freq2)); + + if (PsdRep2 < 10) + RT_TRACE(COMP_COEX, DBG_LOUD, (", PSDReport = %d (%d.0%d dB)\n",psd_report, PsdRep1, PsdRep2)); + else + RT_TRACE(COMP_COEX, DBG_LOUD, (", PSDReport = %d (%d.%d dB)\n",psd_report, PsdRep1,PsdRep2)); +*/ + i++; + + k=0; + + //Add Delay between PSD point + while(1) + { + if (k++ > 20000) + break; + } + + //RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx SweepPSDPoint()==============\n")); + } + + flag = 100; + break; + case 99: //error + + outloop = TRUE; + break; + case 100: //recovery + + //set 3-wire on + val = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x88c); + val &=0xffcfffff; + pBtCoexist->fBtcWrite4Byte(pBtCoexist,0x88c,val); + + //CCK on + val = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x800); + val |= 0x01000000; + pBtCoexist->fBtcWrite4Byte(pBtCoexist,0x800,val); + + //PSD off + val = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x808); + val &=0xffbfffff; + pBtCoexist->fBtcWrite4Byte(pBtCoexist,0x808,val); + + //TRx Mask on + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x780); + + //lock TRx Mask setup + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xdd, 0x80, 0x0); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xdf, 0x1, 0x0); + + //Set RF Rx filter corner + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, 0x0); + + //restore WiFi original channel + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x18, 0x3ff, WiFi_OriginalChannel); + + outloop = TRUE; + break; + + } + + }while (!outloop); + + + + pPsdScan->bIsPSDRunning = FALSE; + + +} + +//============================================================ +// work around function start with wa_halbtc8703b1ant_ +//============================================================ +//============================================================ +// extern function start with EXhalbtc8703b1ant_ +//============================================================ +VOID +EXhalbtc8703b1ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + u1Byte u1Tmp=0x0; + u2Byte u2Tmp=0x0; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx Execute 8703b 1-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n")); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("Ant Det Finish = %s, Ant Det Number = %d\n", + (pBoardInfo->btdmAntDetFinish? "Yes":"No"), pBoardInfo->btdmAntNumByAntDet)); + + pBtCoexist->bStopCoexDm = TRUE; + + // enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. + u2Tmp = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0x2); + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x2, u2Tmp|BIT0|BIT1); + + //set Path control owner to WiFi + halbtc8703b1ant_LTECoex_PathControlOwner(pBtCoexist, BT_8703B_1ANT_PCO_WLSIDE); + + // set GNT_BT to high + halbtc8703b1ant_LTECoex_Set_GNT_BT(pBtCoexist, BT_8703B_1ANT_GNT_BLOCK_RFC_BB, BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, BT_8703B_1ANT_SIG_STA_SET_TO_HIGH); + //Set GNT_WL to low + halbtc8703b1ant_LTECoex_Set_GNT_WL(pBtCoexist, BT_8703B_1ANT_GNT_BLOCK_RFC_BB, BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW, BT_8703B_1ANT_SIG_STA_SET_TO_LOW); + + // set WLAN_ACT = 0 + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0x4); + + // + // S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) + // Local setting bit define + // BIT0: "0" for no antenna inverse; "1" for antenna inverse + // BIT1: "0" for internal switch; "1" for external switch + // BIT2: "0" for one antenna; "1" for two antenna + // NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 + + u1Tmp = 0; + pBoardInfo->btdmAntPos = BTC_ANTENNA_AT_MAIN_PORT; + + if(pBtCoexist->chipInterface == BTC_INTF_USB) + { + pBtCoexist->fBtcWriteLocalReg1Byte(pBtCoexist, 0xfe08, u1Tmp); + } + else if(pBtCoexist->chipInterface == BTC_INTF_SDIO) + { + pBtCoexist->fBtcWriteLocalReg1Byte(pBtCoexist, 0x60, u1Tmp); + } + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ********** LTE coex Reg 0x38 (Power-On) = 0x%x**********\n", halbtc8703b1ant_LTECoex_InDirectReadReg(pBtCoexist, 0x38))); + + +#if 0 + if(pBtCoexist->chipInterface == BTC_INTF_USB) + { + // fixed at S0 for USB interface + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x0); + + u1Tmp |= 0x1; // antenna inverse + pBtCoexist->fBtcWriteLocalReg1Byte(pBtCoexist, 0xfe08, u1Tmp); + + pBoardInfo->btdmAntPos = BTC_ANTENNA_AT_AUX_PORT; + } + else + { + + // for PCIE and SDIO interface, we check efuse 0xc3[6] + if(pBoardInfo->singleAntPath == 0) + { + // set to S1 + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x280); + pBoardInfo->btdmAntPos = BTC_ANTENNA_AT_MAIN_PORT; + } + else if(pBoardInfo->singleAntPath == 1) + { + // set to S0 + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x0); + u1Tmp |= 0x1; // antenna inverse + pBoardInfo->btdmAntPos = BTC_ANTENNA_AT_AUX_PORT; + } + + + + if(pBtCoexist->chipInterface == BTC_INTF_PCI) + { + pBtCoexist->fBtcWriteLocalReg1Byte(pBtCoexist, 0x384, u1Tmp); + } + else if(pBtCoexist->chipInterface == BTC_INTF_SDIO) + { + pBtCoexist->fBtcWriteLocalReg1Byte(pBtCoexist, 0x60, u1Tmp); + } + } + +#endif +} + +VOID +EXhalbtc8703b1ant_PreLoadFirmware( + IN PBTC_COEXIST pBtCoexist + ) +{ +} + +VOID +EXhalbtc8703b1ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ) +{ + halbtc8703b1ant_InitHwConfig(pBtCoexist, TRUE, bWifiOnly); + pBtCoexist->bStopCoexDm = FALSE; +} + +VOID +EXhalbtc8703b1ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Coex Mechanism Init!!\n")); + + pBtCoexist->bStopCoexDm = FALSE; + + halbtc8703b1ant_InitCoexDm(pBtCoexist); + + halbtc8703b1ant_QueryBtInfo(pBtCoexist); +} + +VOID +EXhalbtc8703b1ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + pu1Byte cliBuf=pBtCoexist->cliBuf; + u1Byte u1Tmp[4], i, btInfoExt, psTdmaCase=0; + u2Byte u2Tmp[4]; + u4Byte u4Tmp[4]; + u4Byte faOfdm, faCck; + u4Byte fwVer=0, btPatchVer=0; + static u1Byte PopReportIn10s = 0; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cliBuf); + + if(pBtCoexist->bManualControl) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[Under Manual Control]============"); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n =========================================="); + CL_PRINTF(cliBuf); + } + if(pBtCoexist->bStopCoexDm) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[Coex is STOPPED]============"); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n =========================================="); + CL_PRINTF(cliBuf); + } + + if (pPsdScan->bAntDet_TryCount == 0) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", "Ant PG Num/ Mech/ Pos", + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum, pBoardInfo->btdmAntPos); + CL_PRINTF(cliBuf); + } + else + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d (%d/%d/%d)", "Ant PG Num/ Mech(Ant_Det)/ Pos", + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNumByAntDet, pBoardInfo->btdmAntPos, + pPsdScan->bAntDet_TryCount, pPsdScan->bAntDet_FailCount, pPsdScan->nAntDet_Result); + CL_PRINTF(cliBuf); + + if (pBoardInfo->btdmAntDetFinish) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "Ant Det PSD Value", pPsdScan->nAntDet_PeakVal); + CL_PRINTF(cliBuf); + } + } + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \ + ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion); + CL_PRINTF(cliBuf); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_BT_PATCH_VER, &btPatchVer); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)", "CoexVer/ FwVer/ PatchVer", \ + GLCoexVerDate8703b1Ant, GLCoexVer8703b1Ant, fwVer, btPatchVer, btPatchVer); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", "Wifi channel informed to BT", \ + pCoexDm->wifiChnlInfo[0], pCoexDm->wifiChnlInfo[1], + pCoexDm->wifiChnlInfo[2]); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s", "WifibHiPri/ Ccklock/ CckEverLock", \ + (pCoexSta->bWiFiIsHighPriTask? "Yes":"No"), + (pCoexSta->bCCKLock? "Yes":"No"), + (pCoexSta->bCCKEverLock? "Yes":"No")); + CL_PRINTF(cliBuf); + + // wifi status + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Wifi Status]============"); + CL_PRINTF(cliBuf); + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[BT Status]============"); + CL_PRINTF(cliBuf); + + PopReportIn10s++; + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ", "BT [status/ rssi/ retryCnt/ popCnt]", \ + ((pBtCoexist->btInfo.bBtDisabled)? ("disabled"): ((pCoexSta->bC2hBtInquiryPage)?("inquiry/page scan"):((BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus)? "non-connected idle": + ( (BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus)? "connected-idle":"busy")))), + pCoexSta->btRssi, pCoexSta->btRetryCnt, pCoexSta->popEventCnt); + CL_PRINTF(cliBuf); + + if (PopReportIn10s >= 5) + { + pCoexSta->popEventCnt = 0; + PopReportIn10s = 0; + } + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d / %d", "SCO/HID/PAN/A2DP/Hi-Pri", \ + pBtLinkInfo->bScoExist, pBtLinkInfo->bHidExist, pBtLinkInfo->bPanExist, pBtLinkInfo->bA2dpExist, pBtLinkInfo->bBtHiPriLinkExist); + CL_PRINTF(cliBuf); + + if (pStackInfo->bProfileNotified) + { + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO); + } + else + { + btInfoExt = pCoexSta->btInfoExt; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s", "BT Role/A2DP rate", \ + (pBtLinkInfo->bSlaveRole )? "Slave":"Master", (btInfoExt&BIT0)? "BR":"EDR"); + CL_PRINTF(cliBuf); + } + + + for(i=0; ibtInfoC2hCnt[i]) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", GLBtInfoSrc8703b1Ant[i], \ + pCoexSta->btInfoC2h[i][0], pCoexSta->btInfoC2h[i][1], + pCoexSta->btInfoC2h[i][2], pCoexSta->btInfoC2h[i][3], + pCoexSta->btInfoC2h[i][4], pCoexSta->btInfoC2h[i][5], + pCoexSta->btInfoC2h[i][6], pCoexSta->btInfoC2hCnt[i]); + CL_PRINTF(cliBuf); + } + } + + + if(pBtCoexist->bManualControl) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism] (before Manual)============"); + } + else + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============"); + } + + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ 0x%x", "SM[LowPenaltyRA]/RA Mask", \ + pCoexDm->bCurLowPenaltyRa, pBtCoexist->btInfo.raMask); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %d ", "NoAggr/ CtrlAggr/ AggrSize", \ + (pBtCoexist->btInfo.bRejectAggPkt? "Yes":"No"), (pBtCoexist->btInfo.bBtCtrlAggBufSize? "Yes":"No"), + pBtCoexist->btInfo.aggBufSize); + CL_PRINTF(cliBuf); + + // Fw mechanism + if(pBtCoexist->bManualControl) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism] (before Manual) ============"); + } + else + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============"); + } + + CL_PRINTF(cliBuf); + + psTdmaCase = pCoexDm->curPsTdma; + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)", "PS TDMA", \ + pCoexDm->psTdmaPara[0], pCoexDm->psTdmaPara[1], + pCoexDm->psTdmaPara[2], pCoexDm->psTdmaPara[3], + pCoexDm->psTdmaPara[4], psTdmaCase, + (pCoexDm->bCurPsTdmaOn? "On":"Off"), + (pCoexDm->bAutoTdmaAdjust? "Adj":"Fix") ); + + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "WL/BT Coex Table Type", \ + pCoexSta->nCoexTableType); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c0); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c4); + u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c8); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x6c0/0x6c4/0x6c8(coexTable)", \ + u4Tmp[0], u4Tmp[1], u4Tmp[2]); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x778); + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6cc); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x778/0x6cc/IgnWlanAct", \ + u1Tmp[0], u4Tmp[0], pCoexDm->bCurIgnoreWlanAct); + CL_PRINTF(cliBuf); + + u4Tmp[0] = halbtc8703b1ant_LTECoex_InDirectReadReg(pBtCoexist, 0xa0); + u4Tmp[1] = halbtc8703b1ant_LTECoex_InDirectReadReg(pBtCoexist, 0xa4); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "LTE Coex Table W_L/B_L", \ + u4Tmp[0]&0xffff, u4Tmp[1]&0xffff); + CL_PRINTF(cliBuf); + + u4Tmp[0] = halbtc8703b1ant_LTECoex_InDirectReadReg(pBtCoexist, 0xa8); + u4Tmp[1] = halbtc8703b1ant_LTECoex_InDirectReadReg(pBtCoexist, 0xac); + u4Tmp[2] = halbtc8703b1ant_LTECoex_InDirectReadReg(pBtCoexist, 0xb0); + u4Tmp[3] = halbtc8703b1ant_LTECoex_InDirectReadReg(pBtCoexist, 0xb4); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "LTE Break Table W_L/B_L/L_W/L_B", \ + u4Tmp[0]&0xffff, u4Tmp[1]&0xffff, u4Tmp[2]&0xffff, u4Tmp[3]&0xffff); + CL_PRINTF(cliBuf); + + // Hw setting + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============"); + CL_PRINTF(cliBuf); + + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x430); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x434); + u2Tmp[0] = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0x42a); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x456); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", "0x430/0x434/0x42a/0x456", \ + u4Tmp[0], u4Tmp[1], u2Tmp[0], u1Tmp[0]); + CL_PRINTF(cliBuf); + + + u4Tmp[0] = halbtc8703b1ant_LTECoex_InDirectReadReg(pBtCoexist, 0x38); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x73); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %s", "LTE CoexOn/Path Ctrl Owner", \ + ((u4Tmp[0]&BIT7)>> 7), ((u1Tmp[0]&BIT2)? "WL":"BT")); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", "LTE 3Wire/OPMode/UART/UARTMode", \ + ((u4Tmp[0]&BIT6)>> 6), ((u4Tmp[0]&(BIT5|BIT4))>> 4),((u4Tmp[0]&BIT3)>> 3), (u4Tmp[0]&(BIT2|BIT1|BIT0))); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %s", "GNT_WL_SWCtrl/GNT_BT_SWCtrl/Dbg", \ + ((u4Tmp[0]&BIT12)>> 12), ((u4Tmp[0]&BIT14)>> 14), ((u1Tmp[0]&BIT3)? "On":"Off")); + CL_PRINTF(cliBuf); + + u4Tmp[0] = halbtc8703b1ant_LTECoex_InDirectReadReg(pBtCoexist, 0x54); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", "GNT_WL/GNT_BT/LTE_Busy/UART_Busy", \ + ((u4Tmp[0]&BIT2)>> 2), ((u4Tmp[0]&BIT3)>> 3), ((u4Tmp[0]&BIT1)>> 1), (u4Tmp[0]&BIT0)); + CL_PRINTF(cliBuf); + + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4c6); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x40); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x4c6[4]/0x40[5] (WL/BT PTA)", \ + ((u1Tmp[0] & BIT4)>>4), ((u1Tmp[1] & BIT5)>>5)); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x550); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x522); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x953); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ %s", "0x550(bcn ctrl)/0x522/4-RxAGC", \ + u4Tmp[0], u1Tmp[0], (u1Tmp[1]&0x2)? "On": "Off"); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda0); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda4); + u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda8); + u4Tmp[3] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xcf0); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xa5b); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xa5c); + + faOfdm = ((u4Tmp[0]&0xffff0000) >> 16) + ((u4Tmp[1]&0xffff0000) >> 16) + (u4Tmp[1] & 0xffff) + (u4Tmp[2] & 0xffff) + \ + ((u4Tmp[3]&0xffff0000) >> 16) + (u4Tmp[3] & 0xffff) ; + faCck = (u1Tmp[0] << 8) + u1Tmp[1]; + + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc50); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0xc50/OFDM-CCA/OFDM-FA/CCK-FA", \ + u4Tmp[1]&0xff, u4Tmp[0]&0xffff, faOfdm, faCck); + CL_PRINTF(cliBuf); + + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", "CRC_OK CCK/11g/11n/11n-Agg", \ + pCoexSta->nCRCOK_CCK, pCoexSta->nCRCOK_11g, pCoexSta->nCRCOK_11n, pCoexSta->nCRCOK_11nAgg); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", "CRC_Err CCK/11g/11n/11n-Agg", \ + pCoexSta->nCRCErr_CCK, pCoexSta->nCRCErr_11g, pCoexSta->nCRCErr_11n, pCoexSta->nCRCErr_11nAgg); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x770(high-pri rx/tx)", \ + pCoexSta->highPriorityRx, pCoexSta->highPriorityTx); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x774(low-pri rx/tx)", \ + pCoexSta->lowPriorityRx, pCoexSta->lowPriorityTx); + CL_PRINTF(cliBuf); + + halbtc8703b1ant_ReadScoreBoard(pBtCoexist, &u2Tmp[0]); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %04x", "ScoreBoard[14:0] (from BT)", u2Tmp[0]); + CL_PRINTF(cliBuf); + +#if(BT_AUTO_REPORT_ONLY_8703B_1ANT == 1) + //halbtc8703b1ant_MonitorBtCtr(pBtCoexist); +#endif + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + + +VOID +EXhalbtc8703b1ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + u4Byte u4Tmp=0; + + if(pBtCoexist->bManualControl || pBtCoexist->bStopCoexDm) + return; + + if(BTC_IPS_ENTER == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS ENTER notify\n")); + pCoexSta->bUnderIps = TRUE; + + //Write WL "Active" in Score-board for LPS off + halbtc8703b1ant_PostActiveStateToBT(pBtCoexist, FALSE); + + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + halbtc8703b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FORCE_EXEC, FALSE, TRUE); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + else if(BTC_IPS_LEAVE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS LEAVE notify\n")); + halbtc8703b1ant_PostActiveStateToBT(pBtCoexist, TRUE); + + halbtc8703b1ant_InitHwConfig(pBtCoexist, FALSE, FALSE); + halbtc8703b1ant_InitCoexDm(pBtCoexist); + halbtc8703b1ant_QueryBtInfo(pBtCoexist); + + pCoexSta->bUnderIps = FALSE; + } +} + +VOID +EXhalbtc8703b1ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(pBtCoexist->bManualControl || pBtCoexist->bStopCoexDm) + return; + + if(BTC_LPS_ENABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS ENABLE notify\n")); + pCoexSta->bUnderLps = TRUE; + + if (pCoexSta->bForceLpsOn == TRUE) // LPS No-32K + { + //Write WL "Active" in Score-board for PS-TDMA + halbtc8703b1ant_PostActiveStateToBT(pBtCoexist, TRUE); + + } + else // LPS-32K, need check if this h2c 0x71 can work?? (2015/08/28) + { + //Write WL "Non-Active" in Score-board for Native-PS + halbtc8703b1ant_PostActiveStateToBT(pBtCoexist, FALSE); + + } + } + else if(BTC_LPS_DISABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS DISABLE notify\n")); + pCoexSta->bUnderLps = FALSE; + + + //Write WL "Active" in Score-board for LPS off + halbtc8703b1ant_PostActiveStateToBT(pBtCoexist, TRUE); + + } +} + +VOID +EXhalbtc8703b1ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + BOOLEAN bWifiConnected=FALSE, bBtHsOn=FALSE; + u4Byte wifiLinkStatus=0; + u4Byte numOfWifiLink=0; + BOOLEAN bBtCtrlAggBufSize=FALSE; + u1Byte aggBufSize=5; + + u1Byte u1Tmpa, u1Tmpb; + u4Byte u4Tmp; + + if(pBtCoexist->bManualControl || + pBtCoexist->bStopCoexDm ) + return; + + if(BTC_SCAN_START == type) + { + pCoexSta->bWiFiIsHighPriTask = TRUE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n")); + halbtc8703b1ant_PostActiveStateToBT(pBtCoexist, TRUE); + halbtc8703b1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8); //Force antenna setup for no scan result issue + halbtc8703b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, FORCE_EXEC, FALSE, FALSE); + } + else + { + pCoexSta->bWiFiIsHighPriTask = FALSE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n")); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_AP_NUM, &pCoexSta->nScanAPNum); + } + + if(pBtCoexist->btInfo.bBtDisabled) + return; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + + halbtc8703b1ant_QueryBtInfo(pBtCoexist); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_LINK_STATUS, &wifiLinkStatus); + numOfWifiLink = wifiLinkStatus>>16; + if(numOfWifiLink >= 2) + { + halbtc8703b1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8703b1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, bBtCtrlAggBufSize, aggBufSize); + halbtc8703b1ant_ActionWifiMultiPort(pBtCoexist); + return; + } + + if(pCoexSta->bC2hBtInquiryPage) + { + halbtc8703b1ant_ActionBtInquiry(pBtCoexist); + return; + } + else if(bBtHsOn) + { + halbtc8703b1ant_ActionHs(pBtCoexist); + return; + } + + if(BTC_SCAN_START == type) + { + //RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n")); + if(!bWifiConnected) // non-connected scan + { + halbtc8703b1ant_ActionWifiNotConnectedScan(pBtCoexist); + } + else // wifi is connected + { + halbtc8703b1ant_ActionWifiConnectedScan(pBtCoexist); + } + } + else if(BTC_SCAN_FINISH == type) + { + //RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n")); + if(!bWifiConnected) // non-connected scan + { + halbtc8703b1ant_ActionWifiNotConnected(pBtCoexist); + } + else + { + halbtc8703b1ant_ActionWifiConnected(pBtCoexist); + } + } +} + +VOID +EXhalbtc8703b1ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + BOOLEAN bWifiConnected=FALSE, bBtHsOn=FALSE; + u4Byte wifiLinkStatus=0; + u4Byte numOfWifiLink=0; + BOOLEAN bBtCtrlAggBufSize=FALSE; + u1Byte aggBufSize=5; + + if(pBtCoexist->bManualControl || + pBtCoexist->bStopCoexDm || + pBtCoexist->btInfo.bBtDisabled ) + return; + + if(BTC_ASSOCIATE_START == type) + { + pCoexSta->bWiFiIsHighPriTask = TRUE; + halbtc8703b1ant_PostActiveStateToBT(pBtCoexist, TRUE); + halbtc8703b1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8); //Force antenna setup for no scan result issue + halbtc8703b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, FORCE_EXEC, FALSE, FALSE); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n")); + pCoexDm->nArpCnt = 0; + } + else + { + pCoexSta->bWiFiIsHighPriTask = FALSE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n")); + //pCoexDm->nArpCnt = 0; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_LINK_STATUS, &wifiLinkStatus); + numOfWifiLink = wifiLinkStatus>>16; + if(numOfWifiLink >= 2) + { + halbtc8703b1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8703b1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, bBtCtrlAggBufSize, aggBufSize); + halbtc8703b1ant_ActionWifiMultiPort(pBtCoexist); + return; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + if(pCoexSta->bC2hBtInquiryPage) + { + halbtc8703b1ant_ActionBtInquiry(pBtCoexist); + return; + } + else if(bBtHsOn) + { + halbtc8703b1ant_ActionHs(pBtCoexist); + return; + } + + if(BTC_ASSOCIATE_START == type) + { + //RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n")); + halbtc8703b1ant_ActionWifiNotConnectedAssoAuth(pBtCoexist); + } + else if(BTC_ASSOCIATE_FINISH == type) + { + //RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n")); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + if(!bWifiConnected) // non-connected scan + { + halbtc8703b1ant_ActionWifiNotConnected(pBtCoexist); + } + else + { + halbtc8703b1ant_ActionWifiConnected(pBtCoexist); + } + } +} + +VOID +EXhalbtc8703b1ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + u1Byte H2C_Parameter[3] ={0}; + u4Byte wifiBw; + u1Byte wifiCentralChnl; + BOOLEAN bWifiUnderBMode = FALSE; + + if(pBtCoexist->bManualControl || + pBtCoexist->bStopCoexDm || + pBtCoexist->btInfo.bBtDisabled ) + return; + + if(BTC_MEDIA_CONNECT == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA connect notify\n")); + halbtc8703b1ant_PostActiveStateToBT(pBtCoexist, TRUE); + halbtc8703b1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8); //Force antenna setup for no scan result issue + halbtc8703b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, FORCE_EXEC, FALSE, FALSE); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, &bWifiUnderBMode); + + //Set CCK Tx/Rx high Pri except 11b mode + if (bWifiUnderBMode) + { + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cd, 0x00); //CCK Tx + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cf, 0x00); //CCK Rx + } + else + { + //pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cd, 0x10); //CCK Tx + //pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cf, 0x10); //CCK Rx + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cd, 0x00); //CCK Tx + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cf, 0x10); //CCK Rx + } + + pCoexDm->backupArfrCnt1 = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x430); + pCoexDm->backupArfrCnt2 = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x434); + pCoexDm->backupRetryLimit = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0x42a); + pCoexDm->backupAmpduMaxTime = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x456); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA disconnect notify\n")); + halbtc8703b1ant_PostActiveStateToBT(pBtCoexist, FALSE); + pCoexDm->nArpCnt = 0; + + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cd, 0x0); //CCK Tx + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cf, 0x0); //CCK Rx + + pCoexSta->bCCKEverLock = FALSE; + } + + halbtc8703b1ant_UpdateWifiChannelInfo(pBtCoexist, type); + +} + +VOID +EXhalbtc8703b1ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + BOOLEAN bBtHsOn=FALSE; + u4Byte wifiLinkStatus=0; + u4Byte numOfWifiLink=0; + BOOLEAN bBtCtrlAggBufSize=FALSE, bUnder4way=FALSE; + u1Byte aggBufSize=5; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &bUnder4way); + + if(pBtCoexist->bManualControl || + pBtCoexist->bStopCoexDm || + pBtCoexist->btInfo.bBtDisabled ) + return; + + if( BTC_PACKET_DHCP == type || + BTC_PACKET_EAPOL == type || + BTC_PACKET_ARP == type ) + { + halbtc8703b1ant_PostActiveStateToBT(pBtCoexist, TRUE); + + if (BTC_PACKET_ARP == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], special Packet ARP notify\n")); + + pCoexDm->nArpCnt++; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ARP Packet Count = %d\n", pCoexDm->nArpCnt)); + + if((pCoexDm->nArpCnt >= 10) && (!bUnder4way)) // if APR PKT > 10 after connect, do not go to ActionWifiConnectedSpecialPacket(pBtCoexist) + { + pCoexSta->bWiFiIsHighPriTask = FALSE; + } + else + { + pCoexSta->bWiFiIsHighPriTask = TRUE; + } + } + else + { + pCoexSta->bWiFiIsHighPriTask = TRUE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], special Packet DHCP or EAPOL notify\n")); + } + } + else + { + pCoexSta->bWiFiIsHighPriTask = FALSE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], special Packet [Type = %d] notify\n", type)); + } + + pCoexSta->specialPktPeriodCnt = 0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_LINK_STATUS, &wifiLinkStatus); + numOfWifiLink = wifiLinkStatus>>16; + if(numOfWifiLink >= 2) + { + halbtc8703b1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8703b1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, bBtCtrlAggBufSize, aggBufSize); + halbtc8703b1ant_ActionWifiMultiPort(pBtCoexist); + return; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + if(pCoexSta->bC2hBtInquiryPage) + { + halbtc8703b1ant_ActionBtInquiry(pBtCoexist); + return; + } + else if(bBtHsOn) + { + halbtc8703b1ant_ActionHs(pBtCoexist); + return; + } + + if( BTC_PACKET_DHCP == type || + BTC_PACKET_EAPOL == type || + ( (BTC_PACKET_ARP == type ) && (pCoexSta->bWiFiIsHighPriTask) ) ) + { + halbtc8703b1ant_ActionWifiConnectedSpecialPacket(pBtCoexist); + } +} + +VOID +EXhalbtc8703b1ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + u1Byte btInfo=0; + u1Byte i, rspSource=0; + BOOLEAN bWifiConnected=FALSE; + BOOLEAN bBtBusy=FALSE; + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + + pCoexSta->bC2hBtInfoReqSent = FALSE; + + rspSource = tmpBuf[0]&0xf; + if(rspSource >= BT_INFO_SRC_8703B_1ANT_MAX) + rspSource = BT_INFO_SRC_8703B_1ANT_WIFI_FW; + pCoexSta->btInfoC2hCnt[rspSource]++; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Bt info[%d], length=%d, hex data=[", rspSource, length)); + for(i=0; ibtInfoC2h[rspSource][i] = tmpBuf[i]; + if(i == 1) + btInfo = tmpBuf[i]; + if(i == length-1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x]\n", tmpBuf[i])); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x, ", tmpBuf[i])); + } + } + + // if 0xff, it means BT is under WHCK test + if (btInfo == 0xff) + pCoexSta->bBtWhckTest = TRUE; + else + pCoexSta->bBtWhckTest = FALSE; + + if(BT_INFO_SRC_8703B_1ANT_WIFI_FW != rspSource) + { + pCoexSta->btRetryCnt = // [3:0] + pCoexSta->btInfoC2h[rspSource][2]&0xf; + + if (pCoexSta->btRetryCnt >= 1) + pCoexSta->popEventCnt++; + + if (pCoexSta->btInfoC2h[rspSource][2]&0x20) + pCoexSta->bC2hBtPage = TRUE; + else + pCoexSta->bC2hBtPage = FALSE; + + pCoexSta->btRssi = + pCoexSta->btInfoC2h[rspSource][3]*2-90; + //pCoexSta->btInfoC2h[rspSource][3]*2+10; + + pCoexSta->btInfoExt = + pCoexSta->btInfoC2h[rspSource][4]; + + pCoexSta->bBtTxRxMask = (pCoexSta->btInfoC2h[rspSource][2]&0x40); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TX_RX_MASK, &pCoexSta->bBtTxRxMask); + + + // Here we need to resend some wifi info to BT + // because bt is reset and loss of the info. + if(pCoexSta->btInfoExt & BIT1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n")); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + if(bWifiConnected) + { + halbtc8703b1ant_UpdateWifiChannelInfo(pBtCoexist, BTC_MEDIA_CONNECT); + } + else + { + halbtc8703b1ant_UpdateWifiChannelInfo(pBtCoexist, BTC_MEDIA_DISCONNECT); + } + } + + if(pCoexSta->btInfoExt & BIT3) + { + if(!pBtCoexist->bManualControl && !pBtCoexist->bStopCoexDm) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n")); + halbtc8703b1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE); + } + } + else + { + // BT already NOT ignore Wlan active, do nothing here. + } +#if(BT_AUTO_REPORT_ONLY_8703B_1ANT == 0) + if( (pCoexSta->btInfoExt & BIT4) ) + { + // BT auto report already enabled, do nothing + } + else + { + halbtc8703b1ant_BtAutoReport(pBtCoexist, FORCE_EXEC, TRUE); + } +#endif + } + + // check BIT2 first ==> check if bt is under inquiry or page scan + if(btInfo & BT_INFO_8703B_1ANT_B_INQ_PAGE) + pCoexSta->bC2hBtInquiryPage = TRUE; + else + pCoexSta->bC2hBtInquiryPage = FALSE; + + pCoexSta->nNumOfProfile = 0; + + // set link exist status + if(!(btInfo&BT_INFO_8703B_1ANT_B_CONNECTION)) + { + pCoexSta->bBtLinkExist = FALSE; + pCoexSta->bPanExist = FALSE; + pCoexSta->bA2dpExist = FALSE; + pCoexSta->bHidExist = FALSE; + pCoexSta->bScoExist = FALSE; + + pCoexSta->bBtHiPriLinkExist = FALSE; + } + else // connection exists + { + pCoexSta->bBtLinkExist = TRUE; + if(btInfo & BT_INFO_8703B_1ANT_B_FTP) + { + pCoexSta->bPanExist = TRUE; + pCoexSta->nNumOfProfile++; + } + else + pCoexSta->bPanExist = FALSE; + if(btInfo & BT_INFO_8703B_1ANT_B_A2DP) + { + pCoexSta->bA2dpExist = TRUE; + pCoexSta->nNumOfProfile++; + } + else + pCoexSta->bA2dpExist = FALSE; + if(btInfo & BT_INFO_8703B_1ANT_B_HID) + { + pCoexSta->bHidExist = TRUE; + pCoexSta->nNumOfProfile++; + } + else + pCoexSta->bHidExist = FALSE; + if(btInfo & BT_INFO_8703B_1ANT_B_SCO_ESCO) + { + pCoexSta->bScoExist = TRUE; + pCoexSta->nNumOfProfile++; + } + else + pCoexSta->bScoExist = FALSE; + + if ((pCoexSta->bHidExist == FALSE) && (pCoexSta->bC2hBtInquiryPage == FALSE) &&( pCoexSta->bScoExist == FALSE)) + { + if (pCoexSta->highPriorityTx + pCoexSta->highPriorityRx >= 160) + { + pCoexSta->bHidExist = TRUE; + pCoexSta->wrongProfileNotification++; + pCoexSta->nNumOfProfile++; + btInfo = btInfo | 0x28; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT HID = true (Hi-Pri > 160)!\n")); + } + } + + //Add Hi-Pri Tx/Rx counter to avoid false detection + if (((pCoexSta->bHidExist) || (pCoexSta->bScoExist)) && (pCoexSta->highPriorityTx + pCoexSta->highPriorityRx >= 160) + && (!pCoexSta->bC2hBtInquiryPage)) + pCoexSta->bBtHiPriLinkExist = TRUE; + else + pCoexSta->bBtHiPriLinkExist = FALSE; + + if((btInfo&BT_INFO_8703B_1ANT_B_ACL_BUSY) && (pCoexSta->nNumOfProfile == 0)) + { + if (pCoexSta->lowPriorityTx + pCoexSta->lowPriorityRx >= 160) + { + pCoexSta->bPanExist = TRUE; + pCoexSta->nNumOfProfile++; + pCoexSta->wrongProfileNotification++; + btInfo = btInfo | 0x88; + } + } + } + + halbtc8703b1ant_UpdateBtLinkInfo(pBtCoexist); + + btInfo = btInfo & 0x1f; //mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) + + if(!(btInfo&BT_INFO_8703B_1ANT_B_CONNECTION)) + { + pCoexDm->btStatus = BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n")); + } + else if(btInfo == BT_INFO_8703B_1ANT_B_CONNECTION) // connection exists but no busy + { + pCoexDm->btStatus = BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n")); + } + else if((btInfo&BT_INFO_8703B_1ANT_B_SCO_ESCO) || + (btInfo&BT_INFO_8703B_1ANT_B_SCO_BUSY)) + { + pCoexDm->btStatus = BT_8703B_1ANT_BT_STATUS_SCO_BUSY; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT SCO busy!!!\n")); + } + else if(btInfo&BT_INFO_8703B_1ANT_B_ACL_BUSY) + { + if(BT_8703B_1ANT_BT_STATUS_ACL_BUSY != pCoexDm->btStatus) + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->btStatus = BT_8703B_1ANT_BT_STATUS_ACL_BUSY; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT ACL busy!!!\n")); + } + else + { + pCoexDm->btStatus = BT_8703B_1ANT_BT_STATUS_MAX; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n")); + } + + if( (BT_8703B_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) || + (BT_8703B_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + bBtBusy = TRUE; + else + bBtBusy = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bBtBusy); + + halbtc8703b1ant_RunCoexistMechanism(pBtCoexist); +} + +VOID +EXhalbtc8703b1ant_RfStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + u4Byte u4Tmp; + u1Byte u1Tmpa,u1Tmpb, u1Tmpc; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RF Status notify\n")); + + if(BTC_RF_ON == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RF is turned ON!!\n")); + halbtc8703b1ant_PostActiveStateToBT(pBtCoexist, TRUE); + halbtc8703b1ant_InitHwConfig(pBtCoexist, FALSE, FALSE); + pBtCoexist->bStopCoexDm = FALSE; + } + else if(BTC_RF_OFF == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RF is turned OFF!!\n")); + halbtc8703b1ant_PostActiveStateToBT(pBtCoexist, FALSE); + + halbtc8703b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8703b1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); + halbtc8703b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FORCE_EXEC, FALSE, TRUE); + halbtc8703b1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE); + pBtCoexist->bStopCoexDm = TRUE; + + } +} + +VOID +EXhalbtc8703b1ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte u4Tmp; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Halt notify\n")); + + halbtc8703b1ant_PostActiveStateToBT(pBtCoexist, FALSE); + + halbtc8703b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8703b1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); + halbtc8703b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FORCE_EXEC, FALSE, TRUE); + + halbtc8703b1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE); + + EXhalbtc8703b1ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); + + pBtCoexist->bStopCoexDm = TRUE; +} + +VOID +EXhalbtc8703b1ant_PnpNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte pnpState + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Pnp notify\n")); + + if(BTC_WIFI_PNP_SLEEP == pnpState) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Pnp notify to SLEEP\n")); + + halbtc8703b1ant_PostActiveStateToBT(pBtCoexist, FALSE); + + halbtc8703b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8703b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + halbtc8703b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FORCE_EXEC, FALSE, TRUE); + halbtc8703b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + + pBtCoexist->bStopCoexDm = TRUE; + } + else if(BTC_WIFI_PNP_WAKE_UP == pnpState) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Pnp notify to WAKE UP\n")); + halbtc8703b1ant_PostActiveStateToBT(pBtCoexist, TRUE); + + pBtCoexist->bStopCoexDm = FALSE; + halbtc8703b1ant_InitHwConfig(pBtCoexist, FALSE, FALSE); + halbtc8703b1ant_InitCoexDm(pBtCoexist); + halbtc8703b1ant_QueryBtInfo(pBtCoexist); + } +} + + +VOID +EXhalbtc8703b1ant_ScoreBoardStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ) +{ + // + + +} + +VOID +EXhalbtc8703b1ant_CoexDmReset( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], *****************Coex DM Reset*****************\n")); + + halbtc8703b1ant_InitHwConfig(pBtCoexist, FALSE, FALSE); + //pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + //pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x2, 0xfffff, 0x0); + halbtc8703b1ant_InitCoexDm(pBtCoexist); +} + +VOID +EXhalbtc8703b1ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ) +{ + static u1Byte disVerInfoCnt=0; + u4Byte fwVer=0, btPatchVer=0; + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ==========================Periodical===========================\n")); + + if(disVerInfoCnt <= 5) + { + disVerInfoCnt += 1; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ****************************************************************\n")); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Ant PG Num/ Ant Mech/ Ant Pos = %d/ %d/ %d\n", + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum, pBoardInfo->btdmAntPos)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT stack/ hci ext ver = %s / %d\n", + ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion)); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_BT_PATCH_VER, &btPatchVer); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CoexVer/ FwVer/ PatchVer = %d_%x/ 0x%x/ 0x%x(%d)\n", + GLCoexVerDate8703b1Ant, GLCoexVer8703b1Ant, fwVer, btPatchVer, btPatchVer)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ****************************************************************\n")); + } + +#if(BT_AUTO_REPORT_ONLY_8703B_1ANT == 0) + halbtc8703b1ant_QueryBtInfo(pBtCoexist); + halbtc8703b1ant_MonitorBtEnableDisable(pBtCoexist); +#else + halbtc8703b1ant_MonitorBtCtr(pBtCoexist); + halbtc8703b1ant_MonitorWiFiCtr(pBtCoexist); +#if BT_8703B_1ANT_ANTDET_ENABLE + halbtc8703b1ant_MonitorBtEnableDisable(pBtCoexist); +#endif + + if( halbtc8703b1ant_IsWifiStatusChanged(pBtCoexist) || + pCoexDm->bAutoTdmaAdjust ) + { + + halbtc8703b1ant_RunCoexistMechanism(pBtCoexist); + } + + pCoexSta->specialPktPeriodCnt++; + +#endif +} + +VOID +EXhalbtc8703b1ant_AntennaDetection( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte centFreq, + IN u4Byte offset, + IN u4Byte span, + IN u4Byte seconds + ) +{ + //No Antenna Detection required because 8730b is only 1-Ant +} + +VOID +EXhalbtc8703b1ant_AntennaIsolation( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte centFreq, + IN u4Byte offset, + IN u4Byte span, + IN u4Byte seconds + ) +{ + + +} + +VOID +EXhalbtc8703b1ant_PSDScan( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte centFreq, + IN u4Byte offset, + IN u4Byte span, + IN u4Byte seconds + ) +{ + + +} + +VOID +EXhalbtc8703b1ant_DisplayAntDetection( + IN PBTC_COEXIST pBtCoexist + ) +{ + +} + +#endif + +#else // #if (RTL8723B_SUPPORT == 1) +VOID +EXhalbtc8703b1ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ){} +VOID +EXhalbtc8703b1ant_PreLoadFirmware( + IN PBTC_COEXIST pBtCoexist + ){} +VOID +EXhalbtc8703b1ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ){} +VOID +EXhalbtc8703b1ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ){} +VOID +EXhalbtc8703b1ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ){} +VOID +EXhalbtc8703b1ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ){} +VOID +EXhalbtc8703b1ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ){} +VOID +EXhalbtc8703b1ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ){} +VOID +EXhalbtc8703b1ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ){} +VOID +EXhalbtc8703b1ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ){} +VOID +EXhalbtc8703b1ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ){} +VOID +EXhalbtc8703b1ant_RfStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ){} +VOID +EXhalbtc8703b1ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ){} +VOID +EXhalbtc8703b1ant_PnpNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte pnpState + ){} +VOID +EXhalbtc8703b1ant_ScoreBoardStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ){} +VOID +EXhalbtc8703b1ant_CoexDmReset( + IN PBTC_COEXIST pBtCoexist + ){} +VOID +EXhalbtc8703b1ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ){} +VOID +EXhalbtc8703b1ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ){} +VOID +EXhalbtc8703b1ant_AntennaDetection( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte centFreq, + IN u4Byte offset, + IN u4Byte span, + IN u4Byte seconds + ){} +VOID +EXhalbtc8703b1ant_DisplayAntDetection( + IN PBTC_COEXIST pBtCoexist + ){} + +#endif diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8703b1Ant.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8703b1Ant.h new file mode 100644 index 000000000..9d491b7c3 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8703b1Ant.h @@ -0,0 +1,387 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//=========================================== +// The following is for 8703B 1ANT BT Co-exist definition +//=========================================== +#define BT_AUTO_REPORT_ONLY_8703B_1ANT 1 + +#define BT_INFO_8703B_1ANT_B_FTP BIT7 +#define BT_INFO_8703B_1ANT_B_A2DP BIT6 +#define BT_INFO_8703B_1ANT_B_HID BIT5 +#define BT_INFO_8703B_1ANT_B_SCO_BUSY BIT4 +#define BT_INFO_8703B_1ANT_B_ACL_BUSY BIT3 +#define BT_INFO_8703B_1ANT_B_INQ_PAGE BIT2 +#define BT_INFO_8703B_1ANT_B_SCO_ESCO BIT1 +#define BT_INFO_8703B_1ANT_B_CONNECTION BIT0 + +#define BT_INFO_8703B_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ + (((_BT_INFO_EXT_&BIT0))? TRUE:FALSE) + +#define BTC_RSSI_COEX_THRESH_TOL_8703B_1ANT 2 + +#define BT_8703B_1ANT_WIFI_NOISY_THRESH 30 //max: 255 + +//for Antenna detection +#define BT_8703B_1ANT_ANTDET_PSDTHRES_BACKGROUND 50 +#define BT_8703B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70 +#define BT_8703B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 55 +#define BT_8703B_1ANT_ANTDET_PSDTHRES_1ANT 35 +#define BT_8703B_1ANT_ANTDET_RETRY_INTERVAL 10 //retry timer if ant det is fail, unit: second +#define BT_8703B_1ANT_ANTDET_ENABLE 0 +#define BT_8703B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE 0 + +#define BT_8703B_1ANT_LTECOEX_INDIRECTREG_ACCESS_TIMEOUT 30000 + +typedef enum _BT_8703B_1ANT_SIGNAL_STATE{ + BT_8703B_1ANT_SIG_STA_SET_TO_LOW = 0x0, + BT_8703B_1ANT_SIG_STA_SET_BY_HW = 0x0, + BT_8703B_1ANT_SIG_STA_SET_TO_HIGH = 0x1, + BT_8703B_1ANT_SIG_STA_MAX +}BT_8703B_1ANT_SIGNAL_STATE,*PBT_8703B_1ANT_SIGNAL_STATE; + +typedef enum _BT_8703B_1ANT_PATH_CTRL_OWNER{ + BT_8703B_1ANT_PCO_BTSIDE = 0x0, + BT_8703B_1ANT_PCO_WLSIDE = 0x1, + BT_8703B_1ANT_PCO_MAX +}BT_8703B_1ANT_PATH_CTRL_OWNER,*PBT_8703B_1ANT_PATH_CTRL_OWNER; + +typedef enum _BT_8703B_1ANT_GNT_CTRL_TYPE{ + BT_8703B_1ANT_GNT_TYPE_CTRL_BY_PTA = 0x0, + BT_8703B_1ANT_GNT_TYPE_CTRL_BY_SW = 0x1, + BT_8703B_1ANT_GNT_TYPE_MAX +}BT_8703B_1ANT_GNT_CTRL_TYPE,*PBT_8703B_1ANT_GNT_CTRL_TYPE; + +typedef enum _BT_8703B_1ANT_GNT_CTRL_BLOCK{ + BT_8703B_1ANT_GNT_BLOCK_RFC_BB = 0x0, + BT_8703B_1ANT_GNT_BLOCK_RFC = 0x1, + BT_8703B_1ANT_GNT_BLOCK_BB = 0x2, + BT_8703B_1ANT_GNT_BLOCK_MAX +}BT_8703B_1ANT_GNT_CTRL_BLOCK,*PBT_8703B_1ANT_GNT_CTRL_BLOCK; + +typedef enum _BT_8703B_1ANT_LTE_COEX_TABLE_TYPE{ + BT_8703B_1ANT_CTT_WL_VS_LTE = 0x0, + BT_8703B_1ANT_CTT_BT_VS_LTE = 0x1, + BT_8703B_1ANT_CTT_MAX +}BT_8703B_1ANT_LTE_COEX_TABLE_TYPE,*PBT_8703B_1ANT_LTE_COEX_TABLE_TYPE; + +typedef enum _BT_8703B_1ANT_LTE_BREAK_TABLE_TYPE{ + BT_8703B_1ANT_LBTT_WL_BREAK_LTE = 0x0, + BT_8703B_1ANT_LBTT_BT_BREAK_LTE = 0x1, + BT_8703B_1ANT_LBTT_LTE_BREAK_WL = 0x2, + BT_8703B_1ANT_LBTT_LTE_BREAK_BT = 0x3, + BT_8703B_1ANT_LBTT_MAX +}BT_8703B_1ANT_LTE_BREAK_TABLE_TYPE,*PBT_8703B_1ANT_LTE_BREAK_TABLE_TYPE; + +typedef enum _BT_INFO_SRC_8703B_1ANT{ + BT_INFO_SRC_8703B_1ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8703B_1ANT_BT_RSP = 0x1, + BT_INFO_SRC_8703B_1ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8703B_1ANT_MAX +}BT_INFO_SRC_8703B_1ANT,*PBT_INFO_SRC_8703B_1ANT; + +typedef enum _BT_8703B_1ANT_BT_STATUS{ + BT_8703B_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8703B_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8703B_1ANT_BT_STATUS_INQ_PAGE = 0x2, + BT_8703B_1ANT_BT_STATUS_ACL_BUSY = 0x3, + BT_8703B_1ANT_BT_STATUS_SCO_BUSY = 0x4, + BT_8703B_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, + BT_8703B_1ANT_BT_STATUS_MAX +}BT_8703B_1ANT_BT_STATUS,*PBT_8703B_1ANT_BT_STATUS; + +typedef enum _BT_8703B_1ANT_WIFI_STATUS{ + BT_8703B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8703B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1, + BT_8703B_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2, + BT_8703B_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3, + BT_8703B_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4, + BT_8703B_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5, + BT_8703B_1ANT_WIFI_STATUS_MAX +}BT_8703B_1ANT_WIFI_STATUS,*PBT_8703B_1ANT_WIFI_STATUS; + +typedef enum _BT_8703B_1ANT_COEX_ALGO{ + BT_8703B_1ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8703B_1ANT_COEX_ALGO_SCO = 0x1, + BT_8703B_1ANT_COEX_ALGO_HID = 0x2, + BT_8703B_1ANT_COEX_ALGO_A2DP = 0x3, + BT_8703B_1ANT_COEX_ALGO_A2DP_PANHS = 0x4, + BT_8703B_1ANT_COEX_ALGO_PANEDR = 0x5, + BT_8703B_1ANT_COEX_ALGO_PANHS = 0x6, + BT_8703B_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7, + BT_8703B_1ANT_COEX_ALGO_PANEDR_HID = 0x8, + BT_8703B_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, + BT_8703B_1ANT_COEX_ALGO_HID_A2DP = 0xa, + BT_8703B_1ANT_COEX_ALGO_MAX = 0xb, +}BT_8703B_1ANT_COEX_ALGO,*PBT_8703B_1ANT_COEX_ALGO; + +typedef struct _COEX_DM_8703B_1ANT{ + // hw setting + u1Byte preAntPosType; + u1Byte curAntPosType; + // fw mechanism + BOOLEAN bCurIgnoreWlanAct; + BOOLEAN bPreIgnoreWlanAct; + u1Byte prePsTdma; + u1Byte curPsTdma; + u1Byte psTdmaPara[5]; + u1Byte psTdmaDuAdjType; + BOOLEAN bAutoTdmaAdjust; + BOOLEAN bPrePsTdmaOn; + BOOLEAN bCurPsTdmaOn; + BOOLEAN bPreBtAutoReport; + BOOLEAN bCurBtAutoReport; + u1Byte preLps; + u1Byte curLps; + u1Byte preRpwm; + u1Byte curRpwm; + + // sw mechanism + BOOLEAN bPreLowPenaltyRa; + BOOLEAN bCurLowPenaltyRa; + u4Byte preVal0x6c0; + u4Byte curVal0x6c0; + u4Byte preVal0x6c4; + u4Byte curVal0x6c4; + u4Byte preVal0x6c8; + u4Byte curVal0x6c8; + u1Byte preVal0x6cc; + u1Byte curVal0x6cc; + BOOLEAN bLimitedDig; + + u4Byte backupArfrCnt1; // Auto Rate Fallback Retry cnt + u4Byte backupArfrCnt2; // Auto Rate Fallback Retry cnt + u2Byte backupRetryLimit; + u1Byte backupAmpduMaxTime; + + // algorithm related + u1Byte preAlgorithm; + u1Byte curAlgorithm; + u1Byte btStatus; + u1Byte wifiChnlInfo[3]; + + u4Byte preRaMask; + u4Byte curRaMask; + u1Byte preArfrType; + u1Byte curArfrType; + u1Byte preRetryLimitType; + u1Byte curRetryLimitType; + u1Byte preAmpduTimeType; + u1Byte curAmpduTimeType; + u4Byte nArpCnt; + + u1Byte errorCondition; +} COEX_DM_8703B_1ANT, *PCOEX_DM_8703B_1ANT; + +typedef struct _COEX_STA_8703B_1ANT{ + BOOLEAN bBtLinkExist; + BOOLEAN bScoExist; + BOOLEAN bA2dpExist; + BOOLEAN bHidExist; + BOOLEAN bPanExist; + BOOLEAN bBtHiPriLinkExist; + u1Byte nNumOfProfile; + + BOOLEAN bUnderLps; + BOOLEAN bUnderIps; + u4Byte specialPktPeriodCnt; + u4Byte highPriorityTx; + u4Byte highPriorityRx; + u4Byte lowPriorityTx; + u4Byte lowPriorityRx; + s1Byte btRssi; + BOOLEAN bBtTxRxMask; + u1Byte preBtRssiState; + u1Byte preWifiRssiState[4]; + BOOLEAN bC2hBtInfoReqSent; + u1Byte btInfoC2h[BT_INFO_SRC_8703B_1ANT_MAX][10]; + u4Byte btInfoC2hCnt[BT_INFO_SRC_8703B_1ANT_MAX]; + BOOLEAN bBtWhckTest; + BOOLEAN bC2hBtInquiryPage; + BOOLEAN bC2hBtPage; //Add for win8.1 page out issue + BOOLEAN bWiFiIsHighPriTask; //Add for win8.1 page out issue + u1Byte btRetryCnt; + u1Byte btInfoExt; + u4Byte popEventCnt; + u1Byte nScanAPNum; + + u4Byte nCRCOK_CCK; + u4Byte nCRCOK_11g; + u4Byte nCRCOK_11n; + u4Byte nCRCOK_11nAgg; + + u4Byte nCRCErr_CCK; + u4Byte nCRCErr_11g; + u4Byte nCRCErr_11n; + u4Byte nCRCErr_11nAgg; + + BOOLEAN bCCKLock; + BOOLEAN bPreCCKLock; + BOOLEAN bCCKEverLock; + u1Byte nCoexTableType; + + BOOLEAN bForceLpsOn; + u4Byte wrongProfileNotification; + + BOOLEAN bConCurrentRxModeOn; + + u2Byte nScoreBoard; +}COEX_STA_8703B_1ANT, *PCOEX_STA_8703B_1ANT; + +#define BT_8703B_1ANT_ANTDET_PSD_POINTS 256 //MAX:1024 +#define BT_8703B_1ANT_ANTDET_PSD_AVGNUM 1 //MAX:3 +#define BT_8703B_1ANT_ANTDET_BUF_LEN 16 + +typedef struct _PSDSCAN_STA_8703B_1ANT{ + +u4Byte nAntDet_BTLEChannel; //BT LE Channel ex:2412 +u4Byte nAntDet_BTTxTime; +u4Byte nAntDet_PrePSDScanPeakVal; +BOOLEAN nAntDet_IsAntDetAvailable; +u4Byte nAntDet_PSDScanPeakVal; +BOOLEAN nAntDet_IsBTReplyAvailable; +u4Byte nAntDet_PSDScanPeakFreq; + +u1Byte nAntDet_Result; +u1Byte nAntDet_PeakVal[BT_8703B_1ANT_ANTDET_BUF_LEN]; +u1Byte nAntDet_PeakFreq[BT_8703B_1ANT_ANTDET_BUF_LEN]; +u4Byte bAntDet_TryCount; +u4Byte bAntDet_FailCount; +u4Byte nAntDet_IntevalCount; +u4Byte nAntDet_ThresOffset; + +u4Byte nRealCentFreq; +s4Byte nRealOffset; +u4Byte nRealSpan; + +u4Byte nPSDBandWidth; //unit: Hz +u4Byte nPSDPoint; //128/256/512/1024 +u4Byte nPSDReport[1024]; //unit:dB (20logx), 0~255 +u4Byte nPSDReport_MaxHold[1024]; //unit:dB (20logx), 0~255 +u4Byte nPSDStartPoint; +u4Byte nPSDStopPoint; +u4Byte nPSDMaxValuePoint; +u4Byte nPSDMaxValue; +u4Byte nPSDStartBase; +u4Byte nPSDAvgNum; // 1/8/16/32 +u4Byte nPSDGenCount; +BOOLEAN bIsPSDRunning; +BOOLEAN bIsPSDShowMaxOnly; +} PSDSCAN_STA_8703B_1ANT, *PPSDSCAN_STA_8703B_1ANT; + +//=========================================== +// The following is interface which will notify coex module. +//=========================================== +VOID +EXhalbtc8703b1ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8703b1ant_PreLoadFirmware( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8703b1ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ); +VOID +EXhalbtc8703b1ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8703b1ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8703b1ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8703b1ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8703b1ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8703b1ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8703b1ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8703b1ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ); +VOID +EXhalbtc8703b1ant_RfStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8703b1ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8703b1ant_PnpNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte pnpState + ); +VOID +EXhalbtc8703b1ant_ScoreBoardStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ); +VOID +EXhalbtc8703b1ant_CoexDmReset( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8703b1ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8703b1ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8703b1ant_AntennaDetection( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte centFreq, + IN u4Byte offset, + IN u4Byte span, + IN u4Byte seconds + ); +VOID +EXhalbtc8703b1ant_AntennaIsolation( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte centFreq, + IN u4Byte offset, + IN u4Byte span, + IN u4Byte seconds + ); + +VOID +EXhalbtc8703b1ant_PSDScan( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte centFreq, + IN u4Byte offset, + IN u4Byte span, + IN u4Byte seconds + ); +VOID +EXhalbtc8703b1ant_DisplayAntDetection( + IN PBTC_COEXIST pBtCoexist + ); + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8703b2Ant.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8703b2Ant.c new file mode 100644 index 000000000..2f5d202a2 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8703b2Ant.c @@ -0,0 +1,4865 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//============================================================ +// Description: +// +// This file is for RTL8703B Co-exist mechanism +// +// History +// 2012/11/15 Cosa first check in. +// +//============================================================ + +//============================================================ +// include files +//============================================================ +#include "Mp_Precomp.h" + +#if WPP_SOFTWARE_TRACE +#include "HalBtc8703b2Ant.tmh" +#endif + +#if(BT_30_SUPPORT == 1) +//============================================================ +// Global variables, these are static variables +//============================================================ +static COEX_DM_8703B_2ANT GLCoexDm8703b2Ant; +static PCOEX_DM_8703B_2ANT pCoexDm=&GLCoexDm8703b2Ant; +static COEX_STA_8703B_2ANT GLCoexSta8703b2Ant; +static PCOEX_STA_8703B_2ANT pCoexSta=&GLCoexSta8703b2Ant; + +const char *const GLBtInfoSrc8703b2Ant[]={ + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; + +u4Byte GLCoexVerDate8703b2Ant=20140903; +u4Byte GLCoexVer8703b2Ant=0x43; + +//============================================================ +// local function proto type if needed +//============================================================ +//============================================================ +// local function start with halbtc8703b2ant_ +//============================================================ +u1Byte +halbtc8703b2ant_BtRssiState( + u1Byte levelNum, + u1Byte rssiThresh, + u1Byte rssiThresh1 + ) +{ + s4Byte btRssi=0; + u1Byte btRssiState=pCoexSta->preBtRssiState; + + btRssi = pCoexSta->btRssi; + + if(levelNum == 2) + { + if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW)) + { + if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8703B_2ANT)) + { + btRssiState = BTC_RSSI_STATE_HIGH; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else + { + if(btRssi < rssiThresh) + { + btRssiState = BTC_RSSI_STATE_LOW; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + else if(levelNum == 3) + { + if(rssiThresh > rssiThresh1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Rssi thresh error!!\n")); + return pCoexSta->preBtRssiState; + } + + if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW)) + { + if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8703B_2ANT)) + { + btRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_MEDIUM) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_MEDIUM)) + { + if(btRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8703B_2ANT)) + { + btRssiState = BTC_RSSI_STATE_HIGH; + } + else if(btRssi < rssiThresh) + { + btRssiState = BTC_RSSI_STATE_LOW; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_MEDIUM; + } + } + else + { + if(btRssi < rssiThresh1) + { + btRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + + pCoexSta->preBtRssiState = btRssiState; + + return btRssiState; +} + +u1Byte +halbtc8703b2ant_WifiRssiState( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte index, + IN u1Byte levelNum, + IN u1Byte rssiThresh, + IN u1Byte rssiThresh1 + ) +{ + s4Byte wifiRssi=0; + u1Byte wifiRssiState=pCoexSta->preWifiRssiState[index]; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); + + if(levelNum == 2) + { + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8703B_2ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else + { + if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + else if(levelNum == 3) + { + if(rssiThresh > rssiThresh1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi RSSI thresh error!!\n")); + return pCoexSta->preWifiRssiState[index]; + } + + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8703B_2ANT)) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_MEDIUM) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_MEDIUM)) + { + if(wifiRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8703B_2ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_MEDIUM; + } + } + else + { + if(wifiRssi < rssiThresh1) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + + pCoexSta->preWifiRssiState[index] = wifiRssiState; + + return wifiRssiState; +} + +VOID +halbtc8703b2ant_MonitorBtEnableDisable( + IN PBTC_COEXIST pBtCoexist + ) +{ + static BOOLEAN bPreBtDisabled=FALSE; + static u4Byte btDisableCnt=0; + BOOLEAN bBtActive=TRUE, bBtDisabled=FALSE; + + // This function check if bt is disabled + + if( pCoexSta->highPriorityTx == 0 && + pCoexSta->highPriorityRx == 0 && + pCoexSta->lowPriorityTx == 0 && + pCoexSta->lowPriorityRx == 0) + { + bBtActive = FALSE; + } + if( pCoexSta->highPriorityTx == 0xffff && + pCoexSta->highPriorityRx == 0xffff && + pCoexSta->lowPriorityTx == 0xffff && + pCoexSta->lowPriorityRx == 0xffff) + { + bBtActive = FALSE; + } + if(bBtActive) + { + btDisableCnt = 0; + bBtDisabled = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is enabled !!\n")); + } + else + { + btDisableCnt++; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], bt all counters=0, %d times!!\n", + btDisableCnt)); + if(btDisableCnt >= 2) + { + bBtDisabled = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is disabled !!\n")); + } + } + if(bPreBtDisabled != bBtDisabled) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is from %s to %s!!\n", + (bPreBtDisabled ? "disabled":"enabled"), + (bBtDisabled ? "disabled":"enabled"))); + bPreBtDisabled = bBtDisabled; + if(!bBtDisabled) + { + } + else + { + } + } +} + +VOID +halbtc8703b2ant_LimitedRx( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bRejApAggPkt, + IN BOOLEAN bBtCtrlAggBufSize, + IN u1Byte aggBufSize + ) +{ + BOOLEAN bRejectRxAgg=bRejApAggPkt; + BOOLEAN bBtCtrlRxAggSize=bBtCtrlAggBufSize; + u1Byte rxAggSize=aggBufSize; + + //============================================ + // Rx Aggregation related setting + //============================================ + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, &bRejectRxAgg); + // decide BT control aggregation buf size or not + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, &bBtCtrlRxAggSize); + // aggregation buf size, only work when BT control Rx aggregation size. + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_AGG_BUF_SIZE, &rxAggSize); + // real update aggregation setting + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); +} + +VOID +halbtc8703b2ant_MonitorBtCtr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte regHPTxRx, regLPTxRx, u4Tmp; + u4Byte regHPTx=0, regHPRx=0, regLPTx=0, regLPRx=0; + u1Byte u1Tmp; + + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + + regHPTxRx = 0x770; + regLPTxRx = 0x774; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regHPTxRx); + regHPTx = u4Tmp & bMaskLWord; + regHPRx = (u4Tmp & bMaskHWord)>>16; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regLPTxRx); + regLPTx = u4Tmp & bMaskLWord; + regLPRx = (u4Tmp & bMaskHWord)>>16; + + pCoexSta->highPriorityTx = regHPTx; + pCoexSta->highPriorityRx = regHPRx; + pCoexSta->lowPriorityTx = regLPTx; + pCoexSta->lowPriorityRx = regLPRx; + + if ( (pCoexSta->lowPriorityRx >= 950) && (pCoexSta->lowPriorityRx >= pCoexSta->lowPriorityTx) && (!pCoexSta->bUnderIps) ) + { + pBtLinkInfo->bSlaveRole = TRUE; + } + else + { + pBtLinkInfo->bSlaveRole = FALSE; + } + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", + regHPTxRx, regHPTx, regHPTx, regHPRx, regHPRx)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", + regLPTxRx, regLPTx, regLPTx, regLPRx, regLPRx)); + + // reset counter + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0xc); +} + +VOID +halbtc8703b2ant_MonitorWiFiCtr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte u4Tmp; + u2Byte u2Tmp[3]; + s4Byte wifiRssi=0; + BOOLEAN bWifiBusy = FALSE, bWifiUnderBMode = FALSE; + static u1Byte nCCKLockCounter = 0; + + + if (pCoexSta->bUnderIps) + { + pCoexSta->nCRCOK_CCK = 0; + pCoexSta->nCRCOK_11g = 0; + pCoexSta->nCRCOK_11n = 0; + pCoexSta->nCRCOK_11nAgg = 0; + + pCoexSta->nCRCErr_CCK = 0; + pCoexSta->nCRCErr_11g = 0; + pCoexSta->nCRCErr_11n = 0; + pCoexSta->nCRCErr_11nAgg = 0; + } + else + { + pCoexSta->nCRCOK_CCK = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xf88); + pCoexSta->nCRCOK_11g = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf94); + pCoexSta->nCRCOK_11n = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf90); + pCoexSta->nCRCOK_11nAgg= pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xfb8); + + pCoexSta->nCRCErr_CCK = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xf84); + pCoexSta->nCRCErr_11g = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf96); + pCoexSta->nCRCErr_11n = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf92); + pCoexSta->nCRCErr_11nAgg = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xfba); + } + + //reset counter + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xf16, 0x1, 0x1); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xf16, 0x1, 0x0); +} + +VOID +halbtc8703b2ant_QueryBtInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + pCoexSta->bC2hBtInfoReqSent = TRUE; + + H2C_Parameter[0] |= BIT0; // trigger + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Query Bt Info, FW write 0x61=0x%x\n", + H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x61, 1, H2C_Parameter); +} + +BOOLEAN +halbtc8703b2ant_IsWifiStatusChanged( + IN PBTC_COEXIST pBtCoexist + ) +{ + static BOOLEAN bPreWifiBusy=FALSE, bPreUnder4way=FALSE, bPreBtHsOn=FALSE; + BOOLEAN bWifiBusy=FALSE, bUnder4way=FALSE, bBtHsOn=FALSE; + BOOLEAN bWifiConnected=FALSE; + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH; + + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &bUnder4way); + + if(bWifiConnected) + { + if(bWifiBusy != bPreWifiBusy) + { + bPreWifiBusy = bWifiBusy; + return TRUE; + } + if(bUnder4way != bPreUnder4way) + { + bPreUnder4way = bUnder4way; + return TRUE; + } + if(bBtHsOn != bPreBtHsOn) + { + bPreBtHsOn = bBtHsOn; + return TRUE; + } + + + wifiRssiState = halbtc8703b2ant_WifiRssiState(pBtCoexist,3, 2, BT_8703B_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + + if ( (BTC_RSSI_STATE_HIGH ==wifiRssiState ) || (BTC_RSSI_STATE_LOW ==wifiRssiState )) + { + return TRUE; + } + + } + + return FALSE; +} + +VOID +halbtc8703b2ant_UpdateBtLinkInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bBtHsOn=FALSE; + +#if(BT_AUTO_REPORT_ONLY_8703B_2ANT == 1) // profile from bt patch + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + pBtLinkInfo->bBtLinkExist = pCoexSta->bBtLinkExist; + pBtLinkInfo->bScoExist = pCoexSta->bScoExist; + pBtLinkInfo->bA2dpExist = pCoexSta->bA2dpExist; + pBtLinkInfo->bPanExist = pCoexSta->bPanExist; + pBtLinkInfo->bHidExist = pCoexSta->bHidExist; + + // work around for HS mode. + if(bBtHsOn) + { + pBtLinkInfo->bPanExist = TRUE; + pBtLinkInfo->bBtLinkExist = TRUE; + } +#else // profile from bt stack + pBtLinkInfo->bBtLinkExist = pStackInfo->bBtLinkExist; + pBtLinkInfo->bScoExist = pStackInfo->bScoExist; + pBtLinkInfo->bA2dpExist = pStackInfo->bA2dpExist; + pBtLinkInfo->bPanExist = pStackInfo->bPanExist; + pBtLinkInfo->bHidExist = pStackInfo->bHidExist; + + //for win-8 stack HID report error + if(!pStackInfo->bHidExist) + pStackInfo->bHidExist = pCoexSta->bHidExist; //sync BTInfo with BT firmware and stack + // when stack HID report error, here we use the info from bt fw. + if(!pStackInfo->bBtLinkExist) + pStackInfo->bBtLinkExist = pCoexSta->bBtLinkExist; +#endif + // check if Sco only + if( pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bScoOnly = TRUE; + else + pBtLinkInfo->bScoOnly = FALSE; + + // check if A2dp only + if( !pBtLinkInfo->bScoExist && + pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bA2dpOnly = TRUE; + else + pBtLinkInfo->bA2dpOnly = FALSE; + + // check if Pan only + if( !pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bPanOnly = TRUE; + else + pBtLinkInfo->bPanOnly = FALSE; + + // check if Hid only + if( !pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + pBtLinkInfo->bHidExist ) + pBtLinkInfo->bHidOnly = TRUE; + else + pBtLinkInfo->bHidOnly = FALSE; +} + +u1Byte +halbtc8703b2ant_ActionAlgorithm( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bBtHsOn=FALSE; + u1Byte algorithm=BT_8703B_2ANT_COEX_ALGO_UNDEFINED; + u1Byte numOfDiffProfile=0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + if(!pBtLinkInfo->bBtLinkExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], No BT link exists!!!\n")); + return algorithm; + } + + if(pBtLinkInfo->bScoExist) + numOfDiffProfile++; + if(pBtLinkInfo->bHidExist) + numOfDiffProfile++; + if(pBtLinkInfo->bPanExist) + numOfDiffProfile++; + if(pBtLinkInfo->bA2dpExist) + numOfDiffProfile++; + + if(numOfDiffProfile == 1) + { + if(pBtLinkInfo->bScoExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO only\n")); + algorithm = BT_8703B_2ANT_COEX_ALGO_SCO; + } + else + { + if(pBtLinkInfo->bHidExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID only\n")); + algorithm = BT_8703B_2ANT_COEX_ALGO_HID; + } + else if(pBtLinkInfo->bA2dpExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP only\n")); + algorithm = BT_8703B_2ANT_COEX_ALGO_A2DP; + } + else if(pBtLinkInfo->bPanExist) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN(HS) only\n")); + algorithm = BT_8703B_2ANT_COEX_ALGO_PANHS; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN(EDR) only\n")); + algorithm = BT_8703B_2ANT_COEX_ALGO_PANEDR; + } + } + } + } + else if(numOfDiffProfile == 2) + { + if(pBtLinkInfo->bScoExist) + { + if(pBtLinkInfo->bHidExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID\n")); + algorithm = BT_8703B_2ANT_COEX_ALGO_PANEDR_HID; + } + else if(pBtLinkInfo->bA2dpExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + A2DP ==> SCO\n")); + algorithm = BT_8703B_2ANT_COEX_ALGO_PANEDR_HID; + } + else if(pBtLinkInfo->bPanExist) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + PAN(HS)\n")); + algorithm = BT_8703B_2ANT_COEX_ALGO_SCO; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + PAN(EDR)\n")); + algorithm = BT_8703B_2ANT_COEX_ALGO_PANEDR_HID; + } + } + } + else + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bA2dpExist ) + { +#if 0 + if(pStackInfo->numOfHid >= 2) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID*2 + A2DP\n")); + algorithm = BT_8703B_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + else +#endif + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP\n")); + algorithm = BT_8703B_2ANT_COEX_ALGO_HID_A2DP; + } + } + else if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + PAN(HS)\n")); + algorithm = BT_8703B_2ANT_COEX_ALGO_HID; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + PAN(EDR)\n")); + algorithm = BT_8703B_2ANT_COEX_ALGO_PANEDR_HID; + } + } + else if( pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP + PAN(HS)\n")); + algorithm = BT_8703B_2ANT_COEX_ALGO_A2DP_PANHS; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP + PAN(EDR)\n")); + algorithm = BT_8703B_2ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } + } + else if(numOfDiffProfile == 3) + { + if(pBtLinkInfo->bScoExist) + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bA2dpExist ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + A2DP ==> HID\n")); + algorithm = BT_8703B_2ANT_COEX_ALGO_PANEDR_HID; + } + else if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + PAN(HS)\n")); + algorithm = BT_8703B_2ANT_COEX_ALGO_PANEDR_HID; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + PAN(EDR)\n")); + algorithm = BT_8703B_2ANT_COEX_ALGO_PANEDR_HID; + } + } + else if( pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + A2DP + PAN(HS)\n")); + algorithm = BT_8703B_2ANT_COEX_ALGO_PANEDR_HID; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n")); + algorithm = BT_8703B_2ANT_COEX_ALGO_PANEDR_HID; + } + } + } + else + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP + PAN(HS)\n")); + algorithm = BT_8703B_2ANT_COEX_ALGO_HID_A2DP; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP + PAN(EDR)\n")); + algorithm = BT_8703B_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } + else if(numOfDiffProfile >= 3) + { + if(pBtLinkInfo->bScoExist) + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n")); + + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n")); + algorithm = BT_8703B_2ANT_COEX_ALGO_PANEDR_HID; + } + } + } + } + + return algorithm; +} + +VOID +halbtc8703b2ant_SetFwDacSwingLevel( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte dacSwingLvl + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + // There are several type of dacswing + // 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 + H2C_Parameter[0] = dacSwingLvl; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Set Dac Swing Level=0x%x\n", dacSwingLvl)); + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x64=0x%x\n", H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x64, 1, H2C_Parameter); +} + +VOID +halbtc8703b2ant_SetFwDecBtPwr( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte decBtPwrLvl + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + H2C_Parameter[0] = decBtPwrLvl; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], decrease Bt Power level = %d, FW write 0x62=0x%x\n", + decBtPwrLvl, H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x62, 1, H2C_Parameter); +} + +VOID +halbtc8703b2ant_DecBtPwr( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte decBtPwrLvl + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s Dec BT power level = %d\n", + (bForceExec? "force to":""), decBtPwrLvl)); + pCoexDm->curBtDecPwrLvl = decBtPwrLvl; + + if(!bForceExec) + { + if(pCoexDm->preBtDecPwrLvl == pCoexDm->curBtDecPwrLvl) + return; + } + halbtc8703b2ant_SetFwDecBtPwr(pBtCoexist, pCoexDm->curBtDecPwrLvl); + + pCoexDm->preBtDecPwrLvl = pCoexDm->curBtDecPwrLvl; +} + +VOID +halbtc8703b2ant_SetBtAutoReport( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bEnableAutoReport + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + H2C_Parameter[0] = 0; + + if(bEnableAutoReport) + { + H2C_Parameter[0] |= BIT0; + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], BT FW auto report : %s, FW write 0x68=0x%x\n", + (bEnableAutoReport? "Enabled!!":"Disabled!!"), H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x68, 1, H2C_Parameter); +} + +VOID +halbtc8703b2ant_BtAutoReport( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bEnableAutoReport + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s BT Auto report = %s\n", + (bForceExec? "force to":""), ((bEnableAutoReport)? "Enabled":"Disabled"))); + pCoexDm->bCurBtAutoReport = bEnableAutoReport; + + if(!bForceExec) + { + if(pCoexDm->bPreBtAutoReport == pCoexDm->bCurBtAutoReport) + return; + } + halbtc8703b2ant_SetBtAutoReport(pBtCoexist, pCoexDm->bCurBtAutoReport); + + pCoexDm->bPreBtAutoReport = pCoexDm->bCurBtAutoReport; +} + +VOID +halbtc8703b2ant_FwDacSwingLvl( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte fwDacSwingLvl + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s set FW Dac Swing level = %d\n", + (bForceExec? "force to":""), fwDacSwingLvl)); + pCoexDm->curFwDacSwingLvl = fwDacSwingLvl; + + if(!bForceExec) + { + if(pCoexDm->preFwDacSwingLvl == pCoexDm->curFwDacSwingLvl) + return; + } + + halbtc8703b2ant_SetFwDacSwingLevel(pBtCoexist, pCoexDm->curFwDacSwingLvl); + + pCoexDm->preFwDacSwingLvl = pCoexDm->curFwDacSwingLvl; +} + +VOID +halbtc8703b2ant_SetSwRfRxLpfCorner( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bRxRfShrinkOn + ) +{ + if(bRxRfShrinkOn) + { + //Shrink RF Rx LPF corner + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Shrink RF Rx LPF corner!!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, 0xffffc); + } + else + { + //Resume RF Rx LPF corner + // After initialized, we can use pCoexDm->btRf0x1eBackup + if(pBtCoexist->bInitilized) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Resume RF Rx LPF corner!!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, pCoexDm->btRf0x1eBackup); + } + } +} + +VOID +halbtc8703b2ant_RfShrink( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bRxRfShrinkOn + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Rx RF Shrink = %s\n", + (bForceExec? "force to":""), ((bRxRfShrinkOn)? "ON":"OFF"))); + pCoexDm->bCurRfRxLpfShrink = bRxRfShrinkOn; + + if(!bForceExec) + { + if(pCoexDm->bPreRfRxLpfShrink == pCoexDm->bCurRfRxLpfShrink) + return; + } + halbtc8703b2ant_SetSwRfRxLpfCorner(pBtCoexist, pCoexDm->bCurRfRxLpfShrink); + + pCoexDm->bPreRfRxLpfShrink = pCoexDm->bCurRfRxLpfShrink; +} + +VOID +halbtc8703b2ant_SetSwPenaltyTxRateAdaptive( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bLowPenaltyRa + ) +{ + u1Byte H2C_Parameter[6] ={0}; + + H2C_Parameter[0] = 0x6; // opCode, 0x6= Retry_Penalty + + if(bLowPenaltyRa) + { + H2C_Parameter[1] |= BIT0; + H2C_Parameter[2] = 0x00; //normal rate except MCS7/6/5, OFDM54/48/36 + H2C_Parameter[3] = 0xf7; //MCS7 or OFDM54 + H2C_Parameter[4] = 0xf8; //MCS6 or OFDM48 + H2C_Parameter[5] = 0xf9; //MCS5 or OFDM36 + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set WiFi Low-Penalty Retry: %s", + (bLowPenaltyRa? "ON!!":"OFF!!")) ); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x69, 6, H2C_Parameter); +} + +VOID +halbtc8703b2ant_LowPenaltyRa( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bLowPenaltyRa + ) +{ + //return; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn LowPenaltyRA = %s\n", + (bForceExec? "force to":""), ((bLowPenaltyRa)? "ON":"OFF"))); + pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa; + + if(!bForceExec) + { + if(pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa) + return; + } + halbtc8703b2ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa); + + pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa; +} + +VOID +halbtc8703b2ant_SetDacSwingReg( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte level + ) +{ + u1Byte val=(u1Byte)level; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Write SwDacSwing = 0x%x\n", level)); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x883, 0x3e, val); +} + +VOID +halbtc8703b2ant_SetSwFullTimeDacSwing( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bSwDacSwingOn, + IN u4Byte swDacSwingLvl + ) +{ + if(bSwDacSwingOn) + { + halbtc8703b2ant_SetDacSwingReg(pBtCoexist, swDacSwingLvl); + } + else + { + halbtc8703b2ant_SetDacSwingReg(pBtCoexist, 0x18); + } +} + + +VOID +halbtc8703b2ant_DacSwing( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bDacSwingOn, + IN u4Byte dacSwingLvl + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn DacSwing=%s, dacSwingLvl=0x%x\n", + (bForceExec? "force to":""), ((bDacSwingOn)? "ON":"OFF"), dacSwingLvl)); + pCoexDm->bCurDacSwingOn = bDacSwingOn; + pCoexDm->curDacSwingLvl = dacSwingLvl; + + if(!bForceExec) + { + if( (pCoexDm->bPreDacSwingOn == pCoexDm->bCurDacSwingOn) && + (pCoexDm->preDacSwingLvl == pCoexDm->curDacSwingLvl) ) + return; + } + delay_ms(30); + halbtc8703b2ant_SetSwFullTimeDacSwing(pBtCoexist, bDacSwingOn, dacSwingLvl); + + pCoexDm->bPreDacSwingOn = pCoexDm->bCurDacSwingOn; + pCoexDm->preDacSwingLvl = pCoexDm->curDacSwingLvl; +} + +VOID +halbtc8703b2ant_SetAdcBackOff( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bAdcBackOff + ) +{ + if(bAdcBackOff) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level On!\n")); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xc05, 0x30, 0x3); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level Off!\n")); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xc05, 0x30, 0x1); + } +} + +VOID +halbtc8703b2ant_AdcBackOff( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bAdcBackOff + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn AdcBackOff = %s\n", + (bForceExec? "force to":""), ((bAdcBackOff)? "ON":"OFF"))); + pCoexDm->bCurAdcBackOff = bAdcBackOff; + + if(!bForceExec) + { + if(pCoexDm->bPreAdcBackOff == pCoexDm->bCurAdcBackOff) + return; + } + halbtc8703b2ant_SetAdcBackOff(pBtCoexist, pCoexDm->bCurAdcBackOff); + + pCoexDm->bPreAdcBackOff = pCoexDm->bCurAdcBackOff; +} + +VOID +halbtc8703b2ant_SetAgcTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bAgcTableEn + ) +{ + u1Byte rssiAdjustVal=0; + + //=================BB AGC Gain Table + if(bAgcTableEn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB Agc Table On!\n")); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6e1A0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6d1B0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6c1C0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6b1D0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6a1E0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x691F0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x68200001); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB Agc Table Off!\n")); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xaa1A0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa91B0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa81C0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa71D0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa61E0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa51F0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa4200001); + } + + + //=================RF Gain + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000); + if(bAgcTableEn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table On!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x38fff); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x38ffe); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table Off!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x380c3); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x28ce6); + } + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xef, 0xfffff, 0x0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xed, 0xfffff, 0x1); + if(bAgcTableEn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table On!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x40, 0xfffff, 0x38fff); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x40, 0xfffff, 0x38ffe); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table Off!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x40, 0xfffff, 0x380c3); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x40, 0xfffff, 0x28ce6); + } + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xed, 0xfffff, 0x0); + + // set rssiAdjustVal for wifi module. + if(bAgcTableEn) + { + rssiAdjustVal = 8; + } + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, &rssiAdjustVal); +} + +VOID +halbtc8703b2ant_AgcTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bAgcTableEn + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s %s Agc Table\n", + (bForceExec? "force to":""), ((bAgcTableEn)? "Enable":"Disable"))); + pCoexDm->bCurAgcTableEn = bAgcTableEn; + + if(!bForceExec) + { + if(pCoexDm->bPreAgcTableEn == pCoexDm->bCurAgcTableEn) + return; + } + halbtc8703b2ant_SetAgcTable(pBtCoexist, bAgcTableEn); + + pCoexDm->bPreAgcTableEn = pCoexDm->bCurAgcTableEn; +} + +VOID +halbtc8703b2ant_SetCoexTable( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte val0x6c0, + IN u4Byte val0x6c4, + IN u4Byte val0x6c8, + IN u1Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c0=0x%x\n", val0x6c0)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c0, val0x6c0); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c4=0x%x\n", val0x6c4)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c4, val0x6c4); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, val0x6c8); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc)); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cc, val0x6cc); +} + +VOID +halbtc8703b2ant_CoexTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u4Byte val0x6c0, + IN u4Byte val0x6c4, + IN u4Byte val0x6c8, + IN u1Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s write Coex Table 0x6c0=0x%x, 0x6c4=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n", + (bForceExec? "force to":""), val0x6c0, val0x6c4, val0x6c8, val0x6cc)); + pCoexDm->curVal0x6c0 = val0x6c0; + pCoexDm->curVal0x6c4 = val0x6c4; + pCoexDm->curVal0x6c8 = val0x6c8; + pCoexDm->curVal0x6cc = val0x6cc; + + if(!bForceExec) + { + if( (pCoexDm->preVal0x6c0 == pCoexDm->curVal0x6c0) && + (pCoexDm->preVal0x6c4 == pCoexDm->curVal0x6c4) && + (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) && + (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) ) + return; + } + halbtc8703b2ant_SetCoexTable(pBtCoexist, val0x6c0, val0x6c4, val0x6c8, val0x6cc); + + pCoexDm->preVal0x6c0 = pCoexDm->curVal0x6c0; + pCoexDm->preVal0x6c4 = pCoexDm->curVal0x6c4; + pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8; + pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc; +} + +VOID +halbtc8703b2ant_CoexTableWithType( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + pCoexSta->nCoexTableType = type; + + switch(type) + { + case 0: + halbtc8703b2ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x55555555, 0xffffff, 0x3); + break; + case 1: + halbtc8703b2ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x5afa5afa, 0xffffff, 0x3); + break; + case 2: + halbtc8703b2ant_CoexTable(pBtCoexist, bForceExec, 0x5ada5ada, 0x5ada5ada, 0xffffff, 0x3); + break; + case 3: + halbtc8703b2ant_CoexTable(pBtCoexist, bForceExec, 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3); + break; + case 4: + halbtc8703b2ant_CoexTable(pBtCoexist, bForceExec, 0xffffffff, 0xffffffff, 0xffffff, 0x3); + break; + case 5: + halbtc8703b2ant_CoexTable(pBtCoexist, bForceExec, 0x5fff5fff, 0x5fff5fff, 0xffffff, 0x3); + break; + case 6: + halbtc8703b2ant_CoexTable(pBtCoexist, bForceExec, 0x55ff55ff, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 7: + halbtc8703b2ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 8: + halbtc8703b2ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 9: + halbtc8703b2ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 10: + halbtc8703b2ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 11: + halbtc8703b2ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 12: + halbtc8703b2ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 13: + halbtc8703b2ant_CoexTable(pBtCoexist, bForceExec, 0x5fff5fff, 0xaaaaaaaa, 0xffffff, 0x3); + break; + case 14: + halbtc8703b2ant_CoexTable(pBtCoexist, bForceExec, 0x5fff5fff, 0x5ada5ada, 0xffffff, 0x3); + break; + case 15: + halbtc8703b2ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0xaaaaaaaa, 0xffffff, 0x3); + break; + default: + break; + } +} + +VOID +halbtc8703b2ant_SetFwIgnoreWlanAct( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bEnable + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + if(bEnable) + { + H2C_Parameter[0] |= BIT0; // function enable + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set FW for BT Ignore Wlan_Act, FW write 0x63=0x%x\n", + H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x63, 1, H2C_Parameter); +} + +VOID +halbtc8703b2ant_SetLpsRpwm( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + u1Byte lps=lpsVal; + u1Byte rpwm=rpwmVal; + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_LPS_VAL, &lps); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RPWM_VAL, &rpwm); +} + +VOID +halbtc8703b2ant_LpsRpwm( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + BOOLEAN bForceExecPwrCmd=FALSE; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s set lps/rpwm=0x%x/0x%x \n", + (bForceExec? "force to":""), lpsVal, rpwmVal)); + pCoexDm->curLps = lpsVal; + pCoexDm->curRpwm = rpwmVal; + + if(!bForceExec) + { + if( (pCoexDm->preLps == pCoexDm->curLps) && + (pCoexDm->preRpwm == pCoexDm->curRpwm) ) + { + return; + } + } + halbtc8703b2ant_SetLpsRpwm(pBtCoexist, lpsVal, rpwmVal); + + pCoexDm->preLps = pCoexDm->curLps; + pCoexDm->preRpwm = pCoexDm->curRpwm; +} + +VOID +halbtc8703b2ant_IgnoreWlanAct( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bEnable + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Ignore WlanAct %s\n", + (bForceExec? "force to":""), (bEnable? "ON":"OFF"))); + pCoexDm->bCurIgnoreWlanAct = bEnable; + + if(!bForceExec) + { + if(pCoexDm->bPreIgnoreWlanAct == pCoexDm->bCurIgnoreWlanAct) + return; + } + halbtc8703b2ant_SetFwIgnoreWlanAct(pBtCoexist, bEnable); + + pCoexDm->bPreIgnoreWlanAct = pCoexDm->bCurIgnoreWlanAct; +} + +VOID +halbtc8703b2ant_SetFwPstdma( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte byte1, + IN u1Byte byte2, + IN u1Byte byte3, + IN u1Byte byte4, + IN u1Byte byte5 + ) +{ + u1Byte H2C_Parameter[5] ={0}; + + + if ( (pCoexSta->bA2dpExist) && (pCoexSta->bHidExist) ) + { + byte5 = byte5 | 0x1; + } + + H2C_Parameter[0] = byte1; + H2C_Parameter[1] = byte2; + H2C_Parameter[2] = byte3; + H2C_Parameter[3] = byte4; + H2C_Parameter[4] = byte5; + + pCoexDm->psTdmaPara[0] = byte1; + pCoexDm->psTdmaPara[1] = byte2; + pCoexDm->psTdmaPara[2] = byte3; + pCoexDm->psTdmaPara[3] = byte4; + pCoexDm->psTdmaPara[4] = byte5; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x60(5bytes)=0x%x%08x\n", + H2C_Parameter[0], + H2C_Parameter[1]<<24|H2C_Parameter[2]<<16|H2C_Parameter[3]<<8|H2C_Parameter[4])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x60, 5, H2C_Parameter); +} + +VOID +halbtc8703b2ant_SwMechanism1( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bShrinkRxLPF, + IN BOOLEAN bLowPenaltyRA, + IN BOOLEAN bLimitedDIG, + IN BOOLEAN bBTLNAConstrain + ) +{ + /* + u4Byte wifiBw; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if(BTC_WIFI_BW_HT40 != wifiBw) //only shrink RF Rx LPF for HT40 + { + if (bShrinkRxLPF) + bShrinkRxLPF = FALSE; + } + */ + + //halbtc8703b2ant_RfShrink(pBtCoexist, NORMAL_EXEC, bShrinkRxLPF); + halbtc8703b2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, bLowPenaltyRA); +} + +VOID +halbtc8703b2ant_SwMechanism2( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bAGCTableShift, + IN BOOLEAN bADCBackOff, + IN BOOLEAN bSWDACSwing, + IN u4Byte dacSwingLvl + ) +{ + //halbtc8703b2ant_AgcTable(pBtCoexist, NORMAL_EXEC, bAGCTableShift); + //halbtc8703b2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, bADCBackOff); + //halbtc8703b2ant_DacSwing(pBtCoexist, NORMAL_EXEC, bSWDACSwing, dacSwingLvl); +} + +VOID +halbtc8703b2ant_SetAntPath( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte antPosType, + IN BOOLEAN bInitHwCfg, + IN BOOLEAN bWifiOff + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + u4Byte fwVer=0, u4Tmp=0; + BOOLEAN bPgExtSwitch=FALSE; + BOOLEAN bUseExtSwitch=FALSE; + u1Byte H2C_Parameter[2] ={0}; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_EXT_SWITCH, &bPgExtSwitch); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); // [31:16]=fw ver, [15:0]=fw sub ver + + if((fwVer>0 && fwVer<0xc0000) || bPgExtSwitch) + bUseExtSwitch = TRUE; + + if(bInitHwCfg) + { + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x39, 0x8, 0x1); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x974, 0xff); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x944, 0x3, 0x3); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x930, 0x77); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x67, 0x20, 0x1); + + if(fwVer >= 0x180000) + { + /* Use H2C to set GNT_BT to High to avoid A2DP click */ + H2C_Parameter[0] = 1; + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x6E, 1, H2C_Parameter); + } + else + { + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x765, 0x18); + } + + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); //WiFi TRx Mask off + //remove due to interrupt is disabled that polling c2h will fail and delay 100ms. + //pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x3c, 0x01); //BT TRx Mask off + + if(pBoardInfo->btdmAntPos == BTC_ANTENNA_AT_MAIN_PORT) + { + //tell firmware "no antenna inverse" + H2C_Parameter[0] = 0; + } + else + { + //tell firmware "antenna inverse" + H2C_Parameter[0] = 1; + } + + if (bUseExtSwitch) + { + //ext switch type + H2C_Parameter[1] = 1; + } + else + { + //int switch type + H2C_Parameter[1] = 0; + } + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x65, 2, H2C_Parameter); + } + else + { + if(fwVer >= 0x180000) + { + /* Use H2C to set GNT_BT to "Control by PTA"*/ + H2C_Parameter[0] = 0; + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x6E, 1, H2C_Parameter); + } + else + { + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x765, 0x0); + } + } + + // ext switch setting + if(bUseExtSwitch) + { + if (bInitHwCfg) + { + // 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x4c); + u4Tmp &=~BIT23; + u4Tmp |= BIT24; + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x4c, u4Tmp); + } + + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x0); // fixed internal switch S1->WiFi, S0->BT + switch(antPosType) + { + case BTC_ANT_WIFI_AT_MAIN: + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x92c, 0x3, 0x1); // ext switch main at wifi + break; + case BTC_ANT_WIFI_AT_AUX: + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x92c, 0x3, 0x2); // ext switch aux at wifi + break; + } + } + else // internal switch + { + if (bInitHwCfg) + { + // 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x4c); + u4Tmp |= BIT23; + u4Tmp &=~BIT24; + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x4c, u4Tmp); + } + + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x64, 0x1, 0x0); //fixed external switch S1->Main, S0->Aux + switch(antPosType) + { + case BTC_ANT_WIFI_AT_MAIN: + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x0); // fixed internal switch S1->WiFi, S0->BT + break; + case BTC_ANT_WIFI_AT_AUX: + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x280); // fixed internal switch S0->WiFi, S1->BT + break; + } + } +} + +VOID +halbtc8703b2ant_PsTdma( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bTurnOn, + IN u1Byte type + ) +{ + BOOLEAN bTurnOnByCnt=FALSE; + u1Byte psTdmaTypeByCnt=0; + u1Byte wifiRssiState1, btRssiState; + + + wifiRssiState1 = halbtc8703b2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8703B_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8703b2ant_BtRssiState(2, BT_8703B_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], %s turn %s PS TDMA, type=%d\n", + (bForceExec? "force to":""), (bTurnOn? "ON":"OFF"), type)); + pCoexDm->bCurPsTdmaOn = bTurnOn; + pCoexDm->curPsTdma = type; + + if (!(BTC_RSSI_HIGH(wifiRssiState1) && BTC_RSSI_HIGH(btRssiState)) && bTurnOn) + { + type = type +100; //for WiFi RSSI low or BT RSSI low + pCoexDm->bIsSwitchTo1dot5Ant = TRUE; + } + else + { + pCoexDm->bIsSwitchTo1dot5Ant = FALSE; + } + + + if(!bForceExec) + { + if( (pCoexDm->bPrePsTdmaOn == pCoexDm->bCurPsTdmaOn) && + (pCoexDm->prePsTdma == pCoexDm->curPsTdma) ) + return; + } + if(bTurnOn) + { + switch(type) + { + case 1: + default: + //halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x3c, 0x03, 0xf1, 0x90); + break; + case 2: + //halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0xe1, 0x90); + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x2d, 0x03, 0xf1, 0x90); + break; + case 3: + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1c, 0x3, 0xf1, 0x90); + break; + case 4: + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x10, 0x03, 0xf1, 0x90); + break; + case 5: + //halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x90); + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x3c, 0x3, 0x70, 0x90); + break; + case 6: + //halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0x60, 0x90); + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x2d, 0x3, 0x70, 0x90); + break; + case 7: + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1c, 0x3, 0x70, 0x90); + break; + case 8: + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xa3, 0x10, 0x3, 0x70, 0x90); + break; + case 9: + //halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x3c, 0x03, 0xf1, 0x90); + break; + case 10: + //halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0xe1, 0x90); + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x2d, 0x03, 0xf1, 0x90); + break; + case 11: + //halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0xa, 0xe1, 0x90); + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1c, 0x3, 0xf1, 0x90); + break; + case 12: + //halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0xe1, 0x90); + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x10, 0x3, 0xf1, 0x90); + break; + case 13: + //halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x90); + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x3c, 0x3, 0x70, 0x90); + break; + case 14: + //halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0x60, 0x90); + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x2d, 0x3, 0x70, 0x90); + break; + case 15: + //halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0xa, 0x60, 0x90); + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1c, 0x3, 0x70, 0x90); + break; + case 16: + //halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0x60, 0x90); + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x10, 0x3, 0x70, 0x90); + break; + case 17: + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xa3, 0x2f, 0x2f, 0x60, 0x90); + break; + case 18: + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0xe1, 0x90); + break; + case 19: + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x25, 0xe1, 0x90); + break; + case 20: + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x25, 0x60, 0x90); + break; + case 21: + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x15, 0x03, 0x70, 0x90); + break; + case 71: + //halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); + + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x3c, 0x03, 0xf1, 0x90); + break; + case 101: + case 105: + case 171: + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xd3, 0x3a, 0x03, 0x70, 0x50); + break; + case 102: + case 106: + case 110: + case 114: + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xd3, 0x2d, 0x03, 0x70, 0x50); + break; + case 103: + case 107: + case 111: + case 115: + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xd3, 0x1c, 0x03, 0x70, 0x50); + break; + case 104: + case 108: + case 112: + case 116: + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xd3, 0x10, 0x03, 0x70, 0x50); + break; + case 109: + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x3c, 0x03, 0xf1, 0x90); + break; + case 113: + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x3c, 0x03, 0x70, 0x90); + break; + case 121: + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x15, 0x03, 0x70, 0x90); + break; + case 22: + case 122: + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x35, 0x03, 0x71, 0x11); + break; + } + } + else + { + // disable PS tdma + switch(type) + { + case 0: + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x40, 0x0); + break; + case 1: + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x48, 0x0); + break; + default: + halbtc8703b2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x40, 0x0); + break; + } + } + + // update pre state + pCoexDm->bPrePsTdmaOn = pCoexDm->bCurPsTdmaOn; + pCoexDm->prePsTdma = pCoexDm->curPsTdma; +} + +VOID +halbtc8703b2ant_PsTdmaCheckForPowerSaveState( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bNewPsState + ) +{ + u1Byte lpsMode=0x0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_LPS_MODE, &lpsMode); + + if(lpsMode) // already under LPS state + { + if(bNewPsState) + { + // keep state under LPS, do nothing. + } + else + { + // will leave LPS state, turn off psTdma first + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + } + } + else // NO PS state + { + if(bNewPsState) + { + // will enter LPS state, turn off psTdma first + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + } + else + { + // keep state under NO PS state, do nothing. + } + } +} + +VOID +halbtc8703b2ant_PowerSaveState( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte psType, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + BOOLEAN bLowPwrDisable=FALSE; + + switch(psType) + { + case BTC_PS_WIFI_NATIVE: + // recover to original 32k low power setting + bLowPwrDisable = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_NORMAL_LPS, NULL); + pCoexSta->bForceLpsOn = FALSE; + break; + case BTC_PS_LPS_ON: + halbtc8703b2ant_PsTdmaCheckForPowerSaveState(pBtCoexist, TRUE); + halbtc8703b2ant_LpsRpwm(pBtCoexist, NORMAL_EXEC, lpsVal, rpwmVal); + // when coex force to enter LPS, do not enter 32k low power. + bLowPwrDisable = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + // power save must executed before psTdma. + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_ENTER_LPS, NULL); + pCoexSta->bForceLpsOn = TRUE; + break; + case BTC_PS_LPS_OFF: + halbtc8703b2ant_PsTdmaCheckForPowerSaveState(pBtCoexist, FALSE); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_LEAVE_LPS, NULL); + pCoexSta->bForceLpsOn = FALSE; + break; + default: + break; + } +} + + +VOID +halbtc8703b2ant_CoexAllOff( + IN PBTC_COEXIST pBtCoexist + ) +{ + // fw all off + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + halbtc8703b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + // sw all off + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + // hw all off + //pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); +} + +VOID +halbtc8703b2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + // force to reset coex mechanism + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8703b2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); + halbtc8703b2ant_FwDacSwingLvl(pBtCoexist, FORCE_EXEC, 6); + halbtc8703b2ant_DecBtPwr(pBtCoexist, FORCE_EXEC, 0); + + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); +} + +VOID +halbtc8703b2ant_ActionBtInquiry( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btRssiState; + BOOLEAN bWifiConnected=FALSE; + BOOLEAN bLowPwrDisable=TRUE; + BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE; + + + wifiRssiState = halbtc8703b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + wifiRssiState1 = halbtc8703b2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8703B_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8703b2ant_BtRssiState(2, BT_8703B_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + + + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + if(bScan || bLink || bRoam) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi link process + BT Inq/Page!!\n")); + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 15); + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 22); + } + else if(bWifiConnected) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi connected + BT Inq/Page!!\n")); + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 15); + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 22); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi no-link + BT Inq/Page!!\n")); + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + } + + halbtc8703b2ant_FwDacSwingLvl(pBtCoexist, FORCE_EXEC, 6); + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); +/* + pCoexDm->bNeedRecover0x948 = TRUE; + pCoexDm->backup0x948 = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x948); + + halbtc8703b2ant_SetAntPath(pBtCoexist, BTC_ANT_WIFI_AT_AUX, FALSE, FALSE); +*/ +} + + +VOID +halbtc8703b2ant_ActionWiFiLinkProcess( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte u4Tmp; + u1Byte u1Tmpa, u1Tmpb; + + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 15); + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 22); + + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x948); + u1Tmpa = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x765); + u1Tmpb = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x76e); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x76e=0x%x\n", + u4Tmp, u1Tmpa, u1Tmpb)); +} + +BOOLEAN +halbtc8703b2ant_ActionWifiIdleProcess( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btRssiState; + u4Byte wifiBw; + u1Byte apNum=0; + + wifiRssiState = halbtc8703b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + //wifiRssiState1 = halbtc8703b2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8703B_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + wifiRssiState1 = halbtc8703b2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8703B_2ANT_WIFI_RSSI_COEXSWITCH_THRES-20, 0); + btRssiState = halbtc8703b2ant_BtRssiState(2, BT_8703B_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_AP_NUM, &apNum); + + // define the office environment + if(BTC_RSSI_HIGH(wifiRssiState1) && + (pCoexSta->bHidExist == TRUE) && (pCoexSta->bA2dpExist == TRUE)) + { + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi idle process for BT HID+A2DP exist!!\n")); + + halbtc8703b2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x6); + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + // sw all off + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + + return TRUE; + } + else + { + halbtc8703b2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); + return FALSE; + } + + +} + + + +BOOLEAN +halbtc8703b2ant_IsCommonAction( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte btRssiState=BTC_RSSI_STATE_HIGH; + BOOLEAN bCommon=FALSE, bWifiConnected=FALSE, bWifiBusy=FALSE; + BOOLEAN bBtHsOn=FALSE, bLowPwrDisable=FALSE; + BOOLEAN bAsus8703b=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + + if(!bWifiConnected) + { + bLowPwrDisable = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + halbtc8703b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non-connected idle!!\n")); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + halbtc8703b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + bCommon = TRUE; + } + else + { + if(BT_8703B_2ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus) + { + bLowPwrDisable = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + halbtc8703b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi connected + BT non connected-idle!!\n")); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + halbtc8703b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0xb); + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + bCommon = TRUE; + } + else if(BT_8703B_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) + { + bLowPwrDisable = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + + if(bBtHsOn) + return FALSE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi connected + BT connected-idle!!\n")); + halbtc8703b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + halbtc8703b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0xb); + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8703b2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + bCommon = TRUE; + } + else + { + bLowPwrDisable = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + + if(bWifiBusy) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi Connected-Busy + BT Busy!!\n")); +#if 0 + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_IS_ASUS_8703B, &bAsus8703b); + if(!bAsus8703b) + bCommon = FALSE; + else + bCommon = halbtc8703b2ant_ActionWifiIdleProcess(pBtCoexist); +#else + bCommon = FALSE; +#endif + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi Connected-Idle + BT Busy!!\n")); + //bCommon = FALSE; + bCommon = halbtc8703b2ant_ActionWifiIdleProcess(pBtCoexist); + } + } + } + + return bCommon; +} +VOID +halbtc8703b2ant_TdmaDurationAdjust( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bScoHid, + IN BOOLEAN bTxPause, + IN u1Byte maxInterval + ) +{ + static s4Byte up,dn,m,n,WaitCount; + s4Byte result; //0: no change, +1: increase WiFi duration, -1: decrease WiFi duration + u1Byte retryCount=0; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TdmaDurationAdjust()\n")); + + if(!pCoexDm->bAutoTdmaAdjust) + { + pCoexDm->bAutoTdmaAdjust = TRUE; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], first run TdmaDurationAdjust()!!\n")); + { + if(bScoHid) + { + if(bTxPause) + { + if(maxInterval == 1) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + pCoexDm->psTdmaDuAdjType = 13; + } + else if(maxInterval == 2) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(maxInterval == 3) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + } + else + { + if(maxInterval == 1) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(maxInterval == 2) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(maxInterval == 3) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + } + } + else + { + if(bTxPause) + { + if(maxInterval == 1) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + pCoexDm->psTdmaDuAdjType = 5; + } + else if(maxInterval == 2) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(maxInterval == 3) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + } + else + { + if(maxInterval == 1) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + else if(maxInterval == 2) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(maxInterval == 3) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + } + } + } + //============ + up = 0; + dn = 0; + m = 1; + n= 3; + result = 0; + WaitCount = 0; + } + else + { + //accquire the BT TRx retry count from BT_Info byte2 + retryCount = pCoexSta->btRetryCnt; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], retryCount = %d\n", retryCount)); + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], up=%d, dn=%d, m=%d, n=%d, WaitCount=%d\n", + up, dn, m, n, WaitCount)); + result = 0; + WaitCount++; + + if(retryCount == 0) // no retry in the last 2-second duration + { + up++; + dn--; + + if (dn <= 0) + dn = 0; + + if(up >= n) // if s n 2 retry count0, hռeWiFi duration + { + WaitCount = 0; + n = 3; + up = 0; + dn = 0; + result = 1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Increase wifi duration!!\n")); + } + } + else if (retryCount <= 3) // <=3 retry in the last 2-second duration + { + up--; + dn++; + + if (up <= 0) + up = 0; + + if (dn == 2) // if s 2 2 retry count< 3, hկWiFi duration + { + if (WaitCount <= 2) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter<3!!\n")); + } + } + else //retry count > 3, un1 retry count > 3, hկWiFi duration + { + if (WaitCount == 1) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter>3!!\n")); + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], max Interval = %d\n", maxInterval)); + if(maxInterval == 1) + { + if(bTxPause) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 1\n")); + + if(pCoexDm->curPsTdma == 71) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + pCoexDm->psTdmaDuAdjType = 5; + } + else if(pCoexDm->curPsTdma == 1) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + pCoexDm->psTdmaDuAdjType = 5; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 4) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + if(pCoexDm->curPsTdma == 9) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + pCoexDm->psTdmaDuAdjType = 13; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + + if(result == -1) + { + if(pCoexDm->curPsTdma == 5) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + else if(pCoexDm->curPsTdma == 13) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 8) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + pCoexDm->psTdmaDuAdjType = 5; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + pCoexDm->psTdmaDuAdjType = 13; + } + } + } + else + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 0\n")); + if(pCoexDm->curPsTdma == 5) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 71); + pCoexDm->psTdmaDuAdjType = 71; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 8) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + if(pCoexDm->curPsTdma == 13) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + + if(result == -1) + { + if(pCoexDm->curPsTdma == 71) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + else if(pCoexDm->curPsTdma == 1) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 4) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + else if(pCoexDm->curPsTdma == 1) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 71); + pCoexDm->psTdmaDuAdjType = 71; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + } + } + } + else if(maxInterval == 2) + { + if(bTxPause) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 1\n")); + if(pCoexDm->curPsTdma == 1) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 4) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + if(pCoexDm->curPsTdma == 9) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 5) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + else if(pCoexDm->curPsTdma == 13) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 8) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + } + } + else + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 0\n")); + if(pCoexDm->curPsTdma == 5) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 8) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + if(pCoexDm->curPsTdma == 13) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 1) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 4) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + } + } + } + else if(maxInterval == 3) + { + if(bTxPause) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 1\n")); + if(pCoexDm->curPsTdma == 1) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 4) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + if(pCoexDm->curPsTdma == 9) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 5) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + else if(pCoexDm->curPsTdma == 13) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 8) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + } + } + else + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 0\n")); + if(pCoexDm->curPsTdma == 5) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 8) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + if(pCoexDm->curPsTdma == 13) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 1) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 4) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + } + } + } + } + + // if current PsTdma not match with the recorded one (when scan, dhcp...), + // then we have to adjust it back to the previous record one. + if(pCoexDm->curPsTdma != pCoexDm->psTdmaDuAdjType) + { + BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PsTdma type dismatch!!!, curPsTdma=%d, recordPsTdma=%d\n", + pCoexDm->curPsTdma, pCoexDm->psTdmaDuAdjType)); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + + if( !bScan && !bLink && !bRoam) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, pCoexDm->psTdmaDuAdjType); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n")); + } + } +} + +// SCO only or SCO+PAN(HS) +VOID +halbtc8703b2ant_ActionSco( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8703b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + btRssiState = halbtc8703b2ant_BtRssiState(2, BT_8703B_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8703b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8703b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 4); + + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if (BTC_WIFI_BW_LEGACY == wifiBw) //for SCO quality at 11b/g mode + { + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + } + else //for SCO quality & wifi performance balance at 11n mode + { + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 8); + } + + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); //for voice quality + + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,TRUE,0x4); + } + else + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,TRUE,0x4); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,TRUE,0x4); + } + else + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,TRUE,0x4); + } + } +} + + +VOID +halbtc8703b2ant_ActionHid( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8703b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + btRssiState = halbtc8703b2ant_BtRssiState(2, BT_8703B_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8703b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8703b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if (BTC_WIFI_BW_LEGACY == wifiBw) //for HID at 11b/g mode + { + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + else //for HID quality & wifi performance balance at 11n mode + { + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 9); + } + + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + } + else + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + } + + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +//A2DP only / PAN(EDR) only/ A2DP+PAN(HS) +VOID +halbtc8703b2ant_ActionA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btRssiState; + u4Byte wifiBw; + u1Byte apNum=0; + + wifiRssiState = halbtc8703b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + wifiRssiState1 = halbtc8703b2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8703B_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8703b2ant_BtRssiState(2, BT_8703B_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_AP_NUM, &apNum); + + // define the office environment + if( (apNum >= 10) && BTC_RSSI_HIGH(wifiRssiState1) && BTC_RSSI_HIGH(btRssiState)) + { + //DbgPrint(" AP#>10(%d)\n", apNum); + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + halbtc8703b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + halbtc8703b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + + // sw mechanism + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,TRUE,0x18); + } + else + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,TRUE,0x18); + } + return; + + } + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + halbtc8703b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8703b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + + if (BTC_RSSI_HIGH(wifiRssiState1) && BTC_RSSI_HIGH(btRssiState)) + { + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } + else + { + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 13); + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + } + + + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8703b2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 1); + } + else + { + halbtc8703b2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 1); + } + + // sw mechanism + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +VOID +halbtc8703b2ant_ActionA2dpPanHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8703b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + wifiRssiState1 = halbtc8703b2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8703B_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8703b2ant_BtRssiState(2, BT_8703B_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8703b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8703b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifiRssiState1) && BTC_RSSI_HIGH(btRssiState)) + { + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } + else + { + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 13); + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + } + + halbtc8703b2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 2); + + // sw mechanism + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +VOID +halbtc8703b2ant_ActionPanEdr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState,wifiRssiState1, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8703b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + wifiRssiState1 = halbtc8703b2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8703B_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8703b2ant_BtRssiState(2, BT_8703B_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8703b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8703b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifiRssiState1) && BTC_RSSI_HIGH(btRssiState)) + { + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 10); + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } + else + { + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 13); + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + } + + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + } + else + { + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + } + + // sw mechanism + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + + +//PAN(HS) only +VOID +halbtc8703b2ant_ActionPanHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8703b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + wifiRssiState1 = halbtc8703b2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8703B_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8703b2ant_BtRssiState(2, BT_8703B_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8703b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8703b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +//PAN(EDR)+A2DP +VOID +halbtc8703b2ant_ActionPanEdrA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8703b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + wifiRssiState1 = halbtc8703b2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8703B_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8703b2ant_BtRssiState(2, BT_8703B_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8703b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8703b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifiRssiState1) && BTC_RSSI_HIGH(btRssiState)) + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 12); + + if(BTC_WIFI_BW_HT40 == wifiBw) + halbtc8703b2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 3); + else + halbtc8703b2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 3); + } + else + { + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 13); + halbtc8703b2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 3); + } + + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +VOID +halbtc8703b2ant_ActionPanEdrHid( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8703b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + wifiRssiState1 = halbtc8703b2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8703B_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8703b2ant_BtRssiState(2, BT_8703B_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + halbtc8703b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifiRssiState1) && BTC_RSSI_HIGH(btRssiState)) + { + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } + else + { + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 14); + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + } + + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + if(BTC_WIFI_BW_HT40 == wifiBw) + { + halbtc8703b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 3); + //halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 11); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x780); + } + else + { + halbtc8703b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + //halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + } + halbtc8703b2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 2); + } + else + { + halbtc8703b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + //halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 14); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + halbtc8703b2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 2); + } + + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +// HID+A2DP+PAN(EDR) +VOID +halbtc8703b2ant_ActionHidA2dpPanEdr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState,wifiRssiState1, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8703b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + wifiRssiState1 = halbtc8703b2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8703B_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8703b2ant_BtRssiState(2, BT_8703B_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8703b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8703b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifiRssiState1) && BTC_RSSI_HIGH(btRssiState)) + { + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } + else + { + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 14); + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + if(BTC_WIFI_BW_HT40 == wifiBw) + halbtc8703b2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 3); + else + halbtc8703b2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 3); + } + else + { + halbtc8703b2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 3); + } + + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +VOID +halbtc8703b2ant_ActionHidA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btRssiState; + u4Byte wifiBw; + u1Byte apNum=0; + + wifiRssiState = halbtc8703b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + //btRssiState = halbtc8703b2ant_BtRssiState(2, 29, 0); + wifiRssiState1 = halbtc8703b2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8703B_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8703b2ant_BtRssiState(3, BT_8703B_2ANT_BT_RSSI_COEXSWITCH_THRES, 37); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8703b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, TRUE, 0x5); + + halbtc8703b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_LEGACY == wifiBw) + { + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else if(BTC_RSSI_MEDIUM(btRssiState)) + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + } + else + { // only 802.11N mode we have to dec bt power to 4 degree + if(BTC_RSSI_HIGH(btRssiState)) + { + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_AP_NUM, &apNum); + // need to check ap Number of Not + if(apNum < 10) + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 4); + else + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + } + else if(BTC_RSSI_MEDIUM(btRssiState)) + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + } + + if (BTC_RSSI_HIGH(wifiRssiState1) && BTC_RSSI_HIGH(btRssiState)) + { + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } + else + { + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 14); + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + } + + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8703b2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 3); + } + else + { + halbtc8703b2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 3); + } + + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +VOID +halbtc8703b2ant_ActionBtWhckTest( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + // sw all off + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); +} + +VOID +halbtc8703b2ant_ActionWifiMultiPort( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8703b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8703b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + // sw all off + halbtc8703b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8703b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + // hw all off + //pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + halbtc8703b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8703b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8703b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); +} + +VOID +halbtc8703b2ant_RunCoexistMechanism( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bWifiUnder5G=FALSE, bBtHsOn=FALSE; + u1Byte btInfoOriginal=0, btRetryCnt=0; + u1Byte algorithm=0; + u4Byte numOfWifiLink=0; + u4Byte wifiLinkStatus=0; + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bMiracastPlusBt=FALSE; + BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism()===>\n")); + + if(pBtCoexist->bManualControl) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n")); + return; + } + + if(pCoexSta->bUnderIps) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi is under IPS !!!\n")); + return; + } + + if(pCoexSta->bBtWhckTest) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is under WHCK TEST!!!\n")); + halbtc8703b2ant_ActionBtWhckTest(pBtCoexist); + return; + } + + algorithm = halbtc8703b2ant_ActionAlgorithm(pBtCoexist); + if(pCoexSta->bC2hBtInquiryPage && (BT_8703B_2ANT_COEX_ALGO_PANHS!=algorithm)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is under inquiry/page scan !!\n")); + halbtc8703b2ant_ActionBtInquiry(pBtCoexist); + return; + } + else + { + /* + if(pCoexDm->bNeedRecover0x948) + { + pCoexDm->bNeedRecover0x948 = FALSE; + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, pCoexDm->backup0x948); + } + */ + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + + if(bScan || bLink || bRoam) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], WiFi is under Link Process !!\n")); + halbtc8703b2ant_ActionWiFiLinkProcess(pBtCoexist); + return; + } + + //for P2P + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_LINK_STATUS, &wifiLinkStatus); + numOfWifiLink = wifiLinkStatus>>16; + + if((numOfWifiLink>=2) || (wifiLinkStatus&WIFI_P2P_GO_CONNECTED)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], Multi-Port numOfWifiLink = %d, wifiLinkStatus = 0x%x\n", numOfWifiLink,wifiLinkStatus) ); + + if(pBtLinkInfo->bBtLinkExist) + { + bMiracastPlusBt = TRUE; + } + else + { + bMiracastPlusBt = FALSE; + } + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_MIRACAST_PLUS_BT, &bMiracastPlusBt); + halbtc8703b2ant_ActionWifiMultiPort(pBtCoexist); + + return; + } + else + { + bMiracastPlusBt = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_MIRACAST_PLUS_BT, &bMiracastPlusBt); + } + + pCoexDm->curAlgorithm = algorithm; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Algorithm = %d \n", pCoexDm->curAlgorithm)); + + if(halbtc8703b2ant_IsCommonAction(pBtCoexist)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant common.\n")); + pCoexDm->bAutoTdmaAdjust = FALSE; + } + else + { + if(pCoexDm->curAlgorithm != pCoexDm->preAlgorithm) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], preAlgorithm=%d, curAlgorithm=%d\n", + pCoexDm->preAlgorithm, pCoexDm->curAlgorithm)); + pCoexDm->bAutoTdmaAdjust = FALSE; + } + switch(pCoexDm->curAlgorithm) + { + case BT_8703B_2ANT_COEX_ALGO_SCO: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = SCO.\n")); + halbtc8703b2ant_ActionSco(pBtCoexist); + break; + case BT_8703B_2ANT_COEX_ALGO_HID: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID.\n")); + halbtc8703b2ant_ActionHid(pBtCoexist); + break; + case BT_8703B_2ANT_COEX_ALGO_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = A2DP.\n")); + halbtc8703b2ant_ActionA2dp(pBtCoexist); + break; + case BT_8703B_2ANT_COEX_ALGO_A2DP_PANHS: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n")); + halbtc8703b2ant_ActionA2dpPanHs(pBtCoexist); + break; + case BT_8703B_2ANT_COEX_ALGO_PANEDR: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n")); + halbtc8703b2ant_ActionPanEdr(pBtCoexist); + break; + case BT_8703B_2ANT_COEX_ALGO_PANHS: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HS mode.\n")); + halbtc8703b2ant_ActionPanHs(pBtCoexist); + break; + case BT_8703B_2ANT_COEX_ALGO_PANEDR_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n")); + halbtc8703b2ant_ActionPanEdrA2dp(pBtCoexist); + break; + case BT_8703B_2ANT_COEX_ALGO_PANEDR_HID: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n")); + halbtc8703b2ant_ActionPanEdrHid(pBtCoexist); + break; + case BT_8703B_2ANT_COEX_ALGO_HID_A2DP_PANEDR: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n")); + halbtc8703b2ant_ActionHidA2dpPanEdr(pBtCoexist); + break; + case BT_8703B_2ANT_COEX_ALGO_HID_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n")); + halbtc8703b2ant_ActionHidA2dp(pBtCoexist); + break; + default: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n")); + halbtc8703b2ant_CoexAllOff(pBtCoexist); + break; + } + pCoexDm->preAlgorithm = pCoexDm->curAlgorithm; + } +} + +VOID +halbtc8703b2ant_WifiOffHwCfg( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bIsInMpMode = FALSE; + u1Byte H2C_Parameter[2] ={0}; + u4Byte fwVer=0; + + // set wlan_act to low + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0x4); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x780); //WiFi goto standby while GNT_BT 0-->1 + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); + if(fwVer >= 0x180000) + { + /* Use H2C to set GNT_BT to HIGH */ + H2C_Parameter[0] = 1; + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x6E, 1, H2C_Parameter); + } + else + { + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x765, 0x18); + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_IS_IN_MP_MODE, &bIsInMpMode); + if(!bIsInMpMode) + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x67, 0x20, 0x0); //BT select s0/s1 is controlled by BT + else + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x67, 0x20, 0x1); //BT select s0/s1 is controlled by WiFi +} + +VOID +halbtc8703b2ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bBackUp + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + u4Byte u4Tmp=0, fwVer; + u2Byte u2Tmp=0; + u1Byte u1Tmp=0; + u1Byte H2C_Parameter[2] ={0}; + + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 2Ant Init HW Config!!\n")); + + // backup rf 0x1e value + pCoexDm->btRf0x1eBackup = + pBtCoexist->fBtcGetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff); + + // 0x790[5:0]=0x5 + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x790); + u1Tmp &= 0xc0; + u1Tmp |= 0x5; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x790, u1Tmp); + + //Antenna config + halbtc8703b2ant_SetAntPath(pBtCoexist, BTC_ANT_WIFI_AT_MAIN, TRUE, FALSE); + pCoexSta->disVerInfoCnt = 0; + + // PTA parameter + halbtc8703b2ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 0); + + // Enable counter statistics + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0x4); //0x76e[3] =1, WLAN_Act control by PTA + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x778, 0x3); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x40, 0x20, 0x1); +} + +//============================================================ +// work around function start with wa_halbtc8703b2ant_ +//============================================================ +//============================================================ +// extern function start with EXhalbtc8703b2ant_ +//============================================================ +VOID +EXhalbtc8703b2ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + u2Byte u2Tmp=0x0; + + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x67, 0x20); + + // enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. + u2Tmp = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0x2); + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x2, u2Tmp|BIT0|BIT1); + + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x0); + + if(pBtCoexist->chipInterface == BTC_INTF_USB) + { + // fixed at S0 for USB interface + pBoardInfo->btdmAntPos = BTC_ANTENNA_AT_AUX_PORT; + } + else + { + // for PCIE and SDIO interface, we check efuse 0xc3[6] + if(pBoardInfo->singleAntPath == 0) + { + // set to S1 + pBoardInfo->btdmAntPos = BTC_ANTENNA_AT_MAIN_PORT; + } + else if(pBoardInfo->singleAntPath == 1) + { + // set to S0 + pBoardInfo->btdmAntPos = BTC_ANTENNA_AT_AUX_PORT; + } + } +} + +VOID +EXhalbtc8703b2ant_PreLoadFirmware( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + u1Byte u1Tmp=0x4; /* Set BIT2 by default since it's 2ant case */ + + // + // S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) + // Local setting bit define + // BIT0: "0" for no antenna inverse; "1" for antenna inverse + // BIT1: "0" for internal switch; "1" for external switch + // BIT2: "0" for one antenna; "1" for two antenna + // NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 + if(pBtCoexist->chipInterface == BTC_INTF_USB) + { + // fixed at S0 for USB interface + u1Tmp |= 0x1; // antenna inverse + pBtCoexist->fBtcWriteLocalReg1Byte(pBtCoexist, 0xfe08, u1Tmp); + } + else + { + // for PCIE and SDIO interface, we check efuse 0xc3[6] + if(pBoardInfo->singleAntPath == 0) + { + } + else if(pBoardInfo->singleAntPath == 1) + { + // set to S0 + u1Tmp |= 0x1; // antenna inverse + } + + if(pBtCoexist->chipInterface == BTC_INTF_PCI) + { + pBtCoexist->fBtcWriteLocalReg1Byte(pBtCoexist, 0x384, u1Tmp); + } + else if(pBtCoexist->chipInterface == BTC_INTF_SDIO) + { + pBtCoexist->fBtcWriteLocalReg1Byte(pBtCoexist, 0x60, u1Tmp); + } + } +} + +VOID +EXhalbtc8703b2ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ) +{ + halbtc8703b2ant_InitHwConfig(pBtCoexist, TRUE); +} + +VOID +EXhalbtc8703b2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Coex Mechanism Init!!\n")); + + halbtc8703b2ant_InitCoexDm(pBtCoexist); +} + +VOID +EXhalbtc8703b2ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + pu1Byte cliBuf=pBtCoexist->cliBuf; + u1Byte u1Tmp[4], i, btInfoExt, psTdmaCase=0; + u4Byte u4Tmp[4]; + u4Byte faOfdm, faCck; + u4Byte fwVer=0, btPatchVer=0; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cliBuf); + + if(pBtCoexist->bManualControl) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[Under Manual Control]============"); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n =========================================="); + CL_PRINTF(cliBuf); + } + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:", \ + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \ + ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion); + CL_PRINTF(cliBuf); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_BT_PATCH_VER, &btPatchVer); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)", "CoexVer/ FwVer/ PatchVer", \ + GLCoexVerDate8703b2Ant, GLCoexVer8703b2Ant, fwVer, btPatchVer, btPatchVer); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", "Wifi channel informed to BT", \ + pCoexDm->wifiChnlInfo[0], pCoexDm->wifiChnlInfo[1], + pCoexDm->wifiChnlInfo[2]); + CL_PRINTF(cliBuf); + + // wifi status + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Wifi Status]============"); + CL_PRINTF(cliBuf); + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[BT Status]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %ddBm/ %d] ", "BT [status/ rssi/ retryCnt]", \ + ((pBtCoexist->btInfo.bBtDisabled)? ("disabled"): ((pCoexSta->bC2hBtInquiryPage)?("inquiry/page scan"):((BT_8703B_2ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus)? "non-connected idle": + ( (BT_8703B_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus)? "connected-idle":"busy")))), + pCoexSta->btRssi-100, pCoexSta->btRetryCnt); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP", \ + pBtLinkInfo->bScoExist, pBtLinkInfo->bHidExist, pBtLinkInfo->bPanExist, pBtLinkInfo->bA2dpExist); + CL_PRINTF(cliBuf); + + if (pStackInfo->bProfileNotified) + { + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO); + } + else + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Role", \ + (pBtLinkInfo->bSlaveRole )? "Slave":"Master"); + CL_PRINTF(cliBuf); + } + + btInfoExt = pCoexSta->btInfoExt; + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Info A2DP rate", \ + (btInfoExt&BIT0)? "Basic rate":"EDR rate"); + CL_PRINTF(cliBuf); + + for(i=0; ibtInfoC2hCnt[i]) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", GLBtInfoSrc8703b2Ant[i], \ + pCoexSta->btInfoC2h[i][0], pCoexSta->btInfoC2h[i][1], + pCoexSta->btInfoC2h[i][2], pCoexSta->btInfoC2h[i][3], + pCoexSta->btInfoC2h[i][4], pCoexSta->btInfoC2h[i][5], + pCoexSta->btInfoC2h[i][6], pCoexSta->btInfoC2hCnt[i]); + CL_PRINTF(cliBuf); + } + } + + // Sw mechanism + if(pBtCoexist->bManualControl) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism] (before Manual)============"); + } + else + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============"); + } + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", "SM1[ShRf/ LpRA/ LimDig]", \ + pCoexDm->bCurRfRxLpfShrink, pCoexDm->bCurLowPenaltyRa, pCoexDm->bLimitedDig); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", \ + pCoexDm->bCurAgcTableEn, pCoexDm->bCurAdcBackOff, pCoexDm->bCurDacSwingOn, pCoexDm->curDacSwingLvl); + CL_PRINTF(cliBuf); + + // Fw mechanism + if(pBtCoexist->bManualControl) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism] (before Manual) ============"); + } + else + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============"); + } + + psTdmaCase = pCoexDm->curPsTdma; + + if (pCoexDm->bIsSwitchTo1dot5Ant) + psTdmaCase = psTdmaCase + 100; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)", "PS TDMA", \ + pCoexDm->psTdmaPara[0], pCoexDm->psTdmaPara[1], + pCoexDm->psTdmaPara[2], pCoexDm->psTdmaPara[3], + pCoexDm->psTdmaPara[4], psTdmaCase, + (pCoexDm->bCurPsTdmaOn? "On":"Off"), + (pCoexDm->bAutoTdmaAdjust? "Adj":"Fix") ); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "Coex Table Type", \ + pCoexSta->nCoexTableType); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "DecBtPwr/ IgnWlanAct", \ + pCoexDm->curBtDecPwrLvl, pCoexDm->bCurIgnoreWlanAct); + CL_PRINTF(cliBuf); + + // Hw setting + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "RF-A, 0x1e initVal", \ + pCoexDm->btRf0x1eBackup); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x778); + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x880); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x778/0x880[29:25]", \ + u1Tmp[0], (u4Tmp[0]&0x3e000000) >> 25); + CL_PRINTF(cliBuf); + + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x948); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x67); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x765); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x948/ 0x67[5] / 0x765", \ + u4Tmp[0], ((u1Tmp[0]&0x20)>> 5), u1Tmp[1]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x92c); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x930); + u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x944); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x92c[1:0]/ 0x930[7:0]/0x944[1:0]", \ + u4Tmp[0]&0x3, u4Tmp[1]&0xff, u4Tmp[2]&0x3); + CL_PRINTF(cliBuf); + + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x39); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x40); + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x4c); + u1Tmp[2] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x64); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0x38[11]/0x40/0x4c[24:23]/0x64[0]", \ + ((u1Tmp[0] & 0x8)>>3), u1Tmp[1], ((u4Tmp[0]&0x01800000)>>23), u1Tmp[2]&0x1); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x550); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x522); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x550(bcn ctrl)/0x522", \ + u4Tmp[0], u1Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc50); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x49c); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0xc50(dig)/0x49c(null-drop)", \ + u4Tmp[0]&0xff, u1Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda0); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda4); + u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda8); + u4Tmp[3] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xcf0); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xa5b); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xa5c); + + faOfdm = ((u4Tmp[0]&0xffff0000) >> 16) + ((u4Tmp[1]&0xffff0000) >> 16) + (u4Tmp[1] & 0xffff) + (u4Tmp[2] & 0xffff) + \ + ((u4Tmp[3]&0xffff0000) >> 16) + (u4Tmp[3] & 0xffff) ; + faCck = (u1Tmp[0] << 8) + u1Tmp[1]; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "OFDM-CCA/OFDM-FA/CCK-FA", \ + u4Tmp[0]&0xffff, faOfdm, faCck); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", "CRC_OK CCK/11g/11n/11n-Agg", \ + pCoexSta->nCRCOK_CCK, pCoexSta->nCRCOK_11g, pCoexSta->nCRCOK_11n, pCoexSta->nCRCOK_11nAgg); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", "CRC_Err CCK/11g/11n/11n-Agg", \ + pCoexSta->nCRCErr_CCK, pCoexSta->nCRCErr_11g, pCoexSta->nCRCErr_11n, pCoexSta->nCRCErr_11nAgg); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c0); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c4); + u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c8); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x6cc); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", \ + u4Tmp[0], u4Tmp[1], u4Tmp[2], u1Tmp[0]); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x770(high-pri rx/tx)", \ + pCoexSta->highPriorityRx, pCoexSta->highPriorityTx); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x774(low-pri rx/tx)", \ + pCoexSta->lowPriorityRx, pCoexSta->lowPriorityTx); + CL_PRINTF(cliBuf); +#if(BT_AUTO_REPORT_ONLY_8703B_2ANT == 1) + //halbtc8703b2ant_MonitorBtCtr(pBtCoexist); +#endif + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + + +VOID +EXhalbtc8703b2ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_IPS_ENTER == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS ENTER notify\n")); + pCoexSta->bUnderIps = TRUE; + halbtc8703b2ant_WifiOffHwCfg(pBtCoexist); + halbtc8703b2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE); + halbtc8703b2ant_CoexAllOff(pBtCoexist); + } + else if(BTC_IPS_LEAVE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS LEAVE notify\n")); + pCoexSta->bUnderIps = FALSE; + halbtc8703b2ant_InitHwConfig(pBtCoexist, FALSE); + halbtc8703b2ant_InitCoexDm(pBtCoexist); + halbtc8703b2ant_QueryBtInfo(pBtCoexist); + } +} + +VOID +EXhalbtc8703b2ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_LPS_ENABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS ENABLE notify\n")); + pCoexSta->bUnderLps = TRUE; + } + else if(BTC_LPS_DISABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS DISABLE notify\n")); + pCoexSta->bUnderLps = FALSE; + } +} + +VOID +EXhalbtc8703b2ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + u4Byte u4Tmp; + u1Byte u1Tmpa, u1Tmpb; + + + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x948); + u1Tmpa = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x765); + u1Tmpb = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x76e); + + if(BTC_SCAN_START == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n")); + } + else if(BTC_SCAN_FINISH == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n")); + } + + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x76e=0x%x\n", + u4Tmp, u1Tmpa, u1Tmpb)); +} + +VOID +EXhalbtc8703b2ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_ASSOCIATE_START == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n")); + } + else if(BTC_ASSOCIATE_FINISH == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n")); + } +} + +VOID +EXhalbtc8703b2ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + u1Byte H2C_Parameter[3] ={0}; + u4Byte wifiBw; + u1Byte wifiCentralChnl; + u1Byte apNum=0; + + if(BTC_MEDIA_CONNECT == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA connect notify\n")); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA disconnect notify\n")); + } + + // only 2.4G we need to inform bt the chnl mask + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, &wifiCentralChnl); + if( (BTC_MEDIA_CONNECT == type) && + (wifiCentralChnl <= 14) ) + { + H2C_Parameter[0] = 0x1; + H2C_Parameter[1] = wifiCentralChnl; + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + H2C_Parameter[2] = 0x30; + else + { + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_AP_NUM, &apNum); + if(apNum < 10) + H2C_Parameter[2] = 0x30; + else + H2C_Parameter[2] = 0x20; + } + } + + pCoexDm->wifiChnlInfo[0] = H2C_Parameter[0]; + pCoexDm->wifiChnlInfo[1] = H2C_Parameter[1]; + pCoexDm->wifiChnlInfo[2] = H2C_Parameter[2]; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x66=0x%x\n", + H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x66, 3, H2C_Parameter); +} + +VOID +EXhalbtc8703b2ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(type == BTC_PACKET_DHCP) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], DHCP Packet notify\n")); + } +} + +VOID +EXhalbtc8703b2ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + u1Byte btInfo=0; + u1Byte i, rspSource=0; + BOOLEAN bBtBusy=FALSE, bLimitedDig=FALSE; + BOOLEAN bWifiConnected=FALSE; + static BOOLEAN bPreScoExist=FALSE; + u4Byte raMask=0x0; + + pCoexSta->bC2hBtInfoReqSent = FALSE; + + rspSource = tmpBuf[0]&0xf; + if(rspSource >= BT_INFO_SRC_8703B_2ANT_MAX) + rspSource = BT_INFO_SRC_8703B_2ANT_WIFI_FW; + pCoexSta->btInfoC2hCnt[rspSource]++; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Bt info[%d], length=%d, hex data=[", rspSource, length)); + for(i=0; ibtInfoC2h[rspSource][i] = tmpBuf[i]; + if(i == 1) + btInfo = tmpBuf[i]; + if(i == length-1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x]\n", tmpBuf[i])); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x, ", tmpBuf[i])); + } + } + + if(pBtCoexist->bManualControl) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), return for Manual CTRL<===\n")); + return; + } + + // if 0xff, it means BT is under WHCK test + if (btInfo == 0xff) + pCoexSta->bBtWhckTest = TRUE; + else + pCoexSta->bBtWhckTest = FALSE; + + if(BT_INFO_SRC_8703B_2ANT_WIFI_FW != rspSource) + { + pCoexSta->btRetryCnt = // [3:0] + pCoexSta->btInfoC2h[rspSource][2]&0xf; + + pCoexSta->btRssi = + pCoexSta->btInfoC2h[rspSource][3]*2+10; + + pCoexSta->btInfoExt = + pCoexSta->btInfoC2h[rspSource][4]; + + pCoexSta->bBtTxRxMask = (pCoexSta->btInfoC2h[rspSource][2]&0x40); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TX_RX_MASK, &pCoexSta->bBtTxRxMask); + if (pCoexSta->bBtTxRxMask) + { + /* BT into is responded by BT FW and BT RF REG 0x3C != 0x01 => Need to switch BT TRx Mask */ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x01\n")); + pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x3c, 0x01); + } + + // Here we need to resend some wifi info to BT + // because bt is reset and loss of the info. + if( (pCoexSta->btInfoExt & BIT1) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n")); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + if(bWifiConnected) + { + EXhalbtc8703b2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_CONNECT); + } + else + { + EXhalbtc8703b2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); + } + } + + if( (pCoexSta->btInfoExt & BIT3) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n")); + halbtc8703b2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE); + } + else + { + // BT already NOT ignore Wlan active, do nothing here. + } +#if(BT_AUTO_REPORT_ONLY_8703B_2ANT == 0) + if( (pCoexSta->btInfoExt & BIT4) ) + { + // BT auto report already enabled, do nothing + } + else + { + halbtc8703b2ant_BtAutoReport(pBtCoexist, FORCE_EXEC, TRUE); + } +#endif + } + + // check BIT2 first ==> check if bt is under inquiry or page scan + if(btInfo & BT_INFO_8703B_2ANT_B_INQ_PAGE) + pCoexSta->bC2hBtInquiryPage = TRUE; + else + pCoexSta->bC2hBtInquiryPage = FALSE; + + // set link exist status + if(!(btInfo&BT_INFO_8703B_2ANT_B_CONNECTION)) + { + pCoexSta->bBtLinkExist = FALSE; + pCoexSta->bPanExist = FALSE; + pCoexSta->bA2dpExist = FALSE; + pCoexSta->bHidExist = FALSE; + pCoexSta->bScoExist = FALSE; + } + else // connection exists + { + pCoexSta->bBtLinkExist = TRUE; + if(btInfo & BT_INFO_8703B_2ANT_B_FTP) + pCoexSta->bPanExist = TRUE; + else + pCoexSta->bPanExist = FALSE; + if(btInfo & BT_INFO_8703B_2ANT_B_A2DP) + pCoexSta->bA2dpExist = TRUE; + else + pCoexSta->bA2dpExist = FALSE; + if(btInfo & BT_INFO_8703B_2ANT_B_HID) + pCoexSta->bHidExist = TRUE; + else + pCoexSta->bHidExist = FALSE; + if(btInfo & BT_INFO_8703B_2ANT_B_SCO_ESCO) + pCoexSta->bScoExist = TRUE; + else + pCoexSta->bScoExist = FALSE; + + if ( (pCoexSta->bHidExist == FALSE) && (pCoexSta->bC2hBtInquiryPage == FALSE) && (pCoexSta->bScoExist == FALSE)) + { + if (pCoexSta->highPriorityTx + pCoexSta->highPriorityRx >= 160) + { + pCoexSta->bHidExist = TRUE; + btInfo = btInfo | 0x20; + } + } + } + + halbtc8703b2ant_UpdateBtLinkInfo(pBtCoexist); + + if(!(btInfo&BT_INFO_8703B_2ANT_B_CONNECTION)) + { + pCoexDm->btStatus = BT_8703B_2ANT_BT_STATUS_NON_CONNECTED_IDLE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n")); + } + else if(btInfo == BT_INFO_8703B_2ANT_B_CONNECTION) // connection exists but no busy + { + pCoexDm->btStatus = BT_8703B_2ANT_BT_STATUS_CONNECTED_IDLE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n")); + } + else if((btInfo&BT_INFO_8703B_2ANT_B_SCO_ESCO) || + (btInfo&BT_INFO_8703B_2ANT_B_SCO_BUSY)) + { + pCoexDm->btStatus = BT_8703B_2ANT_BT_STATUS_SCO_BUSY; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT SCO busy!!!\n")); + } + else if(btInfo&BT_INFO_8703B_2ANT_B_ACL_BUSY) + { + pCoexDm->btStatus = BT_8703B_2ANT_BT_STATUS_ACL_BUSY; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT ACL busy!!!\n")); + } + else + { + pCoexDm->btStatus = BT_8703B_2ANT_BT_STATUS_MAX; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n")); + } + + if( (BT_8703B_2ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) || + (BT_8703B_2ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8703B_2ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + bBtBusy = TRUE; + bLimitedDig = TRUE; + } + else + { + bBtBusy = FALSE; + bLimitedDig = FALSE; + } + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bBtBusy); + + pCoexDm->bLimitedDig = bLimitedDig; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_LIMITED_DIG, &bLimitedDig); + + halbtc8703b2ant_RunCoexistMechanism(pBtCoexist); +} + +VOID +EXhalbtc8703b2ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Halt notify\n")); + + halbtc8703b2ant_WifiOffHwCfg(pBtCoexist); + //remove due to interrupt is disabled that polling c2h will fail and delay 100ms. + //pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x3c, 0x15); //BT goto standby while GNT_BT 1-->0 + halbtc8703b2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE); + + EXhalbtc8703b2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); +} + +VOID +EXhalbtc8703b2ant_PnpNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte pnpState + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Pnp notify\n")); + + if(BTC_WIFI_PNP_SLEEP == pnpState) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Pnp notify to SLEEP\n")); + } + else if(BTC_WIFI_PNP_WAKE_UP == pnpState) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Pnp notify to WAKE UP\n")); + halbtc8703b2ant_InitHwConfig(pBtCoexist, FALSE); + halbtc8703b2ant_InitCoexDm(pBtCoexist); + halbtc8703b2ant_QueryBtInfo(pBtCoexist); + } +} + +VOID +EXhalbtc8703b2ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ) +{ + //static u1Byte disVerInfoCnt=0; + u4Byte fwVer=0, btPatchVer=0; + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ==========================Periodical===========================\n")); + + if(pCoexSta->disVerInfoCnt <= 5) + { + pCoexSta->disVerInfoCnt += 1; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ****************************************************************\n")); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Ant PG Num/ Ant Mech/ Ant Pos = %d/ %d/ %d\n", + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum, pBoardInfo->btdmAntPos)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT stack/ hci ext ver = %s / %d\n", + ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion)); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_BT_PATCH_VER, &btPatchVer); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CoexVer/ FwVer/ PatchVer = %d_%x/ 0x%x/ 0x%x(%d)\n", + GLCoexVerDate8703b2Ant, GLCoexVer8703b2Ant, fwVer, btPatchVer, btPatchVer)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ****************************************************************\n")); + + if (pCoexSta->disVerInfoCnt == 3) + { + //Antenna config to set 0x765 = 0x0 (GNT_BT control by PTA) after initial + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Set GNT_BT control by PTA\n")); + halbtc8703b2ant_SetAntPath(pBtCoexist, BTC_ANT_WIFI_AT_MAIN, FALSE, FALSE); + } + } + +#if(BT_AUTO_REPORT_ONLY_8703B_2ANT == 0) + halbtc8703b2ant_QueryBtInfo(pBtCoexist); + halbtc8703b2ant_MonitorBtEnableDisable(pBtCoexist); +#else + halbtc8703b2ant_MonitorBtCtr(pBtCoexist); + halbtc8703b2ant_MonitorWiFiCtr(pBtCoexist); + + if( halbtc8703b2ant_IsWifiStatusChanged(pBtCoexist) || + pCoexDm->bAutoTdmaAdjust) + { + halbtc8703b2ant_RunCoexistMechanism(pBtCoexist); + } +#endif +} + + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8703b2Ant.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8703b2Ant.h new file mode 100644 index 000000000..7cd275ab2 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8703b2Ant.h @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//=========================================== +// The following is for 8703B 2Ant BT Co-exist definition +//=========================================== +#define BT_AUTO_REPORT_ONLY_8703B_2ANT 1 + + +#define BT_INFO_8703B_2ANT_B_FTP BIT7 +#define BT_INFO_8703B_2ANT_B_A2DP BIT6 +#define BT_INFO_8703B_2ANT_B_HID BIT5 +#define BT_INFO_8703B_2ANT_B_SCO_BUSY BIT4 +#define BT_INFO_8703B_2ANT_B_ACL_BUSY BIT3 +#define BT_INFO_8703B_2ANT_B_INQ_PAGE BIT2 +#define BT_INFO_8703B_2ANT_B_SCO_ESCO BIT1 +#define BT_INFO_8703B_2ANT_B_CONNECTION BIT0 + +#define BTC_RSSI_COEX_THRESH_TOL_8703B_2ANT 2 + + +#define BT_8703B_2ANT_WIFI_RSSI_COEXSWITCH_THRES 42 //WiFi RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation +#define BT_8703B_2ANT_BT_RSSI_COEXSWITCH_THRES 46 //BT RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation + +typedef enum _BT_INFO_SRC_8703B_2ANT{ + BT_INFO_SRC_8703B_2ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8703B_2ANT_BT_RSP = 0x1, + BT_INFO_SRC_8703B_2ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8703B_2ANT_MAX +}BT_INFO_SRC_8703B_2ANT,*PBT_INFO_SRC_8703B_2ANT; + +typedef enum _BT_8703B_2ANT_BT_STATUS{ + BT_8703B_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8703B_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8703B_2ANT_BT_STATUS_INQ_PAGE = 0x2, + BT_8703B_2ANT_BT_STATUS_ACL_BUSY = 0x3, + BT_8703B_2ANT_BT_STATUS_SCO_BUSY = 0x4, + BT_8703B_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, + BT_8703B_2ANT_BT_STATUS_MAX +}BT_8703B_2ANT_BT_STATUS,*PBT_8703B_2ANT_BT_STATUS; + +typedef enum _BT_8703B_2ANT_COEX_ALGO{ + BT_8703B_2ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8703B_2ANT_COEX_ALGO_SCO = 0x1, + BT_8703B_2ANT_COEX_ALGO_HID = 0x2, + BT_8703B_2ANT_COEX_ALGO_A2DP = 0x3, + BT_8703B_2ANT_COEX_ALGO_A2DP_PANHS = 0x4, + BT_8703B_2ANT_COEX_ALGO_PANEDR = 0x5, + BT_8703B_2ANT_COEX_ALGO_PANHS = 0x6, + BT_8703B_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7, + BT_8703B_2ANT_COEX_ALGO_PANEDR_HID = 0x8, + BT_8703B_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, + BT_8703B_2ANT_COEX_ALGO_HID_A2DP = 0xa, + BT_8703B_2ANT_COEX_ALGO_MAX = 0xb, +}BT_8703B_2ANT_COEX_ALGO,*PBT_8703B_2ANT_COEX_ALGO; + +typedef struct _COEX_DM_8703B_2ANT{ + // fw mechanism + u1Byte preBtDecPwrLvl; + u1Byte curBtDecPwrLvl; + u1Byte preFwDacSwingLvl; + u1Byte curFwDacSwingLvl; + BOOLEAN bCurIgnoreWlanAct; + BOOLEAN bPreIgnoreWlanAct; + u1Byte prePsTdma; + u1Byte curPsTdma; + u1Byte psTdmaPara[5]; + u1Byte psTdmaDuAdjType; + BOOLEAN bResetTdmaAdjust; + BOOLEAN bAutoTdmaAdjust; + BOOLEAN bPrePsTdmaOn; + BOOLEAN bCurPsTdmaOn; + BOOLEAN bPreBtAutoReport; + BOOLEAN bCurBtAutoReport; + + // sw mechanism + BOOLEAN bPreRfRxLpfShrink; + BOOLEAN bCurRfRxLpfShrink; + u4Byte btRf0x1eBackup; + BOOLEAN bPreLowPenaltyRa; + BOOLEAN bCurLowPenaltyRa; + BOOLEAN bPreDacSwingOn; + u4Byte preDacSwingLvl; + BOOLEAN bCurDacSwingOn; + u4Byte curDacSwingLvl; + BOOLEAN bPreAdcBackOff; + BOOLEAN bCurAdcBackOff; + BOOLEAN bPreAgcTableEn; + BOOLEAN bCurAgcTableEn; + u4Byte preVal0x6c0; + u4Byte curVal0x6c0; + u4Byte preVal0x6c4; + u4Byte curVal0x6c4; + u4Byte preVal0x6c8; + u4Byte curVal0x6c8; + u1Byte preVal0x6cc; + u1Byte curVal0x6cc; + BOOLEAN bLimitedDig; + + // algorithm related + u1Byte preAlgorithm; + u1Byte curAlgorithm; + u1Byte btStatus; + u1Byte wifiChnlInfo[3]; + + BOOLEAN bNeedRecover0x948; + u4Byte backup0x948; + + u1Byte preLps; + u1Byte curLps; + u1Byte preRpwm; + u1Byte curRpwm; + + BOOLEAN bIsSwitchTo1dot5Ant; +} COEX_DM_8703B_2ANT, *PCOEX_DM_8703B_2ANT; + +typedef struct _COEX_STA_8703B_2ANT{ + BOOLEAN bBtLinkExist; + BOOLEAN bScoExist; + BOOLEAN bA2dpExist; + BOOLEAN bHidExist; + BOOLEAN bPanExist; + + BOOLEAN bUnderLps; + BOOLEAN bUnderIps; + u4Byte highPriorityTx; + u4Byte highPriorityRx; + u4Byte lowPriorityTx; + u4Byte lowPriorityRx; + u1Byte btRssi; + BOOLEAN bBtTxRxMask; + u1Byte preBtRssiState; + u1Byte preWifiRssiState[4]; + BOOLEAN bC2hBtInfoReqSent; + u1Byte btInfoC2h[BT_INFO_SRC_8703B_2ANT_MAX][10]; + u4Byte btInfoC2hCnt[BT_INFO_SRC_8703B_2ANT_MAX]; + BOOLEAN bBtWhckTest; + BOOLEAN bC2hBtInquiryPage; + u1Byte btRetryCnt; + u1Byte btInfoExt; + + u4Byte nCRCOK_CCK; + u4Byte nCRCOK_11g; + u4Byte nCRCOK_11n; + u4Byte nCRCOK_11nAgg; + + u4Byte nCRCErr_CCK; + u4Byte nCRCErr_11g; + u4Byte nCRCErr_11n; + u4Byte nCRCErr_11nAgg; + + u1Byte nCoexTableType; + BOOLEAN bForceLpsOn; + + u1Byte disVerInfoCnt; +}COEX_STA_8703B_2ANT, *PCOEX_STA_8703B_2ANT; + +//=========================================== +// The following is interface which will notify coex module. +//=========================================== +VOID +EXhalbtc8703b2ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8703b2ant_PreLoadFirmware( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8703b2ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ); +VOID +EXhalbtc8703b2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8703b2ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8703b2ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8703b2ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8703b2ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8703b2ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8703b2ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8703b2ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ); +VOID +EXhalbtc8703b2ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8703b2ant_PnpNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte pnpState + ); +VOID +EXhalbtc8703b2ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8703b2ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ); + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723a1Ant.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723a1Ant.c new file mode 100644 index 000000000..938df4459 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723a1Ant.c @@ -0,0 +1,1545 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//============================================================ +// Description: +// +// This file is for RTL8723A Co-exist mechanism +// +// History +// 2012/08/22 Cosa first check in. +// 2012/11/14 Cosa Revise for 8723A 1Ant out sourcing. +// +//============================================================ + +//============================================================ +// include files +//============================================================ +#include "Mp_Precomp.h" + +#if WPP_SOFTWARE_TRACE +#include "HalBtc8723a1Ant.tmh" +#endif + +#if(BT_30_SUPPORT == 1) +//============================================================ +// Global variables, these are static variables +//============================================================ +static COEX_DM_8723A_1ANT GLCoexDm8723a1Ant; +static PCOEX_DM_8723A_1ANT pCoexDm=&GLCoexDm8723a1Ant; +static COEX_STA_8723A_1ANT GLCoexSta8723a1Ant; +static PCOEX_STA_8723A_1ANT pCoexSta=&GLCoexSta8723a1Ant; + +const char *const GLBtInfoSrc8723a1Ant[]={ + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; + +//============================================================ +// local function proto type if needed +//============================================================ +//============================================================ +// local function start with halbtc8723a1ant_ +//============================================================ +VOID +halbtc8723a1ant_Reg0x550Bit3( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bSet + ) +{ + u1Byte u1tmp=0; + + u1tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x550); + if(bSet) + { + u1tmp |= BIT3; + } + else + { + u1tmp &= ~BIT3; + } + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x550, u1tmp); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], set 0x550[3]=%d\n", (bSet? 1:0))); +} + +VOID +halbtc8723a1ant_NotifyFwScan( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte scanType + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + if(BTC_SCAN_START == scanType) + H2C_Parameter[0] = 0x1; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Notify FW for wifi scan, write 0x3b=0x%x\n", + H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x3b, 1, H2C_Parameter); +} + +VOID +halbtc8723a1ant_QueryBtInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + pCoexSta->bC2hBtInfoReqSent = TRUE; + + H2C_Parameter[0] |= BIT0; // trigger + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Query Bt Info, FW write 0x38=0x%x\n", + H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x38, 1, H2C_Parameter); +} + +VOID +halbtc8723a1ant_SetSwRfRxLpfCorner( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bRxRfShrinkOn + ) +{ + if(bRxRfShrinkOn) + { + //Shrink RF Rx LPF corner + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Shrink RF Rx LPF corner!!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, 0xf0ff7); + } + else + { + //Resume RF Rx LPF corner + // After initialized, we can use pCoexDm->btRf0x1eBackup + if(pBtCoexist->bInitilized) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Resume RF Rx LPF corner!!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, pCoexDm->btRf0x1eBackup); + } + } +} + +VOID +halbtc8723a1ant_RfShrink( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bRxRfShrinkOn + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Rx RF Shrink = %s\n", + (bForceExec? "force to":""), ((bRxRfShrinkOn)? "ON":"OFF"))); + pCoexDm->bCurRfRxLpfShrink = bRxRfShrinkOn; + + if(!bForceExec) + { + if(pCoexDm->bPreRfRxLpfShrink == pCoexDm->bCurRfRxLpfShrink) + return; + } + halbtc8723a1ant_SetSwRfRxLpfCorner(pBtCoexist, pCoexDm->bCurRfRxLpfShrink); + + pCoexDm->bPreRfRxLpfShrink = pCoexDm->bCurRfRxLpfShrink; +} + +VOID +halbtc8723a1ant_SetSwPenaltyTxRateAdaptive( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bLowPenaltyRa + ) +{ + u1Byte tmpU1; + + tmpU1 = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4fd); + tmpU1 |= BIT0; + if(bLowPenaltyRa) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set low penalty!!\n")); + tmpU1 &= ~BIT2; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set normal!!\n")); + tmpU1 |= BIT2; + } + + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x4fd, tmpU1); +} + +VOID +halbtc8723a1ant_LowPenaltyRa( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bLowPenaltyRa + ) +{ + return; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn LowPenaltyRA = %s\n", + (bForceExec? "force to":""), ((bLowPenaltyRa)? "ON":"OFF"))); + pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa; + + if(!bForceExec) + { + if(pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa) + return; + } + halbtc8723a1ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa); + + pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa; +} + +VOID +halbtc8723a1ant_SetCoexTable( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte val0x6c0, + IN u4Byte val0x6c8, + IN u1Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c0=0x%x\n", val0x6c0)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c0, val0x6c0); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, val0x6c8); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc)); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cc, val0x6cc); +} + +VOID +halbtc8723a1ant_CoexTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u4Byte val0x6c0, + IN u4Byte val0x6c8, + IN u1Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s write Coex Table 0x6c0=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n", + (bForceExec? "force to":""), val0x6c0, val0x6c8, val0x6cc)); + pCoexDm->curVal0x6c0 = val0x6c0; + pCoexDm->curVal0x6c8 = val0x6c8; + pCoexDm->curVal0x6cc = val0x6cc; + + if(!bForceExec) + { + if( (pCoexDm->preVal0x6c0 == pCoexDm->curVal0x6c0) && + (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) && + (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) ) + return; + } + halbtc8723a1ant_SetCoexTable(pBtCoexist, val0x6c0, val0x6c8, val0x6cc); + + pCoexDm->preVal0x6c0 = pCoexDm->curVal0x6c0; + pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8; + pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc; +} + +VOID +halbtc8723a1ant_SetFwIgnoreWlanAct( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bEnable + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + if(bEnable) + { + H2C_Parameter[0] |= BIT0; // function enable + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set FW for BT Ignore Wlan_Act, FW write 0x25=0x%x\n", + H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x25, 1, H2C_Parameter); +} + +VOID +halbtc8723a1ant_IgnoreWlanAct( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bEnable + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Ignore WlanAct %s\n", + (bForceExec? "force to":""), (bEnable? "ON":"OFF"))); + pCoexDm->bCurIgnoreWlanAct = bEnable; + + if(!bForceExec) + { + if(pCoexDm->bPreIgnoreWlanAct == pCoexDm->bCurIgnoreWlanAct) + return; + } + halbtc8723a1ant_SetFwIgnoreWlanAct(pBtCoexist, bEnable); + + pCoexDm->bPreIgnoreWlanAct = pCoexDm->bCurIgnoreWlanAct; +} + +VOID +halbtc8723a1ant_SetFwPstdma( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type, + IN u1Byte byte1, + IN u1Byte byte2, + IN u1Byte byte3, + IN u1Byte byte4, + IN u1Byte byte5 + ) +{ + u1Byte H2C_Parameter[5] ={0}; + u1Byte realByte1=byte1, realByte5=byte5; + BOOLEAN bApEnable=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + + // byte1[1:0] != 0 means enable pstdma + // for 2Ant bt coexist, if byte1 != 0 means enable pstdma + if(byte1) + { + if(bApEnable) + { + if(type != 5 && type != 12) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], FW for 1Ant AP mode\n")); + realByte1 &= ~BIT4; + realByte1 |= BIT5; + + realByte5 |= BIT5; + realByte5 &= ~BIT6; + } + } + } + H2C_Parameter[0] = realByte1; + H2C_Parameter[1] = byte2; + H2C_Parameter[2] = byte3; + H2C_Parameter[3] = byte4; + H2C_Parameter[4] = realByte5; + + pCoexDm->psTdmaPara[0] = realByte1; + pCoexDm->psTdmaPara[1] = byte2; + pCoexDm->psTdmaPara[2] = byte3; + pCoexDm->psTdmaPara[3] = byte4; + pCoexDm->psTdmaPara[4] = realByte5; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x3a(5bytes)=0x%x%08x\n", + H2C_Parameter[0], + H2C_Parameter[1]<<24|H2C_Parameter[2]<<16|H2C_Parameter[3]<<8|H2C_Parameter[4])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x3a, 5, H2C_Parameter); +} + +VOID +halbtc8723a1ant_PsTdma( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bTurnOn, + IN u1Byte type + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn %s PS TDMA, type=%d\n", + (bForceExec? "force to":""), (bTurnOn? "ON":"OFF"), type)); + pCoexDm->bCurPsTdmaOn = bTurnOn; + pCoexDm->curPsTdma = type; + + if(!bForceExec) + { + if( (pCoexDm->bPrePsTdmaOn == pCoexDm->bCurPsTdmaOn) && + (pCoexDm->prePsTdma == pCoexDm->curPsTdma) ) + return; + } + if(pCoexDm->bCurPsTdmaOn) + { + switch(pCoexDm->curPsTdma) + { + case 1: + default: + halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x1a, 0x1a, 0x0, 0x40); + break; + case 2: + halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x12, 0x12, 0x0, 0x40); + break; + case 3: + halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x93, 0x3f, 0x3, 0x10, 0x40); + break; + case 4: + halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x93, 0x15, 0x3, 0x10, 0x0); + break; + case 5: + halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0xa9, 0x15, 0x3, 0x35, 0xc0); + break; + + case 8: + halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x93, 0x25, 0x3, 0x10, 0x0); + break; + case 9: + halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0xa, 0xa, 0x0, 0x40); + break; + case 10: + halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0xa, 0xa, 0x0, 0x40); + break; + case 11: + halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x5, 0x5, 0x0, 0x40); + break; + case 12: + halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0xa9, 0xa, 0x3, 0x15, 0xc0); + break; + + case 18: + halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x93, 0x25, 0x3, 0x10, 0x0); + break; + + case 20: + halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x2a, 0x2a, 0x0, 0x0); + break; + case 21: + halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x93, 0x20, 0x3, 0x10, 0x40); + break; + case 22: + halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x1a, 0x1a, 0x2, 0x40); + break; + case 23: + halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x12, 0x12, 0x2, 0x40); + break; + case 24: + halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0xa, 0xa, 0x2, 0x40); + break; + case 25: + halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x5, 0x5, 0x2, 0x40); + break; + case 26: + halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x93, 0x25, 0x3, 0x10, 0x0); + break; + case 27: + halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x13, 0x5, 0x5, 0x2, 0x40); + break; + case 28: + halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x3, 0x2f, 0x2f, 0x0, 0x0); + break; + + } + } + else + { + // disable PS tdma + switch(pCoexDm->curPsTdma) + { + case 8: + halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x8, 0x0, 0x0, 0x0, 0x0); + break; + case 0: + default: + halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x0, 0x0, 0x0, 0x0, 0x0); + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x860, 0x210); + break; + case 9: + halbtc8723a1ant_SetFwPstdma(pBtCoexist, type, 0x0, 0x0, 0x0, 0x0, 0x0); + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x860, 0x110); + break; + + } + } + + // update pre state + pCoexDm->bPrePsTdmaOn = pCoexDm->bCurPsTdmaOn; + pCoexDm->prePsTdma = pCoexDm->curPsTdma; +} + + +VOID +halbtc8723a1ant_CoexAllOff( + IN PBTC_COEXIST pBtCoexist + ) +{ + // fw all off + halbtc8723a1ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + + // sw all off + halbtc8723a1ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a1ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE); + + // hw all off + halbtc8723a1ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); +} + +VOID +halbtc8723a1ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + // force to reset coex mechanism + halbtc8723a1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE); +} + +VOID +halbtc8723a1ant_BtEnableAction( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8723a1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE); +} + +VOID +halbtc8723a1ant_MonitorBtCtr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte regHPTxRx, regLPTxRx, u4Tmp; + u4Byte regHPTx=0, regHPRx=0, regLPTx=0, regLPRx=0; + u1Byte u1Tmp; + + regHPTxRx = 0x770; + regLPTxRx = 0x774; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regHPTxRx); + regHPTx = u4Tmp & bMaskLWord; + regHPRx = (u4Tmp & bMaskHWord)>>16; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regLPTxRx); + regLPTx = u4Tmp & bMaskLWord; + regLPRx = (u4Tmp & bMaskHWord)>>16; + + pCoexSta->highPriorityTx = regHPTx; + pCoexSta->highPriorityRx = regHPRx; + pCoexSta->lowPriorityTx = regLPTx; + pCoexSta->lowPriorityRx = regLPRx; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", + regHPTxRx, regHPTx, regHPTx, regHPRx, regHPRx)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", + regLPTxRx, regLPTx, regLPTx, regLPRx, regLPRx)); + + // reset counter + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0xc); +} + +VOID +halbtc8723a1ant_MonitorBtEnableDisable( + IN PBTC_COEXIST pBtCoexist + ) +{ + static BOOLEAN bPreBtDisabled=FALSE; + static u4Byte btDisableCnt=0; + BOOLEAN bBtActive=TRUE, bBtDisabled=FALSE; + + // This function check if bt is disabled + + if( pCoexSta->highPriorityTx == 0 && + pCoexSta->highPriorityRx == 0 && + pCoexSta->lowPriorityTx == 0 && + pCoexSta->lowPriorityRx == 0) + { + bBtActive = FALSE; + } + if( pCoexSta->highPriorityTx == 0xffff && + pCoexSta->highPriorityRx == 0xffff && + pCoexSta->lowPriorityTx == 0xffff && + pCoexSta->lowPriorityRx == 0xffff) + { + bBtActive = FALSE; + } + if(bBtActive) + { + btDisableCnt = 0; + bBtDisabled = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is enabled !!\n")); + } + else + { + btDisableCnt++; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], bt all counters=0, %d times!!\n", + btDisableCnt)); + if(btDisableCnt >= 2) + { + bBtDisabled = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is disabled !!\n")); + } + } + if(bPreBtDisabled != bBtDisabled) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is from %s to %s!!\n", + (bPreBtDisabled ? "disabled":"enabled"), + (bBtDisabled ? "disabled":"enabled"))); + bPreBtDisabled = bBtDisabled; + if(!bBtDisabled) + { + halbtc8723a1ant_BtEnableAction(pBtCoexist); + } + else + { + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_NORMAL_LPS, NULL); + } + } +} + +VOID +halbtc8723a1ant_TdmaDurationAdjust( + IN PBTC_COEXIST pBtCoexist + ) +{ + static s4Byte up,dn,m,n,WaitCount; + s4Byte result; //0: no change, +1: increase WiFi duration, -1: decrease WiFi duration + u1Byte retryCount=0; + u1Byte btState; + BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE; + u4Byte wifiBw; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + btState = pCoexDm->btStatus; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], TdmaDurationAdjust()\n")); + if(pCoexDm->psTdmaGlobalCnt != pCoexDm->psTdmaMonitorCnt) + { + pCoexDm->psTdmaMonitorCnt = 0; + pCoexDm->psTdmaGlobalCnt = 0; + } + if(pCoexDm->psTdmaMonitorCnt == 0) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], first run BT A2DP + WiFi busy state!!\n")); + if(btState == BT_STATE_8723A_1ANT_ACL_ONLY_BUSY) + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + else + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 22); + pCoexDm->psTdmaDuAdjType = 22; + } + //============ + up = 0; + dn = 0; + m = 1; + n= 3; + result = 0; + WaitCount = 0; + } + else + { + //accquire the BT TRx retry count from BT_Info byte2 + retryCount = pCoexSta->btRetryCnt; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], retryCount = %d\n", retryCount)); + result = 0; + WaitCount++; + + if(retryCount == 0) // no retry in the last 2-second duration + { + up++; + dn--; + + if (dn <= 0) + dn = 0; + + if(up >= n) // if s n 2 retry count0, hռeWiFi duration + { + WaitCount = 0; + n = 3; + up = 0; + dn = 0; + result = 1; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Increase wifi duration!!\n")); + } + } + else if (retryCount <= 3) // <=3 retry in the last 2-second duration + { + up--; + dn++; + + if (up <= 0) + up = 0; + + if (dn == 2) // if s 2 2 retry count< 3, hկWiFi duration + { + if (WaitCount <= 2) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Decrease wifi duration for retryCounter<3!!\n")); + } + } + else //retry count > 3, un1 retry count > 3, hկWiFi duration + { + if (WaitCount == 1) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Decrease wifi duration for retryCounter>3!!\n")); + } + + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT TxRx counter H+L <= 1200\n")); + if(btState != BT_STATE_8723A_1ANT_ACL_ONLY_BUSY) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], NOT ACL only busy!\n")); + if(BTC_WIFI_BW_HT40 != wifiBw) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 20MHz\n")); + if(result == -1) + { + if(pCoexDm->curPsTdma == 22) + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 23); + pCoexDm->psTdmaDuAdjType = 23; + } + else if(pCoexDm->curPsTdma == 23) + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 24); + pCoexDm->psTdmaDuAdjType = 24; + } + else if(pCoexDm->curPsTdma == 24) + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 25); + pCoexDm->psTdmaDuAdjType = 25; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 25) + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 24); + pCoexDm->psTdmaDuAdjType = 24; + } + else if(pCoexDm->curPsTdma == 24) + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 23); + pCoexDm->psTdmaDuAdjType = 23; + } + else if(pCoexDm->curPsTdma == 23) + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 22); + pCoexDm->psTdmaDuAdjType = 22; + } + } + // error handle, if not in the following state, + // set psTdma again. + if( (pCoexDm->psTdmaDuAdjType != 22) && + (pCoexDm->psTdmaDuAdjType != 23) && + (pCoexDm->psTdmaDuAdjType != 24) && + (pCoexDm->psTdmaDuAdjType != 25) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], duration case out of handle!!\n")); + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 23); + pCoexDm->psTdmaDuAdjType = 23; + } + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 40MHz\n")); + if(result == -1) + { + if(pCoexDm->curPsTdma == 23) + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 24); + pCoexDm->psTdmaDuAdjType = 24; + } + else if(pCoexDm->curPsTdma == 24) + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 25); + pCoexDm->psTdmaDuAdjType = 25; + } + else if(pCoexDm->curPsTdma == 25) + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 27); + pCoexDm->psTdmaDuAdjType = 27; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 27) + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 25); + pCoexDm->psTdmaDuAdjType = 25; + } + else if(pCoexDm->curPsTdma == 25) + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 24); + pCoexDm->psTdmaDuAdjType = 24; + } + else if(pCoexDm->curPsTdma == 24) + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 23); + pCoexDm->psTdmaDuAdjType = 23; + } + } + // error handle, if not in the following state, + // set psTdma again. + if( (pCoexDm->psTdmaDuAdjType != 23) && + (pCoexDm->psTdmaDuAdjType != 24) && + (pCoexDm->psTdmaDuAdjType != 25) && + (pCoexDm->psTdmaDuAdjType != 27) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], duration case out of handle!!\n")); + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 24); + pCoexDm->psTdmaDuAdjType = 24; + } + } + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ACL only busy\n")); + if (result == -1) + { + if(pCoexDm->curPsTdma == 1) + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 11) + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + } + + // error handle, if not in the following state, + // set psTdma again. + if( (pCoexDm->psTdmaDuAdjType != 1) && + (pCoexDm->psTdmaDuAdjType != 2) && + (pCoexDm->psTdmaDuAdjType != 9) && + (pCoexDm->psTdmaDuAdjType != 11) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], duration case out of handle!!\n")); + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + } + } + } + + // if current PsTdma not match with the recorded one (when scan, dhcp...), + // then we have to adjust it back to the previous record one. + if(pCoexDm->curPsTdma != pCoexDm->psTdmaDuAdjType) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PsTdma type dismatch!!!, curPsTdma=%d, recordPsTdma=%d\n", + pCoexDm->curPsTdma, pCoexDm->psTdmaDuAdjType)); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + + if( !bScan && !bLink && !bRoam) + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, pCoexDm->psTdmaDuAdjType); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n")); + } + } + pCoexDm->psTdmaMonitorCnt++; +} + + +VOID +halbtc8723a1ant_CoexForWifiConnect( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bWifiConnected=FALSE, bWifiBusy=FALSE; + u1Byte btState, btInfoOriginal=0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + + btState = pCoexDm->btStatus; + btInfoOriginal = pCoexSta->btInfoC2h[BT_INFO_SRC_8723A_1ANT_BT_RSP][0]; + + if(bWifiConnected) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi connected!!\n")); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + + if( !bWifiBusy && + ((BT_STATE_8723A_1ANT_NO_CONNECTION == btState) || + (BT_STATE_8723A_1ANT_CONNECT_IDLE == btState)) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], [Wifi is idle] or [Bt is non connected idle or Bt is connected idle]!!\n")); + + if(BT_STATE_8723A_1ANT_NO_CONNECTION == btState) + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 9); + else if(BT_STATE_8723A_1ANT_CONNECT_IDLE == btState) + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + + pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xff000000, 0xc0); + } + else + { + if( (BT_STATE_8723A_1ANT_SCO_ONLY_BUSY == btState) || + (BT_STATE_8723A_1ANT_ACL_SCO_BUSY == btState) || + (BT_STATE_8723A_1ANT_HID_BUSY == btState) || + (BT_STATE_8723A_1ANT_HID_SCO_BUSY == btState) ) + { + pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xff000000, 0x60); + } + else + { + pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xff000000, 0xc0); + } + switch(btState) + { + case BT_STATE_8723A_1ANT_NO_CONNECTION: + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + break; + case BT_STATE_8723A_1ANT_CONNECT_IDLE: + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + break; + case BT_STATE_8723A_1ANT_INQ_OR_PAG: + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + break; + case BT_STATE_8723A_1ANT_SCO_ONLY_BUSY: + case BT_STATE_8723A_1ANT_ACL_SCO_BUSY: + case BT_STATE_8723A_1ANT_HID_BUSY: + case BT_STATE_8723A_1ANT_HID_SCO_BUSY: + halbtc8723a1ant_TdmaDurationAdjust(pBtCoexist); + break; + case BT_STATE_8723A_1ANT_ACL_ONLY_BUSY: + if (btInfoOriginal&BT_INFO_8723A_1ANT_B_A2DP) + { + halbtc8723a1ant_TdmaDurationAdjust(pBtCoexist); + } + else if(btInfoOriginal&BT_INFO_8723A_1ANT_B_FTP) + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + } + else if( (btInfoOriginal&BT_INFO_8723A_1ANT_B_A2DP) && + (btInfoOriginal&BT_INFO_8723A_1ANT_B_FTP) ) + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + } + else + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + } + break; + default: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], error!!!, undefined case in halbtc8723a1ant_CoexForWifiConnect()!!\n")); + break; + } + } + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi is disconnected!!\n")); + } + + pCoexDm->psTdmaGlobalCnt++; +} + +//============================================================ +// work around function start with wa_halbtc8723a1ant_ +//============================================================ +VOID +wa_halbtc8723a1ant_MonitorC2h( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte tmp1b=0x0; + u4Byte curC2hTotalCnt=0x0; + static u4Byte preC2hTotalCnt=0x0, sameCntPollingTime=0x0; + + curC2hTotalCnt+=pCoexSta->btInfoC2hCnt[BT_INFO_SRC_8723A_1ANT_BT_RSP]; + + if(curC2hTotalCnt == preC2hTotalCnt) + { + sameCntPollingTime++; + } + else + { + preC2hTotalCnt = curC2hTotalCnt; + sameCntPollingTime = 0; + } + + if(sameCntPollingTime >= 2) + { + tmp1b = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x1af); + if(tmp1b != 0x0) + { + pCoexSta->c2hHangDetectCnt++; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x1af, 0x0); + } + } +} + +//============================================================ +// extern function start with EXhalbtc8723a1ant_ +//============================================================ +VOID +EXhalbtc8723a1ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 1Ant Init HW Config!!\n")); + + // backup rf 0x1e value + pCoexDm->btRf0x1eBackup = + pBtCoexist->fBtcGetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff); + + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x20); + + // enable counter statistics + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0x4); + + // coex table + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cc, 0x0); // 1-Ant coex + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, 0xffff); // wifi break table + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c4, 0x55555555); //coex table + + // antenna switch control parameter + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x858, 0xaaaaaaaa); + + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x860, 0x210); //set antenna at wifi side if ANTSW is software control + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x870, 0x300); //SPDT(connected with TRSW) control by hardware PTA + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x874, 0x22804000); //ANTSW keep by GNT_BT + + // coexistence parameters + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x778, 0x1); // enable RTK mode PTA +} + +VOID +EXhalbtc8723a1ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Coex Mechanism Init!!\n")); + + halbtc8723a1ant_InitCoexDm(pBtCoexist); +} + +VOID +EXhalbtc8723a1ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + pu1Byte cliBuf=pBtCoexist->cliBuf; + u1Byte u1Tmp[4], i, btInfoExt, psTdmaCase=0; + u4Byte u4Tmp[4]; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:", \ + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum); + CL_PRINTF(cliBuf); + + if(pBtCoexist->bManualControl) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "[Action Manual control]!!"); + CL_PRINTF(cliBuf); + } + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \ + ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", "Wifi channel informed to BT", \ + pCoexDm->wifiChnlInfo[0], pCoexDm->wifiChnlInfo[1], + pCoexDm->wifiChnlInfo[2]); + CL_PRINTF(cliBuf); + + // wifi status + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Wifi Status]============"); + CL_PRINTF(cliBuf); + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[BT Status]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", "BT [status/ rssi/ retryCnt]", \ + ((pCoexSta->bC2hBtInquiryPage)?("inquiry/page scan"):((BT_8723A_1ANT_BT_STATUS_IDLE == pCoexDm->btStatus)? "idle":( (BT_8723A_1ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus)? "connected-idle":"busy"))), + pCoexSta->btRssi, pCoexSta->btRetryCnt); + CL_PRINTF(cliBuf); + + if(pStackInfo->bProfileNotified) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP", \ + pStackInfo->bScoExist, pStackInfo->bHidExist, pStackInfo->bPanExist, pStackInfo->bA2dpExist); + CL_PRINTF(cliBuf); + + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO); + } + + btInfoExt = pCoexSta->btInfoExt; + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Info A2DP rate", \ + (btInfoExt&BIT0)? "Basic rate":"EDR rate"); + CL_PRINTF(cliBuf); + + for(i=0; ibtInfoC2hCnt[i]) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", GLBtInfoSrc8723a1Ant[i], \ + pCoexSta->btInfoC2h[i][0], pCoexSta->btInfoC2h[i][1], + pCoexSta->btInfoC2h[i][2], pCoexSta->btInfoC2h[i][3], + pCoexSta->btInfoC2h[i][4], pCoexSta->btInfoC2h[i][5], + pCoexSta->btInfoC2h[i][6], pCoexSta->btInfoC2hCnt[i]); + CL_PRINTF(cliBuf); + } + } + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "write 0x1af=0x0 num", \ + pCoexSta->c2hHangDetectCnt); + CL_PRINTF(cliBuf); + + // Sw mechanism + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============"); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", "SM1[ShRf/ LpRA/ LimDig]", \ + pCoexDm->bCurRfRxLpfShrink, pCoexDm->bCurLowPenaltyRa, pCoexDm->bLimitedDig); + CL_PRINTF(cliBuf); + + // Fw mechanism + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============"); + CL_PRINTF(cliBuf); + + if(!pBtCoexist->bManualControl) + { + psTdmaCase = pCoexDm->curPsTdma; + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x case-%d", "PS TDMA", \ + pCoexDm->psTdmaPara[0], pCoexDm->psTdmaPara[1], + pCoexDm->psTdmaPara[2], pCoexDm->psTdmaPara[3], + pCoexDm->psTdmaPara[4], psTdmaCase); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ", "IgnWlanAct", \ + pCoexDm->bCurIgnoreWlanAct); + CL_PRINTF(cliBuf); + } + + // Hw setting + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "RF-A, 0x1e initVal", \ + pCoexDm->btRf0x1eBackup); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x778); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x783); + u1Tmp[2] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x796); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x778/ 0x783/ 0x796", \ + u1Tmp[0], u1Tmp[1], u1Tmp[2]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x880); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x880", \ + u4Tmp[0]); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x40); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x40", \ + u1Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x550); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x522); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x550(bcn ctrl)/0x522", \ + u4Tmp[0], u1Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x484); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x484(rate adaptive)", \ + u4Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc50); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", \ + u4Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda0); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda4); + u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda8); + u4Tmp[3] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xdac); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0xda0/0xda4/0xda8/0xdac(FA cnt)", \ + u4Tmp[0], u4Tmp[1], u4Tmp[2], u4Tmp[3]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c0); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c4); + u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c8); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x6cc); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", \ + u4Tmp[0], u4Tmp[1], u4Tmp[2], u1Tmp[0]); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x770 (hp rx[31:16]/tx[15:0])", \ + pCoexSta->highPriorityRx, pCoexSta->highPriorityTx); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x774(lp rx[31:16]/tx[15:0])", \ + pCoexSta->lowPriorityRx, pCoexSta->lowPriorityTx); + CL_PRINTF(cliBuf); + + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + + +VOID +EXhalbtc8723a1ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_IPS_ENTER == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS ENTER notify\n")); + halbtc8723a1ant_CoexAllOff(pBtCoexist); + } + else if(BTC_IPS_LEAVE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS LEAVE notify\n")); + //halbtc8723a1ant_InitCoexDm(pBtCoexist); + } +} + +VOID +EXhalbtc8723a1ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_LPS_ENABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS ENABLE notify\n")); + } + else if(BTC_LPS_DISABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS DISABLE notify\n")); + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + } +} + +VOID +EXhalbtc8723a1ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + BOOLEAN bWifiConnected=FALSE; + + halbtc8723a1ant_NotifyFwScan(pBtCoexist, type); + + if(pBtCoexist->btInfo.bBtDisabled) + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 9); + } + else + { + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + if(BTC_SCAN_START == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n")); + if(!bWifiConnected) // non-connected scan + { + //set 0x550[3]=1 before PsTdma + halbtc8723a1ant_Reg0x550Bit3(pBtCoexist, TRUE); + } + + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + } + else if(BTC_SCAN_FINISH == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n")); + if(!bWifiConnected) // non-connected scan + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + } + else + { + halbtc8723a1ant_CoexForWifiConnect(pBtCoexist); + } + } + } +} + +VOID +EXhalbtc8723a1ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + BOOLEAN bWifiConnected=FALSE; + + if(pBtCoexist->btInfo.bBtDisabled) + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 9); + } + else + { + if(BTC_ASSOCIATE_START == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n")); + //set 0x550[3]=1 before PsTdma + halbtc8723a1ant_Reg0x550Bit3(pBtCoexist, TRUE); + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); // extend wifi slot + } + else if(BTC_ASSOCIATE_FINISH == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n")); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + if(!bWifiConnected) // non-connected scan + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + } + else + { + halbtc8723a1ant_CoexForWifiConnect(pBtCoexist); + } + } + } +} + +VOID +EXhalbtc8723a1ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_MEDIA_CONNECT == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA connect notify\n")); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA disconnect notify\n")); + } +} + +VOID +EXhalbtc8723a1ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(type == BTC_PACKET_DHCP) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], DHCP Packet notify\n")); + if(pBtCoexist->btInfo.bBtDisabled) + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 9); + } + else + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 18); + } + } +} + +VOID +EXhalbtc8723a1ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ) +{ + u1Byte btInfo=0; + u1Byte i, rspSource=0; + BOOLEAN bBtHsOn=FALSE, bBtBusy=FALSE, bForceLps=FALSE; + + pCoexSta->bC2hBtInfoReqSent = FALSE; + + rspSource = BT_INFO_SRC_8723A_1ANT_BT_RSP; + pCoexSta->btInfoC2hCnt[rspSource]++; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Bt info[%d], length=%d, hex data=[", rspSource, length)); + for(i=0; ibtInfoC2h[rspSource][i] = tmpBuf[i]; + if(i == 0) + btInfo = tmpBuf[i]; + if(i == length-1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x]\n", tmpBuf[i])); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x, ", tmpBuf[i])); + } + } + + if(BT_INFO_SRC_8723A_1ANT_WIFI_FW != rspSource) + { + pCoexSta->btRetryCnt = + pCoexSta->btInfoC2h[rspSource][1]; + + pCoexSta->btRssi = + pCoexSta->btInfoC2h[rspSource][2]*2+10; + + pCoexSta->btInfoExt = + pCoexSta->btInfoC2h[rspSource][3]; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + // check BIT2 first ==> check if bt is under inquiry or page scan + if(btInfo & BT_INFO_8723A_1ANT_B_INQ_PAGE) + { + pCoexSta->bC2hBtInquiryPage = TRUE; + } + else + { + pCoexSta->bC2hBtInquiryPage = FALSE; + } + btInfo &= ~BIT2; + if(!(btInfo & BIT0)) + { + pCoexDm->btStatus = BT_STATE_8723A_1ANT_NO_CONNECTION; + bForceLps = FALSE; + } + else + { + bForceLps = TRUE; + if(btInfo == 0x1) + { + pCoexDm->btStatus = BT_STATE_8723A_1ANT_CONNECT_IDLE; + } + else if(btInfo == 0x9) + { + pCoexDm->btStatus = BT_STATE_8723A_1ANT_ACL_ONLY_BUSY; + bBtBusy = TRUE; + } + else if(btInfo == 0x13) + { + pCoexDm->btStatus = BT_STATE_8723A_1ANT_SCO_ONLY_BUSY; + bBtBusy = TRUE; + } + else if(btInfo == 0x1b) + { + pCoexDm->btStatus = BT_STATE_8723A_1ANT_ACL_SCO_BUSY; + bBtBusy = TRUE; + } + else if(btInfo == 0x29) + { + pCoexDm->btStatus = BT_STATE_8723A_1ANT_HID_BUSY; + bBtBusy = TRUE; + } + else if(btInfo == 0x3b) + { + pCoexDm->btStatus = BT_STATE_8723A_1ANT_HID_SCO_BUSY; + bBtBusy = TRUE; + } + } + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bBtBusy); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_LIMITED_DIG, &bBtBusy); + if(bForceLps) + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_ENTER_LPS, NULL); + else + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_NORMAL_LPS, NULL); + + if( (BT_STATE_8723A_1ANT_NO_CONNECTION == pCoexDm->btStatus) || + (BT_STATE_8723A_1ANT_CONNECT_IDLE == pCoexDm->btStatus) ) + { + if(pCoexSta->bC2hBtInquiryPage) + pCoexDm->btStatus = BT_STATE_8723A_1ANT_INQ_OR_PAG; + } +} + +VOID +EXhalbtc8723a1ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8723a1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); + + halbtc8723a1ant_LowPenaltyRa(pBtCoexist, FORCE_EXEC, FALSE); + halbtc8723a1ant_RfShrink(pBtCoexist, FORCE_EXEC, FALSE); + + halbtc8723a1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE); + EXhalbtc8723a1ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); +} + +VOID +EXhalbtc8723a1ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE, bWifiConnected=FALSE; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 1Ant Periodical!!\n")); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + + // work around for c2h hang + wa_halbtc8723a1ant_MonitorC2h(pBtCoexist); + + halbtc8723a1ant_QueryBtInfo(pBtCoexist); + halbtc8723a1ant_MonitorBtCtr(pBtCoexist); + halbtc8723a1ant_MonitorBtEnableDisable(pBtCoexist); + + + if(bScan) + return; + if(bLink) + return; + + if(bWifiConnected) + { + if(pBtCoexist->btInfo.bBtDisabled) + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 9); + + halbtc8723a1ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a1ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE); + } + else + { + halbtc8723a1ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a1ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a1ant_CoexForWifiConnect(pBtCoexist); + } + } + else + { + halbtc8723a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + + halbtc8723a1ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a1ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE); + } +} + + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723a1Ant.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723a1Ant.h new file mode 100644 index 000000000..e1c096e28 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723a1Ant.h @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//=========================================== +// The following is for 8723A 1Ant BT Co-exist definition +//=========================================== +#define BT_INFO_8723A_1ANT_B_FTP BIT7 +#define BT_INFO_8723A_1ANT_B_A2DP BIT6 +#define BT_INFO_8723A_1ANT_B_HID BIT5 +#define BT_INFO_8723A_1ANT_B_SCO_BUSY BIT4 +#define BT_INFO_8723A_1ANT_B_ACL_BUSY BIT3 +#define BT_INFO_8723A_1ANT_B_INQ_PAGE BIT2 +#define BT_INFO_8723A_1ANT_B_SCO_ESCO BIT1 +#define BT_INFO_8723A_1ANT_B_CONNECTION BIT0 + +typedef enum _BT_STATE_8723A_1ANT{ + BT_STATE_8723A_1ANT_DISABLED = 0, + BT_STATE_8723A_1ANT_NO_CONNECTION = 1, + BT_STATE_8723A_1ANT_CONNECT_IDLE = 2, + BT_STATE_8723A_1ANT_INQ_OR_PAG = 3, + BT_STATE_8723A_1ANT_ACL_ONLY_BUSY = 4, + BT_STATE_8723A_1ANT_SCO_ONLY_BUSY = 5, + BT_STATE_8723A_1ANT_ACL_SCO_BUSY = 6, + BT_STATE_8723A_1ANT_HID_BUSY = 7, + BT_STATE_8723A_1ANT_HID_SCO_BUSY = 8, + BT_STATE_8723A_1ANT_MAX +}BT_STATE_8723A_1ANT, *PBT_STATE_8723A_1ANT; + +#define BTC_RSSI_COEX_THRESH_TOL_8723A_1ANT 2 + +typedef enum _BT_INFO_SRC_8723A_1ANT{ + BT_INFO_SRC_8723A_1ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8723A_1ANT_BT_RSP = 0x1, + BT_INFO_SRC_8723A_1ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8723A_1ANT_MAX +}BT_INFO_SRC_8723A_1ANT,*PBT_INFO_SRC_8723A_1ANT; + +typedef enum _BT_8723A_1ANT_BT_STATUS{ + BT_8723A_1ANT_BT_STATUS_IDLE = 0x0, + BT_8723A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8723A_1ANT_BT_STATUS_NON_IDLE = 0x2, + BT_8723A_1ANT_BT_STATUS_MAX +}BT_8723A_1ANT_BT_STATUS,*PBT_8723A_1ANT_BT_STATUS; + +typedef enum _BT_8723A_1ANT_COEX_ALGO{ + BT_8723A_1ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8723A_1ANT_COEX_ALGO_SCO = 0x1, + BT_8723A_1ANT_COEX_ALGO_HID = 0x2, + BT_8723A_1ANT_COEX_ALGO_A2DP = 0x3, + BT_8723A_1ANT_COEX_ALGO_PANEDR = 0x4, + BT_8723A_1ANT_COEX_ALGO_PANHS = 0x5, + BT_8723A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x6, + BT_8723A_1ANT_COEX_ALGO_PANEDR_HID = 0x7, + BT_8723A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x8, + BT_8723A_1ANT_COEX_ALGO_HID_A2DP = 0x9, + BT_8723A_1ANT_COEX_ALGO_MAX +}BT_8723A_1ANT_COEX_ALGO,*PBT_8723A_1ANT_COEX_ALGO; + +typedef struct _COEX_DM_8723A_1ANT{ + // fw mechanism + BOOLEAN bCurIgnoreWlanAct; + BOOLEAN bPreIgnoreWlanAct; + u1Byte prePsTdma; + u1Byte curPsTdma; + u1Byte psTdmaPara[5]; + u1Byte psTdmaDuAdjType; + u4Byte psTdmaMonitorCnt; + u4Byte psTdmaGlobalCnt; + BOOLEAN bResetTdmaAdjust; + BOOLEAN bPrePsTdmaOn; + BOOLEAN bCurPsTdmaOn; + + // sw mechanism + BOOLEAN bPreRfRxLpfShrink; + BOOLEAN bCurRfRxLpfShrink; + u4Byte btRf0x1eBackup; + BOOLEAN bPreLowPenaltyRa; + BOOLEAN bCurLowPenaltyRa; + u4Byte preVal0x6c0; + u4Byte curVal0x6c0; + u4Byte preVal0x6c8; + u4Byte curVal0x6c8; + u1Byte preVal0x6cc; + u1Byte curVal0x6cc; + BOOLEAN bLimitedDig; + + // algorithm related + u1Byte preAlgorithm; + u1Byte curAlgorithm; + u1Byte btStatus; + u1Byte wifiChnlInfo[3]; +} COEX_DM_8723A_1ANT, *PCOEX_DM_8723A_1ANT; + +typedef struct _COEX_STA_8723A_1ANT{ + u4Byte highPriorityTx; + u4Byte highPriorityRx; + u4Byte lowPriorityTx; + u4Byte lowPriorityRx; + u1Byte btRssi; + u1Byte preBtRssiState; + u1Byte preBtRssiState1; + u1Byte preWifiRssiState[4]; + BOOLEAN bC2hBtInfoReqSent; + u1Byte btInfoC2h[BT_INFO_SRC_8723A_1ANT_MAX][10]; + u4Byte btInfoC2hCnt[BT_INFO_SRC_8723A_1ANT_MAX]; + BOOLEAN bC2hBtInquiryPage; + u1Byte btRetryCnt; + u1Byte btInfoExt; + //BOOLEAN bHoldForStackOperation; + //u1Byte bHoldPeriodCnt; + // this is for c2h hang work-around + u4Byte c2hHangDetectCnt; +}COEX_STA_8723A_1ANT, *PCOEX_STA_8723A_1ANT; + +//=========================================== +// The following is interface which will notify coex module. +//=========================================== +VOID +EXhalbtc8723a1ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8723a1ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8723a1ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8723a1ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8723a1ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8723a1ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8723a1ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8723a1ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8723a1ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ); +VOID +EXhalbtc8723a1ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8723a1ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8723a1ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ); + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723a2Ant.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723a2Ant.c new file mode 100644 index 000000000..13354570e --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723a2Ant.c @@ -0,0 +1,3747 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//============================================================ +// Description: +// +// This file is for RTL8723A Co-exist mechanism +// +// History +// 2012/08/22 Cosa first check in. +// 2012/11/14 Cosa Revise for 8723A 2Ant out sourcing. +// +//============================================================ + +//============================================================ +// include files +//============================================================ +#include "Mp_Precomp.h" + +#if WPP_SOFTWARE_TRACE +#include "HalBtc8723a2Ant.tmh" +#endif + +#if(BT_30_SUPPORT == 1) +//============================================================ +// Global variables, these are static variables +//============================================================ +static COEX_DM_8723A_2ANT GLCoexDm8723a2Ant; +static PCOEX_DM_8723A_2ANT pCoexDm=&GLCoexDm8723a2Ant; +static COEX_STA_8723A_2ANT GLCoexSta8723a2Ant; +static PCOEX_STA_8723A_2ANT pCoexSta=&GLCoexSta8723a2Ant; + +const char *const GLBtInfoSrc8723a2Ant[]={ + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; + +//============================================================ +// local function proto type if needed +//============================================================ +//============================================================ +// local function start with halbtc8723a2ant_ +//============================================================ +BOOLEAN +halbtc8723a2ant_IsWifiIdle( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bWifiConnected=FALSE, bScan=FALSE, bLink=FALSE, bRoam=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + + if(bWifiConnected) + return FALSE; + if(bScan) + return FALSE; + if(bLink) + return FALSE; + if(bRoam) + return FALSE; + + return TRUE; +} + +BOOLEAN +halbtc8723a2ant_IsWifiConnectedIdle( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bWifiConnected=FALSE, bScan=FALSE, bLink=FALSE, bRoam=FALSE, bWifiBusy=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + + if(bScan) + return FALSE; + if(bLink) + return FALSE; + if(bRoam) + return FALSE; + if(bWifiConnected && !bWifiBusy) + return TRUE; + else + return FALSE; +} + +u1Byte +halbtc8723a2ant_BtRssiState( + u1Byte levelNum, + u1Byte rssiThresh, + u1Byte rssiThresh1 + ) +{ + s4Byte btRssi=0; + u1Byte btRssiState=pCoexSta->preBtRssiState; + + btRssi = pCoexSta->btRssi; + + if(levelNum == 2) + { + if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW)) + { + if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT)) + { + btRssiState = BTC_RSSI_STATE_HIGH; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else + { + if(btRssi < rssiThresh) + { + btRssiState = BTC_RSSI_STATE_LOW; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + else if(levelNum == 3) + { + if(rssiThresh > rssiThresh1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Rssi thresh error!!\n")); + return pCoexSta->preBtRssiState; + } + + if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW)) + { + if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT)) + { + btRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_MEDIUM) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_MEDIUM)) + { + if(btRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT)) + { + btRssiState = BTC_RSSI_STATE_HIGH; + } + else if(btRssi < rssiThresh) + { + btRssiState = BTC_RSSI_STATE_LOW; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_MEDIUM; + } + } + else + { + if(btRssi < rssiThresh1) + { + btRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + + pCoexSta->preBtRssiState = btRssiState; + + return btRssiState; +} + +u1Byte +halbtc8723a2ant_WifiRssiState( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte index, + IN u1Byte levelNum, + IN u1Byte rssiThresh, + IN u1Byte rssiThresh1 + ) +{ + s4Byte wifiRssi=0; + u1Byte wifiRssiState=pCoexSta->preWifiRssiState[index]; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); + + if(levelNum == 2) + { + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else + { + if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + else if(levelNum == 3) + { + if(rssiThresh > rssiThresh1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi RSSI thresh error!!\n")); + return pCoexSta->preWifiRssiState[index]; + } + + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT)) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_MEDIUM) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_MEDIUM)) + { + if(wifiRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_MEDIUM; + } + } + else + { + if(wifiRssi < rssiThresh1) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + + pCoexSta->preWifiRssiState[index] = wifiRssiState; + + return wifiRssiState; +} + +VOID +halbtc8723a2ant_IndicateWifiChnlBwInfo( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + u1Byte H2C_Parameter[3] ={0}; + u4Byte wifiBw; + u1Byte wifiCentralChnl; + + // only 2.4G we need to inform bt the chnl mask + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, &wifiCentralChnl); + if( (BTC_MEDIA_CONNECT == type) && + (wifiCentralChnl <= 14) ) + { + H2C_Parameter[0] = 0x1; + H2C_Parameter[1] = wifiCentralChnl; + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + H2C_Parameter[2] = 0x30; + else + H2C_Parameter[2] = 0x20; + } + + pCoexDm->wifiChnlInfo[0] = H2C_Parameter[0]; + pCoexDm->wifiChnlInfo[1] = H2C_Parameter[1]; + pCoexDm->wifiChnlInfo[2] = H2C_Parameter[2]; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x19=0x%x\n", + H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x19, 3, H2C_Parameter); +} + +VOID +halbtc8723a2ant_QueryBtInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + pCoexSta->bC2hBtInfoReqSent = TRUE; + + H2C_Parameter[0] |= BIT0; // trigger + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Query Bt Info, FW write 0x38=0x%x\n", + H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x38, 1, H2C_Parameter); +} +u1Byte +halbtc8723a2ant_ActionAlgorithm( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + BOOLEAN bBtHsOn=FALSE, bBtBusy=FALSE, bLimitedDig=FALSE; + u1Byte algorithm=BT_8723A_2ANT_COEX_ALGO_UNDEFINED; + u1Byte numOfDiffProfile=0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + //====================== + // here we get BT status first + //====================== + pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_IDLE; + + if((pStackInfo->bScoExist) ||(bBtHsOn) ||(pStackInfo->bHidExist)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO or HID or HS exists, set BT non-idle !!!\n")); + pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_NON_IDLE; + } + else + { + // A2dp profile + if( (pBtCoexist->stackInfo.numOfLink == 1) && + (pStackInfo->bA2dpExist) ) + { + if( (pCoexSta->lowPriorityTx+ pCoexSta->lowPriorityRx) < 100) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP, low priority tx+rx < 100, set BT connected-idle!!!\n")); + pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP, low priority tx+rx >= 100, set BT non-idle!!!\n")); + pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_NON_IDLE; + } + } + // Pan profile + if( (pBtCoexist->stackInfo.numOfLink == 1) && + (pStackInfo->bPanExist) ) + { + if((pCoexSta->lowPriorityTx+ pCoexSta->lowPriorityRx) < 600) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN, low priority tx+rx < 600, set BT connected-idle!!!\n")); + pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE; + } + else + { + if(pCoexSta->lowPriorityTx) + { + if((pCoexSta->lowPriorityRx /pCoexSta->lowPriorityTx)>9 ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN, low priority rx/tx > 9, set BT connected-idle!!!\n")); + pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE; + } + } + } + if(BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE != pCoexDm->btStatus) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN, set BT non-idle!!!\n")); + pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_NON_IDLE; + } + } + // Pan+A2dp profile + if( (pBtCoexist->stackInfo.numOfLink == 2) && + (pStackInfo->bA2dpExist) && + (pStackInfo->bPanExist) ) + { + if((pCoexSta->lowPriorityTx+ pCoexSta->lowPriorityRx) < 600) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN+A2DP, low priority tx+rx < 600, set BT connected-idle!!!\n")); + pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE; + } + else + { + if(pCoexSta->lowPriorityTx) + { + if((pCoexSta->lowPriorityRx /pCoexSta->lowPriorityTx)>9 ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN+A2DP, low priority rx/tx > 9, set BT connected-idle!!!\n")); + pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE; + } + } + } + if(BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE != pCoexDm->btStatus) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN+A2DP, set BT non-idle!!!\n")); + pCoexDm->btStatus = BT_8723A_2ANT_BT_STATUS_NON_IDLE; + } + } + } + if(BT_8723A_2ANT_BT_STATUS_IDLE != pCoexDm->btStatus) + { + bBtBusy = TRUE; + bLimitedDig = TRUE; + } + else + { + bBtBusy = FALSE; + bLimitedDig = FALSE; + } + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bBtBusy); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_LIMITED_DIG, &bLimitedDig); + //====================== + + if(!pStackInfo->bBtLinkExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], No profile exists!!!\n")); + return algorithm; + } + + if(pStackInfo->bScoExist) + numOfDiffProfile++; + if(pStackInfo->bHidExist) + numOfDiffProfile++; + if(pStackInfo->bPanExist) + numOfDiffProfile++; + if(pStackInfo->bA2dpExist) + numOfDiffProfile++; + + if(numOfDiffProfile == 1) + { + if(pStackInfo->bScoExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO only\n")); + algorithm = BT_8723A_2ANT_COEX_ALGO_SCO; + } + else + { + if(pStackInfo->bHidExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID only\n")); + algorithm = BT_8723A_2ANT_COEX_ALGO_HID; + } + else if(pStackInfo->bA2dpExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP only\n")); + algorithm = BT_8723A_2ANT_COEX_ALGO_A2DP; + } + else if(pStackInfo->bPanExist) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN(HS) only\n")); + algorithm = BT_8723A_2ANT_COEX_ALGO_PANHS; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN(EDR) only\n")); + algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR; + } + } + } + } + else if(numOfDiffProfile == 2) + { + if(pStackInfo->bScoExist) + { + if(pStackInfo->bHidExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID\n")); + algorithm = BT_8723A_2ANT_COEX_ALGO_HID; + } + else if(pStackInfo->bA2dpExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + A2DP ==> SCO\n")); + algorithm = BT_8723A_2ANT_COEX_ALGO_SCO; + } + else if(pStackInfo->bPanExist) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + PAN(HS)\n")); + algorithm = BT_8723A_2ANT_COEX_ALGO_SCO; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + PAN(EDR)\n")); + algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR_HID; + } + } + } + else + { + if( pStackInfo->bHidExist && + pStackInfo->bA2dpExist ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP\n")); + algorithm = BT_8723A_2ANT_COEX_ALGO_HID_A2DP; + } + else if( pStackInfo->bHidExist && + pStackInfo->bPanExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + PAN(HS)\n")); + algorithm = BT_8723A_2ANT_COEX_ALGO_HID_A2DP; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + PAN(EDR)\n")); + algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR_HID; + } + } + else if( pStackInfo->bPanExist && + pStackInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP + PAN(HS)\n")); + algorithm = BT_8723A_2ANT_COEX_ALGO_A2DP; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP + PAN(EDR)\n")); + algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } + } + else if(numOfDiffProfile == 3) + { + if(pStackInfo->bScoExist) + { + if( pStackInfo->bHidExist && + pStackInfo->bA2dpExist ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + A2DP ==> HID\n")); + algorithm = BT_8723A_2ANT_COEX_ALGO_HID; + } + else if( pStackInfo->bHidExist && + pStackInfo->bPanExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + PAN(HS)\n")); + algorithm = BT_8723A_2ANT_COEX_ALGO_HID_A2DP; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + PAN(EDR)\n")); + algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR_HID; + } + } + else if( pStackInfo->bPanExist && + pStackInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + A2DP + PAN(HS)\n")); + algorithm = BT_8723A_2ANT_COEX_ALGO_SCO; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n")); + algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR_HID; + } + } + } + else + { + if( pStackInfo->bHidExist && + pStackInfo->bPanExist && + pStackInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP + PAN(HS)\n")); + algorithm = BT_8723A_2ANT_COEX_ALGO_HID_A2DP; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP + PAN(EDR)\n")); + algorithm = BT_8723A_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } + else if(numOfDiffProfile >= 3) + { + if(pStackInfo->bScoExist) + { + if( pStackInfo->bHidExist && + pStackInfo->bPanExist && + pStackInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n")); + + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n")); + algorithm = BT_8723A_2ANT_COEX_ALGO_PANEDR_HID; + } + } + } + } + + return algorithm; +} + +BOOLEAN +halbtc8723a2ant_NeedToDecBtPwr( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bRet=FALSE; + BOOLEAN bBtHsOn=FALSE, bWifiConnected=FALSE; + s4Byte btHsRssi=0; + u1Byte btRssiState=BTC_RSSI_STATE_HIGH; + + btRssiState = halbtc8723a2ant_BtRssiState(2, 42, 0); + + if(!pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn)) + return FALSE; + if(!pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected)) + return FALSE; + if(!pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_HS_RSSI, &btHsRssi)) + return FALSE; + if(BTC_RSSI_LOW(btRssiState)) + return FALSE; + + if(bWifiConnected) + { + if(bBtHsOn) + { + if(btHsRssi > 37) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Need to decrease bt power for HS mode!!\n")); + bRet = TRUE; + } + } + else + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Need to decrease bt power for Wifi is connected!!\n")); + bRet = TRUE; + } + } + + return bRet; +} + +VOID +halbtc8723a2ant_SetFwDacSwingLevel( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte dacSwingLvl + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + // There are several type of dacswing + // 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 + H2C_Parameter[0] = dacSwingLvl; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Set Dac Swing Level=0x%x\n", dacSwingLvl)); + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x29=0x%x\n", H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x29, 1, H2C_Parameter); +} + +VOID +halbtc8723a2ant_SetFwDecBtPwr( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bDecBtPwr + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + H2C_Parameter[0] = 0; + + if(bDecBtPwr) + { + H2C_Parameter[0] |= BIT1; + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], decrease Bt Power : %s, FW write 0x21=0x%x\n", + (bDecBtPwr? "Yes!!":"No!!"), H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x21, 1, H2C_Parameter); +} + +VOID +halbtc8723a2ant_DecBtPwr( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bDecBtPwr + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s Dec BT power = %s\n", + (bForceExec? "force to":""), ((bDecBtPwr)? "ON":"OFF"))); + pCoexDm->bCurDecBtPwr = bDecBtPwr; + + if(!bForceExec) + { + if(pCoexDm->bPreDecBtPwr == pCoexDm->bCurDecBtPwr) + return; + } + halbtc8723a2ant_SetFwDecBtPwr(pBtCoexist, pCoexDm->bCurDecBtPwr); + + pCoexDm->bPreDecBtPwr = pCoexDm->bCurDecBtPwr; +} + +VOID +halbtc8723a2ant_FwDacSwingLvl( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte fwDacSwingLvl + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s set FW Dac Swing level = %d\n", + (bForceExec? "force to":""), fwDacSwingLvl)); + pCoexDm->curFwDacSwingLvl = fwDacSwingLvl; + + if(!bForceExec) + { + if(pCoexDm->preFwDacSwingLvl == pCoexDm->curFwDacSwingLvl) + return; + } + + halbtc8723a2ant_SetFwDacSwingLevel(pBtCoexist, pCoexDm->curFwDacSwingLvl); + + pCoexDm->preFwDacSwingLvl = pCoexDm->curFwDacSwingLvl; +} + +VOID +halbtc8723a2ant_SetSwRfRxLpfCorner( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bRxRfShrinkOn + ) +{ + if(bRxRfShrinkOn) + { + //Shrink RF Rx LPF corner + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Shrink RF Rx LPF corner!!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, 0xf0ff7); + } + else + { + //Resume RF Rx LPF corner + // After initialized, we can use pCoexDm->btRf0x1eBackup + if(pBtCoexist->bInitilized) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Resume RF Rx LPF corner!!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, pCoexDm->btRf0x1eBackup); + } + } +} + +VOID +halbtc8723a2ant_RfShrink( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bRxRfShrinkOn + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Rx RF Shrink = %s\n", + (bForceExec? "force to":""), ((bRxRfShrinkOn)? "ON":"OFF"))); + pCoexDm->bCurRfRxLpfShrink = bRxRfShrinkOn; + + if(!bForceExec) + { + if(pCoexDm->bPreRfRxLpfShrink == pCoexDm->bCurRfRxLpfShrink) + return; + } + halbtc8723a2ant_SetSwRfRxLpfCorner(pBtCoexist, pCoexDm->bCurRfRxLpfShrink); + + pCoexDm->bPreRfRxLpfShrink = pCoexDm->bCurRfRxLpfShrink; +} + +VOID +halbtc8723a2ant_SetSwPenaltyTxRateAdaptive( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bLowPenaltyRa + ) +{ + u1Byte tmpU1; + + tmpU1 = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4fd); + tmpU1 |= BIT0; + if(bLowPenaltyRa) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set low penalty!!\n")); + tmpU1 &= ~BIT2; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set normal!!\n")); + tmpU1 |= BIT2; + } + + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x4fd, tmpU1); +} + +VOID +halbtc8723a2ant_LowPenaltyRa( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bLowPenaltyRa + ) +{ + return; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn LowPenaltyRA = %s\n", + (bForceExec? "force to":""), ((bLowPenaltyRa)? "ON":"OFF"))); + pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa; + + if(!bForceExec) + { + if(pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa) + return; + } + halbtc8723a2ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa); + + pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa; +} + +VOID +halbtc8723a2ant_SetSwFullTimeDacSwing( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bSwDacSwingOn, + IN u4Byte swDacSwingLvl + ) +{ + if(bSwDacSwingOn) + { + pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xff000000, swDacSwingLvl); + } + else + { + pBtCoexist->fBtcSetBbReg(pBtCoexist, 0x880, 0xff000000, 0xc0); + } +} + + +VOID +halbtc8723a2ant_DacSwing( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bDacSwingOn, + IN u4Byte dacSwingLvl + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn DacSwing=%s, dacSwingLvl=0x%x\n", + (bForceExec? "force to":""), ((bDacSwingOn)? "ON":"OFF"), dacSwingLvl)); + pCoexDm->bCurDacSwingOn = bDacSwingOn; + pCoexDm->curDacSwingLvl = dacSwingLvl; + + if(!bForceExec) + { + if( (pCoexDm->bPreDacSwingOn == pCoexDm->bCurDacSwingOn) && + (pCoexDm->preDacSwingLvl == pCoexDm->curDacSwingLvl) ) + return; + } + delay_ms(30); + halbtc8723a2ant_SetSwFullTimeDacSwing(pBtCoexist, bDacSwingOn, dacSwingLvl); + + pCoexDm->bPreDacSwingOn = pCoexDm->bCurDacSwingOn; + pCoexDm->preDacSwingLvl = pCoexDm->curDacSwingLvl; +} + +VOID +halbtc8723a2ant_SetAdcBackOff( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bAdcBackOff + ) +{ + if(bAdcBackOff) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level On!\n")); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc04,0x3a07611); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level Off!\n")); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc04,0x3a05611); + } +} + +VOID +halbtc8723a2ant_AdcBackOff( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bAdcBackOff + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn AdcBackOff = %s\n", + (bForceExec? "force to":""), ((bAdcBackOff)? "ON":"OFF"))); + pCoexDm->bCurAdcBackOff = bAdcBackOff; + + if(!bForceExec) + { + if(pCoexDm->bPreAdcBackOff == pCoexDm->bCurAdcBackOff) + return; + } + halbtc8723a2ant_SetAdcBackOff(pBtCoexist, pCoexDm->bCurAdcBackOff); + + pCoexDm->bPreAdcBackOff = pCoexDm->bCurAdcBackOff; +} + +VOID +halbtc8723a2ant_SetAgcTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bAgcTableEn + ) +{ + u1Byte rssiAdjustVal=0; + + if(bAgcTableEn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table On!\n")); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4e1c0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4d1d0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4c1e0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4b1f0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x4a200001); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xdc000); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x90000); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x51000); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x12000); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1a, 0xfffff, 0x00355); + + rssiAdjustVal = 6; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table Off!\n")); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x641c0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x631d0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x621e0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x611f0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78,0x60200001); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x32000); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0x71000); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xb0000); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x12, 0xfffff, 0xfc000); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1a, 0xfffff, 0x30355); + } + + // set rssiAdjustVal for wifi module. + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, &rssiAdjustVal); +} + + +VOID +halbtc8723a2ant_AgcTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bAgcTableEn + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s %s Agc Table\n", + (bForceExec? "force to":""), ((bAgcTableEn)? "Enable":"Disable"))); + pCoexDm->bCurAgcTableEn = bAgcTableEn; + + if(!bForceExec) + { + if(pCoexDm->bPreAgcTableEn == pCoexDm->bCurAgcTableEn) + return; + } + halbtc8723a2ant_SetAgcTable(pBtCoexist, bAgcTableEn); + + pCoexDm->bPreAgcTableEn = pCoexDm->bCurAgcTableEn; +} + +VOID +halbtc8723a2ant_SetCoexTable( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte val0x6c0, + IN u4Byte val0x6c8, + IN u1Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c0=0x%x\n", val0x6c0)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c0, val0x6c0); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, val0x6c8); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc)); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cc, val0x6cc); +} + +VOID +halbtc8723a2ant_CoexTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u4Byte val0x6c0, + IN u4Byte val0x6c8, + IN u1Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s write Coex Table 0x6c0=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n", + (bForceExec? "force to":""), val0x6c0, val0x6c8, val0x6cc)); + pCoexDm->curVal0x6c0 = val0x6c0; + pCoexDm->curVal0x6c8 = val0x6c8; + pCoexDm->curVal0x6cc = val0x6cc; + + if(!bForceExec) + { + if( (pCoexDm->preVal0x6c0 == pCoexDm->curVal0x6c0) && + (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) && + (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) ) + return; + } + halbtc8723a2ant_SetCoexTable(pBtCoexist, val0x6c0, val0x6c8, val0x6cc); + + pCoexDm->preVal0x6c0 = pCoexDm->curVal0x6c0; + pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8; + pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc; +} + +VOID +halbtc8723a2ant_SetFwIgnoreWlanAct( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bEnable + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + if(bEnable) + { + H2C_Parameter[0] |= BIT0; // function enable + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set FW for BT Ignore Wlan_Act, FW write 0x25=0x%x\n", + H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x25, 1, H2C_Parameter); +} + +VOID +halbtc8723a2ant_IgnoreWlanAct( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bEnable + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Ignore WlanAct %s\n", + (bForceExec? "force to":""), (bEnable? "ON":"OFF"))); + pCoexDm->bCurIgnoreWlanAct = bEnable; + + if(!bForceExec) + { + if(pCoexDm->bPreIgnoreWlanAct == pCoexDm->bCurIgnoreWlanAct) + return; + } + halbtc8723a2ant_SetFwIgnoreWlanAct(pBtCoexist, bEnable); + + pCoexDm->bPreIgnoreWlanAct = pCoexDm->bCurIgnoreWlanAct; +} + +VOID +halbtc8723a2ant_SetFwPstdma( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte byte1, + IN u1Byte byte2, + IN u1Byte byte3, + IN u1Byte byte4, + IN u1Byte byte5 + ) +{ + u1Byte H2C_Parameter[5] ={0}; + + H2C_Parameter[0] = byte1; + H2C_Parameter[1] = byte2; + H2C_Parameter[2] = byte3; + H2C_Parameter[3] = byte4; + H2C_Parameter[4] = byte5; + + pCoexDm->psTdmaPara[0] = byte1; + pCoexDm->psTdmaPara[1] = byte2; + pCoexDm->psTdmaPara[2] = byte3; + pCoexDm->psTdmaPara[3] = byte4; + pCoexDm->psTdmaPara[4] = byte5; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x3a(5bytes)=0x%x%08x\n", + H2C_Parameter[0], + H2C_Parameter[1]<<24|H2C_Parameter[2]<<16|H2C_Parameter[3]<<8|H2C_Parameter[4])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x3a, 5, H2C_Parameter); +} + +VOID +halbtc8723a2ant_PsTdma( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bTurnOn, + IN u1Byte type + ) +{ + u4Byte btTxRxCnt=0; + + btTxRxCnt = pCoexSta->highPriorityTx+pCoexSta->highPriorityRx+ + pCoexSta->lowPriorityTx+pCoexSta->lowPriorityRx; + + if(btTxRxCnt > 3000) + { + pCoexDm->bCurPsTdmaOn = TRUE; + pCoexDm->curPsTdma = 8; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], turn ON PS TDMA, type=%d for BT tx/rx counters=%d(>3000)\n", + pCoexDm->curPsTdma, btTxRxCnt)); + } + else + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn %s PS TDMA, type=%d\n", + (bForceExec? "force to":""), (bTurnOn? "ON":"OFF"), type)); + pCoexDm->bCurPsTdmaOn = bTurnOn; + pCoexDm->curPsTdma = type; + } + + if(!bForceExec) + { + if( (pCoexDm->bPrePsTdmaOn == pCoexDm->bCurPsTdmaOn) && + (pCoexDm->prePsTdma == pCoexDm->curPsTdma) ) + return; + } + if(pCoexDm->bCurPsTdmaOn) + { + switch(pCoexDm->curPsTdma) + { + case 1: + default: + halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x98); + break; + case 2: + halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0xe1, 0x98); + break; + case 3: + halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0xa, 0xe1, 0x98); + break; + case 4: + halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xa3, 0x5, 0x5, 0xe1, 0x80); + break; + case 5: + halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x98); + break; + case 6: + halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0x60, 0x98); + break; + case 7: + halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0xa, 0x60, 0x98); + break; + case 8: + halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xa3, 0x5, 0x5, 0x60, 0x80); + break; + case 9: + halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x98); + break; + case 10: + halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0xe1, 0x98); + break; + case 11: + halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0xa, 0xe1, 0x98); + break; + case 12: + halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0xe1, 0x98); + break; + case 13: + halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x98); + break; + case 14: + halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0x60, 0x98); + break; + case 15: + halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0xa, 0x60, 0x98); + break; + case 16: + halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0x60, 0x98); + break; + case 17: + halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xa3, 0x2f, 0x2f, 0x60, 0x80); + break; + case 18: + halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0xe1, 0x98); + break; + case 19: + halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x25, 0xe1, 0x98); + break; + case 20: + halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x25, 0x60, 0x98); + break; + } + } + else + { + // disable PS tdma + switch(pCoexDm->curPsTdma) + { + case 0: + halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x8, 0x0); + break; + case 1: + halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x0, 0x0); + break; + default: + halbtc8723a2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x8, 0x0); + break; + } + } + + // update pre state + pCoexDm->bPrePsTdmaOn = pCoexDm->bCurPsTdmaOn; + pCoexDm->prePsTdma = pCoexDm->curPsTdma; +} + + +VOID +halbtc8723a2ant_CoexAllOff( + IN PBTC_COEXIST pBtCoexist + ) +{ + // fw all off + halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20); + halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + + // sw all off + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + + // hw all off + halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); +} + +VOID +halbtc8723a2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + // force to reset coex mechanism + halbtc8723a2ant_CoexTable(pBtCoexist, FORCE_EXEC, 0x55555555, 0xffff, 0x3); + halbtc8723a2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); + halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, FORCE_EXEC, 0x20); + halbtc8723a2ant_DecBtPwr(pBtCoexist, FORCE_EXEC, FALSE); + halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE); + + halbtc8723a2ant_AgcTable(pBtCoexist, FORCE_EXEC, FALSE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, FORCE_EXEC, FALSE); + halbtc8723a2ant_LowPenaltyRa(pBtCoexist, FORCE_EXEC, FALSE); + halbtc8723a2ant_RfShrink(pBtCoexist, FORCE_EXEC, FALSE); + halbtc8723a2ant_DacSwing(pBtCoexist, FORCE_EXEC, FALSE, 0xc0); +} + +VOID +halbtc8723a2ant_BtInquiryPage( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bLowPwrDisable=TRUE; + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + + halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); + halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); +} + +VOID +halbtc8723a2ant_BtEnableAction( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bWifiConnected=FALSE; + + // Here we need to resend some wifi info to BT + // because bt is reset and loss of the info. + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + if(bWifiConnected) + { + halbtc8723a2ant_IndicateWifiChnlBwInfo(pBtCoexist, BTC_MEDIA_CONNECT); + } + else + { + halbtc8723a2ant_IndicateWifiChnlBwInfo(pBtCoexist, BTC_MEDIA_DISCONNECT); + } + + halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE); +} + +VOID +halbtc8723a2ant_MonitorBtCtr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte regHPTxRx, regLPTxRx, u4Tmp; + u4Byte regHPTx=0, regHPRx=0, regLPTx=0, regLPRx=0; + u1Byte u1Tmp; + + regHPTxRx = 0x770; + regLPTxRx = 0x774; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regHPTxRx); + regHPTx = u4Tmp & bMaskLWord; + regHPRx = (u4Tmp & bMaskHWord)>>16; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regLPTxRx); + regLPTx = u4Tmp & bMaskLWord; + regLPRx = (u4Tmp & bMaskHWord)>>16; + + pCoexSta->highPriorityTx = regHPTx; + pCoexSta->highPriorityRx = regHPRx; + pCoexSta->lowPriorityTx = regLPTx; + pCoexSta->lowPriorityRx = regLPRx; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", + regHPTxRx, regHPTx, regHPTx, regHPRx, regHPRx)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", + regLPTxRx, regLPTx, regLPTx, regLPRx, regLPRx)); + + // reset counter + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0xc); +} + +VOID +halbtc8723a2ant_MonitorBtEnableDisable( + IN PBTC_COEXIST pBtCoexist + ) +{ + static BOOLEAN bPreBtDisabled=FALSE; + static u4Byte btDisableCnt=0; + BOOLEAN bBtActive=TRUE, bBtDisabled=FALSE; + + // This function check if bt is disabled + + if( pCoexSta->highPriorityTx == 0 && + pCoexSta->highPriorityRx == 0 && + pCoexSta->lowPriorityTx == 0 && + pCoexSta->lowPriorityRx == 0) + { + bBtActive = FALSE; + } + if( pCoexSta->highPriorityTx == 0xffff && + pCoexSta->highPriorityRx == 0xffff && + pCoexSta->lowPriorityTx == 0xffff && + pCoexSta->lowPriorityRx == 0xffff) + { + bBtActive = FALSE; + } + if(bBtActive) + { + btDisableCnt = 0; + bBtDisabled = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is enabled !!\n")); + } + else + { + btDisableCnt++; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], bt all counters=0, %d times!!\n", + btDisableCnt)); + if(btDisableCnt >= 2) + { + bBtDisabled = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is disabled !!\n")); + } + } + if(bPreBtDisabled != bBtDisabled) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is from %s to %s!!\n", + (bPreBtDisabled ? "disabled":"enabled"), + (bBtDisabled ? "disabled":"enabled"))); + bPreBtDisabled = bBtDisabled; + if(!bBtDisabled) + { + halbtc8723a2ant_BtEnableAction(pBtCoexist); + } + } +} + +BOOLEAN +halbtc8723a2ant_IsCommonAction( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + BOOLEAN bCommon=FALSE, bWifiConnected=FALSE; + BOOLEAN bLowPwrDisable=FALSE; + + if(!pStackInfo->bBtLinkExist) + { + bLowPwrDisable = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + } + else + { + bLowPwrDisable = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + + if(halbtc8723a2ant_IsWifiIdle(pBtCoexist) && + BT_8723A_2ANT_BT_STATUS_IDLE == pCoexDm->btStatus) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi idle + Bt idle!!\n")); + + halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); + + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20); + halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + + bCommon = TRUE; + } + else if(!halbtc8723a2ant_IsWifiIdle(pBtCoexist) && + (BT_8723A_2ANT_BT_STATUS_IDLE == pCoexDm->btStatus) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non-idle + BT idle!!\n")); + + halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); + + halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20); + halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); + + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + + bCommon = TRUE; + } + else if(halbtc8723a2ant_IsWifiIdle(pBtCoexist) && + (BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi idle + Bt connected idle!!\n")); + + halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); + + halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20); + halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + + bCommon = TRUE; + } + else if(!halbtc8723a2ant_IsWifiIdle(pBtCoexist) && + (BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non-idle + Bt connected idle!!\n")); + + halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); + + halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20); + halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + + bCommon = TRUE; + } + else if(halbtc8723a2ant_IsWifiIdle(pBtCoexist) && + (BT_8723A_2ANT_BT_STATUS_NON_IDLE == pCoexDm->btStatus) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi idle + BT non-idle!!\n")); + + halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); + + halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20); + halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + + bCommon = TRUE; + } + else if(halbtc8723a2ant_IsWifiConnectedIdle(pBtCoexist) && + (BT_8723A_2ANT_BT_STATUS_NON_IDLE == pCoexDm->btStatus) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi connected-idle + BT non-idle!!\n")); + + halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); + + halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20); + halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + + bCommon = TRUE; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non-idle + BT non-idle!!\n")); + halbtc8723a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x20); + + bCommon = FALSE; + } + + return bCommon; +} +VOID +halbtc8723a2ant_TdmaDurationAdjust( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bScoHid, + IN BOOLEAN bTxPause, + IN u1Byte maxInterval + ) +{ + static s4Byte up,dn,m,n,WaitCount; + s4Byte result; //0: no change, +1: increase WiFi duration, -1: decrease WiFi duration + u1Byte retryCount=0; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TdmaDurationAdjust()\n")); + + if(pCoexDm->bResetTdmaAdjust) + { + pCoexDm->bResetTdmaAdjust = FALSE; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], first run TdmaDurationAdjust()!!\n")); + { + if(bScoHid) + { + if(bTxPause) + { + if(maxInterval == 1) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + pCoexDm->psTdmaDuAdjType = 13; + } + else if(maxInterval == 2) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(maxInterval == 3) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + } + else + { + if(maxInterval == 1) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(maxInterval == 2) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(maxInterval == 3) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + } + } + else + { + if(bTxPause) + { + if(maxInterval == 1) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + pCoexDm->psTdmaDuAdjType = 5; + } + else if(maxInterval == 2) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(maxInterval == 3) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + } + else + { + if(maxInterval == 1) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + else if(maxInterval == 2) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(maxInterval == 3) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + } + } + } + //============ + up = 0; + dn = 0; + m = 1; + n= 3; + result = 0; + WaitCount = 0; + } + else + { + //accquire the BT TRx retry count from BT_Info byte2 + retryCount = pCoexSta->btRetryCnt; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], retryCount = %d\n", retryCount)); + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], up=%d, dn=%d, m=%d, n=%d, WaitCount=%d\n", + up, dn, m, n, WaitCount)); + result = 0; + WaitCount++; + + if(retryCount == 0) // no retry in the last 2-second duration + { + up++; + dn--; + + if (dn <= 0) + dn = 0; + + if(up >= n) // if s n 2 retry count0, hռeWiFi duration + { + WaitCount = 0; + n = 3; + up = 0; + dn = 0; + result = 1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Increase wifi duration!!\n")); + } + } + else if (retryCount <= 3) // <=3 retry in the last 2-second duration + { + up--; + dn++; + + if (up <= 0) + up = 0; + + if (dn == 2) // if s 2 2 retry count< 3, hկWiFi duration + { + if (WaitCount <= 2) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter<3!!\n")); + } + } + else //retry count > 3, un1 retry count > 3, hկWiFi duration + { + if (WaitCount == 1) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter>3!!\n")); + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], max Interval = %d\n", maxInterval)); + if(maxInterval == 1) + { + if(bTxPause) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 1\n")); + + if(pCoexDm->curPsTdma == 1) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + pCoexDm->psTdmaDuAdjType = 5; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 4) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + if(pCoexDm->curPsTdma == 9) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + pCoexDm->psTdmaDuAdjType = 13; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + + if(result == -1) + { + if(pCoexDm->curPsTdma == 5) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + else if(pCoexDm->curPsTdma == 13) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 8) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + pCoexDm->psTdmaDuAdjType = 5; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + pCoexDm->psTdmaDuAdjType = 13; + } + } + } + else + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 0\n")); + if(pCoexDm->curPsTdma == 5) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 8) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + if(pCoexDm->curPsTdma == 13) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + + if(result == -1) + { + if(pCoexDm->curPsTdma == 1) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 4) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + } + } + } + else if(maxInterval == 2) + { + if(bTxPause) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 1\n")); + if(pCoexDm->curPsTdma == 1) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 4) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + if(pCoexDm->curPsTdma == 9) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 5) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + else if(pCoexDm->curPsTdma == 13) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 8) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + } + } + else + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 0\n")); + if(pCoexDm->curPsTdma == 5) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 8) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + if(pCoexDm->curPsTdma == 13) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 1) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 4) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + } + } + } + else if(maxInterval == 3) + { + if(bTxPause) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 1\n")); + if(pCoexDm->curPsTdma == 1) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 4) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + if(pCoexDm->curPsTdma == 9) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 5) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + else if(pCoexDm->curPsTdma == 13) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 8) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + } + } + else + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 0\n")); + if(pCoexDm->curPsTdma == 5) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 8) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + if(pCoexDm->curPsTdma == 13) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 1) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 4) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + } + } + } + } + + // if current PsTdma not match with the recorded one (when scan, dhcp...), + // then we have to adjust it back to the previous record one. + if(pCoexDm->curPsTdma != pCoexDm->psTdmaDuAdjType) + { + BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PsTdma type dismatch!!!, curPsTdma=%d, recordPsTdma=%d\n", + pCoexDm->curPsTdma, pCoexDm->psTdmaDuAdjType)); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + + if( !bScan && !bLink && !bRoam) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, pCoexDm->psTdmaDuAdjType); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n")); + } + } +} + +// SCO only or SCO+PAN(HS) +VOID +halbtc8723a2ant_ActionSco( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1; + u4Byte wifiBw; + + if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist)) + halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); + else + halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0); + // fw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + } + else + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + } + + // sw mechanism + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + } + else + { + wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0); + wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0); + + // fw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + } + else + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + } + + // sw mechanism + if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) || + (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + } + else + { + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + } + } +} + + +VOID +halbtc8723a2ant_ActionHid( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1; + u4Byte wifiBw; + + if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist)) + halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); + else + halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0); + // fw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + } + else + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + } + + // sw mechanism + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + } + else + { + wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0); + wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0); + + // fw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + } + else + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + } + + // sw mechanism + if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) || + (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + } + else + { + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + } + } +} + +//A2DP only / PAN(EDR) only/ A2DP+PAN(HS) +VOID +halbtc8723a2ant_ActionA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btInfoExt; + u4Byte wifiBw; + + btInfoExt = pCoexSta->btInfoExt; + + if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist)) + halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); + else + halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0); + + // fw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + if(btInfoExt&BIT0) //a2dp rate, 1:basic /0:edr + { + halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 3); + } + else + { + halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 1); + } + } + else + { + if(btInfoExt&BIT0) //a2dp rate, 1:basic /0:edr + { + halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 3); + } + else + { + halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 1); + } + } + + // sw mechanism + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + } + else + { + wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0); + wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0); + + // fw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + if(btInfoExt&BIT0) //a2dp rate, 1:basic /0:edr + { + halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 3); + } + else + { + halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 1); + } + } + else + { + if(btInfoExt&BIT0) //a2dp rate, 1:basic /0:edr + { + halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 3); + } + else + { + halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 1); + } + } + + // sw mechanism + if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) || + (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + } + else + { + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + } + } +} + +VOID +halbtc8723a2ant_ActionPanEdr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btInfoExt; + u4Byte wifiBw; + + btInfoExt = pCoexSta->btInfoExt; + + if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist)) + halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); + else + halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0); + + // fw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + } + else + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + } + + // sw mechanism + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + } + else + { + wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0); + wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0); + + // fw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + } + else + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + } + + // sw mechanism + if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) || + (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + } + else + { + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + } + } +} + + +//PAN(HS) only +VOID +halbtc8723a2ant_ActionPanHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState; + u4Byte wifiBw; + + halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0); + + // fw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); + } + else + { + halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + } + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + + // sw mechanism + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + } + else + { + wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0); + + // fw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + } + else + { + halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + } + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + } + else + { + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + } + } +} + +//PAN(EDR)+A2DP +VOID +halbtc8723a2ant_ActionPanEdrA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btInfoExt; + u4Byte wifiBw; + + btInfoExt = pCoexSta->btInfoExt; + + if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist)) + halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); + else + halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0); + + // fw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + if(btInfoExt&BIT0) //a2dp basic rate + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + } + else //a2dp edr rate + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + } + } + else + { + if(btInfoExt&BIT0) //a2dp basic rate + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + } + else //a2dp edr rate + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + } + } + + // sw mechanism + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + } + else + { + wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0); + wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 47, 0); + + // fw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + if(btInfoExt&BIT0) //a2dp basic rate + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + } + else //a2dp edr rate + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + } + } + else + { + if(btInfoExt&BIT0) //a2dp basic rate + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + } + else //a2dp edr rate + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + } + } + + // sw mechanism + if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) || + (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + } + else + { + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + } + } +} + +VOID +halbtc8723a2ant_ActionPanEdrHid( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1; + u4Byte wifiBw; + + if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist)) + halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); + else + halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0); + + // fw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + } + else + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + } + + // sw mechanism + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + } + else + { + wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0); + wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0); + + // fw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + } + else + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + } + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + } + else + { + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + } + } +} + +// HID+A2DP+PAN(EDR) +VOID +halbtc8723a2ant_ActionHidA2dpPanEdr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btInfoExt; + u4Byte wifiBw; + + btInfoExt = pCoexSta->btInfoExt; + + if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist)) + halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); + else + halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0); + + // fw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + if(btInfoExt&BIT0) //a2dp basic rate + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + } + else //a2dp edr rate + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + } + } + else + { + if(btInfoExt&BIT0) //a2dp basic rate + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + } + else //a2dp edr rate + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + } + } + + // sw mechanism + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + } + else + { + wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0); + wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0); + + // fw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + if(btInfoExt&BIT0) //a2dp basic rate + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + } + else //a2dp edr rate + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + } + } + else + { + if(btInfoExt&BIT0) //a2dp basic rate + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + } + else //a2dp edr rate + { + halbtc8723a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + } + } + + // sw mechanism + if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) || + (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + } + else + { + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + } + } +} + +VOID +halbtc8723a2ant_ActionHidA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btInfoExt; + u4Byte wifiBw; + + btInfoExt = pCoexSta->btInfoExt; + + if(halbtc8723a2ant_NeedToDecBtPwr(pBtCoexist)) + halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); + else + halbtc8723a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0xffff, 0x3); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 37, 0); + + // fw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + if(btInfoExt&BIT0) //a2dp basic rate + { + halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 3); + } + else //a2dp edr rate + { + halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 1); + } + } + else + { + if(btInfoExt&BIT0) //a2dp basic rate + { + halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 3); + } + else //a2dp edr rate + { + halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 1); + } + } + + // sw mechanism + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + } + else + { + wifiRssiState = halbtc8723a2ant_WifiRssiState(pBtCoexist, 0, 2, 27, 0); + wifiRssiState1 = halbtc8723a2ant_WifiRssiState(pBtCoexist, 1, 2, 47, 0); + + // fw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + if(btInfoExt&BIT0) //a2dp basic rate + { + halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 3); + } + else //a2dp edr rate + { + halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 1); + } + } + else + { + if(btInfoExt&BIT0) //a2dp basic rate + { + halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 3); + } + else //a2dp edr rate + { + halbtc8723a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 1); + } + } + + // sw mechanism + if( (wifiRssiState1 == BTC_RSSI_STATE_HIGH) || + (wifiRssiState1 == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, TRUE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + } + else + { + halbtc8723a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, FALSE); + halbtc8723a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, FALSE, 0xc0); + } + } +} + +VOID +halbtc8723a2ant_RunCoexistMechanism( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + u1Byte btInfoOriginal=0, btRetryCnt=0; + u1Byte algorithm=0; + + if(pBtCoexist->bManualControl) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Manual control!!!\n")); + return; + } + + if(pStackInfo->bProfileNotified) + { + if(pCoexSta->bHoldForStackOperation) + { + // if bt inquiry/page/pair, do not execute. + return; + } + + algorithm = halbtc8723a2ant_ActionAlgorithm(pBtCoexist); + if(pCoexSta->bHoldPeriodCnt && (BT_8723A_2ANT_COEX_ALGO_PANHS!=algorithm)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex],Hold BT inquiry/page scan setting (cnt = %d)!!\n", + pCoexSta->bHoldPeriodCnt)); + if(pCoexSta->bHoldPeriodCnt >= 6) + { + pCoexSta->bHoldPeriodCnt = 0; + // next time the coexist parameters should be reset again. + } + else + pCoexSta->bHoldPeriodCnt++; + return; + } + + pCoexDm->curAlgorithm = algorithm; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Algorithm = %d \n", pCoexDm->curAlgorithm)); + if(halbtc8723a2ant_IsCommonAction(pBtCoexist)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant common.\n")); + pCoexDm->bResetTdmaAdjust = TRUE; + } + else + { + if(pCoexDm->curAlgorithm != pCoexDm->preAlgorithm) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], preAlgorithm=%d, curAlgorithm=%d\n", + pCoexDm->preAlgorithm, pCoexDm->curAlgorithm)); + pCoexDm->bResetTdmaAdjust = TRUE; + } + switch(pCoexDm->curAlgorithm) + { + case BT_8723A_2ANT_COEX_ALGO_SCO: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = SCO.\n")); + halbtc8723a2ant_ActionSco(pBtCoexist); + break; + case BT_8723A_2ANT_COEX_ALGO_HID: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID.\n")); + halbtc8723a2ant_ActionHid(pBtCoexist); + break; + case BT_8723A_2ANT_COEX_ALGO_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = A2DP.\n")); + halbtc8723a2ant_ActionA2dp(pBtCoexist); + break; + case BT_8723A_2ANT_COEX_ALGO_PANEDR: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n")); + halbtc8723a2ant_ActionPanEdr(pBtCoexist); + break; + case BT_8723A_2ANT_COEX_ALGO_PANHS: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HS mode.\n")); + halbtc8723a2ant_ActionPanHs(pBtCoexist); + break; + case BT_8723A_2ANT_COEX_ALGO_PANEDR_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n")); + halbtc8723a2ant_ActionPanEdrA2dp(pBtCoexist); + break; + case BT_8723A_2ANT_COEX_ALGO_PANEDR_HID: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n")); + halbtc8723a2ant_ActionPanEdrHid(pBtCoexist); + break; + case BT_8723A_2ANT_COEX_ALGO_HID_A2DP_PANEDR: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n")); + halbtc8723a2ant_ActionHidA2dpPanEdr(pBtCoexist); + break; + case BT_8723A_2ANT_COEX_ALGO_HID_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n")); + halbtc8723a2ant_ActionHidA2dp(pBtCoexist); + break; + default: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n")); + halbtc8723a2ant_CoexAllOff(pBtCoexist); + break; + } + pCoexDm->preAlgorithm = pCoexDm->curAlgorithm; + } + } +} + +//============================================================ +// work around function start with wa_halbtc8723a2ant_ +//============================================================ +VOID +wa_halbtc8723a2ant_MonitorC2h( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte tmp1b=0x0; + u4Byte curC2hTotalCnt=0x0; + static u4Byte preC2hTotalCnt=0x0, sameCntPollingTime=0x0; + + curC2hTotalCnt+=pCoexSta->btInfoC2hCnt[BT_INFO_SRC_8723A_2ANT_BT_RSP]; + + if(curC2hTotalCnt == preC2hTotalCnt) + { + sameCntPollingTime++; + } + else + { + preC2hTotalCnt = curC2hTotalCnt; + sameCntPollingTime = 0; + } + + if(sameCntPollingTime >= 2) + { + tmp1b = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x1af); + if(tmp1b != 0x0) + { + pCoexSta->c2hHangDetectCnt++; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x1af, 0x0); + } + } +} + +//============================================================ +// extern function start with EXhalbtc8723a2ant_ +//============================================================ +VOID +EXhalbtc8723a2ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ) +{ +} + +VOID +EXhalbtc8723a2ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ) +{ + u4Byte u4Tmp=0; + u1Byte u1Tmp=0; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 2Ant Init HW Config!!\n")); + + // backup rf 0x1e value + pCoexDm->btRf0x1eBackup = + pBtCoexist->fBtcGetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff); + + // Enable counter statistics + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0x4); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x778, 0x3); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x20); +} + +VOID +EXhalbtc8723a2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Coex Mechanism Init!!\n")); + + halbtc8723a2ant_InitCoexDm(pBtCoexist); +} + +VOID +EXhalbtc8723a2ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + pu1Byte cliBuf=pBtCoexist->cliBuf; + u1Byte u1Tmp[4], i, btInfoExt, psTdmaCase=0; + u4Byte u4Tmp[4]; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:", \ + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum); + CL_PRINTF(cliBuf); + + if(pBtCoexist->bManualControl) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "[Action Manual control]!!"); + CL_PRINTF(cliBuf); + } + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \ + ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", "Wifi channel informed to BT", \ + pCoexDm->wifiChnlInfo[0], pCoexDm->wifiChnlInfo[1], + pCoexDm->wifiChnlInfo[2]); + CL_PRINTF(cliBuf); + + // wifi status + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Wifi Status]============"); + CL_PRINTF(cliBuf); + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[BT Status]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", "BT [status/ rssi/ retryCnt]", \ + ((pCoexSta->bC2hBtInquiryPage)?("inquiry/page scan"):((BT_8723A_2ANT_BT_STATUS_IDLE == pCoexDm->btStatus)? "idle":( (BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus)? "connected-idle":"busy"))), + pCoexSta->btRssi, pCoexSta->btRetryCnt); + CL_PRINTF(cliBuf); + + if(pStackInfo->bProfileNotified) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP", \ + pStackInfo->bScoExist, pStackInfo->bHidExist, pStackInfo->bPanExist, pStackInfo->bA2dpExist); + CL_PRINTF(cliBuf); + + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO); + } + + btInfoExt = pCoexSta->btInfoExt; + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Info A2DP rate", \ + (btInfoExt&BIT0)? "Basic rate":"EDR rate"); + CL_PRINTF(cliBuf); + + for(i=0; ibtInfoC2hCnt[i]) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", GLBtInfoSrc8723a2Ant[i], \ + pCoexSta->btInfoC2h[i][0], pCoexSta->btInfoC2h[i][1], + pCoexSta->btInfoC2h[i][2], pCoexSta->btInfoC2h[i][3], + pCoexSta->btInfoC2h[i][4], pCoexSta->btInfoC2h[i][5], + pCoexSta->btInfoC2h[i][6], pCoexSta->btInfoC2hCnt[i]); + CL_PRINTF(cliBuf); + } + } + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "write 0x1af=0x0 num", \ + pCoexSta->c2hHangDetectCnt); + CL_PRINTF(cliBuf); + + // Sw mechanism + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============"); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", "SM1[ShRf/ LpRA/ LimDig]", \ + pCoexDm->bCurRfRxLpfShrink, pCoexDm->bCurLowPenaltyRa, pCoexDm->bLimitedDig); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", \ + pCoexDm->bCurAgcTableEn, pCoexDm->bCurAdcBackOff, pCoexDm->bCurDacSwingOn, pCoexDm->curDacSwingLvl); + CL_PRINTF(cliBuf); + + // Fw mechanism + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============"); + CL_PRINTF(cliBuf); + + if(!pBtCoexist->bManualControl) + { + psTdmaCase = pCoexDm->curPsTdma; + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x case-%d", "PS TDMA", \ + pCoexDm->psTdmaPara[0], pCoexDm->psTdmaPara[1], + pCoexDm->psTdmaPara[2], pCoexDm->psTdmaPara[3], + pCoexDm->psTdmaPara[4], psTdmaCase); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "DecBtPwr/ IgnWlanAct", \ + pCoexDm->bCurDecBtPwr, pCoexDm->bCurIgnoreWlanAct); + CL_PRINTF(cliBuf); + } + + // Hw setting + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "RF-A, 0x1e initVal", \ + pCoexDm->btRf0x1eBackup); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x778); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x783); + u1Tmp[2] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x796); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x778/ 0x783/ 0x796", \ + u1Tmp[0], u1Tmp[1], u1Tmp[2]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x880); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x880", \ + u4Tmp[0]); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x40); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x40", \ + u1Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x550); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x522); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x550(bcn ctrl)/0x522", \ + u4Tmp[0], u1Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x484); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x484(rate adaptive)", \ + u4Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc50); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", \ + u4Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda0); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda4); + u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda8); + u4Tmp[3] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xdac); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0xda0/0xda4/0xda8/0xdac(FA cnt)", \ + u4Tmp[0], u4Tmp[1], u4Tmp[2], u4Tmp[3]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c0); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c4); + u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c8); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x6cc); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", \ + u4Tmp[0], u4Tmp[1], u4Tmp[2], u1Tmp[0]); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x770 (hp rx[31:16]/tx[15:0])", \ + pCoexSta->highPriorityRx, pCoexSta->highPriorityTx); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x774(lp rx[31:16]/tx[15:0])", \ + pCoexSta->lowPriorityRx, pCoexSta->lowPriorityTx); + CL_PRINTF(cliBuf); + + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + + +VOID +EXhalbtc8723a2ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_IPS_ENTER == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS ENTER notify\n")); + halbtc8723a2ant_CoexAllOff(pBtCoexist); + } + else if(BTC_IPS_LEAVE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS LEAVE notify\n")); + //halbtc8723a2ant_InitCoexDm(pBtCoexist); + } +} + +VOID +EXhalbtc8723a2ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_LPS_ENABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS ENABLE notify\n")); + } + else if(BTC_LPS_DISABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS DISABLE notify\n")); + } +} + +VOID +EXhalbtc8723a2ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_SCAN_START == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n")); + } + else if(BTC_SCAN_FINISH == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n")); + } +} + +VOID +EXhalbtc8723a2ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_ASSOCIATE_START == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n")); + } + else if(BTC_ASSOCIATE_FINISH == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n")); + } +} + +VOID +EXhalbtc8723a2ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_MEDIA_CONNECT == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA connect notify\n")); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA disconnect notify\n")); + } + + halbtc8723a2ant_IndicateWifiChnlBwInfo(pBtCoexist, type); +} + +VOID +EXhalbtc8723a2ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(type == BTC_PACKET_DHCP) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], DHCP Packet notify\n")); + } +} + +VOID +EXhalbtc8723a2ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ) +{ + u1Byte btInfo=0; + u1Byte i, rspSource=0; + BOOLEAN bBtBusy=FALSE, bLimitedDig=FALSE; + BOOLEAN bWifiConnected=FALSE, bBtHsOn=FALSE; + + pCoexSta->bC2hBtInfoReqSent = FALSE; + + rspSource = BT_INFO_SRC_8723A_2ANT_BT_RSP; + pCoexSta->btInfoC2hCnt[rspSource]++; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Bt info[%d], length=%d, hex data=[", rspSource, length)); + for(i=0; ibtInfoC2h[rspSource][i] = tmpBuf[i]; + if(i == 0) + btInfo = tmpBuf[i]; + if(i == length-1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x]\n", tmpBuf[i])); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x, ", tmpBuf[i])); + } + } + + if(BT_INFO_SRC_8723A_2ANT_WIFI_FW != rspSource) + { + pCoexSta->btRetryCnt = + pCoexSta->btInfoC2h[rspSource][1]; + + pCoexSta->btRssi = + pCoexSta->btInfoC2h[rspSource][2]*2+10; + + pCoexSta->btInfoExt = + pCoexSta->btInfoC2h[rspSource][3]; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + // check BIT2 first ==> check if bt is under inquiry or page scan + if(btInfo & BT_INFO_8723A_2ANT_B_INQ_PAGE) + { + pCoexSta->bC2hBtInquiryPage = TRUE; + } + else + { + pCoexSta->bC2hBtInquiryPage = FALSE; + } +} + +VOID +EXhalbtc8723a2ant_StackOperationNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_STACK_OP_INQ_PAGE_PAIR_START == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], StackOP Inquiry/page/pair start notify\n")); + pCoexSta->bHoldForStackOperation = TRUE; + pCoexSta->bHoldPeriodCnt = 1; + halbtc8723a2ant_BtInquiryPage(pBtCoexist); + } + else if(BTC_STACK_OP_INQ_PAGE_PAIR_FINISH == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], StackOP Inquiry/page/pair finish notify\n")); + pCoexSta->bHoldForStackOperation = FALSE; + } +} + +VOID +EXhalbtc8723a2ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Halt notify\n")); + + halbtc8723a2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE); + EXhalbtc8723a2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); +} + +VOID +EXhalbtc8723a2ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 2Ant Periodical!!\n")); + + // work around for c2h hang + wa_halbtc8723a2ant_MonitorC2h(pBtCoexist); + + halbtc8723a2ant_QueryBtInfo(pBtCoexist); + halbtc8723a2ant_MonitorBtCtr(pBtCoexist); + halbtc8723a2ant_MonitorBtEnableDisable(pBtCoexist); + + halbtc8723a2ant_RunCoexistMechanism(pBtCoexist); +} + + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723a2Ant.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723a2Ant.h new file mode 100644 index 000000000..2ce475c1d --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723a2Ant.h @@ -0,0 +1,185 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//=========================================== +// The following is for 8723A 2Ant BT Co-exist definition +//=========================================== +#define BT_INFO_8723A_2ANT_B_FTP BIT7 +#define BT_INFO_8723A_2ANT_B_A2DP BIT6 +#define BT_INFO_8723A_2ANT_B_HID BIT5 +#define BT_INFO_8723A_2ANT_B_SCO_BUSY BIT4 +#define BT_INFO_8723A_2ANT_B_ACL_BUSY BIT3 +#define BT_INFO_8723A_2ANT_B_INQ_PAGE BIT2 +#define BT_INFO_8723A_2ANT_B_SCO_ESCO BIT1 +#define BT_INFO_8723A_2ANT_B_CONNECTION BIT0 + +#define BTC_RSSI_COEX_THRESH_TOL_8723A_2ANT 2 + +typedef enum _BT_INFO_SRC_8723A_2ANT{ + BT_INFO_SRC_8723A_2ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8723A_2ANT_BT_RSP = 0x1, + BT_INFO_SRC_8723A_2ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8723A_2ANT_MAX +}BT_INFO_SRC_8723A_2ANT,*PBT_INFO_SRC_8723A_2ANT; + +typedef enum _BT_8723A_2ANT_BT_STATUS{ + BT_8723A_2ANT_BT_STATUS_IDLE = 0x0, + BT_8723A_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8723A_2ANT_BT_STATUS_NON_IDLE = 0x2, + BT_8723A_2ANT_BT_STATUS_MAX +}BT_8723A_2ANT_BT_STATUS,*PBT_8723A_2ANT_BT_STATUS; + +typedef enum _BT_8723A_2ANT_COEX_ALGO{ + BT_8723A_2ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8723A_2ANT_COEX_ALGO_SCO = 0x1, + BT_8723A_2ANT_COEX_ALGO_HID = 0x2, + BT_8723A_2ANT_COEX_ALGO_A2DP = 0x3, + BT_8723A_2ANT_COEX_ALGO_PANEDR = 0x4, + BT_8723A_2ANT_COEX_ALGO_PANHS = 0x5, + BT_8723A_2ANT_COEX_ALGO_PANEDR_A2DP = 0x6, + BT_8723A_2ANT_COEX_ALGO_PANEDR_HID = 0x7, + BT_8723A_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x8, + BT_8723A_2ANT_COEX_ALGO_HID_A2DP = 0x9, + BT_8723A_2ANT_COEX_ALGO_MAX +}BT_8723A_2ANT_COEX_ALGO,*PBT_8723A_2ANT_COEX_ALGO; + +typedef struct _COEX_DM_8723A_2ANT{ + // fw mechanism + BOOLEAN bPreDecBtPwr; + BOOLEAN bCurDecBtPwr; + //BOOLEAN bPreBtLnaConstrain; + //BOOLEAN bCurBtLnaConstrain; + //u1Byte bPreBtPsdMode; + //u1Byte bCurBtPsdMode; + u1Byte preFwDacSwingLvl; + u1Byte curFwDacSwingLvl; + BOOLEAN bCurIgnoreWlanAct; + BOOLEAN bPreIgnoreWlanAct; + u1Byte prePsTdma; + u1Byte curPsTdma; + u1Byte psTdmaPara[5]; + u1Byte psTdmaDuAdjType; + BOOLEAN bResetTdmaAdjust; + BOOLEAN bPrePsTdmaOn; + BOOLEAN bCurPsTdmaOn; + //BOOLEAN bPreBtAutoReport; + //BOOLEAN bCurBtAutoReport; + + // sw mechanism + BOOLEAN bPreRfRxLpfShrink; + BOOLEAN bCurRfRxLpfShrink; + u4Byte btRf0x1eBackup; + BOOLEAN bPreLowPenaltyRa; + BOOLEAN bCurLowPenaltyRa; + BOOLEAN bPreDacSwingOn; + u4Byte preDacSwingLvl; + BOOLEAN bCurDacSwingOn; + u4Byte curDacSwingLvl; + BOOLEAN bPreAdcBackOff; + BOOLEAN bCurAdcBackOff; + BOOLEAN bPreAgcTableEn; + BOOLEAN bCurAgcTableEn; + u4Byte preVal0x6c0; + u4Byte curVal0x6c0; + u4Byte preVal0x6c8; + u4Byte curVal0x6c8; + u1Byte preVal0x6cc; + u1Byte curVal0x6cc; + BOOLEAN bLimitedDig; + + // algorithm related + u1Byte preAlgorithm; + u1Byte curAlgorithm; + u1Byte btStatus; + u1Byte wifiChnlInfo[3]; +} COEX_DM_8723A_2ANT, *PCOEX_DM_8723A_2ANT; + +typedef struct _COEX_STA_8723A_2ANT{ + u4Byte highPriorityTx; + u4Byte highPriorityRx; + u4Byte lowPriorityTx; + u4Byte lowPriorityRx; + u1Byte btRssi; + u1Byte preBtRssiState; + u1Byte preBtRssiState1; + u1Byte preWifiRssiState[4]; + BOOLEAN bC2hBtInfoReqSent; + u1Byte btInfoC2h[BT_INFO_SRC_8723A_2ANT_MAX][10]; + u4Byte btInfoC2hCnt[BT_INFO_SRC_8723A_2ANT_MAX]; + BOOLEAN bC2hBtInquiryPage; + u1Byte btRetryCnt; + u1Byte btInfoExt; + BOOLEAN bHoldForStackOperation; + u1Byte bHoldPeriodCnt; + // this is for c2h hang work-around + u4Byte c2hHangDetectCnt; +}COEX_STA_8723A_2ANT, *PCOEX_STA_8723A_2ANT; + +//=========================================== +// The following is interface which will notify coex module. +//=========================================== +VOID +EXhalbtc8723a2ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8723a2ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ); +VOID +EXhalbtc8723a2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8723a2ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8723a2ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8723a2ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8723a2ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8723a2ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8723a2ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8723a2ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8723a2ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8723a2ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ); +VOID +EXhalbtc8723a2ant_StackOperationNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8723a2ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ); + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723b1Ant.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723b1Ant.c new file mode 100644 index 000000000..a2768e249 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723b1Ant.c @@ -0,0 +1,5639 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//============================================================ +// Description: +// +// This file is for RTL8723B Co-exist mechanism +// +// History +// 2012/11/15 Cosa first check in. +// +//============================================================ + +//============================================================ +// include files +//============================================================ +#include "Mp_Precomp.h" + +#if WPP_SOFTWARE_TRACE +#include "HalBtc8723b1Ant.tmh" +#endif + +//#include +#if(BT_30_SUPPORT == 1) +//============================================================ +// Global variables, these are static variables +//============================================================ +static COEX_DM_8723B_1ANT GLCoexDm8723b1Ant; +static PCOEX_DM_8723B_1ANT pCoexDm=&GLCoexDm8723b1Ant; +static COEX_STA_8723B_1ANT GLCoexSta8723b1Ant; +static PCOEX_STA_8723B_1ANT pCoexSta=&GLCoexSta8723b1Ant; +static PSDSCAN_STA_8723B_1ANT GLPsdScan8723b1Ant; +static PPSDSCAN_STA_8723B_1ANT pPsdScan = &GLPsdScan8723b1Ant; + + +const char *const GLBtInfoSrc8723b1Ant[]={ + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; + +u4Byte GLCoexVerDate8723b1Ant=20150119; +u4Byte GLCoexVer8723b1Ant=0x58; + +//============================================================ +// local function proto type if needed +//============================================================ +//============================================================ +// local function start with halbtc8723b1ant_ +//============================================================ +u1Byte +halbtc8723b1ant_BtRssiState( + u1Byte levelNum, + u1Byte rssiThresh, + u1Byte rssiThresh1 + ) +{ + s4Byte btRssi=0; + u1Byte btRssiState=pCoexSta->preBtRssiState; + + btRssi = pCoexSta->btRssi; + + if(levelNum == 2) + { + if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW)) + { + if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8723B_1ANT)) + { + btRssiState = BTC_RSSI_STATE_HIGH; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else + { + if(btRssi < rssiThresh) + { + btRssiState = BTC_RSSI_STATE_LOW; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + else if(levelNum == 3) + { + if(rssiThresh > rssiThresh1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Rssi thresh error!!\n")); + return pCoexSta->preBtRssiState; + } + + if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW)) + { + if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8723B_1ANT)) + { + btRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_MEDIUM) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_MEDIUM)) + { + if(btRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8723B_1ANT)) + { + btRssiState = BTC_RSSI_STATE_HIGH; + } + else if(btRssi < rssiThresh) + { + btRssiState = BTC_RSSI_STATE_LOW; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_MEDIUM; + } + } + else + { + if(btRssi < rssiThresh1) + { + btRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + + pCoexSta->preBtRssiState = btRssiState; + + return btRssiState; +} + +u1Byte +halbtc8723b1ant_WifiRssiState( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte index, + IN u1Byte levelNum, + IN u1Byte rssiThresh, + IN u1Byte rssiThresh1 + ) +{ + s4Byte wifiRssi=0; + u1Byte wifiRssiState=pCoexSta->preWifiRssiState[index]; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); + + if(levelNum == 2) + { + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8723B_1ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else + { + if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + else if(levelNum == 3) + { + if(rssiThresh > rssiThresh1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi RSSI thresh error!!\n")); + return pCoexSta->preWifiRssiState[index]; + } + + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8723B_1ANT)) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_MEDIUM) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_MEDIUM)) + { + if(wifiRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8723B_1ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_MEDIUM; + } + } + else + { + if(wifiRssi < rssiThresh1) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + + pCoexSta->preWifiRssiState[index] = wifiRssiState; + + return wifiRssiState; +} + +VOID +halbtc8723b1ant_UpdateRaMask( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u4Byte disRateMask + ) +{ + pCoexDm->curRaMask = disRateMask; + + if( bForceExec || (pCoexDm->preRaMask != pCoexDm->curRaMask)) + { + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_UPDATE_RAMASK, &pCoexDm->curRaMask); + } + pCoexDm->preRaMask = pCoexDm->curRaMask; +} + +VOID +halbtc8723b1ant_AutoRateFallbackRetry( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + BOOLEAN bWifiUnderBMode=FALSE; + + pCoexDm->curArfrType = type; + + if( bForceExec || (pCoexDm->preArfrType != pCoexDm->curArfrType)) + { + switch(pCoexDm->curArfrType) + { + case 0: // normal mode + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x430, pCoexDm->backupArfrCnt1); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x434, pCoexDm->backupArfrCnt2); + break; + case 1: + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, &bWifiUnderBMode); + if(bWifiUnderBMode) + { + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x430, 0x0); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x434, 0x01010101); + } + else + { + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x430, 0x0); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x434, 0x04030201); + } + break; + default: + break; + } + } + + pCoexDm->preArfrType = pCoexDm->curArfrType; +} + +VOID +halbtc8723b1ant_RetryLimit( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + pCoexDm->curRetryLimitType = type; + + if( bForceExec || (pCoexDm->preRetryLimitType != pCoexDm->curRetryLimitType)) + { + switch(pCoexDm->curRetryLimitType) + { + case 0: // normal mode + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x42a, pCoexDm->backupRetryLimit); + break; + case 1: // retry limit=8 + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x42a, 0x0808); + break; + default: + break; + } + } + + pCoexDm->preRetryLimitType = pCoexDm->curRetryLimitType; +} + +VOID +halbtc8723b1ant_AmpduMaxTime( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + pCoexDm->curAmpduTimeType = type; + + if( bForceExec || (pCoexDm->preAmpduTimeType != pCoexDm->curAmpduTimeType)) + { + switch(pCoexDm->curAmpduTimeType) + { + case 0: // normal mode + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x456, pCoexDm->backupAmpduMaxTime); + break; + case 1: // AMPDU timw = 0x38 * 32us + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x456, 0x38); + break; + default: + break; + } + } + + pCoexDm->preAmpduTimeType = pCoexDm->curAmpduTimeType; +} + +VOID +halbtc8723b1ant_LimitedTx( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte raMaskType, + IN u1Byte arfrType, + IN u1Byte retryLimitType, + IN u1Byte ampduTimeType + ) +{ + switch(raMaskType) + { + case 0: // normal mode + halbtc8723b1ant_UpdateRaMask(pBtCoexist, bForceExec, 0x0); + break; + case 1: // disable cck 1/2 + halbtc8723b1ant_UpdateRaMask(pBtCoexist, bForceExec, 0x00000003); + break; + case 2: // disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 + halbtc8723b1ant_UpdateRaMask(pBtCoexist, bForceExec, 0x0001f1f7); + break; + default: + break; + } + + halbtc8723b1ant_AutoRateFallbackRetry(pBtCoexist, bForceExec, arfrType); + halbtc8723b1ant_RetryLimit(pBtCoexist, bForceExec, retryLimitType); + halbtc8723b1ant_AmpduMaxTime(pBtCoexist, bForceExec, ampduTimeType); +} + +VOID +halbtc8723b1ant_LimitedRx( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bRejApAggPkt, + IN BOOLEAN bBtCtrlAggBufSize, + IN u1Byte aggBufSize + ) +{ + BOOLEAN bRejectRxAgg=bRejApAggPkt; + BOOLEAN bBtCtrlRxAggSize=bBtCtrlAggBufSize; + u1Byte rxAggSize=aggBufSize; + + //============================================ + // Rx Aggregation related setting + //============================================ + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, &bRejectRxAgg); + // decide BT control aggregation buf size or not + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, &bBtCtrlRxAggSize); + // aggregation buf size, only work when BT control Rx aggregation size. + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_AGG_BUF_SIZE, &rxAggSize); + // real update aggregation setting + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); + + +} + +VOID +halbtc8723b1ant_QueryBtInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + pCoexSta->bC2hBtInfoReqSent = TRUE; + + H2C_Parameter[0] |= BIT0; // trigger + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Query Bt Info, FW write 0x61=0x%x\n", + H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x61, 1, H2C_Parameter); +} + +VOID +halbtc8723b1ant_MonitorBtCtr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte regHPTxRx, regLPTxRx, u4Tmp, u4Tmp1; + u4Byte regHPTx=0, regHPRx=0, regLPTx=0, regLPRx=0; + u1Byte u1Tmp, u1Tmp1; + s4Byte wifiRssi; + static u4Byte NumOfBtCounterChk = 0; + + //to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS + //if (! (pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x76e) & 0x8) ) + + if (pCoexSta->bUnderIps) + { + //pCoexSta->highPriorityTx = 65535; + //pCoexSta->highPriorityRx = 65535; + //pCoexSta->lowPriorityTx = 65535; + //pCoexSta->lowPriorityRx = 65535; + //return; + } + + regHPTxRx = 0x770; + regLPTxRx = 0x774; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regHPTxRx); + regHPTx = u4Tmp & bMaskLWord; + regHPRx = (u4Tmp & bMaskHWord)>>16; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regLPTxRx); + regLPTx = u4Tmp & bMaskLWord; + regLPRx = (u4Tmp & bMaskHWord)>>16; + + pCoexSta->highPriorityTx = regHPTx; + pCoexSta->highPriorityRx = regHPRx; + pCoexSta->lowPriorityTx = regLPTx; + pCoexSta->lowPriorityRx = regLPRx; + + if( (pCoexSta->lowPriorityTx > 1050) && (!pCoexSta->bC2hBtInquiryPage)) + pCoexSta->popEventCnt++; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n", + regHPRx, regHPTx, regLPRx, regLPTx)); + + // reset counter + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0xc); + + // This part is for wifi FW and driver to update BT's status as disabled. + // The flow is as the following + // 1. disable BT + // 2. if all BT Tx/Rx counter=0, after 6 sec we query bt info + // 3. Because BT will not rsp from mailbox, so wifi fw will know BT is disabled + // 4. FW will rsp c2h for BT that driver will know BT is disabled. + if ((regHPTx == 0) && (regHPRx ==0) && (regLPTx == 0) && (regLPRx == 0)) + { + NumOfBtCounterChk++; + if (NumOfBtCounterChk == 3) +{ + halbtc8723b1ant_QueryBtInfo(pBtCoexist); + } + } + else + { + NumOfBtCounterChk = 0; + } + } + + +VOID +halbtc8723b1ant_MonitorWiFiCtr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte u4Tmp; + u2Byte u2Tmp[3]; + s4Byte wifiRssi=0; + BOOLEAN bWifiBusy = FALSE, bWifiUnderBMode = FALSE; + static u1Byte nCCKLockCounter = 0; + u4Byte TotalCnt; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, &bWifiUnderBMode); + + if (pCoexSta->bUnderIps) + { + pCoexSta->nCRCOK_CCK = 0; + pCoexSta->nCRCOK_11g = 0; + pCoexSta->nCRCOK_11n = 0; + pCoexSta->nCRCOK_11nAgg = 0; + + pCoexSta->nCRCErr_CCK = 0; + pCoexSta->nCRCErr_11g = 0; + pCoexSta->nCRCErr_11n = 0; + pCoexSta->nCRCErr_11nAgg = 0; + } + else + { + pCoexSta->nCRCOK_CCK = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xf88); + pCoexSta->nCRCOK_11g = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf94); + pCoexSta->nCRCOK_11n = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf90); + pCoexSta->nCRCOK_11nAgg= pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xfb8); + + pCoexSta->nCRCErr_CCK = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xf84); + pCoexSta->nCRCErr_11g = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf96); + pCoexSta->nCRCErr_11n = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf92); + pCoexSta->nCRCErr_11nAgg = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xfba); + } + + + //reset counter + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xf16, 0x1, 0x1); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xf16, 0x1, 0x0); + + if ( (bWifiBusy) && (wifiRssi >= 30) && (!bWifiUnderBMode)) + { + TotalCnt = pCoexSta->nCRCOK_CCK + pCoexSta->nCRCOK_11g + pCoexSta->nCRCOK_11n + + pCoexSta->nCRCOK_11nAgg; + + if ( (pCoexDm->btStatus == BT_8723B_1ANT_BT_STATUS_ACL_BUSY) || + (pCoexDm->btStatus == BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY) || + (pCoexDm->btStatus == BT_8723B_1ANT_BT_STATUS_SCO_BUSY) ) + { + if (pCoexSta->nCRCOK_CCK >(TotalCnt -pCoexSta->nCRCOK_CCK)) + { + if (nCCKLockCounter < 3) + nCCKLockCounter++; + } + else + { + if (nCCKLockCounter > 0) + nCCKLockCounter--; + } + + } + else + { + if (nCCKLockCounter > 0) + nCCKLockCounter--; + } + } + else + { + if (nCCKLockCounter > 0) + nCCKLockCounter--; + } + + if (!pCoexSta->bPreCCKLock) + { + + if (nCCKLockCounter >= 3) + pCoexSta->bCCKLock = TRUE; + else + pCoexSta->bCCKLock = FALSE; + } + else + { + if (nCCKLockCounter == 0) + pCoexSta->bCCKLock = FALSE; + else + pCoexSta->bCCKLock = TRUE; + } + + if (pCoexSta->bCCKLock) + pCoexSta->bCCKEverLock = TRUE; + + pCoexSta->bPreCCKLock = pCoexSta->bCCKLock; + + +} + +BOOLEAN +halbtc8723b1ant_IsWifiStatusChanged( + IN PBTC_COEXIST pBtCoexist + ) +{ + static BOOLEAN bPreWifiBusy=FALSE, bPreUnder4way=FALSE, bPreBtHsOn=FALSE; + BOOLEAN bWifiBusy=FALSE, bUnder4way=FALSE, bBtHsOn=FALSE; + BOOLEAN bWifiConnected=FALSE; + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &bUnder4way); + + if(bWifiConnected) + { + if(bWifiBusy != bPreWifiBusy) + { + bPreWifiBusy = bWifiBusy; + return TRUE; + } + if(bUnder4way != bPreUnder4way) + { + bPreUnder4way = bUnder4way; + return TRUE; + } + if(bBtHsOn != bPreBtHsOn) + { + bPreBtHsOn = bBtHsOn; + return TRUE; + } + + + } + + return FALSE; +} + +VOID +halbtc8723b1ant_UpdateBtLinkInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bBtHsOn=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + pBtLinkInfo->bBtLinkExist = pCoexSta->bBtLinkExist; + pBtLinkInfo->bScoExist = pCoexSta->bScoExist; + pBtLinkInfo->bA2dpExist = pCoexSta->bA2dpExist; + pBtLinkInfo->bPanExist = pCoexSta->bPanExist; + pBtLinkInfo->bHidExist = pCoexSta->bHidExist; + pBtLinkInfo->bBtHiPriLinkExist = pCoexSta->bBtHiPriLinkExist; + + // work around for HS mode. + if(bBtHsOn) + { + pBtLinkInfo->bPanExist = TRUE; + pBtLinkInfo->bBtLinkExist = TRUE; + } + + // check if Sco only + if( pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bScoOnly = TRUE; + else + pBtLinkInfo->bScoOnly = FALSE; + + // check if A2dp only + if( !pBtLinkInfo->bScoExist && + pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bA2dpOnly = TRUE; + else + pBtLinkInfo->bA2dpOnly = FALSE; + + // check if Pan only + if( !pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bPanOnly = TRUE; + else + pBtLinkInfo->bPanOnly = FALSE; + + // check if Hid only + if( !pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + pBtLinkInfo->bHidExist ) + pBtLinkInfo->bHidOnly = TRUE; + else + pBtLinkInfo->bHidOnly = FALSE; +} + +u1Byte +halbtc8723b1ant_ActionAlgorithm( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bBtHsOn=FALSE; + u1Byte algorithm=BT_8723B_1ANT_COEX_ALGO_UNDEFINED; + u1Byte numOfDiffProfile=0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + if(!pBtLinkInfo->bBtLinkExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], No BT link exists!!!\n")); + return algorithm; + } + + if(pBtLinkInfo->bScoExist) + numOfDiffProfile++; + if(pBtLinkInfo->bHidExist) + numOfDiffProfile++; + if(pBtLinkInfo->bPanExist) + numOfDiffProfile++; + if(pBtLinkInfo->bA2dpExist) + numOfDiffProfile++; + + if(numOfDiffProfile == 1) + { + if(pBtLinkInfo->bScoExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO only\n")); + algorithm = BT_8723B_1ANT_COEX_ALGO_SCO; + } + else + { + if(pBtLinkInfo->bHidExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID only\n")); + algorithm = BT_8723B_1ANT_COEX_ALGO_HID; + } + else if(pBtLinkInfo->bA2dpExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = A2DP only\n")); + algorithm = BT_8723B_1ANT_COEX_ALGO_A2DP; + } + else if(pBtLinkInfo->bPanExist) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = PAN(HS) only\n")); + algorithm = BT_8723B_1ANT_COEX_ALGO_PANHS; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = PAN(EDR) only\n")); + algorithm = BT_8723B_1ANT_COEX_ALGO_PANEDR; + } + } + } + } + else if(numOfDiffProfile == 2) + { + if(pBtLinkInfo->bScoExist) + { + if(pBtLinkInfo->bHidExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + HID\n")); + algorithm = BT_8723B_1ANT_COEX_ALGO_HID; + } + else if(pBtLinkInfo->bA2dpExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + A2DP ==> SCO\n")); + algorithm = BT_8723B_1ANT_COEX_ALGO_SCO; + } + else if(pBtLinkInfo->bPanExist) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + PAN(HS)\n")); + algorithm = BT_8723B_1ANT_COEX_ALGO_SCO; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + PAN(EDR)\n")); + algorithm = BT_8723B_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } + else + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bA2dpExist ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID + A2DP\n")); + algorithm = BT_8723B_1ANT_COEX_ALGO_HID_A2DP; + } + else if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID + PAN(HS)\n")); + algorithm = BT_8723B_1ANT_COEX_ALGO_HID_A2DP; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID + PAN(EDR)\n")); + algorithm = BT_8723B_1ANT_COEX_ALGO_PANEDR_HID; + } + } + else if( pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = A2DP + PAN(HS)\n")); + algorithm = BT_8723B_1ANT_COEX_ALGO_A2DP_PANHS; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = A2DP + PAN(EDR)\n")); + algorithm = BT_8723B_1ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } + } + else if(numOfDiffProfile == 3) + { + if(pBtLinkInfo->bScoExist) + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bA2dpExist ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n")); + algorithm = BT_8723B_1ANT_COEX_ALGO_HID; + } + else if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + HID + PAN(HS)\n")); + algorithm = BT_8723B_1ANT_COEX_ALGO_HID_A2DP; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n")); + algorithm = BT_8723B_1ANT_COEX_ALGO_PANEDR_HID; + } + } + else if( pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n")); + algorithm = BT_8723B_1ANT_COEX_ALGO_SCO; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n")); + algorithm = BT_8723B_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } + else + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n")); + algorithm = BT_8723B_1ANT_COEX_ALGO_HID_A2DP; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n")); + algorithm = BT_8723B_1ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } + else if(numOfDiffProfile >= 3) + { + if(pBtLinkInfo->bScoExist) + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n")); + + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n")); + algorithm = BT_8723B_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } + } + + return algorithm; +} + +VOID +halbtc8723b1ant_SetBtAutoReport( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bEnableAutoReport + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + H2C_Parameter[0] = 0; + + if(bEnableAutoReport) + { + H2C_Parameter[0] |= BIT0; + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], BT FW auto report : %s, FW write 0x68=0x%x\n", + (bEnableAutoReport? "Enabled!!":"Disabled!!"), H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x68, 1, H2C_Parameter); +} + +VOID +halbtc8723b1ant_BtAutoReport( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bEnableAutoReport + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s BT Auto report = %s\n", + (bForceExec? "force to":""), ((bEnableAutoReport)? "Enabled":"Disabled"))); + pCoexDm->bCurBtAutoReport = bEnableAutoReport; + + if(!bForceExec) + { + if(pCoexDm->bPreBtAutoReport == pCoexDm->bCurBtAutoReport) + return; + } + halbtc8723b1ant_SetBtAutoReport(pBtCoexist, pCoexDm->bCurBtAutoReport); + + pCoexDm->bPreBtAutoReport = pCoexDm->bCurBtAutoReport; +} + +VOID +halbtc8723b1ant_SetSwPenaltyTxRateAdaptive( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bLowPenaltyRa + ) +{ + u1Byte H2C_Parameter[6] ={0}; + + H2C_Parameter[0] = 0x6; // opCode, 0x6= Retry_Penalty + + if(bLowPenaltyRa) + { + H2C_Parameter[1] |= BIT0; + H2C_Parameter[2] = 0x00; //normal rate except MCS7/6/5, OFDM54/48/36 + H2C_Parameter[3] = 0xf7; //MCS7 or OFDM54 + H2C_Parameter[4] = 0xf8; //MCS6 or OFDM48 + H2C_Parameter[5] = 0xf9; //MCS5 or OFDM36 + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set WiFi Low-Penalty Retry: %s", + (bLowPenaltyRa? "ON!!":"OFF!!") )); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x69, 6, H2C_Parameter); +} + +VOID +halbtc8723b1ant_LowPenaltyRa( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bLowPenaltyRa + ) +{ + pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa; + + if(!bForceExec) + { + if(pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa) + return; + } + halbtc8723b1ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa); + + pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa; +} + +VOID +halbtc8723b1ant_SetCoexTable( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte val0x6c0, + IN u4Byte val0x6c4, + IN u4Byte val0x6c8, + IN u1Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c0=0x%x\n", val0x6c0)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c0, val0x6c0); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c4=0x%x\n", val0x6c4)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c4, val0x6c4); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, val0x6c8); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc)); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cc, val0x6cc); +} + +VOID +halbtc8723b1ant_CoexTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u4Byte val0x6c0, + IN u4Byte val0x6c4, + IN u4Byte val0x6c8, + IN u1Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s write Coex Table 0x6c0=0x%x, 0x6c4=0x%x, 0x6cc=0x%x\n", + (bForceExec? "force to":""), val0x6c0, val0x6c4, val0x6cc)); + pCoexDm->curVal0x6c0 = val0x6c0; + pCoexDm->curVal0x6c4 = val0x6c4; + pCoexDm->curVal0x6c8 = val0x6c8; + pCoexDm->curVal0x6cc = val0x6cc; + + if(!bForceExec) + { + if( (pCoexDm->preVal0x6c0 == pCoexDm->curVal0x6c0) && + (pCoexDm->preVal0x6c4 == pCoexDm->curVal0x6c4) && + (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) && + (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) ) + return; + } + halbtc8723b1ant_SetCoexTable(pBtCoexist, val0x6c0, val0x6c4, val0x6c8, val0x6cc); + + pCoexDm->preVal0x6c0 = pCoexDm->curVal0x6c0; + pCoexDm->preVal0x6c4 = pCoexDm->curVal0x6c4; + pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8; + pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc; +} + +VOID +halbtc8723b1ant_CoexTableWithType( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + +#if BT_8723B_1ANT_ANTDET_ENABLE +#if BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE + if (pBoardInfo->btdmAntNumByAntDet == 2) + { + if (type == 3) + type = 14; + else if (type == 4) + type = 13; + else if (type == 5) + type = 8; + } +#endif +#endif + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], ********** CoexTable(%d) **********\n", type)); + + pCoexSta->nCoexTableType = type; + + switch(type) + { + case 0: + halbtc8723b1ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x55555555, 0xffffff, 0x3); + break; + case 1: + halbtc8723b1ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 2: + halbtc8723b1ant_CoexTable(pBtCoexist, bForceExec, 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 3: + halbtc8723b1ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 4: + if ( pCoexSta->bCCKEverLock) + halbtc8723b1ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0xaaaaaaaa, 0xffffff, 0x3); + else + halbtc8723b1ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0xaaaa5a5a, 0xffffff, 0x3); + break; + case 5: + if ( pCoexSta->bCCKEverLock) + halbtc8723b1ant_CoexTable(pBtCoexist, bForceExec, 0xaaaa5a5a, 0xaaaa5a5a, 0xffffff, 0x3); + else + halbtc8723b1ant_CoexTable(pBtCoexist, bForceExec, 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 6: + halbtc8723b1ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0xaaaaaaaa, 0xffffff, 0x3); + break; + case 7: + halbtc8723b1ant_CoexTable(pBtCoexist, bForceExec, 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3); + break; + case 8: + halbtc8723b1ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 9: + halbtc8723b1ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 10: + halbtc8723b1ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 11: + halbtc8723b1ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 12: + halbtc8723b1ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 13: + halbtc8723b1ant_CoexTable(pBtCoexist, bForceExec, 0x5fff5fff, 0xaaaaaaaa, 0xffffff, 0x3); + break; + case 14: + halbtc8723b1ant_CoexTable(pBtCoexist, bForceExec, 0x5fff5fff, 0x5ada5ada, 0xffffff, 0x3); + break; + case 15: + halbtc8723b1ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0xaaaaaaaa, 0xffffff, 0x3); + break; + default: + break; + } +} + +VOID +halbtc8723b1ant_SetFwIgnoreWlanAct( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bEnable + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + if(bEnable) + { + H2C_Parameter[0] |= BIT0; // function enable + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set FW for BT Ignore Wlan_Act, FW write 0x63=0x%x\n", + H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x63, 1, H2C_Parameter); +} + +VOID +halbtc8723b1ant_IgnoreWlanAct( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bEnable + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Ignore WlanAct %s\n", + (bForceExec? "force to":""), (bEnable? "ON":"OFF"))); + pCoexDm->bCurIgnoreWlanAct = bEnable; + + if(!bForceExec) + { + if(pCoexDm->bPreIgnoreWlanAct == pCoexDm->bCurIgnoreWlanAct) + return; + } + halbtc8723b1ant_SetFwIgnoreWlanAct(pBtCoexist, bEnable); + + pCoexDm->bPreIgnoreWlanAct = pCoexDm->bCurIgnoreWlanAct; +} + +VOID +halbtc8723b1ant_SetLpsRpwm( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + u1Byte lps=lpsVal; + u1Byte rpwm=rpwmVal; + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_LPS_VAL, &lps); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RPWM_VAL, &rpwm); +} + +VOID +halbtc8723b1ant_LpsRpwm( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + BOOLEAN bForceExecPwrCmd=FALSE; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s set lps/rpwm=0x%x/0x%x \n", + (bForceExec? "force to":""), lpsVal, rpwmVal)); + pCoexDm->curLps = lpsVal; + pCoexDm->curRpwm = rpwmVal; + + if(!bForceExec) + { + if( (pCoexDm->preLps == pCoexDm->curLps) && + (pCoexDm->preRpwm == pCoexDm->curRpwm) ) + { + return; + } + } + halbtc8723b1ant_SetLpsRpwm(pBtCoexist, lpsVal, rpwmVal); + + pCoexDm->preLps = pCoexDm->curLps; + pCoexDm->preRpwm = pCoexDm->curRpwm; +} + +VOID +halbtc8723b1ant_SwMechanism( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bLowPenaltyRA + ) +{ + halbtc8723b1ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, bLowPenaltyRA); +} + +VOID +halbtc8723b1ant_SetAntPath( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte antPosType, + IN BOOLEAN bForceExec, + IN BOOLEAN bInitHwCfg, + IN BOOLEAN bWifiOff + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + u4Byte fwVer=0, u4Tmp=0, cntBtCalChk=0; + BOOLEAN bPgExtSwitch=FALSE; + BOOLEAN bUseExtSwitch=FALSE; + BOOLEAN bIsInMpMode = FALSE; + u1Byte H2C_Parameter[2] ={0}, u1Tmp = 0; + + pCoexDm->curAntPosType = antPosType; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_EXT_SWITCH, &bPgExtSwitch); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); // [31:16]=fw ver, [15:0]=fw sub ver + + if((fwVer>0 && fwVer<0xc0000) || bPgExtSwitch) + bUseExtSwitch = TRUE; + +#if BT_8723B_1ANT_ANTDET_ENABLE +#if BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE + if (antPosType == BTC_ANT_PATH_PTA) + { + if ((pBoardInfo->btdmAntDetFinish) && (pBoardInfo->btdmAntNumByAntDet == 2)) + { + if(pBoardInfo->btdmAntPos == BTC_ANTENNA_AT_MAIN_PORT) + antPosType = BTC_ANT_PATH_WIFI; + else + antPosType = BTC_ANT_PATH_BT; + } + } +#endif +#endif + + if(bInitHwCfg) + { + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x780); //WiFi TRx Mask on + //remove due to interrupt is disabled that polling c2h will fail and delay 100ms. + //pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x3c, 0x15); //BT TRx Mask on + + if(fwVer >= 0x180000) + { + /* Use H2C to set GNT_BT to HIGH */ + H2C_Parameter[0] = 1; + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x6E, 1, H2C_Parameter); + } + else + { + // set grant_bt to high + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x765, 0x18); + } + //set wlan_act control by PTA + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0x4); + + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x67, 0x20, 0x0); //BT select s0/s1 is controlled by BT + + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x39, 0x8, 0x1); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x974, 0xff); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x944, 0x3, 0x3); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x930, 0x77); + } + else if(bWifiOff) + { + if(fwVer >= 0x180000) + { + /* Use H2C to set GNT_BT to HIGH */ + H2C_Parameter[0] = 1; + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x6E, 1, H2C_Parameter); + } + else + { + // set grant_bt to high + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x765, 0x18); + } + //set wlan_act to always low + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0x4); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_IS_IN_MP_MODE, &bIsInMpMode); + if(!bIsInMpMode) + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x67, 0x20, 0x0); //BT select s0/s1 is controlled by BT + else + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x67, 0x20, 0x1); //BT select s0/s1 is controlled by WiFi + + // 0x4c[24:23]=00, Set Antenna control by BT_RFE_CTRL BT Vendor 0xac=0xf002 + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x4c); + u4Tmp &= ~BIT23; + u4Tmp &= ~BIT24; + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x4c, u4Tmp); + } + else + { + /* Use H2C to set GNT_BT to LOW */ + if(fwVer >= 0x180000) + { + if (pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x765) != 0) + { + H2C_Parameter[0] = 0; + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x6E, 1, H2C_Parameter); + } + } + else + { + // BT calibration check + while(cntBtCalChk <= 20) + { + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x49d); + cntBtCalChk++; + if(u1Tmp & BIT0) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ########### BT is calibrating (wait cnt=%d) ###########\n", cntBtCalChk)); + delay_ms(50); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ********** BT is NOT calibrating (wait cnt=%d)**********\n", cntBtCalChk)); + break; + } + } + + // set grant_bt to PTA + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x765, 0x0); + } + + if (pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x76e) != 0xc) + { + //set wlan_act control by PTA + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0xc); + } + + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x67, 0x20, 0x1); //BT select s0/s1 is controlled by WiFi + } + + if(bUseExtSwitch) + { + if(bInitHwCfg) + { + // 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x4c); + u4Tmp &=~BIT23; + u4Tmp |= BIT24; + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x4c, u4Tmp); + + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x0); // fixed internal switch S1->WiFi, S0->BT + + if(pBoardInfo->btdmAntPos == BTC_ANTENNA_AT_MAIN_PORT) + { + //tell firmware "no antenna inverse" + H2C_Parameter[0] = 0; + H2C_Parameter[1] = 1; //ext switch type + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x65, 2, H2C_Parameter); + } + else + { + //tell firmware "antenna inverse" + H2C_Parameter[0] = 1; + H2C_Parameter[1] = 1; //ext switch type + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x65, 2, H2C_Parameter); + } + } + + if(bForceExec || (pCoexDm->curAntPosType != pCoexDm->preAntPosType)) + { + // ext switch setting + switch(antPosType) + { + case BTC_ANT_PATH_WIFI: + if(pBoardInfo->btdmAntPos == BTC_ANTENNA_AT_MAIN_PORT) + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x92c, 0x3, 0x1); + else + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x92c, 0x3, 0x2); + break; + case BTC_ANT_PATH_BT: + if(pBoardInfo->btdmAntPos == BTC_ANTENNA_AT_MAIN_PORT) + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x92c, 0x3, 0x2); + else + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x92c, 0x3, 0x1); + break; + default: + case BTC_ANT_PATH_PTA: + if(pBoardInfo->btdmAntPos == BTC_ANTENNA_AT_MAIN_PORT) + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x92c, 0x3, 0x1); + else + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x92c, 0x3, 0x2); + break; + } + } + } + else + { + if(bInitHwCfg) + { + // 0x4c[23]=1, 0x4c[24]=0 Antenna control by 0x64 + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x4c); + u4Tmp |= BIT23; + u4Tmp &=~BIT24; + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x4c, u4Tmp); + + //Fix Ext switch Main->S1, Aux->S0 + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x64, 0x1, 0x0); + + if(pBoardInfo->btdmAntPos == BTC_ANTENNA_AT_MAIN_PORT) + { + + //tell firmware "no antenna inverse" + H2C_Parameter[0] = 0; + H2C_Parameter[1] = 0; //internal switch type + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x65, 2, H2C_Parameter); + } + else + { + + //tell firmware "antenna inverse" + H2C_Parameter[0] = 1; + H2C_Parameter[1] = 0; //internal switch type + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x65, 2, H2C_Parameter); + } + } + + if(bForceExec || (pCoexDm->curAntPosType != pCoexDm->preAntPosType)) + { + // internal switch setting + switch(antPosType) + { + case BTC_ANT_PATH_WIFI: + if(pBoardInfo->btdmAntPos == BTC_ANTENNA_AT_MAIN_PORT) + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x0); + else + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x280); + break; + case BTC_ANT_PATH_BT: + if(pBoardInfo->btdmAntPos == BTC_ANTENNA_AT_MAIN_PORT) + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x280); + else + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x0); + break; + default: + case BTC_ANT_PATH_PTA: + if(pBoardInfo->btdmAntPos == BTC_ANTENNA_AT_MAIN_PORT) + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x200); + else + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x80); + break; + } + } + } + + pCoexDm->preAntPosType = pCoexDm->curAntPosType; +} + +VOID +halbtc8723b1ant_SetAntPathDCut( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bAntennaAux, //For 1-Ant--> 1: Antenna at S0, 0: Antenna at S1. Set 0 for 2-Ant + IN BOOLEAN bExtSwitch, // 1: Ext Switch (SPDT) exist on module, 0: no Ext Switch (SPDT) exist on module + IN BOOLEAN bTwoAntenna, // 1: 2-Antenna, 0:1-Antenna + IN u1Byte antennaPos, //Set Antenna Pos, For 1-Ant: BTC_ANT_PATH_WIFI, BTC_ANT_PATH_BT, BTC_ANT_PATH_PTA, For 2-Ant:BTC_ANT_WIFI_AT_MAIN, BTC_ANT_WIFI_AT_Aux + IN u1Byte wifiState //BTC_WIFI_STAT_INIT, BTC_WIFI_STAT_IQK, BTC_WIFI_STAT_NORMAL_OFF, BTC_WIFI_STAT_MP_OFF, BTC_WIFI_STAT_NORMAL, BTC_WIFI_STAT_ANT_DIV + ) +{ + u1Byte dataLen=5; + u1Byte buf[6] = {0}; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set BT Ant, bAntennaAux/bExtSwitch/bTwoAntenna/antennaPos/wifiState=%d/%d/%d/%d/%d\n", + bAntennaAux, bExtSwitch, bTwoAntenna, antennaPos, wifiState)); + + buf[0] = dataLen; + + if(bAntennaAux) + buf[1] = 0x1; + + if(bExtSwitch) + buf[2] = 0x1; + + if(bTwoAntenna) + buf[3] = 0x1; + + buf[4] = antennaPos; + + buf[5] = wifiState; + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_CTRL_8723B_ANT, (PVOID)&buf[0]); +} + +VOID +halbtc8723b1ant_SetFwPstdma( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte byte1, + IN u1Byte byte2, + IN u1Byte byte3, + IN u1Byte byte4, + IN u1Byte byte5 + ) +{ + u1Byte H2C_Parameter[5] ={0}; + u1Byte realByte1=byte1, realByte5=byte5; + BOOLEAN bApEnable=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + + if(bApEnable) + { + if(byte1&BIT4 && !(byte1&BIT5)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], FW for 1Ant AP mode\n")); + realByte1 &= ~BIT4; + realByte1 |= BIT5; + + realByte5 |= BIT5; + realByte5 &= ~BIT6; + } + } + + H2C_Parameter[0] = realByte1; + H2C_Parameter[1] = byte2; + H2C_Parameter[2] = byte3; + H2C_Parameter[3] = byte4; + H2C_Parameter[4] = realByte5; + + pCoexDm->psTdmaPara[0] = realByte1; + pCoexDm->psTdmaPara[1] = byte2; + pCoexDm->psTdmaPara[2] = byte3; + pCoexDm->psTdmaPara[3] = byte4; + pCoexDm->psTdmaPara[4] = realByte5; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], PS-TDMA H2C cmd =0x%x%08x\n", + H2C_Parameter[0], + H2C_Parameter[1]<<24|H2C_Parameter[2]<<16|H2C_Parameter[3]<<8|H2C_Parameter[4])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x60, 5, H2C_Parameter); +} + + +VOID +halbtc8723b1ant_PsTdma( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bTurnOn, + IN u1Byte type + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bTurnOnByCnt=FALSE, bWifiBusy=FALSE, bWiFiNoisy=FALSE; + u1Byte psTdmaTypeByCnt=0, rssiAdjustVal=0; + u1Byte psTdmaByte4Val = 0x50, psTdmaByte0Val = 0x51, psTdmaByte3Val = 0x10; + s1Byte nWiFiDurationAdjust = 0x0; + static BOOLEAN bPreWifiBusy=FALSE; + + pCoexDm->bCurPsTdmaOn = bTurnOn; + pCoexDm->curPsTdma = type; + +#if BT_8723B_1ANT_ANTDET_ENABLE +#if BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE + if (pBoardInfo->btdmAntNumByAntDet == 2) + { + if (bTurnOn) + type = type +100; //for WiFi RSSI low or BT RSSI low + else + type = 1; //always translate to TDMA(off,1) for TDMA-off case + } + +#endif +#endif + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + + if (bWifiBusy != bPreWifiBusy) + { + bForceExec = TRUE; + bPreWifiBusy = bWifiBusy; + } + + if (pCoexDm->bCurPsTdmaOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ********** TDMA(on, %d) **********\n", + pCoexDm->curPsTdma)); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ********** TDMA(off, %d) **********\n", + pCoexDm->curPsTdma)); + } + + if(!bForceExec) + { + if( (pCoexDm->bPrePsTdmaOn == pCoexDm->bCurPsTdmaOn) && + (pCoexDm->prePsTdma == pCoexDm->curPsTdma) ) + return; + } + + if (pCoexSta->nScanAPNum <= 5) + { + nWiFiDurationAdjust = 5; + + if (pCoexSta->nA2DPBitPool >= 35) + nWiFiDurationAdjust = -10; + else if (pCoexSta->nA2DPBitPool >= 45) + nWiFiDurationAdjust = -15; + } + else if (pCoexSta->nScanAPNum >= 40) + { + nWiFiDurationAdjust = -15; + + if (pCoexSta->nA2DPBitPool < 35) + nWiFiDurationAdjust = -5; + else if (pCoexSta->nA2DPBitPool < 45) + nWiFiDurationAdjust = -10; + } + else if (pCoexSta->nScanAPNum >= 20) + { + nWiFiDurationAdjust = -10; + + if (pCoexSta->nA2DPBitPool >= 45) + nWiFiDurationAdjust = -15; + } + else + { + nWiFiDurationAdjust = 0; + + if (pCoexSta->nA2DPBitPool >= 35) + nWiFiDurationAdjust = -10; + else if (pCoexSta->nA2DPBitPool >= 45) + nWiFiDurationAdjust = -15; + } + + if ((type == 1) || (type == 2) || (type == 9) || (type == 11) || (type == 101) + || (type == 102) || (type == 109) || (type == 101)) + { + if (!pCoexSta->bForceLpsOn) //Native power save TDMA, only for A2DP-only case 1/2/9/11 while wifi noisy threshold > 30 + { + psTdmaByte0Val = 0x61; //no null-pkt + psTdmaByte3Val = 0x11; // no tx-pause at BT-slot + psTdmaByte4Val = 0x10; // 0x778 = d/1 toggle, no dynamic slot + } + else + { + psTdmaByte0Val = 0x51; //null-pkt + psTdmaByte3Val = 0x10; //tx-pause at BT-slot + psTdmaByte4Val = 0x50; // 0x778 = d/1 toggle, dynamic slot + } + } + else if ((type == 3) || (type == 13) || (type == 14) || (type == 103) || (type == 113) || (type == 114)) + { + psTdmaByte0Val = 0x51; //null-pkt + psTdmaByte3Val = 0x10; //tx-pause at BT-slot + psTdmaByte4Val = 0x10; // 0x778 = d/1 toggle, no dynamic slot +#if 0 + if (!bWifiBusy) + psTdmaByte4Val = psTdmaByte4Val | 0x1; //0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) +#endif + } + else //native power save case + { + psTdmaByte0Val = 0x61; //no null-pkt + psTdmaByte3Val = 0x11; // no tx-pause at BT-slot + psTdmaByte4Val = 0x11; // 0x778 = d/1 toggle, no dynamic slot + //psTdmaByte4Va is not defne for 0x778 = d/1, 1/1 case + } + + //if (pBtLinkInfo->bSlaveRole == TRUE) + if ((pBtLinkInfo->bSlaveRole == TRUE) && (pBtLinkInfo->bA2dpExist)) + psTdmaByte4Val = psTdmaByte4Val | 0x1; //0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) + + if (type > 100) + { + psTdmaByte0Val = psTdmaByte0Val | 0x82; //set antenna control by SW + psTdmaByte3Val = psTdmaByte3Val | 0x60; //set antenna no toggle, control by antenna diversity + } + + + if(bTurnOn) + { + switch(type) + { + default: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0x51, 0x1a, 0x1a, 0x0, psTdmaByte4Val); + break; + case 1: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x3a+nWiFiDurationAdjust, 0x03, psTdmaByte3Val, psTdmaByte4Val); + break; + case 2: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x2d+nWiFiDurationAdjust, 0x03, psTdmaByte3Val, psTdmaByte4Val); + break; + case 3: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x3a, 0x03, psTdmaByte3Val, psTdmaByte4Val); + break; + case 4: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0x93, 0x15, 0x3, 0x14, 0x0); + break; + case 5: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x15, 0x3, psTdmaByte3Val, 0x11); + break; + case 6: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x20, 0x3, psTdmaByte3Val, 0x11); + break; + case 7: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0x13, 0xc, 0x5, 0x0, 0x0); + break; + case 8: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0x93, 0x25, 0x3, 0x10, 0x0); + break; + case 9: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x21, 0x3, psTdmaByte3Val, psTdmaByte4Val); + break; + case 10: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0x13, 0xa, 0xa, 0x0, 0x40); + break; + case 11: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x21, 0x03, psTdmaByte3Val, psTdmaByte4Val); + break; + case 12: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0x51, 0x0a, 0x0a, 0x0, 0x50); + break; + case 13: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x21, 0x3, psTdmaByte3Val, psTdmaByte4Val); + break; + case 14: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x21, 0x3, psTdmaByte3Val, psTdmaByte4Val); + break; + case 15: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0x13, 0xa, 0x3, 0x8, 0x0); + break; + case 16: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0x93, 0x15, 0x3, 0x10, 0x0); + break; + case 18: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0x93, 0x25, 0x3, 0x10, 0x0); + break; + case 20: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x3f, 0x03, psTdmaByte3Val, 0x10); + break; + case 21: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0x61, 0x25, 0x03, 0x11, 0x11); + break; + case 22: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x25, 0x03, psTdmaByte3Val, 0x10); + break; + case 23: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x3, 0x31, 0x18); + break; + case 24: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0xe3, 0x15, 0x3, 0x31, 0x18); + break; + case 25: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0x3, 0x31, 0x18); + break; + case 26: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0x3, 0x31, 0x18); + break; + case 27: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x3, 0x31, 0x98); + break; + case 28: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0x69, 0x25, 0x3, 0x31, 0x0); + break; + case 29: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0xab, 0x1a, 0x1a, 0x1, 0x10); + break; + case 30: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0x51, 0x30, 0x3, 0x10, 0x10); + break; + case 31: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0xd3, 0x1a, 0x1a, 0, 0x58); + break; + case 32: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x35, 0x3, psTdmaByte3Val, psTdmaByte4Val); + break; + case 33: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x35, 0x3, psTdmaByte3Val, 0x10); + break; + case 34: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0x53, 0x1a, 0x1a, 0x0, 0x10); + break; + case 35: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0x63, 0x1a, 0x1a, 0x0, 0x10); + break; + case 36: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0xd3, 0x12, 0x3, 0x14, 0x50); + break; + case 40: // SoftAP only with no sta associated,BT disable ,TDMA mode for power saving + /* here softap mode screen off will cost 70-80mA for phone */ + halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0x23, 0x18, 0x00, 0x10, 0x24); + break; + + //for 1-Ant translate to 2-Ant + case 101: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x3a+nWiFiDurationAdjust, 0x03, psTdmaByte3Val, psTdmaByte4Val); + break; + case 102: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x2d+nWiFiDurationAdjust, 0x03, psTdmaByte3Val, psTdmaByte4Val); + break; + case 103: + //halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0x51, 0x1d, 0x1d, 0x0, psTdmaByte4Val); + halbtc8723b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x3a, 0x03, psTdmaByte3Val, psTdmaByte4Val); + break; + case 105: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x15, 0x3, psTdmaByte3Val, 0x11); + break; + case 106: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x20, 0x3, psTdmaByte3Val, 0x11); + break; + case 109: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x21, 0x3, psTdmaByte3Val, psTdmaByte4Val); + break; + case 111: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x21, 0x03, psTdmaByte3Val, psTdmaByte4Val); + break; + case 113: + //halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0x51, 0x12, 0x12, 0x0, psTdmaByte4Val); + halbtc8723b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x21, 0x3, psTdmaByte3Val, psTdmaByte4Val); + break; + case 114: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x21, 0x3, psTdmaByte3Val, psTdmaByte4Val); + break; + case 120: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x3f, 0x03, psTdmaByte3Val, 0x10); + break; + case 122: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x25, 0x03, psTdmaByte3Val, 0x10); + break; + case 132: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x25, 0x03, psTdmaByte3Val, psTdmaByte4Val); + break; + case 133: + halbtc8723b1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x25, 0x03, psTdmaByte3Val, 0x11); + break; + + } + } + else + { + + // disable PS tdma + switch(type) + { + case 8: //PTA Control + halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0x8, 0x0, 0x0, 0x0, 0x0); + break; + case 0: + default: //Software control, Antenna at BT side + halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x0, 0x0); + break; + case 1: // 2-Ant, 0x778=3, antenna control by antenna diversity + halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x48, 0x0); + break; +#if 0 + case 9: //Software control, Antenna at WiFi side + halbtc8723b1ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x0, 0x0); + //halbtc8723b1ant_SetAntPathDCut(pBtCoexist, FALSE, FALSE, FALSE, BTC_ANT_PATH_WIFI, BTC_WIFI_STAT_NORMAL); + halbtc8723b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_WIFI, FALSE, FALSE); + break; +#endif + } + } + rssiAdjustVal =0; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, &rssiAdjustVal); + + + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n", + pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x948), pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x765), pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x67))); + + // update pre state + pCoexDm->bPrePsTdmaOn = pCoexDm->bCurPsTdmaOn; + pCoexDm->prePsTdma = pCoexDm->curPsTdma; +} + +BOOLEAN +halbtc8723b1ant_IsCommonAction( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bCommon=FALSE, bWifiConnected=FALSE, bWifiBusy=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + + if(!bWifiConnected && + BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n")); + + //halbtc8723b1ant_SwMechanism(pBtCoexist, FALSE); + + bCommon = TRUE; + } + else if(bWifiConnected && + (BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi connected + BT non connected-idle!!\n")); + + //halbtc8723b1ant_SwMechanism(pBtCoexist, FALSE); + + bCommon = TRUE; + } + else if(!bWifiConnected && + (BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non connected-idle + BT connected-idle!!\n")); + + //halbtc8723b1ant_SwMechanism(pBtCoexist, FALSE); + + bCommon = TRUE; + } + else if(bWifiConnected && + (BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi connected + BT connected-idle!!\n")); + + //halbtc8723b1ant_SwMechanism(pBtCoexist, FALSE); + + bCommon = TRUE; + } + else if(!bWifiConnected && + (BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE != pCoexDm->btStatus) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non connected-idle + BT Busy!!\n")); + + //halbtc8723b1ant_SwMechanism(pBtCoexist, FALSE); + + bCommon = TRUE; + } + else + { + if (bWifiBusy) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi Connected-Busy + BT Busy!!\n")); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi Connected-Idle + BT Busy!!\n")); + } + + bCommon = FALSE; + } + + return bCommon; +} + + +VOID +halbtc8723b1ant_TdmaDurationAdjustForAcl( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte wifiStatus + ) +{ + static s4Byte up,dn,m,n,WaitCount; + s4Byte result; //0: no change, +1: increase WiFi duration, -1: decrease WiFi duration + u1Byte retryCount=0, btInfoExt; + static BOOLEAN bPreWifiBusy=FALSE; + BOOLEAN bWifiBusy = FALSE; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TdmaDurationAdjustForAcl()\n")); + + if(BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY == wifiStatus) + bWifiBusy = TRUE; + else + bWifiBusy = FALSE; + + if( (BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN == wifiStatus) || + (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN == wifiStatus) || + (BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT == wifiStatus) ) + { + if( pCoexDm->curPsTdma != 1 && + pCoexDm->curPsTdma != 2 && + pCoexDm->curPsTdma != 3 && + pCoexDm->curPsTdma != 9 ) + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + + up = 0; + dn = 0; + m = 1; + n= 3; + result = 0; + WaitCount = 0; + } + return; + } + + if(!pCoexDm->bAutoTdmaAdjust) + { + pCoexDm->bAutoTdmaAdjust = TRUE; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], first run TdmaDurationAdjust()!!\n")); + + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + //============ + up = 0; + dn = 0; + m = 1; + n= 3; + result = 0; + WaitCount = 0; + } + else + { + //accquire the BT TRx retry count from BT_Info byte2 + retryCount = pCoexSta->btRetryCnt; + btInfoExt = pCoexSta->btInfoExt; + + if ( (pCoexSta->lowPriorityTx) > 1050 || (pCoexSta->lowPriorityRx) > 1250 ) + retryCount++; + + result = 0; + WaitCount++; + + if(retryCount == 0) // no retry in the last 2-second duration + { + up++; + dn--; + + if (dn <= 0) + dn = 0; + + if(up >= n) // if s n 2 retry count0, hռeWiFi duration + { + WaitCount = 0; + n = 3; + up = 0; + dn = 0; + result = 1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Increase wifi duration!!\n")); + } + } + else if (retryCount <= 3) // <=3 retry in the last 2-second duration + { + up--; + dn++; + + if (up <= 0) + up = 0; + + if (dn == 2) // if s 2 2 retry count< 3, hկWiFi duration + { + if (WaitCount <= 2) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter<3!!\n")); + } + } + else //retry count > 3, un1 retry count > 3, hկWiFi duration + { + if (WaitCount == 1) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter>3!!\n")); + } + + if(result == -1) + { +/* if( (BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(btInfoExt)) && + ((pCoexDm->curPsTdma == 1) ||(pCoexDm->curPsTdma == 2)) ) + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else */ if(pCoexDm->curPsTdma == 1) + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + } + else if(result == 1) + { +/* if( (BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(btInfoExt)) && + ((pCoexDm->curPsTdma == 1) ||(pCoexDm->curPsTdma == 2)) ) + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else */ if(pCoexDm->curPsTdma == 11) + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + } + else //no change + { + /* Bryant Modify + if(bWifiBusy != bPreWifiBusy) //if busy / idle change + { + bPreWifiBusy = bWifiBusy; + halbtc8723b1ant_PsTdma(pBtCoexist, FORCE_EXEC, TRUE, pCoexDm->curPsTdma); + } + */ + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], ********** TDMA(on, %d) **********\n", + pCoexDm->curPsTdma)); + } + + if( pCoexDm->curPsTdma != 1 && + pCoexDm->curPsTdma != 2 && + pCoexDm->curPsTdma != 9 && + pCoexDm->curPsTdma != 11 ) + { + // recover to previous adjust type + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, pCoexDm->psTdmaDuAdjType); + } + } +} + +VOID +halbtc8723b1ant_PsTdmaCheckForPowerSaveState( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bNewPsState + ) +{ + u1Byte lpsMode=0x0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_LPS_MODE, &lpsMode); + + if(lpsMode) // already under LPS state + { + if(bNewPsState) + { + // keep state under LPS, do nothing. + } + else + { + // will leave LPS state, turn off psTdma first + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + } + } + else // NO PS state + { + if(bNewPsState) + { + // will enter LPS state, turn off psTdma first + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + } + else + { + // keep state under NO PS state, do nothing. + } + } +} + +VOID +halbtc8723b1ant_PowerSaveState( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte psType, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + BOOLEAN bLowPwrDisable=FALSE; + + switch(psType) + { + case BTC_PS_WIFI_NATIVE: + // recover to original 32k low power setting + bLowPwrDisable = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_NORMAL_LPS, NULL); + pCoexSta->bForceLpsOn = FALSE; + break; + case BTC_PS_LPS_ON: + halbtc8723b1ant_PsTdmaCheckForPowerSaveState(pBtCoexist, TRUE); + halbtc8723b1ant_LpsRpwm(pBtCoexist, NORMAL_EXEC, lpsVal, rpwmVal); + // when coex force to enter LPS, do not enter 32k low power. + bLowPwrDisable = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + // power save must executed before psTdma. + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_ENTER_LPS, NULL); + pCoexSta->bForceLpsOn = TRUE; + break; + case BTC_PS_LPS_OFF: + halbtc8723b1ant_PsTdmaCheckForPowerSaveState(pBtCoexist, FALSE); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_LEAVE_LPS, NULL); + pCoexSta->bForceLpsOn = FALSE; + break; + default: + break; + } +} + +VOID +halbtc8723b1ant_ActionWifiOnly( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8723b1ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 0); + halbtc8723b1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8); + halbtc8723b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, FORCE_EXEC, FALSE, FALSE); +} + +VOID +halbtc8723b1ant_MonitorBtEnableDisable( + IN PBTC_COEXIST pBtCoexist + ) +{ + static BOOLEAN bPreBtDisabled=FALSE; + static u4Byte btDisableCnt=0; + BOOLEAN bBtActive=TRUE, bBtDisabled=FALSE; + + // This function check if bt is disabled + + if( pCoexSta->highPriorityTx == 0 && + pCoexSta->highPriorityRx == 0 && + pCoexSta->lowPriorityTx == 0 && + pCoexSta->lowPriorityRx == 0) + { + bBtActive = FALSE; + } + if( pCoexSta->highPriorityTx == 0xffff && + pCoexSta->highPriorityRx == 0xffff && + pCoexSta->lowPriorityTx == 0xffff && + pCoexSta->lowPriorityRx == 0xffff) + { + bBtActive = FALSE; + } + if(bBtActive) + { + btDisableCnt = 0; + bBtDisabled = FALSE; + } + else + { + btDisableCnt++; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], bt all counters=0, %d times!!\n", btDisableCnt)); + if(btDisableCnt >= 2) + { + bBtDisabled = TRUE; + } + } + if(bPreBtDisabled != bBtDisabled) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is from %s to %s!!\n", (bPreBtDisabled ? "disabled":"enabled"), + (bBtDisabled ? "disabled":"enabled"))); + + bPreBtDisabled = bBtDisabled; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); + if(bBtDisabled) + { + halbtc8723b1ant_ActionWifiOnly(pBtCoexist); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_LEAVE_LPS, NULL); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_NORMAL_LPS, NULL); + } + } +} + +//============================================= +// +// Software Coex Mechanism start +// +//============================================= + +// SCO only or SCO+PAN(HS) + +/* +VOID +halbtc8723b1ant_ActionSco( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8723b1ant_SwMechanism(pBtCoexist, TRUE); +} + + +VOID +halbtc8723b1ant_ActionHid( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8723b1ant_SwMechanism(pBtCoexist, TRUE); +} + +//A2DP only / PAN(EDR) only/ A2DP+PAN(HS) +VOID +halbtc8723b1ant_ActionA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8723b1ant_SwMechanism(pBtCoexist, FALSE); +} + +VOID +halbtc8723b1ant_ActionA2dpPanHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8723b1ant_SwMechanism(pBtCoexist, FALSE); +} + +VOID +halbtc8723b1ant_ActionPanEdr( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8723b1ant_SwMechanism(pBtCoexist, FALSE); +} + +//PAN(HS) only +VOID +halbtc8723b1ant_ActionPanHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8723b1ant_SwMechanism(pBtCoexist, FALSE); +} + +//PAN(EDR)+A2DP +VOID +halbtc8723b1ant_ActionPanEdrA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8723b1ant_SwMechanism(pBtCoexist, FALSE); +} + +VOID +halbtc8723b1ant_ActionPanEdrHid( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8723b1ant_SwMechanism(pBtCoexist, TRUE); +} + +// HID+A2DP+PAN(EDR) +VOID +halbtc8723b1ant_ActionHidA2dpPanEdr( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8723b1ant_SwMechanism(pBtCoexist, TRUE); +} + +VOID +halbtc8723b1ant_ActionHidA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8723b1ant_SwMechanism(pBtCoexist, TRUE); +} + +*/ + +//============================================= +// +// Non-Software Coex Mechanism start +// +//============================================= +VOID +halbtc8723b1ant_ActionBtWhckTest( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8723b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8723b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); +} + +VOID +halbtc8723b1ant_ActionWifiMultiPort( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8723b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8723b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); +} + +VOID +halbtc8723b1ant_ActionHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); +} + +VOID +halbtc8723b1ant_ActionBtInquiry( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bWifiConnected=FALSE, bApEnable=FALSE, bWifiBusy=FALSE, bBtBusy=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bBtBusy); + + if ( (!bWifiConnected) && (!pCoexSta->bWiFiIsHighPriTask) ) + { + halbtc8723b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8723b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + else if( (pBtLinkInfo->bScoExist) || (pBtLinkInfo->bHidExist) || (pBtLinkInfo->bA2dpExist) ) + { + // SCO/HID/A2DP busy + halbtc8723b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + if (pCoexSta->bC2hBtRemoteNameReq) + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 33); + else + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else if ( (pBtLinkInfo->bPanExist) || (bWifiBusy) ) + { + halbtc8723b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + if (pCoexSta->bC2hBtRemoteNameReq) + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 33); + else + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else + { + halbtc8723b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8723b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + + } +} + +VOID +halbtc8723b1ant_ActionBtScoHidOnlyBusy( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte wifiStatus + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bWifiConnected=FALSE; + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + + // tdma and coex table + + if(pBtLinkInfo->bScoExist) + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 5); + } + else //HID + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 5); + } +} + +VOID +halbtc8723b1ant_ActionWifiConnectedBtAclBusy( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte wifiStatus + ) +{ + u1Byte btRssiState; + + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + btRssiState = halbtc8723b1ant_BtRssiState(2, 28, 0); + + if ( (pCoexSta->lowPriorityRx >= 950) && (!pCoexSta->bUnderIps) ) + { + pBtLinkInfo->bSlaveRole = TRUE; + } + else + { + pBtLinkInfo->bSlaveRole = FALSE; + } + + if(pBtLinkInfo->bHidOnly) //HID + { + halbtc8723b1ant_ActionBtScoHidOnlyBusy(pBtCoexist, wifiStatus); + pCoexDm->bAutoTdmaAdjust = FALSE; + return; + } + else if(pBtLinkInfo->bA2dpOnly) //A2DP + { + if(BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifiStatus) + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + pCoexDm->bAutoTdmaAdjust = FALSE; + } + else + { + halbtc8723b1ant_TdmaDurationAdjustForAcl(pBtCoexist, wifiStatus); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + pCoexDm->bAutoTdmaAdjust = TRUE; + } + } + else if ( ((pBtLinkInfo->bA2dpExist) && (pBtLinkInfo->bPanExist)) || + (pBtLinkInfo->bHidExist&&pBtLinkInfo->bA2dpExist&&pBtLinkInfo->bPanExist) ) //A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + pCoexDm->bAutoTdmaAdjust = FALSE; + } + else if(pBtLinkInfo->bHidExist&&pBtLinkInfo->bA2dpExist) //HID+A2DP + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->bAutoTdmaAdjust = FALSE; + + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 3); + } + else if( (pBtLinkInfo->bPanOnly) || (pBtLinkInfo->bHidExist&&pBtLinkInfo->bPanExist) ) //PAN(OPP,FTP), HID+PAN(OPP,FTP) + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + pCoexDm->bAutoTdmaAdjust = FALSE; + } + else + { + //BT no-profile busy (0x9) + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 33); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + pCoexDm->bAutoTdmaAdjust = FALSE; + } +} + +VOID +halbtc8723b1ant_ActionWifiNotConnected( + IN PBTC_COEXIST pBtCoexist + ) +{ + // power save state + halbtc8723b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + halbtc8723b1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8); + halbtc8723b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); +} + +VOID +halbtc8723b1ant_ActionWifiNotConnectedScan( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + + halbtc8723b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + if(BT_8723B_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) + { + if (pBtLinkInfo->bA2dpExist) + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else if (pBtLinkInfo->bA2dpExist && pBtLinkInfo->bPanExist) + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 22); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 20); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + } + else if( (BT_8723B_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + halbtc8723b1ant_ActionBtScoHidOnlyBusy(pBtCoexist, + BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN); + } + else + { + //Bryant Add + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8723b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + } +} + +VOID +halbtc8723b1ant_ActionWifiNotConnectedAssoAuth( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + + halbtc8723b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + if( (pBtLinkInfo->bScoExist) || (pBtLinkInfo->bHidExist) || (pBtLinkInfo->bA2dpExist) ) + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 4); + } + else if (pBtLinkInfo->bPanExist) + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 20); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 4); + } + else + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8723b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 2); + } +} + +VOID +halbtc8723b1ant_ActionWifiConnectedScan( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + + halbtc8723b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + if(BT_8723B_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) + { + if (pBtLinkInfo->bA2dpExist) + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else if (pBtLinkInfo->bA2dpExist && pBtLinkInfo->bPanExist) + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 22); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 20); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + } + else if( (BT_8723B_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + halbtc8723b1ant_ActionBtScoHidOnlyBusy(pBtCoexist, + BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN); + } + else + { + //Bryant Add + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8723b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + } +} + +VOID +halbtc8723b1ant_ActionWifiConnectedSpecialPacket( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bWifiBusy = FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + + //no special packet process for both WiFi and BT very busy + if ((bWifiBusy) && ((pBtLinkInfo->bPanExist) || (pCoexSta->nNumOfProfile >= 2))) + return; + + halbtc8723b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + if((pBtLinkInfo->bScoExist) || (pBtLinkInfo->bHidExist)) + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 5); + } + else if (pBtLinkInfo->bA2dpExist) + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else if(pBtLinkInfo->bPanExist) + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 20); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8723b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + } +} + +VOID +halbtc8723b1ant_ActionWifiConnected( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bWifiBusy=FALSE; + BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE; + BOOLEAN bUnder4way=FALSE, bApEnable=FALSE; + u4Byte wifiBw; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CoexForWifiConnect()===>\n")); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &bUnder4way); + if(bUnder4way) + { + halbtc8723b1ant_ActionWifiConnectedSpecialPacket(pBtCoexist); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n")); + return; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + if(bScan || bLink || bRoam) + { + if(bScan) + halbtc8723b1ant_ActionWifiConnectedScan(pBtCoexist); + else + halbtc8723b1ant_ActionWifiConnectedSpecialPacket(pBtCoexist); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n")); + return; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + + // power save state + if(!bApEnable && BT_8723B_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus && !pBtCoexist->btLinkInfo.bHidOnly) + { + if(pBtCoexist->btLinkInfo.bA2dpOnly) //A2DP + { + if(!bWifiBusy) + halbtc8723b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else //busy + { + if (pCoexSta->nScanAPNum >= BT_8723B_1ANT_WIFI_NOISY_THRESH) //no force LPS, no PS-TDMA, use pure TDMA + { + halbtc8723b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } + else + { + halbtc8723b1ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + } + } + } + else if ((pCoexSta->bPanExist == FALSE) && (pCoexSta->bA2dpExist == FALSE) && (pCoexSta->bHidExist == FALSE)) + halbtc8723b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else + halbtc8723b1ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + } + else + halbtc8723b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + if(!bWifiBusy) + { + if(BT_8723B_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) + { + halbtc8723b1ant_ActionWifiConnectedBtAclBusy(pBtCoexist, + BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE); + } + else if( (BT_8723B_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + halbtc8723b1ant_ActionBtScoHidOnlyBusy(pBtCoexist, + BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE); + } + else + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8723b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + if ( (pCoexSta->highPriorityTx) + (pCoexSta->highPriorityRx) <= 60 ) + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + } + else + { + if(BT_8723B_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) + { + halbtc8723b1ant_ActionWifiConnectedBtAclBusy(pBtCoexist, + BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY); + } + else if( (BT_8723B_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + halbtc8723b1ant_ActionBtScoHidOnlyBusy(pBtCoexist, + BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY); + } + else + { + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8723b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + if ( (pCoexSta->highPriorityTx) + (pCoexSta->highPriorityRx) <= 60 ) + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + } +} + +VOID +halbtc8723b1ant_RunSwCoexistMechanism( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte algorithm=0; + + algorithm = halbtc8723b1ant_ActionAlgorithm(pBtCoexist); + pCoexDm->curAlgorithm = algorithm; + + if(halbtc8723b1ant_IsCommonAction(pBtCoexist)) + { + + } + else + { + switch(pCoexDm->curAlgorithm) + { + case BT_8723B_1ANT_COEX_ALGO_SCO: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = SCO.\n")); + //halbtc8723b1ant_ActionSco(pBtCoexist); + break; + case BT_8723B_1ANT_COEX_ALGO_HID: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = HID.\n")); + //halbtc8723b1ant_ActionHid(pBtCoexist); + break; + case BT_8723B_1ANT_COEX_ALGO_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = A2DP.\n")); + //halbtc8723b1ant_ActionA2dp(pBtCoexist); + break; + case BT_8723B_1ANT_COEX_ALGO_A2DP_PANHS: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = A2DP+PAN(HS).\n")); + //halbtc8723b1ant_ActionA2dpPanHs(pBtCoexist); + break; + case BT_8723B_1ANT_COEX_ALGO_PANEDR: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = PAN(EDR).\n")); + //halbtc8723b1ant_ActionPanEdr(pBtCoexist); + break; + case BT_8723B_1ANT_COEX_ALGO_PANHS: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = HS mode.\n")); + //halbtc8723b1ant_ActionPanHs(pBtCoexist); + break; + case BT_8723B_1ANT_COEX_ALGO_PANEDR_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = PAN+A2DP.\n")); + //halbtc8723b1ant_ActionPanEdrA2dp(pBtCoexist); + break; + case BT_8723B_1ANT_COEX_ALGO_PANEDR_HID: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = PAN(EDR)+HID.\n")); + //halbtc8723b1ant_ActionPanEdrHid(pBtCoexist); + break; + case BT_8723B_1ANT_COEX_ALGO_HID_A2DP_PANEDR: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = HID+A2DP+PAN.\n")); + //halbtc8723b1ant_ActionHidA2dpPanEdr(pBtCoexist); + break; + case BT_8723B_1ANT_COEX_ALGO_HID_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = HID+A2DP.\n")); + //halbtc8723b1ant_ActionHidA2dp(pBtCoexist); + break; + default: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = coexist All Off!!\n")); + //halbtc8723b1ant_CoexAllOff(pBtCoexist); + break; + } + pCoexDm->preAlgorithm = pCoexDm->curAlgorithm; + } +} + +VOID +halbtc8723b1ant_RunCoexistMechanism( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bWifiConnected=FALSE, bBtHsOn=FALSE, bWifiBusy = FALSE; + BOOLEAN bIncreaseScanDevNum=FALSE; + BOOLEAN bBtCtrlAggBufSize=FALSE; + BOOLEAN bMiracastPlusBt=FALSE; + u1Byte aggBufSize=5; + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiLinkStatus=0; + u4Byte numOfWifiLink=0, wifiBw; + u1Byte iotPeer=BTC_IOT_PEER_UNKNOWN; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism()===>\n")); + + if(pBtCoexist->bManualControl) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n")); + return; + } + + if(pBtCoexist->bStopCoexDm) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n")); + return; + } + + if(pCoexSta->bUnderIps) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi is under IPS !!!\n")); + return; + } + + if(pCoexSta->bBtWhckTest) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is under WHCK TEST!!!\n")); + halbtc8723b1ant_ActionBtWhckTest(pBtCoexist); + return; + } + + if( (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) || + (BT_8723B_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + bIncreaseScanDevNum = TRUE; + } + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, &bIncreaseScanDevNum); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_LINK_STATUS, &wifiLinkStatus); + numOfWifiLink = wifiLinkStatus>>16; + + if((numOfWifiLink>=2) || (wifiLinkStatus&WIFI_P2P_GO_CONNECTED)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], Multi-Port numOfWifiLink = %d, wifiLinkStatus = 0x%x\n", numOfWifiLink,wifiLinkStatus) ); + + if(pBtLinkInfo->bBtLinkExist) + { + halbtc8723b1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 1, 1, 0, 1); + bMiracastPlusBt = TRUE; + } + else + { + halbtc8723b1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + bMiracastPlusBt = FALSE; + } + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_MIRACAST_PLUS_BT, &bMiracastPlusBt); + halbtc8723b1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, bBtCtrlAggBufSize, aggBufSize); + + if (( (pBtLinkInfo->bA2dpExist) || (bWifiBusy) ) && (pCoexSta->bC2hBtInquiryPage) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], BT Is Inquirying \n") ); + halbtc8723b1ant_ActionBtInquiry(pBtCoexist); + } + else + halbtc8723b1ant_ActionWifiMultiPort(pBtCoexist); + + return; + } + else + { + bMiracastPlusBt = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_MIRACAST_PLUS_BT, &bMiracastPlusBt); + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if ( (pBtLinkInfo->bBtLinkExist) && (bWifiConnected) ) + { + halbtc8723b1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 1, 1, 0, 1); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_IOT_PEER, &iotPeer); + + if(BTC_IOT_PEER_CISCO != iotPeer) + { + if(pBtLinkInfo->bScoExist)//if (pBtLinkInfo->bBtHiPriLinkExist) + //halbtc8723b1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x5); + halbtc8723b1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x5); + else + halbtc8723b1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x5); + //halbtc8723b1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, TRUE, 0x8); + } + else + { + if(pBtLinkInfo->bScoExist) + halbtc8723b1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x5); + else + { + if (BTC_WIFI_BW_HT40==wifiBw) + halbtc8723b1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, TRUE, 0x10); + else + halbtc8723b1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, TRUE, 0x8); + } + } + + halbtc8723b1ant_SwMechanism(pBtCoexist, TRUE); + halbtc8723b1ant_RunSwCoexistMechanism(pBtCoexist); //just print debug message + } + else + { + halbtc8723b1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + + halbtc8723b1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x5); + + halbtc8723b1ant_SwMechanism(pBtCoexist, FALSE); + halbtc8723b1ant_RunSwCoexistMechanism(pBtCoexist); ////just print debug message + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + if(pCoexSta->bC2hBtInquiryPage) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], BT Is Inquirying \n") ); + halbtc8723b1ant_ActionBtInquiry(pBtCoexist); + return; + } + else if(bBtHsOn) + { + halbtc8723b1ant_ActionHs(pBtCoexist); + return; + } + + + if(!bWifiConnected) + { + BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi is non connected-idle !!!\n")); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + + if(bScan || bLink || bRoam) + { + if (bScan) + halbtc8723b1ant_ActionWifiNotConnectedScan(pBtCoexist); + else + halbtc8723b1ant_ActionWifiNotConnectedAssoAuth(pBtCoexist); + } + else + halbtc8723b1ant_ActionWifiNotConnected(pBtCoexist); + } + else // wifi LPS/Busy + { + halbtc8723b1ant_ActionWifiConnected(pBtCoexist); + } +} + +u4Byte +halbtc8723b1ant_PSD_Log2Base( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte val + + ) +{ + u1Byte i,j; + u4Byte tmp, tmp2, val_integerdB=0, tindex, shiftcount=0; + u4Byte result,val_fractiondB=0,Table_fraction[21]= {0,432, 332, 274, 232, 200, + 174, 151,132,115,100,86,74,62,51,42, + 32,23,15,7,0}; + + if (val == 0) + return 0; + + tmp = val; + + while(1) + { + if (tmp == 1) + break; + else + { + tmp = (tmp >> 1); + shiftcount++; + } + } + + + val_integerdB = shiftcount+1; + + tmp2=1; + for (j=1; j<= val_integerdB;j++) + tmp2 = tmp2*2; + + tmp = (val*100) /tmp2; + tindex = tmp/5; + + if (tindex > 20) + tindex = 20; + + val_fractiondB = Table_fraction[tindex]; + + result = val_integerdB*100 - val_fractiondB; + + return (result); + + +} + +VOID +halbtc8723b1ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + // force to reset coex mechanism + + // sw all off + halbtc8723b1ant_SwMechanism(pBtCoexist, FALSE); + + //halbtc8723b1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8); + //halbtc8723b1ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 0); + + pCoexSta->popEventCnt = 0; +} + +VOID +halbtc8723b1ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bBackUp, + IN BOOLEAN bWifiOnly + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + u4Byte u4Tmp=0;//, fwVer; + u2Byte u2Tmp=0; + u1Byte u1Tmp=0, u1Tmpa=0, u1Tmpb=0; + u1Byte H2C_Parameter[2] ={0}; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 1Ant Init HW Config!!\n")); + + pPsdScan->nAntDet_IsAntDetAvailable = FALSE; + + //0xf0[15:12] --> Chip Cut information + pCoexSta->nCutVersion = (pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xf1) & 0xf0) >> 4; + +#if 0//move to BTC_MEDIA_CONNECT + if(bBackUp) + { + pCoexDm->backupArfrCnt1 = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x430); + pCoexDm->backupArfrCnt2 = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x434); + pCoexDm->backupRetryLimit = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0x42a); + pCoexDm->backupAmpduMaxTime = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x456); + } +#endif + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x550, 0x8, 0x1); //enable TBTT nterrupt + + // 0x790[5:0]=0x5 + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x790, 0x5); + + // Enable counter statistics + //pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0xc); //0x76e[3] =1, WLAN_Act control by PTA + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x778, 0x1); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x40, 0x20, 0x1); + + + //pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x67, 0x20, 0x1); //BT select s0/s1 is controlled by WiFi + + halbtc8723b1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8); + + //Antenna config + if(bWifiOnly) + halbtc8723b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_WIFI, FORCE_EXEC, TRUE, FALSE); + else + halbtc8723b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FORCE_EXEC, TRUE, FALSE); + +#if 0 + if(bWifiOnly) + { + halbtc8723b1ant_SetAntPathDCut(pBtCoexist, FALSE, FALSE, FALSE, BTC_ANT_PATH_WIFI, BTC_WIFI_STAT_INIT); + halbtc8723b1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8); + } + else + halbtc8723b1ant_SetAntPathDCut(pBtCoexist, FALSE, FALSE, FALSE, BTC_ANT_PATH_BT, BTC_WIFI_STAT_INIT); +#endif + + + + // PTA parameter + halbtc8723b1ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 0); + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x948); + u1Tmpa = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x765); + u1Tmpb = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x67); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n", + u4Tmp, u1Tmpa, u1Tmpb)); +} + + + + + +VOID +halbtc8723b1ant_MechanismSwitch( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bSwitchTo2Antenna + ) +{ + + if (bSwitchTo2Antenna) // 1-Ant -> 2-Ant + { + //un-lock TRx Mask setup for 8723b f-cut + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xdd, 0x80, 0x1); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xdf, 0x1, 0x1); + //WiFi TRx Mask on + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + //BT TRx Mask un-lock 0x2c[0], 0x30[0] = 1 + pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x2c, 0x7c45); + pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x30, 0x7c45); + + //BT TRx Mask on + pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x3c, 0x1); + + halbtc8723b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FORCE_EXEC, FALSE, FALSE); + } + else + { + //WiFi TRx Mask on + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x780); + + //lock TRx Mask setup for 8723b f-cut + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xdd, 0x80, 0x0); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xdf, 0x1, 0x0); + + //BT TRx Mask on + pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x3c, 0x15); + + //BT TRx Mask ock 0x2c[0], 0x30[0] = 0 + pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x2c, 0x7c44); + pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x30, 0x7c44); + + + halbtc8723b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, FORCE_EXEC, FALSE, FALSE); + } + +} + + + + +VOID +halbtc8723b1ant_PSD_ShowAntennaDetectResult( + IN PBTC_COEXIST pBtCoexist + ) +{ + pu1Byte cliBuf=pBtCoexist->cliBuf; + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n============[Antenna Detection info] ============\n"); + CL_PRINTF(cliBuf); + + if (pPsdScan->nAntDet_Result == 1) + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (>%d)", "Ant Det Result", "2-Antenna (Bad-Isolation)", + BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION); + else if (pPsdScan->nAntDet_Result == 2) + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (%d~%d)", "Ant Det Result", "2-Antenna (Good-Isolation)", + BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION+pPsdScan->nAntDet_ThresOffset, BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION); + else + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (%d~%d)", "Ant Det Result", "1-Antenna", + BT_8723B_1ANT_ANTDET_PSDTHRES_1ANT, BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION+pPsdScan->nAntDet_ThresOffset); + + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s ", "Antenna Detection Finish", + (pBoardInfo->btdmAntDetFinish? "Yes":"No")); + CL_PRINTF(cliBuf); + + switch(pPsdScan->nAntDet_Result) + { + case 0: + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "(BT is not available)"); + break; + case 1: // 2-Ant bad-isolation + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "(BT is available)"); + break; + case 2: // 2-Ant good-isolation + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "(BT is available)"); + break; + case 3: // 1-Ant + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "(BT is available)"); + break; + case 4: + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "(Uncertainty result)"); + break; + case 5: + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "(Pre-Scan fai)"); + break; + case 6: + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "(WiFi is Scanning)"); + break; + case 7: + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "(BT is not idle)"); + break; + case 8: + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "(Abort by WiFi Scanning)"); + break; + case 9: + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "(Antenna Init is not ready)"); + break; + case 10: + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "(BT is Inquiry or page)"); + break; + case 11: + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "(BT is Disabled)"); + break; +} + CL_PRINTF(cliBuf); + + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "Ant Detect Total Count",pPsdScan->bAntDet_TryCount); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "Ant Detect Fail Count",pPsdScan->bAntDet_FailCount); + CL_PRINTF(cliBuf); + + if ( (!pBoardInfo->btdmAntDetFinish) && (pPsdScan->nAntDet_Result != 5) ) + return; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Response",(pPsdScan->nAntDet_Result? "ok":"fail")); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ms", "BT Tx Time", pPsdScan->nAntDet_BTTxTime); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "BT Tx Ch", pPsdScan->nAntDet_BTLEChannel); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", "WiFi PSD Cent-Ch/Offset/Span", + pPsdScan->nRealCentFreq, pPsdScan->nRealOffset, pPsdScan->nRealSpan); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d dB", "PSD Pre-Scan Peak Value", pPsdScan->nAntDet_PrePSDScanPeakVal/100); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s (<= %d)", "PSD Pre-Scan result", + (pPsdScan->nAntDet_Result != 5? "ok":"fail"), BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND+pPsdScan->nAntDet_ThresOffset); + CL_PRINTF(cliBuf); + + if (pPsdScan->nAntDet_Result == 5) + return; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s dB", "PSD Scan Peak Value", pPsdScan->nAntDet_PeakVal); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s MHz", "PSD Scan Peak Freq", pPsdScan->nAntDet_PeakFreq); + CL_PRINTF(cliBuf); + + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "TFBGA Package", + (pBoardInfo->bTfbgaPackage)? "Yes":"No"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "PSD Threshold Offset", pPsdScan->nAntDet_ThresOffset); + CL_PRINTF(cliBuf); + +} + +VOID +halbtc8723b1ant_PSD_ShowData( + IN PBTC_COEXIST pBtCoexist + ) +{ + pu1Byte cliBuf=pBtCoexist->cliBuf; + u4Byte nDeltaFreqPerPoint; + u4Byte freq,freq1,freq2,n=0,i=0, j=0, m=0, PsdRep1, PsdRep2; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n\n============[PSD info] (%d)============\n", + pPsdScan->nPSDGenCount); + CL_PRINTF(cliBuf); + + if (pPsdScan->nPSDGenCount == 0) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n No Data !!\n"); + CL_PRINTF(cliBuf); + return; + } + + if (pPsdScan->nPSDPoint == 0) + nDeltaFreqPerPoint = 0; + else + nDeltaFreqPerPoint = pPsdScan->nPSDBandWidth/pPsdScan->nPSDPoint; + + //if (pPsdScan->bIsPSDShowMaxOnly) + if (0) + { + PsdRep1 = pPsdScan->nPSDMaxValue/100; + PsdRep2 = pPsdScan->nPSDMaxValue - PsdRep1 * 100; + + freq = ((pPsdScan->nRealCentFreq-20) * 1000000 + pPsdScan->nPSDMaxValuePoint * nDeltaFreqPerPoint); + freq1 = freq/1000000; + freq2 = freq/1000 - freq1 * 1000; + + if (freq2 < 100) + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n Freq = %d.0%d MHz", + freq1, freq2); + else + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n Freq = %d.%d MHz", + freq1, freq2); + + if (PsdRep2 < 10) + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, ", Value = %d.0%d dB, (%d) \n", + PsdRep1, PsdRep2, pPsdScan->nPSDMaxValue); + else + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, ", Value = %d.%d dB, (%d)\n", + PsdRep1, PsdRep2, pPsdScan->nPSDMaxValue); + + CL_PRINTF(cliBuf); + } + else + { + m = pPsdScan->nPSDStartPoint; + n = pPsdScan->nPSDStartPoint; + i = 1; + j = 1; + + while(1) + { + do + { + freq = ((pPsdScan->nRealCentFreq-20) * 1000000 + m * nDeltaFreqPerPoint); + freq1 = freq/1000000; + freq2 = freq/1000 - freq1 * 1000; + + if (i ==1) + { + if (freq2 == 0) + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n Freq%6d.000", freq1); + else if (freq2 < 100) + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n Freq%6d.0%2d", freq1,freq2); + else + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n Freq%6d.%3d", freq1,freq2); + } + else if ( (i%8 == 0) || (m == pPsdScan->nPSDStopPoint) ) + { + if (freq2 == 0) + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "%6d.000\n", freq1); + else if (freq2 < 100) + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "%6d.0%2d\n", freq1,freq2); + else + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "%6d.%3d\n", freq1,freq2); + } + else + { + if (freq2 == 0) + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "%6d.000", freq1); + else if (freq2 < 100) + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "%6d.0%2d", freq1,freq2); + else + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "%6d.%3d", freq1,freq2); + } + + i++; + m++; + CL_PRINTF(cliBuf); + + }while( (i <= 8) && (m <= pPsdScan->nPSDStopPoint)); + + + do + { + PsdRep1 = pPsdScan->nPSDReport_MaxHold[n]/100; + PsdRep2 = pPsdScan->nPSDReport_MaxHold[n] - PsdRep1 * 100; + + if (j ==1) + { + if (PsdRep2 <10) + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n Val %7d.0%d", PsdRep1,PsdRep2); + else + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n Val %7d.%d", PsdRep1,PsdRep2); + } + else if ( (j%8 == 0) || (n == pPsdScan->nPSDStopPoint) ) + { + if (PsdRep2 <10) + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "%7d.0%d\n", PsdRep1,PsdRep2); + else + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "%7d.%d\n", PsdRep1,PsdRep2); + } + else + { + if (PsdRep2 <10) + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "%7d.0%d", PsdRep1,PsdRep2); + else + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "%7d.%d", PsdRep1,PsdRep2); + } + + j++; + n++; + CL_PRINTF(cliBuf); + + } while( (j <= 8) && (n <= pPsdScan->nPSDStopPoint)); + + if ( (m > pPsdScan->nPSDStopPoint) || (n > pPsdScan->nPSDStopPoint) ) + break; + else + { + i = 1; + j = 1; + } + + } + } + + +} + +VOID +halbtc8723b1ant_PSD_MaxHoldData( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte GenCount + ) +{ + u4Byte i=0, i_max=0, val_max=0, j; + + if (GenCount== 1) + { + memcpy(pPsdScan->nPSDReport_MaxHold, pPsdScan->nPSDReport, BT_8723B_1ANT_ANTDET_PSD_POINTS*sizeof(u4Byte)); + + for (i= pPsdScan->nPSDStartPoint; i<=pPsdScan->nPSDStopPoint; i++) + { + //RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx SweepPSDPoint(), Max_Hold i = %d, PSDReport = %d dB\n", i, pPsdScan->nPSDReport_MaxHold[i])); + } + + pPsdScan->nPSDMaxValuePoint = 0; + pPsdScan->nPSDMaxValue = 0; + + } + else + { + for (i= pPsdScan->nPSDStartPoint; i<=pPsdScan->nPSDStopPoint; i++) + { + if (pPsdScan->nPSDReport[i] > pPsdScan->nPSDReport_MaxHold[i]) + pPsdScan->nPSDReport_MaxHold[i] = pPsdScan->nPSDReport[i]; + + //search Max Value + if (i ==pPsdScan->nPSDStartPoint ) + { + i_max = i; + val_max = pPsdScan->nPSDReport_MaxHold[i]; + } + else + { + if (pPsdScan->nPSDReport_MaxHold[i] > val_max) + { + i_max = i; + val_max = pPsdScan->nPSDReport_MaxHold[i]; + } + } + + //RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx SweepPSDPoint(), Max_Hold i = %d, PSDReport = %d dB\n", i, pPsdScan->nPSDReport_MaxHold[i])); + + } + + pPsdScan->nPSDMaxValuePoint = i_max; + pPsdScan->nPSDMaxValue = val_max; + + //RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx SweepPSDPoint(), Max_Hold i_Max = %d, PSDReport_Max = %d dB\n", pPsdScan->nPSDMaxValuePoint + // ,pPsdScan->nPSDMaxValue)); + } + + +} + +u4Byte +halbtc8723b1ant_PSD_GetData( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte nPoint + ) +{ + //reg 0x808[9:0]: FFT data x + //reg 0x808[22]: 0-->1 to get 1 FFT data y + //reg 0x8b4[15:0]: FFT data y report + + u4Byte val = 0, psd_report =0; + + val = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x808); + + val &= 0xffbffc00; + val |= nPoint; + + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x808, val); + + val |= 0x00400000; + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x808, val); + + + val = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x8b4); + + psd_report = val & 0x0000ffff; + + return psd_report; +} + + +VOID +halbtc8723b1ant_PSD_SweepPoint( +IN PBTC_COEXIST pBtCoexist, + IN u4Byte centFreq, + IN s4Byte offset, + IN u4Byte span, + IN u4Byte points, + IN u4Byte avgnum + ) +{ + u4Byte i,val,n,k=0; + u4Byte nPoints=0, psd_report=0; + u4Byte nStartP=0, nStopP=0, nDeltaFreqPerPoint=156250; + u4Byte nPSDCenterFreq=20*10^6, freq,freq1,freq2; + BOOLEAN outloop = FALSE; + u1Byte flag = 0; + u4Byte tmp, PsdRep1, PsdRep2; + u4Byte WiFi_OriginalChannel = 1; + + pPsdScan->bIsPSDRunning = TRUE; + + do + { + switch(flag) + { + case 0: //Get PSD parameters + default: + //RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx SweepPSDPoint(), centFreq=0x%x, offset=0x%x, span=0x%x\n", + // centFreq, offset, span)); + + pPsdScan->nPSDBandWidth = 40*1000000; + pPsdScan->nPSDPoint = points; + pPsdScan->nPSDStartBase = points/2; + pPsdScan->nPSDAvgNum = avgnum; + pPsdScan->nRealCentFreq = centFreq; + pPsdScan->nRealOffset = offset; + pPsdScan->nRealSpan = span; + + + nPoints = pPsdScan->nPSDPoint; + nDeltaFreqPerPoint = pPsdScan->nPSDBandWidth/pPsdScan->nPSDPoint; + + //PSD point setup + val = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x808); + val &= 0xffff0fff; + + switch(pPsdScan->nPSDPoint) + { + case 128: + val |= 0x0; + break; + case 256: + default: + val |=0x00004000; + break; + case 512: + val |= 0x00008000; + break; + case 1024: + val |= 0x0000c000; + break; + } + + switch(pPsdScan->nPSDAvgNum) + { + case 1: + val |= 0x0; + break; + case 8: + val |=0x00001000; + break; + case 16: + val |= 0x00002000; + break; + case 32: + default: + val |= 0x00003000; + break; + } + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x808, val); + + //RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx SweepPSDPoint(), PSD BW= %d, DeltaFreq=%d\n" + // , pPsdScan->nPSDBandWidth, nDeltaFreqPerPoint)); + flag = 1; + break; + case 1: //calculate the PSD point index from freq/offset/span + nPSDCenterFreq = pPsdScan->nPSDBandWidth /2 +offset*(1000000); + //RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx SweepPSDPoint(), PSD Center Freq = %d\n", (centFreq + offset))); + + nStartP = pPsdScan->nPSDStartBase + (nPSDCenterFreq - span *(1000000)/2) /nDeltaFreqPerPoint; + pPsdScan->nPSDStartPoint = nStartP - pPsdScan->nPSDStartBase; + //RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx SweepPSDPoint(), Start PSD Poin Matrix Index = %d\n", pPsdScan->nPSDStartPoint)); + + nStopP = pPsdScan->nPSDStartBase + (nPSDCenterFreq + span *(1000000)/2) /nDeltaFreqPerPoint; + pPsdScan->nPSDStopPoint = nStopP - pPsdScan->nPSDStartBase-1; + //RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx SweepPSDPoint(), Stop PSD Poin Matrix Index = %d\n",pPsdScan->nPSDStopPoint)); + + flag = 2; + break; + case 2: //set RF channel/BW/Mode + + //set 3-wire off + val = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x88c); + val |= 0x00300000; + pBtCoexist->fBtcWrite4Byte(pBtCoexist,0x88c,val); + + //CCK off + val = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x800); + val &= 0xfeffffff; + pBtCoexist->fBtcWrite4Byte(pBtCoexist,0x800,val); + + //store WiFi original channel + WiFi_OriginalChannel = pBtCoexist->fBtcGetRfReg(pBtCoexist, BTC_RF_A, 0x18, 0x3ff); + + //Set RF channel + if (centFreq == 2484) + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x18, 0x3ff, 0xe); + else + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x18, 0x3ff, (centFreq-2412)/5 + 1); //WiFi TRx Mask on + + //Set RF mode = Rx, RF Gain = 0x8a0 + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x0, 0xfffff, 0x308a0); + + //Set RF Rx filter corner + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, 0x3e4); + + //Set TRx mask off + //un-lock TRx Mask setup + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xdd, 0x80, 0x1); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xdf, 0x1, 0x1); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + flag = 3; + break; + case 3: + memset(pPsdScan->nPSDReport,0, pPsdScan->nPSDPoint*sizeof(u4Byte)); + nStartP = pPsdScan->nPSDStartPoint + pPsdScan->nPSDStartBase; + nStopP = pPsdScan->nPSDStopPoint + pPsdScan->nPSDStartBase + 1; + + i = nStartP; + + while (i < nStopP) + { + if (i >= nPoints) + { + psd_report = halbtc8723b1ant_PSD_GetData(pBtCoexist,i-nPoints); + } + else + { + psd_report = halbtc8723b1ant_PSD_GetData(pBtCoexist,i); + } + + if (psd_report == 0) + tmp = 0; + else + //tmp = 20*log10((double)psd_report); + //20*log2(x)/log2(10), log2Base return theresult of the psd_report*100 + tmp = 6 * halbtc8723b1ant_PSD_Log2Base(pBtCoexist, psd_report); + + n = i-pPsdScan->nPSDStartBase; + pPsdScan->nPSDReport[n] = tmp; + PsdRep1 = pPsdScan->nPSDReport[n] /100; + PsdRep2 = pPsdScan->nPSDReport[n] - PsdRep1 * 100; + + freq = ((centFreq-20) * 1000000 + n * nDeltaFreqPerPoint); + freq1 = freq/1000000; + freq2 = freq/1000 - freq1 * 1000; +/* + if (freq2 < 100) + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx SweepPSDPoint(), i = %d (%d.0%d MHz)", n, freq1, freq2)); + else + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx SweepPSDPoint(), i = %d (%d.%d MHz)", n, freq1, freq2)); + + if (PsdRep2 < 10) + RT_TRACE(COMP_COEX, DBG_LOUD, (", PSDReport = %d (%d.0%d dB)\n",psd_report, PsdRep1, PsdRep2)); + else + RT_TRACE(COMP_COEX, DBG_LOUD, (", PSDReport = %d (%d.%d dB)\n",psd_report, PsdRep1,PsdRep2)); +*/ + i++; + + k=0; + + //Add Delay between PSD point + while(1) + { + if (k++ > 20000) + break; + } + + //RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx SweepPSDPoint()==============\n")); + } + + flag = 100; + break; + case 99: //error + + outloop = TRUE; + break; + case 100: //recovery + + //set 3-wire on + val = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x88c); + val &=0xffcfffff; + pBtCoexist->fBtcWrite4Byte(pBtCoexist,0x88c,val); + + //CCK on + val = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x800); + val |= 0x01000000; + pBtCoexist->fBtcWrite4Byte(pBtCoexist,0x800,val); + + //PSD off + val = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x808); + val &=0xffbfffff; + pBtCoexist->fBtcWrite4Byte(pBtCoexist,0x808,val); + + //TRx Mask on + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x780); + + //lock TRx Mask setup + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xdd, 0x80, 0x0); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xdf, 0x1, 0x0); + + //Set RF Rx filter corner + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, 0x0); + + //restore WiFi original channel + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x18, 0x3ff, WiFi_OriginalChannel); + + outloop = TRUE; + break; + + } + + }while (!outloop); + + + + pPsdScan->bIsPSDRunning = FALSE; + + +} + +VOID +halbtc8723b1ant_PSD_AntennaDetection( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte BTTxTime, + IN u4Byte BTLEChannel + ) +{ + u4Byte realseconds = 0, i=0, j=0; + u4Byte WLPSD_CentFreq = 2484, WLPSD_Span = 2, WLPSD_SweepCount = 50; + s4Byte WLPSD_Offset = -4; + u1Byte BTLECh[13] = {3,6,8,11,13,16,18,21,23,26,28,31,33}; + + u1Byte H2C_Parameter[3] ={0},u1Tmpa,u1Tmpb; + + u1Byte state=0; + BOOLEAN outloop = FALSE, BTResp = FALSE, bScan ,bRoam; + u4Byte freq,freq1,freq2,PsdRep1, PsdRep2, nDeltaFreqPerPoint,u4Tmp; + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + + pBoardInfo->btdmAntDetFinish = FALSE; + memset(pPsdScan->nAntDet_PeakVal, 0, 16*sizeof(UCHAR)); + memset(pPsdScan->nAntDet_PeakFreq, 0, 16*sizeof(UCHAR)); + + if (pBoardInfo->bTfbgaPackage) //for TFBGA + pPsdScan->nAntDet_ThresOffset = 5; + else + pPsdScan->nAntDet_ThresOffset = 0; + + do + { + switch(state) + { + case 0: + if (BTLEChannel == 39) + WLPSD_CentFreq = 2484; + else + { + for (i=1; i<=13; i++) + { + if (BTLECh[i-1] == BTLEChannel) + { + WLPSD_CentFreq = 2412 + (i-1) * 5; + break; + } + } + + if (i == 14) + { + + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx AntennaDetect(), Abort!!, Invalid LE channel = %d\n ", BTLEChannel)); + outloop = TRUE; + break; + } + } + + WLPSD_SweepCount = BTTxTime * 238 /100; //BTTxTime/0.42 + + if (WLPSD_SweepCount % 5 != 0) + WLPSD_SweepCount = (WLPSD_SweepCount/5 + 1) * 5; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx AntennaDetect(), BT_LETxTime=%d, BT_LECh = %d\n", BTTxTime, BTLEChannel)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx AntennaDetect(), WLPSD_CentFreq=%d, WLPSD_Offset = %d, WLPSD_Span = %d, WLPSD_SweepCount = %d\n", + WLPSD_CentFreq, WLPSD_Offset, WLPSD_Span,WLPSD_SweepCount)); + + state = 1; + break; + case 1: //stop coex DM & set antenna path + //Stop Coex DM + pBtCoexist->bStopCoexDm = TRUE; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx AntennaDetect(), Stop Coex DM!!\n")); + + //set native power save + halbtc8723b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + //Set TDMA off, + halbtc8723b1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); + + //Set coex table + halbtc8723b1ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 0); + + if(pBoardInfo->btdmAntPos == BTC_ANTENNA_AT_MAIN_PORT) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Main Port\n")); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx AntennaDetect(), Antenna at Aux Port\n")); + } + + //Set Antenna path, switch WiFi to un-certain antenna port + halbtc8723b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FORCE_EXEC, FALSE, FALSE); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to BT!!\n")); + + //Set AFH mask on at WiFi channel 2472MHz +/- 10MHz + H2C_Parameter[0] = 0x1; + H2C_Parameter[1] = 0xd; + H2C_Parameter[2] = 0x14; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx AntennaDetect(), Set AFH on, Cent-Ch= %d, Mask=%d\n", + H2C_Parameter[1],H2C_Parameter[2])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x66, 3, H2C_Parameter); + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x948); + u1Tmpa = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x765); + u1Tmpb = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x778); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x778=0x%x\n", + u4Tmp, u1Tmpa, u1Tmpb)); + + state =2; + break; + case 2: //Pre-sweep background psd + for (pPsdScan->nPSDGenCount=1; pPsdScan->nPSDGenCount<=3; pPsdScan->nPSDGenCount++) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx AntennaDetect(), PSDGenCount = %d\n ", pPsdScan->nPSDGenCount)); + halbtc8723b1ant_PSD_SweepPoint(pBtCoexist, WLPSD_CentFreq, WLPSD_Offset, WLPSD_Span, BT_8723B_1ANT_ANTDET_PSD_POINTS, BT_8723B_1ANT_ANTDET_PSD_AVGNUM); + halbtc8723b1ant_PSD_MaxHoldData(pBtCoexist, pPsdScan->nPSDGenCount); + } + + pPsdScan->nAntDet_PrePSDScanPeakVal = pPsdScan->nPSDMaxValue; + + if (pPsdScan->nPSDMaxValue > (BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND+pPsdScan->nAntDet_ThresOffset)*100) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx AntennaDetect(), Abort Antenna Detection!! becaus background = %d > thres (%d)\n", + pPsdScan->nPSDMaxValue/100, BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND+pPsdScan->nAntDet_ThresOffset)); + pBoardInfo->btdmAntDetFinish = FALSE; + pBoardInfo->btdmAntNumByAntDet = 1; + pPsdScan->nAntDet_Result = 5; + state = 99; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx AntennaDetect(), Start Antenna Detection!! becaus background = %d <= thres (%d)\n", + pPsdScan->nPSDMaxValue/100, BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND+pPsdScan->nAntDet_ThresOffset)); + state = 3; + } + break; + case 3: + BTResp = pBtCoexist->fBtcSetBtAntDetection(pBtCoexist, (u1Byte)(BTTxTime&0xff), (u1Byte)(BTLEChannel&0xff)); + + for (pPsdScan->nPSDGenCount=1; pPsdScan->nPSDGenCount<=WLPSD_SweepCount; pPsdScan->nPSDGenCount++) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx AntennaDetect(), PSDGenCount = %d\n ", pPsdScan->nPSDGenCount)); + halbtc8723b1ant_PSD_SweepPoint(pBtCoexist, WLPSD_CentFreq, WLPSD_Offset, WLPSD_Span, BT_8723B_1ANT_ANTDET_PSD_POINTS, BT_8723B_1ANT_ANTDET_PSD_AVGNUM); + halbtc8723b1ant_PSD_MaxHoldData(pBtCoexist, pPsdScan->nPSDGenCount); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + + if (bScan ||bRoam) + { + pBoardInfo->btdmAntDetFinish = FALSE; + pBoardInfo->btdmAntNumByAntDet = 1; + pPsdScan->nAntDet_Result = 8; + state = 99; + break; + } + } + + pPsdScan->nAntDet_PSDScanPeakVal = pPsdScan->nPSDMaxValue; + pPsdScan->nAntDet_PSDScanPeakFreq = pPsdScan->nPSDMaxValuePoint; + state = 4; + break; + case 4: + + if (pPsdScan->nPSDPoint == 0) + nDeltaFreqPerPoint = 0; + else + nDeltaFreqPerPoint = pPsdScan->nPSDBandWidth/pPsdScan->nPSDPoint; + + PsdRep1 = pPsdScan->nPSDMaxValue/100; + PsdRep2 = pPsdScan->nPSDMaxValue - PsdRep1 * 100; + + freq = ((pPsdScan->nRealCentFreq-20) * 1000000 + pPsdScan->nPSDMaxValuePoint * nDeltaFreqPerPoint); + freq1 = freq/1000000; + freq2 = freq/1000 - freq1 * 1000; + + if (freq2 < 100) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx AntennaDetect(), Max Value: Freq = %d.0%d MHz", freq1, freq2)); + CL_SPRINTF(pPsdScan->nAntDet_PeakFreq, BT_8723B_1ANT_ANTDET_BUF_LEN, "%d.0%d", freq1,freq2); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx AntennaDetect(), Max Value: Freq = %d.%d MHz", freq1, freq2)); + CL_SPRINTF(pPsdScan->nAntDet_PeakFreq, BT_8723B_1ANT_ANTDET_BUF_LEN, "%d.%d", freq1,freq2); + } + + if (PsdRep2 < 10) + { + RT_TRACE(COMP_COEX, DBG_LOUD, (", Value = %d.0%d dB\n", PsdRep1, PsdRep2)); + CL_SPRINTF(pPsdScan->nAntDet_PeakVal, BT_8723B_1ANT_ANTDET_BUF_LEN, "%d.0%d", PsdRep1,PsdRep2); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, (", Value = %d.%d dB\n",PsdRep1, PsdRep2)); + CL_SPRINTF(pPsdScan->nAntDet_PeakVal, BT_8723B_1ANT_ANTDET_BUF_LEN, "%d.%d", PsdRep1,PsdRep2); + } + + pPsdScan->nAntDet_IsBTReplyAvailable = TRUE; + + if (BTResp == FALSE) + { + pPsdScan->nAntDet_IsBTReplyAvailable = FALSE; + pPsdScan->nAntDet_Result = 0; + pBoardInfo->btdmAntDetFinish = FALSE; + pBoardInfo->btdmAntNumByAntDet = 1; + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx AntennaDetect(), BT Response = Fail \n ")); + } + else if (pPsdScan->nPSDMaxValue > (BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION)*100) + { + pPsdScan->nAntDet_Result = 1; + pBoardInfo->btdmAntDetFinish = TRUE; + pBoardInfo->btdmAntNumByAntDet = 2; + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Bad-Isolation!! \n")); + } + else if (pPsdScan->nPSDMaxValue > (BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION+pPsdScan->nAntDet_ThresOffset)*100) + { + pPsdScan->nAntDet_Result = 2; + pBoardInfo->btdmAntDetFinish = TRUE; + pBoardInfo->btdmAntNumByAntDet = 2; + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 2-Ant, Good-Isolation!! \n")); + } + else if (pPsdScan->nPSDMaxValue > (BT_8723B_1ANT_ANTDET_PSDTHRES_1ANT)*100) + { + pPsdScan->nAntDet_Result = 3; + pBoardInfo->btdmAntDetFinish = TRUE; + pBoardInfo->btdmAntNumByAntDet = 1; + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant!!\n")); + } + else + { + pPsdScan->nAntDet_Result = 4; + pBoardInfo->btdmAntDetFinish = FALSE; + pBoardInfo->btdmAntNumByAntDet = 1; + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx AntennaDetect(), Detect Result = 1-Ant, un-certainity!!\n")); + } + + state = 99; + break; + case 99: //restore setup + + //Set AFH mask off at WiFi channel 2472MHz +/- 10MHz + H2C_Parameter[0] = 0x0; + H2C_Parameter[1] = 0x0; + H2C_Parameter[2] = 0x0; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx AntennaDetect(), Set AFH on, Cent-Ch= %d, Mask=%d\n", + H2C_Parameter[1],H2C_Parameter[2])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x66, 3, H2C_Parameter); + + //Set Antenna Path + halbtc8723b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, FORCE_EXEC, FALSE, FALSE); + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx AntennaDetect(), Set Antenna to PTA\n!!")); + + //Resume Coex DM + pBtCoexist->bStopCoexDm = FALSE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx AntennaDetect(), Resume Coex DM\n!!")); + + //stimulate coex running + halbtc8723b1ant_RunCoexistMechanism(pBtCoexist); + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx AntennaDetect(), Stimulate Coex running\n!!")); + + outloop = TRUE; + break; + } + + }while(!outloop); + + + + } + +VOID +halbtc8723b1ant_PSD_AntennaDetectionCheck( + IN PBTC_COEXIST pBtCoexist + ) +{ + static u4Byte AntDetCount = 0, AntDetFailCount = 0; + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + + BOOLEAN bScan, bRoam; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + + + pPsdScan->nAntDet_BTTxTime = 20; //0.42ms*50 = 20ms + pPsdScan->nAntDet_BTLEChannel = 39; + + AntDetCount++; + + pPsdScan->bAntDet_TryCount = AntDetCount; + + if (bScan ||bRoam) + { + pBoardInfo->btdmAntDetFinish = FALSE; + pPsdScan->nAntDet_Result = 6; + } + else if(pBtCoexist->btInfo.bBtDisabled) + { + pBoardInfo->btdmAntDetFinish = FALSE; + pPsdScan->nAntDet_Result = 11; + } + else if (pCoexSta->nNumOfProfile >= 1) + { + pBoardInfo->btdmAntDetFinish = FALSE; + pPsdScan->nAntDet_Result = 7; + } + else if (!pPsdScan->nAntDet_IsAntDetAvailable) //Antenna initial setup is not ready + { + pBoardInfo->btdmAntDetFinish = FALSE; + pPsdScan->nAntDet_Result = 9; + } + else if (pCoexSta->bC2hBtInquiryPage) + { + pBoardInfo->btdmAntDetFinish = FALSE; + pPsdScan->nAntDet_Result = 10; + } + else + { + halbtc8723b1ant_PSD_AntennaDetection(pBtCoexist, pPsdScan->nAntDet_BTTxTime, pPsdScan->nAntDet_BTLEChannel); + } + + if (!pBoardInfo->btdmAntDetFinish) + AntDetFailCount++; + + pPsdScan->bAntDet_FailCount = AntDetFailCount; + +} + + +//============================================================ +// work around function start with wa_halbtc8723b1ant_ +//============================================================ +//============================================================ +// extern function start with EXhalbtc8723b1ant_ +//============================================================ +VOID +EXhalbtc8723b1ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + u1Byte u1Tmp=0x0; + u2Byte u2Tmp=0x0; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx Execute 8723b 1-Ant PowerOn Setting xxxxxxxxxxxxxxxx!!\n")); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("Ant Det Finish = %s, Ant Det Number = %d\n", + (pBoardInfo->btdmAntDetFinish? "Yes":"No"), pBoardInfo->btdmAntNumByAntDet)); + + pBtCoexist->bStopCoexDm = TRUE; + + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x67, 0x20); + + // enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. + u2Tmp = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0x2); + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x2, u2Tmp|BIT0|BIT1); + + // set GRAN_BT = 1 + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x765, 0x18); + // set WLAN_ACT = 0 + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0x4); + + // + // S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) + // Local setting bit define + // BIT0: "0" for no antenna inverse; "1" for antenna inverse + // BIT1: "0" for internal switch; "1" for external switch + // BIT2: "0" for one antenna; "1" for two antenna + // NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 + if(pBtCoexist->chipInterface == BTC_INTF_USB) + { + // fixed at S0 for USB interface + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x0); + + u1Tmp |= 0x1; // antenna inverse + pBtCoexist->fBtcWriteLocalReg1Byte(pBtCoexist, 0xfe08, u1Tmp); + + pBoardInfo->btdmAntPos = BTC_ANTENNA_AT_AUX_PORT; + } + else + { + // for PCIE and SDIO interface, we check efuse 0xc3[6] + if(pBoardInfo->singleAntPath == 0) + { + // set to S1 + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x280); + pBoardInfo->btdmAntPos = BTC_ANTENNA_AT_MAIN_PORT; + } + else if(pBoardInfo->singleAntPath == 1) + { + // set to S0 + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x0); + u1Tmp |= 0x1; // antenna inverse + pBoardInfo->btdmAntPos = BTC_ANTENNA_AT_AUX_PORT; + } + + if(pBtCoexist->chipInterface == BTC_INTF_PCI) + { + pBtCoexist->fBtcWriteLocalReg1Byte(pBtCoexist, 0x384, u1Tmp); + } + else if(pBtCoexist->chipInterface == BTC_INTF_SDIO) + { + pBtCoexist->fBtcWriteLocalReg1Byte(pBtCoexist, 0x60, u1Tmp); + } + } +} + +VOID +EXhalbtc8723b1ant_PreLoadFirmware( + IN PBTC_COEXIST pBtCoexist + ) +{ +} + +VOID +EXhalbtc8723b1ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ) +{ + halbtc8723b1ant_InitHwConfig(pBtCoexist, TRUE, bWifiOnly); + pBtCoexist->bStopCoexDm = FALSE; +} + +VOID +EXhalbtc8723b1ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Coex Mechanism Init!!\n")); + + pBtCoexist->bStopCoexDm = FALSE; + + halbtc8723b1ant_InitCoexDm(pBtCoexist); + + halbtc8723b1ant_QueryBtInfo(pBtCoexist); +} + +VOID +EXhalbtc8723b1ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + pu1Byte cliBuf=pBtCoexist->cliBuf; + u1Byte u1Tmp[4], i, btInfoExt, psTdmaCase=0; + u2Byte u2Tmp[4]; + u4Byte u4Tmp[4]; + u4Byte faOfdm, faCck; + u4Byte fwVer=0, btPatchVer=0; + static u1Byte PopReportIn10s = 0; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cliBuf); + + if(pBtCoexist->bManualControl) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[Under Manual Control]============"); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n =========================================="); + CL_PRINTF(cliBuf); + } + if(pBtCoexist->bStopCoexDm) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[Coex is STOPPED]============"); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n =========================================="); + CL_PRINTF(cliBuf); + } + + if (pPsdScan->bAntDet_TryCount == 0) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", "Ant PG Num/ Mech/ Pos", + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum, pBoardInfo->btdmAntPos); + CL_PRINTF(cliBuf); + } + else + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d (%d/%d/%d)", "Ant PG Num/ Mech(Ant_Det)/ Pos", + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNumByAntDet, pBoardInfo->btdmAntPos, + pPsdScan->bAntDet_TryCount, pPsdScan->bAntDet_FailCount, pPsdScan->nAntDet_Result); + CL_PRINTF(cliBuf); + + if (pBoardInfo->btdmAntDetFinish) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "Ant Det PSD Value", pPsdScan->nAntDet_PeakVal); + CL_PRINTF(cliBuf); + } + } + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \ + ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion); + CL_PRINTF(cliBuf); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_BT_PATCH_VER, &btPatchVer); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)/ %c", "Version Coex/ Fw/ Patch/ Cut", \ + GLCoexVerDate8723b1Ant, GLCoexVer8723b1Ant, fwVer, btPatchVer, btPatchVer, pCoexSta->nCutVersion+65); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", "Wifi channel informed to BT", \ + pCoexDm->wifiChnlInfo[0], pCoexDm->wifiChnlInfo[1], + pCoexDm->wifiChnlInfo[2]); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s", "WifibHiPri/ Ccklock/ CckEverLock", \ + (pCoexSta->bWiFiIsHighPriTask? "Yes":"No"), + (pCoexSta->bCCKLock? "Yes":"No"), + (pCoexSta->bCCKEverLock? "Yes":"No")); + CL_PRINTF(cliBuf); + + // wifi status + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Wifi Status]============"); + CL_PRINTF(cliBuf); + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[BT Status]============"); + CL_PRINTF(cliBuf); + + PopReportIn10s++; + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ", "BT [status/ rssi/ retryCnt/ popCnt]", \ + ((pBtCoexist->btInfo.bBtDisabled)? ("disabled"): ((pCoexSta->bC2hBtInquiryPage)?("inquiry/page scan"):((BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus)? "non-connected idle": + ( (BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus)? "connected-idle":"busy")))), + pCoexSta->btRssi, pCoexSta->btRetryCnt, pCoexSta->popEventCnt); + CL_PRINTF(cliBuf); + + if (PopReportIn10s >= 5) + { + pCoexSta->popEventCnt = 0; + PopReportIn10s = 0; + } + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d / %d / %d", "SCO/HID/PAN/A2DP/NameReq/WHQL", \ + pBtLinkInfo->bScoExist, pBtLinkInfo->bHidExist, pBtLinkInfo->bPanExist, pBtLinkInfo->bA2dpExist, pCoexSta->bC2hBtRemoteNameReq, pCoexSta->bBtWhckTest ); + CL_PRINTF(cliBuf); + + if (pStackInfo->bProfileNotified) + { + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO); + } + else + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Role", \ + (pBtLinkInfo->bSlaveRole )? "Slave":"Master"); + CL_PRINTF(cliBuf); + } + + btInfoExt = pCoexSta->btInfoExt; + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %d", "A2DP Rate/Bitpool", \ + (btInfoExt&BIT0)? "BR":"EDR", pCoexSta->nA2DPBitPool); + CL_PRINTF(cliBuf); + + for(i=0; ibtInfoC2hCnt[i]) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", GLBtInfoSrc8723b1Ant[i], \ + pCoexSta->btInfoC2h[i][0], pCoexSta->btInfoC2h[i][1], + pCoexSta->btInfoC2h[i][2], pCoexSta->btInfoC2h[i][3], + pCoexSta->btInfoC2h[i][4], pCoexSta->btInfoC2h[i][5], + pCoexSta->btInfoC2h[i][6], pCoexSta->btInfoC2hCnt[i]); + CL_PRINTF(cliBuf); + } + } + + + if(pBtCoexist->bManualControl) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism] (before Manual)============"); + } + else + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============"); + } + + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "SM[LowPenaltyRA]", \ + pCoexDm->bCurLowPenaltyRa); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %d ", "DelBA/ BtCtrlAgg/ AggSize", \ + (pBtCoexist->btInfo.bRejectAggPkt? "Yes":"No"), (pBtCoexist->btInfo.bBtCtrlAggBufSize? "Yes":"No"), + pBtCoexist->btInfo.aggBufSize); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "Rate Mask", \ + pBtCoexist->btInfo.raMask); + CL_PRINTF(cliBuf); + + // Fw mechanism + if(pBtCoexist->bManualControl) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism] (before Manual) ============"); + } + else + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============"); + } + + CL_PRINTF(cliBuf); + + psTdmaCase = pCoexDm->curPsTdma; + if (pBoardInfo->btdmAntNumByAntDet == 2) + { + if (pCoexDm->bCurPsTdmaOn) + psTdmaCase = psTdmaCase +100; //for WiFi RSSI low or BT RSSI low + else + psTdmaCase = 1; //always translate to TDMA(off,1) for TDMA-off case + } + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)", "PS TDMA", \ + pCoexDm->psTdmaPara[0], pCoexDm->psTdmaPara[1], + pCoexDm->psTdmaPara[2], pCoexDm->psTdmaPara[3], + pCoexDm->psTdmaPara[4], psTdmaCase, + (pCoexDm->bCurPsTdmaOn? "On":"Off"), + (pCoexDm->bAutoTdmaAdjust? "Adj":"Fix") ); + + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "Coex Table Type", \ + pCoexSta->nCoexTableType); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "IgnWlanAct", \ + pCoexDm->bCurIgnoreWlanAct); + CL_PRINTF(cliBuf); + + /* + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "Latest error condition(should be 0)", \ + pCoexDm->errorCondition); + CL_PRINTF(cliBuf); + */ + + // Hw setting + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", "backup ARFR1/ARFR2/RL/AMaxTime", \ + pCoexDm->backupArfrCnt1, pCoexDm->backupArfrCnt2, pCoexDm->backupRetryLimit, pCoexDm->backupAmpduMaxTime); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x430); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x434); + u2Tmp[0] = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0x42a); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x456); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", "0x430/0x434/0x42a/0x456", \ + u4Tmp[0], u4Tmp[1], u2Tmp[0], u1Tmp[0]); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x778); + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6cc); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x880); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x778/0x6cc/0x880[29:25]", \ + u1Tmp[0], u4Tmp[0], (u4Tmp[1]&0x3e000000) >> 25); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x948); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x67); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x764); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x76e); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0x948/ 0x67[5] / 0x764 / 0x76e", \ + u4Tmp[0], ((u1Tmp[0]&0x20)>> 5), (u4Tmp[1] & 0xffff), u1Tmp[1]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x92c); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x930); + u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x944); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x92c[1:0]/ 0x930[7:0]/0x944[1:0]", \ + u4Tmp[0]&0x3, u4Tmp[1]&0xff, u4Tmp[2]&0x3); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x39); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x40); + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x4c); + u1Tmp[2] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x64); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0x38[11]/0x40/0x4c[24:23]/0x64[0]", \ + ((u1Tmp[0] & 0x8)>>3), u1Tmp[1], ((u4Tmp[0]&0x01800000)>>23), u1Tmp[2]&0x1); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x550); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x522); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x550(bcn ctrl)/0x522", \ + u4Tmp[0], u1Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc50); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x49c); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0xc50(dig)/0x49c(null-drop)", \ + u4Tmp[0]&0xff, u1Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda0); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda4); + u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda8); + u4Tmp[3] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xcf0); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xa5b); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xa5c); + + faOfdm = ((u4Tmp[0]&0xffff0000) >> 16) + ((u4Tmp[1]&0xffff0000) >> 16) + (u4Tmp[1] & 0xffff) + (u4Tmp[2] & 0xffff) + \ + ((u4Tmp[3]&0xffff0000) >> 16) + (u4Tmp[3] & 0xffff) ; + faCck = (u1Tmp[0] << 8) + u1Tmp[1]; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "OFDM-CCA/OFDM-FA/CCK-FA", \ + u4Tmp[0]&0xffff, faOfdm, faCck); + CL_PRINTF(cliBuf); + + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", "CRC_OK CCK/11g/11n/11n-Agg", \ + pCoexSta->nCRCOK_CCK, pCoexSta->nCRCOK_11g, pCoexSta->nCRCOK_11n, pCoexSta->nCRCOK_11nAgg); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", "CRC_Err CCK/11g/11n/11n-Agg", \ + pCoexSta->nCRCErr_CCK, pCoexSta->nCRCErr_11g, pCoexSta->nCRCErr_11n, pCoexSta->nCRCErr_11nAgg); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c0); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c4); + u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c8); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x6c0/0x6c4/0x6c8(coexTable)", \ + u4Tmp[0], u4Tmp[1], u4Tmp[2]); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x770(high-pri rx/tx)", \ + pCoexSta->highPriorityRx, pCoexSta->highPriorityTx); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x774(low-pri rx/tx)", \ + pCoexSta->lowPriorityRx, pCoexSta->lowPriorityTx); + CL_PRINTF(cliBuf); +#if(BT_AUTO_REPORT_ONLY_8723B_1ANT == 1) + //halbtc8723b1ant_MonitorBtCtr(pBtCoexist); +#endif + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + + +VOID +EXhalbtc8723b1ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + u4Byte u4Tmp=0; + + if(pBtCoexist->bManualControl || pBtCoexist->bStopCoexDm) + return; + + if(BTC_IPS_ENTER == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS ENTER notify\n")); + pCoexSta->bUnderIps = TRUE; + + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + halbtc8723b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FORCE_EXEC, FALSE, TRUE); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + //halbtc8723b1ant_SetAntPathDCut(pBtCoexist, FALSE, FALSE, FALSE, BTC_ANT_PATH_BT, BTC_WIFI_STAT_NORMAL_OFF); + } + else if(BTC_IPS_LEAVE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS LEAVE notify\n")); + + halbtc8723b1ant_InitHwConfig(pBtCoexist, FALSE, FALSE); + halbtc8723b1ant_InitCoexDm(pBtCoexist); + halbtc8723b1ant_QueryBtInfo(pBtCoexist); + + pCoexSta->bUnderIps = FALSE; + } +} + +VOID +EXhalbtc8723b1ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(pBtCoexist->bManualControl || pBtCoexist->bStopCoexDm) + return; + + if(BTC_LPS_ENABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS ENABLE notify\n")); + pCoexSta->bUnderLps = TRUE; + } + else if(BTC_LPS_DISABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS DISABLE notify\n")); + pCoexSta->bUnderLps = FALSE; + } +} + +VOID +EXhalbtc8723b1ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + BOOLEAN bWifiConnected=FALSE, bBtHsOn=FALSE; + u4Byte wifiLinkStatus=0; + u4Byte numOfWifiLink=0; + BOOLEAN bBtCtrlAggBufSize=FALSE; + u1Byte aggBufSize=5; + + u1Byte u1Tmpa, u1Tmpb; + u4Byte u4Tmp; + + if(pBtCoexist->bManualControl || + pBtCoexist->bStopCoexDm ) + return; + + if(BTC_SCAN_START == type) + { + pCoexSta->bWiFiIsHighPriTask = TRUE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n")); + pPsdScan->nAntDet_IsAntDetAvailable = TRUE; + halbtc8723b1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8); //Force antenna setup for no scan result issue + halbtc8723b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, FORCE_EXEC, FALSE, FALSE); + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x948); + u1Tmpa = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x765); + u1Tmpb = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x67); + + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x\n", + u4Tmp, u1Tmpa, u1Tmpb)); + } + else + { + pCoexSta->bWiFiIsHighPriTask = FALSE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n")); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_AP_NUM, &pCoexSta->nScanAPNum); + } + + if(pBtCoexist->btInfo.bBtDisabled) + return; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + + halbtc8723b1ant_QueryBtInfo(pBtCoexist); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_LINK_STATUS, &wifiLinkStatus); + numOfWifiLink = wifiLinkStatus>>16; + if(numOfWifiLink >= 2) + { + halbtc8723b1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8723b1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, bBtCtrlAggBufSize, aggBufSize); + halbtc8723b1ant_ActionWifiMultiPort(pBtCoexist); + return; + } + + if(pCoexSta->bC2hBtInquiryPage) + { + halbtc8723b1ant_ActionBtInquiry(pBtCoexist); + return; + } + else if(bBtHsOn) + { + halbtc8723b1ant_ActionHs(pBtCoexist); + return; + } + + if(BTC_SCAN_START == type) + { + //RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n")); + if(!bWifiConnected) // non-connected scan + { + halbtc8723b1ant_ActionWifiNotConnectedScan(pBtCoexist); + } + else // wifi is connected + { + halbtc8723b1ant_ActionWifiConnectedScan(pBtCoexist); + } + } + else if(BTC_SCAN_FINISH == type) + { + //RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n")); + if(!bWifiConnected) // non-connected scan + { + halbtc8723b1ant_ActionWifiNotConnected(pBtCoexist); + } + else + { + halbtc8723b1ant_ActionWifiConnected(pBtCoexist); + } + } +} + +VOID +EXhalbtc8723b1ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + BOOLEAN bWifiConnected=FALSE, bBtHsOn=FALSE; + u4Byte wifiLinkStatus=0; + u4Byte numOfWifiLink=0; + BOOLEAN bBtCtrlAggBufSize=FALSE; + u1Byte aggBufSize=5; + + if(pBtCoexist->bManualControl || + pBtCoexist->bStopCoexDm || + pBtCoexist->btInfo.bBtDisabled ) + return; + + if(BTC_ASSOCIATE_START == type) + { + pCoexSta->bWiFiIsHighPriTask = TRUE; + pPsdScan->nAntDet_IsAntDetAvailable = TRUE; + halbtc8723b1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8); //Force antenna setup for no scan result issue + halbtc8723b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, FORCE_EXEC, FALSE, FALSE); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n")); + pCoexDm->nArpCnt = 0; + } + else + { + pCoexSta->bWiFiIsHighPriTask = FALSE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n")); + //pCoexDm->nArpCnt = 0; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_LINK_STATUS, &wifiLinkStatus); + numOfWifiLink = wifiLinkStatus>>16; + if(numOfWifiLink >= 2) + { + halbtc8723b1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8723b1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, bBtCtrlAggBufSize, aggBufSize); + halbtc8723b1ant_ActionWifiMultiPort(pBtCoexist); + return; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + if(pCoexSta->bC2hBtInquiryPage) + { + halbtc8723b1ant_ActionBtInquiry(pBtCoexist); + return; + } + else if(bBtHsOn) + { + halbtc8723b1ant_ActionHs(pBtCoexist); + return; + } + + if(BTC_ASSOCIATE_START == type) + { + //RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n")); + halbtc8723b1ant_ActionWifiNotConnectedAssoAuth(pBtCoexist); + } + else if(BTC_ASSOCIATE_FINISH == type) + { + //RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n")); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + if(!bWifiConnected) // non-connected scan + { + halbtc8723b1ant_ActionWifiNotConnected(pBtCoexist); + } + else + { + halbtc8723b1ant_ActionWifiConnected(pBtCoexist); + } + } +} + +VOID +EXhalbtc8723b1ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + u1Byte H2C_Parameter[3] ={0}; + u4Byte wifiBw; + u1Byte wifiCentralChnl; + BOOLEAN bWifiUnderBMode = FALSE; + + if(pBtCoexist->bManualControl || + pBtCoexist->bStopCoexDm || + pBtCoexist->btInfo.bBtDisabled ) + return; + + if(BTC_MEDIA_CONNECT == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA connect notify\n")); + halbtc8723b1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8); //Force antenna setup for no scan result issue + halbtc8723b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, FORCE_EXEC, FALSE, FALSE); + pPsdScan->nAntDet_IsAntDetAvailable = TRUE; + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, &bWifiUnderBMode); + + //Set CCK Tx/Rx high Pri except 11b mode + if (bWifiUnderBMode) + { + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cd, 0x00); //CCK Tx + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cf, 0x00); //CCK Rx + } + else + { + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cd, 0x10); //CCK Tx + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cf, 0x10); //CCK Rx + } + + pCoexDm->backupArfrCnt1 = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x430); + pCoexDm->backupArfrCnt2 = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x434); + pCoexDm->backupRetryLimit = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0x42a); + pCoexDm->backupAmpduMaxTime = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x456); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA disconnect notify\n")); + pCoexDm->nArpCnt = 0; + + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cd, 0x0); //CCK Tx + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cf, 0x0); //CCK Rx + + pCoexSta->bCCKEverLock = FALSE; + } + + // only 2.4G we need to inform bt the chnl mask + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, &wifiCentralChnl); + if( (BTC_MEDIA_CONNECT == type) && + (wifiCentralChnl <= 14) ) + { + //H2C_Parameter[0] = 0x1; + H2C_Parameter[0] = 0x0; + H2C_Parameter[1] = wifiCentralChnl; + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + H2C_Parameter[2] = 0x30; + else + H2C_Parameter[2] = 0x20; + } + + pCoexDm->wifiChnlInfo[0] = H2C_Parameter[0]; + pCoexDm->wifiChnlInfo[1] = H2C_Parameter[1]; + pCoexDm->wifiChnlInfo[2] = H2C_Parameter[2]; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x66=0x%x\n", + H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x66, 3, H2C_Parameter); +} + +VOID +EXhalbtc8723b1ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + BOOLEAN bBtHsOn=FALSE; + u4Byte wifiLinkStatus=0; + u4Byte numOfWifiLink=0; + BOOLEAN bBtCtrlAggBufSize=FALSE, bUnder4way=FALSE; + u1Byte aggBufSize=5; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &bUnder4way); + + if(pBtCoexist->bManualControl || + pBtCoexist->bStopCoexDm || + pBtCoexist->btInfo.bBtDisabled ) + return; + + if( BTC_PACKET_DHCP == type || + BTC_PACKET_EAPOL == type || + BTC_PACKET_ARP == type ) + { + if (BTC_PACKET_ARP == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], special Packet ARP notify\n")); + + pCoexDm->nArpCnt++; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ARP Packet Count = %d\n", pCoexDm->nArpCnt)); + + if((pCoexDm->nArpCnt >= 10) && (!bUnder4way)) // if APR PKT > 10 after connect, do not go to ActionWifiConnectedSpecialPacket(pBtCoexist) + { + pCoexSta->bWiFiIsHighPriTask = FALSE; + } + else + { + pCoexSta->bWiFiIsHighPriTask = TRUE; + } + } + else + { + pCoexSta->bWiFiIsHighPriTask = TRUE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], special Packet DHCP or EAPOL notify\n")); + } + } + else + { + pCoexSta->bWiFiIsHighPriTask = FALSE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], special Packet [Type = %d] notify\n", type)); + } + + pCoexSta->specialPktPeriodCnt = 0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_LINK_STATUS, &wifiLinkStatus); + numOfWifiLink = wifiLinkStatus>>16; + if(numOfWifiLink >= 2) + { + halbtc8723b1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8723b1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, bBtCtrlAggBufSize, aggBufSize); + halbtc8723b1ant_ActionWifiMultiPort(pBtCoexist); + return; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + if(pCoexSta->bC2hBtInquiryPage) + { + halbtc8723b1ant_ActionBtInquiry(pBtCoexist); + return; + } + else if(bBtHsOn) + { + halbtc8723b1ant_ActionHs(pBtCoexist); + return; + } + + if( BTC_PACKET_DHCP == type || + BTC_PACKET_EAPOL == type || + ( (BTC_PACKET_ARP == type ) && (pCoexSta->bWiFiIsHighPriTask) ) ) + { + halbtc8723b1ant_ActionWifiConnectedSpecialPacket(pBtCoexist); + } +} + +VOID +EXhalbtc8723b1ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + u1Byte btInfo=0; + u1Byte i, rspSource=0; + BOOLEAN bWifiConnected=FALSE; + BOOLEAN bBtBusy=FALSE; + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + + pCoexSta->bC2hBtInfoReqSent = FALSE; + + rspSource = tmpBuf[0]&0xf; + if(rspSource >= BT_INFO_SRC_8723B_1ANT_MAX) + rspSource = BT_INFO_SRC_8723B_1ANT_WIFI_FW; + pCoexSta->btInfoC2hCnt[rspSource]++; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Bt info[%d], length=%d, hex data=[", rspSource, length)); + for(i=0; ibtInfoC2h[rspSource][i] = tmpBuf[i]; + if(i == 1) + btInfo = tmpBuf[i]; + if(i == length-1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x]\n", tmpBuf[i])); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x, ", tmpBuf[i])); + } + } + + // if 0xff, it means BT is under WHCK test + if (btInfo == 0xff) + pCoexSta->bBtWhckTest = TRUE; + else + pCoexSta->bBtWhckTest = FALSE; + + if(BT_INFO_SRC_8723B_1ANT_WIFI_FW != rspSource) + { + pCoexSta->btRetryCnt = // [3:0] + pCoexSta->btInfoC2h[rspSource][2]&0xf; + + if (pCoexSta->btRetryCnt >= 1) + pCoexSta->popEventCnt++; + + if (pCoexSta->btInfoC2h[rspSource][2]&0x20) + pCoexSta->bC2hBtRemoteNameReq = TRUE; + else + pCoexSta->bC2hBtRemoteNameReq = FALSE; + + pCoexSta->btRssi = + pCoexSta->btInfoC2h[rspSource][3]*2-90; + //pCoexSta->btInfoC2h[rspSource][3]*2+10; + + pCoexSta->btInfoExt = + pCoexSta->btInfoC2h[rspSource][4]; + + if (pCoexSta->btInfoC2h[rspSource][1] == 0x49) + { + pCoexSta->nA2DPBitPool = + pCoexSta->btInfoC2h[rspSource][6]; + } + else + pCoexSta->nA2DPBitPool = 0; + + pCoexSta->bBtTxRxMask = (pCoexSta->btInfoC2h[rspSource][2]&0x40); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TX_RX_MASK, &pCoexSta->bBtTxRxMask); + +#if BT_8723B_1ANT_ANTDET_ENABLE +#if BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE + if ((pBoardInfo->btdmAntDetFinish) && (pBoardInfo->btdmAntNumByAntDet == 2)) + { + if(pCoexSta->bBtTxRxMask) + { + /* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x1\n")); + + //BT TRx Mask un-lock 0x2c[0], 0x30[0] = 1 + pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x2c, 0x7c45); + pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x30, 0x7c45); + + pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x3c, 0x1); + } + } + else +#endif +#endif + + { + if(!pCoexSta->bBtTxRxMask) + { + /* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x15\n")); + pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x3c, 0x15); + + //BT TRx Mask lock 0x2c[0], 0x30[0] = 0 + pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x2c, 0x7c44); + pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x30, 0x7c44); + } + } + + // Here we need to resend some wifi info to BT + // because bt is reset and loss of the info. + if(pCoexSta->btInfoExt & BIT1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n")); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + if(bWifiConnected) + { + EXhalbtc8723b1ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_CONNECT); + } + else + { + EXhalbtc8723b1ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); + } + } + + if(pCoexSta->btInfoExt & BIT3) + { + if(!pBtCoexist->bManualControl && !pBtCoexist->bStopCoexDm) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n")); + halbtc8723b1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE); + } + } + else + { + // BT already NOT ignore Wlan active, do nothing here. + } +#if(BT_AUTO_REPORT_ONLY_8723B_1ANT == 0) + if( (pCoexSta->btInfoExt & BIT4) ) + { + // BT auto report already enabled, do nothing + } + else + { + halbtc8723b1ant_BtAutoReport(pBtCoexist, FORCE_EXEC, TRUE); + } +#endif + } + + // check BIT2 first ==> check if bt is under inquiry or page scan + if(btInfo & BT_INFO_8723B_1ANT_B_INQ_PAGE) + pCoexSta->bC2hBtInquiryPage = TRUE; + else + pCoexSta->bC2hBtInquiryPage = FALSE; + + pCoexSta->nNumOfProfile = 0; + + // set link exist status + if(!(btInfo&BT_INFO_8723B_1ANT_B_CONNECTION)) + { + pCoexSta->bBtLinkExist = FALSE; + pCoexSta->bPanExist = FALSE; + pCoexSta->bA2dpExist = FALSE; + pCoexSta->bHidExist = FALSE; + pCoexSta->bScoExist = FALSE; + + pCoexSta->bBtHiPriLinkExist = FALSE; + } + else // connection exists + { + pCoexSta->bBtLinkExist = TRUE; + if(btInfo & BT_INFO_8723B_1ANT_B_FTP) + { + pCoexSta->bPanExist = TRUE; + pCoexSta->nNumOfProfile++; + } + else + pCoexSta->bPanExist = FALSE; + if(btInfo & BT_INFO_8723B_1ANT_B_A2DP) + { + pCoexSta->bA2dpExist = TRUE; + pCoexSta->nNumOfProfile++; + } + else + pCoexSta->bA2dpExist = FALSE; + if(btInfo & BT_INFO_8723B_1ANT_B_HID) + { + pCoexSta->bHidExist = TRUE; + pCoexSta->nNumOfProfile++; + } + else + pCoexSta->bHidExist = FALSE; + if(btInfo & BT_INFO_8723B_1ANT_B_SCO_ESCO) + { + pCoexSta->bScoExist = TRUE; + pCoexSta->nNumOfProfile++; + } + else + pCoexSta->bScoExist = FALSE; + + if ((pCoexSta->bHidExist == FALSE) && (pCoexSta->bC2hBtInquiryPage == FALSE) &&( pCoexSta->bScoExist == FALSE)) + { + if (pCoexSta->highPriorityTx + pCoexSta->highPriorityRx >= 160) + { + pCoexSta->bHidExist = TRUE; + pCoexSta->wrongProfileNotification++; + pCoexSta->nNumOfProfile++; + btInfo = btInfo | 0x28; + } + } + + //Add Hi-Pri Tx/Rx counter to avoid false detection + if (((pCoexSta->bHidExist) || (pCoexSta->bScoExist)) && (pCoexSta->highPriorityTx + pCoexSta->highPriorityRx >= 160) + && (!pCoexSta->bC2hBtInquiryPage)) + pCoexSta->bBtHiPriLinkExist = TRUE; + + if((btInfo&BT_INFO_8723B_1ANT_B_ACL_BUSY) && (pCoexSta->nNumOfProfile == 0)) + { + if (pCoexSta->lowPriorityTx + pCoexSta->lowPriorityRx >= 160) + { + pCoexSta->bPanExist = TRUE; + pCoexSta->nNumOfProfile++; + pCoexSta->wrongProfileNotification++; + btInfo = btInfo | 0x88; + } + } + } + + halbtc8723b1ant_UpdateBtLinkInfo(pBtCoexist); + + btInfo = btInfo & 0x1f; //mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) + + if(!(btInfo&BT_INFO_8723B_1ANT_B_CONNECTION)) + { + pCoexDm->btStatus = BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n")); + } + else if(btInfo == BT_INFO_8723B_1ANT_B_CONNECTION) // connection exists but no busy + { + pCoexDm->btStatus = BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n")); + } + else if((btInfo&BT_INFO_8723B_1ANT_B_SCO_ESCO) || + (btInfo&BT_INFO_8723B_1ANT_B_SCO_BUSY)) + { + pCoexDm->btStatus = BT_8723B_1ANT_BT_STATUS_SCO_BUSY; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT SCO busy!!!\n")); + } + else if(btInfo&BT_INFO_8723B_1ANT_B_ACL_BUSY) + { + if(BT_8723B_1ANT_BT_STATUS_ACL_BUSY != pCoexDm->btStatus) + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->btStatus = BT_8723B_1ANT_BT_STATUS_ACL_BUSY; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT ACL busy!!!\n")); + } + else + { + pCoexDm->btStatus = BT_8723B_1ANT_BT_STATUS_MAX; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n")); + } + + if( (BT_8723B_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) || + (BT_8723B_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + bBtBusy = TRUE; + else + bBtBusy = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bBtBusy); + + halbtc8723b1ant_RunCoexistMechanism(pBtCoexist); +} + +VOID +EXhalbtc8723b1ant_RfStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + u4Byte u4Tmp; + u1Byte u1Tmpa,u1Tmpb, u1Tmpc; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RF Status notify\n")); + + if(BTC_RF_ON == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RF is turned ON!!\n")); + pBtCoexist->bStopCoexDm = FALSE; + } + else if(BTC_RF_OFF == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RF is turned OFF!!\n")); + + halbtc8723b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8723b1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); + halbtc8723b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FORCE_EXEC, FALSE, TRUE); + //halbtc8723b1ant_SetAntPathDCut(pBtCoexist, FALSE, FALSE, FALSE, BTC_ANT_PATH_BT, BTC_WIFI_STAT_NORMAL_OFF); + + halbtc8723b1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE); + pBtCoexist->bStopCoexDm = TRUE; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x948); + u1Tmpa = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x765); + u1Tmpb = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x67); + u1Tmpc = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x76e); + + + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x67=0x%x, 0x76e=0x%x\n", + u4Tmp, u1Tmpa, u1Tmpb, u1Tmpc)); + + } +} + +VOID +EXhalbtc8723b1ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte u4Tmp; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Halt notify\n")); + + halbtc8723b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8723b1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); + halbtc8723b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FORCE_EXEC, FALSE, TRUE); + //halbtc8723b1ant_SetAntPathDCut(pBtCoexist, FALSE, FALSE, FALSE, BTC_ANT_PATH_BT, BTC_WIFI_STAT_NORMAL_OFF); + + halbtc8723b1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE); + + EXhalbtc8723b1ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); + + pBtCoexist->bStopCoexDm = TRUE; +} + +VOID +EXhalbtc8723b1ant_PnpNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte pnpState + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Pnp notify\n")); + + if(BTC_WIFI_PNP_SLEEP == pnpState) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Pnp notify to SLEEP\n")); + + halbtc8723b1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8723b1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + halbtc8723b1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FORCE_EXEC, FALSE, TRUE); + halbtc8723b1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + //halbtc8723b1ant_SetAntPathDCut(pBtCoexist, FALSE, FALSE, FALSE, BTC_ANT_PATH_BT, BTC_WIFI_STAT_NORMAL_OFF); + + pBtCoexist->bStopCoexDm = TRUE; + } + else if(BTC_WIFI_PNP_WAKE_UP == pnpState) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Pnp notify to WAKE UP\n")); + pBtCoexist->bStopCoexDm = FALSE; + halbtc8723b1ant_InitHwConfig(pBtCoexist, FALSE, FALSE); + halbtc8723b1ant_InitCoexDm(pBtCoexist); + halbtc8723b1ant_QueryBtInfo(pBtCoexist); + } +} + +VOID +EXhalbtc8723b1ant_CoexDmReset( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], *****************Coex DM Reset*****************\n")); + + halbtc8723b1ant_InitHwConfig(pBtCoexist, FALSE, FALSE); + //pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + //pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x2, 0xfffff, 0x0); + halbtc8723b1ant_InitCoexDm(pBtCoexist); +} + +VOID +EXhalbtc8723b1ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ) +{ + static u1Byte disVerInfoCnt=0; + u4Byte fwVer=0, btPatchVer=0; + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ==========================Periodical===========================\n")); + + if(disVerInfoCnt <= 5) + { + disVerInfoCnt += 1; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ****************************************************************\n")); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Ant PG Num/ Ant Mech/ Ant Pos = %d/ %d/ %d\n", + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum, pBoardInfo->btdmAntPos)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT stack/ hci ext ver = %s / %d\n", + ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion)); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_BT_PATCH_VER, &btPatchVer); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CoexVer/ FwVer/ PatchVer = %d_%x/ 0x%x/ 0x%x(%d)\n", + GLCoexVerDate8723b1Ant, GLCoexVer8723b1Ant, fwVer, btPatchVer, btPatchVer)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ****************************************************************\n")); + } + +#if(BT_AUTO_REPORT_ONLY_8723B_1ANT == 0) + halbtc8723b1ant_QueryBtInfo(pBtCoexist); + halbtc8723b1ant_MonitorBtEnableDisable(pBtCoexist); +#else + halbtc8723b1ant_MonitorBtCtr(pBtCoexist); + halbtc8723b1ant_MonitorWiFiCtr(pBtCoexist); +#if BT_8723B_1ANT_ANTDET_ENABLE + halbtc8723b1ant_MonitorBtEnableDisable(pBtCoexist); +#endif + + if ( (pCoexSta->highPriorityTx + pCoexSta->highPriorityRx < 50) && (pBtLinkInfo->bHidExist == TRUE)) + { + pBtLinkInfo->bHidExist = FALSE; + } + + if( halbtc8723b1ant_IsWifiStatusChanged(pBtCoexist) || + pCoexDm->bAutoTdmaAdjust ) + { + halbtc8723b1ant_RunCoexistMechanism(pBtCoexist); + } + + pCoexSta->specialPktPeriodCnt++; + + // sample to set bt to execute Ant detection + //pBtCoexist->fBtcSetBtAntDetection(pBtCoexist, 20, 14); +/* + if (pPsdScan->bIsAntDetEnable) + { + if (pPsdScan->nPSDGenCount > pPsdScan->realseconds) + pPsdScan->nPSDGenCount = 0; + + halbtc8723b1ant_AntennaDetection(pBtCoexist, pPsdScan->realcentFreq, pPsdScan->realoffset, pPsdScan->realspan, pPsdScan->realseconds); + pPsdScan->nPSDGenTotalCount +=2; + pPsdScan->nPSDGenCount += 2; + } +*/ +#endif +} + +VOID +EXhalbtc8723b1ant_AntennaDetection( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte centFreq, + IN u4Byte offset, + IN u4Byte span, + IN u4Byte seconds + ) +{ + static u4Byte AntDetCount = 0, AntDetFailCount = 0; + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + BOOLEAN bScan, bRoam; + +#if BT_8723B_1ANT_ANTDET_ENABLE + + if (seconds == 0) + { + pPsdScan->bAntDet_TryCount = 0; + pPsdScan->bAntDet_FailCount = 0; + AntDetCount = 0; + AntDetFailCount = 0; + pBoardInfo->btdmAntDetFinish = FALSE; + pBoardInfo->btdmAntNumByAntDet = 1; + return; + } + + if (!pBoardInfo->btdmAntDetFinish) + { + pPsdScan->nAntDet_IntevalCount = pPsdScan->nAntDet_IntevalCount+2; + + if (pPsdScan->nAntDet_IntevalCount >= BT_8723B_1ANT_ANTDET_RETRY_INTERVAL) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is up, Try Detect!!\n")); + halbtc8723b1ant_PSD_AntennaDetectionCheck(pBtCoexist); + + if (pBoardInfo->btdmAntDetFinish) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Success!!\n")); +#if 1 + if (pBoardInfo->btdmAntNumByAntDet == 2) + halbtc8723b1ant_MechanismSwitch(pBtCoexist, TRUE); + else + halbtc8723b1ant_MechanismSwitch(pBtCoexist, FALSE); +#endif + } + else + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Fail!!\n")); + + pPsdScan->nAntDet_IntevalCount = 0; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("xxxxxxxxxxxxxxxx AntennaDetect(), Antenna Det Timer is not up! (%d)\n", pPsdScan->nAntDet_IntevalCount)); + } + + } +#endif + + +/* + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + + + pPsdScan->nAntDet_BTTxTime = seconds; //0.42ms*50 = 20ms + pPsdScan->nAntDet_BTLEChannel = centFreq; + + if (seconds == 0) + { + pPsdScan->bAntDet_TryCount = 0; + pPsdScan->bAntDet_FailCount = 0; + AntDetCount = 0; + AntDetFailCount = 0; + pBoardInfo->btdmAntDetFinish = FALSE; + pBoardInfo->btdmAntNumByAntDet = 1; + return; + } + else + { + AntDetCount++; + + pPsdScan->bAntDet_TryCount = AntDetCount; + + if (bScan ||bRoam) + { + pBoardInfo->btdmAntDetFinish = FALSE; + pPsdScan->nAntDet_Result = 6; + } + else if (pCoexSta->nNumOfProfile >= 1) + { + pBoardInfo->btdmAntDetFinish = FALSE; + pPsdScan->nAntDet_Result = 7; + } + else if (!pPsdScan->nAntDet_IsAntDetAvailable) //Antenna initial setup is not ready + { + pBoardInfo->btdmAntDetFinish = FALSE; + pPsdScan->nAntDet_Result = 9; + } + else if (pCoexSta->bC2hBtInquiryPage) + { + pBoardInfo->btdmAntDetFinish = FALSE; + pPsdScan->nAntDet_Result = 10; + } + else + { + //halbtc8723b1ant_PSD_AntennaDetection(pBtCoexist, pPsdScan->nAntDet_BTTxTime, pPsdScan->nAntDet_BTLEChannel); + } + + if (!pBoardInfo->btdmAntDetFinish) + AntDetFailCount++; + + pPsdScan->bAntDet_FailCount = AntDetFailCount; + } +*/ +} + +VOID +EXhalbtc8723b1ant_AntennaIsolation( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte centFreq, + IN u4Byte offset, + IN u4Byte span, + IN u4Byte seconds + ) +{ + + +} + +VOID +EXhalbtc8723b1ant_PSDScan( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte centFreq, + IN u4Byte offset, + IN u4Byte span, + IN u4Byte seconds + ) +{ + + +} + +VOID +EXhalbtc8723b1ant_DisplayAntDetection( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + +#if BT_8723B_1ANT_ANTDET_ENABLE + if (pPsdScan->bAntDet_TryCount != 0) + { + halbtc8723b1ant_PSD_ShowAntennaDetectResult(pBtCoexist); + + if (pBoardInfo->btdmAntDetFinish) + halbtc8723b1ant_PSD_ShowData(pBtCoexist); + return; + } +#endif + + //halbtc8723b1ant_ShowPSDData(pBtCoexist); +} + + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723b1Ant.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723b1Ant.h new file mode 100644 index 000000000..90a78c819 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723b1Ant.h @@ -0,0 +1,338 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//=========================================== +// The following is for 8723B 1ANT BT Co-exist definition +//=========================================== +#define BT_AUTO_REPORT_ONLY_8723B_1ANT 1 + +#define BT_INFO_8723B_1ANT_B_FTP BIT7 +#define BT_INFO_8723B_1ANT_B_A2DP BIT6 +#define BT_INFO_8723B_1ANT_B_HID BIT5 +#define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT4 +#define BT_INFO_8723B_1ANT_B_ACL_BUSY BIT3 +#define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT2 +#define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT1 +#define BT_INFO_8723B_1ANT_B_CONNECTION BIT0 + +#define BT_INFO_8723B_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ + (((_BT_INFO_EXT_&BIT0))? TRUE:FALSE) + +#define BTC_RSSI_COEX_THRESH_TOL_8723B_1ANT 2 + +#define BT_8723B_1ANT_WIFI_NOISY_THRESH 50 //30 //max: 255 + +//for Antenna detection +#define BT_8723B_1ANT_ANTDET_PSDTHRES_BACKGROUND 50 +#define BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_BADISOLATION 70 +#define BT_8723B_1ANT_ANTDET_PSDTHRES_2ANT_GOODISOLATION 55 +#define BT_8723B_1ANT_ANTDET_PSDTHRES_1ANT 35 +#define BT_8723B_1ANT_ANTDET_RETRY_INTERVAL 10 //retry timer if ant det is fail, unit: second +#define BT_8723B_1ANT_ANTDET_ENABLE 0 +#define BT_8723B_1ANT_ANTDET_COEXMECHANISMSWITCH_ENABLE 0 + +typedef enum _BT_INFO_SRC_8723B_1ANT{ + BT_INFO_SRC_8723B_1ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8723B_1ANT_BT_RSP = 0x1, + BT_INFO_SRC_8723B_1ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8723B_1ANT_MAX +}BT_INFO_SRC_8723B_1ANT,*PBT_INFO_SRC_8723B_1ANT; + +typedef enum _BT_8723B_1ANT_BT_STATUS{ + BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8723B_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8723B_1ANT_BT_STATUS_INQ_PAGE = 0x2, + BT_8723B_1ANT_BT_STATUS_ACL_BUSY = 0x3, + BT_8723B_1ANT_BT_STATUS_SCO_BUSY = 0x4, + BT_8723B_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, + BT_8723B_1ANT_BT_STATUS_MAX +}BT_8723B_1ANT_BT_STATUS,*PBT_8723B_1ANT_BT_STATUS; + +typedef enum _BT_8723B_1ANT_WIFI_STATUS{ + BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8723B_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1, + BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2, + BT_8723B_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3, + BT_8723B_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4, + BT_8723B_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5, + BT_8723B_1ANT_WIFI_STATUS_MAX +}BT_8723B_1ANT_WIFI_STATUS,*PBT_8723B_1ANT_WIFI_STATUS; + +typedef enum _BT_8723B_1ANT_COEX_ALGO{ + BT_8723B_1ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8723B_1ANT_COEX_ALGO_SCO = 0x1, + BT_8723B_1ANT_COEX_ALGO_HID = 0x2, + BT_8723B_1ANT_COEX_ALGO_A2DP = 0x3, + BT_8723B_1ANT_COEX_ALGO_A2DP_PANHS = 0x4, + BT_8723B_1ANT_COEX_ALGO_PANEDR = 0x5, + BT_8723B_1ANT_COEX_ALGO_PANHS = 0x6, + BT_8723B_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7, + BT_8723B_1ANT_COEX_ALGO_PANEDR_HID = 0x8, + BT_8723B_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, + BT_8723B_1ANT_COEX_ALGO_HID_A2DP = 0xa, + BT_8723B_1ANT_COEX_ALGO_MAX = 0xb, +}BT_8723B_1ANT_COEX_ALGO,*PBT_8723B_1ANT_COEX_ALGO; + +typedef struct _COEX_DM_8723B_1ANT{ + // hw setting + u1Byte preAntPosType; + u1Byte curAntPosType; + // fw mechanism + BOOLEAN bCurIgnoreWlanAct; + BOOLEAN bPreIgnoreWlanAct; + u1Byte prePsTdma; + u1Byte curPsTdma; + u1Byte psTdmaPara[5]; + u1Byte psTdmaDuAdjType; + BOOLEAN bAutoTdmaAdjust; + BOOLEAN bPrePsTdmaOn; + BOOLEAN bCurPsTdmaOn; + BOOLEAN bPreBtAutoReport; + BOOLEAN bCurBtAutoReport; + u1Byte preLps; + u1Byte curLps; + u1Byte preRpwm; + u1Byte curRpwm; + + // sw mechanism + BOOLEAN bPreLowPenaltyRa; + BOOLEAN bCurLowPenaltyRa; + u4Byte preVal0x6c0; + u4Byte curVal0x6c0; + u4Byte preVal0x6c4; + u4Byte curVal0x6c4; + u4Byte preVal0x6c8; + u4Byte curVal0x6c8; + u1Byte preVal0x6cc; + u1Byte curVal0x6cc; + BOOLEAN bLimitedDig; + + u4Byte backupArfrCnt1; // Auto Rate Fallback Retry cnt + u4Byte backupArfrCnt2; // Auto Rate Fallback Retry cnt + u2Byte backupRetryLimit; + u1Byte backupAmpduMaxTime; + + // algorithm related + u1Byte preAlgorithm; + u1Byte curAlgorithm; + u1Byte btStatus; + u1Byte wifiChnlInfo[3]; + + u4Byte preRaMask; + u4Byte curRaMask; + u1Byte preArfrType; + u1Byte curArfrType; + u1Byte preRetryLimitType; + u1Byte curRetryLimitType; + u1Byte preAmpduTimeType; + u1Byte curAmpduTimeType; + u4Byte nArpCnt; + + u1Byte errorCondition; +} COEX_DM_8723B_1ANT, *PCOEX_DM_8723B_1ANT; + +typedef struct _COEX_STA_8723B_1ANT{ + BOOLEAN bBtLinkExist; + BOOLEAN bScoExist; + BOOLEAN bA2dpExist; + BOOLEAN bHidExist; + BOOLEAN bPanExist; + BOOLEAN bBtHiPriLinkExist; + u1Byte nNumOfProfile; + + BOOLEAN bUnderLps; + BOOLEAN bUnderIps; + u4Byte specialPktPeriodCnt; + u4Byte highPriorityTx; + u4Byte highPriorityRx; + u4Byte lowPriorityTx; + u4Byte lowPriorityRx; + s1Byte btRssi; + BOOLEAN bBtTxRxMask; + u1Byte preBtRssiState; + u1Byte preWifiRssiState[4]; + BOOLEAN bC2hBtInfoReqSent; + u1Byte btInfoC2h[BT_INFO_SRC_8723B_1ANT_MAX][10]; + u4Byte btInfoC2hCnt[BT_INFO_SRC_8723B_1ANT_MAX]; + BOOLEAN bBtWhckTest; + BOOLEAN bC2hBtInquiryPage; + BOOLEAN bC2hBtRemoteNameReq; + BOOLEAN bWiFiIsHighPriTask; //Add for win8.1 page out issue + u1Byte btRetryCnt; + u1Byte btInfoExt; + u4Byte popEventCnt; + u1Byte nScanAPNum; + + u4Byte nCRCOK_CCK; + u4Byte nCRCOK_11g; + u4Byte nCRCOK_11n; + u4Byte nCRCOK_11nAgg; + + u4Byte nCRCErr_CCK; + u4Byte nCRCErr_11g; + u4Byte nCRCErr_11n; + u4Byte nCRCErr_11nAgg; + + BOOLEAN bCCKLock; + BOOLEAN bPreCCKLock; + BOOLEAN bCCKEverLock; + u1Byte nCoexTableType; + + BOOLEAN bForceLpsOn; + u4Byte wrongProfileNotification; + + u1Byte nA2DPBitPool; + u1Byte nCutVersion; +}COEX_STA_8723B_1ANT, *PCOEX_STA_8723B_1ANT; + +#define BT_8723B_1ANT_ANTDET_PSD_POINTS 256 //MAX:1024 +#define BT_8723B_1ANT_ANTDET_PSD_AVGNUM 1 //MAX:3 +#define BT_8723B_1ANT_ANTDET_BUF_LEN 16 + +typedef struct _PSDSCAN_STA_8723B_1ANT{ + +u4Byte nAntDet_BTLEChannel; //BT LE Channel ex:2412 +u4Byte nAntDet_BTTxTime; +u4Byte nAntDet_PrePSDScanPeakVal; +BOOLEAN nAntDet_IsAntDetAvailable; +u4Byte nAntDet_PSDScanPeakVal; +BOOLEAN nAntDet_IsBTReplyAvailable; +u4Byte nAntDet_PSDScanPeakFreq; + +u1Byte nAntDet_Result; +u1Byte nAntDet_PeakVal[BT_8723B_1ANT_ANTDET_BUF_LEN]; +u1Byte nAntDet_PeakFreq[BT_8723B_1ANT_ANTDET_BUF_LEN]; +u4Byte bAntDet_TryCount; +u4Byte bAntDet_FailCount; +u4Byte nAntDet_IntevalCount; +u4Byte nAntDet_ThresOffset; + +u4Byte nRealCentFreq; +s4Byte nRealOffset; +u4Byte nRealSpan; + +u4Byte nPSDBandWidth; //unit: Hz +u4Byte nPSDPoint; //128/256/512/1024 +u4Byte nPSDReport[1024]; //unit:dB (20logx), 0~255 +u4Byte nPSDReport_MaxHold[1024]; //unit:dB (20logx), 0~255 +u4Byte nPSDStartPoint; +u4Byte nPSDStopPoint; +u4Byte nPSDMaxValuePoint; +u4Byte nPSDMaxValue; +u4Byte nPSDStartBase; +u4Byte nPSDAvgNum; // 1/8/16/32 +u4Byte nPSDGenCount; +BOOLEAN bIsPSDRunning; +BOOLEAN bIsPSDShowMaxOnly; +} PSDSCAN_STA_8723B_1ANT, *PPSDSCAN_STA_8723B_1ANT; + +//=========================================== +// The following is interface which will notify coex module. +//=========================================== +VOID +EXhalbtc8723b1ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8723b1ant_PreLoadFirmware( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8723b1ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ); +VOID +EXhalbtc8723b1ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8723b1ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8723b1ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8723b1ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8723b1ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8723b1ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8723b1ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8723b1ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ); +VOID +EXhalbtc8723b1ant_RfStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8723b1ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8723b1ant_PnpNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte pnpState + ); +VOID +EXhalbtc8723b1ant_CoexDmReset( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8723b1ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8723b1ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8723b1ant_AntennaDetection( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte centFreq, + IN u4Byte offset, + IN u4Byte span, + IN u4Byte seconds + ); +VOID +EXhalbtc8723b1ant_AntennaIsolation( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte centFreq, + IN u4Byte offset, + IN u4Byte span, + IN u4Byte seconds + ); + +VOID +EXhalbtc8723b1ant_PSDScan( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte centFreq, + IN u4Byte offset, + IN u4Byte span, + IN u4Byte seconds + ); +VOID +EXhalbtc8723b1ant_DisplayAntDetection( + IN PBTC_COEXIST pBtCoexist + ); + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723b2Ant.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723b2Ant.c new file mode 100644 index 000000000..4c77b6102 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723b2Ant.c @@ -0,0 +1,4934 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//============================================================ +// Description: +// +// This file is for RTL8723B Co-exist mechanism +// +// History +// 2012/11/15 Cosa first check in. +// +//============================================================ + +//============================================================ +// include files +//============================================================ +#include "Mp_Precomp.h" + +#if WPP_SOFTWARE_TRACE +#include "HalBtc8723b2Ant.tmh" +#endif + +#if(BT_30_SUPPORT == 1) +//============================================================ +// Global variables, these are static variables +//============================================================ +static COEX_DM_8723B_2ANT GLCoexDm8723b2Ant; +static PCOEX_DM_8723B_2ANT pCoexDm=&GLCoexDm8723b2Ant; +static COEX_STA_8723B_2ANT GLCoexSta8723b2Ant; +static PCOEX_STA_8723B_2ANT pCoexSta=&GLCoexSta8723b2Ant; + +const char *const GLBtInfoSrc8723b2Ant[]={ + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; + +u4Byte GLCoexVerDate8723b2Ant=20150119; +u4Byte GLCoexVer8723b2Ant=0x44; + +//============================================================ +// local function proto type if needed +//============================================================ +//============================================================ +// local function start with halbtc8723b2ant_ +//============================================================ +u1Byte +halbtc8723b2ant_BtRssiState( + u1Byte levelNum, + u1Byte rssiThresh, + u1Byte rssiThresh1 + ) +{ + s4Byte btRssi=0; + u1Byte btRssiState=pCoexSta->preBtRssiState; + + btRssi = pCoexSta->btRssi; + + if(levelNum == 2) + { + if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW)) + { + if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) + { + btRssiState = BTC_RSSI_STATE_HIGH; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else + { + if(btRssi < rssiThresh) + { + btRssiState = BTC_RSSI_STATE_LOW; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + else if(levelNum == 3) + { + if(rssiThresh > rssiThresh1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Rssi thresh error!!\n")); + return pCoexSta->preBtRssiState; + } + + if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW)) + { + if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) + { + btRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_MEDIUM) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_MEDIUM)) + { + if(btRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) + { + btRssiState = BTC_RSSI_STATE_HIGH; + } + else if(btRssi < rssiThresh) + { + btRssiState = BTC_RSSI_STATE_LOW; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_MEDIUM; + } + } + else + { + if(btRssi < rssiThresh1) + { + btRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + + pCoexSta->preBtRssiState = btRssiState; + + return btRssiState; +} + +u1Byte +halbtc8723b2ant_WifiRssiState( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte index, + IN u1Byte levelNum, + IN u1Byte rssiThresh, + IN u1Byte rssiThresh1 + ) +{ + s4Byte wifiRssi=0; + u1Byte wifiRssiState=pCoexSta->preWifiRssiState[index]; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); + + if(levelNum == 2) + { + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else + { + if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + else if(levelNum == 3) + { + if(rssiThresh > rssiThresh1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi RSSI thresh error!!\n")); + return pCoexSta->preWifiRssiState[index]; + } + + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_MEDIUM) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_MEDIUM)) + { + if(wifiRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_MEDIUM; + } + } + else + { + if(wifiRssi < rssiThresh1) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + + pCoexSta->preWifiRssiState[index] = wifiRssiState; + + return wifiRssiState; +} + +VOID +halbtc8723b2ant_MonitorBtEnableDisable( + IN PBTC_COEXIST pBtCoexist + ) +{ + static BOOLEAN bPreBtDisabled=FALSE; + static u4Byte btDisableCnt=0; + BOOLEAN bBtActive=TRUE, bBtDisabled=FALSE; + + // This function check if bt is disabled + + if( pCoexSta->highPriorityTx == 0 && + pCoexSta->highPriorityRx == 0 && + pCoexSta->lowPriorityTx == 0 && + pCoexSta->lowPriorityRx == 0) + { + bBtActive = FALSE; + } + if( pCoexSta->highPriorityTx == 0xffff && + pCoexSta->highPriorityRx == 0xffff && + pCoexSta->lowPriorityTx == 0xffff && + pCoexSta->lowPriorityRx == 0xffff) + { + bBtActive = FALSE; + } + if(bBtActive) + { + btDisableCnt = 0; + bBtDisabled = FALSE; + } + else + { + btDisableCnt++; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], bt all counters=0, %d times!!\n", btDisableCnt)); + if(btDisableCnt >= 2) + { + bBtDisabled = TRUE; + } + } + if(bPreBtDisabled != bBtDisabled) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is from %s to %s!!\n", (bPreBtDisabled ? "disabled":"enabled"), + (bBtDisabled ? "disabled":"enabled"))); + + bPreBtDisabled = bBtDisabled; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); + if(bBtDisabled) + { + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_LEAVE_LPS, NULL); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_NORMAL_LPS, NULL); + } + } +} + + +VOID +halbtc8723b2ant_LimitedRx( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bRejApAggPkt, + IN BOOLEAN bBtCtrlAggBufSize, + IN u1Byte aggBufSize + ) +{ + BOOLEAN bRejectRxAgg=bRejApAggPkt; + BOOLEAN bBtCtrlRxAggSize=bBtCtrlAggBufSize; + u1Byte rxAggSize=aggBufSize; + + //============================================ + // Rx Aggregation related setting + //============================================ + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, &bRejectRxAgg); + // decide BT control aggregation buf size or not + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, &bBtCtrlRxAggSize); + // aggregation buf size, only work when BT control Rx aggregation size. + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_AGG_BUF_SIZE, &rxAggSize); + // real update aggregation setting + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); +} + +VOID +halbtc8723b2ant_MonitorBtCtr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte regHPTxRx, regLPTxRx, u4Tmp; + u4Byte regHPTx=0, regHPRx=0, regLPTx=0, regLPRx=0; + u1Byte u1Tmp; + + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + + regHPTxRx = 0x770; + regLPTxRx = 0x774; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regHPTxRx); + regHPTx = u4Tmp & bMaskLWord; + regHPRx = (u4Tmp & bMaskHWord)>>16; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regLPTxRx); + regLPTx = u4Tmp & bMaskLWord; + regLPRx = (u4Tmp & bMaskHWord)>>16; + + pCoexSta->highPriorityTx = regHPTx; + pCoexSta->highPriorityRx = regHPRx; + pCoexSta->lowPriorityTx = regLPTx; + pCoexSta->lowPriorityRx = regLPRx; + + if( (pCoexSta->lowPriorityTx > 1050) && (!pCoexSta->bC2hBtInquiryPage)) + pCoexSta->popEventCnt++; + + if ( (pCoexSta->lowPriorityRx >= 950) && (pCoexSta->lowPriorityRx >= pCoexSta->lowPriorityTx) && (!pCoexSta->bUnderIps) ) + { + pBtLinkInfo->bSlaveRole = TRUE; + } + else + { + pBtLinkInfo->bSlaveRole = FALSE; + } + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", + regHPTxRx, regHPTx, regHPTx, regHPRx, regHPRx)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", + regLPTxRx, regLPTx, regLPTx, regLPRx, regLPRx)); + + // reset counter + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0xc); +} + +VOID +halbtc8723b2ant_MonitorWiFiCtr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte u4Tmp; + u2Byte u2Tmp[3]; + s4Byte wifiRssi=0; + BOOLEAN bWifiBusy = FALSE, bWifiUnderBMode = FALSE; + static u1Byte nCCKLockCounter = 0; + + + if (pCoexSta->bUnderIps) + { + pCoexSta->nCRCOK_CCK = 0; + pCoexSta->nCRCOK_11g = 0; + pCoexSta->nCRCOK_11n = 0; + pCoexSta->nCRCOK_11nAgg = 0; + + pCoexSta->nCRCErr_CCK = 0; + pCoexSta->nCRCErr_11g = 0; + pCoexSta->nCRCErr_11n = 0; + pCoexSta->nCRCErr_11nAgg = 0; + } + else + { + pCoexSta->nCRCOK_CCK = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xf88); + pCoexSta->nCRCOK_11g = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf94); + pCoexSta->nCRCOK_11n = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf90); + pCoexSta->nCRCOK_11nAgg= pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xfb8); + + pCoexSta->nCRCErr_CCK = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xf84); + pCoexSta->nCRCErr_11g = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf96); + pCoexSta->nCRCErr_11n = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf92); + pCoexSta->nCRCErr_11nAgg = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xfba); + } + + //reset counter + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xf16, 0x1, 0x1); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xf16, 0x1, 0x0); +} + +VOID +halbtc8723b2ant_QueryBtInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + pCoexSta->bC2hBtInfoReqSent = TRUE; + + H2C_Parameter[0] |= BIT0; // trigger + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Query Bt Info, FW write 0x61=0x%x\n", + H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x61, 1, H2C_Parameter); +} + +BOOLEAN +halbtc8723b2ant_IsWifiStatusChanged( + IN PBTC_COEXIST pBtCoexist + ) +{ + static BOOLEAN bPreWifiBusy=FALSE, bPreUnder4way=FALSE, bPreBtHsOn=FALSE; + BOOLEAN bWifiBusy=FALSE, bUnder4way=FALSE, bBtHsOn=FALSE; + BOOLEAN bWifiConnected=FALSE; + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH; + + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &bUnder4way); + + if(bWifiConnected) + { + if(bWifiBusy != bPreWifiBusy) + { + bPreWifiBusy = bWifiBusy; + return TRUE; + } + if(bUnder4way != bPreUnder4way) + { + bPreUnder4way = bUnder4way; + return TRUE; + } + if(bBtHsOn != bPreBtHsOn) + { + bPreBtHsOn = bBtHsOn; + return TRUE; + } + + + wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist,3, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + + if ( (BTC_RSSI_STATE_HIGH ==wifiRssiState ) || (BTC_RSSI_STATE_LOW ==wifiRssiState )) + { + return TRUE; + } + + } + + return FALSE; +} + +VOID +halbtc8723b2ant_UpdateBtLinkInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bBtHsOn=FALSE; + +#if(BT_AUTO_REPORT_ONLY_8723B_2ANT == 1) // profile from bt patch + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + pBtLinkInfo->bBtLinkExist = pCoexSta->bBtLinkExist; + pBtLinkInfo->bScoExist = pCoexSta->bScoExist; + pBtLinkInfo->bA2dpExist = pCoexSta->bA2dpExist; + pBtLinkInfo->bPanExist = pCoexSta->bPanExist; + pBtLinkInfo->bHidExist = pCoexSta->bHidExist; + + // work around for HS mode. + if(bBtHsOn) + { + pBtLinkInfo->bPanExist = TRUE; + pBtLinkInfo->bBtLinkExist = TRUE; + } +#else // profile from bt stack + pBtLinkInfo->bBtLinkExist = pStackInfo->bBtLinkExist; + pBtLinkInfo->bScoExist = pStackInfo->bScoExist; + pBtLinkInfo->bA2dpExist = pStackInfo->bA2dpExist; + pBtLinkInfo->bPanExist = pStackInfo->bPanExist; + pBtLinkInfo->bHidExist = pStackInfo->bHidExist; + + //for win-8 stack HID report error + if(!pStackInfo->bHidExist) + pStackInfo->bHidExist = pCoexSta->bHidExist; //sync BTInfo with BT firmware and stack + // when stack HID report error, here we use the info from bt fw. + if(!pStackInfo->bBtLinkExist) + pStackInfo->bBtLinkExist = pCoexSta->bBtLinkExist; +#endif + // check if Sco only + if( pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bScoOnly = TRUE; + else + pBtLinkInfo->bScoOnly = FALSE; + + // check if A2dp only + if( !pBtLinkInfo->bScoExist && + pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bA2dpOnly = TRUE; + else + pBtLinkInfo->bA2dpOnly = FALSE; + + // check if Pan only + if( !pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bPanOnly = TRUE; + else + pBtLinkInfo->bPanOnly = FALSE; + + // check if Hid only + if( !pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + pBtLinkInfo->bHidExist ) + pBtLinkInfo->bHidOnly = TRUE; + else + pBtLinkInfo->bHidOnly = FALSE; +} + +u1Byte +halbtc8723b2ant_ActionAlgorithm( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bBtHsOn=FALSE; + u1Byte algorithm=BT_8723B_2ANT_COEX_ALGO_UNDEFINED; + u1Byte numOfDiffProfile=0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + if(!pBtLinkInfo->bBtLinkExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], No BT link exists!!!\n")); + return algorithm; + } + + if(pBtLinkInfo->bScoExist) + numOfDiffProfile++; + if(pBtLinkInfo->bHidExist) + numOfDiffProfile++; + if(pBtLinkInfo->bPanExist) + numOfDiffProfile++; + if(pBtLinkInfo->bA2dpExist) + numOfDiffProfile++; + + if(numOfDiffProfile == 1) + { + if(pBtLinkInfo->bScoExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO only\n")); + algorithm = BT_8723B_2ANT_COEX_ALGO_SCO; + } + else + { + if(pBtLinkInfo->bHidExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID only\n")); + algorithm = BT_8723B_2ANT_COEX_ALGO_HID; + } + else if(pBtLinkInfo->bA2dpExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP only\n")); + algorithm = BT_8723B_2ANT_COEX_ALGO_A2DP; + } + else if(pBtLinkInfo->bPanExist) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN(HS) only\n")); + algorithm = BT_8723B_2ANT_COEX_ALGO_PANHS; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN(EDR) only\n")); + algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR; + } + } + } + } + else if(numOfDiffProfile == 2) + { + if(pBtLinkInfo->bScoExist) + { + if(pBtLinkInfo->bHidExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID\n")); + algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; + } + else if(pBtLinkInfo->bA2dpExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + A2DP ==> SCO\n")); + algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; + } + else if(pBtLinkInfo->bPanExist) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + PAN(HS)\n")); + algorithm = BT_8723B_2ANT_COEX_ALGO_SCO; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + PAN(EDR)\n")); + algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; + } + } + } + else + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bA2dpExist ) + { +#if 0 + if(pStackInfo->numOfHid >= 2) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID*2 + A2DP\n")); + algorithm = BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + else +#endif + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP\n")); + algorithm = BT_8723B_2ANT_COEX_ALGO_HID_A2DP; + } + } + else if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + PAN(HS)\n")); + algorithm = BT_8723B_2ANT_COEX_ALGO_HID; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + PAN(EDR)\n")); + algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; + } + } + else if( pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP + PAN(HS)\n")); + algorithm = BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP + PAN(EDR)\n")); + algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } + } + else if(numOfDiffProfile == 3) + { + if(pBtLinkInfo->bScoExist) + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bA2dpExist ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + A2DP ==> HID\n")); + algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; + } + else if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + PAN(HS)\n")); + algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + PAN(EDR)\n")); + algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; + } + } + else if( pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + A2DP + PAN(HS)\n")); + algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n")); + algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; + } + } + } + else + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP + PAN(HS)\n")); + algorithm = BT_8723B_2ANT_COEX_ALGO_HID_A2DP; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP + PAN(EDR)\n")); + algorithm = BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } + else if(numOfDiffProfile >= 3) + { + if(pBtLinkInfo->bScoExist) + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n")); + + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n")); + algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; + } + } + } + } + + return algorithm; +} + +VOID +halbtc8723b2ant_SetFwDacSwingLevel( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte dacSwingLvl + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + // There are several type of dacswing + // 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 + H2C_Parameter[0] = dacSwingLvl; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Set Dac Swing Level=0x%x\n", dacSwingLvl)); + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x64=0x%x\n", H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x64, 1, H2C_Parameter); +} + +VOID +halbtc8723b2ant_SetFwDecBtPwr( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte decBtPwrLvl + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + H2C_Parameter[0] = decBtPwrLvl; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], decrease Bt Power level = %d, FW write 0x62=0x%x\n", + decBtPwrLvl, H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x62, 1, H2C_Parameter); +} + +VOID +halbtc8723b2ant_DecBtPwr( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte decBtPwrLvl + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s Dec BT power level = %d\n", + (bForceExec? "force to":""), decBtPwrLvl)); + pCoexDm->curBtDecPwrLvl = decBtPwrLvl; + + if(!bForceExec) + { + if(pCoexDm->preBtDecPwrLvl == pCoexDm->curBtDecPwrLvl) + return; + } + halbtc8723b2ant_SetFwDecBtPwr(pBtCoexist, pCoexDm->curBtDecPwrLvl); + + pCoexDm->preBtDecPwrLvl = pCoexDm->curBtDecPwrLvl; +} + +VOID +halbtc8723b2ant_SetBtAutoReport( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bEnableAutoReport + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + H2C_Parameter[0] = 0; + + if(bEnableAutoReport) + { + H2C_Parameter[0] |= BIT0; + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], BT FW auto report : %s, FW write 0x68=0x%x\n", + (bEnableAutoReport? "Enabled!!":"Disabled!!"), H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x68, 1, H2C_Parameter); +} + +VOID +halbtc8723b2ant_BtAutoReport( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bEnableAutoReport + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s BT Auto report = %s\n", + (bForceExec? "force to":""), ((bEnableAutoReport)? "Enabled":"Disabled"))); + pCoexDm->bCurBtAutoReport = bEnableAutoReport; + + if(!bForceExec) + { + if(pCoexDm->bPreBtAutoReport == pCoexDm->bCurBtAutoReport) + return; + } + halbtc8723b2ant_SetBtAutoReport(pBtCoexist, pCoexDm->bCurBtAutoReport); + + pCoexDm->bPreBtAutoReport = pCoexDm->bCurBtAutoReport; +} + +VOID +halbtc8723b2ant_FwDacSwingLvl( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte fwDacSwingLvl + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s set FW Dac Swing level = %d\n", + (bForceExec? "force to":""), fwDacSwingLvl)); + pCoexDm->curFwDacSwingLvl = fwDacSwingLvl; + + if(!bForceExec) + { + if(pCoexDm->preFwDacSwingLvl == pCoexDm->curFwDacSwingLvl) + return; + } + + halbtc8723b2ant_SetFwDacSwingLevel(pBtCoexist, pCoexDm->curFwDacSwingLvl); + + pCoexDm->preFwDacSwingLvl = pCoexDm->curFwDacSwingLvl; +} + +VOID +halbtc8723b2ant_SetSwRfRxLpfCorner( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bRxRfShrinkOn + ) +{ + if(bRxRfShrinkOn) + { + //Shrink RF Rx LPF corner + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Shrink RF Rx LPF corner!!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, 0xffffc); + } + else + { + //Resume RF Rx LPF corner + // After initialized, we can use pCoexDm->btRf0x1eBackup + if(pBtCoexist->bInitilized) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Resume RF Rx LPF corner!!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, pCoexDm->btRf0x1eBackup); + } + } +} + +VOID +halbtc8723b2ant_RfShrink( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bRxRfShrinkOn + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Rx RF Shrink = %s\n", + (bForceExec? "force to":""), ((bRxRfShrinkOn)? "ON":"OFF"))); + pCoexDm->bCurRfRxLpfShrink = bRxRfShrinkOn; + + if(!bForceExec) + { + if(pCoexDm->bPreRfRxLpfShrink == pCoexDm->bCurRfRxLpfShrink) + return; + } + halbtc8723b2ant_SetSwRfRxLpfCorner(pBtCoexist, pCoexDm->bCurRfRxLpfShrink); + + pCoexDm->bPreRfRxLpfShrink = pCoexDm->bCurRfRxLpfShrink; +} + +VOID +halbtc8723b2ant_SetSwPenaltyTxRateAdaptive( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bLowPenaltyRa + ) +{ + u1Byte H2C_Parameter[6] ={0}; + + H2C_Parameter[0] = 0x6; // opCode, 0x6= Retry_Penalty + + if(bLowPenaltyRa) + { + H2C_Parameter[1] |= BIT0; + H2C_Parameter[2] = 0x00; //normal rate except MCS7/6/5, OFDM54/48/36 + H2C_Parameter[3] = 0xf7; //MCS7 or OFDM54 + H2C_Parameter[4] = 0xf8; //MCS6 or OFDM48 + H2C_Parameter[5] = 0xf9; //MCS5 or OFDM36 + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set WiFi Low-Penalty Retry: %s", + (bLowPenaltyRa? "ON!!":"OFF!!")) ); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x69, 6, H2C_Parameter); +} + +VOID +halbtc8723b2ant_LowPenaltyRa( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bLowPenaltyRa + ) +{ + //return; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn LowPenaltyRA = %s\n", + (bForceExec? "force to":""), ((bLowPenaltyRa)? "ON":"OFF"))); + pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa; + + if(!bForceExec) + { + if(pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa) + return; + } + halbtc8723b2ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa); + + pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa; +} + +VOID +halbtc8723b2ant_SetDacSwingReg( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte level + ) +{ + u1Byte val=(u1Byte)level; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Write SwDacSwing = 0x%x\n", level)); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x883, 0x3e, val); +} + +VOID +halbtc8723b2ant_SetSwFullTimeDacSwing( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bSwDacSwingOn, + IN u4Byte swDacSwingLvl + ) +{ + if(bSwDacSwingOn) + { + halbtc8723b2ant_SetDacSwingReg(pBtCoexist, swDacSwingLvl); + } + else + { + halbtc8723b2ant_SetDacSwingReg(pBtCoexist, 0x18); + } +} + + +VOID +halbtc8723b2ant_DacSwing( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bDacSwingOn, + IN u4Byte dacSwingLvl + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn DacSwing=%s, dacSwingLvl=0x%x\n", + (bForceExec? "force to":""), ((bDacSwingOn)? "ON":"OFF"), dacSwingLvl)); + pCoexDm->bCurDacSwingOn = bDacSwingOn; + pCoexDm->curDacSwingLvl = dacSwingLvl; + + if(!bForceExec) + { + if( (pCoexDm->bPreDacSwingOn == pCoexDm->bCurDacSwingOn) && + (pCoexDm->preDacSwingLvl == pCoexDm->curDacSwingLvl) ) + return; + } + delay_ms(30); + halbtc8723b2ant_SetSwFullTimeDacSwing(pBtCoexist, bDacSwingOn, dacSwingLvl); + + pCoexDm->bPreDacSwingOn = pCoexDm->bCurDacSwingOn; + pCoexDm->preDacSwingLvl = pCoexDm->curDacSwingLvl; +} + +VOID +halbtc8723b2ant_SetAdcBackOff( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bAdcBackOff + ) +{ + if(bAdcBackOff) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level On!\n")); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xc05, 0x30, 0x3); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level Off!\n")); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xc05, 0x30, 0x1); + } +} + +VOID +halbtc8723b2ant_AdcBackOff( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bAdcBackOff + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn AdcBackOff = %s\n", + (bForceExec? "force to":""), ((bAdcBackOff)? "ON":"OFF"))); + pCoexDm->bCurAdcBackOff = bAdcBackOff; + + if(!bForceExec) + { + if(pCoexDm->bPreAdcBackOff == pCoexDm->bCurAdcBackOff) + return; + } + halbtc8723b2ant_SetAdcBackOff(pBtCoexist, pCoexDm->bCurAdcBackOff); + + pCoexDm->bPreAdcBackOff = pCoexDm->bCurAdcBackOff; +} + +VOID +halbtc8723b2ant_SetAgcTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bAgcTableEn + ) +{ + u1Byte rssiAdjustVal=0; + + //=================BB AGC Gain Table + if(bAgcTableEn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB Agc Table On!\n")); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6e1A0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6d1B0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6c1C0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6b1D0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6a1E0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x691F0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x68200001); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB Agc Table Off!\n")); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xaa1A0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa91B0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa81C0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa71D0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa61E0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa51F0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa4200001); + } + + + //=================RF Gain + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000); + if(bAgcTableEn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table On!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x38fff); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x38ffe); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table Off!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x380c3); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x28ce6); + } + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xef, 0xfffff, 0x0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xed, 0xfffff, 0x1); + if(bAgcTableEn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table On!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x40, 0xfffff, 0x38fff); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x40, 0xfffff, 0x38ffe); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table Off!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x40, 0xfffff, 0x380c3); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x40, 0xfffff, 0x28ce6); + } + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xed, 0xfffff, 0x0); + + // set rssiAdjustVal for wifi module. + if(bAgcTableEn) + { + rssiAdjustVal = 8; + } + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, &rssiAdjustVal); +} + +VOID +halbtc8723b2ant_AgcTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bAgcTableEn + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s %s Agc Table\n", + (bForceExec? "force to":""), ((bAgcTableEn)? "Enable":"Disable"))); + pCoexDm->bCurAgcTableEn = bAgcTableEn; + + if(!bForceExec) + { + if(pCoexDm->bPreAgcTableEn == pCoexDm->bCurAgcTableEn) + return; + } + halbtc8723b2ant_SetAgcTable(pBtCoexist, bAgcTableEn); + + pCoexDm->bPreAgcTableEn = pCoexDm->bCurAgcTableEn; +} + +VOID +halbtc8723b2ant_SetCoexTable( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte val0x6c0, + IN u4Byte val0x6c4, + IN u4Byte val0x6c8, + IN u1Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c0=0x%x\n", val0x6c0)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c0, val0x6c0); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c4=0x%x\n", val0x6c4)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c4, val0x6c4); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, val0x6c8); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc)); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cc, val0x6cc); +} + +VOID +halbtc8723b2ant_CoexTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u4Byte val0x6c0, + IN u4Byte val0x6c4, + IN u4Byte val0x6c8, + IN u1Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s write Coex Table 0x6c0=0x%x, 0x6c4=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n", + (bForceExec? "force to":""), val0x6c0, val0x6c4, val0x6c8, val0x6cc)); + pCoexDm->curVal0x6c0 = val0x6c0; + pCoexDm->curVal0x6c4 = val0x6c4; + pCoexDm->curVal0x6c8 = val0x6c8; + pCoexDm->curVal0x6cc = val0x6cc; + + if(!bForceExec) + { + if( (pCoexDm->preVal0x6c0 == pCoexDm->curVal0x6c0) && + (pCoexDm->preVal0x6c4 == pCoexDm->curVal0x6c4) && + (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) && + (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) ) + return; + } + halbtc8723b2ant_SetCoexTable(pBtCoexist, val0x6c0, val0x6c4, val0x6c8, val0x6cc); + + pCoexDm->preVal0x6c0 = pCoexDm->curVal0x6c0; + pCoexDm->preVal0x6c4 = pCoexDm->curVal0x6c4; + pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8; + pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc; +} + +VOID +halbtc8723b2ant_CoexTableWithType( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + pCoexSta->nCoexTableType = type; + + switch(type) + { + case 0: + halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x55555555, 0xffffff, 0x3); + break; + case 1: + halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x5afa5afa, 0xffffff, 0x3); + break; + case 2: + halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x5ada5ada, 0x5ada5ada, 0xffffff, 0x3); + break; + case 3: + halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3); + break; + case 4: + halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0xffffffff, 0xffffffff, 0xffffff, 0x3); + break; + case 5: + halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x5fff5fff, 0x5fff5fff, 0xffffff, 0x3); + break; + case 6: + halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x55ff55ff, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 7: + halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 8: + halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 9: + halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 10: + halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 11: + halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 12: + halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 13: + halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x5fff5fff, 0xaaaaaaaa, 0xffffff, 0x3); + break; + case 14: + halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x5fff5fff, 0x5ada5ada, 0xffffff, 0x3); + break; + case 15: + halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0xaaaaaaaa, 0xffffff, 0x3); + break; + default: + break; + } +} + +VOID +halbtc8723b2ant_SetFwIgnoreWlanAct( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bEnable + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + if(bEnable) + { + H2C_Parameter[0] |= BIT0; // function enable + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set FW for BT Ignore Wlan_Act, FW write 0x63=0x%x\n", + H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x63, 1, H2C_Parameter); +} + +VOID +halbtc8723b2ant_SetLpsRpwm( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + u1Byte lps=lpsVal; + u1Byte rpwm=rpwmVal; + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_LPS_VAL, &lps); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RPWM_VAL, &rpwm); +} + +VOID +halbtc8723b2ant_LpsRpwm( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + BOOLEAN bForceExecPwrCmd=FALSE; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s set lps/rpwm=0x%x/0x%x \n", + (bForceExec? "force to":""), lpsVal, rpwmVal)); + pCoexDm->curLps = lpsVal; + pCoexDm->curRpwm = rpwmVal; + + if(!bForceExec) + { + if( (pCoexDm->preLps == pCoexDm->curLps) && + (pCoexDm->preRpwm == pCoexDm->curRpwm) ) + { + return; + } + } + halbtc8723b2ant_SetLpsRpwm(pBtCoexist, lpsVal, rpwmVal); + + pCoexDm->preLps = pCoexDm->curLps; + pCoexDm->preRpwm = pCoexDm->curRpwm; +} + +VOID +halbtc8723b2ant_IgnoreWlanAct( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bEnable + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Ignore WlanAct %s\n", + (bForceExec? "force to":""), (bEnable? "ON":"OFF"))); + pCoexDm->bCurIgnoreWlanAct = bEnable; + + if(!bForceExec) + { + if(pCoexDm->bPreIgnoreWlanAct == pCoexDm->bCurIgnoreWlanAct) + return; + } + halbtc8723b2ant_SetFwIgnoreWlanAct(pBtCoexist, bEnable); + + pCoexDm->bPreIgnoreWlanAct = pCoexDm->bCurIgnoreWlanAct; +} + +VOID +halbtc8723b2ant_SetFwPstdma( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte byte1, + IN u1Byte byte2, + IN u1Byte byte3, + IN u1Byte byte4, + IN u1Byte byte5 + ) +{ + u1Byte H2C_Parameter[5] ={0}; + + + if ( (pCoexSta->bA2dpExist) && (pCoexSta->bHidExist) ) + { + byte5 = byte5 | 0x1; + } + + H2C_Parameter[0] = byte1; + H2C_Parameter[1] = byte2; + H2C_Parameter[2] = byte3; + H2C_Parameter[3] = byte4; + H2C_Parameter[4] = byte5; + + pCoexDm->psTdmaPara[0] = byte1; + pCoexDm->psTdmaPara[1] = byte2; + pCoexDm->psTdmaPara[2] = byte3; + pCoexDm->psTdmaPara[3] = byte4; + pCoexDm->psTdmaPara[4] = byte5; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x60(5bytes)=0x%x%08x\n", + H2C_Parameter[0], + H2C_Parameter[1]<<24|H2C_Parameter[2]<<16|H2C_Parameter[3]<<8|H2C_Parameter[4])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x60, 5, H2C_Parameter); +} + +VOID +halbtc8723b2ant_SwMechanism1( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bShrinkRxLPF, + IN BOOLEAN bLowPenaltyRA, + IN BOOLEAN bLimitedDIG, + IN BOOLEAN bBTLNAConstrain + ) +{ + /* + u4Byte wifiBw; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if(BTC_WIFI_BW_HT40 != wifiBw) //only shrink RF Rx LPF for HT40 + { + if (bShrinkRxLPF) + bShrinkRxLPF = FALSE; + } + */ + + //halbtc8723b2ant_RfShrink(pBtCoexist, NORMAL_EXEC, bShrinkRxLPF); + halbtc8723b2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, bLowPenaltyRA); +} + +VOID +halbtc8723b2ant_SwMechanism2( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bAGCTableShift, + IN BOOLEAN bADCBackOff, + IN BOOLEAN bSWDACSwing, + IN u4Byte dacSwingLvl + ) +{ + //halbtc8723b2ant_AgcTable(pBtCoexist, NORMAL_EXEC, bAGCTableShift); + //halbtc8723b2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, bADCBackOff); + //halbtc8723b2ant_DacSwing(pBtCoexist, NORMAL_EXEC, bSWDACSwing, dacSwingLvl); +} + +VOID +halbtc8723b2ant_SetAntPath( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte antPosType, + IN BOOLEAN bInitHwCfg, + IN BOOLEAN bWifiOff + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + u4Byte fwVer=0, u4Tmp=0; + BOOLEAN bPgExtSwitch=FALSE; + BOOLEAN bUseExtSwitch=FALSE; + u1Byte H2C_Parameter[2] ={0}; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_EXT_SWITCH, &bPgExtSwitch); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); // [31:16]=fw ver, [15:0]=fw sub ver + + if((fwVer>0 && fwVer<0xc0000) || bPgExtSwitch) + bUseExtSwitch = TRUE; + + if(bInitHwCfg) + { + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x39, 0x8, 0x1); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x974, 0xff); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x944, 0x3, 0x3); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x930, 0x77); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x67, 0x20, 0x1); + + if(fwVer >= 0x180000) + { + /* Use H2C to set GNT_BT to High to avoid A2DP click */ + H2C_Parameter[0] = 1; + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x6E, 1, H2C_Parameter); + } + else + { + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x765, 0x18); + } + + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); //WiFi TRx Mask off + //remove due to interrupt is disabled that polling c2h will fail and delay 100ms. + //pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x3c, 0x01); //BT TRx Mask off + + if(pBoardInfo->btdmAntPos == BTC_ANTENNA_AT_MAIN_PORT) + { + //tell firmware "no antenna inverse" + H2C_Parameter[0] = 0; + } + else + { + //tell firmware "antenna inverse" + H2C_Parameter[0] = 1; + } + + if (bUseExtSwitch) + { + //ext switch type + H2C_Parameter[1] = 1; + } + else + { + //int switch type + H2C_Parameter[1] = 0; + } + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x65, 2, H2C_Parameter); + } + else + { + if(fwVer >= 0x180000) + { + /* Use H2C to set GNT_BT to "Control by PTA"*/ + H2C_Parameter[0] = 0; + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x6E, 1, H2C_Parameter); + } + else + { + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x765, 0x0); + } + } + + // ext switch setting + if(bUseExtSwitch) + { + if (bInitHwCfg) + { + // 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x4c); + u4Tmp &=~BIT23; + u4Tmp |= BIT24; + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x4c, u4Tmp); + } + + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x0); // fixed internal switch S1->WiFi, S0->BT + switch(antPosType) + { + case BTC_ANT_WIFI_AT_MAIN: + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x92c, 0x3, 0x1); // ext switch main at wifi + break; + case BTC_ANT_WIFI_AT_AUX: + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x92c, 0x3, 0x2); // ext switch aux at wifi + break; + } + } + else // internal switch + { + if (bInitHwCfg) + { + // 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x4c); + u4Tmp |= BIT23; + u4Tmp &=~BIT24; + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x4c, u4Tmp); + } + + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x64, 0x1, 0x0); //fixed external switch S1->Main, S0->Aux + switch(antPosType) + { + case BTC_ANT_WIFI_AT_MAIN: + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x0); // fixed internal switch S1->WiFi, S0->BT + break; + case BTC_ANT_WIFI_AT_AUX: + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x280); // fixed internal switch S0->WiFi, S1->BT + break; + } + } +} + +VOID +halbtc8723b2ant_PsTdma( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bTurnOn, + IN u1Byte type + ) +{ + BOOLEAN bTurnOnByCnt=FALSE; + u1Byte psTdmaTypeByCnt=0; + u1Byte wifiRssiState1, btRssiState; + s1Byte nWiFiDurationAdjust = 0x0; + u1Byte psTdmaByte4Modify = 0x0; + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + + + wifiRssiState1 = halbtc8723b2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8723b2ant_BtRssiState(2, BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], %s turn %s PS TDMA, type=%d\n", + (bForceExec? "force to":""), (bTurnOn? "ON":"OFF"), type)); + pCoexDm->bCurPsTdmaOn = bTurnOn; + pCoexDm->curPsTdma = type; + + if (!(BTC_RSSI_HIGH(wifiRssiState1) && BTC_RSSI_HIGH(btRssiState)) && bTurnOn) + { + type = type +100; //for WiFi RSSI low or BT RSSI low + pCoexDm->bIsSwitchTo1dot5Ant = TRUE; + } + else + { + pCoexDm->bIsSwitchTo1dot5Ant = FALSE; + } + + + if(!bForceExec) + { + if( (pCoexDm->bPrePsTdmaOn == pCoexDm->bCurPsTdmaOn) && + (pCoexDm->prePsTdma == pCoexDm->curPsTdma) ) + return; + } + + if (pCoexSta->nScanAPNum <= 5) + { + if (pCoexSta->nA2DPBitPool >= 45) + nWiFiDurationAdjust = -15; + else if (pCoexSta->nA2DPBitPool >= 35) + nWiFiDurationAdjust = -10; + else + nWiFiDurationAdjust = 5; + } + else if (pCoexSta->nScanAPNum <= 20) + { + if (pCoexSta->nA2DPBitPool >= 45) + nWiFiDurationAdjust = -15; + else if (pCoexSta->nA2DPBitPool >= 35) + nWiFiDurationAdjust = -10; + else + nWiFiDurationAdjust = 0; + } + else if (pCoexSta->nScanAPNum <= 40) + { + if (pCoexSta->nA2DPBitPool >= 45) + nWiFiDurationAdjust = -15; + else if (pCoexSta->nA2DPBitPool >= 35) + nWiFiDurationAdjust = -10; + else + nWiFiDurationAdjust = -5; + } + else + { + if (pCoexSta->nA2DPBitPool >= 45) + nWiFiDurationAdjust = -15; + else if (pCoexSta->nA2DPBitPool >= 35) + nWiFiDurationAdjust = -10; + else + nWiFiDurationAdjust = -10; + } + + if ( (pBtLinkInfo->bSlaveRole == TRUE) && (pBtLinkInfo->bA2dpExist) ) + psTdmaByte4Modify = 0x1; //0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) + + + if(bTurnOn) + { + switch(type) + { + case 1: + default: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x3c+nWiFiDurationAdjust, 0x03, 0xf1, 0x90|psTdmaByte4Modify); + break; + case 2: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x2d+nWiFiDurationAdjust, 0x03, 0xf1, 0x90|psTdmaByte4Modify); + break; + case 3: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1c, 0x3, 0xf1, 0x90|psTdmaByte4Modify); + break; + case 4: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x10, 0x03, 0xf1, 0x90|psTdmaByte4Modify); + break; + case 5: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x3c+nWiFiDurationAdjust, 0x3, 0x70, 0x90|psTdmaByte4Modify); + break; + case 6: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x2d+nWiFiDurationAdjust, 0x3, 0x70, 0x90|psTdmaByte4Modify); + break; + case 7: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1c, 0x3, 0x70, 0x90|psTdmaByte4Modify); + break; + case 8: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xa3, 0x10, 0x3, 0x70, 0x90|psTdmaByte4Modify); + break; + case 9: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x3c+nWiFiDurationAdjust, 0x03, 0xf1, 0x90|psTdmaByte4Modify); + break; + case 10: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x2d+nWiFiDurationAdjust, 0x03, 0xf1, 0x90|psTdmaByte4Modify); + break; + case 11: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1c, 0x3, 0xf1, 0x90|psTdmaByte4Modify); + break; + case 12: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x10, 0x3, 0xf1, 0x90|psTdmaByte4Modify); + break; + case 13: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x3c+nWiFiDurationAdjust, 0x3, 0x70, 0x90|psTdmaByte4Modify); + break; + case 14: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x2d+nWiFiDurationAdjust, 0x3, 0x70, 0x90|psTdmaByte4Modify); + break; + case 15: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1c, 0x3, 0x70, 0x90|psTdmaByte4Modify); + break; + case 16: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x10, 0x3, 0x70, 0x90|psTdmaByte4Modify); + break; + case 17: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xa3, 0x2f, 0x2f, 0x60, 0x90); + break; + case 18: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0xe1, 0x90); + break; + case 19: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x25, 0xe1, 0x90); + break; + case 20: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x25, 0x60, 0x90); + break; + case 21: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x15, 0x03, 0x70, 0x90); + break; + case 71: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x3c+nWiFiDurationAdjust, 0x03, 0xf1, 0x90); + break; + case 101: + case 105: + case 171: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xd3, 0x3a+nWiFiDurationAdjust, 0x03, 0x70, 0x50|psTdmaByte4Modify); + break; + case 102: + case 106: + case 110: + case 114: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xd3, 0x2d+nWiFiDurationAdjust, 0x03, 0x70, 0x50|psTdmaByte4Modify); + break; + case 103: + case 107: + case 111: + case 115: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xd3, 0x1c, 0x03, 0x70, 0x50|psTdmaByte4Modify); + break; + case 104: + case 108: + case 112: + case 116: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xd3, 0x10, 0x03, 0x70, 0x50|psTdmaByte4Modify); + break; + case 109: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x3c, 0x03, 0xf1, 0x90|psTdmaByte4Modify); + break; + case 113: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x3c, 0x03, 0x70, 0x90|psTdmaByte4Modify); + break; + case 121: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x15, 0x03, 0x70, 0x90|psTdmaByte4Modify); + break; + case 22: + case 122: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x35, 0x03, 0x71, 0x11); + break; + } + } + else + { + // disable PS tdma + switch(type) + { + case 0: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x40, 0x0); + break; + case 1: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x48, 0x0); + break; + default: + halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x40, 0x0); + break; + } + } + + // update pre state + pCoexDm->bPrePsTdmaOn = pCoexDm->bCurPsTdmaOn; + pCoexDm->prePsTdma = pCoexDm->curPsTdma; +} + +VOID +halbtc8723b2ant_PsTdmaCheckForPowerSaveState( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bNewPsState + ) +{ + u1Byte lpsMode=0x0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_LPS_MODE, &lpsMode); + + if(lpsMode) // already under LPS state + { + if(bNewPsState) + { + // keep state under LPS, do nothing. + } + else + { + // will leave LPS state, turn off psTdma first + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + } + } + else // NO PS state + { + if(bNewPsState) + { + // will enter LPS state, turn off psTdma first + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + } + else + { + // keep state under NO PS state, do nothing. + } + } +} + +VOID +halbtc8723b2ant_PowerSaveState( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte psType, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + BOOLEAN bLowPwrDisable=FALSE; + + switch(psType) + { + case BTC_PS_WIFI_NATIVE: + // recover to original 32k low power setting + bLowPwrDisable = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_NORMAL_LPS, NULL); + pCoexSta->bForceLpsOn = FALSE; + break; + case BTC_PS_LPS_ON: + halbtc8723b2ant_PsTdmaCheckForPowerSaveState(pBtCoexist, TRUE); + halbtc8723b2ant_LpsRpwm(pBtCoexist, NORMAL_EXEC, lpsVal, rpwmVal); + // when coex force to enter LPS, do not enter 32k low power. + bLowPwrDisable = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + // power save must executed before psTdma. + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_ENTER_LPS, NULL); + pCoexSta->bForceLpsOn = TRUE; + break; + case BTC_PS_LPS_OFF: + halbtc8723b2ant_PsTdmaCheckForPowerSaveState(pBtCoexist, FALSE); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_LEAVE_LPS, NULL); + pCoexSta->bForceLpsOn = FALSE; + break; + default: + break; + } +} + + +VOID +halbtc8723b2ant_CoexAllOff( + IN PBTC_COEXIST pBtCoexist + ) +{ + // fw all off + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + // sw all off + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + // hw all off + //pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); +} + +VOID +halbtc8723b2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + // force to reset coex mechanism + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8723b2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); + halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, FORCE_EXEC, 6); + halbtc8723b2ant_DecBtPwr(pBtCoexist, FORCE_EXEC, 0); + + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + pCoexSta->popEventCnt = 0; + +} + +VOID +halbtc8723b2ant_ActionBtInquiry( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btRssiState; + BOOLEAN bWifiConnected=FALSE; + BOOLEAN bLowPwrDisable=TRUE; + BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE; + + + wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + wifiRssiState1 = halbtc8723b2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8723b2ant_BtRssiState(2, BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + + + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + if(bScan || bLink || bRoam) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi link process + BT Inq/Page!!\n")); + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 15); + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 22); + } + else if(bWifiConnected) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi connected + BT Inq/Page!!\n")); + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 15); + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 22); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi no-link + BT Inq/Page!!\n")); + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + } + + halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, FORCE_EXEC, 6); + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); +/* + pCoexDm->bNeedRecover0x948 = TRUE; + pCoexDm->backup0x948 = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x948); + + halbtc8723b2ant_SetAntPath(pBtCoexist, BTC_ANT_WIFI_AT_AUX, FALSE, FALSE); +*/ +} + + +VOID +halbtc8723b2ant_ActionWiFiLinkProcess( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte u4Tmp; + u1Byte u1Tmpa, u1Tmpb; + + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 15); + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 22); + + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x948); + u1Tmpa = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x765); + u1Tmpb = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x76e); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x76e=0x%x\n", + u4Tmp, u1Tmpa, u1Tmpb)); +} + +BOOLEAN +halbtc8723b2ant_ActionWifiIdleProcess( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btRssiState; + u4Byte wifiBw; + u1Byte apNum=0; + + wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + //wifiRssiState1 = halbtc8723b2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + wifiRssiState1 = halbtc8723b2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES-20, 0); + btRssiState = halbtc8723b2ant_BtRssiState(2, BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_AP_NUM, &apNum); + + // define the office environment + if(BTC_RSSI_HIGH(wifiRssiState1) && + (pCoexSta->bHidExist == TRUE) && (pCoexSta->bA2dpExist == TRUE)) + { + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi idle process for BT HID+A2DP exist!!\n")); + + halbtc8723b2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x6); + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + // sw all off + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + + return TRUE; + } + else + { + halbtc8723b2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); + return FALSE; + } + + +} + + + +BOOLEAN +halbtc8723b2ant_IsCommonAction( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte btRssiState=BTC_RSSI_STATE_HIGH; + BOOLEAN bCommon=FALSE, bWifiConnected=FALSE, bWifiBusy=FALSE; + BOOLEAN bBtHsOn=FALSE, bLowPwrDisable=FALSE; + BOOLEAN bAsus8723b=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + + if(!bWifiConnected) + { + bLowPwrDisable = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non-connected idle!!\n")); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + bCommon = TRUE; + } + else + { + if(BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus) + { + bLowPwrDisable = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi connected + BT non connected-idle!!\n")); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0xb); + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + bCommon = TRUE; + } + else if(BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) + { + bLowPwrDisable = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + + if(bBtHsOn) + return FALSE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi connected + BT connected-idle!!\n")); + halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0xb); + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8723b2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + bCommon = TRUE; + } + else + { + bLowPwrDisable = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + + if(bWifiBusy) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi Connected-Busy + BT Busy!!\n")); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_IS_ASUS_8723B, &bAsus8723b); + if(!bAsus8723b) + bCommon = FALSE; + else + bCommon = halbtc8723b2ant_ActionWifiIdleProcess(pBtCoexist); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi Connected-Idle + BT Busy!!\n")); + //bCommon = FALSE; + bCommon = halbtc8723b2ant_ActionWifiIdleProcess(pBtCoexist); + } + } + } + + return bCommon; +} +VOID +halbtc8723b2ant_TdmaDurationAdjust( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bScoHid, + IN BOOLEAN bTxPause, + IN u1Byte maxInterval + ) +{ + static s4Byte up,dn,m,n,WaitCount; + s4Byte result; //0: no change, +1: increase WiFi duration, -1: decrease WiFi duration + u1Byte retryCount=0; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TdmaDurationAdjust()\n")); + + if(!pCoexDm->bAutoTdmaAdjust) + { + pCoexDm->bAutoTdmaAdjust = TRUE; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], first run TdmaDurationAdjust()!!\n")); + { + if(bScoHid) + { + if(bTxPause) + { + if(maxInterval == 1) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + pCoexDm->psTdmaDuAdjType = 13; + } + else if(maxInterval == 2) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(maxInterval == 3) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + } + else + { + if(maxInterval == 1) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(maxInterval == 2) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(maxInterval == 3) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + } + } + else + { + if(bTxPause) + { + if(maxInterval == 1) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + pCoexDm->psTdmaDuAdjType = 5; + } + else if(maxInterval == 2) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(maxInterval == 3) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + } + else + { + if(maxInterval == 1) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + else if(maxInterval == 2) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(maxInterval == 3) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + } + } + } + //============ + up = 0; + dn = 0; + m = 1; + n= 3; + result = 0; + WaitCount = 0; + } + else + { + //accquire the BT TRx retry count from BT_Info byte2 + retryCount = pCoexSta->btRetryCnt; + + if ( (pCoexSta->lowPriorityTx) > 1050 || (pCoexSta->lowPriorityRx) > 1250 ) + retryCount++; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], retryCount = %d\n", retryCount)); + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], up=%d, dn=%d, m=%d, n=%d, WaitCount=%d\n", + up, dn, m, n, WaitCount)); + result = 0; + WaitCount++; + + if(retryCount == 0) // no retry in the last 2-second duration + { + up++; + dn--; + + if (dn <= 0) + dn = 0; + + if(up >= n) // if s n 2 retry count0, hռeWiFi duration + { + WaitCount = 0; + n = 3; + up = 0; + dn = 0; + result = 1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Increase wifi duration!!\n")); + } + } + else if (retryCount <= 3) // <=3 retry in the last 2-second duration + { + up--; + dn++; + + if (up <= 0) + up = 0; + + if (dn == 2) // if s 2 2 retry count< 3, hկWiFi duration + { + if (WaitCount <= 2) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter<3!!\n")); + } + } + else //retry count > 3, un1 retry count > 3, hկWiFi duration + { + if (WaitCount == 1) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter>3!!\n")); + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], max Interval = %d\n", maxInterval)); + if(maxInterval == 1) + { + if(bTxPause) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 1\n")); + + if(pCoexDm->curPsTdma == 71) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + pCoexDm->psTdmaDuAdjType = 5; + } + else if(pCoexDm->curPsTdma == 1) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + pCoexDm->psTdmaDuAdjType = 5; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 4) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + if(pCoexDm->curPsTdma == 9) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + pCoexDm->psTdmaDuAdjType = 13; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + + if(result == -1) + { + if(pCoexDm->curPsTdma == 5) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + else if(pCoexDm->curPsTdma == 13) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 8) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + pCoexDm->psTdmaDuAdjType = 5; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + pCoexDm->psTdmaDuAdjType = 13; + } + } + } + else + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 0\n")); + if(pCoexDm->curPsTdma == 5) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 71); + pCoexDm->psTdmaDuAdjType = 71; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 8) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + if(pCoexDm->curPsTdma == 13) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + + if(result == -1) + { + if(pCoexDm->curPsTdma == 71) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + else if(pCoexDm->curPsTdma == 1) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 4) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + else if(pCoexDm->curPsTdma == 1) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 71); + pCoexDm->psTdmaDuAdjType = 71; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + } + } + } + else if(maxInterval == 2) + { + if(bTxPause) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 1\n")); + if(pCoexDm->curPsTdma == 1) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 4) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + if(pCoexDm->curPsTdma == 9) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 5) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + else if(pCoexDm->curPsTdma == 13) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 8) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + } + } + else + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 0\n")); + if(pCoexDm->curPsTdma == 5) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 8) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + if(pCoexDm->curPsTdma == 13) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 1) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 4) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + } + } + } + else if(maxInterval == 3) + { + if(bTxPause) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 1\n")); + if(pCoexDm->curPsTdma == 1) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 4) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + if(pCoexDm->curPsTdma == 9) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 5) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + else if(pCoexDm->curPsTdma == 13) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 8) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + } + } + else + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 0\n")); + if(pCoexDm->curPsTdma == 5) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 8) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + if(pCoexDm->curPsTdma == 13) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 1) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 4) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + } + } + } + } + + // if current PsTdma not match with the recorded one (when scan, dhcp...), + // then we have to adjust it back to the previous record one. + if(pCoexDm->curPsTdma != pCoexDm->psTdmaDuAdjType) + { + BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PsTdma type dismatch!!!, curPsTdma=%d, recordPsTdma=%d\n", + pCoexDm->curPsTdma, pCoexDm->psTdmaDuAdjType)); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + + if( !bScan && !bLink && !bRoam) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, pCoexDm->psTdmaDuAdjType); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n")); + } + } +} + +// SCO only or SCO+PAN(HS) +VOID +halbtc8723b2ant_ActionSco( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + btRssiState = halbtc8723b2ant_BtRssiState(2, BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 4); + + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if (BTC_WIFI_BW_LEGACY == wifiBw) //for SCO quality at 11b/g mode + { + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + } + else //for SCO quality & wifi performance balance at 11n mode + { + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 8); + } + + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); //for voice quality + + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,TRUE,0x4); + } + else + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,TRUE,0x4); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,TRUE,0x4); + } + else + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,TRUE,0x4); + } + } +} + + +VOID +halbtc8723b2ant_ActionHid( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + btRssiState = halbtc8723b2ant_BtRssiState(2, BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if (BTC_WIFI_BW_LEGACY == wifiBw) //for HID at 11b/g mode + { + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + else //for HID quality & wifi performance balance at 11n mode + { + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 9); + } + + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + } + else + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + } + + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +//A2DP only / PAN(EDR) only/ A2DP+PAN(HS) +VOID +halbtc8723b2ant_ActionA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btRssiState; + u4Byte wifiBw; + u1Byte apNum=0; + + wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + wifiRssiState1 = halbtc8723b2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8723b2ant_BtRssiState(2, BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_AP_NUM, &apNum); + + // define the office environment + if( (apNum >= 10) && BTC_RSSI_HIGH(wifiRssiState1) && BTC_RSSI_HIGH(btRssiState)) + { + //DbgPrint(" AP#>10(%d)\n", apNum); + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + + // sw mechanism + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,TRUE,0x18); + } + else + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,TRUE,0x18); + } + return; + + } + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + + if (BTC_RSSI_HIGH(wifiRssiState1) && BTC_RSSI_HIGH(btRssiState)) + { + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } + else + { + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 13); + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + } + + + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 1); + } + else + { + halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 1); + } + + // sw mechanism + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +VOID +halbtc8723b2ant_ActionA2dpPanHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + wifiRssiState1 = halbtc8723b2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8723b2ant_BtRssiState(2, BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifiRssiState1) && BTC_RSSI_HIGH(btRssiState)) + { + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } + else + { + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 13); + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + } + + halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 2); + + // sw mechanism + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +VOID +halbtc8723b2ant_ActionPanEdr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState,wifiRssiState1, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + wifiRssiState1 = halbtc8723b2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8723b2ant_BtRssiState(2, BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifiRssiState1) && BTC_RSSI_HIGH(btRssiState)) + { + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 10); + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } + else + { + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 13); + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + } + + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + } + else + { + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + } + + // sw mechanism + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + + +//PAN(HS) only +VOID +halbtc8723b2ant_ActionPanHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + wifiRssiState1 = halbtc8723b2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8723b2ant_BtRssiState(2, BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +//PAN(EDR)+A2DP +VOID +halbtc8723b2ant_ActionPanEdrA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + wifiRssiState1 = halbtc8723b2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8723b2ant_BtRssiState(2, BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifiRssiState1) && BTC_RSSI_HIGH(btRssiState)) + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 12); + + if(BTC_WIFI_BW_HT40 == wifiBw) + halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 3); + else + halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 3); + } + else + { + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 13); + halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 3); + } + + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +VOID +halbtc8723b2ant_ActionPanEdrHid( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + wifiRssiState1 = halbtc8723b2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8723b2ant_BtRssiState(2, BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifiRssiState1) && BTC_RSSI_HIGH(btRssiState)) + { + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } + else + { + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 14); + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + } + + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + if(BTC_WIFI_BW_HT40 == wifiBw) + { + halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 3); + //halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 11); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x780); + } + else + { + halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + //halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + } + halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 2); + } + else + { + halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + //halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 14); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 2); + } + + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +// HID+A2DP+PAN(EDR) +VOID +halbtc8723b2ant_ActionHidA2dpPanEdr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState,wifiRssiState1, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + wifiRssiState1 = halbtc8723b2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8723b2ant_BtRssiState(2, BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifiRssiState1) && BTC_RSSI_HIGH(btRssiState)) + { + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } + else + { + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 14); + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + if(BTC_WIFI_BW_HT40 == wifiBw) + halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 3); + else + halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 3); + } + else + { + halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 3); + } + + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +VOID +halbtc8723b2ant_ActionHidA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btRssiState; + u4Byte wifiBw; + u1Byte apNum=0; + + wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + //btRssiState = halbtc8723b2ant_BtRssiState(2, 29, 0); + wifiRssiState1 = halbtc8723b2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8723b2ant_BtRssiState(3, BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES, 37); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, TRUE, 0x5); + + halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_LEGACY == wifiBw) + { + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else if(BTC_RSSI_MEDIUM(btRssiState)) + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + } + else + { // only 802.11N mode we have to dec bt power to 4 degree + if(BTC_RSSI_HIGH(btRssiState)) + { + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_AP_NUM, &apNum); + // need to check ap Number of Not + if(apNum < 10) + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 4); + else + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + } + else if(BTC_RSSI_MEDIUM(btRssiState)) + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + } + + if (BTC_RSSI_HIGH(wifiRssiState1) && BTC_RSSI_HIGH(btRssiState)) + { + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } + else + { + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 14); + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + } + + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 3); + } + else + { + halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 3); + } + + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +VOID +halbtc8723b2ant_ActionBtWhckTest( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + // sw all off + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); +} + +VOID +halbtc8723b2ant_ActionWifiMultiPort( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + // sw all off + halbtc8723b2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8723b2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + // hw all off + //pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8723b2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); +} + +VOID +halbtc8723b2ant_RunCoexistMechanism( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bWifiUnder5G=FALSE, bBtHsOn=FALSE; + u1Byte btInfoOriginal=0, btRetryCnt=0; + u1Byte algorithm=0; + u4Byte numOfWifiLink=0; + u4Byte wifiLinkStatus=0; + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bMiracastPlusBt=FALSE; + BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism()===>\n")); + + if(pBtCoexist->bManualControl) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n")); + return; + } + + if(pCoexSta->bUnderIps) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi is under IPS !!!\n")); + return; + } + + if(pCoexSta->bBtWhckTest) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is under WHCK TEST!!!\n")); + halbtc8723b2ant_ActionBtWhckTest(pBtCoexist); + return; + } + + algorithm = halbtc8723b2ant_ActionAlgorithm(pBtCoexist); + if(pCoexSta->bC2hBtInquiryPage && (BT_8723B_2ANT_COEX_ALGO_PANHS!=algorithm)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is under inquiry/page scan !!\n")); + halbtc8723b2ant_ActionBtInquiry(pBtCoexist); + return; + } + else + { + /* + if(pCoexDm->bNeedRecover0x948) + { + pCoexDm->bNeedRecover0x948 = FALSE; + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, pCoexDm->backup0x948); + } + */ + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + + if(bScan || bLink || bRoam) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], WiFi is under Link Process !!\n")); + halbtc8723b2ant_ActionWiFiLinkProcess(pBtCoexist); + return; + } + + //for P2P + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_LINK_STATUS, &wifiLinkStatus); + numOfWifiLink = wifiLinkStatus>>16; + + if((numOfWifiLink>=2) || (wifiLinkStatus&WIFI_P2P_GO_CONNECTED)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], Multi-Port numOfWifiLink = %d, wifiLinkStatus = 0x%x\n", numOfWifiLink,wifiLinkStatus) ); + + if(pBtLinkInfo->bBtLinkExist) + { + bMiracastPlusBt = TRUE; + } + else + { + bMiracastPlusBt = FALSE; + } + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_MIRACAST_PLUS_BT, &bMiracastPlusBt); + halbtc8723b2ant_ActionWifiMultiPort(pBtCoexist); + + return; + } + else + { + bMiracastPlusBt = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_MIRACAST_PLUS_BT, &bMiracastPlusBt); + } + + pCoexDm->curAlgorithm = algorithm; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Algorithm = %d \n", pCoexDm->curAlgorithm)); + + if(halbtc8723b2ant_IsCommonAction(pBtCoexist)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant common.\n")); + pCoexDm->bAutoTdmaAdjust = FALSE; + } + else + { + if(pCoexDm->curAlgorithm != pCoexDm->preAlgorithm) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], preAlgorithm=%d, curAlgorithm=%d\n", + pCoexDm->preAlgorithm, pCoexDm->curAlgorithm)); + pCoexDm->bAutoTdmaAdjust = FALSE; + } + switch(pCoexDm->curAlgorithm) + { + case BT_8723B_2ANT_COEX_ALGO_SCO: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = SCO.\n")); + halbtc8723b2ant_ActionSco(pBtCoexist); + break; + case BT_8723B_2ANT_COEX_ALGO_HID: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID.\n")); + halbtc8723b2ant_ActionHid(pBtCoexist); + break; + case BT_8723B_2ANT_COEX_ALGO_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = A2DP.\n")); + halbtc8723b2ant_ActionA2dp(pBtCoexist); + break; + case BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n")); + halbtc8723b2ant_ActionA2dpPanHs(pBtCoexist); + break; + case BT_8723B_2ANT_COEX_ALGO_PANEDR: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n")); + halbtc8723b2ant_ActionPanEdr(pBtCoexist); + break; + case BT_8723B_2ANT_COEX_ALGO_PANHS: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HS mode.\n")); + halbtc8723b2ant_ActionPanHs(pBtCoexist); + break; + case BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n")); + halbtc8723b2ant_ActionPanEdrA2dp(pBtCoexist); + break; + case BT_8723B_2ANT_COEX_ALGO_PANEDR_HID: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n")); + halbtc8723b2ant_ActionPanEdrHid(pBtCoexist); + break; + case BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n")); + halbtc8723b2ant_ActionHidA2dpPanEdr(pBtCoexist); + break; + case BT_8723B_2ANT_COEX_ALGO_HID_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n")); + halbtc8723b2ant_ActionHidA2dp(pBtCoexist); + break; + default: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n")); + halbtc8723b2ant_CoexAllOff(pBtCoexist); + break; + } + pCoexDm->preAlgorithm = pCoexDm->curAlgorithm; + } +} + +VOID +halbtc8723b2ant_WifiOffHwCfg( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bIsInMpMode = FALSE; + u1Byte H2C_Parameter[2] ={0}; + u4Byte fwVer=0; + + // set wlan_act to low + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0x4); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x780); //WiFi goto standby while GNT_BT 0-->1 + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); + if(fwVer >= 0x180000) + { + /* Use H2C to set GNT_BT to HIGH */ + H2C_Parameter[0] = 1; + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x6E, 1, H2C_Parameter); + } + else + { + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x765, 0x18); + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_IS_IN_MP_MODE, &bIsInMpMode); + if(!bIsInMpMode) + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x67, 0x20, 0x0); //BT select s0/s1 is controlled by BT + else + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x67, 0x20, 0x1); //BT select s0/s1 is controlled by WiFi +} + +VOID +halbtc8723b2ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bBackUp + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + u4Byte u4Tmp=0, fwVer; + u2Byte u2Tmp=0; + u1Byte u1Tmp=0; + u1Byte H2C_Parameter[2] ={0}; + + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 2Ant Init HW Config!!\n")); + + //0xf0[15:12] --> Chip Cut information + pCoexSta->nCutVersion = (pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xf1) & 0xf0) >> 4; + + // backup rf 0x1e value + pCoexDm->btRf0x1eBackup = + pBtCoexist->fBtcGetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff); + + // 0x790[5:0]=0x5 + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x790); + u1Tmp &= 0xc0; + u1Tmp |= 0x5; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x790, u1Tmp); + + //Antenna config + halbtc8723b2ant_SetAntPath(pBtCoexist, BTC_ANT_WIFI_AT_MAIN, TRUE, FALSE); + pCoexSta->disVerInfoCnt = 0; + + // PTA parameter + halbtc8723b2ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 0); + + // Enable counter statistics + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0x4); //0x76e[3] =1, WLAN_Act control by PTA + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x778, 0x3); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x40, 0x20, 0x1); +} + +//============================================================ +// work around function start with wa_halbtc8723b2ant_ +//============================================================ +//============================================================ +// extern function start with EXhalbtc8723b2ant_ +//============================================================ +VOID +EXhalbtc8723b2ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + u2Byte u2Tmp=0x0; + + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x67, 0x20); + + // enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. + u2Tmp = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0x2); + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x2, u2Tmp|BIT0|BIT1); + + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x0); + + if(pBtCoexist->chipInterface == BTC_INTF_USB) + { + // fixed at S0 for USB interface + pBoardInfo->btdmAntPos = BTC_ANTENNA_AT_AUX_PORT; + } + else + { + // for PCIE and SDIO interface, we check efuse 0xc3[6] + if(pBoardInfo->singleAntPath == 0) + { + // set to S1 + pBoardInfo->btdmAntPos = BTC_ANTENNA_AT_MAIN_PORT; + } + else if(pBoardInfo->singleAntPath == 1) + { + // set to S0 + pBoardInfo->btdmAntPos = BTC_ANTENNA_AT_AUX_PORT; + } + } +} + +VOID +EXhalbtc8723b2ant_PreLoadFirmware( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + u1Byte u1Tmp=0x4; /* Set BIT2 by default since it's 2ant case */ + + // + // S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) + // Local setting bit define + // BIT0: "0" for no antenna inverse; "1" for antenna inverse + // BIT1: "0" for internal switch; "1" for external switch + // BIT2: "0" for one antenna; "1" for two antenna + // NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 + if(pBtCoexist->chipInterface == BTC_INTF_USB) + { + // fixed at S0 for USB interface + u1Tmp |= 0x1; // antenna inverse + pBtCoexist->fBtcWriteLocalReg1Byte(pBtCoexist, 0xfe08, u1Tmp); + } + else + { + // for PCIE and SDIO interface, we check efuse 0xc3[6] + if(pBoardInfo->singleAntPath == 0) + { + } + else if(pBoardInfo->singleAntPath == 1) + { + // set to S0 + u1Tmp |= 0x1; // antenna inverse + } + + if(pBtCoexist->chipInterface == BTC_INTF_PCI) + { + pBtCoexist->fBtcWriteLocalReg1Byte(pBtCoexist, 0x384, u1Tmp); + } + else if(pBtCoexist->chipInterface == BTC_INTF_SDIO) + { + pBtCoexist->fBtcWriteLocalReg1Byte(pBtCoexist, 0x60, u1Tmp); + } + } +} + +VOID +EXhalbtc8723b2ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ) +{ + halbtc8723b2ant_InitHwConfig(pBtCoexist, TRUE); +} + +VOID +EXhalbtc8723b2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Coex Mechanism Init!!\n")); + + halbtc8723b2ant_InitCoexDm(pBtCoexist); +} + +VOID +EXhalbtc8723b2ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + pu1Byte cliBuf=pBtCoexist->cliBuf; + u1Byte u1Tmp[4], i, btInfoExt, psTdmaCase=0; + u4Byte u4Tmp[4]; + u4Byte faOfdm, faCck; + u4Byte fwVer=0, btPatchVer=0; + static u1Byte PopReportIn10s = 0; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cliBuf); + + if(pBtCoexist->bManualControl) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[Under Manual Control]============"); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n =========================================="); + CL_PRINTF(cliBuf); + } + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:", \ + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \ + ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion); + CL_PRINTF(cliBuf); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_BT_PATCH_VER, &btPatchVer); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)/ %c", "Version Coex/ Fw/ Patch/ Cut", \ + GLCoexVerDate8723b2Ant, GLCoexVer8723b2Ant, fwVer, btPatchVer, btPatchVer, pCoexSta->nCutVersion+65); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", "Wifi channel informed to BT", \ + pCoexDm->wifiChnlInfo[0], pCoexDm->wifiChnlInfo[1], + pCoexDm->wifiChnlInfo[2]); + CL_PRINTF(cliBuf); + + // wifi status + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Wifi Status]============"); + CL_PRINTF(cliBuf); + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[BT Status]============"); + CL_PRINTF(cliBuf); + + PopReportIn10s++; + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d/ %d] ", "BT [status/ rssi/ retryCnt/ popCnt]", \ + ((pBtCoexist->btInfo.bBtDisabled)? ("disabled"): ((pCoexSta->bC2hBtInquiryPage)?("inquiry/page scan"):((BT_8723B_1ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus)? "non-connected idle": + ( (BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus)? "connected-idle":"busy")))), + pCoexSta->btRssi-100, pCoexSta->btRetryCnt, pCoexSta->popEventCnt); + CL_PRINTF(cliBuf); + + if (PopReportIn10s >= 5) + { + pCoexSta->popEventCnt = 0; + PopReportIn10s = 0; + } + + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d / %d / %d", "SCO/HID/PAN/A2DP/NameReq/WHQL", \ + pBtLinkInfo->bScoExist, pBtLinkInfo->bHidExist, pBtLinkInfo->bPanExist, pBtLinkInfo->bA2dpExist, pCoexSta->bC2hBtRemoteNameReq, pCoexSta->bBtWhckTest ); + CL_PRINTF(cliBuf); + + if (pStackInfo->bProfileNotified) + { + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO); + } + else + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Role", \ + (pBtLinkInfo->bSlaveRole )? "Slave":"Master"); + CL_PRINTF(cliBuf); + } + + btInfoExt = pCoexSta->btInfoExt; + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "A2DP Rate/Bitpool", \ + (btInfoExt&BIT0)? "BR":"EDR", pCoexSta->nA2DPBitPool); + CL_PRINTF(cliBuf); + + for(i=0; ibtInfoC2hCnt[i]) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", GLBtInfoSrc8723b2Ant[i], \ + pCoexSta->btInfoC2h[i][0], pCoexSta->btInfoC2h[i][1], + pCoexSta->btInfoC2h[i][2], pCoexSta->btInfoC2h[i][3], + pCoexSta->btInfoC2h[i][4], pCoexSta->btInfoC2h[i][5], + pCoexSta->btInfoC2h[i][6], pCoexSta->btInfoC2hCnt[i]); + CL_PRINTF(cliBuf); + } + } + + // Sw mechanism + if(pBtCoexist->bManualControl) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism] (before Manual)============"); + } + else + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============"); + } + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", "SM1[ShRf/ LpRA/ LimDig]", \ + pCoexDm->bCurRfRxLpfShrink, pCoexDm->bCurLowPenaltyRa, pCoexDm->bLimitedDig); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", \ + pCoexDm->bCurAgcTableEn, pCoexDm->bCurAdcBackOff, pCoexDm->bCurDacSwingOn, pCoexDm->curDacSwingLvl); + CL_PRINTF(cliBuf); + + // Fw mechanism + if(pBtCoexist->bManualControl) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism] (before Manual) ============"); + } + else + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============"); + } + + psTdmaCase = pCoexDm->curPsTdma; + + if (pCoexDm->bIsSwitchTo1dot5Ant) + psTdmaCase = psTdmaCase + 100; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (%s,%s)", "PS TDMA", \ + pCoexDm->psTdmaPara[0], pCoexDm->psTdmaPara[1], + pCoexDm->psTdmaPara[2], pCoexDm->psTdmaPara[3], + pCoexDm->psTdmaPara[4], psTdmaCase, + (pCoexDm->bCurPsTdmaOn? "On":"Off"), + (pCoexDm->bAutoTdmaAdjust? "Adj":"Fix") ); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "Coex Table Type", \ + pCoexSta->nCoexTableType); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "DecBtPwr/ IgnWlanAct", \ + pCoexDm->curBtDecPwrLvl, pCoexDm->bCurIgnoreWlanAct); + CL_PRINTF(cliBuf); + + // Hw setting + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "RF-A, 0x1e initVal", \ + pCoexDm->btRf0x1eBackup); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x778); + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x880); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x778/0x880[29:25]", \ + u1Tmp[0], (u4Tmp[0]&0x3e000000) >> 25); + CL_PRINTF(cliBuf); + + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x948); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x67); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x765); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x948/ 0x67[5] / 0x765", \ + u4Tmp[0], ((u1Tmp[0]&0x20)>> 5), u1Tmp[1]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x92c); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x930); + u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x944); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x92c[1:0]/ 0x930[7:0]/0x944[1:0]", \ + u4Tmp[0]&0x3, u4Tmp[1]&0xff, u4Tmp[2]&0x3); + CL_PRINTF(cliBuf); + + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x39); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x40); + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x4c); + u1Tmp[2] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x64); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0x38[11]/0x40/0x4c[24:23]/0x64[0]", \ + ((u1Tmp[0] & 0x8)>>3), u1Tmp[1], ((u4Tmp[0]&0x01800000)>>23), u1Tmp[2]&0x1); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x550); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x522); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x550(bcn ctrl)/0x522", \ + u4Tmp[0], u1Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc50); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x49c); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0xc50(dig)/0x49c(null-drop)", \ + u4Tmp[0]&0xff, u1Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda0); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda4); + u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda8); + u4Tmp[3] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xcf0); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xa5b); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xa5c); + + faOfdm = ((u4Tmp[0]&0xffff0000) >> 16) + ((u4Tmp[1]&0xffff0000) >> 16) + (u4Tmp[1] & 0xffff) + (u4Tmp[2] & 0xffff) + \ + ((u4Tmp[3]&0xffff0000) >> 16) + (u4Tmp[3] & 0xffff) ; + faCck = (u1Tmp[0] << 8) + u1Tmp[1]; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "OFDM-CCA/OFDM-FA/CCK-FA", \ + u4Tmp[0]&0xffff, faOfdm, faCck); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", "CRC_OK CCK/11g/11n/11n-Agg", \ + pCoexSta->nCRCOK_CCK, pCoexSta->nCRCOK_11g, pCoexSta->nCRCOK_11n, pCoexSta->nCRCOK_11nAgg); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", "CRC_Err CCK/11g/11n/11n-Agg", \ + pCoexSta->nCRCErr_CCK, pCoexSta->nCRCErr_11g, pCoexSta->nCRCErr_11n, pCoexSta->nCRCErr_11nAgg); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c0); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c4); + u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c8); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x6cc); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", \ + u4Tmp[0], u4Tmp[1], u4Tmp[2], u1Tmp[0]); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x770(high-pri rx/tx)", \ + pCoexSta->highPriorityRx, pCoexSta->highPriorityTx); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x774(low-pri rx/tx)", \ + pCoexSta->lowPriorityRx, pCoexSta->lowPriorityTx); + CL_PRINTF(cliBuf); +#if(BT_AUTO_REPORT_ONLY_8723B_2ANT == 1) + //halbtc8723b2ant_MonitorBtCtr(pBtCoexist); +#endif + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + + +VOID +EXhalbtc8723b2ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_IPS_ENTER == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS ENTER notify\n")); + pCoexSta->bUnderIps = TRUE; + halbtc8723b2ant_WifiOffHwCfg(pBtCoexist); + halbtc8723b2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE); + halbtc8723b2ant_CoexAllOff(pBtCoexist); + } + else if(BTC_IPS_LEAVE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS LEAVE notify\n")); + pCoexSta->bUnderIps = FALSE; + halbtc8723b2ant_InitHwConfig(pBtCoexist, FALSE); + halbtc8723b2ant_InitCoexDm(pBtCoexist); + halbtc8723b2ant_QueryBtInfo(pBtCoexist); + } +} + +VOID +EXhalbtc8723b2ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_LPS_ENABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS ENABLE notify\n")); + pCoexSta->bUnderLps = TRUE; + } + else if(BTC_LPS_DISABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS DISABLE notify\n")); + pCoexSta->bUnderLps = FALSE; + } +} + +VOID +EXhalbtc8723b2ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + u4Byte u4Tmp; + u1Byte u1Tmpa, u1Tmpb; + + + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x948); + u1Tmpa = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x765); + u1Tmpb = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x76e); + + if(BTC_SCAN_START == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n")); + } + else if(BTC_SCAN_FINISH == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n")); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_AP_NUM, &pCoexSta->nScanAPNum); + } + + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], 0x948=0x%x, 0x765=0x%x, 0x76e=0x%x\n", + u4Tmp, u1Tmpa, u1Tmpb)); +} + +VOID +EXhalbtc8723b2ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_ASSOCIATE_START == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n")); + } + else if(BTC_ASSOCIATE_FINISH == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n")); + } +} + +VOID +EXhalbtc8723b2ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + u1Byte H2C_Parameter[3] ={0}; + u4Byte wifiBw; + u1Byte wifiCentralChnl; + u1Byte apNum=0; + + if(BTC_MEDIA_CONNECT == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA connect notify\n")); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA disconnect notify\n")); + } + + // only 2.4G we need to inform bt the chnl mask + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, &wifiCentralChnl); + if( (BTC_MEDIA_CONNECT == type) && + (wifiCentralChnl <= 14) ) + { + H2C_Parameter[0] = 0x1; + H2C_Parameter[1] = wifiCentralChnl; + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + H2C_Parameter[2] = 0x30; + else + { + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_AP_NUM, &apNum); + if(apNum < 10) + H2C_Parameter[2] = 0x30; + else + H2C_Parameter[2] = 0x20; + } + } + + pCoexDm->wifiChnlInfo[0] = H2C_Parameter[0]; + pCoexDm->wifiChnlInfo[1] = H2C_Parameter[1]; + pCoexDm->wifiChnlInfo[2] = H2C_Parameter[2]; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x66=0x%x\n", + H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x66, 3, H2C_Parameter); +} + +VOID +EXhalbtc8723b2ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(type == BTC_PACKET_DHCP) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], DHCP Packet notify\n")); + } +} + +VOID +EXhalbtc8723b2ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + u1Byte btInfo=0; + u1Byte i, rspSource=0; + BOOLEAN bBtBusy=FALSE, bLimitedDig=FALSE; + BOOLEAN bWifiConnected=FALSE; + static BOOLEAN bPreScoExist=FALSE; + u4Byte raMask=0x0; + + pCoexSta->bC2hBtInfoReqSent = FALSE; + + rspSource = tmpBuf[0]&0xf; + if(rspSource >= BT_INFO_SRC_8723B_2ANT_MAX) + rspSource = BT_INFO_SRC_8723B_2ANT_WIFI_FW; + pCoexSta->btInfoC2hCnt[rspSource]++; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Bt info[%d], length=%d, hex data=[", rspSource, length)); + for(i=0; ibtInfoC2h[rspSource][i] = tmpBuf[i]; + if(i == 1) + btInfo = tmpBuf[i]; + if(i == length-1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x]\n", tmpBuf[i])); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x, ", tmpBuf[i])); + } + } + + if(pBtCoexist->bManualControl) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), return for Manual CTRL<===\n")); + return; + } + + // if 0xff, it means BT is under WHCK test + if (btInfo == 0xff) + pCoexSta->bBtWhckTest = TRUE; + else + pCoexSta->bBtWhckTest = FALSE; + + if(BT_INFO_SRC_8723B_2ANT_WIFI_FW != rspSource) + { + pCoexSta->btRetryCnt = // [3:0] + pCoexSta->btInfoC2h[rspSource][2]&0xf; + + if (pCoexSta->btRetryCnt >= 1) + pCoexSta->popEventCnt++; + + pCoexSta->btRssi = + pCoexSta->btInfoC2h[rspSource][3]*2+10; + + pCoexSta->btInfoExt = + pCoexSta->btInfoC2h[rspSource][4]; + + if (pCoexSta->btInfoC2h[rspSource][2]&0x20) + pCoexSta->bC2hBtRemoteNameReq = TRUE; + else + pCoexSta->bC2hBtRemoteNameReq = FALSE; + + if (pCoexSta->btInfoC2h[rspSource][1] == 0x49) + { + pCoexSta->nA2DPBitPool = + pCoexSta->btInfoC2h[rspSource][6]; + } + else + pCoexSta->nA2DPBitPool = 0; + + pCoexSta->bBtTxRxMask = (pCoexSta->btInfoC2h[rspSource][2]&0x40); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TX_RX_MASK, &pCoexSta->bBtTxRxMask); + if (pCoexSta->bBtTxRxMask) + { + /* BT into is responded by BT FW and BT RF REG 0x3C != 0x01 => Need to switch BT TRx Mask */ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x01\n")); + pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x3c, 0x01); + } + + // Here we need to resend some wifi info to BT + // because bt is reset and loss of the info. + if( (pCoexSta->btInfoExt & BIT1) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n")); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + if(bWifiConnected) + { + EXhalbtc8723b2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_CONNECT); + } + else + { + EXhalbtc8723b2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); + } + } + + if( (pCoexSta->btInfoExt & BIT3) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n")); + halbtc8723b2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE); + } + else + { + // BT already NOT ignore Wlan active, do nothing here. + } +#if(BT_AUTO_REPORT_ONLY_8723B_2ANT == 0) + if( (pCoexSta->btInfoExt & BIT4) ) + { + // BT auto report already enabled, do nothing + } + else + { + halbtc8723b2ant_BtAutoReport(pBtCoexist, FORCE_EXEC, TRUE); + } +#endif + } + + // check BIT2 first ==> check if bt is under inquiry or page scan + if(btInfo & BT_INFO_8723B_2ANT_B_INQ_PAGE) + pCoexSta->bC2hBtInquiryPage = TRUE; + else + pCoexSta->bC2hBtInquiryPage = FALSE; + + // set link exist status + if(!(btInfo&BT_INFO_8723B_2ANT_B_CONNECTION)) + { + pCoexSta->bBtLinkExist = FALSE; + pCoexSta->bPanExist = FALSE; + pCoexSta->bA2dpExist = FALSE; + pCoexSta->bHidExist = FALSE; + pCoexSta->bScoExist = FALSE; + } + else // connection exists + { + pCoexSta->bBtLinkExist = TRUE; + if(btInfo & BT_INFO_8723B_2ANT_B_FTP) + pCoexSta->bPanExist = TRUE; + else + pCoexSta->bPanExist = FALSE; + if(btInfo & BT_INFO_8723B_2ANT_B_A2DP) + pCoexSta->bA2dpExist = TRUE; + else + pCoexSta->bA2dpExist = FALSE; + if(btInfo & BT_INFO_8723B_2ANT_B_HID) + pCoexSta->bHidExist = TRUE; + else + pCoexSta->bHidExist = FALSE; + if(btInfo & BT_INFO_8723B_2ANT_B_SCO_ESCO) + pCoexSta->bScoExist = TRUE; + else + pCoexSta->bScoExist = FALSE; + + if ( (pCoexSta->bHidExist == FALSE) && (pCoexSta->bC2hBtInquiryPage == FALSE) && (pCoexSta->bScoExist == FALSE)) + { + if (pCoexSta->highPriorityTx + pCoexSta->highPriorityRx >= 160) + { + pCoexSta->bHidExist = TRUE; + btInfo = btInfo | 0x28; + } + } + } + + halbtc8723b2ant_UpdateBtLinkInfo(pBtCoexist); + + if(!(btInfo&BT_INFO_8723B_2ANT_B_CONNECTION)) + { + pCoexDm->btStatus = BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n")); + } + else if(btInfo == BT_INFO_8723B_2ANT_B_CONNECTION) // connection exists but no busy + { + pCoexDm->btStatus = BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n")); + } + else if((btInfo&BT_INFO_8723B_2ANT_B_SCO_ESCO) || + (btInfo&BT_INFO_8723B_2ANT_B_SCO_BUSY)) + { + pCoexDm->btStatus = BT_8723B_2ANT_BT_STATUS_SCO_BUSY; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT SCO busy!!!\n")); + } + else if(btInfo&BT_INFO_8723B_2ANT_B_ACL_BUSY) + { + pCoexDm->btStatus = BT_8723B_2ANT_BT_STATUS_ACL_BUSY; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT ACL busy!!!\n")); + } + else + { + pCoexDm->btStatus = BT_8723B_2ANT_BT_STATUS_MAX; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n")); + } + + if( (BT_8723B_2ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) || + (BT_8723B_2ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8723B_2ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + bBtBusy = TRUE; + bLimitedDig = TRUE; + } + else + { + bBtBusy = FALSE; + bLimitedDig = FALSE; + } + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bBtBusy); + + pCoexDm->bLimitedDig = bLimitedDig; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_LIMITED_DIG, &bLimitedDig); + + halbtc8723b2ant_RunCoexistMechanism(pBtCoexist); +} + +VOID +EXhalbtc8723b2ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Halt notify\n")); + + halbtc8723b2ant_WifiOffHwCfg(pBtCoexist); + //remove due to interrupt is disabled that polling c2h will fail and delay 100ms. + //pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x3c, 0x15); //BT goto standby while GNT_BT 1-->0 + halbtc8723b2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE); + + EXhalbtc8723b2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); +} + +VOID +EXhalbtc8723b2ant_PnpNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte pnpState + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Pnp notify\n")); + + if(BTC_WIFI_PNP_SLEEP == pnpState) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Pnp notify to SLEEP\n")); + } + else if(BTC_WIFI_PNP_WAKE_UP == pnpState) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Pnp notify to WAKE UP\n")); + halbtc8723b2ant_InitHwConfig(pBtCoexist, FALSE); + halbtc8723b2ant_InitCoexDm(pBtCoexist); + halbtc8723b2ant_QueryBtInfo(pBtCoexist); + } +} + +VOID +EXhalbtc8723b2ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ) +{ + //static u1Byte disVerInfoCnt=0; + u4Byte fwVer=0, btPatchVer=0; + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ==========================Periodical===========================\n")); + + if(pCoexSta->disVerInfoCnt <= 5) + { + pCoexSta->disVerInfoCnt += 1; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ****************************************************************\n")); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Ant PG Num/ Ant Mech/ Ant Pos = %d/ %d/ %d\n", + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum, pBoardInfo->btdmAntPos)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT stack/ hci ext ver = %s / %d\n", + ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion)); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_BT_PATCH_VER, &btPatchVer); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CoexVer/ FwVer/ PatchVer = %d_%x/ 0x%x/ 0x%x(%d)\n", + GLCoexVerDate8723b2Ant, GLCoexVer8723b2Ant, fwVer, btPatchVer, btPatchVer)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ****************************************************************\n")); + + if (pCoexSta->disVerInfoCnt == 3) + { + //Antenna config to set 0x765 = 0x0 (GNT_BT control by PTA) after initial + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Set GNT_BT control by PTA\n")); + halbtc8723b2ant_SetAntPath(pBtCoexist, BTC_ANT_WIFI_AT_MAIN, FALSE, FALSE); + } + } + +#if(BT_AUTO_REPORT_ONLY_8723B_2ANT == 0) + halbtc8723b2ant_QueryBtInfo(pBtCoexist); + halbtc8723b2ant_MonitorBtEnableDisable(pBtCoexist); +#else + halbtc8723b2ant_MonitorBtCtr(pBtCoexist); + halbtc8723b2ant_MonitorWiFiCtr(pBtCoexist); + + //for some BT speaker that Hi-Pri pkt appear begore start play, this will cause HID exist + if ( (pCoexSta->highPriorityTx + pCoexSta->highPriorityRx < 50) && (pBtLinkInfo->bHidExist == TRUE)) + { + pBtLinkInfo->bHidExist = FALSE; + } + + if( halbtc8723b2ant_IsWifiStatusChanged(pBtCoexist) || + pCoexDm->bAutoTdmaAdjust) + { + halbtc8723b2ant_RunCoexistMechanism(pBtCoexist); + } +#endif +} + + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723b2Ant.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723b2Ant.h new file mode 100644 index 000000000..7ae66968f --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8723b2Ant.h @@ -0,0 +1,235 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//=========================================== +// The following is for 8723B 2Ant BT Co-exist definition +//=========================================== +#define BT_AUTO_REPORT_ONLY_8723B_2ANT 1 + + +#define BT_INFO_8723B_2ANT_B_FTP BIT7 +#define BT_INFO_8723B_2ANT_B_A2DP BIT6 +#define BT_INFO_8723B_2ANT_B_HID BIT5 +#define BT_INFO_8723B_2ANT_B_SCO_BUSY BIT4 +#define BT_INFO_8723B_2ANT_B_ACL_BUSY BIT3 +#define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT2 +#define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT1 +#define BT_INFO_8723B_2ANT_B_CONNECTION BIT0 + +#define BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT 2 + + +#define BT_8723B_2ANT_WIFI_RSSI_COEXSWITCH_THRES 42 //WiFi RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation +#define BT_8723B_2ANT_BT_RSSI_COEXSWITCH_THRES 46 //BT RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation + +typedef enum _BT_INFO_SRC_8723B_2ANT{ + BT_INFO_SRC_8723B_2ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8723B_2ANT_BT_RSP = 0x1, + BT_INFO_SRC_8723B_2ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8723B_2ANT_MAX +}BT_INFO_SRC_8723B_2ANT,*PBT_INFO_SRC_8723B_2ANT; + +typedef enum _BT_8723B_2ANT_BT_STATUS{ + BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8723B_2ANT_BT_STATUS_INQ_PAGE = 0x2, + BT_8723B_2ANT_BT_STATUS_ACL_BUSY = 0x3, + BT_8723B_2ANT_BT_STATUS_SCO_BUSY = 0x4, + BT_8723B_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, + BT_8723B_2ANT_BT_STATUS_MAX +}BT_8723B_2ANT_BT_STATUS,*PBT_8723B_2ANT_BT_STATUS; + +typedef enum _BT_8723B_2ANT_COEX_ALGO{ + BT_8723B_2ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8723B_2ANT_COEX_ALGO_SCO = 0x1, + BT_8723B_2ANT_COEX_ALGO_HID = 0x2, + BT_8723B_2ANT_COEX_ALGO_A2DP = 0x3, + BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS = 0x4, + BT_8723B_2ANT_COEX_ALGO_PANEDR = 0x5, + BT_8723B_2ANT_COEX_ALGO_PANHS = 0x6, + BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7, + BT_8723B_2ANT_COEX_ALGO_PANEDR_HID = 0x8, + BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, + BT_8723B_2ANT_COEX_ALGO_HID_A2DP = 0xa, + BT_8723B_2ANT_COEX_ALGO_MAX = 0xb, +}BT_8723B_2ANT_COEX_ALGO,*PBT_8723B_2ANT_COEX_ALGO; + +typedef struct _COEX_DM_8723B_2ANT{ + // fw mechanism + u1Byte preBtDecPwrLvl; + u1Byte curBtDecPwrLvl; + u1Byte preFwDacSwingLvl; + u1Byte curFwDacSwingLvl; + BOOLEAN bCurIgnoreWlanAct; + BOOLEAN bPreIgnoreWlanAct; + u1Byte prePsTdma; + u1Byte curPsTdma; + u1Byte psTdmaPara[5]; + u1Byte psTdmaDuAdjType; + BOOLEAN bResetTdmaAdjust; + BOOLEAN bAutoTdmaAdjust; + BOOLEAN bPrePsTdmaOn; + BOOLEAN bCurPsTdmaOn; + BOOLEAN bPreBtAutoReport; + BOOLEAN bCurBtAutoReport; + + // sw mechanism + BOOLEAN bPreRfRxLpfShrink; + BOOLEAN bCurRfRxLpfShrink; + u4Byte btRf0x1eBackup; + BOOLEAN bPreLowPenaltyRa; + BOOLEAN bCurLowPenaltyRa; + BOOLEAN bPreDacSwingOn; + u4Byte preDacSwingLvl; + BOOLEAN bCurDacSwingOn; + u4Byte curDacSwingLvl; + BOOLEAN bPreAdcBackOff; + BOOLEAN bCurAdcBackOff; + BOOLEAN bPreAgcTableEn; + BOOLEAN bCurAgcTableEn; + u4Byte preVal0x6c0; + u4Byte curVal0x6c0; + u4Byte preVal0x6c4; + u4Byte curVal0x6c4; + u4Byte preVal0x6c8; + u4Byte curVal0x6c8; + u1Byte preVal0x6cc; + u1Byte curVal0x6cc; + BOOLEAN bLimitedDig; + + // algorithm related + u1Byte preAlgorithm; + u1Byte curAlgorithm; + u1Byte btStatus; + u1Byte wifiChnlInfo[3]; + + BOOLEAN bNeedRecover0x948; + u4Byte backup0x948; + + u1Byte preLps; + u1Byte curLps; + u1Byte preRpwm; + u1Byte curRpwm; + + BOOLEAN bIsSwitchTo1dot5Ant; +} COEX_DM_8723B_2ANT, *PCOEX_DM_8723B_2ANT; + +typedef struct _COEX_STA_8723B_2ANT{ + BOOLEAN bBtLinkExist; + BOOLEAN bScoExist; + BOOLEAN bA2dpExist; + BOOLEAN bHidExist; + BOOLEAN bPanExist; + + BOOLEAN bUnderLps; + BOOLEAN bUnderIps; + u4Byte highPriorityTx; + u4Byte highPriorityRx; + u4Byte lowPriorityTx; + u4Byte lowPriorityRx; + u1Byte btRssi; + BOOLEAN bBtTxRxMask; + u1Byte preBtRssiState; + u1Byte preWifiRssiState[4]; + BOOLEAN bC2hBtInfoReqSent; + u1Byte btInfoC2h[BT_INFO_SRC_8723B_2ANT_MAX][10]; + u4Byte btInfoC2hCnt[BT_INFO_SRC_8723B_2ANT_MAX]; + BOOLEAN bBtWhckTest; + BOOLEAN bC2hBtInquiryPage; + BOOLEAN bC2hBtRemoteNameReq; + u1Byte btRetryCnt; + u1Byte btInfoExt; + u4Byte popEventCnt; + u1Byte nScanAPNum; + + u4Byte nCRCOK_CCK; + u4Byte nCRCOK_11g; + u4Byte nCRCOK_11n; + u4Byte nCRCOK_11nAgg; + + u4Byte nCRCErr_CCK; + u4Byte nCRCErr_11g; + u4Byte nCRCErr_11n; + u4Byte nCRCErr_11nAgg; + + u1Byte nCoexTableType; + BOOLEAN bForceLpsOn; + + u1Byte disVerInfoCnt; + + u1Byte nA2DPBitPool; + u1Byte nCutVersion; +}COEX_STA_8723B_2ANT, *PCOEX_STA_8723B_2ANT; + +//=========================================== +// The following is interface which will notify coex module. +//=========================================== +VOID +EXhalbtc8723b2ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8723b2ant_PreLoadFirmware( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8723b2ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ); +VOID +EXhalbtc8723b2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8723b2ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8723b2ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8723b2ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8723b2ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8723b2ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8723b2ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8723b2ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ); +VOID +EXhalbtc8723b2ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8723b2ant_PnpNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte pnpState + ); +VOID +EXhalbtc8723b2ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8723b2ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ); + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8812a1Ant.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8812a1Ant.c new file mode 100644 index 000000000..d5359ad48 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8812a1Ant.c @@ -0,0 +1,3718 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//============================================================ +// Description: +// +// This file is for RTL8812A Co-exist mechanism +// +// History +// 2012/11/15 Cosa first check in. +// +//============================================================ + +//============================================================ +// include files +//============================================================ +#include "Mp_Precomp.h" + +#if WPP_SOFTWARE_TRACE +#include "HalBtc8812a1Ant.tmh" +#endif + +#if(BT_30_SUPPORT == 1) +//============================================================ +// Global variables, these are static variables +//============================================================ +static COEX_DM_8812A_1ANT GLCoexDm8812a1Ant; +static PCOEX_DM_8812A_1ANT pCoexDm=&GLCoexDm8812a1Ant; +static COEX_STA_8812A_1ANT GLCoexSta8812a1Ant; +static PCOEX_STA_8812A_1ANT pCoexSta=&GLCoexSta8812a1Ant; + +const char *const GLBtInfoSrc8812a1Ant[]={ + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; + +u4Byte GLCoexVerDate8812a1Ant=20140708; +u4Byte GLCoexVer8812a1Ant=0x52; + +//============================================================ +// local function proto type if needed +//============================================================ +//============================================================ +// local function start with halbtc8812a1ant_ +//============================================================ +u1Byte +halbtc8812a1ant_BtRssiState( + u1Byte levelNum, + u1Byte rssiThresh, + u1Byte rssiThresh1 + ) +{ + s4Byte btRssi=0; + u1Byte btRssiState=pCoexSta->preBtRssiState; + + btRssi = pCoexSta->btRssi; + + if(levelNum == 2) + { + if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW)) + { + if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT)) + { + btRssiState = BTC_RSSI_STATE_HIGH; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else + { + if(btRssi < rssiThresh) + { + btRssiState = BTC_RSSI_STATE_LOW; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + else if(levelNum == 3) + { + if(rssiThresh > rssiThresh1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Rssi thresh error!!\n")); + return pCoexSta->preBtRssiState; + } + + if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW)) + { + if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT)) + { + btRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_MEDIUM) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_MEDIUM)) + { + if(btRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT)) + { + btRssiState = BTC_RSSI_STATE_HIGH; + } + else if(btRssi < rssiThresh) + { + btRssiState = BTC_RSSI_STATE_LOW; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_MEDIUM; + } + } + else + { + if(btRssi < rssiThresh1) + { + btRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + + pCoexSta->preBtRssiState = btRssiState; + + return btRssiState; +} + +u1Byte +halbtc8812a1ant_WifiRssiState( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte index, + IN u1Byte levelNum, + IN u1Byte rssiThresh, + IN u1Byte rssiThresh1 + ) +{ + s4Byte wifiRssi=0; + u1Byte wifiRssiState=pCoexSta->preWifiRssiState[index]; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); + + if(levelNum == 2) + { + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else + { + if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + else if(levelNum == 3) + { + if(rssiThresh > rssiThresh1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi RSSI thresh error!!\n")); + return pCoexSta->preWifiRssiState[index]; + } + + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT)) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_MEDIUM) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_MEDIUM)) + { + if(wifiRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_MEDIUM; + } + } + else + { + if(wifiRssi < rssiThresh1) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + + pCoexSta->preWifiRssiState[index] = wifiRssiState; + + return wifiRssiState; +} + +VOID +halbtc8812a1ant_UpdateRaMask( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u4Byte disRateMask + ) +{ + pCoexDm->curRaMask = disRateMask; + + if( bForceExec || (pCoexDm->preRaMask != pCoexDm->curRaMask)) + { + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_UPDATE_RAMASK, &pCoexDm->curRaMask); + } + pCoexDm->preRaMask = pCoexDm->curRaMask; +} + +//to check 0x430/0x434 is correct?? +VOID +halbtc8812a1ant_AutoRateFallbackRetry( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + BOOLEAN bWifiUnderBMode=FALSE; + + pCoexDm->curArfrType = type; + + if( bForceExec || (pCoexDm->preArfrType != pCoexDm->curArfrType)) + { + switch(pCoexDm->curArfrType) + { + case 0: // normal mode + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x430, pCoexDm->backupArfrCnt1); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x434, pCoexDm->backupArfrCnt2); + break; + case 1: + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, &bWifiUnderBMode); + if(bWifiUnderBMode) + { + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x430, 0x0); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x434, 0x01010101); + } + else + { + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x430, 0x0); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x434, 0x04030201); + } + break; + default: + break; + } + } + + pCoexDm->preArfrType = pCoexDm->curArfrType; +} + +//to check 0x42a ?? +VOID +halbtc8812a1ant_RetryLimit( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + pCoexDm->curRetryLimitType = type; + + if( bForceExec || (pCoexDm->preRetryLimitType != pCoexDm->curRetryLimitType)) + { + switch(pCoexDm->curRetryLimitType) + { + case 0: // normal mode + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x42a, pCoexDm->backupRetryLimit); + break; + case 1: // retry limit=8 + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x42a, 0x0808); + break; + default: + break; + } + } + + pCoexDm->preRetryLimitType = pCoexDm->curRetryLimitType; +} + +//to check 0x456?? +VOID +halbtc8812a1ant_AmpduMaxTime( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + pCoexDm->curAmpduTimeType = type; + + if( bForceExec || (pCoexDm->preAmpduTimeType != pCoexDm->curAmpduTimeType)) + { + switch(pCoexDm->curAmpduTimeType) + { + case 0: // normal mode + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x456, pCoexDm->backupAmpduMaxTime); + break; + case 1: // AMPDU timw = 0x38 * 32us + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x456, 0x38); + break; + default: + break; + } + } + + pCoexDm->preAmpduTimeType = pCoexDm->curAmpduTimeType; +} + +VOID +halbtc8812a1ant_LimitedTx( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte raMaskType, + IN u1Byte arfrType, + IN u1Byte retryLimitType, + IN u1Byte ampduTimeType + ) +{ + switch(raMaskType) + { + case 0: // normal mode + halbtc8812a1ant_UpdateRaMask(pBtCoexist, bForceExec, 0x0); + break; + case 1: // disable cck 1/2 + halbtc8812a1ant_UpdateRaMask(pBtCoexist, bForceExec, 0x00000003); + break; + case 2: // disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 + halbtc8812a1ant_UpdateRaMask(pBtCoexist, bForceExec, 0x0001f1f7); + break; + default: + break; + } + + halbtc8812a1ant_AutoRateFallbackRetry(pBtCoexist, bForceExec, arfrType); + halbtc8812a1ant_RetryLimit(pBtCoexist, bForceExec, retryLimitType); + halbtc8812a1ant_AmpduMaxTime(pBtCoexist, bForceExec, ampduTimeType); +} + +VOID +halbtc8812a1ant_LimitedRx( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bRejApAggPkt, + IN BOOLEAN bBtCtrlAggBufSize, + IN u1Byte aggBufSize + ) +{ + BOOLEAN bRejectRxAgg=bRejApAggPkt; + BOOLEAN bBtCtrlRxAggSize=bBtCtrlAggBufSize; + u1Byte rxAggSize=aggBufSize; + + //============================================ + // Rx Aggregation related setting + //============================================ + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, &bRejectRxAgg); + // decide BT control aggregation buf size or not + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, &bBtCtrlRxAggSize); + // aggregation buf size, only work when BT control Rx aggregation size. + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_AGG_BUF_SIZE, &rxAggSize); + // real update aggregation setting + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); + + +} + +VOID +halbtc8812a1ant_QueryBtInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte dataLen=3; + u1Byte buf[5] = {0}; + + if(!pBtCoexist->btInfo.bBtDisabled) + { + if(!pCoexSta->btInfoQueryCnt || + (pCoexSta->btInfoC2hCnt[BT_INFO_SRC_8812A_1ANT_BT_RSP]-pCoexSta->btInfoQueryCnt)>2) + { + buf[0] = dataLen; + buf[1] = 0x1; // polling enable, 1=enable, 0=disable + buf[2] = 0x2; // polling time in seconds + buf[3] = 0x1; // auto report enable, 1=enable, 0=disable + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_CTRL_BT_INFO, (PVOID)&buf[0]); + } + } + pCoexSta->btInfoQueryCnt++; +} + +VOID +halbtc8812a1ant_MonitorBtCtr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte regHPTxRx, regLPTxRx, u4Tmp, u4Tmp1; + u4Byte regHPTx=0, regHPRx=0, regLPTx=0, regLPRx=0; + u1Byte u1Tmp, u1Tmp1; + s4Byte wifiRssi; + static u1Byte NumOfBtCounterChk = 0; + + regHPTxRx = 0x770; + regLPTxRx = 0x774; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regHPTxRx); + regHPTx = u4Tmp & bMaskLWord; + regHPRx = (u4Tmp & bMaskHWord)>>16; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regLPTxRx); + regLPTx = u4Tmp & bMaskLWord; + regLPRx = (u4Tmp & bMaskHWord)>>16; + + pCoexSta->highPriorityTx = regHPTx; + pCoexSta->highPriorityRx = regHPRx; + pCoexSta->lowPriorityTx = regLPTx; + pCoexSta->lowPriorityRx = regLPRx; + + if( (pCoexSta->lowPriorityTx > 1150) && (!pCoexSta->bC2hBtInquiryPage)) + pCoexSta->popEventCnt++; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Hi-Pri Rx/Tx: %d/%d, Lo-Pri Rx/Tx: %d/%d\n", + regHPRx, regHPTx, regLPRx, regLPTx)); + + // reset counter + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0xc); + + if ((regHPTx == 0) && (regHPRx ==0) && (regLPTx == 0) && (regLPRx == 0)) + { + NumOfBtCounterChk++; + if (NumOfBtCounterChk >= 3) + { + halbtc8812a1ant_QueryBtInfo(pBtCoexist); + NumOfBtCounterChk = 0; + } + } +} + +//to check registers +VOID +halbtc8812a1ant_MonitorWiFiCtr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte u4Tmp; + u2Byte u2Tmp[3]; + s4Byte wifiRssi=0; + BOOLEAN bWifiBusy = FALSE, bWifiUnderBMode = FALSE; + static u1Byte nCCKLockCounter = 0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, &bWifiUnderBMode); + + if (pCoexSta->bUnderIps) + { + pCoexSta->nCRCOK_CCK = 0; + pCoexSta->nCRCOK_11g = 0; + pCoexSta->nCRCOK_11n = 0; + pCoexSta->nCRCOK_11nAgg = 0; + + pCoexSta->nCRCErr_CCK = 0; + pCoexSta->nCRCErr_11g = 0; + pCoexSta->nCRCErr_11n = 0; + pCoexSta->nCRCErr_11nAgg = 0; + } + else + { + pCoexSta->nCRCOK_CCK = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf04); + pCoexSta->nCRCOK_11g = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf14); + pCoexSta->nCRCOK_11n = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf10); + pCoexSta->nCRCOK_11nAgg= pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf40); + + pCoexSta->nCRCErr_CCK = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf06); + pCoexSta->nCRCErr_11g = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf16); + pCoexSta->nCRCErr_11n = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf12); + pCoexSta->nCRCErr_11nAgg = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf42); + } + + + //reset counter + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xb58, 0x1, 0x1); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xb58, 0x1, 0x0); + + if ( (bWifiBusy) && (wifiRssi >= 30) && (!bWifiUnderBMode)) + { + if ( (pCoexDm->btStatus == BT_8812A_1ANT_BT_STATUS_ACL_BUSY) || + (pCoexDm->btStatus == BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY) || + (pCoexDm->btStatus == BT_8812A_1ANT_BT_STATUS_SCO_BUSY) ) + { + if (pCoexSta->nCRCOK_CCK >(pCoexSta->nCRCOK_11g + pCoexSta->nCRCOK_11n + + pCoexSta->nCRCOK_11nAgg) ) + { + if (nCCKLockCounter < 5) + nCCKLockCounter++; + } + else + { + if (nCCKLockCounter > 0) + nCCKLockCounter--; + } + + } + else + { + if (nCCKLockCounter > 0) + nCCKLockCounter--; + } + } + else + { + if (nCCKLockCounter > 0) + nCCKLockCounter--; + } + + if (!pCoexSta->bPreCCKLock) + { + + if (nCCKLockCounter >= 5) + pCoexSta->bCCKLock = TRUE; + else + pCoexSta->bCCKLock = FALSE; + } + else + { + if (nCCKLockCounter == 0) + pCoexSta->bCCKLock = FALSE; + else + pCoexSta->bCCKLock = TRUE; + } + + pCoexSta->bPreCCKLock = pCoexSta->bCCKLock; + + +} + +BOOLEAN +halbtc8812a1ant_IsWifiStatusChanged( + IN PBTC_COEXIST pBtCoexist + ) +{ + static BOOLEAN bPreWifiBusy=FALSE, bPreUnder4way=FALSE, bPreBtHsOn=FALSE; + BOOLEAN bWifiBusy=FALSE, bUnder4way=FALSE, bBtHsOn=FALSE; + BOOLEAN bWifiConnected=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &bUnder4way); + + if(bWifiConnected) + { + if(bWifiBusy != bPreWifiBusy) + { + bPreWifiBusy = bWifiBusy; + return TRUE; + } + if(bUnder4way != bPreUnder4way) + { + bPreUnder4way = bUnder4way; + return TRUE; + } + if(bBtHsOn != bPreBtHsOn) + { + bPreBtHsOn = bBtHsOn; + return TRUE; + } + } + + return FALSE; +} + +VOID +halbtc8812a1ant_UpdateBtLinkInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bBtHsOn=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + pBtLinkInfo->bBtLinkExist = pCoexSta->bBtLinkExist; + pBtLinkInfo->bScoExist = pCoexSta->bScoExist; + pBtLinkInfo->bA2dpExist = pCoexSta->bA2dpExist; + pBtLinkInfo->bPanExist = pCoexSta->bPanExist; + pBtLinkInfo->bHidExist = pCoexSta->bHidExist; + + // work around for HS mode. + if(bBtHsOn) + { + pBtLinkInfo->bPanExist = TRUE; + pBtLinkInfo->bBtLinkExist = TRUE; + } + + // check if Sco only + if( pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bScoOnly = TRUE; + else + pBtLinkInfo->bScoOnly = FALSE; + + // check if A2dp only + if( !pBtLinkInfo->bScoExist && + pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bA2dpOnly = TRUE; + else + pBtLinkInfo->bA2dpOnly = FALSE; + + // check if Pan only + if( !pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bPanOnly = TRUE; + else + pBtLinkInfo->bPanOnly = FALSE; + + // check if Hid only + if( !pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + pBtLinkInfo->bHidExist ) + pBtLinkInfo->bHidOnly = TRUE; + else + pBtLinkInfo->bHidOnly = FALSE; +} + +u1Byte +halbtc8812a1ant_ActionAlgorithm( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bBtHsOn=FALSE; + u1Byte algorithm=BT_8812A_1ANT_COEX_ALGO_UNDEFINED; + u1Byte numOfDiffProfile=0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + if(!pBtLinkInfo->bBtLinkExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], No BT link exists!!!\n")); + return algorithm; + } + + if(pBtLinkInfo->bScoExist) + numOfDiffProfile++; + if(pBtLinkInfo->bHidExist) + numOfDiffProfile++; + if(pBtLinkInfo->bPanExist) + numOfDiffProfile++; + if(pBtLinkInfo->bA2dpExist) + numOfDiffProfile++; + + if(numOfDiffProfile == 1) + { + if(pBtLinkInfo->bScoExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO only\n")); + algorithm = BT_8812A_1ANT_COEX_ALGO_SCO; + } + else + { + if(pBtLinkInfo->bHidExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID only\n")); + algorithm = BT_8812A_1ANT_COEX_ALGO_HID; + } + else if(pBtLinkInfo->bA2dpExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = A2DP only\n")); + algorithm = BT_8812A_1ANT_COEX_ALGO_A2DP; + } + else if(pBtLinkInfo->bPanExist) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = PAN(HS) only\n")); + algorithm = BT_8812A_1ANT_COEX_ALGO_PANHS; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = PAN(EDR) only\n")); + algorithm = BT_8812A_1ANT_COEX_ALGO_PANEDR; + } + } + } + } + else if(numOfDiffProfile == 2) + { + if(pBtLinkInfo->bScoExist) + { + if(pBtLinkInfo->bHidExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + HID\n")); + algorithm = BT_8812A_1ANT_COEX_ALGO_HID; + } + else if(pBtLinkInfo->bA2dpExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + A2DP ==> SCO\n")); + algorithm = BT_8812A_1ANT_COEX_ALGO_SCO; + } + else if(pBtLinkInfo->bPanExist) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + PAN(HS)\n")); + algorithm = BT_8812A_1ANT_COEX_ALGO_SCO; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + PAN(EDR)\n")); + algorithm = BT_8812A_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } + else + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bA2dpExist ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID + A2DP\n")); + algorithm = BT_8812A_1ANT_COEX_ALGO_HID_A2DP; + } + else if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID + PAN(HS)\n")); + algorithm = BT_8812A_1ANT_COEX_ALGO_HID_A2DP; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID + PAN(EDR)\n")); + algorithm = BT_8812A_1ANT_COEX_ALGO_PANEDR_HID; + } + } + else if( pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = A2DP + PAN(HS)\n")); + algorithm = BT_8812A_1ANT_COEX_ALGO_A2DP_PANHS; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = A2DP + PAN(EDR)\n")); + algorithm = BT_8812A_1ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } + } + else if(numOfDiffProfile == 3) + { + if(pBtLinkInfo->bScoExist) + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bA2dpExist ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n")); + algorithm = BT_8812A_1ANT_COEX_ALGO_HID; + } + else if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + HID + PAN(HS)\n")); + algorithm = BT_8812A_1ANT_COEX_ALGO_HID_A2DP; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n")); + algorithm = BT_8812A_1ANT_COEX_ALGO_PANEDR_HID; + } + } + else if( pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n")); + algorithm = BT_8812A_1ANT_COEX_ALGO_SCO; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n")); + algorithm = BT_8812A_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } + else + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n")); + algorithm = BT_8812A_1ANT_COEX_ALGO_HID_A2DP; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n")); + algorithm = BT_8812A_1ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } + else if(numOfDiffProfile >= 3) + { + if(pBtLinkInfo->bScoExist) + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n")); + + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n")); + algorithm = BT_8812A_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } + } + + return algorithm; +} + +VOID +halbtc8812a1ant_SetBtAutoReport( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bEnableAutoReport + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + H2C_Parameter[0] = 0; + + if(bEnableAutoReport) + { + H2C_Parameter[0] |= BIT0; + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], BT FW auto report : %s, FW write 0x68=0x%x\n", + (bEnableAutoReport? "Enabled!!":"Disabled!!"), H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x68, 1, H2C_Parameter); +} + +VOID +halbtc8812a1ant_BtAutoReport( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bEnableAutoReport + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s BT Auto report = %s\n", + (bForceExec? "force to":""), ((bEnableAutoReport)? "Enabled":"Disabled"))); + pCoexDm->bCurBtAutoReport = bEnableAutoReport; + + if(!bForceExec) + { + if(pCoexDm->bPreBtAutoReport == pCoexDm->bCurBtAutoReport) + return; + } + halbtc8812a1ant_SetBtAutoReport(pBtCoexist, pCoexDm->bCurBtAutoReport); + + pCoexDm->bPreBtAutoReport = pCoexDm->bCurBtAutoReport; +} + +//to check +VOID +halbtc8812a1ant_SetSwPenaltyTxRateAdaptive( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bLowPenaltyRa + ) +{ + u1Byte tmpU1; + + tmpU1 = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4fd); + tmpU1 |= BIT0; + if(bLowPenaltyRa) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set low penalty!!\n")); + tmpU1 &= ~BIT2; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set normal!!\n")); + tmpU1 |= BIT2; + } + + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x4fd, tmpU1); +} + +VOID +halbtc8812a1ant_LowPenaltyRa( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bLowPenaltyRa + ) +{ + pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa; + + if(!bForceExec) + { + if(pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa) + return; + } + halbtc8812a1ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa); + + pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa; +} + +VOID +halbtc8812a1ant_SetCoexTable( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte val0x6c0, + IN u4Byte val0x6c4, + IN u4Byte val0x6c8, + IN u1Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c0=0x%x\n", val0x6c0)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c0, val0x6c0); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c4=0x%x\n", val0x6c4)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c4, val0x6c4); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, val0x6c8); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc)); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cc, val0x6cc); +} + +VOID +halbtc8812a1ant_CoexTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u4Byte val0x6c0, + IN u4Byte val0x6c4, + IN u4Byte val0x6c8, + IN u1Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s write Coex Table 0x6c0=0x%x, 0x6c4=0x%x, 0x6cc=0x%x\n", + (bForceExec? "force to":""), val0x6c0, val0x6c4, val0x6cc)); + pCoexDm->curVal0x6c0 = val0x6c0; + pCoexDm->curVal0x6c4 = val0x6c4; + pCoexDm->curVal0x6c8 = val0x6c8; + pCoexDm->curVal0x6cc = val0x6cc; + + if(!bForceExec) + { + if( (pCoexDm->preVal0x6c0 == pCoexDm->curVal0x6c0) && + (pCoexDm->preVal0x6c4 == pCoexDm->curVal0x6c4) && + (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) && + (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) ) + return; + } + halbtc8812a1ant_SetCoexTable(pBtCoexist, val0x6c0, val0x6c4, val0x6c8, val0x6cc); + + pCoexDm->preVal0x6c0 = pCoexDm->curVal0x6c0; + pCoexDm->preVal0x6c4 = pCoexDm->curVal0x6c4; + pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8; + pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc; +} + +VOID +halbtc8812a1ant_CoexTableWithType( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ********** CoexTable(%d) **********\n", type)); + + pCoexSta->nCoexTableType = type; + + switch(type) + { + case 0: + halbtc8812a1ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x55555555, 0xffffff, 0x3); + break; + case 1: + halbtc8812a1ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 2: + halbtc8812a1ant_CoexTable(pBtCoexist, bForceExec, 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 3: + halbtc8812a1ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 4: + halbtc8812a1ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0xaaaa5a5a, 0xffffff, 0x3); + break; + case 5: + halbtc8812a1ant_CoexTable(pBtCoexist, bForceExec, 0x5a5a5a5a, 0xaa5a5a5a, 0xffffff, 0x3); + break; + case 6: + halbtc8812a1ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0xaaaaaaaa, 0xffffff, 0x3); + break; + case 7: + halbtc8812a1ant_CoexTable(pBtCoexist, bForceExec, 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3); + break; + default: + break; + } +} + +VOID +halbtc8812a1ant_SetFwIgnoreWlanAct( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bEnable + ) +{ + u1Byte dataLen=3; + u1Byte buf[5] = {0}; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s BT Ignore Wlan_Act\n", + (bEnable? "Enable":"Disable"))); + + buf[0] = dataLen; + buf[1] = 0x1; // OP_Code + buf[2] = 0x1; // OP_Code_Length + if(bEnable) + buf[3] = 0x1; // OP_Code_Content + else + buf[3] = 0x0; + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_CTRL_BT_COEX, (PVOID)&buf[0]); +} + +VOID +halbtc8812a1ant_IgnoreWlanAct( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bEnable + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Ignore WlanAct %s\n", + (bForceExec? "force to":""), (bEnable? "ON":"OFF"))); + pCoexDm->bCurIgnoreWlanAct = bEnable; + + if(!bForceExec) + { + if(pCoexDm->bPreIgnoreWlanAct == pCoexDm->bCurIgnoreWlanAct) + return; + } + halbtc8812a1ant_SetFwIgnoreWlanAct(pBtCoexist, bEnable); + + pCoexDm->bPreIgnoreWlanAct = pCoexDm->bCurIgnoreWlanAct; +} + +VOID +halbtc8812a1ant_SetLpsRpwm( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + u1Byte lps=lpsVal; + u1Byte rpwm=rpwmVal; + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_LPS_VAL, &lps); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RPWM_VAL, &rpwm); +} + +VOID +halbtc8812a1ant_LpsRpwm( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + BOOLEAN bForceExecPwrCmd=FALSE; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s set lps/rpwm=0x%x/0x%x \n", + (bForceExec? "force to":""), lpsVal, rpwmVal)); + pCoexDm->curLps = lpsVal; + pCoexDm->curRpwm = rpwmVal; + + if(!bForceExec) + { + if( (pCoexDm->preLps == pCoexDm->curLps) && + (pCoexDm->preRpwm == pCoexDm->curRpwm) ) + { + return; + } + } + halbtc8812a1ant_SetLpsRpwm(pBtCoexist, lpsVal, rpwmVal); + + pCoexDm->preLps = pCoexDm->curLps; + pCoexDm->preRpwm = pCoexDm->curRpwm; +} + +VOID +halbtc8812a1ant_SwMechanism( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bLowPenaltyRA + ) +{ + halbtc8812a1ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, bLowPenaltyRA); +} + +//to check bForceExec +VOID +halbtc8812a1ant_SetAntPath( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte antPosType, + IN BOOLEAN bForceExec, + IN BOOLEAN bInitHwCfg, + IN BOOLEAN bWifiOff + ) +{ + u1Byte u1Tmp=0; + + pCoexDm->curAntPosType = antPosType; + + if(bInitHwCfg) + { + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0xcb3, 0x77); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x900, 0x00000400); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76d, 0x1); + } + else if(bWifiOff) + { + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0xcb3, 0x77); + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xcb7); + u1Tmp &= ~BIT3; + u1Tmp |= BIT2; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0xcb7, u1Tmp); + } + + if(bForceExec || (pCoexDm->curAntPosType != pCoexDm->preAntPosType)) + { + // ext switch setting + switch(antPosType) + { + case BTC_ANT_PATH_WIFI: + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xcb7); + u1Tmp |= BIT3; + u1Tmp &= ~BIT2; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0xcb7, u1Tmp); + break; + case BTC_ANT_PATH_BT: + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xcb7); + u1Tmp &= ~BIT3; + u1Tmp |= BIT2; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0xcb7, u1Tmp); + break; + default: + case BTC_ANT_PATH_PTA: + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xcb7); + u1Tmp |= BIT3; + u1Tmp &= ~BIT2; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0xcb7, u1Tmp); + break; + } + } + + pCoexDm->preAntPosType = pCoexDm->curAntPosType; +} + +VOID +halbtc8812a1ant_SetFwPstdma( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte byte1, + IN u1Byte byte2, + IN u1Byte byte3, + IN u1Byte byte4, + IN u1Byte byte5 + ) +{ + u1Byte H2C_Parameter[5] ={0}; + u1Byte realByte1=byte1, realByte5=byte5; + BOOLEAN bApEnable=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + + if(bApEnable) + { + if(byte1&BIT4 && !(byte1&BIT5)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], FW for 1Ant AP mode\n")); + realByte1 &= ~BIT4; + realByte1 |= BIT5; + + realByte5 |= BIT5; + realByte5 &= ~BIT6; + } + } + + H2C_Parameter[0] = realByte1; + H2C_Parameter[1] = byte2; + H2C_Parameter[2] = byte3; + H2C_Parameter[3] = byte4; + H2C_Parameter[4] = realByte5; + + pCoexDm->psTdmaPara[0] = realByte1; + pCoexDm->psTdmaPara[1] = byte2; + pCoexDm->psTdmaPara[2] = byte3; + pCoexDm->psTdmaPara[3] = byte4; + pCoexDm->psTdmaPara[4] = realByte5; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], PS-TDMA H2C cmd =0x%x%08x\n", + H2C_Parameter[0], + H2C_Parameter[1]<<24|H2C_Parameter[2]<<16|H2C_Parameter[3]<<8|H2C_Parameter[4])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x60, 5, H2C_Parameter); +} + + +VOID +halbtc8812a1ant_PsTdma( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bTurnOn, + IN u1Byte type + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bTurnOnByCnt=FALSE, bWifiBusy=FALSE, bWiFiNoisy=FALSE; + u1Byte psTdmaTypeByCnt=0, rssiAdjustVal=0; + u1Byte psTdmaByte4Val = 0x50, psTdmaByte0Val = 0x51, psTdmaByte3Val = 0x10; + s1Byte nWiFiDurationAdjust = 0x0; + static BOOLEAN bPreWifiBusy=FALSE; + + pCoexDm->bCurPsTdmaOn = bTurnOn; + pCoexDm->curPsTdma = type; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + + if (bWifiBusy != bPreWifiBusy) + { + bForceExec = TRUE; + bPreWifiBusy = bWifiBusy; + } + + if (pCoexDm->bCurPsTdmaOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ********** TDMA(on, %d) **********\n", + pCoexDm->curPsTdma)); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ********** TDMA(off, %d) **********\n", + pCoexDm->curPsTdma)); + } + + if(!bForceExec) + { + if( (pCoexDm->bPrePsTdmaOn == pCoexDm->bCurPsTdmaOn) && + (pCoexDm->prePsTdma == pCoexDm->curPsTdma) ) + return; + } + + if (pCoexSta->nScanAPNum <= 5) + nWiFiDurationAdjust = 2; + else if (pCoexSta->nScanAPNum >= 40) + nWiFiDurationAdjust = -15; + else if (pCoexSta->nScanAPNum >= 20) + nWiFiDurationAdjust = -10; + + if (!pCoexSta->bForceLpsOn) //only for A2DP-only case 1/2/9/11 while wifi noisy threshold > 30 + { + psTdmaByte0Val = 0x61; //no null-pkt + psTdmaByte3Val = 0x11; // no tx-pause at BT-slot + psTdmaByte4Val = 0x10; // 0x778 = d/1 toggle + } + + if ( (type == 3) || (type == 13) || (type == 14) ) + { + psTdmaByte4Val = psTdmaByte4Val & 0xbf; //no dynamic slot for multi-profile + + if (!bWifiBusy) + psTdmaByte4Val = psTdmaByte4Val | 0x1; //0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) + } + + if (pBtLinkInfo->bSlaveRole == TRUE) + psTdmaByte4Val = psTdmaByte4Val | 0x1; //0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) + + if(bTurnOn) + { + switch(type) + { + default: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0x51, 0x1a, 0x1a, 0x0, psTdmaByte4Val); + break; + case 1: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x3a+nWiFiDurationAdjust, 0x03, psTdmaByte3Val, psTdmaByte4Val); + break; + case 2: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x2d+nWiFiDurationAdjust, 0x03, psTdmaByte3Val, psTdmaByte4Val); + break; + case 3: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0x51, 0x1d, 0x1d, 0x0, psTdmaByte4Val); + break; + case 4: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0x93, 0x15, 0x3, 0x14, 0x0); + break; + case 5: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0x61, 0x15, 0x3, 0x11, 0x11); + break; + case 6: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0x61, 0x20, 0x3, 0x11, 0x11); + break; + case 7: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0x13, 0xc, 0x5, 0x0, 0x0); + break; + case 8: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0x93, 0x25, 0x3, 0x10, 0x0); + break; + case 9: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x21, 0x3, psTdmaByte3Val, psTdmaByte4Val); + break; + case 10: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0x13, 0xa, 0xa, 0x0, 0x40); + break; + case 11: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, psTdmaByte0Val, 0x21, 0x03, psTdmaByte3Val, psTdmaByte4Val); + break; + case 12: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0x51, 0x0a, 0x0a, 0x0, 0x50); + break; + case 13: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0x51, 0x12, 0x12, 0x0, psTdmaByte4Val); + break; + case 14: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0x51, 0x21, 0x3, 0x10, psTdmaByte4Val); + break; + case 15: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0x13, 0xa, 0x3, 0x8, 0x0); + break; + case 16: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0x93, 0x15, 0x3, 0x10, 0x0); + break; + case 18: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0x93, 0x25, 0x3, 0x10, 0x0); + break; + case 20: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0x61, 0x3f, 0x03, 0x11, 0x10); + break; + case 21: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0x61, 0x25, 0x03, 0x11, 0x11); + break; + case 22: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0x61, 0x25, 0x03, 0x11, 0x10); + break; + case 23: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x3, 0x31, 0x18); + break; + case 24: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0xe3, 0x15, 0x3, 0x31, 0x18); + break; + case 25: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0x3, 0x31, 0x18); + break; + case 26: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0x3, 0x31, 0x18); + break; + case 27: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x3, 0x31, 0x98); + break; + case 28: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0x69, 0x25, 0x3, 0x31, 0x0); + break; + case 29: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0xab, 0x1a, 0x1a, 0x1, 0x10); + break; + case 30: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0x51, 0x30, 0x3, 0x10, 0x10); + break; + case 31: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0xd3, 0x1a, 0x1a, 0, 0x58); + break; + case 32: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0x61, 0x35, 0x3, 0x11, 0x11); + break; + case 33: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0xa3, 0x25, 0x3, 0x30, 0x90); + break; + case 34: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0x53, 0x1a, 0x1a, 0x0, 0x10); + break; + case 35: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0x63, 0x1a, 0x1a, 0x0, 0x10); + break; + case 36: + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0xd3, 0x12, 0x3, 0x14, 0x50); + break; + case 40: // SoftAP only with no sta associated,BT disable ,TDMA mode for power saving + /* here softap mode screen off will cost 70-80mA for phone */ + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0x23, 0x18, 0x00, 0x10, 0x24); + break; + } + } + else + { + + // disable PS tdma + switch(type) + { + case 8: //PTA Control + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0x8, 0x0, 0x0, 0x0, 0x0); + break; + case 0: + default: //Software control, Antenna at BT side + halbtc8812a1ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x0, 0x0); + break; + } + } + rssiAdjustVal =0; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, &rssiAdjustVal); + + + // update pre state + pCoexDm->bPrePsTdmaOn = pCoexDm->bCurPsTdmaOn; + pCoexDm->prePsTdma = pCoexDm->curPsTdma; +} + +BOOLEAN +halbtc8812a1ant_IsCommonAction( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bCommon=FALSE, bWifiConnected=FALSE, bWifiBusy=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + + if(!bWifiConnected && + BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n")); + + //halbtc8812a1ant_SwMechanism(pBtCoexist, FALSE); + + bCommon = TRUE; + } + else if(bWifiConnected && + (BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi connected + BT non connected-idle!!\n")); + + //halbtc8812a1ant_SwMechanism(pBtCoexist, FALSE); + + bCommon = TRUE; + } + else if(!bWifiConnected && + (BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non connected-idle + BT connected-idle!!\n")); + + //halbtc8812a1ant_SwMechanism(pBtCoexist, FALSE); + + bCommon = TRUE; + } + else if(bWifiConnected && + (BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi connected + BT connected-idle!!\n")); + + //halbtc8812a1ant_SwMechanism(pBtCoexist, FALSE); + + bCommon = TRUE; + } + else if(!bWifiConnected && + (BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE != pCoexDm->btStatus) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non connected-idle + BT Busy!!\n")); + + //halbtc8812a1ant_SwMechanism(pBtCoexist, FALSE); + + bCommon = TRUE; + } + else + { + if (bWifiBusy) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi Connected-Busy + BT Busy!!\n")); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi Connected-Idle + BT Busy!!\n")); + } + + bCommon = FALSE; + } + + return bCommon; +} + + +VOID +halbtc8812a1ant_TdmaDurationAdjustForAcl( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte wifiStatus + ) +{ + static s4Byte up,dn,m,n,WaitCount; + s4Byte result; //0: no change, +1: increase WiFi duration, -1: decrease WiFi duration + u1Byte retryCount=0, btInfoExt; + static BOOLEAN bPreWifiBusy=FALSE; + BOOLEAN bWifiBusy = FALSE; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TdmaDurationAdjustForAcl()\n")); + + if(BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY == wifiStatus) + bWifiBusy = TRUE; + else + bWifiBusy = FALSE; + + if( (BT_8812A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN == wifiStatus) || + (BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN == wifiStatus) || + (BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT == wifiStatus) ) + { + if( pCoexDm->curPsTdma != 1 && + pCoexDm->curPsTdma != 2 && + pCoexDm->curPsTdma != 3 && + pCoexDm->curPsTdma != 9 ) + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + + up = 0; + dn = 0; + m = 1; + n= 3; + result = 0; + WaitCount = 0; + } + return; + } + + if(!pCoexDm->bAutoTdmaAdjust) + { + pCoexDm->bAutoTdmaAdjust = TRUE; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], first run TdmaDurationAdjust()!!\n")); + + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + //============ + up = 0; + dn = 0; + m = 1; + n= 3; + result = 0; + WaitCount = 0; + } + else + { + //accquire the BT TRx retry count from BT_Info byte2 + retryCount = pCoexSta->btRetryCnt; + btInfoExt = pCoexSta->btInfoExt; + + if ( (pCoexSta->lowPriorityTx) > 1150 || (pCoexSta->lowPriorityRx) > 1250 ) + retryCount++; + + result = 0; + WaitCount++; + + if(retryCount == 0) // no retry in the last 2-second duration + { + up++; + dn--; + + if (dn <= 0) + dn = 0; + + if(up >= n) // if s n 2 retry count0, hռeWiFi duration + { + WaitCount = 0; + n = 3; + up = 0; + dn = 0; + result = 1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Increase wifi duration!!\n")); + } + } + else if (retryCount <= 3) // <=3 retry in the last 2-second duration + { + up--; + dn++; + + if (up <= 0) + up = 0; + + if (dn == 2) // if s 2 2 retry count< 3, hկWiFi duration + { + if (WaitCount <= 2) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter<3!!\n")); + } + } + else //retry count > 3, un1 retry count > 3, hկWiFi duration + { + if (WaitCount == 1) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter>3!!\n")); + } + + if(result == -1) + { + if( (BT_INFO_8812A_1ANT_A2DP_BASIC_RATE(btInfoExt)) && + ((pCoexDm->curPsTdma == 1) ||(pCoexDm->curPsTdma == 2)) ) + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(pCoexDm->curPsTdma == 1) + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + } + else if(result == 1) + { + if( (BT_INFO_8812A_1ANT_A2DP_BASIC_RATE(btInfoExt)) && + ((pCoexDm->curPsTdma == 1) ||(pCoexDm->curPsTdma == 2)) ) + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + } + else //no change + { + /* Bryant Modify + if(bWifiBusy != bPreWifiBusy) //if busy / idle change + { + bPreWifiBusy = bWifiBusy; + halbtc8812a1ant_PsTdma(pBtCoexist, FORCE_EXEC, TRUE, pCoexDm->curPsTdma); + } + */ + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ********** TDMA(on, %d) **********\n", + pCoexDm->curPsTdma)); + } + + if( pCoexDm->curPsTdma != 1 && + pCoexDm->curPsTdma != 2 && + pCoexDm->curPsTdma != 9 && + pCoexDm->curPsTdma != 11 ) + { + // recover to previous adjust type + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, pCoexDm->psTdmaDuAdjType); + } + } +} + +VOID +halbtc8812a1ant_PsTdmaCheckForPowerSaveState( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bNewPsState + ) +{ + u1Byte lpsMode=0x0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_LPS_MODE, &lpsMode); + + if(lpsMode) // already under LPS state + { + if(bNewPsState) + { + // keep state under LPS, do nothing. + } + else + { + // will leave LPS state, turn off psTdma first + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + } + } + else // NO PS state + { + if(bNewPsState) + { + // will enter LPS state, turn off psTdma first + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + } + else + { + // keep state under NO PS state, do nothing. + } + } +} + +VOID +halbtc8812a1ant_PowerSaveState( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte psType, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + BOOLEAN bLowPwrDisable=FALSE; + + switch(psType) + { + case BTC_PS_WIFI_NATIVE: + // recover to original 32k low power setting + bLowPwrDisable = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_NORMAL_LPS, NULL); + pCoexSta->bForceLpsOn = FALSE; + break; + case BTC_PS_LPS_ON: + halbtc8812a1ant_PsTdmaCheckForPowerSaveState(pBtCoexist, TRUE); + halbtc8812a1ant_LpsRpwm(pBtCoexist, NORMAL_EXEC, lpsVal, rpwmVal); + // when coex force to enter LPS, do not enter 32k low power. + bLowPwrDisable = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + // power save must executed before psTdma. + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_ENTER_LPS, NULL); + pCoexSta->bForceLpsOn = TRUE; + break; + case BTC_PS_LPS_OFF: + halbtc8812a1ant_PsTdmaCheckForPowerSaveState(pBtCoexist, FALSE); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_LEAVE_LPS, NULL); + pCoexSta->bForceLpsOn = FALSE; + break; + default: + break; + } +} + +VOID +halbtc8812a1ant_ActionWifiOnly( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8812a1ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 0); + halbtc8812a1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8); + halbtc8812a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, FORCE_EXEC, FALSE, FALSE); +} + +VOID +halbtc8812a1ant_MonitorBtEnableDisable( + IN PBTC_COEXIST pBtCoexist + ) +{ + static BOOLEAN bPreBtDisabled=FALSE; + static u4Byte btDisableCnt=0; + BOOLEAN bBtActive=TRUE, bBtDisabled=FALSE; + + // This function check if bt is disabled + + if( pCoexSta->highPriorityTx == 0 && + pCoexSta->highPriorityRx == 0 && + pCoexSta->lowPriorityTx == 0 && + pCoexSta->lowPriorityRx == 0) + { + bBtActive = FALSE; + } + if( pCoexSta->highPriorityTx == 0xffff && + pCoexSta->highPriorityRx == 0xffff && + pCoexSta->lowPriorityTx == 0xffff && + pCoexSta->lowPriorityRx == 0xffff) + { + bBtActive = FALSE; + } + if(bBtActive) + { + btDisableCnt = 0; + bBtDisabled = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is enabled !!\n")); + } + else + { + btDisableCnt++; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], bt all counters=0, %d times!!\n", + btDisableCnt)); + if(btDisableCnt >= 2) + { + bBtDisabled = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is disabled !!\n")); + halbtc8812a1ant_ActionWifiOnly(pBtCoexist); + } + } + if(bPreBtDisabled != bBtDisabled) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is from %s to %s!!\n", + (bPreBtDisabled ? "disabled":"enabled"), + (bBtDisabled ? "disabled":"enabled"))); + bPreBtDisabled = bBtDisabled; + if(!bBtDisabled) + { + } + else + { + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_LEAVE_LPS, NULL); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_NORMAL_LPS, NULL); + } + } +} + +//============================================= +// +// Software Coex Mechanism start +// +//============================================= + +// SCO only or SCO+PAN(HS) + +/* +VOID +halbtc8812a1ant_ActionSco( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8812a1ant_SwMechanism(pBtCoexist, TRUE); +} + + +VOID +halbtc8812a1ant_ActionHid( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8812a1ant_SwMechanism(pBtCoexist, TRUE); +} + +//A2DP only / PAN(EDR) only/ A2DP+PAN(HS) +VOID +halbtc8812a1ant_ActionA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8812a1ant_SwMechanism(pBtCoexist, FALSE); +} + +VOID +halbtc8812a1ant_ActionA2dpPanHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8812a1ant_SwMechanism(pBtCoexist, FALSE); +} + +VOID +halbtc8812a1ant_ActionPanEdr( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8812a1ant_SwMechanism(pBtCoexist, FALSE); +} + +//PAN(HS) only +VOID +halbtc8812a1ant_ActionPanHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8812a1ant_SwMechanism(pBtCoexist, FALSE); +} + +//PAN(EDR)+A2DP +VOID +halbtc8812a1ant_ActionPanEdrA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8812a1ant_SwMechanism(pBtCoexist, FALSE); +} + +VOID +halbtc8812a1ant_ActionPanEdrHid( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8812a1ant_SwMechanism(pBtCoexist, TRUE); +} + +// HID+A2DP+PAN(EDR) +VOID +halbtc8812a1ant_ActionHidA2dpPanEdr( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8812a1ant_SwMechanism(pBtCoexist, TRUE); +} + +VOID +halbtc8812a1ant_ActionHidA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8812a1ant_SwMechanism(pBtCoexist, TRUE); +} + +*/ + +//============================================= +// +// Non-Software Coex Mechanism start +// +//============================================= +VOID +halbtc8812a1ant_ActionWifiMultiPort( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8812a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8812a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); +} + +VOID +halbtc8812a1ant_ActionHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); +} + +VOID +halbtc8812a1ant_ActionBtInquiry( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bWifiConnected=FALSE, bApEnable=FALSE, bWifiBusy=FALSE, bBtBusy=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bBtBusy); + + if((!bWifiConnected) && (!pCoexSta->bWiFiIsHighPriTask)) + { + halbtc8812a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8812a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + else if((pBtLinkInfo->bScoExist) || (pBtLinkInfo->bHidExist) || (pBtLinkInfo->bA2dpExist)) + { + // SCO/HID/A2DP busy + halbtc8812a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else if ((pBtLinkInfo->bPanExist) || (bWifiBusy)) + { + halbtc8812a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 20); + + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else + { + halbtc8812a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8812a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } +} + +VOID +halbtc8812a1ant_ActionBtScoHidOnlyBusy( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte wifiStatus + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bWifiConnected=FALSE; + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + + // tdma and coex table + + if(pBtLinkInfo->bScoExist) + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 5); + } + else //HID + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 5); + } +} + +VOID +halbtc8812a1ant_ActionWifiConnectedBtAclBusy( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte wifiStatus + ) +{ + u1Byte btRssiState; + + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + btRssiState = halbtc8812a1ant_BtRssiState(2, 28, 0); + + if ( (pCoexSta->lowPriorityRx >= 950) && (!pCoexSta->bUnderIps) ) + { + pBtLinkInfo->bSlaveRole = TRUE; + } + else + { + pBtLinkInfo->bSlaveRole = FALSE; + } + + if(pBtLinkInfo->bHidOnly) //HID + { + halbtc8812a1ant_ActionBtScoHidOnlyBusy(pBtCoexist, wifiStatus); + pCoexDm->bAutoTdmaAdjust = FALSE; + return; + } + else if(pBtLinkInfo->bA2dpOnly) //A2DP + { + if(BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifiStatus) + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + pCoexDm->bAutoTdmaAdjust = FALSE; + } + else + { + halbtc8812a1ant_TdmaDurationAdjustForAcl(pBtCoexist, wifiStatus); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + pCoexDm->bAutoTdmaAdjust = TRUE; + } + } + else if ( ((pBtLinkInfo->bA2dpExist) && (pBtLinkInfo->bPanExist)) || + (pBtLinkInfo->bHidExist&&pBtLinkInfo->bA2dpExist&&pBtLinkInfo->bPanExist) ) //A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + pCoexDm->bAutoTdmaAdjust = FALSE; + } + else if(pBtLinkInfo->bHidExist&&pBtLinkInfo->bA2dpExist) //HID+A2DP + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->bAutoTdmaAdjust = FALSE; + + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 3); + } + else if( (pBtLinkInfo->bPanOnly) || (pBtLinkInfo->bHidExist&&pBtLinkInfo->bPanExist) ) //PAN(OPP,FTP), HID+PAN(OPP,FTP) + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + pCoexDm->bAutoTdmaAdjust = FALSE; + } + else + { + //BT no-profile busy (0x9) + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + pCoexDm->bAutoTdmaAdjust = FALSE; + } +} + +VOID +halbtc8812a1ant_ActionWifiNotConnected( + IN PBTC_COEXIST pBtCoexist + ) +{ + // power save state + halbtc8812a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + halbtc8812a1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8); + halbtc8812a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); +} + +VOID +halbtc8812a1ant_ActionWifiNotConnectedScan( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + + halbtc8812a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + if(BT_8812A_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) + { + if (pBtLinkInfo->bA2dpExist) + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else if (pBtLinkInfo->bA2dpExist && pBtLinkInfo->bPanExist) + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 22); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 20); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + } + else if( (BT_8812A_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + halbtc8812a1ant_ActionBtScoHidOnlyBusy(pBtCoexist, + BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN); + } + else + { + //Bryant Add + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8812a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + } +} + +VOID +halbtc8812a1ant_ActionWifiNotConnectedAssoAuth( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + + halbtc8812a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + if( (pBtLinkInfo->bScoExist) || (pBtLinkInfo->bHidExist) || (pBtLinkInfo->bA2dpExist) ) + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 4); + } + else if (pBtLinkInfo->bPanExist) + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 20); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 4); + } + else + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8812a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 2); + } +} + +VOID +halbtc8812a1ant_ActionWifiConnectedScan( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + + halbtc8812a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + if(BT_8812A_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) + { + if (pBtLinkInfo->bA2dpExist) + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else if (pBtLinkInfo->bA2dpExist && pBtLinkInfo->bPanExist) + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 22); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 20); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + } + else if( (BT_8812A_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + halbtc8812a1ant_ActionBtScoHidOnlyBusy(pBtCoexist, + BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN); + } + else + { + //Bryant Add + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8812a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + } +} + +VOID +halbtc8812a1ant_ActionWifiConnectedSpecialPacket( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + + halbtc8812a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + if((pBtLinkInfo->bScoExist) || (pBtLinkInfo->bHidExist) || (pBtLinkInfo->bA2dpExist)) + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else if(pBtLinkInfo->bPanExist) + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 20); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8812a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + } +} + +VOID +halbtc8812a1ant_ActionWifiConnected( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bWifiBusy=FALSE; + BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE; + BOOLEAN bUnder4way=FALSE, bApEnable=FALSE; + u4Byte wifiBw; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CoexForWifiConnect()===>\n")); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &bUnder4way); + if(bUnder4way) + { + halbtc8812a1ant_ActionWifiConnectedSpecialPacket(pBtCoexist); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n")); + return; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + if(bScan || bLink || bRoam) + { + if(bScan) + halbtc8812a1ant_ActionWifiConnectedScan(pBtCoexist); + else + halbtc8812a1ant_ActionWifiConnectedSpecialPacket(pBtCoexist); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n")); + return; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + + // power save state + if(!bApEnable && BT_8812A_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus && !pBtCoexist->btLinkInfo.bHidOnly) + { + if(pBtCoexist->btLinkInfo.bA2dpOnly) //A2DP + { + if(!bWifiBusy) + halbtc8812a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else //busy + { + if (pCoexSta->nScanAPNum >= BT_8812A_1ANT_WIFI_NOISY_THRESH) //no force LPS, no PS-TDMA, use pure TDMA + { + halbtc8812a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } + else + { + halbtc8812a1ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + } + } + } + else if ((pCoexSta->bPanExist == FALSE) && (pCoexSta->bA2dpExist == FALSE) && (pCoexSta->bHidExist == FALSE)) + halbtc8812a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else + halbtc8812a1ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + } + else + halbtc8812a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + if(!bWifiBusy) + { + if(BT_8812A_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) + { + halbtc8812a1ant_ActionWifiConnectedBtAclBusy(pBtCoexist, + BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE); + } + else if( (BT_8812A_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + halbtc8812a1ant_ActionBtScoHidOnlyBusy(pBtCoexist, + BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE); + } + else + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8812a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + if ( (pCoexSta->highPriorityTx) + (pCoexSta->highPriorityRx) <= 60 ) + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + } + else + { + if(BT_8812A_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) + { + halbtc8812a1ant_ActionWifiConnectedBtAclBusy(pBtCoexist, + BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY); + } + else if( (BT_8812A_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + halbtc8812a1ant_ActionBtScoHidOnlyBusy(pBtCoexist, + BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY); + } + else + { + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8812a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, NORMAL_EXEC, FALSE, FALSE); + if ( (pCoexSta->highPriorityTx) + (pCoexSta->highPriorityRx) <= 60 ) + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + } +} + +VOID +halbtc8812a1ant_RunSwCoexistMechanism( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte algorithm=0; + + algorithm = halbtc8812a1ant_ActionAlgorithm(pBtCoexist); + pCoexDm->curAlgorithm = algorithm; + + if(halbtc8812a1ant_IsCommonAction(pBtCoexist)) + { + + } + else + { + switch(pCoexDm->curAlgorithm) + { + case BT_8812A_1ANT_COEX_ALGO_SCO: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = SCO.\n")); + //halbtc8812a1ant_ActionSco(pBtCoexist); + break; + case BT_8812A_1ANT_COEX_ALGO_HID: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = HID.\n")); + //halbtc8812a1ant_ActionHid(pBtCoexist); + break; + case BT_8812A_1ANT_COEX_ALGO_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = A2DP.\n")); + //halbtc8812a1ant_ActionA2dp(pBtCoexist); + break; + case BT_8812A_1ANT_COEX_ALGO_A2DP_PANHS: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = A2DP+PAN(HS).\n")); + //halbtc8812a1ant_ActionA2dpPanHs(pBtCoexist); + break; + case BT_8812A_1ANT_COEX_ALGO_PANEDR: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = PAN(EDR).\n")); + //halbtc8812a1ant_ActionPanEdr(pBtCoexist); + break; + case BT_8812A_1ANT_COEX_ALGO_PANHS: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = HS mode.\n")); + //halbtc8812a1ant_ActionPanHs(pBtCoexist); + break; + case BT_8812A_1ANT_COEX_ALGO_PANEDR_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = PAN+A2DP.\n")); + //halbtc8812a1ant_ActionPanEdrA2dp(pBtCoexist); + break; + case BT_8812A_1ANT_COEX_ALGO_PANEDR_HID: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = PAN(EDR)+HID.\n")); + //halbtc8812a1ant_ActionPanEdrHid(pBtCoexist); + break; + case BT_8812A_1ANT_COEX_ALGO_HID_A2DP_PANEDR: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = HID+A2DP+PAN.\n")); + //halbtc8812a1ant_ActionHidA2dpPanEdr(pBtCoexist); + break; + case BT_8812A_1ANT_COEX_ALGO_HID_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = HID+A2DP.\n")); + //halbtc8812a1ant_ActionHidA2dp(pBtCoexist); + break; + default: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = coexist All Off!!\n")); + //halbtc8812a1ant_CoexAllOff(pBtCoexist); + break; + } + pCoexDm->preAlgorithm = pCoexDm->curAlgorithm; + } +} + +VOID +halbtc8812a1ant_RunCoexistMechanism( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bWifiConnected=FALSE, bBtHsOn=FALSE; + BOOLEAN bIncreaseScanDevNum=FALSE; + BOOLEAN bBtCtrlAggBufSize=FALSE; + BOOLEAN bMiracastPlusBt=FALSE; + u1Byte aggBufSize=5; + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiLinkStatus=0; + u4Byte numOfWifiLink=0, wifiBw; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism()===>\n")); + + if(pBtCoexist->bManualControl) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n")); + return; + } + + if(pBtCoexist->bStopCoexDm) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n")); + return; + } + + if(pCoexSta->bUnderIps) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi is under IPS !!!\n")); + return; + } + + if( (BT_8812A_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) || + (BT_8812A_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + bIncreaseScanDevNum = TRUE; + } + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, &bIncreaseScanDevNum); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_LINK_STATUS, &wifiLinkStatus); + numOfWifiLink = wifiLinkStatus>>16; + + if((numOfWifiLink>=2) || (wifiLinkStatus&WIFI_P2P_GO_CONNECTED)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], Multi-Port numOfWifiLink = %d, wifiLinkStatus = 0x%x\n", numOfWifiLink,wifiLinkStatus) ); + + if(pBtLinkInfo->bBtLinkExist) + { + halbtc8812a1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 1, 1, 0, 1); + bMiracastPlusBt = TRUE; + } + else + { + halbtc8812a1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + bMiracastPlusBt = FALSE; + } + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_MIRACAST_PLUS_BT, &bMiracastPlusBt); + halbtc8812a1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, bBtCtrlAggBufSize, aggBufSize); + + if ( (pBtLinkInfo->bA2dpExist) && (pCoexSta->bC2hBtInquiryPage) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], BT Is Inquirying \n") ); + halbtc8812a1ant_ActionBtInquiry(pBtCoexist); + } + else + halbtc8812a1ant_ActionWifiMultiPort(pBtCoexist); + + return; + } + else + { + bMiracastPlusBt = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_MIRACAST_PLUS_BT, &bMiracastPlusBt); + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if ( (pBtLinkInfo->bBtLinkExist) && (bWifiConnected) ) + { + halbtc8812a1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 1, 1, 0, 1); + + if(pBtLinkInfo->bScoExist) + halbtc8812a1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, TRUE, FALSE, 0x5); + else + { + if (BTC_WIFI_BW_HT40==wifiBw) + halbtc8812a1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, TRUE, 0x10); + else + halbtc8812a1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, TRUE, 0x8); + } + + halbtc8812a1ant_SwMechanism(pBtCoexist, TRUE); + halbtc8812a1ant_RunSwCoexistMechanism(pBtCoexist); //just print debug message + } + else + { + halbtc8812a1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + + halbtc8812a1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x5); + + halbtc8812a1ant_SwMechanism(pBtCoexist, FALSE); + halbtc8812a1ant_RunSwCoexistMechanism(pBtCoexist); ////just print debug message + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + if(pCoexSta->bC2hBtInquiryPage) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], BT Is Inquirying \n") ); + halbtc8812a1ant_ActionBtInquiry(pBtCoexist); + return; + } + else if(bBtHsOn) + { + halbtc8812a1ant_ActionHs(pBtCoexist); + return; + } + + + if(!bWifiConnected) + { + BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi is non connected-idle !!!\n")); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + + if(bScan || bLink || bRoam) + { + if (bScan) + halbtc8812a1ant_ActionWifiNotConnectedScan(pBtCoexist); + else + halbtc8812a1ant_ActionWifiNotConnectedAssoAuth(pBtCoexist); + } + else + halbtc8812a1ant_ActionWifiNotConnected(pBtCoexist); + } + else // wifi LPS/Busy + { + halbtc8812a1ant_ActionWifiConnected(pBtCoexist); + } +} + +VOID +halbtc8812a1ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + // force to reset coex mechanism + + // sw all off + halbtc8812a1ant_SwMechanism(pBtCoexist, FALSE); + + //halbtc8812a1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8); + //halbtc8812a1ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 0); + + pCoexSta->popEventCnt = 0; +} + +VOID +halbtc8812a1ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bBackUp, + IN BOOLEAN bWifiOnly + ) +{ + u4Byte u4Tmp=0; + u2Byte u2Tmp=0; + u1Byte u1Tmp=0; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 1Ant Init HW Config!!\n")); + + //ant sw control to BT + halbtc8812a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FORCE_EXEC, TRUE, FALSE); + + // 0x790[5:0]=0x5 + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x790); + u1Tmp &= 0xc0; + u1Tmp |= 0x5; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x790, u1Tmp); + + // PTA parameter + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cc, 0x0); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, 0xffff); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c4, 0x55555555); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c0, 0x55555555); + + // coex parameters + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x778, 0x1); + + // enable counter statistics + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0x4); + + // enable PTA + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x20); + + // bt clock related + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4); + u1Tmp |= BIT7; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x4, u1Tmp); + + // bt clock related + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x7); + u1Tmp |= BIT1; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x7, u1Tmp); +} + +//============================================================ +// work around function start with wa_halbtc8812a1ant_ +//============================================================ +//============================================================ +// extern function start with EXhalbtc8812a1ant_ +//============================================================ +VOID +EXhalbtc8812a1ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ) +{ +} + +VOID +EXhalbtc8812a1ant_PreLoadFirmware( + IN PBTC_COEXIST pBtCoexist + ) +{ +} + +VOID +EXhalbtc8812a1ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ) +{ + halbtc8812a1ant_InitHwConfig(pBtCoexist, TRUE, bWifiOnly); + pBtCoexist->bStopCoexDm = FALSE; +} + +VOID +EXhalbtc8812a1ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Coex Mechanism Init!!\n")); + + pBtCoexist->bStopCoexDm = FALSE; + + halbtc8812a1ant_InitCoexDm(pBtCoexist); + + halbtc8812a1ant_QueryBtInfo(pBtCoexist); +} + +VOID +EXhalbtc8812a1ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + pu1Byte cliBuf=pBtCoexist->cliBuf; + u1Byte u1Tmp[4], i, btInfoExt, psTdmaCase=0; + u4Byte u4Tmp[4]; + u4Byte fwVer=0, btPatchVer=0; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cliBuf); + + if(pBtCoexist->bManualControl) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[Under Manual Control]============"); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n =========================================="); + CL_PRINTF(cliBuf); + } + if(pBtCoexist->bStopCoexDm) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[Coex is STOPPED]============"); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n =========================================="); + CL_PRINTF(cliBuf); + } + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:", \ + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \ + ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion); + CL_PRINTF(cliBuf); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_BT_PATCH_VER, &btPatchVer); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)", "CoexVer/ FwVer/ PatchVer", \ + GLCoexVerDate8812a1Ant, GLCoexVer8812a1Ant, fwVer, btPatchVer, btPatchVer); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", "Wifi channel informed to BT", \ + pCoexDm->wifiChnlInfo[0], pCoexDm->wifiChnlInfo[1], + pCoexDm->wifiChnlInfo[2]); + CL_PRINTF(cliBuf); + + // wifi status + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Wifi Status]============"); + CL_PRINTF(cliBuf); + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[BT Status]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", "BT [status/ rssi/ retryCnt]", \ + ((pBtCoexist->btInfo.bBtDisabled)? ("disabled"): ((pCoexSta->bC2hBtInquiryPage)?("inquiry/page scan"):((BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus)? "non-connected idle": + ( (BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus)? "connected-idle":"busy")))), + pCoexSta->btRssi, pCoexSta->btRetryCnt); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP", \ + pBtLinkInfo->bScoExist, pBtLinkInfo->bHidExist, pBtLinkInfo->bPanExist, pBtLinkInfo->bA2dpExist); + CL_PRINTF(cliBuf); + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO); + + btInfoExt = pCoexSta->btInfoExt; + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Info A2DP rate", \ + (btInfoExt&BIT0)? "Basic rate":"EDR rate"); + CL_PRINTF(cliBuf); + + for(i=0; ibtInfoC2hCnt[i]) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", GLBtInfoSrc8812a1Ant[i], \ + pCoexSta->btInfoC2h[i][0], pCoexSta->btInfoC2h[i][1], + pCoexSta->btInfoC2h[i][2], pCoexSta->btInfoC2h[i][3], + pCoexSta->btInfoC2h[i][4], pCoexSta->btInfoC2h[i][5], + pCoexSta->btInfoC2h[i][6], pCoexSta->btInfoC2hCnt[i]); + CL_PRINTF(cliBuf); + } + } + + if(!pBtCoexist->bManualControl) + { + // Sw mechanism + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %d ", "DelBA/ BtCtrlAgg/ AggSize", \ + (pBtCoexist->btInfo.bRejectAggPkt? "Yes":"No"), (pBtCoexist->btInfo.bBtCtrlAggBufSize? "Yes":"No"), + pBtCoexist->btInfo.aggBufSize); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "Rate Mask", \ + pBtCoexist->btInfo.raMask); + CL_PRINTF(cliBuf); + + // Fw mechanism + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============"); + CL_PRINTF(cliBuf); + + psTdmaCase = pCoexDm->curPsTdma; + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x case-%d", "PS TDMA", \ + pCoexDm->psTdmaPara[0], pCoexDm->psTdmaPara[1], + pCoexDm->psTdmaPara[2], pCoexDm->psTdmaPara[3], + pCoexDm->psTdmaPara[4], psTdmaCase); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "Latest error condition(should be 0)", \ + pCoexDm->errorCondition); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ", "IgnWlanAct", \ + pCoexDm->bCurIgnoreWlanAct); + CL_PRINTF(cliBuf); + } + + // Hw setting + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============"); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x778); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x778", \ + u1Tmp[0]); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xcb3); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xcb7); + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x900); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0xcb3/0xcb7/0x900", \ + u1Tmp[0], u1Tmp[1], u4Tmp[0]); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x40); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x40", \ + u1Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x550); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x522); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x550(bcn ctrl)/0x522", \ + u4Tmp[0], u1Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc50); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", \ + u4Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c0); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c4); + u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c8); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x6cc); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", \ + u4Tmp[0], u4Tmp[1], u4Tmp[2], u1Tmp[0]); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x770(hp rx[31:16]/tx[15:0])", \ + pCoexSta->highPriorityRx, pCoexSta->highPriorityTx); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x774(lp rx[31:16]/tx[15:0])", \ + pCoexSta->lowPriorityRx, pCoexSta->lowPriorityTx); + CL_PRINTF(cliBuf); + + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + + + +VOID +EXhalbtc8812a1ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + u4Byte u4Tmp=0; + + if(pBtCoexist->bManualControl || pBtCoexist->bStopCoexDm) + return; + + if(BTC_IPS_ENTER == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS ENTER notify\n")); + pCoexSta->bUnderIps = TRUE; + + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + halbtc8812a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FORCE_EXEC, FALSE, TRUE); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + else if(BTC_IPS_LEAVE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS LEAVE notify\n")); + + halbtc8812a1ant_InitHwConfig(pBtCoexist, FALSE, FALSE); + halbtc8812a1ant_InitCoexDm(pBtCoexist); + halbtc8812a1ant_QueryBtInfo(pBtCoexist); + + pCoexSta->bUnderIps = FALSE; + } +} + +VOID +EXhalbtc8812a1ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(pBtCoexist->bManualControl || pBtCoexist->bStopCoexDm) + return; + + if(BTC_LPS_ENABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS ENABLE notify\n")); + pCoexSta->bUnderLps = TRUE; + } + else if(BTC_LPS_DISABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS DISABLE notify\n")); + pCoexSta->bUnderLps = FALSE; + } +} + +VOID +EXhalbtc8812a1ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + BOOLEAN bWifiConnected=FALSE, bBtHsOn=FALSE; + u4Byte wifiLinkStatus=0; + u4Byte numOfWifiLink=0; + BOOLEAN bBtCtrlAggBufSize=FALSE; + u1Byte aggBufSize=5; + + u1Byte u1Tmpa, u1Tmpb; + u4Byte u4Tmp; + + if(pBtCoexist->bManualControl || + pBtCoexist->bStopCoexDm ) + return; + + if(BTC_SCAN_START == type) + { + pCoexSta->bWiFiIsHighPriTask = TRUE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n")); + + halbtc8812a1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8); //Force antenna setup for no scan result issue + halbtc8812a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, FORCE_EXEC, FALSE, FALSE); + } + else + { + pCoexSta->bWiFiIsHighPriTask = FALSE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n")); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_AP_NUM, &pCoexSta->nScanAPNum); + } + + if(pBtCoexist->btInfo.bBtDisabled) + return; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + + halbtc8812a1ant_QueryBtInfo(pBtCoexist); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_LINK_STATUS, &wifiLinkStatus); + numOfWifiLink = wifiLinkStatus>>16; + if(numOfWifiLink >= 2) + { + halbtc8812a1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8812a1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, bBtCtrlAggBufSize, aggBufSize); + halbtc8812a1ant_ActionWifiMultiPort(pBtCoexist); + return; + } + + if(pCoexSta->bC2hBtInquiryPage) + { + halbtc8812a1ant_ActionBtInquiry(pBtCoexist); + return; + } + else if(bBtHsOn) + { + halbtc8812a1ant_ActionHs(pBtCoexist); + return; + } + + if(BTC_SCAN_START == type) + { + //RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n")); + if(!bWifiConnected) // non-connected scan + { + halbtc8812a1ant_ActionWifiNotConnectedScan(pBtCoexist); + } + else // wifi is connected + { + halbtc8812a1ant_ActionWifiConnectedScan(pBtCoexist); + } + } + else if(BTC_SCAN_FINISH == type) + { + //RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n")); + if(!bWifiConnected) // non-connected scan + { + halbtc8812a1ant_ActionWifiNotConnected(pBtCoexist); + } + else + { + halbtc8812a1ant_ActionWifiConnected(pBtCoexist); + } + } +} + +VOID +EXhalbtc8812a1ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + BOOLEAN bWifiConnected=FALSE, bBtHsOn=FALSE; + u4Byte wifiLinkStatus=0; + u4Byte numOfWifiLink=0; + BOOLEAN bBtCtrlAggBufSize=FALSE; + u1Byte aggBufSize=5; + + if(pBtCoexist->bManualControl || + pBtCoexist->bStopCoexDm || + pBtCoexist->btInfo.bBtDisabled ) + return; + + if(BTC_ASSOCIATE_START == type) + { + pCoexSta->bWiFiIsHighPriTask = TRUE; + halbtc8812a1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8); //Force antenna setup for no scan result issue + halbtc8812a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, FORCE_EXEC, FALSE, FALSE); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n")); + pCoexDm->nArpCnt = 0; + } + else + { + pCoexSta->bWiFiIsHighPriTask = FALSE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n")); + //pCoexDm->nArpCnt = 0; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_LINK_STATUS, &wifiLinkStatus); + numOfWifiLink = wifiLinkStatus>>16; + if(numOfWifiLink >= 2) + { + halbtc8812a1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8812a1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, bBtCtrlAggBufSize, aggBufSize); + halbtc8812a1ant_ActionWifiMultiPort(pBtCoexist); + return; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + if(pCoexSta->bC2hBtInquiryPage) + { + halbtc8812a1ant_ActionBtInquiry(pBtCoexist); + return; + } + else if(bBtHsOn) + { + halbtc8812a1ant_ActionHs(pBtCoexist); + return; + } + + if(BTC_ASSOCIATE_START == type) + { + //RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n")); + halbtc8812a1ant_ActionWifiNotConnectedAssoAuth(pBtCoexist); + } + else if(BTC_ASSOCIATE_FINISH == type) + { + //RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n")); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + if(!bWifiConnected) // non-connected scan + { + halbtc8812a1ant_ActionWifiNotConnected(pBtCoexist); + } + else + { + halbtc8812a1ant_ActionWifiConnected(pBtCoexist); + } + } +} + +//to check registers... +VOID +EXhalbtc8812a1ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + u1Byte dataLen=5; + u1Byte buf[6] = {0}; + u1Byte H2C_Parameter[3] ={0}; + u4Byte wifiBw; + u1Byte wifiCentralChnl; + BOOLEAN bWifiUnderBMode = FALSE; + + if(pBtCoexist->bManualControl || + pBtCoexist->bStopCoexDm || + pBtCoexist->btInfo.bBtDisabled ) + return; + + if(BTC_MEDIA_CONNECT == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA connect notify\n")); + halbtc8812a1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8); //Force antenna setup for no scan result issue + halbtc8812a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, FORCE_EXEC, FALSE, FALSE); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, &bWifiUnderBMode); +#if 0 + //Set CCK Tx/Rx high Pri except 11b mode + if (bWifiUnderBMode) + { + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cd, 0x00); //CCK Tx + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cf, 0x00); //CCK Rx + } + else + { + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cd, 0x10); //CCK Tx + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cf, 0x10); //CCK Rx + } +#endif + pCoexDm->backupArfrCnt1 = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x430); + pCoexDm->backupArfrCnt2 = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x434); + pCoexDm->backupRetryLimit = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0x42a); + pCoexDm->backupAmpduMaxTime = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x456); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA disconnect notify\n")); + pCoexDm->nArpCnt = 0; + + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cd, 0x0); //CCK Tx + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cf, 0x0); //CCK Rx + } + + // only 2.4G we need to inform bt the chnl mask + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, &wifiCentralChnl); + if( (BTC_MEDIA_CONNECT == type) && + (wifiCentralChnl <= 14) ) + { + //H2C_Parameter[0] = 0x1; + H2C_Parameter[0] = 0x0; + H2C_Parameter[1] = wifiCentralChnl; + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + H2C_Parameter[2] = 0x30; + else + H2C_Parameter[2] = 0x20; + } + + pCoexDm->wifiChnlInfo[0] = H2C_Parameter[0]; + pCoexDm->wifiChnlInfo[1] = H2C_Parameter[1]; + pCoexDm->wifiChnlInfo[2] = H2C_Parameter[2]; + + buf[0] = dataLen; + buf[1] = 0x5; // OP_Code + buf[2] = 0x3; // OP_Code_Length + buf[3] = H2C_Parameter[0]; // OP_Code_Content + buf[4] = H2C_Parameter[1]; + buf[5] = H2C_Parameter[2]; + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_CTRL_BT_COEX, (PVOID)&buf[0]); +} + +VOID +EXhalbtc8812a1ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + BOOLEAN bBtHsOn=FALSE; + u4Byte wifiLinkStatus=0; + u4Byte numOfWifiLink=0; + BOOLEAN bBtCtrlAggBufSize=FALSE; + u1Byte aggBufSize=5; + + if(pBtCoexist->bManualControl || + pBtCoexist->bStopCoexDm || + pBtCoexist->btInfo.bBtDisabled ) + return; + + if( BTC_PACKET_DHCP == type || + BTC_PACKET_EAPOL == type || + BTC_PACKET_ARP == type ) + { + if(BTC_PACKET_ARP == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], special Packet ARP notify\n")); + + pCoexDm->nArpCnt++; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ARP Packet Count = %d\n", pCoexDm->nArpCnt)); + + if(pCoexDm->nArpCnt >= 10) // if APR PKT > 10 after connect, do not go to ActionWifiConnectedSpecialPacket(pBtCoexist) + { + pCoexSta->bWiFiIsHighPriTask = FALSE; + } + else + { + pCoexSta->bWiFiIsHighPriTask = TRUE; + } + } + else + { + pCoexSta->bWiFiIsHighPriTask = TRUE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], special Packet DHCP or EAPOL notify\n")); + } + } + else + { + pCoexSta->bWiFiIsHighPriTask = FALSE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], special Packet [Type = %d] notify\n", type)); + } + + pCoexSta->specialPktPeriodCnt = 0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_LINK_STATUS, &wifiLinkStatus); + numOfWifiLink = wifiLinkStatus>>16; + if(numOfWifiLink >= 2) + { + halbtc8812a1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8812a1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, bBtCtrlAggBufSize, aggBufSize); + halbtc8812a1ant_ActionWifiMultiPort(pBtCoexist); + return; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + if(pCoexSta->bC2hBtInquiryPage) + { + halbtc8812a1ant_ActionBtInquiry(pBtCoexist); + return; + } + else if(bBtHsOn) + { + halbtc8812a1ant_ActionHs(pBtCoexist); + return; + } + + if( BTC_PACKET_DHCP == type || + BTC_PACKET_EAPOL == type || + ( (BTC_PACKET_ARP == type ) && (pCoexSta->bWiFiIsHighPriTask) ) ) + { + halbtc8812a1ant_ActionWifiConnectedSpecialPacket(pBtCoexist); + } +} + +VOID +EXhalbtc8812a1ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + u1Byte btInfo=0; + u1Byte i, rspSource=0; + BOOLEAN bWifiConnected=FALSE; + BOOLEAN bBtBusy=FALSE; + + pCoexSta->bC2hBtInfoReqSent = FALSE; + + rspSource = tmpBuf[0]&0xf; + if(rspSource >= BT_INFO_SRC_8812A_1ANT_MAX) + rspSource = BT_INFO_SRC_8812A_1ANT_WIFI_FW; + pCoexSta->btInfoC2hCnt[rspSource]++; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Bt info[%d], length=%d, hex data=[", rspSource, length)); + for(i=0; ibtInfoC2h[rspSource][i] = tmpBuf[i]; + if(i == 1) + btInfo = tmpBuf[i]; + if(i == length-1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x]\n", tmpBuf[i])); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x, ", tmpBuf[i])); + } + } + + if(BT_INFO_SRC_8812A_1ANT_WIFI_FW != rspSource) + { + pCoexSta->btRetryCnt = // [3:0] + pCoexSta->btInfoC2h[rspSource][2]&0xf; + + if (pCoexSta->btRetryCnt >= 1) + pCoexSta->popEventCnt++; + + if (pCoexSta->btInfoC2h[rspSource][2]&0x20) + pCoexSta->bC2hBtPage = TRUE; + else + pCoexSta->bC2hBtPage = FALSE; + + pCoexSta->btRssi = + pCoexSta->btInfoC2h[rspSource][3]*2-90; + //pCoexSta->btInfoC2h[rspSource][3]*2+10; + + pCoexSta->btInfoExt = + pCoexSta->btInfoC2h[rspSource][4]; + + pCoexSta->bBtTxRxMask = (pCoexSta->btInfoC2h[rspSource][2]&0x40); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TX_RX_MASK, &pCoexSta->bBtTxRxMask); + if(!pCoexSta->bBtTxRxMask) + { + /* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x15\n")); + pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x3c, 0x15); + } + + // Here we need to resend some wifi info to BT + // because bt is reset and loss of the info. + if(pCoexSta->btInfoExt & BIT1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n")); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + if(bWifiConnected) + { + EXhalbtc8812a1ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_CONNECT); + } + else + { + EXhalbtc8812a1ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); + } + } + + if(pCoexSta->btInfoExt & BIT3) + { + if(!pBtCoexist->bManualControl && !pBtCoexist->bStopCoexDm) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n")); + halbtc8812a1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE); + } + } + else + { + // BT already NOT ignore Wlan active, do nothing here. + } +#if(BT_AUTO_REPORT_ONLY_8812A_1ANT == 0) + if( (pCoexSta->btInfoExt & BIT4) ) + { + // BT auto report already enabled, do nothing + } + else + { + halbtc8812a1ant_BtAutoReport(pBtCoexist, FORCE_EXEC, TRUE); + } +#endif + } + + // check BIT2 first ==> check if bt is under inquiry or page scan + if(btInfo & BT_INFO_8812A_1ANT_B_INQ_PAGE) + pCoexSta->bC2hBtInquiryPage = TRUE; + else + pCoexSta->bC2hBtInquiryPage = FALSE; + + // set link exist status + if(!(btInfo&BT_INFO_8812A_1ANT_B_CONNECTION)) + { + pCoexSta->bBtLinkExist = FALSE; + pCoexSta->bPanExist = FALSE; + pCoexSta->bA2dpExist = FALSE; + pCoexSta->bHidExist = FALSE; + pCoexSta->bScoExist = FALSE; + } + else // connection exists + { + pCoexSta->bBtLinkExist = TRUE; + if(btInfo & BT_INFO_8812A_1ANT_B_FTP) + pCoexSta->bPanExist = TRUE; + else + pCoexSta->bPanExist = FALSE; + if(btInfo & BT_INFO_8812A_1ANT_B_A2DP) + pCoexSta->bA2dpExist = TRUE; + else + pCoexSta->bA2dpExist = FALSE; + if(btInfo & BT_INFO_8812A_1ANT_B_HID) + pCoexSta->bHidExist = TRUE; + else + pCoexSta->bHidExist = FALSE; + if(btInfo & BT_INFO_8812A_1ANT_B_SCO_ESCO) + pCoexSta->bScoExist = TRUE; + else + pCoexSta->bScoExist = FALSE; + } + + halbtc8812a1ant_UpdateBtLinkInfo(pBtCoexist); + + btInfo = btInfo & 0x1f; //mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) + + if(!(btInfo&BT_INFO_8812A_1ANT_B_CONNECTION)) + { + pCoexDm->btStatus = BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n")); + } + else if(btInfo == BT_INFO_8812A_1ANT_B_CONNECTION) // connection exists but no busy + { + pCoexDm->btStatus = BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n")); + } + else if((btInfo&BT_INFO_8812A_1ANT_B_SCO_ESCO) || + (btInfo&BT_INFO_8812A_1ANT_B_SCO_BUSY)) + { + pCoexDm->btStatus = BT_8812A_1ANT_BT_STATUS_SCO_BUSY; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT SCO busy!!!\n")); + } + else if(btInfo&BT_INFO_8812A_1ANT_B_ACL_BUSY) + { + if(BT_8812A_1ANT_BT_STATUS_ACL_BUSY != pCoexDm->btStatus) + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->btStatus = BT_8812A_1ANT_BT_STATUS_ACL_BUSY; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT ACL busy!!!\n")); + } + else + { + pCoexDm->btStatus = BT_8812A_1ANT_BT_STATUS_MAX; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n")); + } + + if( (BT_8812A_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) || + (BT_8812A_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + bBtBusy = TRUE; + else + bBtBusy = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bBtBusy); + + halbtc8812a1ant_RunCoexistMechanism(pBtCoexist); +} + +VOID +EXhalbtc8812a1ant_RfStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + u4Byte u4Tmp; + u1Byte u1Tmpa,u1Tmpb, u1Tmpc; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RF Status notify\n")); + + if(BTC_RF_ON == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RF is turned ON!!\n")); + pBtCoexist->bStopCoexDm = FALSE; + } + else if(BTC_RF_OFF == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RF is turned OFF!!\n")); + + halbtc8812a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); + halbtc8812a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FORCE_EXEC, FALSE, TRUE); + + halbtc8812a1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE); + pBtCoexist->bStopCoexDm = TRUE; + } +} + +VOID +EXhalbtc8812a1ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte u4Tmp; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Halt notify\n")); + + halbtc8812a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); + halbtc8812a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FORCE_EXEC, FALSE, TRUE); + + halbtc8812a1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE); + + EXhalbtc8812a1ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); + + pBtCoexist->bStopCoexDm = TRUE; +} + +VOID +EXhalbtc8812a1ant_PnpNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte pnpState + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Pnp notify\n")); + + if(BTC_WIFI_PNP_SLEEP == pnpState) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Pnp notify to SLEEP\n")); + + halbtc8812a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + halbtc8812a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FORCE_EXEC, FALSE, TRUE); + halbtc8812a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + + pBtCoexist->bStopCoexDm = TRUE; + } + else if(BTC_WIFI_PNP_WAKE_UP == pnpState) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Pnp notify to WAKE UP\n")); + pBtCoexist->bStopCoexDm = FALSE; + halbtc8812a1ant_InitHwConfig(pBtCoexist, FALSE, FALSE); + halbtc8812a1ant_InitCoexDm(pBtCoexist); + halbtc8812a1ant_QueryBtInfo(pBtCoexist); + } +} + +VOID +EXhalbtc8812a1ant_CoexDmReset( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], *****************Coex DM Reset*****************\n")); + + halbtc8812a1ant_InitHwConfig(pBtCoexist, FALSE, FALSE); + halbtc8812a1ant_InitCoexDm(pBtCoexist); +} + +VOID +EXhalbtc8812a1ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ) +{ + static u1Byte disVerInfoCnt=0; + u4Byte fwVer=0, btPatchVer=0; + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ==========================Periodical===========================\n")); + + if(disVerInfoCnt <= 5) + { + disVerInfoCnt += 1; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ****************************************************************\n")); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Ant PG Num/ Ant Mech/ Ant Pos = %d/ %d/ %d\n", + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum, pBoardInfo->btdmAntPos)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT stack/ hci ext ver = %s / %d\n", + ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion)); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_BT_PATCH_VER, &btPatchVer); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CoexVer/ FwVer/ PatchVer = %d_%x/ 0x%x/ 0x%x(%d)\n", + GLCoexVerDate8812a1Ant, GLCoexVer8812a1Ant, fwVer, btPatchVer, btPatchVer)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ****************************************************************\n")); + } + +#if(BT_AUTO_REPORT_ONLY_8812A_1ANT == 0) + halbtc8812a1ant_QueryBtInfo(pBtCoexist); + halbtc8812a1ant_MonitorBtEnableDisable(pBtCoexist); +#else + halbtc8812a1ant_MonitorBtCtr(pBtCoexist); + halbtc8812a1ant_MonitorWiFiCtr(pBtCoexist); + + if( halbtc8812a1ant_IsWifiStatusChanged(pBtCoexist) || + pCoexDm->bAutoTdmaAdjust ) + { + halbtc8812a1ant_RunCoexistMechanism(pBtCoexist); + } + + pCoexSta->specialPktPeriodCnt++; +#endif +} + +VOID +EXhalbtc8812a1ant_DbgControl( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte opCode, + IN u1Byte opLen, + IN pu1Byte pData + ) +{ + switch(opCode) + { + case BTC_DBG_SET_COEX_NORMAL: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Set CoexMode to Normal\n")); + pBtCoexist->bManualControl = FALSE; + halbtc8812a1ant_InitCoexDm(pBtCoexist); + break; + case BTC_DBG_SET_COEX_WIFI_ONLY: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Set CoexMode to Wifi Only\n")); + pBtCoexist->bManualControl = TRUE; + halbtc8812a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 9); + break; + case BTC_DBG_SET_COEX_BT_ONLY: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Set CoexMode to BT only\n")); + pBtCoexist->bManualControl = TRUE; + halbtc8812a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + break; + case BTC_DBG_SET_COEX_DEC_BT_PWR: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Set Dec BT power\n")); + { + u1Byte dataLen=4; + u1Byte buf[6] = {0}; + u1Byte decBtPwr=0, pwrLevel=0; + if(opLen == 2) + { + decBtPwr = pData[0]; + pwrLevel = pData[1]; + + buf[0] = dataLen; + buf[1] = 0x3; // OP_Code + buf[2] = 0x2; // OP_Code_Length + + buf[3] = decBtPwr; // OP_Code_Content + buf[4] = pwrLevel; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Set Dec BT power=%d, pwrLevel=%d\n", decBtPwr, pwrLevel)); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_CTRL_BT_COEX, (PVOID)&buf[0]); + } + } + break; + + case BTC_DBG_SET_COEX_BT_AFH_MAP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Set BT AFH Map\n")); + { + u1Byte dataLen=5; + u1Byte buf[6] = {0}; + if(opLen == 3) + { + buf[0] = dataLen; + buf[1] = 0x5; // OP_Code + buf[2] = 0x3; // OP_Code_Length + + buf[3] = pData[0]; // OP_Code_Content + buf[4] = pData[1]; + buf[5] = pData[2]; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Set BT AFH Map = %02x %02x %02x\n", + pData[0], pData[1], pData[2])); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_CTRL_BT_COEX, (PVOID)&buf[0]); + } + } + break; + + case BTC_DBG_SET_COEX_BT_IGNORE_WLAN_ACT: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Set BT Ignore Wlan Active\n")); + { + u1Byte dataLen=3; + u1Byte buf[6] = {0}; + if(opLen == 1) + { + buf[0] = dataLen; + buf[1] = 0x1; // OP_Code + buf[2] = 0x1; // OP_Code_Length + + buf[3] = pData[0]; // OP_Code_Content + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Set BT Ignore Wlan Active = 0x%x\n", + pData[0])); + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_CTRL_BT_COEX, (PVOID)&buf[0]); + } + } + break; + default: + break; + } +} + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8812a1Ant.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8812a1Ant.h new file mode 100644 index 000000000..3e2a5d324 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8812a1Ant.h @@ -0,0 +1,259 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//=========================================== +// The following is for 8812A 1ANT BT Co-exist definition +//=========================================== +#define BT_AUTO_REPORT_ONLY_8812A_1ANT 1 + +#define BT_INFO_8812A_1ANT_B_FTP BIT7 +#define BT_INFO_8812A_1ANT_B_A2DP BIT6 +#define BT_INFO_8812A_1ANT_B_HID BIT5 +#define BT_INFO_8812A_1ANT_B_SCO_BUSY BIT4 +#define BT_INFO_8812A_1ANT_B_ACL_BUSY BIT3 +#define BT_INFO_8812A_1ANT_B_INQ_PAGE BIT2 +#define BT_INFO_8812A_1ANT_B_SCO_ESCO BIT1 +#define BT_INFO_8812A_1ANT_B_CONNECTION BIT0 + +#define BT_INFO_8812A_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ + (((_BT_INFO_EXT_&BIT0))? TRUE:FALSE) + +#define BTC_RSSI_COEX_THRESH_TOL_8812A_1ANT 2 + +#define BT_8812A_1ANT_WIFI_NOISY_THRESH 30 //max: 255 + +typedef enum _BT_INFO_SRC_8812A_1ANT{ + BT_INFO_SRC_8812A_1ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8812A_1ANT_BT_RSP = 0x1, + BT_INFO_SRC_8812A_1ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8812A_1ANT_MAX +}BT_INFO_SRC_8812A_1ANT,*PBT_INFO_SRC_8812A_1ANT; + +typedef enum _BT_8812A_1ANT_BT_STATUS{ + BT_8812A_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8812A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8812A_1ANT_BT_STATUS_INQ_PAGE = 0x2, + BT_8812A_1ANT_BT_STATUS_ACL_BUSY = 0x3, + BT_8812A_1ANT_BT_STATUS_SCO_BUSY = 0x4, + BT_8812A_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, + BT_8812A_1ANT_BT_STATUS_MAX +}BT_8812A_1ANT_BT_STATUS,*PBT_8812A_1ANT_BT_STATUS; + +typedef enum _BT_8812A_1ANT_WIFI_STATUS{ + BT_8812A_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8812A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1, + BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2, + BT_8812A_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3, + BT_8812A_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4, + BT_8812A_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5, + BT_8812A_1ANT_WIFI_STATUS_MAX +}BT_8812A_1ANT_WIFI_STATUS,*PBT_8812A_1ANT_WIFI_STATUS; + +typedef enum _BT_8812A_1ANT_COEX_ALGO{ + BT_8812A_1ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8812A_1ANT_COEX_ALGO_SCO = 0x1, + BT_8812A_1ANT_COEX_ALGO_HID = 0x2, + BT_8812A_1ANT_COEX_ALGO_A2DP = 0x3, + BT_8812A_1ANT_COEX_ALGO_A2DP_PANHS = 0x4, + BT_8812A_1ANT_COEX_ALGO_PANEDR = 0x5, + BT_8812A_1ANT_COEX_ALGO_PANHS = 0x6, + BT_8812A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7, + BT_8812A_1ANT_COEX_ALGO_PANEDR_HID = 0x8, + BT_8812A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, + BT_8812A_1ANT_COEX_ALGO_HID_A2DP = 0xa, + BT_8812A_1ANT_COEX_ALGO_MAX = 0xb, +}BT_8812A_1ANT_COEX_ALGO,*PBT_8812A_1ANT_COEX_ALGO; + +typedef struct _COEX_DM_8812A_1ANT{ + // hw setting + u1Byte preAntPosType; + u1Byte curAntPosType; + // fw mechanism + BOOLEAN bCurIgnoreWlanAct; + BOOLEAN bPreIgnoreWlanAct; + u1Byte prePsTdma; + u1Byte curPsTdma; + u1Byte psTdmaPara[5]; + u1Byte psTdmaDuAdjType; + BOOLEAN bAutoTdmaAdjust; + BOOLEAN bPrePsTdmaOn; + BOOLEAN bCurPsTdmaOn; + BOOLEAN bPreBtAutoReport; + BOOLEAN bCurBtAutoReport; + u1Byte preLps; + u1Byte curLps; + u1Byte preRpwm; + u1Byte curRpwm; + + // sw mechanism + BOOLEAN bPreLowPenaltyRa; + BOOLEAN bCurLowPenaltyRa; + u4Byte preVal0x6c0; + u4Byte curVal0x6c0; + u4Byte preVal0x6c4; + u4Byte curVal0x6c4; + u4Byte preVal0x6c8; + u4Byte curVal0x6c8; + u1Byte preVal0x6cc; + u1Byte curVal0x6cc; + BOOLEAN bLimitedDig; + + u4Byte backupArfrCnt1; // Auto Rate Fallback Retry cnt + u4Byte backupArfrCnt2; // Auto Rate Fallback Retry cnt + u2Byte backupRetryLimit; + u1Byte backupAmpduMaxTime; + + // algorithm related + u1Byte preAlgorithm; + u1Byte curAlgorithm; + u1Byte btStatus; + u1Byte wifiChnlInfo[3]; + + u4Byte preRaMask; + u4Byte curRaMask; + u1Byte preArfrType; + u1Byte curArfrType; + u1Byte preRetryLimitType; + u1Byte curRetryLimitType; + u1Byte preAmpduTimeType; + u1Byte curAmpduTimeType; + u4Byte nArpCnt; + + u1Byte errorCondition; +} COEX_DM_8812A_1ANT, *PCOEX_DM_8812A_1ANT; + +typedef struct _COEX_STA_8812A_1ANT{ + BOOLEAN bBtLinkExist; + BOOLEAN bScoExist; + BOOLEAN bA2dpExist; + BOOLEAN bHidExist; + BOOLEAN bPanExist; + + BOOLEAN bUnderLps; + BOOLEAN bUnderIps; + u4Byte specialPktPeriodCnt; + u4Byte highPriorityTx; + u4Byte highPriorityRx; + u4Byte lowPriorityTx; + u4Byte lowPriorityRx; + s1Byte btRssi; + BOOLEAN bBtTxRxMask; + u1Byte preBtRssiState; + u1Byte preWifiRssiState[4]; + BOOLEAN bC2hBtInfoReqSent; + u1Byte btInfoC2h[BT_INFO_SRC_8812A_1ANT_MAX][10]; + u4Byte btInfoC2hCnt[BT_INFO_SRC_8812A_1ANT_MAX]; + u4Byte btInfoQueryCnt; + BOOLEAN bC2hBtInquiryPage; + BOOLEAN bC2hBtPage; //Add for win8.1 page out issue + BOOLEAN bWiFiIsHighPriTask; //Add for win8.1 page out issue + u1Byte btRetryCnt; + u1Byte btInfoExt; + u4Byte popEventCnt; + u1Byte nScanAPNum; + + u4Byte nCRCOK_CCK; + u4Byte nCRCOK_11g; + u4Byte nCRCOK_11n; + u4Byte nCRCOK_11nAgg; + + u4Byte nCRCErr_CCK; + u4Byte nCRCErr_11g; + u4Byte nCRCErr_11n; + u4Byte nCRCErr_11nAgg; + + BOOLEAN bCCKLock; + BOOLEAN bPreCCKLock; + u1Byte nCoexTableType; + + BOOLEAN bForceLpsOn; +}COEX_STA_8812A_1ANT, *PCOEX_STA_8812A_1ANT; + +//=========================================== +// The following is interface which will notify coex module. +//=========================================== +VOID +EXhalbtc8812a1ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8812a1ant_PreLoadFirmware( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8812a1ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ); +VOID +EXhalbtc8812a1ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8812a1ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8812a1ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8812a1ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8812a1ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8812a1ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8812a1ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8812a1ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ); +VOID +EXhalbtc8812a1ant_RfStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8812a1ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8812a1ant_PnpNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte pnpState + ); +VOID +EXhalbtc8812a1ant_CoexDmReset( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8812a1ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8812a1ant_DbgControl( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte opCode, + IN u1Byte opLen, + IN pu1Byte pData + ); +VOID +EXhalbtc8812a1ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ); + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8812a2Ant.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8812a2Ant.c new file mode 100644 index 000000000..d8f1b5720 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8812a2Ant.c @@ -0,0 +1,5435 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//============================================================ +// Description: +// +// This file is for RTL8812A Co-exist mechanism +// +// History +// 2012/08/22 Cosa first check in. +// 2012/11/14 Cosa Revise for 8812A 2Ant out sourcing. +// +//============================================================ + +//============================================================ +// include files +//============================================================ +#include "Mp_Precomp.h" + +#if WPP_SOFTWARE_TRACE +#include "HalBtc8812a2Ant.tmh" +#endif + +#if(BT_30_SUPPORT == 1) +//============================================================ +// Global variables, these are static variables +//============================================================ +static COEX_DM_8812A_2ANT GLCoexDm8812a2Ant; +static PCOEX_DM_8812A_2ANT pCoexDm=&GLCoexDm8812a2Ant; +static COEX_STA_8812A_2ANT GLCoexSta8812a2Ant; +static PCOEX_STA_8812A_2ANT pCoexSta=&GLCoexSta8812a2Ant; + +const char *const GLBtInfoSrc8812a2Ant[]={ + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; + +u4Byte GLCoexVerDate8812a2Ant=20150408; +u4Byte GLCoexVer8812a2Ant=0x39; +//improve 8761ATV D-cut BT off/on fail issue +//============================================================ +// local function proto type if needed +//============================================================ +//============================================================ +// local function start with halbtc8812a2ant_ +//============================================================ +u1Byte +halbtc8812a2ant_BtRssiState( + u1Byte levelNum, + u1Byte rssiThresh, + u1Byte rssiThresh1 + ) +{ + s4Byte btRssi=0; + u1Byte btRssiState=pCoexSta->preBtRssiState; + + btRssi = pCoexSta->btRssi; + + if(levelNum == 2) + { + if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW)) + { + if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT)) + { + btRssiState = BTC_RSSI_STATE_HIGH; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else + { + if(btRssi < rssiThresh) + { + btRssiState = BTC_RSSI_STATE_LOW; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + else if(levelNum == 3) + { + if(rssiThresh > rssiThresh1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Rssi thresh error!!\n")); + return pCoexSta->preBtRssiState; + } + + if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW)) + { + if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT)) + { + btRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_MEDIUM) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_MEDIUM)) + { + if(btRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT)) + { + btRssiState = BTC_RSSI_STATE_HIGH; + } + else if(btRssi < rssiThresh) + { + btRssiState = BTC_RSSI_STATE_LOW; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_MEDIUM; + } + } + else + { + if(btRssi < rssiThresh1) + { + btRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + + pCoexSta->preBtRssiState = btRssiState; + + return btRssiState; +} + +u1Byte +halbtc8812a2ant_WifiRssiState( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte index, + IN u1Byte levelNum, + IN u1Byte rssiThresh, + IN u1Byte rssiThresh1 + ) +{ + s4Byte wifiRssi=0; + u1Byte wifiRssiState=pCoexSta->preWifiRssiState[index]; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); + + if(levelNum == 2) + { + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else + { + if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + else if(levelNum == 3) + { + if(rssiThresh > rssiThresh1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi RSSI thresh error!!\n")); + return pCoexSta->preWifiRssiState[index]; + } + + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT)) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_MEDIUM) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_MEDIUM)) + { + if(wifiRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_MEDIUM; + } + } + else + { + if(wifiRssi < rssiThresh1) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + + pCoexSta->preWifiRssiState[index] = wifiRssiState; + + return wifiRssiState; +} + +VOID +halbtc8812a2ant_SetEnablePTA( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bEnablePTA + ) +{ + if(bEnablePTA) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PTA is enable!\n")); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x20); + + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PTA is disable!\n")); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x00); + + } +} + +VOID +halbtc8812a2ant_EnablePTA( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bEnable + ) +{ + RT_TRACE (COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Enable PTA %s\n", + (bForceExec? "force to":""), (bEnable? "ON":"OFF"))); + pCoexDm->bCurEnablePTA = bEnable; + + if(!bForceExec) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], bPreEnablePTA = %d, bCurEnablePTA = %d!!\n", + pCoexDm->bPreEnablePTA, pCoexDm->bCurEnablePTA)); + + if(pCoexDm->bPreEnablePTA == pCoexDm->bCurEnablePTA) + return; + } + halbtc8812a2ant_SetEnablePTA(pBtCoexist, bEnable); + + + pCoexDm->bPreEnablePTA = pCoexDm->bCurEnablePTA; +} + +VOID +halbtc8812a2ant_MonitorBtEnableDisable( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + static u4Byte btDisableCnt=0; + BOOLEAN bBtActive=TRUE, bBtDisabled=FALSE; + + // This function check if bt is disabled + + // only 8812a need to consider if core stack is installed. + if(!pStackInfo->hciVersion) + { + bBtActive = FALSE; + } +/* + if( pCoexSta->highPriorityTx == 0 && + pCoexSta->highPriorityRx == 0 && + pCoexSta->lowPriorityTx == 0 && + pCoexSta->lowPriorityRx == 0) + { + bBtActive = FALSE; + } + if( pCoexSta->highPriorityTx == 0xffff && + pCoexSta->highPriorityRx == 0xffff && + pCoexSta->lowPriorityTx == 0xffff && + pCoexSta->lowPriorityRx == 0xffff) + { + bBtActive = FALSE; + } +*/ + + if((pCoexSta->prebtInfoC2hCnt_BT_RSP == pCoexSta->btInfoC2hCnt[1]) && + (pCoexSta->prebtInfoC2hCnt_BT_SEND == pCoexSta->btInfoC2hCnt[2])) + { + bBtActive = FALSE; + } + + pCoexSta->prebtInfoC2hCnt_BT_RSP = pCoexSta->btInfoC2hCnt[1]; + pCoexSta->prebtInfoC2hCnt_BT_SEND = pCoexSta->btInfoC2hCnt[2]; + + if(bBtActive) + { + btDisableCnt = 0; + bBtDisabled = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is enabled !!\n")); + } + else + { + btDisableCnt++; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], bt is detected as disabled %d times!!\n", + btDisableCnt)); + if(btDisableCnt >= 2) + { + bBtDisabled = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is disabled !!\n")); + } + } + if(pCoexSta->preBtDisabled != bBtDisabled) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is from %s to %s!!\n", + (pCoexSta->preBtDisabled ? "disabled":"enabled"), + (bBtDisabled ? "disabled":"enabled"))); + pCoexSta->preBtDisabled = bBtDisabled; + + if(!bBtDisabled) + { + // enable PTA +// halbtc8812a2ant_EnablePTA(pBtCoexist,FORCE_EXEC, TRUE); + } + else + { + // disable PTA +// halbtc8812a2ant_EnablePTA(pBtCoexist,FORCE_EXEC, FALSE); + } + } +} + +u4Byte +halbtc8812a2ant_DecideRaMask( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte raMaskType + ) +{ + u4Byte disRaMask=0x0; + + switch(raMaskType) + { + case 0: // normal mode + disRaMask = 0x0; + break; + case 1: // disable cck 1/2 + disRaMask = 0x00000003; + break; + case 2: // disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 + disRaMask = 0x0001f1f7; + break; + default: + break; + } + + return disRaMask; +} + +VOID +halbtc8812a2ant_UpdateRaMask( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u4Byte disRateMask + ) +{ + pCoexDm->curRaMask = disRateMask; + + if( bForceExec || (pCoexDm->preRaMask != pCoexDm->curRaMask)) + { + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_UPDATE_RAMASK, &pCoexDm->curRaMask); + } + pCoexDm->preRaMask = pCoexDm->curRaMask; +} + +VOID +halbtc8812a2ant_AutoRateFallbackRetry( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + BOOLEAN bWifiUnderBMode=FALSE; + + pCoexDm->curArfrType = type; + + if( bForceExec || (pCoexDm->preArfrType != pCoexDm->curArfrType)) + { + switch(pCoexDm->curArfrType) + { + case 0: // normal mode + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x430, pCoexDm->backupArfrCnt1); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x434, pCoexDm->backupArfrCnt2); + break; + case 1: + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, &bWifiUnderBMode); + if(bWifiUnderBMode) + { + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x430, 0x0); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x434, 0x01010101); + } + else + { + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x430, 0x0); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x434, 0x04030201); + } + break; + default: + break; + } + } + + pCoexDm->preArfrType = pCoexDm->curArfrType; +} + +VOID +halbtc8812a2ant_RetryLimit( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + pCoexDm->curRetryLimitType = type; + + if( bForceExec || (pCoexDm->preRetryLimitType != pCoexDm->curRetryLimitType)) + { + switch(pCoexDm->curRetryLimitType) + { + case 0: // normal mode + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x42a, pCoexDm->backupRetryLimit); + break; + case 1: // retry limit=8 + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x42a, 0x0808); + break; + default: + break; + } + } + + pCoexDm->preRetryLimitType = pCoexDm->curRetryLimitType; +} + +VOID +halbtc8812a2ant_AmpduMaxTime( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + pCoexDm->curAmpduTimeType = type; + + if( bForceExec || (pCoexDm->preAmpduTimeType != pCoexDm->curAmpduTimeType)) + { + switch(pCoexDm->curAmpduTimeType) + { + case 0: // normal mode + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x456, pCoexDm->backupAmpduMaxTime); + break; + case 1: // AMPDU timw = 0x38 * 32us + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x456, 0x38); + break; + default: + break; + } + } + + pCoexDm->preAmpduTimeType = pCoexDm->curAmpduTimeType; +} + +VOID +halbtc8812a2ant_LimitedTx( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte raMaskType, + IN u1Byte arfrType, + IN u1Byte retryLimitType, + IN u1Byte ampduTimeType + ) +{ + u4Byte disRaMask=0x0; + + pCoexDm->curRaMaskType = raMaskType; + disRaMask = halbtc8812a2ant_DecideRaMask(pBtCoexist, raMaskType); + halbtc8812a2ant_UpdateRaMask(pBtCoexist, bForceExec, disRaMask); + + halbtc8812a2ant_AutoRateFallbackRetry(pBtCoexist, bForceExec, arfrType); + halbtc8812a2ant_RetryLimit(pBtCoexist, bForceExec, retryLimitType); + halbtc8812a2ant_AmpduMaxTime(pBtCoexist, bForceExec, ampduTimeType); +} + +VOID +halbtc8812a2ant_LimitedRx( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bRejApAggPkt, + IN BOOLEAN bBtCtrlAggBufSize, + IN u1Byte aggBufSize + ) +{ + BOOLEAN bRejectRxAgg=bRejApAggPkt; + BOOLEAN bBtCtrlRxAggSize=bBtCtrlAggBufSize; + u1Byte rxAggSize=aggBufSize; + + //============================================ + // Rx Aggregation related setting + //============================================ + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, &bRejectRxAgg); + // decide BT control aggregation buf size or not + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, &bBtCtrlRxAggSize); + // aggregation buf size, only work when BT control Rx aggregation size. + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_AGG_BUF_SIZE, &rxAggSize); + // real update aggregation setting + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); + + +} + +VOID +halbtc8812a2ant_MonitorBtCtr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte regHPTxRx, regLPTxRx, u4Tmp; + u4Byte regHPTx=0, regHPRx=0, regLPTx=0, regLPRx=0; + u1Byte u1Tmp; + + regHPTxRx = 0x770; + regLPTxRx = 0x774; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regHPTxRx); + regHPTx = u4Tmp & bMaskLWord; + regHPRx = (u4Tmp & bMaskHWord)>>16; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regLPTxRx); + regLPTx = u4Tmp & bMaskLWord; + regLPRx = (u4Tmp & bMaskHWord)>>16; + + pCoexSta->highPriorityTx = regHPTx; + pCoexSta->highPriorityRx = regHPRx; + pCoexSta->lowPriorityTx = regLPTx; + pCoexSta->lowPriorityRx = regLPRx; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", + regHPTxRx, regHPTx, regHPTx, regHPRx, regHPRx)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", + regLPTxRx, regLPTx, regLPTx, regLPRx, regLPRx)); + + // reset counter + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0xc); +} + +VOID +halbtc8812a2ant_QueryBtInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte dataLen=3; + u1Byte buf[5] = {0}; +//8812a watch btifo to check BT enable/disable +// if(!pBtCoexist->btInfo.bBtDisabled) + { + if(!pCoexSta->btInfoQueryCnt || + (pCoexSta->btInfoC2hCnt[BT_INFO_SRC_8812A_2ANT_BT_RSP]-pCoexSta->btInfoQueryCnt)>2) + { + buf[0] = dataLen; + buf[1] = 0x1; // polling enable, 1=enable, 0=disable + buf[2] = 0x2; // polling time in seconds + buf[3] = 0x1; // auto report enable, 1=enable, 0=disable + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_CTRL_BT_INFO, (PVOID)&buf[0]); + } + } + pCoexSta->btInfoQueryCnt++; +} + +BOOLEAN +halbtc8812a2ant_IsWifiStatusChanged( + IN PBTC_COEXIST pBtCoexist + ) +{ + static BOOLEAN bPreWifiBusy=FALSE, bPreUnder4way=FALSE, bPreBtHsOn=FALSE; + BOOLEAN bWifiBusy=FALSE, bUnder4way=FALSE, bBtHsOn=FALSE; + BOOLEAN bWifiConnected=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &bUnder4way); + + if(bWifiConnected) + { + if(bWifiBusy != bPreWifiBusy) + { + bPreWifiBusy = bWifiBusy; + return TRUE; + } + if(bUnder4way != bPreUnder4way) + { + bPreUnder4way = bUnder4way; + return TRUE; + } + if(bBtHsOn != bPreBtHsOn) + { + bPreBtHsOn = bBtHsOn; + return TRUE; + } + } + + return FALSE; +} + +VOID +halbtc8812a2ant_UpdateBtLinkInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bBtHsOn=FALSE; + +#if 1//(BT_AUTO_REPORT_ONLY_8812A_2ANT == 1) // profile from bt patch + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + pBtLinkInfo->bBtLinkExist = pCoexSta->bBtLinkExist; + pBtLinkInfo->bScoExist = pCoexSta->bScoExist; + pBtLinkInfo->bA2dpExist = pCoexSta->bA2dpExist; + pBtLinkInfo->bPanExist = pCoexSta->bPanExist; + pBtLinkInfo->bHidExist = pCoexSta->bHidExist; + pBtLinkInfo->bAclBusy = pCoexSta->bAclBusy; + + // work around for HS mode. + if(bBtHsOn) + { + pBtLinkInfo->bPanExist = TRUE; + pBtLinkInfo->bBtLinkExist = TRUE; + } +#else // profile from bt stack + pBtLinkInfo->bBtLinkExist = pStackInfo->bBtLinkExist; + pBtLinkInfo->bScoExist = pStackInfo->bScoExist; + pBtLinkInfo->bA2dpExist = pStackInfo->bA2dpExist; + pBtLinkInfo->bPanExist = pStackInfo->bPanExist; + pBtLinkInfo->bHidExist = pStackInfo->bHidExist; + + //for win-8 stack HID report error + if(!pStackInfo->bHidExist) + pStackInfo->bHidExist = pCoexSta->bHidExist; //sync BTInfo with BT firmware and stack + // when stack HID report error, here we use the info from bt fw. + if(!pStackInfo->bBtLinkExist) + pStackInfo->bBtLinkExist = pCoexSta->bBtLinkExist; +#endif + // check if Sco only + if( pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bScoOnly = TRUE; + else + pBtLinkInfo->bScoOnly = FALSE; + + // check if A2dp only + if( !pBtLinkInfo->bScoExist && + pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bA2dpOnly = TRUE; + else + pBtLinkInfo->bA2dpOnly = FALSE; + + // check if Pan only + if( !pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bPanOnly = TRUE; + else + pBtLinkInfo->bPanOnly = FALSE; + + // check if Hid only + if( !pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + pBtLinkInfo->bHidExist ) + pBtLinkInfo->bHidOnly = TRUE; + else + pBtLinkInfo->bHidOnly = FALSE; +} + +u1Byte +halbtc8812a2ant_ActionAlgorithm( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + BOOLEAN bBtHsOn=FALSE; + u1Byte algorithm=BT_8812A_2ANT_COEX_ALGO_UNDEFINED; + u1Byte numOfDiffProfile=0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + if(!pBtLinkInfo->bBtLinkExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], No BT link exists!!!\n")); + return algorithm; + } + + if(pBtLinkInfo->bScoExist) + numOfDiffProfile++; + if(pBtLinkInfo->bHidExist) + numOfDiffProfile++; + if(pBtLinkInfo->bPanExist) + numOfDiffProfile++; + if(pBtLinkInfo->bA2dpExist) + numOfDiffProfile++; + + if(numOfDiffProfile == 0) + { + if(pBtLinkInfo->bAclBusy) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ACL Busy only\n")); + algorithm = BT_8812A_2ANT_COEX_ALGO_PANEDR; + } + } + else if(numOfDiffProfile == 1) + { + if(pBtLinkInfo->bScoExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO only\n")); + algorithm = BT_8812A_2ANT_COEX_ALGO_SCO; + } + else + { + if(pBtLinkInfo->bHidExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID only\n")); + algorithm = BT_8812A_2ANT_COEX_ALGO_HID; + } + else if(pBtLinkInfo->bA2dpExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP only\n")); + algorithm = BT_8812A_2ANT_COEX_ALGO_A2DP; + } + else if(pBtLinkInfo->bPanExist) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN(HS) only\n")); + algorithm = BT_8812A_2ANT_COEX_ALGO_PANHS; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN(EDR) only\n")); + algorithm = BT_8812A_2ANT_COEX_ALGO_PANEDR; + } + } + } + } + else if(numOfDiffProfile == 2) + { + if(pBtLinkInfo->bScoExist) + { + if(pBtLinkInfo->bHidExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID\n")); + algorithm = BT_8812A_2ANT_COEX_ALGO_SCO_HID; + } + else if(pBtLinkInfo->bA2dpExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + A2DP ==> SCO\n")); + algorithm = BT_8812A_2ANT_COEX_ALGO_PANEDR_HID; + } + else if(pBtLinkInfo->bPanExist) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + PAN(HS)\n")); + algorithm = BT_8812A_2ANT_COEX_ALGO_SCO; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + PAN(EDR)\n")); + algorithm = BT_8812A_2ANT_COEX_ALGO_SCO; + } + } + } + else + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bA2dpExist ) + { + if(pStackInfo->numOfHid >= 2) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID*2 + A2DP\n")); + algorithm = BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP\n")); + algorithm = BT_8812A_2ANT_COEX_ALGO_HID_A2DP; + } + } + else if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + PAN(HS)\n")); + algorithm = BT_8812A_2ANT_COEX_ALGO_HID; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + PAN(EDR)\n")); + algorithm = BT_8812A_2ANT_COEX_ALGO_PANEDR_HID; + } + } + else if( pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP + PAN(HS)\n")); + algorithm = BT_8812A_2ANT_COEX_ALGO_A2DP_PANHS; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP + PAN(EDR)\n")); + algorithm = BT_8812A_2ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } + } + else if(numOfDiffProfile == 3) + { + if(pBtLinkInfo->bScoExist) + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bA2dpExist ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + A2DP ==> HID\n")); + algorithm = BT_8812A_2ANT_COEX_ALGO_PANEDR_HID; + } + else if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + PAN(HS)\n")); + algorithm = BT_8812A_2ANT_COEX_ALGO_SCO_HID; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + PAN(EDR)\n")); + algorithm = BT_8812A_2ANT_COEX_ALGO_SCO_HID; + } + } + else if( pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + A2DP + PAN(HS)\n")); + algorithm = BT_8812A_2ANT_COEX_ALGO_SCO; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n")); + algorithm = BT_8812A_2ANT_COEX_ALGO_PANEDR_HID; + } + } + } + else + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP + PAN(HS)\n")); + algorithm = BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANHS; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP + PAN(EDR)\n")); + algorithm = BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } + else if(numOfDiffProfile >= 3) + { + if(pBtLinkInfo->bScoExist) + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n")); + + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n")); + algorithm = BT_8812A_2ANT_COEX_ALGO_PANEDR_HID; + } + } + } + } + + return algorithm; +} + +VOID +halbtc8812a2ant_SetFwDacSwingLevel( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte dacSwingLvl + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + // There are several type of dacswing + // 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 + H2C_Parameter[0] = dacSwingLvl; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Set Dac Swing Level=0x%x\n", dacSwingLvl)); + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x64=0x%x\n", H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x64, 1, H2C_Parameter); +} + +VOID +halbtc8812a2ant_SetFwDecBtPwr( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte decBtPwrLvl + ) +{ + u1Byte dataLen=4; + u1Byte buf[6] = {0}; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], decrease Bt Power level = %d\n", + decBtPwrLvl)); + + buf[0] = dataLen; + buf[1] = 0x3; // OP_Code + buf[2] = 0x2; // OP_Code_Length + if(decBtPwrLvl) + buf[3] = 0x1; // OP_Code_Content + else + buf[3] = 0x0; + buf[4] = decBtPwrLvl;// pwrLevel + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_CTRL_BT_COEX, (PVOID)&buf[0]); +} + +VOID +halbtc8812a2ant_DecBtPwr( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte decBtPwrLvl + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s Dec BT power level = %d\n", + (bForceExec? "force to":""), decBtPwrLvl)); + pCoexDm->curBtDecPwrLvl = decBtPwrLvl; + + if(!bForceExec) + { + if(pCoexDm->preBtDecPwrLvl == pCoexDm->curBtDecPwrLvl) + return; + } + halbtc8812a2ant_SetFwDecBtPwr(pBtCoexist, pCoexDm->curBtDecPwrLvl); + + pCoexDm->preBtDecPwrLvl = pCoexDm->curBtDecPwrLvl; +} + +VOID +halbtc8812a2ant_FwDacSwingLvl( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte fwDacSwingLvl + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s set FW Dac Swing level = %d\n", + (bForceExec? "force to":""), fwDacSwingLvl)); + pCoexDm->curFwDacSwingLvl = fwDacSwingLvl; + + if(!bForceExec) + { + if(pCoexDm->preFwDacSwingLvl == pCoexDm->curFwDacSwingLvl) + return; + } + + halbtc8812a2ant_SetFwDacSwingLevel(pBtCoexist, pCoexDm->curFwDacSwingLvl); + + pCoexDm->preFwDacSwingLvl = pCoexDm->curFwDacSwingLvl; +} + +VOID +halbtc8812a2ant_SetSwRfRxLpfCorner( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bRxRfShrinkOn + ) +{ + if(bRxRfShrinkOn) + { + //Shrink RF Rx LPF corner + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Shrink RF Rx LPF corner!!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, 0xffffc); + } + else + { + //Resume RF Rx LPF corner + // After initialized, we can use pCoexDm->btRf0x1eBackup + if(pBtCoexist->bInitilized) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Resume RF Rx LPF corner!!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, pCoexDm->btRf0x1eBackup); + } + } +} + +VOID +halbtc8812a2ant_RfShrink( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bRxRfShrinkOn + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Rx RF Shrink = %s\n", + (bForceExec? "force to":""), ((bRxRfShrinkOn)? "ON":"OFF"))); + pCoexDm->bCurRfRxLpfShrink = bRxRfShrinkOn; + + if(!bForceExec) + { + if(pCoexDm->bPreRfRxLpfShrink == pCoexDm->bCurRfRxLpfShrink) + return; + } + halbtc8812a2ant_SetSwRfRxLpfCorner(pBtCoexist, pCoexDm->bCurRfRxLpfShrink); + + pCoexDm->bPreRfRxLpfShrink = pCoexDm->bCurRfRxLpfShrink; +} + +VOID +halbtc8812a2ant_SetSwPenaltyTxRateAdaptive( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bLowPenaltyRa + ) +{ + u1Byte tmpU1; + + tmpU1 = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4fd); + tmpU1 |= BIT0; + if(bLowPenaltyRa) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set low penalty!!\n")); + tmpU1 &= ~BIT2; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Tx rate adaptive, set normal!!\n")); + tmpU1 |= BIT2; + } + + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x4fd, tmpU1); +} + +VOID +halbtc8812a2ant_LowPenaltyRa( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bLowPenaltyRa + ) +{ + return; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn LowPenaltyRA = %s\n", + (bForceExec? "force to":""), ((bLowPenaltyRa)? "ON":"OFF"))); + pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa; + + if(!bForceExec) + { + if(pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa) + return; + } + halbtc8812a2ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa); + + pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa; +} + +VOID +halbtc8812a2ant_SetDacSwingReg( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte level + ) +{ + u1Byte val=(u1Byte)level; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Write SwDacSwing = 0x%x\n", level)); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xc5b, 0x3e, val); +} + +VOID +halbtc8812a2ant_SetSwFullTimeDacSwing( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bSwDacSwingOn, + IN u4Byte swDacSwingLvl + ) +{ + if(bSwDacSwingOn) + { + halbtc8812a2ant_SetDacSwingReg(pBtCoexist, swDacSwingLvl); + } + else + { + halbtc8812a2ant_SetDacSwingReg(pBtCoexist, 0x18); + } +} + + +VOID +halbtc8812a2ant_DacSwing( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bDacSwingOn, + IN u4Byte dacSwingLvl + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn DacSwing=%s, dacSwingLvl=0x%x\n", + (bForceExec? "force to":""), ((bDacSwingOn)? "ON":"OFF"), dacSwingLvl)); + pCoexDm->bCurDacSwingOn = bDacSwingOn; + pCoexDm->curDacSwingLvl = dacSwingLvl; + + if(!bForceExec) + { + if( (pCoexDm->bPreDacSwingOn == pCoexDm->bCurDacSwingOn) && + (pCoexDm->preDacSwingLvl == pCoexDm->curDacSwingLvl) ) + return; + } + delay_ms(30); + halbtc8812a2ant_SetSwFullTimeDacSwing(pBtCoexist, bDacSwingOn, dacSwingLvl); + + pCoexDm->bPreDacSwingOn = pCoexDm->bCurDacSwingOn; + pCoexDm->preDacSwingLvl = pCoexDm->curDacSwingLvl; +} + +VOID +halbtc8812a2ant_SetAdcBackOff( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bAdcBackOff + ) +{ + if(bAdcBackOff) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level On!\n")); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x8db, 0x60, 0x3); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level Off!\n")); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x8db, 0x60, 0x1); + } +} + +VOID +halbtc8812a2ant_AdcBackOff( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bAdcBackOff + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn AdcBackOff = %s\n", + (bForceExec? "force to":""), ((bAdcBackOff)? "ON":"OFF"))); + pCoexDm->bCurAdcBackOff = bAdcBackOff; + + if(!bForceExec) + { + if(pCoexDm->bPreAdcBackOff == pCoexDm->bCurAdcBackOff) + return; + } + halbtc8812a2ant_SetAdcBackOff(pBtCoexist, pCoexDm->bCurAdcBackOff); + + pCoexDm->bPreAdcBackOff = pCoexDm->bCurAdcBackOff; +} + +VOID +halbtc8812a2ant_SetAgcTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bAgcTableEn + ) +{ + u1Byte rssiAdjustVal=0; + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000); + if(bAgcTableEn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table On!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x28F4B); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x10AB2); + rssiAdjustVal = 8; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table Off!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x2884B); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x104B2); + } + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xef, 0xfffff, 0x0); + + // set rssiAdjustVal for wifi module. + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, &rssiAdjustVal); +} + +VOID +halbtc8812a2ant_AgcTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bAgcTableEn + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s %s Agc Table\n", + (bForceExec? "force to":""), ((bAgcTableEn)? "Enable":"Disable"))); + pCoexDm->bCurAgcTableEn = bAgcTableEn; + + if(!bForceExec) + { + if(pCoexDm->bPreAgcTableEn == pCoexDm->bCurAgcTableEn) + return; + } + halbtc8812a2ant_SetAgcTable(pBtCoexist, bAgcTableEn); + + pCoexDm->bPreAgcTableEn = pCoexDm->bCurAgcTableEn; +} + +VOID +halbtc8812a2ant_SetCoexTable( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte val0x6c0, + IN u4Byte val0x6c4, + IN u4Byte val0x6c8, + IN u1Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c0=0x%x\n", val0x6c0)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c0, val0x6c0); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c4=0x%x\n", val0x6c4)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c4, val0x6c4); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, val0x6c8); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc)); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cc, val0x6cc); +} + +VOID +halbtc8812a2ant_CoexTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u4Byte val0x6c0, + IN u4Byte val0x6c4, + IN u4Byte val0x6c8, + IN u1Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s write Coex Table 0x6c0=0x%x, 0x6c4=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n", + (bForceExec? "force to":""), val0x6c0, val0x6c4, val0x6c8, val0x6cc)); + pCoexDm->curVal0x6c0 = val0x6c0; + pCoexDm->curVal0x6c4 = val0x6c4; + pCoexDm->curVal0x6c8 = val0x6c8; + pCoexDm->curVal0x6cc = val0x6cc; + + if(!bForceExec) + { + if( (pCoexDm->preVal0x6c0 == pCoexDm->curVal0x6c0) && + (pCoexDm->preVal0x6c4 == pCoexDm->curVal0x6c4) && + (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) && + (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) ) + return; + } + halbtc8812a2ant_SetCoexTable(pBtCoexist, val0x6c0, val0x6c4, val0x6c8, val0x6cc); + + pCoexDm->preVal0x6c0 = pCoexDm->curVal0x6c0; + pCoexDm->preVal0x6c4 = pCoexDm->curVal0x6c4; + pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8; + pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc; +} + +VOID +halbtc8812a2ant_CoexTableWithType( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + switch(type) + { + case 0: + halbtc8812a2ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 1: + halbtc8812a2ant_CoexTable(pBtCoexist, bForceExec, 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 2: + halbtc8812a2ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x5ffb5ffb, 0xffffff, 0x3); + break; + case 3: + halbtc8812a2ant_CoexTable(pBtCoexist, bForceExec, 0x5fdf5fdf, 0x5fdb5fdb, 0xffffff, 0x3); + break; + case 4: + halbtc8812a2ant_CoexTable(pBtCoexist, bForceExec, 0xdfffdfff, 0x5fdb5fdb, 0xffffff, 0x3); + break; + case 5: + halbtc8812a2ant_CoexTable(pBtCoexist, bForceExec, 0x5ddd5ddd, 0x5fdb5fdb, 0xffffff, 0x3); + break; + case 6: + halbtc8812a2ant_CoexTable(pBtCoexist, bForceExec, 0x5fff5fff, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 7: + if(pCoexSta->nScanAPNum <= 5) + halbtc8812a2ant_CoexTable(pBtCoexist, bForceExec, 0xffffffff, 0xfafafafa, 0xffffff, 0x3); + else + halbtc8812a2ant_CoexTable(pBtCoexist, bForceExec, 0xffffffff, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 8: + halbtc8812a2ant_CoexTable(pBtCoexist, bForceExec, 0x5f5f5f5f, 0x5a5a5a5a, 0xffffff, 0x3); + break; + + default: + break; + } +} + +VOID +halbtc8812a2ant_SetFwIgnoreWlanAct( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bEnable + ) +{ + u1Byte dataLen=3; + u1Byte buf[5] = {0}; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s BT Ignore Wlan_Act\n", + (bEnable? "Enable":"Disable"))); + + buf[0] = dataLen; + buf[1] = 0x1; // OP_Code + buf[2] = 0x1; // OP_Code_Length + if(bEnable) + buf[3] = 0x1; // OP_Code_Content + else + buf[3] = 0x0; + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_CTRL_BT_COEX, (PVOID)&buf[0]); +} + +VOID +halbtc8812a2ant_IgnoreWlanAct( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bEnable + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Ignore WlanAct %s\n", + (bForceExec? "force to":""), (bEnable? "ON":"OFF"))); + pCoexDm->bCurIgnoreWlanAct = bEnable; + + if(!bForceExec) + { + if(pCoexDm->bPreIgnoreWlanAct == pCoexDm->bCurIgnoreWlanAct) + return; + } + halbtc8812a2ant_SetFwIgnoreWlanAct(pBtCoexist, bEnable); + + pCoexDm->bPreIgnoreWlanAct = pCoexDm->bCurIgnoreWlanAct; +} + +VOID +halbtc8812a2ant_SetFwPstdma( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte byte1, + IN u1Byte byte2, + IN u1Byte byte3, + IN u1Byte byte4, + IN u1Byte byte5 + ) +{ + u1Byte H2C_Parameter[5] ={0}; + u1Byte realByte1=byte1, realByte5=byte5; + BOOLEAN bApEnable=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + + if(bApEnable) + { + if(byte1&BIT4 && !(byte1&BIT5)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], FW for 1Ant AP mode\n")); + realByte1 &= ~BIT4; + realByte1 |= BIT5; + + realByte5 |= BIT5; + realByte5 &= ~BIT6; + } + } + + H2C_Parameter[0] = realByte1; + H2C_Parameter[1] = byte2; + H2C_Parameter[2] = byte3; + H2C_Parameter[3] = byte4; + H2C_Parameter[4] = realByte5; + + + pCoexDm->psTdmaPara[0] = realByte1; + pCoexDm->psTdmaPara[1] = byte2; + pCoexDm->psTdmaPara[2] = byte3; + pCoexDm->psTdmaPara[3] = byte4; + pCoexDm->psTdmaPara[4] = realByte5; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], PS-TDMA H2C cmd =0x%x%08x\n", + H2C_Parameter[0], + H2C_Parameter[1]<<24|H2C_Parameter[2]<<16|H2C_Parameter[3]<<8|H2C_Parameter[4])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x60, 5, H2C_Parameter); +} + +VOID +halbtc8812a2ant_SetLpsRpwm( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + u1Byte lps=lpsVal; + u1Byte rpwm=rpwmVal; + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_LPS_VAL, &lps); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RPWM_VAL, &rpwm); +} + +VOID +halbtc8812a2ant_LpsRpwm( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + BOOLEAN bForceExecPwrCmd=FALSE; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s set lps/rpwm=0x%x/0x%x \n", + (bForceExec? "force to":""), lpsVal, rpwmVal)); + pCoexDm->curLps = lpsVal; + pCoexDm->curRpwm = rpwmVal; + + if(!bForceExec) + { + if( (pCoexDm->preLps == pCoexDm->curLps) && + (pCoexDm->preRpwm == pCoexDm->curRpwm) ) + { + return; + } + } + halbtc8812a2ant_SetLpsRpwm(pBtCoexist, lpsVal, rpwmVal); + + pCoexDm->preLps = pCoexDm->curLps; + pCoexDm->preRpwm = pCoexDm->curRpwm; +} + +VOID +halbtc8812a2ant_SwMechanism1( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bShrinkRxLPF, + IN BOOLEAN bLowPenaltyRA, + IN BOOLEAN bLimitedDIG, + IN BOOLEAN bBTLNAConstrain + ) +{ + /* + u4Byte wifiBw; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if(BTC_WIFI_BW_HT40 != wifiBw) //only shrink RF Rx LPF for HT40 + { + if (bShrinkRxLPF) + bShrinkRxLPF = FALSE; + } + */ + + halbtc8812a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, bShrinkRxLPF); + //halbtc8812a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, bLowPenaltyRA); +} + +VOID +halbtc8812a2ant_SwMechanism2( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bAGCTableShift, + IN BOOLEAN bADCBackOff, + IN BOOLEAN bSWDACSwing, + IN u4Byte dacSwingLvl + ) +{ + //halbtc8812a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, bAGCTableShift); + halbtc8812a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, bADCBackOff); + halbtc8812a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, bSWDACSwing, dacSwingLvl); +} + +VOID +halbtc8812a2ant_SetAntPath( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte antPosType, + IN BOOLEAN bInitHwCfg, + IN BOOLEAN bWifiOff + ) +{ + u1Byte u1Tmp=0; + + if(bInitHwCfg) + { + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x900, 0x00000400); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76d, 0x1); + } + else if(bWifiOff) + { + + } + + // ext switch setting + switch(antPosType) + { + case BTC_ANT_WIFI_AT_CPL_MAIN: + break; + case BTC_ANT_WIFI_AT_CPL_AUX: + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xcb7); + u1Tmp &= ~BIT3; + u1Tmp |= BIT2; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0xcb7, u1Tmp); + break; + default: + break; + } +} + +VOID +halbtc8812a2ant_PsTdma( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bTurnOn, + IN u1Byte type + ) +{ + BOOLEAN bTurnOnByCnt=FALSE; + u1Byte psTdmaTypeByCnt=0; + s1Byte nWiFiDurationAdjust = 0x0; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn %s PS TDMA, type=%d\n", + (bForceExec? "force to":""), (bTurnOn? "ON":"OFF"), type)); + pCoexDm->bCurPsTdmaOn = bTurnOn; + pCoexDm->curPsTdma = type; + + if(!bForceExec) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], bPrePsTdmaOn = %d, bCurPsTdmaOn = %d!!\n", + pCoexDm->bPrePsTdmaOn, pCoexDm->bCurPsTdmaOn)); + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], prePsTdma = %d, curPsTdma = %d!!\n", + pCoexDm->prePsTdma, pCoexDm->curPsTdma)); + + if( (pCoexDm->bPrePsTdmaOn == pCoexDm->bCurPsTdmaOn) && + (pCoexDm->prePsTdma == pCoexDm->curPsTdma) ) + return; + } + + if (pCoexSta->nScanAPNum >= 40) + nWiFiDurationAdjust = -15; + else if (pCoexSta->nScanAPNum >= 20) + nWiFiDurationAdjust = -10; + +/* + if (!pCoexSta->bForceLpsOn) //only for A2DP-only case 1/2/9/11 while wifi noisy threshold > 30 + { + psTdmaByte0Val = 0x61; //no null-pkt + psTdmaByte3Val = 0x11; // no tx-pause at BT-slot + psTdmaByte4Val = 0x10; // 0x778 = d/1 toggle + } + + + if ( (type == 3) || (type == 13) || (type == 14) ) + { + psTdmaByte4Val = psTdmaByte4Val & 0xbf; //no dynamic slot for multi-profile + + if (!bWifiBusy) + psTdmaByte4Val = psTdmaByte4Val | 0x1; //0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) + } + + if (pBtLinkInfo->bSlaveRole == TRUE) + psTdmaByte4Val = psTdmaByte4Val | 0x1; //0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) + +*/ + if(bTurnOn) + { + switch(type) + { + case 1: + default: //d1,wb + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x3c, 0x03, 0x11, 0x10); + break; + case 2: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x32, 0x03, 0x11, 0x10); + break; + case 3: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x28, 0x03, 0x11, 0x10); + break; + case 4: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1e, 0x03, 0x11, 0x10); + break; + case 5: //d1,pb,TXpause + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0x63, 0x3c, 0x03, 0x90, 0x10); + break; + case 6: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0x63, 0x32, 0x03, 0x90, 0x10); + break; + case 7: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0x63, 0x28, 0x03, 0x90, 0x10); + break; + case 8: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0x63, 0x1e, 0x03, 0x90, 0x10); + break; + case 9: //d1,bb + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x3c, 0x03, 0x31, 0x10); + break; + case 10: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x32, 0x03, 0x31, 0x10); + break; + case 11: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x28, 0x03, 0x31, 0x10); + break; + case 12: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1e, 0x03, 0x31, 0x10); + break; + case 13: //d1,bb,TXpause + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x3c, 0x03, 0x30, 0x10); + break; + case 14: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x32, 0x03, 0x30, 0x10); + break; + case 15: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x28, 0x03, 0x30, 0x10); + break; + case 16: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1e, 0x03, 0x30, 0x10); + break; + case 17: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0x61, 0x35, 0x3, 0x11, 0x11); + break; + case 18: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0xe1, 0x90); + break; + case 19: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x25, 0xe1, 0x90); + break; + case 20: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x25, 0x60, 0x90); + break; + case 21: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x15, 0x3, 0x70, 0x90); + break; + case 22: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0x61, 0x1a, 0x1a, 0x21, 0x10); + break; + case 23: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1c, 0x03, 0x31, 0x10); + break; + + case 71: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); + break; + + // following cases is for wifi rssi low, started from 81 + case 80: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0x53, 0x3c, 0x3, 0x90, 0x50); + break; + case 81: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0x53, 0x3a+nWiFiDurationAdjust, 0x3, 0x90, 0x50); + break; + case 82: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0x53, 0x30+nWiFiDurationAdjust, 0x03, 0x90, 0x50); + break; + case 83: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0x53, 0x21, 0x03, 0x90, 0x50); + break; + case 84: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0x53, 0x15, 0x3, 0x90, 0x50); + break; + case 85: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0x53, 0x1d, 0x1d, 0x80, 0x50); + break; + case 86: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0x53, 0x15, 0x15, 0x80, 0x50); + break; + } + } + else + { + // disable PS tdma + switch(type) + { + case 0: //ANT2PTA, 0x778=0x1 + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0x8, 0x0, 0x0, 0x0, 0x0); + break; + case 1: //ANT2BT, 0x778=3 + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x8, 0x0); + delay_ms(5); + halbtc8812a2ant_SetAntPath(pBtCoexist, BTC_ANT_WIFI_AT_CPL_AUX, FALSE, FALSE); + break; + default: + halbtc8812a2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x0, 0x0); + break; + } + } + + // update pre state + pCoexDm->bPrePsTdmaOn = pCoexDm->bCurPsTdmaOn; + pCoexDm->prePsTdma = pCoexDm->curPsTdma; +} + +VOID +halbtc8812a2ant_CoexAllOff( + IN PBTC_COEXIST pBtCoexist + ) +{ + // fw all off + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + halbtc8812a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + // sw all off + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + // hw all off + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); +} + +VOID +halbtc8812a2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + // force to reset coex mechanism + + halbtc8812a2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); + halbtc8812a2ant_FwDacSwingLvl(pBtCoexist, FORCE_EXEC, 6); + halbtc8812a2ant_DecBtPwr(pBtCoexist, FORCE_EXEC, 0); + + halbtc8812a2ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 0); + + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); +} + +VOID +halbtc8812a2ant_PsTdmaCheckForPowerSaveState( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bNewPsState + ) +{ + u1Byte lpsMode=0x0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_LPS_MODE, &lpsMode); + + if(lpsMode) // already under LPS state + { + if(bNewPsState) + { + // keep state under LPS, do nothing. + } + else + { + // will leave LPS state, turn off psTdma first + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + } + } + else // NO PS state + { + if(bNewPsState) + { + // will enter LPS state, turn off psTdma first + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + } + else + { + // keep state under NO PS state, do nothing. + } + } +} + +VOID +halbtc8812a2ant_PowerSaveState( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte psType, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + BOOLEAN bLowPwrDisable=FALSE; + + switch(psType) + { + case BTC_PS_WIFI_NATIVE: + // recover to original 32k low power setting + bLowPwrDisable = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_NORMAL_LPS, NULL); + pCoexSta->bForceLpsOn = FALSE; + break; + case BTC_PS_LPS_ON: + halbtc8812a2ant_PsTdmaCheckForPowerSaveState(pBtCoexist, TRUE); + halbtc8812a2ant_LpsRpwm(pBtCoexist, NORMAL_EXEC, lpsVal, rpwmVal); + // when coex force to enter LPS, do not enter 32k low power. + bLowPwrDisable = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + // power save must executed before psTdma. + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_ENTER_LPS, NULL); + pCoexSta->bForceLpsOn = TRUE; + break; + case BTC_PS_LPS_OFF: + halbtc8812a2ant_PsTdmaCheckForPowerSaveState(pBtCoexist, FALSE); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_LEAVE_LPS, NULL); + pCoexSta->bForceLpsOn = FALSE; + break; + default: + break; + } +} + +VOID +halbtc8812a2ant_ActionBtInquiry( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + halbtc8812a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); +} + +BOOLEAN +halbtc8812a2ant_IsCommonAction( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH; + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bCommon=FALSE, bWifiConnected=FALSE, bWifiBusy=FALSE; + BOOLEAN bBtHsOn=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + + + if(pCoexSta->bC2hBtInquiryPage) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is under inquiry/page scan !!\n")); + halbtc8812a2ant_ActionBtInquiry(pBtCoexist); + return TRUE; + } + + if(pBtLinkInfo->bScoExist || pBtLinkInfo->bHidExist) + { + halbtc8812a2ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 1, 0, 0, 0); + } + else + { + halbtc8812a2ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + } + + if(!bWifiConnected) + { + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non-connected idle!!\n")); + + if( (BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus) || + (BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) ) + { + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 1); + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + } + else + { + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + } + + halbtc8812a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + bCommon = TRUE; + } + else + { + if(BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi connected + BT non connected-idle!!\n")); + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + halbtc8812a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + bCommon = TRUE; + } + else if(BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) + { + if(bBtHsOn) + return FALSE; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi connected + BT connected-idle!!\n")); + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + halbtc8812a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8812a2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + bCommon = TRUE; + } + else + { + if(bWifiBusy) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi Connected-Busy + BT Busy!!\n")); + bCommon = FALSE; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi Connected-Idle + BT Busy!!\n")); + + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + halbtc8812a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 17); + + halbtc8812a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + bCommon = TRUE; + } + } + } + + return bCommon; +} + +VOID +halbtc8812a2ant_TdmaDurationAdjust( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bScoHid, + IN BOOLEAN bTxPause, + IN u1Byte maxInterval + ) +{ + static s4Byte up,dn,m,n,WaitCount; + s4Byte result; //0: no change, +1: increase WiFi duration, -1: decrease WiFi duration + u1Byte retryCount=0; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TdmaDurationAdjust()\n")); + + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + + if(!pCoexDm->bAutoTdmaAdjust) + { + pCoexDm->bAutoTdmaAdjust = TRUE; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], first run TdmaDurationAdjust()!!\n")); + { + if(bScoHid) + { + if(bTxPause) + { + if(maxInterval == 1) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + pCoexDm->psTdmaDuAdjType = 13; + } + else if(maxInterval == 2) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(maxInterval == 3) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + } + else + { + if(maxInterval == 1) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(maxInterval == 2) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(maxInterval == 3) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + } + } + else + { + if(bTxPause) + { + if(maxInterval == 1) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + pCoexDm->psTdmaDuAdjType = 5; + } + else if(maxInterval == 2) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(maxInterval == 3) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + } + else + { + if(maxInterval == 1) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + else if(maxInterval == 2) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(maxInterval == 3) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + } + } + } + //============ + up = 0; + dn = 0; + m = 1; + n= 3; + result = 0; + WaitCount = 0; + } + else + { + //accquire the BT TRx retry count from BT_Info byte2 + retryCount = pCoexSta->btRetryCnt; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], retryCount = %d\n", retryCount)); + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], up=%d, dn=%d, m=%d, n=%d, WaitCount=%d\n", + up, dn, m, n, WaitCount)); + result = 0; + WaitCount++; + + if(retryCount == 0) // no retry in the last 2-second duration + { + up++; + dn--; + + if (dn <= 0) + dn = 0; + + if(up >= n) // if s n 2 retry count0, hռeWiFi duration + { + WaitCount = 0; + n = 3; + up = 0; + dn = 0; + result = 1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Increase wifi duration!!\n")); + } + } + else if (retryCount <= 3) // <=3 retry in the last 2-second duration + { + up--; + dn++; + + if (up <= 0) + up = 0; + + if (dn == 2) // if s 2 2 retry count< 3, hկWiFi duration + { + if (WaitCount <= 2) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter<3!!\n")); + } + } + else //retry count > 3, un1 retry count > 3, hկWiFi duration + { + if (WaitCount == 1) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter>3!!\n")); + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], max Interval = %d\n", maxInterval)); + if(maxInterval == 1) + { + if(bTxPause) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 1\n")); + + if(pCoexDm->curPsTdma == 1) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + pCoexDm->psTdmaDuAdjType = 5; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 4) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + if(pCoexDm->curPsTdma == 9) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + pCoexDm->psTdmaDuAdjType = 13; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + + if(result == -1) + { + if(pCoexDm->curPsTdma == 5) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + else if(pCoexDm->curPsTdma == 13) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 8) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + pCoexDm->psTdmaDuAdjType = 5; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + pCoexDm->psTdmaDuAdjType = 13; + } + } + } + else + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 0\n")); + if(pCoexDm->curPsTdma == 5) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 8) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + if(pCoexDm->curPsTdma == 13) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + + if(result == -1) + { + if(pCoexDm->curPsTdma == 1) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 4) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + } + } + } + else if(maxInterval == 2) + { + if(bTxPause) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 1\n")); + if(pCoexDm->curPsTdma == 1) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 4) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + if(pCoexDm->curPsTdma == 9) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 5) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + else if(pCoexDm->curPsTdma == 13) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 8) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + } + } + else + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 0\n")); + if(pCoexDm->curPsTdma == 5) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 8) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + if(pCoexDm->curPsTdma == 13) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 1) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 4) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + } + } + } + else if(maxInterval == 3) + { + if(bTxPause) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 1\n")); + if(pCoexDm->curPsTdma == 1) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 4) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + if(pCoexDm->curPsTdma == 9) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 5) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + else if(pCoexDm->curPsTdma == 13) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 8) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + } + } + else + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 0\n")); + if(pCoexDm->curPsTdma == 5) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 8) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + if(pCoexDm->curPsTdma == 13) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 1) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 4) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + } + } + } + } + + // if current PsTdma not match with the recorded one (when scan, dhcp...), + // then we have to adjust it back to the previous record one. + if(pCoexDm->curPsTdma != pCoexDm->psTdmaDuAdjType) + { + BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PsTdma type dismatch!!!, curPsTdma=%d, recordPsTdma=%d\n", + pCoexDm->curPsTdma, pCoexDm->psTdmaDuAdjType)); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + + if( !bScan && !bLink && !bRoam) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, pCoexDm->psTdmaDuAdjType); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n")); + } + } +} + +//================== +// pstdma for wifi rssi low +//================== +VOID +halbtc8812a2ant_TdmaDurationAdjustForWifiRssiLow( + IN PBTC_COEXIST pBtCoexist//, + //IN u1Byte wifiStatus + ) +{ + static s4Byte up,dn,m,n,WaitCount; + s4Byte result; //0: no change, +1: increase WiFi duration, -1: decrease WiFi duration + u1Byte retryCount=0, btInfoExt; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], halbtc8812a2ant_TdmaDurationAdjustForWifiRssiLow()\n")); +#if 0 + if( (BT_8812A_2ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN == wifiStatus) || + (BT_8812A_2ANT_WIFI_STATUS_CONNECTED_SCAN == wifiStatus) || + (BT_8812A_2ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT == wifiStatus) ) + { + if( pCoexDm->curPsTdma != 81 && + pCoexDm->curPsTdma != 82 && + pCoexDm->curPsTdma != 83 && + pCoexDm->curPsTdma != 84 ) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 82); + pCoexDm->psTdmaDuAdjType = 82; + + up = 0; + dn = 0; + m = 1; + n= 3; + result = 0; + WaitCount = 0; + } + return; + } +#endif + pCoexDm->bAutoTdmaAdjust = FALSE; + + retryCount = pCoexSta->btRetryCnt; + btInfoExt = pCoexSta->btInfoExt; + + if(!pCoexDm->bAutoTdmaAdjustLowRssi) + { + pCoexDm->bAutoTdmaAdjustLowRssi = TRUE; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], first run TdmaDurationAdjustForWifiRssiLow()!!\n")); + + if(BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(btInfoExt)) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 83); + pCoexDm->psTdmaDuAdjType = 83; + } + else + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 82); + pCoexDm->psTdmaDuAdjType = 82; + } + //============ + up = 0; + dn = 0; + m = 1; + n= 3; + result = 0; + WaitCount = 0; + } + else + { + //accquire the BT TRx retry count from BT_Info byte2 +// retryCount = pCoexSta->btRetryCnt; +// btInfoExt = pCoexSta->btInfoExt; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], retryCount = %d\n", retryCount)); + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], up=%d, dn=%d, m=%d, n=%d, WaitCount=%d\n", + up, dn, m, n, WaitCount)); + result = 0; + WaitCount++; + + if ( (pCoexSta->lowPriorityTx) > 1050 || (pCoexSta->lowPriorityRx) > 1250 ) + retryCount++; + + if(retryCount == 0) // no retry in the last 2-second duration + { + up++; + dn--; + + if (dn <= 0) + dn = 0; + + if(up >= n) // if s n 2 retry count0, hռeWiFi duration + { + WaitCount = 0; + n = 3; + up = 0; + dn = 0; + result = 1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Increase wifi duration!!\n")); + } + } + else if (retryCount <= 3) // <=3 retry in the last 2-second duration + { + up--; + dn++; + + if (up <= 0) + up = 0; + + if (dn == 2) // if s 2 2 retry count< 3, hկWiFi duration + { + if (WaitCount <= 2) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter<3!!\n")); + } + } + else //retry count > 3, un1 retry count > 3, hկWiFi duration + { + if (WaitCount == 1) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter>3!!\n")); + } + + if(result == -1) + { +/* + if( (BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(btInfoExt)) && + ((pCoexDm->curPsTdma == 81) ||(pCoexDm->curPsTdma == 82)) ) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 84); + pCoexDm->psTdmaDuAdjType = 84; + } +*/ + if(pCoexDm->curPsTdma == 80) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 82); + pCoexDm->psTdmaDuAdjType = 82; + } + else if(pCoexDm->curPsTdma == 81) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 82); + pCoexDm->psTdmaDuAdjType = 82; + } + else if(pCoexDm->curPsTdma == 82) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 83); + pCoexDm->psTdmaDuAdjType = 83; + } + else if(pCoexDm->curPsTdma == 83) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 84); + pCoexDm->psTdmaDuAdjType = 84; + } + } + else if(result == 1) + { +/* + if( (BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(btInfoExt)) && + ((pCoexDm->curPsTdma == 81) ||(pCoexDm->curPsTdma == 82)) ) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 83); + pCoexDm->psTdmaDuAdjType = 83; + } +*/ + if(pCoexDm->curPsTdma == 84) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 83); + pCoexDm->psTdmaDuAdjType = 83; + } + else if(pCoexDm->curPsTdma == 83) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 82); + pCoexDm->psTdmaDuAdjType = 82; + } + else if(pCoexDm->curPsTdma == 82) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 81); + pCoexDm->psTdmaDuAdjType = 81; + } + else if((pCoexDm->curPsTdma == 81)&&((pCoexSta->nScanAPNum <= 5))) + { + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 81); + pCoexDm->psTdmaDuAdjType = 81; + } + } + + if( pCoexDm->curPsTdma != 80 && + pCoexDm->curPsTdma != 81 && + pCoexDm->curPsTdma != 82 && + pCoexDm->curPsTdma != 83 && + pCoexDm->curPsTdma != 84 ) + { + // recover to previous adjust type + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, pCoexDm->psTdmaDuAdjType); + } + } +} + +VOID +halbtc8812a2ant_GetBtRssiThreshold( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte pThres0, + IN pu1Byte pThres1 + ) +{ + u1Byte antType, btThreshold=0; + +// pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_ANT_TYPE, &antType); + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + antType = pBoardInfo->antType; + + + switch(antType) + { + case BTC_ANT_TYPE_0: + *pThres0 = 100; + *pThres1 = 100; + break; + case BTC_ANT_TYPE_1: + *pThres0 = 34; + *pThres1 = 42; + break; + case BTC_ANT_TYPE_2: + *pThres0 = 34; + *pThres1 = 42; + break; + case BTC_ANT_TYPE_3: + *pThres0 = 34; + *pThres1 = 42; + break; + case BTC_ANT_TYPE_4: + *pThres0 = 34; + *pThres1 = 42; + break; + default: + break; + } +} + + + +VOID +halbtc8812a2ant_ActionSco( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH, btRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiBw; + u1Byte btThresh0=0, btThresh1=0; + + +// halbtc8812a2ant_GetBtRssiThreshold(pBtCoexist, &btThresh0, &btThresh1); + btRssiState = halbtc8812a2ant_BtRssiState(3, btThresh0, btThresh1); + + wifiRssiState = halbtc8812a2ant_WifiRssiState(pBtCoexist, 0, 2, 34, 0); + btRssiState = halbtc8812a2ant_BtRssiState(3, 34, 42); + + // power save state + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // coex table + if(BTC_RSSI_LOW(btRssiState)) + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 5); + else + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + + // pstdma + if(BTC_RSSI_LOW(btRssiState)) + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + else + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + + // decrease BT power + if(BTC_RSSI_LOW(btRssiState)) + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + else if(BTC_RSSI_MEDIUM(btRssiState)) + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 4); + + // limited Rx + halbtc8812a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + // fw dac swing level + halbtc8812a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if(BTC_RSSI_HIGH(wifiRssiState)) + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,TRUE,0x6); + } + else + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,TRUE,0x6); + } + } + else + { + if(BTC_RSSI_HIGH(wifiRssiState)) + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,TRUE,0x6); + } + else + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,TRUE,0x6); + } + } +} + +VOID +halbtc8812a2ant_ActionScoHid( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH, btRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiBw; + u1Byte btThresh0=0, btThresh1=0; + +// halbtc8812a2ant_GetBtRssiThreshold(pBtCoexist, &btThresh0, &btThresh1); + btRssiState = halbtc8812a2ant_BtRssiState(3, btThresh0, btThresh1); + + wifiRssiState = halbtc8812a2ant_WifiRssiState(pBtCoexist, 0, 2, 34, 0); + btRssiState = halbtc8812a2ant_BtRssiState(3, 34, 42); + + // power save state + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // coex table + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + + // pstdma + if(BTC_RSSI_LOW(btRssiState)) + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + else + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + + // decrease BT power + if(BTC_RSSI_LOW(btRssiState)) + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + else if(BTC_RSSI_MEDIUM(btRssiState)) + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 4); + + // limited Rx + halbtc8812a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, TRUE, 0x8); + + // fw dac swing level + halbtc8812a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if(BTC_RSSI_HIGH(wifiRssiState)) + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x6); + } + else + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x6); + } + } + else + { + if(BTC_RSSI_HIGH(wifiRssiState)) + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x6); + } + else + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x6); + } + } +} + +VOID +halbtc8812a2ant_ActionHid( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH, btRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiBw; + u1Byte anttype=0; + BOOLEAN bApEnable=FALSE; + + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + + anttype = pBoardInfo->antType; + + +// halbtc8812a2ant_GetBtRssiThreshold(pBtCoexist, &btThresh0, &btThresh1); +// btRssiState = halbtc8812a2ant_BtRssiState(3, btThresh0, btThresh1); + + wifiRssiState = halbtc8812a2ant_WifiRssiState(pBtCoexist, 0, 2, 34, 0); + btRssiState = halbtc8812a2ant_BtRssiState(3, 34, 42); + + + if(anttype == 0)//ANTTYPE = 0 92E 2ant with SPDT + { + // power save state & pstdma & coex table + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + else if(anttype == 1) //92E 2ant with coupler and bad ant. isolation, 92E 3ant with bad ant. isolation + { + // power save state & pstdma & coex table + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + else if(anttype == 2)//ANTTYPE = 2, 92E 2ant with coupler and normal/good ant. isolation, 92E 3ant with normal ant. isolation + { + // power save state & pstdma & coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH_8812A)) + { //WIFI RSSI = high & BT RSSI = high & shielding room + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_PsTdma(pBtCoexist, FORCE_EXEC, TRUE, 9); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 3); + } + else if (BTC_RSSI_HIGH(wifiRssiState)&&(!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH_8812A)) + { //WIFI RSSI = high & BT RSSI = high & noisy enviroment + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_PsTdma(pBtCoexist, FORCE_EXEC, TRUE, 9); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 3); + } + else //WIFI RSSI || BT RSSI == low + { + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_PsTdma(pBtCoexist, FORCE_EXEC, TRUE, 9); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 3); + } + } + else if(anttype == 3) //ANTTYPE = 3, 92E 3ant with good ant. isolation + { + // power save state & pstdma & coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH_8812A)) + { //WIFI RSSI = high & BT RSSI = high & shielding room + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + } + else if (BTC_RSSI_HIGH(wifiRssiState)&&(!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH_8812A)) + { //WIFI RSSI = high & BT RSSI = high & noisy enviroment + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + } + else //WIFI RSSI || BT RSSI == low + { + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + } + else //ANTTYPE = 4 for test + { + // power save state & pstdma & coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH_8812A)) + { //WIFI RSSI = high & BT RSSI = high & shielding room + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + else if (BTC_RSSI_HIGH(wifiRssiState)&&(!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH_8812A)) + { //WIFI RSSI = high & BT RSSI = high & noisy enviroment + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + else //WIFI RSSI || BT RSSI == low + { + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + } + + + // power save state + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // coex table + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + // pstdma + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + + // decrease BT power + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + // limited Rx + halbtc8812a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + // fw dac swing level + halbtc8812a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if(BTC_RSSI_HIGH(wifiRssiState)) + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if(BTC_RSSI_HIGH(wifiRssiState)) + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +//A2DP only / PAN(EDR) only/ A2DP+PAN(HS) +VOID +halbtc8812a2ant_ActionA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH, btRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiBw; + u1Byte anttype=0; + BOOLEAN bApEnable=FALSE; + + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + + anttype = pBoardInfo->antType; + +// halbtc8812a2ant_GetBtRssiThreshold(pBtCoexist, &btThresh0, &btThresh1); +// btRssiState = halbtc8812a2ant_BtRssiState(3, btThresh0, btThresh1); + + wifiRssiState = halbtc8812a2ant_WifiRssiState(pBtCoexist, 0, 2, 34, 0); + btRssiState = halbtc8812a2ant_BtRssiState(3, 34, 42); + +// anttype = 4; + + if(anttype == 0)//ANTTYPE = 0 92E 2ant with SPDT + { + + if((pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH_8812A)) + { + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + else + { + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + { //WIFI RSSI = high & BT RSSI = high & shielding room + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + else //WIFI RSSI || BT RSSI == low + { + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + } + + // power save state & pstdma & coex table +/* + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH_8812A)) + { //WIFI RSSI = high & BT RSSI = high & shielding room + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + else if (BTC_RSSI_HIGH(wifiRssiState)&&(!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH_8812A)) + { //WIFI RSSI = high & BT RSSI = high & noisy enviroment + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + else //WIFI RSSI || BT RSSI == low + { + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } +*/ + } + else if(anttype == 1) //92E 2ant with coupler and bad ant. isolation, 92E 3ant with bad ant. isolation + { + // power save state & pstdma & coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH_8812A)) + { //WIFI RSSI = high & BT RSSI = high & shielding room + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 1); //shielding room + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + else if (BTC_RSSI_HIGH(wifiRssiState)&&(!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH_8812A)) + { //WIFI RSSI = high & BT RSSI = high & noisy enviroment + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + else //WIFI RSSI || BT RSSI == low + { + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + + } + else if(anttype == 2)//ANTTYPE = 2, 92E 2ant with coupler and normal/good ant. isolation, 92E 3ant with normal ant. isolation + { + // power save state & pstdma & coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH_8812A)) + { //WIFI RSSI = high & BT RSSI = high & shielding room + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 1); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 5); + } + else if (BTC_RSSI_HIGH(wifiRssiState)&&(!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH_8812A)) + { //WIFI RSSI = high & BT RSSI = high & noisy enviroment + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + else //WIFI RSSI || BT RSSI == low + { + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + } + else if(anttype == 3) //ANTTYPE = 3, 92E 3ant with good ant. isolation + { + // power save state & pstdma & coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH_8812A)) + { //WIFI RSSI = high & BT RSSI = high & shielding room + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + } + else if (BTC_RSSI_HIGH(wifiRssiState)&&(!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH_8812A)) + { //WIFI RSSI = high & BT RSSI = high & noisy enviroment + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + } + else //WIFI RSSI || BT RSSI == low + { + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + } + else //ANTTYPE = 4 for test + { + // power save state & pstdma & coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH_8812A)) + { //WIFI RSSI = high & BT RSSI = high & shielding room + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + else if (BTC_RSSI_HIGH(wifiRssiState)&&(!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH_8812A)) + { //WIFI RSSI = high & BT RSSI = high & noisy enviroment + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + else //WIFI RSSI || BT RSSI == low + { + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + } + + // decrease BT power + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + // decrease BT power +/* + if(BTC_RSSI_LOW(btRssiState)) + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + else if(BTC_RSSI_MEDIUM(btRssiState)) + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else if (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH_8812A) // BT HIGH RSSI & shielding room + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 4); +*/ + // limited Rx + halbtc8812a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + // fw dac swing level + halbtc8812a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + + // sw mechanism + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if(BTC_RSSI_HIGH(wifiRssiState)) + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if(BTC_RSSI_HIGH(wifiRssiState)) + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +VOID +halbtc8812a2ant_ActionA2dpPanHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH, btRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiBw; + u1Byte btThresh0=0, btThresh1=0; + +// halbtc8812a2ant_GetBtRssiThreshold(pBtCoexist, &btThresh0, &btThresh1); + btRssiState = halbtc8812a2ant_BtRssiState(3, btThresh0, btThresh1); + + wifiRssiState = halbtc8812a2ant_WifiRssiState(pBtCoexist, 0, 2, 34, 0); + btRssiState = halbtc8812a2ant_BtRssiState(3, 34, 42); + + // power save state + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 5); + + // pstdma + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 2); + else + halbtc8812a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 2); + + // decrease BT power + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); +/* + // decrease BT power + if(BTC_RSSI_LOW(btRssiState)) + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + else if(BTC_RSSI_MEDIUM(btRssiState)) + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 4); +*/ + // limited Rx + halbtc8812a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + // fw dac swing level + halbtc8812a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + + // sw mechanism + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if(BTC_RSSI_HIGH(wifiRssiState)) + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,TRUE,0x6); + } + else + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,TRUE,0x6); + } + } + else + { + if(BTC_RSSI_HIGH(wifiRssiState)) + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,TRUE,0x6); + } + else + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,TRUE,0x6); + } + } +} + +VOID +halbtc8812a2ant_ActionPanEdr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH, btRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiBw; + u1Byte btThresh0=0, btThresh1=0; + BOOLEAN bApEnable=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + + +// halbtc8812a2ant_GetBtRssiThreshold(pBtCoexist, &btThresh0, &btThresh1); + btRssiState = halbtc8812a2ant_BtRssiState(3, btThresh0, btThresh1); + + wifiRssiState = halbtc8812a2ant_WifiRssiState(pBtCoexist, 0, 2, 34, 0); + btRssiState = halbtc8812a2ant_BtRssiState(3, 34, 42); + + // power save state + if((bApEnable == TRUE) || (BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)))) + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + + // coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + // pstdma + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + else + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 85); + + // decrease BT power + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); +/* + // decrease BT power + if(BTC_RSSI_LOW(btRssiState)) + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + else if(BTC_RSSI_MEDIUM(btRssiState)) + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 4); +*/ + // limited Rx + halbtc8812a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + // fw dac swing level + halbtc8812a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + + // sw mechanism + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if(BTC_RSSI_HIGH(wifiRssiState)) + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if(BTC_RSSI_HIGH(wifiRssiState)) + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +//PAN(HS) only +VOID +halbtc8812a2ant_ActionPanHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH, btRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiBw; + + wifiRssiState = halbtc8812a2ant_WifiRssiState(pBtCoexist, 0, 2, 34, 0); + btRssiState = halbtc8812a2ant_BtRssiState(3, 34, 42); + + // power save state + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // coex table + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + + // pstdma + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + + // decrease BT power + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + +/* + // decrease BT power + if(BTC_RSSI_LOW(btRssiState)) + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + else if(BTC_RSSI_MEDIUM(btRssiState)) + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 4); +*/ + // limited Rx + halbtc8812a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + // fw dac swing level + halbtc8812a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if(BTC_RSSI_HIGH(wifiRssiState)) + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if(BTC_RSSI_HIGH(wifiRssiState)) + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +//PAN(EDR)+A2DP +VOID +halbtc8812a2ant_ActionPanEdrA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH, btRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiBw; + u1Byte btThresh0=0, btThresh1=0; + BOOLEAN bApEnable=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + +// halbtc8812a2ant_GetBtRssiThreshold(pBtCoexist, &btThresh0, &btThresh1); + btRssiState = halbtc8812a2ant_BtRssiState(3, btThresh0, btThresh1); + + + wifiRssiState = halbtc8812a2ant_WifiRssiState(pBtCoexist, 0, 2, 34, 0); + btRssiState = halbtc8812a2ant_BtRssiState(3, 34, 42); + + // power save state + if((bApEnable == TRUE) || (BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)))) + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else if(BTC_RSSI_LOW(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + + // coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + else if(BTC_RSSI_LOW(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 5); + else + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + // pstdma + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 3); + else if(BTC_RSSI_LOW(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 3); + else + { + pCoexDm->bAutoTdmaAdjust = FALSE; + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 86); + } + + // decrease BT power + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + +/* + // decrease BT power + if(BTC_RSSI_LOW(btRssiState)) + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + else if(BTC_RSSI_MEDIUM(btRssiState)) + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 4); +*/ + // limited Rx + halbtc8812a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + // fw dac swing level + halbtc8812a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if(BTC_RSSI_HIGH(wifiRssiState)) + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if(BTC_RSSI_HIGH(wifiRssiState)) + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +VOID +halbtc8812a2ant_ActionPanEdrHid( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH, btRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiBw; + u1Byte btThresh0=0, btThresh1=0; + BOOLEAN bApEnable=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + + halbtc8812a2ant_GetBtRssiThreshold(pBtCoexist, &btThresh0, &btThresh1); + btRssiState = halbtc8812a2ant_BtRssiState(3, btThresh0, btThresh1); + + wifiRssiState = halbtc8812a2ant_WifiRssiState(pBtCoexist, 0, 2, 34, 0); +// btRssiState = halbtc8812a2ant_BtRssiState(3, 34, 42); + + // power save state + if((bApEnable == TRUE) || (BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)))) + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else if(BTC_RSSI_LOW(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + + // coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 3); + else if(BTC_RSSI_LOW(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 5); + else + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + // pstdma + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + else if(BTC_RSSI_LOW(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + else + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 85); + + // decrease BT power + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + +/* + // decrease BT power + if(BTC_RSSI_LOW(btRssiState)) + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + else if(BTC_RSSI_MEDIUM(btRssiState)) + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 4); +*/ + // limited Rx + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + else if(BTC_RSSI_LOW(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + else + halbtc8812a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, TRUE, 0x8); + + // fw dac swing level + halbtc8812a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if(BTC_RSSI_HIGH(wifiRssiState)) + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if(BTC_RSSI_HIGH(wifiRssiState)) + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +// HID+A2DP+PAN(EDR) +VOID +halbtc8812a2ant_ActionHidA2dpPanEdr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH, btRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiBw; + u1Byte btThresh0=0, btThresh1=0; + BOOLEAN bApEnable=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + + halbtc8812a2ant_GetBtRssiThreshold(pBtCoexist, &btThresh0, &btThresh1); + btRssiState = halbtc8812a2ant_BtRssiState(3, btThresh0, btThresh1); + + wifiRssiState = halbtc8812a2ant_WifiRssiState(pBtCoexist, 0, 2, 34, 0); +// btRssiState = halbtc8812a2ant_BtRssiState(3, 34, 42); + + // power save state + if((bApEnable == TRUE) || (BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)))) + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else if(BTC_RSSI_LOW(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + + // coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 3); + else if(BTC_RSSI_LOW(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 5); + else + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + // pstdma + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 3); + else if(BTC_RSSI_LOW(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 3); + else + { + pCoexDm->bAutoTdmaAdjust = FALSE; + halbtc8812a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 86); + } + + // decrease BT power + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); +/* + // decrease BT power + if(BTC_RSSI_LOW(btRssiState)) + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + else if(BTC_RSSI_MEDIUM(btRssiState)) + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 4); +*/ + // limited Rx + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + else if(BTC_RSSI_LOW(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + else + halbtc8812a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, TRUE, 0x8); + + + // fw dac swing level + halbtc8812a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if(BTC_RSSI_HIGH(wifiRssiState)) + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if(BTC_RSSI_HIGH(wifiRssiState)) + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +VOID +halbtc8812a2ant_ActionHidA2dpPanHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH, btRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiBw; + u1Byte btThresh0=0, btThresh1=0; + + halbtc8812a2ant_GetBtRssiThreshold(pBtCoexist, &btThresh0, &btThresh1); + btRssiState = halbtc8812a2ant_BtRssiState(3, btThresh0, btThresh1); + + + wifiRssiState = halbtc8812a2ant_WifiRssiState(pBtCoexist, 0, 2, 34, 0); +// btRssiState = halbtc8812a2ant_BtRssiState(3, 34, 42); + + // power save state + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 3); + else if(BTC_RSSI_LOW(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 5); + else + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + // pstdma + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 2); + else if(BTC_RSSI_LOW(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 2); + else + halbtc8812a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 2); + + // decrease BT power + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + +/* + // decrease BT power + if(BTC_RSSI_LOW(btRssiState)) + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + else if(BTC_RSSI_MEDIUM(btRssiState)) + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 4); +*/ + // limited Rx + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + else if(BTC_RSSI_LOW(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState))) + halbtc8812a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + else + halbtc8812a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, TRUE, 0x8); + + // fw dac swing level + halbtc8812a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if(BTC_RSSI_HIGH(wifiRssiState)) + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if(BTC_RSSI_HIGH(wifiRssiState)) + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +VOID +halbtc8812a2ant_ActionHidA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH, btRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiBw; + u1Byte btThresh0=0, btThresh1=0, anttype=0; + BOOLEAN bApEnable=FALSE; + + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + + anttype = pBoardInfo->antType; + + +// halbtc8812a2ant_GetBtRssiThreshold(pBtCoexist, &btThresh0, &btThresh1); +// btRssiState = halbtc8812a2ant_BtRssiState(3, btThresh0, btThresh1); + + wifiRssiState = halbtc8812a2ant_WifiRssiState(pBtCoexist, 0, 2, 34, 0); + btRssiState = halbtc8812a2ant_BtRssiState(3, 34, 42); + + if(anttype == 0)//ANTTYPE = 0 92E 2ant with SPDT + { + // power save state & pstdma & coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH_8812A)) + { + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_PsTdma(pBtCoexist, FORCE_EXEC, TRUE, 83); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 8); + + } + else if (BTC_RSSI_HIGH(wifiRssiState)&&(!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH_8812A)) + { + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + else + { + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_PsTdma(pBtCoexist, FORCE_EXEC, TRUE, 83); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 8); + } + } + else if(anttype == 1) //92E 2ant with coupler and bad ant. isolation, 92E 3ant with bad ant. isolation + { + // power save state & pstdma & coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH_8812A)) + { + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 2); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 8); + } + else if (BTC_RSSI_HIGH(wifiRssiState)&&(!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH_8812A)) + { + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + else + { + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_PsTdma(pBtCoexist, FORCE_EXEC, TRUE, 83); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 8); + } + } + else if(anttype == 2)//ANTTYPE = 2, 92E 2ant with coupler and normal/good ant. isolation, 92E 3ant with normal ant. isolation + { + // power save state & pstdma & coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH_8812A)) + { //WIFI RSSI = high & BT RSSI = high & shielding room + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 2); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 8); + } + else if (BTC_RSSI_HIGH(wifiRssiState)&&(!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH_8812A)) + { //WIFI RSSI = high & BT RSSI = high & noisy enviroment + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 8); + } + else //WIFI RSSI || BT RSSI == low + { + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_PsTdma(pBtCoexist, FORCE_EXEC, TRUE, 83); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 8); + } + } + else if(anttype == 3) //ANTTYPE = 3, 92E 3ant with good ant. isolation + { + // power save state & pstdma & coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH_8812A)) + { //WIFI RSSI = high & BT RSSI = high & shielding room + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + } + else if (BTC_RSSI_HIGH(wifiRssiState)&&(!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH_8812A)) + { //WIFI RSSI = high & BT RSSI = high & noisy enviroment + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + } + else //WIFI RSSI || BT RSSI == low + { + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8812a2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + } + else //ANTTYPE = 4 for test + { + // power save state & pstdma & coex table + if(BTC_RSSI_HIGH(wifiRssiState) && (!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH_8812A)) + { //WIFI RSSI = high & BT RSSI = high & shielding room + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + else if (BTC_RSSI_HIGH(wifiRssiState)&&(!BTC_RSSI_LOW(btRssiState)) && (pCoexSta->nScanAPNum > NOISY_AP_NUM_THRESH_8812A)) + { //WIFI RSSI = high & BT RSSI = high & noisy enviroment + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + else //WIFI RSSI || BT RSSI == low + { + halbtc8812a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + halbtc8812a2ant_TdmaDurationAdjustForWifiRssiLow(pBtCoexist); + halbtc8812a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + } + + // decrease BT power + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + +/* + // decrease BT power + if(BTC_RSSI_LOW(btRssiState)) + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + else if(BTC_RSSI_MEDIUM(btRssiState)) + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else if (pCoexSta->nScanAPNum < NOISY_AP_NUM_THRESH_8812A) // BT HIGH RSSI & shielding room + halbtc8812a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 4); +*/ + // limited Rx + halbtc8812a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + // fw dac swing level + halbtc8812a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if(BTC_RSSI_HIGH(wifiRssiState)) + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if(BTC_RSSI_HIGH(wifiRssiState)) + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8812a2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8812a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +VOID +halbtc8812a2ant_CoexUnder5G( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8812a2ant_CoexAllOff(pBtCoexist); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Under 5G, force set BT to ignore Wlan active!!\n")); + halbtc8812a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, TRUE); +} +//==================================================== +VOID +halbtc8812a2ant_RunCoexistMechanism( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bWifiUnder5G=FALSE, bBtHsOn=FALSE; + u1Byte btInfoOriginal=0, btRetryCnt=0; + u1Byte algorithm=0; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism()===>\n")); + + if(pBtCoexist->bManualControl) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n")); + return; + } + + if(pCoexSta->bUnderIps) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi is under IPS !!!\n")); + return; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_5G, &bWifiUnder5G); + if(bWifiUnder5G) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism(), run 5G coex setting!!<===\n")); + halbtc8812a2ant_CoexUnder5G(pBtCoexist); + return; + } + + + algorithm = halbtc8812a2ant_ActionAlgorithm(pBtCoexist); + if(pCoexSta->bC2hBtInquiryPage && (BT_8812A_2ANT_COEX_ALGO_PANHS!=algorithm)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is under inquiry/page scan !!\n")); + halbtc8812a2ant_ActionBtInquiry(pBtCoexist); + return; + } + + pCoexDm->curAlgorithm = algorithm; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Algorithm = %d \n", pCoexDm->curAlgorithm)); + + if(halbtc8812a2ant_IsCommonAction(pBtCoexist)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant common.\n")); + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + } + else + { + if(pCoexDm->curAlgorithm != pCoexDm->preAlgorithm) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], preAlgorithm=%d, curAlgorithm=%d\n", + pCoexDm->preAlgorithm, pCoexDm->curAlgorithm)); + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->bAutoTdmaAdjustLowRssi = FALSE; + } + switch(pCoexDm->curAlgorithm) + { + case BT_8812A_2ANT_COEX_ALGO_SCO: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = SCO.\n")); + halbtc8812a2ant_ActionSco(pBtCoexist); + break; + case BT_8812A_2ANT_COEX_ALGO_SCO_HID: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = SCO+HID.\n")); + halbtc8812a2ant_ActionScoHid(pBtCoexist); + break; + case BT_8812A_2ANT_COEX_ALGO_HID: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID.\n")); + halbtc8812a2ant_ActionHid(pBtCoexist); + break; + case BT_8812A_2ANT_COEX_ALGO_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = A2DP.\n")); + halbtc8812a2ant_ActionA2dp(pBtCoexist); + break; + case BT_8812A_2ANT_COEX_ALGO_A2DP_PANHS: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n")); + halbtc8812a2ant_ActionA2dpPanHs(pBtCoexist); + break; + case BT_8812A_2ANT_COEX_ALGO_PANEDR: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n")); + halbtc8812a2ant_ActionPanEdr(pBtCoexist); + break; + case BT_8812A_2ANT_COEX_ALGO_PANHS: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HS mode.\n")); + halbtc8812a2ant_ActionPanHs(pBtCoexist); + break; + case BT_8812A_2ANT_COEX_ALGO_PANEDR_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n")); + halbtc8812a2ant_ActionPanEdrA2dp(pBtCoexist); + break; + case BT_8812A_2ANT_COEX_ALGO_PANEDR_HID: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n")); + halbtc8812a2ant_ActionPanEdrHid(pBtCoexist); + break; + case BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n")); + halbtc8812a2ant_ActionHidA2dpPanEdr(pBtCoexist); + break; + case BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANHS: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN(HS).\n")); + halbtc8812a2ant_ActionHidA2dpPanHs(pBtCoexist); + break; + case BT_8812A_2ANT_COEX_ALGO_HID_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n")); + halbtc8812a2ant_ActionHidA2dp(pBtCoexist); + break; + default: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n")); + halbtc8812a2ant_CoexAllOff(pBtCoexist); + break; + } + pCoexDm->preAlgorithm = pCoexDm->curAlgorithm; + } + +} + +VOID +halbtc8812a2ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bBackUp + ) +{ + u4Byte u4Tmp=0; + u2Byte u2Tmp=0; + u1Byte u1Tmp=0; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 2Ant Init HW Config!!\n")); + + if(bBackUp) + { + // backup rf 0x1e value + pCoexDm->btRf0x1eBackup = + pBtCoexist->fBtcGetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff); + + pCoexDm->backupArfrCnt1 = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x430); + pCoexDm->backupArfrCnt2 = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x434); + pCoexDm->backupRetryLimit = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0x42a); + pCoexDm->backupAmpduMaxTime = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x456); + } + + //ant sw control to BT + halbtc8812a2ant_SetAntPath(pBtCoexist, BTC_ANT_WIFI_AT_CPL_AUX, TRUE, FALSE); + + // 0x790[5:0]=0x5 + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x790); + u1Tmp &= 0xc0; + u1Tmp |= 0x5; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x790, u1Tmp); + + // PTA parameter + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cc, 0x0); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, 0xffff); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c4, 0x55555555); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c0, 0x55555555); + + // coex parameters + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x778, 0x1); + + // enable counter statistics + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0x4); + + // disable PTA to avoid BT insn't on + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x40, 0x00); + + // bt clock related + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x4); + u1Tmp |= BIT7; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x4, u1Tmp); + + // bt clock related + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x7); + u1Tmp |= BIT1; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x7, u1Tmp); +} + +//============================================================ +// work around function start with wa_halbtc8812a2ant_ +//============================================================ +//============================================================ +// extern function start with EXhalbtc8812a2ant_ +//============================================================ +VOID +EXhalbtc8812a2ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ) +{ +} + +VOID +EXhalbtc8812a2ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ) +{ + halbtc8812a2ant_InitHwConfig(pBtCoexist, TRUE); +} + +VOID +EXhalbtc8812a2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Coex Mechanism Init!!\n")); + + halbtc8812a2ant_InitCoexDm(pBtCoexist); +} + +VOID +EXhalbtc8812a2ant_BTOffOnNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte BTstatus + ) +{ + u1Byte u1Tmp=0; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BToff/on notify\n")); + DBG_871X("%s, BTstatus:%d", __func__, BTstatus); + + if(BTC_BT_OFF == BTstatus) + { + //PTA off + pBtCoexist->btInfo.bBtDisabled = TRUE; + halbtc8812a2ant_EnablePTA(pBtCoexist,FORCE_EXEC, FALSE); + + } + else + { + //PTA on + pBtCoexist->btInfo.bBtDisabled = FALSE; + halbtc8812a2ant_EnablePTA(pBtCoexist,FORCE_EXEC, TRUE); + } + +} + + + +VOID +EXhalbtc8812a2ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + pu1Byte cliBuf=pBtCoexist->cliBuf; + u1Byte u1Tmp[4], i, btInfoExt, psTdmaCase=0; + u2Byte u2Tmp[4]; + u4Byte u4Tmp[4]; + u4Byte fwVer=0, btPatchVer=0; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cliBuf); + + if(pBtCoexist->bManualControl) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[Under Manual Control]============"); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n =========================================="); + CL_PRINTF(cliBuf); + } + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:", \ + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "Antenna type:", \ + pBoardInfo->antType); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \ + ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion); + CL_PRINTF(cliBuf); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_BT_PATCH_VER, &btPatchVer); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)", "CoexVer/ FwVer/ PatchVer", \ + GLCoexVerDate8812a2Ant, GLCoexVer8812a2Ant, fwVer, btPatchVer, btPatchVer); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", "Wifi channel informed to BT", \ + pCoexDm->wifiChnlInfo[0], pCoexDm->wifiChnlInfo[1], + pCoexDm->wifiChnlInfo[2]); + CL_PRINTF(cliBuf); + + // wifi status + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Wifi Status]============"); + CL_PRINTF(cliBuf); + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[BT Status]============"); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", "BT [status/ rssi/ retryCnt]", \ + ((pBtCoexist->btInfo.bBtDisabled)? ("disabled"): ((pCoexSta->bC2hBtInquiryPage)?("inquiry/page scan"):((BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus)? "non-connected idle": + ( (BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus)? "connected-idle":"busy")))), + pCoexSta->btRssi, pCoexSta->btRetryCnt); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP", \ + pBtLinkInfo->bScoExist, pBtLinkInfo->bHidExist, pBtLinkInfo->bPanExist, pBtLinkInfo->bA2dpExist); + CL_PRINTF(cliBuf); + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO); + + btInfoExt = pCoexSta->btInfoExt; + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Info A2DP rate", \ + (btInfoExt&BIT0)? "Basic rate":"EDR rate"); + CL_PRINTF(cliBuf); + + for(i=0; ibtInfoC2hCnt[i]) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", GLBtInfoSrc8812a2Ant[i], \ + pCoexSta->btInfoC2h[i][0], pCoexSta->btInfoC2h[i][1], + pCoexSta->btInfoC2h[i][2], pCoexSta->btInfoC2h[i][3], + pCoexSta->btInfoC2h[i][4], pCoexSta->btInfoC2h[i][5], + pCoexSta->btInfoC2h[i][6], pCoexSta->btInfoC2hCnt[i]); + CL_PRINTF(cliBuf); + } + } + + // Sw mechanism + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============"); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", "SM1[ShRf/ LpRA/ LimDig]", \ + pCoexDm->bCurRfRxLpfShrink, pCoexDm->bCurLowPenaltyRa, pCoexDm->bLimitedDig); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", \ + pCoexDm->bCurAgcTableEn, pCoexDm->bCurAdcBackOff, pCoexDm->bCurDacSwingOn, pCoexDm->curDacSwingLvl); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "Rate Mask", \ + pBtCoexist->btInfo.raMask); + CL_PRINTF(cliBuf); + + // Fw mechanism + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============"); + CL_PRINTF(cliBuf); + + psTdmaCase = pCoexDm->curPsTdma; + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d/%d)", "PS TDMA", \ + pCoexDm->psTdmaPara[0], pCoexDm->psTdmaPara[1], + pCoexDm->psTdmaPara[2], pCoexDm->psTdmaPara[3], + pCoexDm->psTdmaPara[4], psTdmaCase, pCoexDm->bAutoTdmaAdjust, pCoexDm->bAutoTdmaAdjustLowRssi); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "DecBtPwr/ IgnWlanAct", \ + pCoexDm->curBtDecPwrLvl, pCoexDm->bCurIgnoreWlanAct); + CL_PRINTF(cliBuf); + + // Hw setting + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "RF-A, 0x1e initVal", \ + pCoexDm->btRf0x1eBackup); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", "backup ARFR1/ARFR2/RL/AMaxTime", \ + pCoexDm->backupArfrCnt1, pCoexDm->backupArfrCnt2, pCoexDm->backupRetryLimit, pCoexDm->backupAmpduMaxTime); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x430); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x434); + u2Tmp[0] = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0x42a); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x456); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", "0x430/0x434/0x42a/0x456", \ + u4Tmp[0], u4Tmp[1], u2Tmp[0], u1Tmp[0]); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x778); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x6cc); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x ", "0x778 (W_Act)/ 0x6cc (CoTab Sel)", \ + u1Tmp[0], u1Tmp[1]); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x8db); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xc5b); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x8db(ADC)/0xc5b[29:25](DAC)", \ + ((u1Tmp[0]&0x60)>>5), ((u1Tmp[1]&0x3e)>>1)); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xcb3); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xcb7); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0xcb3/ 0xcb7", \ + u1Tmp[0], u1Tmp[1]); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x40); + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x4c); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x974); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x40/ 0x4c[24:23]/ 0x974", \ + u1Tmp[0], ((u4Tmp[0]&0x01800000)>>23), u4Tmp[1]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x550); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x522); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x550(bcn ctrl)/0x522", \ + u4Tmp[0], u1Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc50); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xa0a); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0xc50(DIG)/0xa0a(CCK-TH)", \ + u4Tmp[0], u1Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xf48); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xa5b); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xa5c); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0xf48/ 0xa5b (FA cnt-- OFDM : CCK)", \ + u4Tmp[0], (u1Tmp[0]<<8) + u1Tmp[1] ); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c0); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c4); + u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c8); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x6cc); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", \ + u4Tmp[0], u4Tmp[1], u4Tmp[2], u1Tmp[0]); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x770(high-pri rx/tx)", \ + pCoexSta->highPriorityRx, pCoexSta->highPriorityTx); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x774(low-pri rx/tx)", \ + pCoexSta->lowPriorityRx, pCoexSta->lowPriorityTx); + CL_PRINTF(cliBuf); +#if(BT_AUTO_REPORT_ONLY_8812A_2ANT == 1) + halbtc8812a2ant_MonitorBtCtr(pBtCoexist); +#endif + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + + +VOID +EXhalbtc8812a2ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + BOOLEAN bWifiUnder5G=FALSE; + + if(BTC_IPS_ENTER == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS ENTER notify\n")); + pCoexSta->bUnderIps = TRUE; + halbtc8812a2ant_CoexAllOff(pBtCoexist); + halbtc8812a2ant_SetAntPath(pBtCoexist, BTC_ANT_WIFI_AT_CPL_AUX, FALSE, TRUE); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS notify, force set BT to ignore Wlan active!!\n")); + halbtc8812a2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE); + EXhalbtc8812a2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); + } + else if(BTC_IPS_LEAVE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS LEAVE notify\n")); + pCoexSta->bUnderIps = FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_5G, &bWifiUnder5G); + if(!bWifiUnder5G) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS notify, force set BT NOT to ignore Wlan active!!\n")); + halbtc8812a2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE); + } + } +} + +VOID +EXhalbtc8812a2ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_LPS_ENABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS ENABLE notify\n")); + pCoexSta->bUnderLps = TRUE; + } + else if(BTC_LPS_DISABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS DISABLE notify\n")); + pCoexSta->bUnderLps = FALSE; + } +} + +VOID +EXhalbtc8812a2ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_SCAN_START == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n")); + } + else if(BTC_SCAN_FINISH == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n")); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_AP_NUM, &pCoexSta->nScanAPNum); + } +} + +VOID +EXhalbtc8812a2ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_ASSOCIATE_START == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n")); + } + else if(BTC_ASSOCIATE_FINISH == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n")); + } +} + +VOID +EXhalbtc8812a2ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + u1Byte dataLen=5; + u1Byte buf[6] = {0}; + u1Byte H2C_Parameter[3] ={0}; + u4Byte wifiBw; + u1Byte wifiCentralChnl; + + if(pBtCoexist->bManualControl || + pBtCoexist->bStopCoexDm || + pBtCoexist->btInfo.bBtDisabled ) + return; + + if(BTC_MEDIA_CONNECT == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA connect notify\n")); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA disconnect notify\n")); + } + + // only 2.4G we need to inform bt the chnl mask + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, &wifiCentralChnl); + if( (BTC_MEDIA_CONNECT == type) && + (wifiCentralChnl <= 14) ) + { + H2C_Parameter[0] = 0x1; + H2C_Parameter[1] = wifiCentralChnl; + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + H2C_Parameter[2] = 0x30; + else + H2C_Parameter[2] = 0x20; + } + + pCoexDm->wifiChnlInfo[0] = H2C_Parameter[0]; + pCoexDm->wifiChnlInfo[1] = H2C_Parameter[1]; + pCoexDm->wifiChnlInfo[2] = H2C_Parameter[2]; + + buf[0] = dataLen; + buf[1] = 0x5; // OP_Code + buf[2] = 0x3; // OP_Code_Length + buf[3] = H2C_Parameter[0]; // OP_Code_Content + buf[4] = H2C_Parameter[1]; + buf[5] = H2C_Parameter[2]; + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_CTRL_BT_COEX, (PVOID)&buf[0]); +} + +VOID +EXhalbtc8812a2ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(type == BTC_PACKET_DHCP) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], DHCP Packet notify\n")); + } + +} + +VOID +EXhalbtc8812a2ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + u1Byte btInfo=0; + u1Byte i, rspSource=0; + BOOLEAN bBtBusy=FALSE, bLimitedDig=FALSE; + BOOLEAN bWifiConnected=FALSE, bBtHsOn=FALSE, bWifiUnder5G=FALSE; + + pCoexSta->bC2hBtInfoReqSent = FALSE; + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_5G, &bWifiUnder5G); + + rspSource = tmpBuf[0]&0xf; + if(rspSource >= BT_INFO_SRC_8812A_2ANT_MAX) + rspSource = BT_INFO_SRC_8812A_2ANT_WIFI_FW; + pCoexSta->btInfoC2hCnt[rspSource]++; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Bt info[%d], length=%d, hex data=[", rspSource, length)); + for(i=0; ibtInfoC2h[rspSource][i] = tmpBuf[i]; + if(i == 1) + btInfo = tmpBuf[i]; + if(i == length-1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x]\n", tmpBuf[i])); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x, ", tmpBuf[i])); + } + } + + if(BT_INFO_SRC_8812A_2ANT_WIFI_FW != rspSource) + { + pCoexSta->btRetryCnt = // [3:0] + pCoexSta->btInfoC2h[rspSource][2]&0xf; + + pCoexSta->btRssi = + pCoexSta->btInfoC2h[rspSource][3]*2+10; + + pCoexSta->btInfoExt = + pCoexSta->btInfoC2h[rspSource][4]; + + // Here we need to resend some wifi info to BT + // because bt is reset and loss of the info. + if( (pCoexSta->btInfoExt & BIT1) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n")); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + if(bWifiConnected) + { + EXhalbtc8812a2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_CONNECT); + } + else + { + EXhalbtc8812a2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); + } + } + + if( (pCoexSta->btInfoExt&BIT3) && !bWifiUnder5G) + { + // BT already ignored WlanAct + if(!pBtCoexist->bManualControl && !pBtCoexist->bStopCoexDm) + { + if(!pCoexSta->bUnderIps) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n")); + halbtc8812a2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE); + } + } + } + else + { + // BT already NOT ignore Wlan active, do nothing here. + + if(pCoexSta->bUnderIps) + { + // work around for 8812a combo hw bug => when IPS, wlanAct is always high. + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi is under IPS, set BT to ignore Wlan active!!\n")); + halbtc8812a2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE); + } + } + } + + // check BIT2 first ==> check if bt is under inquiry or page scan + if(btInfo & BT_INFO_8812A_2ANT_B_INQ_PAGE) + pCoexSta->bC2hBtInquiryPage = TRUE; + else + pCoexSta->bC2hBtInquiryPage = FALSE; + + // set link exist status + if(!(btInfo&BT_INFO_8812A_2ANT_B_CONNECTION)) + { + pCoexSta->bBtLinkExist = FALSE; + pCoexSta->bPanExist = FALSE; + pCoexSta->bA2dpExist = FALSE; + pCoexSta->bHidExist = FALSE; + pCoexSta->bScoExist = FALSE; + pCoexSta->bAclBusy = FALSE; + } + else // connection exists + { + pCoexSta->bBtLinkExist = TRUE; + if(btInfo & BT_INFO_8812A_2ANT_B_FTP) + pCoexSta->bPanExist = TRUE; + else + pCoexSta->bPanExist = FALSE; + if(btInfo & BT_INFO_8812A_2ANT_B_A2DP) + pCoexSta->bA2dpExist = TRUE; + else + pCoexSta->bA2dpExist = FALSE; + if(btInfo & BT_INFO_8812A_2ANT_B_HID) + pCoexSta->bHidExist = TRUE; + else + pCoexSta->bHidExist = FALSE; + if(btInfo & BT_INFO_8812A_2ANT_B_SCO_ESCO) + pCoexSta->bScoExist = TRUE; + else + pCoexSta->bScoExist = FALSE; + if(btInfo & BT_INFO_8812A_2ANT_B_ACL_BUSY) + pCoexSta->bAclBusy = TRUE; + else + pCoexSta->bAclBusy = FALSE; + + } + + halbtc8812a2ant_UpdateBtLinkInfo(pBtCoexist); + + if(!(btInfo&BT_INFO_8812A_2ANT_B_CONNECTION)) + { + pCoexDm->btStatus = BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n")); + } + else if(btInfo == BT_INFO_8812A_2ANT_B_CONNECTION) // connection exists but no busy + { + pCoexDm->btStatus = BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n")); + } + else if((btInfo&BT_INFO_8812A_2ANT_B_SCO_ESCO) || + (btInfo&BT_INFO_8812A_2ANT_B_SCO_BUSY)) + { + pCoexDm->btStatus = BT_8812A_2ANT_BT_STATUS_SCO_BUSY; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT SCO busy!!!\n")); + } + else if(btInfo&BT_INFO_8812A_2ANT_B_ACL_BUSY) + { + pCoexDm->btStatus = BT_8812A_2ANT_BT_STATUS_ACL_BUSY; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT ACL busy!!!\n")); + } + else + { + pCoexDm->btStatus = BT_8812A_2ANT_BT_STATUS_MAX; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n")); + } + + if( (BT_8812A_2ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) || + (BT_8812A_2ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8812A_2ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + bBtBusy = TRUE; + if(!bWifiUnder5G) + bLimitedDig = TRUE; + } + else + { + bBtBusy = FALSE; + bLimitedDig = FALSE; + } + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bBtBusy); + + pCoexDm->bLimitedDig = bLimitedDig; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_LIMITED_DIG, &bLimitedDig); + + halbtc8812a2ant_RunCoexistMechanism(pBtCoexist); +} + +VOID +EXhalbtc8812a2ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte u1Tmp=0; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Halt notify\n")); + + halbtc8812a2ant_SetAntPath(pBtCoexist, BTC_ANT_WIFI_AT_CPL_AUX, FALSE, TRUE); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Halt notify, force set BT to ignore Wlan active!!\n")); + halbtc8812a2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE); + EXhalbtc8812a2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); + + // 0x522=0xff, pause tx + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x522, 0xff); + // 0x40[7:6]=2'b01, modify BT mode. + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x40, 0xc0, 0x2); + //PTA off. + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x40, 0x20, 0x0); + +} + +VOID +EXhalbtc8812a2ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ) +{ + static u1Byte disVerInfoCnt=0; + u4Byte fwVer=0, btPatchVer=0; + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ==========================Periodical===========================\n")); + + if(disVerInfoCnt <= 5) + { + disVerInfoCnt += 1; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ****************************************************************\n")); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Ant PG Num/ Ant Mech/ Ant Pos = %d/ %d/ %d\n", + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum, pBoardInfo->btdmAntPos)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT stack/ hci ext ver = %s / %d\n", + ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion)); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_BT_PATCH_VER, &btPatchVer); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CoexVer/ FwVer/ PatchVer = %d_%x/ 0x%x/ 0x%x(%d)\n", + GLCoexVerDate8812a2Ant, GLCoexVer8812a2Ant, fwVer, btPatchVer, btPatchVer)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ****************************************************************\n")); + } + +#if(BT_AUTO_REPORT_ONLY_8812A_2ANT == 0) + halbtc8812a2ant_QueryBtInfo(pBtCoexist); + halbtc8812a2ant_MonitorBtCtr(pBtCoexist); +// halbtc8812a2ant_MonitorBtEnableDisable(pBtCoexist); +#else + if( halbtc8812a2ant_IsWifiStatusChanged(pBtCoexist) || + pCoexDm->bAutoTdmaAdjust || + pCoexDm->bAutoTdmaAdjustLowRssi) + { + halbtc8812a2ant_RunCoexistMechanism(pBtCoexist); + } +#endif +} + +VOID +EXhalbtc8812a2ant_DbgControl( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte opCode, + IN u1Byte opLen, + IN pu1Byte pData + ) +{ + switch(opCode) + { + case BTC_DBG_SET_COEX_DEC_BT_PWR: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Set Dec BT power\n")); + { + u1Byte dataLen=4; + u1Byte buf[6] = {0}; + u1Byte decBtPwr=0, pwrLevel=0; + if(opLen == 2) + { + decBtPwr = pData[0]; + pwrLevel = pData[1]; + + buf[0] = dataLen; + buf[1] = 0x3; // OP_Code + buf[2] = 0x2; // OP_Code_Length + + buf[3] = decBtPwr; // OP_Code_Content + buf[4] = pwrLevel; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Set Dec BT power=%d, pwrLevel=%d\n", decBtPwr, pwrLevel)); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_CTRL_BT_COEX, (PVOID)&buf[0]); + } + } + break; + + case BTC_DBG_SET_COEX_BT_AFH_MAP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Set BT AFH Map\n")); + { + u1Byte dataLen=5; + u1Byte buf[6] = {0}; + if(opLen == 3) + { + buf[0] = dataLen; + buf[1] = 0x5; // OP_Code + buf[2] = 0x3; // OP_Code_Length + + buf[3] = pData[0]; // OP_Code_Content + buf[4] = pData[1]; + buf[5] = pData[2]; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Set BT AFH Map = %02x %02x %02x\n", + pData[0], pData[1], pData[2])); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_CTRL_BT_COEX, (PVOID)&buf[0]); + } + } + break; + + case BTC_DBG_SET_COEX_BT_IGNORE_WLAN_ACT: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Set BT Ignore Wlan Active\n")); + { + u1Byte dataLen=3; + u1Byte buf[6] = {0}; + if(opLen == 1) + { + buf[0] = dataLen; + buf[1] = 0x1; // OP_Code + buf[2] = 0x1; // OP_Code_Length + + buf[3] = pData[0]; // OP_Code_Content + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Set BT Ignore Wlan Active = 0x%x\n", + pData[0])); + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_CTRL_BT_COEX, (PVOID)&buf[0]); + } + } + break; + + default: + break; + } +} + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8812a2Ant.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8812a2Ant.h new file mode 100644 index 000000000..bf60763c5 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8812a2Ant.h @@ -0,0 +1,250 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//=========================================== +// The following is for 8812A 2Ant BT Co-exist definition +//=========================================== +#define BT_AUTO_REPORT_ONLY_8812A_2ANT 0 + +#define BT_INFO_8812A_2ANT_B_FTP BIT7 +#define BT_INFO_8812A_2ANT_B_A2DP BIT6 +#define BT_INFO_8812A_2ANT_B_HID BIT5 +#define BT_INFO_8812A_2ANT_B_SCO_BUSY BIT4 +#define BT_INFO_8812A_2ANT_B_ACL_BUSY BIT3 +#define BT_INFO_8812A_2ANT_B_INQ_PAGE BIT2 +#define BT_INFO_8812A_2ANT_B_SCO_ESCO BIT1 +#define BT_INFO_8812A_2ANT_B_CONNECTION BIT0 + +#define BT_INFO_8812A_2ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ + (((_BT_INFO_EXT_&BIT0))? TRUE:FALSE) + +#define BTC_RSSI_COEX_THRESH_TOL_8812A_2ANT 2 +#define NOISY_AP_NUM_THRESH_8812A 50 + + +typedef enum _BT_INFO_SRC_8812A_2ANT{ + BT_INFO_SRC_8812A_2ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8812A_2ANT_BT_RSP = 0x1, + BT_INFO_SRC_8812A_2ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8812A_2ANT_MAX +}BT_INFO_SRC_8812A_2ANT,*PBT_INFO_SRC_8812A_2ANT; + +typedef enum _BT_8812A_2ANT_BT_STATUS{ + BT_8812A_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8812A_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8812A_2ANT_BT_STATUS_INQ_PAGE = 0x2, + BT_8812A_2ANT_BT_STATUS_ACL_BUSY = 0x3, + BT_8812A_2ANT_BT_STATUS_SCO_BUSY = 0x4, + BT_8812A_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, + BT_8812A_2ANT_BT_STATUS_MAX +}BT_8812A_2ANT_BT_STATUS,*PBT_8812A_2ANT_BT_STATUS; + +typedef enum _BT_8812A_2ANT_COEX_ALGO{ + BT_8812A_2ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8812A_2ANT_COEX_ALGO_SCO = 0x1, + BT_8812A_2ANT_COEX_ALGO_SCO_HID = 0x2, + BT_8812A_2ANT_COEX_ALGO_HID = 0x3, + BT_8812A_2ANT_COEX_ALGO_A2DP = 0x4, + BT_8812A_2ANT_COEX_ALGO_A2DP_PANHS = 0x5, + BT_8812A_2ANT_COEX_ALGO_PANEDR = 0x6, + BT_8812A_2ANT_COEX_ALGO_PANHS = 0x7, + BT_8812A_2ANT_COEX_ALGO_PANEDR_A2DP = 0x8, + BT_8812A_2ANT_COEX_ALGO_PANEDR_HID = 0x9, + BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0xa, + BT_8812A_2ANT_COEX_ALGO_HID_A2DP_PANHS = 0xb, + BT_8812A_2ANT_COEX_ALGO_HID_A2DP = 0xc, + BT_8812A_2ANT_COEX_ALGO_MAX = 0xd +}BT_8812A_2ANT_COEX_ALGO,*PBT_8812A_2ANT_COEX_ALGO; + +typedef struct _COEX_DM_8812A_2ANT{ + // fw mechanism + u1Byte preBtDecPwrLvl; + u1Byte curBtDecPwrLvl; + u1Byte preFwDacSwingLvl; + u1Byte curFwDacSwingLvl; + BOOLEAN bCurIgnoreWlanAct; + BOOLEAN bPreIgnoreWlanAct; + u1Byte prePsTdma; + u1Byte curPsTdma; + u1Byte psTdmaPara[5]; + u1Byte psTdmaDuAdjType; + BOOLEAN bAutoTdmaAdjust; + BOOLEAN bAutoTdmaAdjustLowRssi; + BOOLEAN bPrePsTdmaOn; + BOOLEAN bCurPsTdmaOn; + BOOLEAN bPreBtAutoReport; + BOOLEAN bCurBtAutoReport; + u1Byte preLps; + u1Byte curLps; + u1Byte preRpwm; + u1Byte curRpwm; + BOOLEAN bPreEnablePTA; + BOOLEAN bCurEnablePTA; + + + // sw mechanism + BOOLEAN bPreRfRxLpfShrink; + BOOLEAN bCurRfRxLpfShrink; + u4Byte btRf0x1eBackup; + BOOLEAN bPreLowPenaltyRa; + BOOLEAN bCurLowPenaltyRa; + BOOLEAN bPreDacSwingOn; + u4Byte preDacSwingLvl; + BOOLEAN bCurDacSwingOn; + u4Byte curDacSwingLvl; + BOOLEAN bPreAdcBackOff; + BOOLEAN bCurAdcBackOff; + BOOLEAN bPreAgcTableEn; + BOOLEAN bCurAgcTableEn; + u4Byte preVal0x6c0; + u4Byte curVal0x6c0; + u4Byte preVal0x6c4; + u4Byte curVal0x6c4; + u4Byte preVal0x6c8; + u4Byte curVal0x6c8; + u1Byte preVal0x6cc; + u1Byte curVal0x6cc; + BOOLEAN bLimitedDig; + u4Byte backupArfrCnt1; // Auto Rate Fallback Retry cnt + u4Byte backupArfrCnt2; // Auto Rate Fallback Retry cnt + u2Byte backupRetryLimit; + u1Byte backupAmpduMaxTime; + + // algorithm related + u1Byte preAlgorithm; + u1Byte curAlgorithm; + u1Byte btStatus; + u1Byte wifiChnlInfo[3]; + + u4Byte preRaMask; + u4Byte curRaMask; + u1Byte curRaMaskType; + u1Byte preArfrType; + u1Byte curArfrType; + u1Byte preRetryLimitType; + u1Byte curRetryLimitType; + u1Byte preAmpduTimeType; + u1Byte curAmpduTimeType; +} COEX_DM_8812A_2ANT, *PCOEX_DM_8812A_2ANT; + +typedef struct _COEX_STA_8812A_2ANT{ + BOOLEAN bBtLinkExist; + BOOLEAN bScoExist; + BOOLEAN bA2dpExist; + BOOLEAN bHidExist; + BOOLEAN bPanExist; + BOOLEAN bAclBusy; + + BOOLEAN bUnderLps; + BOOLEAN bUnderIps; + u4Byte highPriorityTx; + u4Byte highPriorityRx; + u4Byte lowPriorityTx; + u4Byte lowPriorityRx; + u1Byte btRssi; + u1Byte preBtRssiState; + u1Byte preBtDisabled; + u1Byte preWifiRssiState[4]; + BOOLEAN bC2hBtInfoReqSent; + u1Byte btInfoC2h[BT_INFO_SRC_8812A_2ANT_MAX][10]; + u4Byte btInfoC2hCnt[BT_INFO_SRC_8812A_2ANT_MAX]; + u4Byte prebtInfoC2hCnt_BT_RSP; + u4Byte prebtInfoC2hCnt_BT_SEND; + u4Byte btInfoQueryCnt; + BOOLEAN bC2hBtInquiryPage; + u1Byte btRetryCnt; + u1Byte btInfoExt; + u1Byte nScanAPNum; + + u4Byte nCRCOK_CCK; + u4Byte nCRCOK_11g; + u4Byte nCRCOK_11n; + u4Byte nCRCOK_11nAgg; + + u4Byte nCRCErr_CCK; + u4Byte nCRCErr_11g; + u4Byte nCRCErr_11n; + u4Byte nCRCErr_11nAgg; + + u1Byte nCoexTableType; + BOOLEAN bForceLpsOn; + + u1Byte disVerInfoCnt; + +}COEX_STA_8812A_2ANT, *PCOEX_STA_8812A_2ANT; + +//=========================================== +// The following is interface which will notify coex module. +//=========================================== +VOID +EXhalbtc8812a2ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8812a2ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ); +VOID +EXhalbtc8812a2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8812a2ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8812a2ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8812a2ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8812a2ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8812a2ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8812a2ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8812a2ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ); +VOID +EXhalbtc8812a2ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8812a2ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8812a2ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8812a2ant_DbgControl( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte opCode, + IN u1Byte opLen, + IN pu1Byte pData + ); +VOID +EXhalbtc8812a2ant_BTOffOnNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte BTstatus + ); + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8821a1Ant.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8821a1Ant.c new file mode 100644 index 000000000..df3507765 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8821a1Ant.c @@ -0,0 +1,3434 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//============================================================ +// Description: +// +// This file is for 8821A_1ANT Co-exist mechanism +// +// History +// 2012/11/15 Cosa first check in. +// +//============================================================ + +//============================================================ +// include files +//============================================================ +#include "Mp_Precomp.h" + +#if WPP_SOFTWARE_TRACE +#include "HalBtc8821a1Ant.tmh" +#endif + +#if(BT_30_SUPPORT == 1) +//============================================================ +// Global variables, these are static variables +//============================================================ +static COEX_DM_8821A_1ANT GLCoexDm8821a1Ant; +static PCOEX_DM_8821A_1ANT pCoexDm=&GLCoexDm8821a1Ant; +static COEX_STA_8821A_1ANT GLCoexSta8821a1Ant; +static PCOEX_STA_8821A_1ANT pCoexSta=&GLCoexSta8821a1Ant; + +const char *const GLBtInfoSrc8821a1Ant[]={ + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; + +u4Byte GLCoexVerDate8821a1Ant=20140306; +u4Byte GLCoexVer8821a1Ant=0x4b; + +//============================================================ +// local function proto type if needed +//============================================================ +//============================================================ +// local function start with halbtc8821a1ant_ +//============================================================ +u1Byte +halbtc8821a1ant_BtRssiState( + u1Byte levelNum, + u1Byte rssiThresh, + u1Byte rssiThresh1 + ) +{ + s4Byte btRssi=0; + u1Byte btRssiState=pCoexSta->preBtRssiState; + + btRssi = pCoexSta->btRssi; + + if(levelNum == 2) + { + if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW)) + { + if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT)) + { + btRssiState = BTC_RSSI_STATE_HIGH; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else + { + if(btRssi < rssiThresh) + { + btRssiState = BTC_RSSI_STATE_LOW; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + else if(levelNum == 3) + { + if(rssiThresh > rssiThresh1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Rssi thresh error!!\n")); + return pCoexSta->preBtRssiState; + } + + if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW)) + { + if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT)) + { + btRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_MEDIUM) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_MEDIUM)) + { + if(btRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT)) + { + btRssiState = BTC_RSSI_STATE_HIGH; + } + else if(btRssi < rssiThresh) + { + btRssiState = BTC_RSSI_STATE_LOW; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_MEDIUM; + } + } + else + { + if(btRssi < rssiThresh1) + { + btRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + + pCoexSta->preBtRssiState = btRssiState; + + return btRssiState; +} + +u1Byte +halbtc8821a1ant_WifiRssiState( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte index, + IN u1Byte levelNum, + IN u1Byte rssiThresh, + IN u1Byte rssiThresh1 + ) +{ + s4Byte wifiRssi=0; + u1Byte wifiRssiState=pCoexSta->preWifiRssiState[index]; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); + + if(levelNum == 2) + { + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else + { + if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + else if(levelNum == 3) + { + if(rssiThresh > rssiThresh1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi RSSI thresh error!!\n")); + return pCoexSta->preWifiRssiState[index]; + } + + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT)) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_MEDIUM) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_MEDIUM)) + { + if(wifiRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_MEDIUM; + } + } + else + { + if(wifiRssi < rssiThresh1) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + + pCoexSta->preWifiRssiState[index] = wifiRssiState; + + return wifiRssiState; +} + +VOID +halbtc8821a1ant_UpdateRaMask( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u4Byte disRateMask + ) +{ + pCoexDm->curRaMask = disRateMask; + + if( bForceExec || (pCoexDm->preRaMask != pCoexDm->curRaMask)) + { + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_UPDATE_RAMASK, &pCoexDm->curRaMask); + } + pCoexDm->preRaMask = pCoexDm->curRaMask; +} + +VOID +halbtc8821a1ant_AutoRateFallbackRetry( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + BOOLEAN bWifiUnderBMode=FALSE; + + pCoexDm->curArfrType = type; + + if( bForceExec || (pCoexDm->preArfrType != pCoexDm->curArfrType)) + { + switch(pCoexDm->curArfrType) + { + case 0: // normal mode + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x430, pCoexDm->backupArfrCnt1); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x434, pCoexDm->backupArfrCnt2); + break; + case 1: + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, &bWifiUnderBMode); + if(bWifiUnderBMode) + { + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x430, 0x0); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x434, 0x01010101); + } + else + { + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x430, 0x0); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x434, 0x04030201); + } + break; + default: + break; + } + } + + pCoexDm->preArfrType = pCoexDm->curArfrType; +} + +VOID +halbtc8821a1ant_RetryLimit( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + pCoexDm->curRetryLimitType = type; + + if( bForceExec || (pCoexDm->preRetryLimitType != pCoexDm->curRetryLimitType)) + { + switch(pCoexDm->curRetryLimitType) + { + case 0: // normal mode + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x42a, pCoexDm->backupRetryLimit); + break; + case 1: // retry limit=8 + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x42a, 0x0808); + break; + default: + break; + } + } + + pCoexDm->preRetryLimitType = pCoexDm->curRetryLimitType; +} + +VOID +halbtc8821a1ant_AmpduMaxTime( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + pCoexDm->curAmpduTimeType = type; + + if( bForceExec || (pCoexDm->preAmpduTimeType != pCoexDm->curAmpduTimeType)) + { + switch(pCoexDm->curAmpduTimeType) + { + case 0: // normal mode + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x456, pCoexDm->backupAmpduMaxTime); + break; + case 1: // AMPDU timw = 0x38 * 32us + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x456, 0x38); + break; + default: + break; + } + } + + pCoexDm->preAmpduTimeType = pCoexDm->curAmpduTimeType; +} + +VOID +halbtc8821a1ant_LimitedTx( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte raMaskType, + IN u1Byte arfrType, + IN u1Byte retryLimitType, + IN u1Byte ampduTimeType + ) +{ + switch(raMaskType) + { + case 0: // normal mode + halbtc8821a1ant_UpdateRaMask(pBtCoexist, bForceExec, 0x0); + break; + case 1: // disable cck 1/2 + halbtc8821a1ant_UpdateRaMask(pBtCoexist, bForceExec, 0x00000003); + break; + case 2: // disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 + halbtc8821a1ant_UpdateRaMask(pBtCoexist, bForceExec, 0x0001f1f7); + break; + default: + break; + } + + halbtc8821a1ant_AutoRateFallbackRetry(pBtCoexist, bForceExec, arfrType); + halbtc8821a1ant_RetryLimit(pBtCoexist, bForceExec, retryLimitType); + halbtc8821a1ant_AmpduMaxTime(pBtCoexist, bForceExec, ampduTimeType); +} + +VOID +halbtc8821a1ant_LimitedRx( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bRejApAggPkt, + IN BOOLEAN bBtCtrlAggBufSize, + IN u1Byte aggBufSize + ) +{ + BOOLEAN bRejectRxAgg=bRejApAggPkt; + BOOLEAN bBtCtrlRxAggSize=bBtCtrlAggBufSize; + u1Byte rxAggSize=aggBufSize; + + //============================================ + // Rx Aggregation related setting + //============================================ + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, &bRejectRxAgg); + // decide BT control aggregation buf size or not + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, &bBtCtrlRxAggSize); + // aggregation buf size, only work when BT control Rx aggregation size. + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_AGG_BUF_SIZE, &rxAggSize); + // real update aggregation setting + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); + + +} + +VOID +halbtc8821a1ant_MonitorBtCtr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte regHPTxRx, regLPTxRx, u4Tmp, u4Tmp1; + u4Byte regHPTx=0, regHPRx=0, regLPTx=0, regLPRx=0; + u1Byte u1Tmp, u1Tmp1; + s4Byte wifiRssi; +#if 0 + //to avoid 0x76e[3] = 1 (WLAN_Act control by PTA) during IPS + if (! (pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x76e) & 0x8) ) + { + pCoexSta->highPriorityTx = 65535; + pCoexSta->highPriorityRx = 65535; + pCoexSta->lowPriorityTx = 65535; + pCoexSta->lowPriorityRx = 65535; + return; + } +#endif + regHPTxRx = 0x770; + regLPTxRx = 0x774; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regHPTxRx); + regHPTx = u4Tmp & bMaskLWord; + regHPRx = (u4Tmp & bMaskHWord)>>16; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regLPTxRx); + regLPTx = u4Tmp & bMaskLWord; + regLPRx = (u4Tmp & bMaskHWord)>>16; + + pCoexSta->highPriorityTx = regHPTx; + pCoexSta->highPriorityRx = regHPRx; + pCoexSta->lowPriorityTx = regLPTx; + pCoexSta->lowPriorityRx = regLPRx; + + // reset counter + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0xc); +} + +VOID +halbtc8821a1ant_QueryBtInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + pCoexSta->bC2hBtInfoReqSent = TRUE; + + H2C_Parameter[0] |= BIT0; // trigger + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Query Bt Info, FW write 0x61=0x%x\n", + H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x61, 1, H2C_Parameter); +} + +BOOLEAN +halbtc8821a1ant_IsWifiStatusChanged( + IN PBTC_COEXIST pBtCoexist + ) +{ + static BOOLEAN bPreWifiBusy=FALSE, bPreUnder4way=FALSE, bPreBtHsOn=FALSE; + BOOLEAN bWifiBusy=FALSE, bUnder4way=FALSE, bBtHsOn=FALSE; + BOOLEAN bWifiConnected=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &bUnder4way); + + if(bWifiConnected) + { + if(bWifiBusy != bPreWifiBusy) + { + bPreWifiBusy = bWifiBusy; + return TRUE; + } + if(bUnder4way != bPreUnder4way) + { + bPreUnder4way = bUnder4way; + return TRUE; + } + if(bBtHsOn != bPreBtHsOn) + { + bPreBtHsOn = bBtHsOn; + return TRUE; + } + } + + return FALSE; +} + +VOID +halbtc8821a1ant_UpdateBtLinkInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bBtHsOn=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + pBtLinkInfo->bBtLinkExist = pCoexSta->bBtLinkExist; + pBtLinkInfo->bScoExist = pCoexSta->bScoExist; + pBtLinkInfo->bA2dpExist = pCoexSta->bA2dpExist; + pBtLinkInfo->bPanExist = pCoexSta->bPanExist; + pBtLinkInfo->bHidExist = pCoexSta->bHidExist; + + // work around for HS mode. + if(bBtHsOn) + { + pBtLinkInfo->bPanExist = TRUE; + pBtLinkInfo->bBtLinkExist = TRUE; + } + + // check if Sco only + if( pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bScoOnly = TRUE; + else + pBtLinkInfo->bScoOnly = FALSE; + + // check if A2dp only + if( !pBtLinkInfo->bScoExist && + pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bA2dpOnly = TRUE; + else + pBtLinkInfo->bA2dpOnly = FALSE; + + // check if Pan only + if( !pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bPanOnly = TRUE; + else + pBtLinkInfo->bPanOnly = FALSE; + + // check if Hid only + if( !pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + pBtLinkInfo->bHidExist ) + pBtLinkInfo->bHidOnly = TRUE; + else + pBtLinkInfo->bHidOnly = FALSE; +} + +u1Byte +halbtc8821a1ant_ActionAlgorithm( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bBtHsOn=FALSE; + u1Byte algorithm=BT_8821A_1ANT_COEX_ALGO_UNDEFINED; + u1Byte numOfDiffProfile=0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + if(!pBtLinkInfo->bBtLinkExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], No BT link exists!!!\n")); + return algorithm; + } + + if(pBtLinkInfo->bScoExist) + numOfDiffProfile++; + if(pBtLinkInfo->bHidExist) + numOfDiffProfile++; + if(pBtLinkInfo->bPanExist) + numOfDiffProfile++; + if(pBtLinkInfo->bA2dpExist) + numOfDiffProfile++; + + if(numOfDiffProfile == 1) + { + if(pBtLinkInfo->bScoExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO only\n")); + algorithm = BT_8821A_1ANT_COEX_ALGO_SCO; + } + else + { + if(pBtLinkInfo->bHidExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID only\n")); + algorithm = BT_8821A_1ANT_COEX_ALGO_HID; + } + else if(pBtLinkInfo->bA2dpExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = A2DP only\n")); + algorithm = BT_8821A_1ANT_COEX_ALGO_A2DP; + } + else if(pBtLinkInfo->bPanExist) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = PAN(HS) only\n")); + algorithm = BT_8821A_1ANT_COEX_ALGO_PANHS; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = PAN(EDR) only\n")); + algorithm = BT_8821A_1ANT_COEX_ALGO_PANEDR; + } + } + } + } + else if(numOfDiffProfile == 2) + { + if(pBtLinkInfo->bScoExist) + { + if(pBtLinkInfo->bHidExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + HID\n")); + algorithm = BT_8821A_1ANT_COEX_ALGO_HID; + } + else if(pBtLinkInfo->bA2dpExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + A2DP ==> SCO\n")); + algorithm = BT_8821A_1ANT_COEX_ALGO_SCO; + } + else if(pBtLinkInfo->bPanExist) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + PAN(HS)\n")); + algorithm = BT_8821A_1ANT_COEX_ALGO_SCO; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + PAN(EDR)\n")); + algorithm = BT_8821A_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } + else + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bA2dpExist ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID + A2DP\n")); + algorithm = BT_8821A_1ANT_COEX_ALGO_HID_A2DP; + } + else if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID + PAN(HS)\n")); + algorithm = BT_8821A_1ANT_COEX_ALGO_HID_A2DP; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID + PAN(EDR)\n")); + algorithm = BT_8821A_1ANT_COEX_ALGO_PANEDR_HID; + } + } + else if( pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = A2DP + PAN(HS)\n")); + algorithm = BT_8821A_1ANT_COEX_ALGO_A2DP_PANHS; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = A2DP + PAN(EDR)\n")); + algorithm = BT_8821A_1ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } + } + else if(numOfDiffProfile == 3) + { + if(pBtLinkInfo->bScoExist) + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bA2dpExist ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + HID + A2DP ==> HID\n")); + algorithm = BT_8821A_1ANT_COEX_ALGO_HID; + } + else if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + HID + PAN(HS)\n")); + algorithm = BT_8821A_1ANT_COEX_ALGO_HID_A2DP; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + HID + PAN(EDR)\n")); + algorithm = BT_8821A_1ANT_COEX_ALGO_PANEDR_HID; + } + } + else if( pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + A2DP + PAN(HS)\n")); + algorithm = BT_8821A_1ANT_COEX_ALGO_SCO; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + A2DP + PAN(EDR) ==> HID\n")); + algorithm = BT_8821A_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } + else + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID + A2DP + PAN(HS)\n")); + algorithm = BT_8821A_1ANT_COEX_ALGO_HID_A2DP; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = HID + A2DP + PAN(EDR)\n")); + algorithm = BT_8821A_1ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } + else if(numOfDiffProfile >= 3) + { + if(pBtLinkInfo->bScoExist) + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Error!!! BT Profile = SCO + HID + A2DP + PAN(HS)\n")); + + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Profile = SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n")); + algorithm = BT_8821A_1ANT_COEX_ALGO_PANEDR_HID; + } + } + } + } + + return algorithm; +} + +VOID +halbtc8821a1ant_SetBtAutoReport( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bEnableAutoReport + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + H2C_Parameter[0] = 0; + + if(bEnableAutoReport) + { + H2C_Parameter[0] |= BIT0; + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], BT FW auto report : %s, FW write 0x68=0x%x\n", + (bEnableAutoReport? "Enabled!!":"Disabled!!"), H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x68, 1, H2C_Parameter); +} + +VOID +halbtc8821a1ant_BtAutoReport( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bEnableAutoReport + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s BT Auto report = %s\n", + (bForceExec? "force to":""), ((bEnableAutoReport)? "Enabled":"Disabled"))); + pCoexDm->bCurBtAutoReport = bEnableAutoReport; + + if(!bForceExec) + { + if(pCoexDm->bPreBtAutoReport == pCoexDm->bCurBtAutoReport) + return; + } + halbtc8821a1ant_SetBtAutoReport(pBtCoexist, pCoexDm->bCurBtAutoReport); + + pCoexDm->bPreBtAutoReport = pCoexDm->bCurBtAutoReport; +} + +VOID +halbtc8821a1ant_SetSwPenaltyTxRateAdaptive( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bLowPenaltyRa + ) +{ + u1Byte H2C_Parameter[6] ={0}; + + H2C_Parameter[0] = 0x6; // opCode, 0x6= Retry_Penalty + + if(bLowPenaltyRa) + { + H2C_Parameter[1] |= BIT0; + H2C_Parameter[2] = 0x00; //normal rate except MCS7/6/5, OFDM54/48/36 + H2C_Parameter[3] = 0xf7; //MCS7 or OFDM54 + H2C_Parameter[4] = 0xf8; //MCS6 or OFDM48 + H2C_Parameter[5] = 0xf9; //MCS5 or OFDM36 + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set WiFi Low-Penalty Retry: %s", + (bLowPenaltyRa? "ON!!":"OFF!!") )); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x69, 6, H2C_Parameter); +} + +VOID +halbtc8821a1ant_LowPenaltyRa( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bLowPenaltyRa + ) +{ + pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa; + + if(!bForceExec) + { + if(pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa) + return; + } + halbtc8821a1ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa); + + pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa; +} + +VOID +halbtc8821a1ant_SetCoexTable( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte val0x6c0, + IN u4Byte val0x6c4, + IN u4Byte val0x6c8, + IN u1Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c0=0x%x\n", val0x6c0)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c0, val0x6c0); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c4=0x%x\n", val0x6c4)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c4, val0x6c4); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, val0x6c8); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc)); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cc, val0x6cc); +} + +VOID +halbtc8821a1ant_CoexTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u4Byte val0x6c0, + IN u4Byte val0x6c4, + IN u4Byte val0x6c8, + IN u1Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s write Coex Table 0x6c0=0x%x, 0x6c4=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n", + (bForceExec? "force to":""), val0x6c0, val0x6c4, val0x6c8, val0x6cc)); + pCoexDm->curVal0x6c0 = val0x6c0; + pCoexDm->curVal0x6c4 = val0x6c4; + pCoexDm->curVal0x6c8 = val0x6c8; + pCoexDm->curVal0x6cc = val0x6cc; + + if(!bForceExec) + { + if( (pCoexDm->preVal0x6c0 == pCoexDm->curVal0x6c0) && + (pCoexDm->preVal0x6c4 == pCoexDm->curVal0x6c4) && + (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) && + (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) ) + return; + } + halbtc8821a1ant_SetCoexTable(pBtCoexist, val0x6c0, val0x6c4, val0x6c8, val0x6cc); + + pCoexDm->preVal0x6c0 = pCoexDm->curVal0x6c0; + pCoexDm->preVal0x6c4 = pCoexDm->curVal0x6c4; + pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8; + pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc; +} + +VOID +halbtc8821a1ant_CoexTableWithType( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ********** CoexTable(%d) **********\n", type)); + + switch(type) + { + case 0: + halbtc8821a1ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x55555555, 0xffffff, 0x3); + break; + case 1: + halbtc8821a1ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 2: + halbtc8821a1ant_CoexTable(pBtCoexist, bForceExec, 0x5a5a5a5a, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 3: + halbtc8821a1ant_CoexTable(pBtCoexist, bForceExec, 0x5a5a5a5a, 0xaaaaaaaa, 0xffffff, 0x3); + break; + case 4: + halbtc8821a1ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0xaaaaaaaa, 0xffffff, 0x3); + break; + case 5: + halbtc8821a1ant_CoexTable(pBtCoexist, bForceExec, 0x5a5a5a5a, 0xaaaa5a5a, 0xffffff, 0x3); + break; + case 6: + halbtc8821a1ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0xaaaa5a5a, 0xffffff, 0x3); + break; + case 7: + halbtc8821a1ant_CoexTable(pBtCoexist, bForceExec, 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3); + break; + default: + break; + } +} + +VOID +halbtc8821a1ant_SetFwIgnoreWlanAct( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bEnable + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + if(bEnable) + { + H2C_Parameter[0] |= BIT0; // function enable + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set FW for BT Ignore Wlan_Act, FW write 0x63=0x%x\n", + H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x63, 1, H2C_Parameter); +} + +VOID +halbtc8821a1ant_IgnoreWlanAct( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bEnable + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Ignore WlanAct %s\n", + (bForceExec? "force to":""), (bEnable? "ON":"OFF"))); + pCoexDm->bCurIgnoreWlanAct = bEnable; + + if(!bForceExec) + { + if(pCoexDm->bPreIgnoreWlanAct == pCoexDm->bCurIgnoreWlanAct) + return; + } + halbtc8821a1ant_SetFwIgnoreWlanAct(pBtCoexist, bEnable); + + pCoexDm->bPreIgnoreWlanAct = pCoexDm->bCurIgnoreWlanAct; +} + +VOID +halbtc8821a1ant_SetFwPstdma( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte byte1, + IN u1Byte byte2, + IN u1Byte byte3, + IN u1Byte byte4, + IN u1Byte byte5 + ) +{ + u1Byte H2C_Parameter[5] ={0}; + u1Byte realByte1=byte1, realByte5=byte5; + BOOLEAN bApEnable=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + + if(bApEnable) + { + if(byte1&BIT4 && !(byte1&BIT5)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], FW for 1Ant AP mode\n")); + realByte1 &= ~BIT4; + realByte1 |= BIT5; + + realByte5 |= BIT5; + realByte5 &= ~BIT6; + } + } + + H2C_Parameter[0] = realByte1; + H2C_Parameter[1] = byte2; + H2C_Parameter[2] = byte3; + H2C_Parameter[3] = byte4; + H2C_Parameter[4] = realByte5; + + pCoexDm->psTdmaPara[0] = realByte1; + pCoexDm->psTdmaPara[1] = byte2; + pCoexDm->psTdmaPara[2] = byte3; + pCoexDm->psTdmaPara[3] = byte4; + pCoexDm->psTdmaPara[4] = realByte5; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], PS-TDMA H2C cmd =0x%x%08x\n", + H2C_Parameter[0], + H2C_Parameter[1]<<24|H2C_Parameter[2]<<16|H2C_Parameter[3]<<8|H2C_Parameter[4])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x60, 5, H2C_Parameter); +} + +VOID +halbtc8821a1ant_SetLpsRpwm( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + u1Byte lps=lpsVal; + u1Byte rpwm=rpwmVal; + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_LPS_VAL, &lps); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RPWM_VAL, &rpwm); +} + +VOID +halbtc8821a1ant_LpsRpwm( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + BOOLEAN bForceExecPwrCmd=FALSE; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s set lps/rpwm=0x%x/0x%x \n", + (bForceExec? "force to":""), lpsVal, rpwmVal)); + pCoexDm->curLps = lpsVal; + pCoexDm->curRpwm = rpwmVal; + + if(!bForceExec) + { + if( (pCoexDm->preLps == pCoexDm->curLps) && + (pCoexDm->preRpwm == pCoexDm->curRpwm) ) + { + return; + } + } + halbtc8821a1ant_SetLpsRpwm(pBtCoexist, lpsVal, rpwmVal); + + pCoexDm->preLps = pCoexDm->curLps; + pCoexDm->preRpwm = pCoexDm->curRpwm; +} + +VOID +halbtc8821a1ant_SwMechanism( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bLowPenaltyRA + ) +{ + halbtc8821a1ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, bLowPenaltyRA); +} + +VOID +halbtc8821a1ant_SetAntPath( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte antPosType, + IN BOOLEAN bInitHwCfg, + IN BOOLEAN bWifiOff + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + u4Byte fwVer=0, u4Tmp=0; + u1Byte H2C_Parameter[2] ={0}; + + if(bInitHwCfg) + { + // 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x4c); + u4Tmp &=~BIT23; + u4Tmp |= BIT24; + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x4c, u4Tmp); + + //0x765 = 0x18 + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x765, 0x18, 0x3); + + if(pBoardInfo->btdmAntPos == BTC_ANTENNA_AT_MAIN_PORT) + { + //tell firmware "antenna inverse" ==> WRONG firmware antenna control code.==>need fw to fix + H2C_Parameter[0] = 1; + H2C_Parameter[1] = 1; + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x65, 2, H2C_Parameter); + + //pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x64, 0x1, 0x1); //Main Ant to BT for IPS case 0x4c[23]=1 + } + else + { + //tell firmware "no antenna inverse" ==> WRONG firmware antenna control code.==>need fw to fix + H2C_Parameter[0] = 0; + H2C_Parameter[1] = 1; + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x65, 2, H2C_Parameter); + + //pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x64, 0x1, 0x0); //Aux Ant to BT for IPS case 0x4c[23]=1 + } + } + else if(bWifiOff) + { + // 0x4c[24:23]=00, Set Antenna control by BT_RFE_CTRL BT Vendor 0xac=0xf002 + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x4c); + u4Tmp &= ~BIT23; + u4Tmp &= ~BIT24; + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x4c, u4Tmp); + + //0x765 = 0x18 + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x765, 0x18, 0x3); + } + else + { + //0x765 = 0x0 + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x765, 0x18, 0x0); + } + + // ext switch setting + switch(antPosType) + { + case BTC_ANT_PATH_WIFI: + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0xcb4, 0x77); + if(pBoardInfo->btdmAntPos == BTC_ANTENNA_AT_MAIN_PORT) + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xcb7, 0x30, 0x1); + else + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xcb7, 0x30, 0x2); + break; + case BTC_ANT_PATH_BT: + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0xcb4, 0x77); + if(pBoardInfo->btdmAntPos == BTC_ANTENNA_AT_MAIN_PORT) + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xcb7, 0x30, 0x2); + else + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xcb7, 0x30, 0x1); + break; + default: + case BTC_ANT_PATH_PTA: + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0xcb4, 0x66); + if(pBoardInfo->btdmAntPos == BTC_ANTENNA_AT_MAIN_PORT) + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xcb7, 0x30, 0x1); + else + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xcb7, 0x30, 0x2); + break; + } +} + +VOID +halbtc8821a1ant_PsTdma( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bTurnOn, + IN u1Byte type + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + BOOLEAN bTurnOnByCnt=FALSE; + u1Byte psTdmaTypeByCnt=0, rssiAdjustVal=0; + //u4Byte fwVer=0; + + pCoexDm->bCurPsTdmaOn = bTurnOn; + pCoexDm->curPsTdma = type; + + if (pCoexDm->bCurPsTdmaOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ********** TDMA(on, %d) **********\n", + pCoexDm->curPsTdma)); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ********** TDMA(off, %d) **********\n", + pCoexDm->curPsTdma)); + } + + if(!bForceExec) + { + if( (pCoexDm->bPrePsTdmaOn == pCoexDm->bCurPsTdmaOn) && + (pCoexDm->prePsTdma == pCoexDm->curPsTdma) ) + return; + } + if(bTurnOn) + { + switch(type) + { + default: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x51, 0x1a, 0x1a, 0x0, 0x50); + break; + case 1: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x51, 0x3a, 0x03, 0x10, 0x50); + rssiAdjustVal = 11; + break; + case 2: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x51, 0x2b, 0x03, 0x10, 0x50); + rssiAdjustVal = 14; + break; + case 3: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x51, 0x1d, 0x1d, 0x0, 0x52); + break; + case 4: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x93, 0x15, 0x3, 0x14, 0x0); + rssiAdjustVal = 17; + break; + case 5: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x61, 0x15, 0x3, 0x11, 0x10); + break; + case 6: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x61, 0x20, 0x3, 0x11, 0x13); + break; + case 7: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x13, 0xc, 0x5, 0x0, 0x0); + break; + case 8: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x93, 0x25, 0x3, 0x10, 0x0); + break; + case 9: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x51, 0x21, 0x3, 0x10, 0x50); + rssiAdjustVal = 18; + break; + case 10: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x13, 0xa, 0xa, 0x0, 0x40); + break; + case 11: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x51, 0x15, 0x03, 0x10, 0x50); + rssiAdjustVal = 20; + break; + case 12: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x51, 0x0a, 0x0a, 0x0, 0x50); + break; + case 13: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x51, 0x12, 0x12, 0x0, 0x50); + break; + case 14: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x51, 0x21, 0x3, 0x10, 0x52); + break; + case 15: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x13, 0xa, 0x3, 0x8, 0x0); + break; + case 16: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x93, 0x15, 0x3, 0x10, 0x0); + rssiAdjustVal = 18; + break; + case 18: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x93, 0x25, 0x3, 0x10, 0x0); + rssiAdjustVal = 14; + break; + case 20: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x61, 0x35, 0x03, 0x11, 0x10); + break; + case 21: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x61, 0x25, 0x03, 0x11, 0x11); + break; + case 22: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x61, 0x25, 0x03, 0x11, 0x10); + break; + case 23: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x3, 0x31, 0x18); + rssiAdjustVal = 22; + break; + case 24: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0xe3, 0x15, 0x3, 0x31, 0x18); + rssiAdjustVal = 22; + break; + case 25: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0x3, 0x31, 0x18); + rssiAdjustVal = 22; + break; + case 26: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0x3, 0x31, 0x18); + rssiAdjustVal = 22; + break; + case 27: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x3, 0x31, 0x98); + rssiAdjustVal = 22; + break; + case 28: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x69, 0x25, 0x3, 0x31, 0x0); + break; + case 29: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0xab, 0x1a, 0x1a, 0x1, 0x10); + break; + case 30: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x51, 0x30, 0x3, 0x10, 0x10); + break; + case 31: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0xd3, 0x1a, 0x1a, 0, 0x58); + break; + case 32: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x61, 0x35, 0x3, 0x11, 0x11); + break; + case 33: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0xa3, 0x25, 0x3, 0x30, 0x90); + break; + case 34: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x53, 0x1a, 0x1a, 0x0, 0x10); + break; + case 35: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x63, 0x1a, 0x1a, 0x0, 0x10); + break; + case 36: + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0xd3, 0x12, 0x3, 0x14, 0x50); + break; + case 40: // SoftAP only with no sta associated,BT disable ,TDMA mode for power saving + /* here softap mode screen off will cost 70-80mA for phone */ + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x23, 0x18, 0x00, 0x10, 0x24); + break; + } + } + else + { + // disable PS tdma + switch(type) + { + case 8: //PTA Control + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x8, 0x0, 0x0, 0x0, 0x0); + halbtc8821a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, FALSE, FALSE); + break; + case 0: + default: //Software control, Antenna at BT side + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x0, 0x0); + halbtc8821a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FALSE, FALSE); + break; + case 9: //Software control, Antenna at WiFi side + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x0, 0x0); + halbtc8821a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_WIFI, FALSE, FALSE); + break; + case 10: // under 5G + halbtc8821a1ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x8, 0x0); + halbtc8821a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FALSE, FALSE); + break; + } + } + rssiAdjustVal =0; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, &rssiAdjustVal); + + // update pre state + pCoexDm->bPrePsTdmaOn = pCoexDm->bCurPsTdmaOn; + pCoexDm->prePsTdma = pCoexDm->curPsTdma; +} + +VOID +halbtc8821a1ant_CoexAllOff( + IN PBTC_COEXIST pBtCoexist + ) +{ + // sw all off + halbtc8821a1ant_SwMechanism(pBtCoexist, FALSE); + + // hw all off + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); +} + +BOOLEAN +halbtc8821a1ant_IsCommonAction( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bCommon=FALSE, bWifiConnected=FALSE, bWifiBusy=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + + if(!bWifiConnected && + BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non connected-idle + BT non connected-idle!!\n")); + halbtc8821a1ant_SwMechanism(pBtCoexist, FALSE); + + bCommon = TRUE; + } + else if(bWifiConnected && + (BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi connected + BT non connected-idle!!\n")); + halbtc8821a1ant_SwMechanism(pBtCoexist, FALSE); + + bCommon = TRUE; + } + else if(!bWifiConnected && + (BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non connected-idle + BT connected-idle!!\n")); + halbtc8821a1ant_SwMechanism(pBtCoexist, FALSE); + + bCommon = TRUE; + } + else if(bWifiConnected && + (BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi connected + BT connected-idle!!\n")); + halbtc8821a1ant_SwMechanism(pBtCoexist, FALSE); + + bCommon = TRUE; + } + else if(!bWifiConnected && + (BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE != pCoexDm->btStatus) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non connected-idle + BT Busy!!\n")); + halbtc8821a1ant_SwMechanism(pBtCoexist, FALSE); + + bCommon = TRUE; + } + else + { + if (bWifiBusy) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi Connected-Busy + BT Busy!!\n")); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi Connected-Idle + BT Busy!!\n")); + } + + bCommon = FALSE; + } + + return bCommon; +} + + +VOID +halbtc8821a1ant_TdmaDurationAdjustForAcl( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte wifiStatus + ) +{ + static s4Byte up,dn,m,n,WaitCount; + s4Byte result; //0: no change, +1: increase WiFi duration, -1: decrease WiFi duration + u1Byte retryCount=0, btInfoExt; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TdmaDurationAdjustForAcl()\n")); + + if( (BT_8821A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN == wifiStatus) || + (BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SCAN == wifiStatus) || + (BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT == wifiStatus) ) + { + if( pCoexDm->curPsTdma != 1 && + pCoexDm->curPsTdma != 2 && + pCoexDm->curPsTdma != 3 && + pCoexDm->curPsTdma != 9 ) + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + + up = 0; + dn = 0; + m = 1; + n= 3; + result = 0; + WaitCount = 0; + } + return; + } + + if(!pCoexDm->bAutoTdmaAdjust) + { + pCoexDm->bAutoTdmaAdjust = TRUE; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], first run TdmaDurationAdjust()!!\n")); + + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + //============ + up = 0; + dn = 0; + m = 1; + n= 3; + result = 0; + WaitCount = 0; + } + else + { + //accquire the BT TRx retry count from BT_Info byte2 + retryCount = pCoexSta->btRetryCnt; + btInfoExt = pCoexSta->btInfoExt; + result = 0; + WaitCount++; + + if(retryCount == 0) // no retry in the last 2-second duration + { + up++; + dn--; + + if (dn <= 0) + dn = 0; + + if(up >= n) // if s n 2 retry count0, hռeWiFi duration + { + WaitCount = 0; + n = 3; + up = 0; + dn = 0; + result = 1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Increase wifi duration!!\n")); + } + } + else if (retryCount <= 3) // <=3 retry in the last 2-second duration + { + up--; + dn++; + + if (up <= 0) + up = 0; + + if (dn == 2) // if s 2 2 retry count< 3, hկWiFi duration + { + if (WaitCount <= 2) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter<3!!\n")); + } + } + else //retry count > 3, un1 retry count > 3, hկWiFi duration + { + if (WaitCount == 1) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter>3!!\n")); + } + + if(result == -1) + { + if( (BT_INFO_8821A_1ANT_A2DP_BASIC_RATE(btInfoExt)) && + ((pCoexDm->curPsTdma == 1) ||(pCoexDm->curPsTdma == 2)) ) + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(pCoexDm->curPsTdma == 1) + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + } + else if(result == 1) + { + if( (BT_INFO_8821A_1ANT_A2DP_BASIC_RATE(btInfoExt)) && + ((pCoexDm->curPsTdma == 1) ||(pCoexDm->curPsTdma == 2)) ) + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + } + else //no change + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ********** TDMA(on, %d) **********\n", + pCoexDm->curPsTdma)); + } + + if( pCoexDm->curPsTdma != 1 && + pCoexDm->curPsTdma != 2 && + pCoexDm->curPsTdma != 9 && + pCoexDm->curPsTdma != 11 ) + { + // recover to previous adjust type + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, pCoexDm->psTdmaDuAdjType); + } + } +} + +VOID +halbtc8821a1ant_PsTdmaCheckForPowerSaveState( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bNewPsState + ) +{ + u1Byte lpsMode=0x0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_LPS_MODE, &lpsMode); + + if(lpsMode) // already under LPS state + { + if(bNewPsState) + { + // keep state under LPS, do nothing. + } + else + { + // will leave LPS state, turn off psTdma first + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + } + } + else // NO PS state + { + if(bNewPsState) + { + // will enter LPS state, turn off psTdma first + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + } + else + { + // keep state under NO PS state, do nothing. + } + } +} + +VOID +halbtc8821a1ant_PowerSaveState( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte psType, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + BOOLEAN bLowPwrDisable=FALSE; + + switch(psType) + { + case BTC_PS_WIFI_NATIVE: + // recover to original 32k low power setting + bLowPwrDisable = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_NORMAL_LPS, NULL); + break; + case BTC_PS_LPS_ON: + halbtc8821a1ant_PsTdmaCheckForPowerSaveState(pBtCoexist, TRUE); + halbtc8821a1ant_LpsRpwm(pBtCoexist, NORMAL_EXEC, lpsVal, rpwmVal); + // when coex force to enter LPS, do not enter 32k low power. + bLowPwrDisable = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + // power save must executed before psTdma. + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_ENTER_LPS, NULL); + break; + case BTC_PS_LPS_OFF: + halbtc8821a1ant_PsTdmaCheckForPowerSaveState(pBtCoexist, FALSE); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_LEAVE_LPS, NULL); + break; + default: + break; + } +} + +VOID +halbtc8821a1ant_CoexUnder5G( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8821a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + halbtc8821a1ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, TRUE); + + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 10); + + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8821a1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + + halbtc8821a1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 5); +} + +VOID +halbtc8821a1ant_ActionWifiOnly( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 9); +} + +VOID +halbtc8821a1ant_MonitorBtEnableDisable( + IN PBTC_COEXIST pBtCoexist + ) +{ + static BOOLEAN bPreBtDisabled=FALSE; + static u4Byte btDisableCnt=0; + BOOLEAN bBtActive=TRUE, bBtDisabled=FALSE; + + // This function check if bt is disabled + + if( pCoexSta->highPriorityTx == 0 && + pCoexSta->highPriorityRx == 0 && + pCoexSta->lowPriorityTx == 0 && + pCoexSta->lowPriorityRx == 0) + { + bBtActive = FALSE; + } + if( pCoexSta->highPriorityTx == 0xffff && + pCoexSta->highPriorityRx == 0xffff && + pCoexSta->lowPriorityTx == 0xffff && + pCoexSta->lowPriorityRx == 0xffff) + { + bBtActive = FALSE; + } + if(bBtActive) + { + btDisableCnt = 0; + bBtDisabled = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is enabled !!\n")); + } + else + { + btDisableCnt++; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], bt all counters=0, %d times!!\n", + btDisableCnt)); + if(btDisableCnt >= 2) + { + bBtDisabled = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is disabled !!\n")); + halbtc8821a1ant_ActionWifiOnly(pBtCoexist); + } + } + if(bPreBtDisabled != bBtDisabled) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is from %s to %s!!\n", + (bPreBtDisabled ? "disabled":"enabled"), + (bBtDisabled ? "disabled":"enabled"))); + bPreBtDisabled = bBtDisabled; + if(!bBtDisabled) + { + } + else + { + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_LEAVE_LPS, NULL); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_NORMAL_LPS, NULL); + } + } +} + +//============================================= +// +// Software Coex Mechanism start +// +//============================================= + +// SCO only or SCO+PAN(HS) +VOID +halbtc8821a1ant_ActionSco( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8821a1ant_SwMechanism(pBtCoexist, TRUE); +} + +VOID +halbtc8821a1ant_ActionHid( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8821a1ant_SwMechanism(pBtCoexist, TRUE); +} + +//A2DP only / PAN(EDR) only/ A2DP+PAN(HS) +VOID +halbtc8821a1ant_ActionA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8821a1ant_SwMechanism(pBtCoexist, FALSE); +} + +VOID +halbtc8821a1ant_ActionA2dpPanHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8821a1ant_SwMechanism(pBtCoexist, FALSE); +} + +VOID +halbtc8821a1ant_ActionPanEdr( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8821a1ant_SwMechanism(pBtCoexist, FALSE); +} + +//PAN(HS) only +VOID +halbtc8821a1ant_ActionPanHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8821a1ant_SwMechanism(pBtCoexist, FALSE); +} + +//PAN(EDR)+A2DP +VOID +halbtc8821a1ant_ActionPanEdrA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8821a1ant_SwMechanism(pBtCoexist, FALSE); +} + +VOID +halbtc8821a1ant_ActionPanEdrHid( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8821a1ant_SwMechanism(pBtCoexist, TRUE); +} + +// HID+A2DP+PAN(EDR) +VOID +halbtc8821a1ant_ActionHidA2dpPanEdr( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8821a1ant_SwMechanism(pBtCoexist, TRUE); +} + +VOID +halbtc8821a1ant_ActionHidA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8821a1ant_SwMechanism(pBtCoexist, TRUE); +} + +//============================================= +// +// Non-Software Coex Mechanism start +// +//============================================= +VOID +halbtc8821a1ant_ActionWifiMultiPort( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8821a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); +} + +VOID +halbtc8821a1ant_ActionHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); +} + +VOID +halbtc8821a1ant_ActionBtInquiry( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bWifiConnected=FALSE, bApEnable=FALSE, bWifiBusy=FALSE, bBtBusy=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bBtBusy); + + if((!bWifiConnected) && (!pCoexSta->bWiFiIsHighPriTask)) + { + halbtc8821a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + } + else if((pBtLinkInfo->bScoExist) || (pBtLinkInfo->bHidExist) || (pBtLinkInfo->bA2dpExist)) + { + // SCO/HID/A2DP busy + halbtc8821a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else if ((pBtLinkInfo->bPanExist) || (bWifiBusy)) + { + halbtc8821a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 20); + + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else + { + halbtc8821a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } +} + +VOID +halbtc8821a1ant_ActionBtScoHidOnlyBusy( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte wifiStatus + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bWifiConnected=FALSE; + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + + // tdma and coex table + + if(pBtLinkInfo->bScoExist) + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + } + else //HID + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 5); + } +} + +VOID +halbtc8821a1ant_ActionWifiConnectedBtAclBusy( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte wifiStatus + ) +{ + u1Byte btRssiState; + + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + btRssiState = halbtc8821a1ant_BtRssiState(2, 28, 0); + + if(pBtLinkInfo->bHidOnly) //HID + { + halbtc8821a1ant_ActionBtScoHidOnlyBusy(pBtCoexist, wifiStatus); + pCoexDm->bAutoTdmaAdjust = FALSE; + return; + } + else if(pBtLinkInfo->bA2dpOnly) //A2DP + { + if(BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE == wifiStatus) + { + //halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + //halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 1); + pCoexDm->bAutoTdmaAdjust = FALSE; + } + else if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821a1ant_TdmaDurationAdjustForAcl(pBtCoexist, wifiStatus); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 1); + } + else //for low BT RSSI + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 1); + pCoexDm->bAutoTdmaAdjust = FALSE; + } + } + else if(pBtLinkInfo->bHidExist&&pBtLinkInfo->bA2dpExist) //HID+A2DP + { + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->bAutoTdmaAdjust = FALSE; + } + else //for low BT RSSI + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->bAutoTdmaAdjust = FALSE; + } + + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 6); + } + else if( (pBtLinkInfo->bPanOnly) || (pBtLinkInfo->bHidExist&&pBtLinkInfo->bPanExist) ) //PAN(OPP,FTP), HID+PAN(OPP,FTP) + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 6); + pCoexDm->bAutoTdmaAdjust = FALSE; + } + else if ( ((pBtLinkInfo->bA2dpExist) && (pBtLinkInfo->bPanExist)) || + (pBtLinkInfo->bHidExist&&pBtLinkInfo->bA2dpExist&&pBtLinkInfo->bPanExist) ) //A2DP+PAN(OPP,FTP), HID+A2DP+PAN(OPP,FTP) + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 1); + pCoexDm->bAutoTdmaAdjust = FALSE; + } + else + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 1); + pCoexDm->bAutoTdmaAdjust = FALSE; + } +} + +VOID +halbtc8821a1ant_ActionWifiNotConnected( + IN PBTC_COEXIST pBtCoexist + ) +{ + // power save state + halbtc8821a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + halbtc8821a1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); +} + +VOID +halbtc8821a1ant_ActionWifiNotConnectedScan( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + + halbtc8821a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + if(BT_8821A_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) + { + if (pBtLinkInfo->bA2dpExist) + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else if (pBtLinkInfo->bA2dpExist && pBtLinkInfo->bPanExist) + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 22); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 20); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + } + else if( (BT_8821A_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + halbtc8821a1ant_ActionBtScoHidOnlyBusy(pBtCoexist, + BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SCAN); + } + else + { + //halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 20); + //halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 1); + + //Bryant Add + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + } +} + +VOID +halbtc8821a1ant_ActionWifiNotConnectedAssoAuth( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + + halbtc8821a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + if( (pBtLinkInfo->bScoExist) || (pBtLinkInfo->bHidExist) ) + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else if( (pBtLinkInfo->bA2dpExist) || (pBtLinkInfo->bPanExist) ) + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 20); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + } +} + +VOID +halbtc8821a1ant_ActionWifiConnectedScan( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + + halbtc8821a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + if(BT_8821A_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) + { + if (pBtLinkInfo->bA2dpExist) + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else if (pBtLinkInfo->bA2dpExist && pBtLinkInfo->bPanExist) + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 22); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 20); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + } + else if( (BT_8821A_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + halbtc8821a1ant_ActionBtScoHidOnlyBusy(pBtCoexist, + BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SCAN); + } + else + { + //halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 20); + //halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 1); + + //Bryant Add + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + } +} + +VOID +halbtc8821a1ant_ActionWifiConnectedSpecialPacket( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + + halbtc8821a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + if((pBtLinkInfo->bScoExist) || (pBtLinkInfo->bHidExist) || (pBtLinkInfo->bA2dpExist)) + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 32); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else if(pBtLinkInfo->bPanExist) + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 20); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 4); + } + else + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + } +} + +VOID +halbtc8821a1ant_ActionWifiConnected( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bWifiBusy=FALSE; + BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE; + BOOLEAN bUnder4way=FALSE, bApEnable=FALSE; + u4Byte wifiBw; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CoexForWifiConnect()===>\n")); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &bUnder4way); + if(bUnder4way) + { + halbtc8821a1ant_ActionWifiConnectedSpecialPacket(pBtCoexist); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CoexForWifiConnect(), return for wifi is under 4way<===\n")); + return; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + if(bScan || bLink || bRoam) + { + if(bScan) + halbtc8821a1ant_ActionWifiConnectedScan(pBtCoexist); + else + halbtc8821a1ant_ActionWifiConnectedSpecialPacket(pBtCoexist); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CoexForWifiConnect(), return for wifi is under scan<===\n")); + return; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_AP_MODE_ENABLE, &bApEnable); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + // power save state + if(!bApEnable && BT_8821A_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus && !pBtCoexist->btLinkInfo.bHidOnly) + { + if(!bWifiBusy && pBtCoexist->btLinkInfo.bA2dpOnly) //A2DP + halbtc8821a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else + halbtc8821a1ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + } + else + halbtc8821a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + // tdma and coex table + if(!bWifiBusy) + { + if(BT_8821A_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) + { + halbtc8821a1ant_ActionWifiConnectedBtAclBusy(pBtCoexist, + BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE); + } + else if( (BT_8821A_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + halbtc8821a1ant_ActionBtScoHidOnlyBusy(pBtCoexist, + BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE); + } + else + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + } + } + else + { + if(BT_8821A_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) + { + halbtc8821a1ant_ActionWifiConnectedBtAclBusy(pBtCoexist, + BT_8821A_1ANT_WIFI_STATUS_CONNECTED_BUSY); + } + else if( (BT_8821A_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + halbtc8821a1ant_ActionBtScoHidOnlyBusy(pBtCoexist, + BT_8821A_1ANT_WIFI_STATUS_CONNECTED_BUSY); + } + else + { + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 8); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + } + } +} + +VOID +halbtc8821a1ant_RunSwCoexistMechanism( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte algorithm=0; + + algorithm = halbtc8821a1ant_ActionAlgorithm(pBtCoexist); + pCoexDm->curAlgorithm = algorithm; + + if(halbtc8821a1ant_IsCommonAction(pBtCoexist)) + { + + } + else + { + switch(pCoexDm->curAlgorithm) + { + case BT_8821A_1ANT_COEX_ALGO_SCO: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = SCO.\n")); + halbtc8821a1ant_ActionSco(pBtCoexist); + break; + case BT_8821A_1ANT_COEX_ALGO_HID: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = HID.\n")); + halbtc8821a1ant_ActionHid(pBtCoexist); + break; + case BT_8821A_1ANT_COEX_ALGO_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = A2DP.\n")); + halbtc8821a1ant_ActionA2dp(pBtCoexist); + break; + case BT_8821A_1ANT_COEX_ALGO_A2DP_PANHS: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = A2DP+PAN(HS).\n")); + halbtc8821a1ant_ActionA2dpPanHs(pBtCoexist); + break; + case BT_8821A_1ANT_COEX_ALGO_PANEDR: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = PAN(EDR).\n")); + halbtc8821a1ant_ActionPanEdr(pBtCoexist); + break; + case BT_8821A_1ANT_COEX_ALGO_PANHS: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = HS mode.\n")); + halbtc8821a1ant_ActionPanHs(pBtCoexist); + break; + case BT_8821A_1ANT_COEX_ALGO_PANEDR_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = PAN+A2DP.\n")); + halbtc8821a1ant_ActionPanEdrA2dp(pBtCoexist); + break; + case BT_8821A_1ANT_COEX_ALGO_PANEDR_HID: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = PAN(EDR)+HID.\n")); + halbtc8821a1ant_ActionPanEdrHid(pBtCoexist); + break; + case BT_8821A_1ANT_COEX_ALGO_HID_A2DP_PANEDR: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = HID+A2DP+PAN.\n")); + halbtc8821a1ant_ActionHidA2dpPanEdr(pBtCoexist); + break; + case BT_8821A_1ANT_COEX_ALGO_HID_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = HID+A2DP.\n")); + halbtc8821a1ant_ActionHidA2dp(pBtCoexist); + break; + default: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action algorithm = coexist All Off!!\n")); + //halbtc8821a1ant_CoexAllOff(pBtCoexist); + break; + } + pCoexDm->preAlgorithm = pCoexDm->curAlgorithm; + } +} + +VOID +halbtc8821a1ant_RunCoexistMechanism( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bWifiConnected=FALSE, bBtHsOn=FALSE; + BOOLEAN bIncreaseScanDevNum=FALSE; + BOOLEAN bBtCtrlAggBufSize=FALSE; + u1Byte aggBufSize=5; + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH; + u4Byte wifiLinkStatus=0; + u4Byte numOfWifiLink=0; + BOOLEAN bWifiUnder5G=FALSE; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism()===>\n")); + + if(pBtCoexist->bManualControl) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n")); + return; + } + + if(pBtCoexist->bStopCoexDm) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism(), return for Stop Coex DM <===\n")); + return; + } + + if(pCoexSta->bUnderIps) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi is under IPS !!!\n")); + return; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_5G, &bWifiUnder5G); + if(bWifiUnder5G) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism(), return for 5G <===\n")); + halbtc8821a1ant_CoexUnder5G(pBtCoexist); + return; + } + + if( (BT_8821A_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) || + (BT_8821A_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + bIncreaseScanDevNum = TRUE; + } + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_INC_SCAN_DEV_NUM, &bIncreaseScanDevNum); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_LINK_STATUS, &wifiLinkStatus); + numOfWifiLink = wifiLinkStatus>>16; + if((numOfWifiLink>=2) || (wifiLinkStatus&WIFI_P2P_GO_CONNECTED)) + { + halbtc8821a1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8821a1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, bBtCtrlAggBufSize, aggBufSize); + halbtc8821a1ant_ActionWifiMultiPort(pBtCoexist); + return; + } + + if(!pBtLinkInfo->bScoExist && !pBtLinkInfo->bHidExist) + { + halbtc8821a1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + } + else + { + if(bWifiConnected) + { + wifiRssiState = halbtc8821a1ant_WifiRssiState(pBtCoexist, 1, 2, 30, 0); + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821a1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 1, 1, 1, 1); + } + else + { + halbtc8821a1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 1, 1, 1, 1); + } + } + else + { + halbtc8821a1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + } + + } + + if(pBtLinkInfo->bScoExist) + { + bBtCtrlAggBufSize = TRUE; + aggBufSize = 0x3; + } + else if(pBtLinkInfo->bHidExist) + { + bBtCtrlAggBufSize = TRUE; + aggBufSize = 0x5; + } + else if(pBtLinkInfo->bA2dpExist || pBtLinkInfo->bPanExist) + { + bBtCtrlAggBufSize = TRUE; + aggBufSize = 0x8; + } + halbtc8821a1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, bBtCtrlAggBufSize, aggBufSize); + + halbtc8821a1ant_RunSwCoexistMechanism(pBtCoexist); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + if(pCoexSta->bC2hBtInquiryPage) + { + halbtc8821a1ant_ActionBtInquiry(pBtCoexist); + return; + } + else if(bBtHsOn) + { + halbtc8821a1ant_ActionHs(pBtCoexist); + return; + } + + + if(!bWifiConnected) + { + BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi is non connected-idle !!!\n")); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + + if(bScan || bLink || bRoam) + { + if (bScan) + halbtc8821a1ant_ActionWifiNotConnectedScan(pBtCoexist); + else + halbtc8821a1ant_ActionWifiNotConnectedAssoAuth(pBtCoexist); + } + else + halbtc8821a1ant_ActionWifiNotConnected(pBtCoexist); + } + else // wifi LPS/Busy + { + halbtc8821a1ant_ActionWifiConnected(pBtCoexist); + } +} + +VOID +halbtc8821a1ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + // force to reset coex mechanism + // sw all off + halbtc8821a1ant_SwMechanism(pBtCoexist, FALSE); + + //halbtc8821a1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 0); +} + +VOID +halbtc8821a1ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bBackUp, + IN BOOLEAN bWifiOnly + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + u4Byte u4Tmp=0; + u2Byte u2Tmp=0; + u1Byte u1Tmp=0; + u1Byte H2C_Parameter[2] ={0}; + BOOLEAN bWifiUnder5G=FALSE; + + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 1Ant Init HW Config!!\n")); + + if(bWifiOnly) + return; + + if(bBackUp) + { + pCoexDm->backupArfrCnt1 = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x430); + pCoexDm->backupArfrCnt2 = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x434); + pCoexDm->backupRetryLimit = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0x42a); + pCoexDm->backupAmpduMaxTime = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x456); + } + + // 0x790[5:0]=0x5 + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x790); + u1Tmp &= 0xc0; + u1Tmp |= 0x5; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x790, u1Tmp); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_5G, &bWifiUnder5G); + + //Antenna config + if(bWifiUnder5G) + halbtc8821a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, TRUE, FALSE); + else + halbtc8821a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_PTA, TRUE, FALSE); + + // PTA parameter + halbtc8821a1ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 0); + + // Enable counter statistics + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0xc); //0x76e[3] =1, WLAN_Act control by PTA + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x778, 0x3); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x40, 0x20, 0x1); +} + +//============================================================ +// work around function start with wa_halbtc8821a1ant_ +//============================================================ +//============================================================ +// extern function start with EXhalbtc8821a1ant_ +//============================================================ +VOID +EXhalbtc8821a1ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ) +{ +} + +VOID +EXhalbtc8821a1ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ) +{ + halbtc8821a1ant_InitHwConfig(pBtCoexist, TRUE, bWifiOnly); +} + +VOID +EXhalbtc8821a1ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Coex Mechanism Init!!\n")); + + pBtCoexist->bStopCoexDm = FALSE; + + halbtc8821a1ant_InitCoexDm(pBtCoexist); + + halbtc8821a1ant_QueryBtInfo(pBtCoexist); +} + +VOID +EXhalbtc8821a1ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + pu1Byte cliBuf=pBtCoexist->cliBuf; + u1Byte u1Tmp[4], i, btInfoExt, psTdmaCase=0; + u2Byte u2Tmp[4]; + u4Byte u4Tmp[4]; + u4Byte faOfdm, faCck; + u4Byte fwVer=0, btPatchVer=0; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cliBuf); + + if(pBtCoexist->bManualControl) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[Under Manual Control]============"); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n =========================================="); + CL_PRINTF(cliBuf); + } + if(pBtCoexist->bStopCoexDm) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[Coex is STOPPED]============"); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n =========================================="); + CL_PRINTF(cliBuf); + } + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", "Ant PG Num/ Ant Mech/ Ant Pos:", \ + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum, pBoardInfo->btdmAntPos); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \ + ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion); + CL_PRINTF(cliBuf); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_BT_PATCH_VER, &btPatchVer); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)", "CoexVer/ FwVer/ PatchVer", \ + GLCoexVerDate8821a1Ant, GLCoexVer8821a1Ant, fwVer, btPatchVer, btPatchVer); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", "Wifi channel informed to BT", \ + pCoexDm->wifiChnlInfo[0], pCoexDm->wifiChnlInfo[1], + pCoexDm->wifiChnlInfo[2]); + CL_PRINTF(cliBuf); + + // wifi status + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Wifi Status]============"); + CL_PRINTF(cliBuf); + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[BT Status]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", "BT [status/ rssi/ retryCnt]", \ + ((pBtCoexist->btInfo.bBtDisabled)? ("disabled"): ((pCoexSta->bC2hBtInquiryPage)?("inquiry/page scan"):((BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus)? "non-connected idle": + ( (BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus)? "connected-idle":"busy")))), + pCoexSta->btRssi, pCoexSta->btRetryCnt); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP", \ + pBtLinkInfo->bScoExist, pBtLinkInfo->bHidExist, pBtLinkInfo->bPanExist, pBtLinkInfo->bA2dpExist); + CL_PRINTF(cliBuf); + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO); + + btInfoExt = pCoexSta->btInfoExt; + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Info A2DP rate", \ + (btInfoExt&BIT0)? "Basic rate":"EDR rate"); + CL_PRINTF(cliBuf); + + for(i=0; ibtInfoC2hCnt[i]) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", GLBtInfoSrc8821a1Ant[i], \ + pCoexSta->btInfoC2h[i][0], pCoexSta->btInfoC2h[i][1], + pCoexSta->btInfoC2h[i][2], pCoexSta->btInfoC2h[i][3], + pCoexSta->btInfoC2h[i][4], pCoexSta->btInfoC2h[i][5], + pCoexSta->btInfoC2h[i][6], pCoexSta->btInfoC2hCnt[i]); + CL_PRINTF(cliBuf); + } + } + + if(!pBtCoexist->bManualControl) + { + // Sw mechanism + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "SM[LowPenaltyRA]", \ + pCoexDm->bCurLowPenaltyRa); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %d ", "DelBA/ BtCtrlAgg/ AggSize", \ + (pBtCoexist->btInfo.bRejectAggPkt? "Yes":"No"), (pBtCoexist->btInfo.bBtCtrlAggBufSize? "Yes":"No"), + pBtCoexist->btInfo.aggBufSize); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "Rate Mask", \ + pBtCoexist->btInfo.raMask); + CL_PRINTF(cliBuf); + + // Fw mechanism + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============"); + CL_PRINTF(cliBuf); + + psTdmaCase = pCoexDm->curPsTdma; + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)", "PS TDMA", \ + pCoexDm->psTdmaPara[0], pCoexDm->psTdmaPara[1], + pCoexDm->psTdmaPara[2], pCoexDm->psTdmaPara[3], + pCoexDm->psTdmaPara[4], psTdmaCase, pCoexDm->bAutoTdmaAdjust); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d ", "IgnWlanAct", \ + pCoexDm->bCurIgnoreWlanAct); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x ", "Latest error condition(should be 0)", \ + pCoexDm->errorCondition); + CL_PRINTF(cliBuf); + } + + // Hw setting + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", "backup ARFR1/ARFR2/RL/AMaxTime", \ + pCoexDm->backupArfrCnt1, pCoexDm->backupArfrCnt2, pCoexDm->backupRetryLimit, pCoexDm->backupAmpduMaxTime); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x430); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x434); + u2Tmp[0] = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0x42a); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x456); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/0x%x/0x%x/0x%x", "0x430/0x434/0x42a/0x456", \ + u4Tmp[0], u4Tmp[1], u2Tmp[0], u1Tmp[0]); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x778); + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc58); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x778/ 0xc58[29:25]", \ + u1Tmp[0], (u4Tmp[0]&0x3e000000) >> 25); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x8db); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x8db[6:5]", \ + ((u1Tmp[0]&0x60)>>5)); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x975); + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xcb4); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0xcb4[29:28]/0xcb4[7:0]/0x974[9:8]", \ + (u4Tmp[0]&0x30000000)>>28, u4Tmp[0]&0xff, u1Tmp[0]& 0x3); + CL_PRINTF(cliBuf); + + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x40); + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x4c); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x64); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x40/0x4c[24:23]/0x64[0]", \ + u1Tmp[0], ((u4Tmp[0]&0x01800000)>>23), u1Tmp[1]&0x1); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x550); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x522); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x550(bcn ctrl)/0x522", \ + u4Tmp[0], u1Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc50); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0xc50(dig)", \ + u4Tmp[0]&0xff); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xf48); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xa5d); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xa5c); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "OFDM-FA/ CCK-FA", \ + u4Tmp[0], (u1Tmp[0]<<8) + u1Tmp[1] ); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c0); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c4); + u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c8); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x6c0/0x6c4/0x6c8(coexTable)", \ + u4Tmp[0], u4Tmp[1], u4Tmp[2]); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x770(high-pri rx/tx)", \ + pCoexSta->highPriorityRx, pCoexSta->highPriorityTx); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x774(low-pri rx/tx)", \ + pCoexSta->lowPriorityRx, pCoexSta->lowPriorityTx); + CL_PRINTF(cliBuf); +#if(BT_AUTO_REPORT_ONLY_8821A_1ANT == 1) + halbtc8821a1ant_MonitorBtCtr(pBtCoexist); +#endif + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + + +VOID +EXhalbtc8821a1ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + u4Byte u4Tmp=0; + + if(pBtCoexist->bManualControl || pBtCoexist->bStopCoexDm) + return; + + if(BTC_IPS_ENTER == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS ENTER notify\n")); + pCoexSta->bUnderIps = TRUE; + + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + halbtc8821a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FALSE, TRUE); + //halbtc8821a1ant_SetAntPathDCut(pBtCoexist, FALSE, FALSE, FALSE, BTC_ANT_PATH_BT, BTC_WIFI_STAT_NORMAL_OFF); + } + else if(BTC_IPS_LEAVE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS LEAVE notify\n")); + pCoexSta->bUnderIps = FALSE; + + halbtc8821a1ant_InitHwConfig(pBtCoexist, FALSE, FALSE); + halbtc8821a1ant_InitCoexDm(pBtCoexist); + halbtc8821a1ant_QueryBtInfo(pBtCoexist); + } +} + +VOID +EXhalbtc8821a1ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(pBtCoexist->bManualControl || pBtCoexist->bStopCoexDm) + return; + + if(BTC_LPS_ENABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS ENABLE notify\n")); + pCoexSta->bUnderLps = TRUE; + } + else if(BTC_LPS_DISABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS DISABLE notify\n")); + pCoexSta->bUnderLps = FALSE; + } +} + +VOID +EXhalbtc8821a1ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + BOOLEAN bWifiConnected=FALSE, bBtHsOn=FALSE; + u4Byte wifiLinkStatus=0; + u4Byte numOfWifiLink=0; + BOOLEAN bBtCtrlAggBufSize=FALSE; + u1Byte aggBufSize=5; + + if(pBtCoexist->bManualControl || + pBtCoexist->bStopCoexDm ) + return; + + if(BTC_SCAN_START == type) + { + pCoexSta->bWiFiIsHighPriTask = TRUE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n")); + + halbtc8821a1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 8); //Force antenna setup for no scan result issue + } + else + { + pCoexSta->bWiFiIsHighPriTask = FALSE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n")); + } + + if(pBtCoexist->btInfo.bBtDisabled) + return; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + + halbtc8821a1ant_QueryBtInfo(pBtCoexist); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_LINK_STATUS, &wifiLinkStatus); + numOfWifiLink = wifiLinkStatus>>16; + if(numOfWifiLink >= 2) + { + halbtc8821a1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8821a1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, bBtCtrlAggBufSize, aggBufSize); + halbtc8821a1ant_ActionWifiMultiPort(pBtCoexist); + return; + } + + if(pCoexSta->bC2hBtInquiryPage) + { + halbtc8821a1ant_ActionBtInquiry(pBtCoexist); + return; + } + else if(bBtHsOn) + { + halbtc8821a1ant_ActionHs(pBtCoexist); + return; + } + + if(BTC_SCAN_START == type) + { + //RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n")); + if(!bWifiConnected) // non-connected scan + { + halbtc8821a1ant_ActionWifiNotConnectedScan(pBtCoexist); + } + else // wifi is connected + { + halbtc8821a1ant_ActionWifiConnectedScan(pBtCoexist); + } + } + else if(BTC_SCAN_FINISH == type) + { + //RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n")); + if(!bWifiConnected) // non-connected scan + { + halbtc8821a1ant_ActionWifiNotConnected(pBtCoexist); + } + else + { + halbtc8821a1ant_ActionWifiConnected(pBtCoexist); + } + } +} + +VOID +EXhalbtc8821a1ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + BOOLEAN bWifiConnected=FALSE, bBtHsOn=FALSE; + u4Byte wifiLinkStatus=0; + u4Byte numOfWifiLink=0; + BOOLEAN bBtCtrlAggBufSize=FALSE; + u1Byte aggBufSize=5; + + if(pBtCoexist->bManualControl || + pBtCoexist->bStopCoexDm || + pBtCoexist->btInfo.bBtDisabled ) + return; + + if(BTC_ASSOCIATE_START == type) + { + pCoexSta->bWiFiIsHighPriTask = TRUE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n")); + pCoexDm->nArpCnt = 0; + } + else + { + pCoexSta->bWiFiIsHighPriTask = FALSE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n")); + pCoexDm->nArpCnt = 0; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_LINK_STATUS, &wifiLinkStatus); + numOfWifiLink = wifiLinkStatus>>16; + if(numOfWifiLink >= 2) + { + halbtc8821a1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8821a1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, bBtCtrlAggBufSize, aggBufSize); + halbtc8821a1ant_ActionWifiMultiPort(pBtCoexist); + return; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + if(pCoexSta->bC2hBtInquiryPage) + { + halbtc8821a1ant_ActionBtInquiry(pBtCoexist); + return; + } + else if(bBtHsOn) + { + halbtc8821a1ant_ActionHs(pBtCoexist); + return; + } + + if(BTC_ASSOCIATE_START == type) + { + //RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n")); + halbtc8821a1ant_ActionWifiNotConnectedAssoAuth(pBtCoexist); + } + else if(BTC_ASSOCIATE_FINISH == type) + { + //RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n")); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + if(!bWifiConnected) // non-connected scan + { + halbtc8821a1ant_ActionWifiNotConnected(pBtCoexist); + } + else + { + halbtc8821a1ant_ActionWifiConnected(pBtCoexist); + } + } +} + +VOID +EXhalbtc8821a1ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + u1Byte H2C_Parameter[3] ={0}; + u4Byte wifiBw; + u1Byte wifiCentralChnl; + + if(pBtCoexist->bManualControl || + pBtCoexist->bStopCoexDm || + pBtCoexist->btInfo.bBtDisabled ) + return; + + if(BTC_MEDIA_CONNECT == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA connect notify\n")); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA disconnect notify\n")); + pCoexDm->nArpCnt = 0; + } + + // only 2.4G we need to inform bt the chnl mask + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, &wifiCentralChnl); + if( (BTC_MEDIA_CONNECT == type) && + (wifiCentralChnl <= 14) ) + { + //H2C_Parameter[0] = 0x1; + H2C_Parameter[0] = 0x0; + H2C_Parameter[1] = wifiCentralChnl; + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + H2C_Parameter[2] = 0x30; + else + H2C_Parameter[2] = 0x20; + } + + pCoexDm->wifiChnlInfo[0] = H2C_Parameter[0]; + pCoexDm->wifiChnlInfo[1] = H2C_Parameter[1]; + pCoexDm->wifiChnlInfo[2] = H2C_Parameter[2]; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x66=0x%x\n", + H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x66, 3, H2C_Parameter); +} + +VOID +EXhalbtc8821a1ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + BOOLEAN bBtHsOn=FALSE; + u4Byte wifiLinkStatus=0; + u4Byte numOfWifiLink=0; + BOOLEAN bBtCtrlAggBufSize=FALSE; + u1Byte aggBufSize=5; + + if(pBtCoexist->bManualControl || + pBtCoexist->bStopCoexDm || + pBtCoexist->btInfo.bBtDisabled ) + return; + + if( BTC_PACKET_DHCP == type || + BTC_PACKET_EAPOL == type || + BTC_PACKET_ARP == type ) + { + pCoexSta->bWiFiIsHighPriTask = TRUE; + + if(BTC_PACKET_ARP == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], special Packet ARP notify\n")); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], special Packet DHCP or EAPOL notify\n")); + } + } + else + { + pCoexSta->bWiFiIsHighPriTask = FALSE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], special Packet [Type = %d] notify\n", type)); + } + + pCoexSta->specialPktPeriodCnt = 0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_LINK_STATUS, &wifiLinkStatus); + numOfWifiLink = wifiLinkStatus>>16; + if(numOfWifiLink >= 2) + { + halbtc8821a1ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0); + halbtc8821a1ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, bBtCtrlAggBufSize, aggBufSize); + halbtc8821a1ant_ActionWifiMultiPort(pBtCoexist); + return; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + if(pCoexSta->bC2hBtInquiryPage) + { + halbtc8821a1ant_ActionBtInquiry(pBtCoexist); + return; + } + else if(bBtHsOn) + { + halbtc8821a1ant_ActionHs(pBtCoexist); + return; + } + + if( BTC_PACKET_DHCP == type || + BTC_PACKET_EAPOL == type || + BTC_PACKET_ARP == type ) + { + //RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], special Packet(%d) notify\n", type)); + if(BTC_PACKET_ARP == type) + { + pCoexDm->nArpCnt++; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ARP Packet Count = %d\n", pCoexDm->nArpCnt)); + if(pCoexDm->nArpCnt >= 10) // if APR PKT > 10 after connect, do not go to ActionWifiConnectedSpecialPacket(pBtCoexist) + return; + } + + halbtc8821a1ant_ActionWifiConnectedSpecialPacket(pBtCoexist); + } +} + +VOID +EXhalbtc8821a1ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + u1Byte btInfo=0; + u1Byte i, rspSource=0; + BOOLEAN bWifiConnected=FALSE; + BOOLEAN bBtBusy=FALSE; + BOOLEAN bWifiUnder5G=FALSE; + + pCoexSta->bC2hBtInfoReqSent = FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_5G, &bWifiUnder5G); + + rspSource = tmpBuf[0]&0xf; + if(rspSource >= BT_INFO_SRC_8821A_1ANT_MAX) + rspSource = BT_INFO_SRC_8821A_1ANT_WIFI_FW; + pCoexSta->btInfoC2hCnt[rspSource]++; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Bt info[%d], length=%d, hex data=[", rspSource, length)); + for(i=0; ibtInfoC2h[rspSource][i] = tmpBuf[i]; + if(i == 1) + btInfo = tmpBuf[i]; + if(i == length-1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x]\n", tmpBuf[i])); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x, ", tmpBuf[i])); + } + } + + if(BT_INFO_SRC_8821A_1ANT_WIFI_FW != rspSource) + { + pCoexSta->btRetryCnt = // [3:0] + pCoexSta->btInfoC2h[rspSource][2]&0xf; + + if (pCoexSta->btInfoC2h[rspSource][2]&0x20) + pCoexSta->bC2hBtPage = TRUE; + else + pCoexSta->bC2hBtPage = FALSE; + + pCoexSta->btRssi = + pCoexSta->btInfoC2h[rspSource][3]*2+10; + + pCoexSta->btInfoExt = + pCoexSta->btInfoC2h[rspSource][4]; + + pCoexSta->bBtTxRxMask = (pCoexSta->btInfoC2h[rspSource][2]&0x40); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TX_RX_MASK, &pCoexSta->bBtTxRxMask); + if(!pCoexSta->bBtTxRxMask) + { + /* BT into is responded by BT FW and BT RF REG 0x3C != 0x15 => Need to switch BT TRx Mask */ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x15\n")); + pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x3c, 0x15); + } + + // Here we need to resend some wifi info to BT + // because bt is reset and loss of the info. + if(pCoexSta->btInfoExt & BIT1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n")); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + if(bWifiConnected) + { + EXhalbtc8821a1ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_CONNECT); + } + else + { + EXhalbtc8821a1ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); + } + } + + if( (pCoexSta->btInfoExt & BIT3) && !bWifiUnder5G) + { + if(!pBtCoexist->bManualControl && !pBtCoexist->bStopCoexDm) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n")); + halbtc8821a1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE); + } + } + else + { + // BT already NOT ignore Wlan active, do nothing here. + } +#if(BT_AUTO_REPORT_ONLY_8821A_1ANT == 0) + if( (pCoexSta->btInfoExt & BIT4) ) + { + // BT auto report already enabled, do nothing + } + else + { + halbtc8821a1ant_BtAutoReport(pBtCoexist, FORCE_EXEC, TRUE); + } +#endif + } + + // check BIT2 first ==> check if bt is under inquiry or page scan + if(btInfo & BT_INFO_8821A_1ANT_B_INQ_PAGE) + pCoexSta->bC2hBtInquiryPage = TRUE; + else + pCoexSta->bC2hBtInquiryPage = FALSE; + + // set link exist status + if(!(btInfo&BT_INFO_8821A_1ANT_B_CONNECTION)) + { + pCoexSta->bBtLinkExist = FALSE; + pCoexSta->bPanExist = FALSE; + pCoexSta->bA2dpExist = FALSE; + pCoexSta->bHidExist = FALSE; + pCoexSta->bScoExist = FALSE; + } + else // connection exists + { + pCoexSta->bBtLinkExist = TRUE; + if(btInfo & BT_INFO_8821A_1ANT_B_FTP) + pCoexSta->bPanExist = TRUE; + else + pCoexSta->bPanExist = FALSE; + if(btInfo & BT_INFO_8821A_1ANT_B_A2DP) + pCoexSta->bA2dpExist = TRUE; + else + pCoexSta->bA2dpExist = FALSE; + if(btInfo & BT_INFO_8821A_1ANT_B_HID) + pCoexSta->bHidExist = TRUE; + else + pCoexSta->bHidExist = FALSE; + if(btInfo & BT_INFO_8821A_1ANT_B_SCO_ESCO) + pCoexSta->bScoExist = TRUE; + else + pCoexSta->bScoExist = FALSE; + } + + halbtc8821a1ant_UpdateBtLinkInfo(pBtCoexist); + + btInfo = btInfo & 0x1f; //mask profile bit for connect-ilde identification ( for CSR case: A2DP idle --> 0x41) + + if(!(btInfo&BT_INFO_8821A_1ANT_B_CONNECTION)) + { + pCoexDm->btStatus = BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n")); + } + else if(btInfo == BT_INFO_8821A_1ANT_B_CONNECTION) // connection exists but no busy + { + pCoexDm->btStatus = BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n")); + } + else if((btInfo&BT_INFO_8821A_1ANT_B_SCO_ESCO) || + (btInfo&BT_INFO_8821A_1ANT_B_SCO_BUSY)) + { + pCoexDm->btStatus = BT_8821A_1ANT_BT_STATUS_SCO_BUSY; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT SCO busy!!!\n")); + } + else if(btInfo&BT_INFO_8821A_1ANT_B_ACL_BUSY) + { + if(BT_8821A_1ANT_BT_STATUS_ACL_BUSY != pCoexDm->btStatus) + pCoexDm->bAutoTdmaAdjust = FALSE; + pCoexDm->btStatus = BT_8821A_1ANT_BT_STATUS_ACL_BUSY; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT ACL busy!!!\n")); + } + else + { + pCoexDm->btStatus = BT_8821A_1ANT_BT_STATUS_MAX; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n")); + } + + if( (BT_8821A_1ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) || + (BT_8821A_1ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + bBtBusy = TRUE; + else + bBtBusy = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bBtBusy); + + halbtc8821a1ant_RunCoexistMechanism(pBtCoexist); +} + +VOID +EXhalbtc8821a1ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte u4Tmp; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Halt notify\n")); + + halbtc8821a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8821a1ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 0); + halbtc8821a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FALSE, TRUE); + //halbtc8821a1ant_SetAntPathDCut(pBtCoexist, FALSE, FALSE, FALSE, BTC_ANT_PATH_BT, BTC_WIFI_STAT_NORMAL_OFF); + + halbtc8821a1ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE); + + EXhalbtc8821a1ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); + + pBtCoexist->bStopCoexDm = TRUE; +} + +VOID +EXhalbtc8821a1ant_PnpNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte pnpState + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Pnp notify\n")); + + if(BTC_WIFI_PNP_SLEEP == pnpState) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Pnp notify to SLEEP\n")); + + halbtc8821a1ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8821a1ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + halbtc8821a1ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + halbtc8821a1ant_SetAntPath(pBtCoexist, BTC_ANT_PATH_BT, FALSE, TRUE); + //halbtc8821a1ant_SetAntPathDCut(pBtCoexist, FALSE, FALSE, FALSE, BTC_ANT_PATH_BT, BTC_WIFI_STAT_NORMAL_OFF); + + pBtCoexist->bStopCoexDm = TRUE; + } + else if(BTC_WIFI_PNP_WAKE_UP == pnpState) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Pnp notify to WAKE UP\n")); + pBtCoexist->bStopCoexDm = FALSE; + halbtc8821a1ant_InitHwConfig(pBtCoexist, FALSE, FALSE); + halbtc8821a1ant_InitCoexDm(pBtCoexist); + halbtc8821a1ant_QueryBtInfo(pBtCoexist); + } +} + +VOID +EXhalbtc8821a1ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ) +{ + static u1Byte disVerInfoCnt=0; + u4Byte fwVer=0, btPatchVer=0; + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ==========================Periodical===========================\n")); + + if(disVerInfoCnt <= 5) + { + disVerInfoCnt += 1; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ****************************************************************\n")); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Ant PG Num/ Ant Mech/ Ant Pos = %d/ %d/ %d\n", + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum, pBoardInfo->btdmAntPos)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT stack/ hci ext ver = %s / %d\n", + ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion)); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_BT_PATCH_VER, &btPatchVer); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CoexVer/ FwVer/ PatchVer = %d_%x/ 0x%x/ 0x%x(%d)\n", + GLCoexVerDate8821a1Ant, GLCoexVer8821a1Ant, fwVer, btPatchVer, btPatchVer)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ****************************************************************\n")); + } + +#if(BT_AUTO_REPORT_ONLY_8821A_1ANT == 0) + halbtc8821a1ant_QueryBtInfo(pBtCoexist); + halbtc8821a1ant_MonitorBtCtr(pBtCoexist); + halbtc8821a1ant_MonitorBtEnableDisable(pBtCoexist); +#else + if( halbtc8821a1ant_IsWifiStatusChanged(pBtCoexist) || + pCoexDm->bAutoTdmaAdjust ) + { + //if(pCoexSta->specialPktPeriodCnt > 2) + //{ + halbtc8821a1ant_RunCoexistMechanism(pBtCoexist); + //} + } + + pCoexSta->specialPktPeriodCnt++; +#endif +} + + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8821a1Ant.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8821a1Ant.h new file mode 100644 index 000000000..829a81187 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8821a1Ant.h @@ -0,0 +1,214 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//=========================================== +// The following is for 8821A 1ANT BT Co-exist definition +//=========================================== +#define BT_AUTO_REPORT_ONLY_8821A_1ANT 1 + +#define BT_INFO_8821A_1ANT_B_FTP BIT7 +#define BT_INFO_8821A_1ANT_B_A2DP BIT6 +#define BT_INFO_8821A_1ANT_B_HID BIT5 +#define BT_INFO_8821A_1ANT_B_SCO_BUSY BIT4 +#define BT_INFO_8821A_1ANT_B_ACL_BUSY BIT3 +#define BT_INFO_8821A_1ANT_B_INQ_PAGE BIT2 +#define BT_INFO_8821A_1ANT_B_SCO_ESCO BIT1 +#define BT_INFO_8821A_1ANT_B_CONNECTION BIT0 + +#define BT_INFO_8821A_1ANT_A2DP_BASIC_RATE(_BT_INFO_EXT_) \ + (((_BT_INFO_EXT_&BIT0))? TRUE:FALSE) + +#define BTC_RSSI_COEX_THRESH_TOL_8821A_1ANT 2 + +typedef enum _BT_INFO_SRC_8821A_1ANT{ + BT_INFO_SRC_8821A_1ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8821A_1ANT_BT_RSP = 0x1, + BT_INFO_SRC_8821A_1ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8821A_1ANT_MAX +}BT_INFO_SRC_8821A_1ANT,*PBT_INFO_SRC_8821A_1ANT; + +typedef enum _BT_8821A_1ANT_BT_STATUS{ + BT_8821A_1ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8821A_1ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8821A_1ANT_BT_STATUS_INQ_PAGE = 0x2, + BT_8821A_1ANT_BT_STATUS_ACL_BUSY = 0x3, + BT_8821A_1ANT_BT_STATUS_SCO_BUSY = 0x4, + BT_8821A_1ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, + BT_8821A_1ANT_BT_STATUS_MAX +}BT_8821A_1ANT_BT_STATUS,*PBT_8821A_1ANT_BT_STATUS; + +typedef enum _BT_8821A_1ANT_WIFI_STATUS{ + BT_8821A_1ANT_WIFI_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8821A_1ANT_WIFI_STATUS_NON_CONNECTED_ASSO_AUTH_SCAN = 0x1, + BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SCAN = 0x2, + BT_8821A_1ANT_WIFI_STATUS_CONNECTED_SPECIAL_PKT = 0x3, + BT_8821A_1ANT_WIFI_STATUS_CONNECTED_IDLE = 0x4, + BT_8821A_1ANT_WIFI_STATUS_CONNECTED_BUSY = 0x5, + BT_8821A_1ANT_WIFI_STATUS_MAX +}BT_8821A_1ANT_WIFI_STATUS,*PBT_8821A_1ANT_WIFI_STATUS; + +typedef enum _BT_8821A_1ANT_COEX_ALGO{ + BT_8821A_1ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8821A_1ANT_COEX_ALGO_SCO = 0x1, + BT_8821A_1ANT_COEX_ALGO_HID = 0x2, + BT_8821A_1ANT_COEX_ALGO_A2DP = 0x3, + BT_8821A_1ANT_COEX_ALGO_A2DP_PANHS = 0x4, + BT_8821A_1ANT_COEX_ALGO_PANEDR = 0x5, + BT_8821A_1ANT_COEX_ALGO_PANHS = 0x6, + BT_8821A_1ANT_COEX_ALGO_PANEDR_A2DP = 0x7, + BT_8821A_1ANT_COEX_ALGO_PANEDR_HID = 0x8, + BT_8821A_1ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, + BT_8821A_1ANT_COEX_ALGO_HID_A2DP = 0xa, + BT_8821A_1ANT_COEX_ALGO_MAX = 0xb, +}BT_8821A_1ANT_COEX_ALGO,*PBT_8821A_1ANT_COEX_ALGO; + +typedef struct _COEX_DM_8821A_1ANT{ + // fw mechanism + BOOLEAN bCurIgnoreWlanAct; + BOOLEAN bPreIgnoreWlanAct; + u1Byte prePsTdma; + u1Byte curPsTdma; + u1Byte psTdmaPara[5]; + u1Byte psTdmaDuAdjType; + BOOLEAN bAutoTdmaAdjust; + BOOLEAN bPrePsTdmaOn; + BOOLEAN bCurPsTdmaOn; + BOOLEAN bPreBtAutoReport; + BOOLEAN bCurBtAutoReport; + u1Byte preLps; + u1Byte curLps; + u1Byte preRpwm; + u1Byte curRpwm; + + // sw mechanism + BOOLEAN bPreLowPenaltyRa; + BOOLEAN bCurLowPenaltyRa; + u4Byte preVal0x6c0; + u4Byte curVal0x6c0; + u4Byte preVal0x6c4; + u4Byte curVal0x6c4; + u4Byte preVal0x6c8; + u4Byte curVal0x6c8; + u1Byte preVal0x6cc; + u1Byte curVal0x6cc; + + u4Byte backupArfrCnt1; // Auto Rate Fallback Retry cnt + u4Byte backupArfrCnt2; // Auto Rate Fallback Retry cnt + u2Byte backupRetryLimit; + u1Byte backupAmpduMaxTime; + + // algorithm related + u1Byte preAlgorithm; + u1Byte curAlgorithm; + u1Byte btStatus; + u1Byte wifiChnlInfo[3]; + + u4Byte preRaMask; + u4Byte curRaMask; + u1Byte preArfrType; + u1Byte curArfrType; + u1Byte preRetryLimitType; + u1Byte curRetryLimitType; + u1Byte preAmpduTimeType; + u1Byte curAmpduTimeType; + u4Byte nArpCnt; + + u1Byte errorCondition; +} COEX_DM_8821A_1ANT, *PCOEX_DM_8821A_1ANT; + +typedef struct _COEX_STA_8821A_1ANT{ + BOOLEAN bBtLinkExist; + BOOLEAN bScoExist; + BOOLEAN bA2dpExist; + BOOLEAN bHidExist; + BOOLEAN bPanExist; + + BOOLEAN bUnderLps; + BOOLEAN bUnderIps; + u4Byte specialPktPeriodCnt; + u4Byte highPriorityTx; + u4Byte highPriorityRx; + u4Byte lowPriorityTx; + u4Byte lowPriorityRx; + u1Byte btRssi; + BOOLEAN bBtTxRxMask; + u1Byte preBtRssiState; + u1Byte preWifiRssiState[4]; + BOOLEAN bC2hBtInfoReqSent; + u1Byte btInfoC2h[BT_INFO_SRC_8821A_1ANT_MAX][10]; + u4Byte btInfoC2hCnt[BT_INFO_SRC_8821A_1ANT_MAX]; + BOOLEAN bC2hBtInquiryPage; + BOOLEAN bC2hBtPage; //Add for win8.1 page out issue + BOOLEAN bWiFiIsHighPriTask; //Add for win8.1 page out issue + u1Byte btRetryCnt; + u1Byte btInfoExt; +}COEX_STA_8821A_1ANT, *PCOEX_STA_8821A_1ANT; + +//=========================================== +// The following is interface which will notify coex module. +//=========================================== +VOID +EXhalbtc8821a1ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8821a1ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ); +VOID +EXhalbtc8821a1ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8821a1ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8821a1ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8821a1ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8821a1ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8821a1ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8821a1ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8821a1ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ); +VOID +EXhalbtc8821a1ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8821a1ant_PnpNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte pnpState + ); +VOID +EXhalbtc8821a1ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8821a1ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ); + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8821a2Ant.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8821a2Ant.c new file mode 100644 index 000000000..85288a7fd --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8821a2Ant.c @@ -0,0 +1,4859 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//============================================================ +// Description: +// +// This file is for RTL8821A Co-exist mechanism +// +// History +// 2012/11/15 Cosa first check in. +// +//============================================================ + +//============================================================ +// include files +//============================================================ +#include "Mp_Precomp.h" + +#if WPP_SOFTWARE_TRACE +#include "HalBtc8821a2Ant.tmh" +#endif + +#if (RTL8821A_SUPPORT == 1) + +#if(BT_30_SUPPORT == 1) +//============================================================ +// Global variables, these are static variables +//============================================================ +static COEX_DM_8821A_2ANT GLCoexDm8821a2Ant; +static PCOEX_DM_8821A_2ANT pCoexDm=&GLCoexDm8821a2Ant; +static COEX_STA_8821A_2ANT GLCoexSta8821a2Ant; +static PCOEX_STA_8821A_2ANT pCoexSta=&GLCoexSta8821a2Ant; + +const char *const GLBtInfoSrc8821a2Ant[]={ + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; + +u4Byte GLCoexVerDate8821a2Ant=20150921; +u4Byte GLCoexVer8821a2Ant=0x58; +//modify 20140903v43 a2dpandhid tdmaonoff a2dp glitch _ tdma off 778=3(case1)->778=1(case0) +//and to improve tp while a2dphid case23->case25 , case123->case125 for asus spec +//and modify for asus bt WHQL test _ tdma off_ 778=3->1_ +//============================================================ +// local function proto type if needed +//============================================================ +//============================================================ +// local function start with halbtc8821a2ant_ +//============================================================ +u1Byte +halbtc8821a2ant_BtRssiState( + u1Byte levelNum, + u1Byte rssiThresh, + u1Byte rssiThresh1 + ) +{ + s4Byte btRssi=0; + u1Byte btRssiState=pCoexSta->preBtRssiState; + + btRssi = pCoexSta->btRssi; + + if(levelNum == 2) + { + if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW)) + { + if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT)) + { + btRssiState = BTC_RSSI_STATE_HIGH; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else + { + if(btRssi < rssiThresh) + { + btRssiState = BTC_RSSI_STATE_LOW; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + else if(levelNum == 3) + { + if(rssiThresh > rssiThresh1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Rssi thresh error!!\n")); + return pCoexSta->preBtRssiState; + } + + if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW)) + { + if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT)) + { + btRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_MEDIUM) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_MEDIUM)) + { + if(btRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT)) + { + btRssiState = BTC_RSSI_STATE_HIGH; + } + else if(btRssi < rssiThresh) + { + btRssiState = BTC_RSSI_STATE_LOW; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_MEDIUM; + } + } + else + { + if(btRssi < rssiThresh1) + { + btRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + + pCoexSta->preBtRssiState = btRssiState; + + return btRssiState; +} + +u1Byte +halbtc8821a2ant_WifiRssiState( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte index, + IN u1Byte levelNum, + IN u1Byte rssiThresh, + IN u1Byte rssiThresh1 + ) +{ + s4Byte wifiRssi=0; + u1Byte wifiRssiState=pCoexSta->preWifiRssiState[index]; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); + + if(levelNum == 2) + { + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else + { + if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + else if(levelNum == 3) + { + if(rssiThresh > rssiThresh1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi RSSI thresh error!!\n")); + return pCoexSta->preWifiRssiState[index]; + } + + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT)) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_MEDIUM) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_MEDIUM)) + { + if(wifiRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_MEDIUM; + } + } + else + { + if(wifiRssi < rssiThresh1) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + + pCoexSta->preWifiRssiState[index] = wifiRssiState; + + return wifiRssiState; +} + +VOID +halbtc8821a2ant_MonitorBtEnableDisable( + IN PBTC_COEXIST pBtCoexist + ) +{ + static BOOLEAN bPreBtDisabled=FALSE; + static u4Byte btDisableCnt=0; + BOOLEAN bBtActive=TRUE, bBtDisabled=FALSE; + + // This function check if bt is disabled + + if( pCoexSta->highPriorityTx == 0 && + pCoexSta->highPriorityRx == 0 && + pCoexSta->lowPriorityTx == 0 && + pCoexSta->lowPriorityRx == 0) + { + bBtActive = FALSE; + } + if( pCoexSta->highPriorityTx == 0xffff && + pCoexSta->highPriorityRx == 0xffff && + pCoexSta->lowPriorityTx == 0xffff && + pCoexSta->lowPriorityRx == 0xffff) + { + bBtActive = FALSE; + } + if(bBtActive) + { + btDisableCnt = 0; + bBtDisabled = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is enabled !!\n")); + } + else + { + btDisableCnt++; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], bt all counters=0, %d times!!\n", + btDisableCnt)); + if(btDisableCnt >= 2) + { + bBtDisabled = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is disabled !!\n")); + } + } + if(bPreBtDisabled != bBtDisabled) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is from %s to %s!!\n", + (bPreBtDisabled ? "disabled":"enabled"), + (bBtDisabled ? "disabled":"enabled"))); + bPreBtDisabled = bBtDisabled; + if(!bBtDisabled) + { + } + else + { + } + } +} + +VOID +halbtc8821a2ant_LimitedRx( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bRejApAggPkt, + IN BOOLEAN bBtCtrlAggBufSize, + IN u1Byte aggBufSize + ) +{ + BOOLEAN bRejectRxAgg=bRejApAggPkt; + BOOLEAN bBtCtrlRxAggSize=bBtCtrlAggBufSize; + u1Byte rxAggSize=aggBufSize; + + //============================================ + // Rx Aggregation related setting + //============================================ + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, &bRejectRxAgg); + // decide BT control aggregation buf size or not + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, &bBtCtrlRxAggSize); + // aggregation buf size, only work when BT control Rx aggregation size. + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_AGG_BUF_SIZE, &rxAggSize); + // real update aggregation setting + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); +} + +VOID +halbtc8821a2ant_MonitorBtCtr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte regHPTxRx, regLPTxRx, u4Tmp; + u4Byte regHPTx=0, regHPRx=0, regLPTx=0, regLPRx=0; + u1Byte u1Tmp; + + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + + regHPTxRx = 0x770; + regLPTxRx = 0x774; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regHPTxRx); + regHPTx = u4Tmp & bMaskLWord; + regHPRx = (u4Tmp & bMaskHWord)>>16; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regLPTxRx); + regLPTx = u4Tmp & bMaskLWord; + regLPRx = (u4Tmp & bMaskHWord)>>16; + + pCoexSta->highPriorityTx = regHPTx; + pCoexSta->highPriorityRx = regHPRx; + pCoexSta->lowPriorityTx = regLPTx; + pCoexSta->lowPriorityRx = regLPRx; + + if ( (pCoexSta->lowPriorityRx >= 950) && (pCoexSta->lowPriorityRx >= pCoexSta->lowPriorityTx) && (!pCoexSta->bUnderIps) ) + { + pBtLinkInfo->bSlaveRole = TRUE; + } + else + { + pBtLinkInfo->bSlaveRole = FALSE; + } + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", + regHPTxRx, regHPTx, regHPTx, regHPRx, regHPRx)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", + regLPTxRx, regLPTx, regLPTx, regLPRx, regLPRx)); + + // reset counter + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0xc); +} + +VOID +halbtc8821a2ant_MonitorWiFiCtr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte u4Tmp; + u2Byte u2Tmp[3]; + s4Byte wifiRssi=0; + BOOLEAN bWifiBusy = FALSE, bWifiUnderBMode = FALSE; + static u1Byte nCCKLockCounter = 0; + + + if (pCoexSta->bUnderIps) + { + pCoexSta->nCRCOK_CCK = 0; + pCoexSta->nCRCOK_11g = 0; + pCoexSta->nCRCOK_11n = 0; + pCoexSta->nCRCOK_11nAgg = 0; + + pCoexSta->nCRCErr_CCK = 0; + pCoexSta->nCRCErr_11g = 0; + pCoexSta->nCRCErr_11n = 0; + pCoexSta->nCRCErr_11nAgg = 0; + } + else + { + pCoexSta->nCRCOK_CCK = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xf88); + pCoexSta->nCRCOK_11g = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf94); + pCoexSta->nCRCOK_11n = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf90); + pCoexSta->nCRCOK_11nAgg= pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xfb8); + + pCoexSta->nCRCErr_CCK = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xf84); + pCoexSta->nCRCErr_11g = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf96); + pCoexSta->nCRCErr_11n = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xf92); + pCoexSta->nCRCErr_11nAgg = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xfba); + } + + //reset counter + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xf16, 0x1, 0x1); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xf16, 0x1, 0x0); +} + +VOID +halbtc8821a2ant_QueryBtInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + pCoexSta->bC2hBtInfoReqSent = TRUE; + + H2C_Parameter[0] |= BIT0; // trigger + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Query Bt Info, FW write 0x61=0x%x\n", + H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x61, 1, H2C_Parameter); +} + +BOOLEAN +halbtc8821a2ant_IsWifiStatusChanged( + IN PBTC_COEXIST pBtCoexist + ) +{ + static BOOLEAN bPreWifiBusy=FALSE, bPreUnder4way=FALSE, bPreBtHsOn=FALSE; + BOOLEAN bWifiBusy=FALSE, bUnder4way=FALSE, bBtHsOn=FALSE; + BOOLEAN bWifiConnected=FALSE; + u1Byte wifiRssiState=BTC_RSSI_STATE_HIGH; + + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &bUnder4way); + + if(bWifiConnected) + { + if(bWifiBusy != bPreWifiBusy) + { + bPreWifiBusy = bWifiBusy; + return TRUE; + } + if(bUnder4way != bPreUnder4way) + { + bPreUnder4way = bUnder4way; + return TRUE; + } + if(bBtHsOn != bPreBtHsOn) + { + bPreBtHsOn = bBtHsOn; + return TRUE; + } + + + wifiRssiState = halbtc8821a2ant_WifiRssiState(pBtCoexist,3, 2, BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + + if ( (BTC_RSSI_STATE_HIGH ==wifiRssiState ) || (BTC_RSSI_STATE_LOW ==wifiRssiState )) + { + return TRUE; + } + + } + + return FALSE; +} + +VOID +halbtc8821a2ant_UpdateBtLinkInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bBtHsOn=FALSE; + +#if(BT_AUTO_REPORT_ONLY_8821A_2ANT == 1) // profile from bt patch + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + pBtLinkInfo->bBtLinkExist = pCoexSta->bBtLinkExist; + pBtLinkInfo->bScoExist = pCoexSta->bScoExist; + pBtLinkInfo->bA2dpExist = pCoexSta->bA2dpExist; + pBtLinkInfo->bPanExist = pCoexSta->bPanExist; + pBtLinkInfo->bHidExist = pCoexSta->bHidExist; + + // work around for HS mode. + if(bBtHsOn) + { + pBtLinkInfo->bPanExist = TRUE; + pBtLinkInfo->bBtLinkExist = TRUE; + } +#else // profile from bt stack + pBtLinkInfo->bBtLinkExist = pStackInfo->bBtLinkExist; + pBtLinkInfo->bScoExist = pStackInfo->bScoExist; + pBtLinkInfo->bA2dpExist = pStackInfo->bA2dpExist; + pBtLinkInfo->bPanExist = pStackInfo->bPanExist; + pBtLinkInfo->bHidExist = pStackInfo->bHidExist; + + //for win-8 stack HID report error + if(!pStackInfo->bHidExist) + pStackInfo->bHidExist = pCoexSta->bHidExist; //sync BTInfo with BT firmware and stack + // when stack HID report error, here we use the info from bt fw. + if(!pStackInfo->bBtLinkExist) + pStackInfo->bBtLinkExist = pCoexSta->bBtLinkExist; +#endif + // check if Sco only + if( pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bScoOnly = TRUE; + else + pBtLinkInfo->bScoOnly = FALSE; + + // check if A2dp only + if( !pBtLinkInfo->bScoExist && + pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bA2dpOnly = TRUE; + else + pBtLinkInfo->bA2dpOnly = FALSE; + + // check if Pan only + if( !pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + pBtLinkInfo->bPanExist && + !pBtLinkInfo->bHidExist ) + pBtLinkInfo->bPanOnly = TRUE; + else + pBtLinkInfo->bPanOnly = FALSE; + + // check if Hid only + if( !pBtLinkInfo->bScoExist && + !pBtLinkInfo->bA2dpExist && + !pBtLinkInfo->bPanExist && + pBtLinkInfo->bHidExist ) + pBtLinkInfo->bHidOnly = TRUE; + else + pBtLinkInfo->bHidOnly = FALSE; +} + +u1Byte +halbtc8821a2ant_ActionAlgorithm( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bBtHsOn=FALSE; + u1Byte algorithm=BT_8821A_2ANT_COEX_ALGO_UNDEFINED; + u1Byte numOfDiffProfile=0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + if(!pBtLinkInfo->bBtLinkExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], No BT link exists!!!\n")); + return algorithm; + } + + if(pBtLinkInfo->bScoExist) + numOfDiffProfile++; + if(pBtLinkInfo->bHidExist) + numOfDiffProfile++; + if(pBtLinkInfo->bPanExist) + numOfDiffProfile++; + if(pBtLinkInfo->bA2dpExist) + numOfDiffProfile++; + + if(numOfDiffProfile == 1) + { + if(pBtLinkInfo->bScoExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO only\n")); + algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; + } + else + { + if(pBtLinkInfo->bHidExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID only\n")); + algorithm = BT_8821A_2ANT_COEX_ALGO_HID; + } + else if(pBtLinkInfo->bA2dpExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP only\n")); + algorithm = BT_8821A_2ANT_COEX_ALGO_A2DP; + } + else if(pBtLinkInfo->bPanExist) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN(HS) only\n")); + algorithm = BT_8821A_2ANT_COEX_ALGO_PANHS; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN(EDR) only\n")); + algorithm = BT_8821A_2ANT_COEX_ALGO_PANEDR; + } + } + } + } + else if(numOfDiffProfile == 2) + { + if(pBtLinkInfo->bScoExist) + { + if(pBtLinkInfo->bHidExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID\n")); + algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; + } + else if(pBtLinkInfo->bA2dpExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + A2DP ==> SCO\n")); + algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; + } + else if(pBtLinkInfo->bPanExist) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + PAN(HS)\n")); + algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + PAN(EDR)\n")); + algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; + } + } + } + else + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bA2dpExist ) + { +#if 0 + if(pStackInfo->numOfHid >= 2) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID*2 + A2DP\n")); + algorithm = BT_8821A_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + else +#endif + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP\n")); + algorithm = BT_8821A_2ANT_COEX_ALGO_HID_A2DP; + } + } + else if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + PAN(HS)\n")); + algorithm = BT_8821A_2ANT_COEX_ALGO_HID; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + PAN(EDR)\n")); + algorithm = BT_8821A_2ANT_COEX_ALGO_PANEDR_HID; + } + } + else if( pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP + PAN(HS)\n")); + algorithm = BT_8821A_2ANT_COEX_ALGO_A2DP_PANHS; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP + PAN(EDR)\n")); + algorithm = BT_8821A_2ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } + } + else if(numOfDiffProfile == 3) + { + if(pBtLinkInfo->bScoExist) + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bA2dpExist ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + A2DP ==> SCO\n")); + algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; + } + else if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + PAN(HS) ==> SCO\n")); + algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + PAN(EDR) ==> SCO\n")); + algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; + } + } + else if( pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + A2DP + PAN(HS)\n")); + algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n")); + algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; + } + } + } + else + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP + PAN(HS)\n")); + algorithm = BT_8821A_2ANT_COEX_ALGO_HID_A2DP; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP + PAN(EDR)\n")); + algorithm = BT_8821A_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } + else if(numOfDiffProfile >= 3) + { + if(pBtLinkInfo->bScoExist) + { + if( pBtLinkInfo->bHidExist && + pBtLinkInfo->bPanExist && + pBtLinkInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n")); + + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n")); + algorithm = BT_8821A_2ANT_COEX_ALGO_SCO; + } + } + } + } + + return algorithm; +} + +VOID +halbtc8821a2ant_SetFwDacSwingLevel( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte dacSwingLvl + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + // There are several type of dacswing + // 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 + H2C_Parameter[0] = dacSwingLvl; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Set Dac Swing Level=0x%x\n", dacSwingLvl)); + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x64=0x%x\n", H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x64, 1, H2C_Parameter); +} + +VOID +halbtc8821a2ant_SetFwDecBtPwr( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte decBtPwrLvl + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + H2C_Parameter[0] = decBtPwrLvl; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], decrease Bt Power level = %d, FW write 0x62=0x%x\n", + decBtPwrLvl, H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x62, 1, H2C_Parameter); +} + +VOID +halbtc8821a2ant_DecBtPwr( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte decBtPwrLvl + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s Dec BT power level = %d\n", + (bForceExec? "force to":""), decBtPwrLvl)); + pCoexDm->curBtDecPwrLvl = decBtPwrLvl; + + if(!bForceExec) + { + if(pCoexDm->preBtDecPwrLvl == pCoexDm->curBtDecPwrLvl) + return; + } + halbtc8821a2ant_SetFwDecBtPwr(pBtCoexist, pCoexDm->curBtDecPwrLvl); + + pCoexDm->preBtDecPwrLvl = pCoexDm->curBtDecPwrLvl; +} + +VOID +halbtc8821a2ant_SetBtAutoReport( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bEnableAutoReport + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + H2C_Parameter[0] = 0; + + if(bEnableAutoReport) + { + H2C_Parameter[0] |= BIT0; + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], BT FW auto report : %s, FW write 0x68=0x%x\n", + (bEnableAutoReport? "Enabled!!":"Disabled!!"), H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x68, 1, H2C_Parameter); +} + +VOID +halbtc8821a2ant_BtAutoReport( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bEnableAutoReport + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s BT Auto report = %s\n", + (bForceExec? "force to":""), ((bEnableAutoReport)? "Enabled":"Disabled"))); + pCoexDm->bCurBtAutoReport = bEnableAutoReport; + + if(!bForceExec) + { + if(pCoexDm->bPreBtAutoReport == pCoexDm->bCurBtAutoReport) + return; + } + halbtc8821a2ant_SetBtAutoReport(pBtCoexist, pCoexDm->bCurBtAutoReport); + + pCoexDm->bPreBtAutoReport = pCoexDm->bCurBtAutoReport; +} + +VOID +halbtc8821a2ant_FwDacSwingLvl( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte fwDacSwingLvl + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s set FW Dac Swing level = %d\n", + (bForceExec? "force to":""), fwDacSwingLvl)); + pCoexDm->curFwDacSwingLvl = fwDacSwingLvl; + + if(!bForceExec) + { + if(pCoexDm->preFwDacSwingLvl == pCoexDm->curFwDacSwingLvl) + return; + } + + halbtc8821a2ant_SetFwDacSwingLevel(pBtCoexist, pCoexDm->curFwDacSwingLvl); + + pCoexDm->preFwDacSwingLvl = pCoexDm->curFwDacSwingLvl; +} + +VOID +halbtc8821a2ant_SetSwRfRxLpfCorner( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bRxRfShrinkOn + ) +{ + if(bRxRfShrinkOn) + { + //Shrink RF Rx LPF corner + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Shrink RF Rx LPF corner!!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, 0xffffc); + } + else + { + //Resume RF Rx LPF corner + // After initialized, we can use pCoexDm->btRf0x1eBackup + if(pBtCoexist->bInitilized) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Resume RF Rx LPF corner!!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, pCoexDm->btRf0x1eBackup); + } + } +} + +VOID +halbtc8821a2ant_RfShrink( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bRxRfShrinkOn + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Rx RF Shrink = %s\n", + (bForceExec? "force to":""), ((bRxRfShrinkOn)? "ON":"OFF"))); + pCoexDm->bCurRfRxLpfShrink = bRxRfShrinkOn; + + if(!bForceExec) + { + if(pCoexDm->bPreRfRxLpfShrink == pCoexDm->bCurRfRxLpfShrink) + return; + } + halbtc8821a2ant_SetSwRfRxLpfCorner(pBtCoexist, pCoexDm->bCurRfRxLpfShrink); + + pCoexDm->bPreRfRxLpfShrink = pCoexDm->bCurRfRxLpfShrink; +} + +VOID +halbtc8821a2ant_SetSwPenaltyTxRateAdaptive( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bLowPenaltyRa + ) +{ + u1Byte H2C_Parameter[6] ={0}; + + H2C_Parameter[0] = 0x6; // opCode, 0x6= Retry_Penalty + + if(bLowPenaltyRa) + { + H2C_Parameter[1] |= BIT0; + H2C_Parameter[2] = 0x00; //normal rate except MCS7/6/5, OFDM54/48/36 + H2C_Parameter[3] = 0xf5; //MCS7 or OFDM54 + H2C_Parameter[4] = 0xa0; //MCS6 or OFDM48 + H2C_Parameter[5] = 0xa0; //MCS5 or OFDM36 + //H2C_Parameter[3] = 0xf7; //MCS7 or OFDM54 + //H2C_Parameter[4] = 0xf8; //MCS6 or OFDM48 + //H2C_Parameter[5] = 0xf9; //MCS5 or OFDM36 + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set WiFi Low-Penalty Retry: %s", + (bLowPenaltyRa? "ON!!":"OFF!!")) ); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x69, 6, H2C_Parameter); +} + +VOID +halbtc8821a2ant_LowPenaltyRa( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bLowPenaltyRa + ) +{ + //return; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn LowPenaltyRA = %s\n", + (bForceExec? "force to":""), ((bLowPenaltyRa)? "ON":"OFF"))); + pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa; + + if(!bForceExec) + { + if(pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa) + return; + } + halbtc8821a2ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa); + + pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa; +} + +VOID +halbtc8821a2ant_SetDacSwingReg( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte level + ) +{ + u1Byte val=(u1Byte)level; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Write SwDacSwing = 0x%x\n", level)); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xc5b, 0x3e, val); +} + +VOID +halbtc8821a2ant_SetSwFullTimeDacSwing( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bSwDacSwingOn, + IN u4Byte swDacSwingLvl + ) +{ + if(bSwDacSwingOn) + { + halbtc8821a2ant_SetDacSwingReg(pBtCoexist, swDacSwingLvl); + } + else + { + halbtc8821a2ant_SetDacSwingReg(pBtCoexist, 0x18); + } +} + + +VOID +halbtc8821a2ant_DacSwing( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bDacSwingOn, + IN u4Byte dacSwingLvl + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn DacSwing=%s, dacSwingLvl=0x%x\n", + (bForceExec? "force to":""), ((bDacSwingOn)? "ON":"OFF"), dacSwingLvl)); + pCoexDm->bCurDacSwingOn = bDacSwingOn; + pCoexDm->curDacSwingLvl = dacSwingLvl; + + if(!bForceExec) + { + if( (pCoexDm->bPreDacSwingOn == pCoexDm->bCurDacSwingOn) && + (pCoexDm->preDacSwingLvl == pCoexDm->curDacSwingLvl) ) + return; + } + delay_ms(30); + halbtc8821a2ant_SetSwFullTimeDacSwing(pBtCoexist, bDacSwingOn, dacSwingLvl); + + pCoexDm->bPreDacSwingOn = pCoexDm->bCurDacSwingOn; + pCoexDm->preDacSwingLvl = pCoexDm->curDacSwingLvl; +} + +VOID +halbtc8821a2ant_SetAdcBackOff( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bAdcBackOff + ) +{ + if(bAdcBackOff) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level On!\n")); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x8db, 0x60, 0x3); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level Off!\n")); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x8db, 0x60, 0x1); + } +} + +VOID +halbtc8821a2ant_AdcBackOff( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bAdcBackOff + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn AdcBackOff = %s\n", + (bForceExec? "force to":""), ((bAdcBackOff)? "ON":"OFF"))); + pCoexDm->bCurAdcBackOff = bAdcBackOff; + + if(!bForceExec) + { + if(pCoexDm->bPreAdcBackOff == pCoexDm->bCurAdcBackOff) + return; + } + halbtc8821a2ant_SetAdcBackOff(pBtCoexist, pCoexDm->bCurAdcBackOff); + + pCoexDm->bPreAdcBackOff = pCoexDm->bCurAdcBackOff; +} + +VOID +halbtc8821a2ant_SetAgcTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bAgcTableEn + ) +{ + u1Byte rssiAdjustVal=0; + + //=================BB AGC Gain Table + if(bAgcTableEn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB Agc Table On!\n")); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6e1A0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6d1B0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6c1C0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6b1D0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6a1E0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x691F0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x68200001); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB Agc Table Off!\n")); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xaa1A0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa91B0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa81C0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa71D0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa61E0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa51F0001); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa4200001); + } + + + //=================RF Gain + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000); + if(bAgcTableEn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table On!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x38fff); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x38ffe); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table Off!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x380c3); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x28ce6); + } + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xef, 0xfffff, 0x0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xed, 0xfffff, 0x1); + if(bAgcTableEn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table On!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x40, 0xfffff, 0x38fff); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x40, 0xfffff, 0x38ffe); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table Off!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x40, 0xfffff, 0x380c3); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x40, 0xfffff, 0x28ce6); + } + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xed, 0xfffff, 0x0); + + // set rssiAdjustVal for wifi module. + if(bAgcTableEn) + { + rssiAdjustVal = 8; + } + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, &rssiAdjustVal); +} + +VOID +halbtc8821a2ant_AgcTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bAgcTableEn + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s %s Agc Table\n", + (bForceExec? "force to":""), ((bAgcTableEn)? "Enable":"Disable"))); + pCoexDm->bCurAgcTableEn = bAgcTableEn; + + if(!bForceExec) + { + if(pCoexDm->bPreAgcTableEn == pCoexDm->bCurAgcTableEn) + return; + } + halbtc8821a2ant_SetAgcTable(pBtCoexist, bAgcTableEn); + + pCoexDm->bPreAgcTableEn = pCoexDm->bCurAgcTableEn; +} + +VOID +halbtc8821a2ant_SetCoexTable( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte val0x6c0, + IN u4Byte val0x6c4, + IN u4Byte val0x6c8, + IN u1Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c0=0x%x\n", val0x6c0)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c0, val0x6c0); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c4=0x%x\n", val0x6c4)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c4, val0x6c4); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, val0x6c8); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc)); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cc, val0x6cc); +} + +VOID +halbtc8821a2ant_CoexTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u4Byte val0x6c0, + IN u4Byte val0x6c4, + IN u4Byte val0x6c8, + IN u1Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s write Coex Table 0x6c0=0x%x, 0x6c4=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n", + (bForceExec? "force to":""), val0x6c0, val0x6c4, val0x6c8, val0x6cc)); + pCoexDm->curVal0x6c0 = val0x6c0; + pCoexDm->curVal0x6c4 = val0x6c4; + pCoexDm->curVal0x6c8 = val0x6c8; + pCoexDm->curVal0x6cc = val0x6cc; + + if(!bForceExec) + { + if( (pCoexDm->preVal0x6c0 == pCoexDm->curVal0x6c0) && + (pCoexDm->preVal0x6c4 == pCoexDm->curVal0x6c4) && + (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) && + (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) ) + return; + } + halbtc8821a2ant_SetCoexTable(pBtCoexist, val0x6c0, val0x6c4, val0x6c8, val0x6cc); + + pCoexDm->preVal0x6c0 = pCoexDm->curVal0x6c0; + pCoexDm->preVal0x6c4 = pCoexDm->curVal0x6c4; + pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8; + pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc; +} + +VOID +halbtc8821a2ant_CoexTableWithType( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + pCoexSta->nCoexTableType = type; + + switch(type) + { + case 0: + halbtc8821a2ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x55555555, 0xffffff, 0x3); + break; + case 1: + halbtc8821a2ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x5afa5afa, 0xffffff, 0x3); + break; + case 2: + halbtc8821a2ant_CoexTable(pBtCoexist, bForceExec, 0x5ada5ada, 0x5ada5ada, 0xffffff, 0x3); + break; + case 3: + halbtc8821a2ant_CoexTable(pBtCoexist, bForceExec, 0xaaaaaaaa, 0xaaaaaaaa, 0xffffff, 0x3); + break; + case 4: + halbtc8821a2ant_CoexTable(pBtCoexist, bForceExec, 0xffffffff, 0xffffffff, 0xffffff, 0x3); + break; + case 5: + halbtc8821a2ant_CoexTable(pBtCoexist, bForceExec, 0x5fff5fff, 0x5fff5fff, 0xffffff, 0x3); + break; + case 6: + halbtc8821a2ant_CoexTable(pBtCoexist, bForceExec, 0x55ff55ff, 0x5a5a5a5a, 0xffffff, 0x3); + break; + case 7: + halbtc8821a2ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 8: + halbtc8821a2ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 9: + halbtc8821a2ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 10: + halbtc8821a2ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 11: + halbtc8821a2ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 12: + halbtc8821a2ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0x5ada5ada, 0xffffff, 0x3); + break; + case 13: + halbtc8821a2ant_CoexTable(pBtCoexist, bForceExec, 0x5fff5fff, 0xaaaaaaaa, 0xffffff, 0x3); + break; + case 14: + halbtc8821a2ant_CoexTable(pBtCoexist, bForceExec, 0x5fff5fff, 0x5ada5ada, 0xffffff, 0x3); + break; + case 15: + halbtc8821a2ant_CoexTable(pBtCoexist, bForceExec, 0x55dd55dd, 0xaaaaaaaa, 0xffffff, 0x3); + break; + case 16: + halbtc8821a2ant_CoexTable(pBtCoexist, bForceExec, 0x5fdf5fdf, 0x5fdb5fdb, 0xffffff, 0x3); + break; + case 17: + halbtc8821a2ant_CoexTable(pBtCoexist, bForceExec, 0xfafafafa, 0xfafafafa, 0xffffff, 0x3); + break; + default: + break; + } +} + +VOID +halbtc8821a2ant_SetFwIgnoreWlanAct( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bEnable + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + if(bEnable) + { + H2C_Parameter[0] |= BIT0; // function enable + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set FW for BT Ignore Wlan_Act, FW write 0x63=0x%x\n", + H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x63, 1, H2C_Parameter); +} + +VOID +halbtc8821a2ant_SetLpsRpwm( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + u1Byte lps=lpsVal; + u1Byte rpwm=rpwmVal; + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_LPS_VAL, &lps); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RPWM_VAL, &rpwm); +} + +VOID +halbtc8821a2ant_LpsRpwm( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + BOOLEAN bForceExecPwrCmd=FALSE; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s set lps/rpwm=0x%x/0x%x \n", + (bForceExec? "force to":""), lpsVal, rpwmVal)); + pCoexDm->curLps = lpsVal; + pCoexDm->curRpwm = rpwmVal; + + if(!bForceExec) + { + if( (pCoexDm->preLps == pCoexDm->curLps) && + (pCoexDm->preRpwm == pCoexDm->curRpwm) ) + { + return; + } + } + halbtc8821a2ant_SetLpsRpwm(pBtCoexist, lpsVal, rpwmVal); + + pCoexDm->preLps = pCoexDm->curLps; + pCoexDm->preRpwm = pCoexDm->curRpwm; +} + +VOID +halbtc8821a2ant_IgnoreWlanAct( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bEnable + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Ignore WlanAct %s\n", + (bForceExec? "force to":""), (bEnable? "ON":"OFF"))); + pCoexDm->bCurIgnoreWlanAct = bEnable; + + if(!bForceExec) + { + if(pCoexDm->bPreIgnoreWlanAct == pCoexDm->bCurIgnoreWlanAct) + return; + } + halbtc8821a2ant_SetFwIgnoreWlanAct(pBtCoexist, bEnable); + + pCoexDm->bPreIgnoreWlanAct = pCoexDm->bCurIgnoreWlanAct; +} + +VOID +halbtc8821a2ant_SetFwPstdma( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte byte1, + IN u1Byte byte2, + IN u1Byte byte3, + IN u1Byte byte4, + IN u1Byte byte5 + ) +{ + u1Byte H2C_Parameter[5] ={0}; + + H2C_Parameter[0] = byte1; + H2C_Parameter[1] = byte2; + H2C_Parameter[2] = byte3; + H2C_Parameter[3] = byte4; + H2C_Parameter[4] = byte5; + + pCoexDm->psTdmaPara[0] = byte1; + pCoexDm->psTdmaPara[1] = byte2; + pCoexDm->psTdmaPara[2] = byte3; + pCoexDm->psTdmaPara[3] = byte4; + pCoexDm->psTdmaPara[4] = byte5; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x60(5bytes)=0x%x%08x\n", + H2C_Parameter[0], + H2C_Parameter[1]<<24|H2C_Parameter[2]<<16|H2C_Parameter[3]<<8|H2C_Parameter[4])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x60, 5, H2C_Parameter); +} + +VOID +halbtc8821a2ant_SwMechanism1( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bShrinkRxLPF, + IN BOOLEAN bLowPenaltyRA, + IN BOOLEAN bLimitedDIG, + IN BOOLEAN bBTLNAConstrain + ) +{ + /* + u4Byte wifiBw; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if(BTC_WIFI_BW_HT40 != wifiBw) //only shrink RF Rx LPF for HT40 + { + if (bShrinkRxLPF) + bShrinkRxLPF = FALSE; + } + */ + + //halbtc8821a2ant_RfShrink(pBtCoexist, NORMAL_EXEC, bShrinkRxLPF); + halbtc8821a2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, bLowPenaltyRA); +} + +VOID +halbtc8821a2ant_SwMechanism2( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bAGCTableShift, + IN BOOLEAN bADCBackOff, + IN BOOLEAN bSWDACSwing, + IN u4Byte dacSwingLvl + ) +{ + //halbtc8821a2ant_AgcTable(pBtCoexist, NORMAL_EXEC, bAGCTableShift); + //halbtc8821a2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, bADCBackOff); + halbtc8821a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, bSWDACSwing, dacSwingLvl); +} + +VOID +halbtc8821a2ant_SetAntPath( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte antPosType, + IN BOOLEAN bInitHwCfg, + IN BOOLEAN bWifiOff + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + u4Byte u4Tmp=0; + u1Byte H2C_Parameter[2] ={0}; + + if(bInitHwCfg) + { + // 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x4c); + u4Tmp &=~BIT23; + u4Tmp |= BIT24; + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x4c, u4Tmp); + + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x974, 0x3ff); + //pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0xcb4, 0x77); + + if(pBoardInfo->btdmAntPos == BTC_ANTENNA_AT_MAIN_PORT) + { + //tell firmware "antenna inverse" ==> WRONG firmware antenna control code.==>need fw to fix + H2C_Parameter[0] = 1; + H2C_Parameter[1] = 1; + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x65, 2, H2C_Parameter); + } + else + { + //tell firmware "no antenna inverse" ==> WRONG firmware antenna control code.==>need fw to fix + H2C_Parameter[0] = 0; + H2C_Parameter[1] = 1; + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x65, 2, H2C_Parameter); + } + } + + // ext switch setting + switch(antPosType) + { + case BTC_ANT_WIFI_AT_MAIN: + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xcb7, 0x30, 0x1); + break; + case BTC_ANT_WIFI_AT_AUX: + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xcb7, 0x30, 0x2); + break; + } +} + +VOID +halbtc8821a2ant_PsTdma( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bTurnOn, + IN u1Byte type + ) +{ + BOOLEAN bTurnOnByCnt=FALSE; + u1Byte psTdmaTypeByCnt=0; + u1Byte wifiRssiState1, btRssiState; + + + wifiRssiState1 = halbtc8821a2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8821a2ant_BtRssiState(2, BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + if (!(BTC_RSSI_HIGH(wifiRssiState1) && BTC_RSSI_HIGH(btRssiState)) && bTurnOn) + { + type = type +100; //for WiFi RSSI low or BT RSSI low + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn %s PS TDMA, type=%d\n", + (bForceExec? "force to":""), (bTurnOn? "ON":"OFF"), type)); + pCoexDm->bCurPsTdmaOn = bTurnOn; + pCoexDm->curPsTdma = type; + + if(!bForceExec) + { + if( (pCoexDm->bPrePsTdmaOn == pCoexDm->bCurPsTdmaOn) && + (pCoexDm->prePsTdma == pCoexDm->curPsTdma) ) + return; + } + if(bTurnOn) + { + switch(type) + { + case 1: + default: + //halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x3c, 0x03, 0xf1, 0x90); + break; + case 2: + //halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0xe1, 0x90); + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x2d, 0x03, 0xf1, 0x90); + break; + case 3: + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1c, 0x3, 0xf1, 0x90); + break; + case 4: + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x10, 0x03, 0xf1, 0x90); + break; + case 5: + //halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x90); + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x3c, 0x3, 0x70, 0x90); + break; + case 6: + //halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0x60, 0x90); + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x2d, 0x3, 0x70, 0x90); + break; + case 7: + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1c, 0x3, 0x70, 0x90); + break; + case 8: + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xa3, 0x10, 0x3, 0x70, 0x90); + break; + case 9: + //halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x3c, 0x03, 0xf1, 0x90); + break; + case 10: + //halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0xe1, 0x90); + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x2d, 0x03, 0xf1, 0x90); + break; + case 11: + //halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0xa, 0xe1, 0x90); + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1c, 0x3, 0xf1, 0x90); + break; + case 12: + //halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0xe1, 0x90); + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x10, 0x3, 0xf1, 0x90); + break; + case 13: + //halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x90); + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x3c, 0x3, 0x70, 0x90); + break; + case 14: + //halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0x60, 0x90); + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x2d, 0x3, 0x70, 0x90); + break; + case 15: + //halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0xa, 0x60, 0x90); + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1c, 0x3, 0x70, 0x90); + break; + case 16: + //halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0x60, 0x90); + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x10, 0x3, 0x70, 0x90); + break; + case 17: + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xa3, 0x2f, 0x2f, 0x60, 0x90); + break; + case 18: + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0xe1, 0x90); + break; + case 19: + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x25, 0xe1, 0x90); + break; + case 20: + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x25, 0x60, 0x90); + break; + case 21: + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x15, 0x03, 0x70, 0x90); + break; + case 23: + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1e, 0x03, 0xf0, 0x14); + break; + case 24: + case 124: + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xd3, 0x3c, 0x03, 0x70, 0x50); + break; + //case25/case125 : for lenovo bt pan tp degrade<30% while wifi downlink + case 25: + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x14, 0x03, 0xf1, 0x90); + break; + case 26: + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x30, 0x03, 0xf1, 0x90); + break; + case 71: + //halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); + + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x3c, 0x03, 0xf1, 0x90); + break; + case 101: + case 105: + case 171: + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xd3, 0x3a, 0x03, 0x70, 0x50); + break; + case 102: + case 106: + case 110: + case 114: + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xd3, 0x2d, 0x03, 0x70, 0x50); + break; + case 103: + case 107: + case 111: + case 115: + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xd3, 0x1c, 0x03, 0x70, 0x50); + break; + case 104: + case 108: + case 112: + case 116: + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xd3, 0x10, 0x03, 0x70, 0x50); + break; + case 109: + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x3c, 0x03, 0xf1, 0x90); + break; + case 113: + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x3c, 0x03, 0x70, 0x90); + break; + case 121: + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x15, 0x03, 0x70, 0x90); + break; + case 22: + case 122: + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x35, 0x03, 0x71, 0x11); + break; + case 123: + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xd3, 0x1c, 0x03, 0x70, 0x54); + break; + //case25/case125 : for lenovo bt pan tp degrade<30% while wifi downlink + case 125: + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xd3, 0x14, 0x03, 0x70, 0x50); + break; + case 126: + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0xd3, 0x30, 0x03, 0x70, 0x50); + break; + } + } + else + { + // disable PS tdma + switch(type) + { + case 0: + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x40, 0x0); + break; + case 1: + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x48, 0x0); + break; + default: + halbtc8821a2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x40, 0x0); + break; + } + } + + // update pre state + pCoexDm->bPrePsTdmaOn = pCoexDm->bCurPsTdmaOn; + pCoexDm->prePsTdma = pCoexDm->curPsTdma; +} + +VOID +halbtc8821a2ant_PsTdmaCheckForPowerSaveState( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bNewPsState + ) +{ + u1Byte lpsMode=0x0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_LPS_MODE, &lpsMode); + + if(lpsMode) // already under LPS state + { + if(bNewPsState) + { + // keep state under LPS, do nothing. + } + else + { + // will leave LPS state, turn off psTdma first + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + } + } + else // NO PS state + { + if(bNewPsState) + { + // will enter LPS state, turn off psTdma first + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + } + else + { + // keep state under NO PS state, do nothing. + } + } +} + +VOID +halbtc8821a2ant_PowerSaveState( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte psType, + IN u1Byte lpsVal, + IN u1Byte rpwmVal + ) +{ + BOOLEAN bLowPwrDisable=FALSE; + + switch(psType) + { + case BTC_PS_WIFI_NATIVE: + // recover to original 32k low power setting + bLowPwrDisable = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_NORMAL_LPS, NULL); + pCoexSta->bForceLpsOn = FALSE; + break; + case BTC_PS_LPS_ON: + halbtc8821a2ant_PsTdmaCheckForPowerSaveState(pBtCoexist, TRUE); + halbtc8821a2ant_LpsRpwm(pBtCoexist, NORMAL_EXEC, lpsVal, rpwmVal); + // when coex force to enter LPS, do not enter 32k low power. + bLowPwrDisable = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + // power save must executed before psTdma. + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_ENTER_LPS, NULL); + pCoexSta->bForceLpsOn = TRUE; + break; + case BTC_PS_LPS_OFF: + halbtc8821a2ant_PsTdmaCheckForPowerSaveState(pBtCoexist, FALSE); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_LEAVE_LPS, NULL); + pCoexSta->bForceLpsOn = FALSE; + break; + default: + break; + } +} + + +VOID +halbtc8821a2ant_CoexAllOff( + IN PBTC_COEXIST pBtCoexist + ) +{ + // fw all off + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + halbtc8821a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + // sw all off + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + // hw all off + //pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); +} + +VOID +halbtc8821a2ant_CoexUnder5G( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8821a2ant_CoexAllOff(pBtCoexist); + + halbtc8821a2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, TRUE); +} + +VOID +halbtc8821a2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + // force to reset coex mechanism + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8821a2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); + halbtc8821a2ant_FwDacSwingLvl(pBtCoexist, FORCE_EXEC, 6); + halbtc8821a2ant_DecBtPwr(pBtCoexist, FORCE_EXEC, 0); + + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); +} + +VOID +halbtc8821a2ant_ActionBtInquiry( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btRssiState; + BOOLEAN bWifiConnected=FALSE; + BOOLEAN bLowPwrDisable=TRUE; + BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE; + + + wifiRssiState = halbtc8821a2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + wifiRssiState1 = halbtc8821a2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8821a2ant_BtRssiState(2, BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + + + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + if(bScan || bLink || bRoam) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi link process + BT Inq/Page!!\n")); + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 15); + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 22); + } + else if(bWifiConnected) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi connected + BT Inq/Page!!\n")); + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 15); + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 22); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi no-link + BT Inq/Page!!\n")); + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + } + + halbtc8821a2ant_FwDacSwingLvl(pBtCoexist, FORCE_EXEC, 6); + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + +} + + +VOID +halbtc8821a2ant_ActionWiFiLinkProcess( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte u1Tmpa, u1Tmpb; + + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 15); + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 22); + + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + + + u1Tmpa = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x765); + u1Tmpb = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x76e); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], 0x765=0x%x, 0x76e=0x%x\n", u1Tmpa, u1Tmpb)); +} + +BOOLEAN +halbtc8821a2ant_ActionWifiIdleProcess( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btRssiState; + u4Byte wifiBw; + u1Byte apNum=0; + + wifiRssiState = halbtc8821a2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + //wifiRssiState1 = halbtc8821a2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + wifiRssiState1 = halbtc8821a2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES-20, 0); + btRssiState = halbtc8821a2ant_BtRssiState(2, BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_AP_NUM, &apNum); + + // define the office environment + if(BTC_RSSI_HIGH(wifiRssiState1) && + (pCoexSta->bHidExist == TRUE) && (pCoexSta->bA2dpExist == TRUE)) + { + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi idle process for BT HID+A2DP exist!!\n")); + + halbtc8821a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x6); + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + // sw all off + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + + return TRUE; + } + + // + else if (pCoexSta->bPanExist== TRUE) + { + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi idle process for BT PAN exist!!\n")); + + halbtc8821a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x6); + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + // sw all off + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + + return TRUE; + } + + else + { + halbtc8821a2ant_DacSwing(pBtCoexist, NORMAL_EXEC, TRUE, 0x18); + return FALSE; + } + + +} + + + +BOOLEAN +halbtc8821a2ant_IsCommonAction( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte btRssiState=BTC_RSSI_STATE_HIGH; + BOOLEAN bCommon=FALSE, bWifiConnected=FALSE, bWifiBusy=FALSE; + BOOLEAN bBtHsOn=FALSE, bLowPwrDisable=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + + if(!bWifiConnected) + { + bLowPwrDisable = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + halbtc8821a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi non-connected idle!!\n")); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + halbtc8821a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + bCommon = TRUE; + } + else + { + if(BT_8821A_2ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus) + { + bLowPwrDisable = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + halbtc8821a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi connected + BT non connected-idle!!\n")); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + halbtc8821a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0xb); + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + bCommon = TRUE; + } + else if(BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) + { + bLowPwrDisable = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + + if(bBtHsOn) + return FALSE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi connected + BT connected-idle!!\n")); + halbtc8821a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + halbtc8821a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0xb); + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8821a2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + bCommon = TRUE; + } + else + { + bLowPwrDisable = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + + if(bWifiBusy) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi Connected-Busy + BT Busy!!\n")); + bCommon = FALSE; + //bCommon = halbtc8821a2ant_ActionWifiIdleProcess(pBtCoexist); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi Connected-Idle + BT Busy!!\n")); + //bCommon = FALSE; + bCommon = halbtc8821a2ant_ActionWifiIdleProcess(pBtCoexist); + } + } + } + + return bCommon; +} +VOID +halbtc8821a2ant_TdmaDurationAdjust( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bScoHid, + IN BOOLEAN bTxPause, + IN u1Byte maxInterval + ) +{ + static s4Byte up,dn,m,n,WaitCount; + s4Byte result; //0: no change, +1: increase WiFi duration, -1: decrease WiFi duration + u1Byte retryCount=0; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TdmaDurationAdjust()\n")); + + if(!pCoexDm->bAutoTdmaAdjust) + { + pCoexDm->bAutoTdmaAdjust = TRUE; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], first run TdmaDurationAdjust()!!\n")); + { + if(bScoHid) + { + if(bTxPause) + { + if(maxInterval == 1) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + pCoexDm->psTdmaDuAdjType = 13; + } + else if(maxInterval == 2) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(maxInterval == 3) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + } + else + { + if(maxInterval == 1) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(maxInterval == 2) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(maxInterval == 3) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + } + } + else + { + if(bTxPause) + { + if(maxInterval == 1) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + pCoexDm->psTdmaDuAdjType = 5; + } + else if(maxInterval == 2) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(maxInterval == 3) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + } + else + { + if(maxInterval == 1) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + else if(maxInterval == 2) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(maxInterval == 3) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + } + } + } + //============ + up = 0; + dn = 0; + m = 1; + n= 3; + result = 0; + WaitCount = 0; + } + else + { + //accquire the BT TRx retry count from BT_Info byte2 + retryCount = pCoexSta->btRetryCnt; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], retryCount = %d\n", retryCount)); + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], up=%d, dn=%d, m=%d, n=%d, WaitCount=%d\n", + up, dn, m, n, WaitCount)); + result = 0; + WaitCount++; + + if(retryCount == 0) // no retry in the last 2-second duration + { + up++; + dn--; + + if (dn <= 0) + dn = 0; + + if(up >= n) // if s n 2 retry count0, hռeWiFi duration + { + WaitCount = 0; + n = 3; + up = 0; + dn = 0; + result = 1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Increase wifi duration!!\n")); + } + } + else if (retryCount <= 3) // <=3 retry in the last 2-second duration + { + up--; + dn++; + + if (up <= 0) + up = 0; + + if (dn == 2) // if s 2 2 retry count< 3, hկWiFi duration + { + if (WaitCount <= 2) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter<3!!\n")); + } + } + else //retry count > 3, un1 retry count > 3, hկWiFi duration + { + if (WaitCount == 1) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter>3!!\n")); + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], max Interval = %d\n", maxInterval)); + if(maxInterval == 1) + { + if(bTxPause) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 1\n")); + + if(pCoexDm->curPsTdma == 71) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + pCoexDm->psTdmaDuAdjType = 5; + } + else if(pCoexDm->curPsTdma == 1) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + pCoexDm->psTdmaDuAdjType = 5; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 4) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + if(pCoexDm->curPsTdma == 9) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + pCoexDm->psTdmaDuAdjType = 13; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + + if(result == -1) + { + if(pCoexDm->curPsTdma == 5) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + else if(pCoexDm->curPsTdma == 13) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 8) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + pCoexDm->psTdmaDuAdjType = 5; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + pCoexDm->psTdmaDuAdjType = 13; + } + } + } + else + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 0\n")); + if(pCoexDm->curPsTdma == 5) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 71); + pCoexDm->psTdmaDuAdjType = 71; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 8) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + if(pCoexDm->curPsTdma == 13) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + + if(result == -1) + { + if(pCoexDm->curPsTdma == 71) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + else if(pCoexDm->curPsTdma == 1) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 4) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + else if(pCoexDm->curPsTdma == 1) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 71); + pCoexDm->psTdmaDuAdjType = 71; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + } + } + } + else if(maxInterval == 2) + { + if(bTxPause) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 1\n")); + if(pCoexDm->curPsTdma == 1) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 4) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + if(pCoexDm->curPsTdma == 9) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 5) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + else if(pCoexDm->curPsTdma == 13) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 8) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + } + } + else + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 0\n")); + if(pCoexDm->curPsTdma == 5) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 8) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + if(pCoexDm->curPsTdma == 13) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 1) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 4) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + } + } + } + else if(maxInterval == 3) + { + if(bTxPause) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 1\n")); + if(pCoexDm->curPsTdma == 1) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 4) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + if(pCoexDm->curPsTdma == 9) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 5) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + else if(pCoexDm->curPsTdma == 13) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 8) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + } + } + else + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 0\n")); + if(pCoexDm->curPsTdma == 5) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 8) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + if(pCoexDm->curPsTdma == 13) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 1) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 4) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + } + } + } + } + + // if current PsTdma not match with the recorded one (when scan, dhcp...), + // then we have to adjust it back to the previous record one. + if(pCoexDm->curPsTdma != pCoexDm->psTdmaDuAdjType) + { + BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PsTdma type dismatch!!!, curPsTdma=%d, recordPsTdma=%d\n", + pCoexDm->curPsTdma, pCoexDm->psTdmaDuAdjType)); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + + if( !bScan && !bLink && !bRoam) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, pCoexDm->psTdmaDuAdjType); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n")); + } + } +} + +// SCO only or SCO+PAN(HS) +VOID +halbtc8821a2ant_ActionSco( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + u1Byte wifiRssiState, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8821a2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + btRssiState = halbtc8821a2ant_BtRssiState(2, BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8821a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8821a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 4); + + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if (BTC_WIFI_BW_LEGACY == wifiBw) //for SCO quality at 11b/g mode + { + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + } + else //for SCO quality & wifi performance balance at 11n mode + { + if(BTC_WIFI_BW_HT40 == wifiBw) + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 8); + else + { + if(pBtLinkInfo->bScoOnly) + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 17); + else + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 12); + } + } + + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); //for voice quality + + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,TRUE,0x18); + } + else + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,TRUE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,TRUE,0x18); + } + else + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,TRUE,0x18); + } + } +} + + +VOID +halbtc8821a2ant_ActionHid( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8821a2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + btRssiState = halbtc8821a2ant_BtRssiState(2, BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8821a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8821a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if (BTC_WIFI_BW_LEGACY == wifiBw) //for HID at 11b/g mode + { + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + } + else //for HID quality & wifi performance balance at 11n mode + { + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); + } + + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 24); + + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +//A2DP only / PAN(EDR) only/ A2DP+PAN(HS) +VOID +halbtc8821a2ant_ActionA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btRssiState; + u4Byte wifiBw; + u1Byte apNum=0; + + wifiRssiState = halbtc8821a2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + wifiRssiState1 = halbtc8821a2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8821a2ant_BtRssiState(2, BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_AP_NUM, &apNum); + + // define the office environment + if( (apNum >= 10) && BTC_RSSI_HIGH(wifiRssiState1) && BTC_RSSI_HIGH(btRssiState)) + { + //DbgPrint(" AP#>10(%d)\n", apNum); + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + halbtc8821a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + halbtc8821a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + //halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 23); + + // sw mechanism + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,TRUE,0x6); + } + else + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,TRUE,0x6); + } + return; + + } + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + halbtc8821a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8821a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + + if (BTC_RSSI_HIGH(wifiRssiState1) && BTC_RSSI_HIGH(btRssiState)) + { + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } + else + { + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 13); + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + } + + + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + //halbtc8821a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 1); + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 23); + } + else + { + //halbtc8821a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 1); + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 23); + } + + // sw mechanism + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +VOID +halbtc8821a2ant_ActionA2dpPanHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8821a2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + wifiRssiState1 = halbtc8821a2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8821a2ant_BtRssiState(2, BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8821a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8821a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifiRssiState1) && BTC_RSSI_HIGH(btRssiState)) + { + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } + else + { + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 13); + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + } + + halbtc8821a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 2); + + // sw mechanism + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +VOID +halbtc8821a2ant_ActionPanEdr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState,wifiRssiState1, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8821a2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + wifiRssiState1 = halbtc8821a2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8821a2ant_BtRssiState(2, BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8821a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8821a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifiRssiState1) && BTC_RSSI_HIGH(btRssiState)) + { + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 10); + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } + else + { + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 13); + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + } + + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 26); + } + else + { + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 26); + } + + // sw mechanism + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + + +//PAN(HS) only +VOID +halbtc8821a2ant_ActionPanHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8821a2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + wifiRssiState1 = halbtc8821a2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8821a2ant_BtRssiState(2, BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8821a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8821a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +//PAN(EDR)+A2DP +VOID +halbtc8821a2ant_ActionPanEdrA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8821a2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + wifiRssiState1 = halbtc8821a2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8821a2ant_BtRssiState(2, BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8821a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8821a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifiRssiState1) && BTC_RSSI_HIGH(btRssiState)) + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + else + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 12); + + if(BTC_WIFI_BW_HT40 == wifiBw) + halbtc8821a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 3); + else + halbtc8821a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 3); + } + else + { + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 13); + halbtc8821a2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 3); + } + + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +VOID +halbtc8821a2ant_ActionPanEdrHid( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8821a2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + wifiRssiState1 = halbtc8821a2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8821a2ant_BtRssiState(2, BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + halbtc8821a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifiRssiState1) && BTC_RSSI_HIGH(btRssiState)) + { + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } + else + { + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 14); + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + } + + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + if(BTC_WIFI_BW_HT40 == wifiBw) + { + halbtc8821a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 3); + //halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 11); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x780); + } + else + { + halbtc8821a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + //halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + } + halbtc8821a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 2); + } + else + { + halbtc8821a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + //halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 14); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + halbtc8821a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 2); + } + + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +// HID+A2DP+PAN(EDR) +VOID +halbtc8821a2ant_ActionHidA2dpPanEdr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState,wifiRssiState1, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8821a2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + wifiRssiState1 = halbtc8821a2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8821a2ant_BtRssiState(2, BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 0); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8821a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, FALSE, 0x8); + + halbtc8821a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + if (BTC_RSSI_HIGH(wifiRssiState1) && BTC_RSSI_HIGH(btRssiState)) + { + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } + else + { + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 14); + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + if(BTC_WIFI_BW_HT40 == wifiBw) + halbtc8821a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 3); + else + halbtc8821a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 3); + } + else + { + halbtc8821a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 3); + } + + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +VOID +halbtc8821a2ant_ActionHidA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, wifiRssiState1, btRssiState; + u4Byte wifiBw; + u1Byte apNum=0; + + wifiRssiState = halbtc8821a2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + //btRssiState = halbtc8821a2ant_BtRssiState(2, 29, 0); + wifiRssiState1 = halbtc8821a2ant_WifiRssiState(pBtCoexist, 1, 2, BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES, 0); + btRssiState = halbtc8821a2ant_BtRssiState(3, BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES, 37); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + + halbtc8821a2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, TRUE, 0x5); + + halbtc8821a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_LEGACY == wifiBw) + { + if(BTC_RSSI_HIGH(btRssiState)) + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else if(BTC_RSSI_MEDIUM(btRssiState)) + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + } + else + { // only 802.11N mode we have to dec bt power to 4 degree + if(BTC_RSSI_HIGH(btRssiState)) + { + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_AP_NUM, &apNum); + // need to check ap Number of Not + if(apNum < 10) + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 4); + else + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + } + else if(BTC_RSSI_MEDIUM(btRssiState)) + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); + else + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + } + + if (BTC_RSSI_HIGH(wifiRssiState1) && BTC_RSSI_HIGH(btRssiState)) + { + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + } + else + { + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 14); + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_LPS_ON, 0x50, 0x4); + } + + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + //halbtc8821a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 3); + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 23); + } + else + { + //halbtc8821a2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 3); + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 23); + } + + // sw mechanism + if(BTC_WIFI_BW_HT40 == wifiBw) + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +VOID +halbtc8821a2ant_ActionBtWhckTest( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + // sw all off + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); +} + +VOID +halbtc8821a2ant_ActionWifiMultiPort( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8821a2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8821a2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); + + // sw all off + halbtc8821a2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821a2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + // hw all off + //pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); + halbtc8821a2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); + + halbtc8821a2ant_PowerSaveState(pBtCoexist, BTC_PS_WIFI_NATIVE, 0x0, 0x0); + halbtc8821a2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); +} + +VOID +halbtc8821a2ant_RunCoexistMechanism( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bWifiUnder5G=FALSE, bBtHsOn=FALSE; + u1Byte btInfoOriginal=0, btRetryCnt=0; + u1Byte algorithm=0; + u4Byte numOfWifiLink=0; + u4Byte wifiLinkStatus=0; + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + BOOLEAN bMiracastPlusBt=FALSE; + BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism()===>\n")); + + if(pBtCoexist->bManualControl) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism(), return for Manual CTRL <===\n")); + return; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_5G, &bWifiUnder5G); + if(bWifiUnder5G) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism(), run 5G coex setting!!<===\n")); + halbtc8821a2ant_CoexUnder5G(pBtCoexist); + return; + } + + if(pCoexSta->bUnderIps) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi is under IPS !!!\n")); + return; + } + + if(pCoexSta->bBtWhckTest) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is under WHCK TEST!!!\n")); + halbtc8821a2ant_ActionBtWhckTest(pBtCoexist); + return; + } + + algorithm = halbtc8821a2ant_ActionAlgorithm(pBtCoexist); + if(pCoexSta->bC2hBtInquiryPage && (BT_8821A_2ANT_COEX_ALGO_PANHS!=algorithm)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is under inquiry/page scan !!\n")); + halbtc8821a2ant_ActionBtInquiry(pBtCoexist); + return; + } + else + { + + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + + if(bScan || bLink || bRoam) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], WiFi is under Link Process !!\n")); + halbtc8821a2ant_ActionWiFiLinkProcess(pBtCoexist); + return; + } + + //for P2P + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_LINK_STATUS, &wifiLinkStatus); + numOfWifiLink = wifiLinkStatus>>16; + + if((numOfWifiLink>=2) || (wifiLinkStatus&WIFI_P2P_GO_CONNECTED)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], Multi-Port numOfWifiLink = %d, wifiLinkStatus = 0x%x\n", numOfWifiLink,wifiLinkStatus) ); + + if(pBtLinkInfo->bBtLinkExist) + { + bMiracastPlusBt = TRUE; + } + else + { + bMiracastPlusBt = FALSE; + } + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_MIRACAST_PLUS_BT, &bMiracastPlusBt); + halbtc8821a2ant_ActionWifiMultiPort(pBtCoexist); + + return; + } + else + { + bMiracastPlusBt = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_MIRACAST_PLUS_BT, &bMiracastPlusBt); + } + + pCoexDm->curAlgorithm = algorithm; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Algorithm = %d \n", pCoexDm->curAlgorithm)); + + if(halbtc8821a2ant_IsCommonAction(pBtCoexist)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant common.\n")); + pCoexDm->bAutoTdmaAdjust = FALSE; + } + else + { + if(pCoexDm->curAlgorithm != pCoexDm->preAlgorithm) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], preAlgorithm=%d, curAlgorithm=%d\n", + pCoexDm->preAlgorithm, pCoexDm->curAlgorithm)); + pCoexDm->bAutoTdmaAdjust = FALSE; + } + switch(pCoexDm->curAlgorithm) + { + case BT_8821A_2ANT_COEX_ALGO_SCO: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = SCO.\n")); + halbtc8821a2ant_ActionSco(pBtCoexist); + break; + case BT_8821A_2ANT_COEX_ALGO_HID: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID.\n")); + halbtc8821a2ant_ActionHid(pBtCoexist); + break; + case BT_8821A_2ANT_COEX_ALGO_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = A2DP.\n")); + halbtc8821a2ant_ActionA2dp(pBtCoexist); + break; + case BT_8821A_2ANT_COEX_ALGO_A2DP_PANHS: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n")); + halbtc8821a2ant_ActionA2dpPanHs(pBtCoexist); + break; + case BT_8821A_2ANT_COEX_ALGO_PANEDR: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n")); + halbtc8821a2ant_ActionPanEdr(pBtCoexist); + break; + case BT_8821A_2ANT_COEX_ALGO_PANHS: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HS mode.\n")); + halbtc8821a2ant_ActionPanHs(pBtCoexist); + break; + case BT_8821A_2ANT_COEX_ALGO_PANEDR_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n")); + halbtc8821a2ant_ActionPanEdrA2dp(pBtCoexist); + break; + case BT_8821A_2ANT_COEX_ALGO_PANEDR_HID: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n")); + halbtc8821a2ant_ActionPanEdrHid(pBtCoexist); + break; + case BT_8821A_2ANT_COEX_ALGO_HID_A2DP_PANEDR: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n")); + halbtc8821a2ant_ActionHidA2dpPanEdr(pBtCoexist); + break; + case BT_8821A_2ANT_COEX_ALGO_HID_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n")); + halbtc8821a2ant_ActionHidA2dp(pBtCoexist); + break; + default: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n")); + halbtc8821a2ant_CoexAllOff(pBtCoexist); + break; + } + pCoexDm->preAlgorithm = pCoexDm->curAlgorithm; + } +} + +VOID +halbtc8821a2ant_WifiOffHwCfg( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bIsInMpMode = FALSE; + u1Byte H2C_Parameter[2] ={0}; + u4Byte fwVer=0; + + // set wlan_act to low + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0x4); + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x780); //WiFi goto standby while GNT_BT 0-->1 + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); + if(fwVer >= 0x180000) + { + /* Use H2C to set GNT_BT to HIGH */ + H2C_Parameter[0] = 1; + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x6E, 1, H2C_Parameter); + } + else + { + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x765, 0x18); + } +} + +VOID +halbtc8821a2ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bBackUp + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + u4Byte u4Tmp=0, fwVer; + u2Byte u2Tmp=0; + u1Byte u1Tmp=0; + u1Byte H2C_Parameter[2] ={0}; + + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 2Ant Init HW Config!!\n")); + + // backup rf 0x1e value + pCoexDm->btRf0x1eBackup = + pBtCoexist->fBtcGetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff); + + // 0x790[5:0]=0x5 + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x790); + u1Tmp &= 0xc0; + u1Tmp |= 0x5; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x790, u1Tmp); + + //Antenna config + halbtc8821a2ant_SetAntPath(pBtCoexist, BTC_ANT_WIFI_AT_MAIN, TRUE, FALSE); + pCoexSta->disVerInfoCnt = 0; + + // PTA parameter + halbtc8821a2ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 0); + + // Enable counter statistics + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0x4); //0x76e[3] =1, WLAN_Act control by PTA + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x778, 0x3); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x40, 0x20, 0x1); +} + +//============================================================ +// work around function start with wa_halbtc8821a2ant_ +//============================================================ +//============================================================ +// extern function start with EXhalbtc8821a2ant_ +//============================================================ +VOID +EXhalbtc8821a2ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ) +{ + +} + +VOID +EXhalbtc8821a2ant_PreLoadFirmware( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + u1Byte u1Tmp=0x4; /* Set BIT2 by default since it's 2ant case */ + + // + // S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) + // Local setting bit define + // BIT0: "0" for no antenna inverse; "1" for antenna inverse + // BIT1: "0" for internal switch; "1" for external switch + // BIT2: "0" for one antenna; "1" for two antenna + // NOTE: here default all internal switch and 1-antenna ==> BIT1=0 and BIT2=0 + if(pBtCoexist->chipInterface == BTC_INTF_USB) + { + // fixed at S0 for USB interface + u1Tmp |= 0x1; // antenna inverse + pBtCoexist->fBtcWriteLocalReg1Byte(pBtCoexist, 0xfe08, u1Tmp); + } + else + { + // for PCIE and SDIO interface, we check efuse 0xc3[6] + if(pBoardInfo->singleAntPath == 0) + { + } + else if(pBoardInfo->singleAntPath == 1) + { + // set to S0 + u1Tmp |= 0x1; // antenna inverse + } + + if(pBtCoexist->chipInterface == BTC_INTF_PCI) + { + pBtCoexist->fBtcWriteLocalReg1Byte(pBtCoexist, 0x384, u1Tmp); + } + else if(pBtCoexist->chipInterface == BTC_INTF_SDIO) + { + pBtCoexist->fBtcWriteLocalReg1Byte(pBtCoexist, 0x60, u1Tmp); + } + } +} + +VOID +EXhalbtc8821a2ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ) +{ + halbtc8821a2ant_InitHwConfig(pBtCoexist, TRUE); +} + +VOID +EXhalbtc8821a2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Coex Mechanism Init!!\n")); + + halbtc8821a2ant_InitCoexDm(pBtCoexist); +} + +VOID +EXhalbtc8821a2ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + pu1Byte cliBuf=pBtCoexist->cliBuf; + u1Byte u1Tmp[4], i, btInfoExt, psTdmaCase=0; + u4Byte u4Tmp[4]; + u4Byte faOfdm, faCck; + u4Byte fwVer=0, btPatchVer=0; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cliBuf); + + if(pBtCoexist->bManualControl) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[Under Manual Control]============"); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n =========================================="); + CL_PRINTF(cliBuf); + } + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:", \ + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \ + ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion); + CL_PRINTF(cliBuf); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_BT_PATCH_VER, &btPatchVer); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)", "CoexVer/ FwVer/ PatchVer", \ + GLCoexVerDate8821a2Ant, GLCoexVer8821a2Ant, fwVer, btPatchVer, btPatchVer); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", "Wifi channel informed to BT", \ + pCoexDm->wifiChnlInfo[0], pCoexDm->wifiChnlInfo[1], + pCoexDm->wifiChnlInfo[2]); + CL_PRINTF(cliBuf); + + // wifi status + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Wifi Status]============"); + CL_PRINTF(cliBuf); + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[BT Status]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %ddBm/ %d] ", "BT [status/ rssi/ retryCnt]", \ + ((pBtCoexist->btInfo.bBtDisabled)? ("disabled"): ((pCoexSta->bC2hBtInquiryPage)?("inquiry/page scan"):((BT_8821A_2ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus)? "non-connected idle": + ( (BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus)? "connected-idle":"busy")))), + pCoexSta->btRssi-100, pCoexSta->btRetryCnt); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP", \ + pBtLinkInfo->bScoExist, pBtLinkInfo->bHidExist, pBtLinkInfo->bPanExist, pBtLinkInfo->bA2dpExist); + CL_PRINTF(cliBuf); + + if (pStackInfo->bProfileNotified) + { + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO); + } + else + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Role", \ + (pBtLinkInfo->bSlaveRole )? "Slave":"Master"); + CL_PRINTF(cliBuf); + } + + btInfoExt = pCoexSta->btInfoExt; + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Info A2DP rate", \ + (btInfoExt&BIT0)? "Basic rate":"EDR rate"); + CL_PRINTF(cliBuf); + + for(i=0; ibtInfoC2hCnt[i]) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", GLBtInfoSrc8821a2Ant[i], \ + pCoexSta->btInfoC2h[i][0], pCoexSta->btInfoC2h[i][1], + pCoexSta->btInfoC2h[i][2], pCoexSta->btInfoC2h[i][3], + pCoexSta->btInfoC2h[i][4], pCoexSta->btInfoC2h[i][5], + pCoexSta->btInfoC2h[i][6], pCoexSta->btInfoC2hCnt[i]); + CL_PRINTF(cliBuf); + } + } + + // Sw mechanism + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============"); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", "SM1[ShRf/ LpRA/ LimDig]", \ + pCoexDm->bCurRfRxLpfShrink, pCoexDm->bCurLowPenaltyRa, pCoexDm->bLimitedDig); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", \ + pCoexDm->bCurAgcTableEn, pCoexDm->bCurAdcBackOff, pCoexDm->bCurDacSwingOn, pCoexDm->curDacSwingLvl); + CL_PRINTF(cliBuf); + + // Fw mechanism + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============"); + CL_PRINTF(cliBuf); + + psTdmaCase = pCoexDm->curPsTdma; + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)", "PS TDMA", \ + pCoexDm->psTdmaPara[0], pCoexDm->psTdmaPara[1], + pCoexDm->psTdmaPara[2], pCoexDm->psTdmaPara[3], + pCoexDm->psTdmaPara[4], psTdmaCase, pCoexDm->bAutoTdmaAdjust); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "Coex Table Type", \ + pCoexSta->nCoexTableType); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "DecBtPwr/ IgnWlanAct", \ + pCoexDm->curBtDecPwrLvl, pCoexDm->bCurIgnoreWlanAct); + CL_PRINTF(cliBuf); + + // Hw setting + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "RF-A, 0x1e initVal", \ + pCoexDm->btRf0x1eBackup); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x778); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xc5b); + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x880); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x778/0x880[29:25]/0xc58[29:25]", \ + u1Tmp[0], (u4Tmp[0]&0x3e000000) >> 25, ((u1Tmp[1]&0x3e)>>1)); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x764); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x76e); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x764/ 0x765/ 0x76e", \ + (u4Tmp[0]&0xff), (u4Tmp[0]&0xff00)>>8, u1Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xcb4); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0xcb4[7:0](ctrl)/ 0xcb4[29:28](val)", \ + u4Tmp[0]&0xff, ((u4Tmp[0]&0x30000000)>>28)); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x40); + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x4c); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x974); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x40/ 0x4c[24:23]/ 0x974", \ + u1Tmp[0], ((u4Tmp[0]&0x01800000)>>23), u4Tmp[1]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x550); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x522); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x550(bcn ctrl)/0x522", \ + u4Tmp[0], u1Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc50); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x49c); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0xc50(dig)/0x49c(null-drop)", \ + u4Tmp[0]&0xff, u1Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda0); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda4); + u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda8); + u4Tmp[3] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xcf0); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xa5b); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xa5c); + + faOfdm = ((u4Tmp[0]&0xffff0000) >> 16) + ((u4Tmp[1]&0xffff0000) >> 16) + (u4Tmp[1] & 0xffff) + (u4Tmp[2] & 0xffff) + \ + ((u4Tmp[3]&0xffff0000) >> 16) + (u4Tmp[3] & 0xffff) ; + faCck = (u1Tmp[0] << 8) + u1Tmp[1]; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "OFDM-CCA/OFDM-FA/CCK-FA", \ + u4Tmp[0]&0xffff, faOfdm, faCck); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", "CRC_OK CCK/11g/11n/11n-Agg", \ + pCoexSta->nCRCOK_CCK, pCoexSta->nCRCOK_11g, pCoexSta->nCRCOK_11n, pCoexSta->nCRCOK_11nAgg); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", "CRC_Err CCK/11g/11n/11n-Agg", \ + pCoexSta->nCRCErr_CCK, pCoexSta->nCRCErr_11g, pCoexSta->nCRCErr_11n, pCoexSta->nCRCErr_11nAgg); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c0); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c4); + u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c8); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x6cc); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", \ + u4Tmp[0], u4Tmp[1], u4Tmp[2], u1Tmp[0]); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x770(high-pri rx/tx)", \ + pCoexSta->highPriorityRx, pCoexSta->highPriorityTx); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x774(low-pri rx/tx)", \ + pCoexSta->lowPriorityRx, pCoexSta->lowPriorityTx); + CL_PRINTF(cliBuf); +#if(BT_AUTO_REPORT_ONLY_8821A_2ANT == 1) + //halbtc8821a2ant_MonitorBtCtr(pBtCoexist); +#endif + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + + +VOID +EXhalbtc8821a2ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_IPS_ENTER == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS ENTER notify\n")); + pCoexSta->bUnderIps = TRUE; + halbtc8821a2ant_WifiOffHwCfg(pBtCoexist); + halbtc8821a2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE); + halbtc8821a2ant_CoexAllOff(pBtCoexist); + } + else if(BTC_IPS_LEAVE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS LEAVE notify\n")); + pCoexSta->bUnderIps = FALSE; + halbtc8821a2ant_InitHwConfig(pBtCoexist, FALSE); + halbtc8821a2ant_InitCoexDm(pBtCoexist); + halbtc8821a2ant_QueryBtInfo(pBtCoexist); + } +} + +VOID +EXhalbtc8821a2ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_LPS_ENABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS ENABLE notify\n")); + pCoexSta->bUnderLps = TRUE; + } + else if(BTC_LPS_DISABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS DISABLE notify\n")); + pCoexSta->bUnderLps = FALSE; + } +} + +VOID +EXhalbtc8821a2ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + u1Byte u1Tmpa, u1Tmpb; + + u1Tmpa = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x765); + u1Tmpb = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x76e); + + if(BTC_SCAN_START == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n")); + } + else if(BTC_SCAN_FINISH == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n")); + } + + RT_TRACE(COMP_COEX, DBG_LOUD, ("############# [BTCoex], 0x765=0x%x, 0x76e=0x%x\n", u1Tmpa, u1Tmpb)); +} + +VOID +EXhalbtc8821a2ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_ASSOCIATE_START == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n")); + } + else if(BTC_ASSOCIATE_FINISH == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n")); + } +} + +VOID +EXhalbtc8821a2ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + u1Byte H2C_Parameter[3] ={0}; + u4Byte wifiBw; + u1Byte wifiCentralChnl; + u1Byte apNum=0; + + if(BTC_MEDIA_CONNECT == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA connect notify\n")); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA disconnect notify\n")); + } + + // only 2.4G we need to inform bt the chnl mask + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, &wifiCentralChnl); + if( (BTC_MEDIA_CONNECT == type) && + (wifiCentralChnl <= 14) ) + { + H2C_Parameter[0] = 0x1; + H2C_Parameter[1] = wifiCentralChnl; + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + H2C_Parameter[2] = 0x30; + else + { + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_AP_NUM, &apNum); + if(apNum < 10) + H2C_Parameter[2] = 0x30; + else + H2C_Parameter[2] = 0x20; + } + } + + pCoexDm->wifiChnlInfo[0] = H2C_Parameter[0]; + pCoexDm->wifiChnlInfo[1] = H2C_Parameter[1]; + pCoexDm->wifiChnlInfo[2] = H2C_Parameter[2]; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x66=0x%x\n", + H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x66, 3, H2C_Parameter); +} + +VOID +EXhalbtc8821a2ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(type == BTC_PACKET_DHCP) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], DHCP Packet notify\n")); + } +} + +VOID +EXhalbtc8821a2ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ) +{ + PBTC_BT_LINK_INFO pBtLinkInfo=&pBtCoexist->btLinkInfo; + u1Byte btInfo=0; + u1Byte i, rspSource=0; + BOOLEAN bBtBusy=FALSE, bLimitedDig=FALSE; + BOOLEAN bWifiConnected=FALSE, bWifiUnder5G=FALSE; + static BOOLEAN bPreScoExist=FALSE; + u4Byte raMask=0x0; + + pCoexSta->bC2hBtInfoReqSent = FALSE; + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_5G, &bWifiUnder5G); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + + rspSource = tmpBuf[0]&0xf; + if(rspSource >= BT_INFO_SRC_8821A_2ANT_MAX) + rspSource = BT_INFO_SRC_8821A_2ANT_WIFI_FW; + pCoexSta->btInfoC2hCnt[rspSource]++; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Bt info[%d], length=%d, hex data=[", rspSource, length)); + for(i=0; ibtInfoC2h[rspSource][i] = tmpBuf[i]; + if(i == 1) + btInfo = tmpBuf[i]; + if(i == length-1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x]\n", tmpBuf[i])); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x, ", tmpBuf[i])); + } + } + + if(pBtCoexist->bManualControl) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), return for Manual CTRL<===\n")); + return; + } + + // if 0xff, it means BT is under WHCK test + if (btInfo == 0xff) + pCoexSta->bBtWhckTest = TRUE; + else + pCoexSta->bBtWhckTest = FALSE; + + if(BT_INFO_SRC_8821A_2ANT_WIFI_FW != rspSource) + { + pCoexSta->btRetryCnt = // [3:0] + pCoexSta->btInfoC2h[rspSource][2]&0xf; + + pCoexSta->btRssi = + pCoexSta->btInfoC2h[rspSource][3]*2+10; + + pCoexSta->btInfoExt = + pCoexSta->btInfoC2h[rspSource][4]; + + pCoexSta->bBtTxRxMask = (pCoexSta->btInfoC2h[rspSource][2]&0x40); + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TX_RX_MASK, &pCoexSta->bBtTxRxMask); + if(pCoexSta->bBtTxRxMask) + { + /* BT into is responded by BT FW and BT RF REG 0x3C != 0x01 => Need to switch BT TRx Mask */ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Switch BT TRx Mask since BT RF REG 0x3C != 0x01\n")); + pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x3c, 0x01); + } + + // Here we need to resend some wifi info to BT + // because bt is reset and loss of the info. + if( (pCoexSta->btInfoExt & BIT1) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT ext info bit1 check, send wifi BW&Chnl to BT!!\n")); + if(bWifiConnected) + { + EXhalbtc8821a2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_CONNECT); + } + else + { + EXhalbtc8821a2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); + } + } + + + if(!pBtCoexist->bManualControl && !bWifiUnder5G) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT ext info = 0x%x!!\n", pCoexSta->btInfoExt)); + if( (pCoexSta->btInfoExt&BIT3) ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT ext info bit3=1, bWifiConnected=%d\n", bWifiConnected)); + if(bWifiConnected) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n")); + halbtc8821a2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE); + } + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT ext info bit3=0, bWifiConnected=%d\n", bWifiConnected)); + // BT already NOT ignore Wlan active, do nothing here. + if(!bWifiConnected) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT ext info bit3 check, set BT to ignore Wlan active!!\n")); + halbtc8821a2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE); + } + } + } + +#if(BT_AUTO_REPORT_ONLY_8821A_2ANT == 0) + if( (pCoexSta->btInfoExt & BIT4) ) + { + // BT auto report already enabled, do nothing + } + else + { + halbtc8821a2ant_BtAutoReport(pBtCoexist, FORCE_EXEC, TRUE); + } +#endif + } + + // check BIT2 first ==> check if bt is under inquiry or page scan + if(btInfo & BT_INFO_8821A_2ANT_B_INQ_PAGE) + pCoexSta->bC2hBtInquiryPage = TRUE; + else + pCoexSta->bC2hBtInquiryPage = FALSE; + + // set link exist status + if(!(btInfo&BT_INFO_8821A_2ANT_B_CONNECTION)) + { + pCoexSta->bBtLinkExist = FALSE; + pCoexSta->bPanExist = FALSE; + pCoexSta->bA2dpExist = FALSE; + pCoexSta->bHidExist = FALSE; + pCoexSta->bScoExist = FALSE; + } + else // connection exists + { + pCoexSta->bBtLinkExist = TRUE; + if(btInfo & BT_INFO_8821A_2ANT_B_FTP) + pCoexSta->bPanExist = TRUE; + else + pCoexSta->bPanExist = FALSE; + if(btInfo & BT_INFO_8821A_2ANT_B_A2DP) + pCoexSta->bA2dpExist = TRUE; + else + pCoexSta->bA2dpExist = FALSE; + if(btInfo & BT_INFO_8821A_2ANT_B_HID) + pCoexSta->bHidExist = TRUE; + else + pCoexSta->bHidExist = FALSE; + if(btInfo & BT_INFO_8821A_2ANT_B_SCO_ESCO) + pCoexSta->bScoExist = TRUE; + else + pCoexSta->bScoExist = FALSE; + + if ( (pCoexSta->bHidExist == FALSE) && (pCoexSta->bC2hBtInquiryPage == FALSE) && (pCoexSta->bScoExist == FALSE)) + { + if (pCoexSta->highPriorityTx + pCoexSta->highPriorityRx >= 160) + pCoexSta->bHidExist = TRUE; + } + } + + halbtc8821a2ant_UpdateBtLinkInfo(pBtCoexist); + + if(!(btInfo&BT_INFO_8821A_2ANT_B_CONNECTION)) + { + pCoexDm->btStatus = BT_8821A_2ANT_BT_STATUS_NON_CONNECTED_IDLE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Non-Connected idle!!!\n")); + } + else if(btInfo == BT_INFO_8821A_2ANT_B_CONNECTION) // connection exists but no busy + { + pCoexDm->btStatus = BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Connected-idle!!!\n")); + } + else if((btInfo&BT_INFO_8821A_2ANT_B_SCO_ESCO) || + (btInfo&BT_INFO_8821A_2ANT_B_SCO_BUSY)) + { + pCoexDm->btStatus = BT_8821A_2ANT_BT_STATUS_SCO_BUSY; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT SCO busy!!!\n")); + } + else if(btInfo&BT_INFO_8821A_2ANT_B_ACL_BUSY) + { + pCoexDm->btStatus = BT_8821A_2ANT_BT_STATUS_ACL_BUSY; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT ACL busy!!!\n")); + } + else + { + pCoexDm->btStatus = BT_8821A_2ANT_BT_STATUS_MAX; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BtInfoNotify(), BT Non-Defined state!!!\n")); + } + + if( (BT_8821A_2ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) || + (BT_8821A_2ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || + (BT_8821A_2ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) ) + { + bBtBusy = TRUE; + bLimitedDig = TRUE; + } + else + { + bBtBusy = FALSE; + bLimitedDig = FALSE; + } + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bBtBusy); + + pCoexDm->bLimitedDig = bLimitedDig; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_LIMITED_DIG, &bLimitedDig); + + halbtc8821a2ant_RunCoexistMechanism(pBtCoexist); +} + +VOID +EXhalbtc8821a2ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Halt notify\n")); + + halbtc8821a2ant_WifiOffHwCfg(pBtCoexist); + //remove due to interrupt is disabled that polling c2h will fail and delay 100ms. + //pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x3c, 0x15); //BT goto standby while GNT_BT 1-->0 + halbtc8821a2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE); + + EXhalbtc8821a2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); +} + +VOID +EXhalbtc8821a2ant_PnpNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte pnpState + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Pnp notify\n")); + + if(BTC_WIFI_PNP_SLEEP == pnpState) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Pnp notify to SLEEP\n")); + } + else if(BTC_WIFI_PNP_WAKE_UP == pnpState) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Pnp notify to WAKE UP\n")); + halbtc8821a2ant_InitHwConfig(pBtCoexist, FALSE); + halbtc8821a2ant_InitCoexDm(pBtCoexist); + halbtc8821a2ant_QueryBtInfo(pBtCoexist); + } +} + +VOID +EXhalbtc8821a2ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ) +{ + //static u1Byte disVerInfoCnt=0; + u4Byte fwVer=0, btPatchVer=0; + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ==========================Periodical===========================\n")); + + if(pCoexSta->disVerInfoCnt <= 5) + { + pCoexSta->disVerInfoCnt += 1; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ****************************************************************\n")); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Ant PG Num/ Ant Mech/ Ant Pos = %d/ %d/ %d\n", + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum, pBoardInfo->btdmAntPos)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT stack/ hci ext ver = %s / %d\n", + ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion)); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_BT_PATCH_VER, &btPatchVer); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CoexVer/ FwVer/ PatchVer = %d_%x/ 0x%x/ 0x%x(%d)\n", + GLCoexVerDate8821a2Ant, GLCoexVer8821a2Ant, fwVer, btPatchVer, btPatchVer)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ****************************************************************\n")); + + if (pCoexSta->disVerInfoCnt == 3) + { + //Antenna config to set 0x765 = 0x0 (GNT_BT control by PTA) after initial + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Set GNT_BT control by PTA\n")); + halbtc8821a2ant_SetAntPath(pBtCoexist, BTC_ANT_WIFI_AT_MAIN, FALSE, FALSE); + } + } + +#if(BT_AUTO_REPORT_ONLY_8821A_2ANT == 0) + halbtc8821a2ant_QueryBtInfo(pBtCoexist); + halbtc8821a2ant_MonitorBtEnableDisable(pBtCoexist); +#else + halbtc8821a2ant_MonitorBtCtr(pBtCoexist); + halbtc8821a2ant_MonitorWiFiCtr(pBtCoexist); + + if( halbtc8821a2ant_IsWifiStatusChanged(pBtCoexist) || + pCoexDm->bAutoTdmaAdjust) + { + halbtc8821a2ant_RunCoexistMechanism(pBtCoexist); + } +#endif +} + + +#endif + +#else // #if (RTL8821A_SUPPORT == 1) +VOID +EXhalbtc8821a2ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ){} +VOID +EXhalbtc8821a2ant_PreLoadFirmware( + IN PBTC_COEXIST pBtCoexist + ){} +VOID +EXhalbtc8821a2ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ){} +VOID +EXhalbtc8821a2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ){} +VOID +EXhalbtc8821a2ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ){} +VOID +EXhalbtc8821a2ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ){} +VOID +EXhalbtc8821a2ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ){} +VOID +EXhalbtc8821a2ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ){} +VOID +EXhalbtc8821a2ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ){} +VOID +EXhalbtc8821a2ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ){} +VOID +EXhalbtc8821a2ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ){} +VOID +EXhalbtc8821a2ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ){} +VOID +EXhalbtc8821a2ant_PnpNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte pnpState + ){} +VOID +EXhalbtc8821a2ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ){} +VOID +EXhalbtc8821a2ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ){} +#endif // #if (RTL8821A_SUPPORT == 1) \ No newline at end of file diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8821a2Ant.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8821a2Ant.h new file mode 100644 index 000000000..7964b3455 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8821a2Ant.h @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//=========================================== +// The following is for 8821A 2Ant BT Co-exist definition +//=========================================== +#define BT_AUTO_REPORT_ONLY_8821A_2ANT 1 + + +#define BT_INFO_8821A_2ANT_B_FTP BIT7 +#define BT_INFO_8821A_2ANT_B_A2DP BIT6 +#define BT_INFO_8821A_2ANT_B_HID BIT5 +#define BT_INFO_8821A_2ANT_B_SCO_BUSY BIT4 +#define BT_INFO_8821A_2ANT_B_ACL_BUSY BIT3 +#define BT_INFO_8821A_2ANT_B_INQ_PAGE BIT2 +#define BT_INFO_8821A_2ANT_B_SCO_ESCO BIT1 +#define BT_INFO_8821A_2ANT_B_CONNECTION BIT0 + +#define BTC_RSSI_COEX_THRESH_TOL_8821A_2ANT 2 + + +#define BT_8821A_2ANT_WIFI_RSSI_COEXSWITCH_THRES 42 //WiFi RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation +#define BT_8821A_2ANT_BT_RSSI_COEXSWITCH_THRES 46 //BT RSSI Threshold for 2-Ant TDMA/1-Ant PS-TDMA translation + +typedef enum _BT_INFO_SRC_8821A_2ANT{ + BT_INFO_SRC_8821A_2ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8821A_2ANT_BT_RSP = 0x1, + BT_INFO_SRC_8821A_2ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8821A_2ANT_MAX +}BT_INFO_SRC_8821A_2ANT,*PBT_INFO_SRC_8821A_2ANT; + +typedef enum _BT_8821A_2ANT_BT_STATUS{ + BT_8821A_2ANT_BT_STATUS_NON_CONNECTED_IDLE = 0x0, + BT_8821A_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8821A_2ANT_BT_STATUS_INQ_PAGE = 0x2, + BT_8821A_2ANT_BT_STATUS_ACL_BUSY = 0x3, + BT_8821A_2ANT_BT_STATUS_SCO_BUSY = 0x4, + BT_8821A_2ANT_BT_STATUS_ACL_SCO_BUSY = 0x5, + BT_8821A_2ANT_BT_STATUS_MAX +}BT_8821A_2ANT_BT_STATUS,*PBT_8821A_2ANT_BT_STATUS; + +typedef enum _BT_8821A_2ANT_COEX_ALGO{ + BT_8821A_2ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8821A_2ANT_COEX_ALGO_SCO = 0x1, + BT_8821A_2ANT_COEX_ALGO_HID = 0x2, + BT_8821A_2ANT_COEX_ALGO_A2DP = 0x3, + BT_8821A_2ANT_COEX_ALGO_A2DP_PANHS = 0x4, + BT_8821A_2ANT_COEX_ALGO_PANEDR = 0x5, + BT_8821A_2ANT_COEX_ALGO_PANHS = 0x6, + BT_8821A_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7, + BT_8821A_2ANT_COEX_ALGO_PANEDR_HID = 0x8, + BT_8821A_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, + BT_8821A_2ANT_COEX_ALGO_HID_A2DP = 0xa, + BT_8821A_2ANT_COEX_ALGO_MAX = 0xb, +}BT_8821A_2ANT_COEX_ALGO,*PBT_8821A_2ANT_COEX_ALGO; + +typedef struct _COEX_DM_8821A_2ANT{ + // fw mechanism + u1Byte preBtDecPwrLvl; + u1Byte curBtDecPwrLvl; + u1Byte preFwDacSwingLvl; + u1Byte curFwDacSwingLvl; + BOOLEAN bCurIgnoreWlanAct; + BOOLEAN bPreIgnoreWlanAct; + u1Byte prePsTdma; + u1Byte curPsTdma; + u1Byte psTdmaPara[5]; + u1Byte psTdmaDuAdjType; + BOOLEAN bResetTdmaAdjust; + BOOLEAN bAutoTdmaAdjust; + BOOLEAN bPrePsTdmaOn; + BOOLEAN bCurPsTdmaOn; + BOOLEAN bPreBtAutoReport; + BOOLEAN bCurBtAutoReport; + + // sw mechanism + BOOLEAN bPreRfRxLpfShrink; + BOOLEAN bCurRfRxLpfShrink; + u4Byte btRf0x1eBackup; + BOOLEAN bPreLowPenaltyRa; + BOOLEAN bCurLowPenaltyRa; + BOOLEAN bPreDacSwingOn; + u4Byte preDacSwingLvl; + BOOLEAN bCurDacSwingOn; + u4Byte curDacSwingLvl; + BOOLEAN bPreAdcBackOff; + BOOLEAN bCurAdcBackOff; + BOOLEAN bPreAgcTableEn; + BOOLEAN bCurAgcTableEn; + u4Byte preVal0x6c0; + u4Byte curVal0x6c0; + u4Byte preVal0x6c4; + u4Byte curVal0x6c4; + u4Byte preVal0x6c8; + u4Byte curVal0x6c8; + u1Byte preVal0x6cc; + u1Byte curVal0x6cc; + BOOLEAN bLimitedDig; + + // algorithm related + u1Byte preAlgorithm; + u1Byte curAlgorithm; + u1Byte btStatus; + u1Byte wifiChnlInfo[3]; + + BOOLEAN bNeedRecover0x948; + u4Byte backup0x948; + + u1Byte preLps; + u1Byte curLps; + u1Byte preRpwm; + u1Byte curRpwm; +} COEX_DM_8821A_2ANT, *PCOEX_DM_8821A_2ANT; + +typedef struct _COEX_STA_8821A_2ANT{ + BOOLEAN bBtLinkExist; + BOOLEAN bScoExist; + BOOLEAN bA2dpExist; + BOOLEAN bHidExist; + BOOLEAN bPanExist; + + BOOLEAN bUnderLps; + BOOLEAN bUnderIps; + u4Byte highPriorityTx; + u4Byte highPriorityRx; + u4Byte lowPriorityTx; + u4Byte lowPriorityRx; + u1Byte btRssi; + BOOLEAN bBtTxRxMask; + u1Byte preBtRssiState; + u1Byte preWifiRssiState[4]; + BOOLEAN bC2hBtInfoReqSent; + u1Byte btInfoC2h[BT_INFO_SRC_8821A_2ANT_MAX][10]; + u4Byte btInfoC2hCnt[BT_INFO_SRC_8821A_2ANT_MAX]; + BOOLEAN bBtWhckTest; + BOOLEAN bC2hBtInquiryPage; + u1Byte btRetryCnt; + u1Byte btInfoExt; + + u4Byte nCRCOK_CCK; + u4Byte nCRCOK_11g; + u4Byte nCRCOK_11n; + u4Byte nCRCOK_11nAgg; + + u4Byte nCRCErr_CCK; + u4Byte nCRCErr_11g; + u4Byte nCRCErr_11n; + u4Byte nCRCErr_11nAgg; + + u1Byte nCoexTableType; + BOOLEAN bForceLpsOn; + + u1Byte disVerInfoCnt; +}COEX_STA_8821A_2ANT, *PCOEX_STA_8821A_2ANT; + +//=========================================== +// The following is interface which will notify coex module. +//=========================================== +VOID +EXhalbtc8821a2ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8821a2ant_PreLoadFirmware( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8821a2ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ); +VOID +EXhalbtc8821a2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8821a2ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8821a2ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8821a2ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8821a2ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8821a2ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8821a2ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8821a2ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ); +VOID +EXhalbtc8821a2ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8821a2ant_PnpNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte pnpState + ); +VOID +EXhalbtc8821a2ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8821a2ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ); + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8821aCsr2Ant.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8821aCsr2Ant.c new file mode 100644 index 000000000..5a0145c3c --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8821aCsr2Ant.c @@ -0,0 +1,4344 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//============================================================ +// Description: +// +// This file is for RTL8821A_CSR_CSR Co-exist mechanism +// +// History +// 2012/08/22 Cosa first check in. +// 2012/11/14 Cosa Revise for 8821A_CSR 2Ant out sourcing. +// +//============================================================ + +//============================================================ +// include files +//============================================================ +#include "Mp_Precomp.h" + +#if WPP_SOFTWARE_TRACE +#include "HalBtcCsr8821a2Ant.tmh" +#endif + +#define _BTCOEX_CSR 1 + +#ifndef rtw_warn_on + #define rtw_warn_on(condition) do {} while (0) +#endif + +#if(BT_30_SUPPORT == 1) +//============================================================ +// Global variables, these are static variables +//============================================================ +static COEX_DM_8821A_CSR_2ANT GLCoexDm8821aCsr2Ant; +static PCOEX_DM_8821A_CSR_2ANT pCoexDm=&GLCoexDm8821aCsr2Ant; +static COEX_STA_8821A_CSR_2ANT GLCoexSta8821aCsr2Ant; +static PCOEX_STA_8821A_CSR_2ANT pCoexSta=&GLCoexSta8821aCsr2Ant; + +const char *const GLBtInfoSrc8821aCsr2Ant[]={ + "BT Info[wifi fw]", + "BT Info[bt rsp]", + "BT Info[bt auto report]", +}; + +u4Byte GLCoexVerDate8821aCsr2Ant=20140901; +u4Byte GLCoexVer8821aCsr2Ant=0x51; + +//============================================================ +// local function proto type if needed +//============================================================ +//============================================================ +// local function start with halbtc8821aCsr2ant_ +//============================================================ +u1Byte +halbtc8821aCsr2ant_BtRssiState( + u1Byte levelNum, + u1Byte rssiThresh, + u1Byte rssiThresh1 + ) +{ + s4Byte btRssi=0; + u1Byte btRssiState=pCoexSta->preBtRssiState; + + btRssi = pCoexSta->btRssi; + + if(levelNum == 2) + { + if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW)) + { + if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8821A_CSR_2ANT)) + { + btRssiState = BTC_RSSI_STATE_HIGH; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else + { + if(btRssi < rssiThresh) + { + btRssiState = BTC_RSSI_STATE_LOW; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + else if(levelNum == 3) + { + if(rssiThresh > rssiThresh1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT Rssi thresh error!!\n")); + return pCoexSta->preBtRssiState; + } + + if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW)) + { + if(btRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8821A_CSR_2ANT)) + { + btRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else if( (pCoexSta->preBtRssiState == BTC_RSSI_STATE_MEDIUM) || + (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_MEDIUM)) + { + if(btRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8821A_CSR_2ANT)) + { + btRssiState = BTC_RSSI_STATE_HIGH; + } + else if(btRssi < rssiThresh) + { + btRssiState = BTC_RSSI_STATE_LOW; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_MEDIUM; + } + } + else + { + if(btRssi < rssiThresh1) + { + btRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + btRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + + pCoexSta->preBtRssiState = btRssiState; + + return btRssiState; +} + +u1Byte +halbtc8821aCsr2ant_WifiRssiState( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte index, + IN u1Byte levelNum, + IN u1Byte rssiThresh, + IN u1Byte rssiThresh1 + ) +{ + s4Byte wifiRssi=0; + u1Byte wifiRssiState=pCoexSta->preWifiRssiState[index]; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); + + if(levelNum == 2) + { + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8821A_CSR_2ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else + { + if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + else if(levelNum == 3) + { + if(rssiThresh > rssiThresh1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], wifi RSSI thresh error!!\n")); + return pCoexSta->preWifiRssiState[index]; + } + + if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW)) + { + if(wifiRssi >= (rssiThresh+BTC_RSSI_COEX_THRESH_TOL_8821A_CSR_2ANT)) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_LOW; + } + } + else if( (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_MEDIUM) || + (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_MEDIUM)) + { + if(wifiRssi >= (rssiThresh1+BTC_RSSI_COEX_THRESH_TOL_8821A_CSR_2ANT)) + { + wifiRssiState = BTC_RSSI_STATE_HIGH; + } + else if(wifiRssi < rssiThresh) + { + wifiRssiState = BTC_RSSI_STATE_LOW; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_MEDIUM; + } + } + else + { + if(wifiRssi < rssiThresh1) + { + wifiRssiState = BTC_RSSI_STATE_MEDIUM; + } + else + { + wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; + } + } + } + + pCoexSta->preWifiRssiState[index] = wifiRssiState; + + return wifiRssiState; +} + +VOID +halbtc8821aCsr2ant_MonitorBtEnableDisable( + IN PBTC_COEXIST pBtCoexist + ) +{ + static BOOLEAN bPreBtDisabled=FALSE; + static u4Byte btDisableCnt=0; + BOOLEAN bBtActive=TRUE, bBtDisabled=FALSE; + + // This function check if bt is disabled + + if( pCoexSta->highPriorityTx == 0 && + pCoexSta->highPriorityRx == 0 && + pCoexSta->lowPriorityTx == 0 && + pCoexSta->lowPriorityRx == 0) + { + bBtActive = FALSE; + } + if( pCoexSta->highPriorityTx == 0xffff && + pCoexSta->highPriorityRx == 0xffff && + pCoexSta->lowPriorityTx == 0xffff && + pCoexSta->lowPriorityRx == 0xffff) + { + bBtActive = FALSE; + } + if(bBtActive) + { + btDisableCnt = 0; + bBtDisabled = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is enabled !!\n")); + } + else + { + btDisableCnt++; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], bt all counters=0, %d times!!\n", + btDisableCnt)); + if(btDisableCnt >= 2) + { + bBtDisabled = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_DISABLE, &bBtDisabled); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is disabled !!\n")); + } + } + if(bPreBtDisabled != bBtDisabled) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is from %s to %s!!\n", + (bPreBtDisabled ? "disabled":"enabled"), + (bBtDisabled ? "disabled":"enabled"))); + bPreBtDisabled = bBtDisabled; + if(!bBtDisabled) + { + } + else + { + } + } +} + +VOID +halbtc8821aCsr2ant_MonitorBtCtr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u4Byte regHPTxRx, regLPTxRx, u4Tmp; + u4Byte regHPTx=0, regHPRx=0, regLPTx=0, regLPRx=0; + u1Byte u1Tmp; + + regHPTxRx = 0x770; + regLPTxRx = 0x774; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regHPTxRx); + regHPTx = u4Tmp & bMaskLWord; + regHPRx = (u4Tmp & bMaskHWord)>>16; + + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regLPTxRx); + regLPTx = u4Tmp & bMaskLWord; + regLPRx = (u4Tmp & bMaskHWord)>>16; + + pCoexSta->highPriorityTx = regHPTx; + pCoexSta->highPriorityRx = regHPRx; + pCoexSta->lowPriorityTx = regLPTx; + pCoexSta->lowPriorityRx = regLPRx; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], High Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", + regHPTxRx, regHPTx, regHPTx, regHPRx, regHPRx)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Low Priority Tx/Rx (reg 0x%x)=0x%x(%d)/0x%x(%d)\n", + regLPTxRx, regLPTx, regLPTx, regLPRx, regLPRx)); + + // reset counter + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0x5d); +} + +VOID +halbtc8821aCsr2ant_UpdateRaMask( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u4Byte disRateMask + ) +{ + pCoexDm->curRaMask = disRateMask; + + if( bForceExec || (pCoexDm->preRaMask != pCoexDm->curRaMask)) + { + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_UPDATE_RAMASK, &pCoexDm->curRaMask); + } + pCoexDm->preRaMask = pCoexDm->curRaMask; +} + +VOID +halbtc8821aCsr2ant_AutoRateFallbackRetry( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + BOOLEAN bWifiUnderBMode=FALSE; + + pCoexDm->curArfrType = type; + + if( bForceExec || (pCoexDm->preArfrType != pCoexDm->curArfrType)) + { + switch(pCoexDm->curArfrType) + { + case 0: // normal mode + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x430, pCoexDm->backupArfrCnt1); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x434, pCoexDm->backupArfrCnt2); + break; + case 1: + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, &bWifiUnderBMode); + if(bWifiUnderBMode) + { + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x430, 0x0); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x434, 0x01010101); + } + else + { + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x430, 0x0); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x434, 0x04030201); + } + break; + default: + break; + } + } + + pCoexDm->preArfrType = pCoexDm->curArfrType; +} + +VOID +halbtc8821aCsr2ant_RetryLimit( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + pCoexDm->curRetryLimitType = type; + + if( bForceExec || (pCoexDm->preRetryLimitType != pCoexDm->curRetryLimitType)) + { + switch(pCoexDm->curRetryLimitType) + { + case 0: // normal mode + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x42a, pCoexDm->backupRetryLimit); + break; + case 1: // retry limit=8 + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x42a, 0x0808); + break; + default: + break; + } + } + + pCoexDm->preRetryLimitType = pCoexDm->curRetryLimitType; +} + +VOID +halbtc8821aCsr2ant_AmpduMaxTime( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + pCoexDm->curAmpduTimeType = type; + + if( bForceExec || (pCoexDm->preAmpduTimeType != pCoexDm->curAmpduTimeType)) + { + switch(pCoexDm->curAmpduTimeType) + { + case 0: // normal mode + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x456, pCoexDm->backupAmpduMaxTime); + break; + case 1: // AMPDU timw = 0x38 * 32us + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x456, 0x38); + break; + case 2: + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x456, 0x17); + break; + default: + break; + } + } + + pCoexDm->preAmpduTimeType = pCoexDm->curAmpduTimeType; +} + +VOID +halbtc8821aCsr2Ant_AmpduMaxNum( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte type + ) +{ + pCoexDm->curAmpduNumType = type; + + if( bForceExec || (pCoexDm->preAmpduNumType != pCoexDm->curAmpduNumType)) + { + switch(pCoexDm->curAmpduNumType) + { + case 0: // normal mode + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x4ca, pCoexDm->backupAmpduMaxNum); + break; + case 1: + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x4ca, 0x0808); + break; + case 2: + pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x4ca, 0x1f1f); + break; + default: + break; + } + } + + pCoexDm->preAmpduNumType = pCoexDm->curAmpduNumType; + +} + +VOID +halbtc8821aCsr2ant_LimitedTx( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte raMaskType, + IN u1Byte arfrType, + IN u1Byte retryLimitType, + IN u1Byte ampduTimeType, + IN u1Byte ampduNumType + ) +{ + switch(raMaskType) + { + case 0: // normal mode + halbtc8821aCsr2ant_UpdateRaMask(pBtCoexist, bForceExec, 0x0); + break; + case 1: // disable cck 1/2 + halbtc8821aCsr2ant_UpdateRaMask(pBtCoexist, bForceExec, 0x00000003); + break; + case 2: // disable cck 1/2/5.5, ofdm 6/9/12/18/24, mcs 0/1/2/3/4 + halbtc8821aCsr2ant_UpdateRaMask(pBtCoexist, bForceExec, 0x0001f1f7); + break; + default: + break; + } + + halbtc8821aCsr2ant_AutoRateFallbackRetry(pBtCoexist, bForceExec, arfrType); + halbtc8821aCsr2ant_RetryLimit(pBtCoexist, bForceExec, retryLimitType); + halbtc8821aCsr2ant_AmpduMaxTime(pBtCoexist, bForceExec, ampduTimeType); + halbtc8821aCsr2Ant_AmpduMaxNum(pBtCoexist, bForceExec, ampduNumType); +} + + + +VOID +halbtc8821aCsr2ant_LimitedRx( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bRejApAggPkt, + IN BOOLEAN bBtCtrlAggBufSize, + IN u1Byte aggBufSize + ) +{ + BOOLEAN bRejectRxAgg=bRejApAggPkt; + BOOLEAN bBtCtrlRxAggSize=bBtCtrlAggBufSize; + u1Byte rxAggSize=aggBufSize; + + //============================================ + // Rx Aggregation related setting + //============================================ + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, &bRejectRxAgg); + // decide BT control aggregation buf size or not + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, &bBtCtrlRxAggSize); + // aggregation buf size, only work when BT control Rx aggregation size. + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_AGG_BUF_SIZE, &rxAggSize); + // real update aggregation setting + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); +} + +VOID +halbtc8821aCsr2ant_QueryBtInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + pCoexSta->bC2hBtInfoReqSent = TRUE; + + H2C_Parameter[0] |= BIT0; // trigger + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Query Bt Info, FW write 0x61=0x%x\n", + H2C_Parameter[0])); + + rtw_warn_on(_BTCOEX_CSR); + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x61, 1, H2C_Parameter); +} + +u1Byte +halbtc8821aCsr2ant_ActionAlgorithm( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + BOOLEAN bBtHsOn=FALSE; + u1Byte algorithm=BT_8821A_CSR_2ANT_COEX_ALGO_UNDEFINED; + u1Byte numOfDiffProfile=0; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + //sync StackInfo with BT firmware and stack + pStackInfo->bHidExist = pCoexSta->bHidExist; + pStackInfo->bBtLinkExist = pCoexSta->bBtLinkExist; + pStackInfo->bScoExist = pCoexSta->bScoExist; + pStackInfo->bPanExist = pCoexSta->bPanExist; + pStackInfo->bA2dpExist = pCoexSta->bA2dpExist; + + if(!pStackInfo->bBtLinkExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], No profile exists!!!\n")); + return algorithm; + } + + if(pStackInfo->bScoExist) + numOfDiffProfile++; + if(pStackInfo->bHidExist) + numOfDiffProfile++; + if(pStackInfo->bPanExist) + numOfDiffProfile++; + if(pStackInfo->bA2dpExist) + numOfDiffProfile++; + + if(numOfDiffProfile == 1) + { + if(pStackInfo->bScoExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO only\n")); + algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_SCO; + } + else + { + if(pStackInfo->bHidExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID only\n")); + algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_HID; + } + else if(pStackInfo->bA2dpExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP only\n")); + algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_A2DP; + } + else if(pStackInfo->bPanExist) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN(HS) only\n")); + algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_PANHS; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PAN(EDR) only\n")); + algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR; + } + } + } + } + else if(numOfDiffProfile == 2) + { + if(pStackInfo->bScoExist) + { + if(pStackInfo->bHidExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID\n")); + algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID; + } + else if(pStackInfo->bA2dpExist) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + A2DP ==> SCO\n")); + algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID; + } + else if(pStackInfo->bPanExist) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + PAN(HS)\n")); + algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_SCO; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + PAN(EDR)\n")); + algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID; + } + } + } + else + { + if( pStackInfo->bHidExist && + pStackInfo->bA2dpExist ) + { + if(pStackInfo->numOfHid >= 2) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID*2 + A2DP\n")); + algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP\n")); + algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP; + } + } + else if( pStackInfo->bHidExist && + pStackInfo->bPanExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + PAN(HS)\n")); + algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_HID; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + PAN(EDR)\n")); + algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID; + } + } + else if( pStackInfo->bPanExist && + pStackInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP + PAN(HS)\n")); + algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_A2DP_PANHS; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], A2DP + PAN(EDR)\n")); + algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_A2DP; + } + } + } + } + else if(numOfDiffProfile == 3) + { + if(pStackInfo->bScoExist) + { + if( pStackInfo->bHidExist && + pStackInfo->bA2dpExist ) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + A2DP ==> HID\n")); + algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID; + } + else if( pStackInfo->bHidExist && + pStackInfo->bPanExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + PAN(HS)\n")); + algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + PAN(EDR)\n")); + algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID; + } + } + else if( pStackInfo->bPanExist && + pStackInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + A2DP + PAN(HS)\n")); + algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + A2DP + PAN(EDR) ==> HID\n")); + algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID; + } + } + } + else + { + if( pStackInfo->bHidExist && + pStackInfo->bPanExist && + pStackInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP + PAN(HS)\n")); + algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], HID + A2DP + PAN(EDR)\n")); + algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP_PANEDR; + } + } + } + } + else if(numOfDiffProfile >= 3) + { + if(pStackInfo->bScoExist) + { + if( pStackInfo->bHidExist && + pStackInfo->bPanExist && + pStackInfo->bA2dpExist ) + { + if(bBtHsOn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Error!!! SCO + HID + A2DP + PAN(HS)\n")); + + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCO + HID + A2DP + PAN(EDR)==>PAN(EDR)+HID\n")); + algorithm = BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID; + } + } + } + } + + return algorithm; +} + +BOOLEAN +halbtc8821aCsr2ant_NeedToDecBtPwr( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bRet=FALSE; + BOOLEAN bBtHsOn=FALSE, bWifiConnected=FALSE; + s4Byte btHsRssi=0; + u1Byte btRssiState; + + if(!pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn)) + return FALSE; + if(!pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected)) + return FALSE; + if(!pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_HS_RSSI, &btHsRssi)) + return FALSE; + + btRssiState = halbtc8821aCsr2ant_BtRssiState(2, 35, 0); + + if(bWifiConnected) + { + if(bBtHsOn) + { + if(btHsRssi > 37) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Need to decrease bt power for HS mode!!\n")); + bRet = TRUE; + } + } + else + { + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Need to decrease bt power for Wifi is connected!!\n")); + bRet = TRUE; + } + } + } + + return bRet; +} + +VOID +halbtc8821aCsr2ant_SetFwDacSwingLevel( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte dacSwingLvl + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + // There are several type of dacswing + // 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 + H2C_Parameter[0] = dacSwingLvl; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Set Dac Swing Level=0x%x\n", dacSwingLvl)); + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x64=0x%x\n", H2C_Parameter[0])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x64, 1, H2C_Parameter); +} + +VOID +halbtc8821aCsr2ant_SetFwDecBtPwr( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bDecBtPwr + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + H2C_Parameter[0] = 0; + + if(bDecBtPwr) + { + H2C_Parameter[0] |= BIT1; + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], decrease Bt Power : %s, FW write 0x62=0x%x\n", + (bDecBtPwr? "Yes!!":"No!!"), H2C_Parameter[0])); + + rtw_warn_on(_BTCOEX_CSR); + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x62, 1, H2C_Parameter); +} + +VOID +halbtc8821aCsr2ant_DecBtPwr( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bDecBtPwr + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s Dec BT power = %s\n", + (bForceExec? "force to":""), ((bDecBtPwr)? "ON":"OFF"))); + pCoexDm->bCurDecBtPwr = bDecBtPwr; + + if(!bForceExec) + { + if(pCoexDm->bPreDecBtPwr == pCoexDm->bCurDecBtPwr) + return; + } + + /* TODO: may CSR consider to decrease BT power? */ + //halbtc8821aCsr2ant_SetFwDecBtPwr(pBtCoexist, pCoexDm->bCurDecBtPwr); + + pCoexDm->bPreDecBtPwr = pCoexDm->bCurDecBtPwr; +} + +VOID +halbtc8821aCsr2ant_SetBtAutoReport( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bEnableAutoReport + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + H2C_Parameter[0] = 0; + + if(bEnableAutoReport) + { + H2C_Parameter[0] |= BIT0; + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], BT FW auto report : %s, FW write 0x68=0x%x\n", + (bEnableAutoReport? "Enabled!!":"Disabled!!"), H2C_Parameter[0])); + + rtw_warn_on(_BTCOEX_CSR); + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x68, 1, H2C_Parameter); +} + +VOID +halbtc8821aCsr2ant_BtAutoReport( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bEnableAutoReport + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s BT Auto report = %s\n", + (bForceExec? "force to":""), ((bEnableAutoReport)? "Enabled":"Disabled"))); + pCoexDm->bCurBtAutoReport = bEnableAutoReport; + + if(!bForceExec) + { + if(pCoexDm->bPreBtAutoReport == pCoexDm->bCurBtAutoReport) + return; + } + //halbtc8821aCsr2ant_SetBtAutoReport(pBtCoexist, pCoexDm->bCurBtAutoReport); + + pCoexDm->bPreBtAutoReport = pCoexDm->bCurBtAutoReport; +} + +VOID +halbtc8821aCsr2ant_FwDacSwingLvl( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u1Byte fwDacSwingLvl + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s set FW Dac Swing level = %d\n", + (bForceExec? "force to":""), fwDacSwingLvl)); + pCoexDm->curFwDacSwingLvl = fwDacSwingLvl; + + if(!bForceExec) + { + if(pCoexDm->preFwDacSwingLvl == pCoexDm->curFwDacSwingLvl) + return; + } + + halbtc8821aCsr2ant_SetFwDacSwingLevel(pBtCoexist, pCoexDm->curFwDacSwingLvl); + + pCoexDm->preFwDacSwingLvl = pCoexDm->curFwDacSwingLvl; +} + +VOID +halbtc8821aCsr2ant_SetSwRfRxLpfCorner( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bRxRfShrinkOn + ) +{ + if(bRxRfShrinkOn) + { + //Shrink RF Rx LPF corner + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Shrink RF Rx LPF corner!!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, 0xffffc); + } + else + { + //Resume RF Rx LPF corner + // After initialized, we can use pCoexDm->btRf0x1eBackup + if(pBtCoexist->bInitilized) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Resume RF Rx LPF corner!!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, pCoexDm->btRf0x1eBackup); + } + } +} + +VOID +halbtc8821aCsr2ant_RfShrink( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bRxRfShrinkOn + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Rx RF Shrink = %s\n", + (bForceExec? "force to":""), ((bRxRfShrinkOn)? "ON":"OFF"))); + pCoexDm->bCurRfRxLpfShrink = bRxRfShrinkOn; + + if(!bForceExec) + { + if(pCoexDm->bPreRfRxLpfShrink == pCoexDm->bCurRfRxLpfShrink) + return; + } + halbtc8821aCsr2ant_SetSwRfRxLpfCorner(pBtCoexist, pCoexDm->bCurRfRxLpfShrink); + + pCoexDm->bPreRfRxLpfShrink = pCoexDm->bCurRfRxLpfShrink; +} + +VOID +halbtc8821aCsr2ant_SetSwPenaltyTxRateAdaptive( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bLowPenaltyRa + ) +{ + u1Byte H2C_Parameter[6] ={0}; + + H2C_Parameter[0] = 0x6; // opCode, 0x6= Retry_Penalty + + if(bLowPenaltyRa) + { + H2C_Parameter[1] |= BIT0; + H2C_Parameter[2] = 0x00; //normal rate except MCS7/6/5, OFDM54/48/36 + H2C_Parameter[3] = 0xf7; //MCS7 or OFDM54 + H2C_Parameter[4] = 0xf8; //MCS6 or OFDM48 + H2C_Parameter[5] = 0xf9; //MCS5 or OFDM36 + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set WiFi Low-Penalty Retry: %s", + (bLowPenaltyRa? "ON!!":"OFF!!") )); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x69, 6, H2C_Parameter); +} + +VOID +halbtc8821aCsr2ant_LowPenaltyRa( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bLowPenaltyRa + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn LowPenaltyRA = %s\n", + (bForceExec? "force to":""), ((bLowPenaltyRa)? "ON":"OFF"))); + pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa; + + if(!bForceExec) + { + if(pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa) + return; + } + halbtc8821aCsr2ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa); + + pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa; +} + +VOID +halbtc8821aCsr2ant_SetDacSwingReg( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte level + ) +{ + u1Byte val=(u1Byte)level; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Write SwDacSwing = 0x%x\n", level)); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xc5b, 0x3e, val); +} + +VOID +halbtc8821aCsr2ant_SetSwFullTimeDacSwing( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bSwDacSwingOn, + IN u4Byte swDacSwingLvl + ) +{ + if(bSwDacSwingOn) + { + halbtc8821aCsr2ant_SetDacSwingReg(pBtCoexist, swDacSwingLvl); + } + else + { + halbtc8821aCsr2ant_SetDacSwingReg(pBtCoexist, 0x18); + } +} + + +VOID +halbtc8821aCsr2ant_DacSwing( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bDacSwingOn, + IN u4Byte dacSwingLvl + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn DacSwing=%s, dacSwingLvl=0x%x\n", + (bForceExec? "force to":""), ((bDacSwingOn)? "ON":"OFF"), dacSwingLvl)); + pCoexDm->bCurDacSwingOn = bDacSwingOn; + pCoexDm->curDacSwingLvl = dacSwingLvl; + + if(!bForceExec) + { + if( (pCoexDm->bPreDacSwingOn == pCoexDm->bCurDacSwingOn) && + (pCoexDm->preDacSwingLvl == pCoexDm->curDacSwingLvl) ) + return; + } + delay_ms(30); + halbtc8821aCsr2ant_SetSwFullTimeDacSwing(pBtCoexist, bDacSwingOn, dacSwingLvl); + + pCoexDm->bPreDacSwingOn = pCoexDm->bCurDacSwingOn; + pCoexDm->preDacSwingLvl = pCoexDm->curDacSwingLvl; +} + +VOID +halbtc8821aCsr2ant_SetAdcBackOff( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bAdcBackOff + ) +{ + if(bAdcBackOff) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level On!\n")); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x8db, 0x60, 0x3); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BB BackOff Level Off!\n")); + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x8db, 0x60, 0x1); + } +} + +VOID +halbtc8821aCsr2ant_AdcBackOff( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bAdcBackOff + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn AdcBackOff = %s\n", + (bForceExec? "force to":""), ((bAdcBackOff)? "ON":"OFF"))); + pCoexDm->bCurAdcBackOff = bAdcBackOff; + + if(!bForceExec) + { + if(pCoexDm->bPreAdcBackOff == pCoexDm->bCurAdcBackOff) + return; + } + halbtc8821aCsr2ant_SetAdcBackOff(pBtCoexist, pCoexDm->bCurAdcBackOff); + + pCoexDm->bPreAdcBackOff = pCoexDm->bCurAdcBackOff; +} + +VOID +halbtc8821aCsr2ant_SetAgcTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bAgcTableEn + ) +{ + u1Byte rssiAdjustVal=0; + + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000); + if(bAgcTableEn) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table On!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x28F4B); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x10AB2); + rssiAdjustVal = 8; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Agc Table Off!\n")); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x2884B); + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x104B2); + } + pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xef, 0xfffff, 0x0); + + // set rssiAdjustVal for wifi module. + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, &rssiAdjustVal); +} + +VOID +halbtc8821aCsr2ant_AgcTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bAgcTableEn + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s %s Agc Table\n", + (bForceExec? "force to":""), ((bAgcTableEn)? "Enable":"Disable"))); + pCoexDm->bCurAgcTableEn = bAgcTableEn; + + if(!bForceExec) + { + if(pCoexDm->bPreAgcTableEn == pCoexDm->bCurAgcTableEn) + return; + } + halbtc8821aCsr2ant_SetAgcTable(pBtCoexist, bAgcTableEn); + + pCoexDm->bPreAgcTableEn = pCoexDm->bCurAgcTableEn; +} + +VOID +halbtc8821aCsr2ant_SetCoexTable( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte val0x6c0, + IN u4Byte val0x6c4, + IN u4Byte val0x6c8, + IN u1Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c0=0x%x\n", val0x6c0)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c0, val0x6c0); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c4=0x%x\n", val0x6c4)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c4, val0x6c4); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6c8=0x%x\n", val0x6c8)); + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, val0x6c8); + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set coex table, set 0x6cc=0x%x\n", val0x6cc)); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cc, val0x6cc); +} + +VOID +halbtc8821aCsr2ant_CoexTable( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN u4Byte val0x6c0, + IN u4Byte val0x6c4, + IN u4Byte val0x6c8, + IN u1Byte val0x6cc + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s write Coex Table 0x6c0=0x%x, 0x6c4=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n", + (bForceExec? "force to":""), val0x6c0, val0x6c4, val0x6c8, val0x6cc)); + pCoexDm->curVal0x6c0 = val0x6c0; + pCoexDm->curVal0x6c4 = val0x6c4; + pCoexDm->curVal0x6c8 = val0x6c8; + pCoexDm->curVal0x6cc = val0x6cc; + + if(!bForceExec) + { + if( (pCoexDm->preVal0x6c0 == pCoexDm->curVal0x6c0) && + (pCoexDm->preVal0x6c4 == pCoexDm->curVal0x6c4) && + (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) && + (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) ) + return; + } + halbtc8821aCsr2ant_SetCoexTable(pBtCoexist, val0x6c0, val0x6c4, val0x6c8, val0x6cc); + + pCoexDm->preVal0x6c0 = pCoexDm->curVal0x6c0; + pCoexDm->preVal0x6c4 = pCoexDm->curVal0x6c4; + pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8; + pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc; +} + +VOID +halbtc8821aCsr2ant_SetFwIgnoreWlanAct( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bEnable + ) +{ + u1Byte H2C_Parameter[1] ={0}; + + if(bEnable) + { + H2C_Parameter[0] |= BIT0; // function enable + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], set FW for BT Ignore Wlan_Act, FW write 0x63=0x%x\n", + H2C_Parameter[0])); + + rtw_warn_on(_BTCOEX_CSR); + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x63, 1, H2C_Parameter); +} + +VOID +halbtc8821aCsr2ant_IgnoreWlanAct( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bEnable + ) +{ + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn Ignore WlanAct %s\n", + (bForceExec? "force to":""), (bEnable? "ON":"OFF"))); + pCoexDm->bCurIgnoreWlanAct = bEnable; + + if(!bForceExec) + { + if(pCoexDm->bPreIgnoreWlanAct == pCoexDm->bCurIgnoreWlanAct) + return; + } + //halbtc8821aCsr2ant_SetFwIgnoreWlanAct(pBtCoexist, bEnable); + + pCoexDm->bPreIgnoreWlanAct = pCoexDm->bCurIgnoreWlanAct; +} + +VOID +halbtc8821aCsr2ant_SetFwPstdma( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte byte1, + IN u1Byte byte2, + IN u1Byte byte3, + IN u1Byte byte4, + IN u1Byte byte5 + ) +{ + u1Byte H2C_Parameter[6] ={0}; + + H2C_Parameter[0] = byte1; + H2C_Parameter[1] = byte2; + H2C_Parameter[2] = byte3; + H2C_Parameter[3] = byte4; + H2C_Parameter[4] = byte5; + H2C_Parameter[5] = 0x01; + + pCoexDm->psTdmaPara[0] = byte1; + pCoexDm->psTdmaPara[1] = byte2; + pCoexDm->psTdmaPara[2] = byte3; + pCoexDm->psTdmaPara[3] = byte4; + pCoexDm->psTdmaPara[4] = byte5; + pCoexDm->psTdmaPara[5] = 0x01; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x60(6bytes)=0x%x%08x%02x\n", + H2C_Parameter[0], + H2C_Parameter[1]<<24|H2C_Parameter[2]<<16|H2C_Parameter[3]<<8|H2C_Parameter[4], H2C_Parameter[5])); + + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x60, 6, H2C_Parameter); +} + +VOID +halbtc8821aCsr2ant_SwMechanism1( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bShrinkRxLPF, + IN BOOLEAN bLowPenaltyRA, + IN BOOLEAN bLimitedDIG, + IN BOOLEAN bBTLNAConstrain + ) +{ + u4Byte wifiBw; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if(BTC_WIFI_BW_HT40 != wifiBw) //only shrink RF Rx LPF for HT40 + { + if (bShrinkRxLPF) + bShrinkRxLPF = FALSE; + } + + halbtc8821aCsr2ant_RfShrink(pBtCoexist, NORMAL_EXEC, bShrinkRxLPF); + halbtc8821aCsr2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, bLowPenaltyRA); + + //no limited DIG + //halbtc8821aCsr2ant_SetBtLnaConstrain(pBtCoexist, NORMAL_EXEC, bBTLNAConstrain); +} + +VOID +halbtc8821aCsr2ant_SwMechanism2( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bAGCTableShift, + IN BOOLEAN bADCBackOff, + IN BOOLEAN bSWDACSwing, + IN u4Byte dacSwingLvl + ) +{ + //halbtc8821aCsr2ant_AgcTable(pBtCoexist, NORMAL_EXEC, bAGCTableShift); + halbtc8821aCsr2ant_AdcBackOff(pBtCoexist, NORMAL_EXEC, bADCBackOff); + halbtc8821aCsr2ant_DacSwing(pBtCoexist, NORMAL_EXEC, bSWDACSwing, dacSwingLvl); +} + +VOID +halbtc8821aCsr2ant_SetAntPath( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte antPosType, + IN BOOLEAN bInitHwCfg, + IN BOOLEAN bWifiOff + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + u4Byte u4Tmp=0; + u1Byte H2C_Parameter[2] ={0}; + + if(bInitHwCfg) + { + // 0x4c[23]=0, 0x4c[24]=1 Antenna control by WL/BT + u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x4c); + u4Tmp &=~BIT23; + u4Tmp |= BIT24; + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x4c, u4Tmp); + + pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x974, 0x3ff); + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0xcb4, 0x77); + + if(pBoardInfo->btdmAntPos == BTC_ANTENNA_AT_MAIN_PORT) + { + //tell firmware "antenna inverse" ==> WRONG firmware antenna control code.==>need fw to fix + H2C_Parameter[0] = 1; + H2C_Parameter[1] = 1; + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x65, 2, H2C_Parameter); + } + else + { + //tell firmware "no antenna inverse" ==> WRONG firmware antenna control code.==>need fw to fix + H2C_Parameter[0] = 0; + H2C_Parameter[1] = 1; + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x65, 2, H2C_Parameter); + } + } + + // ext switch setting + switch(antPosType) + { + case BTC_ANT_WIFI_AT_MAIN: + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xcb7, 0x30, 0x1); + break; + case BTC_ANT_WIFI_AT_AUX: + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xcb7, 0x30, 0x2); + break; + } +} + +VOID +halbtc8821aCsr2ant_PsTdma( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bForceExec, + IN BOOLEAN bTurnOn, + IN u1Byte type + ) +{ + BOOLEAN bTurnOnByCnt=FALSE; + u1Byte psTdmaTypeByCnt=0; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], %s turn %s PS TDMA, type=%d\n", + (bForceExec? "force to":""), (bTurnOn? "ON":"OFF"), type)); + pCoexDm->bCurPsTdmaOn = bTurnOn; + pCoexDm->curPsTdma = type; + + if(!bForceExec) + { + if( (pCoexDm->bPrePsTdmaOn == pCoexDm->bCurPsTdmaOn) && + (pCoexDm->prePsTdma == pCoexDm->curPsTdma) ) + return; + } + if(bTurnOn) + { + switch(type) + { + case 1: + default: + halbtc8821aCsr2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); + break; + case 2: + halbtc8821aCsr2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0xe1, 0x90); + break; + case 3: + halbtc8821aCsr2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1c, 0x3, 0xf1, 0x90); + break; + case 4: + halbtc8821aCsr2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x10, 0x03, 0xf1, 0x90); + break; + case 5: + halbtc8821aCsr2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x90); + break; + case 6: + halbtc8821aCsr2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0x60, 0x90); + break; + case 7: + halbtc8821aCsr2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1c, 0x3, 0x70, 0x90); + break; + case 8: + halbtc8821aCsr2ant_SetFwPstdma(pBtCoexist, 0xa3, 0x10, 0x3, 0x70, 0x90); + break; + case 9: + halbtc8821aCsr2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); + break; + case 10: + halbtc8821aCsr2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0xe1, 0x90); + break; + case 11: + halbtc8821aCsr2ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0xa, 0xe1, 0x90); + break; + case 12: + halbtc8821aCsr2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0xe1, 0x90); + break; + case 13: + halbtc8821aCsr2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x90); + break; + case 14: + halbtc8821aCsr2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0x60, 0x90); + break; + case 15: + halbtc8821aCsr2ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0xa, 0x60, 0x90); + break; + case 16: + halbtc8821aCsr2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0x60, 0x90); + break; + case 17: + halbtc8821aCsr2ant_SetFwPstdma(pBtCoexist, 0xa3, 0x2f, 0x2f, 0x60, 0x90); + break; + case 18: + halbtc8821aCsr2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0xe1, 0x90); + break; + case 19: + halbtc8821aCsr2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x25, 0xe1, 0x90); + break; + case 20: + halbtc8821aCsr2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x25, 0x60, 0x90); + break; + case 21: + halbtc8821aCsr2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x15, 0x03, 0x70, 0x90); + break; + case 22: //ad2dp master + halbtc8821aCsr2ant_SetFwPstdma(pBtCoexist, 0xeb, 0x11, 0x11, 0x21, 0x10); + break; + case 23: //a2dp slave + halbtc8821aCsr2ant_SetFwPstdma(pBtCoexist, 0xeb, 0x12, 0x12, 0x20, 0x10); + break; + case 71: + halbtc8821aCsr2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); + break; + } + } + else + { + // disable PS tdma + switch(type) + { + case 0: + halbtc8821aCsr2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x40, 0x0); + break; + case 1: + halbtc8821aCsr2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x48, 0x0); + break; + default: + halbtc8821aCsr2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x40, 0x0); + break; + } + } + + // update pre state + pCoexDm->bPrePsTdmaOn = pCoexDm->bCurPsTdmaOn; + pCoexDm->prePsTdma = pCoexDm->curPsTdma; +} + +VOID +halbtc8821aCsr2ant_CoexAllOff( + IN PBTC_COEXIST pBtCoexist + ) +{ + // fw all off + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + halbtc8821aCsr2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + + // sw all off + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + + // hw all off + halbtc8821aCsr2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x55555555, 0xffff, 0x3); +} + +VOID +halbtc8821aCsr2ant_CoexUnder5G( + IN PBTC_COEXIST pBtCoexist + ) +{ + halbtc8821aCsr2ant_CoexAllOff(pBtCoexist); + + halbtc8821aCsr2ant_IgnoreWlanAct(pBtCoexist, NORMAL_EXEC, TRUE); +} + +VOID +halbtc8821aCsr2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + // force to reset coex mechanism + halbtc8821aCsr2ant_CoexTable(pBtCoexist, FORCE_EXEC, 0x55555555, 0x55555555, 0xffff, 0x3); + + halbtc8821aCsr2ant_PsTdma(pBtCoexist, FORCE_EXEC, FALSE, 1); + halbtc8821aCsr2ant_FwDacSwingLvl(pBtCoexist, FORCE_EXEC, 6); + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, FORCE_EXEC, FALSE); + + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); +} + +VOID +halbtc8821aCsr2ant_BtInquiryPage( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bLowPwrDisable=TRUE; + + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + + halbtc8821aCsr2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55ff55ff, 0x5afa5afa, 0xffff, 0x3); + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); +} +BOOLEAN +halbtc8821aCsr2ant_IsCommonAction( + IN PBTC_COEXIST pBtCoexist + ) +{ + BOOLEAN bCommon=FALSE, bWifiConnected=FALSE, bWifiBusy=FALSE; + BOOLEAN bLowPwrDisable=FALSE; + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + + if(!bWifiConnected && + BT_8821A_CSR_2ANT_BT_STATUS_IDLE == pCoexDm->btStatus) + { + bLowPwrDisable = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi IPS + BT IPS!!\n")); + + + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + halbtc8821aCsr2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + halbtc8821aCsr2ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0, 0); + halbtc8821aCsr2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, 0, 0, 0); + + bCommon = TRUE; + } + else if(bWifiConnected && + (BT_8821A_CSR_2ANT_BT_STATUS_IDLE == pCoexDm->btStatus) ) + { + bLowPwrDisable = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + + if(bWifiBusy) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi Busy + BT IPS!!\n")); + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi LPS + BT IPS!!\n")); + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + } + + halbtc8821aCsr2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + halbtc8821aCsr2ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0, 0); + halbtc8821aCsr2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, 0, 0, 0); + + bCommon = TRUE; + } + else if(!bWifiConnected && + (BT_8821A_CSR_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) ) + { + bLowPwrDisable = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi IPS + BT LPS!!\n")); + + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + halbtc8821aCsr2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + halbtc8821aCsr2ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0, 0); + halbtc8821aCsr2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, 0, 0, 0); + + bCommon = TRUE; + } + else if(bWifiConnected && + (BT_8821A_CSR_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) ) + { + bLowPwrDisable = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + + if(bWifiBusy) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi Busy + BT LPS!!\n")); + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi LPS + BT LPS!!\n")); + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + } + + halbtc8821aCsr2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,TRUE,TRUE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + halbtc8821aCsr2ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0, 0); + halbtc8821aCsr2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, 0, 0, 0); + + bCommon = TRUE; + } + else if(!bWifiConnected && + (BT_8821A_CSR_2ANT_BT_STATUS_NON_IDLE == pCoexDm->btStatus) ) + { + bLowPwrDisable = FALSE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi IPS + BT Busy!!\n")); + + //halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + halbtc8821aCsr2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + halbtc8821aCsr2ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0, 0); + halbtc8821aCsr2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, 0, 0, 0); + + bCommon = TRUE; + } + else + { + bLowPwrDisable = TRUE; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); + + if(bWifiBusy) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi Busy + BT Busy!!\n")); + bCommon = FALSE; + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Wifi LPS + BT Busy!!\n")); + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 21); + + if(halbtc8821aCsr2ant_NeedToDecBtPwr(pBtCoexist)) + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); + else + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + + bCommon = TRUE; + } + + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,TRUE,TRUE); + } + + if (bCommon == TRUE) + halbtc8821aCsr2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55ff55ff, 0x5afa5afa, 0xffff, 0x3); + + return bCommon; +} +VOID +halbtc8821aCsr2ant_TdmaDurationAdjust( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bScoHid, + IN BOOLEAN bTxPause, + IN u1Byte maxInterval + ) +{ + static s4Byte up,dn,m,n,WaitCount; + s4Byte result; //0: no change, +1: increase WiFi duration, -1: decrease WiFi duration + u1Byte retryCount=0; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TdmaDurationAdjust()\n")); + + if(pCoexDm->bResetTdmaAdjust) + { + pCoexDm->bResetTdmaAdjust = FALSE; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], first run TdmaDurationAdjust()!!\n")); + { + if(bScoHid) + { + if(bTxPause) + { + if(maxInterval == 1) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + pCoexDm->psTdmaDuAdjType = 13; + } + else if(maxInterval == 2) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(maxInterval == 3) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + } + else + { + if(maxInterval == 1) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(maxInterval == 2) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(maxInterval == 3) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + } + } + else + { + if(bTxPause) + { + if(maxInterval == 1) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + pCoexDm->psTdmaDuAdjType = 5; + } + else if(maxInterval == 2) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(maxInterval == 3) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + } + else + { + if(maxInterval == 1) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + else if(maxInterval == 2) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(maxInterval == 3) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + } + } + } + //============ + up = 0; + dn = 0; + m = 1; + n= 3; + result = 0; + WaitCount = 0; + } + else + { + //accquire the BT TRx retry count from BT_Info byte2 + retryCount = pCoexSta->btRetryCnt; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], retryCount = %d\n", retryCount)); + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], up=%d, dn=%d, m=%d, n=%d, WaitCount=%d\n", + up, dn, m, n, WaitCount)); + result = 0; + WaitCount++; + + if(retryCount == 0) // no retry in the last 2-second duration + { + up++; + dn--; + + if (dn <= 0) + dn = 0; + + if(up >= n) // if s n 2 retry count0, hռeWiFi duration + { + WaitCount = 0; + n = 3; + up = 0; + dn = 0; + result = 1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Increase wifi duration!!\n")); + } + } + else if (retryCount <= 3) // <=3 retry in the last 2-second duration + { + up--; + dn++; + + if (up <= 0) + up = 0; + + if (dn == 2) // if s 2 2 retry count< 3, hկWiFi duration + { + if (WaitCount <= 2) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter<3!!\n")); + } + } + else //retry count > 3, un1 retry count > 3, hկWiFi duration + { + if (WaitCount == 1) + m++; // קK@blevelӦ^ + else + m = 1; + + if ( m >= 20) //m ̤j = 20 ' ̤j120 recheckO_վ WiFi duration. + m = 20; + + n = 3*m; + up = 0; + dn = 0; + WaitCount = 0; + result = -1; + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], Decrease wifi duration for retryCounter>3!!\n")); + } + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], max Interval = %d\n", maxInterval)); + if(maxInterval == 1) + { + if(bTxPause) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 1\n")); + + if(pCoexDm->curPsTdma == 71) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + pCoexDm->psTdmaDuAdjType = 5; + } + else if(pCoexDm->curPsTdma == 1) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + pCoexDm->psTdmaDuAdjType = 5; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 4) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + if(pCoexDm->curPsTdma == 9) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + pCoexDm->psTdmaDuAdjType = 13; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + + if(result == -1) + { + if(pCoexDm->curPsTdma == 5) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + else if(pCoexDm->curPsTdma == 13) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 8) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + pCoexDm->psTdmaDuAdjType = 5; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + pCoexDm->psTdmaDuAdjType = 13; + } + } + } + else + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 0\n")); + if(pCoexDm->curPsTdma == 5) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 71); + pCoexDm->psTdmaDuAdjType = 71; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 8) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + if(pCoexDm->curPsTdma == 13) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + + if(result == -1) + { + if(pCoexDm->curPsTdma == 71) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + else if(pCoexDm->curPsTdma == 1) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 4) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + pCoexDm->psTdmaDuAdjType = 1; + } + else if(pCoexDm->curPsTdma == 1) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 71); + pCoexDm->psTdmaDuAdjType = 71; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + pCoexDm->psTdmaDuAdjType = 9; + } + } + } + } + else if(maxInterval == 2) + { + if(bTxPause) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 1\n")); + if(pCoexDm->curPsTdma == 1) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 4) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + if(pCoexDm->curPsTdma == 9) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 5) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + else if(pCoexDm->curPsTdma == 13) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 8) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 6); + pCoexDm->psTdmaDuAdjType = 6; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + pCoexDm->psTdmaDuAdjType = 14; + } + } + } + else + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 0\n")); + if(pCoexDm->curPsTdma == 5) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 8) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + if(pCoexDm->curPsTdma == 13) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 1) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 4) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 2); + pCoexDm->psTdmaDuAdjType = 2; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + pCoexDm->psTdmaDuAdjType = 10; + } + } + } + } + else if(maxInterval == 3) + { + if(bTxPause) + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 1\n")); + if(pCoexDm->curPsTdma == 1) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 4) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + if(pCoexDm->curPsTdma == 9) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 5) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 8); + pCoexDm->psTdmaDuAdjType = 8; + } + else if(pCoexDm->curPsTdma == 13) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 16); + pCoexDm->psTdmaDuAdjType = 16; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 8) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 7); + pCoexDm->psTdmaDuAdjType = 7; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 15); + pCoexDm->psTdmaDuAdjType = 15; + } + } + } + else + { + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], TxPause = 0\n")); + if(pCoexDm->curPsTdma == 5) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 6) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 7) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 8) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + if(pCoexDm->curPsTdma == 13) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 14) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 15) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 16) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + if(result == -1) + { + if(pCoexDm->curPsTdma == 1) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 4); + pCoexDm->psTdmaDuAdjType = 4; + } + else if(pCoexDm->curPsTdma == 9) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 12); + pCoexDm->psTdmaDuAdjType = 12; + } + } + else if (result == 1) + { + if(pCoexDm->curPsTdma == 4) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 3) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 2) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 3); + pCoexDm->psTdmaDuAdjType = 3; + } + else if(pCoexDm->curPsTdma == 12) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 11) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + else if(pCoexDm->curPsTdma == 10) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 11); + pCoexDm->psTdmaDuAdjType = 11; + } + } + } + } + } + + // if current PsTdma not match with the recorded one (when scan, dhcp...), + // then we have to adjust it back to the previous record one. + if(pCoexDm->curPsTdma != pCoexDm->psTdmaDuAdjType) + { + BOOLEAN bScan=FALSE, bLink=FALSE, bRoam=FALSE; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], PsTdma type dismatch!!!, curPsTdma=%d, recordPsTdma=%d\n", + pCoexDm->curPsTdma, pCoexDm->psTdmaDuAdjType)); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + + if( !bScan && !bLink && !bRoam) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, pCoexDm->psTdmaDuAdjType); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], roaming/link/scan is under progress, will adjust next time!!!\n")); + } + } + + // when halbtc8821aCsr2ant_TdmaDurationAdjust() is called, fw dac swing is included in the function. + //if(pCoexDm->psTdmaDuAdjType == 71) + // halbtc8821aCsr2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0xc); //Skip because A2DP get worse at HT40 + //else + halbtc8821aCsr2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0x6); +} + +// SCO only or SCO+PAN(HS) +VOID +halbtc8821aCsr2ant_ActionSco( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState,btRssiState; + u4Byte wifiBw; + + halbtc8821aCsr2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55555555, 0x55555555, 0xffffff, 0x3); + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); + + halbtc8821aCsr2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, TRUE); + + halbtc8821aCsr2ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 1, 0, 2, 0); + + if(pCoexSta->bSlave == FALSE) + halbtc8821aCsr2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, TRUE, 0x4); + else + halbtc8821aCsr2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, TRUE, 0x2); + +/* + wifiRssiState = halbtc8821aCsr2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + btRssiState = halbtc8821aCsr2ant_BtRssiState(2, 35, 0); + + halbtc8821aCsr2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 4); + + if(halbtc8821aCsr2ant_NeedToDecBtPwr(pBtCoexist)) + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); + else + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if (BTC_WIFI_BW_LEGACY == wifiBw) //for SCO quality at 11b/g mode + { + halbtc8821aCsr2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x5a5a5a5a, 0x5a5a5a5a, 0xffff, 0x3); + } + else //for SCO quality & wifi performance balance at 11n mode + { + halbtc8821aCsr2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x5aea5aea, 0x5aea5aea, 0xffff, 0x3); + } + + if(BTC_WIFI_BW_HT40 == wifiBw) + { + + // fw mechanism + //halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); //for voice quality + } + else + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); //for voice quality + } + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + // fw mechanism + //halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); //for voice quality + } + else + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 0); //for voice quality + } + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +*/ +} + + +VOID +halbtc8821aCsr2ant_ActionHid( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8821aCsr2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + btRssiState = halbtc8821aCsr2ant_BtRssiState(2, 35, 0); + + halbtc8821aCsr2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + if(halbtc8821aCsr2ant_NeedToDecBtPwr(pBtCoexist)) + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); + else + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if (BTC_WIFI_BW_LEGACY == wifiBw) //for HID at 11b/g mode + { + halbtc8821aCsr2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55ff55ff, 0x5a5a5a5a, 0xffff, 0x3); + } + else //for HID quality & wifi performance balance at 11n mode + { + halbtc8821aCsr2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55ff55ff, 0x5aea5aea, 0xffff, 0x3); + } + + if(BTC_WIFI_BW_HT40 == wifiBw) + { + // fw mechanism + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + } + else + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + } + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + // fw mechanism + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 9); + } + else + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 13); + } + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +//A2DP only / PAN(EDR) only/ A2DP+PAN(HS) +VOID +halbtc8821aCsr2ant_ActionA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, btRssiState; + u4Byte wifiBw; + + halbtc8821aCsr2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, FALSE, TRUE, 0x8); + + if(pCoexSta->bSlave == FALSE) + { + halbtc8821aCsr2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0xfdfdfdfd, 0xdfdadfda, 0xffffff, 0x3); + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 22); + halbtc8821aCsr2ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0, 1); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,TRUE,0x0c); + } + else + { + halbtc8821aCsr2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0xfdfdfdfd, 0xdfdadfda, 0xffffff, 0x3); + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 23); + halbtc8821aCsr2ant_LimitedTx(pBtCoexist, NORMAL_EXEC, 0, 0, 0, 0, 2); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,TRUE,0x18); + } + +/* + wifiRssiState = halbtc8821aCsr2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + btRssiState = halbtc8821aCsr2ant_BtRssiState(2, 35, 0); + + //fw dac swing is called in halbtc8821aCsr2ant_TdmaDurationAdjust() + //halbtc8821aCsr2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + + if(halbtc8821aCsr2ant_NeedToDecBtPwr(pBtCoexist)) + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); + else + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if(BTC_WIFI_BW_HT40 == wifiBw) + { + // fw mechanism + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 1); + } + else + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 1); + } + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + // fw mechanism + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 1); + } + else + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 1); + } + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +*/ +} + +VOID +halbtc8821aCsr2ant_ActionA2dpPanHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, btRssiState, btInfoExt; + u4Byte wifiBw; + + btInfoExt = pCoexSta->btInfoExt; + wifiRssiState = halbtc8821aCsr2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + btRssiState = halbtc8821aCsr2ant_BtRssiState(2,35, 0); + + //fw dac swing is called in halbtc8821aCsr2ant_TdmaDurationAdjust() + //halbtc8821aCsr2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + + if(halbtc8821aCsr2ant_NeedToDecBtPwr(pBtCoexist)) + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); + else + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if(BTC_WIFI_BW_HT40 == wifiBw) + { + // fw mechanism + if(btInfoExt&BIT0) //a2dp basic rate + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 2); + } + else //a2dp edr rate + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 1); + } + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + // fw mechanism + if(btInfoExt&BIT0) //a2dp basic rate + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 2); + } + else //a2dp edr rate + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 1); + } + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +VOID +halbtc8821aCsr2ant_ActionPanEdr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8821aCsr2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + btRssiState = halbtc8821aCsr2ant_BtRssiState(2, 35, 0); + + halbtc8821aCsr2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + if(halbtc8821aCsr2ant_NeedToDecBtPwr(pBtCoexist)) + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); + else + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if (BTC_WIFI_BW_LEGACY == wifiBw) //for HID at 11b/g mode + { + halbtc8821aCsr2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55ff55ff, 0x5aff5aff, 0xffff, 0x3); + } + else //for HID quality & wifi performance balance at 11n mode + { + halbtc8821aCsr2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55ff55ff, 0x5aff5aff, 0xffff, 0x3); + } + + if(BTC_WIFI_BW_HT40 == wifiBw) + { + // fw mechanism + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + } + else + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + } + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + // fw mechanism + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 1); + } + else + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 5); + } + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + + +//PAN(HS) only +VOID +halbtc8821aCsr2ant_ActionPanHs( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8821aCsr2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + btRssiState = halbtc8821aCsr2ant_BtRssiState(2, 35, 0); + + halbtc8821aCsr2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if(BTC_WIFI_BW_HT40 == wifiBw) + { + // fw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); + } + else + { + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + } + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + // fw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); + } + else + { + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + } + + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + } + else + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, FALSE, 1); + } + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +//PAN(EDR)+A2DP +VOID +halbtc8821aCsr2ant_ActionPanEdrA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, btRssiState, btInfoExt; + u4Byte wifiBw; + + btInfoExt = pCoexSta->btInfoExt; + wifiRssiState = halbtc8821aCsr2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + btRssiState = halbtc8821aCsr2ant_BtRssiState(2, 35, 0); + + halbtc8821aCsr2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + if(halbtc8821aCsr2ant_NeedToDecBtPwr(pBtCoexist)) + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); + else + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if (BTC_WIFI_BW_LEGACY == wifiBw) //for HID at 11b/g mode + { + halbtc8821aCsr2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55ff55ff, 0x5afa5afa, 0xffff, 0x3); + } + else //for HID quality & wifi performance balance at 11n mode + { + halbtc8821aCsr2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55ff55ff, 0x5afa5afa, 0xffff, 0x3); + } + + if(BTC_WIFI_BW_HT40 == wifiBw) + { + // fw mechanism + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + if(btInfoExt&BIT0) //a2dp basic rate + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 3); + } + else //a2dp edr rate + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 3); + } + } + else + { + if(btInfoExt&BIT0) //a2dp basic rate + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 3); + } + else //a2dp edr rate + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 3); + } + } + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,TRUE,FALSE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + }; + } + else + { + // fw mechanism + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + if(btInfoExt&BIT0) //a2dp basic rate + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 3); + } + else //a2dp edr rate + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, FALSE, FALSE, 3); + } + } + else + { + if(btInfoExt&BIT0) //a2dp basic rate + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 3); + } + else //a2dp edr rate + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, FALSE, TRUE, 3); + } + } + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,FALSE,FALSE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +VOID +halbtc8821aCsr2ant_ActionPanEdrHid( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, btRssiState; + u4Byte wifiBw; + + wifiRssiState = halbtc8821aCsr2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + btRssiState = halbtc8821aCsr2ant_BtRssiState(2, 35, 0); + + halbtc8821aCsr2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + if(halbtc8821aCsr2ant_NeedToDecBtPwr(pBtCoexist)) + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); + else + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if (BTC_WIFI_BW_LEGACY == wifiBw) //for HID at 11b/g mode + { + halbtc8821aCsr2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55ff55ff, 0x5a5f5a5f, 0xffff, 0x3); + } + else //for HID quality & wifi performance balance at 11n mode + { + halbtc8821aCsr2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55ff55ff, 0x5a5f5a5f, 0xffff, 0x3); + } + + if(BTC_WIFI_BW_HT40 == wifiBw) + { + halbtc8821aCsr2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 3); + // fw mechanism + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + } + else + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + } + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + halbtc8821aCsr2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + // fw mechanism + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 10); + } + else + { + halbtc8821aCsr2ant_PsTdma(pBtCoexist, NORMAL_EXEC, TRUE, 14); + } + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +// HID+A2DP+PAN(EDR) +VOID +halbtc8821aCsr2ant_ActionHidA2dpPanEdr( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, btRssiState, btInfoExt; + u4Byte wifiBw; + + btInfoExt = pCoexSta->btInfoExt; + wifiRssiState = halbtc8821aCsr2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + btRssiState = halbtc8821aCsr2ant_BtRssiState(2, 35, 0); + + halbtc8821aCsr2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); + + if(halbtc8821aCsr2ant_NeedToDecBtPwr(pBtCoexist)) + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); + else + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if (BTC_WIFI_BW_LEGACY == wifiBw) //for HID at 11b/g mode + { + halbtc8821aCsr2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55ff55ff, 0x5a5a5a5a, 0xffff, 0x3); + } + else //for HID quality & wifi performance balance at 11n mode + { + halbtc8821aCsr2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55ff55ff, 0x5a5a5a5a, 0xffff, 0x3); + } + + if(BTC_WIFI_BW_HT40 == wifiBw) + { + // fw mechanism + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + if(btInfoExt&BIT0) //a2dp basic rate + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 3); + } + else //a2dp edr rate + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 3); + } + } + else + { + if(btInfoExt&BIT0) //a2dp basic rate + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 3); + } + else //a2dp edr rate + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 3); + } + } + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + // fw mechanism + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + if(btInfoExt&BIT0) //a2dp basic rate + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 3); + } + else //a2dp edr rate + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 3); + } + } + else + { + if(btInfoExt&BIT0) //a2dp basic rate + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 3); + } + else //a2dp edr rate + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 3); + } + } + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +VOID +halbtc8821aCsr2ant_ActionHidA2dp( + IN PBTC_COEXIST pBtCoexist + ) +{ + u1Byte wifiRssiState, btRssiState, btInfoExt; + u4Byte wifiBw; + + btInfoExt = pCoexSta->btInfoExt; + wifiRssiState = halbtc8821aCsr2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); + btRssiState = halbtc8821aCsr2ant_BtRssiState(2, 35, 0); + + if(halbtc8821aCsr2ant_NeedToDecBtPwr(pBtCoexist)) + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, TRUE); + else + halbtc8821aCsr2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, FALSE); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + + if (BTC_WIFI_BW_LEGACY == wifiBw) //for HID at 11b/g mode + { +//Allen halbtc8821aCsr2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55ff55ff, 0x5a5a5a5a, 0xffff, 0x3); + halbtc8821aCsr2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55ff55ff, 0x5f5b5f5b, 0xffffff, 0x3); + } + else //for HID quality & wifi performance balance at 11n mode + { +//Allen halbtc8821aCsr2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55ff55ff, 0x5a5a5a5a, 0xffff, 0x3); + halbtc8821aCsr2ant_CoexTable(pBtCoexist, NORMAL_EXEC, 0x55ff55ff, 0x5f5b5f5b, 0xffffff, 0x3); + + } + + if(BTC_WIFI_BW_HT40 == wifiBw) + { + // fw mechanism + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + if(btInfoExt&BIT0) //a2dp basic rate + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 2); + } + else //a2dp edr rate + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 2); + } + } + else + { + if(btInfoExt&BIT0) //a2dp basic rate + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 2); + } + else //a2dp edr rate + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 2); + } + } + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,TRUE,TRUE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } + else + { + // fw mechanism + if( (btRssiState == BTC_RSSI_STATE_HIGH) || + (btRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + if(btInfoExt&BIT0) //a2dp basic rate + { +// halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 2); + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 2); + + } + else //a2dp edr rate + { +//Allen halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, TRUE, FALSE, 2); + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 2); + } + } + else + { + if(btInfoExt&BIT0) //a2dp basic rate + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 2); + } + else //a2dp edr rate + { + halbtc8821aCsr2ant_TdmaDurationAdjust(pBtCoexist, TRUE, TRUE, 2); + } + } + + // sw mechanism + if( (wifiRssiState == BTC_RSSI_STATE_HIGH) || + (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) ) + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,TRUE,FALSE,FALSE,0x18); + } + else + { + halbtc8821aCsr2ant_SwMechanism1(pBtCoexist,FALSE,TRUE,FALSE,FALSE); + halbtc8821aCsr2ant_SwMechanism2(pBtCoexist,FALSE,FALSE,FALSE,0x18); + } + } +} + +VOID +halbtc8821aCsr2ant_RunCoexistMechanism( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + BOOLEAN bWifiUnder5G=FALSE; + u1Byte btInfoOriginal=0, btRetryCnt=0; + u1Byte algorithm=0; + + if(pBtCoexist->bManualControl) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Manual control!!!\n")); + return; + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_5G, &bWifiUnder5G); + + if(bWifiUnder5G) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], RunCoexistMechanism(), run 5G coex setting!!<===\n")); + halbtc8821aCsr2ant_CoexUnder5G(pBtCoexist); + return; + } + + //if(pStackInfo->bProfileNotified) + { + algorithm = halbtc8821aCsr2ant_ActionAlgorithm(pBtCoexist); + if(pCoexSta->bC2hBtInquiryPage && (BT_8821A_CSR_2ANT_COEX_ALGO_PANHS!=algorithm)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT is under inquiry/page scan !!\n")); + halbtc8821aCsr2ant_BtInquiryPage(pBtCoexist); + return; + } + + pCoexDm->curAlgorithm = algorithm; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Algorithm = %d \n", pCoexDm->curAlgorithm)); + + if(halbtc8821aCsr2ant_IsCommonAction(pBtCoexist)) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant common.\n")); + pCoexDm->bResetTdmaAdjust = TRUE; + } + else + { + if(pCoexDm->curAlgorithm != pCoexDm->preAlgorithm) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], preAlgorithm=%d, curAlgorithm=%d\n", + pCoexDm->preAlgorithm, pCoexDm->curAlgorithm)); + pCoexDm->bResetTdmaAdjust = TRUE; + } + switch(pCoexDm->curAlgorithm) + { + case BT_8821A_CSR_2ANT_COEX_ALGO_SCO: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = SCO.\n")); + halbtc8821aCsr2ant_ActionSco(pBtCoexist); + break; + case BT_8821A_CSR_2ANT_COEX_ALGO_HID: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID.\n")); + halbtc8821aCsr2ant_ActionHid(pBtCoexist); + break; + case BT_8821A_CSR_2ANT_COEX_ALGO_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = A2DP.\n")); + halbtc8821aCsr2ant_ActionA2dp(pBtCoexist); + break; + case BT_8821A_CSR_2ANT_COEX_ALGO_A2DP_PANHS: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = A2DP+PAN(HS).\n")); + halbtc8821aCsr2ant_ActionA2dpPanHs(pBtCoexist); + break; + case BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN(EDR).\n")); + halbtc8821aCsr2ant_ActionPanEdr(pBtCoexist); + break; + case BT_8821A_CSR_2ANT_COEX_ALGO_PANHS: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HS mode.\n")); + halbtc8821aCsr2ant_ActionPanHs(pBtCoexist); + break; + case BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN+A2DP.\n")); + halbtc8821aCsr2ant_ActionPanEdrA2dp(pBtCoexist); + break; + case BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = PAN(EDR)+HID.\n")); + halbtc8821aCsr2ant_ActionPanEdrHid(pBtCoexist); + break; + case BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP_PANEDR: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP+PAN.\n")); + halbtc8821aCsr2ant_ActionHidA2dpPanEdr(pBtCoexist); + break; + case BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = HID+A2DP.\n")); + halbtc8821aCsr2ant_ActionHidA2dp(pBtCoexist); + break; + default: + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Action 2-Ant, algorithm = coexist All Off!!\n")); + halbtc8821aCsr2ant_CoexAllOff(pBtCoexist); + break; + } + pCoexDm->preAlgorithm = pCoexDm->curAlgorithm; + } + } +} + + + +//============================================================ +// work around function start with wa_halbtc8821aCsr2ant_ +//============================================================ +//============================================================ +// extern function start with EXhalbtc8821aCsr2ant_ +//============================================================ +VOID +EXhalbtc8821aCsr2ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ) +{ +} + +VOID +EXhalbtc8821aCsr2ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + u4Byte u4Tmp=0; + u2Byte u2Tmp=0; + u1Byte u1Tmp=0; + u1Byte H2C_Parameter[2] ={0}; + + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], 2Ant Init HW Config!!\n")); + + if(bWifiOnly) + return; + + //if(bBackUp) + { + // backup rf 0x1e value + pCoexDm->btRf0x1eBackup = pBtCoexist->fBtcGetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff); + pCoexDm->backupArfrCnt1 = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x430); + pCoexDm->backupArfrCnt2 = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x434); + pCoexDm->backupRetryLimit = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0x42a); + pCoexDm->backupAmpduMaxTime = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x456); + pCoexDm->backupAmpduMaxNum = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0x4ca); + } + + #if 0 /* REMOVE */ + // 0x790[5:0]=0x5 + u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x790); + u1Tmp &= 0xc0; + u1Tmp |= 0x5; + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x790, u1Tmp); + #endif + + //Antenna config + halbtc8821aCsr2ant_SetAntPath(pBtCoexist, BTC_ANT_WIFI_AT_MAIN, TRUE, FALSE); + + // PTA parameter + halbtc8821aCsr2ant_CoexTable(pBtCoexist, FORCE_EXEC, 0x55555555, 0x55555555, 0xffff, 0x3); + + // Enable counter statistics + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0xc); //0x76e[3] =1, WLAN_Act control by PTA + pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x778, 0x3); + + #if 0 /* REMOVE */ + pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x40, 0x20, 0x1); + #endif +} + +VOID +EXhalbtc8821aCsr2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Coex Mechanism Init!!\n")); + + halbtc8821aCsr2ant_InitCoexDm(pBtCoexist); +} + +VOID +EXhalbtc8821aCsr2ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ) +{ + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + pu1Byte cliBuf=pBtCoexist->cliBuf; + u1Byte u1Tmp[4], i, btInfoExt, psTdmaCase=0; + u4Byte u4Tmp[4]; + u4Byte fwVer=0, btPatchVer=0; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:", \ + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum); + CL_PRINTF(cliBuf); + + if(pBtCoexist->bManualControl) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "[Action Manual control]!!"); + CL_PRINTF(cliBuf); + } + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \ + ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion); + CL_PRINTF(cliBuf); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_BT_PATCH_VER, &btPatchVer); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d_%d/ 0x%x/ 0x%x(%d)", "CoexVer/ FwVer/ PatchVer", \ + GLCoexVerDate8821aCsr2Ant, GLCoexVer8821aCsr2Ant, fwVer, btPatchVer, btPatchVer); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x ", "Wifi channel informed to BT", \ + pCoexDm->wifiChnlInfo[0], pCoexDm->wifiChnlInfo[1], + pCoexDm->wifiChnlInfo[2]); + CL_PRINTF(cliBuf); + + // wifi status + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Wifi Status]============"); + CL_PRINTF(cliBuf); + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_WIFI_STATUS); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[BT Status]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s/ %d/ %d] ", "BT [status/ rssi/ retryCnt]", \ + ((pCoexSta->bC2hBtInquiryPage)?("inquiry/page scan"):((BT_8821A_CSR_2ANT_BT_STATUS_IDLE == pCoexDm->btStatus)? "idle":( (BT_8821A_CSR_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus)? "connected-idle":"busy"))), + pCoexSta->btRssi, pCoexSta->btRetryCnt); + CL_PRINTF(cliBuf); + + if(pStackInfo->bProfileNotified) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP", \ + pStackInfo->bScoExist, pStackInfo->bHidExist, pStackInfo->bPanExist, pStackInfo->bA2dpExist); + CL_PRINTF(cliBuf); + + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO); + } + + btInfoExt = pCoexSta->btInfoExt; + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "BT Info A2DP rate", \ + (btInfoExt&BIT0)? "Basic rate":"EDR rate"); + CL_PRINTF(cliBuf); + + for(i=0; ibtInfoC2hCnt[i]) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", GLBtInfoSrc8821aCsr2Ant[i], \ + pCoexSta->btInfoC2h[i][0], pCoexSta->btInfoC2h[i][1], + pCoexSta->btInfoC2h[i][2], pCoexSta->btInfoC2h[i][3], + pCoexSta->btInfoC2h[i][4], pCoexSta->btInfoC2h[i][5], + pCoexSta->btInfoC2h[i][6], pCoexSta->btInfoC2hCnt[i]); + CL_PRINTF(cliBuf); + } + } + + // Sw mechanism + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Sw mechanism]============"); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", "SM1[ShRf/ LpRA/ LimDig]", \ + pCoexDm->bCurRfRxLpfShrink, pCoexDm->bCurLowPenaltyRa, pCoexDm->bLimitedDig); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d(0x%x) ", "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", \ + pCoexDm->bCurAgcTableEn, pCoexDm->bCurAdcBackOff, pCoexDm->bCurDacSwingOn, pCoexDm->curDacSwingLvl); + CL_PRINTF(cliBuf); + + // Fw mechanism + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============"); + CL_PRINTF(cliBuf); + + if(!pBtCoexist->bManualControl) + { + psTdmaCase = pCoexDm->curPsTdma; + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x case-%d", "PS TDMA", \ + pCoexDm->psTdmaPara[0], pCoexDm->psTdmaPara[1], + pCoexDm->psTdmaPara[2], pCoexDm->psTdmaPara[3], + pCoexDm->psTdmaPara[4], psTdmaCase); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d ", "DecBtPwr/ IgnWlanAct", \ + pCoexDm->bCurDecBtPwr, pCoexDm->bCurIgnoreWlanAct); + CL_PRINTF(cliBuf); + } + + // Hw setting + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============"); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "RF-A, 0x1e initVal", \ + pCoexDm->btRf0x1eBackup); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x778); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x6cc); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x ", "0x778 (W_Act)/ 0x6cc (CoTab Sel)", \ + u1Tmp[0], u1Tmp[1]); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x8db); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xc5b); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x8db(ADC)/0xc5b[29:25](DAC)", \ + ((u1Tmp[0]&0x60)>>5), ((u1Tmp[1]&0x3e)>>1)); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xcb4); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0xcb4[7:0](ctrl)/ 0xcb4[29:28](val)", \ + u4Tmp[0]&0xff, ((u4Tmp[0]&0x30000000)>>28)); + CL_PRINTF(cliBuf); + + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x40); + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x4c); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x974); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x40/ 0x4c[24:23]/ 0x974", \ + u1Tmp[0], ((u4Tmp[0]&0x01800000)>>23), u4Tmp[1]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x550); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x522); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0x550(bcn ctrl)/0x522", \ + u4Tmp[0], u1Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc50); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xa0a); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "0xc50(DIG)/0xa0a(CCK-TH)", \ + u4Tmp[0], u1Tmp[0]); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xf48); + u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xa5b); + u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xa5c); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x", "OFDM-FA/ CCK-FA", \ + u4Tmp[0], (u1Tmp[0]<<8) + u1Tmp[1] ); + CL_PRINTF(cliBuf); + + u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c0); + u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c4); + u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c8); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x6c0/0x6c4/0x6c8", \ + u4Tmp[0], u4Tmp[1], u4Tmp[2]); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x770 (hi-pri Rx/Tx)", \ + pCoexSta->highPriorityRx, pCoexSta->highPriorityTx); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "0x774(low-pri Rx/Tx)", \ + pCoexSta->lowPriorityRx, pCoexSta->lowPriorityTx); + CL_PRINTF(cliBuf); + + pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS); +} + + +VOID +EXhalbtc8821aCsr2ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_IPS_ENTER == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS ENTER notify\n")); + pCoexSta->bUnderIps = TRUE; + halbtc8821aCsr2ant_CoexAllOff(pBtCoexist); + } + else if(BTC_IPS_LEAVE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], IPS LEAVE notify\n")); + pCoexSta->bUnderIps = FALSE; + //halbtc8821aCsr2ant_InitCoexDm(pBtCoexist); + } +} + +VOID +EXhalbtc8821aCsr2ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_LPS_ENABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS ENABLE notify\n")); + pCoexSta->bUnderLps = TRUE; + } + else if(BTC_LPS_DISABLE == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], LPS DISABLE notify\n")); + pCoexSta->bUnderLps = FALSE; + } +} + +VOID +EXhalbtc8821aCsr2ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_SCAN_START == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN START notify\n")); + } + else if(BTC_SCAN_FINISH == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], SCAN FINISH notify\n")); + } +} + +VOID +EXhalbtc8821aCsr2ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(BTC_ASSOCIATE_START == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT START notify\n")); + } + else if(BTC_ASSOCIATE_FINISH == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CONNECT FINISH notify\n")); + } +} + +VOID +EXhalbtc8821aCsr2ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + u1Byte H2C_Parameter[3] ={0}; + u4Byte wifiBw; + u1Byte wifiCentralChnl; + + if(BTC_MEDIA_CONNECT == type) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA connect notify\n")); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], MEDIA disconnect notify\n")); + } + + // only 2.4G we need to inform bt the chnl mask + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, &wifiCentralChnl); + if( (BTC_MEDIA_CONNECT == type) && + (wifiCentralChnl <= 14) ) + { + H2C_Parameter[0] = 0x1; + H2C_Parameter[1] = wifiCentralChnl; + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + if(BTC_WIFI_BW_HT40 == wifiBw) + H2C_Parameter[2] = 0x30; + else + H2C_Parameter[2] = 0x20; + } + + #if 0 /* REMOVE */ + pCoexDm->wifiChnlInfo[0] = H2C_Parameter[0]; + pCoexDm->wifiChnlInfo[1] = H2C_Parameter[1]; + pCoexDm->wifiChnlInfo[2] = H2C_Parameter[2]; + + RT_TRACE(COMP_COEX, DBG_TRACE, ("[BTCoex], FW write 0x66=0x%x\n", + H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2])); + + rtw_warn_on(_BTCOEX_CSR); + pBtCoexist->fBtcFillH2c(pBtCoexist, 0x66, 3, H2C_Parameter); + #endif +} + +VOID +EXhalbtc8821aCsr2ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(type == BTC_PACKET_DHCP) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], DHCP Packet notify\n")); + } +} + +VOID +EXhalbtc8821aCsr2ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ) +{ + u1Byte btInfo=0; + u1Byte i, rspSource=0; + BOOLEAN bBtBusy=FALSE, bLimitedDig=FALSE; + BOOLEAN bWifiConnected=FALSE, bBtHsOn=FALSE, bWifiUnder5G=FALSE; + + pCoexSta->bC2hBtInfoReqSent = FALSE; + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_5G, &bWifiUnder5G); + + rspSource = tmpBuf[0]&0xf; + if(rspSource >= BT_INFO_SRC_8821A_CSR_2ANT_MAX) + rspSource = BT_INFO_SRC_8821A_CSR_2ANT_WIFI_FW; + pCoexSta->btInfoC2hCnt[rspSource]++; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Bt info[%d], length=%d, hex data=[", rspSource, length)); + for(i=0; ibtInfoC2h[rspSource][i] = tmpBuf[i]; + if(i == 1) + btInfo = tmpBuf[i]; + if(i == length-1) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x]\n", tmpBuf[i])); + } + else + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("0x%02x, ", tmpBuf[i])); + } + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); + if(BT_INFO_SRC_8821A_CSR_2ANT_WIFI_FW != rspSource) + { + pCoexSta->btRetryCnt = // [3:0] + pCoexSta->btInfoC2h[rspSource][2]&0xf; + + pCoexSta->btRssi = + pCoexSta->btInfoC2h[rspSource][3]*2+10; + + pCoexSta->btInfoExt = + pCoexSta->btInfoC2h[rspSource][4]; + + #if 0 /* REMOVE */ + // Here we need to resend some wifi info to BT + // because bt is reset and loss of the info. + if( (pCoexSta->btInfoExt & BIT1) ) + { + + if(bWifiConnected) + { + EXhalbtc8821aCsr2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_CONNECT); + } + else + { + EXhalbtc8821aCsr2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); + } + } + #endif + + #if 0 /* REMOVE */ + if(!pBtCoexist->bManualControl && !bWifiUnder5G) + { + if( (pCoexSta->btInfoExt&BIT3) ) + { + if(bWifiConnected) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT ext info bit3 check, set BT NOT to ignore Wlan active!!\n")); + halbtc8821aCsr2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, FALSE); + } + } + else + { + // BT already NOT ignore Wlan active, do nothing here. + if(!bWifiConnected) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT ext info bit3 check, set BT to ignore Wlan active!!\n")); + halbtc8821aCsr2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE); + } + } + } + #endif + + #if 0 /* REMOVE */ + if( (pCoexSta->btInfoExt & BIT4) ) + { + // BT auto report already enabled, do nothing + } + else + { + halbtc8821aCsr2ant_BtAutoReport(pBtCoexist, FORCE_EXEC, TRUE); + } + #endif + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + + if(btInfo == BT_INFO_8821A_CSR_2ANT_B_CONNECTION) // connection exists but no busy + { + pCoexSta->bBtLinkExist = TRUE; + pCoexDm->btStatus = BT_8821A_CSR_2ANT_BT_STATUS_CONNECTED_IDLE; + } + else if(btInfo & BT_INFO_8821A_CSR_2ANT_B_CONNECTION) // connection exists and some link is busy + { + pCoexSta->bBtLinkExist = TRUE; + + if(btInfo & BT_INFO_8821A_CSR_2ANT_B_FTP) + pCoexSta->bPanExist = TRUE; + else + pCoexSta->bPanExist = FALSE; + + if(btInfo & BT_INFO_8821A_CSR_2ANT_B_A2DP) + pCoexSta->bA2dpExist = TRUE; + else + pCoexSta->bA2dpExist = FALSE; + + if(btInfo & BT_INFO_8821A_CSR_2ANT_B_HID) + pCoexSta->bHidExist = TRUE; + else + pCoexSta->bHidExist = FALSE; + + if(btInfo & BT_INFO_8821A_CSR_2ANT_B_SCO_ESCO) + pCoexSta->bScoExist = TRUE; + else + pCoexSta->bScoExist = FALSE; + + if (pCoexSta->btInfoExt & 0x80) + pCoexSta->bSlave = TRUE; //Slave + else + pCoexSta->bSlave = FALSE; //Master + + pCoexDm->btStatus = BT_8821A_CSR_2ANT_BT_STATUS_NON_IDLE; + } + else + { + pCoexSta->bBtLinkExist = FALSE; + pCoexSta->bPanExist = FALSE; + pCoexSta->bA2dpExist = FALSE; + pCoexSta->bSlave = FALSE; + pCoexSta->bHidExist = FALSE; + pCoexSta->bScoExist = FALSE; + pCoexDm->btStatus = BT_8821A_CSR_2ANT_BT_STATUS_IDLE; + } + + if(bBtHsOn) + { + pCoexDm->btStatus = BT_8821A_CSR_2ANT_BT_STATUS_NON_IDLE; + } + + if(btInfo & BT_INFO_8821A_CSR_2ANT_B_INQ_PAGE) + { + pCoexSta->bC2hBtInquiryPage = TRUE; + pCoexDm->btStatus = BT_8821A_CSR_2ANT_BT_STATUS_NON_IDLE; + } + else + { + pCoexSta->bC2hBtInquiryPage = FALSE; + } + + + if(BT_8821A_CSR_2ANT_BT_STATUS_NON_IDLE == pCoexDm->btStatus) + { + bBtBusy = TRUE; + } + else + { + bBtBusy = FALSE; + } + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bBtBusy); + + if(BT_8821A_CSR_2ANT_BT_STATUS_IDLE != pCoexDm->btStatus) + { + bLimitedDig = TRUE; + } + else + { + bLimitedDig = FALSE; + } + pCoexDm->bLimitedDig = bLimitedDig; + pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_LIMITED_DIG, &bLimitedDig); + + halbtc8821aCsr2ant_RunCoexistMechanism(pBtCoexist); +} + +VOID +EXhalbtc8821aCsr2ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Halt notify\n")); + + halbtc8821aCsr2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE); + EXhalbtc8821aCsr2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); +} + +VOID +EXhalbtc8821aCsr2ant_PnpNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte pnpState + ) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Pnp notify\n")); + + if(BTC_WIFI_PNP_SLEEP == pnpState) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Pnp notify to SLEEP\n")); + halbtc8821aCsr2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, TRUE); + } + else if(BTC_WIFI_PNP_WAKE_UP == pnpState) + { + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Pnp notify to WAKE UP\n")); + } +} + +VOID +EXhalbtc8821aCsr2ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ) +{ + static u1Byte disVerInfoCnt=0; + u4Byte fwVer=0, btPatchVer=0; + PBTC_BOARD_INFO pBoardInfo=&pBtCoexist->boardInfo; + PBTC_STACK_INFO pStackInfo=&pBtCoexist->stackInfo; + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ==========================Periodical===========================\n")); + + if(disVerInfoCnt <= 5) + { + disVerInfoCnt += 1; + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ****************************************************************\n")); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Ant PG Num/ Ant Mech/ Ant Pos = %d/ %d/ %d\n", + pBoardInfo->pgAntNum, pBoardInfo->btdmAntNum, pBoardInfo->btdmAntPos)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], BT stack/ hci ext ver = %s / %d\n", + ((pStackInfo->bProfileNotified)? "Yes":"No"), pStackInfo->hciVersion)); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_BT_PATCH_VER, &btPatchVer); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], CoexVer/ FwVer/ PatchVer = %d_%x/ 0x%x/ 0x%x(%d)\n", + GLCoexVerDate8821aCsr2Ant, GLCoexVer8821aCsr2Ant, fwVer, btPatchVer, btPatchVer)); + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], ****************************************************************\n")); + } + + //halbtc8821aCsr2ant_QueryBtInfo(pBtCoexist); + //halbtc8821aCsr2ant_RunCoexistMechanism(pBtCoexist); + halbtc8821aCsr2ant_MonitorBtCtr(pBtCoexist); + halbtc8821aCsr2ant_MonitorBtEnableDisable(pBtCoexist); +} + + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8821aCsr2Ant.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8821aCsr2Ant.h new file mode 100644 index 000000000..9a96b07e1 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtc8821aCsr2Ant.h @@ -0,0 +1,208 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//=========================================== +// The following is for 8821A_CSR 2Ant BT Co-exist definition +//=========================================== +#define BT_INFO_8821A_CSR_2ANT_B_FTP BIT7 +#define BT_INFO_8821A_CSR_2ANT_B_A2DP BIT6 +#define BT_INFO_8821A_CSR_2ANT_B_HID BIT5 +#define BT_INFO_8821A_CSR_2ANT_B_SCO_BUSY BIT4 +#define BT_INFO_8821A_CSR_2ANT_B_ACL_BUSY BIT3 +#define BT_INFO_8821A_CSR_2ANT_B_INQ_PAGE BIT2 +#define BT_INFO_8821A_CSR_2ANT_B_SCO_ESCO BIT1 +#define BT_INFO_8821A_CSR_2ANT_B_CONNECTION BIT0 + +#define BTC_RSSI_COEX_THRESH_TOL_8821A_CSR_2ANT 2 + +typedef enum _BT_INFO_SRC_8821A_CSR_2ANT{ + BT_INFO_SRC_8821A_CSR_2ANT_WIFI_FW = 0x0, + BT_INFO_SRC_8821A_CSR_2ANT_BT_RSP = 0x1, + BT_INFO_SRC_8821A_CSR_2ANT_BT_ACTIVE_SEND = 0x2, + BT_INFO_SRC_8821A_CSR_2ANT_MAX +}BT_INFO_SRC_8821A_CSR_2ANT,*PBT_INFO_SRC_8821A_CSR_2ANT; + +typedef enum _BT_8821A_CSR_2ANT_BT_STATUS{ + BT_8821A_CSR_2ANT_BT_STATUS_IDLE = 0x0, + BT_8821A_CSR_2ANT_BT_STATUS_CONNECTED_IDLE = 0x1, + BT_8821A_CSR_2ANT_BT_STATUS_NON_IDLE = 0x2, + BT_8821A_CSR_2ANT_BT_STATUS_MAX +}BT_8821A_CSR_2ANT_BT_STATUS,*PBT_8821A_CSR_2ANT_BT_STATUS; + +typedef enum _BT_8821A_CSR_2ANT_COEX_ALGO{ + BT_8821A_CSR_2ANT_COEX_ALGO_UNDEFINED = 0x0, + BT_8821A_CSR_2ANT_COEX_ALGO_SCO = 0x1, + BT_8821A_CSR_2ANT_COEX_ALGO_HID = 0x2, + BT_8821A_CSR_2ANT_COEX_ALGO_A2DP = 0x3, + BT_8821A_CSR_2ANT_COEX_ALGO_A2DP_PANHS = 0x4, + BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR = 0x5, + BT_8821A_CSR_2ANT_COEX_ALGO_PANHS = 0x6, + BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_A2DP = 0x7, + BT_8821A_CSR_2ANT_COEX_ALGO_PANEDR_HID = 0x8, + BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP_PANEDR = 0x9, + BT_8821A_CSR_2ANT_COEX_ALGO_HID_A2DP = 0xa, + BT_8821A_CSR_2ANT_COEX_ALGO_MAX = 0xb, +}BT_8821A_CSR_2ANT_COEX_ALGO,*PBT_8821A_CSR_2ANT_COEX_ALGO; + +typedef struct _COEX_DM_8821A_CSR_2ANT{ + // fw mechanism + BOOLEAN bPreDecBtPwr; + BOOLEAN bCurDecBtPwr; + u1Byte preFwDacSwingLvl; + u1Byte curFwDacSwingLvl; + BOOLEAN bCurIgnoreWlanAct; + BOOLEAN bPreIgnoreWlanAct; + u1Byte prePsTdma; + u1Byte curPsTdma; + u1Byte psTdmaPara[6]; + u1Byte psTdmaDuAdjType; + BOOLEAN bResetTdmaAdjust; + BOOLEAN bPrePsTdmaOn; + BOOLEAN bCurPsTdmaOn; + BOOLEAN bPreBtAutoReport; + BOOLEAN bCurBtAutoReport; + + // sw mechanism + BOOLEAN bPreRfRxLpfShrink; + BOOLEAN bCurRfRxLpfShrink; + u4Byte btRf0x1eBackup; + BOOLEAN bPreLowPenaltyRa; + BOOLEAN bCurLowPenaltyRa; + BOOLEAN bPreDacSwingOn; + u4Byte preDacSwingLvl; + BOOLEAN bCurDacSwingOn; + u4Byte curDacSwingLvl; + BOOLEAN bPreAdcBackOff; + BOOLEAN bCurAdcBackOff; + BOOLEAN bPreAgcTableEn; + BOOLEAN bCurAgcTableEn; + u4Byte preVal0x6c0; + u4Byte curVal0x6c0; + u4Byte preVal0x6c4; + u4Byte curVal0x6c4; + u4Byte preVal0x6c8; + u4Byte curVal0x6c8; + u1Byte preVal0x6cc; + u1Byte curVal0x6cc; + BOOLEAN bLimitedDig; + + u4Byte preRaMask; + u4Byte curRaMask; + + u1Byte curAmpduNumType; + u1Byte preAmpduNumType; + u2Byte backupAmpduMaxNum; + + u1Byte curAmpduTimeType; + u1Byte preAmpduTimeType; + u1Byte backupAmpduMaxTime; + + u1Byte curArfrType; + u1Byte preArfrType; + u4Byte backupArfrCnt1; + u4Byte backupArfrCnt2; + + u1Byte curRetryLimitType; + u1Byte preRetryLimitType; + u2Byte backupRetryLimit; + + // algorithm related + u1Byte preAlgorithm; + u1Byte curAlgorithm; + u1Byte btStatus; + u1Byte wifiChnlInfo[3]; +} COEX_DM_8821A_CSR_2ANT, *PCOEX_DM_8821A_CSR_2ANT; + +typedef struct _COEX_STA_8821A_CSR_2ANT{ + BOOLEAN bBtLinkExist; + BOOLEAN bScoExist; + BOOLEAN bA2dpExist; + BOOLEAN bSlave; + BOOLEAN bHidExist; + BOOLEAN bPanExist; + + BOOLEAN bUnderLps; + BOOLEAN bUnderIps; + u4Byte highPriorityTx; + u4Byte highPriorityRx; + u4Byte lowPriorityTx; + u4Byte lowPriorityRx; + u1Byte btRssi; + u1Byte preBtRssiState; + u1Byte preWifiRssiState[4]; + BOOLEAN bC2hBtInfoReqSent; + u1Byte btInfoC2h[BT_INFO_SRC_8821A_CSR_2ANT_MAX][10]; + u4Byte btInfoC2hCnt[BT_INFO_SRC_8821A_CSR_2ANT_MAX]; + BOOLEAN bC2hBtInquiryPage; + u1Byte btRetryCnt; + u1Byte btInfoExt; +}COEX_STA_8821A_CSR_2ANT, *PCOEX_STA_8821A_CSR_2ANT; + +//=========================================== +// The following is interface which will notify coex module. +//=========================================== +VOID +EXhalbtc8821aCsr2ant_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8821aCsr2ant_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ); +VOID +EXhalbtc8821aCsr2ant_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8821aCsr2ant_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8821aCsr2ant_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8821aCsr2ant_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8821aCsr2ant_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8821aCsr2ant_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8821aCsr2ant_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtc8821aCsr2ant_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ); +VOID +EXhalbtc8821aCsr2ant_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8821aCsr2ant_PnpNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte pnpState + ); +VOID +EXhalbtc8821aCsr2ant_Periodical( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtc8821aCsr2ant_DisplayCoexInfo( + IN PBTC_COEXIST pBtCoexist + ); + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtcOutSrc.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtcOutSrc.h new file mode 100644 index 000000000..25dc3bf71 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/HalBtcOutSrc.h @@ -0,0 +1,748 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __HALBTC_OUT_SRC_H__ +#define __HALBTC_OUT_SRC_H__ + +#define NORMAL_EXEC FALSE +#define FORCE_EXEC TRUE + +#define BTC_RF_OFF 0x0 +#define BTC_RF_ON 0x1 + +#define BTC_RF_A 0x0 +#define BTC_RF_B 0x1 +#define BTC_RF_C 0x2 +#define BTC_RF_D 0x3 + +#define BTC_SMSP SINGLEMAC_SINGLEPHY +#define BTC_DMDP DUALMAC_DUALPHY +#define BTC_DMSP DUALMAC_SINGLEPHY +#define BTC_MP_UNKNOWN 0xff + +#define BT_COEX_ANT_TYPE_PG 0 +#define BT_COEX_ANT_TYPE_ANTDIV 1 +#define BT_COEX_ANT_TYPE_DETECTED 2 + +#define BTC_MIMO_PS_STATIC 0 // 1ss +#define BTC_MIMO_PS_DYNAMIC 1 // 2ss + +#define BTC_RATE_DISABLE 0 +#define BTC_RATE_ENABLE 1 + +// single Antenna definition +#define BTC_ANT_PATH_WIFI 0 +#define BTC_ANT_PATH_BT 1 +#define BTC_ANT_PATH_PTA 2 +// dual Antenna definition +#define BTC_ANT_WIFI_AT_MAIN 0 +#define BTC_ANT_WIFI_AT_AUX 1 +// coupler Antenna definition +#define BTC_ANT_WIFI_AT_CPL_MAIN 0 +#define BTC_ANT_WIFI_AT_CPL_AUX 1 + +typedef enum _BTC_POWERSAVE_TYPE{ + BTC_PS_WIFI_NATIVE = 0, // wifi original power save behavior + BTC_PS_LPS_ON = 1, + BTC_PS_LPS_OFF = 2, + BTC_PS_MAX +} BTC_POWERSAVE_TYPE, *PBTC_POWERSAVE_TYPE; + +typedef enum _BTC_BT_REG_TYPE{ + BTC_BT_REG_RF = 0, + BTC_BT_REG_MODEM = 1, + BTC_BT_REG_BLUEWIZE = 2, + BTC_BT_REG_VENDOR = 3, + BTC_BT_REG_LE = 4, + BTC_BT_REG_MAX +} BTC_BT_REG_TYPE, *PBTC_BT_REG_TYPE; + +typedef enum _BTC_CHIP_INTERFACE{ + BTC_INTF_UNKNOWN = 0, + BTC_INTF_PCI = 1, + BTC_INTF_USB = 2, + BTC_INTF_SDIO = 3, + BTC_INTF_MAX +} BTC_CHIP_INTERFACE, *PBTC_CHIP_INTERFACE; + +typedef enum _BTC_CHIP_TYPE{ + BTC_CHIP_UNDEF = 0, + BTC_CHIP_CSR_BC4 = 1, + BTC_CHIP_CSR_BC8 = 2, + BTC_CHIP_RTL8723A = 3, + BTC_CHIP_RTL8821 = 4, + BTC_CHIP_RTL8723B = 5, + BTC_CHIP_MAX +} BTC_CHIP_TYPE, *PBTC_CHIP_TYPE; + +// following is for wifi link status +#define WIFI_STA_CONNECTED BIT0 +#define WIFI_AP_CONNECTED BIT1 +#define WIFI_HS_CONNECTED BIT2 +#define WIFI_P2P_GO_CONNECTED BIT3 +#define WIFI_P2P_GC_CONNECTED BIT4 + +// following is for command line utility +#define CL_SPRINTF rsprintf +#define CL_PRINTF DCMD_Printf + + +typedef struct _BTC_BOARD_INFO{ + // The following is some board information + u1Byte btChipType; + u1Byte pgAntNum; // pg ant number + u1Byte btdmAntNum; // ant number for btdm + u1Byte btdmAntNumByAntDet; // ant number for btdm after antenna detection + u1Byte btdmAntPos; //Bryant Add to indicate Antenna Position for (pgAntNum = 2) && (btdmAntNum =1) (DPDT+1Ant case) + u1Byte singleAntPath; // current used for 8723b only, 1=>s0, 0=>s1 + u1Byte bTfbgaPackage; //for Antenna detect threshold + u1Byte btdmAntDetFinish; + u1Byte antType; +} BTC_BOARD_INFO, *PBTC_BOARD_INFO; + +typedef enum _BTC_DBG_OPCODE{ + BTC_DBG_SET_COEX_NORMAL = 0x0, + BTC_DBG_SET_COEX_WIFI_ONLY = 0x1, + BTC_DBG_SET_COEX_BT_ONLY = 0x2, + BTC_DBG_SET_COEX_DEC_BT_PWR = 0x3, + BTC_DBG_SET_COEX_BT_AFH_MAP = 0x4, + BTC_DBG_SET_COEX_BT_IGNORE_WLAN_ACT = 0x5, + BTC_DBG_MAX +}BTC_DBG_OPCODE,*PBTC_DBG_OPCODE; + +typedef enum _BTC_RSSI_STATE{ + BTC_RSSI_STATE_HIGH = 0x0, + BTC_RSSI_STATE_MEDIUM = 0x1, + BTC_RSSI_STATE_LOW = 0x2, + BTC_RSSI_STATE_STAY_HIGH = 0x3, + BTC_RSSI_STATE_STAY_MEDIUM = 0x4, + BTC_RSSI_STATE_STAY_LOW = 0x5, + BTC_RSSI_MAX +}BTC_RSSI_STATE,*PBTC_RSSI_STATE; +#define BTC_RSSI_HIGH(_rssi_) ((_rssi_==BTC_RSSI_STATE_HIGH||_rssi_==BTC_RSSI_STATE_STAY_HIGH)? TRUE:FALSE) +#define BTC_RSSI_MEDIUM(_rssi_) ((_rssi_==BTC_RSSI_STATE_MEDIUM||_rssi_==BTC_RSSI_STATE_STAY_MEDIUM)? TRUE:FALSE) +#define BTC_RSSI_LOW(_rssi_) ((_rssi_==BTC_RSSI_STATE_LOW||_rssi_==BTC_RSSI_STATE_STAY_LOW)? TRUE:FALSE) + +typedef enum _BTC_WIFI_ROLE{ + BTC_ROLE_STATION = 0x0, + BTC_ROLE_AP = 0x1, + BTC_ROLE_IBSS = 0x2, + BTC_ROLE_HS_MODE = 0x3, + BTC_ROLE_MAX +}BTC_WIFI_ROLE,*PBTC_WIFI_ROLE; + +typedef enum _BTC_WIRELESS_FREQ{ + BTC_FREQ_2_4G = 0x0, + BTC_FREQ_5G = 0x1, + BTC_FREQ_MAX +}BTC_WIRELESS_FREQ,*PBTC_WIRELESS_FREQ; + +typedef enum _BTC_WIFI_BW_MODE{ + BTC_WIFI_BW_LEGACY = 0x0, + BTC_WIFI_BW_HT20 = 0x1, + BTC_WIFI_BW_HT40 = 0x2, + BTC_WIFI_BW_HT80 = 0x3, + BTC_WIFI_BW_HT160 = 0x4, + BTC_WIFI_BW_MAX +}BTC_WIFI_BW_MODE,*PBTC_WIFI_BW_MODE; + +typedef enum _BTC_WIFI_TRAFFIC_DIR{ + BTC_WIFI_TRAFFIC_TX = 0x0, + BTC_WIFI_TRAFFIC_RX = 0x1, + BTC_WIFI_TRAFFIC_MAX +}BTC_WIFI_TRAFFIC_DIR,*PBTC_WIFI_TRAFFIC_DIR; + +typedef enum _BTC_WIFI_PNP{ + BTC_WIFI_PNP_WAKE_UP = 0x0, + BTC_WIFI_PNP_SLEEP = 0x1, + BTC_WIFI_PNP_MAX +}BTC_WIFI_PNP,*PBTC_WIFI_PNP; + +typedef enum _BTC_IOT_PEER +{ + BTC_IOT_PEER_UNKNOWN = 0, + BTC_IOT_PEER_REALTEK = 1, + BTC_IOT_PEER_REALTEK_92SE = 2, + BTC_IOT_PEER_BROADCOM = 3, + BTC_IOT_PEER_RALINK = 4, + BTC_IOT_PEER_ATHEROS = 5, + BTC_IOT_PEER_CISCO = 6, + BTC_IOT_PEER_MERU = 7, + BTC_IOT_PEER_MARVELL = 8, + BTC_IOT_PEER_REALTEK_SOFTAP = 9,// peer is RealTek SOFT_AP, by Bohn, 2009.12.17 + BTC_IOT_PEER_SELF_SOFTAP = 10, // Self is SoftAP + BTC_IOT_PEER_AIRGO = 11, + BTC_IOT_PEER_INTEL = 12, + BTC_IOT_PEER_RTK_APCLIENT = 13, + BTC_IOT_PEER_REALTEK_81XX = 14, + BTC_IOT_PEER_REALTEK_WOW = 15, + BTC_IOT_PEER_REALTEK_JAGUAR_BCUTAP = 16, + BTC_IOT_PEER_REALTEK_JAGUAR_CCUTAP = 17, + BTC_IOT_PEER_MAX, +}BTC_IOT_PEER, *PBTC_IOT_PEER; + +//for 8723b-d cut large current issue +typedef enum _BT_WIFI_COEX_STATE{ + BTC_WIFI_STAT_INIT, + BTC_WIFI_STAT_IQK, + BTC_WIFI_STAT_NORMAL_OFF, + BTC_WIFI_STAT_MP_OFF, + BTC_WIFI_STAT_NORMAL, + BTC_WIFI_STAT_ANT_DIV, + BTC_WIFI_STAT_MAX +}BT_WIFI_COEX_STATE,*PBT_WIFI_COEX_STATE; + +typedef enum _BT_ANT_TYPE{ + BTC_ANT_TYPE_0, + BTC_ANT_TYPE_1, + BTC_ANT_TYPE_2, + BTC_ANT_TYPE_3, + BTC_ANT_TYPE_4, + BTC_ANT_TYPE_MAX +}BT_ANT_TYPE,*PBT_ANT_TYPE; + +// defined for BFP_BTC_GET +typedef enum _BTC_GET_TYPE{ + // type BOOLEAN + BTC_GET_BL_HS_OPERATION, + BTC_GET_BL_HS_CONNECTING, + BTC_GET_BL_WIFI_CONNECTED, + BTC_GET_BL_WIFI_BUSY, + BTC_GET_BL_WIFI_SCAN, + BTC_GET_BL_WIFI_LINK, + BTC_GET_BL_WIFI_ROAM, + BTC_GET_BL_WIFI_4_WAY_PROGRESS, + BTC_GET_BL_WIFI_UNDER_5G, + BTC_GET_BL_WIFI_AP_MODE_ENABLE, + BTC_GET_BL_WIFI_ENABLE_ENCRYPTION, + BTC_GET_BL_WIFI_UNDER_B_MODE, + BTC_GET_BL_EXT_SWITCH, + BTC_GET_BL_WIFI_IS_IN_MP_MODE, + BTC_GET_BL_IS_ASUS_8723B, + + // type s4Byte + BTC_GET_S4_WIFI_RSSI, + BTC_GET_S4_HS_RSSI, + + // type u4Byte + BTC_GET_U4_WIFI_BW, + BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, + BTC_GET_U4_WIFI_FW_VER, + BTC_GET_U4_WIFI_LINK_STATUS, + BTC_GET_U4_BT_PATCH_VER, + + // type u1Byte + BTC_GET_U1_WIFI_DOT11_CHNL, + BTC_GET_U1_WIFI_CENTRAL_CHNL, + BTC_GET_U1_WIFI_HS_CHNL, + BTC_GET_U1_MAC_PHY_MODE, + BTC_GET_U1_AP_NUM, + BTC_GET_U1_ANT_TYPE, + BTC_GET_U1_IOT_PEER, + + //===== for 1Ant ====== + BTC_GET_U1_LPS_MODE, + + BTC_GET_MAX +}BTC_GET_TYPE,*PBTC_GET_TYPE; + +// defined for BFP_BTC_SET +typedef enum _BTC_SET_TYPE{ + // type BOOLEAN + BTC_SET_BL_BT_DISABLE, + BTC_SET_BL_BT_TRAFFIC_BUSY, + BTC_SET_BL_BT_LIMITED_DIG, + BTC_SET_BL_FORCE_TO_ROAM, + BTC_SET_BL_TO_REJ_AP_AGG_PKT, + BTC_SET_BL_BT_CTRL_AGG_SIZE, + BTC_SET_BL_INC_SCAN_DEV_NUM, + BTC_SET_BL_BT_TX_RX_MASK, + BTC_SET_BL_MIRACAST_PLUS_BT, + + // type u1Byte + BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, + BTC_SET_U1_AGG_BUF_SIZE, + + // type trigger some action + BTC_SET_ACT_GET_BT_RSSI, + BTC_SET_ACT_AGGREGATE_CTRL, + //===== for 1Ant ====== + // type BOOLEAN + + // type u1Byte + BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE, + BTC_SET_U1_LPS_VAL, + BTC_SET_U1_RPWM_VAL, + // type trigger some action + BTC_SET_ACT_LEAVE_LPS, + BTC_SET_ACT_ENTER_LPS, + BTC_SET_ACT_NORMAL_LPS, + BTC_SET_ACT_DISABLE_LOW_POWER, + BTC_SET_ACT_UPDATE_RAMASK, + BTC_SET_ACT_SEND_MIMO_PS, + // BT Coex related + BTC_SET_ACT_CTRL_BT_INFO, + BTC_SET_ACT_CTRL_BT_COEX, + BTC_SET_ACT_CTRL_8723B_ANT, + //================= + BTC_SET_MAX +}BTC_SET_TYPE,*PBTC_SET_TYPE; + +typedef enum _BTC_DBG_DISP_TYPE{ + BTC_DBG_DISP_COEX_STATISTICS = 0x0, + BTC_DBG_DISP_BT_LINK_INFO = 0x1, + BTC_DBG_DISP_WIFI_STATUS = 0x2, + BTC_DBG_DISP_MAX +}BTC_DBG_DISP_TYPE,*PBTC_DBG_DISP_TYPE; + +typedef enum _BTC_NOTIFY_TYPE_IPS{ + BTC_IPS_LEAVE = 0x0, + BTC_IPS_ENTER = 0x1, + BTC_IPS_MAX +}BTC_NOTIFY_TYPE_IPS,*PBTC_NOTIFY_TYPE_IPS; +typedef enum _BTC_NOTIFY_TYPE_LPS{ + BTC_LPS_DISABLE = 0x0, + BTC_LPS_ENABLE = 0x1, + BTC_LPS_MAX +}BTC_NOTIFY_TYPE_LPS,*PBTC_NOTIFY_TYPE_LPS; +typedef enum _BTC_NOTIFY_TYPE_SCAN{ + BTC_SCAN_FINISH = 0x0, + BTC_SCAN_START = 0x1, + BTC_SCAN_MAX +}BTC_NOTIFY_TYPE_SCAN,*PBTC_NOTIFY_TYPE_SCAN; +typedef enum _BTC_NOTIFY_TYPE_ASSOCIATE{ + BTC_ASSOCIATE_FINISH = 0x0, + BTC_ASSOCIATE_START = 0x1, + BTC_ASSOCIATE_MAX +}BTC_NOTIFY_TYPE_ASSOCIATE,*PBTC_NOTIFY_TYPE_ASSOCIATE; +typedef enum _BTC_NOTIFY_TYPE_MEDIA_STATUS{ + BTC_MEDIA_DISCONNECT = 0x0, + BTC_MEDIA_CONNECT = 0x1, + BTC_MEDIA_MAX +}BTC_NOTIFY_TYPE_MEDIA_STATUS,*PBTC_NOTIFY_TYPE_MEDIA_STATUS; +typedef enum _BTC_NOTIFY_TYPE_SPECIAL_PACKET{ + BTC_PACKET_UNKNOWN = 0x0, + BTC_PACKET_DHCP = 0x1, + BTC_PACKET_ARP = 0x2, + BTC_PACKET_EAPOL = 0x3, + BTC_PACKET_MAX +}BTC_NOTIFY_TYPE_SPECIAL_PACKET,*PBTC_NOTIFY_TYPE_SPECIAL_PACKET; +typedef enum _BTC_NOTIFY_TYPE_STACK_OPERATION{ + BTC_STACK_OP_NONE = 0x0, + BTC_STACK_OP_INQ_PAGE_PAIR_START = 0x1, + BTC_STACK_OP_INQ_PAGE_PAIR_FINISH = 0x2, + BTC_STACK_OP_MAX +}BTC_NOTIFY_TYPE_STACK_OPERATION,*PBTC_NOTIFY_TYPE_STACK_OPERATION; + +//Bryant Add +typedef enum _BTC_ANTENNA_POS{ + BTC_ANTENNA_AT_MAIN_PORT = 0x1, + BTC_ANTENNA_AT_AUX_PORT = 0x2, +}BTC_ANTENNA_POS,*PBTC_ANTENNA_POS; + +//Bryant Add +typedef enum _BTC_BT_OFFON{ + BTC_BT_OFF = 0x0, + BTC_BT_ON = 0x1, +}BTC_BTOFFON,*PBTC_BT_OFFON; + +typedef u1Byte +(*BFP_BTC_R1)( + IN PVOID pBtcContext, + IN u4Byte RegAddr + ); +typedef u2Byte +(*BFP_BTC_R2)( + IN PVOID pBtcContext, + IN u4Byte RegAddr + ); +typedef u4Byte +(*BFP_BTC_R4)( + IN PVOID pBtcContext, + IN u4Byte RegAddr + ); +typedef VOID +(*BFP_BTC_W1)( + IN PVOID pBtcContext, + IN u4Byte RegAddr, + IN u1Byte Data + ); +typedef VOID +(*BFP_BTC_W1_BIT_MASK)( + IN PVOID pBtcContext, + IN u4Byte regAddr, + IN u1Byte bitMask, + IN u1Byte data1b + ); +typedef VOID +(*BFP_BTC_W2)( + IN PVOID pBtcContext, + IN u4Byte RegAddr, + IN u2Byte Data + ); +typedef VOID +(*BFP_BTC_W4)( + IN PVOID pBtcContext, + IN u4Byte RegAddr, + IN u4Byte Data + ); +typedef VOID +(*BFP_BTC_LOCAL_REG_W1)( + IN PVOID pBtcContext, + IN u4Byte RegAddr, + IN u1Byte Data + ); +typedef VOID +(*BFP_BTC_SET_BB_REG)( + IN PVOID pBtcContext, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); +typedef u4Byte +(*BFP_BTC_GET_BB_REG)( + IN PVOID pBtcContext, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); +typedef VOID +(*BFP_BTC_SET_RF_REG)( + IN PVOID pBtcContext, + IN u1Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); +typedef u4Byte +(*BFP_BTC_GET_RF_REG)( + IN PVOID pBtcContext, + IN u1Byte eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); +typedef VOID +(*BFP_BTC_FILL_H2C)( + IN PVOID pBtcContext, + IN u1Byte elementId, + IN u4Byte cmdLen, + IN pu1Byte pCmdBuffer + ); + +typedef BOOLEAN +(*BFP_BTC_GET)( + IN PVOID pBtCoexist, + IN u1Byte getType, + OUT PVOID pOutBuf + ); + +typedef BOOLEAN +(*BFP_BTC_SET)( + IN PVOID pBtCoexist, + IN u1Byte setType, + OUT PVOID pInBuf + ); +typedef u2Byte +(*BFP_BTC_SET_BT_REG)( + IN PVOID pBtcContext, + IN u1Byte regType, + IN u4Byte offset, + IN u4Byte value + ); +typedef BOOLEAN +(*BFP_BTC_SET_BT_ANT_DETECTION)( + IN PVOID pBtcContext, + IN u1Byte txTime, + IN u1Byte btChnl + ); +typedef u2Byte +(*BFP_BTC_GET_BT_REG)( + IN PVOID pBtcContext, + IN u1Byte regType, + IN u4Byte offset, + IN pu4Byte data + ); +typedef VOID +(*BFP_BTC_DISP_DBG_MSG)( + IN PVOID pBtCoexist, + IN u1Byte dispType + ); + +typedef struct _BTC_BT_INFO{ + BOOLEAN bBtDisabled; + u1Byte rssiAdjustForAgcTableOn; + u1Byte rssiAdjustFor1AntCoexType; + BOOLEAN bPreBtCtrlAggBufSize; + BOOLEAN bBtCtrlAggBufSize; + BOOLEAN bPreRejectAggPkt; + BOOLEAN bRejectAggPkt; + BOOLEAN bIncreaseScanDevNum; + BOOLEAN bBtTxRxMask; + u1Byte preAggBufSize; + u1Byte aggBufSize; + BOOLEAN bBtBusy; + BOOLEAN bLimitedDig; + u2Byte btHciVer; + u2Byte btRealFwVer; + u1Byte btFwVer; + u4Byte getBtFwVerCnt; + BOOLEAN bMiracastPlusBt; + + BOOLEAN bBtDisableLowPwr; + + BOOLEAN bBtCtrlLps; + BOOLEAN bBtLpsOn; + BOOLEAN bForceToRoam; // for 1Ant solution + u1Byte lpsVal; + u1Byte rpwmVal; + u4Byte raMask; +} BTC_BT_INFO, *PBTC_BT_INFO; + +typedef struct _BTC_STACK_INFO{ + BOOLEAN bProfileNotified; + u2Byte hciVersion; // stack hci version + u1Byte numOfLink; + BOOLEAN bBtLinkExist; + BOOLEAN bScoExist; + BOOLEAN bAclExist; + BOOLEAN bA2dpExist; + BOOLEAN bHidExist; + u1Byte numOfHid; + BOOLEAN bPanExist; + BOOLEAN bUnknownAclExist; + s1Byte minBtRssi; +} BTC_STACK_INFO, *PBTC_STACK_INFO; + +typedef struct _BTC_BT_LINK_INFO{ + BOOLEAN bBtLinkExist; + BOOLEAN bBtHiPriLinkExist; + BOOLEAN bScoExist; + BOOLEAN bScoOnly; + BOOLEAN bA2dpExist; + BOOLEAN bA2dpOnly; + BOOLEAN bHidExist; + BOOLEAN bHidOnly; + BOOLEAN bPanExist; + BOOLEAN bPanOnly; + BOOLEAN bSlaveRole; + BOOLEAN bAclBusy; +} BTC_BT_LINK_INFO, *PBTC_BT_LINK_INFO; + +typedef struct _BTC_STATISTICS{ + u4Byte cntBind; + u4Byte cntPowerOn; + u4Byte cntPreLoadFirmware; + u4Byte cntInitHwConfig; + u4Byte cntInitCoexDm; + u4Byte cntIpsNotify; + u4Byte cntLpsNotify; + u4Byte cntScanNotify; + u4Byte cntConnectNotify; + u4Byte cntMediaStatusNotify; + u4Byte cntSpecialPacketNotify; + u4Byte cntBtInfoNotify; + u4Byte cntRfStatusNotify; + u4Byte cntPeriodical; + u4Byte cntCoexDmSwitch; + u4Byte cntStackOperationNotify; + u4Byte cntDbgCtrl; +} BTC_STATISTICS, *PBTC_STATISTICS; + +typedef struct _BTC_COEXIST{ + BOOLEAN bBinded; // make sure only one adapter can bind the data context + PVOID Adapter; // default adapter + BTC_BOARD_INFO boardInfo; + BTC_BT_INFO btInfo; // some bt info referenced by non-bt module + BTC_STACK_INFO stackInfo; + BTC_BT_LINK_INFO btLinkInfo; + BTC_CHIP_INTERFACE chipInterface; + + BOOLEAN bInitilized; + BOOLEAN bStopCoexDm; + BOOLEAN bManualControl; + pu1Byte cliBuf; + BTC_STATISTICS statistics; + u1Byte pwrModeVal[10]; + + // function pointers + // io related + BFP_BTC_R1 fBtcRead1Byte; + BFP_BTC_W1 fBtcWrite1Byte; + BFP_BTC_W1_BIT_MASK fBtcWrite1ByteBitMask; + BFP_BTC_R2 fBtcRead2Byte; + BFP_BTC_W2 fBtcWrite2Byte; + BFP_BTC_R4 fBtcRead4Byte; + BFP_BTC_W4 fBtcWrite4Byte; + BFP_BTC_LOCAL_REG_W1 fBtcWriteLocalReg1Byte; + // read/write bb related + BFP_BTC_SET_BB_REG fBtcSetBbReg; + BFP_BTC_GET_BB_REG fBtcGetBbReg; + + // read/write rf related + BFP_BTC_SET_RF_REG fBtcSetRfReg; + BFP_BTC_GET_RF_REG fBtcGetRfReg; + + // fill h2c related + BFP_BTC_FILL_H2C fBtcFillH2c; + // other + BFP_BTC_DISP_DBG_MSG fBtcDispDbgMsg; + // normal get/set related + BFP_BTC_GET fBtcGet; + BFP_BTC_SET fBtcSet; + + BFP_BTC_GET_BT_REG fBtcGetBtReg; + BFP_BTC_SET_BT_REG fBtcSetBtReg; + + BFP_BTC_SET_BT_ANT_DETECTION fBtcSetBtAntDetection; +} BTC_COEXIST, *PBTC_COEXIST; + +extern BTC_COEXIST GLBtCoexist; + +BOOLEAN +EXhalbtcoutsrc_InitlizeVariables( + IN PVOID Adapter + ); +VOID +EXhalbtcoutsrc_PowerOnSetting( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtcoutsrc_PreLoadFirmware( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtcoutsrc_InitHwConfig( + IN PBTC_COEXIST pBtCoexist, + IN BOOLEAN bWifiOnly + ); +VOID +EXhalbtcoutsrc_InitCoexDm( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtcoutsrc_IpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtcoutsrc_LpsNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtcoutsrc_ScanNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtcoutsrc_ConnectNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte action + ); +VOID +EXhalbtcoutsrc_MediaStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN RT_MEDIA_STATUS mediaStatus + ); +VOID +EXhalbtcoutsrc_SpecialPacketNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte pktType + ); +VOID +EXhalbtcoutsrc_BtInfoNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ); +VOID +EXhalbtcoutsrc_RfStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtcoutsrc_StackOperationNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ); +VOID +EXhalbtcoutsrc_HaltNotify( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtcoutsrc_PnpNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte pnpState + ); +VOID +EXhalbtcoutsrc_ScoreBoardStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN pu1Byte tmpBuf, + IN u1Byte length + ); +VOID +EXhalbtcoutsrc_CoexDmSwitch( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtcoutsrc_Periodical( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtcoutsrc_DbgControl( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte opCode, + IN u1Byte opLen, + IN pu1Byte pData + ); +VOID +EXhalbtcoutsrc_AntennaDetection( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte centFreq, + IN u4Byte offset, + IN u4Byte span, + IN u4Byte seconds + ); +VOID +EXhalbtcoutsrc_StackUpdateProfileInfo( + VOID + ); +VOID +EXhalbtcoutsrc_SetHciVersion( + IN u2Byte hciVersion + ); +VOID +EXhalbtcoutsrc_SetBtPatchVersion( + IN u2Byte btHciVersion, + IN u2Byte btPatchVersion + ); +VOID +EXhalbtcoutsrc_UpdateMinBtRssi( + IN s1Byte btRssi + ); +#if 0 +VOID +EXhalbtcoutsrc_SetBtExist( + IN BOOLEAN bBtExist + ); +#endif +VOID +EXhalbtcoutsrc_SetChipType( + IN u1Byte chipType + ); +VOID +EXhalbtcoutsrc_SetAntNum( + IN u1Byte type, + IN u1Byte antNum + ); +VOID +EXhalbtcoutsrc_SetSingleAntPath( + IN u1Byte singleAntPath + ); +VOID +EXhalbtcoutsrc_DisplayBtCoexInfo( + IN PBTC_COEXIST pBtCoexist + ); +VOID +EXhalbtcoutsrc_DisplayAntDetection( + IN PBTC_COEXIST pBtCoexist + ); + +#endif diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/Mp_Precomp.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/Mp_Precomp.h new file mode 100644 index 000000000..62abb5e28 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/btc/Mp_Precomp.h @@ -0,0 +1,89 @@ +/****************************************************************************** + * + * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __MP_PRECOMP_H__ +#define __MP_PRECOMP_H__ + +#include +#include + +#define BT_TMP_BUF_SIZE 100 + +#ifdef PLATFORM_LINUX +#define rsprintf snprintf +#elif defined(PLATFORM_WINDOWS) +#define rsprintf sprintf_s +#endif + +#define DCMD_Printf DBG_BT_INFO + +#define delay_ms(ms) rtw_mdelay_os(ms) + +#ifdef bEnable +#undef bEnable +#endif + +#define WPP_SOFTWARE_TRACE 0 + +typedef enum _BTC_MSG_COMP_TYPE{ + COMP_COEX = 0, + COMP_MAX +}BTC_MSG_COMP_TYPE; +extern u4Byte GLBtcDbgType[]; + +#define DBG_OFF 0 +#define DBG_SEC 1 +#define DBG_SERIOUS 2 +#define DBG_WARNING 3 +#define DBG_LOUD 4 +#define DBG_TRACE 5 + +#if DBG +#ifdef RT_TRACE +#undef RT_TRACE +#define RT_TRACE(dbgtype, dbgflag, printstr)\ +do {\ + if (GLBtcDbgType[dbgtype] & BIT(dbgflag))\ + {\ + DbgPrint printstr;\ + }\ +} while (0) +#endif +#else +#define RT_TRACE(dbgtype, dbgflag, printstr) +#endif + +#include "HalBtcOutSrc.h" +#include "HalBtc8188c2Ant.h" +#include "HalBtc8192d2Ant.h" +#include "HalBtc8192e1Ant.h" +#include "HalBtc8192e2Ant.h" +#include "HalBtc8723a1Ant.h" +#include "HalBtc8723a2Ant.h" +#include "HalBtc8723b1Ant.h" +#include "HalBtc8723b2Ant.h" +#include "HalBtc8812a1Ant.h" +#include "HalBtc8812a2Ant.h" +#include "HalBtc8821a1Ant.h" +#include "HalBtc8821a2Ant.h" +#include "HalBtc8821aCsr2Ant.h" +#include "HalBtc8703b1Ant.h" +#include "HalBtc8703b2Ant.h" + +#endif // __MP_PRECOMP_H__ diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/efuse/efuse_mask.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/efuse/efuse_mask.h new file mode 100644 index 000000000..4f58ebe49 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/efuse/efuse_mask.h @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#if DEV_BUS_TYPE == RT_USB_INTERFACE + + #if defined(CONFIG_RTL8188E) + #include "rtl8188e/HalEfuseMask8188E_USB.h" + #endif + + #if defined(CONFIG_RTL8812A) + #include "rtl8812a/HalEfuseMask8812A_USB.h" + #endif + + #if defined(CONFIG_RTL8821A) + #include "rtl8812a/HalEfuseMask8821A_USB.h" + #endif + + #if defined(CONFIG_RTL8192E) + #include "rtl8192e/HalEfuseMask8192E_USB.h" + #endif + + #if defined(CONFIG_RTL8723B) + #include "rtl8723b/HalEfuseMask8723B_USB.h" + #endif + + #if defined(CONFIG_RTL8814A) + #include "rtl8814a/HalEfuseMask8814A_USB.h" + #endif + + #if defined(CONFIG_RTL8703B) + #include "rtl8703b/HalEfuseMask8703B_USB.h" + #endif + + #if defined(CONFIG_RTL8188F) + #include "rtl8188f/HalEfuseMask8188F_USB.h" + #endif + +#elif DEV_BUS_TYPE == RT_PCI_INTERFACE + + #if defined(CONFIG_RTL8188E) + #include "rtl8188e/HalEfuseMask8188E_PCIE.h" + #endif + + #if defined(CONFIG_RTL8812A) + #include "rtl8812a/HalEfuseMask8812A_PCIE.h" + #endif + + #if defined(CONFIG_RTL8821A) + #include "rtl8812a/HalEfuseMask8821A_PCIE.h" + #endif + + #if defined(CONFIG_RTL8192E) + #include "rtl8192e/HalEfuseMask8192E_PCIE.h" + #endif + + #if defined(CONFIG_RTL8723B) + #include "rtl8723b/HalEfuseMask8723B_PCIE.h" + #endif + + #if defined(CONFIG_RTL8814A) + #include "rtl8814a/HalEfuseMask8814A_PCIE.h" + #endif + + #if defined(CONFIG_RTL8703B) + #include "rtl8703b/HalEfuseMask8703B_PCIE.h" + #endif + +#elif DEV_BUS_TYPE == RT_SDIO_INTERFACE + + #if defined(CONFIG_RTL8188E) + #include "rtl8188e/HalEfuseMask8188E_SDIO.h" + #endif + + #if defined(CONFIG_RTL8703B) + #include "rtl8703b/HalEfuseMask8703B_SDIO.h" + #endif + + #if defined(CONFIG_RTL8188F) + #include "rtl8188f/HalEfuseMask8188F_SDIO.h" + #endif + +#endif \ No newline at end of file diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/efuse/rtl8188f/HalEfuseMask8188F_SDIO.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/efuse/rtl8188f/HalEfuseMask8188F_SDIO.c new file mode 100644 index 000000000..4840acb6a --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/efuse/rtl8188f/HalEfuseMask8188F_SDIO.c @@ -0,0 +1,103 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +//#include "Mp_Precomp.h" +//#include "../odm_precomp.h" + +#include + +#include "HalEfuseMask8188F_SDIO.h" + + + +/****************************************************************************** +* MSDIO.TXT +******************************************************************************/ + +u1Byte Array_MP_8188F_MSDIO[] = { +0xFF, +0xF3, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x0F, +0xF1, +0xFF, +0xFF, +0xFF, +0xFF, +0xFF, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, +0x00, + +}; + +u2Byte +EFUSE_GetArrayLen_MP_8188F_MSDIO(VOID) +{ + return sizeof(Array_MP_8188F_MSDIO)/sizeof(u1Byte); +} + +VOID +EFUSE_GetMaskArray_MP_8188F_MSDIO( + IN OUT pu1Byte Array + ) +{ + u2Byte len = EFUSE_GetArrayLen_MP_8188F_MSDIO(), i = 0; + + for (i = 0; i < len; ++i) + Array[i] = Array_MP_8188F_MSDIO[i]; +} +BOOLEAN +EFUSE_IsAddressMasked_MP_8188F_MSDIO( + IN u2Byte Offset + ) +{ + int r = Offset/16; + int c = (Offset%16) / 2; + int result = 0; + + if (c < 4) // Upper double word + result = (Array_MP_8188F_MSDIO[r] & (0x10 << c)); + else + result = (Array_MP_8188F_MSDIO[r] & (0x01 << (c-4))); + + return (result > 0) ? 0 : 1; +} + + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/efuse/rtl8188f/HalEfuseMask8188F_SDIO.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/efuse/rtl8188f/HalEfuseMask8188F_SDIO.h new file mode 100644 index 000000000..3fa4e3e7e --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/efuse/rtl8188f/HalEfuseMask8188F_SDIO.h @@ -0,0 +1,41 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + + + +/****************************************************************************** +* MSDIO.TXT +******************************************************************************/ + + +u2Byte +EFUSE_GetArrayLen_MP_8188F_MSDIO(VOID); + +VOID +EFUSE_GetMaskArray_MP_8188F_MSDIO( + IN OUT pu1Byte Array +); + +BOOLEAN +EFUSE_IsAddressMasked_MP_8188F_MSDIO( // TC: Test Chip, MP: MP Chip + IN u2Byte Offset +); + + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/efuse/rtl8188f/HalEfuseMask8188F_USB.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/efuse/rtl8188f/HalEfuseMask8188F_USB.c new file mode 100644 index 000000000..dddc3fa67 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/efuse/rtl8188f/HalEfuseMask8188F_USB.c @@ -0,0 +1,101 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +//#include "Mp_Precomp.h" +//#include "../odm_precomp.h" + +#include + +#include "HalEfuseMask8188F_USB.h" + + +/****************************************************************************** +* MUSB.TXT +******************************************************************************/ + +u1Byte Array_MP_8188F_MUSB[] = { + 0xFF, + 0xF3, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x0F, + 0xF1, + 0xFF, + 0xFF, + 0xFF, + 0xFF, + 0x70, + 0x00, + 0x12, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, +}; + +u2Byte +EFUSE_GetArrayLen_MP_8188F_MUSB(VOID) +{ + return sizeof(Array_MP_8188F_MUSB)/sizeof(u1Byte); +} + +VOID +EFUSE_GetMaskArray_MP_8188F_MUSB( + IN OUT pu1Byte Array + ) +{ + u2Byte len = EFUSE_GetArrayLen_MP_8188F_MUSB(), i = 0; + + for (i = 0; i < len; ++i) + Array[i] = Array_MP_8188F_MUSB[i]; +} +BOOLEAN +EFUSE_IsAddressMasked_MP_8188F_MUSB( + IN u2Byte Offset + ) +{ + int r = Offset/16; + int c = (Offset%16) / 2; + int result = 0; + + if (c < 4) // Upper double word + result = (Array_MP_8188F_MUSB[r] & (0x10 << c)); + else + result = (Array_MP_8188F_MUSB[r] & (0x01 << (c-4))); + + return (result > 0) ? 0 : 1; +} + + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/efuse/rtl8188f/HalEfuseMask8188F_USB.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/efuse/rtl8188f/HalEfuseMask8188F_USB.h new file mode 100644 index 000000000..e4890cad0 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/efuse/rtl8188f/HalEfuseMask8188F_USB.h @@ -0,0 +1,42 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + + + +/****************************************************************************** +* MUSB.TXT +******************************************************************************/ + + +u2Byte +EFUSE_GetArrayLen_MP_8188F_MUSB(VOID); + +VOID +EFUSE_GetMaskArray_MP_8188F_MUSB( + IN OUT pu1Byte Array +); + +BOOLEAN +EFUSE_IsAddressMasked_MP_8188F_MUSB( // TC: Test Chip, MP: MP Chip + IN u2Byte Offset +); + + + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_btcoex.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_btcoex.c new file mode 100644 index 000000000..29a64c2d4 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_btcoex.c @@ -0,0 +1,3690 @@ +/****************************************************************************** + * + * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define __HAL_BTCOEX_C__ + +#ifdef CONFIG_BT_COEXIST + +#include +#include +#include + +//==================================== +// Global variables +//==================================== +const char *const BtProfileString[] = +{ + "NONE", + "A2DP", + "PAN", + "HID", + "SCO", +}; + +const char *const BtSpecString[] = +{ + "1.0b", + "1.1", + "1.2", + "2.0+EDR", + "2.1+EDR", + "3.0+HS", + "4.0", +}; + +const char *const BtLinkRoleString[] = +{ + "Master", + "Slave", +}; + +const char *const h2cStaString[] = +{ + "successful", + "h2c busy", + "rf off", + "fw not read", +}; + +const char *const ioStaString[] = +{ + "success", + "can not IO", + "rf off", + "fw not read", + "wait io timeout", + "invalid len", + "idle Q empty", + "insert waitQ fail", + "unknown fail", + "wrong level", + "h2c stopped", +}; + +const char *const GLBtcWifiBwString[]={ + "11bg", + "HT20", + "HT40", + "HT80", + "HT160" +}; + +const char *const GLBtcWifiFreqString[]={ + "2.4G", + "5G" +}; + +const char *const GLBtcIotPeerString[] = { + "UNKNOWN", + "REALTEK", + "REALTEK_92SE", + "BROADCOM", + "RALINK", + "ATHEROS", + "CISCO", + "MERU", + "MARVELL", + "REALTEK_SOFTAP", /* peer is RealTek SOFT_AP, by Bohn, 2009.12.17 */ + "SELF_SOFTAP", /* Self is SoftAP */ + "AIRGO", + "INTEL", + "RTK_APCLIENT", + "REALTEK_81XX", + "REALTEK_WOW", + "REALTEK_JAGUAR_BCUTAP", + "REALTEK_JAGUAR_CCUTAP" +}; + +#define HALBTCOUTSRC_AGG_CHK_WINDOW_IN_MS 8000 + +BTC_COEXIST GLBtCoexist; +u8 GLBtcWiFiInScanState; +u8 GLBtcWiFiInIQKState; +u8 GLBtcWiFiInIPS; +u8 GLBtcWiFiInLPS; +u8 GLBtcBtCoexAliveRegistered; + +/* + * BT control H2C/C2H + */ +/* EXT_EID */ +typedef enum _bt_ext_eid { + C2H_WIFI_FW_ACTIVE_RSP = 0, + C2H_TRIG_BY_BT_FW +} BT_EXT_EID; + +/* C2H_STATUS */ +typedef enum _bt_c2h_status { + BT_STATUS_OK = 0, + BT_STATUS_VERSION_MISMATCH, + BT_STATUS_UNKNOWN_OPCODE, + BT_STATUS_ERROR_PARAMETER +} BT_C2H_STATUS; + +/* C2H BT OP CODES */ +typedef enum _bt_op_code { + BT_OP_GET_BT_VERSION = 0, + BT_OP_WRITE_REG_ADDR = 12, + BT_OP_WRITE_REG_VALUE, + BT_OP_READ_REG = 17 +} BT_OP_CODE; + +#define BTC_MPOPER_TIMEOUT 50 /* unit: ms */ + +#define C2H_MAX_SIZE 16 +u8 GLBtcBtMpOperSeq; +_mutex GLBtcBtMpOperLock; +_timer GLBtcBtMpOperTimer; +_sema GLBtcBtMpRptSema; +u8 GLBtcBtMpRptSeq; +u8 GLBtcBtMpRptStatus; +u8 GLBtcBtMpRptRsp[C2H_MAX_SIZE]; +u8 GLBtcBtMpRptRspSize; +u8 GLBtcBtMpRptWait; +u8 GLBtcBtMpRptWiFiOK; +u8 GLBtcBtMpRptBTOK; + +/* + * Debug + */ +u32 GLBtcDbgType[COMP_MAX]; +u8 GLBtcDbgBuf[BT_TMP_BUF_SIZE]; + +typedef struct _btcoexdbginfo +{ + u8 *info; + u32 size; // buffer total size + u32 len; // now used length +} BTCDBGINFO, *PBTCDBGINFO; + +BTCDBGINFO GLBtcDbgInfo; + +#define BT_Operation(Adapter) _FALSE + +static void DBG_BT_INFO_INIT(PBTCDBGINFO pinfo, u8 *pbuf, u32 size) +{ + if (NULL == pinfo) return; + + _rtw_memset(pinfo, 0, sizeof(BTCDBGINFO)); + + if (pbuf && size) { + pinfo->info = pbuf; + pinfo->size = size; + } +} + +void DBG_BT_INFO(u8 *dbgmsg) +{ + PBTCDBGINFO pinfo; + u32 msglen, buflen; + u8 *pbuf; + + + pinfo = &GLBtcDbgInfo; + + if (NULL == pinfo->info) + return; + + msglen = strlen(dbgmsg); + if (pinfo->len + msglen > pinfo->size) + return; + + pbuf = pinfo->info + pinfo->len; + _rtw_memcpy(pbuf, dbgmsg, msglen); + pinfo->len += msglen; +} + +//==================================== +// Debug related function +//==================================== +static u8 halbtcoutsrc_IsBtCoexistAvailable(PBTC_COEXIST pBtCoexist) +{ + if (!pBtCoexist->bBinded || + NULL == pBtCoexist->Adapter) + { + return _FALSE; + } + return _TRUE; +} + +static void halbtcoutsrc_DbgInit(void) +{ + u8 i; + + for (i = 0; i < COMP_MAX; i++) + GLBtcDbgType[i] = 0; +} + +static u8 halbtcoutsrc_IsCsrBtCoex(PBTC_COEXIST pBtCoexist) +{ + if (pBtCoexist->boardInfo.btChipType == BTC_CHIP_CSR_BC4 + || pBtCoexist->boardInfo.btChipType == BTC_CHIP_CSR_BC8 + ){ + return _TRUE; + } + return _FALSE; +} + +static u8 halbtcoutsrc_IsHwMailboxExist(PBTC_COEXIST pBtCoexist) +{ + if (pBtCoexist->boardInfo.btChipType == BTC_CHIP_CSR_BC4 + || pBtCoexist->boardInfo.btChipType == BTC_CHIP_CSR_BC8 + ){ + return _FALSE; + } + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) + { + return _FALSE; + } + else + return _TRUE; +} + +static void halbtcoutsrc_LeaveLps(PBTC_COEXIST pBtCoexist) +{ + PADAPTER padapter; + + + padapter = pBtCoexist->Adapter; + + pBtCoexist->btInfo.bBtCtrlLps = _TRUE; + pBtCoexist->btInfo.bBtLpsOn = _FALSE; + + rtw_btcoex_LPS_Leave(padapter); +} + +void halbtcoutsrc_EnterLps(PBTC_COEXIST pBtCoexist) +{ + PADAPTER padapter; + + + padapter = pBtCoexist->Adapter; + + pBtCoexist->btInfo.bBtCtrlLps = _TRUE; + pBtCoexist->btInfo.bBtLpsOn = _TRUE; + + rtw_btcoex_LPS_Enter(padapter); +} + +void halbtcoutsrc_NormalLps(PBTC_COEXIST pBtCoexist) +{ + PADAPTER padapter; + + + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Normal LPS behavior!!!\n")); + + padapter = pBtCoexist->Adapter; + + if (pBtCoexist->btInfo.bBtCtrlLps) + { + pBtCoexist->btInfo.bBtLpsOn = _FALSE; + rtw_btcoex_LPS_Leave(padapter); + pBtCoexist->btInfo.bBtCtrlLps = _FALSE; + + // recover the LPS state to the original +#if 0 + padapter->HalFunc.UpdateLPSStatusHandler( + padapter, + pPSC->RegLeisurePsMode, + pPSC->RegPowerSaveMode); +#endif + } +} + +/* + * Constraint: + * 1. this function will request pwrctrl->lock + */ +void halbtcoutsrc_LeaveLowPower(PBTC_COEXIST pBtCoexist) +{ +#ifdef CONFIG_LPS_LCLK + PADAPTER padapter; + PHAL_DATA_TYPE pHalData; + struct pwrctrl_priv *pwrctrl; + s32 ready; + u32 stime; + s32 utime; + u32 timeout; // unit: ms + + + padapter = pBtCoexist->Adapter; + pHalData = GET_HAL_DATA(padapter); + pwrctrl = adapter_to_pwrctl(padapter); + ready = _FAIL; +#ifdef LPS_RPWM_WAIT_MS + timeout = LPS_RPWM_WAIT_MS; +#else // !LPS_RPWM_WAIT_MS + timeout = 30; +#endif // !LPS_RPWM_WAIT_MS + + if (GLBtcBtCoexAliveRegistered == _TRUE) + return; + + stime = rtw_get_current_time(); + do { + ready = rtw_register_task_alive(padapter, BTCOEX_ALIVE); + if (_SUCCESS == ready) + break; + + utime = rtw_get_passing_time_ms(stime); + if (utime > timeout) + break; + + rtw_msleep_os(1); + } while (1); + + GLBtcBtCoexAliveRegistered = _TRUE; +#endif // CONFIG_LPS_LCLK +} + +/* + * Constraint: + * 1. this function will request pwrctrl->lock + */ +void halbtcoutsrc_NormalLowPower(PBTC_COEXIST pBtCoexist) +{ +#ifdef CONFIG_LPS_LCLK + PADAPTER padapter; + + if (GLBtcBtCoexAliveRegistered == _FALSE) + return; + + padapter = pBtCoexist->Adapter; + rtw_unregister_task_alive(padapter, BTCOEX_ALIVE); + + GLBtcBtCoexAliveRegistered = _FALSE; +#endif // CONFIG_LPS_LCLK +} + +void halbtcoutsrc_DisableLowPower(PBTC_COEXIST pBtCoexist, u8 bLowPwrDisable) +{ + pBtCoexist->btInfo.bBtDisableLowPwr = bLowPwrDisable; + if (bLowPwrDisable) + halbtcoutsrc_LeaveLowPower(pBtCoexist); // leave 32k low power. + else + halbtcoutsrc_NormalLowPower(pBtCoexist); // original 32k low power behavior. +} + +void halbtcoutsrc_AggregationCheck(PBTC_COEXIST pBtCoexist) +{ + PADAPTER padapter; + BOOLEAN bNeedToAct = _FALSE; + static u32 preTime = 0; + u32 curTime = 0; + + padapter = pBtCoexist->Adapter; + + //===================================== + // To void continuous deleteBA=>addBA=>deleteBA=>addBA + // This function is not allowed to continuous called. + // It can only be called after 8 seconds. + //===================================== + + curTime = rtw_systime_to_ms(rtw_get_current_time()); + if((curTime - preTime) < HALBTCOUTSRC_AGG_CHK_WINDOW_IN_MS) // over 8 seconds you can execute this function again. + { + return; + } + else + { + preTime = curTime; + } + + if (pBtCoexist->btInfo.bRejectAggPkt) + { + bNeedToAct = _TRUE; + pBtCoexist->btInfo.bPreRejectAggPkt = pBtCoexist->btInfo.bRejectAggPkt; + } + else + { + if(pBtCoexist->btInfo.bPreRejectAggPkt) + { + bNeedToAct = _TRUE; + pBtCoexist->btInfo.bPreRejectAggPkt = pBtCoexist->btInfo.bRejectAggPkt; + } + + if (pBtCoexist->btInfo.bPreBtCtrlAggBufSize != + pBtCoexist->btInfo.bBtCtrlAggBufSize) + { + bNeedToAct = _TRUE; + pBtCoexist->btInfo.bPreBtCtrlAggBufSize = pBtCoexist->btInfo.bBtCtrlAggBufSize; + } + + if (pBtCoexist->btInfo.bBtCtrlAggBufSize) + { + if (pBtCoexist->btInfo.preAggBufSize != + pBtCoexist->btInfo.aggBufSize) + { + bNeedToAct = _TRUE; + } + pBtCoexist->btInfo.preAggBufSize = pBtCoexist->btInfo.aggBufSize; + } + } + + if (bNeedToAct) + rtw_btcoex_rx_ampdu_apply(padapter); +} + +u8 halbtcoutsrc_IsWifiBusy(PADAPTER padapter) +{ + struct mlme_priv *pmlmepriv; + + + pmlmepriv = &padapter->mlmepriv; + + if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) + { + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + return _TRUE; + if (_TRUE == pmlmepriv->LinkDetectInfo.bBusyTraffic) + return _TRUE; + } + +#if defined(CONFIG_CONCURRENT_MODE) + pmlmepriv = &padapter->pbuddy_adapter->mlmepriv; + + if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) + { + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + return _TRUE; + if (_TRUE == pmlmepriv->LinkDetectInfo.bBusyTraffic) + return _TRUE; + } +#endif + + return _FALSE; +} + +static u32 _halbtcoutsrc_GetWifiLinkStatus(PADAPTER padapter) +{ + struct mlme_priv *pmlmepriv; + u8 bp2p; + u32 portConnectedStatus; + + + pmlmepriv = &padapter->mlmepriv; + bp2p = _FALSE; + portConnectedStatus = 0; + +#ifdef CONFIG_P2P + if (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE)) + bp2p = _TRUE; +#endif // CONFIG_P2P + + if (check_fwstate(pmlmepriv, WIFI_ASOC_STATE) == _TRUE) + { + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + { + if (_TRUE == bp2p) + portConnectedStatus |= WIFI_P2P_GO_CONNECTED; + else + portConnectedStatus |= WIFI_AP_CONNECTED; + } + else + { + if (_TRUE == bp2p) + portConnectedStatus |= WIFI_P2P_GC_CONNECTED; + else + portConnectedStatus |= WIFI_STA_CONNECTED; + } + } + + return portConnectedStatus; +} + +u32 halbtcoutsrc_GetWifiLinkStatus(PBTC_COEXIST pBtCoexist) +{ + //================================= + // return value: + // [31:16]=> connected port number + // [15:0]=> port connected bit define + //================================ + + PADAPTER padapter; + u32 retVal; + u32 portConnectedStatus, numOfConnectedPort; + + + padapter = pBtCoexist->Adapter; + retVal = 0; + portConnectedStatus = 0; + numOfConnectedPort = 0; + + retVal = _halbtcoutsrc_GetWifiLinkStatus(padapter); + if (retVal) + { + portConnectedStatus |= retVal; + numOfConnectedPort++; + } + +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->pbuddy_adapter) + { + retVal = _halbtcoutsrc_GetWifiLinkStatus(padapter->pbuddy_adapter); + if (retVal) + { + portConnectedStatus |= retVal; + numOfConnectedPort++; + } + } +#endif // CONFIG_CONCURRENT_MODE + + retVal = (numOfConnectedPort << 16) | portConnectedStatus; + + return retVal; +} + +static u8 _is_btfwver_valid(PBTC_COEXIST pBtCoexist, u16 btfwver) +{ + if (!btfwver) + return _FALSE; + + if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) + if (btfwver == 0x8723) + return _FALSE; + + return _TRUE; +} + +static void _btmpoper_timer_hdl(void *p) +{ + if (GLBtcBtMpRptWait) { + GLBtcBtMpRptWait = 0; + _rtw_up_sema(&GLBtcBtMpRptSema); + } +} + +/* + * !IMPORTANT! + * Before call this function, caller should acquire "GLBtcBtMpOperLock"! + * Othrewise there will be racing problem and something may go wrong. + */ +static u8 _btmpoper_cmd(PBTC_COEXIST pBtCoexist, u8 opcode, u8 opcodever, u8 *cmd, u8 size) +{ + PADAPTER padapter; + u8 buf[H2C_BTMP_OPER_LEN] = {0}; + u8 buflen; + u8 seq; + u8 timer_cancelled; + s32 ret; + + + if (!cmd && size) + size = 0; + if ((size + 2) > H2C_BTMP_OPER_LEN) + return BT_STATUS_H2C_LENGTH_EXCEEDED; + buflen = size + 2; + + seq = GLBtcBtMpOperSeq & 0xF; + GLBtcBtMpOperSeq++; + + buf[0] = (opcodever & 0xF) | (seq << 4); + buf[1] = opcode; + if (cmd && size) + _rtw_memcpy(buf+2, cmd, size); + + GLBtcBtMpRptWait = 1; + GLBtcBtMpRptWiFiOK = 0; + GLBtcBtMpRptBTOK = 0; + GLBtcBtMpRptStatus = 0; + padapter = pBtCoexist->Adapter; + _set_timer(&GLBtcBtMpOperTimer, BTC_MPOPER_TIMEOUT); + if (rtw_hal_fill_h2c_cmd(padapter, H2C_BT_MP_OPER, buflen, buf) == _FAIL) { + _cancel_timer(&GLBtcBtMpOperTimer, &timer_cancelled); + ret = BT_STATUS_H2C_FAIL; + goto exit; + } + + _rtw_down_sema(&GLBtcBtMpRptSema); + /* GLBtcBtMpRptWait should be 0 here*/ + + if (!GLBtcBtMpRptWiFiOK) { + DBG_871X("%s: Didn't get H2C Rsp Event!\n", __FUNCTION__); + ret = BT_STATUS_H2C_TIMTOUT; + goto exit; + } + if (!GLBtcBtMpRptBTOK) { + DBG_871X("%s: Didn't get BT response!\n", __FUNCTION__); + ret = BT_STATUS_H2C_BT_NO_RSP; + goto exit; + } + if (seq != GLBtcBtMpRptSeq) { + DBG_871X("%s: Sequence number not match!(%d!=%d)!\n", + __FUNCTION__, seq, GLBtcBtMpRptSeq); + ret = BT_STATUS_C2H_REQNUM_MISMATCH; + goto exit; + } + + switch (GLBtcBtMpRptStatus) { + /* Examine the status reported from C2H */ + case BT_STATUS_OK: + ret = BT_STATUS_BT_OP_SUCCESS; + DBG_871X("%s: C2H status = BT_STATUS_BT_OP_SUCCESS\n", __FUNCTION__); + break; + case BT_STATUS_VERSION_MISMATCH: + ret = BT_STATUS_OPCODE_L_VERSION_MISMATCH; + DBG_871X("%s: C2H status = BT_STATUS_OPCODE_L_VERSION_MISMATCH\n", __FUNCTION__); + break; + case BT_STATUS_UNKNOWN_OPCODE: + ret = BT_STATUS_UNKNOWN_OPCODE_L; + DBG_871X("%s: C2H status = MP_BT_STATUS_UNKNOWN_OPCODE_L\n", __FUNCTION__); + break; + case BT_STATUS_ERROR_PARAMETER: + ret = BT_STATUS_PARAMETER_FORMAT_ERROR_L; + DBG_871X("%s: C2H status = MP_BT_STATUS_PARAMETER_FORMAT_ERROR_L\n", __FUNCTION__); + break; + default: + ret = BT_STATUS_UNKNOWN_STATUS_L; + DBG_871X("%s: C2H status = MP_BT_STATUS_UNKNOWN_STATUS_L\n", __FUNCTION__); + break; + } + +exit: + return ret; +} + +u32 halbtcoutsrc_GetBtPatchVer(PBTC_COEXIST pBtCoexist) +{ + if (_is_btfwver_valid(pBtCoexist, pBtCoexist->btInfo.btRealFwVer) == _TRUE) + goto exit; + + if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) { + _irqL irqL; + u8 ret; + + + _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + ret = _btmpoper_cmd(pBtCoexist, BT_OP_GET_BT_VERSION, 0, NULL, 0); + if (BT_STATUS_BT_OP_SUCCESS == ret) { + pBtCoexist->btInfo.btRealFwVer = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp); + pBtCoexist->btInfo.btFwVer = *(GLBtcBtMpRptRsp+2); + } + pBtCoexist->btInfo.getBtFwVerCnt++; + + _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL); + } else { +#ifdef CONFIG_BT_COEXIST_SOCKET_TRX + u1Byte dataLen = 2; + u1Byte buf[4] = {0}; + + buf[0] = 0x0; /* OP_Code */ + buf[1] = 0x0; /* OP_Code_Length */ + BT_SendEventExtBtCoexControl(pBtCoexist->Adapter, _FALSE, dataLen, &buf[0]); +#endif /* !CONFIG_BT_COEXIST_SOCKET_TRX */ + } + +exit: + return pBtCoexist->btInfo.btRealFwVer; +} + +s32 halbtcoutsrc_GetWifiRssi(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData; + s32 UndecoratedSmoothedPWDB = 0; + + pHalData = GET_HAL_DATA(padapter); + + UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB; + + return UndecoratedSmoothedPWDB; +} + +static u8 halbtcoutsrc_GetWifiScanAPNum(PADAPTER padapter) +{ + struct mlme_priv *pmlmepriv; + struct mlme_ext_priv *pmlmeext; + static u8 scan_AP_num = 0; + + + pmlmepriv = &padapter->mlmepriv; + pmlmeext = &padapter->mlmeextpriv; + + if (GLBtcWiFiInScanState == _FALSE) { + if (pmlmepriv->num_of_scanned > 0xFF) + scan_AP_num = 0xFF; + else + scan_AP_num = (u8)pmlmepriv->num_of_scanned; + } + + return scan_AP_num; +} + +u8 halbtcoutsrc_Get(void *pBtcContext, u8 getType, void *pOutBuf) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + PHAL_DATA_TYPE pHalData; + struct mlme_ext_priv *mlmeext; + u8 bSoftApExist, bVwifiExist; + u8 *pu8; + s32 *pS4Tmp; + u32 *pU4Tmp; + u8 *pU1Tmp; + u8 ret; + + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return _FALSE; + + padapter = pBtCoexist->Adapter; + pHalData = GET_HAL_DATA(padapter); + mlmeext = &padapter->mlmeextpriv; + bSoftApExist = _FALSE; + bVwifiExist = _FALSE; + pu8 = (u8*)pOutBuf; + pS4Tmp = (s32*)pOutBuf; + pU4Tmp = (u32*)pOutBuf; + pU1Tmp = (u8*)pOutBuf; + ret = _TRUE; + + switch (getType) + { + case BTC_GET_BL_HS_OPERATION: + *pu8 = _FALSE; + ret = _FALSE; + break; + + case BTC_GET_BL_HS_CONNECTING: + *pu8 = _FALSE; + ret = _FALSE; + break; + + case BTC_GET_BL_WIFI_CONNECTED: + *pu8 = check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE); +#ifdef CONFIG_CONCURRENT_MODE + if ((_FALSE == *pu8) && padapter->pbuddy_adapter) + { + *pu8 = check_fwstate(&padapter->pbuddy_adapter->mlmepriv, WIFI_ASOC_STATE); + } +#endif // CONFIG_CONCURRENT_MODE + break; + + case BTC_GET_BL_WIFI_BUSY: + *pu8 = halbtcoutsrc_IsWifiBusy(padapter); + break; + + case BTC_GET_BL_WIFI_SCAN: +#if 0 + *pu8 = check_fwstate(&padapter->mlmepriv, WIFI_SITE_MONITOR); +#ifdef CONFIG_CONCURRENT_MODE + if ((_FALSE == *pu8) && padapter->pbuddy_adapter) + { + *pu8 = check_fwstate(&padapter->pbuddy_adapter->mlmepriv, WIFI_SITE_MONITOR); + } +#endif // CONFIG_CONCURRENT_MODE +#else + /* Use the value of the new variable GLBtcWiFiInScanState to judge whether WiFi is in scan state or not, since the originally used flag + WIFI_SITE_MONITOR in fwstate may not be cleared in time */ + *pu8 = GLBtcWiFiInScanState; +#endif + break; + + case BTC_GET_BL_WIFI_LINK: + *pu8 = check_fwstate(&padapter->mlmepriv, WIFI_UNDER_LINKING); +#ifdef CONFIG_CONCURRENT_MODE + if ((_FALSE == *pu8) && padapter->pbuddy_adapter) + { + *pu8 = check_fwstate(&padapter->pbuddy_adapter->mlmepriv, WIFI_UNDER_LINKING); + } +#endif // CONFIG_CONCURRENT_MODE + break; + + case BTC_GET_BL_WIFI_ROAM: + *pu8 = check_fwstate(&padapter->mlmepriv, WIFI_UNDER_LINKING); +#ifdef CONFIG_CONCURRENT_MODE + if ((_FALSE == *pu8) && padapter->pbuddy_adapter) + { + *pu8 = check_fwstate(&padapter->pbuddy_adapter->mlmepriv, WIFI_UNDER_LINKING); + } +#endif // CONFIG_CONCURRENT_MODE + break; + + case BTC_GET_BL_WIFI_4_WAY_PROGRESS: + *pu8 = _FALSE; + break; + + case BTC_GET_BL_WIFI_UNDER_5G: + *pu8 = (pHalData->CurrentBandType == 1)? _TRUE : _FALSE; + break; + + case BTC_GET_BL_WIFI_AP_MODE_ENABLE: + *pu8 = check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE); +#ifdef CONFIG_CONCURRENT_MODE + if ((_FALSE == *pu8) && padapter->pbuddy_adapter) + { + *pu8 = check_fwstate(&padapter->pbuddy_adapter->mlmepriv, WIFI_AP_STATE); + } +#endif // CONFIG_CONCURRENT_MODE + break; + + case BTC_GET_BL_WIFI_ENABLE_ENCRYPTION: + *pu8 = padapter->securitypriv.dot11PrivacyAlgrthm == 0? _FALSE: _TRUE; + break; + + case BTC_GET_BL_WIFI_UNDER_B_MODE: + if (mlmeext->cur_wireless_mode == WIRELESS_11B) + *pu8 = _TRUE; + else + *pu8 = _FALSE; + break; + + case BTC_GET_BL_WIFI_IS_IN_MP_MODE: + if (padapter->registrypriv.mp_mode == 0) + { + *pu8 = _FALSE; + } + else + { + *pu8 = _TRUE; + } + break; + + case BTC_GET_BL_EXT_SWITCH: + *pu8 = _FALSE; + break; + case BTC_GET_BL_IS_ASUS_8723B: + /* Always return FALSE in linux driver since this case is added only for windows driver */ + *pu8 = _FALSE; + break; + + case BTC_GET_S4_WIFI_RSSI: + *pS4Tmp = halbtcoutsrc_GetWifiRssi(padapter); + break; + + case BTC_GET_S4_HS_RSSI: + *pS4Tmp = 0; + ret = _FALSE; + break; + + case BTC_GET_U4_WIFI_BW: + if (IsLegacyOnly(mlmeext->cur_wireless_mode)) + *pU4Tmp = BTC_WIFI_BW_LEGACY; + else if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_20) + *pU4Tmp = BTC_WIFI_BW_HT20; + else if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) + *pU4Tmp = BTC_WIFI_BW_HT40; + else + *pU4Tmp = BTC_WIFI_BW_HT40; /* todo */ + break; + + case BTC_GET_U4_WIFI_TRAFFIC_DIRECTION: + { + PRT_LINK_DETECT_T plinkinfo; + plinkinfo = &padapter->mlmepriv.LinkDetectInfo; + + if (plinkinfo->NumTxOkInPeriod > plinkinfo->NumRxOkInPeriod) + *pU4Tmp = BTC_WIFI_TRAFFIC_TX; + else + *pU4Tmp = BTC_WIFI_TRAFFIC_RX; + } + break; + + case BTC_GET_U4_WIFI_FW_VER: + *pU4Tmp = pHalData->FirmwareVersion << 16; + *pU4Tmp |= pHalData->FirmwareSubVersion; + break; + + case BTC_GET_U4_WIFI_LINK_STATUS: + *pU4Tmp = halbtcoutsrc_GetWifiLinkStatus(pBtCoexist); + break; + + case BTC_GET_U4_BT_PATCH_VER: + *pU4Tmp = halbtcoutsrc_GetBtPatchVer(pBtCoexist); + break; + + case BTC_GET_U1_WIFI_DOT11_CHNL: + *pU1Tmp = padapter->mlmeextpriv.cur_channel; + break; + + case BTC_GET_U1_WIFI_CENTRAL_CHNL: + *pU1Tmp = pHalData->CurrentChannel; + break; + + case BTC_GET_U1_WIFI_HS_CHNL: + *pU1Tmp = 0; + ret = _FALSE; + break; + + case BTC_GET_U1_MAC_PHY_MODE: +// *pU1Tmp = BTC_SMSP; +// *pU1Tmp = BTC_DMSP; +// *pU1Tmp = BTC_DMDP; +// *pU1Tmp = BTC_MP_UNKNOWN; + break; + + case BTC_GET_U1_AP_NUM: + *pU1Tmp = halbtcoutsrc_GetWifiScanAPNum(padapter); + break; + case BTC_GET_U1_ANT_TYPE: + switch(pHalData->bt_coexist.btAntisolation) + { + case 0: + *pU1Tmp = (u1Byte)BTC_ANT_TYPE_0; + pBtCoexist->boardInfo.antType = (u1Byte)BTC_ANT_TYPE_0; + break; + case 1: + *pU1Tmp = (u1Byte)BTC_ANT_TYPE_1; + pBtCoexist->boardInfo.antType = (u1Byte)BTC_ANT_TYPE_1; + break; + case 2: + *pU1Tmp = (u1Byte)BTC_ANT_TYPE_2; + pBtCoexist->boardInfo.antType = (u1Byte)BTC_ANT_TYPE_2; + break; + case 3: + *pU1Tmp = (u1Byte)BTC_ANT_TYPE_3; + pBtCoexist->boardInfo.antType = (u1Byte)BTC_ANT_TYPE_3; + break; + case 4: + *pU1Tmp = (u1Byte)BTC_ANT_TYPE_4; + pBtCoexist->boardInfo.antType = (u1Byte)BTC_ANT_TYPE_4; + break; + } + break; + case BTC_GET_U1_IOT_PEER: + *pU1Tmp = mlmeext->mlmext_info.assoc_AP_vendor; + break; + + //=======1Ant=========== + case BTC_GET_U1_LPS_MODE: + *pU1Tmp = padapter->dvobj->pwrctl_priv.pwr_mode; + break; + + default: + ret = _FALSE; + break; + } + + return ret; +} + +u8 halbtcoutsrc_Set(void *pBtcContext, u8 setType, void *pInBuf) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + PHAL_DATA_TYPE pHalData; + u8 *pu8; + u8 *pU1Tmp; + u32 *pU4Tmp; + u8 ret; + + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + padapter = pBtCoexist->Adapter; + pHalData = GET_HAL_DATA(padapter); + pu8 = (u8*)pInBuf; + pU1Tmp = (u8*)pInBuf; + pU4Tmp = (u32*)pInBuf; + ret = _TRUE; + + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return _FALSE; + + switch (setType) + { + // set some u8 type variables. + case BTC_SET_BL_BT_DISABLE: + pBtCoexist->btInfo.bBtDisabled = *pu8; + break; + + case BTC_SET_BL_BT_TRAFFIC_BUSY: + pBtCoexist->btInfo.bBtBusy = *pu8; + break; + + case BTC_SET_BL_BT_LIMITED_DIG: + pBtCoexist->btInfo.bLimitedDig = *pu8; + break; + + case BTC_SET_BL_FORCE_TO_ROAM: + pBtCoexist->btInfo.bForceToRoam = *pu8; + break; + + case BTC_SET_BL_TO_REJ_AP_AGG_PKT: + pBtCoexist->btInfo.bRejectAggPkt = *pu8; + break; + + case BTC_SET_BL_BT_CTRL_AGG_SIZE: + pBtCoexist->btInfo.bBtCtrlAggBufSize = *pu8; + break; + + case BTC_SET_BL_INC_SCAN_DEV_NUM: + pBtCoexist->btInfo.bIncreaseScanDevNum = *pu8; + break; + + case BTC_SET_BL_BT_TX_RX_MASK: + pBtCoexist->btInfo.bBtTxRxMask = *pu8; + break; + + case BTC_SET_BL_MIRACAST_PLUS_BT: + pBtCoexist->btInfo.bMiracastPlusBt = *pu8; + break; + + // set some u8 type variables. + case BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON: + pBtCoexist->btInfo.rssiAdjustForAgcTableOn = *pU1Tmp; + break; + + case BTC_SET_U1_AGG_BUF_SIZE: + pBtCoexist->btInfo.aggBufSize = *pU1Tmp; + break; + + // the following are some action which will be triggered + case BTC_SET_ACT_GET_BT_RSSI: +#if 0 + BT_SendGetBtRssiEvent(padapter); +#else + ret = _FALSE; +#endif + break; + + case BTC_SET_ACT_AGGREGATE_CTRL: + halbtcoutsrc_AggregationCheck(pBtCoexist); + break; + + //=======1Ant=========== + // set some u8 type variables. + case BTC_SET_U1_RSSI_ADJ_VAL_FOR_1ANT_COEX_TYPE: + pBtCoexist->btInfo.rssiAdjustFor1AntCoexType = *pU1Tmp; + break; + + case BTC_SET_U1_LPS_VAL: + pBtCoexist->btInfo.lpsVal = *pU1Tmp; + break; + + case BTC_SET_U1_RPWM_VAL: + pBtCoexist->btInfo.rpwmVal = *pU1Tmp; + break; + + // the following are some action which will be triggered + case BTC_SET_ACT_LEAVE_LPS: + halbtcoutsrc_LeaveLps(pBtCoexist); + break; + + case BTC_SET_ACT_ENTER_LPS: + halbtcoutsrc_EnterLps(pBtCoexist); + break; + + case BTC_SET_ACT_NORMAL_LPS: + halbtcoutsrc_NormalLps(pBtCoexist); + break; + + case BTC_SET_ACT_DISABLE_LOW_POWER: + halbtcoutsrc_DisableLowPower(pBtCoexist, *pu8); + break; + + case BTC_SET_ACT_UPDATE_RAMASK: + pBtCoexist->btInfo.raMask = *pU4Tmp; + + if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE) + { + struct sta_info *psta; + PWLAN_BSSID_EX cur_network; + + cur_network = &padapter->mlmeextpriv.mlmext_info.network; + psta = rtw_get_stainfo(&padapter->stapriv, cur_network->MacAddress); + rtw_hal_update_ra_mask(psta, 0); + } + break; + + case BTC_SET_ACT_SEND_MIMO_PS: + { + u8 newMimoPsMode = 3; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + /* *pU1Tmp = 0 use SM_PS static type */ + /* *pU1Tmp = 1 disable SM_PS */ + if (*pU1Tmp == 0) + newMimoPsMode = WLAN_HT_CAP_SM_PS_STATIC; + else if (*pU1Tmp == 1) + newMimoPsMode = WLAN_HT_CAP_SM_PS_DISABLED; + + if (check_fwstate(&padapter->mlmepriv , WIFI_ASOC_STATE) == _TRUE) { + /* issue_action_SM_PS(padapter, get_my_bssid(&(pmlmeinfo->network)), newMimoPsMode); */ + issue_action_SM_PS_wait_ack(padapter , get_my_bssid(&(pmlmeinfo->network)) , newMimoPsMode, 3 , 1); + } + } + break; + + case BTC_SET_ACT_CTRL_BT_INFO: +#ifdef CONFIG_BT_COEXIST_SOCKET_TRX + { + u8 dataLen = *pU1Tmp; + u8 tmpBuf[20]; + if (dataLen) + { + _rtw_memcpy(tmpBuf, pU1Tmp+1, dataLen); + } + BT_SendEventExtBtInfoControl(padapter, dataLen, &tmpBuf[0]); + } +#else //!CONFIG_BT_COEXIST_SOCKET_TRX + ret = _FALSE; +#endif //CONFIG_BT_COEXIST_SOCKET_TRX + break; + + case BTC_SET_ACT_CTRL_BT_COEX: +#ifdef CONFIG_BT_COEXIST_SOCKET_TRX + { + u8 dataLen = *pU1Tmp; + u8 tmpBuf[20]; + if (dataLen) + { + _rtw_memcpy(tmpBuf, pU1Tmp+1, dataLen); + } + BT_SendEventExtBtCoexControl(padapter, _FALSE, dataLen, &tmpBuf[0]); + } +#else //!CONFIG_BT_COEXIST_SOCKET_TRX + ret = _FALSE; +#endif //CONFIG_BT_COEXIST_SOCKET_TRX + break; + case BTC_SET_ACT_CTRL_8723B_ANT: +#if 0 + { + u1Byte dataLen=*pU1Tmp; + u1Byte tmpBuf[20]; + if(dataLen) + { + PlatformMoveMemory(&tmpBuf[0], pU1Tmp+1, dataLen); + } + BT_Set8723bAnt(Adapter, dataLen, &tmpBuf[0]); + } +#else + ret = _FALSE; +#endif + break; + //===================== + default: + ret = _FALSE; + break; + } + + return ret; +} + +u8 halbtcoutsrc_UnderIps(PBTC_COEXIST pBtCoexist) +{ + PADAPTER padapter; + struct pwrctrl_priv *pwrpriv; + u8 bMacPwrCtrlOn; + + padapter = pBtCoexist->Adapter; + pwrpriv = &padapter->dvobj->pwrctl_priv; + bMacPwrCtrlOn = _FALSE; + + if ((_TRUE == pwrpriv->bips_processing) + && (IPS_NONE != pwrpriv->ips_mode_req) + ) + { + return _TRUE; + } + + if (rf_off == pwrpriv->rf_pwrstate) + { + return _TRUE; + } + + rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); + if (_FALSE == bMacPwrCtrlOn) + { + return _TRUE; + } + + return _FALSE; +} + +u8 halbtcoutsrc_UnderLps(PBTC_COEXIST pBtCoexist) +{ + return GLBtcWiFiInLPS; +} + +u8 halbtcoutsrc_Under32K(PBTC_COEXIST pBtCoexist) +{ + /* todo: the method to check whether wifi is under 32K or not */ + return _FALSE; +} + +void halbtcoutsrc_DisplayCoexStatistics(PBTC_COEXIST pBtCoexist) +{ +#if 0 + PADAPTER padapter = (PADAPTER)pBtCoexist->Adapter; + PBT_MGNT pBtMgnt = &padapter->MgntInfo.BtInfo.BtMgnt; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + u8 *cliBuf = pBtCoexist->cliBuf; + u8 i; + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Statistics]============"); + CL_PRINTF(cliBuf); + +#if (H2C_USE_IO_THREAD != 1) + for(i=0; ih2cStatistics[i]) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s] = %d", "H2C statistics", \ + h2cStaString[i], pHalData->h2cStatistics[i]); + CL_PRINTF(cliBuf); + } + } +#else + for(i=0; iioComStr.ioH2cStatistics[i]) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = [%s] = %d", "H2C statistics", \ + ioStaString[i], Adapter->ioComStr.ioH2cStatistics[i]); + CL_PRINTF(cliBuf); + } + } +#endif +#if 0 + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "lastHMEBoxNum", \ + pHalData->LastHMEBoxNum); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x / 0x%x", "LastOkH2c/FirstFailH2c(fwNotRead)", \ + pHalData->lastSuccessH2cEid, pHalData->firstFailedH2cEid); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", "c2hIsr/c2hIntr/clr1AF/noRdy/noBuf", \ + pHalData->InterruptLog.nIMR_C2HCMD, DBG_Var.c2hInterruptCnt, DBG_Var.c2hClrReadC2hCnt, + DBG_Var.c2hNotReadyCnt, DBG_Var.c2hBufAlloFailCnt); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "c2hPacket", \ + DBG_Var.c2hPacketCnt); + CL_PRINTF(cliBuf); +#endif + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "Periodical/ DbgCtrl", \ + pBtCoexist->statistics.cntPeriodical, pBtCoexist->statistics.cntDbgCtrl); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d", "PowerOn/InitHw/InitCoexDm/RfStatus", \ + pBtCoexist->statistics.cntPowerOn, pBtCoexist->statistics.cntInitHwConfig, pBtCoexist->statistics.cntInitCoexDm, + pBtCoexist->statistics.cntRfStatusNotify); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", "Ips/Lps/Scan/Connect/Mstatus", \ + pBtCoexist->statistics.cntIpsNotify, pBtCoexist->statistics.cntLpsNotify, + pBtCoexist->statistics.cntScanNotify, pBtCoexist->statistics.cntConnectNotify, + pBtCoexist->statistics.cntMediaStatusNotify); + CL_PRINTF(cliBuf); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d", "Special pkt/Bt info/ bind", + pBtCoexist->statistics.cntSpecialPacketNotify, pBtCoexist->statistics.cntBtInfoNotify, + pBtCoexist->statistics.cntBind); + CL_PRINTF(cliBuf); +#endif +} + +void halbtcoutsrc_DisplayBtLinkInfo(PBTC_COEXIST pBtCoexist) +{ +#if 0 + PADAPTER padapter = (PADAPTER)pBtCoexist->Adapter; + PBT_MGNT pBtMgnt = &padapter->MgntInfo.BtInfo.BtMgnt; + u8 *cliBuf = pBtCoexist->cliBuf; + u8 i; + + + if (pBtCoexist->stackInfo.bProfileNotified) + { + for (i=0; iExtConfig.NumberOfACL; i++) + { + if (pBtMgnt->ExtConfig.HCIExtensionVer >= 1) + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s/ %s", "Bt link type/spec/role", \ + BtProfileString[pBtMgnt->ExtConfig.aclLink[i].BTProfile], + BtSpecString[pBtMgnt->ExtConfig.aclLink[i].BTCoreSpec], + BtLinkRoleString[pBtMgnt->ExtConfig.aclLink[i].linkRole]); + CL_PRINTF(cliBuf); } + else + { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s/ %s", "Bt link type/spec", \ + BtProfileString[pBtMgnt->ExtConfig.aclLink[i].BTProfile], + BtSpecString[pBtMgnt->ExtConfig.aclLink[i].BTCoreSpec]); + CL_PRINTF(cliBuf); + } + } + } +#endif +} + +void halbtcoutsrc_DisplayWifiStatus(PBTC_COEXIST pBtCoexist) +{ + PADAPTER padapter = pBtCoexist->Adapter; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + u8* cliBuf=pBtCoexist->cliBuf; + s32 wifiRssi=0, btHsRssi=0; + BOOLEAN bScan=_FALSE, bLink=_FALSE, bRoam=_FALSE, bWifiBusy=_FALSE, bWifiUnderBMode=_FALSE; + u32 wifiBw=BTC_WIFI_BW_HT20, wifiTrafficDir=BTC_WIFI_TRAFFIC_TX, wifiFreq=BTC_FREQ_2_4G; + u32 wifiLinkStatus=0x0; + BOOLEAN bBtHsOn=_FALSE, bLowPower=_FALSE; + u8 wifiChnl=0, wifiHsChnl=0, nScanAPNum = 0, FwPSState; + + wifiLinkStatus = halbtcoutsrc_GetWifiLinkStatus(pBtCoexist); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d/ %d/ %d", "STA/vWifi/HS/p2pGo/p2pGc", \ + ((wifiLinkStatus&WIFI_STA_CONNECTED)? 1:0), ((wifiLinkStatus&WIFI_AP_CONNECTED)? 1:0), + ((wifiLinkStatus&WIFI_HS_CONNECTED)? 1:0), ((wifiLinkStatus&WIFI_P2P_GO_CONNECTED)? 1:0), + ((wifiLinkStatus&WIFI_P2P_GC_CONNECTED)? 1:0) ); + CL_PRINTF(cliBuf); + + if (wifiLinkStatus&WIFI_STA_CONNECTED) { + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s", "IOT Peer", GLBtcIotPeerString[padapter->mlmeextpriv.mlmext_info.assoc_AP_vendor]); + CL_PRINTF(cliBuf); + } + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_WIFI_DOT11_CHNL, &wifiChnl); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_WIFI_HS_CHNL, &wifiHsChnl); CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d(%d)", "Dot11 channel / HsChnl(High Speed)", \ + wifiChnl, wifiHsChnl, bBtHsOn); + CL_PRINTF(cliBuf); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_HS_RSSI, &btHsRssi); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d", "Wifi rssi/ HS rssi", \ + wifiRssi-100, btHsRssi-100); + CL_PRINTF(cliBuf); + + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d/ %d/ %d ", "Wifi bLink/ bRoam/ bScan", \ + bLink, bRoam, bScan); + CL_PRINTF(cliBuf); + + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_5G, &wifiFreq); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_UNDER_B_MODE, &bWifiUnderBMode); + pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_AP_NUM, &nScanAPNum); + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s / %s/ %s/ AP=%d ", "Wifi freq/ bw/ traffic", \ + GLBtcWifiFreqString[wifiFreq], ((bWifiUnderBMode)? "11b": GLBtcWifiBwString[wifiBw]), + ((!bWifiBusy)? "idle": ((BTC_WIFI_TRAFFIC_TX==wifiTrafficDir)? "uplink":"downlink")), + nScanAPNum); + CL_PRINTF(cliBuf); + + // power status + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %s%s%s", "Power Status", \ + ((halbtcoutsrc_UnderIps(pBtCoexist) == _TRUE)? "IPS ON":"IPS OFF"), + ((halbtcoutsrc_UnderLps(pBtCoexist) == _TRUE)? ", LPS ON":", LPS OFF"), + ((halbtcoutsrc_Under32K(pBtCoexist) == _TRUE)? ", 32k":"")); + CL_PRINTF(cliBuf); + + CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %02x %02x %02x %02x %02x %02x (0x%x/0x%x)", "Power mode cmd(lps/rpwm)", \ + pBtCoexist->pwrModeVal[0], pBtCoexist->pwrModeVal[1], + pBtCoexist->pwrModeVal[2], pBtCoexist->pwrModeVal[3], + pBtCoexist->pwrModeVal[4], pBtCoexist->pwrModeVal[5], + pBtCoexist->btInfo.lpsVal, + pBtCoexist->btInfo.rpwmVal); + CL_PRINTF(cliBuf); +} + +void halbtcoutsrc_DisplayDbgMsg(void *pBtcContext, u8 dispType) +{ + PBTC_COEXIST pBtCoexist; + + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + switch(dispType) + { + case BTC_DBG_DISP_COEX_STATISTICS: + halbtcoutsrc_DisplayCoexStatistics(pBtCoexist); + break; + case BTC_DBG_DISP_BT_LINK_INFO: + halbtcoutsrc_DisplayBtLinkInfo(pBtCoexist); + break; + case BTC_DBG_DISP_WIFI_STATUS: + halbtcoutsrc_DisplayWifiStatus(pBtCoexist); + break; + default: + break; + } +} + +//==================================== +// IO related function +//==================================== +u8 halbtcoutsrc_Read1Byte(void *pBtcContext, u32 RegAddr) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + padapter = pBtCoexist->Adapter; + + return rtw_read8(padapter, RegAddr); +} + +u16 halbtcoutsrc_Read2Byte(void *pBtcContext, u32 RegAddr) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + padapter = pBtCoexist->Adapter; + + return rtw_read16(padapter, RegAddr); +} + +u32 halbtcoutsrc_Read4Byte(void *pBtcContext, u32 RegAddr) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + padapter = pBtCoexist->Adapter; + + return rtw_read32(padapter, RegAddr); +} + +void halbtcoutsrc_Write1Byte(void *pBtcContext, u32 RegAddr, u8 Data) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + padapter = pBtCoexist->Adapter; + + rtw_write8(padapter, RegAddr, Data); +} + +void halbtcoutsrc_BitMaskWrite1Byte(void *pBtcContext, u32 regAddr, u8 bitMask, u8 data1b) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + u8 originalValue, bitShift; + u8 i; + + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + padapter = pBtCoexist->Adapter; + originalValue = 0; + bitShift = 0; + + if(bitMask != 0xff) + { + originalValue = rtw_read8(padapter, regAddr); + + for (i=0; i<=7; i++) + { + if ((bitMask>>i)&0x1) + break; + } + bitShift = i; + + data1b = (originalValue & ~bitMask) | ((data1b << bitShift) & bitMask); + } + + rtw_write8(padapter, regAddr, data1b); +} + +void halbtcoutsrc_Write2Byte(void *pBtcContext, u32 RegAddr, u16 Data) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + padapter = pBtCoexist->Adapter; + + rtw_write16(padapter, RegAddr, Data); +} + +void halbtcoutsrc_Write4Byte(void *pBtcContext, u32 RegAddr, u32 Data) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + padapter = pBtCoexist->Adapter; + + rtw_write32(padapter, RegAddr, Data); +} + +void halbtcoutsrc_WriteLocalReg1Byte(void *pBtcContext, u32 RegAddr, u8 Data) +{ + PBTC_COEXIST pBtCoexist=(PBTC_COEXIST)pBtcContext; + PADAPTER Adapter=pBtCoexist->Adapter; + + if(BTC_INTF_SDIO == pBtCoexist->chipInterface) + { + rtw_write8(Adapter, SDIO_LOCAL_BASE | RegAddr, Data); + } + else + { + rtw_write8(Adapter, RegAddr, Data); + } +} + +void halbtcoutsrc_SetBbReg(void *pBtcContext, u32 RegAddr, u32 BitMask, u32 Data) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + padapter = pBtCoexist->Adapter; + + PHY_SetBBReg(padapter, RegAddr, BitMask, Data); +} + + +u32 halbtcoutsrc_GetBbReg(void *pBtcContext, u32 RegAddr, u32 BitMask) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + padapter = pBtCoexist->Adapter; + + return PHY_QueryBBReg(padapter, RegAddr, BitMask); +} + +void halbtcoutsrc_SetRfReg(void *pBtcContext, u8 eRFPath, u32 RegAddr, u32 BitMask, u32 Data) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + padapter = pBtCoexist->Adapter; + + PHY_SetRFReg(padapter, eRFPath, RegAddr, BitMask, Data); +} + +u32 halbtcoutsrc_GetRfReg(void *pBtcContext, u8 eRFPath, u32 RegAddr, u32 BitMask) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + padapter = pBtCoexist->Adapter; + + return PHY_QueryRFReg(padapter, eRFPath, RegAddr, BitMask); +} + +u16 halbtcoutsrc_SetBtReg(void *pBtcContext, u8 RegType, u32 RegAddr, u32 Data) +{ + PBTC_COEXIST pBtCoexist; + u16 ret = BT_STATUS_BT_OP_SUCCESS; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + + if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) { + u8 buf[3] = {0}; + _irqL irqL; + u8 op_code; + u8 status; + + _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + Data = cpu_to_le32(Data); + op_code = BT_OP_WRITE_REG_VALUE; + status = _btmpoper_cmd(pBtCoexist, op_code, 0, (u8 *)&Data, 3); + if (status != BT_STATUS_BT_OP_SUCCESS) + ret = SET_BT_MP_OPER_RET(op_code, status); + else { + buf[0] = RegType; + *(u16 *)(buf+1) = cpu_to_le16((u16)RegAddr); + op_code = BT_OP_WRITE_REG_ADDR; + status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 3); + if (status != BT_STATUS_BT_OP_SUCCESS) + ret = SET_BT_MP_OPER_RET(op_code, status); + } + + _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL); + } else + ret = BT_STATUS_NOT_IMPLEMENT; + + return ret; +} + +u8 halbtcoutsrc_SetBtAntDetection(void *pBtcContext, u8 txTime, u8 btChnl) +{ +/* Always return _FALSE since we don't implement this yet */ +#if 0 + PBTC_COEXIST pBtCoexist = (PBTC_COEXIST)pBtcContext; + PADAPTER Adapter = pBtCoexist->Adapter; + u1Byte btCanTx = 0; + BOOLEAN bStatus = FALSE; + + bStatus = NDBG_SetBtAntDetection(Adapter, txTime, btChnl, &btCanTx); + if (bStatus && btCanTx) + return _TRUE; + else + return _FALSE; +#else + return _FALSE; +#endif +} + +u16 halbtcoutsrc_GetBtReg(void *pBtcContext, u8 RegType, u32 RegAddr, u32 *data) +{ + PBTC_COEXIST pBtCoexist; + u16 ret = BT_STATUS_BT_OP_SUCCESS; + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + + if (halbtcoutsrc_IsHwMailboxExist(pBtCoexist) == _TRUE) { + u8 buf[3] = {0}; + _irqL irqL; + u8 op_code; + u8 status; + + buf[0] = RegType; + *(u16 *)(buf+1) = cpu_to_le16((u16)RegAddr); + + _enter_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + op_code = BT_OP_READ_REG; + status = _btmpoper_cmd(pBtCoexist, op_code, 0, buf, 3); + if (status == BT_STATUS_BT_OP_SUCCESS) + *data = le16_to_cpu(*(u16 *)GLBtcBtMpRptRsp); + else + ret = SET_BT_MP_OPER_RET(op_code, status); + + _exit_critical_mutex(&GLBtcBtMpOperLock, &irqL); + + } else + ret = BT_STATUS_NOT_IMPLEMENT; + + return ret; +} + +void halbtcoutsrc_FillH2cCmd(void *pBtcContext, u8 elementId, u32 cmdLen, u8 *pCmdBuffer) +{ + PBTC_COEXIST pBtCoexist; + PADAPTER padapter; + + + pBtCoexist = (PBTC_COEXIST)pBtcContext; + padapter = pBtCoexist->Adapter; + + rtw_hal_fill_h2c_cmd(padapter, elementId, cmdLen, pCmdBuffer); +} + +//==================================== +// Extern functions called by other module +//==================================== +u8 EXhalbtcoutsrc_IsTfbgaPackageType(PADAPTER padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + +#ifdef CONFIG_RTL8723B + if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA80) + || (pHalData->PackageType == PACKAGE_TFBGA90)) { + return _TRUE; + } +#endif + + return _FALSE; +} + +u8 EXhalbtcoutsrc_BindBtCoexWithAdapter(void *padapter) +{ + PBTC_COEXIST pBtCoexist=&GLBtCoexist; + u1Byte antNum=2, chipType; + + if(pBtCoexist->bBinded) + return _FALSE; + else + pBtCoexist->bBinded = _TRUE; + + pBtCoexist->statistics.cntBind++; + + pBtCoexist->Adapter = padapter; + + pBtCoexist->stackInfo.bProfileNotified = _FALSE; + + pBtCoexist->btInfo.bBtCtrlAggBufSize = _FALSE; + pBtCoexist->btInfo.aggBufSize = 5; + + pBtCoexist->btInfo.bIncreaseScanDevNum = _FALSE; + pBtCoexist->btInfo.bMiracastPlusBt = _FALSE; + +#if 0 + chipType = HALBT_GetBtChipType(Adapter); + EXhalbtcoutsrc_SetChipType(chipType); + antNum = HALBT_GetPgAntNum(Adapter); + EXhalbtcoutsrc_SetAntNum(BT_COEX_ANT_TYPE_PG, antNum); +#endif + // set default antenna position to main port + pBtCoexist->boardInfo.btdmAntPos = BTC_ANTENNA_AT_MAIN_PORT; + + pBtCoexist->boardInfo.btdmAntDetFinish = _FALSE; + pBtCoexist->boardInfo.btdmAntNumByAntDet = 1; + + pBtCoexist->boardInfo.bTfbgaPackage = EXhalbtcoutsrc_IsTfbgaPackageType((PADAPTER)padapter); + + if (pBtCoexist->boardInfo.bTfbgaPackage) + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Package Type = TFBGA\n")); + else + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], Package Type = Non-TFBGA\n")); + + return _TRUE; +} + +u8 EXhalbtcoutsrc_InitlizeVariables(void *padapter) +{ + PBTC_COEXIST pBtCoexist = &GLBtCoexist; + + //pBtCoexist->statistics.cntBind++; + + halbtcoutsrc_DbgInit(); + +#ifdef CONFIG_PCI_HCI + pBtCoexist->chipInterface = BTC_INTF_PCI; +#elif defined(CONFIG_USB_HCI) + pBtCoexist->chipInterface = BTC_INTF_USB; +#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + pBtCoexist->chipInterface = BTC_INTF_SDIO; +#else + pBtCoexist->chipInterface = BTC_INTF_UNKNOWN; +#endif + + EXhalbtcoutsrc_BindBtCoexWithAdapter(padapter); + + pBtCoexist->fBtcRead1Byte = halbtcoutsrc_Read1Byte; + pBtCoexist->fBtcWrite1Byte = halbtcoutsrc_Write1Byte; + pBtCoexist->fBtcWrite1ByteBitMask = halbtcoutsrc_BitMaskWrite1Byte; + pBtCoexist->fBtcRead2Byte = halbtcoutsrc_Read2Byte; + pBtCoexist->fBtcWrite2Byte = halbtcoutsrc_Write2Byte; + pBtCoexist->fBtcRead4Byte = halbtcoutsrc_Read4Byte; + pBtCoexist->fBtcWrite4Byte = halbtcoutsrc_Write4Byte; + pBtCoexist->fBtcWriteLocalReg1Byte = halbtcoutsrc_WriteLocalReg1Byte; + + pBtCoexist->fBtcSetBbReg = halbtcoutsrc_SetBbReg; + pBtCoexist->fBtcGetBbReg = halbtcoutsrc_GetBbReg; + + pBtCoexist->fBtcSetRfReg = halbtcoutsrc_SetRfReg; + pBtCoexist->fBtcGetRfReg = halbtcoutsrc_GetRfReg; + + pBtCoexist->fBtcFillH2c = halbtcoutsrc_FillH2cCmd; + pBtCoexist->fBtcDispDbgMsg = halbtcoutsrc_DisplayDbgMsg; + + pBtCoexist->fBtcGet = halbtcoutsrc_Get; + pBtCoexist->fBtcSet = halbtcoutsrc_Set; + pBtCoexist->fBtcGetBtReg = halbtcoutsrc_GetBtReg; + pBtCoexist->fBtcSetBtReg = halbtcoutsrc_SetBtReg; + pBtCoexist->fBtcSetBtAntDetection = halbtcoutsrc_SetBtAntDetection; + + pBtCoexist->cliBuf = &GLBtcDbgBuf[0]; + + pBtCoexist->boardInfo.singleAntPath = 0; + + GLBtcWiFiInScanState = _FALSE; + + GLBtcWiFiInIQKState = _FALSE; + + GLBtcWiFiInIPS = _FALSE; + + GLBtcWiFiInLPS = _FALSE; + + GLBtcBtCoexAliveRegistered = _FALSE; + + /* BT Control H2C/C2H*/ + GLBtcBtMpOperSeq = 0; + _rtw_mutex_init(&GLBtcBtMpOperLock); + _init_timer(&GLBtcBtMpOperTimer, ((PADAPTER)padapter)->pnetdev, _btmpoper_timer_hdl, pBtCoexist); + _rtw_init_sema(&GLBtcBtMpRptSema, 0); + GLBtcBtMpRptSeq = 0; + GLBtcBtMpRptStatus = 0; + _rtw_memset(GLBtcBtMpRptRsp, 0, C2H_MAX_SIZE); + GLBtcBtMpRptRspSize = 0; + GLBtcBtMpRptWait = 0; + GLBtcBtMpRptWiFiOK = 0; + GLBtcBtMpRptBTOK = 0; + + return _TRUE; +} + +void EXhalbtcoutsrc_PowerOnSetting(PBTC_COEXIST pBtCoexist) +{ + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + /* Power on setting function is only added in 8723B currently */ + if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8723b2ant_PowerOnSetting(pBtCoexist); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8723b1ant_PowerOnSetting(pBtCoexist); + } +} + +void EXhalbtcoutsrc_PreLoadFirmware(PBTC_COEXIST pBtCoexist) +{ + if(!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + pBtCoexist->statistics.cntPreLoadFirmware++; + + if(IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) + { + if(pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8723b2ant_PreLoadFirmware(pBtCoexist); + else if(pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8723b1ant_PreLoadFirmware(pBtCoexist); + } +} + +void EXhalbtcoutsrc_InitHwConfig(PBTC_COEXIST pBtCoexist, u8 bWifiOnly) +{ + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + pBtCoexist->statistics.cntInitHwConfig++; + + if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) + { + if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) + EXhalbtc8821aCsr2ant_InitHwConfig(pBtCoexist, bWifiOnly); + else if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8821a2ant_InitHwConfig(pBtCoexist, bWifiOnly); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8821a1ant_InitHwConfig(pBtCoexist, bWifiOnly); + } + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8723b2ant_InitHwConfig(pBtCoexist, bWifiOnly); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8723b1ant_InitHwConfig(pBtCoexist, bWifiOnly); + } + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8703b2ant_InitHwConfig(pBtCoexist, bWifiOnly); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8703b1ant_InitHwConfig(pBtCoexist, bWifiOnly); + } + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8192e2ant_InitHwConfig(pBtCoexist, bWifiOnly); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8192e1ant_InitHwConfig(pBtCoexist, bWifiOnly); + } + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8812a2ant_InitHwConfig(pBtCoexist, bWifiOnly); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8812a1ant_InitHwConfig(pBtCoexist, bWifiOnly); + } +} + +void EXhalbtcoutsrc_InitCoexDm(PBTC_COEXIST pBtCoexist) +{ + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + pBtCoexist->statistics.cntInitCoexDm++; + + if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) + { + if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) + EXhalbtc8821aCsr2ant_InitCoexDm(pBtCoexist); + else if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8821a2ant_InitCoexDm(pBtCoexist); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8821a1ant_InitCoexDm(pBtCoexist); + } + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8723b2ant_InitCoexDm(pBtCoexist); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8723b1ant_InitCoexDm(pBtCoexist); + } + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8703b2ant_InitCoexDm(pBtCoexist); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8703b1ant_InitCoexDm(pBtCoexist); + } + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8192e2ant_InitCoexDm(pBtCoexist); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8192e1ant_InitCoexDm(pBtCoexist); + } + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8812a2ant_InitCoexDm(pBtCoexist); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8812a1ant_InitCoexDm(pBtCoexist); + } + + pBtCoexist->bInitilized = _TRUE; +} + +void EXhalbtcoutsrc_IpsNotify(PBTC_COEXIST pBtCoexist, u8 type) +{ + u8 ipsType; + + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + pBtCoexist->statistics.cntIpsNotify++; + if (pBtCoexist->bManualControl) + return; + + if (IPS_NONE == type) + { + ipsType = BTC_IPS_LEAVE; + GLBtcWiFiInIPS = _FALSE; + } + else + { + ipsType = BTC_IPS_ENTER; + GLBtcWiFiInIPS = _TRUE; + } + + // All notify is called in cmd thread, don't need to leave low power again +// halbtcoutsrc_LeaveLowPower(pBtCoexist); + + if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) + { + if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) + EXhalbtc8821aCsr2ant_IpsNotify(pBtCoexist, ipsType); + else if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8821a2ant_IpsNotify(pBtCoexist, ipsType); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8821a1ant_IpsNotify(pBtCoexist, ipsType); + } + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8723b2ant_IpsNotify(pBtCoexist, ipsType); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8723b1ant_IpsNotify(pBtCoexist, ipsType); + } + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8703b2ant_IpsNotify(pBtCoexist, ipsType); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8703b1ant_IpsNotify(pBtCoexist, ipsType); + } + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8192e2ant_IpsNotify(pBtCoexist, ipsType); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8192e1ant_IpsNotify(pBtCoexist, ipsType); + } + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8812a2ant_IpsNotify(pBtCoexist, ipsType); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8812a1ant_IpsNotify(pBtCoexist, ipsType); + } + +// halbtcoutsrc_NormalLowPower(pBtCoexist); +} + +void EXhalbtcoutsrc_LpsNotify(PBTC_COEXIST pBtCoexist, u8 type) +{ + u8 lpsType; + + + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + pBtCoexist->statistics.cntLpsNotify++; + if (pBtCoexist->bManualControl) + return; + + if (PS_MODE_ACTIVE == type) + { + lpsType = BTC_LPS_DISABLE; + GLBtcWiFiInLPS = _FALSE; + } + else + { + lpsType = BTC_LPS_ENABLE; + GLBtcWiFiInLPS = _TRUE; + } + + if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) + { + if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) + EXhalbtc8821aCsr2ant_LpsNotify(pBtCoexist, lpsType); + else if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8821a2ant_LpsNotify(pBtCoexist, lpsType); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8821a1ant_LpsNotify(pBtCoexist, lpsType); + } + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8723b2ant_LpsNotify(pBtCoexist, lpsType); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8723b1ant_LpsNotify(pBtCoexist, lpsType); + } + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8703b2ant_LpsNotify(pBtCoexist, lpsType); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8703b1ant_LpsNotify(pBtCoexist, lpsType); + } + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8192e2ant_LpsNotify(pBtCoexist, lpsType); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8192e1ant_LpsNotify(pBtCoexist, lpsType); + } + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8812a2ant_LpsNotify(pBtCoexist, lpsType); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8812a1ant_LpsNotify(pBtCoexist, lpsType); + } +} + +void EXhalbtcoutsrc_ScanNotify(PBTC_COEXIST pBtCoexist, u8 type) +{ + u8 scanType; + + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + pBtCoexist->statistics.cntScanNotify++; + if (pBtCoexist->bManualControl) + return; + + if (type) + { + scanType = BTC_SCAN_START; + GLBtcWiFiInScanState = _TRUE; + } + else + { + scanType = BTC_SCAN_FINISH; + GLBtcWiFiInScanState = _FALSE; + } + + // All notify is called in cmd thread, don't need to leave low power again +// halbtcoutsrc_LeaveLowPower(pBtCoexist); + + if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) + { + if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) + EXhalbtc8821aCsr2ant_ScanNotify(pBtCoexist, scanType); + else if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8821a2ant_ScanNotify(pBtCoexist, scanType); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8821a1ant_ScanNotify(pBtCoexist, scanType); + } + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8723b2ant_ScanNotify(pBtCoexist, scanType); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8723b1ant_ScanNotify(pBtCoexist, scanType); + } + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8703b2ant_ScanNotify(pBtCoexist, scanType); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8703b1ant_ScanNotify(pBtCoexist, scanType); + } + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8192e2ant_ScanNotify(pBtCoexist, scanType); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8192e1ant_ScanNotify(pBtCoexist, scanType); + } + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8812a2ant_ScanNotify(pBtCoexist, scanType); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8812a1ant_ScanNotify(pBtCoexist, scanType); + } + +// halbtcoutsrc_NormalLowPower(pBtCoexist); +} + +void EXhalbtcoutsrc_ConnectNotify(PBTC_COEXIST pBtCoexist, u8 action) +{ + u8 assoType; + + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + pBtCoexist->statistics.cntConnectNotify++; + if (pBtCoexist->bManualControl) + return; + + if (action) + assoType = BTC_ASSOCIATE_START; + else + assoType = BTC_ASSOCIATE_FINISH; + + // All notify is called in cmd thread, don't need to leave low power again +// halbtcoutsrc_LeaveLowPower(pBtCoexist); + + if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) + { + if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) + EXhalbtc8821aCsr2ant_ConnectNotify(pBtCoexist, assoType); + else if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8821a2ant_ConnectNotify(pBtCoexist, assoType); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8821a1ant_ConnectNotify(pBtCoexist, assoType); + } + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8723b2ant_ConnectNotify(pBtCoexist, assoType); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8723b1ant_ConnectNotify(pBtCoexist, assoType); + } + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8703b2ant_ConnectNotify(pBtCoexist, assoType); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8703b1ant_ConnectNotify(pBtCoexist, assoType); + } + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8192e2ant_ConnectNotify(pBtCoexist, assoType); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8192e1ant_ConnectNotify(pBtCoexist, assoType); + } + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8812a2ant_ConnectNotify(pBtCoexist, assoType); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8812a1ant_ConnectNotify(pBtCoexist, assoType); + } + +// halbtcoutsrc_NormalLowPower(pBtCoexist); +} + +void EXhalbtcoutsrc_MediaStatusNotify(PBTC_COEXIST pBtCoexist, RT_MEDIA_STATUS mediaStatus) +{ + u8 mStatus; + + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + pBtCoexist->statistics.cntMediaStatusNotify++; + if (pBtCoexist->bManualControl) + return; + + if (RT_MEDIA_CONNECT == mediaStatus) + mStatus = BTC_MEDIA_CONNECT; + else + mStatus = BTC_MEDIA_DISCONNECT; + + // All notify is called in cmd thread, don't need to leave low power again +// halbtcoutsrc_LeaveLowPower(pBtCoexist); + + if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) + { + if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) + EXhalbtc8821aCsr2ant_MediaStatusNotify(pBtCoexist, mStatus); + else if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8821a2ant_MediaStatusNotify(pBtCoexist, mStatus); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8821a1ant_MediaStatusNotify(pBtCoexist, mStatus); + } + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8723b2ant_MediaStatusNotify(pBtCoexist, mStatus); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8723b1ant_MediaStatusNotify(pBtCoexist, mStatus); + } + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8703b2ant_MediaStatusNotify(pBtCoexist, mStatus); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8703b1ant_MediaStatusNotify(pBtCoexist, mStatus); + } + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8192e2ant_MediaStatusNotify(pBtCoexist, mStatus); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8192e1ant_MediaStatusNotify(pBtCoexist, mStatus); + } + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8812a2ant_MediaStatusNotify(pBtCoexist, mStatus); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8812a1ant_MediaStatusNotify(pBtCoexist, mStatus); + } + +// halbtcoutsrc_NormalLowPower(pBtCoexist); +} + +void EXhalbtcoutsrc_SpecialPacketNotify(PBTC_COEXIST pBtCoexist, u8 pktType) +{ + u8 packetType; + + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + pBtCoexist->statistics.cntSpecialPacketNotify++; + if (pBtCoexist->bManualControl) + return; + + if (PACKET_DHCP == pktType) + packetType = BTC_PACKET_DHCP; + else if (PACKET_EAPOL == pktType) + packetType = BTC_PACKET_EAPOL; + else if (PACKET_ARP == pktType) + packetType = BTC_PACKET_ARP; + else + { + packetType = BTC_PACKET_UNKNOWN; + return; + } + + // All notify is called in cmd thread, don't need to leave low power again +// halbtcoutsrc_LeaveLowPower(pBtCoexist); + + if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) + { + if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) + EXhalbtc8821aCsr2ant_SpecialPacketNotify(pBtCoexist, packetType); + else if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8821a2ant_SpecialPacketNotify(pBtCoexist, packetType); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8821a1ant_SpecialPacketNotify(pBtCoexist, packetType); + } + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8723b2ant_SpecialPacketNotify(pBtCoexist, packetType); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8723b1ant_SpecialPacketNotify(pBtCoexist, packetType); + } + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8703b2ant_SpecialPacketNotify(pBtCoexist, packetType); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8703b1ant_SpecialPacketNotify(pBtCoexist, packetType); + } + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8192e2ant_SpecialPacketNotify(pBtCoexist, packetType); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8192e1ant_SpecialPacketNotify(pBtCoexist, packetType); + } + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8812a2ant_SpecialPacketNotify(pBtCoexist, packetType); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8812a1ant_SpecialPacketNotify(pBtCoexist, packetType); + } + +// halbtcoutsrc_NormalLowPower(pBtCoexist); +} + +void EXhalbtcoutsrc_BtInfoNotify(PBTC_COEXIST pBtCoexist, u8 *tmpBuf, u8 length) +{ + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + pBtCoexist->statistics.cntBtInfoNotify++; + + // All notify is called in cmd thread, don't need to leave low power again +// halbtcoutsrc_LeaveLowPower(pBtCoexist); + + if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) + { + if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) + EXhalbtc8821aCsr2ant_BtInfoNotify(pBtCoexist, tmpBuf, length); + else if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8821a2ant_BtInfoNotify(pBtCoexist, tmpBuf, length); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8821a1ant_BtInfoNotify(pBtCoexist, tmpBuf, length); + } + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8723b2ant_BtInfoNotify(pBtCoexist, tmpBuf, length); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8723b1ant_BtInfoNotify(pBtCoexist, tmpBuf, length); + } + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8703b2ant_BtInfoNotify(pBtCoexist, tmpBuf, length); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8703b1ant_BtInfoNotify(pBtCoexist, tmpBuf, length); + } + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8192e2ant_BtInfoNotify(pBtCoexist, tmpBuf, length); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8192e1ant_BtInfoNotify(pBtCoexist, tmpBuf, length); + } + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8812a2ant_BtInfoNotify(pBtCoexist, tmpBuf, length); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8812a1ant_BtInfoNotify(pBtCoexist, tmpBuf, length); + } + +// halbtcoutsrc_NormalLowPower(pBtCoexist); +} + +VOID +EXhalbtcoutsrc_RfStatusNotify( + IN PBTC_COEXIST pBtCoexist, + IN u1Byte type + ) +{ + if(!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + pBtCoexist->statistics.cntRfStatusNotify++; + + if(IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) + { + } + else if(IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) + { + if(pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8723b1ant_RfStatusNotify(pBtCoexist, type); + } + else if(IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) + { + if(pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8703b1ant_RfStatusNotify(pBtCoexist, type); + } + else if(IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) + { + } + else if(IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) + { + } +} + +void EXhalbtcoutsrc_StackOperationNotify(PBTC_COEXIST pBtCoexist, u8 type) +{ +#if 0 + u8 stackOpType; + + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + pBtCoexist->statistics.cntStackOperationNotify++; + if (pBtCoexist->bManualControl) + return; + + if ((HCI_BT_OP_INQUIRY_START == type) || + (HCI_BT_OP_PAGING_START == type) || + (HCI_BT_OP_PAIRING_START == type)) + { + stackOpType = BTC_STACK_OP_INQ_PAGE_PAIR_START; + } + else if ((HCI_BT_OP_INQUIRY_FINISH == type) || + (HCI_BT_OP_PAGING_SUCCESS == type) || + (HCI_BT_OP_PAGING_UNSUCCESS == type) || + (HCI_BT_OP_PAIRING_FINISH == type) ) + { + stackOpType = BTC_STACK_OP_INQ_PAGE_PAIR_FINISH; + } + else + { + stackOpType = BTC_STACK_OP_NONE; + } + +#endif +} + +void EXhalbtcoutsrc_HaltNotify(PBTC_COEXIST pBtCoexist) +{ + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) + { + if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) + EXhalbtc8821aCsr2ant_HaltNotify(pBtCoexist); + else if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8821a2ant_HaltNotify(pBtCoexist); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8821a1ant_HaltNotify(pBtCoexist); + } + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8723b2ant_HaltNotify(pBtCoexist); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8723b1ant_HaltNotify(pBtCoexist); + } + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8703b2ant_HaltNotify(pBtCoexist); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8703b1ant_HaltNotify(pBtCoexist); + } + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8192e2ant_HaltNotify(pBtCoexist); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8192e1ant_HaltNotify(pBtCoexist); + } + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8812a2ant_HaltNotify(pBtCoexist); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8812a1ant_HaltNotify(pBtCoexist); + } + + pBtCoexist->bBinded = FALSE; +} + +void EXhalbtcoutsrc_SwitchBtTRxMask(PBTC_COEXIST pBtCoexist) +{ + if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + { + halbtcoutsrc_SetBtReg(pBtCoexist, 0, 0x3c, 0x01); //BT goto standby while GNT_BT 1-->0 + } + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + { + halbtcoutsrc_SetBtReg(pBtCoexist, 0, 0x3c, 0x15); //BT goto standby while GNT_BT 1-->0 + } + } +} + +void EXhalbtcoutsrc_PnpNotify(PBTC_COEXIST pBtCoexist, u8 pnpState) +{ + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + // + // currently only 1ant we have to do the notification, + // once pnp is notified to sleep state, we have to leave LPS that we can sleep normally. + // + + if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8723b1ant_PnpNotify(pBtCoexist,pnpState); + else if(pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8723b2ant_PnpNotify(pBtCoexist,pnpState); + } + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8703b1ant_PnpNotify(pBtCoexist,pnpState); + else if(pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8703b2ant_PnpNotify(pBtCoexist,pnpState); + } + else if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) + { + if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) + EXhalbtc8821aCsr2ant_PnpNotify(pBtCoexist, pnpState); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8821a1ant_PnpNotify(pBtCoexist,pnpState); + else if(pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8821a2ant_PnpNotify(pBtCoexist,pnpState); + } + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8192e1ant_PnpNotify(pBtCoexist, pnpState); + } + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8812a1ant_PnpNotify(pBtCoexist, pnpState); + } +} + +void EXhalbtcoutsrc_ScoreBoardStatusNotify(PBTC_COEXIST pBtCoexist, u8 *tmpBuf, u8 length) +{ + if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) { + if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8703b1ant_ScoreBoardStatusNotify(pBtCoexist, tmpBuf, length); + } +} + +void EXhalbtcoutsrc_CoexDmSwitch(PBTC_COEXIST pBtCoexist) +{ + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + pBtCoexist->statistics.cntCoexDmSwitch++; + + halbtcoutsrc_LeaveLowPower(pBtCoexist); + + if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 1) + { + pBtCoexist->bStopCoexDm = TRUE; + EXhalbtc8723b1ant_CoexDmReset(pBtCoexist); + EXhalbtcoutsrc_SetAntNum(BT_COEX_ANT_TYPE_DETECTED, 2); + EXhalbtc8723b2ant_InitHwConfig(pBtCoexist, FALSE); + EXhalbtc8723b2ant_InitCoexDm(pBtCoexist); + pBtCoexist->bStopCoexDm = FALSE; + } + } + + halbtcoutsrc_NormalLowPower(pBtCoexist); +} + +void EXhalbtcoutsrc_Periodical(PBTC_COEXIST pBtCoexist) +{ + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + pBtCoexist->statistics.cntPeriodical++; + + // Periodical should be called in cmd thread, + // don't need to leave low power again +// halbtcoutsrc_LeaveLowPower(pBtCoexist); + + if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) + { + if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) + EXhalbtc8821aCsr2ant_Periodical(pBtCoexist); + else if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8821a2ant_Periodical(pBtCoexist); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + { + if (!halbtcoutsrc_UnderIps(pBtCoexist)) + { + EXhalbtc8821a1ant_Periodical(pBtCoexist); + } + } + } + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8723b2ant_Periodical(pBtCoexist); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8723b1ant_Periodical(pBtCoexist); + } + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8703b2ant_Periodical(pBtCoexist); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8703b1ant_Periodical(pBtCoexist); + } + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8192e2ant_Periodical(pBtCoexist); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8192e1ant_Periodical(pBtCoexist); + } + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8812a2ant_Periodical(pBtCoexist); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8812a1ant_Periodical(pBtCoexist); + } + +// halbtcoutsrc_NormalLowPower(pBtCoexist); +} + +void EXhalbtcoutsrc_DbgControl(PBTC_COEXIST pBtCoexist, u8 opCode, u8 opLen, u8 *pData) +{ + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + pBtCoexist->statistics.cntDbgCtrl++; + + // This function doesn't be called yet, + // default no need to leave low power to avoid deadlock +// halbtcoutsrc_LeaveLowPower(pBtCoexist); + + if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8192e1ant_DbgControl(pBtCoexist, opCode, opLen, pData); + } + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8812a2ant_DbgControl(pBtCoexist, opCode, opLen, pData); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8812a1ant_DbgControl(pBtCoexist, opCode, opLen, pData); + } + +// halbtcoutsrc_NormalLowPower(pBtCoexist); +} + +#if 0 +VOID +EXhalbtcoutsrc_AntennaDetection( + IN PBTC_COEXIST pBtCoexist, + IN u4Byte centFreq, + IN u4Byte offset, + IN u4Byte span, + IN u4Byte seconds + ) +{ + if(!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + /* Need to refine the following power save operations to enable this function in the future */ +#if 0 + IPSDisable(pBtCoexist->Adapter, FALSE, 0); + LeisurePSLeave(pBtCoexist->Adapter, LPS_DISABLE_BT_COEX); +#endif + + if(IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) + { + if(pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8723b1ant_AntennaDetection(pBtCoexist, centFreq, offset, span, seconds); + } + + //IPSReturn(pBtCoexist->Adapter, 0xff); +} +#endif + +void EXhalbtcoutsrc_StackUpdateProfileInfo(void) +{ +#ifdef CONFIG_BT_COEXIST_SOCKET_TRX + PBTC_COEXIST pBtCoexist = &GLBtCoexist; + PADAPTER padapter = (PADAPTER)GLBtCoexist.Adapter; + PBT_MGNT pBtMgnt = &padapter->coex_info.BtMgnt; + u8 i; + + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + pBtCoexist->stackInfo.bProfileNotified = _TRUE; + + pBtCoexist->stackInfo.numOfLink = + pBtMgnt->ExtConfig.NumberOfACL+pBtMgnt->ExtConfig.NumberOfSCO; + + // reset first + pBtCoexist->stackInfo.bBtLinkExist = _FALSE; + pBtCoexist->stackInfo.bScoExist = _FALSE; + pBtCoexist->stackInfo.bAclExist = _FALSE; + pBtCoexist->stackInfo.bA2dpExist = _FALSE; + pBtCoexist->stackInfo.bHidExist = _FALSE; + pBtCoexist->stackInfo.numOfHid = 0; + pBtCoexist->stackInfo.bPanExist = _FALSE; + + if (!pBtMgnt->ExtConfig.NumberOfACL) + pBtCoexist->stackInfo.minBtRssi = 0; + + if (pBtCoexist->stackInfo.numOfLink) + { + pBtCoexist->stackInfo.bBtLinkExist = _TRUE; + if (pBtMgnt->ExtConfig.NumberOfSCO) + pBtCoexist->stackInfo.bScoExist = _TRUE; + if (pBtMgnt->ExtConfig.NumberOfACL) + pBtCoexist->stackInfo.bAclExist = _TRUE; + } + + for (i=0; iExtConfig.NumberOfACL; i++) + { + if (BT_PROFILE_A2DP == pBtMgnt->ExtConfig.aclLink[i].BTProfile) + { + pBtCoexist->stackInfo.bA2dpExist = _TRUE; + } + else if (BT_PROFILE_PAN == pBtMgnt->ExtConfig.aclLink[i].BTProfile) + { + pBtCoexist->stackInfo.bPanExist = _TRUE; + } + else if (BT_PROFILE_HID == pBtMgnt->ExtConfig.aclLink[i].BTProfile) + { + pBtCoexist->stackInfo.bHidExist = _TRUE; + pBtCoexist->stackInfo.numOfHid++; + } + else + { + pBtCoexist->stackInfo.bUnknownAclExist = _TRUE; + } + } +#endif //CONFIG_BT_COEXIST_SOCKET_TRX +} + +void EXhalbtcoutsrc_UpdateMinBtRssi(s8 btRssi) +{ + PBTC_COEXIST pBtCoexist = &GLBtCoexist; + + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + pBtCoexist->stackInfo.minBtRssi = btRssi; +} + +void EXhalbtcoutsrc_SetHciVersion(u16 hciVersion) +{ + PBTC_COEXIST pBtCoexist = &GLBtCoexist; + + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + pBtCoexist->stackInfo.hciVersion = hciVersion; +} + +void EXhalbtcoutsrc_SetBtPatchVersion(u16 btHciVersion, u16 btPatchVersion) +{ + PBTC_COEXIST pBtCoexist = &GLBtCoexist; + + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + pBtCoexist->btInfo.btRealFwVer = btPatchVersion; + pBtCoexist->btInfo.btHciVer = btHciVersion; +} + +#if 0 +void EXhalbtcoutsrc_SetBtExist(u8 bBtExist) +{ + GLBtCoexist.boardInfo.bBtExist = bBtExist; +} +#endif +void EXhalbtcoutsrc_SetChipType(u8 chipType) +{ + switch(chipType) + { + default: + case BT_2WIRE: + case BT_ISSC_3WIRE: + case BT_ACCEL: + case BT_RTL8756: + GLBtCoexist.boardInfo.btChipType = BTC_CHIP_UNDEF; + break; + case BT_CSR_BC4: + GLBtCoexist.boardInfo.btChipType = BTC_CHIP_CSR_BC4; + break; + case BT_CSR_BC8: + GLBtCoexist.boardInfo.btChipType = BTC_CHIP_CSR_BC8; + break; + case BT_RTL8723A: + GLBtCoexist.boardInfo.btChipType = BTC_CHIP_RTL8723A; + break; + case BT_RTL8821: + GLBtCoexist.boardInfo.btChipType = BTC_CHIP_RTL8821; + break; + case BT_RTL8723B: + GLBtCoexist.boardInfo.btChipType = BTC_CHIP_RTL8723B; + break; + } +} + +void EXhalbtcoutsrc_SetAntNum(u8 type, u8 antNum) +{ + if (BT_COEX_ANT_TYPE_PG == type) + { + GLBtCoexist.boardInfo.pgAntNum = antNum; + GLBtCoexist.boardInfo.btdmAntNum = antNum; +#if 0 + //The antenna position: Main (default) or Aux for pgAntNum=2 && btdmAntNum =1 + //The antenna position should be determined by auto-detect mechanism + // The following is assumed to main, and those must be modified if y auto-detect mechanism is ready + if ((GLBtCoexist.boardInfo.pgAntNum == 2) && (GLBtCoexist.boardInfo.btdmAntNum == 1) ) + GLBtCoexist.boardInfo.btdmAntPos = BTC_ANTENNA_AT_MAIN_PORT; + else + GLBtCoexist.boardInfo.btdmAntPos = BTC_ANTENNA_AT_MAIN_PORT; +#endif + } + else if (BT_COEX_ANT_TYPE_ANTDIV == type) + { + GLBtCoexist.boardInfo.btdmAntNum = antNum; + //GLBtCoexist.boardInfo.btdmAntPos = BTC_ANTENNA_AT_MAIN_PORT; + } + else if (BT_COEX_ANT_TYPE_DETECTED == type) + { + GLBtCoexist.boardInfo.btdmAntNum = antNum; + //GLBtCoexist.boardInfo.btdmAntPos = BTC_ANTENNA_AT_MAIN_PORT; + } +} + +// +// Currently used by 8723b only, S0 or S1 +// +void EXhalbtcoutsrc_SetSingleAntPath(u8 singleAntPath) +{ + GLBtCoexist.boardInfo.singleAntPath = singleAntPath; +} + +void EXhalbtcoutsrc_DisplayBtCoexInfo(PBTC_COEXIST pBtCoexist) +{ + if (!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + halbtcoutsrc_LeaveLowPower(pBtCoexist); + + if (IS_HARDWARE_TYPE_8821(pBtCoexist->Adapter)) + { + if (halbtcoutsrc_IsCsrBtCoex(pBtCoexist) == _TRUE) + EXhalbtc8821aCsr2ant_DisplayCoexInfo(pBtCoexist); + else if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8821a2ant_DisplayCoexInfo(pBtCoexist); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8821a1ant_DisplayCoexInfo(pBtCoexist); + } + else if (IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8723b2ant_DisplayCoexInfo(pBtCoexist); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8723b1ant_DisplayCoexInfo(pBtCoexist); + } + else if (IS_HARDWARE_TYPE_8703B(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8703b2ant_DisplayCoexInfo(pBtCoexist); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8703b1ant_DisplayCoexInfo(pBtCoexist); + } + else if (IS_HARDWARE_TYPE_8192E(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8192e2ant_DisplayCoexInfo(pBtCoexist); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8192e1ant_DisplayCoexInfo(pBtCoexist); + } + else if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) + { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8812a2ant_DisplayCoexInfo(pBtCoexist); + else if (pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8812a1ant_DisplayCoexInfo(pBtCoexist); + } + + halbtcoutsrc_NormalLowPower(pBtCoexist); +} + +void EXhalbtcoutsrc_DisplayAntDetection(PBTC_COEXIST pBtCoexist) +{ + if(!halbtcoutsrc_IsBtCoexistAvailable(pBtCoexist)) + return; + + halbtcoutsrc_LeaveLowPower(pBtCoexist); + + if(IS_HARDWARE_TYPE_8723B(pBtCoexist->Adapter)) + { + if(pBtCoexist->boardInfo.btdmAntNum == 1) + EXhalbtc8723b1ant_DisplayAntDetection(pBtCoexist); + } + + halbtcoutsrc_NormalLowPower(pBtCoexist); +} + +void EXhalbtcoutsrc_BTOffOnNotify(PBTC_COEXIST pBtCoexist, u8 bBTON) +{ + + if (IS_HARDWARE_TYPE_8812(pBtCoexist->Adapter)) { + if (pBtCoexist->boardInfo.btdmAntNum == 2) + EXhalbtc8812a2ant_BTOffOnNotify(pBtCoexist, (bBTON == _TRUE)?BTC_BT_ON:BTC_BT_OFF); + } + +} + +static void halbt_InitHwConfig92C(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData; + u8 u1Tmp; + + + pHalData = GET_HAL_DATA(padapter); + if( (pHalData->bt_coexist.btChipType == BT_CSR_BC4) || + (pHalData->bt_coexist.btChipType == BT_CSR_BC8)) + { + if (pHalData->rf_type == RF_1T1R) + { + // Config to 1T1R + u1Tmp = rtw_read8(padapter, rOFDM0_TRxPathEnable); + u1Tmp &= ~BIT(1); + rtw_write8(padapter, rOFDM0_TRxPathEnable, u1Tmp); + RT_DISP(FBT, BT_TRACE, ("[BTCoex], BT write 0xC04 = 0x%x\n", u1Tmp)); + + u1Tmp = rtw_read8(padapter, rOFDM1_TRxPathEnable); + u1Tmp &= ~BIT(1); + rtw_write8(padapter, rOFDM1_TRxPathEnable, u1Tmp); + RT_DISP(FBT, BT_TRACE, ("[BTCoex], BT write 0xD04 = 0x%x\n", u1Tmp)); + } + } +} + +static void halbt_InitHwConfig92D(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData; + u8 u1Tmp; + + pHalData = GET_HAL_DATA(padapter); + if ((pHalData->bt_coexist.btChipType == BT_CSR_BC4) || + (pHalData->bt_coexist.btChipType == BT_CSR_BC8)) + { + if (pHalData->rf_type == RF_1T1R) + { + // Config to 1T1R + u1Tmp = rtw_read8(padapter, rOFDM0_TRxPathEnable); + u1Tmp &= ~BIT(1); + rtw_write8(padapter, rOFDM0_TRxPathEnable, u1Tmp); + RT_DISP(FBT, BT_TRACE, ("[BTCoex], BT write 0xC04 = 0x%x\n", u1Tmp)); + + u1Tmp = rtw_read8(padapter, rOFDM1_TRxPathEnable); + u1Tmp &= ~BIT(1); + rtw_write8(padapter, rOFDM1_TRxPathEnable, u1Tmp); + RT_DISP(FBT, BT_TRACE, ("[BTCoex], BT write 0xD04 = 0x%x\n", u1Tmp)); + } + } +} + +/* + * Description: + * Run BT-Coexist mechansim or not + * + */ +void hal_btcoex_SetBTCoexist(PADAPTER padapter, u8 bBtExist) +{ + PHAL_DATA_TYPE pHalData; + + + pHalData = GET_HAL_DATA(padapter); + pHalData->bt_coexist.bBtExist = bBtExist; + + //EXhalbtcoutsrc_SetBtExist(bBtExist); +} + +/* + * Dewcription: + * Check is co-exist mechanism enabled or not + * + * Return: + * _TRUE Enable BT co-exist mechanism + * _FALSE Disable BT co-exist mechanism + */ +u8 hal_btcoex_IsBtExist(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData; + + + pHalData = GET_HAL_DATA(padapter); + return pHalData->bt_coexist.bBtExist; +} + +u8 hal_btcoex_IsBtDisabled(PADAPTER padapter) +{ + if (!hal_btcoex_IsBtExist(padapter)) + return _TRUE; + + if (GLBtCoexist.btInfo.bBtDisabled) + return _TRUE; + else + return _FALSE; +} + +void hal_btcoex_SetChipType(PADAPTER padapter, u8 chipType) +{ + PHAL_DATA_TYPE pHalData; + + + pHalData = GET_HAL_DATA(padapter); + pHalData->bt_coexist.btChipType = chipType; + + EXhalbtcoutsrc_SetChipType(chipType); +} + +u8 hal_btcoex_GetChipType(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData; + + + pHalData = GET_HAL_DATA(padapter); + return pHalData->bt_coexist.btChipType; +} + +void hal_btcoex_SetPgAntNum(PADAPTER padapter, u8 antNum) +{ + PHAL_DATA_TYPE pHalData; + + + pHalData = GET_HAL_DATA(padapter); + + pHalData->bt_coexist.btTotalAntNum = antNum; + EXhalbtcoutsrc_SetAntNum(BT_COEX_ANT_TYPE_PG, antNum); +} + +u8 hal_btcoex_GetPgAntNum(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData; + + + pHalData = GET_HAL_DATA(padapter); + + return pHalData->bt_coexist.btTotalAntNum; +} + +void hal_btcoex_SetSingleAntPath(PADAPTER padapter, u8 singleAntPath) +{ + EXhalbtcoutsrc_SetSingleAntPath(singleAntPath); +} + +u8 hal_btcoex_Initialize(PADAPTER padapter) +{ + u8 ret1; + u8 ret2; + + + _rtw_memset(&GLBtCoexist, 0, sizeof(GLBtCoexist)); + ret1 = EXhalbtcoutsrc_InitlizeVariables((void*)padapter); + ret2 = (ret1==_TRUE) ? _TRUE : _FALSE; + + return ret2; +} + +void hal_btcoex_PowerOnSetting(PADAPTER padapter) +{ + EXhalbtcoutsrc_PowerOnSetting(&GLBtCoexist); +} + +void hal_btcoex_PreLoadFirmware(PADAPTER padapter) +{ + EXhalbtcoutsrc_PreLoadFirmware(&GLBtCoexist); +} + +void hal_btcoex_InitHwConfig(PADAPTER padapter, u8 bWifiOnly) +{ + if (!hal_btcoex_IsBtExist(padapter)) + return; + + EXhalbtcoutsrc_InitHwConfig(&GLBtCoexist, bWifiOnly); + EXhalbtcoutsrc_InitCoexDm(&GLBtCoexist); +} + +void hal_btcoex_IpsNotify(PADAPTER padapter, u8 type) +{ + EXhalbtcoutsrc_IpsNotify(&GLBtCoexist, type); +} + +void hal_btcoex_LpsNotify(PADAPTER padapter, u8 type) +{ + EXhalbtcoutsrc_LpsNotify(&GLBtCoexist, type); +} + +void hal_btcoex_ScanNotify(PADAPTER padapter, u8 type) +{ + EXhalbtcoutsrc_ScanNotify(&GLBtCoexist, type); +} + +void hal_btcoex_ConnectNotify(PADAPTER padapter, u8 action) +{ + EXhalbtcoutsrc_ConnectNotify(&GLBtCoexist, action); +} + +void hal_btcoex_MediaStatusNotify(PADAPTER padapter, u8 mediaStatus) +{ + EXhalbtcoutsrc_MediaStatusNotify(&GLBtCoexist, mediaStatus); +} + +void hal_btcoex_SpecialPacketNotify(PADAPTER padapter, u8 pktType) +{ + EXhalbtcoutsrc_SpecialPacketNotify(&GLBtCoexist, pktType); +} + +void hal_btcoex_IQKNotify(PADAPTER padapter, u8 state) +{ + GLBtcWiFiInIQKState = state; +} + +void hal_btcoex_BtInfoNotify(PADAPTER padapter, u8 length, u8 *tmpBuf) +{ + if (GLBtcWiFiInIQKState == _TRUE) + return; + + EXhalbtcoutsrc_BtInfoNotify(&GLBtCoexist, tmpBuf, length); +} + +void hal_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf) +{ + u8 extid, status, len, seq; + + + if (!GLBtcBtMpRptWait) + return; + + if ((length < 3) || (!tmpBuf)) + return; + + extid = tmpBuf[0]; + /* not response from BT FW then exit*/ + switch (extid) { + case C2H_WIFI_FW_ACTIVE_RSP: + GLBtcBtMpRptWiFiOK = 1; + return; + + case C2H_TRIG_BY_BT_FW: + _cancel_timer_ex(&GLBtcBtMpOperTimer); + GLBtcBtMpRptWait = 0; + GLBtcBtMpRptBTOK = 1; + break; + + default: + return; + } + + status = tmpBuf[1] & 0xF; + len = tmpBuf[1] >> 4; + seq = tmpBuf[2] >> 4; + + GLBtcBtMpRptSeq = seq; + GLBtcBtMpRptStatus = status; + _rtw_memcpy(GLBtcBtMpRptRsp, tmpBuf+3, len); + GLBtcBtMpRptRspSize = len; + _rtw_up_sema(&GLBtcBtMpRptSema); +} + +void hal_btcoex_SuspendNotify(PADAPTER padapter, u8 state) +{ + if (state == 1) + state = BTC_WIFI_PNP_SLEEP; + else + state = BTC_WIFI_PNP_WAKE_UP; + + EXhalbtcoutsrc_PnpNotify(&GLBtCoexist, state); +} + +void hal_btcoex_HaltNotify(PADAPTER padapter) +{ + EXhalbtcoutsrc_HaltNotify(&GLBtCoexist); +} + +void hal_btcoex_ScoreBoardStatusNotify(PADAPTER padapter, u8 length, u8 *tmpBuf) +{ + EXhalbtcoutsrc_ScoreBoardStatusNotify(&GLBtCoexist, tmpBuf, length); +} + +void hal_btcoex_SwitchBtTRxMask(PADAPTER padapter) +{ + EXhalbtcoutsrc_SwitchBtTRxMask(&GLBtCoexist); +} + +void hal_btcoex_Hanlder(PADAPTER padapter) +{ + EXhalbtcoutsrc_Periodical(&GLBtCoexist); +} + +s32 hal_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter) +{ + return (s32)GLBtCoexist.btInfo.bRejectAggPkt; +} + +s32 hal_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER padapter) +{ + return (s32)GLBtCoexist.btInfo.bBtCtrlAggBufSize; +} + +u32 hal_btcoex_GetAMPDUSize(PADAPTER padapter) +{ + return (u32)GLBtCoexist.btInfo.aggBufSize; +} + +void hal_btcoex_SetManualControl(PADAPTER padapter, u8 bmanual) +{ + GLBtCoexist.bManualControl = bmanual; +} + +u8 hal_btcoex_1Ant(PADAPTER padapter) +{ + if (hal_btcoex_IsBtExist(padapter) == _FALSE) + return _FALSE; + + if (GLBtCoexist.boardInfo.btdmAntNum == 1) + return _TRUE; + + return _FALSE; +} + +u8 hal_btcoex_IsBtControlLps(PADAPTER padapter) +{ + if (hal_btcoex_IsBtExist(padapter) == _FALSE) + return _FALSE; + + if (GLBtCoexist.btInfo.bBtDisabled) + return _FALSE; + + if (GLBtCoexist.btInfo.bBtCtrlLps) + return _TRUE; + + return _FALSE; +} + +u8 hal_btcoex_IsLpsOn(PADAPTER padapter) +{ + if (hal_btcoex_IsBtExist(padapter) == _FALSE) + return _FALSE; + + if (GLBtCoexist.btInfo.bBtDisabled) + return _FALSE; + + if (GLBtCoexist.btInfo.bBtLpsOn) + return _TRUE; + + return _FALSE; +} + +u8 hal_btcoex_RpwmVal(PADAPTER padapter) +{ + return GLBtCoexist.btInfo.rpwmVal; +} + +u8 hal_btcoex_LpsVal(PADAPTER padapter) +{ + return GLBtCoexist.btInfo.lpsVal; +} + +u32 hal_btcoex_GetRaMask(PADAPTER padapter) +{ + if (!hal_btcoex_IsBtExist(padapter)) + return 0; + + if (GLBtCoexist.btInfo.bBtDisabled) + return 0; + + /* Modify by YiWei , suggest by Cosa and Jenyu + * Remove the limit antenna number , because 2 antenna case (ex: 8192eu)also want to get BT coex report rate mask. + */ + /*if (GLBtCoexist.boardInfo.btdmAntNum != 1) + return 0;*/ + + return GLBtCoexist.btInfo.raMask; +} + +void hal_btcoex_RecordPwrMode(PADAPTER padapter, u8 *pCmdBuf, u8 cmdLen) +{ + RT_TRACE(COMP_COEX, DBG_LOUD, ("[BTCoex], FW write pwrModeCmd=0x%04x%08x\n", + pCmdBuf[0]<<8|pCmdBuf[1], + pCmdBuf[2]<<24|pCmdBuf[3]<<16|pCmdBuf[4]<<8|pCmdBuf[5])); + + _rtw_memcpy(GLBtCoexist.pwrModeVal, pCmdBuf, cmdLen); +} + +void hal_btcoex_DisplayBtCoexInfo(PADAPTER padapter, u8 *pbuf, u32 bufsize) +{ + PBTCDBGINFO pinfo; + + + pinfo = &GLBtcDbgInfo; + DBG_BT_INFO_INIT(pinfo, pbuf, bufsize); + EXhalbtcoutsrc_DisplayBtCoexInfo(&GLBtCoexist); + DBG_BT_INFO_INIT(pinfo, NULL, 0); +} + +void hal_btcoex_SetDBG(PADAPTER padapter, u32 *pDbgModule) +{ + u32 i; + + + if (NULL == pDbgModule) + return; + + for (i = 0; i < COMP_MAX; i++) + GLBtcDbgType[i] = pDbgModule[i]; +} + +u32 hal_btcoex_GetDBG(PADAPTER padapter, u8 *pStrBuf, u32 bufSize) +{ + s32 count; + u8 *pstr; + u32 leftSize; + + + if ((NULL == pStrBuf) || (0 == bufSize)) + return 0; + + count = 0; + pstr = pStrBuf; + leftSize = bufSize; +// DBG_871X(FUNC_ADPT_FMT ": bufsize=%d\n", FUNC_ADPT_ARG(padapter), bufSize); + + count = rtw_sprintf(pstr, leftSize, "#define DBG\t%d\n", DBG); + if ((count < 0) || (count >= leftSize)) + goto exit; + pstr += count; + leftSize -= count; + + count = rtw_sprintf(pstr, leftSize, "BTCOEX Debug Setting:\n"); + if ((count < 0) || (count >= leftSize)) + goto exit; + pstr += count; + leftSize -= count; + + count = rtw_sprintf(pstr, leftSize, + "COMP_COEX: 0x%08X\n\n", + GLBtcDbgType[COMP_COEX]); + if ((count < 0) || (count >= leftSize)) + goto exit; + pstr += count; + leftSize -= count; + +#if 0 + count = rtw_sprintf(pstr, leftSize, "INTERFACE Debug Setting Definition:\n"); + if ((count < 0) || (count >= leftSize)) + goto exit; + pstr += count; + leftSize -= count; + count = rtw_sprintf(pstr, leftSize, "\tbit[0]=%d for INTF_INIT\n", + GLBtcDbgType[BTC_MSG_INTERFACE]&INTF_INIT?1:0); + if ((count < 0) || (count >= leftSize)) + goto exit; + pstr += count; + leftSize -= count; + count = rtw_sprintf(pstr, leftSize, "\tbit[2]=%d for INTF_NOTIFY\n\n", + GLBtcDbgType[BTC_MSG_INTERFACE]&INTF_NOTIFY?1:0); + if ((count < 0) || (count >= leftSize)) + goto exit; + pstr += count; + leftSize -= count; + + count = rtw_sprintf(pstr, leftSize, "ALGORITHM Debug Setting Definition:\n"); + if ((count < 0) || (count >= leftSize)) + goto exit; + pstr += count; + leftSize -= count; + count = rtw_sprintf(pstr, leftSize, "\tbit[0]=%d for BT_RSSI_STATE\n", + GLBtcDbgType[BTC_MSG_ALGORITHM]&ALGO_BT_RSSI_STATE?1:0); + if ((count < 0) || (count >= leftSize)) + goto exit; + pstr += count; + leftSize -= count; + count = rtw_sprintf(pstr, leftSize, "\tbit[1]=%d for WIFI_RSSI_STATE\n", + GLBtcDbgType[BTC_MSG_ALGORITHM]&ALGO_WIFI_RSSI_STATE?1:0); + if ((count < 0) || (count >= leftSize)) + goto exit; + pstr += count; + leftSize -= count; + count = rtw_sprintf(pstr, leftSize, "\tbit[2]=%d for BT_MONITOR\n", + GLBtcDbgType[BTC_MSG_ALGORITHM]&ALGO_BT_MONITOR?1:0); + if ((count < 0) || (count >= leftSize)) + goto exit; + pstr += count; + leftSize -= count; + count = rtw_sprintf(pstr, leftSize, "\tbit[3]=%d for TRACE\n", + GLBtcDbgType[BTC_MSG_ALGORITHM]&ALGO_TRACE?1:0); + if ((count < 0) || (count >= leftSize)) + goto exit; + pstr += count; + leftSize -= count; + count = rtw_sprintf(pstr, leftSize, "\tbit[4]=%d for TRACE_FW\n", + GLBtcDbgType[BTC_MSG_ALGORITHM]&ALGO_TRACE_FW?1:0); + if ((count < 0) || (count >= leftSize)) + goto exit; + pstr += count; + leftSize -= count; + count = rtw_sprintf(pstr, leftSize, "\tbit[5]=%d for TRACE_FW_DETAIL\n", + GLBtcDbgType[BTC_MSG_ALGORITHM]&ALGO_TRACE_FW_DETAIL?1:0); + if ((count < 0) || (count >= leftSize)) + goto exit; + pstr += count; + leftSize -= count; + count = rtw_sprintf(pstr, leftSize, "\tbit[6]=%d for TRACE_FW_EXEC\n", + GLBtcDbgType[BTC_MSG_ALGORITHM]&ALGO_TRACE_FW_EXEC?1:0); + if ((count < 0) || (count >= leftSize)) + goto exit; + pstr += count; + leftSize -= count; + count = rtw_sprintf(pstr, leftSize, "\tbit[7]=%d for TRACE_SW\n", + GLBtcDbgType[BTC_MSG_ALGORITHM]&ALGO_TRACE_SW?1:0); + if ((count < 0) || (count >= leftSize)) + goto exit; + pstr += count; + leftSize -= count; + count = rtw_sprintf(pstr, leftSize, "\tbit[8]=%d for TRACE_SW_DETAIL\n", + GLBtcDbgType[BTC_MSG_ALGORITHM]&ALGO_TRACE_SW_DETAIL?1:0); + if ((count < 0) || (count >= leftSize)) + goto exit; + pstr += count; + leftSize -= count; + count = rtw_sprintf(pstr, leftSize, "\tbit[9]=%d for TRACE_SW_EXEC\n", + GLBtcDbgType[BTC_MSG_ALGORITHM]&ALGO_TRACE_SW_EXEC?1:0); + if ((count < 0) || (count >= leftSize)) + goto exit; + pstr += count; + leftSize -= count; +#endif + +exit: + count = pstr - pStrBuf; +// DBG_871X(FUNC_ADPT_FMT ": usedsize=%d\n", FUNC_ADPT_ARG(padapter), count); + + return count; +} + +u8 hal_btcoex_IncreaseScanDeviceNum(PADAPTER padapter) +{ + if (!hal_btcoex_IsBtExist(padapter)) + return _FALSE; + + if (GLBtCoexist.btInfo.bIncreaseScanDevNum) + return _TRUE; + + return _FALSE; +} + +u8 hal_btcoex_IsBtLinkExist(PADAPTER padapter) +{ + if (GLBtCoexist.btLinkInfo.bBtLinkExist) + return _TRUE; + + return _FALSE; +} + +void hal_btcoex_SetBtPatchVersion(PADAPTER padapter,u16 btHciVer,u16 btPatchVer) +{ + EXhalbtcoutsrc_SetBtPatchVersion(btHciVer,btPatchVer); +} + +void hal_btcoex_SetHciVersion(PADAPTER padapter, u16 hciVersion) +{ + EXhalbtcoutsrc_SetHciVersion(hciVersion); +} + +void hal_btcoex_StackUpdateProfileInfo(void) +{ + EXhalbtcoutsrc_StackUpdateProfileInfo(); +} + +void hal_btcoex_BTOffOnNotify(PADAPTER padapter, u8 bBTON) +{ + EXhalbtcoutsrc_BTOffOnNotify(&GLBtCoexist, bBTON); +} + +/* + * Description: + * Setting BT coex antenna isolation type . + * coex mechanisn/ spital stream/ best throughput + * anttype = 0 , PSTDMA / 2SS / 0.5T , bad isolation , WiFi/BT ANT Distance<15cm , (<20dB) for 2,3 antenna + * anttype = 1 , PSTDMA / 1SS / 0.5T , normal isolaiton , 50cm>WiFi/BT ANT Distance>15cm , (>20dB) for 2 antenna + * anttype = 2 , TDMA / 2SS / T , normal isolaiton , 50cm>WiFi/BT ANT Distance>15cm , (>20dB) for 3 antenna + * anttype = 3 , no TDMA / 1SS / 0.5T , good isolation , WiFi/BT ANT Distance >50cm , (>40dB) for 2 antenna + * anttype = 4 , no TDMA / 2SS / T , good isolation , WiFi/BT ANT Distance >50cm , (>40dB) for 3 antenna + * wifi only throughput ~ T + * wifi/BT share one antenna with SPDT + */ +void hal_btcoex_SetAntIsolationType(PADAPTER padapter, u8 anttype) +{ + PHAL_DATA_TYPE pHalData; + PBTC_COEXIST pBtCoexist = &GLBtCoexist; + + /*DBG_871X("####%s , anttype = %d , %d\n" , __func__ , anttype , __LINE__); */ + pHalData = GET_HAL_DATA(padapter); + + + pHalData->bt_coexist.btAntisolation = anttype; + + switch (pHalData->bt_coexist.btAntisolation) { + case 0: + pBtCoexist->boardInfo.antType = (u1Byte)BTC_ANT_TYPE_0; + break; + case 1: + pBtCoexist->boardInfo.antType = (u1Byte)BTC_ANT_TYPE_1; + break; + case 2: + pBtCoexist->boardInfo.antType = (u1Byte)BTC_ANT_TYPE_2; + break; + case 3: + pBtCoexist->boardInfo.antType = (u1Byte)BTC_ANT_TYPE_3; + break; + case 4: + pBtCoexist->boardInfo.antType = (u1Byte)BTC_ANT_TYPE_4; + break; + } + +} + +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE +int +hal_btcoex_ParseAntIsolationConfigFile( + PADAPTER Adapter, + char* buffer +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u32 i = 0 , j = 0; + char *szLine , *ptmp; + int rtStatus = _SUCCESS; + char param_value_string[10]; + u8 param_value; + u8 anttype = 4; + + u8 ant_num = 3 , ant_distance = 50 , rfe_type = 1; + + typedef struct ant_isolation { + char *param_name; /* antenna isolation config parameter name */ + u8 *value; /* antenna isolation config parameter value */ + } ANT_ISOLATION; + + ANT_ISOLATION ant_isolation_param[] = { + {"ANT_NUMBER" , &ant_num}, + {"ANT_DISTANCE" , &ant_distance}, + {"RFE_TYPE" , &rfe_type}, + {NULL , 0} + }; + + + + /* DBG_871X("===>Hal_ParseAntIsolationConfigFile()\n" ); */ + + ptmp = buffer; + for (szLine = GetLineFromBuffer(ptmp) ; szLine != NULL; szLine = GetLineFromBuffer(ptmp)) { + /* skip comment */ + if (IsCommentString(szLine)) + continue; + + /* DBG_871X("%s : szLine = %s , strlen(szLine) = %d\n" , __func__ , szLine , strlen(szLine));*/ + for (j = 0 ; ant_isolation_param[j].param_name != NULL ; j++) { + if (strstr(szLine , ant_isolation_param[j].param_name) != NULL) { + i = 0; + while (i < strlen(szLine)) { + if (szLine[i] != '"') + ++i; + else { + /* skip only has one " */ + if (strpbrk(szLine , "\"") == strrchr(szLine , '"')) { + DBG_871X("Fail to parse parameters , format error!\n"); + break; + } + _rtw_memset((PVOID)param_value_string , 0 , 10); + if (!ParseQualifiedString(szLine , &i , param_value_string , '"' , '"')) { + DBG_871X("Fail to parse parameters\n"); + return _FAIL; + } else if (!GetU1ByteIntegerFromStringInDecimal(param_value_string , ant_isolation_param[j].value)) + DBG_871X("Fail to GetU1ByteIntegerFromStringInDecimal\n"); + + break; + } + } + } + } + } + + /* YiWei 20140716 , for BT coex antenna isolation control */ + /* rfe_type = 0 was SPDT , rfe_type = 1 was coupler */ + if (ant_num == 3 && ant_distance >= 50) + anttype = 3; + else if (ant_num == 2 && ant_distance >= 50 && rfe_type == 1) + anttype = 2; + else if (ant_num == 3 && ant_distance >= 15 && ant_distance < 50) + anttype = 2; + else if (ant_num == 2 && ant_distance >= 15 && ant_distance < 50 && rfe_type == 1) + anttype = 2; + else if ((ant_num == 2 && ant_distance < 15 && rfe_type == 1) || (ant_num == 3 && ant_distance < 15)) + anttype = 1; + else if (ant_num == 2 && rfe_type == 0) + anttype = 0; + else + anttype = 0; + + hal_btcoex_SetAntIsolationType(Adapter, anttype); + + DBG_871X("%s : ant_num = %d\n" , __func__ , ant_num); + DBG_871X("%s : ant_distance = %d\n" , __func__ , ant_distance); + DBG_871X("%s : rfe_type = %d\n" , __func__ , rfe_type); + /* DBG_871X("<===Hal_ParseAntIsolationConfigFile()\n"); */ + return rtStatus; +} + + +int +hal_btcoex_AntIsolationConfig_ParaFile( + IN PADAPTER Adapter, + IN char* pFileName +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + int rlen = 0 , rtStatus = _FAIL; + + _rtw_memset(pHalData->para_file_buf , 0 , MAX_PARA_FILE_BUF_LEN); + + rtw_get_phy_file_path(Adapter, pFileName); + if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) + { + rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN); + if (rlen > 0) + { + rtStatus = _SUCCESS; + } + } + + + if (rtStatus == _SUCCESS) { + /*DBG_871X("%s(): read %s ok\n", __func__ , pFileName);*/ + rtStatus = hal_btcoex_ParseAntIsolationConfigFile(Adapter , pHalData->para_file_buf); + } else { + DBG_871X("%s(): No File %s, Load from *** Array!\n" , __func__ , pFileName); + } + + return rtStatus; +} +#endif // CONFIG_LOAD_PHY_PARA_FROM_FILE + +u16 hal_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data) +{ + u16 ret = 0; + + halbtcoutsrc_LeaveLowPower(&GLBtCoexist); + + ret = halbtcoutsrc_GetBtReg(&GLBtCoexist, type, addr, data); + + halbtcoutsrc_NormalLowPower(&GLBtCoexist); + + return ret; +} + +u16 hal_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val) +{ + u16 ret = 0; + + halbtcoutsrc_LeaveLowPower(&GLBtCoexist); + + ret = halbtcoutsrc_SetBtReg(&GLBtCoexist, type, addr, val); + + halbtcoutsrc_NormalLowPower(&GLBtCoexist); + + return ret; +} +#endif // CONFIG_BT_COEXIST + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_com.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_com.c new file mode 100644 index 000000000..ea4d095c0 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_com.c @@ -0,0 +1,4842 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _HAL_COM_C_ + +#include +#include "hal_com_h2c.h" + +#include "hal_data.h" + +//#define CONFIG_GTK_OL_DBG + +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE +char rtw_phy_para_file_path[PATH_LENGTH_MAX]; +#endif + +void dump_chip_info(HAL_VERSION ChipVersion) +{ + int cnt = 0; + u8 buf[128]={0}; + + if (IS_8188E(ChipVersion)) + cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8188E_"); + else if (IS_8188F(ChipVersion)) + cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8188F_"); + else if (IS_8812_SERIES(ChipVersion)) + cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8812_"); + else if (IS_8192E(ChipVersion)) + cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8192E_"); + else if (IS_8821_SERIES(ChipVersion)) + cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8821_"); + else if (IS_8723B_SERIES(ChipVersion)) + cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8723B_"); + else if (IS_8703B_SERIES(ChipVersion)) + cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8703B_"); + else if (IS_8814A_SERIES(ChipVersion)) + cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8814A_"); + else + cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_UNKNOWN_"); + + cnt += sprintf((buf+cnt), "%s_", IS_NORMAL_CHIP(ChipVersion)?"Normal_Chip":"Test_Chip"); + if(IS_CHIP_VENDOR_TSMC(ChipVersion)) + cnt += sprintf((buf+cnt), "%s_","TSMC"); + else if(IS_CHIP_VENDOR_UMC(ChipVersion)) + cnt += sprintf((buf+cnt), "%s_","UMC"); + else if(IS_CHIP_VENDOR_SMIC(ChipVersion)) + cnt += sprintf((buf+cnt), "%s_","SMIC"); + + if (IS_A_CUT(ChipVersion)) + cnt += sprintf((buf+cnt), "A_CUT_"); + else if (IS_B_CUT(ChipVersion)) + cnt += sprintf((buf+cnt), "B_CUT_"); + else if (IS_C_CUT(ChipVersion)) + cnt += sprintf((buf+cnt), "C_CUT_"); + else if (IS_D_CUT(ChipVersion)) + cnt += sprintf((buf+cnt), "D_CUT_"); + else if (IS_E_CUT(ChipVersion)) + cnt += sprintf((buf+cnt), "E_CUT_"); + else if (IS_F_CUT(ChipVersion)) + cnt += sprintf((buf+cnt), "F_CUT_"); + else if (IS_I_CUT(ChipVersion)) + cnt += sprintf((buf+cnt), "I_CUT_"); + else if (IS_J_CUT(ChipVersion)) + cnt += sprintf((buf+cnt), "J_CUT_"); + else if (IS_K_CUT(ChipVersion)) + cnt += sprintf((buf+cnt), "K_CUT_"); + else + cnt += sprintf((buf+cnt), "UNKNOWN_CUT(%d)_", ChipVersion.CUTVersion); + + if(IS_1T1R(ChipVersion)) cnt += sprintf((buf+cnt), "1T1R_"); + else if(IS_1T2R(ChipVersion)) cnt += sprintf((buf+cnt), "1T2R_"); + else if(IS_2T2R(ChipVersion)) cnt += sprintf((buf+cnt), "2T2R_"); + else if(IS_3T3R(ChipVersion)) cnt += sprintf((buf+cnt), "3T3R_"); + else if(IS_3T4R(ChipVersion)) cnt += sprintf((buf+cnt), "3T4R_"); + else if(IS_4T4R(ChipVersion)) cnt += sprintf((buf+cnt), "4T4R_"); + else cnt += sprintf((buf+cnt), "UNKNOWN_RFTYPE(%d)_", ChipVersion.RFType); + + cnt += sprintf((buf+cnt), "RomVer(%d)\n", ChipVersion.ROMVer); + + DBG_871X("%s", buf); +} +void rtw_hal_config_rftype(PADAPTER padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + if (IS_1T1R(pHalData->VersionID)) { + pHalData->rf_type = RF_1T1R; + pHalData->NumTotalRFPath = 1; + } + else if (IS_2T2R(pHalData->VersionID)) { + pHalData->rf_type = RF_2T2R; + pHalData->NumTotalRFPath = 2; + } + else if (IS_1T2R(pHalData->VersionID)) { + pHalData->rf_type = RF_1T2R; + pHalData->NumTotalRFPath = 2; + } + else if(IS_3T3R(pHalData->VersionID)) { + pHalData->rf_type = RF_3T3R; + pHalData->NumTotalRFPath = 3; + } + else if(IS_4T4R(pHalData->VersionID)) { + pHalData->rf_type = RF_4T4R; + pHalData->NumTotalRFPath = 4; + } + else { + pHalData->rf_type = RF_1T1R; + pHalData->NumTotalRFPath = 1; + } + + DBG_871X("%s RF_Type is %d TotalTxPath is %d \n", __FUNCTION__, pHalData->rf_type, pHalData->NumTotalRFPath); +} + +#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 + +/* + * Description: + * Use hardware(efuse), driver parameter(registry) and default channel plan + * to decide which one should be used. + * + * Parameters: + * padapter pointer of adapter + * hw_alpha2 country code from HW (efuse/eeprom/mapfile) + * hw_chplan channel plan from HW (efuse/eeprom/mapfile) + * BIT[7] software configure mode; 0:Enable, 1:disable + * BIT[6:0] Channel Plan + * sw_alpha2 country code from HW (registry/module param) + * sw_chplan channel plan from SW (registry/module param) + * def_chplan channel plan used when HW/SW both invalid + * AutoLoadFail efuse autoload fail or not + * + * Return: + * Final channel plan decision + * + */ +u8 hal_com_config_channel_plan( + IN PADAPTER padapter, + IN char *hw_alpha2, + IN u8 hw_chplan, + IN char *sw_alpha2, + IN u8 sw_chplan, + IN u8 def_chplan, + IN BOOLEAN AutoLoadFail + ) +{ + PHAL_DATA_TYPE pHalData; + u8 force_hw_chplan = _FALSE; + int chplan = -1; + const struct country_chplan *country_ent = NULL, *ent; + + pHalData = GET_HAL_DATA(padapter); + + /* treat 0xFF as invalid value, bypass hw_chplan & force_hw_chplan parsing */ + if (hw_chplan == 0xFF) + goto chk_hw_country_code; + + if (AutoLoadFail == _TRUE) + goto chk_sw_config; + + #ifndef CONFIG_FORCE_SW_CHANNEL_PLAN + if (hw_chplan & EEPROM_CHANNEL_PLAN_BY_HW_MASK) + force_hw_chplan = _TRUE; + #endif + + hw_chplan &= (~EEPROM_CHANNEL_PLAN_BY_HW_MASK); + +chk_hw_country_code: + if (hw_alpha2 && !IS_ALPHA2_NO_SPECIFIED(hw_alpha2)) { + ent = rtw_get_chplan_from_country(hw_alpha2); + if (ent) { + /* get chplan from hw country code, by pass hw chplan setting */ + country_ent = ent; + chplan = ent->chplan; + goto chk_sw_config; + } else + DBG_871X_LEVEL(_drv_always_, "%s unsupported hw_alpha2:\"%c%c\"\n", __func__, hw_alpha2[0], hw_alpha2[1]); + } + + if (rtw_is_channel_plan_valid(hw_chplan)) + chplan = hw_chplan; + else if (force_hw_chplan == _TRUE) { + DBG_871X_LEVEL(_drv_always_, "%s unsupported hw_chplan:0x%02X\n", __func__, hw_chplan); + /* hw infomaton invalid, refer to sw information */ + force_hw_chplan = _FALSE; + } + +chk_sw_config: + if (force_hw_chplan == _TRUE) + goto done; + + if (sw_alpha2 && !IS_ALPHA2_NO_SPECIFIED(sw_alpha2)) { + ent = rtw_get_chplan_from_country(sw_alpha2); + if (ent) { + /* get chplan from sw country code, by pass sw chplan setting */ + country_ent = ent; + chplan = ent->chplan; + goto done; + } else + DBG_871X_LEVEL(_drv_always_, "%s unsupported sw_alpha2:\"%c%c\"\n", __func__, sw_alpha2[0], sw_alpha2[1]); + } + + if (rtw_is_channel_plan_valid(sw_chplan)) { + /* cancel hw_alpha2 because chplan is specified by sw_chplan*/ + country_ent = NULL; + chplan = sw_chplan; + } else if (sw_chplan != RTW_CHPLAN_MAX) + DBG_871X_LEVEL(_drv_always_, "%s unsupported sw_chplan:0x%02X\n", __func__, sw_chplan); + +done: + if (chplan == -1) { + DBG_871X_LEVEL(_drv_always_, "%s use def_chplan:0x%02X\n", __func__, def_chplan); + chplan = def_chplan; + } else if (country_ent) { + DBG_871X_LEVEL(_drv_always_, "%s country code:\"%c%c\" with chplan:0x%02X\n", __func__ + , country_ent->alpha2[0], country_ent->alpha2[1], country_ent->chplan); + } else + DBG_871X_LEVEL(_drv_always_, "%s chplan:0x%02X\n", __func__, chplan); + + padapter->mlmepriv.country_ent = country_ent; + pHalData->bDisableSWChannelPlan = force_hw_chplan; + + return chplan; +} + +BOOLEAN +HAL_IsLegalChannel( + IN PADAPTER Adapter, + IN u32 Channel + ) +{ + BOOLEAN bLegalChannel = _TRUE; + + if (Channel > 14) { + if(IsSupported5G(Adapter->registrypriv.wireless_mode) == _FALSE) { + bLegalChannel = _FALSE; + DBG_871X("Channel > 14 but wireless_mode do not support 5G\n"); + } + } else if ((Channel <= 14) && (Channel >=1)){ + if(IsSupported24G(Adapter->registrypriv.wireless_mode) == _FALSE) { + bLegalChannel = _FALSE; + DBG_871X("(Channel <= 14) && (Channel >=1) but wireless_mode do not support 2.4G\n"); + } + } else { + bLegalChannel = _FALSE; + DBG_871X("Channel is Invalid !!!\n"); + } + + return bLegalChannel; +} + +u8 MRateToHwRate(u8 rate) +{ + u8 ret = DESC_RATE1M; + + switch(rate) + { + case MGN_1M: ret = DESC_RATE1M; break; + case MGN_2M: ret = DESC_RATE2M; break; + case MGN_5_5M: ret = DESC_RATE5_5M; break; + case MGN_11M: ret = DESC_RATE11M; break; + case MGN_6M: ret = DESC_RATE6M; break; + case MGN_9M: ret = DESC_RATE9M; break; + case MGN_12M: ret = DESC_RATE12M; break; + case MGN_18M: ret = DESC_RATE18M; break; + case MGN_24M: ret = DESC_RATE24M; break; + case MGN_36M: ret = DESC_RATE36M; break; + case MGN_48M: ret = DESC_RATE48M; break; + case MGN_54M: ret = DESC_RATE54M; break; + + case MGN_MCS0: ret = DESC_RATEMCS0; break; + case MGN_MCS1: ret = DESC_RATEMCS1; break; + case MGN_MCS2: ret = DESC_RATEMCS2; break; + case MGN_MCS3: ret = DESC_RATEMCS3; break; + case MGN_MCS4: ret = DESC_RATEMCS4; break; + case MGN_MCS5: ret = DESC_RATEMCS5; break; + case MGN_MCS6: ret = DESC_RATEMCS6; break; + case MGN_MCS7: ret = DESC_RATEMCS7; break; + case MGN_MCS8: ret = DESC_RATEMCS8; break; + case MGN_MCS9: ret = DESC_RATEMCS9; break; + case MGN_MCS10: ret = DESC_RATEMCS10; break; + case MGN_MCS11: ret = DESC_RATEMCS11; break; + case MGN_MCS12: ret = DESC_RATEMCS12; break; + case MGN_MCS13: ret = DESC_RATEMCS13; break; + case MGN_MCS14: ret = DESC_RATEMCS14; break; + case MGN_MCS15: ret = DESC_RATEMCS15; break; + case MGN_MCS16: ret = DESC_RATEMCS16; break; + case MGN_MCS17: ret = DESC_RATEMCS17; break; + case MGN_MCS18: ret = DESC_RATEMCS18; break; + case MGN_MCS19: ret = DESC_RATEMCS19; break; + case MGN_MCS20: ret = DESC_RATEMCS20; break; + case MGN_MCS21: ret = DESC_RATEMCS21; break; + case MGN_MCS22: ret = DESC_RATEMCS22; break; + case MGN_MCS23: ret = DESC_RATEMCS23; break; + case MGN_MCS24: ret = DESC_RATEMCS24; break; + case MGN_MCS25: ret = DESC_RATEMCS25; break; + case MGN_MCS26: ret = DESC_RATEMCS26; break; + case MGN_MCS27: ret = DESC_RATEMCS27; break; + case MGN_MCS28: ret = DESC_RATEMCS28; break; + case MGN_MCS29: ret = DESC_RATEMCS29; break; + case MGN_MCS30: ret = DESC_RATEMCS30; break; + case MGN_MCS31: ret = DESC_RATEMCS31; break; + + case MGN_VHT1SS_MCS0: ret = DESC_RATEVHTSS1MCS0; break; + case MGN_VHT1SS_MCS1: ret = DESC_RATEVHTSS1MCS1; break; + case MGN_VHT1SS_MCS2: ret = DESC_RATEVHTSS1MCS2; break; + case MGN_VHT1SS_MCS3: ret = DESC_RATEVHTSS1MCS3; break; + case MGN_VHT1SS_MCS4: ret = DESC_RATEVHTSS1MCS4; break; + case MGN_VHT1SS_MCS5: ret = DESC_RATEVHTSS1MCS5; break; + case MGN_VHT1SS_MCS6: ret = DESC_RATEVHTSS1MCS6; break; + case MGN_VHT1SS_MCS7: ret = DESC_RATEVHTSS1MCS7; break; + case MGN_VHT1SS_MCS8: ret = DESC_RATEVHTSS1MCS8; break; + case MGN_VHT1SS_MCS9: ret = DESC_RATEVHTSS1MCS9; break; + case MGN_VHT2SS_MCS0: ret = DESC_RATEVHTSS2MCS0; break; + case MGN_VHT2SS_MCS1: ret = DESC_RATEVHTSS2MCS1; break; + case MGN_VHT2SS_MCS2: ret = DESC_RATEVHTSS2MCS2; break; + case MGN_VHT2SS_MCS3: ret = DESC_RATEVHTSS2MCS3; break; + case MGN_VHT2SS_MCS4: ret = DESC_RATEVHTSS2MCS4; break; + case MGN_VHT2SS_MCS5: ret = DESC_RATEVHTSS2MCS5; break; + case MGN_VHT2SS_MCS6: ret = DESC_RATEVHTSS2MCS6; break; + case MGN_VHT2SS_MCS7: ret = DESC_RATEVHTSS2MCS7; break; + case MGN_VHT2SS_MCS8: ret = DESC_RATEVHTSS2MCS8; break; + case MGN_VHT2SS_MCS9: ret = DESC_RATEVHTSS2MCS9; break; + case MGN_VHT3SS_MCS0: ret = DESC_RATEVHTSS3MCS0; break; + case MGN_VHT3SS_MCS1: ret = DESC_RATEVHTSS3MCS1; break; + case MGN_VHT3SS_MCS2: ret = DESC_RATEVHTSS3MCS2; break; + case MGN_VHT3SS_MCS3: ret = DESC_RATEVHTSS3MCS3; break; + case MGN_VHT3SS_MCS4: ret = DESC_RATEVHTSS3MCS4; break; + case MGN_VHT3SS_MCS5: ret = DESC_RATEVHTSS3MCS5; break; + case MGN_VHT3SS_MCS6: ret = DESC_RATEVHTSS3MCS6; break; + case MGN_VHT3SS_MCS7: ret = DESC_RATEVHTSS3MCS7; break; + case MGN_VHT3SS_MCS8: ret = DESC_RATEVHTSS3MCS8; break; + case MGN_VHT3SS_MCS9: ret = DESC_RATEVHTSS3MCS9; break; + case MGN_VHT4SS_MCS0: ret = DESC_RATEVHTSS4MCS0; break; + case MGN_VHT4SS_MCS1: ret = DESC_RATEVHTSS4MCS1; break; + case MGN_VHT4SS_MCS2: ret = DESC_RATEVHTSS4MCS2; break; + case MGN_VHT4SS_MCS3: ret = DESC_RATEVHTSS4MCS3; break; + case MGN_VHT4SS_MCS4: ret = DESC_RATEVHTSS4MCS4; break; + case MGN_VHT4SS_MCS5: ret = DESC_RATEVHTSS4MCS5; break; + case MGN_VHT4SS_MCS6: ret = DESC_RATEVHTSS4MCS6; break; + case MGN_VHT4SS_MCS7: ret = DESC_RATEVHTSS4MCS7; break; + case MGN_VHT4SS_MCS8: ret = DESC_RATEVHTSS4MCS8; break; + case MGN_VHT4SS_MCS9: ret = DESC_RATEVHTSS4MCS9; break; + default: break; + } + + return ret; +} + +u8 HwRateToMRate(u8 rate) +{ + u8 ret_rate = MGN_1M; + + switch(rate) + { + + case DESC_RATE1M: ret_rate = MGN_1M; break; + case DESC_RATE2M: ret_rate = MGN_2M; break; + case DESC_RATE5_5M: ret_rate = MGN_5_5M; break; + case DESC_RATE11M: ret_rate = MGN_11M; break; + case DESC_RATE6M: ret_rate = MGN_6M; break; + case DESC_RATE9M: ret_rate = MGN_9M; break; + case DESC_RATE12M: ret_rate = MGN_12M; break; + case DESC_RATE18M: ret_rate = MGN_18M; break; + case DESC_RATE24M: ret_rate = MGN_24M; break; + case DESC_RATE36M: ret_rate = MGN_36M; break; + case DESC_RATE48M: ret_rate = MGN_48M; break; + case DESC_RATE54M: ret_rate = MGN_54M; break; + case DESC_RATEMCS0: ret_rate = MGN_MCS0; break; + case DESC_RATEMCS1: ret_rate = MGN_MCS1; break; + case DESC_RATEMCS2: ret_rate = MGN_MCS2; break; + case DESC_RATEMCS3: ret_rate = MGN_MCS3; break; + case DESC_RATEMCS4: ret_rate = MGN_MCS4; break; + case DESC_RATEMCS5: ret_rate = MGN_MCS5; break; + case DESC_RATEMCS6: ret_rate = MGN_MCS6; break; + case DESC_RATEMCS7: ret_rate = MGN_MCS7; break; + case DESC_RATEMCS8: ret_rate = MGN_MCS8; break; + case DESC_RATEMCS9: ret_rate = MGN_MCS9; break; + case DESC_RATEMCS10: ret_rate = MGN_MCS10; break; + case DESC_RATEMCS11: ret_rate = MGN_MCS11; break; + case DESC_RATEMCS12: ret_rate = MGN_MCS12; break; + case DESC_RATEMCS13: ret_rate = MGN_MCS13; break; + case DESC_RATEMCS14: ret_rate = MGN_MCS14; break; + case DESC_RATEMCS15: ret_rate = MGN_MCS15; break; + case DESC_RATEMCS16: ret_rate = MGN_MCS16; break; + case DESC_RATEMCS17: ret_rate = MGN_MCS17; break; + case DESC_RATEMCS18: ret_rate = MGN_MCS18; break; + case DESC_RATEMCS19: ret_rate = MGN_MCS19; break; + case DESC_RATEMCS20: ret_rate = MGN_MCS20; break; + case DESC_RATEMCS21: ret_rate = MGN_MCS21; break; + case DESC_RATEMCS22: ret_rate = MGN_MCS22; break; + case DESC_RATEMCS23: ret_rate = MGN_MCS23; break; + case DESC_RATEMCS24: ret_rate = MGN_MCS24; break; + case DESC_RATEMCS25: ret_rate = MGN_MCS25; break; + case DESC_RATEMCS26: ret_rate = MGN_MCS26; break; + case DESC_RATEMCS27: ret_rate = MGN_MCS27; break; + case DESC_RATEMCS28: ret_rate = MGN_MCS28; break; + case DESC_RATEMCS29: ret_rate = MGN_MCS29; break; + case DESC_RATEMCS30: ret_rate = MGN_MCS30; break; + case DESC_RATEMCS31: ret_rate = MGN_MCS31; break; + case DESC_RATEVHTSS1MCS0: ret_rate = MGN_VHT1SS_MCS0; break; + case DESC_RATEVHTSS1MCS1: ret_rate = MGN_VHT1SS_MCS1; break; + case DESC_RATEVHTSS1MCS2: ret_rate = MGN_VHT1SS_MCS2; break; + case DESC_RATEVHTSS1MCS3: ret_rate = MGN_VHT1SS_MCS3; break; + case DESC_RATEVHTSS1MCS4: ret_rate = MGN_VHT1SS_MCS4; break; + case DESC_RATEVHTSS1MCS5: ret_rate = MGN_VHT1SS_MCS5; break; + case DESC_RATEVHTSS1MCS6: ret_rate = MGN_VHT1SS_MCS6; break; + case DESC_RATEVHTSS1MCS7: ret_rate = MGN_VHT1SS_MCS7; break; + case DESC_RATEVHTSS1MCS8: ret_rate = MGN_VHT1SS_MCS8; break; + case DESC_RATEVHTSS1MCS9: ret_rate = MGN_VHT1SS_MCS9; break; + case DESC_RATEVHTSS2MCS0: ret_rate = MGN_VHT2SS_MCS0; break; + case DESC_RATEVHTSS2MCS1: ret_rate = MGN_VHT2SS_MCS1; break; + case DESC_RATEVHTSS2MCS2: ret_rate = MGN_VHT2SS_MCS2; break; + case DESC_RATEVHTSS2MCS3: ret_rate = MGN_VHT2SS_MCS3; break; + case DESC_RATEVHTSS2MCS4: ret_rate = MGN_VHT2SS_MCS4; break; + case DESC_RATEVHTSS2MCS5: ret_rate = MGN_VHT2SS_MCS5; break; + case DESC_RATEVHTSS2MCS6: ret_rate = MGN_VHT2SS_MCS6; break; + case DESC_RATEVHTSS2MCS7: ret_rate = MGN_VHT2SS_MCS7; break; + case DESC_RATEVHTSS2MCS8: ret_rate = MGN_VHT2SS_MCS8; break; + case DESC_RATEVHTSS2MCS9: ret_rate = MGN_VHT2SS_MCS9; break; + case DESC_RATEVHTSS3MCS0: ret_rate = MGN_VHT3SS_MCS0; break; + case DESC_RATEVHTSS3MCS1: ret_rate = MGN_VHT3SS_MCS1; break; + case DESC_RATEVHTSS3MCS2: ret_rate = MGN_VHT3SS_MCS2; break; + case DESC_RATEVHTSS3MCS3: ret_rate = MGN_VHT3SS_MCS3; break; + case DESC_RATEVHTSS3MCS4: ret_rate = MGN_VHT3SS_MCS4; break; + case DESC_RATEVHTSS3MCS5: ret_rate = MGN_VHT3SS_MCS5; break; + case DESC_RATEVHTSS3MCS6: ret_rate = MGN_VHT3SS_MCS6; break; + case DESC_RATEVHTSS3MCS7: ret_rate = MGN_VHT3SS_MCS7; break; + case DESC_RATEVHTSS3MCS8: ret_rate = MGN_VHT3SS_MCS8; break; + case DESC_RATEVHTSS3MCS9: ret_rate = MGN_VHT3SS_MCS9; break; + case DESC_RATEVHTSS4MCS0: ret_rate = MGN_VHT4SS_MCS0; break; + case DESC_RATEVHTSS4MCS1: ret_rate = MGN_VHT4SS_MCS1; break; + case DESC_RATEVHTSS4MCS2: ret_rate = MGN_VHT4SS_MCS2; break; + case DESC_RATEVHTSS4MCS3: ret_rate = MGN_VHT4SS_MCS3; break; + case DESC_RATEVHTSS4MCS4: ret_rate = MGN_VHT4SS_MCS4; break; + case DESC_RATEVHTSS4MCS5: ret_rate = MGN_VHT4SS_MCS5; break; + case DESC_RATEVHTSS4MCS6: ret_rate = MGN_VHT4SS_MCS6; break; + case DESC_RATEVHTSS4MCS7: ret_rate = MGN_VHT4SS_MCS7; break; + case DESC_RATEVHTSS4MCS8: ret_rate = MGN_VHT4SS_MCS8; break; + case DESC_RATEVHTSS4MCS9: ret_rate = MGN_VHT4SS_MCS9; break; + + default: + DBG_871X("HwRateToMRate(): Non supported Rate [%x]!!!\n",rate ); + break; + } + + return ret_rate; +} + +void HalSetBrateCfg( + IN PADAPTER Adapter, + IN u8 *mBratesOS, + OUT u16 *pBrateCfg) +{ + u8 i, is_brate, brate; + + for(i=0;iQueue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO + pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];//VI + pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[0];//BE + pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];//BK + + pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN + pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT + pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH + pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD +} + +static VOID +_TwoOutPipeMapping( + IN PADAPTER pAdapter, + IN BOOLEAN bWIFICfg + ) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter); + + if(bWIFICfg){ //WMM + + // BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA + //{ 0, 1, 0, 1, 0, 0, 0, 0, 0 }; + //0:ep_0 num, 1:ep_1 num + + pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1];//VO + pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];//VI + pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];//BE + pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];//BK + + pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN + pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT + pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH + pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD + + } + else{//typical setting + + + //BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA + //{ 1, 1, 0, 0, 0, 0, 0, 0, 0 }; + //0:ep_0 num, 1:ep_1 num + + pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO + pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];//VI + pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];//BE + pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];//BK + + pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN + pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT + pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH + pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD + + } + +} + +static VOID _ThreeOutPipeMapping( + IN PADAPTER pAdapter, + IN BOOLEAN bWIFICfg + ) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter); + + if(bWIFICfg){//for WMM + + // BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA + //{ 1, 2, 1, 0, 0, 0, 0, 0, 0 }; + //0:H, 1:N, 2:L + + pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO + pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];//VI + pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];//BE + pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];//BK + + pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN + pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT + pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH + pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD + + } + else{//typical setting + + + // BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA + //{ 2, 2, 1, 0, 0, 0, 0, 0, 0 }; + //0:H, 1:N, 2:L + + pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO + pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];//VI + pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];//BE + pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];//BK + + pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN + pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT + pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];//HIGH + pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD + } + +} +static VOID _FourOutPipeMapping( + IN PADAPTER pAdapter, + IN BOOLEAN bWIFICfg + ) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(pAdapter); + + if(bWIFICfg){//for WMM + + // BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA + //{ 1, 2, 1, 0, 0, 0, 0, 0, 0 }; + //0:H, 1:N, 2:L ,3:E + + pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO + pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];//VI + pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];//BE + pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];//BK + + pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN + pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT + pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[3];//HIGH + pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD + + } + else{//typical setting + + + // BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA + //{ 2, 2, 1, 0, 0, 0, 0, 0, 0 }; + //0:H, 1:N, 2:L + + pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];//VO + pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];//VI + pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];//BE + pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];//BK + + pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];//BCN + pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];//MGT + pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[3];//HIGH + pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];//TXCMD + } + +} +BOOLEAN +Hal_MappingOutPipe( + IN PADAPTER pAdapter, + IN u8 NumOutPipe + ) +{ + struct registry_priv *pregistrypriv = &pAdapter->registrypriv; + + BOOLEAN bWIFICfg = (pregistrypriv->wifi_spec) ?_TRUE:_FALSE; + + BOOLEAN result = _TRUE; + + switch(NumOutPipe) + { + case 2: + _TwoOutPipeMapping(pAdapter, bWIFICfg); + break; + case 3: + case 4: + _ThreeOutPipeMapping(pAdapter, bWIFICfg); + break; + case 1: + _OneOutPipeMapping(pAdapter); + break; + default: + result = _FALSE; + break; + } + + return result; + +} + +void hal_init_macaddr(_adapter *adapter) +{ + rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, adapter_mac_addr(adapter)); +#ifdef CONFIG_CONCURRENT_MODE + if (adapter->pbuddy_adapter) + rtw_hal_set_hwreg(adapter->pbuddy_adapter, HW_VAR_MAC_ADDR, adapter_mac_addr(adapter->pbuddy_adapter)); +#endif +} + +void rtw_init_hal_com_default_value(PADAPTER Adapter) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + + pHalData->AntDetection = 1; +} + +/* +* C2H event format: +* Field TRIGGER CONTENT CMD_SEQ CMD_LEN CMD_ID +* BITS [127:120] [119:16] [15:8] [7:4] [3:0] +*/ + +void c2h_evt_clear(_adapter *adapter) +{ + rtw_write8(adapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE); +} + +s32 c2h_evt_read(_adapter *adapter, u8 *buf) +{ + s32 ret = _FAIL; + struct c2h_evt_hdr *c2h_evt; + int i; + u8 trigger; + + if (buf == NULL) + goto exit; + +#if defined (CONFIG_RTL8188E) + + trigger = rtw_read8(adapter, REG_C2HEVT_CLEAR); + + if (trigger == C2H_EVT_HOST_CLOSE) { + goto exit; /* Not ready */ + } else if (trigger != C2H_EVT_FW_CLOSE) { + goto clear_evt; /* Not a valid value */ + } + + c2h_evt = (struct c2h_evt_hdr *)buf; + + _rtw_memset(c2h_evt, 0, 16); + + *buf = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL); + *(buf+1) = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 1); + + RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "c2h_evt_read(): ", + &c2h_evt , sizeof(c2h_evt)); + + if (0) { + DBG_871X("%s id:%u, len:%u, seq:%u, trigger:0x%02x\n", __func__ + , c2h_evt->id, c2h_evt->plen, c2h_evt->seq, trigger); + } + + /* Read the content */ + for (i = 0; i < c2h_evt->plen; i++) + c2h_evt->payload[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i); + + RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "c2h_evt_read(): Command Content:\n", + c2h_evt->payload, c2h_evt->plen); + + ret = _SUCCESS; + +clear_evt: + /* + * Clear event to notify FW we have read the command. + * If this field isn't clear, the FW won't update the next command message. + */ + c2h_evt_clear(adapter); +#endif +exit: + return ret; +} + +/* +* C2H event format: +* Field TRIGGER CMD_LEN CONTENT CMD_SEQ CMD_ID +* BITS [127:120] [119:112] [111:16] [15:8] [7:0] +*/ +s32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf) +{ + s32 ret = _FAIL; + struct c2h_evt_hdr_88xx *c2h_evt; + int i; + u8 trigger; + + if (buf == NULL) + goto exit; + +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) + + trigger = rtw_read8(adapter, REG_C2HEVT_CLEAR); + + if (trigger == C2H_EVT_HOST_CLOSE) { + goto exit; /* Not ready */ + } else if (trigger != C2H_EVT_FW_CLOSE) { + goto clear_evt; /* Not a valid value */ + } + + c2h_evt = (struct c2h_evt_hdr_88xx *)buf; + + _rtw_memset(c2h_evt, 0, 16); + + c2h_evt->id = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL); + c2h_evt->seq = rtw_read8(adapter, REG_C2HEVT_CMD_SEQ_88XX); + c2h_evt->plen = rtw_read8(adapter, REG_C2HEVT_CMD_LEN_88XX); + + RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "c2h_evt_read(): ", + &c2h_evt , sizeof(c2h_evt)); + + if (0) { + DBG_871X("%s id:%u, len:%u, seq:%u, trigger:0x%02x\n", __func__ + , c2h_evt->id, c2h_evt->plen, c2h_evt->seq, trigger); + } + + /* Read the content */ + for (i = 0; i < c2h_evt->plen; i++) + c2h_evt->payload[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i); + + RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "c2h_evt_read(): Command Content:\n", + c2h_evt->payload, c2h_evt->plen); + + ret = _SUCCESS; + +clear_evt: + /* + * Clear event to notify FW we have read the command. + * If this field isn't clear, the FW won't update the next command message. + */ + c2h_evt_clear(adapter); +#endif +exit: + return ret; +} + +#define GET_C2H_MAC_HIDDEN_RPT_UUID_X(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 0, 0, 8) +#define GET_C2H_MAC_HIDDEN_RPT_UUID_Y(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 1, 0, 8) +#define GET_C2H_MAC_HIDDEN_RPT_UUID_Z(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 2, 0, 5) +#define GET_C2H_MAC_HIDDEN_RPT_UUID_CRC(_data) LE_BITS_TO_2BYTE(((u8 *)(_data)) + 2, 5, 11) +#define GET_C2H_MAC_HIDDEN_RPT_HCI_TYPE(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 0, 4) +#define GET_C2H_MAC_HIDDEN_RPT_PACKAGE_TYPE(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 4, 3) +#define GET_C2H_MAC_HIDDEN_RPT_TR_SWITCH(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 4, 7, 1) +#define GET_C2H_MAC_HIDDEN_RPT_WL_FUNC(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 5, 0, 4) +#define GET_C2H_MAC_HIDDEN_RPT_HW_STYPE(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 5, 4, 4) +#define GET_C2H_MAC_HIDDEN_RPT_BW(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 0, 3) +#define GET_C2H_MAC_HIDDEN_RPT_FAB(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 3, 2) +#define GET_C2H_MAC_HIDDEN_RPT_ANT_NUM(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 6, 5, 3) +#define GET_C2H_MAC_HIDDEN_RPT_80211_PROTOCOL(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 2, 2) +#define GET_C2H_MAC_HIDDEN_RPT_NIC_ROUTER(_data) LE_BITS_TO_1BYTE(((u8 *)(_data)) + 7, 6, 2) + +#ifndef DBG_C2H_MAC_HIDDEN_RPT_HANDLE +#define DBG_C2H_MAC_HIDDEN_RPT_HANDLE 0 +#endif + +int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + int ret = _FAIL; + + u32 uuid; + u8 uuid_x; + u8 uuid_y; + u8 uuid_z; + u16 uuid_crc; + + u8 hci_type; + u8 package_type; + u8 tr_switch; + u8 wl_func; + u8 hw_stype; + u8 bw; + u8 fab; + u8 ant_num; + u8 protocol; + u8 nic; + + int i; + + if (len < MAC_HIDDEN_RPT_LEN) { + DBG_871X_LEVEL(_drv_warning_, "%s len(%u) < %d\n", __func__, len, MAC_HIDDEN_RPT_LEN); + goto exit; + } + + uuid_x = GET_C2H_MAC_HIDDEN_RPT_UUID_X(data); + uuid_y = GET_C2H_MAC_HIDDEN_RPT_UUID_Y(data); + uuid_z = GET_C2H_MAC_HIDDEN_RPT_UUID_Z(data); + uuid_crc = GET_C2H_MAC_HIDDEN_RPT_UUID_CRC(data); + + hci_type = GET_C2H_MAC_HIDDEN_RPT_HCI_TYPE(data); + package_type = GET_C2H_MAC_HIDDEN_RPT_PACKAGE_TYPE(data); + + tr_switch = GET_C2H_MAC_HIDDEN_RPT_TR_SWITCH(data); + + wl_func = GET_C2H_MAC_HIDDEN_RPT_WL_FUNC(data); + hw_stype = GET_C2H_MAC_HIDDEN_RPT_HW_STYPE(data); + + bw = GET_C2H_MAC_HIDDEN_RPT_BW(data); + fab = GET_C2H_MAC_HIDDEN_RPT_FAB(data); + ant_num = GET_C2H_MAC_HIDDEN_RPT_ANT_NUM(data); + + protocol = GET_C2H_MAC_HIDDEN_RPT_80211_PROTOCOL(data); + nic = GET_C2H_MAC_HIDDEN_RPT_NIC_ROUTER(data); + + if (DBG_C2H_MAC_HIDDEN_RPT_HANDLE) { + for (i = 0; i < len; i++) + DBG_871X("%s: 0x%02X\n", __func__, *(data + i)); + + DBG_871X("uuid x:0x%02x y:0x%02x z:0x%x crc:0x%x\n", uuid_x, uuid_y, uuid_z, uuid_crc); + DBG_871X("hci_type:0x%x\n", hci_type); + DBG_871X("package_type:0x%x\n", package_type); + DBG_871X("tr_switch:0x%x\n", tr_switch); + DBG_871X("wl_func:0x%x\n", wl_func); + DBG_871X("hw_stype:0x%x\n", hw_stype); + DBG_871X("bw:0x%x\n", bw); + DBG_871X("fab:0x%x\n", fab); + DBG_871X("ant_num:0x%x\n", ant_num); + DBG_871X("protocol:0x%x\n", protocol); + DBG_871X("nic:0x%x\n", nic); + } + + /* + * NOTICE: + * for now, the following is common info/format + * if there is any hal difference need to export + * some IC dependent code will need to be implement + */ hal_data->PackageType = package_type; + hal_spec->wl_func &= mac_hidden_wl_func_to_hal_wl_func(wl_func); + hal_spec->bw_cap &= mac_hidden_max_bw_to_hal_bw_cap(bw); + hal_spec->nss_num = rtw_min(hal_spec->nss_num, ant_num); + hal_spec->proto_cap &= mac_hidden_proto_to_hal_proto_cap(protocol); + + /* TODO: tr_switch */ + /* TODO: fab */ + + ret = _SUCCESS; + +exit: + return ret; +} + +int c2h_mac_hidden_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + int ret = _FAIL; + + int i; + + if (len < MAC_HIDDEN_RPT_2_LEN) { + RTW_WARN("%s len(%u) < %d\n", __func__, len, MAC_HIDDEN_RPT_2_LEN); + goto exit; + } + + if (DBG_C2H_MAC_HIDDEN_RPT_HANDLE) { + for (i = 0; i < len; i++) + DBG_871X_LEVEL(_drv_always_, "%s: 0x%02X\n", __func__, *(data + i)); + } + + ret = _SUCCESS; + +exit: + return ret; +} + +int hal_read_mac_hidden_rpt(_adapter *adapter) +{ + int ret = _FAIL; + int ret_fwdl; + u8 mac_hidden_rpt[MAC_HIDDEN_RPT_LEN + MAC_HIDDEN_RPT_2_LEN] = {0}; + u32 start = rtw_get_current_time(); + u32 cnt = 0; + u32 timeout_ms = 800; + u32 min_cnt = 10; + u8 id = C2H_DEFEATURE_RSVD; + int i; + +#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI) + u8 hci_type = rtw_get_intf_type(adapter); + + if ((hci_type == RTW_USB || hci_type == RTW_PCIE) + && !rtw_is_hw_init_completed(adapter)) + rtw_hal_power_on(adapter); +#endif + + /* inform FW mac hidden rpt from reg is needed */ + rtw_write8(adapter, REG_C2HEVT_MSG_NORMAL, C2H_DEFEATURE_RSVD); + + /* download FW */ + ret_fwdl = rtw_hal_fw_dl(adapter, _FALSE); + if (ret_fwdl != _SUCCESS) + goto mac_hidden_rpt_hdl; + + /* polling for data ready */ + start = rtw_get_current_time(); + do { + cnt++; + id = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL); + if (id == C2H_MAC_HIDDEN_RPT || RTW_CANNOT_IO(adapter)) + break; + rtw_msleep_os(10); + } while (rtw_get_passing_time_ms(start) < timeout_ms || cnt < min_cnt); + + if (id == C2H_MAC_HIDDEN_RPT) { + /* read data */ + for (i = 0; i < MAC_HIDDEN_RPT_LEN + MAC_HIDDEN_RPT_2_LEN; i++) + mac_hidden_rpt[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i); + } + + /* inform FW mac hidden rpt has read */ + rtw_write8(adapter, REG_C2HEVT_MSG_NORMAL, C2H_DBG); + +mac_hidden_rpt_hdl: + c2h_mac_hidden_rpt_hdl(adapter, mac_hidden_rpt, MAC_HIDDEN_RPT_LEN); + c2h_mac_hidden_rpt_2_hdl(adapter, mac_hidden_rpt + MAC_HIDDEN_RPT_LEN, MAC_HIDDEN_RPT_2_LEN); + + if (ret_fwdl == _SUCCESS && id == C2H_MAC_HIDDEN_RPT) + ret = _SUCCESS; + +exit: + +#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI) + if ((hci_type == RTW_USB || hci_type == RTW_PCIE) + && !rtw_is_hw_init_completed(adapter)) + rtw_hal_power_off(adapter); +#endif + + DBG_871X("%s %s! (%u, %dms), fwdl:%d, id:0x%02x\n", __func__ + , (ret == _SUCCESS)?"OK":"Fail", cnt, rtw_get_passing_time_ms(start), ret_fwdl, id); + + return ret; +} + +int c2h_defeature_dbg_hdl(_adapter *adapter, u8 *data, u8 len) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + int ret = _FAIL; + + int i; + + if (len < DEFEATURE_DBG_LEN) { + RTW_WARN("%s len(%u) < %d\n", __func__, len, DEFEATURE_DBG_LEN); + goto exit; + } + + for (i = 0; i < len; i++) + DBG_871X_LEVEL(_drv_always_,"%s: 0x%02X\n", __func__, *(data + i)); + + ret = _SUCCESS; + +exit: + return ret; +} + + +#ifndef DBG_CUSTOMER_STR_RPT_HANDLE +#define DBG_CUSTOMER_STR_RPT_HANDLE 0 +#endif + +#ifdef CONFIG_RTW_CUSTOMER_STR +s32 rtw_hal_h2c_customer_str_req(_adapter *adapter) +{ + u8 h2c_data[H2C_CUSTOMER_STR_REQ_LEN] = {0}; + + SET_H2CCMD_CUSTOMER_STR_REQ_EN(h2c_data, 1); + return rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_REQ, H2C_CUSTOMER_STR_REQ_LEN, h2c_data); +} + +#define C2H_CUSTOMER_STR_RPT_BYTE0(_data) ((u8 *)(_data)) +#define C2H_CUSTOMER_STR_RPT_2_BYTE8(_data) ((u8 *)(_data)) + +int c2h_customer_str_rpt_hdl(_adapter *adapter, u8 *data, u8 len) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + int ret = _FAIL; + int i; + + if (len < CUSTOMER_STR_RPT_LEN) { + RTW_WARN("%s len(%u) < %d\n", __func__, len, CUSTOMER_STR_RPT_LEN); + goto exit; + } + + if (DBG_CUSTOMER_STR_RPT_HANDLE) + RTW_PRINT_DUMP("customer_str_rpt: ", data, CUSTOMER_STR_RPT_LEN); + + _enter_critical_mutex(&dvobj->customer_str_mutex, NULL); + + if (dvobj->customer_str_sctx != NULL) { + if (dvobj->customer_str_sctx->status != RTW_SCTX_SUBMITTED) + RTW_WARN("%s invalid sctx.status:%d\n", __func__, dvobj->customer_str_sctx->status); + _rtw_memcpy(dvobj->customer_str, C2H_CUSTOMER_STR_RPT_BYTE0(data), CUSTOMER_STR_RPT_LEN); + dvobj->customer_str_sctx->status = RTX_SCTX_CSTR_WAIT_RPT2; + } else + RTW_WARN("%s sctx not set\n", __func__); + + _exit_critical_mutex(&dvobj->customer_str_mutex, NULL); + + ret = _SUCCESS; + +exit: + return ret; +} + +int c2h_customer_str_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + int ret = _FAIL; + int i; + + if (len < CUSTOMER_STR_RPT_2_LEN) { + RTW_WARN("%s len(%u) < %d\n", __func__, len, CUSTOMER_STR_RPT_2_LEN); + goto exit; + } + + if (DBG_CUSTOMER_STR_RPT_HANDLE) + RTW_PRINT_DUMP("customer_str_rpt_2: ", data, CUSTOMER_STR_RPT_2_LEN); + + _enter_critical_mutex(&dvobj->customer_str_mutex, NULL); + + if (dvobj->customer_str_sctx != NULL) { + if (dvobj->customer_str_sctx->status != RTX_SCTX_CSTR_WAIT_RPT2) + RTW_WARN("%s rpt not ready\n", __func__); + _rtw_memcpy(dvobj->customer_str + CUSTOMER_STR_RPT_LEN, C2H_CUSTOMER_STR_RPT_2_BYTE8(data), CUSTOMER_STR_RPT_2_LEN); + rtw_sctx_done(&dvobj->customer_str_sctx); + } else + RTW_WARN("%s sctx not set\n", __func__); + + _exit_critical_mutex(&dvobj->customer_str_mutex, NULL); + + ret = _SUCCESS; + +exit: + return ret; +} + +/* read customer str */ +s32 rtw_hal_customer_str_read(_adapter *adapter, u8 *cs) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct submit_ctx sctx; + s32 ret = _SUCCESS; + + _enter_critical_mutex(&dvobj->customer_str_mutex, NULL); + if (dvobj->customer_str_sctx != NULL) + ret = _FAIL; + else { + rtw_sctx_init(&sctx, 2 * 1000); + dvobj->customer_str_sctx = &sctx; + } + _exit_critical_mutex(&dvobj->customer_str_mutex, NULL); + + if (ret == _FAIL) { + RTW_WARN("%s another handle ongoing\n", __func__); + goto exit; + } + + ret = rtw_customer_str_req_cmd(adapter); + if (ret != _SUCCESS) { + RTW_WARN("%s read cmd fail\n", __func__); + _enter_critical_mutex(&dvobj->customer_str_mutex, NULL); + dvobj->customer_str_sctx = NULL; + _exit_critical_mutex(&dvobj->customer_str_mutex, NULL); + goto exit; + } + + /* wait till rpt done or timeout */ + rtw_sctx_wait(&sctx, __func__); + + _enter_critical_mutex(&dvobj->customer_str_mutex, NULL); + dvobj->customer_str_sctx = NULL; + if (sctx.status == RTW_SCTX_DONE_SUCCESS) + _rtw_memcpy(cs, dvobj->customer_str, RTW_CUSTOMER_STR_LEN); + else + ret = _FAIL; + _exit_critical_mutex(&dvobj->customer_str_mutex, NULL); + +exit: + return ret; +} + +s32 rtw_hal_h2c_customer_str_write(_adapter *adapter, const u8 *cs) +{ + u8 h2c_data_w1[H2C_CUSTOMER_STR_W1_LEN] = {0}; + u8 h2c_data_w2[H2C_CUSTOMER_STR_W2_LEN] = {0}; + u8 h2c_data_w3[H2C_CUSTOMER_STR_W3_LEN] = {0}; + s32 ret; + + SET_H2CCMD_CUSTOMER_STR_W1_EN(h2c_data_w1, 1); + _rtw_memcpy(H2CCMD_CUSTOMER_STR_W1_BYTE0(h2c_data_w1), cs, 6); + + SET_H2CCMD_CUSTOMER_STR_W2_EN(h2c_data_w2, 1); + _rtw_memcpy(H2CCMD_CUSTOMER_STR_W2_BYTE6(h2c_data_w2), cs + 6, 6); + + SET_H2CCMD_CUSTOMER_STR_W3_EN(h2c_data_w3, 1); + _rtw_memcpy(H2CCMD_CUSTOMER_STR_W3_BYTE12(h2c_data_w3), cs + 6 + 6, 4); + + ret = rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_W1, H2C_CUSTOMER_STR_W1_LEN, h2c_data_w1); + if (ret != _SUCCESS) { + RTW_WARN("%s w1 fail\n", __func__); + goto exit; + } + + ret = rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_W2, H2C_CUSTOMER_STR_W2_LEN, h2c_data_w2); + if (ret != _SUCCESS) { + RTW_WARN("%s w2 fail\n", __func__); + goto exit; + } + + ret = rtw_hal_fill_h2c_cmd(adapter, H2C_CUSTOMER_STR_W3, H2C_CUSTOMER_STR_W3_LEN, h2c_data_w3); + if (ret != _SUCCESS) { + RTW_WARN("%s w3 fail\n", __func__); + goto exit; + } + +exit: + return ret; +} + +/* write customer str and check if value reported is the same as requested */ +s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct submit_ctx sctx; + s32 ret = _SUCCESS; + + _enter_critical_mutex(&dvobj->customer_str_mutex, NULL); + if (dvobj->customer_str_sctx != NULL) + ret = _FAIL; + else { + rtw_sctx_init(&sctx, 2 * 1000); + dvobj->customer_str_sctx = &sctx; + } + _exit_critical_mutex(&dvobj->customer_str_mutex, NULL); + + if (ret == _FAIL) { + RTW_WARN("%s another handle ongoing\n", __func__); + goto exit; + } + + ret = rtw_customer_str_write_cmd(adapter, cs); + if (ret != _SUCCESS) { + RTW_WARN("%s write cmd fail\n", __func__); + _enter_critical_mutex(&dvobj->customer_str_mutex, NULL); + dvobj->customer_str_sctx = NULL; + _exit_critical_mutex(&dvobj->customer_str_mutex, NULL); + goto exit; + } + + ret = rtw_customer_str_req_cmd(adapter); + if (ret != _SUCCESS) { + RTW_WARN("%s read cmd fail\n", __func__); + _enter_critical_mutex(&dvobj->customer_str_mutex, NULL); + dvobj->customer_str_sctx = NULL; + _exit_critical_mutex(&dvobj->customer_str_mutex, NULL); + goto exit; + } + + /* wait till rpt done or timeout */ + rtw_sctx_wait(&sctx, __func__); + + _enter_critical_mutex(&dvobj->customer_str_mutex, NULL); + dvobj->customer_str_sctx = NULL; + if (sctx.status == RTW_SCTX_DONE_SUCCESS) { + if (_rtw_memcmp(cs, dvobj->customer_str, RTW_CUSTOMER_STR_LEN) != _TRUE) { + RTW_WARN("%s read back check fail\n", __func__); + RTW_INFO_DUMP("write req: ", cs, RTW_CUSTOMER_STR_LEN); + RTW_INFO_DUMP("read back: ", dvobj->customer_str, RTW_CUSTOMER_STR_LEN); + ret = _FAIL; + } + } else + ret = _FAIL; + _exit_critical_mutex(&dvobj->customer_str_mutex, NULL); + +exit: + return ret; +} +#endif /* CONFIG_RTW_CUSTOMER_STR */ + + +u8 rtw_hal_networktype_to_raid(_adapter *adapter, struct sta_info *psta) +{ + if(IS_NEW_GENERATION_IC(adapter)){ + return networktype_to_raid_ex(adapter,psta); + } + else{ + return networktype_to_raid(adapter,psta); + } + +} +u8 rtw_get_mgntframe_raid(_adapter *adapter,unsigned char network_type) +{ + + u8 raid; + if(IS_NEW_GENERATION_IC(adapter)){ + + raid = (network_type & WIRELESS_11B) ?RATEID_IDX_B + :RATEID_IDX_G; + } + else{ + raid = (network_type & WIRELESS_11B) ?RATR_INX_WIRELESS_B + :RATR_INX_WIRELESS_G; + } + return raid; +} + +void rtw_hal_update_sta_rate_mask(PADAPTER padapter, struct sta_info *psta) +{ + u8 i, rf_type, limit; + u64 tx_ra_bitmap; + + if(psta == NULL) + { + return; + } + + tx_ra_bitmap = 0; + + //b/g mode ra_bitmap + for (i=0; ibssrateset); i++) + { + if (psta->bssrateset[i]) + tx_ra_bitmap |= rtw_get_bit_value_from_ieee_value(psta->bssrateset[i]&0x7f); + } + +#ifdef CONFIG_80211N_HT +#ifdef CONFIG_80211AC_VHT + //AC mode ra_bitmap + if(psta->vhtpriv.vht_option) + { + tx_ra_bitmap |= (rtw_vht_rate_to_bitmap(psta->vhtpriv.vht_mcs_map) << 12); + } + else +#endif //CONFIG_80211AC_VHT + { + //n mode ra_bitmap + if(psta->htpriv.ht_option) + { + rf_type = RF_1T1R; + rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + if(rf_type == RF_2T2R) + limit=16;// 2R + else if(rf_type == RF_3T3R) + limit=24;// 3R + else + limit=8;// 1R + + + /* Handling SMPS mode for AP MODE only*/ + if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) { + /*0:static SMPS, 1:dynamic SMPS, 3:SMPS disabled, 2:reserved*/ + if (psta->htpriv.smps_cap == 0 || psta->htpriv.smps_cap == 1) { + /*operate with only one active receive chain // 11n-MCS rate <= MSC7*/ + limit = 8;/* 1R*/ + } + } + + for (i=0; ihtpriv.ht_cap.supp_mcs_set[i/8] & BIT(i%8)) + tx_ra_bitmap |= BIT(i+12); + } + } + } +#endif //CONFIG_80211N_HT + DBG_871X("supp_mcs_set = %02x, %02x, %02x, rf_type=%d, tx_ra_bitmap=%016llx\n" + , psta->htpriv.ht_cap.supp_mcs_set[0], psta->htpriv.ht_cap.supp_mcs_set[1], psta->htpriv.ht_cap.supp_mcs_set[2], rf_type, tx_ra_bitmap); + psta->ra_mask = tx_ra_bitmap; + psta->init_rate = get_highest_rate_idx(tx_ra_bitmap)&0x3f; +} + +#ifndef SEC_CAM_ACCESS_TIMEOUT_MS + #define SEC_CAM_ACCESS_TIMEOUT_MS 200 +#endif + +#ifndef DBG_SEC_CAM_ACCESS + #define DBG_SEC_CAM_ACCESS 0 +#endif + +u32 rtw_sec_read_cam(_adapter *adapter, u8 addr) +{ + _mutex *mutex = &adapter_to_dvobj(adapter)->cam_ctl.sec_cam_access_mutex; + u32 rdata; + u32 cnt = 0; + u32 start = 0, end = 0; + u8 timeout = 0; + u8 sr = 0; + + _enter_critical_mutex(mutex, NULL); + + rtw_write32(adapter, REG_CAMCMD, CAM_POLLINIG | addr); + + start = rtw_get_current_time(); + while (1) { + if (rtw_is_surprise_removed(adapter)) { + sr = 1; + break; + } + + cnt++; + if (0 == (rtw_read32(adapter, REG_CAMCMD) & CAM_POLLINIG)) + break; + + if (rtw_get_passing_time_ms(start) > SEC_CAM_ACCESS_TIMEOUT_MS) { + timeout = 1; + break; + } + } + end = rtw_get_current_time(); + + rdata = rtw_read32(adapter, REG_CAMREAD); + + _exit_critical_mutex(mutex, NULL); + + if (DBG_SEC_CAM_ACCESS || timeout) { + DBG_871X(FUNC_ADPT_FMT" addr:0x%02x, rdata:0x%08x, to:%u, polling:%u, %d ms\n" + , FUNC_ADPT_ARG(adapter), addr, rdata, timeout, cnt, rtw_get_time_interval_ms(start, end)); + } + + return rdata; +} + +void rtw_sec_write_cam(_adapter *adapter, u8 addr, u32 wdata) +{ + _mutex *mutex = &adapter_to_dvobj(adapter)->cam_ctl.sec_cam_access_mutex; + u32 cnt = 0; + u32 start = 0, end = 0; + u8 timeout = 0; + u8 sr = 0; + + _enter_critical_mutex(mutex, NULL); + + rtw_write32(adapter, REG_CAMWRITE, wdata); + rtw_write32(adapter, REG_CAMCMD, CAM_POLLINIG | CAM_WRITE | addr); + + start = rtw_get_current_time(); + while (1) { + if (rtw_is_surprise_removed(adapter)) { + sr = 1; + break; + } + + cnt++; + if (0 == (rtw_read32(adapter, REG_CAMCMD) & CAM_POLLINIG)) + break; + + if (rtw_get_passing_time_ms(start) > SEC_CAM_ACCESS_TIMEOUT_MS) { + timeout = 1; + break; + } + } + end = rtw_get_current_time(); + + _exit_critical_mutex(mutex, NULL); + + if (DBG_SEC_CAM_ACCESS || timeout) { + DBG_871X(FUNC_ADPT_FMT" addr:0x%02x, wdata:0x%08x, to:%u, polling:%u, %d ms\n" + , FUNC_ADPT_ARG(adapter), addr, wdata, timeout, cnt, rtw_get_time_interval_ms(start, end)); + } +} + +void rtw_sec_read_cam_ent(_adapter *adapter, u8 id, u8 *ctrl, u8 *mac, u8 *key) +{ + unsigned int val, addr; + u8 i; + u32 rdata; + u8 begin = 0; + u8 end = 5; /* TODO: consider other key length accordingly */ + + if (!ctrl && !mac && !key) { + rtw_warn_on(1); + goto exit; + } + + /* TODO: check id range */ + + if (!ctrl && !mac) + begin = 2; /* read from key */ + + if (!key && !mac) + end = 0; /* read to ctrl */ + else if (!key) + end = 2; /* read to mac */ + + for (i = begin; i <= end; i++) { + rdata = rtw_sec_read_cam(adapter, (id << 3) | i); + + switch (i) { + case 0: + if (ctrl) + _rtw_memcpy(ctrl, (u8 *)(&rdata), 2); + if (mac) + _rtw_memcpy(mac, ((u8 *)(&rdata)) + 2, 2); + break; + case 1: + if (mac) + _rtw_memcpy(mac + 2, (u8 *)(&rdata), 4); + break; + default: + if (key) + _rtw_memcpy(key + (i - 2) * 4, (u8 *)(&rdata), 4); + break; + } + } + +exit: + return; +} + + +void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key) +{ + unsigned int i; + int j; + u8 addr; + u32 wdata; + + /* TODO: consider other key length accordingly */ +#if 0 + switch ((ctrl & 0x1c) >> 2) { + case _WEP40_: + case _TKIP_ + case _AES_ + case _WEP104_ + + } +#else + j = 7; +#endif + + for (; j >= 0; j--) { + switch (j) { + case 0: + wdata = (ctrl | (mac[0] << 16) | (mac[1] << 24)); + break; + case 1: + wdata = (mac[2] | (mac[3] << 8) | (mac[4] << 16) | (mac[5] << 24)); + break; + case 6: + case 7: + wdata = 0; + break; + default: + i = (j - 2) << 2; + wdata = (key[i] | (key[i + 1] << 8) | (key[i + 2] << 16) | (key[i + 3] << 24)); + break; + } + + addr = (id << 3) + j; + + rtw_sec_write_cam(adapter, addr, wdata); + } +} + +bool rtw_sec_read_cam_is_gk(_adapter *adapter, u8 id) +{ + bool res; + u16 ctrl; + + rtw_sec_read_cam_ent(adapter, id, (u8 *)&ctrl, NULL, NULL); + + res = (ctrl & BIT6) ? _TRUE : _FALSE; + return res; +} + +void hw_var_port_switch(_adapter *adapter) +{ +#ifdef CONFIG_CONCURRENT_MODE +#ifdef CONFIG_RUNTIME_PORT_SWITCH +/* +0x102: MSR +0x550: REG_BCN_CTRL +0x551: REG_BCN_CTRL_1 +0x55A: REG_ATIMWND +0x560: REG_TSFTR +0x568: REG_TSFTR1 +0x570: REG_ATIMWND_1 +0x610: REG_MACID +0x618: REG_BSSID +0x700: REG_MACID1 +0x708: REG_BSSID1 +*/ + + int i; + u8 msr; + u8 bcn_ctrl; + u8 bcn_ctrl_1; + u8 atimwnd[2]; + u8 atimwnd_1[2]; + u8 tsftr[8]; + u8 tsftr_1[8]; + u8 macid[6]; + u8 bssid[6]; + u8 macid_1[6]; + u8 bssid_1[6]; + + u8 iface_type; + + msr = rtw_read8(adapter, MSR); + bcn_ctrl = rtw_read8(adapter, REG_BCN_CTRL); + bcn_ctrl_1 = rtw_read8(adapter, REG_BCN_CTRL_1); + + for (i=0; i<2; i++) + atimwnd[i] = rtw_read8(adapter, REG_ATIMWND+i); + for (i=0; i<2; i++) + atimwnd_1[i] = rtw_read8(adapter, REG_ATIMWND_1+i); + + for (i=0; i<8; i++) + tsftr[i] = rtw_read8(adapter, REG_TSFTR+i); + for (i=0; i<8; i++) + tsftr_1[i] = rtw_read8(adapter, REG_TSFTR1+i); + + for (i=0; i<6; i++) + macid[i] = rtw_read8(adapter, REG_MACID+i); + + for (i=0; i<6; i++) + bssid[i] = rtw_read8(adapter, REG_BSSID+i); + + for (i=0; i<6; i++) + macid_1[i] = rtw_read8(adapter, REG_MACID1+i); + + for (i=0; i<6; i++) + bssid_1[i] = rtw_read8(adapter, REG_BSSID1+i); + +#ifdef DBG_RUNTIME_PORT_SWITCH + DBG_871X(FUNC_ADPT_FMT" before switch\n" + "msr:0x%02x\n" + "bcn_ctrl:0x%02x\n" + "bcn_ctrl_1:0x%02x\n" + "atimwnd:0x%04x\n" + "atimwnd_1:0x%04x\n" + "tsftr:%llu\n" + "tsftr1:%llu\n" + "macid:"MAC_FMT"\n" + "bssid:"MAC_FMT"\n" + "macid_1:"MAC_FMT"\n" + "bssid_1:"MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter) + , msr + , bcn_ctrl + , bcn_ctrl_1 + , *((u16*)atimwnd) + , *((u16*)atimwnd_1) + , *((u64*)tsftr) + , *((u64*)tsftr_1) + , MAC_ARG(macid) + , MAC_ARG(bssid) + , MAC_ARG(macid_1) + , MAC_ARG(bssid_1) + ); +#endif /* DBG_RUNTIME_PORT_SWITCH */ + + /* disable bcn function, disable update TSF */ + rtw_write8(adapter, REG_BCN_CTRL, (bcn_ctrl & (~EN_BCN_FUNCTION)) | DIS_TSF_UDT); + rtw_write8(adapter, REG_BCN_CTRL_1, (bcn_ctrl_1 & (~EN_BCN_FUNCTION)) | DIS_TSF_UDT); + + /* switch msr */ + msr = (msr&0xf0) |((msr&0x03) << 2) | ((msr&0x0c) >> 2); + rtw_write8(adapter, MSR, msr); + + /* write port0 */ + rtw_write8(adapter, REG_BCN_CTRL, bcn_ctrl_1 & ~EN_BCN_FUNCTION); + for (i=0; i<2; i++) + rtw_write8(adapter, REG_ATIMWND+i, atimwnd_1[i]); + for (i=0; i<8; i++) + rtw_write8(adapter, REG_TSFTR+i, tsftr_1[i]); + for (i=0; i<6; i++) + rtw_write8(adapter, REG_MACID+i, macid_1[i]); + for (i=0; i<6; i++) + rtw_write8(adapter, REG_BSSID+i, bssid_1[i]); + + /* write port1 */ + rtw_write8(adapter, REG_BCN_CTRL_1, bcn_ctrl & ~EN_BCN_FUNCTION); + for (i=0; i<2; i++) + rtw_write8(adapter, REG_ATIMWND_1+1, atimwnd[i]); + for (i=0; i<8; i++) + rtw_write8(adapter, REG_TSFTR1+i, tsftr[i]); + for (i=0; i<6; i++) + rtw_write8(adapter, REG_MACID1+i, macid[i]); + for (i=0; i<6; i++) + rtw_write8(adapter, REG_BSSID1+i, bssid[i]); + + /* write bcn ctl */ +#ifdef CONFIG_BT_COEXIST +#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) + // always enable port0 beacon function for PSTDMA + bcn_ctrl_1 |= EN_BCN_FUNCTION; + // always disable port1 beacon function for PSTDMA + bcn_ctrl &= ~EN_BCN_FUNCTION; +#endif +#endif + rtw_write8(adapter, REG_BCN_CTRL, bcn_ctrl_1); + rtw_write8(adapter, REG_BCN_CTRL_1, bcn_ctrl); + + if (adapter->iface_type == IFACE_PORT0) { + adapter->iface_type = IFACE_PORT1; + adapter->pbuddy_adapter->iface_type = IFACE_PORT0; + DBG_871X_LEVEL(_drv_always_, "port switch - port0("ADPT_FMT"), port1("ADPT_FMT")\n", + ADPT_ARG(adapter->pbuddy_adapter), ADPT_ARG(adapter)); + } else { + adapter->iface_type = IFACE_PORT0; + adapter->pbuddy_adapter->iface_type = IFACE_PORT1; + DBG_871X_LEVEL(_drv_always_, "port switch - port0("ADPT_FMT"), port1("ADPT_FMT")\n", + ADPT_ARG(adapter), ADPT_ARG(adapter->pbuddy_adapter)); + } + +#ifdef DBG_RUNTIME_PORT_SWITCH + msr = rtw_read8(adapter, MSR); + bcn_ctrl = rtw_read8(adapter, REG_BCN_CTRL); + bcn_ctrl_1 = rtw_read8(adapter, REG_BCN_CTRL_1); + + for (i=0; i<2; i++) + atimwnd[i] = rtw_read8(adapter, REG_ATIMWND+i); + for (i=0; i<2; i++) + atimwnd_1[i] = rtw_read8(adapter, REG_ATIMWND_1+i); + + for (i=0; i<8; i++) + tsftr[i] = rtw_read8(adapter, REG_TSFTR+i); + for (i=0; i<8; i++) + tsftr_1[i] = rtw_read8(adapter, REG_TSFTR1+i); + + for (i=0; i<6; i++) + macid[i] = rtw_read8(adapter, REG_MACID+i); + + for (i=0; i<6; i++) + bssid[i] = rtw_read8(adapter, REG_BSSID+i); + + for (i=0; i<6; i++) + macid_1[i] = rtw_read8(adapter, REG_MACID1+i); + + for (i=0; i<6; i++) + bssid_1[i] = rtw_read8(adapter, REG_BSSID1+i); + + DBG_871X(FUNC_ADPT_FMT" after switch\n" + "msr:0x%02x\n" + "bcn_ctrl:0x%02x\n" + "bcn_ctrl_1:0x%02x\n" + "atimwnd:%u\n" + "atimwnd_1:%u\n" + "tsftr:%llu\n" + "tsftr1:%llu\n" + "macid:"MAC_FMT"\n" + "bssid:"MAC_FMT"\n" + "macid_1:"MAC_FMT"\n" + "bssid_1:"MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter) + , msr + , bcn_ctrl + , bcn_ctrl_1 + , *((u16*)atimwnd) + , *((u16*)atimwnd_1) + , *((u64*)tsftr) + , *((u64*)tsftr_1) + , MAC_ARG(macid) + , MAC_ARG(bssid) + , MAC_ARG(macid_1) + , MAC_ARG(bssid_1) + ); +#endif /* DBG_RUNTIME_PORT_SWITCH */ + +#endif /* CONFIG_RUNTIME_PORT_SWITCH */ +#endif /* CONFIG_CONCURRENT_MODE */ +} + +const char * const _h2c_msr_role_str[] = { + "RSVD", + "STA", + "AP", + "GC", + "GO", + "TDLS", + "ADHOC", + "INVALID", +}; + +/* +* rtw_hal_set_FwMediaStatusRpt_cmd - +* +* @adapter: +* @opmode: 0:disconnect, 1:connect +* @miracast: 0:it's not in miracast scenario. 1:it's in miracast scenario +* @miracast_sink: 0:source. 1:sink +* @role: The role of this macid. 0:rsvd. 1:STA. 2:AP. 3:GC. 4:GO. 5:TDLS +* @macid: +* @macid_ind: 0:update Media Status to macid. 1:update Media Status from macid to macid_end +* @macid_end: +*/ +s32 rtw_hal_set_FwMediaStatusRpt_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, bool macid_ind, u8 macid_end) +{ + struct macid_ctl_t *macid_ctl = &adapter->dvobj->macid_ctl; + u8 parm[H2C_MEDIA_STATUS_RPT_LEN] = {0}; + int i; + s32 ret; + + SET_H2CCMD_MSRRPT_PARM_OPMODE(parm, opmode); + SET_H2CCMD_MSRRPT_PARM_MACID_IND(parm, macid_ind); + SET_H2CCMD_MSRRPT_PARM_MIRACAST(parm, miracast); + SET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK(parm, miracast_sink); + SET_H2CCMD_MSRRPT_PARM_ROLE(parm, role); + SET_H2CCMD_MSRRPT_PARM_MACID(parm, macid); + SET_H2CCMD_MSRRPT_PARM_MACID_END(parm, macid_end); + + RT_PRINT_DATA(_module_hal_init_c_, _drv_always_, "MediaStatusRpt parm:", parm, H2C_MEDIA_STATUS_RPT_LEN); + + ret = rtw_hal_fill_h2c_cmd(adapter, H2C_MEDIA_STATUS_RPT, H2C_MEDIA_STATUS_RPT_LEN, parm); + if (ret != _SUCCESS) + goto exit; + +#if defined(CONFIG_RTL8188E) + if (rtw_get_chip_type(adapter) == RTL8188E) { + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + + /* 8188E FW doesn't set macid no link, driver does it by self */ + if (opmode) + rtw_hal_set_hwreg(adapter, HW_VAR_MACID_LINK, &macid); + else + rtw_hal_set_hwreg(adapter, HW_VAR_MACID_NOLINK, &macid); + + /* for 8188E RA */ + #if (RATE_ADAPTIVE_SUPPORT == 1) + if (hal_data->fw_ractrl == _FALSE) { + u8 max_macid; + + max_macid = rtw_search_max_mac_id(adapter); + rtw_hal_set_hwreg(adapter, HW_VAR_TX_RPT_MAX_MACID, &max_macid); + } + #endif + } +#endif + +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) + /* TODO: this should move to IOT issue area */ + if (rtw_get_chip_type(adapter) == RTL8812 + || rtw_get_chip_type(adapter) == RTL8821 + ) { + if (MLME_IS_STA(adapter)) + Hal_PatchwithJaguar_8812(adapter, opmode); + } +#endif + + SET_H2CCMD_MSRRPT_PARM_MACID_IND(parm, 0); + if (macid_ind == 0) + macid_end = macid; + + for (i = macid; macid <= macid_end; macid++) + rtw_macid_ctl_set_h2c_msr(macid_ctl, macid, parm[0]); + +exit: + return ret; +} + +inline s32 rtw_hal_set_FwMediaStatusRpt_single_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid) +{ + return rtw_hal_set_FwMediaStatusRpt_cmd(adapter, opmode, miracast, miracast_sink, role, macid, 0, 0); +} + +inline s32 rtw_hal_set_FwMediaStatusRpt_range_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, u8 macid_end) +{ + return rtw_hal_set_FwMediaStatusRpt_cmd(adapter, opmode, miracast, miracast_sink, role, macid, 1, macid_end); +} + +void rtw_hal_set_FwRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc) +{ + struct hal_ops *pHalFunc = &padapter->HalFunc; + u8 u1H2CRsvdPageParm[H2C_RSVDPAGE_LOC_LEN]={0}; + u8 ret = 0; + + DBG_871X("RsvdPageLoc: ProbeRsp=%d PsPoll=%d Null=%d QoSNull=%d BTNull=%d\n", + rsvdpageloc->LocProbeRsp, rsvdpageloc->LocPsPoll, + rsvdpageloc->LocNullData, rsvdpageloc->LocQosNull, + rsvdpageloc->LocBTQosNull); + + SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1H2CRsvdPageParm, rsvdpageloc->LocProbeRsp); + SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1H2CRsvdPageParm, rsvdpageloc->LocPsPoll); + SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocNullData); + SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocQosNull); + SET_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocBTQosNull); + + ret = rtw_hal_fill_h2c_cmd(padapter, + H2C_RSVD_PAGE, + H2C_RSVDPAGE_LOC_LEN, + u1H2CRsvdPageParm); + +} + +#ifdef CONFIG_GPIO_WAKEUP +void rtw_hal_switch_gpio_wl_ctrl(_adapter *padapter, u8 index, u8 enable) +{ + /* + * Switch GPIO_13, GPIO_14 to wlan control, or pull GPIO_13,14 MUST fail. + * It happended at 8723B/8192E/8821A. New IC will check multi function GPIO, + * and implement HAL function. + * TODO: GPIO_8 multi function? + */ + if (index == 13 || index == 14) + rtw_hal_set_hwreg(padapter, HW_SET_GPIO_WL_CTRL, (u8 *)(&enable)); +} + +void rtw_hal_set_output_gpio(_adapter *padapter, u8 index, u8 outputval) +{ + if ( index <= 7 ) { + /* config GPIO mode */ + rtw_write8(padapter, REG_GPIO_PIN_CTRL + 3, + rtw_read8(padapter, REG_GPIO_PIN_CTRL + 3) & ~BIT(index) ); + + /* config GPIO Sel */ + /* 0: input */ + /* 1: output */ + rtw_write8(padapter, REG_GPIO_PIN_CTRL + 2, + rtw_read8(padapter, REG_GPIO_PIN_CTRL + 2) | BIT(index)); + + /* set output value */ + if ( outputval ) { + rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1, + rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) | BIT(index)); + } else { + rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1, + rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) & ~BIT(index)); + } + } else if (index <= 15){ + /* 88C Series: */ + /* index: 11~8 transform to 3~0 */ + /* 8723 Series: */ + /* index: 12~8 transform to 4~0 */ + + index -= 8; + + /* config GPIO mode */ + rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 3, + rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 3) & ~BIT(index) ); + + /* config GPIO Sel */ + /* 0: input */ + /* 1: output */ + rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 2, + rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 2) | BIT(index)); + + /* set output value */ + if ( outputval ) { + rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1, + rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) | BIT(index)); + } else { + rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1, + rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) & ~BIT(index)); + } + } else { + DBG_871X("%s: invalid GPIO%d=%d\n", + __FUNCTION__, index, outputval); + } +} +#endif + +void rtw_hal_set_FwAoacRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc) +{ + struct hal_ops *pHalFunc = &padapter->HalFunc; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + u8 res = 0, count = 0, ret = 0; +} + +static void rtw_hal_construct_beacon(_adapter *padapter, + u8 *pframe, u32 *pLength) +{ + struct rtw_ieee80211_hdr *pwlanhdr; + u16 *fctrl; + u32 rate_len, pktlen; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + + + //DBG_871X("%s\n", __FUNCTION__); + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN); + + SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/); + //pmlmeext->mgnt_seq++; + SetFrameSubType(pframe, WIFI_BEACON); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pktlen = sizeof (struct rtw_ieee80211_hdr_3addr); + + //timestamp will be inserted by hardware + pframe += 8; + pktlen += 8; + + // beacon interval: 2 bytes + _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2); + + pframe += 2; + pktlen += 2; + + // capability info: 2 bytes + _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); + + pframe += 2; + pktlen += 2; + + if( (pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) + { + //DBG_871X("ie len=%d\n", cur_network->IELength); + pktlen += cur_network->IELength - sizeof(NDIS_802_11_FIXED_IEs); + _rtw_memcpy(pframe, cur_network->IEs+sizeof(NDIS_802_11_FIXED_IEs), pktlen); + + goto _ConstructBeacon; + } + + //below for ad-hoc mode + + // SSID + pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen); + + // supported rates... + rate_len = rtw_get_rateset_len(cur_network->SupportedRates); + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8)? 8: rate_len), cur_network->SupportedRates, &pktlen); + + // DS parameter set + pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen); + + if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) + { + u32 ATIMWindow; + // IBSS Parameter Set... + //ATIMWindow = cur->Configuration.ATIMWindow; + ATIMWindow = 0; + pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen); + } + + + //todo: ERP IE + + + // EXTERNDED SUPPORTED RATE + if (rate_len > 8) + { + pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen); + } + + + //todo:HT for adhoc + +_ConstructBeacon: + + if ((pktlen + TXDESC_SIZE) > 512) + { + DBG_871X("beacon frame too large\n"); + return; + } + + *pLength = pktlen; + + //DBG_871X("%s bcn_sz=%d\n", __FUNCTION__, pktlen); + +} + +static void rtw_hal_construct_PSPoll(_adapter *padapter, + u8 *pframe, u32 *pLength) +{ + struct rtw_ieee80211_hdr *pwlanhdr; + u16 *fctrl; + u32 pktlen; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + //DBG_871X("%s\n", __FUNCTION__); + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + // Frame control. + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + SetPwrMgt(fctrl); + SetFrameSubType(pframe, WIFI_PSPOLL); + + // AID. + SetDuration(pframe, (pmlmeinfo->aid | 0xc000)); + + // BSSID. + _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + // TA. + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + + *pLength = 16; +} + +static void rtw_hal_construct_NullFunctionData( + PADAPTER padapter, + u8 *pframe, + u32 *pLength, + u8 *StaAddr, + u8 bQoS, + u8 AC, + u8 bEosp, + u8 bForcePowerSave) +{ + struct rtw_ieee80211_hdr *pwlanhdr; + u16 *fctrl; + u32 pktlen; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wlan_network *cur_network = &pmlmepriv->cur_network; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + + //DBG_871X("%s:%d\n", __FUNCTION__, bForcePowerSave); + + pwlanhdr = (struct rtw_ieee80211_hdr*)pframe; + + fctrl = &pwlanhdr->frame_ctl; + *(fctrl) = 0; + if (bForcePowerSave) + { + SetPwrMgt(fctrl); + } + + switch(cur_network->network.InfrastructureMode) + { + case Ndis802_11Infrastructure: + SetToDs(fctrl); + _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, StaAddr, ETH_ALEN); + break; + case Ndis802_11APMode: + SetFrDs(fctrl); + _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN); + break; + case Ndis802_11IBSS: + default: + _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + break; + } + + SetSeqNum(pwlanhdr, 0); + + if (bQoS == _TRUE) { + struct rtw_ieee80211_hdr_3addr_qos *pwlanqoshdr; + + SetFrameSubType(pframe, WIFI_QOS_DATA_NULL); + + pwlanqoshdr = (struct rtw_ieee80211_hdr_3addr_qos*)pframe; + SetPriority(&pwlanqoshdr->qc, AC); + SetEOSP(&pwlanqoshdr->qc, bEosp); + + pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos); + } else { + SetFrameSubType(pframe, WIFI_DATA_NULL); + + pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + } + + *pLength = pktlen; +} + +void rtw_hal_construct_ProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength, + u8 *StaAddr, BOOLEAN bHideSSID) +{ + struct rtw_ieee80211_hdr *pwlanhdr; + u16 *fctrl; + u8 *mac, *bssid; + u32 pktlen; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + + /*DBG_871X("%s\n", __FUNCTION__);*/ + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + mac = adapter_mac_addr(padapter); + bssid = cur_network->MacAddress; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN); + + SetSeqNum(pwlanhdr, 0); + SetFrameSubType(fctrl, WIFI_PROBERSP); + + pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + pframe += pktlen; + + if (cur_network->IELength > MAX_IE_SZ) + return; + + _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength); + pframe += cur_network->IELength; + pktlen += cur_network->IELength; + + *pLength = pktlen; +} + +/* + * Description: Fill the reserved packets that FW will use to RSVD page. + * Now we just send 4 types packet to rsvd page. + * (1)Beacon, (2)Ps-poll, (3)Null data, (4)ProbeRsp. + * Input: + * finished - FALSE:At the first time we will send all the packets as a large packet to Hw, + * so we need to set the packet length to total lengh. + * TRUE: At the second time, we should send the first packet (default:beacon) + * to Hw again and set the lengh in descriptor to the real beacon lengh. + * 2009.10.15 by tynli. + * + * Page Size = 128: 8188e, 8723a/b, 8192c/d, + * Page Size = 256: 8192e, 8821a + * Page Size = 512: 8812a + */ + +void rtw_hal_set_fw_rsvd_page(_adapter* adapter, bool finished) +{ + PHAL_DATA_TYPE pHalData; + struct xmit_frame *pcmdframe; + struct pkt_attrib *pattrib; + struct xmit_priv *pxmitpriv; + struct mlme_ext_priv *pmlmeext; + struct mlme_ext_info *pmlmeinfo; + struct pwrctrl_priv *pwrctl; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct hal_ops *pHalFunc = &adapter->HalFunc; + u32 BeaconLength = 0, ProbeRspLength = 0, PSPollLength = 0; + u32 NullDataLength = 0, QosNullLength = 0, BTQosNullLength = 0; + u32 ProbeReqLength = 0, NullFunctionDataLength = 0; + u8 TxDescLen = TXDESC_SIZE, TxDescOffset = TXDESC_OFFSET; + u8 TotalPageNum = 0 , CurtPktPageNum = 0 , RsvdPageNum = 0; + u8 *ReservedPagePacket; + u16 BufIndex = 0; + u32 TotalPacketLen = 0, MaxRsvdPageBufSize = 0, PageSize = 0; + RSVDPAGE_LOC RsvdPageLoc; + +#ifdef DBG_CONFIG_ERROR_DETECT + struct sreset_priv *psrtpriv; +#endif /* DBG_CONFIG_ERROR_DETECT */ + + + pHalData = GET_HAL_DATA(adapter); +#ifdef DBG_CONFIG_ERROR_DETECT + psrtpriv = &pHalData->srestpriv; +#endif + pxmitpriv = &adapter->xmitpriv; + pmlmeext = &adapter->mlmeextpriv; + pmlmeinfo = &pmlmeext->mlmext_info; + pwrctl = adapter_to_pwrctl(adapter); + + rtw_hal_get_def_var(adapter, HAL_DEF_TX_PAGE_SIZE, (u8 *)&PageSize); + + if (PageSize == 0) { + DBG_871X("[Error]: %s, PageSize is zero!!\n", __func__); + return; + } + + if (pwrctl->wowlan_mode == _TRUE || pwrctl->wowlan_ap_mode == _TRUE) + RsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _TRUE); + else + RsvdPageNum = rtw_hal_get_txbuff_rsvd_page_num(adapter, _FALSE); + + DBG_871X("%s PageSize: %d, RsvdPageNUm: %d\n",__func__, PageSize, RsvdPageNum); + + MaxRsvdPageBufSize = RsvdPageNum*PageSize; + + if (MaxRsvdPageBufSize > MAX_CMDBUF_SZ) { + DBG_871X("%s MaxRsvdPageBufSize(%d) is larger than MAX_CMDBUF_SZ(%d)", + __func__, MaxRsvdPageBufSize, MAX_CMDBUF_SZ); + rtw_warn_on(1); + return; + } + + pcmdframe = rtw_alloc_cmdxmitframe(pxmitpriv); + + if (pcmdframe == NULL) { + DBG_871X("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__); + return; + } + + ReservedPagePacket = pcmdframe->buf_addr; + _rtw_memset(&RsvdPageLoc, 0, sizeof(RSVDPAGE_LOC)); + + /* beacon * 2 pages */ + BufIndex = TxDescOffset; + rtw_hal_construct_beacon(adapter, + &ReservedPagePacket[BufIndex], &BeaconLength); + + /* + * When we count the first page size, we need to reserve description size for the RSVD + * packet, it will be filled in front of the packet in TXPKTBUF. + */ + CurtPktPageNum = (u8)PageNum((TxDescLen + BeaconLength), PageSize); + /* If we don't add 1 more page, ARP offload function will fail at 8723bs.*/ + if (CurtPktPageNum == 1) + CurtPktPageNum += 1; + + TotalPageNum += CurtPktPageNum; + + BufIndex += (CurtPktPageNum*PageSize); + + if (pwrctl->wowlan_ap_mode == _TRUE) { + /* (4) probe response*/ + RsvdPageLoc.LocProbeRsp = TotalPageNum; + rtw_hal_construct_ProbeRsp( + adapter, &ReservedPagePacket[BufIndex], + &ProbeRspLength, + get_my_bssid(&pmlmeinfo->network), _FALSE); + rtw_hal_fill_fake_txdesc(adapter, + &ReservedPagePacket[BufIndex-TxDescLen], + ProbeRspLength, _FALSE, _FALSE, _FALSE); + + CurtPktPageNum = (u8)PageNum(TxDescLen + ProbeRspLength, PageSize); + TotalPageNum += CurtPktPageNum; + TotalPacketLen = BufIndex + ProbeRspLength; + BufIndex += (CurtPktPageNum*PageSize); + goto download_page; + } + + /* ps-poll * 1 page */ + RsvdPageLoc.LocPsPoll = TotalPageNum; + DBG_871X("LocPsPoll: %d\n", RsvdPageLoc.LocPsPoll); + rtw_hal_construct_PSPoll(adapter, + &ReservedPagePacket[BufIndex], &PSPollLength); + rtw_hal_fill_fake_txdesc(adapter, + &ReservedPagePacket[BufIndex-TxDescLen], + PSPollLength, _TRUE, _FALSE, _FALSE); + + CurtPktPageNum = (u8)PageNum((TxDescLen + PSPollLength), PageSize); + + TotalPageNum += CurtPktPageNum; + + BufIndex += (CurtPktPageNum*PageSize); + +#ifdef CONFIG_BT_COEXIST + /* BT Qos null data * 1 page */ + RsvdPageLoc.LocBTQosNull = TotalPageNum; + DBG_871X("LocBTQosNull: %d\n", RsvdPageLoc.LocBTQosNull); + rtw_hal_construct_NullFunctionData( + adapter, + &ReservedPagePacket[BufIndex], + &BTQosNullLength, + get_my_bssid(&pmlmeinfo->network), + _TRUE, 0, 0, _FALSE); + rtw_hal_fill_fake_txdesc(adapter, + &ReservedPagePacket[BufIndex-TxDescLen], + BTQosNullLength, _FALSE, _TRUE, _FALSE); + + CurtPktPageNum = (u8)PageNum(TxDescLen + BTQosNullLength, PageSize); + + TotalPageNum += CurtPktPageNum; + + BufIndex += (CurtPktPageNum*PageSize); +#endif /* CONFIG_BT_COEXIT */ + + /* null data * 1 page */ + RsvdPageLoc.LocNullData = TotalPageNum; + DBG_871X("LocNullData: %d\n", RsvdPageLoc.LocNullData); + rtw_hal_construct_NullFunctionData( + adapter, + &ReservedPagePacket[BufIndex], + &NullDataLength, + get_my_bssid(&pmlmeinfo->network), + _FALSE, 0, 0, _FALSE); + rtw_hal_fill_fake_txdesc(adapter, + &ReservedPagePacket[BufIndex-TxDescLen], + NullDataLength, _FALSE, _FALSE, _FALSE); + + CurtPktPageNum = (u8)PageNum(TxDescLen + NullDataLength, PageSize); + + TotalPageNum += CurtPktPageNum; + + BufIndex += (CurtPktPageNum*PageSize); + + //Qos null data * 1 page + RsvdPageLoc.LocQosNull = TotalPageNum; + DBG_871X("LocQosNull: %d\n", RsvdPageLoc.LocQosNull); + rtw_hal_construct_NullFunctionData( + adapter, + &ReservedPagePacket[BufIndex], + &QosNullLength, + get_my_bssid(&pmlmeinfo->network), + _TRUE, 0, 0, _FALSE); + rtw_hal_fill_fake_txdesc(adapter, + &ReservedPagePacket[BufIndex-TxDescLen], + QosNullLength, _FALSE, _FALSE, _FALSE); + + CurtPktPageNum = (u8)PageNum(TxDescLen + QosNullLength, PageSize); + + TotalPageNum += CurtPktPageNum; + + TotalPacketLen = BufIndex + QosNullLength; + + BufIndex += (CurtPktPageNum*PageSize); + +download_page: + /* DBG_871X("%s BufIndex(%d), TxDescLen(%d), PageSize(%d)\n",__func__, BufIndex, TxDescLen, PageSize);*/ + DBG_871X("%s PageNum(%d), pktlen(%d)\n", + __func__, TotalPageNum, TotalPacketLen); + + if (TotalPacketLen > MaxRsvdPageBufSize) { + DBG_871X("%s(ERROR): rsvd page size is not enough!!TotalPacketLen %d, MaxRsvdPageBufSize %d\n", + __FUNCTION__, TotalPacketLen,MaxRsvdPageBufSize); + rtw_warn_on(1); + goto error; + } else { + /* update attribute */ + pattrib = &pcmdframe->attrib; + update_mgntframe_attrib(adapter, pattrib); + pattrib->qsel = QSLT_BEACON; + pattrib->pktlen = TotalPacketLen - TxDescOffset; + pattrib->last_txcmdsz = TotalPacketLen - TxDescOffset; +#ifdef CONFIG_PCI_HCI + dump_mgntframe(adapter, pcmdframe); +#else + dump_mgntframe_and_wait(adapter, pcmdframe, 100); +#endif + } + + DBG_871X("%s: Set RSVD page location to Fw ,TotalPacketLen(%d), TotalPageNum(%d)\n", + __func__,TotalPacketLen,TotalPageNum); + + if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { + rtw_hal_set_FwRsvdPage_cmd(adapter, &RsvdPageLoc); + if (pwrctl->wowlan_mode == _TRUE) + rtw_hal_set_FwAoacRsvdPage_cmd(adapter, &RsvdPageLoc); + } else if (pwrctl->wowlan_pno_enable) { +#ifdef CONFIG_PNO_SUPPORT + rtw_hal_set_FwAoacRsvdPage_cmd(adapter, &RsvdPageLoc); + if(pwrctl->pno_in_resume) + rtw_hal_set_scan_offload_info_cmd(adapter, + &RsvdPageLoc, 0); + else + rtw_hal_set_scan_offload_info_cmd(adapter, + &RsvdPageLoc, 1); +#endif /* CONFIG_PNO_SUPPORT */ + } + return; +error: + rtw_free_xmitframe(pxmitpriv, pcmdframe); +} + +#ifdef CONFIG_TDLS +#ifdef CONFIG_TDLS_CH_SW +s32 rtw_hal_ch_sw_oper_offload(_adapter *padapter, u8 channel, u8 channel_offset, u16 bwmode) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + u8 ch_sw_h2c_buf[4] = {0x00, 0x00, 0x00, 0x00}; + + + SET_H2CCMD_CH_SW_OPER_OFFLOAD_CH_NUM(ch_sw_h2c_buf, channel); + SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_MODE(ch_sw_h2c_buf, bwmode); + switch (bwmode) { + case CHANNEL_WIDTH_40: + SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_40M_SC(ch_sw_h2c_buf, channel_offset); + break; + case CHANNEL_WIDTH_80: + SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_80M_SC(ch_sw_h2c_buf, channel_offset); + break; + case CHANNEL_WIDTH_20: + default: + break; + } + SET_H2CCMD_CH_SW_OPER_OFFLOAD_RFE_TYPE(ch_sw_h2c_buf, pHalData->RFEType); + + return rtw_hal_fill_h2c_cmd(padapter, H2C_CHNL_SWITCH_OPER_OFFLOAD, sizeof(ch_sw_h2c_buf), ch_sw_h2c_buf); +} +#endif +#endif + +void SetHwReg(_adapter *adapter, u8 variable, u8 *val) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); +_func_enter_; + + switch (variable) { + case HW_VAR_PORT_SWITCH: + hw_var_port_switch(adapter); + break; + case HW_VAR_INIT_RTS_RATE: + { + u16 brate_cfg = *((u16*)val); + u8 rate_index = 0; + HAL_VERSION *hal_ver = &hal_data->VersionID; + + if (IS_8188E(*hal_ver)) { + + while (brate_cfg > 0x1) { + brate_cfg = (brate_cfg >> 1); + rate_index++; + } + rtw_write8(adapter, REG_INIRTS_RATE_SEL, rate_index); + } else { + rtw_warn_on(1); + } + } + break; + case HW_VAR_SEC_CFG: + { + #if defined(CONFIG_CONCURRENT_MODE) && !defined(DYNAMIC_CAMID_ALLOC) + // enable tx enc and rx dec engine, and no key search for MC/BC + rtw_write8(adapter, REG_SECCFG, SCR_NoSKMC|SCR_RxDecEnable|SCR_TxEncEnable); + #elif defined(DYNAMIC_CAMID_ALLOC) + u16 reg_scr_ori; + u16 reg_scr; + + reg_scr = reg_scr_ori = rtw_read16(adapter, REG_SECCFG); + reg_scr |= (SCR_CHK_KEYID|SCR_RxDecEnable|SCR_TxEncEnable); + + if (_rtw_camctl_chk_cap(adapter, SEC_CAP_CHK_BMC)) + reg_scr |= SCR_CHK_BMC; + + if (_rtw_camctl_chk_flags(adapter, SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH)) + reg_scr |= SCR_NoSKMC; + + if (reg_scr != reg_scr_ori) + rtw_write16(adapter, REG_SECCFG, reg_scr); + #else + rtw_write8(adapter, REG_SECCFG, *((u8*)val)); + #endif + } + break; + case HW_VAR_SEC_DK_CFG: + { + struct security_priv *sec = &adapter->securitypriv; + u8 reg_scr = rtw_read8(adapter, REG_SECCFG); + + if (val) /* Enable default key related setting */ + { + reg_scr |= SCR_TXBCUSEDK; + if (sec->dot11AuthAlgrthm != dot11AuthAlgrthm_8021X) + reg_scr |= (SCR_RxUseDK|SCR_TxUseDK); + } + else /* Disable default key related setting */ + { + reg_scr &= ~(SCR_RXBCUSEDK|SCR_TXBCUSEDK|SCR_RxUseDK|SCR_TxUseDK); + } + + rtw_write8(adapter, REG_SECCFG, reg_scr); + } + break; + + case HW_VAR_ASIX_IOT: + // enable ASIX IOT function + if (*((u8*)val) == _TRUE) { + // 0xa2e[0]=0 (disable rake receiver) + rtw_write8(adapter, rCCK0_FalseAlarmReport+2, + rtw_read8(adapter, rCCK0_FalseAlarmReport+2) & ~(BIT0)); + // 0xa1c=0xa0 (reset channel estimation if signal quality is bad) + rtw_write8(adapter, rCCK0_DSPParameter2, 0xa0); + } else { + // restore reg:0xa2e, reg:0xa1c + rtw_write8(adapter, rCCK0_FalseAlarmReport+2, + rtw_read8(adapter, rCCK0_FalseAlarmReport+2)|(BIT0)); + rtw_write8(adapter, rCCK0_DSPParameter2, 0x00); + } + break; + default: + if (0) + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" variable(%d) not defined!\n", + FUNC_ADPT_ARG(adapter), variable); + break; + } + +_func_exit_; +} + +void GetHwReg(_adapter *adapter, u8 variable, u8 *val) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + +_func_enter_; + + switch (variable) { + case HW_VAR_BASIC_RATE: + *((u16*)val) = hal_data->BasicRateSet; + break; + case HW_VAR_RF_TYPE: + *((u8*)val) = hal_data->rf_type; + break; + case HW_VAR_DO_IQK: + *val = hal_data->bNeedIQK; + break; + case HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO: + if (hal_is_band_support(adapter, BAND_ON_5G)) + *val = _TRUE; + else + *val = _FALSE; + + break; + default: + if (0) + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" variable(%d) not defined!\n", + FUNC_ADPT_ARG(adapter), variable); + break; + } + +_func_exit_; +} + +u8 +SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u8 bResult = _SUCCESS; + + switch(variable) { + + case HAL_DEF_DBG_DUMP_RXPKT: + hal_data->bDumpRxPkt = *((u8*)value); + break; + case HAL_DEF_DBG_DUMP_TXPKT: + hal_data->bDumpTxPkt = *((u8*)value); + break; + case HAL_DEF_ANT_DETECT: + hal_data->AntDetection = *((u8 *)value); + break; + case HAL_DEF_DBG_DIS_PWT: + hal_data->bDisableTXPowerTraining = *((u8*)value); + break; + default: + DBG_871X_LEVEL(_drv_always_, "%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __FUNCTION__, variable); + bResult = _FAIL; + break; + } + + return bResult; +} + +#ifdef CONFIG_BEAMFORMING +u8 rtw_hal_query_txbfer_rf_num(_adapter *adapter) +{ + struct registry_priv *pregistrypriv = &adapter->registrypriv; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + + if ((pregistrypriv->beamformer_rf_num) && (IS_HARDWARE_TYPE_8814AE(adapter) || IS_HARDWARE_TYPE_8814AU(adapter) || IS_HARDWARE_TYPE_8822BU(adapter))) + return pregistrypriv->beamformer_rf_num; + else if (IS_HARDWARE_TYPE_8814AE(adapter) +/* +#if defined(CONFIG_USB_HCI) + || (IS_HARDWARE_TYPE_8814AU(adapter) && (pUsbModeMech->CurUsbMode == 2 || pUsbModeMech->HubUsbMode == 2)) //for USB3.0 +#endif +*/ + ) { + /*BF cap provided by Yu Chen, Sean, 2015, 01 */ + if (hal_data->rf_type == RF_3T3R) + return 2; + else if (hal_data->rf_type == RF_4T4R) + return 3; + else + return 1; + } else + return 1; + +} +u8 rtw_hal_query_txbfee_rf_num(_adapter *adapter) +{ + struct registry_priv *pregistrypriv = &adapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + + if ((pregistrypriv->beamformee_rf_num) && (IS_HARDWARE_TYPE_8814AE(adapter) || IS_HARDWARE_TYPE_8814AU(adapter) || IS_HARDWARE_TYPE_8822BU(adapter))) + return pregistrypriv->beamformee_rf_num; + else if (IS_HARDWARE_TYPE_8814AE(adapter) || IS_HARDWARE_TYPE_8814AU(adapter)) { + if (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_BROADCOM) + return 2; + else + return 2;/*TODO: May be 3 in the future, by ChenYu. */ + } else + return 1; + +} +#endif + +u8 +GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u8 bResult = _SUCCESS; + + switch(variable) { + case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB: + { + struct mlme_priv *pmlmepriv; + struct sta_priv *pstapriv; + struct sta_info *psta; + + pmlmepriv = &adapter->mlmepriv; + pstapriv = &adapter->stapriv; + psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress); + if (psta) + { + *((int*)value) = psta->rssi_stat.UndecoratedSmoothedPWDB; + } + } + break; + case HAL_DEF_DBG_DUMP_RXPKT: + *((u8*)value) = hal_data->bDumpRxPkt; + break; + case HAL_DEF_DBG_DUMP_TXPKT: + *((u8*)value) = hal_data->bDumpTxPkt; + break; + case HAL_DEF_ANT_DETECT: + *((u8 *)value) = hal_data->AntDetection; + break; + case HAL_DEF_MACID_SLEEP: + *(u8*)value = _FALSE; + break; + case HAL_DEF_TX_PAGE_SIZE: + *(( u32*)value) = PAGE_SIZE_128; + break; + case HAL_DEF_DBG_DIS_PWT: + *(u8*)value = hal_data->bDisableTXPowerTraining; + break; +#ifdef CONFIG_BEAMFORMING + case HAL_DEF_BEAMFORMER_CAP: + *(u8 *)value = rtw_hal_query_txbfer_rf_num(adapter); + break; + case HAL_DEF_BEAMFORMEE_CAP: + *(u8 *)value = rtw_hal_query_txbfee_rf_num(adapter); + break; +#endif + default: + DBG_871X_LEVEL(_drv_always_, "%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __FUNCTION__, variable); + bResult = _FAIL; + break; + } + + return bResult; +} + +void SetHalODMVar( + PADAPTER Adapter, + HAL_ODM_VARIABLE eVariable, + PVOID pValue1, + BOOLEAN bSet) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T podmpriv = &pHalData->odmpriv; + //_irqL irqL; + switch(eVariable){ + case HAL_ODM_STA_INFO: + { + struct sta_info *psta = (struct sta_info *)pValue1; + if(bSet){ + DBG_8192C("### Set STA_(%d) info ###\n",psta->mac_id); + ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS,psta->mac_id,psta); + } + else{ + DBG_8192C("### Clean STA_(%d) info ###\n",psta->mac_id); + //_enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); + ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS,psta->mac_id,NULL); + + //_exit_critical_bh(&pHalData->odm_stainfo_lock, &irqL); + } + } + break; + case HAL_ODM_P2P_STATE: + ODM_CmnInfoUpdate(podmpriv,ODM_CMNINFO_WIFI_DIRECT,bSet); + break; + case HAL_ODM_WIFI_DISPLAY_STATE: + ODM_CmnInfoUpdate(podmpriv,ODM_CMNINFO_WIFI_DISPLAY,bSet); + break; + case HAL_ODM_REGULATION: + ODM_CmnInfoInit(podmpriv, ODM_CMNINFO_DOMAIN_CODE_2G, pHalData->Regulation2_4G); + ODM_CmnInfoInit(podmpriv, ODM_CMNINFO_DOMAIN_CODE_5G, pHalData->Regulation5G); + break; +#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) + case HAL_ODM_NOISE_MONITOR: + { + struct noise_info *pinfo = (struct noise_info *)pValue1; + + #ifdef DBG_NOISE_MONITOR + DBG_8192C("### Noise monitor chan(%d)-bPauseDIG:%d,IGIValue:0x%02x,max_time:%d (ms) ###\n", + pinfo->chan,pinfo->bPauseDIG,pinfo->IGIValue,pinfo->max_time); + #endif + + pHalData->noise[pinfo->chan] = ODM_InbandNoise_Monitor(podmpriv,pinfo->bPauseDIG,pinfo->IGIValue,pinfo->max_time); + DBG_871X("chan_%d, noise = %d (dBm)\n",pinfo->chan,pHalData->noise[pinfo->chan]); + #ifdef DBG_NOISE_MONITOR + DBG_871X("noise_a = %d, noise_b = %d noise_all:%d \n", + podmpriv->noise_level.noise[ODM_RF_PATH_A], + podmpriv->noise_level.noise[ODM_RF_PATH_B], + podmpriv->noise_level.noise_all); + #endif + } + break; +#endif/*#ifdef CONFIG_BACKGROUND_NOISE_MONITOR*/ + + case HAL_ODM_INITIAL_GAIN: + { + u8 rx_gain = *((u8 *)(pValue1)); + /*printk("rx_gain:%x\n",rx_gain);*/ + if (rx_gain == 0xff) {/*restore rx gain*/ + /*ODM_Write_DIG(podmpriv,pDigTable->BackupIGValue);*/ + odm_PauseDIG(podmpriv, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, rx_gain); + } else { + /*pDigTable->BackupIGValue = pDigTable->CurIGValue;*/ + /*ODM_Write_DIG(podmpriv,rx_gain);*/ + odm_PauseDIG(podmpriv, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, rx_gain); + } + } + break; + case HAL_ODM_FA_CNT_DUMP: + if (*((u8 *)pValue1)) + podmpriv->DebugComponents |= (ODM_COMP_DIG | ODM_COMP_FA_CNT); + else + podmpriv->DebugComponents &= ~(ODM_COMP_DIG | ODM_COMP_FA_CNT); + break; + case HAL_ODM_DBG_FLAG: + ODM_CmnInfoUpdate(podmpriv, ODM_CMNINFO_DBG_COMP, *((u8Byte *)pValue1)); + break; + case HAL_ODM_DBG_LEVEL: + ODM_CmnInfoUpdate(podmpriv, ODM_CMNINFO_DBG_LEVEL, *((u4Byte *)pValue1)); + break; + case HAL_ODM_RX_INFO_DUMP: + { + PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure(podmpriv , PHYDM_FALSEALMCNT); + pDIG_T pDM_DigTable = &podmpriv->DM_DigTable; + void *sel; + + sel = pValue1; + + DBG_871X_SEL(sel , "============ Rx Info dump ===================\n"); + DBG_871X_SEL(sel , "bLinked = %d, RSSI_Min = %d(%%), CurrentIGI = 0x%x\n", podmpriv->bLinked, podmpriv->RSSI_Min, pDM_DigTable->CurIGValue); + DBG_871X_SEL(sel , "Cnt_Cck_fail = %d, Cnt_Ofdm_fail = %d, Total False Alarm = %d\n", FalseAlmCnt->Cnt_Cck_fail, FalseAlmCnt->Cnt_Ofdm_fail, FalseAlmCnt->Cnt_all); + + if (podmpriv->bLinked) { + DBG_871X_SEL(sel , "RxRate = %s", HDATA_RATE(podmpriv->RxRate)); + DBG_871X_SEL(sel , " RSSI_A = %d(%%), RSSI_B = %d(%%)\n", podmpriv->RSSI_A, podmpriv->RSSI_B); + #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA + rtw_dump_raw_rssi_info(Adapter, sel); + #endif + } + } + break; + +#ifdef CONFIG_AUTO_CHNL_SEL_NHM + case HAL_ODM_AUTO_CHNL_SEL: + { + ACS_OP acs_op = *(ACS_OP *)pValue1; + + rtw_phydm_func_set(Adapter, ODM_BB_NHM_CNT); + + if (ACS_INIT == acs_op) { + #ifdef DBG_AUTO_CHNL_SEL_NHM + DBG_871X("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: ACS_INIT\n", ADPT_ARG(Adapter)); + #endif + odm_AutoChannelSelectInit(podmpriv); + } else if (ACS_RESET == acs_op) { + /* Reset statistics for auto channel selection mechanism.*/ + #ifdef DBG_AUTO_CHNL_SEL_NHM + DBG_871X("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: ACS_RESET\n", ADPT_ARG(Adapter)); + #endif + odm_AutoChannelSelectReset(podmpriv); + + } else if (ACS_SELECT == acs_op) { + /* Collect NHM measurement result after current channel */ + #ifdef DBG_AUTO_CHNL_SEL_NHM + DBG_871X("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: ACS_SELECT, CH(%d)\n", ADPT_ARG(Adapter), rtw_get_acs_channel(Adapter)); + #endif + odm_AutoChannelSelect(podmpriv, rtw_get_acs_channel(Adapter)); + } else + DBG_871X("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: Unexpected OP\n", ADPT_ARG(Adapter)); + + } + break; +#endif +#ifdef CONFIG_ANTENNA_DIVERSITY + case HAL_ODM_ANTDIV_SELECT: + { + u8 antenna = (*(u8 *)pValue1); + + /*switch antenna*/ + ODM_UpdateRxIdleAnt(&pHalData->odmpriv, antenna); + /*DBG_871X("==> HAL_ODM_ANTDIV_SELECT, Ant_(%s)\n", (antenna == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");*/ + + } + break; +#endif + + default: + break; + } +} + +void GetHalODMVar( + PADAPTER Adapter, + HAL_ODM_VARIABLE eVariable, + PVOID pValue1, + PVOID pValue2) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T podmpriv = &pHalData->odmpriv; + + switch (eVariable) { +#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) + case HAL_ODM_NOISE_MONITOR: + { + u8 chan = *(u8 *)pValue1; + *(s16 *)pValue2 = pHalData->noise[chan]; + #ifdef DBG_NOISE_MONITOR + DBG_8192C("### Noise monitor chan(%d)-noise:%d (dBm) ###\n", + chan, pHalData->noise[chan]); + #endif + } + break; +#endif/*#ifdef CONFIG_BACKGROUND_NOISE_MONITOR*/ + case HAL_ODM_DBG_FLAG: + *((u8Byte *)pValue1) = podmpriv->DebugComponents; + break; + case HAL_ODM_DBG_LEVEL: + *((u4Byte *)pValue1) = podmpriv->DebugLevel; + break; + +#ifdef CONFIG_AUTO_CHNL_SEL_NHM + case HAL_ODM_AUTO_CHNL_SEL: + { + #ifdef DBG_AUTO_CHNL_SEL_NHM + DBG_871X("[ACS-"ADPT_FMT"] HAL_ODM_AUTO_CHNL_SEL: GET_BEST_CHAN\n", ADPT_ARG(Adapter)); + #endif + /* Retrieve better channel from NHM mechanism */ + if (IsSupported24G(Adapter->registrypriv.wireless_mode)) + *((u8 *)(pValue1)) = ODM_GetAutoChannelSelectResult(podmpriv, BAND_ON_2_4G); + if (IsSupported5G(Adapter->registrypriv.wireless_mode)) + *((u8 *)(pValue2)) = ODM_GetAutoChannelSelectResult(podmpriv, BAND_ON_5G); + } + break; +#endif +#ifdef CONFIG_ANTENNA_DIVERSITY + case HAL_ODM_ANTDIV_SELECT: + { + pFAT_T pDM_FatTable = &podmpriv->DM_FatTable; + *((u8 *)pValue1) = pDM_FatTable->RxIdleAnt; + } + break; +#endif + case HAL_ODM_INITIAL_GAIN: + { + pDIG_T pDM_DigTable = &podmpriv->DM_DigTable; + *((u8 *)pValue1) = pDM_DigTable->CurIGValue; + } + break; + default: + break; + } +} + + +u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); + PDM_ODM_T podmpriv = &pHalData->odmpriv; + u32 result = 0; + + switch (ops) { + case HAL_PHYDM_DIS_ALL_FUNC: + podmpriv->SupportAbility = DYNAMIC_FUNC_DISABLE; + break; + case HAL_PHYDM_FUNC_SET: + podmpriv->SupportAbility |= ability; + break; + case HAL_PHYDM_FUNC_CLR: + podmpriv->SupportAbility &= ~(ability); + break; + case HAL_PHYDM_ABILITY_BK: + /* dm flag backup*/ + podmpriv->BK_SupportAbility = podmpriv->SupportAbility; + break; + case HAL_PHYDM_ABILITY_RESTORE: + /* restore dm flag */ + podmpriv->SupportAbility = podmpriv->BK_SupportAbility; + break; + case HAL_PHYDM_ABILITY_SET: + podmpriv->SupportAbility = ability; + break; + case HAL_PHYDM_ABILITY_GET: + result = podmpriv->SupportAbility; + break; + } + return result; +} + + +BOOLEAN +eqNByte( + u8* str1, + u8* str2, + u32 num + ) +{ + if(num==0) + return _FALSE; + while(num>0) + { + num--; + if(str1[num]!=str2[num]) + return _FALSE; + } + return _TRUE; +} + +// +// Description: +// Translate a character to hex digit. +// +u32 +MapCharToHexDigit( + IN char chTmp +) +{ + if(chTmp >= '0' && chTmp <= '9') + return (chTmp - '0'); + else if(chTmp >= 'a' && chTmp <= 'f') + return (10 + (chTmp - 'a')); + else if(chTmp >= 'A' && chTmp <= 'F') + return (10 + (chTmp - 'A')); + else + return 0; +} + + + +// +// Description: +// Parse hex number from the string pucStr. +// +BOOLEAN +GetHexValueFromString( + IN char* szStr, + IN OUT u32* pu4bVal, + IN OUT u32* pu4bMove +) +{ + char* szScan = szStr; + + // Check input parameter. + if(szStr == NULL || pu4bVal == NULL || pu4bMove == NULL) + { + DBG_871X("GetHexValueFromString(): Invalid inpur argumetns! szStr: %p, pu4bVal: %p, pu4bMove: %p\n", szStr, pu4bVal, pu4bMove); + return _FALSE; + } + + // Initialize output. + *pu4bMove = 0; + *pu4bVal = 0; + + // Skip leading space. + while( *szScan != '\0' && + (*szScan == ' ' || *szScan == '\t') ) + { + szScan++; + (*pu4bMove)++; + } + + // Skip leading '0x' or '0X'. + if(*szScan == '0' && (*(szScan+1) == 'x' || *(szScan+1) == 'X')) + { + szScan += 2; + (*pu4bMove) += 2; + } + + // Check if szScan is now pointer to a character for hex digit, + // if not, it means this is not a valid hex number. + if(!IsHexDigit(*szScan)) + { + return _FALSE; + } + + // Parse each digit. + do + { + (*pu4bVal) <<= 4; + *pu4bVal += MapCharToHexDigit(*szScan); + + szScan++; + (*pu4bMove)++; + } while(IsHexDigit(*szScan)); + + return _TRUE; +} + +BOOLEAN +GetFractionValueFromString( + IN char* szStr, + IN OUT u8* pInteger, + IN OUT u8* pFraction, + IN OUT u32* pu4bMove +) +{ + char *szScan = szStr; + + // Initialize output. + *pu4bMove = 0; + *pInteger = 0; + *pFraction = 0; + + // Skip leading space. + while ( *szScan != '\0' && (*szScan == ' ' || *szScan == '\t') ) { + ++szScan; + ++(*pu4bMove); + } + + // Parse each digit. + do { + (*pInteger) *= 10; + *pInteger += ( *szScan - '0' ); + + ++szScan; + ++(*pu4bMove); + + if ( *szScan == '.' ) + { + ++szScan; + ++(*pu4bMove); + + if ( *szScan < '0' || *szScan > '9' ) + return _FALSE; + else { + *pFraction = *szScan - '0'; + ++szScan; + ++(*pu4bMove); + return _TRUE; + } + } + } while(*szScan >= '0' && *szScan <= '9'); + + return _TRUE; +} + +// +// Description: +// Return TRUE if szStr is comment out with leading "//". +// +BOOLEAN +IsCommentString( + IN char *szStr +) +{ + if(*szStr == '/' && *(szStr+1) == '/') + { + return _TRUE; + } + else + { + return _FALSE; + } +} + +BOOLEAN +GetU1ByteIntegerFromStringInDecimal( + IN char* Str, + IN OUT u8* pInt + ) +{ + u16 i = 0; + *pInt = 0; + + while ( Str[i] != '\0' ) + { + if ( Str[i] >= '0' && Str[i] <= '9' ) + { + *pInt *= 10; + *pInt += ( Str[i] - '0' ); + } + else + { + return _FALSE; + } + ++i; + } + + return _TRUE; +} + +// <20121004, Kordan> For example, +// ParseQualifiedString(inString, 0, outString, '[', ']') gets "Kordan" from a string "Hello [Kordan]". +// If RightQualifier does not exist, it will hang on in the while loop +BOOLEAN +ParseQualifiedString( + IN char* In, + IN OUT u32* Start, + OUT char* Out, + IN char LeftQualifier, + IN char RightQualifier + ) +{ + u32 i = 0, j = 0; + char c = In[(*Start)++]; + + if (c != LeftQualifier) + return _FALSE; + + i = (*Start); + while ((c = In[(*Start)++]) != RightQualifier) + ; // find ']' + j = (*Start) - 2; + strncpy((char *)Out, (const char*)(In+i), j-i+1); + + return _TRUE; +} + +BOOLEAN +isAllSpaceOrTab( + u8* data, + u8 size + ) +{ + u8 cnt = 0, NumOfSpaceAndTab = 0; + + while( size > cnt ) + { + if ( data[cnt] == ' ' || data[cnt] == '\t' || data[cnt] == '\0' ) + ++NumOfSpaceAndTab; + + ++cnt; + } + + return size == NumOfSpaceAndTab; +} + + +void rtw_hal_check_rxfifo_full(_adapter *adapter) +{ + struct dvobj_priv *psdpriv = adapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(adapter); + int save_cnt=_FALSE; + + //switch counter to RX fifo + if (IS_8188E(pHalData->VersionID) || IS_8188F(pHalData->VersionID) + || IS_8812_SERIES(pHalData->VersionID) || IS_8821_SERIES(pHalData->VersionID) + || IS_8723B_SERIES(pHalData->VersionID) || IS_8192E(pHalData->VersionID) || IS_8703B_SERIES(pHalData->VersionID)) + { + rtw_write8(adapter, REG_RXERR_RPT+3, rtw_read8(adapter, REG_RXERR_RPT+3)|0xa0); + save_cnt = _TRUE; + } + else + { + //todo: other chips + } + + + if (save_cnt) { + pdbgpriv->dbg_rx_fifo_last_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow; + pdbgpriv->dbg_rx_fifo_curr_overflow = rtw_read16(adapter, REG_RXERR_RPT); + pdbgpriv->dbg_rx_fifo_diff_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow-pdbgpriv->dbg_rx_fifo_last_overflow; + } else { + /* special value to indicate no implementation */ + pdbgpriv->dbg_rx_fifo_last_overflow = 1; + pdbgpriv->dbg_rx_fifo_curr_overflow = 1; + pdbgpriv->dbg_rx_fifo_diff_overflow = 1; + } +} + +void linked_info_dump(_adapter *padapter,u8 benable) +{ + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + + if(padapter->bLinkInfoDump == benable) + return; + + DBG_871X("%s %s \n",__FUNCTION__,(benable)?"enable":"disable"); + + if(benable){ + #ifdef CONFIG_LPS + pwrctrlpriv->org_power_mgnt = pwrctrlpriv->power_mgnt;//keep org value + rtw_pm_set_lps(padapter,PS_MODE_ACTIVE); + #endif + + #ifdef CONFIG_IPS + pwrctrlpriv->ips_org_mode = pwrctrlpriv->ips_mode;//keep org value + rtw_pm_set_ips(padapter,IPS_NONE); + #endif + } + else{ + #ifdef CONFIG_IPS + rtw_pm_set_ips(padapter, pwrctrlpriv->ips_org_mode); + #endif // CONFIG_IPS + + #ifdef CONFIG_LPS + rtw_pm_set_lps(padapter, pwrctrlpriv->org_power_mgnt ); + #endif // CONFIG_LPS + } + padapter->bLinkInfoDump = benable ; +} + +#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA +void rtw_get_raw_rssi_info(void *sel, _adapter *padapter) +{ + u8 isCCKrate,rf_path; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info; + + DBG_871X_SEL_NL(sel,"RxRate = %s, PWDBALL = %d(%%), rx_pwr_all = %d(dBm)\n", + HDATA_RATE(psample_pkt_rssi->data_rate), psample_pkt_rssi->pwdball, psample_pkt_rssi->pwr_all); + isCCKrate = (psample_pkt_rssi->data_rate <= DESC_RATE11M)?TRUE :FALSE; + + if(isCCKrate) + psample_pkt_rssi->mimo_signal_strength[0] = psample_pkt_rssi->pwdball; + + for(rf_path = 0;rf_pathNumTotalRFPath;rf_path++) + { + DBG_871X_SEL_NL(sel, "RF_PATH_%d=>signal_strength:%d(%%),signal_quality:%d(%%)\n" + , rf_path, psample_pkt_rssi->mimo_signal_strength[rf_path], psample_pkt_rssi->mimo_signal_quality[rf_path]); + + if(!isCCKrate){ + DBG_871X_SEL_NL(sel,"\trx_ofdm_pwr:%d(dBm),rx_ofdm_snr:%d(dB)\n", + psample_pkt_rssi->ofdm_pwr[rf_path],psample_pkt_rssi->ofdm_snr[rf_path]); + } + } +} + +void rtw_dump_raw_rssi_info(_adapter *padapter, void *sel) +{ + u8 isCCKrate,rf_path; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info; + DBG_871X_SEL(sel, "============ RAW Rx Info dump ===================\n"); + DBG_871X_SEL(sel, "RxRate = %s, PWDBALL = %d(%%), rx_pwr_all = %d(dBm)\n", HDATA_RATE(psample_pkt_rssi->data_rate), psample_pkt_rssi->pwdball, psample_pkt_rssi->pwr_all); + + isCCKrate = (psample_pkt_rssi->data_rate <= DESC_RATE11M)?TRUE :FALSE; + + if(isCCKrate) + psample_pkt_rssi->mimo_signal_strength[0] = psample_pkt_rssi->pwdball; + + for(rf_path = 0;rf_pathNumTotalRFPath;rf_path++) + { + DBG_871X_SEL(sel , "RF_PATH_%d=>signal_strength:%d(%%),signal_quality:%d(%%)" + , rf_path, psample_pkt_rssi->mimo_signal_strength[rf_path], psample_pkt_rssi->mimo_signal_quality[rf_path]); + + if (!isCCKrate) + DBG_871X_SEL(sel , ",rx_ofdm_pwr:%d(dBm),rx_ofdm_snr:%d(dB)\n", psample_pkt_rssi->ofdm_pwr[rf_path], psample_pkt_rssi->ofdm_snr[rf_path]); + else + DBG_871X_SEL(sel , "\n"); + + } +} + +void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe) +{ + u8 isCCKrate,rf_path; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; + + PODM_PHY_INFO_T pPhyInfo = (PODM_PHY_INFO_T)(&pattrib->phy_info); + struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info; + + psample_pkt_rssi->data_rate = pattrib->data_rate; + isCCKrate = (pattrib->data_rate <= DESC_RATE11M)?TRUE :FALSE; + + psample_pkt_rssi->pwdball = pPhyInfo->RxPWDBAll; + psample_pkt_rssi->pwr_all = pPhyInfo->RecvSignalPower; + + for(rf_path = 0;rf_pathNumTotalRFPath;rf_path++) + { + psample_pkt_rssi->mimo_signal_strength[rf_path] = pPhyInfo->RxMIMOSignalStrength[rf_path]; + psample_pkt_rssi->mimo_signal_quality[rf_path] = pPhyInfo->RxMIMOSignalQuality[rf_path]; + if(!isCCKrate){ + psample_pkt_rssi->ofdm_pwr[rf_path] = pPhyInfo->RxPwr[rf_path]; + psample_pkt_rssi->ofdm_snr[rf_path] = pPhyInfo->RxSNR[rf_path]; + } + } +} +#endif + +int check_phy_efuse_tx_power_info_valid(PADAPTER padapter) { + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + u8* pContent = pHalData->efuse_eeprom_data; + int index = 0; + u16 tx_index_offset = 0x0000; + + switch (rtw_get_chip_type(padapter)) { + case RTL8723B: + tx_index_offset = EEPROM_TX_PWR_INX_8723B; + break; + case RTL8703B: + tx_index_offset = EEPROM_TX_PWR_INX_8703B; + break; + case RTL8188E: + tx_index_offset = EEPROM_TX_PWR_INX_88E; + break; + case RTL8188F: + tx_index_offset = EEPROM_TX_PWR_INX_8188F; + break; + case RTL8192E: + tx_index_offset = EEPROM_TX_PWR_INX_8192E; + break; + case RTL8821: + tx_index_offset = EEPROM_TX_PWR_INX_8821; + break; + case RTL8812: + tx_index_offset = EEPROM_TX_PWR_INX_8812; + break; + case RTL8814A: + tx_index_offset = EEPROM_TX_PWR_INX_8814; + break; + default: + tx_index_offset = 0x0010; + break; + } + + /* TODO: chacking length by ICs */ + for (index = 0 ; index < 11 ; index++) { + if (pContent[tx_index_offset + index] == 0xFF) + return _FALSE; + } + return _TRUE; +} + +int hal_efuse_macaddr_offset(_adapter *adapter) +{ + u8 interface_type = 0; + int addr_offset = -1; + + interface_type = rtw_get_intf_type(adapter); + + switch (rtw_get_chip_type(adapter)) { +#ifdef CONFIG_RTL8723B + case RTL8723B: + if (interface_type == RTW_USB) + addr_offset = EEPROM_MAC_ADDR_8723BU; + else if (interface_type == RTW_SDIO) + addr_offset = EEPROM_MAC_ADDR_8723BS; + else if (interface_type == RTW_PCIE) + addr_offset = EEPROM_MAC_ADDR_8723BE; + break; +#endif +#ifdef CONFIG_RTL8703B + case RTL8703B: + if (interface_type == RTW_USB) + addr_offset = EEPROM_MAC_ADDR_8703BU; + else if (interface_type == RTW_SDIO) + addr_offset = EEPROM_MAC_ADDR_8703BS; + break; +#endif +#ifdef CONFIG_RTL8188E + case RTL8188E: + if (interface_type == RTW_USB) + addr_offset = EEPROM_MAC_ADDR_88EU; + else if (interface_type == RTW_SDIO) + addr_offset = EEPROM_MAC_ADDR_88ES; + else if (interface_type == RTW_PCIE) + addr_offset = EEPROM_MAC_ADDR_88EE; + break; +#endif +#ifdef CONFIG_RTL8188F + case RTL8188F: + if (interface_type == RTW_USB) + addr_offset = EEPROM_MAC_ADDR_8188FU; + else if (interface_type == RTW_SDIO) + addr_offset = EEPROM_MAC_ADDR_8188FS; + break; +#endif +#ifdef CONFIG_RTL8812A + case RTL8812: + if (interface_type == RTW_USB) + addr_offset = EEPROM_MAC_ADDR_8812AU; + else if (interface_type == RTW_PCIE) + addr_offset = EEPROM_MAC_ADDR_8812AE; + break; +#endif +#ifdef CONFIG_RTL8821A + case RTL8821: + if (interface_type == RTW_USB) + addr_offset = EEPROM_MAC_ADDR_8821AU; + else if (interface_type == RTW_SDIO) + addr_offset = EEPROM_MAC_ADDR_8821AS; + else if (interface_type == RTW_PCIE) + addr_offset = EEPROM_MAC_ADDR_8821AE; + break; +#endif +#ifdef CONFIG_RTL8192E + case RTL8192E: + if (interface_type == RTW_USB) + addr_offset = EEPROM_MAC_ADDR_8192EU; + else if (interface_type == RTW_SDIO) + addr_offset = EEPROM_MAC_ADDR_8192ES; + else if (interface_type == RTW_PCIE) + addr_offset = EEPROM_MAC_ADDR_8192EE; + break; +#endif +#ifdef CONFIG_RTL8814A + case RTL8814A: + if (interface_type == RTW_USB) + addr_offset = EEPROM_MAC_ADDR_8814AU; + else if (interface_type == RTW_PCIE) + addr_offset = EEPROM_MAC_ADDR_8814AE; + break; +#endif + } + + if (addr_offset == -1) { + DBG_871X_LEVEL(_drv_err_, "%s: unknown combination - chip_type:%u, interface:%u\n" + , __func__, rtw_get_chip_type(adapter), rtw_get_intf_type(adapter)); + } + + return addr_offset; +} + +int Hal_GetPhyEfuseMACAddr(PADAPTER padapter, u8 *mac_addr) +{ + int ret = _FAIL; + int addr_offset; + + addr_offset = hal_efuse_macaddr_offset(padapter); + if (addr_offset == -1) + goto exit; + + ret = rtw_efuse_map_read(padapter, addr_offset, ETH_ALEN, mac_addr); + +exit: + return ret; +} + +#ifdef CONFIG_EFUSE_CONFIG_FILE +u32 Hal_readPGDataFromConfigFile(PADAPTER padapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); + u32 ret; + + ret = rtw_read_efuse_from_file(EFUSE_MAP_PATH, hal_data->efuse_eeprom_data); + hal_data->efuse_file_status = ((ret == _FAIL) ? EFUSE_FILE_FAILED : EFUSE_FILE_LOADED); + + return ret; +} + +u32 Hal_ReadMACAddrFromFile(PADAPTER padapter, u8 *mac_addr) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); + u32 ret = _FAIL; + + if (rtw_read_macaddr_from_file(WIFIMAC_PATH, mac_addr) == _SUCCESS + && rtw_check_invalid_mac_address(mac_addr, _TRUE) == _FALSE + ) { + hal_data->macaddr_file_status = MACADDR_FILE_LOADED; + ret = _SUCCESS; + } else { + hal_data->macaddr_file_status = MACADDR_FILE_FAILED; + } + + return ret; +} +#endif /* CONFIG_EFUSE_CONFIG_FILE */ + +int hal_config_macaddr(_adapter *adapter, bool autoload_fail) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + u8 addr[ETH_ALEN]; + int addr_offset = hal_efuse_macaddr_offset(adapter); + u8 *hw_addr = NULL; + int ret = _SUCCESS; + + if (autoload_fail) + goto bypass_hw_pg; + + if (addr_offset != -1) + hw_addr = &hal_data->efuse_eeprom_data[addr_offset]; + +#ifdef CONFIG_EFUSE_CONFIG_FILE + /* if the hw_addr is written by efuse file, set to NULL */ + if (hal_data->efuse_file_status == EFUSE_FILE_LOADED) + hw_addr = NULL; +#endif + + if (!hw_addr) { + /* try getting hw pg data */ + if (Hal_GetPhyEfuseMACAddr(adapter, addr) == _SUCCESS) + hw_addr = addr; + } + + /* check hw pg data */ + if (hw_addr && rtw_check_invalid_mac_address(hw_addr, _TRUE) == _FALSE) { + _rtw_memcpy(hal_data->EEPROMMACAddr, hw_addr, ETH_ALEN); + goto exit; + } + +bypass_hw_pg: + +#ifdef CONFIG_EFUSE_CONFIG_FILE + /* check wifi mac file */ + if (Hal_ReadMACAddrFromFile(adapter, addr) == _SUCCESS) { + _rtw_memcpy(hal_data->EEPROMMACAddr, addr, ETH_ALEN); + goto exit; + } +#endif + + _rtw_memset(hal_data->EEPROMMACAddr, 0, ETH_ALEN); + ret = _FAIL; + +exit: + return ret; +} + +#ifdef CONFIG_RF_POWER_TRIM +u32 Array_kfreemap[] = { +0x08,0xe, +0x06,0xc, +0x04,0xa, +0x02,0x8, +0x00,0x6, +0x03,0x4, +0x05,0x2, +0x07,0x0, +0x09,0x0, +0x0c,0x0, +}; + +void rtw_bb_rf_gain_offset(_adapter *padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct registry_priv *registry_par = &padapter->registrypriv; + struct kfree_data_t *kfree_data = &pHalData->kfree_data; + u8 value = pHalData->EEPROMRFGainOffset; + u8 tmp = 0x3e; + u32 res, i = 0; + u4Byte ArrayLen = sizeof(Array_kfreemap)/sizeof(u32); + pu4Byte Array = Array_kfreemap; + u4Byte v1 = 0, v2 = 0, GainValue = 0, target = 0; + + if (registry_par->RegPwrTrimEnable == 2) { + DBG_871X("Registry kfree default force disable.\n"); + return; + } + +#if defined(CONFIG_RTL8723B) + if (value & BIT4 || (registry_par->RegPwrTrimEnable == 1)) { + DBG_871X("Offset RF Gain.\n"); + DBG_871X("Offset RF Gain. pHalData->EEPROMRFGainVal=0x%x\n",pHalData->EEPROMRFGainVal); + + if(pHalData->EEPROMRFGainVal != 0xff){ + + if(pHalData->ant_path == ODM_RF_PATH_A) { + GainValue=(pHalData->EEPROMRFGainVal & 0x0f); + + } else { + GainValue=(pHalData->EEPROMRFGainVal & 0xf0)>>4; + } + DBG_871X("Ant PATH_%d GainValue Offset = 0x%x\n",(pHalData->ant_path == ODM_RF_PATH_A) ? (ODM_RF_PATH_A) : (ODM_RF_PATH_B),GainValue); + + for (i = 0; i < ArrayLen; i += 2 ) + { + //DBG_871X("ArrayLen in =%d ,Array 1 =0x%x ,Array2 =0x%x \n",i,Array[i],Array[i]+1); + v1 = Array[i]; + v2 = Array[i+1]; + if ( v1 == GainValue ) { + DBG_871X("Offset RF Gain. got v1 =0x%x ,v2 =0x%x \n",v1,v2); + target=v2; + break; + } + } + DBG_871X("pHalData->EEPROMRFGainVal=0x%x ,Gain offset Target Value=0x%x\n",pHalData->EEPROMRFGainVal,target); + + res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff); + DBG_871X("Offset RF Gain. before reg 0x7f=0x%08x\n",res); + PHY_SetRFReg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, BIT18|BIT17|BIT16|BIT15, target); + res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff); + + DBG_871X("Offset RF Gain. After reg 0x7f=0x%08x\n",res); + + }else { + + DBG_871X("Offset RF Gain. pHalData->EEPROMRFGainVal=0x%x != 0xff, didn't run Kfree\n",pHalData->EEPROMRFGainVal); + } + } else { + DBG_871X("Using the default RF gain.\n"); + } + +#elif defined(CONFIG_RTL8188E) + if (value & BIT4 || (registry_par->RegPwrTrimEnable == 1)) { + DBG_871X("8188ES Offset RF Gain.\n"); + DBG_871X("8188ES Offset RF Gain. EEPROMRFGainVal=0x%x\n", + pHalData->EEPROMRFGainVal); + + if (pHalData->EEPROMRFGainVal != 0xff) { + res = rtw_hal_read_rfreg(padapter, RF_PATH_A, + REG_RF_BB_GAIN_OFFSET, 0xffffffff); + + DBG_871X("Offset RF Gain. reg 0x55=0x%x\n",res); + res &= 0xfff87fff; + + res |= (pHalData->EEPROMRFGainVal & 0x0f) << 15; + DBG_871X("Offset RF Gain. res=0x%x\n",res); + + rtw_hal_write_rfreg(padapter, RF_PATH_A, + REG_RF_BB_GAIN_OFFSET, + RF_GAIN_OFFSET_MASK, res); + } else { + DBG_871X("Offset RF Gain. EEPROMRFGainVal=0x%x == 0xff, didn't run Kfree\n", + pHalData->EEPROMRFGainVal); + } + } else { + DBG_871X("Using the default RF gain.\n"); + } +#else + /* TODO: call this when channel switch */ + if (kfree_data->flag & KFREE_FLAG_ON) + rtw_rf_apply_tx_gain_offset(padapter, 6); /* input ch6 to select BB_GAIN_2G */ +#endif + +} +#endif /*CONFIG_RF_POWER_TRIM */ + +bool kfree_data_is_bb_gain_empty(struct kfree_data_t *data) +{ +#ifdef CONFIG_RF_POWER_TRIM + int i, j; + + for (i = 0; i < BB_GAIN_NUM; i++) + for (j = 0; j < RF_PATH_MAX; j++) + if (data->bb_gain[i][j] != 0) + return 0; +#endif + return 1; +} + +#ifdef CONFIG_USB_RX_AGGREGATION +void rtw_set_usb_agg_by_mode_normal(_adapter *padapter, u8 cur_wireless_mode) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + if(cur_wireless_mode < WIRELESS_11_24N + && cur_wireless_mode > 0) //ABG mode + { +#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER + u32 remainder = 0; + u8 quotient = 0; + + remainder = MAX_RECVBUF_SZ % (4*1024); + quotient = (u8)(MAX_RECVBUF_SZ >> 12); + + if (quotient > 5) { + pHalData->RegAcUsbDmaSize = 0x6; + pHalData->RegAcUsbDmaTime = 0x10; + } else { + if (remainder >= 2048) { + pHalData->RegAcUsbDmaSize = quotient; + pHalData->RegAcUsbDmaTime = 0x10; + } else { + pHalData->RegAcUsbDmaSize = (quotient-1); + pHalData->RegAcUsbDmaTime = 0x10; + } + } +#else /* !CONFIG_PREALLOC_RX_SKB_BUFFER */ + if(0x6 != pHalData->RegAcUsbDmaSize || 0x10 !=pHalData->RegAcUsbDmaTime) + { + pHalData->RegAcUsbDmaSize = 0x6; + pHalData->RegAcUsbDmaTime = 0x10; + rtw_write16(padapter, REG_RXDMA_AGG_PG_TH, + pHalData->RegAcUsbDmaSize | (pHalData->RegAcUsbDmaTime<<8)); + } +#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */ + + } + else if(cur_wireless_mode >= WIRELESS_11_24N + && cur_wireless_mode <= WIRELESS_MODE_MAX)//N AC mode + { +#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER + u32 remainder = 0; + u8 quotient = 0; + + remainder = MAX_RECVBUF_SZ % (4*1024); + quotient = (u8)(MAX_RECVBUF_SZ >> 12); + + if (quotient > 5) { + pHalData->RegAcUsbDmaSize = 0x5; + pHalData->RegAcUsbDmaTime = 0x20; + } else { + if (remainder >= 2048) { + pHalData->RegAcUsbDmaSize = quotient; + pHalData->RegAcUsbDmaTime = 0x10; + } else { + pHalData->RegAcUsbDmaSize = (quotient-1); + pHalData->RegAcUsbDmaTime = 0x10; + } + } +#else /* !CONFIG_PREALLOC_RX_SKB_BUFFER */ + if(0x5 != pHalData->RegAcUsbDmaSize || 0x20 !=pHalData->RegAcUsbDmaTime) + { + pHalData->RegAcUsbDmaSize = 0x5; + pHalData->RegAcUsbDmaTime = 0x20; + rtw_write16(padapter, REG_RXDMA_AGG_PG_TH, + pHalData->RegAcUsbDmaSize | (pHalData->RegAcUsbDmaTime<<8)); + } +#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */ + + } + else + { + /* DBG_871X("%s: Unknow wireless mode(0x%x)\n",__func__,padapter->mlmeextpriv.cur_wireless_mode); */ + } +} + +void rtw_set_usb_agg_by_mode_customer(_adapter *padapter, u8 cur_wireless_mode, u8 UsbDmaSize, u8 Legacy_UsbDmaSize) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + if (cur_wireless_mode < WIRELESS_11_24N + && cur_wireless_mode > 0) { /* ABG mode */ + if (Legacy_UsbDmaSize != pHalData->RegAcUsbDmaSize + || 0x10 != pHalData->RegAcUsbDmaTime) { + pHalData->RegAcUsbDmaSize = Legacy_UsbDmaSize; + pHalData->RegAcUsbDmaTime = 0x10; + rtw_write16(padapter, REG_RXDMA_AGG_PG_TH, + pHalData->RegAcUsbDmaSize | (pHalData->RegAcUsbDmaTime<<8)); + } + } else if (cur_wireless_mode >= WIRELESS_11_24N + && cur_wireless_mode <= WIRELESS_MODE_MAX) { /* N AC mode */ + if (UsbDmaSize != pHalData->RegAcUsbDmaSize + || 0x20 != pHalData->RegAcUsbDmaTime) { + pHalData->RegAcUsbDmaSize = UsbDmaSize; + pHalData->RegAcUsbDmaTime = 0x20; + rtw_write16(padapter, REG_RXDMA_AGG_PG_TH, + pHalData->RegAcUsbDmaSize | (pHalData->RegAcUsbDmaTime<<8)); + } + } else { + /* DBG_871X("%s: Unknown wireless mode(0x%x)\n",__func__,padapter->mlmeextpriv.cur_wireless_mode); */ + } +} + +void rtw_set_usb_agg_by_mode(_adapter *padapter, u8 cur_wireless_mode) +{ +#ifdef CONFIG_PLATFORM_NOVATEK_NT72668 + rtw_set_usb_agg_by_mode_customer(padapter, cur_wireless_mode, 0x3, 0x3); + return; +#endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */ + + rtw_set_usb_agg_by_mode_normal(padapter, cur_wireless_mode); +} +#endif //CONFIG_USB_RX_AGGREGATION + +//To avoid RX affect TX throughput +void dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeextpriv = &(padapter->mlmeextpriv); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8 cur_wireless_mode = pmlmeextpriv->cur_wireless_mode; +#ifdef CONFIG_CONCURRENT_MODE + struct mlme_ext_priv *pbuddymlmeextpriv = &(padapter->pbuddy_adapter->mlmeextpriv); +#endif //CONFIG_CONCURRENT_MODE + +#ifdef CONFIG_USB_RX_AGGREGATION + if(IS_HARDWARE_TYPE_8821U(padapter) )//|| IS_HARDWARE_TYPE_8192EU(padapter)) + { + //This AGG_PH_TH only for UsbRxAggMode == USB_RX_AGG_USB + if((pHalData->UsbRxAggMode == USB_RX_AGG_USB) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE)) + { + if(pdvobjpriv->traffic_stat.cur_tx_tp > 2 && pdvobjpriv->traffic_stat.cur_rx_tp < 30) + rtw_write16(padapter , REG_RXDMA_AGG_PG_TH , 0x1010); + else if (pdvobjpriv->traffic_stat.last_tx_bytes > 220000 && pdvobjpriv->traffic_stat.cur_rx_tp < 30) + rtw_write16(padapter , REG_RXDMA_AGG_PG_TH , 0x1006); + else + rtw_write16(padapter, REG_RXDMA_AGG_PG_TH,0x2005); //dmc agg th 20K + + //DBG_871X("TX_TP=%u, RX_TP=%u \n", pdvobjpriv->traffic_stat.cur_tx_tp, pdvobjpriv->traffic_stat.cur_rx_tp); + } + } + else if(IS_HARDWARE_TYPE_8812(padapter)) + { +#ifdef CONFIG_CONCURRENT_MODE + if(rtw_linked_check(padapter) == _TRUE && rtw_linked_check(padapter->pbuddy_adapter) == _TRUE) + { + if(pbuddymlmeextpriv->cur_wireless_mode >= pmlmeextpriv->cur_wireless_mode) + cur_wireless_mode = pbuddymlmeextpriv->cur_wireless_mode; + else + cur_wireless_mode = pmlmeextpriv->cur_wireless_mode; + + rtw_set_usb_agg_by_mode(padapter,cur_wireless_mode); + } + else if (rtw_linked_check(padapter) == _TRUE && rtw_linked_check(padapter->pbuddy_adapter) == _FALSE) + { + rtw_set_usb_agg_by_mode(padapter,cur_wireless_mode); + } +#else //!CONFIG_CONCURRENT_MODE + rtw_set_usb_agg_by_mode(padapter,cur_wireless_mode); +#endif //CONFIG_CONCURRENT_MODE +#ifdef CONFIG_PLATFORM_NOVATEK_NT72668 + } else { + rtw_set_usb_agg_by_mode(padapter, cur_wireless_mode); +#endif /* CONFIG_PLATFORM_NOVATEK_NT72668 */ + } +#endif +} + +//bus-agg check for SoftAP mode +inline u8 rtw_hal_busagg_qsel_check(_adapter *padapter,u8 pre_qsel,u8 next_qsel) +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u8 chk_rst = _SUCCESS; + + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + return chk_rst; + + //if((pre_qsel == 0xFF)||(next_qsel== 0xFF)) + // return chk_rst; + + if( ((pre_qsel == QSLT_HIGH)||((next_qsel== QSLT_HIGH))) + && (pre_qsel != next_qsel )){ + //DBG_871X("### bus-agg break cause of qsel misatch, pre_qsel=0x%02x,next_qsel=0x%02x ###\n", + // pre_qsel,next_qsel); + chk_rst = _FAIL; + } + return chk_rst; +} + +/* + * Description: + * dump_TX_FIFO: This is only used to dump TX_FIFO for debug WoW mode offload + * contant. + * + * Input: + * adapter: adapter pointer. + * page_num: The max. page number that user want to dump. + * page_size: page size of each page. eg. 128 bytes, 256 bytes, 512byte. + */ +void dump_TX_FIFO(_adapter* padapter, u8 page_num, u16 page_size){ + + int i; + u8 val = 0; + u8 base = 0; + u32 addr = 0; + u32 count = (page_size / 8); + + if (page_num <= 0) { + DBG_871X("!!%s: incorrect input page_num paramter!\n", __func__); + return; + } + + if (page_size < 128 || page_size > 512) { + DBG_871X("!!%s: incorrect input page_size paramter!\n", __func__); + return; + } + + DBG_871X("+%s+\n", __func__); + val = rtw_read8(padapter, 0x106); + rtw_write8(padapter, 0x106, 0x69); + DBG_871X("0x106: 0x%02x\n", val); + base = rtw_read8(padapter, 0x209); + DBG_871X("0x209: 0x%02x\n", base); + + addr = ((base) * page_size)/8; + for (i = 0 ; i < page_num * count ; i+=2) { + rtw_write32(padapter, 0x140, addr + i); + printk(" %08x %08x ", rtw_read32(padapter, 0x144), rtw_read32(padapter, 0x148)); + rtw_write32(padapter, 0x140, addr + i + 1); + printk(" %08x %08x \n", rtw_read32(padapter, 0x144), rtw_read32(padapter, 0x148)); + } +} + +#ifdef CONFIG_GPIO_API +u8 rtw_hal_get_gpio(_adapter* adapter, u8 gpio_num) +{ + u8 value; + u8 direction; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter); + + rtw_ps_deny(adapter, PS_DENY_IOCTL); + + DBG_871X("rf_pwrstate=0x%02x\n", pwrpriv->rf_pwrstate); + LeaveAllPowerSaveModeDirect(adapter); + + /* Read GPIO Direction */ + direction = (rtw_read8(adapter,REG_GPIO_PIN_CTRL + 2) & BIT(gpio_num)) >> gpio_num; + + /* According the direction to read register value */ + if( direction ) + value = (rtw_read8(adapter, REG_GPIO_PIN_CTRL + 1)& BIT(gpio_num)) >> gpio_num; + else + value = (rtw_read8(adapter, REG_GPIO_PIN_CTRL)& BIT(gpio_num)) >> gpio_num; + + rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL); + DBG_871X("%s direction=%d value=%d\n",__FUNCTION__,direction,value); + + return value; +} + +int rtw_hal_set_gpio_output_value(_adapter* adapter, u8 gpio_num, bool isHigh) +{ + u8 direction = 0; + u8 res = -1; + if (IS_HARDWARE_TYPE_8188E(adapter)){ + /* Check GPIO is 4~7 */ + if( gpio_num > 7 || gpio_num < 4) + { + DBG_871X("%s The gpio number does not included 4~7.\n",__FUNCTION__); + return -1; + } + } + + rtw_ps_deny(adapter, PS_DENY_IOCTL); + + LeaveAllPowerSaveModeDirect(adapter); + + /* Read GPIO direction */ + direction = (rtw_read8(adapter,REG_GPIO_PIN_CTRL + 2) & BIT(gpio_num)) >> gpio_num; + + /* If GPIO is output direction, setting value. */ + if( direction ) + { + if(isHigh) + rtw_write8(adapter, REG_GPIO_PIN_CTRL + 1, rtw_read8(adapter, REG_GPIO_PIN_CTRL + 1) | BIT(gpio_num)); + else + rtw_write8(adapter, REG_GPIO_PIN_CTRL + 1, rtw_read8(adapter, REG_GPIO_PIN_CTRL + 1) & ~BIT(gpio_num)); + + DBG_871X("%s Set gpio %x[%d]=%d\n",__FUNCTION__,REG_GPIO_PIN_CTRL+1,gpio_num,isHigh ); + res = 0; + } + else + { + DBG_871X("%s The gpio is input,not be set!\n",__FUNCTION__); + res = -1; + } + + rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL); + return res; +} + +int rtw_hal_config_gpio(_adapter* adapter, u8 gpio_num, bool isOutput) +{ + if (IS_HARDWARE_TYPE_8188E(adapter)){ + if( gpio_num > 7 || gpio_num < 4) + { + DBG_871X("%s The gpio number does not included 4~7.\n",__FUNCTION__); + return -1; + } + } + + DBG_871X("%s gpio_num =%d direction=%d\n",__FUNCTION__,gpio_num,isOutput); + + rtw_ps_deny(adapter, PS_DENY_IOCTL); + + LeaveAllPowerSaveModeDirect(adapter); + + if( isOutput ) + { + rtw_write8(adapter, REG_GPIO_PIN_CTRL + 2, rtw_read8(adapter, REG_GPIO_PIN_CTRL + 2) | BIT(gpio_num)); + } + else + { + rtw_write8(adapter, REG_GPIO_PIN_CTRL + 2, rtw_read8(adapter, REG_GPIO_PIN_CTRL + 2) & ~BIT(gpio_num)); + } + + rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL); + + return 0; +} +int rtw_hal_register_gpio_interrupt(_adapter* adapter, int gpio_num, void(*callback)(u8 level)) +{ + u8 value; + u8 direction; + PHAL_DATA_TYPE phal = GET_HAL_DATA(adapter); + + if (IS_HARDWARE_TYPE_8188E(adapter)){ + if(gpio_num > 7 || gpio_num < 4) + { + DBG_871X_LEVEL(_drv_always_, "%s The gpio number does not included 4~7.\n",__FUNCTION__); + return -1; + } + } + + rtw_ps_deny(adapter, PS_DENY_IOCTL); + + LeaveAllPowerSaveModeDirect(adapter); + + /* Read GPIO direction */ + direction = (rtw_read8(adapter,REG_GPIO_PIN_CTRL + 2) & BIT(gpio_num)) >> gpio_num; + if(direction){ + DBG_871X_LEVEL(_drv_always_, "%s Can't register output gpio as interrupt.\n",__FUNCTION__); + return -1; + } + + /* Config GPIO Mode */ + rtw_write8(adapter, REG_GPIO_PIN_CTRL + 3, rtw_read8(adapter, REG_GPIO_PIN_CTRL + 3) | BIT(gpio_num)); + + /* Register GPIO interrupt handler*/ + adapter->gpiointpriv.callback[gpio_num] = callback; + + /* Set GPIO interrupt mode, 0:positive edge, 1:negative edge */ + value = rtw_read8(adapter, REG_GPIO_PIN_CTRL) & BIT(gpio_num); + adapter->gpiointpriv.interrupt_mode = rtw_read8(adapter, REG_HSIMR + 2)^value; + rtw_write8(adapter, REG_GPIO_INTM, adapter->gpiointpriv.interrupt_mode); + + /* Enable GPIO interrupt */ + adapter->gpiointpriv.interrupt_enable_mask = rtw_read8(adapter, REG_HSIMR + 2) | BIT(gpio_num); + rtw_write8(adapter, REG_HSIMR + 2, adapter->gpiointpriv.interrupt_enable_mask); + + rtw_hal_update_hisr_hsisr_ind(adapter, 1); + + rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL); + + return 0; +} +int rtw_hal_disable_gpio_interrupt(_adapter* adapter, int gpio_num) +{ + u8 value; + u8 direction; + PHAL_DATA_TYPE phal = GET_HAL_DATA(adapter); + + if (IS_HARDWARE_TYPE_8188E(adapter)){ + if(gpio_num > 7 || gpio_num < 4) + { + DBG_871X("%s The gpio number does not included 4~7.\n",__FUNCTION__); + return -1; + } + } + + rtw_ps_deny(adapter, PS_DENY_IOCTL); + + LeaveAllPowerSaveModeDirect(adapter); + + /* Config GPIO Mode */ + rtw_write8(adapter, REG_GPIO_PIN_CTRL + 3, rtw_read8(adapter, REG_GPIO_PIN_CTRL + 3) &~ BIT(gpio_num)); + + /* Unregister GPIO interrupt handler*/ + adapter->gpiointpriv.callback[gpio_num] = NULL; + + /* Reset GPIO interrupt mode, 0:positive edge, 1:negative edge */ + adapter->gpiointpriv.interrupt_mode = rtw_read8(adapter, REG_GPIO_INTM) &~ BIT(gpio_num); + rtw_write8(adapter, REG_GPIO_INTM, 0x00); + + /* Disable GPIO interrupt */ + adapter->gpiointpriv.interrupt_enable_mask = rtw_read8(adapter, REG_HSIMR + 2) &~ BIT(gpio_num); + rtw_write8(adapter, REG_HSIMR + 2, adapter->gpiointpriv.interrupt_enable_mask); + + if(!adapter->gpiointpriv.interrupt_enable_mask) + rtw_hal_update_hisr_hsisr_ind(adapter, 0); + + rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL); + + return 0; +} +#endif + +s8 rtw_hal_ch_sw_iqk_info_search(_adapter* padapter, u8 central_chnl, u8 bw_mode) { + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8 i; + + for (i = 0; i < MAX_IQK_INFO_BACKUP_CHNL_NUM; i++) { + if ((pHalData->iqk_reg_backup[i].central_chnl != 0)) { + if ((pHalData->iqk_reg_backup[i].central_chnl == central_chnl) + && (pHalData->iqk_reg_backup[i].bw_mode == bw_mode)) { + return i; + } + } + } + + return -1; +} + +void rtw_hal_ch_sw_iqk_info_backup(_adapter* padapter) { + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + s8 res; + u8 i; + + /* If it's an existed record, overwrite it */ + res = rtw_hal_ch_sw_iqk_info_search(padapter, pHalData->CurrentChannel, pHalData->CurrentChannelBW); + if ((res >= 0) && (res < MAX_IQK_INFO_BACKUP_CHNL_NUM)) { + rtw_hal_set_hwreg(padapter, HW_VAR_CH_SW_IQK_INFO_BACKUP, (u8*)&(pHalData->iqk_reg_backup[res])); + return; + } + + /* Search for the empty record to use */ + for (i = 0; i < MAX_IQK_INFO_BACKUP_CHNL_NUM; i++) { + if (pHalData->iqk_reg_backup[i].central_chnl == 0) { + rtw_hal_set_hwreg(padapter, HW_VAR_CH_SW_IQK_INFO_BACKUP, (u8*)&(pHalData->iqk_reg_backup[i])); + return; + } + } + + /* Else, overwrite the oldest record */ + for (i = 1; i < MAX_IQK_INFO_BACKUP_CHNL_NUM; i++) { + _rtw_memcpy(&(pHalData->iqk_reg_backup[i - 1]), &(pHalData->iqk_reg_backup[i]), sizeof(struct hal_iqk_reg_backup)); + } + rtw_hal_set_hwreg(padapter, HW_VAR_CH_SW_IQK_INFO_BACKUP, (u8*)&(pHalData->iqk_reg_backup[MAX_IQK_INFO_BACKUP_CHNL_NUM - 1])); +} + +void rtw_hal_ch_sw_iqk_info_restore(_adapter* padapter, u8 ch_sw_use_case) { + rtw_hal_set_hwreg(padapter, HW_VAR_CH_SW_IQK_INFO_RESTORE, &ch_sw_use_case); +} + +void rtw_dump_mac_rx_counters(_adapter* padapter,struct dbg_rx_counter *rx_counter) +{ + u32 mac_cck_ok=0, mac_ofdm_ok=0, mac_ht_ok=0, mac_vht_ok=0; + u32 mac_cck_err=0, mac_ofdm_err=0, mac_ht_err=0, mac_vht_err=0; + u32 mac_cck_fa=0, mac_ofdm_fa=0, mac_ht_fa=0; + u32 DropPacket=0; + + if(!rx_counter){ + rtw_warn_on(1); + return; + } + + PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28|BIT29|BIT30|BIT31, 0x3); + mac_cck_ok = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);// [15:0] + PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28|BIT29|BIT30|BIT31, 0x0); + mac_ofdm_ok = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);// [15:0] + PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28|BIT29|BIT30|BIT31, 0x6); + mac_ht_ok = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);// [15:0] + mac_vht_ok = 0; + if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) { + PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28|BIT29|BIT30|BIT31, 0x0); + PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT26, 0x1); + mac_vht_ok = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);// [15:0] + } + + PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28|BIT29|BIT30|BIT31, 0x4); + mac_cck_err = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);// [15:0] + PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28|BIT29|BIT30|BIT31, 0x1); + mac_ofdm_err = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);// [15:0] + PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28|BIT29|BIT30|BIT31, 0x7); + mac_ht_err = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);// [15:0] + mac_vht_err = 0; + if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) { + PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28|BIT29|BIT30|BIT31, 0x1); + PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT26, 0x1); + mac_vht_err = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);// [15:0] + } + + PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28|BIT29|BIT30|BIT31, 0x5); + mac_cck_fa = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);// [15:0] + PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28|BIT29|BIT30|BIT31, 0x2); + mac_ofdm_fa = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);// [15:0] + PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT28|BIT29|BIT30|BIT31, 0x9); + mac_ht_fa = PHY_QueryMacReg(padapter, REG_RXERR_RPT, bMaskLWord);// [15:0] + + //Mac_DropPacket + rtw_write32(padapter, REG_RXERR_RPT, (rtw_read32(padapter, REG_RXERR_RPT)& 0x0FFFFFFF)| Mac_DropPacket); + DropPacket = rtw_read32(padapter, REG_RXERR_RPT)& 0x0000FFFF; + + rx_counter->rx_pkt_ok = mac_cck_ok+mac_ofdm_ok+mac_ht_ok+mac_vht_ok; + rx_counter->rx_pkt_crc_error = mac_cck_err+mac_ofdm_err+mac_ht_err+mac_vht_err; + rx_counter->rx_cck_fa = mac_cck_fa; + rx_counter->rx_ofdm_fa = mac_ofdm_fa; + rx_counter->rx_ht_fa = mac_ht_fa; + rx_counter->rx_pkt_drop = DropPacket; +} +void rtw_reset_mac_rx_counters(_adapter* padapter) +{ + + if (IS_HARDWARE_TYPE_8703B(padapter) || IS_HARDWARE_TYPE_8188F(padapter)) + PHY_SetMacReg(padapter, 0x608, BIT19, 0x1); /* If no packet rx, MaxRx clock be gating ,BIT_DISGCLK bit19 set 1 for fix*/ + + //reset mac counter + PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT27, 0x1); + PHY_SetMacReg(padapter, REG_RXERR_RPT, BIT27, 0x0); +} + +void rtw_dump_phy_rx_counters(_adapter* padapter,struct dbg_rx_counter *rx_counter) +{ + u32 cckok=0,cckcrc=0,ofdmok=0,ofdmcrc=0,htok=0,htcrc=0,OFDM_FA=0,CCK_FA=0,vht_ok=0,vht_err=0; + if(!rx_counter){ + rtw_warn_on(1); + return; + } + if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)){ + cckok = PHY_QueryBBReg(padapter, 0xF04, 0x3FFF); // [13:0] + ofdmok = PHY_QueryBBReg(padapter, 0xF14, 0x3FFF); // [13:0] + htok = PHY_QueryBBReg(padapter, 0xF10, 0x3FFF); // [13:0] + vht_ok = PHY_QueryBBReg(padapter, 0xF0C, 0x3FFF); // [13:0] + cckcrc = PHY_QueryBBReg(padapter, 0xF04, 0x3FFF0000); // [29:16] + ofdmcrc = PHY_QueryBBReg(padapter, 0xF14, 0x3FFF0000); // [29:16] + htcrc = PHY_QueryBBReg(padapter, 0xF10, 0x3FFF0000); // [29:16] + vht_err = PHY_QueryBBReg(padapter, 0xF0C, 0x3FFF0000); // [29:16] + CCK_FA = PHY_QueryBBReg(padapter, 0xA5C, bMaskLWord); + OFDM_FA = PHY_QueryBBReg(padapter, 0xF48, bMaskLWord); + } + else + { + cckok = PHY_QueryBBReg(padapter, 0xF88, bMaskDWord); + ofdmok = PHY_QueryBBReg(padapter, 0xF94, bMaskLWord); + htok = PHY_QueryBBReg(padapter, 0xF90, bMaskLWord); + vht_ok = 0; + cckcrc = PHY_QueryBBReg(padapter, 0xF84, bMaskDWord); + ofdmcrc = PHY_QueryBBReg(padapter, 0xF94, bMaskHWord); + htcrc = PHY_QueryBBReg(padapter, 0xF90, bMaskHWord); + vht_err = 0; + OFDM_FA = PHY_QueryBBReg(padapter, 0xCF0, bMaskLWord) + PHY_QueryBBReg(padapter, 0xCF2, bMaskLWord) + + PHY_QueryBBReg(padapter, 0xDA2, bMaskLWord) + PHY_QueryBBReg(padapter, 0xDA4, bMaskLWord) + + PHY_QueryBBReg(padapter, 0xDA6, bMaskLWord) + PHY_QueryBBReg(padapter, 0xDA8, bMaskLWord); + + CCK_FA=(rtw_read8(padapter, 0xA5B )<<8 ) | (rtw_read8(padapter, 0xA5C)); + } + + rx_counter->rx_pkt_ok = cckok+ofdmok+htok+vht_ok; + rx_counter->rx_pkt_crc_error = cckcrc+ofdmcrc+htcrc+vht_err; + rx_counter->rx_ofdm_fa = OFDM_FA; + rx_counter->rx_cck_fa = CCK_FA; + +} + +void rtw_reset_phy_trx_ok_counters(_adapter *padapter) +{ + if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) { + PHY_SetBBReg(padapter, 0xB58, BIT0, 0x1); + PHY_SetBBReg(padapter, 0xB58, BIT0, 0x0); + } +} +void rtw_reset_phy_rx_counters(_adapter *padapter) +{ + //reset phy counter + if (IS_HARDWARE_TYPE_JAGUAR(padapter) || IS_HARDWARE_TYPE_JAGUAR2(padapter)) + { + rtw_reset_phy_trx_ok_counters(padapter); + + PHY_SetBBReg(padapter, 0x9A4, BIT17, 0x1);//reset OFDA FA counter + PHY_SetBBReg(padapter, 0x9A4, BIT17, 0x0); + + PHY_SetBBReg(padapter, 0xA2C, BIT15, 0x0);//reset CCK FA counter + PHY_SetBBReg(padapter, 0xA2C, BIT15, 0x1); + } + else + { + PHY_SetBBReg(padapter, 0xF14, BIT16, 0x1); + rtw_msleep_os(10); + PHY_SetBBReg(padapter, 0xF14, BIT16, 0x0); + + PHY_SetBBReg(padapter, 0xD00, BIT27, 0x1);//reset OFDA FA counter + PHY_SetBBReg(padapter, 0xC0C, BIT31, 0x1);//reset OFDA FA counter + PHY_SetBBReg(padapter, 0xD00, BIT27, 0x0); + PHY_SetBBReg(padapter, 0xC0C, BIT31, 0x0); + + PHY_SetBBReg(padapter, 0xA2C, BIT15, 0x0);//reset CCK FA counter + PHY_SetBBReg(padapter, 0xA2C, BIT15, 0x1); + } +} +#ifdef DBG_RX_COUNTER_DUMP +void rtw_dump_drv_rx_counters(_adapter* padapter,struct dbg_rx_counter *rx_counter) +{ + struct recv_priv *precvpriv = &padapter->recvpriv; + if(!rx_counter){ + rtw_warn_on(1); + return; + } + rx_counter->rx_pkt_ok = padapter->drv_rx_cnt_ok; + rx_counter->rx_pkt_crc_error = padapter->drv_rx_cnt_crcerror; + rx_counter->rx_pkt_drop = precvpriv->rx_drop - padapter->drv_rx_cnt_drop; +} +void rtw_reset_drv_rx_counters(_adapter* padapter) +{ + struct recv_priv *precvpriv = &padapter->recvpriv; + padapter->drv_rx_cnt_ok = 0; + padapter->drv_rx_cnt_crcerror = 0; + padapter->drv_rx_cnt_drop = precvpriv->rx_drop; +} +void rtw_dump_phy_rxcnts_preprocess(_adapter* padapter,u8 rx_cnt_mode) +{ + u8 initialgain; + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); + + if((!(padapter->dump_rx_cnt_mode& DUMP_PHY_RX_COUNTER)) && (rx_cnt_mode & DUMP_PHY_RX_COUNTER)) + { + /*initialgain = pDigTable->CurIGValue;*/ + rtw_hal_get_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, NULL); + DBG_871X("%s CurIGValue:0x%02x\n",__FUNCTION__,initialgain); + rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, _FALSE); + /*disable dynamic functions, such as high power, DIG*/ + rtw_phydm_ability_backup(padapter); + rtw_phydm_func_clr(padapter, (ODM_BB_DIG|ODM_BB_FA_CNT)); + } + else if((padapter->dump_rx_cnt_mode& DUMP_PHY_RX_COUNTER) &&(!(rx_cnt_mode & DUMP_PHY_RX_COUNTER ))) + { + //turn on phy-dynamic functions + rtw_phydm_ability_restore(padapter); + initialgain = 0xff; //restore RX GAIN + rtw_hal_set_odm_var(padapter, HAL_ODM_INITIAL_GAIN, &initialgain, _FALSE); + + } +} + +void rtw_dump_rx_counters(_adapter* padapter) +{ + struct dbg_rx_counter rx_counter; + + if( padapter->dump_rx_cnt_mode & DUMP_DRV_RX_COUNTER ){ + _rtw_memset(&rx_counter,0,sizeof(struct dbg_rx_counter)); + rtw_dump_drv_rx_counters(padapter,&rx_counter); + DBG_871X( "Drv Received packet OK:%d CRC error:%d Drop Packets: %d\n", + rx_counter.rx_pkt_ok,rx_counter.rx_pkt_crc_error,rx_counter.rx_pkt_drop); + rtw_reset_drv_rx_counters(padapter); + } + + if( padapter->dump_rx_cnt_mode & DUMP_MAC_RX_COUNTER ){ + _rtw_memset(&rx_counter,0,sizeof(struct dbg_rx_counter)); + rtw_dump_mac_rx_counters(padapter,&rx_counter); + DBG_871X( "Mac Received packet OK:%d CRC error:%d FA Counter: %d Drop Packets: %d\n", + rx_counter.rx_pkt_ok,rx_counter.rx_pkt_crc_error, + rx_counter.rx_cck_fa+rx_counter.rx_ofdm_fa+rx_counter.rx_ht_fa, + rx_counter.rx_pkt_drop); + rtw_reset_mac_rx_counters(padapter); + } + + if(padapter->dump_rx_cnt_mode & DUMP_PHY_RX_COUNTER ){ + _rtw_memset(&rx_counter,0,sizeof(struct dbg_rx_counter)); + rtw_dump_phy_rx_counters(padapter,&rx_counter); + //DBG_871X("%s: OFDM_FA =%d\n", __FUNCTION__, rx_counter.rx_ofdm_fa); + //DBG_871X("%s: CCK_FA =%d\n", __FUNCTION__, rx_counter.rx_cck_fa); + DBG_871X("Phy Received packet OK:%d CRC error:%d FA Counter: %d\n",rx_counter.rx_pkt_ok,rx_counter.rx_pkt_crc_error, + rx_counter.rx_ofdm_fa+rx_counter.rx_cck_fa); + rtw_reset_phy_rx_counters(padapter); + } +} +#endif +void rtw_get_noise(_adapter* padapter) +{ +#if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct noise_info info; + if(rtw_linked_check(padapter)){ + info.bPauseDIG = _TRUE; + info.IGIValue = 0x1e; + info.max_time = 100;//ms + info.chan = pmlmeext->cur_channel ;//rtw_get_oper_ch(padapter); + rtw_ps_deny(padapter, PS_DENY_IOCTL); + LeaveAllPowerSaveModeDirect(padapter); + + rtw_hal_set_odm_var(padapter, HAL_ODM_NOISE_MONITOR,&info, _FALSE); + //ODM_InbandNoise_Monitor(podmpriv,_TRUE,0x20,100); + rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL); + rtw_hal_get_odm_var(padapter, HAL_ODM_NOISE_MONITOR,&(info.chan), &(padapter->recvpriv.noise)); + #ifdef DBG_NOISE_MONITOR + DBG_871X("chan:%d,noise_level:%d\n",info.chan,padapter->recvpriv.noise); + #endif + } +#endif + +} + +u8 rtw_get_current_tx_rate(_adapter *padapter, u8 macid) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + u8 rate_id = 0; + +#if (RATE_ADAPTIVE_SUPPORT == 1) + rate_id = ODM_RA_GetDecisionRate_8188E(pDM_Odm, macid); +#else + rate_id = (pRA_Table->link_tx_rate[macid]) & 0x7f; +#endif + + return rate_id; + +} + +#ifdef CONFIG_FW_C2H_DEBUG + +/* C2H RX package original is 128. +if enable CONFIG_FW_C2H_DEBUG, it should increase to 256. + C2H FW debug message: + without aggregate: + {C2H_CmdID,Seq,SubID,Len,Content[0~n]} + Content[0~n]={'a','b','c',...,'z','\n'} + with aggregate: + {C2H_CmdID,Seq,SubID,Len,Content[0~n]} + Content[0~n]={'a','b','c',...,'z','\n',Extend C2H pkt 2...} + Extend C2H pkt 2={C2H CmdID,Seq,SubID,Len,Content = {'a','b','c',...,'z','\n'}} + Author: Isaac */ + +void Debug_FwC2H(PADAPTER padapter, u8 *pdata, u8 len) +{ + int i = 0; + int cnt = 0, total_length = 0; + u8 buf[128] = {0}; + u8 more_data = _FALSE; + u8 *nextdata = NULL; + u8 test = 0; + + u8 data_len; + u8 seq_no; + + nextdata = pdata; + do { + data_len = *(nextdata + 1); + seq_no = *(nextdata + 2); + + for (i = 0 ; i < data_len - 2 ; i++) { + cnt += sprintf((buf+cnt), "%c", nextdata[3 + i]); + + if (nextdata[3 + i] == 0x0a && nextdata[4 + i] == 0xff) + more_data = _TRUE; + else if (nextdata[3 + i] == 0x0a && nextdata[4 + i] != 0xff) + more_data = _FALSE; + } + + DBG_871X("[RTKFW, SEQ=%d]: %s", seq_no, buf); + data_len += 3; + total_length += data_len; + + if (more_data == _TRUE) { + _rtw_memset(buf, '\0', 128); + cnt = 0; + nextdata = (pdata + total_length); + } + } while (more_data == _TRUE); +} +#endif /*CONFIG_FW_C2H_DEBUG*/ +void update_IOT_info(_adapter *padapter) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + switch (pmlmeinfo->assoc_AP_vendor) + { + case HT_IOT_PEER_MARVELL: + pmlmeinfo->turboMode_cts2self = 1; + pmlmeinfo->turboMode_rtsen = 0; + break; + + case HT_IOT_PEER_RALINK: + pmlmeinfo->turboMode_cts2self = 0; + pmlmeinfo->turboMode_rtsen = 1; + //disable high power + rtw_phydm_func_clr(padapter, ODM_BB_DYNAMIC_TXPWR); + break; + case HT_IOT_PEER_REALTEK: + //rtw_write16(padapter, 0x4cc, 0xffff); + //rtw_write16(padapter, 0x546, 0x01c0); + //disable high power + rtw_phydm_func_clr(padapter, ODM_BB_DYNAMIC_TXPWR); + break; + default: + pmlmeinfo->turboMode_cts2self = 0; + pmlmeinfo->turboMode_rtsen = 1; + break; + } + +} +#ifdef CONFIG_AUTO_CHNL_SEL_NHM +void rtw_acs_start(_adapter *padapter, bool bStart) +{ + if (_TRUE == bStart) { + ACS_OP acs_op = ACS_INIT; + + rtw_hal_set_odm_var(padapter, HAL_ODM_AUTO_CHNL_SEL, &acs_op, _TRUE); + rtw_set_acs_channel(padapter, 0); + SET_ACS_STATE(padapter, ACS_ENABLE); + } else { + SET_ACS_STATE(padapter, ACS_DISABLE); + #ifdef DBG_AUTO_CHNL_SEL_NHM + if (1) { + u8 best_24g_ch = 0; + u8 best_5g_ch = 0; + + rtw_hal_get_odm_var(padapter, HAL_ODM_AUTO_CHNL_SEL, &(best_24g_ch), &(best_5g_ch)); + DBG_871X("[ACS-"ADPT_FMT"] Best 2.4G CH:%u\n", ADPT_ARG(padapter), best_24g_ch); + DBG_871X("[ACS-"ADPT_FMT"] Best 5G CH:%u\n", ADPT_ARG(padapter), best_5g_ch); + } + #endif + } +} +#endif + +/* TODO: merge with phydm, see odm_SetCrystalCap() */ +void hal_set_crystal_cap(_adapter *adapter, u8 crystal_cap) +{ + crystal_cap = crystal_cap & 0x3F; + + switch (rtw_get_chip_type(adapter)) { +#if defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) + case RTL8188E: + case RTL8188F: + /* write 0x24[16:11] = 0x24[22:17] = CrystalCap */ + PHY_SetBBReg(adapter, REG_AFE_XTAL_CTRL, 0x007FF800, (crystal_cap | (crystal_cap << 6))); + break; +#endif +#if defined(CONFIG_RTL8812A) + case RTL8812: + /* write 0x2C[30:25] = 0x2C[24:19] = CrystalCap */ + PHY_SetBBReg(adapter, REG_MAC_PHY_CTRL, 0x7FF80000, (crystal_cap | (crystal_cap << 6))); + break; +#endif +#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8192E) + case RTL8723B: + case RTL8703B: + case RTL8821: + case RTL8192E: + /* write 0x2C[23:18] = 0x2C[17:12] = CrystalCap */ + PHY_SetBBReg(adapter, REG_MAC_PHY_CTRL, 0x00FFF000, (crystal_cap | (crystal_cap << 6))); + break; +#endif +#if defined(CONFIG_RTL8814A) + case RTL8814A: + /* write 0x2C[26:21] = 0x2C[20:15] = CrystalCap*/ + PHY_SetBBReg(adapter, REG_MAC_PHY_CTRL, 0x07FF8000, (crystal_cap | (crystal_cap << 6))); + break; +#endif +#if defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) + case RTL8821B: + case RTL8822B: + /* write 0x28[6:1] = 0x24[30:25] = CrystalCap */ + crystal_cap = crystal_cap & 0x3F; + PHY_SetBBReg(adapter, REG_AFE_XTAL_CTRL, 0x7E000000, crystal_cap); + PHY_SetBBReg(adapter, REG_AFE_PLL_CTRL, 0x7E, crystal_cap); + break; +#endif + default: + rtw_warn_on(1); + } +} + +int hal_spec_init(_adapter *adapter) +{ + u8 interface_type = 0; + int ret = _SUCCESS; + + interface_type = rtw_get_intf_type(adapter); + + switch (rtw_get_chip_type(adapter)) { +#ifdef CONFIG_RTL8723B + case RTL8723B: + init_hal_spec_8723b(adapter); + break; +#endif +#ifdef CONFIG_RTL8703B + case RTL8703B: + init_hal_spec_8703b(adapter); + break; +#endif +#ifdef CONFIG_RTL8188E + case RTL8188E: + init_hal_spec_8188e(adapter); + break; +#endif +#ifdef CONFIG_RTL8188F + case RTL8188F: + init_hal_spec_8188f(adapter); + break; +#endif +#ifdef CONFIG_RTL8812A + case RTL8812: + init_hal_spec_8812a(adapter); + break; +#endif +#ifdef CONFIG_RTL8821A + case RTL8821: + init_hal_spec_8821a(adapter); + break; +#endif +#ifdef CONFIG_RTL8192E + case RTL8192E: + init_hal_spec_8192e(adapter); + break; +#endif +#ifdef CONFIG_RTL8814A + case RTL8814A: + init_hal_spec_8814a(adapter); + break; +#endif + default: + DBG_871X_LEVEL(_drv_err_, "%s: unknown chip_type:%u\n" + , __func__, rtw_get_chip_type(adapter)); + ret = _FAIL; + break; + } + + return ret; +} + +static const char * const _band_cap_str[] = { + /* BIT0 */"2G", + /* BIT1 */"5G", +}; + +static const char * const _bw_cap_str[] = { + /* BIT0 */"5M", + /* BIT1 */"10M", + /* BIT2 */"20M", + /* BIT3 */"40M", + /* BIT4 */"80M", + /* BIT5 */"160M", + /* BIT6 */"80_80M", +}; + +static const char * const _proto_cap_str[] = { + /* BIT0 */"b", + /* BIT1 */"g", + /* BIT2 */"n", + /* BIT3 */"ac", +}; + +static const char * const _wl_func_str[] = { + /* BIT0 */"P2P", + /* BIT1 */"MIRACAST", + /* BIT2 */"TDLS", + /* BIT3 */"FTM", +}; + +void dump_hal_spec(void *sel, _adapter *adapter) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + int i; + + DBG_871X_SEL_NL(sel, "macid_num:%u\n", hal_spec->macid_num); + DBG_871X_SEL_NL(sel, "sec_cap:0x%02x\n", hal_spec->sec_cap); + DBG_871X_SEL_NL(sel, "sec_cam_ent_num:%u\n", hal_spec->sec_cam_ent_num); + DBG_871X_SEL_NL(sel, "nss_num:%u\n", hal_spec->nss_num); + + DBG_871X_SEL_NL(sel, "band_cap:"); + for (i = 0; i < BAND_CAP_BIT_NUM; i++) { + if (((hal_spec->band_cap) >> i) & BIT0 && _band_cap_str[i]) + DBG_871X_SEL(sel, "%s ", _band_cap_str[i]); + } + DBG_871X_SEL(sel, "\n"); + + DBG_871X_SEL_NL(sel, "bw_cap:"); + for (i = 0; i < BW_CAP_BIT_NUM; i++) { + if (((hal_spec->bw_cap) >> i) & BIT0 && _bw_cap_str[i]) + DBG_871X_SEL(sel, "%s ", _bw_cap_str[i]); + } + DBG_871X_SEL(sel, "\n"); + + DBG_871X_SEL_NL(sel, "proto_cap:"); + for (i = 0; i < PROTO_CAP_BIT_NUM; i++) { + if (((hal_spec->proto_cap) >> i) & BIT0 && _proto_cap_str[i]) + DBG_871X_SEL(sel, "%s ", _proto_cap_str[i]); + } + DBG_871X_SEL(sel, "\n"); + + DBG_871X_SEL_NL(sel, "wl_func:"); + for (i = 0; i < WL_FUNC_BIT_NUM; i++) { + if (((hal_spec->wl_func) >> i) & BIT0 && _wl_func_str[i]) + DBG_871X_SEL(sel, "%s ", _wl_func_str[i]); + } + DBG_871X_SEL(sel, "\n"); +} + +inline bool hal_chk_band_cap(_adapter *adapter, u8 cap) +{ + return (GET_HAL_SPEC(adapter)->band_cap & cap); +} + +inline bool hal_chk_bw_cap(_adapter *adapter, u8 cap) +{ + return (GET_HAL_SPEC(adapter)->bw_cap & cap); +} + +inline bool hal_chk_proto_cap(_adapter *adapter, u8 cap) +{ + return (GET_HAL_SPEC(adapter)->proto_cap & cap); +} + +inline bool hal_chk_wl_func(_adapter *adapter, u8 func) +{ + return (GET_HAL_SPEC(adapter)->wl_func & func); +} + +inline bool hal_is_band_support(_adapter *adapter, u8 band) +{ + return (GET_HAL_SPEC(adapter)->band_cap & band_to_band_cap(band)); +} + +inline bool hal_is_bw_support(_adapter *adapter, u8 bw) +{ + return (GET_HAL_SPEC(adapter)->bw_cap & ch_width_to_bw_cap(bw)); +} + +inline bool hal_is_wireless_mode_support(_adapter *adapter, u8 mode) +{ + u8 proto_cap = GET_HAL_SPEC(adapter)->proto_cap; + + if (mode == WIRELESS_11B) + if ((proto_cap & PROTO_CAP_11B) && hal_chk_band_cap(adapter, BAND_CAP_2G)) + return 1; + + if (mode == WIRELESS_11G) + if ((proto_cap & PROTO_CAP_11G) && hal_chk_band_cap(adapter, BAND_CAP_2G)) + return 1; + + if (mode == WIRELESS_11A) + if ((proto_cap & PROTO_CAP_11G) && hal_chk_band_cap(adapter, BAND_CAP_5G)) + return 1; + + if (mode == WIRELESS_11_24N) + if ((proto_cap & PROTO_CAP_11N) && hal_chk_band_cap(adapter, BAND_CAP_2G)) + return 1; + + if (mode == WIRELESS_11_5N) + if ((proto_cap & PROTO_CAP_11N) && hal_chk_band_cap(adapter, BAND_CAP_5G)) + return 1; + + if (mode == WIRELESS_11AC) + if ((proto_cap & PROTO_CAP_11AC) && hal_chk_band_cap(adapter, BAND_CAP_5G)) + return 1; + + return 0; +} + +/* +* hal_largest_bw - starting from in_bw, get largest bw supported by HAL +* @adapter: +* @in_bw: starting bw, value of CHANNEL_WIDTH +* +* Returns: value of CHANNEL_WIDTH +*/ +u8 hal_largest_bw(_adapter *adapter, u8 in_bw) +{ + for (; in_bw > CHANNEL_WIDTH_20; in_bw--) { + if (hal_is_bw_support(adapter, in_bw)) + break; + } + + if (!hal_is_bw_support(adapter, in_bw)) + rtw_warn_on(1); + + return in_bw; +} + +#ifdef CONFIG_ANTENNA_DIVERSITY +u8 rtw_hal_antdiv_before_linked(_adapter *padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8 cur_ant, change_ant; + + if (!pHalData->AntDivCfg) + return _FALSE; + + if (pHalData->sw_antdiv_bl_state == 0) { + pHalData->sw_antdiv_bl_state = 1; + + rtw_hal_get_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &cur_ant, NULL); + change_ant = (cur_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT; + + return rtw_antenna_select_cmd(padapter, change_ant, _FALSE); + } + + pHalData->sw_antdiv_bl_state = 0; + return _FALSE; +} + +void rtw_hal_antdiv_rssi_compared(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + if (pHalData->AntDivCfg) { + /*DBG_871X("update_network=> org-RSSI(%d), new-RSSI(%d)\n", dst->Rssi, src->Rssi);*/ + /*select optimum_antenna for before linked =>For antenna diversity*/ + if (dst->Rssi >= src->Rssi) {/*keep org parameter*/ + src->Rssi = dst->Rssi; + src->PhyInfo.Optimum_antenna = dst->PhyInfo.Optimum_antenna; + } + } +} +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_com_c2h.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_com_c2h.h new file mode 100644 index 000000000..a9b1fe7d7 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_com_c2h.h @@ -0,0 +1,76 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __COMMON_C2H_H__ +#define __COMMON_C2H_H__ + +typedef enum _C2H_EVT { + C2H_DBG = 0x00, + C2H_LB = 0x01, + C2H_TXBF = 0x02, + C2H_CCX_TX_RPT = 0x03, + C2H_BT_INFO = 0x09, + C2H_BT_MP_INFO = 0x0B, + C2H_RA_RPT = 0x0C, + C2H_RA_PARA_RPT = 0x0E, + C2H_FW_CHNL_SWITCH_COMPLETE = 0x10, + C2H_IQK_FINISH = 0x11, + C2H_MAILBOX_STATUS = 0x15, + C2H_P2P_RPORT = 0x16, + C2H_MAC_HIDDEN_RPT = 0x19, + C2H_MAC_HIDDEN_RPT_2 = 0x1A, + C2H_BCN_EARLY_RPT = 0x1E, + C2H_BT_SCOREBOARD_STATUS = 0x20, + C2H_DEFEATURE_DBG = 0x22, + C2H_CUSTOMER_STR_RPT = 0x24, + C2H_CUSTOMER_STR_RPT_2 = 0x25, + C2H_DEFEATURE_RSVD = 0xFD, + C2H_EXTEND = 0xff, +} C2H_EVT; + +typedef enum _EXTEND_C2H_EVT { + EXTEND_C2H_DBG_PRINT = 0 +} EXTEND_C2H_EVT; + +/* C2H_MAC_HIDDEN_RPT, 0x19 */ +#define MAC_HIDDEN_RPT_LEN 8 +int c2h_mac_hidden_rpt_hdl(_adapter *adapter, u8 *data, u8 len); + +/* C2H_MAC_HIDDEN_RPT_2, 0x1A */ +#define MAC_HIDDEN_RPT_2_LEN 5 +int c2h_mac_hidden_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len); + +int hal_read_mac_hidden_rpt(_adapter *adapter); + +/* C2H_DEFEATURE_DBG, 0x22 */ +#define DEFEATURE_DBG_LEN 1 +int c2h_defeature_dbg_hdl(_adapter *adapter, u8 *data, u8 len); + +#ifdef CONFIG_RTW_CUSTOMER_STR +/* C2H_CUSTOMER_STR_RPT, 0x24 */ +#define CUSTOMER_STR_RPT_LEN 8 +int c2h_customer_str_rpt_hdl(_adapter *adapter, u8 *data, u8 len); + +/* C2H_CUSTOMER_STR_RPT_2, 0x25 */ +#define CUSTOMER_STR_RPT_2_LEN 8 +int c2h_customer_str_rpt_2_hdl(_adapter *adapter, u8 *data, u8 len); +#endif /* CONFIG_RTW_CUSTOMER_STR */ + +#endif /* __COMMON_C2H_H__ */ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_com_phycfg.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_com_phycfg.c new file mode 100644 index 000000000..9bb536806 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_com_phycfg.c @@ -0,0 +1,4303 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _HAL_COM_PHYCFG_C_ + +#include +#include + +/* +* rtw_regsty_get_target_tx_power - +* +* Return dBm or -1 for undefined +*/ +s8 rtw_regsty_get_target_tx_power( + IN PADAPTER Adapter, + IN u8 Band, + IN u8 RfPath, + IN RATE_SECTION RateSection + ) +{ + struct registry_priv *regsty = adapter_to_regsty(Adapter); + s8 value = 0; + + if (RfPath > RF_PATH_D) { + DBG_871X_LEVEL(_drv_always_, "%s invalid RfPath:%d\n", __func__, RfPath); + return -1; + } + + if (Band != BAND_ON_2_4G + #ifdef CONFIG_IEEE80211_BAND_5GHZ + && Band != BAND_ON_5G + #endif + ) { + DBG_871X_LEVEL(_drv_always_, "%s invalid Band:%d\n", __func__, Band); + return -1; + } + + if (RateSection >= RATE_SECTION_NUM + #ifdef CONFIG_IEEE80211_BAND_5GHZ + || (Band == BAND_ON_5G && RateSection == CCK) + #endif + ) { + DBG_871X_LEVEL(_drv_always_, "%s invalid RateSection:%d in %sG, RfPath:%d\n", __func__ + , RateSection, (Band == BAND_ON_2_4G) ? "2.4" : "5", RfPath); + return -1; + } + + if (Band == BAND_ON_2_4G) + value = regsty->target_tx_pwr_2g[RfPath][RateSection]; +#ifdef CONFIG_IEEE80211_BAND_5GHZ + else /* BAND_ON_5G */ + value = regsty->target_tx_pwr_5g[RfPath][RateSection - 1]; +#endif + + return value; +} + +bool rtw_regsty_chk_target_tx_power_valid(_adapter *adapter) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + int path, tx_num, band, rs; + s8 target; + + for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) { + if (!hal_is_band_support(adapter, band)) + continue; + + for (path = 0; path < RF_PATH_MAX; path++) { + if (path >= hal_data->NumTotalRFPath) + break; + + for (rs = 0; rs < RATE_SECTION_NUM; rs++) { + tx_num = rate_section_to_tx_num(rs); + if (tx_num >= hal_spec->nss_num) + continue; + + if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs)) + continue; + + if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) + continue; + + target = rtw_regsty_get_target_tx_power(adapter, band, path, rs); + if (target == -1) + return _FALSE; + } + } + } + + return _TRUE; +} + +/* +* PHY_GetTxPowerByRateBase - +* +* Return 2 times of dBm +*/ +u8 +PHY_GetTxPowerByRateBase( + IN PADAPTER Adapter, + IN u8 Band, + IN u8 RfPath, + IN u8 TxNum, + IN RATE_SECTION RateSection + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u8 value = 0; + + if (RfPath > RF_PATH_D) { + DBG_871X_LEVEL(_drv_always_, "%s invalid RfPath:%d\n", __func__, RfPath); + return 0; + } + + if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) { + DBG_871X_LEVEL(_drv_always_, "%s invalid Band:%d\n", __func__, Band); + return 0; + } + + if (RateSection >= RATE_SECTION_NUM + || (Band == BAND_ON_5G && RateSection == CCK) + ) { + DBG_871X_LEVEL(_drv_always_, "%s invalid RateSection:%d in %sG, RfPath:%d, TxNum:%d\n", __func__ + , RateSection, (Band == BAND_ON_2_4G) ? "2.4" : "5", RfPath, TxNum); + return 0; + } + + if (Band == BAND_ON_2_4G) + value = pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][RateSection]; + else /* BAND_ON_5G */ + value = pHalData->TxPwrByRateBase5G[RfPath][TxNum][RateSection - 1]; + + return value; +} + +VOID +phy_SetTxPowerByRateBase( + IN PADAPTER Adapter, + IN u8 Band, + IN u8 RfPath, + IN RATE_SECTION RateSection, + IN u8 TxNum, + IN u8 Value + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + if (RfPath > RF_PATH_D) { + DBG_871X_LEVEL(_drv_always_, "%s invalid RfPath:%d\n", __func__, RfPath); + return; + } + + if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) { + DBG_871X_LEVEL(_drv_always_, "%s invalid Band:%d\n", __func__, Band); + return; + } + + if (RateSection >= RATE_SECTION_NUM + || (Band == BAND_ON_5G && RateSection == CCK) + ) { + DBG_871X_LEVEL(_drv_always_, "%s invalid RateSection:%d in %sG, RfPath:%d, TxNum:%d\n", __func__ + , RateSection, (Band == BAND_ON_2_4G) ? "2.4" : "5", RfPath, TxNum); + return; + } + + if (Band == BAND_ON_2_4G) + pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][RateSection] = Value; + else /* BAND_ON_5G */ + pHalData->TxPwrByRateBase5G[RfPath][TxNum][RateSection - 1] = Value; +} + +/* +* phy_get_target_tx_power - +* +* Return 2 times of dBm +*/ +u8 phy_get_target_tx_power( + IN PADAPTER Adapter, + IN u8 Band, + IN u8 RfPath, + IN RATE_SECTION RateSection + ) +{ + struct registry_priv *regsty = adapter_to_regsty(Adapter); + s16 target_power; + + if (phy_is_tx_power_by_rate_needed(Adapter) == _FALSE && regsty->target_tx_pwr_valid == _TRUE) + target_power = 2 * rtw_regsty_get_target_tx_power(Adapter, Band, RfPath, RateSection); + else + target_power = PHY_GetTxPowerByRateBase(Adapter, Band, RfPath, rate_section_to_tx_num(RateSection), RateSection); + + return target_power; +} + +#ifdef TX_POWER_BY_RATE_OLD +VOID +phy_StoreTxPowerByRateBaseOld( + IN PADAPTER pAdapter + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA( pAdapter ); + u16 rawValue = 0; + u8 base = 0; + u8 path = 0; + + rawValue = ( u16 ) ( pHalData->MCSTxPowerLevelOriginalOffset[0][7] >> 8 ) & 0xFF; + base = ( rawValue >> 4 ) * 10 + ( rawValue & 0xF ); + phy_SetTxPowerByRateBase( pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, CCK, RF_1TX, base ); + + rawValue = ( u16 ) ( pHalData->MCSTxPowerLevelOriginalOffset[0][1] >> 24 ) & 0xFF; + base = ( rawValue >> 4 ) * 10 + ( rawValue & 0xF ); + phy_SetTxPowerByRateBase( pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, OFDM, RF_1TX, base ); + + rawValue = ( u16 ) ( pHalData->MCSTxPowerLevelOriginalOffset[0][3] >> 24 ) & 0xFF; + base = ( rawValue >> 4 ) * 10 + ( rawValue & 0xF ); + phy_SetTxPowerByRateBase( pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, HT_MCS0_MCS7, RF_1TX, base ); + + rawValue = ( u16 ) ( pHalData->MCSTxPowerLevelOriginalOffset[0][5] >> 24 ) & 0xFF; + base = ( rawValue >> 4) * 10 + ( rawValue & 0xF ); + phy_SetTxPowerByRateBase( pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, HT_MCS8_MCS15, RF_2TX, base ); + + rawValue = ( u16 ) ( pHalData->MCSTxPowerLevelOriginalOffset[0][7] & 0xFF ); + base = ( rawValue >> 4 ) * 10 + ( rawValue & 0xF ); + phy_SetTxPowerByRateBase( pAdapter, BAND_ON_2_4G, ODM_RF_PATH_B, CCK, RF_1TX, base ); + + rawValue = ( u16 ) ( pHalData->MCSTxPowerLevelOriginalOffset[0][9] >> 24 ) & 0xFF; + base = ( rawValue >> 4 ) * 10 + ( rawValue & 0xF ); + phy_SetTxPowerByRateBase( pAdapter, BAND_ON_2_4G, ODM_RF_PATH_B, OFDM, RF_1TX, base ); + + rawValue = ( u16 ) ( pHalData->MCSTxPowerLevelOriginalOffset[0][11] >> 24 ) & 0xFF; + base = ( rawValue >> 4 ) * 10 + ( rawValue & 0xF ); + phy_SetTxPowerByRateBase( pAdapter, BAND_ON_2_4G, ODM_RF_PATH_B, HT_MCS0_MCS7, RF_1TX, base ); + + rawValue = ( u16 ) ( pHalData->MCSTxPowerLevelOriginalOffset[0][13] >> 24 ) & 0xFF; + base = ( rawValue >> 4 ) * 10 + ( rawValue & 0xF ); + phy_SetTxPowerByRateBase( pAdapter, BAND_ON_2_4G, ODM_RF_PATH_B, HT_MCS8_MCS15, RF_2TX, base ); +} +#endif /* TX_POWER_BY_RATE_OLD */ + +VOID +phy_StoreTxPowerByRateBase( + IN PADAPTER pAdapter + ) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(pAdapter); + + u8 rate_sec_base[RATE_SECTION_NUM] = { + MGN_11M, + MGN_54M, + MGN_MCS7, + MGN_MCS15, + MGN_MCS23, + MGN_MCS31, + MGN_VHT1SS_MCS7, + MGN_VHT2SS_MCS7, + MGN_VHT3SS_MCS7, + MGN_VHT4SS_MCS7, + }; + + u8 band, path, rs, tx_num, base, index; + + for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) { + + for (path = RF_PATH_A; path < RF_PATH_MAX; path++) { + /* TODO: 8814A's NumTotalRFPath differs at probe(3) and up(4), need fixed + if (path >= hal_data->NumTotalRFPath) + break; + */ + + for (rs = 0; rs < RATE_SECTION_NUM; rs++) { + tx_num = rate_section_to_tx_num(rs); + if (tx_num >= hal_spec->nss_num) + continue; + + if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs)) + continue; + + base = _PHY_GetTxPowerByRate(pAdapter, band, path, tx_num, rate_sec_base[rs]); + phy_SetTxPowerByRateBase(pAdapter, band, path, rs, tx_num, base); + } + } + } +} + +#ifdef TX_POWER_BY_RATE_OLD +u8 +PHY_GetRateSectionIndexOfTxPowerByRate( + IN PADAPTER pAdapter, + IN u32 RegAddr, + IN u32 BitMask + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA( pAdapter ); + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + u8 index = 0; + + if ( pDM_Odm->PhyRegPgVersion == 0 ) + { + switch ( RegAddr ) + { + case rTxAGC_A_Rate18_06: index = 0; break; + case rTxAGC_A_Rate54_24: index = 1; break; + case rTxAGC_A_CCK1_Mcs32: index = 6; break; + case rTxAGC_B_CCK11_A_CCK2_11: + if ( BitMask == bMaskH3Bytes ) + index = 7; + else if ( BitMask == 0x000000ff ) + index = 15; + break; + + case rTxAGC_A_Mcs03_Mcs00: index = 2; break; + case rTxAGC_A_Mcs07_Mcs04: index = 3; break; + case rTxAGC_A_Mcs11_Mcs08: index = 4; break; + case rTxAGC_A_Mcs15_Mcs12: index = 5; break; + case rTxAGC_B_Rate18_06: index = 8; break; + case rTxAGC_B_Rate54_24: index = 9; break; + case rTxAGC_B_CCK1_55_Mcs32: index = 14; break; + case rTxAGC_B_Mcs03_Mcs00: index = 10; break; + case rTxAGC_B_Mcs07_Mcs04: index = 11; break; + case rTxAGC_B_Mcs11_Mcs08: index = 12; break; + case rTxAGC_B_Mcs15_Mcs12: index = 13; break; + default: + DBG_871X("Invalid RegAddr 0x3%x in PHY_GetRateSectionIndexOfTxPowerByRate()", RegAddr ); + break; + }; + } + + return index; +} +#endif /* TX_POWER_BY_RATE_OLD */ + +VOID +PHY_GetRateValuesOfTxPowerByRate( + IN PADAPTER pAdapter, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Value, + OUT u8 *Rate, + OUT s8 *PwrByRateVal, + OUT u8 *RateNum + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA( pAdapter ); + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + u8 index = 0, i = 0; + + switch ( RegAddr ) + { + case rTxAGC_A_Rate18_06: + case rTxAGC_B_Rate18_06: + Rate[0] = MGN_6M; + Rate[1] = MGN_9M; + Rate[2] = MGN_12M; + Rate[3] = MGN_18M; + for ( i = 0; i < 4; ++ i ) + { + PwrByRateVal[i] = ( s8 ) ( ( ( ( Value >> (i * 8 + 4) ) & 0xF ) ) * 10 + + ( ( Value >> (i * 8) ) & 0xF ) ); + } + *RateNum = 4; + break; + + case rTxAGC_A_Rate54_24: + case rTxAGC_B_Rate54_24: + Rate[0] = MGN_24M; + Rate[1] = MGN_36M; + Rate[2] = MGN_48M; + Rate[3] = MGN_54M; + for ( i = 0; i < 4; ++ i ) + { + PwrByRateVal[i] = ( s8 ) ( ( ( ( Value >> (i * 8 + 4) ) & 0xF ) ) * 10 + + ( ( Value >> (i * 8) ) & 0xF ) ); + } + *RateNum = 4; + break; + + case rTxAGC_A_CCK1_Mcs32: + Rate[0] = MGN_1M; + PwrByRateVal[0] = ( s8 ) ( ( ( ( Value >> (8 + 4) ) & 0xF ) ) * 10 + + ( ( Value >> 8 ) & 0xF ) ); + *RateNum = 1; + break; + + case rTxAGC_B_CCK11_A_CCK2_11: + if ( BitMask == 0xffffff00 ) + { + Rate[0] = MGN_2M; + Rate[1] = MGN_5_5M; + Rate[2] = MGN_11M; + for ( i = 1; i < 4; ++ i ) + { + PwrByRateVal[i - 1] = ( s8 ) ( ( ( ( Value >> (i * 8 + 4) ) & 0xF ) ) * 10 + + ( ( Value >> (i * 8) ) & 0xF ) ); + } + *RateNum = 3; + } + else if ( BitMask == 0x000000ff ) + { + Rate[0] = MGN_11M; + PwrByRateVal[0] = ( s8 ) ( ( ( ( Value >> 4 ) & 0xF ) ) * 10 + + ( Value & 0xF ) ); + *RateNum = 1; + } + break; + + case rTxAGC_A_Mcs03_Mcs00: + case rTxAGC_B_Mcs03_Mcs00: + Rate[0] = MGN_MCS0; + Rate[1] = MGN_MCS1; + Rate[2] = MGN_MCS2; + Rate[3] = MGN_MCS3; + for ( i = 0; i < 4; ++ i ) + { + PwrByRateVal[i] = ( s8 ) ( ( ( ( Value >> (i * 8 + 4) ) & 0xF ) ) * 10 + + ( ( Value >> (i * 8) ) & 0xF ) ); + } + *RateNum = 4; + break; + + case rTxAGC_A_Mcs07_Mcs04: + case rTxAGC_B_Mcs07_Mcs04: + Rate[0] = MGN_MCS4; + Rate[1] = MGN_MCS5; + Rate[2] = MGN_MCS6; + Rate[3] = MGN_MCS7; + for ( i = 0; i < 4; ++ i ) + { + PwrByRateVal[i] = ( s8 ) ( ( ( ( Value >> (i * 8 + 4) ) & 0xF ) ) * 10 + + ( ( Value >> (i * 8) ) & 0xF ) ); + } + *RateNum = 4; + break; + + case rTxAGC_A_Mcs11_Mcs08: + case rTxAGC_B_Mcs11_Mcs08: + Rate[0] = MGN_MCS8; + Rate[1] = MGN_MCS9; + Rate[2] = MGN_MCS10; + Rate[3] = MGN_MCS11; + for ( i = 0; i < 4; ++ i ) + { + PwrByRateVal[i] = ( s8 ) ( ( ( ( Value >> (i * 8 + 4) ) & 0xF ) ) * 10 + + ( ( Value >> (i * 8) ) & 0xF ) ); + } + *RateNum = 4; + break; + + case rTxAGC_A_Mcs15_Mcs12: + case rTxAGC_B_Mcs15_Mcs12: + Rate[0] = MGN_MCS12; + Rate[1] = MGN_MCS13; + Rate[2] = MGN_MCS14; + Rate[3] = MGN_MCS15; + for ( i = 0; i < 4; ++ i ) + { + PwrByRateVal[i] = ( s8 ) ( ( ( ( Value >> (i * 8 + 4) ) & 0xF ) ) * 10 + + ( ( Value >> (i * 8) ) & 0xF ) ); + } + *RateNum = 4; + + break; + + case rTxAGC_B_CCK1_55_Mcs32: + Rate[0] = MGN_1M; + Rate[1] = MGN_2M; + Rate[2] = MGN_5_5M; + for ( i = 1; i < 4; ++ i ) + { + PwrByRateVal[i - 1] = ( s8 ) ( ( ( ( Value >> ( i * 8 + 4) ) & 0xF ) ) * 10 + + ( ( Value >> ( i * 8) ) & 0xF ) ); + } + *RateNum = 3; + break; + + case 0xC20: + case 0xE20: + case 0x1820: + case 0x1a20: + Rate[0] = MGN_1M; + Rate[1] = MGN_2M; + Rate[2] = MGN_5_5M; + Rate[3] = MGN_11M; + for ( i = 0; i < 4; ++ i ) + { + PwrByRateVal[i] = ( s8 ) ( ( ( ( Value >> (i * 8 + 4) ) & 0xF ) ) * 10 + + ( ( Value >> (i * 8) ) & 0xF ) ); + } + *RateNum = 4; + break; + + case 0xC24: + case 0xE24: + case 0x1824: + case 0x1a24: + Rate[0] = MGN_6M; + Rate[1] = MGN_9M; + Rate[2] = MGN_12M; + Rate[3] = MGN_18M; + for ( i = 0; i < 4; ++ i ) + { + PwrByRateVal[i] = ( s8 ) ( ( ( ( Value >> (i * 8 + 4) ) & 0xF ) ) * 10 + + ( ( Value >> (i * 8) ) & 0xF ) ); + } + *RateNum = 4; + break; + + case 0xC28: + case 0xE28: + case 0x1828: + case 0x1a28: + Rate[0] = MGN_24M; + Rate[1] = MGN_36M; + Rate[2] = MGN_48M; + Rate[3] = MGN_54M; + for ( i = 0; i < 4; ++ i ) + { + PwrByRateVal[i] = ( s8 ) ( ( ( ( Value >> (i * 8 + 4) ) & 0xF ) ) * 10 + + ( ( Value >> (i * 8) ) & 0xF ) ); + } + *RateNum = 4; + break; + + case 0xC2C: + case 0xE2C: + case 0x182C: + case 0x1a2C: + Rate[0] = MGN_MCS0; + Rate[1] = MGN_MCS1; + Rate[2] = MGN_MCS2; + Rate[3] = MGN_MCS3; + for ( i = 0; i < 4; ++ i ) + { + PwrByRateVal[i] = ( s8 ) ( ( ( ( Value >> (i * 8 + 4) ) & 0xF ) ) * 10 + + ( ( Value >> (i * 8) ) & 0xF ) ); + } + *RateNum = 4; + break; + + case 0xC30: + case 0xE30: + case 0x1830: + case 0x1a30: + Rate[0] = MGN_MCS4; + Rate[1] = MGN_MCS5; + Rate[2] = MGN_MCS6; + Rate[3] = MGN_MCS7; + for ( i = 0; i < 4; ++ i ) + { + PwrByRateVal[i] = ( s8 ) ( ( ( ( Value >> (i * 8 + 4) ) & 0xF ) ) * 10 + + ( ( Value >> (i * 8) ) & 0xF ) ); + } + *RateNum = 4; + break; + + case 0xC34: + case 0xE34: + case 0x1834: + case 0x1a34: + Rate[0] = MGN_MCS8; + Rate[1] = MGN_MCS9; + Rate[2] = MGN_MCS10; + Rate[3] = MGN_MCS11; + for ( i = 0; i < 4; ++ i ) + { + PwrByRateVal[i] = ( s8 ) ( ( ( ( Value >> (i * 8 + 4) ) & 0xF ) ) * 10 + + ( ( Value >> (i * 8) ) & 0xF ) ); + } + *RateNum = 4; + break; + + case 0xC38: + case 0xE38: + case 0x1838: + case 0x1a38: + Rate[0] = MGN_MCS12; + Rate[1] = MGN_MCS13; + Rate[2] = MGN_MCS14; + Rate[3] = MGN_MCS15; + for ( i = 0; i < 4; ++ i ) + { + PwrByRateVal[i] = ( s8 ) ( ( ( ( Value >> (i * 8 + 4) ) & 0xF ) ) * 10 + + ( ( Value >> (i * 8) ) & 0xF ) ); + } + *RateNum = 4; + break; + + case 0xC3C: + case 0xE3C: + case 0x183C: + case 0x1a3C: + Rate[0] = MGN_VHT1SS_MCS0; + Rate[1] = MGN_VHT1SS_MCS1; + Rate[2] = MGN_VHT1SS_MCS2; + Rate[3] = MGN_VHT1SS_MCS3; + for ( i = 0; i < 4; ++ i ) + { + PwrByRateVal[i] = ( s8 ) ( ( ( ( Value >> (i * 8 + 4) ) & 0xF ) ) * 10 + + ( ( Value >> (i * 8) ) & 0xF ) ); + } + *RateNum = 4; + break; + + case 0xC40: + case 0xE40: + case 0x1840: + case 0x1a40: + Rate[0] = MGN_VHT1SS_MCS4; + Rate[1] = MGN_VHT1SS_MCS5; + Rate[2] = MGN_VHT1SS_MCS6; + Rate[3] = MGN_VHT1SS_MCS7; + for ( i = 0; i < 4; ++ i ) + { + PwrByRateVal[i] = ( s8 ) ( ( ( ( Value >> (i * 8 + 4) ) & 0xF ) ) * 10 + + ( ( Value >> (i * 8) ) & 0xF ) ); + } + *RateNum = 4; + break; + + case 0xC44: + case 0xE44: + case 0x1844: + case 0x1a44: + Rate[0] = MGN_VHT1SS_MCS8; + Rate[1] = MGN_VHT1SS_MCS9; + Rate[2] = MGN_VHT2SS_MCS0; + Rate[3] = MGN_VHT2SS_MCS1; + for ( i = 0; i < 4; ++ i ) + { + PwrByRateVal[i] = ( s8 ) ( ( ( ( Value >> (i * 8 + 4) ) & 0xF ) ) * 10 + + ( ( Value >> (i * 8) ) & 0xF ) ); + } + *RateNum = 4; + break; + + case 0xC48: + case 0xE48: + case 0x1848: + case 0x1a48: + Rate[0] = MGN_VHT2SS_MCS2; + Rate[1] = MGN_VHT2SS_MCS3; + Rate[2] = MGN_VHT2SS_MCS4; + Rate[3] = MGN_VHT2SS_MCS5; + for ( i = 0; i < 4; ++ i ) + { + PwrByRateVal[i] = ( s8 ) ( ( ( ( Value >> (i * 8 + 4) ) & 0xF ) ) * 10 + + ( ( Value >> (i * 8) ) & 0xF ) ); + } + *RateNum = 4; + break; + + case 0xC4C: + case 0xE4C: + case 0x184C: + case 0x1a4C: + Rate[0] = MGN_VHT2SS_MCS6; + Rate[1] = MGN_VHT2SS_MCS7; + Rate[2] = MGN_VHT2SS_MCS8; + Rate[3] = MGN_VHT2SS_MCS9; + for ( i = 0; i < 4; ++ i ) + { + PwrByRateVal[i] = ( s8 ) ( ( ( ( Value >> (i * 8 + 4) ) & 0xF ) ) * 10 + + ( ( Value >> (i * 8) ) & 0xF ) ); + } + *RateNum = 4; + break; + + case 0xCD8: + case 0xED8: + case 0x18D8: + case 0x1aD8: + Rate[0] = MGN_MCS16; + Rate[1] = MGN_MCS17; + Rate[2] = MGN_MCS18; + Rate[3] = MGN_MCS19; + for ( i = 0; i < 4; ++ i ) + { + PwrByRateVal[i] = ( s8 ) ( ( ( ( Value >> (i * 8 + 4) ) & 0xF ) ) * 10 + + ( ( Value >> (i * 8) ) & 0xF ) ); + } + *RateNum = 4; + break; + + case 0xCDC: + case 0xEDC: + case 0x18DC: + case 0x1aDC: + Rate[0] = MGN_MCS20; + Rate[1] = MGN_MCS21; + Rate[2] = MGN_MCS22; + Rate[3] = MGN_MCS23; + for ( i = 0; i < 4; ++ i ) + { + PwrByRateVal[i] = ( s8 ) ( ( ( ( Value >> (i * 8 + 4) ) & 0xF ) ) * 10 + + ( ( Value >> (i * 8) ) & 0xF ) ); + } + *RateNum = 4; + break; + + case 0xCE0: + case 0xEE0: + case 0x18E0: + case 0x1aE0: + Rate[0] = MGN_VHT3SS_MCS0; + Rate[1] = MGN_VHT3SS_MCS1; + Rate[2] = MGN_VHT3SS_MCS2; + Rate[3] = MGN_VHT3SS_MCS3; + for ( i = 0; i < 4; ++ i ) + { + PwrByRateVal[i] = ( s8 ) ( ( ( ( Value >> (i * 8 + 4) ) & 0xF ) ) * 10 + + ( ( Value >> (i * 8) ) & 0xF ) ); + } + *RateNum = 4; + break; + + case 0xCE4: + case 0xEE4: + case 0x18E4: + case 0x1aE4: + Rate[0] = MGN_VHT3SS_MCS4; + Rate[1] = MGN_VHT3SS_MCS5; + Rate[2] = MGN_VHT3SS_MCS6; + Rate[3] = MGN_VHT3SS_MCS7; + for ( i = 0; i < 4; ++ i ) + { + PwrByRateVal[i] = ( s8 ) ( ( ( ( Value >> (i * 8 + 4) ) & 0xF ) ) * 10 + + ( ( Value >> (i * 8) ) & 0xF ) ); + } + *RateNum = 4; + break; + + case 0xCE8: + case 0xEE8: + case 0x18E8: + case 0x1aE8: + Rate[0] = MGN_VHT3SS_MCS8; + Rate[1] = MGN_VHT3SS_MCS9; + for ( i = 0; i < 2; ++ i ) + { + PwrByRateVal[i] = ( s8 ) ( ( ( ( Value >> (i * 8 + 4) ) & 0xF ) ) * 10 + + ( ( Value >> (i * 8) ) & 0xF ) ); + } + *RateNum = 2; + break; + + default: + DBG_871X_LEVEL(_drv_always_, "Invalid RegAddr 0x%x in %s()\n", RegAddr, __func__); + break; + }; +} + +void +PHY_StoreTxPowerByRateNew( + IN PADAPTER pAdapter, + IN u32 Band, + IN u32 RfPath, + IN u32 TxNum, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Data + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + u8 i = 0, rates[4] = {0}, rateNum = 0; + s8 PwrByRateVal[4] = {0}; + + PHY_GetRateValuesOfTxPowerByRate(pAdapter, RegAddr, BitMask, Data, rates, PwrByRateVal, &rateNum); + + if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) { + DBG_871X_LEVEL(_drv_always_, "Invalid Band %d\n", Band); + return; + } + + if (RfPath > ODM_RF_PATH_D) { + DBG_871X_LEVEL(_drv_always_, "Invalid RfPath %d\n", RfPath); + return; + } + + if (TxNum > ODM_RF_PATH_D) { + DBG_871X_LEVEL(_drv_always_, "Invalid TxNum %d\n", TxNum); + return; + } + + for (i = 0; i < rateNum; ++i) { + u8 rate_idx = PHY_GetRateIndexOfTxPowerByRate(rates[i]); + + if (IS_1T_RATE(rates[i])) + pHalData->TxPwrByRateOffset[Band][RfPath][RF_1TX][rate_idx] = PwrByRateVal[i]; + else if (IS_2T_RATE(rates[i])) + pHalData->TxPwrByRateOffset[Band][RfPath][RF_2TX][rate_idx] = PwrByRateVal[i]; + else if (IS_3T_RATE(rates[i])) + pHalData->TxPwrByRateOffset[Band][RfPath][RF_3TX][rate_idx] = PwrByRateVal[i]; + else if (IS_4T_RATE(rates[i])) + pHalData->TxPwrByRateOffset[Band][RfPath][RF_4TX][rate_idx] = PwrByRateVal[i]; + else + rtw_warn_on(1); + } +} + +#ifdef TX_POWER_BY_RATE_OLD +void +PHY_StoreTxPowerByRateOld( + IN PADAPTER pAdapter, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Data + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + u8 index = PHY_GetRateSectionIndexOfTxPowerByRate( pAdapter, RegAddr, BitMask ); + + pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][index] = Data; + //DBG_871X("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n", pHalData->pwrGroupCnt, + // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0]); +} +#endif /* TX_POWER_BY_RATE_OLD */ + +VOID +PHY_InitTxPowerByRate( + IN PADAPTER pAdapter + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + u8 band = 0, rfPath = 0, TxNum = 0, rate = 0, i = 0, j = 0; + + if ( IS_HARDWARE_TYPE_8188E( pAdapter ) ) + { + for ( i = 0; i < MAX_PG_GROUP; ++i ) + for ( j = 0; j < 16; ++j ) + pHalData->MCSTxPowerLevelOriginalOffset[i][j] = 0; + } + else + { + for ( band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band ) + for ( rfPath = 0; rfPath < TX_PWR_BY_RATE_NUM_RF; ++rfPath ) + for ( TxNum = 0; TxNum < TX_PWR_BY_RATE_NUM_RF; ++TxNum ) + for ( rate = 0; rate < TX_PWR_BY_RATE_NUM_RATE; ++rate ) + pHalData->TxPwrByRateOffset[band][rfPath][TxNum][rate] = 0; + } +} + +VOID +PHY_StoreTxPowerByRate( + IN PADAPTER pAdapter, + IN u32 Band, + IN u32 RfPath, + IN u32 TxNum, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Data + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + + if ( pDM_Odm->PhyRegPgVersion > 0 ) + { + PHY_StoreTxPowerByRateNew( pAdapter, Band, RfPath, TxNum, RegAddr, BitMask, Data ); + } +#ifdef TX_POWER_BY_RATE_OLD + else if ( pDM_Odm->PhyRegPgVersion == 0 ) + { + PHY_StoreTxPowerByRateOld( pAdapter, RegAddr, BitMask, Data ); + + if ( RegAddr == rTxAGC_A_Mcs15_Mcs12 && pHalData->rf_type == RF_1T1R ) + pHalData->pwrGroupCnt++; + else if ( RegAddr == rTxAGC_B_Mcs15_Mcs12 && pHalData->rf_type != RF_1T1R ) + pHalData->pwrGroupCnt++; + } +#endif + else + DBG_871X("Invalid PHY_REG_PG.txt version %d\n", pDM_Odm->PhyRegPgVersion ); + +} + +#ifdef TX_POWER_BY_RATE_OLD +VOID +phy_ConvertTxPowerByRateByBase( + IN u32* pData, + IN u8 Start, + IN u8 End, + IN u8 BaseValue + ) +{ + s8 i = 0; + u8 TempValue = 0; + u32 TempData = 0; + + for ( i = 3; i >= 0; --i ) + { + if ( i >= Start && i <= End ) + { + // Get the exact value + TempValue = ( u8 ) ( *pData >> ( i * 8 ) ) & 0xF; + TempValue += ( ( u8 ) ( ( *pData >> ( i * 8 + 4 ) ) & 0xF ) ) * 10; + + // Change the value to a relative value + TempValue = ( TempValue > BaseValue ) ? TempValue - BaseValue : BaseValue - TempValue; + } + else + { + TempValue = ( u8 ) ( *pData >> ( i * 8 ) ) & 0xFF; + } + + TempData <<= 8; + TempData |= TempValue; + } + + *pData = TempData; +} + + +VOID +PHY_ConvertTxPowerByRateInDbmToRelativeValuesOld( + IN PADAPTER pAdapter + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA( pAdapter ); + u8 base = 0; + + //DBG_871X("===>PHY_ConvertTxPowerByRateInDbmToRelativeValuesOld()\n" ); + + // CCK + base = PHY_GetTxPowerByRateBase( pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, RF_1TX, CCK ); + phy_ConvertTxPowerByRateByBase( + &( pHalData->MCSTxPowerLevelOriginalOffset[0][6] ), 1, 1, base ); + phy_ConvertTxPowerByRateByBase( + &( pHalData->MCSTxPowerLevelOriginalOffset[0][7] ), 1, 3, base ); + + // OFDM + base = PHY_GetTxPowerByRateBase( pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, RF_1TX, OFDM ); + phy_ConvertTxPowerByRateByBase( + &( pHalData->MCSTxPowerLevelOriginalOffset[0][0] ), 0, 3, base ); + phy_ConvertTxPowerByRateByBase( + &( pHalData->MCSTxPowerLevelOriginalOffset[0][1] ), 0, 3, base ); + + // HT MCS0~7 + base = PHY_GetTxPowerByRateBase( pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, RF_1TX, HT_MCS0_MCS7 ); + phy_ConvertTxPowerByRateByBase( + &( pHalData->MCSTxPowerLevelOriginalOffset[0][2] ), 0, 3, base ); + phy_ConvertTxPowerByRateByBase( + &( pHalData->MCSTxPowerLevelOriginalOffset[0][3] ), 0, 3, base ); + + // HT MCS8~15 + base = PHY_GetTxPowerByRateBase( pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, RF_2TX, HT_MCS8_MCS15 ); + phy_ConvertTxPowerByRateByBase( + &( pHalData->MCSTxPowerLevelOriginalOffset[0][4] ), 0, 3, base ); + phy_ConvertTxPowerByRateByBase( + &( pHalData->MCSTxPowerLevelOriginalOffset[0][5] ), 0, 3, base ); + + // CCK + base = PHY_GetTxPowerByRateBase( pAdapter, BAND_ON_2_4G, ODM_RF_PATH_B, RF_1TX, CCK ); + phy_ConvertTxPowerByRateByBase( + &( pHalData->MCSTxPowerLevelOriginalOffset[0][14] ), 1, 3, base ); + phy_ConvertTxPowerByRateByBase( + &( pHalData->MCSTxPowerLevelOriginalOffset[0][15] ), 0, 0, base ); + + // OFDM + base = PHY_GetTxPowerByRateBase( pAdapter, BAND_ON_2_4G, ODM_RF_PATH_B, RF_1TX, OFDM ); + phy_ConvertTxPowerByRateByBase( + &( pHalData->MCSTxPowerLevelOriginalOffset[0][8] ), 0, 3, base ); + phy_ConvertTxPowerByRateByBase( + &( pHalData->MCSTxPowerLevelOriginalOffset[0][9] ), 0, 3, base ); + + // HT MCS0~7 + base = PHY_GetTxPowerByRateBase( pAdapter, BAND_ON_2_4G, ODM_RF_PATH_B, RF_1TX, HT_MCS0_MCS7 ); + phy_ConvertTxPowerByRateByBase( + &( pHalData->MCSTxPowerLevelOriginalOffset[0][10] ), 0, 3, base ); + phy_ConvertTxPowerByRateByBase( + &( pHalData->MCSTxPowerLevelOriginalOffset[0][11] ), 0, 3, base ); + + // HT MCS8~15 + base = PHY_GetTxPowerByRateBase( pAdapter, BAND_ON_2_4G, ODM_RF_PATH_B, RF_2TX, HT_MCS8_MCS15 ); + phy_ConvertTxPowerByRateByBase( + &( pHalData->MCSTxPowerLevelOriginalOffset[0][12] ), 0, 3, base ); + phy_ConvertTxPowerByRateByBase( + &( pHalData->MCSTxPowerLevelOriginalOffset[0][13] ), 0, 3, base ); + + //DBG_871X("<===PHY_ConvertTxPowerByRateInDbmToRelativeValuesOld()\n" ); +} +#endif /* TX_POWER_BY_RATE_OLD */ + +VOID +phy_ConvertTxPowerByRateInDbmToRelativeValues( + IN PADAPTER pAdapter + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA( pAdapter ); + u8 base = 0, i = 0, value = 0, + band = 0, path = 0, txNum = 0, index = 0, + startIndex = 0, endIndex = 0; + u8 cckRates[4] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M}, + ofdmRates[8] = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M}, + mcs0_7Rates[8] = {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7}, + mcs8_15Rates[8] = {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15}, + mcs16_23Rates[8] = {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19, MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23}, + vht1ssRates[10] = {MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4, + MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9}, + vht2ssRates[10] = {MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4, + MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9}, + vht3ssRates[10] = {MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4, + MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9}; + + //DBG_871X("===>PHY_ConvertTxPowerByRateInDbmToRelativeValues()\n" ); + + for ( band = BAND_ON_2_4G; band <= BAND_ON_5G; ++band ) + { + for ( path = ODM_RF_PATH_A; path <= ODM_RF_PATH_D; ++path ) + { + for ( txNum = RF_1TX; txNum < RF_MAX_TX_NUM; ++txNum ) + { + // CCK + base = PHY_GetTxPowerByRate( pAdapter, band, path, txNum, MGN_11M ); + for ( i = 0; i < sizeof( cckRates ); ++i ) + { + value = PHY_GetTxPowerByRate( pAdapter, band, path, txNum, cckRates[i] ); + PHY_SetTxPowerByRate( pAdapter, band, path, txNum, cckRates[i], value - base ); + } + + // OFDM + base = PHY_GetTxPowerByRate( pAdapter, band, path, txNum, MGN_54M ); + for ( i = 0; i < sizeof( ofdmRates ); ++i ) + { + value = PHY_GetTxPowerByRate( pAdapter, band, path, txNum, ofdmRates[i] ); + PHY_SetTxPowerByRate( pAdapter, band, path, txNum, ofdmRates[i], value - base ); + } + + // HT MCS0~7 + base = PHY_GetTxPowerByRate( pAdapter, band, path, txNum, MGN_MCS7 ); + for ( i = 0; i < sizeof( mcs0_7Rates ); ++i ) + { + value = PHY_GetTxPowerByRate( pAdapter, band, path, txNum, mcs0_7Rates[i] ); + PHY_SetTxPowerByRate( pAdapter, band, path, txNum, mcs0_7Rates[i], value - base ); + } + + // HT MCS8~15 + base = PHY_GetTxPowerByRate( pAdapter, band, path, txNum, MGN_MCS15 ); + for ( i = 0; i < sizeof( mcs8_15Rates ); ++i ) + { + value = PHY_GetTxPowerByRate( pAdapter, band, path, txNum, mcs8_15Rates[i] ); + PHY_SetTxPowerByRate( pAdapter, band, path, txNum, mcs8_15Rates[i], value - base ); + } + + // HT MCS16~23 + base = PHY_GetTxPowerByRate( pAdapter, band, path, txNum, MGN_MCS23 ); + for ( i = 0; i < sizeof( mcs16_23Rates ); ++i ) + { + value = PHY_GetTxPowerByRate( pAdapter, band, path, txNum, mcs16_23Rates[i] ); + PHY_SetTxPowerByRate( pAdapter, band, path, txNum, mcs16_23Rates[i], value - base ); + } + + // VHT 1SS + base = PHY_GetTxPowerByRate( pAdapter, band, path, txNum, MGN_VHT1SS_MCS7 ); + for ( i = 0; i < sizeof( vht1ssRates ); ++i ) + { + value = PHY_GetTxPowerByRate( pAdapter, band, path, txNum, vht1ssRates[i] ); + PHY_SetTxPowerByRate( pAdapter, band, path, txNum, vht1ssRates[i], value - base ); + } + + // VHT 2SS + base = PHY_GetTxPowerByRate( pAdapter, band, path, txNum, MGN_VHT2SS_MCS7 ); + for ( i = 0; i < sizeof( vht2ssRates ); ++i ) + { + value = PHY_GetTxPowerByRate( pAdapter, band, path, txNum, vht2ssRates[i] ); + PHY_SetTxPowerByRate( pAdapter, band, path, txNum, vht2ssRates[i], value - base ); + } + + // VHT 3SS + base = PHY_GetTxPowerByRate( pAdapter, band, path, txNum, MGN_VHT3SS_MCS7 ); + for ( i = 0; i < sizeof( vht3ssRates ); ++i ) + { + value = PHY_GetTxPowerByRate( pAdapter, band, path, txNum, vht3ssRates[i] ); + PHY_SetTxPowerByRate( pAdapter, band, path, txNum, vht3ssRates[i], value - base ); + } + } + } + } + + //DBG_871X("<===PHY_ConvertTxPowerByRateInDbmToRelativeValues()\n" ); +} + +/* + * This function must be called if the value in the PHY_REG_PG.txt(or header) + * is exact dBm values + */ +VOID +PHY_TxPowerByRateConfiguration( + IN PADAPTER pAdapter + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA( pAdapter); + + phy_StoreTxPowerByRateBase( pAdapter ); + phy_ConvertTxPowerByRateInDbmToRelativeValues( pAdapter ); +} + +VOID +PHY_SetTxPowerIndexByRateSection( + IN PADAPTER pAdapter, + IN u8 RFPath, + IN u8 Channel, + IN u8 RateSection + ) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); + + if ( RateSection == CCK ) + { + u8 cckRates[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M}; + if ( pHalData->CurrentBandType == BAND_ON_2_4G ) + PHY_SetTxPowerIndexByRateArray( pAdapter, RFPath, pHalData->CurrentChannelBW, Channel, + cckRates, sizeof(cckRates)/sizeof(u8) ); + + } + else if ( RateSection == OFDM ) + { + u8 ofdmRates[] = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M}; + PHY_SetTxPowerIndexByRateArray( pAdapter, RFPath, pHalData->CurrentChannelBW, Channel, + ofdmRates, sizeof(ofdmRates)/sizeof(u8)); + + } + else if ( RateSection == HT_MCS0_MCS7 ) + { + u8 htRates1T[] = {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7}; + PHY_SetTxPowerIndexByRateArray( pAdapter, RFPath, pHalData->CurrentChannelBW, Channel, + htRates1T, sizeof(htRates1T)/sizeof(u8)); + + } + else if ( RateSection == HT_MCS8_MCS15 ) + { + u8 htRates2T[] = {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15}; + PHY_SetTxPowerIndexByRateArray( pAdapter, RFPath, pHalData->CurrentChannelBW, Channel, + htRates2T, sizeof(htRates2T)/sizeof(u8)); + + } + else if ( RateSection == HT_MCS16_MCS23 ) + { + u1Byte htRates3T[] = {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19, MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23}; + PHY_SetTxPowerIndexByRateArray( pAdapter, RFPath, pHalData->CurrentChannelBW, Channel, + htRates3T, sizeof(htRates3T)/sizeof(u1Byte)); + + } + else if ( RateSection == HT_MCS24_MCS31 ) + { + u1Byte htRates4T[] = {MGN_MCS24, MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29, MGN_MCS30, MGN_MCS31}; + PHY_SetTxPowerIndexByRateArray( pAdapter, RFPath, pHalData->CurrentChannelBW, Channel, + htRates4T, sizeof(htRates4T)/sizeof(u1Byte)); + + } + else if ( RateSection == VHT_1SSMCS0_1SSMCS9 ) + { + u8 vhtRates1T[] = {MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4, + MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9}; + PHY_SetTxPowerIndexByRateArray( pAdapter, RFPath, pHalData->CurrentChannelBW, Channel, + vhtRates1T, sizeof(vhtRates1T)/sizeof(u8)); + + } + else if ( RateSection == VHT_2SSMCS0_2SSMCS9 ) + { + u8 vhtRates2T[] = {MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4, + MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9}; + + PHY_SetTxPowerIndexByRateArray( pAdapter, RFPath, pHalData->CurrentChannelBW, Channel, + vhtRates2T, sizeof(vhtRates2T)/sizeof(u8)); + } + else if ( RateSection == VHT_3SSMCS0_3SSMCS9 ) + { + u1Byte vhtRates3T[] = {MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4, + MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9}; + + PHY_SetTxPowerIndexByRateArray( pAdapter, RFPath, pHalData->CurrentChannelBW, Channel, + vhtRates3T, sizeof(vhtRates3T)/sizeof(u1Byte)); + } + else if ( RateSection == VHT_4SSMCS0_4SSMCS9 ) + { + u1Byte vhtRates4T[] = {MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4, + MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9}; + + PHY_SetTxPowerIndexByRateArray( pAdapter, RFPath, pHalData->CurrentChannelBW, Channel, + vhtRates4T, sizeof(vhtRates4T)/sizeof(u1Byte)); + } + else + { + DBG_871X("Invalid RateSection %d in %s", RateSection, __FUNCTION__ ); + } +} + +BOOLEAN +phy_GetChnlIndex( + IN u8 Channel, + OUT u8* ChannelIdx + ) +{ + u8 i = 0; + BOOLEAN bIn24G=_TRUE; + + if (Channel <= 14) { + bIn24G = _TRUE; + *ChannelIdx = Channel - 1; + } else { + bIn24G = _FALSE; + + for (i = 0; i < CENTER_CH_5G_ALL_NUM; ++i) { + if (center_ch_5g_all[i] == Channel) { + *ChannelIdx = i; + return bIn24G; + } + } + } + + return bIn24G; +} + +u8 +PHY_GetTxPowerIndexBase( + IN PADAPTER pAdapter, + IN u8 RFPath, + IN u8 Rate, + IN CHANNEL_WIDTH BandWidth, + IN u8 Channel, + OUT PBOOLEAN bIn24G + ) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + u8 i = 0; //default set to 1S + u8 txPower = 0; + u8 chnlIdx = (Channel-1); + + if (HAL_IsLegalChannel(pAdapter, Channel) == _FALSE) + { + chnlIdx = 0; + DBG_871X("Illegal channel!!\n"); + } + + *bIn24G = phy_GetChnlIndex(Channel, &chnlIdx); + + //DBG_871X("[%s] Channel Index: %d\n", (*bIn24G?"2.4G":"5G"), chnlIdx); + + if (*bIn24G) //3 ============================== 2.4 G ============================== + { + if ( IS_CCK_RATE(Rate) ) + { + txPower = pHalData->Index24G_CCK_Base[RFPath][chnlIdx]; + } + else if ( MGN_6M <= Rate ) + { + txPower = pHalData->Index24G_BW40_Base[RFPath][chnlIdx]; + } + else + { + DBG_871X("PHY_GetTxPowerIndexBase: INVALID Rate.\n"); + } + + //DBG_871X("Base Tx power(RF-%c, Rate #%d, Channel Index %d) = 0x%X\n", + // ((RFPath==0)?'A':'B'), Rate, chnlIdx, txPower); + + // OFDM-1T + if ( (MGN_6M <= Rate && Rate <= MGN_54M) && ! IS_CCK_RATE(Rate) ) + { + txPower += pHalData->OFDM_24G_Diff[RFPath][TX_1S]; + //DBG_871X("+PowerDiff 2.4G (RF-%c): (OFDM-1T) = (%d)\n", ((RFPath==0)?'A':'B'), pHalData->OFDM_24G_Diff[RFPath][TX_1S]); + } + // BW20-1S, BW20-2S + if (BandWidth == CHANNEL_WIDTH_20) + { + if ( (MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW20_24G_Diff[RFPath][TX_1S]; + if ( (MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW20_24G_Diff[RFPath][TX_2S]; + if ( (MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW20_24G_Diff[RFPath][TX_3S]; + if ( (MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW20_24G_Diff[RFPath][TX_4S]; + + //DBG_871X("+PowerDiff 2.4G (RF-%c): (BW20-1S, BW20-2S, BW20-3S, BW20-4S) = (%d, %d, %d, %d)\n", ((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), + // pHalData->BW20_24G_Diff[RFPath][TX_1S], pHalData->BW20_24G_Diff[RFPath][TX_2S], + // pHalData->BW20_24G_Diff[RFPath][TX_3S], pHalData->BW20_24G_Diff[RFPath][TX_4S]); + } + // BW40-1S, BW40-2S + else if (BandWidth == CHANNEL_WIDTH_40) + { + if ( (MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_24G_Diff[RFPath][TX_1S]; + if ( (MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_24G_Diff[RFPath][TX_2S]; + if ( (MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_24G_Diff[RFPath][TX_3S]; + if ( (MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_24G_Diff[RFPath][TX_4S]; + + //DBG_871X("+PowerDiff 2.4G (RF-%c): (BW40-1S, BW40-2S, BW40-3S, BW40-4S) = (%d, %d, %d, %d)\n", ((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), + // pHalData->BW40_24G_Diff[RFPath][TX_1S], pHalData->BW40_24G_Diff[RFPath][TX_2S], + // pHalData->BW40_24G_Diff[RFPath][TX_3S], pHalData->BW40_24G_Diff[RFPath][TX_4S]); + } + // Willis suggest adopt BW 40M power index while in BW 80 mode + else if ( BandWidth == CHANNEL_WIDTH_80 ) + { + if ( (MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_24G_Diff[RFPath][TX_1S]; + if ( (MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_24G_Diff[RFPath][TX_2S]; + if ( (MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_24G_Diff[RFPath][TX_3S]; + if ( (MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_24G_Diff[RFPath][TX_4S]; + + //DBG_871X("+PowerDiff 2.4G (RF-%c): (BW40-1S, BW40-2S, BW40-3S, BW40-4T) = (%d, %d, %d, %d) P.S. Current is in BW 80MHz\n", ((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), + // pHalData->BW40_24G_Diff[RFPath][TX_1S], pHalData->BW40_24G_Diff[RFPath][TX_2S], + // pHalData->BW40_24G_Diff[RFPath][TX_3S], pHalData->BW40_24G_Diff[RFPath][TX_4S]); + } + } + else //3 ============================== 5 G ============================== + { + if ( MGN_6M <= Rate ) + { + txPower = pHalData->Index5G_BW40_Base[RFPath][chnlIdx]; + } + else + { + DBG_871X("===> mpt_ProQueryCalTxPower_Jaguar: INVALID Rate.\n"); + } + + //DBG_871X("Base Tx power(RF-%c, Rate #%d, Channel Index %d) = 0x%X\n", + // ((RFPath==0)?'A':'B'), Rate, chnlIdx, txPower); + + // OFDM-1T + if ( (MGN_6M <= Rate && Rate <= MGN_54M) && ! IS_CCK_RATE(Rate)) + { + txPower += pHalData->OFDM_5G_Diff[RFPath][TX_1S]; + //DBG_871X("+PowerDiff 5G (RF-%c): (OFDM-1T) = (%d)\n", ((RFPath==0)?'A':'B'), pHalData->OFDM_5G_Diff[RFPath][TX_1S]); + } + + // BW20-1S, BW20-2S + if (BandWidth == CHANNEL_WIDTH_20) + { + if ( (MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW20_5G_Diff[RFPath][TX_1S]; + if ( (MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW20_5G_Diff[RFPath][TX_2S]; + if ( (MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW20_5G_Diff[RFPath][TX_3S]; + if ( (MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW20_5G_Diff[RFPath][TX_4S]; + + //DBG_871X("+PowerDiff 5G (RF-%c): (BW20-1S, BW20-2S, BW20-3S, BW20-4S) = (%d, %d, %d, %d)\n", ((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), + // pHalData->BW20_5G_Diff[RFPath][TX_1S], pHalData->BW20_5G_Diff[RFPath][TX_2S], + // pHalData->BW20_5G_Diff[RFPath][TX_3S], pHalData->BW20_5G_Diff[RFPath][TX_4S]); + } + // BW40-1S, BW40-2S + else if (BandWidth == CHANNEL_WIDTH_40) + { + if ( (MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_5G_Diff[RFPath][TX_1S]; + if ( (MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_5G_Diff[RFPath][TX_2S]; + if ( (MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_5G_Diff[RFPath][TX_3S]; + if ( (MGN_MCS24 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW40_5G_Diff[RFPath][TX_4S]; + + //DBG_871X("+PowerDiff 5G(RF-%c): (BW40-1S, BW40-2S) = (%d, %d, %d, %d)\n", ((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), + // pHalData->BW40_5G_Diff[RFPath][TX_1S], pHalData->BW40_5G_Diff[RFPath][TX_2S], + // pHalData->BW40_5G_Diff[RFPath][TX_3S], pHalData->BW40_5G_Diff[RFPath][TX_4S]); + } + // BW80-1S, BW80-2S + else if (BandWidth== CHANNEL_WIDTH_80) + { + // <20121220, Kordan> Get the index of array "Index5G_BW80_Base". + for (i = 0; i < CENTER_CH_5G_80M_NUM; ++i) + if (center_ch_5g_80m[i] == Channel) + chnlIdx = i; + + txPower = pHalData->Index5G_BW80_Base[RFPath][chnlIdx]; + + if ( (MGN_MCS0 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT1SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += + pHalData->BW80_5G_Diff[RFPath][TX_1S]; + if ( (MGN_MCS8 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT2SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW80_5G_Diff[RFPath][TX_2S]; + if ( (MGN_MCS16 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT3SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW80_5G_Diff[RFPath][TX_3S]; + if ( (MGN_MCS23 <= Rate && Rate <= MGN_MCS31) || (MGN_VHT4SS_MCS0 <= Rate && Rate <= MGN_VHT4SS_MCS9)) + txPower += pHalData->BW80_5G_Diff[RFPath][TX_4S]; + + //DBG_871X("+PowerDiff 5G(RF-%c): (BW80-1S, BW80-2S, BW80-3S, BW80-4S) = (%d, %d, %d, %d)\n",((RFPath==0)?'A':(RFPath==1)?'B':(RFPath==2)?'C':'D'), + // pHalData->BW80_5G_Diff[RFPath][TX_1S], pHalData->BW80_5G_Diff[RFPath][TX_2S], + // pHalData->BW80_5G_Diff[RFPath][TX_3S], pHalData->BW80_5G_Diff[RFPath][TX_4S]); + } + } + + return txPower; +} + +s8 +PHY_GetTxPowerTrackingOffset( + PADAPTER pAdapter, + u8 RFPath, + u8 Rate + ) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + s8 offset = 0; + + if( pDM_Odm->RFCalibrateInfo.TxPowerTrackControl == _FALSE) + return offset; + + if ((Rate == MGN_1M) ||(Rate == MGN_2M)||(Rate == MGN_5_5M)||(Rate == MGN_11M)) + { + offset = pDM_Odm->RFCalibrateInfo.Remnant_CCKSwingIdx; + /*DBG_871X("+Remnant_CCKSwingIdx = 0x%x\n", RFPath, Rate, pRFCalibrateInfo->Remnant_CCKSwingIdx);*/ + } + else + { + offset = pDM_Odm->RFCalibrateInfo.Remnant_OFDMSwingIdx[RFPath]; + /*DBG_871X("+Remanant_OFDMSwingIdx[RFPath %u][Rate 0x%x] = 0x%x\n", RFPath, Rate, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath]); */ + + } + + return offset; +} + +u8 +PHY_GetRateIndexOfTxPowerByRate( + IN u8 Rate + ) +{ + u8 index = 0; + switch ( Rate ) + { + case MGN_1M: index = 0; break; + case MGN_2M: index = 1; break; + case MGN_5_5M: index = 2; break; + case MGN_11M: index = 3; break; + case MGN_6M: index = 4; break; + case MGN_9M: index = 5; break; + case MGN_12M: index = 6; break; + case MGN_18M: index = 7; break; + case MGN_24M: index = 8; break; + case MGN_36M: index = 9; break; + case MGN_48M: index = 10; break; + case MGN_54M: index = 11; break; + case MGN_MCS0: index = 12; break; + case MGN_MCS1: index = 13; break; + case MGN_MCS2: index = 14; break; + case MGN_MCS3: index = 15; break; + case MGN_MCS4: index = 16; break; + case MGN_MCS5: index = 17; break; + case MGN_MCS6: index = 18; break; + case MGN_MCS7: index = 19; break; + case MGN_MCS8: index = 20; break; + case MGN_MCS9: index = 21; break; + case MGN_MCS10: index = 22; break; + case MGN_MCS11: index = 23; break; + case MGN_MCS12: index = 24; break; + case MGN_MCS13: index = 25; break; + case MGN_MCS14: index = 26; break; + case MGN_MCS15: index = 27; break; + case MGN_MCS16: index = 28; break; + case MGN_MCS17: index = 29; break; + case MGN_MCS18: index = 30; break; + case MGN_MCS19: index = 31; break; + case MGN_MCS20: index = 32; break; + case MGN_MCS21: index = 33; break; + case MGN_MCS22: index = 34; break; + case MGN_MCS23: index = 35; break; + case MGN_MCS24: index = 36; break; + case MGN_MCS25: index = 37; break; + case MGN_MCS26: index = 38; break; + case MGN_MCS27: index = 39; break; + case MGN_MCS28: index = 40; break; + case MGN_MCS29: index = 41; break; + case MGN_MCS30: index = 42; break; + case MGN_MCS31: index = 43; break; + case MGN_VHT1SS_MCS0: index = 44; break; + case MGN_VHT1SS_MCS1: index = 45; break; + case MGN_VHT1SS_MCS2: index = 46; break; + case MGN_VHT1SS_MCS3: index = 47; break; + case MGN_VHT1SS_MCS4: index = 48; break; + case MGN_VHT1SS_MCS5: index = 49; break; + case MGN_VHT1SS_MCS6: index = 50; break; + case MGN_VHT1SS_MCS7: index = 51; break; + case MGN_VHT1SS_MCS8: index = 52; break; + case MGN_VHT1SS_MCS9: index = 53; break; + case MGN_VHT2SS_MCS0: index = 54; break; + case MGN_VHT2SS_MCS1: index = 55; break; + case MGN_VHT2SS_MCS2: index = 56; break; + case MGN_VHT2SS_MCS3: index = 57; break; + case MGN_VHT2SS_MCS4: index = 58; break; + case MGN_VHT2SS_MCS5: index = 59; break; + case MGN_VHT2SS_MCS6: index = 60; break; + case MGN_VHT2SS_MCS7: index = 61; break; + case MGN_VHT2SS_MCS8: index = 62; break; + case MGN_VHT2SS_MCS9: index = 63; break; + case MGN_VHT3SS_MCS0: index = 64; break; + case MGN_VHT3SS_MCS1: index = 65; break; + case MGN_VHT3SS_MCS2: index = 66; break; + case MGN_VHT3SS_MCS3: index = 67; break; + case MGN_VHT3SS_MCS4: index = 68; break; + case MGN_VHT3SS_MCS5: index = 69; break; + case MGN_VHT3SS_MCS6: index = 70; break; + case MGN_VHT3SS_MCS7: index = 71; break; + case MGN_VHT3SS_MCS8: index = 72; break; + case MGN_VHT3SS_MCS9: index = 73; break; + case MGN_VHT4SS_MCS0: index = 74; break; + case MGN_VHT4SS_MCS1: index = 75; break; + case MGN_VHT4SS_MCS2: index = 76; break; + case MGN_VHT4SS_MCS3: index = 77; break; + case MGN_VHT4SS_MCS4: index = 78; break; + case MGN_VHT4SS_MCS5: index = 79; break; + case MGN_VHT4SS_MCS6: index = 80; break; + case MGN_VHT4SS_MCS7: index = 81; break; + case MGN_VHT4SS_MCS8: index = 82; break; + case MGN_VHT4SS_MCS9: index = 83; break; + default: + DBG_871X("Invalid rate 0x%x in %s\n", Rate, __FUNCTION__ ); + break; + }; + + return index; +} + +s8 +_PHY_GetTxPowerByRate( + IN PADAPTER pAdapter, + IN u8 Band, + IN u8 RFPath, + IN u8 TxNum, + IN u8 Rate + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + s8 value = 0; + u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate); + + if (Band != BAND_ON_2_4G && Band != BAND_ON_5G) { + DBG_871X("Invalid band %d in %s\n", Band, __func__); + goto exit; + } + if (RFPath > ODM_RF_PATH_D) { + DBG_871X("Invalid RfPath %d in %s\n", RFPath, __func__); + goto exit; + } + if (TxNum >= RF_MAX_TX_NUM) { + DBG_871X("Invalid TxNum %d in %s\n", TxNum, __func__); + goto exit; + } + if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) { + DBG_871X("Invalid RateIndex %d in %s\n", rateIndex, __func__); + goto exit; + } + + value = pHalData->TxPwrByRateOffset[Band][RFPath][TxNum][rateIndex]; + +exit: + return value; +} + + +s8 +PHY_GetTxPowerByRate( + IN PADAPTER pAdapter, + IN u8 Band, + IN u8 RFPath, + IN u8 TxNum, + IN u8 Rate + ) +{ + if (!phy_is_tx_power_by_rate_needed(pAdapter)) + return 0; + + return _PHY_GetTxPowerByRate(pAdapter, Band, RFPath, TxNum, Rate); +} + +VOID +PHY_SetTxPowerByRate( + IN PADAPTER pAdapter, + IN u8 Band, + IN u8 RFPath, + IN u8 TxNum, + IN u8 Rate, + IN s8 Value + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA( pAdapter ); + u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate( Rate ); + + if ( Band != BAND_ON_2_4G && Band != BAND_ON_5G ) + { + DBG_871X("Invalid band %d in %s\n", Band, __FUNCTION__ ); + return; + } + if ( RFPath > ODM_RF_PATH_D ) + { + DBG_871X("Invalid RfPath %d in %s\n", RFPath, __FUNCTION__ ); + return; + } + if ( TxNum >= RF_MAX_TX_NUM ) + { + DBG_871X( "Invalid TxNum %d in %s\n", TxNum, __FUNCTION__ ); + return; + } + if ( rateIndex >= TX_PWR_BY_RATE_NUM_RATE ) + { + DBG_871X("Invalid RateIndex %d in %s\n", rateIndex, __FUNCTION__ ); + return; + } + + pHalData->TxPwrByRateOffset[Band][RFPath][TxNum][rateIndex] = Value; +} + +VOID +PHY_SetTxPowerLevelByPath( + IN PADAPTER Adapter, + IN u8 channel, + IN u8 path + ) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + BOOLEAN bIsIn24G = (pHalData->CurrentBandType == BAND_ON_2_4G ); + + //if ( pMgntInfo->RegNByteAccess == 0 ) + { + if ( bIsIn24G ) + PHY_SetTxPowerIndexByRateSection( Adapter, path, channel, CCK ); + + PHY_SetTxPowerIndexByRateSection( Adapter, path, channel, OFDM ); + PHY_SetTxPowerIndexByRateSection( Adapter, path, channel, HT_MCS0_MCS7 ); + + if (IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter)) + PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, VHT_1SSMCS0_1SSMCS9); + + if (pHalData->NumTotalRFPath >= 2) + { + PHY_SetTxPowerIndexByRateSection( Adapter, path, channel, HT_MCS8_MCS15 ); + + if (IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter)) + PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, VHT_2SSMCS0_2SSMCS9); + + if (IS_HARDWARE_TYPE_8814A(Adapter)) + { + PHY_SetTxPowerIndexByRateSection( Adapter, path, channel, HT_MCS16_MCS23 ); + PHY_SetTxPowerIndexByRateSection( Adapter, path, channel, VHT_3SSMCS0_3SSMCS9 ); + } + } + } +} + +VOID +PHY_SetTxPowerIndexByRateArray( + IN PADAPTER pAdapter, + IN u8 RFPath, + IN CHANNEL_WIDTH BandWidth, + IN u8 Channel, + IN u8* Rates, + IN u8 RateArraySize + ) +{ + u32 powerIndex = 0; + int i = 0; + + for (i = 0; i < RateArraySize; ++i) + { + powerIndex = PHY_GetTxPowerIndex(pAdapter, RFPath, Rates[i], BandWidth, Channel); + PHY_SetTxPowerIndex(pAdapter, powerIndex, RFPath, Rates[i]); + } +} + +s8 +phy_GetWorldWideLimit( + s8* LimitTable +) +{ + s8 min = LimitTable[0]; + u8 i = 0; + + for (i = 0; i < MAX_REGULATION_NUM; ++i) { + if (LimitTable[i] < min) + min = LimitTable[i]; + } + + return min; +} + +s8 +phy_GetChannelIndexOfTxPowerLimit( + IN u8 Band, + IN u8 Channel + ) +{ + s8 channelIndex = -1; + u8 i = 0; + + if (Band == BAND_ON_2_4G) { + channelIndex = Channel - 1; + } else if (Band == BAND_ON_5G) { + for (i = 0; i < CENTER_CH_5G_ALL_NUM; ++i) { + if (center_ch_5g_all[i] == Channel) + channelIndex = i; + } + } else { + DBG_871X_LEVEL(_drv_always_, "Invalid Band %d in %s\n", Band, __func__); + } + + if (channelIndex == -1) + DBG_871X_LEVEL(_drv_always_, "Invalid Channel %d of Band %d in %s\n", Channel, Band, __func__); + + return channelIndex; +} + +s8 +PHY_GetTxPowerLimit( + IN PADAPTER Adapter, + IN u32 RegPwrTblSel, + IN BAND_TYPE Band, + IN CHANNEL_WIDTH Bandwidth, + IN u8 RfPath, + IN u8 DataRate, + IN u8 Channel + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + s16 band = -1, regulation = -1, bandwidth = -1, + rateSection = -1, channel = -1; + s8 powerLimit = MAX_POWER_INDEX; + + if ( ( Adapter->registrypriv.RegEnableTxPowerLimit == 2 && pHalData->EEPROMRegulatory != 1 ) || + Adapter->registrypriv.RegEnableTxPowerLimit == 0 ) + return MAX_POWER_INDEX; + + switch (RegPwrTblSel) { + case 1: + regulation = TXPWR_LMT_ETSI; + break; + case 2: + regulation = TXPWR_LMT_MKK; + break; + case 3: + regulation = TXPWR_LMT_FCC; + break; + case 4: + regulation = TXPWR_LMT_WW; + break; + default: + regulation = (Band == BAND_ON_2_4G) ? pHalData->Regulation2_4G : pHalData->Regulation5G; + break; + } + + //DBG_871X("pMgntInfo->RegPwrTblSel %d, final regulation %d\n", Adapter->registrypriv.RegPwrTblSel, regulation ); + + + if ( Band == BAND_ON_2_4G ) band = 0; + else if ( Band == BAND_ON_5G ) band = 1; + + if ( Bandwidth == CHANNEL_WIDTH_20 ) bandwidth = 0; + else if ( Bandwidth == CHANNEL_WIDTH_40 ) bandwidth = 1; + else if ( Bandwidth == CHANNEL_WIDTH_80 ) bandwidth = 2; + else if ( Bandwidth == CHANNEL_WIDTH_160 ) bandwidth = 3; + + switch ( DataRate ) + { + case MGN_1M: case MGN_2M: case MGN_5_5M: case MGN_11M: + rateSection = 0; + break; + + case MGN_6M: case MGN_9M: case MGN_12M: case MGN_18M: + case MGN_24M: case MGN_36M: case MGN_48M: case MGN_54M: + rateSection = 1; + break; + + case MGN_MCS0: case MGN_MCS1: case MGN_MCS2: case MGN_MCS3: + case MGN_MCS4: case MGN_MCS5: case MGN_MCS6: case MGN_MCS7: + rateSection = 2; + break; + + case MGN_MCS8: case MGN_MCS9: case MGN_MCS10: case MGN_MCS11: + case MGN_MCS12: case MGN_MCS13: case MGN_MCS14: case MGN_MCS15: + rateSection = 3; + break; + + case MGN_MCS16: case MGN_MCS17: case MGN_MCS18: case MGN_MCS19: + case MGN_MCS20: case MGN_MCS21: case MGN_MCS22: case MGN_MCS23: + rateSection = 4; + break; + + case MGN_MCS24: case MGN_MCS25: case MGN_MCS26: case MGN_MCS27: + case MGN_MCS28: case MGN_MCS29: case MGN_MCS30: case MGN_MCS31: + rateSection = 5; + break; + + case MGN_VHT1SS_MCS0: case MGN_VHT1SS_MCS1: case MGN_VHT1SS_MCS2: + case MGN_VHT1SS_MCS3: case MGN_VHT1SS_MCS4: case MGN_VHT1SS_MCS5: + case MGN_VHT1SS_MCS6: case MGN_VHT1SS_MCS7: case MGN_VHT1SS_MCS8: + case MGN_VHT1SS_MCS9: + rateSection = 6; + break; + + case MGN_VHT2SS_MCS0: case MGN_VHT2SS_MCS1: case MGN_VHT2SS_MCS2: + case MGN_VHT2SS_MCS3: case MGN_VHT2SS_MCS4: case MGN_VHT2SS_MCS5: + case MGN_VHT2SS_MCS6: case MGN_VHT2SS_MCS7: case MGN_VHT2SS_MCS8: + case MGN_VHT2SS_MCS9: + rateSection = 7; + break; + + case MGN_VHT3SS_MCS0: case MGN_VHT3SS_MCS1: case MGN_VHT3SS_MCS2: + case MGN_VHT3SS_MCS3: case MGN_VHT3SS_MCS4: case MGN_VHT3SS_MCS5: + case MGN_VHT3SS_MCS6: case MGN_VHT3SS_MCS7: case MGN_VHT3SS_MCS8: + case MGN_VHT3SS_MCS9: + rateSection = 8; + break; + + case MGN_VHT4SS_MCS0: case MGN_VHT4SS_MCS1: case MGN_VHT4SS_MCS2: + case MGN_VHT4SS_MCS3: case MGN_VHT4SS_MCS4: case MGN_VHT4SS_MCS5: + case MGN_VHT4SS_MCS6: case MGN_VHT4SS_MCS7: case MGN_VHT4SS_MCS8: + case MGN_VHT4SS_MCS9: + rateSection = 9; + break; + + default: + DBG_871X("Wrong rate 0x%x\n", DataRate ); + break; + } + + if ( Band == BAND_ON_5G && rateSection == 0 ) + DBG_871X("Wrong rate 0x%x: No CCK in 5G Band\n", DataRate ); + + // workaround for wrong index combination to obtain tx power limit, + // OFDM only exists in BW 20M + if ( rateSection == 1 ) + bandwidth = 0; + + // workaround for wrong index combination to obtain tx power limit, + // CCK table will only be given in BW 20M + if ( rateSection == 0 ) + bandwidth = 0; + + // workaround for wrong indxe combination to obtain tx power limit, + // HT on 80M will reference to HT on 40M + if ( ( rateSection == 2 || rateSection == 3 ) && Band == BAND_ON_5G && bandwidth == 2 ) { + bandwidth = 1; + } + + if ( Band == BAND_ON_2_4G ) + channel = phy_GetChannelIndexOfTxPowerLimit( BAND_ON_2_4G, Channel ); + else if ( Band == BAND_ON_5G ) + channel = phy_GetChannelIndexOfTxPowerLimit( BAND_ON_5G, Channel ); + else if ( Band == BAND_ON_BOTH ) + { + // BAND_ON_BOTH don't care temporarily + } + + if ( band == -1 || regulation == -1 || bandwidth == -1 || + rateSection == -1 || channel == -1 ) + { + //DBG_871X("Wrong index value to access power limit table [band %d][regulation %d][bandwidth %d][rf_path %d][rate_section %d][chnlGroup %d]\n", + // band, regulation, bandwidth, RfPath, rateSection, channelGroup ); + + return MAX_POWER_INDEX; + } + + if ( Band == BAND_ON_2_4G ) { + s8 limits[10] = {0}; u8 i = 0; + if (bandwidth >= MAX_2_4G_BANDWIDTH_NUM) + bandwidth = MAX_2_4G_BANDWIDTH_NUM - 1; + for (i = 0; i < MAX_REGULATION_NUM; ++i) + limits[i] = pHalData->TxPwrLimit_2_4G[i][bandwidth][rateSection][channel][RfPath]; + + powerLimit = (regulation == TXPWR_LMT_WW) ? phy_GetWorldWideLimit(limits) : + pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channel][RfPath]; + + } else if ( Band == BAND_ON_5G ) { + s8 limits[10] = {0}; u8 i = 0; + for (i = 0; i < MAX_REGULATION_NUM; ++i) + limits[i] = pHalData->TxPwrLimit_5G[i][bandwidth][rateSection][channel][RfPath]; + + powerLimit = (regulation == TXPWR_LMT_WW) ? phy_GetWorldWideLimit(limits) : + pHalData->TxPwrLimit_5G[regulation][bandwidth][rateSection][channel][RfPath]; + } else + DBG_871X("No power limit table of the specified band\n" ); + + // combine 5G VHT & HT rate + // 5G 20M and 40M HT and VHT can cross reference + /* + if ( Band == BAND_ON_5G && powerLimit == MAX_POWER_INDEX ) { + if ( bandwidth == 0 || bandwidth == 1 ) { + RT_TRACE( COMP_INIT, DBG_LOUD, ( "No power limit table of the specified band %d, bandwidth %d, ratesection %d, rf path %d\n", + band, bandwidth, rateSection, RfPath ) ); + if ( rateSection == 2 ) + powerLimit = pHalData->TxPwrLimit_5G[regulation] + [bandwidth][4][channelGroup][RfPath]; + else if ( rateSection == 4 ) + powerLimit = pHalData->TxPwrLimit_5G[regulation] + [bandwidth][2][channelGroup][RfPath]; + else if ( rateSection == 3 ) + powerLimit = pHalData->TxPwrLimit_5G[regulation] + [bandwidth][5][channelGroup][RfPath]; + else if ( rateSection == 5 ) + powerLimit = pHalData->TxPwrLimit_5G[regulation] + [bandwidth][3][channelGroup][RfPath]; + } + } + */ + //DBG_871X("TxPwrLmt[Regulation %d][Band %d][BW %d][RFPath %d][Rate 0x%x][Chnl %d] = %d\n", + // regulation, pHalData->CurrentBandType, Bandwidth, RfPath, DataRate, Channel, powerLimit); + return powerLimit; +} + +VOID +phy_CrossReferenceHTAndVHTTxPowerLimit( + IN PADAPTER pAdapter + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + u8 regulation, bw, channel, rs, ref_rs; + int ht_ref_vht_5g_20_40 = 0; + int vht_ref_ht_5g_20_40 = 0; + int ht_has_ref_5g_20_40 = 0; + int vht_has_ref_5g_20_40 = 0; + + pHalData->tx_pwr_lmt_5g_20_40_ref = 0; + + for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) { + + for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) { + + for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) { + + for (rs = 0; rs < MAX_RATE_SECTION_NUM; ++rs) { + + /* 5G 20M 40M VHT and HT can cross reference */ + if (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40) { + if (rs == HT_1SS) + ref_rs = VHT_1SS; + else if (rs == HT_2SS) + ref_rs = VHT_2SS; + else if (rs == HT_3SS) + ref_rs = VHT_3SS; + else if (rs == HT_4SS) + ref_rs = VHT_4SS; + else if (rs == VHT_1SS) + ref_rs = HT_1SS; + else if (rs == VHT_2SS) + ref_rs = HT_2SS; + else if (rs == VHT_3SS) + ref_rs = HT_3SS; + else if (rs == VHT_4SS) + ref_rs = HT_4SS; + else + continue; + + if (pHalData->TxPwrLimit_5G[regulation][bw][ref_rs][channel][RF_PATH_A] == MAX_POWER_INDEX) + continue; + + if (IS_HT_RATE_SECTION(rs)) + ht_has_ref_5g_20_40++; + else if (IS_VHT_RATE_SECTION(rs)) + vht_has_ref_5g_20_40++; + else + continue; + + if (pHalData->TxPwrLimit_5G[regulation][bw][rs][channel][RF_PATH_A] != MAX_POWER_INDEX) + continue; + + if (IS_HT_RATE_SECTION(rs) && IS_VHT_RATE_SECTION(ref_rs)) + ht_ref_vht_5g_20_40++; + else if (IS_VHT_RATE_SECTION(rs) && IS_HT_RATE_SECTION(ref_rs)) + vht_ref_ht_5g_20_40++; + + if (0) + DBG_871X("reg:%u, bw:%u, ch:%u, %s ref %s\n" + , regulation, bw, channel + , rate_section_str(rs), rate_section_str(ref_rs)); + + pHalData->TxPwrLimit_5G[regulation][bw][rs][channel][RF_PATH_A] = + pHalData->TxPwrLimit_5G[regulation][bw][ref_rs][channel][RF_PATH_A]; + } + + } + } + } + } + + if (0) { + DBG_871X("ht_ref_vht_5g_20_40:%d, ht_has_ref_5g_20_40:%d\n", ht_ref_vht_5g_20_40, ht_has_ref_5g_20_40); + DBG_871X("vht_ref_hht_5g_20_40:%d, vht_has_ref_5g_20_40:%d\n", vht_ref_ht_5g_20_40, vht_has_ref_5g_20_40); + } + + /* 5G 20M&40M HT all come from VHT*/ + if (ht_ref_vht_5g_20_40 && ht_has_ref_5g_20_40 == ht_ref_vht_5g_20_40) + pHalData->tx_pwr_lmt_5g_20_40_ref |= TX_PWR_LMT_REF_HT_FROM_VHT; + + /* 5G 20M&40M VHT all come from HT*/ + if (vht_ref_ht_5g_20_40 && vht_has_ref_5g_20_40 == vht_ref_ht_5g_20_40) + pHalData->tx_pwr_lmt_5g_20_40_ref |= TX_PWR_LMT_REF_VHT_FROM_HT; +} + +VOID +PHY_ConvertTxPowerLimitToPowerIndex( + IN PADAPTER Adapter + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u8 base; + u8 regulation, bw, channel, rateSection; + s8 tempValue = 0, tempPwrLmt = 0; + u8 rfPath = 0; + + if (pHalData->odmpriv.PhyRegPgValueType != PHY_REG_PG_EXACT_VALUE) { + rtw_warn_on(1); + return; + } + + phy_CrossReferenceHTAndVHTTxPowerLimit(Adapter); + + for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) { + + for (bw = 0; bw < MAX_2_4G_BANDWIDTH_NUM; ++bw) { + + for (channel = 0; channel < CENTER_CH_2G_NUM; ++channel) { + + for (rateSection = CCK; rateSection <= HT_4SS; ++rateSection) { + tempPwrLmt = pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][RF_PATH_A]; + + if (tempPwrLmt != MAX_POWER_INDEX) { + + for (rfPath = RF_PATH_A; rfPath < MAX_RF_PATH; ++rfPath) { + base = phy_get_target_tx_power(Adapter, BAND_ON_2_4G, rfPath, rateSection); + tempValue = tempPwrLmt - base; + pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][rfPath] = tempValue; + } + } + } + } + } + } + + if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(Adapter)) { + + for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) { + + for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; ++bw) { + + for (channel = 0; channel < CENTER_CH_5G_ALL_NUM; ++channel) { + + for (rateSection = OFDM; rateSection <= VHT_4SS; ++rateSection) { + tempPwrLmt = pHalData->TxPwrLimit_5G[regulation][bw][rateSection][channel][RF_PATH_A]; + + if (tempPwrLmt != MAX_POWER_INDEX) { + + for (rfPath = RF_PATH_A; rfPath < MAX_RF_PATH; ++rfPath) { + base = phy_get_target_tx_power(Adapter, BAND_ON_5G, rfPath, rateSection); + tempValue = tempPwrLmt - base; + pHalData->TxPwrLimit_5G[regulation][bw][rateSection][channel][rfPath] = tempValue; + } + } + } + } + } + } + } +} + +/* +* PHY_InitTxPowerLimit - Set all hal_data.TxPwrLimit_2_4G, TxPwrLimit_5G array to MAX_POWER_INDEX +*/ +VOID +PHY_InitTxPowerLimit( + IN PADAPTER Adapter + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u8 i, j, k, l, m; + + for (i = 0; i < MAX_REGULATION_NUM; ++i) + for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j) + for (k = 0; k < MAX_RATE_SECTION_NUM; ++k) + for (m = 0; m < CENTER_CH_2G_NUM; ++m) + for (l = 0; l < MAX_RF_PATH; ++l) + pHalData->TxPwrLimit_2_4G[i][j][k][m][l] = MAX_POWER_INDEX; + + for (i = 0; i < MAX_REGULATION_NUM; ++i) + for (j = 0; j < MAX_5G_BANDWIDTH_NUM; ++j) + for (k = 0; k < MAX_RATE_SECTION_NUM; ++k) + for (m = 0; m < CENTER_CH_5G_ALL_NUM; ++m) + for (l = 0; l < MAX_RF_PATH; ++l) + pHalData->TxPwrLimit_5G[i][j][k][m][l] = MAX_POWER_INDEX; +} + +/* +* PHY_SetTxPowerLimit - Parsing TX power limit from phydm array, called by odm_ConfigBB_TXPWR_LMT_XXX in phydm +*/ +VOID +PHY_SetTxPowerLimit( + IN PDM_ODM_T pDM_Odm, + IN u8 *Regulation, + IN u8 *Band, + IN u8 *Bandwidth, + IN u8 *RateSection, + IN u8 *RfPath, + IN u8 *Channel, + IN u8 *PowerLimit + ) +{ + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u8 regulation = 0, bandwidth = 0, rateSection = 0, channel; + s8 powerLimit = 0, prevPowerLimit, channelIndex; + + if (0) + DBG_871X("Index of power limit table [band %s][regulation %s][bw %s][rate section %s][rf path %s][chnl %s][val %s]\n" + , Band, Regulation, Bandwidth, RateSection, RfPath, Channel, PowerLimit); + + if (GetU1ByteIntegerFromStringInDecimal((s8 *)Channel, &channel) == _FALSE + || GetU1ByteIntegerFromStringInDecimal((s8 *)PowerLimit, &powerLimit) == _FALSE + ){ + DBG_871X_LEVEL(_drv_always_, "Illegal index of power limit table [ch %s][val %s]\n", Channel, PowerLimit); + return; + } + + powerLimit = powerLimit > MAX_POWER_INDEX ? MAX_POWER_INDEX : powerLimit; + + if (eqNByte(Regulation, (u8 *)("FCC"), 3)) + regulation = TXPWR_LMT_FCC; + else if (eqNByte(Regulation, (u8 *)("MKK"), 3)) + regulation = TXPWR_LMT_MKK; + else if (eqNByte(Regulation, (u8 *)("ETSI"), 4)) + regulation = TXPWR_LMT_ETSI; + else if (eqNByte(Regulation, (u8 *)("WW13"), 4)) + regulation = TXPWR_LMT_WW; + else { + DBG_871X_LEVEL(_drv_always_, "unknown regulation:%s", Regulation); + return; + } + + if (eqNByte(RateSection, (u8 *)("CCK"), 3) && eqNByte(RfPath, (u8 *)("1T"), 2)) + rateSection = CCK; + else if (eqNByte(RateSection, (u8 *)("OFDM"), 4) && eqNByte(RfPath, (u8 *)("1T"), 2)) + rateSection = OFDM; + else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("1T"), 2)) + rateSection = HT_1SS; + else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("2T"), 2)) + rateSection = HT_2SS; + else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("3T"), 2)) + rateSection = HT_3SS; + else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("4T"), 2)) + rateSection = HT_4SS; + else if (eqNByte(RateSection, (u8 *)("VHT"), 3) && eqNByte(RfPath, (u8 *)("1T"), 2)) + rateSection = VHT_1SS; + else if (eqNByte(RateSection, (u8 *)("VHT"), 3) && eqNByte(RfPath, (u8 *)("2T"), 2)) + rateSection = VHT_2SS; + else if (eqNByte(RateSection, (u8 *)("VHT"), 3) && eqNByte(RfPath, (u8 *)("3T"), 2)) + rateSection = VHT_3SS; + else if (eqNByte(RateSection, (u8 *)("VHT"), 3) && eqNByte(RfPath, (u8 *)("4T"), 2)) + rateSection = VHT_4SS; + else { + DBG_871X_LEVEL(_drv_always_, "Wrong rate section: (%s,%s)\n", RateSection, RfPath); + return; + } + + if (eqNByte(Bandwidth, (u8 *)("20M"), 3)) + bandwidth = CHANNEL_WIDTH_20; + else if (eqNByte(Bandwidth, (u8 *)("40M"), 3)) + bandwidth = CHANNEL_WIDTH_40; + else if (eqNByte(Bandwidth, (u8 *)("80M"), 3)) + bandwidth = CHANNEL_WIDTH_80; + else { + DBG_871X_LEVEL(_drv_always_, "unknown bandwidth: %s\n", Bandwidth); + return; + } + + if (eqNByte(Band, (u8 *)("2.4G"), 4)) { + channelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_2_4G, channel); + + if (channelIndex == -1) { + DBG_871X_LEVEL(_drv_always_, "unsupported channel: %d at 2.4G\n", channel); + return; + } + + if (bandwidth >= MAX_2_4G_BANDWIDTH_NUM) { + DBG_871X_LEVEL(_drv_always_, "unsupported bandwidth: %s at 2.4G\n", Bandwidth); + return; + } + + prevPowerLimit = pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A]; + + if (prevPowerLimit != MAX_POWER_INDEX) + DBG_871X_LEVEL(_drv_always_, "duplicate tx power limit combination [band %s][regulation %s][bw %s][rate section %s][rf path %s][chnl %s]\n" + , Band, Regulation, Bandwidth, RateSection, RfPath, Channel); + + if (powerLimit < prevPowerLimit) + pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A] = powerLimit; + + if (0) + DBG_871X("2.4G Band value : [regulation %d][bw %d][rate_section %d][chnl %d][val %d]\n" + , regulation, bandwidth, rateSection, channelIndex, pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][ODM_RF_PATH_A]); + } else if (eqNByte(Band, (u8 *)("5G"), 2)) { + + channelIndex = phy_GetChannelIndexOfTxPowerLimit(BAND_ON_5G, channel); + + if (channelIndex == -1) { + DBG_871X_LEVEL(_drv_always_, "unsupported channel: %d at 5G\n", channel); + return; + } + + prevPowerLimit = pHalData->TxPwrLimit_5G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A]; + + if (prevPowerLimit != MAX_POWER_INDEX) + DBG_871X_LEVEL(_drv_always_, "duplicate tx power limit combination [band %s][regulation %s][bw %s][rate section %s][rf path %s][chnl %s]\n" + , Band, Regulation, Bandwidth, RateSection, RfPath, Channel); + + if (powerLimit < prevPowerLimit) + pHalData->TxPwrLimit_5G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A] = powerLimit; + + if (0) + DBG_871X("5G Band value : [regulation %d][bw %d][rate_section %d][chnl %d][val %d]\n" + , regulation, bandwidth, rateSection, channel, pHalData->TxPwrLimit_5G[regulation][bandwidth][rateSection][channelIndex][RF_PATH_A]); + } else { + DBG_871X_LEVEL(_drv_always_, "Cannot recognize the band info in %s\n", Band); + return; + } +} + +u8 +PHY_GetTxPowerIndex( + IN PADAPTER pAdapter, + IN u8 RFPath, + IN u8 Rate, + IN CHANNEL_WIDTH BandWidth, + IN u8 Channel + ) +{ + u8 txPower = 0x3E; + + if (IS_HARDWARE_TYPE_8814A(pAdapter)) { +#if (RTL8814A_SUPPORT == 1) + txPower = PHY_GetTxPowerIndex_8814A(pAdapter, RFPath, Rate, BandWidth, Channel); +#endif + } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) { +#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) + txPower = PHY_GetTxPowerIndex_8812A(pAdapter, RFPath, Rate, BandWidth, Channel); +#endif + } + else if (IS_HARDWARE_TYPE_8723B(pAdapter)) { +#if (RTL8723B_SUPPORT == 1) + txPower = PHY_GetTxPowerIndex_8723B(pAdapter, RFPath, Rate, BandWidth, Channel); +#endif + } + else if (IS_HARDWARE_TYPE_8703B(pAdapter)) { +#if (RTL8703B_SUPPORT == 1) + txPower = PHY_GetTxPowerIndex_8703B(pAdapter, RFPath, Rate, BandWidth, Channel); +#endif + } + else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { +#if (RTL8192E_SUPPORT==1) + txPower = PHY_GetTxPowerIndex_8192E(pAdapter, RFPath, Rate, BandWidth, Channel); +#endif + } + else if (IS_HARDWARE_TYPE_8188E(pAdapter)) { +#if (RTL8188E_SUPPORT==1) + txPower = PHY_GetTxPowerIndex_8188E(pAdapter, RFPath, Rate, BandWidth, Channel); +#endif + } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) { +#if (RTL8188F_SUPPORT == 1) + txPower = PHY_GetTxPowerIndex_8188F(pAdapter, RFPath, Rate, BandWidth, Channel); +#endif + } + + return txPower; +} + +VOID +PHY_SetTxPowerIndex( + IN PADAPTER pAdapter, + IN u32 PowerIndex, + IN u8 RFPath, + IN u8 Rate + ) +{ + if (IS_HARDWARE_TYPE_8814A(pAdapter)) { +#if (RTL8814A_SUPPORT == 1) + PHY_SetTxPowerIndex_8814A(pAdapter, PowerIndex, RFPath, Rate); +#endif + } + else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) { +#if ((RTL8812A_SUPPORT==1) || (RTL8821A_SUPPORT == 1)) + PHY_SetTxPowerIndex_8812A( pAdapter, PowerIndex, RFPath, Rate ); +#endif + } + else if (IS_HARDWARE_TYPE_8723B(pAdapter)) { +#if (RTL8723B_SUPPORT==1) + PHY_SetTxPowerIndex_8723B( pAdapter, PowerIndex, RFPath, Rate ); +#endif + } + else if (IS_HARDWARE_TYPE_8703B(pAdapter)) { +#if (RTL8703B_SUPPORT==1) + PHY_SetTxPowerIndex_8703B( pAdapter, PowerIndex, RFPath, Rate ); +#endif + } + else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { +#if (RTL8192E_SUPPORT==1) + PHY_SetTxPowerIndex_8192E( pAdapter, PowerIndex, RFPath, Rate ); +#endif + } + else if (IS_HARDWARE_TYPE_8188E(pAdapter)) { +#if (RTL8188E_SUPPORT==1) + PHY_SetTxPowerIndex_8188E( pAdapter, PowerIndex, RFPath, Rate ); +#endif + } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) { +#if (RTL8188F_SUPPORT == 1) + PHY_SetTxPowerIndex_8188F(pAdapter, PowerIndex, RFPath, Rate); +#endif + } +} + +bool phy_is_tx_power_limit_needed(_adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter)); + + if (regsty->RegEnableTxPowerLimit == 1 + || (regsty->RegEnableTxPowerLimit == 2 && hal_data->EEPROMRegulatory == 1)) + return _TRUE; + return _FALSE; +} + +bool phy_is_tx_power_by_rate_needed(_adapter *adapter) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter)); + + if (regsty->RegEnableTxPowerByRate == 1 + || (regsty->RegEnableTxPowerByRate == 2 && hal_data->EEPROMRegulatory != 2)) + return _TRUE; + return _FALSE; +} + +int phy_load_tx_power_by_rate(_adapter *adapter, u8 chk_file) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter)); + int ret = _FAIL; + + hal_data->txpwr_by_rate_loaded = 0; + PHY_InitTxPowerByRate(adapter); + + /* tx power limit is based on tx power by rate */ + hal_data->txpwr_limit_loaded = 0; + +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + if (chk_file + && phy_ConfigBBWithPgParaFile(adapter, PHY_FILE_PHY_REG_PG) == _SUCCESS + ) { + hal_data->txpwr_by_rate_from_file = 1; + goto post_hdl; + } +#endif + +#ifdef CONFIG_EMBEDDED_FWIMG + if (HAL_STATUS_SUCCESS == ODM_ConfigBBWithHeaderFile(&hal_data->odmpriv, CONFIG_BB_PHY_REG_PG)) { + DBG_871X("default power by rate loaded\n"); + hal_data->txpwr_by_rate_from_file = 0; + goto post_hdl; + } +#endif + + DBG_871X_LEVEL(_drv_err_, "%s():Read Tx power by rate fail\n", __func__); + goto exit; + +post_hdl: + if (hal_data->odmpriv.PhyRegPgValueType != PHY_REG_PG_EXACT_VALUE) { + rtw_warn_on(1); + goto exit; + } + + PHY_TxPowerByRateConfiguration(adapter); + hal_data->txpwr_by_rate_loaded = 1; + + ret = _SUCCESS; + +exit: + return ret; +} + +int phy_load_tx_power_limit(_adapter *adapter, u8 chk_file) +{ + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter)); + int ret = _FAIL; + + hal_data->txpwr_limit_loaded = 0; + PHY_InitTxPowerLimit(adapter); + + if (!hal_data->txpwr_by_rate_loaded && regsty->target_tx_pwr_valid != _TRUE) { + DBG_871X_LEVEL(_drv_err_, "%s():Read Tx power limit before target tx power is specify\n", __func__); + goto exit; + } + +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + if (chk_file + && PHY_ConfigRFWithPowerLimitTableParaFile(adapter, PHY_FILE_TXPWR_LMT) == _SUCCESS + ) { + hal_data->txpwr_limit_from_file = 1; + goto post_hdl; + } +#endif + +#ifdef CONFIG_EMBEDDED_FWIMG + if (HAL_STATUS_SUCCESS == ODM_ConfigRFWithHeaderFile(&hal_data->odmpriv, CONFIG_RF_TXPWR_LMT, (ODM_RF_RADIO_PATH_E)0)) { + DBG_871X("default power limit loaded\n"); + hal_data->txpwr_limit_from_file = 0; + goto post_hdl; + } +#endif + + DBG_871X_LEVEL(_drv_err_, "%s():Read Tx power limit fail\n", __func__); + goto exit; + +post_hdl: + PHY_ConvertTxPowerLimitToPowerIndex(adapter); + hal_data->txpwr_limit_loaded = 1; + ret = _SUCCESS; + +exit: + return ret; +} + +void phy_load_tx_power_ext_info(_adapter *adapter, u8 chk_file) +{ + struct registry_priv *regsty = adapter_to_regsty(adapter); + + /* check registy target tx power */ + regsty->target_tx_pwr_valid = rtw_regsty_chk_target_tx_power_valid(adapter); + + /* power by rate and limit */ + if (phy_is_tx_power_by_rate_needed(adapter) + || (phy_is_tx_power_limit_needed(adapter) && regsty->target_tx_pwr_valid != _TRUE)) + phy_load_tx_power_by_rate(adapter, chk_file); + + if (phy_is_tx_power_limit_needed(adapter)) + phy_load_tx_power_limit(adapter, chk_file); +} + +inline void phy_reload_tx_power_ext_info(_adapter *adapter) +{ + phy_load_tx_power_ext_info(adapter, 1); +} + +inline void phy_reload_default_tx_power_ext_info(_adapter *adapter) +{ + phy_load_tx_power_ext_info(adapter, 0); +} + +void dump_tx_power_ext_info(void *sel, _adapter *adapter) +{ + struct registry_priv *regsty = adapter_to_regsty(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + + if (phy_is_tx_power_by_rate_needed(adapter) + || (phy_is_tx_power_limit_needed(adapter) && regsty->target_tx_pwr_valid != _TRUE)) + DBG_871X_SEL_NL(sel, "target_tx_power: from powr by rate\n"); + else if (regsty->target_tx_pwr_valid == _TRUE) + DBG_871X_SEL_NL(sel, "target_tx_power: from registry\n"); + else + DBG_871X_SEL_NL(sel, "target_tx_power: unavailable\n"); + + + DBG_871X_SEL_NL(sel, "tx_power_by_rate: %s, %s, %s\n" + , phy_is_tx_power_by_rate_needed(adapter) ? "enabled" : "disabled" + , hal_data->txpwr_by_rate_loaded ? "loaded" : "unloaded" + , hal_data->txpwr_by_rate_from_file ? "file" : "default" + ); + + DBG_871X_SEL_NL(sel, "tx_power_limit: %s, %s, %s\n" + , phy_is_tx_power_limit_needed(adapter) ? "enabled" : "disabled" + , hal_data->txpwr_limit_loaded ? "loaded" : "unloaded" + , hal_data->txpwr_limit_from_file ? "file" : "default" + ); +} + +void dump_target_tx_power(void *sel, _adapter *adapter) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct registry_priv *regsty = adapter_to_regsty(adapter); + int path, tx_num, band, rs; + u8 target; + + for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) { + if (!hal_is_band_support(adapter, band)) + continue; + + for (path = 0; path < RF_PATH_MAX; path++) { + if (path >= hal_data->NumTotalRFPath) + break; + + DBG_871X_SEL_NL(sel, "[%s][%c]\n", band_str(band), rf_path_char(path)); + + for (rs = 0; rs < RATE_SECTION_NUM; rs++) { + tx_num = rate_section_to_tx_num(rs); + if (tx_num >= hal_spec->nss_num) + continue; + + if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs)) + continue; + + if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) + continue; + + target = phy_get_target_tx_power(adapter, band, path, rs); + + if (target % 2) + DBG_871X_SEL(sel, "%7s: %2d.5\n", rate_section_str(rs), target / 2); + else + DBG_871X_SEL(sel, "%7s: %4d\n", rate_section_str(rs), target / 2); + } + } + } + +exit: + return; +} + +void dump_tx_power_by_rate(void *sel, _adapter *adapter) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + int path, tx_num, band, n, rs; + u8 rate_num, max_rate_num, base; + s8 by_rate_offset; + + for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) { + if (!hal_is_band_support(adapter, band)) + continue; + + for (path = 0; path < RF_PATH_MAX; path++) { + if (path >= hal_data->NumTotalRFPath) + break; + + DBG_871X_SEL_NL(sel, "[%s][%c]\n", band_str(band), rf_path_char(path)); + + for (rs = 0; rs < RATE_SECTION_NUM; rs++) { + tx_num = rate_section_to_tx_num(rs); + if (tx_num >= hal_spec->nss_num) + continue; + + if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs)) + continue; + + if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) + continue; + + if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) + max_rate_num = 10; + else + max_rate_num = 8; + rate_num = rate_section_rate_num(rs); + base = PHY_GetTxPowerByRateBase(adapter, band, path, tx_num, rs); + + DBG_871X_SEL_NL(sel, "%7s: ", rate_section_str(rs)); + + /* dump power by rate in db */ + for (n = rate_num - 1; n >= 0; n--) { + by_rate_offset = PHY_GetTxPowerByRate(adapter, band, path, tx_num, rates_by_sections[rs].rates[n]); + + if ((base + by_rate_offset) % 2) + DBG_871X_SEL(sel, "%2d.5 ", (base + by_rate_offset) / 2); + else + DBG_871X_SEL(sel, "%4d ", (base + by_rate_offset) / 2); + } + for (n = 0; n < max_rate_num - rate_num; n++) + DBG_871X_SEL(sel, "%4s ", ""); + + DBG_871X_SEL(sel, "|"); + + /* dump power by rate in offset */ + for (n = rate_num - 1; n >= 0; n--) { + by_rate_offset = PHY_GetTxPowerByRate(adapter, band, path, tx_num, rates_by_sections[rs].rates[n]); + DBG_871X_SEL(sel, "%3d ", by_rate_offset); + } + DBG_871X_SEL_NL(sel, "\n"); + + } + } + } +} + +void dump_tx_power_limit(void *sel, _adapter *adapter) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct registry_priv *regsty = dvobj_to_regsty(adapter_to_dvobj(adapter)); + + int bw, band, ch_num, rs, i, path; + u8 ch, n, rd; + + if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) + DBG_871X_SEL_NL(sel, "tx_pwr_lmt_5g_20_40_ref:0x%02x\n", hal_data->tx_pwr_lmt_5g_20_40_ref); + + for (band = BAND_ON_2_4G; band <= BAND_ON_5G; band++) { + if (!hal_is_band_support(adapter, band)) + continue; + + rd = (band == BAND_ON_2_4G ? hal_data->Regulation2_4G : hal_data->Regulation5G); + + for (bw = 0; bw < MAX_5G_BANDWIDTH_NUM; bw++) { + + if (bw >= CHANNEL_WIDTH_160) + break; + if (band == BAND_ON_2_4G && bw >= CHANNEL_WIDTH_80) + break; + + if (band == BAND_ON_2_4G) + ch_num = CENTER_CH_2G_NUM; + else + ch_num = center_chs_5g_num(bw); + + if (ch_num == 0) { + rtw_warn_on(1); + break; + } + + for (rs = 0; rs < RATE_SECTION_NUM; rs++) { + if (band == BAND_ON_2_4G && IS_VHT_RATE_SECTION(rs)) + continue; + if (band == BAND_ON_5G && IS_CCK_RATE_SECTION(rs)) + continue; + if (bw > CHANNEL_WIDTH_20 && (IS_CCK_RATE_SECTION(rs) || IS_OFDM_RATE_SECTION(rs))) + continue; + if (bw > CHANNEL_WIDTH_40 && IS_HT_RATE_SECTION(rs)) + continue; + + if (rate_section_to_tx_num(rs) >= hal_spec->nss_num) + continue; + + if (IS_VHT_RATE_SECTION(rs) && !IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(adapter)) + continue; + + /* by pass 5G 20M, 40M pure reference */ + if (band == BAND_ON_5G && (bw == CHANNEL_WIDTH_20 || bw == CHANNEL_WIDTH_40)) { + if (hal_data->tx_pwr_lmt_5g_20_40_ref == TX_PWR_LMT_REF_HT_FROM_VHT) { + if (IS_HT_RATE_SECTION(rs)) + continue; + } else if (hal_data->tx_pwr_lmt_5g_20_40_ref == TX_PWR_LMT_REF_VHT_FROM_HT) { + if (IS_VHT_RATE_SECTION(rs) && bw <= CHANNEL_WIDTH_40) + continue; + } + } + + DBG_871X_SEL_NL(sel, "[%s][%s][%s]\n" + , band_str(band) + , ch_width_str(bw) + , rate_section_str(rs) + ); + + /* header for limit in db */ + DBG_871X_SEL_NL(sel, "%3s %5s %5s %5s %5s " + , "ch" + , (rd == TXPWR_LMT_FCC ? "*FCC" : "FCC") + , (rd == TXPWR_LMT_ETSI ? "*ETSI" : "ETSI") + , (rd == TXPWR_LMT_MKK ? "*MKK" : "MKK") + , (rd == TXPWR_LMT_WW ? "*WW" : "WW") + ); + + /* header for limit offset */ + for (path = 0; path < RF_PATH_MAX; path++) { + if (path >= hal_data->NumTotalRFPath) + break; + DBG_871X_SEL(sel, "|%3c %3c %3c %3c " + , (rd == TXPWR_LMT_FCC ? rf_path_char(path) : ' ') + , (rd == TXPWR_LMT_ETSI ? rf_path_char(path) : ' ') + , (rd == TXPWR_LMT_MKK ? rf_path_char(path) : ' ') + , (rd == TXPWR_LMT_WW ? rf_path_char(path) : ' ') + ); + } + DBG_871X_SEL(sel, "\n"); + + for (n = 0; n < ch_num; n++) { + s8 limit_idx[RF_PATH_MAX][MAX_REGULATION_NUM]; + s8 limit_offset[MAX_REGULATION_NUM]; + u8 base; + + if (band == BAND_ON_2_4G) + ch = n + 1; + else + ch = center_chs_5g(bw, n); + + if (ch == 0) { + rtw_warn_on(1); + break; + } + + /* dump limit in db (calculate from path A) */ + limit_offset[0] = PHY_GetTxPowerLimit(adapter, 3, band, bw, RF_PATH_A, rates_by_sections[rs].rates[0], ch); /* FCC */ + limit_offset[1] = PHY_GetTxPowerLimit(adapter, 1, band, bw, RF_PATH_A, rates_by_sections[rs].rates[0], ch); /* ETSI */ + limit_offset[2] = PHY_GetTxPowerLimit(adapter, 2, band, bw, RF_PATH_A, rates_by_sections[rs].rates[0], ch); /* MKK */ + limit_offset[3] = PHY_GetTxPowerLimit(adapter, 4, band, bw, RF_PATH_A, rates_by_sections[rs].rates[0], ch); /* WW */ + + base = phy_get_target_tx_power(adapter, band, RF_PATH_A, rs); + + DBG_871X_SEL_NL(sel, "%3u ", ch); + for (i = 0; i < MAX_REGULATION_NUM; i++) { + if (limit_offset[i] == MAX_POWER_INDEX) { + limit_idx[0][i] = MAX_POWER_INDEX; + DBG_871X_SEL(sel, "%5s ", "NA"); + } else { + limit_idx[0][i] = limit_offset[i] + base; + if ((limit_offset[i] + base) % 2) + DBG_871X_SEL(sel, "%3d.5 ", (limit_offset[i] + base) / 2); + else + DBG_871X_SEL(sel, "%5d ", (limit_offset[i] + base) / 2); + } + } + + /* dump limit offset of each path */ + for (path = 0; path < RF_PATH_MAX; path++) { + if (path >= hal_data->NumTotalRFPath) + break; + limit_offset[0] = PHY_GetTxPowerLimit(adapter, 3, band, bw, path, rates_by_sections[rs].rates[0], ch); /* FCC */ + limit_offset[1] = PHY_GetTxPowerLimit(adapter, 1, band, bw, path, rates_by_sections[rs].rates[0], ch); /* ETSI */ + limit_offset[2] = PHY_GetTxPowerLimit(adapter, 2, band, bw, path, rates_by_sections[rs].rates[0], ch); /* MKK */ + limit_offset[3] = PHY_GetTxPowerLimit(adapter, 4, band, bw, path, rates_by_sections[rs].rates[0], ch); /* WW */ + + base = phy_get_target_tx_power(adapter, band, path, rs); + + DBG_871X_SEL(sel, "|"); + for (i = 0; i < MAX_REGULATION_NUM; i++) { + if (limit_offset[i] == MAX_POWER_INDEX) { + limit_idx[path][i] = MAX_POWER_INDEX; + DBG_871X_SEL(sel, "%3s ", "NA"); + } else { + limit_idx[path][i] = limit_offset[i] + base; + DBG_871X_SEL(sel, "%3d ", limit_offset[i]); + } + } + } + + /* compare limit_idx of each path, print 'x' when mismatch */ + if (hal_data->NumTotalRFPath > 1) { + for (i = 0; i < MAX_REGULATION_NUM; i++) { + for (path = 0; path < RF_PATH_MAX; path++) { + if (path >= hal_data->NumTotalRFPath) + break; + if (limit_idx[path][i] != limit_idx[(path + 1) % hal_data->NumTotalRFPath][i]) + break; + } + if (path >= hal_data->NumTotalRFPath) + DBG_871X_SEL(sel, " "); + else + DBG_871X_SEL(sel, "x"); + } + } + DBG_871X_SEL(sel, "\n"); + + } + DBG_871X_SEL_NL(sel, "\n"); + } + } + } +} + +/* + * phy file path is stored in global char array rtw_phy_para_file_path + * need to care about racing + */ +int rtw_get_phy_file_path(_adapter *adapter, const char *file_name) +{ +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + int len = 0; + + if (file_name) { + len += snprintf(rtw_phy_para_file_path, PATH_LENGTH_MAX, "%s", rtw_phy_file_path); + #if defined(CONFIG_MULTIDRV) || defined(REALTEK_CONFIG_PATH_WITH_IC_NAME_FOLDER) + len += snprintf(rtw_phy_para_file_path + len, PATH_LENGTH_MAX - len, "%s/", hal_spec->ic_name); + #endif + len += snprintf(rtw_phy_para_file_path + len, PATH_LENGTH_MAX - len, "%s", file_name); + + return _TRUE; + } +#endif + return _FALSE; +} + +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE +int +phy_ConfigMACWithParaFile( + IN PADAPTER Adapter, + IN char* pFileName +) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + int rlen = 0, rtStatus = _FAIL; + char *szLine, *ptmp; + u32 u4bRegOffset, u4bRegValue, u4bMove; + + if(!(Adapter->registrypriv.load_phy_file & LOAD_MAC_PARA_FILE)) + return rtStatus; + + _rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN); + + if ((pHalData->mac_reg_len == 0) && (pHalData->mac_reg == NULL)) + { + rtw_get_phy_file_path(Adapter, pFileName); + if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) + { + rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN); + if (rlen > 0) + { + rtStatus = _SUCCESS; + pHalData->mac_reg = rtw_zvmalloc(rlen); + if(pHalData->mac_reg) { + _rtw_memcpy(pHalData->mac_reg, pHalData->para_file_buf, rlen); + pHalData->mac_reg_len = rlen; + } + else { + DBG_871X("%s mac_reg alloc fail !\n",__FUNCTION__); + } + } + } + } + else + { + if ((pHalData->mac_reg_len != 0) && (pHalData->mac_reg != NULL)) { + _rtw_memcpy(pHalData->para_file_buf, pHalData->mac_reg, pHalData->mac_reg_len); + rtStatus = _SUCCESS; + } + else { + DBG_871X("%s(): Critical Error !!!\n",__FUNCTION__); + } + } + + if (rtStatus == _SUCCESS) + { + ptmp = pHalData->para_file_buf; + for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) + { + if(!IsCommentString(szLine)) + { + // Get 1st hex value as register offset + if(GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) + { + if(u4bRegOffset == 0xffff) + { // Ending. + break; + } + + // Get 2nd hex value as register value. + szLine += u4bMove; + if(GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) + { + rtw_write8(Adapter, u4bRegOffset, (u8)u4bRegValue); + } + } + } + } + } + else + { + DBG_871X("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName); + } + + return rtStatus; +} + +int +phy_ConfigBBWithParaFile( + IN PADAPTER Adapter, + IN char* pFileName, + IN u32 ConfigType +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + int rlen = 0, rtStatus = _FAIL; + char *szLine, *ptmp; + u32 u4bRegOffset, u4bRegValue, u4bMove; + char *pBuf = NULL; + u32 *pBufLen = NULL; + + if(!(Adapter->registrypriv.load_phy_file & LOAD_BB_PARA_FILE)) + return rtStatus; + + switch(ConfigType) + { + case CONFIG_BB_PHY_REG: + pBuf = pHalData->bb_phy_reg; + pBufLen = &pHalData->bb_phy_reg_len; + break; + case CONFIG_BB_AGC_TAB: + pBuf = pHalData->bb_agc_tab; + pBufLen = &pHalData->bb_agc_tab_len; + break; + default: + DBG_871X("Unknown ConfigType!! %d\r\n", ConfigType); + break; + } + + _rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN); + + if ((pBufLen != NULL) && (*pBufLen == 0) && (pBuf == NULL)) + { + rtw_get_phy_file_path(Adapter, pFileName); + if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) + { + rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN); + if (rlen > 0) + { + rtStatus = _SUCCESS; + pBuf = rtw_zvmalloc(rlen); + if(pBuf) { + _rtw_memcpy(pBuf, pHalData->para_file_buf, rlen); + *pBufLen = rlen; + + switch(ConfigType) + { + case CONFIG_BB_PHY_REG: + pHalData->bb_phy_reg = pBuf; + break; + case CONFIG_BB_AGC_TAB: + pHalData->bb_agc_tab = pBuf; + break; + } + } + else { + DBG_871X("%s(): ConfigType %d alloc fail !\n",__FUNCTION__,ConfigType); + } + } + } + } + else + { + if ((pBufLen != NULL) && (*pBufLen != 0) && (pBuf != NULL)) { + _rtw_memcpy(pHalData->para_file_buf, pBuf, *pBufLen); + rtStatus = _SUCCESS; + } + else { + DBG_871X("%s(): Critical Error !!!\n",__FUNCTION__); + } + } + + if (rtStatus == _SUCCESS) + { + ptmp = pHalData->para_file_buf; + for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) + { + if(!IsCommentString(szLine)) + { + // Get 1st hex value as register offset. + if(GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) + { + if(u4bRegOffset == 0xffff) + { // Ending. + break; + } + else if (u4bRegOffset == 0xfe || u4bRegOffset == 0xffe) + { + #ifdef CONFIG_LONG_DELAY_ISSUE + rtw_msleep_os(50); + #else + rtw_mdelay_os(50); + #endif + } + else if (u4bRegOffset == 0xfd) + { + rtw_mdelay_os(5); + } + else if (u4bRegOffset == 0xfc) + { + rtw_mdelay_os(1); + } + else if (u4bRegOffset == 0xfb) + { + rtw_udelay_os(50); + } + else if (u4bRegOffset == 0xfa) + { + rtw_udelay_os(5); + } + else if (u4bRegOffset == 0xf9) + { + rtw_udelay_os(1); + } + + // Get 2nd hex value as register value. + szLine += u4bMove; + if(GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) + { + //DBG_871X("[BB-ADDR]%03lX=%08lX\n", u4bRegOffset, u4bRegValue); + PHY_SetBBReg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue); + + if (u4bRegOffset == 0xa24) + pHalData->odmpriv.RFCalibrateInfo.RegA24 = u4bRegValue; + + // Add 1us delay between BB/RF register setting. + rtw_udelay_os(1); + } + } + } + } + } + else + { + DBG_871X("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName); + } + + return rtStatus; +} + +VOID +phy_DecryptBBPgParaFile( + PADAPTER Adapter, + char* buffer + ) +{ + u32 i = 0, j = 0; + u8 map[95] = {0}; + u8 currentChar; + char *BufOfLines, *ptmp; + + //DBG_871X("=====>phy_DecryptBBPgParaFile()\n"); + // 32 the ascii code of the first visable char, 126 the last one + for ( i = 0; i < 95; ++i ) + map[i] = ( u8 ) ( 94 - i ); + + ptmp = buffer; + i = 0; + for (BufOfLines = GetLineFromBuffer(ptmp); BufOfLines != NULL; BufOfLines = GetLineFromBuffer(ptmp)) + { + //DBG_871X("Encrypted Line: %s\n", BufOfLines); + + for ( j = 0; j < strlen(BufOfLines); ++j ) + { + currentChar = BufOfLines[j]; + + if ( currentChar == '\0' ) + break; + + currentChar -= (u8) ( ( ( ( i + j ) * 3 ) % 128 ) ); + + BufOfLines[j] = map[currentChar - 32] + 32; + } + //DBG_871X("Decrypted Line: %s\n", BufOfLines ); + if (strlen(BufOfLines) != 0) + i++; + BufOfLines[strlen(BufOfLines)] = '\n'; + } +} + +int +phy_ParseBBPgParaFile( + PADAPTER Adapter, + char* buffer + ) +{ + int rtStatus = _SUCCESS; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + char *szLine, *ptmp; + u32 u4bRegOffset, u4bRegMask, u4bRegValue; + u32 u4bMove; + BOOLEAN firstLine = _TRUE; + u8 tx_num = 0; + u8 band = 0, rf_path = 0; + + //DBG_871X("=====>phy_ParseBBPgParaFile()\n"); + + if ( Adapter->registrypriv.RegDecryptCustomFile == 1 ) + phy_DecryptBBPgParaFile( Adapter, buffer); + + ptmp = buffer; + for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) + { + if (isAllSpaceOrTab(szLine, sizeof(*szLine))) + continue; + + if(!IsCommentString(szLine)) + { + // Get header info (relative value or exact value) + if ( firstLine ) + { + if ( eqNByte( szLine, (u8 *)("#[v1]"), 5 ) ) + { + + pHalData->odmpriv.PhyRegPgVersion = szLine[3] - '0'; + //DBG_871X("This is a new format PHY_REG_PG.txt \n"); + } + else if ( eqNByte( szLine, (u8 *)("#[v0]"), 5 )) + { + pHalData->odmpriv.PhyRegPgVersion = szLine[3] - '0'; + //DBG_871X("This is a old format PHY_REG_PG.txt ok\n"); + } + else + { + DBG_871X("The format in PHY_REG_PG are invalid %s\n", szLine); + return _FAIL; + } + + if ( eqNByte( szLine + 5, (u8 *)("[Exact]#"), 8 ) ) + { + pHalData->odmpriv.PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + //DBG_871X("The values in PHY_REG_PG are exact values ok\n"); + firstLine = _FALSE; + continue; + } + else if ( eqNByte( szLine + 5, (pu1Byte)("[Relative]#"), 11 ) ) + { + pHalData->odmpriv.PhyRegPgValueType = PHY_REG_PG_RELATIVE_VALUE; + //DBG_871X("The values in PHY_REG_PG are relative values ok\n"); + firstLine = _FALSE; + continue; + } + else + { + DBG_871X("The values in PHY_REG_PG are invalid %s\n", szLine); + return _FAIL; + } + } + + if ( pHalData->odmpriv.PhyRegPgVersion == 0 ) + { + // Get 1st hex value as register offset. + if(GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) + { + szLine += u4bMove; + if(u4bRegOffset == 0xffff) + { // Ending. + break; + } + + // Get 2nd hex value as register mask. + if ( GetHexValueFromString(szLine, &u4bRegMask, &u4bMove) ) + szLine += u4bMove; + else + return _FAIL; + + if ( pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_RELATIVE_VALUE ) + { + // Get 3rd hex value as register value. + if(GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) + { + PHY_StoreTxPowerByRate(Adapter, 0, 0, 1, u4bRegOffset, u4bRegMask, u4bRegValue); + //DBG_871X("[ADDR] %03X=%08X Mask=%08x\n", u4bRegOffset, u4bRegValue, u4bRegMask); + } + else + { + return _FAIL; + } + } + else if ( pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_EXACT_VALUE ) + { + u32 combineValue = 0; + u8 integer = 0, fraction = 0; + + if ( GetFractionValueFromString( szLine, &integer, &fraction, &u4bMove ) ) + szLine += u4bMove; + else + return _FAIL; + + integer *= 2; + if ( fraction == 5 ) integer += 1; + combineValue |= ( ( ( integer / 10 ) << 4 ) + ( integer % 10 ) ); + //DBG_871X(" %d", integer ); + + if ( GetFractionValueFromString( szLine, &integer, &fraction, &u4bMove ) ) + szLine += u4bMove; + else + return _FAIL; + + integer *= 2; + if ( fraction == 5 ) integer += 1; + combineValue <<= 8; + combineValue |= ( ( ( integer / 10 ) << 4 ) + ( integer % 10 ) ); + //DBG_871X(" %d", integer ); + + if ( GetFractionValueFromString( szLine, &integer, &fraction, &u4bMove ) ) + szLine += u4bMove; + else + return _FAIL; + + integer *= 2; + if ( fraction == 5 ) integer += 1; + combineValue <<= 8; + combineValue |= ( ( ( integer / 10 ) << 4 ) + ( integer % 10 ) ); + //DBG_871X(" %d", integer ); + + if ( GetFractionValueFromString( szLine, &integer, &fraction, &u4bMove ) ) + szLine += u4bMove; + else + return _FAIL; + + integer *= 2; + if ( fraction == 5 ) integer += 1; + combineValue <<= 8; + combineValue |= ( ( ( integer / 10 ) << 4 ) + ( integer % 10 ) ); + //DBG_871X(" %d", integer ); + PHY_StoreTxPowerByRate(Adapter, 0, 0, 1, u4bRegOffset, u4bRegMask, combineValue); + + //DBG_871X("[ADDR] 0x%3x = 0x%4x\n", u4bRegOffset, combineValue ); + } + } + } + else if ( pHalData->odmpriv.PhyRegPgVersion > 0 ) + { + u32 index = 0, cnt = 0; + + if ( eqNByte( szLine, "0xffff", 6 ) ) + break; + + if( !eqNByte( "#[END]#", szLine, 7 ) ) + { + // load the table label info + if ( szLine[0] == '#' ) + { + index = 0; + if ( eqNByte( szLine, "#[2.4G]" , 7 ) ) + { + band = BAND_ON_2_4G; + index += 8; + } + else if ( eqNByte( szLine, "#[5G]", 5) ) + { + band = BAND_ON_5G; + index += 6; + } + else + { + DBG_871X("Invalid band %s in PHY_REG_PG.txt \n", szLine ); + return _FAIL; + } + + rf_path= szLine[index] - 'A'; + //DBG_871X(" Table label Band %d, RfPath %d\n", band, rf_path ); + } + else // load rows of tables + { + if ( szLine[1] == '1' ) + tx_num = RF_1TX; + else if ( szLine[1] == '2' ) + tx_num = RF_2TX; + else if ( szLine[1] == '3' ) + tx_num = RF_3TX; + else if ( szLine[1] == '4' ) + tx_num = RF_4TX; + else + { + DBG_871X("Invalid row in PHY_REG_PG.txt '%c'(%d)\n", szLine[1], szLine[1]); + return _FAIL; + } + + while ( szLine[index] != ']' ) + ++index; + ++index;// skip ] + + // Get 2nd hex value as register offset. + szLine += index; + if ( GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove) ) + szLine += u4bMove; + else + return _FAIL; + + // Get 2nd hex value as register mask. + if ( GetHexValueFromString(szLine, &u4bRegMask, &u4bMove) ) + szLine += u4bMove; + else + return _FAIL; + + if ( pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_RELATIVE_VALUE ) + { + // Get 3rd hex value as register value. + if(GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) + { + PHY_StoreTxPowerByRate(Adapter, band, rf_path, tx_num, u4bRegOffset, u4bRegMask, u4bRegValue); + //DBG_871X("[ADDR] %03X (tx_num %d) =%08X Mask=%08x\n", u4bRegOffset, tx_num, u4bRegValue, u4bRegMask); + } + else + { + return _FAIL; + } + } + else if ( pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_EXACT_VALUE ) + { + u32 combineValue = 0; + u8 integer = 0, fraction = 0; + + if ( GetFractionValueFromString( szLine, &integer, &fraction, &u4bMove ) ) + szLine += u4bMove; + else + return _FAIL; + + integer *= 2; + if ( fraction == 5 ) integer += 1; + combineValue |= ( ( ( integer / 10 ) << 4 ) + ( integer % 10 ) ); + //DBG_871X(" %d", integer ); + + if ( GetFractionValueFromString( szLine, &integer, &fraction, &u4bMove ) ) + szLine += u4bMove; + else + return _FAIL; + + integer *= 2; + if ( fraction == 5 ) integer += 1; + combineValue <<= 8; + combineValue |= ( ( ( integer / 10 ) << 4 ) + ( integer % 10 ) ); + //DBG_871X(" %d", integer ); + + if ( GetFractionValueFromString( szLine, &integer, &fraction, &u4bMove ) ) + szLine += u4bMove; + else + return _FAIL; + + integer *= 2; + if ( fraction == 5 ) integer += 1; + combineValue <<= 8; + combineValue |= ( ( ( integer / 10 ) << 4 ) + ( integer % 10 ) ); + //DBG_871X(" %d", integer ); + + if ( GetFractionValueFromString( szLine, &integer, &fraction, &u4bMove ) ) + szLine += u4bMove; + else + return _FAIL; + + integer *= 2; + if ( fraction == 5 ) integer += 1; + combineValue <<= 8; + combineValue |= ( ( ( integer / 10 ) << 4 ) + ( integer % 10 ) ); + //DBG_871X(" %d", integer ); + PHY_StoreTxPowerByRate(Adapter, band, rf_path, tx_num, u4bRegOffset, u4bRegMask, combineValue); + + //DBG_871X("[ADDR] 0x%3x (tx_num %d) = 0x%4x\n", u4bRegOffset, tx_num, combineValue ); + } + } + } + } + } + } + //DBG_871X("<=====phy_ParseBBPgParaFile()\n"); + return rtStatus; +} + +int +phy_ConfigBBWithPgParaFile( + IN PADAPTER Adapter, + IN const char *pFileName) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + int rlen = 0, rtStatus = _FAIL; + + if(!(Adapter->registrypriv.load_phy_file & LOAD_BB_PG_PARA_FILE)) + return rtStatus; + + _rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN); + + if (pHalData->bb_phy_reg_pg == NULL) { + rtw_get_phy_file_path(Adapter, pFileName); + if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) + { + rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN); + if (rlen > 0) + { + rtStatus = _SUCCESS; + pHalData->bb_phy_reg_pg = rtw_zvmalloc(rlen); + if(pHalData->bb_phy_reg_pg) { + _rtw_memcpy(pHalData->bb_phy_reg_pg, pHalData->para_file_buf, rlen); + pHalData->bb_phy_reg_pg_len = rlen; + } + else { + DBG_871X("%s bb_phy_reg_pg alloc fail !\n",__FUNCTION__); + } + } + } + } else { + if ((pHalData->bb_phy_reg_pg_len != 0) && (pHalData->bb_phy_reg_pg != NULL)) { + _rtw_memcpy(pHalData->para_file_buf, pHalData->bb_phy_reg_pg, pHalData->bb_phy_reg_pg_len); + rtStatus = _SUCCESS; + } + else { + DBG_871X("%s(): Critical Error !!!\n",__FUNCTION__); + } + } + + if(rtStatus == _SUCCESS) + { + //DBG_871X("phy_ConfigBBWithPgParaFile(): read %s ok\n", pFileName); + phy_ParseBBPgParaFile(Adapter, pHalData->para_file_buf); + } + else + { + DBG_871X("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName); + } + + return rtStatus; +} + +#if (MP_DRIVER == 1 ) + +int +phy_ConfigBBWithMpParaFile( + IN PADAPTER Adapter, + IN char* pFileName +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + int rlen = 0, rtStatus = _FAIL; + char *szLine, *ptmp; + u32 u4bRegOffset, u4bRegValue, u4bMove; + + if(!(Adapter->registrypriv.load_phy_file & LOAD_BB_MP_PARA_FILE)) + return rtStatus; + + _rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN); + + if ((pHalData->bb_phy_reg_mp_len == 0) && (pHalData->bb_phy_reg_mp == NULL)) + { + rtw_get_phy_file_path(Adapter, pFileName); + if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) + { + rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN); + if (rlen > 0) + { + rtStatus = _SUCCESS; + pHalData->bb_phy_reg_mp = rtw_zvmalloc(rlen); + if(pHalData->bb_phy_reg_mp) { + _rtw_memcpy(pHalData->bb_phy_reg_mp, pHalData->para_file_buf, rlen); + pHalData->bb_phy_reg_mp_len = rlen; + } + else { + DBG_871X("%s bb_phy_reg_mp alloc fail !\n",__FUNCTION__); + } + } + } + } + else + { + if ((pHalData->bb_phy_reg_mp_len != 0) && (pHalData->bb_phy_reg_mp != NULL)) { + _rtw_memcpy(pHalData->para_file_buf, pHalData->bb_phy_reg_mp, pHalData->bb_phy_reg_mp_len); + rtStatus = _SUCCESS; + } + else { + DBG_871X("%s(): Critical Error !!!\n",__FUNCTION__); + } + } + + if(rtStatus == _SUCCESS) + { + //DBG_871X("phy_ConfigBBWithMpParaFile(): read %s ok\n", pFileName); + + ptmp = pHalData->para_file_buf; + for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) + { + if(!IsCommentString(szLine)) + { + // Get 1st hex value as register offset. + if(GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) + { + if(u4bRegOffset == 0xffff) + { // Ending. + break; + } + else if (u4bRegOffset == 0xfe || u4bRegOffset == 0xffe) + { + #ifdef CONFIG_LONG_DELAY_ISSUE + rtw_msleep_os(50); + #else + rtw_mdelay_os(50); + #endif + } + else if (u4bRegOffset == 0xfd) + { + rtw_mdelay_os(5); + } + else if (u4bRegOffset == 0xfc) + { + rtw_mdelay_os(1); + } + else if (u4bRegOffset == 0xfb) + { + rtw_udelay_os(50); + } + else if (u4bRegOffset == 0xfa) + { + rtw_udelay_os(5); + } + else if (u4bRegOffset == 0xf9) + { + rtw_udelay_os(1); + } + + // Get 2nd hex value as register value. + szLine += u4bMove; + if(GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) + { + //DBG_871X("[ADDR]%03lX=%08lX\n", u4bRegOffset, u4bRegValue); + PHY_SetBBReg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue); + + // Add 1us delay between BB/RF register setting. + rtw_udelay_os(1); + } + } + } + } + } + else + { + DBG_871X("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName); + } + + return rtStatus; +} + +#endif + +int +PHY_ConfigRFWithParaFile( + IN PADAPTER Adapter, + IN char* pFileName, + IN u8 eRFPath +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + int rlen = 0, rtStatus = _FAIL; + char *szLine, *ptmp; + u32 u4bRegOffset, u4bRegValue, u4bMove; + u16 i; + char *pBuf = NULL; + u32 *pBufLen = NULL; + + if(!(Adapter->registrypriv.load_phy_file & LOAD_RF_PARA_FILE)) + return rtStatus; + + switch(eRFPath) + { + case ODM_RF_PATH_A: + pBuf = pHalData->rf_radio_a; + pBufLen = &pHalData->rf_radio_a_len; + break; + case ODM_RF_PATH_B: + pBuf = pHalData->rf_radio_b; + pBufLen = &pHalData->rf_radio_b_len; + break; + default: + DBG_871X("Unknown RF path!! %d\r\n", eRFPath); + break; + } + + _rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN); + + if ((pBufLen != NULL) && (*pBufLen == 0) && (pBuf == NULL)) + { + rtw_get_phy_file_path(Adapter, pFileName); + if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) + { + rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN); + if (rlen > 0) + { + rtStatus = _SUCCESS; + pBuf = rtw_zvmalloc(rlen); + if(pBuf) { + _rtw_memcpy(pBuf, pHalData->para_file_buf, rlen); + *pBufLen = rlen; + + switch(eRFPath) + { + case ODM_RF_PATH_A: + pHalData->rf_radio_a = pBuf; + break; + case ODM_RF_PATH_B: + pHalData->rf_radio_b = pBuf; + break; + } + } + else { + DBG_871X("%s(): eRFPath=%d alloc fail !\n",__FUNCTION__,eRFPath); + } + } + } + } + else + { + if ((pBufLen != NULL) && (*pBufLen != 0) && (pBuf != NULL)) { + _rtw_memcpy(pHalData->para_file_buf, pBuf, *pBufLen); + rtStatus = _SUCCESS; + } + else { + DBG_871X("%s(): Critical Error !!!\n",__FUNCTION__); + } + } + + if(rtStatus == _SUCCESS) + { + //DBG_871X("%s(): read %s successfully\n", __FUNCTION__, pFileName); + + ptmp = pHalData->para_file_buf; + for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) + { + if(!IsCommentString(szLine)) + { + // Get 1st hex value as register offset. + if(GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) + { + if(u4bRegOffset == 0xfe || u4bRegOffset == 0xffe) + { // Deay specific ms. Only RF configuration require delay. + #ifdef CONFIG_LONG_DELAY_ISSUE + rtw_msleep_os(50); + #else + rtw_mdelay_os(50); + #endif + } + else if (u4bRegOffset == 0xfd) + { + //delay_ms(5); + for(i=0;i<100;i++) + rtw_udelay_os(MAX_STALL_TIME); + } + else if (u4bRegOffset == 0xfc) + { + //delay_ms(1); + for(i=0;i<20;i++) + rtw_udelay_os(MAX_STALL_TIME); + } + else if (u4bRegOffset == 0xfb) + { + rtw_udelay_os(50); + } + else if (u4bRegOffset == 0xfa) + { + rtw_udelay_os(5); + } + else if (u4bRegOffset == 0xf9) + { + rtw_udelay_os(1); + } + else if(u4bRegOffset == 0xffff) + { + break; + } + + // Get 2nd hex value as register value. + szLine += u4bMove; + if(GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) + { + PHY_SetRFReg(Adapter, eRFPath, u4bRegOffset, bRFRegOffsetMask, u4bRegValue); + + // Temp add, for frequency lock, if no delay, that may cause + // frequency shift, ex: 2412MHz => 2417MHz + // If frequency shift, the following action may works. + // Fractional-N table in radio_a.txt + //0x2a 0x00001 // channel 1 + //0x2b 0x00808 frequency divider. + //0x2b 0x53333 + //0x2c 0x0000c + rtw_udelay_os(1); + } + } + } + } + } + else + { + DBG_871X("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName); + } + + return rtStatus; +} + +VOID +initDeltaSwingIndexTables( + PADAPTER Adapter, + char* Band, + char* Path, + char* Sign, + char* Channel, + char* Rate, + char* Data +) +{ + #define STR_EQUAL_5G(_band, _path, _sign, _rate, _chnl) \ + ((strcmp(Band, _band) == 0) && (strcmp(Path, _path) == 0) && (strcmp(Sign, _sign) == 0) &&\ + (strcmp(Rate, _rate) == 0) && (strcmp(Channel, _chnl) == 0)\ + ) + #define STR_EQUAL_2G(_band, _path, _sign, _rate) \ + ((strcmp(Band, _band) == 0) && (strcmp(Path, _path) == 0) && (strcmp(Sign, _sign) == 0) &&\ + (strcmp(Rate, _rate) == 0)\ + ) + + #define STORE_SWING_TABLE(_array, _iteratedIdx) \ + for(token = strsep(&Data, delim); token != NULL; token = strsep(&Data, delim))\ + {\ + sscanf(token, "%d", &idx);\ + _array[_iteratedIdx++] = (u8)idx;\ + }\ + + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + u32 j = 0; + char *token; + char delim[] = ","; + u32 idx = 0; + + //DBG_871X("===>initDeltaSwingIndexTables(): Band: %s;\nPath: %s;\nSign: %s;\nChannel: %s;\nRate: %s;\n, Data: %s;\n", + // Band, Path, Sign, Channel, Rate, Data); + + if ( STR_EQUAL_2G("2G", "A", "+", "CCK") ) + { + STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, j); + } + else if ( STR_EQUAL_2G("2G", "A", "-", "CCK") ) + { + STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, j); + } + else if ( STR_EQUAL_2G("2G", "B", "+", "CCK") ) + { + STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, j); + } + else if ( STR_EQUAL_2G("2G", "B", "-", "CCK") ) + { + STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, j); + } + else if ( STR_EQUAL_2G("2G", "A", "+", "ALL") ) + { + STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, j); + } + else if ( STR_EQUAL_2G("2G", "A", "-", "ALL") ) + { + STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, j); + } + else if ( STR_EQUAL_2G("2G", "B", "+", "ALL") ) + { + STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, j); + } + else if ( STR_EQUAL_2G("2G", "B", "-", "ALL") ) + { + STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, j); + } + else if ( STR_EQUAL_5G("5G", "A", "+", "ALL", "0") ) + { + STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0], j); + } + else if ( STR_EQUAL_5G("5G", "A", "-", "ALL", "0") ) + { + STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0], j); + } + else if ( STR_EQUAL_5G("5G", "B", "+", "ALL", "0") ) + { + STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0], j); + } + else if ( STR_EQUAL_5G("5G", "B", "-", "ALL", "0") ) + { + STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0], j); + } + else if ( STR_EQUAL_5G("5G", "A", "+", "ALL", "1") ) + { + STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1], j); + } + else if ( STR_EQUAL_5G("5G", "A", "-", "ALL", "1") ) + { + STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1], j); + } + else if ( STR_EQUAL_5G("5G", "B", "+", "ALL", "1") ) + { + STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1], j); + } + else if ( STR_EQUAL_5G("5G", "B", "-", "ALL", "1") ) + { + STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1], j); + } + else if ( STR_EQUAL_5G("5G", "A", "+", "ALL", "2") ) + { + STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2], j); + } + else if ( STR_EQUAL_5G("5G", "A", "-", "ALL", "2") ) + { + STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2], j); + } + else if ( STR_EQUAL_5G("5G", "B", "+", "ALL", "2") ) + { + STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2], j); + } + else if ( STR_EQUAL_5G("5G", "B", "-", "ALL", "2") ) + { + STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2], j); + } + else if ( STR_EQUAL_5G("5G", "A", "+", "ALL", "3") ) + { + STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[3], j); + } + else if ( STR_EQUAL_5G("5G", "A", "-", "ALL", "3") ) + { + STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[3], j); + } + else if ( STR_EQUAL_5G("5G", "B", "+", "ALL", "3") ) + { + STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[3], j); + } + else if ( STR_EQUAL_5G("5G", "B", "-", "ALL", "3") ) + { + STORE_SWING_TABLE(pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[3], j); + } + else + { + DBG_871X("===>initDeltaSwingIndexTables(): The input is invalid!!\n"); + } +} + +int +PHY_ConfigRFWithTxPwrTrackParaFile( + IN PADAPTER Adapter, + IN char* pFileName +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + int rlen = 0, rtStatus = _FAIL; + char *szLine, *ptmp; + u32 i = 0, j = 0; + char c = 0; + + if(!(Adapter->registrypriv.load_phy_file & LOAD_RF_TXPWR_TRACK_PARA_FILE)) + return rtStatus; + + _rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN); + + if ((pHalData->rf_tx_pwr_track_len == 0) && (pHalData->rf_tx_pwr_track == NULL)) + { + rtw_get_phy_file_path(Adapter, pFileName); + if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) + { + rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN); + if (rlen > 0) + { + rtStatus = _SUCCESS; + pHalData->rf_tx_pwr_track = rtw_zvmalloc(rlen); + if(pHalData->rf_tx_pwr_track) { + _rtw_memcpy(pHalData->rf_tx_pwr_track, pHalData->para_file_buf, rlen); + pHalData->rf_tx_pwr_track_len = rlen; + } + else { + DBG_871X("%s rf_tx_pwr_track alloc fail !\n",__FUNCTION__); + } + } + } + } + else + { + if ((pHalData->rf_tx_pwr_track_len != 0) && (pHalData->rf_tx_pwr_track != NULL)) { + _rtw_memcpy(pHalData->para_file_buf, pHalData->rf_tx_pwr_track, pHalData->rf_tx_pwr_track_len); + rtStatus = _SUCCESS; + } + else { + DBG_871X("%s(): Critical Error !!!\n",__FUNCTION__); + } + } + + if(rtStatus == _SUCCESS) + { + //DBG_871X("%s(): read %s successfully\n", __FUNCTION__, pFileName); + + ptmp = pHalData->para_file_buf; + for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) + { + if ( ! IsCommentString(szLine) ) + { + char band[5]="", path[5]="", sign[5] = ""; + char chnl[5]="", rate[10]=""; + char data[300]=""; // 100 is too small + + if (strlen(szLine) < 10 || szLine[0] != '[') + continue; + + strncpy(band, szLine+1, 2); + strncpy(path, szLine+5, 1); + strncpy(sign, szLine+8, 1); + + i = 10; // szLine+10 + if ( ! ParseQualifiedString(szLine, &i, rate, '[', ']') ) { + //DBG_871X("Fail to parse rate!\n"); + } + if ( ! ParseQualifiedString(szLine, &i, chnl, '[', ']') ) { + //DBG_871X("Fail to parse channel group!\n"); + } + while ( szLine[i] != '{' && i < strlen(szLine)) + i++; + if ( ! ParseQualifiedString(szLine, &i, data, '{', '}') ) { + //DBG_871X("Fail to parse data!\n"); + } + + initDeltaSwingIndexTables(Adapter, band, path, sign, chnl, rate, data); + } + } + } + else + { + DBG_871X("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName); + } +#if 0 + for (i = 0; i < DELTA_SWINGIDX_SIZE; ++i) + { + DBG_871X("pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P[%d] = %d\n", i, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P[i]); + DBG_871X("pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N[%d] = %d\n", i, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N[i]); + DBG_871X("pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P[%d] = %d\n", i, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P[i]); + DBG_871X("pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N[%d] = %d\n", i, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N[i]); + DBG_871X("pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P[%d] = %d\n", i, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P[i]); + DBG_871X("pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N[%d] = %d\n", i, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N[i]); + DBG_871X("pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P[%d] = %d\n", i, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P[i]); + DBG_871X("pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N[%d] = %d\n", i, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N[i]); + + for (j = 0; j < 3; ++j) + { + DBG_871X("pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[%d][%d] = %d\n", j, i, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[j][i]); + DBG_871X("pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[%d][%d] = %d\n", j, i, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[j][i]); + DBG_871X("pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[%d][%d] = %d\n", j, i, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[j][i]); + DBG_871X("pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[%d][%d] = %d\n", j, i, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[j][i]); + } + } +#endif + return rtStatus; +} + +int +phy_ParsePowerLimitTableFile( + PADAPTER Adapter, + char* buffer +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + u32 i = 0, forCnt = 0; + u8 loadingStage = 0, limitValue = 0, fraction = 0; + char *szLine, *ptmp; + int rtStatus = _SUCCESS; + char band[10], bandwidth[10], rateSection[10], + regulation[TXPWR_LMT_MAX_REGULATION_NUM][10], rfPath[10],colNumBuf[10]; + u8 colNum = 0; + + DBG_871X("===>phy_ParsePowerLimitTableFile()\n" ); + + if ( Adapter->registrypriv.RegDecryptCustomFile == 1 ) + phy_DecryptBBPgParaFile( Adapter, buffer); + + ptmp = buffer; + for (szLine = GetLineFromBuffer(ptmp); szLine != NULL; szLine = GetLineFromBuffer(ptmp)) + { + if (isAllSpaceOrTab(szLine, sizeof(*szLine))) + continue; + + // skip comment + if ( IsCommentString( szLine ) ) { + continue; + } + + if( loadingStage == 0 ) { + for ( forCnt = 0; forCnt < TXPWR_LMT_MAX_REGULATION_NUM; ++forCnt ) + _rtw_memset( ( PVOID ) regulation[forCnt], 0, 10 ); + _rtw_memset( ( PVOID ) band, 0, 10 ); + _rtw_memset( ( PVOID ) bandwidth, 0, 10 ); + _rtw_memset( ( PVOID ) rateSection, 0, 10 ); + _rtw_memset( ( PVOID ) rfPath, 0, 10 ); + _rtw_memset( ( PVOID ) colNumBuf, 0, 10 ); + + if ( szLine[0] != '#' || szLine[1] != '#' ) + continue; + + // skip the space + i = 2; + while ( szLine[i] == ' ' || szLine[i] == '\t' ) + ++i; + + szLine[--i] = ' '; // return the space in front of the regulation info + + // Parse the label of the table + if ( ! ParseQualifiedString( szLine, &i, band, ' ', ',' ) ) { + DBG_871X( "Fail to parse band!\n"); + return _FAIL; + } + if ( ! ParseQualifiedString( szLine, &i, bandwidth, ' ', ',' ) ) { + DBG_871X("Fail to parse bandwidth!\n"); + return _FAIL; + } + if ( ! ParseQualifiedString( szLine, &i, rfPath, ' ', ',' ) ) { + DBG_871X("Fail to parse rf path!\n"); + return _FAIL; + } + if ( ! ParseQualifiedString( szLine, &i, rateSection, ' ', ',' ) ) { + DBG_871X("Fail to parse rate!\n"); + return _FAIL; + } + + loadingStage = 1; + } + else if ( loadingStage == 1 ) + { + if ( szLine[0] != '#' || szLine[1] != '#' ) + continue; + + // skip the space + i = 2; + while ( szLine[i] == ' ' || szLine[i] == '\t' ) + ++i; + + if ( !eqNByte( (u8 *)(szLine + i), (u8 *)("START"), 5 ) ) { + DBG_871X("Lost \"## START\" label\n"); + return _FAIL; + } + + loadingStage = 2; + } + else if ( loadingStage == 2 ) + { + if ( szLine[0] != '#' || szLine[1] != '#' ) + continue; + + // skip the space + i = 2; + while ( szLine[i] == ' ' || szLine[i] == '\t' ) + ++i; + + if ( ! ParseQualifiedString( szLine, &i, colNumBuf, '#', '#' ) ) { + DBG_871X("Fail to parse column number!\n"); + return _FAIL; + } + + if ( !GetU1ByteIntegerFromStringInDecimal( colNumBuf, &colNum ) ) + return _FAIL; + + if ( colNum > TXPWR_LMT_MAX_REGULATION_NUM ) { + DBG_871X("unvalid col number %d (greater than max %d)\n", + colNum, TXPWR_LMT_MAX_REGULATION_NUM ); + return _FAIL; + } + + for ( forCnt = 0; forCnt < colNum; ++forCnt ) + { + u8 regulation_name_cnt = 0; + + // skip the space + while ( szLine[i] == ' ' || szLine[i] == '\t' ) + ++i; + + while ( szLine[i] != ' ' && szLine[i] != '\t' && szLine[i] != '\0' ) + regulation[forCnt][regulation_name_cnt++] = szLine[i++]; + //DBG_871X("regulation %s!\n", regulation[forCnt]); + + if ( regulation_name_cnt == 0 ) { + DBG_871X("unvalid number of regulation!\n"); + return _FAIL; + } + } + + loadingStage = 3; + } + else if ( loadingStage == 3 ) + { + char channel[10] = {0}, powerLimit[10] = {0}; + u8 cnt = 0; + + // the table ends + if ( szLine[0] == '#' && szLine[1] == '#' ) { + i = 2; + while ( szLine[i] == ' ' || szLine[i] == '\t' ) + ++i; + + if ( eqNByte( (u8 *)(szLine + i), (u8 *)("END"), 3 ) ) { + loadingStage = 0; + continue; + } + else { + DBG_871X("Wrong format\n"); + DBG_871X("<===== phy_ParsePowerLimitTableFile()\n"); + return _FAIL; + } + } + + if ( ( szLine[0] != 'c' && szLine[0] != 'C' ) || + ( szLine[1] != 'h' && szLine[1] != 'H' ) ) { + DBG_871X("Meet wrong channel => power limt pair '%c','%c'(%d,%d)\n", szLine[0], szLine[1], szLine[0], szLine[1]); + continue; + } + i = 2;// move to the location behind 'h' + + // load the channel number + cnt = 0; + while ( szLine[i] >= '0' && szLine[i] <= '9' ) { + channel[cnt] = szLine[i]; + ++cnt; + ++i; + } + //DBG_871X("chnl %s!\n", channel); + + for ( forCnt = 0; forCnt < colNum; ++forCnt ) + { + // skip the space between channel number and the power limit value + while ( szLine[i] == ' ' || szLine[i] == '\t' ) + ++i; + + // load the power limit value + cnt = 0; + fraction = 0; + _rtw_memset( ( PVOID ) powerLimit, 0, 10 ); + while ( ( szLine[i] >= '0' && szLine[i] <= '9' ) || szLine[i] == '.' ) + { + if ( szLine[i] == '.' ){ + if ( ( szLine[i+1] >= '0' && szLine[i+1] <= '9' ) ) { + fraction = szLine[i+1]; + i += 2; + } + else { + DBG_871X("Wrong fraction in TXPWR_LMT.txt\n"); + return _FAIL; + } + + break; + } + + powerLimit[cnt] = szLine[i]; + ++cnt; + ++i; + } + + if ( powerLimit[0] == '\0' ) { + powerLimit[0] = '6'; + powerLimit[1] = '3'; + i += 2; + } + else { + if ( !GetU1ByteIntegerFromStringInDecimal( powerLimit, &limitValue ) ) + return _FAIL; + + limitValue *= 2; + cnt = 0; + if ( fraction == '5' ) + ++limitValue; + + // the value is greater or equal to 100 + if ( limitValue >= 100 ) { + powerLimit[cnt++] = limitValue/100 + '0'; + limitValue %= 100; + + if ( limitValue >= 10 ) { + powerLimit[cnt++] = limitValue/10 + '0'; + limitValue %= 10; + } + else { + powerLimit[cnt++] = '0'; + } + + powerLimit[cnt++] = limitValue + '0'; + } + // the value is greater or equal to 10 + else if ( limitValue >= 10 ) { + powerLimit[cnt++] = limitValue/10 + '0'; + limitValue %= 10; + powerLimit[cnt++] = limitValue + '0'; + } + // the value is less than 10 + else + powerLimit[cnt++] = limitValue + '0'; + + powerLimit[cnt] = '\0'; + } + + //DBG_871X("ch%s => %s\n", channel, powerLimit); + + // store the power limit value + PHY_SetTxPowerLimit(pDM_Odm, (u8 *)regulation[forCnt], (u8 *)band, + (u8 *)bandwidth, (u8 *)rateSection, (u8 *)rfPath, (u8 *)channel, (u8 *)powerLimit ); + + } + } + else + { + DBG_871X("Abnormal loading stage in phy_ParsePowerLimitTableFile()!\n"); + rtStatus = _FAIL; + break; + } + } + + DBG_871X("<===phy_ParsePowerLimitTableFile()\n"); + return rtStatus; +} + +int +PHY_ConfigRFWithPowerLimitTableParaFile( + IN PADAPTER Adapter, + IN const char *pFileName +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + int rlen = 0, rtStatus = _FAIL; + + if(!(Adapter->registrypriv.load_phy_file & LOAD_RF_TXPWR_LMT_PARA_FILE)) + return rtStatus; + + _rtw_memset(pHalData->para_file_buf, 0, MAX_PARA_FILE_BUF_LEN); + + if (pHalData->rf_tx_pwr_lmt == NULL) { + rtw_get_phy_file_path(Adapter, pFileName); + if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) + { + rlen = rtw_retrieve_from_file(rtw_phy_para_file_path, pHalData->para_file_buf, MAX_PARA_FILE_BUF_LEN); + if (rlen > 0) + { + rtStatus = _SUCCESS; + pHalData->rf_tx_pwr_lmt = rtw_zvmalloc(rlen); + if(pHalData->rf_tx_pwr_lmt) { + _rtw_memcpy(pHalData->rf_tx_pwr_lmt, pHalData->para_file_buf, rlen); + pHalData->rf_tx_pwr_lmt_len = rlen; + } + else { + DBG_871X("%s rf_tx_pwr_lmt alloc fail !\n",__FUNCTION__); + } + } + } + } else { + if ((pHalData->rf_tx_pwr_lmt_len != 0) && (pHalData->rf_tx_pwr_lmt != NULL)) { + _rtw_memcpy(pHalData->para_file_buf, pHalData->rf_tx_pwr_lmt, pHalData->rf_tx_pwr_lmt_len); + rtStatus = _SUCCESS; + } + else { + DBG_871X("%s(): Critical Error !!!\n",__FUNCTION__); + } + } + + if(rtStatus == _SUCCESS) + { + //DBG_871X("%s(): read %s ok\n", __FUNCTION__, pFileName); + rtStatus = phy_ParsePowerLimitTableFile( Adapter, pHalData->para_file_buf ); + } + else + { + DBG_871X("%s(): No File %s, Load from HWImg Array!\n", __FUNCTION__, pFileName); + } + + return rtStatus; +} + +void phy_free_filebuf_mask(_adapter *padapter, u8 mask) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + if (pHalData->mac_reg && (mask & LOAD_MAC_PARA_FILE)) { + rtw_vmfree(pHalData->mac_reg, pHalData->mac_reg_len); + pHalData->mac_reg = NULL; + } + if (mask & LOAD_BB_PARA_FILE) { + if (pHalData->bb_phy_reg) { + rtw_vmfree(pHalData->bb_phy_reg, pHalData->bb_phy_reg_len); + pHalData->bb_phy_reg = NULL; + } + if (pHalData->bb_agc_tab) { + rtw_vmfree(pHalData->bb_agc_tab, pHalData->bb_agc_tab_len); + pHalData->bb_agc_tab = NULL; + } + } + if (pHalData->bb_phy_reg_pg && (mask & LOAD_BB_PG_PARA_FILE)) { + rtw_vmfree(pHalData->bb_phy_reg_pg, pHalData->bb_phy_reg_pg_len); + pHalData->bb_phy_reg_pg = NULL; + } + if (pHalData->bb_phy_reg_mp && (mask & LOAD_BB_MP_PARA_FILE)) { + rtw_vmfree(pHalData->bb_phy_reg_mp, pHalData->bb_phy_reg_mp_len); + pHalData->bb_phy_reg_mp = NULL; + } + if (mask & LOAD_RF_PARA_FILE) { + if (pHalData->rf_radio_a) { + rtw_vmfree(pHalData->rf_radio_a, pHalData->rf_radio_a_len); + pHalData->rf_radio_a = NULL; + } + if (pHalData->rf_radio_b) { + rtw_vmfree(pHalData->rf_radio_b, pHalData->rf_radio_b_len); + pHalData->rf_radio_b = NULL; + } + } + if (pHalData->rf_tx_pwr_track && (mask & LOAD_RF_TXPWR_TRACK_PARA_FILE)) { + rtw_vmfree(pHalData->rf_tx_pwr_track, pHalData->rf_tx_pwr_track_len); + pHalData->rf_tx_pwr_track = NULL; + } + if (pHalData->rf_tx_pwr_lmt && (mask & LOAD_RF_TXPWR_LMT_PARA_FILE)) { + rtw_vmfree(pHalData->rf_tx_pwr_lmt, pHalData->rf_tx_pwr_lmt_len); + pHalData->rf_tx_pwr_lmt = NULL; + } +} + +inline void phy_free_filebuf(_adapter *padapter) +{ + phy_free_filebuf_mask(padapter, 0xFF); +} + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_dm.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_dm.c new file mode 100644 index 000000000..83736c674 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_dm.c @@ -0,0 +1,197 @@ +/****************************************************************************** + * + * Copyright(c) 2014 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include +#include + +// A mapping from HalData to ODM. +ODM_BOARD_TYPE_E boardType(u8 InterfaceSel) +{ + ODM_BOARD_TYPE_E board = ODM_BOARD_DEFAULT; + +#ifdef CONFIG_PCI_HCI + INTERFACE_SELECT_PCIE pcie = (INTERFACE_SELECT_PCIE)InterfaceSel; + switch (pcie) + { + case INTF_SEL0_SOLO_MINICARD: + board |= ODM_BOARD_MINICARD; + break; + case INTF_SEL1_BT_COMBO_MINICARD: + board |= ODM_BOARD_BT; + board |= ODM_BOARD_MINICARD; + break; + default: + board = ODM_BOARD_DEFAULT; + break; + } + +#elif defined(CONFIG_USB_HCI) + INTERFACE_SELECT_USB usb = (INTERFACE_SELECT_USB)InterfaceSel; + switch (usb) + { + case INTF_SEL1_USB_High_Power: + board |= ODM_BOARD_EXT_LNA; + board |= ODM_BOARD_EXT_PA; + break; + case INTF_SEL2_MINICARD: + board |= ODM_BOARD_MINICARD; + break; + case INTF_SEL4_USB_Combo: + board |= ODM_BOARD_BT; + break; + case INTF_SEL5_USB_Combo_MF: + board |= ODM_BOARD_BT; + break; + case INTF_SEL0_USB: + case INTF_SEL3_USB_Solo: + default: + board = ODM_BOARD_DEFAULT; + break; + } + +#endif + //DBG_871X("===> boardType(): (pHalData->InterfaceSel, pDM_Odm->BoardType) = (%d, %d)\n", InterfaceSel, board); + + return board; +} + +void Init_ODM_ComInfo(_adapter *adapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(adapter); + PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct mlme_priv *pmlmepriv = &adapter->mlmepriv; + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter); + int i; + + _rtw_memset(pDM_Odm,0,sizeof(*pDM_Odm)); + + pDM_Odm->Adapter = adapter; + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PLATFORM, ODM_CE); + + rtw_odm_init_ic_type(adapter); + + if (rtw_get_intf_type(adapter) == RTW_GSPI) + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_INTERFACE, ODM_ITRF_SDIO); + else + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_INTERFACE, rtw_get_intf_type(adapter)); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_MP_TEST_CHIP, IS_NORMAL_CHIP(pHalData->VersionID)); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PATCH_ID, pHalData->CustomerID); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BWIFI_TEST, adapter->registrypriv.wifi_spec); + + + if (pHalData->rf_type == RF_1T1R) + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_1T1R); + else if (pHalData->rf_type == RF_1T2R) + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_1T2R); + else if (pHalData->rf_type == RF_2T2R) + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T2R); + else if (pHalData->rf_type == RF_2T2R_GREEN) + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T2R_GREEN); + else if (pHalData->rf_type == RF_2T3R) + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T3R); + else if (pHalData->rf_type == RF_2T4R) + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_2T4R); + else if (pHalData->rf_type == RF_3T3R) + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_3T3R); + else if (pHalData->rf_type == RF_3T4R) + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_3T4R); + else if (pHalData->rf_type == RF_4T4R) + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_4T4R); + else + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_TYPE, ODM_XTXR); + + +{ + //1 ======= BoardType: ODM_CMNINFO_BOARD_TYPE ======= + u8 odm_board_type = ODM_BOARD_DEFAULT; + + if (pHalData->ExternalLNA_2G != 0) { + odm_board_type |= ODM_BOARD_EXT_LNA; + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_LNA, 1); + } + if (pHalData->ExternalLNA_5G != 0) { + odm_board_type |= ODM_BOARD_EXT_LNA_5G; + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_LNA, 1); + } + if (pHalData->ExternalPA_2G != 0) { + odm_board_type |= ODM_BOARD_EXT_PA; + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_PA, 1); + } + if (pHalData->ExternalPA_5G != 0) { + odm_board_type |= ODM_BOARD_EXT_PA_5G; + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_5G_EXT_PA, 1); + } + if (pHalData->EEPROMBluetoothCoexist) + odm_board_type |= ODM_BOARD_BT; + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_BOARD_TYPE, odm_board_type); + //1 ============== End of BoardType ============== +} + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_DOMAIN_CODE_2G, pHalData->Regulation2_4G); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_DOMAIN_CODE_5G, pHalData->Regulation5G); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GPA, pHalData->TypeGPA); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_APA, pHalData->TypeAPA); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_GLNA, pHalData->TypeGLNA); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_ALNA, pHalData->TypeALNA); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RFE_TYPE, pHalData->RFEType); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_EXT_TRSW, 0); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_RF_ANTENNA_TYPE, pHalData->TRxAntDivType); + + /* Pointer reference */ + ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_TX_UNI, &(dvobj->traffic_stat.tx_bytes)); + ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_RX_UNI, &(dvobj->traffic_stat.rx_bytes)); + ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_WM_MODE, &(pmlmeext->cur_wireless_mode)); + ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_BAND, &(pHalData->CurrentBandType)); + ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_FORCED_RATE, &(pHalData->ForcedDataRate)); + + ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_SEC_CHNL_OFFSET, &(pHalData->nCur40MhzPrimeSC)); + ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_SEC_MODE, &(adapter->securitypriv.dot11PrivacyAlgrthm)); + ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_BW, &(pHalData->CurrentChannelBW)); + ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_CHNL, &( pHalData->CurrentChannel)); + ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_NET_CLOSED, &(adapter->net_closed)); + ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_FORCED_IGI_LB, &(pHalData->u1ForcedIgiLb)); + + ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_SCAN, &(pmlmepriv->bScanInProcess)); + ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_POWER_SAVING, &(pwrctl->bpower_saving)); + /*Add by Yuchen for phydm beamforming*/ + ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_TX_TP, &(dvobj->traffic_stat.cur_tx_tp)); + ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_RX_TP, &(dvobj->traffic_stat.cur_rx_tp)); +#ifdef CONFIG_USB_HCI + ODM_CmnInfoHook(pDM_Odm, ODM_CMNINFO_HUBUSBMODE, &(dvobj->usb_speed)); +#endif + for(i=0; i +#include + +int usb_init_recv_priv(_adapter *padapter, u16 ini_in_buf_sz) +{ + struct recv_priv *precvpriv = &padapter->recvpriv; + int i, res = _SUCCESS; + struct recv_buf *precvbuf; + +#ifdef CONFIG_RECV_THREAD_MODE + _rtw_init_sema(&precvpriv->recv_sema, 0);//will be removed + _rtw_init_sema(&precvpriv->terminate_recvthread_sema, 0);//will be removed +#endif /* CONFIG_RECV_THREAD_MODE */ + +#ifdef PLATFORM_LINUX + tasklet_init(&precvpriv->recv_tasklet, + (void(*)(unsigned long))usb_recv_tasklet, + (unsigned long)padapter); +#endif /* PLATFORM_LINUX */ + +#ifdef PLATFORM_FREEBSD + #ifdef CONFIG_RX_INDICATE_QUEUE + TASK_INIT(&precvpriv->rx_indicate_tasklet, 0, rtw_rx_indicate_tasklet, padapter); + #endif /* CONFIG_RX_INDICATE_QUEUE */ +#endif /* PLATFORM_FREEBSD */ + +#ifdef CONFIG_USB_INTERRUPT_IN_PIPE +#ifdef PLATFORM_LINUX + precvpriv->int_in_urb = usb_alloc_urb(0, GFP_KERNEL); + if(precvpriv->int_in_urb == NULL){ + res = _FAIL; + DBG_8192C("alloc_urb for interrupt in endpoint fail !!!!\n"); + goto exit; + } +#endif /* PLATFORM_LINUX */ + precvpriv->int_in_buf = rtw_zmalloc(ini_in_buf_sz); + if(precvpriv->int_in_buf == NULL){ + res = _FAIL; + DBG_8192C("alloc_mem for interrupt in endpoint fail !!!!\n"); + goto exit; + } +#endif /* CONFIG_USB_INTERRUPT_IN_PIPE */ + + /* init recv_buf */ + _rtw_init_queue(&precvpriv->free_recv_buf_queue); + _rtw_init_queue(&precvpriv->recv_buf_pending_queue); + #ifndef CONFIG_USE_USB_BUFFER_ALLOC_RX + /* this is used only when RX_IOBUF is sk_buff */ + skb_queue_head_init(&precvpriv->free_recv_skb_queue); + #endif + + DBG_871X("NR_RECVBUFF: %d\n", NR_RECVBUFF); + DBG_871X("MAX_RECVBUF_SZ: %d\n", MAX_RECVBUF_SZ); + precvpriv->pallocated_recv_buf = rtw_zmalloc(NR_RECVBUFF *sizeof(struct recv_buf) + 4); + if(precvpriv->pallocated_recv_buf==NULL){ + res= _FAIL; + RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("alloc recv_buf fail!\n")); + goto exit; + } + + precvpriv->precv_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(precvpriv->pallocated_recv_buf), 4); + + precvbuf = (struct recv_buf*)precvpriv->precv_buf; + + for(i=0; i < NR_RECVBUFF ; i++) + { + _rtw_init_listhead(&precvbuf->list); + + _rtw_spinlock_init(&precvbuf->recvbuf_lock); + + precvbuf->alloc_sz = MAX_RECVBUF_SZ; + + res = rtw_os_recvbuf_resource_alloc(padapter, precvbuf); + if(res==_FAIL) + break; + + precvbuf->ref_cnt = 0; + precvbuf->adapter =padapter; + + //rtw_list_insert_tail(&precvbuf->list, &(precvpriv->free_recv_buf_queue.queue)); + + precvbuf++; + } + + precvpriv->free_recv_buf_queue_cnt = NR_RECVBUFF; + +#if defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD) + + skb_queue_head_init(&precvpriv->rx_skb_queue); + +#ifdef CONFIG_RX_INDICATE_QUEUE + memset(&precvpriv->rx_indicate_queue, 0, sizeof(struct ifqueue)); + mtx_init(&precvpriv->rx_indicate_queue.ifq_mtx, "rx_indicate_queue", NULL, MTX_DEF); +#endif /* CONFIG_RX_INDICATE_QUEUE */ + +#ifdef CONFIG_PREALLOC_RECV_SKB + { + int i; + SIZE_PTR tmpaddr=0; + SIZE_PTR alignment=0; + struct sk_buff *pskb=NULL; + + DBG_871X("NR_PREALLOC_RECV_SKB: %d\n", NR_PREALLOC_RECV_SKB); +#ifdef CONFIG_FIX_NR_BULKIN_BUFFER + DBG_871X("Enable CONFIG_FIX_NR_BULKIN_BUFFER\n"); +#endif + + for(i=0; idev = padapter->pifp; + #else + pskb->dev = padapter->pnetdev; + #endif //PLATFORM_FREEBSD + +#ifndef CONFIG_PREALLOC_RX_SKB_BUFFER + tmpaddr = (SIZE_PTR)pskb->data; + alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1); + skb_reserve(pskb, (RECVBUFF_ALIGN_SZ - alignment)); +#endif + skb_queue_tail(&precvpriv->free_recv_skb_queue, pskb); + } + } + } +#endif /* CONFIG_PREALLOC_RECV_SKB */ + +#endif /* defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD) */ + +exit: + + return res; +} + +void usb_free_recv_priv (_adapter *padapter, u16 ini_in_buf_sz) +{ + int i; + struct recv_buf *precvbuf; + struct recv_priv *precvpriv = &padapter->recvpriv; + + precvbuf = (struct recv_buf *)precvpriv->precv_buf; + + for(i=0; i < NR_RECVBUFF ; i++) + { + rtw_os_recvbuf_resource_free(padapter, precvbuf); + precvbuf++; + } + + if(precvpriv->pallocated_recv_buf) + rtw_mfree(precvpriv->pallocated_recv_buf, NR_RECVBUFF *sizeof(struct recv_buf) + 4); + +#ifdef CONFIG_USB_INTERRUPT_IN_PIPE +#ifdef PLATFORM_LINUX + if(precvpriv->int_in_urb) + { + usb_free_urb(precvpriv->int_in_urb); + } +#endif + if(precvpriv->int_in_buf) + rtw_mfree(precvpriv->int_in_buf, ini_in_buf_sz); +#endif /* CONFIG_USB_INTERRUPT_IN_PIPE */ + +#ifdef PLATFORM_LINUX + + if (skb_queue_len(&precvpriv->rx_skb_queue)) { + DBG_8192C(KERN_WARNING "rx_skb_queue not empty\n"); + } + + rtw_skb_queue_purge(&precvpriv->rx_skb_queue); + + if (skb_queue_len(&precvpriv->free_recv_skb_queue)) { + DBG_8192C(KERN_WARNING "free_recv_skb_queue not empty, %d\n", skb_queue_len(&precvpriv->free_recv_skb_queue)); + } + +#if !defined(CONFIG_USE_USB_BUFFER_ALLOC_RX) + #if defined(CONFIG_PREALLOC_RECV_SKB) && defined(CONFIG_PREALLOC_RX_SKB_BUFFER) + { + struct sk_buff *skb; + + while ((skb = skb_dequeue(&precvpriv->free_recv_skb_queue)) != NULL) + { + if (rtw_free_skb_premem(skb) != 0) + rtw_skb_free(skb); + } + } + #else + rtw_skb_queue_purge(&precvpriv->free_recv_skb_queue); + #endif /* defined(CONFIG_PREALLOC_RX_SKB_BUFFER) && defined(CONFIG_PREALLOC_RECV_SKB) */ +#endif /* !defined(CONFIG_USE_USB_BUFFER_ALLOC_RX) */ + +#endif /* PLATFORM_LINUX */ + +#ifdef PLATFORM_FREEBSD + struct sk_buff *pskb; + while (NULL != (pskb = skb_dequeue(&precvpriv->rx_skb_queue))) + { + rtw_skb_free(pskb); + } + + #if !defined(CONFIG_USE_USB_BUFFER_ALLOC_RX) + rtw_skb_queue_purge(&precvpriv->free_recv_skb_queue); + #endif + +#ifdef CONFIG_RX_INDICATE_QUEUE + struct mbuf *m; + for (;;) { + IF_DEQUEUE(&precvpriv->rx_indicate_queue, m); + if (m == NULL) + break; + m_freem(m); + } + mtx_destroy(&precvpriv->rx_indicate_queue.ifq_mtx); +#endif /* CONFIG_RX_INDICATE_QUEUE */ + +#endif /* PLATFORM_FREEBSD */ +} + +#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ +int usb_write_async(struct usb_device *udev, u32 addr, void *pdata, u16 len) +{ + u8 request; + u8 requesttype; + u16 wvalue; + u16 index; + int ret; + + requesttype = VENDOR_WRITE;//write_out + request = REALTEK_USB_VENQT_CMD_REQ; + index = REALTEK_USB_VENQT_CMD_IDX;//n/a + + wvalue = (u16)(addr&0x0000ffff); + + ret = _usbctrl_vendorreq_async_write(udev, request, wvalue, index, pdata, len, requesttype); + + return ret; +} + +int usb_async_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val) +{ + u8 data; + int ret; + struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfhdl->pintf_dev; + struct usb_device *udev=pdvobjpriv->pusbdev; + + _func_enter_; + data = val; + ret = usb_write_async(udev, addr, &data, 1); + _func_exit_; + + return ret; +} + +int usb_async_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val) +{ + u16 data; + int ret; + struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfhdl->pintf_dev; + struct usb_device *udev=pdvobjpriv->pusbdev; + + _func_enter_; + data = val; + ret = usb_write_async(udev, addr, &data, 2); + _func_exit_; + + return ret; +} + +int usb_async_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val) +{ + u32 data; + int ret; + struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfhdl->pintf_dev; + struct usb_device *udev=pdvobjpriv->pusbdev; + + _func_enter_; + data = val; + ret = usb_write_async(udev, addr, &data, 4); + _func_exit_; + + return ret; +} +#endif /* CONFIG_USB_SUPPORT_ASYNC_VDN_REQ */ + +u8 usb_read8(struct intf_hdl *pintfhdl, u32 addr) +{ + u8 request; + u8 requesttype; + u16 wvalue; + u16 index; + u16 len; + u8 data=0; + + _func_enter_; + + request = 0x05; + requesttype = 0x01;//read_in + index = 0;//n/a + + wvalue = (u16)(addr&0x0000ffff); + len = 1; + usbctrl_vendorreq(pintfhdl, request, wvalue, index, + &data, len, requesttype); + + _func_exit_; + + return data; +} + +u16 usb_read16(struct intf_hdl *pintfhdl, u32 addr) +{ + u8 request; + u8 requesttype; + u16 wvalue; + u16 index; + u16 len; + u16 data=0; + + _func_enter_; + + request = 0x05; + requesttype = 0x01;//read_in + index = 0;//n/a + + wvalue = (u16)(addr&0x0000ffff); + len = 2; + usbctrl_vendorreq(pintfhdl, request, wvalue, index, + &data, len, requesttype); + + _func_exit_; + + return data; + +} + +u32 usb_read32(struct intf_hdl *pintfhdl, u32 addr) +{ + u8 request; + u8 requesttype; + u16 wvalue; + u16 index; + u16 len; + u32 data=0; + + _func_enter_; + + request = 0x05; + requesttype = 0x01;//read_in + index = 0;//n/a + + wvalue = (u16)(addr&0x0000ffff); + len = 4; + usbctrl_vendorreq(pintfhdl, request, wvalue, index, + &data, len, requesttype); + + _func_exit_; + + return data; +} + +int usb_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val) +{ + u8 request; + u8 requesttype; + u16 wvalue; + u16 index; + u16 len; + u8 data; + int ret; + + _func_enter_; + + request = 0x05; + requesttype = 0x00;//write_out + index = 0;//n/a + + wvalue = (u16)(addr&0x0000ffff); + len = 1; + + data = val; + ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index, + &data, len, requesttype); + + _func_exit_; + + return ret; +} + +int usb_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val) +{ + u8 request; + u8 requesttype; + u16 wvalue; + u16 index; + u16 len; + u16 data; + int ret; + + _func_enter_; + + request = 0x05; + requesttype = 0x00;//write_out + index = 0;//n/a + + wvalue = (u16)(addr&0x0000ffff); + len = 2; + + data = val; + ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index, + &data, len, requesttype); + + _func_exit_; + + return ret; + +} + +int usb_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val) +{ + u8 request; + u8 requesttype; + u16 wvalue; + u16 index; + u16 len; + u32 data; + int ret; + + _func_enter_; + + request = 0x05; + requesttype = 0x00;//write_out + index = 0;//n/a + + wvalue = (u16)(addr&0x0000ffff); + len = 4; + data =val; + ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index, + &data, len, requesttype); + + _func_exit_; + + return ret; + +} + +int usb_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata) +{ + u8 request; + u8 requesttype; + u16 wvalue; + u16 index; + u16 len; + u8 buf[VENDOR_CMD_MAX_DATA_LEN]={0}; + int ret; + + _func_enter_; + + request = 0x05; + requesttype = 0x00;//write_out + index = 0;//n/a + + wvalue = (u16)(addr&0x0000ffff); + len = length; + _rtw_memcpy(buf, pdata, len ); + ret = usbctrl_vendorreq(pintfhdl, request, wvalue, index, + buf, len, requesttype); + + _func_exit_; + + return ret; + +} diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_intf.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_intf.c new file mode 100644 index 000000000..94f3d1199 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_intf.c @@ -0,0 +1,1086 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#define _HAL_INTF_C_ + +#include +#include + +const u32 _chip_type_to_odm_ic_type[] = { + 0, + ODM_RTL8188E, + ODM_RTL8192E, + ODM_RTL8812, + ODM_RTL8821, + ODM_RTL8723B, + ODM_RTL8814A, + ODM_RTL8703B, + ODM_RTL8188F, + 0, +}; + +void rtw_hal_chip_configure(_adapter *padapter) +{ + padapter->HalFunc.intf_chip_configure(padapter); +} + +void rtw_hal_read_chip_info(_adapter *padapter) +{ + u8 hci_type = rtw_get_intf_type(padapter); + u32 start = rtw_get_current_time(); + + /* before access eFuse, make sure card enable has been called */ + if ((hci_type == RTW_SDIO || hci_type == RTW_GSPI) + && !rtw_is_hw_init_completed(padapter)) + rtw_hal_power_on(padapter); + + padapter->HalFunc.read_adapter_info(padapter); + + if ((hci_type == RTW_SDIO || hci_type == RTW_GSPI) + && !rtw_is_hw_init_completed(padapter)) + rtw_hal_power_off(padapter); + + DBG_871X("%s in %d ms\n", __func__, rtw_get_passing_time_ms(start)); +} + +void rtw_hal_read_chip_version(_adapter *padapter) +{ + padapter->HalFunc.read_chip_version(padapter); + rtw_odm_init_ic_type(padapter); +} + +void rtw_hal_def_value_init(_adapter *padapter) +{ + if (is_primary_adapter(padapter)) { + padapter->HalFunc.init_default_value(padapter); + + rtw_init_hal_com_default_value(padapter); + + { + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct hal_spec_t *hal_spec = GET_HAL_SPEC(padapter); + + /* hal_spec is ready here */ + dvobj->macid_ctl.num = rtw_min(hal_spec->macid_num, MACID_NUM_SW_LIMIT); + + dvobj->cam_ctl.sec_cap = hal_spec->sec_cap; + dvobj->cam_ctl.num = rtw_min(hal_spec->sec_cam_ent_num, SEC_CAM_ENT_NUM_SW_LIMIT); + } + } +} + +u8 rtw_hal_data_init(_adapter *padapter) +{ + if (is_primary_adapter(padapter)) { + padapter->hal_data_sz = sizeof(HAL_DATA_TYPE); + padapter->HalData = rtw_zvmalloc(padapter->hal_data_sz); + if(padapter->HalData == NULL){ + DBG_8192C("cant not alloc memory for HAL DATA \n"); + return _FAIL; + } + } + return _SUCCESS; +} + +void rtw_hal_data_deinit(_adapter *padapter) +{ + if (is_primary_adapter(padapter)) { + if (padapter->HalData) + { + #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + phy_free_filebuf(padapter); + #endif + rtw_vmfree(padapter->HalData, padapter->hal_data_sz); + padapter->HalData = NULL; + padapter->hal_data_sz = 0; + } + } +} + +void rtw_hal_free_data(_adapter *padapter) +{ + //free HAL Data + rtw_hal_data_deinit(padapter); +} +void rtw_hal_dm_init(_adapter *padapter) +{ + if (is_primary_adapter(padapter)) { + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + + padapter->HalFunc.dm_init(padapter); + + _rtw_spinlock_init(&pHalData->IQKSpinLock); + + phy_load_tx_power_ext_info(padapter, 1); + } +} +void rtw_hal_dm_deinit(_adapter *padapter) +{ + if (is_primary_adapter(padapter)) { + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + + padapter->HalFunc.dm_deinit(padapter); + + _rtw_spinlock_free(&pHalData->IQKSpinLock); + } +} +void rtw_hal_sw_led_init(_adapter *padapter) +{ + if(padapter->HalFunc.InitSwLeds) + padapter->HalFunc.InitSwLeds(padapter); +} + +void rtw_hal_sw_led_deinit(_adapter *padapter) +{ + if(padapter->HalFunc.DeInitSwLeds) + padapter->HalFunc.DeInitSwLeds(padapter); +} + +u32 rtw_hal_power_on(_adapter *padapter) +{ + return padapter->HalFunc.hal_power_on(padapter); +} +void rtw_hal_power_off(_adapter *padapter) +{ + struct macid_ctl_t *macid_ctl = &padapter->dvobj->macid_ctl; + + _rtw_memset(macid_ctl->h2c_msr, 0, MACID_NUM_SW_LIMIT); + + padapter->HalFunc.hal_power_off(padapter); +} + + +void rtw_hal_init_opmode(_adapter *padapter) +{ + NDIS_802_11_NETWORK_INFRASTRUCTURE networkType = Ndis802_11InfrastructureMax; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + sint fw_state; + + fw_state = get_fwstate(pmlmepriv); + + if (fw_state & WIFI_ADHOC_STATE) + networkType = Ndis802_11IBSS; + else if (fw_state & WIFI_STATION_STATE) + networkType = Ndis802_11Infrastructure; + else if (fw_state & WIFI_AP_STATE) + networkType = Ndis802_11APMode; + else + return; + + rtw_setopmode_cmd(padapter, networkType, _FALSE); +} + +uint rtw_hal_init(_adapter *padapter) +{ + uint status = _SUCCESS; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + int i; + + status = padapter->HalFunc.hal_init(padapter); + + if (status == _SUCCESS) { + pHalData->hw_init_completed = _TRUE; + + if (padapter->registrypriv.notch_filter == 1) + rtw_hal_notch_filter(padapter, 1); + + for (i = 0; iiface_nums; i++) + rtw_sec_restore_wep_key(dvobj->padapters[i]); + + rtw_led_control(padapter, LED_CTL_POWER_ON); + + init_hw_mlme_ext(padapter); + + rtw_hal_init_opmode(padapter); + +#ifdef CONFIG_RF_POWER_TRIM + rtw_bb_rf_gain_offset(padapter); +#endif /*CONFIG_RF_POWER_TRIM*/ + + } else { + pHalData->hw_init_completed = _FALSE; + DBG_871X("rtw_hal_init: hal__init fail\n"); + } + + RT_TRACE(_module_hal_init_c_,_drv_err_,("-rtl871x_hal_init:status=0x%x\n",status)); + + return status; + +} + +uint rtw_hal_deinit(_adapter *padapter) +{ + uint status = _SUCCESS; + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + int i; +_func_enter_; + + status = padapter->HalFunc.hal_deinit(padapter); + + if(status == _SUCCESS){ + rtw_led_control(padapter, LED_CTL_POWER_OFF); + pHalData->hw_init_completed = _FALSE; + } + else + { + DBG_871X("\n rtw_hal_deinit: hal_init fail\n"); + } + +_func_exit_; + + return status; +} + +void rtw_hal_set_hwreg(_adapter *padapter, u8 variable, u8 *val) +{ + padapter->HalFunc.SetHwRegHandler(padapter, variable, val); +} + +void rtw_hal_get_hwreg(_adapter *padapter, u8 variable, u8 *val) +{ + padapter->HalFunc.GetHwRegHandler(padapter, variable, val); +} + +#ifdef CONFIG_C2H_PACKET_EN +void rtw_hal_set_hwreg_with_buf(_adapter *padapter, u8 variable, u8 *pbuf, int len) +{ + if (padapter->HalFunc.SetHwRegHandlerWithBuf) + padapter->HalFunc.SetHwRegHandlerWithBuf(padapter, variable, pbuf, len); +} +#endif + +u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue) +{ + return padapter->HalFunc.SetHalDefVarHandler(padapter,eVariable,pValue); +} +u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue) +{ + return padapter->HalFunc.GetHalDefVarHandler(padapter,eVariable,pValue); +} + +void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1,BOOLEAN bSet) +{ + padapter->HalFunc.SetHalODMVarHandler(padapter,eVariable,pValue1,bSet); +} +void rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1,PVOID pValue2) +{ + padapter->HalFunc.GetHalODMVarHandler(padapter,eVariable,pValue1,pValue2); +} + +/* FOR SDIO & PCIE */ +void rtw_hal_enable_interrupt(_adapter *padapter) +{ +#if defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) + padapter->HalFunc.enable_interrupt(padapter); +#endif //#if defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) +} + +/* FOR SDIO & PCIE */ +void rtw_hal_disable_interrupt(_adapter *padapter) +{ +#if defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) + padapter->HalFunc.disable_interrupt(padapter); +#endif //#if defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) +} + + +u8 rtw_hal_check_ips_status(_adapter *padapter) +{ + u8 val = _FALSE; + if (padapter->HalFunc.check_ips_status) + val = padapter->HalFunc.check_ips_status(padapter); + else + DBG_871X("%s: HalFunc.check_ips_status is NULL!\n", __FUNCTION__); + + return val; +} + +s32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan) +{ + return padapter->HalFunc.fw_dl(padapter, wowlan); +} + +#if defined(CONFIG_USB_HCI) || defined (CONFIG_PCI_HCI) +u32 rtw_hal_inirp_init(_adapter *padapter) +{ + if (is_primary_adapter(padapter)) + return padapter->HalFunc.inirp_init(padapter); + return _SUCCESS; +} +u32 rtw_hal_inirp_deinit(_adapter *padapter) +{ + + if (is_primary_adapter(padapter)) + return padapter->HalFunc.inirp_deinit(padapter); + + return _SUCCESS; +} +#endif //#if defined(CONFIG_USB_HCI) || defined (CONFIG_PCI_HCI) + +#if defined(CONFIG_PCI_HCI) +void rtw_hal_irp_reset(_adapter *padapter) +{ + padapter->HalFunc.irp_reset(padapter); +} +#endif //#if defined(CONFIG_PCI_HCI) + +/* for USB Auto-suspend */ +u8 rtw_hal_intf_ps_func(_adapter *padapter,HAL_INTF_PS_FUNC efunc_id, u8* val) +{ + if(padapter->HalFunc.interface_ps_func) + return padapter->HalFunc.interface_ps_func(padapter,efunc_id,val); + return _FAIL; +} + +s32 rtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + return padapter->HalFunc.hal_xmitframe_enqueue(padapter, pxmitframe); +} + +s32 rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + return padapter->HalFunc.hal_xmit(padapter, pxmitframe); +} + +/* + * [IMPORTANT] This function would be run in interrupt context. + */ +s32 rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe) +{ + s32 ret = _FAIL; + u8 *pframe, subtype; + struct rtw_ieee80211_hdr *pwlanhdr; + struct sta_info *psta; + struct sta_priv *pstapriv = &padapter->stapriv; + + update_mgntframe_attrib_addr(padapter, pmgntframe); + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + subtype = GetFrameSubType(pframe); /* bit(7)~bit(2) */ + + //pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + //_rtw_memcpy(pmgntframe->attrib.ra, pwlanhdr->addr1, ETH_ALEN); + +#ifdef CONFIG_IEEE80211W + if (padapter->securitypriv.binstallBIPkey == _TRUE && (subtype == WIFI_DEAUTH || subtype == WIFI_DISASSOC || + subtype == WIFI_ACTION)) + { + if (IS_MCAST(pmgntframe->attrib.ra) && pmgntframe->attrib.key_type != IEEE80211W_NO_KEY) { + pmgntframe->attrib.encrypt = _BIP_; + /* pmgntframe->attrib.bswenc = _TRUE; */ + } else if (pmgntframe->attrib.key_type != IEEE80211W_NO_KEY) { + psta = rtw_get_stainfo(pstapriv, pmgntframe->attrib.ra); + if (psta && psta->bpairwise_key_installed == _TRUE) { + pmgntframe->attrib.encrypt = _AES_; + pmgntframe->attrib.bswenc = _TRUE; + } else { + DBG_871X("%s, %d, bpairwise_key_installed is FALSE\n", __func__, __LINE__); + goto no_mgmt_coalesce; + } + } + DBG_871X("encrypt=%d, bswenc=%d\n", pmgntframe->attrib.encrypt, pmgntframe->attrib.bswenc); + rtw_mgmt_xmitframe_coalesce(padapter, pmgntframe->pkt, pmgntframe); + } +#endif //CONFIG_IEEE80211W +no_mgmt_coalesce: + ret = padapter->HalFunc.mgnt_xmit(padapter, pmgntframe); + return ret; +} + +s32 rtw_hal_init_xmit_priv(_adapter *padapter) +{ + return padapter->HalFunc.init_xmit_priv(padapter); +} +void rtw_hal_free_xmit_priv(_adapter *padapter) +{ + padapter->HalFunc.free_xmit_priv(padapter); +} + +s32 rtw_hal_init_recv_priv(_adapter *padapter) +{ + return padapter->HalFunc.init_recv_priv(padapter); +} +void rtw_hal_free_recv_priv(_adapter *padapter) +{ + padapter->HalFunc.free_recv_priv(padapter); +} + +void rtw_hal_update_ra_mask(struct sta_info *psta, u8 rssi_level) +{ + _adapter *padapter; + struct mlme_priv *pmlmepriv; + + if(!psta) + return; + + padapter = psta->padapter; + + pmlmepriv = &(padapter->mlmepriv); + + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + { + add_RATid(padapter, psta, rssi_level); + } + else + { + padapter->HalFunc.UpdateRAMaskHandler(padapter, psta->mac_id, rssi_level); + } +} + +void rtw_hal_add_ra_tid(_adapter *padapter, u64 bitmap, u8 *arg, u8 rssi_level) +{ + padapter->HalFunc.Add_RateATid(padapter, bitmap, arg, rssi_level); +} + +/* Start specifical interface thread */ +void rtw_hal_start_thread(_adapter *padapter) +{ +#if defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) +#ifndef CONFIG_SDIO_TX_TASKLET + padapter->HalFunc.run_thread(padapter); +#endif +#endif +} +/* Start specifical interface thread */ +void rtw_hal_stop_thread(_adapter *padapter) +{ +#if defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) +#ifndef CONFIG_SDIO_TX_TASKLET + + padapter->HalFunc.cancel_thread(padapter); + +#endif +#endif +} + +u32 rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask) +{ + u32 data = 0; + if(padapter->HalFunc.read_bbreg) + data = padapter->HalFunc.read_bbreg(padapter, RegAddr, BitMask); + return data; +} +void rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data) +{ + if(padapter->HalFunc.write_bbreg) + padapter->HalFunc.write_bbreg(padapter, RegAddr, BitMask, Data); +} + +u32 rtw_hal_read_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask) +{ + u32 data = 0; + + if (padapter->HalFunc.read_rfreg) { + data = padapter->HalFunc.read_rfreg(padapter, eRFPath, RegAddr, BitMask); + + if (match_rf_read_sniff_ranges(eRFPath, RegAddr, BitMask)) { + DBG_871X("DBG_IO rtw_hal_read_rfreg(%u, 0x%04x, 0x%08x) read:0x%08x(0x%08x)\n" + , eRFPath, RegAddr, BitMask, (data << PHY_CalculateBitShift(BitMask)), data); + } + } + + return data; +} + +void rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data) +{ + if (padapter->HalFunc.write_rfreg) { + + if (match_rf_write_sniff_ranges(eRFPath, RegAddr, BitMask)) { + DBG_871X("DBG_IO rtw_hal_write_rfreg(%u, 0x%04x, 0x%08x) write:0x%08x(0x%08x)\n" + , eRFPath, RegAddr, BitMask, (Data << PHY_CalculateBitShift(BitMask)), Data); + } + + padapter->HalFunc.write_rfreg(padapter, eRFPath, RegAddr, BitMask, Data); + +#ifdef CONFIG_PCI_HCI + if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(padapter)) /*For N-Series IC, suggest by Jenyu*/ + rtw_udelay_os(2); +#endif + } +} + +#if defined(CONFIG_PCI_HCI) +s32 rtw_hal_interrupt_handler(_adapter *padapter) +{ + s32 ret = _FAIL; + ret = padapter->HalFunc.interrupt_handler(padapter); + return ret; +} +#endif +#if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT) +void rtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf) +{ + padapter->HalFunc.interrupt_handler(padapter, pkt_len, pbuf); +} +#endif + +void rtw_hal_set_bwmode(_adapter *padapter, CHANNEL_WIDTH Bandwidth, u8 Offset) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + + ODM_AcquireSpinLock( pDM_Odm, RT_IQK_SPINLOCK); + if(pDM_Odm->RFCalibrateInfo.bIQKInProgress == _TRUE) + DBG_871X_LEVEL(_drv_err_, "%s, %d, IQK may race condition\n", __func__,__LINE__); + ODM_ReleaseSpinLock( pDM_Odm, RT_IQK_SPINLOCK); + padapter->HalFunc.set_bwmode_handler(padapter, Bandwidth, Offset); + +} + +void rtw_hal_set_chan(_adapter *padapter, u8 channel) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + + ODM_AcquireSpinLock( pDM_Odm, RT_IQK_SPINLOCK); + if(pDM_Odm->RFCalibrateInfo.bIQKInProgress == _TRUE) + DBG_871X_LEVEL(_drv_err_, "%s, %d, IQK may race condition\n", __func__,__LINE__); + ODM_ReleaseSpinLock( pDM_Odm, RT_IQK_SPINLOCK); + padapter->HalFunc.set_channel_handler(padapter, channel); +} + +void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + + ODM_AcquireSpinLock( pDM_Odm, RT_IQK_SPINLOCK); + if(pDM_Odm->RFCalibrateInfo.bIQKInProgress == _TRUE) + DBG_871X_LEVEL(_drv_err_, "%s, %d, IQK may race condition\n", __func__,__LINE__); + ODM_ReleaseSpinLock( pDM_Odm, RT_IQK_SPINLOCK); + padapter->HalFunc.set_chnl_bw_handler(padapter, channel, Bandwidth, Offset40, Offset80); +} + +void rtw_hal_set_tx_power_level(_adapter *padapter, u8 channel) +{ + if(padapter->HalFunc.set_tx_power_level_handler) + padapter->HalFunc.set_tx_power_level_handler(padapter, channel); +} + +void rtw_hal_get_tx_power_level(_adapter *padapter, s32 *powerlevel) +{ + if(padapter->HalFunc.get_tx_power_level_handler) + padapter->HalFunc.get_tx_power_level_handler(padapter, powerlevel); +} + +void rtw_hal_dm_watchdog(_adapter *padapter) +{ + if (!is_primary_adapter(padapter)) + return; + + padapter->HalFunc.hal_dm_watchdog(padapter); + +} + +#ifdef CONFIG_LPS_LCLK_WD_TIMER +void rtw_hal_dm_watchdog_in_lps(_adapter *padapter) +{ +#if defined(CONFIG_CONCURRENT_MODE) + if (padapter->iface_type != IFACE_PORT0) + return; +#endif + + if (adapter_to_pwrctl(padapter)->bFwCurrentInPSMode ==_TRUE ) { + padapter->HalFunc.hal_dm_watchdog_in_lps(padapter);//this fuction caller is in interrupt context + } +} +#endif + +void rtw_hal_bcn_related_reg_setting(_adapter *padapter) +{ + padapter->HalFunc.SetBeaconRelatedRegistersHandler(padapter); +} + +#ifdef CONFIG_HOSTAPD_MLME +s32 rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt) +{ + if(padapter->HalFunc.hostap_mgnt_xmit_entry) + return padapter->HalFunc.hostap_mgnt_xmit_entry(padapter, pkt); + return _FAIL; +} +#endif //CONFIG_HOSTAPD_MLME + +#ifdef DBG_CONFIG_ERROR_DETECT +void rtw_hal_sreset_init(_adapter *padapter) +{ + padapter->HalFunc.sreset_init_value(padapter); +} +void rtw_hal_sreset_reset(_adapter *padapter) +{ + padapter = GET_PRIMARY_ADAPTER(padapter); + padapter->HalFunc.silentreset(padapter); +} + +void rtw_hal_sreset_reset_value(_adapter *padapter) +{ + padapter->HalFunc.sreset_reset_value(padapter); +} + +void rtw_hal_sreset_xmit_status_check(_adapter *padapter) +{ + if (!is_primary_adapter(padapter)) + return; + + padapter->HalFunc.sreset_xmit_status_check(padapter); +} +void rtw_hal_sreset_linked_status_check(_adapter *padapter) +{ + if (!is_primary_adapter(padapter)) + return; + padapter->HalFunc.sreset_linked_status_check(padapter); +} +u8 rtw_hal_sreset_get_wifi_status(_adapter *padapter) +{ + return padapter->HalFunc.sreset_get_wifi_status(padapter); +} + +bool rtw_hal_sreset_inprogress(_adapter *padapter) +{ + padapter = GET_PRIMARY_ADAPTER(padapter); + return padapter->HalFunc.sreset_inprogress(padapter); +} +#endif //DBG_CONFIG_ERROR_DETECT + +#ifdef CONFIG_IOL +int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt) +{ + if(adapter->HalFunc.IOL_exec_cmds_sync) + return adapter->HalFunc.IOL_exec_cmds_sync(adapter, xmit_frame, max_wating_ms,bndy_cnt); + return _FAIL; +} +#endif + +#ifdef CONFIG_XMIT_THREAD_MODE +s32 rtw_hal_xmit_thread_handler(_adapter *padapter) +{ + return padapter->HalFunc.xmit_thread_handler(padapter); +} +#endif + +void rtw_hal_notch_filter(_adapter *adapter, bool enable) +{ + if(adapter->HalFunc.hal_notch_filter) + adapter->HalFunc.hal_notch_filter(adapter,enable); +} + +bool rtw_hal_c2h_valid(_adapter *adapter, u8 *buf) +{ + HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter); + HAL_VERSION *hal_ver = &HalData->VersionID; + bool ret = _FAIL; + + if (IS_8188E(*hal_ver)) { + ret = c2h_evt_valid((struct c2h_evt_hdr *)buf); + } else if(IS_8192E(*hal_ver) || IS_8812_SERIES(*hal_ver) || IS_8821_SERIES(*hal_ver) || IS_8723B_SERIES(*hal_ver)) { + ret = c2h_evt_valid((struct c2h_evt_hdr_88xx*)buf); + } else { + rtw_warn_on(1); + } + + return ret; +} + +s32 rtw_hal_c2h_evt_read(_adapter *adapter, u8 *buf) +{ + HAL_DATA_TYPE *HalData = GET_HAL_DATA(adapter); + HAL_VERSION *hal_ver = &HalData->VersionID; + s32 ret = _FAIL; + + if (IS_8188E(*hal_ver)) { + ret = c2h_evt_read(adapter, buf); + } else if(IS_8192E(*hal_ver) || IS_8812_SERIES(*hal_ver) || IS_8821_SERIES(*hal_ver) || IS_8723B_SERIES(*hal_ver)) { + ret = c2h_evt_read_88xx(adapter, buf); + } else { + rtw_warn_on(1); + } + + return ret; +} + +s32 rtw_hal_c2h_handler(_adapter *adapter, u8 *c2h_evt) +{ + s32 ret = _FAIL; + if (adapter->HalFunc.c2h_handler) + ret = adapter->HalFunc.c2h_handler(adapter, c2h_evt); + return ret; +} + +c2h_id_filter rtw_hal_c2h_id_filter_ccx(_adapter *adapter) +{ + return adapter->HalFunc.c2h_id_filter_ccx; +} + +s32 rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter) +{ + return GET_HAL_DATA(padapter)->bDisableSWChannelPlan; +} + +s32 rtw_hal_macid_sleep(PADAPTER padapter, u8 macid) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + u8 support; + + support = _FALSE; + rtw_hal_get_def_var(padapter, HAL_DEF_MACID_SLEEP, &support); + if (_FALSE == support) + return _FAIL; + + if (macid >= macid_ctl->num) { + DBG_871X_LEVEL(_drv_err_, FUNC_ADPT_FMT": Invalid macid(%u)\n", + FUNC_ADPT_ARG(padapter), macid); + return _FAIL; + } + + rtw_hal_set_hwreg(padapter, HW_VAR_MACID_SLEEP, &macid); + + return _SUCCESS; +} + +s32 rtw_hal_macid_wakeup(PADAPTER padapter, u8 macid) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + u8 support; + + support = _FALSE; + rtw_hal_get_def_var(padapter, HAL_DEF_MACID_SLEEP, &support); + if (_FALSE == support) + return _FAIL; + + if (macid >= macid_ctl->num) { + DBG_871X_LEVEL(_drv_err_, FUNC_ADPT_FMT": Invalid macid(%u)\n", + FUNC_ADPT_ARG(padapter), macid); + return _FAIL; + } + + rtw_hal_set_hwreg(padapter, HW_VAR_MACID_WAKEUP, &macid); + + return _SUCCESS; +} + +s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer) +{ + _adapter *pri_adapter = GET_PRIMARY_ADAPTER(padapter); + + if (pri_adapter->bFWReady == _TRUE) + return padapter->HalFunc.fill_h2c_cmd(padapter, ElementID, CmdLen, pCmdBuffer); + else if (padapter->registrypriv.mp_mode == 0) + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" FW doesn't exit when no MP mode, by pass H2C id:0x%02x\n" + , FUNC_ADPT_ARG(padapter), ElementID); + return _FAIL; +} + +void rtw_hal_fill_fake_txdesc(_adapter* padapter, u8* pDesc, u32 BufferLen, + u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame) +{ + padapter->HalFunc.fill_fake_txdesc(padapter, pDesc, BufferLen,IsPsPoll, IsBTQosNull, bDataFrame); + +} +u8 rtw_hal_get_txbuff_rsvd_page_num(_adapter *adapter, bool wowlan) +{ + return adapter->HalFunc.hal_get_tx_buff_rsvd_page_num(adapter, wowlan); +} + +#ifdef CONFIG_GPIO_API +void rtw_hal_update_hisr_hsisr_ind(_adapter *padapter, u32 flag) +{ + if (padapter->HalFunc.update_hisr_hsisr_ind) + padapter->HalFunc.update_hisr_hsisr_ind(padapter, flag); +} +#endif + +void rtw_hal_fw_correct_bcn(_adapter *padapter) +{ + if (padapter->HalFunc.fw_correct_bcn) + padapter->HalFunc.fw_correct_bcn(padapter); +} + +#define rtw_hal_error_msg(ops_fun) \ + DBG_871X_LEVEL(_drv_always_, "### %s - Error : Please hook HalFunc.%s ###\n",__FUNCTION__,ops_fun) + +u8 rtw_hal_ops_check(_adapter *padapter) +{ + u8 ret = _SUCCESS; +#if 1 + /*** initialize section ***/ + if (NULL == padapter->HalFunc.read_chip_version) { + rtw_hal_error_msg("read_chip_version"); + ret = _FAIL; + } + if (NULL == padapter->HalFunc.init_default_value) { + rtw_hal_error_msg("init_default_value"); + ret = _FAIL; + } + if (NULL == padapter->HalFunc.intf_chip_configure) { + rtw_hal_error_msg("intf_chip_configure"); + ret = _FAIL; + } + if (NULL == padapter->HalFunc.read_adapter_info) { + rtw_hal_error_msg("read_adapter_info"); + ret = _FAIL; + } + + if (NULL == padapter->HalFunc.hal_power_on) { + rtw_hal_error_msg("hal_power_on"); + ret = _FAIL; + } + if (NULL == padapter->HalFunc.hal_power_off) { + rtw_hal_error_msg("hal_power_off"); + ret = _FAIL; + } + + if (NULL == padapter->HalFunc.hal_init) { + rtw_hal_error_msg("hal_init"); + ret = _FAIL; + } + if (NULL == padapter->HalFunc.hal_deinit) { + rtw_hal_error_msg("hal_deinit"); + ret = _FAIL; + } + + /*** xmit section ***/ + if (NULL == padapter->HalFunc.init_xmit_priv) { + rtw_hal_error_msg("init_xmit_priv"); + ret = _FAIL; + } + if (NULL == padapter->HalFunc.free_xmit_priv) { + rtw_hal_error_msg("free_xmit_priv"); + ret = _FAIL; + } + if (NULL == padapter->HalFunc.hal_xmit) { + rtw_hal_error_msg("hal_xmit"); + ret = _FAIL; + } + if (NULL == padapter->HalFunc.mgnt_xmit) { + rtw_hal_error_msg("mgnt_xmit"); + ret = _FAIL; + } + #ifdef CONFIG_XMIT_THREAD_MODE + if (NULL == padapter->HalFunc.xmit_thread_handler) { + rtw_hal_error_msg("xmit_thread_handler"); + ret = _FAIL; + } + #endif + if (NULL == padapter->HalFunc.hal_xmitframe_enqueue) { + rtw_hal_error_msg("hal_xmitframe_enqueue"); + ret = _FAIL; + } + #if defined(CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) + #ifndef CONFIG_SDIO_TX_TASKLET + if (NULL == padapter->HalFunc.run_thread) { + rtw_hal_error_msg("run_thread"); + ret = _FAIL; + } + if (NULL == padapter->HalFunc.cancel_thread) { + rtw_hal_error_msg("cancel_thread"); + ret = _FAIL; + } + #endif + #endif + + /*** recv section ***/ + if (NULL == padapter->HalFunc.init_recv_priv) { + rtw_hal_error_msg("init_recv_priv"); + ret = _FAIL; + } + if (NULL == padapter->HalFunc.free_recv_priv) { + rtw_hal_error_msg("free_recv_priv"); + ret = _FAIL; + } + #if defined(CONFIG_USB_HCI) || defined (CONFIG_PCI_HCI) + if (NULL == padapter->HalFunc.inirp_init) { + rtw_hal_error_msg("inirp_init"); + ret = _FAIL; + } + if (NULL == padapter->HalFunc.inirp_deinit) { + rtw_hal_error_msg("inirp_deinit"); + ret = _FAIL; + } + #endif //#if defined(CONFIG_USB_HCI) || defined (CONFIG_PCI_HCI) + + + /*** interrupt hdl section ***/ + #if defined(CONFIG_PCI_HCI) + if (NULL == padapter->HalFunc.irp_reset) { + rtw_hal_error_msg("irp_reset"); + ret = _FAIL; + } + #endif/*#if defined(CONFIG_PCI_HCI)*/ + #if (defined(CONFIG_PCI_HCI)) || (defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)) + if (NULL == padapter->HalFunc.interrupt_handler) { + rtw_hal_error_msg("interrupt_handler"); + ret = _FAIL; + } + #endif /*#if (defined(CONFIG_PCI_HCI)) || (defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT))*/ + + #if defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) + if (NULL == padapter->HalFunc.enable_interrupt) { + rtw_hal_error_msg("enable_interrupt"); + ret = _FAIL; + } + if (NULL == padapter->HalFunc.disable_interrupt) { + rtw_hal_error_msg("disable_interrupt"); + ret = _FAIL; + } + #endif //defined(CONFIG_PCI_HCI) || defined (CONFIG_SDIO_HCI) || defined (CONFIG_GSPI_HCI) + + + /*** DM section ***/ + if (NULL == padapter->HalFunc.dm_init) { + rtw_hal_error_msg("dm_init"); + ret = _FAIL; + } + if (NULL == padapter->HalFunc.dm_deinit) { + rtw_hal_error_msg("dm_deinit"); + ret = _FAIL; + } + if (NULL == padapter->HalFunc.hal_dm_watchdog) { + rtw_hal_error_msg("hal_dm_watchdog"); + ret = _FAIL; + } + #ifdef CONFIG_LPS_LCLK_WD_TIMER + if (NULL == padapter->HalFunc.hal_dm_watchdog_in_lps) { + rtw_hal_error_msg("hal_dm_watchdog_in_lps"); + ret = _FAIL; + } + #endif + + /*** xxx section ***/ + if (NULL == padapter->HalFunc.set_bwmode_handler) { + rtw_hal_error_msg("set_bwmode_handler"); + ret = _FAIL; + } + + if (NULL == padapter->HalFunc.set_channel_handler) { + rtw_hal_error_msg("set_channel_handler"); + ret = _FAIL; + } + + if (NULL == padapter->HalFunc.set_chnl_bw_handler) { + rtw_hal_error_msg("set_chnl_bw_handler"); + ret = _FAIL; + } + + if (NULL == padapter->HalFunc.SetHwRegHandler) { + rtw_hal_error_msg("SetHwRegHandler"); + ret = _FAIL; + } + if (NULL == padapter->HalFunc.GetHwRegHandler) { + rtw_hal_error_msg("GetHwRegHandler"); + ret = _FAIL; + } + if (NULL == padapter->HalFunc.GetHalDefVarHandler) { + rtw_hal_error_msg("GetHalDefVarHandler"); + ret = _FAIL; + } + if (NULL == padapter->HalFunc.SetHalDefVarHandler) { + rtw_hal_error_msg("SetHalDefVarHandler"); + ret = _FAIL; + } + if (NULL == padapter->HalFunc.GetHalODMVarHandler) { + rtw_hal_error_msg("GetHalODMVarHandler"); + ret = _FAIL; + } + if (NULL == padapter->HalFunc.SetHalODMVarHandler) { + rtw_hal_error_msg("SetHalODMVarHandler"); + ret = _FAIL; + } + if (NULL == padapter->HalFunc.UpdateRAMaskHandler) { + rtw_hal_error_msg("UpdateRAMaskHandler"); + ret = _FAIL; + } + + if (NULL == padapter->HalFunc.SetBeaconRelatedRegistersHandler) { + rtw_hal_error_msg("SetBeaconRelatedRegistersHandler"); + ret = _FAIL; + } + + if (NULL == padapter->HalFunc.Add_RateATid) { + rtw_hal_error_msg("Add_RateATid"); + ret = _FAIL; + } + + if (NULL == padapter->HalFunc.fill_h2c_cmd) { + rtw_hal_error_msg("fill_h2c_cmd"); + ret = _FAIL; + } + #if defined(CONFIG_LPS) + if (NULL == padapter->HalFunc.fill_fake_txdesc) { + rtw_hal_error_msg("fill_fake_txdesc"); + ret = _FAIL; + } + #endif + if (NULL == padapter->HalFunc.hal_get_tx_buff_rsvd_page_num) { + rtw_hal_error_msg("hal_get_tx_buff_rsvd_page_num"); + ret = _FAIL; + } + + if (NULL == padapter->HalFunc.fw_dl) { + rtw_hal_error_msg("fw_dl"); + ret = _FAIL; + } + + if ((IS_HARDWARE_TYPE_8814A(padapter) + || IS_HARDWARE_TYPE_8822BU(padapter) || IS_HARDWARE_TYPE_8822BS(padapter)) + && NULL == padapter->HalFunc.fw_correct_bcn) { + rtw_hal_error_msg("fw_correct_bcn"); + ret = _FAIL; + } + + + /*** SReset section ***/ + #ifdef DBG_CONFIG_ERROR_DETECT + if (NULL == padapter->HalFunc.sreset_init_value) { + rtw_hal_error_msg("sreset_init_value"); + ret = _FAIL; + } + if (NULL == padapter->HalFunc.sreset_reset_value) { + rtw_hal_error_msg("sreset_reset_value"); + ret = _FAIL; + } + if (NULL == padapter->HalFunc.silentreset) { + rtw_hal_error_msg("silentreset"); + ret = _FAIL; + } + if (NULL == padapter->HalFunc.sreset_xmit_status_check) { + rtw_hal_error_msg("sreset_xmit_status_check"); + ret = _FAIL; + } + if (NULL == padapter->HalFunc.sreset_linked_status_check) { + rtw_hal_error_msg("sreset_linked_status_check"); + ret = _FAIL; + } + if (NULL == padapter->HalFunc.sreset_get_wifi_status) { + rtw_hal_error_msg("sreset_get_wifi_status"); + ret = _FAIL; + } + if (NULL == padapter->HalFunc.sreset_inprogress) { + rtw_hal_error_msg("sreset_inprogress"); + ret = _FAIL; + } + #endif //#ifdef DBG_CONFIG_ERROR_DETECT + +#endif + return ret; +} + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_mp.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_mp.c new file mode 100644 index 000000000..2fc6ef965 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_mp.c @@ -0,0 +1,2164 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _HAL_MP_C_ +#ifdef CONFIG_MP_INCLUDED + +#ifdef CONFIG_RTL8188E +#include +#endif +#ifdef CONFIG_RTL8723B +#include +#endif +#ifdef CONFIG_RTL8192E +#include +#endif +#ifdef CONFIG_RTL8814A +#include +#endif +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) +#include +#endif +#ifdef CONFIG_RTL8703B +#include +#endif +#ifdef CONFIG_RTL8188F +#include +#endif + + +u8 MgntQuery_NssTxRate(u16 Rate) +{ + u8 NssNum = RF_TX_NUM_NONIMPLEMENT; + + if ((Rate >= MGN_MCS8 && Rate <= MGN_MCS15) || + (Rate >= MGN_VHT2SS_MCS0 && Rate <= MGN_VHT2SS_MCS9)) + NssNum = RF_2TX; + else if ((Rate >= MGN_MCS16 && Rate <= MGN_MCS23) || + (Rate >= MGN_VHT3SS_MCS0 && Rate <= MGN_VHT3SS_MCS9)) + NssNum = RF_3TX; + else if ((Rate >= MGN_MCS24 && Rate <= MGN_MCS31) || + (Rate >= MGN_VHT4SS_MCS0 && Rate <= MGN_VHT4SS_MCS9)) + NssNum = RF_4TX; + else + NssNum = RF_1TX; + + return NssNum; +} + +void hal_mpt_SwitchRfSetting(PADAPTER pAdapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + u8 ChannelToSw = pMptCtx->MptChannelToSw; + ULONG ulRateIdx = pMptCtx->MptRateIndex; + ULONG ulbandwidth = pMptCtx->MptBandWidth; + + /* <20120525, Kordan> Dynamic mechanism for APK, asked by Dennis.*/ + if (IS_HARDWARE_TYPE_8188ES(pAdapter) && (1 <= ChannelToSw && ChannelToSw <= 11) && + (ulRateIdx == MPT_RATE_MCS0 || ulRateIdx == MPT_RATE_1M || ulRateIdx == MPT_RATE_6M)) { + pMptCtx->backup0x52_RF_A = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0); + pMptCtx->backup0x52_RF_B = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0); + + if ((PlatformEFIORead4Byte(pAdapter, 0xF4)&BIT29) == BIT29) { + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB); + PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB); + } else { + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xD); + PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xD); + } + } else if (IS_HARDWARE_TYPE_8188EE(pAdapter)) { /* <20140903, VincentL> Asked by RF Eason and Edlu*/ + + if (ChannelToSw == 3 && ulbandwidth == MPT_BW_40MHZ) { + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0xB); /*RF 0x52 = 0x0007E4BD*/ + } else { + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, 0x9); /*RF 0x52 = 0x0007E49D*/ + } + + } else if (IS_HARDWARE_TYPE_8188E(pAdapter)) { + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_A); + PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_0x52, 0x000F0, pMptCtx->backup0x52_RF_B); + } +} + +s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + + + if (!netif_running(padapter->pnetdev)) { + RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: interface not opened!\n")); + return _FAIL; + } + + if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) { + RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: not in MP mode!\n")); + return _FAIL; + } + if (enable) + pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE; + else + pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _FALSE; + + return _SUCCESS; +} + +void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + + + *enable = pDM_Odm->RFCalibrateInfo.TxPowerTrackControl; +} + + +void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14) +{ + u32 TempVal = 0, TempVal2 = 0, TempVal3 = 0; + u32 CurrCCKSwingVal = 0, CCKSwingIndex = 12; + u8 i; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + u1Byte u1Channel = pHalData->CurrentChannel; + ULONG ulRateIdx = pMptCtx->MptRateIndex; + u1Byte DataRate = 0xFF; + + /* Suggested by BB David. 2015.04.27*/ + if(IS_HARDWARE_TYPE_8188F(Adapter)) + return; + + DataRate = MptToMgntRate(ulRateIdx); + + if (u1Channel == 14 && IS_CCK_RATE(DataRate)) + pHalData->bCCKinCH14 = TRUE; + else + pHalData->bCCKinCH14 = FALSE; + + if (IS_HARDWARE_TYPE_8703B(Adapter)) { + if ((u1Channel == 14) && IS_CCK_RATE(DataRate)) { + /* Channel 14 in CCK, need to set 0xA26~0xA29 to 0 for 8703B */ + PHY_SetBBReg(Adapter, rCCK0_TxFilter2, bMaskHWord, 0); + PHY_SetBBReg(Adapter, rCCK0_DebugPort, bMaskLWord, 0); + + RT_TRACE(_module_mp_, DBG_LOUD, ("MPT_CCKTxPowerAdjust 8703B CCK in Channel %u\n", u1Channel)); + } else { + /* Normal setting for 8703B, just recover to the default setting. */ + /* This hardcore values reference from the parameter which BB team gave. */ + for (i = 0 ; i < 2 ; ++i) + PHY_SetBBReg(Adapter, pHalData->RegForRecover[i].offset, bMaskDWord, pHalData->RegForRecover[i].value); + + RT_TRACE(_module_mp_, DBG_LOUD, ("MPT_CCKTxPowerAdjust 8703B in Channel %u restore to default setting\n", u1Channel)); + } + } else { + + /* get current cck swing value and check 0xa22 & 0xa23 later to match the table.*/ + CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord); + + if (!pHalData->bCCKinCH14) { + /* Readback the current bb cck swing value and compare with the table to */ + /* get the current swing index */ + for (i = 0; i < CCK_TABLE_SIZE; i++) { + if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) && + (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch1_Ch13[i][1])) { + CCKSwingIndex = i; + RT_TRACE(_module_mp_, DBG_LOUD, ("Ch1~13, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n", + (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex)); + break; + } + } + + /*Write 0xa22 0xa23*/ + TempVal = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][0] + + (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1]<<8); + + + /*Write 0xa24 ~ 0xa27*/ + TempVal2 = 0; + TempVal2 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][2] + + (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][3]<<8) + + (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4]<<16) + + (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][5]<<24); + + /*Write 0xa28 0xa29*/ + TempVal3 = 0; + TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] + + (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7]<<8); + } else { + for (i = 0; i < CCK_TABLE_SIZE; i++) { + if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch14[i][0]) && + (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch14[i][1])) { + CCKSwingIndex = i; + RT_TRACE(_module_mp_, DBG_LOUD, ("Ch14, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n", + (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex)); + break; + } + } + + /*Write 0xa22 0xa23*/ + TempVal = CCKSwingTable_Ch14[CCKSwingIndex][0] + + (CCKSwingTable_Ch14[CCKSwingIndex][1]<<8); + + /*Write 0xa24 ~ 0xa27*/ + TempVal2 = 0; + TempVal2 = CCKSwingTable_Ch14[CCKSwingIndex][2] + + (CCKSwingTable_Ch14[CCKSwingIndex][3]<<8) + + (CCKSwingTable_Ch14[CCKSwingIndex][4]<<16) + + (CCKSwingTable_Ch14[CCKSwingIndex][5]<<24); + + /*Write 0xa28 0xa29*/ + TempVal3 = 0; + TempVal3 = CCKSwingTable_Ch14[CCKSwingIndex][6] + + (CCKSwingTable_Ch14[CCKSwingIndex][7]<<8); + } + + write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal); + write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2); + write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3); + + } + +} + +void hal_mpt_SetChannel(PADAPTER pAdapter) +{ + u8 eRFPath; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + struct mp_priv *pmp = &pAdapter->mppriv; + u8 channel = pmp->channel; + u8 bandwidth = pmp->bandwidth; + + hal_mpt_SwitchRfSetting(pAdapter); + + SelectChannel(pAdapter, channel); + + pHalData->bSwChnl = _TRUE; + pHalData->bSetChnlBW = _TRUE; + rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0); + + hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14); + +} + +/* + * Notice + * Switch bandwitdth may change center frequency(channel) + */ +void hal_mpt_SetBandwidth(PADAPTER pAdapter) +{ + struct mp_priv *pmp = &pAdapter->mppriv; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + u8 channel = pmp->channel; + u8 bandwidth = pmp->bandwidth; + + SetBWMode(pAdapter, pmp->bandwidth, pmp->prime_channel_offset); + pHalData->bSwChnl = _TRUE; + pHalData->bSetChnlBW = _TRUE; + rtw_hal_set_chnl_bw(pAdapter, channel, bandwidth, 0, 0); + + hal_mpt_SwitchRfSetting(pAdapter); +} + +void mpt_SetTxPower_Old(PADAPTER pAdapter, MPT_TXPWR_DEF Rate, u8 *pTxPower) +{ + RT_TRACE(_module_mp_, DBG_LOUD, ("===>mpt_SetTxPower_Old(): Case = %d\n", Rate)); + switch (Rate) { + case MPT_CCK: + { + u4Byte TxAGC = 0, pwr = 0; + u1Byte rf; + + pwr = pTxPower[ODM_RF_PATH_A]; + if (pwr < 0x3f) { + TxAGC = (pwr<<16)|(pwr<<8)|(pwr); + PHY_SetBBReg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pTxPower[ODM_RF_PATH_A]); + PHY_SetBBReg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC); + } + pwr = pTxPower[ODM_RF_PATH_B]; + if (pwr < 0x3f) { + TxAGC = (pwr<<16)|(pwr<<8)|(pwr); + PHY_SetBBReg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, pTxPower[ODM_RF_PATH_B]); + PHY_SetBBReg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, TxAGC); + } + + } break; + + case MPT_OFDM_AND_HT: + { + u4Byte TxAGC = 0; + u1Byte pwr = 0, rf; + + pwr = pTxPower[0]; + if (pwr < 0x3f) { + TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); + DBG_871X("HT Tx-rf(A) Power = 0x%x\n", TxAGC); + + PHY_SetBBReg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); + PHY_SetBBReg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); + PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); + PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); + PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); + PHY_SetBBReg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); + } + TxAGC = 0; + pwr = pTxPower[1]; + if (pwr < 0x3f) { + TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); + DBG_871X("HT Tx-rf(B) Power = 0x%x\n", TxAGC); + + PHY_SetBBReg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC); + PHY_SetBBReg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC); + PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC); + PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC); + PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC); + PHY_SetBBReg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC); + } + } break; + + default: + break; + } + DBG_871X("<===mpt_SetTxPower_Old()\n"); +} + + + +void +mpt_SetTxPower( + PADAPTER pAdapter, + MPT_TXPWR_DEF Rate, + pu1Byte pTxPower + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + u1Byte path = 0 , i = 0, MaxRate = MGN_6M; + u1Byte StartPath = ODM_RF_PATH_A, EndPath = ODM_RF_PATH_B; + + if (IS_HARDWARE_TYPE_8814A(pAdapter)) + EndPath = ODM_RF_PATH_D; + else if (IS_HARDWARE_TYPE_8188F(pAdapter)) + EndPath = ODM_RF_PATH_A; + + switch (Rate) { + case MPT_CCK: + { + u1Byte rate[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M}; + + for (path = StartPath; path <= EndPath; path++) + for (i = 0; i < sizeof(rate); ++i) + PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]); + } + break; + + case MPT_OFDM: + { + u1Byte rate[] = { + MGN_6M, MGN_9M, MGN_12M, MGN_18M, + MGN_24M, MGN_36M, MGN_48M, MGN_54M, + }; + + for (path = StartPath; path <= EndPath; path++) + for (i = 0; i < sizeof(rate); ++i) + PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]); + } break; + + case MPT_HT: + { + u1Byte rate[] = { + MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, + MGN_MCS5, MGN_MCS6, MGN_MCS7, MGN_MCS8, MGN_MCS9, + MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14, + MGN_MCS15, MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19, + MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23, MGN_MCS24, + MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29, + MGN_MCS30, MGN_MCS31, + }; + if (pHalData->rf_type == RF_3T3R) + MaxRate = MGN_MCS23; + else if (pHalData->rf_type == RF_2T2R) + MaxRate = MGN_MCS15; + else + MaxRate = MGN_MCS7; + + for (path = StartPath; path <= EndPath; path++) { + for (i = 0; i < sizeof(rate); ++i) { + if (rate[i] > MaxRate) + break; + PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]); + } + } + } break; + + case MPT_VHT: + { + u1Byte rate[] = { + MGN_VHT1SS_MCS0, MGN_VHT1SS_MCS1, MGN_VHT1SS_MCS2, MGN_VHT1SS_MCS3, MGN_VHT1SS_MCS4, + MGN_VHT1SS_MCS5, MGN_VHT1SS_MCS6, MGN_VHT1SS_MCS7, MGN_VHT1SS_MCS8, MGN_VHT1SS_MCS9, + MGN_VHT2SS_MCS0, MGN_VHT2SS_MCS1, MGN_VHT2SS_MCS2, MGN_VHT2SS_MCS3, MGN_VHT2SS_MCS4, + MGN_VHT2SS_MCS5, MGN_VHT2SS_MCS6, MGN_VHT2SS_MCS7, MGN_VHT2SS_MCS8, MGN_VHT2SS_MCS9, + MGN_VHT3SS_MCS0, MGN_VHT3SS_MCS1, MGN_VHT3SS_MCS2, MGN_VHT3SS_MCS3, MGN_VHT3SS_MCS4, + MGN_VHT3SS_MCS5, MGN_VHT3SS_MCS6, MGN_VHT3SS_MCS7, MGN_VHT3SS_MCS8, MGN_VHT3SS_MCS9, + MGN_VHT4SS_MCS0, MGN_VHT4SS_MCS1, MGN_VHT4SS_MCS2, MGN_VHT4SS_MCS3, MGN_VHT4SS_MCS4, + MGN_VHT4SS_MCS5, MGN_VHT4SS_MCS6, MGN_VHT4SS_MCS7, MGN_VHT4SS_MCS8, MGN_VHT4SS_MCS9, + }; + + if (pHalData->rf_type == RF_3T3R) + MaxRate = MGN_VHT3SS_MCS9; + else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R) + MaxRate = MGN_VHT2SS_MCS9; + else + MaxRate = MGN_VHT1SS_MCS9; + + for (path = StartPath; path <= EndPath; path++) { + for (i = 0; i < sizeof(rate); ++i) { + if (rate[i] > MaxRate) + break; + PHY_SetTxPowerIndex(pAdapter, pTxPower[path], path, rate[i]); + } + } + } break; + + default: + DBG_871X("<===mpt_SetTxPower: Illegal channel!!\n"); + break; + } + +} + + +void hal_mpt_SetTxPower(PADAPTER pAdapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + + if (pHalData->rf_chip < RF_TYPE_MAX) { + if (IS_HARDWARE_TYPE_8188E(pAdapter) || + IS_HARDWARE_TYPE_8723B(pAdapter) || + IS_HARDWARE_TYPE_8192E(pAdapter) || + IS_HARDWARE_TYPE_8703B(pAdapter) || + IS_HARDWARE_TYPE_8188F(pAdapter)) { + u8 path = (pHalData->AntennaTxPath == ANTENNA_A) ? (ODM_RF_PATH_A) : (ODM_RF_PATH_B); + + DBG_8192C("===> MPT_ProSetTxPower: Old\n"); + + RT_TRACE(_module_mp_, DBG_LOUD, ("===> MPT_ProSetTxPower[Old]:\n")); + mpt_SetTxPower_Old(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel); + mpt_SetTxPower_Old(pAdapter, MPT_OFDM_AND_HT, pMptCtx->TxPwrLevel); + + } else { + DBG_871X("===> MPT_ProSetTxPower: Jaguar\n"); + mpt_SetTxPower(pAdapter, MPT_CCK, pMptCtx->TxPwrLevel); + mpt_SetTxPower(pAdapter, MPT_OFDM, pMptCtx->TxPwrLevel); + mpt_SetTxPower(pAdapter, MPT_HT, pMptCtx->TxPwrLevel); + mpt_SetTxPower(pAdapter, MPT_VHT, pMptCtx->TxPwrLevel); + + } + } else + DBG_8192C("RFChipID < RF_TYPE_MAX, the RF chip is not supported - %d\n", pHalData->rf_chip); + + ODM_ClearTxPowerTrackingState(pDM_Odm); + +} + + +void hal_mpt_SetDataRate(PADAPTER pAdapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + u32 DataRate; + + DataRate = MptToMgntRate(pMptCtx->MptRateIndex); + + hal_mpt_SwitchRfSetting(pAdapter); + + hal_mpt_CCKTxPowerAdjust(pAdapter, pHalData->bCCKinCH14); +#ifdef CONFIG_RTL8723B + if (IS_HARDWARE_TYPE_8723B(pAdapter) || IS_HARDWARE_TYPE_8188F(pAdapter)) { + if (IS_CCK_RATE(DataRate)) { + if (pMptCtx->MptRfPath == ODM_RF_PATH_A) + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0x6); + else + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0x6); + } else { + if (pMptCtx->MptRfPath == ODM_RF_PATH_A) + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE); + else + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE); + } + } + + if ((IS_HARDWARE_TYPE_8723BS(pAdapter) && + ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)))) { + if (pMptCtx->MptRfPath == ODM_RF_PATH_A) + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, 0xF, 0xE); + else + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x71, 0xF, 0xE); + } +#endif +} + + +#define RF_PATH_AB 22 + +#ifdef CONFIG_RTL8814A +VOID mpt_ToggleIG_8814A(PADAPTER pAdapter) +{ + u1Byte Path = 0; + u4Byte IGReg = rA_IGI_Jaguar, IGvalue = 0; + + for (Path; Path <= ODM_RF_PATH_D; Path++) { + switch (Path) { + case ODM_RF_PATH_B: + IGReg = rB_IGI_Jaguar; + break; + case ODM_RF_PATH_C: + IGReg = rC_IGI_Jaguar2; + break; + case ODM_RF_PATH_D: + IGReg = rD_IGI_Jaguar2; + break; + default: + IGReg = rA_IGI_Jaguar; + break; + } + + IGvalue = PHY_QueryBBReg(pAdapter, IGReg, bMaskByte0); + PHY_SetBBReg(pAdapter, IGReg, bMaskByte0, IGvalue+2); + PHY_SetBBReg(pAdapter, IGReg, bMaskByte0, IGvalue); + } +} + +VOID mpt_SetRFPath_8814A(PADAPTER pAdapter) +{ + + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx; + R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */ + R_ANTENNA_SELECT_CCK *p_cck_txrx; + u8 ForcedDataRate = MptToMgntRate(pMptCtx->MptRateIndex); + u8 HtStbcCap = pAdapter->registrypriv.stbc_cap; + /*/PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pMgntInfo);*/ + /*/PRT_VERY_HIGH_THROUGHPUT pVHTInfo = GET_VHT_INFO(pMgntInfo);*/ + + u32 ulAntennaTx = pHalData->AntennaTxPath; + u32 ulAntennaRx = pHalData->AntennaRxPath; + u8 NssforRate = MgntQuery_NssTxRate(ForcedDataRate); + + if (NssforRate == RF_2TX) { + DBG_871X("===> SetAntenna 2T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx); + + switch (ulAntennaTx) { + case ANTENNA_BC: + pMptCtx->MptRfPath = ODM_RF_PATH_BC; + /*pHalData->ValidTxPath = 0x06; linux no use */ + PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x106); /*/ 0x940[15:4]=12'b0000_0100_0011*/ + break; + + case ANTENNA_CD: + pMptCtx->MptRfPath = ODM_RF_PATH_CD; + /*pHalData->ValidTxPath = 0x0C;*/ + PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x40c); /*/ 0x940[15:4]=12'b0000_0100_0011*/ + break; + case ANTENNA_AB: default: + pMptCtx->MptRfPath = ODM_RF_PATH_AB; + /*pHalData->ValidTxPath = 0x03;*/ + PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0000fff0, 0x043); /*/ 0x940[15:4]=12'b0000_0100_0011*/ + break; + } + + } else if (NssforRate == RF_3TX) { + DBG_871X("===> SetAntenna 3T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx); + + switch (ulAntennaTx) { + case ANTENNA_BCD: + pMptCtx->MptRfPath = ODM_RF_PATH_BCD; + /*pHalData->ValidTxPath = 0x0e;*/ + PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x90e); /*/ 0x940[27:16]=12'b0010_0100_0111*/ + break; + + case ANTENNA_ABC: default: + pMptCtx->MptRfPath = ODM_RF_PATH_ABC; + /*pHalData->ValidTxPath = 0x0d;*/ + PHY_SetBBReg(pAdapter, rTxAnt_23Nsts_Jaguar2, 0x0fff0000, 0x247); /*/ 0x940[27:16]=12'b0010_0100_0111*/ + break; + } + + } else { /*/if(NssforRate == RF_1TX)*/ + DBG_871X("===> SetAntenna 1T ForcedDataRate %d NssforRate %d AntennaTx %d\n", ForcedDataRate, NssforRate, ulAntennaTx); + switch (ulAntennaTx) { + case ANTENNA_B: + pMptCtx->MptRfPath = ODM_RF_PATH_B; + /*pHalData->ValidTxPath = 0x02;*/ + PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x4); /*/ 0xa07[7:4] = 4'b0100*/ + PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x002); /*/ 0x93C[31:20]=12'b0000_0000_0010*/ + PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x2); /* 0x80C[7:4] = 4'b0010*/ + break; + + case ANTENNA_C: + pMptCtx->MptRfPath = ODM_RF_PATH_C; + /*pHalData->ValidTxPath = 0x04;*/ + PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x2); /*/ 0xa07[7:4] = 4'b0010*/ + PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x004); /*/ 0x93C[31:20]=12'b0000_0000_0100*/ + PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x4); /*/ 0x80C[7:4] = 4'b0100*/ + break; + + case ANTENNA_D: + pMptCtx->MptRfPath = ODM_RF_PATH_D; + /*pHalData->ValidTxPath = 0x08;*/ + PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x1); /*/ 0xa07[7:4] = 4'b0001*/ + PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x008); /*/ 0x93C[31:20]=12'b0000_0000_1000*/ + PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x8); /*/ 0x80C[7:4] = 4'b1000*/ + break; + + case ANTENNA_A: default: + pMptCtx->MptRfPath = ODM_RF_PATH_A; + /*pHalData->ValidTxPath = 0x01;*/ + PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0xf0000000, 0x8); /*/ 0xa07[7:4] = 4'b1000*/ + PHY_SetBBReg(pAdapter, rTxAnt_1Nsts_Jaguar2, 0xfff00000, 0x001); /*/ 0x93C[31:20]=12'b0000_0000_0001*/ + PHY_SetBBReg(pAdapter, rTxPath_Jaguar, 0xf0, 0x1); /*/ 0x80C[7:4] = 4'b0001*/ + break; + } + } + + switch (ulAntennaRx) { + case ANTENNA_A: + /*pHalData->ValidRxPath = 0x01;*/ + PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2); + PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11); + PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3); + PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x0); + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ + /*/ CCA related PD_delay_th*/ + PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); + PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); + break; + + case ANTENNA_B: + /*pHalData->ValidRxPath = 0x02;*/ + PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2); + PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22); + PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3); + PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x1); + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ + /*/ CCA related PD_delay_th*/ + PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); + PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); + break; + + case ANTENNA_C: + /*pHalData->ValidRxPath = 0x04;*/ + PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2); + PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x44); + PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3); + PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x2); + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ + /*/ CCA related PD_delay_th*/ + PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); + PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); + break; + + case ANTENNA_D: + /*pHalData->ValidRxPath = 0x08;*/ + PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2); + PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x88); + PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3); + PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0C000000, 0x3); + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_C_0x0[19:16] = 1, Standby mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/ + /*/ CCA related PD_delay_th*/ + PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); + PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); + break; + + case ANTENNA_BC: + /*pHalData->ValidRxPath = 0x06;*/ + PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2); + PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x66); + PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3); + PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6); + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_D_0x0[19:16] = 1, Standby mode*/ + /*/ CCA related PD_delay_th*/ + PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); + PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); + break; + + case ANTENNA_CD: + /*pHalData->ValidRxPath = 0x0C;*/ + PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2); + PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xcc); + PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3); + PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0xB); + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, Rx mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/ + /*/ CCA related PD_delay_th*/ + PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x5); + PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0xA); + break; + + case ANTENNA_BCD: + /*pHalData->ValidRxPath = 0x0e;*/ + PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2); + PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xee); + PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3); + PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x6); + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_A_0x0[19:16] = 1, Standby mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, Rx mode*/ + /*/ CCA related PD_delay_th*/ + PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3); + PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8); + break; + + case ANTENNA_ABCD: + /*pHalData->ValidRxPath = 0x0f;*/ + PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x2); + PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0xff); + PHY_SetBBReg(pAdapter, 0x1000, bMaskByte2, 0x3); + PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, 0x0f000000, 0x1); + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_A_0x0[19:16] = 3, RX mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, RX mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_C, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_C_0x0[19:16] = 3, RX mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_D, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_D_0x0[19:16] = 3, RX mode*/ + /*/ CCA related PD_delay_th*/ + PHY_SetBBReg(pAdapter, rAGC_table_Jaguar, 0x0F000000, 0x3); + PHY_SetBBReg(pAdapter, rPwed_TH_Jaguar, 0x0000000F, 0x8); + break; + + default: + RT_TRACE(_module_mp_, _drv_warning_, ("Unknown Rx antenna.\n")); + break; + } + + PHY_Set_SecCCATH_by_RXANT_8814A(pAdapter, ulAntennaRx); + + mpt_ToggleIG_8814A(pAdapter); + RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n")); +} + +VOID +mpt_SetSingleTone_8814A( + IN PADAPTER pAdapter, + IN BOOLEAN bSingleTone, + IN BOOLEAN bEnPMacTx) +{ + + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + u1Byte StartPath = ODM_RF_PATH_A, EndPath = ODM_RF_PATH_A; + static u4Byte regIG0 = 0, regIG1 = 0, regIG2 = 0, regIG3 = 0; + + if (bSingleTone) { + regIG0 = PHY_QueryBBReg(pAdapter, rA_TxScale_Jaguar, bMaskDWord); /*/ 0xC1C[31:21]*/ + regIG1 = PHY_QueryBBReg(pAdapter, rB_TxScale_Jaguar, bMaskDWord); /*/ 0xE1C[31:21]*/ + regIG2 = PHY_QueryBBReg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord); /*/ 0x181C[31:21]*/ + regIG3 = PHY_QueryBBReg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord); /*/ 0x1A1C[31:21]*/ + + switch (pMptCtx->MptRfPath) { + case ODM_RF_PATH_A: case ODM_RF_PATH_B: + case ODM_RF_PATH_C: case ODM_RF_PATH_D: + StartPath = pMptCtx->MptRfPath; + EndPath = pMptCtx->MptRfPath; + break; + case ODM_RF_PATH_AB: + EndPath = ODM_RF_PATH_B; + break; + case ODM_RF_PATH_BC: + StartPath = ODM_RF_PATH_B; + EndPath = ODM_RF_PATH_C; + break; + case ODM_RF_PATH_ABC: + EndPath = ODM_RF_PATH_C; + break; + case ODM_RF_PATH_BCD: + StartPath = ODM_RF_PATH_B; + EndPath = ODM_RF_PATH_D; + break; + case ODM_RF_PATH_ABCD: + EndPath = ODM_RF_PATH_D; + break; + } + + if (bEnPMacTx == FALSE) { + hal_mpt_SetOFDMContinuousTx(pAdapter, _TRUE); + issue_nulldata(pAdapter, NULL, 1, 3, 500); + } + + PHY_SetBBReg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x1); /*/ Disable CCA*/ + + for (StartPath; StartPath <= EndPath; StartPath++) { + PHY_SetRFReg(pAdapter, StartPath, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */ + PHY_SetRFReg(pAdapter, StartPath, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/ + + PHY_SetRFReg(pAdapter, StartPath, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/ + } + + PHY_SetBBReg(pAdapter, rA_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xC1C[31:21]*/ + PHY_SetBBReg(pAdapter, rB_TxScale_Jaguar, 0xFFE00000, 0); /*/ 0xE1C[31:21]*/ + PHY_SetBBReg(pAdapter, rC_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x181C[31:21]*/ + PHY_SetBBReg(pAdapter, rD_TxScale_Jaguar2, 0xFFE00000, 0); /*/ 0x1A1C[31:21]*/ + + } else { + + switch (pMptCtx->MptRfPath) { + case ODM_RF_PATH_A: case ODM_RF_PATH_B: + case ODM_RF_PATH_C: case ODM_RF_PATH_D: + StartPath = pMptCtx->MptRfPath; + EndPath = pMptCtx->MptRfPath; + break; + case ODM_RF_PATH_AB: + EndPath = ODM_RF_PATH_B; + break; + case ODM_RF_PATH_BC: + StartPath = ODM_RF_PATH_B; + EndPath = ODM_RF_PATH_C; + break; + case ODM_RF_PATH_ABC: + EndPath = ODM_RF_PATH_C; + break; + case ODM_RF_PATH_BCD: + StartPath = ODM_RF_PATH_B; + EndPath = ODM_RF_PATH_D; + break; + case ODM_RF_PATH_ABCD: + EndPath = ODM_RF_PATH_D; + break; + } + + for (StartPath; StartPath <= EndPath; StartPath++) + PHY_SetRFReg(pAdapter, StartPath, LNA_Low_Gain_3, BIT1, 0x0); /*// RF LO disabled*/ + + + PHY_SetBBReg(pAdapter, rCCAonSec_Jaguar, BIT1, 0x0); /* Enable CCA*/ + + if (bEnPMacTx == FALSE) + hal_mpt_SetOFDMContinuousTx(pAdapter, _FALSE); + + PHY_SetBBReg(pAdapter, rA_TxScale_Jaguar, bMaskDWord, regIG0); /* 0xC1C[31:21]*/ + PHY_SetBBReg(pAdapter, rB_TxScale_Jaguar, bMaskDWord, regIG1); /* 0xE1C[31:21]*/ + PHY_SetBBReg(pAdapter, rC_TxScale_Jaguar2, bMaskDWord, regIG2); /* 0x181C[31:21]*/ + PHY_SetBBReg(pAdapter, rD_TxScale_Jaguar2, bMaskDWord, regIG3); /* 0x1A1C[31:21]*/ + } +} + +#endif + +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) +void mpt_SetRFPath_8812A(PADAPTER pAdapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx; + u32 ulAntennaTx, ulAntennaRx; + + ulAntennaTx = pHalData->AntennaTxPath; + ulAntennaRx = pHalData->AntennaRxPath; + + switch (ulAntennaTx) { + case ANTENNA_A: + pMptCtx->MptRfPath = ODM_RF_PATH_A; + PHY_SetBBReg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x1111); + if (pHalData->RFEType == 3 && IS_HARDWARE_TYPE_8812(pAdapter)) + PHY_SetBBReg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0); + break; + case ANTENNA_B: + pMptCtx->MptRfPath = ODM_RF_PATH_B; + PHY_SetBBReg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x2222); + if (pHalData->RFEType == 3 && IS_HARDWARE_TYPE_8812(pAdapter)) + PHY_SetBBReg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x1); + break; + case ANTENNA_AB: + pMptCtx->MptRfPath = ODM_RF_PATH_AB; + PHY_SetBBReg(pAdapter, rTxPath_Jaguar, bMaskLWord, 0x3333); + if (pHalData->RFEType == 3 && IS_HARDWARE_TYPE_8812(pAdapter)) + PHY_SetBBReg(pAdapter, r_ANTSEL_SW_Jaguar, bMask_AntselPathFollow_Jaguar, 0x0); + break; + default: + pMptCtx->MptRfPath = ODM_RF_PATH_AB; + DBG_871X("Unknown Tx antenna.\n"); + break; + } + + switch (ulAntennaRx) { + u32 reg0xC50 = 0; + case ANTENNA_A: + PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x11); + PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x1); /*/ RF_B_0x0[19:16] = 1, Standby mode*/ + PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0); + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, BIT19|BIT18|BIT17|BIT16, 0x3); + + /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/ + reg0xC50 = PHY_QueryBBReg(pAdapter, rA_IGI_Jaguar, bMaskByte0); + PHY_SetBBReg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50+2); + PHY_SetBBReg(pAdapter, rA_IGI_Jaguar, bMaskByte0, reg0xC50); + break; + case ANTENNA_B: + PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x22); + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, 0xF0000, 0x1);/*/ RF_A_0x0[19:16] = 1, Standby mode */ + PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x1); + PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, BIT19|BIT18|BIT17|BIT16, 0x3); + + /*/ <20121101, Kordan> To prevent gain table from not switched, asked by Ynlin.*/ + reg0xC50 = PHY_QueryBBReg(pAdapter, rB_IGI_Jaguar, bMaskByte0); + PHY_SetBBReg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50+2); + PHY_SetBBReg(pAdapter, rB_IGI_Jaguar, bMaskByte0, reg0xC50); + break; + case ANTENNA_AB: + PHY_SetBBReg(pAdapter, rRxPath_Jaguar, bMaskByte0, 0x33); + PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_AC_Jaguar, 0xF0000, 0x3); /*/ RF_B_0x0[19:16] = 3, Rx mode*/ + PHY_SetBBReg(pAdapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0); + break; + default: + DBG_871X("Unknown Rx antenna.\n"); + break; + } + RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n")); +} +#endif + + +#ifdef CONFIG_RTL8723B +void mpt_SetRFPath_8723B(PADAPTER pAdapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + u32 ulAntennaTx, ulAntennaRx; + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ulAntennaTx = pHalData->AntennaTxPath; + ulAntennaRx = pHalData->AntennaRxPath; + + if (pHalData->rf_chip >= RF_TYPE_MAX) { + DBG_8192C("This RF chip ID is not supported\n"); + return; + } + + switch (pAdapter->mppriv.antenna_tx) { + u8 p = 0, i = 0; + case ANTENNA_A: /*/ Actually path S1 (Wi-Fi)*/ + { + pMptCtx->MptRfPath = ODM_RF_PATH_A; + PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7, 0x0); + PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/ + + /*/<20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.*/ + if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)) + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E); + else + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E); + + + for (i = 0; i < 3; ++i) { + u4Byte offset = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][0]; + u4Byte data = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][1]; + + if (offset != 0) { + PHY_SetBBReg(pAdapter, offset, bMaskDWord, data); + DBG_8192C("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data); + } + + } + for (i = 0; i < 2; ++i) { + u4Byte offset = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][0]; + u4Byte data = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][1]; + + if (offset != 0) { + PHY_SetBBReg(pAdapter, offset, bMaskDWord, data); + DBG_8192C("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data); + } + } + } + break; + case ANTENNA_B: /*/ Actually path S0 (BT)*/ + { + u4Byte offset; + u4Byte data; + + pMptCtx->MptRfPath = ODM_RF_PATH_B; + PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7, 0x5); + PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x1); /*/ AGC Table Sel.*/ + + /* <20130522, Kordan> 0x51 and 0x71 should be set immediately after path switched, or they might be overwritten.*/ + if ((pHalData->PackageType == PACKAGE_TFBGA79) || (pHalData->PackageType == PACKAGE_TFBGA90)) + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B10E); + else + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E); + + for (i = 0; i < 3; ++i) { + /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/ + offset = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_A][i][0]; + data = pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_B][i][1]; + if (pRFCalibrateInfo->TxIQC_8723B[ODM_RF_PATH_B][i][0] != 0) { + PHY_SetBBReg(pAdapter, offset, bMaskDWord, data); + DBG_8192C("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data); + } + } + /*/ <20130603, Kordan> Because BB suppors only 1T1R, we restore IQC to S1 instead of S0.*/ + for (i = 0; i < 2; ++i) { + offset = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_A][i][0]; + data = pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_B][i][1]; + + if (pRFCalibrateInfo->RxIQC_8723B[ODM_RF_PATH_B][i][0] != 0) { + PHY_SetBBReg(pAdapter, offset, bMaskDWord, data); + DBG_8192C("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data); + } + } + } + break; + default: + pMptCtx->MptRfPath = RF_PATH_AB; + RT_TRACE(_module_mp_, _drv_notice_, ("Unknown Tx antenna.\n")); + break; + } + RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n")); +} +#endif + +#ifdef CONFIG_RTL8703B +void mpt_SetRFPath_8703B(PADAPTER pAdapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + u4Byte ulAntennaTx, ulAntennaRx; + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ulAntennaTx = pHalData->AntennaTxPath; + ulAntennaRx = pHalData->AntennaRxPath; + + if (pHalData->rf_chip >= RF_TYPE_MAX) { + DBG_871X("This RF chip ID is not supported\n"); + return; + } + + switch (pAdapter->mppriv.antenna_tx) { + u1Byte p = 0, i = 0; + + case ANTENNA_A: /* Actually path S1 (Wi-Fi) */ + { + pMptCtx->MptRfPath = ODM_RF_PATH_A; + PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7, 0x0); + PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x0); /* AGC Table Sel*/ + + for (i = 0; i < 3; ++i) { + u4Byte offset = pRFCalibrateInfo->TxIQC_8703B[i][0]; + u4Byte data = pRFCalibrateInfo->TxIQC_8703B[i][1]; + + if (offset != 0) { + PHY_SetBBReg(pAdapter, offset, bMaskDWord, data); + DBG_871X("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data); + } + + } + for (i = 0; i < 2; ++i) { + u4Byte offset = pRFCalibrateInfo->RxIQC_8703B[i][0]; + u4Byte data = pRFCalibrateInfo->RxIQC_8703B[i][1]; + + if (offset != 0) { + PHY_SetBBReg(pAdapter, offset, bMaskDWord, data); + DBG_871X("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data); + } + } + } + break; + case ANTENNA_B: /* Actually path S0 (BT)*/ + { + pMptCtx->MptRfPath = ODM_RF_PATH_B; + PHY_SetBBReg(pAdapter, rS0S1_PathSwitch, BIT9|BIT8|BIT7, 0x5); + PHY_SetBBReg(pAdapter, 0xB2C, BIT31, 0x1); /* AGC Table Sel */ + + for (i = 0; i < 3; ++i) { + u4Byte offset = pRFCalibrateInfo->TxIQC_8703B[i][0]; + u4Byte data = pRFCalibrateInfo->TxIQC_8703B[i][1]; + + if (pRFCalibrateInfo->TxIQC_8703B[i][0] != 0) { + PHY_SetBBReg(pAdapter, offset, bMaskDWord, data); + DBG_871X("Switch to S0 TxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data); + } + } + for (i = 0; i < 2; ++i) { + u4Byte offset = pRFCalibrateInfo->RxIQC_8703B[i][0]; + u4Byte data = pRFCalibrateInfo->RxIQC_8703B[i][1]; + + if (pRFCalibrateInfo->RxIQC_8703B[i][0] != 0) { + PHY_SetBBReg(pAdapter, offset, bMaskDWord, data); + DBG_871X("Switch to S0 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data); + } + } + } + break; + default: + pMptCtx->MptRfPath = RF_PATH_AB; + RT_TRACE(_module_mp_, _drv_notice_, ("Unknown Tx antenna.\n")); + break; + } + + RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n")); +} +#endif + + +VOID mpt_SetRFPath_819X(PADAPTER pAdapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + u4Byte ulAntennaTx, ulAntennaRx; + R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */ + R_ANTENNA_SELECT_CCK *p_cck_txrx; + u1Byte r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0; + u1Byte chgTx = 0, chgRx = 0; + u4Byte r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0; + + ulAntennaTx = pHalData->AntennaTxPath; + ulAntennaRx = pHalData->AntennaRxPath; + + p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val; + p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val; + + p_ofdm_tx->r_ant_ht1 = 0x1; + p_ofdm_tx->r_ant_ht2 = 0x2;/*Second TX RF path is A*/ + p_ofdm_tx->r_ant_non_ht = 0x3;/*/ 0x1+0x2=0x3 */ + + switch (ulAntennaTx) { + case ANTENNA_A: + p_ofdm_tx->r_tx_antenna = 0x1; + r_ofdm_tx_en_val = 0x1; + p_ofdm_tx->r_ant_l = 0x1; + p_ofdm_tx->r_ant_ht_s1 = 0x1; + p_ofdm_tx->r_ant_non_ht_s1 = 0x1; + p_cck_txrx->r_ccktx_enable = 0x8; + chgTx = 1; + /*/ From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/ + /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/ + { + PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2); + PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1); + r_ofdm_tx_en_val = 0x3; + /*/ Power save*/ + /*/cosa r_ant_select_ofdm_val = 0x11111111;*/ + /*/ We need to close RFB by SW control*/ + if (pHalData->rf_type == RF_2T2R) { + PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0); + PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1); + PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0); + PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1); + PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0); + } + } + pMptCtx->MptRfPath = ODM_RF_PATH_A; + break; + case ANTENNA_B: + p_ofdm_tx->r_tx_antenna = 0x2; + r_ofdm_tx_en_val = 0x2; + p_ofdm_tx->r_ant_l = 0x2; + p_ofdm_tx->r_ant_ht_s1 = 0x2; + p_ofdm_tx->r_ant_non_ht_s1 = 0x2; + p_cck_txrx->r_ccktx_enable = 0x4; + chgTx = 1; + /*/ From SD3 Willis suggestion !!! Set RF A as standby*/ + /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/ + { + PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1); + PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2); + + /*/ 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.*/ + /*/ 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control*/ + if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) { + PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1); + PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0); + PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0); + /*/PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/ + PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0); + PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1); + } + } + pMptCtx->MptRfPath = ODM_RF_PATH_B; + break; + case ANTENNA_AB:/*/ For 8192S*/ + p_ofdm_tx->r_tx_antenna = 0x3; + r_ofdm_tx_en_val = 0x3; + p_ofdm_tx->r_ant_l = 0x3; + p_ofdm_tx->r_ant_ht_s1 = 0x3; + p_ofdm_tx->r_ant_non_ht_s1 = 0x3; + p_cck_txrx->r_ccktx_enable = 0xC; + chgTx = 1; + /*/ From SD3Willis suggestion !!! Set RF B as standby*/ + /*/if (IS_HARDWARE_TYPE_8192S(pAdapter))*/ + { + PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2); + PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2); + /* Disable Power save*/ + /*cosa r_ant_select_ofdm_val = 0x3321333;*/ + /* 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control*/ + if (pHalData->rf_type == RF_2T2R) { + PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0); + + PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0); + /*/PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);*/ + PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1); + PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1); + } + } + pMptCtx->MptRfPath = ODM_RF_PATH_AB; + break; + default: + break; + } + + + +/*// r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D +// r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D +// r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D */ + switch (ulAntennaRx) { + case ANTENNA_A: + r_rx_antenna_ofdm = 0x1; /* A*/ + p_cck_txrx->r_cckrx_enable = 0x0; /* default: A*/ + p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A*/ + chgRx = 1; + break; + case ANTENNA_B: + r_rx_antenna_ofdm = 0x2; /*/ B*/ + p_cck_txrx->r_cckrx_enable = 0x1; /*/ default: B*/ + p_cck_txrx->r_cckrx_enable_2 = 0x1; /*/ option: B*/ + chgRx = 1; + break; + case ANTENNA_AB:/*/ For 8192S and 8192E/U...*/ + r_rx_antenna_ofdm = 0x3;/*/ AB*/ + p_cck_txrx->r_cckrx_enable = 0x0;/*/ default:A*/ + p_cck_txrx->r_cckrx_enable_2 = 0x1;/*/ option:B*/ + chgRx = 1; + break; + default: + break; + } + + + if (chgTx && chgRx) { + switch (pHalData->rf_chip) { + case RF_8225: + case RF_8256: + case RF_6052: + /*/r_ant_sel_cck_val = r_ant_select_cck_val;*/ + PHY_SetBBReg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); /*/OFDM Tx*/ + PHY_SetBBReg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); /*/OFDM Tx*/ + PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/ + PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); /*/OFDM Rx*/ + if (IS_HARDWARE_TYPE_8192E(pAdapter)) { + PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/ + PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x000000F0, r_rx_antenna_ofdm); /*/OFDM Rx*/ + } + PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);/*/r_ant_sel_cck_val); /CCK TxRx*/ + break; + + default: + DBG_871X("Unsupported RFChipID for switching antenna.\n"); + break; + } + } +} /* MPT_ProSetRFPath */ + + +void hal_mpt_SetAntenna(PADAPTER pAdapter) + +{ + DBG_871X("Do %s\n", __func__); +#ifdef CONFIG_RTL8814A + if (IS_HARDWARE_TYPE_8814A(pAdapter)) { + mpt_SetRFPath_8814A(pAdapter); + return; + } +#endif +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) + if (IS_HARDWARE_TYPE_JAGUAR(pAdapter)) { + mpt_SetRFPath_8812A(pAdapter); + return; + } +#endif +#ifdef CONFIG_RTL8723B + if (IS_HARDWARE_TYPE_8723B(pAdapter)) { + mpt_SetRFPath_8723B(pAdapter); + return; + } +#endif +#ifdef CONFIG_RTL8703B + if (IS_HARDWARE_TYPE_8703B(pAdapter)) { + mpt_SetRFPath_8703B(pAdapter); + return; + } +#endif + +/* else if (IS_HARDWARE_TYPE_8821B(pAdapter)) + mpt_SetRFPath_8821B(pAdapter); + Prepare for 8822B + else if (IS_HARDWARE_TYPE_8822B(Context)) + mpt_SetRFPath_8822B(Context); +*/ + mpt_SetRFPath_819X(pAdapter); + DBG_871X("mpt_SetRFPath_819X Do %s\n", __func__); + +} + + +s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + if (!netif_running(pAdapter->pnetdev)) { + RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter! Fail: interface not opened!\n")); + return _FAIL; + } + + + if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) { + RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter: Fail! not in MP mode!\n")); + return _FAIL; + } + + + target_ther &= 0xff; + if (target_ther < 0x07) + target_ther = 0x07; + else if (target_ther > 0x1d) + target_ther = 0x1d; + + pHalData->EEPROMThermalMeter = target_ther; + + return _SUCCESS; +} + + +void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter) +{ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x42, BIT17 | BIT16, 0x03); + +} + + +u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter) + +{ + u32 ThermalValue = 0; + + ThermalValue = (u1Byte)PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, 0x42, 0xfc00); /*0x42: RF Reg[15:10]*/ + return (u8)ThermalValue; + +} + + +void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 *value) +{ +#if 0 + fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER); + rtw_msleep_os(1000); + fw_cmd_data(pAdapter, value, 1); + *value &= 0xFF; +#else + hal_mpt_TriggerRFThermalMeter(pAdapter); + rtw_msleep_os(1000); + *value = hal_mpt_ReadRFThermalMeter(pAdapter); +#endif + +} + + +void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + pAdapter->mppriv.MptCtx.bSingleCarrier = bStart; + + if (bStart) {/*/ Start Single Carrier.*/ + RT_TRACE(_module_mp_, _drv_alert_, ("SetSingleCarrierTx: test start\n")); + /*/ Start Single Carrier.*/ + /*/ 1. if OFDM block on?*/ + if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) + PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1); /*set OFDM block on*/ + + /*/ 2. set CCK test mode off, set to CCK normal mode*/ + PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0); + + /*/ 3. turn on scramble setting*/ + PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 1); + + /*/ 4. Turn On Continue Tx and turn off the other test modes.*/ +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) + if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/) + PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18|BIT17|BIT16, OFDM_SingleCarrier); + else +#endif + PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_SingleCarrier); + + } else { + /*/ Stop Single Carrier.*/ + /*/ Stop Single Carrier.*/ + /*/ Turn off all test modes.*/ +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) + if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/) + PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18|BIT17|BIT16, OFDM_ALL_OFF); + else +#endif + + PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF); + + rtw_msleep_os(10); + /*/BB Reset*/ + PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); + PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); + } +} + + +void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + u4Byte ulAntennaTx = pHalData->AntennaTxPath; + static u4Byte regRF = 0, regBB0 = 0, regBB1 = 0, regBB2 = 0, regBB3 = 0; + u8 rfPath; + + switch (ulAntennaTx) { + case ANTENNA_B: + rfPath = ODM_RF_PATH_B; + break; + case ANTENNA_C: + rfPath = ODM_RF_PATH_C; + break; + case ANTENNA_D: + rfPath = ODM_RF_PATH_D; + break; + case ANTENNA_A: + default: + rfPath = ODM_RF_PATH_A; + break; + } + + pAdapter->mppriv.MptCtx.bSingleTone = bStart; + if (bStart) { + /*/ Start Single Tone.*/ + /*/ <20120326, Kordan> To amplify the power of tone for Xtal calibration. (asked by Edlu)*/ + if (IS_HARDWARE_TYPE_8188E(pAdapter)) { + regRF = PHY_QueryRFReg(pAdapter, rfPath, LNA_Low_Gain_3, bRFRegOffsetMask); + + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/ + PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0); + PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0); + } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { /*/ USB need to do RF LO disable first, PCIE isn't required to follow this order.*/ + /*/Set MAC REG 88C: Prevent SingleTone Fail*/ + PHY_SetMacReg(pAdapter, 0x88C, 0xF00000, 0xF); + PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO disabled*/ + PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/ + } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) { + if (pMptCtx->MptRfPath == ODM_RF_PATH_A) { + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x1); /*/ RF LO enabled*/ + } else { + /*/ S0/S1 both use PATH A to configure*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /*/ Tx mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x1); /*/ RF LO enabled*/ + } + } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) { + if (pMptCtx->MptRfPath == ODM_RF_PATH_A) { + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x2); /* Tx mode */ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x53, 0xF000, 0x1); /* RF LO enabled */ + } + } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) { + /*Set BB REG 88C: Prevent SingleTone Fail*/ + PHY_SetBBReg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xF); + PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1); + PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x2); + } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter)) { +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) + u1Byte p = ODM_RF_PATH_A; + + regRF = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC_Jaguar, bRFRegOffsetMask); + regBB0 = PHY_QueryBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord); + regBB1 = PHY_QueryBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord); + regBB2 = PHY_QueryBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, bMaskDWord); + regBB3 = PHY_QueryBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, bMaskDWord); + + PHY_SetBBReg(pAdapter, rOFDMCCKEN_Jaguar, BIT29|BIT28, 0x0); /*/ Disable CCK and OFDM*/ + + if (pMptCtx->MptRfPath == ODM_RF_PATH_AB) { + for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) { + PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */ + PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/ + PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/ + } + } else { + PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC_Jaguar, 0xF0000, 0x2); /*/ Tx mode: RF0x00[19:16]=4'b0010 */ + PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC_Jaguar, 0x1F, 0x0); /*/ Lowest RF gain index: RF_0x0[4:0] = 0*/ + PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x1); /*/ RF LO enabled*/ + } + + PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/ + PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, 0xFF00F0, 0x77007); /*/ 0xCB0[[23:16, 7:4] = 0x77007*/ + + if (pHalData->ExternalPA_5G) { + PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x12); /*/ 0xCB4[23:16] = 0x12*/ + PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x12); /*/ 0xEB4[23:16] = 0x12*/ + } else if (pHalData->ExternalPA_2G) { + PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x11); /*/ 0xCB4[23:16] = 0x11*/ + PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, 0xFF00000, 0x11); /*/ 0xEB4[23:16] = 0x11*/ + } +#endif + } +#ifdef CONFIG_RTL8814A + else if (IS_HARDWARE_TYPE_8814A(pAdapter)) + mpt_SetSingleTone_8814A(pAdapter, TRUE, FALSE); +#endif + else /*/ Turn On SingleTone and turn off the other test modes.*/ + PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_SingleTone); + + write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); + write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); + + } else {/*/ Stop Single Ton e.*/ + + if (IS_HARDWARE_TYPE_8188E(pAdapter)) { + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, LNA_Low_Gain_3, bRFRegOffsetMask, regRF); + PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1); + PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1); + } else if (IS_HARDWARE_TYPE_8192E(pAdapter)) { + PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x3);/*/ Tx mode*/ + PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x0);/*/ RF LO disabled */ + /*/ RESTORE MAC REG 88C: Enable RF Functions*/ + PHY_SetMacReg(pAdapter, 0x88C, 0xF00000, 0x0); + } else if (IS_HARDWARE_TYPE_8723B(pAdapter)) { + if (pMptCtx->MptRfPath == ODM_RF_PATH_A) { + + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x56, 0xF, 0x0); /*/ RF LO disabled*/ + } else { + /*/ S0/S1 both use PATH A to configure*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /*/ Rx mode*/ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x76, 0xF, 0x0); /*/ RF LO disabled*/ + } + } else if (IS_HARDWARE_TYPE_8703B(pAdapter)) { + + if (pMptCtx->MptRfPath == ODM_RF_PATH_A) { + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, 0xF0000, 0x3); /* Rx mode */ + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, 0x53, 0xF000, 0x0); /* RF LO disabled */ + } + } else if (IS_HARDWARE_TYPE_8188F(pAdapter)) { + PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, RF_AC, 0xF0000, 0x3); /*Tx mode*/ + PHY_SetRFReg(pAdapter, pMptCtx->MptRfPath, LNA_Low_Gain_3, BIT1, 0x0); /*RF LO disabled*/ + /*Set BB REG 88C: Prevent SingleTone Fail*/ + PHY_SetBBReg(pAdapter, rFPGA0_AnalogParameter4, 0xF00000, 0xc); + } else if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8822B(pAdapter)) { +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) + u1Byte p = ODM_RF_PATH_A; + + PHY_SetBBReg(pAdapter, rOFDMCCKEN_Jaguar, BIT29|BIT28, 0x3); /*/ Disable CCK and OFDM*/ + + if (pMptCtx->MptRfPath == ODM_RF_PATH_AB) { + for (p = ODM_RF_PATH_A; p <= ODM_RF_PATH_B; ++p) { + PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF); + PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x0); /*/ RF LO disabled*/ + } + } else { + PHY_SetRFReg(pAdapter, p, RF_AC_Jaguar, bRFRegOffsetMask, regRF); + PHY_SetRFReg(pAdapter, p, LNA_Low_Gain_3, BIT1, 0x0); /*/ RF LO disabled*/ + } + + PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar, bMaskDWord, regBB0); + PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar, bMaskDWord, regBB1); + PHY_SetBBReg(pAdapter, rA_RFE_Pinmux_Jaguar+4, bMaskDWord, regBB2); + PHY_SetBBReg(pAdapter, rB_RFE_Pinmux_Jaguar+4, bMaskDWord, regBB3); +#endif + } +#ifdef CONFIG_RTL8814A + else if (IS_HARDWARE_TYPE_8814A(pAdapter)) + mpt_SetSingleTone_8814A(pAdapter, FALSE, FALSE); + + else/*/ Turn off all test modes.*/ + PHY_SetBBReg(pAdapter, rSingleTone_ContTx_Jaguar, BIT18|BIT17|BIT16, OFDM_ALL_OFF); +#endif + write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); + write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); + + } +} + + +void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart) +{ + u8 Rate; + pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart; + + Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx); + if (bStart) {/* Start Carrier Suppression.*/ + RT_TRACE(_module_mp_, _drv_alert_, ("SetCarrierSuppressionTx: test start\n")); + if (Rate <= MPT_RATE_11M) { + /*/ 1. if CCK block on?*/ + if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn)) + write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/ + + /*/Turn Off All Test Mode*/ + if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/) + PHY_SetBBReg(pAdapter, 0x914, BIT18|BIT17|BIT16, OFDM_ALL_OFF);/* rSingleTone_ContTx_Jaguar*/ + else + PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF); + + write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*/transmit mode*/ + write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); /*/turn off scramble setting*/ + + /*/Set CCK Tx Test Rate*/ + write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); /*/Set FTxRate to 1Mbps*/ + } + + /*Set for dynamic set Power index*/ + write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); + write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); + + } else {/* Stop Carrier Suppression.*/ + RT_TRACE(_module_mp_, _drv_alert_, ("SetCarrierSuppressionTx: test stop\n")); + + if (Rate <= MPT_RATE_11M) { + write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/ + write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/ + + /*BB Reset*/ + write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); + write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); + } + /*Stop for dynamic set Power index*/ + write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); + write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); + } + DBG_871X("\n MPT_ProSetCarrierSupp() is finished.\n"); +} + +void hal_mpt_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart) +{ + u32 cckrate; + + if (bStart) { + RT_TRACE(_module_mp_, _drv_alert_, + ("SetCCKContinuousTx: test start\n")); + + /*/ 1. if CCK block on?*/ + if (!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn)) + write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);/*set CCK block on*/ + + /*/Turn Off All Test Mode*/ + if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) + PHY_SetBBReg(pAdapter, 0x914, BIT18|BIT17|BIT16, OFDM_ALL_OFF);/*rSingleTone_ContTx_Jaguar*/ + else + PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF); + + /*/Set CCK Tx Test Rate*/ + + cckrate = pAdapter->mppriv.rateidx; + + write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate); + write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*/transmit mode*/ + write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); /*/turn on scramble setting*/ + + if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) { + PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3); /* rCCK0_RxHP 0xa15[1:0] = 11 force cck rxiq = 0*/ + PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /*/ 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/ + PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1); + PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 1); + } + + write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); + write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); + + } else { + RT_TRACE(_module_mp_, _drv_info_, + ("SetCCKContinuousTx: test stop\n")); + + write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*/normal mode*/ + write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); /*/turn on scramble setting*/ + + if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_8814A(pAdapter) /* && !IS_HARDWARE_TYPE_8822B(pAdapter) */) { + PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0);/* rCCK0_RxHP 0xa15[1:0] = 2b00*/ + PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /*/ 0xc08[16] = 0*/ + + PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0); + PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 0); + } + + /*/BB Reset*/ + write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); + write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); + + write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); + write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); + } + + pAdapter->mppriv.MptCtx.bCckContTx = bStart; + pAdapter->mppriv.MptCtx.bOfdmContTx = _FALSE; +} + +void hal_mpt_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + if (bStart) { + RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test start\n"));/*/ 1. if OFDM block on?*/ + if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) + PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*/set OFDM block on*/ + + /*/ 2. set CCK test mode off, set to CCK normal mode*/ + PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0); + + /*/ 3. turn on scramble setting*/ + PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 1); + + if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_8814A(pAdapter) /*&& !IS_HARDWARE_TYPE_8822B(pAdapter)*/) { + PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3); /* rCCK0_RxHP 0xa15[1:0] = 2b'11*/ + PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1*/ + } + + /*/ 4. Turn On Continue Tx and turn off the other test modes.*/ + if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/) + PHY_SetBBReg(pAdapter, 0x914, BIT18|BIT17|BIT16, OFDM_ContinuousTx);/*rSingleTone_ContTx_Jaguar*/ + else + PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ContinuousTx); + + write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); + write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); + + } else { + RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test stop\n")); + if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_8814A(pAdapter) /*|| IS_HARDWARE_TYPE_8822B(pAdapter)*/) + PHY_SetBBReg(pAdapter, 0x914, BIT18|BIT17|BIT16, OFDM_ALL_OFF); + else + PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF); + /*/Delay 10 ms*/ + rtw_msleep_os(10); + + if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_8814A(pAdapter) /*&&! IS_HARDWARE_TYPE_8822B(pAdapter)*/) { + PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0);/*/ 0xa15[1:0] = 0*/ + PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0);/*/ 0xc08[16] = 0*/ + } + + /*/BB Reset*/ + PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); + PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); + + write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); + write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); + } + + pAdapter->mppriv.MptCtx.bCckContTx = _FALSE; + pAdapter->mppriv.MptCtx.bOfdmContTx = bStart; +} + +void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart) +{ + u8 Rate; + RT_TRACE(_module_mp_, _drv_info_, + ("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx)); + + Rate = HwRateToMPTRate(pAdapter->mppriv.rateidx); + pAdapter->mppriv.MptCtx.bStartContTx = bStart; + + if (Rate <= MPT_RATE_11M) + hal_mpt_SetCCKContinuousTx(pAdapter, bStart); + else if (Rate >= MPT_RATE_6M) + hal_mpt_SetOFDMContinuousTx(pAdapter, bStart); +} + +u32 hal_mpt_query_phytxok(PADAPTER pAdapter) +{ + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo; + u16 count = 0; + + if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) + count = PHY_QueryBBReg(pAdapter, 0xF50, bMaskLWord); /* [15:0]*/ + else + count = PHY_QueryBBReg(pAdapter, 0xF50, bMaskHWord); /* [31:16]*/ + + if (count > 50000) { + rtw_reset_phy_trx_ok_counters(pAdapter); + pAdapter->mppriv.tx.sended += count; + count = 0; + } + + return pAdapter->mppriv.tx.sended + count; + +} + +#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) +/* for HW TX mode */ +static VOID mpt_StopCckContTx( + PADAPTER pAdapter + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + u1Byte u1bReg; + + pMptCtx->bCckContTx = FALSE; + pMptCtx->bOfdmContTx = FALSE; + + PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); /*normal mode*/ + PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/ + + if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) { + PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 2b00*/ + PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/ + + PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 0); + PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 0); + } + + /*BB Reset*/ + PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); + PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); + + PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); + PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); + +} /* mpt_StopCckContTx */ + + +static VOID mpt_StopOfdmContTx( + PADAPTER pAdapter + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + u1Byte u1bReg; + u4Byte data; + + pMptCtx->bCckContTx = FALSE; + pMptCtx->bOfdmContTx = FALSE; + + if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) + PHY_SetBBReg(pAdapter, 0x914, BIT18|BIT17|BIT16, OFDM_ALL_OFF); + else + PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF); + + rtw_mdelay_os(10); + + if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) { + PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x0); /* 0xa15[1:0] = 0*/ + PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x0); /* 0xc08[16] = 0*/ + } + + /*BB Reset*/ + PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); + PHY_SetBBReg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); + + PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); + PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); +} /* mpt_StopOfdmContTx */ + + +static VOID mpt_StartCckContTx( + PADAPTER pAdapter + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + u4Byte cckrate; + + /* 1. if CCK block on */ + if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn)) + PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bCCKEn, 1);/*set CCK block on*/ + + /*Turn Off All Test Mode*/ + if (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) + PHY_SetBBReg(pAdapter, 0x914, BIT18|BIT17|BIT16, OFDM_ALL_OFF); + else + PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ALL_OFF); + + cckrate = pAdapter->mppriv.rateidx; + + PHY_SetBBReg(pAdapter, rCCK0_System, bCCKTxRate, cckrate); + + PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); /*transmit mode*/ + PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 0x1); /*turn on scramble setting*/ + + if (!IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(pAdapter)) { + PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 11 force cck rxiq = 0*/ + PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1 force ofdm rxiq = ofdm txiq*/ + PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, BIT14, 1); + PHY_SetBBReg(pAdapter, 0x0B34, BIT14, 1); + } + + PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); + PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); + + pMptCtx->bCckContTx = TRUE; + pMptCtx->bOfdmContTx = FALSE; + +} /* mpt_StartCckContTx */ + + +static VOID mpt_StartOfdmContTx( + PADAPTER pAdapter + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); + + /* 1. if OFDM block on?*/ + if (!PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) + PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 1);/*set OFDM block on*/ + + /* 2. set CCK test mode off, set to CCK normal mode*/ + PHY_SetBBReg(pAdapter, rCCK0_System, bCCKBBMode, 0); + + /* 3. turn on scramble setting*/ + PHY_SetBBReg(pAdapter, rCCK0_System, bCCKScramble, 1); + + if (!IS_HARDWARE_TYPE_JAGUAR(pAdapter) && !IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) { + PHY_SetBBReg(pAdapter, 0xa14, 0x300, 0x3); /* 0xa15[1:0] = 2b'11*/ + PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, 0x10000, 0x1); /* 0xc08[16] = 1*/ + } + + /* 4. Turn On Continue Tx and turn off the other test modes.*/ + if (IS_HARDWARE_TYPE_JAGUAR(pAdapter) || IS_HARDWARE_TYPE_JAGUAR2(pAdapter)) + PHY_SetBBReg(pAdapter, 0x914, BIT18|BIT17|BIT16, OFDM_ContinuousTx); + else + PHY_SetBBReg(pAdapter, rOFDM1_LSTF, BIT30|BIT29|BIT28, OFDM_ContinuousTx); + + PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); + PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); + + pMptCtx->bCckContTx = FALSE; + pMptCtx->bOfdmContTx = TRUE; +} /* mpt_StartOfdmContTx */ + + +void mpt_ProSetPMacTx(PADAPTER Adapter) +{ + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo; + u32 u4bTmp; + + DbgPrint("SGI %d bSPreamble %d bSTBC %d bLDPC %d NDP_sound %d\n", PMacTxInfo.bSGI, PMacTxInfo.bSPreamble, PMacTxInfo.bSTBC, PMacTxInfo.bLDPC, PMacTxInfo.NDP_sound); + DbgPrint("TXSC %d BandWidth %d PacketPeriod %d PacketCount %d PacketLength %d PacketPattern %d\n", PMacTxInfo.TX_SC, PMacTxInfo.BandWidth, PMacTxInfo.PacketPeriod, PMacTxInfo.PacketCount, PMacTxInfo.PacketLength, PMacTxInfo.PacketPattern); +#if 0 + PRINT_DATA("LSIG ", PMacTxInfo.LSIG, 3); + PRINT_DATA("HT_SIG", PMacTxInfo.HT_SIG, 6); + PRINT_DATA("VHT_SIG_A", PMacTxInfo.VHT_SIG_A, 6); + PRINT_DATA("VHT_SIG_B", PMacTxInfo.VHT_SIG_B, 4); + DbgPrint("VHT_SIG_B_CRC %x\n", PMacTxInfo.VHT_SIG_B_CRC); + PRINT_DATA("VHT_Delimiter", PMacTxInfo.VHT_Delimiter, 4); + + PRINT_DATA("Src Address", Adapter->mac_addr, 6); + PRINT_DATA("Dest Address", PMacTxInfo.MacAddress, 6); +#endif + + if (PMacTxInfo.bEnPMacTx == FALSE) { + if (PMacTxInfo.Mode == CONTINUOUS_TX) { + PHY_SetBBReg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/ + if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) + mpt_StopCckContTx(Adapter); + else + mpt_StopOfdmContTx(Adapter); + } else if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) { + u4bTmp = PHY_QueryBBReg(Adapter, 0xf50, bMaskLWord); + PHY_SetBBReg(Adapter, 0xb1c, bMaskLWord, u4bTmp+50); + PHY_SetBBReg(Adapter, 0xb04, 0xf, 2); /*TX Stop*/ + } else + PHY_SetBBReg(Adapter, 0xb04, 0xf, 2); /* TX Stop*/ + + if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) { + /* Stop HW TX -> Stop Continuous TX -> Stop RF Setting*/ + if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) + mpt_StopCckContTx(Adapter); + else + mpt_StopOfdmContTx(Adapter); + + mpt_SetSingleTone_8814A(Adapter, FALSE, TRUE); + } + + return; + } + + if (PMacTxInfo.Mode == CONTINUOUS_TX) { + PMacTxInfo.PacketCount = 1; + + if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) + mpt_StartCckContTx(Adapter); + else + mpt_StartOfdmContTx(Adapter); + } else if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) { + /* Continuous TX -> HW TX -> RF Setting */ + PMacTxInfo.PacketCount = 1; + + if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) + mpt_StartCckContTx(Adapter); + else + mpt_StartOfdmContTx(Adapter); + } else if (PMacTxInfo.Mode == PACKETS_TX) { + if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE) && PMacTxInfo.PacketCount == 0) + PMacTxInfo.PacketCount = 0xffff; + } + + if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) { + /* 0xb1c[0:15] TX packet count 0xb1C[31:16] SFD*/ + u4bTmp = PMacTxInfo.PacketCount|(PMacTxInfo.SFD << 16); + PHY_SetBBReg(Adapter, 0xb1c, bMaskDWord, u4bTmp); + /* 0xb40 7:0 SIGNAL 15:8 SERVICE 31:16 LENGTH*/ + u4bTmp = PMacTxInfo.SignalField|(PMacTxInfo.ServiceField << 8)|(PMacTxInfo.LENGTH << 16); + PHY_SetBBReg(Adapter, 0xb40, bMaskDWord, u4bTmp); + u4bTmp = PMacTxInfo.CRC16[0] | (PMacTxInfo.CRC16[1] << 8); + PHY_SetBBReg(Adapter, 0xb44, bMaskLWord, u4bTmp); + + if (PMacTxInfo.bSPreamble) + PHY_SetBBReg(Adapter, 0xb0c, BIT27, 0); + else + PHY_SetBBReg(Adapter, 0xb0c, BIT27, 1); + } else { + PHY_SetBBReg(Adapter, 0xb18, 0xfffff, PMacTxInfo.PacketCount); + + u4bTmp = PMacTxInfo.LSIG[0]|((PMacTxInfo.LSIG[1]) << 8)|((PMacTxInfo.LSIG[2]) << 16)|((PMacTxInfo.PacketPattern) << 24); + PHY_SetBBReg(Adapter, 0xb08, bMaskDWord, u4bTmp); /* Set 0xb08[23:0] = LSIG, 0xb08[31:24] = Data init octet*/ + + if (PMacTxInfo.PacketPattern == 0x12) + u4bTmp = 0x3000000; + else + u4bTmp = 0; + } + + if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE)) { + u4bTmp |= PMacTxInfo.HT_SIG[0]|((PMacTxInfo.HT_SIG[1]) << 8)|((PMacTxInfo.HT_SIG[2]) << 16); + PHY_SetBBReg(Adapter, 0xb0c, bMaskDWord, u4bTmp); + u4bTmp = PMacTxInfo.HT_SIG[3]|((PMacTxInfo.HT_SIG[4]) << 8)|((PMacTxInfo.HT_SIG[5]) << 16); + PHY_SetBBReg(Adapter, 0xb10, 0xffffff, u4bTmp); + } else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) { + u4bTmp |= PMacTxInfo.VHT_SIG_A[0]|((PMacTxInfo.VHT_SIG_A[1]) << 8)|((PMacTxInfo.VHT_SIG_A[2]) << 16); + PHY_SetBBReg(Adapter, 0xb0c, bMaskDWord, u4bTmp); + u4bTmp = PMacTxInfo.VHT_SIG_A[3]|((PMacTxInfo.VHT_SIG_A[4]) << 8)|((PMacTxInfo.VHT_SIG_A[5]) << 16); + PHY_SetBBReg(Adapter, 0xb10, 0xffffff, u4bTmp); + + _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_SIG_B, 4); + PHY_SetBBReg(Adapter, 0xb14, bMaskDWord, u4bTmp); + } + + if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) { + u4bTmp = (PMacTxInfo.VHT_SIG_B_CRC << 24)|PMacTxInfo.PacketPeriod; /* for TX interval */ + PHY_SetBBReg(Adapter, 0xb20, bMaskDWord, u4bTmp); + + _rtw_memcpy(&u4bTmp, PMacTxInfo.VHT_Delimiter, 4); + PHY_SetBBReg(Adapter, 0xb24, bMaskDWord, u4bTmp); + + /* 0xb28 - 0xb34 24 byte Probe Request MAC Header*/ + /*& Duration & Frame control*/ + PHY_SetBBReg(Adapter, 0xb28, bMaskDWord, 0x00000040); + + /* Address1 [0:3]*/ + u4bTmp = PMacTxInfo.MacAddress[0]|(PMacTxInfo.MacAddress[1] << 8)|(PMacTxInfo.MacAddress[2] << 16)|(PMacTxInfo.MacAddress[3] << 24); + PHY_SetBBReg(Adapter, 0xb2C, bMaskDWord, u4bTmp); + + /* Address3 [3:0]*/ + PHY_SetBBReg(Adapter, 0xb38, bMaskDWord, u4bTmp); + + /* Address2[0:1] & Address1 [5:4]*/ + u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8)|(Adapter->mac_addr[0] << 16)|(Adapter->mac_addr[1] << 24); + PHY_SetBBReg(Adapter, 0xb30, bMaskDWord, u4bTmp); + + /* Address2 [5:2]*/ + u4bTmp = Adapter->mac_addr[2]|(Adapter->mac_addr[3] << 8)|(Adapter->mac_addr[4] << 16)|(Adapter->mac_addr[5] << 24); + PHY_SetBBReg(Adapter, 0xb34, bMaskDWord, u4bTmp); + + /* Sequence Control & Address3 [5:4]*/ + /*u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8) ;*/ + /*PHY_SetBBReg(Adapter, 0xb38, bMaskDWord, u4bTmp);*/ + } else { + PHY_SetBBReg(Adapter, 0xb20, bMaskDWord, PMacTxInfo.PacketPeriod); /* for TX interval*/ + /* & Duration & Frame control */ + PHY_SetBBReg(Adapter, 0xb24, bMaskDWord, 0x00000040); + + /* 0xb24 - 0xb38 24 byte Probe Request MAC Header*/ + /* Address1 [0:3]*/ + u4bTmp = PMacTxInfo.MacAddress[0]|(PMacTxInfo.MacAddress[1] << 8)|(PMacTxInfo.MacAddress[2] << 16)|(PMacTxInfo.MacAddress[3] << 24); + PHY_SetBBReg(Adapter, 0xb28, bMaskDWord, u4bTmp); + + /* Address3 [3:0]*/ + PHY_SetBBReg(Adapter, 0xb34, bMaskDWord, u4bTmp); + + /* Address2[0:1] & Address1 [5:4]*/ + u4bTmp = PMacTxInfo.MacAddress[4]|(PMacTxInfo.MacAddress[5] << 8)|(Adapter->mac_addr[0] << 16)|(Adapter->mac_addr[1] << 24); + PHY_SetBBReg(Adapter, 0xb2c, bMaskDWord, u4bTmp); + + /* Address2 [5:2] */ + u4bTmp = Adapter->mac_addr[2]|(Adapter->mac_addr[3] << 8)|(Adapter->mac_addr[4] << 16)|(Adapter->mac_addr[5] << 24); + PHY_SetBBReg(Adapter, 0xb30, bMaskDWord, u4bTmp); + + /* Sequence Control & Address3 [5:4]*/ + u4bTmp = PMacTxInfo.MacAddress[4] | (PMacTxInfo.MacAddress[5] << 8); + PHY_SetBBReg(Adapter, 0xb38, bMaskDWord, u4bTmp); + } + + PHY_SetBBReg(Adapter, 0xb48, bMaskByte3, PMacTxInfo.TX_RATE_HEX); + + /* 0xb4c 3:0 TXSC 5:4 BW 7:6 m_STBC 8 NDP_Sound*/ + u4bTmp = (PMacTxInfo.TX_SC)|((PMacTxInfo.BandWidth) << 4)|((PMacTxInfo.m_STBC - 1) << 6)|((PMacTxInfo.NDP_sound) << 8); + PHY_SetBBReg(Adapter, 0xb4c, 0x1ff, u4bTmp); + + if (IS_HARDWARE_TYPE_8814A(Adapter) || IS_HARDWARE_TYPE_8822B(Adapter)) { + u4Byte offset = 0xb44; + + if (IS_MPT_OFDM_RATE(PMacTxInfo.TX_RATE)) + PHY_SetBBReg(Adapter, offset, 0xc0000000, 0); + else if (IS_MPT_HT_RATE(PMacTxInfo.TX_RATE)) + PHY_SetBBReg(Adapter, offset, 0xc0000000, 1); + else if (IS_MPT_VHT_RATE(PMacTxInfo.TX_RATE)) + PHY_SetBBReg(Adapter, offset, 0xc0000000, 2); + } + + PHY_SetBBReg(Adapter, 0xb00, BIT8, 1); /* Turn on PMAC*/ +/* //PHY_SetBBReg(Adapter, 0xb04, 0xf, 2); //TX Stop*/ + if (IS_MPT_CCK_RATE(PMacTxInfo.TX_RATE)) { + PHY_SetBBReg(Adapter, 0xb04, 0xf, 8); /*TX CCK ON*/ + PHY_SetBBReg(Adapter, 0xA84, BIT31, 0); + } else + PHY_SetBBReg(Adapter, 0xb04, 0xf, 4); /* TX Ofdm ON */ + + if (PMacTxInfo.Mode == OFDM_Single_Tone_TX) + mpt_SetSingleTone_8814A(Adapter, TRUE, TRUE); + +} +#endif + +#endif /* CONFIG_MP_INCLUDE*/ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_phy.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_phy.c new file mode 100644 index 000000000..feb619edb --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/hal_phy.c @@ -0,0 +1,285 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _HAL_PHY_C_ + +#include + +//================================================================================ +// Constant. +//================================================================================ +// 2008/11/20 MH For Debug only, RF +static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG]; + +/** +* Function: PHY_CalculateBitShift +* +* OverView: Get shifted position of the BitMask +* +* Input: +* u4Byte BitMask, +* +* Output: none +* Return: u4Byte Return the shift bit bit position of the mask +*/ +u32 +PHY_CalculateBitShift( + u32 BitMask + ) +{ + u32 i; + + for(i=0; i<=31; i++) + { + if ( ((BitMask>>i) & 0x1 ) == 1) + break; + } + + return (i); +} + + +// +// ==> RF shadow Operation API Code Section!!! +// +/*----------------------------------------------------------------------------- + * Function: PHY_RFShadowRead + * PHY_RFShadowWrite + * PHY_RFShadowCompare + * PHY_RFShadowRecorver + * PHY_RFShadowCompareAll + * PHY_RFShadowRecorverAll + * PHY_RFShadowCompareFlagSet + * PHY_RFShadowRecorverFlagSet + * + * Overview: When we set RF register, we must write shadow at first. + * When we are running, we must compare shadow abd locate error addr. + * Decide to recorver or not. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 11/20/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +u32 +PHY_RFShadowRead( + IN PADAPTER Adapter, + IN u8 eRFPath, + IN u32 Offset) +{ + return RF_Shadow[eRFPath][Offset].Value; + +} /* PHY_RFShadowRead */ + + +VOID +PHY_RFShadowWrite( + IN PADAPTER Adapter, + IN u8 eRFPath, + IN u32 Offset, + IN u32 Data) +{ + RF_Shadow[eRFPath][Offset].Value = (Data & bRFRegOffsetMask); + RF_Shadow[eRFPath][Offset].Driver_Write = _TRUE; + +} /* PHY_RFShadowWrite */ + + +BOOLEAN +PHY_RFShadowCompare( + IN PADAPTER Adapter, + IN u8 eRFPath, + IN u32 Offset) +{ + u32 reg; + // Check if we need to check the register + if (RF_Shadow[eRFPath][Offset].Compare == _TRUE) + { + reg = rtw_hal_read_rfreg(Adapter, eRFPath, Offset, bRFRegOffsetMask); + // Compare shadow and real rf register for 20bits!! + if (RF_Shadow[eRFPath][Offset].Value != reg) + { + // Locate error position. + RF_Shadow[eRFPath][Offset].ErrorOrNot = _TRUE; + //RT_TRACE(COMP_INIT, DBG_LOUD, + //("PHY_RFShadowCompare RF-%d Addr%02lx Err = %05lx\n", + //eRFPath, Offset, reg)); + } + return RF_Shadow[eRFPath][Offset].ErrorOrNot ; + } + return _FALSE; +} /* PHY_RFShadowCompare */ + + +VOID +PHY_RFShadowRecorver( + IN PADAPTER Adapter, + IN u8 eRFPath, + IN u32 Offset) +{ + // Check if the address is error + if (RF_Shadow[eRFPath][Offset].ErrorOrNot == _TRUE) + { + // Check if we need to recorver the register. + if (RF_Shadow[eRFPath][Offset].Recorver == _TRUE) + { + rtw_hal_write_rfreg(Adapter, eRFPath, Offset, bRFRegOffsetMask, + RF_Shadow[eRFPath][Offset].Value); + //RT_TRACE(COMP_INIT, DBG_LOUD, + //("PHY_RFShadowRecorver RF-%d Addr%02lx=%05lx", + //eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value)); + } + } + +} /* PHY_RFShadowRecorver */ + + +VOID +PHY_RFShadowCompareAll( + IN PADAPTER Adapter) +{ + u8 eRFPath = 0 ; + u32 Offset = 0, maxReg= GET_RF6052_REAL_MAX_REG(Adapter); + + for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) + { + for (Offset = 0; Offset < maxReg; Offset++) + { + PHY_RFShadowCompare(Adapter, eRFPath, Offset); + } + } + +} /* PHY_RFShadowCompareAll */ + + +VOID +PHY_RFShadowRecorverAll( + IN PADAPTER Adapter) +{ + u8 eRFPath =0; + u32 Offset = 0, maxReg= GET_RF6052_REAL_MAX_REG(Adapter); + + for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) + { + for (Offset = 0; Offset < maxReg; Offset++) + { + PHY_RFShadowRecorver(Adapter, eRFPath, Offset); + } + } + +} /* PHY_RFShadowRecorverAll */ + + +VOID +PHY_RFShadowCompareFlagSet( + IN PADAPTER Adapter, + IN u8 eRFPath, + IN u32 Offset, + IN u8 Type) +{ + // Set True or False!!! + RF_Shadow[eRFPath][Offset].Compare = Type; + +} /* PHY_RFShadowCompareFlagSet */ + + +VOID +PHY_RFShadowRecorverFlagSet( + IN PADAPTER Adapter, + IN u8 eRFPath, + IN u32 Offset, + IN u8 Type) +{ + // Set True or False!!! + RF_Shadow[eRFPath][Offset].Recorver= Type; + +} /* PHY_RFShadowRecorverFlagSet */ + + +VOID +PHY_RFShadowCompareFlagSetAll( + IN PADAPTER Adapter) +{ + u8 eRFPath = 0; + u32 Offset = 0, maxReg= GET_RF6052_REAL_MAX_REG(Adapter); + + for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) + { + for (Offset = 0; Offset < maxReg; Offset++) + { + // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! + if (Offset != 0x26 && Offset != 0x27) + PHY_RFShadowCompareFlagSet(Adapter, eRFPath, Offset, _FALSE); + else + PHY_RFShadowCompareFlagSet(Adapter, eRFPath, Offset, _TRUE); + } + } + +} /* PHY_RFShadowCompareFlagSetAll */ + + +VOID +PHY_RFShadowRecorverFlagSetAll( + IN PADAPTER Adapter) +{ + u8 eRFPath = 0; + u32 Offset = 0, maxReg= GET_RF6052_REAL_MAX_REG(Adapter); + + for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) + { + for (Offset = 0; Offset < maxReg; Offset++) + { + // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! + if (Offset != 0x26 && Offset != 0x27) + PHY_RFShadowRecorverFlagSet(Adapter, eRFPath, Offset, _FALSE); + else + PHY_RFShadowRecorverFlagSet(Adapter, eRFPath, Offset, _TRUE); + } + } + +} /* PHY_RFShadowCompareFlagSetAll */ + +VOID +PHY_RFShadowRefresh( + IN PADAPTER Adapter) +{ + u8 eRFPath = 0; + u32 Offset = 0, maxReg= GET_RF6052_REAL_MAX_REG(Adapter); + + for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) + { + for (Offset = 0; Offset < maxReg; Offset++) + { + RF_Shadow[eRFPath][Offset].Value = 0; + RF_Shadow[eRFPath][Offset].Compare = _FALSE; + RF_Shadow[eRFPath][Offset].Recorver = _FALSE; + RF_Shadow[eRFPath][Offset].ErrorOrNot = _FALSE; + RF_Shadow[eRFPath][Offset].Driver_Write = _FALSE; + } + } + +} /* PHY_RFShadowRead */ + + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/led/hal_usb_led.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/led/hal_usb_led.c new file mode 100644 index 000000000..3b9a1cad8 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/led/hal_usb_led.c @@ -0,0 +1,5180 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include +#include + +// +// Description: +// Implementation of LED blinking behavior. +// It toggle off LED and schedule corresponding timer if necessary. +// +void +SwLedBlink( + PLED_USB pLed + ) +{ + _adapter *padapter = pLed->padapter; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u8 bStopBlinking = _FALSE; + + // Change LED according to BlinkingLedState specified. + if( pLed->BlinkingLedState == RTW_LED_ON ) + { + SwLedOn(padapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); + } + else + { + SwLedOff(padapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,( "Blinktimes (%d): turn off\n", pLed->BlinkTimes)); + } + + // Determine if we shall change LED state again. + pLed->BlinkTimes--; + switch(pLed->CurrLedState) + { + + case LED_BLINK_NORMAL: + if(pLed->BlinkTimes == 0) + { + bStopBlinking = _TRUE; + } + break; + + case LED_BLINK_StartToBlink: + if( check_fwstate(pmlmepriv, _FW_LINKED) && check_fwstate(pmlmepriv, WIFI_STATION_STATE) ) + { + bStopBlinking = _TRUE; + } + if( check_fwstate(pmlmepriv, _FW_LINKED) && + (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) ) + { + bStopBlinking = _TRUE; + } + else if(pLed->BlinkTimes == 0) + { + bStopBlinking = _TRUE; + } + break; + + case LED_BLINK_WPS: + if( pLed->BlinkTimes == 0 ) + { + bStopBlinking = _TRUE; + } + break; + + + default: + bStopBlinking = _TRUE; + break; + + } + + if(bStopBlinking) + { + if( adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on ) + { + SwLedOff(padapter, pLed); + } + else if( (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) && (pLed->bLedOn == _FALSE)) + { + SwLedOn(padapter, pLed); + } + else if( (check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE) && pLed->bLedOn == _TRUE) + { + SwLedOff(padapter, pLed); + } + + pLed->BlinkTimes = 0; + pLed->bLedBlinkInProgress = _FALSE; + } + else + { + // Assign LED state to toggle. + if( pLed->BlinkingLedState == RTW_LED_ON ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + + // Schedule a timer to toggle LED state. + switch( pLed->CurrLedState ) + { + case LED_BLINK_NORMAL: + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + break; + + case LED_BLINK_SLOWLY: + case LED_BLINK_StartToBlink: + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL); + break; + + case LED_BLINK_WPS: + { + if( pLed->BlinkingLedState == RTW_LED_ON ) + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LONG_INTERVAL); + else + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LONG_INTERVAL); + } + break; + + default: + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL); + break; + } + } +} + +void +SwLedBlink1( + PLED_USB pLed + ) +{ + _adapter *padapter = pLed->padapter; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + struct led_priv *ledpriv = &(padapter->ledpriv); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + PLED_USB pLed1 = &(ledpriv->SwLed1); + u8 bStopBlinking = _FALSE; + + u32 uLedBlinkNoLinkInterval = LED_BLINK_NO_LINK_INTERVAL_ALPHA; //add by ylb 20121012 for customer led for alpha + if(pHalData->CustomerID == RT_CID_819x_ALPHA_Dlink) + uLedBlinkNoLinkInterval= LED_BLINK_NO_LINK_INTERVAL_ALPHA_500MS; + + if(pHalData->CustomerID == RT_CID_819x_CAMEO) + pLed = &(ledpriv->SwLed1); + + // Change LED according to BlinkingLedState specified. + if( pLed->BlinkingLedState == RTW_LED_ON ) + { + SwLedOn(padapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,( "Blinktimes (%d): turn on\n", pLed->BlinkTimes)); + } + else + { + SwLedOff(padapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); + } + + + if(pHalData->CustomerID == RT_CID_DEFAULT) + { + if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) + { + if(!pLed1->bSWLedCtrl) + { + SwLedOn(padapter, pLed1); + pLed1->bSWLedCtrl = _TRUE; + } + else if(!pLed1->bLedOn) + SwLedOn(padapter, pLed1); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (): turn on pLed1\n")); + } + else + { + if(!pLed1->bSWLedCtrl) + { + SwLedOff(padapter, pLed1); + pLed1->bSWLedCtrl = _TRUE; + } + else if(pLed1->bLedOn) + SwLedOff(padapter, pLed1); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (): turn off pLed1\n")); + } + } + + switch(pLed->CurrLedState) + { + case LED_BLINK_SLOWLY: + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), uLedBlinkNoLinkInterval);//change by ylb 20121012 for customer led for alpha + break; + + case LED_BLINK_NORMAL: + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA); + break; + + case LED_BLINK_SCAN: + pLed->BlinkTimes--; + if( pLed->BlinkTimes == 0 ) + { + bStopBlinking = _TRUE; + } + + if(bStopBlinking) + { + if( adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on ) + { + SwLedOff(padapter, pLed); + } + else if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) + { + pLed->bLedLinkBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_NORMAL; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); + + } + else if(check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE) + { + pLed->bLedNoLinkBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_SLOWLY; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), uLedBlinkNoLinkInterval); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); + } + pLed->bLedScanBlinkInProgress = _FALSE; + } + else + { + if( adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on ) + { + SwLedOff(padapter, pLed); + } + else + { + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); + } + } + break; + + case LED_BLINK_TXRX: + pLed->BlinkTimes--; + if( pLed->BlinkTimes == 0 ) + { + bStopBlinking = _TRUE; + } + if(bStopBlinking) + { + if( adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on ) + { + SwLedOff(padapter, pLed); + } + else if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) + { + pLed->bLedLinkBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_NORMAL; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); + } + else if(check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE) + { + pLed->bLedNoLinkBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_SLOWLY; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), uLedBlinkNoLinkInterval); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); + } + pLed->BlinkTimes = 0; + pLed->bLedBlinkInProgress = _FALSE; + } + else + { + if( adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on ) + { + SwLedOff(padapter, pLed); + } + else + { + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + } + break; + + case LED_BLINK_WPS: + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); + break; + + case LED_BLINK_WPS_STOP: //WPS success + if(pLed->BlinkingLedState == RTW_LED_ON) + { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA); + bStopBlinking = _FALSE; + } + else + { + bStopBlinking = _TRUE; + } + + if(bStopBlinking) + { + if( adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on ) + { + SwLedOff(padapter, pLed); + } + else + { + pLed->bLedLinkBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_NORMAL; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); + } + pLed->bLedWPSBlinkInProgress = _FALSE; + } + break; + + default: + break; + } + +} + +void +SwLedBlink2( + PLED_USB pLed + ) +{ + _adapter *padapter = pLed->padapter; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u8 bStopBlinking = _FALSE; + + // Change LED according to BlinkingLedState specified. + if( pLed->BlinkingLedState == RTW_LED_ON) + { + SwLedOn(padapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); + } + else + { + SwLedOff(padapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); + } + + switch(pLed->CurrLedState) + { + case LED_BLINK_SCAN: + pLed->BlinkTimes--; + if( pLed->BlinkTimes == 0 ) + { + bStopBlinking = _TRUE; + } + + if(bStopBlinking) + { + if( adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on ) + { + SwLedOff(padapter, pLed); + } + else if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) + { + pLed->CurrLedState = RTW_LED_ON; + pLed->BlinkingLedState = RTW_LED_ON; + SwLedOn(padapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("stop scan blink CurrLedState %d\n", pLed->CurrLedState)); + + } + else if(check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE) + { + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + SwLedOff(padapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("stop scan blink CurrLedState %d\n", pLed->CurrLedState)); + } + pLed->bLedScanBlinkInProgress = _FALSE; + } + else + { + if( adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on ) + { + SwLedOff(padapter, pLed); + } + else + { + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); + } + } + break; + + case LED_BLINK_TXRX: + pLed->BlinkTimes--; + if( pLed->BlinkTimes == 0 ) + { + bStopBlinking = _TRUE; + } + if(bStopBlinking) + { + if( adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on ) + { + SwLedOff(padapter, pLed); + } + else if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) + { + pLed->CurrLedState = RTW_LED_ON; + pLed->BlinkingLedState = RTW_LED_ON; + SwLedOn(padapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("stop CurrLedState %d\n", pLed->CurrLedState)); + + } + else if(check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE) + { + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + SwLedOff(padapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("stop CurrLedState %d\n", pLed->CurrLedState)); + } + pLed->bLedBlinkInProgress = _FALSE; + } + else + { + if( adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on ) + { + SwLedOff(padapter, pLed); + } + else + { + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + } + break; + + default: + break; + } + +} + +void +SwLedBlink3( + PLED_USB pLed + ) +{ + _adapter *padapter = pLed->padapter; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u8 bStopBlinking = _FALSE; + + // Change LED according to BlinkingLedState specified. + if( pLed->BlinkingLedState == RTW_LED_ON ) + { + SwLedOn(padapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); + } + else + { + if(pLed->CurrLedState != LED_BLINK_WPS_STOP) + SwLedOff(padapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); + } + + switch(pLed->CurrLedState) + { + case LED_BLINK_SCAN: + pLed->BlinkTimes--; + if( pLed->BlinkTimes == 0 ) + { + bStopBlinking = _TRUE; + } + + if(bStopBlinking) + { + if( adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on ) + { + SwLedOff(padapter, pLed); + } + else if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) + { + pLed->CurrLedState = RTW_LED_ON; + pLed->BlinkingLedState = RTW_LED_ON; + if( !pLed->bLedOn ) + SwLedOn(padapter, pLed); + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); + } + else if(check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE) + { + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + if( pLed->bLedOn ) + SwLedOff(padapter, pLed); + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); + } + pLed->bLedScanBlinkInProgress = _FALSE; + } + else + { + if( adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on ) + { + SwLedOff(padapter, pLed); + } + else + { + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); + } + } + break; + + case LED_BLINK_TXRX: + pLed->BlinkTimes--; + if( pLed->BlinkTimes == 0 ) + { + bStopBlinking = _TRUE; + } + if(bStopBlinking) + { + if( adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on ) + { + SwLedOff(padapter, pLed); + } + else if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) + { + pLed->CurrLedState = RTW_LED_ON; + pLed->BlinkingLedState = RTW_LED_ON; + + if( !pLed->bLedOn ) + SwLedOn(padapter, pLed); + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); + } + else if(check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE) + { + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + + if( pLed->bLedOn ) + SwLedOff(padapter, pLed); + + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); + } + pLed->bLedBlinkInProgress = _FALSE; + } + else + { + if( adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on ) + { + SwLedOff(padapter, pLed); + } + else + { + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + } + break; + + case LED_BLINK_WPS: + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); + break; + + case LED_BLINK_WPS_STOP: //WPS success + if(pLed->BlinkingLedState == RTW_LED_ON) + { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA); + bStopBlinking = _FALSE; + } + else + { + bStopBlinking = _TRUE; + } + + if(bStopBlinking) + { + if( adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on ) + { + SwLedOff(padapter, pLed); + } + else + { + pLed->CurrLedState = RTW_LED_ON; + pLed->BlinkingLedState = RTW_LED_ON; + SwLedOn(padapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); + } + pLed->bLedWPSBlinkInProgress = _FALSE; + } + break; + + + default: + break; + } + +} + + +void +SwLedBlink4( + PLED_USB pLed + ) +{ + _adapter *padapter = pLed->padapter; + struct led_priv *ledpriv = &(padapter->ledpriv); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + PLED_USB pLed1 = &(ledpriv->SwLed1); + u8 bStopBlinking = _FALSE; + + // Change LED according to BlinkingLedState specified. + if( pLed->BlinkingLedState == RTW_LED_ON ) + { + SwLedOn(padapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); + } + else + { + SwLedOff(padapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); + } + + if(!pLed1->bLedWPSBlinkInProgress && pLed1->BlinkingLedState == LED_UNKNOWN) + { + pLed1->BlinkingLedState = RTW_LED_OFF; + pLed1->CurrLedState = RTW_LED_OFF; + SwLedOff(padapter, pLed1); + } + + switch(pLed->CurrLedState) + { + case LED_BLINK_SLOWLY: + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); + break; + + case LED_BLINK_StartToBlink: + if( pLed->bLedOn ) + { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL); + } + else + { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + } + break; + + case LED_BLINK_SCAN: + pLed->BlinkTimes--; + if( pLed->BlinkTimes == 0 ) + { + bStopBlinking = _FALSE; + } + + if(bStopBlinking) + { + if( adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) + { + SwLedOff(padapter, pLed); + } + else + { + pLed->bLedNoLinkBlinkInProgress = _FALSE; + pLed->CurrLedState = LED_BLINK_SLOWLY; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); + } + pLed->bLedScanBlinkInProgress = _FALSE; + } + else + { + if( adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) + { + SwLedOff(padapter, pLed); + } + else + { + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); + } + } + break; + + case LED_BLINK_TXRX: + pLed->BlinkTimes--; + if( pLed->BlinkTimes == 0 ) + { + bStopBlinking = _TRUE; + } + if(bStopBlinking) + { + if( adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) + { + SwLedOff(padapter, pLed); + } + else + { + pLed->bLedNoLinkBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_SLOWLY; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); + } + pLed->bLedBlinkInProgress = _FALSE; + } + else + { + if( adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) + { + SwLedOff(padapter, pLed); + } + else + { + + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + } + break; + + case LED_BLINK_WPS: + if( pLed->bLedOn ) + { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL); + } + else + { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + } + break; + + case LED_BLINK_WPS_STOP: //WPS authentication fail + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + break; + + case LED_BLINK_WPS_STOP_OVERLAP: //WPS session overlap + pLed->BlinkTimes--; + if(pLed->BlinkTimes == 0) + { + if(pLed->bLedOn) + { + pLed->BlinkTimes = 1; + } + else + { + bStopBlinking = _TRUE; + } + } + + if(bStopBlinking) + { + pLed->BlinkTimes = 10; + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA); + } + else + { + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + } + break; + + case LED_BLINK_ALWAYS_ON: + pLed->BlinkTimes--; + if( pLed->BlinkTimes == 0 ) + { + bStopBlinking = _TRUE; + } + if(bStopBlinking) + { + if( adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) + { + SwLedOff(padapter, pLed); + } + else + { + pLed->bLedNoLinkBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_SLOWLY; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); + } + pLed->bLedBlinkInProgress = _FALSE; + } + else + { + if( adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) + { + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("RFOff Status \n")); + SwLedOff(padapter, pLed); + } + else + { + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + } + break; + + default: + break; + } + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("SwLedBlink4 CurrLedState %d\n", pLed->CurrLedState)); + + +} + +void +SwLedBlink5( + PLED_USB pLed + ) +{ + _adapter *padapter = pLed->padapter; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u8 bStopBlinking = _FALSE; + + // Change LED according to BlinkingLedState specified. + if( pLed->BlinkingLedState == RTW_LED_ON ) + { + SwLedOn(padapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); + } + else + { + SwLedOff(padapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); + } + + switch(pLed->CurrLedState) + { + case LED_BLINK_SCAN: + pLed->BlinkTimes--; + if( pLed->BlinkTimes == 0 ) + { + bStopBlinking = _TRUE; + } + + if(bStopBlinking) + { + if( adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) + { + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + if(pLed->bLedOn) + SwLedOff(padapter, pLed); + } + else + { pLed->CurrLedState = RTW_LED_ON; + pLed->BlinkingLedState = RTW_LED_ON; + if(!pLed->bLedOn) + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + + pLed->bLedScanBlinkInProgress = _FALSE; + } + else + { + if( adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) + { + SwLedOff(padapter, pLed); + } + else + { + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); + } + } + break; + + + case LED_BLINK_TXRX: + pLed->BlinkTimes--; + if( pLed->BlinkTimes == 0 ) + { + bStopBlinking = _TRUE; + } + + if(bStopBlinking) + { + if( adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) + { + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + if(pLed->bLedOn) + SwLedOff(padapter, pLed); + } + else + { + pLed->CurrLedState = RTW_LED_ON; + pLed->BlinkingLedState = RTW_LED_ON; + if(!pLed->bLedOn) + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + + pLed->bLedBlinkInProgress = _FALSE; + } + else + { + if( adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) + { + SwLedOff(padapter, pLed); + } + else + { + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + } + break; + + default: + break; + } + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("SwLedBlink5 CurrLedState %d\n", pLed->CurrLedState)); + + +} + +void +SwLedBlink6( + PLED_USB pLed + ) +{ + _adapter *padapter = pLed->padapter; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u8 bStopBlinking = _FALSE; + + // Change LED according to BlinkingLedState specified. + if( pLed->BlinkingLedState == RTW_LED_ON ) + { + SwLedOn(padapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); + } + else + { + SwLedOff(padapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); + } + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("<==== blink6\n")); +} + +void +SwLedBlink7( + PLED_USB pLed + ) +{ + PADAPTER Adapter = pLed->padapter; + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + BOOLEAN bStopBlinking = _FALSE; + + // Change LED according to BlinkingLedState specified. + if( pLed->BlinkingLedState == RTW_LED_ON ) + { + SwLedOn(Adapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); + } + else + { + if(pLed->CurrLedState != LED_BLINK_WPS_STOP) + SwLedOff(Adapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); + } + + switch(pLed->CurrLedState) + { + case LED_BLINK_SCAN: + pLed->BlinkTimes--; + if( pLed->BlinkTimes == 0 ) + { + bStopBlinking = _TRUE; + } + + if(bStopBlinking) + { + if( adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on ) + { + SwLedOff(Adapter, pLed); + } + else if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) + { + pLed->CurrLedState = RTW_LED_ON; + pLed->BlinkingLedState = RTW_LED_ON; + if( !pLed->bLedOn ) + SwLedOn(Adapter, pLed); + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); + } + else if(check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE) + { + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + if( pLed->bLedOn ) + SwLedOff(Adapter, pLed); + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); + } + pLed->bLedScanBlinkInProgress = _FALSE; + } + else + { + if( adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on ) + { + SwLedOff(Adapter, pLed); + } + else + { + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_NETGEAR); + } + } + break; + + case LED_BLINK_WPS: + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_NETGEAR); + break; + + case LED_BLINK_WPS_STOP: //WPS success + if(pLed->BlinkingLedState == RTW_LED_ON) + { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_NETGEAR); + bStopBlinking = _FALSE; + } + else + { + bStopBlinking = _TRUE; + } + + if(bStopBlinking) + { + if( adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on ) + { + SwLedOff(Adapter, pLed); + } + else + { + pLed->CurrLedState = RTW_LED_ON; + pLed->BlinkingLedState = RTW_LED_ON; + SwLedOn(Adapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); + } + pLed->bLedWPSBlinkInProgress = _FALSE; + } + break; + + + default: + break; + } + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("<==== blink7\n")); + +} + +void +SwLedBlink8( + PLED_USB pLed + ) +{ + PADAPTER Adapter = pLed->padapter; + + // Change LED according to BlinkingLedState specified. + if( pLed->BlinkingLedState == RTW_LED_ON ) + { + SwLedOn(Adapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes blink8(%d): turn on\n", pLed->BlinkTimes)); + } + else + { + SwLedOff(Adapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes blink8(%d): turn off\n", pLed->BlinkTimes)); + } + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("<==== blink8\n")); + +} + +//page added for Belkin AC950. 20120813 +void +SwLedBlink9( + PLED_USB pLed + ) +{ + PADAPTER Adapter = pLed->padapter; + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + BOOLEAN bStopBlinking = _FALSE; + + // Change LED according to BlinkingLedState specified. + if( pLed->BlinkingLedState == RTW_LED_ON ) + { + SwLedOn(Adapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); + } + else + { + SwLedOff(Adapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); + } + //DBG_871X("%s, pLed->CurrLedState=%d, pLed->BlinkingLedState=%d \n", __FUNCTION__, pLed->CurrLedState, pLed->BlinkingLedState); + + + switch(pLed->CurrLedState) + { + case RTW_LED_ON: + SwLedOn(Adapter, pLed); + break; + + case RTW_LED_OFF: + SwLedOff(Adapter, pLed); + break; + + case LED_BLINK_SLOWLY: + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); + break; + + case LED_BLINK_StartToBlink: + if( pLed->bLedOn ) + { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL); + } + else + { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + } + break; + + case LED_BLINK_SCAN: + pLed->BlinkTimes--; + if( pLed->BlinkTimes == 0 ) + { + bStopBlinking = _TRUE; + } + + if(bStopBlinking) + { + if( adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on ) + { + SwLedOff(Adapter, pLed); + } + else if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + { + pLed->bLedLinkBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_SLOWLY; + + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); + } + else if(check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE) + { + pLed->bLedNoLinkBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_SLOWLY; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); + } + pLed->BlinkTimes = 0; + pLed->bLedBlinkInProgress = _FALSE; + } + else + { + if( adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) + { + SwLedOff(Adapter, pLed); + } + else + { + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); + } + } + break; + + case LED_BLINK_TXRX: + pLed->BlinkTimes--; + if( pLed->BlinkTimes == 0 ) + { + bStopBlinking = _TRUE; + } + if(bStopBlinking) + { + if( adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) + { + SwLedOff(Adapter, pLed); + } + else + { + pLed->CurrLedState = LED_BLINK_SLOWLY; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + pLed->bLedBlinkInProgress = _FALSE; + } + else + { + if( adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) + { + SwLedOff(Adapter, pLed); + } + else + { + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + } + break; + + case LED_BLINK_WPS: + if( pLed->bLedOn ) + { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL); + } + else + { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + } + break; + + case LED_BLINK_WPS_STOP: //WPS authentication fail + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + break; + + case LED_BLINK_WPS_STOP_OVERLAP: //WPS session overlap + pLed->BlinkTimes--; + pLed->BlinkCounter --; + if(pLed->BlinkCounter == 0) + { + pLed->BlinkingLedState = RTW_LED_OFF; + pLed->CurrLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + } + else + { + if(pLed->BlinkTimes == 0) + { + if(pLed->bLedOn) + { + pLed->BlinkTimes = 1; + } + else + { + bStopBlinking = _TRUE; + } + } + + if(bStopBlinking) + { + pLed->BlinkTimes = 10; + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA); + } + else + { + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + } + } + break; + + case LED_BLINK_ALWAYS_ON: + pLed->BlinkTimes--; + if( pLed->BlinkTimes == 0 ) + { + bStopBlinking = _TRUE; + } + if(bStopBlinking) + { + if( adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) + { + SwLedOff(Adapter, pLed); + } + else + { + if(IS_HARDWARE_TYPE_8812AU(Adapter)) + { + pLed->BlinkingLedState = RTW_LED_ON; + pLed->CurrLedState = LED_BLINK_ALWAYS_ON; + } + else + { + pLed->bLedNoLinkBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_SLOWLY; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + } + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); + } + pLed->bLedBlinkInProgress = _FALSE; + } + else + { + if( adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) + { + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("RFOff Status \n")); + SwLedOff(Adapter, pLed); + } + else + { + if(IS_HARDWARE_TYPE_8812AU(Adapter)) + { + pLed->BlinkingLedState = RTW_LED_ON; + } + else + { + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + } + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + } + break; + + case LED_BLINK_LINK_IN_PROCESS: + if( pLed->bLedOn ) + { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ON_BELKIN); + } + else + { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_OFF_BELKIN); + } + break; + + case LED_BLINK_AUTH_ERROR: + pLed->BlinkTimes--; + if( pLed->BlinkTimes == 0 ) + { + bStopBlinking = _TRUE; + } + if(bStopBlinking == _FALSE) + { + if( pLed->bLedOn ) + { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_ERROR_INTERVAL_BELKIN); + } + else + { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_ERROR_INTERVAL_BELKIN); + } + } + else + { + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_ERROR_INTERVAL_BELKIN); + } + break; + + default: + break; + } + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("SwLedBlink9 CurrLedState %d\n", pLed->CurrLedState)); +} + +//page added for Netgear A6200V2. 20120827 +void +SwLedBlink10( + PLED_USB pLed + ) +{ + PADAPTER Adapter = pLed->padapter; + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + BOOLEAN bStopBlinking = _FALSE; + + // Change LED according to BlinkingLedState specified. + if( pLed->BlinkingLedState == RTW_LED_ON ) + { + SwLedOn(Adapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); + } + else + { + SwLedOff(Adapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); + } + + + switch(pLed->CurrLedState) + { + case RTW_LED_ON: + SwLedOn(Adapter, pLed); + break; + + case RTW_LED_OFF: + SwLedOff(Adapter, pLed); + break; + + case LED_BLINK_SLOWLY: + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); + break; + + case LED_BLINK_StartToBlink: + if( pLed->bLedOn ) + { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL); + } + else + { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + } + break; + + case LED_BLINK_SCAN: + pLed->BlinkTimes--; + if( pLed->BlinkTimes == 0 ) + { + bStopBlinking = _TRUE; + } + + if(bStopBlinking) + { + if( adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on ) + { + SwLedOff(Adapter, pLed); + } + else if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) + { + pLed->bLedNoLinkBlinkInProgress = _FALSE; + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); + } + pLed->BlinkTimes = 0; + pLed->bLedBlinkInProgress = _FALSE; + } + else + { + if( adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) + { + SwLedOff(Adapter, pLed); + } + else + { + if( pLed->bLedOn ) + { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_NETGEAR); + } + else + { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_SLOWLY_INTERVAL_NETGEAR+LED_BLINK_LINK_INTERVAL_NETGEAR); + } + } + } + break; + + case LED_BLINK_WPS: + if( pLed->bLedOn ) + { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_NETGEAR); + } + else + { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL+LED_BLINK_LINK_INTERVAL_NETGEAR); + } + break; + + case LED_BLINK_WPS_STOP: //WPS authentication fail + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + break; + + case LED_BLINK_WPS_STOP_OVERLAP: //WPS session overlap + pLed->BlinkTimes--; + pLed->BlinkCounter --; + if(pLed->BlinkCounter == 0) + { + pLed->BlinkingLedState = RTW_LED_OFF; + pLed->CurrLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + } + else + { + if(pLed->BlinkTimes == 0) + { + if(pLed->bLedOn) + { + pLed->BlinkTimes = 1; + } + else + { + bStopBlinking = _TRUE; + } + } + + if(bStopBlinking) + { + pLed->BlinkTimes = 10; + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA); + } + else + { + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + } + } + break; + + case LED_BLINK_ALWAYS_ON: + pLed->BlinkTimes--; + if( pLed->BlinkTimes == 0 ) + { + bStopBlinking = _TRUE; + } + if(bStopBlinking) + { + if( adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) + { + SwLedOff(Adapter, pLed); + } + else + { + if(IS_HARDWARE_TYPE_8812AU(Adapter)) + { + pLed->BlinkingLedState = RTW_LED_ON; + pLed->CurrLedState = LED_BLINK_ALWAYS_ON; + } + else + { + pLed->bLedNoLinkBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_SLOWLY; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + } + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); + } + pLed->bLedBlinkInProgress = _FALSE; + } + else + { + if( adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) + { + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("RFOff Status \n")); + SwLedOff(Adapter, pLed); + } + else + { + if(IS_HARDWARE_TYPE_8812AU(Adapter)) + { + pLed->BlinkingLedState = RTW_LED_ON; + } + else + { + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + } + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + } + break; + + case LED_BLINK_LINK_IN_PROCESS: + if( pLed->bLedOn ) + { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ON_BELKIN); + } + else + { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_OFF_BELKIN); + } + break; + + case LED_BLINK_AUTH_ERROR: + pLed->BlinkTimes--; + if( pLed->BlinkTimes == 0 ) + { + bStopBlinking = _TRUE; + } + if(bStopBlinking == _FALSE) + { + if( pLed->bLedOn ) + { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_ERROR_INTERVAL_BELKIN); + } + else + { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_ERROR_INTERVAL_BELKIN); + } + } + else + { + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_ERROR_INTERVAL_BELKIN); + } + break; + + default: + break; + } + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("SwLedBlink10 CurrLedState %d\n", pLed->CurrLedState)); + +} + +void +SwLedBlink11( + PLED_USB pLed + ) +{ + PADAPTER Adapter = pLed->padapter; + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + BOOLEAN bStopBlinking = _FALSE; + + // Change LED according to BlinkingLedState specified. + if( pLed->BlinkingLedState == RTW_LED_ON ) + { + SwLedOn(Adapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); + } + else + { + SwLedOff(Adapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); + } + + switch(pLed->CurrLedState) + { + case LED_BLINK_TXRX: + if( adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) + { + SwLedOff(Adapter, pLed); + } + else + { + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); + } + + break; + + case LED_BLINK_WPS: + if(pLed->BlinkTimes == 5) + { + SwLedOn(Adapter, pLed); + _set_timer(&(pLed->BlinkTimer), LED_CM11_LINK_ON_INTERVEL); + } + else + { + if( pLed->bLedOn ) + { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_CM11_BLINK_INTERVAL); + } + else + { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_CM11_BLINK_INTERVAL); + } + } + pLed->BlinkTimes--; + if( pLed->BlinkTimes == 0 ) + { + bStopBlinking = _TRUE; + } + if(bStopBlinking == _TRUE) + pLed->BlinkTimes = 5; + break; + + case LED_BLINK_WPS_STOP: //WPS authentication fail + if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) + { + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); + } + else + { + pLed->CurrLedState = RTW_LED_ON; + pLed->BlinkingLedState = RTW_LED_ON; + SwLedOn(Adapter, pLed); + _set_timer(&(pLed->BlinkTimer), 0); + } + break; + + default: + break; + } + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("SwLedBlink5 CurrLedState %d\n", pLed->CurrLedState)); +} + +void +SwLedBlink12( + PLED_USB pLed + ) +{ + PADAPTER Adapter = pLed->padapter; + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + BOOLEAN bStopBlinking = _FALSE; + + // Change LED according to BlinkingLedState specified. + if( pLed->BlinkingLedState == RTW_LED_ON ) + { + SwLedOn(Adapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%ld): turn on\n", pLed->BlinkTimes)); + } + else + { + SwLedOff(Adapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%ld): turn off\n", pLed->BlinkTimes)); + } + + switch(pLed->CurrLedState) + { + case LED_BLINK_SLOWLY: + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); + break; + + case LED_BLINK_TXRX: + pLed->BlinkTimes--; + if( pLed->BlinkTimes == 0 ) + { + bStopBlinking = _TRUE; + } + + if(bStopBlinking) + { + if( adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) + { + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + if(pLed->bLedOn) + SwLedOff(Adapter, pLed); + } + else + { + pLed->bLedNoLinkBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_SLOWLY; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); + } + + pLed->bLedBlinkInProgress = _FALSE; + } + else + { + if( adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) + { + SwLedOff(Adapter, pLed); + } + else + { + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + } + break; + + default: + break; + } + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("SwLedBlink8 CurrLedState %d\n", pLed->CurrLedState)); + + +} + +VOID +SwLedBlink13( + IN PLED_USB pLed + ) +{ + PADAPTER Adapter = pLed->padapter; + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + BOOLEAN bStopBlinking = _FALSE; + static u8 LinkBlinkCnt=0; + + // Change LED according to BlinkingLedState specified. + if( pLed->BlinkingLedState == RTW_LED_ON ) + { + SwLedOn(Adapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); + } + else + { + if(pLed->CurrLedState != LED_BLINK_WPS_STOP) + SwLedOff(Adapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); + } + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("!!! SwLedBlink13 CurrLedState %d, bLedWPSBlinkInProgress %d, bLedBlinkInProgress %d\n", pLed->CurrLedState,pLed->bLedWPSBlinkInProgress,pLed->bLedBlinkInProgress)); + switch(pLed->CurrLedState) + { + case LED_BLINK_LINK_IN_PROCESS: + if(!pLed->bLedWPSBlinkInProgress) + LinkBlinkCnt++; + + if(LinkBlinkCnt>15) + { + LinkBlinkCnt=0; + pLed->bLedBlinkInProgress = _FALSE; + break; + } + if( pLed->bLedOn ) + { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), 500); + } + else + { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), 500); + } + + break; + + case LED_BLINK_WPS: + if( pLed->bLedOn ) + { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_WPS_BLINK_ON_INTERVAL_NETGEAR); + } + else + { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_WPS_BLINK_OFF_INTERVAL_NETGEAR); + } + + break; + + case LED_BLINK_WPS_STOP: //WPS success + SwLedOff(Adapter, pLed); + pLed->bLedWPSBlinkInProgress = _FALSE; + break; + + default: + LinkBlinkCnt=0; + break; + } + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("<==== blink13\n")); + +} + +VOID +SwLedBlink14( + IN PLED_USB pLed + ) +{ + PADAPTER Adapter = pLed->padapter; + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + BOOLEAN bStopBlinking = _FALSE; + static u8 LinkBlinkCnt=0; + + // Change LED according to BlinkingLedState specified. + if( pLed->BlinkingLedState == RTW_LED_ON ) + { + SwLedOn(Adapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); + } + else + { + if(pLed->CurrLedState != LED_BLINK_WPS_STOP) + SwLedOff(Adapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); + } + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("!!! SwLedBlink14 CurrLedState %d, bLedWPSBlinkInProgress %d, bLedBlinkInProgress %d\n", pLed->CurrLedState,pLed->bLedWPSBlinkInProgress,pLed->bLedBlinkInProgress)); + switch(pLed->CurrLedState) + { + case LED_BLINK_TXRX: + pLed->BlinkTimes--; + if( pLed->BlinkTimes == 0 ) + { + bStopBlinking = _TRUE; + } + if(bStopBlinking) + { + if( adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) + { + SwLedOff(Adapter, pLed); + } + else + { + SwLedOn(Adapter, pLed); + } + pLed->bLedBlinkInProgress = _FALSE; + } + else + { + if( adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) + { + SwLedOff(Adapter, pLed); + } + else + { + if( pLed->bLedOn ) + { + pLed->BlinkingLedState = RTW_LED_OFF; + if (IS_HARDWARE_TYPE_8812AU(Adapter)) + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA); + else + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + else + { + pLed->BlinkingLedState = RTW_LED_ON; + if (IS_HARDWARE_TYPE_8812AU(Adapter)) + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + else + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + } + } + + break; + + default: + LinkBlinkCnt=0; + break; + } + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("<==== blink14\n")); +} + +VOID +SwLedBlink15( + IN PLED_USB pLed + ) +{ + PADAPTER Adapter = pLed->padapter; + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + BOOLEAN bStopBlinking = _FALSE; + static u8 LinkBlinkCnt=0; + // Change LED according to BlinkingLedState specified. + + if( pLed->BlinkingLedState == RTW_LED_ON ) + { + SwLedOn(Adapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); + } + else + { + if(pLed->CurrLedState != LED_BLINK_WPS_STOP) + SwLedOff(Adapter, pLed); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); + } + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("!!! SwLedBlink15 CurrLedState %d, bLedWPSBlinkInProgress %d, bLedBlinkInProgress %d\n", pLed->CurrLedState,pLed->bLedWPSBlinkInProgress,pLed->bLedBlinkInProgress)); + switch(pLed->CurrLedState) + { + case LED_BLINK_WPS: + if( pLed->bLedOn ) + { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_WPS_BLINK_ON_INTERVAL_DLINK); + } + else + { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_WPS_BLINK_OFF_INTERVAL_DLINK); + } + break; + + case LED_BLINK_WPS_STOP: //WPS success + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("blink15, LED_BLINK_WPS_STOP BlinkingLedState %d\n",pLed->BlinkingLedState)); + + if(pLed->BlinkingLedState == RTW_LED_OFF) + { + pLed->bLedWPSBlinkInProgress = _FALSE; + return; + } + + pLed->CurrLedState = LED_BLINK_WPS_STOP; + pLed->BlinkingLedState = RTW_LED_OFF; + + _set_timer(&(pLed->BlinkTimer), LED_WPS_BLINK_LINKED_ON_INTERVAL_DLINK); + break; + + case LED_BLINK_NO_LINK: + { + static BOOLEAN bLedOn=_TRUE; + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("blink15, LED_NO_LINK_BLINK bLedOn %d\n",bLedOn)); + if(bLedOn) + { + bLedOn=_FALSE; + pLed->BlinkingLedState = RTW_LED_OFF; + } + else + { + bLedOn=_TRUE; + pLed->BlinkingLedState = RTW_LED_ON; + } + pLed->bLedBlinkInProgress = _TRUE; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL); + } + break; + + case LED_BLINK_LINK_IDEL: + { + static BOOLEAN bLedOn=_TRUE; + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("blink15, LED_BLINK_LINK_IDEL bLedOn %d\n",bLedOn)); + if(bLedOn) + { + bLedOn=_FALSE; + pLed->BlinkingLedState = RTW_LED_OFF; + } + else + { + bLedOn=_TRUE; + pLed->BlinkingLedState = RTW_LED_ON; + + } + pLed->bLedBlinkInProgress = _TRUE; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_IDEL_INTERVAL); + } + break; + + case LED_BLINK_SCAN: + { + static u8 BlinkTime=0; + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("blink15, LED_SCAN_BLINK bLedOn %d\n",BlinkTime)); + if(BlinkTime %2==0) + { + pLed->BlinkingLedState = RTW_LED_ON; + } + else + { + pLed->BlinkingLedState = RTW_LED_OFF; + } + BlinkTime ++; + + if(BlinkTime<24) + { + pLed->bLedBlinkInProgress = _TRUE; + + if(pLed->BlinkingLedState == RTW_LED_ON) + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_OFF_INTERVAL); + else + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_ON_INTERVAL); + } + else + { + //if(pLed->OLDLedState ==LED_NO_LINK_BLINK) + if(check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE) + { + pLed->CurrLedState = LED_BLINK_NO_LINK; + pLed->BlinkingLedState = RTW_LED_ON; + + _set_timer(&(pLed->BlinkTimer), 100); + } + BlinkTime =0; + } + } + break; + + case LED_BLINK_TXRX: + pLed->BlinkTimes--; + if( pLed->BlinkTimes == 0 ) + { + bStopBlinking = _TRUE; + } + if(bStopBlinking) + { + if( adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) + { + SwLedOff(Adapter, pLed); + } + else + { + SwLedOn(Adapter, pLed); + } + pLed->bLedBlinkInProgress = _FALSE; + } + else + { + if( adapter_to_pwrctl(Adapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(Adapter)->rfoff_reason > RF_CHANGE_BY_PS) + { + SwLedOff(Adapter, pLed); + } + else + { + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + } + break; + + default: + LinkBlinkCnt=0; + break; + } + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("<==== blink15\n")); +} + +// +// Description: +// Handler function of LED Blinking. +// We dispatch acture LED blink action according to LedStrategy. +// +void BlinkHandler(PLED_USB pLed) +{ + _adapter *padapter = pLed->padapter; + struct led_priv *ledpriv = &(padapter->ledpriv); + + //DBG_871X("%s (%s:%d)\n",__FUNCTION__, current->comm, current->pid); + + if (RTW_CANNOT_RUN(padapter) || (!rtw_is_hw_init_completed(padapter))) { + /*DBG_871X("%s bDriverStopped:%s, bSurpriseRemoved:%s\n" + , __func__ + , rtw_is_drv_stopped(padapter)?"True":"False" + , rtw_is_surprise_removed(padapter)?"True":"False" );*/ + return; + } + + switch(ledpriv->LedStrategy) + { + case SW_LED_MODE0: + SwLedBlink(pLed); + break; + + case SW_LED_MODE1: + SwLedBlink1(pLed); + break; + + case SW_LED_MODE2: + SwLedBlink2(pLed); + break; + + case SW_LED_MODE3: + SwLedBlink3(pLed); + break; + + case SW_LED_MODE4: + SwLedBlink4(pLed); + break; + + case SW_LED_MODE5: + SwLedBlink5(pLed); + break; + + case SW_LED_MODE6: + SwLedBlink6(pLed); + break; + + case SW_LED_MODE7: + SwLedBlink7(pLed); + break; + + case SW_LED_MODE8: + SwLedBlink8(pLed); + break; + + case SW_LED_MODE9: + SwLedBlink9(pLed); + break; + + case SW_LED_MODE10: + SwLedBlink10(pLed); + break; + + case SW_LED_MODE11: + SwLedBlink11(pLed); + break; + + case SW_LED_MODE12: + SwLedBlink12(pLed); + break; + + case SW_LED_MODE13: + SwLedBlink13(pLed); + break; + + case SW_LED_MODE14: + SwLedBlink14(pLed); + break; + + case SW_LED_MODE15: + SwLedBlink15(pLed); + break; + + default: + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("BlinkWorkItemCallback 0x%x \n", ledpriv->LedStrategy)); + //SwLedBlink(pLed); + break; + } +} + +// +// Description: +// Callback function of LED BlinkTimer, +// it just schedules to corresponding BlinkWorkItem/led_blink_hdl +// +void BlinkTimerCallback(void *data) +{ + PLED_USB pLed = (PLED_USB)data; + _adapter *padapter = pLed->padapter; + + //DBG_871X("%s\n", __FUNCTION__); + + if (RTW_CANNOT_RUN(padapter) || (!rtw_is_hw_init_completed(padapter))) { + /*DBG_871X("%s bDriverStopped:%s, bSurpriseRemoved:%s\n" + , __func__ + , rtw_is_drv_stopped(padapter)?"True":"False" + , rtw_is_surprise_removed(padapter)?"True":"False" );*/ + return; + } + + #ifdef CONFIG_LED_HANDLED_BY_CMD_THREAD + rtw_led_blink_cmd(padapter, (PVOID)pLed); + #else + _set_workitem(&(pLed->BlinkWorkItem)); + #endif +} + +// +// Description: +// Callback function of LED BlinkWorkItem. +// We dispatch acture LED blink action according to LedStrategy. +// +void BlinkWorkItemCallback(_workitem *work) +{ + PLED_USB pLed = container_of(work, LED_USB, BlinkWorkItem); + BlinkHandler(pLed); +} + +static void +SwLedControlMode0( + _adapter *padapter, + LED_CTL_MODE LedAction +) +{ + struct led_priv *ledpriv = &(padapter->ledpriv); + PLED_USB pLed = &(ledpriv->SwLed1); + + // Decide led state + switch(LedAction) + { + case LED_CTL_TX: + case LED_CTL_RX: + if( pLed->bLedBlinkInProgress == _FALSE ) + { + pLed->bLedBlinkInProgress = _TRUE; + + pLed->CurrLedState = LED_BLINK_NORMAL; + pLed->BlinkTimes = 2; + + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + } + break; + + case LED_CTL_START_TO_LINK: + if( pLed->bLedBlinkInProgress == _FALSE ) + { + pLed->bLedBlinkInProgress = _TRUE; + + pLed->CurrLedState = LED_BLINK_StartToBlink; + pLed->BlinkTimes = 24; + + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL); + } + else + { + pLed->CurrLedState = LED_BLINK_StartToBlink; + } + break; + + case LED_CTL_LINK: + pLed->CurrLedState = RTW_LED_ON; + if( pLed->bLedBlinkInProgress == _FALSE ) + { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), 0); + } + break; + + case LED_CTL_NO_LINK: + pLed->CurrLedState = RTW_LED_OFF; + if( pLed->bLedBlinkInProgress == _FALSE ) + { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), 0); + } + break; + + case LED_CTL_POWER_OFF: + pLed->CurrLedState = RTW_LED_OFF; + if(pLed->bLedBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + SwLedOff(padapter, pLed); + break; + + case LED_CTL_START_WPS: + if( pLed->bLedBlinkInProgress == _FALSE || pLed->CurrLedState == RTW_LED_ON) + { + pLed->bLedBlinkInProgress = _TRUE; + + pLed->CurrLedState = LED_BLINK_WPS; + pLed->BlinkTimes = 20; + + if( pLed->bLedOn ) + { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LONG_INTERVAL); + } + else + { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LONG_INTERVAL); + } + } + break; + + case LED_CTL_STOP_WPS: + if(pLed->bLedBlinkInProgress) + { + pLed->CurrLedState = RTW_LED_OFF; + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + break; + + + default: + break; + } + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led %d\n", pLed->CurrLedState)); + +} + + //ALPHA, added by chiyoko, 20090106 +static void +SwLedControlMode1( + _adapter *padapter, + LED_CTL_MODE LedAction +) +{ + struct led_priv *ledpriv = &(padapter->ledpriv); + PLED_USB pLed = &(ledpriv->SwLed0); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + + u32 uLedBlinkNoLinkInterval = LED_BLINK_NO_LINK_INTERVAL_ALPHA; //add by ylb 20121012 for customer led for alpha + if(pHalData->CustomerID == RT_CID_819x_ALPHA_Dlink) + uLedBlinkNoLinkInterval= LED_BLINK_NO_LINK_INTERVAL_ALPHA_500MS; + + if(pHalData->CustomerID == RT_CID_819x_CAMEO) + pLed = &(ledpriv->SwLed1); + + switch(LedAction) + { + case LED_CTL_POWER_ON: + case LED_CTL_START_TO_LINK: + case LED_CTL_NO_LINK: + if( pLed->bLedNoLinkBlinkInProgress == _FALSE ) + { + if(pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed)) + { + return; + } + if( pLed->bLedLinkBlinkInProgress == _TRUE ) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedLinkBlinkInProgress = _FALSE; + } + if(pLed->bLedBlinkInProgress ==_TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + + pLed->bLedNoLinkBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_SLOWLY; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), uLedBlinkNoLinkInterval);//change by ylb 20121012 for customer led for alpha + } + break; + + case LED_CTL_LINK: + if( pLed->bLedLinkBlinkInProgress == _FALSE ) + { + if(pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed)) + { + return; + } + if(pLed->bLedNoLinkBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedNoLinkBlinkInProgress = _FALSE; + } + if(pLed->bLedBlinkInProgress ==_TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + pLed->bLedLinkBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_NORMAL; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA); + } + break; + + case LED_CTL_SITE_SURVEY: + if((pmlmepriv->LinkDetectInfo.bBusyTraffic) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE)) + ; + else if(pLed->bLedScanBlinkInProgress ==_FALSE) + { + if(IS_LED_WPS_BLINKING(pLed)) + return; + + if(pLed->bLedNoLinkBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedNoLinkBlinkInProgress = _FALSE; + } + if( pLed->bLedLinkBlinkInProgress == _TRUE ) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedLinkBlinkInProgress = _FALSE; + } + if(pLed->bLedBlinkInProgress ==_TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + pLed->bLedScanBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_SCAN; + pLed->BlinkTimes = 24; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + + if (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && adapter_to_pwrctl(padapter)->rfoff_reason == RF_CHANGE_BY_IPS) + _set_timer(&(pLed->BlinkTimer), LED_INITIAL_INTERVAL); + else + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); + + } + break; + + case LED_CTL_TX: + case LED_CTL_RX: + if(pLed->bLedBlinkInProgress ==_FALSE) + { + if(pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed)) + { + return; + } + if(pLed->bLedNoLinkBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedNoLinkBlinkInProgress = _FALSE; + } + if( pLed->bLedLinkBlinkInProgress == _TRUE ) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedLinkBlinkInProgress = _FALSE; + } + pLed->bLedBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_TXRX; + pLed->BlinkTimes = 2; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + break; + + case LED_CTL_START_WPS: //wait until xinpin finish + case LED_CTL_START_WPS_BOTTON: + if(pLed->bLedWPSBlinkInProgress ==_FALSE) + { + if(pLed->bLedNoLinkBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedNoLinkBlinkInProgress = _FALSE; + } + if( pLed->bLedLinkBlinkInProgress == _TRUE ) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedLinkBlinkInProgress = _FALSE; + } + if(pLed->bLedBlinkInProgress ==_TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + if(pLed->bLedScanBlinkInProgress ==_TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedScanBlinkInProgress = _FALSE; + } + pLed->bLedWPSBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_WPS; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); + } + break; + + + case LED_CTL_STOP_WPS: + if(pLed->bLedNoLinkBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedNoLinkBlinkInProgress = _FALSE; + } + if( pLed->bLedLinkBlinkInProgress == _TRUE ) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedLinkBlinkInProgress = _FALSE; + } + if(pLed->bLedBlinkInProgress ==_TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + if(pLed->bLedScanBlinkInProgress ==_TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedScanBlinkInProgress = _FALSE; + } + if(pLed->bLedWPSBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + } + else + { + pLed->bLedWPSBlinkInProgress = _TRUE; + } + + pLed->CurrLedState = LED_BLINK_WPS_STOP; + if(pLed->bLedOn) + { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA); + } + else + { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), 0); + } + break; + + case LED_CTL_STOP_WPS_FAIL: + if(pLed->bLedWPSBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedWPSBlinkInProgress = _FALSE; + } + + pLed->bLedNoLinkBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_SLOWLY; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), uLedBlinkNoLinkInterval);//change by ylb 20121012 for customer led for alpha + break; + + case LED_CTL_POWER_OFF: + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + if( pLed->bLedNoLinkBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedNoLinkBlinkInProgress = _FALSE; + } + if( pLed->bLedLinkBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedLinkBlinkInProgress = _FALSE; + } + if( pLed->bLedBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + if( pLed->bLedWPSBlinkInProgress ) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedWPSBlinkInProgress = _FALSE; + } + if( pLed->bLedScanBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedScanBlinkInProgress = _FALSE; + } + + SwLedOff(padapter, pLed); + break; + + default: + break; + + } + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led %d\n", pLed->CurrLedState)); +} + + //Arcadyan/Sitecom , added by chiyoko, 20090216 +static void +SwLedControlMode2( + _adapter *padapter, + LED_CTL_MODE LedAction +) +{ + struct led_priv *ledpriv = &(padapter->ledpriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + PLED_USB pLed = &(ledpriv->SwLed0); + + switch(LedAction) + { + case LED_CTL_SITE_SURVEY: + if(pmlmepriv->LinkDetectInfo.bBusyTraffic) + ; + else if(pLed->bLedScanBlinkInProgress ==_FALSE) + { + if(IS_LED_WPS_BLINKING(pLed)) + return; + + if(pLed->bLedBlinkInProgress ==_TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + pLed->bLedScanBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_SCAN; + pLed->BlinkTimes = 24; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); + } + break; + + case LED_CTL_TX: + case LED_CTL_RX: + if((pLed->bLedBlinkInProgress ==_FALSE) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE)) + { + if(pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed)) + { + return; + } + + pLed->bLedBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_TXRX; + pLed->BlinkTimes = 2; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + break; + + case LED_CTL_LINK: + pLed->CurrLedState = RTW_LED_ON; + pLed->BlinkingLedState = RTW_LED_ON; + if( pLed->bLedBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + if( pLed->bLedScanBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedScanBlinkInProgress = _FALSE; + } + + _set_timer(&(pLed->BlinkTimer), 0); + break; + + case LED_CTL_START_WPS: //wait until xinpin finish + case LED_CTL_START_WPS_BOTTON: + if(pLed->bLedWPSBlinkInProgress ==_FALSE) + { + if(pLed->bLedBlinkInProgress ==_TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + if(pLed->bLedScanBlinkInProgress ==_TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedScanBlinkInProgress = _FALSE; + } + pLed->bLedWPSBlinkInProgress = _TRUE; + pLed->CurrLedState = RTW_LED_ON; + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), 0); + } + break; + + case LED_CTL_STOP_WPS: + pLed->bLedWPSBlinkInProgress = _FALSE; + if(adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on) + { + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), 0); + } + else + { + pLed->CurrLedState = RTW_LED_ON; + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), 0); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); + } + break; + + case LED_CTL_STOP_WPS_FAIL: + pLed->bLedWPSBlinkInProgress = _FALSE; + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), 0); + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); + break; + + case LED_CTL_START_TO_LINK: + case LED_CTL_NO_LINK: + if(!IS_LED_BLINKING(pLed)) + { + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), 0); + } + break; + + case LED_CTL_POWER_OFF: + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + if( pLed->bLedBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + if( pLed->bLedScanBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedScanBlinkInProgress = _FALSE; + } + if( pLed->bLedWPSBlinkInProgress ) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedWPSBlinkInProgress = _FALSE; + } + + SwLedOff(padapter, pLed); + break; + + default: + break; + + } + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); +} + + //COREGA, added by chiyoko, 20090316 + static void + SwLedControlMode3( + _adapter *padapter, + LED_CTL_MODE LedAction +) +{ + struct led_priv *ledpriv = &(padapter->ledpriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + PLED_USB pLed = &(ledpriv->SwLed0); + + switch(LedAction) + { + case LED_CTL_SITE_SURVEY: + if(pmlmepriv->LinkDetectInfo.bBusyTraffic) + ; + else if(pLed->bLedScanBlinkInProgress ==_FALSE) + { + if(IS_LED_WPS_BLINKING(pLed)) + return; + + if(pLed->bLedBlinkInProgress ==_TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + pLed->bLedScanBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_SCAN; + pLed->BlinkTimes = 24; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); + } + break; + + case LED_CTL_TX: + case LED_CTL_RX: + if((pLed->bLedBlinkInProgress ==_FALSE) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE)) + { + if(pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed)) + { + return; + } + + pLed->bLedBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_TXRX; + pLed->BlinkTimes = 2; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + break; + + case LED_CTL_LINK: + if(IS_LED_WPS_BLINKING(pLed)) + return; + + pLed->CurrLedState = RTW_LED_ON; + pLed->BlinkingLedState = RTW_LED_ON; + if( pLed->bLedBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + if( pLed->bLedScanBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedScanBlinkInProgress = _FALSE; + } + + _set_timer(&(pLed->BlinkTimer), 0); + break; + + case LED_CTL_START_WPS: //wait until xinpin finish + case LED_CTL_START_WPS_BOTTON: + if(pLed->bLedWPSBlinkInProgress ==_FALSE) + { + if(pLed->bLedBlinkInProgress ==_TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + if(pLed->bLedScanBlinkInProgress ==_TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedScanBlinkInProgress = _FALSE; + } + pLed->bLedWPSBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_WPS; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); + } + break; + + case LED_CTL_STOP_WPS: + if(pLed->bLedWPSBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedWPSBlinkInProgress = _FALSE; + } + else + { + pLed->bLedWPSBlinkInProgress = _TRUE; + } + + pLed->CurrLedState = LED_BLINK_WPS_STOP; + if(pLed->bLedOn) + { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA); + } + else + { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), 0); + } + + break; + + case LED_CTL_STOP_WPS_FAIL: + if(pLed->bLedWPSBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedWPSBlinkInProgress = _FALSE; + } + + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), 0); + break; + + case LED_CTL_START_TO_LINK: + case LED_CTL_NO_LINK: + if(!IS_LED_BLINKING(pLed)) + { + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), 0); + } + break; + + case LED_CTL_POWER_OFF: + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + if( pLed->bLedBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + if( pLed->bLedScanBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedScanBlinkInProgress = _FALSE; + } + if( pLed->bLedWPSBlinkInProgress ) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedWPSBlinkInProgress = _FALSE; + } + + SwLedOff(padapter, pLed); + break; + + default: + break; + + } + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); +} + + + //Edimax-Belkin, added by chiyoko, 20090413 +static void +SwLedControlMode4( + _adapter *padapter, + LED_CTL_MODE LedAction +) +{ + struct led_priv *ledpriv = &(padapter->ledpriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + PLED_USB pLed = &(ledpriv->SwLed0); + PLED_USB pLed1 = &(ledpriv->SwLed1); + + switch(LedAction) + { + case LED_CTL_START_TO_LINK: + if(pLed1->bLedWPSBlinkInProgress) + { + pLed1->bLedWPSBlinkInProgress = _FALSE; + _cancel_timer_ex(&(pLed1->BlinkTimer)); + + pLed1->BlinkingLedState = RTW_LED_OFF; + pLed1->CurrLedState = RTW_LED_OFF; + + if(pLed1->bLedOn) + _set_timer(&(pLed->BlinkTimer), 0); + } + + if( pLed->bLedStartToLinkBlinkInProgress == _FALSE ) + { + if(pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed)) + { + return; + } + if(pLed->bLedBlinkInProgress ==_TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + if(pLed->bLedNoLinkBlinkInProgress ==_TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedNoLinkBlinkInProgress = _FALSE; + } + + pLed->bLedStartToLinkBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_StartToBlink; + if( pLed->bLedOn ) + { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL); + } + else + { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + } + } + break; + + case LED_CTL_LINK: + case LED_CTL_NO_LINK: + //LED1 settings + if(LedAction == LED_CTL_LINK) + { + if(pLed1->bLedWPSBlinkInProgress) + { + pLed1->bLedWPSBlinkInProgress = _FALSE; + _cancel_timer_ex(&(pLed1->BlinkTimer)); + + pLed1->BlinkingLedState = RTW_LED_OFF; + pLed1->CurrLedState = RTW_LED_OFF; + + if(pLed1->bLedOn) + _set_timer(&(pLed->BlinkTimer), 0); + } + } + + if( pLed->bLedNoLinkBlinkInProgress == _FALSE ) + { + if(pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed)) + { + return; + } + if(pLed->bLedBlinkInProgress ==_TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + + pLed->bLedNoLinkBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_SLOWLY; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); + } + break; + + case LED_CTL_SITE_SURVEY: + if((pmlmepriv->LinkDetectInfo.bBusyTraffic) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE)) + ; + else if(pLed->bLedScanBlinkInProgress ==_FALSE) + { + if(IS_LED_WPS_BLINKING(pLed)) + return; + + if(pLed->bLedNoLinkBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedNoLinkBlinkInProgress = _FALSE; + } + if(pLed->bLedBlinkInProgress ==_TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + pLed->bLedScanBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_SCAN; + pLed->BlinkTimes = 24; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); + } + break; + + case LED_CTL_TX: + case LED_CTL_RX: + if(pLed->bLedBlinkInProgress ==_FALSE) + { + if(pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed)) + { + return; + } + if(pLed->bLedNoLinkBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedNoLinkBlinkInProgress = _FALSE; + } + pLed->bLedBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_TXRX; + pLed->BlinkTimes = 2; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + break; + + case LED_CTL_START_WPS: //wait until xinpin finish + case LED_CTL_START_WPS_BOTTON: + if(pLed1->bLedWPSBlinkInProgress) + { + pLed1->bLedWPSBlinkInProgress = _FALSE; + _cancel_timer_ex(&(pLed1->BlinkTimer)); + + pLed1->BlinkingLedState = RTW_LED_OFF; + pLed1->CurrLedState = RTW_LED_OFF; + + if(pLed1->bLedOn) + _set_timer(&(pLed->BlinkTimer), 0); + } + + if(pLed->bLedWPSBlinkInProgress ==_FALSE) + { + if(pLed->bLedNoLinkBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedNoLinkBlinkInProgress = _FALSE; + } + if(pLed->bLedBlinkInProgress ==_TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + if(pLed->bLedScanBlinkInProgress ==_TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedScanBlinkInProgress = _FALSE; + } + pLed->bLedWPSBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_WPS; + if( pLed->bLedOn ) + { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL); + } + else + { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + } + } + break; + + case LED_CTL_STOP_WPS: //WPS connect success + if(pLed->bLedWPSBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedWPSBlinkInProgress = _FALSE; + } + + pLed->bLedNoLinkBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_SLOWLY; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); + + break; + + case LED_CTL_STOP_WPS_FAIL: //WPS authentication fail + if(pLed->bLedWPSBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedWPSBlinkInProgress = _FALSE; + } + + pLed->bLedNoLinkBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_SLOWLY; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); + + //LED1 settings + if(pLed1->bLedWPSBlinkInProgress) + _cancel_timer_ex(&(pLed1->BlinkTimer)); + else + pLed1->bLedWPSBlinkInProgress = _TRUE; + + pLed1->CurrLedState = LED_BLINK_WPS_STOP; + if( pLed1->bLedOn ) + pLed1->BlinkingLedState = RTW_LED_OFF; + else + pLed1->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + + break; + + case LED_CTL_STOP_WPS_FAIL_OVERLAP: //WPS session overlap + if(pLed->bLedWPSBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedWPSBlinkInProgress = _FALSE; + } + + pLed->bLedNoLinkBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_SLOWLY; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); + + //LED1 settings + if(pLed1->bLedWPSBlinkInProgress) + _cancel_timer_ex(&(pLed1->BlinkTimer)); + else + pLed1->bLedWPSBlinkInProgress = _TRUE; + + pLed1->CurrLedState = LED_BLINK_WPS_STOP_OVERLAP; + pLed1->BlinkTimes = 10; + if( pLed1->bLedOn ) + pLed1->BlinkingLedState = RTW_LED_OFF; + else + pLed1->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + + break; + + case LED_CTL_POWER_OFF: + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + + if( pLed->bLedNoLinkBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedNoLinkBlinkInProgress = _FALSE; + } + if( pLed->bLedLinkBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedLinkBlinkInProgress = _FALSE; + } + if( pLed->bLedBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + if( pLed->bLedWPSBlinkInProgress ) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedWPSBlinkInProgress = _FALSE; + } + if( pLed->bLedScanBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedScanBlinkInProgress = _FALSE; + } + if( pLed->bLedStartToLinkBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedStartToLinkBlinkInProgress = _FALSE; + } + + if( pLed1->bLedWPSBlinkInProgress ) + { + _cancel_timer_ex(&(pLed1->BlinkTimer)); + pLed1->bLedWPSBlinkInProgress = _FALSE; + } + + pLed1->BlinkingLedState = LED_UNKNOWN; + SwLedOff(padapter, pLed); + SwLedOff(padapter, pLed1); + break; + + case LED_CTL_CONNECTION_NO_TRANSFER: + if(pLed->bLedBlinkInProgress == _FALSE) + { + if(pLed->bLedNoLinkBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedNoLinkBlinkInProgress = _FALSE; + } + pLed->bLedBlinkInProgress = _TRUE; + + pLed->CurrLedState = LED_BLINK_ALWAYS_ON; + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); + } + break; + + default: + break; + + } + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led %d\n", pLed->CurrLedState)); +} + + + + //Sercomm-Belkin, added by chiyoko, 20090415 +static void +SwLedControlMode5( + _adapter *padapter, + LED_CTL_MODE LedAction +) +{ + struct led_priv *ledpriv = &(padapter->ledpriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + PLED_USB pLed = &(ledpriv->SwLed0); + + if(pHalData->CustomerID == RT_CID_819x_CAMEO) + pLed = &(ledpriv->SwLed1); + + switch(LedAction) + { + case LED_CTL_POWER_ON: + case LED_CTL_NO_LINK: + case LED_CTL_LINK: //solid blue + pLed->CurrLedState = RTW_LED_ON; + pLed->BlinkingLedState = RTW_LED_ON; + + _set_timer(&(pLed->BlinkTimer), 0); + break; + + case LED_CTL_SITE_SURVEY: + if((pmlmepriv->LinkDetectInfo.bBusyTraffic) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE)) + ; + else if(pLed->bLedScanBlinkInProgress ==_FALSE) + { + if(pLed->bLedBlinkInProgress ==_TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + pLed->bLedScanBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_SCAN; + pLed->BlinkTimes = 24; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); + } + break; + + case LED_CTL_TX: + case LED_CTL_RX: + if(pLed->bLedBlinkInProgress ==_FALSE) + { + if(pLed->CurrLedState == LED_BLINK_SCAN) + { + return; + } + pLed->bLedBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_TXRX; + pLed->BlinkTimes = 2; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + break; + + case LED_CTL_POWER_OFF: + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + + if( pLed->bLedBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + + SwLedOff(padapter, pLed); + break; + + default: + break; + + } + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led %d\n", pLed->CurrLedState)); +} + + //WNC-Corega, added by chiyoko, 20090902 +static void +SwLedControlMode6( + _adapter *padapter, + LED_CTL_MODE LedAction +) +{ + struct led_priv *ledpriv = &(padapter->ledpriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + PLED_USB pLed0 = &(ledpriv->SwLed0); + + switch(LedAction) + { + case LED_CTL_POWER_ON: + case LED_CTL_LINK: + case LED_CTL_NO_LINK: + _cancel_timer_ex(&(pLed0->BlinkTimer)); + pLed0->CurrLedState = RTW_LED_ON; + pLed0->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed0->BlinkTimer), 0); + break; + + case LED_CTL_POWER_OFF: + SwLedOff(padapter, pLed0); + break; + + default: + break; + } + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("ledcontrol 6 Led %d\n", pLed0->CurrLedState)); +} + +//Netgear, added by sinda, 2011/11/11 + void + SwLedControlMode7( + PADAPTER Adapter, + LED_CTL_MODE LedAction + ) +{ + struct led_priv *ledpriv = &(Adapter->ledpriv); + struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; + PLED_USB pLed = &(ledpriv->SwLed0); + + switch(LedAction) + { + case LED_CTL_SITE_SURVEY: + if(pmlmepriv->LinkDetectInfo.bBusyTraffic) + ; + else if(pLed->bLedScanBlinkInProgress == _FALSE) + { + if(IS_LED_WPS_BLINKING(pLed)) + return; + + if(pLed->bLedBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + pLed->bLedScanBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_SCAN; + pLed->BlinkTimes = 6; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_NETGEAR); + } + break; + + case LED_CTL_LINK: + if(IS_LED_WPS_BLINKING(pLed)) + return; + + pLed->CurrLedState = RTW_LED_ON; + pLed->BlinkingLedState = RTW_LED_ON; + if( pLed->bLedBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + if( pLed->bLedScanBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedScanBlinkInProgress = _FALSE; + } + + _set_timer(&(pLed->BlinkTimer), 0); + break; + + case LED_CTL_START_WPS: //wait until xinpin finish + case LED_CTL_START_WPS_BOTTON: + if(pLed->bLedWPSBlinkInProgress ==_FALSE) + { + if(pLed->bLedBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + if(pLed->bLedScanBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedScanBlinkInProgress = _FALSE; + } + pLed->bLedWPSBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_WPS; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_NETGEAR); + } + break; + + case LED_CTL_STOP_WPS: + if(pLed->bLedWPSBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedWPSBlinkInProgress = _FALSE; + } + else + { + pLed->bLedWPSBlinkInProgress = _TRUE; + } + + pLed->CurrLedState = LED_BLINK_WPS_STOP; + if(pLed->bLedOn) + { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_NETGEAR); + } + else + { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), 0); + } + + break; + + + case LED_CTL_STOP_WPS_FAIL: + case LED_CTL_STOP_WPS_FAIL_OVERLAP: //WPS session overlap + if(pLed->bLedWPSBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedWPSBlinkInProgress = _FALSE; + } + + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), 0); + break; + + case LED_CTL_START_TO_LINK: + case LED_CTL_NO_LINK: + if(!IS_LED_BLINKING(pLed)) + { + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), 0); + } + break; + + case LED_CTL_POWER_OFF: + case LED_CTL_POWER_ON: + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + if( pLed->bLedBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + if( pLed->bLedScanBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedScanBlinkInProgress = _FALSE; + } + if( pLed->bLedWPSBlinkInProgress ) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedWPSBlinkInProgress = _FALSE; + } + + _set_timer(&(pLed->BlinkTimer), 0); + break; + + default: + break; + + } + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("LEd control mode 7 CurrLedState %d\n", pLed->CurrLedState)); +} + +void +SwLedControlMode8( + PADAPTER Adapter, + LED_CTL_MODE LedAction + ) +{ + struct led_priv *ledpriv = &(Adapter->ledpriv); + struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; + PLED_USB pLed0 = &(ledpriv->SwLed0); + + switch(LedAction) + { + case LED_CTL_LINK: + _cancel_timer_ex(&(pLed0->BlinkTimer)); + pLed0->CurrLedState = RTW_LED_ON; + pLed0->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed0->BlinkTimer), 0); + break; + + case LED_CTL_NO_LINK: + _cancel_timer_ex(&(pLed0->BlinkTimer)); + pLed0->CurrLedState = RTW_LED_OFF; + pLed0->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed0->BlinkTimer), 0); + break; + + case LED_CTL_POWER_OFF: + SwLedOff(Adapter, pLed0); + break; + + default: + break; + } + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led control mode 8 %d\n", pLed0->CurrLedState)); + +} + +//page added for Belkin AC950, 20120813 +void +SwLedControlMode9( + IN PADAPTER Adapter, + IN LED_CTL_MODE LedAction +) +{ + struct led_priv *ledpriv = &(Adapter->ledpriv); + struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; + PLED_USB pLed = &(ledpriv->SwLed0); + PLED_USB pLed1 = &(ledpriv->SwLed1); + PLED_USB pLed2 = &(ledpriv->SwLed2); + BOOLEAN bWPSOverLap = _FALSE; + //DBG_871X("LedAction=%d \n", LedAction); + switch(LedAction) + { + case LED_CTL_START_TO_LINK: + if(pLed2->bLedBlinkInProgress == _FALSE) + { + pLed2->bLedBlinkInProgress = _TRUE; + pLed2->BlinkingLedState = RTW_LED_ON; + pLed2->CurrLedState = LED_BLINK_LINK_IN_PROCESS; + + _set_timer(&(pLed2->BlinkTimer), 0); + } + break; + + case LED_CTL_LINK: + case LED_CTL_NO_LINK: + //LED1 settings + if(LedAction == LED_CTL_NO_LINK) + { + //if(pMgntInfo->AuthStatus == AUTH_STATUS_FAILED) + if(0) + { + pLed1->CurrLedState = LED_BLINK_AUTH_ERROR; + if( pLed1->bLedOn ) + pLed1->BlinkingLedState = RTW_LED_OFF; + else + pLed1->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed1->BlinkTimer), 0); + } + else + { + pLed1->CurrLedState = RTW_LED_OFF; + pLed1->BlinkingLedState = RTW_LED_OFF; + if( pLed1->bLedOn ) + _set_timer(&(pLed1->BlinkTimer), 0); + } + } + else + { + pLed1->CurrLedState = RTW_LED_OFF; + pLed1->BlinkingLedState = RTW_LED_OFF; + if( pLed1->bLedOn ) + _set_timer(&(pLed1->BlinkTimer), 0); + } + + //LED2 settings + if(LedAction == LED_CTL_LINK) + { + if(Adapter->securitypriv.dot11PrivacyAlgrthm != _NO_PRIVACY_) + { + if(pLed2->bLedBlinkInProgress ==_TRUE) + { + _cancel_timer_ex(&(pLed2->BlinkTimer)); + pLed2->bLedBlinkInProgress = _FALSE; + } + pLed2->CurrLedState = RTW_LED_ON; + pLed2->bLedNoLinkBlinkInProgress = _TRUE; + if(!pLed2->bLedOn) + _set_timer(&(pLed2->BlinkTimer), 0); + } + else + { + if(pLed2->bLedWPSBlinkInProgress != _TRUE) + { + pLed2->CurrLedState = RTW_LED_OFF; + pLed2->BlinkingLedState = RTW_LED_OFF; + if(pLed2->bLedOn) + _set_timer(&(pLed2->BlinkTimer), 0); + } + } + } + else //NO_LINK + { + if(pLed2->bLedWPSBlinkInProgress == _FALSE) + { + pLed2->CurrLedState = RTW_LED_OFF; + pLed2->BlinkingLedState = RTW_LED_OFF; + if(pLed2->bLedOn) + _set_timer(&(pLed2->BlinkTimer), 0); + } + } + + //LED0 settings + if( pLed->bLedNoLinkBlinkInProgress == _FALSE ) + { + if(pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed)) + { + return; + } + if(pLed->bLedBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + + pLed->bLedNoLinkBlinkInProgress = _TRUE; + if(IS_HARDWARE_TYPE_8812AU(Adapter)) + { + if(LedAction == LED_CTL_LINK) + { + pLed->BlinkingLedState = RTW_LED_ON; + pLed->CurrLedState = LED_BLINK_SLOWLY; + } + else + { + pLed->CurrLedState = LED_BLINK_SLOWLY; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + } + } + else + { + pLed->CurrLedState = LED_BLINK_SLOWLY; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + } + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); + } + + break; + + case LED_CTL_SITE_SURVEY: + if((pmlmepriv->LinkDetectInfo.bBusyTraffic) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE)) + ; + else //if(pLed->bLedScanBlinkInProgress ==FALSE) + { + if(IS_LED_WPS_BLINKING(pLed)) + return; + + if(pLed->bLedNoLinkBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedNoLinkBlinkInProgress = _FALSE; + } + if(pLed->bLedBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + pLed->bLedScanBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_SCAN; + pLed->BlinkTimes = 24; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); + + } + break; + + case LED_CTL_TX: + case LED_CTL_RX: + if(pLed->bLedBlinkInProgress == _FALSE) + { + if(pLed->CurrLedState == LED_BLINK_SCAN || IS_LED_WPS_BLINKING(pLed)) + { + return; + } + if(pLed->bLedNoLinkBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedNoLinkBlinkInProgress = _FALSE; + } + pLed->bLedBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_TXRX; + pLed->BlinkTimes = 2; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + break; + + case LED_CTL_START_WPS: //wait until xinpin finish + case LED_CTL_START_WPS_BOTTON: + pLed2->bLedBlinkInProgress = _TRUE; + pLed2->BlinkingLedState = RTW_LED_ON; + pLed2->CurrLedState = LED_BLINK_LINK_IN_PROCESS; + pLed2->bLedWPSBlinkInProgress = _TRUE; + + _set_timer(&(pLed2->BlinkTimer), 500); + + break; + + case LED_CTL_STOP_WPS: //WPS connect success + //LED2 settings + if(pLed2->bLedWPSBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed2->BlinkTimer)); + pLed2->bLedBlinkInProgress = _FALSE; + pLed2->bLedWPSBlinkInProgress = _FALSE; + } + pLed2->CurrLedState = RTW_LED_ON; + pLed2->bLedNoLinkBlinkInProgress = _TRUE; + if(!pLed2->bLedOn) + _set_timer(&(pLed2->BlinkTimer), 0); + + //LED1 settings + _cancel_timer_ex(&(pLed1->BlinkTimer)); + pLed1->CurrLedState = RTW_LED_OFF; + pLed1->BlinkingLedState = RTW_LED_OFF; + if( pLed1->bLedOn ) + _set_timer(&(pLed1->BlinkTimer), 0); + + + break; + + case LED_CTL_STOP_WPS_FAIL: //WPS authentication fail + //LED1 settings + //if(bWPSOverLap == _FALSE) + { + pLed1->CurrLedState = LED_BLINK_AUTH_ERROR; + pLed1->BlinkTimes = 50; + if( pLed1->bLedOn ) + pLed1->BlinkingLedState = RTW_LED_OFF; + else + pLed1->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed1->BlinkTimer), 0); + } + //else + //{ + // bWPSOverLap = _FALSE; + // pLed1->CurrLedState = RTW_LED_OFF; + // pLed1->BlinkingLedState = RTW_LED_OFF; + // _set_timer(&(pLed1->BlinkTimer), 0); + //} + + //LED2 settings + pLed2->CurrLedState = RTW_LED_OFF; + pLed2->BlinkingLedState = RTW_LED_OFF; + pLed2->bLedWPSBlinkInProgress = _FALSE; + if( pLed2->bLedOn ) + _set_timer(&(pLed2->BlinkTimer), 0); + + break; + + case LED_CTL_STOP_WPS_FAIL_OVERLAP: //WPS session overlap + //LED1 settings + bWPSOverLap = _TRUE; + pLed1->CurrLedState = LED_BLINK_WPS_STOP_OVERLAP; + pLed1->BlinkTimes = 10; + pLed1->BlinkCounter = 50; + if( pLed1->bLedOn ) + pLed1->BlinkingLedState = RTW_LED_OFF; + else + pLed1->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed1->BlinkTimer), 0); + + //LED2 settings + pLed2->CurrLedState = RTW_LED_OFF; + pLed2->BlinkingLedState = RTW_LED_OFF; + pLed2->bLedWPSBlinkInProgress = _FALSE; + if( pLed2->bLedOn ) + _set_timer(&(pLed2->BlinkTimer), 0); + + break; + + case LED_CTL_POWER_OFF: + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + + if( pLed->bLedNoLinkBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedNoLinkBlinkInProgress = _FALSE; + } + if( pLed->bLedLinkBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedLinkBlinkInProgress = _FALSE; + } + if( pLed->bLedBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + if( pLed->bLedWPSBlinkInProgress ) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedWPSBlinkInProgress = _FALSE; + } + if( pLed->bLedScanBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedScanBlinkInProgress = _FALSE; + } + if( pLed->bLedStartToLinkBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedStartToLinkBlinkInProgress = _FALSE; + } + + if( pLed1->bLedWPSBlinkInProgress ) + { + _cancel_timer_ex(&(pLed1->BlinkTimer)); + pLed1->bLedWPSBlinkInProgress = _FALSE; + } + + + pLed1->BlinkingLedState = LED_UNKNOWN; + SwLedOff(Adapter, pLed); + SwLedOff(Adapter, pLed1); + break; + + case LED_CTL_CONNECTION_NO_TRANSFER: + if(pLed->bLedBlinkInProgress == _FALSE) + { + if(pLed->bLedNoLinkBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedNoLinkBlinkInProgress = _FALSE; + } + pLed->bLedBlinkInProgress = _TRUE; + + pLed->CurrLedState = LED_BLINK_ALWAYS_ON; + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); + } + break; + + default: + break; + + } + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led control mode 9 Led %d\n", pLed->CurrLedState)); +} + +//page added for Netgear A6200V2, 20120827 +void +SwLedControlMode10( + PADAPTER Adapter, + LED_CTL_MODE LedAction +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct led_priv *ledpriv = &(Adapter->ledpriv); + struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; + PLED_USB pLed = &(ledpriv->SwLed0); + PLED_USB pLed1 = &(ledpriv->SwLed1); + + switch(LedAction) + { + case LED_CTL_START_TO_LINK: + if(pLed1->bLedBlinkInProgress == _FALSE) + { + pLed1->bLedBlinkInProgress = _TRUE; + pLed1->BlinkingLedState = RTW_LED_ON; + pLed1->CurrLedState = LED_BLINK_LINK_IN_PROCESS; + + _set_timer(&(pLed1->BlinkTimer), 0); + } + break; + + case LED_CTL_LINK: + case LED_CTL_NO_LINK: + if(LedAction == LED_CTL_LINK) + { + if(pLed->bLedWPSBlinkInProgress == _TRUE || pLed1->bLedWPSBlinkInProgress == _TRUE) + ; + else + { + if(pHalData->CurrentBandType == BAND_ON_2_4G) + //LED0 settings + { + pLed->CurrLedState = RTW_LED_ON; + pLed->BlinkingLedState = RTW_LED_ON; + if(pLed->bLedBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + _set_timer(&(pLed->BlinkTimer), 0); + + pLed1->CurrLedState = RTW_LED_OFF; + pLed1->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed1->BlinkTimer), 0); + } + else if(pHalData->CurrentBandType == BAND_ON_5G) + //LED1 settings + { + pLed1->CurrLedState = RTW_LED_ON; + pLed1->BlinkingLedState = RTW_LED_ON; + if(pLed1->bLedBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed1->BlinkTimer)); + pLed1->bLedBlinkInProgress = _FALSE; + } + _set_timer(&(pLed1->BlinkTimer), 0); + + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), 0); + } + } + } + else if(LedAction == LED_CTL_NO_LINK) //TODO by page + { + if(pLed->bLedWPSBlinkInProgress == _TRUE || pLed1->bLedWPSBlinkInProgress == _TRUE) + ; + else + { + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + if( pLed->bLedOn ) + _set_timer(&(pLed->BlinkTimer), 0); + + pLed1->CurrLedState = RTW_LED_OFF; + pLed1->BlinkingLedState = RTW_LED_OFF; + if( pLed1->bLedOn ) + _set_timer(&(pLed1->BlinkTimer), 0); + } + } + + break; + + case LED_CTL_SITE_SURVEY: + if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) + ; //don't blink when media connect + else //if(pLed->bLedScanBlinkInProgress ==FALSE) + { + if(IS_LED_WPS_BLINKING(pLed) || IS_LED_WPS_BLINKING(pLed1)) + return; + + if(pLed->bLedNoLinkBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedNoLinkBlinkInProgress = _FALSE; + } + if(pLed->bLedBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + pLed->bLedScanBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_SCAN; + pLed->BlinkTimes = 12; + pLed->BlinkingLedState = LED_BLINK_SCAN; + _set_timer(&(pLed->BlinkTimer), 0); + + if(pLed1->bLedNoLinkBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed1->BlinkTimer)); + pLed1->bLedNoLinkBlinkInProgress = _FALSE; + } + if(pLed1->bLedBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed1->BlinkTimer)); + pLed1->bLedBlinkInProgress = _FALSE; + } + pLed1->bLedScanBlinkInProgress = _TRUE; + pLed1->CurrLedState = LED_BLINK_SCAN; + pLed1->BlinkTimes = 12; + pLed1->BlinkingLedState = LED_BLINK_SCAN; + _set_timer(&(pLed1->BlinkTimer), LED_BLINK_LINK_SLOWLY_INTERVAL_NETGEAR); + + } + break; + + case LED_CTL_START_WPS: //wait until xinpin finish + case LED_CTL_START_WPS_BOTTON: + //LED0 settings + if(pLed->bLedBlinkInProgress == _FALSE) + { + pLed->bLedBlinkInProgress = _TRUE; + pLed->bLedWPSBlinkInProgress = _TRUE; + pLed->BlinkingLedState = LED_BLINK_WPS; + pLed->CurrLedState = LED_BLINK_WPS; + _set_timer(&(pLed->BlinkTimer), 0); + } + + //LED1 settings + if(pLed1->bLedBlinkInProgress == _FALSE) + { + pLed1->bLedBlinkInProgress = _TRUE; + pLed1->bLedWPSBlinkInProgress = _TRUE; + pLed1->BlinkingLedState = LED_BLINK_WPS; + pLed1->CurrLedState = LED_BLINK_WPS; + _set_timer(&(pLed1->BlinkTimer), LED_BLINK_NORMAL_INTERVAL+LED_BLINK_LINK_INTERVAL_NETGEAR); + } + + + break; + + case LED_CTL_STOP_WPS: //WPS connect success + if(pHalData->CurrentBandType == BAND_ON_2_4G) + //LED0 settings + { + pLed->bLedWPSBlinkInProgress = _FALSE; + pLed->CurrLedState = RTW_LED_ON; + pLed->BlinkingLedState = RTW_LED_ON; + if(pLed->bLedBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + _set_timer(&(pLed->BlinkTimer), 0); + + pLed1->CurrLedState = RTW_LED_OFF; + pLed1->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed1->BlinkTimer), 0); + } + else if(pHalData->CurrentBandType == BAND_ON_5G) + //LED1 settings + { + pLed1->bLedWPSBlinkInProgress = _FALSE; + pLed1->CurrLedState = RTW_LED_ON; + pLed1->BlinkingLedState = RTW_LED_ON; + if(pLed1->bLedBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed1->BlinkTimer)); + pLed1->bLedBlinkInProgress = _FALSE; + } + _set_timer(&(pLed1->BlinkTimer), 0); + + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), 0); + } + + break; + + case LED_CTL_STOP_WPS_FAIL: //WPS authentication fail + //LED1 settings + pLed1->bLedWPSBlinkInProgress = _FALSE; + pLed1->CurrLedState = RTW_LED_OFF; + pLed1->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed1->BlinkTimer), 0); + + //LED0 settings + pLed->bLedWPSBlinkInProgress = _FALSE; + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + if( pLed->bLedOn ) + _set_timer(&(pLed->BlinkTimer), 0); + + break; + + + default: + break; + + } + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led control mode 10 Led %d\n", pLed->CurrLedState)); +} + + //Edimax-ASUS, added by Page, 20121221 +void +SwLedControlMode11( + PADAPTER Adapter, + LED_CTL_MODE LedAction +) +{ + struct led_priv *ledpriv = &(Adapter->ledpriv); + struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; + PLED_USB pLed = &(ledpriv->SwLed0); + + switch(LedAction) + { + case LED_CTL_POWER_ON: + case LED_CTL_START_TO_LINK: + case LED_CTL_NO_LINK: + pLed->CurrLedState = RTW_LED_ON; + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), 0); + break; + + case LED_CTL_LINK: + if( pLed->bLedBlinkInProgress == _TRUE ) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + pLed->bLedBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_TXRX; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); + break; + + case LED_CTL_START_WPS: //wait until xinpin finish + case LED_CTL_START_WPS_BOTTON: + if(pLed->bLedBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + pLed->bLedWPSBlinkInProgress = _TRUE; + pLed->bLedBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_WPS; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + pLed->BlinkTimes = 5; + _set_timer(&(pLed->BlinkTimer), 0); + + break; + + + case LED_CTL_STOP_WPS: + case LED_CTL_STOP_WPS_FAIL: + if(pLed->bLedBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + pLed->CurrLedState = LED_BLINK_WPS_STOP; + _set_timer(&(pLed->BlinkTimer), 0); + break; + + case LED_CTL_POWER_OFF: + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + + if( pLed->bLedNoLinkBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedNoLinkBlinkInProgress = _FALSE; + } + if( pLed->bLedLinkBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedLinkBlinkInProgress = _FALSE; + } + if( pLed->bLedBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + if( pLed->bLedWPSBlinkInProgress ) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedWPSBlinkInProgress = _FALSE; + } + if( pLed->bLedScanBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedScanBlinkInProgress = _FALSE; + } + + SwLedOff(Adapter, pLed); + break; + + default: + break; + + } + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led mode 1 CurrLedState %d\n", pLed->CurrLedState)); +} + +// page added for NEC + +VOID +SwLedControlMode12( + PADAPTER Adapter, + LED_CTL_MODE LedAction +) +{ + struct led_priv *ledpriv = &(Adapter->ledpriv); + struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; + PLED_USB pLed = &(ledpriv->SwLed0); + + switch(LedAction) + { + case LED_CTL_POWER_ON: + case LED_CTL_NO_LINK: + case LED_CTL_LINK: + case LED_CTL_SITE_SURVEY: + + if( pLed->bLedNoLinkBlinkInProgress == _FALSE ) + { + if(pLed->bLedBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + + pLed->bLedNoLinkBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_SLOWLY; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); + } + break; + + case LED_CTL_TX: + case LED_CTL_RX: + if(pLed->bLedBlinkInProgress == _FALSE) + { + if(pLed->bLedNoLinkBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedNoLinkBlinkInProgress = _FALSE; + } + pLed->bLedBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_TXRX; + pLed->BlinkTimes = 2; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + break; + + case LED_CTL_POWER_OFF: + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + + if( pLed->bLedBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + + if( pLed->bLedScanBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedScanBlinkInProgress = _FALSE; + } + + if(pLed->bLedNoLinkBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedNoLinkBlinkInProgress = _FALSE; + } + + SwLedOff(Adapter, pLed); + break; + + default: + break; + + } + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("SWLed12 %d\n", pLed->CurrLedState)); +} + +// Maddest add for NETGEAR R6100 + +VOID +SwLedControlMode13( + IN PADAPTER Adapter, + IN LED_CTL_MODE LedAction +) +{ + struct led_priv *ledpriv = &(Adapter->ledpriv); + struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; + PLED_USB pLed = &(ledpriv->SwLed0); + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led control mode 13 CurrLedState %d, LedAction %d\n", pLed->CurrLedState,LedAction)); + switch(LedAction) + { + case LED_CTL_LINK: + if(pLed->bLedWPSBlinkInProgress) + { + return; + } + + + pLed->CurrLedState = RTW_LED_ON; + pLed->BlinkingLedState = RTW_LED_ON; + if( pLed->bLedBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + if( pLed->bLedScanBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedScanBlinkInProgress = _FALSE; + } + + _set_timer(&(pLed->BlinkTimer), 0); + break; + + case LED_CTL_START_WPS: //wait until xinpin finish + case LED_CTL_START_WPS_BOTTON: + if(pLed->bLedWPSBlinkInProgress == _FALSE) + { + if(pLed->bLedBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + if(pLed->bLedScanBlinkInProgress == _TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedScanBlinkInProgress = _FALSE; + } + pLed->bLedWPSBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_WPS; + if( pLed->bLedOn ) + { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_WPS_BLINK_OFF_INTERVAL_NETGEAR); + } + else + { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_WPS_BLINK_ON_INTERVAL_NETGEAR); + } + } + break; + + case LED_CTL_STOP_WPS: + if(pLed->bLedWPSBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedWPSBlinkInProgress = _FALSE; + } + else + { + pLed->bLedWPSBlinkInProgress = _TRUE; + } + + pLed->bLedWPSBlinkInProgress = _FALSE; + pLed->CurrLedState = LED_BLINK_WPS_STOP; + if(pLed->bLedOn) + { + pLed->BlinkingLedState = RTW_LED_OFF; + + _set_timer(&(pLed->BlinkTimer), 0); + } + + break; + + + case LED_CTL_STOP_WPS_FAIL: + case LED_CTL_STOP_WPS_FAIL_OVERLAP: //WPS session overlap + if(pLed->bLedWPSBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedWPSBlinkInProgress = _FALSE; + } + + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), 0); + break; + + case LED_CTL_START_TO_LINK: + if((pLed->bLedBlinkInProgress == _FALSE) && (pLed->bLedWPSBlinkInProgress == _FALSE)) + { + pLed->bLedBlinkInProgress = _TRUE; + pLed->BlinkingLedState = RTW_LED_ON; + pLed->CurrLedState = LED_BLINK_LINK_IN_PROCESS; + + _set_timer(&(pLed->BlinkTimer), 0); + } + break; + + case LED_CTL_NO_LINK: + + if(pLed->bLedWPSBlinkInProgress) + { + return; + } + if( pLed->bLedBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + if( pLed->bLedScanBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedScanBlinkInProgress = _FALSE; + } + //if(!IS_LED_BLINKING(pLed)) + { + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), 0); + } + break; + + case LED_CTL_POWER_OFF: + case LED_CTL_POWER_ON: + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + if( pLed->bLedBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + if( pLed->bLedScanBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedScanBlinkInProgress = _FALSE; + } + if( pLed->bLedWPSBlinkInProgress ) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedWPSBlinkInProgress = _FALSE; + } + + if (LedAction == LED_CTL_POWER_ON) + _set_timer(&(pLed->BlinkTimer), 0); + else + SwLedOff(Adapter, pLed); + break; + + default: + break; + + } + + +} + +// Maddest add for DNI Buffalo + +VOID +SwLedControlMode14( + IN PADAPTER Adapter, + IN LED_CTL_MODE LedAction +) +{ + struct led_priv *ledpriv = &(Adapter->ledpriv); + PLED_USB pLed = &(ledpriv->SwLed0); + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led control mode 14 CurrLedState %d, LedAction %d\n", pLed->CurrLedState,LedAction)); + switch(LedAction) + { + case LED_CTL_POWER_OFF: + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led control mode 14 LED_CTL_POWER_OFF\n")); + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + if( pLed->bLedBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + SwLedOff(Adapter, pLed); + break; + + case LED_CTL_POWER_ON: + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led control mode 14 LED_CTL_POWER_ON\n")); + SwLedOn(Adapter, pLed); + break; + + case LED_CTL_LINK: + case LED_CTL_NO_LINK: + if (IS_HARDWARE_TYPE_8812AU(Adapter)) + SwLedOn(Adapter, pLed); + break; + + case LED_CTL_TX: + case LED_CTL_RX: + if(pLed->bLedBlinkInProgress ==_FALSE) + { + pLed->bLedBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_TXRX; + pLed->BlinkTimes = 2; + if( pLed->bLedOn ) + { + pLed->BlinkingLedState = RTW_LED_OFF; + if (IS_HARDWARE_TYPE_8812AU(Adapter)) + _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA); + else + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + else + { + pLed->BlinkingLedState = RTW_LED_ON; + if (IS_HARDWARE_TYPE_8812AU(Adapter)) + _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); + else + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + } + } + break; + + default: + break; + } +} + +// Maddest add for Dlink + +VOID +SwLedControlMode15( + IN PADAPTER Adapter, + IN LED_CTL_MODE LedAction +) +{ + struct led_priv *ledpriv = &(Adapter->ledpriv); + struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; + PLED_USB pLed = &(ledpriv->SwLed0); + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led control mode 15 CurrLedState %d, LedAction %d\n", pLed->CurrLedState,LedAction)); + switch(LedAction) + { + case LED_CTL_START_WPS: //wait until xinpin finish + case LED_CTL_START_WPS_BOTTON: + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led control mode 15 LED_CTL_START_WPS\n")); + if(pLed->bLedWPSBlinkInProgress ==_FALSE) + { + if(pLed->bLedBlinkInProgress ==_TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + if(pLed->bLedScanBlinkInProgress ==_TRUE) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedScanBlinkInProgress = _FALSE; + } + pLed->bLedWPSBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_WPS; + if( pLed->bLedOn ) + { + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), LED_WPS_BLINK_OFF_INTERVAL_NETGEAR); + } + else + { + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_WPS_BLINK_ON_INTERVAL_NETGEAR); + } + } + break; + + case LED_CTL_STOP_WPS: + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led control mode 15 LED_CTL_STOP_WPS\n")); + if(pLed->bLedWPSBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + } + + pLed->CurrLedState = LED_BLINK_WPS_STOP; + //if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) + { + pLed->BlinkingLedState = RTW_LED_ON; + + _set_timer(&(pLed->BlinkTimer), 0); + } + + break; + + case LED_CTL_STOP_WPS_FAIL: + case LED_CTL_STOP_WPS_FAIL_OVERLAP: //WPS session overlap + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led control mode 15 LED_CTL_STOP_WPS_FAIL\n")); + if(pLed->bLedWPSBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedWPSBlinkInProgress = _FALSE; + } + + pLed->CurrLedState = RTW_LED_OFF; + pLed->BlinkingLedState = RTW_LED_OFF; + _set_timer(&(pLed->BlinkTimer), 0); + break; + + case LED_CTL_NO_LINK: + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led control mode 15 LED_CTL_NO_LINK\n")); + if(pLed->bLedWPSBlinkInProgress) + { + return; + } + + /*if(Adapter->securitypriv.dot11PrivacyAlgrthm > _NO_PRIVACY_) + { + if(SecIsTxKeyInstalled(Adapter, pMgntInfo->Bssid)) + { + } + else + { + if(pMgntInfo->LEDAssocState ==LED_ASSOC_SECURITY_BEGIN) + return; + } + }*/ + + if( pLed->bLedBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + if( pLed->bLedScanBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedScanBlinkInProgress = _FALSE; + } + //if(!IS_LED_BLINKING(pLed)) + { + pLed->CurrLedState = LED_BLINK_NO_LINK; + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), 30); + } + break; + + case LED_CTL_LINK: + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led control mode 15 LED_CTL_LINK\n")); + + if(pLed->bLedWPSBlinkInProgress) + { + return; + } + + if( pLed->bLedBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + + pLed->CurrLedState = LED_BLINK_LINK_IDEL; + pLed->BlinkingLedState = RTW_LED_ON; + + _set_timer(&(pLed->BlinkTimer), 30); + break; + + case LED_CTL_SITE_SURVEY : + if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) + return; + + if(pLed->bLedWPSBlinkInProgress ==_TRUE) + return; + + if( pLed->bLedBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + pLed->CurrLedState = LED_BLINK_SCAN; + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), 0); + break; + + case LED_CTL_TX: + case LED_CTL_RX: + if(pLed->bLedWPSBlinkInProgress) + { + return; + } + + if( pLed->bLedBlinkInProgress) + { + _cancel_timer_ex(&(pLed->BlinkTimer)); + pLed->bLedBlinkInProgress = _FALSE; + } + + pLed->bLedBlinkInProgress = _TRUE; + pLed->CurrLedState = LED_BLINK_TXRX; + pLed->BlinkTimes = 2; + if( pLed->bLedOn ) + pLed->BlinkingLedState = RTW_LED_OFF; + else + pLed->BlinkingLedState = RTW_LED_ON; + _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); + break; + + default: + break; + } +} + +void +LedControlUSB( + _adapter *padapter, + LED_CTL_MODE LedAction + ) +{ + struct led_priv *ledpriv = &(padapter->ledpriv); + +#if(MP_DRIVER == 1) + if (padapter->registrypriv.mp_mode == 1) + return; +#endif + + if (RTW_CANNOT_RUN(padapter) || (!rtw_is_hw_init_completed(padapter))) { + /*DBG_871X("%s bDriverStopped:%s, bSurpriseRemoved:%s\n" + , __func__ + , rtw_is_drv_stopped(padapter)?"True":"False" + , rtw_is_surprise_removed(padapter)?"True":"False" );*/ + return; + } + + if( ledpriv->bRegUseLed == _FALSE) + return; + + //if(priv->bInHctTest) + // return; + +#ifdef CONFIG_CONCURRENT_MODE + // Only do led action for PRIMARY_ADAPTER + if (padapter->adapter_type != PRIMARY_ADAPTER) + return; +#endif + + if( (adapter_to_pwrctl(padapter)->rf_pwrstate != rf_on && + adapter_to_pwrctl(padapter)->rfoff_reason > RF_CHANGE_BY_PS) && + (LedAction == LED_CTL_TX || LedAction == LED_CTL_RX || + LedAction == LED_CTL_SITE_SURVEY || + LedAction == LED_CTL_LINK || + LedAction == LED_CTL_NO_LINK || + LedAction == LED_CTL_POWER_ON) ) + { + return; + } + + switch(ledpriv->LedStrategy) + { + case SW_LED_MODE0: + SwLedControlMode0(padapter, LedAction); + break; + + case SW_LED_MODE1: + SwLedControlMode1(padapter, LedAction); + break; + + case SW_LED_MODE2: + SwLedControlMode2(padapter, LedAction); + break; + + case SW_LED_MODE3: + SwLedControlMode3(padapter, LedAction); + break; + + case SW_LED_MODE4: + SwLedControlMode4(padapter, LedAction); + break; + + case SW_LED_MODE5: + SwLedControlMode5(padapter, LedAction); + break; + + case SW_LED_MODE6: + SwLedControlMode6(padapter, LedAction); + break; + + case SW_LED_MODE7: + SwLedControlMode7(padapter, LedAction); + break; + + case SW_LED_MODE8: + SwLedControlMode8(padapter, LedAction); + break; + + case SW_LED_MODE9: + SwLedControlMode9(padapter, LedAction); + break; + + case SW_LED_MODE10: + SwLedControlMode10(padapter, LedAction); + break; + + case SW_LED_MODE11: + SwLedControlMode11(padapter, LedAction); + break; + + case SW_LED_MODE12: + SwLedControlMode12(padapter, LedAction); + break; + + case SW_LED_MODE13: + SwLedControlMode13(padapter, LedAction); + break; + + case SW_LED_MODE14: + SwLedControlMode14(padapter, LedAction); + break; + + case SW_LED_MODE15: + SwLedControlMode15(padapter, LedAction); + break; + + default: + break; + } + + RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("LedStrategy:%d, LedAction %d\n", ledpriv->LedStrategy,LedAction)); +} + +// +// Description: +// Reset status of LED_871x object. +// +void ResetLedStatus(PLED_USB pLed) { + + pLed->CurrLedState = RTW_LED_OFF; // Current LED state. + pLed->bLedOn = _FALSE; // true if LED is ON, false if LED is OFF. + + pLed->bLedBlinkInProgress = _FALSE; // true if it is blinking, false o.w.. + pLed->bLedWPSBlinkInProgress = _FALSE; + + pLed->BlinkTimes = 0; // Number of times to toggle led state for blinking. + pLed->BlinkCounter = 0; + pLed->BlinkingLedState = LED_UNKNOWN; // Next state for blinking, either RTW_LED_ON or RTW_LED_OFF are. + + pLed->bLedNoLinkBlinkInProgress = _FALSE; + pLed->bLedLinkBlinkInProgress = _FALSE; + pLed->bLedStartToLinkBlinkInProgress = _FALSE; + pLed->bLedScanBlinkInProgress = _FALSE; +} + + // +// Description: +// Initialize an LED_871x object. +// +void +InitLed( + _adapter *padapter, + PLED_USB pLed, + LED_PIN LedPin + ) +{ + pLed->padapter = padapter; + pLed->LedPin = LedPin; + + ResetLedStatus(pLed); + _init_timer(&(pLed->BlinkTimer), padapter->pnetdev, BlinkTimerCallback, pLed); + _init_workitem(&(pLed->BlinkWorkItem), BlinkWorkItemCallback, pLed); +} + + +// +// Description: +// DeInitialize an LED_871x object. +// +void +DeInitLed( + PLED_USB pLed + ) +{ + _cancel_workitem_sync(&(pLed->BlinkWorkItem)); + _cancel_timer_ex(&(pLed->BlinkTimer)); + ResetLedStatus(pLed); +} + + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halhwimg.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halhwimg.h new file mode 100644 index 000000000..a8963e033 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halhwimg.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#pragma once +#ifndef __INC_HW_IMG_H +#define __INC_HW_IMG_H + +// +// 2011/03/15 MH Add for different IC HW image file selection. code size consideration. +// +#if RT_PLATFORM == PLATFORM_LINUX + + #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + // For 92C + #define RTL8192CE_HWIMG_SUPPORT 1 + #define RTL8192CE_TEST_HWIMG_SUPPORT 0 + #define RTL8192CU_HWIMG_SUPPORT 0 + #define RTL8192CU_TEST_HWIMG_SUPPORT 0 + + // For 92D + #define RTL8192DE_HWIMG_SUPPORT 1 + #define RTL8192DE_TEST_HWIMG_SUPPORT 0 + #define RTL8192DU_HWIMG_SUPPORT 0 + #define RTL8192DU_TEST_HWIMG_SUPPORT 0 + + // For 8723 + #define RTL8723E_HWIMG_SUPPORT 1 + #define RTL8723U_HWIMG_SUPPORT 0 + #define RTL8723S_HWIMG_SUPPORT 0 + + //For 88E + #define RTL8188EE_HWIMG_SUPPORT 0 + #define RTL8188EU_HWIMG_SUPPORT 0 + #define RTL8188ES_HWIMG_SUPPORT 0 + + #elif (DEV_BUS_TYPE == RT_USB_INTERFACE) + // For 92C + #define RTL8192CE_HWIMG_SUPPORT 0 + #define RTL8192CE_TEST_HWIMG_SUPPORT 0 + #define RTL8192CU_HWIMG_SUPPORT 1 + #define RTL8192CU_TEST_HWIMG_SUPPORT 0 + + //For 92D + #define RTL8192DE_HWIMG_SUPPORT 0 + #define RTL8192DE_TEST_HWIMG_SUPPORT 0 + #define RTL8192DU_HWIMG_SUPPORT 1 + #define RTL8192DU_TEST_HWIMG_SUPPORT 0 + + // For 8723 + #define RTL8723E_HWIMG_SUPPORT 0 + #define RTL8723U_HWIMG_SUPPORT 1 + #define RTL8723S_HWIMG_SUPPORT 0 + + //For 88E + #define RTL8188EE_HWIMG_SUPPORT 0 + #define RTL8188EU_HWIMG_SUPPORT 0 + #define RTL8188ES_HWIMG_SUPPORT 0 + + #elif (DEV_BUS_TYPE == RT_SDIO_INTERFACE) + // For 92C + #define RTL8192CE_HWIMG_SUPPORT 0 + #define RTL8192CE_TEST_HWIMG_SUPPORT 0 + #define RTL8192CU_HWIMG_SUPPORT 1 + #define RTL8192CU_TEST_HWIMG_SUPPORT 0 + + //For 92D + #define RTL8192DE_HWIMG_SUPPORT 0 + #define RTL8192DE_TEST_HWIMG_SUPPORT 0 + #define RTL8192DU_HWIMG_SUPPORT 1 + #define RTL8192DU_TEST_HWIMG_SUPPORT 0 + + // For 8723 + #define RTL8723E_HWIMG_SUPPORT 0 + #define RTL8723U_HWIMG_SUPPORT 0 + #define RTL8723S_HWIMG_SUPPORT 1 + + //For 88E + #define RTL8188EE_HWIMG_SUPPORT 0 + #define RTL8188EU_HWIMG_SUPPORT 0 + #define RTL8188ES_HWIMG_SUPPORT 0 + #endif + +#else // PLATFORM_WINDOWS & MacOSX + +//For 92C +#define RTL8192CE_HWIMG_SUPPORT 1 +#define RTL8192CE_TEST_HWIMG_SUPPORT 1 +#define RTL8192CU_HWIMG_SUPPORT 1 +#define RTL8192CU_TEST_HWIMG_SUPPORT 1 + +// For 92D +#define RTL8192DE_HWIMG_SUPPORT 1 +#define RTL8192DE_TEST_HWIMG_SUPPORT 1 +#define RTL8192DU_HWIMG_SUPPORT 1 +#define RTL8192DU_TEST_HWIMG_SUPPORT 1 + + #if defined(UNDER_CE) + // For 8723 + #define RTL8723E_HWIMG_SUPPORT 0 + #define RTL8723U_HWIMG_SUPPORT 0 + #define RTL8723S_HWIMG_SUPPORT 1 + + // For 88E + #define RTL8188EE_HWIMG_SUPPORT 0 + #define RTL8188EU_HWIMG_SUPPORT 0 + #define RTL8188ES_HWIMG_SUPPORT 0 + + #else + + // For 8723 + #define RTL8723E_HWIMG_SUPPORT 1 + //#define RTL_8723E_TEST_HWIMG_SUPPORT 1 + #define RTL8723U_HWIMG_SUPPORT 1 + //#define RTL_8723U_TEST_HWIMG_SUPPORT 1 + #define RTL8723S_HWIMG_SUPPORT 1 + //#define RTL_8723S_TEST_HWIMG_SUPPORT 1 + + //For 88E + #define RTL8188EE_HWIMG_SUPPORT 1 + #define RTL8188EU_HWIMG_SUPPORT 1 + #define RTL8188ES_HWIMG_SUPPORT 1 + #endif + +#endif + +#endif //__INC_HW_IMG_H diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halphyrf_ap.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halphyrf_ap.c new file mode 100644 index 000000000..142fef12e --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halphyrf_ap.c @@ -0,0 +1,2504 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + #include "mp_precomp.h" + #include "phydm_precomp.h" + +#ifndef index_mapping_NUM_88E + #define index_mapping_NUM_88E 15 +#endif + +//#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + +#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _deltaThermal) \ + do {\ + for(_offset = 0; _offset < _size; _offset++)\ + {\ + if(_deltaThermal < thermalThreshold[_direction][_offset])\ + {\ + if(_offset != 0)\ + _offset--;\ + break;\ + }\ + } \ + if(_offset >= _size)\ + _offset = _size-1;\ + } while(0) + + +void ConfigureTxpowerTrack( + IN PVOID pDM_VOID, + OUT PTXPWRTRACK_CFG pConfig + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if RTL8812A_SUPPORT +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + //if (IS_HARDWARE_TYPE_8812(pDM_Odm->Adapter)) + if(pDM_Odm->SupportICType==ODM_RTL8812) + ConfigureTxpowerTrack_8812A(pConfig); + //else +#endif +#endif + +#if RTL8814A_SUPPORT + if(pDM_Odm->SupportICType== ODM_RTL8814A) + ConfigureTxpowerTrack_8814A(pConfig); +#endif + + +#if RTL8188E_SUPPORT + if(pDM_Odm->SupportICType==ODM_RTL8188E) + ConfigureTxpowerTrack_8188E(pConfig); +#endif +} + +#if (RTL8192E_SUPPORT==1) +VOID +ODM_TXPowerTrackingCallback_ThermalMeter_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PVOID pDM_VOID +#else + IN PADAPTER Adapter +#endif + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte ThermalValue = 0, delta, delta_IQK, delta_LCK, channel, is_decrease, rf_mimo_mode; + u1Byte ThermalValue_AVG_count = 0; + u1Byte OFDM_min_index = 10; //OFDM BB Swing should be less than +2.5dB, which is required by Arthur + s1Byte OFDM_index[2], index ; + u4Byte ThermalValue_AVG = 0, Reg0x18; + u4Byte i = 0, j = 0, rf; + s4Byte value32, CCK_index = 0, ele_A, ele_D, ele_C, X, Y; + prtl8192cd_priv priv = pDM_Odm->priv; + + rf_mimo_mode = pDM_Odm->RFType; + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("%s:%d rf_mimo_mode:%d\n", __FUNCTION__, __LINE__, rf_mimo_mode)); + +#ifdef MP_TEST + if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) { + channel = priv->pshare->working_channel; + if (priv->pshare->mp_txpwr_tracking == FALSE) + return; + } else +#endif + { + channel = (priv->pmib->dot11RFEntry.dot11channel); + } + + ThermalValue = (unsigned char)ODM_GetRFReg(pDM_Odm, RF_PATH_A, ODM_RF_T_METER_92E, 0xfc00); //0x42: RF Reg[15:10] 88E + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther)); + + + switch (rf_mimo_mode) { + case MIMO_1T1R: + rf = 1; + break; + case MIMO_2T2R: + rf = 2; + break; + default: + rf = 2; + break; + } + + //Query OFDM path A default setting Bit[31:21] + ele_D = PHY_QueryBBReg(priv, rOFDM0_XATxIQImbalance, bMaskOFDM_D); + for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) { + if (ele_D == (OFDMSwingTable_92E[i] >> 22)) { + OFDM_index[0] = (unsigned char)i; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("PathA 0xC80[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[0])); + break; + } + } + + //Query OFDM path B default setting + if (rf_mimo_mode == MIMO_2T2R) { + ele_D = PHY_QueryBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskOFDM_D); + for (i = 0; i < OFDM_TABLE_SIZE_92E; i++) { + if (ele_D == (OFDMSwingTable_92E[i] >> 22)) { + OFDM_index[1] = (unsigned char)i; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("PathB 0xC88[31:22] = 0x%x, OFDM_index=%d\n", ele_D, OFDM_index[1])); + break; + } + } + } + + /* calculate average thermal meter */ + { + priv->pshare->ThermalValue_AVG_88XX[priv->pshare->ThermalValue_AVG_index_88XX] = ThermalValue; + priv->pshare->ThermalValue_AVG_index_88XX++; + if (priv->pshare->ThermalValue_AVG_index_88XX == AVG_THERMAL_NUM_88XX) + priv->pshare->ThermalValue_AVG_index_88XX = 0; + + for (i = 0; i < AVG_THERMAL_NUM_88XX; i++) { + if (priv->pshare->ThermalValue_AVG_88XX[i]) { + ThermalValue_AVG += priv->pshare->ThermalValue_AVG_88XX[i]; + ThermalValue_AVG_count++; + } + } + + if (ThermalValue_AVG_count) { + ThermalValue = (unsigned char)(ThermalValue_AVG / ThermalValue_AVG_count); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("AVG Thermal Meter = 0x%x \n", ThermalValue)); + } + } + + /* Initialize */ + if (!priv->pshare->ThermalValue) { + priv->pshare->ThermalValue = priv->pmib->dot11RFEntry.ther; + priv->pshare->ThermalValue_IQK = ThermalValue; + priv->pshare->ThermalValue_LCK = ThermalValue; + } + + if (ThermalValue != priv->pshare->ThermalValue) { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\n******** START POWER TRACKING ********\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther)); + + delta = RTL_ABS(ThermalValue, priv->pmib->dot11RFEntry.ther); + delta_IQK = RTL_ABS(ThermalValue, priv->pshare->ThermalValue_IQK); + delta_LCK = RTL_ABS(ThermalValue, priv->pshare->ThermalValue_LCK); + is_decrease = ((ThermalValue < priv->pmib->dot11RFEntry.ther) ? 1 : 0); + +#ifdef _TRACKING_TABLE_FILE + if (priv->pshare->rf_ft_var.pwr_track_file) { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Diff: (%s)%d ==> get index from table : %d)\n", (is_decrease?"-":"+"), delta, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0))); + + if (is_decrease) { + for (i = 0; i < rf; i++) { + OFDM_index[i] = priv->pshare->OFDM_index0[i] + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0); + OFDM_index[i] = ((OFDM_index[i] > (OFDM_TABLE_SIZE_92E- 1)) ? (OFDM_TABLE_SIZE_92E - 1) : OFDM_index[i]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0))); + CCK_index = priv->pshare->CCK_index0 + get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1); + CCK_index = ((CCK_index > (CCK_TABLE_SIZE_92E - 1)) ? (CCK_TABLE_SIZE_92E - 1) : CCK_index); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> Decrese power ---> new CCK_INDEX:%d (%d + %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1))); + } + } else { + for (i = 0; i < rf; i++) { + OFDM_index[i] = priv->pshare->OFDM_index0[i] - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0); + OFDM_index[i] = ((OFDM_index[i] < OFDM_min_index) ? OFDM_min_index : OFDM_index[i]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> Increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[i], priv->pshare->OFDM_index0[i], get_tx_tracking_index(priv, channel, i, delta, is_decrease, 0))); + CCK_index = priv->pshare->CCK_index0 - get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1); + CCK_index = ((CCK_index < 0 )? 0 : CCK_index); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> Increse power ---> new CCK_INDEX:%d (%d - %d)\n", CCK_index, priv->pshare->CCK_index0, get_tx_tracking_index(priv, channel, i, delta, is_decrease, 1))); + } + } + } +#endif //CFG_TRACKING_TABLE_FILE + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("OFDMSwingTable_92E[(unsigned int)OFDM_index[0]] = %x \n",OFDMSwingTable_92E[(unsigned int)OFDM_index[0]])); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("OFDMSwingTable_92E[(unsigned int)OFDM_index[1]] = %x \n",OFDMSwingTable_92E[(unsigned int)OFDM_index[1]])); + + //Adujst OFDM Ant_A according to IQK result + ele_D = (OFDMSwingTable_92E[(unsigned int)OFDM_index[0]] & 0xFFC00000) >> 22; + X = priv->pshare->RegE94; + Y = priv->pshare->RegE9C; + + if (X != 0) { + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + ele_A = ((X * ele_D) >> 8) & 0x000003FF; + + //new element C = element D x Y + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + ele_C = ((Y * ele_D) >> 8) & 0x000003FF; + + //wirte new elements A, C, D to regC80 and regC94, element B is always 0 + value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; + PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C&0x000003C0)>>6; + PHY_SetBBReg(priv, rOFDM0_XCTxAFE, bMaskH4Bits, value32); + + value32 = ((X * ele_D)>>7)&0x01; + PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(24), value32); + } else { + PHY_SetBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_92E[(unsigned int)OFDM_index[0]]); + PHY_SetBBReg(priv, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); + PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(24), 0x00); + } + + set_CCK_swing_index(priv, CCK_index); + + if (rf == 2) { + ele_D = (OFDMSwingTable_92E[(unsigned int)OFDM_index[1]] & 0xFFC00000) >> 22; + X = priv->pshare->RegEB4; + Y = priv->pshare->RegEBC; + + if (X != 0) { + if ((X & 0x00000200) != 0) //consider minus + X = X | 0xFFFFFC00; + ele_A = ((X * ele_D) >> 8) & 0x000003FF; + + //new element C = element D x Y + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + ele_C = ((Y * ele_D) >> 8) & 0x00003FF; + + //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 + value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; + PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C & 0x000003C0) >> 6; + PHY_SetBBReg(priv, rOFDM0_XDTxAFE, bMaskH4Bits, value32); + + value32 = ((X * ele_D) >> 7) & 0x01; + PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(28), value32); + } else { + PHY_SetBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_92E[(unsigned int)OFDM_index[1]]); + PHY_SetBBReg(priv, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); + PHY_SetBBReg(priv, rOFDM0_ECCAThreshold, BIT(28), 0x00); + } + + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("0xc80 = 0x%x \n", PHY_QueryBBReg(priv, rOFDM0_XATxIQImbalance, bMaskDWord))); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("0xc88 = 0x%x \n", PHY_QueryBBReg(priv, rOFDM0_XBTxIQImbalance, bMaskDWord))); + + if (delta_IQK > 3) { + priv->pshare->ThermalValue_IQK = ThermalValue; +#ifdef MP_TEST + if (!(priv->pshare->rf_ft_var.mp_specific && (OPMODE & (WIFI_MP_CTX_BACKGROUND | WIFI_MP_CTX_PACKET)))) +#endif + PHY_IQCalibrate_8192E(pDM_Odm,false); + } + + if (delta_LCK > 8) { + RTL_W8(0x522, 0xff); + Reg0x18 = PHY_QueryRFReg(priv, RF_PATH_A, 0x18, bMask20Bits, 1); + PHY_SetRFReg(priv, RF_PATH_A, 0xB4, BIT(14), 1); + PHY_SetRFReg(priv, RF_PATH_A, 0x18, BIT(15), 1); + delay_ms(1); + PHY_SetRFReg(priv, RF_PATH_A, 0xB4, BIT(14), 0); + PHY_SetRFReg(priv, RF_PATH_A, 0x18, bMask20Bits, Reg0x18); + RTL_W8(0x522, 0x0); + priv->pshare->ThermalValue_LCK = ThermalValue; + } + } + + //update thermal meter value + priv->pshare->ThermalValue = ThermalValue; + for (i = 0 ; i < rf ; i++) + priv->pshare->OFDM_index[i] = OFDM_index[i]; + priv->pshare->CCK_index = CCK_index; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("\n******** END:%s() ********\n", __FUNCTION__)); +} +#endif + +#if (RTL8814A_SUPPORT ==1) + +VOID +ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries2( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PVOID pDM_VOID +#else + IN PADAPTER Adapter +#endif + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, channel, is_increase; + u1Byte ThermalValue_AVG_count = 0, p = 0, i = 0; + u4Byte ThermalValue_AVG = 0, Reg0x18; + u4Byte BBSwingReg[4] = {rA_TxScale_Jaguar,rB_TxScale_Jaguar,rC_TxScale_Jaguar2,rD_TxScale_Jaguar2}; + s4Byte ele_D; + u4Byte BBswingIdx; + prtl8192cd_priv priv = pDM_Odm->priv; + TXPWRTRACK_CFG c; + BOOLEAN bTSSIenable = FALSE; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + //4 1. The following TWO tables decide the final index of OFDM/CCK swing table. + pu1Byte deltaSwingTableIdx_TUP_A = NULL, deltaSwingTableIdx_TDOWN_A = NULL; + pu1Byte deltaSwingTableIdx_TUP_B = NULL, deltaSwingTableIdx_TDOWN_B = NULL; + //for 8814 add by Yu Chen + pu1Byte deltaSwingTableIdx_TUP_C = NULL, deltaSwingTableIdx_TDOWN_C = NULL; + pu1Byte deltaSwingTableIdx_TUP_D = NULL, deltaSwingTableIdx_TDOWN_D = NULL; + +#ifdef MP_TEST + if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) { + channel = priv->pshare->working_channel; + if (priv->pshare->mp_txpwr_tracking == FALSE) + return; + } else +#endif + { + channel = (priv->pmib->dot11RFEntry.dot11channel); + } + + ConfigureTxpowerTrack(pDM_Odm, &c); + pRFCalibrateInfo->DefaultOfdmIndex = priv->pshare->OFDM_index0[ODM_RF_PATH_A]; + + (*c.GetDeltaSwingTable)(pDM_Odm, (pu1Byte*)&deltaSwingTableIdx_TUP_A, (pu1Byte*)&deltaSwingTableIdx_TDOWN_A, + (pu1Byte*)&deltaSwingTableIdx_TUP_B, (pu1Byte*)&deltaSwingTableIdx_TDOWN_B); + + if(pDM_Odm->SupportICType & ODM_RTL8814A) // for 8814 path C & D + (*c.GetDeltaSwingTable8814only)(pDM_Odm, (pu1Byte*)&deltaSwingTableIdx_TUP_C, (pu1Byte*)&deltaSwingTableIdx_TDOWN_C, + (pu1Byte*)&deltaSwingTableIdx_TUP_D, (pu1Byte*)&deltaSwingTableIdx_TDOWN_D); + + ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, c.ThermalRegAddr, 0xfc00); //0x42: RF Reg[15:10] 88E + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("\nReadback Thermal Meter = 0x%x, pre thermal meter 0x%x, EEPROMthermalmeter 0x%x\n", ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue, priv->pmib->dot11RFEntry.ther)); + + /* Initialize */ + if (!pDM_Odm->RFCalibrateInfo.ThermalValue) { + pDM_Odm->RFCalibrateInfo.ThermalValue = priv->pmib->dot11RFEntry.ther; + } + + if (!pDM_Odm->RFCalibrateInfo.ThermalValue_LCK) { + pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = priv->pmib->dot11RFEntry.ther; + } + + if (!pDM_Odm->RFCalibrateInfo.ThermalValue_IQK) { + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = priv->pmib->dot11RFEntry.ther; + } + + bTSSIenable = (BOOLEAN)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, rRF_TxGainOffset, BIT7); // check TSSI enable + + //4 Query OFDM BB swing default setting Bit[31:21] + for(p = ODM_RF_PATH_A ; p < c.RfPathCount ; p++) + { + ele_D = ODM_GetBBReg(pDM_Odm, BBSwingReg[p], 0xffe00000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("0x%x:0x%x ([31:21] = 0x%x)\n", BBSwingReg[p], ODM_GetBBReg(pDM_Odm, BBSwingReg[p], bMaskDWord), ele_D)); + + for (BBswingIdx = 0; BBswingIdx < TXSCALE_TABLE_SIZE; BBswingIdx++) {//4 + if (ele_D == TxScalingTable_Jaguar[BBswingIdx]) { + pDM_Odm->RFCalibrateInfo.OFDM_index[p] = (u1Byte)BBswingIdx; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("OFDM_index[%d]=%d\n",p, pDM_Odm->RFCalibrateInfo.OFDM_index[p])); + break; + } + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("KfreeOffset[%d]=%d\n",p, pRFCalibrateInfo->KfreeOffset[p])); + + } + + /* calculate average thermal meter */ + pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index] = ThermalValue; + pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index++; + if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index == c.AverageThermalNum) //Average times = c.AverageThermalNum + pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index = 0; + + for(i = 0; i < c.AverageThermalNum; i++) + { + if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]) + { + ThermalValue_AVG += pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]; + ThermalValue_AVG_count++; + } + } + + if(ThermalValue_AVG_count) //Calculate Average ThermalValue after average enough times + { + ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("AVG Thermal Meter = 0x%X, EEPROMthermalmeter = 0x%X\n", ThermalValue, priv->pmib->dot11RFEntry.ther)); + } + + //4 Calculate delta, delta_LCK, delta_IQK. + delta = RTL_ABS(ThermalValue, priv->pmib->dot11RFEntry.ther); + delta_LCK = RTL_ABS(ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue_LCK); + delta_IQK = RTL_ABS(ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue_IQK); + is_increase = ((ThermalValue < priv->pmib->dot11RFEntry.ther) ? 0 : 1); + + //4 if necessary, do LCK. + if (!(pDM_Odm->SupportICType & ODM_RTL8821)) { + if (delta_LCK > c.Threshold_IQK) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= Threshold_IQK(%d)\n", delta_LCK, c.Threshold_IQK)); + pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue; + if (c.PHY_LCCalibrate) + (*c.PHY_LCCalibrate)(pDM_Odm); + } + } + + if (delta_IQK > c.Threshold_IQK) + { + panic_printk("%s(%d)\n", __FUNCTION__, __LINE__); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_IQK(%d) >= Threshold_IQK(%d)\n", delta_IQK, c.Threshold_IQK)); + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; + if(c.DoIQK) + (*c.DoIQK)(pDM_Odm, TRUE, 0, 0); + } + + if(!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/ + return; + + //4 Do Power Tracking + + if(bTSSIenable == TRUE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("**********Enter PURE TSSI MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, TSSI_MODE, p, 0); + } + else if (ThermalValue != pDM_Odm->RFCalibrateInfo.ThermalValue) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("\n******** START POWER TRACKING ********\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue, priv->pmib->dot11RFEntry.ther)); + +#ifdef _TRACKING_TABLE_FILE + if (priv->pshare->rf_ft_var.pwr_track_file) + { + if (is_increase) // thermal is higher than base + { + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + { + switch(p) + { + case ODM_RF_PATH_B: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_B[%d] = %d\n", delta, deltaSwingTableIdx_TUP_B[delta])); + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_B[delta]; // Record delta swing for mix mode power tracking + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + case ODM_RF_PATH_C: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_C[%d] = %d\n", delta, deltaSwingTableIdx_TUP_C[delta])); + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_C[delta]; // Record delta swing for mix mode power tracking + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + case ODM_RF_PATH_D: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_D[%d] = %d\n", delta, deltaSwingTableIdx_TUP_D[delta])); + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_D[delta]; // Record delta swing for mix mode power tracking + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_A[%d] = %d\n", delta, deltaSwingTableIdx_TUP_A[delta])); + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_A[delta]; // Record delta swing for mix mode power tracking + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + } + } + } + else // thermal is lower than base + { + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + { + switch(p) + { + case ODM_RF_PATH_B: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_B[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_B[delta])); + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; // Record delta swing for mix mode power tracking + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + case ODM_RF_PATH_C: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_C[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_C[delta])); + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; // Record delta swing for mix mode power tracking + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + case ODM_RF_PATH_D: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_D[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_D[delta])); + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; // Record delta swing for mix mode power tracking + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_A[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_A[delta])); + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; // Record delta swing for mix mode power tracking + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + } + } + } + + if (is_increase) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> increse power ---> \n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> decrese power --->\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); + } + } +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\n******** END:%s() ********\n", __FUNCTION__)); + //update thermal meter value + pDM_Odm->RFCalibrateInfo.ThermalValue = ThermalValue; + + } +} + +#elif(ODM_IC_11AC_SERIES_SUPPORT) +VOID +ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PVOID pDM_VOID +#else + IN PADAPTER Adapter +#endif + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + unsigned char ThermalValue = 0, delta, delta_LCK, channel, is_decrease; + unsigned char ThermalValue_AVG_count = 0; + unsigned int ThermalValue_AVG = 0, Reg0x18; + unsigned int BBSwingReg[4]={0xc1c,0xe1c,0x181c,0x1a1c}; + int ele_D, value32; + char OFDM_index[2], index; + unsigned int i = 0, j = 0, rf_path, max_rf_path =2 ,rf; + prtl8192cd_priv priv = pDM_Odm->priv; + unsigned char OFDM_min_index = 7; //OFDM BB Swing should be less than +2.5dB, which is required by Arthur and Mimic + +#ifdef MP_TEST + if ((OPMODE & WIFI_MP_STATE) || priv->pshare->rf_ft_var.mp_specific) { + channel = priv->pshare->working_channel; + if (priv->pshare->mp_txpwr_tracking == FALSE) + return; + } else +#endif + { + channel = (priv->pmib->dot11RFEntry.dot11channel); + } + +#if RTL8881A_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8881A) { + max_rf_path = 1; + if ((get_bonding_type_8881A() == BOND_8881AM ||get_bonding_type_8881A() == BOND_8881AN) + && priv->pshare->rf_ft_var.use_intpa8881A && (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G)) + OFDM_min_index = 6; // intPA - upper bond set to +3 dB (base: -2 dB)ot11RFEntry.phyBandSelect == PHY_BAND_2G)) + else + OFDM_min_index = 10; //OFDM BB Swing should be less than +1dB, which is required by Arthur and Mimic + } +#endif + + + ThermalValue = (unsigned char)PHY_QueryRFReg(priv, RF_PATH_A, 0x42, 0xfc00, 1); //0x42: RF Reg[15:10] 88E + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther)); + + + //4 Query OFDM BB swing default setting Bit[31:21] + for(rf_path = 0 ; rf_path < max_rf_path ; rf_path++){ + ele_D = PHY_QueryBBReg(priv, BBSwingReg[rf_path], 0xffe00000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("0x%x:0x%x ([31:21] = 0x%x)\n",BBSwingReg[rf_path], PHY_QueryBBReg(priv, BBSwingReg[rf_path], bMaskDWord),ele_D)); + for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {//4 + if (ele_D == OFDMSwingTable_8812[i]) { + OFDM_index[rf_path] = (unsigned char)i; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("OFDM_index[%d]=%d\n",rf_path, OFDM_index[rf_path])); + break; + } + } + } +#if 0 + //Query OFDM path A default setting Bit[31:21] + ele_D = PHY_QueryBBReg(priv, 0xc1c, 0xffe00000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("0xc1c:0x%x ([31:21] = 0x%x)\n", PHY_QueryBBReg(priv, 0xc1c, bMaskDWord),ele_D)); + for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) {//4 + if (ele_D == OFDMSwingTable_8812[i]) { + OFDM_index[0] = (unsigned char)i; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("OFDM_index[0]=%d\n", OFDM_index[0])); + break; + } + } + //Query OFDM path B default setting + if (rf == 2) { + ele_D = PHY_QueryBBReg(priv, 0xe1c, 0xffe00000); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("0xe1c:0x%x ([32:21] = 0x%x)\n", PHY_QueryBBReg(priv, 0xe1c, bMaskDWord),ele_D)); + for (i = 0; i < OFDM_TABLE_SIZE_8812; i++) { + if (ele_D == OFDMSwingTable_8812[i]) { + OFDM_index[1] = (unsigned char)i; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("OFDM_index[1]=%d\n", OFDM_index[1])); + break; + } + } + } +#endif + /* Initialize */ + if (!priv->pshare->ThermalValue) { + priv->pshare->ThermalValue = priv->pmib->dot11RFEntry.ther; + priv->pshare->ThermalValue_LCK = ThermalValue; + } + + /* calculate average thermal meter */ + { + priv->pshare->ThermalValue_AVG_8812[priv->pshare->ThermalValue_AVG_index_8812] = ThermalValue; + priv->pshare->ThermalValue_AVG_index_8812++; + if (priv->pshare->ThermalValue_AVG_index_8812 == AVG_THERMAL_NUM_8812) + priv->pshare->ThermalValue_AVG_index_8812 = 0; + + for (i = 0; i < AVG_THERMAL_NUM_8812; i++) { + if (priv->pshare->ThermalValue_AVG_8812[i]) { + ThermalValue_AVG += priv->pshare->ThermalValue_AVG_8812[i]; + ThermalValue_AVG_count++; + } + } + + if (ThermalValue_AVG_count) { + ThermalValue = (unsigned char)(ThermalValue_AVG / ThermalValue_AVG_count); + //printk("AVG Thermal Meter = 0x%x \n", ThermalValue); + } + } + + + //4 If necessary, do power tracking + + if(!priv->pmib->dot11RFEntry.ther) /*Don't do power tracking since no calibrated thermal value*/ + return; + + if (ThermalValue != priv->pshare->ThermalValue) { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\n******** START POWER TRACKING ********\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n", ThermalValue, priv->pshare->ThermalValue, priv->pmib->dot11RFEntry.ther)); + delta = RTL_ABS(ThermalValue, priv->pmib->dot11RFEntry.ther); + delta_LCK = RTL_ABS(ThermalValue, priv->pshare->ThermalValue_LCK); + is_decrease = ((ThermalValue < priv->pmib->dot11RFEntry.ther) ? 1 : 0); + //if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) + { +#ifdef _TRACKING_TABLE_FILE + if (priv->pshare->rf_ft_var.pwr_track_file) { + for (rf_path = 0; rf_path < max_rf_path; rf_path++) { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Diff: (%s)%d ==> get index from table : %d)\n", (is_decrease?"-":"+"), delta, get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0))); + if (is_decrease) { + OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] + get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0); + OFDM_index[rf_path] = ((OFDM_index[rf_path] > (OFDM_TABLE_SIZE_8812 - 1)) ? (OFDM_TABLE_SIZE_8812 - 1) : OFDM_index[rf_path]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> decrese power ---> new OFDM_INDEX:%d (%d + %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0))); +#if 0// RTL8881A_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8881A){ + if(priv->pshare->rf_ft_var.pwrtrk_TxAGC_enable){ + if(priv->pshare->AddTxAGC){//TxAGC has been added + AddTxPower88XX_AC(priv,0); + priv->pshare->AddTxAGC = 0; + priv->pshare->AddTxAGC_index = 0; + } + } + } +#endif + } else { + + OFDM_index[rf_path] = priv->pshare->OFDM_index0[rf_path] - get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0); +#if 0// RTL8881A_SUPPORT + if(pDM_Odm->SupportICType == ODM_RTL8881A){ + if(priv->pshare->rf_ft_var.pwrtrk_TxAGC_enable){ + if(OFDM_index[i] < OFDM_min_index){ + priv->pshare->AddTxAGC_index = (OFDM_min_index - OFDM_index[i])/2; // Calculate Remnant TxAGC Value, 2 index for 1 TxAGC + AddTxPower88XX_AC(priv,priv->pshare->AddTxAGC_index); + priv->pshare->AddTxAGC = 1; //AddTxAGC Flag = 1 + OFDM_index[i] = OFDM_min_index; + } + else{ + if(priv->pshare->AddTxAGC){// TxAGC been added + priv->pshare->AddTxAGC = 0; + priv->pshare->AddTxAGC_index = 0; + AddTxPower88XX_AC(priv,0); //minus the added TPI + } + } + } + } +#else + OFDM_index[rf_path] = ((OFDM_index[rf_path] < OFDM_min_index) ? OFDM_min_index : OFDM_index[rf_path]); +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,(">>> increse power ---> new OFDM_INDEX:%d (%d - %d)\n", OFDM_index[rf_path], priv->pshare->OFDM_index0[rf_path], get_tx_tracking_index(priv, channel, rf_path, delta, is_decrease, 0))); + } + } + } +#endif + //4 Set new BB swing index + for (rf_path = 0; rf_path < max_rf_path; rf_path++) { + PHY_SetBBReg(priv, BBSwingReg[rf_path], 0xffe00000, OFDMSwingTable_8812[(unsigned int)OFDM_index[rf_path]]); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Readback 0x%x[31:21] = 0x%x, OFDM_index:%d\n",BBSwingReg[rf_path], PHY_QueryBBReg(priv, BBSwingReg[rf_path], 0xffe00000), OFDM_index[rf_path])); + } + + } + if (delta_LCK > 8) { + RTL_W8(0x522, 0xff); + Reg0x18 = PHY_QueryRFReg(priv, RF_PATH_A, 0x18, bMask20Bits, 1); + PHY_SetRFReg(priv, RF_PATH_A, 0xB4, BIT(14), 1); + PHY_SetRFReg(priv, RF_PATH_A, 0x18, BIT(15), 1); + delay_ms(200); // frequency deviation + PHY_SetRFReg(priv, RF_PATH_A, 0xB4, BIT(14), 0); + PHY_SetRFReg(priv, RF_PATH_A, 0x18, bMask20Bits, Reg0x18); + #ifdef CONFIG_RTL_8812_SUPPORT + if (GET_CHIP_VER(priv)== VERSION_8812E) + UpdateBBRFVal8812(priv, priv->pmib->dot11RFEntry.dot11channel); + #endif + RTL_W8(0x522, 0x0); + priv->pshare->ThermalValue_LCK = ThermalValue; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("\n******** END:%s() ********\n", __FUNCTION__)); + + //update thermal meter value + priv->pshare->ThermalValue = ThermalValue; + for (rf_path = 0; rf_path < max_rf_path; rf_path++) + priv->pshare->OFDM_index[rf_path] = OFDM_index[rf_path]; + } +} + +#endif + + +VOID +ODM_TXPowerTrackingCallback_ThermalMeter( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PVOID pDM_VOID +#else + IN PADAPTER Adapter +#endif + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); +#if (RTL8814A_SUPPORT == 1) //use this function to do power tracking after 8814 by YuChen + if (pDM_Odm->SupportICType & ODM_RTL8814A) { + ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries2(pDM_Odm); + return; + } +#elif ODM_IC_11AC_SERIES_SUPPORT + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries(pDM_Odm); + return; + } +#endif + +#if (RTL8192E_SUPPORT == 1) + if (pDM_Odm->SupportICType==ODM_RTL8192E) { + ODM_TXPowerTrackingCallback_ThermalMeter_92E(pDM_Odm); + return; + } +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + //PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; +#endif + + u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, offset; + u1Byte ThermalValue_AVG_count = 0; + u4Byte ThermalValue_AVG = 0; +// s4Byte ele_A=0, ele_D, TempCCk, X, value32; +// s4Byte Y, ele_C=0; +// s1Byte OFDM_index[2], CCK_index=0, OFDM_index_old[2]={0,0}, CCK_index_old=0, index; +// s1Byte deltaPowerIndex = 0; + u4Byte i = 0;//, j = 0; + BOOLEAN is2T = FALSE; +// BOOLEAN bInteralPA = FALSE; + + u1Byte OFDM_max_index = 34, rf = (is2T) ? 2 : 1; //OFDM BB Swing should be less than +3.0dB, which is required by Arthur + u1Byte Indexforchannel = 0;/*GetRightChnlPlaceforIQK(pHalData->CurrentChannel)*/ + enum _POWER_DEC_INC { POWER_DEC, POWER_INC }; + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #endif + + TXPWRTRACK_CFG c; + + + //4 1. The following TWO tables decide the final index of OFDM/CCK swing table. + s1Byte deltaSwingTableIdx[2][index_mapping_NUM_88E] = { + // {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} + {0,0,2,3,4,4,5,6,7,7,8,9,10,10,11}, {0,0,1,2,3,4,4,4,4,5,7,8,9,9,10} + }; + u1Byte thermalThreshold[2][index_mapping_NUM_88E]={ + // {{Power decreasing(lower temperature)}, {Power increasing(higher temperature)}} + {0,2,4,6,8,10,12,14,16,18,20,22,24,26,27}, {0,2,4,6,8,10,12,14,16,18,20,22,25,25,25} + }; + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + prtl8192cd_priv priv = pDM_Odm->priv; +#endif + + //4 2. Initilization ( 7 steps in total ) + + ConfigureTxpowerTrack(pDM_Odm, &c); + + pDM_Odm->RFCalibrateInfo.TXPowerTrackingCallbackCnt++; //cosa add for debug + pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = TRUE; + +#if (MP_DRIVER == 1) + pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = pHalData->TxPowerTrackControl; // We should keep updating the control variable according to HalData. + // RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files. + pDM_Odm->RFCalibrateInfo.RegA24 = 0x090e1317; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && defined(MP_TEST) + if ((OPMODE & WIFI_MP_STATE) || pDM_Odm->priv->pshare->rf_ft_var.mp_specific) { + if(pDM_Odm->priv->pshare->mp_txpwr_tracking == FALSE) + return; + } +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>odm_TXPowerTrackingCallback_ThermalMeter_8188E, pDM_Odm->BbSwingIdxCckBase: %d, pDM_Odm->BbSwingIdxOfdmBase: %d \n", pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->BbSwingIdxOfdmBase)); +/* + if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) { + ODM_SetRFReg(pDM_Odm, RF_PATH_A, c.ThermalRegAddr, BIT17 | BIT16, 0x3); + pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; + return; + } +*/ + ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, RF_PATH_A, c.ThermalRegAddr, 0xfc00); //0x42: RF Reg[15:10] 88E +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if( ! ThermalValue || ! pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) +#else + if( ! pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) +#endif + return; + + //4 3. Initialize ThermalValues of RFCalibrateInfo + + if( ! pDM_Odm->RFCalibrateInfo.ThermalValue) + { + pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue; + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; + } + + if(pDM_Odm->RFCalibrateInfo.bReloadtxpowerindex) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("reload ofdm index for band switch\n")); + } + + //4 4. Calculate average thermal meter + + pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index] = ThermalValue; + pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index++; + if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index == c.AverageThermalNum) + pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index = 0; + + for(i = 0; i < c.AverageThermalNum; i++) + { + if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]) + { + ThermalValue_AVG += pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]; + ThermalValue_AVG_count++; + } + } + + if(ThermalValue_AVG_count) + { + // Give the new thermo value a weighting + ThermalValue_AVG += (ThermalValue*4); + + ThermalValue = (u1Byte)(ThermalValue_AVG / (ThermalValue_AVG_count+4)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("AVG Thermal Meter = 0x%x \n", ThermalValue)); + } + + //4 5. Calculate delta, delta_LCK, delta_IQK. + + delta = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue):(pDM_Odm->RFCalibrateInfo.ThermalValue - ThermalValue); + delta_LCK = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_LCK)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_LCK):(pDM_Odm->RFCalibrateInfo.ThermalValue_LCK - ThermalValue); + delta_IQK = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_IQK)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK):(pDM_Odm->RFCalibrateInfo.ThermalValue_IQK - ThermalValue); + + //4 6. If necessary, do LCK. + if (!(pDM_Odm->SupportICType & ODM_RTL8821)) { + /*if((delta_LCK > pHalData->Delta_LCK) && (pHalData->Delta_LCK != 0))*/ + if (delta_LCK >= c.Threshold_IQK) { + /*Delta temperature is equal to or larger than 20 centigrade.*/ + pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue; + (*c.PHY_LCCalibrate)(pDM_Odm); + } + } + + //3 7. If necessary, move the index of swing table to adjust Tx power. + + if (delta > 0 && pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) + { +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue); +#else + delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - pDM_Odm->priv->pmib->dot11RFEntry.ther):(pDM_Odm->priv->pmib->dot11RFEntry.ther - ThermalValue); +#endif + + + //4 7.1 The Final Power Index = BaseIndex + PowerIndexOffset + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if(ThermalValue > pHalData->EEPROMThermalMeter) { +#else + if(ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) { +#endif + CALCULATE_SWINGTALBE_OFFSET(offset, POWER_INC, index_mapping_NUM_88E, delta); + pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex; + pDM_Odm->RFCalibrateInfo.DeltaPowerIndex = deltaSwingTableIdx[POWER_INC][offset]; + + } else { + + CALCULATE_SWINGTALBE_OFFSET(offset, POWER_DEC, index_mapping_NUM_88E, delta); + pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex; + pDM_Odm->RFCalibrateInfo.DeltaPowerIndex = (-1)*deltaSwingTableIdx[POWER_DEC][offset]; + } + + if (pDM_Odm->RFCalibrateInfo.DeltaPowerIndex == pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast) + pDM_Odm->RFCalibrateInfo.PowerIndexOffset = 0; + else + pDM_Odm->RFCalibrateInfo.PowerIndexOffset = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex - pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast; + + for(i = 0; i < rf; i++) + pDM_Odm->RFCalibrateInfo.OFDM_index[i] = pRFCalibrateInfo->BbSwingIdxOfdmBase + pDM_Odm->RFCalibrateInfo.PowerIndexOffset; + pDM_Odm->RFCalibrateInfo.CCK_index = pRFCalibrateInfo->BbSwingIdxCckBase + pDM_Odm->RFCalibrateInfo.PowerIndexOffset; + + pRFCalibrateInfo->BbSwingIdxCck = pDM_Odm->RFCalibrateInfo.CCK_index; + pRFCalibrateInfo->BbSwingIdxOfdm[RF_PATH_A] = pDM_Odm->RFCalibrateInfo.OFDM_index[RF_PATH_A]; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxCck, pRFCalibrateInfo->BbSwingIdxCckBase, pDM_Odm->RFCalibrateInfo.PowerIndexOffset)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("The 'OFDM' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxOfdm[RF_PATH_A], pRFCalibrateInfo->BbSwingIdxOfdmBase, pDM_Odm->RFCalibrateInfo.PowerIndexOffset)); + + //4 7.1 Handle boundary conditions of index. + + + for(i = 0; i < rf; i++) + { + if(pDM_Odm->RFCalibrateInfo.OFDM_index[i] > OFDM_max_index) + { + pDM_Odm->RFCalibrateInfo.OFDM_index[i] = OFDM_max_index; + } + else if (pDM_Odm->RFCalibrateInfo.OFDM_index[i] < 0) + { + pDM_Odm->RFCalibrateInfo.OFDM_index[i] = 0; + } + } + + if(pDM_Odm->RFCalibrateInfo.CCK_index > c.SwingTableSize_CCK-1) + pDM_Odm->RFCalibrateInfo.CCK_index = c.SwingTableSize_CCK-1; + else if (pDM_Odm->RFCalibrateInfo.CCK_index < 0) + pDM_Odm->RFCalibrateInfo.CCK_index = 0; + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("The thermal meter is unchanged or TxPowerTracking OFF: ThermalValue: %d , pDM_Odm->RFCalibrateInfo.ThermalValue: %d)\n", ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue)); + pDM_Odm->RFCalibrateInfo.PowerIndexOffset = 0; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TxPowerTracking: [CCK] Swing Current Index: %d, Swing Base Index: %d\n", pDM_Odm->RFCalibrateInfo.CCK_index, pRFCalibrateInfo->BbSwingIdxCckBase)); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TxPowerTracking: [OFDM] Swing Current Index: %d, Swing Base Index: %d\n", pDM_Odm->RFCalibrateInfo.OFDM_index[RF_PATH_A], pRFCalibrateInfo->BbSwingIdxOfdmBase)); + + if (pDM_Odm->RFCalibrateInfo.PowerIndexOffset != 0 && pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) + { + //4 7.2 Configure the Swing Table to adjust Tx Power. + + pDM_Odm->RFCalibrateInfo.bTxPowerChanged = TRUE; // Always TRUE after Tx Power is adjusted by power tracking. + // + // 2012/04/23 MH According to Luke's suggestion, we can not write BB digital + // to increase TX power. Otherwise, EVM will be bad. + // + // 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. + if (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue) + { + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + // ("Temperature Increasing: delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + // pDM_Odm->RFCalibrateInfo.PowerIndexOffset, delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue)); + } + else if (ThermalValue < pDM_Odm->RFCalibrateInfo.ThermalValue)// Low temperature + { + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + // ("Temperature Decreasing: delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + // pDM_Odm->RFCalibrateInfo.PowerIndexOffset, delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue)); + } +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (ThermalValue > pHalData->EEPROMThermalMeter) +#else + if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) +#endif + { +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Temperature(%d) hugher than PG value(%d), increases the power by TxAGC\n", ThermalValue, pHalData->EEPROMThermalMeter)); + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, TXAGC, 0, 0); + } + else + { + // ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Temperature(%d) lower than PG value(%d), increases the power by TxAGC\n", ThermalValue, pHalData->EEPROMThermalMeter)); + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, RF_PATH_A, Indexforchannel); + if(is2T) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, RF_PATH_B, Indexforchannel); + } + + pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->BbSwingIdxCck; + pRFCalibrateInfo->BbSwingIdxOfdmBase = pRFCalibrateInfo->BbSwingIdxOfdm[RF_PATH_A]; + pDM_Odm->RFCalibrateInfo.ThermalValue = ThermalValue; + + } + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + // if((delta_IQK > pHalData->Delta_IQK) && (pHalData->Delta_IQK != 0)) + if ((delta_IQK >= 8)) // Delta temperature is equal to or larger than 20 centigrade. + (*c.DoIQK)(pDM_Odm, delta_IQK, ThermalValue, 8); +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("<===dm_TXPowerTrackingCallback_ThermalMeter_8188E\n")); + + pDM_Odm->RFCalibrateInfo.TXPowercount = 0; +} + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + + +VOID +phy_PathAStandBy( + IN PADAPTER pAdapter + ) +{ + RTPRINT(FINIT, INIT_IQK, ("Path-A standby mode!\n")); + + PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x0); + PHY_SetBBReg(pAdapter, 0x840, bMaskDWord, 0x00010000); + PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x808000); +} + +//1 7. IQK +//#define MAX_TOLERANCE 5 +//#define IQK_DELAY_TIME 1 //ms + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathA_IQK_8192C( + IN PADAPTER pAdapter, + IN BOOLEAN configPathB + ) +{ + + u4Byte regEAC, regE94, regE9C, regEA4; + u1Byte result = 0x00; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + RTPRINT(FINIT, INIT_IQK, ("Path A IQK!\n")); + + //path-A IQK setting + RTPRINT(FINIT, INIT_IQK, ("Path-A IQK setting!\n")); + if(pAdapter->interfaceIndex == 0) + { + PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1f); + PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f); + } + else + { + PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x10008c22); + PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x10008c22); + } + + PHY_SetBBReg(pAdapter, rTx_IQK_PI_A, bMaskDWord, 0x82140102); + + PHY_SetBBReg(pAdapter, rRx_IQK_PI_A, bMaskDWord, configPathB ? 0x28160202 : + IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202:0x28160502); + + //path-B IQK setting + if(configPathB) + { + PHY_SetBBReg(pAdapter, rTx_IQK_Tone_B, bMaskDWord, 0x10008c22); + PHY_SetBBReg(pAdapter, rRx_IQK_Tone_B, bMaskDWord, 0x10008c22); + PHY_SetBBReg(pAdapter, rTx_IQK_PI_B, bMaskDWord, 0x82140102); + PHY_SetBBReg(pAdapter, rRx_IQK_PI_B, bMaskDWord, 0x28160202); + } + + //LO calibration setting + RTPRINT(FINIT, INIT_IQK, ("LO calibration setting!\n")); + PHY_SetBBReg(pAdapter, rIQK_AGC_Rsp, bMaskDWord, 0x001028d1); + + //One shot, path A LOK & IQK + RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n")); + PHY_SetBBReg(pAdapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + PHY_SetBBReg(pAdapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms + RTPRINT(FINIT, INIT_IQK, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME)); + PlatformStallExecution(IQK_DELAY_TIME*1000); + + // Check failed + regEAC = PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", regEAC)); + regE94 = PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("0xe94 = 0x%x\n", regE94)); + regE9C= PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("0xe9c = 0x%x\n", regE9C)); + regEA4= PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_A_2, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("0xea4 = 0x%x\n", regEA4)); + + if(!(regEAC & BIT28) && + (((regE94 & 0x03FF0000)>>16) != 0x142) && + (((regE9C & 0x03FF0000)>>16) != 0x42) ) + result |= 0x01; + else //if Tx not OK, ignore Rx + return result; + + if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK + (((regEA4 & 0x03FF0000)>>16) != 0x132) && + (((regEAC & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else + RTPRINT(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n")); + + return result; + + +} + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathB_IQK_8192C( + IN PADAPTER pAdapter + ) +{ + u4Byte regEAC, regEB4, regEBC, regEC4, regECC; + u1Byte result = 0x00; + RTPRINT(FINIT, INIT_IQK, ("Path B IQK!\n")); + + //One shot, path B LOK & IQK + RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n")); + PHY_SetBBReg(pAdapter, rIQK_AGC_Cont, bMaskDWord, 0x00000002); + PHY_SetBBReg(pAdapter, rIQK_AGC_Cont, bMaskDWord, 0x00000000); + + // delay x ms + RTPRINT(FINIT, INIT_IQK, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME)); + PlatformStallExecution(IQK_DELAY_TIME*1000); + + // Check failed + regEAC = PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", regEAC)); + regEB4 = PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("0xeb4 = 0x%x\n", regEB4)); + regEBC= PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("0xebc = 0x%x\n", regEBC)); + regEC4= PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_B_2, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("0xec4 = 0x%x\n", regEC4)); + regECC= PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_B_2, bMaskDWord); + RTPRINT(FINIT, INIT_IQK, ("0xecc = 0x%x\n", regECC)); + + if(!(regEAC & BIT31) && + (((regEB4 & 0x03FF0000)>>16) != 0x142) && + (((regEBC & 0x03FF0000)>>16) != 0x42)) + result |= 0x01; + else + return result; + + if(!(regEAC & BIT30) && + (((regEC4 & 0x03FF0000)>>16) != 0x132) && + (((regECC & 0x03FF0000)>>16) != 0x36)) + result |= 0x02; + else + RTPRINT(FINIT, INIT_IQK, ("Path B Rx IQK fail!!\n")); + + + return result; + +} + +VOID +phy_PathAFillIQKMatrix( + IN PADAPTER pAdapter, + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly + ) +{ + u4Byte Oldval_0, X, TX0_A, reg; + s4Byte Y, TX0_C; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + RTPRINT(FINIT, INIT_IQK, ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); + + if(final_candidate == 0xFF) + return; + + else if(bIQKOK) + { + Oldval_0 = (PHY_QueryBBReg(pAdapter, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][0]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX0_A = (X * Oldval_0) >> 8; + RTPRINT(FINIT, INIT_IQK, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); + PHY_SetBBReg(pAdapter, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); + PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(31), ((X * Oldval_0>>7) & 0x1)); + + Y = result[final_candidate][1]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + //path B IQK result + 3 + if(pAdapter->interfaceIndex == 1 && pHalData->CurrentBandType == BAND_ON_5G) + Y += 3; + + TX0_C = (Y * Oldval_0) >> 8; + RTPRINT(FINIT, INIT_IQK, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); + PHY_SetBBReg(pAdapter, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6)); + PHY_SetBBReg(pAdapter, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F)); + PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(29), ((Y * Oldval_0>>7) & 0x1)); + + if(bTxOnly) + { + RTPRINT(FINIT, INIT_IQK, ("phy_PathAFillIQKMatrix only Tx OK\n")); + return; + } + + reg = result[final_candidate][2]; + PHY_SetBBReg(pAdapter, rOFDM0_XARxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][3] & 0x3F; + PHY_SetBBReg(pAdapter, rOFDM0_XARxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][3] >> 6) & 0xF; + PHY_SetBBReg(pAdapter, rOFDM0_RxIQExtAnta, 0xF0000000, reg); + } +} + +VOID +phy_PathBFillIQKMatrix( + IN PADAPTER pAdapter, + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly //do Tx only + ) +{ + u4Byte Oldval_1, X, TX1_A, reg; + s4Byte Y, TX1_C; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + RTPRINT(FINIT, INIT_IQK, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed")); + + if(final_candidate == 0xFF) + return; + + else if(bIQKOK) + { + Oldval_1 = (PHY_QueryBBReg(pAdapter, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][4]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX1_A = (X * Oldval_1) >> 8; + RTPRINT(FINIT, INIT_IQK, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); + PHY_SetBBReg(pAdapter, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); + PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(27), ((X * Oldval_1>>7) & 0x1)); + + Y = result[final_candidate][5]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + if(pHalData->CurrentBandType == BAND_ON_5G) + Y += 3; //temp modify for preformance + TX1_C = (Y * Oldval_1) >> 8; + RTPRINT(FINIT, INIT_IQK, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); + PHY_SetBBReg(pAdapter, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6)); + PHY_SetBBReg(pAdapter, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F)); + PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(25), ((Y * Oldval_1>>7) & 0x1)); + + if(bTxOnly) + return; + + reg = result[final_candidate][6]; + PHY_SetBBReg(pAdapter, rOFDM0_XBRxIQImbalance, 0x3FF, reg); + + reg = result[final_candidate][7] & 0x3F; + PHY_SetBBReg(pAdapter, rOFDM0_XBRxIQImbalance, 0xFC00, reg); + + reg = (result[final_candidate][7] >> 6) & 0xF; + PHY_SetBBReg(pAdapter, rOFDM0_AGCRSSITable, 0x0000F000, reg); + } +} + + +BOOLEAN +phy_SimularityCompare_92C( + IN PADAPTER pAdapter, + IN s4Byte result[][8], + IN u1Byte c1, + IN u1Byte c2 + ) +{ + u4Byte i, j, diff, SimularityBitMap, bound = 0; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + u1Byte final_candidate[2] = {0xFF, 0xFF}; //for path A and path B + BOOLEAN bResult = TRUE, is2T = IS_92C_SERIAL( pHalData->VersionID); + + if(is2T) + bound = 8; + else + bound = 4; + + SimularityBitMap = 0; + + for( i = 0; i < bound; i++ ) + { + diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]); + if (diff > MAX_TOLERANCE) + { + if((i == 2 || i == 6) && !SimularityBitMap) + { + if(result[c1][i]+result[c1][i+1] == 0) + final_candidate[(i/4)] = c2; + else if (result[c2][i]+result[c2][i+1] == 0) + final_candidate[(i/4)] = c1; + else + SimularityBitMap = SimularityBitMap|(1< do IQK again +*/ +BOOLEAN +phy_SimularityCompare( + IN PADAPTER pAdapter, + IN s4Byte result[][8], + IN u1Byte c1, + IN u1Byte c2 + ) +{ + return phy_SimularityCompare_92C(pAdapter, result, c1, c2); + +} + +VOID +phy_IQCalibrate_8192C( + IN PADAPTER pAdapter, + IN s4Byte result[][8], + IN u1Byte t, + IN BOOLEAN is2T + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + u4Byte i; + u1Byte PathAOK, PathBOK; + u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + //since 92C & 92D have the different define in IQK_BB_REG + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE, /*rFPGA0_RFMOD*/ rCCK0_AFESetting + }; + + u4Byte IQK_BB_REG_92D[IQK_BB_REG_NUM_92D] = { //for normal + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rOFDM0_TRxPathEnable, + /*rFPGA0_RFMOD*/ rCCK0_AFESetting, rFPGA0_AnalogParameter4, + rOFDM0_XAAGCCore1, rOFDM0_XBAGCCore1 + }; +#if MP_DRIVER + const u4Byte retryCount = 9; +#else + const u4Byte retryCount = 2; +#endif + //Neil Chen--2011--05--19-- + //3 Path Div + u1Byte rfPathSwitch=0x0; + + // Note: IQ calibration must be performed after loading + // PHY_REG.txt , and radio_a, radio_b.txt + + u4Byte bbvalue; + + if(t==0) + { + //bbvalue = PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bMaskDWord); + // RTPRINT(FINIT, INIT_IQK, ("phy_IQCalibrate_8192C()==>0x%08x\n",bbvalue)); + + RTPRINT(FINIT, INIT_IQK, ("IQ Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); + + // Save ADDA parameters, turn Path A ADDA on + phy_SaveADDARegisters(pAdapter, ADDA_REG, pHalData->ADDA_backup, IQK_ADDA_REG_NUM); + phy_SaveMACRegisters(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup); + phy_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup, IQK_BB_REG_NUM); + } + + phy_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T); + + if(t==0) + { + pHalData->bRfPiEnable = (u1Byte)PHY_QueryBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, BIT(8)); + } + + if(!pHalData->bRfPiEnable){ + // Switch BB to PI mode to do IQ Calibration. + phy_PIModeSwitch(pAdapter, TRUE); + } + + //MAC settings + phy_MACSettingCalibration(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup); + + //PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, BIT24, 0x00); + PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskDWord, (0x0f000000 | (PHY_QueryBBReg(pAdapter, rCCK0_AFESetting, bMaskDWord))) ); + PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); + PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); + PHY_SetBBReg(pAdapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); + { + PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); + PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); + PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); + PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); + } + + if(is2T) + { + PHY_SetBBReg(pAdapter, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000); + PHY_SetBBReg(pAdapter, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000); + } + + { + //Page B init + PHY_SetBBReg(pAdapter, rConfig_AntA, bMaskDWord, 0x00080000); + + if(is2T) + { + PHY_SetBBReg(pAdapter, rConfig_AntB, bMaskDWord, 0x00080000); + } + } + // IQ calibration setting + RTPRINT(FINIT, INIT_IQK, ("IQK setting!\n")); + PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x808000); + PHY_SetBBReg(pAdapter, rTx_IQK, bMaskDWord, 0x01007c00); + PHY_SetBBReg(pAdapter, rRx_IQK, bMaskDWord, 0x01004800); + + for(i = 0 ; i < retryCount ; i++){ + PathAOK = phy_PathA_IQK_8192C(pAdapter, is2T); + if(PathAOK == 0x03){ + RTPRINT(FINIT, INIT_IQK, ("Path A IQK Success!!\n")); + result[t][0] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][1] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][2] = (PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + result[t][3] = (PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; + break; + } + else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK + { + RTPRINT(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n")); + + result[t][0] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][1] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + } + } + + if(0x00 == PathAOK){ + RTPRINT(FINIT, INIT_IQK, ("Path A IQK failed!!\n")); + } + + if(is2T){ + phy_PathAStandBy(pAdapter); + + // Turn Path B ADDA on + phy_PathADDAOn(pAdapter, ADDA_REG, FALSE, is2T); + + for(i = 0 ; i < retryCount ; i++){ + PathBOK = phy_PathB_IQK_8192C(pAdapter); + if(PathBOK == 0x03){ + RTPRINT(FINIT, INIT_IQK, ("Path B IQK Success!!\n")); + result[t][4] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; + result[t][5] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; + result[t][6] = (PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; + result[t][7] = (PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_B_2, bMaskDWord)&0x3FF0000)>>16; + break; + } + else if (i == (retryCount - 1) && PathBOK == 0x01) //Tx IQK OK + { + RTPRINT(FINIT, INIT_IQK, ("Path B Only Tx IQK Success!!\n")); + result[t][4] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16; + result[t][5] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16; + } + } + + if(0x00 == PathBOK){ + RTPRINT(FINIT, INIT_IQK, ("Path B IQK failed!!\n")); + } + } + + //Back to BB mode, load original value + RTPRINT(FINIT, INIT_IQK, ("IQK:Back to BB mode, load original value!\n")); + PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0); + + if(t!=0) + { + if(!pHalData->bRfPiEnable){ + // Switch back BB to SI mode after finish IQ Calibration. + phy_PIModeSwitch(pAdapter, FALSE); + } + + // Reload ADDA power saving parameters + phy_ReloadADDARegisters(pAdapter, ADDA_REG, pHalData->ADDA_backup, IQK_ADDA_REG_NUM); + + // Reload MAC parameters + phy_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pHalData->IQK_MAC_backup); + + // Reload BB parameters + phy_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup, IQK_BB_REG_NUM); + + /*Restore RX initial gain*/ + PHY_SetBBReg(pAdapter, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3); + if (is2T) + PHY_SetBBReg(pAdapter, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3); + //load 0xe30 IQC default value + PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + + } + RTPRINT(FINIT, INIT_IQK, ("phy_IQCalibrate_8192C() <==\n")); + +} + + +VOID +phy_LCCalibrate92C( + IN PADAPTER pAdapter, + IN BOOLEAN is2T + ) +{ + u1Byte tmpReg; + u4Byte RF_Amode=0, RF_Bmode=0, LC_Cal; +// HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + //Check continuous TX and Packet TX + tmpReg = PlatformEFIORead1Byte(pAdapter, 0xd03); + + if((tmpReg&0x70) != 0) //Deal with contisuous TX case + PlatformEFIOWrite1Byte(pAdapter, 0xd03, tmpReg&0x8F); //disable all continuous TX + else // Deal with Packet TX case + PlatformEFIOWrite1Byte(pAdapter, REG_TXPAUSE, 0xFF); // block all queues + + if((tmpReg&0x70) != 0) + { + //1. Read original RF mode + //Path-A + RF_Amode = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits); + + //Path-B + if(is2T) + RF_Bmode = PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits); + + //2. Set RF mode = standby mode + //Path-A + PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000); + + //Path-B + if(is2T) + PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000); + } + + //3. Read RF reg18 + LC_Cal = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits); + + //4. Set LC calibration begin bit15 + PHY_SetRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000); + + delay_ms(100); + + + //Restore original situation + if((tmpReg&0x70) != 0) //Deal with contisuous TX case + { + //Path-A + PlatformEFIOWrite1Byte(pAdapter, 0xd03, tmpReg); + PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); + + //Path-B + if(is2T) + PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); + } + else // Deal with Packet TX case + { + PlatformEFIOWrite1Byte(pAdapter, REG_TXPAUSE, 0x00); + } +} + + +VOID +phy_LCCalibrate( + IN PADAPTER pAdapter, + IN BOOLEAN is2T + ) +{ + phy_LCCalibrate92C(pAdapter, is2T); +} + + + +//Analog Pre-distortion calibration +#define APK_BB_REG_NUM 8 +#define APK_CURVE_REG_NUM 4 +#define PATH_NUM 2 + +VOID +phy_APCalibrate_8192C( + IN PADAPTER pAdapter, + IN s1Byte delta, + IN BOOLEAN is2T + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + u4Byte regD[PATH_NUM]; + u4Byte tmpReg, index, offset, i, apkbound; + u1Byte path, pathbound = PATH_NUM; + u4Byte BB_backup[APK_BB_REG_NUM]; + u4Byte BB_REG[APK_BB_REG_NUM] = { + rFPGA1_TxBlock, rOFDM0_TRxPathEnable, + rFPGA0_RFMOD, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, + rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE }; + u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x00204000 }; + u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x22204000 }; + + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN }; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG}; + + u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, + {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} + }; + + u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings + {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} + }; + + u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, + {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} + }; + + u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} + }; +#if 0 + u4Byte APK_RF_value_A[PATH_NUM][APK_BB_REG_NUM] = { + {0x1adb0, 0x1adb0, 0x1ada0, 0x1ad90, 0x1ad80}, + {0x00fb0, 0x00fb0, 0x00fa0, 0x00f90, 0x00f80} + }; +#endif + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on + + u4Byte APK_offset[PATH_NUM] = { + rConfig_AntA, rConfig_AntB}; + + u4Byte APK_normal_offset[PATH_NUM] = { + rConfig_Pmpd_AntA, rConfig_Pmpd_AntB}; + + u4Byte APK_value[PATH_NUM] = { + 0x92fc0000, 0x12fc0000}; + + u4Byte APK_normal_value[PATH_NUM] = { + 0x92680000, 0x12680000}; + + s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { + {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} + }; + + u4Byte APK_normal_setting_value_1[13] = { + 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, + 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, + 0x12680000, 0x00880000, 0x00880000 + }; + + u4Byte APK_normal_setting_value_2[16] = { + 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, + 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, + 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, + 0x00050006 + }; + + u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a +// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; + + s4Byte BB_offset, delta_V, delta_offset; + +#if MP_DRIVER == 1 + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); + + pMptCtx->APK_bound[0] = 45; + pMptCtx->APK_bound[1] = 52; +#endif + + RTPRINT(FINIT, INIT_IQK, ("==>phy_APCalibrate_8192C() delta %d\n", delta)); + RTPRINT(FINIT, INIT_IQK, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); + if(!is2T) + pathbound = 1; + + //2 FOR NORMAL CHIP SETTINGS + +// Temporarily do not allow normal driver to do the following settings because these offset +// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal +// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the +// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. +#if MP_DRIVER != 1 + return; +#endif + //settings adjust for normal chip + for(index = 0; index < PATH_NUM; index ++) + { + APK_offset[index] = APK_normal_offset[index]; + APK_value[index] = APK_normal_value[index]; + AFE_on_off[index] = 0x6fdb25a4; + } + + for(index = 0; index < APK_BB_REG_NUM; index ++) + { + for(path = 0; path < pathbound; path++) + { + APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; + APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; + } + BB_AP_MODE[index] = BB_normal_AP_MODE[index]; + } + + apkbound = 6; + + //save BB default value + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + if(index == 0) //skip + continue; + BB_backup[index] = PHY_QueryBBReg(pAdapter, BB_REG[index], bMaskDWord); + } + + //save MAC default value + phy_SaveMACRegisters(pAdapter, MAC_REG, MAC_backup); + + //save AFE default value + phy_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + + for(path = 0; path < pathbound; path++) + { + + + if(path == RF_PATH_A) + { + //path A APK + //load APK setting + //path-A + offset = rPdp_AntA; + for(index = 0; index < 11; index ++) + { + PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); + + offset += 0x04; + } + + PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); + + offset = rConfig_AntA; + for(; index < 13; index ++) + { + PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x400000); + + //path A + offset = rPdp_AntA; + for(index = 0; index < 16; index++) + { + PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_2[index]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); + + offset += 0x04; + } + PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0); + } + else if(path == RF_PATH_B) + { + //path B APK + //load APK setting + //path-B + offset = rPdp_AntB; + for(index = 0; index < 10; index ++) + { + PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); + + offset += 0x04; + } + PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); + + PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); + + offset = rConfig_AntA; + index = 11; + for(; index < 13; index ++) //offset 0xb68, 0xb6c + { + PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x400000); + + //path B + offset = 0xb60; + for(index = 0; index < 16; index++) + { + PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_2[index]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); + + offset += 0x04; + } + PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0); + } + + //save RF default value + regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask); + + //Path A AFE all on, path B AFE All off or vise versa + for(index = 0; index < IQK_ADDA_REG_NUM ; index++) + PHY_SetBBReg(pAdapter, AFE_REG[index], bMaskDWord, AFE_on_off[path]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xe70 %x\n", PHY_QueryBBReg(pAdapter, rRx_Wait_CCA, bMaskDWord))); + + //BB to AP mode + if(path == 0) + { + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + + if(index == 0) //skip + continue; + else if (index < 5) + PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); + else if (BB_REG[index] == 0x870) + PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26); + else + PHY_SetBBReg(pAdapter, BB_REG[index], BIT10, 0x0); + } + + PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + } + else //path B + { + PHY_SetBBReg(pAdapter, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); + PHY_SetBBReg(pAdapter, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); + + } + + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x800 %x\n", PHY_QueryBBReg(pAdapter, 0x800, bMaskDWord))); + + //MAC settings + phy_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup); + + if(path == RF_PATH_A) //Path B to standby mode + { + PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bRFRegOffsetMask, 0x10000); + } + else //Path A to standby mode + { + PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x10000); + PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE1, bRFRegOffsetMask, 0x1000f); + PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE2, bRFRegOffsetMask, 0x20103); + } + + delta_offset = ((delta+14)/2); + if(delta_offset < 0) + delta_offset = 0; + else if (delta_offset > 12) + delta_offset = 12; + + //AP calibration + for(index = 0; index < APK_BB_REG_NUM; index++) + { + if(index != 1) //only DO PA11+PAD01001, AP RF setting + continue; + + tmpReg = APK_RF_init_value[path][index]; +#if 1 + if(!pHalData->bAPKThermalMeterIgnore) + { + BB_offset = (tmpReg & 0xF0000) >> 16; + + if(!(tmpReg & BIT15)) //sign bit 0 + { + BB_offset = -BB_offset; + } + + delta_V = APK_delta_mapping[index][delta_offset]; + + BB_offset += delta_V; + + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset)); + + if(BB_offset < 0) + { + tmpReg = tmpReg & (~BIT15); + BB_offset = -BB_offset; + } + else + { + tmpReg = tmpReg | BIT15; + } + tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); + } +#endif + +#if DEV_BUS_TYPE==RT_PCI_INTERFACE + if(IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)) + PHY_SetRFReg(pAdapter, path, RF_IPA_A, bRFRegOffsetMask, 0x894ae); + else +#endif + PHY_SetRFReg(pAdapter, path, RF_IPA_A, bRFRegOffsetMask, 0x8992e); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bRFRegOffsetMask))); + PHY_SetRFReg(pAdapter, path, RF_AC, bRFRegOffsetMask, APK_RF_value_0[path][index]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bRFRegOffsetMask))); + PHY_SetRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask, tmpReg); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask))); + + // PA11+PAD01111, one shot + i = 0; + do + { + PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0x800000); + { + PHY_SetBBReg(pAdapter, APK_offset[path], bMaskDWord, APK_value[0]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", APK_offset[path], PHY_QueryBBReg(pAdapter, APK_offset[path], bMaskDWord))); + delay_ms(3); + PHY_SetBBReg(pAdapter, APK_offset[path], bMaskDWord, APK_value[1]); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0x%x value 0x%x\n", APK_offset[path], PHY_QueryBBReg(pAdapter, APK_offset[path], bMaskDWord))); + + delay_ms(20); + } + PHY_SetBBReg(pAdapter, rFPGA0_IQK, 0xffffff00, 0); + + if(path == RF_PATH_A) + tmpReg = PHY_QueryBBReg(pAdapter, rAPK, 0x03E00000); + else + tmpReg = PHY_QueryBBReg(pAdapter, rAPK, 0xF8000000); + RTPRINT(FINIT, INIT_IQK, ("phy_APCalibrate_8192C() offset 0xbd8[25:21] %x\n", tmpReg)); + + + i++; + } + while(tmpReg > apkbound && i < 4); + + APK_result[path][index] = tmpReg; + } + } + + //reload MAC default value + phy_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup); + + //reload BB default value + for(index = 0; index < APK_BB_REG_NUM ; index++) + { + + if(index == 0) //skip + continue; + PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_backup[index]); + } + + //reload AFE default value + phy_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + + //reload RF path default value + for(path = 0; path < pathbound; path++) + { + PHY_SetRFReg(pAdapter, path, RF_TXBIAS_A, bRFRegOffsetMask, regD[path]); + if(path == RF_PATH_B) + { + PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE1, bRFRegOffsetMask, 0x1000f); + PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE2, bRFRegOffsetMask, 0x20101); + } + + //note no index == 0 + if (APK_result[path][1] > 6) + APK_result[path][1] = 6; + RTPRINT(FINIT, INIT_IQK, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); + } + + RTPRINT(FINIT, INIT_IQK, ("\n")); + + + for(path = 0; path < pathbound; path++) + { + PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G1_G4, bRFRegOffsetMask, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); + if(path == RF_PATH_A) + PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G5_G8, bRFRegOffsetMask, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); + else + PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G5_G8, bRFRegOffsetMask, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); + + PHY_SetRFReg(pAdapter, path, RF_BS_PA_APSET_G9_G11, bRFRegOffsetMask, ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); + } + + pHalData->bAPKdone = TRUE; + + RTPRINT(FINIT, INIT_IQK, ("<==phy_APCalibrate_8192C()\n")); +} + + +VOID +PHY_IQCalibrate_8192C( + IN PADAPTER pAdapter, + IN BOOLEAN bReCovery + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + s4Byte result[4][8]; //last is final result + u1Byte i, final_candidate, Indexforchannel; + BOOLEAN bPathAOK, bPathBOK; + s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; + BOOLEAN is12simular, is13simular, is23simular; + BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, + rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, + rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, + rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, + rOFDM0_RxIQExtAnta}; + + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; + +#if MP_DRIVER == 1 + bStartContTx = pAdapter->MptCtx.bStartContTx; + bSingleTone = pAdapter->MptCtx.bSingleTone; + bCarrierSuppression = pAdapter->MptCtx.bCarrierSuppression; +#endif + + //ignore IQK when continuous Tx + if(bStartContTx || bSingleTone || bCarrierSuppression) + return; + +#ifdef DISABLE_BB_RF + return; +#endif + if(pAdapter->bSlaveOfDMSP) + return; + + if (bReCovery) + { + phy_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup_recover, 9); + return; + + } + + RTPRINT(FINIT, INIT_IQK, ("IQK:Start!!!\n")); + + for(i = 0; i < 8; i++) + { + result[0][i] = 0; + result[1][i] = 0; + result[2][i] = 0; + result[3][i] = 0; + } + final_candidate = 0xff; + bPathAOK = FALSE; + bPathBOK = FALSE; + is12simular = FALSE; + is23simular = FALSE; + is13simular = FALSE; + + AcquireCCKAndRWPageAControl(pAdapter); + /*RT_TRACE(COMP_INIT,DBG_LOUD,("Acquire Mutex in IQCalibrate\n"));*/ + for (i=0; i<3; i++) + { + /*For 88C 1T1R*/ + phy_IQCalibrate_8192C(pAdapter, result, i, FALSE); + + if(i == 1) + { + is12simular = phy_SimularityCompare(pAdapter, result, 0, 1); + if(is12simular) + { + final_candidate = 0; + break; + } + } + + if(i == 2) + { + is13simular = phy_SimularityCompare(pAdapter, result, 0, 2); + if(is13simular) + { + final_candidate = 0; + break; + } + + is23simular = phy_SimularityCompare(pAdapter, result, 1, 2); + if(is23simular) + final_candidate = 1; + else + { + for(i = 0; i < 8; i++) + RegTmp += result[3][i]; + + if(RegTmp != 0) + final_candidate = 3; + else + final_candidate = 0xFF; + } + } + } +// RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n")); + ReleaseCCKAndRWPageAControl(pAdapter); + + for (i=0; i<4; i++) + { + RegE94 = result[i][0]; + RegE9C = result[i][1]; + RegEA4 = result[i][2]; + RegEAC = result[i][3]; + RegEB4 = result[i][4]; + RegEBC = result[i][5]; + RegEC4 = result[i][6]; + RegECC = result[i][7]; + RTPRINT(FINIT, INIT_IQK, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + } + + if(final_candidate != 0xff) + { + pHalData->RegE94 = RegE94 = result[final_candidate][0]; + pHalData->RegE9C = RegE9C = result[final_candidate][1]; + RegEA4 = result[final_candidate][2]; + RegEAC = result[final_candidate][3]; + pHalData->RegEB4 = RegEB4 = result[final_candidate][4]; + pHalData->RegEBC = RegEBC = result[final_candidate][5]; + RegEC4 = result[final_candidate][6]; + RegECC = result[final_candidate][7]; + RTPRINT(FINIT, INIT_IQK, ("IQK: final_candidate is %x\n",final_candidate)); + RTPRINT(FINIT, INIT_IQK, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + bPathAOK = bPathBOK = TRUE; + } + else + { + RegE94 = RegEB4 = pHalData->RegE94 = pHalData->RegEB4 = 0x100; //X default value + RegE9C = RegEBC = pHalData->RegE9C = pHalData->RegEBC = 0x0; //Y default value + } + + if((RegE94 != 0)/*&&(RegEA4 != 0)*/) + { + if(pHalData->CurrentBandType == BAND_ON_5G) + phy_PathAFillIQKMatrix_5G_Normal(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); + else + phy_PathAFillIQKMatrix(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); + + } + + if (IS_92C_SERIAL(pHalData->VersionID) || IS_92D_SINGLEPHY(pHalData->VersionID)) + { + if((RegEB4 != 0)/*&&(RegEC4 != 0)*/) + { + if(pHalData->CurrentBandType == BAND_ON_5G) + phy_PathBFillIQKMatrix_5G_Normal(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); + else + phy_PathBFillIQKMatrix(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); + } + } + + phy_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pHalData->IQK_BB_backup_recover, 9); + +} + + +VOID +PHY_LCCalibrate_8192C( + IN PADAPTER pAdapter + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + BOOLEAN bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE; + PMGNT_INFO pMgntInfo=&pAdapter->MgntInfo; + PMGNT_INFO pMgntInfoBuddyAdapter; + u4Byte timeout = 2000, timecount = 0; + PADAPTER BuddyAdapter = pAdapter->BuddyAdapter; + +#if MP_DRIVER == 1 + bStartContTx = pAdapter->MptCtx.bStartContTx; + bSingleTone = pAdapter->MptCtx.bSingleTone; + bCarrierSuppression = pAdapter->MptCtx.bCarrierSuppression; +#endif + +#ifdef DISABLE_BB_RF + return; +#endif + + //ignore LCK when continuous Tx + if(bStartContTx || bSingleTone || bCarrierSuppression) + return; + + if(BuddyAdapter != NULL && + ((pAdapter->interfaceIndex == 0 && pHalData->CurrentBandType == BAND_ON_2_4G) || + (pAdapter->interfaceIndex == 1 && pHalData->CurrentBandType == BAND_ON_5G))) + { + pMgntInfoBuddyAdapter=&BuddyAdapter->MgntInfo; + while(pMgntInfoBuddyAdapter->bScanInProgress && timecount < timeout) + { + delay_ms(50); + timecount += 50; + } + } + + while(pMgntInfo->bScanInProgress && timecount < timeout) + { + delay_ms(50); + timecount += 50; + } + + pHalData->bLCKInProgress = TRUE; + + RTPRINT(FINIT, INIT_IQK, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pAdapter->interfaceIndex, pHalData->CurrentBandType, timecount)); + + //if(IS_92C_SERIAL(pHalData->VersionID) || IS_92D_SINGLEPHY(pHalData->VersionID)) + if(IS_2T2R(pHalData->VersionID)) + { + phy_LCCalibrate(pAdapter, TRUE); + } + else{ + // For 88C 1T1R + phy_LCCalibrate(pAdapter, FALSE); + } + + pHalData->bLCKInProgress = FALSE; + + RTPRINT(FINIT, INIT_IQK, ("LCK:Finish!!!interface %d\n", pAdapter->interfaceIndex)); + + +} + +VOID +PHY_APCalibrate_8192C( + IN PADAPTER pAdapter, + IN s1Byte delta + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + //default disable APK, because Tx NG issue, suggest by Jenyu, 2011.11.25 + return; + +#ifdef DISABLE_BB_RF + return; +#endif + +#if FOR_BRAZIL_PRETEST != 1 + if(pHalData->bAPKdone) +#endif + return; + + if(IS_92C_SERIAL( pHalData->VersionID)){ + phy_APCalibrate_8192C(pAdapter, delta, TRUE); + } + else{ + // For 88C 1T1R + phy_APCalibrate_8192C(pAdapter, delta, FALSE); + } +} + + +#endif + + +//3============================================================ +//3 IQ Calibration +//3============================================================ + +VOID +ODM_ResetIQKResult( + IN PVOID pDM_VOID +) +{ + return; +} +#if 1//!(DM_ODM_SUPPORT_TYPE & ODM_AP) +u1Byte ODM_GetRightChnlPlaceforIQK(u1Byte chnl) +{ + u1Byte channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = + {1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,138,140,149,151,153,155,157,159,161,163,165}; + u1Byte place = chnl; + + + if(chnl > 14) + { + for(place = 14; placeAdapter; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (*pDM_Odm->pIsFcsModeEnable) + return; +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if (!IS_HARDWARE_TYPE_JAGUAR(Adapter)) + return; +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + else if (IS_HARDWARE_TYPE_8812AU(Adapter)) + return; +#endif +#endif + +#if (RTL8821A_SUPPORT == 1) + if (pDM_Odm->bLinked) { + if ((*pDM_Odm->pChannel != pDM_Odm->preChannel) && (!*pDM_Odm->pbScanInProcess)) { + pDM_Odm->preChannel = *pDM_Odm->pChannel; + pDM_Odm->LinkedInterval = 0; + } + + if (pDM_Odm->LinkedInterval < 3) + pDM_Odm->LinkedInterval++; + + if (pDM_Odm->LinkedInterval == 2) { + /*Mark out IQK flow to prevent tx stuck. by Maddest 20130306*/ + /*Open it verified by James 20130715*/ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PHY_IQCalibrate_8821A(pDM_Odm, FALSE); +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHY_IQCalibrate(Adapter, FALSE); +#else + PHY_IQCalibrate_8821A(Adapter, FALSE); +#endif + } + } else + pDM_Odm->LinkedInterval = 0; +#endif +} + +void phydm_rf_init(IN PVOID pDM_VOID) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + odm_TXPowerTrackingInit(pDM_Odm); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + ODM_ClearTxPowerTrackingState(pDM_Odm); +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#if (RTL8814A_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8814A) + PHY_IQCalibrate_8814A_Init(pDM_Odm); +#endif +#endif + +} + +void phydm_rf_watchdog(IN PVOID pDM_VOID) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + ODM_TXPowerTrackingCheck(pDM_Odm); + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + odm_IQCalibrate(pDM_Odm); +#endif +} diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halphyrf_ap.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halphyrf_ap.h new file mode 100644 index 000000000..4cacdb54a --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halphyrf_ap.h @@ -0,0 +1,162 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + #ifndef __HAL_PHY_RF_H__ + #define __HAL_PHY_RF_H__ + +#include "phydm_powertracking_ap.h" +#if (RTL8814A_SUPPORT == 1) +#include "rtl8814a/phydm_iqk_8814a.h" +#endif + +#if (RTL8822B_SUPPORT == 1) +#include "rtl8822b/phydm_iqk_8822b.h" +#endif + + +typedef enum _PWRTRACK_CONTROL_METHOD { + BBSWING, + TXAGC, + MIX_MODE, + TSSI_MODE +} PWRTRACK_METHOD; + +typedef VOID (*FuncSetPwr)(PVOID, PWRTRACK_METHOD, u1Byte, u1Byte); +typedef VOID(*FuncIQK)(PVOID, u1Byte, u1Byte, u1Byte); +typedef VOID (*FuncLCK)(PVOID); + //refine by YuChen for 8814A +typedef VOID (*FuncSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); +typedef VOID (*FuncSwing8814only)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); + +typedef struct _TXPWRTRACK_CFG { + u1Byte SwingTableSize_CCK; + u1Byte SwingTableSize_OFDM; + u1Byte Threshold_IQK; + u1Byte Threshold_DPK; + u1Byte AverageThermalNum; + u1Byte RfPathCount; + u4Byte ThermalRegAddr; + FuncSetPwr ODM_TxPwrTrackSetPwr; + FuncIQK DoIQK; + FuncLCK PHY_LCCalibrate; + FuncSwing GetDeltaSwingTable; + FuncSwing8814only GetDeltaSwingTable8814only; +} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG; + +VOID +ConfigureTxpowerTrack( + IN PVOID pDM_VOID, + OUT PTXPWRTRACK_CFG pConfig + ); + + +VOID +ODM_TXPowerTrackingCallback_ThermalMeter( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PVOID pDM_VOID +#else + IN PADAPTER Adapter +#endif + ); + +#if (RTL8192E_SUPPORT==1) +VOID +ODM_TXPowerTrackingCallback_ThermalMeter_92E( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PVOID pDM_VOID +#else + IN PADAPTER Adapter +#endif + ); +#endif + +#if (RTL8814A_SUPPORT == 1) +VOID +ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries2( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PVOID pDM_VOID +#else + IN PADAPTER Adapter +#endif + ); + +#elif ODM_IC_11AC_SERIES_SUPPORT +VOID +ODM_TXPowerTrackingCallback_ThermalMeter_JaguarSeries( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PVOID pDM_VOID +#else + IN PADAPTER Adapter +#endif + ); +#endif + +#define IS_CCK_RATE(_rate) (ODM_MGN_1M == _rate || _rate == ODM_MGN_2M || _rate == ODM_MGN_5_5M || _rate == ODM_MGN_11M ) + + +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#define MAX_TOLERANCE 5 +#define IQK_DELAY_TIME 1 //ms + + // +// BB/MAC/RF other monitor API +// + +void PHY_SetMonitorMode8192C(IN PADAPTER pAdapter, + IN BOOLEAN bEnableMonitorMode ); + +// +// IQ calibrate +// +void +PHY_IQCalibrate_8192C( IN PADAPTER pAdapter, + IN BOOLEAN bReCovery); + +// +// LC calibrate +// +void +PHY_LCCalibrate_8192C( IN PADAPTER pAdapter); + +// +// AP calibrate +// +void +PHY_APCalibrate_8192C( IN PADAPTER pAdapter, + IN s1Byte delta); +#endif + +#define ODM_TARGET_CHNL_NUM_2G_5G 59 + + +VOID +ODM_ResetIQKResult( + IN PVOID pDM_VOID +); +u1Byte +ODM_GetRightChnlPlaceforIQK( + IN u1Byte chnl +); + +void phydm_rf_init(IN PVOID pDM_VOID); +void phydm_rf_watchdog(IN PVOID pDM_VOID); + +#endif // #ifndef __HAL_PHY_RF_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halphyrf_ce.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halphyrf_ce.c new file mode 100644 index 000000000..8afa89706 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halphyrf_ce.c @@ -0,0 +1,711 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + + +#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _deltaThermal) \ + do {\ + for(_offset = 0; _offset < _size; _offset++)\ + {\ + if(_deltaThermal < thermalThreshold[_direction][_offset])\ + {\ + if(_offset != 0)\ + _offset--;\ + break;\ + }\ + } \ + if(_offset >= _size)\ + _offset = _size-1;\ + } while(0) + +void ConfigureTxpowerTrack( + IN PVOID pDM_VOID, + OUT PTXPWRTRACK_CFG pConfig + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + +#if RTL8192E_SUPPORT + if(pDM_Odm->SupportICType==ODM_RTL8192E) + ConfigureTxpowerTrack_8192E(pConfig); +#endif +#if RTL8821A_SUPPORT + if(pDM_Odm->SupportICType==ODM_RTL8821) + ConfigureTxpowerTrack_8821A(pConfig); +#endif +#if RTL8812A_SUPPORT + if(pDM_Odm->SupportICType==ODM_RTL8812) + ConfigureTxpowerTrack_8812A(pConfig); +#endif +#if RTL8188E_SUPPORT + if(pDM_Odm->SupportICType==ODM_RTL8188E) + ConfigureTxpowerTrack_8188E(pConfig); +#endif + +#if RTL8723B_SUPPORT + if(pDM_Odm->SupportICType==ODM_RTL8723B) + ConfigureTxpowerTrack_8723B(pConfig); +#endif + +#if RTL8814A_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8814A) + ConfigureTxpowerTrack_8814A(pConfig); +#endif + +#if RTL8703B_SUPPORT + if(pDM_Odm->SupportICType==ODM_RTL8703B) + ConfigureTxpowerTrack_8703B(pConfig); +#endif + +#if RTL8188F_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8188F) + ConfigureTxpowerTrack_8188F(pConfig); +#endif +} + +//====================================================================== +// <20121113, Kordan> This function should be called when TxAGC changed. +// Otherwise the previous compensation is gone, because we record the +// delta of temperature between two TxPowerTracking watch dogs. +// +// NOTE: If Tx BB swing or Tx scaling is varified during run-time, still +// need to call this function. +//====================================================================== +VOID +ODM_ClearTxPowerTrackingState( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pDM_Odm->Adapter); + u1Byte p = 0; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->DefaultCckIndex; + pRFCalibrateInfo->BbSwingIdxCck = pRFCalibrateInfo->DefaultCckIndex; + pDM_Odm->RFCalibrateInfo.CCK_index = 0; + + for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) + { + pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->DefaultOfdmIndex; + pRFCalibrateInfo->BbSwingIdxOfdm[p] = pRFCalibrateInfo->DefaultOfdmIndex; + pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->DefaultOfdmIndex; + + pRFCalibrateInfo->PowerIndexOffset[p] = 0; + pRFCalibrateInfo->DeltaPowerIndex[p] = 0; + pRFCalibrateInfo->DeltaPowerIndexLast[p] = 0; + pRFCalibrateInfo->PowerIndexOffset[p] = 0; + + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = 0; /* Initial Mix mode power tracking*/ + pRFCalibrateInfo->Remnant_OFDMSwingIdx[p] = 0; + pRFCalibrateInfo->KfreeOffset[p] = 0; + } + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = FALSE; /*Initial at Modify Tx Scaling Mode*/ + pRFCalibrateInfo->Modify_TxAGC_Flag_PathB = FALSE; /*Initial at Modify Tx Scaling Mode*/ + pRFCalibrateInfo->Modify_TxAGC_Flag_PathC = FALSE; /*Initial at Modify Tx Scaling Mode*/ + pRFCalibrateInfo->Modify_TxAGC_Flag_PathD = FALSE; /*Initial at Modify Tx Scaling Mode*/ + pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; + pRFCalibrateInfo->ThermalValue = pHalData->EEPROMThermalMeter; + + pRFCalibrateInfo->Modify_TxAGC_Value_CCK=0; //modify by Mingzhi.Guo + pRFCalibrateInfo->Modify_TxAGC_Value_OFDM=0; //modify by Mingzhi.Guo +} + +VOID +ODM_TXPowerTrackingCallback_ThermalMeter( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER Adapter +#endif + ) +{ + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + #endif +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0; + s1Byte diff_DPK[4] = {0}; + u1Byte ThermalValue_AVG_count = 0; + u4Byte ThermalValue_AVG = 0; + + u1Byte OFDM_min_index = 0; // OFDM BB Swing should be less than +3.0dB, which is required by Arthur + u1Byte Indexforchannel = 0; // GetRightChnlPlaceforIQK(pHalData->CurrentChannel) + BOOLEAN bTSSIenable = FALSE; + + TXPWRTRACK_CFG c; + + //4 1. The following TWO tables decide the final index of OFDM/CCK swing table. + pu1Byte deltaSwingTableIdx_TUP_A; + pu1Byte deltaSwingTableIdx_TDOWN_A; + pu1Byte deltaSwingTableIdx_TUP_B; + pu1Byte deltaSwingTableIdx_TDOWN_B; + /*for 8814 add by Yu Chen*/ + pu1Byte deltaSwingTableIdx_TUP_C; + pu1Byte deltaSwingTableIdx_TDOWN_C; + pu1Byte deltaSwingTableIdx_TUP_D; + pu1Byte deltaSwingTableIdx_TDOWN_D; + + //4 2. Initilization ( 7 steps in total ) + + ConfigureTxpowerTrack(pDM_Odm, &c); + + (*c.GetDeltaSwingTable)(pDM_Odm, (pu1Byte*)&deltaSwingTableIdx_TUP_A, (pu1Byte*)&deltaSwingTableIdx_TDOWN_A, + (pu1Byte*)&deltaSwingTableIdx_TUP_B, (pu1Byte*)&deltaSwingTableIdx_TDOWN_B); + + if (pDM_Odm->SupportICType & ODM_RTL8814A) /*for 8814 path C & D*/ + (*c.GetDeltaSwingTable8814only)(pDM_Odm, (pu1Byte *)&deltaSwingTableIdx_TUP_C, (pu1Byte *)&deltaSwingTableIdx_TDOWN_C, + (pu1Byte *)&deltaSwingTableIdx_TUP_D, (pu1Byte *)&deltaSwingTableIdx_TDOWN_D); + + + pDM_Odm->RFCalibrateInfo.TXPowerTrackingCallbackCnt++; //cosa add for debug + pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = TRUE; + +#if (MP_DRIVER == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = pHalData->TxPowerTrackControl; // We should keep updating the control variable according to HalData. +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (pDM_Odm->mp_mode == TRUE) +#endif + // RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files. + pDM_Odm->RFCalibrateInfo.RegA24 = 0x090e1317; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("===>ODM_TXPowerTrackingCallback_ThermalMeter Start\n pRFCalibrateInfo->BbSwingIdxCckBase: %d, pRFCalibrateInfo->BbSwingIdxOfdmBase[A]: %d, pRFCalibrateInfo->DefaultOfdmIndex: %d\n", + pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->BbSwingIdxOfdmBase[ODM_RF_PATH_A], pRFCalibrateInfo->DefaultOfdmIndex)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("pDM_Odm->RFCalibrateInfo.TxPowerTrackControl %d, pHalData->EEPROMThermalMeter %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl, pHalData->EEPROMThermalMeter)); + ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, c.ThermalRegAddr, 0xfc00); //0x42: RF Reg[15:10] 88E + if( ! pDM_Odm->RFCalibrateInfo.TxPowerTrackControl || pHalData->EEPROMThermalMeter == 0 || + pHalData->EEPROMThermalMeter == 0xFF) + return; + + + //4 3. Initialize ThermalValues of RFCalibrateInfo + + if(pDM_Odm->RFCalibrateInfo.bReloadtxpowerindex) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("reload ofdm index for band switch\n")); + } + + //4 4. Calculate average thermal meter + + pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index] = ThermalValue; + pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index++; + if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index == c.AverageThermalNum) //Average times = c.AverageThermalNum + pDM_Odm->RFCalibrateInfo.ThermalValue_AVG_index = 0; + + for(i = 0; i < c.AverageThermalNum; i++) + { + if(pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]) + { + ThermalValue_AVG += pDM_Odm->RFCalibrateInfo.ThermalValue_AVG[i]; + ThermalValue_AVG_count++; + } + } + + if(ThermalValue_AVG_count) //Calculate Average ThermalValue after average enough times + { + ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("AVG Thermal Meter = 0x%X, EFUSE Thermal Base = 0x%X\n", ThermalValue, pHalData->EEPROMThermalMeter)); + } + + //4 5. Calculate delta, delta_LCK, delta_IQK. + + //"delta" here is used to determine whether thermal value changes or not. + delta = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue):(pDM_Odm->RFCalibrateInfo.ThermalValue - ThermalValue); + delta_LCK = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_LCK)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_LCK):(pDM_Odm->RFCalibrateInfo.ThermalValue_LCK - ThermalValue); + delta_IQK = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_IQK)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK):(pDM_Odm->RFCalibrateInfo.ThermalValue_IQK - ThermalValue); + + if (pDM_Odm->RFCalibrateInfo.ThermalValue_IQK == 0xff) { /*no PG, use thermal value for IQK*/ + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; + delta_IQK = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_IQK)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_IQK):(pDM_Odm->RFCalibrateInfo.ThermalValue_IQK - ThermalValue); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, use ThermalValue for IQK\n")); + } + + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + diff_DPK[p] = (s1Byte)ThermalValue - (s1Byte)pDM_Odm->RFCalibrateInfo.DpkThermal[p]; + + /*4 6. If necessary, do LCK.*/ + if (!(pDM_Odm->SupportICType & ODM_RTL8821)) { + + if (pDM_Odm->RFCalibrateInfo.ThermalValue_LCK == 0xff) { + /*no PG , do LCK at initial status*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, do LCK\n")); + pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue; + if (c.PHY_LCCalibrate) + (*c.PHY_LCCalibrate)(pDM_Odm); + delta_LCK = (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue_LCK)?(ThermalValue - pDM_Odm->RFCalibrateInfo.ThermalValue_LCK):(pDM_Odm->RFCalibrateInfo.ThermalValue_LCK - ThermalValue); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK)); + /*DBG_871X("(delta, delta_LCK, delta_IQK) = (%d, %d, %d), %d\n", delta, delta_LCK, delta_IQK, c.Threshold_IQK);*/ + + /* 4 6. If necessary, do LCK.*/ + + if (delta_LCK >= c.Threshold_IQK) { + /* Delta temperature is equal to or larger than 20 centigrade.*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= Threshold_IQK(%d)\n", delta_LCK, c.Threshold_IQK)); + pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = ThermalValue; + if (c.PHY_LCCalibrate) + (*c.PHY_LCCalibrate)(pDM_Odm); + } + } + //3 7. If necessary, move the index of swing table to adjust Tx power. + + if (delta > 0 && pDM_Odm->RFCalibrateInfo.TxPowerTrackControl) + { + //"delta" here is used to record the absolute value of differrence. +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue); +#else + delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - pDM_Odm->priv->pmib->dot11RFEntry.ther):(pDM_Odm->priv->pmib->dot11RFEntry.ther - ThermalValue); +#endif + if (delta >= TXPWR_TRACK_TABLE_SIZE) + delta = TXPWR_TRACK_TABLE_SIZE - 1; + + //4 7.1 The Final Power Index = BaseIndex + PowerIndexOffset + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if(ThermalValue > pHalData->EEPROMThermalMeter) { +#else + if(ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) { +#endif + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { + pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p] = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p]; /* recording power index offset */ + switch (p) { + case ODM_RF_PATH_B: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_B[%d] = %d\n", delta, deltaSwingTableIdx_TUP_B[delta])); + + pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_B[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_B[delta]; /* Record delta swing for mix mode power tracking */ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_A])); + + + break; + + case ODM_RF_PATH_C: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_C[%d] = %d\n", delta, deltaSwingTableIdx_TUP_C[delta])); + + pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_C[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_C[delta]; /* Record delta swing for mix mode power tracking */ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + case ODM_RF_PATH_D: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_D[%d] = %d\n", delta, deltaSwingTableIdx_TUP_D[delta])); + + pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_D[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_D[delta]; /* Record delta swing for mix mode power tracking */ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_A[%d] = %d\n", delta, deltaSwingTableIdx_TUP_A[delta])); + + pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_A[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_A[delta]; /* Record delta swing for mix mode power tracking */ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + } + } + } else { + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { + pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p] = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p]; /* recording poer index offset */ + switch (p) { + case ODM_RF_PATH_B: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_B[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_B[delta])); + pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; /* Record delta swing for mix mode power tracking */ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + case ODM_RF_PATH_C: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_C[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_C[delta])); + pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; /* Record delta swing for mix mode power tracking */ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + case ODM_RF_PATH_D: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_D[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_D[delta])); + pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; /* Record delta swing for mix mode power tracking */ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_A[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_A[delta])); + pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; /* Record delta swing for mix mode power tracking */ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pDM_Odm->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + } + } + } + + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("\n\n=========================== [Path-%d] Calculating PowerIndexOffset===========================\n", p)); + if (pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] == pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p]) /* If Thermal value changes but lookup table value still the same */ + pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = 0; + else + pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] - pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p]; /* Power Index Diff between 2 times Power Tracking */ + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("[Path-%d] PowerIndexOffset(%d) = DeltaPowerIndex(%d) - DeltaPowerIndexLast(%d)\n", p, pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p], pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p], pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p])); + + pDM_Odm->RFCalibrateInfo.OFDM_index[p] = pRFCalibrateInfo->BbSwingIdxOfdmBase[p] + pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p]; + pDM_Odm->RFCalibrateInfo.CCK_index = pRFCalibrateInfo->BbSwingIdxCckBase + pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p]; + + pRFCalibrateInfo->BbSwingIdxCck = pDM_Odm->RFCalibrateInfo.CCK_index; + pRFCalibrateInfo->BbSwingIdxOfdm[p] = pDM_Odm->RFCalibrateInfo.OFDM_index[p]; + + + + /* *************Print BB Swing Base and Index Offset************* */ + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxCck, pRFCalibrateInfo->BbSwingIdxCckBase, pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p])); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("The 'OFDM' final index(%d) = BaseIndex[%d](%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxOfdm[p], p, pRFCalibrateInfo->BbSwingIdxOfdmBase[p], pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p])); + + //4 7.1 Handle boundary conditions of index. + + if(pDM_Odm->RFCalibrateInfo.OFDM_index[p] > c.SwingTableSize_OFDM-1) + { + pDM_Odm->RFCalibrateInfo.OFDM_index[p] = c.SwingTableSize_OFDM-1; + } + else if (pDM_Odm->RFCalibrateInfo.OFDM_index[p] < OFDM_min_index) + { + pDM_Odm->RFCalibrateInfo.OFDM_index[p] = OFDM_min_index; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("\n\n========================================================================================================\n")); + if(pDM_Odm->RFCalibrateInfo.CCK_index > c.SwingTableSize_CCK-1) + pDM_Odm->RFCalibrateInfo.CCK_index = c.SwingTableSize_CCK-1; + else if (pDM_Odm->RFCalibrateInfo.CCK_index <= 0) + pDM_Odm->RFCalibrateInfo.CCK_index = 0; + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("The thermal meter is unchanged or TxPowerTracking OFF(%d): ThermalValue: %d , pDM_Odm->RFCalibrateInfo.ThermalValue: %d\n", + pDM_Odm->RFCalibrateInfo.TxPowerTrackControl, ThermalValue, pDM_Odm->RFCalibrateInfo.ThermalValue)); + + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = 0; + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TxPowerTracking: [CCK] Swing Current Index: %d, Swing Base Index: %d\n", + pDM_Odm->RFCalibrateInfo.CCK_index, pRFCalibrateInfo->BbSwingIdxCckBase)); /*Print Swing base & current*/ + + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TxPowerTracking: [OFDM] Swing Current Index: %d, Swing Base Index[%d]: %d\n", + pDM_Odm->RFCalibrateInfo.OFDM_index[p], p, pRFCalibrateInfo->BbSwingIdxOfdmBase[p])); + } + + if ((pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_A] != 0 || + pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_B] != 0 || + pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_C] != 0 || + pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_D] != 0) && + pDM_Odm->RFCalibrateInfo.TxPowerTrackControl && (pHalData->EEPROMThermalMeter != 0xff)) + { + //4 7.2 Configure the Swing Table to adjust Tx Power. + + pDM_Odm->RFCalibrateInfo.bTxPowerChanged = TRUE; // Always TRUE after Tx Power is adjusted by power tracking. + // + // 2012/04/23 MH According to Luke's suggestion, we can not write BB digital + // to increase TX power. Otherwise, EVM will be bad. + // + // 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. + if (ThermalValue > pDM_Odm->RFCalibrateInfo.ThermalValue) + { + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature Increasing(%d): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + p, pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p], delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue)); + } + } + else if (ThermalValue < pDM_Odm->RFCalibrateInfo.ThermalValue)// Low temperature + { + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature Decreasing(%d): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + p, pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p], delta, ThermalValue, pHalData->EEPROMThermalMeter, pDM_Odm->RFCalibrateInfo.ThermalValue)); + } + } + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (ThermalValue > pHalData->EEPROMThermalMeter) +#else + if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) +#endif + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) higher than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); + + if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8821 || + pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8814A || + pDM_Odm->SupportICType == ODM_RTL8822B || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8703B) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); + } + else + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel); + } + } + else + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) lower than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); + + if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8821 || + pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8814A || + pDM_Odm->SupportICType == ODM_RTL8822B || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8703B) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking MIX_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, Indexforchannel); + } + else + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("**********Enter POWER Tracking BBSWING_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel); + } + + } + + pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->BbSwingIdxCck; /*Record last time Power Tracking result as base.*/ + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->BbSwingIdxOfdm[p]; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("pDM_Odm->RFCalibrateInfo.ThermalValue = %d ThermalValue= %d\n", pDM_Odm->RFCalibrateInfo.ThermalValue, ThermalValue)); + + pDM_Odm->RFCalibrateInfo.ThermalValue = ThermalValue; /*Record last Power Tracking Thermal Value*/ + + } + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + if (!IS_HARDWARE_TYPE_8723B(Adapter) && !IS_HARDWARE_TYPE_8192E(Adapter) && !IS_HARDWARE_TYPE_8703B(Adapter)) { + /* Delta temperature is equal to or larger than 20 centigrade (When threshold is 8).*/ + if (delta_IQK >= c.Threshold_IQK) { + if (!pDM_Odm->RFCalibrateInfo.bIQKInProgress) + (*c.DoIQK)(pDM_Odm, delta_IQK, ThermalValue, 8); + } + } + if (!(pDM_Odm->SupportICType & ODM_RTL8814A)) { + if (pDM_Odm->RFCalibrateInfo.DpkThermal[ODM_RF_PATH_A] != 0) { + if (diff_DPK[ODM_RF_PATH_A] >= c.Threshold_DPK) { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, (diff_DPK[ODM_RF_PATH_A] / c.Threshold_DPK)); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + } else if ((diff_DPK[ODM_RF_PATH_A] <= -1 * c.Threshold_DPK)) { + s4Byte value = 0x20 + (diff_DPK[ODM_RF_PATH_A] / c.Threshold_DPK); + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, value); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + } else { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, 0); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + } + } + if (pDM_Odm->RFCalibrateInfo.DpkThermal[ODM_RF_PATH_B] != 0) { + if (diff_DPK[ODM_RF_PATH_B] >= c.Threshold_DPK) { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, (diff_DPK[ODM_RF_PATH_B] / c.Threshold_DPK)); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + } else if ((diff_DPK[ODM_RF_PATH_B] <= -1 * c.Threshold_DPK)) { + s4Byte value = 0x20 + (diff_DPK[ODM_RF_PATH_B] / c.Threshold_DPK); + + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, value); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + } else { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, 0); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + } + } + } + +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("<===ODM_TXPowerTrackingCallback_ThermalMeter End\n")); + + pDM_Odm->RFCalibrateInfo.TXPowercount = 0; +} + + +//3============================================================ +//3 IQ Calibration +//3============================================================ + +VOID +ODM_ResetIQKResult( + IN PVOID pDM_VOID +) +{ + return; + +} +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +u1Byte ODM_GetRightChnlPlaceforIQK(u1Byte chnl) +{ + u1Byte channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = + {1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,138,140,149,151,153,155,157,159,161,163,165}; + u1Byte place = chnl; + + + if(chnl > 14) + { + for(place = 14; placeAdapter; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (*pDM_Odm->pIsFcsModeEnable) + return; +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if (!IS_HARDWARE_TYPE_JAGUAR(Adapter)) + return; +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + else if (IS_HARDWARE_TYPE_8812AU(Adapter)) + return; +#endif +#endif + +#if (RTL8821A_SUPPORT == 1) + if (pDM_Odm->bLinked) { + if ((*pDM_Odm->pChannel != pDM_Odm->preChannel) && (!*pDM_Odm->pbScanInProcess)) { + pDM_Odm->preChannel = *pDM_Odm->pChannel; + pDM_Odm->LinkedInterval = 0; + } + + if (pDM_Odm->LinkedInterval < 3) + pDM_Odm->LinkedInterval++; + + if (pDM_Odm->LinkedInterval == 2) { + /*Mark out IQK flow to prevent tx stuck. by Maddest 20130306*/ + /*Open it verified by James 20130715*/ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + /*Change channel will do IQK , cancel duplicate doIQK by YiWei*/ + /*PHY_IQCalibrate_8821A(pDM_Odm, FALSE);*/ +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHY_IQCalibrate(Adapter, FALSE); +#else + PHY_IQCalibrate_8821A(Adapter, FALSE); +#endif + } + } else + pDM_Odm->LinkedInterval = 0; +#endif +} + +void phydm_rf_init(IN PVOID pDM_VOID) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + odm_TXPowerTrackingInit(pDM_Odm); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + ODM_ClearTxPowerTrackingState(pDM_Odm); +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#if (RTL8814A_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8814A) + PHY_IQCalibrate_8814A_Init(pDM_Odm); +#endif +#endif + +} + +void phydm_rf_watchdog(IN PVOID pDM_VOID) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + ODM_TXPowerTrackingCheck(pDM_Odm); + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + odm_IQCalibrate(pDM_Odm); +#endif +} diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halphyrf_ce.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halphyrf_ce.h new file mode 100644 index 000000000..2e5f22355 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halphyrf_ce.h @@ -0,0 +1,106 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + #ifndef __HAL_PHY_RF_H__ + #define __HAL_PHY_RF_H__ + +/*#include "phydm_kfree.h"*/ +#if (RTL8814A_SUPPORT == 1) +#include "rtl8814a/phydm_iqk_8814a.h" +#endif + +#if (RTL8822B_SUPPORT == 1) +#include "rtl8822b/phydm_iqk_8822b.h" +#endif +#include "phydm_powertracking_ce.h" + + +typedef enum _SPUR_CAL_METHOD { + PLL_RESET, + AFE_PHASE_SEL +} SPUR_CAL_METHOD; + +typedef enum _PWRTRACK_CONTROL_METHOD { + BBSWING, + TXAGC, + MIX_MODE, + TSSI_MODE +} PWRTRACK_METHOD; + +typedef VOID (*FuncSetPwr)(PVOID, PWRTRACK_METHOD, u1Byte, u1Byte); +typedef VOID(*FuncIQK)(PVOID, u1Byte, u1Byte, u1Byte); +typedef VOID (*FuncLCK)(PVOID); +typedef VOID (*FuncSwing)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); +typedef VOID (*FuncSwing8814only)(PVOID, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); + +typedef struct _TXPWRTRACK_CFG { + u1Byte SwingTableSize_CCK; + u1Byte SwingTableSize_OFDM; + u1Byte Threshold_IQK; + u1Byte Threshold_DPK; + u1Byte AverageThermalNum; + u1Byte RfPathCount; + u4Byte ThermalRegAddr; + FuncSetPwr ODM_TxPwrTrackSetPwr; + FuncIQK DoIQK; + FuncLCK PHY_LCCalibrate; + FuncSwing GetDeltaSwingTable; + FuncSwing8814only GetDeltaSwingTable8814only; +} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG; + +void ConfigureTxpowerTrack( + IN PVOID pDM_VOID, + OUT PTXPWRTRACK_CFG pConfig + ); + + +VOID +ODM_ClearTxPowerTrackingState( + IN PVOID pDM_VOID + ); + +VOID +ODM_TXPowerTrackingCallback_ThermalMeter( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PVOID pDM_VOID +#else + IN PADAPTER Adapter +#endif + ); + + + +#define ODM_TARGET_CHNL_NUM_2G_5G 59 + + +VOID +ODM_ResetIQKResult( + IN PVOID pDM_VOID +); +u1Byte +ODM_GetRightChnlPlaceforIQK( + IN u1Byte chnl +); + +void phydm_rf_init( IN PVOID pDM_VOID); +void phydm_rf_watchdog( IN PVOID pDM_VOID); + +#endif // #ifndef __HAL_PHY_RF_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halphyrf_win.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halphyrf_win.c new file mode 100644 index 000000000..41087bf36 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halphyrf_win.c @@ -0,0 +1,716 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + #include "mp_precomp.h" + #include "phydm_precomp.h" + +//#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + +#define CALCULATE_SWINGTALBE_OFFSET(_offset, _direction, _size, _deltaThermal) \ + do {\ + for(_offset = 0; _offset < _size; _offset++)\ + {\ + if(_deltaThermal < thermalThreshold[_direction][_offset])\ + {\ + if(_offset != 0)\ + _offset--;\ + break;\ + }\ + } \ + if(_offset >= _size)\ + _offset = _size-1;\ + } while(0) + + +void ConfigureTxpowerTrack( + IN PDM_ODM_T pDM_Odm, + OUT PTXPWRTRACK_CFG pConfig + ) +{ +#if RTL8192E_SUPPORT + if(pDM_Odm->SupportICType==ODM_RTL8192E) + ConfigureTxpowerTrack_8192E(pConfig); +#endif +#if RTL8821A_SUPPORT + if(pDM_Odm->SupportICType==ODM_RTL8821) + ConfigureTxpowerTrack_8821A(pConfig); +#endif +#if RTL8812A_SUPPORT + if(pDM_Odm->SupportICType==ODM_RTL8812) + ConfigureTxpowerTrack_8812A(pConfig); +#endif +#if RTL8188E_SUPPORT + if(pDM_Odm->SupportICType==ODM_RTL8188E) + ConfigureTxpowerTrack_8188E(pConfig); +#endif + +#if RTL8188F_SUPPORT + if(pDM_Odm->SupportICType==ODM_RTL8188F) + ConfigureTxpowerTrack_8188F(pConfig); +#endif + +#if RTL8723B_SUPPORT + if(pDM_Odm->SupportICType==ODM_RTL8723B) + ConfigureTxpowerTrack_8723B(pConfig); +#endif + +#if RTL8814A_SUPPORT + if(pDM_Odm->SupportICType==ODM_RTL8814A) + ConfigureTxpowerTrack_8814A(pConfig); +#endif + +#if RTL8821B_SUPPORT + if(pDM_Odm->SupportICType==ODM_RTL8821B) + ConfigureTxpowerTrack_8821B(pConfig); +#endif + +#if RTL8703B_SUPPORT + if(pDM_Odm->SupportICType==ODM_RTL8703B) + ConfigureTxpowerTrack_8703B(pConfig); +#endif + +} + +//====================================================================== +// <20121113, Kordan> This function should be called when TxAGC changed. +// Otherwise the previous compensation is gone, because we record the +// delta of temperature between two TxPowerTracking watch dogs. +// +// NOTE: If Tx BB swing or Tx scaling is varified during run-time, still +// need to call this function. +//====================================================================== +VOID +ODM_ClearTxPowerTrackingState( + IN PDM_ODM_T pDM_Odm + ) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pDM_Odm->Adapter); + u1Byte p = 0; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->DefaultCckIndex; + pRFCalibrateInfo->BbSwingIdxCck = pRFCalibrateInfo->DefaultCckIndex; + pRFCalibrateInfo->CCK_index = 0; + + for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) + { + pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->DefaultOfdmIndex; + pRFCalibrateInfo->BbSwingIdxOfdm[p] = pRFCalibrateInfo->DefaultOfdmIndex; + pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->DefaultOfdmIndex; + + pRFCalibrateInfo->PowerIndexOffset[p] = 0; + pRFCalibrateInfo->DeltaPowerIndex[p] = 0; + pRFCalibrateInfo->DeltaPowerIndexLast[p] = 0; + + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = 0; // Initial Mix mode power tracking + pRFCalibrateInfo->Remnant_OFDMSwingIdx[p] = 0; + pRFCalibrateInfo->KfreeOffset[p] = 0; + } + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA= FALSE; //Initial at Modify Tx Scaling Mode + pRFCalibrateInfo->Modify_TxAGC_Flag_PathB= FALSE; //Initial at Modify Tx Scaling Mode + pRFCalibrateInfo->Modify_TxAGC_Flag_PathC= FALSE; //Initial at Modify Tx Scaling Mode + pRFCalibrateInfo->Modify_TxAGC_Flag_PathD= FALSE; //Initial at Modify Tx Scaling Mode + pRFCalibrateInfo->Remnant_CCKSwingIdx= 0; + pRFCalibrateInfo->ThermalValue = pHalData->EEPROMThermalMeter; + + pRFCalibrateInfo->Modify_TxAGC_Value_CCK=0; //modify by Mingzhi.Guo + pRFCalibrateInfo->Modify_TxAGC_Value_OFDM=0; //modify by Mingzhi.Guo + +} + +VOID +ODM_TXPowerTrackingCallback_ThermalMeter( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER Adapter +#endif + ) +{ + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#else + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + u1Byte ThermalValue = 0, delta, delta_LCK, delta_IQK, p = 0, i = 0, pathName = 0; + s1Byte diff_DPK[4] = {0}; + u1Byte ThermalValue_AVG_count = 0; + u4Byte ThermalValue_AVG = 0; + + u1Byte OFDM_min_index = 0; // OFDM BB Swing should be less than +3.0dB, which is required by Arthur + u1Byte Indexforchannel = 0; // GetRightChnlPlaceforIQK(pHalData->CurrentChannel) + BOOLEAN bTSSIenable = FALSE; + + TXPWRTRACK_CFG c; + + //4 1. The following TWO tables decide the final index of OFDM/CCK swing table. + pu1Byte deltaSwingTableIdx_TUP_A, deltaSwingTableIdx_TDOWN_A; + pu1Byte deltaSwingTableIdx_TUP_B, deltaSwingTableIdx_TDOWN_B; + //for 8814 add by Yu Chen + pu1Byte deltaSwingTableIdx_TUP_C = NULL, deltaSwingTableIdx_TDOWN_C = NULL; + pu1Byte deltaSwingTableIdx_TUP_D= NULL, deltaSwingTableIdx_TDOWN_D = NULL; + + //4 2. Initilization ( 7 steps in total ) + + ConfigureTxpowerTrack(pDM_Odm, &c); + + (*c.GetDeltaSwingTable)(pDM_Odm, (pu1Byte*)&deltaSwingTableIdx_TUP_A, (pu1Byte*)&deltaSwingTableIdx_TDOWN_A, + (pu1Byte*)&deltaSwingTableIdx_TUP_B, (pu1Byte*)&deltaSwingTableIdx_TDOWN_B); + + if(pDM_Odm->SupportICType & ODM_RTL8814A) // for 8814 path C & D + (*c.GetDeltaSwingTable8814only)(pDM_Odm, (pu1Byte*)&deltaSwingTableIdx_TUP_C, (pu1Byte*)&deltaSwingTableIdx_TDOWN_C, + (pu1Byte*)&deltaSwingTableIdx_TUP_D, (pu1Byte*)&deltaSwingTableIdx_TDOWN_D); + + + pRFCalibrateInfo->TXPowerTrackingCallbackCnt++; //cosa add for debug + pRFCalibrateInfo->bTXPowerTrackingInit = TRUE; + +#if (MP_DRIVER == 1) + /*pRFCalibrateInfo->TxPowerTrackControl = pHalData->TxPowerTrackControl; + We should keep updating the control variable according to HalData. + RFCalibrateInfo.RegA24 will be initialized when ODM HW configuring, but MP configures with para files. */ + pRFCalibrateInfo->RegA24 = 0x090e1317; +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("===>ODM_TXPowerTrackingCallback_ThermalMeter, \ + \n pRFCalibrateInfo->BbSwingIdxCckBase: %d, pRFCalibrateInfo->BbSwingIdxOfdmBase[A]: %d, pRFCalibrateInfo->DefaultOfdmIndex: %d\n", + pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->BbSwingIdxOfdmBase[ODM_RF_PATH_A], pRFCalibrateInfo->DefaultOfdmIndex)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("pRFCalibrateInfo->TxPowerTrackControl %d, pHalData->EEPROMThermalMeter %d\n", pRFCalibrateInfo->TxPowerTrackControl, pHalData->EEPROMThermalMeter)); + ThermalValue = (u1Byte)ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, c.ThermalRegAddr, 0xfc00); //0x42: RF Reg[15:10] 88E + + + if( ! pRFCalibrateInfo->TxPowerTrackControl ) + return; + + + //4 3. Initialize ThermalValues of RFCalibrateInfo + + if(pRFCalibrateInfo->bReloadtxpowerindex) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("reload ofdm index for band switch\n")); + } + + //4 4. Calculate average thermal meter + + pRFCalibrateInfo->ThermalValue_AVG[pRFCalibrateInfo->ThermalValue_AVG_index] = ThermalValue; + pRFCalibrateInfo->ThermalValue_AVG_index++; + if(pRFCalibrateInfo->ThermalValue_AVG_index == c.AverageThermalNum) //Average times = c.AverageThermalNum + pRFCalibrateInfo->ThermalValue_AVG_index = 0; + + for(i = 0; i < c.AverageThermalNum; i++) + { + if(pRFCalibrateInfo->ThermalValue_AVG[i]) + { + ThermalValue_AVG += pRFCalibrateInfo->ThermalValue_AVG[i]; + ThermalValue_AVG_count++; + } + } + + if(ThermalValue_AVG_count) //Calculate Average ThermalValue after average enough times + { + ThermalValue = (u1Byte)(ThermalValue_AVG / ThermalValue_AVG_count); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("AVG Thermal Meter = 0x%X, EFUSE Thermal Base = 0x%X\n", ThermalValue, pHalData->EEPROMThermalMeter)); + } + + //4 5. Calculate delta, delta_LCK, delta_IQK. + + //"delta" here is used to determine whether thermal value changes or not. + delta = (ThermalValue > pRFCalibrateInfo->ThermalValue)?(ThermalValue - pRFCalibrateInfo->ThermalValue):(pRFCalibrateInfo->ThermalValue - ThermalValue); + delta_LCK = (ThermalValue > pRFCalibrateInfo->ThermalValue_LCK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_LCK):(pRFCalibrateInfo->ThermalValue_LCK - ThermalValue); + delta_IQK = (ThermalValue > pRFCalibrateInfo->ThermalValue_IQK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_IQK):(pRFCalibrateInfo->ThermalValue_IQK - ThermalValue); + + if(pRFCalibrateInfo->ThermalValue_IQK == 0xff) //no PG, use thermal value for IQK + { + pRFCalibrateInfo->ThermalValue_IQK = ThermalValue; + delta_IQK = (ThermalValue > pRFCalibrateInfo->ThermalValue_IQK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_IQK):(pRFCalibrateInfo->ThermalValue_IQK - ThermalValue); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, use ThermalValue for IQK\n")); + } + + for(p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + { + diff_DPK[p] = (s1Byte)ThermalValue - (s1Byte)pRFCalibrateInfo->DpkThermal[p]; + } + + //4 6. If necessary, do LCK. + + if (!(pDM_Odm->SupportICType & ODM_RTL8821)) { + /*no PG , do LCK at initial status*/ + if (pRFCalibrateInfo->ThermalValue_LCK == 0xff) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("no PG, do LCK\n")); + pRFCalibrateInfo->ThermalValue_LCK = ThermalValue; + if(c.PHY_LCCalibrate) + (*c.PHY_LCCalibrate)(pDM_Odm); + delta_LCK = (ThermalValue > pRFCalibrateInfo->ThermalValue_LCK)?(ThermalValue - pRFCalibrateInfo->ThermalValue_LCK):(pRFCalibrateInfo->ThermalValue_LCK - ThermalValue); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("(delta, delta_LCK, delta_IQK) = (%d, %d, %d)\n", delta, delta_LCK, delta_IQK)); + + /* Delta temperature is equal to or larger than 20 centigrade.*/ + if (delta_LCK >= c.Threshold_IQK) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("delta_LCK(%d) >= Threshold_IQK(%d)\n", delta_LCK, c.Threshold_IQK)); + pRFCalibrateInfo->ThermalValue_LCK = ThermalValue; + if(c.PHY_LCCalibrate) + (*c.PHY_LCCalibrate)(pDM_Odm); + } + } + + //3 7. If necessary, move the index of swing table to adjust Tx power. + + if (delta > 0 && pRFCalibrateInfo->TxPowerTrackControl) + { + //"delta" here is used to record the absolute value of differrence. +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + delta = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue); +#else + delta = (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther)?(ThermalValue - pDM_Odm->priv->pmib->dot11RFEntry.ther):(pDM_Odm->priv->pmib->dot11RFEntry.ther - ThermalValue); +#endif + if (delta >= TXPWR_TRACK_TABLE_SIZE) + delta = TXPWR_TRACK_TABLE_SIZE - 1; + + //4 7.1 The Final Power Index = BaseIndex + PowerIndexOffset + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if(ThermalValue > pHalData->EEPROMThermalMeter) { +#else + if(ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) { +#endif + + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + { + pRFCalibrateInfo->DeltaPowerIndexLast[p] = pRFCalibrateInfo->DeltaPowerIndex[p]; //recording poer index offset + switch(p) + { + case ODM_RF_PATH_B: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_B[%d] = %d\n", delta, deltaSwingTableIdx_TUP_B[delta])); + + pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_B[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_B[delta]; // Record delta swing for mix mode power tracking + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + case ODM_RF_PATH_C: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_C[%d] = %d\n", delta, deltaSwingTableIdx_TUP_C[delta])); + + pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_C[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_C[delta]; // Record delta swing for mix mode power tracking + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + case ODM_RF_PATH_D: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_D[%d] = %d\n", delta, deltaSwingTableIdx_TUP_D[delta])); + + pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_D[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_D[delta]; // Record delta swing for mix mode power tracking + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TUP_A[%d] = %d\n", delta, deltaSwingTableIdx_TUP_A[delta])); + + pRFCalibrateInfo->DeltaPowerIndex[p] = deltaSwingTableIdx_TUP_A[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = deltaSwingTableIdx_TUP_A[delta]; // Record delta swing for mix mode power tracking + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is higher and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + } + + } + + } + else { + + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + { + pRFCalibrateInfo->DeltaPowerIndexLast[p] = pRFCalibrateInfo->DeltaPowerIndex[p]; //recording poer index offset + switch(p) + { + case ODM_RF_PATH_B: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_B[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_B[delta])); + pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_B[delta]; // Record delta swing for mix mode power tracking + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_B] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + case ODM_RF_PATH_C: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_C[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_C[delta])); + pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_C[delta]; // Record delta swing for mix mode power tracking + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_C] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + case ODM_RF_PATH_D: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_D[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_D[delta])); + pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_D[delta]; // Record delta swing for mix mode power tracking + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_D] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("deltaSwingTableIdx_TDOWN_A[%d] = %d\n", delta, deltaSwingTableIdx_TDOWN_A[delta])); + pRFCalibrateInfo->DeltaPowerIndex[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; + pRFCalibrateInfo->Absolute_OFDMSwingIdx[p] = -1 * deltaSwingTableIdx_TDOWN_A[delta]; // Record delta swing for mix mode power tracking + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Temp is lower and pRFCalibrateInfo->Absolute_OFDMSwingIdx[ODM_RF_PATH_A] = %d\n", pRFCalibrateInfo->Absolute_OFDMSwingIdx[p])); + break; + } + + } + + } + + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("\n\n=========================== [Path-%d] Calculating PowerIndexOffset===========================\n", p)); + + if(pRFCalibrateInfo->DeltaPowerIndex[p] == pRFCalibrateInfo->DeltaPowerIndexLast[p]) // If Thermal value changes but lookup table value still the same + pRFCalibrateInfo->PowerIndexOffset[p] = 0; + else + pRFCalibrateInfo->PowerIndexOffset[p] = pRFCalibrateInfo->DeltaPowerIndex[p] - pRFCalibrateInfo->DeltaPowerIndexLast[p]; // Power Index Diff between 2 times Power Tracking + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("[Path-%d] PowerIndexOffset(%d) = DeltaPowerIndex(%d) - DeltaPowerIndexLast(%d)\n", p, pRFCalibrateInfo->PowerIndexOffset[p], pRFCalibrateInfo->DeltaPowerIndex[p], pRFCalibrateInfo->DeltaPowerIndexLast[p])); + + pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->BbSwingIdxOfdmBase[p] + pRFCalibrateInfo->PowerIndexOffset[p]; + pRFCalibrateInfo->CCK_index = pRFCalibrateInfo->BbSwingIdxCckBase + pRFCalibrateInfo->PowerIndexOffset[p]; + + pRFCalibrateInfo->BbSwingIdxCck = pRFCalibrateInfo->CCK_index; + pRFCalibrateInfo->BbSwingIdxOfdm[p] = pRFCalibrateInfo->OFDM_index[p]; + + // *************Print BB Swing Base and Index Offset************* + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("The 'CCK' final index(%d) = BaseIndex(%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxCck, pRFCalibrateInfo->BbSwingIdxCckBase, pRFCalibrateInfo->PowerIndexOffset[p])); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("The 'OFDM' final index(%d) = BaseIndex[%d](%d) + PowerIndexOffset(%d)\n", pRFCalibrateInfo->BbSwingIdxOfdm[p], p, pRFCalibrateInfo->BbSwingIdxOfdmBase[p], pRFCalibrateInfo->PowerIndexOffset[p])); + + //4 7.1 Handle boundary conditions of index. + + if(pRFCalibrateInfo->OFDM_index[p] > c.SwingTableSize_OFDM-1) + { + pRFCalibrateInfo->OFDM_index[p] = c.SwingTableSize_OFDM-1; + } + else if (pRFCalibrateInfo->OFDM_index[p] <= OFDM_min_index) + { + pRFCalibrateInfo->OFDM_index[p] = OFDM_min_index; + } + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("\n\n========================================================================================================\n")); + if(pRFCalibrateInfo->CCK_index > c.SwingTableSize_CCK-1) + pRFCalibrateInfo->CCK_index = c.SwingTableSize_CCK-1; + else if (pRFCalibrateInfo->CCK_index <= 0) + pRFCalibrateInfo->CCK_index = 0; + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("The thermal meter is unchanged or TxPowerTracking OFF(%d): ThermalValue: %d , pRFCalibrateInfo->ThermalValue: %d\n", + pRFCalibrateInfo->TxPowerTrackControl, ThermalValue, pRFCalibrateInfo->ThermalValue)); + + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + pRFCalibrateInfo->PowerIndexOffset[p] = 0; + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TxPowerTracking: [CCK] Swing Current Index: %d, Swing Base Index: %d\n", + pRFCalibrateInfo->CCK_index, pRFCalibrateInfo->BbSwingIdxCckBase)); //Print Swing base & current + + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("TxPowerTracking: [OFDM] Swing Current Index: %d, Swing Base Index[%d]: %d\n", + pRFCalibrateInfo->OFDM_index[p], p, pRFCalibrateInfo->BbSwingIdxOfdmBase[p])); + } + + if ((pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_A] != 0 || + pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_B] != 0 || + pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_C] != 0 || + pRFCalibrateInfo->PowerIndexOffset[ODM_RF_PATH_D] != 0) && + pRFCalibrateInfo->TxPowerTrackControl && (pHalData->EEPROMThermalMeter != 0xff)) + { + //4 7.2 Configure the Swing Table to adjust Tx Power. + + pRFCalibrateInfo->bTxPowerChanged = TRUE; // Always TRUE after Tx Power is adjusted by power tracking. + // + // 2012/04/23 MH According to Luke's suggestion, we can not write BB digital + // to increase TX power. Otherwise, EVM will be bad. + // + // 2012/04/25 MH Add for tx power tracking to set tx power in tx agc for 88E. + if (ThermalValue > pRFCalibrateInfo->ThermalValue) + { + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature Increasing(%d): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + p, pRFCalibrateInfo->PowerIndexOffset[p], delta, ThermalValue, pHalData->EEPROMThermalMeter, pRFCalibrateInfo->ThermalValue)); + } + } + + else if (ThermalValue < pRFCalibrateInfo->ThermalValue)// Low temperature + { + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature Decreasing(%d): delta_pi: %d , delta_t: %d, Now_t: %d, EFUSE_t: %d, Last_t: %d\n", + p, pRFCalibrateInfo->PowerIndexOffset[p], delta, ThermalValue, pHalData->EEPROMThermalMeter, pRFCalibrateInfo->ThermalValue)); + } + } + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (ThermalValue > pHalData->EEPROMThermalMeter) +#else + if (ThermalValue > pDM_Odm->priv->pmib->dot11RFEntry.ther) +#endif + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) higher than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); + + if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E ||pDM_Odm->SupportICType == ODM_RTL8821 || + pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8814A || pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8188F) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("**********Enter POWER Tracking MIX_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, 0); + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("**********Enter POWER Tracking BBSWING_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel); + } + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("Temperature(%d) lower than PG value(%d)\n", ThermalValue, pHalData->EEPROMThermalMeter)); + + if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8821 || + pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8814A || pDM_Odm->SupportICType == ODM_RTL8703B || pDM_Odm->SupportICType == ODM_RTL8188F) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("**********Enter POWER Tracking MIX_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, MIX_MODE, p, Indexforchannel); + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("**********Enter POWER Tracking BBSWING_MODE**********\n")); + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + (*c.ODM_TxPwrTrackSetPwr)(pDM_Odm, BBSWING, p, Indexforchannel); + } + + } + + pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->BbSwingIdxCck; // Record last time Power Tracking result as base. + for (p = ODM_RF_PATH_A; p < c.RfPathCount; p++) + pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->BbSwingIdxOfdm[p]; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("pRFCalibrateInfo->ThermalValue = %d ThermalValue= %d\n", pRFCalibrateInfo->ThermalValue, ThermalValue)); + + pRFCalibrateInfo->ThermalValue = ThermalValue; //Record last Power Tracking Thermal Value + + } + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + if(!IS_HARDWARE_TYPE_8723B(Adapter)) + { + // Delta temperature is equal to or larger than 20 centigrade (When threshold is 8). + if ((delta_IQK >= c.Threshold_IQK)) { + if ( ! pRFCalibrateInfo->bIQKInProgress) + (*c.DoIQK)(pDM_Odm, delta_IQK, ThermalValue, 8); + } + } + if (pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_A] != 0) { + if ((diff_DPK[ODM_RF_PATH_A] >= c.Threshold_DPK)) { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, (diff_DPK[ODM_RF_PATH_A] / c.Threshold_DPK)); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + } else if ((diff_DPK[ODM_RF_PATH_A] <= -1 * c.Threshold_DPK)) { + s4Byte value = 0x20 + (diff_DPK[ODM_RF_PATH_A] / c.Threshold_DPK); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, value); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + } else { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xcc4, BIT14|BIT13|BIT12|BIT11|BIT10, 0); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + } + } + if (pRFCalibrateInfo->DpkThermal[ODM_RF_PATH_B] != 0) { + if ((diff_DPK[ODM_RF_PATH_B] >= c.Threshold_DPK)) { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, (diff_DPK[ODM_RF_PATH_B] / c.Threshold_DPK)); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + } else if ((diff_DPK[ODM_RF_PATH_B] <= -1 * c.Threshold_DPK)) { + s4Byte value = 0x20 + (diff_DPK[ODM_RF_PATH_B] / c.Threshold_DPK); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, value); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + } else { + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x1); + ODM_SetBBReg(pDM_Odm, 0xec4, BIT14|BIT13|BIT12|BIT11|BIT10, 0); + ODM_SetBBReg(pDM_Odm, 0x82c, BIT(31), 0x0); + } + } + +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("<===ODM_TXPowerTrackingCallback_ThermalMeter\n")); + + pRFCalibrateInfo->TXPowercount = 0; +} + + + +//3============================================================ +//3 IQ Calibration +//3============================================================ + +VOID +ODM_ResetIQKResult( + IN PDM_ODM_T pDM_Odm +) +{ + return; +} +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +u1Byte ODM_GetRightChnlPlaceforIQK(u1Byte chnl) +{ + u1Byte channel_all[ODM_TARGET_CHNL_NUM_2G_5G] = + {1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,100,102,104,106,108,110,112,114,116,118,120,122,124,126,128,130,132,134,136,138,140,149,151,153,155,157,159,161,163,165}; + u1Byte place = chnl; + + + if(chnl > 14) + { + for(place = 14; placeAdapter; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (*pDM_Odm->pIsFcsModeEnable) + return; +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if (!IS_HARDWARE_TYPE_JAGUAR(Adapter)) + return; +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + else if (IS_HARDWARE_TYPE_8812AU(Adapter)) + return; +#endif +#endif + +#if (RTL8821A_SUPPORT == 1) + if (pDM_Odm->bLinked) { + if ((*pDM_Odm->pChannel != pDM_Odm->preChannel) && (!*pDM_Odm->pbScanInProcess)) { + pDM_Odm->preChannel = *pDM_Odm->pChannel; + pDM_Odm->LinkedInterval = 0; + } + + if (pDM_Odm->LinkedInterval < 3) + pDM_Odm->LinkedInterval++; + + if (pDM_Odm->LinkedInterval == 2) { + /*Mark out IQK flow to prevent tx stuck. by Maddest 20130306*/ + /*Open it verified by James 20130715*/ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PHY_IQCalibrate_8821A(pDM_Odm, FALSE); +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHY_IQCalibrate(Adapter, FALSE); +#else + PHY_IQCalibrate_8821A(Adapter, FALSE); +#endif + } + } else + pDM_Odm->LinkedInterval = 0; +#endif +} + +void phydm_rf_init(IN PDM_ODM_T pDM_Odm) +{ + + odm_TXPowerTrackingInit(pDM_Odm); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + ODM_ClearTxPowerTrackingState(pDM_Odm); +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#if (RTL8814A_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8814A) + PHY_IQCalibrate_8814A_Init(pDM_Odm); +#endif +#endif + +} + +void phydm_rf_watchdog(IN PDM_ODM_T pDM_Odm) +{ + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + ODM_TXPowerTrackingCheck(pDM_Odm); + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + odm_IQCalibrate(pDM_Odm); +#endif +} \ No newline at end of file diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halphyrf_win.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halphyrf_win.h new file mode 100644 index 000000000..aa20db1b7 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/halphyrf_win.h @@ -0,0 +1,108 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + #ifndef __HAL_PHY_RF_H__ + #define __HAL_PHY_RF_H__ + +#include "phydm_kfree.h" +#if (RTL8814A_SUPPORT == 1) +#include "rtl8814a/phydm_iqk_8814a.h" +#endif + +#if (RTL8822B_SUPPORT == 1) +#include "rtl8822b/phydm_iqk_8822b.h" +#endif +#include "phydm_powertracking_win.h" + +typedef enum _SPUR_CAL_METHOD { + PLL_RESET, + AFE_PHASE_SEL +} SPUR_CAL_METHOD; + +typedef enum _PWRTRACK_CONTROL_METHOD { + BBSWING, + TXAGC, + MIX_MODE, + TSSI_MODE +} PWRTRACK_METHOD; + +typedef VOID (*FuncSetPwr)(PDM_ODM_T, PWRTRACK_METHOD, u1Byte, u1Byte); +typedef VOID(*FuncIQK)(PVOID, u1Byte, u1Byte, u1Byte); +typedef VOID (*FuncLCK)(PDM_ODM_T); + //refine by YuChen for 8814A +typedef VOID (*FuncSwing)(PDM_ODM_T, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); +typedef VOID (*FuncSwing8814only)(PDM_ODM_T, pu1Byte*, pu1Byte*, pu1Byte*, pu1Byte*); + +typedef struct _TXPWRTRACK_CFG { + u1Byte SwingTableSize_CCK; + u1Byte SwingTableSize_OFDM; + u1Byte Threshold_IQK; + u1Byte Threshold_DPK; + u1Byte AverageThermalNum; + u1Byte RfPathCount; + u4Byte ThermalRegAddr; + FuncSetPwr ODM_TxPwrTrackSetPwr; + FuncIQK DoIQK; + FuncLCK PHY_LCCalibrate; + FuncSwing GetDeltaSwingTable; + FuncSwing8814only GetDeltaSwingTable8814only; +} TXPWRTRACK_CFG, *PTXPWRTRACK_CFG; + +VOID +ConfigureTxpowerTrack( + IN PDM_ODM_T pDM_Odm, + OUT PTXPWRTRACK_CFG pConfig + ); + + +VOID +ODM_ClearTxPowerTrackingState( + IN PDM_ODM_T pDM_Odm + ); + +VOID +ODM_TXPowerTrackingCallback_ThermalMeter( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER Adapter +#endif + ); + + + +#define ODM_TARGET_CHNL_NUM_2G_5G 59 + + +VOID +ODM_ResetIQKResult( + IN PDM_ODM_T pDM_Odm +); +u1Byte +ODM_GetRightChnlPlaceforIQK( + IN u1Byte chnl +); + +VOID odm_IQCalibrate(IN PDM_ODM_T pDM_Odm); +VOID phydm_rf_init( IN PDM_ODM_T pDM_Odm); +VOID phydm_rf_watchdog( IN PDM_ODM_T pDM_Odm); + +#endif // #ifndef __HAL_PHY_RF_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/mp_precomp.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/mp_precomp.h new file mode 100644 index 000000000..2e950cb2e --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/mp_precomp.h @@ -0,0 +1,20 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm.c new file mode 100644 index 000000000..d80c163aa --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm.c @@ -0,0 +1,2165 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +const u2Byte dB_Invert_Table[12][8] = { + { 1, 1, 1, 2, 2, 2, 2, 3}, + { 3, 3, 4, 4, 4, 5, 6, 6}, + { 7, 8, 9, 10, 11, 13, 14, 16}, + { 18, 20, 22, 25, 28, 32, 35, 40}, + { 45, 50, 56, 63, 71, 79, 89, 100}, + { 112, 126, 141, 158, 178, 200, 224, 251}, + { 282, 316, 355, 398, 447, 501, 562, 631}, + { 708, 794, 891, 1000, 1122, 1259, 1413, 1585}, + { 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981}, + { 4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000}, + { 11220, 12589, 14125, 15849, 17783, 19953, 22387, 25119}, + { 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535} +}; + + +//============================================================ +// Local Function predefine. +//============================================================ + +/* START------------COMMON INFO RELATED--------------- */ + +VOID +odm_GlobalAdapterCheck( + IN VOID + ); + +//move to odm_PowerTacking.h by YuChen + + + +VOID +odm_UpdatePowerTrainingState( + IN PDM_ODM_T pDM_Odm +); + +//============================================================ +//3 Export Interface +//============================================================ + +/*Y = 10*log(X)*/ +s4Byte +ODM_PWdB_Conversion( + IN s4Byte X, + IN u4Byte TotalBit, + IN u4Byte DecimalBit + ) +{ + s4Byte Y, integer = 0, decimal = 0; + u4Byte i; + + if(X == 0) + X = 1; // log2(x), x can't be 0 + + for(i = (TotalBit-1); i > 0; i--) + { + if(X & BIT(i)) + { + integer = i; + if(i > 0) + decimal = (X & BIT(i-1))?2:0; //decimal is 0.5dB*3=1.5dB~=2dB + break; + } + } + + Y = 3*(integer-DecimalBit)+decimal; //10*log(x)=3*log2(x), + + return Y; +} + +s4Byte +ODM_SignConversion( + IN s4Byte value, + IN u4Byte TotalBit + ) +{ + if(value&BIT(TotalBit-1)) + value -= BIT(TotalBit); + return value; +} + +VOID +ODM_InitMpDriverStatus( + IN PDM_ODM_T pDM_Odm +) +{ +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + + // Decide when compile time + #if(MP_DRIVER == 1) + pDM_Odm->mp_mode = TRUE; + #else + pDM_Odm->mp_mode = FALSE; + #endif + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + + PADAPTER Adapter = pDM_Odm->Adapter; + + // Update information every period + pDM_Odm->mp_mode = (BOOLEAN)Adapter->registrypriv.mp_mode; + +#else + + // MP mode is always false at AP side + pDM_Odm->mp_mode = FALSE; + +#endif +} + +VOID +ODM_UpdateMpDriverStatus( + IN PDM_ODM_T pDM_Odm +) +{ +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + + // Do nothing. + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + + // Update information erery period + pDM_Odm->mp_mode = (BOOLEAN)Adapter->registrypriv.mp_mode; + +#else + + // Do nothing. + +#endif +} + +VOID +PHYDM_InitTRXAntennaSetting( + IN PDM_ODM_T pDM_Odm +) +{ +#if (RTL8814A_SUPPORT == 1) + + if (pDM_Odm->SupportICType & (ODM_RTL8814A)) { + u1Byte RxAnt = 0, TxAnt = 0; + + RxAnt = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG(BB_RX_PATH, pDM_Odm), ODM_BIT(BB_RX_PATH, pDM_Odm)); + TxAnt = (u1Byte)ODM_GetBBReg(pDM_Odm, ODM_REG(BB_TX_PATH, pDM_Odm), ODM_BIT(BB_TX_PATH, pDM_Odm)); + pDM_Odm->TXAntStatus = (TxAnt & 0xf); + pDM_Odm->RXAntStatus = (RxAnt & 0xf); + } +#endif +} + +VOID +phydm_Init_cck_setting( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte value_824,value_82c; + + pDM_Odm->bCckHighPower = (BOOLEAN) ODM_GetBBReg(pDM_Odm, ODM_REG(CCK_RPT_FORMAT,pDM_Odm), ODM_BIT(CCK_RPT_FORMAT,pDM_Odm)); + + #if (RTL8192E_SUPPORT == 1) + if(pDM_Odm->SupportICType & (ODM_RTL8192E)) + { + /* 0x824[9] = 0x82C[9] = 0xA80[7] these regiaters settinh should be equal or CCK RSSI report may inaccurate */ + value_824 = ODM_GetBBReg(pDM_Odm, 0x824, BIT9); + value_82c = ODM_GetBBReg(pDM_Odm, 0x82c, BIT9); + + if(value_824 != value_82c) + { + ODM_SetBBReg(pDM_Odm, 0x82c , BIT9, value_824); + } + ODM_SetBBReg(pDM_Odm, 0xa80 , BIT7, value_824); + pDM_Odm->cck_agc_report_type = (BOOLEAN)value_824; + } + #endif + + #if (RTL8703B_SUPPORT == 1) + if (pDM_Odm->SupportICType & (ODM_RTL8703B)) { + + pDM_Odm->cck_agc_report_type = ODM_GetBBReg(pDM_Odm, 0x950, BIT11) ? 1 : 0; /*1: 4bit LNA , 0: 3bit LNA */ + + if (pDM_Odm->cck_agc_report_type != 1) { + DbgPrint("[Warning] 8703B CCK should be 4bit LNA, ie. 0x950[11] = 1\n"); + /**/ + } + } + #endif + +} + +u1Byte DummyHubUsbMode = 1;/* USB 2.0 */ +void phydm_hook_dummy_member( + IN PDM_ODM_T pDM_Odm + ) +{ + if (pDM_Odm->HubUsbMode == NULL) + pDM_Odm->HubUsbMode = &DummyHubUsbMode; +} + + +VOID +odm_CommonInfoSelfInit( + IN PDM_ODM_T pDM_Odm + ) +{ + phydm_Init_cck_setting(pDM_Odm); + pDM_Odm->RFPathRxEnable = (u1Byte) ODM_GetBBReg(pDM_Odm, ODM_REG(BB_RX_PATH,pDM_Odm), ODM_BIT(BB_RX_PATH,pDM_Odm)); +#if (DM_ODM_SUPPORT_TYPE != ODM_CE) + pDM_Odm->pbNet_closed = &pDM_Odm->BOOLEAN_temp; +#endif + + PHYDM_InitDebugSetting(pDM_Odm); + ODM_InitMpDriverStatus(pDM_Odm); + PHYDM_InitTRXAntennaSetting(pDM_Odm); + + pDM_Odm->TxRate = 0xFF; + + pDM_Odm->number_linked_client = 0; + pDM_Odm->pre_number_linked_client = 0; + pDM_Odm->number_active_client = 0; + pDM_Odm->pre_number_active_client = 0; + phydm_hook_dummy_member(pDM_Odm); + +} + +VOID +odm_CommonInfoSelfUpdate( + IN PDM_ODM_T pDM_Odm + ) +{ + u1Byte EntryCnt = 0, num_active_client = 0; + u4Byte i, OneEntry_MACID = 0, ma_rx_tp = 0; + PSTA_INFO_T pEntry; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + + pEntry = pDM_Odm->pODM_StaInfo[0]; + if(pMgntInfo->mAssoc) + { + pEntry->bUsed=TRUE; + for (i=0; i<6; i++) + pEntry->MacAddr[i] = pMgntInfo->Bssid[i]; + } + else + { + pEntry->bUsed=FALSE; + for (i=0; i<6; i++) + pEntry->MacAddr[i] = 0; + } + + //STA mode is linked to AP + if(IS_STA_VALID(pDM_Odm->pODM_StaInfo[0]) && !ACTING_AS_AP(Adapter)) + pDM_Odm->bsta_state = TRUE; + else + pDM_Odm->bsta_state = FALSE; +#endif + +/* THis variable cannot be used because it is wrong*/ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + if (*(pDM_Odm->pBandWidth) == ODM_BW40M) + { + if (*(pDM_Odm->pSecChOffset) == 1) + pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 2; + else if (*(pDM_Odm->pSecChOffset) == 2) + pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 2; + } else if (*(pDM_Odm->pBandWidth) == ODM_BW80M) { + if (*(pDM_Odm->pSecChOffset) == 1) + pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 6; + else if (*(pDM_Odm->pSecChOffset) == 2) + pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 6; + } else + pDM_Odm->ControlChannel = *(pDM_Odm->pChannel); +#else + if (*(pDM_Odm->pBandWidth) == ODM_BW40M) { + if (*(pDM_Odm->pSecChOffset) == 1) + pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 2; + else if (*(pDM_Odm->pSecChOffset) == 2) + pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 2; + } else + pDM_Odm->ControlChannel = *(pDM_Odm->pChannel); +#endif + + for (i=0; ipODM_StaInfo[i]; + if(IS_STA_VALID(pEntry)) + { + EntryCnt++; + if(EntryCnt==1) + { + OneEntry_MACID=i; + } + + #if (DM_ODM_SUPPORT_TYPE == ODM_AP) + ma_rx_tp = (pEntry->rx_byte_cnt_LowMAW)<<3; /* low moving average RX TP ( bit /sec)*/ + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("ClientTP[%d]: ((%d )) bit/sec\n", i, ma_rx_tp)); + + if (ma_rx_tp > ACTIVE_TP_THRESHOLD) + num_active_client++; + #endif + } + } + + if(EntryCnt == 1) + { + pDM_Odm->bOneEntryOnly = TRUE; + pDM_Odm->OneEntry_MACID=OneEntry_MACID; + } + else + pDM_Odm->bOneEntryOnly = FALSE; + + pDM_Odm->pre_number_linked_client = pDM_Odm->number_linked_client; + pDM_Odm->pre_number_active_client = pDM_Odm->number_active_client; + + pDM_Odm->number_linked_client = EntryCnt; + pDM_Odm->number_active_client = num_active_client; + + /* Update MP driver status*/ + ODM_UpdateMpDriverStatus(pDM_Odm); +} + +VOID +odm_CommonInfoSelfReset( + IN PDM_ODM_T pDM_Odm + ) +{ +#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + pDM_Odm->PhyDbgInfo.NumQryBeaconPkt = 0; +#endif +} + +PVOID +PhyDM_Get_Structure( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Structure_Type +) + +{ + PVOID pStruct = NULL; +#if RTL8195A_SUPPORT + switch (Structure_Type){ + case PHYDM_FALSEALMCNT: + pStruct = &FalseAlmCnt; + break; + + case PHYDM_CFOTRACK: + pStruct = &DM_CfoTrack; + break; + + case PHYDM_ADAPTIVITY: + pStruct = &(pDM_Odm->Adaptivity); + break; + + default: + break; + } + +#else + switch (Structure_Type){ + case PHYDM_FALSEALMCNT: + pStruct = &(pDM_Odm->FalseAlmCnt); + break; + + case PHYDM_CFOTRACK: + pStruct = &(pDM_Odm->DM_CfoTrack); + break; + + case PHYDM_ADAPTIVITY: + pStruct = &(pDM_Odm->Adaptivity); + break; + + default: + break; + } + +#endif + return pStruct; +} + +VOID +odm_HWSetting( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (RTL8821A_SUPPORT == 1) + if(pDM_Odm->SupportICType & ODM_RTL8821) + odm_HWSetting_8821A(pDM_Odm); +#endif + +} + +// +// 2011/09/21 MH Add to describe different team necessary resource allocate?? +// +VOID +ODM_DMInit( + IN PDM_ODM_T pDM_Odm + ) +{ + odm_CommonInfoSelfInit(pDM_Odm); + odm_DIGInit(pDM_Odm); + Phydm_NHMCounterStatisticsInit(pDM_Odm); + Phydm_AdaptivityInit(pDM_Odm); + phydm_ra_info_init(pDM_Odm); + odm_RateAdaptiveMaskInit(pDM_Odm); + odm_RA_ParaAdjust_init(pDM_Odm); + ODM_CfoTrackingInit(pDM_Odm); + ODM_EdcaTurboInit(pDM_Odm); + odm_RSSIMonitorInit(pDM_Odm); + phydm_rf_init(pDM_Odm); + odm_TXPowerTrackingInit(pDM_Odm); + odm_AntennaDiversityInit(pDM_Odm); + odm_AutoChannelSelectInit(pDM_Odm); + odm_PathDiversityInit(pDM_Odm); +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + phydm_Beamforming_Init(pDM_Odm); +#endif + + if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + { + odm_DynamicBBPowerSavingInit(pDM_Odm); + odm_DynamicTxPowerInit(pDM_Odm); + +#if (RTL8188E_SUPPORT == 1) + if(pDM_Odm->SupportICType==ODM_RTL8188E) + { + odm_PrimaryCCA_Init(pDM_Odm); + ODM_RAInfo_Init_all(pDM_Odm); + } +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + + #if (RTL8723B_SUPPORT == 1) + if(pDM_Odm->SupportICType == ODM_RTL8723B) + odm_SwAntDetectInit(pDM_Odm); + #endif + + #if (RTL8192E_SUPPORT == 1) + if(pDM_Odm->SupportICType==ODM_RTL8192E) + odm_PrimaryCCA_Check_Init(pDM_Odm); + #endif + +#endif + + } + +} + +VOID +ODM_DMReset( + IN PDM_ODM_T pDM_Odm + ) +{ + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + + ODM_AntDivReset(pDM_Odm); + phydm_setEDCCAThresholdAPI(pDM_Odm, pDM_DigTable->CurIGValue); +} + + +VOID +phydm_support_ablity_debug( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte pre_support_ability; + u4Byte used = *_used; + u4Byte out_len = *_out_len; + + pre_support_ability = pDM_Odm->SupportAbility ; + PHYDM_SNPRINTF((output+used, out_len-used,"\n%s\n", "================================")); + if(dm_value[0] == 100) + { + PHYDM_SNPRINTF((output+used, out_len-used, "[Supportablity] PhyDM Selection\n")); + PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "================================")); + PHYDM_SNPRINTF((output+used, out_len-used, "00. (( %s ))DIG \n", ((pDM_Odm->SupportAbility & ODM_BB_DIG)?("V"):(".")) )); + PHYDM_SNPRINTF((output+used, out_len-used, "01. (( %s ))RA_MASK \n", ((pDM_Odm->SupportAbility & ODM_BB_RA_MASK)?("V"):(".")) )); + PHYDM_SNPRINTF((output+used, out_len-used, "02. (( %s ))DYNAMIC_TXPWR \n", ((pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)?("V"):(".")) )); + PHYDM_SNPRINTF((output+used, out_len-used, "03. (( %s ))FA_CNT \n", ((pDM_Odm->SupportAbility & ODM_BB_FA_CNT)?("V"):(".")) )); + PHYDM_SNPRINTF((output+used, out_len-used, "04. (( %s ))RSSI_MONITOR \n", ((pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR)?("V"):(".")) )); + PHYDM_SNPRINTF((output+used, out_len-used, "05. (( %s ))CCK_PD \n", ((pDM_Odm->SupportAbility & ODM_BB_CCK_PD)?("V"):(".")) )); + PHYDM_SNPRINTF((output+used, out_len-used, "06. (( %s ))ANT_DIV \n", ((pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)?("V"):(".")) )); + PHYDM_SNPRINTF((output+used, out_len-used, "07. (( %s ))PWR_SAVE \n", ((pDM_Odm->SupportAbility & ODM_BB_PWR_SAVE)?("V"):(".")) )); + PHYDM_SNPRINTF((output+used, out_len-used, "08. (( %s ))PWR_TRAIN \n", ((pDM_Odm->SupportAbility & ODM_BB_PWR_TRAIN)?("V"):(".")) )); + PHYDM_SNPRINTF((output+used, out_len-used, "09. (( %s ))RATE_ADAPTIVE \n", ((pDM_Odm->SupportAbility & ODM_BB_RATE_ADAPTIVE)?("V"):(".")) )); + PHYDM_SNPRINTF((output+used, out_len-used, "10. (( %s ))PATH_DIV \n", ((pDM_Odm->SupportAbility & ODM_BB_PATH_DIV)?("V"):(".")))); + PHYDM_SNPRINTF((output+used, out_len-used, "11. (( %s ))PSD \n", ((pDM_Odm->SupportAbility & ODM_BB_PSD)?("V"):(".")) )); + PHYDM_SNPRINTF((output+used, out_len-used, "12. (( %s ))RXHP \n", ((pDM_Odm->SupportAbility & ODM_BB_RXHP)?("V"):(".")) )); + PHYDM_SNPRINTF((output+used, out_len-used, "13. (( %s ))ADAPTIVITY \n", ((pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY)?("V"):(".")) )); + PHYDM_SNPRINTF((output+used, out_len-used, "14. (( %s ))CFO_TRACKING \n", ((pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING)?("V"):(".")) )); + PHYDM_SNPRINTF((output+used, out_len-used, "15. (( %s ))NHM_CNT \n", ((pDM_Odm->SupportAbility & ODM_BB_NHM_CNT)?("V"):(".")) )); + PHYDM_SNPRINTF((output+used, out_len-used, "16. (( %s ))PRIMARY_CCA \n", ((pDM_Odm->SupportAbility & ODM_BB_PRIMARY_CCA)?("V"):(".")) )); + PHYDM_SNPRINTF((output+used, out_len-used, "20. (( %s ))EDCA_TURBO \n", ((pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO)?("V"):(".")) )); + PHYDM_SNPRINTF((output+used, out_len-used, "21. (( %s ))EARLY_MODE \n", ((pDM_Odm->SupportAbility & ODM_MAC_EARLY_MODE)?("V"):(".")) )); + PHYDM_SNPRINTF((output+used, out_len-used, "24. (( %s ))TX_PWR_TRACK \n", ((pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)?("V"):(".")) )); + PHYDM_SNPRINTF((output+used, out_len-used, "25. (( %s ))RX_GAIN_TRACK \n", ((pDM_Odm->SupportAbility & ODM_RF_RX_GAIN_TRACK)?("V"):(".")) )); + PHYDM_SNPRINTF((output+used, out_len-used, "26. (( %s ))RF_CALIBRATION \n", ((pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)?("V"):(".")) )); + PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "================================")); + } + /* + else if(dm_value[0] == 101) + { + pDM_Odm->SupportAbility = 0 ; + DbgPrint("Disable all SupportAbility components \n"); + PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "Disable all SupportAbility components")); + } + */ + else + { + + if(dm_value[1] == 1) //enable + { + pDM_Odm->SupportAbility |= BIT(dm_value[0]) ; + if(BIT(dm_value[0]) & ODM_BB_PATH_DIV) + { + odm_PathDiversityInit(pDM_Odm); + } + } + else if(dm_value[1] == 2) //disable + { + pDM_Odm->SupportAbility &= ~(BIT(dm_value[0])) ; + } + else + { + //DbgPrint("\n[Warning!!!] 1:enable, 2:disable \n\n"); + PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "[Warning!!!] 1:enable, 2:disable")); + } + } + PHYDM_SNPRINTF((output+used, out_len-used,"pre-SupportAbility = 0x%x\n", pre_support_ability )); + PHYDM_SNPRINTF((output+used, out_len-used,"Curr-SupportAbility = 0x%x\n", pDM_Odm->SupportAbility )); + PHYDM_SNPRINTF((output+used, out_len-used,"%s\n", "================================")); +} + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +// +//tmp modify for LC Only +// +VOID +ODM_DMWatchdog_LPS( + IN PDM_ODM_T pDM_Odm + ) +{ + odm_CommonInfoSelfUpdate(pDM_Odm); + odm_FalseAlarmCounterStatistics(pDM_Odm); + odm_RSSIMonitorCheck(pDM_Odm); + odm_DIGbyRSSI_LPS(pDM_Odm); + odm_CCKPacketDetectionThresh(pDM_Odm); + odm_CommonInfoSelfReset(pDM_Odm); + + if(*(pDM_Odm->pbPowerSaving)==TRUE) + return; +} +#endif +// +// 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. +// You can not add any dummy function here, be care, you can only use DM structure +// to perform any new ODM_DM. +// +VOID +ODM_DMWatchdog( + IN PDM_ODM_T pDM_Odm + ) +{ + odm_CommonInfoSelfUpdate(pDM_Odm); + phydm_BasicDbgMessage(pDM_Odm); + odm_HWSetting(pDM_Odm); + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + { + prtl8192cd_priv priv = pDM_Odm->priv; + if( (priv->auto_channel != 0) && (priv->auto_channel != 2) )//if ACS running, do not do FA/CCA counter read + return; + } +#endif + odm_FalseAlarmCounterStatistics(pDM_Odm); + phydm_NoisyDetection(pDM_Odm); + + odm_RSSIMonitorCheck(pDM_Odm); + + if(*(pDM_Odm->pbPowerSaving) == TRUE) + { + odm_DIGbyRSSI_LPS(pDM_Odm); + { + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + Phydm_Adaptivity(pDM_Odm, pDM_DigTable->CurIGValue); + } + #if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + odm_AntennaDiversity(pDM_Odm); /*enable AntDiv in PS mode, request from SD4 Jeff*/ + #endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("DMWatchdog in power saving mode\n")); + return; + } + + Phydm_CheckAdaptivity(pDM_Odm); + odm_UpdatePowerTrainingState(pDM_Odm); + odm_DIG(pDM_Odm); + { + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + Phydm_Adaptivity(pDM_Odm, pDM_DigTable->CurIGValue); + } + odm_CCKPacketDetectionThresh(pDM_Odm); + phydm_ra_dynamic_retry_limit(pDM_Odm); + phydm_ra_dynamic_retry_count(pDM_Odm); + odm_RefreshRateAdaptiveMask(pDM_Odm); + odm_RefreshBasicRateMask(pDM_Odm); + odm_DynamicBBPowerSaving(pDM_Odm); + odm_EdcaTurboCheck(pDM_Odm); + odm_PathDiversity(pDM_Odm); + ODM_CfoTracking(pDM_Odm); + odm_DynamicTxPower(pDM_Odm); + odm_AntennaDiversity(pDM_Odm); +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + phydm_Beamforming_Watchdog(pDM_Odm); +#endif + + phydm_rf_watchdog(pDM_Odm); + + if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + { + +#if (RTL8188E_SUPPORT == 1) + if(pDM_Odm->SupportICType==ODM_RTL8188E) + odm_DynamicPrimaryCCA(pDM_Odm); +#endif + +#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + + #if (RTL8192E_SUPPORT == 1) + if(pDM_Odm->SupportICType==ODM_RTL8192E) + odm_DynamicPrimaryCCA_Check(pDM_Odm); + #endif +#endif + } + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + odm_dtc(pDM_Odm); +#endif + + odm_CommonInfoSelfReset(pDM_Odm); + +} + + +// +// Init /.. Fixed HW value. Only init time. +// +VOID +ODM_CmnInfoInit( + IN PDM_ODM_T pDM_Odm, + IN ODM_CMNINFO_E CmnInfo, + IN u4Byte Value + ) +{ + // + // This section is used for init value + // + switch (CmnInfo) + { + // + // Fixed ODM value. + // + case ODM_CMNINFO_ABILITY: + pDM_Odm->SupportAbility = (u4Byte)Value; + break; + + case ODM_CMNINFO_RF_TYPE: + pDM_Odm->RFType = (u1Byte)Value; + break; + + case ODM_CMNINFO_PLATFORM: + pDM_Odm->SupportPlatform = (u1Byte)Value; + break; + + case ODM_CMNINFO_INTERFACE: + pDM_Odm->SupportInterface = (u1Byte)Value; + break; + + case ODM_CMNINFO_MP_TEST_CHIP: + pDM_Odm->bIsMPChip= (u1Byte)Value; + break; + + case ODM_CMNINFO_IC_TYPE: + pDM_Odm->SupportICType = Value; + break; + + case ODM_CMNINFO_CUT_VER: + pDM_Odm->CutVersion = (u1Byte)Value; + break; + + case ODM_CMNINFO_FAB_VER: + pDM_Odm->FabVersion = (u1Byte)Value; + break; + + case ODM_CMNINFO_RFE_TYPE: + pDM_Odm->RFEType = (u1Byte)Value; + break; + + case ODM_CMNINFO_RF_ANTENNA_TYPE: + pDM_Odm->AntDivType= (u1Byte)Value; + break; + + case ODM_CMNINFO_BOARD_TYPE: + pDM_Odm->BoardType = (u1Byte)Value; + break; + + case ODM_CMNINFO_PACKAGE_TYPE: + pDM_Odm->PackageType = (u1Byte)Value; + break; + + case ODM_CMNINFO_EXT_LNA: + pDM_Odm->ExtLNA = (u1Byte)Value; + break; + + case ODM_CMNINFO_5G_EXT_LNA: + pDM_Odm->ExtLNA5G = (u1Byte)Value; + break; + + case ODM_CMNINFO_EXT_PA: + pDM_Odm->ExtPA = (u1Byte)Value; + break; + + case ODM_CMNINFO_5G_EXT_PA: + pDM_Odm->ExtPA5G = (u1Byte)Value; + break; + + case ODM_CMNINFO_GPA: + pDM_Odm->TypeGPA = (u2Byte)Value; + break; + case ODM_CMNINFO_APA: + pDM_Odm->TypeAPA = (u2Byte)Value; + break; + case ODM_CMNINFO_GLNA: + pDM_Odm->TypeGLNA = (u2Byte)Value; + break; + case ODM_CMNINFO_ALNA: + pDM_Odm->TypeALNA = (u2Byte)Value; + break; + + case ODM_CMNINFO_EXT_TRSW: + pDM_Odm->ExtTRSW = (u1Byte)Value; + break; + case ODM_CMNINFO_EXT_LNA_GAIN: + pDM_Odm->ExtLNAGain = (u1Byte)Value; + break; + case ODM_CMNINFO_PATCH_ID: + pDM_Odm->PatchID = (u1Byte)Value; + break; + case ODM_CMNINFO_BINHCT_TEST: + pDM_Odm->bInHctTest = (BOOLEAN)Value; + break; + case ODM_CMNINFO_BWIFI_TEST: + pDM_Odm->bWIFITest = (BOOLEAN)Value; + break; + case ODM_CMNINFO_SMART_CONCURRENT: + pDM_Odm->bDualMacSmartConcurrent = (BOOLEAN )Value; + break; + case ODM_CMNINFO_DOMAIN_CODE_2G: + pDM_Odm->odm_Regulation2_4G = (u1Byte)Value; + break; + case ODM_CMNINFO_DOMAIN_CODE_5G: + pDM_Odm->odm_Regulation5G = (u1Byte)Value; + break; + case ODM_CMNINFO_CONFIG_BB_RF: + pDM_Odm->ConfigBBRF = (BOOLEAN)Value; + break; + case ODM_CMNINFO_IQKFWOFFLOAD: + pDM_Odm->IQKFWOffload = (u1Byte)Value; + break; + //To remove the compiler warning, must add an empty default statement to handle the other values. + default: + //do nothing + break; + + } + +} + + +VOID +ODM_CmnInfoHook( + IN PDM_ODM_T pDM_Odm, + IN ODM_CMNINFO_E CmnInfo, + IN PVOID pValue + ) +{ + // + // Hook call by reference pointer. + // + switch (CmnInfo) + { + // + // Dynamic call by reference pointer. + // + case ODM_CMNINFO_MAC_PHY_MODE: + pDM_Odm->pMacPhyMode = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_TX_UNI: + pDM_Odm->pNumTxBytesUnicast = (u8Byte *)pValue; + break; + + case ODM_CMNINFO_RX_UNI: + pDM_Odm->pNumRxBytesUnicast = (u8Byte *)pValue; + break; + + case ODM_CMNINFO_WM_MODE: + pDM_Odm->pWirelessMode = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_BAND: + pDM_Odm->pBandType = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_SEC_CHNL_OFFSET: + pDM_Odm->pSecChOffset = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_SEC_MODE: + pDM_Odm->pSecurity = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_BW: + pDM_Odm->pBandWidth = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_CHNL: + pDM_Odm->pChannel = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_DMSP_GET_VALUE: + pDM_Odm->pbGetValueFromOtherMac = (BOOLEAN *)pValue; + break; + + case ODM_CMNINFO_BUDDY_ADAPTOR: + pDM_Odm->pBuddyAdapter = (PADAPTER *)pValue; + break; + + case ODM_CMNINFO_DMSP_IS_MASTER: + pDM_Odm->pbMasterOfDMSP = (BOOLEAN *)pValue; + break; + + case ODM_CMNINFO_SCAN: + pDM_Odm->pbScanInProcess = (BOOLEAN *)pValue; + break; + + case ODM_CMNINFO_POWER_SAVING: + pDM_Odm->pbPowerSaving = (BOOLEAN *)pValue; + break; + + case ODM_CMNINFO_ONE_PATH_CCA: + pDM_Odm->pOnePathCCA = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_DRV_STOP: + pDM_Odm->pbDriverStopped = (BOOLEAN *)pValue; + break; + + case ODM_CMNINFO_PNP_IN: + pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep = (BOOLEAN *)pValue; + break; + + case ODM_CMNINFO_INIT_ON: + pDM_Odm->pinit_adpt_in_progress = (BOOLEAN *)pValue; + break; + + case ODM_CMNINFO_ANT_TEST: + pDM_Odm->pAntennaTest = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_NET_CLOSED: + pDM_Odm->pbNet_closed = (BOOLEAN *)pValue; + break; + + case ODM_CMNINFO_FORCED_RATE: + pDM_Odm->pForcedDataRate = (pu2Byte)pValue; + break; + + case ODM_CMNINFO_FORCED_IGI_LB: + pDM_Odm->pu1ForcedIgiLb = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_P2P_LINK: + pDM_Odm->DM_DigTable.bP2PInProcess = (u1Byte *)pValue; + break; + + case ODM_CMNINFO_IS1ANTENNA: + pDM_Odm->pIs1Antenna = (BOOLEAN *)pValue; + break; + + case ODM_CMNINFO_RFDEFAULTPATH: + pDM_Odm->pRFDefaultPath= (u1Byte *)pValue; + break; + + case ODM_CMNINFO_FCS_MODE: + pDM_Odm->pIsFcsModeEnable = (BOOLEAN *)pValue; + break; + /*add by YuChen for beamforming PhyDM*/ + case ODM_CMNINFO_HUBUSBMODE: + pDM_Odm->HubUsbMode = (u1Byte *)pValue; + break; + case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS: + pDM_Odm->pbFwDwRsvdPageInProgress = (BOOLEAN *)pValue; + break; + case ODM_CMNINFO_TX_TP: + pDM_Odm->pCurrentTxTP = (u4Byte *)pValue; + break; + case ODM_CMNINFO_RX_TP: + pDM_Odm->pCurrentRxTP = (u4Byte *)pValue; + break; + case ODM_CMNINFO_SOUNDING_SEQ: + pDM_Odm->pSoundingSeq = (u1Byte *)pValue; + break; + //case ODM_CMNINFO_RTSTA_AID: + // pDM_Odm->pAidMap = (u1Byte *)pValue; + // break; + + //case ODM_CMNINFO_BT_COEXIST: + // pDM_Odm->BTCoexist = (BOOLEAN *)pValue; + + //case ODM_CMNINFO_STA_STATUS: + //pDM_Odm->pODM_StaInfo[] = (PSTA_INFO_T)pValue; + //break; + + //case ODM_CMNINFO_PHY_STATUS: + // pDM_Odm->pPhyInfo = (ODM_PHY_INFO *)pValue; + // break; + + //case ODM_CMNINFO_MAC_STATUS: + // pDM_Odm->pMacInfo = (ODM_MAC_INFO *)pValue; + // break; + //To remove the compiler warning, must add an empty default statement to handle the other values. + default: + //do nothing + break; + + } + +} + + +VOID +ODM_CmnInfoPtrArrayHook( + IN PDM_ODM_T pDM_Odm, + IN ODM_CMNINFO_E CmnInfo, + IN u2Byte Index, + IN PVOID pValue + ) +{ + // + // Hook call by reference pointer. + // + switch (CmnInfo) + { + // + // Dynamic call by reference pointer. + // + case ODM_CMNINFO_STA_STATUS: + pDM_Odm->pODM_StaInfo[Index] = (PSTA_INFO_T)pValue; + + if (IS_STA_VALID(pDM_Odm->pODM_StaInfo[Index])) + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + pDM_Odm->platform2phydm_macid_table[((PSTA_INFO_T)pValue)->AssociatedMacId] = Index; /*AssociatedMacId are unique bttween different Adapter*/ + #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + pDM_Odm->platform2phydm_macid_table[((PSTA_INFO_T)pValue)->aid] = Index; + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + pDM_Odm->platform2phydm_macid_table[((PSTA_INFO_T)pValue)->mac_id] = Index; + #endif + + break; + //To remove the compiler warning, must add an empty default statement to handle the other values. + default: + //do nothing + break; + } + +} + + +// +// Update Band/CHannel/.. The values are dynamic but non-per-packet. +// +VOID +ODM_CmnInfoUpdate( + IN PDM_ODM_T pDM_Odm, + IN u4Byte CmnInfo, + IN u8Byte Value + ) +{ + // + // This init variable may be changed in run time. + // + switch (CmnInfo) + { + case ODM_CMNINFO_LINK_IN_PROGRESS: + pDM_Odm->bLinkInProcess = (BOOLEAN)Value; + break; + + case ODM_CMNINFO_ABILITY: + pDM_Odm->SupportAbility = (u4Byte)Value; + break; + + case ODM_CMNINFO_RF_TYPE: + pDM_Odm->RFType = (u1Byte)Value; + break; + + case ODM_CMNINFO_WIFI_DIRECT: + pDM_Odm->bWIFI_Direct = (BOOLEAN)Value; + break; + + case ODM_CMNINFO_WIFI_DISPLAY: + pDM_Odm->bWIFI_Display = (BOOLEAN)Value; + break; + + case ODM_CMNINFO_LINK: + pDM_Odm->bLinked = (BOOLEAN)Value; + break; + + case ODM_CMNINFO_STATION_STATE: + pDM_Odm->bsta_state = (BOOLEAN)Value; + break; + + case ODM_CMNINFO_RSSI_MIN: + pDM_Odm->RSSI_Min= (u1Byte)Value; + break; + + case ODM_CMNINFO_DBG_COMP: + pDM_Odm->DebugComponents = Value; + break; + + case ODM_CMNINFO_DBG_LEVEL: + pDM_Odm->DebugLevel = (u4Byte)Value; + break; + case ODM_CMNINFO_RA_THRESHOLD_HIGH: + pDM_Odm->RateAdaptive.HighRSSIThresh = (u1Byte)Value; + break; + + case ODM_CMNINFO_RA_THRESHOLD_LOW: + pDM_Odm->RateAdaptive.LowRSSIThresh = (u1Byte)Value; + break; +#if defined(BT_30_SUPPORT) && (BT_30_SUPPORT == 1) + // The following is for BT HS mode and BT coexist mechanism. + case ODM_CMNINFO_BT_ENABLED: + pDM_Odm->bBtEnabled = (BOOLEAN)Value; + break; + + case ODM_CMNINFO_BT_HS_CONNECT_PROCESS: + pDM_Odm->bBtConnectProcess = (BOOLEAN)Value; + break; + + case ODM_CMNINFO_BT_HS_RSSI: + pDM_Odm->btHsRssi = (u1Byte)Value; + break; + + case ODM_CMNINFO_BT_OPERATION: + pDM_Odm->bBtHsOperation = (BOOLEAN)Value; + break; + + case ODM_CMNINFO_BT_LIMITED_DIG: + pDM_Odm->bBtLimitedDig = (BOOLEAN)Value; + break; + + case ODM_CMNINFO_BT_DIG: + pDM_Odm->btHsDigVal = (u1Byte)Value; + break; + + case ODM_CMNINFO_BT_BUSY: + pDM_Odm->bBtBusy = (BOOLEAN)Value; + break; + + case ODM_CMNINFO_BT_DISABLE_EDCA: + pDM_Odm->bBtDisableEdcaTurbo = (BOOLEAN)Value; + break; +#endif + +#if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23 +#ifdef UNIVERSAL_REPEATER + case ODM_CMNINFO_VXD_LINK: + pDM_Odm->VXD_bLinked= (BOOLEAN)Value; + break; +#endif +#endif + + case ODM_CMNINFO_AP_TOTAL_NUM: + pDM_Odm->APTotalNum = (u1Byte)Value; + break; + + case ODM_CMNINFO_POWER_TRAINING: + pDM_Odm->bDisablePowerTraining = (BOOLEAN)Value; + break; + +/* + case ODM_CMNINFO_OP_MODE: + pDM_Odm->OPMode = (u1Byte)Value; + break; + + case ODM_CMNINFO_WM_MODE: + pDM_Odm->WirelessMode = (u1Byte)Value; + break; + + case ODM_CMNINFO_BAND: + pDM_Odm->BandType = (u1Byte)Value; + break; + + case ODM_CMNINFO_SEC_CHNL_OFFSET: + pDM_Odm->SecChOffset = (u1Byte)Value; + break; + + case ODM_CMNINFO_SEC_MODE: + pDM_Odm->Security = (u1Byte)Value; + break; + + case ODM_CMNINFO_BW: + pDM_Odm->BandWidth = (u1Byte)Value; + break; + + case ODM_CMNINFO_CHNL: + pDM_Odm->Channel = (u1Byte)Value; + break; +*/ + default: + //do nothing + break; + } + + +} + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +ODM_InitAllWorkItems(IN PDM_ODM_T pDM_Odm ) +{ + + PADAPTER pAdapter = pDM_Odm->Adapter; +#if USE_WORKITEM + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + ODM_InitializeWorkItem( pDM_Odm, + &pDM_Odm->DM_SWAT_Table.phydm_SwAntennaSwitchWorkitem, + (RT_WORKITEM_CALL_BACK)ODM_SW_AntDiv_WorkitemCallback, + (PVOID)pAdapter, + "AntennaSwitchWorkitem"); + #endif + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + ODM_InitializeWorkItem(pDM_Odm, + &pDM_Odm->dm_sat_table.hl_smart_antenna_workitem, + (RT_WORKITEM_CALL_BACK)phydm_beam_switch_workitem_callback, + (PVOID)pAdapter, + "hl_smart_ant_workitem"); + + ODM_InitializeWorkItem(pDM_Odm, + &pDM_Odm->dm_sat_table.hl_smart_antenna_decision_workitem, + (RT_WORKITEM_CALL_BACK)phydm_beam_decision_workitem_callback, + (PVOID)pAdapter, + "hl_smart_ant_decision_workitem"); + #endif + + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->PathDivSwitchWorkitem), + (RT_WORKITEM_CALL_BACK)odm_PathDivChkAntSwitchWorkitemCallback, + (PVOID)pAdapter, + "SWAS_WorkItem"); + + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->CCKPathDiversityWorkitem), + (RT_WORKITEM_CALL_BACK)odm_CCKTXPathDiversityWorkItemCallback, + (PVOID)pAdapter, + "CCKTXPathDiversityWorkItem"); + + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->MPT_DIGWorkitem), + (RT_WORKITEM_CALL_BACK)odm_MPT_DIGWorkItemCallback, + (PVOID)pAdapter, + "MPT_DIGWorkitem"); + + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->RaRptWorkitem), + (RT_WORKITEM_CALL_BACK)ODM_UpdateInitRateWorkItemCallback, + (PVOID)pAdapter, + "RaRptWorkitem"); + +#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->FastAntTrainingWorkitem), + (RT_WORKITEM_CALL_BACK)odm_FastAntTrainingWorkItemCallback, + (PVOID)pAdapter, + "FastAntTrainingWorkitem"); +#endif + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->DM_RXHP_Table.PSDTimeWorkitem), + (RT_WORKITEM_CALL_BACK)odm_PSD_RXHPWorkitemCallback, + (PVOID)pAdapter, + "PSDRXHP_WorkItem"); + +#endif /*#if USE_WORKITEM*/ + +#if (BEAMFORMING_SUPPORT == 1) + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_EnterWorkItem), + (RT_WORKITEM_CALL_BACK)halComTxbf_EnterWorkItemCallback, + (PVOID)pAdapter, + "Txbf_EnterWorkItem"); + + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_LeaveWorkItem), + (RT_WORKITEM_CALL_BACK)halComTxbf_LeaveWorkItemCallback, + (PVOID)pAdapter, + "Txbf_LeaveWorkItem"); + + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_FwNdpaWorkItem), + (RT_WORKITEM_CALL_BACK)halComTxbf_FwNdpaWorkItemCallback, + (PVOID)pAdapter, + "Txbf_FwNdpaWorkItem"); + + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_ClkWorkItem), + (RT_WORKITEM_CALL_BACK)halComTxbf_ClkWorkItemCallback, + (PVOID)pAdapter, + "Txbf_ClkWorkItem"); + + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_RateWorkItem), + (RT_WORKITEM_CALL_BACK)halComTxbf_RateWorkItemCallback, + (PVOID)pAdapter, + "Txbf_RateWorkItem"); + + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_StatusWorkItem), + (RT_WORKITEM_CALL_BACK)halComTxbf_StatusWorkItemCallback, + (PVOID)pAdapter, + "Txbf_StatusWorkItem"); + + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_ResetTxPathWorkItem), + (RT_WORKITEM_CALL_BACK)halComTxbf_ResetTxPathWorkItemCallback, + (PVOID)pAdapter, + "Txbf_ResetTxPathWorkItem"); + + ODM_InitializeWorkItem( + pDM_Odm, + &(pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_GetTxRateWorkItem), + (RT_WORKITEM_CALL_BACK)halComTxbf_GetTxRateWorkItemCallback, + (PVOID)pAdapter, + "Txbf_GetTxRateWorkItem"); +#endif +} + +VOID +ODM_FreeAllWorkItems(IN PDM_ODM_T pDM_Odm ) +{ +#if USE_WORKITEM + +#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + ODM_FreeWorkItem(&(pDM_Odm->DM_SWAT_Table.phydm_SwAntennaSwitchWorkitem)); +#endif + +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + ODM_FreeWorkItem(&(pDM_Odm->dm_sat_table.hl_smart_antenna_workitem)); + ODM_FreeWorkItem(&(pDM_Odm->dm_sat_table.hl_smart_antenna_decision_workitem)); +#endif + + ODM_FreeWorkItem(&(pDM_Odm->PathDivSwitchWorkitem)); + ODM_FreeWorkItem(&(pDM_Odm->CCKPathDiversityWorkitem)); +#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + ODM_FreeWorkItem(&(pDM_Odm->FastAntTrainingWorkitem)); +#endif + ODM_FreeWorkItem(&(pDM_Odm->MPT_DIGWorkitem)); + ODM_FreeWorkItem(&(pDM_Odm->RaRptWorkitem)); + ODM_FreeWorkItem((&pDM_Odm->DM_RXHP_Table.PSDTimeWorkitem)); + /*ODM_FreeWorkItem((&pDM_Odm->sbdcnt_workitem));*/ +#endif + +#if (BEAMFORMING_SUPPORT == 1) + ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_EnterWorkItem)); + ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_LeaveWorkItem)); + ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_FwNdpaWorkItem)); + ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_ClkWorkItem)); + ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_RateWorkItem)); + ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_StatusWorkItem)); + ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_ResetTxPathWorkItem)); + ODM_FreeWorkItem((&pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_GetTxRateWorkItem)); +#endif + +} +#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ + +/* +VOID +odm_FindMinimumRSSI( + IN PDM_ODM_T pDM_Odm + ) +{ + u4Byte i; + u1Byte RSSI_Min = 0xFF; + + for(i=0; ipODM_StaInfo[i] != NULL) + if(IS_STA_VALID(pDM_Odm->pODM_StaInfo[i]) ) + { + if(pDM_Odm->pODM_StaInfo[i]->RSSI_Ave < RSSI_Min) + { + RSSI_Min = pDM_Odm->pODM_StaInfo[i]->RSSI_Ave; + } + } + } + + pDM_Odm->RSSI_Min = RSSI_Min; + +} + +VOID +odm_IsLinked( + IN PDM_ODM_T pDM_Odm + ) +{ + u4Byte i; + BOOLEAN Linked = FALSE; + + for(i=0; ipODM_StaInfo[i]) ) + { + Linked = TRUE; + break; + } + + } + + pDM_Odm->bLinked = Linked; +} +*/ + +VOID +ODM_InitAllTimers( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + ODM_AntDivTimers(pDM_Odm,INIT_ANTDIV_TIMMER); +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +#ifdef MP_TEST + if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) + ODM_InitializeTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer, + (RT_TIMER_CALL_BACK)odm_MPT_DIGCallback, NULL, "MPT_DIGTimer"); +#endif +#elif(DM_ODM_SUPPORT_TYPE == ODM_WIN) + ODM_InitializeTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer, + (RT_TIMER_CALL_BACK)odm_MPT_DIGCallback, NULL, "MPT_DIGTimer"); +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + ODM_InitializeTimer(pDM_Odm, &pDM_Odm->PSDTimer, + (RT_TIMER_CALL_BACK)dm_PSDMonitorCallback, NULL, "PSDTimer"); + ODM_InitializeTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer, + (RT_TIMER_CALL_BACK)odm_PathDivChkAntSwitchCallback, NULL, "PathDivTimer"); + ODM_InitializeTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer, + (RT_TIMER_CALL_BACK)odm_CCKTXPathDiversityCallback, NULL, "CCKPathDiversityTimer"); + ODM_InitializeTimer(pDM_Odm, &pDM_Odm->DM_RXHP_Table.PSDTimer, + (RT_TIMER_CALL_BACK)odm_PSD_RXHPCallback, NULL, "PSDRXHPTimer"); + ODM_InitializeTimer(pDM_Odm, &pDM_Odm->sbdcnt_timer, + (RT_TIMER_CALL_BACK)phydm_sbd_callback, NULL, "SbdTimer"); +#if (BEAMFORMING_SUPPORT == 1) + ODM_InitializeTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_FwNdpaTimer, + (RT_TIMER_CALL_BACK)halComTxbf_FwNdpaTimerCallback, NULL, "Txbf_FwNdpaTimer"); +#endif +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (BEAMFORMING_SUPPORT == 1) + ODM_InitializeTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.BeamformingTimer, + (RT_TIMER_CALL_BACK)Beamforming_SWTimerCallback, NULL, "BeamformingTimer"); +#endif +#endif +} + +VOID +ODM_CancelAllTimers( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + // + // 2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in + // win7 platform. + // + HAL_ADAPTER_STS_CHK(pDM_Odm) +#endif + +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + ODM_AntDivTimers(pDM_Odm,CANCEL_ANTDIV_TIMMER); +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +#ifdef MP_TEST + if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) + ODM_CancelTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer); +#endif +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + ODM_CancelTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer); +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + ODM_CancelTimer(pDM_Odm, &pDM_Odm->PSDTimer); + ODM_CancelTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer); + ODM_CancelTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer); + ODM_CancelTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer); + ODM_CancelTimer(pDM_Odm, &pDM_Odm->DM_RXHP_Table.PSDTimer); + ODM_CancelTimer(pDM_Odm, &pDM_Odm->sbdcnt_timer); +#if (BEAMFORMING_SUPPORT == 1) + ODM_CancelTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_FwNdpaTimer); +#endif +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (BEAMFORMING_SUPPORT == 1) + ODM_CancelTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.BeamformingTimer); +#endif +#endif + +} + + +VOID +ODM_ReleaseAllTimers( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + ODM_AntDivTimers(pDM_Odm,RELEASE_ANTDIV_TIMMER); +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + #ifdef MP_TEST + if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) + ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer); + #endif +#elif(DM_ODM_SUPPORT_TYPE == ODM_WIN) +ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer); +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->PSDTimer); + ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer); + ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer); + ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer); + ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->DM_RXHP_Table.PSDTimer); + ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->sbdcnt_timer); +#if (BEAMFORMING_SUPPORT == 1) + ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.TxbfInfo.Txbf_FwNdpaTimer); +#endif +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (BEAMFORMING_SUPPORT == 1) + ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->BeamformingInfo.BeamformingTimer); +#endif +#endif +} + + +//3============================================================ +//3 Tx Power Tracking +//3============================================================ + + + + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +VOID +ODM_InitAllThreads( + IN PDM_ODM_T pDM_Odm + ) +{ + #ifdef TPT_THREAD + kTPT_task_init(pDM_Odm->priv); + #endif +} + +VOID +ODM_StopAllThreads( + IN PDM_ODM_T pDM_Odm + ) +{ + #ifdef TPT_THREAD + kTPT_task_stop(pDM_Odm->priv); + #endif +} +#endif + + +#if( DM_ODM_SUPPORT_TYPE == ODM_WIN) +// +// 2011/07/26 MH Add an API for testing IQK fail case. +// +BOOLEAN +ODM_CheckPowerStatus( + IN PADAPTER Adapter) +{ + + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + RT_RF_POWER_STATE rtState; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + + // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. + if (pMgntInfo->init_adpt_in_progress == TRUE) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter\n")); + return TRUE; + } + + // + // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. + // + Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); + if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", + Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); + return FALSE; + } + return TRUE; +} +#elif( DM_ODM_SUPPORT_TYPE == ODM_AP) +BOOLEAN +ODM_CheckPowerStatus( + IN PADAPTER Adapter) +{ + /* + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + RT_RF_POWER_STATE rtState; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + + // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. + if (pMgntInfo->init_adpt_in_progress == TRUE) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); + return TRUE; + } + + // + // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. + // + Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); + if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", + Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); + return FALSE; + } + */ + return TRUE; +} +#endif + +// need to ODM CE Platform +//move to here for ANT detection mechanism using + +#if ((DM_ODM_SUPPORT_TYPE == ODM_WIN)||(DM_ODM_SUPPORT_TYPE == ODM_CE)) +u4Byte +GetPSDData( + IN PDM_ODM_T pDM_Odm, + unsigned int point, + u1Byte initial_gain_psd) +{ + //unsigned int val, rfval; + //int psd_report; + u4Byte psd_report; + + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + //Debug Message + //val = PHY_QueryBBReg(Adapter,0x908, bMaskDWord); + //DbgPrint("Reg908 = 0x%x\n",val); + //val = PHY_QueryBBReg(Adapter,0xDF4, bMaskDWord); + //rfval = PHY_QueryRFReg(Adapter, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask); + //DbgPrint("RegDF4 = 0x%x, RFReg00 = 0x%x\n",val, rfval); + //DbgPrint("PHYTXON = %x, OFDMCCA_PP = %x, CCKCCA_PP = %x, RFReg00 = %x\n", + //(val&BIT25)>>25, (val&BIT14)>>14, (val&BIT15)>>15, rfval); + + //Set DCO frequency index, offset=(40MHz/SamplePts)*point + ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point); + + //Start PSD calculation, Reg808[22]=0->1 + ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 1); + //Need to wait for HW PSD report + ODM_StallExecution(1000); + ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 0); + //Read PSD report, Reg8B4[15:0] + psd_report = ODM_GetBBReg(pDM_Odm,0x8B4, bMaskDWord) & 0x0000FFFF; + +#if 1//(DEV_BUS_TYPE == RT_PCI_INTERFACE) && ( (RT_PLATFORM == PLATFORM_LINUX) || (RT_PLATFORM == PLATFORM_MACOSX)) + psd_report = (u4Byte) (odm_ConvertTo_dB(psd_report))+(u4Byte)(initial_gain_psd-0x1c); +#else + psd_report = (int) (20*log10((double)psd_report))+(int)(initial_gain_psd-0x1c); +#endif + + return psd_report; + +} +#endif + +u4Byte +odm_ConvertTo_dB( + u4Byte Value) +{ + u1Byte i; + u1Byte j; + u4Byte dB; + + Value = Value & 0xFFFF; + + for (i = 0; i < 12; i++) + { + if (Value <= dB_Invert_Table[i][7]) + { + break; + } + } + + if (i >= 12) + { + return (96); // maximum 96 dB + } + + for (j = 0; j < 8; j++) + { + if (Value <= dB_Invert_Table[i][j]) + { + break; + } + } + + dB = (i << 3) + j + 1; + + return (dB); +} + +u4Byte +odm_ConvertTo_linear( + u4Byte Value) +{ + u1Byte i; + u1Byte j; + u4Byte linear; + + /* 1dB~96dB */ + + Value = Value & 0xFF; + + i = (u1Byte)((Value - 1) >> 3); + j = (u1Byte)(Value - 1) - (i << 3); + + linear = dB_Invert_Table[i][j]; + + return (linear); +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +ODM_UpdateInitRateWorkItemCallback( + IN PVOID pContext + ) +{ + PADAPTER Adapter = (PADAPTER)pContext; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + u1Byte p = 0; + + if(pDM_Odm->SupportICType == ODM_RTL8821) + { + ODM_TxPwrTrackSetPwr8821A(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0); + } + else if(pDM_Odm->SupportICType == ODM_RTL8812) + { + for (p = ODM_RF_PATH_A; p < MAX_PATH_NUM_8812A; p++) //DOn't know how to include &c + { + ODM_TxPwrTrackSetPwr8812A(pDM_Odm, MIX_MODE, p, 0); + } + } + else if(pDM_Odm->SupportICType == ODM_RTL8723B) + { + ODM_TxPwrTrackSetPwr_8723B(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0); + } + else if(pDM_Odm->SupportICType == ODM_RTL8192E) + { + for (p = ODM_RF_PATH_A; p < MAX_PATH_NUM_8192E; p++) //DOn't know how to include &c + { + ODM_TxPwrTrackSetPwr92E(pDM_Odm, MIX_MODE, p, 0); + } + } + else if(pDM_Odm->SupportICType == ODM_RTL8188E) + { + ODM_TxPwrTrackSetPwr88E(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0); + } +} +#endif + +// +// ODM multi-port consideration, added by Roger, 2013.10.01. +// +VOID +ODM_AsocEntry_Init( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER pLoopAdapter = GetDefaultAdapter(pDM_Odm->Adapter); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pLoopAdapter); + PDM_ODM_T pDM_OutSrc = &pHalData->DM_OutSrc; + u1Byte TotalAssocEntryNum = 0; + u1Byte index = 0; + + + ODM_CmnInfoPtrArrayHook(pDM_OutSrc, ODM_CMNINFO_STA_STATUS, 0, &pLoopAdapter->MgntInfo.DefaultPort[0]); + pLoopAdapter->MgntInfo.DefaultPort[0].MultiPortStationIdx = TotalAssocEntryNum; + + pLoopAdapter = GetNextExtAdapter(pLoopAdapter); + TotalAssocEntryNum +=1; + + while(pLoopAdapter) + { + for (index = 0; index MgntInfo.AsocEntry[index]); + pLoopAdapter->MgntInfo.AsocEntry[index].MultiPortStationIdx = TotalAssocEntryNum+index; + } + + TotalAssocEntryNum+= index; + if(IS_HARDWARE_TYPE_8188E((pDM_Odm->Adapter))) + pLoopAdapter->RASupport = TRUE; + pLoopAdapter = GetNextExtAdapter(pLoopAdapter); + } +#endif +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +/* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */ +void odm_dtc(PDM_ODM_T pDM_Odm) +{ +#ifdef CONFIG_DM_RESP_TXAGC + #define DTC_BASE 35 /* RSSI higher than this value, start to decade TX power */ + #define DTC_DWN_BASE (DTC_BASE-5) /* RSSI lower than this value, start to increase TX power */ + + /* RSSI vs TX power step mapping: decade TX power */ + static const u8 dtc_table_down[]={ + DTC_BASE, + (DTC_BASE+5), + (DTC_BASE+10), + (DTC_BASE+15), + (DTC_BASE+20), + (DTC_BASE+25) + }; + + /* RSSI vs TX power step mapping: increase TX power */ + static const u8 dtc_table_up[]={ + DTC_DWN_BASE, + (DTC_DWN_BASE-5), + (DTC_DWN_BASE-10), + (DTC_DWN_BASE-15), + (DTC_DWN_BASE-15), + (DTC_DWN_BASE-20), + (DTC_DWN_BASE-20), + (DTC_DWN_BASE-25), + (DTC_DWN_BASE-25), + (DTC_DWN_BASE-30), + (DTC_DWN_BASE-35) + }; + + u8 i; + u8 dtc_steps=0; + u8 sign; + u8 resp_txagc=0; + + #if 0 + /* As DIG is disabled, DTC is also disable */ + if(!(pDM_Odm->SupportAbility & ODM_XXXXXX)) + return; + #endif + + if (DTC_BASE < pDM_Odm->RSSI_Min) { + /* need to decade the CTS TX power */ + sign = 1; + for (i=0;i= pDM_Odm->RSSI_Min) || (dtc_steps >= 6)) + break; + else + dtc_steps++; + } + } +#if 0 + else if (DTC_DWN_BASE > pDM_Odm->RSSI_Min) + { + /* needs to increase the CTS TX power */ + sign = 0; + dtc_steps = 1; + for (i=0;iRSSI_Min) || (dtc_steps>=10)) + break; + else + dtc_steps++; + } + } +#endif + else + { + sign = 0; + dtc_steps = 0; + } + + resp_txagc = dtc_steps | (sign << 4); + resp_txagc = resp_txagc | (resp_txagc << 5); + ODM_Write1Byte(pDM_Odm, 0x06d9, resp_txagc); + + DBG_871X("%s RSSI_Min:%u, set RESP_TXAGC to %s %u\n", + __func__, pDM_Odm->RSSI_Min, sign?"minus":"plus", dtc_steps); +#endif /* CONFIG_RESP_TXAGC_ADJUST */ +} + +#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ + +VOID +odm_UpdatePowerTrainingState( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm , PHYDM_FALSEALMCNT); + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + u4Byte score = 0; + + if(!(pDM_Odm->SupportAbility & ODM_BB_PWR_TRAIN)) + return; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState()============>\n")); + pDM_Odm->bChangeState = FALSE; + + // Debug command + if(pDM_Odm->ForcePowerTrainingState) + { + if(pDM_Odm->ForcePowerTrainingState == 1 && !pDM_Odm->bDisablePowerTraining) + { + pDM_Odm->bChangeState = TRUE; + pDM_Odm->bDisablePowerTraining = TRUE; + } + else if(pDM_Odm->ForcePowerTrainingState == 2 && pDM_Odm->bDisablePowerTraining) + { + pDM_Odm->bChangeState = TRUE; + pDM_Odm->bDisablePowerTraining = FALSE; + } + + pDM_Odm->PT_score = 0; + pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM = 0; + pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK = 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): ForcePowerTrainingState = %d\n", + pDM_Odm->ForcePowerTrainingState)); + return; + } + + if(!pDM_Odm->bLinked) + return; + + // First connect + if((pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE)) + { + pDM_Odm->PT_score = 0; + pDM_Odm->bChangeState = TRUE; + pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM = 0; + pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK = 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): First Connect\n")); + return; + } + + // Compute score + if(pDM_Odm->NHM_cnt_0 >= 215) + score = 2; + else if(pDM_Odm->NHM_cnt_0 >= 190) + score = 1; // unknow state + else + { + u4Byte RX_Pkt_Cnt; + + RX_Pkt_Cnt = (u4Byte)(pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM) + (u4Byte)(pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK); + + if((FalseAlmCnt->Cnt_CCA_all > 31 && RX_Pkt_Cnt > 31) && (FalseAlmCnt->Cnt_CCA_all >= RX_Pkt_Cnt)) + { + if((RX_Pkt_Cnt + (RX_Pkt_Cnt >> 1)) <= FalseAlmCnt->Cnt_CCA_all) + score = 0; + else if((RX_Pkt_Cnt + (RX_Pkt_Cnt >> 2)) <= FalseAlmCnt->Cnt_CCA_all) + score = 1; + else + score = 2; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): RX_Pkt_Cnt = %d, Cnt_CCA_all = %d\n", + RX_Pkt_Cnt, FalseAlmCnt->Cnt_CCA_all)); + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): NumQryPhyStatusOFDM = %d, NumQryPhyStatusCCK = %d\n", + (u4Byte)(pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM), (u4Byte)(pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK))); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): NHM_cnt_0 = %d, score = %d\n", + pDM_Odm->NHM_cnt_0, score)); + + // smoothing + pDM_Odm->PT_score = (score << 4) + (pDM_Odm->PT_score>>1) + (pDM_Odm->PT_score>>2); + score = (pDM_Odm->PT_score + 32) >> 6; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): PT_score = %d, score after smoothing = %d\n", + pDM_Odm->PT_score, score)); + + // Mode decision + if(score == 2) + { + if(pDM_Odm->bDisablePowerTraining) + { + pDM_Odm->bChangeState = TRUE; + pDM_Odm->bDisablePowerTraining = FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): Change state\n")); + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): Enable Power Training\n")); + } + else if(score == 0) + { + if(!pDM_Odm->bDisablePowerTraining) + { + pDM_Odm->bChangeState = TRUE; + pDM_Odm->bDisablePowerTraining = TRUE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): Change state\n")); + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_RA_MASK, ODM_DBG_LOUD,("odm_UpdatePowerTrainingState(): Disable Power Training\n")); + } + + pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM = 0; + pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK = 0; +#endif +} + + + +/*===========================================================*/ +/* The following is for compile only*/ +/*===========================================================*/ +/*#define TARGET_CHNL_NUM_2G_5G 59*/ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +u1Byte GetRightChnlPlaceforIQK(u1Byte chnl) +{ + u1Byte channel_all[TARGET_CHNL_NUM_2G_5G] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, + 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 149, 151, 153, 155, 157, 159, 161, 163, 165}; + u1Byte place = chnl; + + + if (chnl > 14) { + for (place = 14; place < sizeof(channel_all); place++) { + if (channel_all[place] == chnl) + return place-13; + } + } + + return 0; +} + +VOID +FillH2CCmd92C( + IN PADAPTER Adapter, + IN u1Byte ElementID, + IN u4Byte CmdLen, + IN pu1Byte pCmdBuffer +) +{} +VOID +PHY_SetTxPowerLevel8192C( + IN PADAPTER Adapter, + IN u1Byte channel + ) +{ +} +#endif +/*===========================================================*/ + +VOID +phydm_NoisyDetection( + IN PDM_ODM_T pDM_Odm + ) +{ + u4Byte Total_FA_Cnt, Total_CCA_Cnt; + u4Byte Score = 0, i, Score_Smooth; + + Total_CCA_Cnt = pDM_Odm->FalseAlmCnt.Cnt_CCA_all; + Total_FA_Cnt = pDM_Odm->FalseAlmCnt.Cnt_all; + +/* + if( Total_FA_Cnt*16>=Total_CCA_Cnt*14 ) // 87.5 + + else if( Total_FA_Cnt*16>=Total_CCA_Cnt*12 ) // 75 + + else if( Total_FA_Cnt*16>=Total_CCA_Cnt*10 ) // 56.25 + + else if( Total_FA_Cnt*16>=Total_CCA_Cnt*8 ) // 50 + + else if( Total_FA_Cnt*16>=Total_CCA_Cnt*7 ) // 43.75 + + else if( Total_FA_Cnt*16>=Total_CCA_Cnt*6 ) // 37.5 + + else if( Total_FA_Cnt*16>=Total_CCA_Cnt*5 ) // 31.25% + + else if( Total_FA_Cnt*16>=Total_CCA_Cnt*4 ) // 25% + + else if( Total_FA_Cnt*16>=Total_CCA_Cnt*3 ) // 18.75% + + else if( Total_FA_Cnt*16>=Total_CCA_Cnt*2 ) // 12.5% + + else if( Total_FA_Cnt*16>=Total_CCA_Cnt*1 ) // 6.25% +*/ + for(i=0;i<=16;i++) + { + if( Total_FA_Cnt*16>=Total_CCA_Cnt*(16-i) ) + { + Score = 16-i; + break; + } + } + + // NoisyDecision_Smooth = NoisyDecision_Smooth>>1 + (Score<<3)>>1; + pDM_Odm->NoisyDecision_Smooth = (pDM_Odm->NoisyDecision_Smooth>>1) + (Score<<2); + + // Round the NoisyDecision_Smooth: +"3" comes from (2^3)/2-1 + Score_Smooth = (Total_CCA_Cnt>=300)?((pDM_Odm->NoisyDecision_Smooth+3)>>3):0; + + pDM_Odm->NoisyDecision = (Score_Smooth>=3)?1:0; +/* + switch(Score_Smooth) + { + case 0: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=0%%\n")); + break; + case 1: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=6.25%%\n")); + break; + case 2: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=12.5%%\n")); + break; + case 3: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=18.75%%\n")); + break; + case 4: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=25%%\n")); + break; + case 5: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=31.25%%\n")); + break; + case 6: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=37.5%%\n")); + break; + case 7: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=43.75%%\n")); + break; + case 8: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=50%%\n")); + break; + case 9: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=56.25%%\n")); + break; + case 10: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=62.5%%\n")); + break; + case 11: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=68.75%%\n")); + break; + case 12: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=75%%\n")); + break; + case 13: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=81.25%%\n")); + break; + case 14: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=87.5%%\n")); + break; + case 15: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=93.75%%\n")); + break; + case 16: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Total_FA_Cnt/Total_CCA_Cnt=100%%\n")); + break; + default: + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("[NoisyDetection] Unknown Value!! Need Check!!\n")); + } +*/ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD, + ("[NoisyDetection] Total_CCA_Cnt=%d, Total_FA_Cnt=%d, NoisyDecision_Smooth=%d, Score=%d, Score_Smooth=%d, pDM_Odm->NoisyDecision=%d\n", + Total_CCA_Cnt, Total_FA_Cnt, pDM_Odm->NoisyDecision_Smooth, Score, Score_Smooth, pDM_Odm->NoisyDecision)); + +} + + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm.h new file mode 100644 index 000000000..cf42ef2da --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm.h @@ -0,0 +1,1440 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __HALDMOUTSRC_H__ +#define __HALDMOUTSRC_H__ + +//============================================================ +// include files +//============================================================ +#include "phydm_pre_define.h" +#include "phydm_dig.h" +#include "phydm_edcaturbocheck.h" +#include "phydm_pathdiv.h" +#include "phydm_antdiv.h" +#include "phydm_antdect.h" +#include "phydm_dynamicbbpowersaving.h" +#include "phydm_rainfo.h" +#include "phydm_dynamictxpower.h" +#include "phydm_cfotracking.h" +#include "phydm_acs.h" +#include "phydm_adaptivity.h" + + +#if (RTL8814A_SUPPORT == 1) +#include "rtl8814a/phydm_iqk_8814a.h" +#endif + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#include "halphyrf_ap.h" +#include "phydm_powertracking_ap.h" +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) +#include "phydm_beamforming.h" +#include "phydm_noisemonitor.h" +#include "halphyrf_ce.h" +#include "phydm_powertracking_ce.h" +#endif + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) +#include "phydm_beamforming.h" +#include "phydm_rxhp.h" +#include "halphyrf_win.h" +#include "phydm_powertracking_win.h" +#endif + +//============================================================ +// Definition +//============================================================ +// +// 2011/09/22 MH Define all team supprt ability. +// + +// +// 2011/09/22 MH Define for all teams. Please Define the constan in your precomp header. +// +//#define DM_ODM_SUPPORT_AP 0 +//#define DM_ODM_SUPPORT_ADSL 0 +//#define DM_ODM_SUPPORT_CE 0 +//#define DM_ODM_SUPPORT_MP 1 + +// +// 2011/09/28 MH Define ODM SW team support flag. +// + +//For SW AntDiv, PathDiv, 8192C AntDiv joint use +#define TP_MODE 0 +#define RSSI_MODE 1 + +#define TRAFFIC_LOW 0 +#define TRAFFIC_HIGH 1 +#define TRAFFIC_ULTRA_LOW 2 +#define TRAFFIC_MID 3 + + +#define NONE 0 + + + + +//8723A High Power IGI Setting +#define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 +#define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 +#define DM_DIG_HIGH_PWR_THRESHOLD 0x3a +#define DM_DIG_LOW_PWR_THRESHOLD 0x14 + + +//============================================================ +// structure and define +//============================================================ + +// +// 2011/09/20 MH Add for AP/ADSLpseudo DM structuer requirement. +// We need to remove to other position??? +// +#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) +typedef struct rtl8192cd_priv { + u1Byte temp; + +}rtl8192cd_priv, *prtl8192cd_priv; +#endif + + +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) +typedef struct _ADAPTER{ + u1Byte temp; + #ifdef AP_BUILD_WORKAROUND + HAL_DATA_TYPE* temp2; + prtl8192cd_priv priv; + #endif +}ADAPTER, *PADAPTER; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + +typedef struct _WLAN_STA{ + u1Byte temp; +} WLAN_STA, *PRT_WLAN_STA; + +#endif + +typedef struct _Dynamic_Primary_CCA{ + u1Byte PriCCA_flag; + u1Byte intf_flag; + u1Byte intf_type; + u1Byte DupRTS_flag; + u1Byte Monitor_flag; + u1Byte CH_offset; + u1Byte MF_state; +}Pri_CCA_T, *pPri_CCA_T; + + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + + +#ifdef ADSL_AP_BUILD_WORKAROUND +#define MAX_TOLERANCE 5 +#define IQK_DELAY_TIME 1 //ms +#endif +#if 0//defined in 8192cd.h +// +// Indicate different AP vendor for IOT issue. +// +typedef enum _HT_IOT_PEER +{ + HT_IOT_PEER_UNKNOWN = 0, + HT_IOT_PEER_REALTEK = 1, + HT_IOT_PEER_REALTEK_92SE = 2, + HT_IOT_PEER_BROADCOM = 3, + HT_IOT_PEER_RALINK = 4, + HT_IOT_PEER_ATHEROS = 5, + HT_IOT_PEER_CISCO = 6, + HT_IOT_PEER_MERU = 7, + HT_IOT_PEER_MARVELL = 8, + HT_IOT_PEER_REALTEK_SOFTAP = 9,// peer is RealTek SOFT_AP, by Bohn, 2009.12.17 + HT_IOT_PEER_SELF_SOFTAP = 10, // Self is SoftAP + HT_IOT_PEER_AIRGO = 11, + HT_IOT_PEER_INTEL = 12, + HT_IOT_PEER_RTK_APCLIENT = 13, + HT_IOT_PEER_REALTEK_81XX = 14, + HT_IOT_PEER_REALTEK_WOW = 15, + HT_IOT_PEER_MAX = 16 +}HT_IOT_PEER_E, *PHTIOT_PEER_E; +#endif +#endif//#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#define DM_Type_ByFW 0 +#define DM_Type_ByDriver 1 + +// +// Declare for common info +// + +#define IQK_THRESHOLD 8 +#define DPK_THRESHOLD 4 + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +__PACK typedef struct _ODM_Phy_Status_Info_ +{ + u1Byte RxPWDBAll; + u1Byte SignalQuality; /* in 0-100 index. */ + u1Byte RxMIMOSignalStrength[4]; /* in 0~100 index */ + s1Byte RxMIMOSignalQuality[4]; /* EVM */ + s1Byte RxSNR[4]; /* per-path's SNR */ +#if (RTL8822B_SUPPORT == 1) + u1Byte RxCount; /* RX path counter---*/ +#endif + u1Byte BandWidth; + +} __WLAN_ATTRIB_PACK__ ODM_PHY_INFO_T, *PODM_PHY_INFO_T; + +typedef struct _ODM_Phy_Status_Info_Append_ +{ + u1Byte MAC_CRC32; + +}ODM_PHY_INFO_Append_T,*PODM_PHY_INFO_Append_T; + +#else + +typedef struct _ODM_Phy_Status_Info_ +{ + // + // Be care, if you want to add any element please insert between + // RxPWDBAll & SignalStrength. + // +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + u4Byte RxPWDBAll; +#else + u1Byte RxPWDBAll; +#endif + u1Byte SignalQuality; /* in 0-100 index. */ + s1Byte RxMIMOSignalQuality[4]; /* per-path's EVM */ + u1Byte RxMIMOEVMdbm[4]; /* per-path's EVM dbm */ + u1Byte RxMIMOSignalStrength[4]; /* in 0~100 index */ + s2Byte Cfo_short[4]; /* per-path's Cfo_short */ + s2Byte Cfo_tail[4]; /* per-path's Cfo_tail */ + s1Byte RxPower; /* in dBm Translate from PWdB */ + s1Byte RecvSignalPower; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */ + u1Byte BTRxRSSIPercentage; + u1Byte SignalStrength; /* in 0-100 index. */ + s1Byte RxPwr[4]; /* per-path's pwdb */ + s1Byte RxSNR[4]; /* per-path's SNR */ +#if (RTL8822B_SUPPORT == 1) + u1Byte RxCount:2; /* RX path counter---*/ + u1Byte BandWidth:2; + u1Byte rxsc:4; /* sub-channel---*/ +#else + u1Byte BandWidth; +#endif + u1Byte btCoexPwrAdjust; +#if (RTL8822B_SUPPORT == 1) + u1Byte channel; /* channel number---*/ + BOOLEAN bMuPacket; /* is MU packet or not---*/ + BOOLEAN bBeamformed; /* BF packet---*/ +#endif +}ODM_PHY_INFO_T,*PODM_PHY_INFO_T; +#endif + +typedef struct _ODM_Per_Pkt_Info_ +{ + //u1Byte Rate; + u1Byte DataRate; + u1Byte StationID; + BOOLEAN bPacketMatchBSSID; + BOOLEAN bPacketToSelf; + BOOLEAN bPacketBeacon; + BOOLEAN bToSelf; +}ODM_PACKET_INFO_T,*PODM_PACKET_INFO_T; + + +typedef struct _ODM_Phy_Dbg_Info_ +{ + //ODM Write,debug info + s1Byte RxSNRdB[4]; + u4Byte NumQryPhyStatus; + u4Byte NumQryPhyStatusCCK; + u4Byte NumQryPhyStatusOFDM; +#if (RTL8822B_SUPPORT == 1) + u4Byte NumQryMuPkt; + u4Byte NumQryBfPkt; +#endif + u1Byte NumQryBeaconPkt; + //Others + s4Byte RxEVM[4]; + +}ODM_PHY_DBG_INFO_T; + + +typedef struct _ODM_Mac_Status_Info_ +{ + u1Byte test; + +}ODM_MAC_INFO; + +// +// 2011/20/20 MH For MP driver RT_WLAN_STA = STA_INFO_T +// Please declare below ODM relative info in your STA info structure. +// +#if 1 +typedef struct _ODM_STA_INFO{ + // Driver Write + BOOLEAN bUsed; // record the sta status link or not? + //u1Byte WirelessMode; // + u1Byte IOTPeer; // Enum value. HT_IOT_PEER_E + + // ODM Write + //1 PHY_STATUS_INFO + u1Byte RSSI_Path[4]; // + u1Byte RSSI_Ave; + u1Byte RXEVM[4]; + u1Byte RXSNR[4]; + + // ODM Write + //1 TX_INFO (may changed by IC) + //TX_INFO_T pTxInfo; // Define in IC folder. Move lower layer. +#if 0 + u1Byte ANTSEL_A; //in Jagar: 4bit; others: 2bit + u1Byte ANTSEL_B; //in Jagar: 4bit; others: 2bit + u1Byte ANTSEL_C; //only in Jagar: 4bit + u1Byte ANTSEL_D; //only in Jagar: 4bit + u1Byte TX_ANTL; //not in Jagar: 2bit + u1Byte TX_ANT_HT; //not in Jagar: 2bit + u1Byte TX_ANT_CCK; //not in Jagar: 2bit + u1Byte TXAGC_A; //not in Jagar: 4bit + u1Byte TXAGC_B; //not in Jagar: 4bit + u1Byte TXPWR_OFFSET; //only in Jagar: 3bit + u1Byte TX_ANT; //only in Jagar: 4bit for TX_ANTL/TX_ANTHT/TX_ANT_CCK +#endif + + // + // Please use compile flag to disabe the strcutrue for other IC except 88E. + // Move To lower layer. + // + // ODM Write Wilson will handle this part(said by Luke.Lee) + //TX_RPT_T pTxRpt; // Define in IC folder. Move lower layer. +#if 0 + //1 For 88E RA (don't redefine the naming) + u1Byte rate_id; + u1Byte rate_SGI; + u1Byte rssi_sta_ra; + u1Byte SGI_enable; + u1Byte Decision_rate; + u1Byte Pre_rate; + u1Byte Active; + + // Driver write Wilson handle. + //1 TX_RPT (don't redefine the naming) + u2Byte RTY[4]; // ??? + u2Byte TOTAL; // ??? + u2Byte DROP; // ??? + // + // Please use compile flag to disabe the strcutrue for other IC except 88E. + // +#endif + +}ODM_STA_INFO_T, *PODM_STA_INFO_T; +#endif + +// +// 2011/10/20 MH Define Common info enum for all team. +// +typedef enum _ODM_Common_Info_Definition +{ +//-------------REMOVED CASE-----------// + //ODM_CMNINFO_CCK_HP, + //ODM_CMNINFO_RFPATH_ENABLE, // Define as ODM write??? + //ODM_CMNINFO_BT_COEXIST, // ODM_BT_COEXIST_E + //ODM_CMNINFO_OP_MODE, // ODM_OPERATION_MODE_E +//-------------REMOVED CASE-----------// + + // + // Fixed value: + // + + //-----------HOOK BEFORE REG INIT-----------// + ODM_CMNINFO_PLATFORM = 0, + ODM_CMNINFO_ABILITY, // ODM_ABILITY_E + ODM_CMNINFO_INTERFACE, // ODM_INTERFACE_E + ODM_CMNINFO_MP_TEST_CHIP, + ODM_CMNINFO_IC_TYPE, // ODM_IC_TYPE_E + ODM_CMNINFO_CUT_VER, // ODM_CUT_VERSION_E + ODM_CMNINFO_FAB_VER, // ODM_FAB_E + ODM_CMNINFO_RF_TYPE, // ODM_RF_PATH_E or ODM_RF_TYPE_E? + ODM_CMNINFO_RFE_TYPE, + ODM_CMNINFO_BOARD_TYPE, // ODM_BOARD_TYPE_E + ODM_CMNINFO_PACKAGE_TYPE, + ODM_CMNINFO_EXT_LNA, // TRUE + ODM_CMNINFO_5G_EXT_LNA, + ODM_CMNINFO_EXT_PA, + ODM_CMNINFO_5G_EXT_PA, + ODM_CMNINFO_GPA, + ODM_CMNINFO_APA, + ODM_CMNINFO_GLNA, + ODM_CMNINFO_ALNA, + ODM_CMNINFO_EXT_TRSW, + ODM_CMNINFO_EXT_LNA_GAIN, + ODM_CMNINFO_PATCH_ID, //CUSTOMER ID + ODM_CMNINFO_BINHCT_TEST, + ODM_CMNINFO_BWIFI_TEST, + ODM_CMNINFO_SMART_CONCURRENT, + ODM_CMNINFO_CONFIG_BB_RF, + ODM_CMNINFO_DOMAIN_CODE_2G, + ODM_CMNINFO_DOMAIN_CODE_5G, + ODM_CMNINFO_IQKFWOFFLOAD, + ODM_CMNINFO_HUBUSBMODE, + ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS, + ODM_CMNINFO_TX_TP, + ODM_CMNINFO_RX_TP, + ODM_CMNINFO_SOUNDING_SEQ, + //-----------HOOK BEFORE REG INIT-----------// + + + // + // Dynamic value: + // +//--------- POINTER REFERENCE-----------// + ODM_CMNINFO_MAC_PHY_MODE, // ODM_MAC_PHY_MODE_E + ODM_CMNINFO_TX_UNI, + ODM_CMNINFO_RX_UNI, + ODM_CMNINFO_WM_MODE, // ODM_WIRELESS_MODE_E + ODM_CMNINFO_BAND, // ODM_BAND_TYPE_E + ODM_CMNINFO_SEC_CHNL_OFFSET, // ODM_SEC_CHNL_OFFSET_E + ODM_CMNINFO_SEC_MODE, // ODM_SECURITY_E + ODM_CMNINFO_BW, // ODM_BW_E + ODM_CMNINFO_CHNL, + ODM_CMNINFO_FORCED_RATE, + + ODM_CMNINFO_DMSP_GET_VALUE, + ODM_CMNINFO_BUDDY_ADAPTOR, + ODM_CMNINFO_DMSP_IS_MASTER, + ODM_CMNINFO_SCAN, + ODM_CMNINFO_POWER_SAVING, + ODM_CMNINFO_ONE_PATH_CCA, // ODM_CCA_PATH_E + ODM_CMNINFO_DRV_STOP, + ODM_CMNINFO_PNP_IN, + ODM_CMNINFO_INIT_ON, + ODM_CMNINFO_ANT_TEST, + ODM_CMNINFO_NET_CLOSED, + //ODM_CMNINFO_RTSTA_AID, // For win driver only? + ODM_CMNINFO_FORCED_IGI_LB, + ODM_CMNINFO_P2P_LINK, + ODM_CMNINFO_FCS_MODE, + ODM_CMNINFO_IS1ANTENNA, + ODM_CMNINFO_RFDEFAULTPATH, +//--------- POINTER REFERENCE-----------// + +//------------CALL BY VALUE-------------// + ODM_CMNINFO_WIFI_DIRECT, + ODM_CMNINFO_WIFI_DISPLAY, + ODM_CMNINFO_LINK_IN_PROGRESS, + ODM_CMNINFO_LINK, + ODM_CMNINFO_STATION_STATE, + ODM_CMNINFO_RSSI_MIN, + ODM_CMNINFO_DBG_COMP, // u8Byte + ODM_CMNINFO_DBG_LEVEL, // u4Byte + ODM_CMNINFO_RA_THRESHOLD_HIGH, // u1Byte + ODM_CMNINFO_RA_THRESHOLD_LOW, // u1Byte + ODM_CMNINFO_RF_ANTENNA_TYPE, // u1Byte + ODM_CMNINFO_BT_ENABLED, + ODM_CMNINFO_BT_HS_CONNECT_PROCESS, + ODM_CMNINFO_BT_HS_RSSI, + ODM_CMNINFO_BT_OPERATION, + ODM_CMNINFO_BT_LIMITED_DIG, //Need to Limited Dig or not + ODM_CMNINFO_BT_DIG, + ODM_CMNINFO_BT_BUSY, //Check Bt is using or not//neil + ODM_CMNINFO_BT_DISABLE_EDCA, +#if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23 +#ifdef UNIVERSAL_REPEATER + ODM_CMNINFO_VXD_LINK, +#endif +#endif + ODM_CMNINFO_AP_TOTAL_NUM, + ODM_CMNINFO_POWER_TRAINING, +//------------CALL BY VALUE-------------// + + // + // Dynamic ptr array hook itms. + // + ODM_CMNINFO_STA_STATUS, + ODM_CMNINFO_PHY_STATUS, + ODM_CMNINFO_MAC_STATUS, + + ODM_CMNINFO_MAX, + + +}ODM_CMNINFO_E; + +// +// 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY +// +typedef enum _ODM_Support_Ability_Definition +{ + // + // BB ODM section BIT 0-19 + // + ODM_BB_DIG = BIT0, + ODM_BB_RA_MASK = BIT1, + ODM_BB_DYNAMIC_TXPWR = BIT2, + ODM_BB_FA_CNT = BIT3, + ODM_BB_RSSI_MONITOR = BIT4, + ODM_BB_CCK_PD = BIT5, + ODM_BB_ANT_DIV = BIT6, + ODM_BB_PWR_SAVE = BIT7, + ODM_BB_PWR_TRAIN = BIT8, + ODM_BB_RATE_ADAPTIVE = BIT9, + ODM_BB_PATH_DIV = BIT10, + ODM_BB_PSD = BIT11, + ODM_BB_RXHP = BIT12, + ODM_BB_ADAPTIVITY = BIT13, + ODM_BB_CFO_TRACKING = BIT14, + ODM_BB_NHM_CNT = BIT15, + ODM_BB_PRIMARY_CCA = BIT16, + ODM_BB_TXBF = BIT17, + + // + // MAC DM section BIT 20-23 + // + ODM_MAC_EDCA_TURBO = BIT20, + ODM_MAC_EARLY_MODE = BIT21, + + // + // RF ODM section BIT 24-31 + // + ODM_RF_TX_PWR_TRACK = BIT24, + ODM_RF_RX_GAIN_TRACK = BIT25, + ODM_RF_CALIBRATION = BIT26, + +}ODM_ABILITY_E; + +//Move some non-DM enum,define, struc. form phydm.h to phydm_types.h by Dino + +// ODM_CMNINFO_ONE_PATH_CCA +typedef enum tag_CCA_Path +{ + ODM_CCA_2R = 0, + ODM_CCA_1R_A = 1, + ODM_CCA_1R_B = 2, +}ODM_CCA_PATH_E; + +//move RAInfo to Phydm_RaInfo.h + +//Remove struct PATHDIV_PARA to odm_PathDiv.h + +//Remove struct to odm_PowerTracking.h by YuChen +// +// ODM Dynamic common info value definition +// +//Move AntDiv form phydm.h to Phydm_AntDiv.h by Dino + +//move PathDiv to Phydm_PathDiv.h + +typedef enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE{ + PHY_REG_PG_RELATIVE_VALUE = 0, + PHY_REG_PG_EXACT_VALUE = 1 +} PHY_REG_PG_TYPE; + +// +// 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. +// +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (RT_PLATFORM != PLATFORM_LINUX) +typedef +#endif + +struct DM_Out_Source_Dynamic_Mechanism_Structure +#else// for AP,ADSL,CE Team +typedef struct DM_Out_Source_Dynamic_Mechanism_Structure +#endif +{ + //RT_TIMER FastAntTrainingTimer; + // + // Add for different team use temporarily + // + PADAPTER Adapter; // For CE/NIC team + prtl8192cd_priv priv; // For AP/ADSL team + // WHen you use Adapter or priv pointer, you must make sure the pointer is ready. + BOOLEAN odm_ready; + +#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) + rtl8192cd_priv fake_priv; +#endif +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + // ADSL_AP_BUILD_WORKAROUND + ADAPTER fake_adapter; +#endif + + PHY_REG_PG_TYPE PhyRegPgValueType; + u1Byte PhyRegPgVersion; + + u8Byte DebugComponents; + u4Byte DebugLevel; + + u4Byte NumQryPhyStatusAll; //CCK + OFDM + u4Byte LastNumQryPhyStatusAll; + u4Byte RxPWDBAve; + BOOLEAN MPDIG_2G; //off MPDIG + u1Byte Times_2G; + +//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------// + BOOLEAN bCckHighPower; + u1Byte RFPathRxEnable; // ODM_CMNINFO_RFPATH_ENABLE + u1Byte ControlChannel; +//------ ODM HANDLE, DRIVER NEEDS NOT TO HOOK------// + +//--------REMOVED COMMON INFO----------// + //u1Byte PseudoMacPhyMode; + //BOOLEAN *BTCoexist; + //BOOLEAN PseudoBtCoexist; + //u1Byte OPMode; + //BOOLEAN bAPMode; + //BOOLEAN bClientMode; + //BOOLEAN bAdHocMode; + //BOOLEAN bSlaveOfDMSP; +//--------REMOVED COMMON INFO----------// + + +//1 COMMON INFORMATION + + // + // Init Value + // +//-----------HOOK BEFORE REG INIT-----------// + // ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 + u1Byte SupportPlatform; + // ODM Support Ability DIG/RATR/TX_PWR_TRACK/ KK = 1/2/3/K + u4Byte SupportAbility; + // ODM PCIE/USB/SDIO = 1/2/3 + u1Byte SupportInterface; + // ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... + u4Byte SupportICType; + // Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... + u1Byte CutVersion; + // Fab Version TSMC/UMC = 0/1 + u1Byte FabVersion; + // RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... + u1Byte RFType; + u1Byte RFEType; + // Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... + u1Byte BoardType; + u1Byte PackageType; + u2Byte TypeGLNA; + u2Byte TypeGPA; + u2Byte TypeALNA; + u2Byte TypeAPA; + // with external LNA NO/Yes = 0/1 + u1Byte ExtLNA; // 2G + u1Byte ExtLNA5G; //5G + // with external PA NO/Yes = 0/1 + u1Byte ExtPA; // 2G + u1Byte ExtPA5G; //5G + // with external TRSW NO/Yes = 0/1 + u1Byte ExtTRSW; + u1Byte ExtLNAGain; // 2G + u1Byte PatchID; //Customer ID + BOOLEAN bInHctTest; + BOOLEAN bWIFITest; + + BOOLEAN bDualMacSmartConcurrent; + u4Byte BK_SupportAbility; + u1Byte AntDivType; + BOOLEAN ConfigBBRF; + u1Byte odm_Regulation2_4G; + u1Byte odm_Regulation5G; + u1Byte IQKFWOffload; +//-----------HOOK BEFORE REG INIT-----------// + + // + // Dynamic Value + // +//--------- POINTER REFERENCE-----------// + + u1Byte u1Byte_temp; + BOOLEAN BOOLEAN_temp; + PADAPTER PADAPTER_temp; + + // MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 + u1Byte *pMacPhyMode; + //TX Unicast byte count + u8Byte *pNumTxBytesUnicast; + //RX Unicast byte count + u8Byte *pNumRxBytesUnicast; + // Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 + u1Byte *pWirelessMode; //ODM_WIRELESS_MODE_E + // Frequence band 2.4G/5G = 0/1 + u1Byte *pBandType; + // Secondary channel offset don't_care/below/above = 0/1/2 + u1Byte *pSecChOffset; + // Security mode Open/WEP/AES/TKIP = 0/1/2/3 + u1Byte *pSecurity; + // BW info 20M/40M/80M = 0/1/2 + u1Byte *pBandWidth; + // Central channel location Ch1/Ch2/.... + u1Byte *pChannel; //central channel number + BOOLEAN DPK_Done; + // Common info for 92D DMSP + + BOOLEAN *pbGetValueFromOtherMac; + PADAPTER *pBuddyAdapter; + BOOLEAN *pbMasterOfDMSP; //MAC0: master, MAC1: slave + // Common info for Status + BOOLEAN *pbScanInProcess; + BOOLEAN *pbPowerSaving; + // CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. + u1Byte *pOnePathCCA; + //pMgntInfo->AntennaTest + u1Byte *pAntennaTest; + BOOLEAN *pbNet_closed; + //u1Byte *pAidMap; + u1Byte *pu1ForcedIgiLb; + BOOLEAN *pIsFcsModeEnable; +/*--------- For 8723B IQK-----------*/ + BOOLEAN *pIs1Antenna; + u1Byte *pRFDefaultPath; + // 0:S1, 1:S0 + +//--------- POINTER REFERENCE-----------// + pu2Byte pForcedDataRate; + pu1Byte HubUsbMode; + BOOLEAN *pbFwDwRsvdPageInProgress; + u4Byte *pCurrentTxTP; + u4Byte *pCurrentRxTP; + u1Byte *pSoundingSeq; +//------------CALL BY VALUE-------------// + BOOLEAN bLinkInProcess; + BOOLEAN bWIFI_Direct; + BOOLEAN bWIFI_Display; + BOOLEAN bLinked; + BOOLEAN bsta_state; +#if(DM_ODM_SUPPORT_TYPE & ODM_AP) // for repeater mode add by YuChen 2014.06.23 +#ifdef UNIVERSAL_REPEATER + BOOLEAN VXD_bLinked; +#endif +#endif // for repeater mode add by YuChen 2014.06.23 + u1Byte RSSI_Min; + u1Byte InterfaceIndex; /*Add for 92D dual MAC: 0--Mac0 1--Mac1*/ + BOOLEAN bIsMPChip; + BOOLEAN bOneEntryOnly; + BOOLEAN mp_mode; + u4Byte OneEntry_MACID; + u1Byte pre_number_linked_client; + u1Byte number_linked_client; + u1Byte pre_number_active_client; + u1Byte number_active_client; + // Common info for BTDM + BOOLEAN bBtEnabled; // BT is enabled + BOOLEAN bBtConnectProcess; // BT HS is under connection progress. + u1Byte btHsRssi; // BT HS mode wifi rssi value. + BOOLEAN bBtHsOperation; // BT HS mode is under progress + u1Byte btHsDigVal; // use BT rssi to decide the DIG value + BOOLEAN bBtDisableEdcaTurbo; // Under some condition, don't enable the EDCA Turbo + BOOLEAN bBtBusy; // BT is busy. + BOOLEAN bBtLimitedDig; // BT is busy. + BOOLEAN bDisablePhyApi; +//------------CALL BY VALUE-------------// + u1Byte RSSI_A; + u1Byte RSSI_B; + u1Byte RSSI_C; + u1Byte RSSI_D; + u8Byte RSSI_TRSW; + u8Byte RSSI_TRSW_H; + u8Byte RSSI_TRSW_L; + u8Byte RSSI_TRSW_iso; + u1Byte TXAntStatus; + u1Byte RXAntStatus; + u1Byte cck_lna_idx; + u1Byte cck_vga_idx; + u1Byte ofdm_agc_idx[4]; + + u1Byte RxRate; + BOOLEAN bNoisyState; + u1Byte TxRate; + u1Byte LinkedInterval; + u1Byte preChannel; + u4Byte TxagcOffsetValueA; + BOOLEAN IsTxagcOffsetPositiveA; + u4Byte TxagcOffsetValueB; + BOOLEAN IsTxagcOffsetPositiveB; + u4Byte tx_tp; + u4Byte rx_tp; + u4Byte total_tp; + u8Byte curTxOkCnt; + u8Byte curRxOkCnt; + u8Byte lastTxOkCnt; + u8Byte lastRxOkCnt; + u4Byte BbSwingOffsetA; + BOOLEAN IsBbSwingOffsetPositiveA; + u4Byte BbSwingOffsetB; + BOOLEAN IsBbSwingOffsetPositiveB; + u1Byte antdiv_rssi; + u1Byte fat_comb_a; + u1Byte fat_comb_b; + u1Byte antdiv_intvl; + u1Byte AntType; + u1Byte pre_AntType; + u1Byte antdiv_period; + u1Byte antdiv_select; + u1Byte path_select; + u1Byte antdiv_evm_en; + u1Byte bdc_holdstate; + u1Byte NdpaPeriod; + BOOLEAN H2C_RARpt_connect; + BOOLEAN cck_agc_report_type; + + u1Byte dm_dig_max_TH; + u1Byte dm_dig_min_TH; + u1Byte print_agc; + u1Byte TrafficLoad; + u1Byte pre_TrafficLoad; + + + //For Adaptivtiy + u2Byte NHM_cnt_0; + u2Byte NHM_cnt_1; + s1Byte TH_L2H_default; + s1Byte TH_EDCCA_HL_diff_default; + s1Byte TH_L2H_ini; + s1Byte TH_EDCCA_HL_diff; + s1Byte TH_L2H_ini_mode2; + s1Byte TH_EDCCA_HL_diff_mode2; + BOOLEAN Carrier_Sense_enable; + u1Byte Adaptivity_IGI_upper; + BOOLEAN adaptivity_flag; + u1Byte DCbackoff; + BOOLEAN Adaptivity_enable; + u1Byte APTotalNum; + BOOLEAN EDCCA_enable; + ADAPTIVITY_STATISTICS Adaptivity; + //For Adaptivtiy + u1Byte LastUSBHub; + u1Byte TxBfDataRate; + + u1Byte c2h_cmd_start; + u1Byte fw_debug_trace[60]; + u1Byte pre_c2h_seq; + BOOLEAN fw_buff_is_enpty; + u4Byte data_frame_num; + + /*for noise detection*/ + BOOLEAN NoisyDecision; /*b_noisy*/ + BOOLEAN pre_b_noisy; + u4Byte NoisyDecision_Smooth; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + ODM_NOISE_MONITOR noise_level;//[ODM_MAX_CHANNEL_NUM]; +#endif + // + //2 Define STA info. + // _ODM_STA_INFO + // 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? + PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; + u2Byte platform2phydm_macid_table[ODM_ASSOCIATE_ENTRY_NUM]; /* platform_macid_table[platform_macid] = phydm_macid */ + +#if (RATE_ADAPTIVE_SUPPORT == 1) + u2Byte CurrminRptTime; + ODM_RA_INFO_T RAInfo[ODM_ASSOCIATE_ENTRY_NUM]; //Use MacID as array index. STA MacID=0, VWiFi Client MacID={1, ODM_ASSOCIATE_ENTRY_NUM-1} //YJ,add,120119 +#endif + // + // 2012/02/14 MH Add to share 88E ra with other SW team. + // We need to colelct all support abilit to a proper area. + // + BOOLEAN RaSupport88E; + + // Define ........... + + // Latest packet phy info (ODM write) + ODM_PHY_DBG_INFO_T PhyDbgInfo; + //PHY_INFO_88E PhyInfo; + + // Latest packet phy info (ODM write) + ODM_MAC_INFO *pMacInfo; + //MAC_INFO_88E MacInfo; + + // Different Team independt structure?? + + // + //TX_RTP_CMN TX_retrpo; + //TX_RTP_88E TX_retrpo; + //TX_RTP_8195 TX_retrpo; + + // + //ODM Structure + // +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + #if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + BDC_T DM_BdcTable; + #endif + + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + SAT_T dm_sat_table; + #endif + +#endif + FAT_T DM_FatTable; + DIG_T DM_DigTable; + + PS_T DM_PSTable; + Pri_CCA_T DM_PriCCA; +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + RXHP_T DM_RXHP_Table; +#endif + RA_T DM_RA_Table; + FALSE_ALARM_STATISTICS FalseAlmCnt; + FALSE_ALARM_STATISTICS FlaseAlmCntBuddyAdapter; + SWAT_T DM_SWAT_Table; + CFO_TRACKING DM_CfoTrack; + ACS DM_ACS; + + +#if (RTL8814A_SUPPORT == 1) + IQK_INFO IQK_info; +#endif /* (RTL8814A_SUPPORT==1) */ + + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + //Path Div Struct + PATHDIV_PARA pathIQK; +#endif +#if(defined(CONFIG_PATH_DIVERSITY)) + PATHDIV_T DM_PathDiv; +#endif + + EDCA_T DM_EDCA_Table; + u4Byte WMMEDCA_BE; + + // Copy from SD4 structure + // + // ================================================== + // + + //common + //u1Byte DM_Type; + //u1Byte PSD_Report_RXHP[80]; // Add By Gary + //u1Byte PSD_func_flag; // Add By Gary + //for DIG + //u1Byte bDMInitialGainEnable; + //u1Byte binitialized; // for dm_initial_gain_Multi_STA use. + + BOOLEAN *pbDriverStopped; + BOOLEAN *pbDriverIsGoingToPnpSetPowerSleep; + BOOLEAN *pinit_adpt_in_progress; + + //PSD + BOOLEAN bUserAssignLevel; + RT_TIMER PSDTimer; + u1Byte RSSI_BT; //come from BT + BOOLEAN bPSDinProcess; + BOOLEAN bPSDactive; + BOOLEAN bDMInitialGainEnable; + + //MPT DIG + RT_TIMER MPT_DIGTimer; + + //for rate adaptive, in fact, 88c/92c fw will handle this + u1Byte bUseRAMask; + + ODM_RATE_ADAPTIVE RateAdaptive; +//#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if(defined(CONFIG_ANT_DETECTION)) + ANT_DETECTED_INFO AntDetectedInfo; // Antenna detected information for RSSI tool +#endif + ODM_RF_CAL_T RFCalibrateInfo; + + + // + // Dynamic ATC switch + // + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + // + // Power Training + // + u1Byte ForcePowerTrainingState; + BOOLEAN bChangeState; + u4Byte PT_score; + u8Byte OFDM_RX_Cnt; + u8Byte CCK_RX_Cnt; +#endif + BOOLEAN bDisablePowerTraining; + + // + // ODM system resource. + // + + // ODM relative time. + RT_TIMER PathDivSwitchTimer; + //2011.09.27 add for Path Diversity + RT_TIMER CCKPathDiversityTimer; + RT_TIMER FastAntTrainingTimer; +#ifdef ODM_EVM_ENHANCE_ANTDIV + RT_TIMER EVM_FastAntTrainingTimer; +#endif + RT_TIMER sbdcnt_timer; + + // ODM relative workitem. +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if USE_WORKITEM + RT_WORK_ITEM PathDivSwitchWorkitem; + RT_WORK_ITEM CCKPathDiversityWorkitem; + RT_WORK_ITEM FastAntTrainingWorkitem; + RT_WORK_ITEM MPT_DIGWorkitem; + RT_WORK_ITEM RaRptWorkitem; + RT_WORK_ITEM sbdcnt_workitem; +#endif +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +#if (BEAMFORMING_SUPPORT == 1) + RT_BEAMFORMING_INFO BeamformingInfo; +#endif +#endif + +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + +#if (RT_PLATFORM != PLATFORM_LINUX) +} DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure +#else +}; +#endif + +#else// for AP,ADSL,CE Team +} DM_ODM_T, *PDM_ODM_T; // DM_Dynamic_Mechanism_Structure +#endif + + +typedef enum _PHYDM_STRUCTURE_TYPE{ + PHYDM_FALSEALMCNT, + PHYDM_CFOTRACK, + PHYDM_ADAPTIVITY, + PHYDM_ROMINFO, + +}PHYDM_STRUCTURE_TYPE; + + + + typedef enum _ODM_RF_CONTENT{ + odm_radioa_txt = 0x1000, + odm_radiob_txt = 0x1001, + odm_radioc_txt = 0x1002, + odm_radiod_txt = 0x1003 +} ODM_RF_CONTENT; + +typedef enum _ODM_BB_Config_Type{ + CONFIG_BB_PHY_REG, + CONFIG_BB_AGC_TAB, + CONFIG_BB_AGC_TAB_2G, + CONFIG_BB_AGC_TAB_5G, + CONFIG_BB_PHY_REG_PG, + CONFIG_BB_PHY_REG_MP, + CONFIG_BB_AGC_TAB_DIFF, +} ODM_BB_Config_Type, *PODM_BB_Config_Type; + +typedef enum _ODM_RF_Config_Type{ + CONFIG_RF_RADIO, + CONFIG_RF_TXPWR_LMT, +} ODM_RF_Config_Type, *PODM_RF_Config_Type; + +typedef enum _ODM_FW_Config_Type{ + CONFIG_FW_NIC, +} ODM_FW_Config_Type; + +// Status code +#if (DM_ODM_SUPPORT_TYPE != ODM_WIN) +typedef enum _RT_STATUS{ + RT_STATUS_SUCCESS, + RT_STATUS_FAILURE, + RT_STATUS_PENDING, + RT_STATUS_RESOURCE, + RT_STATUS_INVALID_CONTEXT, + RT_STATUS_INVALID_PARAMETER, + RT_STATUS_NOT_SUPPORT, + RT_STATUS_OS_API_FAILED, +}RT_STATUS,*PRT_STATUS; +#endif // end of RT_STATUS definition + +#ifdef REMOVE_PACK +#pragma pack() +#endif + +//#include "odm_function.h" + +//3=========================================================== +//3 DIG +//3=========================================================== + +//Remove DIG by Yuchen + +//3=========================================================== +//3 AGC RX High Power Mode +//3=========================================================== +#define LNA_Low_Gain_1 0x64 +#define LNA_Low_Gain_2 0x5A +#define LNA_Low_Gain_3 0x58 + +#define FA_RXHP_TH1 5000 +#define FA_RXHP_TH2 1500 +#define FA_RXHP_TH3 800 +#define FA_RXHP_TH4 600 +#define FA_RXHP_TH5 500 + +//3=========================================================== +//3 EDCA +//3=========================================================== + +//3=========================================================== +//3 Dynamic Tx Power +//3=========================================================== +//Dynamic Tx Power Control Threshold + +//Remove By YuChen + +//3=========================================================== +//3 Tx Power Tracking +//3=========================================================== + + + +//3=========================================================== +//3 Rate Adaptive +//3=========================================================== +//Remove to odm_RaInfo.h by RS_James + +//3=========================================================== +//3 BB Power Save +//3=========================================================== + +typedef enum tag_1R_CCA_Type_Definition +{ + CCA_1R =0, + CCA_2R = 1, + CCA_MAX = 2, +}DM_1R_CCA_E; + +typedef enum tag_RF_Type_Definition +{ + RF_Save =0, + RF_Normal = 1, + RF_MAX = 2, +}DM_RF_E; + + +// +// Extern Global Variables. +// +//PowerTracking move to odm_powerTrakcing.h by YuChen +// +// check Sta pointer valid or not +// +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) +#define IS_STA_VALID(pSta) (pSta && pSta->expire_to) +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#define IS_STA_VALID(pSta) (pSta && pSta->bUsed) +#else +#define IS_STA_VALID(pSta) (pSta) +#endif + +//Remove DIG by yuchen + +//Remove BB power saving by Yuchen + +//remove PT by yuchen + +//ODM_RAStateCheck() Remove by RS_James + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_AP|ODM_ADSL)) +//============================================================ +// function prototype +//============================================================ +//#define DM_ChangeDynamicInitGainThresh ODM_ChangeDynamicInitGainThresh +//void ODM_ChangeDynamicInitGainThresh(IN PADAPTER pAdapter, +// IN INT32 DM_Type, +// IN INT32 DM_Value); + +//Remove DIG by yuchen + + +BOOLEAN +ODM_CheckPowerStatus( + IN PADAPTER Adapter + ); + + +//Remove ODM_RateAdaptiveStateApInit() by RS_James + +//Remove Edca by YuChen + +#endif + + + +u4Byte odm_ConvertTo_dB(u4Byte Value); + +u4Byte odm_ConvertTo_linear(u4Byte Value); + +#if((DM_ODM_SUPPORT_TYPE==ODM_WIN)||(DM_ODM_SUPPORT_TYPE==ODM_CE)) + +u4Byte +GetPSDData( + PDM_ODM_T pDM_Odm, + unsigned int point, + u1Byte initial_gain_psd); + +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +VOID +ODM_DMWatchdog_LPS( + IN PDM_ODM_T pDM_Odm +); +#endif + + +s4Byte +ODM_PWdB_Conversion( + IN s4Byte X, + IN u4Byte TotalBit, + IN u4Byte DecimalBit + ); + +s4Byte +ODM_SignConversion( + IN s4Byte value, + IN u4Byte TotalBit + ); + +VOID +ODM_DMInit( + IN PDM_ODM_T pDM_Odm +); + +VOID +ODM_DMReset( + IN PDM_ODM_T pDM_Odm + ); + +VOID +phydm_support_ablity_debug( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len + ); + +VOID +ODM_DMWatchdog( + IN PDM_ODM_T pDM_Odm // For common use in the future + ); + +VOID +ODM_CmnInfoInit( + IN PDM_ODM_T pDM_Odm, + IN ODM_CMNINFO_E CmnInfo, + IN u4Byte Value + ); + +VOID +ODM_CmnInfoHook( + IN PDM_ODM_T pDM_Odm, + IN ODM_CMNINFO_E CmnInfo, + IN PVOID pValue + ); + +VOID +ODM_CmnInfoPtrArrayHook( + IN PDM_ODM_T pDM_Odm, + IN ODM_CMNINFO_E CmnInfo, + IN u2Byte Index, + IN PVOID pValue + ); + +VOID +ODM_CmnInfoUpdate( + IN PDM_ODM_T pDM_Odm, + IN u4Byte CmnInfo, + IN u8Byte Value + ); + +#if(DM_ODM_SUPPORT_TYPE==ODM_AP) +VOID +ODM_InitAllThreads( + IN PDM_ODM_T pDM_Odm + ); + +VOID +ODM_StopAllThreads( + IN PDM_ODM_T pDM_Odm + ); +#endif + +VOID +ODM_InitAllTimers( + IN PDM_ODM_T pDM_Odm + ); + +VOID +ODM_CancelAllTimers( + IN PDM_ODM_T pDM_Odm + ); + +VOID +ODM_ReleaseAllTimers( + IN PDM_ODM_T pDM_Odm + ); + + + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID ODM_InitAllWorkItems(IN PDM_ODM_T pDM_Odm ); +VOID ODM_FreeAllWorkItems(IN PDM_ODM_T pDM_Odm ); + + + +u8Byte +PlatformDivision64( + IN u8Byte x, + IN u8Byte y +); + +//==================================================== +//3 PathDiV End +//==================================================== + + +#define DM_ChangeDynamicInitGainThresh ODM_ChangeDynamicInitGainThresh +//void ODM_ChangeDynamicInitGainThresh(IN PADAPTER pAdapter, +// IN INT32 DM_Type, +// IN INT32 DM_Value); +// +// PathDiveristy Remove by RS_James + +typedef enum tag_DIG_Connect_Definition +{ + DIG_STA_DISCONNECT = 0, + DIG_STA_CONNECT = 1, + DIG_STA_BEFORE_CONNECT = 2, + DIG_MultiSTA_DISCONNECT = 3, + DIG_MultiSTA_CONNECT = 4, + DIG_CONNECT_MAX +}DM_DIG_CONNECT_E; + + +// +// 2012/01/12 MH Check afapter status. Temp fix BSOD. +// +#define HAL_ADAPTER_STS_CHK(pDM_Odm)\ + if (pDM_Odm->Adapter == NULL)\ + {\ + return;\ + }\ + + +// +// For new definition in MP temporarily fro power tracking, +// +/* +#define odm_TXPowerTrackingDirectCall(_Adapter) \ + IS_HARDWARE_TYPE_8192D(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_92D(_Adapter) : \ + IS_HARDWARE_TYPE_8192C(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_92C(_Adapter) : \ + IS_HARDWARE_TYPE_8723A(_Adapter) ? odm_TXPowerTrackingCallback_ThermalMeter_8723A(_Adapter) :\ + ODM_TXPowerTrackingCallback_ThermalMeter(_Adapter) +*/ + + +#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +VOID +ODM_AsocEntry_Init( + IN PDM_ODM_T pDM_Odm + ); + +//Remove ODM_DynamicARFBSelect() by RS_James + +PVOID +PhyDM_Get_Structure( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Structure_Type +); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) ||(DM_ODM_SUPPORT_TYPE == ODM_CE) +/*===========================================================*/ +/* The following is for compile only*/ +/*===========================================================*/ + +#define IS_HARDWARE_TYPE_8723A(_Adapter) FALSE +#define IS_HARDWARE_TYPE_8723AE(_Adapter) FALSE +#define IS_HARDWARE_TYPE_8192C(_Adapter) FALSE +#define IS_HARDWARE_TYPE_8192D(_Adapter) FALSE +#define RF_T_METER_92D 0x42 + + +#define SET_TX_DESC_ANTSEL_A_92C(__pTxDesc, __Value) SET_BITS_TO_LE_1BYTE(__pTxDesc+8+3, 0, 1, __Value) +#define SET_TX_DESC_TX_ANTL_92C(__pTxDesc, __Value) SET_BITS_TO_LE_1BYTE(__pTxDesc+8+3, 4, 2, __Value) +#define SET_TX_DESC_TX_ANT_HT_92C(__pTxDesc, __Value) SET_BITS_TO_LE_1BYTE(__pTxDesc+8+3, 6, 2, __Value) +#define SET_TX_DESC_TX_ANT_CCK_92C(__pTxDesc, __Value) SET_BITS_TO_LE_1BYTE(__pTxDesc+8+3, 2, 2, __Value) + +#define GET_RX_STATUS_DESC_RX_MCS(__pRxStatusDesc) LE_BITS_TO_1BYTE( __pRxStatusDesc+12, 0, 6) + +#define RX_HAL_IS_CCK_RATE_92C(pDesc)\ + (GET_RX_STATUS_DESC_RX_MCS(pDesc) == DESC_RATE1M ||\ + GET_RX_STATUS_DESC_RX_MCS(pDesc) == DESC_RATE2M ||\ + GET_RX_STATUS_DESC_RX_MCS(pDesc) == DESC_RATE5_5M ||\ + GET_RX_STATUS_DESC_RX_MCS(pDesc) == DESC_RATE11M) + +#define H2C_92C_PSD_RESULT 16 + +#define rConfig_ram64x16 0xb2c + +#define TARGET_CHNL_NUM_2G_5G 59 +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +VOID +FillH2CCmd92C( + IN PADAPTER Adapter, + IN u1Byte ElementID, + IN u4Byte CmdLen, + IN pu1Byte pCmdBuffer +); +VOID +PHY_SetTxPowerLevel8192C( + IN PADAPTER Adapter, + IN u1Byte channel + ); +u1Byte GetRightChnlPlaceforIQK(u1Byte chnl); + +#endif + +//=========================================================== +#endif //#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +void odm_dtc(PDM_ODM_T pDM_Odm); +#endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */ + + +VOID phydm_NoisyDetection(IN PDM_ODM_T pDM_Odm ); + + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_acs.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_acs.c new file mode 100644 index 000000000..e18047e75 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_acs.c @@ -0,0 +1,1306 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ +#include "mp_precomp.h" +#include "phydm_precomp.h" + + +u1Byte +ODM_GetAutoChannelSelectResult( + IN PVOID pDM_VOID, + IN u1Byte Band +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PACS pACS = &pDM_Odm->DM_ACS; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if(Band == ODM_BAND_2_4G) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[ACS] ODM_GetAutoChannelSelectResult(): CleanChannel_2G(%d)\n", pACS->CleanChannel_2G)); + return (u1Byte)pACS->CleanChannel_2G; + } + else + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[ACS] ODM_GetAutoChannelSelectResult(): CleanChannel_5G(%d)\n", pACS->CleanChannel_5G)); + return (u1Byte)pACS->CleanChannel_5G; + } +#else + return (u1Byte)pACS->CleanChannel_2G; +#endif + +} + +VOID +odm_AutoChannelSelectSetting( + IN PVOID pDM_VOID, + IN BOOLEAN IsEnable +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u2Byte period = 0x2710;// 40ms in default + u2Byte NHMType = 0x7; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectSetting()=========> \n")); + + if(IsEnable) + {//20 ms + period = 0x1388; + NHMType = 0x1; + } + + if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + { + //PHY parameters initialize for ac series + ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11AC+2, period); //0x990[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms + //ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8|BIT9|BIT10, NHMType); //0x994[9:8]=3 enable CCX + } + else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + { + //PHY parameters initialize for n series + ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N+2, period); //0x894[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms + //ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, NHMType); //0x890[9:8]=3 enable CCX + } +#endif +} + +VOID +odm_AutoChannelSelectInit( + IN PVOID pDM_VOID +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PACS pACS = &pDM_Odm->DM_ACS; + u1Byte i; + + if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT)) + return; + + if(pACS->bForceACSResult) + return; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectInit()=========> \n")); + + pACS->CleanChannel_2G = 1; + pACS->CleanChannel_5G = 36; + + for (i = 0; i < ODM_MAX_CHANNEL_2G; ++i) + { + pACS->Channel_Info_2G[0][i] = 0; + pACS->Channel_Info_2G[1][i] = 0; + } + + if(pDM_Odm->SupportICType & (ODM_IC_11AC_SERIES|ODM_RTL8192D)) + { + for (i = 0; i < ODM_MAX_CHANNEL_5G; ++i) + { + pACS->Channel_Info_5G[0][i] = 0; + pACS->Channel_Info_5G[1][i] = 0; + } + } +#endif +} + +VOID +odm_AutoChannelSelectReset( + IN PVOID pDM_VOID +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PACS pACS = &pDM_Odm->DM_ACS; + + if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT)) + return; + + if(pACS->bForceACSResult) + return; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectReset()=========> \n")); + + odm_AutoChannelSelectSetting(pDM_Odm,TRUE);// for 20ms measurement + Phydm_NHMCounterStatisticsReset(pDM_Odm); +#endif +} + +VOID +odm_AutoChannelSelect( + IN PVOID pDM_VOID, + IN u1Byte Channel +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PACS pACS = &pDM_Odm->DM_ACS; + u1Byte ChannelIDX = 0, SearchIDX = 0; + u2Byte MaxScore=0; + + if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT)) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Return: SupportAbility ODM_BB_NHM_CNT is disabled\n")); + return; + } + + if(pACS->bForceACSResult) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Force 2G clean channel = %d, 5G clean channel = %d\n", + pACS->CleanChannel_2G, pACS->CleanChannel_5G)); + return; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Channel = %d=========> \n", Channel)); + + Phydm_GetNHMCounterStatistics(pDM_Odm); + odm_AutoChannelSelectSetting(pDM_Odm,FALSE); + + if(Channel >=1 && Channel <=14) + { + ChannelIDX = Channel - 1; + pACS->Channel_Info_2G[1][ChannelIDX]++; + + if(pACS->Channel_Info_2G[1][ChannelIDX] >= 2) + pACS->Channel_Info_2G[0][ChannelIDX] = (pACS->Channel_Info_2G[0][ChannelIDX] >> 1) + + (pACS->Channel_Info_2G[0][ChannelIDX] >> 2) + (pDM_Odm->NHM_cnt_0>>2); + else + pACS->Channel_Info_2G[0][ChannelIDX] = pDM_Odm->NHM_cnt_0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): NHM_cnt_0 = %d \n", pDM_Odm->NHM_cnt_0)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Channel_Info[0][%d] = %d, Channel_Info[1][%d] = %d\n", ChannelIDX, pACS->Channel_Info_2G[0][ChannelIDX], ChannelIDX, pACS->Channel_Info_2G[1][ChannelIDX])); + + for(SearchIDX = 0; SearchIDX < ODM_MAX_CHANNEL_2G; SearchIDX++) + { + if(pACS->Channel_Info_2G[1][SearchIDX] != 0) + { + if(pACS->Channel_Info_2G[0][SearchIDX] >= MaxScore) + { + MaxScore = pACS->Channel_Info_2G[0][SearchIDX]; + pACS->CleanChannel_2G = SearchIDX+1; + } + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("(1)odm_AutoChannelSelect(): 2G: CleanChannel_2G = %d, MaxScore = %d \n", + pACS->CleanChannel_2G, MaxScore)); + + } + else if(Channel >= 36) + { + // Need to do + pACS->CleanChannel_5G = Channel; + } +#endif +} + +#if ( DM_ODM_SUPPORT_TYPE & ODM_AP ) + +VOID +phydm_AutoChannelSelectSettingAP( + IN PVOID pDM_VOID, + IN u4Byte setting, // 0: STORE_DEFAULT_NHM_SETTING; 1: RESTORE_DEFAULT_NHM_SETTING, 2: ACS_NHM_SETTING + IN u4Byte acs_step +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + prtl8192cd_priv priv = pDM_Odm->priv; + PACS pACS = &pDM_Odm->DM_ACS; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectSettingAP()=========> \n")); + + //3 Store Default Setting + if(setting == STORE_DEFAULT_NHM_SETTING) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("STORE_DEFAULT_NHM_SETTING\n")); + + if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) // store Reg0x990, Reg0x994, Reg0x998, Reg0x99C, Reg0x9a0 + { + pACS->Reg0x990 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TIMER_11AC); // Reg0x990 + pACS->Reg0x994 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC); // Reg0x994 + pACS->Reg0x998 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC); // Reg0x998 + pACS->Reg0x99C = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC); // Reg0x99c + pACS->Reg0x9A0 = ODM_Read1Byte(pDM_Odm, ODM_REG_NHM_TH8_11AC); // Reg0x9a0, u1Byte + } + else if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + { + pACS->Reg0x890 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N); // Reg0x890 + pACS->Reg0x894 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N); // Reg0x894 + pACS->Reg0x898 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N); // Reg0x898 + pACS->Reg0x89C = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N); // Reg0x89c + pACS->Reg0xE28 = ODM_Read1Byte(pDM_Odm, ODM_REG_NHM_TH8_11N); // Reg0xe28, u1Byte + } + } + + //3 Restore Default Setting + else if(setting == RESTORE_DEFAULT_NHM_SETTING) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("RESTORE_DEFAULT_NHM_SETTING\n")); + + if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) // store Reg0x990, Reg0x994, Reg0x998, Reg0x99C, Reg0x9a0 + { + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TIMER_11AC, pACS->Reg0x990); + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, pACS->Reg0x994); + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, pACS->Reg0x998); + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, pACS->Reg0x99C); + ODM_Write1Byte(pDM_Odm, ODM_REG_NHM_TH8_11AC, pACS->Reg0x9A0); + } + else if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + { + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, pACS->Reg0x890); + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N, pACS->Reg0x894); + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, pACS->Reg0x898); + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, pACS->Reg0x89C); + ODM_Write1Byte(pDM_Odm, ODM_REG_NHM_TH8_11N, pACS->Reg0xE28); + } + } + + //3 ACS Setting + else if(setting == ACS_NHM_SETTING) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("ACS_NHM_SETTING\n")); + u2Byte period; + period = 0x61a8; + pACS->ACS_Step = acs_step; + + if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + { + //4 Set NHM period, 0x990[31:16]=0x61a8, Time duration for NHM unit: 4us, 0x61a8=100ms + ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11AC+2, period); + //4 Set NHM ignore_cca=1, ignore_txon=1, ccx_en=0 + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC,BIT8|BIT9|BIT10, 3); + + if(pACS->ACS_Step == 0) + { + //4 Set IGI + ODM_SetBBReg(pDM_Odm,0xc50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x3E); + if (get_rf_mimo_mode(priv) != MIMO_1T1R) + ODM_SetBBReg(pDM_Odm,0xe50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x3E); + + //4 Set ACS NHM threshold + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0x82786e64); + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffff8c); + ODM_Write1Byte(pDM_Odm, ODM_REG_NHM_TH8_11AC, 0xff); + ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC+2, 0xffff); + + } + else if(pACS->ACS_Step == 1) + { + //4 Set IGI + ODM_SetBBReg(pDM_Odm,0xc50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x2A); + if (get_rf_mimo_mode(priv) != MIMO_1T1R) + ODM_SetBBReg(pDM_Odm,0xe50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x2A); + + //4 Set ACS NHM threshold + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0x5a50463c); + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffff64); + + } + + } + else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + { + //4 Set NHM period, 0x894[31:16]=0x61a8, Time duration for NHM unit: 4us, 0x61a8=100ms + ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N+2, period); + //4 Set NHM ignore_cca=1, ignore_txon=1, ccx_en=0 + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N,BIT8|BIT9|BIT10, 3); + + if(pACS->ACS_Step == 0) + { + //4 Set IGI + ODM_SetBBReg(pDM_Odm,0xc50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x3E); + if (get_rf_mimo_mode(priv) != MIMO_1T1R) + ODM_SetBBReg(pDM_Odm,0xc58,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x3E); + + //4 Set ACS NHM threshold + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0x82786e64); + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffff8c); + ODM_Write1Byte(pDM_Odm, ODM_REG_NHM_TH8_11N, 0xff); + ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N+2, 0xffff); + + } + else if(pACS->ACS_Step == 1) + { + //4 Set IGI + ODM_SetBBReg(pDM_Odm,0xc50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x2A); + if (get_rf_mimo_mode(priv) != MIMO_1T1R) + ODM_SetBBReg(pDM_Odm,0xc58,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x2A); + + //4 Set ACS NHM threshold + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0x5a50463c); + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffff64); + + } + } + } + +} + +VOID +phydm_GetNHMStatisticsAP( + IN PVOID pDM_VOID, + IN u4Byte idx, // @ 2G, Real channel number = idx+1 + IN u4Byte acs_step +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + prtl8192cd_priv priv = pDM_Odm->priv; + PACS pACS = &pDM_Odm->DM_ACS; + u4Byte value32 = 0; + u1Byte i; + + pACS->ACS_Step = acs_step; + + if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + { + //4 Check if NHM result is ready + for (i=0; i<20; i++) { + + ODM_delay_ms(1); + if ( ODM_GetBBReg(pDM_Odm,rFPGA0_PSDReport,BIT17) ) + break; + } + + //4 Get NHM Statistics + if ( pACS->ACS_Step==1 ) { + + value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT7_TO_CNT4_11N); + + pACS->NHM_Cnt[idx][9] = (value32 & bMaskByte1) >> 8; + pACS->NHM_Cnt[idx][8] = (value32 & bMaskByte0); + + value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT_11N); // ODM_REG_NHM_CNT3_TO_CNT0_11N + + pACS->NHM_Cnt[idx][7] = (value32 & bMaskByte3) >> 24; + pACS->NHM_Cnt[idx][6] = (value32 & bMaskByte2) >> 16; + pACS->NHM_Cnt[idx][5] = (value32 & bMaskByte1) >> 8; + + } else if (pACS->ACS_Step==2) { + + value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT_11N); // ODM_REG_NHM_CNT3_TO_CNT0_11N + + pACS->NHM_Cnt[idx][4] = ODM_Read1Byte(pDM_Odm, ODM_REG_NHM_CNT7_TO_CNT4_11N); + pACS->NHM_Cnt[idx][3] = (value32 & bMaskByte3) >> 24; + pACS->NHM_Cnt[idx][2] = (value32 & bMaskByte2) >> 16; + pACS->NHM_Cnt[idx][1] = (value32 & bMaskByte1) >> 8; + pACS->NHM_Cnt[idx][0] = (value32 & bMaskByte0); + } + } + else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + { + //4 Check if NHM result is ready + for (i=0; i<20; i++) { + + ODM_delay_ms(1); + if (ODM_GetBBReg(pDM_Odm,ODM_REG_NHM_DUR_READY_11AC,BIT17)) + break; + } + + if ( pACS->ACS_Step==1 ) { + + value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT7_TO_CNT4_11AC); + + pACS->NHM_Cnt[idx][9] = (value32 & bMaskByte1) >> 8; + pACS->NHM_Cnt[idx][8] = (value32 & bMaskByte0); + + value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT_11AC); // ODM_REG_NHM_CNT3_TO_CNT0_11AC + + pACS->NHM_Cnt[idx][7] = (value32 & bMaskByte3) >> 24; + pACS->NHM_Cnt[idx][6] = (value32 & bMaskByte2) >> 16; + pACS->NHM_Cnt[idx][5] = (value32 & bMaskByte1) >> 8; + + } else if (pACS->ACS_Step==2) { + + value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT_11AC); // ODM_REG_NHM_CNT3_TO_CNT0_11AC + + pACS->NHM_Cnt[idx][4] = ODM_Read1Byte(pDM_Odm, ODM_REG_NHM_CNT7_TO_CNT4_11AC); + pACS->NHM_Cnt[idx][3] = (value32 & bMaskByte3) >> 24; + pACS->NHM_Cnt[idx][2] = (value32 & bMaskByte2) >> 16; + pACS->NHM_Cnt[idx][1] = (value32 & bMaskByte1) >> 8; + pACS->NHM_Cnt[idx][0] = (value32 & bMaskByte0); + } + } + +} + + +//#define ACS_DEBUG_INFO //acs debug default off +/* +int phydm_AutoChannelSelectAP( + IN PVOID pDM_VOID, + IN u4Byte ACS_Type, // 0: RXCount_Type, 1:NHM_Type + IN u4Byte available_chnl_num // amount of all channels + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PACS pACS = &pDM_Odm->DM_ACS; + prtl8192cd_priv priv = pDM_Odm->priv; + + static u4Byte score2G[MAX_2G_CHANNEL_NUM], score5G[MAX_5G_CHANNEL_NUM]; + u4Byte score[MAX_BSS_NUM], use_nhm = 0; + u4Byte minScore=0xffffffff; + u4Byte tmpScore, tmpIdx=0; + u4Byte traffic_check = 0; + u4Byte fa_count_weighting = 1; + int i, j, idx=0, idx_2G_end=-1, idx_5G_begin=-1, minChan=0; + struct bss_desc *pBss=NULL; + +#ifdef _DEBUG_RTL8192CD_ + char tmpbuf[400]; + int len=0; +#endif + + memset(score2G, '\0', sizeof(score2G)); + memset(score5G, '\0', sizeof(score5G)); + + for (i=0; iavailable_chnl_num; i++) { + if (priv->available_chnl[i] <= 14) + idx_2G_end = i; + else + break; + } + + for (i=0; iavailable_chnl_num; i++) { + if (priv->available_chnl[i] > 14) { + idx_5G_begin = i; + break; + } + } + +// DELETE +#ifndef CONFIG_RTL_NEW_AUTOCH + for (i=0; isite_survey->count; i++) { + pBss = &priv->site_survey->bss[i]; + for (idx=0; idxavailable_chnl_num; idx++) { + if (pBss->channel == priv->available_chnl[idx]) { + if (pBss->channel <= 14) + setChannelScore(idx, score2G, 0, MAX_2G_CHANNEL_NUM-1); + else + score5G[idx - idx_5G_begin] += 5; + break; + } + } + } +#endif + + if (idx_2G_end >= 0) + for (i=0; i<=idx_2G_end; i++) + score[i] = score2G[i]; + if (idx_5G_begin >= 0) + for (i=idx_5G_begin; iavailable_chnl_num; i++) + score[i] = score5G[i - idx_5G_begin]; + +#ifdef CONFIG_RTL_NEW_AUTOCH + { + u4Byte y, ch_begin=0, ch_end= priv->available_chnl_num; + + u4Byte do_ap_check = 1, ap_ratio = 0; + + if (idx_2G_end >= 0) + ch_end = idx_2G_end+1; + if (idx_5G_begin >= 0) + ch_begin = idx_5G_begin; + +#ifdef ACS_DEBUG_INFO//for debug + printk("\n"); + for (y=ch_begin; yavailable_chnl[y], + priv->chnl_ss_mac_rx_count[y], + priv->chnl_ss_mac_rx_count_40M[y], + priv->chnl_ss_fa_count[y], + score[y]); + printk("\n"); +#endif + +#if defined(CONFIG_RTL_88E_SUPPORT) || defined(CONFIG_WLAN_HAL_8192EE) + if( pDM_Odm->SupportICType&(ODM_RTL8188E|ODM_RTL8192E)&& priv->pmib->dot11RFEntry.acs_type ) + { + u4Byte tmp_score[MAX_BSS_NUM]; + memcpy(tmp_score, score, sizeof(score)); + if (find_clean_channel(priv, ch_begin, ch_end, tmp_score)) { + //memcpy(score, tmp_score, sizeof(score)); +#ifdef _DEBUG_RTL8192CD_ + printk("!! Found clean channel, select minimum FA channel\n"); +#endif + goto USE_CLN_CH; + } +#ifdef _DEBUG_RTL8192CD_ + printk("!! Not found clean channel, use NHM algorithm\n"); +#endif + use_nhm = 1; +USE_CLN_CH: + for (y=ch_begin; ynhm_cnt[y][i]; + for (j=0; jL, score: %d\n", + y+1, priv->nhm_cnt[y][9], priv->nhm_cnt[y][8], priv->nhm_cnt[y][7], + priv->nhm_cnt[y][6], priv->nhm_cnt[y][5], priv->nhm_cnt[y][4], + priv->nhm_cnt[y][3], priv->nhm_cnt[y][2], priv->nhm_cnt[y][1], + priv->nhm_cnt[y][0], score[y]); +#endif + } + + if (!use_nhm) + memcpy(score, tmp_score, sizeof(score)); + + goto choose_ch; + } +#endif + + // For each channel, weighting behind channels with MAC RX counter + //For each channel, weighting the channel with FA counter + + for (y=ch_begin; ychnl_ss_mac_rx_count[y]; + if (priv->chnl_ss_mac_rx_count[y] > 30) + do_ap_check = 0; + if( priv->chnl_ss_mac_rx_count[y] > MAC_RX_COUNT_THRESHOLD ) + traffic_check = 1; + +#ifdef RTK_5G_SUPPORT + if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) +#endif + { + if ((int)(y-4) >= (int)ch_begin) + score[y-4] += 2 * priv->chnl_ss_mac_rx_count[y]; + if ((int)(y-3) >= (int)ch_begin) + score[y-3] += 8 * priv->chnl_ss_mac_rx_count[y]; + if ((int)(y-2) >= (int)ch_begin) + score[y-2] += 8 * priv->chnl_ss_mac_rx_count[y]; + if ((int)(y-1) >= (int)ch_begin) + score[y-1] += 10 * priv->chnl_ss_mac_rx_count[y]; + if ((int)(y+1) < (int)ch_end) + score[y+1] += 10 * priv->chnl_ss_mac_rx_count[y]; + if ((int)(y+2) < (int)ch_end) + score[y+2] += 8 * priv->chnl_ss_mac_rx_count[y]; + if ((int)(y+3) < (int)ch_end) + score[y+3] += 8 * priv->chnl_ss_mac_rx_count[y]; + if ((int)(y+4) < (int)ch_end) + score[y+4] += 2 * priv->chnl_ss_mac_rx_count[y]; + } + + //this is for CH_LOAD caculation + if( priv->chnl_ss_cca_count[y] > priv->chnl_ss_fa_count[y]) + priv->chnl_ss_cca_count[y]-= priv->chnl_ss_fa_count[y]; + else + priv->chnl_ss_cca_count[y] = 0; + } + +#ifdef ACS_DEBUG_INFO//for debug + printk("\n"); + for (y=ch_begin; yavailable_chnl[y], score[y]); + printk("\n"); +#endif + + for (y=ch_begin; ychnl_ss_mac_rx_count_40M[y]) { + score[y] += 5 * priv->chnl_ss_mac_rx_count_40M[y]; + if (priv->chnl_ss_mac_rx_count_40M[y] > 30) + do_ap_check = 0; + if( priv->chnl_ss_mac_rx_count_40M[y] > MAC_RX_COUNT_THRESHOLD ) + traffic_check = 1; + +#ifdef RTK_5G_SUPPORT + if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) +#endif + { + if ((int)(y-6) >= (int)ch_begin) + score[y-6] += 1 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y-5) >= (int)ch_begin) + score[y-5] += 4 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y-4) >= (int)ch_begin) + score[y-4] += 4 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y-3) >= (int)ch_begin) + score[y-3] += 5 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y-2) >= (int)ch_begin) + score[y-2] += (5 * priv->chnl_ss_mac_rx_count_40M[y])/2; + if ((int)(y-1) >= (int)ch_begin) + score[y-1] += 5 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y+1) < (int)ch_end) + score[y+1] += 5 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y+2) < (int)ch_end) + score[y+2] += (5 * priv->chnl_ss_mac_rx_count_40M[y])/2; + if ((int)(y+3) < (int)ch_end) + score[y+3] += 5 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y+4) < (int)ch_end) + score[y+4] += 4 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y+5) < (int)ch_end) + score[y+5] += 4 * priv->chnl_ss_mac_rx_count_40M[y]; + if ((int)(y+6) < (int)ch_end) + score[y+6] += 1 * priv->chnl_ss_mac_rx_count_40M[y]; + } + } + } + +#ifdef ACS_DEBUG_INFO//for debug + printk("\n"); + for (y=ch_begin; yavailable_chnl[y], score[y]); + printk("\n"); + printk("4. do_ap_check=%d traffic_check=%d\n", do_ap_check, traffic_check); + printk("\n"); +#endif + + if( traffic_check == 0) + fa_count_weighting = 5; + else + fa_count_weighting = 1; + + for (y=ch_begin; ychnl_ss_fa_count[y]; + } + +#ifdef ACS_DEBUG_INFO//for debug + printk("\n"); + for (y=ch_begin; yavailable_chnl[y], score[y]); + printk("\n"); +#endif + + if (do_ap_check) { + for (i=0; isite_survey->count; i++) { + pBss = &priv->site_survey->bss[i]; + for (y=ch_begin; ychannel == priv->available_chnl[y]) { + if (pBss->channel <= 14) { +#ifdef ACS_DEBUG_INFO//for debug + printk("\n"); + printk("chnl[%d] has ap rssi=%d bw[0x%02x]\n", + pBss->channel, pBss->rssi, pBss->t_stamp[1]); + printk("\n"); +#endif + if (pBss->rssi > 60) + ap_ratio = 4; + else if (pBss->rssi > 35) + ap_ratio = 2; + else + ap_ratio = 1; + + if ((pBss->t_stamp[1] & 0x6) == 0) { + score[y] += 50 * ap_ratio; + if ((int)(y-4) >= (int)ch_begin) + score[y-4] += 10 * ap_ratio; + if ((int)(y-3) >= (int)ch_begin) + score[y-3] += 20 * ap_ratio; + if ((int)(y-2) >= (int)ch_begin) + score[y-2] += 30 * ap_ratio; + if ((int)(y-1) >= (int)ch_begin) + score[y-1] += 40 * ap_ratio; + if ((int)(y+1) < (int)ch_end) + score[y+1] += 40 * ap_ratio; + if ((int)(y+2) < (int)ch_end) + score[y+2] += 30 * ap_ratio; + if ((int)(y+3) < (int)ch_end) + score[y+3] += 20 * ap_ratio; + if ((int)(y+4) < (int)ch_end) + score[y+4] += 10 * ap_ratio; + } + else if ((pBss->t_stamp[1] & 0x4) == 0) { + score[y] += 50 * ap_ratio; + if ((int)(y-3) >= (int)ch_begin) + score[y-3] += 20 * ap_ratio; + if ((int)(y-2) >= (int)ch_begin) + score[y-2] += 30 * ap_ratio; + if ((int)(y-1) >= (int)ch_begin) + score[y-1] += 40 * ap_ratio; + if ((int)(y+1) < (int)ch_end) + score[y+1] += 50 * ap_ratio; + if ((int)(y+2) < (int)ch_end) + score[y+2] += 50 * ap_ratio; + if ((int)(y+3) < (int)ch_end) + score[y+3] += 50 * ap_ratio; + if ((int)(y+4) < (int)ch_end) + score[y+4] += 50 * ap_ratio; + if ((int)(y+5) < (int)ch_end) + score[y+5] += 40 * ap_ratio; + if ((int)(y+6) < (int)ch_end) + score[y+6] += 30 * ap_ratio; + if ((int)(y+7) < (int)ch_end) + score[y+7] += 20 * ap_ratio; + } + else { + score[y] += 50 * ap_ratio; + if ((int)(y-7) >= (int)ch_begin) + score[y-7] += 20 * ap_ratio; + if ((int)(y-6) >= (int)ch_begin) + score[y-6] += 30 * ap_ratio; + if ((int)(y-5) >= (int)ch_begin) + score[y-5] += 40 * ap_ratio; + if ((int)(y-4) >= (int)ch_begin) + score[y-4] += 50 * ap_ratio; + if ((int)(y-3) >= (int)ch_begin) + score[y-3] += 50 * ap_ratio; + if ((int)(y-2) >= (int)ch_begin) + score[y-2] += 50 * ap_ratio; + if ((int)(y-1) >= (int)ch_begin) + score[y-1] += 50 * ap_ratio; + if ((int)(y+1) < (int)ch_end) + score[y+1] += 40 * ap_ratio; + if ((int)(y+2) < (int)ch_end) + score[y+2] += 30 * ap_ratio; + if ((int)(y+3) < (int)ch_end) + score[y+3] += 20 * ap_ratio; + } + } + else { + if ((pBss->t_stamp[1] & 0x6) == 0) { + score[y] += 500; + } + else if ((pBss->t_stamp[1] & 0x4) == 0) { + score[y] += 500; + if ((int)(y+1) < (int)ch_end) + score[y+1] += 500; + } + else { + score[y] += 500; + if ((int)(y-1) >= (int)ch_begin) + score[y-1] += 500; + } + } + break; + } + } + } + } + +#ifdef ACS_DEBUG_INFO//for debug + printk("\n"); + for (y=ch_begin; yavailable_chnl[y],score[y]); + printk("\n"); +#endif + +#ifdef SS_CH_LOAD_PROC + + // caculate noise level -- suggested by wilson + for (y=ch_begin; ychnl_ss_fa_count[y]>1000) { + fa_lv = 100; + } else if (priv->chnl_ss_fa_count[y]>500) { + fa_lv = 34 * (priv->chnl_ss_fa_count[y]-500) / 500 + 66; + } else if (priv->chnl_ss_fa_count[y]>200) { + fa_lv = 33 * (priv->chnl_ss_fa_count[y] - 200) / 300 + 33; + } else if (priv->chnl_ss_fa_count[y]>100) { + fa_lv = 18 * (priv->chnl_ss_fa_count[y] - 100) / 100 + 15; + } else { + fa_lv = 15 * priv->chnl_ss_fa_count[y] / 100; + } + if (priv->chnl_ss_cca_count[y]>400) { + cca_lv = 100; + } else if (priv->chnl_ss_cca_count[y]>200) { + cca_lv = 34 * (priv->chnl_ss_cca_count[y] - 200) / 200 + 66; + } else if (priv->chnl_ss_cca_count[y]>80) { + cca_lv = 33 * (priv->chnl_ss_cca_count[y] - 80) / 120 + 33; + } else if (priv->chnl_ss_cca_count[y]>40) { + cca_lv = 18 * (priv->chnl_ss_cca_count[y] - 40) / 40 + 15; + } else { + cca_lv = 15 * priv->chnl_ss_cca_count[y] / 40; + } + + priv->chnl_ss_load[y] = (((fa_lv > cca_lv)? fa_lv : cca_lv)*75+((score[y]>100)?100:score[y])*25)/100; + + DEBUG_INFO("ch:%d f=%d (%d), c=%d (%d), fl=%d, cl=%d, sc=%d, cu=%d\n", + priv->available_chnl[y], + priv->chnl_ss_fa_count[y], fa_thd, + priv->chnl_ss_cca_count[y], cca_thd, + fa_lv, + cca_lv, + score[y], + priv->chnl_ss_load[y]); + + } +#endif + } +#endif + +choose_ch: + +#ifdef DFS + // heavy weighted DFS channel + if (idx_5G_begin >= 0){ + for (i=idx_5G_begin; iavailable_chnl_num; i++) { + if (!priv->pmib->dot11DFSEntry.disable_DFS && is_DFS_channel(priv->available_chnl[i]) + && (score[i]!= 0xffffffff)){ + score[i] += 1600; + } + } + } +#endif + + +//prevent Auto Channel selecting wrong channel in 40M mode----------------- + if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) + && priv->pshare->is_40m_bw) { +#if 0 + if (GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset == 1) { + //Upper Primary Channel, cannot select the two lowest channels + if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11G) { + score[0] = 0xffffffff; + score[1] = 0xffffffff; + score[2] = 0xffffffff; + score[3] = 0xffffffff; + score[4] = 0xffffffff; + + score[13] = 0xffffffff; + score[12] = 0xffffffff; + score[11] = 0xffffffff; + } + +// if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) { +// score[idx_5G_begin] = 0xffffffff; +// score[idx_5G_begin + 1] = 0xffffffff; +// } + } + else if (GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset == 2) { + //Lower Primary Channel, cannot select the two highest channels + if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11G) { + score[0] = 0xffffffff; + score[1] = 0xffffffff; + score[2] = 0xffffffff; + + score[13] = 0xffffffff; + score[12] = 0xffffffff; + score[11] = 0xffffffff; + score[10] = 0xffffffff; + score[9] = 0xffffffff; + } + +// if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) { +// score[priv->available_chnl_num - 2] = 0xffffffff; +// score[priv->available_chnl_num - 1] = 0xffffffff; +// } + } +#endif + for (i=0; i<=idx_2G_end; ++i) + if (priv->available_chnl[i] == 14) + score[i] = 0xffffffff; // mask chan14 + +#ifdef RTK_5G_SUPPORT + if (idx_5G_begin >= 0) { + for (i=idx_5G_begin; iavailable_chnl_num; i++) { + int ch = priv->available_chnl[i]; + if(priv->available_chnl[i] > 144) + --ch; + if((ch%4) || ch==140 || ch == 164 ) //mask ch 140, ch 165, ch 184... + score[i] = 0xffffffff; + } + } +#endif + + + } + + if (priv->pmib->dot11RFEntry.disable_ch1213) { + for (i=0; i<=idx_2G_end; ++i) { + int ch = priv->available_chnl[i]; + if ((ch == 12) || (ch == 13)) + score[i] = 0xffffffff; + } + } + + if (((priv->pmib->dot11StationConfigEntry.dot11RegDomain == DOMAIN_GLOBAL) || + (priv->pmib->dot11StationConfigEntry.dot11RegDomain == DOMAIN_WORLD_WIDE)) && + (idx_2G_end >= 11) && (idx_2G_end < 14)) { + score[13] = 0xffffffff; // mask chan14 + score[12] = 0xffffffff; // mask chan13 + score[11] = 0xffffffff; // mask chan12 + } + +//------------------------------------------------------------------ + +#ifdef _DEBUG_RTL8192CD_ + for (i=0; iavailable_chnl_num; i++) { + len += sprintf(tmpbuf+len, "ch%d:%u ", priv->available_chnl[i], score[i]); + } + strcat(tmpbuf, "\n"); + panic_printk("%s", tmpbuf); + +#endif + + if ( (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) + && (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80)) + { + for (i=0; iavailable_chnl_num; i++) { + if (is80MChannel(priv->available_chnl, priv->available_chnl_num, priv->available_chnl[i])) { + tmpScore = 0; + for (j=0; j<4; j++) { + if ((tmpScore != 0xffffffff) && (score[i+j] != 0xffffffff)) + tmpScore += score[i+j]; + else + tmpScore = 0xffffffff; + } + tmpScore = tmpScore / 4; + if (minScore > tmpScore) { + minScore = tmpScore; + + tmpScore = 0xffffffff; + for (j=0; j<4; j++) { + if (score[i+j] < tmpScore) { + tmpScore = score[i+j]; + tmpIdx = i+j; + } + } + + idx = tmpIdx; + } + i += 3; + } + } + if (minScore == 0xffffffff) { + // there is no 80M channels + priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20; + for (i=0; iavailable_chnl_num; i++) { + if (score[i] < minScore) { + minScore = score[i]; + idx = i; + } + } + } + } + else if( (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) + && (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20_40)) + { + for (i=0; iavailable_chnl_num; i++) { + if(is40MChannel(priv->available_chnl,priv->available_chnl_num,priv->available_chnl[i])) { + tmpScore = 0; + for(j=0;j<2;j++) { + if ((tmpScore != 0xffffffff) && (score[i+j] != 0xffffffff)) + tmpScore += score[i+j]; + else + tmpScore = 0xffffffff; + } + tmpScore = tmpScore / 2; + if(minScore > tmpScore) { + minScore = tmpScore; + + tmpScore = 0xffffffff; + for (j=0; j<2; j++) { + if (score[i+j] < tmpScore) { + tmpScore = score[i+j]; + tmpIdx = i+j; + } + } + + idx = tmpIdx; + } + i += 1; + } + } + if (minScore == 0xffffffff) { + // there is no 40M channels + priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20; + for (i=0; iavailable_chnl_num; i++) { + if (score[i] < minScore) { + minScore = score[i]; + idx = i; + } + } + } + } + else if( (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G) + && (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20_40) + && (priv->available_chnl_num >= 8) ) + { + u4Byte groupScore[14]; + + memset(groupScore, 0xff , sizeof(groupScore)); + for (i=0; iavailable_chnl_num-4; i++) { + if (score[i] != 0xffffffff && score[i+4] != 0xffffffff) { + groupScore[i] = score[i] + score[i+4]; + DEBUG_INFO("groupScore, ch %d,%d: %d\n", i+1, i+5, groupScore[i]); + if (groupScore[i] < minScore) { +#ifdef AUTOCH_SS_SPEEDUP + if(priv->pmib->miscEntry.autoch_1611_enable) + { + if(priv->available_chnl[i]==1 || priv->available_chnl[i]==6 || priv->available_chnl[i]==11) + { + minScore = groupScore[i]; + idx = i; + } + } + else +#endif + { + minScore = groupScore[i]; + idx = i; + } + } + } + } + + if (score[idx] < score[idx+4]) { + GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE; + priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_ABOVE; + } else { + idx = idx + 4; + GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW; + priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_BELOW; + } + } + else + { + for (i=0; iavailable_chnl_num; i++) { + if (score[i] < minScore) { +#ifdef AUTOCH_SS_SPEEDUP + if(priv->pmib->miscEntry.autoch_1611_enable) + { + if(priv->available_chnl[i]==1 || priv->available_chnl[i]==6 || priv->available_chnl[i]==11) + { + minScore = score[i]; + idx = i; + } + } + else +#endif + { + minScore = score[i]; + idx = i; + } + } + } + } + + if (IS_A_CUT_8881A(priv) && + (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80)) { + if ((priv->available_chnl[idx] == 36) || + (priv->available_chnl[idx] == 52) || + (priv->available_chnl[idx] == 100) || + (priv->available_chnl[idx] == 116) || + (priv->available_chnl[idx] == 132) || + (priv->available_chnl[idx] == 149) || + (priv->available_chnl[idx] == 165)) + idx++; + else if ((priv->available_chnl[idx] == 48) || + (priv->available_chnl[idx] == 64) || + (priv->available_chnl[idx] == 112) || + (priv->available_chnl[idx] == 128) || + (priv->available_chnl[idx] == 144) || + (priv->available_chnl[idx] == 161) || + (priv->available_chnl[idx] == 177)) + idx--; + } + + minChan = priv->available_chnl[idx]; + + // skip channel 14 if don't support ofdm + if ((priv->pmib->dot11RFEntry.disable_ch14_ofdm) && + (minChan == 14)) { + score[idx] = 0xffffffff; + + minScore = 0xffffffff; + for (i=0; iavailable_chnl_num; i++) { + if (score[i] < minScore) { + minScore = score[i]; + idx = i; + } + } + minChan = priv->available_chnl[idx]; + } + +#if 0 + //Check if selected channel available for 80M/40M BW or NOT ? + if(priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G) + { + if(priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80) + { + if(!is80MChannel(priv->available_chnl,priv->available_chnl_num,minChan)) + { + //printk("BW=80M, selected channel = %d is unavaliable! reduce to 40M\n", minChan); + //priv->pmib->dot11nConfigEntry.dot11nUse40M = HT_CHANNEL_WIDTH_20_40; + priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20_40; + } + } + + if(priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20_40) + { + if(!is40MChannel(priv->available_chnl,priv->available_chnl_num,minChan)) + { + //printk("BW=40M, selected channel = %d is unavaliable! reduce to 20M\n", minChan); + //priv->pmib->dot11nConfigEntry.dot11nUse40M = HT_CHANNEL_WIDTH_20; + priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20; + } + } + } +#endif + +#ifdef CONFIG_RTL_NEW_AUTOCH + RTL_W32(RXERR_RPT, RXERR_RPT_RST); +#endif + +// auto adjust contro-sideband + if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) + && (priv->pshare->is_40m_bw ==1 || priv->pshare->is_40m_bw ==2)) { + +#ifdef RTK_5G_SUPPORT + if (priv->pmib->dot11RFEntry.phyBandSelect & PHY_BAND_5G) { + if( (minChan>144) ? ((minChan-1)%8) : (minChan%8)) { + GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE; + priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_ABOVE; + } else { + GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW; + priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_BELOW; + } + + } else +#endif + { +#if 0 +#ifdef CONFIG_RTL_NEW_AUTOCH + unsigned int ch_max; + + if (priv->available_chnl[idx_2G_end] >= 13) + ch_max = 13; + else + ch_max = priv->available_chnl[idx_2G_end]; + + if ((minChan >= 5) && (minChan <= (ch_max-5))) { + if (score[minChan+4] > score[minChan-4]) { // what if some channels were cancelled? + GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW; + priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_BELOW; + } else { + GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE; + priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_ABOVE; + } + } else +#endif + { + if (minChan < 5) { + GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE; + priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_ABOVE; + } + else if (minChan > 7) { + GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW; + priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_BELOW; + } + } +#endif + } + } +//----------------------- + +#if defined(__ECOS) && defined(CONFIG_SDIO_HCI) + panic_printk("Auto channel choose ch:%d\n", minChan); +#else +#ifdef _DEBUG_RTL8192CD_ + panic_printk("Auto channel choose ch:%d\n", minChan); +#endif +#endif +#ifdef ACS_DEBUG_INFO//for debug + printk("7. minChan:%d 2nd_offset:%d\n", minChan, priv->pshare->offset_2nd_chan); +#endif + + return minChan; +} +*/ + +#endif + +VOID +phydm_CLMInit( + IN PVOID pDM_VOID, + IN u2Byte sampleNum /*unit : 4us*/ +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_TIME_PERIOD_11AC, bMaskLWord, sampleNum); /*4us sample 1 time*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11AC, BIT8, 0x1); /*Enable CCX for CLM*/ + } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_TIME_PERIOD_11N, bMaskLWord, sampleNum); /*4us sample 1 time*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11N, BIT8, 0x1); /*Enable CCX for CLM*/ + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[%s] : CLM sampleNum = %d\n", __func__, sampleNum)); + +} + +VOID +phydm_CLMtrigger( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11AC, BIT0, 0x0); /*Trigger CLM*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11AC, BIT0, 0x1); + } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11N, BIT0, 0x0); /*Trigger CLM*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11N, BIT0, 0x1); + } +} + +BOOLEAN +phydm_checkCLMready( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte value32 = 0; + BOOLEAN ret = FALSE; + + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_RESULT_11AC, bMaskDWord); /*make sure CLM calc is ready*/ + else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_READY_11N, bMaskDWord); /*make sure CLM calc is ready*/ + + if (value32 & BIT16) + ret = TRUE; + else + ret = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[%s] : CLM ready = %d\n", __func__, ret)); + + return ret; +} + +u2Byte +phydm_getCLMresult( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte value32 = 0; + u2Byte results = 0; + + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_RESULT_11AC, bMaskDWord); /*read CLM calc result*/ + else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_RESULT_11N, bMaskDWord); /*read CLM calc result*/ + + results = (u2Byte)(value32 & bMaskLWord); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[%s] : CLM result = %d\n", __func__, results)); + + return results; +/*results are number of CCA times in sampleNum*/ +} + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_acs.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_acs.h new file mode 100644 index 000000000..d7eabda84 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_acs.h @@ -0,0 +1,129 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMACS_H__ +#define __PHYDMACS_H__ + +#define ACS_VERSION "1.0" +#define CLM_VERSION "1.0" + +#define ODM_MAX_CHANNEL_2G 14 +#define ODM_MAX_CHANNEL_5G 24 + +// For phydm_AutoChannelSelectSettingAP() +#define STORE_DEFAULT_NHM_SETTING 0 +#define RESTORE_DEFAULT_NHM_SETTING 1 +#define ACS_NHM_SETTING 2 + +typedef struct _ACS_ +{ + BOOLEAN bForceACSResult; + u1Byte CleanChannel_2G; + u1Byte CleanChannel_5G; + u2Byte Channel_Info_2G[2][ODM_MAX_CHANNEL_2G]; //Channel_Info[1]: Channel Score, Channel_Info[2]:Channel_Scan_Times + u2Byte Channel_Info_5G[2][ODM_MAX_CHANNEL_5G]; + +#if ( DM_ODM_SUPPORT_TYPE & ODM_AP ) + u1Byte ACS_Step; + // NHM Count 0-11 + u1Byte NHM_Cnt[14][11]; + + // AC-Series, for storing previous setting + u4Byte Reg0x990; + u4Byte Reg0x994; + u4Byte Reg0x998; + u4Byte Reg0x99C; + u1Byte Reg0x9A0; // u1Byte + + // N-Series, for storing previous setting + u4Byte Reg0x890; + u4Byte Reg0x894; + u4Byte Reg0x898; + u4Byte Reg0x89C; + u1Byte Reg0xE28; // u1Byte +#endif + +}ACS, *PACS; + + +VOID +odm_AutoChannelSelectInit( + IN PVOID pDM_VOID +); + +VOID +odm_AutoChannelSelectReset( + IN PVOID pDM_VOID +); + +VOID +odm_AutoChannelSelect( + IN PVOID pDM_VOID, + IN u1Byte Channel +); + +u1Byte +ODM_GetAutoChannelSelectResult( + IN PVOID pDM_VOID, + IN u1Byte Band +); + +#if ( DM_ODM_SUPPORT_TYPE & ODM_AP ) + +VOID +phydm_AutoChannelSelectSettingAP( + IN PVOID pDM_VOID, + IN u4Byte Setting, // 0: STORE_DEFAULT_NHM_SETTING; 1: RESTORE_DEFAULT_NHM_SETTING, 2: ACS_NHM_SETTING + IN u4Byte acs_step +); + +VOID +phydm_GetNHMStatisticsAP( + IN PVOID pDM_VOID, + IN u4Byte idx, // @ 2G, Real channel number = idx+1 + IN u4Byte acs_step +); + +#endif //#if ( DM_ODM_SUPPORT_TYPE & ODM_AP ) + + +VOID +phydm_CLMInit( + IN PVOID pDM_VOID, + IN u2Byte sampleNum +); + +VOID +phydm_CLMtrigger( + IN PVOID pDM_VOID +); + +BOOLEAN +phydm_checkCLMready( + IN PVOID pDM_VOID +); + +u2Byte +phydm_getCLMresult( + IN PVOID pDM_VOID +); + + +#endif //#ifndef __PHYDMACS_H__ \ No newline at end of file diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_adaptivity.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_adaptivity.c new file mode 100644 index 000000000..8883be5f9 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_adaptivity.c @@ -0,0 +1,946 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if WPP_SOFTWARE_TRACE +#include "PhyDM_Adaptivity.tmh" +#endif +#endif + + +VOID +Phydm_CheckAdaptivity( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY); + + if (pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY) { +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (pDM_Odm->APTotalNum > Adaptivity->APNumTH) { + pDM_Odm->Adaptivity_enable = FALSE; + pDM_Odm->adaptivity_flag = FALSE; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("AP total num > %d!!, disable adaptivity\n", Adaptivity->APNumTH)); + } else +#endif + { + if (Adaptivity->DynamicLinkAdaptivity == TRUE) { + if (pDM_Odm->bLinked && Adaptivity->bCheck == FALSE) { + Phydm_NHMCounterStatistics(pDM_Odm); + Phydm_CheckEnvironment(pDM_Odm); + } else if (!pDM_Odm->bLinked) + Adaptivity->bCheck = FALSE; + } else { + pDM_Odm->Adaptivity_enable = TRUE; + + if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) + pDM_Odm->adaptivity_flag = FALSE; + else + pDM_Odm->adaptivity_flag = TRUE; + } + } + } else { + pDM_Odm->Adaptivity_enable = FALSE; + pDM_Odm->adaptivity_flag = FALSE; + } + + + +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +BOOLEAN +Phydm_CheckChannelPlan( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER pAdapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo); + + if (pMgntInfo->RegEnableAdaptivity == 2) { + if (pDM_Odm->Carrier_Sense_enable == FALSE) { /*check domain Code for Adaptivity or CarrierSense*/ + if ((*pDM_Odm->pBandType == ODM_BAND_5G) && + !(pDM_Odm->odm_Regulation5G == REGULATION_ETSI || pDM_Odm->odm_Regulation5G == REGULATION_WW)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 5G domain code : %d\n", pDM_Odm->odm_Regulation5G)); + pDM_Odm->Adaptivity_enable = FALSE; + pDM_Odm->adaptivity_flag = FALSE; + return TRUE; + } else if ((*pDM_Odm->pBandType == ODM_BAND_2_4G) && + !(pDM_Odm->odm_Regulation2_4G == REGULATION_ETSI || pDM_Odm->odm_Regulation2_4G == REGULATION_WW)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity skip 2.4G domain code : %d\n", pDM_Odm->odm_Regulation2_4G)); + pDM_Odm->Adaptivity_enable = FALSE; + pDM_Odm->adaptivity_flag = FALSE; + return TRUE; + + } else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity neither 2G nor 5G band, return\n")); + pDM_Odm->Adaptivity_enable = FALSE; + pDM_Odm->adaptivity_flag = FALSE; + return TRUE; + } + } else { + if ((*pDM_Odm->pBandType == ODM_BAND_5G) && + !(pDM_Odm->odm_Regulation5G == REGULATION_MKK || pDM_Odm->odm_Regulation5G == REGULATION_WW)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 5G domain code : %d\n", pDM_Odm->odm_Regulation5G)); + pDM_Odm->Adaptivity_enable = FALSE; + pDM_Odm->adaptivity_flag = FALSE; + return TRUE; + } + + else if ((*pDM_Odm->pBandType == ODM_BAND_2_4G) && + !(pDM_Odm->odm_Regulation2_4G == REGULATION_MKK || pDM_Odm->odm_Regulation2_4G == REGULATION_WW)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense skip 2.4G domain code : %d\n", pDM_Odm->odm_Regulation2_4G)); + pDM_Odm->Adaptivity_enable = FALSE; + pDM_Odm->adaptivity_flag = FALSE; + return TRUE; + + } else if ((*pDM_Odm->pBandType != ODM_BAND_2_4G) && (*pDM_Odm->pBandType != ODM_BAND_5G)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("CarrierSense neither 2G nor 5G band, return\n")); + pDM_Odm->Adaptivity_enable = FALSE; + pDM_Odm->adaptivity_flag = FALSE; + return TRUE; + } + } + } + + return FALSE; + +} +#endif + +VOID +Phydm_NHMCounterStatisticsInit( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + /*PHY parameters initialize for n series*/ + ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N + 2, 0xC350); /*0x894[31:16]=0x0xC350 Time duration for NHM unit: us, 0xc350=200ms*/ + ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N + 2, 0xffff); /*0x890[31:16]=0xffff th_9, th_10*/ + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff50); /*0x898=0xffffff52 th_3, th_2, th_1, th_0*/ + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff); /*0x89c=0xffffffff th_7, th_6, th_5, th_4*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_FPGA0_IQK_11N, bMaskByte0, 0xff); /*0xe28[7:0]=0xff th_8*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10 | BIT9 | BIT8, 0x1); /*0x890[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT7, 0x1); /*0xc0c[7]=1 max power among all RX ants*/ + } +#if (RTL8195A_SUPPORT == 0) + else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + /*PHY parameters initialize for ac series*/ + ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11AC + 2, 0xC350); /*0x990[31:16]=0xC350 Time duration for NHM unit: us, 0xc350=200ms*/ + ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC + 2, 0xffff); /*0x994[31:16]=0xffff th_9, th_10*/ + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff50); /*0x998=0xffffff52 th_3, th_2, th_1, th_0*/ + ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff); /*0x99c=0xffffffff th_7, th_6, th_5, th_4*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH8_11AC, bMaskByte0, 0xff); /*0x9a0[7:0]=0xff th_8*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8 | BIT9 | BIT10, 0x1); /*0x994[10:8]=1 ignoreCCA ignore PHYTXON enable CCX*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_9E8_11AC, BIT0, 0x1); /*0x9e8[7]=1 max power among all RX ants*/ + + } +#endif +} + +VOID +Phydm_NHMCounterStatistics( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT)) + return; + + /*Get NHM report*/ + Phydm_GetNHMCounterStatistics(pDM_Odm); + + /*Reset NHM counter*/ + Phydm_NHMCounterStatisticsReset(pDM_Odm); +} + +VOID +Phydm_GetNHMCounterStatistics( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte value32 = 0; +#if (RTL8195A_SUPPORT == 0) + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11AC, bMaskDWord); + else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) +#endif + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_NHM_CNT_11N, bMaskDWord); + + pDM_Odm->NHM_cnt_0 = (u1Byte)(value32 & bMaskByte0); + pDM_Odm->NHM_cnt_1 = (u1Byte)((value32 & bMaskByte1) >> 8); + +} + +VOID +Phydm_NHMCounterStatisticsReset( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 0); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT1, 1); + } +#if (RTL8195A_SUPPORT == 0) + else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 0); + ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT1, 1); + } + +#endif + +} + +VOID +Phydm_SetEDCCAThreshold( + IN PVOID pDM_VOID, + IN s1Byte H2L, + IN s1Byte L2H +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskByte2|bMaskByte0, (u4Byte)((u1Byte)L2H|(u1Byte)H2L<<16)); +#if (RTL8195A_SUPPORT == 0) + else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, bMaskLWord, (u2Byte)((u1Byte)L2H|(u1Byte)H2L<<8)); +#endif + +} + +VOID +Phydm_SetLNA( + IN PVOID pDM_VOID, + IN PhyDM_set_LNA type +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (pDM_Odm->SupportICType & (ODM_RTL8188E | ODM_RTL8192E)) { + if (type == PhyDM_disable_LNA) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x37f82); /*disable LNA*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + if (pDM_Odm->RFType > ODM_1T1R) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x37f82); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0); + } + } else if (type == PhyDM_enable_LNA) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0x77f82); /*back to normal*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + if (pDM_Odm->RFType > ODM_1T1R) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0x77f82); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0); + } + } + } else if (pDM_Odm->SupportICType & ODM_RTL8723B) { + if (type == PhyDM_disable_LNA) { + /*S0*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0001f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xe6137); /*disable LNA*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + /*S1*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, 0xfffff, 0x3008d); /*select Rx mode and disable LNA*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0); + } else if (type == PhyDM_enable_LNA) { + /*S0*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0001f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xe6177); /*disable LNA*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + /*S1*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, 0xfffff, 0x300bd); /*select Rx mode and disable LNA*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0); + } + + } else if (pDM_Odm->SupportICType & ODM_RTL8812) { + if (type == PhyDM_disable_LNA) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3f7ff); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + if (pDM_Odm->RFType > ODM_1T1R) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3f7ff); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xc22bf); /*disable LNA*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0); + } + } else if (type == PhyDM_enable_LNA) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x3f7ff); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + if (pDM_Odm->RFType > ODM_1T1R) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x31, 0xfffff, 0x3f7ff); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x32, 0xfffff, 0xc26bf); /*disable LNA*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xef, 0x80000, 0x0); + } + } + } else if (pDM_Odm->SupportICType & (ODM_RTL8821 | ODM_RTL8881A)) { + if (type == PhyDM_disable_LNA) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0002f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xfb09b); /*disable LNA*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + } else if (type == PhyDM_enable_LNA) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x30, 0xfffff, 0x18000); /*select Rx mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x31, 0xfffff, 0x0002f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x32, 0xfffff, 0xfb0bb); /*disable LNA*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0); + } + } +} + + + +VOID +Phydm_SetTRxMux( + IN PVOID pDM_VOID, + IN PhyDM_Trx_MUX_Type txMode, + IN PhyDM_Trx_MUX_Type rxMode +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) { + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT3 | BIT2 | BIT1, txMode); /*set TXmod to standby mode to remove outside noise affect*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N, BIT22 | BIT21 | BIT20, rxMode); /*set RXmod to standby mode to remove outside noise affect*/ + if (pDM_Odm->RFType > ODM_1T1R) { + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT3 | BIT2 | BIT1, txMode); /*set TXmod to standby mode to remove outside noise affect*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_RPT_FORMAT_11N_B, BIT22 | BIT21 | BIT20, rxMode); /*set RXmod to standby mode to remove outside noise affect*/ + } + } +#if (RTL8195A_SUPPORT == 0) + else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT11 | BIT10 | BIT9 | BIT8, txMode); /*set TXmod to standby mode to remove outside noise affect*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC, BIT7 | BIT6 | BIT5 | BIT4, rxMode); /*set RXmod to standby mode to remove outside noise affect*/ + if (pDM_Odm->RFType > ODM_1T1R) { + ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT11 | BIT10 | BIT9 | BIT8, txMode); /*set TXmod to standby mode to remove outside noise affect*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC_B, BIT7 | BIT6 | BIT5 | BIT4, rxMode); /*set RXmod to standby mode to remove outside noise affect*/ + } + } +#endif + +} + +VOID +Phydm_MACEDCCAState( + IN PVOID pDM_VOID, + IN PhyDM_MACEDCCA_Type State +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + if (State == PhyDM_IGNORE_EDCCA) { + ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 1); /*ignore EDCCA reg520[15]=1*/ + ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 0); /*reg524[11]=0*/ + } else { /*don't set MAC ignore EDCCA signal*/ + ODM_SetMACReg(pDM_Odm, REG_TX_PTCL_CTRL, BIT15, 0); /*don't ignore EDCCA reg520[15]=0*/ + ODM_SetMACReg(pDM_Odm, REG_RD_CTRL, BIT11, 1); /*reg524[11]=1 */ + } + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("EDCCA enable State = %d\n", State)); + +} + +BOOLEAN +Phydm_CalNHMcnt( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u2Byte Base = 0; + + Base = pDM_Odm->NHM_cnt_0 + pDM_Odm->NHM_cnt_1; + + if (Base != 0) { + pDM_Odm->NHM_cnt_0 = ((pDM_Odm->NHM_cnt_0) << 8) / Base; + pDM_Odm->NHM_cnt_1 = ((pDM_Odm->NHM_cnt_1) << 8) / Base; + } + if ((pDM_Odm->NHM_cnt_0 - pDM_Odm->NHM_cnt_1) >= 100) + return TRUE; /*clean environment*/ + else + return FALSE; /*noisy environment*/ + +} + + +VOID +Phydm_CheckEnvironment( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY); + BOOLEAN isCleanEnvironment = FALSE; + + if (Adaptivity->bFirstLink == TRUE) { + if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) + pDM_Odm->adaptivity_flag = FALSE; + else + pDM_Odm->adaptivity_flag = TRUE; + + Adaptivity->bFirstLink = FALSE; + return; + } else { + if (Adaptivity->NHMWait < 3) { /*Start enter NHM after 4 NHMWait*/ + Adaptivity->NHMWait++; + Phydm_NHMCounterStatistics(pDM_Odm); + return; + } else { + Phydm_NHMCounterStatistics(pDM_Odm); + isCleanEnvironment = Phydm_CalNHMcnt(pDM_Odm); + if (isCleanEnvironment == TRUE) { + pDM_Odm->TH_L2H_ini = Adaptivity->TH_L2H_ini_backup; /*adaptivity mode*/ + pDM_Odm->TH_EDCCA_HL_diff = Adaptivity->TH_EDCCA_HL_diff_backup; + + pDM_Odm->Adaptivity_enable = TRUE; + + if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) + pDM_Odm->adaptivity_flag = FALSE; + else + pDM_Odm->adaptivity_flag = TRUE; + } else { + pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2; /*mode2*/ + pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2; + + pDM_Odm->adaptivity_flag = FALSE; + pDM_Odm->Adaptivity_enable = FALSE; + } + Adaptivity->NHMWait = 0; + Adaptivity->bFirstLink = TRUE; + Adaptivity->bCheck = TRUE; + } + + } + + +} + +VOID +Phydm_SearchPwdBLowerBound( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY); + u4Byte value32 = 0; + u1Byte cnt, IGI = 0x45; /*IGI = 0x50 for cal EDCCA lower bound*/ + u1Byte txEdcca1 = 0, txEdcca0 = 0; + BOOLEAN bAdjust = TRUE; + s1Byte TH_L2H_dmc, TH_H2L_dmc, IGI_target = 0x32; + s1Byte Diff; + + if (pDM_Odm->SupportICType & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) + Phydm_SetLNA(pDM_Odm, PhyDM_disable_LNA); + else { + Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE); + odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, 0x7e); + } + + Diff = IGI_target - (s1Byte)IGI; + TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff; + if (TH_L2H_dmc > 10) + TH_L2H_dmc = 10; + TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff; + + Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc); + ODM_delay_ms(5); + + while (bAdjust) { + for (cnt = 0; cnt < 20; cnt++) { + if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11N, bMaskDWord); +#if (RTL8195A_SUPPORT == 0) + else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC, bMaskDWord); +#endif + if (value32 & BIT30 && (pDM_Odm->SupportICType & (ODM_RTL8723A | ODM_RTL8723B | ODM_RTL8188E))) + txEdcca1 = txEdcca1 + 1; + else if (value32 & BIT29) + txEdcca1 = txEdcca1 + 1; + else + txEdcca0 = txEdcca0 + 1; + } + + if (txEdcca1 > 1) { + IGI = IGI - 1; + TH_L2H_dmc = TH_L2H_dmc + 1; + if (TH_L2H_dmc > 10) + TH_L2H_dmc = 10; + TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff; + + Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc); + if (TH_L2H_dmc == 10) { + bAdjust = FALSE; + Adaptivity->H2L_lb = TH_H2L_dmc; + Adaptivity->L2H_lb = TH_L2H_dmc; + pDM_Odm->Adaptivity_IGI_upper = IGI; + } + + txEdcca1 = 0; + txEdcca0 = 0; + + } else { + bAdjust = FALSE; + Adaptivity->H2L_lb = TH_H2L_dmc; + Adaptivity->L2H_lb = TH_L2H_dmc; + pDM_Odm->Adaptivity_IGI_upper = IGI; + txEdcca1 = 0; + txEdcca0 = 0; + } + } + + pDM_Odm->Adaptivity_IGI_upper = pDM_Odm->Adaptivity_IGI_upper - pDM_Odm->DCbackoff; + Adaptivity->H2L_lb = Adaptivity->H2L_lb + pDM_Odm->DCbackoff; + Adaptivity->L2H_lb = Adaptivity->L2H_lb + pDM_Odm->DCbackoff; + + if (pDM_Odm->SupportICType & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) + Phydm_SetLNA(pDM_Odm, PhyDM_enable_LNA); + else { + Phydm_SetTRxMux(pDM_Odm, PhyDM_TX_MODE, PhyDM_RX_MODE); + odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, NONE); + } + + Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f); /*resume to no link state*/ +} + +VOID +Phydm_AdaptivityInit( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY); + s1Byte IGItarget = 0x32; + /*pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;*/ +#if(DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER pAdapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo); + pDM_Odm->Carrier_Sense_enable = (BOOLEAN)pMgntInfo->RegEnableCarrierSense; + pDM_Odm->DCbackoff = (u1Byte)pMgntInfo->RegDCbackoff; + Adaptivity->DynamicLinkAdaptivity = (BOOLEAN)pMgntInfo->RegDmLinkAdaptivity; + Adaptivity->APNumTH = (u1Byte)pMgntInfo->RegAPNumTH; +#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) + pDM_Odm->Carrier_Sense_enable = (pDM_Odm->Adapter->registrypriv.adaptivity_mode != 0) ? TRUE : FALSE; + pDM_Odm->DCbackoff = pDM_Odm->Adapter->registrypriv.adaptivity_dc_backoff; + Adaptivity->DynamicLinkAdaptivity = (pDM_Odm->Adapter->registrypriv.adaptivity_dml != 0) ? TRUE : FALSE; +#endif + + +#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) + + if (pDM_Odm->Carrier_Sense_enable == FALSE) { +#if(DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (pMgntInfo->RegL2HForAdaptivity != 0) + pDM_Odm->TH_L2H_ini = pMgntInfo->RegL2HForAdaptivity; + else +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (pDM_Odm->Adapter->registrypriv.adaptivity_th_l2h_ini != 0) + pDM_Odm->TH_L2H_ini = pDM_Odm->Adapter->registrypriv.adaptivity_th_l2h_ini; + else +#endif + pDM_Odm->TH_L2H_ini = 0xf5; + } else + pDM_Odm->TH_L2H_ini = 0xa; + +#if(DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (pMgntInfo->RegHLDiffForAdaptivity != 0) + pDM_Odm->TH_EDCCA_HL_diff = pMgntInfo->RegHLDiffForAdaptivity; + else +#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) + if (pDM_Odm->Adapter->registrypriv.adaptivity_th_edcca_hl_diff != 0) + pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->Adapter->registrypriv.adaptivity_th_edcca_hl_diff; + else +#endif + pDM_Odm->TH_EDCCA_HL_diff = 7; + + Adaptivity->TH_L2H_ini_backup = pDM_Odm->TH_L2H_ini; + Adaptivity->TH_EDCCA_HL_diff_backup = pDM_Odm->TH_EDCCA_HL_diff; + +#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + prtl8192cd_priv priv = pDM_Odm->priv; + + if (pDM_Odm->Carrier_Sense_enable) { + pDM_Odm->TH_L2H_ini = 0xa; + pDM_Odm->TH_EDCCA_HL_diff = 7; + } else { + Adaptivity->TH_L2H_ini_backup = pDM_Odm->TH_L2H_ini; /*set by mib*/ + pDM_Odm->TH_EDCCA_HL_diff = 7; + } + + Adaptivity->TH_EDCCA_HL_diff_backup = pDM_Odm->TH_EDCCA_HL_diff; + if (priv->pshare->rf_ft_var.adaptivity_enable == 2) + Adaptivity->DynamicLinkAdaptivity = TRUE; + else + Adaptivity->DynamicLinkAdaptivity = FALSE; + +#endif + + pDM_Odm->Adaptivity_IGI_upper = 0; + pDM_Odm->Adaptivity_enable = FALSE; /*use this flag to decide enable or disable*/ + + if (pDM_Odm->bWIFITest == TRUE || pDM_Odm->mp_mode == TRUE) + pDM_Odm->EDCCA_enable = FALSE; + else + pDM_Odm->EDCCA_enable = TRUE; /*even no adaptivity, we still enable EDCCA*/ + + pDM_Odm->TH_L2H_ini_mode2 = 20; + pDM_Odm->TH_EDCCA_HL_diff_mode2 = 8; + + Adaptivity->IGI_Base = 0x32; + Adaptivity->IGI_target = 0x1c; + Adaptivity->H2L_lb = 0; + Adaptivity->L2H_lb = 0; + Adaptivity->NHMWait = 0; + Adaptivity->bCheck = FALSE; + Adaptivity->bFirstLink = TRUE; + Adaptivity->AdajustIGILevel = 0; + + Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA); + + /*Search pwdB lower bound*/ + if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11N, bMaskDWord, 0x208); +#if (RTL8195A_SUPPORT == 0) + else if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC, bMaskDWord, 0x209); +#endif + + if (pDM_Odm->SupportICType & ODM_IC_11N_GAIN_IDX_EDCCA) { + /*ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DOWN_OPT_11N, BIT12 | BIT11 | BIT10, 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DCNF_11N, BIT21 | BIT20, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ + } +#if (RTL8195A_SUPPORT == 0) + if (pDM_Odm->SupportICType & ODM_IC_11AC_GAIN_IDX_EDCCA) { /*8814a no need to find pwdB lower bound, maybe*/ + /*ODM_SetBBReg(pDM_Odm, ODM_REG_EDCCA_DOWN_OPT, BIT30 | BIT29 | BIT28, 0x7);*/ /*interfernce need > 2^x us, and then EDCCA will be 1*/ + ODM_SetBBReg(pDM_Odm, ODM_REG_ACBB_EDCCA_ENHANCE, BIT29 | BIT28, 0x1); /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/ + } + + if(!(pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))) + Phydm_SearchPwdBLowerBound(pDM_Odm); +#endif + +/*we need to consider PwdB upper bound for 8814 later IC*/ + Adaptivity->AdajustIGILevel = (u1Byte)((pDM_Odm->TH_L2H_ini + IGItarget) - PwdBUpperBound + DFIRloss); /*IGI = L2H - PwdB - DFIRloss*/ + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("TH_L2H_ini = 0x%x, TH_EDCCA_HL_diff = 0x%x, Adaptivity->AdajustIGILevel = 0x%x\n", pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff, Adaptivity->AdajustIGILevel)); + + /*phydm_setEDCCAThresholdAPI(pDM_Odm, pDM_DigTable->CurIGValue);*/ + +} + + +VOID +Phydm_Adaptivity( + IN PVOID pDM_VOID, + IN u1Byte IGI +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + s1Byte TH_L2H_dmc, TH_H2L_dmc; + s1Byte Diff = 0, IGI_target; + PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER pAdapter = pDM_Odm->Adapter; + BOOLEAN bFwCurrentInPSMode = FALSE; + PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo); + + pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode)); + + /*Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.*/ + if (bFwCurrentInPSMode) + return; +#endif + + if ((pDM_Odm->EDCCA_enable == FALSE) || (pDM_Odm->bWIFITest == TRUE)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Disable EDCCA!!!\n")); + return; + } + + if (!(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("adaptivity disable, enable EDCCA mode!!!\n")); + pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2; + pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2; + } +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + else{ + if (Phydm_CheckChannelPlan(pDM_Odm) || (pDM_Odm->APTotalNum > Adaptivity->APNumTH)) { + pDM_Odm->TH_L2H_ini = pDM_Odm->TH_L2H_ini_mode2; + pDM_Odm->TH_EDCCA_HL_diff = pDM_Odm->TH_EDCCA_HL_diff_mode2; + } + } +#endif + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("odm_Adaptivity() =====>\n")); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI_Base=0x%x, TH_L2H_ini = %d, TH_EDCCA_HL_diff = %d\n", + Adaptivity->IGI_Base, pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff)); +#if (RTL8195A_SUPPORT == 0) + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) { + /*fix AC series when enable EDCCA hang issue*/ + ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 1); /*ADC_mask disable*/ + ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 0); /*ADC_mask enable*/ + } +#endif + if (*pDM_Odm->pBandWidth == ODM_BW20M) /*CHANNEL_WIDTH_20*/ + IGI_target = Adaptivity->IGI_Base; + else if (*pDM_Odm->pBandWidth == ODM_BW40M) + IGI_target = Adaptivity->IGI_Base + 2; +#if (RTL8195A_SUPPORT == 0) + else if (*pDM_Odm->pBandWidth == ODM_BW80M) + IGI_target = Adaptivity->IGI_Base + 2; +#endif + else + IGI_target = Adaptivity->IGI_Base; + Adaptivity->IGI_target = (u1Byte) IGI_target; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("BandWidth=%s, IGI_target=0x%x, DynamicLinkAdaptivity = %d\n", + (*pDM_Odm->pBandWidth == ODM_BW80M) ? "80M" : ((*pDM_Odm->pBandWidth == ODM_BW40M) ? "40M" : "20M"), IGI_target, Adaptivity->DynamicLinkAdaptivity)); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("RSSI_min = %d, Adaptivity->AdajustIGILevel= 0x%x, adaptivity_flag = %d, Adaptivity_enable = %d\n", + pDM_Odm->RSSI_Min, Adaptivity->AdajustIGILevel, pDM_Odm->adaptivity_flag, pDM_Odm->Adaptivity_enable)); + + if ((Adaptivity->DynamicLinkAdaptivity == TRUE) && (!pDM_Odm->bLinked) && (pDM_Odm->Adaptivity_enable == FALSE)) { + Phydm_SetEDCCAThreshold(pDM_Odm, 0x7f, 0x7f); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("In DynamicLink mode(noisy) and No link, Turn off EDCCA!!\n")); + return; + } + + if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) { + if ((Adaptivity->AdajustIGILevel > IGI) && (pDM_Odm->Adaptivity_enable == TRUE)) + Diff = Adaptivity->AdajustIGILevel - IGI; + + TH_L2H_dmc = pDM_Odm->TH_L2H_ini - Diff + IGI_target; + TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff; + } +#if (RTL8195A_SUPPORT == 0) + else { + Diff = IGI_target - (s1Byte)IGI; + TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff; + if (TH_L2H_dmc > 10 && (pDM_Odm->Adaptivity_enable == TRUE)) + TH_L2H_dmc = 10; + + TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff; + + /*replace lower bound to prevent EDCCA always equal 1*/ + if (TH_H2L_dmc < Adaptivity->H2L_lb) + TH_H2L_dmc = Adaptivity->H2L_lb; + if (TH_L2H_dmc < Adaptivity->L2H_lb) + TH_L2H_dmc = Adaptivity->L2H_lb; + } +#endif + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d\n", IGI, TH_L2H_dmc, TH_H2L_dmc)); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("Adaptivity_IGI_upper=0x%x, H2L_lb = 0x%x, L2H_lb = 0x%x\n", pDM_Odm->Adaptivity_IGI_upper, Adaptivity->H2L_lb, Adaptivity->L2H_lb)); + + Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc); + return; +} + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +VOID +Phydm_AdaptivityBSOD( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER pAdapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo); + u1Byte count = 0; + u4Byte u4Value; + + /* + 1. turn off RF (TRX Mux in standby mode) + 2. H2C mac id drop + 3. ignore EDCCA + 4. wait for clear FIFO + 5. don't ignore EDCCA + 6. turn on RF (TRX Mux in TRx mdoe) + 7. H2C mac id resume + */ + + RT_TRACE(COMP_MLME, DBG_WARNING, ("MAC id drop packet!!!!!\n")); + + pAdapter->dropPktByMacIdCnt++; + pMgntInfo->bDropPktInProgress = TRUE; + + pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_MAX_Q_PAGE_NUM, (pu1Byte)(&u4Value)); + RT_TRACE(COMP_INIT, DBG_LOUD, ("Queue Reserved Page Number = 0x%08x\n", u4Value)); + pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_AVBL_Q_PAGE_NUM, (pu1Byte)(&u4Value)); + RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page Number = 0x%08x\n", u4Value)); + +#if 1 + + /*Standby mode*/ + Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE); + ODM_Write_DIG(pDM_Odm, 0x20); + + /*H2C mac id drop*/ + MacIdIndicateDisconnect(pAdapter); + + /*Ignore EDCCA*/ + Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA); + + delay_ms(50); + count = 5; + +#else + + do { + + u8Byte diffTime, curTime, oldestTime; + u1Byte queueIdx + + //3 Standby mode + Phydm_SetTRxMux(pDM_Odm, PhyDM_STANDBY_MODE, PhyDM_STANDBY_MODE); + ODM_Write_DIG(pDM_Odm, 0x20); + + //3 H2C mac id drop + MacIdIndicateDisconnect(pAdapter); + + //3 Ignore EDCCA + Phydm_MACEDCCAState(pDM_Odm, PhyDM_IGNORE_EDCCA); + + count++; + delay_ms(10); + + // Check latest packet + curTime = PlatformGetCurrentTime(); + oldestTime = 0xFFFFFFFFFFFFFFFF; + + for (queueIdx = 0; queueIdx < MAX_TX_QUEUE; queueIdx++) { + if (!IS_DATA_QUEUE(queueIdx)) + continue; + + if (!pAdapter->bTcbBusyQEmpty[queueIdx]) { + RT_TRACE(COMP_MLME, DBG_WARNING, ("oldestTime = %llu\n", oldestTime)); + RT_TRACE(COMP_MLME, DBG_WARNING, ("Q[%d] = %llu\n", queueIdx, pAdapter->firstTcbSysTime[queueIdx])); + if (pAdapter->firstTcbSysTime[queueIdx] < oldestTime) + oldestTime = pAdapter->firstTcbSysTime[queueIdx]; + } + } + + diffTime = curTime - oldestTime; + + RT_TRACE(COMP_MLME, DBG_WARNING, ("diff s = %llu\n", (diffTime / 1000000))); + + } while (((diffTime / 1000000) >= 4) && (oldestTime != 0xFFFFFFFFFFFFFFFF)); +#endif + + /*Resume EDCCA*/ + Phydm_MACEDCCAState(pDM_Odm, PhyDM_DONT_IGNORE_EDCCA); + + /*Turn on TRx mode*/ + Phydm_SetTRxMux(pDM_Odm, PhyDM_TX_MODE, PhyDM_RX_MODE); + ODM_Write_DIG(pDM_Odm, 0x20); + + /*Resume H2C macid*/ + MacIdRecoverMediaStatus(pAdapter); + + pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_AVBL_Q_PAGE_NUM, (pu1Byte)(&u4Value)); + RT_TRACE(COMP_INIT, DBG_LOUD, ("Available Queue Page Number = 0x%08x\n", u4Value)); + + pMgntInfo->bDropPktInProgress = FALSE; + RT_TRACE(COMP_MLME, DBG_WARNING, ("End of MAC id drop packet, spent %dms\n", count * 10)); + +} + +#endif + +VOID +phydm_setEDCCAThresholdAPI( + IN PVOID pDM_VOID, + IN u1Byte IGI +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTIVITY_STATISTICS Adaptivity = (PADAPTIVITY_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_ADAPTIVITY); + s1Byte TH_L2H_dmc, TH_H2L_dmc; + s1Byte Diff = 0, IGI_target = 0x32; + + if (pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY) { + + if (pDM_Odm->SupportICType & (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) { + if (Adaptivity->AdajustIGILevel > IGI) + Diff = Adaptivity->AdajustIGILevel - IGI; + + TH_L2H_dmc = pDM_Odm->TH_L2H_ini - Diff + IGI_target; + TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff; + } +#if (RTL8195A_SUPPORT == 0) + else { + Diff = IGI_target - (s1Byte)IGI; + TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff; + if (TH_L2H_dmc > 10) + TH_L2H_dmc = 10; + + TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff; + + /*replace lower bound to prevent EDCCA always equal 1*/ + if (TH_H2L_dmc < Adaptivity->H2L_lb) + TH_H2L_dmc = Adaptivity->H2L_lb; + if (TH_L2H_dmc < Adaptivity->L2H_lb) + TH_L2H_dmc = Adaptivity->L2H_lb; + } +#endif + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("API :IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d\n", IGI, TH_L2H_dmc, TH_H2L_dmc)); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_ADAPTIVITY, ODM_DBG_LOUD, ("API :Adaptivity_IGI_upper=0x%x, H2L_lb = 0x%x, L2H_lb = 0x%x\n", pDM_Odm->Adaptivity_IGI_upper, Adaptivity->H2L_lb, Adaptivity->L2H_lb)); + + Phydm_SetEDCCAThreshold(pDM_Odm, TH_H2L_dmc, TH_L2H_dmc); + } + +} diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_adaptivity.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_adaptivity.h new file mode 100644 index 000000000..819ea346c --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_adaptivity.h @@ -0,0 +1,172 @@ + +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMADAPTIVITY_H__ +#define __PHYDMADAPTIVITY_H__ + +#define ADAPTIVITY_VERSION "9.0" + +#define PwdBUpperBound 7 +#define DFIRloss 5 + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) +typedef enum _tag_PhyDM_REGULATION_Type { + REGULATION_FCC = 0, + REGULATION_MKK = 1, + REGULATION_ETSI = 2, + REGULATION_WW = 3, + + MAX_REGULATION_NUM = 4 +} PhyDM_REGULATION_TYPE; +#endif + +typedef enum tag_PhyDM_set_LNA { + PhyDM_disable_LNA = 0, + PhyDM_enable_LNA = 1, +} PhyDM_set_LNA; + + +typedef enum tag_PhyDM_TRx_MUX_Type +{ + PhyDM_SHUTDOWN = 0, + PhyDM_STANDBY_MODE = 1, + PhyDM_TX_MODE = 2, + PhyDM_RX_MODE = 3 +}PhyDM_Trx_MUX_Type; + +typedef enum tag_PhyDM_MACEDCCA_Type +{ + PhyDM_IGNORE_EDCCA = 0, + PhyDM_DONT_IGNORE_EDCCA = 1 +}PhyDM_MACEDCCA_Type; + +typedef struct _ADAPTIVITY_STATISTICS { + s1Byte TH_L2H_ini_backup; + s1Byte TH_EDCCA_HL_diff_backup; + s1Byte IGI_Base; + u1Byte IGI_target; + u1Byte NHMWait; + s1Byte H2L_lb; + s1Byte L2H_lb; + BOOLEAN bFirstLink; + BOOLEAN bCheck; + BOOLEAN DynamicLinkAdaptivity; + u1Byte APNumTH; + u1Byte AdajustIGILevel; +} ADAPTIVITY_STATISTICS, *PADAPTIVITY_STATISTICS; + +VOID +Phydm_CheckAdaptivity( + IN PVOID pDM_VOID + ); + +VOID +Phydm_CheckEnvironment( + IN PVOID pDM_VOID + ); + +VOID +Phydm_NHMCounterStatisticsInit( + IN PVOID pDM_VOID + ); + +VOID +Phydm_NHMCounterStatistics( + IN PVOID pDM_VOID + ); + +VOID +Phydm_NHMCounterStatisticsReset( + IN PVOID pDM_VOID +); + +VOID +Phydm_GetNHMCounterStatistics( + IN PVOID pDM_VOID +); + +VOID +Phydm_MACEDCCAState( + IN PVOID pDM_VOID, + IN PhyDM_MACEDCCA_Type State +); + +VOID +Phydm_SetEDCCAThreshold( + IN PVOID pDM_VOID, + IN s1Byte H2L, + IN s1Byte L2H +); + +VOID +Phydm_SetTRxMux( + IN PVOID pDM_VOID, + IN PhyDM_Trx_MUX_Type txMode, + IN PhyDM_Trx_MUX_Type rxMode +); + +BOOLEAN +Phydm_CalNHMcnt( + IN PVOID pDM_VOID +); + +VOID +Phydm_SearchPwdBLowerBound( + IN PVOID pDM_VOID +); + +VOID +Phydm_AdaptivityInit( + IN PVOID pDM_VOID + ); + +VOID +Phydm_Adaptivity( + IN PVOID pDM_VOID, + IN u1Byte IGI + ); + +VOID +phydm_setEDCCAThresholdAPI( + IN PVOID pDM_VOID, + IN u1Byte IGI +); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +Phydm_DisableEDCCA( + IN PVOID pDM_VOID +); + +VOID +Phydm_DynamicEDCCA( + IN PVOID pDM_VOID +); + +VOID +Phydm_AdaptivityBSOD( + IN PVOID pDM_VOID +); + +#endif + + +#endif diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_antdect.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_antdect.c new file mode 100644 index 000000000..afa478cb4 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_antdect.c @@ -0,0 +1,964 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +//#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) +#if(defined(CONFIG_ANT_DETECTION)) + +//IS_ANT_DETECT_SUPPORT_SINGLE_TONE(Adapter) +//IS_ANT_DETECT_SUPPORT_RSSI(Adapter) +//IS_ANT_DETECT_SUPPORT_PSD(Adapter) + +//1 [1. Single Tone Method] =================================================== + +// +// Description: +// Set Single/Dual Antenna default setting for products that do not do detection in advance. +// +// Added by Joseph, 2012.03.22 +// +VOID +ODM_SingleDualAntennaDefaultSetting( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + PADAPTER pAdapter = pDM_Odm->Adapter; + + u1Byte btAntNum=BT_GetPgAntNum(pAdapter); + // Set default antenna A and B status + if(btAntNum == 2) + { + pDM_SWAT_Table->ANTA_ON=TRUE; + pDM_SWAT_Table->ANTB_ON=TRUE; + + } + else if(btAntNum == 1) + {// Set antenna A as default + pDM_SWAT_Table->ANTA_ON=TRUE; + pDM_SWAT_Table->ANTB_ON=FALSE; + + } + else + { + RT_ASSERT(FALSE, ("Incorrect antenna number!!\n")); + } +} + + +//2 8723A ANT DETECT +// +// Description: +// Implement IQK single tone for RF DPK loopback and BB PSD scanning. +// This function is cooperated with BB team Neil. +// +// Added by Roger, 2011.12.15 +// +BOOLEAN +ODM_SingleDualAntennaDetection( + IN PVOID pDM_VOID, + IN u1Byte mode + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER pAdapter = pDM_Odm->Adapter; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + u4Byte CurrentChannel,RfLoopReg; + u1Byte n; + u4Byte Reg88c, Regc08, Reg874, Regc50, Reg948, Regb2c, Reg92c, Reg930, Reg064, AFE_rRx_Wait_CCA; + u1Byte initial_gain = 0x5a; + u4Byte PSD_report_tmp; + u4Byte AntA_report = 0x0, AntB_report = 0x0, AntO_report = 0x0; + BOOLEAN bResult = TRUE; + u4Byte AFE_Backup[16]; + u4Byte AFE_REG_8723A[16] = { + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN, + rFPGA0_XCD_SwitchControl, rBlue_Tooth}; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection()============>\n")); + + + if (!(pDM_Odm->SupportICType & ODM_RTL8723B)) + return bResult; + + // Retrieve antenna detection registry info, added by Roger, 2012.11.27. + if(!IS_ANT_DETECT_SUPPORT_SINGLE_TONE(pAdapter)) + return bResult; + + //1 Backup Current RF/BB Settings + + CurrentChannel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask); + RfLoopReg = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask); + if (pDM_Odm->SupportICType & ODM_RTL8723B) { + Reg92c = ODM_GetBBReg(pDM_Odm, rDPDT_control, bMaskDWord); + Reg930 = ODM_GetBBReg(pDM_Odm, rfe_ctrl_anta_src, bMaskDWord); + Reg948 = ODM_GetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord); + Regb2c = ODM_GetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord); + Reg064 = ODM_GetMACReg(pDM_Odm, rSYM_WLBT_PAPE_SEL, BIT29); + ODM_SetBBReg(pDM_Odm, rDPDT_control, 0x3, 0x1); + ODM_SetBBReg(pDM_Odm, rfe_ctrl_anta_src, 0xff, 0x77); + ODM_SetMACReg(pDM_Odm, rSYM_WLBT_PAPE_SEL, BIT29, 0x1); //dbg 7 + ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0x3c0, 0x0);//dbg 8 + ODM_SetBBReg(pDM_Odm, rAGC_table_select, BIT31, 0x0); + } + + ODM_StallExecution(10); + + //Store A Path Register 88c, c08, 874, c50 + Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord); + Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord); + Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord); + Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord); + + // Store AFE Registers + if (pDM_Odm->SupportICType & ODM_RTL8723B) + AFE_rRx_Wait_CCA = ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA,bMaskDWord); + + //Set PSD 128 pts + ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0); //128 pts + + // To SET CH1 to do + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x7401); //Channel 1 + + // AFE all on step + if (pDM_Odm->SupportICType & ODM_RTL8723B) + ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x01c00016); + + // 3 wire Disable + ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0); + + //BB IQK Setting + ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4); + ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000); + + //IQK setting tone@ 4.34Mhz + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + + //Page B init + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000); + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f); + if (pDM_Odm->SupportICType & ODM_RTL8723B) { + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82150016); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150016); + } + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0); + ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7f, initial_gain); + + //IQK Single tone start + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x808000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + ODM_StallExecution(10000); + + // PSD report of antenna A + PSD_report_tmp=0x0; + for (n=0;n<2;n++) + { + PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain); + if(PSD_report_tmp >AntA_report) + AntA_report=PSD_report_tmp; + } + + // change to Antenna B + if (pDM_Odm->SupportICType & ODM_RTL8723B) { + //ODM_SetBBReg(pDM_Odm, rDPDT_control, 0x3, 0x2); + ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0xfff, 0x280); + ODM_SetBBReg(pDM_Odm, rAGC_table_select, BIT31, 0x1); + } + + ODM_StallExecution(10); + + // PSD report of antenna B + PSD_report_tmp=0x0; + for (n=0;n<2;n++) + { + PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain); + if(PSD_report_tmp > AntB_report) + AntB_report=PSD_report_tmp; + } + + //Close IQK Single Tone function + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, 0xffffff00, 0x000000); + + //1 Return to antanna A + if (pDM_Odm->SupportICType & ODM_RTL8723B) { + // external DPDT + ODM_SetBBReg(pDM_Odm, rDPDT_control, bMaskDWord, Reg92c); + + //internal S0/S1 + ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord, Reg948); + ODM_SetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord, Regb2c); + ODM_SetBBReg(pDM_Odm, rfe_ctrl_anta_src, bMaskDWord, Reg930); + ODM_SetMACReg(pDM_Odm, rSYM_WLBT_PAPE_SEL, BIT29, Reg064); + } + + ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08); + ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874); + ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40); + ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord, Regc50); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,CurrentChannel); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask,RfLoopReg); + + //Reload AFE Registers + if (pDM_Odm->SupportICType & ODM_RTL8723B) + ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, AFE_rRx_Wait_CCA); + + if (pDM_Odm->SupportICType & ODM_RTL8723B) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d\n", 2416, AntA_report)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d\n", 2416, AntB_report)); + + //2 Test Ant B based on Ant A is ON + if((AntA_report >= 100) && (AntB_report >= 100) && (AntA_report <= 135) && (AntB_report <= 135)) + { + u1Byte TH1=2, TH2=6; + + if((AntA_report - AntB_report < TH1) || (AntB_report - AntA_report < TH1)) + { + pDM_SWAT_Table->ANTA_ON=TRUE; + pDM_SWAT_Table->ANTB_ON=TRUE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SingleDualAntennaDetection(): Dual Antenna\n")); + } + else if(((AntA_report - AntB_report >= TH1) && (AntA_report - AntB_report <= TH2)) || + ((AntB_report - AntA_report >= TH1) && (AntB_report - AntA_report <= TH2))) + { + pDM_SWAT_Table->ANTA_ON=FALSE; + pDM_SWAT_Table->ANTB_ON=FALSE; + bResult = FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n")); + } + else + { + pDM_SWAT_Table->ANTA_ON = TRUE; + pDM_SWAT_Table->ANTB_ON=FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SingleDualAntennaDetection(): Single Antenna\n")); + } + pDM_Odm->AntDetectedInfo.bAntDetected= TRUE; + pDM_Odm->AntDetectedInfo.dBForAntA = AntA_report; + pDM_Odm->AntDetectedInfo.dBForAntB = AntB_report; + pDM_Odm->AntDetectedInfo.dBForAntO = AntO_report; + + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("return FALSE!!\n")); + bResult = FALSE; + } + } + return bResult; + +} + + + +//1 [2. Scan AP RSSI Method] ================================================== + + + + +BOOLEAN +ODM_SwAntDivCheckBeforeLink( + IN PVOID pDM_VOID + ) +{ + +#if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM) + + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE* pHalData = GET_HAL_DATA(Adapter); + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + s1Byte Score = 0; + PRT_WLAN_BSS pTmpBssDesc, pTestBssDesc; + u1Byte power_target_L = 9, power_target_H = 16; + u1Byte tmp_power_diff = 0,power_diff = 0,avg_power_diff = 0,max_power_diff = 0,min_power_diff = 0xff; + u2Byte index, counter = 0; + static u1Byte ScanChannel; + u4Byte tmp_SWAS_NoLink_BK_Reg948; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ANTA_ON = (( %d )) , ANTB_ON = (( %d ))\n", pDM_Odm->DM_SWAT_Table.ANTA_ON, pDM_Odm->DM_SWAT_Table.ANTB_ON)); + + //if(HP id) + { + if(pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult==TRUE && pDM_Odm->SupportICType == ODM_RTL8723B) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("8723B RSSI-based Antenna Detection is done\n")); + return FALSE; + } + + if(pDM_Odm->SupportICType == ODM_RTL8723B) + { + if(pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 == 0xff) + pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 = ODM_Read4Byte(pDM_Odm, rS0S1_PathSwitch ); + } + } + + if (pDM_Odm->Adapter == NULL) //For BSOD when plug/unplug fast. //By YJ,120413 + { // The ODM structure is not initialized. + return FALSE; + } + + // Retrieve antenna detection registry info, added by Roger, 2012.11.27. + if(!IS_ANT_DETECT_SUPPORT_RSSI(Adapter)) + { + return FALSE; + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Antenna Detection: RSSI Method\n")); + } + + // Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF. + PlatformAcquireSpinLock(Adapter, RT_RF_STATE_SPINLOCK); + if(pHalData->eRFPowerState!=eRfOn || pMgntInfo->RFChangeInProgress || pMgntInfo->bMediaConnect) + { + PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("ODM_SwAntDivCheckBeforeLink(): RFChangeInProgress(%x), eRFPowerState(%x)\n", + pMgntInfo->RFChangeInProgress, pHalData->eRFPowerState)); + + pDM_SWAT_Table->SWAS_NoLink_State = 0; + + return FALSE; + } + else + { + PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK); + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("pDM_SWAT_Table->SWAS_NoLink_State = %d\n", pDM_SWAT_Table->SWAS_NoLink_State)); + //1 Run AntDiv mechanism "Before Link" part. + if(pDM_SWAT_Table->SWAS_NoLink_State == 0) + { + //1 Prepare to do Scan again to check current antenna state. + + // Set check state to next step. + pDM_SWAT_Table->SWAS_NoLink_State = 1; + + // Copy Current Scan list. + pMgntInfo->tmpNumBssDesc = pMgntInfo->NumBssDesc; + PlatformMoveMemory((PVOID)Adapter->MgntInfo.tmpbssDesc, (PVOID)pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC); + + // Go back to scan function again. + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Scan one more time\n")); + pMgntInfo->ScanStep=0; + pMgntInfo->bScanAntDetect = TRUE; + ScanChannel = odm_SwAntDivSelectScanChnl(Adapter); + + + if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8821)) + { + if(pDM_FatTable->RxIdleAnt == MAIN_ANT) + ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT); + else + ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT); + if(ScanChannel == 0) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("ODM_SwAntDivCheckBeforeLink(): No AP List Avaiable, Using Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"AUX_ANT":"MAIN_ANT")); + + if(IS_5G_WIRELESS_MODE(pMgntInfo->dot11CurrentWirelessMode)) + { + pDM_SWAT_Table->Ant5G = pDM_FatTable->RxIdleAnt; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant5G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + } + else + { + pDM_SWAT_Table->Ant2G = pDM_FatTable->RxIdleAnt; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant2G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + } + return FALSE; + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("ODM_SwAntDivCheckBeforeLink: Change to %s for testing.\n", ((pDM_FatTable->RxIdleAnt == MAIN_ANT)?"MAIN_ANT":"AUX_ANT"))); + } else if (pDM_Odm->SupportICType & (ODM_RTL8723B)) { + /*Switch Antenna to another one.*/ + + tmp_SWAS_NoLink_BK_Reg948 = ODM_Read4Byte(pDM_Odm, rS0S1_PathSwitch); + + if ((pDM_SWAT_Table->CurAntenna == MAIN_ANT) && (tmp_SWAS_NoLink_BK_Reg948 == 0x200)) { + ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0xfff, 0x280); + ODM_SetBBReg(pDM_Odm, rAGC_table_select, BIT31, 0x1); + pDM_SWAT_Table->CurAntenna = AUX_ANT; + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Reg[948]= (( %x )) was in wrong state\n", tmp_SWAS_NoLink_BK_Reg948)); + return FALSE; + } + ODM_StallExecution(10); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Change to (( %s-ant)) for testing.\n", (pDM_SWAT_Table->CurAntenna == MAIN_ANT)?"MAIN":"AUX")); + } + + odm_SwAntDivConstructScanChnl(Adapter, ScanChannel); + PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5); + + return TRUE; + } + else //pDM_SWAT_Table->SWAS_NoLink_State == 1 + { + //1 ScanComple() is called after antenna swiched. + //1 Check scan result and determine which antenna is going + //1 to be used. + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,(" tmpNumBssDesc= (( %d )) \n",pMgntInfo->tmpNumBssDesc));// debug for Dino + + for(index = 0; index < pMgntInfo->tmpNumBssDesc; index++) + { + pTmpBssDesc = &(pMgntInfo->tmpbssDesc[index]); // Antenna 1 + pTestBssDesc = &(pMgntInfo->bssDesc[index]); // Antenna 2 + + if(PlatformCompareMemory(pTestBssDesc->bdBssIdBuf, pTmpBssDesc->bdBssIdBuf, 6)!=0) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): ERROR!! This shall not happen.\n")); + continue; + } + + if(pDM_Odm->SupportICType != ODM_RTL8723B) + { + if(pTmpBssDesc->ChannelNumber == ScanChannel) + { + if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Compare scan entry: Score++\n")); + RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); + + Score++; + PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS)); + } + else if(pTmpBssDesc->RecvSignalPower < pTestBssDesc->RecvSignalPower) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Compare scan entry: Score--\n")); + RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); + Score--; + } + else + { + if(pTestBssDesc->bdTstamp - pTmpBssDesc->bdTstamp < 5000) + { + RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("The 2nd Antenna didn't get this AP\n\n")); + } + } + } + } + else // 8723B + { + if(pTmpBssDesc->ChannelNumber == ScanChannel) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ChannelNumber == ScanChannel -> (( %d )) \n", pTmpBssDesc->ChannelNumber )); + + if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower) // Pow(Ant1) > Pow(Ant2) + { + counter++; + tmp_power_diff=(u1Byte)(pTmpBssDesc->RecvSignalPower - pTestBssDesc->RecvSignalPower); + power_diff = power_diff + tmp_power_diff; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); + ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf); + ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf); + + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("tmp_power_diff: (( %d)),max_power_diff: (( %d)),min_power_diff: (( %d)) \n", tmp_power_diff,max_power_diff,min_power_diff)); + if(tmp_power_diff > max_power_diff) + max_power_diff=tmp_power_diff; + if(tmp_power_diff < min_power_diff) + min_power_diff=tmp_power_diff; + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("max_power_diff: (( %d)),min_power_diff: (( %d)) \n",max_power_diff,min_power_diff)); + + PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS)); + } + else if(pTestBssDesc->RecvSignalPower > pTmpBssDesc->RecvSignalPower) // Pow(Ant1) < Pow(Ant2) + { + counter++; + tmp_power_diff=(u1Byte)(pTestBssDesc->RecvSignalPower - pTmpBssDesc->RecvSignalPower); + power_diff = power_diff + tmp_power_diff; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); + ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf); + ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf); + if(tmp_power_diff > max_power_diff) + max_power_diff=tmp_power_diff; + if(tmp_power_diff < min_power_diff) + min_power_diff=tmp_power_diff; + } + else // Pow(Ant1) = Pow(Ant2) + { + if(pTestBssDesc->bdTstamp > pTmpBssDesc->bdTstamp) // Stamp(Ant1) < Stamp(Ant2) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("time_diff: %lld\n", (pTestBssDesc->bdTstamp-pTmpBssDesc->bdTstamp)/1000)); + if(pTestBssDesc->bdTstamp - pTmpBssDesc->bdTstamp > 5000) + { + counter++; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); + ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf); + ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf); + min_power_diff = 0; + } + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Error !!!]: Time_diff: %lld\n", (pTestBssDesc->bdTstamp-pTmpBssDesc->bdTstamp)/1000)); + } + } + } + } + } + + if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8821)) + { + if(pMgntInfo->NumBssDesc!=0 && Score<0) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("ODM_SwAntDivCheckBeforeLink(): Using Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + ("ODM_SwAntDivCheckBeforeLink(): Remain Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"AUX_ANT":"MAIN_ANT")); + + if(pDM_FatTable->RxIdleAnt == MAIN_ANT) + ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT); + else + ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT); + } + + if(IS_5G_WIRELESS_MODE(pMgntInfo->dot11CurrentWirelessMode)) + { + pDM_SWAT_Table->Ant5G = pDM_FatTable->RxIdleAnt; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant5G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + } + else + { + pDM_SWAT_Table->Ant2G = pDM_FatTable->RxIdleAnt; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant2G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + } + } + else if(pDM_Odm->SupportICType == ODM_RTL8723B) + { + if(counter == 0) + { + if(pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec == FALSE) + { + pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec = TRUE; + pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Counter=(( 0 )) , [[ Cannot find any AP with Aux-ant ]] -> Scan Target-channel again \n")); + + //3 [ Scan again ] + odm_SwAntDivConstructScanChnl(Adapter, ScanChannel); + PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5); + return TRUE; + } + else// Pre_Aux_FailDetec == TRUE + { + //2 [ Single Antenna ] + pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec = FALSE; + pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Counter=(( 0 )) , [[ Still cannot find any AP ]] \n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n")); + } + pDM_Odm->DM_SWAT_Table.Aux_FailDetec_Counter++; + } + else + { + pDM_Odm->DM_SWAT_Table.Pre_Aux_FailDetec = FALSE; + + if(counter==3) + { + avg_power_diff = ((power_diff-max_power_diff - min_power_diff)>>1)+ ((max_power_diff + min_power_diff)>>2); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: (( %d )) , power_diff: (( %d )) \n", counter, power_diff)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ counter==3 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d )) \n", avg_power_diff,max_power_diff, min_power_diff)); + } + else if(counter>=4) + { + avg_power_diff=(power_diff-max_power_diff - min_power_diff) / (counter - 2); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: (( %d )) , power_diff: (( %d )) \n", counter, power_diff)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ counter>=4 ] Modified avg_power_diff: (( %d )) , max_power_diff: (( %d )) , min_power_diff: (( %d )) \n", avg_power_diff,max_power_diff, min_power_diff)); + + } + else//counter==1,2 + { + avg_power_diff=power_diff/counter; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("avg_power_diff: (( %d )) , counter: (( %d )) , power_diff: (( %d )) \n", avg_power_diff,counter, power_diff)); + } + + //2 [ Retry ] + if( (avg_power_diff >=power_target_L) && (avg_power_diff <=power_target_H) ) + { + pDM_Odm->DM_SWAT_Table.Retry_Counter++; + + if(pDM_Odm->DM_SWAT_Table.Retry_Counter<=3) + { + pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[[ Low confidence result ]] avg_power_diff= (( %d )) -> Scan Target-channel again ]] \n", avg_power_diff)); + + //3 [ Scan again ] + odm_SwAntDivConstructScanChnl(Adapter, ScanChannel); + PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5); + return TRUE; + } + else + { + pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[[ Still Low confidence result ]] (( Retry_Counter > 3 )) \n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n")); + } + + } + //2 [ Dual Antenna ] + else if( (pMgntInfo->NumBssDesc != 0) && (avg_power_diff < power_target_L) ) + { + pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE; + if(pDM_Odm->DM_SWAT_Table.ANTB_ON == FALSE) + { + pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE; + pDM_Odm->DM_SWAT_Table.ANTB_ON = TRUE; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SwAntDivCheckBeforeLink(): Dual antenna\n")); + pDM_Odm->DM_SWAT_Table.Dual_Ant_Counter++; + + // set bt coexDM from 1ant coexDM to 2ant coexDM + BT_SetBtCoexAntNum(Adapter, BT_COEX_ANT_TYPE_DETECTED, 2); + + //3 [ Init antenna diversity ] + pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV; + ODM_AntDivInit(pDM_Odm); + } + //2 [ Single Antenna ] + else if(avg_power_diff > power_target_H) + { + pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult=TRUE; + if(pDM_Odm->DM_SWAT_Table.ANTB_ON == TRUE) + { + pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE; + pDM_Odm->DM_SWAT_Table.ANTB_ON = FALSE; + //BT_SetBtCoexAntNum(Adapter, BT_COEX_ANT_TYPE_DETECTED, 1); + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n")); + pDM_Odm->DM_SWAT_Table.Single_Ant_Counter++; + } + } + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("bResult=(( %d ))\n",pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Dual_Ant_Counter = (( %d )), Single_Ant_Counter = (( %d )) , Retry_Counter = (( %d )) , Aux_FailDetec_Counter = (( %d ))\n\n\n", + pDM_Odm->DM_SWAT_Table.Dual_Ant_Counter,pDM_Odm->DM_SWAT_Table.Single_Ant_Counter,pDM_Odm->DM_SWAT_Table.Retry_Counter,pDM_Odm->DM_SWAT_Table.Aux_FailDetec_Counter)); + + //2 recover the antenna setting + + if(pDM_Odm->DM_SWAT_Table.ANTB_ON == FALSE) + ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0xfff, (pDM_SWAT_Table->SWAS_NoLink_BK_Reg948)); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("bResult=(( %d )), Recover Reg[948]= (( %x )) \n\n",pDM_Odm->DM_SWAT_Table.RSSI_AntDect_bResult, pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 )); + + + } + + // Check state reset to default and wait for next time. + pDM_SWAT_Table->SWAS_NoLink_State = 0; + pMgntInfo->bScanAntDetect = FALSE; + + return FALSE; + } + +#else + return FALSE; +#endif + +return FALSE; +} + + + + + + +//1 [3. PSD Method] ========================================================== + + + + +u4Byte +odm_GetPSDData( + IN PVOID pDM_VOID, + IN u2Byte point, + IN u1Byte initial_gain) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte psd_report; + + ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point); + ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 1); //Start PSD calculation, Reg808[22]=0->1 + ODM_StallExecution(150);//Wait for HW PSD report + ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 0);//Stop PSD calculation, Reg808[22]=1->0 + psd_report = ODM_GetBBReg(pDM_Odm,0x8B4, bMaskDWord) & 0x0000FFFF;//Read PSD report, Reg8B4[15:0] + + psd_report = (u4Byte) (odm_ConvertTo_dB(psd_report));//+(u4Byte)(initial_gain); + return psd_report; +} + + + +VOID +ODM_SingleDualAntennaDetection_PSD( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte Channel_ori; + u1Byte initial_gain = 0x36; + u1Byte tone_idx; + u1Byte Tone_lenth_1=7, Tone_lenth_2=4; + u2Byte Tone_idx_1[7]={88, 104, 120, 8, 24, 40, 56}; + u2Byte Tone_idx_2[4]={8, 24, 40, 56}; + u4Byte PSD_report_Main[11]={0}, PSD_report_Aux[11]={0}; + //u1Byte Tone_lenth_1=4, Tone_lenth_2=2; + //u2Byte Tone_idx_1[4]={88, 120, 24, 56}; + //u2Byte Tone_idx_2[2]={ 24, 56}; + //u4Byte PSD_report_Main[6]={0}, PSD_report_Aux[6]={0}; + + u4Byte PSD_report_temp,MAX_PSD_report_Main=0,MAX_PSD_report_Aux=0; + u4Byte PSD_power_threshold; + u4Byte Main_psd_result=0, Aux_psd_result=0; + u4Byte Regc50, Reg948, Regb2c,Regc14,Reg908; + u4Byte i=0,test_num=8; + + + if(pDM_Odm->SupportICType != ODM_RTL8723B) + return; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection_PSD()============> \n")); + + //2 [ Backup Current RF/BB Settings ] + + Channel_ori = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask); + Reg948 = ODM_GetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord); + Regb2c = ODM_GetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord); + Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord); + Regc14 = ODM_GetBBReg(pDM_Odm, 0xc14, bMaskDWord); + Reg908 = ODM_GetBBReg(pDM_Odm, 0x908, bMaskDWord); + + //2 [ Setting for doing PSD function (CH4)] + ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0); //disable whole CCK block + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); // Turn off TX -> Pause TX Queue + ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0); // [ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA] + + // PHYTXON while loop + ODM_SetBBReg(pDM_Odm, 0x908, bMaskDWord, 0x803); + while (ODM_GetBBReg(pDM_Odm, 0xdf4, BIT6)) + { + i++; + if (i > 1000000) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Wait in %s() more than %d times!\n", __FUNCTION__, i)); + break; + } + } + + ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, initial_gain); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); // Set RF to CH4 & 40M + ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0xf); // 3 wire Disable 88c[23:20]=0xf + ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0); //128 pt //Set PSD 128 ptss + ODM_StallExecution(3000); + + + //2 [ Doing PSD Function in (CH4)] + + //Antenna A + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Main-ant (CH4)\n")); + ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x200); + ODM_StallExecution(10); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dbg\n")); + for (i=0;iPSD_report_Main[tone_idx] ) + PSD_report_Main[tone_idx]+=PSD_report_temp; + } + } + //Antenna B + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Aux-ant (CH4)\n")); + ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x280); + ODM_StallExecution(10); + for (i=0;iPSD_report_Aux[tone_idx] ) + PSD_report_Aux[tone_idx]+=PSD_report_temp; + } + } + //2 [ Doing PSD Function in (CH8)] + + ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0x0); // 3 wire enable 88c[23:20]=0x0 + ODM_StallExecution(3000); + + ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, initial_gain); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, 0x7ff, 0x04); // Set RF to CH8 & 40M + + ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0xf); // 3 wire Disable 88c[23:20]=0xf + ODM_StallExecution(3000); + + //Antenna A + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Main-ant (CH8)\n")); + ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x200); + ODM_StallExecution(10); + + for (i=0;iPSD_report_Main[tone_idx] ) + PSD_report_Main[Tone_lenth_1+tone_idx]+=PSD_report_temp; + } + } + + //Antenna B + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Switch to Aux-ant (CH8)\n")); + ODM_SetBBReg(pDM_Odm, 0x948, 0xfff, 0x280); + ODM_StallExecution(10); + + for (i=0;iPSD_report_Aux[tone_idx] ) + PSD_report_Aux[Tone_lenth_1+tone_idx]+=PSD_report_temp; + } + } + + //2 [ Calculate Result ] + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\nMain PSD Result: (ALL) \n")); + for (tone_idx=0;tone_idx<(Tone_lenth_1+Tone_lenth_2);tone_idx++) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tone-%d]: %d, \n",(tone_idx+1), PSD_report_Main[tone_idx] )); + Main_psd_result+= PSD_report_Main[tone_idx]; + if(PSD_report_Main[tone_idx]>MAX_PSD_report_Main) + MAX_PSD_report_Main=PSD_report_Main[tone_idx]; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--------------------------- \nTotal_Main= (( %d ))\n", Main_psd_result)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAX_Main = (( %d ))\n", MAX_PSD_report_Main)); + + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\nAux PSD Result: (ALL) \n")); + for (tone_idx=0;tone_idx<(Tone_lenth_1+Tone_lenth_2);tone_idx++) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tone-%d]: %d, \n",(tone_idx+1), PSD_report_Aux[tone_idx] )); + Aux_psd_result+= PSD_report_Aux[tone_idx]; + if(PSD_report_Aux[tone_idx]>MAX_PSD_report_Aux) + MAX_PSD_report_Aux=PSD_report_Aux[tone_idx]; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("--------------------------- \nTotal_Aux= (( %d ))\n", Aux_psd_result)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("MAX_Aux = (( %d ))\n\n", MAX_PSD_report_Aux)); + + //Main_psd_result=Main_psd_result-MAX_PSD_report_Main; + //Aux_psd_result=Aux_psd_result-MAX_PSD_report_Aux; + PSD_power_threshold=(Main_psd_result*7)>>3; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Main_result , Aux_result ] = [ %d , %d ], PSD_power_threshold=(( %d ))\n", Main_psd_result, Aux_psd_result,PSD_power_threshold)); + + //3 [ Dual Antenna ] + if(Aux_psd_result >= PSD_power_threshold ) + { + if(pDM_Odm->DM_SWAT_Table.ANTB_ON == FALSE) + { + pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE; + pDM_Odm->DM_SWAT_Table.ANTB_ON = TRUE; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SwAntDivCheckBeforeLink(): Dual antenna\n")); + + // set bt coexDM from 1ant coexDM to 2ant coexDM + //BT_SetBtCoexAntNum(pAdapter, BT_COEX_ANT_TYPE_DETECTED, 2); + + // Init antenna diversity + pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV; + ODM_AntDivInit(pDM_Odm); + } + //3 [ Single Antenna ] + else + { + if(pDM_Odm->DM_SWAT_Table.ANTB_ON == TRUE) + { + pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE; + pDM_Odm->DM_SWAT_Table.ANTB_ON = FALSE; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n")); + } + + //2 [ Recover all parameters ] + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,Channel_ori); + ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, 0xf00000, 0x0); // 3 wire enable 88c[23:20]=0x0 + ODM_SetBBReg(pDM_Odm, 0xc50, 0x7f, Regc50); + + ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord, Reg948); + ODM_SetBBReg(pDM_Odm, rAGC_table_select, bMaskDWord, Regb2c); + + ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 1); //enable whole CCK block + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x0); //Turn on TX // Resume TX Queue + ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, Regc14); // [ Set IQK Matrix = 0 ] equivalent to [ Turn on CCA] + ODM_SetBBReg(pDM_Odm, 0x908, bMaskDWord, Reg908); + + return; + +} + +#endif +void +odm_SwAntDetectInit( + IN PVOID pDM_VOID + ) +{ +#if(defined(CONFIG_ANT_DETECTION)) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + + //pDM_SWAT_Table->PreAntenna = MAIN_ANT; + //pDM_SWAT_Table->CurAntenna = MAIN_ANT; + pDM_SWAT_Table->SWAS_NoLink_State = 0; + pDM_SWAT_Table->Pre_Aux_FailDetec = FALSE; + pDM_SWAT_Table->SWAS_NoLink_BK_Reg948 = 0xff; +#endif +} + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_antdect.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_antdect.h new file mode 100644 index 000000000..8cf60e8f9 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_antdect.h @@ -0,0 +1,98 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMANTDECT_H__ +#define __PHYDMANTDECT_H__ + +#define ANTDECT_VERSION "2.1" /*2015.07.29 by YuChen*/ + +#if(defined(CONFIG_ANT_DETECTION)) +//#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN |ODM_CE)) +//ANT Test +#define ANTTESTALL 0x00 /*Ant A or B will be Testing*/ +#define ANTTESTA 0x01 /*Ant A will be Testing*/ +#define ANTTESTB 0x02 /*Ant B will be testing*/ + +#define MAX_ANTENNA_DETECTION_CNT 10 + + +typedef struct _ANT_DETECTED_INFO{ + BOOLEAN bAntDetected; + u4Byte dBForAntA; + u4Byte dBForAntB; + u4Byte dBForAntO; +}ANT_DETECTED_INFO, *PANT_DETECTED_INFO; + + +typedef enum tag_SW_Antenna_Switch_Definition +{ + Antenna_A = 1, + Antenna_B = 2, + Antenna_MAX = 3, +}DM_SWAS_E; + + + +//1 [1. Single Tone Method] =================================================== + + + +VOID +ODM_SingleDualAntennaDefaultSetting( + IN PVOID pDM_VOID + ); + +BOOLEAN +ODM_SingleDualAntennaDetection( + IN PVOID pDM_VOID, + IN u1Byte mode + ); + +//1 [2. Scan AP RSSI Method] ================================================== + +#define SwAntDivCheckBeforeLink ODM_SwAntDivCheckBeforeLink + +BOOLEAN +ODM_SwAntDivCheckBeforeLink( + IN PVOID pDM_VOID + ); + + + + +//1 [3. PSD Method] ========================================================== + + +VOID +ODM_SingleDualAntennaDetection_PSD( + IN PVOID pDM_VOID +); + +#endif + +VOID +odm_SwAntDetectInit( + IN PVOID pDM_VOID + ); + + +#endif + + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_antdiv.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_antdiv.c new file mode 100644 index 000000000..188af39cf --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_antdiv.c @@ -0,0 +1,4762 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +//====================================================== +// when antenna test utility is on or some testing need to disable antenna diversity +// call this function to disable all ODM related mechanisms which will switch antenna. +//====================================================== +VOID +ODM_StopAntennaSwitchDm( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + // disable ODM antenna diversity + pDM_Odm->SupportAbility &= ~ODM_BB_ANT_DIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("STOP Antenna Diversity \n")); +} + +VOID +ODM_SetAntConfig( + IN PVOID pDM_VOID, + IN u1Byte antSetting // 0=A, 1=B, 2=C, .... + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + if(pDM_Odm->SupportICType == ODM_RTL8723B) + { + if(antSetting == 0) // ant A + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000000); + else if(antSetting == 1) + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000280); + } +} + +//====================================================== + + +VOID +ODM_SwAntDivRestAfterLink( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + u4Byte i; + + if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) { + + pDM_SWAT_Table->try_flag = SWAW_STEP_INIT; + pDM_SWAT_Table->RSSI_Trying = 0; + pDM_SWAT_Table->Double_chk_flag= 0; + + pDM_FatTable->RxIdleAnt=MAIN_ANT; + + for (i=0; iMainAnt_Sum[i] = 0; + pDM_FatTable->AuxAnt_Sum[i] = 0; + pDM_FatTable->MainAnt_Cnt[i] = 0; + pDM_FatTable->AuxAnt_Cnt[i] = 0; + } + + } +} + + +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) +VOID +odm_AntDiv_on_off( + IN PVOID pDM_VOID , + IN u1Byte swch + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + if(pDM_FatTable->AntDiv_OnOff != swch) + { + if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) + return; + + if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) N-Series HW-AntDiv block\n",(swch==ANTDIV_ON)?"ON" : "OFF")); + ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, swch); //OFDM AntDiv function block enable + ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, swch); //CCK AntDiv function block enable + } + else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) AC-Series HW-AntDiv block\n",(swch==ANTDIV_ON)?"ON" : "OFF")); + if (pDM_Odm->SupportICType == ODM_RTL8812) { + ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, swch); //OFDM AntDiv function block enable + ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, swch); //CCK AntDiv function block enable + } else { + ODM_SetBBReg(pDM_Odm, 0x8D4 , BIT24, swch); //OFDM AntDiv function block enable + + if( (pDM_Odm->CutVersion >= ODM_CUT_C) && (pDM_Odm->SupportICType == ODM_RTL8821) && ( pDM_Odm->AntDivType != S0S1_SW_ANTDIV)) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) CCK HW-AntDiv block\n",(swch==ANTDIV_ON)?"ON" : "OFF")); + ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, swch); + ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, swch); //CCK AntDiv function block enable + } + } + } + } + pDM_FatTable->AntDiv_OnOff =swch; + +} + +VOID +phydm_FastTraining_enable( + IN PVOID pDM_VOID, + IN u1Byte swch + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte enable; + + if (swch == FAT_ON) + enable=1; + else + enable=0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Fast Ant Training_en = ((%d))\n", enable)); + + if (pDM_Odm->SupportICType == ODM_RTL8188E) { + ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, enable); /*enable fast training*/ + /**/ + } else if (pDM_Odm->SupportICType == ODM_RTL8192E) { + ODM_SetBBReg(pDM_Odm, 0xB34 , BIT28, enable); /*enable fast training (path-A)*/ + /*ODM_SetBBReg(pDM_Odm, 0xB34 , BIT29, enable);*/ /*enable fast training (path-B)*/ + } else if (pDM_Odm->SupportICType == ODM_RTL8821) { + ODM_SetBBReg(pDM_Odm, 0x900 , BIT19, enable); /*enable fast training */ + /**/ + } +} + +VOID +odm_Tx_By_TxDesc_or_Reg( + IN PVOID pDM_VOID, + IN u1Byte swch + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte enable; + + enable = (swch == TX_BY_DESC) ? 1 : 0; + + if(pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV) + { + if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT) + { + ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, enable); + } + else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT) + { + ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, enable); + } + } +} + +VOID +ODM_UpdateRxIdleAnt( + IN PVOID pDM_VOID, + IN u1Byte Ant + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + u4Byte DefaultAnt, OptionalAnt,value32; + + if(pDM_FatTable->RxIdleAnt != Ant) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] RxIdleAnt =%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + + if(!(pDM_Odm->SupportICType & ODM_RTL8723B)) + pDM_FatTable->RxIdleAnt = Ant; + + if(Ant == MAIN_ANT) + { + DefaultAnt = ANT1_2G; + OptionalAnt = ANT2_2G; + } + else + { + DefaultAnt = ANT2_2G; + OptionalAnt = ANT1_2G; + } + + if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT) + { + if(pDM_Odm->SupportICType==ODM_RTL8192E) + { + ODM_SetBBReg(pDM_Odm, 0xB38 , BIT5|BIT4|BIT3, DefaultAnt); //Default RX + ODM_SetBBReg(pDM_Odm, 0xB38 , BIT8|BIT7|BIT6, OptionalAnt);//Optional RX + ODM_SetBBReg(pDM_Odm, 0x860, BIT14|BIT13|BIT12, DefaultAnt);//Default TX + } + #if (RTL8723B_SUPPORT == 1) + else if (pDM_Odm->SupportICType == ODM_RTL8723B) { + + value32 = ODM_GetBBReg(pDM_Odm, 0x948, 0xFFF); + + if(value32 !=0x280) + ODM_UpdateRxIdleAnt_8723B(pDM_Odm, Ant, DefaultAnt, OptionalAnt); + else { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Fail to set RX antenna due to 0x948 = 0x280\n")); + /**/ + } + } + #endif + else { /*8188E & 8188F*/ + + #if (RTL8188F_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8188F) { + phydm_update_rx_idle_antenna_8188F(pDM_Odm, DefaultAnt); + /**/ + } + #endif + + ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, DefaultAnt); /*Default RX*/ + ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, OptionalAnt); /*Optional RX*/ + ODM_SetBBReg(pDM_Odm, 0x860, BIT14|BIT13|BIT12, DefaultAnt); /*Default TX*/ + } + } + else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT) + { + u2Byte value16 = ODM_Read2Byte(pDM_Odm, ODM_REG_TRMUX_11AC+2); + // + // 2014/01/14 MH/Luke.Lee Add direct write for register 0xc0a to prevnt + // incorrect 0xc08 bit0-15 .We still not know why it is changed. + // + value16 &= ~(BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3); + value16 |= ((u2Byte)DefaultAnt <<3); + value16 |= ((u2Byte)OptionalAnt <<6); + value16 |= ((u2Byte)DefaultAnt <<9); + ODM_Write2Byte(pDM_Odm, ODM_REG_TRMUX_11AC+2, value16); + /* + ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC , BIT21|BIT20|BIT19, DefaultAnt); //Default RX + ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC , BIT24|BIT23|BIT22, OptionalAnt);//Optional RX + ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC , BIT27|BIT26|BIT25, DefaultAnt); //Default TX + */ + } + + if(pDM_Odm->SupportICType==ODM_RTL8188E) + { + ODM_SetMACReg(pDM_Odm, 0x6D8 , BIT7|BIT6, DefaultAnt); //PathA Resp Tx + } + else + { + ODM_SetMACReg(pDM_Odm, 0x6D8 , BIT10|BIT9|BIT8, DefaultAnt); //PathA Resp Tx + } + + } + else// pDM_FatTable->RxIdleAnt == Ant + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Stay in Ori-Ant ] RxIdleAnt =%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + pDM_FatTable->RxIdleAnt = Ant; + } +} + +VOID +odm_UpdateTxAnt( + IN PVOID pDM_VOID, + IN u1Byte Ant, + IN u4Byte MacId + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + u1Byte TxAnt; + + if (pDM_Odm->AntDivType==CG_TRX_SMART_ANTDIV) + { + TxAnt=Ant; + } + else + { + if(Ant == MAIN_ANT) + TxAnt = ANT1_2G; + else + TxAnt = ANT2_2G; + } + + pDM_FatTable->antsel_a[MacId] = TxAnt&BIT0; + pDM_FatTable->antsel_b[MacId] = (TxAnt&BIT1)>>1; + pDM_FatTable->antsel_c[MacId] = (TxAnt&BIT2)>>2; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tx from TxInfo]: MacID:(( %d )), TxAnt = (( %s ))\n", MacId, (Ant == MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=(( 3'b%d%d%d ))\n",pDM_FatTable->antsel_c[MacId] , pDM_FatTable->antsel_b[MacId] , pDM_FatTable->antsel_a[MacId] )); + +} + +#ifdef BEAMFORMING_SUPPORT +#if(DM_ODM_SUPPORT_TYPE == ODM_AP) + +VOID +odm_BDC_Init( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pBDC_T pDM_BdcTable=&pDM_Odm->DM_BdcTable; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n[ BDC Initialization......] \n")); + pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; + pDM_BdcTable->BDC_Mode=BDC_MODE_NULL; + pDM_BdcTable->BDC_Try_flag=0; + pDM_BdcTable->BDCcoexType_wBfer=0; + pDM_Odm->bdc_holdstate=0xff; + + if(pDM_Odm->SupportICType == ODM_RTL8192E) + { + ODM_SetBBReg(pDM_Odm, 0xd7c , 0x0FFFFFFF, 0x1081008); + ODM_SetBBReg(pDM_Odm, 0xd80 , 0x0FFFFFFF, 0); + } + else if(pDM_Odm->SupportICType == ODM_RTL8812) + { + ODM_SetBBReg(pDM_Odm, 0x9b0 , 0x0FFFFFFF, 0x1081008); //0x9b0[30:0] = 01081008 + ODM_SetBBReg(pDM_Odm, 0x9b4 , 0x0FFFFFFF, 0); //0x9b4[31:0] = 00000000 + } + +} + + +VOID +odm_CSI_on_off( + IN PVOID pDM_VOID, + IN u1Byte CSI_en + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + if(CSI_en==CSI_ON) + { + if(pDM_Odm->SupportICType == ODM_RTL8192E) + { + ODM_SetMACReg(pDM_Odm, 0xd84 , BIT11, 1); //0xd84[11]=1 + } + else if(pDM_Odm->SupportICType == ODM_RTL8812) + { + ODM_SetMACReg(pDM_Odm, 0x9b0 , BIT31, 1); //0x9b0[31]=1 + } + + } + else if(CSI_en==CSI_OFF) + { + if(pDM_Odm->SupportICType == ODM_RTL8192E) + { + ODM_SetMACReg(pDM_Odm, 0xd84 , BIT11, 0); //0xd84[11]=0 + } + else if(pDM_Odm->SupportICType == ODM_RTL8812) + { + ODM_SetMACReg(pDM_Odm, 0x9b0 , BIT31, 0); //0x9b0[31]=0 + } + } +} + +VOID +odm_BDCcoexType_withBferClient( + IN PVOID pDM_VOID, + IN u1Byte swch + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pBDC_T pDM_BdcTable = &pDM_Odm->DM_BdcTable; + u1Byte BDCcoexType_wBfer; + + if(swch==DIVON_CSIOFF) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[BDCcoexType: 1] {DIV,CSI} ={1,0} \n")); + BDCcoexType_wBfer=1; + + if(BDCcoexType_wBfer != pDM_BdcTable->BDCcoexType_wBfer) + { + odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); + odm_CSI_on_off(pDM_Odm,CSI_OFF); + pDM_BdcTable->BDCcoexType_wBfer=1; + } + } + else if(swch==DIVOFF_CSION) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[BDCcoexType: 2] {DIV,CSI} ={0,1}\n")); + BDCcoexType_wBfer=2; + + if(BDCcoexType_wBfer != pDM_BdcTable->BDCcoexType_wBfer) + { + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + odm_CSI_on_off(pDM_Odm,CSI_ON); + pDM_BdcTable->BDCcoexType_wBfer=2; + } + } +} + +VOID +odm_BF_AntDiv_ModeArbitration( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pBDC_T pDM_BdcTable = &pDM_Odm->DM_BdcTable; + u1Byte current_BDC_Mode; + + #if(DM_ODM_SUPPORT_TYPE == ODM_AP) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n")); + + //2 Mode 1 + if((pDM_BdcTable->num_Txbfee_Client !=0) && (pDM_BdcTable->num_Txbfer_Client == 0)) + { + current_BDC_Mode=BDC_MODE_1; + + if(current_BDC_Mode != pDM_BdcTable->BDC_Mode) + { + pDM_BdcTable->BDC_Mode=BDC_MODE_1; + odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); + pDM_BdcTable->BDC_RxIdleUpdate_counter=1; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode1 ))\n")); + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance Mode] : (( Mode1 ))\n")); + } + //2 Mode 2 + else if((pDM_BdcTable->num_Txbfee_Client ==0) && (pDM_BdcTable->num_Txbfer_Client != 0)) + { + current_BDC_Mode=BDC_MODE_2; + + if(current_BDC_Mode != pDM_BdcTable->BDC_Mode) + { + pDM_BdcTable->BDC_Mode=BDC_MODE_2; + pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; + pDM_BdcTable->BDC_Try_flag=0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode2 ))\n")); + + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance Mode] : (( Mode2 ))\n")); + } + //2 Mode 3 + else if((pDM_BdcTable->num_Txbfee_Client !=0) && (pDM_BdcTable->num_Txbfer_Client != 0)) + { + current_BDC_Mode=BDC_MODE_3; + + if(current_BDC_Mode != pDM_BdcTable->BDC_Mode) + { + pDM_BdcTable->BDC_Mode=BDC_MODE_3; + pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; + pDM_BdcTable->BDC_Try_flag=0; + pDM_BdcTable->BDC_RxIdleUpdate_counter=1; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode3 ))\n")); + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance Mode] : (( Mode3 ))\n")); + } + //2 Mode 4 + else if((pDM_BdcTable->num_Txbfee_Client ==0) && (pDM_BdcTable->num_Txbfer_Client == 0)) + { + current_BDC_Mode=BDC_MODE_4; + + if(current_BDC_Mode != pDM_BdcTable->BDC_Mode) + { + pDM_BdcTable->BDC_Mode=BDC_MODE_4; + odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode4 ))\n")); + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance Mode] : (( Mode4 ))\n")); + } + #endif + +} + +VOID +odm_DivTrainState_setting( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pBDC_T pDM_BdcTable=&pDM_Odm->DM_BdcTable; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n*****[S T A R T ]***** [2-0. DIV_TRAIN_STATE] \n")); + pDM_BdcTable->BDC_Try_counter =2; + pDM_BdcTable->BDC_Try_flag=1; + pDM_BdcTable->BDC_state=BDC_BFer_TRAIN_STATE; + odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); +} + +VOID +odm_BDCcoex_BFeeRxDiv_Arbitration( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pBDC_T pDM_BdcTable = &pDM_Odm->DM_BdcTable; + BOOLEAN StopBF_flag; + u1Byte BDC_active_Mode; + + + #if(DM_ODM_SUPPORT_TYPE == ODM_AP) + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***{ num_BFee, num_BFer , num_Client} = (( %d , %d , %d)) \n",pDM_BdcTable->num_Txbfee_Client,pDM_BdcTable->num_Txbfer_Client,pDM_BdcTable->num_Client)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***{ num_BF_tars, num_DIV_tars } = (( %d , %d )) \n",pDM_BdcTable->num_BfTar , pDM_BdcTable->num_DivTar )); + + //2 [ MIB control ] + if (pDM_Odm->bdc_holdstate==2) + { + odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); + pDM_BdcTable->BDC_state=BDC_BF_HOLD_STATE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Force in [ BF STATE] \n")); + return; + } + else if (pDM_Odm->bdc_holdstate==1) + { + pDM_BdcTable->BDC_state=BDC_DIV_HOLD_STATE; + odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Force in [ DIV STATE] \n")); + return; + } + + //------------------------------------------------------------ + + + + //2 Mode 2 & 3 + if(pDM_BdcTable->BDC_Mode==BDC_MODE_2 ||pDM_BdcTable->BDC_Mode==BDC_MODE_3) + { + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n{ Try_flag , Try_counter } = { %d , %d } \n",pDM_BdcTable->BDC_Try_flag,pDM_BdcTable->BDC_Try_counter)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BDCcoexType = (( %d )) \n\n", pDM_BdcTable->BDCcoexType_wBfer)); + + // All Client have Bfer-Cap------------------------------- + if(pDM_BdcTable->num_Txbfer_Client == pDM_BdcTable->num_Client) //BFer STA Only?: yes + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BFer STA only? (( Yes ))\n")); + pDM_BdcTable->BDC_Try_flag=0; + pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; + odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); + return; + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BFer STA only? (( No ))\n")); + } + // + if(pDM_BdcTable->bAll_BFSta_Idle==FALSE && pDM_BdcTable->bAll_DivSta_Idle==TRUE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("All DIV-STA are idle, but BF-STA not\n")); + pDM_BdcTable->BDC_Try_flag=0; + pDM_BdcTable->BDC_state=BDC_BFer_TRAIN_STATE; + odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); + return; + } + else if(pDM_BdcTable->bAll_BFSta_Idle==TRUE && pDM_BdcTable->bAll_DivSta_Idle==FALSE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("All BF-STA are idle, but DIV-STA not\n")); + pDM_BdcTable->BDC_Try_flag=0; + pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; + odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); + return; + } + + //Select active mode-------------------------------------- + if(pDM_BdcTable->num_BfTar ==0) // Selsect_1, Selsect_2 + { + if(pDM_BdcTable->num_DivTar ==0) // Selsect_3 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 1 )) \n")); + pDM_BdcTable->BDC_active_Mode=1; + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 2 ))\n")); + pDM_BdcTable->BDC_active_Mode=2; + } + pDM_BdcTable->BDC_Try_flag=0; + pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; + odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); + return; + } + else // num_BfTar > 0 + { + if(pDM_BdcTable->num_DivTar ==0) // Selsect_3 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 3 ))\n")); + pDM_BdcTable->BDC_active_Mode=3; + pDM_BdcTable->BDC_Try_flag=0; + pDM_BdcTable->BDC_state=BDC_BFer_TRAIN_STATE; + odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); + return; + } + else // Selsect_4 + { + BDC_active_Mode=4; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 4 ))\n")); + + if(BDC_active_Mode!=pDM_BdcTable->BDC_active_Mode) + { + pDM_BdcTable->BDC_active_Mode=4; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to active mode (( 4 )) & return!!! \n")); + return; + } + } + } + +#if 1 + if (pDM_Odm->bdc_holdstate==0xff) + { + pDM_BdcTable->BDC_state=BDC_DIV_HOLD_STATE; + odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Force in [ DIV STATE] \n")); + return; + } +#endif + + // Does Client number changed ? ------------------------------- + if(pDM_BdcTable->num_Client !=pDM_BdcTable->pre_num_Client) + { + pDM_BdcTable->BDC_Try_flag=0; + pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ The number of client has been changed !!!] return to (( BDC_DIV_TRAIN_STATE )) \n")); + } + pDM_BdcTable->pre_num_Client=pDM_BdcTable->num_Client; + + if( pDM_BdcTable->BDC_Try_flag==0) + { + //2 DIV_TRAIN_STATE (Mode 2-0) + if(pDM_BdcTable->BDC_state==BDC_DIV_TRAIN_STATE) + { + odm_DivTrainState_setting( pDM_Odm); + } + //2 BFer_TRAIN_STATE (Mode 2-1) + else if(pDM_BdcTable->BDC_state==BDC_BFer_TRAIN_STATE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-1. BFer_TRAIN_STATE ]***** \n")); + + //if(pDM_BdcTable->num_BfTar==0) + //{ + // ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( No )), [ BDC_BFer_TRAIN_STATE ] >> [BDC_DIV_TRAIN_STATE] \n")); + // odm_DivTrainState_setting( pDM_Odm); + //} + //else //num_BfTar != 0 + //{ + pDM_BdcTable->BDC_Try_counter=2; + pDM_BdcTable->BDC_Try_flag=1; + pDM_BdcTable->BDC_state=BDC_DECISION_STATE; + odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( Yes )), [ BDC_BFer_TRAIN_STATE ] >> [BDC_DECISION_STATE] \n")); + //} + } + //2 DECISION_STATE (Mode 2-2) + else if(pDM_BdcTable->BDC_state==BDC_DECISION_STATE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-2. DECISION_STATE]***** \n")); + //if(pDM_BdcTable->num_BfTar==0) + //{ + // ODM_AntDiv_Printk(("BF_tars exist? : (( No )), [ DECISION_STATE ] >> [BDC_DIV_TRAIN_STATE] \n")); + // odm_DivTrainState_setting( pDM_Odm); + //} + //else //num_BfTar != 0 + //{ + if(pDM_BdcTable->BF_pass==FALSE || pDM_BdcTable->DIV_pass == FALSE) + StopBF_flag=TRUE; + else + StopBF_flag=FALSE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( Yes )), {BF_pass, DIV_pass, StopBF_flag } = { %d, %d, %d } \n" ,pDM_BdcTable->BF_pass,pDM_BdcTable->DIV_pass,StopBF_flag)); + + if(StopBF_flag==TRUE) //DIV_en + { + pDM_BdcTable->BDC_Hold_counter=10; //20 + odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); + pDM_BdcTable->BDC_state=BDC_DIV_HOLD_STATE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ StopBF_flag= ((TRUE)), BDC_DECISION_STATE ] >> [BDC_DIV_HOLD_STATE] \n")); + } + else //BF_en + { + pDM_BdcTable->BDC_Hold_counter=10; //20 + odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); + pDM_BdcTable->BDC_state=BDC_BF_HOLD_STATE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[StopBF_flag= ((FALSE)), BDC_DECISION_STATE ] >> [BDC_BF_HOLD_STATE] \n")); + } + //} + } + //2 BF-HOLD_STATE (Mode 2-3) + else if(pDM_BdcTable->BDC_state==BDC_BF_HOLD_STATE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-3. BF_HOLD_STATE ]*****\n")); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BDC_Hold_counter = (( %d )) \n",pDM_BdcTable->BDC_Hold_counter )); + + if(pDM_BdcTable->BDC_Hold_counter==1) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE] \n")); + odm_DivTrainState_setting( pDM_Odm); + } + else + { + pDM_BdcTable->BDC_Hold_counter--; + + //if(pDM_BdcTable->num_BfTar==0) + //{ + // ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( No )), [ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE] \n")); + // odm_DivTrainState_setting( pDM_Odm); + //} + //else //num_BfTar != 0 + //{ + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( Yes ))\n")); + pDM_BdcTable->BDC_state=BDC_BF_HOLD_STATE; + odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_BF_HOLD_STATE ] >> [BDC_BF_HOLD_STATE] \n")); + //} + } + + } + //2 DIV-HOLD_STATE (Mode 2-4) + else if(pDM_BdcTable->BDC_state==BDC_DIV_HOLD_STATE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-4. DIV_HOLD_STATE ]*****\n")); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BDC_Hold_counter = (( %d )) \n",pDM_BdcTable->BDC_Hold_counter )); + + if(pDM_BdcTable->BDC_Hold_counter==1) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE] \n")); + odm_DivTrainState_setting( pDM_Odm); + } + else + { + pDM_BdcTable->BDC_Hold_counter--; + pDM_BdcTable->BDC_state=BDC_DIV_HOLD_STATE; + odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_HOLD_STATE] \n")); + } + + } + + } + else if( pDM_BdcTable->BDC_Try_flag==1) + { + //2 Set Training Counter + if(pDM_BdcTable->BDC_Try_counter >1) + { + pDM_BdcTable->BDC_Try_counter--; + if(pDM_BdcTable->BDC_Try_counter ==1) + pDM_BdcTable->BDC_Try_flag=0; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training !!\n")); + //return ; + } + + } + + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n[end]\n")); + + #endif //#if(DM_ODM_SUPPORT_TYPE == ODM_AP) + + + + + + +} + +#endif +#endif //#ifdef BEAMFORMING_SUPPORT + + +#if (RTL8188E_SUPPORT == 1) + + +VOID +odm_RX_HWAntDiv_Init_88E( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte value32; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + + if(pDM_Odm->mp_mode == TRUE) + { + ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv + ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); // 1:CG, 0:CS + return; + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => AntDivType=[CGCS_RX_HW_ANTDIV]\n")); + + //MAC Setting + value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); + ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output + //Pin Settings + ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW + ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 1); //Regb2c[22]=1'b0 //disable CS/CG switch + ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only + //OFDM Settings + ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0); + //CCK Settings + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples + + ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , 0xFFFF, 0x0001); //antenna mapping table + + pDM_FatTable->enable_ctrl_frame_antdiv = 1; +} + +VOID +odm_TRX_HWAntDiv_Init_88E( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte value32; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + if(pDM_Odm->mp_mode == TRUE) + { + ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); //Default RX (0/1) + return; + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => AntDivType=[CG_TRX_HW_ANTDIV (SPDT)]\n")); + + //MAC Setting + value32 = ODM_GetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord); + ODM_SetMACReg(pDM_Odm, ODM_REG_ANTSEL_PIN_11N, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output + //Pin Settings + ODM_SetBBReg(pDM_Odm, ODM_REG_PIN_CTRL_11N , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW + ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch + ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only + //OFDM Settings + ODM_SetBBReg(pDM_Odm, ODM_REG_ANTDIV_PARA1_11N , bMaskDWord, 0x000000a0); + //CCK Settings + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_PWR_SAV4_11N , BIT7, 1); //Fix CCK PHY status report issue + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_ANTDIV_PARA2_11N , BIT4, 1); //CCK complete HW AntDiv within 64 samples + + //antenna mapping table + if(!pDM_Odm->bIsMPChip) //testchip + { + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001 + ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010 + } + else //MPchip + ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , bMaskDWord, 0x0201); /*Reg914=3'b010, Reg915=3'b001*/ + + pDM_FatTable->enable_ctrl_frame_antdiv = 1; +} + + +#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) +VOID +odm_Smart_HWAntDiv_Init_88E( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte value32, i; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => AntDivType=[CG_TRX_SMART_ANTDIV]\n")); + + if(pDM_Odm->mp_mode == TRUE) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("pDM_Odm->AntDivType: %d\n", pDM_Odm->AntDivType)); + return; + } + + pDM_FatTable->TrainIdx = 0; + pDM_FatTable->FAT_State = FAT_PREPARE_STATE; + + pDM_Odm->fat_comb_a=5; + pDM_Odm->antdiv_intvl = 0x64; // 100ms + + for(i=0; i<6; i++) + { + pDM_FatTable->Bssid[i] = 0; + } + for(i=0; i< (pDM_Odm->fat_comb_a) ; i++) + { + pDM_FatTable->antSumRSSI[i] = 0; + pDM_FatTable->antRSSIcnt[i] = 0; + pDM_FatTable->antAveRSSI[i] = 0; + } + + //MAC Setting + value32 = ODM_GetMACReg(pDM_Odm, 0x4c, bMaskDWord); + ODM_SetMACReg(pDM_Odm, 0x4c, bMaskDWord, value32|(BIT23|BIT25)); //Reg4C[25]=1, Reg4C[23]=1 for pin output + value32 = ODM_GetMACReg(pDM_Odm, 0x7B4, bMaskDWord); + ODM_SetMACReg(pDM_Odm, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); //Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match + //value32 = PlatformEFIORead4Byte(Adapter, 0x7B4); + //PlatformEFIOWrite4Byte(Adapter, 0x7b4, value32|BIT18); //append MACID in reponse packet + + //Match MAC ADDR + ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, 0); + ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, 0); + + ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW + ODM_SetBBReg(pDM_Odm, 0x864 , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW + ODM_SetBBReg(pDM_Odm, 0xb2c , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch + ODM_SetBBReg(pDM_Odm, 0xb2c , BIT31, 0); //Regb2c[31]=1'b1 //output at CS only + ODM_SetBBReg(pDM_Odm, 0xca4 , bMaskDWord, 0x000000a0); + + //antenna mapping table + if(pDM_Odm->fat_comb_a == 2) + { + if(!pDM_Odm->bIsMPChip) //testchip + { + ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 1); //Reg858[10:8]=3'b001 + ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010 + } + else //MPchip + { + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 1); + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 2); + } + } + else + { + if(!pDM_Odm->bIsMPChip) //testchip + { + ODM_SetBBReg(pDM_Odm, 0x858 , BIT10|BIT9|BIT8, 0); //Reg858[10:8]=3'b000 + ODM_SetBBReg(pDM_Odm, 0x858 , BIT13|BIT12|BIT11, 1); //Reg858[13:11]=3'b001 + ODM_SetBBReg(pDM_Odm, 0x878 , BIT16, 0); + ODM_SetBBReg(pDM_Odm, 0x858 , BIT15|BIT14, 2); //(Reg878[0],Reg858[14:15])=3'b010 + ODM_SetBBReg(pDM_Odm, 0x878 , BIT19|BIT18|BIT17, 3);//Reg878[3:1]=3b'011 + ODM_SetBBReg(pDM_Odm, 0x878 , BIT22|BIT21|BIT20, 4);//Reg878[6:4]=3b'100 + ODM_SetBBReg(pDM_Odm, 0x878 , BIT25|BIT24|BIT23, 5);//Reg878[9:7]=3b'101 + ODM_SetBBReg(pDM_Odm, 0x878 , BIT28|BIT27|BIT26, 6);//Reg878[12:10]=3b'110 + ODM_SetBBReg(pDM_Odm, 0x878 , BIT31|BIT30|BIT29, 7);//Reg878[15:13]=3b'111 + } + else //MPchip + { + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 4); // 0: 3b'000 + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 2); // 1: 3b'001 + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte2, 0); // 2: 3b'010 + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte3, 1); // 3: 3b'011 + ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte0, 3); // 4: 3b'100 + ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte1, 5); // 5: 3b'101 + ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte2, 6); // 6: 3b'110 + ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte3, 255); // 7: 3b'111 + } + } + + //Default Ant Setting when no fast training + ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, 0); //Default RX + ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, 1); //Optional RX + ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, 0);//Default TX + + //Enter Traing state + ODM_SetBBReg(pDM_Odm, 0x864 , BIT2|BIT1|BIT0, (pDM_Odm->fat_comb_a-1)); //Reg864[2:0]=3'd6 //ant combination=reg864[2:0]+1 + + //SW Control + //PHY_SetBBReg(Adapter, 0x864 , BIT10, 1); + //PHY_SetBBReg(Adapter, 0x870 , BIT9, 1); + //PHY_SetBBReg(Adapter, 0x870 , BIT8, 1); + //PHY_SetBBReg(Adapter, 0x864 , BIT11, 1); + //PHY_SetBBReg(Adapter, 0x860 , BIT9, 0); + //PHY_SetBBReg(Adapter, 0x860 , BIT8, 0); +} +#endif + +#endif //#if (RTL8188E_SUPPORT == 1) + + +#if (RTL8192E_SUPPORT == 1) +VOID +odm_RX_HWAntDiv_Init_92E( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + if(pDM_Odm->mp_mode == TRUE) + { + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 0); //r_rxdiv_enable_anta Regc50[8]=1'b0 0: control by c50[9] + ODM_SetBBReg(pDM_Odm, 0xc50 , BIT9, 1); // 1:CG, 0:CS + return; + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => AntDivType=[CGCS_RX_HW_ANTDIV]\n")); + + //Pin Settings + ODM_SetBBReg(pDM_Odm, 0x870 , BIT8, 0);//Reg870[8]=1'b0, // "antsel" is controled by HWs + ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 1); //Regc50[8]=1'b1 //" CS/CG switching" is controled by HWs + + //Mapping table + ODM_SetBBReg(pDM_Odm, 0x914 , 0xFFFF, 0x0100); //antenna mapping table + + //OFDM Settings + ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF, 0xA0); //thershold + ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF000, 0x0); //bias + + //CCK Settings + ODM_SetBBReg(pDM_Odm, 0xa04 , 0xF000000, 0); //Select which path to receive for CCK_1 & CCK_2 + ODM_SetBBReg(pDM_Odm, 0xb34 , BIT30, 0); //(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 + ODM_SetBBReg(pDM_Odm, 0xa74 , BIT7, 1); //Fix CCK PHY status report issue + ODM_SetBBReg(pDM_Odm, 0xa0c , BIT4, 1); //CCK complete HW AntDiv within 64 samples + + #ifdef ODM_EVM_ENHANCE_ANTDIV + //EVM enhance AntDiv method init---------------------------------------------------------------------- + pDM_FatTable->EVM_method_enable=0; + pDM_FatTable->FAT_State = NORMAL_STATE_MIAN; + pDM_Odm->antdiv_intvl = 0x64; + ODM_SetBBReg(pDM_Odm, 0x910 , 0x3f, 0xf ); + pDM_Odm->antdiv_evm_en=1; + //pDM_Odm->antdiv_period=1; + + #endif + +} + +VOID +odm_TRX_HWAntDiv_Init_92E( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + if(pDM_Odm->mp_mode == TRUE) + { + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 0); //r_rxdiv_enable_anta Regc50[8]=1'b0 0: control by c50[9] + ODM_SetBBReg(pDM_Odm, 0xc50 , BIT9, 1); // 1:CG, 0:CS + return; + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => AntDivType=[ Only for DIR605, CG_TRX_HW_ANTDIV]\n")); + + //3 --RFE pin setting--------- + //[MAC] + ODM_SetMACReg(pDM_Odm, 0x38, BIT11, 1); //DBG PAD Driving control (GPIO 8) + ODM_SetMACReg(pDM_Odm, 0x4c, BIT23, 0); //path-A , RFE_CTRL_3 + ODM_SetMACReg(pDM_Odm, 0x4c, BIT29, 1); //path-A , RFE_CTRL_8 + //[BB] + ODM_SetBBReg(pDM_Odm, 0x944 , BIT3, 1); //RFE_buffer + ODM_SetBBReg(pDM_Odm, 0x944 , BIT8, 1); + ODM_SetBBReg(pDM_Odm, 0x940 , BIT7|BIT6, 0x0); // r_rfe_path_sel_ (RFE_CTRL_3) + ODM_SetBBReg(pDM_Odm, 0x940 , BIT17|BIT16, 0x0); // r_rfe_path_sel_ (RFE_CTRL_8) + ODM_SetBBReg(pDM_Odm, 0x944 , BIT31, 0); //RFE_buffer + ODM_SetBBReg(pDM_Odm, 0x92C , BIT3, 0); //rfe_inv (RFE_CTRL_3) + ODM_SetBBReg(pDM_Odm, 0x92C , BIT8, 1); //rfe_inv (RFE_CTRL_8) + ODM_SetBBReg(pDM_Odm, 0x930 , 0xF000, 0x8); //path-A , RFE_CTRL_3 + ODM_SetBBReg(pDM_Odm, 0x934 , 0xF, 0x8); //path-A , RFE_CTRL_8 + //3 ------------------------- + + //Pin Settings + ODM_SetBBReg(pDM_Odm, 0xC50 , BIT8, 0); //path-A //disable CS/CG switch + +/* Let it follows PHY_REG for bit9 setting + if(pDM_Odm->priv->pshare->rf_ft_var.use_ext_pa || pDM_Odm->priv->pshare->rf_ft_var.use_ext_lna) + ODM_SetBBReg(pDM_Odm, 0xC50 , BIT9, 1);//path-A //output at CS + else + ODM_SetBBReg(pDM_Odm, 0xC50 , BIT9, 0); //path-A //output at CG ->normal power +*/ + + ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0); //path-A //antsel antselb by HW + ODM_SetBBReg(pDM_Odm, 0xB38 , BIT10, 0); //path-A //antsel2 by HW + + //Mapping table + ODM_SetBBReg(pDM_Odm, 0x914 , 0xFFFF, 0x0100); //antenna mapping table + + //OFDM Settings + ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF, 0xA0); //thershold + ODM_SetBBReg(pDM_Odm, 0xca4 , 0x7FF000, 0x0); //bias + + //CCK Settings + ODM_SetBBReg(pDM_Odm, 0xa04 , 0xF000000, 0); //Select which path to receive for CCK_1 & CCK_2 + ODM_SetBBReg(pDM_Odm, 0xb34 , BIT30, 0); //(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 + ODM_SetBBReg(pDM_Odm, 0xa74 , BIT7, 1); //Fix CCK PHY status report issue + ODM_SetBBReg(pDM_Odm, 0xa0c , BIT4, 1); //CCK complete HW AntDiv within 64 samples + + //Timming issue + ODM_SetBBReg(pDM_Odm, 0xE20 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec) + + #ifdef ODM_EVM_ENHANCE_ANTDIV + //EVM enhance AntDiv method init---------------------------------------------------------------------- + pDM_FatTable->EVM_method_enable=0; + pDM_FatTable->FAT_State = NORMAL_STATE_MIAN; + pDM_Odm->antdiv_intvl = 0x64; + ODM_SetBBReg(pDM_Odm, 0x910 , 0x3f, 0xf ); + pDM_Odm->antdiv_evm_en=1; + //pDM_Odm->antdiv_period=1; + #endif +} + +#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) +VOID +odm_Smart_HWAntDiv_Init_92E( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => AntDivType=[CG_TRX_SMART_ANTDIV]\n")); +} +#endif + +#endif //#if (RTL8192E_SUPPORT == 1) + + +#if (RTL8723B_SUPPORT == 1) +VOID +odm_TRX_HWAntDiv_Init_8723B( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8723B AntDiv_Init => AntDivType=[CG_TRX_HW_ANTDIV(DPDT)]\n")); + + //Mapping Table + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0); + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1); + + //OFDM HW AntDiv Parameters + ODM_SetBBReg(pDM_Odm, 0xCA4 , 0x7FF, 0xa0); //thershold + ODM_SetBBReg(pDM_Odm, 0xCA4 , 0x7FF000, 0x00); //bias + + //CCK HW AntDiv Parameters + ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M + ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples + + //BT Coexistence + ODM_SetBBReg(pDM_Odm, 0x864, BIT12, 0); //keep antsel_map when GNT_BT = 1 + ODM_SetBBReg(pDM_Odm, 0x874 , BIT23, 0); //Disable hw antsw & fast_train.antsw when GNT_BT=1 + + //Output Pin Settings + ODM_SetBBReg(pDM_Odm, 0x870 , BIT8, 0); // + + ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0); //WL_BB_SEL_BTG_TRXG_anta, (1: HW CTRL 0: SW CTRL) + ODM_SetBBReg(pDM_Odm, 0x948 , BIT7, 0); + + ODM_SetMACReg(pDM_Odm, 0x40 , BIT3, 1); + ODM_SetMACReg(pDM_Odm, 0x38 , BIT11, 1); + ODM_SetMACReg(pDM_Odm, 0x4C , BIT24|BIT23, 2); //select DPDT_P and DPDT_N as output pin + + ODM_SetBBReg(pDM_Odm, 0x944 , BIT0|BIT1, 3); //in/out + ODM_SetBBReg(pDM_Odm, 0x944 , BIT31, 0); // + + ODM_SetBBReg(pDM_Odm, 0x92C , BIT1, 0); //DPDT_P non-inverse + ODM_SetBBReg(pDM_Odm, 0x92C , BIT0, 1); //DPDT_N inverse + + ODM_SetBBReg(pDM_Odm, 0x930 , 0xF0, 8); // DPDT_P = ANTSEL[0] + ODM_SetBBReg(pDM_Odm, 0x930 , 0xF, 8); // DPDT_N = ANTSEL[0] + + //Timming issue + ODM_SetBBReg(pDM_Odm, 0xE20 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec) + + //2 [--For HW Bug Setting] + if(pDM_Odm->AntType == ODM_AUTO_ANT) + ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function block enable + +} + + + +VOID +odm_S0S1_SWAntDiv_Init_8723B( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8723B AntDiv_Init => AntDivType=[ S0S1_SW_AntDiv] \n")); + + //Mapping Table + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0); + ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1); + + //Output Pin Settings + //ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0x1); + ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0); + + pDM_FatTable->bBecomeLinked =FALSE; + pDM_SWAT_Table->try_flag = SWAW_STEP_INIT; + pDM_SWAT_Table->Double_chk_flag = 0; + + //Timming issue + ODM_SetBBReg(pDM_Odm, 0xE20 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec) + + //2 [--For HW Bug Setting] + ODM_SetBBReg(pDM_Odm, 0x80C , BIT21, 0); //TX Ant by Reg + +} + +VOID +ODM_UpdateRxIdleAnt_8723B( + IN PVOID pDM_VOID, + IN u1Byte Ant, + IN u4Byte DefaultAnt, + IN u4Byte OptionalAnt +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + PADAPTER pAdapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + u1Byte count=0; + u1Byte u1Temp; + u1Byte H2C_Parameter; + + if(!pDM_Odm->bLinked) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Fail to set RX antenna due to no link\n")); + return; + } + +#if 0 + // Send H2C command to FW + // Enable wifi calibration + H2C_Parameter = TRUE; + ODM_FillH2CCmd(pDM_Odm, ODM_H2C_WIFI_CALIBRATION, 1, &H2C_Parameter); + + // Check if H2C command sucess or not (0x1e6) + u1Temp = ODM_Read1Byte(pDM_Odm, 0x1e6); + while((u1Temp != 0x1) && (count < 100)) + { + ODM_delay_us(10); + u1Temp = ODM_Read1Byte(pDM_Odm, 0x1e6); + count++; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: H2C command status = %d, count = %d\n", u1Temp, count)); + + if(u1Temp == 0x1) + { + // Check if BT is doing IQK (0x1e7) + count = 0; + u1Temp = ODM_Read1Byte(pDM_Odm, 0x1e7); + while((!(u1Temp & BIT0)) && (count < 100)) + { + ODM_delay_us(50); + u1Temp = ODM_Read1Byte(pDM_Odm, 0x1e7); + count++; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: BT IQK status = %d, count = %d\n", u1Temp, count)); + + if(u1Temp & BIT0) + { + ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0x1); + ODM_SetBBReg(pDM_Odm, 0x948 , BIT9, DefaultAnt); + ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, DefaultAnt); //Default RX + ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, OptionalAnt); //Optional RX + ODM_SetBBReg(pDM_Odm, 0x860, BIT14|BIT13|BIT12, DefaultAnt); //Default TX + pDM_FatTable->RxIdleAnt = Ant; + + // Set TX AGC by S0/S1 + // Need to consider Linux driver +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + pAdapter->HalFunc.SetTxPowerLevelHandler(pAdapter, pHalData->CurrentChannel); +#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) + rtw_hal_set_tx_power_level(pAdapter, pHalData->CurrentChannel); +#endif + + // Set IQC by S0/S1 + ODM_SetIQCbyRFpath(pDM_Odm,DefaultAnt); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Sucess to set RX antenna\n")); + } + else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Fail to set RX antenna due to BT IQK\n")); + } + else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Fail to set RX antenna due to H2C command fail\n")); + + // Send H2C command to FW + // Disable wifi calibration + H2C_Parameter = FALSE; + ODM_FillH2CCmd(pDM_Odm, ODM_H2C_WIFI_CALIBRATION, 1, &H2C_Parameter); +#else + + ODM_SetBBReg(pDM_Odm, 0x948 , BIT6, 0x1); + ODM_SetBBReg(pDM_Odm, 0x948 , BIT9, DefaultAnt); + ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, DefaultAnt); /*Default RX*/ + ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, OptionalAnt); /*Optional RX*/ + ODM_SetBBReg(pDM_Odm, 0x860, BIT14|BIT13|BIT12, DefaultAnt); /*Default TX*/ + pDM_FatTable->RxIdleAnt = Ant; + + /* Set TX AGC by S0/S1 */ + /* Need to consider Linux driver */ + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + pAdapter->HalFunc.SetTxPowerLevelHandler(pAdapter, pHalData->CurrentChannel); + #elif(DM_ODM_SUPPORT_TYPE == ODM_CE) + rtw_hal_set_tx_power_level(pAdapter, pHalData->CurrentChannel); + #endif + + /* Set IQC by S0/S1 */ + ODM_SetIQCbyRFpath(pDM_Odm, DefaultAnt); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Success to set RX antenna\n")); + +#endif +} + +BOOLEAN +phydm_IsBtEnable_8723b( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte bt_state; + /*u4Byte reg75;*/ + + /*reg75 = ODM_GetBBReg(pDM_Odm, 0x74 , BIT8);*/ + /*ODM_SetBBReg(pDM_Odm, 0x74 , BIT8, 0x0);*/ + ODM_SetBBReg(pDM_Odm, 0xa0 , BIT24|BIT25|BIT26, 0x5); + bt_state = ODM_GetBBReg(pDM_Odm, 0xa0 , (BIT3|BIT2|BIT1|BIT0)); + /*ODM_SetBBReg(pDM_Odm, 0x74 , BIT8, reg75);*/ + + if ((bt_state == 4) || (bt_state == 7) || (bt_state == 9) || (bt_state == 13)) + return TRUE; + else + return FALSE; +} +#endif //#if (RTL8723B_SUPPORT == 1) + +#if (RTL8821A_SUPPORT == 1) +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 +VOID +phydm_hl_smart_ant_type1_init_8821a( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + u4Byte value32; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A SmartAnt_Init => AntDivType=[Hong-Lin Smart Ant Type1]\n")); + + /*---------------------------------------- + GPIO 2-3 for Beam control + reg0x66[2]=0 + reg0x44[27:26] = 0 + reg0x44[23:16] //enable_output for P_GPIO[7:0] + reg0x44[15:8] //output_value for P_GPIO[7:0] + reg0x40[1:0] = 0 //GPIO function + ------------------------------------------*/ + + /*GPIO Setting*/ + ODM_SetMACReg(pDM_Odm, 0x64 , BIT18, 0); + ODM_SetMACReg(pDM_Odm, 0x44 , BIT27|BIT26, 0); + ODM_SetMACReg(pDM_Odm, 0x44 , BIT19|BIT18, 0x3); /*enable_output for P_GPIO[3:2]*/ + /*ODM_SetMACReg(pDM_Odm, 0x44 , BIT11|BIT10, 0);*/ /*output value*/ + ODM_SetMACReg(pDM_Odm, 0x40 , BIT1|BIT0, 0); /*GPIO function*/ + + /*Hong_lin smart antenna HW Setting*/ + pdm_sat_table->data_codeword_bit_num = 24;/*max=32*/ + pdm_sat_table->beam_patten_num_each_ant = 4; + + #if DEV_BUS_TYPE == RT_SDIO_INTERFACE + pdm_sat_table->latch_time = 100; /*mu sec*/ + #elif DEV_BUS_TYPE == RT_USB_INTERFACE + pdm_sat_table->latch_time = 100; /*mu sec*/ + #endif + pdm_sat_table->pkt_skip_statistic_en = 0; + + pdm_sat_table->ant_num = 2;/*max=8*/ + + pdm_sat_table->fix_beam_pattern_en = 0; + pdm_sat_table->decision_holding_period = 0; + + /*beam training setting*/ + pdm_sat_table->pkt_counter = 0; + pdm_sat_table->per_beam_training_pkt_num = 10; + + /*set default beam*/ + pdm_sat_table->fast_training_beam_num = 0; + pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; + phydm_set_all_ant_same_beam_num(pDM_Odm); + + pDM_FatTable->FAT_State = FAT_BEFORE_LINK_STATE; + + /*[BB] FAT Setting*/ + ODM_SetBBReg(pDM_Odm, 0xc08 , BIT18|BIT17|BIT16, pdm_sat_table->ant_num); + ODM_SetBBReg(pDM_Odm, 0xc08 , BIT31, 0); /*increase ant num every FAT period 0:+1, 1+2*/ + ODM_SetBBReg(pDM_Odm, 0x8c4 , BIT2|BIT1, 1); /*change cca antenna timming threshold if no CCA occurred: 0:200ms / 1:100ms / 2:no use / 3: 300*/ + ODM_SetBBReg(pDM_Odm, 0x8c4 , BIT0, 1); /*FAT_watchdog_en*/ + + value32 = ODM_GetMACReg(pDM_Odm, 0x7B4, bMaskDWord); + ODM_SetMACReg(pDM_Odm, 0x7b4, bMaskDWord, value32|(BIT16|BIT17)); /*Reg7B4[16]=1 enable antenna training */ + /*Reg7B4[17]=1 enable match MAC Addr*/ + ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, 0);/*Match MAC ADDR*/ + ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, 0); + +} +#endif + +VOID +odm_TRX_HWAntDiv_Init_8821A( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (DPDT)] \n")); + + //Output Pin Settings + ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0); + + ODM_SetMACReg(pDM_Odm, 0x64 , BIT29, 1); //PAPE by WLAN control + ODM_SetMACReg(pDM_Odm, 0x64 , BIT28, 1); //LNAON by WLAN control + + ODM_SetBBReg(pDM_Odm, 0xCB0 , bMaskDWord, 0x77775745); + ODM_SetBBReg(pDM_Odm, 0xCB8 , BIT16, 0); + + ODM_SetMACReg(pDM_Odm, 0x4C , BIT23, 0); //select DPDT_P and DPDT_N as output pin + ODM_SetMACReg(pDM_Odm, 0x4C , BIT24, 1); //by WLAN control + ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF, 8); // DPDT_P = ANTSEL[0] + ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF0, 8); // DPDT_N = ANTSEL[0] + ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT29, 0); //DPDT_P non-inverse + ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT28, 1); //DPDT_N inverse + + //Mapping Table + ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0); + ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1); + + //OFDM HW AntDiv Parameters + ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold + ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x10); //bias + + //CCK HW AntDiv Parameters + ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M + ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples + + ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //ANTSEL_CCK sent to the smart_antenna circuit + ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function block enable + + //BT Coexistence + ODM_SetBBReg(pDM_Odm, 0xCAC , BIT9, 1); //keep antsel_map when GNT_BT = 1 + ODM_SetBBReg(pDM_Odm, 0x804 , BIT4, 1); //Disable hw antsw & fast_train.antsw when GNT_BT=1 + + //Timming issue + ODM_SetBBReg(pDM_Odm, 0x818 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec) + ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns + + //response TX ant by RX ant + ODM_SetMACReg(pDM_Odm, 0x668 , BIT3, 1); + +} + +VOID +odm_S0S1_SWAntDiv_Init_8821A( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A AntDiv_Init => AntDivType=[ S0S1_SW_AntDiv]\n")); + + //Output Pin Settings + ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0); + + ODM_SetMACReg(pDM_Odm, 0x64 , BIT29, 1); //PAPE by WLAN control + ODM_SetMACReg(pDM_Odm, 0x64 , BIT28, 1); //LNAON by WLAN control + + ODM_SetBBReg(pDM_Odm, 0xCB0 , bMaskDWord, 0x77775745); + ODM_SetBBReg(pDM_Odm, 0xCB8 , BIT16, 0); + + ODM_SetMACReg(pDM_Odm, 0x4C , BIT23, 0); //select DPDT_P and DPDT_N as output pin + ODM_SetMACReg(pDM_Odm, 0x4C , BIT24, 1); //by WLAN control + ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF, 8); // DPDT_P = ANTSEL[0] + ODM_SetBBReg(pDM_Odm, 0xCB4 , 0xF0, 8); // DPDT_N = ANTSEL[0] + ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT29, 0); //DPDT_P non-inverse + ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT28, 1); //DPDT_N inverse + + //Mapping Table + ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0); + ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1); + + //OFDM HW AntDiv Parameters + ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold + ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x10); //bias + + //CCK HW AntDiv Parameters + ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M + ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples + + ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //ANTSEL_CCK sent to the smart_antenna circuit + ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function block enable + + //BT Coexistence + ODM_SetBBReg(pDM_Odm, 0xCAC , BIT9, 1); //keep antsel_map when GNT_BT = 1 + ODM_SetBBReg(pDM_Odm, 0x804 , BIT4, 1); //Disable hw antsw & fast_train.antsw when GNT_BT=1 + + //Timming issue + ODM_SetBBReg(pDM_Odm, 0x818 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec) + ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns + + //response TX ant by RX ant + ODM_SetMACReg(pDM_Odm, 0x668 , BIT3, 1); + + + ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); + + pDM_SWAT_Table->try_flag = SWAW_STEP_INIT; + pDM_SWAT_Table->Double_chk_flag = 0; + pDM_SWAT_Table->CurAntenna = MAIN_ANT; + pDM_SWAT_Table->PreAntenna = MAIN_ANT; + pDM_SWAT_Table->SWAS_NoLink_State = 0; + +} +#endif //#if (RTL8821A_SUPPORT == 1) + +#if (RTL8881A_SUPPORT == 1) +VOID +odm_RX_HWAntDiv_Init_8881A( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8881A AntDiv_Init => AntDivType=[ CGCS_RX_HW_ANTDIV] \n")); + +} + +VOID +odm_TRX_HWAntDiv_Init_8881A( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8881A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (SPDT)] \n")); + + //Output Pin Settings + // [SPDT related] + ODM_SetMACReg(pDM_Odm, 0x4C , BIT25, 0); + ODM_SetMACReg(pDM_Odm, 0x4C , BIT26, 0); + ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT31, 0); //delay buffer + ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT22, 0); + ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT24, 1); + ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF00, 8); // DPDT_P = ANTSEL[0] + ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF0000, 8); // DPDT_N = ANTSEL[0] + + //Mapping Table + ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0); + ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1); + + //OFDM HW AntDiv Parameters + ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold + ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x0); //bias + ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns + + //CCK HW AntDiv Parameters + ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M + ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples + + //Timming issue + ODM_SetBBReg(pDM_Odm, 0x818 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec) + + //2 [--For HW Bug Setting] + + ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); //TX Ant by Reg // A-cut bug +} + +#endif //#if (RTL8881A_SUPPORT == 1) + + +#if (RTL8812A_SUPPORT == 1) +VOID +odm_TRX_HWAntDiv_Init_8812A( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8812A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (SPDT)] \n")); + + //3 //3 --RFE pin setting--------- + //[BB] + ODM_SetBBReg(pDM_Odm, 0x900 , BIT10|BIT9|BIT8, 0x0); //disable SW switch + ODM_SetBBReg(pDM_Odm, 0x900 , BIT17|BIT16, 0x0); + ODM_SetBBReg(pDM_Odm, 0x974 , BIT7|BIT6, 0x3); // in/out + ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT31, 0); //delay buffer + ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT26, 0); + ODM_SetBBReg(pDM_Odm, 0xCB4 , BIT27, 1); + ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF000000, 8); // DPDT_P = ANTSEL[0] + ODM_SetBBReg(pDM_Odm, 0xCB0 , 0xF0000000, 8); // DPDT_N = ANTSEL[0] + //3 ------------------------- + + //Mapping Table + ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0); + ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1); + + //OFDM HW AntDiv Parameters + ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold + ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x0); //bias + ODM_SetBBReg(pDM_Odm, 0x8CC , BIT20|BIT19|BIT18, 3); //settling time of antdiv by RF LNA = 100ns + + //CCK HW AntDiv Parameters + ODM_SetBBReg(pDM_Odm, 0xA74 , BIT7, 1); //patch for clk from 88M to 80M + ODM_SetBBReg(pDM_Odm, 0xA0C , BIT4, 1); //do 64 samples + + //Timming issue + ODM_SetBBReg(pDM_Odm, 0x818 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec) + + //2 [--For HW Bug Setting] + + ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); //TX Ant by Reg // A-cut bug + +} + +#endif //#if (RTL8812A_SUPPORT == 1) + +#if (RTL8188F_SUPPORT == 1) +VOID +odm_S0S1_SWAntDiv_Init_8188F( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188F AntDiv_Init => AntDivType=[ S0S1_SW_AntDiv]\n")); + + + /*GPIO Setting*/ + /*ODM_SetMACReg(pDM_Odm, 0x64 , BIT18, 0); */ + /*ODM_SetMACReg(pDM_Odm, 0x44 , BIT28|BIT27, 0);*/ + ODM_SetMACReg(pDM_Odm, 0x44 , BIT20|BIT19, 0x3); /*enable_output for P_GPIO[4:3]*/ + /*ODM_SetMACReg(pDM_Odm, 0x44 , BIT12|BIT11, 0);*/ /*output value*/ + /*ODM_SetMACReg(pDM_Odm, 0x40 , BIT1|BIT0, 0);*/ /*GPIO function*/ + + pDM_FatTable->bBecomeLinked = FALSE; + pDM_SWAT_Table->try_flag = SWAW_STEP_INIT; + pDM_SWAT_Table->Double_chk_flag = 0; +} + +VOID +phydm_update_rx_idle_antenna_8188F( + IN PVOID pDM_VOID, + IN u4Byte default_ant +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte codeword; + + if (default_ant == ANT1_2G) + codeword = 1; /*2'b01*/ + else + codeword = 2;/*2'b10*/ + + ODM_SetMACReg(pDM_Odm, 0x44 , (BIT12|BIT11), codeword); /*GPIO[4:3] output value*/ +} + +#endif + + + +#ifdef ODM_EVM_ENHANCE_ANTDIV + +VOID +odm_EVM_FastAnt_Reset( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + pDM_FatTable->EVM_method_enable=0; + odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); + pDM_FatTable->FAT_State = NORMAL_STATE_MIAN; + pDM_Odm->antdiv_period=0; + ODM_SetMACReg(pDM_Odm, 0x608, BIT8, 0); +} + + +VOID +odm_EVM_Enhance_AntDiv( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte Main_RSSI, Aux_RSSI ; + u4Byte Main_CRC_utility=0,Aux_CRC_utility=0,utility_ratio=1; + u4Byte Main_EVM, Aux_EVM,Diff_RSSI=0,diff_EVM=0; + u1Byte score_EVM=0,score_CRC=0; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + u4Byte value32, i; + BOOLEAN Main_above1=FALSE,Aux_above1=FALSE; + BOOLEAN Force_antenna=FALSE; + PSTA_INFO_T pEntry; + pDM_FatTable->TargetAnt_enhance=0xFF; + + + if((pDM_Odm->SupportICType & ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC)) + { + if(pDM_Odm->bOneEntryOnly) + { + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[One Client only] \n")); + i = pDM_Odm->OneEntry_MACID; + + Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0; + Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0; + + if((Main_RSSI==0 && Aux_RSSI !=0 && Aux_RSSI>=FORCE_RSSI_DIFF) || (Main_RSSI!=0 && Aux_RSSI==0 && Main_RSSI>=FORCE_RSSI_DIFF)) + { + Diff_RSSI=FORCE_RSSI_DIFF; + } + else if(Main_RSSI!=0 && Aux_RSSI !=0) + { + Diff_RSSI = (Main_RSSI>=Aux_RSSI)?(Main_RSSI-Aux_RSSI):(Aux_RSSI-Main_RSSI); + } + + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Main_Cnt = (( %d )) , Main_RSSI= (( %d )) \n", pDM_FatTable->MainAnt_Cnt[i], Main_RSSI)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Aux_Cnt = (( %d )) , Aux_RSSI = (( %d )) \n" , pDM_FatTable->AuxAnt_Cnt[i] , Aux_RSSI)); + + if( ((Main_RSSI>=Evm_RSSI_TH_High||Aux_RSSI>=Evm_RSSI_TH_High )|| (pDM_FatTable->EVM_method_enable==1) ) + //&& (Diff_RSSI <= FORCE_RSSI_DIFF + 1) + ) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[> TH_H || EVM_method_enable==1] && ")); + + if(((Main_RSSI>=Evm_RSSI_TH_Low)||(Aux_RSSI>=Evm_RSSI_TH_Low) )) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[> TH_L ] \n")); + + //2 [ Normal state Main] + if(pDM_FatTable->FAT_State == NORMAL_STATE_MIAN) + { + + pDM_FatTable->EVM_method_enable=1; + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + pDM_Odm->antdiv_period=3; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ start training: MIAN] \n")); + pDM_FatTable->MainAntEVM_Sum[i] = 0; + pDM_FatTable->AuxAntEVM_Sum[i] = 0; + pDM_FatTable->MainAntEVM_Cnt[i] = 0; + pDM_FatTable->AuxAntEVM_Cnt[i] = 0; + + pDM_FatTable->FAT_State = NORMAL_STATE_AUX; + ODM_SetMACReg(pDM_Odm, 0x608, BIT8, 1); //Accept CRC32 Error packets. + ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT); + + pDM_FatTable->CRC32_Ok_Cnt=0; + pDM_FatTable->CRC32_Fail_Cnt=0; + ODM_SetTimer(pDM_Odm,&pDM_Odm->EVM_FastAntTrainingTimer, pDM_Odm->antdiv_intvl ); //m + } + //2 [ Normal state Aux ] + else if(pDM_FatTable->FAT_State == NORMAL_STATE_AUX) + { + pDM_FatTable->MainCRC32_Ok_Cnt=pDM_FatTable->CRC32_Ok_Cnt; + pDM_FatTable->MainCRC32_Fail_Cnt=pDM_FatTable->CRC32_Fail_Cnt; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ start training: AUX] \n")); + pDM_FatTable->FAT_State = TRAINING_STATE; + ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT); + + pDM_FatTable->CRC32_Ok_Cnt=0; + pDM_FatTable->CRC32_Fail_Cnt=0; + ODM_SetTimer(pDM_Odm,&pDM_Odm->EVM_FastAntTrainingTimer, pDM_Odm->antdiv_intvl ); //ms + } + else if(pDM_FatTable->FAT_State == TRAINING_STATE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Training state ] \n")); + pDM_FatTable->FAT_State = NORMAL_STATE_MIAN; + + //3 [CRC32 statistic] + pDM_FatTable->AuxCRC32_Ok_Cnt=pDM_FatTable->CRC32_Ok_Cnt; + pDM_FatTable->AuxCRC32_Fail_Cnt=pDM_FatTable->CRC32_Fail_Cnt; + + if( (pDM_FatTable->MainCRC32_Ok_Cnt >= ((pDM_FatTable->AuxCRC32_Ok_Cnt)<<1)) || (Diff_RSSI>=18)) + { + pDM_FatTable->TargetAnt_CRC32=MAIN_ANT; + Force_antenna=TRUE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("CRC32 Force Main \n")); + } + else if((pDM_FatTable->AuxCRC32_Ok_Cnt >= ((pDM_FatTable->MainCRC32_Ok_Cnt)<<1)) || (Diff_RSSI>=18)) + { + pDM_FatTable->TargetAnt_CRC32=AUX_ANT; + Force_antenna=TRUE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("CRC32 Force Aux \n")); + } + else + { + if(pDM_FatTable->MainCRC32_Fail_Cnt<=5) + pDM_FatTable->MainCRC32_Fail_Cnt=5; + + if(pDM_FatTable->AuxCRC32_Fail_Cnt<=5) + pDM_FatTable->AuxCRC32_Fail_Cnt=5; + + if(pDM_FatTable->MainCRC32_Ok_Cnt >pDM_FatTable->MainCRC32_Fail_Cnt ) + Main_above1=TRUE; + + if(pDM_FatTable->AuxCRC32_Ok_Cnt >pDM_FatTable->AuxCRC32_Fail_Cnt ) + Aux_above1=TRUE; + + if(Main_above1==TRUE && Aux_above1==FALSE) + { + Force_antenna=TRUE; + pDM_FatTable->TargetAnt_CRC32=MAIN_ANT; + } + else if(Main_above1==FALSE && Aux_above1==TRUE) + { + Force_antenna=TRUE; + pDM_FatTable->TargetAnt_CRC32=AUX_ANT; + } + else if(Main_above1==TRUE && Aux_above1==TRUE) + { + Main_CRC_utility=((pDM_FatTable->MainCRC32_Ok_Cnt)<<7)/pDM_FatTable->MainCRC32_Fail_Cnt; + Aux_CRC_utility=((pDM_FatTable->AuxCRC32_Ok_Cnt)<<7)/pDM_FatTable->AuxCRC32_Fail_Cnt; + pDM_FatTable->TargetAnt_CRC32 = (Main_CRC_utility==Aux_CRC_utility)?(pDM_FatTable->pre_TargetAnt_enhance):((Main_CRC_utility>=Aux_CRC_utility)?MAIN_ANT:AUX_ANT); + + if(Main_CRC_utility!=0 && Aux_CRC_utility!=0) + { + if(Main_CRC_utility>=Aux_CRC_utility) + utility_ratio=(Main_CRC_utility<<1)/Aux_CRC_utility; + else + utility_ratio=(Aux_CRC_utility<<1)/Main_CRC_utility; + } + } + else if(Main_above1==FALSE && Aux_above1==FALSE) + { + if(pDM_FatTable->MainCRC32_Ok_Cnt==0) + pDM_FatTable->MainCRC32_Ok_Cnt=1; + if(pDM_FatTable->AuxCRC32_Ok_Cnt==0) + pDM_FatTable->AuxCRC32_Ok_Cnt=1; + + Main_CRC_utility=((pDM_FatTable->MainCRC32_Fail_Cnt)<<7)/pDM_FatTable->MainCRC32_Ok_Cnt; + Aux_CRC_utility=((pDM_FatTable->AuxCRC32_Fail_Cnt)<<7)/pDM_FatTable->AuxCRC32_Ok_Cnt; + pDM_FatTable->TargetAnt_CRC32 = (Main_CRC_utility==Aux_CRC_utility)?(pDM_FatTable->pre_TargetAnt_enhance):((Main_CRC_utility<=Aux_CRC_utility)?MAIN_ANT:AUX_ANT); + + if(Main_CRC_utility!=0 && Aux_CRC_utility!=0) + { + if(Main_CRC_utility>=Aux_CRC_utility) + utility_ratio=(Main_CRC_utility<<1)/(Aux_CRC_utility); + else + utility_ratio=(Aux_CRC_utility<<1)/(Main_CRC_utility); + } + } + } + ODM_SetMACReg(pDM_Odm, 0x608, BIT8, 0);//NOT Accept CRC32 Error packets. + + //3 [EVM statistic] + Main_EVM = (pDM_FatTable->MainAntEVM_Cnt[i]!=0)?(pDM_FatTable->MainAntEVM_Sum[i]/pDM_FatTable->MainAntEVM_Cnt[i]):0; + Aux_EVM = (pDM_FatTable->AuxAntEVM_Cnt[i]!=0)?(pDM_FatTable->AuxAntEVM_Sum[i]/pDM_FatTable->AuxAntEVM_Cnt[i]):0; + pDM_FatTable->TargetAnt_EVM = (Main_EVM==Aux_EVM)?(pDM_FatTable->pre_TargetAnt_enhance):((Main_EVM>=Aux_EVM)?MAIN_ANT:AUX_ANT); + + if((Main_EVM==0 || Aux_EVM==0)) + diff_EVM=0; + else if(Main_EVM>=Aux_EVM) + diff_EVM=Main_EVM-Aux_EVM; + else + diff_EVM=Aux_EVM-Main_EVM; + + //2 [ Decision state ] + if(pDM_FatTable->TargetAnt_EVM ==pDM_FatTable->TargetAnt_CRC32 ) + { + if( (utility_ratio<2 && Force_antenna==FALSE) && diff_EVM<=2) + pDM_FatTable->TargetAnt_enhance=pDM_FatTable->pre_TargetAnt_enhance; + else + pDM_FatTable->TargetAnt_enhance=pDM_FatTable->TargetAnt_EVM; + } + else if(diff_EVM<=2 && (utility_ratio > 4 && Force_antenna==FALSE)) + { + pDM_FatTable->TargetAnt_enhance=pDM_FatTable->TargetAnt_CRC32; + } + else if(diff_EVM>=20) // + { + pDM_FatTable->TargetAnt_enhance=pDM_FatTable->TargetAnt_EVM; + } + else if(utility_ratio>=6 && Force_antenna==FALSE) // utility_ratio>3 + { + pDM_FatTable->TargetAnt_enhance=pDM_FatTable->TargetAnt_CRC32; + } + else + { + if(Force_antenna==TRUE) + score_CRC=3; + else if(utility_ratio>=4) //>2 + score_CRC=2; + else if(utility_ratio>=3) //>1.5 + score_CRC=1; + else + score_CRC=0; + + if(diff_EVM>=10) + score_EVM=2; + else if(diff_EVM>=5) + score_EVM=1; + else + score_EVM=0; + + if(score_CRC>score_EVM) + pDM_FatTable->TargetAnt_enhance=pDM_FatTable->TargetAnt_CRC32; + else if(score_CRCTargetAnt_enhance=pDM_FatTable->TargetAnt_EVM; + else + pDM_FatTable->TargetAnt_enhance=pDM_FatTable->pre_TargetAnt_enhance; + } + pDM_FatTable->pre_TargetAnt_enhance=pDM_FatTable->TargetAnt_enhance; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : MainEVM_Cnt = (( %d )) , Main_EVM= (( %d )) \n",i, pDM_FatTable->MainAntEVM_Cnt[i], Main_EVM)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : AuxEVM_Cnt = (( %d )) , Aux_EVM = (( %d )) \n" ,i, pDM_FatTable->AuxAntEVM_Cnt[i] , Aux_EVM)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** TargetAnt_EVM = (( %s ))\n", ( pDM_FatTable->TargetAnt_EVM ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("M_CRC_Ok = (( %d )) , M_CRC_Fail = (( %d )), Main_CRC_utility = (( %d )) \n" , pDM_FatTable->MainCRC32_Ok_Cnt, pDM_FatTable->MainCRC32_Fail_Cnt,Main_CRC_utility)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("A_CRC_Ok = (( %d )) , A_CRC_Fail = (( %d )), Aux_CRC_utility = (( %d )) \n" , pDM_FatTable->AuxCRC32_Ok_Cnt, pDM_FatTable->AuxCRC32_Fail_Cnt,Aux_CRC_utility)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** TargetAnt_CRC32 = (( %s ))\n", ( pDM_FatTable->TargetAnt_CRC32 ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("****** TargetAnt_enhance = (( %s ))******\n", ( pDM_FatTable->TargetAnt_enhance ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + + + } + } + else // RSSI< = Evm_RSSI_TH_Low + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ TH_L ] \n")); + odm_EVM_FastAnt_Reset(pDM_Odm); + } + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[escape from> TH_H || EVM_method_enable==1] \n")); + odm_EVM_FastAnt_Reset(pDM_Odm); + } + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[multi-Client] \n")); + odm_EVM_FastAnt_Reset(pDM_Odm); + } + } +} + +VOID +odm_EVM_FastAntTrainingCallback( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("******odm_EVM_FastAntTrainingCallback****** \n")); + odm_HW_AntDiv(pDM_Odm); +} +#endif + +VOID +odm_HW_AntDiv( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte i,MinMaxRSSI=0xFF, AntDivMaxRSSI=0, MaxRSSI=0, LocalMaxRSSI; + u4Byte Main_RSSI, Aux_RSSI; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + u1Byte RxIdleAnt = pDM_FatTable->RxIdleAnt, TargetAnt = 7; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + PSTA_INFO_T pEntry; + + #ifdef BEAMFORMING_SUPPORT + #if(DM_ODM_SUPPORT_TYPE == ODM_AP) + pBDC_T pDM_BdcTable = &pDM_Odm->DM_BdcTable; + u4Byte TH1=500000; + u4Byte TH2=10000000; + u4Byte MA_rx_Temp, degrade_TP_temp, improve_TP_temp; + u1Byte Monitor_RSSI_threshold=30; + + pDM_BdcTable->BF_pass=TRUE; + pDM_BdcTable->DIV_pass=TRUE; + pDM_BdcTable->bAll_DivSta_Idle=TRUE; + pDM_BdcTable->bAll_BFSta_Idle=TRUE; + pDM_BdcTable->num_BfTar=0 ; + pDM_BdcTable->num_DivTar=0; + pDM_BdcTable->num_Client=0; + #endif + #endif + + if(!pDM_Odm->bLinked) //bLinked==False + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); + + if(pDM_FatTable->bBecomeLinked == TRUE) + { + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT); + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); + pDM_Odm->antdiv_period=0; + + pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; + } + return; + } + else + { + if(pDM_FatTable->bBecomeLinked ==FALSE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n")); + odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); + + //if(pDM_Odm->SupportICType == ODM_RTL8821 ) + //ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function disable + + //#if(DM_ODM_SUPPORT_TYPE == ODM_AP) + //else if(pDM_Odm->SupportICType == ODM_RTL8881A) + // ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function disable + //#endif + + //else if(pDM_Odm->SupportICType == ODM_RTL8723B ||pDM_Odm->SupportICType == ODM_RTL8812) + //ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function disable + + pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; + + if(pDM_Odm->SupportICType==ODM_RTL8723B && pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) + { + ODM_SetBBReg(pDM_Odm, 0x930 , 0xF0, 8); // DPDT_P = ANTSEL[0] // for 8723B AntDiv function patch. BB Dino 130412 + ODM_SetBBReg(pDM_Odm, 0x930 , 0xF, 8); // DPDT_N = ANTSEL[0] + } + + //2 BDC Init + #ifdef BEAMFORMING_SUPPORT + #if(DM_ODM_SUPPORT_TYPE == ODM_AP) + odm_BDC_Init(pDM_Odm); + #endif + #endif + + #ifdef ODM_EVM_ENHANCE_ANTDIV + odm_EVM_FastAnt_Reset(pDM_Odm); + #endif + } + } + + if (pDM_Odm->bOneEntryOnly == TRUE) + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); + else + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_DESC); + + + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n AntDiv Start =>\n")); + + #ifdef ODM_EVM_ENHANCE_ANTDIV + if(pDM_Odm->antdiv_evm_en==1) + { + odm_EVM_Enhance_AntDiv(pDM_Odm); + if(pDM_FatTable->FAT_State !=NORMAL_STATE_MIAN) + return; + } + else + { + odm_EVM_FastAnt_Reset(pDM_Odm); + } + #endif + + //2 BDC Mode Arbitration + #ifdef BEAMFORMING_SUPPORT + #if(DM_ODM_SUPPORT_TYPE == ODM_AP) + if(pDM_Odm->antdiv_evm_en == 0 ||pDM_FatTable->EVM_method_enable==0) + { + odm_BF_AntDiv_ModeArbitration(pDM_Odm); + } + #endif + #endif + + for (i=0; ipODM_StaInfo[i]; + if(IS_STA_VALID(pEntry)) + { + //2 Caculate RSSI per Antenna + Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0; + Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0; + TargetAnt = (Main_RSSI==Aux_RSSI)?pDM_FatTable->RxIdleAnt:((Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT); + + //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("*** SupportICType=[%d] \n",pDM_Odm->SupportICType)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : Main_Cnt = (( %d )) , Main_RSSI= (( %d )) \n",i, pDM_FatTable->MainAnt_Cnt[i], Main_RSSI)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : Aux_Cnt = (( %d )) , Aux_RSSI = (( %d )) \n" ,i, pDM_FatTable->AuxAnt_Cnt[i] , Aux_RSSI)); + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** MAC ID:[ %d ] , TargetAnt = (( %s )) \n", i ,( TargetAnt ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("*** Phy_AntSel_A=[ %d, %d, %d] \n",((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT2)>>2, + // ((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT1) >>1, ((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT0))); + + LocalMaxRSSI = (Main_RSSI>Aux_RSSI)?Main_RSSI:Aux_RSSI; + //2 Select MaxRSSI for DIG + if((LocalMaxRSSI > AntDivMaxRSSI) && (LocalMaxRSSI < 40)) + AntDivMaxRSSI = LocalMaxRSSI; + if(LocalMaxRSSI > MaxRSSI) + MaxRSSI = LocalMaxRSSI; + + //2 Select RX Idle Antenna + if ( (LocalMaxRSSI != 0) && (LocalMaxRSSI < MinMaxRSSI) ) + { + RxIdleAnt = TargetAnt; + MinMaxRSSI = LocalMaxRSSI; + } + + #ifdef ODM_EVM_ENHANCE_ANTDIV + if(pDM_Odm->antdiv_evm_en==1) + { + if(pDM_FatTable->TargetAnt_enhance!=0xFF) + { + TargetAnt=pDM_FatTable->TargetAnt_enhance; + RxIdleAnt = pDM_FatTable->TargetAnt_enhance; + } + } + #endif + + //2 Select TX Antenna + if(pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV) + { + #ifdef BEAMFORMING_SUPPORT + #if(DM_ODM_SUPPORT_TYPE == ODM_AP) + if(pDM_BdcTable->w_BFee_Client[i]==0) + #endif + #endif + { + odm_UpdateTxAnt(pDM_Odm, TargetAnt, i); + } + } + + //------------------------------------------------------------ + + #ifdef BEAMFORMING_SUPPORT + #if(DM_ODM_SUPPORT_TYPE == ODM_AP) + + pDM_BdcTable->num_Client++; + + if(pDM_BdcTable->BDC_Mode==BDC_MODE_2 ||pDM_BdcTable->BDC_Mode==BDC_MODE_3) + { + //2 Byte Counter + + MA_rx_Temp= (pEntry->rx_byte_cnt_LowMAW)<<3 ; // RX TP ( bit /sec) + + if(pDM_BdcTable->BDC_state==BDC_BFer_TRAIN_STATE) + { + pDM_BdcTable->MA_rx_TP_DIV[i]= MA_rx_Temp ; + } + else + { + pDM_BdcTable->MA_rx_TP[i] =MA_rx_Temp ; + } + + if( (MA_rx_Temp < TH2) && (MA_rx_Temp > TH1) && (LocalMaxRSSI<=Monitor_RSSI_threshold)) + { + if(pDM_BdcTable->w_BFer_Client[i]==1) // Bfer_Target + { + pDM_BdcTable->num_BfTar++; + + if(pDM_BdcTable->BDC_state==BDC_DECISION_STATE && pDM_BdcTable->BDC_Try_flag==0) + { + improve_TP_temp = (pDM_BdcTable->MA_rx_TP_DIV[i] * 9)>>3 ; //* 1.125 + pDM_BdcTable->BF_pass = (pDM_BdcTable->MA_rx_TP[i] > improve_TP_temp)?TRUE:FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : { MA_rx_TP,improve_TP_temp , MA_rx_TP_DIV, BF_pass}={ %d, %d, %d , %d } \n" ,i,pDM_BdcTable->MA_rx_TP[i],improve_TP_temp,pDM_BdcTable->MA_rx_TP_DIV[i], pDM_BdcTable->BF_pass )); + } + } + else// DIV_Target + { + pDM_BdcTable->num_DivTar++; + + if(pDM_BdcTable->BDC_state==BDC_DECISION_STATE && pDM_BdcTable->BDC_Try_flag==0) + { + degrade_TP_temp=(pDM_BdcTable->MA_rx_TP_DIV[i]*5)>>3;//* 0.625 + pDM_BdcTable->DIV_pass = (pDM_BdcTable->MA_rx_TP[i] >degrade_TP_temp)?TRUE:FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : { MA_rx_TP, degrade_TP_temp , MA_rx_TP_DIV, DIV_pass}=\n{ %d, %d, %d , %d } \n" ,i,pDM_BdcTable->MA_rx_TP[i],degrade_TP_temp,pDM_BdcTable->MA_rx_TP_DIV[i], pDM_BdcTable->DIV_pass )); + } + } + } + + if(MA_rx_Temp > TH1) + { + if(pDM_BdcTable->w_BFer_Client[i]==1) // Bfer_Target + { + pDM_BdcTable->bAll_BFSta_Idle=FALSE; + } + else// DIV_Target + { + pDM_BdcTable->bAll_DivSta_Idle=FALSE; + } + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : { BFmeeCap , BFmerCap} = { %d , %d } \n" ,i, pDM_BdcTable->w_BFee_Client[i] , pDM_BdcTable->w_BFer_Client[i])); + + if(pDM_BdcTable->BDC_state==BDC_BFer_TRAIN_STATE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : MA_rx_TP_DIV = (( %d )) \n",i,pDM_BdcTable->MA_rx_TP_DIV[i] )); + + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : MA_rx_TP = (( %d )) \n",i,pDM_BdcTable->MA_rx_TP[i] )); + } + + } + #endif + #endif + + } + + #ifdef BEAMFORMING_SUPPORT + #if(DM_ODM_SUPPORT_TYPE == ODM_AP) + if(pDM_BdcTable->BDC_Try_flag==0) + #endif + #endif + { + pDM_FatTable->MainAnt_Sum[i] = 0; + pDM_FatTable->AuxAnt_Sum[i] = 0; + pDM_FatTable->MainAnt_Cnt[i] = 0; + pDM_FatTable->AuxAnt_Cnt[i] = 0; + } + } + + + + //2 Set RX Idle Antenna & TX Antenna(Because of HW Bug ) + #if(DM_ODM_SUPPORT_TYPE == ODM_AP ) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** RxIdleAnt = (( %s ))\n\n", ( RxIdleAnt ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + + #ifdef BEAMFORMING_SUPPORT + #if(DM_ODM_SUPPORT_TYPE == ODM_AP) + if(pDM_BdcTable->BDC_Mode==BDC_MODE_1 ||pDM_BdcTable->BDC_Mode==BDC_MODE_3) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** BDC_RxIdleUpdate_counter = (( %d ))\n", pDM_BdcTable->BDC_RxIdleUpdate_counter)); + + if(pDM_BdcTable->BDC_RxIdleUpdate_counter==1) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***Update RxIdle Antenna!!! \n")); + pDM_BdcTable->BDC_RxIdleUpdate_counter=30; + ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt); + } + else + { + pDM_BdcTable->BDC_RxIdleUpdate_counter--; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***NOT update RxIdle Antenna because of BF ( need to fix TX-ant)\n")); + } + } + else + #endif + #endif + ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt); + #else + + ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt); + + #endif//#if(DM_ODM_SUPPORT_TYPE == ODM_AP) + + + + //2 BDC Main Algorithm + #ifdef BEAMFORMING_SUPPORT + #if(DM_ODM_SUPPORT_TYPE == ODM_AP) + if(pDM_Odm->antdiv_evm_en ==0 ||pDM_FatTable->EVM_method_enable==0) + { + odm_BDCcoex_BFeeRxDiv_Arbitration(pDM_Odm); + } + #endif + #endif + + if(AntDivMaxRSSI == 0) + pDM_DigTable->AntDiv_RSSI_max = pDM_Odm->RSSI_Min; + else + pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI; + + pDM_DigTable->RSSI_max = MaxRSSI; +} + + + +#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + +VOID +odm_S0S1_SWAntDiv_Reset( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + pDM_FatTable->bBecomeLinked = FALSE; + pDM_SWAT_Table->try_flag = SWAW_STEP_INIT; + pDM_SWAT_Table->Double_chk_flag = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_S0S1_SWAntDiv_Reset(): pDM_FatTable->bBecomeLinked = %d\n", pDM_FatTable->bBecomeLinked)); +} + +VOID +odm_S0S1_SwAntDiv( + IN PVOID pDM_VOID, + IN u1Byte Step + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + u4Byte i, MinMaxRSSI = 0xFF, LocalMaxRSSI, LocalMinRSSI; + u4Byte Main_RSSI, Aux_RSSI; + u1Byte HighTraffic_TrainTime_U = 0x32, HighTraffic_TrainTime_L = 0, Train_time_temp; + u1Byte LowTraffic_TrainTime_U = 200, LowTraffic_TrainTime_L = 0; + u1Byte RxIdleAnt = pDM_SWAT_Table->PreAntenna, TargetAnt, nextAnt = 0; + PSTA_INFO_T pEntry = NULL; + u4Byte value32; + + + if(!pDM_Odm->bLinked) //bLinked==False + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); + if(pDM_FatTable->bBecomeLinked == TRUE) + { + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); + if (pDM_Odm->SupportICType == ODM_RTL8723B) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set REG 948[9:6]=0x0\n")); + ODM_SetBBReg(pDM_Odm, 0x948 , (BIT9|BIT8|BIT7|BIT6), 0x0); + } + pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; + } + return; + } + else + { + if(pDM_FatTable->bBecomeLinked ==FALSE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n")); + + if(pDM_Odm->SupportICType == ODM_RTL8723B) + { + value32 = ODM_GetBBReg(pDM_Odm, 0x864, BIT5|BIT4|BIT3); + + #if (RTL8723B_SUPPORT == 1) + if (value32 == 0x0) + ODM_UpdateRxIdleAnt_8723B(pDM_Odm, MAIN_ANT, ANT1_2G, ANT2_2G); + else if (value32 == 0x1) + ODM_UpdateRxIdleAnt_8723B(pDM_Odm, AUX_ANT, ANT2_2G, ANT1_2G); + #endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("8723B: First link! Force antenna to %s\n",(value32 == 0x0?"MAIN":"AUX") )); + } + pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; + } + } + + if (pDM_Odm->bOneEntryOnly == TRUE) + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); + else + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_DESC); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[%d] { try_flag=(( %d )), Step=(( %d )), Double_chk_flag = (( %d )) }\n", + __LINE__,pDM_SWAT_Table->try_flag,Step,pDM_SWAT_Table->Double_chk_flag)); + + // Handling step mismatch condition. + // Peak step is not finished at last time. Recover the variable and check again. + if( Step != pDM_SWAT_Table->try_flag ) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Step != try_flag] Need to Reset After Link\n")); + ODM_SwAntDivRestAfterLink(pDM_Odm); + } + + if (pDM_SWAT_Table->try_flag == SWAW_STEP_INIT) { + + pDM_SWAT_Table->try_flag = SWAW_STEP_PEEK; + pDM_SWAT_Table->Train_time_flag=0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[set try_flag = 0] Prepare for peek!\n\n")); + return; + + } else { + + //1 Normal State (Begin Trying) + if (pDM_SWAT_Table->try_flag == SWAW_STEP_PEEK) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TxOkCnt=(( %llu )), RxOkCnt=(( %llu )), TrafficLoad = (%d))\n", pDM_Odm->curTxOkCnt, pDM_Odm->curRxOkCnt, pDM_Odm->TrafficLoad)); + + if (pDM_Odm->TrafficLoad == TRAFFIC_HIGH) + { + Train_time_temp = pDM_SWAT_Table->Train_time ; + + if(pDM_SWAT_Table->Train_time_flag==3) + { + HighTraffic_TrainTime_L=0xa; + + if(Train_time_temp<=16) + Train_time_temp=HighTraffic_TrainTime_L; + else + Train_time_temp-=16; + + } + else if(pDM_SWAT_Table->Train_time_flag==2) + { + Train_time_temp-=8; + HighTraffic_TrainTime_L=0xf; + } + else if(pDM_SWAT_Table->Train_time_flag==1) + { + Train_time_temp-=4; + HighTraffic_TrainTime_L=0x1e; + } + else if(pDM_SWAT_Table->Train_time_flag==0) + { + Train_time_temp+=8; + HighTraffic_TrainTime_L=0x28; + } + + + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Train_time_temp = ((%d))\n",Train_time_temp)); + + //-- + if(Train_time_temp > HighTraffic_TrainTime_U) + Train_time_temp=HighTraffic_TrainTime_U; + + else if(Train_time_temp < HighTraffic_TrainTime_L) + Train_time_temp=HighTraffic_TrainTime_L; + + pDM_SWAT_Table->Train_time = Train_time_temp; /*10ms~200ms*/ + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Train_time_flag=((%d)), Train_time=((%d))\n", pDM_SWAT_Table->Train_time_flag, pDM_SWAT_Table->Train_time)); + + } else if ((pDM_Odm->TrafficLoad == TRAFFIC_MID) || (pDM_Odm->TrafficLoad == TRAFFIC_LOW)) { + + Train_time_temp=pDM_SWAT_Table->Train_time ; + + if(pDM_SWAT_Table->Train_time_flag==3) + { + LowTraffic_TrainTime_L=10; + if(Train_time_temp<50) + Train_time_temp=LowTraffic_TrainTime_L; + else + Train_time_temp-=50; + } + else if(pDM_SWAT_Table->Train_time_flag==2) + { + Train_time_temp-=30; + LowTraffic_TrainTime_L=36; + } + else if(pDM_SWAT_Table->Train_time_flag==1) + { + Train_time_temp-=10; + LowTraffic_TrainTime_L=40; + } + else + Train_time_temp+=10; + + //-- + if(Train_time_temp >= LowTraffic_TrainTime_U) + Train_time_temp=LowTraffic_TrainTime_U; + + else if(Train_time_temp <= LowTraffic_TrainTime_L) + Train_time_temp=LowTraffic_TrainTime_L; + + pDM_SWAT_Table->Train_time = Train_time_temp; /*10ms~200ms*/ + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Train_time_flag=((%d)) , Train_time=((%d))\n", pDM_SWAT_Table->Train_time_flag, pDM_SWAT_Table->Train_time)); + + } else { + pDM_SWAT_Table->Train_time = 0xc8; /*200ms*/ + + } + + //----------------- + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Current MinMaxRSSI is ((%d))\n", pDM_FatTable->MinMaxRSSI)); + + //---reset index--- + if (pDM_SWAT_Table->reset_idx >= RSSI_CHECK_RESET_PERIOD) { + + pDM_FatTable->MinMaxRSSI = 0; + pDM_SWAT_Table->reset_idx = 0; + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reset_idx = (( %d ))\n", pDM_SWAT_Table->reset_idx)); + + pDM_SWAT_Table->reset_idx++; + + //---double check flag--- + if ((pDM_FatTable->MinMaxRSSI > RSSI_CHECK_THRESHOLD) && (pDM_SWAT_Table->Double_chk_flag == 0)) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" MinMaxRSSI is ((%d)), and > %d\n", + pDM_FatTable->MinMaxRSSI, RSSI_CHECK_THRESHOLD)); + + pDM_SWAT_Table->Double_chk_flag =1; + pDM_SWAT_Table->try_flag = SWAW_STEP_DETERMINE; + pDM_SWAT_Table->RSSI_Trying = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Test the current Ant for (( %d )) ms again\n", pDM_SWAT_Table->Train_time)); + ODM_UpdateRxIdleAnt(pDM_Odm, pDM_FatTable->RxIdleAnt); + ODM_SetTimer(pDM_Odm, &(pDM_SWAT_Table->phydm_SwAntennaSwitchTimer), pDM_SWAT_Table->Train_time); /*ms*/ + return; + } + + nextAnt = (pDM_FatTable->RxIdleAnt == MAIN_ANT)? AUX_ANT : MAIN_ANT; + + pDM_SWAT_Table->try_flag = SWAW_STEP_DETERMINE; + + if(pDM_SWAT_Table->reset_idx<=1) + pDM_SWAT_Table->RSSI_Trying = 2; + else + pDM_SWAT_Table->RSSI_Trying = 1; + + odm_S0S1_SwAntDivByCtrlFrame(pDM_Odm, SWAW_STEP_PEEK); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[set try_flag=1] Normal State: Begin Trying!!\n")); + + } else if ((pDM_SWAT_Table->try_flag == SWAW_STEP_DETERMINE) && (pDM_SWAT_Table->Double_chk_flag == 0)) { + + nextAnt = (pDM_FatTable->RxIdleAnt == MAIN_ANT)? AUX_ANT : MAIN_ANT; + pDM_SWAT_Table->RSSI_Trying--; + } + + //1 Decision State + if ((pDM_SWAT_Table->try_flag == SWAW_STEP_DETERMINE) && (pDM_SWAT_Table->RSSI_Trying == 0)) { + + BOOLEAN bByCtrlFrame = FALSE; + u8Byte pkt_cnt_total = 0; + + for (i=0; ipODM_StaInfo[i]; + if(IS_STA_VALID(pEntry)) + { + //2 Caculate RSSI per Antenna + Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0; + Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0; + + if(pDM_FatTable->MainAnt_Cnt[i]<=1 && pDM_FatTable->CCK_counter_main>=1) + Main_RSSI=0; + + if(pDM_FatTable->AuxAnt_Cnt[i]<=1 && pDM_FatTable->CCK_counter_aux>=1) + Aux_RSSI=0; + + TargetAnt = (Main_RSSI==Aux_RSSI)?pDM_SWAT_Table->PreAntenna:((Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT); + LocalMaxRSSI = (Main_RSSI>=Aux_RSSI) ? Main_RSSI : Aux_RSSI; + LocalMinRSSI = (Main_RSSI>=Aux_RSSI) ? Aux_RSSI : Main_RSSI; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** CCK_counter_main = (( %d )) , CCK_counter_aux= (( %d )) \n", pDM_FatTable->CCK_counter_main, pDM_FatTable->CCK_counter_aux)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** OFDM_counter_main = (( %d )) , OFDM_counter_aux= (( %d )) \n", pDM_FatTable->OFDM_counter_main, pDM_FatTable->OFDM_counter_aux)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Main_Cnt = (( %d )) , Main_RSSI= (( %d )) \n", pDM_FatTable->MainAnt_Cnt[i], Main_RSSI)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Aux_Cnt = (( %d )) , Aux_RSSI = (( %d )) \n", pDM_FatTable->AuxAnt_Cnt[i] , Aux_RSSI )); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** MAC ID:[ %d ] , TargetAnt = (( %s )) \n", i ,( TargetAnt ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT")); + + //2 Select RX Idle Antenna + + if (LocalMaxRSSI != 0 && LocalMaxRSSI < MinMaxRSSI) + { + RxIdleAnt = TargetAnt; + MinMaxRSSI = LocalMaxRSSI; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** LocalMaxRSSI-LocalMinRSSI = ((%d))\n",(LocalMaxRSSI-LocalMinRSSI))); + + if((LocalMaxRSSI-LocalMinRSSI)>8) + { + if(LocalMinRSSI != 0) + pDM_SWAT_Table->Train_time_flag=3; + else + { + if (MinMaxRSSI > RSSI_CHECK_THRESHOLD) + pDM_SWAT_Table->Train_time_flag=0; + else + pDM_SWAT_Table->Train_time_flag=3; + } + } + else if((LocalMaxRSSI-LocalMinRSSI)>5) + pDM_SWAT_Table->Train_time_flag=2; + else if((LocalMaxRSSI-LocalMinRSSI)>2) + pDM_SWAT_Table->Train_time_flag=1; + else + pDM_SWAT_Table->Train_time_flag=0; + + } + + //2 Select TX Antenna + if(TargetAnt == MAIN_ANT) + pDM_FatTable->antsel_a[i] = ANT1_2G; + else + pDM_FatTable->antsel_a[i] = ANT2_2G; + + } + pDM_FatTable->MainAnt_Sum[i] = 0; + pDM_FatTable->AuxAnt_Sum[i] = 0; + pDM_FatTable->MainAnt_Cnt[i] = 0; + pDM_FatTable->AuxAnt_Cnt[i] = 0; + } + + if(pDM_SWAT_Table->bSWAntDivByCtrlFrame) + { + odm_S0S1_SwAntDivByCtrlFrame(pDM_Odm, SWAW_STEP_DETERMINE); + bByCtrlFrame = TRUE; + } + + pkt_cnt_total = pDM_FatTable->CCK_counter_main + pDM_FatTable->CCK_counter_aux + + pDM_FatTable->OFDM_counter_main + pDM_FatTable->OFDM_counter_aux; + pDM_FatTable->CCK_counter_main=0; + pDM_FatTable->CCK_counter_aux=0; + pDM_FatTable->OFDM_counter_main=0; + pDM_FatTable->OFDM_counter_aux=0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Control frame packet counter = %d, Data frame packet counter = %llu\n", + pDM_SWAT_Table->PktCnt_SWAntDivByCtrlFrame, pkt_cnt_total)); + + if(MinMaxRSSI == 0xff || ((pkt_cnt_total < (pDM_SWAT_Table->PktCnt_SWAntDivByCtrlFrame >> 1)) && pDM_Odm->PhyDbgInfo.NumQryBeaconPkt < 2)) + { + MinMaxRSSI = 0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Check RSSI of control frame because MinMaxRSSI == 0xff\n")); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("bByCtrlFrame = %d\n", bByCtrlFrame)); + + if(bByCtrlFrame) + { + Main_RSSI = (pDM_FatTable->MainAnt_CtrlFrame_Cnt!=0)?(pDM_FatTable->MainAnt_CtrlFrame_Sum/pDM_FatTable->MainAnt_CtrlFrame_Cnt):0; + Aux_RSSI = (pDM_FatTable->AuxAnt_CtrlFrame_Cnt!=0)?(pDM_FatTable->AuxAnt_CtrlFrame_Sum/pDM_FatTable->AuxAnt_CtrlFrame_Cnt):0; + + if(pDM_FatTable->MainAnt_CtrlFrame_Cnt<=1 && pDM_FatTable->CCK_CtrlFrame_Cnt_main>=1) + Main_RSSI=0; + + if(pDM_FatTable->AuxAnt_CtrlFrame_Cnt<=1 && pDM_FatTable->CCK_CtrlFrame_Cnt_aux>=1) + Aux_RSSI=0; + + if (Main_RSSI != 0 || Aux_RSSI != 0) + { + RxIdleAnt = (Main_RSSI==Aux_RSSI)?pDM_SWAT_Table->PreAntenna:((Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT); + LocalMaxRSSI = (Main_RSSI>=Aux_RSSI) ? Main_RSSI : Aux_RSSI; + LocalMinRSSI = (Main_RSSI>=Aux_RSSI) ? Aux_RSSI : Main_RSSI; + + if((LocalMaxRSSI-LocalMinRSSI)>8) + pDM_SWAT_Table->Train_time_flag=3; + else if((LocalMaxRSSI-LocalMinRSSI)>5) + pDM_SWAT_Table->Train_time_flag=2; + else if((LocalMaxRSSI-LocalMinRSSI)>2) + pDM_SWAT_Table->Train_time_flag=1; + else + pDM_SWAT_Table->Train_time_flag=0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Control frame: Main_RSSI = %d, Aux_RSSI = %d\n", Main_RSSI, Aux_RSSI)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("RxIdleAnt decided by control frame = %s\n", (RxIdleAnt == MAIN_ANT?"MAIN":"AUX"))); + } + } + } + + pDM_FatTable->MinMaxRSSI = MinMaxRSSI; + pDM_SWAT_Table->try_flag = SWAW_STEP_PEEK; + + if( pDM_SWAT_Table->Double_chk_flag==1) + { + pDM_SWAT_Table->Double_chk_flag=0; + + if (pDM_FatTable->MinMaxRSSI > RSSI_CHECK_THRESHOLD) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [Double check] MinMaxRSSI ((%d)) > %d again!!\n", + pDM_FatTable->MinMaxRSSI, RSSI_CHECK_THRESHOLD)); + + ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[reset try_flag = 0] Training accomplished !!!]\n\n\n")); + return; + } + else + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [Double check] MinMaxRSSI ((%d)) <= %d !!\n", + pDM_FatTable->MinMaxRSSI, RSSI_CHECK_THRESHOLD)); + + nextAnt = (pDM_FatTable->RxIdleAnt == MAIN_ANT)? AUX_ANT : MAIN_ANT; + pDM_SWAT_Table->try_flag = SWAW_STEP_PEEK; + pDM_SWAT_Table->reset_idx = RSSI_CHECK_RESET_PERIOD; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[set try_flag=0] Normal State: Need to tryg again!!\n\n\n")); + return; + } + } + else + { + if (pDM_FatTable->MinMaxRSSI < RSSI_CHECK_THRESHOLD) + pDM_SWAT_Table->reset_idx = RSSI_CHECK_RESET_PERIOD; + + pDM_SWAT_Table->PreAntenna =RxIdleAnt; + ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt ); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("[reset try_flag = 0] Training accomplished !!!] \n\n\n")); + return; + } + + } + + } + + //1 4.Change TRX antenna + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("RSSI_Trying = (( %d )), Ant: (( %s )) >>> (( %s )) \n", + pDM_SWAT_Table->RSSI_Trying, (pDM_FatTable->RxIdleAnt == MAIN_ANT?"MAIN":"AUX"),(nextAnt == MAIN_ANT?"MAIN":"AUX"))); + + ODM_UpdateRxIdleAnt(pDM_Odm, nextAnt); + + //1 5.Reset Statistics + + pDM_FatTable->RxIdleAnt = nextAnt; + + //1 6.Set next timer (Trying State) + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Test ((%s)) Ant for (( %d )) ms\n", (nextAnt == MAIN_ANT?"MAIN":"AUX"), pDM_SWAT_Table->Train_time)); + ODM_SetTimer(pDM_Odm, &(pDM_SWAT_Table->phydm_SwAntennaSwitchTimer), pDM_SWAT_Table->Train_time); /*ms*/ +} + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +ODM_SW_AntDiv_Callback( + PRT_TIMER pTimer +) +{ + PADAPTER Adapter = (PADAPTER)pTimer->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + pSWAT_T pDM_SWAT_Table = &pHalData->DM_OutSrc.DM_SWAT_Table; + + #if DEV_BUS_TYPE==RT_PCI_INTERFACE + #if USE_WORKITEM + ODM_ScheduleWorkItem(&pDM_SWAT_Table->phydm_SwAntennaSwitchWorkitem); + #else + { + //DbgPrint("SW_antdiv_Callback"); + odm_S0S1_SwAntDiv(&pHalData->DM_OutSrc, SWAW_STEP_DETERMINE); + } + #endif + #else + ODM_ScheduleWorkItem(&pDM_SWAT_Table->phydm_SwAntennaSwitchWorkitem); + #endif +} +VOID +ODM_SW_AntDiv_WorkitemCallback( + IN PVOID pContext + ) +{ + PADAPTER pAdapter = (PADAPTER)pContext; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + //DbgPrint("SW_antdiv_Workitem_Callback"); + odm_S0S1_SwAntDiv(&pHalData->DM_OutSrc, SWAW_STEP_DETERMINE); +} + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + +VOID +ODM_SW_AntDiv_WorkitemCallback( + IN PVOID pContext +) +{ + PADAPTER + pAdapter = (PADAPTER)pContext; + HAL_DATA_TYPE + *pHalData = GET_HAL_DATA(pAdapter); + + /*DbgPrint("SW_antdiv_Workitem_Callback");*/ + odm_S0S1_SwAntDiv(&pHalData->odmpriv, SWAW_STEP_DETERMINE); +} + +VOID +ODM_SW_AntDiv_Callback(void *FunctionContext) +{ + PDM_ODM_T pDM_Odm= (PDM_ODM_T)FunctionContext; + PADAPTER padapter = pDM_Odm->Adapter; + if(padapter->net_closed == _TRUE) + return; + + #if 0 /* Can't do I/O in timer callback*/ + odm_S0S1_SwAntDiv(pDM_Odm, SWAW_STEP_DETERMINE); + #else + rtw_run_in_thread_cmd(padapter, ODM_SW_AntDiv_WorkitemCallback, padapter); + #endif +} + + +#endif + +VOID +odm_S0S1_SwAntDivByCtrlFrame( + IN PVOID pDM_VOID, + IN u1Byte Step + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + switch(Step) + { + case SWAW_STEP_PEEK: + pDM_SWAT_Table->PktCnt_SWAntDivByCtrlFrame = 0; + pDM_SWAT_Table->bSWAntDivByCtrlFrame = TRUE; + pDM_FatTable->MainAnt_CtrlFrame_Cnt = 0; + pDM_FatTable->AuxAnt_CtrlFrame_Cnt = 0; + pDM_FatTable->MainAnt_CtrlFrame_Sum = 0; + pDM_FatTable->AuxAnt_CtrlFrame_Sum = 0; + pDM_FatTable->CCK_CtrlFrame_Cnt_main = 0; + pDM_FatTable->CCK_CtrlFrame_Cnt_aux = 0; + pDM_FatTable->OFDM_CtrlFrame_Cnt_main = 0; + pDM_FatTable->OFDM_CtrlFrame_Cnt_aux = 0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_S0S1_SwAntDivForAPMode(): Start peek and reset counter\n")); + break; + case SWAW_STEP_DETERMINE: + pDM_SWAT_Table->bSWAntDivByCtrlFrame = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_S0S1_SwAntDivForAPMode(): Stop peek\n")); + break; + default: + pDM_SWAT_Table->bSWAntDivByCtrlFrame = FALSE; + break; + } +} + +VOID +odm_AntselStatisticsOfCtrlFrame( + IN PVOID pDM_VOID, + IN u1Byte antsel_tr_mux, + IN u4Byte RxPWDBAll + + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + if(antsel_tr_mux == ANT1_2G) + { + pDM_FatTable->MainAnt_CtrlFrame_Sum+=RxPWDBAll; + pDM_FatTable->MainAnt_CtrlFrame_Cnt++; + } + else + { + pDM_FatTable->AuxAnt_CtrlFrame_Sum+=RxPWDBAll; + pDM_FatTable->AuxAnt_CtrlFrame_Cnt++; + } +} + +VOID +odm_S0S1_SwAntDivByCtrlFrame_ProcessRSSI( + IN PVOID pDM_VOID, + IN PVOID p_phy_info_void, + IN PVOID p_pkt_info_void + //IN PODM_PHY_INFO_T pPhyInfo, + //IN PODM_PACKET_INFO_T pPktinfo + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PODM_PHY_INFO_T pPhyInfo=(PODM_PHY_INFO_T)p_phy_info_void; + PODM_PACKET_INFO_T pPktinfo=(PODM_PACKET_INFO_T)p_pkt_info_void; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + BOOLEAN isCCKrate; + + if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) + return; + + if(pDM_Odm->AntDivType != S0S1_SW_ANTDIV) + return; + + // In try state + if(!pDM_SWAT_Table->bSWAntDivByCtrlFrame) + return; + + // No HW error and match receiver address + if(!pPktinfo->bToSelf) + return; + + pDM_SWAT_Table->PktCnt_SWAntDivByCtrlFrame++; + isCCKrate = ((pPktinfo->DataRate >= DESC_RATE1M ) && (pPktinfo->DataRate <= DESC_RATE11M ))?TRUE :FALSE; + + if(isCCKrate) + { + pDM_FatTable->antsel_rx_keep_0 = (pDM_FatTable->RxIdleAnt == MAIN_ANT) ? ANT1_2G : ANT2_2G; + + if(pDM_FatTable->antsel_rx_keep_0==ANT1_2G) + pDM_FatTable->CCK_CtrlFrame_Cnt_main++; + else + pDM_FatTable->CCK_CtrlFrame_Cnt_aux++; + + odm_AntselStatisticsOfCtrlFrame(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]); + } + else + { + if(pDM_FatTable->antsel_rx_keep_0==ANT1_2G) + pDM_FatTable->OFDM_CtrlFrame_Cnt_main++; + else + pDM_FatTable->OFDM_CtrlFrame_Cnt_aux++; + + odm_AntselStatisticsOfCtrlFrame(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPhyInfo->RxPWDBAll); + } +} + +#endif //#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1) + + + + +VOID +odm_SetNextMACAddrTarget( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + PSTA_INFO_T pEntry; + u4Byte value32, i; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SetNextMACAddrTarget() ==>\n")); + + if (pDM_Odm->bLinked) + { + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + + if ((pDM_FatTable->TrainIdx+1) == ODM_ASSOCIATE_ENTRY_NUM) + pDM_FatTable->TrainIdx = 0; + else + pDM_FatTable->TrainIdx++; + + pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx]; + + if (IS_STA_VALID(pEntry)) { + + /*Match MAC ADDR*/ + #if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) + value32 = (pEntry->hwaddr[5]<<8)|pEntry->hwaddr[4]; + #else + value32 = (pEntry->MacAddr[5]<<8)|pEntry->MacAddr[4]; + #endif + + ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, value32);/*0x7b4~0x7b5*/ + + #if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) + value32 = (pEntry->hwaddr[3]<<24)|(pEntry->hwaddr[2]<<16) |(pEntry->hwaddr[1]<<8) |pEntry->hwaddr[0]; + #else + value32 = (pEntry->MacAddr[3]<<24)|(pEntry->MacAddr[2]<<16) |(pEntry->MacAddr[1]<<8) |pEntry->MacAddr[0]; + #endif + ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, value32);/*0x7b0~0x7b3*/ + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_FatTable->TrainIdx=%d\n", pDM_FatTable->TrainIdx)); + + #if (DM_ODM_SUPPORT_TYPE & (ODM_AP | ODM_CE)) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC Addr = %x:%x:%x:%x:%x:%x\n", + pEntry->hwaddr[5], pEntry->hwaddr[4], pEntry->hwaddr[3], pEntry->hwaddr[2], pEntry->hwaddr[1], pEntry->hwaddr[0])); + #else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC Addr = %x:%x:%x:%x:%x:%x\n", + pEntry->MacAddr[5], pEntry->MacAddr[4], pEntry->MacAddr[3], pEntry->MacAddr[2], pEntry->MacAddr[1], pEntry->MacAddr[0])); + #endif + + break; + } + } + } + +#if 0 + // + //2012.03.26 LukeLee: This should be removed later, the MAC address is changed according to MACID in turn + // + #if( DM_ODM_SUPPORT_TYPE & ODM_WIN) + { + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + + for (i=0; i<6; i++) + { + Bssid[i] = pMgntInfo->Bssid[i]; + //DbgPrint("Bssid[%d]=%x\n", i, Bssid[i]); + } + } + #endif + + //odm_SetNextMACAddrTarget(pDM_Odm); + + //1 Select MAC Address Filter + for (i=0; i<6; i++) + { + if(Bssid[i] != pDM_FatTable->Bssid[i]) + { + bMatchBSSID = FALSE; + break; + } + } + if(bMatchBSSID == FALSE) + { + //Match MAC ADDR + value32 = (Bssid[5]<<8)|Bssid[4]; + ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, value32); + value32 = (Bssid[3]<<24)|(Bssid[2]<<16) |(Bssid[1]<<8) |Bssid[0]; + ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, value32); + } + + return bMatchBSSID; +#endif + +} + +#if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + +VOID +odm_FastAntTraining( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + u4Byte MaxRSSI_pathA=0, Pckcnt_pathA=0; + u1Byte i,TargetAnt_pathA=0; + BOOLEAN bPktFilterMacth_pathA = FALSE; + #if(RTL8192E_SUPPORT == 1) + u4Byte MaxRSSI_pathB=0, Pckcnt_pathB=0; + u1Byte TargetAnt_pathB=0; + BOOLEAN bPktFilterMacth_pathB = FALSE; + #endif + + + if(!pDM_Odm->bLinked) //bLinked==False + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); + + if(pDM_FatTable->bBecomeLinked == TRUE) + { + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + phydm_FastTraining_enable(pDM_Odm , FAT_OFF); + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); + pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; + } + return; + } + else + { + if(pDM_FatTable->bBecomeLinked ==FALSE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked!!!]\n")); + pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; + } + } + + if (pDM_Odm->bOneEntryOnly == TRUE) + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); + else + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_DESC); + + + if(pDM_Odm->SupportICType == ODM_RTL8188E) + { + ODM_SetBBReg(pDM_Odm, 0x864 , BIT2|BIT1|BIT0, ((pDM_Odm->fat_comb_a)-1)); + } + #if(RTL8192E_SUPPORT == 1) + else if(pDM_Odm->SupportICType == ODM_RTL8192E) + { + ODM_SetBBReg(pDM_Odm, 0xB38 , BIT2|BIT1|BIT0, ((pDM_Odm->fat_comb_a)-1) ); //path-A // ant combination=regB38[2:0]+1 + ODM_SetBBReg(pDM_Odm, 0xB38 , BIT18|BIT17|BIT16, ((pDM_Odm->fat_comb_b)-1) ); //path-B // ant combination=regB38[18:16]+1 + } + #endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("==>odm_FastAntTraining()\n")); + + //1 TRAINING STATE + if(pDM_FatTable->FAT_State == FAT_TRAINING_STATE) + { + //2 Caculate RSSI per Antenna + + //3 [path-A]--------------------------- + for (i=0; i<(pDM_Odm->fat_comb_a); i++) // i : antenna index + { + if(pDM_FatTable->antRSSIcnt[i] == 0) + pDM_FatTable->antAveRSSI[i] = 0; + else + { + pDM_FatTable->antAveRSSI[i] = pDM_FatTable->antSumRSSI[i] /pDM_FatTable->antRSSIcnt[i]; + bPktFilterMacth_pathA = TRUE; + } + + if(pDM_FatTable->antAveRSSI[i] > MaxRSSI_pathA) + { + MaxRSSI_pathA = pDM_FatTable->antAveRSSI[i]; + Pckcnt_pathA = pDM_FatTable ->antRSSIcnt[i]; + TargetAnt_pathA = i ; + } + else if(pDM_FatTable->antAveRSSI[i] == MaxRSSI_pathA) + { + if( (pDM_FatTable->antRSSIcnt[i] ) > Pckcnt_pathA) + { + MaxRSSI_pathA = pDM_FatTable->antAveRSSI[i]; + Pckcnt_pathA = pDM_FatTable ->antRSSIcnt[i]; + TargetAnt_pathA = i ; + } + } + + ODM_RT_TRACE("*** Ant-Index : [ %d ], Counter = (( %d )), Avg RSSI = (( %d )) \n", i, pDM_FatTable->antRSSIcnt[i], pDM_FatTable->antAveRSSI[i] ); + } + + + /* + #if(RTL8192E_SUPPORT == 1) + //3 [path-B]--------------------------- + for (i=0; i<(pDM_Odm->fat_comb_b); i++) + { + if(pDM_FatTable->antRSSIcnt_pathB[i] == 0) + pDM_FatTable->antAveRSSI_pathB[i] = 0; + else // (antRSSIcnt[i] != 0) + { + pDM_FatTable->antAveRSSI_pathB[i] = pDM_FatTable->antSumRSSI_pathB[i] /pDM_FatTable->antRSSIcnt_pathB[i]; + bPktFilterMacth_pathB = TRUE; + } + if(pDM_FatTable->antAveRSSI_pathB[i] > MaxRSSI_pathB) + { + MaxRSSI_pathB = pDM_FatTable->antAveRSSI_pathB[i]; + Pckcnt_pathB = pDM_FatTable ->antRSSIcnt_pathB[i]; + TargetAnt_pathB = (u1Byte) i; + } + if(pDM_FatTable->antAveRSSI_pathB[i] == MaxRSSI_pathB) + { + if(pDM_FatTable ->antRSSIcnt_pathB > Pckcnt_pathB) + { + MaxRSSI_pathB = pDM_FatTable->antAveRSSI_pathB[i]; + TargetAnt_pathB = (u1Byte) i; + } + } + if (pDM_Odm->fat_print_rssi==1) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***{Path-B}: Sum RSSI[%d] = (( %d )), cnt RSSI [%d] = (( %d )), Avg RSSI[%d] = (( %d )) \n", + i, pDM_FatTable->antSumRSSI_pathB[i], i, pDM_FatTable->antRSSIcnt_pathB[i], i, pDM_FatTable->antAveRSSI_pathB[i])); + } + } + #endif + */ + + //1 DECISION STATE + + //2 Select TRX Antenna + + phydm_FastTraining_enable(pDM_Odm, FAT_OFF); + + //3 [path-A]--------------------------- + if(bPktFilterMacth_pathA == FALSE) + { + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("{Path-A}: None Packet is matched\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("{Path-A}: None Packet is matched\n")); + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + } + else + { + ODM_RT_TRACE("TargetAnt_pathA = (( %d )) , MaxRSSI_pathA = (( %d )) \n",TargetAnt_pathA,MaxRSSI_pathA); + + //3 [ update RX-optional ant ] Default RX is Omni, Optional RX is the best decision by FAT + if(pDM_Odm->SupportICType == ODM_RTL8188E) + { + ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, TargetAnt_pathA); + } + else if(pDM_Odm->SupportICType == ODM_RTL8192E) + { + ODM_SetBBReg(pDM_Odm, 0xB38 , BIT8|BIT7|BIT6, TargetAnt_pathA);//Optional RX [pth-A] + } + //3 [ update TX ant ] + odm_UpdateTxAnt(pDM_Odm, TargetAnt_pathA, (pDM_FatTable->TrainIdx)); + + if(TargetAnt_pathA == 0) + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + } + /* + #if(RTL8192E_SUPPORT == 1) + //3 [path-B]--------------------------- + if(bPktFilterMacth_pathB == FALSE) + { + if (pDM_Odm->fat_print_rssi==1) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***[%d]{Path-B}: None Packet is matched\n\n\n",__LINE__)); + } + } + else + { + if (pDM_Odm->fat_print_rssi==1) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, + (" ***TargetAnt_pathB = (( %d )) *** MaxRSSI = (( %d ))***\n\n\n",TargetAnt_pathB,MaxRSSI_pathB)); + } + ODM_SetBBReg(pDM_Odm, 0xB38 , BIT21|BIT20|BIT19, TargetAnt_pathB); //Default RX is Omni, Optional RX is the best decision by FAT + ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info + + pDM_FatTable->antsel_pathB[pDM_FatTable->TrainIdx] = TargetAnt_pathB; + } + #endif + */ + + //2 Reset Counter + for(i=0; i<(pDM_Odm->fat_comb_a); i++) + { + pDM_FatTable->antSumRSSI[i] = 0; + pDM_FatTable->antRSSIcnt[i] = 0; + } + /* + #if(RTL8192E_SUPPORT == 1) + for(i=0; i<=(pDM_Odm->fat_comb_b); i++) + { + pDM_FatTable->antSumRSSI_pathB[i] = 0; + pDM_FatTable->antRSSIcnt_pathB[i] = 0; + } + #endif + */ + + pDM_FatTable->FAT_State = FAT_PREPARE_STATE; + return; + } + + //1 NORMAL STATE + if (pDM_FatTable->FAT_State == FAT_PREPARE_STATE) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Start Prepare State ]\n")); + + odm_SetNextMACAddrTarget(pDM_Odm); + + //2 Prepare Training + pDM_FatTable->FAT_State = FAT_TRAINING_STATE; + phydm_FastTraining_enable(pDM_Odm , FAT_ON); + odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); //enable HW AntDiv + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Start Training State]\n")); + + ODM_SetTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer, pDM_Odm->antdiv_intvl ); //ms + } + +} + +VOID +odm_FastAntTrainingCallback( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PADAPTER padapter = pDM_Odm->Adapter; + if(padapter->net_closed == _TRUE) + return; + //if(*pDM_Odm->pbNet_closed == TRUE) + // return; +#endif + +#if USE_WORKITEM + ODM_ScheduleWorkItem(&pDM_Odm->FastAntTrainingWorkitem); +#else + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("******odm_FastAntTrainingCallback****** \n")); + odm_FastAntTraining(pDM_Odm); +#endif +} + +VOID +odm_FastAntTrainingWorkItemCallback( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("******odm_FastAntTrainingWorkItemCallback****** \n")); + odm_FastAntTraining(pDM_Odm); +} + +#endif + +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + +u4Byte +phydm_construct_hl_beam_codeword( + IN PVOID pDM_VOID, + IN u4Byte *beam_pattern_idx, + IN u4Byte ant_num + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte codeword = 0; + u4Byte data_tmp; + u1Byte i; + + if (ant_num < 8) { + for (i = 0; i < ant_num; i++) { + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("beam_pattern_num[%x] = %x\n",i,beam_pattern_num[i] ));*/ + if (beam_pattern_idx[i] == 0) { + data_tmp = 0x1; + /**/ + } else if (beam_pattern_idx[i] == 1) { + data_tmp = 0x2; + /**/ + } else if (beam_pattern_idx[i] == 2) { + data_tmp = 0x4; + /**/ + } else if (beam_pattern_idx[i] == 3) { + data_tmp = 0x8; + /**/ + } + codeword |= (data_tmp<<(i*4)); + } + } + + return codeword; +} + +VOID +phydm_update_beam_pattern( + IN PVOID pDM_VOID, + IN u4Byte codeword, + IN u4Byte codeword_length + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); + u1Byte i; + BOOLEAN beam_ctrl_signal; + u4Byte one = 0x1; + u4Byte reg44_tmp_p, reg44_tmp_n, reg44_ori; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Set Beam Pattern =0x%x\n", codeword)); + + reg44_ori = ODM_GetMACReg(pDM_Odm, 0x44, bMaskDWord); + /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44_ori =0x%x\n", reg44_ori));*/ + + for (i = 0; i <= (codeword_length-1); i++) { + beam_ctrl_signal = (BOOLEAN)((codeword&BIT(i)) >> i); + + if (pDM_Odm->DebugComponents & ODM_COMP_ANT_DIV) { + + if (i == (codeword_length-1)) { + DbgPrint("%d ]\n", beam_ctrl_signal); + /**/ + } else if (i == 0) { + DbgPrint("Send codeword[1:24] ---> [ %d ", beam_ctrl_signal); + /**/ + } else if ((i % 4) == 3) { + DbgPrint("%d | ", beam_ctrl_signal); + /**/ + } else { + DbgPrint("%d ", beam_ctrl_signal); + /**/ + } + } + + #if 1 + reg44_tmp_p = reg44_ori & (~(BIT11|BIT10)); /*clean bit 10 & 11*/ + reg44_tmp_p |= ((1<<11) | (beam_ctrl_signal<<10)); + reg44_tmp_n = reg44_ori & (~(BIT11|BIT10)); + + /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("reg44_tmp_p =(( 0x%x )), reg44_tmp_n = (( 0x%x ))\n", reg44_tmp_p, reg44_tmp_n));*/ + ODM_SetMACReg(pDM_Odm, 0x44 , bMaskDWord, reg44_tmp_p); + ODM_SetMACReg(pDM_Odm, 0x44 , bMaskDWord, reg44_tmp_n); + #else + ODM_SetMACReg(pDM_Odm, 0x44 , BIT11|BIT10, ((1<<1) | beam_ctrl_signal)); + ODM_SetMACReg(pDM_Odm, 0x44 , BIT11, 0); + #endif + + } +} + +VOID +phydm_update_rx_idle_beam( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); + u4Byte i; + + pdm_sat_table->update_beam_codeword = phydm_construct_hl_beam_codeword(pDM_Odm, &(pdm_sat_table->rx_idle_beam[0]), pdm_sat_table->ant_num); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set target beam_pattern codeword = (( 0x%x ))\n", pdm_sat_table->update_beam_codeword)); + + for (i = 0; i < (pdm_sat_table->ant_num); i++) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Beam ] RxIdleBeam[%d] =%d\n", i, pdm_sat_table->rx_idle_beam[i])); + /**/ + } + + #if DEV_BUS_TYPE == RT_PCI_INTERFACE + phydm_update_beam_pattern(pDM_Odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->data_codeword_bit_num); + #else + ODM_ScheduleWorkItem(&pdm_sat_table->hl_smart_antenna_workitem); + /*ODM_StallExecution(1);*/ + #endif + + pdm_sat_table->pre_codeword = pdm_sat_table->update_beam_codeword; +} + +VOID +phydm_hl_smart_ant_cmd( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); + u4Byte used = *_used; + u4Byte out_len = *_out_len; + u4Byte one = 0x1; + u4Byte codeword_length = pdm_sat_table->data_codeword_bit_num; + u4Byte beam_ctrl_signal, i; + + if (dm_value[0] == 1) { /*fix beam pattern*/ + + pdm_sat_table->fix_beam_pattern_en = dm_value[1]; + + if (pdm_sat_table->fix_beam_pattern_en == 1) { + + pdm_sat_table->fix_beam_pattern_codeword = dm_value[2]; + + if (pdm_sat_table->fix_beam_pattern_codeword > (one<fix_beam_pattern_codeword, codeword_length)); + (pdm_sat_table->fix_beam_pattern_codeword) &= 0xffffff; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Auto modify to (0x%x)\n", pdm_sat_table->fix_beam_pattern_codeword)); + } + + pdm_sat_table->update_beam_codeword = pdm_sat_table->fix_beam_pattern_codeword; + + /*---------------------------------------------------------*/ + PHYDM_SNPRINTF((output+used, out_len-used, "Fix Beam Pattern\n")); + for (i = 0; i <= (codeword_length-1); i++) { + beam_ctrl_signal = (BOOLEAN)((pdm_sat_table->update_beam_codeword&BIT(i)) >> i); + + if (i == (codeword_length-1)) { + PHYDM_SNPRINTF((output+used, out_len-used, "%d]\n", beam_ctrl_signal)); + /**/ + } else if (i == 0) { + PHYDM_SNPRINTF((output+used, out_len-used, "Send Codeword[1:24] to RFU -> [%d", beam_ctrl_signal)); + /**/ + } else if ((i % 4) == 3) { + PHYDM_SNPRINTF((output+used, out_len-used, "%d|", beam_ctrl_signal)); + /**/ + } else { + PHYDM_SNPRINTF((output+used, out_len-used, "%d", beam_ctrl_signal)); + /**/ + } + } + /*---------------------------------------------------------*/ + + + #if DEV_BUS_TYPE == RT_PCI_INTERFACE + phydm_update_beam_pattern(pDM_Odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->data_codeword_bit_num); + #else + ODM_ScheduleWorkItem(&pdm_sat_table->hl_smart_antenna_workitem); + /*ODM_StallExecution(1);*/ + #endif + } else if (pdm_sat_table->fix_beam_pattern_en == 0) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Smart Antenna: Enable\n")); + } + + } else if (dm_value[0] == 2) { /*set latch time*/ + + pdm_sat_table->latch_time = dm_value[1]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] latch_time =0x%x\n", pdm_sat_table->latch_time)); + } else if (dm_value[0] == 3) { + + pdm_sat_table->fix_training_num_en = dm_value[1]; + + if (pdm_sat_table->fix_training_num_en == 1) { + pdm_sat_table->per_beam_training_pkt_num = dm_value[2]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Fix per_beam_training_pkt_num = (( 0x%x ))\n", pdm_sat_table->per_beam_training_pkt_num)); + } else if (pdm_sat_table->fix_training_num_en == 0) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] AUTO per_beam_training_pkt_num\n")); + /**/ + } + } + +} + + +void +phydm_set_all_ant_same_beam_num( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); + + if (pDM_Odm->AntDivType == HL_SW_SMART_ANT_TYPE1) { /*2Ant for 8821A*/ + + pdm_sat_table->rx_idle_beam[0] = pdm_sat_table->fast_training_beam_num; + pdm_sat_table->rx_idle_beam[1] = pdm_sat_table->fast_training_beam_num; + } + + pdm_sat_table->update_beam_codeword = phydm_construct_hl_beam_codeword(pDM_Odm, &(pdm_sat_table->rx_idle_beam[0]), pdm_sat_table->ant_num); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Set all ant beam_pattern: codeword = (( 0x%x ))\n", pdm_sat_table->update_beam_codeword)); + + #if DEV_BUS_TYPE == RT_PCI_INTERFACE + phydm_update_beam_pattern(pDM_Odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->data_codeword_bit_num); + #else + ODM_ScheduleWorkItem(&pdm_sat_table->hl_smart_antenna_workitem); + /*ODM_StallExecution(1);*/ + #endif +} + +VOID +odm_FastAntTraining_hl_smart_antenna_type1( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); + pFAT_T pDM_FatTable = &(pDM_Odm->DM_FatTable); + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + u4Byte codeword = 0, i, j; + u4Byte TargetAnt; + u4Byte avg_rssi_tmp; + u4Byte target_ant_beam_max_rssi[SUPPORT_RF_PATH_NUM] = {0}; + u4Byte max_beam_ant_rssi = 0; + u4Byte target_ant_beam[SUPPORT_RF_PATH_NUM] = {0}; + u4Byte beam_tmp; + + + if (!pDM_Odm->bLinked) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n")); + + if (pDM_FatTable->bBecomeLinked == TRUE) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Link -> no Link\n")); + pDM_FatTable->FAT_State = FAT_BEFORE_LINK_STATE; + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("change to (( %d )) FAT_state\n", pDM_FatTable->FAT_State)); + + pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; + } + return; + + } else { + if (pDM_FatTable->bBecomeLinked == FALSE) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n")); + + pDM_FatTable->FAT_State = FAT_PREPARE_STATE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("change to (( %d )) FAT_state\n", pDM_FatTable->FAT_State)); + + /*pdm_sat_table->fast_training_beam_num = 0;*/ + /*phydm_set_all_ant_same_beam_num(pDM_Odm);*/ + + pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked; + } + } + + if (pDM_Odm->bOneEntryOnly == TRUE) + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); + else + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_DESC); + + /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("HL Smart Ant Training: State (( %d ))\n", pDM_FatTable->FAT_State));*/ + + /* [DECISION STATE] */ + /*=======================================================================================*/ + if (pDM_FatTable->FAT_State == FAT_DECISION_STATE) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 3. In Decision State]\n")); + phydm_FastTraining_enable(pDM_Odm , FAT_OFF); + + /*compute target beam in each antenna*/ + for (i = 0; i < (pdm_sat_table->ant_num); i++) { + for (j = 0; j < (pdm_sat_table->beam_patten_num_each_ant); j++) { + + if (pdm_sat_table->pkt_rssi_cnt[i][j] == 0) { + avg_rssi_tmp = pdm_sat_table->pkt_rssi_pre[i][j]; + /**/ + } else { + avg_rssi_tmp = (pdm_sat_table->pkt_rssi_sum[i][j]) / (pdm_sat_table->pkt_rssi_cnt[i][j]); + pdm_sat_table->pkt_rssi_pre[i][j] = avg_rssi_tmp; + /**/ + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant[%d], Beam[%d]: pkt_num=(( %d )), avg_rssi=(( %d ))\n", i, j, pdm_sat_table->pkt_rssi_cnt[i][j], avg_rssi_tmp)); + + if (avg_rssi_tmp > target_ant_beam_max_rssi[i]) { + target_ant_beam[i] = j; + target_ant_beam_max_rssi[i] = avg_rssi_tmp; + } + + /*reset counter value*/ + pdm_sat_table->pkt_rssi_sum[i][j] = 0; + pdm_sat_table->pkt_rssi_cnt[i][j] = 0; + + } + pdm_sat_table->rx_idle_beam[i] = target_ant_beam[i]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("---------> Target of Ant[%d]: Beam_num-(( %d )) RSSI= ((%d))\n", + i, target_ant_beam[i], target_ant_beam_max_rssi[i])); + + if (target_ant_beam_max_rssi[i] > max_beam_ant_rssi) { + TargetAnt = i; + max_beam_ant_rssi = target_ant_beam_max_rssi[i]; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Target of Ant = (( %d )) max_beam_ant_rssi = (( %d ))\n", + TargetAnt, max_beam_ant_rssi)); + } + } + + if (TargetAnt == 0) + TargetAnt = MAIN_ANT; + else if (TargetAnt == 1) + TargetAnt = AUX_ANT; + + /* [ update RX ant ]*/ + ODM_UpdateRxIdleAnt(pDM_Odm, (u1Byte)TargetAnt); + + /* [ update TX ant ]*/ + odm_UpdateTxAnt(pDM_Odm, (u1Byte)TargetAnt, (pDM_FatTable->TrainIdx)); + + /*set beam in each antenna*/ + phydm_update_rx_idle_beam(pDM_Odm); + + phydm_FastTraining_enable(pDM_Odm , FAT_OFF); + odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); + pDM_FatTable->FAT_State = FAT_PREPARE_STATE; + + } + /* [TRAINING STATE] */ + else if (pDM_FatTable->FAT_State == FAT_TRAINING_STATE) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2. In Training State]\n")); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("fat_beam_n = (( %d )), pre_fat_beam_n = (( %d ))\n", + pdm_sat_table->fast_training_beam_num, pdm_sat_table->pre_fast_training_beam_num)); + + if (pdm_sat_table->fast_training_beam_num > pdm_sat_table->pre_fast_training_beam_num) { + + pdm_sat_table->force_update_beam_en = 0; + + } else { + + pdm_sat_table->force_update_beam_en = 1; + + pdm_sat_table->pkt_counter = 0; + beam_tmp = pdm_sat_table->fast_training_beam_num; + if (pdm_sat_table->fast_training_beam_num >= (pdm_sat_table->beam_patten_num_each_ant-1)) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Timeout Update] Beam_num (( %d )) -> (( decision ))\n", pdm_sat_table->fast_training_beam_num)); + phydm_FastTraining_enable(pDM_Odm , FAT_OFF); + pDM_FatTable->FAT_State = FAT_DECISION_STATE; + odm_FastAntTraining_hl_smart_antenna_type1(pDM_Odm); + + } else { + pdm_sat_table->fast_training_beam_num++; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Timeout Update] Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num)); + phydm_set_all_ant_same_beam_num(pDM_Odm); + pDM_FatTable->FAT_State = FAT_TRAINING_STATE; + + } + } + pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Update Pre_Beam =(( %d ))\n", pdm_sat_table->pre_fast_training_beam_num)); + } + /* [Prepare State] */ + /*=======================================================================================*/ + else if (pDM_FatTable->FAT_State == FAT_PREPARE_STATE) { + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n\n[ 1. In Prepare State]\n")); + + if (pDM_Odm->pre_TrafficLoad == (pDM_Odm->TrafficLoad)) { + if (pdm_sat_table->decision_holding_period != 0) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Holding_period = (( %d )), return!!!\n", pdm_sat_table->decision_holding_period)); + pdm_sat_table->decision_holding_period--; + return; + } + } + + + /* Set training packet number*/ + if (pdm_sat_table->fix_training_num_en == 0) { + + switch (pDM_Odm->TrafficLoad) { + + case TRAFFIC_HIGH: + pdm_sat_table->per_beam_training_pkt_num = 20; + pdm_sat_table->decision_holding_period = 0; + break; + case TRAFFIC_MID: + pdm_sat_table->per_beam_training_pkt_num = 10; + pdm_sat_table->decision_holding_period = 1; + break; + case TRAFFIC_LOW: + pdm_sat_table->per_beam_training_pkt_num = 5; /*ping 60000*/ + pdm_sat_table->decision_holding_period = 3; + break; + case TRAFFIC_ULTRA_LOW: + pdm_sat_table->per_beam_training_pkt_num = 2; + pdm_sat_table->decision_holding_period = 5; + break; + default: + break; + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Fix_training_num = (( %d )), per_beam_training_pkt_num = (( %d ))\n", + pdm_sat_table->fix_training_num_en , pdm_sat_table->per_beam_training_pkt_num)); + + /* Set training MAC Addr. of target */ + odm_SetNextMACAddrTarget(pDM_Odm); + + phydm_FastTraining_enable(pDM_Odm , FAT_ON); + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + pdm_sat_table->pkt_counter = 0; + pdm_sat_table->fast_training_beam_num = 0; + phydm_set_all_ant_same_beam_num(pDM_Odm); + pdm_sat_table->pre_fast_training_beam_num = pdm_sat_table->fast_training_beam_num; + pDM_FatTable->FAT_State = FAT_TRAINING_STATE; + } + +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +VOID +phydm_beam_switch_workitem_callback( + IN PVOID pContext + ) +{ + PADAPTER pAdapter = (PADAPTER)pContext; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); + + #if DEV_BUS_TYPE != RT_PCI_INTERFACE + pdm_sat_table->pkt_skip_statistic_en = 1; + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Beam Switch Workitem Callback, pkt_skip_statistic_en = (( %d ))\n", pdm_sat_table->pkt_skip_statistic_en)); + + phydm_update_beam_pattern(pDM_Odm, pdm_sat_table->update_beam_codeword, pdm_sat_table->data_codeword_bit_num); + + #if DEV_BUS_TYPE != RT_PCI_INTERFACE + /*ODM_StallExecution(pdm_sat_table->latch_time);*/ + pdm_sat_table->pkt_skip_statistic_en = 0; + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pkt_skip_statistic_en = (( %d )), latch_time = (( %d ))\n", pdm_sat_table->pkt_skip_statistic_en, pdm_sat_table->latch_time)); +} + +VOID +phydm_beam_decision_workitem_callback( + IN PVOID pContext + ) +{ + PADAPTER pAdapter = (PADAPTER)pContext; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] Beam decision Workitem Callback\n")); + odm_FastAntTraining_hl_smart_antenna_type1(pDM_Odm); +} +#endif + +#endif /*#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1*/ + +VOID +ODM_AntDivInit( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + + + if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] Not Support Antenna Diversity Function\n")); + return; + } + //--- +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_2G) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[2G AntDiv Init]: Only Support 2G Antenna Diversity Function\n")); + if(!(pDM_Odm->SupportICType & ODM_ANTDIV_2G_SUPPORT_IC)) + return; + } + else if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_5G) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[5G AntDiv Init]: Only Support 5G Antenna Diversity Function\n")); + if(!(pDM_Odm->SupportICType & ODM_ANTDIV_5G_SUPPORT_IC)) + return; + } + else if(pDM_FatTable->AntDiv_2G_5G == (ODM_ANTDIV_2G|ODM_ANTDIV_5G)) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[2G & 5G AntDiv Init]:Support Both 2G & 5G Antenna Diversity Function\n")); + } + +#endif + //--- + + //2 [--General---] + pDM_Odm->antdiv_period=0; + + pDM_FatTable->bBecomeLinked =FALSE; + pDM_FatTable->AntDiv_OnOff =0xff; + + //3 - AP - + #if (DM_ODM_SUPPORT_TYPE == ODM_AP) + + #ifdef BEAMFORMING_SUPPORT + #if(DM_ODM_SUPPORT_TYPE == ODM_AP) + odm_BDC_Init(pDM_Odm); + #endif + #endif + + //3 - WIN - + #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + pDM_SWAT_Table->Ant5G = MAIN_ANT; + pDM_SWAT_Table->Ant2G = MAIN_ANT; + pDM_FatTable->CCK_counter_main=0; + pDM_FatTable->CCK_counter_aux=0; + pDM_FatTable->OFDM_counter_main=0; + pDM_FatTable->OFDM_counter_aux=0; + #endif + + //2 [---Set MAIN_ANT as default antenna if Auto-Ant enable---] + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + + pDM_Odm->AntType = ODM_AUTO_ANT; + + pDM_FatTable->RxIdleAnt = 0xff; /*to make RX-idle-antenna will be updated absolutly*/ + ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT); + + //2 [---Set TX Antenna---] + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); + + + //2 [--88E---] + if(pDM_Odm->SupportICType == ODM_RTL8188E) + { + #if (RTL8188E_SUPPORT == 1) + //pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; + //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; + //pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV; + + if( (pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV) && (pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV) && (pDM_Odm->AntDivType != CG_TRX_SMART_ANTDIV)) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 88E Not Supprrt This AntDiv Type\n")); + pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); + return; + } + + if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) + odm_RX_HWAntDiv_Init_88E(pDM_Odm); + else if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) + odm_TRX_HWAntDiv_Init_88E(pDM_Odm); + #if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) + else if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV) + odm_Smart_HWAntDiv_Init_88E(pDM_Odm); + #endif + #endif + } + + //2 [--92E---] + #if (RTL8192E_SUPPORT == 1) + else if(pDM_Odm->SupportICType == ODM_RTL8192E) + { + //pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; + //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; + //pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV; + + if( (pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV) && (pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV) && (pDM_Odm->AntDivType != CG_TRX_SMART_ANTDIV)) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8192E Not Supprrt This AntDiv Type\n")); + pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); + return; + } + + if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) + odm_RX_HWAntDiv_Init_92E(pDM_Odm); + else if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) + odm_TRX_HWAntDiv_Init_92E(pDM_Odm); + #if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) + else if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV) + odm_Smart_HWAntDiv_Init_92E(pDM_Odm); + #endif + + } + #endif + + //2 [--8723B---] + #if (RTL8723B_SUPPORT == 1) + else if(pDM_Odm->SupportICType == ODM_RTL8723B) + { + //pDM_Odm->AntDivType = S0S1_SW_ANTDIV; + //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; + + if(pDM_Odm->AntDivType != S0S1_SW_ANTDIV && pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8723B Not Supprrt This AntDiv Type\n")); + pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); + return; + } + + if( pDM_Odm->AntDivType==S0S1_SW_ANTDIV) + odm_S0S1_SWAntDiv_Init_8723B(pDM_Odm); + else if(pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV) + odm_TRX_HWAntDiv_Init_8723B(pDM_Odm); + } + #endif + + //2 [--8811A 8821A---] + #if (RTL8821A_SUPPORT == 1) + else if(pDM_Odm->SupportICType == ODM_RTL8821) + { + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + pDM_Odm->AntDivType = HL_SW_SMART_ANT_TYPE1; + + if (pDM_Odm->AntDivType == HL_SW_SMART_ANT_TYPE1) { + + odm_TRX_HWAntDiv_Init_8821A(pDM_Odm); + phydm_hl_smart_ant_type1_init_8821a(pDM_Odm); + } else + #endif + { + /*pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;*/ + pDM_Odm->AntDivType = S0S1_SW_ANTDIV; + + if (pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV && pDM_Odm->AntDivType != S0S1_SW_ANTDIV) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Return!!!] 8821A & 8811A Not Supprrt This AntDiv Type\n")); + pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); + return; + } + if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) + odm_TRX_HWAntDiv_Init_8821A(pDM_Odm); + else if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) + odm_S0S1_SWAntDiv_Init_8821A(pDM_Odm); + } + } + #endif + + //2 [--8881A---] + #if (RTL8881A_SUPPORT == 1) + else if(pDM_Odm->SupportICType == ODM_RTL8881A) + { + //pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; + //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; + + if(pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV && pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8881A Not Supprrt This AntDiv Type\n")); + pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); + return; + } + if(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) + odm_RX_HWAntDiv_Init_8881A(pDM_Odm); + else if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) + odm_TRX_HWAntDiv_Init_8881A(pDM_Odm); + } + #endif + + //2 [--8812---] + #if (RTL8812A_SUPPORT == 1) + else if(pDM_Odm->SupportICType == ODM_RTL8812) + { + //pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; + + if( pDM_Odm->AntDivType != CG_TRX_HW_ANTDIV) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] 8812A Not Supprrt This AntDiv Type\n")); + pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); + return; + } + odm_TRX_HWAntDiv_Init_8812A(pDM_Odm); + } + #endif + + /*[--8188F---]*/ + #if (RTL8188F_SUPPORT == 1) + else if (pDM_Odm->SupportICType == ODM_RTL8188F) { + + pDM_Odm->AntDivType = S0S1_SW_ANTDIV; + odm_S0S1_SWAntDiv_Init_8188F(pDM_Odm); + } + #endif + /* + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** SupportICType=[%lu]\n",pDM_Odm->SupportICType)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** AntDiv SupportAbility=[%lu]\n",(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)>>6)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** AntDiv Type=[%d]\n",pDM_Odm->AntDivType)); + */ +} + +VOID +ODM_AntDiv( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER pAdapter = pDM_Odm->Adapter; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); + #endif + + if(*pDM_Odm->pBandType == ODM_BAND_5G ) + { + if(pDM_FatTable->idx_AntDiv_counter_5G < pDM_Odm->antdiv_period ) + { + pDM_FatTable->idx_AntDiv_counter_5G++; + return; + } + else + pDM_FatTable->idx_AntDiv_counter_5G=0; + } + else if(*pDM_Odm->pBandType == ODM_BAND_2_4G ) + { + if(pDM_FatTable->idx_AntDiv_counter_2G < pDM_Odm->antdiv_period ) + { + pDM_FatTable->idx_AntDiv_counter_2G++; + return; + } + else + pDM_FatTable->idx_AntDiv_counter_2G=0; + } + + //---------- + if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[Return!!!] Not Support Antenna Diversity Function\n")); + return; + } + + //---------- +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + + if (pDM_FatTable->enable_ctrl_frame_antdiv) { + + if ((pDM_Odm->data_frame_num <= 10) && (pDM_Odm->bLinked)) + pDM_FatTable->use_ctrl_frame_antdiv = 1; + else + pDM_FatTable->use_ctrl_frame_antdiv = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("use_ctrl_frame_antdiv = (( %d )), data_frame_num = (( %d ))\n", pDM_FatTable->use_ctrl_frame_antdiv, pDM_Odm->data_frame_num)); + pDM_Odm->data_frame_num = 0; + } + + if(pAdapter->MgntInfo.AntennaTest) + return; + + { + #if (BEAMFORMING_SUPPORT == 1) + BEAMFORMING_CAP BeamformCap = (pDM_Odm->BeamformingInfo.BeamformCap); + + if( BeamformCap & BEAMFORMEE_CAP ) // BFmee On && Div On -> Div Off + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ AntDiv : OFF ] BFmee ==1 \n")); + if(pDM_FatTable->fix_ant_bfee == 0) + { + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + pDM_FatTable->fix_ant_bfee = 1; + } + return; + } + else // BFmee Off && Div Off -> Div On + { + if((pDM_FatTable->fix_ant_bfee == 1) && pDM_Odm->bLinked) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ AntDiv : ON ] BFmee ==0\n")); + if((pDM_Odm->AntDivType!=S0S1_SW_ANTDIV) ) + odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); + + pDM_FatTable->fix_ant_bfee = 0; + } + } + #endif + } +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + //----------just for fool proof + + if(pDM_Odm->antdiv_rssi) + pDM_Odm->DebugComponents |= ODM_COMP_ANT_DIV; + else + pDM_Odm->DebugComponents &= ~ODM_COMP_ANT_DIV; + + if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_2G) + { + //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 2G AntDiv Running ]\n")); + if(!(pDM_Odm->SupportICType & ODM_ANTDIV_2G_SUPPORT_IC)) + return; + } + else if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_5G) + { + //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 5G AntDiv Running ]\n")); + if(!(pDM_Odm->SupportICType & ODM_ANTDIV_5G_SUPPORT_IC)) + return; + } + //else if(pDM_FatTable->AntDiv_2G_5G == (ODM_ANTDIV_2G|ODM_ANTDIV_5G)) + //{ + //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 2G & 5G AntDiv Running ]\n")); + //} +#endif + + //---------- + + if (pDM_Odm->antdiv_select==1) + pDM_Odm->AntType = ODM_FIX_MAIN_ANT; + else if (pDM_Odm->antdiv_select==2) + pDM_Odm->AntType = ODM_FIX_AUX_ANT; + else //if (pDM_Odm->antdiv_select==0) + pDM_Odm->AntType = ODM_AUTO_ANT; + + //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("AntType= (( %d )) , pre_AntType= (( %d )) \n",pDM_Odm->AntType,pDM_Odm->pre_AntType)); + + if(pDM_Odm->AntType != ODM_AUTO_ANT) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Fix Antenna at (( %s ))\n",(pDM_Odm->AntType == ODM_FIX_MAIN_ANT)?"MAIN":"AUX")); + + if(pDM_Odm->AntType != pDM_Odm->pre_AntType) + { + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_REG); + + if(pDM_Odm->AntType == ODM_FIX_MAIN_ANT) + ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT); + else if(pDM_Odm->AntType == ODM_FIX_AUX_ANT) + ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT); + } + pDM_Odm->pre_AntType=pDM_Odm->AntType; + return; + } + else + { + if(pDM_Odm->AntType != pDM_Odm->pre_AntType) + { + odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); + /*odm_Tx_By_TxDesc_or_Reg(pDM_Odm, TX_BY_DESC);*/ + } + pDM_Odm->pre_AntType=pDM_Odm->AntType; + } + + + //3 ----------------------------------------------------------------------------------------------------------- + //2 [--88E---] + if(pDM_Odm->SupportICType == ODM_RTL8188E) + { + #if (RTL8188E_SUPPORT == 1) + if(pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV ||pDM_Odm->AntDivType==CGCS_RX_HW_ANTDIV) + odm_HW_AntDiv(pDM_Odm); + + #if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) + else if (pDM_Odm->AntDivType==CG_TRX_SMART_ANTDIV) + odm_FastAntTraining(pDM_Odm); + #endif + + #endif + + } + //2 [--92E---] + #if (RTL8192E_SUPPORT == 1) + else if(pDM_Odm->SupportICType == ODM_RTL8192E) + { + if(pDM_Odm->AntDivType==CGCS_RX_HW_ANTDIV || pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV) + odm_HW_AntDiv(pDM_Odm); + + #if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) + else if (pDM_Odm->AntDivType==CG_TRX_SMART_ANTDIV) + odm_FastAntTraining(pDM_Odm); + #endif + + } + #endif + + #if (RTL8723B_SUPPORT == 1) + //2 [--8723B---] + else if(pDM_Odm->SupportICType == ODM_RTL8723B) + { + if (phydm_IsBtEnable_8723b(pDM_Odm)) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[BT is enable!!!] AntDiv: OFF\n")); + if (pDM_FatTable->bBecomeLinked == TRUE) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Set REG 948[9:6]=0x0\n")); + if (pDM_Odm->SupportICType == ODM_RTL8723B) + ODM_SetBBReg(pDM_Odm, 0x948 , BIT9|BIT8|BIT7|BIT6, 0x0); + + pDM_FatTable->bBecomeLinked = FALSE; + } + } else { + if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) { + + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_S0S1_SwAntDiv(pDM_Odm, SWAW_STEP_PEEK); + #endif + } else if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) + odm_HW_AntDiv(pDM_Odm); + } + } + #endif + + //2 [--8821A---] + #if (RTL8821A_SUPPORT == 1) + else if (pDM_Odm->SupportICType == ODM_RTL8821) + { + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + if (pDM_Odm->AntDivType == HL_SW_SMART_ANT_TYPE1) { + + if (pdm_sat_table->fix_beam_pattern_en != 0) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n", pdm_sat_table->fix_beam_pattern_codeword)); + /*return;*/ + } else { + /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ SmartAnt ] AntDivType = HL_SW_SMART_ANT_TYPE1\n"));*/ + odm_FastAntTraining_hl_smart_antenna_type1(pDM_Odm); + } + + } else + #endif + { + if (!pDM_Odm->bBtEnabled) /*BT disabled*/ + { + if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) { + pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [S0S1_SW_ANTDIV] -> [CG_TRX_HW_ANTDIV]\n")); + /*ODM_SetBBReg(pDM_Odm, 0x8D4 , BIT24, 1); */ + if (pDM_FatTable->bBecomeLinked == TRUE) + odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); + } + + } else { /*BT enabled*/ + + if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) { + pDM_Odm->AntDivType = S0S1_SW_ANTDIV; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [CG_TRX_HW_ANTDIV] -> [S0S1_SW_ANTDIV]\n")); + /*ODM_SetBBReg(pDM_Odm, 0x8D4 , BIT24, 0);*/ + odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF); + } + } + + if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) { + + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_S0S1_SwAntDiv(pDM_Odm, SWAW_STEP_PEEK); + #endif + } else if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) + odm_HW_AntDiv(pDM_Odm); + } + } + #endif + + //2 [--8881A---] + #if (RTL8881A_SUPPORT == 1) + else if(pDM_Odm->SupportICType == ODM_RTL8881A) + odm_HW_AntDiv(pDM_Odm); + #endif + + //2 [--8812A---] + #if (RTL8812A_SUPPORT == 1) + else if(pDM_Odm->SupportICType == ODM_RTL8812) + odm_HW_AntDiv(pDM_Odm); + #endif + + #if (RTL8188F_SUPPORT == 1) + /* [--8188F---]*/ + else if (pDM_Odm->SupportICType == ODM_RTL8188F) { + + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_S0S1_SwAntDiv(pDM_Odm, SWAW_STEP_PEEK); + #endif + } + #endif + +} + + +VOID +odm_AntselStatistics( + IN PVOID pDM_VOID, + IN u1Byte antsel_tr_mux, + IN u4Byte MacId, + IN u4Byte utility, + IN u1Byte method + + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + if(method==RSSI_METHOD) + { + if(antsel_tr_mux == ANT1_2G) + { + pDM_FatTable->MainAnt_Sum[MacId]+=utility; + pDM_FatTable->MainAnt_Cnt[MacId]++; + } + else + { + pDM_FatTable->AuxAnt_Sum[MacId]+=utility; + pDM_FatTable->AuxAnt_Cnt[MacId]++; + } + } + #ifdef ODM_EVM_ENHANCE_ANTDIV + else if(method==EVM_METHOD) + { + if(antsel_tr_mux == ANT1_2G) + { + pDM_FatTable->MainAntEVM_Sum[MacId]+=(utility<<5); + pDM_FatTable->MainAntEVM_Cnt[MacId]++; + } + else + { + pDM_FatTable->AuxAntEVM_Sum[MacId]+=(utility<<5); + pDM_FatTable->AuxAntEVM_Cnt[MacId]++; + } + } + else if(method==CRC32_METHOD) + { + if(utility==0) + pDM_FatTable->CRC32_Fail_Cnt++; + else + pDM_FatTable->CRC32_Ok_Cnt+=utility; + } + #endif +} + + +VOID +ODM_Process_RSSIForAntDiv( + IN OUT PVOID pDM_VOID, + IN PVOID p_phy_info_void, + IN PVOID p_pkt_info_void + //IN PODM_PHY_INFO_T pPhyInfo, + //IN PODM_PACKET_INFO_T pPktinfo + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PODM_PHY_INFO_T pPhyInfo=(PODM_PHY_INFO_T)p_phy_info_void; + PODM_PACKET_INFO_T pPktinfo=(PODM_PACKET_INFO_T)p_pkt_info_void; + u1Byte isCCKrate=0,CCKMaxRate=ODM_RATE11M; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + pSAT_T pdm_sat_table = &(pDM_Odm->dm_sat_table); + u4Byte beam_tmp; + #endif + + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + u4Byte RxPower_Ant0, RxPower_Ant1; + u4Byte RxEVM_Ant0, RxEVM_Ant1; + #else + u1Byte RxPower_Ant0, RxPower_Ant1; + u1Byte RxEVM_Ant0, RxEVM_Ant1; + #endif + + CCKMaxRate=ODM_RATE11M; + isCCKrate = (pPktinfo->DataRate <= CCKMaxRate)?TRUE:FALSE; + + if ((pDM_Odm->SupportICType & (ODM_RTL8192E|ODM_RTL8812)) && (pPktinfo->DataRate > CCKMaxRate)) + { + RxPower_Ant0 = pPhyInfo->RxMIMOSignalStrength[0]; + RxPower_Ant1= pPhyInfo->RxMIMOSignalStrength[1]; + + RxEVM_Ant0 =pPhyInfo->RxMIMOSignalQuality[0]; + RxEVM_Ant1 =pPhyInfo->RxMIMOSignalQuality[1]; + } + else + RxPower_Ant0=pPhyInfo->RxPWDBAll; + + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + if (pDM_Odm->AntDivType == HL_SW_SMART_ANT_TYPE1) + { + if ((pDM_Odm->SupportICType & ODM_HL_SMART_ANT_TYPE1_SUPPORT) && + (pPktinfo->bPacketToSelf) && + (pDM_FatTable->FAT_State == FAT_TRAINING_STATE) + ) { + + if (pdm_sat_table->pkt_skip_statistic_en == 0) { + /* + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", + pPktinfo->StationID, pDM_FatTable->antsel_rx_keep_0, pDM_FatTable->hw_antsw_occur, pdm_sat_table->fast_training_beam_num, RxPower_Ant0)); + */ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antsel_pathA = ((%d)), bPacketToSelf = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n", + pPktinfo->StationID, pDM_FatTable->antsel_rx_keep_0, pPktinfo->bPacketToSelf, pdm_sat_table->fast_training_beam_num, RxPower_Ant0)); + + + pdm_sat_table->pkt_rssi_sum[pDM_FatTable->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num] += RxPower_Ant0; + pdm_sat_table->pkt_rssi_cnt[pDM_FatTable->antsel_rx_keep_0][pdm_sat_table->fast_training_beam_num]++; + pdm_sat_table->pkt_counter++; + + /*swich beam every N pkt*/ + if ((pdm_sat_table->pkt_counter) >= (pdm_sat_table->per_beam_training_pkt_num)) { + + pdm_sat_table->pkt_counter = 0; + beam_tmp = pdm_sat_table->fast_training_beam_num; + + if (pdm_sat_table->fast_training_beam_num >= (pdm_sat_table->beam_patten_num_each_ant-1)) { + + pDM_FatTable->FAT_State = FAT_DECISION_STATE; + + #if DEV_BUS_TYPE == RT_PCI_INTERFACE + odm_FastAntTraining_hl_smart_antenna_type1(pDM_Odm); + #else + ODM_ScheduleWorkItem(&pdm_sat_table->hl_smart_antenna_decision_workitem); + #endif + + + } else { + pdm_sat_table->fast_training_beam_num++; + phydm_set_all_ant_same_beam_num(pDM_Odm); + + pDM_FatTable->FAT_State = FAT_TRAINING_STATE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Update Beam_num (( %d )) -> (( %d ))\n", beam_tmp, pdm_sat_table->fast_training_beam_num)); + } + } + } + } + } else + #endif + if (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV) { + if( (pDM_Odm->SupportICType & ODM_SMART_ANT_SUPPORT) && (pPktinfo->bPacketToSelf) && (pDM_FatTable->FAT_State == FAT_TRAINING_STATE) )//(pPktinfo->bPacketMatchBSSID && (!pPktinfo->bPacketBeacon)) + { + u1Byte antsel_tr_mux; + antsel_tr_mux = (pDM_FatTable->antsel_rx_keep_2<<2) |(pDM_FatTable->antsel_rx_keep_1 <<1) |pDM_FatTable->antsel_rx_keep_0; + pDM_FatTable->antSumRSSI[antsel_tr_mux] += RxPower_Ant0; + pDM_FatTable->antRSSIcnt[antsel_tr_mux]++; + } + } + else //AntDivType != CG_TRX_SMART_ANTDIV + { + if ((pDM_Odm->SupportICType & ODM_ANTDIV_SUPPORT) && (pPktinfo->bPacketToSelf || pDM_FatTable->use_ctrl_frame_antdiv)) + { + if(pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E) + { + odm_AntselStatistics(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID,RxPower_Ant0,RSSI_METHOD); + + #ifdef ODM_EVM_ENHANCE_ANTDIV + if(!isCCKrate) + { + odm_AntselStatistics(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID,RxEVM_Ant0,EVM_METHOD); + } + #endif + } + else// SupportICType == ODM_RTL8821 and ODM_RTL8723B and ODM_RTL8812) + { + if(isCCKrate && (pDM_Odm->AntDivType == S0S1_SW_ANTDIV)) + { + pDM_FatTable->antsel_rx_keep_0 = (pDM_FatTable->RxIdleAnt == MAIN_ANT) ? ANT1_2G : ANT2_2G; + + + if(pDM_FatTable->antsel_rx_keep_0==ANT1_2G) + pDM_FatTable->CCK_counter_main++; + else// if(pDM_FatTable->antsel_rx_keep_0==ANT2_2G) + pDM_FatTable->CCK_counter_aux++; + + odm_AntselStatistics(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID, RxPower_Ant0,RSSI_METHOD); + } + else + { + if(pDM_FatTable->antsel_rx_keep_0==ANT1_2G) + pDM_FatTable->OFDM_counter_main++; + else// if(pDM_FatTable->antsel_rx_keep_0==ANT2_2G) + pDM_FatTable->OFDM_counter_aux++; + odm_AntselStatistics(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID, RxPower_Ant0,RSSI_METHOD); + } + } + } + } + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("isCCKrate=%d, PWDB_ALL=%d\n",isCCKrate, pPhyInfo->RxPWDBAll)); + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=3'b%d%d%d\n",pDM_FatTable->antsel_rx_keep_2, pDM_FatTable->antsel_rx_keep_1, pDM_FatTable->antsel_rx_keep_0)); +} + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) +VOID +ODM_SetTxAntByTxInfo( + IN PVOID pDM_VOID, + IN pu1Byte pDesc, + IN u1Byte macId + + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) + return; + + if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) + return; + + + if (pDM_Odm->SupportICType == ODM_RTL8723B) { +#if (RTL8723B_SUPPORT == 1) + SET_TX_DESC_ANTSEL_A_8723B(pDesc, pDM_FatTable->antsel_a[macId]); + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8723B] SetTxAntByTxInfo_WIN: MacID=%d, antsel_tr_mux=3'b%d%d%d\n", + macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));*/ +#endif + } else if (pDM_Odm->SupportICType == ODM_RTL8821) { +#if (RTL8821A_SUPPORT == 1) + SET_TX_DESC_ANTSEL_A_8812(pDesc, pDM_FatTable->antsel_a[macId]); + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8821A] SetTxAntByTxInfo_WIN: MacID=%d, antsel_tr_mux=3'b%d%d%d\n", + macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));*/ +#endif + } else if (pDM_Odm->SupportICType == ODM_RTL8188E) { +#if (RTL8188E_SUPPORT == 1) + SET_TX_DESC_ANTSEL_A_88E(pDesc, pDM_FatTable->antsel_a[macId]); + SET_TX_DESC_ANTSEL_B_88E(pDesc, pDM_FatTable->antsel_b[macId]); + SET_TX_DESC_ANTSEL_C_88E(pDesc, pDM_FatTable->antsel_c[macId]); + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8188E] SetTxAntByTxInfo_WIN: MacID=%d, antsel_tr_mux=3'b%d%d%d\n", + macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));*/ +#endif + } +} +#elif(DM_ODM_SUPPORT_TYPE == ODM_AP) + +VOID +ODM_SetTxAntByTxInfo( + struct rtl8192cd_priv *priv, + struct tx_desc *pdesc, + unsigned short aid +) +{ + pFAT_T pDM_FatTable = &priv->pshare->_dmODM.DM_FatTable; + u4Byte SupportICType = priv->pshare->_dmODM.SupportICType; + + if (SupportICType == ODM_RTL8881A) { + /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__); */ + pdesc->Dword6 &= set_desc(~(BIT(18)|BIT(17)|BIT(16))); + pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_a[aid]<<16); + } else if (SupportICType == ODM_RTL8192E) { + /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8192E******\n",__FUNCTION__,__LINE__); */ + pdesc->Dword6 &= set_desc(~(BIT(18)|BIT(17)|BIT(16))); + pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_a[aid]<<16); + } else if (SupportICType == ODM_RTL8188E) { + /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8188E******\n",__FUNCTION__,__LINE__);*/ + pdesc->Dword2 &= set_desc(~BIT(24)); + pdesc->Dword2 &= set_desc(~BIT(25)); + pdesc->Dword7 &= set_desc(~BIT(29)); + + pdesc->Dword2 |= set_desc(pDM_FatTable->antsel_a[aid]<<24); + pdesc->Dword2 |= set_desc(pDM_FatTable->antsel_b[aid]<<25); + pdesc->Dword7 |= set_desc(pDM_FatTable->antsel_c[aid]<<29); + + + } else if (SupportICType == ODM_RTL8812) { + /*[path-A]*/ + /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__);*/ + + pdesc->Dword6 &= set_desc(~BIT(16)); + pdesc->Dword6 &= set_desc(~BIT(17)); + pdesc->Dword6 &= set_desc(~BIT(18)); + + pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_a[aid]<<16); + pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_b[aid]<<17); + pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_c[aid]<<18); + + } +} +#endif + + +VOID +ODM_AntDiv_Config( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("WIN Config Antenna Diversity\n")); + if(pDM_Odm->SupportICType==ODM_RTL8723B) + { + if((!pDM_Odm->DM_SWAT_Table.ANTA_ON || !pDM_Odm->DM_SWAT_Table.ANTB_ON)) + pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); + } +#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + /* do noting, branch only */ +#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("AP Config Antenna Diversity\n")); + + //2 [ NOT_SUPPORT_ANTDIV ] + #if(defined(CONFIG_NOT_SUPPORT_ANTDIV)) + pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Disable AntDiv function] : Not Support 2.4G & 5G Antenna Diversity\n")); + + //2 [ 2G&5G_SUPPORT_ANTDIV ] + #elif(defined(CONFIG_2G5G_SUPPORT_ANTDIV)) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Enable AntDiv function] : 2.4G & 5G Support Antenna Diversity Simultaneously \n")); + pDM_FatTable->AntDiv_2G_5G = (ODM_ANTDIV_2G|ODM_ANTDIV_5G); + + if(pDM_Odm->SupportICType & ODM_ANTDIV_SUPPORT) + pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV; + if(*pDM_Odm->pBandType == ODM_BAND_5G ) + { + #if ( defined(CONFIG_5G_CGCS_RX_DIVERSITY) ) + pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n")); + panic_printk("[ 5G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n"); + #elif( defined(CONFIG_5G_CG_TRX_DIVERSITY)||defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A)) + pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CG_TRX_HW_ANTDIV\n")); + panic_printk("[ 5G] : AntDiv Type = CG_TRX_HW_ANTDIV\n"); + #elif( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) + pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CG_SMART_ANTDIV\n")); + #elif( defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY) ) + pDM_Odm->AntDivType = S0S1_SW_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = S0S1_SW_ANTDIV\n")); + #endif + } + else if(*pDM_Odm->pBandType == ODM_BAND_2_4G ) + { + #if ( defined(CONFIG_2G_CGCS_RX_DIVERSITY) ) + pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n")); + #elif( defined(CONFIG_2G_CG_TRX_DIVERSITY) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A)) + pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CG_TRX_HW_ANTDIV\n")); + #elif( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) + pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CG_SMART_ANTDIV\n")); + #elif( defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY) ) + pDM_Odm->AntDivType = S0S1_SW_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = S0S1_SW_ANTDIV\n")); + #endif + } + + //2 [ 5G_SUPPORT_ANTDIV ] + #elif(defined(CONFIG_5G_SUPPORT_ANTDIV)) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n")); + panic_printk("[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n"); + pDM_FatTable->AntDiv_2G_5G = (ODM_ANTDIV_5G); + if(*pDM_Odm->pBandType == ODM_BAND_5G ) + { + if(pDM_Odm->SupportICType & ODM_ANTDIV_5G_SUPPORT_IC) + pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV; + #if ( defined(CONFIG_5G_CGCS_RX_DIVERSITY) ) + pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n")); + panic_printk("[ 5G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n"); + #elif( defined(CONFIG_5G_CG_TRX_DIVERSITY) ) + pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; + panic_printk("[ 5G] : AntDiv Type = CG_TRX_HW_ANTDIV\n"); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CG_TRX_HW_ANTDIV\n")); + #elif( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) + pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CG_SMART_ANTDIV\n")); + #elif( defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY) ) + pDM_Odm->AntDivType = S0S1_SW_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = S0S1_SW_ANTDIV\n")); + #endif + } + else if(*pDM_Odm->pBandType == ODM_BAND_2_4G ) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Not Support 2G AntDivType\n")); + pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); + } + + //2 [ 2G_SUPPORT_ANTDIV ] + #elif(defined(CONFIG_2G_SUPPORT_ANTDIV)) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Enable AntDiv function] : Only 2.4G Support Antenna Diversity\n")); + pDM_FatTable->AntDiv_2G_5G = (ODM_ANTDIV_2G); + if(*pDM_Odm->pBandType == ODM_BAND_2_4G ) + { + if(pDM_Odm->SupportICType & ODM_ANTDIV_2G_SUPPORT_IC) + pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV; + #if ( defined(CONFIG_2G_CGCS_RX_DIVERSITY) ) + pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n")); + #elif( defined(CONFIG_2G_CG_TRX_DIVERSITY) ) + pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CG_TRX_HW_ANTDIV\n")); + #elif( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) + pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CG_SMART_ANTDIV\n")); + #elif( defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY) ) + pDM_Odm->AntDivType = S0S1_SW_ANTDIV; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = S0S1_SW_ANTDIV\n")); + #endif + } + else if(*pDM_Odm->pBandType == ODM_BAND_5G ) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Not Support 5G AntDivType\n")); + pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV); + } + #endif +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SupportAbility = (( %x ))\n", pDM_Odm->SupportAbility )); + +} + + +VOID +ODM_AntDivTimers( + IN PVOID pDM_VOID, + IN u1Byte state + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + if(state==INIT_ANTDIV_TIMMER) + { + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + ODM_InitializeTimer(pDM_Odm, &(pDM_Odm->DM_SWAT_Table.phydm_SwAntennaSwitchTimer), + (RT_TIMER_CALL_BACK)ODM_SW_AntDiv_Callback, NULL, "phydm_SwAntennaSwitchTimer"); + #elif ( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) + ODM_InitializeTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer, + (RT_TIMER_CALL_BACK)odm_FastAntTrainingCallback, NULL, "FastAntTrainingTimer"); + #endif + + #ifdef ODM_EVM_ENHANCE_ANTDIV + ODM_InitializeTimer(pDM_Odm,&pDM_Odm->EVM_FastAntTrainingTimer, + (RT_TIMER_CALL_BACK)odm_EVM_FastAntTrainingCallback, NULL, "EVM_FastAntTrainingTimer"); + #endif + } + else if(state==CANCEL_ANTDIV_TIMMER) + { + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + ODM_CancelTimer(pDM_Odm, &(pDM_Odm->DM_SWAT_Table.phydm_SwAntennaSwitchTimer)); + #elif ( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) + ODM_CancelTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer); + #endif + + #ifdef ODM_EVM_ENHANCE_ANTDIV + ODM_CancelTimer(pDM_Odm,&pDM_Odm->EVM_FastAntTrainingTimer); + #endif + } + else if(state==RELEASE_ANTDIV_TIMMER) + { + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + ODM_ReleaseTimer(pDM_Odm, &(pDM_Odm->DM_SWAT_Table.phydm_SwAntennaSwitchTimer)); + #elif ( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) + ODM_ReleaseTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer); + #endif + + #ifdef ODM_EVM_ENHANCE_ANTDIV + ODM_ReleaseTimer(pDM_Odm,&pDM_Odm->EVM_FastAntTrainingTimer); + #endif + } + +} + +#endif /*#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))*/ + +VOID +ODM_AntDivReset( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (pDM_Odm->AntDivType == S0S1_SW_ANTDIV) + { + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_S0S1_SWAntDiv_Reset(pDM_Odm); + #endif + } + +} + +VOID +odm_AntennaDiversityInit( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + if(pDM_Odm->mp_mode == TRUE) + return; + + #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + ODM_AntDiv_Config(pDM_Odm); + ODM_AntDivInit(pDM_Odm); + #endif +} + +VOID +odm_AntennaDiversity( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + if(pDM_Odm->mp_mode == TRUE) + return; + + #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + ODM_AntDiv(pDM_Odm); + #endif +} + + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_antdiv.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_antdiv.h new file mode 100644 index 000000000..83b6353f5 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_antdiv.h @@ -0,0 +1,567 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMANTDIV_H__ +#define __PHYDMANTDIV_H__ + +/*#define ANTDIV_VERSION "2.0" //2014.11.04*/ +/*#define ANTDIV_VERSION "2.1" //2015.01.13 Dino*/ +/*#define ANTDIV_VERSION "2.2" 2015.01.16 Dino*/ +/*#define ANTDIV_VERSION "3.1" 2015.07.29 YuChen, remove 92c 92d 8723a*/ +/*#define ANTDIV_VERSION "3.2" 2015.08.11 Stanley, disable antenna diversity when BT is enable for 8723B*/ +/*#define ANTDIV_VERSION "3.3" 2015.08.12 Stanley. 8723B does not need to check the antenna is control by BT, + because antenna diversity only works when BT is disable or radio off*/ +#define ANTDIV_VERSION "3.4" /*2015.08.28 Dino 1.Add 8821A Smart Antenna 2. Add 8188F SW S0S1 Antenna Diversity*/ + +//1 ============================================================ +//1 Definition +//1 ============================================================ + +#define MAIN_ANT 1 +#define AUX_ANT 2 + +#define ANT1_2G 0 // = ANT2_5G +#define ANT2_2G 1 // = ANT1_5G +/*smart antenna*/ +#define SUPPORT_RF_PATH_NUM 4 +#define SUPPORT_BEAM_PATTERN_NUM 4 + + +//Antenna Diversty Control Type +#define ODM_AUTO_ANT 0 +#define ODM_FIX_MAIN_ANT 1 +#define ODM_FIX_AUX_ANT 2 + +#define ODM_N_ANTDIV_SUPPORT (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8188F) +#define ODM_AC_ANTDIV_SUPPORT (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812) +#define ODM_ANTDIV_SUPPORT (ODM_N_ANTDIV_SUPPORT|ODM_AC_ANTDIV_SUPPORT) +#define ODM_SMART_ANT_SUPPORT (ODM_RTL8188E|ODM_RTL8192E) +#define ODM_HL_SMART_ANT_TYPE1_SUPPORT (ODM_RTL8821) + +#define ODM_ANTDIV_2G_SUPPORT_IC (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8881A|ODM_RTL8188F) +#define ODM_ANTDIV_5G_SUPPORT_IC (ODM_RTL8821|ODM_RTL8881A|ODM_RTL8812) + +#define ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC (ODM_RTL8192E) + +#define ODM_ANTDIV_2G BIT0 +#define ODM_ANTDIV_5G BIT1 + +#define ANTDIV_ON 1 +#define ANTDIV_OFF 0 + +#define FAT_ON 1 +#define FAT_OFF 0 + +#define TX_BY_DESC 1 +#define TX_BY_REG 0 + +#define RSSI_METHOD 0 +#define EVM_METHOD 1 +#define CRC32_METHOD 2 + +#define INIT_ANTDIV_TIMMER 0 +#define CANCEL_ANTDIV_TIMMER 1 +#define RELEASE_ANTDIV_TIMMER 2 + +#define CRC32_FAIL 1 +#define CRC32_OK 0 + +#define Evm_RSSI_TH_High 25 +#define Evm_RSSI_TH_Low 20 + +#define NORMAL_STATE_MIAN 1 +#define NORMAL_STATE_AUX 2 +#define TRAINING_STATE 3 + +#define FORCE_RSSI_DIFF 10 + +#define CSI_ON 1 +#define CSI_OFF 0 + +#define DIVON_CSIOFF 1 +#define DIVOFF_CSION 2 + +#define BDC_DIV_TRAIN_STATE 0 +#define BDC_BFer_TRAIN_STATE 1 +#define BDC_DECISION_STATE 2 +#define BDC_BF_HOLD_STATE 3 +#define BDC_DIV_HOLD_STATE 4 + +#define BDC_MODE_1 1 +#define BDC_MODE_2 2 +#define BDC_MODE_3 3 +#define BDC_MODE_4 4 +#define BDC_MODE_NULL 0xff + +/*SW S0S1 antenna diversity*/ +#define SWAW_STEP_INIT 0xff +#define SWAW_STEP_PEEK 0 +#define SWAW_STEP_DETERMINE 1 + +#define RSSI_CHECK_RESET_PERIOD 10 +#define RSSI_CHECK_THRESHOLD 50 + +/*Hong Lin Smart antenna*/ +#define HL_SMTANT_2WIRE_DATA_LEN 24 + +//1 ============================================================ +//1 structure +//1 ============================================================ + + +typedef struct _SW_Antenna_Switch_ +{ + u1Byte Double_chk_flag; /*If current antenna RSSI > "RSSI_CHECK_THRESHOLD", than check this antenna again*/ + u1Byte try_flag; + s4Byte PreRSSI; + u1Byte CurAntenna; + u1Byte PreAntenna; + u1Byte RSSI_Trying; + u1Byte reset_idx; + u1Byte Train_time; + u1Byte Train_time_flag; /*base on RSSI difference between two antennas*/ + RT_TIMER phydm_SwAntennaSwitchTimer; + u4Byte PktCnt_SWAntDivByCtrlFrame; + BOOLEAN bSWAntDivByCtrlFrame; + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #if USE_WORKITEM + RT_WORK_ITEM phydm_SwAntennaSwitchWorkitem; + #endif + #endif + + /* AntDect (Before link Antenna Switch check) need to be moved*/ + u2Byte Single_Ant_Counter; + u2Byte Dual_Ant_Counter; + u2Byte Aux_FailDetec_Counter; + u2Byte Retry_Counter; + u1Byte SWAS_NoLink_State; + u4Byte SWAS_NoLink_BK_Reg948; + BOOLEAN ANTA_ON; /*To indicate Ant A is or not*/ + BOOLEAN ANTB_ON; /*To indicate Ant B is on or not*/ + BOOLEAN Pre_Aux_FailDetec; + BOOLEAN RSSI_AntDect_bResult; + u1Byte Ant5G; + u1Byte Ant2G; + + +}SWAT_T, *pSWAT_T; + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) +typedef struct _BF_DIV_COEX_ +{ + BOOLEAN w_BFer_Client[ODM_ASSOCIATE_ENTRY_NUM]; + BOOLEAN w_BFee_Client[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte MA_rx_TP[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte MA_rx_TP_DIV[ODM_ASSOCIATE_ENTRY_NUM]; + + u1Byte BDCcoexType_wBfer; + u1Byte num_Txbfee_Client; + u1Byte num_Txbfer_Client; + u1Byte BDC_Try_counter; + u1Byte BDC_Hold_counter; + u1Byte BDC_Mode; + u1Byte BDC_active_Mode; + u1Byte BDC_state; + u1Byte BDC_RxIdleUpdate_counter; + u1Byte num_Client; + u1Byte pre_num_Client; + u1Byte num_BfTar; + u1Byte num_DivTar; + + BOOLEAN bAll_DivSta_Idle; + BOOLEAN bAll_BFSta_Idle; + BOOLEAN BDC_Try_flag; + BOOLEAN BF_pass; + BOOLEAN DIV_pass; +}BDC_T,*pBDC_T; +#endif +#endif + +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 +typedef struct _SMART_ANTENNA_TRAINNING_ { + u4Byte latch_time; + BOOLEAN pkt_skip_statistic_en; + u4Byte fix_beam_pattern_en; + u4Byte fix_training_num_en; + u4Byte fix_beam_pattern_codeword; + u4Byte update_beam_codeword; + u4Byte ant_num; /*number of smart beam antenna*/ + u4Byte beam_patten_num_each_ant;/*number of beam can be switched in each antenna*/ + u4Byte data_codeword_bit_num; + u4Byte per_beam_training_pkt_num; + u1Byte decision_holding_period; + u4Byte pkt_counter; + u4Byte fast_training_beam_num; + u4Byte pre_fast_training_beam_num; + u4Byte pkt_rssi_pre[SUPPORT_RF_PATH_NUM][SUPPORT_BEAM_PATTERN_NUM]; + u4Byte pkt_rssi_sum[8][SUPPORT_BEAM_PATTERN_NUM]; + u4Byte pkt_rssi_cnt[8][SUPPORT_BEAM_PATTERN_NUM]; + u4Byte rx_idle_beam[SUPPORT_RF_PATH_NUM]; + u4Byte pre_codeword; + BOOLEAN force_update_beam_en; + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + RT_WORK_ITEM hl_smart_antenna_workitem; + RT_WORK_ITEM hl_smart_antenna_decision_workitem; + #endif + +} SAT_T, *pSAT_T; +#endif + +typedef struct _FAST_ANTENNA_TRAINNING_ +{ + u1Byte Bssid[6]; + u1Byte antsel_rx_keep_0; + u1Byte antsel_rx_keep_1; + u1Byte antsel_rx_keep_2; + u1Byte antsel_rx_keep_3; + u4Byte antSumRSSI[7]; + u4Byte antRSSIcnt[7]; + u4Byte antAveRSSI[7]; + u1Byte FAT_State; + u4Byte TrainIdx; + u1Byte antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; + u1Byte antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; + u1Byte antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u1Byte RxIdleAnt; + u1Byte AntDiv_OnOff; + BOOLEAN bBecomeLinked; + u4Byte MinMaxRSSI; + u1Byte idx_AntDiv_counter_2G; + u1Byte idx_AntDiv_counter_5G; + u1Byte AntDiv_2G_5G; + u4Byte CCK_counter_main; + u4Byte CCK_counter_aux; + u4Byte OFDM_counter_main; + u4Byte OFDM_counter_aux; + + #ifdef ODM_EVM_ENHANCE_ANTDIV + u4Byte MainAntEVM_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte AuxAntEVM_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte MainAntEVM_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte AuxAntEVM_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + BOOLEAN EVM_method_enable; + u1Byte TargetAnt_EVM; + u1Byte TargetAnt_CRC32; + u1Byte TargetAnt_enhance; + u1Byte pre_TargetAnt_enhance; + u2Byte Main_MPDU_OK_cnt; + u2Byte Aux_MPDU_OK_cnt; + + u4Byte CRC32_Ok_Cnt; + u4Byte CRC32_Fail_Cnt; + u4Byte MainCRC32_Ok_Cnt; + u4Byte AuxCRC32_Ok_Cnt; + u4Byte MainCRC32_Fail_Cnt; + u4Byte AuxCRC32_Fail_Cnt; + #endif + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + u4Byte CCK_CtrlFrame_Cnt_main; + u4Byte CCK_CtrlFrame_Cnt_aux; + u4Byte OFDM_CtrlFrame_Cnt_main; + u4Byte OFDM_CtrlFrame_Cnt_aux; + u4Byte MainAnt_CtrlFrame_Sum; + u4Byte AuxAnt_CtrlFrame_Sum; + u4Byte MainAnt_CtrlFrame_Cnt; + u4Byte AuxAnt_CtrlFrame_Cnt; + #endif + BOOLEAN fix_ant_bfee; + BOOLEAN enable_ctrl_frame_antdiv; + BOOLEAN use_ctrl_frame_antdiv; + u1Byte hw_antsw_occur; +}FAT_T,*pFAT_T; + + +//1 ============================================================ +//1 enumeration +//1 ============================================================ + + + +typedef enum _FAT_STATE /*Fast antenna training*/ +{ + FAT_BEFORE_LINK_STATE = 0, + FAT_PREPARE_STATE = 1, + FAT_TRAINING_STATE = 2, + FAT_DECISION_STATE = 3 +}FAT_STATE_E, *PFAT_STATE_E; + +typedef enum _ANT_DIV_TYPE +{ + CG_TRX_HW_ANTDIV = 0x01, + CGCS_RX_HW_ANTDIV = 0x02, + CG_TRX_SMART_ANTDIV = 0x03, + S0S1_SW_ANTDIV = 0x04, /*8723B intrnal switch S0 S1*/ + HL_SW_SMART_ANT_TYPE1 = 0x10 /*Hong-Lin Smart antenna use for 8821AE which is a 2 Ant. entitys, and each Ant. is equipped with 4 antenna patterns*/ +}ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E; + + +//1 ============================================================ +//1 function prototype +//1 ============================================================ + + +VOID +ODM_StopAntennaSwitchDm( + IN PVOID pDM_VOID + ); +VOID +ODM_SetAntConfig( + IN PVOID pDM_VOID, + IN u1Byte antSetting // 0=A, 1=B, 2=C, .... + ); + + +#define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink + +VOID ODM_SwAntDivRestAfterLink( + IN PVOID pDM_VOID + ); + +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + +VOID +ODM_UpdateRxIdleAnt( + IN PVOID pDM_VOID, + IN u1Byte Ant +); + +#if (RTL8723B_SUPPORT == 1) +VOID +ODM_UpdateRxIdleAnt_8723B( + IN PVOID pDM_VOID, + IN u1Byte Ant, + IN u4Byte DefaultAnt, + IN u4Byte OptionalAnt +); +#endif + +#if (RTL8188F_SUPPORT == 1) +VOID +phydm_update_rx_idle_antenna_8188F( + IN PVOID pDM_VOID, + IN u4Byte default_ant +); +#endif + + +#ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +ODM_SW_AntDiv_Callback( + IN PRT_TIMER pTimer + ); + +VOID +ODM_SW_AntDiv_WorkitemCallback( + IN PVOID pContext + ); + + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + +VOID +ODM_SW_AntDiv_WorkitemCallback( + IN PVOID pContext +); + +VOID +ODM_SW_AntDiv_Callback( + void *FunctionContext + ); + +#endif + +VOID +odm_S0S1_SwAntDivByCtrlFrame( + IN PVOID pDM_VOID, + IN u1Byte Step +); + +VOID +odm_AntselStatisticsOfCtrlFrame( + IN PVOID pDM_VOID, + IN u1Byte antsel_tr_mux, + IN u4Byte RxPWDBAll +); + +VOID +odm_S0S1_SwAntDivByCtrlFrame_ProcessRSSI( + IN PVOID pDM_VOID, + IN PVOID p_phy_info_void, + IN PVOID p_pkt_info_void +); + +#endif + +#ifdef ODM_EVM_ENHANCE_ANTDIV +VOID +odm_EVM_FastAntTrainingCallback( + IN PVOID pDM_VOID +); +#endif + +VOID +odm_HW_AntDiv( + IN PVOID pDM_VOID +); + +#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) ) +VOID +odm_FastAntTraining( + IN PVOID pDM_VOID +); + +VOID +odm_FastAntTrainingCallback( + IN PVOID pDM_VOID +); + +VOID +odm_FastAntTrainingWorkItemCallback( + IN PVOID pDM_VOID +); +#endif + + +#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +phydm_beam_switch_workitem_callback( + IN PVOID pContext + ); + +VOID +phydm_beam_decision_workitem_callback( + IN PVOID pContext + ); + +#endif + +VOID +phydm_update_beam_pattern( + IN PVOID pDM_VOID, + IN u4Byte codeword, + IN u4Byte codeword_length + ); + +void +phydm_set_all_ant_same_beam_num( + IN PVOID pDM_VOID + ); + +VOID +phydm_hl_smart_ant_cmd( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len +); + +#endif/*#ifdef CONFIG_HL_SMART_ANTENNA_TYPE1*/ + +VOID +ODM_AntDivInit( + IN PVOID pDM_VOID +); + +VOID +ODM_AntDiv( + IN PVOID pDM_VOID +); + +VOID +odm_AntselStatistics( + IN PVOID pDM_VOID, + IN u1Byte antsel_tr_mux, + IN u4Byte MacId, + IN u4Byte utility, + IN u1Byte method +); + +VOID +ODM_Process_RSSIForAntDiv( + IN OUT PVOID pDM_VOID, + IN PVOID p_phy_info_void, + IN PVOID p_pkt_info_void +); + + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) +VOID +ODM_SetTxAntByTxInfo( + IN PVOID pDM_VOID, + IN pu1Byte pDesc, + IN u1Byte macId +); + +#elif(DM_ODM_SUPPORT_TYPE == ODM_AP) + +VOID +ODM_SetTxAntByTxInfo( + struct rtl8192cd_priv *priv, + struct tx_desc *pdesc, + unsigned short aid +); + +#endif + + +VOID +ODM_AntDiv_Config( + IN PVOID pDM_VOID +); + +VOID +ODM_AntDivTimers( + IN PVOID pDM_VOID, + IN u1Byte state +); + +#endif /*#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))*/ + +VOID +ODM_AntDivReset( + IN PVOID pDM_VOID +); + +VOID +odm_AntennaDiversityInit( + IN PVOID pDM_VOID +); + +VOID +odm_AntennaDiversity( + IN PVOID pDM_VOID +); + + +#endif /*#ifndef __ODMANTDIV_H__*/ diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_beamforming.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_beamforming.c new file mode 100644 index 000000000..c4ff1eb63 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_beamforming.c @@ -0,0 +1,1940 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if WPP_SOFTWARE_TRACE +#include "phydm_beamforming.tmh" +#endif +#endif + +#if (BEAMFORMING_SUPPORT == 1) + +PRT_BEAMFORM_STAINFO +phydm_staInfoInit( + IN PDM_ODM_T pDM_Odm, + IN u2Byte staIdx + ) +{ + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORM_STAINFO pEntry = &(pBeamInfo->BeamformSTAinfo); + PSTA_INFO_T pSTA = pDM_Odm->pODM_StaInfo[staIdx]; + PADAPTER Adapter = pDM_Odm->Adapter; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pMgntInfo); + PRT_VERY_HIGH_THROUGHPUT pVHTInfo = GET_VHT_INFO(pMgntInfo); + + ODM_MoveMemory(pDM_Odm, pEntry->MyMacAddr, Adapter->CurrentAddress, 6); + + pEntry->HtBeamformCap = pHTInfo->HtBeamformCap; + pEntry->VhtBeamformCap = pVHTInfo->VhtBeamformCap; + + /*IBSS, AP mode*/ + if (staIdx != 0) { + pEntry->AID = pSTA->AID; + pEntry->RA = pSTA->MacAddr; + pEntry->MacID = pSTA->AssociatedMacId; + pEntry->WirelessMode = pSTA->WirelessMode; + pEntry->BW = pSTA->BandWidth; + pEntry->CurBeamform = pSTA->HTInfo.HtCurBeamform; + } else {/*client mode*/ + pEntry->AID = pMgntInfo->mAId; + pEntry->RA = pMgntInfo->Bssid; + pEntry->MacID = pMgntInfo->mMacId; + pEntry->WirelessMode = pMgntInfo->dot11CurrentWirelessMode; + pEntry->BW = pMgntInfo->dot11CurrentChannelBandWidth; + pEntry->CurBeamform = pHTInfo->HtCurBeamform; + } + + if ((pEntry->WirelessMode & WIRELESS_MODE_AC_5G) || (pEntry->WirelessMode & WIRELESS_MODE_AC_24G)) { + if (staIdx != 0) + pEntry->CurBeamformVHT = pSTA->VHTInfo.VhtCurBeamform; + else + pEntry->CurBeamformVHT = pVHTInfo->VhtCurBeamform; + } + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("pSTA->wireless_mode = 0x%x, staidx = %d\n", pSTA->WirelessMode, staIdx)); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + + if (!IS_STA_VALID(pSTA)) { + rtw_warn_on(1); + DBG_871X("%s => sta_info(mac_id:%d) failed\n", __func__, staIdx); + return pEntry; + } + + ODM_MoveMemory(pDM_Odm, pEntry->MyMacAddr, adapter_mac_addr(pSTA->padapter), 6); + pEntry->HtBeamformCap = pSTA->htpriv.beamform_cap; + + pEntry->AID = pSTA->aid; + pEntry->RA = pSTA->hwaddr; + pEntry->MacID = pSTA->mac_id; + pEntry->WirelessMode = pSTA->wireless_mode; + pEntry->BW = pSTA->bw_mode; + + pEntry->CurBeamform = pSTA->htpriv.beamform_cap; +#if ODM_IC_11AC_SERIES_SUPPORT + if ((pEntry->WirelessMode & WIRELESS_MODE_AC_5G) || (pEntry->WirelessMode & WIRELESS_MODE_AC_24G)) { + pEntry->CurBeamformVHT = pSTA->vhtpriv.beamform_cap; + pEntry->VhtBeamformCap = pSTA->vhtpriv.beamform_cap; + } +#endif + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("pSTA->wireless_mode = 0x%x, staidx = %d\n", pSTA->wireless_mode, staIdx)); +#endif + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("pEntry->CurBeamform = 0x%x, pEntry->CurBeamformVHT = 0x%x\n", pEntry->CurBeamform, pEntry->CurBeamformVHT)); + return pEntry; + +} +void phydm_staInfoUpdate( + IN PDM_ODM_T pDM_Odm, + IN u2Byte staIdx, + PRT_BEAMFORMEE_ENTRY pBeamformEntry + ) +{ + PSTA_INFO_T pSTA = pDM_Odm->pODM_StaInfo[staIdx]; + + if (!IS_STA_VALID(pSTA)) + return; + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + pSTA->txbf_paid = pBeamformEntry->P_AID; + pSTA->txbf_gid = pBeamformEntry->G_ID; +#endif +} + + +u1Byte +Beamforming_GetHTNDPTxRate( + IN PVOID pDM_VOID, + u1Byte CompSteeringNumofBFer +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte Nr_index = 0; + u1Byte NDPTxRate; + /*Find Nr*/ + + if (pDM_Odm->SupportICType & ODM_RTL8814A) + Nr_index = TxBF_Nr(halTxbf8814A_GetNtx(pDM_Odm), CompSteeringNumofBFer); + else + Nr_index = TxBF_Nr(1, CompSteeringNumofBFer); + + switch (Nr_index) { + case 1: + NDPTxRate = MGN_MCS8; + break; + + case 2: + NDPTxRate = MGN_MCS16; + break; + + case 3: + NDPTxRate = MGN_MCS24; + break; + + default: + NDPTxRate = MGN_MCS8; + break; + } + +return NDPTxRate; + +} + +u1Byte +Beamforming_GetVHTNDPTxRate( + IN PVOID pDM_VOID, + u1Byte CompSteeringNumofBFer +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte Nr_index = 0; + u1Byte NDPTxRate; + /*Find Nr*/ + if (pDM_Odm->SupportICType & ODM_RTL8814A) + Nr_index = TxBF_Nr(halTxbf8814A_GetNtx(pDM_Odm), CompSteeringNumofBFer); + else + Nr_index = TxBF_Nr(1, CompSteeringNumofBFer); + + switch (Nr_index) { + case 1: + NDPTxRate = MGN_VHT2SS_MCS0; + break; + + case 2: + NDPTxRate = MGN_VHT3SS_MCS0; + break; + + case 3: + NDPTxRate = MGN_VHT4SS_MCS0; + break; + + default: + NDPTxRate = MGN_VHT2SS_MCS0; + break; + } + +return NDPTxRate; + +} + + +PRT_BEAMFORMEE_ENTRY +phydm_Beamforming_GetBFeeEntryByAddr( + IN PVOID pDM_VOID, + IN pu1Byte RA, + OUT pu1Byte Idx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { + if (pBeamInfo->BeamformeeEntry[i].bUsed && (eqMacAddr(RA, pBeamInfo->BeamformeeEntry[i].MacAddr))) { + *Idx = i; + return &(pBeamInfo->BeamformeeEntry[i]); + } + } + + return NULL; +} + +PRT_BEAMFORMER_ENTRY +phydm_Beamforming_GetBFerEntryByAddr( + IN PVOID pDM_VOID, + IN pu1Byte TA, + OUT pu1Byte Idx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + + for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) { + if (pBeamInfo->BeamformerEntry[i].bUsed && (eqMacAddr(TA, pBeamInfo->BeamformerEntry[i].MacAddr))) { + *Idx = i; + return &(pBeamInfo->BeamformerEntry[i]); + } + } + + return NULL; +} + + +PRT_BEAMFORMEE_ENTRY +phydm_Beamforming_GetEntryByMacId( + IN PVOID pDM_VOID, + IN u1Byte MacId, + OUT pu1Byte Idx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { + if (pBeamInfo->BeamformeeEntry[i].bUsed && (MacId == pBeamInfo->BeamformeeEntry[i].MacId)) { + *Idx = i; + return &(pBeamInfo->BeamformeeEntry[i]); + } + } + + return NULL; +} + + +BEAMFORMING_CAP +phydm_Beamforming_GetEntryBeamCapByMacId( + IN PVOID pDM_VOID, + IN u1Byte MacId + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + BEAMFORMING_CAP BeamformEntryCap = BEAMFORMING_CAP_NONE; + + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { + if (pBeamInfo->BeamformeeEntry[i].bUsed && (MacId == pBeamInfo->BeamformeeEntry[i].MacId)) { + BeamformEntryCap = pBeamInfo->BeamformeeEntry[i].BeamformEntryCap; + i = BEAMFORMEE_ENTRY_NUM; + } + } + + return BeamformEntryCap; +} + + +PRT_BEAMFORMEE_ENTRY +phydm_Beamforming_GetFreeBFeeEntry( + IN PVOID pDM_VOID, + OUT pu1Byte Idx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { + if (pBeamInfo->BeamformeeEntry[i].bUsed == FALSE) { + *Idx = i; + return &(pBeamInfo->BeamformeeEntry[i]); + } + } + return NULL; +} + +PRT_BEAMFORMER_ENTRY +phydm_Beamforming_GetFreeBFerEntry( + IN PVOID pDM_VOID, + OUT pu1Byte Idx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s ===>\n", __func__)); + + for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) { + if (pBeamInfo->BeamformerEntry[i].bUsed == FALSE) { + *Idx = i; + return &(pBeamInfo->BeamformerEntry[i]); + } + } + return NULL; +} + +/* +// Description: Get the first entry index of MU Beamformee. +// +// Return Value: Index of the first MU sta. +// +// 2015.05.25. Created by tynli. +// +*/ +u1Byte +phydm_Beamforming_GetFirstMUBFeeEntryIdx( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte idx = 0xFF; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + BOOLEAN bFound = FALSE; + + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + if (pBeamInfo->BeamformeeEntry[idx].bUsed && pBeamInfo->BeamformeeEntry[idx].is_mu_sta) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] idx=%d!\n", __func__, idx)); + bFound = TRUE; + break; + } + } + + if (!bFound) + idx = 0xFF; + + return idx; +} + + +/*Add SU BFee and MU BFee*/ +PRT_BEAMFORMEE_ENTRY +Beamforming_AddBFeeEntry( + IN PVOID pDM_VOID, + IN PRT_BEAMFORM_STAINFO pSTA, + IN BEAMFORMING_CAP BeamformCap, + IN u1Byte NumofSoundingDim, + IN u1Byte CompSteeringNumofBFer, + OUT pu1Byte Idx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMEE_ENTRY pEntry = phydm_Beamforming_GetFreeBFeeEntry(pDM_Odm, Idx); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + if (pEntry != NULL) { + pEntry->bUsed = TRUE; + pEntry->AID = pSTA->AID; + pEntry->MacId = pSTA->MacID; + pEntry->SoundBW = pSTA->BW; + ODM_MoveMemory(pDM_Odm, pEntry->MyMacAddr, pSTA->MyMacAddr, 6); + + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_AP)) { + /*BSSID[44:47] xor BSSID[40:43]*/ + u2Byte BSSID = ((pSTA->MyMacAddr[5] & 0xf0) >> 4) ^ (pSTA->MyMacAddr[5] & 0xf); + /*(dec(A) + dec(B)*32) mod 512*/ + pEntry->P_AID = (pSTA->AID + BSSID * 32) & 0x1ff; + pEntry->G_ID = 63; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BFee P_AID addressed to STA=%d\n", __func__, pEntry->P_AID)); + } else if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) { + /*ad hoc mode*/ + pEntry->P_AID = 0; + pEntry->G_ID = 63; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BFee P_AID as IBSS=%d\n", __func__, pEntry->P_AID)); + } else { + /*client mode*/ + pEntry->P_AID = pSTA->RA[5]; + /*BSSID[39:47]*/ + pEntry->P_AID = (pEntry->P_AID << 1) | (pSTA->RA[4] >> 7); + pEntry->G_ID = 0; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BFee P_AID addressed to AP=0x%X\n", __func__, pEntry->P_AID)); + } + cpMacAddr(pEntry->MacAddr, pSTA->RA); + pEntry->bTxBF = FALSE; + pEntry->bSound = FALSE; + pEntry->SoundPeriod = 400; + pEntry->BeamformEntryCap = BeamformCap; + pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; + +/* pEntry->LogSeq = 0xff; Move to Beamforming_AddBFerEntry*/ +/* pEntry->LogRetryCnt = 0; Move to Beamforming_AddBFerEntry*/ +/* pEntry->LogSuccessCnt = 0; Move to Beamforming_AddBFerEntry*/ + + pEntry->LogStatusFailCnt = 0; + + pEntry->NumofSoundingDim = NumofSoundingDim; + pEntry->CompSteeringNumofBFer = CompSteeringNumofBFer; + + if (BeamformCap & BEAMFORMER_CAP_VHT_MU) { + pDM_Odm->BeamformingInfo.beamformee_mu_cnt += 1; + pEntry->is_mu_sta = TRUE; + pDM_Odm->BeamformingInfo.FirstMUBFeeIndex = phydm_Beamforming_GetFirstMUBFeeEntryIdx(pDM_Odm); + } else if (BeamformCap & BEAMFORMER_CAP_VHT_SU) { + pDM_Odm->BeamformingInfo.beamformee_su_cnt += 1; + pEntry->is_mu_sta = FALSE; + } + + return pEntry; + } + else + return NULL; +} + +/*Add SU BFee and MU BFer*/ +PRT_BEAMFORMER_ENTRY +Beamforming_AddBFerEntry( + IN PVOID pDM_VOID, + IN PRT_BEAMFORM_STAINFO pSTA, + IN BEAMFORMING_CAP BeamformCap, + IN u1Byte NumofSoundingDim, + OUT pu1Byte Idx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMER_ENTRY pEntry = phydm_Beamforming_GetFreeBFerEntry(pDM_Odm, Idx); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + if (pEntry != NULL) { + pEntry->bUsed = TRUE; + ODM_MoveMemory(pDM_Odm, pEntry->MyMacAddr, pSTA->MyMacAddr, 6); + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_AP)) { + /*BSSID[44:47] xor BSSID[40:43]*/ + u2Byte BSSID = ((pSTA->MyMacAddr[5] & 0xf0) >> 4) ^ (pSTA->MyMacAddr[5] & 0xf); + + pEntry->P_AID = (pSTA->AID + BSSID * 32) & 0x1ff; + pEntry->G_ID = 63; + /*(dec(A) + dec(B)*32) mod 512*/ + } else if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) { + pEntry->P_AID = 0; + pEntry->G_ID = 63; + } else { + pEntry->P_AID = pSTA->RA[5]; + /*BSSID[39:47]*/ + pEntry->P_AID = (pEntry->P_AID << 1) | (pSTA->RA[4] >> 7); + pEntry->G_ID = 0; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: P_AID addressed to AP=0x%X\n", __func__, pEntry->P_AID)); + } + + cpMacAddr(pEntry->MacAddr, pSTA->RA); + pEntry->BeamformEntryCap = BeamformCap; + + pEntry->PreLogSeq = 0; /*Modified by Jeffery @2015-04-13*/ + pEntry->LogSeq = 0; /*Modified by Jeffery @2014-10-29*/ + pEntry->LogRetryCnt = 0; /*Modified by Jeffery @2014-10-29*/ + pEntry->LogSuccess = 0; /*LogSuccess is NOT needed to be accumulated, so LogSuccessCnt->LogSuccess, 2015-04-13, Jeffery*/ + pEntry->ClockResetTimes = 0; /*Modified by Jeffery @2015-04-13*/ + + pEntry->NumofSoundingDim = NumofSoundingDim; + + if (BeamformCap & BEAMFORMEE_CAP_VHT_MU) { + pDM_Odm->BeamformingInfo.beamformer_mu_cnt += 1; + pEntry->is_mu_ap = TRUE; + pEntry->AID = pSTA->AID; + } else if (BeamformCap & BEAMFORMEE_CAP_VHT_SU) { + pDM_Odm->BeamformingInfo.beamformer_su_cnt += 1; + pEntry->is_mu_ap = FALSE; + } + + return pEntry; + } + else + return NULL; +} + +#if 0 +BOOLEAN +Beamforming_RemoveEntry( + IN PADAPTER Adapter, + IN pu1Byte RA, + OUT pu1Byte Idx + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + PRT_BEAMFORMER_ENTRY pBFerEntry = phydm_Beamforming_GetBFerEntryByAddr(pDM_Odm, RA, Idx); + PRT_BEAMFORMEE_ENTRY pEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, Idx); + BOOLEAN ret = FALSE; + + RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s Start!\n", __func__)); + RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s, pBFerEntry=0x%x\n", __func__, pBFerEntry)); + RT_DISP(FBEAM, FBEAM_FUN, ("[Beamforming]@%s, pEntry=0x%x\n", __func__, pEntry)); + + if (pEntry != NULL) { + pEntry->bUsed = FALSE; + pEntry->BeamformEntryCap = BEAMFORMING_CAP_NONE; + /*pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;*/ + pEntry->bBeamformingInProgress = FALSE; + ret = TRUE; + } + if (pBFerEntry != NULL) { + pBFerEntry->bUsed = FALSE; + pBFerEntry->BeamformEntryCap = BEAMFORMING_CAP_NONE; + ret = TRUE; + } + return ret; + +} +#endif + +/* Used for BeamformingStart_V1 */ +VOID +phydm_Beamforming_NDPARate( + IN PVOID pDM_VOID, + CHANNEL_WIDTH BW, + u1Byte Rate +) +{ + u2Byte NDPARate = Rate; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + if (NDPARate == 0) { + if(pDM_Odm->RSSI_Min > 30) // link RSSI > 30% + NDPARate = ODM_RATE24M; + else + NDPARate = ODM_RATE6M; + } + + if (NDPARate < ODM_RATEMCS0) + BW = (CHANNEL_WIDTH)ODM_BW20M; + + NDPARate = (NDPARate << 8) | BW; + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_RATE, (pu1Byte)&NDPARate); + +} + + +/* Used for BeamformingStart_SW and BeamformingStart_FW */ +VOID +phydm_Beamforming_DymNDPARate( + IN PVOID pDM_VOID +) +{ + u2Byte NDPARate = ODM_RATE6M, BW; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + if (pDM_Odm->RSSI_Min > 30) /*link RSSI > 30%*/ + NDPARate = ODM_RATE24M; + else + NDPARate = ODM_RATE6M; + + BW = ODM_BW20M; + NDPARate = NDPARate << 8 | BW; + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_RATE, (pu1Byte)&NDPARate); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s End, NDPA Rate = 0x%X\n", __func__, NDPARate)); +} + +/* +* SW Sounding : SW Timer unit 1ms +* HW Timer unit (1/32000) s 32k is clock. +* FW Sounding : FW Timer unit 10ms +*/ +VOID +Beamforming_DymPeriod( + IN PVOID pDM_VOID, + IN u8 status +) +{ + u1Byte Idx; + BOOLEAN bChangePeriod = FALSE; + u2Byte SoundPeriod_SW, SoundPeriod_FW; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + PRT_BEAMFORMEE_ENTRY pBeamformEntry; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PRT_SOUNDING_INFO pSoundInfo = &(pBeamInfo->SoundingInfo); + + PRT_BEAMFORMEE_ENTRY pEntry = &(pBeamInfo->BeamformeeEntry[pBeamInfo->BeamformeeCurIdx]); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + //3 TODO per-client throughput caculation. + + if ((*(pDM_Odm->pCurrentTxTP) + *(pDM_Odm->pCurrentRxTP) > 2) && ((pEntry->LogStatusFailCnt <= 20) || status)) { + SoundPeriod_SW = 40; /* 40ms */ + SoundPeriod_FW = 40; /* From H2C cmd, unit = 10ms */ + } else { + SoundPeriod_SW = 4000;/* 4s */ + SoundPeriod_FW = 400; + } + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]SoundPeriod_SW=%d, SoundPeriod_FW=%d\n", __func__, SoundPeriod_SW, SoundPeriod_FW)); + + for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { + pBeamformEntry = pBeamInfo->BeamformeeEntry+Idx; + + if (pBeamformEntry->DefaultCSICnt > 20) { + /*Modified by David*/ + SoundPeriod_SW = 4000; + SoundPeriod_FW = 400; + } + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Period = %d\n", __func__, SoundPeriod_SW)); + if (pBeamformEntry->BeamformEntryCap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) { + if (pSoundInfo->SoundMode == SOUNDING_FW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_FW_HT_TIMER) { + if (pBeamformEntry->SoundPeriod != SoundPeriod_FW) { + pBeamformEntry->SoundPeriod = SoundPeriod_FW; + bChangePeriod = TRUE; /*Only FW sounding need to send H2C packet to change sound period. */ + } + } else if (pBeamformEntry->SoundPeriod != SoundPeriod_SW) { + pBeamformEntry->SoundPeriod = SoundPeriod_SW; + } + } + } + + if (bChangePeriod) + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_FW_NDPA, (pu1Byte)&Idx); +} + + + + +BOOLEAN +Beamforming_SendHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN CHANNEL_WIDTH BW, + IN u1Byte QIdx + ) +{ + BOOLEAN ret = TRUE; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (QIdx == BEACON_QUEUE) + ret = SendFWHTNDPAPacket(pDM_Odm, RA, BW); + else + ret = SendSWHTNDPAPacket(pDM_Odm, RA, BW); + + return ret; +} + + + +BOOLEAN +Beamforming_SendVHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN u2Byte AID, + IN CHANNEL_WIDTH BW, + IN u1Byte QIdx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + BOOLEAN ret = TRUE; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + + HalComTxbf_Set(pDM_Odm, TXBF_SET_GET_TX_RATE, NULL); + + if ((pDM_Odm->TxBfDataRate >= ODM_RATEVHTSS3MCS7) && (pDM_Odm->TxBfDataRate <= ODM_RATEVHTSS3MCS9)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s: 3SS VHT 789 don't sounding\n", __func__)); + + } else { + if (QIdx == BEACON_QUEUE) /* Send to reserved page => FW NDPA */ + ret = SendFWVHTNDPAPacket(pDM_Odm, RA, AID, BW); + else { +#ifdef SUPPORT_MU_BF + #if (SUPPORT_MU_BF == 1) + pBeamInfo->is_mu_sounding = TRUE; + ret = SendSWVHTMUNDPAPacket(pDM_Odm, BW); + #else + pBeamInfo->is_mu_sounding = FALSE; + ret = SendSWVHTNDPAPacket(pDM_Odm, RA, AID, BW); + #endif +#else + pBeamInfo->is_mu_sounding = FALSE; + ret = SendSWVHTNDPAPacket(pDM_Odm, RA, AID, BW); +#endif + } + } + return ret; +} + + +BEAMFORMING_NOTIFY_STATE +phydm_beamfomring_bSounding( + IN PVOID pDM_VOID, + PRT_BEAMFORMING_INFO pBeamInfo, + pu1Byte Idx + ) +{ + BEAMFORMING_NOTIFY_STATE bSounding = BEAMFORMING_NOTIFY_NONE; + RT_BEAMFORMING_OID_INFO BeamOidInfo = pBeamInfo->BeamformingOidInfo; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + /*if(( Beamforming_GetBeamCap(pBeamInfo) & BEAMFORMER_CAP) == 0)*/ + /*bSounding = BEAMFORMING_NOTIFY_RESET;*/ + if (BeamOidInfo.SoundOidMode == SOUNDING_STOP_All_TIMER) + bSounding = BEAMFORMING_NOTIFY_RESET; + else { + u1Byte i; + + for (i = 0 ; i < BEAMFORMEE_ENTRY_NUM ; i++) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s: BFee Entry %d bUsed=%d, bSound=%d\n", __func__, i, pBeamInfo->BeamformeeEntry[i].bUsed, pBeamInfo->BeamformeeEntry[i].bSound)); + if (pBeamInfo->BeamformeeEntry[i].bUsed && (!pBeamInfo->BeamformeeEntry[i].bSound)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Add BFee entry %d\n", __func__, i)); + *Idx = i; + if (pBeamInfo->BeamformeeEntry[i].is_mu_sta) + bSounding = BEAMFORMEE_NOTIFY_ADD_MU; + else + bSounding = BEAMFORMEE_NOTIFY_ADD_SU; + } + + if ((!pBeamInfo->BeamformeeEntry[i].bUsed) && pBeamInfo->BeamformeeEntry[i].bSound) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Delete BFee entry %d\n", __func__, i)); + *Idx = i; + if (pBeamInfo->BeamformeeEntry[i].is_mu_sta) + bSounding = BEAMFORMEE_NOTIFY_DELETE_MU; + else + bSounding = BEAMFORMEE_NOTIFY_DELETE_SU; + } + } + } + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s End, bSounding = %d\n", __func__, bSounding)); + return bSounding; +} + + +//This function is unused +u1Byte +phydm_beamforming_SoundingIdx( + IN PVOID pDM_VOID, + PRT_BEAMFORMING_INFO pBeamInfo + ) +{ + u1Byte Idx = 0; + RT_BEAMFORMEE_ENTRY BeamEntry; + RT_BEAMFORMING_OID_INFO BeamOidInfo = pBeamInfo->BeamformingOidInfo; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + if (BeamOidInfo.SoundOidMode == SOUNDING_SW_HT_TIMER || BeamOidInfo.SoundOidMode == SOUNDING_SW_VHT_TIMER || + BeamOidInfo.SoundOidMode == SOUNDING_HW_HT_TIMER || BeamOidInfo.SoundOidMode == SOUNDING_HW_VHT_TIMER) + Idx = BeamOidInfo.SoundOidIdx; + else { + u1Byte i; + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { + if (pBeamInfo->BeamformeeEntry[i].bUsed && (FALSE == pBeamInfo->BeamformeeEntry[i].bSound)) { + Idx = i; + break; + } + } + } + + return Idx; +} + + +SOUNDING_MODE +phydm_beamforming_SoundingMode( + IN PVOID pDM_VOID, + PRT_BEAMFORMING_INFO pBeamInfo, + u1Byte Idx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte SupportInterface = pDM_Odm->SupportInterface; + + RT_BEAMFORMEE_ENTRY BeamEntry = pBeamInfo->BeamformeeEntry[Idx]; + RT_BEAMFORMING_OID_INFO BeamOidInfo = pBeamInfo->BeamformingOidInfo; + SOUNDING_MODE Mode = BeamOidInfo.SoundOidMode; + + if (BeamOidInfo.SoundOidMode == SOUNDING_SW_VHT_TIMER || BeamOidInfo.SoundOidMode == SOUNDING_HW_VHT_TIMER) { + if (BeamEntry.BeamformEntryCap & BEAMFORMER_CAP_VHT_SU) + Mode = BeamOidInfo.SoundOidMode; + else + Mode = SOUNDING_STOP_All_TIMER; + } else if (BeamOidInfo.SoundOidMode == SOUNDING_SW_HT_TIMER || BeamOidInfo.SoundOidMode == SOUNDING_HW_HT_TIMER) { + if (BeamEntry.BeamformEntryCap & BEAMFORMER_CAP_HT_EXPLICIT) + Mode = BeamOidInfo.SoundOidMode; + else + Mode = SOUNDING_STOP_All_TIMER; + } else if (BeamEntry.BeamformEntryCap & BEAMFORMER_CAP_VHT_SU) { + if ((SupportInterface == ODM_ITRF_USB) && !(pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_RTL8822B))) + Mode = SOUNDING_FW_VHT_TIMER; + else + Mode = SOUNDING_SW_VHT_TIMER; + } else if (BeamEntry.BeamformEntryCap & BEAMFORMER_CAP_HT_EXPLICIT) { + if ((SupportInterface == ODM_ITRF_USB) && !(pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_RTL8822B))) + Mode = SOUNDING_FW_HT_TIMER; + else + Mode = SOUNDING_SW_HT_TIMER; + } else + Mode = SOUNDING_STOP_All_TIMER; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SupportInterface=%d, Mode=%d\n", __func__, SupportInterface, Mode)); + + return Mode; +} + + +u2Byte +phydm_beamforming_SoundingTime( + IN PVOID pDM_VOID, + PRT_BEAMFORMING_INFO pBeamInfo, + SOUNDING_MODE Mode, + u1Byte Idx + ) +{ + u2Byte SoundingTime = 0xffff; + RT_BEAMFORMEE_ENTRY BeamEntry = pBeamInfo->BeamformeeEntry[Idx]; + RT_BEAMFORMING_OID_INFO BeamOidInfo = pBeamInfo->BeamformingOidInfo; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + if (Mode == SOUNDING_HW_HT_TIMER || Mode == SOUNDING_HW_VHT_TIMER) + SoundingTime = BeamOidInfo.SoundOidPeriod * 32; + else if (Mode == SOUNDING_SW_HT_TIMER || Mode == SOUNDING_SW_VHT_TIMER) + /*Modified by David*/ + SoundingTime = BeamEntry.SoundPeriod; /*BeamOidInfo.SoundOidPeriod;*/ + else + SoundingTime = BeamEntry.SoundPeriod; + + return SoundingTime; +} + + +CHANNEL_WIDTH +phydm_beamforming_SoundingBW( + IN PVOID pDM_VOID, + PRT_BEAMFORMING_INFO pBeamInfo, + SOUNDING_MODE Mode, + u1Byte Idx + ) +{ + CHANNEL_WIDTH SoundingBW = CHANNEL_WIDTH_20; + RT_BEAMFORMEE_ENTRY BeamEntry = pBeamInfo->BeamformeeEntry[Idx]; + RT_BEAMFORMING_OID_INFO BeamOidInfo = pBeamInfo->BeamformingOidInfo; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (Mode == SOUNDING_HW_HT_TIMER || Mode == SOUNDING_HW_VHT_TIMER) + SoundingBW = BeamOidInfo.SoundOidBW; + else if (Mode == SOUNDING_SW_HT_TIMER || Mode == SOUNDING_SW_VHT_TIMER) + /*Modified by David*/ + SoundingBW = BeamEntry.SoundBW; /*BeamOidInfo.SoundOidBW;*/ + else + SoundingBW = BeamEntry.SoundBW; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, SoundingBW=0x%X\n", __func__, SoundingBW)); + + return SoundingBW; +} + + +BOOLEAN +phydm_Beamforming_SelectBeamEntry( + IN PVOID pDM_VOID, + PRT_BEAMFORMING_INFO pBeamInfo + ) +{ + PRT_SOUNDING_INFO pSoundInfo = &(pBeamInfo->SoundingInfo); + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + /*pEntry.bSound is different between first and latter NDPA, and should not be used as BFee entry selection*/ + /*BTW, latter modification should sync to the selection mechanism of AP/ADSL instead of the fixed SoundIdx.*/ + pSoundInfo->SoundIdx = phydm_beamforming_SoundingIdx(pDM_Odm, pBeamInfo); + /*pSoundInfo->SoundIdx = 0;*/ + + if (pSoundInfo->SoundIdx < BEAMFORMEE_ENTRY_NUM) + pSoundInfo->SoundMode = phydm_beamforming_SoundingMode(pDM_Odm, pBeamInfo, pSoundInfo->SoundIdx); + else + pSoundInfo->SoundMode = SOUNDING_STOP_All_TIMER; + + if (SOUNDING_STOP_All_TIMER == pSoundInfo->SoundMode) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Return because of SOUNDING_STOP_All_TIMER\n", __func__)); + return FALSE; + } else { + pSoundInfo->SoundBW = phydm_beamforming_SoundingBW(pDM_Odm, pBeamInfo, pSoundInfo->SoundMode, pSoundInfo->SoundIdx ); + pSoundInfo->SoundPeriod = phydm_beamforming_SoundingTime(pDM_Odm, pBeamInfo, pSoundInfo->SoundMode, pSoundInfo->SoundIdx ); + return TRUE; + } +} + +/*SU BFee Entry Only*/ +BOOLEAN +phydm_beamforming_StartPeriod( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + BOOLEAN Ret = TRUE; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_SOUNDING_INFO pSoundInfo = &(pBeamInfo->SoundingInfo); + + phydm_Beamforming_DymNDPARate(pDM_Odm); + + phydm_Beamforming_SelectBeamEntry(pDM_Odm, pBeamInfo); // Modified + + if (pSoundInfo->SoundMode == SOUNDING_SW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_SW_HT_TIMER) + ODM_SetTimer(pDM_Odm, &pBeamInfo->BeamformingTimer, pSoundInfo->SoundPeriod); + else if (pSoundInfo->SoundMode == SOUNDING_HW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_HW_HT_TIMER || + pSoundInfo->SoundMode == SOUNDING_AUTO_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_AUTO_HT_TIMER) { + HAL_HW_TIMER_TYPE TimerType = HAL_TIMER_TXBF; + u4Byte val = (pSoundInfo->SoundPeriod | (TimerType<<16)); + + //HW timer stop: All IC has the same setting + Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_HW_REG_TIMER_STOP, (pu1Byte)(&TimerType)); + //ODM_Write1Byte(pDM_Odm, 0x15F, 0); + //HW timer init: All IC has the same setting, but 92E & 8812A only write 2 bytes + Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_HW_REG_TIMER_INIT, (pu1Byte)(&val)); + //ODM_Write1Byte(pDM_Odm, 0x164, 1); + //ODM_Write4Byte(pDM_Odm, 0x15C, val); + //HW timer start: All IC has the same setting + Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_HW_REG_TIMER_START, (pu1Byte)(&TimerType)); + //ODM_Write1Byte(pDM_Odm, 0x15F, 0x5); + } else if (pSoundInfo->SoundMode == SOUNDING_FW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_FW_HT_TIMER) + Ret = BeamformingStart_FW(pDM_Odm, pSoundInfo->SoundIdx); + else + Ret = FALSE; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SoundIdx=%d, SoundMode=%d, SoundBW=%d, SoundPeriod=%d\n", __func__, + pSoundInfo->SoundIdx, pSoundInfo->SoundMode, pSoundInfo->SoundBW, pSoundInfo->SoundPeriod)); + + return Ret; +} + +// Used after Beamforming_Leave, and will clear the setting of the "already deleted" entry +/*SU BFee Entry Only*/ +VOID +phydm_beamforming_EndPeriod_SW( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + u1Byte Idx = 0; + PRT_BEAMFORMEE_ENTRY pBeamformEntry; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_SOUNDING_INFO pSoundInfo = &(pBeamInfo->SoundingInfo); + + HAL_HW_TIMER_TYPE TimerType = HAL_TIMER_TXBF; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + if (pSoundInfo->SoundMode == SOUNDING_SW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_SW_HT_TIMER) + ODM_CancelTimer(pDM_Odm, &pBeamInfo->BeamformingTimer); + else if (pSoundInfo->SoundMode == SOUNDING_HW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_HW_HT_TIMER || + pSoundInfo->SoundMode == SOUNDING_AUTO_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_AUTO_HT_TIMER) + /*HW timer stop: All IC has the same setting*/ + Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_HW_REG_TIMER_STOP, (pu1Byte)(&TimerType)); + /*ODM_Write1Byte(pDM_Odm, 0x15F, 0);*/ +} + +VOID +phydm_beamforming_EndPeriod_FW( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte Idx = 0; + + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_FW_NDPA, (pu1Byte)&Idx); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]\n", __func__)); +} + + +/*SU BFee Entry Only*/ +VOID +phydm_beamforming_ClearEntry_SW( + IN PVOID pDM_VOID, + BOOLEAN IsDelete, + u1Byte DeleteIdx + ) +{ + u1Byte Idx = 0; + PRT_BEAMFORMEE_ENTRY pBeamformEntry = NULL; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + + if (IsDelete) { + if (DeleteIdx < BEAMFORMEE_ENTRY_NUM) { + pBeamformEntry = pBeamInfo->BeamformeeEntry + DeleteIdx; + if (!((!pBeamformEntry->bUsed) && pBeamformEntry->bSound)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SW DeleteIdx is wrong!!!!!\n", __func__)); + return; + } + } + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SW delete BFee entry %d\n", __func__, DeleteIdx)); + if (pBeamformEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING) { + pBeamformEntry->bBeamformingInProgress = FALSE; + pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; + } else if (pBeamformEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_STATUS, (pu1Byte)&DeleteIdx); + } + pBeamformEntry->bSound = FALSE; + } else { + for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { + pBeamformEntry = pBeamInfo->BeamformeeEntry+Idx; + + /*Used after bSounding=RESET, and will clear the setting of "ever sounded" entry, which is not necessarily be deleted.*/ + /*This function is mainly used in case "BeamOidInfo.SoundOidMode == SOUNDING_STOP_All_TIMER".*/ + /*However, setting oid doesn't delete entries (bUsed is still TRUE), new entries may fail to be added in.*/ + + if (pBeamformEntry->bSound) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] SW reset BFee entry %d\n", __func__, Idx)); + /* + * If End procedure is + * 1. Between (Send NDPA, C2H packet return), reset state to initialized. + * After C2H packet return , status bit will be set to zero. + * + * 2. After C2H packet, then reset state to initialized and clear status bit. + */ + + if (pBeamformEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING) + phydm_Beamforming_End_SW(pDM_Odm, 0); + else if (pBeamformEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZED; + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_STATUS, (pu1Byte)&Idx); + } + + pBeamformEntry->bSound = FALSE; + } + } + } +} + +VOID +phydm_beamforming_ClearEntry_FW( + IN PVOID pDM_VOID, + BOOLEAN IsDelete, + u1Byte DeleteIdx + ) +{ + u1Byte Idx = 0; + PRT_BEAMFORMEE_ENTRY pBeamformEntry = NULL; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + + if (IsDelete) { + if (DeleteIdx < BEAMFORMEE_ENTRY_NUM) { + pBeamformEntry = pBeamInfo->BeamformeeEntry + DeleteIdx; + + if (!((!pBeamformEntry->bUsed) && pBeamformEntry->bSound)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] FW DeleteIdx is wrong!!!!!\n", __func__)); + return; + } + } + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: FW delete BFee entry %d\n", __func__, DeleteIdx)); + pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_UNINITIALIZE; + pBeamformEntry->bSound = FALSE; + } else { + for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { + pBeamformEntry = pBeamInfo->BeamformeeEntry+Idx; + + /*Used after bSounding=RESET, and will clear the setting of "ever sounded" entry, which is not necessarily be deleted.*/ + /*This function is mainly used in case "BeamOidInfo.SoundOidMode == SOUNDING_STOP_All_TIMER".*/ + /*However, setting oid doesn't delete entries (bUsed is still TRUE), new entries may fail to be added in.*/ + + if (pBeamformEntry->bSound) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]FW reset BFee entry %d\n", __func__, Idx)); + /* + * If End procedure is + * 1. Between (Send NDPA, C2H packet return), reset state to initialized. + * After C2H packet return , status bit will be set to zero. + * + * 2. After C2H packet, then reset state to initialized and clear status bit. + */ + + pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZED; + pBeamformEntry->bSound = FALSE; + } + } + } +} + +/* +* Called : +* 1. Add and delete entry : Beamforming_Enter/Beamforming_Leave +* 2. FW trigger : Beamforming_SetTxBFen +* 3. Set OID_RT_BEAMFORMING_PERIOD : BeamformingControl_V2 +*/ +VOID +phydm_Beamforming_Notify( + IN PVOID pDM_VOID + ) +{ + u1Byte Idx=BEAMFORMEE_ENTRY_NUM; + BEAMFORMING_NOTIFY_STATE bSounding = BEAMFORMING_NOTIFY_NONE; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_SOUNDING_INFO pSoundInfo = &(pBeamInfo->SoundingInfo); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + bSounding = phydm_beamfomring_bSounding(pDM_Odm, pBeamInfo, &Idx); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, Before notify, bSounding=%d, Idx=%d\n", __func__, bSounding, Idx)); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: pBeamInfo->beamformee_su_cnt = %d\n", __func__, pBeamInfo->beamformee_su_cnt)); + + + switch (bSounding) { + case BEAMFORMEE_NOTIFY_ADD_SU: + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_ADD_SU\n", __func__)); + phydm_beamforming_StartPeriod(pDM_Odm); + break; + + case BEAMFORMEE_NOTIFY_DELETE_SU: + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_DELETE_SU\n", __func__)); + if (pSoundInfo->SoundMode == SOUNDING_FW_HT_TIMER || pSoundInfo->SoundMode == SOUNDING_FW_VHT_TIMER) { + phydm_beamforming_ClearEntry_FW(pDM_Odm, TRUE, Idx); + if (pBeamInfo->beamformee_su_cnt == 0) { /* For 2->1 entry, we should not cancel SW timer */ + phydm_beamforming_EndPeriod_FW(pDM_Odm); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: No BFee left\n", __func__)); + } + } else { + phydm_beamforming_ClearEntry_SW(pDM_Odm, TRUE, Idx); + if (pBeamInfo->beamformee_su_cnt == 0) { /* For 2->1 entry, we should not cancel SW timer */ + phydm_beamforming_EndPeriod_SW(pDM_Odm); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: No BFee left\n", __func__)); + } + } + break; + + case BEAMFORMEE_NOTIFY_ADD_MU: + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_ADD_MU\n", __func__)); + if (pBeamInfo->beamformee_mu_cnt == 2) { + /*if (pSoundInfo->SoundMode == SOUNDING_SW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_SW_HT_TIMER) + ODM_SetTimer(pDM_Odm, &pBeamInfo->BeamformingTimer, pSoundInfo->SoundPeriod);*/ + ODM_SetTimer(pDM_Odm, &pBeamInfo->BeamformingTimer, 1000); /*Do MU sounding every 1sec*/ + } else + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Less or larger than 2 MU STAs, not to set timer\n", __func__)); + break; + + case BEAMFORMEE_NOTIFY_DELETE_MU: + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: BEAMFORMEE_NOTIFY_DELETE_MU\n", __func__)); + if (pBeamInfo->beamformee_mu_cnt == 1) { + /*if (pSoundInfo->SoundMode == SOUNDING_SW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_SW_HT_TIMER)*/{ + ODM_CancelTimer(pDM_Odm, &pBeamInfo->BeamformingTimer); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Less than 2 MU STAs, stop sounding\n", __func__)); + } + } + break; + + case BEAMFORMING_NOTIFY_RESET: + if (pSoundInfo->SoundMode == SOUNDING_FW_HT_TIMER || pSoundInfo->SoundMode == SOUNDING_FW_VHT_TIMER) { + phydm_beamforming_ClearEntry_FW(pDM_Odm, FALSE, Idx); + phydm_beamforming_EndPeriod_FW(pDM_Odm); + } else { + phydm_beamforming_ClearEntry_SW(pDM_Odm, FALSE, Idx); + phydm_beamforming_EndPeriod_SW(pDM_Odm); + } + + break; + + default: + break; + } + +} + + + +BOOLEAN +Beamforming_InitEntry( + IN PVOID pDM_VOID, + IN u2Byte staIdx, + pu1Byte BFerBFeeIdx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMEE_ENTRY pBeamformEntry = NULL; + PRT_BEAMFORMER_ENTRY pBeamformerEntry = NULL; + PRT_BEAMFORM_STAINFO pSTA = NULL; + BEAMFORMING_CAP BeamformCap = BEAMFORMING_CAP_NONE; + u1Byte BFerIdx=0xF, BFeeIdx=0xF; + u1Byte NumofSoundingDim = 0, CompSteeringNumofBFer = 0; + + pSTA = phydm_staInfoInit(pDM_Odm, staIdx); + + /*The current setting does not support Beaforming*/ + if (BEAMFORMING_CAP_NONE == pSTA->HtBeamformCap && BEAMFORMING_CAP_NONE == pSTA->VhtBeamformCap) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("The configuration disabled Beamforming! Skip...\n")); + return FALSE; + } + + if (pSTA->WirelessMode < WIRELESS_MODE_N_24G) + return FALSE; + else { /*HT*/ + /*We are Beamformee because the STA is Beamformer*/ + if (TEST_FLAG(pSTA->CurBeamform, BEAMFORMING_HT_BEAMFORMER_ENABLE)) { + BeamformCap =(BEAMFORMING_CAP)(BeamformCap |BEAMFORMEE_CAP_HT_EXPLICIT); + NumofSoundingDim = (pSTA->CurBeamform&BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP)>>6; + } + /*We are Beamformer because the STA is Beamformee*/ + if (TEST_FLAG(pSTA->CurBeamform, BEAMFORMING_HT_BEAMFORMEE_ENABLE) || + TEST_FLAG(pSTA->HtBeamformCap, BEAMFORMING_HT_BEAMFORMER_TEST)) { + BeamformCap =(BEAMFORMING_CAP)(BeamformCap | BEAMFORMER_CAP_HT_EXPLICIT); + CompSteeringNumofBFer = (pSTA->CurBeamform & BEAMFORMING_HT_BEAMFORMER_STEER_NUM)>>4; + } + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] HT CurBeamform=0x%X, BeamformCap=0x%X\n", __func__, pSTA->CurBeamform, BeamformCap)); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] HT NumofSoundingDim=%d, CompSteeringNumofBFer=%d\n", __func__, NumofSoundingDim, CompSteeringNumofBFer)); +#if (ODM_IC_11AC_SERIES_SUPPORT == 1) + if (pSTA->WirelessMode & WIRELESS_MODE_AC_5G || pSTA->WirelessMode & WIRELESS_MODE_AC_24G) { /*VHT*/ + + /* We are Beamformee because the STA is SU Beamformer*/ + if (TEST_FLAG(pSTA->CurBeamformVHT, BEAMFORMING_VHT_BEAMFORMER_ENABLE)) { + BeamformCap =(BEAMFORMING_CAP)(BeamformCap |BEAMFORMEE_CAP_VHT_SU); + NumofSoundingDim = (pSTA->CurBeamformVHT & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM)>>12; + } + /* We are Beamformer because the STA is SU Beamformee*/ + if (TEST_FLAG(pSTA->CurBeamformVHT, BEAMFORMING_VHT_BEAMFORMEE_ENABLE) || + TEST_FLAG(pSTA->VhtBeamformCap, BEAMFORMING_VHT_BEAMFORMER_TEST)) { + BeamformCap =(BEAMFORMING_CAP)(BeamformCap |BEAMFORMER_CAP_VHT_SU); + CompSteeringNumofBFer = (pSTA->CurBeamformVHT & BEAMFORMING_VHT_BEAMFORMER_STS_CAP)>>8; + } + /* We are Beamformee because the STA is MU Beamformer*/ + if (TEST_FLAG(pSTA->CurBeamformVHT, BEAMFORMING_VHT_MU_MIMO_AP_ENABLE)) { + BeamformCap = (BEAMFORMING_CAP)(BeamformCap | BEAMFORMEE_CAP_VHT_MU); + NumofSoundingDim = (pSTA->CurBeamformVHT & BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM)>>12; + } + /* We are Beamformer because the STA is MU Beamformee*/ + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_AP)) { /* Only AP mode supports to act an MU beamformer */ + if (TEST_FLAG(pSTA->CurBeamformVHT, BEAMFORMING_VHT_MU_MIMO_STA_ENABLE) || + TEST_FLAG(pSTA->VhtBeamformCap, BEAMFORMING_VHT_BEAMFORMER_TEST)) { + BeamformCap = (BEAMFORMING_CAP)(BeamformCap | BEAMFORMER_CAP_VHT_MU); + CompSteeringNumofBFer = (pSTA->CurBeamformVHT & BEAMFORMING_VHT_BEAMFORMER_STS_CAP)>>8; + } + } + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]VHT CurBeamformVHT=0x%X, BeamformCap=0x%X\n", __func__, pSTA->CurBeamformVHT, BeamformCap)); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]VHT NumofSoundingDim=0x%X, CompSteeringNumofBFer=0x%X\n", __func__, NumofSoundingDim, CompSteeringNumofBFer)); + + } +#endif + } + + + if(BeamformCap == BEAMFORMING_CAP_NONE) + return FALSE; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Self BF Entry Cap = 0x%02X\n", __func__, BeamformCap)); + + /*We are BFee, so the entry is BFer*/ + if (BeamformCap & (BEAMFORMEE_CAP_VHT_MU | BEAMFORMEE_CAP_VHT_SU | BEAMFORMEE_CAP_HT_EXPLICIT)) { + pBeamformerEntry = phydm_Beamforming_GetBFerEntryByAddr(pDM_Odm, pSTA->RA, &BFerIdx); + + if (pBeamformerEntry == NULL) { + pBeamformerEntry = Beamforming_AddBFerEntry(pDM_Odm, pSTA, BeamformCap, NumofSoundingDim , &BFerIdx); + if (pBeamformerEntry == NULL) + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Not enough BFer entry!!!!!\n", __func__)); + } + } + + /*We are BFer, so the entry is BFee*/ + if (BeamformCap & (BEAMFORMER_CAP_VHT_MU | BEAMFORMER_CAP_VHT_SU | BEAMFORMER_CAP_HT_EXPLICIT)) { + pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, pSTA->RA, &BFeeIdx); + + /*pGBFeeIdx = 0xF hNثeentrySۦPMACIDb*/ + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Get BFee entry 0x%X by address\n", __func__, BFeeIdx)); + if (pBeamformEntry == NULL) { + pBeamformEntry = Beamforming_AddBFeeEntry(pDM_Odm, pSTA, BeamformCap, NumofSoundingDim, CompSteeringNumofBFer, &BFeeIdx); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]: pSTA->AID=%d, pSTA->MacID=%d\n", __func__, pSTA->AID, pSTA->MacID)); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]: Add BFee entry %d\n", __func__, BFeeIdx)); + + if (pBeamformEntry == NULL) + return FALSE; + else + pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZEING; + } else { + /*Entry has been created. If entry is initialing or progressing then errors occur.*/ + if (pBeamformEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_INITIALIZED && + pBeamformEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_PROGRESSED) { + return FALSE; + } else + pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZEING; + } + pBeamformEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZED; + phydm_staInfoUpdate(pDM_Odm, staIdx, pBeamformEntry); + } + + *BFerBFeeIdx = (BFerIdx<<4) | BFeeIdx; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End: BFerIdx=0x%X, BFeeIdx=0x%X, BFerBFeeIdx=0x%X\n", __func__, BFerIdx, BFeeIdx, *BFerBFeeIdx)); + + return TRUE; +} + + +VOID +Beamforming_DeInitEntry( + IN PVOID pDM_VOID, + pu1Byte RA + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte Idx = 0; + + PRT_BEAMFORMER_ENTRY pBFerEntry = phydm_Beamforming_GetBFerEntryByAddr(pDM_Odm, RA, &Idx); + PRT_BEAMFORMEE_ENTRY pBFeeEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); + BOOLEAN ret = FALSE; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + if (pBFeeEntry != NULL) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, pBFeeEntry\n", __func__)); + pBFeeEntry->bUsed = FALSE; + pBFeeEntry->BeamformEntryCap = BEAMFORMING_CAP_NONE; + pBFeeEntry->bBeamformingInProgress = FALSE; + if (pBFeeEntry->is_mu_sta) { + pDM_Odm->BeamformingInfo.beamformee_mu_cnt -= 1; + pDM_Odm->BeamformingInfo.FirstMUBFeeIndex = phydm_Beamforming_GetFirstMUBFeeEntryIdx(pDM_Odm); + } else { + pDM_Odm->BeamformingInfo.beamformee_su_cnt -= 1; + } + ret = TRUE; + } + + if (pBFerEntry != NULL) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, pBFerEntry\n", __func__)); + pBFerEntry->bUsed = FALSE; + pBFerEntry->BeamformEntryCap = BEAMFORMING_CAP_NONE; + if (pBFerEntry->is_mu_ap) + pDM_Odm->BeamformingInfo.beamformer_mu_cnt -= 1; + else + pDM_Odm->BeamformingInfo.beamformer_su_cnt -= 1; + ret = TRUE; + } + + if (ret == TRUE) + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_LEAVE, (pu1Byte)&Idx); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s End, Idx = 0x%X\n", __func__, Idx)); +} + + +VOID +Beamforming_Reset( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte Idx = 0; + PRT_BEAMFORMING_INFO pBeamformingInfo = &(pDM_Odm->BeamformingInfo); + + for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { + if (pBeamformingInfo->BeamformeeEntry[Idx].bUsed == TRUE) { + pBeamformingInfo->BeamformeeEntry[Idx].bUsed = FALSE; + pBeamformingInfo->BeamformeeEntry[Idx].BeamformEntryCap = BEAMFORMING_CAP_NONE; + /*pBeamformingInfo->BeamformeeEntry[Idx].BeamformEntryState = BEAMFORMING_ENTRY_STATE_UNINITIALIZE;*/ + /*Modified by David*/ + pBeamformingInfo->BeamformeeEntry[Idx].bBeamformingInProgress = FALSE; + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_LEAVE, (pu1Byte)&Idx); + } + } + + for (Idx = 0; Idx < BEAMFORMER_ENTRY_NUM; Idx++) { + pBeamformingInfo->BeamformerEntry[Idx].bUsed = FALSE; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Idx=%d, bUsed=%d\n", __func__, Idx, pBeamformingInfo->BeamformerEntry[Idx].bUsed)); + } + +} + + +BOOLEAN +BeamformingStart_V1( + IN PVOID pDM_VOID, + pu1Byte RA, + BOOLEAN Mode, + CHANNEL_WIDTH BW, + u1Byte Rate + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte Idx = 0; + PRT_BEAMFORMEE_ENTRY pEntry; + BOOLEAN ret = TRUE; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + + pEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); + + if (pEntry->bUsed == FALSE) { + pEntry->bBeamformingInProgress = FALSE; + return FALSE; + } else { + if (pEntry->bBeamformingInProgress) + return FALSE; + + pEntry->bBeamformingInProgress = TRUE; + + if (Mode == 1) { + if (!(pEntry->BeamformEntryCap & BEAMFORMER_CAP_HT_EXPLICIT)) { + pEntry->bBeamformingInProgress = FALSE; + return FALSE; + } + } else if (Mode == 0) { + if (!(pEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU)) { + pEntry->bBeamformingInProgress = FALSE; + return FALSE; + } + } + + if (pEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_INITIALIZED && pEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_PROGRESSED) { + pEntry->bBeamformingInProgress = FALSE; + return FALSE; + } else { + pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSING; + pEntry->bSound = TRUE; + } + } + + pEntry->SoundBW = BW; + pBeamInfo->BeamformeeCurIdx = Idx; + phydm_Beamforming_NDPARate(pDM_Odm, BW, Rate); + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_STATUS, (pu1Byte)&Idx); + + if (Mode == 1) + ret = Beamforming_SendHTNDPAPacket(pDM_Odm, RA, BW, NORMAL_QUEUE); + else + ret = Beamforming_SendVHTNDPAPacket(pDM_Odm, RA, pEntry->AID, BW, NORMAL_QUEUE); + + if (ret == FALSE) { + Beamforming_Leave(pDM_Odm, RA); + pEntry->bBeamformingInProgress = FALSE; + return FALSE; + } + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Idx %d\n", __func__, Idx)); + return TRUE; +} + + +BOOLEAN +BeamformingStart_SW( + IN PVOID pDM_VOID, + u1Byte Idx, + u1Byte Mode, + CHANNEL_WIDTH BW + ) +{ + pu1Byte RA = NULL; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMEE_ENTRY pEntry; + BOOLEAN ret = TRUE; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + + pEntry = &(pBeamInfo->BeamformeeEntry[Idx]); + + if (pEntry->bUsed == FALSE) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Skip Beamforming, no entry for Idx =%d\n", Idx)); + pEntry->bBeamformingInProgress = FALSE; + return FALSE; + } else { + if (pEntry->bBeamformingInProgress) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("bBeamformingInProgress, skip...\n")); + return FALSE; + } + + pEntry->bBeamformingInProgress = TRUE; + RA = pEntry->MacAddr; + + if (Mode == SOUNDING_SW_HT_TIMER || Mode == SOUNDING_HW_HT_TIMER || Mode == SOUNDING_AUTO_HT_TIMER) { + if (!(pEntry->BeamformEntryCap & BEAMFORMER_CAP_HT_EXPLICIT)) { + pEntry->bBeamformingInProgress = FALSE; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Return by not support BEAMFORMER_CAP_HT_EXPLICIT <==\n", __func__)); + return FALSE; + } + } else if (Mode == SOUNDING_SW_VHT_TIMER || Mode == SOUNDING_HW_VHT_TIMER || Mode == SOUNDING_AUTO_VHT_TIMER) { + if (!(pEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU)) { + pEntry->bBeamformingInProgress = FALSE; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Return by not support BEAMFORMER_CAP_VHT_SU <==\n", __func__)); + return FALSE; + } + } + if (pEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_INITIALIZED && pEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_PROGRESSED) { + pEntry->bBeamformingInProgress = FALSE; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Return by incorrect BeamformEntryState(%d) <==\n", __func__, pEntry->BeamformEntryState)); + return FALSE; + } else { + pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSING; + pEntry->bSound = TRUE; + } + } + + pBeamInfo->BeamformeeCurIdx = Idx; + /*2014.12.22 Luke: Need to be checked*/ + /*GET_TXBF_INFO(Adapter)->fTxbfSet(Adapter, TXBF_SET_SOUNDING_STATUS, (pu1Byte)&Idx);*/ + + if (Mode == SOUNDING_SW_HT_TIMER || Mode == SOUNDING_HW_HT_TIMER || Mode == SOUNDING_AUTO_HT_TIMER) + ret = Beamforming_SendHTNDPAPacket(pDM_Odm, RA , BW, NORMAL_QUEUE); + else + ret = Beamforming_SendVHTNDPAPacket(pDM_Odm, RA , pEntry->AID, BW, NORMAL_QUEUE); + + if (ret == FALSE) { + Beamforming_Leave(pDM_Odm, RA); + pEntry->bBeamformingInProgress = FALSE; + return FALSE; + } + + + /*-------------------------- + // Send BF Report Poll for MU BF + --------------------------*/ +#ifdef SUPPORT_MU_BF +#if (SUPPORT_MU_BF == 1) +{ + u1Byte idx, PollSTACnt = 0; + BOOLEAN bGetFirstBFee = FALSE; + + if (pBeamInfo->beamformee_mu_cnt > 1) { /* More than 1 MU STA*/ + + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + pEntry = &(pBeamInfo->BeamformeeEntry[idx]); + if (pEntry->is_mu_sta) { + if (bGetFirstBFee) { + PollSTACnt++; + if (PollSTACnt == (pBeamInfo->beamformee_mu_cnt - 1))/* The last STA*/ + SendSWVHTBFReportPoll(pDM_Odm, pEntry->MacAddr, TRUE); + else + SendSWVHTBFReportPoll(pDM_Odm, pEntry->MacAddr, FALSE); + } else { + bGetFirstBFee = TRUE; + } + } + } + } +} +#endif +#endif + return TRUE; +} + + +BOOLEAN +BeamformingStart_FW( + IN PVOID pDM_VOID, + u1Byte Idx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pu1Byte RA = NULL; + PRT_BEAMFORMEE_ENTRY pEntry; + BOOLEAN ret = TRUE; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + + pEntry = &(pBeamInfo->BeamformeeEntry[Idx]); + if (pEntry->bUsed == FALSE) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Skip Beamforming, no entry for Idx =%d\n", Idx)); + return FALSE; + } + + pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSING; + pEntry->bSound = TRUE; + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_FW_NDPA, (pu1Byte)&Idx); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End, Idx=0x%X\n", __func__, Idx)); + return TRUE; +} + +VOID +Beamforming_CheckSoundingSuccess( + IN PVOID pDM_VOID, + BOOLEAN Status +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PRT_BEAMFORMEE_ENTRY pEntry = &(pBeamInfo->BeamformeeEntry[pBeamInfo->BeamformeeCurIdx]); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[David]@%s Start!\n", __func__)); + + if (Status == 1) { + if (pEntry->LogStatusFailCnt == 21) + Beamforming_DymPeriod(pDM_Odm, Status); + pEntry->LogStatusFailCnt = 0; + } else if (pEntry->LogStatusFailCnt <= 20) { + pEntry->LogStatusFailCnt++; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s LogStatusFailCnt %d\n", __func__, pEntry->LogStatusFailCnt)); + } + if (pEntry->LogStatusFailCnt > 20) { + pEntry->LogStatusFailCnt = 21; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s LogStatusFailCnt > 20, Stop SOUNDING\n", __func__)); + Beamforming_DymPeriod(pDM_Odm, Status); + } +} + +VOID +phydm_Beamforming_End_SW( + IN PVOID pDM_VOID, + BOOLEAN Status + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMEE_ENTRY pEntry = &(pBeamInfo->BeamformeeEntry[pBeamInfo->BeamformeeCurIdx]); + + if (pEntry->BeamformEntryState != BEAMFORMING_ENTRY_STATE_PROGRESSING) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BeamformStatus %d\n", __func__, pEntry->BeamformEntryState)); + return; + } + + if ((pDM_Odm->TxBfDataRate >= ODM_RATEVHTSS3MCS7) && (pDM_Odm->TxBfDataRate <= ODM_RATEVHTSS3MCS9)) { + ODM_RT_TRACE(pDM_Odm, BEAMFORMING_DEBUG, ODM_DBG_LOUD, ("[%s] VHT3SS 7,8,9, do not apply V matrix.\n", __func__)); + pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZED; + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_STATUS, (pu1Byte)&(pBeamInfo->BeamformeeCurIdx)); + } else if (Status == 1) { + pEntry->LogStatusFailCnt = 0; + pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED; + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_STATUS, (pu1Byte)&(pBeamInfo->BeamformeeCurIdx)); + } else { + pEntry->LogStatusFailCnt++; + pEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_INITIALIZED; + HalComTxbf_Set(pDM_Odm, TXBF_SET_TX_PATH_RESET, (pu1Byte)&(pBeamInfo->BeamformeeCurIdx)); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] LogStatusFailCnt %d\n", __func__, pEntry->LogStatusFailCnt)); + } + + if (pEntry->LogStatusFailCnt > 30) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s LogStatusFailCnt > 50, Stop SOUNDING\n", __func__)); + pEntry->bSound = FALSE; + Beamforming_DeInitEntry(pDM_Odm, pEntry->MacAddr); + + /*Modified by David - Every action of deleting entry should follow by Notify*/ + phydm_Beamforming_Notify(pDM_Odm); + } + pEntry->bBeamformingInProgress = FALSE; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: Status=%d\n", __func__, Status)); +} + + +VOID +Beamforming_TimerCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PVOID pDM_VOID +#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) + IN PVOID pContext +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; +#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) + PADAPTER Adapter = (PADAPTER)pContext; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif + BOOLEAN ret = FALSE; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PRT_BEAMFORMEE_ENTRY pEntry = &(pBeamInfo->BeamformeeEntry[pBeamInfo->BeamformeeCurIdx]); + PRT_SOUNDING_INFO pSoundInfo = &(pBeamInfo->SoundingInfo); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + if (pEntry->bBeamformingInProgress) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("bBeamformingInProgress, reset it\n")); + phydm_Beamforming_End_SW(pDM_Odm, 0); + } + + ret = phydm_Beamforming_SelectBeamEntry(pDM_Odm, pBeamInfo); +#if (SUPPORT_MU_BF == 1) + if (ret && pBeamInfo->beamformee_mu_cnt > 1) + ret = 1; + else + ret = 0; +#endif + if (ret) + ret = BeamformingStart_SW(pDM_Odm, pSoundInfo->SoundIdx, pSoundInfo->SoundMode, pSoundInfo->SoundBW); + else + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s, Error value return from BeamformingStart_V2\n", __func__)); + + if ((pBeamInfo->beamformee_su_cnt != 0) || (pBeamInfo->beamformee_mu_cnt > 1)) { + if (pSoundInfo->SoundMode == SOUNDING_SW_VHT_TIMER || pSoundInfo->SoundMode == SOUNDING_SW_HT_TIMER) + ODM_SetTimer(pDM_Odm, &pBeamInfo->BeamformingTimer, pSoundInfo->SoundPeriod); + else { + u4Byte val = (pSoundInfo->SoundPeriod << 16) | HAL_TIMER_TXBF; + Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_HW_REG_TIMER_RESTART, (pu1Byte)(&val)); + } + } +} + + +VOID +Beamforming_SWTimerCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PRT_TIMER pTimer +#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) + void *FunctionContext +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = (PADAPTER)pTimer->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + Beamforming_TimerCallback(pDM_Odm); +#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)FunctionContext; + PADAPTER Adapter = pDM_Odm->Adapter; + + if (Adapter->net_closed == TRUE) + return; + rtw_run_in_thread_cmd(Adapter, Beamforming_TimerCallback, Adapter); +#endif + +} + + +VOID +phydm_Beamforming_Init( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PHAL_TXBF_INFO pTxbfInfo = &pBeamInfo->TxbfInfo; + PRT_BEAMFORMING_OID_INFO pBeamOidInfo = &(pBeamInfo->BeamformingOidInfo); + + pBeamOidInfo->SoundOidMode = SOUNDING_STOP_OID_TIMER; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Mode (%d)\n", __func__, pBeamOidInfo->SoundOidMode)); + + pBeamInfo->beamformee_su_cnt = 0; + pBeamInfo->beamformer_su_cnt = 0; + pBeamInfo->beamformee_mu_cnt = 0; + pBeamInfo->beamformer_mu_cnt = 0; + pBeamInfo->beamformee_mu_reg_maping = 0; + pBeamInfo->mu_ap_index = 0; + pBeamInfo->is_mu_sounding = FALSE; + pBeamInfo->FirstMUBFeeIndex = 0xFF; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + pBeamInfo->SourceAdapter = pDM_Odm->Adapter; +#endif + halComTxbf_beamformInit(pDM_Odm); +} + + +VOID +Beamforming_Enter( + IN PVOID pDM_VOID, + IN u2Byte staIdx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte BFerBFeeIdx = 0xff; + + if (Beamforming_InitEntry(pDM_Odm, staIdx, &BFerBFeeIdx)) + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_ENTER, (pu1Byte)&BFerBFeeIdx); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End!\n", __func__)); +} + + +VOID +Beamforming_Leave( + IN PVOID pDM_VOID, + pu1Byte RA + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (RA == NULL) + Beamforming_Reset(pDM_Odm); + else + Beamforming_DeInitEntry(pDM_Odm, RA); + + phydm_Beamforming_Notify(pDM_Odm); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End!!\n", __func__)); +} + +#if 0 +//Nobody calls this function +VOID +phydm_Beamforming_SetTxBFen( + IN PVOID pDM_VOID, + u1Byte MacId, + BOOLEAN bTxBF + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte Idx = 0; + PRT_BEAMFORMEE_ENTRY pEntry; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + pEntry = phydm_Beamforming_GetEntryByMacId(pDM_Odm, MacId, &Idx); + + if(pEntry == NULL) + return; + else + pEntry->bTxBF = bTxBF; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s MacId %d TxBF %d\n", __func__, pEntry->MacId, pEntry->bTxBF)); + + phydm_Beamforming_Notify(pDM_Odm); +} +#endif + +BEAMFORMING_CAP +phydm_Beamforming_GetBeamCap( + IN PVOID pDM_VOID, + IN PRT_BEAMFORMING_INFO pBeamInfo + ) +{ + u1Byte i; + BOOLEAN bSelfBeamformer = FALSE; + BOOLEAN bSelfBeamformee = FALSE; + RT_BEAMFORMEE_ENTRY BeamformeeEntry; + RT_BEAMFORMER_ENTRY BeamformerEntry; + BEAMFORMING_CAP BeamformCap = BEAMFORMING_CAP_NONE; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { + BeamformeeEntry = pBeamInfo->BeamformeeEntry[i]; + + if (BeamformeeEntry.bUsed) { + bSelfBeamformer = TRUE; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BFee entry %d bUsed=TRUE\n", __func__, i)); + break; + } + } + + for (i = 0; i < BEAMFORMER_ENTRY_NUM; i++) { + BeamformerEntry = pBeamInfo->BeamformerEntry[i]; + + if (BeamformerEntry.bUsed) { + bSelfBeamformee = TRUE; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]: BFer entry %d bUsed=TRUE\n", __func__, i)); + break; + } + } + + if (bSelfBeamformer) + BeamformCap = (BEAMFORMING_CAP)(BeamformCap | BEAMFORMER_CAP); + if (bSelfBeamformee) + BeamformCap = (BEAMFORMING_CAP)(BeamformCap | BEAMFORMEE_CAP); + + return BeamformCap; +} + + +BOOLEAN +BeamformingControl_V1( + IN PVOID pDM_VOID, + pu1Byte RA, + u1Byte AID, + u1Byte Mode, + CHANNEL_WIDTH BW, + u1Byte Rate + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + BOOLEAN ret = TRUE; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("AID (%d), Mode (%d), BW (%d)\n", AID, Mode, BW)); + + switch (Mode) { + case 0: + ret = BeamformingStart_V1(pDM_Odm, RA, 0, BW, Rate); + break; + case 1: + ret = BeamformingStart_V1(pDM_Odm, RA, 1, BW, Rate); + break; + case 2: + phydm_Beamforming_NDPARate(pDM_Odm, BW, Rate); + ret = Beamforming_SendVHTNDPAPacket(pDM_Odm, RA, AID, BW, NORMAL_QUEUE); + break; + case 3: + phydm_Beamforming_NDPARate(pDM_Odm, BW, Rate); + ret = Beamforming_SendHTNDPAPacket(pDM_Odm, RA, BW, NORMAL_QUEUE); + break; + } + return ret; +} + +/*Only OID uses this function*/ +BOOLEAN +phydm_BeamformingControl_V2( + IN PVOID pDM_VOID, + u1Byte Idx, + u1Byte Mode, + CHANNEL_WIDTH BW, + u2Byte Period + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMING_OID_INFO pBeamOidInfo = &(pBeamInfo->BeamformingOidInfo); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Start!\n", __func__)); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Idx (%d), Mode (%d), BW (%d), Period (%d)\n", Idx, Mode, BW, Period)); + + pBeamOidInfo->SoundOidIdx = Idx; + pBeamOidInfo->SoundOidMode = (SOUNDING_MODE) Mode; + pBeamOidInfo->SoundOidBW = BW; + pBeamOidInfo->SoundOidPeriod = Period; + + phydm_Beamforming_Notify(pDM_Odm); + + return TRUE; +} + + +VOID +phydm_Beamforming_Watchdog( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_TRACE, ("%s Start!\n", __func__)); + + if (pBeamInfo->beamformee_su_cnt == 0) + return; + + Beamforming_DymPeriod(pDM_Odm,0); + phydm_Beamforming_DymNDPARate(pDM_Odm); + +} + + +#endif diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_beamforming.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_beamforming.h new file mode 100644 index 000000000..c11084624 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_beamforming.h @@ -0,0 +1,366 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __INC_BEAMFORMING_H +#define __INC_BEAMFORMING_H + +#ifndef BEAMFORMING_SUPPORT +#define BEAMFORMING_SUPPORT 0 +#endif + +/*Beamforming Related*/ +#include "txbf/halcomtxbf.h" +#include "txbf/haltxbfjaguar.h" +#include "txbf/haltxbf8192e.h" +#include "txbf/haltxbf8814a.h" +#include "txbf/haltxbf8821b.h" +#include "txbf/haltxbf8822b.h" +#include "txbf/haltxbfinterface.h" + +#if (BEAMFORMING_SUPPORT == 1) + +#define MAX_BEAMFORMEE_SU 2 +#define MAX_BEAMFORMER_SU 2 +#if (RTL8822B_SUPPORT == 1) +#define MAX_BEAMFORMEE_MU 6 +#define MAX_BEAMFORMER_MU 1 +#else +#define MAX_BEAMFORMEE_MU 0 +#define MAX_BEAMFORMER_MU 0 +#endif + +#define BEAMFORMEE_ENTRY_NUM (MAX_BEAMFORMEE_SU + MAX_BEAMFORMEE_MU) +#define BEAMFORMER_ENTRY_NUM (MAX_BEAMFORMER_SU + MAX_BEAMFORMER_MU) + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +/*for different naming between WIN and CE*/ +#define BEACON_QUEUE BCN_QUEUE_INX +#define NORMAL_QUEUE MGT_QUEUE_INX +#define RT_DISABLE_FUNC RTW_DISABLE_FUNC +#define RT_ENABLE_FUNC RTW_ENABLE_FUNC +#endif + +typedef enum _BEAMFORMING_ENTRY_STATE { + BEAMFORMING_ENTRY_STATE_UNINITIALIZE, + BEAMFORMING_ENTRY_STATE_INITIALIZEING, + BEAMFORMING_ENTRY_STATE_INITIALIZED, + BEAMFORMING_ENTRY_STATE_PROGRESSING, + BEAMFORMING_ENTRY_STATE_PROGRESSED +} BEAMFORMING_ENTRY_STATE, *PBEAMFORMING_ENTRY_STATE; + + +typedef enum _BEAMFORMING_NOTIFY_STATE { + BEAMFORMING_NOTIFY_NONE, + BEAMFORMING_NOTIFY_ADD, + BEAMFORMING_NOTIFY_DELETE, + BEAMFORMEE_NOTIFY_ADD_SU, + BEAMFORMEE_NOTIFY_DELETE_SU, + BEAMFORMEE_NOTIFY_ADD_MU, + BEAMFORMEE_NOTIFY_DELETE_MU, + BEAMFORMING_NOTIFY_RESET +} BEAMFORMING_NOTIFY_STATE, *PBEAMFORMING_NOTIFY_STATE; + +typedef enum _BEAMFORMING_CAP { + BEAMFORMING_CAP_NONE = 0x0, + BEAMFORMER_CAP_HT_EXPLICIT = BIT1, + BEAMFORMEE_CAP_HT_EXPLICIT = BIT2, + BEAMFORMER_CAP_VHT_SU = BIT5, /* Self has er Cap, because Reg er & peer ee */ + BEAMFORMEE_CAP_VHT_SU = BIT6, /* Self has ee Cap, because Reg ee & peer er */ + BEAMFORMER_CAP_VHT_MU = BIT7, /* Self has er Cap, because Reg er & peer ee */ + BEAMFORMEE_CAP_VHT_MU = BIT8, /* Self has ee Cap, because Reg ee & peer er */ + BEAMFORMER_CAP = BIT9, + BEAMFORMEE_CAP = BIT10, +}BEAMFORMING_CAP, *PBEAMFORMING_CAP; + + +typedef enum _SOUNDING_MODE { + SOUNDING_SW_VHT_TIMER = 0x0, + SOUNDING_SW_HT_TIMER = 0x1, + SOUNDING_STOP_All_TIMER = 0x2, + SOUNDING_HW_VHT_TIMER = 0x3, + SOUNDING_HW_HT_TIMER = 0x4, + SOUNDING_STOP_OID_TIMER = 0x5, + SOUNDING_AUTO_VHT_TIMER = 0x6, + SOUNDING_AUTO_HT_TIMER = 0x7, + SOUNDING_FW_VHT_TIMER = 0x8, + SOUNDING_FW_HT_TIMER = 0x9, +}SOUNDING_MODE, *PSOUNDING_MODE; + +typedef struct _RT_BEAMFORM_STAINFO { + pu1Byte RA; + u2Byte AID; + u2Byte MacID; + u1Byte MyMacAddr[6]; + WIRELESS_MODE WirelessMode; + CHANNEL_WIDTH BW; + BEAMFORMING_CAP BeamformCap; + u1Byte HtBeamformCap; + u2Byte VhtBeamformCap; + u1Byte CurBeamform; + u2Byte CurBeamformVHT; +} RT_BEAMFORM_STAINFO, *PRT_BEAMFORM_STAINFO; + + +typedef struct _RT_BEAMFORMEE_ENTRY { + BOOLEAN bUsed; + BOOLEAN bTxBF; + BOOLEAN bSound; + u2Byte AID; /*Used to construct AID field of NDPA packet.*/ + u2Byte MacId; /*Used to Set Reg42C in IBSS mode. */ + u2Byte P_AID; /*Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */ + u2Byte G_ID; /*Used to fill Tx DESC*/ + u1Byte MyMacAddr[6]; + u1Byte MacAddr[6]; /*Used to fill Reg6E4 to fill Mac address of CSI report frame.*/ + CHANNEL_WIDTH SoundBW; /*Sounding BandWidth*/ + u2Byte SoundPeriod; + BEAMFORMING_CAP BeamformEntryCap; + BEAMFORMING_ENTRY_STATE BeamformEntryState; + BOOLEAN bBeamformingInProgress; + /*u1Byte LogSeq; // Move to _RT_BEAMFORMER_ENTRY*/ + /*u2Byte LogRetryCnt:3; // 0~4 // Move to _RT_BEAMFORMER_ENTRY*/ + /*u2Byte LogSuccessCnt:2; // 0~2 // Move to _RT_BEAMFORMER_ENTRY*/ + u2Byte LogStatusFailCnt:5; // 0~21 + u2Byte DefaultCSICnt:5; // 0~21 + u1Byte CSIMatrix[327]; + u2Byte CSIMatrixLen; + u1Byte NumofSoundingDim; + u1Byte CompSteeringNumofBFer; + u1Byte su_reg_index; + /*For MU-MIMO*/ + BOOLEAN is_mu_sta; + u1Byte mu_reg_index; + u1Byte gid_valid[8]; + u1Byte user_position[16]; +} RT_BEAMFORMEE_ENTRY, *PRT_BEAMFORMEE_ENTRY; + +typedef struct _RT_BEAMFORMER_ENTRY { + BOOLEAN bUsed; + /*P_AID of BFer entry is probably not used*/ + u2Byte P_AID; /*Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */ + u2Byte G_ID; + u1Byte MyMacAddr[6]; + u1Byte MacAddr[6]; + BEAMFORMING_CAP BeamformEntryCap; + u1Byte NumofSoundingDim; + u1Byte ClockResetTimes; /*Modified by Jeffery @2015-04-10*/ + u1Byte PreLogSeq; /*Modified by Jeffery @2015-03-30*/ + u1Byte LogSeq; /*Modified by Jeffery @2014-10-29*/ + u2Byte LogRetryCnt:3; /*Modified by Jeffery @2014-10-29*/ + u2Byte LogSuccess:2; /*Modified by Jeffery @2014-10-29*/ + u1Byte su_reg_index; + /*For MU-MIMO*/ + BOOLEAN is_mu_ap; + u1Byte gid_valid[8]; + u1Byte user_position[16]; + u2Byte AID; +} RT_BEAMFORMER_ENTRY, *PRT_BEAMFORMER_ENTRY; + +typedef struct _RT_SOUNDING_INFO { + u1Byte SoundIdx; + CHANNEL_WIDTH SoundBW; + SOUNDING_MODE SoundMode; + u2Byte SoundPeriod; +} RT_SOUNDING_INFO, *PRT_SOUNDING_INFO; + + + +typedef struct _RT_BEAMFORMING_OID_INFO { + u1Byte SoundOidIdx; + CHANNEL_WIDTH SoundOidBW; + SOUNDING_MODE SoundOidMode; + u2Byte SoundOidPeriod; +} RT_BEAMFORMING_OID_INFO, *PRT_BEAMFORMING_OID_INFO; + + +typedef struct _RT_BEAMFORMING_INFO { + BEAMFORMING_CAP BeamformCap; + RT_BEAMFORMEE_ENTRY BeamformeeEntry[BEAMFORMEE_ENTRY_NUM]; + RT_BEAMFORMER_ENTRY BeamformerEntry[BEAMFORMER_ENTRY_NUM]; + RT_BEAMFORM_STAINFO BeamformSTAinfo; + u1Byte BeamformeeCurIdx; + RT_TIMER BeamformingTimer; + RT_TIMER mu_timer; + RT_SOUNDING_INFO SoundingInfo; + RT_BEAMFORMING_OID_INFO BeamformingOidInfo; + HAL_TXBF_INFO TxbfInfo; + u1Byte SoundingSequence; + u1Byte beamformee_su_cnt; + u1Byte beamformer_su_cnt; + u4Byte beamformee_su_reg_maping; + u4Byte beamformer_su_reg_maping; + /*For MU-MINO*/ + u1Byte beamformee_mu_cnt; + u1Byte beamformer_mu_cnt; + u4Byte beamformee_mu_reg_maping; + u1Byte mu_ap_index; + BOOLEAN is_mu_sounding; + u1Byte FirstMUBFeeIndex; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER SourceAdapter; +#endif + /* Control register */ + u4Byte RegMUTxCtrl; /* For USB/SDIO interfaces aync I/O */ +} RT_BEAMFORMING_INFO, *PRT_BEAMFORMING_INFO; + + +typedef struct _RT_NDPA_STA_INFO { + u2Byte AID:12; + u2Byte FeedbackType:1; + u2Byte NcIndex:3; +} RT_NDPA_STA_INFO, *PRT_NDPA_STA_INFO; + + +BEAMFORMING_CAP +phydm_Beamforming_GetEntryBeamCapByMacId( + IN PVOID pDM_VOID, + IN u1Byte MacId + ); + +PRT_BEAMFORMEE_ENTRY +phydm_Beamforming_GetBFeeEntryByAddr( + IN PVOID pDM_VOID, + IN pu1Byte RA, + OUT pu1Byte Idx + ); + +PRT_BEAMFORMER_ENTRY +phydm_Beamforming_GetBFerEntryByAddr( + IN PVOID pDM_VOID, + IN pu1Byte TA, + OUT pu1Byte Idx + ); + +u1Byte +Beamforming_GetHTNDPTxRate( + IN PVOID pDM_VOID, + u1Byte CompSteeringNumofBFer +); + +u1Byte +Beamforming_GetVHTNDPTxRate( + IN PVOID pDM_VOID, + u1Byte CompSteeringNumofBFer +); + +VOID +phydm_Beamforming_Notify( + IN PVOID pDM_VOID + ); + + +VOID +Beamforming_Enter( + IN PVOID pDM_VOID, + IN u2Byte staIdx + ); + +VOID +Beamforming_Leave( + IN PVOID pDM_VOID, + pu1Byte RA + ); + +BOOLEAN +BeamformingStart_FW( + IN PVOID pDM_VOID, + u1Byte Idx + ); + +VOID +Beamforming_CheckSoundingSuccess( + IN PVOID pDM_VOID, + BOOLEAN Status +); + +VOID +phydm_Beamforming_End_SW( + IN PVOID pDM_VOID, + BOOLEAN Status + ); + +VOID +Beamforming_TimerCallback( + IN PVOID pDM_VOID + ); + +VOID +phydm_Beamforming_Init( + IN PVOID pDM_VOID + ); + + + +BEAMFORMING_CAP +phydm_Beamforming_GetBeamCap( + IN PVOID pDM_VOID, + IN PRT_BEAMFORMING_INFO pBeamInfo + ); + + +BOOLEAN +BeamformingControl_V1( + IN PVOID pDM_VOID, + pu1Byte RA, + u1Byte AID, + u1Byte Mode, + CHANNEL_WIDTH BW, + u1Byte Rate + ); + + +BOOLEAN +phydm_BeamformingControl_V2( + IN PVOID pDM_VOID, + u1Byte Idx, + u1Byte Mode, + CHANNEL_WIDTH BW, + u2Byte Period + ); + +VOID +phydm_Beamforming_Watchdog( + IN PVOID pDM_VOID + ); + +VOID +Beamforming_SWTimerCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PRT_TIMER pTimer +#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) + void *FunctionContext +#endif + ); + +BOOLEAN +Beamforming_SendHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN CHANNEL_WIDTH BW, + IN u1Byte QIdx + ); + + +BOOLEAN +Beamforming_SendVHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN u2Byte AID, + IN CHANNEL_WIDTH BW, + IN u1Byte QIdx + ); + +#else +#define Beamforming_GidPAid(Adapter, pTcb) +#define Beamforming_Enter(pDM_Odm, staIdx) +#define Beamforming_Leave(pDM_Odm, RA) +#define Beamforming_End_FW(pDMOdm) +#define BeamformingControl_V1(pDM_Odm, RA, AID, Mode, BW, Rate) TRUE +#define BeamformingControl_V2(pDM_Odm, Idx, Mode, BW, Period) TRUE +#define phydm_Beamforming_End_SW(pDM_Odm, _Status) +#define Beamforming_TimerCallback(pDM_Odm) +#define phydm_Beamforming_Init(pDM_Odm) +#define phydm_BeamformingControl_V2(pDM_Odm, _Idx, _Mode, _BW, _Period) FALSE +#define Beamforming_Watchdog(pDM_Odm) +#define phydm_Beamforming_Watchdog(pDM_Odm) + + +#endif +#endif diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_cfotracking.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_cfotracking.c new file mode 100644 index 000000000..0aa78f17e --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_cfotracking.c @@ -0,0 +1,347 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +VOID +odm_SetCrystalCap( + IN PVOID pDM_VOID, + IN u1Byte CrystalCap +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); + BOOLEAN bEEPROMCheck; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + bEEPROMCheck = (pHalData->EEPROMVersion >= 0x01)?TRUE:FALSE; +#else + bEEPROMCheck = TRUE; +#endif + + if(pCfoTrack->CrystalCap == CrystalCap) + return; + + pCfoTrack->CrystalCap = CrystalCap; + + if (pDM_Odm->SupportICType & (ODM_RTL8188E | ODM_RTL8188F)) { + /* write 0x24[22:17] = 0x24[16:11] = CrystalCap */ + CrystalCap = CrystalCap & 0x3F; + ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x007ff800, (CrystalCap|(CrystalCap << 6))); + } else if (pDM_Odm->SupportICType & ODM_RTL8812) { + /* write 0x2C[30:25] = 0x2C[24:19] = CrystalCap */ + CrystalCap = CrystalCap & 0x3F; + ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x7FF80000, (CrystalCap|(CrystalCap << 6))); + } else if (((pDM_Odm->SupportICType & ODM_RTL8723A) && bEEPROMCheck) || + (pDM_Odm->SupportICType & (ODM_RTL8703B|ODM_RTL8723B|ODM_RTL8192E|ODM_RTL8821))) { + /* 0x2C[23:18] = 0x2C[17:12] = CrystalCap */ + CrystalCap = CrystalCap & 0x3F; + ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x00FFF000, (CrystalCap|(CrystalCap << 6))); + } else if (pDM_Odm->SupportICType & ODM_RTL8821B) { + /* write 0x28[6:1] = 0x24[30:25] = CrystalCap */ + CrystalCap = CrystalCap & 0x3F; + ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x7E000000, CrystalCap); + ODM_SetBBReg(pDM_Odm, REG_AFE_PLL_CTRL, 0x7E, CrystalCap); + } else if (pDM_Odm->SupportICType & ODM_RTL8814A) { + /* write 0x2C[26:21] = 0x2C[20:15] = CrystalCap */ + CrystalCap = CrystalCap & 0x3F; + ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0x07FF8000, (CrystalCap|(CrystalCap << 6))); + } else if (pDM_Odm->SupportICType & ODM_RTL8822B) { + /* write 0x24[30:25] = 0x28[6:1] = CrystalCap */ + CrystalCap = CrystalCap & 0x3F; + ODM_SetBBReg(pDM_Odm, REG_AFE_XTAL_CTRL, 0x7e000000, CrystalCap); + ODM_SetBBReg(pDM_Odm, REG_AFE_PLL_CTRL, 0x7e, CrystalCap); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_SetCrystalCap(): Use default setting.\n")); + ODM_SetBBReg(pDM_Odm, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap|(CrystalCap << 6))); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("odm_SetCrystalCap(): CrystalCap = 0x%x\n", CrystalCap)); +#endif +} + +u1Byte +odm_GetDefaultCrytaltalCap( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte CrystalCap = 0x20; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + CrystalCap = pHalData->CrystalCap; +#else + prtl8192cd_priv priv = pDM_Odm->priv; + + if(priv->pmib->dot11RFEntry.xcap > 0) + CrystalCap = priv->pmib->dot11RFEntry.xcap; +#endif + + CrystalCap = CrystalCap & 0x3f; + + return CrystalCap; +} + +VOID +odm_SetATCStatus( + IN PVOID pDM_VOID, + IN BOOLEAN ATCStatus +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); + + if(pCfoTrack->bATCStatus == ATCStatus) + return; + + ODM_SetBBReg(pDM_Odm, ODM_REG(BB_ATC,pDM_Odm), ODM_BIT(BB_ATC,pDM_Odm), ATCStatus); + pCfoTrack->bATCStatus = ATCStatus; +} + +BOOLEAN +odm_GetATCStatus( + IN PVOID pDM_VOID +) +{ + BOOLEAN ATCStatus; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ATCStatus = (BOOLEAN)ODM_GetBBReg(pDM_Odm, ODM_REG(BB_ATC,pDM_Odm), ODM_BIT(BB_ATC,pDM_Odm)); + return ATCStatus; +} + +VOID +ODM_CfoTrackingReset( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); + + pCfoTrack->DefXCap = odm_GetDefaultCrytaltalCap(pDM_Odm); + pCfoTrack->bAdjust = TRUE; + + if(pCfoTrack->CrystalCap > pCfoTrack->DefXCap) + { + odm_SetCrystalCap(pDM_Odm, pCfoTrack->CrystalCap - 1); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, + ("ODM_CfoTrackingReset(): approch default value (0x%x)\n", pCfoTrack->CrystalCap)); + } else if (pCfoTrack->CrystalCap < pCfoTrack->DefXCap) + { + odm_SetCrystalCap(pDM_Odm, pCfoTrack->CrystalCap + 1); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, + ("ODM_CfoTrackingReset(): approch default value (0x%x)\n", pCfoTrack->CrystalCap)); + } + + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + odm_SetATCStatus(pDM_Odm, TRUE); + #endif +} + +VOID +ODM_CfoTrackingInit( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); + + pCfoTrack->DefXCap = pCfoTrack->CrystalCap = odm_GetDefaultCrytaltalCap(pDM_Odm); + pCfoTrack->bATCStatus = odm_GetATCStatus(pDM_Odm); + pCfoTrack->bAdjust = TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init()=========> \n")); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking_init(): bATCStatus = %d, CrystalCap = 0x%x \n",pCfoTrack->bATCStatus, pCfoTrack->DefXCap)); +} + +VOID +ODM_CfoTracking( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); + int CFO_kHz_A, CFO_kHz_B, CFO_ave = 0; + int CFO_ave_diff; + int CrystalCap = (int)pCfoTrack->CrystalCap; + u1Byte Adjust_Xtal = 1; + + //4 Support ability + if(!(pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING)) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Return: SupportAbility ODM_BB_CFO_TRACKING is disabled\n")); + return; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking()=========> \n")); + + if(!pDM_Odm->bLinked || !pDM_Odm->bOneEntryOnly) + { + //4 No link or more than one entry + ODM_CfoTrackingReset(pDM_Odm); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Reset: bLinked = %d, bOneEntryOnly = %d\n", + pDM_Odm->bLinked, pDM_Odm->bOneEntryOnly)); + } + else + { + //3 1. CFO Tracking + //4 1.1 No new packet + if(pCfoTrack->packetCount == pCfoTrack->packetCount_pre) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): packet counter doesn't change\n")); + return; + } + pCfoTrack->packetCount_pre = pCfoTrack->packetCount; + + //4 1.2 Calculate CFO + CFO_kHz_A = (int)((pCfoTrack->CFO_tail[0] * 3125) / 10)>>7; /* CFO_tail[1:0] is S(8,7), (num_subcarrier>>7) x 312.5K = CFO value(K Hz) */ + CFO_kHz_B = (int)((pCfoTrack->CFO_tail[1] * 3125) / 10)>>7; + + if(pDM_Odm->RFType < ODM_2T2R) + CFO_ave = CFO_kHz_A; + else + CFO_ave = (int)(CFO_kHz_A + CFO_kHz_B) >> 1; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): CFO_kHz_A = %dkHz, CFO_kHz_B = %dkHz, CFO_ave = %dkHz\n", + CFO_kHz_A, CFO_kHz_B, CFO_ave)); + + //4 1.3 Avoid abnormal large CFO + CFO_ave_diff = (pCfoTrack->CFO_ave_pre >= CFO_ave)?(pCfoTrack->CFO_ave_pre - CFO_ave):(CFO_ave - pCfoTrack->CFO_ave_pre); + if(CFO_ave_diff > 20 && pCfoTrack->largeCFOHit == 0 && !pCfoTrack->bAdjust) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): first large CFO hit\n")); + pCfoTrack->largeCFOHit = 1; + return; + } + else + pCfoTrack->largeCFOHit = 0; + pCfoTrack->CFO_ave_pre = CFO_ave; + + //4 1.4 Dynamic Xtal threshold + if(pCfoTrack->bAdjust == FALSE) + { + if(CFO_ave > CFO_TH_XTAL_HIGH || CFO_ave < (-CFO_TH_XTAL_HIGH)) + pCfoTrack->bAdjust = TRUE; + } + else + { + if(CFO_ave < CFO_TH_XTAL_LOW && CFO_ave > (-CFO_TH_XTAL_LOW)) + pCfoTrack->bAdjust = FALSE; + } + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + //4 1.5 BT case: Disable CFO tracking + if(pDM_Odm->bBtEnabled) + { + pCfoTrack->bAdjust = FALSE; + odm_SetCrystalCap(pDM_Odm, pCfoTrack->DefXCap); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Disable CFO tracking for BT!!\n")); + } +/* + //4 1.6 Big jump + if(pCfoTrack->bAdjust) + { + if(CFO_ave > CFO_TH_XTAL_LOW) + Adjust_Xtal = Adjust_Xtal + ((CFO_ave - CFO_TH_XTAL_LOW) >> 2); + else if(CFO_ave < (-CFO_TH_XTAL_LOW)) + Adjust_Xtal = Adjust_Xtal + ((CFO_TH_XTAL_LOW - CFO_ave) >> 2); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Crystal cap offset = %d\n", Adjust_Xtal)); + } +*/ +#endif + + //4 1.7 Adjust Crystal Cap. + if(pCfoTrack->bAdjust) + { + if(CFO_ave > CFO_TH_XTAL_LOW) + CrystalCap = CrystalCap + Adjust_Xtal; + else if(CFO_ave < (-CFO_TH_XTAL_LOW)) + CrystalCap = CrystalCap - Adjust_Xtal; + + if(CrystalCap > 0x3f) + CrystalCap = 0x3f; + else if (CrystalCap < 0) + CrystalCap = 0; + + odm_SetCrystalCap(pDM_Odm, (u1Byte)CrystalCap); + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Crystal cap = 0x%x, Default Crystal cap = 0x%x\n", + pCfoTrack->CrystalCap, pCfoTrack->DefXCap)); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + return; + + //3 2. Dynamic ATC switch + if(CFO_ave < CFO_TH_ATC && CFO_ave > -CFO_TH_ATC) + { + odm_SetATCStatus(pDM_Odm, FALSE); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Disable ATC!!\n")); + } + else + { + odm_SetATCStatus(pDM_Odm, TRUE); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CFO_TRACKING, ODM_DBG_LOUD, ("ODM_CfoTracking(): Enable ATC!!\n")); + } +#endif + } +} + +VOID +ODM_ParsingCFO( + IN PVOID pDM_VOID, + IN PVOID pPktinfo_VOID, + IN s1Byte* pcfotail + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PODM_PACKET_INFO_T pPktinfo = (PODM_PACKET_INFO_T)pPktinfo_VOID; + PCFO_TRACKING pCfoTrack = (PCFO_TRACKING)PhyDM_Get_Structure( pDM_Odm, PHYDM_CFOTRACK); + u1Byte i; + + if(!(pDM_Odm->SupportAbility & ODM_BB_CFO_TRACKING)) + return; + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if(pPktinfo->bPacketMatchBSSID) +#else + if(pPktinfo->StationID != 0) +#endif + { + //3 Update CFO report for path-A & path-B + // Only paht-A and path-B have CFO tail and short CFO + for(i = ODM_RF_PATH_A; i <= ODM_RF_PATH_B; i++) + { + pCfoTrack->CFO_tail[i] = (int)pcfotail[i]; + } + + //3 Update packet counter + if(pCfoTrack->packetCount == 0xffffffff) + pCfoTrack->packetCount = 0; + else + pCfoTrack->packetCount++; + } +} + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_cfotracking.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_cfotracking.h new file mode 100644 index 000000000..7eca3f6e9 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_cfotracking.h @@ -0,0 +1,68 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMCFOTRACK_H__ +#define __PHYDMCFOTRACK_H__ + +#define CFO_TRACKING_VERSION "1.2" /*2015.06.17*/ + +#define CFO_TH_XTAL_HIGH 20 // kHz +#define CFO_TH_XTAL_LOW 10 // kHz +#define CFO_TH_ATC 80 // kHz + +typedef struct _CFO_TRACKING_ +{ + BOOLEAN bATCStatus; + BOOLEAN largeCFOHit; + BOOLEAN bAdjust; + u1Byte CrystalCap; + u1Byte DefXCap; + int CFO_tail[2]; + int CFO_ave_pre; + u4Byte packetCount; + u4Byte packetCount_pre; + + BOOLEAN bForceXtalCap; + BOOLEAN bReset; +}CFO_TRACKING, *PCFO_TRACKING; + +VOID +ODM_CfoTrackingReset( + IN PVOID pDM_VOID +); + +VOID +ODM_CfoTrackingInit( + IN PVOID pDM_VOID +); + +VOID +ODM_CfoTracking( + IN PVOID pDM_VOID +); + +VOID +ODM_ParsingCFO( + IN PVOID pDM_VOID, + IN PVOID pPktinfo_VOID, + IN s1Byte* pcfotail +); + +#endif \ No newline at end of file diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_debug.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_debug.c new file mode 100644 index 000000000..73efc277f --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_debug.c @@ -0,0 +1,2005 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + + +VOID +PHYDM_InitDebugSetting( + IN PDM_ODM_T pDM_Odm +) +{ + pDM_Odm->DebugLevel = ODM_DBG_TRACE; + + pDM_Odm->DebugComponents = + \ +#if DBG +//BB Functions +// ODM_COMP_DIG | +// ODM_COMP_RA_MASK | +// ODM_COMP_DYNAMIC_TXPWR | +// ODM_COMP_FA_CNT | +// ODM_COMP_RSSI_MONITOR | +// ODM_COMP_CCK_PD | +/* ODM_COMP_ANT_DIV |*/ +// ODM_COMP_PWR_SAVE | +// ODM_COMP_PWR_TRAIN | +// ODM_COMP_RATE_ADAPTIVE | +// ODM_COMP_PATH_DIV | +// ODM_COMP_DYNAMIC_PRICCA | +// ODM_COMP_RXHP | +// ODM_COMP_MP | +// ODM_COMP_CFO_TRACKING | +// ODM_COMP_ACS | +// PHYDM_COMP_ADAPTIVITY | +// PHYDM_COMP_RA_DBG | +/* PHYDM_COMP_TXBF |*/ +//MAC Functions +// ODM_COMP_EDCA_TURBO | +// ODM_COMP_EARLY_MODE | +/* ODM_FW_DEBUG_TRACE |*/ +//RF Functions +// ODM_COMP_TX_PWR_TRACK | +// ODM_COMP_RX_GAIN_TRACK | +// ODM_COMP_CALIBRATION | +//Common +/* ODM_PHY_CONFIG |*/ +// ODM_COMP_COMMON | +// ODM_COMP_INIT | +// ODM_COMP_PSD | +/* ODM_COMP_NOISY_DETECT |*/ +#endif + 0; + + pDM_Odm->fw_buff_is_enpty = TRUE; + pDM_Odm->pre_c2h_seq = 0; +} + +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) +static u1Byte BbDbgBuf[BB_TMP_BUF_SIZE]; + +VOID +phydm_BB_RxHang_Info(IN PDM_ODM_T pDM_Odm) +{ + u4Byte value32 = 0; + + + if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + return; + + value32 = ODM_GetBBReg(pDM_Odm, 0xF80 , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "rptreg of sc/bw/ht/...", value32); + DCMD_Printf(BbDbgBuf); + + /* dbg_port = state machine */ + { + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0x007); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x8fc", value32); + DCMD_Printf(BbDbgBuf); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "state machine", (value32)); + DCMD_Printf(BbDbgBuf); + } + + /* dbg_port = CCA-related*/ + { + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0x204); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x8fc", value32); + DCMD_Printf(BbDbgBuf); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "CCA-related", (value32)); + DCMD_Printf(BbDbgBuf); + } + + + /* dbg_port = edcca/rxd*/ + { + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0x278); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x8fc", value32); + DCMD_Printf(BbDbgBuf); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "edcca/rxd", (value32)); + DCMD_Printf(BbDbgBuf); + } + + /* dbg_port = rx_state/mux_state/ADC_MASK_OFDM*/ + { + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0x290); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x8fc", value32); + DCMD_Printf(BbDbgBuf); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "rx_state/mux_state/ADC_MASK_OFDM", (value32)); + DCMD_Printf(BbDbgBuf); + } + + /* dbg_port = bf-related*/ + { + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0x2B2); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x8fc", value32); + DCMD_Printf(BbDbgBuf); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "bf-related", (value32)); + DCMD_Printf(BbDbgBuf); + } + + /* dbg_port = bf-related*/ + { + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0x2B8); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x8fc", value32); + DCMD_Printf(BbDbgBuf); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "bf-related", (value32)); + DCMD_Printf(BbDbgBuf); + } + + /* dbg_port = txon/rxd*/ + { + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xA03); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x8fc", value32); + DCMD_Printf(BbDbgBuf); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "txon/rxd", (value32)); + DCMD_Printf(BbDbgBuf); + } + + /* dbg_port = l_rate/l_length*/ + { + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xA0B); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x8fc", value32); + DCMD_Printf(BbDbgBuf); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "l_rate/l_length", (value32)); + DCMD_Printf(BbDbgBuf); + } + + /* dbg_port = rxd/rxd_hit*/ + { + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xA0D); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x8fc", value32); + DCMD_Printf(BbDbgBuf); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "rxd/rxd_hit", (value32)); + DCMD_Printf(BbDbgBuf); + } + + /* dbg_port = dis_cca*/ + { + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xAA0); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x8fc", value32); + DCMD_Printf(BbDbgBuf); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "dis_cca", (value32)); + DCMD_Printf(BbDbgBuf); + } + + + /* dbg_port = tx*/ + { + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xAB0); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x8fc", value32); + DCMD_Printf(BbDbgBuf); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "tx", (value32)); + DCMD_Printf(BbDbgBuf); + } + + /* dbg_port = rx plcp*/ + { + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xAD0); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x8fc", value32); + DCMD_Printf(BbDbgBuf); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "rx plcp", (value32)); + DCMD_Printf(BbDbgBuf); + + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xAD1); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x8fc", value32); + DCMD_Printf(BbDbgBuf); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "rx plcp", (value32)); + DCMD_Printf(BbDbgBuf); + + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xAD2); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x8fc", value32); + DCMD_Printf(BbDbgBuf); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "rx plcp", (value32)); + DCMD_Printf(BbDbgBuf); + + ODM_SetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord, 0xAD3); + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_DBG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "0x8fc", value32); + DCMD_Printf(BbDbgBuf); + + value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_RPT_11AC , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = 0x%x", "rx plcp", (value32)); + DCMD_Printf(BbDbgBuf); + } + +} + +VOID +phydm_BB_Debug_Info(IN PDM_ODM_T pDM_Odm) +{ + + u1Byte RX_HT_BW, RX_VHT_BW, RXSC, RX_HT, RX_BW; + static u1Byte vRX_BW ; + u4Byte value32, value32_1, value32_2, value32_3; + s4Byte SFO_A, SFO_B, SFO_C, SFO_D; + s4Byte LFO_A, LFO_B, LFO_C, LFO_D; + static u1Byte MCSS, Tail, Parity, rsv, vrsv, idx, smooth, htsound, agg, stbc, vstbc, fec, fecext, sgi, sgiext, htltf, vgid, vNsts, vtxops, vrsv2, vbrsv, bf, vbcrc; + static u2Byte HLength, htcrc8, Length; + static u2Byte vpaid; + static u2Byte vLength, vhtcrc8, vMCSS, vTail, vbTail; + static u1Byte HMCSS, HRX_BW; + + + u1Byte pwDB; + s1Byte RXEVM_0, RXEVM_1, RXEVM_2 ; + u1Byte RF_gain_pathA, RF_gain_pathB, RF_gain_pathC, RF_gain_pathD; + u1Byte RX_SNR_pathA, RX_SNR_pathB, RX_SNR_pathC, RX_SNR_pathD; + s4Byte sig_power; + const char *RXHT_table[3] = {"legacy", "HT", "VHT"}; + const char *BW_table[3] = {"20M", "40M", "80M"}; + const char *RXSC_table[7] = {"duplicate/full bw", "usc20-1", "lsc20-1", "usc20-2", "lsc20-2", "usc40", "lsc40"}; + + const char *L_rate[8] = {"6M", "9M", "12M", "18M", "24M", "36M", "48M", "54M"}; + + + /* + const double evm_comp_20M = 0.579919469776867; //10*log10(64.0/56.0) + const double evm_comp_40M = 0.503051183113957; //10*log10(128.0/114.0) + const double evm_comp_80M = 0.244245993314183; //10*log10(256.0/242.0) + const double evm_comp_160M = 0.244245993314183; //10*log10(512.0/484.0) + */ + + if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + return; + + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s\n", "BB Report Info"); + DCMD_Printf(BbDbgBuf); + + /*BW & Mode Detection*/ + + value32 = ODM_GetBBReg(pDM_Odm, 0xf80 , bMaskDWord); + value32_2 = value32; + RX_HT_BW = (u1Byte)(value32 & 0x1); + RX_VHT_BW = (u1Byte)((value32 >> 1) & 0x3); + RXSC = (u1Byte)(value32 & 0x78); + value32_1 = (value32 & 0x180) >> 7; + RX_HT = (u1Byte)(value32_1); + /* + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "F80", value32_2); + DCMD_Printf(BbDbgBuf); + + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "RX_HT_BW", RX_HT_BW); + DCMD_Printf(BbDbgBuf); + + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "RX_VHT_BW", RX_VHT_BW); + DCMD_Printf(BbDbgBuf); + + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "RX_SC", RXSC); + DCMD_Printf(BbDbgBuf); + + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "RX_HT", RX_HT); + DCMD_Printf(BbDbgBuf); + */ + + /*rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n RX_HT:%s ", RXHT_table[RX_HT]);*/ + /*DCMD_Printf(BbDbgBuf);*/ + RX_BW = 0; + + if (RX_HT == 2) { + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n Mode: VHT Mode"); + DCMD_Printf(BbDbgBuf); + if (RX_VHT_BW == 0) { + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, " BW=20M"); + DCMD_Printf(BbDbgBuf); + } else if (RX_VHT_BW == 1) { + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, " BW=40M"); + DCMD_Printf(BbDbgBuf); + } else { + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, " BW=80M"); + DCMD_Printf(BbDbgBuf); + } + RX_BW = RX_VHT_BW; + } else if (RX_HT == 1) { + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n Mode: HT Mode"); + DCMD_Printf(BbDbgBuf); + if (RX_HT_BW == 0) { + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, " BW=20M"); + DCMD_Printf(BbDbgBuf); + } else if (RX_HT_BW == 1) { + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, " BW=40M"); + DCMD_Printf(BbDbgBuf); + } + RX_BW = RX_HT_BW; + } else { + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n Mode: Legeacy Mode"); + DCMD_Printf(BbDbgBuf); + } + + if (RX_HT != 0) { + if (RXSC == 0) + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n duplicate/full bw"); + else if (RXSC == 1) + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n usc20-1"); + else if (RXSC == 2) + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n lsc20-1"); + else if (RXSC == 3) + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n usc20-2"); + else if (RXSC == 4) + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n lsc20-2"); + else if (RXSC == 9) + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n usc40"); + else if (RXSC == 10) + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n lsc40"); + DCMD_Printf(BbDbgBuf); + } + /* + if(RX_HT == 2){ + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, " BW:%s", BW_table[RX_VHT_BW]); + RX_BW = RX_VHT_BW; + } + else if(RX_HT == 1){ + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, " BW:%s", BW_table[RX_HT_BW]); + RX_BW = RX_HT_BW; + } + else + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, ""); + + DCMD_Printf(BbDbgBuf); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, " RXSC:%s", RXSC_table[RXSC]); + DCMD_Printf(BbDbgBuf); + */ + + +/* rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "dB Conversion: 10log(65)", ODM_PWdB_Conversion(65,10,0));*/ +/* DCMD_Printf(BbDbgBuf);*/ + + /* RX signal power and AGC related info*/ + + value32 = ODM_GetBBReg(pDM_Odm, 0xF90 , bMaskDWord); + pwDB = (u1Byte)((value32 & bMaskByte1) >> 8); + pwDB = pwDB >> 1; + sig_power = -110 + pwDB; + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "OFDM RX Signal Power(dB)", sig_power); + DCMD_Printf(BbDbgBuf); + + + value32 = ODM_GetBBReg(pDM_Odm, 0xd14 , bMaskDWord); + RX_SNR_pathA = (u1Byte)(value32 & 0xFF) >> 1; + RF_gain_pathA = (s1Byte)((value32 & bMaskByte1) >> 8); + RF_gain_pathA *= 2; + value32 = ODM_GetBBReg(pDM_Odm, 0xd54 , bMaskDWord); + RX_SNR_pathB = (u1Byte)(value32 & 0xFF) >> 1; + RF_gain_pathB = (s1Byte)((value32 & bMaskByte1) >> 8); + RF_gain_pathB *= 2; + value32 = ODM_GetBBReg(pDM_Odm, 0xd94 , bMaskDWord); + RX_SNR_pathC = (u1Byte)(value32 & 0xFF) >> 1; + RF_gain_pathC = (s1Byte)((value32 & bMaskByte1) >> 8); + RF_gain_pathC *= 2; + value32 = ODM_GetBBReg(pDM_Odm, 0xdd4 , bMaskDWord); + RX_SNR_pathD = (u1Byte)(value32 & 0xFF) >> 1; + RF_gain_pathD = (s1Byte)((value32 & bMaskByte1) >> 8); + RF_gain_pathD *= 2; + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "OFDM RX RF Gain(A/B/C/D)", RF_gain_pathA, RF_gain_pathA, RF_gain_pathC, RF_gain_pathD); + DCMD_Printf(BbDbgBuf); + + + /* RX Counter related info*/ + + value32 = ODM_GetBBReg(pDM_Odm, 0xF08, bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "OFDM CCA Counter", ((value32&0xFFFF0000)>>16)); + DCMD_Printf(BbDbgBuf); + + value32 = ODM_GetBBReg(pDM_Odm, 0xFD0, bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "OFDM SBD Fail Counter", value32&0xFFFF); + DCMD_Printf(BbDbgBuf); + + value32 = ODM_GetBBReg(pDM_Odm, 0xFC4, bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d", "VHT SIGA/SIGB CRC8 Fail Counter", value32&0xFFFF, ((value32&0xFFFF0000)>>16)); + DCMD_Printf(BbDbgBuf); + + value32 = ODM_GetBBReg(pDM_Odm, 0xFCC, bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "CCK CCA Counter", value32&0xFFFF); + DCMD_Printf(BbDbgBuf); + + value32 = ODM_GetBBReg(pDM_Odm, 0xFBC, bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d", "LSIG (\"Parity Fail\"/\"Rate Illegal\") Counter", value32&0xFFFF, ((value32&0xFFFF0000)>>16)); + DCMD_Printf(BbDbgBuf); + + value32_1 = ODM_GetBBReg(pDM_Odm, 0xFC8, bMaskDWord); + value32_2 = ODM_GetBBReg(pDM_Odm, 0xFC0, bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d", "HT/VHT MCS NOT SUPPORT counter", ((value32_2&0xFFFF0000)>>16), value32_1&0xFFFF); + DCMD_Printf(BbDbgBuf); + + + /* PostFFT related info*/ + + + value32 = ODM_GetBBReg(pDM_Odm, 0xF8c , bMaskDWord); + RXEVM_0 = (s1Byte)((value32 & bMaskByte2) >> 16); + RXEVM_0 /= 2; + if (RXEVM_0 < -63) + RXEVM_0 = 0; + + DCMD_Printf(BbDbgBuf); + RXEVM_1 = (s1Byte)((value32 & bMaskByte3) >> 24); + RXEVM_1 /= 2; + value32 = ODM_GetBBReg(pDM_Odm, 0xF88 , bMaskDWord); + RXEVM_2 = (s1Byte)((value32 & bMaskByte2) >> 16); + RXEVM_2 /= 2; + + if (RXEVM_1 < -63) + RXEVM_1 = 0; + if (RXEVM_2 < -63) + RXEVM_2 = 0; + + /* + if(RX_BW == 0){ + RXEVM_0 -= evm_comp_20M; + RXEVM_1 -= evm_comp_20M; + RXEVM_2 -= evm_comp_20M; + } + else if(RX_BW == 1){ + RXEVM_0 -= evm_comp_40M; + RXEVM_1 -= evm_comp_40M; + RXEVM_2 -= evm_comp_40M; + } + else if (RX_BW == 2){ + RXEVM_0 -= evm_comp_80M; + RXEVM_1 -= evm_comp_80M; + RXEVM_2 -= evm_comp_80M; + } + */ + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d", "RXEVM (1ss/2ss/3ss)", RXEVM_0, RXEVM_1, RXEVM_2); + DCMD_Printf(BbDbgBuf); + +/* value32 = ODM_GetBBReg(pDM_Odm, 0xD14 ,bMaskDWord);*/ + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d / %d / %d", "RXSNR(A/B/C/D, dB)", RX_SNR_pathA, RX_SNR_pathB, RX_SNR_pathC, RX_SNR_pathD); + DCMD_Printf(BbDbgBuf); +/* rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d", "B_RXSNR", (value32&0xFF00)>>9);*/ +/* DCMD_Printf(BbDbgBuf);*/ + + value32 = ODM_GetBBReg(pDM_Odm, 0xF8C , bMaskDWord); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d", "CSI_1st /CSI_2nd", value32&0xFFFF, ((value32&0xFFFF0000)>>16)); + DCMD_Printf(BbDbgBuf); + + + //BW & Mode Detection + + //Reset Page F Counter + ODM_SetBBReg(pDM_Odm, 0xB58 , BIT0, 1); + ODM_SetBBReg(pDM_Odm, 0xB58 , BIT0, 0); + + //CFO Report Info + //Short CFO + value32 = ODM_GetBBReg(pDM_Odm, 0xd0c , bMaskDWord); + value32_1 = ODM_GetBBReg(pDM_Odm, 0xd4c , bMaskDWord); + value32_2 = ODM_GetBBReg(pDM_Odm, 0xd8c , bMaskDWord); + value32_3 = ODM_GetBBReg(pDM_Odm, 0xdcc , bMaskDWord); + + SFO_A = (s4Byte)(value32 & bMask12Bits); + SFO_B = (s4Byte)(value32_1 & bMask12Bits); + SFO_C = (s4Byte)(value32_2 & bMask12Bits); + SFO_D = (s4Byte)(value32_3 & bMask12Bits); + + LFO_A = (s4Byte)(value32 >> 16); + LFO_B = (s4Byte)(value32_1 >> 16); + LFO_C = (s4Byte)(value32_2 >> 16); + LFO_D = (s4Byte)(value32_3 >> 16); + + //SFO 2's to dec + if (SFO_A > 2047) + SFO_A = SFO_A - 4096; + SFO_A = (SFO_A * 312500) / 2048; + + if (SFO_B > 2047) + SFO_B = SFO_B - 4096; + SFO_B = (SFO_B * 312500) / 2048; + if (SFO_C > 2047) + SFO_C = SFO_C - 4096; + SFO_C = (SFO_C * 312500) / 2048; + if (SFO_D > 2047) + SFO_D = SFO_D - 4096; + SFO_D = (SFO_D * 312500) / 2048; + + //LFO 2's to dec + + if (LFO_A > 4095) + LFO_A = LFO_A - 8192; + + if (LFO_B > 4095) + LFO_B = LFO_B - 8192; + + if (LFO_C > 4095) + LFO_C = LFO_C - 8192; + + if (LFO_D > 4095) + LFO_D = LFO_D - 8192; + LFO_A = LFO_A * 312500 / 4096; + LFO_B = LFO_B * 312500 / 4096; + LFO_C = LFO_C * 312500 / 4096; + LFO_D = LFO_D * 312500 / 4096; + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "CFO Report Info"); + DCMD_Printf(BbDbgBuf); + + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d/ %d/ %d", " Short CFO(Hz) ", SFO_A, SFO_B, SFO_C, SFO_D); + DCMD_Printf(BbDbgBuf); + + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d/ %d/ %d", " Long CFO(Hz) ", LFO_A, LFO_B, LFO_C, LFO_D); + DCMD_Printf(BbDbgBuf); + + //SCFO + value32 = ODM_GetBBReg(pDM_Odm, 0xd10 , bMaskDWord); + value32_1 = ODM_GetBBReg(pDM_Odm, 0xd50 , bMaskDWord); + value32_2 = ODM_GetBBReg(pDM_Odm, 0xd90 , bMaskDWord); + value32_3 = ODM_GetBBReg(pDM_Odm, 0xdd0 , bMaskDWord); + + SFO_A = (s4Byte)(value32 & 0x7ff); + SFO_B = (s4Byte)(value32_1 & 0x7ff); + SFO_C = (s4Byte)(value32_2 & 0x7ff); + SFO_D = (s4Byte)(value32_3 & 0x7ff); + + if (SFO_A > 1023) + SFO_A = SFO_A - 2048; + + if (SFO_B > 2047) + SFO_B = SFO_B - 4096; + + if (SFO_C > 2047) + SFO_C = SFO_C - 4096; + + if (SFO_D > 2047) + SFO_D = SFO_D - 4096; + + SFO_A = SFO_A * 312500 / 1024; + SFO_B = SFO_B * 312500 / 1024; + SFO_C = SFO_C * 312500 / 1024; + SFO_D = SFO_D * 312500 / 1024; + + LFO_A = (s4Byte)(value32 >> 16); + LFO_B = (s4Byte)(value32_1 >> 16); + LFO_C = (s4Byte)(value32_2 >> 16); + LFO_D = (s4Byte)(value32_3 >> 16); + + if (LFO_A > 4095) + LFO_A = LFO_A - 8192; + + if (LFO_B > 4095) + LFO_B = LFO_B - 8192; + + if (LFO_C > 4095) + LFO_C = LFO_C - 8192; + + if (LFO_D > 4095) + LFO_D = LFO_D - 8192; + LFO_A = LFO_A * 312500 / 4096; + LFO_B = LFO_B * 312500 / 4096; + LFO_C = LFO_C * 312500 / 4096; + LFO_D = LFO_D * 312500 / 4096; + + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d/ %d/ %d", " Value SCFO(Hz) ", SFO_A, SFO_B, SFO_C, SFO_D); + DCMD_Printf(BbDbgBuf); + + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d/ %d/ %d", " ACQ CFO(Hz) ", LFO_A, LFO_B, LFO_C, LFO_D); + DCMD_Printf(BbDbgBuf); + + value32 = ODM_GetBBReg(pDM_Odm, 0xd14 , bMaskDWord); + value32_1 = ODM_GetBBReg(pDM_Odm, 0xd54 , bMaskDWord); + value32_2 = ODM_GetBBReg(pDM_Odm, 0xd94 , bMaskDWord); + value32_3 = ODM_GetBBReg(pDM_Odm, 0xdd4 , bMaskDWord); + + LFO_A = (s4Byte)(value32 >> 16); + LFO_B = (s4Byte)(value32_1 >> 16); + LFO_C = (s4Byte)(value32_2 >> 16); + LFO_D = (s4Byte)(value32_3 >> 16); + + if (LFO_A > 4095) + LFO_A = LFO_A - 8192; + + if (LFO_B > 4095) + LFO_B = LFO_B - 8192; + + if (LFO_C > 4095) + LFO_C = LFO_C - 8192; + + if (LFO_D > 4095) + LFO_D = LFO_D - 8192; + + LFO_A = LFO_A * 312500 / 4096; + LFO_B = LFO_B * 312500 / 4096; + LFO_C = LFO_C * 312500 / 4096; + LFO_D = LFO_D * 312500 / 4096; + + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d / %d/ %d/ %d", " End CFO(Hz) ", LFO_A, LFO_B, LFO_C, LFO_D); + DCMD_Printf(BbDbgBuf); + + value32 = ODM_GetBBReg(pDM_Odm, 0xf20 , bMaskDWord); /*L SIG*/ + + Tail = (u1Byte)((value32 & 0xfc0000) >> 16); + Parity = (u1Byte)((value32 & 0x20000) >> 16); + Length = (u2Byte)((value32 & 0x1ffe00) >> 8); + rsv = (u1Byte)(value32 & 0x10); + MCSS = (u1Byte)(value32 & 0x0f); + + switch (MCSS) { + case 0x0b: + idx = 0; + break; + case 0x0f: + idx = 1; + break; + case 0x0a: + idx = 2; + break; + case 0x0e: + idx = 3; + break; + case 0x09: + idx = 4; + break; + case 0x08: + idx = 5; + break; + case 0x0c: + idx = 6; + break; + default: + idx = 6; + break; + + } + + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "L-SIG"); + DCMD_Printf(BbDbgBuf); + + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n Rate:%s", L_rate[idx]); + DCMD_Printf(BbDbgBuf); + + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %x/ %x /%x", " Rsv/Length/Parity", rsv, RX_BW, Length); + DCMD_Printf(BbDbgBuf); + + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "HT-SIG1"); + DCMD_Printf(BbDbgBuf); + + value32 = ODM_GetBBReg(pDM_Odm, 0xf2c , bMaskDWord); /*HT SIG*/ + if (RX_HT == 1) { + + HMCSS = (u1Byte)(value32 & 0x7F); + HRX_BW = (u1Byte)(value32 & 0x80); + HLength = (u2Byte)((value32 >> 8) & 0xffff); + } + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %x / %x/ %x", " MCS/BW/Length", HMCSS, HRX_BW, HLength); + DCMD_Printf(BbDbgBuf); + + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "HT-SIG2"); + DCMD_Printf(BbDbgBuf); + + value32 = ODM_GetBBReg(pDM_Odm, 0xf30 , bMaskDWord); /*HT SIG*/ + + if (RX_HT == 1) { + smooth = (u1Byte)(value32 & 0x01); + htsound = (u1Byte)(value32 & 0x02); + rsv = (u1Byte)(value32 & 0x04); + agg = (u1Byte)(value32 & 0x08); + stbc = (u1Byte)(value32 & 0x30); + fec = (u1Byte)(value32 & 0x40); + sgi = (u1Byte)(value32 & 0x80); + htltf = (u1Byte)((value32 & 0x300) >> 8); + htcrc8 = (u2Byte)((value32 & 0x3fc00) >> 8); + Tail = (u1Byte)((value32 & 0xfc0000) >> 16); + + + } + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %x / %x/ %x/ %x/ %x/ %x", " Smooth/NoSound/Rsv/Aggregate/STBC/LDPC", smooth, htsound, rsv, agg, stbc, fec); + DCMD_Printf(BbDbgBuf); + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %x / %x/ %x/ %x", " SGI/E-HT-LTFs/CRC/Tail", sgi, htltf, htcrc8, Tail); + DCMD_Printf(BbDbgBuf); + + + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "VHT-SIG-A1"); + DCMD_Printf(BbDbgBuf); + value32 = ODM_GetBBReg(pDM_Odm, 0xf2c , bMaskDWord); /*VHT SIG A1*/ + if (RX_HT == 2) { + /* value32 = ODM_GetBBReg(pDM_Odm, 0xf2c ,bMaskDWord);*/ + vRX_BW = (u1Byte)(value32 & 0x03); + vrsv = (u1Byte)(value32 & 0x04); + vstbc = (u1Byte)(value32 & 0x08); + vgid = (u1Byte)((value32 & 0x3f0) >> 4); + vNsts = (u1Byte)(((value32 & 0x1c00) >> 8) + 1); + vpaid = (u2Byte)(value32 & 0x3fe); + vtxops = (u1Byte)((value32 & 0x400000) >> 20); + vrsv2 = (u1Byte)((value32 & 0x800000) >> 20); + } + + /*rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %x", "F2C", value32);*/ + /*DCMD_Printf(BbDbgBuf);*/ + + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %x / %x/ %x/ %x/ %x/ %x /%x /%x", " BW/Rsv1/STBC/GID/Nsts/PAID/TXOPPS/Rsv2", vRX_BW, vrsv, vstbc, vgid, vNsts, vpaid, vtxops, vrsv2); + DCMD_Printf(BbDbgBuf); + + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "VHT-SIG-A2"); + DCMD_Printf(BbDbgBuf); + value32 = ODM_GetBBReg(pDM_Odm, 0xf30 , bMaskDWord); /*VHT SIG*/ + + + if (RX_HT == 2) { + /*value32 = ODM_GetBBReg(pDM_Odm, 0xf30 ,bMaskDWord); */ /*VHT SIG*/ + + //sgi=(u1Byte)(value32&0x01); + sgiext = (u1Byte)(value32 & 0x03); + //fec = (u1Byte)(value32&0x04); + fecext = (u1Byte)(value32 & 0x0C); + + vMCSS = (u1Byte)(value32 & 0xf0); + bf = (u1Byte)((value32 & 0x100) >> 8); + vrsv = (u1Byte)((value32 & 0x200) >> 8); + vhtcrc8 = (u2Byte)((value32 & 0x3fc00) >> 8); + vTail = (u1Byte)((value32 & 0xfc0000) >> 16); + } + /*rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %x", "F30", value32);*/ + /*DCMD_Printf(BbDbgBuf);*/ + + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %x / %x/ %x/ %x/ %x/ %x/ %x", " SGI/FEC/MCS/BF/Rsv/CRC/Tail", sgiext, fecext, vMCSS, bf, vrsv, vhtcrc8, vTail); + DCMD_Printf(BbDbgBuf); + + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "VHT-SIG-B"); + DCMD_Printf(BbDbgBuf); + value32 = ODM_GetBBReg(pDM_Odm, 0xf34 , bMaskDWord); /*VHT SIG*/ + { + vLength = (u2Byte)(value32 & 0x1fffff); + vbrsv = (u1Byte)((value32 & 0x600000) >> 20); + vbTail = (u2Byte)((value32 & 0x1f800000) >> 20); + vbcrc = (u1Byte)((value32 & 0x80000000) >> 28); + + } + /*rsprintf(BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %x", "F34", value32);*/ + /*DCMD_Printf(BbDbgBuf);*/ + rsprintf((char *)BbDbgBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %x / %x/ %x/ %x/", " Length/Rsv/Tail/CRC", vLength, vbrsv, vbTail, vbcrc); + DCMD_Printf(BbDbgBuf); + + +} + +void phydm_sbd_check( + IN PDM_ODM_T pDM_Odm +) +{ + static u4Byte pkt_cnt = 0; + static BOOLEAN sbd_state = 0; + u4Byte sym_count, count, value32; + + if (sbd_state == 0) { + pkt_cnt++; + if (pkt_cnt % 5 == 0) { /*read SBD conter once every 5 packets*/ + ODM_SetTimer(pDM_Odm, &pDM_Odm->sbdcnt_timer, 0); /*ms*/ + sbd_state = 1; + } + } else { /*read counter*/ + value32 = ODM_GetBBReg(pDM_Odm, 0xF98, bMaskDWord); + sym_count = (value32 & 0x7C000000) >> 26; + count = (value32 & 0x3F00000) >> 20; + DbgPrint("#SBD# sym_count %d count %d\n", sym_count, count); + sbd_state = 0; + } +} + +void phydm_sbd_callback( + PRT_TIMER pTimer +) +{ + PADAPTER Adapter = (PADAPTER)pTimer->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + +#if USE_WORKITEM + ODM_ScheduleWorkItem(&pDM_Odm->sbdcnt_workitem); +#else + phydm_sbd_check(pDM_Odm); +#endif +} + +void phydm_sbd_workitem_callback( + IN PVOID pContext +) +{ + PADAPTER pAdapter = (PADAPTER)pContext; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + phydm_sbd_check(pDM_Odm); +} +#endif +VOID +phydm_BasicDbgMessage +( + IN PVOID pDM_VOID +) +{ +#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure(pDM_Odm , PHYDM_FALSEALMCNT); + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + u1Byte legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54}; + u1Byte vht_en = ((pDM_Odm->RxRate) >= ODM_RATEVHTSS1MCS0) ? 1 : 0; + + if (pDM_Odm->RxRate <= ODM_RATE11M) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[CCK AGC Report] LNA_idx = 0x%x, VGA_idx = 0x%x\n", + pDM_Odm->cck_lna_idx, pDM_Odm->cck_vga_idx)); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[OFDM AGC Report] { 0x%x, 0x%x, 0x%x, 0x%x }\n", + pDM_Odm->ofdm_agc_idx[0], pDM_Odm->ofdm_agc_idx[1], pDM_Odm->ofdm_agc_idx[2], pDM_Odm->ofdm_agc_idx[3])); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI: { %d, %d, %d, %d }, RxRate: { %s%s%s%s%d%s}\n", + (pDM_Odm->RSSI_A == 0xff) ? 0 : pDM_Odm->RSSI_A , + (pDM_Odm->RSSI_B == 0xff) ? 0 : pDM_Odm->RSSI_B , + (pDM_Odm->RSSI_C == 0xff) ? 0 : pDM_Odm->RSSI_C, + (pDM_Odm->RSSI_D == 0xff) ? 0 : pDM_Odm->RSSI_D, + ((pDM_Odm->RxRate >= ODM_RATEVHTSS1MCS0) && (pDM_Odm->RxRate <= ODM_RATEVHTSS1MCS9)) ? "VHT 1ss " : "", + ((pDM_Odm->RxRate >= ODM_RATEVHTSS2MCS0) && (pDM_Odm->RxRate <= ODM_RATEVHTSS2MCS9)) ? "VHT 2ss " : "", + ((pDM_Odm->RxRate >= ODM_RATEVHTSS3MCS0) && (pDM_Odm->RxRate <= ODM_RATEVHTSS3MCS9)) ? "VHT 3ss " : "", + (pDM_Odm->RxRate >= ODM_RATEMCS0) ? "MCS " : "", + (vht_en) ? ((pDM_Odm->RxRate - ODM_RATEVHTSS1MCS0)%10) : ((pDM_Odm->RxRate >= ODM_RATEMCS0) ? (pDM_Odm->RxRate - ODM_RATEMCS0) : ((pDM_Odm->RxRate <= ODM_RATE54M)?legacy_table[pDM_Odm->RxRate]:0)), + (pDM_Odm->RxRate >= ODM_RATEMCS0) ? "" : "M")); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + FalseAlmCnt->Cnt_CCK_CCA, FalseAlmCnt->Cnt_OFDM_CCA, FalseAlmCnt->Cnt_CCA_all)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n", + FalseAlmCnt->Cnt_Cck_fail, FalseAlmCnt->Cnt_Ofdm_fail, FalseAlmCnt->Cnt_all)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("[OFDM FA Detail] Parity_Fail = (( %d )), Rate_Illegal = (( %d )), CRC8_fail = (( %d )), Mcs_fail = (( %d )), Fast_Fsync = (( %d )), SB_Search_fail = (( %d ))\n", + FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal, FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail, FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked = %d, RSSI_Min = %d, CurrentIGI = 0x%x, bNoisy=%d\n\n", + pDM_Odm->bLinked, pDM_Odm->RSSI_Min, pDM_DigTable->CurIGValue, pDM_Odm->NoisyDecision)); +/* + temp_reg = ODM_GetBBReg(pDM_Odm, 0xDD0, bMaskByte0); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("0xDD0 = 0x%x\n",temp_reg)); + + temp_reg = ODM_GetBBReg(pDM_Odm, 0xDDc, bMaskByte1); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("0xDDD = 0x%x\n",temp_reg)); + + temp_reg = ODM_GetBBReg(pDM_Odm, 0xc50, bMaskByte0); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("0xC50 = 0x%x\n",temp_reg)); + + temp_reg = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0, 0x3fe0); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("RF 0x0[13:5] = 0x%x\n\n",temp_reg)); +*/ + +#endif +} + + +VOID phydm_BasicProfile( + IN PVOID pDM_VOID, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + char *Cut = NULL; + char *ICType = NULL; + u4Byte used = *_used; + u4Byte out_len = *_out_len; + u4Byte commit_ver = 0; + u4Byte date = 0; + char *commit_by = NULL; + u4Byte release_ver = 0; + + PHYDM_SNPRINTF((output + used, out_len - used, "%-35s\n", "% Basic Profile %")); + + if (pDM_Odm->SupportICType == ODM_RTL8192C) + ICType = "RTL8192C"; + else if (pDM_Odm->SupportICType == ODM_RTL8192D) + ICType = "RTL8192D"; + else if (pDM_Odm->SupportICType == ODM_RTL8723A) + ICType = "RTL8723A"; + else if (pDM_Odm->SupportICType == ODM_RTL8188E) + ICType = "RTL8188E"; + else if (pDM_Odm->SupportICType == ODM_RTL8812) + ICType = "RTL8812A"; + else if (pDM_Odm->SupportICType == ODM_RTL8821) + ICType = "RTL8821A"; + else if (pDM_Odm->SupportICType == ODM_RTL8192E) + ICType = "RTL8192E"; + else if (pDM_Odm->SupportICType == ODM_RTL8723B) + ICType = "RTL8723B"; + else if (pDM_Odm->SupportICType == ODM_RTL8814A) + ICType = "RTL8814A"; + else if (pDM_Odm->SupportICType == ODM_RTL8881A) + ICType = "RTL8881A"; + else if (pDM_Odm->SupportICType == ODM_RTL8821B) + ICType = "RTL8821B"; + else if (pDM_Odm->SupportICType == ODM_RTL8822B) + ICType = "RTL8822B"; +#if (RTL8703B_SUPPORT == 1) + else if (pDM_Odm->SupportICType == ODM_RTL8703B) { + ICType = "RTL8703B"; + date = RELEASE_DATE_8703B; + commit_by = COMMIT_BY_8703B; + release_ver = RELEASE_VERSION_8703B; + } +#endif + else if (pDM_Odm->SupportICType == ODM_RTL8195A) + ICType = "RTL8195A"; + else if (pDM_Odm->SupportICType == ODM_RTL8188F) + ICType = "RTL8188F"; + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s (MP Chip: %s)\n", "IC Type", ICType, pDM_Odm->bIsMPChip ? "Yes" : "No")); + + if (pDM_Odm->CutVersion == ODM_CUT_A) + Cut = "A"; + else if (pDM_Odm->CutVersion == ODM_CUT_B) + Cut = "B"; + else if (pDM_Odm->CutVersion == ODM_CUT_C) + Cut = "C"; + else if (pDM_Odm->CutVersion == ODM_CUT_D) + Cut = "D"; + else if (pDM_Odm->CutVersion == ODM_CUT_E) + Cut = "E"; + else if (pDM_Odm->CutVersion == ODM_CUT_F) + Cut = "F"; + else if (pDM_Odm->CutVersion == ODM_CUT_I) + Cut = "I"; + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Cut Version", Cut)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d\n", "PHY Parameter Version", ODM_GetHWImgVersion(pDM_Odm))); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d\n", "PHY Parameter Commit date", date)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "PHY Parameter Commit by", commit_by)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d\n", "PHY Parameter Release Version", release_ver)); + +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + { + PADAPTER Adapter = pDM_Odm->Adapter; + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d (Subversion: %d)\n", "FW Version", Adapter->MgntInfo.FirmwareVersion, Adapter->MgntInfo.FirmwareSubVersion)); + } +#elif (DM_ODM_SUPPORT_TYPE & ODM_AP) + { + struct rtl8192cd_priv *priv = pDM_Odm->priv; + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d (Subversion: %d)\n", "FW Version", priv->pshare->fw_version, priv->pshare->fw_sub_version)); + } +#else + { + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %d (Subversion: %d)\n", "FW Version", pHalData->FirmwareVersion, pHalData->FirmwareSubVersion)); + } +#endif + //1 PHY DM Version List + PHYDM_SNPRINTF((output + used, out_len - used, "%-35s\n", "% PHYDM Version %")); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Adaptivity", ADAPTIVITY_VERSION)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "DIG", DIG_VERSION)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Dynamic BB PowerSaving", DYNAMIC_BBPWRSAV_VERSION)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "CFO Tracking", CFO_TRACKING_VERSION)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Antenna Diversity", ANTDIV_VERSION)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Power Tracking", POWRTRACKING_VERSION)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Dynamic TxPower", DYNAMIC_TXPWR_VERSION)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "RA Info", RAINFO_VERSION)); +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Antenna Detection", ANTDECT_VERSION)); +#endif + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Auto Channel Selection", ACS_VERSION)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "EDCA Turbo", EDCATURBO_VERSION)); + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "Path Diversity", PATHDIV_VERSION)); +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "RxHP", RXHP_VERSION)); +#endif +#if (RTL8822B_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8822B) + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s: %s\n", "PHY config 8822B", PHY_CONFIG_VERSION_8822B)); + +#endif + *_used = used; + *_out_len = out_len; + +} + +VOID +phydm_fw_trace_en_h2c( + IN PVOID pDM_VOID, + IN BOOLEAN enable, + IN u4Byte monitor_mode, + IN u4Byte macid +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + u1Byte H2C_Parameter[3] = {0}; + + H2C_Parameter[0] = enable; + H2C_Parameter[1] = (u1Byte)monitor_mode; + H2C_Parameter[2] = (u1Byte)macid; + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("---->\n")); + if (monitor_mode == 0){ + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[H2C] FW_debug_en: (( %d ))\n", enable)); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[H2C] FW_debug_en: (( %d )), mode: (( %d )), macid: (( %d ))\n", enable, monitor_mode, macid)); + } + ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_FW_TRACE_EN, 3, H2C_Parameter); +} + +VOID +phydm_get_per_path_txagc( + IN PVOID pDM_VOID, + IN u1Byte path, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte rate_idx; + u1Byte txagc; + u4Byte used = *_used; + u4Byte out_len = *_out_len; + +#if (RTL8822B_SUPPORT == 1) + if ((pDM_Odm->SupportICType & ODM_RTL8822B) && (path <= ODM_RF_PATH_B)) { + for (rate_idx = 0; rate_idx <= 0x53; rate_idx++) { + if (rate_idx == ODM_RATE1M) + PHYDM_SNPRINTF((output + used, out_len - used, " %-35s\n", "CCK====>")); + else if (rate_idx == ODM_RATE6M) + PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "OFDM====>")); + else if (rate_idx == ODM_RATEMCS0) + PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "HT 1ss====>")); + else if (rate_idx == ODM_RATEMCS8) + PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "HT 2ss====>")); + else if (rate_idx == ODM_RATEMCS16) + PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "HT 3ss====>")); + else if (rate_idx == ODM_RATEMCS24) + PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "HT 4ss====>")); + else if (rate_idx == ODM_RATEVHTSS1MCS0) + PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "VHT 1ss====>")); + else if (rate_idx == ODM_RATEVHTSS2MCS0) + PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "VHT 2ss====>")); + else if (rate_idx == ODM_RATEVHTSS3MCS0) + PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "VHT 3ss====>")); + else if (rate_idx == ODM_RATEVHTSS4MCS0) + PHYDM_SNPRINTF((output + used, out_len - used, "\n %-35s\n", "VHT 4ss====>")); + + txagc = config_phydm_read_txagc_8822b(pDM_Odm, path, rate_idx); + if (config_phydm_read_txagc_check_8822b(txagc)) + PHYDM_SNPRINTF((output + used, out_len - used, " 0x%02x ", txagc)); + else + PHYDM_SNPRINTF((output + used, out_len - used, " 0x%s ", "xx")); + } + } +#endif +} + + +VOID +phydm_get_txagc( + IN PVOID pDM_VOID, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte used = *_used; + u4Byte out_len = *_out_len; + + /* Path-A */ + PHYDM_SNPRINTF((output + used, out_len - used, "%-35s\n", "Path-A====================")); + phydm_get_per_path_txagc(pDM_Odm, ODM_RF_PATH_A, _used, output, _out_len); + + /* Path-B */ + PHYDM_SNPRINTF((output + used, out_len - used, "\n%-35s\n", "Path-B====================")); + phydm_get_per_path_txagc(pDM_Odm, ODM_RF_PATH_B, _used, output, _out_len); + + /* Path-C */ + PHYDM_SNPRINTF((output + used, out_len - used, "\n%-35s\n", "Path-C====================")); + phydm_get_per_path_txagc(pDM_Odm, ODM_RF_PATH_C, _used, output, _out_len); + + /* Path-D */ + PHYDM_SNPRINTF((output + used, out_len - used, "\n%-35s\n", "Path-D====================")); + phydm_get_per_path_txagc(pDM_Odm, ODM_RF_PATH_D, _used, output, _out_len); + +} + +VOID +phydm_set_txagc( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte used = *_used; + u4Byte out_len = *_out_len; + +#if (RTL8822B_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8822B) { + if (dm_value[0] <= 1) { + if (phydm_write_txagc_1byte_8822b(pDM_Odm, dm_value[2], dm_value[0], (u1Byte)dm_value[1])) + PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s%x%s%x\n", "Write path-", dm_value[0], "rate index-0x", dm_value[1], " = 0x", dm_value[2])); + else + PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s%x%s\n", "Write path-", (dm_value[0] & 0x1), "rate index-0x", (dm_value[1] & 0x7f), " fail")); + } else { + PHYDM_SNPRINTF((output + used, out_len - used, " %s%d %s%x%s\n", "Write path-", (dm_value[0] & 0x1), "rate index-0x", (dm_value[1] & 0x7f), " fail")); + } + } +#endif +} + +VOID +odm_debug_trace( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u8Byte pre_debug_components, one = 1; + u4Byte used = *_used; + u4Byte out_len = *_out_len; + + pre_debug_components = pDM_Odm->DebugComponents; + + PHYDM_SNPRINTF((output + used, out_len - used, "\n%s\n", "================================")); + if (dm_value[0] == 100) { + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[Debug Message] PhyDM Selection")); + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); + PHYDM_SNPRINTF((output + used, out_len - used, "00. (( %s ))DIG\n", ((pDM_Odm->DebugComponents & ODM_COMP_DIG) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "01. (( %s ))RA_MASK\n", ((pDM_Odm->DebugComponents & ODM_COMP_RA_MASK) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "02. (( %s ))DYNAMIC_TXPWR\n", ((pDM_Odm->DebugComponents & ODM_COMP_DYNAMIC_TXPWR) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "03. (( %s ))FA_CNT\n", ((pDM_Odm->DebugComponents & ODM_COMP_FA_CNT) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "04. (( %s ))RSSI_MONITOR\n", ((pDM_Odm->DebugComponents & ODM_COMP_RSSI_MONITOR) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "05. (( %s ))CCK_PD\n", ((pDM_Odm->DebugComponents & ODM_COMP_CCK_PD) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "06. (( %s ))ANT_DIV\n", ((pDM_Odm->DebugComponents & ODM_COMP_ANT_DIV) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "07. (( %s ))PWR_SAVE\n", ((pDM_Odm->DebugComponents & ODM_COMP_PWR_SAVE) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "08. (( %s ))PWR_TRAIN\n", ((pDM_Odm->DebugComponents & ODM_COMP_PWR_TRAIN) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "09. (( %s ))RATE_ADAPTIVE\n", ((pDM_Odm->DebugComponents & ODM_COMP_RATE_ADAPTIVE) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "10. (( %s ))PATH_DIV\n", ((pDM_Odm->DebugComponents & ODM_COMP_PATH_DIV) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "11. (( %s ))PSD\n", ((pDM_Odm->DebugComponents & ODM_COMP_PSD) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "12. (( %s ))DYNAMIC_PRICCA\n", ((pDM_Odm->DebugComponents & ODM_COMP_DYNAMIC_PRICCA) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "13. (( %s ))RXHP\n", ((pDM_Odm->DebugComponents & ODM_COMP_RXHP) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "14. (( %s ))MP\n", ((pDM_Odm->DebugComponents & ODM_COMP_MP) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "15. (( %s ))CFO_TRACKING\n", ((pDM_Odm->DebugComponents & ODM_COMP_CFO_TRACKING) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "16. (( %s ))ACS\n", ((pDM_Odm->DebugComponents & ODM_COMP_ACS) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "17. (( %s ))ADAPTIVITY\n", ((pDM_Odm->DebugComponents & PHYDM_COMP_ADAPTIVITY) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "18. (( %s ))RA_DBG\n", ((pDM_Odm->DebugComponents & PHYDM_COMP_RA_DBG) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "20. (( %s ))EDCA_TURBO\n", ((pDM_Odm->DebugComponents & ODM_COMP_EDCA_TURBO) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "21. (( %s ))EARLY_MODE\n", ((pDM_Odm->DebugComponents & ODM_COMP_EARLY_MODE) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "22. (( %s ))FW_DEBUG_TRACE\n", ((pDM_Odm->DebugComponents & ODM_FW_DEBUG_TRACE) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "24. (( %s ))TX_PWR_TRACK\n", ((pDM_Odm->DebugComponents & ODM_COMP_TX_PWR_TRACK) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "25. (( %s ))RX_GAIN_TRACK\n", ((pDM_Odm->DebugComponents & ODM_COMP_RX_GAIN_TRACK) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "26. (( %s ))CALIBRATION\n", ((pDM_Odm->DebugComponents & ODM_COMP_CALIBRATION) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "28. (( %s ))PHY_CONFIG\n", ((pDM_Odm->DebugComponents & ODM_PHY_CONFIG) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "29. (( %s ))BEAMFORMING_DEBUG\n", ((pDM_Odm->DebugComponents & BEAMFORMING_DEBUG) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "30. (( %s ))COMMON\n", ((pDM_Odm->DebugComponents & ODM_COMP_COMMON) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "31. (( %s ))INIT\n", ((pDM_Odm->DebugComponents & ODM_COMP_INIT) ? ("V") : (".")))); + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); + + } else if (dm_value[0] == 101) { + pDM_Odm->DebugComponents = 0; + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "Disable all debug components")); + } else { + if (dm_value[1] == 1) { /*enable*/ + pDM_Odm->DebugComponents |= (one << dm_value[0]); + + if (dm_value[0] == 22) { /*FW trace function*/ + phydm_fw_trace_en_h2c(pDM_Odm, 1, dm_value[2], dm_value[3]); /*H2C to enable C2H Msg*/ + } + } else if (dm_value[1] == 2) { /*disable*/ + pDM_Odm->DebugComponents &= ~(one << dm_value[0]); + + if (dm_value[0] == 22) { /*FW trace function*/ + phydm_fw_trace_en_h2c(pDM_Odm, 0, dm_value[2], dm_value[3]); /*H2C to disable C2H Msg*/ + } + } else + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "[Warning!!!] 1:enable, 2:disable")); + } + PHYDM_SNPRINTF((output + used, out_len - used, "pre-DbgComponents = 0x%x\n", (u4Byte)pre_debug_components)); + PHYDM_SNPRINTF((output + used, out_len - used, "Curr-DbgComponents = 0x%x\n", ((u4Byte)pDM_Odm->DebugComponents))); + PHYDM_SNPRINTF((output + used, out_len - used, "%s\n", "================================")); +} + +VOID +phydm_DumpBbReg( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte Addr = 0; + + /* BB Reg */ + for (Addr = 0x800; Addr < 0xfff; Addr += 4) + DbgPrint("%04x %08x\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord)); + + if (pDM_Odm->SupportICType & (ODM_RTL8822B|ODM_RTL8814A)) { + + if (pDM_Odm->RFType > ODM_2T2R) { + for (Addr = 0x1800; Addr < 0x18ff; Addr += 4) + DbgPrint("%04x %08x\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord)); + } + + if (pDM_Odm->RFType > ODM_3T3R) { + for (Addr = 0x1a00; Addr < 0x1aff; Addr += 4) + DbgPrint("%04x %08x\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord)); + } + + for (Addr = 0x1900; Addr < 0x19ff; Addr += 4) + DbgPrint("%04x %08x\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord)); + + for (Addr = 0x1c00; Addr < 0x1cff; Addr += 4) + DbgPrint("%04x %08x\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord)); + + for (Addr = 0x1f00; Addr < 0x1fff; Addr += 4) + DbgPrint("%04x %08x\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord)); + } +} + +VOID +phydm_DumpAllReg( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte Addr = 0; + + /* dump MAC register */ + DbgPrint("MAC==========\n"); + for (Addr = 0; Addr < 0x7ff; Addr += 4) + DbgPrint("%04x %08x\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord)); + + for (Addr = 1000; Addr < 0x17ff; Addr += 4) + DbgPrint("%04x %08x\n", Addr, ODM_GetBBReg(pDM_Odm, Addr, bMaskDWord)); + + /* dump BB register */ + DbgPrint("BB==========\n"); + phydm_DumpBbReg(pDM_Odm); + + /* dump RF register */ + DbgPrint("RF-A==========\n"); + for (Addr = 0; Addr < 0xFF; Addr++) + DbgPrint("%02x %05x\n", Addr, ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, Addr, bRFRegOffsetMask)); + + if (pDM_Odm->RFType > ODM_1T1R) { + DbgPrint("RF-B==========\n"); + for (Addr = 0; Addr < 0xFF; Addr++) + DbgPrint("%02x %05x\n", Addr, ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, Addr, bRFRegOffsetMask)); + } + + if (pDM_Odm->RFType > ODM_2T2R) { + DbgPrint("RF-C==========\n"); + for (Addr = 0; Addr < 0xFF; Addr++) + DbgPrint("%02x %05x\n", Addr, ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_C, Addr, bRFRegOffsetMask)); + } + + if (pDM_Odm->RFType > ODM_3T3R) { + DbgPrint("RF-D==========\n"); + for (Addr = 0; Addr < 0xFF; Addr++) + DbgPrint("%02x %05x\n", Addr, ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_D, Addr, bRFRegOffsetMask)); + } +} + +struct _PHYDM_COMMAND { + char name[16]; + u1Byte id; +}; + +enum PHYDM_CMD_ID { + PHYDM_DEMO, + PHYDM_RA, + PHYDM_PROFILE, + PHYDM_PATHDIV, + PHYDM_DEBUG, + PHYDM_SUPPORT_ABILITY, + PHYDM_GET_TXAGC, + PHYDM_SET_TXAGC, + PHYDM_SMART_ANT, + PHYDM_API, + PHYDM_TRX_PATH, + PHYDM_LA_MODE, + PHYDM_DUMP_REG +}; + +struct _PHYDM_COMMAND phy_dm_ary[] = { + {"demo", PHYDM_DEMO}, + {"ra", PHYDM_RA}, + {"profile", PHYDM_PROFILE}, + {"pathdiv", PHYDM_PATHDIV}, + {"dbg", PHYDM_DEBUG}, + {"ability", PHYDM_SUPPORT_ABILITY}, + {"get_txagc", PHYDM_GET_TXAGC}, + {"set_txagc", PHYDM_SET_TXAGC}, + {"smtant", PHYDM_SMART_ANT}, + {"api", PHYDM_API}, + {"trxpath", PHYDM_TRX_PATH}, + {"lamode", PHYDM_LA_MODE}, + {"dumpreg", PHYDM_DUMP_REG} +}; + +VOID +phydm_cmd_parser( + IN PDM_ODM_T pDM_Odm, + IN char input[][MAX_ARGV], + IN u4Byte input_num, + IN u1Byte flag, + OUT char *output, + IN u4Byte out_len +) +{ + u4Byte used = 0; + u1Byte id = 0; + int var1[5] = {0}; + int i, input_idx = 0; + + if (flag == 0) { + PHYDM_SNPRINTF((output + used, out_len - used, "GET, nothing to print\n")); + return; + } + + PHYDM_SNPRINTF((output + used, out_len - used, "\n")); + + //Parsing Cmd ID + if (input_num) { + int n, i; + + n = sizeof(phy_dm_ary) / sizeof(struct _PHYDM_COMMAND); + for (i = 0; i < n; i++) { + if (strcmp(phy_dm_ary[i].name, input[0]) == 0) { + id = phy_dm_ary[i].id; + break; + } + } + if (i == n) { + PHYDM_SNPRINTF((output + used, out_len - used, "SET, command not found!\n")); + return; + } + } + + switch (id) { + case PHYDM_DEMO: /*echo demo 10 0x3a z abcde >cmd*/ + { + u4Byte directory = 0; +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) + char char_temp; +#else + u4Byte char_temp = ' '; +#endif + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &directory); + PHYDM_SNPRINTF((output + used, out_len - used, "Decimal Value = %d\n", directory)); + PHYDM_SSCANF(input[2], DCMD_HEX, &directory); + PHYDM_SNPRINTF((output + used, out_len - used, "Hex Value = 0x%x\n", directory)); + PHYDM_SSCANF(input[3], DCMD_CHAR, &char_temp); + PHYDM_SNPRINTF((output + used, out_len - used, "Char = %c\n", char_temp)); + PHYDM_SNPRINTF((output + used, out_len - used, "String = %s\n", input[4])); + } + break; + + case PHYDM_RA: + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + + PHYDM_SNPRINTF((output + used, out_len - used, "new SET, RA_var[%d]= (( %d ))\n", i , var1[i])); + input_idx++; + } + } + + if (input_idx >= 1) { + /*PHYDM_SNPRINTF((output+used, out_len-used, "odm_RA_debug\n"));*/ +#if (defined(CONFIG_RA_DBG_CMD)) + odm_RA_debug((PVOID)pDM_Odm, var1); +#endif + } + + + break; + + case PHYDM_PATHDIV: + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); + + /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, PATHDIV_var[%d]= (( %d ))\n", i , var1[i]));*/ + input_idx++; + } + } + + if (input_idx >= 1) { + /*PHYDM_SNPRINTF((output+used, out_len-used, "odm_PATHDIV_debug\n"));*/ +#if (defined(CONFIG_PATH_DIVERSITY)) + odm_pathdiv_debug(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); +#endif + } + + break; + + case PHYDM_DEBUG: + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + + /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, Debug_var[%d]= (( %d ))\n", i , var1[i]));*/ + input_idx++; + } + } + + if (input_idx >= 1) { + /*PHYDM_SNPRINTF((output+used, out_len-used, "odm_debug_comp\n"));*/ + odm_debug_trace(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); + } + + + break; + + case PHYDM_SUPPORT_ABILITY: + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + + /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, support ablity_var[%d]= (( %d ))\n", i , var1[i]));*/ + input_idx++; + } + } + + if (input_idx >= 1) { + /*PHYDM_SNPRINTF((output+used, out_len-used, "support ablity\n"));*/ + phydm_support_ablity_debug(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); + } + + break; + + case PHYDM_SMART_ANT: + + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_HEX, &var1[i]); + input_idx++; + } + } + + if (input_idx >= 1) { + #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1 + phydm_hl_smart_ant_cmd(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); + #endif + #endif + } + + break; + + case PHYDM_API: +#if (RTL8822B_SUPPORT == 1) + { + if (pDM_Odm->SupportICType & ODM_RTL8822B) { + BOOLEAN bEnableDbgMode; + u1Byte central_ch, primary_ch_idx, bandwidth; + + for (i = 0; i < 4; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + } + + bEnableDbgMode = (BOOLEAN)var1[0]; + central_ch = (u1Byte) var1[1]; + primary_ch_idx = (u1Byte) var1[2]; + bandwidth = (ODM_BW_E) var1[3]; + + if (bEnableDbgMode) { + pDM_Odm->bDisablePhyApi = FALSE; + config_phydm_switch_channel_bw_8822b(pDM_Odm, central_ch, primary_ch_idx, bandwidth); + pDM_Odm->bDisablePhyApi = TRUE; + PHYDM_SNPRINTF((output+used, out_len-used, "central_ch = %d, primary_ch_idx = %d, bandwidth = %d\n", central_ch, primary_ch_idx, bandwidth)); + } else { + pDM_Odm->bDisablePhyApi = FALSE; + PHYDM_SNPRINTF((output+used, out_len-used, "Disable API debug mode\n")); + } + } else + PHYDM_SNPRINTF((output+used, out_len-used, "This IC doesn't support PHYDM API function\n")); + } +#else + PHYDM_SNPRINTF((output+used, out_len-used, "This IC doesn't support PHYDM API function\n")); +#endif + break; + + case PHYDM_PROFILE: /*echo profile, >cmd*/ + phydm_BasicProfile(pDM_Odm, &used, output, &out_len); + break; + + case PHYDM_GET_TXAGC: + phydm_get_txagc(pDM_Odm, &used, output, &out_len); + break; + + case PHYDM_SET_TXAGC: + for (i = 0; i < 5; i++) { + if (input[i + 1]) { + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + + /*PHYDM_SNPRINTF((output+used, out_len-used, "new SET, support ablity_var[%d]= (( %d ))\n", i , var1[i]));*/ + input_idx++; + } + } + + phydm_set_txagc(pDM_Odm, (u4Byte *)var1, &used, output, &out_len); + break; + + case PHYDM_TRX_PATH: +#if (RTL8822B_SUPPORT == 1) + { + if (pDM_Odm->SupportICType & ODM_RTL8822B) { + u1Byte TxPath, RxPath; + BOOLEAN bEnableDbgMode, bTx2Path; + + for (i = 0; i < 4; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + } + + bEnableDbgMode = (BOOLEAN)var1[0]; + TxPath = (u1Byte) var1[1]; + RxPath = (u1Byte) var1[2]; + bTx2Path = (BOOLEAN) var1[3]; + + if (bEnableDbgMode) { + pDM_Odm->bDisablePhyApi = FALSE; + config_phydm_trx_mode_8822b(pDM_Odm, TxPath, RxPath, bTx2Path); + pDM_Odm->bDisablePhyApi = TRUE; + PHYDM_SNPRINTF((output+used, out_len-used, "TxPath = 0x%x, RxPath = 0x%x, bTx2Path = %d\n", TxPath, RxPath, bTx2Path)); + } else { + pDM_Odm->bDisablePhyApi = FALSE; + PHYDM_SNPRINTF((output+used, out_len-used, "Disable API debug mode\n")); + } + } else + PHYDM_SNPRINTF((output+used, out_len-used, "This IC doesn't support PHYDM API function\n")); + } +#else + PHYDM_SNPRINTF((output+used, out_len-used, "This IC doesn't support PHYDM API function\n")); +#endif + break; + + case PHYDM_LA_MODE: +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if ((RTL8822B_SUPPORT == 1) || (RTL8814A_SUPPORT == 1)) + { + if (pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_RTL8822B)) { + u2Byte PollingTime; + u1Byte TrigSel, TrigSigSel, DmaDataSigSel, TriggerTime; + BOOLEAN bEnableLaMode; + + for (i = 0; i < 6; i++) { + if (input[i + 1]) + PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]); + } + + bEnableLaMode = (BOOLEAN)var1[0]; + if (bEnableLaMode) { + TrigSel = (u1Byte)var1[1]; + TrigSigSel = (u1Byte)var1[2]; + DmaDataSigSel = (u1Byte)var1[3]; + TriggerTime = (u1Byte)var1[4]; + PollingTime = (((u1Byte)var1[5]) << 6); + + ADCSmp_Set(pDM_Odm->Adapter, TrigSel, TrigSigSel, DmaDataSigSel, TriggerTime, PollingTime); + PHYDM_SNPRINTF((output+used, out_len-used, "TrigSel = %d, TrigSigSel = %d, DmaDataSigSel = %d\n", TrigSel, TrigSigSel, DmaDataSigSel)); + PHYDM_SNPRINTF((output+used, out_len-used, "TriggerTime = %d, PollingTime = %d\n", TriggerTime, PollingTime)); + } else { + ADCSmp_Stop(pDM_Odm->Adapter); + PHYDM_SNPRINTF((output+used, out_len-used, "Disable LA mode\n")); + } + } else + PHYDM_SNPRINTF((output+used, out_len-used, "This IC doesn't support LA mode\n")); + } +#else + PHYDM_SNPRINTF((output+used, out_len-used, "This IC doesn't support LA mode\n")); +#endif +#else + PHYDM_SNPRINTF((output+used, out_len-used, "This IC doesn't support LA mode\n")); +#endif + break; + + case PHYDM_DUMP_REG: + { + u1Byte type = 0; + + if (input[1]) { + PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]); + type = (u1Byte)var1[0]; + } + + if (type == 0) + phydm_DumpBbReg(pDM_Odm); + else if (type == 1) + phydm_DumpAllReg(pDM_Odm); + } + break; + default: + PHYDM_SNPRINTF((output + used, out_len - used, "SET, unknown command!\n")); + break; + + } +} + +#ifdef __ECOS +char *strsep(char **s, const char *ct) +{ + char *sbegin = *s; + char *end; + + if (sbegin == NULL) + return NULL; + + end = strpbrk(sbegin, ct); + if (end) + *end++ = '\0'; + *s = end; + return sbegin; +} +#endif + +#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) +s4Byte +phydm_cmd( + IN PDM_ODM_T pDM_Odm, + IN char *input, + IN u4Byte in_len, + IN u1Byte flag, + OUT char *output, + IN u4Byte out_len +) +{ + char *token; + u4Byte Argc = 0; + char Argv[MAX_ARGC][MAX_ARGV]; + + do { + token = strsep(&input, ", "); + if (token) { + strcpy(Argv[Argc], token); + Argc++; + } else + break; + } while (Argc < MAX_ARGC); + + if (Argc == 1) + Argv[0][strlen(Argv[0]) - 1] = '\0'; + + phydm_cmd_parser(pDM_Odm, Argv, Argc, flag, output, out_len); + + return 0; +} +#endif + + +VOID +phydm_fw_trace_handler( + IN PVOID pDM_VOID, + IN pu1Byte CmdBuf, + IN u1Byte CmdLen +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + /*u1Byte debug_trace_11byte[60];*/ + u1Byte freg_num, c2h_seq, buf_0 = 0; + + if (CmdLen > 12) + return; + + buf_0 = CmdBuf[0]; + freg_num = (buf_0 & 0xf); + c2h_seq = (buf_0 & 0xf0) >> 4; + /*ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] freg_num = (( %d )), c2h_seq = (( %d ))\n", freg_num,c2h_seq ));*/ + + /*strncpy(debug_trace_11byte,&CmdBuf[1],(CmdLen-1));*/ + /*debug_trace_11byte[CmdLen-1] = '\0';*/ + /*ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] %s\n", debug_trace_11byte));*/ + /*ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] CmdLen = (( %d ))\n", CmdLen));*/ + /*ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW debug message] c2h_cmd_start = (( %d ))\n", pDM_Odm->c2h_cmd_start));*/ + + + + /*ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("pre_seq = (( %d )), current_seq = (( %d ))\n", pDM_Odm->pre_c2h_seq, c2h_seq));*/ + /*ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("fw_buff_is_enpty = (( %d ))\n", pDM_Odm->fw_buff_is_enpty));*/ + + if ((c2h_seq != pDM_Odm->pre_c2h_seq) && pDM_Odm->fw_buff_is_enpty == FALSE) { + pDM_Odm->fw_debug_trace[pDM_Odm->c2h_cmd_start] = '\0'; + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW Dbg Queue Overflow] %s\n", pDM_Odm->fw_debug_trace)); + pDM_Odm->c2h_cmd_start = 0; + } + + if ((CmdLen - 1) > (60 - pDM_Odm->c2h_cmd_start)) { + pDM_Odm->fw_debug_trace[pDM_Odm->c2h_cmd_start] = '\0'; + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW Dbg Queue error: wrong C2H length] %s\n", pDM_Odm->fw_debug_trace)); + pDM_Odm->c2h_cmd_start = 0; + return; + } + + strncpy((char *)&(pDM_Odm->fw_debug_trace[pDM_Odm->c2h_cmd_start]), (char *)&CmdBuf[1], (CmdLen-1)); + pDM_Odm->c2h_cmd_start += (CmdLen - 1); + pDM_Odm->fw_buff_is_enpty = FALSE; + + if (freg_num == 0 || pDM_Odm->c2h_cmd_start >= 60) { + if (pDM_Odm->c2h_cmd_start < 60) + pDM_Odm->fw_debug_trace[pDM_Odm->c2h_cmd_start] = '\0'; + else + pDM_Odm->fw_debug_trace[59] = '\0'; + + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s\n", pDM_Odm->fw_debug_trace)); + /*DbgPrint("[FW DBG Msg] %s\n", pDM_Odm->fw_debug_trace);*/ + pDM_Odm->c2h_cmd_start = 0; + pDM_Odm->fw_buff_is_enpty = TRUE; + } + + pDM_Odm->pre_c2h_seq = c2h_seq; +} + +VOID +phydm_fw_trace_handler_code( + IN PVOID pDM_VOID, + IN pu1Byte Buffer, + IN u1Byte CmdLen +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte function = Buffer[0]; + u1Byte dbg_num = Buffer[1]; + u2Byte content_0 = (((u2Byte)Buffer[3])<<8)|((u2Byte)Buffer[2]); + u2Byte content_1 = (((u2Byte)Buffer[5])<<8)|((u2Byte)Buffer[4]); + u2Byte content_2 = (((u2Byte)Buffer[7])<<8)|((u2Byte)Buffer[6]); + u2Byte content_3 = (((u2Byte)Buffer[9])<<8)|((u2Byte)Buffer[8]); + u2Byte content_4 = (((u2Byte)Buffer[11])<<8)|((u2Byte)Buffer[10]); + + if(CmdLen >12) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW Msg] Invalid cmd length (( %d )) >12 \n", CmdLen)); + } + + //ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW Msg] Func=((%d)), num=((%d)), ct_0=((%d)), ct_1=((%d)), ct_2=((%d)), ct_3=((%d)), ct_4=((%d))\n", + // function, dbg_num, content_0, content_1, content_2, content_3, content_4)); + + /*--------------------------------------------*/ + if(function == RATE_DECISION) { + if(dbg_num == 0) { + if(content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW][RateDecisoin] RA_CNT=((%d)) Max_device=((%d))--------------------------->\n", content_1, content_2)); + } else if(content_0 == 2) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW][RateDecisoin] Check RA macid= ((%d)), MediaStatus=((%d)), Dis_RA=((%d)), try_bit=((0x%x))\n", content_1, content_2, content_3, content_4)); + } else if(content_0 == 3) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateDecisoin] Check RA total=((%d)), drop=((0x%x)), TXRPT_TRY_bit=((%x)), bNoisy=((%x))\n", content_1, content_2, content_3, content_4)); + } + } else if(dbg_num == 1) { + if(content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW][RateDecisoin] RTY[0,1,2,3]=[ %d, %d, %d, %d ] \n", content_1, content_2, content_3, content_4)); + } else if(content_0 == 2) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW][RateDecisoin] RTY[4]=[ %d ], drop=((%d)), total=((%d)), current_rate=((0x%x))\n", content_1, content_2, content_3, content_4)); + } else if(content_0 == 3) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW][RateDecisoin] penality_idx=((%d ))\n", content_1)); + } + } + + else if(dbg_num == 3) { + if (content_0 == 1) + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateDecisoin] Fast_RA (( DOWN )) total=((%d)), total>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\n", content_1, content_2, content_3, content_4)); + else if (content_0 == 2) + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateDecisoin] Fast_RA (( UP )) total_acc=((%d)), total_acc>>1=((%d)), R4+R3+R2 = ((%d)), RateDownHold = ((%d))\n", content_1, content_2, content_3, content_4)); + else if (content_0 == 3) + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateDecisoin] Fast_RA (( UP )) ((Rate Down Hold)) RA_CNT=((%d))\n", content_1)); + else if (content_0 == 4) + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateDecisoin] Fast_RA (( UP )) ((tota_accl<5 skip)) RA_CNT=((%d))\n", content_1)); + else if (content_0 == 8) + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateDecisoin] Fast_RA (( Reset Tx Rpt )) RA_CNT=((%d))\n", content_1)); + } + + else if(dbg_num == 5) { + if(content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW][RateDecisoin] (( UP)) Nsc=((%d)), N_High=((%d))\n", content_1, content_2)); + } else if(content_0 == 2) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW][RateDecisoin] ((DOWN)) Nsc=((%d)), N_Low=((%d))\n", content_1, content_2)); + } else if(content_0 == 3) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW][RateDecisoin] ((HOLD)) Nsc=((%d)), N_High=((%d)), N_Low=((%d)), Reset_CNT=((%d))\n", content_1, content_2, content_3, content_4)); + } + } + else if(dbg_num == 0x60) { + if(content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW][RateDecisoin] ((AP RPT)) macid=((%d)), BUPDATE[macid]=((%d))\n", content_1, content_2)); + } else if(content_0 == 4) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW][RateDecisoin] ((AP RPT)) pass=((%d)), rty_num=((%d)), drop=((%d)), total=((%d))\n", content_1, content_2, content_3, content_4)); + } else if(content_0 == 5) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("[FW][RateDecisoin] ((AP RPT)) PASS=((%d)), RTY_NUM=((%d)), DROP=((%d)), TOTAL=((%d))\n", content_1, content_2, content_3, content_4)); + } + } + else if(dbg_num == 0xff) { + if(content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE,ODM_DBG_LOUD,("\n\n")); + } + } + + } + /*--------------------------------------------*/ + else if (function == INIT_RA_TABLE){ + if(dbg_num == 3) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][INIT_RA_INFO] Ra_init, RA_SKIP_CNT = (( %d ))\n", content_0)); + } + + } + /*--------------------------------------------*/ + else if (function == RATE_UP) { + if(dbg_num == 2) { + if(content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateUp] ((Highest rate -> return)), macid=((%d)) Nsc=((%d))\n", content_1, content_2)); + } + } else if(dbg_num == 5) { + if (content_0 == 0) + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateUp] ((Rate UP)), up_rate_tmp=((0x%x)), rate_idx=((0x%x)), SGI_en=((%d)), SGI=((%d))\n", content_1, content_2, content_3, content_4)); + else if (content_0 == 1) + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateUp] ((Rate UP)), rate_1=((0x%x)), rate_2=((0x%x)), BW=((%d)), Try_Bit=((%d))\n", content_1, content_2, content_3, content_4)); + } + + } + /*--------------------------------------------*/ + else if (function == RATE_DOWN) { + if(dbg_num == 5) { + if(content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][RateDownStep] ((Rate Down)), macid=((%d)), rate=((0x%x)), BW=((%d))\n", content_1, content_2, content_3)); + } + } + } else if (function == TRY_DONE) { + if (dbg_num == 1) { + if (content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][Try Done] ((try succsess )) macid=((%d)), Try_Done_cnt=((%d))\n", content_1, content_2)); + /**/ + } + } else if (dbg_num == 2) { + if (content_0 == 1) + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][Try Done] ((try fail )) macid=((%d)), Try_Done_cnt=((%d)), multi_try_rate=((%d))\n", content_1, content_2, content_3)); + } + } + /*--------------------------------------------*/ + else if (function == F_RATE_AP_RPT) { + if(dbg_num == 1) { + if(content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] ((1)), SPE_STATIS=((0x%x))---------->\n", content_3)); + } + } else if(dbg_num == 2) { + if(content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] RTY_all=((%d))\n", content_1)); + } + } else if(dbg_num == 3) { + if(content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID1[%d], TOTAL=((%d)), RTY=((%d))\n", content_3, content_1, content_2)); + } + } else if(dbg_num == 4) { + if(content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID2[%d], TOTAL=((%d)), RTY=((%d))\n", content_3, content_1, content_2)); + } + } else if(dbg_num == 5) { + if(content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID1[%d], PASS=((%d)), DROP=((%d))\n", content_3, content_1, content_2)); + } + } else if(dbg_num == 6) { + if(content_0 == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW][AP RPT] MACID2[%d],, PASS=((%d)), DROP=((%d))\n", content_3, content_1, content_2)); + } + } + } + /*--------------------------------------------*/ + + +} + +VOID +phydm_fw_trace_handler_8051( + IN PVOID pDM_VOID, + IN pu1Byte Buffer, + IN u1Byte CmdLen +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if 0 + if (CmdLen >= 3) + CmdBuf[CmdLen - 1] = '\0'; + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s\n", &(CmdBuf[3]))); +#else + + int i = 0; + u1Byte Extend_c2hSubID = 0, Extend_c2hDbgLen = 0, Extend_c2hDbgSeq = 0; + u1Byte fw_debug_trace[128]; + pu1Byte Extend_c2hDbgContent = 0; + + if (CmdLen > 127) + return; + + Extend_c2hSubID = Buffer[0]; + Extend_c2hDbgLen = Buffer[1]; + Extend_c2hDbgContent = Buffer + 2; /*DbgSeq+DbgContent for show HEX*/ + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + RT_DISP(FC2H, C2H_Summary, ("[Extend C2H packet], Extend_c2hSubId=0x%x, Extend_c2hDbgLen=%d\n", + Extend_c2hSubID, Extend_c2hDbgLen)); + + RT_DISP_DATA(FC2H, C2H_Summary, "[Extend C2H packet], Content Hex:", Extend_c2hDbgContent, CmdLen-2); + #endif + +GoBackforAggreDbgPkt: + i = 0; + Extend_c2hDbgSeq = Buffer[2]; + Extend_c2hDbgContent = Buffer + 3; + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + RT_DISP(FC2H, C2H_Summary, ("[RTKFW, SEQ= %d] :", Extend_c2hDbgSeq)); + #endif + + for (; ; i++) { + fw_debug_trace[i] = Extend_c2hDbgContent[i]; + if (Extend_c2hDbgContent[i + 1] == '\0') { + fw_debug_trace[i + 1] = '\0'; + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s", &(fw_debug_trace[0]))); + break; + } else if (Extend_c2hDbgContent[i] == '\n') { + fw_debug_trace[i + 1] = '\0'; + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("[FW DBG Msg] %s", &(fw_debug_trace[0]))); + Buffer = Extend_c2hDbgContent + i + 3; + goto GoBackforAggreDbgPkt; + } + } + + +#endif +} + + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_debug.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_debug.h new file mode 100644 index 000000000..60e84e424 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_debug.h @@ -0,0 +1,330 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __ODM_DBG_H__ +#define __ODM_DBG_H__ + +#define DEBUG_VERSION "1.0" /*2015.01.13 Dino*/ +//----------------------------------------------------------------------------- +// Define the debug levels +// +// 1. DBG_TRACE and DBG_LOUD are used for normal cases. +// So that, they can help SW engineer to develope or trace states changed +// and also help HW enginner to trace every operation to and from HW, +// e.g IO, Tx, Rx. +// +// 2. DBG_WARNNING and DBG_SERIOUS are used for unusual or error cases, +// which help us to debug SW or HW. +// +//----------------------------------------------------------------------------- +// +// Never used in a call to ODM_RT_TRACE()! +// +#define ODM_DBG_OFF 1 + +// +// Fatal bug. +// For example, Tx/Rx/IO locked up, OS hangs, memory access violation, +// resource allocation failed, unexpected HW behavior, HW BUG and so on. +// +#define ODM_DBG_SERIOUS 2 + +// +// Abnormal, rare, or unexpeted cases. +// For example, IRP/Packet/OID canceled, device suprisely unremoved and so on. +// +#define ODM_DBG_WARNING 3 + +// +// Normal case with useful information about current SW or HW state. +// For example, Tx/Rx descriptor to fill, Tx/Rx descriptor completed status, +// SW protocol state change, dynamic mechanism state change and so on. +// +#define ODM_DBG_LOUD 4 + +// +// Normal case with detail execution flow or information. +// +#define ODM_DBG_TRACE 5 + +/*FW DBG MSG*/ +#define RATE_DECISION BIT0 +#define INIT_RA_TABLE BIT1 +#define RATE_UP BIT2 +#define RATE_DOWN BIT3 +#define TRY_DONE BIT4 +#define F_RATE_AP_RPT BIT7 + +//----------------------------------------------------------------------------- +// Define the tracing components +// +//----------------------------------------------------------------------------- +//BB Functions +#define ODM_COMP_DIG BIT0 +#define ODM_COMP_RA_MASK BIT1 +#define ODM_COMP_DYNAMIC_TXPWR BIT2 +#define ODM_COMP_FA_CNT BIT3 +#define ODM_COMP_RSSI_MONITOR BIT4 +#define ODM_COMP_CCK_PD BIT5 +#define ODM_COMP_ANT_DIV BIT6 +#define ODM_COMP_PWR_SAVE BIT7 +#define ODM_COMP_PWR_TRAIN BIT8 +#define ODM_COMP_RATE_ADAPTIVE BIT9 +#define ODM_COMP_PATH_DIV BIT10 +#define ODM_COMP_PSD BIT11 +#define ODM_COMP_DYNAMIC_PRICCA BIT12 +#define ODM_COMP_RXHP BIT13 +#define ODM_COMP_MP BIT14 +#define ODM_COMP_CFO_TRACKING BIT15 +#define ODM_COMP_ACS BIT16 +#define PHYDM_COMP_ADAPTIVITY BIT17 +#define PHYDM_COMP_RA_DBG BIT18 +#define PHYDM_COMP_TXBF BIT19 +//MAC Functions +#define ODM_COMP_EDCA_TURBO BIT20 +#define ODM_COMP_EARLY_MODE BIT21 +#define ODM_FW_DEBUG_TRACE BIT22 +//RF Functions +#define ODM_COMP_TX_PWR_TRACK BIT24 +#define ODM_COMP_RX_GAIN_TRACK BIT25 +#define ODM_COMP_CALIBRATION BIT26 +//Common Functions +#define ODM_PHY_CONFIG BIT28 +#define BEAMFORMING_DEBUG BIT29 +#define ODM_COMP_COMMON BIT30 +#define ODM_COMP_INIT BIT31 +#define ODM_COMP_NOISY_DETECT BIT32 + +/*------------------------Export Marco Definition---------------------------*/ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #define RT_PRINTK DbgPrint +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #define DbgPrint printk + #define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args); + #define RT_DISP(dbgtype, dbgflag, printstr) +#else + #define DbgPrint panic_printk + #define RT_PRINTK(fmt, args...) DbgPrint( "%s(): " fmt, __FUNCTION__, ## args); +#endif + +#ifndef ASSERT + #define ASSERT(expr) +#endif + +#if DBG +#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) \ + do { \ + if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel || level == ODM_DBG_SERIOUS)) \ + { \ + if(pDM_Odm->SupportICType == ODM_RTL8192C) \ + DbgPrint("[ODM-92C] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8192D) \ + DbgPrint("[ODM-92D] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8723A) \ + DbgPrint("[ODM-8723A] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8188E) \ + DbgPrint("[ODM-8188E] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8192E) \ + DbgPrint("[ODM-8192E] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8812) \ + DbgPrint("[ODM-8812] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8821) \ + DbgPrint("[ODM-8821] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8814A) \ + DbgPrint("[ODM-8814] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8703B) \ + DbgPrint("[ODM-8703B] "); \ + else if(pDM_Odm->SupportICType == ODM_RTL8822B) \ + DbgPrint("[ODM-8822] "); \ + else if (pDM_Odm->SupportICType == ODM_RTL8188F) \ + DbgPrint("[ODM-8188F] "); \ + RT_PRINTK fmt; \ + } \ + } while (0) + +#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) \ + if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \ + { \ + RT_PRINTK fmt; \ + } + +#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) \ + if(!(expr)) { \ + DbgPrint( "Assertion failed! %s at ......\n", #expr); \ + DbgPrint( " ......%s,%s,line=%d\n",__FILE__,__FUNCTION__,__LINE__); \ + RT_PRINTK fmt; \ + ASSERT(FALSE); \ + } +#define ODM_dbg_enter() { DbgPrint("==> %s\n", __FUNCTION__); } +#define ODM_dbg_exit() { DbgPrint("<== %s\n", __FUNCTION__); } +#define ODM_dbg_trace(str) { DbgPrint("%s:%s\n", __FUNCTION__, str); } + +#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) \ + if(((comp) & pDM_Odm->DebugComponents) && (level <= pDM_Odm->DebugLevel)) \ + { \ + int __i; \ + pu1Byte __ptr = (pu1Byte)ptr; \ + DbgPrint("[ODM] "); \ + DbgPrint(title_str); \ + DbgPrint(" "); \ + for( __i=0; __i<6; __i++ ) \ + DbgPrint("%02X%s", __ptr[__i], (__i==5)?"":"-"); \ + DbgPrint("\n"); \ + } +#else +#define ODM_RT_TRACE(pDM_Odm, comp, level, fmt) +#define ODM_RT_TRACE_F(pDM_Odm, comp, level, fmt) +#define ODM_RT_ASSERT(pDM_Odm, expr, fmt) +#define ODM_dbg_enter() +#define ODM_dbg_exit() +#define ODM_dbg_trace(str) +#define ODM_PRINT_ADDR(pDM_Odm, comp, level, title_str, ptr) +#endif + + +VOID +PHYDM_InitDebugSetting(IN PDM_ODM_T pDM_Odm); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID phydm_BB_RxHang_Info(IN PDM_ODM_T pDM_Odm); +#endif + +#define BB_TMP_BUF_SIZE 100 +VOID phydm_BB_Debug_Info(IN PDM_ODM_T pDM_Odm); +VOID phydm_BasicDbgMessage( IN PVOID pDM_VOID); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#define PHYDM_DBGPRINT 0 +#define PHYDM_SSCANF(x, y, z) DCMD_Scanf(x, y, z) +#if (PHYDM_DBGPRINT == 1) +#define PHYDM_SNPRINTF(msg) \ + do {\ + rsprintf msg;\ + DbgPrint(output);\ + } while (0) +#else +#define PHYDM_SNPRINTF(msg) \ + do {\ + rsprintf msg;\ + DCMD_Printf(output);\ + } while (0) +#endif +#else +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +#define PHYDM_DBGPRINT 0 +#else +#define PHYDM_DBGPRINT 1 +#endif +#define MAX_ARGC 20 +#define MAX_ARGV 16 +#define DCMD_DECIMAL "%d" +#define DCMD_CHAR "%c" +#define DCMD_HEX "%x" + +#define PHYDM_SSCANF(x, y, z) sscanf(x, y, z) +#if (PHYDM_DBGPRINT == 1) +#define PHYDM_SNPRINTF(msg)\ + do {\ + snprintf msg;\ + DbgPrint(output);\ + } while (0) +#else +#define PHYDM_SNPRINTF(msg)\ + do {\ + if(out_len > used)\ + used+=snprintf msg;\ + } while (0) +#endif +#endif + + +VOID phydm_BasicProfile( + IN PVOID pDM_VOID, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len + ); +#if(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) +s4Byte +phydm_cmd( + IN PDM_ODM_T pDM_Odm, + IN char *input, + IN u4Byte in_len, + IN u1Byte flag, + OUT char *output, + IN u4Byte out_len +); +#endif +VOID +phydm_cmd_parser( + IN PDM_ODM_T pDM_Odm, + IN char input[][16], + IN u4Byte input_num, + IN u1Byte flag, + OUT char *output, + IN u4Byte out_len +); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +void phydm_sbd_check( + IN PDM_ODM_T pDM_Odm + ); + +void phydm_sbd_callback( + PRT_TIMER pTimer + ); + +void phydm_sbd_workitem_callback( + IN PVOID pContext + ); +#endif + +VOID +phydm_fw_trace_en_h2c( + IN PVOID pDM_VOID, + IN BOOLEAN enable, + IN u4Byte monitor_mode, + IN u4Byte macid +); + +VOID +phydm_fw_trace_handler( + IN PVOID pDM_VOID, + IN pu1Byte CmdBuf, + IN u1Byte CmdLen +); + +VOID +phydm_fw_trace_handler_code( + IN PVOID pDM_VOID, + IN pu1Byte Buffer, + IN u1Byte CmdLen +); + +VOID +phydm_fw_trace_handler_8051( + IN PVOID pDM_VOID, + IN pu1Byte CmdBuf, + IN u1Byte CmdLen +); + +#endif // __ODM_DBG_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_dig.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_dig.c new file mode 100644 index 000000000..fbca415fa --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_dig.c @@ -0,0 +1,2086 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ +#include "mp_precomp.h" +#include "phydm_precomp.h" + + +VOID +ODM_ChangeDynamicInitGainThresh( + IN PVOID pDM_VOID, + IN u4Byte DM_Type, + IN u4Byte DM_Value + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + + if (DM_Type == DIG_TYPE_THRESH_HIGH) + { + pDM_DigTable->RssiHighThresh = DM_Value; + } + else if (DM_Type == DIG_TYPE_THRESH_LOW) + { + pDM_DigTable->RssiLowThresh = DM_Value; + } + else if (DM_Type == DIG_TYPE_ENABLE) + { + pDM_DigTable->Dig_Enable_Flag = TRUE; + } + else if (DM_Type == DIG_TYPE_DISABLE) + { + pDM_DigTable->Dig_Enable_Flag = FALSE; + } + else if (DM_Type == DIG_TYPE_BACKOFF) + { + if(DM_Value > 30) + DM_Value = 30; + pDM_DigTable->BackoffVal = (u1Byte)DM_Value; + } + else if(DM_Type == DIG_TYPE_RX_GAIN_MIN) + { + if(DM_Value == 0) + DM_Value = 0x1; + pDM_DigTable->rx_gain_range_min = (u1Byte)DM_Value; + } + else if(DM_Type == DIG_TYPE_RX_GAIN_MAX) + { + if(DM_Value > 0x50) + DM_Value = 0x50; + pDM_DigTable->rx_gain_range_max = (u1Byte)DM_Value; + } +} // DM_ChangeDynamicInitGainThresh // + +int +getIGIForDiff(int value_IGI) +{ + #define ONERCCA_LOW_TH 0x30 + #define ONERCCA_LOW_DIFF 8 + + if (value_IGI < ONERCCA_LOW_TH) { + if ((ONERCCA_LOW_TH - value_IGI) < ONERCCA_LOW_DIFF) + return ONERCCA_LOW_TH; + else + return value_IGI + ONERCCA_LOW_DIFF; + } else { + return value_IGI; + } +} + +VOID +odm_FAThresholdCheck( + IN PVOID pDM_VOID, + IN BOOLEAN bDFSBand, + IN BOOLEAN bPerformance, + IN u4Byte RxTp, + IN u4Byte TxTp, + OUT u4Byte* dm_FA_thres + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if(pDM_Odm->bLinked && (bPerformance||bDFSBand)) + { + if(pDM_Odm->SupportICType == ODM_RTL8192D) + { + // 8192D special case + dm_FA_thres[0] = DM_DIG_FA_TH0_92D; + dm_FA_thres[1] = DM_DIG_FA_TH1_92D; + dm_FA_thres[2] = DM_DIG_FA_TH2_92D; + } +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + else if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) + { + // For AP + if((RxTp>>2) > TxTp && RxTp < 10000 && RxTp > 500) // 10Mbps & 0.5Mbps + { + dm_FA_thres[0] = 0x080; + dm_FA_thres[1] = 0x100; + dm_FA_thres[2] = 0x200; + } + else + { + dm_FA_thres[0] = 0x100; + dm_FA_thres[1] = 0x200; + dm_FA_thres[2] = 0x300; + } + } +#else + else if(pDM_Odm->SupportICType == ODM_RTL8723A && pDM_Odm->bBtLimitedDig) + { + // 8723A BT special case + dm_FA_thres[0] = DM_DIG_FA_TH0; + dm_FA_thres[1] = 0x250; + dm_FA_thres[2] = 0x300; + } +#endif + else + { + // For NIC + dm_FA_thres[0] = DM_DIG_FA_TH0; + dm_FA_thres[1] = DM_DIG_FA_TH1; + dm_FA_thres[2] = DM_DIG_FA_TH2; + } + } + else + { +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + if(bDFSBand) + { + // For DFS band and no link + dm_FA_thres[0] = 250; + dm_FA_thres[1] = 1000; + dm_FA_thres[2] = 2000; + } + else +#endif + { + dm_FA_thres[0] = 2000; + dm_FA_thres[1] = 4000; + dm_FA_thres[2] = 5000; + } + } + return; +} + +u1Byte +odm_ForbiddenIGICheck( + IN PVOID pDM_VOID, + IN u1Byte DIG_Dynamic_MIN, + IN u1Byte CurrentIGI + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + PFALSE_ALARM_STATISTICS pFalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); + u1Byte rx_gain_range_min = pDM_DigTable->rx_gain_range_min; + + if(pFalseAlmCnt->Cnt_all > 10000) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnormally false alarm case. \n")); + + if(pDM_DigTable->LargeFAHit != 3) + pDM_DigTable->LargeFAHit++; + + if(pDM_DigTable->ForbiddenIGI < CurrentIGI)//if(pDM_DigTable->ForbiddenIGI < pDM_DigTable->CurIGValue) + { + pDM_DigTable->ForbiddenIGI = CurrentIGI;//pDM_DigTable->ForbiddenIGI = pDM_DigTable->CurIGValue; + pDM_DigTable->LargeFAHit = 1; + } + + if(pDM_DigTable->LargeFAHit >= 3) + { + if((pDM_DigTable->ForbiddenIGI + 2) > pDM_DigTable->rx_gain_range_max) + rx_gain_range_min = pDM_DigTable->rx_gain_range_max; + else + rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 2); + pDM_DigTable->Recover_cnt = 1800; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnormally false alarm case: Recover_cnt = %d \n", pDM_DigTable->Recover_cnt)); + } + } + else + { + if(pDM_DigTable->Recover_cnt != 0) + { + pDM_DigTable->Recover_cnt --; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Recover_cnt = %d \n", pDM_DigTable->Recover_cnt)); + } + else + { + if(pDM_DigTable->LargeFAHit < 3) + { + if((pDM_DigTable->ForbiddenIGI - 2) < DIG_Dynamic_MIN) //DM_DIG_MIN) + { + pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; //DM_DIG_MIN; + rx_gain_range_min = DIG_Dynamic_MIN; //DM_DIG_MIN; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n")); + } + else + { + pDM_DigTable->ForbiddenIGI -= 2; + rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 2); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n")); + } + } + else + { + pDM_DigTable->LargeFAHit = 0; + } + } + } + + return rx_gain_range_min; + +} + +VOID +odm_InbandNoiseCalculate ( + IN PVOID pDM_VOID + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + u1Byte IGIBackup, TimeCnt = 0, ValidCnt = 0; + BOOLEAN bTimeout = TRUE; + s1Byte sNoise_A, sNoise_B; + s4Byte NoiseRpt_A = 0,NoiseRpt_B = 0; + u4Byte tmp = 0; + static u1Byte failCnt = 0; + + if(!(pDM_Odm->SupportICType & (ODM_RTL8192E))) + return; + + if(pDM_Odm->RFType == ODM_1T1R || *(pDM_Odm->pOnePathCCA) != ODM_CCA_2R) + return; + + if(!pDM_DigTable->bNoiseEst) + return; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_InbandNoiseEstimate()========>\n")); + + //1 Set initial gain. + IGIBackup = pDM_DigTable->CurIGValue; + pDM_DigTable->IGIOffset_A = 0; + pDM_DigTable->IGIOffset_B = 0; + ODM_Write_DIG(pDM_Odm, 0x24); + + //1 Update idle time power report + if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N, BIT25, 0x0); + + delay_ms(2); + + //1 Get noise power level + while(1) + { + //2 Read Noise Floor Report + if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + tmp = ODM_GetBBReg(pDM_Odm, 0x8f8, bMaskLWord); + + sNoise_A = (s1Byte)(tmp & 0xff); + sNoise_B = (s1Byte)((tmp & 0xff00)>>8); + + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("sNoise_A = %d, sNoise_B = %d\n",sNoise_A, sNoise_B)); + + if((sNoise_A < 20 && sNoise_A >= -70) && (sNoise_B < 20 && sNoise_B >= -70)) + { + ValidCnt++; + NoiseRpt_A += sNoise_A; + NoiseRpt_B += sNoise_B; + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("sNoise_A = %d, sNoise_B = %d\n",sNoise_A, sNoise_B)); + } + + TimeCnt++; + bTimeout = (TimeCnt >= 150)?TRUE:FALSE; + + if(ValidCnt == 20 || bTimeout) + break; + + delay_ms(2); + + } + + //1 Keep idle time power report + if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + ODM_SetBBReg(pDM_Odm, ODM_REG_TX_ANT_CTRL_11N, BIT25, 0x1); + + //1 Recover IGI + ODM_Write_DIG(pDM_Odm, IGIBackup); + + //1 Calculate Noise Floor + if(ValidCnt != 0) + { + NoiseRpt_A /= (ValidCnt<<1); + NoiseRpt_B /= (ValidCnt<<1); + } + + if(bTimeout) + { + NoiseRpt_A = 0; + NoiseRpt_B = 0; + + failCnt ++; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("Noise estimate fail time = %d\n", failCnt)); + + if(failCnt == 3) + { + failCnt = 0; + pDM_DigTable->bNoiseEst = FALSE; + } + } + else + { + NoiseRpt_A = -110 + 0x24 + NoiseRpt_A -6; + NoiseRpt_B = -110 + 0x24 + NoiseRpt_B -6; + pDM_DigTable->bNoiseEst = FALSE; + failCnt = 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("NoiseRpt_A = %d, NoiseRpt_B = %d\n", NoiseRpt_A, NoiseRpt_B)); + } + + //1 Calculate IGI Offset + if(NoiseRpt_A > NoiseRpt_B) + { + pDM_DigTable->IGIOffset_A = NoiseRpt_A - NoiseRpt_B; + pDM_DigTable->IGIOffset_B = 0; + } + else + { + pDM_DigTable->IGIOffset_A = 0; + pDM_DigTable->IGIOffset_B = NoiseRpt_B - NoiseRpt_A; + } + +#endif + return; +} + +VOID +odm_DigForBtHsMode( + IN PVOID pDM_VOID + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable=&pDM_Odm->DM_DigTable; + u1Byte digForBtHs=0; + u1Byte digUpBound=0x5a; + + if(pDM_Odm->bBtConnectProcess) + { + if(pDM_Odm->SupportICType&(ODM_RTL8723A)) + digForBtHs = 0x28; + else + digForBtHs = 0x22; + } + else + { + // + // Decide DIG value by BT HS RSSI. + // + digForBtHs = pDM_Odm->btHsRssi+4; + + //DIG Bound + if(pDM_Odm->SupportICType&(ODM_RTL8723A)) + digUpBound = 0x3e; + + if(digForBtHs > digUpBound) + digForBtHs = digUpBound; + if(digForBtHs < 0x1c) + digForBtHs = 0x1c; + + // update Current IGI + pDM_DigTable->BT30_CurIGI = digForBtHs; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DigForBtHsMode() : set DigValue=0x%x\n", digForBtHs)); +#endif +} + +VOID +ODM_Write_DIG( + IN PVOID pDM_VOID, + IN u1Byte CurrentIGI + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + + if (pDM_DigTable->bStopDIG) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_Write_DIG(): Stop Writing IGI\n")); + return; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("ODM_Write_DIG(): ODM_REG(IGI_A,pDM_Odm)=0x%x, ODM_BIT(IGI,pDM_Odm)=0x%x\n", + ODM_REG(IGI_A,pDM_Odm),ODM_BIT(IGI,pDM_Odm))); + + //1 Check initial gain by upper bound + if ((!pDM_DigTable->bPSDInProgress) && pDM_Odm->bLinked) + { + if (CurrentIGI > pDM_DigTable->rx_gain_range_max) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("ODM_Write_DIG(): CurrentIGI(0x%02x) is larger than upper bound !!\n", CurrentIGI)); + CurrentIGI = pDM_DigTable->rx_gain_range_max; + } + if (pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY && pDM_Odm->adaptivity_flag == TRUE) + { + if(CurrentIGI > pDM_Odm->Adaptivity_IGI_upper) + CurrentIGI = pDM_Odm->Adaptivity_IGI_upper; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_Write_DIG(): Adaptivity case: Force upper bound to 0x%x !!!!!!\n", CurrentIGI)); + } + } + + if(pDM_DigTable->CurIGValue != CurrentIGI) + { + + /*Add by YuChen for USB IO too slow issue*/ + if ((pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY) && (CurrentIGI > pDM_DigTable->CurIGValue)) + Phydm_Adaptivity(pDM_Odm, CurrentIGI); + + //1 Set IGI value + if(pDM_Odm->SupportPlatform & (ODM_WIN|ODM_CE)) + { + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + + if(pDM_Odm->RFType > ODM_1T1R) + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + + if((pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) && (pDM_Odm->RFType > ODM_2T2R)) + { + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_C,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_D,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + } + } + else if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) + { + switch(*(pDM_Odm->pOnePathCCA)) + { + case ODM_CCA_2R: + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + + if(pDM_Odm->RFType > ODM_1T1R) + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + + if((pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) && (pDM_Odm->RFType > ODM_2T2R)) + { + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_C,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_D,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + } + break; + case ODM_CCA_1R_A: + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + if(pDM_Odm->RFType != ODM_1T1R) + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI)); + break; + case ODM_CCA_1R_B: + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI)); + if(pDM_Odm->RFType != ODM_1T1R) + ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI); + break; + } + } + pDM_DigTable->CurIGValue = CurrentIGI; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_TRACE, ("ODM_Write_DIG(): CurrentIGI(0x%02x).\n", CurrentIGI)); + +} + +VOID +odm_PauseDIG( + IN PVOID pDM_VOID, + IN PHYDM_PAUSE_TYPE PauseType, + IN PHYDM_PAUSE_LEVEL pause_level, + IN u1Byte IGIValue +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG()=========> level = %d\n", pause_level)); + + if ((pDM_DigTable->pause_dig_level == 0) && (!(pDM_Odm->SupportAbility & ODM_BB_DIG) || !(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, + ("odm_PauseDIG(): Return: SupportAbility DIG or FA is disabled !!\n")); + return; + } + + if (pause_level > DM_DIG_MAX_PAUSE_TYPE) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, + ("odm_PauseDIG(): Return: Wrong pause level !!\n")); + return; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): pause level = 0x%x, Current value = 0x%x\n", pDM_DigTable->pause_dig_level, IGIValue)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", + pDM_DigTable->pause_dig_value[7], pDM_DigTable->pause_dig_value[6], pDM_DigTable->pause_dig_value[5], pDM_DigTable->pause_dig_value[4], + pDM_DigTable->pause_dig_value[3], pDM_DigTable->pause_dig_value[2], pDM_DigTable->pause_dig_value[1], pDM_DigTable->pause_dig_value[0])); + + switch (PauseType) { + /* Pause DIG */ + case PHYDM_PAUSE: + { + /* Disable DIG */ + ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, pDM_Odm->SupportAbility & (~ODM_BB_DIG)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Pause DIG !!\n")); + + /* Backup IGI value */ + if (pDM_DigTable->pause_dig_level == 0) { + pDM_DigTable->IGIBackup = pDM_DigTable->CurIGValue; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Backup IGI = 0x%x, new IGI = 0x%x\n", pDM_DigTable->IGIBackup, IGIValue)); + } + + /* Record IGI value */ + pDM_DigTable->pause_dig_value[pause_level] = IGIValue; + + /* Update pause level */ + pDM_DigTable->pause_dig_level = (pDM_DigTable->pause_dig_level | BIT(pause_level)); + + /* Write new IGI value */ + if (BIT(pause_level + 1) > pDM_DigTable->pause_dig_level) { + ODM_Write_DIG(pDM_Odm, IGIValue); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): IGI of higher level = 0x%x\n", IGIValue)); + } + break; + } + /* Resume DIG */ + case PHYDM_RESUME: + { + /* check if the level is illegal or not */ + if ((pDM_DigTable->pause_dig_level & (BIT(pause_level))) != 0) { + pDM_DigTable->pause_dig_level = pDM_DigTable->pause_dig_level & (~(BIT(pause_level))); + pDM_DigTable->pause_dig_value[pause_level] = 0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Resume DIG !!\n")); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Wrong resume level !!\n")); + break; + } + + /* Resume DIG */ + if (pDM_DigTable->pause_dig_level == 0) { + /* Write backup IGI value */ + ODM_Write_DIG(pDM_Odm, pDM_DigTable->IGIBackup); + pDM_DigTable->bIgnoreDIG = TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Write original IGI = 0x%x\n", pDM_DigTable->IGIBackup)); + + /* Enable DIG */ + ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, pDM_Odm->SupportAbility | ODM_BB_DIG); + break; + } + + if (BIT(pause_level) > pDM_DigTable->pause_dig_level) { + u1Byte max_level; + + /* Calculate the maximum level now */ + for (max_level = (pause_level - 1); max_level >= 0; max_level--) { + if ((pDM_DigTable->pause_dig_level & BIT(max_level)) > 0) + break; + } + + /* write IGI of lower level */ + ODM_Write_DIG(pDM_Odm, pDM_DigTable->pause_dig_value[max_level]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Write IGI (0x%x) of level (%d)\n", + pDM_DigTable->pause_dig_value[max_level], max_level)); + break; + } + break; + } + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): Wrong type !!\n")); + break; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): pause level = 0x%x, Current value = 0x%x\n", pDM_DigTable->pause_dig_level, IGIValue)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_PauseDIG(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", + pDM_DigTable->pause_dig_value[7], pDM_DigTable->pause_dig_value[6], pDM_DigTable->pause_dig_value[5], pDM_DigTable->pause_dig_value[4], + pDM_DigTable->pause_dig_value[3], pDM_DigTable->pause_dig_value[2], pDM_DigTable->pause_dig_value[1], pDM_DigTable->pause_dig_value[0])); + +} + +BOOLEAN +odm_DigAbort( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + prtl8192cd_priv priv = pDM_Odm->priv; +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER pAdapter = pDM_Odm->Adapter; + pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table; +#endif + + //SupportAbility + if(!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT)) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: SupportAbility ODM_BB_FA_CNT is disabled\n")); + return TRUE; + } + + //SupportAbility + if(!(pDM_Odm->SupportAbility & ODM_BB_DIG)) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: SupportAbility ODM_BB_DIG is disabled\n")); + return TRUE; + } + + //ScanInProcess + if(*(pDM_Odm->pbScanInProcess)) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: In Scan Progress \n")); + return TRUE; + } + + if(pDM_DigTable->bIgnoreDIG) + { + pDM_DigTable->bIgnoreDIG = FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: Ignore DIG \n")); + return TRUE; + } + + //add by Neil Chen to avoid PSD is processing + if(pDM_Odm->bDMInitialGainEnable == FALSE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: PSD is Processing \n")); + return TRUE; + } + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #if OS_WIN_FROM_WIN7(OS_VERSION) + if(IsAPModeExist( pAdapter) && pAdapter->bInHctTest) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: Is AP mode or In HCT Test \n")); + return TRUE; + } + #endif + + if(pDM_Odm->bBtHsOperation) + { + odm_DigForBtHsMode(pDM_Odm); + } + + if(!(pDM_Odm->SupportICType &(ODM_RTL8723A|ODM_RTL8188E))) + { + if(pRX_HP_Table->RXHP_flag == 1) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: In RXHP Operation \n")); + return TRUE; + } + } +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV + if((pDM_Odm->bLinked) && (pDM_Odm->Adapter->registrypriv.force_igi !=0)) + { + printk("pDM_Odm->RSSI_Min=%d \n",pDM_Odm->RSSI_Min); + ODM_Write_DIG(pDM_Odm,pDM_Odm->Adapter->registrypriv.force_igi); + return TRUE; + } + #endif +#else + if (!(priv->up_time > 5)) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Return: Not In DIG Operation Period \n")); + return TRUE; + } +#endif + + return FALSE; +} + +VOID +odm_DIGInit( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); +#endif + + pDM_DigTable->bStopDIG = FALSE; + pDM_DigTable->bIgnoreDIG = FALSE; + pDM_DigTable->bPSDInProgress = FALSE; + pDM_DigTable->CurIGValue = (u1Byte) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm)); + pDM_DigTable->RssiLowThresh = DM_DIG_THRESH_LOW; + pDM_DigTable->RssiHighThresh = DM_DIG_THRESH_HIGH; + pDM_DigTable->FALowThresh = DM_FALSEALARM_THRESH_LOW; + pDM_DigTable->FAHighThresh = DM_FALSEALARM_THRESH_HIGH; + pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT; + pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX; + pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN; + pDM_DigTable->PreCCK_CCAThres = 0xFF; + pDM_DigTable->CurCCK_CCAThres = 0x83; + pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC; + pDM_DigTable->LargeFAHit = 0; + pDM_DigTable->Recover_cnt = 0; + pDM_DigTable->bMediaConnect_0 = FALSE; + pDM_DigTable->bMediaConnect_1 = FALSE; + + //To Initialize pDM_Odm->bDMInitialGainEnable == FALSE to avoid DIG error + pDM_Odm->bDMInitialGainEnable = TRUE; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + pDM_DigTable->DIG_Dynamic_MIN_0 = 0x25; + pDM_DigTable->DIG_Dynamic_MIN_1 = 0x25; + + // For AP\ ADSL modified DIG + pDM_DigTable->bTpTarget = FALSE; + pDM_DigTable->bNoiseEst = TRUE; + pDM_DigTable->IGIOffset_A = 0; + pDM_DigTable->IGIOffset_B = 0; + pDM_DigTable->TpTrainTH_min = 0; + + // For RTL8881A + FalseAlmCnt->Cnt_Ofdm_fail_pre = 0; + + //Dyanmic EDCCA + if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + { + ODM_SetBBReg(pDM_Odm, 0xC50, 0xFFFF0000, 0xfafd); + } +#else + pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC; + pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC; + + //To Initi BT30 IGI + pDM_DigTable->BT30_CurIGI=0x32; + + ODM_Memory_Set(pDM_Odm, pDM_DigTable->pause_dig_value, 0, (DM_DIG_MAX_PAUSE_TYPE + 1)); + pDM_DigTable->pause_dig_level = 0; + ODM_Memory_Set(pDM_Odm, pDM_DigTable->pause_cckpd_value, 0, (DM_DIG_MAX_PAUSE_TYPE + 1)); + pDM_DigTable->pause_cckpd_level = 0; +#endif + + if(pDM_Odm->BoardType & (ODM_BOARD_EXT_PA|ODM_BOARD_EXT_LNA)) + { + pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; + pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; + } + else + { + pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC; + pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC; + } + +} + + +VOID +odm_DIG( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER pAdapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pDM_Odm->Adapter); +#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + prtl8192cd_priv priv = pDM_Odm->priv; + PSTA_INFO_T pEntry; +#endif + + // Common parameters + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + PFALSE_ALARM_STATISTICS pFalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); + BOOLEAN FirstConnect,FirstDisConnect; + u1Byte DIG_MaxOfMin, DIG_Dynamic_MIN; + u1Byte dm_dig_max, dm_dig_min; + u1Byte CurrentIGI = pDM_DigTable->CurIGValue; + u1Byte offset; + u4Byte dm_FA_thres[3]; + u4Byte TxTp = 0, RxTp = 0; + BOOLEAN bDFSBand = FALSE; + BOOLEAN bPerformance = TRUE, bFirstTpTarget = FALSE, bFirstCoverage = FALSE; +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + u4Byte TpTrainTH_MIN = DM_DIG_TP_Target_TH0; + static u1Byte TimeCnt = 0; + u1Byte i; +#endif + + if(odm_DigAbort(pDM_Odm) == TRUE) + return; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG()===========================>\n\n")); + + + //1 Update status +#if (RTL8192D_SUPPORT==1) + if(pDM_Odm->SupportICType == ODM_RTL8192D) + { + if(*(pDM_Odm->pMacPhyMode) == ODM_DMSP) + { + if(*(pDM_Odm->pbMasterOfDMSP)) + { + DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; + FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE); + FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE); + } + else + { + DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1; + FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == FALSE); + FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == TRUE); + } + } + else + { + if(*(pDM_Odm->pBandType) == ODM_BAND_5G) + { + DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; + FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE); + FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE); + } + else + { + DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1; + FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == FALSE); + FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == TRUE); + } + } + } + else +#endif + { + DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0; + FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE); + FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE); + } + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + //1 Noise Floor Estimate + //pDM_DigTable->bNoiseEst = (FirstConnect)?TRUE:pDM_DigTable->bNoiseEst; + //odm_InbandNoiseCalculate (pDM_Odm); + + //1 Mode decision + if(pDM_Odm->bLinked) + { + //2 Calculate total TP + for (i=0; ipODM_StaInfo[i]; + if(IS_STA_VALID(pEntry)) + { + RxTp += (u4Byte)(pEntry->rx_byte_cnt_LowMAW>>7); + TxTp += (u4Byte)(pEntry->tx_byte_cnt_LowMAW>>7); //Kbps + } + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TX TP = %dkbps, RX TP = %dkbps\n", TxTp, RxTp)); + } + + switch(pDM_Odm->priv->pshare->rf_ft_var.dig_cov_enable) + { + case 0: + { + bPerformance = TRUE; + break; + } + case 1: + { + bPerformance = FALSE; + break; + } + case 2: + { + if(pDM_Odm->bLinked) + { + if(pDM_DigTable->TpTrainTH_min > DM_DIG_TP_Target_TH0) + TpTrainTH_MIN = pDM_DigTable->TpTrainTH_min; + + if(pDM_DigTable->TpTrainTH_min > DM_DIG_TP_Target_TH1) + TpTrainTH_MIN = DM_DIG_TP_Target_TH1; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TP training mode lower bound = %dkbps\n", TpTrainTH_MIN)); + + //2 Decide DIG mode by total TP + if((TxTp + RxTp) > DM_DIG_TP_Target_TH1) // change to performance mode + { + bFirstTpTarget = (!pDM_DigTable->bTpTarget)?TRUE:FALSE; + pDM_DigTable->bTpTarget = TRUE; + bPerformance = TRUE; + } + else if((TxTp + RxTp) < TpTrainTH_MIN) // change to coverage mode + { + bFirstCoverage = (pDM_DigTable->bTpTarget)?TRUE:FALSE; + + if(TimeCnt < DM_DIG_TP_Training_Period) + { + pDM_DigTable->bTpTarget = FALSE; + bPerformance = FALSE; + TimeCnt++; + } + else + { + pDM_DigTable->bTpTarget = TRUE; + bPerformance = TRUE; + bFirstTpTarget = TRUE; + TimeCnt = 0; + } + } + else // remain previous mode + { + bPerformance = pDM_DigTable->bTpTarget; + + if(!bPerformance) + { + if(TimeCnt < DM_DIG_TP_Training_Period) + TimeCnt++; + else + { + pDM_DigTable->bTpTarget = TRUE; + bPerformance = TRUE; + bFirstTpTarget = TRUE; + TimeCnt = 0; + } + } + } + + if(!bPerformance) + pDM_DigTable->TpTrainTH_min = RxTp + TxTp; + + } + else + { + bPerformance = FALSE; + pDM_DigTable->TpTrainTH_min = 0; + } + break; + } + default: + bPerformance = TRUE; + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("====== DIG mode = %d ======\n", pDM_Odm->priv->pshare->rf_ft_var.dig_cov_enable)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("====== bPerformance = %d ======\n", bPerformance)); +#endif + + //1 Boundary Decision +#if (RTL8192C_SUPPORT==1) + if((pDM_Odm->SupportICType & ODM_RTL8192C) && (pDM_Odm->BoardType & (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_PA))) + { + //2 High power case + if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL)) + { + dm_dig_max = DM_DIG_MAX_AP_HP; + dm_dig_min = DM_DIG_MIN_AP_HP; + } + else + { + dm_dig_max = DM_DIG_MAX_NIC_HP; + dm_dig_min = DM_DIG_MIN_NIC_HP; + } + DIG_MaxOfMin = DM_DIG_MAX_AP_HP; + } + else +#endif + { +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + //2 For AP\ADSL + if(!bPerformance) + { + dm_dig_max = DM_DIG_MAX_AP_COVERAGR; + dm_dig_min = DM_DIG_MIN_AP_COVERAGE; + DIG_MaxOfMin = DM_DIG_MAX_OF_MIN_COVERAGE; + } + else + { + dm_dig_max = DM_DIG_MAX_AP; + dm_dig_min = DM_DIG_MIN_AP; + DIG_MaxOfMin = DM_DIG_MAX_OF_MIN; + } + + //4 DFS band + if (((*pDM_Odm->pChannel>= 52) &&(*pDM_Odm->pChannel <= 64)) || + ((*pDM_Odm->pChannel >= 100) && (*pDM_Odm->pChannel <= 140))) + { + bDFSBand = TRUE; + if (*pDM_Odm->pBandWidth == ODM_BW20M){ + dm_dig_min = DM_DIG_MIN_AP_DFS+2; + } + else{ + dm_dig_min = DM_DIG_MIN_AP_DFS; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): ====== In DFS band ======\n")); + } + + //4 TX2path + if (priv->pmib->dot11RFEntry.tx2path && !bDFSBand && (*(pDM_Odm->pWirelessMode) == ODM_WM_B)) + dm_dig_max = 0x2A; + +#if RTL8192E_SUPPORT +#ifdef HIGH_POWER_EXT_LNA + if ((pDM_Odm->SupportICType & (ODM_RTL8192E)) && (pDM_Odm->ExtLNA)) + dm_dig_max = 0x42; +#endif +#endif + +#else + //2 For WIN\CE + if(pDM_Odm->SupportICType >= ODM_RTL8188E) + dm_dig_max = 0x5A; + else + dm_dig_max = DM_DIG_MAX_NIC; + + if(pDM_Odm->SupportICType != ODM_RTL8821) + dm_dig_min = DM_DIG_MIN_NIC; + else + dm_dig_min = 0x1C; + + DIG_MaxOfMin = DM_DIG_MAX_AP; +#endif + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Absolutly upper bound = 0x%x, lower bound = 0x%x\n",dm_dig_max, dm_dig_min)); + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + // for P2P case + if(0 < *pDM_Odm->pu1ForcedIgiLb) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): P2P case: Force IGI lb to: %u !!!!!!\n", *pDM_Odm->pu1ForcedIgiLb)); + dm_dig_min = *pDM_Odm->pu1ForcedIgiLb; + dm_dig_max = (dm_dig_min <= dm_dig_max) ? (dm_dig_max) : (dm_dig_min + 1); + } +#endif + + //1 Adjust boundary by RSSI + if(pDM_Odm->bLinked && bPerformance) + { + //2 Modify DIG upper bound +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + offset = 15; +#else + //4 Modify DIG upper bound for 92E, 8723A\B, 8821 & 8812 BT + if((pDM_Odm->SupportICType & (ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8812|ODM_RTL8821|ODM_RTL8723A)) && (pDM_Odm->bBtLimitedDig==1)) + { + offset = 10; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Coex. case: Force upper bound to RSSI + %d !!!!!!\n", offset)); + } + else + offset = 15; +#endif + + if((pDM_Odm->RSSI_Min + offset) > dm_dig_max ) + pDM_DigTable->rx_gain_range_max = dm_dig_max; + else if((pDM_Odm->RSSI_Min + offset) < dm_dig_min ) + pDM_DigTable->rx_gain_range_max = dm_dig_min; + else + pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + offset; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + //2 Modify DIG lower bound + //if(pDM_Odm->bOneEntryOnly) + { + if(pDM_Odm->RSSI_Min < dm_dig_min) + DIG_Dynamic_MIN = dm_dig_min; + else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin) + DIG_Dynamic_MIN = DIG_MaxOfMin; + else + DIG_Dynamic_MIN = pDM_Odm->RSSI_Min; + } +#else + { + //4 For AP +#ifdef __ECOS + HAL_REORDER_BARRIER(); +#else + rmb(); +#endif + if (bDFSBand) + { + DIG_Dynamic_MIN = dm_dig_min; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DFS band: Force lower bound to 0x%x after link !!!!!!\n", dm_dig_min)); + } + else + { + if(pDM_Odm->RSSI_Min < dm_dig_min) + DIG_Dynamic_MIN = dm_dig_min; + else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin) + DIG_Dynamic_MIN = DIG_MaxOfMin; + else + DIG_Dynamic_MIN = pDM_Odm->RSSI_Min; + } + } +#endif + } + else + { +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + if(bPerformance && bDFSBand) + { + pDM_DigTable->rx_gain_range_max = 0x28; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DFS band: Force upper bound to 0x%x before link !!!!!!\n", pDM_DigTable->rx_gain_range_max)); + } + else +#endif + { + pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_OF_MIN; + } + DIG_Dynamic_MIN = dm_dig_min; + } + + //1 Force Lower Bound for AntDiv + if(pDM_Odm->bLinked && !pDM_Odm->bOneEntryOnly) + { + if((pDM_Odm->SupportICType & ODM_ANTDIV_SUPPORT) && (pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)) + { + if (pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV || pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV) { + if (pDM_DigTable->AntDiv_RSSI_max > DIG_MaxOfMin) + DIG_Dynamic_MIN = DIG_MaxOfMin; + else + DIG_Dynamic_MIN = (u1Byte) pDM_DigTable->AntDiv_RSSI_max; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Antenna diversity case: Force lower bound to 0x%x !!!!!!\n", DIG_Dynamic_MIN)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Antenna diversity case: RSSI_max = 0x%x !!!!!!\n", pDM_DigTable->AntDiv_RSSI_max)); + } + } + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Adjust boundary by RSSI Upper bound = 0x%x, Lower bound = 0x%x\n", + pDM_DigTable->rx_gain_range_max, DIG_Dynamic_MIN)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Link status: bLinked = %d, RSSI = %d, bFirstConnect = %d, bFirsrDisConnect = %d\n\n", + pDM_Odm->bLinked, pDM_Odm->RSSI_Min, FirstConnect, FirstDisConnect)); + + //1 Modify DIG lower bound, deal with abnormal case + //2 Abnormal false alarm case +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + if(bDFSBand) + { + pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; + } + else +#endif + { + if(!pDM_Odm->bLinked) + { + pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; + + if (FirstDisConnect) + pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; + } + else + pDM_DigTable->rx_gain_range_min = odm_ForbiddenIGICheck(pDM_Odm, DIG_Dynamic_MIN, CurrentIGI); + } + + //2 Abnormal # beacon case +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if(pDM_Odm->bLinked && !FirstConnect) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Beacon Num (%d)\n", pDM_Odm->PhyDbgInfo.NumQryBeaconPkt)); + if((pDM_Odm->PhyDbgInfo.NumQryBeaconPkt < 5) && (pDM_Odm->bsta_state)) + { + pDM_DigTable->rx_gain_range_min = dm_dig_min; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnrormal #beacon (%d) case in STA mode: Force lower bound to 0x%x !!!!!!\n\n", + pDM_Odm->PhyDbgInfo.NumQryBeaconPkt, pDM_DigTable->rx_gain_range_min)); + } + } +#endif + + //2 Abnormal lower bound case + if(pDM_DigTable->rx_gain_range_min > pDM_DigTable->rx_gain_range_max) + { + pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnrormal lower bound case: Force lower bound to 0x%x !!!!!!\n\n",pDM_DigTable->rx_gain_range_min)); + } + + + //1 False alarm threshold decision + odm_FAThresholdCheck(pDM_Odm, bDFSBand, bPerformance, RxTp, TxTp, dm_FA_thres); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): False alarm threshold = %d, %d, %d \n\n", dm_FA_thres[0], dm_FA_thres[1], dm_FA_thres[2])); + + //1 Adjust initial gain by false alarm + if(pDM_Odm->bLinked && bPerformance) + { + //2 After link + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Adjust IGI after link\n")); + + if(bFirstTpTarget || (FirstConnect && bPerformance)) + { + pDM_DigTable->LargeFAHit = 0; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + if(bDFSBand) + { + if(pDM_Odm->RSSI_Min > 0x28) + CurrentIGI = 0x28; + else + CurrentIGI = pDM_Odm->RSSI_Min; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DFS band: One-shot to 0x28 upmost!!!!!!\n")); + } + else +#endif + { + if(pDM_Odm->RSSI_Min < DIG_MaxOfMin) + { + if(CurrentIGI < pDM_Odm->RSSI_Min) + CurrentIGI = pDM_Odm->RSSI_Min; + } + else + { + if(CurrentIGI < DIG_MaxOfMin) + CurrentIGI = DIG_MaxOfMin; + } + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) +#if (RTL8812A_SUPPORT==1) + if(pDM_Odm->SupportICType == ODM_RTL8812) + ODM_ConfigBBWithHeaderFile(pDM_Odm, CONFIG_BB_AGC_TAB_DIFF); +#endif +#endif + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First connect case: IGI does on-shot to 0x%x\n", CurrentIGI)); + + } + else + { + if(pFalseAlmCnt->Cnt_all > dm_FA_thres[2]) + CurrentIGI = CurrentIGI + 4; + else if (pFalseAlmCnt->Cnt_all > dm_FA_thres[1]) + CurrentIGI = CurrentIGI + 2; + else if(pFalseAlmCnt->Cnt_all < dm_FA_thres[0]) + CurrentIGI = CurrentIGI - 2; + + //4 Abnormal # beacon case +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if((pDM_Odm->PhyDbgInfo.NumQryBeaconPkt < 5) && (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH1) && (pDM_Odm->bsta_state)) + { + CurrentIGI = pDM_DigTable->rx_gain_range_min; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Abnormal #beacon (%d) case: IGI does one-shot to 0x%x\n", + pDM_Odm->PhyDbgInfo.NumQryBeaconPkt, CurrentIGI)); + } +#endif + } + } + else + { + //2 Before link + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Adjust IGI before link\n")); + + if(FirstDisConnect || bFirstCoverage) + { + CurrentIGI = dm_dig_min; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First disconnect case: IGI does on-shot to lower bound\n")); + } + else + { + if(pFalseAlmCnt->Cnt_all > dm_FA_thres[2]) + CurrentIGI = CurrentIGI + 4; + else if (pFalseAlmCnt->Cnt_all > dm_FA_thres[1]) + CurrentIGI = CurrentIGI + 2; + else if(pFalseAlmCnt->Cnt_all < dm_FA_thres[0]) + CurrentIGI = CurrentIGI - 2; + } + } + + //1 Check initial gain by upper/lower bound + if(CurrentIGI < pDM_DigTable->rx_gain_range_min) + CurrentIGI = pDM_DigTable->rx_gain_range_min; + + if(CurrentIGI > pDM_DigTable->rx_gain_range_max) + CurrentIGI = pDM_DigTable->rx_gain_range_max; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue=0x%x, TotalFA = %d\n\n", CurrentIGI, pFalseAlmCnt->Cnt_all)); + + //1 High power RSSI threshold +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + if((pDM_Odm->SupportICType == ODM_RTL8723A)&& (pHalData->UndecoratedSmoothedPWDB > DM_DIG_HIGH_PWR_THRESHOLD)) + { + // High power IGI lower bound + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): UndecoratedSmoothedPWDB(%#x)\n", pHalData->UndecoratedSmoothedPWDB)); + if(CurrentIGI < DM_DIG_HIGH_PWR_IGI_LOWER_BOUND) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue(%#x)\n", pDM_DigTable->CurIGValue)); + //pDM_DigTable->CurIGValue = DM_DIG_HIGH_PWR_IGI_LOWER_BOUND; + CurrentIGI=DM_DIG_HIGH_PWR_IGI_LOWER_BOUND; + } + } + if((pDM_Odm->SupportICType & ODM_RTL8723A) && IS_WIRELESS_MODE_G(pAdapter)) + { + if(pHalData->UndecoratedSmoothedPWDB > 0x28) + { + if(CurrentIGI < DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND) + { + //pDM_DigTable->CurIGValue = DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND; + CurrentIGI = DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND; + } + } + } +#endif + + //1 Update status +#if (RTL8192D_SUPPORT==1) + if(pDM_Odm->SupportICType == ODM_RTL8192D) + { + //sherry delete DualMacSmartConncurrent 20110517 + if(*(pDM_Odm->pMacPhyMode) == ODM_DMSP) + { + ODM_Write_DIG_DMSP(pDM_Odm, CurrentIGI);//ODM_Write_DIG_DMSP(pDM_Odm, pDM_DigTable->CurIGValue); + if(*(pDM_Odm->pbMasterOfDMSP)) + { + pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; + pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; + } + else + { + pDM_DigTable->bMediaConnect_1 = pDM_Odm->bLinked; + pDM_DigTable->DIG_Dynamic_MIN_1 = DIG_Dynamic_MIN; + } + } + else + { + ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); + if(*(pDM_Odm->pBandType) == ODM_BAND_5G) + { + pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; + pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; + } + else + { + pDM_DigTable->bMediaConnect_1 = pDM_Odm->bLinked; + pDM_DigTable->DIG_Dynamic_MIN_1 = DIG_Dynamic_MIN; + } + } + } + else +#endif + { +#if ((DM_ODM_SUPPORT_TYPE & ODM_WIN) || ((DM_ODM_SUPPORT_TYPE & ODM_CE) && (ODM_CONFIG_BT_COEXIST == 1))) + if(pDM_Odm->bBtHsOperation) + { + if(pDM_Odm->bLinked) + { + if(pDM_DigTable->BT30_CurIGI > (CurrentIGI)) + ODM_Write_DIG(pDM_Odm, CurrentIGI); + else + ODM_Write_DIG(pDM_Odm, pDM_DigTable->BT30_CurIGI); + + pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; + pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; + } + else + { + if(pDM_Odm->bLinkInProcess) + ODM_Write_DIG(pDM_Odm, 0x1c); + else if(pDM_Odm->bBtConnectProcess) + ODM_Write_DIG(pDM_Odm, 0x28); + else + ODM_Write_DIG(pDM_Odm, pDM_DigTable->BT30_CurIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); + } + } + else // BT is not using +#endif + { + ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); + pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked; + pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN; + } + } +} + +VOID +odm_DIGbyRSSI_LPS( + IN PVOID pDM_VOID + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PFALSE_ALARM_STATISTICS pFalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); + + u1Byte RSSI_Lower=DM_DIG_MIN_NIC; //0x1E or 0x1C + u1Byte CurrentIGI=pDM_Odm->RSSI_Min; + + if(odm_DigAbort(pDM_Odm) == TRUE) + return; + + CurrentIGI=CurrentIGI+RSSI_OFFSET_DIG; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIGbyRSSI_LPS()==>\n")); + + // Using FW PS mode to make IGI + //Adjust by FA in LPS MODE + if(pFalseAlmCnt->Cnt_all> DM_DIG_FA_TH2_LPS) + CurrentIGI = CurrentIGI+4; + else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS) + CurrentIGI = CurrentIGI+2; + else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS) + CurrentIGI = CurrentIGI-2; + + + //Lower bound checking + + //RSSI Lower bound check + if((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC) + RSSI_Lower =(pDM_Odm->RSSI_Min-10); + else + RSSI_Lower =DM_DIG_MIN_NIC; + + //Upper and Lower Bound checking + if(CurrentIGI > DM_DIG_MAX_NIC) + CurrentIGI=DM_DIG_MAX_NIC; + else if(CurrentIGI < RSSI_Lower) + CurrentIGI =RSSI_Lower; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIGbyRSSI_LPS(): pFalseAlmCnt->Cnt_all = %d\n",pFalseAlmCnt->Cnt_all)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIGbyRSSI_LPS(): pDM_Odm->RSSI_Min = %d\n",pDM_Odm->RSSI_Min)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIGbyRSSI_LPS(): CurrentIGI = 0x%x\n",CurrentIGI)); + + ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue); +#endif +} + +//3============================================================ +//3 FASLE ALARM CHECK +//3============================================================ + +VOID +odm_FalseAlarmCounterStatistics( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); + u4Byte ret_value; + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +//Mark there, and check this in odm_DMWatchDog +#if 0 //(DM_ODM_SUPPORT_TYPE == ODM_AP) + prtl8192cd_priv priv = pDM_Odm->priv; + if( (priv->auto_channel != 0) && (priv->auto_channel != 2) ) + return; +#endif +#endif + + if(!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT)) + return; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics()======>\n")); + +#if (ODM_IC_11N_SERIES_SUPPORT == 1) + if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES) + { + + //hold ofdm counter + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); //hold page C counter + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); //hold page D counter + + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord); + FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff); + FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16); + + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord); + FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff); + FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16); + + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord); + FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff); + FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16); + + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord); + FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff); + + FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal + + FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail + + FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail; + +#if (RTL8188E_SUPPORT==1) + if(pDM_Odm->SupportICType == ODM_RTL8188E) + { + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_SC_CNT_11N, bMaskDWord); + FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff); + FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16); + } +#endif + +#if (RTL8192D_SUPPORT==1) + if(pDM_Odm->SupportICType == ODM_RTL8192D) + { + odm_GetCCKFalseAlarm_92D(pDM_Odm); + } + else +#endif + { + //hold cck counter + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT12, 1); + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT14, 1); + + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0); + FalseAlmCnt->Cnt_Cck_fail = ret_value; + + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_MSB_11N, bMaskByte3); + FalseAlmCnt->Cnt_Cck_fail += (ret_value& 0xff)<<8; + + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord); + FalseAlmCnt->Cnt_CCK_CCA = ((ret_value&0xFF)<<8) |((ret_value&0xFF00)>>8); + } + + FalseAlmCnt->Cnt_all = ( FalseAlmCnt->Cnt_Fast_Fsync + + FalseAlmCnt->Cnt_SB_Search_fail + + FalseAlmCnt->Cnt_Parity_Fail + + FalseAlmCnt->Cnt_Rate_Illegal + + FalseAlmCnt->Cnt_Crc8_fail + + FalseAlmCnt->Cnt_Mcs_fail + + FalseAlmCnt->Cnt_Cck_fail); + + FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA; + +#if (RTL8192C_SUPPORT==1) + if(pDM_Odm->SupportICType == ODM_RTL8192C) + odm_ResetFACounter_92C(pDM_Odm); +#endif + +#if (RTL8192D_SUPPORT==1) + if(pDM_Odm->SupportICType == ODM_RTL8192D) + odm_ResetFACounter_92D(pDM_Odm); +#endif + + if(pDM_Odm->SupportICType >=ODM_RTL8723A) + { + //reset false alarm counter registers + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 1); + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 0); + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 1); + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 0); + + //update ofdm counter + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 0); //update page C counter + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 0); //update page D counter + + //reset CCK CCA counter + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 0); + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 2); + //reset CCK FA counter + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 0); + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 2); + } + + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n", + FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Parity_Fail=%d, Cnt_Rate_Illegal=%d\n", + FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n", + FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail)); + } +#endif + +#if (ODM_IC_11AC_SERIES_SUPPORT == 1) + if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + { + u4Byte CCKenable; + + /* read OFDM FA counter */ + FalseAlmCnt->Cnt_Ofdm_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_11AC, bMaskLWord); + + + /* Read CCK FA counter */ + FalseAlmCnt->Cnt_Cck_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_11AC, bMaskLWord); + + /* read CCK/OFDM CCA counter */ + ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11AC, bMaskDWord); + FalseAlmCnt->Cnt_OFDM_CCA = (ret_value & 0xffff0000) >> 16; + FalseAlmCnt->Cnt_CCK_CCA = ret_value & 0xffff; + +#if (RTL8881A_SUPPORT==1) + /* For 8881A */ + if(pDM_Odm->SupportICType == ODM_RTL8881A) + { + u4Byte Cnt_Ofdm_fail_temp = 0; + + if(FalseAlmCnt->Cnt_Ofdm_fail >= FalseAlmCnt->Cnt_Ofdm_fail_pre) + { + Cnt_Ofdm_fail_temp = FalseAlmCnt->Cnt_Ofdm_fail_pre; + FalseAlmCnt->Cnt_Ofdm_fail_pre = FalseAlmCnt->Cnt_Ofdm_fail; + FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Ofdm_fail - Cnt_Ofdm_fail_temp; + } + else + FalseAlmCnt->Cnt_Ofdm_fail_pre = FalseAlmCnt->Cnt_Ofdm_fail; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail_pre)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Ofdm_fail_pre=%d\n", Cnt_Ofdm_fail_temp)); + + /* Reset FA counter by enable/disable OFDM */ + if(FalseAlmCnt->Cnt_Ofdm_fail_pre >= 0x7fff) + { + // reset OFDM + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_RX_PATH_11AC, BIT29,0); + ODM_SetBBReg(pDM_Odm, ODM_REG_BB_RX_PATH_11AC, BIT29,1); + FalseAlmCnt->Cnt_Ofdm_fail_pre = 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Reset false alarm counter\n")); + } + } +#endif + + /* reset OFDM FA coutner */ + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 1); + ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 0); + + /* reset CCK FA counter */ + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 0); + ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 1); + + /* reset CCA counter */ + ODM_SetBBReg(pDM_Odm, ODM_REG_RST_RPT_11AC, BIT0, 1); + ODM_SetBBReg(pDM_Odm, ODM_REG_RST_RPT_11AC, BIT0, 0); + + CCKenable = ODM_GetBBReg(pDM_Odm, ODM_REG_BB_RX_PATH_11AC, BIT28); + if(CCKenable)//if(*pDM_Odm->pBandType == ODM_BAND_2_4G) + { + FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail + FalseAlmCnt->Cnt_Cck_fail; + FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_CCK_CCA + FalseAlmCnt->Cnt_OFDM_CCA; + } + else + { + FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail; + FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA; + } + + } +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_OFDM_CCA=%d\n", FalseAlmCnt->Cnt_OFDM_CCA)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_CCK_CCA=%d\n", FalseAlmCnt->Cnt_CCK_CCA)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_CCA_all=%d\n", FalseAlmCnt->Cnt_CCA_all)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Cck_fail=%d\n", FalseAlmCnt->Cnt_Cck_fail)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Cnt_Ofdm_fail=%d\n", FalseAlmCnt->Cnt_Ofdm_fail)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("odm_FalseAlarmCounterStatistics(): Total False Alarm=%d\n\n", FalseAlmCnt->Cnt_all)); +} + +//3============================================================ +//3 CCK Packet Detect Threshold +//3============================================================ + +VOID +odm_PauseCCKPacketDetection( + IN PVOID pDM_VOID, + IN PHYDM_PAUSE_TYPE PauseType, + IN PHYDM_PAUSE_LEVEL pause_level, + IN u1Byte CCKPDThreshold +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection()=========> level = %d\n", pause_level)); + + if ((pDM_DigTable->pause_cckpd_level == 0) && (!(pDM_Odm->SupportAbility & ODM_BB_CCK_PD) || !(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("Return: SupportAbility ODM_BB_CCK_PD or ODM_BB_FA_CNT is disabled\n")); + return; + } + + if (pause_level > DM_DIG_MAX_PAUSE_TYPE) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCK_PD, ODM_DBG_LOUD, + ("odm_PauseCCKPacketDetection(): Return: Wrong pause level !!\n")); + return; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): pause level = 0x%x, Current value = 0x%x\n", pDM_DigTable->pause_cckpd_level, CCKPDThreshold)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", + pDM_DigTable->pause_cckpd_value[7], pDM_DigTable->pause_cckpd_value[6], pDM_DigTable->pause_cckpd_value[5], pDM_DigTable->pause_cckpd_value[4], + pDM_DigTable->pause_cckpd_value[3], pDM_DigTable->pause_cckpd_value[2], pDM_DigTable->pause_cckpd_value[1], pDM_DigTable->pause_cckpd_value[0])); + + switch (PauseType) { + /* Pause CCK Packet Detection Threshold */ + case PHYDM_PAUSE: + { + /* Disable CCK PD */ + ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, pDM_Odm->SupportAbility & (~ODM_BB_CCK_PD)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): Pause CCK packet detection threshold !!\n")); + + /* Backup original CCK PD threshold decided by CCK PD mechanism */ + if (pDM_DigTable->pause_cckpd_level == 0) { + pDM_DigTable->CCKPDBackup = pDM_DigTable->CurCCK_CCAThres; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCK_PD, ODM_DBG_LOUD, + ("odm_PauseCCKPacketDetection(): Backup CCKPD = 0x%x, new CCKPD = 0x%x\n", pDM_DigTable->CCKPDBackup, CCKPDThreshold)); + } + + /* Update pause level */ + pDM_DigTable->pause_cckpd_level = (pDM_DigTable->pause_cckpd_level | BIT(pause_level)); + + /* Record CCK PD threshold */ + pDM_DigTable->pause_cckpd_value[pause_level] = CCKPDThreshold; + + /* Write new CCK PD threshold */ + if (BIT(pause_level + 1) > pDM_DigTable->pause_cckpd_level) { + ODM_Write_CCK_CCA_Thres(pDM_Odm, CCKPDThreshold); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): CCKPD of higher level = 0x%x\n", CCKPDThreshold)); + } + break; + } + /* Resume CCK Packet Detection Threshold */ + case PHYDM_RESUME: + { + /* check if the level is illegal or not */ + if ((pDM_DigTable->pause_cckpd_level & (BIT(pause_level))) != 0) { + pDM_DigTable->pause_cckpd_level = pDM_DigTable->pause_cckpd_level & (~(BIT(pause_level))); + pDM_DigTable->pause_cckpd_value[pause_level] = 0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): Resume CCK PD !!\n")); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): Wrong resume level !!\n")); + break; + } + + /* Resume DIG */ + if (pDM_DigTable->pause_cckpd_level == 0) { + /* Write backup IGI value */ + ODM_Write_CCK_CCA_Thres(pDM_Odm, pDM_DigTable->CCKPDBackup); + /* pDM_DigTable->bIgnoreDIG = TRUE; */ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): Write original CCKPD = 0x%x\n", pDM_DigTable->CCKPDBackup)); + + /* Enable DIG */ + ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, pDM_Odm->SupportAbility | ODM_BB_CCK_PD); + break; + } + + if (BIT(pause_level) > pDM_DigTable->pause_cckpd_level) { + u1Byte max_level; + + /* Calculate the maximum level now */ + for (max_level = (pause_level - 1); max_level >= 0; max_level--) { + if ((pDM_DigTable->pause_cckpd_level & BIT(max_level)) > 0) + break; + } + + /* write CCKPD of lower level */ + ODM_Write_CCK_CCA_Thres(pDM_Odm, pDM_DigTable->pause_cckpd_value[max_level]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): Write CCKPD (0x%x) of level (%d)\n", + pDM_DigTable->pause_cckpd_value[max_level], max_level)); + break; + } + break; + } + default: + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): Wrong type !!\n")); + break; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): pause level = 0x%x, Current value = 0x%x\n", pDM_DigTable->pause_cckpd_level, CCKPDThreshold)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("odm_PauseCCKPacketDetection(): pause value = 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", + pDM_DigTable->pause_cckpd_value[7], pDM_DigTable->pause_cckpd_value[6], pDM_DigTable->pause_cckpd_value[5], pDM_DigTable->pause_cckpd_value[4], + pDM_DigTable->pause_cckpd_value[3], pDM_DigTable->pause_cckpd_value[2], pDM_DigTable->pause_cckpd_value[1], pDM_DigTable->pause_cckpd_value[0])); +} + + +VOID +odm_CCKPacketDetectionThresh( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); + u1Byte CurCCK_CCAThres, RSSI_thd = 55; + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +//modify by Guo.Mingzhi 2011-12-29 + if (pDM_Odm->bDualMacSmartConcurrent == TRUE) +// if (pDM_Odm->bDualMacSmartConcurrent == FALSE) + return; + if(pDM_Odm->bBtHsOperation) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh() write 0xcd for BT HS mode!!\n")); + ODM_Write_CCK_CCA_Thres(pDM_Odm, 0xcd); + return; + } +#endif + + if((!(pDM_Odm->SupportAbility & ODM_BB_CCK_PD)) ||(!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh() return==========\n")); +#ifdef MCR_WIRELESS_EXTEND + ODM_Write_CCK_CCA_Thres(pDM_Odm, 0x43); +#endif + return; + } + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + if(pDM_Odm->ExtLNA) + return; +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh() ==========>\n")); + + if (pDM_Odm->bLinked) + { + if (pDM_Odm->RSSI_Min > RSSI_thd) + CurCCK_CCAThres = 0xcd; + else if ((pDM_Odm->RSSI_Min <= RSSI_thd) && (pDM_Odm->RSSI_Min > 10)) + CurCCK_CCAThres = 0x83; + else + { + if(FalseAlmCnt->Cnt_Cck_fail > 1000) + CurCCK_CCAThres = 0x83; + else + CurCCK_CCAThres = 0x40; + } + } else { + if(FalseAlmCnt->Cnt_Cck_fail > 1000) + CurCCK_CCAThres = 0x83; + else + CurCCK_CCAThres = 0x40; + } + +#if (RTL8192D_SUPPORT==1) + if((pDM_Odm->SupportICType == ODM_RTL8192D) && (*pDM_Odm->pBandType == ODM_BAND_2_4G)) + ODM_Write_CCK_CCA_Thres_92D(pDM_Odm, CurCCK_CCAThres); + else +#endif + ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_CCK_PD, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh() CurCCK_CCAThres = 0x%x\n",CurCCK_CCAThres)); +} + +VOID +ODM_Write_CCK_CCA_Thres( + IN PVOID pDM_VOID, + IN u1Byte CurCCK_CCAThres + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + + if(pDM_DigTable->CurCCK_CCAThres!=CurCCK_CCAThres) //modify by Guo.Mingzhi 2012-01-03 + { + ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA,pDM_Odm), CurCCK_CCAThres); + } + pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres; + pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres; +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +// <20130108, Kordan> E.g., With LNA used, we make the Rx power smaller to have a better EVM. (Asked by Willis) +VOID +odm_RFEControl( + IN PDM_ODM_T pDM_Odm, + IN u8Byte RSSIVal + ) +{ + PADAPTER Adapter = (PADAPTER)pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + static u1Byte TRSW_HighPwr = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("===> odm_RFEControl, RSSI = %d, TRSW_HighPwr = 0x%X, pHalData->RFEType = %d\n", + RSSIVal, TRSW_HighPwr, pHalData->RFEType )); + + if (pHalData->RFEType == 3) { + + pDM_Odm->RSSI_TRSW = RSSIVal; + + if (pDM_Odm->RSSI_TRSW >= pDM_Odm->RSSI_TRSW_H) + { + TRSW_HighPwr = 1; // Switch to + PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT1|BIT0, 0x1); // Set ANTSW=1/ANTSWB=0 for SW control + PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT9|BIT8, 0x3); // Set ANTSW=1/ANTSWB=0 for SW control + + } + else if (pDM_Odm->RSSI_TRSW <= pDM_Odm->RSSI_TRSW_L) + { + TRSW_HighPwr = 0; // Switched back + PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT1|BIT0, 0x1); // Set ANTSW=1/ANTSWB=0 for SW control + PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT9|BIT8, 0x0); // Set ANTSW=1/ANTSWB=0 for SW control + + } + } + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("(pDM_Odm->RSSI_TRSW_H, pDM_Odm->RSSI_TRSW_L) = (%d, %d)\n", pDM_Odm->RSSI_TRSW_H, pDM_Odm->RSSI_TRSW_L)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("(RSSIVal, RSSIVal, pDM_Odm->RSSI_TRSW_iso) = (%d, %d, %d)\n", + RSSIVal, pDM_Odm->RSSI_TRSW_iso, pDM_Odm->RSSI_TRSW)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("<=== odm_RFEControl, RSSI = %d, TRSW_HighPwr = 0x%X\n", RSSIVal, TRSW_HighPwr)); +} + +VOID +odm_MPT_DIGWorkItemCallback( + IN PVOID pContext + ) +{ + PADAPTER Adapter = (PADAPTER)pContext; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + ODM_MPT_DIG(pDM_Odm); +} + +VOID +odm_MPT_DIGCallback( + PRT_TIMER pTimer +) +{ + PADAPTER Adapter = (PADAPTER)pTimer->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + + #if DEV_BUS_TYPE==RT_PCI_INTERFACE + #if USE_WORKITEM + PlatformScheduleWorkItem(&pDM_Odm->MPT_DIGWorkitem); + #else + ODM_MPT_DIG(pDM_Odm); + #endif + #else + PlatformScheduleWorkItem(&pDM_Odm->MPT_DIGWorkitem); + #endif + +} + +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) +VOID +odm_MPT_DIGCallback( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if USE_WORKITEM + PlatformScheduleWorkItem(&pDM_Odm->MPT_DIGWorkitem); +#else + ODM_MPT_DIG(pDM_Odm); +#endif +} +#endif + +#if (DM_ODM_SUPPORT_TYPE != ODM_CE) +VOID +odm_MPT_Write_DIG( + IN PVOID pDM_VOID, + IN u1Byte CurIGValue +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + + ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_A,pDM_Odm), CurIGValue); + + if(pDM_Odm->RFType > ODM_1T1R) + ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_B,pDM_Odm), CurIGValue); + + if((pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) && (pDM_Odm->RFType > ODM_2T2R)) + { + ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_C,pDM_Odm), CurIGValue); + ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_D,pDM_Odm), CurIGValue); + } + + pDM_DigTable->CurIGValue = CurIGValue; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("CurIGValue = 0x%x\n", CurIGValue)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("pDM_Odm->RFType = 0x%x\n", pDM_Odm->RFType)); +} + +VOID +ODM_MPT_DIG( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + PFALSE_ALARM_STATISTICS pFalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure( pDM_Odm, PHYDM_FALSEALMCNT); + u1Byte CurrentIGI = pDM_DigTable->CurIGValue; + u1Byte DIG_Upper = 0x40, DIG_Lower = 0x20; + u4Byte RXOK_cal; + u4Byte RxPWDBAve_final; + u1Byte IGI_A = 0x20, IGI_B = 0x20; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + + #if ODM_FIX_2G_DIG + IGI_A = 0x22; + IGI_B = 0x24; + #endif + +#else + if (!(pDM_Odm->priv->pshare->rf_ft_var.mp_specific && pDM_Odm->priv->pshare->mp_dig_on)) + return; + + if (*pDM_Odm->pBandType == ODM_BAND_5G) + DIG_Lower = 0x22; +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("===> ODM_MPT_DIG, pBandType = %d\n", *pDM_Odm->pBandType)); + +#if (ODM_FIX_2G_DIG || (DM_ODM_SUPPORT_TYPE & ODM_AP)) + if (*pDM_Odm->pBandType == ODM_BAND_5G || (pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_RTL8822B))) // for 5G or 8814 +#else + if (1) // for both 2G/5G +#endif + { + odm_FalseAlarmCounterStatistics(pDM_Odm); + + RXOK_cal = pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK + pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM; + RxPWDBAve_final = (RXOK_cal != 0)?pDM_Odm->RxPWDBAve/RXOK_cal:0; + + pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK = 0; + pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM = 0; + pDM_Odm->RxPWDBAve = 0; + pDM_Odm->MPDIG_2G = FALSE; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + pDM_Odm->Times_2G = 0; +#endif + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("RX OK = %d\n", RXOK_cal)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("RSSI = %d\n", RxPWDBAve_final)); + + if (RXOK_cal >= 70 && RxPWDBAve_final <= 40) + { + if (CurrentIGI > 0x24) + odm_MPT_Write_DIG(pDM_Odm, 0x24); + } + else + { + if(pFalseAlmCnt->Cnt_all > 1000){ + CurrentIGI = CurrentIGI + 8; + } + else if(pFalseAlmCnt->Cnt_all > 200){ + CurrentIGI = CurrentIGI + 4; + } + else if (pFalseAlmCnt->Cnt_all > 50){ + CurrentIGI = CurrentIGI + 2; + } + else if (pFalseAlmCnt->Cnt_all < 2){ + CurrentIGI = CurrentIGI - 2; + } + + if (CurrentIGI < DIG_Lower ){ + CurrentIGI = DIG_Lower; + } + + if(CurrentIGI > DIG_Upper){ + CurrentIGI = DIG_Upper; + } + + odm_MPT_Write_DIG(pDM_Odm, CurrentIGI); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG = 0x%x, Cnt_all = %d, Cnt_Ofdm_fail = %d, Cnt_Cck_fail = %d\n", + CurrentIGI, pFalseAlmCnt->Cnt_all, pFalseAlmCnt->Cnt_Ofdm_fail, pFalseAlmCnt->Cnt_Cck_fail)); + } + } + else + { + if(pDM_Odm->MPDIG_2G == FALSE) + { + if((pDM_Odm->SupportPlatform & ODM_WIN) && !(pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_RTL8822B))) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("===> Fix IGI\n")); + ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_A,pDM_Odm), IGI_A); + ODM_Write1Byte( pDM_Odm, ODM_REG(IGI_B,pDM_Odm), IGI_B); + pDM_DigTable->CurIGValue = IGI_B; + } + else + odm_MPT_Write_DIG(pDM_Odm, IGI_A); + } + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + pDM_Odm->Times_2G++; + + if (pDM_Odm->Times_2G == 3) +#endif + { + pDM_Odm->MPDIG_2G = TRUE; + } + } + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (pDM_Odm->SupportICType == ODM_RTL8812) + odm_RFEControl(pDM_Odm, RxPWDBAve_final); +#endif + + ODM_SetTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer, 700); +} +#endif diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_dig.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_dig.h new file mode 100644 index 000000000..e7c89edb7 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_dig.h @@ -0,0 +1,327 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMDIG_H__ +#define __PHYDMDIG_H__ + +#define DIG_VERSION "1.8" /*2015.07.01*/ + +/* Pause DIG & CCKPD */ +#define DM_DIG_MAX_PAUSE_TYPE 0x7 + +typedef struct _Dynamic_Initial_Gain_Threshold_ +{ + BOOLEAN bStopDIG; // for debug + BOOLEAN bIgnoreDIG; + BOOLEAN bPSDInProgress; + + u1Byte Dig_Enable_Flag; + u1Byte Dig_Ext_Port_Stage; + + int RssiLowThresh; + int RssiHighThresh; + + u4Byte FALowThresh; + u4Byte FAHighThresh; + + u1Byte CurSTAConnectState; + u1Byte PreSTAConnectState; + u1Byte CurMultiSTAConnectState; + + u1Byte PreIGValue; + u1Byte CurIGValue; + u1Byte BackupIGValue; //MP DIG + u1Byte BT30_CurIGI; + u1Byte IGIBackup; + + s1Byte BackoffVal; + s1Byte BackoffVal_range_max; + s1Byte BackoffVal_range_min; + u1Byte rx_gain_range_max; + u1Byte rx_gain_range_min; + u1Byte Rssi_val_min; + + u1Byte PreCCK_CCAThres; + u1Byte CurCCK_CCAThres; + u1Byte PreCCKPDState; + u1Byte CurCCKPDState; + u1Byte CCKPDBackup; + u1Byte pause_cckpd_level; + u1Byte pause_cckpd_value[DM_DIG_MAX_PAUSE_TYPE + 1]; + + u1Byte LargeFAHit; + u1Byte ForbiddenIGI; + u4Byte Recover_cnt; + + u1Byte DIG_Dynamic_MIN_0; + u1Byte DIG_Dynamic_MIN_1; + BOOLEAN bMediaConnect_0; + BOOLEAN bMediaConnect_1; + + u4Byte AntDiv_RSSI_max; + u4Byte RSSI_max; + + u1Byte *bP2PInProcess; + + u1Byte pause_dig_level; + u1Byte pause_dig_value[DM_DIG_MAX_PAUSE_TYPE + 1]; + +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + BOOLEAN bTpTarget; + BOOLEAN bNoiseEst; + u4Byte TpTrainTH_min; + u1Byte IGIOffset_A; + u1Byte IGIOffset_B; +#endif +}DIG_T,*pDIG_T; + +typedef struct _FALSE_ALARM_STATISTICS{ + u4Byte Cnt_Parity_Fail; + u4Byte Cnt_Rate_Illegal; + u4Byte Cnt_Crc8_fail; + u4Byte Cnt_Mcs_fail; + u4Byte Cnt_Ofdm_fail; + u4Byte Cnt_Ofdm_fail_pre; //For RTL8881A + u4Byte Cnt_Cck_fail; + u4Byte Cnt_all; + u4Byte Cnt_Fast_Fsync; + u4Byte Cnt_SB_Search_fail; + u4Byte Cnt_OFDM_CCA; + u4Byte Cnt_CCK_CCA; + u4Byte Cnt_CCA_all; + u4Byte Cnt_BW_USC; //Gary + u4Byte Cnt_BW_LSC; //Gary +}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS; + +typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition +{ + DIG_TYPE_THRESH_HIGH = 0, + DIG_TYPE_THRESH_LOW = 1, + DIG_TYPE_BACKOFF = 2, + DIG_TYPE_RX_GAIN_MIN = 3, + DIG_TYPE_RX_GAIN_MAX = 4, + DIG_TYPE_ENABLE = 5, + DIG_TYPE_DISABLE = 6, + DIG_OP_TYPE_MAX +}DM_DIG_OP_E; + +/* +typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition +{ + CCK_PD_STAGE_LowRssi = 0, + CCK_PD_STAGE_HighRssi = 1, + CCK_PD_STAGE_MAX = 3, +}DM_CCK_PDTH_E; + +typedef enum tag_DIG_EXT_PORT_ALGO_Definition +{ + DIG_EXT_PORT_STAGE_0 = 0, + DIG_EXT_PORT_STAGE_1 = 1, + DIG_EXT_PORT_STAGE_2 = 2, + DIG_EXT_PORT_STAGE_3 = 3, + DIG_EXT_PORT_STAGE_MAX = 4, +}DM_DIG_EXT_PORT_ALG_E; + +typedef enum tag_DIG_Connect_Definition +{ + DIG_STA_DISCONNECT = 0, + DIG_STA_CONNECT = 1, + DIG_STA_BEFORE_CONNECT = 2, + DIG_MultiSTA_DISCONNECT = 3, + DIG_MultiSTA_CONNECT = 4, + DIG_CONNECT_MAX +}DM_DIG_CONNECT_E; + + +#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;} + +#define DM_MultiSTA_InitGainChangeNotify_CONNECT(_ADAPTER) \ + DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_CONNECT) + +#define DM_MultiSTA_InitGainChangeNotify_DISCONNECT(_ADAPTER) \ + DM_MultiSTA_InitGainChangeNotify(DIG_MultiSTA_DISCONNECT) +*/ + +typedef enum tag_PHYDM_Pause_Type { + PHYDM_PAUSE = BIT0, + PHYDM_RESUME = BIT1 +} PHYDM_PAUSE_TYPE; + +typedef enum tag_PHYDM_Pause_Level { +/* number of pause level can't exceed DM_DIG_MAX_PAUSE_TYPE */ + PHYDM_PAUSE_LEVEL_0 = 0, + PHYDM_PAUSE_LEVEL_1 = 1, + PHYDM_PAUSE_LEVEL_2 = 2, + PHYDM_PAUSE_LEVEL_3 = 3, + PHYDM_PAUSE_LEVEL_4 = 4, + PHYDM_PAUSE_LEVEL_5 = 5, + PHYDM_PAUSE_LEVEL_6 = 6, + PHYDM_PAUSE_LEVEL_7 = DM_DIG_MAX_PAUSE_TYPE /* maximum level */ +} PHYDM_PAUSE_LEVEL; + + +#define DM_DIG_THRESH_HIGH 40 +#define DM_DIG_THRESH_LOW 35 + +#define DM_FALSEALARM_THRESH_LOW 400 +#define DM_FALSEALARM_THRESH_HIGH 1000 + +#define DM_DIG_MAX_NIC 0x3e +#define DM_DIG_MIN_NIC 0x1e //0x22//0x1c +#define DM_DIG_MAX_OF_MIN_NIC 0x3e + +#define DM_DIG_MAX_AP 0x3e +#define DM_DIG_MIN_AP 0x1c +#define DM_DIG_MAX_OF_MIN 0x2A //0x32 +#define DM_DIG_MIN_AP_DFS 0x20 + +#define DM_DIG_MAX_NIC_HP 0x46 +#define DM_DIG_MIN_NIC_HP 0x2e + +#define DM_DIG_MAX_AP_HP 0x42 +#define DM_DIG_MIN_AP_HP 0x30 + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) +#define DM_DIG_MAX_AP_COVERAGR 0x26 +#define DM_DIG_MIN_AP_COVERAGE 0x1c +#define DM_DIG_MAX_OF_MIN_COVERAGE 0x22 + +#define DM_DIG_TP_Target_TH0 500 +#define DM_DIG_TP_Target_TH1 1000 +#define DM_DIG_TP_Training_Period 10 +#endif + +//vivi 92c&92d has different definition, 20110504 +//this is for 92c +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) + #ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV + #define DM_DIG_FA_TH0 0x80//0x20 + #else + #define DM_DIG_FA_TH0 0x200//0x20 + #endif +#else + #define DM_DIG_FA_TH0 0x200//0x20 +#endif + +#define DM_DIG_FA_TH1 0x300 +#define DM_DIG_FA_TH2 0x400 +//this is for 92d +#define DM_DIG_FA_TH0_92D 0x100 +#define DM_DIG_FA_TH1_92D 0x400 +#define DM_DIG_FA_TH2_92D 0x600 + +#define DM_DIG_BACKOFF_MAX 12 +#define DM_DIG_BACKOFF_MIN -4 +#define DM_DIG_BACKOFF_DEFAULT 10 + +#define DM_DIG_FA_TH0_LPS 4 //-> 4 in lps +#define DM_DIG_FA_TH1_LPS 15 //-> 15 lps +#define DM_DIG_FA_TH2_LPS 30 //-> 30 lps +#define RSSI_OFFSET_DIG 0x05 + +VOID +ODM_ChangeDynamicInitGainThresh( + IN PVOID pDM_VOID, + IN u4Byte DM_Type, + IN u4Byte DM_Value + ); + +VOID +ODM_Write_DIG( + IN PVOID pDM_VOID, + IN u1Byte CurrentIGI + ); + +VOID +odm_PauseDIG( + IN PVOID pDM_VOID, + IN PHYDM_PAUSE_TYPE PauseType, + IN PHYDM_PAUSE_LEVEL pause_level, + IN u1Byte IGIValue + ); + +VOID +odm_DIGInit( + IN PVOID pDM_VOID + ); + +VOID +odm_DIG( + IN PVOID pDM_VOID + ); + +VOID +odm_DIGbyRSSI_LPS( + IN PVOID pDM_VOID + ); + +VOID +odm_FalseAlarmCounterStatistics( + IN PVOID pDM_VOID + ); + +VOID +odm_PauseCCKPacketDetection( + IN PVOID pDM_VOID, + IN PHYDM_PAUSE_TYPE PauseType, + IN PHYDM_PAUSE_LEVEL pause_level, + IN u1Byte CCKPDThreshold + ); + +VOID +odm_CCKPacketDetectionThresh( + IN PVOID pDM_VOID + ); + +VOID +ODM_Write_CCK_CCA_Thres( + IN PVOID pDM_VOID, + IN u1Byte CurCCK_CCAThres + ); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +odm_MPT_DIGCallback( + PRT_TIMER pTimer +); + +VOID +odm_MPT_DIGWorkItemCallback( + IN PVOID pContext + ); + +#endif + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) +VOID +odm_MPT_DIGCallback( + IN PVOID pDM_VOID +); +#endif + +#if (DM_ODM_SUPPORT_TYPE != ODM_CE) +VOID +ODM_MPT_DIG( + IN PVOID pDM_VOID +); +#endif + + +#endif diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_dynamicbbpowersaving.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_dynamicbbpowersaving.c new file mode 100644 index 000000000..ab01c4760 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_dynamicbbpowersaving.c @@ -0,0 +1,219 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +VOID +odm_DynamicBBPowerSavingInit( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable; + + pDM_PSTable->PreCCAState = CCA_MAX; + pDM_PSTable->CurCCAState = CCA_MAX; + pDM_PSTable->PreRFState = RF_MAX; + pDM_PSTable->CurRFState = RF_MAX; + pDM_PSTable->Rssi_val_min = 0; + pDM_PSTable->initialize = 0; +} + + +VOID +odm_DynamicBBPowerSaving( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + + if (pDM_Odm->SupportICType != ODM_RTL8723A) + return; + if(!(pDM_Odm->SupportAbility & ODM_BB_PWR_SAVE)) + return; + if(!(pDM_Odm->SupportPlatform & (ODM_WIN|ODM_CE))) + return; + + //1 2.Power Saving for 92C + if((pDM_Odm->SupportICType == ODM_RTL8192C) &&(pDM_Odm->RFType == ODM_2T2R)) + { + odm_1R_CCA(pDM_Odm); + } + + // 20100628 Joseph: Turn off BB power save for 88CE because it makesthroughput unstable. + // 20100831 Joseph: Turn ON BB power save again after modifying AGC delay from 900ns ot 600ns. + //1 3.Power Saving for 88C + else + { + ODM_RF_Saving(pDM_Odm, FALSE); + } +#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +} + +VOID +odm_1R_CCA( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable; + + if(pDM_Odm->RSSI_Min!= 0xFF) + { + + if(pDM_PSTable->PreCCAState == CCA_2R) + { + if(pDM_Odm->RSSI_Min >= 35) + pDM_PSTable->CurCCAState = CCA_1R; + else + pDM_PSTable->CurCCAState = CCA_2R; + + } + else{ + if(pDM_Odm->RSSI_Min <= 30) + pDM_PSTable->CurCCAState = CCA_2R; + else + pDM_PSTable->CurCCAState = CCA_1R; + } + } + else{ + pDM_PSTable->CurCCAState=CCA_MAX; + } + + if(pDM_PSTable->PreCCAState != pDM_PSTable->CurCCAState) + { + if(pDM_PSTable->CurCCAState == CCA_1R) + { + if( pDM_Odm->RFType ==ODM_2T2R ) + { + ODM_SetBBReg(pDM_Odm, 0xc04 , bMaskByte0, 0x13); + //PHY_SetBBReg(pAdapter, 0xe70, bMaskByte3, 0x20); + } + else + { + ODM_SetBBReg(pDM_Odm, 0xc04 , bMaskByte0, 0x23); + //PHY_SetBBReg(pAdapter, 0xe70, 0x7fc00000, 0x10c); // Set RegE70[30:22] = 9b'100001100 + } + } + else + { + ODM_SetBBReg(pDM_Odm, 0xc04 , bMaskByte0, 0x33); + //PHY_SetBBReg(pAdapter,0xe70, bMaskByte3, 0x63); + } + pDM_PSTable->PreCCAState = pDM_PSTable->CurCCAState; + } +} + +void +ODM_RF_Saving( + IN PVOID pDM_VOID, + IN u1Byte bForceInNormal + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) + pPS_T pDM_PSTable = &pDM_Odm->DM_PSTable; + u1Byte Rssi_Up_bound = 30 ; + u1Byte Rssi_Low_bound = 25; +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if(pDM_Odm->PatchID == 40 ) //RT_CID_819x_FUNAI_TV + { + Rssi_Up_bound = 50 ; + Rssi_Low_bound = 45; + } +#endif + if(pDM_PSTable->initialize == 0){ + + pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14; + pDM_PSTable->RegC70 = (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord)&BIT3)>>3; + pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24; + pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12; + //Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord); + pDM_PSTable->initialize = 1; + } + + if(!bForceInNormal) + { + if(pDM_Odm->RSSI_Min != 0xFF) + { + if(pDM_PSTable->PreRFState == RF_Normal) + { + if(pDM_Odm->RSSI_Min >= Rssi_Up_bound) + pDM_PSTable->CurRFState = RF_Save; + else + pDM_PSTable->CurRFState = RF_Normal; + } + else{ + if(pDM_Odm->RSSI_Min <= Rssi_Low_bound) + pDM_PSTable->CurRFState = RF_Normal; + else + pDM_PSTable->CurRFState = RF_Save; + } + } + else + pDM_PSTable->CurRFState=RF_MAX; + } + else + { + pDM_PSTable->CurRFState = RF_Normal; + } + + if(pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) + { + if(pDM_PSTable->CurRFState == RF_Save) + { + // 8723 RSSI report will be wrong. Set 0x874[5]=1 when enter BB power saving mode. + // Suggested by SD3 Yu-Nan. 2011.01.20. + if(pDM_Odm->SupportICType == ODM_RTL8723A) + { + ODM_SetBBReg(pDM_Odm, 0x874 , BIT5, 0x1); //Reg874[5]=1b'1 + } + ODM_SetBBReg(pDM_Odm, 0x874 , 0x1C0000, 0x2); //Reg874[20:18]=3'b010 + ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, 0); //RegC70[3]=1'b0 + ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); //Reg85C[31:24]=0x63 + ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); //Reg874[15:14]=2'b10 + ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); //RegA75[7:4]=0x3 + ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); //Reg818[28]=1'b0 + ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x1); //Reg818[28]=1'b1 + } + else + { + ODM_SetBBReg(pDM_Odm, 0x874 , 0x1CC000, pDM_PSTable->Reg874); + ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, pDM_PSTable->RegC70); + ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C); + ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74); + ODM_SetBBReg(pDM_Odm,0x818, BIT28, 0x0); + + if(pDM_Odm->SupportICType == ODM_RTL8723A) + { + ODM_SetBBReg(pDM_Odm,0x874 , BIT5, 0x0); //Reg874[5]=1b'0 + } + } + pDM_PSTable->PreRFState =pDM_PSTable->CurRFState; + } +#endif +} + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_dynamicbbpowersaving.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_dynamicbbpowersaving.h new file mode 100644 index 000000000..365c17181 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_dynamicbbpowersaving.h @@ -0,0 +1,63 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMDYNAMICBBPOWERSAVING_H__ +#define __PHYDMDYNAMICBBPOWERSAVING_H__ + +#define DYNAMIC_BBPWRSAV_VERSION "1.0" + +typedef struct _Dynamic_Power_Saving_ +{ + u1Byte PreCCAState; + u1Byte CurCCAState; + + u1Byte PreRFState; + u1Byte CurRFState; + + int Rssi_val_min; + + u1Byte initialize; + u4Byte Reg874,RegC70,Reg85C,RegA74; + +}PS_T,*pPS_T; + +#define dm_RF_Saving ODM_RF_Saving + +void ODM_RF_Saving( + IN PVOID pDM_VOID, + IN u1Byte bForceInNormal +); + +VOID +odm_DynamicBBPowerSavingInit( + IN PVOID pDM_VOID + ); + +VOID +odm_DynamicBBPowerSaving( + IN PVOID pDM_VOID + ); + +VOID +odm_1R_CCA( + IN PVOID pDM_VOID + ); + +#endif diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_dynamictxpower.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_dynamictxpower.c new file mode 100644 index 000000000..7a9d3ec83 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_dynamictxpower.c @@ -0,0 +1,633 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +VOID +odm_DynamicTxPowerInit( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + #if DEV_BUS_TYPE==RT_USB_INTERFACE + if(RT_GetInterfaceSelection(Adapter) == INTF_SEL1_USB_High_Power) + { + odm_DynamicTxPowerSavePowerIndex(pDM_Odm); + pMgntInfo->bDynamicTxPowerEnable = TRUE; + } + else + #else + //so 92c pci do not need dynamic tx power? vivi check it later + if(IS_HARDWARE_TYPE_8192D(Adapter)) + pMgntInfo->bDynamicTxPowerEnable = TRUE; + else + pMgntInfo->bDynamicTxPowerEnable = FALSE; + #endif + + + pHalData->LastDTPLvl = TxHighPwrLevel_Normal; + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + + +#endif + +} + +VOID +odm_DynamicTxPowerSavePowerIndex( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) + u1Byte index; + u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + for(index = 0; index< 6; index++) + pHalData->PowerIndex_backup[index] = PlatformEFIORead1Byte(Adapter, Power_Index_REG[index]); + + +#endif +#endif +} + +VOID +odm_DynamicTxPowerRestorePowerIndex( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) + u1Byte index; + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + for(index = 0; index< 6; index++) + PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], pHalData->PowerIndex_backup[index]); + + +#endif +#endif +} + +VOID +odm_DynamicTxPowerWritePowerIndex( + IN PVOID pDM_VOID, + IN u1Byte Value) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte index; + u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; + + for(index = 0; index< 6; index++) + //PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], Value); + ODM_Write1Byte(pDM_Odm, Power_Index_REG[index], Value); + +} + + +VOID +odm_DynamicTxPower( + IN PVOID pDM_VOID + ) +{ + // + // For AP/ADSL use prtl8192cd_priv + // For CE/NIC use PADAPTER + // + //PADAPTER pAdapter = pDM_Odm->Adapter; +// prtl8192cd_priv priv = pDM_Odm->priv; + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)) + return; + // + // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate + // at the same time. In the stage2/3, we need to prive universal interface and merge all + // HW dynamic mechanism. + // + switch (pDM_Odm->SupportPlatform) + { + case ODM_WIN: + case ODM_CE: + odm_DynamicTxPowerNIC(pDM_Odm); + break; + case ODM_AP: + odm_DynamicTxPowerAP(pDM_Odm); + break; + + case ODM_ADSL: + //odm_DIGAP(pDM_Odm); + break; + } + + +} + + +VOID +odm_DynamicTxPowerNIC( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR)) + return; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + + if(pDM_Odm->SupportICType == ODM_RTL8192C) + { + odm_DynamicTxPower_92C(pDM_Odm); + } + else if(pDM_Odm->SupportICType == ODM_RTL8192D) + { + odm_DynamicTxPower_92D(pDM_Odm); + } + else if (pDM_Odm->SupportICType == ODM_RTL8821) + { +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = GetDefaultMgntInfo(Adapter); + + if (pMgntInfo->RegRspPwr == 1) + { + if(pDM_Odm->RSSI_Min > 60) + { + ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11AC, BIT20|BIT19|BIT18, 1); // Resp TXAGC offset = -3dB + + } + else if(pDM_Odm->RSSI_Min < 55) + { + ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11AC, BIT20|BIT19|BIT18, 0); // Resp TXAGC offset = 0dB + } + } +#endif + } +#endif +} + +VOID +odm_DynamicTxPowerAP( + IN PVOID pDM_VOID + + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + +//#if ((RTL8192C_SUPPORT==1) || (RTL8192D_SUPPORT==1) || (RTL8188E_SUPPORT==1) || (RTL8812E_SUPPORT==1)) + + + prtl8192cd_priv priv = pDM_Odm->priv; + s4Byte i; + s2Byte pwr_thd = TX_POWER_NEAR_FIELD_THRESH_AP; + + if(!priv->pshare->rf_ft_var.tx_pwr_ctrl) + return; + +#if ((RTL8812E_SUPPORT==1) || (RTL8881A_SUPPORT==1) || (RTL8814A_SUPPORT==1)) + if (pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8881A | ODM_RTL8814A)) + pwr_thd = TX_POWER_NEAR_FIELD_THRESH_8812; +#endif + +#if defined(CONFIG_RTL_92D_SUPPORT) || defined(CONFIG_RTL_92C_SUPPORT) + if(CHIP_VER_92X_SERIES(priv)) + { +#ifdef HIGH_POWER_EXT_PA + if(pDM_Odm->ExtPA) + tx_power_control(priv); +#endif + } +#endif + /* + * Check if station is near by to use lower tx power + */ + + if ((priv->up_time % 3) == 0 ) { + int disable_pwr_ctrl = ((pDM_Odm->FalseAlmCnt.Cnt_all > 1000 ) || ((pDM_Odm->FalseAlmCnt.Cnt_all > 300 ) && ((RTL_R8(0xc50) & 0x7f) >= 0x32))) ? 1 : 0; + + for(i=0; ipODM_StaInfo[i]; + if(IS_STA_VALID(pstat) ) { + if(disable_pwr_ctrl) + pstat->hp_level = 0; + else if ((pstat->hp_level == 0) && (pstat->rssi > pwr_thd)) + pstat->hp_level = 1; + else if ((pstat->hp_level == 1) && (pstat->rssi < (pwr_thd-8))) + pstat->hp_level = 0; + } + } + +#if defined(CONFIG_WLAN_HAL_8192EE) + if (GET_CHIP_VER(priv) == VERSION_8192E) { + if( !disable_pwr_ctrl && (pDM_Odm->RSSI_Min != 0xff) ) { + if(pDM_Odm->RSSI_Min > pwr_thd) + RRSR_power_control_11n(priv, 1 ); + else if(pDM_Odm->RSSI_Min < (pwr_thd-8)) + RRSR_power_control_11n(priv, 0 ); + } else { + RRSR_power_control_11n(priv, 0 ); + } + } +#endif + +#ifdef CONFIG_WLAN_HAL_8814AE + if (GET_CHIP_VER(priv) == VERSION_8814A) { + if (!disable_pwr_ctrl && (pDM_Odm->RSSI_Min != 0xff)) { + if (pDM_Odm->RSSI_Min > pwr_thd) + RRSR_power_control_14(priv, 1); + else if (pDM_Odm->RSSI_Min < (pwr_thd-8)) + RRSR_power_control_14(priv, 0); + } else { + RRSR_power_control_14(priv, 0); + } + } +#endif + + } +//#endif + +#endif +} + + +VOID +odm_DynamicTxPower_92C( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + s4Byte UndecoratedSmoothedPWDB; + + // 2012/01/12 MH According to Luke's suggestion, only high power will support the feature. + if (pDM_Odm->ExtPA == FALSE) + return; + + // STA not connected and AP not connected + if((!pMgntInfo->bMediaConnect) && + (pHalData->EntryMinUndecoratedSmoothedPWDB == 0)) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("Not connected to any \n")); + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + + //the LastDTPlvl should reset when disconnect, + //otherwise the tx power level wouldn't change when disconnect and connect again. + // Maddest 20091220. + pHalData->LastDTPLvl=TxHighPwrLevel_Normal; + return; + } + +#if (INTEL_PROXIMITY_SUPPORT == 1) + // Intel set fixed tx power + if(pMgntInfo->IntelProximityModeInfo.PowerOutput > 0) + { + switch(pMgntInfo->IntelProximityModeInfo.PowerOutput){ + case 1: + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_100; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_100\n")); + break; + case 2: + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_70; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_70\n")); + break; + case 3: + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_50; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_50\n")); + break; + case 4: + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_35; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_35\n")); + break; + case 5: + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_15; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_15\n")); + break; + default: + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_100; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_100\n")); + break; + } + } + else +#endif + { + if( (pMgntInfo->bDynamicTxPowerEnable != TRUE) || + pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER) + { + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + } + else + { + if(pMgntInfo->bMediaConnect) // Default port + { + if(ACTING_AS_AP(Adapter) || ACTING_AS_IBSS(Adapter)) + { + UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); + } + else + { + UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); + } + } + else // associated entry pwdb + { + UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); + } + + if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2) + { + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n")); + } + else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) && + (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) ) + { + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n")); + } + else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5)) + { + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n")); + } + } + } + if( pHalData->DynamicTxHighPowerLvl != pHalData->LastDTPLvl ) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("PHY_SetTxPowerLevel8192C() Channel = %d \n" , pHalData->CurrentChannel)); + PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel); + if( (pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Normal) && + (pHalData->LastDTPLvl == TxHighPwrLevel_Level1 || pHalData->LastDTPLvl == TxHighPwrLevel_Level2)) //TxHighPwrLevel_Normal + odm_DynamicTxPowerRestorePowerIndex(pDM_Odm); + else if(pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) + odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x14); + else if(pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) + odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x10); + } + pHalData->LastDTPLvl = pHalData->DynamicTxHighPowerLvl; + + + + +#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +} + + +VOID +odm_DynamicTxPower_92D( + IN PVOID pDM_VOID + ) +{ +#if (RTL8192D_SUPPORT==1) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + s4Byte UndecoratedSmoothedPWDB; + + PADAPTER BuddyAdapter = Adapter->BuddyAdapter; + BOOLEAN bGetValueFromBuddyAdapter = dm_DualMacGetParameterFromBuddyAdapter(Adapter); + u1Byte HighPowerLvlBackForMac0 = TxHighPwrLevel_Level1; + + // 2012/01/12 MH According to Luke's suggestion, only high power will support the feature. + if (pDM_Odm->ExtPA == FALSE) + return; + + // If dynamic high power is disabled. + if( (pMgntInfo->bDynamicTxPowerEnable != TRUE) || + pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER) + { + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + return; + } + + // STA not connected and AP not connected + if((!pMgntInfo->bMediaConnect) && + (pHalData->EntryMinUndecoratedSmoothedPWDB == 0)) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("Not connected to any \n")); + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + + //the LastDTPlvl should reset when disconnect, + //otherwise the tx power level wouldn't change when disconnect and connect again. + // Maddest 20091220. + pHalData->LastDTPLvl=TxHighPwrLevel_Normal; + return; + } + + if(pMgntInfo->bMediaConnect) // Default port + { + if(ACTING_AS_AP(Adapter) || pMgntInfo->mIbss) + { + UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); + } + else + { + UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); + } + } + else // associated entry pwdb + { + UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); + } + + if(IS_HARDWARE_TYPE_8192D(Adapter) && GET_HAL_DATA(Adapter)->CurrentBandType == 1){ + if(UndecoratedSmoothedPWDB >= 0x33) + { + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level2 (TxPwr=0x0)\n")); + } + else if((UndecoratedSmoothedPWDB <0x33) && + (UndecoratedSmoothedPWDB >= 0x2b) ) + { + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level1 (TxPwr=0x10)\n")); + } + else if(UndecoratedSmoothedPWDB < 0x2b) + { + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Normal\n")); + } + + } + else + + { + if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2) + { + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n")); + } + else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) && + (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) ) + { + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n")); + } + else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5)) + { + pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n")); + } + + } + +//sherry delete flag 20110517 + if(bGetValueFromBuddyAdapter) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 1 \n")); + if(Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR,DBG_LOUD,("dm_DynamicTxPower() change value \n")); + HighPowerLvlBackForMac0 = pHalData->DynamicTxHighPowerLvl; + pHalData->DynamicTxHighPowerLvl = Adapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP; + PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel); + pHalData->DynamicTxHighPowerLvl = HighPowerLvlBackForMac0; + Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = FALSE; + } + } + + if( (pHalData->DynamicTxHighPowerLvl != pHalData->LastDTPLvl) ) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("PHY_SetTxPowerLevel8192S() Channel = %d \n" , pHalData->CurrentChannel)); + if(Adapter->DualMacSmartConcurrent == TRUE) + { + if(BuddyAdapter == NULL) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter == NULL case \n")); + if(!Adapter->bSlaveOfDMSP) + { + PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel); + } + } + else + { + if(pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMSP \n")); + if(Adapter->bSlaveOfDMSP) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR,DBG_LOUD,("dm_DynamicTxPower() bslave case \n")); + BuddyAdapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = TRUE; + BuddyAdapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP = pHalData->DynamicTxHighPowerLvl; + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR,DBG_LOUD,("dm_DynamicTxPower() master case \n")); + if(!bGetValueFromBuddyAdapter) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 0 \n")); + PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel); + } + } + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_DYNAMIC_TXPWR,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMDP\n")); + PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel); + } + } + } + else + { + PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel); + } + + } + pHalData->LastDTPLvl = pHalData->DynamicTxHighPowerLvl; + + +#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#endif +} + +VOID +odm_DynamicTxPower_8821( + IN PVOID pDM_VOID, + IN pu1Byte pDesc, + IN u1Byte macId + ) +{ +#if (RTL8821A_SUPPORT == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PSTA_INFO_T pEntry; + u1Byte reg0xc56_byte; + u1Byte reg0xe56_byte; + u1Byte txpwr_offset = 0; + + pEntry = pDM_Odm->pODM_StaInfo[macId]; + + reg0xc56_byte = ODM_Read1Byte(pDM_Odm, 0xc56); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("reg0xc56_byte=%d\n", reg0xc56_byte)); + + if (pEntry[macId].rssi_stat.UndecoratedSmoothedPWDB > 85) { + + /* Avoid TXAGC error after TX power offset is applied. + For example: Reg0xc56=0x6, if txpwr_offset=3( reduce 11dB ) + Total power = 6-11= -5( overflow!! ), PA may be burned ! + so txpwr_offset should be adjusted by Reg0xc56*/ + + if (reg0xc56_byte < 7) + txpwr_offset = 1; + else if (reg0xc56_byte < 11) + txpwr_offset = 2; + else + txpwr_offset = 3; + + SET_TX_DESC_TX_POWER_OFFSET_8812(pDesc, txpwr_offset); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_DynamicTxPower_8821: RSSI=%d, txpwr_offset=%d\n", pEntry[macId].rssi_stat.UndecoratedSmoothedPWDB, txpwr_offset)); + + } else{ + SET_TX_DESC_TX_POWER_OFFSET_8812(pDesc, txpwr_offset); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_TXPWR, DBG_LOUD, ("odm_DynamicTxPower_8821: RSSI=%d, txpwr_offset=%d\n", pEntry[macId].rssi_stat.UndecoratedSmoothedPWDB, txpwr_offset)); + + } +#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ +#endif /*#if (RTL8821A_SUPPORT==1)*/ +} + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_dynamictxpower.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_dynamictxpower.h new file mode 100644 index 000000000..db61bf85d --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_dynamictxpower.h @@ -0,0 +1,98 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMDYNAMICTXPOWER_H__ +#define __PHYDMDYNAMICTXPOWER_H__ + +/*#define DYNAMIC_TXPWR_VERSION "1.0"*/ +#define DYNAMIC_TXPWR_VERSION "1.1" /*2015.01.13*/ + +#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 +#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 +#define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F +#define TX_POWER_NEAR_FIELD_THRESH_8812 60 + +#define TxHighPwrLevel_Normal 0 +#define TxHighPwrLevel_Level1 1 +#define TxHighPwrLevel_Level2 2 +#define TxHighPwrLevel_BT1 3 +#define TxHighPwrLevel_BT2 4 +#define TxHighPwrLevel_15 5 +#define TxHighPwrLevel_35 6 +#define TxHighPwrLevel_50 7 +#define TxHighPwrLevel_70 8 +#define TxHighPwrLevel_100 9 + +VOID +odm_DynamicTxPowerInit( + IN PVOID pDM_VOID + ); + +VOID +odm_DynamicTxPowerRestorePowerIndex( + IN PVOID pDM_VOID + ); + +VOID +odm_DynamicTxPowerNIC( + IN PVOID pDM_VOID + ); + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) +VOID +odm_DynamicTxPowerSavePowerIndex( + IN PVOID pDM_VOID + ); + +VOID +odm_DynamicTxPowerWritePowerIndex( + IN PVOID pDM_VOID, + IN u1Byte Value); + +VOID +odm_DynamicTxPower_92C( + IN PVOID pDM_VOID + ); + +VOID +odm_DynamicTxPower_92D( + IN PVOID pDM_VOID + ); + +VOID +odm_DynamicTxPower_8821( + IN PVOID pDM_VOID, + IN pu1Byte pDesc, + IN u1Byte macId + ); + +#endif + +VOID +odm_DynamicTxPower( + IN PVOID pDM_VOID + ); + +VOID +odm_DynamicTxPowerAP( + IN PVOID pDM_VOID + ); + +#endif diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_edcaturbocheck.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_edcaturbocheck.c new file mode 100644 index 000000000..6d3dc6d38 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_edcaturbocheck.c @@ -0,0 +1,835 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +VOID +ODM_EdcaTurboInit( + IN PVOID pDM_VOID) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + +#if (DM_ODM_SUPPORT_TYPE==ODM_WIN) + PADAPTER Adapter = NULL; + HAL_DATA_TYPE *pHalData = NULL; + + if(pDM_Odm->Adapter==NULL) { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EdcaTurboInit fail!!!\n")); + return; + } + + Adapter=pDM_Odm->Adapter; + pHalData=GET_HAL_DATA(Adapter); + + pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE; + pDM_Odm->DM_EDCA_Table.bIsCurRDLState = FALSE; + pHalData->bIsAnyNonBEPkts = FALSE; + +#elif(DM_ODM_SUPPORT_TYPE==ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE; + pDM_Odm->DM_EDCA_Table.bIsCurRDLState = FALSE; + Adapter->recvpriv.bIsAnyNonBEPkts =FALSE; + +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial VO PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_VO_PARAM))); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial VI PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_VI_PARAM))); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BE PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BE_PARAM))); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BK PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BK_PARAM))); + + +} // ODM_InitEdcaTurbo + +VOID +odm_EdcaTurboCheck( + IN PVOID pDM_VOID + ) +{ + // + // For AP/ADSL use prtl8192cd_priv + // For CE/NIC use PADAPTER + // + + // + // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate + // at the same time. In the stage2/3, we need to prive universal interface and merge all + // HW dynamic mechanism. + // + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("odm_EdcaTurboCheck========================>\n")); + + if(!(pDM_Odm->SupportAbility& ODM_MAC_EDCA_TURBO )) + return; + + switch (pDM_Odm->SupportPlatform) + { + case ODM_WIN: + +#if(DM_ODM_SUPPORT_TYPE==ODM_WIN) + odm_EdcaTurboCheckMP(pDM_Odm); +#endif + break; + + case ODM_CE: +#if(DM_ODM_SUPPORT_TYPE==ODM_CE) + odm_EdcaTurboCheckCE(pDM_Odm); +#endif + break; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("<========================odm_EdcaTurboCheck\n")); + +} // odm_CheckEdcaTurbo + +#if(DM_ODM_SUPPORT_TYPE==ODM_CE) + + +VOID +odm_EdcaTurboCheckCE( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + u32 EDCA_BE_UL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_UL[pMgntInfo->IOTPeer]; + u32 EDCA_BE_DL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_DL[pMgntInfo->IOTPeer]; + u32 ICType=pDM_Odm->SupportICType; + u32 IOTPeer=0; + u8 WirelessMode=0xFF; //invalid value + u32 trafficIndex; + u32 edca_param; + u64 cur_tx_bytes = 0; + u64 cur_rx_bytes = 0; + u8 bbtchange = _FALSE; + u8 bBiasOnRx = _FALSE; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter); + struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); + struct recv_priv *precvpriv = &(Adapter->recvpriv); + struct registry_priv *pregpriv = &Adapter->registrypriv; + struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + if(pDM_Odm->bLinked != _TRUE) + { + precvpriv->bIsAnyNonBEPkts = _FALSE; + return; + } + + if ((pregpriv->wifi_spec == 1) )//|| (pmlmeinfo->HT_enable == 0)) + { + precvpriv->bIsAnyNonBEPkts = _FALSE; + return; + } + + if(pDM_Odm->pWirelessMode!=NULL) + WirelessMode=*(pDM_Odm->pWirelessMode); + + IOTPeer = pmlmeinfo->assoc_AP_vendor; + + if (IOTPeer >= HT_IOT_PEER_MAX) + { + precvpriv->bIsAnyNonBEPkts = _FALSE; + return; + } + + if( (pDM_Odm->SupportICType == ODM_RTL8192C) || + (pDM_Odm->SupportICType == ODM_RTL8723A) || + (pDM_Odm->SupportICType == ODM_RTL8188E)) + { + if((IOTPeer == HT_IOT_PEER_RALINK)||(IOTPeer == HT_IOT_PEER_ATHEROS)) + bBiasOnRx = _TRUE; + } + + // Check if the status needs to be changed. + if((bbtchange) || (!precvpriv->bIsAnyNonBEPkts) ) + { + cur_tx_bytes = pdvobjpriv->traffic_stat.cur_tx_bytes; + cur_rx_bytes = pdvobjpriv->traffic_stat.cur_rx_bytes; + + //traffic, TX or RX + if(bBiasOnRx) + { + if (cur_tx_bytes > (cur_rx_bytes << 2)) + { // Uplink TP is present. + trafficIndex = UP_LINK; + } + else + { // Balance TP is present. + trafficIndex = DOWN_LINK; + } + } + else + { + if (cur_rx_bytes > (cur_tx_bytes << 2)) + { // Downlink TP is present. + trafficIndex = DOWN_LINK; + } + else + { // Balance TP is present. + trafficIndex = UP_LINK; + } + } + + //if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) + { + if (ICType == ODM_RTL8192D) { + // Single PHY + if (pDM_Odm->RFType == ODM_2T2R) { + EDCA_BE_UL = 0x60a42b; //0x5ea42b; + EDCA_BE_DL = 0x60a42b; //0x5ea42b; + } else { + EDCA_BE_UL = 0x6ea42b; + EDCA_BE_DL = 0x6ea42b; + } + } + else + { + if(pDM_Odm->SupportInterface==ODM_ITRF_PCIE) { + if((ICType==ODM_RTL8192C)&&(pDM_Odm->RFType==ODM_2T2R)) { + EDCA_BE_UL = 0x60a42b; + EDCA_BE_DL = 0x60a42b; + } else { + EDCA_BE_UL = 0x6ea42b; + EDCA_BE_DL = 0x6ea42b; + } + } + } + + //92D txop can't be set to 0x3e for cisco1250 + if((ICType!=ODM_RTL8192D) && (IOTPeer== HT_IOT_PEER_CISCO) &&(WirelessMode==ODM_WM_N24G)) + { + EDCA_BE_DL = edca_setting_DL[IOTPeer]; + EDCA_BE_UL = edca_setting_UL[IOTPeer]; + } + //merge from 92s_92c_merge temp brunch v2445 20120215 + else if((IOTPeer == HT_IOT_PEER_CISCO) &&((WirelessMode==ODM_WM_G)||(WirelessMode==(ODM_WM_B|ODM_WM_G))||(WirelessMode==ODM_WM_A)||(WirelessMode==ODM_WM_B))) + { + EDCA_BE_DL = edca_setting_DL_GMode[IOTPeer]; + } + else if((IOTPeer== HT_IOT_PEER_AIRGO )&& ((WirelessMode==ODM_WM_G)||(WirelessMode==ODM_WM_A))) + { + EDCA_BE_DL = 0xa630; + } + else if(IOTPeer == HT_IOT_PEER_MARVELL) + { + EDCA_BE_DL = edca_setting_DL[IOTPeer]; + EDCA_BE_UL = edca_setting_UL[IOTPeer]; + } + else if(IOTPeer == HT_IOT_PEER_ATHEROS) + { + // Set DL EDCA for Atheros peer to 0x3ea42b. Suggested by SD3 Wilson for ASUS TP issue. + EDCA_BE_DL = edca_setting_DL[IOTPeer]; + } + + if((ICType==ODM_RTL8812)||(ICType==ODM_RTL8821)||(ICType==ODM_RTL8192E)) //add 8812AU/8812AE + { + EDCA_BE_UL = 0x5ea42b; + EDCA_BE_DL = 0x5ea42b; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("8812A: EDCA_BE_UL=0x%x EDCA_BE_DL =0x%x",EDCA_BE_UL,EDCA_BE_DL)); + } + + if (trafficIndex == DOWN_LINK) + edca_param = EDCA_BE_DL; + else + edca_param = EDCA_BE_UL; + + rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param); + + pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex; + } + + pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = _TRUE; + } + else + { + // + // Turn Off EDCA turbo here. + // Restore original EDCA according to the declaration of AP. + // + if(pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) + { + rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE); + pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = _FALSE; + } + } + +} + + +#elif(DM_ODM_SUPPORT_TYPE==ODM_WIN) +VOID +odm_EdcaTurboCheckMP( + IN PVOID pDM_VOID + ) +{ + + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PADAPTER pDefaultAdapter = GetDefaultAdapter(Adapter); + PADAPTER pExtAdapter = GetFirstExtAdapter(Adapter);//NULL; + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + PSTA_QOS pStaQos = Adapter->MgntInfo.pStaQos; + //[Win7 Count Tx/Rx statistic for Extension Port] odm_CheckEdcaTurbo's Adapter is always Default. 2009.08.20, by Bohn + u8Byte Ext_curTxOkCnt = 0; + u8Byte Ext_curRxOkCnt = 0; + //For future Win7 Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn. + u1Byte TwoPortStatus = (u1Byte)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE; + + // Keep past Tx/Rx packet count for RT-to-RT EDCA turbo. + u8Byte curTxOkCnt = 0; + u8Byte curRxOkCnt = 0; + u4Byte EDCA_BE_UL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_UL[pMgntInfo->IOTPeer]; + u4Byte EDCA_BE_DL = 0x5ea42b;//Parameter suggested by Scott //edca_setting_DL[pMgntInfo->IOTPeer]; + u4Byte EDCA_BE = 0x5ea42b; + u1Byte IOTPeer=0; + BOOLEAN *pbIsCurRDLState=NULL; + BOOLEAN bLastIsCurRDLState=FALSE; + BOOLEAN bBiasOnRx=FALSE; + BOOLEAN bEdcaTurboOn=FALSE; + u1Byte TxRate = 0xFF; + u8Byte value64; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("odm_EdcaTurboCheckMP========================>")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BE PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BE_PARAM))); + +////=============================== +////list paramter for different platform +////=============================== + bLastIsCurRDLState=pDM_Odm->DM_EDCA_Table.bIsCurRDLState; + pbIsCurRDLState=&(pDM_Odm->DM_EDCA_Table.bIsCurRDLState); + + //2012/09/14 MH Add + if (pMgntInfo->NumNonBePkt > pMgntInfo->RegEdcaThresh && !Adapter->MgntInfo.bWiFiConfg) + pHalData->bIsAnyNonBEPkts = TRUE; + + pMgntInfo->NumNonBePkt = 0; + + // Caculate TX/RX TP: + //curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - pMgntInfo->lastTxOkCnt; + //curRxOkCnt = Adapter->RxStats.NumRxBytesUnicast - pMgntInfo->lastRxOkCnt; + curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - pDM_Odm->lastTxOkCnt; + curRxOkCnt = Adapter->RxStats.NumRxBytesUnicast - pDM_Odm->lastRxOkCnt; + pDM_Odm->lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast; + pDM_Odm->lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast; + + if(pExtAdapter == NULL) + pExtAdapter = pDefaultAdapter; + + Ext_curTxOkCnt = pExtAdapter->TxStats.NumTxBytesUnicast - pMgntInfo->Ext_lastTxOkCnt; + Ext_curRxOkCnt = pExtAdapter->RxStats.NumRxBytesUnicast - pMgntInfo->Ext_lastRxOkCnt; + GetTwoPortSharedResource(Adapter,TWO_PORT_SHARED_OBJECT__STATUS,NULL,&TwoPortStatus); + //For future Win7 Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn. + if(TwoPortStatus == TWO_PORT_STATUS__EXTENSION_ONLY) + { + curTxOkCnt = Ext_curTxOkCnt ; + curRxOkCnt = Ext_curRxOkCnt ; + } + // + IOTPeer=pMgntInfo->IOTPeer; + bBiasOnRx=(pMgntInfo->IOTAction & HT_IOT_ACT_EDCA_BIAS_ON_RX)?TRUE:FALSE; + bEdcaTurboOn=((!pHalData->bIsAnyNonBEPkts))?TRUE:FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("bIsAnyNonBEPkts : 0x%lx \n",pHalData->bIsAnyNonBEPkts)); + + +////=============================== +////check if edca turbo is disabled +////=============================== + if(odm_IsEdcaTurboDisable(pDM_Odm)) + { + pHalData->bIsAnyNonBEPkts = FALSE; + pMgntInfo->lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast; + pMgntInfo->lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast; + pMgntInfo->Ext_lastTxOkCnt = pExtAdapter->TxStats.NumTxBytesUnicast; + pMgntInfo->Ext_lastRxOkCnt = pExtAdapter->RxStats.NumRxBytesUnicast; + + } + +////=============================== +////remove iot case out +////=============================== + ODM_EdcaParaSelByIot(pDM_Odm, &EDCA_BE_UL, &EDCA_BE_DL); + + +////=============================== +////Check if the status needs to be changed. +////=============================== + if(bEdcaTurboOn) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("bEdcaTurboOn : 0x%x bBiasOnRx : 0x%x\n",bEdcaTurboOn,bBiasOnRx)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("curTxOkCnt : 0x%lx \n",curTxOkCnt)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("curRxOkCnt : 0x%lx \n",curRxOkCnt)); + if(bBiasOnRx) + odm_EdcaChooseTrafficIdx(pDM_Odm,curTxOkCnt, curRxOkCnt, TRUE, pbIsCurRDLState); + else + odm_EdcaChooseTrafficIdx(pDM_Odm,curTxOkCnt, curRxOkCnt, FALSE, pbIsCurRDLState); + +//modify by Guo.Mingzhi 2011-12-29 + EDCA_BE=((*pbIsCurRDLState)==TRUE)?EDCA_BE_DL:EDCA_BE_UL; + if(IS_HARDWARE_TYPE_8821U(Adapter)) + { + if(pMgntInfo->RegTxDutyEnable) + { + //2013.01.23 LukeLee: debug for 8811AU thermal issue (reduce Tx duty cycle) + if(!pMgntInfo->ForcedDataRate) //auto rate + { + if(pDM_Odm->TxRate != 0xFF) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + } + else //force rate + { + TxRate = (u1Byte) pMgntInfo->ForcedDataRate; + } + + value64 = (curRxOkCnt<<2); + if(curTxOkCnt < value64) //Downlink + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); + else //Uplink + { + /*DbgPrint("pRFCalibrateInfo->ThermalValue = 0x%X\n", pRFCalibrateInfo->ThermalValue);*/ + /*if(pRFCalibrateInfo->ThermalValue < pHalData->EEPROMThermalMeter)*/ + if((pDM_Odm->RFCalibrateInfo.ThermalValue < 0x2c) || (*pDM_Odm->pBandType == BAND_ON_2_4G)) + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); + else + { + switch (TxRate) + { + case MGN_VHT1SS_MCS6: + case MGN_VHT1SS_MCS5: + case MGN_MCS6: + case MGN_MCS5: + case MGN_48M: + case MGN_54M: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0x1ea42b); + break; + case MGN_VHT1SS_MCS4: + case MGN_MCS4: + case MGN_36M: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa42b); + break; + case MGN_VHT1SS_MCS3: + case MGN_MCS3: + case MGN_24M: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa47f); + break; + case MGN_VHT1SS_MCS2: + case MGN_MCS2: + case MGN_18M: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa57f); + break; + case MGN_VHT1SS_MCS1: + case MGN_MCS1: + case MGN_9M: + case MGN_12M: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa77f); + break; + case MGN_VHT1SS_MCS0: + case MGN_MCS0: + case MGN_6M: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa87f); + break; + default: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); + break; + } + } + } + } + else + { + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); + } + + } + else if (IS_HARDWARE_TYPE_8812AU(Adapter)){ + if(pMgntInfo->RegTxDutyEnable) + { + //2013.07.26 Wilson: debug for 8812AU thermal issue (reduce Tx duty cycle) + // it;s the same issue as 8811AU + if(!pMgntInfo->ForcedDataRate) //auto rate + { + if(pDM_Odm->TxRate != 0xFF) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + } + else //force rate + { + TxRate = (u1Byte) pMgntInfo->ForcedDataRate; + } + + value64 = (curRxOkCnt<<2); + if(curTxOkCnt < value64) //Downlink + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); + else //Uplink + { + /*DbgPrint("pRFCalibrateInfo->ThermalValue = 0x%X\n", pRFCalibrateInfo->ThermalValue);*/ + /*if(pRFCalibrateInfo->ThermalValue < pHalData->EEPROMThermalMeter)*/ + if((pDM_Odm->RFCalibrateInfo.ThermalValue < 0x2c) || (*pDM_Odm->pBandType == BAND_ON_2_4G)) + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); + else + { + switch (TxRate) + { + case MGN_VHT2SS_MCS9: + case MGN_VHT1SS_MCS9: + case MGN_VHT1SS_MCS8: + case MGN_MCS15: + case MGN_MCS7: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0x1ea44f); + case MGN_VHT2SS_MCS8: + case MGN_VHT1SS_MCS7: + case MGN_MCS14: + case MGN_MCS6: + case MGN_54M: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa44f); + case MGN_VHT2SS_MCS7: + case MGN_VHT2SS_MCS6: + case MGN_VHT1SS_MCS6: + case MGN_VHT1SS_MCS5: + case MGN_MCS13: + case MGN_MCS5: + case MGN_48M: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa630); + break; + case MGN_VHT2SS_MCS5: + case MGN_VHT2SS_MCS4: + case MGN_VHT1SS_MCS4: + case MGN_VHT1SS_MCS3: + case MGN_MCS12: + case MGN_MCS4: + case MGN_MCS3: + case MGN_36M: + case MGN_24M: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa730); + break; + case MGN_VHT2SS_MCS3: + case MGN_VHT2SS_MCS2: + case MGN_VHT2SS_MCS1: + case MGN_VHT1SS_MCS2: + case MGN_VHT1SS_MCS1: + case MGN_MCS11: + case MGN_MCS10: + case MGN_MCS9: + case MGN_MCS2: + case MGN_MCS1: + case MGN_18M: + case MGN_12M: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa830); + break; + case MGN_VHT2SS_MCS0: + case MGN_VHT1SS_MCS0: + case MGN_MCS0: + case MGN_MCS8: + case MGN_9M: + case MGN_6M: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa87f); + break; + default: + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); + break; + } + } + } + } + else + { + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); + } + } + else + ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EDCA Turbo on: EDCA_BE:0x%lx\n",EDCA_BE)); + + pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = TRUE; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EDCA_BE_DL : 0x%lx EDCA_BE_UL : 0x%lx EDCA_BE : 0x%lx \n",EDCA_BE_DL,EDCA_BE_UL,EDCA_BE)); + + } + else + { + // Turn Off EDCA turbo here. + // Restore original EDCA according to the declaration of AP. + if(pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) + { + Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AC_PARAM, GET_WMM_PARAM_ELE_SINGLE_AC_PARAM(pStaQos->WMMParamEle, AC0_BE) ); + + pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Restore EDCA BE: 0x%lx \n",pDM_Odm->WMMEDCA_BE)); + + } + } + +} + + +//check if edca turbo is disabled +BOOLEAN +odm_IsEdcaTurboDisable( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + u4Byte IOTPeer=pMgntInfo->IOTPeer; + + if(pDM_Odm->bBtDisableEdcaTurbo) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("EdcaTurboDisable for BT!!\n")); + return TRUE; + } + + if((!(pDM_Odm->SupportAbility& ODM_MAC_EDCA_TURBO ))|| + (pDM_Odm->bWIFITest)|| + (IOTPeer>= HT_IOT_PEER_MAX)) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("EdcaTurboDisable\n")); + return TRUE; + } + + + // 1. We do not turn on EDCA turbo mode for some AP that has IOT issue + // 2. User may disable EDCA Turbo mode with OID settings. + if(pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("IOTAction:EdcaTurboDisable\n")); + return TRUE; + } + + return FALSE; + + +} + +//add iot case here: for MP/CE +VOID +ODM_EdcaParaSelByIot( + IN PVOID pDM_VOID, + OUT u4Byte *EDCA_BE_UL, + OUT u4Byte *EDCA_BE_DL + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u4Byte IOTPeer=0; + u4Byte ICType=pDM_Odm->SupportICType; + u1Byte WirelessMode=0xFF; //invalid value + u4Byte RFType=pDM_Odm->RFType; + u4Byte IOTPeerSubType = 0; + + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + u1Byte TwoPortStatus = (u1Byte)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE; + + if(pDM_Odm->pWirelessMode!=NULL) + WirelessMode=*(pDM_Odm->pWirelessMode); + +/////////////////////////////////////////////////////////// +////list paramter for different platform + + IOTPeer=pMgntInfo->IOTPeer; + IOTPeerSubType=pMgntInfo->IOTPeerSubtype; + GetTwoPortSharedResource(Adapter,TWO_PORT_SHARED_OBJECT__STATUS,NULL,&TwoPortStatus); + + + if(ICType==ODM_RTL8192D) + { + // Single PHY + if(pDM_Odm->RFType==ODM_2T2R) + { + (*EDCA_BE_UL) = 0x60a42b; //0x5ea42b; + (*EDCA_BE_DL) = 0x60a42b; //0x5ea42b; + + } + else + { + (*EDCA_BE_UL) = 0x6ea42b; + (*EDCA_BE_DL) = 0x6ea42b; + } + + } +////============================ +/// IOT case for MP +////============================ + + else + { + + if(pDM_Odm->SupportInterface==ODM_ITRF_PCIE){ + if((ICType==ODM_RTL8192C)&&(pDM_Odm->RFType==ODM_2T2R)) { + (*EDCA_BE_UL) = 0x60a42b; + (*EDCA_BE_DL) = 0x60a42b; + } + else + { + (*EDCA_BE_UL) = 0x6ea42b; + (*EDCA_BE_DL) = 0x6ea42b; + } + } + } + + if(TwoPortStatus == TWO_PORT_STATUS__EXTENSION_ONLY) + { + (*EDCA_BE_UL) = 0x5ea42b;//Parameter suggested by Scott //edca_setting_UL[ExtAdapter->MgntInfo.IOTPeer]; + (*EDCA_BE_DL) = 0x5ea42b;//Parameter suggested by Scott //edca_setting_DL[ExtAdapter->MgntInfo.IOTPeer]; + } + + #if (INTEL_PROXIMITY_SUPPORT == 1) + if(pMgntInfo->IntelClassModeInfo.bEnableCA == TRUE) + { + (*EDCA_BE_UL) = (*EDCA_BE_DL) = 0xa44f; + } + else + #endif + { + if((pMgntInfo->IOTAction & (HT_IOT_ACT_FORCED_ENABLE_BE_TXOP|HT_IOT_ACT_AMSDU_ENABLE))) + {// To check whether we shall force turn on TXOP configuration. + if(!((*EDCA_BE_UL) & 0xffff0000)) + (*EDCA_BE_UL) |= 0x005e0000; // Force TxOP limit to 0x005e for UL. + if(!((*EDCA_BE_DL) & 0xffff0000)) + (*EDCA_BE_DL) |= 0x005e0000; // Force TxOP limit to 0x005e for DL. + } + + //92D txop can't be set to 0x3e for cisco1250 + if((ICType!=ODM_RTL8192D) && (IOTPeer== HT_IOT_PEER_CISCO) &&(WirelessMode==ODM_WM_N24G)) + { + (*EDCA_BE_DL) = edca_setting_DL[IOTPeer]; + (*EDCA_BE_UL) = edca_setting_UL[IOTPeer]; + } + //merge from 92s_92c_merge temp brunch v2445 20120215 + else if((IOTPeer == HT_IOT_PEER_CISCO) &&((WirelessMode==ODM_WM_G)||(WirelessMode==(ODM_WM_B|ODM_WM_G))||(WirelessMode==ODM_WM_A)||(WirelessMode==ODM_WM_B))) + { + (*EDCA_BE_DL) = edca_setting_DL_GMode[IOTPeer]; + } + else if((IOTPeer== HT_IOT_PEER_AIRGO )&& ((WirelessMode==ODM_WM_G)||(WirelessMode==ODM_WM_A))) + { + (*EDCA_BE_DL) = 0xa630; + } + + else if(IOTPeer == HT_IOT_PEER_MARVELL) + { + (*EDCA_BE_DL) = edca_setting_DL[IOTPeer]; + (*EDCA_BE_UL) = edca_setting_UL[IOTPeer]; + } + else if(IOTPeer == HT_IOT_PEER_ATHEROS && IOTPeerSubType != HT_IOT_PEER_TPLINK_AC1750) + { + // Set DL EDCA for Atheros peer to 0x3ea42b. Suggested by SD3 Wilson for ASUS TP issue. + if(WirelessMode==ODM_WM_G) + (*EDCA_BE_DL) = edca_setting_DL_GMode[IOTPeer]; + else + (*EDCA_BE_DL) = edca_setting_DL[IOTPeer]; + + if(ICType == ODM_RTL8821) + (*EDCA_BE_DL) = 0x5ea630; + + } + } + + if((ICType == ODM_RTL8192D)&&(IOTPeerSubType == HT_IOT_PEER_LINKSYS_E4200_V1)&&((WirelessMode==ODM_WM_N5G))) + { + (*EDCA_BE_DL) = 0x432b; + (*EDCA_BE_UL) = 0x432b; + } + + + + if((ICType==ODM_RTL8812)||(ICType==ODM_RTL8192E)) //add 8812AU/8812AE + { + (*EDCA_BE_UL) = 0x5ea42b; + (*EDCA_BE_DL) = 0x5ea42b; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("8812A: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx\n",(*EDCA_BE_UL),(*EDCA_BE_DL))); + } + + if((ICType==ODM_RTL8814A) && (IOTPeer == HT_IOT_PEER_REALTEK)) /*8814AU and 8814AR*/ + { + (*EDCA_BE_UL) = 0x5ea42b; + (*EDCA_BE_DL) = 0xa42b; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("8814A: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx\n",(*EDCA_BE_UL),(*EDCA_BE_DL))); + } + + + + // Revised for Atheros DIR-655 IOT issue to improve down link TP, added by Roger, 2013.03.22. + if((ICType == ODM_RTL8723A) && (IOTPeerSubType== HT_IOT_PEER_ATHEROS_DIR655) && + (pMgntInfo->dot11CurrentChannelNumber == 6)) + { + (*EDCA_BE_DL) = 0xa92b; + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Special: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx, IOTPeer = %d\n",(*EDCA_BE_UL),(*EDCA_BE_DL), IOTPeer)); + +} + + +VOID +odm_EdcaChooseTrafficIdx( + IN PVOID pDM_VOID, + IN u8Byte cur_tx_bytes, + IN u8Byte cur_rx_bytes, + IN BOOLEAN bBiasOnRx, + OUT BOOLEAN *pbIsCurRDLState + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if(bBiasOnRx) + { + + if(cur_tx_bytes>(cur_rx_bytes*4)) + { + *pbIsCurRDLState=FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Uplink Traffic\n ")); + + } + else + { + *pbIsCurRDLState=TRUE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Balance Traffic\n")); + + } + } + else + { + if(cur_rx_bytes>(cur_tx_bytes*4)) + { + *pbIsCurRDLState=TRUE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Downlink Traffic\n")); + + } + else + { + *pbIsCurRDLState=FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Balance Traffic\n")); + } + } + + return ; +} + +#endif + + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_edcaturbocheck.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_edcaturbocheck.h new file mode 100644 index 000000000..d4cd8d841 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_edcaturbocheck.h @@ -0,0 +1,100 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMEDCATURBOCHECK_H__ +#define __PHYDMEDCATURBOCHECK_H__ + +/*#define EDCATURBO_VERSION "2.1"*/ +#define EDCATURBO_VERSION "2.2" /*2015.01.13*/ + +typedef struct _EDCA_TURBO_ +{ + BOOLEAN bCurrentTurboEDCA; + BOOLEAN bIsCurRDLState; + + #if(DM_ODM_SUPPORT_TYPE == ODM_CE ) + u4Byte prv_traffic_idx; // edca turbo + #endif + +}EDCA_T,*pEDCA_T; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) +static u4Byte edca_setting_UL[HT_IOT_PEER_MAX] = +// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU MARVELL 92U_AP SELF_AP(DownLink/Tx) +{ 0x5e4322, 0xa44f, 0x5e4322, 0x5ea32b, 0x5ea422, 0x5ea322, 0x3ea430, 0x5ea42b, 0x5ea44f, 0x5e4322, 0x5e4322}; + + +static u4Byte edca_setting_DL[HT_IOT_PEER_MAX] = +// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU, MARVELL 92U_AP SELF_AP(UpLink/Rx) +{ 0xa44f, 0x5ea44f, 0x5e4322, 0x5ea42b, 0xa44f, 0xa630, 0x5ea630, 0x5ea42b, 0xa44f, 0xa42b, 0xa42b}; + +static u4Byte edca_setting_DL_GMode[HT_IOT_PEER_MAX] = +// UNKNOWN REALTEK_90 REALTEK_92SE BROADCOM RALINK ATHEROS CISCO MERU, MARVELL 92U_AP SELF_AP +{ 0x4322, 0xa44f, 0x5e4322, 0xa42b, 0x5e4322, 0x4322, 0xa42b, 0x5ea42b, 0xa44f, 0x5e4322, 0x5ea42b}; + +#endif + + + +VOID +odm_EdcaTurboCheck( + IN PVOID pDM_VOID + ); +VOID +ODM_EdcaTurboInit( + IN PVOID pDM_VOID +); + +#if(DM_ODM_SUPPORT_TYPE==ODM_WIN) +VOID +odm_EdcaTurboCheckMP( + IN PVOID pDM_VOID + ); + +//check if edca turbo is disabled +BOOLEAN +odm_IsEdcaTurboDisable( + IN PVOID pDM_VOID +); +//choose edca paramter for special IOT case +VOID +ODM_EdcaParaSelByIot( + IN PVOID pDM_VOID, + OUT u4Byte *EDCA_BE_UL, + OUT u4Byte *EDCA_BE_DL + ); +//check if it is UL or DL +VOID +odm_EdcaChooseTrafficIdx( + IN PVOID pDM_VOID, + IN u8Byte cur_tx_bytes, + IN u8Byte cur_rx_bytes, + IN BOOLEAN bBiasOnRx, + OUT BOOLEAN *pbIsCurRDLState + ); + +#elif (DM_ODM_SUPPORT_TYPE==ODM_CE) +VOID +odm_EdcaTurboCheckCE( + IN PVOID pDM_VOID + ); +#endif + +#endif diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_features.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_features.h new file mode 100644 index 000000000..f31c8161c --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_features.h @@ -0,0 +1,115 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDM_FEATURES_H__ +#define __PHYDM_FEATURES + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + /*Antenna Diversity*/ + #define CONFIG_PHYDM_ANTENNA_DIVERSITY + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + + #if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) + #define CONFIG_S0S1_SW_ANTENNA_DIVERSITY + #endif + + #if (RTL8821A_SUPPORT == 1) + /*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/ + #endif + #endif + + /*#define CONFIG_PATH_DIVERSITY*/ + /*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ + #define CONFIG_ANT_DETECTION + #define CONFIG_RA_DBG_CMD + +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + + /* [ Configure RA Debug H2C CMD ]*/ + #define CONFIG_RA_DBG_CMD + + /*#define CONFIG_PATH_DIVERSITY*/ + /*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ + #define CONFIG_RA_DYNAMIC_RATE_ID + + /* [ Configure Antenna Diversity ] */ + #if defined(CONFIG_RTL_8881A_ANT_SWITCH) || defined(CONFIG_SLOT_0_ANT_SWITCH) || defined(CONFIG_SLOT_1_ANT_SWITCH) + #define CONFIG_PHYDM_ANTENNA_DIVERSITY + #define ODM_EVM_ENHANCE_ANTDIV + + /*----------*/ + + #if (!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) && !defined(CONFIG_2G_CGCS_RX_DIVERSITY) && !defined(CONFIG_2G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY)) + #define CONFIG_NO_2G_DIVERSITY + #endif + + #ifdef CONFIG_NO_5G_DIVERSITY_8881A + #define CONFIG_NO_5G_DIVERSITY + #elif defined(CONFIG_5G_CGCS_RX_DIVERSITY_8881A) + #define CONFIG_5G_CGCS_RX_DIVERSITY + #elif defined(CONFIG_5G_CG_TRX_DIVERSITY_8881A) + #define CONFIG_5G_CG_TRX_DIVERSITY + #elif defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A) + #define CONFIG_2G5G_CG_TRX_DIVERSITY + #endif + #if (!defined(CONFIG_NO_5G_DIVERSITY) && !defined(CONFIG_5G_CGCS_RX_DIVERSITY) && !defined(CONFIG_5G_CG_TRX_DIVERSITY) && !defined(CONFIG_2G5G_CG_TRX_DIVERSITY) && !defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) + #define CONFIG_NO_5G_DIVERSITY + #endif + /*----------*/ + #if (defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY)) + #define CONFIG_NOT_SUPPORT_ANTDIV + #elif (!defined(CONFIG_NO_2G_DIVERSITY) && defined(CONFIG_NO_5G_DIVERSITY)) + #define CONFIG_2G_SUPPORT_ANTDIV + #elif (defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) + #define CONFIG_5G_SUPPORT_ANTDIV + #elif ((!defined(CONFIG_NO_2G_DIVERSITY) && !defined(CONFIG_NO_5G_DIVERSITY)) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY)) + #define CONFIG_2G5G_SUPPORT_ANTDIV + #endif + /*----------*/ + #endif + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + + /*Antenna Diversity*/ + #ifdef CONFIG_ANTENNA_DIVERSITY + #define CONFIG_PHYDM_ANTENNA_DIVERSITY + + #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY + + #if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) + #define CONFIG_S0S1_SW_ANTENNA_DIVERSITY + #endif + + #if (RTL8821A_SUPPORT == 1) + /*#define CONFIG_HL_SMART_ANTENNA_TYPE1*/ + #endif + #endif + #endif + + /*#define CONFIG_RA_DBG_CMD*/ + /*#define CONFIG_ANT_DETECTION*/ + /*#define CONFIG_PATH_DIVERSITY*/ + /*#define CONFIG_RA_DYNAMIC_RTY_LIMIT*/ + +#endif + + +#endif diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_hwconfig.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_hwconfig.c new file mode 100644 index 000000000..22601ec50 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_hwconfig.c @@ -0,0 +1,3149 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#define READ_AND_CONFIG_MP(ic, txt) (ODM_ReadAndConfig_MP_##ic##txt(pDM_Odm)) +#define READ_AND_CONFIG_TC(ic, txt) (ODM_ReadAndConfig_TC_##ic##txt(pDM_Odm)) + + +#if (PHYDM_TESTCHIP_SUPPORT == 1) +#define READ_AND_CONFIG(ic, txt) do {\ + if (pDM_Odm->bIsMPChip)\ + READ_AND_CONFIG_MP(ic,txt);\ + else\ + READ_AND_CONFIG_TC(ic,txt);\ + } while(0) +#else + #define READ_AND_CONFIG READ_AND_CONFIG_MP +#endif + +#define GET_VERSION_MP(ic, txt) (ODM_GetVersion_MP_##ic##txt()) +#define GET_VERSION_TC(ic, txt) (ODM_GetVersion_TC_##ic##txt()) +#define GET_VERSION(ic, txt) (pDM_Odm->bIsMPChip?GET_VERSION_MP(ic,txt):GET_VERSION_TC(ic,txt)) + +u1Byte +odm_QueryRxPwrPercentage( + IN s1Byte AntPower + ) +{ + if ((AntPower <= -100) || (AntPower >= 20)) + { + return 0; + } + else if (AntPower >= 0) + { + return 100; + } + else + { + return (100+AntPower); + } + +} + + +// +// 2012/01/12 MH MOve some signal strength smooth method to MP HAL layer. +// IF other SW team do not support the feature, remove this section.?? +// +s4Byte +odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Lenovo( + IN OUT PDM_ODM_T pDM_Odm, + s4Byte CurrSig +) +{ + s4Byte RetSig = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + //if(pDM_Odm->SupportInterface == ODM_ITRF_PCIE) + { + // Step 1. Scale mapping. + // 20100611 Joseph: Re-tunning RSSI presentation for Lenovo. + // 20100426 Joseph: Modify Signal strength mapping. + // This modification makes the RSSI indication similar to Intel solution. + // 20100414 Joseph: Tunning RSSI for Lenovo according to RTL8191SE. + if(CurrSig >= 54 && CurrSig <= 100) + { + RetSig = 100; + } + else if(CurrSig>=42 && CurrSig <= 53 ) + { + RetSig = 95; + } + else if(CurrSig>=36 && CurrSig <= 41 ) + { + RetSig = 74 + ((CurrSig - 36) *20)/6; + } + else if(CurrSig>=33 && CurrSig <= 35 ) + { + RetSig = 65 + ((CurrSig - 33) *8)/2; + } + else if(CurrSig>=18 && CurrSig <= 32 ) + { + RetSig = 62 + ((CurrSig - 18) *2)/15; + } + else if(CurrSig>=15 && CurrSig <= 17 ) + { + RetSig = 33 + ((CurrSig - 15) *28)/2; + } + else if(CurrSig>=10 && CurrSig <= 14 ) + { + RetSig = 39; + } + else if(CurrSig>=8 && CurrSig <= 9 ) + { + RetSig = 33; + } + else if(CurrSig <= 8 ) + { + RetSig = 19; + } + } +#endif //ENDIF (DM_ODM_SUPPORT_TYPE == ODM_WIN) + return RetSig; +} + +s4Byte +odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Netcore( + IN OUT PDM_ODM_T pDM_Odm, + s4Byte CurrSig +) +{ + s4Byte RetSig = 0; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + //if(pDM_Odm->SupportInterface == ODM_ITRF_USB) + { + // Netcore request this modification because 2009.04.13 SU driver use it. + if(CurrSig >= 31 && CurrSig <= 100) + { + RetSig = 100; + } + else if(CurrSig >= 21 && CurrSig <= 30) + { + RetSig = 90 + ((CurrSig - 20) / 1); + } + else if(CurrSig >= 11 && CurrSig <= 20) + { + RetSig = 80 + ((CurrSig - 10) / 1); + } + else if(CurrSig >= 7 && CurrSig <= 10) + { + RetSig = 69 + (CurrSig - 7); + } + else if(CurrSig == 6) + { + RetSig = 54; + } + else if(CurrSig == 5) + { + RetSig = 45; + } + else if(CurrSig == 4) + { + RetSig = 36; + } + else if(CurrSig == 3) + { + RetSig = 27; + } + else if(CurrSig == 2) + { + RetSig = 18; + } + else if(CurrSig == 1) + { + RetSig = 9; + } + else + { + RetSig = CurrSig; + } + } +#endif //ENDIF (DM_ODM_SUPPORT_TYPE == ODM_WIN) + return RetSig; +} + + +s4Byte +odm_SignalScaleMapping_92CSeries( + IN OUT PDM_ODM_T pDM_Odm, + IN s4Byte CurrSig +) +{ + s4Byte RetSig = 0; +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + if(pDM_Odm->SupportInterface == ODM_ITRF_PCIE) + { + // Step 1. Scale mapping. + if(CurrSig >= 61 && CurrSig <= 100) + { + RetSig = 90 + ((CurrSig - 60) / 4); + } + else if(CurrSig >= 41 && CurrSig <= 60) + { + RetSig = 78 + ((CurrSig - 40) / 2); + } + else if(CurrSig >= 31 && CurrSig <= 40) + { + RetSig = 66 + (CurrSig - 30); + } + else if(CurrSig >= 21 && CurrSig <= 30) + { + RetSig = 54 + (CurrSig - 20); + } + else if(CurrSig >= 5 && CurrSig <= 20) + { + RetSig = 42 + (((CurrSig - 5) * 2) / 3); + } + else if(CurrSig == 4) + { + RetSig = 36; + } + else if(CurrSig == 3) + { + RetSig = 27; + } + else if(CurrSig == 2) + { + RetSig = 18; + } + else if(CurrSig == 1) + { + RetSig = 9; + } + else + { + RetSig = CurrSig; + } + } +#endif + +#if ((DEV_BUS_TYPE == RT_USB_INTERFACE) ||(DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + if((pDM_Odm->SupportInterface == ODM_ITRF_USB) || (pDM_Odm->SupportInterface == ODM_ITRF_SDIO)) + { + if(CurrSig >= 51 && CurrSig <= 100) + { + RetSig = 100; + } + else if(CurrSig >= 41 && CurrSig <= 50) + { + RetSig = 80 + ((CurrSig - 40)*2); + } + else if(CurrSig >= 31 && CurrSig <= 40) + { + RetSig = 66 + (CurrSig - 30); + } + else if(CurrSig >= 21 && CurrSig <= 30) + { + RetSig = 54 + (CurrSig - 20); + } + else if(CurrSig >= 10 && CurrSig <= 20) + { + RetSig = 42 + (((CurrSig - 10) * 2) / 3); + } + else if(CurrSig >= 5 && CurrSig <= 9) + { + RetSig = 22 + (((CurrSig - 5) * 3) / 2); + } + else if(CurrSig >= 1 && CurrSig <= 4) + { + RetSig = 6 + (((CurrSig - 1) * 3) / 2); + } + else + { + RetSig = CurrSig; + } + } + +#endif + return RetSig; +} +s4Byte +odm_SignalScaleMapping( + IN OUT PDM_ODM_T pDM_Odm, + IN s4Byte CurrSig +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if( (pDM_Odm->SupportPlatform == ODM_WIN) && + (pDM_Odm->SupportInterface != ODM_ITRF_PCIE) && //USB & SDIO + (pDM_Odm->PatchID==10))//pMgntInfo->CustomerID == RT_CID_819x_Netcore + { + return odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Netcore(pDM_Odm,CurrSig); + } + else if( (pDM_Odm->SupportPlatform == ODM_WIN) && + (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) && + (pDM_Odm->PatchID==19))//pMgntInfo->CustomerID == RT_CID_819x_Lenovo) + { + return odm_SignalScaleMapping_92CSeries_patch_RT_CID_819x_Lenovo(pDM_Odm, CurrSig); + }else +#endif + { + return odm_SignalScaleMapping_92CSeries(pDM_Odm,CurrSig); + } + +} + + + +static u1Byte odm_SQ_process_patch_RT_CID_819x_Lenovo( + IN PDM_ODM_T pDM_Odm, + IN u1Byte isCCKrate, + IN u1Byte PWDB_ALL, + IN u1Byte path, + IN u1Byte RSSI +) +{ + u1Byte SQ = 0; +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + + if(isCCKrate){ + + if(IS_HARDWARE_TYPE_8723AE(pDM_Odm->Adapter)) + { + + // + // Expected signal strength and bars indication at Lenovo lab. 2013.04.11 + // 802.11n, 802.11b, 802.11g only at channel 6 + // + // Attenuation (dB) OS Signal Bars RSSI by Xirrus (dBm) + // 50 5 -52 + // 55 5 -54 + // 60 5 -55 + // 65 5 -59 + // 70 5 -63 + // 75 5 -66 + // 80 4 -72 + // 85 3 -75 + // 90 3 -80 + // 95 2 -85 + // 100 1 -89 + // 102 1 -90 + // 104 1 -91 + // + RT_TRACE(COMP_DBG, DBG_WARNING, ("odm_SQ_process_patch_RT_CID_819x_Lenovo\n")); + +#if OS_WIN_FROM_WIN8(OS_VERSION) + if(PWDB_ALL >= 50) + SQ = 100; + else if(PWDB_ALL >= 23 && PWDB_ALL < 50) + SQ = 80; + else if(PWDB_ALL >= 18 && PWDB_ALL < 23) + SQ = 60; + else if(PWDB_ALL >= 8 && PWDB_ALL < 18) + SQ = 40; + else + SQ = 10; +#else + if(PWDB_ALL >= 34) + SQ = 100; + else if(PWDB_ALL >= 23 && PWDB_ALL < 34) + SQ = 80; + else if(PWDB_ALL >= 18 && PWDB_ALL < 23) + SQ = 60; + else if(PWDB_ALL >= 8 && PWDB_ALL < 18) + SQ = 40; + else + SQ = 10; + + if(PWDB_ALL == 0)// Abnormal case, do not indicate the value above 20 on Win7 + SQ = 20; +#endif + + } + else if(IS_HARDWARE_TYPE_8192E(pDM_Odm->Adapter)){ + + // + // Expected signal strength and bars indication at Lenovo lab. 2013.04.11 + // 802.11n, 802.11b, 802.11g only at channel 6 + // + // Attenuation (dB) OS Signal Bars RSSI by Xirrus (dBm) + // 50 5 -49 + // 55 5 -49 + // 60 5 -50 + // 65 5 -51 + // 70 5 -52 + // 75 5 -54 + // 80 5 -55 + // 85 4 -60 + // 90 3 -63 + // 95 3 -65 + // 100 2 -67 + // 102 2 -67 + // 104 1 -70 + // + + if(PWDB_ALL >= 50) + SQ = 100; + else if(PWDB_ALL >= 35 && PWDB_ALL < 50) + SQ = 80; + else if(PWDB_ALL >= 31 && PWDB_ALL < 35) + SQ = 60; + else if(PWDB_ALL >= 22 && PWDB_ALL < 31) + SQ = 40; + else if(PWDB_ALL >= 18 && PWDB_ALL < 22) + SQ = 20; + else + SQ = 10; + } else { + if (PWDB_ALL >= 50) + SQ = 100; + else if (PWDB_ALL >= 35 && PWDB_ALL < 50) + SQ = 80; + else if (PWDB_ALL >= 22 && PWDB_ALL < 35) + SQ = 60; + else if (PWDB_ALL >= 18 && PWDB_ALL < 22) + SQ = 40; + else + SQ = 10; + } + + } + else + {//OFDM rate + + if(IS_HARDWARE_TYPE_8723AE(pDM_Odm->Adapter) || + IS_HARDWARE_TYPE_8192E(pDM_Odm->Adapter)) + { + if(RSSI >= 45) + SQ = 100; + else if(RSSI >= 22 && RSSI < 45) + SQ = 80; + else if(RSSI >= 18 && RSSI < 22) + SQ = 40; + else + SQ = 20; + } else { + if(RSSI >= 45) + SQ = 100; + else if(RSSI >= 22 && RSSI < 45) + SQ = 80; + else if(RSSI >= 18 && RSSI < 22) + SQ = 40; + else + SQ = 20; + } + } + + RT_TRACE(COMP_DBG, DBG_TRACE, ("isCCKrate(%#d), PWDB_ALL(%#d), RSSI(%#d), SQ(%#d)\n", isCCKrate, PWDB_ALL, RSSI, SQ)); + +#endif + return SQ; +} + +static u1Byte odm_SQ_process_patch_RT_CID_819x_Acer( + IN PDM_ODM_T pDM_Odm, + IN u1Byte isCCKrate, + IN u1Byte PWDB_ALL, + IN u1Byte path, + IN u1Byte RSSI +) +{ + u1Byte SQ = 0; + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + + if(isCCKrate){ + + RT_TRACE(COMP_DBG, DBG_WARNING, ("odm_SQ_process_patch_RT_Acer\n")); + +#if OS_WIN_FROM_WIN8(OS_VERSION) + + if(PWDB_ALL >= 50) + SQ = 100; + else if(PWDB_ALL >= 35 && PWDB_ALL < 50) + SQ = 80; + else if(PWDB_ALL >= 30 && PWDB_ALL < 35) + SQ = 60; + else if(PWDB_ALL >= 25 && PWDB_ALL < 30) + SQ = 40; + else if(PWDB_ALL >= 20 && PWDB_ALL < 25) + SQ = 20; + else + SQ = 10; +#else + if(PWDB_ALL >= 50) + SQ = 100; + else if(PWDB_ALL >= 35 && PWDB_ALL < 50) + SQ = 80; + else if(PWDB_ALL >= 30 && PWDB_ALL < 35) + SQ = 60; + else if(PWDB_ALL >= 25 && PWDB_ALL < 30) + SQ = 40; + else if(PWDB_ALL >= 20 && PWDB_ALL < 25) + SQ = 20; + else + SQ = 10; + + if(PWDB_ALL == 0)// Abnormal case, do not indicate the value above 20 on Win7 + SQ = 20; +#endif + + + + } + else + {//OFDM rate + + if(IS_HARDWARE_TYPE_8723AE(pDM_Odm->Adapter) || + IS_HARDWARE_TYPE_8192E(pDM_Odm->Adapter)) + { + if(RSSI >= 45) + SQ = 100; + else if(RSSI >= 22 && RSSI < 45) + SQ = 80; + else if(RSSI >= 18 && RSSI < 22) + SQ = 40; + else + SQ = 20; + } + else + { + if(RSSI >= 35) + SQ = 100; + else if(RSSI >= 30 && RSSI < 35) + SQ = 80; + else if(RSSI >= 25 && RSSI < 30) + SQ = 40; + else + SQ = 20; + } + } + + RT_TRACE(COMP_DBG, DBG_LOUD, ("isCCKrate(%#d), PWDB_ALL(%#d), RSSI(%#d), SQ(%#d)\n", isCCKrate, PWDB_ALL, RSSI, SQ)); + +#endif + return SQ; +} + +static u1Byte +odm_EVMdbToPercentage( + IN s1Byte Value + ) +{ + // + // -33dB~0dB to 0%~99% + // + s1Byte ret_val; + + ret_val = Value; + ret_val /= 2; + + /*DbgPrint("Value=%d\n", Value);*/ + /*ODM_RT_DISP(FRX, RX_PHY_SQ, ("EVMdbToPercentage92C Value=%d / %x\n", ret_val, ret_val));*/ +#ifdef ODM_EVM_ENHANCE_ANTDIV + if (ret_val >= 0) + ret_val = 0; + + if (ret_val <= -40) + ret_val = -40; + + ret_val = 0 - ret_val; + ret_val *= 3; +#else + if (ret_val >= 0) + ret_val = 0; + + if (ret_val <= -33) + ret_val = -33; + + ret_val = 0 - ret_val; + ret_val *= 3; + + if (ret_val == 99) + ret_val = 100; +#endif + + return (u1Byte)ret_val; +} + +static u1Byte +odm_EVMdbm_JaguarSeries( + IN s1Byte Value + ) +{ + s1Byte ret_val = Value; + + // -33dB~0dB to 33dB ~ 0dB + if(ret_val == -128) + ret_val = 127; + else if (ret_val < 0) + ret_val = 0 - ret_val; + + ret_val = ret_val >> 1; + return (u1Byte)ret_val; +} + +static s2Byte +odm_Cfo( + IN s1Byte Value +) +{ + s2Byte ret_val; + + if (Value < 0) + { + ret_val = 0 - Value; + ret_val = (ret_val << 1) + (ret_val >> 1) ; // *2.5~=312.5/2^7 + ret_val = ret_val | BIT12; // set bit12 as 1 for negative cfo + } + else + { + ret_val = Value; + ret_val = (ret_val << 1) + (ret_val>>1) ; // *2.5~=312.5/2^7 + } + return ret_val; +} + +#if(ODM_IC_11N_SERIES_SUPPORT == 1) + +s1Byte +odm_CCKRSSI_8703B( + IN u2Byte LNA_idx, + IN u1Byte VGA_idx + ) +{ + s1Byte rx_pwr_all = 0x00; + + switch (LNA_idx) { + case 0xf: + rx_pwr_all = -48 - (2 * VGA_idx); + break; + case 0xb: + rx_pwr_all = -42 - (2 * VGA_idx); /*TBD*/ + break; + case 0xa: + rx_pwr_all = -36 - (2 * VGA_idx); + break; + case 8: + rx_pwr_all = -32 - (2 * VGA_idx); + break; + case 7: + rx_pwr_all = -28 - (2 * VGA_idx); /*TBD*/ + break; + case 4: + rx_pwr_all = -16 - (2 * VGA_idx); + break; + case 0: + rx_pwr_all = -2 - (2 * VGA_idx); + break; + default: + /*rx_pwr_all = -53+(2*(31-VGA_idx));*/ + /*DbgPrint("wrong LNA index\n");*/ + break; + + } + return rx_pwr_all; +} + +VOID +odm_RxPhyStatus92CSeries_Parsing( + IN OUT PDM_ODM_T pDM_Odm, + OUT PODM_PHY_INFO_T pPhyInfo, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo + ) +{ + SWAT_T *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + u1Byte i, Max_spatial_stream; + s1Byte rx_pwr[4], rx_pwr_all=0; + u1Byte EVM, PWDB_ALL = 0, PWDB_ALL_BT; + u1Byte RSSI, total_rssi=0; + BOOLEAN isCCKrate=FALSE; + u1Byte rf_rx_num = 0; + u1Byte cck_highpwr = 0; + u1Byte LNA_idx = 0; + u1Byte VGA_idx = 0; + PPHY_STATUS_RPT_8192CD_T pPhyStaRpt = (PPHY_STATUS_RPT_8192CD_T)pPhyStatus; + + isCCKrate = (pPktinfo->DataRate <= ODM_RATE11M) ? TRUE : FALSE; + pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = -1; + pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1; + + + if(isCCKrate) + { + u1Byte report; + u1Byte cck_agc_rpt; + + pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK++; + // + // (1)Hardware does not provide RSSI for CCK + // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) + // + + //if(pHalData->eRFPowerState == eRfOn) + cck_highpwr = pDM_Odm->bCckHighPower; + //else + // cck_highpwr = FALSE; + + cck_agc_rpt = pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a ; + + //2011.11.28 LukeLee: 88E use different LNA & VGA gain table + //The RSSI formula should be modified according to the gain table + //In 88E, cck_highpwr is always set to 1 + if (pDM_Odm->SupportICType & (ODM_RTL8703B)) { + + #if (RTL8703B_SUPPORT == 1) + if (pDM_Odm->cck_agc_report_type == 1) { /*4 bit LNA*/ + + u1Byte cck_agc_rpt_b = (pPhyStaRpt->cck_rpt_b_ofdm_cfosho_b & BIT7) ? 1 : 0; + + LNA_idx = (cck_agc_rpt_b << 3) | ((cck_agc_rpt & 0xE0) >> 5); + VGA_idx = (cck_agc_rpt & 0x1F); + + rx_pwr_all = odm_CCKRSSI_8703B(LNA_idx, VGA_idx); + PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); + if (PWDB_ALL > 100) + PWDB_ALL = 100; + + } + #endif + } else if (pDM_Odm->SupportICType & (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8188F)) /*3 bit LNA*/ + { + LNA_idx = ((cck_agc_rpt & 0xE0) >>5); + VGA_idx = (cck_agc_rpt & 0x1F); + if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8192E)) + { + if(pDM_Odm->cck_agc_report_type == 0 && (pDM_Odm->SupportICType & ODM_RTL8192E) ) + { + switch(LNA_idx) + { + case 7: + rx_pwr_all = -45 - 2*(VGA_idx); + break; + case 6: + rx_pwr_all = -43 -2*(VGA_idx); + break; + case 5: + rx_pwr_all = -27 - 2*(VGA_idx); + break; + case 4: + rx_pwr_all = -21 - 2*(VGA_idx); + break; + case 3: + rx_pwr_all = -18 - 2*(VGA_idx); + break; + case 2: + rx_pwr_all = -6 - 2*(VGA_idx); + break; + case 1: + rx_pwr_all = 9 -2*(VGA_idx); + break; + case 0: + rx_pwr_all = 15 -2*(VGA_idx); + break; + default: + + break; + } + + if(pDM_Odm->BoardType & ODM_BOARD_EXT_LNA) + { + rx_pwr_all -= pDM_Odm->ExtLNAGain; + } + + PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); + } + else + { + switch(LNA_idx) + { + case 7: + if(VGA_idx <= 27) + rx_pwr_all = -100 + 2*(27-VGA_idx); //VGA_idx = 27~2 + else + rx_pwr_all = -100; + break; + case 6: + rx_pwr_all = -48 + 2*(2-VGA_idx); //VGA_idx = 2~0 + break; + case 5: + rx_pwr_all = -42 + 2*(7-VGA_idx); //VGA_idx = 7~5 + break; + case 4: + rx_pwr_all = -36 + 2*(7-VGA_idx); //VGA_idx = 7~4 + break; + case 3: + //rx_pwr_all = -28 + 2*(7-VGA_idx); //VGA_idx = 7~0 + rx_pwr_all = -24 + 2*(7-VGA_idx); //VGA_idx = 7~0 + break; + case 2: + if(cck_highpwr) + rx_pwr_all = -12 + 2*(5-VGA_idx); //VGA_idx = 5~0 + else + rx_pwr_all = -6+ 2*(5-VGA_idx); + break; + case 1: + rx_pwr_all = 8-2*VGA_idx; + break; + case 0: + rx_pwr_all = 14-2*VGA_idx; + break; + default: + //DbgPrint("CCK Exception default\n"); + break; + } + rx_pwr_all += 8; + + //2012.10.08 LukeLee: Modify for 92E CCK RSSI + if(pDM_Odm->SupportICType == ODM_RTL8192E) + rx_pwr_all += 8; + + PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); + if(cck_highpwr == FALSE) + { + if(PWDB_ALL >= 80) + PWDB_ALL = ((PWDB_ALL-80)<<1)+((PWDB_ALL-80)>>1)+80; + else if((PWDB_ALL <= 78) && (PWDB_ALL >= 20)) + PWDB_ALL += 3; + if(PWDB_ALL>100) + PWDB_ALL = 100; + } + } + } + else if(pDM_Odm->SupportICType & (ODM_RTL8723B)) + { +#if (RTL8723B_SUPPORT == 1) + rx_pwr_all = odm_CCKRSSI_8723B(LNA_idx,VGA_idx); + PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); + if(PWDB_ALL>100) + PWDB_ALL = 100; +#endif + } else if (pDM_Odm->SupportICType & (ODM_RTL8188F)) { +#if (RTL8188F_SUPPORT == 1) + rx_pwr_all = odm_CCKRSSI_8188F(LNA_idx, VGA_idx); + PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); + if (PWDB_ALL > 100) + PWDB_ALL = 100; +#endif + } + } + else + { + if(!cck_highpwr) + { + report =( cck_agc_rpt & 0xc0 )>>6; + switch(report) + { + // 03312009 modified by cosa + // Modify the RF RNA gain value to -40, -20, -2, 14 by Jenyu's suggestion + // Note: different RF with the different RNA gain. + case 0x3: + rx_pwr_all = -46 - (cck_agc_rpt & 0x3e); + break; + case 0x2: + rx_pwr_all = -26 - (cck_agc_rpt & 0x3e); + break; + case 0x1: + rx_pwr_all = -12 - (cck_agc_rpt & 0x3e); + break; + case 0x0: + rx_pwr_all = 16 - (cck_agc_rpt & 0x3e); + break; + } + } + else + { + //report = pDrvInfo->cfosho[0] & 0x60; + //report = pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a& 0x60; + + report = (cck_agc_rpt & 0x60)>>5; + switch(report) + { + case 0x3: + rx_pwr_all = -46 - ((cck_agc_rpt & 0x1f)<<1) ; + break; + case 0x2: + rx_pwr_all = -26 - ((cck_agc_rpt & 0x1f)<<1); + break; + case 0x1: + rx_pwr_all = -12 - ((cck_agc_rpt & 0x1f)<<1) ; + break; + case 0x0: + rx_pwr_all = 16 - ((cck_agc_rpt & 0x1f)<<1) ; + break; + } + } + + PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); + + //Modification for ext-LNA board + if(pDM_Odm->BoardType & (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_PA)) + { + if((cck_agc_rpt>>7) == 0){ + PWDB_ALL = (PWDB_ALL>94)?100:(PWDB_ALL +6); + } + else + { + if(PWDB_ALL > 38) + PWDB_ALL -= 16; + else + PWDB_ALL = (PWDB_ALL<=16)?(PWDB_ALL>>2):(PWDB_ALL -12); + } + + //CCK modification + if(PWDB_ALL > 25 && PWDB_ALL <= 60) + PWDB_ALL += 6; + //else if (PWDB_ALL <= 25) + // PWDB_ALL += 8; + } + else//Modification for int-LNA board + { + if(PWDB_ALL > 99) + PWDB_ALL -= 8; + else if(PWDB_ALL > 50 && PWDB_ALL <= 68) + PWDB_ALL += 4; + } + } + + pDM_Odm->cck_lna_idx = LNA_idx; + pDM_Odm->cck_vga_idx = VGA_idx; + pPhyInfo->RxPWDBAll = PWDB_ALL; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + pPhyInfo->BTRxRSSIPercentage = PWDB_ALL; + pPhyInfo->RecvSignalPower = rx_pwr_all; +#endif + // + // (3) Get Signal Quality (EVM) + // + //if(pPktinfo->bPacketMatchBSSID) + { + u1Byte SQ,SQ_rpt; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if((pDM_Odm->SupportPlatform == ODM_WIN) && + (pDM_Odm->PatchID==RT_CID_819x_Lenovo)){ + SQ = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm,isCCKrate,PWDB_ALL,0,0); + }else if((pDM_Odm->SupportPlatform == ODM_WIN) && + (pDM_Odm->PatchID==RT_CID_819x_Acer)) + { + SQ = odm_SQ_process_patch_RT_CID_819x_Acer(pDM_Odm,isCCKrate,PWDB_ALL,0,0); + }else +#endif + if(pPhyInfo->RxPWDBAll > 40 && !pDM_Odm->bInHctTest){ + SQ = 100; + } + else{ + SQ_rpt = pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all; + + if(SQ_rpt > 64) + SQ = 0; + else if (SQ_rpt < 20) + SQ = 100; + else + SQ = ((64-SQ_rpt) * 100) / 44; + + } + + //DbgPrint("cck SQ = %d\n", SQ); + pPhyInfo->SignalQuality = SQ; + pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = SQ; + pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1; + } + + for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++) { + if (i == 0) + pPhyInfo->RxMIMOSignalStrength[0] = PWDB_ALL; + else + pPhyInfo->RxMIMOSignalStrength[1] = 0; + } + } + else //2 is OFDM rate + { + pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM++; + + // + // (1)Get RSSI for HT rate + // + + for(i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX; i++) + { + // 2008/01/30 MH we will judge RF RX path now. + if (pDM_Odm->RFPathRxEnable & BIT(i)) + rf_rx_num++; + //else + //continue; + + rx_pwr[i] = ((pPhyStaRpt->path_agc[i].gain& 0x3F)*2) - 110; + pDM_Odm->ofdm_agc_idx[i] = (pPhyStaRpt->path_agc[i].gain & 0x3F); + + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + pPhyInfo->RxPwr[i] = rx_pwr[i]; + #endif + + /* Translate DBM to percentage. */ + RSSI = odm_QueryRxPwrPercentage(rx_pwr[i]); + total_rssi += RSSI; + //RT_DISP(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI)); + + + if(pDM_Odm->SupportICType&ODM_RTL8192C) + { + //Modification for ext-LNA board + if(pDM_Odm->BoardType & (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_PA)) + { + if((pPhyStaRpt->path_agc[i].trsw) == 1) + RSSI = (RSSI>94)?100:(RSSI +6); + else + RSSI = (RSSI<=16)?(RSSI>>3):(RSSI -16); + + if((RSSI <= 34) && (RSSI >=4)) + RSSI -= 4; + } + } + + pPhyInfo->RxMIMOSignalStrength[i] =(u1Byte) RSSI; + + #if (DM_ODM_SUPPORT_TYPE & (/*ODM_WIN|*/ODM_CE|ODM_AP)) + //Get Rx snr value in DB + pPhyInfo->RxSNR[i] = pDM_Odm->PhyDbgInfo.RxSNRdB[i] = (s4Byte)(pPhyStaRpt->path_rxsnr[i]/2); + #endif + + /* Record Signal Strength for next packet */ + //if(pPktinfo->bPacketMatchBSSID) + { +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if((pDM_Odm->SupportPlatform == ODM_WIN) && + (pDM_Odm->PatchID==RT_CID_819x_Lenovo)) + { + if(i==ODM_RF_PATH_A) + pPhyInfo->SignalQuality = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm,isCCKrate,PWDB_ALL,i,RSSI); + + } + else if((pDM_Odm->SupportPlatform == ODM_WIN) && + (pDM_Odm->PatchID==RT_CID_819x_Acer)) + { + pPhyInfo->SignalQuality = odm_SQ_process_patch_RT_CID_819x_Acer(pDM_Odm,isCCKrate,PWDB_ALL,0,RSSI); + } +#endif + } + } + + + // + // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) + // + rx_pwr_all = (((pPhyStaRpt->cck_sig_qual_ofdm_pwdb_all) >> 1 )& 0x7f) -110; + + PWDB_ALL_BT = PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); + + + pPhyInfo->RxPWDBAll = PWDB_ALL; + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ODM OFDM RSSI=%d\n",pPhyInfo->RxPWDBAll)); + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + pPhyInfo->BTRxRSSIPercentage = PWDB_ALL_BT; + pPhyInfo->RxPower = rx_pwr_all; + pPhyInfo->RecvSignalPower = rx_pwr_all; + #endif + + if((pDM_Odm->SupportPlatform == ODM_WIN) &&(pDM_Odm->PatchID==19)){ + //do nothing + }else if((pDM_Odm->SupportPlatform == ODM_WIN) &&(pDM_Odm->PatchID==25)){ + //do nothing + } + else{//pMgntInfo->CustomerID != RT_CID_819x_Lenovo + // + // (3)EVM of HT rate + // + if(pPktinfo->DataRate >=ODM_RATEMCS8 && pPktinfo->DataRate <=ODM_RATEMCS15) + Max_spatial_stream = 2; //both spatial stream make sense + else + Max_spatial_stream = 1; //only spatial stream 1 makes sense + + for(i=0; i>= 1" because the compilor of free build environment + // fill most significant bit to "zero" when doing shifting operation which may change a negative + // value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore. + EVM = odm_EVMdbToPercentage( (pPhyStaRpt->stream_rxevm[i] )); //dbm + + //GET_RX_STATUS_DESC_RX_MCS(pDesc), pDrvInfo->rxevm[i], "%", EVM)); + + //if(pPktinfo->bPacketMatchBSSID) + { + if(i==ODM_RF_PATH_A) // Fill value in RFD, Get the first spatial stream only + { + pPhyInfo->SignalQuality = (u1Byte)(EVM & 0xff); + } + pPhyInfo->RxMIMOSignalQuality[i] = (u1Byte)(EVM & 0xff); + } + } + } + + ODM_ParsingCFO(pDM_Odm, pPktinfo, pPhyStaRpt->path_cfotail); + + } +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + //UI BSS List signal strength(in percentage), make it good looking, from 0~100. + //It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp(). + if(isCCKrate) + { +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + // 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/ + pPhyInfo->SignalStrength = SignalScaleProc(pDM_Odm->Adapter, PWDB_ALL, TRUE, TRUE); +#else + #ifdef CONFIG_SIGNAL_SCALE_MAPPING + pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pDM_Odm, PWDB_ALL));/*PWDB_ALL;*/ + #else + pPhyInfo->SignalStrength = (u1Byte)PWDB_ALL; + #endif +#endif /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ + } + else + { + if (rf_rx_num != 0) + { + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + // 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/ + pPhyInfo->SignalStrength = SignalScaleProc(pDM_Odm->Adapter, (total_rssi /= rf_rx_num), TRUE, FALSE); + #else + #ifdef CONFIG_SIGNAL_SCALE_MAPPING + pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pDM_Odm, total_rssi /= rf_rx_num)); + #else + total_rssi/=rf_rx_num; + pPhyInfo->SignalStrength = (u1Byte)total_rssi; + #endif + #endif + } + } +#endif /*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))*/ + + //DbgPrint("isCCKrate = %d, pPhyInfo->RxPWDBAll = %d, pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a = 0x%x\n", + //isCCKrate, pPhyInfo->RxPWDBAll, pPhyStaRpt->cck_agc_rpt_ofdm_cfosho_a); + + //For 92C/92D HW (Hybrid) Antenna Diversity +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + //For 88E HW Antenna Diversity + pDM_Odm->DM_FatTable.antsel_rx_keep_0 = pPhyStaRpt->ant_sel; + pDM_Odm->DM_FatTable.antsel_rx_keep_1 = pPhyStaRpt->ant_sel_b; + pDM_Odm->DM_FatTable.antsel_rx_keep_2 = pPhyStaRpt->antsel_rx_keep_2; +#endif +} +#endif + +#if ODM_IC_11AC_SERIES_SUPPORT + +VOID +odm_RxPhyBWJaguarSeries_Parsing( + OUT PODM_PHY_INFO_T pPhyInfo, + IN PODM_PACKET_INFO_T pPktinfo, + IN PPHY_STATUS_RPT_8812_T pPhyStaRpt +) +{ + + if(pPktinfo->DataRate <= ODM_RATE54M) { + switch (pPhyStaRpt->r_RFMOD) { + case 1: + if (pPhyStaRpt->sub_chnl == 0) + pPhyInfo->BandWidth = 1; + else + pPhyInfo->BandWidth = 0; + break; + + case 2: + if (pPhyStaRpt->sub_chnl == 0) + pPhyInfo->BandWidth = 2; + else if (pPhyStaRpt->sub_chnl == 9 || pPhyStaRpt->sub_chnl == 10) + pPhyInfo->BandWidth = 1; + else + pPhyInfo->BandWidth = 0; + break; + + default: + case 0: + pPhyInfo->BandWidth = 0; + break; + } + } + +} + +VOID +odm_RxPhyStatusJaguarSeries_Parsing( + IN OUT PDM_ODM_T pDM_Odm, + OUT PODM_PHY_INFO_T pPhyInfo, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo +) +{ + u1Byte i, Max_spatial_stream; + s1Byte rx_pwr[4], rx_pwr_all = 0; + u1Byte EVM, EVMdbm, PWDB_ALL = 0, PWDB_ALL_BT; + u1Byte RSSI, avg_rssi = 0, best_rssi = 0, second_rssi = 0; + u1Byte isCCKrate = 0; + u1Byte rf_rx_num = 0; + u1Byte cck_highpwr = 0; + u1Byte LNA_idx, VGA_idx; + PPHY_STATUS_RPT_8812_T pPhyStaRpt = (PPHY_STATUS_RPT_8812_T)pPhyStatus; + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + + odm_RxPhyBWJaguarSeries_Parsing(pPhyInfo, pPktinfo, pPhyStaRpt); + + if (pPktinfo->DataRate <= ODM_RATE11M) + isCCKrate = TRUE; + else + isCCKrate = FALSE; + + pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = -1; + pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_B] = -1; + pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_C] = -1; + pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_D] = -1; + + if (isCCKrate) { + u1Byte cck_agc_rpt; + pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK++; + + /*(1)Hardware does not provide RSSI for CCK*/ + /*(2)PWDB, Average PWDB calculated by hardware (for rate adaptive)*/ + + /*if(pHalData->eRFPowerState == eRfOn)*/ + cck_highpwr = pDM_Odm->bCckHighPower; + /*else*/ + /*cck_highpwr = FALSE;*/ + + cck_agc_rpt = pPhyStaRpt->cfosho[0] ; + LNA_idx = ((cck_agc_rpt & 0xE0) >> 5); + VGA_idx = (cck_agc_rpt & 0x1F); + + if (pDM_Odm->SupportICType == ODM_RTL8812) { + switch (LNA_idx) { + case 7: + if (VGA_idx <= 27) + rx_pwr_all = -100 + 2 * (27 - VGA_idx); /*VGA_idx = 27~2*/ + else + rx_pwr_all = -100; + break; + case 6: + rx_pwr_all = -48 + 2 * (2 - VGA_idx); /*VGA_idx = 2~0*/ + break; + case 5: + rx_pwr_all = -42 + 2 * (7 - VGA_idx); /*VGA_idx = 7~5*/ + break; + case 4: + rx_pwr_all = -36 + 2 * (7 - VGA_idx); /*VGA_idx = 7~4*/ + break; + case 3: + /*rx_pwr_all = -28 + 2*(7-VGA_idx); VGA_idx = 7~0*/ + rx_pwr_all = -24 + 2 * (7 - VGA_idx); /*VGA_idx = 7~0*/ + break; + case 2: + if (cck_highpwr) + rx_pwr_all = -12 + 2 * (5 - VGA_idx); /*VGA_idx = 5~0*/ + else + rx_pwr_all = -6 + 2 * (5 - VGA_idx); + break; + case 1: + rx_pwr_all = 8 - 2 * VGA_idx; + break; + case 0: + rx_pwr_all = 14 - 2 * VGA_idx; + break; + default: + /*DbgPrint("CCK Exception default\n");*/ + break; + } + rx_pwr_all += 6; + PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); + + if (cck_highpwr == FALSE) { + if (PWDB_ALL >= 80) + PWDB_ALL = ((PWDB_ALL - 80) << 1) + ((PWDB_ALL - 80) >> 1) + 80; + else if ((PWDB_ALL <= 78) && (PWDB_ALL >= 20)) + PWDB_ALL += 3; + if (PWDB_ALL > 100) + PWDB_ALL = 100; + } + } else if (pDM_Odm->SupportICType & (ODM_RTL8821 | ODM_RTL8881A)) { + s1Byte Pout = -6; + + switch (LNA_idx) { + case 5: + rx_pwr_all = Pout - 32 - (2 * VGA_idx); + break; + case 4: + rx_pwr_all = Pout - 24 - (2 * VGA_idx); + break; + case 2: + rx_pwr_all = Pout - 11 - (2 * VGA_idx); + break; + case 1: + rx_pwr_all = Pout + 5 - (2 * VGA_idx); + break; + case 0: + rx_pwr_all = Pout + 21 - (2 * VGA_idx); + break; + } + PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); + } else if (pDM_Odm->SupportICType == ODM_RTL8814A || pDM_Odm->SupportICType == ODM_RTL8822B) { + s1Byte Pout = -6; + + switch (LNA_idx) { + /*CCK only use LNA: 2, 3, 5, 7*/ + case 7: + rx_pwr_all = Pout - 32 - (2 * VGA_idx); + break; + case 5: + rx_pwr_all = Pout - 22 - (2 * VGA_idx); + break; + case 3: + rx_pwr_all = Pout - 2 - (2 * VGA_idx); + break; + case 2: + rx_pwr_all = Pout + 5 - (2 * VGA_idx); + break; + /*case 6:*/ + /*rx_pwr_all = Pout -26 - (2*VGA_idx);*/ + /*break;*/ + /*case 4:*/ + /*rx_pwr_all = Pout - 8 - (2*VGA_idx);*/ + /*break;*/ + /*case 1:*/ + /*rx_pwr_all = Pout + 21 - (2*VGA_idx);*/ + /*break;*/ + /*case 0:*/ + /*rx_pwr_all = Pout + 10 - (2*VGA_idx);*/ +/* // break;*/ + default: +/* //DbgPrint("CCK Exception default\n");*/ + break; + } + PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); + } + + pPhyInfo->RxPWDBAll = PWDB_ALL; +/* //if(pPktinfo->StationID == 0)*/ +/* //{*/ +/* // DbgPrint("CCK: LNA_idx = %d, VGA_idx = %d, pPhyInfo->RxPWDBAll = %d\n",*/ +/* // LNA_idx, VGA_idx, pPhyInfo->RxPWDBAll);*/ +/* //}*/ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + pPhyInfo->BTRxRSSIPercentage = PWDB_ALL; + pPhyInfo->RecvSignalPower = rx_pwr_all; +#endif + /*(3) Get Signal Quality (EVM)*/ + if (pPktinfo->bPacketMatchBSSID) { + u1Byte SQ, SQ_rpt; + + if ((pDM_Odm->SupportPlatform == ODM_WIN) && + (pDM_Odm->PatchID == RT_CID_819x_Lenovo)) { + SQ = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm, isCCKrate, PWDB_ALL, 0, 0); + } else if (pPhyInfo->RxPWDBAll > 40 && !pDM_Odm->bInHctTest) { + SQ = 100; + } else { + SQ_rpt = pPhyStaRpt->pwdb_all; + + if (SQ_rpt > 64) + SQ = 0; + else if (SQ_rpt < 20) + SQ = 100; + else + SQ = ((64 - SQ_rpt) * 100) / 44; + } + +/* //DbgPrint("cck SQ = %d\n", SQ);*/ + pPhyInfo->SignalQuality = SQ; + pPhyInfo->RxMIMOSignalQuality[ODM_RF_PATH_A] = SQ; + } + + for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { + if (i == 0) + pPhyInfo->RxMIMOSignalStrength[0] = PWDB_ALL; + else + pPhyInfo->RxMIMOSignalStrength[i] = 0; + } + } else { + /*is OFDM rate*/ + pDM_FatTable->hw_antsw_occur = pPhyStaRpt->hw_antsw_occur; + + pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM++; + + /*(1)Get RSSI for OFDM rate*/ + + for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { + /*2008/01/30 MH we will judge RF RX path now.*/ +/* //DbgPrint("pDM_Odm->RFPathRxEnable = %x\n", pDM_Odm->RFPathRxEnable);*/ + if (pDM_Odm->RFPathRxEnable & BIT(i)) + rf_rx_num++; +/* //else*/ +/* //continue;*/ + /*2012.05.25 LukeLee: Testchip AGC report is wrong, it should be restored back to old formula in MP chip*/ +/* //if((pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821)) && (!pDM_Odm->bIsMPChip))*/ + if (i < ODM_RF_PATH_C) + rx_pwr[i] = (pPhyStaRpt->gain_trsw[i] & 0x7F) - 110; + else + rx_pwr[i] = (pPhyStaRpt->gain_trsw_cd[i - 2] & 0x7F) - 110; +/* //else*/ + /*rx_pwr[i] = ((pPhyStaRpt->gain_trsw[i]& 0x3F)*2) - 110; OLD FORMULA*/ + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + pPhyInfo->RxPwr[i] = rx_pwr[i]; +#endif + + /* Translate DBM to percentage. */ + RSSI = odm_QueryRxPwrPercentage(rx_pwr[i]); + + /*total_rssi += RSSI;*/ + /*Get the best two RSSI*/ + if (RSSI > best_rssi && RSSI > second_rssi) { + second_rssi = best_rssi; + best_rssi = RSSI; + } else if (RSSI > second_rssi && RSSI <= best_rssi) + second_rssi = RSSI; + + /*RT_DISP(FRX, RX_PHY_SS, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], RSSI));*/ + + pPhyInfo->RxMIMOSignalStrength[i] = (u1Byte) RSSI; + + + /*Get Rx snr value in DB*/ + if (i < ODM_RF_PATH_C) + pPhyInfo->RxSNR[i] = pDM_Odm->PhyDbgInfo.RxSNRdB[i] = pPhyStaRpt->rxsnr[i] / 2; + else if (pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_RTL8822B)) + pPhyInfo->RxSNR[i] = pDM_Odm->PhyDbgInfo.RxSNRdB[i] = pPhyStaRpt->csi_current[i - 2] / 2; + +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) + /*(2) CFO_short & CFO_tail*/ + if (i < ODM_RF_PATH_C) { + pPhyInfo->Cfo_short[i] = odm_Cfo((pPhyStaRpt->cfosho[i])); + pPhyInfo->Cfo_tail[i] = odm_Cfo((pPhyStaRpt->cfotail[i])); + } +#endif + /* Record Signal Strength for next packet */ + if (pPktinfo->bPacketMatchBSSID) { +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if ((pDM_Odm->SupportPlatform == ODM_WIN) && + (pDM_Odm->PatchID == RT_CID_819x_Lenovo)) { + if (i == ODM_RF_PATH_A) + pPhyInfo->SignalQuality = odm_SQ_process_patch_RT_CID_819x_Lenovo(pDM_Odm, isCCKrate, PWDB_ALL, i, RSSI); + + } +#endif + } + } + + /*(3)PWDB, Average PWDB calculated by hardware (for rate adaptive)*/ + + /*2012.05.25 LukeLee: Testchip AGC report is wrong, it should be restored back to old formula in MP chip*/ + if ((pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) && (!pDM_Odm->bIsMPChip)) + rx_pwr_all = (pPhyStaRpt->pwdb_all & 0x7f) - 110; + else + rx_pwr_all = (((pPhyStaRpt->pwdb_all) >> 1) & 0x7f) - 110; /*OLD FORMULA*/ + + PWDB_ALL_BT = PWDB_ALL = odm_QueryRxPwrPercentage(rx_pwr_all); + + pPhyInfo->RxPWDBAll = PWDB_ALL; + /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_RSSI_MONITOR, ODM_DBG_LOUD, ("ODM OFDM RSSI=%d\n",pPhyInfo->RxPWDBAll));*/ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + pPhyInfo->BTRxRSSIPercentage = PWDB_ALL_BT; + pPhyInfo->RxPower = rx_pwr_all; + pPhyInfo->RecvSignalPower = rx_pwr_all; +#endif + + if ((pDM_Odm->SupportPlatform == ODM_WIN) && (pDM_Odm->PatchID == 19)) { + /*do nothing*/ + } else { + /*pMgntInfo->CustomerID != RT_CID_819x_Lenovo*/ + + /*(4)EVM of OFDM rate*/ + + if ((pPktinfo->DataRate >= ODM_RATEMCS8) && + (pPktinfo->DataRate <= ODM_RATEMCS15)) + Max_spatial_stream = 2; + else if ((pPktinfo->DataRate >= ODM_RATEVHTSS2MCS0) && + (pPktinfo->DataRate <= ODM_RATEVHTSS2MCS9)) + Max_spatial_stream = 2; + else if ((pPktinfo->DataRate >= ODM_RATEMCS16) && + (pPktinfo->DataRate <= ODM_RATEMCS23)) + Max_spatial_stream = 3; + else if ((pPktinfo->DataRate >= ODM_RATEVHTSS3MCS0) && + (pPktinfo->DataRate <= ODM_RATEVHTSS3MCS9)) + Max_spatial_stream = 3; + else + Max_spatial_stream = 1; + + if (pPktinfo->bPacketMatchBSSID) { + /*DbgPrint("pPktinfo->DataRate = %d\n", pPktinfo->DataRate);*/ + + for (i = 0; i < Max_spatial_stream; i++) { + /*Do not use shift operation like "rx_evmX >>= 1" because the compilor of free build environment*/ + /*fill most significant bit to "zero" when doing shifting operation which may change a negative*/ + /*value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore.*/ + + if (pPktinfo->DataRate >= ODM_RATE6M && pPktinfo->DataRate <= ODM_RATE54M) { + if (i == ODM_RF_PATH_A) { + EVM = odm_EVMdbToPercentage((pPhyStaRpt->sigevm)); /*dbm*/ + EVM += 20; + if (EVM > 100) + EVM = 100; + } + } else { + if (i < ODM_RF_PATH_C) { + if (pPhyStaRpt->rxevm[i] == -128) + pPhyStaRpt->rxevm[i] = -25; + EVM = odm_EVMdbToPercentage((pPhyStaRpt->rxevm[i])); /*dbm*/ + } else { + if (pPhyStaRpt->rxevm_cd[i - 2] == -128){ + pPhyStaRpt->rxevm_cd[i - 2] = -25; + } + EVM = odm_EVMdbToPercentage((pPhyStaRpt->rxevm_cd[i - 2])); /*dbm*/ + } + } + + if (i < ODM_RF_PATH_C) + EVMdbm = odm_EVMdbm_JaguarSeries(pPhyStaRpt->rxevm[i]); + else + EVMdbm = odm_EVMdbm_JaguarSeries(pPhyStaRpt->rxevm_cd[i - 2]); + /*RT_DISP(FRX, RX_PHY_SQ, ("RXRATE=%x RXEVM=%x EVM=%s%d\n",*/ + /*pPktinfo->DataRate, pPhyStaRpt->rxevm[i], "%", EVM));*/ + + { + if (i == ODM_RF_PATH_A) { + /*Fill value in RFD, Get the first spatial stream only*/ + pPhyInfo->SignalQuality = EVM; + } + pPhyInfo->RxMIMOSignalQuality[i] = EVM; +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) + pPhyInfo->RxMIMOEVMdbm[i] = EVMdbm; +#endif + } + } + } + } + + ODM_ParsingCFO(pDM_Odm, pPktinfo, pPhyStaRpt->cfotail); + + } +/* //DbgPrint("isCCKrate= %d, pPhyInfo->SignalStrength=%d % PWDB_AL=%d rf_rx_num=%d\n", isCCKrate, pPhyInfo->SignalStrength, PWDB_ALL, rf_rx_num);*/ + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + /*UI BSS List signal strength(in percentage), make it good looking, from 0~100.*/ + /*It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp().*/ + if (isCCKrate) { +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + /*2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/*/ + pPhyInfo->SignalStrength = SignalScaleProc(pDM_Odm->Adapter, PWDB_ALL, FALSE, TRUE); +#else + pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pDM_Odm, PWDB_ALL));/*PWDB_ALL;*/ +#endif + } else { + if (rf_rx_num != 0) { + /* 2015/01 Sean, use the best two RSSI only, suggested by Ynlin and ChenYu.*/ + if (rf_rx_num == 1) + avg_rssi = best_rssi; + else + avg_rssi = (best_rssi + second_rssi)/2; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + /* 2012/01/12 MH Use customeris signal strength from HalComRxdDesc.c/*/ + pPhyInfo->SignalStrength = SignalScaleProc(pDM_Odm->Adapter, avg_rssi, FALSE, FALSE); +#else + pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pDM_Odm, avg_rssi)); +#endif + } + } +#endif + pDM_Odm->RxPWDBAve = pDM_Odm->RxPWDBAve + pPhyInfo->RxPWDBAll; + + pDM_Odm->DM_FatTable.antsel_rx_keep_0 = pPhyStaRpt->antidx_anta; + pDM_Odm->DM_FatTable.antsel_rx_keep_1 = pPhyStaRpt->antidx_antb; + pDM_Odm->DM_FatTable.antsel_rx_keep_2 = pPhyStaRpt->antidx_antc; + pDM_Odm->DM_FatTable.antsel_rx_keep_3 = pPhyStaRpt->antidx_antd; + /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("StaID[%d]: antidx_anta = ((%d)), MatchBSSID = ((%d))\n", pPktinfo->StationID, pPhyStaRpt->antidx_anta, pPktinfo->bPacketMatchBSSID));*/ + + +/* DbgPrint("pPhyStaRpt->antidx_anta = %d, pPhyStaRpt->antidx_antb = %d\n",*/ +/* pPhyStaRpt->antidx_anta, pPhyStaRpt->antidx_antb);*/ +/* DbgPrint("----------------------------\n");*/ +/* DbgPrint("pPktinfo->StationID=%d, pPktinfo->DataRate=0x%x\n",pPktinfo->StationID, pPktinfo->DataRate);*/ +/* DbgPrint("pPhyStaRpt->r_RFMOD = %d\n", pPhyStaRpt->r_RFMOD);*/ +/* DbgPrint("pPhyStaRpt->gain_trsw[0]=0x%x, pPhyStaRpt->gain_trsw[1]=0x%x\n",*/ +/* pPhyStaRpt->gain_trsw[0],pPhyStaRpt->gain_trsw[1]);*/ +/* DbgPrint("pPhyStaRpt->gain_trsw[2]=0x%x, pPhyStaRpt->gain_trsw[3]=0x%x\n",*/ +/* pPhyStaRpt->gain_trsw_cd[0],pPhyStaRpt->gain_trsw_cd[1]);*/ +/* DbgPrint("pPhyStaRpt->pwdb_all = 0x%x, pPhyInfo->RxPWDBAll = %d\n", pPhyStaRpt->pwdb_all, pPhyInfo->RxPWDBAll);*/ +/* DbgPrint("pPhyStaRpt->cfotail[i] = 0x%x, pPhyStaRpt->CFO_tail[i] = 0x%x\n", pPhyStaRpt->cfotail[0], pPhyStaRpt->cfotail[1]);*/ +/* DbgPrint("pPhyStaRpt->rxevm[0] = %d, pPhyStaRpt->rxevm[1] = %d\n", pPhyStaRpt->rxevm[0], pPhyStaRpt->rxevm[1]);*/ +/* DbgPrint("pPhyStaRpt->rxevm[2] = %d, pPhyStaRpt->rxevm[3] = %d\n", pPhyStaRpt->rxevm_cd[0], pPhyStaRpt->rxevm_cd[1]);*/ +/* DbgPrint("pPhyInfo->RxMIMOSignalStrength[0]=%d, pPhyInfo->RxMIMOSignalStrength[1]=%d, RxPWDBAll=%d\n",*/ +/* pPhyInfo->RxMIMOSignalStrength[0], pPhyInfo->RxMIMOSignalStrength[1], pPhyInfo->RxPWDBAll);*/ +/* DbgPrint("pPhyInfo->RxMIMOSignalStrength[2]=%d, pPhyInfo->RxMIMOSignalStrength[3]=%d\n",*/ +/* pPhyInfo->RxMIMOSignalStrength[2], pPhyInfo->RxMIMOSignalStrength[3]);*/ +/* DbgPrint("ppPhyInfo->RxMIMOSignalQuality[0]=%d, pPhyInfo->RxMIMOSignalQuality[1]=%d\n",*/ +/* pPhyInfo->RxMIMOSignalQuality[0], pPhyInfo->RxMIMOSignalQuality[1]);*/ +/* DbgPrint("ppPhyInfo->RxMIMOSignalQuality[2]=%d, pPhyInfo->RxMIMOSignalQuality[3]=%d\n",*/ +/* pPhyInfo->RxMIMOSignalQuality[2], pPhyInfo->RxMIMOSignalQuality[3]);*/ + +} + +#endif + +VOID +odm_Init_RSSIForDM( + IN OUT PDM_ODM_T pDM_Odm + ) +{ + +} + +VOID +odm_Process_RSSIForDM( + IN OUT PDM_ODM_T pDM_Odm, + IN PODM_PHY_INFO_T pPhyInfo, + IN PODM_PACKET_INFO_T pPktinfo + ) +{ + + s4Byte UndecoratedSmoothedPWDB, UndecoratedSmoothedCCK, UndecoratedSmoothedOFDM, RSSI_Ave; + u1Byte i, isCCKrate=0; + u1Byte RSSI_max, RSSI_min; + u4Byte OFDM_pkt=0; + u4Byte Weighting=0; + PSTA_INFO_T pEntry; + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; + #endif + + if (pPktinfo->StationID >= ODM_ASSOCIATE_ENTRY_NUM) + return; + + #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY + odm_S0S1_SwAntDivByCtrlFrame_ProcessRSSI(pDM_Odm, pPhyInfo, pPktinfo); + #endif + + // + // 2012/05/30 MH/Luke.Lee Add some description + // In windows driver: AP/IBSS mode STA + // + //if (pDM_Odm->SupportPlatform == ODM_WIN) + //{ + // pEntry = pDM_Odm->pODM_StaInfo[pDM_Odm->pAidMap[pPktinfo->StationID-1]]; + //} + //else + pEntry = pDM_Odm->pODM_StaInfo[pPktinfo->StationID]; + + if(!IS_STA_VALID(pEntry) ) + { + return; + } + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + if ((pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) && + (pDM_FatTable->enable_ctrl_frame_antdiv) + ) + { + if (pPktinfo->bPacketMatchBSSID) + pDM_Odm->data_frame_num++; + + if ((pDM_FatTable->use_ctrl_frame_antdiv)) { + if (!pPktinfo->bToSelf)/*data frame + CTRL frame*/ + return; + } else { + if ((!pPktinfo->bPacketMatchBSSID))/*data frame only*/ + return; + } + } else +#endif + { + if ((!pPktinfo->bPacketMatchBSSID))/*data frame only*/ + return; + } + + if(pPktinfo->bPacketBeacon) + pDM_Odm->PhyDbgInfo.NumQryBeaconPkt++; + + isCCKrate = (pPktinfo->DataRate <= ODM_RATE11M )?TRUE :FALSE; + pDM_Odm->RxRate = pPktinfo->DataRate; + + //--------------Statistic for antenna/path diversity------------------ + if(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) + { + #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + ODM_Process_RSSIForAntDiv(pDM_Odm,pPhyInfo,pPktinfo); + #endif + } + #if(defined(CONFIG_PATH_DIVERSITY)) + else if(pDM_Odm->SupportAbility & ODM_BB_PATH_DIV) + { + phydm_process_rssi_for_path_div(pDM_Odm,pPhyInfo,pPktinfo); + } + #endif + //-----------------Smart Antenna Debug Message------------------// + + UndecoratedSmoothedCCK = pEntry->rssi_stat.UndecoratedSmoothedCCK; + UndecoratedSmoothedOFDM = pEntry->rssi_stat.UndecoratedSmoothedOFDM; + UndecoratedSmoothedPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; + + if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon) + { + + if(!isCCKrate)//ofdm rate + { +#if (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1) + if (pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_RTL8822B)) { + u1Byte RX_count = 0; + u4Byte RSSI_linear = 0; + + if (pDM_Odm->RXAntStatus & ODM_RF_A) { + pDM_Odm->RSSI_A = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; + RX_count++; + RSSI_linear += odm_ConvertTo_linear(pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]); + } else + pDM_Odm->RSSI_A = 0; + + if (pDM_Odm->RXAntStatus & ODM_RF_B) { + pDM_Odm->RSSI_B = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]; + RX_count++; + RSSI_linear += odm_ConvertTo_linear(pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]); + } else + pDM_Odm->RSSI_B = 0; + + if (pDM_Odm->RXAntStatus & ODM_RF_C) { + pDM_Odm->RSSI_C = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_C]; + RX_count++; + RSSI_linear += odm_ConvertTo_linear(pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_C]); + } else + pDM_Odm->RSSI_C = 0; + + if (pDM_Odm->RXAntStatus & ODM_RF_D) { + pDM_Odm->RSSI_D = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_D]; + RX_count++; + RSSI_linear += odm_ConvertTo_linear(pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_D]); + } else + pDM_Odm->RSSI_D = 0; + + /* Calculate average RSSI */ + switch (RX_count) { + case 2: + RSSI_linear = (RSSI_linear >> 1); + break; + case 3: + RSSI_linear = ((RSSI_linear) + (RSSI_linear << 1) + (RSSI_linear << 3)) >> 5; /* RSSI_linear/3 ~ RSSI_linear*11/32 */ + break; + case 4: + RSSI_linear = (RSSI_linear >> 2); + break; + } + RSSI_Ave = odm_ConvertTo_dB(RSSI_linear); + } else +#endif + { + if (pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B] == 0) { + RSSI_Ave = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; + pDM_Odm->RSSI_A = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; + pDM_Odm->RSSI_B = 0; + } else { + /*DbgPrint("pRfd->Status.RxMIMOSignalStrength[0] = %d, pRfd->Status.RxMIMOSignalStrength[1] = %d\n",*/ + /*pRfd->Status.RxMIMOSignalStrength[0], pRfd->Status.RxMIMOSignalStrength[1]);*/ + pDM_Odm->RSSI_A = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; + pDM_Odm->RSSI_B = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]; + + if (pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A] > pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]) { + RSSI_max = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; + RSSI_min = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]; + } else { + RSSI_max = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]; + RSSI_min = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; + } + if ((RSSI_max - RSSI_min) < 3) + RSSI_Ave = RSSI_max; + else if ((RSSI_max - RSSI_min) < 6) + RSSI_Ave = RSSI_max - 1; + else if ((RSSI_max - RSSI_min) < 10) + RSSI_Ave = RSSI_max - 2; + else + RSSI_Ave = RSSI_max - 3; + } + } + + //1 Process OFDM RSSI + if(UndecoratedSmoothedOFDM <= 0) // initialize + { + UndecoratedSmoothedOFDM = pPhyInfo->RxPWDBAll; + } + else + { + if(pPhyInfo->RxPWDBAll > (u4Byte)UndecoratedSmoothedOFDM) + { + UndecoratedSmoothedOFDM = + ( ((UndecoratedSmoothedOFDM)*(Rx_Smooth_Factor-1)) + + (RSSI_Ave)) /(Rx_Smooth_Factor); + UndecoratedSmoothedOFDM = UndecoratedSmoothedOFDM + 1; + } + else + { + UndecoratedSmoothedOFDM = + ( ((UndecoratedSmoothedOFDM)*(Rx_Smooth_Factor-1)) + + (RSSI_Ave)) /(Rx_Smooth_Factor); + } + } + if (pEntry->rssi_stat.OFDM_pkt != 64) { + i = 63; + pEntry->rssi_stat.OFDM_pkt -= (u4Byte)(((pEntry->rssi_stat.PacketMap>>i)&BIT0)-1); + } + pEntry->rssi_stat.PacketMap = (pEntry->rssi_stat.PacketMap<<1) | BIT0; + + } + else + { + RSSI_Ave = pPhyInfo->RxPWDBAll; + pDM_Odm->RSSI_A = (u1Byte) pPhyInfo->RxPWDBAll; + pDM_Odm->RSSI_B = 0xFF; + pDM_Odm->RSSI_C = 0xFF; + pDM_Odm->RSSI_D = 0xFF; + + //1 Process CCK RSSI + if(UndecoratedSmoothedCCK <= 0) // initialize + { + UndecoratedSmoothedCCK = pPhyInfo->RxPWDBAll; + } + else + { + if(pPhyInfo->RxPWDBAll > (u4Byte)UndecoratedSmoothedCCK) + { + UndecoratedSmoothedCCK = + ( ((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) + + (pPhyInfo->RxPWDBAll)) /(Rx_Smooth_Factor); + UndecoratedSmoothedCCK = UndecoratedSmoothedCCK + 1; + } + else + { + UndecoratedSmoothedCCK = + ( ((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) + + (pPhyInfo->RxPWDBAll)) /(Rx_Smooth_Factor); + } + } + i = 63; + pEntry->rssi_stat.OFDM_pkt -= (u4Byte)((pEntry->rssi_stat.PacketMap>>i)&BIT0); + pEntry->rssi_stat.PacketMap = pEntry->rssi_stat.PacketMap<<1; + } + + //if(pEntry) + { + //2011.07.28 LukeLee: modified to prevent unstable CCK RSSI + if (pEntry->rssi_stat.OFDM_pkt == 64) { /* speed up when all packets are OFDM*/ + UndecoratedSmoothedPWDB = UndecoratedSmoothedOFDM; + } else { + if (pEntry->rssi_stat.ValidBit < 64) + pEntry->rssi_stat.ValidBit++; + + if (pEntry->rssi_stat.ValidBit == 64) { + Weighting = ((pEntry->rssi_stat.OFDM_pkt<<4) > 64)?64:(pEntry->rssi_stat.OFDM_pkt<<4); + UndecoratedSmoothedPWDB = (Weighting*UndecoratedSmoothedOFDM+(64-Weighting)*UndecoratedSmoothedCCK)>>6; + } else { + if (pEntry->rssi_stat.ValidBit != 0) + UndecoratedSmoothedPWDB = (pEntry->rssi_stat.OFDM_pkt*UndecoratedSmoothedOFDM+(pEntry->rssi_stat.ValidBit-pEntry->rssi_stat.OFDM_pkt)*UndecoratedSmoothedCCK)/pEntry->rssi_stat.ValidBit; + else + UndecoratedSmoothedPWDB = 0; + } + } + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (pEntry->rssi_stat.UndecoratedSmoothedPWDB == -1) + phydm_ra_rssi_rpt_wk(pDM_Odm); + #endif + pEntry->rssi_stat.UndecoratedSmoothedCCK = UndecoratedSmoothedCCK; + pEntry->rssi_stat.UndecoratedSmoothedOFDM = UndecoratedSmoothedOFDM; + pEntry->rssi_stat.UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB; + + //DbgPrint("OFDM_pkt=%d, Weighting=%d\n", OFDM_pkt, Weighting); + //DbgPrint("UndecoratedSmoothedOFDM=%d, UndecoratedSmoothedPWDB=%d, UndecoratedSmoothedCCK=%d\n", + // UndecoratedSmoothedOFDM, UndecoratedSmoothedPWDB, UndecoratedSmoothedCCK); + + } + + } +} + + +#if(ODM_IC_11N_SERIES_SUPPORT ==1) +// +// Endianness before calling this API +// +VOID +ODM_PhyStatusQuery_92CSeries( + IN OUT PDM_ODM_T pDM_Odm, + OUT PODM_PHY_INFO_T pPhyInfo, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo + ) +{ + odm_RxPhyStatus92CSeries_Parsing(pDM_Odm, pPhyInfo, pPhyStatus, pPktinfo); + odm_Process_RSSIForDM(pDM_Odm, pPhyInfo, pPktinfo); +} +#endif + + +// +// Endianness before calling this API +// +#if ODM_IC_11AC_SERIES_SUPPORT + +VOID +ODM_PhyStatusQuery_JaguarSeries( + IN OUT PDM_ODM_T pDM_Odm, + OUT PODM_PHY_INFO_T pPhyInfo, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo + ) +{ + odm_RxPhyStatusJaguarSeries_Parsing( + pDM_Odm, + pPhyInfo, + pPhyStatus, + pPktinfo); + + odm_Process_RSSIForDM(pDM_Odm,pPhyInfo,pPktinfo); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + //phydm_sbd_check(pDM_Odm); +#endif +} +#endif + +VOID +ODM_PhyStatusQuery( + IN OUT PDM_ODM_T pDM_Odm, + OUT PODM_PHY_INFO_T pPhyInfo, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo + ) +{ +#if (RTL8822B_SUPPORT == 1) + if (pDM_Odm->SupportICType & ODM_RTL8822B) { + phydm_RxPhyStatusJaguarSeries2(pDM_Odm, pPhyStatus, pPktinfo, pPhyInfo); + return; + } +#endif + +#if ODM_IC_11AC_SERIES_SUPPORT + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + ODM_PhyStatusQuery_JaguarSeries(pDM_Odm, pPhyInfo, pPhyStatus, pPktinfo); +#endif + +#if ODM_IC_11N_SERIES_SUPPORT + if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES ) + ODM_PhyStatusQuery_92CSeries(pDM_Odm,pPhyInfo,pPhyStatus,pPktinfo); +#endif +} + +// For future use. +VOID ODM_MacStatusQuery( + IN OUT PDM_ODM_T pDM_Odm, + IN pu1Byte pMacStatus, + IN u1Byte MacID, + IN BOOLEAN bPacketMatchBSSID, + IN BOOLEAN bPacketToSelf, + IN BOOLEAN bPacketBeacon + ) +{ + // 2011/10/19 Driver team will handle in the future. + +} + + +// +// If you want to add a new IC, Please follow below template and generate a new one. +// +// + +HAL_STATUS +ODM_ConfigRFWithHeaderFile( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_Config_Type ConfigType, + IN ODM_RF_RADIO_PATH_E eRFPath + ) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("===>ODM_ConfigRFWithHeaderFile (%s)\n", (pDM_Odm->bIsMPChip) ? "MPChip" : "TestChip")); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("pDM_Odm->SupportPlatform: 0x%X, pDM_Odm->SupportInterface: 0x%X, pDM_Odm->BoardType: 0x%X\n", + pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface, pDM_Odm->BoardType)); + +//1 AP doesn't use PHYDM power tracking table in these ICs +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) +#if (RTL8723A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8723A) + { + if(ConfigType == CONFIG_RF_RADIO) { + if(eRFPath == ODM_RF_PATH_A) + READ_AND_CONFIG_MP(8723A,_RadioA); + } + } +#endif +#if (RTL8812A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8812) + { + if(ConfigType == CONFIG_RF_RADIO) { + if(eRFPath == ODM_RF_PATH_A){ + READ_AND_CONFIG_MP(8812A,_RadioA); + } + else if(eRFPath == ODM_RF_PATH_B){ + READ_AND_CONFIG_MP(8812A,_RadioB); + } + } + else if(ConfigType == CONFIG_RF_TXPWR_LMT) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) && (DEV_BUS_TYPE == RT_PCI_INTERFACE) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + if ((pHalData->EEPROMSVID == 0x17AA && pHalData->EEPROMSMID == 0xA811) || + (pHalData->EEPROMSVID == 0x10EC && pHalData->EEPROMSMID == 0xA812) || + (pHalData->EEPROMSVID == 0x10EC && pHalData->EEPROMSMID == 0x8812)) + READ_AND_CONFIG_MP(8812A,_TXPWR_LMT_HM812A03); + else + #endif + READ_AND_CONFIG_MP(8812A,_TXPWR_LMT); + } + } +#endif +#if (RTL8821A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8821) + { + if(ConfigType == CONFIG_RF_RADIO) { + if(eRFPath == ODM_RF_PATH_A){ + READ_AND_CONFIG_MP(8821A,_RadioA); + } + } + else if(ConfigType == CONFIG_RF_TXPWR_LMT) { + if (pDM_Odm->SupportInterface == ODM_ITRF_USB) { + if (pDM_Odm->ExtPA5G || pDM_Odm->ExtLNA5G) + READ_AND_CONFIG_MP(8821A,_TXPWR_LMT_8811AU_FEM); + else + READ_AND_CONFIG_MP(8821A,_TXPWR_LMT_8811AU_IPA); + } + else { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + if (pMgntInfo->CustomerID == RT_CID_8821AE_ASUS_MB) + READ_AND_CONFIG_MP(8821A,_TXPWR_LMT_8821A_SAR_8mm); + else if (pMgntInfo->CustomerID == RT_CID_ASUS_NB) + READ_AND_CONFIG_MP(8821A,_TXPWR_LMT_8821A_SAR_5mm); + else + #endif + READ_AND_CONFIG_MP(8821A,_TXPWR_LMT_8821A); + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("<===8821_ODM_ConfigRFWithHeaderFile\n")); + } +#endif + +#if (RTL8723B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8723B) + { + if(ConfigType == CONFIG_RF_RADIO) + READ_AND_CONFIG_MP(8723B,_RadioA); + else if(ConfigType == CONFIG_RF_TXPWR_LMT) + READ_AND_CONFIG_MP(8723B,_TXPWR_LMT); + } +#endif + +#if (RTL8192E_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8192E) + { + if(ConfigType == CONFIG_RF_RADIO) { + if(eRFPath == ODM_RF_PATH_A) + READ_AND_CONFIG_MP(8192E,_RadioA); + else if(eRFPath == ODM_RF_PATH_B) + READ_AND_CONFIG_MP(8192E,_RadioB); + } else if (ConfigType == CONFIG_RF_TXPWR_LMT) { +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) && (DEV_BUS_TYPE == RT_PCI_INTERFACE) /*Refine by Vincent Lan for 5mm SAR pwr limit*/ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + if ((pHalData->EEPROMSVID == 0x11AD && pHalData->EEPROMSMID == 0x8192) || + (pHalData->EEPROMSVID == 0x11AD && pHalData->EEPROMSMID == 0x8193)) + READ_AND_CONFIG_MP(8192E, _TXPWR_LMT_8192E_SAR_5mm); + else +#endif + READ_AND_CONFIG_MP(8192E,_TXPWR_LMT); + } + } +#endif +#endif//(DM_ODM_SUPPORT_TYPE != ODM_AP) + +//1 All platforms support +#if (RTL8188E_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8188E) + { + if(ConfigType == CONFIG_RF_RADIO) { + if(eRFPath == ODM_RF_PATH_A) + READ_AND_CONFIG_MP(8188E,_RadioA); + } + else if(ConfigType == CONFIG_RF_TXPWR_LMT) + READ_AND_CONFIG_MP(8188E,_TXPWR_LMT); + } +#endif +#if (RTL8814A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8814A) + { + if(ConfigType == CONFIG_RF_RADIO) { + if(eRFPath == ODM_RF_PATH_A) + READ_AND_CONFIG_MP(8814A,_RadioA); + else if(eRFPath == ODM_RF_PATH_B) + READ_AND_CONFIG_MP(8814A,_RadioB); + else if(eRFPath == ODM_RF_PATH_C) + READ_AND_CONFIG_MP(8814A,_RadioC); + else if(eRFPath == ODM_RF_PATH_D) + READ_AND_CONFIG_MP(8814A,_RadioD); + } + else if(ConfigType == CONFIG_RF_TXPWR_LMT) + READ_AND_CONFIG_MP(8814A,_TXPWR_LMT); + } +#endif +#if (RTL8703B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8703B) { + if (ConfigType == CONFIG_RF_RADIO) { + if (eRFPath == ODM_RF_PATH_A) + READ_AND_CONFIG_MP(8703B, _RadioA); + } + } +#endif + +#if (RTL8188F_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8188F) { + if (ConfigType == CONFIG_RF_RADIO) { + if (eRFPath == ODM_RF_PATH_A) + READ_AND_CONFIG_MP(8188F, _RadioA); + } else if (ConfigType == CONFIG_RF_TXPWR_LMT) + READ_AND_CONFIG_MP(8188F, _TXPWR_LMT); + } +#endif + +//1 New ICs (WIN only) +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (RTL8821B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8821B) + { + if (ConfigType == CONFIG_RF_RADIO) { + if (eRFPath == ODM_RF_PATH_A) + READ_AND_CONFIG(8821B, _RadioA); + } else if (ConfigType == CONFIG_RF_TXPWR_LMT) + READ_AND_CONFIG(8821B, _TXPWR_LMT); + } +#endif +#if (RTL8822B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8822B) + { + if(ConfigType == CONFIG_RF_RADIO) { + if(eRFPath == ODM_RF_PATH_A) + READ_AND_CONFIG_MP(8822B, _RadioA); + else if(eRFPath == ODM_RF_PATH_B) + READ_AND_CONFIG_MP(8822B, _RadioB); + } + } +#endif +#if ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) +#if (RTL8188F_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8188F) + { + if(ConfigType == CONFIG_RF_RADIO) { + if(eRFPath == ODM_RF_PATH_A) + READ_AND_CONFIG_TC(8188F,_RadioA); + } + } +#endif +#endif +#endif//(DM_ODM_SUPPORT_TYPE & ODM_WIN) + + return HAL_STATUS_SUCCESS; +} + +HAL_STATUS +ODM_ConfigRFWithTxPwrTrackHeaderFile( + IN PDM_ODM_T pDM_Odm + ) +{ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("===>ODM_ConfigRFWithTxPwrTrackHeaderFile (%s)\n", (pDM_Odm->bIsMPChip) ? "MPChip" : "TestChip")); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("pDM_Odm->SupportPlatform: 0x%X, pDM_Odm->SupportInterface: 0x%X, pDM_Odm->BoardType: 0x%X\n", + pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface, pDM_Odm->BoardType)); + + +//1 AP doesn't use PHYDM power tracking table in these ICs +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) +#if RTL8821A_SUPPORT + if(pDM_Odm->SupportICType == ODM_RTL8821) + { + if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) + READ_AND_CONFIG_MP(8821A,_TxPowerTrack_PCIE); + else if (pDM_Odm->SupportInterface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8821A,_TxPowerTrack_USB); + else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8821A,_TxPowerTrack_SDIO); + } +#endif +#if RTL8812A_SUPPORT + if(pDM_Odm->SupportICType == ODM_RTL8812) + { + if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) + READ_AND_CONFIG_MP(8812A,_TxPowerTrack_PCIE); + else if (pDM_Odm->SupportInterface == ODM_ITRF_USB) { + if (pDM_Odm->RFEType == 3 && pDM_Odm->bIsMPChip) + READ_AND_CONFIG_MP(8812A,_TxPowerTrack_RFE3); + else + READ_AND_CONFIG_MP(8812A,_TxPowerTrack_USB); + } + + } +#endif +#if RTL8192E_SUPPORT + if(pDM_Odm->SupportICType == ODM_RTL8192E) + { + if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) + READ_AND_CONFIG_MP(8192E,_TxPowerTrack_PCIE); + else if (pDM_Odm->SupportInterface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8192E,_TxPowerTrack_USB); + else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8192E,_TxPowerTrack_SDIO); + } +#endif +#if RTL8723B_SUPPORT + if(pDM_Odm->SupportICType == ODM_RTL8723B) + { + if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) + READ_AND_CONFIG_MP(8723B,_TxPowerTrack_PCIE); + else if (pDM_Odm->SupportInterface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8723B,_TxPowerTrack_USB); + else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8723B,_TxPowerTrack_SDIO); + } +#endif +#if RTL8188E_SUPPORT + if(pDM_Odm->SupportICType == ODM_RTL8188E) + { + if (pDM_Odm->SupportInterface == ODM_ITRF_PCIE) + READ_AND_CONFIG_MP(8188E,_TxPowerTrack_PCIE); + else if (pDM_Odm->SupportInterface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8188E,_TxPowerTrack_USB); + else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8188E,_TxPowerTrack_SDIO); + } +#endif +#endif//(DM_ODM_SUPPORT_TYPE != ODM_AP) + +//1 All platforms support +#if RTL8814A_SUPPORT + if(pDM_Odm->SupportICType == ODM_RTL8814A) + { + if(pDM_Odm->RFEType == 0) + READ_AND_CONFIG_MP(8814A,_TxPowerTrack_Type0); + else if(pDM_Odm->RFEType == 2) + READ_AND_CONFIG_MP(8814A,_TxPowerTrack_Type2); + else if (pDM_Odm->RFEType == 5) + READ_AND_CONFIG_MP(8814A, _TxPowerTrack_Type5); + else + READ_AND_CONFIG_MP(8814A,_TxPowerTrack); + } +#endif +#if RTL8703B_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8703B) { + if (pDM_Odm->SupportInterface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8703B, _TxPowerTrack_USB); + else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8703B, _TxPowerTrack_SDIO); + } +#endif + +#if RTL8188F_SUPPORT + if (pDM_Odm->SupportICType == ODM_RTL8188F) { + if (pDM_Odm->SupportInterface == ODM_ITRF_USB) + READ_AND_CONFIG_MP(8188F, _TxPowerTrack_USB); + else if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO) + READ_AND_CONFIG_MP(8188F, _TxPowerTrack_SDIO); + } +#endif + +//1 New ICs (WIN only) +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if RTL8821B_SUPPORT + if(pDM_Odm->SupportICType == ODM_RTL8821B) + READ_AND_CONFIG(8821B,_TxPowerTrack); +#endif +#if RTL8822B_SUPPORT +/* if(pDM_Odm->SupportICType == ODM_RTL8822B) + READ_AND_CONFIG_MP(8822B, _TxPowerTrack); */ +#endif + +#if ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) +#if RTL8188F_SUPPORT + if(pDM_Odm->SupportICType == ODM_RTL8188F) + READ_AND_CONFIG_TC(8188F,_TxPowerTrack_PCIE); +#endif +#endif +#endif//(DM_ODM_SUPPORT_TYPE & ODM_WIN) + + + return HAL_STATUS_SUCCESS; +} + +HAL_STATUS +ODM_ConfigBBWithHeaderFile( + IN PDM_ODM_T pDM_Odm, + IN ODM_BB_Config_Type ConfigType + ) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); +#endif + +//1 AP doesn't use PHYDM initialization in these ICs +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) +#if (RTL8723A_SUPPORT == 1) + if(pDM_Odm->SupportICType == ODM_RTL8723A) + { + if(ConfigType == CONFIG_BB_PHY_REG){ + READ_AND_CONFIG_MP(8723A,_PHY_REG); + }else if(ConfigType == CONFIG_BB_AGC_TAB){ + READ_AND_CONFIG_MP(8723A,_AGC_TAB); + } + } +#endif +#if (RTL8812A_SUPPORT == 1) + if(pDM_Odm->SupportICType == ODM_RTL8812) + { + if(ConfigType == CONFIG_BB_PHY_REG){ + READ_AND_CONFIG_MP(8812A,_PHY_REG); + }else if(ConfigType == CONFIG_BB_AGC_TAB){ + READ_AND_CONFIG_MP(8812A,_AGC_TAB); + } + else if(ConfigType == CONFIG_BB_PHY_REG_PG) + { + if (pDM_Odm->RFEType == 3 && pDM_Odm->bIsMPChip) + READ_AND_CONFIG_MP(8812A,_PHY_REG_PG_ASUS); + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + else if (pMgntInfo->CustomerID == RT_CID_WNC_NEC && pDM_Odm->bIsMPChip) + READ_AND_CONFIG_MP(8812A,_PHY_REG_PG_NEC); + #endif + else + READ_AND_CONFIG_MP(8812A,_PHY_REG_PG); + } + else if(ConfigType == CONFIG_BB_PHY_REG_MP){ + READ_AND_CONFIG_MP(8812A,_PHY_REG_MP); + } + else if(ConfigType == CONFIG_BB_AGC_TAB_DIFF) + { + if ((36 <= *pDM_Odm->pChannel) && (*pDM_Odm->pChannel <= 64)) + AGC_DIFF_CONFIG_MP(8812A,LB); + else if (100 <= *pDM_Odm->pChannel) + AGC_DIFF_CONFIG_MP(8812A,HB); + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8812AGCTABArray\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8812PHY_REGArray\n")); + } +#endif +#if (RTL8821A_SUPPORT == 1) + if(pDM_Odm->SupportICType == ODM_RTL8821) + { + if(ConfigType == CONFIG_BB_PHY_REG){ + READ_AND_CONFIG_MP(8821A,_PHY_REG); + }else if(ConfigType == CONFIG_BB_AGC_TAB){ + READ_AND_CONFIG_MP(8821A,_AGC_TAB); + }else if(ConfigType == CONFIG_BB_PHY_REG_PG){ + READ_AND_CONFIG_MP(8821A,_PHY_REG_PG); + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8821AGCTABArray\n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8821PHY_REGArray\n")); + } +#endif +#if (RTL8723B_SUPPORT == 1) + if(pDM_Odm->SupportICType == ODM_RTL8723B) + { + if(ConfigType == CONFIG_BB_PHY_REG){ + READ_AND_CONFIG_MP(8723B,_PHY_REG); + }else if(ConfigType == CONFIG_BB_AGC_TAB){ + READ_AND_CONFIG_MP(8723B,_AGC_TAB); + }else if(ConfigType == CONFIG_BB_PHY_REG_PG){ + READ_AND_CONFIG_MP(8723B,_PHY_REG_PG); + } + } +#endif +#if (RTL8192E_SUPPORT == 1) + if(pDM_Odm->SupportICType == ODM_RTL8192E) + { + if(ConfigType == CONFIG_BB_PHY_REG){ + READ_AND_CONFIG_MP(8192E,_PHY_REG); + }else if(ConfigType == CONFIG_BB_AGC_TAB){ + READ_AND_CONFIG_MP(8192E,_AGC_TAB); + }else if(ConfigType == CONFIG_BB_PHY_REG_PG){ + READ_AND_CONFIG_MP(8192E,_PHY_REG_PG); + } + } +#endif +#endif//(DM_ODM_SUPPORT_TYPE != ODM_AP) + + +//1 All platforms support +#if (RTL8188E_SUPPORT == 1) + if(pDM_Odm->SupportICType == ODM_RTL8188E) + { + if(ConfigType == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8188E,_PHY_REG); + else if(ConfigType == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8188E,_AGC_TAB); + else if(ConfigType == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG_MP(8188E,_PHY_REG_PG); + } +#endif +#if (RTL8814A_SUPPORT == 1) + if(pDM_Odm->SupportICType == ODM_RTL8814A) + { + if(ConfigType == CONFIG_BB_PHY_REG){ + READ_AND_CONFIG_MP(8814A,_PHY_REG); + }else if(ConfigType == CONFIG_BB_AGC_TAB){ + READ_AND_CONFIG_MP(8814A,_AGC_TAB); + }else if(ConfigType == CONFIG_BB_PHY_REG_PG){ + READ_AND_CONFIG_MP(8814A,_PHY_REG_PG); + }else if(ConfigType == CONFIG_BB_PHY_REG_MP){ + READ_AND_CONFIG_MP(8814A,_PHY_REG_MP); + } + } +#endif +#if (RTL8703B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8703B) { + if (ConfigType == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8703B, _PHY_REG); + else if (ConfigType == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8703B, _AGC_TAB); + else if (ConfigType == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG_MP(8703B, _PHY_REG_PG); + } +#endif + +#if (RTL8188F_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8188F) { + if (ConfigType == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8188F, _PHY_REG); + else if (ConfigType == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8188F, _AGC_TAB); + else if (ConfigType == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG_MP(8188F, _PHY_REG_PG); + } +#endif + +//1 New ICs (WIN only) +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (RTL8821B_SUPPORT == 1) + if(pDM_Odm->SupportICType == ODM_RTL8821B) + { + if (ConfigType == CONFIG_BB_PHY_REG) { + READ_AND_CONFIG(8821B,_PHY_REG); + } else if (ConfigType == CONFIG_BB_AGC_TAB) { + READ_AND_CONFIG(8821B,_AGC_TAB); + } else if (ConfigType == CONFIG_BB_PHY_REG_PG) { + READ_AND_CONFIG(8821B,_PHY_REG_PG); + } + } +#endif +#if (RTL8822B_SUPPORT == 1) + if(pDM_Odm->SupportICType == ODM_RTL8822B) + { + if(ConfigType == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_MP(8822B, _PHY_REG); + else if(ConfigType == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_MP(8822B, _AGC_TAB); +/* else if(ConfigType == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG_MP(8822B, _PHY_REG_PG); + else if(ConfigType == CONFIG_BB_PHY_REG_MP) + READ_AND_CONFIG_MP(8822B, _PHY_REG_MP); */ + } +#endif +#if ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) +#if (RTL8188F_SUPPORT == 1) + if(pDM_Odm->SupportICType == ODM_RTL8188F) + { + if(ConfigType == CONFIG_BB_PHY_REG) + READ_AND_CONFIG_TC(8188F,_PHY_REG); + else if(ConfigType == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG_TC(8188F,_AGC_TAB); + else if(ConfigType == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG_TC(8188F,_PHY_REG_PG); + } +#endif +#endif +#if (RTL8195A_SUPPORT == 1) + if(pDM_Odm->SupportICType == ODM_RTL8195A) + { + if(ConfigType == CONFIG_BB_PHY_REG) + READ_AND_CONFIG(8195A,_PHY_REG); + else if(ConfigType == CONFIG_BB_AGC_TAB) + READ_AND_CONFIG(8195A,_AGC_TAB); + else if(ConfigType == CONFIG_BB_PHY_REG_PG) + READ_AND_CONFIG(8195A,_PHY_REG_PG); + } +#endif +#endif//(DM_ODM_SUPPORT_TYPE & ODM_WIN) + + return HAL_STATUS_SUCCESS; +} + +HAL_STATUS +ODM_ConfigMACWithHeaderFile( + IN PDM_ODM_T pDM_Odm + ) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("===>ODM_ConfigMACWithHeaderFile (%s)\n", (pDM_Odm->bIsMPChip) ? "MPChip" : "TestChip")); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, + ("pDM_Odm->SupportPlatform: 0x%X, pDM_Odm->SupportInterface: 0x%X, pDM_Odm->BoardType: 0x%X\n", + pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface, pDM_Odm->BoardType)); + +//1 AP doesn't use PHYDM initialization in these ICs +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) +#if (RTL8723A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8723A){ + READ_AND_CONFIG_MP(8723A,_MAC_REG); + } +#endif +#if (RTL8812A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8812){ + READ_AND_CONFIG_MP(8812A,_MAC_REG); + } +#endif +#if (RTL8821A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8821){ + READ_AND_CONFIG_MP(8821A,_MAC_REG); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("<===8821_ODM_ConfigMACwithHeaderFile\n")); + } +#endif +#if (RTL8723B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8723B){ + READ_AND_CONFIG_MP(8723B,_MAC_REG); + } +#endif +#if (RTL8192E_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8192E){ + READ_AND_CONFIG_MP(8192E,_MAC_REG); + } +#endif +#endif//(DM_ODM_SUPPORT_TYPE != ODM_AP) + +//1 All platforms support +#if (RTL8188E_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8188E){ + READ_AND_CONFIG_MP(8188E,_MAC_REG); + } +#endif +#if (RTL8814A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8814A){ + READ_AND_CONFIG_MP(8814A,_MAC_REG); + } +#endif +#if (RTL8703B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8703B) + READ_AND_CONFIG_MP(8703B, _MAC_REG); +#endif + +#if (RTL8188F_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8188F) + READ_AND_CONFIG_MP(8188F, _MAC_REG); +#endif + +//1 New ICs (WIN only) +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (RTL8821B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8821B){ + READ_AND_CONFIG(8821B,_MAC_REG); + } +#endif +#if (RTL8822B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8822B) + READ_AND_CONFIG_MP(8822B, _MAC_REG); +#endif + +#if ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) +#if (RTL8188F_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8188F) + READ_AND_CONFIG_TC(8188F,_MAC_REG); +#endif +#endif +#if (RTL8195A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8195A) + READ_AND_CONFIG_MP(8195A,_MAC_REG); +#endif +#endif /*#if (DM_ODM_SUPPORT_TYPE & ODM_WIN)*/ + + return HAL_STATUS_SUCCESS; +} + +u4Byte +ODM_GetHWImgVersion( + IN PDM_ODM_T pDM_Odm + ) +{ + u4Byte Version=0; + +//1 AP doesn't use PHYDM initialization in these ICs +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) +#if (RTL8723A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8723A) + Version = GET_VERSION_MP(8723A,_MAC_REG); +#endif +#if (RTL8723B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8723B) + Version = GET_VERSION_MP(8723B,_MAC_REG); +#endif +#if (RTL8821A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8821) + Version = GET_VERSION_MP(8821A,_MAC_REG); +#endif +#if (RTL8192E_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8192E) + Version = GET_VERSION_MP(8192E,_MAC_REG); +#endif +#if (RTL8812A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8812) + Version = GET_VERSION_MP(8812A,_MAC_REG); +#endif +#endif //(DM_ODM_SUPPORT_TYPE != ODM_AP) + +/*1 All platforms support*/ +#if (RTL8188E_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8188E) + Version = GET_VERSION_MP(8188E,_MAC_REG); +#endif +#if (RTL8814A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8814A) + Version = GET_VERSION_MP(8814A,_MAC_REG); +#endif +#if (RTL8703B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8703B) + Version = GET_VERSION_MP(8703B, _MAC_REG); +#endif +#if (RTL8188F_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8188F) + Version = GET_VERSION_MP(8188F, _MAC_REG); +#endif + +//1 New ICs (WIN only) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if (RTL8821B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8821B) + Version = GET_VERSION(8821B,_MAC_REG); +#endif +#if (RTL8822B_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8822B) + Version = GET_VERSION(8822B, _MAC_REG); +#endif +#if ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) +#if (RTL8188F_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8188F) + Version = GET_VERSION_TC(8188F, _MAC_REG); +#endif +#endif +#endif //(DM_ODM_SUPPORT_TYPE == ODM_WIN) + + return Version; +} + +#if (RTL8822B_SUPPORT == 1) +/* For 8822B only!! need to move to FW finally */ +/*==============================================*/ + +VOID +phydm_ResetPhyInfo( + IN PDM_ODM_T pPhydm, + OUT PODM_PHY_INFO_T pPhyInfo +) +{ + pPhyInfo->RxPWDBAll = 0; + pPhyInfo->SignalQuality = 0; + pPhyInfo->BandWidth = 0; +#if (RTL8822B_SUPPORT == 1) + pPhyInfo->RxCount = 0; +#endif + ODM_Memory_Set(pPhydm, pPhyInfo->RxMIMOSignalQuality, 0 , 4); + ODM_Memory_Set(pPhydm, pPhyInfo->RxMIMOSignalStrength, 0, 4); + ODM_Memory_Set(pPhydm, pPhyInfo->RxSNR, 0, 4); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + pPhyInfo->RxPower = -110; + pPhyInfo->RecvSignalPower = -110; + pPhyInfo->BTRxRSSIPercentage = 0; + pPhyInfo->SignalStrength = 0; + pPhyInfo->btCoexPwrAdjust = 0; +#if (RTL8822B_SUPPORT == 1) + pPhyInfo->channel = 0; + pPhyInfo->bMuPacket = 0; + pPhyInfo->bBeamformed = 0; + pPhyInfo->rxsc = 0; +#endif + ODM_Memory_Set(pPhydm, pPhyInfo->RxPwr, -110, 4); + ODM_Memory_Set(pPhydm, pPhyInfo->RxMIMOEVMdbm, 0, 4); + ODM_Memory_Set(pPhydm, pPhyInfo->Cfo_short, 0, 8); + ODM_Memory_Set(pPhydm, pPhyInfo->Cfo_tail, 0, 8); +#endif +} + +VOID +phydm_SetPerPathPhyInfo( + IN u1Byte RxPath, + IN s1Byte RxPwr, + IN s1Byte RxEVM, + IN s1Byte Cfo_tail, + IN s1Byte RxSNR, + OUT PODM_PHY_INFO_T pPhyInfo +) +{ + u1Byte EVMdBm = 0; + u1Byte EVMPercentage = 0; + + /* SNR is S(8,1), EVM is S(8,1), CFO is S(8,7) */ + + if (RxEVM < 0) { + /* Calculate EVM in dBm */ + EVMdBm = ((u1Byte)(0 - RxEVM) >> 1); + + /* Calculate EVM in percentage */ + if (EVMdBm >= 33) + EVMPercentage = 100; + else + EVMPercentage = (EVMdBm << 1) + (EVMdBm); + } + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + pPhyInfo->RxPwr[RxPath] = RxPwr; + pPhyInfo->RxMIMOEVMdbm[RxPath] = EVMdBm; + + /* CFO = CFO_tail * 312.5 / 2^7 ~= CFO tail * 39/512 (kHz)*/ + pPhyInfo->Cfo_tail[RxPath] = Cfo_tail; + pPhyInfo->Cfo_tail[RxPath] = ((pPhyInfo->Cfo_tail[RxPath] << 5) + (pPhyInfo->Cfo_tail[RxPath] << 2) + + (pPhyInfo->Cfo_tail[RxPath] << 1) + (pPhyInfo->Cfo_tail[RxPath])) >> 9; +#endif + + pPhyInfo->RxMIMOSignalStrength[RxPath] = odm_QueryRxPwrPercentage(RxPwr); + pPhyInfo->RxMIMOSignalQuality[RxPath] = EVMPercentage; + pPhyInfo->RxSNR[RxPath] = RxSNR >> 1; + +/* + //if (pPktinfo->bPacketMatchBSSID) + { + DbgPrint("Path (%d)--------\n", RxPath); + DbgPrint("RxPwr = %d, Signal strength = %d\n", pPhyInfo->RxPwr[RxPath], pPhyInfo->RxMIMOSignalStrength[RxPath]); + DbgPrint("EVMdBm = %d, Signal quality = %d\n", pPhyInfo->RxMIMOEVMdbm[RxPath], pPhyInfo->RxMIMOSignalQuality[RxPath]); + DbgPrint("CFO = %d, SNR = %d\n", pPhyInfo->Cfo_tail[RxPath], pPhyInfo->RxSNR[RxPath]); + } +*/ +} + +VOID +phydm_SetCommonPhyInfo( + IN s1Byte RxPower, + IN u1Byte channel, + IN BOOLEAN bBeamformed, + IN BOOLEAN bMuPacket, + IN u1Byte bandwidth, + IN u1Byte signalQuality, + IN u1Byte rxsc, + OUT PODM_PHY_INFO_T pPhyInfo +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + pPhyInfo->RxPower = RxPower; /* RSSI in dB */ + pPhyInfo->RecvSignalPower = RxPower; /* RSSI in dB */ + pPhyInfo->channel = channel; /* channel number */ + pPhyInfo->bBeamformed = bBeamformed; /* apply BF */ + pPhyInfo->bMuPacket = bMuPacket; /* MU packet */ + pPhyInfo->rxsc = rxsc; +#endif + pPhyInfo->RxPWDBAll = odm_QueryRxPwrPercentage(RxPower); /* RSSI in percentage */ + pPhyInfo->SignalQuality = signalQuality; /* signal quality */ + pPhyInfo->BandWidth = bandwidth; /* bandwidth */ + +/* + //if (pPktinfo->bPacketMatchBSSID) + { + DbgPrint("RxPWDBAll = %d, RxPower = %d, RecvSignalPower = %d\n", pPhyInfo->RxPWDBAll, pPhyInfo->RxPower, pPhyInfo->RecvSignalPower); + DbgPrint("SignalQuality = %d\n", pPhyInfo->SignalQuality); + DbgPrint("bBeamformed = %d, bMuPacket = %d, RxCount = %d\n", pPhyInfo->bBeamformed, pPhyInfo->bMuPacket, pPhyInfo->RxCount + 1); + DbgPrint("channel = %d, rxsc = %d, BandWidth = %d\n", channel, rxsc, bandwidth); + } +*/ +} + +VOID +phydm_GetRxPhyStatusType0( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo, + OUT PODM_PHY_INFO_T pPhyInfo +) +{ + /* Type 0 is used for cck packet */ + + PPHY_STATUS_RPT_JAGUAR2_TYPE0 pPhyStaRpt = (PPHY_STATUS_RPT_JAGUAR2_TYPE0)pPhyStatus; + u1Byte i, SQ = 0; + + /* Calculate Signal Quality*/ + if (pPktinfo->bPacketMatchBSSID) { + if (pPhyStaRpt->signal_quality >= 64) + SQ = 0; + else if (pPhyStaRpt->signal_quality <= 20) + SQ = 100; + else { + /* mapping to 2~99% */ + SQ = 64 - pPhyStaRpt->signal_quality; + SQ = ((SQ << 3) + SQ) >> 2; + } + } + + /* Update CCK packet counter */ + pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK++; + + /* Update Common information */ + phydm_SetCommonPhyInfo((pPhyStaRpt->pwdb - 110), pPhyStaRpt->channel, FALSE, + FALSE, ODM_BW20M, SQ, pPhyStaRpt->rxsc, pPhyInfo); + + /* Update CCK pwdb */ + phydm_SetPerPathPhyInfo(ODM_RF_PATH_A, (pPhyStaRpt->pwdb - 110), 0, 0, 0, pPhyInfo); /* Update per-path information */ + +/* + //if (pPktinfo->bPacketMatchBSSID) + { + DbgPrint("pwdb = 0x%x, MP gain index = 0x%x, TRSW = 0x%x\n", pPhyStaRpt->pwdb, pPhyStaRpt->gain, pPhyStaRpt->trsw); + DbgPrint("channel = %d, band = %d, rxsc = %d\n", pPhyStaRpt->channel, pPhyStaRpt->band, pPhyStaRpt->rxsc); + DbgPrint("agc_table = 0x%x, agc_rpt 0x%x, bb_power = 0x%x\n", pPhyStaRpt->agc_table, pPhyStaRpt->agc_rpt, pPhyStaRpt->bb_power); + DbgPrint("length = %d, SQ = %d\n", pPhyStaRpt->length, pPhyStaRpt->signal_quality); + DbgPrint("antidx a = 0x%x, b = 0x%x, c = 0x%x, d = 0x%x\n", pPhyStaRpt->antidx_a, pPhyStaRpt->antidx_b, pPhyStaRpt->antidx_c, pPhyStaRpt->antidx_d); + DbgPrint("rsvd_0 = 0x%x, rsvd_1 = 0x%x, rsvd_2 = 0x%x\n", pPhyStaRpt->rsvd_0, pPhyStaRpt->rsvd_1, pPhyStaRpt->rsvd_2); + DbgPrint("rsvd_3 = 0x%x, rsvd_4 = 0x%x, rsvd_5 = 0x%x\n", pPhyStaRpt->rsvd_3, pPhyStaRpt->rsvd_4, pPhyStaRpt->rsvd_5); + DbgPrint("rsvd_6 = 0x%x, rsvd_7 = 0x%x, rsvd_8 = 0x%x\n", pPhyStaRpt->rsvd_6, pPhyStaRpt->rsvd_7, pPhyStaRpt->rsvd_8); + } +*/ +} + +VOID +phydm_GetRxPhyStatusType1( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo, + OUT PODM_PHY_INFO_T pPhyInfo +) +{ + /* Type 1 is used for ofdm packet */ + + PPHY_STATUS_RPT_JAGUAR2_TYPE1 pPhyStaRpt = (PPHY_STATUS_RPT_JAGUAR2_TYPE1)pPhyStatus; + s1Byte rx_pwr_db = -120; + u1Byte i, rxsc, bw, RxCount = 0; + BOOLEAN bMU; + + /* Update OFDM packet counter */ + pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM++; + + /* Update per-path information */ + for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { + if (pDM_Odm->RXAntStatus & BIT(i)) { + s1Byte rx_path_pwr_db; + + /* RX path counter */ + RxCount++; + + /* Update per-path information (RSSI_dB RSSI_percentage EVM SNR CFO SQ) */ + /* EVM report is reported by stream, not path */ + rx_path_pwr_db = pPhyStaRpt->pwdb[i] - 110; /* per-path pwdb in dB domain */ + phydm_SetPerPathPhyInfo(i, rx_path_pwr_db, pPhyStaRpt->rxevm[RxCount - 1], + pPhyStaRpt->cfo_tail[i], pPhyStaRpt->rxsnr[i], pPhyInfo); + + /* search maximum pwdb */ + if (rx_path_pwr_db > rx_pwr_db) + rx_pwr_db = rx_path_pwr_db; + } + } + + /* mapping RX counter from 1~4 to 0~3 */ + if (RxCount > 0) + pPhyInfo->RxCount = RxCount - 1; + + /* Check if MU packet or not */ + if ((pPhyStaRpt->gid != 0) && (pPhyStaRpt->gid != 63)) { + bMU = TRUE; + pDM_Odm->PhyDbgInfo.NumQryMuPkt++; + } else + bMU = FALSE; + + /* Count BF packet */ + pDM_Odm->PhyDbgInfo.NumQryBfPkt = pDM_Odm->PhyDbgInfo.NumQryBfPkt + pPhyStaRpt->beamformed; + + /* Check sub-channel */ + if ((pPktinfo->DataRate > ODM_RATE11M) && (pPktinfo->DataRate < ODM_RATEMCS0)) + rxsc = pPhyStaRpt->l_rxsc; + else + rxsc = pPhyStaRpt->ht_rxsc; + + /* Check RX bandwidth */ + if ((rxsc >= 1) && (rxsc <= 8)) + bw = ODM_BW20M; + else if ((rxsc >= 9) && (rxsc <= 12)) + bw = ODM_BW40M; + else if (rxsc >= 13) + bw = ODM_BW80M; + else + bw = pPhyStaRpt->rf_mode; + + /* Update packet information */ + phydm_SetCommonPhyInfo(rx_pwr_db, pPhyStaRpt->channel, (BOOLEAN)pPhyStaRpt->beamformed, + bMU, bw, odm_EVMdbToPercentage(pPhyStaRpt->rxevm[0]), rxsc, pPhyInfo); + +/* + //if (pPktinfo->bPacketMatchBSSID) + { + DbgPrint("channel = %d, band = %d, l_rxsc = %d, ht_rxsc = %d, rf_mode = %d\n", pPhyStaRpt->channel, pPhyStaRpt->band, pPhyStaRpt->l_rxsc, pPhyStaRpt->ht_rxsc, pPhyStaRpt->rf_mode); + DbgPrint("Antidx A = %d, B = %d, C = %d, D = %d\n", pPhyStaRpt->antidx_a, pPhyStaRpt->antidx_b, pPhyStaRpt->antidx_c, pPhyStaRpt->antidx_d); + DbgPrint("pwdb A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->pwdb[0], pPhyStaRpt->pwdb[1], pPhyStaRpt->pwdb[2], pPhyStaRpt->pwdb[3]); + DbgPrint("EVM A: %d, B: %d, C: %d, D: %d\n", pPhyStaRpt->rxevm[0], pPhyStaRpt->rxevm[1], pPhyStaRpt->rxevm[2], pPhyStaRpt->rxevm[3]); + DbgPrint("SNR A: %d, B: %d, C: %d, D: %d\n", pPhyStaRpt->rxsnr[0], pPhyStaRpt->rxsnr[1], pPhyStaRpt->rxsnr[2], pPhyStaRpt->rxsnr[3]); + DbgPrint("CFO A: %d, B: %d, C: %d, D: %d\n", pPhyStaRpt->cfo_tail[0], pPhyStaRpt->cfo_tail[1], pPhyStaRpt->cfo_tail[2], pPhyStaRpt->cfo_tail[3]); + DbgPrint("paid = %d, gid = %d, length = %d\n", (pPhyStaRpt->paid + (pPhyStaRpt->paid_msb<<8)), pPhyStaRpt->gid, pPhyStaRpt->lsig_length); + DbgPrint("ldpc: %d, stbc: %d, bf: %d, gnt_bt: %d, antsw: %d\n", pPhyStaRpt->ldpc, pPhyStaRpt->stbc, pPhyStaRpt->beamformed, pPhyStaRpt->gnt_bt, pPhyStaRpt->hw_antsw_occu); + DbgPrint("NBI: %d, pos: %d\n", pPhyStaRpt->nb_intf_flag, (pPhyStaRpt->intf_pos + (pPhyStaRpt->intf_pos_msb<<8))); + DbgPrint("rsvd_0 = %d, rsvd_1 = %d, rsvd_2 = %d, rsvd_3 = %d, rsvd_4 = %d, rsvd_5 = %d\n", pPhyStaRpt->rsvd_0, pPhyStaRpt->rsvd_1, pPhyStaRpt->rsvd_2, pPhyStaRpt->rsvd_3, pPhyStaRpt->rsvd_4, pPhyStaRpt->rsvd_5); + } + DbgPrint("phydm_GetRxPhyStatusType1 pPktinfo->bPacketMatchBSSID = %d\n", pPktinfo->bPacketMatchBSSID); + DbgPrint("pPktinfo->DataRate = 0x%x\n", pPktinfo->DataRate); +*/ +} + +VOID +phydm_GetRxPhyStatusType2( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo, + OUT PODM_PHY_INFO_T pPhyInfo +) +{ + PPHY_STATUS_RPT_JAGUAR2_TYPE2 pPhyStaRpt = (PPHY_STATUS_RPT_JAGUAR2_TYPE2)pPhyStatus; + s1Byte rx_pwr_db = -120; + u1Byte i, rxsc, bw, RxCount = 0; + + /* Update OFDM packet counter */ + pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM++; + + /* Update per-path information */ + for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { + if (pDM_Odm->RXAntStatus & BIT(i)) { + s1Byte rx_path_pwr_db; + + /* RX path counter */ + RxCount++; + + /* Update per-path information (RSSI_dB RSSI_percentage EVM SNR CFO SQ) */ + rx_path_pwr_db = pPhyStaRpt->pwdb[i] - 110; /* per-path pwdb in dB domain */ + phydm_SetPerPathPhyInfo(i, rx_path_pwr_db, 0, 0, 0, pPhyInfo); + + /* search maximum pwdb */ + if (rx_path_pwr_db > rx_pwr_db) + rx_pwr_db = rx_path_pwr_db; + } + } + + /* mapping RX counter from 1~4 to 0~3 */ + if (RxCount > 0) + pPhyInfo->RxCount = RxCount - 1; + + /* Check RX sub-channel */ + if ((pPktinfo->DataRate > ODM_RATE11M) && (pPktinfo->DataRate < ODM_RATEMCS0)) + rxsc = pPhyStaRpt->l_rxsc; + else + rxsc = pPhyStaRpt->ht_rxsc; + + /* Check RX bandwidth */ + /* the BW information of sc=0 is useless, because there is no information of RF mode*/ + if ((rxsc >= 1) && (rxsc <= 8)) + bw = ODM_BW20M; + else if ((rxsc >= 9) && (rxsc <= 12)) + bw = ODM_BW40M; + else if (rxsc >= 13) + bw = ODM_BW80M; + else + bw = ODM_BW20M; + + /* Update packet information */ + phydm_SetCommonPhyInfo(rx_pwr_db, pPhyStaRpt->channel, (BOOLEAN)pPhyStaRpt->beamformed, + FALSE, bw, 0, rxsc, pPhyInfo); + +/* + //if (pPktinfo->bPacketMatchBSSID) + { + DbgPrint("channel = %d, band = %d, l_rxsc = %d, ht_rxsc = %d\n", pPhyStaRpt->channel, pPhyStaRpt->band, pPhyStaRpt->l_rxsc, pPhyStaRpt->ht_rxsc); + DbgPrint("pwdb A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->pwdb[0], pPhyStaRpt->pwdb[1], pPhyStaRpt->pwdb[2], pPhyStaRpt->pwdb[3]); + DbgPrint("Agc table A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->agc_table_a, pPhyStaRpt->agc_table_b, pPhyStaRpt->agc_table_c, pPhyStaRpt->agc_table_d); + DbgPrint("Gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->gain_a, pPhyStaRpt->gain_b, pPhyStaRpt->gain_c, pPhyStaRpt->gain_d); + DbgPrint("TRSW A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->trsw_a, pPhyStaRpt->trsw_b, pPhyStaRpt->trsw_c, pPhyStaRpt->trsw_d); + DbgPrint("AAGC step A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->aagc_step_a, pPhyStaRpt->aagc_step_b, pPhyStaRpt->aagc_step_c, pPhyStaRpt->aagc_step_d); + DbgPrint("HT AAGC gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->ht_aagc_gain[0], pPhyStaRpt->ht_aagc_gain[1], pPhyStaRpt->ht_aagc_gain[2], pPhyStaRpt->ht_aagc_gain[3]); + DbgPrint("DAGC gain A: 0x%x, B: 0x%x, C: 0x%x, D: 0x%x\n", pPhyStaRpt->dagc_gain[0], pPhyStaRpt->dagc_gain[1], pPhyStaRpt->dagc_gain[2], pPhyStaRpt->dagc_gain[3]); + DbgPrint("ldpc: %d, stbc: %d, bf: %d, gnt_bt: %d, antsw: %d\n", pPhyStaRpt->ldpc, pPhyStaRpt->stbc, pPhyStaRpt->beamformed, pPhyStaRpt->gnt_bt, pPhyStaRpt->hw_antsw_occu); + DbgPrint("counter: %d, syn_count: %d\n", pPhyStaRpt->counter, pPhyStaRpt->syn_count); + DbgPrint("cnt_cca2agc_rdy: %d, cnt_pw2cca: %d, shift_l_map\n", pPhyStaRpt->cnt_cca2agc_rdy, pPhyStaRpt->cnt_pw2cca, pPhyStaRpt->shift_l_map); + DbgPrint("rsvd_0 = %d, rsvd_1 = %d, rsvd_2 = %d, rsvd_3 = %d, rsvd_4 = %d, rsvd_5 = %d\n", pPhyStaRpt->rsvd_0, pPhyStaRpt->rsvd_1, pPhyStaRpt->rsvd_2, pPhyStaRpt->rsvd_3, pPhyStaRpt->rsvd_4); + DbgPrint("rsvd_5 = %d, rsvd_6 = %d, rsvd_6 = %d\n", pPhyStaRpt->rsvd_5, pPhyStaRpt->rsvd_6, pPhyStaRpt->rsvd_7); + } +*/ +} + +VOID +phydm_GetRxPhyStatusType5( + IN pu1Byte pPhyStatus +) +{ +/* + DbgPrint("DW0: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 3), *(pPhyStatus + 2), *(pPhyStatus + 1), *(pPhyStatus + 0)); + DbgPrint("DW1: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 7), *(pPhyStatus + 6), *(pPhyStatus + 5), *(pPhyStatus + 4)); + DbgPrint("DW2: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 11), *(pPhyStatus + 10), *(pPhyStatus + 9), *(pPhyStatus + 8)); + DbgPrint("DW3: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 15), *(pPhyStatus + 14), *(pPhyStatus + 13), *(pPhyStatus + 12)); + DbgPrint("DW4: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 19), *(pPhyStatus + 18), *(pPhyStatus + 17), *(pPhyStatus + 16)); + DbgPrint("DW5: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 23), *(pPhyStatus + 22), *(pPhyStatus + 21), *(pPhyStatus + 20)); + DbgPrint("DW6: 0x%02x%02x%02x%02x\n", *(pPhyStatus + 27), *(pPhyStatus + 26), *(pPhyStatus + 25), *(pPhyStatus + 24)); +*/ +} + +VOID +phydm_Process_RSSIForDM_Jaguar2( + IN OUT PDM_ODM_T pDM_Odm, + IN PODM_PHY_INFO_T pPhyInfo, + IN PODM_PACKET_INFO_T pPktinfo + ) +{ + u4Byte UndecoratedSmoothedPWDB, RSSI_Ave; + u1Byte i; + PSTA_INFO_T pEntry; + + if (pPktinfo->StationID >= ODM_ASSOCIATE_ENTRY_NUM) + return; + + pEntry = pDM_Odm->pODM_StaInfo[pPktinfo->StationID]; + + if (!IS_STA_VALID(pEntry)) + return; + + if ((!pPktinfo->bPacketMatchBSSID))/*data frame only*/ + return; + + if (pPktinfo->bPacketBeacon) + pDM_Odm->PhyDbgInfo.NumQryBeaconPkt++; + + if (pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon) { + u4Byte RSSI_linear = 0; + + UndecoratedSmoothedPWDB = (u4Byte)pEntry->rssi_stat.UndecoratedSmoothedPWDB; + pDM_Odm->RSSI_A = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_A]; + pDM_Odm->RSSI_B = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_B]; + pDM_Odm->RSSI_C = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_C]; + pDM_Odm->RSSI_D = pPhyInfo->RxMIMOSignalStrength[ODM_RF_PATH_D]; + + for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_MAX_JAGUAR; i++) { + if (pPhyInfo->RxMIMOSignalStrength[i] != 0) + RSSI_linear += odm_ConvertTo_linear(pPhyInfo->RxMIMOSignalStrength[i]); + } + + switch (pPhyInfo->RxCount + 1) { + case 2: + RSSI_linear = (RSSI_linear >> 1); + break; + case 3: + RSSI_linear = ((RSSI_linear) + (RSSI_linear << 1) + (RSSI_linear << 3)) >> 5; /* RSSI_linear/3 ~ RSSI_linear*11/32 */ + break; + case 4: + RSSI_linear = (RSSI_linear >> 2); + break; + } + RSSI_Ave = odm_ConvertTo_dB(RSSI_linear); + + if (UndecoratedSmoothedPWDB <= 0) + UndecoratedSmoothedPWDB = pPhyInfo->RxPWDBAll; + else + UndecoratedSmoothedPWDB = (RSSI_Ave + ((UndecoratedSmoothedPWDB<<4) - UndecoratedSmoothedPWDB))>>4; + + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (pEntry->rssi_stat.UndecoratedSmoothedPWDB == -1) + phydm_ra_rssi_rpt_wk(pDM_Odm); + #endif + + pEntry->rssi_stat.UndecoratedSmoothedPWDB = (s4Byte)UndecoratedSmoothedPWDB; + } +} + +VOID +phydm_RxPhyStatusJaguarSeries2( + IN PDM_ODM_T pPhydm, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo, + OUT PODM_PHY_INFO_T pPhyInfo +) +{ + u1Byte phy_status_type = (*pPhyStatus & 0xf); + + /*DbgPrint("phydm_RxPhyStatusJaguarSeries2================> (page: %d)\n", phy_status_type);*/ + + /* Memory reset */ + phydm_ResetPhyInfo(pPhydm, pPhyInfo); + + /* Phy status parsing */ + switch (phy_status_type) { + case 0: + { + phydm_GetRxPhyStatusType0(pPhydm, pPhyStatus, pPktinfo, pPhyInfo); + break; + } + case 1: + { + phydm_GetRxPhyStatusType1(pPhydm, pPhyStatus, pPktinfo, pPhyInfo); + break; + } + case 2: + { + phydm_GetRxPhyStatusType2(pPhydm, pPhyStatus, pPktinfo, pPhyInfo); + break; + } + case 5: + { + phydm_GetRxPhyStatusType5(pPhyStatus); + return; + } + default: + return; + } + + /* Update signal strength to UI, and pPhyInfo->RxPWDBAll is the maximum RSSI of all path */ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + pPhyInfo->SignalStrength = SignalScaleProc(pPhydm->Adapter, pPhyInfo->RxPWDBAll, FALSE, FALSE); +#else + pPhyInfo->SignalStrength = (u1Byte)(odm_SignalScaleMapping(pPhydm, pPhyInfo->RxPWDBAll)); +#endif + + /* Calculate average RSSI and smoothed RSSI */ + phydm_Process_RSSIForDM_Jaguar2(pPhydm, pPhyInfo, pPktinfo); + +} +/*==============================================*/ +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_hwconfig.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_hwconfig.h new file mode 100644 index 000000000..7a95f4302 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_hwconfig.h @@ -0,0 +1,499 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __HALHWOUTSRC_H__ +#define __HALHWOUTSRC_H__ + + +/*--------------------------Define -------------------------------------------*/ + +#define AGC_DIFF_CONFIG_MP(ic, band) (ODM_ReadAndConfig_MP_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_MP_##ic##_AGC_TAB_DIFF_##band, \ + sizeof(Array_MP_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte))) +#define AGC_DIFF_CONFIG_TC(ic, band) (ODM_ReadAndConfig_TC_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_TC_##ic##_AGC_TAB_DIFF_##band, \ + sizeof(Array_TC_##ic##_AGC_TAB_DIFF_##band)/sizeof(u4Byte))) + +#define AGC_DIFF_CONFIG(ic, band) do {\ + if (pDM_Odm->bIsMPChip)\ + AGC_DIFF_CONFIG_MP(ic,band);\ + else\ + AGC_DIFF_CONFIG_TC(ic,band);\ + } while(0) + + +//============================================================ +// structure and define +//============================================================ + +__PACK typedef struct _Phy_Rx_AGC_Info +{ + #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte gain:7,trsw:1; + #else + u1Byte trsw:1,gain:7; + #endif +} __WLAN_ATTRIB_PACK__ PHY_RX_AGC_INFO_T, *pPHY_RX_AGC_INFO_T; + +__PACK typedef struct _Phy_Status_Rpt_8192cd { + PHY_RX_AGC_INFO_T path_agc[2]; + u1Byte ch_corr[2]; + u1Byte cck_sig_qual_ofdm_pwdb_all; + u1Byte cck_agc_rpt_ofdm_cfosho_a; + u1Byte cck_rpt_b_ofdm_cfosho_b; + u1Byte rsvd_1;/*ch_corr_msb;*/ + u1Byte noise_power_db_msb; + s1Byte path_cfotail[2]; + u1Byte pcts_mask[2]; + s1Byte stream_rxevm[2]; + u1Byte path_rxsnr[2]; + u1Byte noise_power_db_lsb; + u1Byte rsvd_2[3]; + u1Byte stream_csi[2]; + u1Byte stream_target_csi[2]; + s1Byte sig_evm; + u1Byte rsvd_3; + +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte antsel_rx_keep_2: 1; /*ex_intf_flg:1;*/ + u1Byte sgi_en: 1; + u1Byte rxsc: 2; + u1Byte idle_long: 1; + u1Byte r_ant_train_en: 1; + u1Byte ant_sel_b: 1; + u1Byte ant_sel: 1; +#else /*_BIG_ENDIAN_ */ + u1Byte ant_sel: 1; + u1Byte ant_sel_b: 1; + u1Byte r_ant_train_en: 1; + u1Byte idle_long: 1; + u1Byte rxsc: 2; + u1Byte sgi_en: 1; + u1Byte antsel_rx_keep_2: 1;/*ex_intf_flg:1;*/ +#endif +} __WLAN_ATTRIB_PACK__ PHY_STATUS_RPT_8192CD_T, *PPHY_STATUS_RPT_8192CD_T; + + +typedef struct _Phy_Status_Rpt_8812 { +/* DWORD 0*/ + u1Byte gain_trsw[2]; /*path-A and path-B {TRSW, gain[6:0] }*/ + u1Byte chl_num_LSB; /*channel number[7:0]*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte chl_num_MSB: 2; /*channel number[9:8]*/ + u1Byte sub_chnl: 4; /*sub-channel location[3:0]*/ + u1Byte r_RFMOD: 2; /*RF mode[1:0]*/ +#else /*_BIG_ENDIAN_ */ + u1Byte r_RFMOD: 2; + u1Byte sub_chnl: 4; + u1Byte chl_num_MSB: 2; +#endif + +/* DWORD 1*/ + u1Byte pwdb_all; /*CCK signal quality / OFDM pwdb all*/ + s1Byte cfosho[2]; /*DW1 byte 1 DW1 byte2 CCK AGC report and CCK_BB_Power / OFDM Path-A and Path-B short CFO*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + /*this should be checked again because the definition of 8812 and 8814 is different*/ +/* u1Byte r_cck_rx_enable_pathc:2; cck rx enable pathc[1:0]*/ +/* u1Byte cck_rx_path:4; cck rx path[3:0]*/ + u1Byte resvd_0: 6; + u1Byte bt_RF_ch_MSB: 2; /*8812A:2'b0 8814A: bt rf channel keep[7:6]*/ +#else /*_BIG_ENDIAN_*/ + u1Byte bt_RF_ch_MSB: 2; + u1Byte resvd_0: 6; +#endif + +/* DWORD 2*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte ant_div_sw_a: 1; /*8812A: ant_div_sw_a 8814A: 1'b0*/ + u1Byte ant_div_sw_b: 1; /*8812A: ant_div_sw_b 8814A: 1'b0*/ + u1Byte bt_RF_ch_LSB: 6; /*8812A: 6'b0 8814A: bt rf channel keep[5:0]*/ +#else /*_BIG_ENDIAN_ */ + u1Byte bt_RF_ch_LSB: 6; + u1Byte ant_div_sw_b: 1; + u1Byte ant_div_sw_a: 1; +#endif + s1Byte cfotail[2]; /*DW2 byte 1 DW2 byte 2 path-A and path-B CFO tail*/ + u1Byte PCTS_MSK_RPT_0; /*PCTS mask report[7:0]*/ + u1Byte PCTS_MSK_RPT_1; /*PCTS mask report[15:8]*/ + +/* DWORD 3*/ + s1Byte rxevm[2]; /*DW3 byte 1 DW3 byte 2 stream 1 and stream 2 RX EVM*/ + s1Byte rxsnr[2]; /*DW3 byte 3 DW4 byte 0 path-A and path-B RX SNR*/ + +/* DWORD 4*/ + u1Byte PCTS_MSK_RPT_2; /*PCTS mask report[23:16]*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte PCTS_MSK_RPT_3: 6; /*PCTS mask report[29:24]*/ + u1Byte pcts_rpt_valid: 1; /*pcts_rpt_valid*/ + u1Byte resvd_1: 1; /*1'b0*/ +#else /*_BIG_ENDIAN_*/ + u1Byte resvd_1: 1; + u1Byte pcts_rpt_valid: 1; + u1Byte PCTS_MSK_RPT_3: 6; +#endif + s1Byte rxevm_cd[2]; /*DW 4 byte 3 DW5 byte 0 8812A: 16'b0 8814A: stream 3 and stream 4 RX EVM*/ + +/* DWORD 5*/ + u1Byte csi_current[2]; /*DW5 byte 1 DW5 byte 2 8812A: stream 1 and 2 CSI 8814A: path-C and path-D RX SNR*/ + u1Byte gain_trsw_cd[2]; /*DW5 byte 3 DW6 byte 0 path-C and path-D {TRSW, gain[6:0] }*/ + +/* DWORD 6*/ + s1Byte sigevm; /*signal field EVM*/ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte antidx_antc: 3; /*8812A: 3'b0 8814A: antidx_antc[2:0]*/ + u1Byte antidx_antd: 3; /*8812A: 3'b0 8814A: antidx_antd[2:0]*/ + u1Byte dpdt_ctrl_keep: 1; /*8812A: 1'b0 8814A: dpdt_ctrl_keep*/ + u1Byte GNT_BT_keep: 1; /*8812A: 1'b0 8814A: GNT_BT_keep*/ +#else /*_BIG_ENDIAN_*/ + u1Byte GNT_BT_keep: 1; + u1Byte dpdt_ctrl_keep: 1; + u1Byte antidx_antd: 3; + u1Byte antidx_antc: 3; +#endif +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte antidx_anta: 3; /*antidx_anta[2:0]*/ + u1Byte antidx_antb: 3; /*antidx_antb[2:0]*/ + u1Byte hw_antsw_occur: 2; /*1'b0*/ +#else /*_BIG_ENDIAN_*/ + u1Byte hw_antsw_occur: 2; + u1Byte antidx_antb: 3; + u1Byte antidx_anta: 3; +#endif +} PHY_STATUS_RPT_8812_T, *PPHY_STATUS_RPT_8812_T; + +VOID +odm_Init_RSSIForDM( + IN OUT PDM_ODM_T pDM_Odm + ); + +VOID +ODM_PhyStatusQuery( + IN OUT PDM_ODM_T pDM_Odm, + OUT PODM_PHY_INFO_T pPhyInfo, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo + ); + +VOID +ODM_MacStatusQuery( + IN OUT PDM_ODM_T pDM_Odm, + IN pu1Byte pMacStatus, + IN u1Byte MacID, + IN BOOLEAN bPacketMatchBSSID, + IN BOOLEAN bPacketToSelf, + IN BOOLEAN bPacketBeacon + ); + +HAL_STATUS +ODM_ConfigRFWithTxPwrTrackHeaderFile( + IN PDM_ODM_T pDM_Odm + ); + +HAL_STATUS +ODM_ConfigRFWithHeaderFile( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_Config_Type ConfigType, + IN ODM_RF_RADIO_PATH_E eRFPath + ); + +HAL_STATUS +ODM_ConfigBBWithHeaderFile( + IN PDM_ODM_T pDM_Odm, + IN ODM_BB_Config_Type ConfigType + ); + +HAL_STATUS +ODM_ConfigMACWithHeaderFile( + IN PDM_ODM_T pDM_Odm + ); + + +u4Byte +ODM_GetHWImgVersion( + IN PDM_ODM_T pDM_Odm + ); + +s4Byte +odm_SignalScaleMapping( + IN OUT PDM_ODM_T pDM_Odm, + IN s4Byte CurrSig + ); + +#if (RTL8822B_SUPPORT == 1) +/*For 8822B only!! need to move to FW finally */ +/*==============================================*/ +VOID +phydm_RxPhyStatusJaguarSeries2( + IN PDM_ODM_T pPhydm, + IN pu1Byte pPhyStatus, + IN PODM_PACKET_INFO_T pPktinfo, + OUT PODM_PHY_INFO_T pPhyInfo +); + +typedef struct _Phy_Status_Rpt_Jaguar2_Type0 { + /* DW0 */ + u1Byte page_num; + u1Byte pwdb; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte gain: 6; + u1Byte rsvd_0: 1; + u1Byte trsw: 1; +#else + u1Byte trsw: 1; + u1Byte rsvd_0: 1; + u1Byte gain: 6; +#endif + u1Byte rsvd_1; + + /* DW1 */ + u1Byte rsvd_2; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte rxsc: 4; + u1Byte agc_table: 4; +#else + u1Byte agc_table: 4; + u1Byte rxsc: 4; +#endif + u1Byte channel; + u1Byte band; + + /* DW2 */ + u2Byte length; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte antidx_a: 3; + u1Byte antidx_b: 3; + u1Byte rsvd_3: 2; + u1Byte antidx_c: 3; + u1Byte antidx_d: 3; + u1Byte rsvd_4:2; +#else + u1Byte rsvd_3: 2; + u1Byte antidx_b: 3; + u1Byte antidx_a: 3; + u1Byte rsvd_4:2; + u1Byte antidx_d: 3; + u1Byte antidx_c: 3; +#endif + + /* DW3 */ + u1Byte signal_quality; + u1Byte agc_rpt; + u1Byte bb_power; + u1Byte rsvd_5; + + /* DW4 */ + u4Byte rsvd_6; + + /* DW5 */ + u4Byte rsvd_7; + + /* DW6 */ + u4Byte rsvd_8; +} PHY_STATUS_RPT_JAGUAR2_TYPE0, *PPHY_STATUS_RPT_JAGUAR2_TYPE0; + +typedef struct _Phy_Status_Rpt_Jaguar2_Type1 { + /* DW0 and DW1 */ + u1Byte page_num; + u1Byte pwdb[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte l_rxsc: 4; + u1Byte ht_rxsc: 4; +#else + u1Byte ht_rxsc: 4; + u1Byte l_rxsc: 4; +#endif + u1Byte channel; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte band: 2; + u1Byte rsvd_0: 1; + u1Byte hw_antsw_occu: 1; + u1Byte gnt_bt: 1; + u1Byte ldpc: 1; + u1Byte stbc: 1; + u1Byte beamformed: 1; +#else + u1Byte beamformed: 1; + u1Byte stbc: 1; + u1Byte ldpc: 1; + u1Byte gnt_bt: 1; + u1Byte hw_antsw_occu: 1; + u1Byte rsvd_0: 1; + u1Byte band: 2; +#endif + + /* DW2 */ + u2Byte lsig_length; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte antidx_a: 3; + u1Byte antidx_b: 3; + u1Byte rsvd_1: 2; + u1Byte antidx_c: 3; + u1Byte antidx_d: 3; + u1Byte rsvd_2: 2; +#else + u1Byte rsvd_1: 2; + u1Byte antidx_b: 3; + u1Byte antidx_a: 3; + u1Byte rsvd_2: 2; + u1Byte antidx_d: 3; + u1Byte antidx_c: 3; +#endif + + /* DW3 */ + u1Byte paid; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte paid_msb: 1; + u1Byte gid: 6; + u1Byte rsvd_3: 1; +#else + u1Byte rsvd_3: 1; + u1Byte gid: 6; + u1Byte paid_msb: 1; +#endif + u1Byte intf_pos; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte intf_pos_msb: 1; + u1Byte rsvd_4: 2; + u1Byte nb_intf_flag: 1; + u1Byte rf_mode: 2; + u1Byte rsvd_5: 2; +#else + u1Byte rsvd_5: 2; + u1Byte rf_mode: 2; + u1Byte nb_intf_flag: 1; + u1Byte rsvd_4: 2; + u1Byte intf_pos_msb: 1; +#endif + + /* DW4 */ + s1Byte rxevm[4]; /* s(8,1) */ + + /* DW5 */ + s1Byte cfo_tail[4]; /* s(8,7) */ + + /* DW6 */ + s1Byte rxsnr[4]; /* s(8,1) */ +} PHY_STATUS_RPT_JAGUAR2_TYPE1, *PPHY_STATUS_RPT_JAGUAR2_TYPE1; + +typedef struct _Phy_Status_Rpt_Jaguar2_Type2 { + /* DW0 ane DW1 */ + u1Byte page_num; + u1Byte pwdb[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte l_rxsc: 4; + u1Byte ht_rxsc: 4; +#else + u1Byte ht_rxsc: 4; + u1Byte l_rxsc: 4; +#endif + u1Byte channel; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte band: 2; + u1Byte rsvd_0: 1; + u1Byte hw_antsw_occu: 1; + u1Byte gnt_bt: 1; + u1Byte ldpc: 1; + u1Byte stbc: 1; + u1Byte beamformed: 1; +#else + u1Byte beamformed: 1; + u1Byte stbc: 1; + u1Byte ldpc: 1; + u1Byte gnt_bt: 1; + u1Byte hw_antsw_occu: 1; + u1Byte rsvd_0: 1; + u1Byte band: 2; +#endif + + /* DW2 */ +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte shift_l_map: 6; + u1Byte rsvd_1: 2; +#else + u1Byte rsvd_1: 2; + u1Byte shift_l_map: 6; +#endif + u1Byte cnt_pw2cca; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte agc_table_a: 4; + u1Byte agc_table_b: 4; + u1Byte agc_table_c: 4; + u1Byte agc_table_d: 4; +#else + u1Byte agc_table_b: 4; + u1Byte agc_table_a: 4; + u1Byte agc_table_d: 4; + u1Byte agc_table_c: 4; +#endif + + /* DW3 ~ DW6*/ + u1Byte cnt_cca2agc_rdy; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte gain_a: 6; + u1Byte rsvd_2: 1; + u1Byte trsw_a: 1; + u1Byte gain_b: 6; + u1Byte rsvd_3: 1; + u1Byte trsw_b: 1; + u1Byte gain_c: 6; + u1Byte rsvd_4: 1; + u1Byte trsw_c: 1; + u1Byte gain_d: 6; + u1Byte rsvd_5: 1; + u1Byte trsw_d: 1; + u1Byte aagc_step_a: 2; + u1Byte aagc_step_b: 2; + u1Byte aagc_step_c: 2; + u1Byte aagc_step_d: 2; +#else + u1Byte trsw_a: 1; + u1Byte rsvd_2: 1; + u1Byte gain_a: 6; + u1Byte trsw_b: 1; + u1Byte rsvd_3: 1; + u1Byte gain_b: 6; + u1Byte trsw_c: 1; + u1Byte rsvd_4: 1; + u1Byte gain_c: 6; + u1Byte trsw_d: 1; + u1Byte rsvd_5: 1; + u1Byte gain_d: 6; + u1Byte aagc_step_d: 2; + u1Byte aagc_step_c: 2; + u1Byte aagc_step_b: 2; + u1Byte aagc_step_a: 2; +#endif + u1Byte ht_aagc_gain[4]; + u1Byte dagc_gain[4]; +#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE) + u1Byte counter: 6; + u1Byte rsvd_6: 2; + u1Byte syn_count: 5; + u1Byte rsvd_7:3; +#else + u1Byte rsvd_6: 2; + u1Byte counter: 6; + u1Byte rsvd_7:3; + u1Byte syn_count: 5; +#endif +} PHY_STATUS_RPT_JAGUAR2_TYPE2, *PPHY_STATUS_RPT_JAGUAR2_TYPE2; +/*==============================================*/ +#endif +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_interface.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_interface.c new file mode 100644 index 000000000..7f50b3ba5 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_interface.c @@ -0,0 +1,1014 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ + +#include "mp_precomp.h" +#include "phydm_precomp.h" + +// +// ODM IO Relative API. +// + +u1Byte +ODM_Read1Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + prtl8192cd_priv priv = pDM_Odm->priv; + return RTL_R8(RegAddr); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + return rtw_read8(Adapter,RegAddr); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + return PlatformEFIORead1Byte(Adapter, RegAddr); +#endif + +} + + +u2Byte +ODM_Read2Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + prtl8192cd_priv priv = pDM_Odm->priv; + return RTL_R16(RegAddr); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + return rtw_read16(Adapter,RegAddr); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + return PlatformEFIORead2Byte(Adapter, RegAddr); +#endif + +} + + +u4Byte +ODM_Read4Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + prtl8192cd_priv priv = pDM_Odm->priv; + return RTL_R32(RegAddr); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + return rtw_read32(Adapter,RegAddr); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + return PlatformEFIORead4Byte(Adapter, RegAddr); +#endif + +} + + +VOID +ODM_Write1Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u1Byte Data + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + prtl8192cd_priv priv = pDM_Odm->priv; + RTL_W8(RegAddr, Data); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + rtw_write8(Adapter,RegAddr, Data); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformEFIOWrite1Byte(Adapter, RegAddr, Data); +#endif + +} + + +VOID +ODM_Write2Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u2Byte Data + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + prtl8192cd_priv priv = pDM_Odm->priv; + RTL_W16(RegAddr, Data); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + rtw_write16(Adapter,RegAddr, Data); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformEFIOWrite2Byte(Adapter, RegAddr, Data); +#endif + +} + + +VOID +ODM_Write4Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte Data + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + prtl8192cd_priv priv = pDM_Odm->priv; + RTL_W32(RegAddr, Data); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + rtw_write32(Adapter,RegAddr, Data); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformEFIOWrite4Byte(Adapter, RegAddr, Data); +#endif + +} + + +VOID +ODM_SetMACReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + PHY_SetBBReg(pDM_Odm->priv, RegAddr, BitMask, Data); +#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) + PADAPTER Adapter = pDM_Odm->Adapter; + PHY_SetBBReg(Adapter, RegAddr, BitMask, Data); +#endif +} + + +u4Byte +ODM_GetMACReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + return PHY_QueryBBReg(pDM_Odm->priv, RegAddr, BitMask); +#elif(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + return PHY_QueryMacReg(pDM_Odm->Adapter, RegAddr, BitMask); +#endif +} + + +VOID +ODM_SetBBReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + PHY_SetBBReg(pDM_Odm->priv, RegAddr, BitMask, Data); +#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) + PADAPTER Adapter = pDM_Odm->Adapter; + PHY_SetBBReg(Adapter, RegAddr, BitMask, Data); +#endif +} + + +u4Byte +ODM_GetBBReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + return PHY_QueryBBReg(pDM_Odm->priv, RegAddr, BitMask); +#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) + PADAPTER Adapter = pDM_Odm->Adapter; + return PHY_QueryBBReg(Adapter, RegAddr, BitMask); +#endif +} + + +VOID +ODM_SetRFReg( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_SetRFReg(pDM_Odm->priv, eRFPath, RegAddr, BitMask, Data); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data); + ODM_delay_us(2); + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PHY_SetRFReg(pDM_Odm->Adapter, eRFPath, RegAddr, BitMask, Data); +#endif +} + + +u4Byte +ODM_GetRFReg( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + return PHY_QueryRFReg(pDM_Odm->priv, eRFPath, RegAddr, BitMask, 1); +#elif(DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN)) + PADAPTER Adapter = pDM_Odm->Adapter; + return PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask); +#endif +} + + + + +// +// ODM Memory relative API. +// +VOID +ODM_AllocateMemory( + IN PDM_ODM_T pDM_Odm, + OUT PVOID *pPtr, + IN u4Byte length + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + *pPtr = kmalloc(length, GFP_ATOMIC); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) + *pPtr = rtw_zvmalloc(length); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformAllocateMemory(Adapter, pPtr, length); +#endif +} + +// length could be ignored, used to detect memory leakage. +VOID +ODM_FreeMemory( + IN PDM_ODM_T pDM_Odm, + OUT PVOID pPtr, + IN u4Byte length + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + kfree(pPtr); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) + rtw_vmfree(pPtr, length); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + //PADAPTER Adapter = pDM_Odm->Adapter; + PlatformFreeMemory(pPtr, length); +#endif +} + +VOID +ODM_MoveMemory( + IN PDM_ODM_T pDM_Odm, + OUT PVOID pDest, + IN PVOID pSrc, + IN u4Byte Length + ) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + memcpy(pDest, pSrc, Length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) + _rtw_memcpy(pDest, pSrc, Length); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformMoveMemory(pDest, pSrc, Length); +#endif +} + +void ODM_Memory_Set( + IN PDM_ODM_T pDM_Odm, + IN PVOID pbuf, + IN s1Byte value, + IN u4Byte length +) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + memset(pbuf, value, length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) + _rtw_memset(pbuf,value, length); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformFillMemory(pbuf,length,value); +#endif +} +s4Byte ODM_CompareMemory( + IN PDM_ODM_T pDM_Odm, + IN PVOID pBuf1, + IN PVOID pBuf2, + IN u4Byte length + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + return memcmp(pBuf1,pBuf2,length); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) + return _rtw_memcmp(pBuf1,pBuf2,length); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + return PlatformCompareMemory(pBuf1,pBuf2,length); +#endif +} + + + +// +// ODM MISC relative API. +// +VOID +ODM_AcquireSpinLock( + IN PDM_ODM_T pDM_Odm, + IN RT_SPINLOCK_TYPE type + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + rtw_odm_acquirespinlock(Adapter, type); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformAcquireSpinLock(Adapter, type); +#endif +} +VOID +ODM_ReleaseSpinLock( + IN PDM_ODM_T pDM_Odm, + IN RT_SPINLOCK_TYPE type + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE ) + PADAPTER Adapter = pDM_Odm->Adapter; + rtw_odm_releasespinlock(Adapter, type); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformReleaseSpinLock(Adapter, type); +#endif +} + +// +// Work item relative API. FOr MP driver only~! +// +VOID +ODM_InitializeWorkItem( + IN PDM_ODM_T pDM_Odm, + IN PRT_WORK_ITEM pRtWorkItem, + IN RT_WORKITEM_CALL_BACK RtWorkItemCallback, + IN PVOID pContext, + IN const char* szID + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformInitializeWorkItem(Adapter, pRtWorkItem, RtWorkItemCallback, pContext, szID); +#endif +} + + +VOID +ODM_StartWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformStartWorkItem(pRtWorkItem); +#endif +} + + +VOID +ODM_StopWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformStopWorkItem(pRtWorkItem); +#endif +} + + +VOID +ODM_FreeWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformFreeWorkItem(pRtWorkItem); +#endif +} + + +VOID +ODM_ScheduleWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformScheduleWorkItem(pRtWorkItem); +#endif +} + + +VOID +ODM_IsWorkItemScheduled( + IN PRT_WORK_ITEM pRtWorkItem + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformIsWorkItemScheduled(pRtWorkItem); +#endif +} + + + +// +// ODM Timer relative API. +// +VOID +ODM_StallExecution( + IN u4Byte usDelay + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + rtw_udelay_os(usDelay); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformStallExecution(usDelay); +#endif +} + +VOID +ODM_delay_ms(IN u4Byte ms) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + delay_ms(ms); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + rtw_mdelay_os(ms); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + delay_ms(ms); +#endif +} + +VOID +ODM_delay_us(IN u4Byte us) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + delay_us(us); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + rtw_udelay_os(us); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PlatformStallExecution(us); +#endif +} + +VOID +ODM_sleep_ms(IN u4Byte ms) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + rtw_msleep_os(ms); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#endif +} + +VOID +ODM_sleep_us(IN u4Byte us) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + rtw_usleep_os(us); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#endif +} + +VOID +ODM_SetTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer, + IN u4Byte msDelay + ) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + mod_timer(pTimer, jiffies + RTL_MILISECONDS_TO_JIFFIES(msDelay)); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + _set_timer(pTimer,msDelay ); //ms +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformSetTimer(Adapter, pTimer, msDelay); +#endif + +} + +VOID +ODM_InitializeTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer, + IN RT_TIMER_CALL_BACK CallBackFunc, + IN PVOID pContext, + IN const char* szID + ) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + init_timer(pTimer); + pTimer->function = CallBackFunc; + pTimer->data = (unsigned long)pDM_Odm; + mod_timer(pTimer, jiffies+RTL_MILISECONDS_TO_JIFFIES(10)); +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + _init_timer(pTimer,Adapter->pnetdev,CallBackFunc,pDM_Odm); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformInitializeTimer(Adapter, pTimer, CallBackFunc,pContext,szID); +#endif +} + + +VOID +ODM_CancelTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer + ) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + del_timer(pTimer); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + _cancel_timer_ex(pTimer); +#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PlatformCancelTimer(Adapter, pTimer); +#endif +} + + +VOID +ODM_ReleaseTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + + PADAPTER Adapter = pDM_Odm->Adapter; + + // <20120301, Kordan> If the initilization fails, InitializeAdapterXxx will return regardless of InitHalDm. + // Hence, uninitialized timers cause BSOD when the driver releases resources since the init fail. + if (pTimer == 0) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_SERIOUS, ("=====>ODM_ReleaseTimer(), The timer is NULL! Please check it!\n")); + return; + } + + PlatformReleaseTimer(Adapter, pTimer); +#endif +} + +BOOLEAN +phydm_actingDetermine( + IN PDM_ODM_T pDM_Odm, + IN PHYDM_ACTING_TYPE type + ) +{ + BOOLEAN ret = FALSE; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->BeamformingInfo.SourceAdapter; +#else + PADAPTER Adapter = pDM_Odm->Adapter; +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + if (type == PhyDM_ACTING_AS_AP) + ret = ACTING_AS_AP(Adapter); + else if (type == PhyDM_ACTING_AS_IBSS) + ret = ACTING_AS_IBSS(Adapter); +#elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + + if (type == PhyDM_ACTING_AS_AP) + ret = check_fwstate(pmlmepriv, WIFI_AP_STATE); + else if (type == PhyDM_ACTING_AS_IBSS) + ret = check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE); +#endif + + return ret; + +} + + +u1Byte +phydm_trans_h2c_id( + IN PDM_ODM_T pDM_Odm, + IN u1Byte phydm_h2c_id +) +{ + u1Byte platform_h2c_id=0xff; + + + switch(phydm_h2c_id) + { + //1 [0] + case ODM_H2C_RSSI_REPORT: + + #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + if(pDM_Odm->SupportICType == ODM_RTL8188E) + { + platform_h2c_id = H2C_88E_RSSI_REPORT; + } + else if(pDM_Odm->SupportICType == ODM_RTL8814A) + { + platform_h2c_id =H2C_8814A_RSSI_REPORT; + } + else + { + platform_h2c_id = H2C_RSSI_REPORT; + } + + #elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + platform_h2c_id = H2C_RSSI_SETTING; + + #elif(DM_ODM_SUPPORT_TYPE & ODM_AP) + #if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1)) + if (pDM_Odm->SupportICType == ODM_RTL8881A || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8814A || (pDM_Odm->SupportICType == ODM_RTL8822B)) + { + platform_h2c_id =H2C_88XX_RSSI_REPORT; + /*ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] H2C_88XX_RSSI_REPORT CMD_ID = (( %d ))\n", platform_h2c_id));*/ + } else + #endif + #if(RTL8812A_SUPPORT==1) + if(pDM_Odm->SupportICType == ODM_RTL8812) + { + platform_h2c_id = H2C_8812_RSSI_REPORT; + } else + #endif + {} + #endif + + break; + + //1 [3] + case ODM_H2C_WIFI_CALIBRATION: + #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + platform_h2c_id =H2C_WIFI_CALIBRATION; + + #elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + #if(RTL8723B_SUPPORT==1) + platform_h2c_id = H2C_8723B_BT_WLAN_CALIBRATION; + #endif + + #elif(DM_ODM_SUPPORT_TYPE & ODM_AP) + + + #endif + + break; + + + //1 [4] + case ODM_H2C_IQ_CALIBRATION: + #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + platform_h2c_id =H2C_IQ_CALIBRATION; + + #elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + #if((RTL8812A_SUPPORT==1) ||(RTL8821A_SUPPORT==1)) + platform_h2c_id = H2C_8812_IQ_CALIBRATION; + #endif + #elif(DM_ODM_SUPPORT_TYPE & ODM_AP) + + + #endif + + break; + //1 [5] + case ODM_H2C_RA_PARA_ADJUST: + + #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + if (pDM_Odm->SupportICType & (ODM_RTL8814A | ODM_RTL8822B)) + platform_h2c_id = H2C_8814A_RA_PARA_ADJUST; + else + platform_h2c_id = H2C_RA_PARA_ADJUST; + #elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + #if((RTL8812A_SUPPORT==1) ||(RTL8821A_SUPPORT==1)) + platform_h2c_id = H2C_8812_RA_PARA_ADJUST; + #elif ((RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1)) + platform_h2c_id = H2C_RA_PARA_ADJUST; + #elif(RTL8192E_SUPPORT==1) + platform_h2c_id =H2C_8192E_RA_PARA_ADJUST; + #elif(RTL8723B_SUPPORT==1) + platform_h2c_id =H2C_8723B_RA_PARA_ADJUST; + #endif + + #elif(DM_ODM_SUPPORT_TYPE & ODM_AP) + #if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1)) + if (pDM_Odm->SupportICType == ODM_RTL8881A || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8814A || (pDM_Odm->SupportICType == ODM_RTL8822B)) { + platform_h2c_id =H2C_88XX_RA_PARA_ADJUST; + /*ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] H2C_88XX_RA_PARA_ADJUST CMD_ID = (( %d ))\n", platform_h2c_id));*/ + } else + #endif + #if(RTL8812A_SUPPORT==1) + if(pDM_Odm->SupportICType == ODM_RTL8812) + { + platform_h2c_id = H2C_8812_RA_PARA_ADJUST; + } else + #endif + {} + #endif + + break; + + + //1 [6] + case PHYDM_H2C_DYNAMIC_TX_PATH: + + #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + if(pDM_Odm->SupportICType == ODM_RTL8814A) + { + platform_h2c_id =H2C_8814A_DYNAMIC_TX_PATH; + } + #elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + #if (RTL8814A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8814A) + platform_h2c_id = H2C_DYNAMIC_TX_PATH; + #endif + #elif(DM_ODM_SUPPORT_TYPE & ODM_AP) + #if(RTL8814A_SUPPORT==1) + if( pDM_Odm->SupportICType == ODM_RTL8814A) + { + platform_h2c_id = H2C_88XX_DYNAMIC_TX_PATH; + } + #endif + + #endif + + break; + + /* [7]*/ + case PHYDM_H2C_FW_TRACE_EN: + + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + if (pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_RTL8822B)) + platform_h2c_id = H2C_8814A_FW_TRACE_EN; + else + platform_h2c_id = H2C_FW_TRACE_EN; + + #elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + + + #elif(DM_ODM_SUPPORT_TYPE & ODM_AP) + #if ((RTL8881A_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8814A_SUPPORT == 1) || (RTL8822B_SUPPORT == 1)) + if (pDM_Odm->SupportICType == ODM_RTL8881A || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8814A || (pDM_Odm->SupportICType == ODM_RTL8822B)) + platform_h2c_id = H2C_88XX_FW_TRACE_EN; + else + #endif + #if (RTL8812A_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8812) { + platform_h2c_id = H2C_8812_FW_TRACE_EN; + } else + #endif + {} + + #endif + + break; + + case PHYDM_H2C_TXBF: +#if ((RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1)) + platform_h2c_id = 0x41; /*H2C_TxBF*/ +#endif + break; + + default: + platform_h2c_id=0xff; + break; + } + + return platform_h2c_id; + +} + +// +// ODM FW relative API. +// + +VOID +ODM_FillH2CCmd( + IN PDM_ODM_T pDM_Odm, + IN u1Byte phydm_h2c_id, + IN u4Byte CmdLen, + IN pu1Byte pCmdBuffer +) +{ + PADAPTER Adapter = pDM_Odm->Adapter; + u1Byte platform_h2c_id; + + platform_h2c_id=phydm_trans_h2c_id(pDM_Odm, phydm_h2c_id); + + if(platform_h2c_id==0xff) + { + ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] Wrong H2C CMD-ID !! platform_h2c_id==0xff , PHYDM_ElementID=((%d )) \n",phydm_h2c_id)); + return; + } + + #if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + if (pDM_Odm->SupportICType == ODM_RTL8188E) + if (!pDM_Odm->RaSupport88E) + FillH2CCmd88E(Adapter, platform_h2c_id, CmdLen, pCmdBuffer); + else if (pDM_Odm->SupportICType == ODM_RTL8192C) + FillH2CCmd92C(Adapter, platform_h2c_id, CmdLen, pCmdBuffer); + else if (pDM_Odm->SupportICType == ODM_RTL8814A) + FillH2CCmd8814A(Adapter, platform_h2c_id, CmdLen, pCmdBuffer); + else if (pDM_Odm->SupportICType == ODM_RTL8822B) +#if (RTL8822B_SUPPORT == 1) + FillH2CCmd8822B(Adapter, platform_h2c_id, CmdLen, pCmdBuffer); +#endif + else + FillH2CCmd(Adapter, platform_h2c_id, CmdLen, pCmdBuffer); + + #elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + rtw_hal_fill_h2c_cmd(Adapter, platform_h2c_id, CmdLen, pCmdBuffer); + + #elif(DM_ODM_SUPPORT_TYPE & ODM_AP) + #if((RTL8881A_SUPPORT==1)||(RTL8192E_SUPPORT==1)||(RTL8814A_SUPPORT==1)) + if(pDM_Odm->SupportICType == ODM_RTL8881A || pDM_Odm->SupportICType == ODM_RTL8192E|| pDM_Odm->SupportICType == ODM_RTL8814A) + { + GET_HAL_INTERFACE(pDM_Odm->priv)->FillH2CCmdHandler(pDM_Odm->priv, platform_h2c_id, CmdLen, pCmdBuffer); + //FillH2CCmd88XX(pDM_Odm->priv, platform_h2c_id, CmdLen, pCmdBuffer); + } else + #endif + #if(RTL8812A_SUPPORT==1) + if(pDM_Odm->SupportICType == ODM_RTL8812) + { + FillH2CCmd8812(pDM_Odm->priv, platform_h2c_id, CmdLen, pCmdBuffer); + } else + #endif + {} + #endif +} + +u1Byte +phydm_c2H_content_parsing( + IN PVOID pDM_VOID, + IN u1Byte c2hCmdId, + IN u1Byte c2hCmdLen, + IN pu1Byte tmpBuf +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + #endif + u1Byte Extend_c2hSubID = 0; + u1Byte find_c2h_cmd = TRUE; + + switch (c2hCmdId) { + case PHYDM_C2H_DBG: + if (pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_RTL8822B)) + phydm_fw_trace_handler(pDM_Odm, tmpBuf, c2hCmdLen); + + break; + + case PHYDM_C2H_RA_RPT: + phydm_c2h_ra_report_handler(pDM_Odm, tmpBuf, c2hCmdLen); + break; + + case PHYDM_C2H_RA_PARA_RPT: + ODM_C2HRaParaReportHandler(pDM_Odm, tmpBuf, c2hCmdLen); + break; + + case PHYDM_C2H_DYNAMIC_TX_PATH_RPT: + if (pDM_Odm->SupportICType & (ODM_RTL8814A)) + phydm_c2h_dtp_handler(pDM_Odm, tmpBuf, c2hCmdLen); + + break; + + case PHYDM_C2H_IQK_FINISH: + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + + if (pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8821)) { + + RT_TRACE(COMP_MP, DBG_LOUD, ("== FW IQK Finish ==\n")); + PlatformAcquireSpinLock(Adapter, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE; + PlatformReleaseSpinLock(Adapter, RT_IQK_SPINLOCK); + pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime = 0; + pDM_Odm->RFCalibrateInfo.IQK_ProgressingTime = ODM_GetProgressingTime(pDM_Odm, pDM_Odm->RFCalibrateInfo.IQK_StartTime); + } + + #endif + break; + + case PHYDM_C2H_DBG_CODE: + phydm_fw_trace_handler_code(pDM_Odm, tmpBuf, c2hCmdLen); + break; + + case PHYDM_C2H_EXTEND: + Extend_c2hSubID = tmpBuf[0]; + if (Extend_c2hSubID == PHYDM_EXTEND_C2H_DBG_PRINT) + phydm_fw_trace_handler_8051(pDM_Odm, tmpBuf, c2hCmdLen); + + break; + + default: + find_c2h_cmd = FALSE; + break; + } + + return find_c2h_cmd; + +} + +u8Byte +ODM_GetCurrentTime( + IN PDM_ODM_T pDM_Odm + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + return 0; +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + return (u8Byte)rtw_get_current_time(); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + return PlatformGetCurrentTime(); +#endif +} + +u8Byte +ODM_GetProgressingTime( + IN PDM_ODM_T pDM_Odm, + IN u8Byte Start_Time + ) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + return 0; +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + return rtw_get_passing_time_ms((u4Byte)Start_Time); +#elif(DM_ODM_SUPPORT_TYPE & ODM_WIN) + return ((PlatformGetCurrentTime() - Start_Time)>>10); +#endif +} + + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_interface.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_interface.h new file mode 100644 index 000000000..342c493e8 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_interface.h @@ -0,0 +1,442 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __ODM_INTERFACE_H__ +#define __ODM_INTERFACE_H__ + +#define INTERFACE_VERSION "1.0" /*2015.01.13 Dino*/ + +// +// =========== Constant/Structure/Enum/... Define +// + + + +// +// =========== Macro Define +// + +#define _reg_all(_name) ODM_##_name +#define _reg_ic(_name, _ic) ODM_##_name##_ic +#define _bit_all(_name) BIT_##_name +#define _bit_ic(_name, _ic) BIT_##_name##_ic + +// _cat: implemented by Token-Pasting Operator. +#if 0 +#define _cat(_name, _ic_type, _func) \ + ( \ + _func##_all(_name) \ + ) +#endif + +/*=================================== + +#define ODM_REG_DIG_11N 0xC50 +#define ODM_REG_DIG_11AC 0xDDD + +ODM_REG(DIG,_pDM_Odm) +=====================================*/ + +#define _reg_11N(_name) ODM_REG_##_name##_11N +#define _reg_11AC(_name) ODM_REG_##_name##_11AC +#define _bit_11N(_name) ODM_BIT_##_name##_11N +#define _bit_11AC(_name) ODM_BIT_##_name##_11AC + +#ifdef __ECOS +#define _rtk_cat(_name, _ic_type, _func) \ + ( \ + ((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \ + _func##_11AC(_name) \ + ) +#else + +#define _cat(_name, _ic_type, _func) \ + ( \ + ((_ic_type) & ODM_IC_11N_SERIES)? _func##_11N(_name): \ + _func##_11AC(_name) \ + ) +#endif +/* +// only sample code +//#define _cat(_name, _ic_type, _func) \ +// ( \ +// ((_ic_type) & ODM_RTL8192C)? _func##_ic(_name, _8192C): \ +// ((_ic_type) & ODM_RTL8192D)? _func##_ic(_name, _8192D): \ +// ((_ic_type) & ODM_RTL8192S)? _func##_ic(_name, _8192S): \ +// ((_ic_type) & ODM_RTL8723A)? _func##_ic(_name, _8723A): \ +// ((_ic_type) & ODM_RTL8188E)? _func##_ic(_name, _8188E): \ +// _func##_ic(_name, _8195) \ +// ) +*/ + +// _name: name of register or bit. +// Example: "ODM_REG(R_A_AGC_CORE1, pDM_Odm)" +// gets "ODM_R_A_AGC_CORE1" or "ODM_R_A_AGC_CORE1_8192C", depends on SupportICType. +#ifdef __ECOS +#define ODM_REG(_name, _pDM_Odm) _rtk_cat(_name, _pDM_Odm->SupportICType, _reg) +#define ODM_BIT(_name, _pDM_Odm) _rtk_cat(_name, _pDM_Odm->SupportICType, _bit) +#else +#define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg) +#define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit) +#endif +typedef enum _PHYDM_H2C_CMD { + ODM_H2C_RSSI_REPORT = 0, + ODM_H2C_PSD_RESULT = 1, + ODM_H2C_PathDiv = 2, + ODM_H2C_WIFI_CALIBRATION = 3, + ODM_H2C_IQ_CALIBRATION = 4, + ODM_H2C_RA_PARA_ADJUST = 5, + PHYDM_H2C_DYNAMIC_TX_PATH = 6, + PHYDM_H2C_FW_TRACE_EN = 7, + PHYDM_H2C_TXBF = 8, + ODM_MAX_H2CCMD +} PHYDM_H2C_CMD; + +typedef enum _PHYDM_C2H_EVT { + PHYDM_C2H_DBG = 0, + PHYDM_C2H_LB = 1, + PHYDM_C2H_XBF = 2, + PHYDM_C2H_TX_REPORT = 3, + PHYDM_C2H_INFO = 9, + PHYDM_C2H_BT_MP = 11, + PHYDM_C2H_RA_RPT = 12, + PHYDM_C2H_RA_PARA_RPT = 14, + PHYDM_C2H_DYNAMIC_TX_PATH_RPT = 15, + PHYDM_C2H_IQK_FINISH = 17, /*0x11*/ + PHYDM_C2H_DBG_CODE = 0xFE, + PHYDM_C2H_EXTEND = 0xFF, +} PHYDM_C2H_EVT; + +typedef enum _PHYDM_EXTEND_C2H_EVT { + PHYDM_EXTEND_C2H_DBG_PRINT = 0 + +} PHYDM_EXTEND_C2H_EVT; + +typedef enum _PHYDM_ACTING_TYPE { + PhyDM_ACTING_AS_IBSS = 0, + PhyDM_ACTING_AS_AP = 1 +} PHYDM_ACTING_TYPE; + + +// +// 2012/02/17 MH For non-MP compile pass only. Linux does not support workitem. +// Suggest HW team to use thread instead of workitem. Windows also support the feature. +// +#if (DM_ODM_SUPPORT_TYPE != ODM_WIN) +typedef void *PRT_WORK_ITEM ; +typedef void RT_WORKITEM_HANDLE,*PRT_WORKITEM_HANDLE; +typedef VOID (*RT_WORKITEM_CALL_BACK)(PVOID pContext); + +#if 0 +typedef struct tasklet_struct RT_WORKITEM_HANDLE, *PRT_WORKITEM_HANDLE; + +typedef struct _RT_WORK_ITEM +{ + + RT_WORKITEM_HANDLE Handle; // Platform-dependent handle for this workitem, e.g. Ndis Workitem object. + PVOID Adapter; // Pointer to Adapter object. + PVOID pContext; // Parameter to passed to CallBackFunc(). + RT_WORKITEM_CALL_BACK CallbackFunc; // Callback function of the workitem. + u1Byte RefCount; // 0: driver is going to unload, 1: No such workitem scheduled, 2: one workitem is schedueled. + PVOID pPlatformExt; // Pointer to platform-dependent extension. + BOOLEAN bFree; + char szID[36]; // An identity string of this workitem. +}RT_WORK_ITEM, *PRT_WORK_ITEM; + +#endif + + +#endif + +// +// =========== Extern Variable ??? It should be forbidden. +// + + +// +// =========== EXtern Function Prototype +// + + +u1Byte +ODM_Read1Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr + ); + +u2Byte +ODM_Read2Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr + ); + +u4Byte +ODM_Read4Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr + ); + +VOID +ODM_Write1Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u1Byte Data + ); + +VOID +ODM_Write2Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u2Byte Data + ); + +VOID +ODM_Write4Byte( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte Data + ); + +VOID +ODM_SetMACReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); + +u4Byte +ODM_GetMACReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); + +VOID +ODM_SetBBReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); + +u4Byte +ODM_GetBBReg( + IN PDM_ODM_T pDM_Odm, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); + +VOID +ODM_SetRFReg( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask, + IN u4Byte Data + ); + +u4Byte +ODM_GetRFReg( + IN PDM_ODM_T pDM_Odm, + IN ODM_RF_RADIO_PATH_E eRFPath, + IN u4Byte RegAddr, + IN u4Byte BitMask + ); + + +// +// Memory Relative Function. +// +VOID +ODM_AllocateMemory( + IN PDM_ODM_T pDM_Odm, + OUT PVOID *pPtr, + IN u4Byte length + ); +VOID +ODM_FreeMemory( + IN PDM_ODM_T pDM_Odm, + OUT PVOID pPtr, + IN u4Byte length + ); + +VOID +ODM_MoveMemory( + IN PDM_ODM_T pDM_Odm, + OUT PVOID pDest, + IN PVOID pSrc, + IN u4Byte Length + ); + +s4Byte ODM_CompareMemory( + IN PDM_ODM_T pDM_Odm, + IN PVOID pBuf1, + IN PVOID pBuf2, + IN u4Byte length + ); + +void ODM_Memory_Set + (IN PDM_ODM_T pDM_Odm, + IN PVOID pbuf, + IN s1Byte value, + IN u4Byte length); + +// +// ODM MISC-spin lock relative API. +// +VOID +ODM_AcquireSpinLock( + IN PDM_ODM_T pDM_Odm, + IN RT_SPINLOCK_TYPE type + ); + +VOID +ODM_ReleaseSpinLock( + IN PDM_ODM_T pDM_Odm, + IN RT_SPINLOCK_TYPE type + ); + + +// +// ODM MISC-workitem relative API. +// +VOID +ODM_InitializeWorkItem( + IN PDM_ODM_T pDM_Odm, + IN PRT_WORK_ITEM pRtWorkItem, + IN RT_WORKITEM_CALL_BACK RtWorkItemCallback, + IN PVOID pContext, + IN const char* szID + ); + +VOID +ODM_StartWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ); + +VOID +ODM_StopWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ); + +VOID +ODM_FreeWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ); + +VOID +ODM_ScheduleWorkItem( + IN PRT_WORK_ITEM pRtWorkItem + ); + +VOID +ODM_IsWorkItemScheduled( + IN PRT_WORK_ITEM pRtWorkItem + ); + +// +// ODM Timer relative API. +// +VOID +ODM_StallExecution( + IN u4Byte usDelay + ); + +VOID +ODM_delay_ms(IN u4Byte ms); + + + +VOID +ODM_delay_us(IN u4Byte us); + +VOID +ODM_sleep_ms(IN u4Byte ms); + +VOID +ODM_sleep_us(IN u4Byte us); + +VOID +ODM_SetTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer, + IN u4Byte msDelay + ); + +VOID +ODM_InitializeTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer, + IN RT_TIMER_CALL_BACK CallBackFunc, + IN PVOID pContext, + IN const char* szID + ); + +VOID +ODM_CancelTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer + ); + +VOID +ODM_ReleaseTimer( + IN PDM_ODM_T pDM_Odm, + IN PRT_TIMER pTimer + ); + +BOOLEAN +phydm_actingDetermine( + IN PDM_ODM_T pDM_Odm, + IN PHYDM_ACTING_TYPE type + ); + +// +// ODM FW relative API. +// +VOID +ODM_FillH2CCmd( + IN PDM_ODM_T pDM_Odm, + IN u1Byte ElementID, + IN u4Byte CmdLen, + IN pu1Byte pCmdBuffer +); + +u1Byte +phydm_c2H_content_parsing( + IN PVOID pDM_VOID, + IN u1Byte c2hCmdId, + IN u1Byte c2hCmdLen, + IN pu1Byte tmpBuf +); + +u8Byte +ODM_GetCurrentTime( + IN PDM_ODM_T pDM_Odm + ); +u8Byte +ODM_GetProgressingTime( + IN PDM_ODM_T pDM_Odm, + IN u8Byte Start_Time + ); + +#endif // __ODM_INTERFACE_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_noisemonitor.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_noisemonitor.c new file mode 100644 index 000000000..647709cb5 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_noisemonitor.c @@ -0,0 +1,299 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ +//#include "mp_precomp.h" +#include "phydm_precomp.h" +#include "phydm_noisemonitor.h" + +//================================================= +// This function is for inband noise test utility only +// To obtain the inband noise level(dbm), do the following. +// 1. disable DIG and Power Saving +// 2. Set initial gain = 0x1a +// 3. Stop updating idle time pwer report (for driver read) +// - 0x80c[25] +// +//================================================= + +#define Valid_Min -35 +#define Valid_Max 10 +#define ValidCnt 5 + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + +s2Byte odm_InbandNoise_Monitor_NSeries(PDM_ODM_T pDM_Odm,u8 bPauseDIG,u8 IGIValue,u32 max_time) +{ + u4Byte tmp4b; + u1Byte max_rf_path=0,rf_path; + u1Byte reg_c50, reg_c58,valid_done=0; + struct noise_level noise_data; + u32 start = 0, func_start=0, func_end = 0; + + func_start = ODM_GetCurrentTime(pDM_Odm); + pDM_Odm->noise_level.noise_all = 0; + + if((pDM_Odm->RFType == ODM_1T2R) ||(pDM_Odm->RFType == ODM_2T2R)) + max_rf_path = 2; + else + max_rf_path = 1; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("odm_DebugControlInbandNoise_Nseries() ==> \n")); + + ODM_Memory_Set(pDM_Odm,&noise_data,0,sizeof(struct noise_level)); + + // + // Step 1. Disable DIG && Set initial gain. + // + + if(bPauseDIG) + { + odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, IGIValue); + } + // + // Step 2. Disable all power save for read registers + // + //dcmd_DebugControlPowerSave(pAdapter, PSDisable); + + // + // Step 3. Get noise power level + // + start = ODM_GetCurrentTime(pDM_Odm); + while(1) + { + + //Stop updating idle time pwer report (for driver read) + ODM_SetBBReg(pDM_Odm, rFPGA0_TxGainStage, BIT25, 1); + + //Read Noise Floor Report + tmp4b = ODM_GetBBReg(pDM_Odm, 0x8f8,bMaskDWord ); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("Noise Floor Report (0x8f8) = 0x%08x\n", tmp4b)); + + //ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0, TestInitialGain); + //if(max_rf_path == 2) + // ODM_SetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0, TestInitialGain); + + //update idle time pwer report per 5us + ODM_SetBBReg(pDM_Odm, rFPGA0_TxGainStage, BIT25, 0); + + noise_data.value[ODM_RF_PATH_A] = (u1Byte)(tmp4b&0xff); + noise_data.value[ODM_RF_PATH_B] = (u1Byte)((tmp4b&0xff00)>>8); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("value_a = 0x%x(%d), value_b = 0x%x(%d)\n", + noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_A], noise_data.value[ODM_RF_PATH_B], noise_data.value[ODM_RF_PATH_B])); + + for(rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) + { + noise_data.sval[rf_path] = (s1Byte)noise_data.value[rf_path]; + noise_data.sval[rf_path] /= 2; + } + + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("sval_a = %d, sval_b = %d\n", + noise_data.sval[ODM_RF_PATH_A], noise_data.sval[ODM_RF_PATH_B])); + //ODM_delay_ms(10); + //ODM_sleep_ms(10); + + for(rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) + { + if( (noise_data.valid_cnt[rf_path] < ValidCnt) && (noise_data.sval[rf_path] < Valid_Max && noise_data.sval[rf_path] >= Valid_Min)) + { + noise_data.valid_cnt[rf_path]++; + noise_data.sum[rf_path] += noise_data.sval[rf_path]; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("RF_Path:%d Valid sval = %d\n", rf_path,noise_data.sval[rf_path])); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("Sum of sval = %d, \n", noise_data.sum[rf_path])); + if(noise_data.valid_cnt[rf_path] == ValidCnt) + { + valid_done++; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("After divided, RF_Path:%d ,sum = %d \n", rf_path,noise_data.sum[rf_path])); + } + + } + + } + + //printk("####### valid_done:%d #############\n",valid_done); + if ((valid_done==max_rf_path) || (ODM_GetProgressingTime(pDM_Odm,start) > max_time)) + { + for(rf_path = ODM_RF_PATH_A; rf_path < max_rf_path; rf_path++) + { + //printk("%s PATH_%d - sum = %d, valid_cnt = %d \n",__FUNCTION__,rf_path,noise_data.sum[rf_path], noise_data.valid_cnt[rf_path]); + if(noise_data.valid_cnt[rf_path]) + noise_data.sum[rf_path] /= noise_data.valid_cnt[rf_path]; + else + noise_data.sum[rf_path] = 0; + } + break; + } + } + reg_c50 = (s4Byte)ODM_GetBBReg(pDM_Odm,rOFDM0_XAAGCCore1,bMaskByte0); + reg_c50 &= ~BIT7; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("0x%x = 0x%02x(%d)\n", rOFDM0_XAAGCCore1, reg_c50, reg_c50)); + pDM_Odm->noise_level.noise[ODM_RF_PATH_A] = -110 + reg_c50 + noise_data.sum[ODM_RF_PATH_A]; + pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_A]; + + if(max_rf_path == 2){ + reg_c58 = (s4Byte)ODM_GetBBReg(pDM_Odm,rOFDM0_XBAGCCore1,bMaskByte0); + reg_c58 &= ~BIT7; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("0x%x = 0x%02x(%d)\n", rOFDM0_XBAGCCore1, reg_c58, reg_c58)); + pDM_Odm->noise_level.noise[ODM_RF_PATH_B] = -110 + reg_c58 + noise_data.sum[ODM_RF_PATH_B]; + pDM_Odm->noise_level.noise_all += pDM_Odm->noise_level.noise[ODM_RF_PATH_B]; + } + pDM_Odm->noise_level.noise_all /= max_rf_path; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD,("noise_a = %d, noise_b = %d\n", + pDM_Odm->noise_level.noise[ODM_RF_PATH_A], + pDM_Odm->noise_level.noise[ODM_RF_PATH_B])); + + // + // Step 4. Recover the Dig + // + if(bPauseDIG) + { + odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, IGIValue); + } + func_end = ODM_GetProgressingTime(pDM_Odm,func_start) ; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_DebugControlInbandNoise_Nseries() <==\n")); + return pDM_Odm->noise_level.noise_all; + +} + +s2Byte +odm_InbandNoise_Monitor_ACSeries(PDM_ODM_T pDM_Odm, u8 bPauseDIG, u8 IGIValue, u32 max_time + ) +{ + s4Byte rxi_buf_anta, rxq_buf_anta; /*rxi_buf_antb, rxq_buf_antb;*/ + s4Byte value32, pwdb_A = 0, sval, noise, sum; + BOOLEAN pd_flag; + u1Byte i, valid_cnt; + u32 start = 0, func_start = 0, func_end = 0; + + + if (!(pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8821))) + return 0; + + func_start = ODM_GetCurrentTime(pDM_Odm); + pDM_Odm->noise_level.noise_all = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_InbandNoise_Monitor_ACSeries() ==>\n")); + + /* Step 1. Disable DIG && Set initial gain. */ + if (bPauseDIG) + odm_PauseDIG(pDM_Odm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_1, IGIValue); + + /* Step 2. Disable all power save for read registers */ + /*dcmd_DebugControlPowerSave(pAdapter, PSDisable); */ + + /* Step 3. Get noise power level */ + start = ODM_GetCurrentTime(pDM_Odm); + + /* reset counters */ + sum = 0; + valid_cnt = 0; + + /* Step 3. Get noise power level */ + while (1) { + /*Set IGI=0x1C */ + ODM_Write_DIG(pDM_Odm, 0x1C); + /*stop CK320&CK88 */ + ODM_SetBBReg(pDM_Odm, 0x8B4, BIT6, 1); + /*Read Path-A */ + ODM_SetBBReg(pDM_Odm, 0x8FC, bMaskDWord, 0x200); /*set debug port*/ + value32 = ODM_GetBBReg(pDM_Odm, 0xFA0, bMaskDWord); /*read debug port*/ + + rxi_buf_anta = (value32 & 0xFFC00) >> 10; /*rxi_buf_anta=RegFA0[19:10]*/ + rxq_buf_anta = value32 & 0x3FF; /*rxq_buf_anta=RegFA0[19:10]*/ + + pd_flag = (BOOLEAN) ((value32 & BIT31) >> 31); + + /*Not in packet detection period or Tx state */ + if ((!pd_flag) || (rxi_buf_anta != 0x200)) { + /*sign conversion*/ + rxi_buf_anta = ODM_SignConversion(rxi_buf_anta, 10); + rxq_buf_anta = ODM_SignConversion(rxq_buf_anta, 10); + + pwdb_A = ODM_PWdB_Conversion(rxi_buf_anta * rxi_buf_anta + rxq_buf_anta * rxq_buf_anta, 20, 18); /*S(10,9)*S(10,9)=S(20,18)*/ + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pwdb_A= %d dB, rxi_buf_anta= 0x%x, rxq_buf_anta= 0x%x\n", pwdb_A, rxi_buf_anta & 0x3FF, rxq_buf_anta & 0x3FF)); + } + + /*BB Reset*/ + ODM_Write1Byte(pDM_Odm, 0x02, ODM_Read1Byte(pDM_Odm, 0x02) & (~BIT0)); + ODM_Write1Byte(pDM_Odm, 0x02, ODM_Read1Byte(pDM_Odm, 0x02) | BIT0); + + /*Start CK320&CK88*/ + ODM_SetBBReg(pDM_Odm, 0x8B4, BIT6, 0); + + sval = pwdb_A; + + if (sval < 0 && sval >= -27) { + if (valid_cnt < ValidCnt) { + valid_cnt++; + sum += sval; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Valid sval = %d\n", sval)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("Sum of sval = %d,\n", sum)); + if ((valid_cnt >= ValidCnt) || (ODM_GetProgressingTime(pDM_Odm, start) > max_time)) { + sum /= valid_cnt; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("After divided, sum = %d\n", sum)); + break; + } + } + } + } + + /*ADC backoff is 12dB,*/ + /*Ptarget=0x1C-110=-82dBm*/ + noise = sum + 12 + 0x1C - 110; + + /*Offset*/ + noise = noise - 3; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("noise = %d\n", noise)); + pDM_Odm->noise_level.noise_all = (s2Byte)noise; + + /* Step 4. Recover the Dig*/ + if (bPauseDIG) + odm_PauseDIG(pDM_Odm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_1, IGIValue); + + func_end = ODM_GetProgressingTime(pDM_Odm, func_start); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_InbandNoise_Monitor_ACSeries() <==\n")); + + return pDM_Odm->noise_level.noise_all; +} + + + +s2Byte +ODM_InbandNoise_Monitor(PVOID pDM_VOID, u8 bPauseDIG, u8 IGIValue, u32 max_time) +{ + + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) + return odm_InbandNoise_Monitor_ACSeries(pDM_Odm, bPauseDIG, IGIValue, max_time); + else + return odm_InbandNoise_Monitor_NSeries(pDM_Odm, bPauseDIG, IGIValue, max_time); +} + +#endif + + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_noisemonitor.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_noisemonitor.h new file mode 100644 index 000000000..022cefe28 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_noisemonitor.h @@ -0,0 +1,49 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + *****************************************************************************/ +#ifndef __ODMNOISEMONITOR_H__ +#define __ODMNOISEMONITOR_H__ + +#define ODM_MAX_CHANNEL_NUM 38//14+24 +struct noise_level +{ + //u1Byte value_a, value_b; + u1Byte value[MAX_RF_PATH]; + //s1Byte sval_a, sval_b; + s1Byte sval[MAX_RF_PATH]; + + //s4Byte noise_a=0, noise_b=0,sum_a=0, sum_b=0; + //s4Byte noise[ODM_RF_PATH_MAX]; + s4Byte sum[MAX_RF_PATH]; + //u1Byte valid_cnt_a=0, valid_cnt_b=0, + u1Byte valid[MAX_RF_PATH]; + u1Byte valid_cnt[MAX_RF_PATH]; + +}; + + +typedef struct _ODM_NOISE_MONITOR_ +{ + s1Byte noise[MAX_RF_PATH]; + s2Byte noise_all; +}ODM_NOISE_MONITOR; + +s2Byte ODM_InbandNoise_Monitor(PVOID pDM_VOID,u8 bPauseDIG,u8 IGIValue,u32 max_time); + +#endif diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_pathdiv.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_pathdiv.c new file mode 100644 index 000000000..f1a8f1122 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_pathdiv.c @@ -0,0 +1,2311 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#if(defined(CONFIG_PATH_DIVERSITY)) +#if RTL8814A_SUPPORT + +VOID +phydm_dtp_fix_tx_path( + IN PVOID pDM_VOID, + IN u1Byte path + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv; + u1Byte i,num_enable_path=0; + + if(path==pDM_PathDiv->pre_tx_path) + { + return; + } + else + { + pDM_PathDiv->pre_tx_path=path; + } + + ODM_SetBBReg( pDM_Odm, 0x93c, BIT18|BIT19, 3); + + for(i=0; i<4; i++) + { + if(path&BIT(i)) + num_enable_path++; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Number of trun-on path : (( %d ))\n", num_enable_path)); + + if(num_enable_path == 1) + { + ODM_SetBBReg( pDM_Odm, 0x93c, 0xf00000, path); + + if(path==PHYDM_A)//1-1 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A ))\n")); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); + } + else if(path==PHYDM_B)//1-2 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B ))\n")); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 0); + } + else if(path==PHYDM_C)//1-3 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( C ))\n")); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 0); + + } + else if(path==PHYDM_D)//1-4 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( D ))\n")); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 0); + } + + } + else if(num_enable_path == 2) + { + ODM_SetBBReg( pDM_Odm, 0x93c, 0xf00000, path); + ODM_SetBBReg( pDM_Odm, 0x940, 0xf0, path); + + if(path==PHYDM_AB)//2-1 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B ))\n")); + //set for 1ss + ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 1); + //set for 2ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 1); + } + else if(path==PHYDM_AC)//2-2 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A C ))\n")); + //set for 1ss + ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 1); + //set for 2ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 1); + } + else if(path==PHYDM_AD)//2-3 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A D ))\n")); + //set for 1ss + ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 1); + //set for 2ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 1); + } + else if(path==PHYDM_BC)//2-4 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B C ))\n")); + //set for 1ss + ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 0); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 1); + //set for 2ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 1); + } + else if(path==PHYDM_BD)//2-5 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B D ))\n")); + //set for 1ss + ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 0); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 1); + //set for 2ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 1); + } + else if(path==PHYDM_CD)//2-6 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( C D ))\n")); + //set for 1ss + ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 0); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 1); + //set for 2ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 1); + } + + } + else if(num_enable_path == 3) + { + ODM_SetBBReg( pDM_Odm, 0x93c, 0xf00000, path); + ODM_SetBBReg( pDM_Odm, 0x940, 0xf0, path); + ODM_SetBBReg( pDM_Odm, 0x940, 0xf0000, path); + + if(path==PHYDM_ABC)//3-1 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B C))\n")); + //set for 1ss + ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 1); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 2); + //set for 2ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 1); + ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 2); + //set for 3ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT21|BIT20, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT23|BIT22, 1); + ODM_SetBBReg( pDM_Odm, 0x940, BIT25|BIT24, 2); + } + else if(path==PHYDM_ABD)//3-2 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A B D ))\n")); + //set for 1ss + ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 1); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 2); + //set for 2ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 1); + ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 2); + //set for 3ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT21|BIT20, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT23|BIT22, 1); + ODM_SetBBReg( pDM_Odm, 0x940, BIT27|BIT26, 2); + + } + else if(path==PHYDM_ACD)//3-3 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( A C D ))\n")); + //set for 1ss + ODM_SetBBReg( pDM_Odm, 0x93c, BIT25|BIT24, 0); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 1); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 2); + //set for 2ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT9|BIT8, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 1); + ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 2); + //set for 3ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT21|BIT20, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT25|BIT24, 1); + ODM_SetBBReg( pDM_Odm, 0x940, BIT27|BIT26, 2); + } + else if(path==PHYDM_BCD)//3-4 + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path (( B C D))\n")); + //set for 1ss + ODM_SetBBReg( pDM_Odm, 0x93c, BIT27|BIT26, 0); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT29|BIT28, 1); + ODM_SetBBReg( pDM_Odm, 0x93c, BIT31|BIT30, 2); + //set for 2ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT11|BIT10, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT13|BIT12, 1); + ODM_SetBBReg( pDM_Odm, 0x940, BIT15|BIT14, 2); + //set for 3ss + ODM_SetBBReg( pDM_Odm, 0x940, BIT23|BIT22, 0); + ODM_SetBBReg( pDM_Odm, 0x940, BIT25|BIT24, 1); + ODM_SetBBReg( pDM_Odm, 0x940, BIT27|BIT26, 2); + } + } + else if(num_enable_path == 4) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" Trun on path ((A B C D))\n")); + } + +} + +VOID +phydm_find_default_path( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv; + u4Byte rssi_avg_a=0, rssi_avg_b=0, rssi_avg_c=0, rssi_avg_d=0, rssi_avg_bcd=0; + u4Byte rssi_total_a=0, rssi_total_b=0, rssi_total_c=0, rssi_total_d=0; + + //2 Default Path Selection By RSSI + + rssi_avg_a = (pDM_PathDiv->path_a_cnt_all > 0)? (pDM_PathDiv->path_a_sum_all / pDM_PathDiv->path_a_cnt_all) :0 ; + rssi_avg_b = (pDM_PathDiv->path_b_cnt_all > 0)? (pDM_PathDiv->path_b_sum_all / pDM_PathDiv->path_b_cnt_all) :0 ; + rssi_avg_c = (pDM_PathDiv->path_c_cnt_all > 0)? (pDM_PathDiv->path_c_sum_all / pDM_PathDiv->path_c_cnt_all) :0 ; + rssi_avg_d = (pDM_PathDiv->path_d_cnt_all > 0)? (pDM_PathDiv->path_d_sum_all / pDM_PathDiv->path_d_cnt_all) :0 ; + + + pDM_PathDiv->path_a_sum_all = 0; + pDM_PathDiv->path_a_cnt_all = 0; + pDM_PathDiv->path_b_sum_all = 0; + pDM_PathDiv->path_b_cnt_all = 0; + pDM_PathDiv->path_c_sum_all = 0; + pDM_PathDiv->path_c_cnt_all = 0; + pDM_PathDiv->path_d_sum_all = 0; + pDM_PathDiv->path_d_cnt_all = 0; + + if(pDM_PathDiv->use_path_a_as_default_ant == 1) + { + rssi_avg_bcd=(rssi_avg_b+rssi_avg_c+rssi_avg_d)/3; + + if( (rssi_avg_a + ANT_DECT_RSSI_TH) > rssi_avg_bcd ) + { + pDM_PathDiv->is_pathA_exist=TRUE; + pDM_PathDiv->default_path=PATH_A; + } + else + { + pDM_PathDiv->is_pathA_exist=FALSE; + } + } + else + { + if( (rssi_avg_a >=rssi_avg_b) && (rssi_avg_a >=rssi_avg_c)&&(rssi_avg_a >=rssi_avg_d)) + pDM_PathDiv->default_path=PATH_A; + else if( (rssi_avg_b >=rssi_avg_c)&&(rssi_avg_b >=rssi_avg_d)) + pDM_PathDiv->default_path=PATH_B; + else if( rssi_avg_c >=rssi_avg_d) + pDM_PathDiv->default_path=PATH_C; + else + pDM_PathDiv->default_path=PATH_D; + } + + +} + + +VOID +phydm_candidate_dtp_update( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv; + + pDM_PathDiv->num_candidate=3; + + if(pDM_PathDiv->use_path_a_as_default_ant == 1) + { + if(pDM_PathDiv->num_tx_path==3) + { + if(pDM_PathDiv->is_pathA_exist) + { + pDM_PathDiv->ant_candidate_1 = PHYDM_ABC; + pDM_PathDiv->ant_candidate_2 = PHYDM_ABD; + pDM_PathDiv->ant_candidate_3 = PHYDM_ACD; + } + else // use path BCD + { + pDM_PathDiv->num_candidate=1; + phydm_dtp_fix_tx_path(pDM_Odm, PHYDM_BCD); + return; + } + } + else if(pDM_PathDiv->num_tx_path==2) + { + if(pDM_PathDiv->is_pathA_exist) + { + pDM_PathDiv->ant_candidate_1 = PHYDM_AB; + pDM_PathDiv->ant_candidate_2 = PHYDM_AC; + pDM_PathDiv->ant_candidate_3 = PHYDM_AD; + } + else + { + pDM_PathDiv->ant_candidate_1 = PHYDM_BC; + pDM_PathDiv->ant_candidate_2 = PHYDM_BD; + pDM_PathDiv->ant_candidate_3 = PHYDM_CD; + } + } + } + else + { + //2 3 TX Mode + if(pDM_PathDiv->num_tx_path==3)//choose 3 ant form 4 + { + if(pDM_PathDiv->default_path == PATH_A) //choose 2 ant form 3 + { + pDM_PathDiv->ant_candidate_1 = PHYDM_ABC; + pDM_PathDiv->ant_candidate_2 = PHYDM_ABD; + pDM_PathDiv->ant_candidate_3 = PHYDM_ACD; + } + else if(pDM_PathDiv->default_path==PATH_B) + { + pDM_PathDiv->ant_candidate_1 = PHYDM_ABC; + pDM_PathDiv->ant_candidate_2 = PHYDM_ABD; + pDM_PathDiv->ant_candidate_3 = PHYDM_BCD; + } + else if(pDM_PathDiv->default_path == PATH_C) + { + pDM_PathDiv->ant_candidate_1 = PHYDM_ABC; + pDM_PathDiv->ant_candidate_2 = PHYDM_ACD; + pDM_PathDiv->ant_candidate_3 = PHYDM_BCD; + } + else if(pDM_PathDiv->default_path == PATH_D) + { + pDM_PathDiv->ant_candidate_1 = PHYDM_ABD; + pDM_PathDiv->ant_candidate_2 = PHYDM_ACD; + pDM_PathDiv->ant_candidate_3 = PHYDM_BCD; + } + } + + //2 2 TX Mode + else if(pDM_PathDiv->num_tx_path==2)//choose 2 ant form 4 + { + if(pDM_PathDiv->default_path == PATH_A) //choose 2 ant form 3 + { + pDM_PathDiv->ant_candidate_1 = PHYDM_AB; + pDM_PathDiv->ant_candidate_2 = PHYDM_AC; + pDM_PathDiv->ant_candidate_3 = PHYDM_AD; + } + else if(pDM_PathDiv->default_path==PATH_B) + { + pDM_PathDiv->ant_candidate_1 = PHYDM_AB; + pDM_PathDiv->ant_candidate_2 = PHYDM_BC; + pDM_PathDiv->ant_candidate_3 = PHYDM_BD; + } + else if(pDM_PathDiv->default_path == PATH_C) + { + pDM_PathDiv->ant_candidate_1 = PHYDM_AC; + pDM_PathDiv->ant_candidate_2 = PHYDM_BC; + pDM_PathDiv->ant_candidate_3 = PHYDM_CD; + } + else if(pDM_PathDiv->default_path == PATH_D) + { + pDM_PathDiv->ant_candidate_1= PHYDM_AD; + pDM_PathDiv->ant_candidate_2 = PHYDM_BD; + pDM_PathDiv->ant_candidate_3= PHYDM_CD; + } + } + } +} + + +VOID +phydm_dynamic_tx_path( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pPATHDIV_T pDM_PathDiv = &pDM_Odm->DM_PathDiv; + + PSTA_INFO_T pEntry; + u4Byte i; + u1Byte num_client=0; + u1Byte H2C_Parameter[6] ={0}; + + + if(!pDM_Odm->bLinked) //bLinked==False + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("DTP_8814 [No Link!!!]\n")); + + if(pDM_PathDiv->bBecomeLinked == TRUE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" [Be disconnected]----->\n")); + pDM_PathDiv->bBecomeLinked = pDM_Odm->bLinked; + } + return; + } + else + { + if(pDM_PathDiv->bBecomeLinked ==FALSE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, (" [Be Linked !!!]----->\n")); + pDM_PathDiv->bBecomeLinked = pDM_Odm->bLinked; + } + } + + //2 [Period CTRL] + if(pDM_PathDiv->dtp_period >=2) + { + pDM_PathDiv->dtp_period=0; + } + else + { + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Phydm_Dynamic_Tx_Path_8814A() Stay = (( %d ))\n",pDM_PathDiv->dtp_period)); + pDM_PathDiv->dtp_period++; + return; + } + + + //2 [Fix Path] + if (pDM_Odm->path_select != PHYDM_AUTO_PATH) + { + return; + } + + //2 [Check Bfer] + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #if (BEAMFORMING_SUPPORT == 1) + { + BEAMFORMING_CAP BeamformCap = (pDM_Odm->BeamformingInfo.BeamformCap); + + if( BeamformCap & BEAMFORMER_CAP ) // BFmer On && Div On -> Div Off + { + if( pDM_PathDiv->fix_path_bfer == 0) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("[ PathDiv : OFF ] BFmer ==1 \n")); + pDM_PathDiv->fix_path_bfer = 1 ; + } + return; + } + else // BFmer Off && Div Off -> Div On + { + if( pDM_PathDiv->fix_path_bfer == 1 ) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("[ PathDiv : ON ] BFmer ==0 \n")); + pDM_PathDiv->fix_path_bfer = 0; + } + } + } + #endif + #endif + + if(pDM_PathDiv->use_path_a_as_default_ant ==1) + { + phydm_find_default_path(pDM_Odm); + phydm_candidate_dtp_update(pDM_Odm); + } + else + { + if( pDM_PathDiv->dtp_state == PHYDM_DTP_INIT) + { + phydm_find_default_path(pDM_Odm); + phydm_candidate_dtp_update(pDM_Odm); + pDM_PathDiv->dtp_state = PHYDM_DTP_RUNNING_1; + } + + else if( pDM_PathDiv->dtp_state == PHYDM_DTP_RUNNING_1) + { + pDM_PathDiv->dtp_check_patha_counter++; + + if(pDM_PathDiv->dtp_check_patha_counter>=NUM_RESET_DTP_PERIOD) + { + pDM_PathDiv->dtp_check_patha_counter=0; + pDM_PathDiv->dtp_state = PHYDM_DTP_INIT; + } + //2 Search space update + else + { + // 1. find the worst candidate + + + // 2. repalce the worst candidate + } + } + } + + //2 Dynamic Path Selection H2C + + if(pDM_PathDiv->num_candidate == 1) + { + return; + } + else + { + H2C_Parameter[0] = pDM_PathDiv->num_candidate; + H2C_Parameter[1] = pDM_PathDiv->num_tx_path; + H2C_Parameter[2] = pDM_PathDiv->ant_candidate_1; + H2C_Parameter[3] = pDM_PathDiv->ant_candidate_2; + H2C_Parameter[4] = pDM_PathDiv->ant_candidate_3; + + ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_DYNAMIC_TX_PATH, 6, H2C_Parameter); + } + +} + + + +VOID +phydm_dynamic_tx_path_init( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pPATHDIV_T pDM_PathDiv = &(pDM_Odm->DM_PathDiv); + PADAPTER pAdapter = pDM_Odm->Adapter; + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + USB_MODE_MECH *pUsbModeMech = &pAdapter->UsbModeMechanism; + #endif + u1Byte search_space_2[NUM_CHOOSE2_FROM4]= {PHYDM_AB, PHYDM_AC, PHYDM_AD, PHYDM_BC, PHYDM_BD, PHYDM_CD }; + u1Byte search_space_3[NUM_CHOOSE3_FROM4]= {PHYDM_BCD, PHYDM_ACD, PHYDM_ABD, PHYDM_ABC}; + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + pDM_PathDiv->is_u3_mode = (pUsbModeMech->CurUsbMode==USB_MODE_U3)? 1 : 0 ; + #else + pDM_PathDiv->is_u3_mode = 1; + #endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("Dynamic TX Path Init 8814\n")); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("is_u3_mode = (( %d ))\n", pDM_PathDiv->is_u3_mode)); + + memcpy(&(pDM_PathDiv->search_space_2[0]), &(search_space_2[0]), NUM_CHOOSE2_FROM4); + memcpy(&(pDM_PathDiv->search_space_3[0]), &(search_space_3[0]), NUM_CHOOSE3_FROM4); + + pDM_PathDiv->use_path_a_as_default_ant= 1; + pDM_PathDiv->dtp_state = PHYDM_DTP_INIT; + pDM_Odm->path_select = PHYDM_AUTO_PATH; + pDM_PathDiv->path_div_type = PHYDM_4R_PATH_DIV; + + + if(pDM_PathDiv->is_u3_mode ) + { + pDM_PathDiv->num_tx_path=3; + phydm_dtp_fix_tx_path(pDM_Odm, PHYDM_BCD);/* 3TX Set Init TX Path*/ + + } + else + { + pDM_PathDiv->num_tx_path=2; + phydm_dtp_fix_tx_path(pDM_Odm, PHYDM_BC);/* 2TX // Set Init TX Path*/ + } + +} + + +VOID +phydm_process_rssi_for_path_div( + IN OUT PVOID pDM_VOID, + IN PVOID p_phy_info_void, + IN PVOID p_pkt_info_void + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PODM_PHY_INFO_T pPhyInfo=(PODM_PHY_INFO_T)p_phy_info_void; + PODM_PACKET_INFO_T pPktinfo=(PODM_PACKET_INFO_T)p_pkt_info_void; + pPATHDIV_T pDM_PathDiv = &(pDM_Odm->DM_PathDiv); + + if(pPktinfo->bPacketToSelf || pPktinfo->bPacketMatchBSSID) + { + if(pPktinfo->DataRate > ODM_RATE11M) + { + if(pDM_PathDiv->path_div_type == PHYDM_4R_PATH_DIV) + { + #if RTL8814A_SUPPORT + if(pDM_Odm->SupportICType & ODM_RTL8814A) + { + pDM_PathDiv->path_a_sum_all+=pPhyInfo->RxMIMOSignalStrength[0]; + pDM_PathDiv->path_a_cnt_all++; + + pDM_PathDiv->path_b_sum_all+=pPhyInfo->RxMIMOSignalStrength[1]; + pDM_PathDiv->path_b_cnt_all++; + + pDM_PathDiv->path_c_sum_all+=pPhyInfo->RxMIMOSignalStrength[2]; + pDM_PathDiv->path_c_cnt_all++; + + pDM_PathDiv->path_d_sum_all+=pPhyInfo->RxMIMOSignalStrength[3]; + pDM_PathDiv->path_d_cnt_all++; + } + #endif + } + else + { + pDM_PathDiv->PathA_Sum[pPktinfo->StationID]+=pPhyInfo->RxMIMOSignalStrength[0]; + pDM_PathDiv->PathA_Cnt[pPktinfo->StationID]++; + + pDM_PathDiv->PathB_Sum[pPktinfo->StationID]+=pPhyInfo->RxMIMOSignalStrength[1]; + pDM_PathDiv->PathB_Cnt[pPktinfo->StationID]++; + } + } + } + + +} + +#endif //#if RTL8814A_SUPPORT + +VOID +odm_pathdiv_debug( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pPATHDIV_T pDM_PathDiv = &(pDM_Odm->DM_PathDiv); + u4Byte used = *_used; + u4Byte out_len = *_out_len; + + pDM_Odm->path_select = (dm_value[0] & 0xf); + PHYDM_SNPRINTF((output+used, out_len-used,"Path_select = (( 0x%x ))\n",pDM_Odm->path_select )); + + //2 [Fix Path] + if (pDM_Odm->path_select != PHYDM_AUTO_PATH) + { + PHYDM_SNPRINTF((output+used, out_len-used,"Trun on path [%s%s%s%s]\n", + ((pDM_Odm->path_select) & 0x1)?"A":"", + ((pDM_Odm->path_select) & 0x2)?"B":"", + ((pDM_Odm->path_select) & 0x4)?"C":"", + ((pDM_Odm->path_select) & 0x8)?"D":"" )); + + phydm_dtp_fix_tx_path( pDM_Odm, pDM_Odm->path_select ); + } + else + { + PHYDM_SNPRINTF((output+used, out_len-used,"%s\n","Auto Path")); + } +} + +#endif // #if(defined(CONFIG_PATH_DIVERSITY)) + +VOID +phydm_c2h_dtp_handler( + IN PVOID pDM_VOID, + IN pu1Byte CmdBuf, + IN u1Byte CmdLen +) +{ +#if(defined(CONFIG_PATH_DIVERSITY)) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pPATHDIV_T pDM_PathDiv = &(pDM_Odm->DM_PathDiv); + + u1Byte macid = CmdBuf[0]; + u1Byte target = CmdBuf[1]; + u1Byte nsc_1 = CmdBuf[2]; + u1Byte nsc_2 = CmdBuf[3]; + u1Byte nsc_3 = CmdBuf[4]; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("Target_candidate = (( %d ))\n", target)); + /* + if( (nsc_1 >= nsc_2) && (nsc_1 >= nsc_3)) + { + phydm_dtp_fix_tx_path(pDM_Odm, pDM_PathDiv->ant_candidate_1); + } + else if( nsc_2 >= nsc_3) + { + phydm_dtp_fix_tx_path(pDM_Odm, pDM_PathDiv->ant_candidate_2); + } + else + { + phydm_dtp_fix_tx_path(pDM_Odm, pDM_PathDiv->ant_candidate_3); + } + */ +#endif +} + +VOID +odm_PathDiversity( + IN PVOID pDM_VOID +) +{ +#if(defined(CONFIG_PATH_DIVERSITY)) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + if(!(pDM_Odm->SupportAbility & ODM_BB_PATH_DIV)) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("Return: Not Support PathDiv\n")); + return; + } + + #if RTL8812A_SUPPORT + + if(pDM_Odm->SupportICType & ODM_RTL8812) + ODM_PathDiversity_8812A(pDM_Odm); + else + #endif + + #if RTL8814A_SUPPORT + if(pDM_Odm->SupportICType & ODM_RTL8814A) + phydm_dynamic_tx_path(pDM_Odm); + else + #endif + {} +#endif +} + +VOID +odm_PathDiversityInit( + IN PVOID pDM_VOID +) +{ +#if(defined(CONFIG_PATH_DIVERSITY)) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + /*pDM_Odm->SupportAbility |= ODM_BB_PATH_DIV;*/ + + if(pDM_Odm->mp_mode == TRUE) + return; + + if(!(pDM_Odm->SupportAbility & ODM_BB_PATH_DIV)) + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("Return: Not Support PathDiv\n")); + return; + } + +#if RTL8812A_SUPPORT + if(pDM_Odm->SupportICType & ODM_RTL8812) + ODM_PathDiversityInit_8812A(pDM_Odm); + else + #endif + + #if RTL8814A_SUPPORT + if(pDM_Odm->SupportICType & ODM_RTL8814A) + phydm_dynamic_tx_path_init(pDM_Odm); + else + #endif + {} +#endif +} + + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +// +// 2011/12/02 MH Copy from MP oursrc for temporarily test. +// +#if RTL8192C_SUPPORT +BOOLEAN +odm_IsConnected_92C( + IN PADAPTER Adapter +) +{ + PRT_WLAN_STA pEntry; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + u4Byte i; + BOOLEAN bConnected=FALSE; + + if(pMgntInfo->mAssoc) + { + bConnected = TRUE; + } + else + { + for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) + { + if(IsAPModeExist(Adapter) && GetFirstExtAdapter(Adapter) != NULL) + pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i); + else + pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i); + + if(pEntry!=NULL) + { + if(pEntry->bAssociated) + { + bConnected = TRUE; + break; + } + } + else + { + break; + } + } + } + return bConnected; +} + +BOOLEAN +ODM_PathDiversityBeforeLink92C( + //IN PADAPTER Adapter + IN PDM_ODM_T pDM_Odm + ) +{ +#if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE* pHalData = NULL; + PMGNT_INFO pMgntInfo = NULL; + //pSWAT_T pDM_SWAT_Table = &Adapter->DM_SWAT_Table; + pPD_T pDM_PDTable = NULL; + + s1Byte Score = 0; + PRT_WLAN_BSS pTmpBssDesc; + PRT_WLAN_BSS pTestBssDesc; + + u1Byte target_chnl = 0; + u2Byte index; + + if (pDM_Odm->Adapter == NULL) //For BSOD when plug/unplug fast. //By YJ,120413 + { // The ODM structure is not initialized. + return FALSE; + } + pHalData = GET_HAL_DATA(Adapter); + pMgntInfo = &Adapter->MgntInfo; + pDM_PDTable = &Adapter->DM_PDTable; + + // Condition that does not need to use path diversity. + if((!(pHalData->CVID_Version==VERSION_1_BEFORE_8703B && IS_92C_SERIAL(pHalData->VersionID))) || (pHalData->PathDivCfg!=1) || pMgntInfo->AntennaTest ) + { + RT_TRACE(COMP_INIT, DBG_LOUD, + ("ODM_PathDiversityBeforeLink92C(): No PathDiv Mechanism before link.\n")); + return FALSE; + } + + // Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF. + PlatformAcquireSpinLock(Adapter, RT_RF_STATE_SPINLOCK); + if(pHalData->eRFPowerState!=eRfOn || pMgntInfo->RFChangeInProgress || pMgntInfo->bMediaConnect) + { + PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK); + + RT_TRACE(COMP_INIT, DBG_LOUD, + ("ODM_PathDiversityBeforeLink92C(): RFChangeInProgress(%x), eRFPowerState(%x)\n", + pMgntInfo->RFChangeInProgress, + pHalData->eRFPowerState)); + + //pDM_SWAT_Table->SWAS_NoLink_State = 0; + pDM_PDTable->PathDiv_NoLink_State = 0; + + return FALSE; + } + else + { + PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK); + } + + //1 Run AntDiv mechanism "Before Link" part. + //if(pDM_SWAT_Table->SWAS_NoLink_State == 0) + if(pDM_PDTable->PathDiv_NoLink_State == 0) + { + //1 Prepare to do Scan again to check current antenna state. + + // Set check state to next step. + //pDM_SWAT_Table->SWAS_NoLink_State = 1; + pDM_PDTable->PathDiv_NoLink_State = 1; + + // Copy Current Scan list. + Adapter->MgntInfo.tmpNumBssDesc = pMgntInfo->NumBssDesc; + PlatformMoveMemory((PVOID)Adapter->MgntInfo.tmpbssDesc, (PVOID)pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC); + + // Switch Antenna to another one. + if(pDM_PDTable->DefaultRespPath == 0) + { + PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x05); // TRX path = PathB + odm_SetRespPath_92C(Adapter, 1); + pDM_PDTable->OFDMTXPath = 0xFFFFFFFF; + pDM_PDTable->CCKTXPath = 0xFFFFFFFF; + } + else + { + PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x00); // TRX path = PathA + odm_SetRespPath_92C(Adapter, 0); + pDM_PDTable->OFDMTXPath = 0x0; + pDM_PDTable->CCKTXPath = 0x0; + } +#if 0 + + pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna; + pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==Antenna_A)?Antenna_B:Antenna_A; + + RT_TRACE(COMP_INIT, DBG_LOUD, + ("ODM_SwAntDivCheckBeforeLink: Change to Ant(%s) for testing.\n", (pDM_SWAT_Table->CurAntenna==Antenna_A)?"A":"B")); + //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna); + pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8)); + PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860); +#endif + + // Go back to scan function again. + RT_TRACE(COMP_INIT, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C: Scan one more time\n")); + pMgntInfo->ScanStep=0; + target_chnl = odm_SwAntDivSelectScanChnl(Adapter); + odm_SwAntDivConstructScanChnl(Adapter, target_chnl); + PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5); + + return TRUE; + } + else + { + //1 ScanComple() is called after antenna swiched. + //1 Check scan result and determine which antenna is going + //1 to be used. + + for(index=0; indexMgntInfo.tmpNumBssDesc; index++) + { + pTmpBssDesc = &(Adapter->MgntInfo.tmpbssDesc[index]); + pTestBssDesc = &(pMgntInfo->bssDesc[index]); + + if(PlatformCompareMemory(pTestBssDesc->bdBssIdBuf, pTmpBssDesc->bdBssIdBuf, 6)!=0) + { + RT_TRACE(COMP_INIT, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C(): ERROR!! This shall not happen.\n")); + continue; + } + + if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower) + { + RT_TRACE(COMP_INIT, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C: Compare scan entry: Score++\n")); + RT_PRINT_STR(COMP_INIT, DBG_LOUD, "SSID: ", pTestBssDesc->bdSsIdBuf, pTestBssDesc->bdSsIdLen); + RT_TRACE(COMP_INIT, DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); + + Score++; + PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS)); + } + else if(pTmpBssDesc->RecvSignalPower < pTestBssDesc->RecvSignalPower) + { + RT_TRACE(COMP_INIT, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C: Compare scan entry: Score--\n")); + RT_PRINT_STR(COMP_INIT, DBG_LOUD, "SSID: ", pTestBssDesc->bdSsIdBuf, pTestBssDesc->bdSsIdLen); + RT_TRACE(COMP_INIT, DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower)); + Score--; + } + + } + + if(pMgntInfo->NumBssDesc!=0 && Score<=0) + { + RT_TRACE(COMP_INIT, DBG_LOUD, + ("ODM_PathDiversityBeforeLink92C(): DefaultRespPath=%d\n", pDM_PDTable->DefaultRespPath)); + + //pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna; + } + else + { + RT_TRACE(COMP_INIT, DBG_LOUD, + ("ODM_PathDiversityBeforeLink92C(): DefaultRespPath=%d\n", pDM_PDTable->DefaultRespPath)); + + if(pDM_PDTable->DefaultRespPath == 0) + { + pDM_PDTable->OFDMTXPath = 0xFFFFFFFF; + pDM_PDTable->CCKTXPath = 0xFFFFFFFF; + odm_SetRespPath_92C(Adapter, 1); + } + else + { + pDM_PDTable->OFDMTXPath = 0x0; + pDM_PDTable->CCKTXPath = 0x0; + odm_SetRespPath_92C(Adapter, 0); + } + PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x01); // RX path = PathAB + + //pDM_SWAT_Table->CurAntenna = pDM_SWAT_Table->PreAntenna; + + //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna); + //pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8)); + //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860); + } + + // Check state reset to default and wait for next time. + //pDM_SWAT_Table->SWAS_NoLink_State = 0; + pDM_PDTable->PathDiv_NoLink_State = 0; + + return FALSE; + } +#else + return FALSE; +#endif + +} + + + +VOID +odm_PathDiversityAfterLink_92C( + IN PADAPTER Adapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + pPD_T pDM_PDTable = &Adapter->DM_PDTable; + u1Byte DefaultRespPath=0; + + if((!(pHalData->CVID_Version==VERSION_1_BEFORE_8703B && IS_92C_SERIAL(pHalData->VersionID))) || (pHalData->PathDivCfg != 1) || (pHalData->eRFPowerState == eRfOff)) + { + if(pHalData->PathDivCfg == 0) + { + RT_TRACE( COMP_INIT, DBG_LOUD, ("No ODM_TXPathDiversity()\n")); + } + else + { + RT_TRACE( COMP_INIT, DBG_LOUD, ("2T ODM_TXPathDiversity()\n")); + } + return; + } + if(!odm_IsConnected_92C(Adapter)) + { + RT_TRACE( COMP_INIT, DBG_LOUD, ("ODM_TXPathDiversity(): No Connections\n")); + return; + } + + + if(pDM_PDTable->TrainingState == 0) + { + RT_TRACE( COMP_INIT, DBG_LOUD, ("ODM_TXPathDiversity() ==>\n")); + odm_OFDMTXPathDiversity_92C(Adapter); + + if((pDM_PDTable->CCKPathDivEnable == TRUE) && (pDM_PDTable->OFDM_Pkt_Cnt < 100)) + { + //RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: TrainingState=0\n")); + + if(pDM_PDTable->CCK_Pkt_Cnt > 300) + pDM_PDTable->Timer = 20; + else if(pDM_PDTable->CCK_Pkt_Cnt > 100) + pDM_PDTable->Timer = 60; + else + pDM_PDTable->Timer = 250; + RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: timer=%d\n",pDM_PDTable->Timer)); + + PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x00); // RX path = PathA + pDM_PDTable->TrainingState = 1; + ODM_SetTimer( pDM_Odm, &pDM_Odm->CCKPathDiversityTimer, pDM_PDTable->Timer); //ms + } + else + { + pDM_PDTable->CCKTXPath = pDM_PDTable->OFDMTXPath; + DefaultRespPath = pDM_PDTable->OFDMDefaultRespPath; + RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_SetRespPath_92C: Skip odm_CCKTXPathDiversity_92C, DefaultRespPath is OFDM\n")); + odm_SetRespPath_92C(Adapter, DefaultRespPath); + odm_ResetPathDiversity_92C(Adapter); + RT_TRACE( COMP_INIT, DBG_LOUD, ("ODM_TXPathDiversity() <==\n")); + } + } + else if(pDM_PDTable->TrainingState == 1) + { + //RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: TrainingState=1\n")); + PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x05); // RX path = PathB + pDM_PDTable->TrainingState = 2; + ODM_SetTimer( pDM_Odm, &pDM_Odm->CCKPathDiversityTimer, pDM_PDTable->Timer); //ms + } + else + { + //RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: TrainingState=2\n")); + pDM_PDTable->TrainingState = 0; + odm_CCKTXPathDiversity_92C(Adapter); + if(pDM_PDTable->OFDM_Pkt_Cnt != 0) + { + DefaultRespPath = pDM_PDTable->OFDMDefaultRespPath; + RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_SetRespPath_92C: DefaultRespPath is OFDM\n")); + } + else + { + DefaultRespPath = pDM_PDTable->CCKDefaultRespPath; + RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_SetRespPath_92C: DefaultRespPath is CCK\n")); + } + odm_SetRespPath_92C(Adapter, DefaultRespPath); + odm_ResetPathDiversity_92C(Adapter); + RT_TRACE( COMP_INIT, DBG_LOUD, ("ODM_TXPathDiversity() <==\n")); + } + +} + +VOID +odm_SetRespPath_92C( + IN PADAPTER Adapter, + IN u1Byte DefaultRespPath + ) +{ + pPD_T pDM_PDTable = &Adapter->DM_PDTable; + + RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_SetRespPath_92C: Select Response Path=%d\n",DefaultRespPath)); + if(DefaultRespPath != pDM_PDTable->DefaultRespPath) + { + if(DefaultRespPath == 0) + { + PlatformEFIOWrite1Byte(Adapter, 0x6D8, (PlatformEFIORead1Byte(Adapter, 0x6D8)&0xc0)|0x15); + } + else + { + PlatformEFIOWrite1Byte(Adapter, 0x6D8, (PlatformEFIORead1Byte(Adapter, 0x6D8)&0xc0)|0x2A); + } + } + pDM_PDTable->DefaultRespPath = DefaultRespPath; +} + +VOID +odm_OFDMTXPathDiversity_92C( + IN PADAPTER Adapter) +{ +// HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + PRT_WLAN_STA pEntry; + u1Byte i, DefaultRespPath = 0; + s4Byte MinRSSI = 0xFF; + pPD_T pDM_PDTable = &Adapter->DM_PDTable; + pDM_PDTable->OFDMTXPath = 0; + + //1 Default Port + if(pMgntInfo->mAssoc) + { + RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: Default port RSSI[0]=%d, RSSI[1]=%d\n", + Adapter->RxStats.RxRSSIPercentage[0], Adapter->RxStats.RxRSSIPercentage[1])); + if(Adapter->RxStats.RxRSSIPercentage[0] > Adapter->RxStats.RxRSSIPercentage[1]) + { + pDM_PDTable->OFDMTXPath = pDM_PDTable->OFDMTXPath & (~BIT0); + MinRSSI = Adapter->RxStats.RxRSSIPercentage[1]; + DefaultRespPath = 0; + RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: Default port Select Path-0\n")); + } + else + { + pDM_PDTable->OFDMTXPath = pDM_PDTable->OFDMTXPath | BIT0; + MinRSSI = Adapter->RxStats.RxRSSIPercentage[0]; + DefaultRespPath = 1; + RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: Default port Select Path-1\n")); + } + //RT_TRACE( COMP_INIT, DBG_LOUD, ("pDM_PDTable->OFDMTXPath =0x%x\n",pDM_PDTable->OFDMTXPath)); + } + //1 Extension Port + for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) + { + if(IsAPModeExist(Adapter) && GetFirstExtAdapter(Adapter) != NULL) + pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i); + else + pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i); + + if(pEntry!=NULL) + { + if(pEntry->bAssociated) + { + RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: MACID=%d, RSSI_0=%d, RSSI_1=%d\n", + pEntry->AssociatedMacId, pEntry->rssi_stat.RxRSSIPercentage[0], pEntry->rssi_stat.RxRSSIPercentage[1])); + + if(pEntry->rssi_stat.RxRSSIPercentage[0] > pEntry->rssi_stat.RxRSSIPercentage[1]) + { + pDM_PDTable->OFDMTXPath = pDM_PDTable->OFDMTXPath & ~(BIT(pEntry->AssociatedMacId)); + //pHalData->TXPath = pHalData->TXPath & ~(1<<(pEntry->AssociatedMacId)); + RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: MACID=%d Select Path-0\n", pEntry->AssociatedMacId)); + if(pEntry->rssi_stat.RxRSSIPercentage[1] < MinRSSI) + { + MinRSSI = pEntry->rssi_stat.RxRSSIPercentage[1]; + DefaultRespPath = 0; + } + } + else + { + pDM_PDTable->OFDMTXPath = pDM_PDTable->OFDMTXPath | BIT(pEntry->AssociatedMacId); + //pHalData->TXPath = pHalData->TXPath | (1 << (pEntry->AssociatedMacId)); + RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: MACID=%d Select Path-1\n", pEntry->AssociatedMacId)); + if(pEntry->rssi_stat.RxRSSIPercentage[0] < MinRSSI) + { + MinRSSI = pEntry->rssi_stat.RxRSSIPercentage[0]; + DefaultRespPath = 1; + } + } + } + } + else + { + break; + } + } + + pDM_PDTable->OFDMDefaultRespPath = DefaultRespPath; +} + + +VOID +odm_CCKTXPathDiversity_92C( + IN PADAPTER Adapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + PRT_WLAN_STA pEntry; + s4Byte MinRSSI = 0xFF; + u1Byte i, DefaultRespPath = 0; +// BOOLEAN bBModePathDiv = FALSE; + pPD_T pDM_PDTable = &Adapter->DM_PDTable; + + //1 Default Port + if(pMgntInfo->mAssoc) + { + if(pHalData->OFDM_Pkt_Cnt == 0) + { + for(i=0; i<2; i++) + { + if(pDM_PDTable->RSSI_CCK_Path_cnt[i] > 1) //Because the first packet is discarded + pDM_PDTable->RSSI_CCK_Path[i] = pDM_PDTable->RSSI_CCK_Path[i] / (pDM_PDTable->RSSI_CCK_Path_cnt[i]-1); + else + pDM_PDTable->RSSI_CCK_Path[i] = 0; + } + RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: pDM_PDTable->RSSI_CCK_Path[0]=%d, pDM_PDTable->RSSI_CCK_Path[1]=%d\n", + pDM_PDTable->RSSI_CCK_Path[0], pDM_PDTable->RSSI_CCK_Path[1])); + RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: pDM_PDTable->RSSI_CCK_Path_cnt[0]=%d, pDM_PDTable->RSSI_CCK_Path_cnt[1]=%d\n", + pDM_PDTable->RSSI_CCK_Path_cnt[0], pDM_PDTable->RSSI_CCK_Path_cnt[1])); + + if(pDM_PDTable->RSSI_CCK_Path[0] > pDM_PDTable->RSSI_CCK_Path[1]) + { + pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath & (~BIT0); + MinRSSI = pDM_PDTable->RSSI_CCK_Path[1]; + DefaultRespPath = 0; + RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Default port Select CCK Path-0\n")); + } + else if(pDM_PDTable->RSSI_CCK_Path[0] < pDM_PDTable->RSSI_CCK_Path[1]) + { + pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath | BIT0; + MinRSSI = pDM_PDTable->RSSI_CCK_Path[0]; + DefaultRespPath = 1; + RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Default port Select CCK Path-1\n")); + } + else + { + if((pDM_PDTable->RSSI_CCK_Path[0] != 0) && (pDM_PDTable->RSSI_CCK_Path[0] < MinRSSI)) + { + pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath & (~BIT0); + RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Default port Select CCK Path-0\n")); + MinRSSI = pDM_PDTable->RSSI_CCK_Path[1]; + DefaultRespPath = 0; + } + else + { + RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Default port unchange CCK Path\n")); + } + } + } + else //Follow OFDM decision + { + pDM_PDTable->CCKTXPath = (pDM_PDTable->CCKTXPath & (~BIT0)) | (pDM_PDTable->OFDMTXPath &BIT0); + RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Follow OFDM decision, Default port Select CCK Path-%d\n", + pDM_PDTable->CCKTXPath &BIT0)); + } + } + //1 Extension Port + for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) + { + if(IsAPModeExist(Adapter) && GetFirstExtAdapter(Adapter) != NULL) + pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i); + else + pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i); + + if(pEntry!=NULL) + { + if(pEntry->bAssociated) + { + if(pEntry->rssi_stat.OFDM_Pkt_Cnt == 0) + { + u1Byte j=0; + for(j=0; j<2; j++) + { + if(pEntry->rssi_stat.RSSI_CCK_Path_cnt[j] > 1) + pEntry->rssi_stat.RSSI_CCK_Path[j] = pEntry->rssi_stat.RSSI_CCK_Path[j] / (pEntry->rssi_stat.RSSI_CCK_Path_cnt[j]-1); + else + pEntry->rssi_stat.RSSI_CCK_Path[j] = 0; + } + RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d, RSSI_CCK0=%d, RSSI_CCK1=%d\n", + pEntry->AssociatedMacId, pEntry->rssi_stat.RSSI_CCK_Path[0], pEntry->rssi_stat.RSSI_CCK_Path[1])); + + if(pEntry->rssi_stat.RSSI_CCK_Path[0] >pEntry->rssi_stat.RSSI_CCK_Path[1]) + { + pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath & ~(BIT(pEntry->AssociatedMacId)); + RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d Select CCK Path-0\n", pEntry->AssociatedMacId)); + if(pEntry->rssi_stat.RSSI_CCK_Path[1] < MinRSSI) + { + MinRSSI = pEntry->rssi_stat.RSSI_CCK_Path[1]; + DefaultRespPath = 0; + } + } + else if(pEntry->rssi_stat.RSSI_CCK_Path[0] rssi_stat.RSSI_CCK_Path[1]) + { + pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath | BIT(pEntry->AssociatedMacId); + RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d Select CCK Path-1\n", pEntry->AssociatedMacId)); + if(pEntry->rssi_stat.RSSI_CCK_Path[0] < MinRSSI) + { + MinRSSI = pEntry->rssi_stat.RSSI_CCK_Path[0]; + DefaultRespPath = 1; + } + } + else + { + if((pEntry->rssi_stat.RSSI_CCK_Path[0] != 0) && (pEntry->rssi_stat.RSSI_CCK_Path[0] < MinRSSI)) + { + pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath & ~(BIT(pEntry->AssociatedMacId)); + MinRSSI = pEntry->rssi_stat.RSSI_CCK_Path[1]; + DefaultRespPath = 0; + RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d Select CCK Path-0\n", pEntry->AssociatedMacId)); + } + else + { + RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d unchange CCK Path\n", pEntry->AssociatedMacId)); + } + } + } + else //Follow OFDM decision + { + pDM_PDTable->CCKTXPath = (pDM_PDTable->CCKTXPath & (~(BIT(pEntry->AssociatedMacId)))) | (pDM_PDTable->OFDMTXPath & BIT(pEntry->AssociatedMacId)); + RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Follow OFDM decision, MACID=%d Select CCK Path-%d\n", + pEntry->AssociatedMacId, (pDM_PDTable->CCKTXPath & BIT(pEntry->AssociatedMacId))>>(pEntry->AssociatedMacId))); + } + } + } + else + { + break; + } + } + + RT_TRACE( COMP_INIT, DBG_LOUD, ("odm_CCKTXPathDiversity_92C:MinRSSI=%d\n",MinRSSI)); + + if(MinRSSI == 0xFF) + DefaultRespPath = pDM_PDTable->CCKDefaultRespPath; + + pDM_PDTable->CCKDefaultRespPath = DefaultRespPath; +} + + +VOID +odm_ResetPathDiversity_92C( + IN PADAPTER Adapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + pPD_T pDM_PDTable = &Adapter->DM_PDTable; + PRT_WLAN_STA pEntry; + u4Byte i,j; + + pDM_PDTable->CCK_Pkt_Cnt = 0; + pDM_PDTable->OFDM_Pkt_Cnt = 0; + pHalData->CCK_Pkt_Cnt =0; + pHalData->OFDM_Pkt_Cnt =0; + + if(pDM_PDTable->CCKPathDivEnable == TRUE) + PHY_SetBBReg(Adapter, rCCK0_AFESetting , 0x0F000000, 0x01); //RX path = PathAB + + for(i=0; i<2; i++) + { + pDM_PDTable->RSSI_CCK_Path_cnt[i]=0; + pDM_PDTable->RSSI_CCK_Path[i] = 0; + } + for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) + { + if(IsAPModeExist(Adapter) && GetFirstExtAdapter(Adapter) != NULL) + pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i); + else + pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i); + + if(pEntry!=NULL) + { + pEntry->rssi_stat.CCK_Pkt_Cnt = 0; + pEntry->rssi_stat.OFDM_Pkt_Cnt = 0; + for(j=0; j<2; j++) + { + pEntry->rssi_stat.RSSI_CCK_Path_cnt[j] = 0; + pEntry->rssi_stat.RSSI_CCK_Path[j] = 0; + } + } + else + break; + } +} + + + + + +VOID +odm_CCKTXPathDiversityCallback( + PRT_TIMER pTimer +) +{ +#if USE_WORKITEM + PADAPTER Adapter = (PADAPTER)pTimer->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#else + PADAPTER Adapter = (PADAPTER)pTimer->Adapter; +#endif + +#if DEV_BUS_TYPE==RT_PCI_INTERFACE +#if USE_WORKITEM + PlatformScheduleWorkItem(&pDM_Odm->CCKPathDiversityWorkitem); +#else + odm_PathDiversityAfterLink_92C(Adapter); +#endif +#else + PlatformScheduleWorkItem(&pDM_Odm->CCKPathDiversityWorkitem); +#endif + +} + + +VOID +odm_CCKTXPathDiversityWorkItemCallback( + IN PVOID pContext + ) +{ + PADAPTER Adapter = (PADAPTER)pContext; + + odm_CCKTXPathDiversity_92C(Adapter); +} + +// +// 20100514 Luke/Joseph: +// Callback function for 500ms antenna test trying. +// +VOID +odm_PathDivChkAntSwitchCallback( + PRT_TIMER pTimer +) +{ + PADAPTER Adapter = (PADAPTER)pTimer->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + +#if DEV_BUS_TYPE==RT_PCI_INTERFACE + +#if USE_WORKITEM + PlatformScheduleWorkItem(&pDM_Odm->PathDivSwitchWorkitem); +#else + odm_PathDivChkAntSwitch(pDM_Odm); +#endif +#else + PlatformScheduleWorkItem(&pDM_Odm->PathDivSwitchWorkitem); +#endif + +//odm_SwAntDivChkAntSwitch(Adapter, SWAW_STEP_DETERMINE); + +} + + +VOID +odm_PathDivChkAntSwitchWorkitemCallback( + IN PVOID pContext + ) +{ + PADAPTER pAdapter = (PADAPTER)pContext; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + odm_PathDivChkAntSwitch(pDM_Odm); +} + + + //MAC0_ACCESS_PHY1 + +// 2011-06-22 Neil Chen & Gary Hsin +// Refer to Jr.Luke's SW ANT DIV +// 92D Path Diversity Main function +// refer to 88C software antenna diversity +// +VOID +odm_PathDivChkAntSwitch( + PDM_ODM_T pDM_Odm + //PADAPTER Adapter, + //u1Byte Step +) +{ + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + + + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + s4Byte curRSSI=100, RSSI_A, RSSI_B; + u1Byte nextAntenna=AUX_ANT; + static u8Byte lastTxOkCnt=0, lastRxOkCnt=0; + u8Byte curTxOkCnt, curRxOkCnt; + static u8Byte TXByteCnt_A=0, TXByteCnt_B=0, RXByteCnt_A=0, RXByteCnt_B=0; + u8Byte CurByteCnt=0, PreByteCnt=0; + static u1Byte TrafficLoad = TRAFFIC_LOW; + u1Byte Score_A=0, Score_B=0; + u1Byte i=0x0; + // Neil Chen + static u1Byte pathdiv_para=0x0; + static u1Byte switchfirsttime=0x00; + // u1Byte regB33 = (u1Byte) PHY_QueryBBReg(Adapter, 0xB30,BIT27); + u1Byte regB33 = (u1Byte)ODM_GetBBReg(pDM_Odm, PATHDIV_REG, BIT27); + + + //u1Byte reg637 =0x0; + static u1Byte fw_value=0x0; + //u8Byte curTxOkCnt_tmp, curRxOkCnt_tmp; + PADAPTER BuddyAdapter = Adapter->BuddyAdapter; // another adapter MAC + // Path Diversity //Neil Chen--2011--06--22 + + //u1Byte PathDiv_Trigger = (u1Byte) PHY_QueryBBReg(Adapter, 0xBA0,BIT31); + u1Byte PathDiv_Trigger = (u1Byte) ODM_GetBBReg(pDM_Odm, PATHDIV_TRI,BIT31); + u1Byte PathDiv_Enable = pHalData->bPathDiv_Enable; + + + //DbgPrint("Path Div PG Value:%x \n",PathDiv_Enable); + if((BuddyAdapter==NULL)||(!PathDiv_Enable)||(PathDiv_Trigger)||(pHalData->CurrentBandType == BAND_ON_2_4G)) + { + return; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD,("===================>odm_PathDivChkAntSwitch()\n")); + + // The first time to switch path excluding 2nd, 3rd, ....etc.... + if(switchfirsttime==0) + { + if(regB33==0) + { + pDM_SWAT_Table->CurAntenna = MAIN_ANT; // Default MAC0_5G-->Path A (current antenna) + } + } + + // Condition that does not need to use antenna diversity. + if(pDM_Odm->SupportICType != ODM_RTL8192D) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_PathDiversityMechanims(): No PathDiv Mechanism.\n")); + return; + } + + // Radio off: Status reset to default and return. + if(pHalData->eRFPowerState==eRfOff) + { + //ODM_SwAntDivRestAfterLink(Adapter); + return; + } + + /* + // Handling step mismatch condition. + // Peak step is not finished at last time. Recover the variable and check again. + if( Step != pDM_SWAT_Table->try_flag ) + { + ODM_SwAntDivRestAfterLink(Adapter); + } */ + + if(pDM_SWAT_Table->try_flag == 0xff) + { + // Select RSSI checking target + if(pMgntInfo->mAssoc && !ACTING_AS_AP(Adapter)) + { + // Target: Infrastructure mode AP. + pHalData->RSSI_target = NULL; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_PathDivMechanism(): RSSI_target is DEF AP!\n")); + } + else + { + u1Byte index = 0; + PRT_WLAN_STA pEntry = NULL; + PADAPTER pTargetAdapter = NULL; + + if( pMgntInfo->mIbss || ACTING_AS_AP(Adapter) ) + { + // Target: AP/IBSS peer. + pTargetAdapter = Adapter; + } + else if(IsAPModeExist(Adapter) && GetFirstExtAdapter(Adapter) != NULL) + { + // Target: VWIFI peer. + pTargetAdapter = GetFirstExtAdapter(Adapter); + } + + if(pTargetAdapter != NULL) + { + for(index=0; indexbAssociated) + break; + } + } + } + + if(pEntry == NULL) + { + ODM_PathDivRestAfterLink(pDM_Odm); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): No Link.\n")); + return; + } + else + { + pHalData->RSSI_target = pEntry; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): RSSI_target is PEER STA\n")); + } + } + + pHalData->RSSI_cnt_A = 0; + pHalData->RSSI_cnt_B = 0; + pDM_SWAT_Table->try_flag = 0; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): Set try_flag to 0 prepare for peak!\n")); + return; + } + else + { + // 1st step + curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - lastTxOkCnt; + curRxOkCnt = Adapter->RxStats.NumRxBytesUnicast - lastRxOkCnt; + lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast; + lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast; + + if(pDM_SWAT_Table->try_flag == 1) // Training State + { + if(pDM_SWAT_Table->CurAntenna == MAIN_ANT) + { + TXByteCnt_A += curTxOkCnt; + RXByteCnt_A += curRxOkCnt; + } + else + { + TXByteCnt_B += curTxOkCnt; + RXByteCnt_B += curRxOkCnt; + } + + nextAntenna = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? AUX_ANT : MAIN_ANT; + pDM_SWAT_Table->RSSI_Trying--; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: RSSI_Trying = %d\n",pDM_SWAT_Table->RSSI_Trying)); + if(pDM_SWAT_Table->RSSI_Trying == 0) + { + CurByteCnt = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? (TXByteCnt_A+RXByteCnt_A) : (TXByteCnt_B+RXByteCnt_B); + PreByteCnt = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? (TXByteCnt_B+RXByteCnt_B) : (TXByteCnt_A+RXByteCnt_A); + + if(TrafficLoad == TRAFFIC_HIGH) + { + //CurByteCnt = PlatformDivision64(CurByteCnt, 9); + PreByteCnt =PreByteCnt*9; + } + else if(TrafficLoad == TRAFFIC_LOW) + { + //CurByteCnt = PlatformDivision64(CurByteCnt, 2); + PreByteCnt =PreByteCnt*2; + } + if(pHalData->RSSI_cnt_A > 0) + RSSI_A = pHalData->RSSI_sum_A/pHalData->RSSI_cnt_A; + else + RSSI_A = 0; + if(pHalData->RSSI_cnt_B > 0) + RSSI_B = pHalData->RSSI_sum_B/pHalData->RSSI_cnt_B; + else + RSSI_B = 0; + curRSSI = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? RSSI_A : RSSI_B; + pDM_SWAT_Table->PreRSSI = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? RSSI_B : RSSI_A; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: PreRSSI = %d, CurRSSI = %d\n",pDM_SWAT_Table->PreRSSI, curRSSI)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: preAntenna= %s, curAntenna= %s \n", + (pDM_SWAT_Table->PreAntenna == MAIN_ANT?"MAIN":"AUX"), (pDM_SWAT_Table->CurAntenna == MAIN_ANT?"MAIN":"AUX"))); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n", + RSSI_A, pHalData->RSSI_cnt_A, RSSI_B, pHalData->RSSI_cnt_B)); + } + + } + else // try_flag=0 + { + + if(pHalData->RSSI_cnt_A > 0) + RSSI_A = pHalData->RSSI_sum_A/pHalData->RSSI_cnt_A; + else + RSSI_A = 0; + if(pHalData->RSSI_cnt_B > 0) + RSSI_B = pHalData->RSSI_sum_B/pHalData->RSSI_cnt_B; + else + RSSI_B = 0; + curRSSI = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? RSSI_A : RSSI_B; + pDM_SWAT_Table->PreRSSI = (pDM_SWAT_Table->PreAntenna == MAIN_ANT)? RSSI_A : RSSI_B; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: PreRSSI = %d, CurRSSI = %d\n", pDM_SWAT_Table->PreRSSI, curRSSI)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: preAntenna= %s, curAntenna= %s \n", + (pDM_SWAT_Table->PreAntenna == MAIN_ANT?"MAIN":"AUX"), (pDM_SWAT_Table->CurAntenna == MAIN_ANT?"MAIN":"AUX"))); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n", + RSSI_A, pHalData->RSSI_cnt_A, RSSI_B, pHalData->RSSI_cnt_B)); + //RT_TRACE(COMP_INIT, DBG_LOUD, ("Ekul:curTxOkCnt = %d\n", curTxOkCnt)); + //RT_TRACE(COMP_INIT, DBG_LOUD, ("Ekul:curRxOkCnt = %d\n", curRxOkCnt)); + } + + //1 Trying State + if((pDM_SWAT_Table->try_flag == 1)&&(pDM_SWAT_Table->RSSI_Trying == 0)) + { + + if(pDM_SWAT_Table->TestMode == TP_MODE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: TestMode = TP_MODE")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH= TRY:CurByteCnt = %"i64fmt"d,", CurByteCnt)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH= TRY:PreByteCnt = %"i64fmt"d\n",PreByteCnt)); + if(CurByteCnt < PreByteCnt) + { + if(pDM_SWAT_Table->CurAntenna == MAIN_ANT) + pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1; + else + pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1; + } + else + { + if(pDM_SWAT_Table->CurAntenna == MAIN_ANT) + pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1; + else + pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1; + } + for (i= 0; i<8; i++) + { + if(((pDM_SWAT_Table->SelectAntennaMap>>i)&BIT0) == 1) + Score_A++; + else + Score_B++; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("SelectAntennaMap=%x\n ",pDM_SWAT_Table->SelectAntennaMap)); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Score_A=%d, Score_B=%d\n", Score_A, Score_B)); + + if(pDM_SWAT_Table->CurAntenna == MAIN_ANT) + { + nextAntenna = (Score_A >= Score_B)?MAIN_ANT:AUX_ANT; + } + else + { + nextAntenna = (Score_B >= Score_A)?AUX_ANT:MAIN_ANT; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: nextAntenna=%s\n",(nextAntenna==MAIN_ANT)?"MAIN":"AUX")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: preAntenna= %s, curAntenna= %s \n", + (pDM_SWAT_Table->PreAntenna == MAIN_ANT?"MAIN":"AUX"), (pDM_SWAT_Table->CurAntenna == MAIN_ANT?"MAIN":"AUX"))); + + if(nextAntenna != pDM_SWAT_Table->CurAntenna) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Switch back to another antenna")); + } + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: current anntena is good\n")); + } + } + + + if(pDM_SWAT_Table->TestMode == RSSI_MODE) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: TestMode = RSSI_MODE")); + pDM_SWAT_Table->SelectAntennaMap=0xAA; + if(curRSSI < pDM_SWAT_Table->PreRSSI) //Current antenna is worse than previous antenna + { + //RT_TRACE(COMP_INIT, DBG_LOUD, ("SWAS: Switch back to another antenna")); + nextAntenna = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)?AUX_ANT : MAIN_ANT; + } + else // current anntena is good + { + nextAntenna =pDM_SWAT_Table->CurAntenna; + //RT_TRACE(COMP_INIT, DBG_LOUD, ("SWAS: current anntena is good\n")); + } + } + + pDM_SWAT_Table->try_flag = 0; + pHalData->RSSI_sum_A = 0; + pHalData->RSSI_cnt_A = 0; + pHalData->RSSI_sum_B = 0; + pHalData->RSSI_cnt_B = 0; + TXByteCnt_A = 0; + TXByteCnt_B = 0; + RXByteCnt_A = 0; + RXByteCnt_B = 0; + + } + + //1 Normal State + else if(pDM_SWAT_Table->try_flag == 0) + { + if(TrafficLoad == TRAFFIC_HIGH) + { + if ((curTxOkCnt+curRxOkCnt) > 3750000)//if(PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000) + TrafficLoad = TRAFFIC_HIGH; + else + TrafficLoad = TRAFFIC_LOW; + } + else if(TrafficLoad == TRAFFIC_LOW) + { + if ((curTxOkCnt+curRxOkCnt) > 3750000)//if(PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000) + TrafficLoad = TRAFFIC_HIGH; + else + TrafficLoad = TRAFFIC_LOW; + } + if(TrafficLoad == TRAFFIC_HIGH) + pDM_SWAT_Table->bTriggerAntennaSwitch = 0; + //RT_TRACE(COMP_INIT, DBG_LOUD, ("Normal:TrafficLoad = %llu\n", curTxOkCnt+curRxOkCnt)); + + //Prepare To Try Antenna + nextAntenna = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? AUX_ANT : MAIN_ANT; + pDM_SWAT_Table->try_flag = 1; + if((curRxOkCnt+curTxOkCnt) > 1000) + { +#if DEV_BUS_TYPE==RT_PCI_INTERFACE + pDM_SWAT_Table->RSSI_Trying = 4; +#else + pDM_SWAT_Table->RSSI_Trying = 2; +#endif + pDM_SWAT_Table->TestMode = TP_MODE; + } + else + { + pDM_SWAT_Table->RSSI_Trying = 2; + pDM_SWAT_Table->TestMode = RSSI_MODE; + + } + + //RT_TRACE(COMP_INIT, DBG_LOUD, ("SWAS: Normal State -> Begin Trying!\n")); + pHalData->RSSI_sum_A = 0; + pHalData->RSSI_cnt_A = 0; + pHalData->RSSI_sum_B = 0; + pHalData->RSSI_cnt_B = 0; + } // end of try_flag=0 + } + + //1 4.Change TRX antenna + if(nextAntenna != pDM_SWAT_Table->CurAntenna) + { + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Change TX Antenna!\n ")); + //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, nextAntenna); for 88C + if(nextAntenna==MAIN_ANT) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Next Antenna is RF PATH A\n ")); + pathdiv_para = 0x02; //02 to switchback to RF path A + fw_value = 0x03; +#if DEV_BUS_TYPE==RT_PCI_INTERFACE + odm_PathDiversity_8192D(pDM_Odm, pathdiv_para); +#else + ODM_FillH2CCmd(pDM_Odm, ODM_H2C_PathDiv,1,(pu1Byte)(&fw_value)); +#endif + } + else if(nextAntenna==AUX_ANT) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Next Antenna is RF PATH B\n ")); + if(switchfirsttime==0) // First Time To Enter Path Diversity + { + switchfirsttime=0x01; + pathdiv_para = 0x00; + fw_value=0x00; // to backup RF Path A Releated Registers + +#if DEV_BUS_TYPE==RT_PCI_INTERFACE + odm_PathDiversity_8192D(pDM_Odm, pathdiv_para); +#else + ODM_FillH2CCmd(pDM_Odm, ODM_H2C_PathDiv,1,(pu1Byte)(&fw_value)); + //for(u1Byte n=0; n<80,n++) + //{ + //delay_us(500); + ODM_delay_ms(500); + odm_PathDiversity_8192D(pDM_Odm, pathdiv_para); + + fw_value=0x01; // to backup RF Path A Releated Registers + ODM_FillH2CCmd(pDM_Odm, ODM_H2C_PathDiv,1,(pu1Byte)(&fw_value)); +#endif + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: FIRST TIME To DO PATH SWITCH!\n ")); + } + else + { + pathdiv_para = 0x01; + fw_value = 0x02; +#if DEV_BUS_TYPE==RT_PCI_INTERFACE + odm_PathDiversity_8192D(pDM_Odm, pathdiv_para); +#else + ODM_FillH2CCmd(pDM_Odm, ODM_H2C_PathDiv,1,(pu1Byte)(&fw_value)); +#endif + } + } + // odm_PathDiversity_8192D(Adapter, pathdiv_para); + } + + //1 5.Reset Statistics + pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna; + pDM_SWAT_Table->CurAntenna = nextAntenna; + pDM_SWAT_Table->PreRSSI = curRSSI; + + //1 6.Set next timer + + if(pDM_SWAT_Table->RSSI_Trying == 0) + return; + + if(pDM_SWAT_Table->RSSI_Trying%2 == 0) + { + if(pDM_SWAT_Table->TestMode == TP_MODE) + { + if(TrafficLoad == TRAFFIC_HIGH) + { +#if DEV_BUS_TYPE==RT_PCI_INTERFACE + ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 10 ); //ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 10 ms\n")); +#else + ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 20 ); //ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 20 ms\n")); +#endif + } + else if(TrafficLoad == TRAFFIC_LOW) + { + ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 50 ); //ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 50 ms\n")); + } + } + else // TestMode == RSSI_MODE + { + ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 500 ); //ms + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 500 ms\n")); + } + } + else + { + if(pDM_SWAT_Table->TestMode == TP_MODE) + { + if(TrafficLoad == TRAFFIC_HIGH) + +#if DEV_BUS_TYPE==RT_PCI_INTERFACE + ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 90 ); //ms + //ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 90 ms\n")); +#else + ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 180); //ms +#endif + else if(TrafficLoad == TRAFFIC_LOW) + ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 100 ); //ms + } + else + ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 500 ); //ms + } +} + + + +VOID +ODM_CCKPathDiversityChkPerPktRssi( + PADAPTER Adapter, + BOOLEAN bIsDefPort, + BOOLEAN bMatchBSSID, + PRT_WLAN_STA pEntry, + PRT_RFD pRfd, + pu1Byte pDesc + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + BOOLEAN bCount = FALSE; + pPD_T pDM_PDTable = &Adapter->DM_PDTable; + //BOOLEAN isCCKrate = RX_HAL_IS_CCK_RATE_92C(pDesc); +#if DEV_BUS_TYPE != RT_SDIO_INTERFACE + BOOLEAN isCCKrate = RX_HAL_IS_CCK_RATE(Adapter, pDesc); +#else //below code would be removed if we have verified SDIO + BOOLEAN isCCKrate = IS_HARDWARE_TYPE_8188E(Adapter) ? RX_HAL_IS_CCK_RATE_88E(pDesc) : RX_HAL_IS_CCK_RATE_92C(pDesc); +#endif + + if ((pHalData->PathDivCfg != 1)) + return; + + if(pHalData->RSSI_target==NULL && bIsDefPort && bMatchBSSID) + bCount = TRUE; + else if(pHalData->RSSI_target!=NULL && pEntry!=NULL && pHalData->RSSI_target==pEntry) + bCount = TRUE; + + if(bCount && isCCKrate) + { + if(pDM_PDTable->TrainingState == 1 ) + { + if(pEntry) + { + if(pEntry->rssi_stat.RSSI_CCK_Path_cnt[0] != 0) + pEntry->rssi_stat.RSSI_CCK_Path[0] += pRfd->Status.RxPWDBAll; + pEntry->rssi_stat.RSSI_CCK_Path_cnt[0]++; + } + else + { + if(pDM_PDTable->RSSI_CCK_Path_cnt[0] != 0) + pDM_PDTable->RSSI_CCK_Path[0] += pRfd->Status.RxPWDBAll; + pDM_PDTable->RSSI_CCK_Path_cnt[0]++; + } + } + else if(pDM_PDTable->TrainingState == 2 ) + { + if(pEntry) + { + if(pEntry->rssi_stat.RSSI_CCK_Path_cnt[1] != 0) + pEntry->rssi_stat.RSSI_CCK_Path[1] += pRfd->Status.RxPWDBAll; + pEntry->rssi_stat.RSSI_CCK_Path_cnt[1]++; + } + else + { + if(pDM_PDTable->RSSI_CCK_Path_cnt[1] != 0) + pDM_PDTable->RSSI_CCK_Path[1] += pRfd->Status.RxPWDBAll; + pDM_PDTable->RSSI_CCK_Path_cnt[1]++; + } + } + } +} + + + + +//Neil Chen---2011--06--22 +//----92D Path Diversity----// +//#ifdef PathDiv92D +//================================== +//3 Path Diversity +//================================== +// +// 20100514 Luke/Joseph: +// Add new function for antenna diversity after link. +// This is the main function of antenna diversity after link. +// This function is called in HalDmWatchDog() and ODM_SwAntDivChkAntSwitchCallback(). +// HalDmWatchDog() calls this function with SWAW_STEP_PEAK to initialize the antenna test. +// In SWAW_STEP_PEAK, another antenna and a 500ms timer will be set for testing. +// After 500ms, ODM_SwAntDivChkAntSwitchCallback() calls this function to compare the signal just +// listened on the air with the RSSI of original antenna. +// It chooses the antenna with better RSSI. +// There is also a aged policy for error trying. Each error trying will cost more 5 seconds waiting +// penalty to get next try. +// +// +// 20100503 Joseph: +// Add new function SwAntDivCheck8192C(). +// This is the main function of Antenna diversity function before link. +// Mainly, it just retains last scan result and scan again. +// After that, it compares the scan result to see which one gets better RSSI. +// It selects antenna with better receiving power and returns better scan result. +// + + +// +// 20100514 Luke/Joseph: +// This function is used to gather the RSSI information for antenna testing. +// It selects the RSSI of the peer STA that we want to know. +// +VOID +ODM_PathDivChkPerPktRssi( + PADAPTER Adapter, + BOOLEAN bIsDefPort, + BOOLEAN bMatchBSSID, + PRT_WLAN_STA pEntry, + PRT_RFD pRfd + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + BOOLEAN bCount = FALSE; + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + + if(pHalData->RSSI_target==NULL && bIsDefPort && bMatchBSSID) + bCount = TRUE; + else if(pHalData->RSSI_target!=NULL && pEntry!=NULL && pHalData->RSSI_target==pEntry) + bCount = TRUE; + + if(bCount) + { + //1 RSSI for SW Antenna Switch + if(pDM_SWAT_Table->CurAntenna == MAIN_ANT) + { + pHalData->RSSI_sum_A += pRfd->Status.RxPWDBAll; + pHalData->RSSI_cnt_A++; + } + else + { + pHalData->RSSI_sum_B += pRfd->Status.RxPWDBAll; + pHalData->RSSI_cnt_B++; + + } + } +} + + +// +// 20100514 Luke/Joseph: +// Add new function to reset antenna diversity state after link. +// +VOID +ODM_PathDivRestAfterLink( + IN PDM_ODM_T pDM_Odm + ) +{ + PADAPTER Adapter=pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table; + + pHalData->RSSI_cnt_A = 0; + pHalData->RSSI_cnt_B = 0; + pDM_SWAT_Table->try_flag = 0x0; // NOT 0xff + pDM_SWAT_Table->RSSI_Trying = 0; + pDM_SWAT_Table->SelectAntennaMap=0xAA; + pDM_SWAT_Table->CurAntenna = MAIN_ANT; +} + + +//================================================== +//3 PathDiv End +//================================================== + + +VOID +ODM_FillTXPathInTXDESC( + IN PADAPTER Adapter, + IN PRT_TCB pTcb, + IN pu1Byte pDesc +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u4Byte TXPath; + pPD_T pDM_PDTable = &Adapter->DM_PDTable; + + //2011.09.05 Add by Luke Lee for path diversity + if(pHalData->PathDivCfg == 1) + { + TXPath = (pDM_PDTable->OFDMTXPath >> pTcb->macId) & BIT0; + //RT_TRACE( COMP_INIT, DBG_LOUD, ("Fill TXDESC: macID=%d, TXPath=%d\n", pTcb->macId, TXPath)); + //SET_TX_DESC_TX_ANT_CCK(pDesc,TXPath); + if(TXPath == 0) + { + SET_TX_DESC_TX_ANTL_92C(pDesc,1); + SET_TX_DESC_TX_ANT_HT_92C(pDesc,1); + } + else + { + SET_TX_DESC_TX_ANTL_92C(pDesc,2); + SET_TX_DESC_TX_ANT_HT_92C(pDesc,2); + } + TXPath = (pDM_PDTable->CCKTXPath >> pTcb->macId) & BIT0; + if(TXPath == 0) + { + SET_TX_DESC_TX_ANT_CCK_92C(pDesc,1); + } + else + { + SET_TX_DESC_TX_ANT_CCK_92C(pDesc,2); + } + } +} + +//Only for MP //Neil Chen--2012--0502-- +VOID +odm_PathDivInit_92D( +IN PDM_ODM_T pDM_Odm) +{ + pPATHDIV_PARA pathIQK = &pDM_Odm->pathIQK; + + pathIQK->org_2g_RegC14=0x0; + pathIQK->org_2g_RegC4C=0x0; + pathIQK->org_2g_RegC80=0x0; + pathIQK->org_2g_RegC94=0x0; + pathIQK->org_2g_RegCA0=0x0; + pathIQK->org_5g_RegC14=0x0; + pathIQK->org_5g_RegCA0=0x0; + pathIQK->org_5g_RegE30=0x0; + pathIQK->swt_2g_RegC14=0x0; + pathIQK->swt_2g_RegC4C=0x0; + pathIQK->swt_2g_RegC80=0x0; + pathIQK->swt_2g_RegC94=0x0; + pathIQK->swt_2g_RegCA0=0x0; + pathIQK->swt_5g_RegC14=0x0; + pathIQK->swt_5g_RegCA0=0x0; + pathIQK->swt_5g_RegE30=0x0; + +} + + +u1Byte +odm_SwAntDivSelectScanChnl( + IN PADAPTER Adapter + ) +{ +#if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM) + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + u2Byte i; + u1Byte j, ScanChannel = 0, ChannelNum = 0; + PRT_CHANNEL_LIST pChannelList = GET_RT_CHANNEL_LIST(pMgntInfo); + u1Byte EachChannelSTAs[MAX_SCAN_CHANNEL_NUM] = {0}; + + if(pMgntInfo->tmpNumBssDesc == 0) + return 0; + + for(i = 0; i < pMgntInfo->tmpNumBssDesc; i++) + { + ChannelNum = pMgntInfo->tmpbssDesc[i].ChannelNumber; + for(j = 0; j < pChannelList->ChannelLen; j++) + { + if(pChannelList->ChnlListEntry[j].ChannelNum == ChannelNum) + { + EachChannelSTAs[j]++; + break; + } + } + } + + for(i = 0; i < MAX_SCAN_CHANNEL_NUM; i++) + { + if(EachChannelSTAs[i] > EachChannelSTAs[ScanChannel]) + ScanChannel = (u1Byte)i; + } + + if(EachChannelSTAs[ScanChannel] == 0) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("odm_SwAntDivSelectScanChnl(): Scan List is empty.\n")); + return 0; + } + + ScanChannel = pChannelList->ChnlListEntry[ScanChannel].ChannelNum; + + + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, + ("odm_SwAntDivSelectScanChnl(): Channel (( %d )) is select as scan channel.\n", ScanChannel)); + + return ScanChannel; +#else + return 0; +#endif +} + + +VOID +odm_SwAntDivConstructScanChnl( + IN PADAPTER Adapter, + IN u1Byte ScanChnl + ) +{ + + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + + if(ScanChnl == 0) + { + u1Byte i; + PRT_CHANNEL_LIST pChannelList = GET_RT_CHANNEL_LIST(pMgntInfo); + + // 20100519 Joseph: Original antenna scanned nothing. + // Test antenna shall scan all channel with half period in this condition. + + RT_TRACE_F(COMP_SCAN, DBG_TRACE, (" RT_CHNL_LIST_ACTION_CONSTRUCT chnl %d \n", ScanChnl)); + + RtActChannelList(Adapter, RT_CHNL_LIST_ACTION_CONSTRUCT_SCAN_LIST, NULL, NULL); + for(i = 0; i < pChannelList->ChannelLen; i++) + pChannelList->ChnlListEntry[i].ScanPeriod /= 2; + } + else + { + // The using of this CustomizedScanRequest is a trick to rescan the two channels + // under the NORMAL scanning process. It will not affect MGNT_INFO.CustomizedScanRequest. + CUSTOMIZED_SCAN_REQUEST CustomScanReq; + + CustomScanReq.bEnabled = TRUE; + CustomScanReq.Channels[0] = ScanChnl; + CustomScanReq.Channels[1] = pMgntInfo->dot11CurrentChannelNumber; + CustomScanReq.nChannels = 2; + CustomScanReq.ScanType = SCAN_ACTIVE; + CustomScanReq.Duration = DEFAULT_PASSIVE_SCAN_PERIOD; + + RT_TRACE_F(COMP_SCAN, DBG_TRACE, (" RT_CHNL_LIST_ACTION_CONSTRUCT chnl %d \n", ScanChnl)); + + RtActChannelList(Adapter, RT_CHNL_LIST_ACTION_CONSTRUCT_SCAN_LIST, &CustomScanReq, NULL); + } + +} +#else + +VOID +odm_PathDivChkAntSwitchCallback( + PRT_TIMER pTimer +) +{ +} + +VOID +odm_PathDivChkAntSwitchWorkitemCallback( + IN PVOID pContext + ) +{ +} + +VOID +odm_CCKTXPathDiversityCallback( + PRT_TIMER pTimer +) +{ +} + +VOID +odm_CCKTXPathDiversityWorkItemCallback( + IN PVOID pContext + ) +{ +} +u1Byte +odm_SwAntDivSelectScanChnl( + IN PADAPTER Adapter + ) +{ + return 0; +} +VOID +odm_SwAntDivConstructScanChnl( + IN PADAPTER Adapter, + IN u1Byte ScanChnl + ) +{ +} + + +#endif + +#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_pathdiv.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_pathdiv.h new file mode 100644 index 000000000..020288ea4 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_pathdiv.h @@ -0,0 +1,324 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMPATHDIV_H__ +#define __PHYDMPATHDIV_H__ +/*#define PATHDIV_VERSION "2.0" //2014.11.04*/ +#define PATHDIV_VERSION "3.0" /*2015.01.13 Dino*/ + +#if(defined(CONFIG_PATH_DIVERSITY)) +#define USE_PATH_A_AS_DEFAULT_ANT //for 8814 dynamic TX path selection + +#define NUM_RESET_DTP_PERIOD 5 +#define ANT_DECT_RSSI_TH 3 + +#define PATH_A 1 +#define PATH_B 2 +#define PATH_C 3 +#define PATH_D 4 + +#define PHYDM_AUTO_PATH 0 +#define PHYDM_FIX_PATH 1 + +#define NUM_CHOOSE2_FROM4 6 +#define NUM_CHOOSE3_FROM4 4 + + +#define PHYDM_A BIT0 +#define PHYDM_B BIT1 +#define PHYDM_C BIT2 +#define PHYDM_D BIT3 +#define PHYDM_AB (BIT0 | BIT1) // 0 +#define PHYDM_AC (BIT0 | BIT2) // 1 +#define PHYDM_AD (BIT0 | BIT3) // 2 +#define PHYDM_BC (BIT1 | BIT2) // 3 +#define PHYDM_BD (BIT1 | BIT3) // 4 +#define PHYDM_CD (BIT2 | BIT3) // 5 + +#define PHYDM_ABC (BIT0 | BIT1 | BIT2) /* 0*/ +#define PHYDM_ABD (BIT0 | BIT1 | BIT3) /* 1*/ +#define PHYDM_ACD (BIT0 | BIT2 | BIT3) /* 2*/ +#define PHYDM_BCD (BIT1 | BIT2 | BIT3) /* 3*/ + +#define PHYDM_ABCD (BIT0 | BIT1 | BIT2 | BIT3) + + +typedef enum dtp_state +{ + PHYDM_DTP_INIT=1, + PHYDM_DTP_RUNNING_1 + +}PHYDM_DTP_STATE; + +typedef enum path_div_type +{ + PHYDM_2R_PATH_DIV = 1, + PHYDM_4R_PATH_DIV = 2 +}PHYDM_PATH_DIV_TYPE; + +VOID +phydm_process_rssi_for_path_div( + IN OUT PVOID pDM_VOID, + IN PVOID p_phy_info_void, + IN PVOID p_pkt_info_void + ); + +typedef struct _ODM_PATH_DIVERSITY_ +{ + u1Byte RespTxPath; + u1Byte PathSel[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u4Byte PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM]; + u2Byte PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u2Byte PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; + u1Byte path_div_type; + #if RTL8814A_SUPPORT + + u4Byte path_a_sum_all; + u4Byte path_b_sum_all; + u4Byte path_c_sum_all; + u4Byte path_d_sum_all; + + u4Byte path_a_cnt_all; + u4Byte path_b_cnt_all; + u4Byte path_c_cnt_all; + u4Byte path_d_cnt_all; + + u1Byte dtp_period; + BOOLEAN bBecomeLinked; + BOOLEAN is_u3_mode; + u1Byte num_tx_path; + u1Byte default_path; + u1Byte num_candidate; + u1Byte ant_candidate_1; + u1Byte ant_candidate_2; + u1Byte ant_candidate_3; + u1Byte dtp_state; + u1Byte dtp_check_patha_counter; + BOOLEAN fix_path_bfer; + u1Byte search_space_2[NUM_CHOOSE2_FROM4]; + u1Byte search_space_3[NUM_CHOOSE3_FROM4]; + + u1Byte pre_tx_path; + u1Byte use_path_a_as_default_ant; + BOOLEAN is_pathA_exist; + + #endif +}PATHDIV_T, *pPATHDIV_T; + + +#endif //#if(defined(CONFIG_PATH_DIVERSITY)) + +VOID +phydm_c2h_dtp_handler( + IN PVOID pDM_VOID, + IN pu1Byte CmdBuf, + IN u1Byte CmdLen + ); + +VOID +odm_PathDiversityInit( + IN PVOID pDM_VOID + ); + +VOID +odm_PathDiversity( + IN PVOID pDM_VOID + ); + +VOID +odm_pathdiv_debug( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value, + IN u4Byte *_used, + OUT char *output, + IN u4Byte *_out_len + ); + + + +//1 [OLD IC]-------------------------------------------------------------------------------- + + + + + + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + +//#define PATHDIV_ENABLE 1 +#define dm_PathDiv_RSSI_Check ODM_PathDivChkPerPktRssi +#define PathDivCheckBeforeLink8192C ODM_PathDiversityBeforeLink92C + + + + +typedef struct _PathDiv_Parameter_define_ +{ + u4Byte org_5g_RegE30; + u4Byte org_5g_RegC14; + u4Byte org_5g_RegCA0; + u4Byte swt_5g_RegE30; + u4Byte swt_5g_RegC14; + u4Byte swt_5g_RegCA0; + //for 2G IQK information + u4Byte org_2g_RegC80; + u4Byte org_2g_RegC4C; + u4Byte org_2g_RegC94; + u4Byte org_2g_RegC14; + u4Byte org_2g_RegCA0; + + u4Byte swt_2g_RegC80; + u4Byte swt_2g_RegC4C; + u4Byte swt_2g_RegC94; + u4Byte swt_2g_RegC14; + u4Byte swt_2g_RegCA0; +}PATHDIV_PARA,*pPATHDIV_PARA; + +VOID +odm_PathDiversityInit_92C( + IN PADAPTER Adapter + ); + +VOID +odm_2TPathDiversityInit_92C( + IN PADAPTER Adapter + ); + +VOID +odm_1TPathDiversityInit_92C( + IN PADAPTER Adapter + ); + +BOOLEAN +odm_IsConnected_92C( + IN PADAPTER Adapter + ); + +BOOLEAN +ODM_PathDiversityBeforeLink92C( + //IN PADAPTER Adapter + IN PDM_ODM_T pDM_Odm + ); + +VOID +odm_PathDiversityAfterLink_92C( + IN PADAPTER Adapter + ); + +VOID +odm_SetRespPath_92C( + IN PADAPTER Adapter, + IN u1Byte DefaultRespPath + ); + +VOID +odm_OFDMTXPathDiversity_92C( + IN PADAPTER Adapter + ); + +VOID +odm_CCKTXPathDiversity_92C( + IN PADAPTER Adapter + ); + +VOID +odm_ResetPathDiversity_92C( + IN PADAPTER Adapter + ); + +VOID +odm_CCKTXPathDiversityCallback( + PRT_TIMER pTimer + ); + +VOID +odm_CCKTXPathDiversityWorkItemCallback( + IN PVOID pContext + ); + +VOID +odm_PathDivChkAntSwitchCallback( + PRT_TIMER pTimer + ); + +VOID +odm_PathDivChkAntSwitchWorkitemCallback( + IN PVOID pContext + ); + + +VOID +odm_PathDivChkAntSwitch( + PDM_ODM_T pDM_Odm + ); + +VOID +ODM_CCKPathDiversityChkPerPktRssi( + PADAPTER Adapter, + BOOLEAN bIsDefPort, + BOOLEAN bMatchBSSID, + PRT_WLAN_STA pEntry, + PRT_RFD pRfd, + pu1Byte pDesc + ); + +VOID +ODM_PathDivChkPerPktRssi( + PADAPTER Adapter, + BOOLEAN bIsDefPort, + BOOLEAN bMatchBSSID, + PRT_WLAN_STA pEntry, + PRT_RFD pRfd + ); + +VOID +ODM_PathDivRestAfterLink( + IN PDM_ODM_T pDM_Odm + ); + +VOID +ODM_FillTXPathInTXDESC( + IN PADAPTER Adapter, + IN PRT_TCB pTcb, + IN pu1Byte pDesc + ); + +VOID +odm_PathDivInit_92D( + IN PDM_ODM_T pDM_Odm + ); + +u1Byte +odm_SwAntDivSelectScanChnl( + IN PADAPTER Adapter + ); + +VOID +odm_SwAntDivConstructScanChnl( + IN PADAPTER Adapter, + IN u1Byte ScanChnl + ); + + #endif //#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + + + #endif //#ifndef __ODMPATHDIV_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_powertracking_ap.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_powertracking_ap.c new file mode 100644 index 000000000..4f8623958 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_powertracking_ap.c @@ -0,0 +1,1050 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#if !defined(_OUTSRC_COEXIST) +//============================================================ +// Global var +//============================================================ + + +u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE_92D] = { + 0x0b40002d, // 0, -15.0dB + 0x0c000030, // 1, -14.5dB + 0x0cc00033, // 2, -14.0dB + 0x0d800036, // 3, -13.5dB + 0x0e400039, // 4, -13.0dB + 0x0f00003c, // 5, -12.5dB + 0x10000040, // 6, -12.0dB + 0x11000044, // 7, -11.5dB + 0x12000048, // 8, -11.0dB + 0x1300004c, // 9, -10.5dB + 0x14400051, // 10, -10.0dB + 0x15800056, // 11, -9.5dB + 0x16c0005b, // 12, -9.0dB + 0x18000060, // 13, -8.5dB + 0x19800066, // 14, -8.0dB + 0x1b00006c, // 15, -7.5dB + 0x1c800072, // 16, -7.0dB + 0x1e400079, // 17, -6.5dB + 0x20000080, // 18, -6.0dB + 0x22000088, // 19, -5.5dB + 0x24000090, // 20, -5.0dB + 0x26000098, // 21, -4.5dB + 0x288000a2, // 22, -4.0dB + 0x2ac000ab, // 23, -3.5dB + 0x2d4000b5, // 24, -3.0dB + 0x300000c0, // 25, -2.5dB + 0x32c000cb, // 26, -2.0dB + 0x35c000d7, // 27, -1.5dB + 0x390000e4, // 28, -1.0dB + 0x3c8000f2, // 29, -0.5dB + 0x40000100, // 30, +0dB + 0x43c0010f, // 31, +0.5dB + 0x47c0011f, // 32, +1.0dB + 0x4c000130, // 33, +1.5dB + 0x50800142, // 34, +2.0dB + 0x55400155, // 35, +2.5dB + 0x5a400169, // 36, +3.0dB + 0x5fc0017f, // 37, +3.5dB + 0x65400195, // 38, +4.0dB + 0x6b8001ae, // 39, +4.5dB + 0x71c001c7, // 40, +5.0dB + 0x788001e2, // 41, +5.5dB + 0x7f8001fe // 42, +6.0dB +}; + +u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, // 0, -16.0dB + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 1, -15.5dB + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 2, -15.0dB + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 3, -14.5dB + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 4, -14.0dB + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 5, -13.5dB + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 6, -13.0dB + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 7, -12.5dB + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 8, -12.0dB + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 9, -11.5dB + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 10, -11.0dB + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 11, -10.5dB + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 12, -10.0dB + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 13, -9.5dB + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 14, -9.0dB + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 15, -8.5dB + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 17, -7.5dB + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 18, -7.0dB + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 19, -6.5dB + {0x1c, 0x1a, 0x18, 0x12, 0x0e, 0x08, 0x04, 0x02}, // 20, -6.0dB + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 21, -5.5dB + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 22, -5.0dB + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 23, -4.5dB + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 24, -4.0dB + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 25, -3.5dB + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 26, -3.0dB + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 27, -2.5dB + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 28, -2.0dB + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 29, -1.5dB + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 30, -1.0dB + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 31, -0.5dB + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} // 32, +0dB +}; + + +u1Byte CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8]= { + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, // 0, -16.0dB + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 1, -15.5dB + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 2, -15.0dB + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 3, -14.5dB + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 4, -14.0dB + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 5, -13.5dB + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 6, -13.0dB + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 7, -12.5dB + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 8, -12.0dB + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 9, -11.5dB + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 10, -11.0dB + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 11, -10.5dB + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 12, -10.0dB + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 13, -9.5dB + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 14, -9.0dB + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 15, -8.5dB + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 17, -7.5dB + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 18, -7.0dB + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 19, -6.5dB + {0x1c, 0x1a, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 20, -6.0dB + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 21, -5.5dB + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 22, -5.0dB + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 23, -4.5dB + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 24, -4.0dB + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 25, -3.5dB + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 26, -3.0dB + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 27, -2.5dB + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 28, -2.0dB + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 29, -1.5dB + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 30, -1.0dB + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 31, -0.5dB + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} // 32, +0dB +}; + +u4Byte OFDMSwingTable[OFDM_TABLE_SIZE_92D] = { + 0x0b40002d, // 0, -15.0dB + 0x0c000030, // 1, -14.5dB + 0x0cc00033, // 2, -14.0dB + 0x0d800036, // 3, -13.5dB + 0x0e400039, // 4, -13.0dB + 0x0f00003c, // 5, -12.5dB + 0x10000040, // 6, -12.0dB + 0x11000044, // 7, -11.5dB + 0x12000048, // 8, -11.0dB + 0x1300004c, // 9, -10.5dB + 0x14400051, // 10, -10.0dB + 0x15800056, // 11, -9.5dB + 0x16c0005b, // 12, -9.0dB + 0x18000060, // 13, -8.5dB + 0x19800066, // 14, -8.0dB + 0x1b00006c, // 15, -7.5dB + 0x1c800072, // 16, -7.0dB + 0x1e400079, // 17, -6.5dB + 0x20000080, // 18, -6.0dB + 0x22000088, // 19, -5.5dB + 0x24000090, // 20, -5.0dB + 0x26000098, // 21, -4.5dB + 0x288000a2, // 22, -4.0dB + 0x2ac000ab, // 23, -3.5dB + 0x2d4000b5, // 24, -3.0dB + 0x300000c0, // 25, -2.5dB + 0x32c000cb, // 26, -2.0dB + 0x35c000d7, // 27, -1.5dB + 0x390000e4, // 28, -1.0dB + 0x3c8000f2, // 29, -0.5dB + 0x40000100, // 30, +0dB + 0x43c0010f, // 31, +0.5dB + 0x47c0011f, // 32, +1.0dB + 0x4c000130, // 33, +1.5dB + 0x50800142, // 34, +2.0dB + 0x55400155, // 35, +2.5dB + 0x5a400169, // 36, +3.0dB + 0x5fc0017f, // 37, +3.5dB + 0x65400195, // 38, +4.0dB + 0x6b8001ae, // 39, +4.5dB + 0x71c001c7, // 40, +5.0dB + 0x788001e2, // 41, +5.5dB + 0x7f8001fe // 42, +6.0dB +}; + + +u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, // 0, -16.0dB + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 1, -15.5dB + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 2, -15.0dB + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 3, -14.5dB + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 4, -14.0dB + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 5, -13.5dB + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 6, -13.0dB + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 7, -12.5dB + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 8, -12.0dB + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 9, -11.5dB + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 10, -11.0dB + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 11, -10.5dB + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 12, -10.0dB + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 13, -9.5dB + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 14, -9.0dB + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 15, -8.5dB + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 17, -7.5dB + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 18, -7.0dB + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 19, -6.5dB + {0x1c, 0x1a, 0x18, 0x12, 0x0e, 0x08, 0x04, 0x02}, // 20, -6.0dB + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 21, -5.5dB + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 22, -5.0dB + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 23, -4.5dB + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 24, -4.0dB + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 25, -3.5dB + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 26, -3.0dB + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 27, -2.5dB + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 28, -2.0dB + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 29, -1.5dB + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 30, -1.0dB + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 31, -0.5dB + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} // 32, +0dB +}; + + +u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]= { + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, // 0, -16.0dB + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 1, -15.5dB + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 2, -15.0dB + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 3, -14.5dB + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 4, -14.0dB + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 5, -13.5dB + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 6, -13.0dB + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 7, -12.5dB + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 8, -12.0dB + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 9, -11.5dB + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 10, -11.0dB + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 11, -10.5dB + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 12, -10.0dB + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 13, -9.5dB + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 14, -9.0dB + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 15, -8.5dB + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 17, -7.5dB + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 18, -7.0dB + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 19, -6.5dB + {0x1c, 0x1a, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 20, -6.0dB + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 21, -5.5dB + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 22, -5.0dB + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 23, -4.5dB + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 24, -4.0dB + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 25, -3.5dB + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 26, -3.0dB + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 27, -2.5dB + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 28, -2.0dB + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 29, -1.5dB + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 30, -1.0dB + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 31, -0.5dB + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} // 32, +0dB +}; + +u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16] = { +{0x16, 0x15, 0x13, 0x10, 0xD, 0x9, 0x6, 0x3, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 0 -16dB */ +{0x18, 0x17, 0x15, 0x12, 0xE, 0xA, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 1 -15.5dB */ +{0x1B, 0x1A, 0x18, 0x14, 0x10, 0xB, 0x7, 0x4, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 2 -15dB */ +{0x1F, 0x1E, 0x1B, 0x17, 0x12, 0xD, 0x8, 0x5, 0x2, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 3 -14.5dB */ +{0x22, 0x21, 0x1E, 0x19, 0x14, 0xE, 0x9, 0x5, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 4 -14dB */ +{0x26, 0x25, 0x22, 0x1C, 0x16, 0x10, 0xA, 0x6, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 5 -13.5dB */ +{0x2B, 0x2A, 0x26, 0x20, 0x19, 0x12, 0xC, 0x7, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 6 -13dB */ +{0x30, 0x2F, 0x2A, 0x24, 0x1C, 0x14, 0xD, 0x8, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 7 -12.5dB */ +{0x36, 0x34, 0x2F, 0x28, 0x1F, 0x17, 0xF, 0x9, 0x4, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 8 -12dB */ +{0x3D, 0x3B, 0x35, 0x2D, 0x23, 0x19, 0x11, 0xA, 0x5, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 9 -11.5dB */ +{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0xB, 0x5, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 10 -11dB */ +{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0xC, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 11 -10.5dB */ +{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0xE, 0x6, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 12 -10dB */ +{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0xF, 0x7, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 13 -9.5dB */ +{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x8, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 14 -9dB */ +{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x9, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 15 -8.5dB */ +{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0xA, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 16 -8dB */ +{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0xB, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 17 -7.5dB */ +{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0xD, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 18 -7dB */ +{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0xE, 0x4, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, /* 19 -6.5dB */ +{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x5, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} /* 20 -6dB */ +}; + + +#if 0 +u4Byte OFDMSwingTable_92E[OFDM_TABLE_SIZE_92E] = { + /* Index0 6 dB */ 0x7fc001ff, + /* Index1 5.7dB */ 0x7b4001ed, + /* Index2 5.4dB */ 0x774001dd, + /* Index3 5.1dB */ 0x734001cd, + /* Index4 4.8dB */ 0x6f4001bd, + /* Index5 4.5dB */ 0x6b8001ae, + /* Index6 4.2dB */ 0x67c0019f, + /* Index7 3.9dB */ 0x64400191, + /* Index8 3.6dB */ 0x60c00183, + /* Index9 3.3dB */ 0x5d800176, + /* Index10 3 dB */ 0x5a80016a, + /* Index11 2.7dB */ 0x5740015d, + /* Index12 2.4dB */ 0x54400151, + /* Index13 2.1dB */ 0x51800146, + /* Index14 1.8dB */ 0x4ec0013b, + /* Index15 1.5dB */ 0x4c000130, + /* Index16 1.2dB */ 0x49800126, + /* Index17 0.9dB */ 0x4700011c, + /* Index18 0.6dB */ 0x44800112, + /* Index19 0.3dB */ 0x42000108, + /* Index20 0 dB */ 0x40000100, // 20 This is OFDM base index + /* Index21 -0.3dB */ 0x3dc000f7, + /* Index22 -0.6dB */ 0x3bc000ef, + /* Index23 -0.9dB */ 0x39c000e7, + /* Index24 -1.2dB */ 0x37c000df, + /* Index25 -1.5dB */ 0x35c000d7, + /* Index26 -1.8dB */ 0x340000d0, + /* Index27 -2.1dB */ 0x324000c9, + /* Index28 -2.4dB */ 0x308000c2, + /* Index29 -2.7dB */ 0x2f0000bc, + /* Index30 -3 dB */ 0x2d4000b5, + /* Index31 -3.3dB */ 0x2bc000af, + /* Index32 -3.6dB */ 0x2a4000a9, + /* Index33 -3.9dB */ 0x28c000a3, + /* Index34 -4.2dB */ 0x2780009e, + /* Index35 -4.5dB */ 0x26000098, + /* Index36 -4.8dB */ 0x24c00093, + /* Index37 -5.1dB */ 0x2380008e, + /* Index38 -5.4dB */ 0x22400089, + /* Index39 -5.7dB */ 0x21400085, + /* Index40 -6 dB */ 0x20000080, + /* Index41 -6.3dB */ 0x1f00007c, + /* Index42 -6.6dB */ 0x1e000078, + /* Index43 -6.9dB */ 0x1d000074, + /* Index44 -7.2dB */ 0x1c000070, + /* Index45 -7.5dB */ 0x1b00006c, + /* Index46 -7.8dB */ 0x1a000068, + /* Index47 -8.1dB */ 0x19400065, + /* Index48 -8.4dB */ 0x18400061, + /* Index49 -8.7dB */ 0x1780005e, + /* Index50 -9 dB */ 0x16c0005b, + /* Index51 -9.3dB */ 0x16000058, + /* Index52 -9.6dB */ 0x15400055, + /* Index53 -9.9dB */ 0x14800052 +}; +u1Byte CCKSwingTable_Ch1_Ch13_92E[CCK_TABLE_SIZE_92E][8] = { + /* Index0 0 dB */ {0x36, 0x34 , 0x2E , 0x26 , 0x1C , 0x12 , 0x08 , 0x04}, + /* Index1 -0.3dB */ {0x34, 0x32 , 0x2C , 0x25 , 0x1B , 0x11 , 0x08 , 0x04}, + /* Index2 -0.6dB */ {0x32, 0x30 , 0x2B , 0x23 , 0x1A , 0x11 , 0x07 , 0x04}, + /* Index3 -0.9dB */ {0x31, 0x2F , 0x29 , 0x22 , 0x19 , 0x10 , 0x07 , 0x04}, + /* Index4 -1.2dB */ {0x2F, 0x2D , 0x28 , 0x21 , 0x18 , 0x10 , 0x07 , 0x03}, + /* Index5 -1.5dB */ {0x2D, 0x2C , 0x27 , 0x20 , 0x18 , 0x0F , 0x07 , 0x03}, + /* Index6 -1.8dB */ {0x2C, 0x2A , 0x25 , 0x1F , 0x17 , 0x0F , 0x06 , 0x03}, + /* Index7 -2.1dB */ {0x2A, 0x29 , 0x24 , 0x1E , 0x16 , 0x0E , 0x06 , 0x03}, + /* Index8 -2.4dB */ {0x29, 0x27 , 0x23 , 0x1D , 0x15 , 0x0E , 0x06 , 0x03}, + /* Index9 -2.7dB */ {0x27, 0x26 , 0x22 , 0x1C , 0x14 , 0x0D , 0x06 , 0x03}, + /* Index10 -3 dB */ {0x26, 0x25 , 0x20 , 0x1B , 0x14 , 0x0D , 0x06 , 0x03}, + /* Index11 -3.3dB */ {0x25, 0x23 , 0x1F , 0x1A , 0x13 , 0x0C , 0x05 , 0x03}, + /* Index12 -3.6dB */ {0x24, 0x22 , 0x1E , 0x19 , 0x12 , 0x0C , 0x05 , 0x03}, + /* Index13 -3.9dB */ {0x22, 0x21 , 0x1D , 0x18 , 0x12 , 0x0B , 0x05 , 0x03}, + /* Index14 -4.2dB */ {0x21, 0x20 , 0x1C , 0x17 , 0x11 , 0x0B , 0x05 , 0x02}, + /* Index15 -4.5dB */ {0x20, 0x1F , 0x1B , 0x17 , 0x11 , 0x0B , 0x05 , 0x02}, + /* Index16 -4.8dB */ {0x1F, 0x1E , 0x1A , 0x16 , 0x10 , 0x0A , 0x05 , 0x02}, + /* Index17 -5.1dB */ {0x1E, 0x1D , 0x1A , 0x15 , 0x10 , 0x0A , 0x04 , 0x02}, + /* Index18 -5.4dB */ {0x1D, 0x1C , 0x19 , 0x14 , 0x0F , 0x0A , 0x04 , 0x02}, + /* Index19 -5.7dB */ {0x1C, 0x1B , 0x18 , 0x14 , 0x0E , 0x09 , 0x04 , 0x02}, + /* Index20 -6.0dB */ {0x1B, 0x1A , 0x17 , 0x13 , 0x0E , 0x09 , 0x04 , 0x02}, // 20 This is CCK base index + /* Index21 -6.3dB */ {0x1A, 0x19 , 0x16 , 0x12 , 0x0E , 0x09 , 0x04 , 0x02}, + /* Index22 -6.6dB */ {0x19, 0x18 , 0x15 , 0x12 , 0x0D , 0x08 , 0x04 , 0x02}, + /* Index23 -6.9dB */ {0x18, 0x17 , 0x15 , 0x11 , 0x0D , 0x08 , 0x04 , 0x02}, + /* Index24 -7.2dB */ {0x18, 0x17 , 0x14 , 0x11 , 0x0C , 0x08 , 0x03 , 0x02}, + /* Index25 -7.5dB */ {0x17, 0x16 , 0x13 , 0x10 , 0x0C , 0x08 , 0x03 , 0x02}, + /* Index26 -7.8dB */ {0x16, 0x15 , 0x13 , 0x0F , 0x0B , 0x07 , 0x03 , 0x02}, + /* Index27 -8.1dB */ {0x15, 0x14 , 0x12 , 0x0F , 0x0B , 0x07 , 0x03 , 0x02}, + /* Index28 -8.4dB */ {0x14, 0x14 , 0x11 , 0x0E , 0x0B , 0x07 , 0x03 , 0x02}, + /* Index29 -8.7dB */ {0x14, 0x13 , 0x11 , 0x0E , 0x0A , 0x07 , 0x03 , 0x01}, + /* Index30 -9.0dB */ {0x13, 0x12 , 0x10 , 0x0D , 0x0A , 0x06 , 0x03 , 0x01}, // 30 This is hp CCK base index + /* Index31 -9.3dB */ {0x12, 0x12 , 0x0F , 0x0D , 0x0A , 0x06 , 0x03 , 0x01}, + /* Index32 -9.6dB */ {0x12, 0x11 , 0x0F , 0x0D , 0x09 , 0x06 , 0x03 , 0x01}, + /* Index33 -9.9dB */ {0x11, 0x11 , 0x0F , 0x0C , 0x09 , 0x06 , 0x03 , 0x01}, + /* Index34 -10.2dB */ {0x11, 0x11 , 0x0E , 0x0C , 0x09 , 0x06 , 0x02 , 0x01}, + /* Index35 -10.5dB */ {0x10, 0x0F , 0x0E , 0x0B , 0x08 , 0x05 , 0x02 , 0x01}, + /* Index36 -10.8dB */ {0x10, 0x0F , 0x0D , 0x0B , 0x08 , 0x05 , 0x02 , 0x01}, + /* Index37 -11.1dB */ {0x0F, 0x0E , 0x0D , 0x0A , 0x08 , 0x05 , 0x02 , 0x01}, + /* Index38 -11.4dB */ {0x0E, 0x0E , 0x0C , 0x0A , 0x07 , 0x05 , 0x02 , 0x01}, + /* Index39 -11.7dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x07 , 0x05 , 0x02 , 0x01}, + /* Index40 -12 dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x07 , 0x05 , 0x02 , 0x01}, + /* Index41 -12.3dB */ {0x0D, 0x0D , 0x0B , 0x09 , 0x07 , 0x04 , 0x02 , 0x01}, + /* Index42 -12.6dB */ {0x0D, 0x0C , 0x0B , 0x09 , 0x07 , 0x04 , 0x02 , 0x01}, + /* Index43 -12.9dB */ {0x0C, 0x0C , 0x0A , 0x09 , 0x06 , 0x04 , 0x02 , 0x01}, + /* Index44 -13.2dB */ {0x0C, 0x0B , 0x0A , 0x08 , 0x06 , 0x04 , 0x02 , 0x01}, + /* Index45 -13.5dB */ {0x0B, 0x0B , 0x0A , 0x08 , 0x06 , 0x04 , 0x02 , 0x01}, + /* Index46 -13.8dB */ {0x0B, 0x0B , 0x09 , 0x08 , 0x06 , 0x04 , 0x02 , 0x01}, + /* Index47 -14.1dB */ {0x0B, 0x0A , 0x09 , 0x07 , 0x06 , 0x04 , 0x02 , 0x01}, + /* Index48 -14.4dB */ {0x0A, 0x0A , 0x09 , 0x07 , 0x05 , 0x03 , 0x02 , 0x01}, + /* Index49 -14.7dB */ {0x0A, 0x0A , 0x08 , 0x07 , 0x05 , 0x03 , 0x01 , 0x01}, + /* Index50 -15 dB */ {0x0A, 0x09 , 0x08 , 0x07 , 0x05 , 0x03 , 0x01 , 0x01}, + /* Index51 -15.3dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x05 , 0x03 , 0x01 , 0x01}, + /* Index52 -15.6dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x05 , 0x03 , 0x01 , 0x01}, + /* Index53 -15.9dB */ {0x09, 0x08 , 0x07 , 0x06 , 0x04 , 0x03 , 0x01 , 0x01} +}; +u1Byte CCKSwingTable_Ch14_92E[CCK_TABLE_SIZE_92E][8] = { + /* Index0 0 dB */ {0x36, 0x34 , 0x2E , 0x26 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index1 -0.3dB */ {0x34, 0x32 , 0x2C , 0x25 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index2 -0.6dB */ {0x32, 0x30 , 0x2B , 0x23 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index3 -0.9dB */ {0x31, 0x2F , 0x29 , 0x22 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index4 -1.2dB */ {0x2F, 0x2D , 0x28 , 0x21 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index5 -1.5dB */ {0x2D, 0x2C , 0x27 , 0x20 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index6 -1.8dB */ {0x2C, 0x2A , 0x25 , 0x1F , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index7 -2.1dB */ {0x2A, 0x29 , 0x24 , 0x1E , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index8 -2.4dB */ {0x29, 0x27 , 0x23 , 0x1D , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index9 -2.7dB */ {0x27, 0x26 , 0x22 , 0x1C , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index10 -3 dB */ {0x26, 0x25 , 0x20 , 0x1B , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index11 -3.3dB */ {0x25, 0x23 , 0x1F , 0x1A , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index12 -3.6dB */ {0x24, 0x22 , 0x1E , 0x19 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index13 -3.9dB */ {0x22, 0x21 , 0x1D , 0x18 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index14 -4.2dB */ {0x21, 0x20 , 0x1C , 0x17 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index15 -4.5dB */ {0x20, 0x1F , 0x1B , 0x17 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index16 -4.8dB */ {0x1F, 0x1E , 0x1A , 0x16 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index17 -5.1dB */ {0x1E, 0x1D , 0x1A , 0x15 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index18 -5.4dB */ {0x1D, 0x1C , 0x19 , 0x14 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index19 -5.7dB */ {0x1C, 0x1B , 0x18 , 0x14 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index20 -6 dB */ {0x1B, 0x1A , 0x17 , 0x13 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index21 -6.3dB */ {0x1A, 0x19 , 0x16 , 0x12 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index22 -6.6dB */ {0x19, 0x18 , 0x15 , 0x12 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index23 -6.9dB */ {0x18, 0x17 , 0x15 , 0x11 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index24 -7.2dB */ {0x18, 0x17 , 0x14 , 0x11 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index25 -7.5dB */ {0x17, 0x16 , 0x13 , 0x10 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index26 -7.8dB */ {0x16, 0x15 , 0x13 , 0x0F , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index27 -8.1dB */ {0x15, 0x14 , 0x12 , 0x0F , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index28 -8.4dB */ {0x14, 0x14 , 0x11 , 0x0E , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index29 -8.7dB */ {0x14, 0x13 , 0x11 , 0x0E , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index30 -9 dB */ {0x13, 0x12 , 0x10 , 0x0D , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index31 -9.3dB */ {0x12, 0x12 , 0x0F , 0x0D , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index32 -9.6dB */ {0x12, 0x11 , 0x0F , 0x0D , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index33 -9.9dB */ {0x11, 0x11 , 0x0F , 0x0C , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index34 -10.2dB */ {0x11, 0x11 , 0x0E , 0x0C , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index35 -10.5dB */ {0x10, 0x0F , 0x0E , 0x0B , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index36 -10.8dB */ {0x10, 0x0F , 0x0D , 0x0B , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index37 -11.1dB */ {0x0F, 0x0E , 0x0D , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index38 -11.4dB */ {0x0E, 0x0E , 0x0C , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index39 -11.7dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index40 -12 dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index41 -12.3dB */ {0x0D, 0x0D , 0x0B , 0x09 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index42 -12.6dB */ {0x0D, 0x0C , 0x0B , 0x09 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index43 -12.9dB */ {0x0C, 0x0C , 0x0A , 0x09 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index44 -13.2dB */ {0x0C, 0x0B , 0x0A , 0x08 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index45 -13.5dB */ {0x0B, 0x0B , 0x0A , 0x08 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index46 -13.8dB */ {0x0B, 0x0B , 0x09 , 0x08 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index47 -14.1dB */ {0x0B, 0x0A , 0x09 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index48 -14.4dB */ {0x0A, 0x0A , 0x09 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index49 -14.7dB */ {0x0A, 0x0A , 0x08 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index50 -15 dB */ {0x0A, 0x09 , 0x08 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index51 -15.3dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index52 -15.6dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index53 -15.9dB */ {0x09, 0x08 , 0x07 , 0x06 , 0x00 , 0x00 , 0x00 , 0x00} +}; +#endif + +#ifdef AP_BUILD_WORKAROUND + +unsigned int TxPwrTrk_OFDM_SwingTbl[TxPwrTrk_OFDM_SwingTbl_Len] = { + /* +6.0dB */ 0x7f8001fe, + /* +5.5dB */ 0x788001e2, + /* +5.0dB */ 0x71c001c7, + /* +4.5dB */ 0x6b8001ae, + /* +4.0dB */ 0x65400195, + /* +3.5dB */ 0x5fc0017f, + /* +3.0dB */ 0x5a400169, + /* +2.5dB */ 0x55400155, + /* +2.0dB */ 0x50800142, + /* +1.5dB */ 0x4c000130, + /* +1.0dB */ 0x47c0011f, + /* +0.5dB */ 0x43c0010f, + /* 0.0dB */ 0x40000100, + /* -0.5dB */ 0x3c8000f2, + /* -1.0dB */ 0x390000e4, + /* -1.5dB */ 0x35c000d7, + /* -2.0dB */ 0x32c000cb, + /* -2.5dB */ 0x300000c0, + /* -3.0dB */ 0x2d4000b5, + /* -3.5dB */ 0x2ac000ab, + /* -4.0dB */ 0x288000a2, + /* -4.5dB */ 0x26000098, + /* -5.0dB */ 0x24000090, + /* -5.5dB */ 0x22000088, + /* -6.0dB */ 0x20000080, + /* -6.5dB */ 0x1a00006c, + /* -7.0dB */ 0x1c800072, + /* -7.5dB */ 0x18000060, + /* -8.0dB */ 0x19800066, + /* -8.5dB */ 0x15800056, + /* -9.0dB */ 0x26c0005b, + /* -9.5dB */ 0x14400051, + /* -10.0dB */ 0x24400051, + /* -10.5dB */ 0x1300004c, + /* -11.0dB */ 0x12000048, + /* -11.5dB */ 0x11000044, + /* -12.0dB */ 0x10000040 +}; +#endif + +#endif + + +u1Byte DeltaSwingTableIdx_2GA_P_DEFAULT[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3 +, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; +u1Byte DeltaSwingTableIdx_2GA_N_DEFAULT[DELTA_SWINGIDX_SIZE] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4 +, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; + + +#ifdef CONFIG_WLAN_HAL_8192EE +u4Byte OFDMSwingTable_92E[OFDM_TABLE_SIZE_92E] = { + /* Index0 6 dB */ 0x7fc001ff, + /* Index1 5.7dB */ 0x7b4001ed, + /* Index2 5.4dB */ 0x774001dd, + /* Index3 5.1dB */ 0x734001cd, + /* Index4 4.8dB */ 0x6f4001bd, + /* Index5 4.5dB */ 0x6b8001ae, + /* Index6 4.2dB */ 0x67c0019f, + /* Index7 3.9dB */ 0x64400191, + /* Index8 3.6dB */ 0x60c00183, + /* Index9 3.3dB */ 0x5d800176, + /* Index10 3 dB */ 0x5a80016a, + /* Index11 2.7dB */ 0x5740015d, + /* Index12 2.4dB */ 0x54400151, + /* Index13 2.1dB */ 0x51800146, + /* Index14 1.8dB */ 0x4ec0013b, + /* Index15 1.5dB */ 0x4c000130, + /* Index16 1.2dB */ 0x49800126, + /* Index17 0.9dB */ 0x4700011c, + /* Index18 0.6dB */ 0x44800112, + /* Index19 0.3dB */ 0x42000108, + /* Index20 0 dB */ 0x40000100, // 20 This is OFDM base index + /* Index21 -0.3dB */ 0x3dc000f7, + /* Index22 -0.6dB */ 0x3bc000ef, + /* Index23 -0.9dB */ 0x39c000e7, + /* Index24 -1.2dB */ 0x37c000df, + /* Index25 -1.5dB */ 0x35c000d7, + /* Index26 -1.8dB */ 0x340000d0, + /* Index27 -2.1dB */ 0x324000c9, + /* Index28 -2.4dB */ 0x308000c2, + /* Index29 -2.7dB */ 0x2f0000bc, + /* Index30 -3 dB */ 0x2d4000b5, + /* Index31 -3.3dB */ 0x2bc000af, + /* Index32 -3.6dB */ 0x2a4000a9, + /* Index33 -3.9dB */ 0x28c000a3, + /* Index34 -4.2dB */ 0x2780009e, + /* Index35 -4.5dB */ 0x26000098, + /* Index36 -4.8dB */ 0x24c00093, + /* Index37 -5.1dB */ 0x2380008e, + /* Index38 -5.4dB */ 0x22400089, + /* Index39 -5.7dB */ 0x21400085, + /* Index40 -6 dB */ 0x20000080, + /* Index41 -6.3dB */ 0x1f00007c, + /* Index42 -6.6dB */ 0x1e000078, + /* Index43 -6.9dB */ 0x1d000074, + /* Index44 -7.2dB */ 0x1c000070, + /* Index45 -7.5dB */ 0x1b00006c, + /* Index46 -7.8dB */ 0x1a000068, + /* Index47 -8.1dB */ 0x19400065, + /* Index48 -8.4dB */ 0x18400061, + /* Index49 -8.7dB */ 0x1780005e, + /* Index50 -9 dB */ 0x16c0005b, + /* Index51 -9.3dB */ 0x16000058, + /* Index52 -9.6dB */ 0x15400055, + /* Index53 -9.9dB */ 0x14800052 +}; +u1Byte CCKSwingTable_Ch1_Ch13_92E[CCK_TABLE_SIZE_92E][8] = { + /* Index0 0 dB */ {0x36, 0x34 , 0x2E , 0x26 , 0x1C , 0x12 , 0x08 , 0x04}, + /* Index1 -0.3dB */ {0x34, 0x32 , 0x2C , 0x25 , 0x1B , 0x11 , 0x08 , 0x04}, + /* Index2 -0.6dB */ {0x32, 0x30 , 0x2B , 0x23 , 0x1A , 0x11 , 0x07 , 0x04}, + /* Index3 -0.9dB */ {0x31, 0x2F , 0x29 , 0x22 , 0x19 , 0x10 , 0x07 , 0x04}, + /* Index4 -1.2dB */ {0x2F, 0x2D , 0x28 , 0x21 , 0x18 , 0x10 , 0x07 , 0x03}, + /* Index5 -1.5dB */ {0x2D, 0x2C , 0x27 , 0x20 , 0x18 , 0x0F , 0x07 , 0x03}, + /* Index6 -1.8dB */ {0x2C, 0x2A , 0x25 , 0x1F , 0x17 , 0x0F , 0x06 , 0x03}, + /* Index7 -2.1dB */ {0x2A, 0x29 , 0x24 , 0x1E , 0x16 , 0x0E , 0x06 , 0x03}, + /* Index8 -2.4dB */ {0x29, 0x27 , 0x23 , 0x1D , 0x15 , 0x0E , 0x06 , 0x03}, + /* Index9 -2.7dB */ {0x27, 0x26 , 0x22 , 0x1C , 0x14 , 0x0D , 0x06 , 0x03}, + /* Index10 -3 dB */ {0x26, 0x25 , 0x20 , 0x1B , 0x14 , 0x0D , 0x06 , 0x03}, + /* Index11 -3.3dB */ {0x25, 0x23 , 0x1F , 0x1A , 0x13 , 0x0C , 0x05 , 0x03}, + /* Index12 -3.6dB */ {0x24, 0x22 , 0x1E , 0x19 , 0x12 , 0x0C , 0x05 , 0x03}, + /* Index13 -3.9dB */ {0x22, 0x21 , 0x1D , 0x18 , 0x12 , 0x0B , 0x05 , 0x03}, + /* Index14 -4.2dB */ {0x21, 0x20 , 0x1C , 0x17 , 0x11 , 0x0B , 0x05 , 0x02}, + /* Index15 -4.5dB */ {0x20, 0x1F , 0x1B , 0x17 , 0x11 , 0x0B , 0x05 , 0x02}, + /* Index16 -4.8dB */ {0x1F, 0x1E , 0x1A , 0x16 , 0x10 , 0x0A , 0x05 , 0x02}, + /* Index17 -5.1dB */ {0x1E, 0x1D , 0x1A , 0x15 , 0x10 , 0x0A , 0x04 , 0x02}, + /* Index18 -5.4dB */ {0x1D, 0x1C , 0x19 , 0x14 , 0x0F , 0x0A , 0x04 , 0x02}, + /* Index19 -5.7dB */ {0x1C, 0x1B , 0x18 , 0x14 , 0x0E , 0x09 , 0x04 , 0x02}, + /* Index20 -6.0dB */ {0x1B, 0x1A , 0x17 , 0x13 , 0x0E , 0x09 , 0x04 , 0x02}, // 20 This is CCK base index + /* Index21 -6.3dB */ {0x1A, 0x19 , 0x16 , 0x12 , 0x0E , 0x09 , 0x04 , 0x02}, + /* Index22 -6.6dB */ {0x19, 0x18 , 0x15 , 0x12 , 0x0D , 0x08 , 0x04 , 0x02}, + /* Index23 -6.9dB */ {0x18, 0x17 , 0x15 , 0x11 , 0x0D , 0x08 , 0x04 , 0x02}, + /* Index24 -7.2dB */ {0x18, 0x17 , 0x14 , 0x11 , 0x0C , 0x08 , 0x03 , 0x02}, + /* Index25 -7.5dB */ {0x17, 0x16 , 0x13 , 0x10 , 0x0C , 0x08 , 0x03 , 0x02}, + /* Index26 -7.8dB */ {0x16, 0x15 , 0x13 , 0x0F , 0x0B , 0x07 , 0x03 , 0x02}, + /* Index27 -8.1dB */ {0x15, 0x14 , 0x12 , 0x0F , 0x0B , 0x07 , 0x03 , 0x02}, + /* Index28 -8.4dB */ {0x14, 0x14 , 0x11 , 0x0E , 0x0B , 0x07 , 0x03 , 0x02}, + /* Index29 -8.7dB */ {0x14, 0x13 , 0x11 , 0x0E , 0x0A , 0x07 , 0x03 , 0x01}, + /* Index30 -9.0dB */ {0x13, 0x12 , 0x10 , 0x0D , 0x0A , 0x06 , 0x03 , 0x01}, // 30 This is hp CCK base index + /* Index31 -9.3dB */ {0x12, 0x12 , 0x0F , 0x0D , 0x0A , 0x06 , 0x03 , 0x01}, + /* Index32 -9.6dB */ {0x12, 0x11 , 0x0F , 0x0D , 0x09 , 0x06 , 0x03 , 0x01}, + /* Index33 -9.9dB */ {0x11, 0x11 , 0x0F , 0x0C , 0x09 , 0x06 , 0x03 , 0x01}, + /* Index34 -10.2dB */ {0x11, 0x11 , 0x0E , 0x0C , 0x09 , 0x06 , 0x02 , 0x01}, + /* Index35 -10.5dB */ {0x10, 0x0F , 0x0E , 0x0B , 0x08 , 0x05 , 0x02 , 0x01}, + /* Index36 -10.8dB */ {0x10, 0x0F , 0x0D , 0x0B , 0x08 , 0x05 , 0x02 , 0x01}, + /* Index37 -11.1dB */ {0x0F, 0x0E , 0x0D , 0x0A , 0x08 , 0x05 , 0x02 , 0x01}, + /* Index38 -11.4dB */ {0x0E, 0x0E , 0x0C , 0x0A , 0x07 , 0x05 , 0x02 , 0x01}, + /* Index39 -11.7dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x07 , 0x05 , 0x02 , 0x01}, + /* Index40 -12 dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x07 , 0x05 , 0x02 , 0x01}, + /* Index41 -12.3dB */ {0x0D, 0x0D , 0x0B , 0x09 , 0x07 , 0x04 , 0x02 , 0x01}, + /* Index42 -12.6dB */ {0x0D, 0x0C , 0x0B , 0x09 , 0x07 , 0x04 , 0x02 , 0x01}, + /* Index43 -12.9dB */ {0x0C, 0x0C , 0x0A , 0x09 , 0x06 , 0x04 , 0x02 , 0x01}, + /* Index44 -13.2dB */ {0x0C, 0x0B , 0x0A , 0x08 , 0x06 , 0x04 , 0x02 , 0x01}, + /* Index45 -13.5dB */ {0x0B, 0x0B , 0x0A , 0x08 , 0x06 , 0x04 , 0x02 , 0x01}, + /* Index46 -13.8dB */ {0x0B, 0x0B , 0x09 , 0x08 , 0x06 , 0x04 , 0x02 , 0x01}, + /* Index47 -14.1dB */ {0x0B, 0x0A , 0x09 , 0x07 , 0x06 , 0x04 , 0x02 , 0x01}, + /* Index48 -14.4dB */ {0x0A, 0x0A , 0x09 , 0x07 , 0x05 , 0x03 , 0x02 , 0x01}, + /* Index49 -14.7dB */ {0x0A, 0x0A , 0x08 , 0x07 , 0x05 , 0x03 , 0x01 , 0x01}, + /* Index50 -15 dB */ {0x0A, 0x09 , 0x08 , 0x07 , 0x05 , 0x03 , 0x01 , 0x01}, + /* Index51 -15.3dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x05 , 0x03 , 0x01 , 0x01}, + /* Index52 -15.6dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x05 , 0x03 , 0x01 , 0x01}, + /* Index53 -15.9dB */ {0x09, 0x08 , 0x07 , 0x06 , 0x04 , 0x03 , 0x01 , 0x01} +}; +u1Byte CCKSwingTable_Ch14_92E[CCK_TABLE_SIZE_92E][8] = { + /* Index0 0 dB */ {0x36, 0x34 , 0x2E , 0x26 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index1 -0.3dB */ {0x34, 0x32 , 0x2C , 0x25 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index2 -0.6dB */ {0x32, 0x30 , 0x2B , 0x23 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index3 -0.9dB */ {0x31, 0x2F , 0x29 , 0x22 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index4 -1.2dB */ {0x2F, 0x2D , 0x28 , 0x21 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index5 -1.5dB */ {0x2D, 0x2C , 0x27 , 0x20 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index6 -1.8dB */ {0x2C, 0x2A , 0x25 , 0x1F , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index7 -2.1dB */ {0x2A, 0x29 , 0x24 , 0x1E , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index8 -2.4dB */ {0x29, 0x27 , 0x23 , 0x1D , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index9 -2.7dB */ {0x27, 0x26 , 0x22 , 0x1C , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index10 -3 dB */ {0x26, 0x25 , 0x20 , 0x1B , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index11 -3.3dB */ {0x25, 0x23 , 0x1F , 0x1A , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index12 -3.6dB */ {0x24, 0x22 , 0x1E , 0x19 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index13 -3.9dB */ {0x22, 0x21 , 0x1D , 0x18 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index14 -4.2dB */ {0x21, 0x20 , 0x1C , 0x17 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index15 -4.5dB */ {0x20, 0x1F , 0x1B , 0x17 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index16 -4.8dB */ {0x1F, 0x1E , 0x1A , 0x16 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index17 -5.1dB */ {0x1E, 0x1D , 0x1A , 0x15 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index18 -5.4dB */ {0x1D, 0x1C , 0x19 , 0x14 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index19 -5.7dB */ {0x1C, 0x1B , 0x18 , 0x14 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index20 -6 dB */ {0x1B, 0x1A , 0x17 , 0x13 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index21 -6.3dB */ {0x1A, 0x19 , 0x16 , 0x12 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index22 -6.6dB */ {0x19, 0x18 , 0x15 , 0x12 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index23 -6.9dB */ {0x18, 0x17 , 0x15 , 0x11 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index24 -7.2dB */ {0x18, 0x17 , 0x14 , 0x11 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index25 -7.5dB */ {0x17, 0x16 , 0x13 , 0x10 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index26 -7.8dB */ {0x16, 0x15 , 0x13 , 0x0F , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index27 -8.1dB */ {0x15, 0x14 , 0x12 , 0x0F , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index28 -8.4dB */ {0x14, 0x14 , 0x11 , 0x0E , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index29 -8.7dB */ {0x14, 0x13 , 0x11 , 0x0E , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index30 -9 dB */ {0x13, 0x12 , 0x10 , 0x0D , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index31 -9.3dB */ {0x12, 0x12 , 0x0F , 0x0D , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index32 -9.6dB */ {0x12, 0x11 , 0x0F , 0x0D , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index33 -9.9dB */ {0x11, 0x11 , 0x0F , 0x0C , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index34 -10.2dB */ {0x11, 0x11 , 0x0E , 0x0C , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index35 -10.5dB */ {0x10, 0x0F , 0x0E , 0x0B , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index36 -10.8dB */ {0x10, 0x0F , 0x0D , 0x0B , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index37 -11.1dB */ {0x0F, 0x0E , 0x0D , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index38 -11.4dB */ {0x0E, 0x0E , 0x0C , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index39 -11.7dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index40 -12 dB */ {0x0E, 0x0D , 0x0C , 0x0A , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index41 -12.3dB */ {0x0D, 0x0D , 0x0B , 0x09 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index42 -12.6dB */ {0x0D, 0x0C , 0x0B , 0x09 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index43 -12.9dB */ {0x0C, 0x0C , 0x0A , 0x09 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index44 -13.2dB */ {0x0C, 0x0B , 0x0A , 0x08 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index45 -13.5dB */ {0x0B, 0x0B , 0x0A , 0x08 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index46 -13.8dB */ {0x0B, 0x0B , 0x09 , 0x08 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index47 -14.1dB */ {0x0B, 0x0A , 0x09 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index48 -14.4dB */ {0x0A, 0x0A , 0x09 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index49 -14.7dB */ {0x0A, 0x0A , 0x08 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index50 -15 dB */ {0x0A, 0x09 , 0x08 , 0x07 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index51 -15.3dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index52 -15.6dB */ {0x09, 0x09 , 0x08 , 0x06 , 0x00 , 0x00 , 0x00 , 0x00}, + /* Index53 -15.9dB */ {0x09, 0x08 , 0x07 , 0x06 , 0x00 , 0x00 , 0x00 , 0x00} +}; +#endif + +#if(RTL8814A_SUPPORT == 1) +u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE] = +{ + 0x081, // 0, -12.0dB + 0x088, // 1, -11.5dB + 0x090, // 2, -11.0dB + 0x099, // 3, -10.5dB + 0x0A2, // 4, -10.0dB + 0x0AC, // 5, -9.5dB + 0x0B6, // 6, -9.0dB + 0x0C0, // 7, -8.5dB + 0x0CC, // 8, -8.0dB + 0x0D8, // 9, -7.5dB + 0x0E5, // 10, -7.0dB + 0x0F2, // 11, -6.5dB + 0x101, // 12, -6.0dB + 0x110, // 13, -5.5dB + 0x120, // 14, -5.0dB + 0x131, // 15, -4.5dB + 0x143, // 16, -4.0dB + 0x156, // 17, -3.5dB + 0x16A, // 18, -3.0dB + 0x180, // 19, -2.5dB + 0x197, // 20, -2.0dB + 0x1AF, // 21, -1.5dB + 0x1C8, // 22, -1.0dB + 0x1E3, // 23, -0.5dB + 0x200, // 24, +0 dB + 0x21E, // 25, +0.5dB + 0x23E, // 26, +1.0dB + 0x261, // 27, +1.5dB + 0x285, // 28, +2.0dB + 0x2AB, // 29, +2.5dB + 0x2D3, // 30, +3.0dB + 0x2FE, // 31, +3.5dB + 0x32B, // 32, +4.0dB + 0x35C, // 33, +4.5dB + 0x38E, // 34, +5.0dB + 0x3C4, // 35, +5.5dB + 0x3FE // 36, +6.0dB +}; +#elif(ODM_IC_11AC_SERIES_SUPPORT) +u4Byte OFDMSwingTable_8812[OFDM_TABLE_SIZE_8812] = { + 0x3FE, // 0, (6dB) + 0x3C4, // 1, (5.5dB) + 0x38E, // 2, (5dB) + 0x35C, // 3, (4.5dB) + 0x32B, // 4, (4dB) + 0x2FE, // 5, (3.5dB) + 0x2D3, // 6, (3dB) + 0x2AB, // 7, (2.5dB) + 0x285, // 8, (2dB) + 0x261, // 9, (1.5dB + 0x23E, // 10, (1dB) + 0x21E, // 11, (0.5dB) + 0x200, // 12, (0dB) 8814 int PA 2G default + 0x1E3, // 13, (-0.5dB) + 0x1C8, // 14, (-1dB) + 0x1AF, // 15, (-1.5dB) + 0x197, // 16, (-2dB) + 0x180, // 17, (-2.5dB) + 0x16A, // 18, (-3dB) 8812 / 8814 int PA 5G / 8814 ext PA 2G5G default + 0x156, // 19, (-3.5dB) + 0x143, // 20, (-4dB) 8812 HP default + 0x131, // 21, (-4.5dB) + 0x120, // 22, (-5dB) + 0x110, // 23, (-5.5dB) + 0x101, // 24, (-6dB) + 0x0F2, // 25, (-6.5dB) + 0x0E5, // 26, (-7dB) + 0x0D8, // 27, (-7.5dB) + 0x0CC, // 28, (-8dB) + 0x0C0, // 29, (-8.5dB) + 0x0B6, // 30, (-9dB) + 0x0AC, // 31, (-9.5dB) + 0x0A2, // 32, (-10dB) + 0x099, // 33, (-10.5dB) + 0x090, // 34, (-11dB) + 0x088, // 35, (-11.5dB) + 0x081, // 36, (-12dB) + 0x079, // 37, (-12.5dB) + 0x072, // 38, (-13dB) + 0x06c, // 39, (-13.5dB) + 0x066, // 40, (-14dB) + 0x060, // 41, (-14.5dB) + 0x05B // 42, (-15dB) +}; +#endif + +//#endif +//3============================================================ +//3 Tx Power Tracking +//3============================================================ + +VOID +odm_TXPowerTrackingInit( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + if(!(pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_IC_11N_SERIES))) + return; +#endif + + odm_TXPowerTrackingThermalMeterInit(pDM_Odm); +} + + +VOID +odm_TXPowerTrackingThermalMeterInit( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + u1Byte p; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + pMgntInfo->bTXPowerTracking = TRUE; + pHalData->TXPowercount = 0; + pHalData->bTXPowerTrackingInit = FALSE; + + if(pDM_Odm->mp_mode == FALSE) + pHalData->TxPowerTrackControl = TRUE; + ODM_RT_TRACE(pDM_Odm,COMP_POWER_TRACKING, DBG_LOUD, ("pMgntInfo->bTXPowerTracking = %d\n", pMgntInfo->bTXPowerTracking)); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #ifdef CONFIG_RTL8188E + { + pDM_Odm->RFCalibrateInfo.bTXPowerTracking = _TRUE; + pDM_Odm->RFCalibrateInfo.TXPowercount = 0; + pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = _FALSE; + + if(pDM_Odm->mp_mode == FALSE) + pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE; + + MSG_8192C("pDM_Odm TxPowerTrackControl = %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl); + } + #else + { + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct dm_priv *pdmpriv = &pHalData->dmpriv; + + //if(IS_HARDWARE_TYPE_8192C(pHalData)) + { + pdmpriv->bTXPowerTracking = _TRUE; + pdmpriv->TXPowercount = 0; + pdmpriv->bTXPowerTrackingInit = _FALSE; + + if(pDM_Odm->mp_mode == FALSE) //for mp driver, turn off txpwrtracking as default + pdmpriv->TxPowerTrackControl = _TRUE; + + } + MSG_8192C("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl); + + } + #endif//endif (CONFIG_RTL8188E==1) +#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + + #ifdef RTL8188E_SUPPORT + { + pDM_Odm->RFCalibrateInfo.bTXPowerTracking = _TRUE; + pDM_Odm->RFCalibrateInfo.TXPowercount = 0; + pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = _FALSE; + pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE; + pDM_Odm->RFCalibrateInfo.TM_Trigger = 0; + } + #endif +#endif + + pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = TRUE; + pDM_Odm->RFCalibrateInfo.DeltaPowerIndex = 0; + pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast = 0; + pDM_Odm->RFCalibrateInfo.PowerIndexOffset = 0; + pDM_Odm->RFCalibrateInfo.ThermalValue = 0; + pRFCalibrateInfo->DefaultOfdmIndex = 28; + + +#if RTL8188E_SUPPORT + pRFCalibrateInfo->DefaultCckIndex = 20; // -6 dB +#elif RTL8192E_SUPPORT + pRFCalibrateInfo->DefaultCckIndex = 8; // -12 dB +#endif + pRFCalibrateInfo->BbSwingIdxOfdmBase = pRFCalibrateInfo->DefaultOfdmIndex; + pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->DefaultCckIndex; + pDM_Odm->RFCalibrateInfo.CCK_index = pRFCalibrateInfo->DefaultCckIndex; + for(p = 0; p < MAX_RF_PATH; p++) + { + pDM_Odm->RFCalibrateInfo.OFDM_index[p] = pRFCalibrateInfo->DefaultOfdmIndex; + pRFCalibrateInfo->BbSwingIdxOfdm[p] = pRFCalibrateInfo->DefaultOfdmIndex; + pRFCalibrateInfo->KfreeOffset[p] = 0; // for 8814 kfree + } + pRFCalibrateInfo->BbSwingIdxCck = pRFCalibrateInfo->DefaultCckIndex; + +} + + +VOID +ODM_TXPowerTrackingCheck( + IN PVOID pDM_VOID + ) +{ + // + // For AP/ADSL use prtl8192cd_priv + // For CE/NIC use PADAPTER + // + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + + + if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) + return; + + // + // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate + // at the same time. In the stage2/3, we need to prive universal interface and merge all + // HW dynamic mechanism. + // + switch (pDM_Odm->SupportPlatform) + { + case ODM_WIN: + odm_TXPowerTrackingCheckMP(pDM_Odm); + break; + + case ODM_CE: + odm_TXPowerTrackingCheckCE(pDM_Odm); + break; + + case ODM_AP: + odm_TXPowerTrackingCheckAP(pDM_Odm); + break; + default: + break; + } + +} + +VOID +odm_TXPowerTrackingCheckCE( + IN PVOID pDM_VOID + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + + #if(RTL8188E_SUPPORT==1) + + //if(!pMgntInfo->bTXPowerTracking /*|| (!pdmpriv->TxPowerTrackControl && pdmpriv->bAPKdone)*/) + if(!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) + { + return; + } + + if(!pDM_Odm->RFCalibrateInfo.TM_Trigger) //at least delay 1 sec + { + //pHalData->TxPowerCheckCnt++; //cosa add for debug + ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); + //DBG_8192C("Trigger 92C Thermal Meter!!\n"); + + pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; + return; + + } + else + { + //DBG_8192C("Schedule TxPowerTracking direct call!!\n"); + odm_TXPowerTrackingCallback_ThermalMeter_8188E(Adapter); + pDM_Odm->RFCalibrateInfo.TM_Trigger = 0; + } + #endif + +#endif +} + +VOID +odm_TXPowerTrackingCheckMP( + IN PVOID pDM_VOID + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + + if (ODM_CheckPowerStatus(Adapter) == FALSE) + return; + + if(!Adapter->bSlaveOfDMSP || Adapter->DualMacSmartConcurrent == FALSE) + odm_TXPowerTrackingThermalMeterCheck(Adapter); +#endif + +} + + +VOID +odm_TXPowerTrackingCheckAP( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + prtl8192cd_priv priv = pDM_Odm->priv; + +#if ((RTL8188E_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8812A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) || (RTL8814A_SUPPORT == 1)) + if (pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8812|ODM_RTL8881A|ODM_RTL8814A)) + ODM_TXPowerTrackingCallback_ThermalMeter(pDM_Odm); + else +#endif + { + } +#endif + +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +VOID +odm_TXPowerTrackingThermalMeterCheck( + IN PADAPTER Adapter + ) +{ +#ifndef AP_BUILD_WORKAROUND +#if (HAL_CODE_BASE==RTL8192_C) + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + static u1Byte TM_Trigger = 0; + //u1Byte TxPowerCheckCnt = 5; //10 sec + + if(!pMgntInfo->bTXPowerTracking /*|| (!pHalData->TxPowerTrackControl && pHalData->bAPKdone)*/) + { + return; + } + + if(!TM_Trigger) //at least delay 1 sec + { + if (IS_HARDWARE_TYPE_8188E(Adapter) || IS_HARDWARE_TYPE_8812(Adapter)) + PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); + else + PHY_SetRFReg(Adapter, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Trigger 92C Thermal Meter!!\n")); + + TM_Trigger = 1; + return; + } + else + { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Schedule TxPowerTracking direct call!!\n")); + odm_TXPowerTrackingDirectCall(Adapter); //Using direct call is instead, added by Roger, 2009.06.18. + TM_Trigger = 0; + } +#endif +#endif +} + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_powertracking_ap.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_powertracking_ap.h new file mode 100644 index 000000000..8c7c2867e --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_powertracking_ap.h @@ -0,0 +1,314 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMPOWERTRACKING_H__ +#define __PHYDMPOWERTRACKING_H__ + +#define POWRTRACKING_VERSION "1.1" + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +#ifdef RTK_AC_SUPPORT +#define ODM_IC_11AC_SERIES_SUPPORT 1 +#else +#define ODM_IC_11AC_SERIES_SUPPORT 0 +#endif +#else +#define ODM_IC_11AC_SERIES_SUPPORT 1 +#endif + +#define DPK_DELTA_MAPPING_NUM 13 +#define index_mapping_HP_NUM 15 +#define DELTA_SWINGIDX_SIZE 30 +#define BAND_NUM 3 +#define MAX_RF_PATH 4 +#define TXSCALE_TABLE_SIZE 37 +#define IQK_MAC_REG_NUM 4 +#define IQK_ADDA_REG_NUM 16 +#define IQK_BB_REG_NUM_MAX 10 + +#define IQK_BB_REG_NUM 9 + +#define HP_THERMAL_NUM 8 + +#define AVG_THERMAL_NUM 8 +#define IQK_Matrix_REG_NUM 8 +//#define IQK_Matrix_Settings_NUM 1+24+21 +#define IQK_Matrix_Settings_NUM (14+24+21) // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G + +#if !defined(_OUTSRC_COEXIST) +#define OFDM_TABLE_SIZE_92D 43 +#define OFDM_TABLE_SIZE 37 +#define CCK_TABLE_SIZE 33 +#define CCK_TABLE_SIZE_88F 21 + + + +//#define OFDM_TABLE_SIZE_92E 54 +//#define CCK_TABLE_SIZE_92E 54 +extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE_92D]; +extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]; + + +extern u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE_92D]; +extern u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch14_New [CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16]; + +#endif + +#define ODM_OFDM_TABLE_SIZE 37 +#define ODM_CCK_TABLE_SIZE 33 +// <20140613, YuChen> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. +extern u1Byte DeltaSwingTableIdx_2GA_P_DEFAULT[DELTA_SWINGIDX_SIZE]; +extern u1Byte DeltaSwingTableIdx_2GA_N_DEFAULT[DELTA_SWINGIDX_SIZE]; + + +//extern u4Byte OFDMSwingTable_92E[OFDM_TABLE_SIZE_92E]; +//extern u1Byte CCKSwingTable_Ch1_Ch13_92E[CCK_TABLE_SIZE_92E][8]; +//extern u1Byte CCKSwingTable_Ch14_92E[CCK_TABLE_SIZE_92E][8]; + +#ifdef CONFIG_WLAN_HAL_8192EE +#define OFDM_TABLE_SIZE_92E 54 +#define CCK_TABLE_SIZE_92E 54 +extern u4Byte OFDMSwingTable_92E[OFDM_TABLE_SIZE_92E]; +extern u1Byte CCKSwingTable_Ch1_Ch13_92E[CCK_TABLE_SIZE_92E][8]; +extern u1Byte CCKSwingTable_Ch14_92E[CCK_TABLE_SIZE_92E][8]; +#endif + +#define OFDM_TABLE_SIZE_8812 43 +#define AVG_THERMAL_NUM_8812 4 + +#if(RTL8814A_SUPPORT == 1) +extern u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE]; +#elif(ODM_IC_11AC_SERIES_SUPPORT) +extern unsigned int OFDMSwingTable_8812[OFDM_TABLE_SIZE_8812]; +#endif + +#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck + +typedef struct _IQK_MATRIX_REGS_SETTING{ + BOOLEAN bIQKDone; + s4Byte Value[1][IQK_Matrix_REG_NUM]; +}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING; + +typedef struct ODM_RF_Calibration_Structure +{ + //for tx power tracking + + u4Byte RegA24; // for TempCCK + s4Byte RegE94; + s4Byte RegE9C; + s4Byte RegEB4; + s4Byte RegEBC; + + //u1Byte bTXPowerTracking; + u1Byte TXPowercount; + BOOLEAN bTXPowerTrackingInit; + BOOLEAN bTXPowerTracking; + u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default + u1Byte TM_Trigger; + u1Byte InternalPA5G[2]; //pathA / pathB + + u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 + u1Byte ThermalValue; + u1Byte ThermalValue_LCK; + u1Byte ThermalValue_IQK; + u1Byte ThermalValue_DPK; + u1Byte ThermalValue_AVG[AVG_THERMAL_NUM]; + u1Byte ThermalValue_AVG_index; + u1Byte ThermalValue_RxGain; + u1Byte ThermalValue_Crystal; + u1Byte ThermalValue_DPKstore; + u1Byte ThermalValue_DPKtrack; + BOOLEAN TxPowerTrackingInProgress; + BOOLEAN bDPKenable; + + BOOLEAN bReloadtxpowerindex; + u1Byte bRfPiEnable; + u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug + + u1Byte bCCKinCH14; + u1Byte CCK_index; + u1Byte OFDM_index[MAX_RF_PATH]; + s1Byte PowerIndexOffset; + s1Byte DeltaPowerIndex; + s1Byte DeltaPowerIndexLast; + BOOLEAN bTxPowerChanged; + + u1Byte ThermalValue_HP[HP_THERMAL_NUM]; + u1Byte ThermalValue_HP_index; + IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; + BOOLEAN bNeedIQK; + u1Byte Delta_IQK; + u1Byte Delta_LCK; + u1Byte DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKC_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKC_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKD_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKD_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GC_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GC_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GD_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GD_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GC_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GC_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GD_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GD_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE]; + + u1Byte BbSwingIdxOfdm[MAX_RF_PATH]; + u1Byte BbSwingIdxOfdmCurrent; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + u1Byte BbSwingIdxOfdmBase[MAX_RF_PATH]; +#else + u1Byte BbSwingIdxOfdmBase; +#endif + BOOLEAN BbSwingFlagOfdm; + u1Byte BbSwingIdxCck; + u1Byte BbSwingIdxCckCurrent; + u1Byte BbSwingIdxCckBase; + u1Byte DefaultOfdmIndex; + u1Byte DefaultCckIndex; + BOOLEAN BbSwingFlagCck; + + s1Byte Absolute_OFDMSwingIdx[MAX_RF_PATH]; + s1Byte Remnant_OFDMSwingIdx[MAX_RF_PATH]; + s1Byte Remnant_CCKSwingIdx; + s1Byte Modify_TxAGC_Value; /*Remnat compensate value at TxAGC */ + BOOLEAN Modify_TxAGC_Flag_PathA; + BOOLEAN Modify_TxAGC_Flag_PathB; + BOOLEAN Modify_TxAGC_Flag_PathC; + BOOLEAN Modify_TxAGC_Flag_PathD; + BOOLEAN Modify_TxAGC_Flag_PathA_CCK; + + s1Byte KfreeOffset[MAX_RF_PATH]; + + //--------------------------------------------------------------------// + + //for IQK + u4Byte RegC04; + u4Byte Reg874; + u4Byte RegC08; + u4Byte RegB68; + u4Byte RegB6C; + u4Byte Reg870; + u4Byte Reg860; + u4Byte Reg864; + + BOOLEAN bIQKInitialized; + BOOLEAN bLCKInProgress; + BOOLEAN bAntennaDetected; + u4Byte ADDA_backup[IQK_ADDA_REG_NUM]; + u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM]; + u4Byte IQK_BB_backup_recover[9]; + u4Byte IQK_BB_backup[IQK_BB_REG_NUM]; + + //for APK + u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a + u1Byte bAPKdone; + u1Byte bAPKThermalMeterIgnore; + u1Byte bDPdone; + u1Byte bDPPathAOK; + u1Byte bDPPathBOK; + + /*Add by Yuchen for Kfree Phydm*/ + u1Byte RegRfKFreeEnable; /*for registry*/ + u1Byte RfKFreeEnable; /*for efuse enable check*/ + +}ODM_RF_CAL_T,*PODM_RF_CAL_T; + +VOID +odm_TXPowerTrackingCheckAP( + IN PVOID pDM_VOID + ); + +VOID +ODM_TXPowerTrackingCheck( + IN PVOID pDM_VOID + ); + + +VOID +odm_TXPowerTrackingThermalMeterInit( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingInit( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingCheckMP( + IN PVOID pDM_VOID + ); + + +VOID +odm_TXPowerTrackingCheckCE( + IN PVOID pDM_VOID + ); + + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + +VOID +odm_TXPowerTrackingCallbackThermalMeter92C( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingCallbackRXGainThermalMeter92D( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingCallbackThermalMeter92D( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingDirectCall92C( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingThermalMeterCheck( + IN PADAPTER Adapter + ); + +#endif + + + +#endif diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_powertracking_ce.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_powertracking_ce.c new file mode 100644 index 000000000..b8fe78407 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_powertracking_ce.c @@ -0,0 +1,670 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +/*============================================================ */ +/* include files */ +/*============================================================ */ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +//============================================================ +// Global var +//============================================================ + +u4Byte OFDMSwingTable[OFDM_TABLE_SIZE] = { + 0x7f8001fe, // 0, +6.0dB + 0x788001e2, // 1, +5.5dB + 0x71c001c7, // 2, +5.0dB + 0x6b8001ae, // 3, +4.5dB + 0x65400195, // 4, +4.0dB + 0x5fc0017f, // 5, +3.5dB + 0x5a400169, // 6, +3.0dB + 0x55400155, // 7, +2.5dB + 0x50800142, // 8, +2.0dB + 0x4c000130, // 9, +1.5dB + 0x47c0011f, // 10, +1.0dB + 0x43c0010f, // 11, +0.5dB + 0x40000100, // 12, +0dB + 0x3c8000f2, // 13, -0.5dB + 0x390000e4, // 14, -1.0dB + 0x35c000d7, // 15, -1.5dB + 0x32c000cb, // 16, -2.0dB + 0x300000c0, // 17, -2.5dB + 0x2d4000b5, // 18, -3.0dB + 0x2ac000ab, // 19, -3.5dB + 0x288000a2, // 20, -4.0dB + 0x26000098, // 21, -4.5dB + 0x24000090, // 22, -5.0dB + 0x22000088, // 23, -5.5dB + 0x20000080, // 24, -6.0dB + 0x1e400079, // 25, -6.5dB + 0x1c800072, // 26, -7.0dB + 0x1b00006c, // 27. -7.5dB + 0x19800066, // 28, -8.0dB + 0x18000060, // 29, -8.5dB + 0x16c0005b, // 30, -9.0dB + 0x15800056, // 31, -9.5dB + 0x14400051, // 32, -10.0dB + 0x1300004c, // 33, -10.5dB + 0x12000048, // 34, -11.0dB + 0x11000044, // 35, -11.5dB + 0x10000040, // 36, -12.0dB +}; + +u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = { + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0dB + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 1, -0.5dB + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 2, -1.0dB + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 3, -1.5dB + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 4, -2.0dB + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 5, -2.5dB + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 6, -3.0dB + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 7, -3.5dB + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 8, -4.0dB + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 9, -4.5dB + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 10, -5.0dB + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 11, -5.5dB + {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 12, -6.0dB <== default + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 13, -6.5dB + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 14, -7.0dB + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 15, -7.5dB + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 17, -8.5dB + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 18, -9.0dB + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 19, -9.5dB + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 20, -10.0dB + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 21, -10.5dB + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 22, -11.0dB + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 23, -11.5dB + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 24, -12.0dB + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 25, -12.5dB + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 26, -13.0dB + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 27, -13.5dB + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 28, -14.0dB + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 29, -14.5dB + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 30, -15.0dB + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 31, -15.5dB + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} // 32, -16.0dB +}; + + +u1Byte CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = { + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0dB + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 1, -0.5dB + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 2, -1.0dB + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 3, -1.5dB + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 4, -2.0dB + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 5, -2.5dB + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 6, -3.0dB + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 7, -3.5dB + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 8, -4.0dB + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 9, -4.5dB + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 10, -5.0dB + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 11, -5.5dB + {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 12, -6.0dB <== default + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 13, -6.5dB + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 14, -7.0dB + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 15, -7.5dB + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 17, -8.5dB + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 18, -9.0dB + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 19, -9.5dB + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 20, -10.0dB + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 21, -10.5dB + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 22, -11.0dB + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 23, -11.5dB + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 24, -12.0dB + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 25, -12.5dB + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 26, -13.0dB + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 27, -13.5dB + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 28, -14.0dB + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 29, -14.5dB + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 30, -15.0dB + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 31, -15.5dB + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} // 32, -16.0dB +}; + + +u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE] = { + 0x0b40002d, // 0, -15.0dB + 0x0c000030, // 1, -14.5dB + 0x0cc00033, // 2, -14.0dB + 0x0d800036, // 3, -13.5dB + 0x0e400039, // 4, -13.0dB + 0x0f00003c, // 5, -12.5dB + 0x10000040, // 6, -12.0dB + 0x11000044, // 7, -11.5dB + 0x12000048, // 8, -11.0dB + 0x1300004c, // 9, -10.5dB + 0x14400051, // 10, -10.0dB + 0x15800056, // 11, -9.5dB + 0x16c0005b, // 12, -9.0dB + 0x18000060, // 13, -8.5dB + 0x19800066, // 14, -8.0dB + 0x1b00006c, // 15, -7.5dB + 0x1c800072, // 16, -7.0dB + 0x1e400079, // 17, -6.5dB + 0x20000080, // 18, -6.0dB + 0x22000088, // 19, -5.5dB + 0x24000090, // 20, -5.0dB + 0x26000098, // 21, -4.5dB + 0x288000a2, // 22, -4.0dB + 0x2ac000ab, // 23, -3.5dB + 0x2d4000b5, // 24, -3.0dB + 0x300000c0, // 25, -2.5dB + 0x32c000cb, // 26, -2.0dB + 0x35c000d7, // 27, -1.5dB + 0x390000e4, // 28, -1.0dB + 0x3c8000f2, // 29, -0.5dB + 0x40000100, // 30, +0dB + 0x43c0010f, // 31, +0.5dB + 0x47c0011f, // 32, +1.0dB + 0x4c000130, // 33, +1.5dB + 0x50800142, // 34, +2.0dB + 0x55400155, // 35, +2.5dB + 0x5a400169, // 36, +3.0dB + 0x5fc0017f, // 37, +3.5dB + 0x65400195, // 38, +4.0dB + 0x6b8001ae, // 39, +4.5dB + 0x71c001c7, // 40, +5.0dB + 0x788001e2, // 41, +5.5dB + 0x7f8001fe // 42, +6.0dB +}; + + +u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16] = { +{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ +{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ +{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ +{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ +{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ +{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ +{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ +{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ +{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ +{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ +{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ +{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ +{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ +{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ +{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ +{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ +{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ +{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ +{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ +{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ +{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + + +u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, // 0, -16.0dB + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 1, -15.5dB + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 2, -15.0dB + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 3, -14.5dB + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 4, -14.0dB + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 5, -13.5dB + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 6, -13.0dB + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 7, -12.5dB + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 8, -12.0dB + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 9, -11.5dB + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 10, -11.0dB + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 11, -10.5dB + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 12, -10.0dB + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 13, -9.5dB + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 14, -9.0dB + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 15, -8.5dB + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 17, -7.5dB + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 18, -7.0dB + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 19, -6.5dB + {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 20, -6.0dB + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 21, -5.5dB + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 22, -5.0dB + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 23, -4.5dB + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 24, -4.0dB + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 25, -3.5dB + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 26, -3.0dB + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 27, -2.5dB + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 28, -2.0dB + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 29, -1.5dB + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 30, -1.0dB + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 31, -0.5dB + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} // 32, +0dB +}; + + +u1Byte CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8]= { + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, // 0, -16.0dB + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 1, -15.5dB + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 2, -15.0dB + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 3, -14.5dB + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 4, -14.0dB + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 5, -13.5dB + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 6, -13.0dB + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 7, -12.5dB + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 8, -12.0dB + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 9, -11.5dB + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 10, -11.0dB + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 11, -10.5dB + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 12, -10.0dB + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 13, -9.5dB + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 14, -9.0dB + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 15, -8.5dB + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 17, -7.5dB + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 18, -7.0dB + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 19, -6.5dB + {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 20, -6.0dB + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 21, -5.5dB + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 22, -5.0dB + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 23, -4.5dB + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 24, -4.0dB + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 25, -3.5dB + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 26, -3.0dB + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 27, -2.5dB + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 28, -2.0dB + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 29, -1.5dB + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 30, -1.0dB + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 31, -0.5dB + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} // 32, +0dB +}; + +u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE] = +{ + 0x081, // 0, -12.0dB + 0x088, // 1, -11.5dB + 0x090, // 2, -11.0dB + 0x099, // 3, -10.5dB + 0x0A2, // 4, -10.0dB + 0x0AC, // 5, -9.5dB + 0x0B6, // 6, -9.0dB + 0x0C0, // 7, -8.5dB + 0x0CC, // 8, -8.0dB + 0x0D8, // 9, -7.5dB + 0x0E5, // 10, -7.0dB + 0x0F2, // 11, -6.5dB + 0x101, // 12, -6.0dB + 0x110, // 13, -5.5dB + 0x120, // 14, -5.0dB + 0x131, // 15, -4.5dB + 0x143, // 16, -4.0dB + 0x156, // 17, -3.5dB + 0x16A, // 18, -3.0dB + 0x180, // 19, -2.5dB + 0x197, // 20, -2.0dB + 0x1AF, // 21, -1.5dB + 0x1C8, // 22, -1.0dB + 0x1E3, // 23, -0.5dB + 0x200, // 24, +0 dB + 0x21E, // 25, +0.5dB + 0x23E, // 26, +1.0dB + 0x261, // 27, +1.5dB + 0x285, // 28, +2.0dB + 0x2AB, // 29, +2.5dB + 0x2D3, // 30, +3.0dB + 0x2FE, // 31, +3.5dB + 0x32B, // 32, +4.0dB + 0x35C, // 33, +4.5dB + 0x38E, // 34, +5.0dB + 0x3C4, // 35, +5.5dB + 0x3FE // 36, +6.0dB +}; + +#ifdef AP_BUILD_WORKAROUND + +unsigned int TxPwrTrk_OFDM_SwingTbl[TxPwrTrk_OFDM_SwingTbl_Len] = { + /* +6.0dB */ 0x7f8001fe, + /* +5.5dB */ 0x788001e2, + /* +5.0dB */ 0x71c001c7, + /* +4.5dB */ 0x6b8001ae, + /* +4.0dB */ 0x65400195, + /* +3.5dB */ 0x5fc0017f, + /* +3.0dB */ 0x5a400169, + /* +2.5dB */ 0x55400155, + /* +2.0dB */ 0x50800142, + /* +1.5dB */ 0x4c000130, + /* +1.0dB */ 0x47c0011f, + /* +0.5dB */ 0x43c0010f, + /* 0.0dB */ 0x40000100, + /* -0.5dB */ 0x3c8000f2, + /* -1.0dB */ 0x390000e4, + /* -1.5dB */ 0x35c000d7, + /* -2.0dB */ 0x32c000cb, + /* -2.5dB */ 0x300000c0, + /* -3.0dB */ 0x2d4000b5, + /* -3.5dB */ 0x2ac000ab, + /* -4.0dB */ 0x288000a2, + /* -4.5dB */ 0x26000098, + /* -5.0dB */ 0x24000090, + /* -5.5dB */ 0x22000088, + /* -6.0dB */ 0x20000080, + /* -6.5dB */ 0x1a00006c, + /* -7.0dB */ 0x1c800072, + /* -7.5dB */ 0x18000060, + /* -8.0dB */ 0x19800066, + /* -8.5dB */ 0x15800056, + /* -9.0dB */ 0x26c0005b, + /* -9.5dB */ 0x14400051, + /* -10.0dB */ 0x24400051, + /* -10.5dB */ 0x1300004c, + /* -11.0dB */ 0x12000048, + /* -11.5dB */ 0x11000044, + /* -12.0dB */ 0x10000040 +}; +#endif + + + +VOID +odm_TXPowerTrackingInit( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + if(!(pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_IC_11N_SERIES))) + return; +#endif + + odm_TXPowerTrackingThermalMeterInit(pDM_Odm); +} + +u1Byte +getSwingIndex( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u1Byte i = 0; + u4Byte bbSwing; + u4Byte swingTableSize; + pu4Byte pSwingTable; + + if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723B + || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8703B + ) { + bbSwing = PHY_QueryBBReg(Adapter, rOFDM0_XATxIQImbalance, 0xFFC00000); + + pSwingTable = OFDMSwingTable_New; + swingTableSize = OFDM_TABLE_SIZE; + } else { +#if ((RTL8812A_SUPPORT==1)||(RTL8821A_SUPPORT==1)) + if (pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8821) + { + bbSwing = PHY_GetTxBBSwing_8812A(Adapter, pHalData->CurrentBandType, ODM_RF_PATH_A); + pSwingTable = TxScalingTable_Jaguar; + swingTableSize = TXSCALE_TABLE_SIZE; + } + else +#endif + { + bbSwing = 0; + pSwingTable = OFDMSwingTable; + swingTableSize = OFDM_TABLE_SIZE; + } + } + + for (i = 0; i < swingTableSize; ++i) { + u4Byte tableValue = pSwingTable[i]; + + if (tableValue >= 0x100000 ) + tableValue >>= 22; + if (bbSwing == tableValue) + break; + } + return i; +} + +VOID +odm_TXPowerTrackingThermalMeterInit( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte defaultSwingIndex = getSwingIndex(pDM_Odm); + u1Byte p = 0; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + if(pDM_Odm->mp_mode == FALSE) + pHalData->TxPowerTrackControl = TRUE; +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + pRFCalibrateInfo->bTXPowerTracking = _TRUE; + pRFCalibrateInfo->TXPowercount = 0; + pRFCalibrateInfo->bTXPowerTrackingInit = _FALSE; + + if(pDM_Odm->mp_mode == FALSE) + pRFCalibrateInfo->TxPowerTrackControl = _TRUE; + else + pRFCalibrateInfo->TxPowerTrackControl = _FALSE; + + if(pDM_Odm->mp_mode == FALSE) + pRFCalibrateInfo->TxPowerTrackControl = _TRUE; + + + MSG_8192C("pDM_Odm TxPowerTrackControl = %d\n", pRFCalibrateInfo->TxPowerTrackControl); + +#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + #ifdef RTL8188E_SUPPORT + { + pRFCalibrateInfo->bTXPowerTracking = _TRUE; + pRFCalibrateInfo->TXPowercount = 0; + pRFCalibrateInfo->bTXPowerTrackingInit = _FALSE; + pRFCalibrateInfo->TxPowerTrackControl = _TRUE; + } + #endif +#endif + + //pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = TRUE; + pRFCalibrateInfo->ThermalValue = pHalData->EEPROMThermalMeter; + pRFCalibrateInfo->ThermalValue_IQK = pHalData->EEPROMThermalMeter; + pRFCalibrateInfo->ThermalValue_LCK = pHalData->EEPROMThermalMeter; + + // The index of "0 dB" in SwingTable. + if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723B || + pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8703B) { + pRFCalibrateInfo->DefaultOfdmIndex = (defaultSwingIndex >= OFDM_TABLE_SIZE) ? 30 : defaultSwingIndex; + pRFCalibrateInfo->DefaultCckIndex = 20; + } + else if(pDM_Odm->SupportICType == ODM_RTL8188F) //add by Mingzhi.Guo 2015-03-23 + { + pRFCalibrateInfo->DefaultOfdmIndex =28; //OFDM: -1dB + pRFCalibrateInfo->DefaultCckIndex =20; //CCK:-6dB + } + else + { + pRFCalibrateInfo->DefaultOfdmIndex = (defaultSwingIndex >= TXSCALE_TABLE_SIZE) ? 24 : defaultSwingIndex; + pRFCalibrateInfo->DefaultCckIndex = 24; + } + + pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->DefaultCckIndex; + pRFCalibrateInfo->CCK_index = pRFCalibrateInfo->DefaultCckIndex; + + for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) + { + pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->DefaultOfdmIndex; + pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->DefaultOfdmIndex; + pRFCalibrateInfo->DeltaPowerIndex[p] = 0; + pRFCalibrateInfo->DeltaPowerIndexLast[p] = 0; + pRFCalibrateInfo->PowerIndexOffset[p] = 0; + } + pRFCalibrateInfo->Modify_TxAGC_Value_OFDM=0; //add by Mingzhi.Guo + pRFCalibrateInfo->Modify_TxAGC_Value_CCK=0; //add by Mingzhi.Guo + +} + + +VOID +ODM_TXPowerTrackingCheck( + IN PVOID pDM_VOID + ) +{ + /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate + at the same time. In the stage2/3, we need to prive universal interface and merge all + HW dynamic mechanism. */ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + switch (pDM_Odm->SupportPlatform) + { + case ODM_WIN: + odm_TXPowerTrackingCheckMP(pDM_Odm); + break; + + case ODM_CE: + odm_TXPowerTrackingCheckCE(pDM_Odm); + break; + + case ODM_AP: + odm_TXPowerTrackingCheckAP(pDM_Odm); + break; + + default: + break; + } + +} + +VOID +odm_TXPowerTrackingCheckCE( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + + if (!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) + return; + + if(!pDM_Odm->RFCalibrateInfo.TM_Trigger) //at least delay 1 sec + { + //pHalData->TxPowerCheckCnt++; //cosa add for debug + if (IS_HARDWARE_TYPE_8188E(Adapter) || IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8192E(Adapter) + || IS_HARDWARE_TYPE_8723B(Adapter) + || IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter) + || IS_HARDWARE_TYPE_8703B(Adapter) + ) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_T_METER_NEW, (BIT17 | BIT16), 0x03); + } else { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_T_METER_OLD, bRFRegOffsetMask, 0x60); + } + + //DBG_871X("Trigger Thermal Meter!!\n"); + + pDM_Odm->RFCalibrateInfo.TM_Trigger = 1; + return; + } + else + { + //DBG_871X("Schedule TxPowerTracking direct call!!\n"); + ODM_TXPowerTrackingCallback_ThermalMeter(Adapter); + pDM_Odm->RFCalibrateInfo.TM_Trigger = 0; + } + +#endif +} + +VOID +odm_TXPowerTrackingCheckMP( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + + if (ODM_CheckPowerStatus(Adapter) == FALSE) + { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("===>ODM_CheckPowerStatus() return FALSE\n")); + return; + } + + if(!Adapter->bSlaveOfDMSP || Adapter->DualMacSmartConcurrent == FALSE) + odm_TXPowerTrackingThermalMeterCheck(Adapter); + else { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("!Adapter->bSlaveOfDMSP || Adapter->DualMacSmartConcurrent == FALSE\n")); + } +#endif + +} + + +VOID +odm_TXPowerTrackingCheckAP( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + prtl8192cd_priv priv = pDM_Odm->priv; + + return; + +#endif +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +odm_TXPowerTrackingThermalMeterCheck( + IN PADAPTER Adapter + ) +{ +#ifndef AP_BUILD_WORKAROUND + static u1Byte TM_Trigger = 0; + + if(!(GET_HAL_DATA(Adapter)->DM_OutSrc.SupportAbility & ODM_RF_TX_PWR_TRACK)) + { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, + ("===>odm_TXPowerTrackingThermalMeterCheck(),pMgntInfo->bTXPowerTracking is FALSE, return!!\n")); + return; + } + + if(!TM_Trigger) //at least delay 1 sec + { + if (IS_HARDWARE_TYPE_8188E(Adapter) || IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8192E(Adapter) || + IS_HARDWARE_TYPE_8723B(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter) || IS_HARDWARE_TYPE_8188F(Adapter) + || IS_HARDWARE_TYPE_8703B(Adapter)) + PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); + else + PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); + + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Trigger Thermal Meter!!\n")); + + TM_Trigger = 1; + return; + } + else + { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Schedule TxPowerTracking direct call!!\n")); + odm_TXPowerTrackingDirectCall(Adapter); //Using direct call is instead, added by Roger, 2009.06.18. + TM_Trigger = 0; + } +#endif +} +#endif + + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_powertracking_ce.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_powertracking_ce.h new file mode 100644 index 000000000..c068b7479 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_powertracking_ce.h @@ -0,0 +1,296 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMPOWERTRACKING_H__ +#define __PHYDMPOWERTRACKING_H__ + +#define POWRTRACKING_VERSION "1.1" + +#define DPK_DELTA_MAPPING_NUM 13 +#define index_mapping_HP_NUM 15 +#define OFDM_TABLE_SIZE 43 +#define CCK_TABLE_SIZE 33 +#define CCK_TABLE_SIZE_88F 21 +#define TXSCALE_TABLE_SIZE 37 +#define TXPWR_TRACK_TABLE_SIZE 30 +#define DELTA_SWINGIDX_SIZE 30 +#define BAND_NUM 4 + +#define AVG_THERMAL_NUM 8 +#define HP_THERMAL_NUM 8 +#define IQK_MAC_REG_NUM 4 +#define IQK_ADDA_REG_NUM 16 +#define IQK_BB_REG_NUM_MAX 10 + +#define IQK_BB_REG_NUM 9 + + + +#define IQK_Matrix_REG_NUM 8 +#define IQK_Matrix_Settings_NUM 14+24+21 // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G + +extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE]; +extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]; + +extern u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE]; +extern u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch14_New [CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16]; + + +extern u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE]; + +// <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. +static u1Byte DeltaSwingTableIdx_2GA_P_8188E[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; +static u1Byte DeltaSwingTableIdx_2GA_N_8188E[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; + +#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck + +typedef struct _IQK_MATRIX_REGS_SETTING{ + BOOLEAN bIQKDone; + s4Byte Value[3][IQK_Matrix_REG_NUM]; + BOOLEAN bBWIqkResultSaved[3]; +}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING; + +typedef struct ODM_RF_Calibration_Structure +{ + //for tx power tracking + + u4Byte RegA24; // for TempCCK + s4Byte RegE94; + s4Byte RegE9C; + s4Byte RegEB4; + s4Byte RegEBC; + + u1Byte TXPowercount; + BOOLEAN bTXPowerTrackingInit; + BOOLEAN bTXPowerTracking; + u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default + u1Byte TM_Trigger; + u1Byte InternalPA5G[2]; //pathA / pathB + + u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 + u1Byte ThermalValue; + u1Byte ThermalValue_LCK; + u1Byte ThermalValue_IQK; + u1Byte ThermalValue_DPK; + u1Byte ThermalValue_AVG[AVG_THERMAL_NUM]; + u1Byte ThermalValue_AVG_index; + u1Byte ThermalValue_RxGain; + u1Byte ThermalValue_Crystal; + u1Byte ThermalValue_DPKstore; + u1Byte ThermalValue_DPKtrack; + BOOLEAN TxPowerTrackingInProgress; + + BOOLEAN bReloadtxpowerindex; + u1Byte bRfPiEnable; + u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug + + + //------------------------- Tx power Tracking -------------------------// + u1Byte bCCKinCH14; + u1Byte CCK_index; + u1Byte OFDM_index[MAX_RF_PATH]; + s1Byte PowerIndexOffset[MAX_RF_PATH]; + s1Byte DeltaPowerIndex[MAX_RF_PATH]; + s1Byte DeltaPowerIndexLast[MAX_RF_PATH]; + BOOLEAN bTxPowerChanged; + + u1Byte ThermalValue_HP[HP_THERMAL_NUM]; + u1Byte ThermalValue_HP_index; + IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; + u1Byte Delta_LCK; + s1Byte BBSwingDiff2G, BBSwingDiff5G; // Unit: dB + u1Byte DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKC_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKC_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKD_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKD_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GC_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GC_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GD_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GD_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GC_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GC_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GD_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GD_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE]; + + u1Byte BbSwingIdxOfdm[MAX_RF_PATH]; + u1Byte BbSwingIdxOfdmCurrent; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + u1Byte BbSwingIdxOfdmBase[MAX_RF_PATH]; +#else + u1Byte BbSwingIdxOfdmBase; +#endif + BOOLEAN BbSwingFlagOfdm; + u1Byte BbSwingIdxCck; + u1Byte BbSwingIdxCckCurrent; + u1Byte BbSwingIdxCckBase; + u1Byte DefaultOfdmIndex; + u1Byte DefaultCckIndex; + BOOLEAN BbSwingFlagCck; + + s1Byte Absolute_OFDMSwingIdx[MAX_RF_PATH]; + s1Byte Remnant_OFDMSwingIdx[MAX_RF_PATH]; + s1Byte Remnant_CCKSwingIdx; + s1Byte Modify_TxAGC_Value; /*Remnat compensate value at TxAGC */ + BOOLEAN Modify_TxAGC_Flag_PathA; + BOOLEAN Modify_TxAGC_Flag_PathB; + BOOLEAN Modify_TxAGC_Flag_PathC; + BOOLEAN Modify_TxAGC_Flag_PathD; + BOOLEAN Modify_TxAGC_Flag_PathA_CCK; + + s1Byte KfreeOffset[MAX_RF_PATH]; + + //--------------------------------------------------------------------// + + //for IQK + u4Byte RegC04; + u4Byte Reg874; + u4Byte RegC08; + u4Byte RegB68; + u4Byte RegB6C; + u4Byte Reg870; + u4Byte Reg860; + u4Byte Reg864; + + BOOLEAN bIQKInitialized; + BOOLEAN bLCKInProgress; + BOOLEAN bAntennaDetected; + BOOLEAN bNeedIQK; + BOOLEAN bIQKInProgress; + u1Byte Delta_IQK; + u4Byte ADDA_backup[IQK_ADDA_REG_NUM]; + u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM]; + u4Byte IQK_BB_backup_recover[9]; + u4Byte IQK_BB_backup[IQK_BB_REG_NUM]; + u4Byte TxIQC_8723B[2][3][2]; // { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} + u4Byte RxIQC_8723B[2][2][2]; // { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} + u4Byte TxIQC_8703B[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u4Byte RxIQC_8703B[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + + + + // IQK time measurement + u8Byte IQK_StartTime; + u8Byte IQK_ProgressingTime; + u4Byte LOK_Result; + + //for APK + u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a + u1Byte bAPKdone; + u1Byte bAPKThermalMeterIgnore; + + // DPK + BOOLEAN bDPKFail; + u1Byte bDPdone; + u1Byte bDPPathAOK; + u1Byte bDPPathBOK; + + u4Byte TxLOK[2]; + u4Byte DpkTxAGC; + s4Byte DpkGain; + u4Byte DpkThermal[4]; + s1Byte Modify_TxAGC_Value_OFDM; + s1Byte Modify_TxAGC_Value_CCK; +}ODM_RF_CAL_T,*PODM_RF_CAL_T; + + +VOID +ODM_TXPowerTrackingCheck( + IN PVOID pDM_VOID + ); + + +VOID +odm_TXPowerTrackingInit( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingCheckAP( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingThermalMeterInit( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingInit( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingCheckMP( + IN PVOID pDM_VOID + ); + + +VOID +odm_TXPowerTrackingCheckCE( + IN PVOID pDM_VOID + ); + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + +VOID +odm_TXPowerTrackingCallbackThermalMeter92C( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingCallbackRXGainThermalMeter92D( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingCallbackThermalMeter92D( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingDirectCall92C( + IN PADAPTER Adapter + ); + +VOID +odm_TXPowerTrackingThermalMeterCheck( + IN PADAPTER Adapter + ); + +#endif + +#endif diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_powertracking_win.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_powertracking_win.c new file mode 100644 index 000000000..acf2147c8 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_powertracking_win.c @@ -0,0 +1,687 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +//============================================================ +// Global var +//============================================================ + +u4Byte OFDMSwingTable[OFDM_TABLE_SIZE] = { + 0x7f8001fe, // 0, +6.0dB + 0x788001e2, // 1, +5.5dB + 0x71c001c7, // 2, +5.0dB + 0x6b8001ae, // 3, +4.5dB + 0x65400195, // 4, +4.0dB + 0x5fc0017f, // 5, +3.5dB + 0x5a400169, // 6, +3.0dB + 0x55400155, // 7, +2.5dB + 0x50800142, // 8, +2.0dB + 0x4c000130, // 9, +1.5dB + 0x47c0011f, // 10, +1.0dB + 0x43c0010f, // 11, +0.5dB + 0x40000100, // 12, +0dB + 0x3c8000f2, // 13, -0.5dB + 0x390000e4, // 14, -1.0dB + 0x35c000d7, // 15, -1.5dB + 0x32c000cb, // 16, -2.0dB + 0x300000c0, // 17, -2.5dB + 0x2d4000b5, // 18, -3.0dB + 0x2ac000ab, // 19, -3.5dB + 0x288000a2, // 20, -4.0dB + 0x26000098, // 21, -4.5dB + 0x24000090, // 22, -5.0dB + 0x22000088, // 23, -5.5dB + 0x20000080, // 24, -6.0dB + 0x1e400079, // 25, -6.5dB + 0x1c800072, // 26, -7.0dB + 0x1b00006c, // 27. -7.5dB + 0x19800066, // 28, -8.0dB + 0x18000060, // 29, -8.5dB + 0x16c0005b, // 30, -9.0dB + 0x15800056, // 31, -9.5dB + 0x14400051, // 32, -10.0dB + 0x1300004c, // 33, -10.5dB + 0x12000048, // 34, -11.0dB + 0x11000044, // 35, -11.5dB + 0x10000040, // 36, -12.0dB +}; + +u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = { + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0dB + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 1, -0.5dB + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 2, -1.0dB + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 3, -1.5dB + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 4, -2.0dB + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 5, -2.5dB + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 6, -3.0dB + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 7, -3.5dB + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 8, -4.0dB + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 9, -4.5dB + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 10, -5.0dB + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 11, -5.5dB + {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 12, -6.0dB <== default + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 13, -6.5dB + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 14, -7.0dB + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 15, -7.5dB + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 17, -8.5dB + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 18, -9.0dB + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 19, -9.5dB + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 20, -10.0dB + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 21, -10.5dB + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 22, -11.0dB + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 23, -11.5dB + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 24, -12.0dB + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 25, -12.5dB + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 26, -13.0dB + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 27, -13.5dB + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 28, -14.0dB + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 29, -14.5dB + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 30, -15.0dB + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 31, -15.5dB + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} // 32, -16.0dB +}; + + +u1Byte CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = { + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0dB + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 1, -0.5dB + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 2, -1.0dB + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 3, -1.5dB + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 4, -2.0dB + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 5, -2.5dB + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 6, -3.0dB + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 7, -3.5dB + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 8, -4.0dB + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 9, -4.5dB + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 10, -5.0dB + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 11, -5.5dB + {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 12, -6.0dB <== default + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 13, -6.5dB + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 14, -7.0dB + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 15, -7.5dB + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 17, -8.5dB + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 18, -9.0dB + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 19, -9.5dB + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 20, -10.0dB + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 21, -10.5dB + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 22, -11.0dB + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 23, -11.5dB + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 24, -12.0dB + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 25, -12.5dB + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 26, -13.0dB + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 27, -13.5dB + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 28, -14.0dB + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 29, -14.5dB + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 30, -15.0dB + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 31, -15.5dB + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} // 32, -16.0dB +}; + + +u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE] = { + 0x0b40002d, // 0, -15.0dB + 0x0c000030, // 1, -14.5dB + 0x0cc00033, // 2, -14.0dB + 0x0d800036, // 3, -13.5dB + 0x0e400039, // 4, -13.0dB + 0x0f00003c, // 5, -12.5dB + 0x10000040, // 6, -12.0dB + 0x11000044, // 7, -11.5dB + 0x12000048, // 8, -11.0dB + 0x1300004c, // 9, -10.5dB + 0x14400051, // 10, -10.0dB + 0x15800056, // 11, -9.5dB + 0x16c0005b, // 12, -9.0dB + 0x18000060, // 13, -8.5dB + 0x19800066, // 14, -8.0dB + 0x1b00006c, // 15, -7.5dB + 0x1c800072, // 16, -7.0dB + 0x1e400079, // 17, -6.5dB + 0x20000080, // 18, -6.0dB + 0x22000088, // 19, -5.5dB + 0x24000090, // 20, -5.0dB + 0x26000098, // 21, -4.5dB + 0x288000a2, // 22, -4.0dB + 0x2ac000ab, // 23, -3.5dB + 0x2d4000b5, // 24, -3.0dB + 0x300000c0, // 25, -2.5dB + 0x32c000cb, // 26, -2.0dB + 0x35c000d7, // 27, -1.5dB + 0x390000e4, // 28, -1.0dB + 0x3c8000f2, // 29, -0.5dB + 0x40000100, // 30, +0dB + 0x43c0010f, // 31, +0.5dB + 0x47c0011f, // 32, +1.0dB + 0x4c000130, // 33, +1.5dB + 0x50800142, // 34, +2.0dB + 0x55400155, // 35, +2.5dB + 0x5a400169, // 36, +3.0dB + 0x5fc0017f, // 37, +3.5dB + 0x65400195, // 38, +4.0dB + 0x6b8001ae, // 39, +4.5dB + 0x71c001c7, // 40, +5.0dB + 0x788001e2, // 41, +5.5dB + 0x7f8001fe // 42, +6.0dB +}; + + +u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16] = { +{0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ +{0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ +{0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ +{0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ +{0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ +{0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ +{0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ +{0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ +{0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ +{0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ +{0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ +{0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ +{0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ +{0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ +{0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ +{0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ +{0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ +{0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ +{0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ +{0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ +{0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ +}; + + +u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8] = { + {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}, // 0, -16.0dB + {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 1, -15.5dB + {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 2, -15.0dB + {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 3, -14.5dB + {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 4, -14.0dB + {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 5, -13.5dB + {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 6, -13.0dB + {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 7, -12.5dB + {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 8, -12.0dB + {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 9, -11.5dB + {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 10, -11.0dB + {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 11, -10.5dB + {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 12, -10.0dB + {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 13, -9.5dB + {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 14, -9.0dB + {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 15, -8.5dB + {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB + {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 17, -7.5dB + {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 18, -7.0dB + {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 19, -6.5dB + {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 20, -6.0dB + {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 21, -5.5dB + {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 22, -5.0dB + {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 23, -4.5dB + {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 24, -4.0dB + {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 25, -3.5dB + {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 26, -3.0dB + {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 27, -2.5dB + {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 28, -2.0dB + {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 29, -1.5dB + {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 30, -1.0dB + {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 31, -0.5dB + {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04} // 32, +0dB +}; + + +u1Byte CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8]= { + {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}, // 0, -16.0dB + {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 1, -15.5dB + {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 2, -15.0dB + {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 3, -14.5dB + {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 4, -14.0dB + {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 5, -13.5dB + {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 6, -13.0dB + {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 7, -12.5dB + {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 8, -12.0dB + {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 9, -11.5dB + {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 10, -11.0dB + {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 11, -10.5dB + {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 12, -10.0dB + {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 13, -9.5dB + {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 14, -9.0dB + {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 15, -8.5dB + {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB + {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 17, -7.5dB + {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 18, -7.0dB + {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 19, -6.5dB + {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 20, -6.0dB + {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 21, -5.5dB + {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 22, -5.0dB + {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 23, -4.5dB + {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 24, -4.0dB + {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 25, -3.5dB + {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 26, -3.0dB + {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 27, -2.5dB + {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 28, -2.0dB + {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 29, -1.5dB + {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 30, -1.0dB + {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 31, -0.5dB + {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00} // 32, +0dB +}; + +u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE] = +{ + 0x081, // 0, -12.0dB + 0x088, // 1, -11.5dB + 0x090, // 2, -11.0dB + 0x099, // 3, -10.5dB + 0x0A2, // 4, -10.0dB + 0x0AC, // 5, -9.5dB + 0x0B6, // 6, -9.0dB + 0x0C0, // 7, -8.5dB + 0x0CC, // 8, -8.0dB + 0x0D8, // 9, -7.5dB + 0x0E5, // 10, -7.0dB + 0x0F2, // 11, -6.5dB + 0x101, // 12, -6.0dB + 0x110, // 13, -5.5dB + 0x120, // 14, -5.0dB + 0x131, // 15, -4.5dB + 0x143, // 16, -4.0dB + 0x156, // 17, -3.5dB + 0x16A, // 18, -3.0dB + 0x180, // 19, -2.5dB + 0x197, // 20, -2.0dB + 0x1AF, // 21, -1.5dB + 0x1C8, // 22, -1.0dB + 0x1E3, // 23, -0.5dB + 0x200, // 24, +0 dB + 0x21E, // 25, +0.5dB + 0x23E, // 26, +1.0dB + 0x261, // 27, +1.5dB + 0x285, // 28, +2.0dB + 0x2AB, // 29, +2.5dB + 0x2D3, // 30, +3.0dB + 0x2FE, // 31, +3.5dB + 0x32B, // 32, +4.0dB + 0x35C, // 33, +4.5dB + 0x38E, // 34, +5.0dB + 0x3C4, // 35, +5.5dB + 0x3FE // 36, +6.0dB +}; + +#ifdef AP_BUILD_WORKAROUND + +unsigned int TxPwrTrk_OFDM_SwingTbl[TxPwrTrk_OFDM_SwingTbl_Len] = { + /* +6.0dB */ 0x7f8001fe, + /* +5.5dB */ 0x788001e2, + /* +5.0dB */ 0x71c001c7, + /* +4.5dB */ 0x6b8001ae, + /* +4.0dB */ 0x65400195, + /* +3.5dB */ 0x5fc0017f, + /* +3.0dB */ 0x5a400169, + /* +2.5dB */ 0x55400155, + /* +2.0dB */ 0x50800142, + /* +1.5dB */ 0x4c000130, + /* +1.0dB */ 0x47c0011f, + /* +0.5dB */ 0x43c0010f, + /* 0.0dB */ 0x40000100, + /* -0.5dB */ 0x3c8000f2, + /* -1.0dB */ 0x390000e4, + /* -1.5dB */ 0x35c000d7, + /* -2.0dB */ 0x32c000cb, + /* -2.5dB */ 0x300000c0, + /* -3.0dB */ 0x2d4000b5, + /* -3.5dB */ 0x2ac000ab, + /* -4.0dB */ 0x288000a2, + /* -4.5dB */ 0x26000098, + /* -5.0dB */ 0x24000090, + /* -5.5dB */ 0x22000088, + /* -6.0dB */ 0x20000080, + /* -6.5dB */ 0x1a00006c, + /* -7.0dB */ 0x1c800072, + /* -7.5dB */ 0x18000060, + /* -8.0dB */ 0x19800066, + /* -8.5dB */ 0x15800056, + /* -9.0dB */ 0x26c0005b, + /* -9.5dB */ 0x14400051, + /* -10.0dB */ 0x24400051, + /* -10.5dB */ 0x1300004c, + /* -11.0dB */ 0x12000048, + /* -11.5dB */ 0x11000044, + /* -12.0dB */ 0x10000040 +}; + +#endif + +VOID +odm_TXPowerTrackingInit( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + if(!(pDM_Odm->SupportICType & (ODM_RTL8814A|ODM_IC_11N_SERIES|ODM_RTL8822B))) + return; +#endif + + odm_TXPowerTrackingThermalMeterInit(pDM_Odm); +} + +u1Byte +getSwingIndex( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u1Byte i = 0; + u4Byte bbSwing; + u4Byte swingTableSize; + pu4Byte pSwingTable; + + if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723B || + pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8188F || pDM_Odm->SupportICType == ODM_RTL8703B) + { + bbSwing = PHY_QueryBBReg(Adapter, rOFDM0_XATxIQImbalance, 0xFFC00000); + + pSwingTable = OFDMSwingTable_New; + swingTableSize = OFDM_TABLE_SIZE; + } else { + bbSwing = PHY_GetTxBBSwing_8812A(Adapter, pHalData->CurrentBandType, ODM_RF_PATH_A); + pSwingTable = TxScalingTable_Jaguar; + swingTableSize = TXSCALE_TABLE_SIZE; + } + + for (i = 0; i < swingTableSize; ++i) { + u4Byte tableValue = pSwingTable[i]; + + if (tableValue >= 0x100000 ) + tableValue >>= 22; + if (bbSwing == tableValue) + break; + } + return i; +} + +VOID +odm_TXPowerTrackingThermalMeterInit( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte defaultSwingIndex = getSwingIndex(pDM_Odm); + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u1Byte p = 0; + + if(pDM_Odm->mp_mode == FALSE) + pRFCalibrateInfo->TxPowerTrackControl = TRUE; +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #ifdef CONFIG_RTL8188E + { + pRFCalibrateInfo->bTXPowerTracking = _TRUE; + pRFCalibrateInfo->TXPowercount = 0; + pRFCalibrateInfo->bTXPowerTrackingInit = _FALSE; + + if(pDM_Odm->mp_mode == FALSE) + pRFCalibrateInfo->TxPowerTrackControl = _TRUE; + + MSG_8192C("pDM_Odm TxPowerTrackControl = %d\n", pRFCalibrateInfo->TxPowerTrackControl); + } + #else + { + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct dm_priv *pdmpriv = &pHalData->dmpriv; + + pdmpriv->bTXPowerTracking = _TRUE; + pdmpriv->TXPowercount = 0; + pdmpriv->bTXPowerTrackingInit = _FALSE; + + if(pDM_Odm->mp_mode == FALSE) + pdmpriv->TxPowerTrackControl = _TRUE; + + MSG_8192C("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl); + + } + #endif//endif (CONFIG_RTL8188E==1) +#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + #ifdef RTL8188E_SUPPORT + { + pRFCalibrateInfo->bTXPowerTracking = _TRUE; + pRFCalibrateInfo->TXPowercount = 0; + pRFCalibrateInfo->bTXPowerTrackingInit = _FALSE; + pRFCalibrateInfo->TxPowerTrackControl = _TRUE; + } + #endif +#endif + + pRFCalibrateInfo->TxPowerTrackControl = TRUE; + pRFCalibrateInfo->ThermalValue = pHalData->EEPROMThermalMeter; + pRFCalibrateInfo->ThermalValue_IQK = pHalData->EEPROMThermalMeter; + pRFCalibrateInfo->ThermalValue_LCK = pHalData->EEPROMThermalMeter; + + // The index of "0 dB" in SwingTable. + if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723B || + pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8703B) + { + pRFCalibrateInfo->DefaultOfdmIndex = (defaultSwingIndex >= OFDM_TABLE_SIZE) ? 30 : defaultSwingIndex; + pRFCalibrateInfo->DefaultCckIndex = 20; + } + else if(pDM_Odm->SupportICType == ODM_RTL8188F) //add by Mingzhi.Guo 2015-03-23 + { + pRFCalibrateInfo->DefaultOfdmIndex =28; //OFDM: -1dB + pRFCalibrateInfo->DefaultCckIndex =20; //CCK:-6dB + } + else + { + pRFCalibrateInfo->DefaultOfdmIndex = (defaultSwingIndex >= TXSCALE_TABLE_SIZE) ? 24 : defaultSwingIndex; + pRFCalibrateInfo->DefaultCckIndex = 24; + } + + pRFCalibrateInfo->BbSwingIdxCckBase = pRFCalibrateInfo->DefaultCckIndex; + pRFCalibrateInfo->CCK_index = pRFCalibrateInfo->DefaultCckIndex; + + for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p) + { + pRFCalibrateInfo->BbSwingIdxOfdmBase[p] = pRFCalibrateInfo->DefaultOfdmIndex; + pRFCalibrateInfo->OFDM_index[p] = pRFCalibrateInfo->DefaultOfdmIndex; + pRFCalibrateInfo->DeltaPowerIndex[p] = 0; + pRFCalibrateInfo->DeltaPowerIndexLast[p] = 0; + pRFCalibrateInfo->PowerIndexOffset[p] = 0; + pRFCalibrateInfo->KfreeOffset[p] = 0; + } + pRFCalibrateInfo->Modify_TxAGC_Value_OFDM=0; //add by Mingzhi.Guo + pRFCalibrateInfo->Modify_TxAGC_Value_CCK=0; //add by Mingzhi.Guo + +} + + +VOID +ODM_TXPowerTrackingCheck( + IN PVOID pDM_VOID + ) +{ + // + // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate + // at the same time. In the stage2/3, we need to prive universal interface and merge all + // HW dynamic mechanism. + // + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + switch (pDM_Odm->SupportPlatform) + { + case ODM_WIN: + odm_TXPowerTrackingCheckMP(pDM_Odm); + break; + + case ODM_CE: + odm_TXPowerTrackingCheckCE(pDM_Odm); + break; + + case ODM_AP: + odm_TXPowerTrackingCheckAP(pDM_Odm); + break; + + default: + break; + } + +} + +VOID +odm_TXPowerTrackingCheckCE( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PADAPTER Adapter = pDM_Odm->Adapter; + #if ((RTL8188F_SUPPORT == 1)) + rtl8192c_odm_CheckTXPowerTracking(Adapter); + #endif + + #if(RTL8188E_SUPPORT==1) + + if(!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK)) + { + return; + } + + if(!pRFCalibrateInfo->TM_Trigger) //at least delay 1 sec + { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); + //DBG_8192C("Trigger 92C Thermal Meter!!\n"); + + pRFCalibrateInfo->TM_Trigger = 1; + return; + + } + else + { + //DBG_8192C("Schedule TxPowerTracking direct call!!\n"); + odm_TXPowerTrackingCallback_ThermalMeter_8188E(Adapter); + pRFCalibrateInfo->TM_Trigger = 0; + } + #endif +#endif +} + +VOID +odm_TXPowerTrackingCheckMP( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + + if(*pDM_Odm->pIsFcsModeEnable) + return; + + if (ODM_CheckPowerStatus(Adapter) == FALSE) + { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("===>ODM_CheckPowerStatus() return FALSE\n")); + return; + } + + if(IS_HARDWARE_TYPE_8821B(Adapter)) // TODO: Don't Do PowerTracking + return; + +// #if(RTL8192D_SUPPORT==1) +// if(!Adapter->bSlaveOfDMSP || Adapter->DualMacSmartConcurrent == FALSE) + if (IS_HARDWARE_TYPE_8814A(Adapter) || IS_HARDWARE_TYPE_8188F(Adapter)) + odm_TXPowerTrackingThermalMeterCheck(Adapter); + else { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("!Adapter->bSlaveOfDMSP || Adapter->DualMacSmartConcurrent == FALSE\n")); + } +// #endif +#endif + +} + + +VOID +odm_TXPowerTrackingCheckAP( + IN PVOID pDM_VOID + ) +{ +return; + +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +VOID +odm_TXPowerTrackingDirectCall( + IN PADAPTER Adapter + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + ODM_TXPowerTrackingCallback_ThermalMeter(Adapter); +} + +VOID +odm_TXPowerTrackingThermalMeterCheck( + IN PADAPTER Adapter + ) +{ +#ifndef AP_BUILD_WORKAROUND + static u1Byte TM_Trigger = 0; + + if(!(GET_HAL_DATA(Adapter)->DM_OutSrc.SupportAbility & ODM_RF_TX_PWR_TRACK)) + { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, + ("===>odm_TXPowerTrackingThermalMeterCheck(),pMgntInfo->bTXPowerTracking is FALSE, return!!\n")); + return; + } + + if(!TM_Trigger) //at least delay 1 sec + { + if (IS_HARDWARE_TYPE_8188E(Adapter) || IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8192E(Adapter) || + IS_HARDWARE_TYPE_8723B(Adapter) || IS_HARDWARE_TYPE_8814A(Adapter) || IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8703B(Adapter)) + PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03); + else + PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); + + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Trigger Thermal Meter!!\n")); + + TM_Trigger = 1; + return; + } + else + { + RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Schedule TxPowerTracking direct call!!\n")); + odm_TXPowerTrackingDirectCall(Adapter); //Using direct call is instead, added by Roger, 2009.06.18. + TM_Trigger = 0; + } +#endif +} + +#endif //end #ifMP + + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_powertracking_win.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_powertracking_win.h new file mode 100644 index 000000000..0ecb3179b --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_powertracking_win.h @@ -0,0 +1,265 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMPOWERTRACKING_H__ +#define __PHYDMPOWERTRACKING_H__ + +#define POWRTRACKING_VERSION "1.1" + +#define DPK_DELTA_MAPPING_NUM 13 +#define index_mapping_HP_NUM 15 +#define TXSCALE_TABLE_SIZE 37 +#define TXPWR_TRACK_TABLE_SIZE 30 +#define DELTA_SWINGIDX_SIZE 30 +#define BAND_NUM 3 +#define MAX_RF_PATH 4 +#define CCK_TABLE_SIZE_88F 21 + + +#define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck + +#define IQK_Matrix_Settings_NUM 14+24+21 // Channels_2_4G_NUM + Channels_5G_20M_NUM + Channels_5G +#define AVG_THERMAL_NUM 8 +#define HP_THERMAL_NUM 8 +#define IQK_Matrix_REG_NUM 8 +#define IQK_MAC_REG_NUM 4 +#define IQK_ADDA_REG_NUM 16 + +#define IQK_BB_REG_NUM 9 + + +extern u4Byte OFDMSwingTable[OFDM_TABLE_SIZE]; +extern u1Byte CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]; + +extern u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE]; +extern u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch14_New [CCK_TABLE_SIZE][8]; +extern u1Byte CCKSwingTable_Ch1_Ch14_88F[CCK_TABLE_SIZE_88F][16]; + +extern u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE]; + +// <20121018, Kordan> In case fail to read TxPowerTrack.txt, we use the table of 88E as the default table. +static u1Byte DeltaSwingTableIdx_2GA_P_8188E[] = {0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9}; +static u1Byte DeltaSwingTableIdx_2GA_N_8188E[] = {0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11}; + +VOID +ODM_TXPowerTrackingCheck( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingCheckAP( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingThermalMeterInit( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingInit( + IN PVOID pDM_VOID + ); + +VOID +odm_TXPowerTrackingCheckMP( + IN PVOID pDM_VOID + ); + + +VOID +odm_TXPowerTrackingCheckCE( + IN PVOID pDM_VOID + ); + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + + +VOID +odm_TXPowerTrackingThermalMeterCheck( + IN PADAPTER Adapter + ); + +#endif + +typedef struct _IQK_MATRIX_REGS_SETTING{ + BOOLEAN bIQKDone; + s4Byte Value[3][IQK_Matrix_REG_NUM]; + BOOLEAN bBWIqkResultSaved[3]; +}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING; + +typedef struct ODM_RF_Calibration_Structure +{ + //for tx power tracking + + u4Byte RegA24; // for TempCCK + s4Byte RegE94; + s4Byte RegE9C; + s4Byte RegEB4; + s4Byte RegEBC; + //u1Byte bTXPowerTracking; + u1Byte TXPowercount; + BOOLEAN bTXPowerTrackingInit; + BOOLEAN bTXPowerTracking; + u1Byte TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default + u1Byte TM_Trigger; + u1Byte InternalPA5G[2]; //pathA / pathB + + u1Byte ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 + u1Byte ThermalValue; + u1Byte ThermalValue_LCK; + u1Byte ThermalValue_IQK; + u1Byte ThermalValue_AVG[AVG_THERMAL_NUM]; + u1Byte ThermalValue_AVG_index; + u1Byte ThermalValue_RxGain; + + BOOLEAN bReloadtxpowerindex; + u1Byte bRfPiEnable; + u4Byte TXPowerTrackingCallbackCnt; //cosa add for debug + + + //------------------------- Tx power Tracking -------------------------// + u1Byte bCCKinCH14; + u1Byte CCK_index; + u1Byte OFDM_index[MAX_RF_PATH]; + s1Byte PowerIndexOffset[MAX_RF_PATH]; + s1Byte DeltaPowerIndex[MAX_RF_PATH]; + s1Byte DeltaPowerIndexLast[MAX_RF_PATH]; + BOOLEAN bTxPowerChanged; + + u1Byte ThermalValue_HP[HP_THERMAL_NUM]; + u1Byte ThermalValue_HP_index; + IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; + u1Byte Delta_LCK; + s1Byte BBSwingDiff2G, BBSwingDiff5G; // Unit: dB + u1Byte DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKC_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKC_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKD_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GCCKD_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GC_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GC_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GD_P[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GD_N[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GC_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GC_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GD_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_5GD_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE]; + u1Byte DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE]; + + u1Byte BbSwingIdxOfdm[MAX_RF_PATH]; + u1Byte BbSwingIdxOfdmCurrent; +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + u1Byte BbSwingIdxOfdmBase[MAX_RF_PATH]; +#else + u1Byte BbSwingIdxOfdmBase; +#endif + BOOLEAN BbSwingFlagOfdm; + u1Byte BbSwingIdxCck; + u1Byte BbSwingIdxCckCurrent; + u1Byte BbSwingIdxCckBase; + u1Byte DefaultOfdmIndex; + u1Byte DefaultCckIndex; + BOOLEAN BbSwingFlagCck; + + s1Byte Absolute_OFDMSwingIdx[MAX_RF_PATH]; + s1Byte Remnant_OFDMSwingIdx[MAX_RF_PATH]; + s1Byte Remnant_CCKSwingIdx; + s1Byte Modify_TxAGC_Value; /*Remnat compensate value at TxAGC */ + BOOLEAN Modify_TxAGC_Flag_PathA; + BOOLEAN Modify_TxAGC_Flag_PathB; + BOOLEAN Modify_TxAGC_Flag_PathC; + BOOLEAN Modify_TxAGC_Flag_PathD; + BOOLEAN Modify_TxAGC_Flag_PathA_CCK; + + s1Byte KfreeOffset[MAX_RF_PATH]; + + //--------------------------------------------------------------------// + + //for IQK + u4Byte RegC04; + u4Byte Reg874; + u4Byte RegC08; + u4Byte RegB68; + u4Byte RegB6C; + u4Byte Reg870; + u4Byte Reg860; + u4Byte Reg864; + + BOOLEAN bIQKInitialized; + BOOLEAN bLCKInProgress; + BOOLEAN bAntennaDetected; + BOOLEAN bNeedIQK; + BOOLEAN bIQKInProgress; + u1Byte Delta_IQK; + u4Byte ADDA_backup[IQK_ADDA_REG_NUM]; + u4Byte IQK_MAC_backup[IQK_MAC_REG_NUM]; + u4Byte IQK_BB_backup_recover[9]; + u4Byte IQK_BB_backup[IQK_BB_REG_NUM]; + u4Byte TxIQC_8723B[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ + u4Byte RxIQC_8723B[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ + u4Byte TxIQC_8703B[3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}}*/ + u4Byte RxIQC_8703B[2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}}*/ + + + + // IQK time measurement + u8Byte IQK_StartTime; + u8Byte IQK_ProgressingTime; + u4Byte LOK_Result; + + //for APK + u4Byte APKoutput[2][2]; //path A/B; output1_1a/output1_2a + u1Byte bAPKdone; + u1Byte bAPKThermalMeterIgnore; + + // DPK + BOOLEAN bDPKFail; + u1Byte bDPdone; + u1Byte bDPPathAOK; + u1Byte bDPPathBOK; + + u4Byte TxLOK[2]; + u4Byte DpkTxAGC; + s4Byte DpkGain; + u4Byte DpkThermal[4]; + + s1Byte Modify_TxAGC_Value_OFDM; + s1Byte Modify_TxAGC_Value_CCK; +}ODM_RF_CAL_T,*PODM_RF_CAL_T; + + + + +#endif diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_pre_define.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_pre_define.h new file mode 100644 index 000000000..c64e0d40f --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_pre_define.h @@ -0,0 +1,615 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __PHYDMPREDEFINE_H__ +#define __PHYDMPREDEFINE_H__ + +//1 ============================================================ +//1 Definition +//1 ============================================================ + +//Max path of IC +#define MAX_PATH_NUM_92CS 2 +#define MAX_PATH_NUM_8188E 1 +#define MAX_PATH_NUM_8192E 2 +#define MAX_PATH_NUM_8723B 1 +#define MAX_PATH_NUM_8812A 2 +#define MAX_PATH_NUM_8821A 1 +#define MAX_PATH_NUM_8814A 4 +#define MAX_PATH_NUM_8822B 2 +#define MAX_PATH_NUM_8821B 2 +#define MAX_PATH_NUM_8703B 1 +#define MAX_PATH_NUM_8188F 1 + +//Max RF path +#define ODM_RF_PATH_MAX 2 +#define ODM_RF_PATH_MAX_JAGUAR 4 + +//number of entry +#if(DM_ODM_SUPPORT_TYPE & (ODM_CE)) + #define ASSOCIATE_ENTRY_NUM MACID_NUM_SW_LIMIT /* Max size of AsocEntry[].*/ + #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM +#elif(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + #define ASSOCIATE_ENTRY_NUM NUM_STAT + #define ODM_ASSOCIATE_ENTRY_NUM (ASSOCIATE_ENTRY_NUM+1) +#else + #define ODM_ASSOCIATE_ENTRY_NUM ((ASSOCIATE_ENTRY_NUM*3)+1) +#endif + +/* -----MGN rate--------------------------------- */ + +#define ODM_MGN_1M 0x02 +#define ODM_MGN_2M 0x04 +#define ODM_MGN_5_5M 0x0b +#define ODM_MGN_11M 0x16 + +#define ODM_MGN_6M 0x0c +#define ODM_MGN_9M 0x12 +#define ODM_MGN_12M 0x18 +#define ODM_MGN_18M 0x24 +#define ODM_MGN_24M 0x30 +#define ODM_MGN_36M 0x48 +#define ODM_MGN_48M 0x60 +#define ODM_MGN_54M 0x6c + +/*TxHT = 1*/ +#define ODM_MGN_MCS0 0x80 +#define ODM_MGN_MCS1 0x81 +#define ODM_MGN_MCS2 0x82 +#define ODM_MGN_MCS3 0x83 +#define ODM_MGN_MCS4 0x84 +#define ODM_MGN_MCS5 0x85 +#define ODM_MGN_MCS6 0x86 +#define ODM_MGN_MCS7 0x87 +#define ODM_MGN_MCS8 0x88 +#define ODM_MGN_MCS9 0x89 +#define ODM_MGN_MCS10 0x8a +#define ODM_MGN_MCS11 0x8b +#define ODM_MGN_MCS12 0x8c +#define ODM_MGN_MCS13 0x8d +#define ODM_MGN_MCS14 0x8e +#define ODM_MGN_MCS15 0x8f +#define ODM_MGN_VHT1SS_MCS0 0x90 +#define ODM_MGN_VHT1SS_MCS1 0x91 +#define ODM_MGN_VHT1SS_MCS2 0x92 +#define ODM_MGN_VHT1SS_MCS3 0x93 +#define ODM_MGN_VHT1SS_MCS4 0x94 +#define ODM_MGN_VHT1SS_MCS5 0x95 +#define ODM_MGN_VHT1SS_MCS6 0x96 +#define ODM_MGN_VHT1SS_MCS7 0x97 +#define ODM_MGN_VHT1SS_MCS8 0x98 +#define ODM_MGN_VHT1SS_MCS9 0x99 +#define ODM_MGN_VHT2SS_MCS0 0x9a +#define ODM_MGN_VHT2SS_MCS1 0x9b +#define ODM_MGN_VHT2SS_MCS2 0x9c +#define ODM_MGN_VHT2SS_MCS3 0x9d +#define ODM_MGN_VHT2SS_MCS4 0x9e +#define ODM_MGN_VHT2SS_MCS5 0x9f +#define ODM_MGN_VHT2SS_MCS6 0xa0 +#define ODM_MGN_VHT2SS_MCS7 0xa1 +#define ODM_MGN_VHT2SS_MCS8 0xa2 +#define ODM_MGN_VHT2SS_MCS9 0xa3 + +#define ODM_MGN_MCS0_SG 0xc0 +#define ODM_MGN_MCS1_SG 0xc1 +#define ODM_MGN_MCS2_SG 0xc2 +#define ODM_MGN_MCS3_SG 0xc3 +#define ODM_MGN_MCS4_SG 0xc4 +#define ODM_MGN_MCS5_SG 0xc5 +#define ODM_MGN_MCS6_SG 0xc6 +#define ODM_MGN_MCS7_SG 0xc7 +#define ODM_MGN_MCS8_SG 0xc8 +#define ODM_MGN_MCS9_SG 0xc9 +#define ODM_MGN_MCS10_SG 0xca +#define ODM_MGN_MCS11_SG 0xcb +#define ODM_MGN_MCS12_SG 0xcc +#define ODM_MGN_MCS13_SG 0xcd +#define ODM_MGN_MCS14_SG 0xce +#define ODM_MGN_MCS15_SG 0xcf + +/* -----DESC rate--------------------------------- */ + +#define ODM_RATEMCS15_SG 0x1c +#define ODM_RATEMCS32 0x20 + + +// CCK Rates, TxHT = 0 +#define ODM_RATE1M 0x00 +#define ODM_RATE2M 0x01 +#define ODM_RATE5_5M 0x02 +#define ODM_RATE11M 0x03 +// OFDM Rates, TxHT = 0 +#define ODM_RATE6M 0x04 +#define ODM_RATE9M 0x05 +#define ODM_RATE12M 0x06 +#define ODM_RATE18M 0x07 +#define ODM_RATE24M 0x08 +#define ODM_RATE36M 0x09 +#define ODM_RATE48M 0x0A +#define ODM_RATE54M 0x0B +// MCS Rates, TxHT = 1 +#define ODM_RATEMCS0 0x0C +#define ODM_RATEMCS1 0x0D +#define ODM_RATEMCS2 0x0E +#define ODM_RATEMCS3 0x0F +#define ODM_RATEMCS4 0x10 +#define ODM_RATEMCS5 0x11 +#define ODM_RATEMCS6 0x12 +#define ODM_RATEMCS7 0x13 +#define ODM_RATEMCS8 0x14 +#define ODM_RATEMCS9 0x15 +#define ODM_RATEMCS10 0x16 +#define ODM_RATEMCS11 0x17 +#define ODM_RATEMCS12 0x18 +#define ODM_RATEMCS13 0x19 +#define ODM_RATEMCS14 0x1A +#define ODM_RATEMCS15 0x1B +#define ODM_RATEMCS16 0x1C +#define ODM_RATEMCS17 0x1D +#define ODM_RATEMCS18 0x1E +#define ODM_RATEMCS19 0x1F +#define ODM_RATEMCS20 0x20 +#define ODM_RATEMCS21 0x21 +#define ODM_RATEMCS22 0x22 +#define ODM_RATEMCS23 0x23 +#define ODM_RATEMCS24 0x24 +#define ODM_RATEMCS25 0x25 +#define ODM_RATEMCS26 0x26 +#define ODM_RATEMCS27 0x27 +#define ODM_RATEMCS28 0x28 +#define ODM_RATEMCS29 0x29 +#define ODM_RATEMCS30 0x2A +#define ODM_RATEMCS31 0x2B +#define ODM_RATEVHTSS1MCS0 0x2C +#define ODM_RATEVHTSS1MCS1 0x2D +#define ODM_RATEVHTSS1MCS2 0x2E +#define ODM_RATEVHTSS1MCS3 0x2F +#define ODM_RATEVHTSS1MCS4 0x30 +#define ODM_RATEVHTSS1MCS5 0x31 +#define ODM_RATEVHTSS1MCS6 0x32 +#define ODM_RATEVHTSS1MCS7 0x33 +#define ODM_RATEVHTSS1MCS8 0x34 +#define ODM_RATEVHTSS1MCS9 0x35 +#define ODM_RATEVHTSS2MCS0 0x36 +#define ODM_RATEVHTSS2MCS1 0x37 +#define ODM_RATEVHTSS2MCS2 0x38 +#define ODM_RATEVHTSS2MCS3 0x39 +#define ODM_RATEVHTSS2MCS4 0x3A +#define ODM_RATEVHTSS2MCS5 0x3B +#define ODM_RATEVHTSS2MCS6 0x3C +#define ODM_RATEVHTSS2MCS7 0x3D +#define ODM_RATEVHTSS2MCS8 0x3E +#define ODM_RATEVHTSS2MCS9 0x3F +#define ODM_RATEVHTSS3MCS0 0x40 +#define ODM_RATEVHTSS3MCS1 0x41 +#define ODM_RATEVHTSS3MCS2 0x42 +#define ODM_RATEVHTSS3MCS3 0x43 +#define ODM_RATEVHTSS3MCS4 0x44 +#define ODM_RATEVHTSS3MCS5 0x45 +#define ODM_RATEVHTSS3MCS6 0x46 +#define ODM_RATEVHTSS3MCS7 0x47 +#define ODM_RATEVHTSS3MCS8 0x48 +#define ODM_RATEVHTSS3MCS9 0x49 +#define ODM_RATEVHTSS4MCS0 0x4A +#define ODM_RATEVHTSS4MCS1 0x4B +#define ODM_RATEVHTSS4MCS2 0x4C +#define ODM_RATEVHTSS4MCS3 0x4D +#define ODM_RATEVHTSS4MCS4 0x4E +#define ODM_RATEVHTSS4MCS5 0x4F +#define ODM_RATEVHTSS4MCS6 0x50 +#define ODM_RATEVHTSS4MCS7 0x51 +#define ODM_RATEVHTSS4MCS8 0x52 +#define ODM_RATEVHTSS4MCS9 0x53 + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1) +#else + #if (RTL8192E_SUPPORT == 1) + #define ODM_NUM_RATE_IDX (ODM_RATEMCS15+1) + #elif (RTL8723B_SUPPORT == 1) || (RTL8188E_SUPPORT == 1) || (RTL8188F_SUPPORT == 1) + #define ODM_NUM_RATE_IDX (ODM_RATEMCS7+1) + #elif (RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) + #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS1MCS9+1) + #elif (RTL8812A_SUPPORT == 1) + #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS2MCS9+1) + #elif(RTL8814A_SUPPORT == 1) + #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS3MCS9+1) + #else + #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9+1) + #endif +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#define CONFIG_SFW_SUPPORTED +#endif + +//1 ============================================================ +//1 enumeration +//1 ============================================================ + + +// ODM_CMNINFO_INTERFACE +typedef enum tag_ODM_Support_Interface_Definition +{ + ODM_ITRF_PCIE = 0x1, + ODM_ITRF_USB = 0x2, + ODM_ITRF_SDIO = 0x4, + ODM_ITRF_ALL = 0x7, +}ODM_INTERFACE_E; + +// ODM_CMNINFO_IC_TYPE +typedef enum tag_ODM_Support_IC_Type_Definition +{ + ODM_RTL8192S = BIT0, + ODM_RTL8192C = BIT1, + ODM_RTL8192D = BIT2, + ODM_RTL8723A = BIT3, + ODM_RTL8188E = BIT4, + ODM_RTL8812 = BIT5, + ODM_RTL8821 = BIT6, + ODM_RTL8192E = BIT7, + ODM_RTL8723B = BIT8, + ODM_RTL8814A = BIT9, + ODM_RTL8881A = BIT10, + ODM_RTL8821B = BIT11, + ODM_RTL8822B = BIT12, + ODM_RTL8703B = BIT13, + ODM_RTL8195A = BIT14, + ODM_RTL8188F = BIT15 +}ODM_IC_TYPE_E; + + + + +#define ODM_IC_11N_SERIES (ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8703B|ODM_RTL8188F) +#define ODM_IC_11AC_SERIES (ODM_RTL8812|ODM_RTL8821|ODM_RTL8814A|ODM_RTL8881A|ODM_RTL8821B|ODM_RTL8822B) +#define ODM_IC_TXBF_SUPPORT (ODM_RTL8192E|ODM_RTL8812|ODM_RTL8821|ODM_RTL8814A|ODM_RTL8881A|ODM_RTL8822B) +#define ODM_IC_11N_GAIN_IDX_EDCCA (ODM_RTL8195A|ODM_RTL8703B|ODM_RTL8188F) +#define ODM_IC_11AC_GAIN_IDX_EDCCA (ODM_RTL8814A|ODM_RTL8822B) + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + +#ifdef RTK_AC_SUPPORT +#define ODM_IC_11AC_SERIES_SUPPORT 1 +#else +#define ODM_IC_11AC_SERIES_SUPPORT 0 +#endif + +#define ODM_IC_11N_SERIES_SUPPORT 1 +#define ODM_CONFIG_BT_COEXIST 0 + +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +#define ODM_IC_11AC_SERIES_SUPPORT 1 +#define ODM_IC_11N_SERIES_SUPPORT 1 +#define ODM_CONFIG_BT_COEXIST 1 + +#else + +#if((RTL8192C_SUPPORT == 1) || (RTL8192D_SUPPORT == 1) || (RTL8723A_SUPPORT == 1) || (RTL8188E_SUPPORT == 1) ||\ +(RTL8723B_SUPPORT == 1) || (RTL8192E_SUPPORT == 1) || (RTL8195A_SUPPORT == 1) || (RTL8703B_SUPPORT == 1) || \ +(RTL8188F_SUPPORT == 1)) +#define ODM_IC_11N_SERIES_SUPPORT 1 +#define ODM_IC_11AC_SERIES_SUPPORT 0 +#else +#define ODM_IC_11N_SERIES_SUPPORT 0 +#define ODM_IC_11AC_SERIES_SUPPORT 1 +#endif + +#ifdef CONFIG_BT_COEXIST +#define ODM_CONFIG_BT_COEXIST 1 +#else +#define ODM_CONFIG_BT_COEXIST 0 +#endif + +#endif + + +//ODM_CMNINFO_CUT_VER +typedef enum tag_ODM_Cut_Version_Definition +{ + ODM_CUT_A = 0, + ODM_CUT_B = 1, + ODM_CUT_C = 2, + ODM_CUT_D = 3, + ODM_CUT_E = 4, + ODM_CUT_F = 5, + + ODM_CUT_I = 8, + ODM_CUT_J = 9, + ODM_CUT_K = 10, + ODM_CUT_TEST = 15, +}ODM_CUT_VERSION_E; + +// ODM_CMNINFO_FAB_VER +typedef enum tag_ODM_Fab_Version_Definition +{ + ODM_TSMC = 0, + ODM_UMC = 1, +}ODM_FAB_E; + +// ODM_CMNINFO_RF_TYPE +// +// For example 1T2R (A+AB = BIT0|BIT4|BIT5) +// +typedef enum tag_ODM_RF_Path_Bit_Definition +{ + ODM_RF_A = BIT0, + ODM_RF_B = BIT1, + ODM_RF_C = BIT2, + ODM_RF_D = BIT3, +}ODM_RF_PATH_E; + +typedef enum tag_PHYDM_RF_TX_NUM { + ODM_1T = 1, + ODM_2T = 2, + ODM_3T = 3, + ODM_4T = 4, +} ODM_RF_TX_NUM_E; + +typedef enum tag_ODM_RF_Type_Definition { + ODM_1T1R, + ODM_1T2R, + ODM_2T2R, + ODM_2T2R_GREEN, + ODM_2T3R, + ODM_2T4R, + ODM_3T3R, + ODM_3T4R, + ODM_4T4R, + ODM_XTXR +}ODM_RF_TYPE_E; + + +typedef enum tag_ODM_MAC_PHY_Mode_Definition +{ + ODM_SMSP = 0, + ODM_DMSP = 1, + ODM_DMDP = 2, +}ODM_MAC_PHY_MODE_E; + + +typedef enum tag_BT_Coexist_Definition +{ + ODM_BT_BUSY = 1, + ODM_BT_ON = 2, + ODM_BT_OFF = 3, + ODM_BT_NONE = 4, +}ODM_BT_COEXIST_E; + +// ODM_CMNINFO_OP_MODE +typedef enum tag_Operation_Mode_Definition +{ + ODM_NO_LINK = BIT0, + ODM_LINK = BIT1, + ODM_SCAN = BIT2, + ODM_POWERSAVE = BIT3, + ODM_AP_MODE = BIT4, + ODM_CLIENT_MODE = BIT5, + ODM_AD_HOC = BIT6, + ODM_WIFI_DIRECT = BIT7, + ODM_WIFI_DISPLAY = BIT8, +}ODM_OPERATION_MODE_E; + +// ODM_CMNINFO_WM_MODE +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) +typedef enum tag_Wireless_Mode_Definition +{ + ODM_WM_UNKNOW = 0x0, + ODM_WM_B = BIT0, + ODM_WM_G = BIT1, + ODM_WM_A = BIT2, + ODM_WM_N24G = BIT3, + ODM_WM_N5G = BIT4, + ODM_WM_AUTO = BIT5, + ODM_WM_AC = BIT6, +}ODM_WIRELESS_MODE_E; +#else +typedef enum tag_Wireless_Mode_Definition +{ + ODM_WM_UNKNOWN = 0x00,/*0x0*/ + ODM_WM_A = BIT0, /* 0x1*/ + ODM_WM_B = BIT1, /* 0x2*/ + ODM_WM_G = BIT2,/* 0x4*/ + ODM_WM_AUTO = BIT3,/* 0x8*/ + ODM_WM_N24G = BIT4,/* 0x10*/ + ODM_WM_N5G = BIT5,/* 0x20*/ + ODM_WM_AC_5G = BIT6,/* 0x40*/ + ODM_WM_AC_24G = BIT7,/* 0x80*/ + ODM_WM_AC_ONLY = BIT8,/* 0x100*/ + ODM_WM_MAX = BIT11/* 0x800*/ + +}ODM_WIRELESS_MODE_E; +#endif + +// ODM_CMNINFO_BAND +typedef enum tag_Band_Type_Definition +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + ODM_BAND_2_4G = BIT0, + ODM_BAND_5G = BIT1, +#else + ODM_BAND_2_4G = 0, + ODM_BAND_5G, + ODM_BAND_ON_BOTH, + ODM_BANDMAX +#endif +}ODM_BAND_TYPE_E; + + +// ODM_CMNINFO_SEC_CHNL_OFFSET +typedef enum tag_Secondary_Channel_Offset_Definition +{ + ODM_DONT_CARE = 0, + ODM_BELOW = 1, + ODM_ABOVE = 2 +}ODM_SEC_CHNL_OFFSET_E; + +// ODM_CMNINFO_SEC_MODE +typedef enum tag_Security_Definition +{ + ODM_SEC_OPEN = 0, + ODM_SEC_WEP40 = 1, + ODM_SEC_TKIP = 2, + ODM_SEC_RESERVE = 3, + ODM_SEC_AESCCMP = 4, + ODM_SEC_WEP104 = 5, + ODM_WEP_WPA_MIXED = 6, // WEP + WPA + ODM_SEC_SMS4 = 7, +}ODM_SECURITY_E; + +// ODM_CMNINFO_BW +typedef enum tag_Bandwidth_Definition +{ + ODM_BW20M = 0, + ODM_BW40M = 1, + ODM_BW80M = 2, + ODM_BW160M = 3, + ODM_BW5M = 4, + ODM_BW10M = 5, + ODM_BW_MAX = 6 +}ODM_BW_E; + +// ODM_CMNINFO_CHNL + +// ODM_CMNINFO_BOARD_TYPE +typedef enum tag_Board_Definition +{ + ODM_BOARD_DEFAULT = 0, // The DEFAULT case. + ODM_BOARD_MINICARD = BIT(0), // 0 = non-mini card, 1= mini card. + ODM_BOARD_SLIM = BIT(1), // 0 = non-slim card, 1 = slim card + ODM_BOARD_BT = BIT(2), // 0 = without BT card, 1 = with BT + ODM_BOARD_EXT_PA = BIT(3), // 0 = no 2G ext-PA, 1 = existing 2G ext-PA + ODM_BOARD_EXT_LNA = BIT(4), // 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA + ODM_BOARD_EXT_TRSW = BIT(5), // 0 = no ext-TRSW, 1 = existing ext-TRSW + ODM_BOARD_EXT_PA_5G = BIT(6), // 0 = no 5G ext-PA, 1 = existing 5G ext-PA + ODM_BOARD_EXT_LNA_5G= BIT(7), // 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA +}ODM_BOARD_TYPE_E; + +typedef enum tag_ODM_Package_Definition +{ + ODM_PACKAGE_DEFAULT = 0, + ODM_PACKAGE_QFN68 = BIT(0), + ODM_PACKAGE_TFBGA90 = BIT(1), + ODM_PACKAGE_TFBGA79 = BIT(2), +}ODM_Package_TYPE_E; + +typedef enum tag_ODM_TYPE_GPA_Definition { + TYPE_GPA0 = 0x0000, + TYPE_GPA1 = 0x0055, + TYPE_GPA2 = 0x00AA, + TYPE_GPA3 = 0x00FF, + TYPE_GPA4 = 0x5500, + TYPE_GPA5 = 0x5555, + TYPE_GPA6 = 0x55AA, + TYPE_GPA7 = 0x55FF, + TYPE_GPA8 = 0xAA00, + TYPE_GPA9 = 0xAA55, + TYPE_GPA10 = 0xAAAA, + TYPE_GPA11 = 0xAAFF, + TYPE_GPA12 = 0xFF00, + TYPE_GPA13 = 0xFF55, + TYPE_GPA14 = 0xFFAA, + TYPE_GPA15 = 0xFFFF, +}ODM_TYPE_GPA_E; + +typedef enum tag_ODM_TYPE_APA_Definition { + TYPE_APA0 = 0x0000, + TYPE_APA1 = 0x0055, + TYPE_APA2 = 0x00AA, + TYPE_APA3 = 0x00FF, + TYPE_APA4 = 0x5500, + TYPE_APA5 = 0x5555, + TYPE_APA6 = 0x55AA, + TYPE_APA7 = 0x55FF, + TYPE_APA8 = 0xAA00, + TYPE_APA9 = 0xAA55, + TYPE_APA10 = 0xAAAA, + TYPE_APA11 = 0xAAFF, + TYPE_APA12 = 0xFF00, + TYPE_APA13 = 0xFF55, + TYPE_APA14 = 0xFFAA, + TYPE_APA15 = 0xFFFF, +}ODM_TYPE_APA_E; + +typedef enum tag_ODM_TYPE_GLNA_Definition { + TYPE_GLNA0 = 0x0000, + TYPE_GLNA1 = 0x0055, + TYPE_GLNA2 = 0x00AA, + TYPE_GLNA3 = 0x00FF, + TYPE_GLNA4 = 0x5500, + TYPE_GLNA5 = 0x5555, + TYPE_GLNA6 = 0x55AA, + TYPE_GLNA7 = 0x55FF, + TYPE_GLNA8 = 0xAA00, + TYPE_GLNA9 = 0xAA55, + TYPE_GLNA10 = 0xAAAA, + TYPE_GLNA11 = 0xAAFF, + TYPE_GLNA12 = 0xFF00, + TYPE_GLNA13 = 0xFF55, + TYPE_GLNA14 = 0xFFAA, + TYPE_GLNA15 = 0xFFFF, +}ODM_TYPE_GLNA_E; + +typedef enum tag_ODM_TYPE_ALNA_Definition { + TYPE_ALNA0 = 0x0000, + TYPE_ALNA1 = 0x0055, + TYPE_ALNA2 = 0x00AA, + TYPE_ALNA3 = 0x00FF, + TYPE_ALNA4 = 0x5500, + TYPE_ALNA5 = 0x5555, + TYPE_ALNA6 = 0x55AA, + TYPE_ALNA7 = 0x55FF, + TYPE_ALNA8 = 0xAA00, + TYPE_ALNA9 = 0xAA55, + TYPE_ALNA10 = 0xAAAA, + TYPE_ALNA11 = 0xAAFF, + TYPE_ALNA12 = 0xFF00, + TYPE_ALNA13 = 0xFF55, + TYPE_ALNA14 = 0xFFAA, + TYPE_ALNA15 = 0xFFFF, +}ODM_TYPE_ALNA_E; + + +typedef enum _ODM_RF_RADIO_PATH { + ODM_RF_PATH_A = 0, //Radio Path A + ODM_RF_PATH_B = 1, //Radio Path B + ODM_RF_PATH_C = 2, //Radio Path C + ODM_RF_PATH_D = 3, //Radio Path D + ODM_RF_PATH_AB, + ODM_RF_PATH_AC, + ODM_RF_PATH_AD, + ODM_RF_PATH_BC, + ODM_RF_PATH_BD, + ODM_RF_PATH_CD, + ODM_RF_PATH_ABC, + ODM_RF_PATH_ACD, + ODM_RF_PATH_BCD, + ODM_RF_PATH_ABCD, + // ODM_RF_PATH_MAX, //Max RF number 90 support +} ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E; + +typedef enum _ODM_PARAMETER_INIT { + ODM_PRE_SETTING = 0, + ODM_POST_SETTING = 1, +} ODM_PARAMETER_INIT_E; + +#endif diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_precomp.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_precomp.h new file mode 100644 index 000000000..99f96a771 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_precomp.h @@ -0,0 +1,320 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __ODM_PRECOMP_H__ +#define __ODM_PRECOMP_H__ + +#include "phydm_types.h" +#include "phydm_features.h" + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#include "Precomp.h" // We need to include mp_precomp.h due to batch file setting. +#else +#define TEST_FALG___ 1 +#endif + +#if (DM_ODM_SUPPORT_TYPE ==ODM_CE) +#define RTL8192CE_SUPPORT 0 +#define RTL8192CU_SUPPORT 0 +#define RTL8192C_SUPPORT 0 + +#define RTL8192DE_SUPPORT 0 +#define RTL8192DU_SUPPORT 0 +#define RTL8192D_SUPPORT 0 + +#define RTL8723AU_SUPPORT 0 +#define RTL8723AS_SUPPORT 0 +#define RTL8723AE_SUPPORT 0 +#define RTL8723A_SUPPORT 0 +#define RTL8723_FPGA_VERIFICATION 0 +#endif + +//2 Config Flags and Structs - defined by each ODM Type + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "../8192cd_cfg.h" + #include "../odm_inc.h" + + #include "../8192cd.h" + #include "../8192cd_util.h" + #ifdef _BIG_ENDIAN_ + #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG + #else + #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE + #endif + + #ifdef AP_BUILD_WORKAROUND + #include "../8192cd_headers.h" + #include "../8192cd_debug.h" + #endif + +#elif (DM_ODM_SUPPORT_TYPE ==ODM_CE) + #define __PACK + #define __WLAN_ATTRIB_PACK__ +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "mp_precomp.h" + #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE + #define __PACK + #define __WLAN_ATTRIB_PACK__ +#endif + +//2 OutSrc Header Files + +#include "phydm.h" +#include "phydm_hwconfig.h" +#include "phydm_debug.h" +#include "phydm_regdefine11ac.h" +#include "phydm_regdefine11n.h" +#include "phydm_interface.h" +#include "phydm_reg.h" + + +#if (DM_ODM_SUPPORT_TYPE & ODM_CE) +#define RTL8821B_SUPPORT 0 +#define RTL8822B_SUPPORT 0 + +VOID +PHY_SetTxPowerLimit( + IN PDM_ODM_T pDM_Odm, + IN u8 *Regulation, + IN u8 *Band, + IN u8 *Bandwidth, + IN u8 *RateSection, + IN u8 *RfPath, + IN u8 *Channel, + IN u8 *PowerLimit +); + +#endif + +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) +#define RTL8821B_SUPPORT 0 +#define RTL8822B_SUPPORT 0 +#define RTL8703B_SUPPORT 0 +#define RTL8188F_SUPPORT 0 +#endif + +#if RTL8188E_SUPPORT == 1 +#define RTL8188E_T_SUPPORT 1 +#ifdef CONFIG_SFW_SUPPORTED +#define RTL8188E_S_SUPPORT 1 +#else +#define RTL8188E_S_SUPPORT 0 +#endif +#endif + +#if (RTL8188E_SUPPORT==1) +#include "rtl8188e/hal8188erateadaptive.h"//for RA,Power training +#include "rtl8188e/halhwimg8188e_mac.h" +#include "rtl8188e/halhwimg8188e_rf.h" +#include "rtl8188e/halhwimg8188e_bb.h" +#include "rtl8188e/halhwimg8188e_t_fw.h" +#include "rtl8188e/halhwimg8188e_s_fw.h" +#include "rtl8188e/phydm_regconfig8188e.h" +#include "rtl8188e/phydm_rtl8188e.h" +#include "rtl8188e/hal8188ereg.h" +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8188e_hal.h" + #include "rtl8188e/halphyrf_8188e_ce.h" +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "rtl8188e/halphyrf_8188e_win.h" +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "rtl8188e/halphyrf_8188e_ap.h" +#endif +#endif //88E END + +#if (RTL8192E_SUPPORT==1) + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "rtl8192e/halphyrf_8192e_win.h" /*FOR_8192E_IQK*/ + #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "rtl8192e/halphyrf_8192e_ap.h" /*FOR_8192E_IQK*/ + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8192e/halphyrf_8192e_ce.h" /*FOR_8192E_IQK*/ + #endif + +#include "rtl8192e/phydm_rtl8192e.h" //FOR_8192E_IQK +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) + #include "rtl8192e/halhwimg8192e_bb.h" + #include "rtl8192e/halhwimg8192e_mac.h" + #include "rtl8192e/halhwimg8192e_rf.h" + #include "rtl8192e/phydm_regconfig8192e.h" + #include "rtl8192e/halhwimg8192e_fw.h" + #include "rtl8192e/hal8192ereg.h" +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8192e_hal.h" +#endif +#endif //92E END + +#if (RTL8812A_SUPPORT==1) + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "rtl8812a/halphyrf_8812a_win.h" + #elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "rtl8812a/halphyrf_8812a_ap.h" + #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8812a/halphyrf_8812a_ce.h" + #endif + + //#include "rtl8812a/HalPhyRf_8812A.h" //FOR_8812_IQK + #if (DM_ODM_SUPPORT_TYPE != ODM_AP) + #include "rtl8812a/halhwimg8812a_bb.h" + #include "rtl8812a/halhwimg8812a_mac.h" + #include "rtl8812a/halhwimg8812a_rf.h" + #include "rtl8812a/phydm_regconfig8812a.h" + #include "rtl8812a/halhwimg8812a_fw.h" + #include "rtl8812a/phydm_rtl8812a.h" + #endif + + #if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8812a_hal.h" + #endif + +#endif //8812 END + +#if (RTL8814A_SUPPORT==1) + +#include "rtl8814a/halhwimg8814a_mac.h" +#include "rtl8814a/halhwimg8814a_rf.h" +#include "rtl8814a/halhwimg8814a_bb.h" +#if (DM_ODM_SUPPORT_TYPE != ODM_AP) + #include "rtl8814a/halhwimg8814a_fw.h" + #include "rtl8814a/phydm_rtl8814a.h" +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "rtl8814a/halphyrf_8814a_win.h" +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8814a/halphyrf_8814a_ce.h" +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + #include "rtl8814a/halphyrf_8814a_ap.h" +#endif + #include "rtl8814a/phydm_regconfig8814a.h" +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8814a_hal.h" + #include "rtl8814a/phydm_iqk_8814a.h" +#endif +#endif //8814 END + +#if (RTL8881A_SUPPORT==1)//FOR_8881_IQK +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#include "rtl8821a/phydm_iqk_8821a_win.h" +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +#include "rtl8821a/phydm_iqk_8821a_ce.h" +#else +#include "rtl8821a/phydm_iqk_8821a_ap.h" +#endif +//#include "rtl8881a/HalHWImg8881A_BB.h" +//#include "rtl8881a/HalHWImg8881A_MAC.h" +//#include "rtl8881a/HalHWImg8881A_RF.h" +//#include "rtl8881a/odm_RegConfig8881A.h" +#endif + +#if (RTL8723B_SUPPORT==1) +#include "rtl8723b/halhwimg8723b_mac.h" +#include "rtl8723b/halhwimg8723b_rf.h" +#include "rtl8723b/halhwimg8723b_bb.h" +#include "rtl8723b/halhwimg8723b_fw.h" +#include "rtl8723b/phydm_regconfig8723b.h" +#include "rtl8723b/phydm_rtl8723b.h" +#include "rtl8723b/hal8723breg.h" +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "rtl8723b/halphyrf_8723b_win.h" +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8723b/halphyrf_8723b_ce.h" + #include "rtl8723b/halhwimg8723b_mp.h" + #include "rtl8723b_hal.h" +#endif +#endif + +#if (RTL8821A_SUPPORT==1) +#include "rtl8821a/halhwimg8821a_mac.h" +#include "rtl8821a/halhwimg8821a_rf.h" +#include "rtl8821a/halhwimg8821a_bb.h" +#include "rtl8821a/halhwimg8821a_fw.h" +#include "rtl8821a/phydm_regconfig8821a.h" +#include "rtl8821a/phydm_rtl8821a.h" +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #include "rtl8821a/halphyrf_8821a_win.h" +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include "rtl8821a/halphyrf_8821a_ce.h" + #include "rtl8821a/phydm_iqk_8821a_ce.h"/*for IQK*/ + #include "rtl8812a/halphyrf_8812a_ce.h"/*for IQK,LCK,Power-tracking*/ + #include "rtl8812a_hal.h" +#else +#endif +#endif + +#if (RTL8821B_SUPPORT==1) +#include "rtl8821b/halhwimg8821b_mac.h" +#include "rtl8821b/halhwimg8821b_rf.h" +#include "rtl8821b/halhwimg8821b_bb.h" +#include "rtl8821b/halhwimg8821b_fw.h" +#include "rtl8821b/phydm_regconfig8821b.h" +#include "rtl8821b/halhwimg8821b_testchip_mac.h" +#include "rtl8821b/halhwimg8821b_testchip_rf.h" +#include "rtl8821b/halhwimg8821b_testchip_bb.h" +#include "rtl8821b/halhwimg8821b_testchip_fw.h" +#include "rtl8821b/halphyrf_8821b.h" +#endif + +#if (RTL8822B_SUPPORT==1) +#include "rtl8822b/halhwimg8822b_mac.h" +#include "rtl8822b/halhwimg8822b_rf.h" +#include "rtl8822b/halhwimg8822b_bb.h" +/*#include "rtl8822b/halhwimg8822b_fw.h"*/ +#include "rtl8822b/phydm_regconfig8822b.h" +#include "rtl8822b/halphyrf_8822b.h" +#include "rtl8822b/phydm_rtl8822b.h" +#include "rtl8822b/phydm_hal_api8822b.h" +#include "rtl8822b/version_rtl8822b.h" +#endif + +#if (RTL8703B_SUPPORT==1) +#include "rtl8703b/phydm_regconfig8703b.h" +#include "rtl8703b/halhwimg8703b_mac.h" +#include "rtl8703b/halhwimg8703b_rf.h" +#include "rtl8703b/halhwimg8703b_bb.h" +#include "rtl8703b/halhwimg8703b_fw.h" +#include "rtl8703b/halphyrf_8703b.h" +#include "rtl8703b/version_rtl8703b.h" +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +#include "rtl8703b_hal.h" +#endif +#endif + +#if (RTL8188F_SUPPORT == 1) +#include "rtl8188f/halhwimg8188f_mac.h" +#include "rtl8188f/halhwimg8188f_rf.h" +#include "rtl8188f/halhwimg8188f_bb.h" +#include "rtl8188f/halhwimg8188f_fw.h" +#include "rtl8188f/hal8188freg.h" +#include "rtl8188f/phydm_rtl8188f.h" +#include "rtl8188f/phydm_regconfig8188f.h" +#include "rtl8188f/halphyrf_8188f.h" /* for IQK,LCK,Power-tracking */ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +#include "rtl8188f_hal.h" +#endif +#endif + +#endif // __ODM_PRECOMP_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_rainfo.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_rainfo.c new file mode 100644 index 000000000..5cd230813 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_rainfo.c @@ -0,0 +1,2574 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#if (defined(CONFIG_RA_DBG_CMD)) +VOID +ODM_C2HRaParaReportHandler( + IN PVOID pDM_VOID, + IN pu1Byte CmdBuf, + IN u1Byte CmdLen +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + + u1Byte para_idx = CmdBuf[0]; //Retry Penalty, NH, NL + u1Byte RateTypeStart = CmdBuf[1]; + u1Byte RateTypeLength = CmdLen - 2; + u1Byte i; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[ From FW C2H RA Para ] CmdBuf[0]= (( %d ))\n", CmdBuf[0])); + + if (para_idx == RADBG_RTY_PENALTY) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |Rate Index| |RTY Penality Index| \n")); + + for (i = 0 ; i < (RateTypeLength) ; i++) { + if (pRA_Table->is_ra_dbg_init) + pRA_Table->RTY_P_default[RateTypeStart + i] = CmdBuf[2 + i]; + + pRA_Table->RTY_P[RateTypeStart + i] = CmdBuf[2 + i]; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("%8d %15d \n", (RateTypeStart + i), pRA_Table->RTY_P[RateTypeStart + i])); + } + + } else if (para_idx == RADBG_N_HIGH) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |Rate Index| |N-High| \n")); + + + } else if (para_idx == RADBG_N_LOW){ + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |Rate Index| |N-Low| \n")); + + } + else if (para_idx == RADBG_RATE_UP_RTY_RATIO) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |Rate Index| |Rate Up RTY Ratio| \n")); + + for (i = 0 ; i < (RateTypeLength) ; i++) { + if (pRA_Table->is_ra_dbg_init) + pRA_Table->RATE_UP_RTY_RATIO_default[RateTypeStart + i] = CmdBuf[2 + i]; + + pRA_Table->RATE_UP_RTY_RATIO[RateTypeStart + i] = CmdBuf[2 + i]; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("%8d %15d \n", (RateTypeStart + i), pRA_Table->RATE_UP_RTY_RATIO[RateTypeStart + i])); + } + } else if (para_idx == RADBG_RATE_DOWN_RTY_RATIO) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |Rate Index| |Rate Down RTY Ratio| \n")); + + for (i = 0 ; i < (RateTypeLength) ; i++) { + if (pRA_Table->is_ra_dbg_init) + pRA_Table->RATE_DOWN_RTY_RATIO_default[RateTypeStart + i] = CmdBuf[2 + i]; + + pRA_Table->RATE_DOWN_RTY_RATIO[RateTypeStart + i] = CmdBuf[2 + i]; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("%8d %15d \n", (RateTypeStart + i), pRA_Table->RATE_DOWN_RTY_RATIO[RateTypeStart + i])); + } + } else if (para_idx == RADBG_DEBUG_MONITOR1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); + if (pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES) { + + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d \n", "RSSI =", CmdBuf[1])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x \n", "Rate =", CmdBuf[2] & 0x7f)); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d \n", "SGI =", (CmdBuf[2] & 0x80) >> 7)); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d \n", "BW =", CmdBuf[3])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d \n", "BW_max =", CmdBuf[4])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x \n", "multi_rate0 =", CmdBuf[5])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x \n", "multi_rate1 =", CmdBuf[6])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d \n", "DISRA =", CmdBuf[7])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d \n", "VHT_EN =", CmdBuf[8])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d \n", "SGI_support =", CmdBuf[9])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d \n", "try_ness =", CmdBuf[10])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x \n", "pre_rate =", CmdBuf[11])); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d \n", "RSSI =", CmdBuf[1])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %x \n", "BW =", CmdBuf[2])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d \n", "DISRA =", CmdBuf[3])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d \n", "VHT_EN =", CmdBuf[4])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d \n", "Hightest Rate =", CmdBuf[5])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x \n", "Lowest Rate =", CmdBuf[6])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x \n", "SGI_support =", CmdBuf[7])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d \n", "Rate_ID =", CmdBuf[8]));; + } + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); + } else if (para_idx == RADBG_DEBUG_MONITOR2) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); + if (pDM_Odm->SupportICType & PHYDM_IC_3081_SERIES) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %d \n", "RateID =", CmdBuf[1])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x \n", "highest_rate =", CmdBuf[2])); + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s 0x%x \n", "lowest_rate =", CmdBuf[3])); + + for (i = 4 ; i <= 11 ; i++) + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("RAMASK = 0x%x \n", CmdBuf[i])); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s %x%x %x%x %x%x %x%x \n", "RA Mask:", + CmdBuf[8], CmdBuf[7], CmdBuf[6], CmdBuf[5], CmdBuf[4], CmdBuf[3], CmdBuf[2], CmdBuf[1])); + } + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("-------------------------------\n")); + } else if (para_idx == RADBG_DEBUG_MONITOR3) { + + for (i = 0 ; i < (CmdLen - 1) ; i++) + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("content[%d] = %d \n", i, CmdBuf[1 + i])); + } else if (para_idx == RADBG_DEBUG_MONITOR4) + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("%5s {%d.%d} \n", "RA Version =", CmdBuf[1], CmdBuf[2])); + +} + +VOID +odm_RA_ParaAdjust_Send_H2C( + IN PVOID pDM_VOID +) +{ + + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + u1Byte H2C_Parameter[6] = {0}; + + H2C_Parameter[0] = RA_FIRST_MACID; + + //ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("RA_Para_feedback_req= (( %d )) \n",pRA_Table->RA_Para_feedback_req )); + if (pRA_Table->RA_Para_feedback_req) { //H2C_Parameter[5]=1 ; ask FW for all RA parameters + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] Ask FW for RA parameter \n")); + H2C_Parameter[5] |= BIT1; //ask FW to report RA parameters + H2C_Parameter[1] = pRA_Table->para_idx; //pRA_Table->para_idx; + pRA_Table->RA_Para_feedback_req = 0; + } else { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[H2C] Send H2C to FW for modifying RA parameter \n")); + + H2C_Parameter[1] = pRA_Table->para_idx; + H2C_Parameter[2] = pRA_Table->rate_idx; + //1 [8 bit] + if (pRA_Table->para_idx == RADBG_RTY_PENALTY || pRA_Table->para_idx == RADBG_RATE_UP_RTY_RATIO || pRA_Table->para_idx == RADBG_RATE_DOWN_RTY_RATIO) { + H2C_Parameter[3] = pRA_Table->value; + H2C_Parameter[4] = 0; + } + //1 [16 bit] + else { //if ((pRA_Table->rate_idx==RADBG_N_HIGH)||(pRA_Table->rate_idx==RADBG_N_LOW)) + H2C_Parameter[3] = (u1Byte)(((pRA_Table->value_16) & 0xf0) >> 4); //byte1 + H2C_Parameter[4] = (u1Byte)((pRA_Table->value_16) & 0x0f); //byte0 + } + } + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" H2C_Parameter[1] = 0x%x \n", H2C_Parameter[1])); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" H2C_Parameter[2] = 0x%x \n", H2C_Parameter[2])); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" H2C_Parameter[3] = 0x%x \n", H2C_Parameter[3])); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" H2C_Parameter[4] = 0x%x \n", H2C_Parameter[4])); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" H2C_Parameter[5] = 0x%x \n", H2C_Parameter[5])); + + ODM_FillH2CCmd(pDM_Odm, ODM_H2C_RA_PARA_ADJUST, 6, H2C_Parameter); + +} + + +VOID +odm_RA_ParaAdjust( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + u1Byte para_idx = pRA_Table->para_idx; + u1Byte rate_idx = pRA_Table->rate_idx; + u1Byte value = pRA_Table->value; + u1Byte Pre_value = 0xff; + + BOOLEAN sign = 0; + + if (pRA_Table->para_idx == RADBG_RTY_PENALTY) { + Pre_value = pRA_Table->RTY_P[rate_idx]; + pRA_Table->RTY_P[rate_idx] = value; + pRA_Table->RTY_P_modify_note[rate_idx] = 1; + } else if (pRA_Table->para_idx == RADBG_N_HIGH) { + + } else if (pRA_Table->para_idx == RADBG_N_LOW) { + + } else if (pRA_Table->para_idx == RADBG_RATE_UP_RTY_RATIO) { + Pre_value = pRA_Table->RATE_UP_RTY_RATIO[rate_idx]; + pRA_Table->RATE_UP_RTY_RATIO[rate_idx] = value; + pRA_Table->RATE_UP_RTY_RATIO_modify_note[rate_idx] = 1; + } else if (pRA_Table->para_idx == RADBG_RATE_DOWN_RTY_RATIO) { + Pre_value = pRA_Table->RATE_DOWN_RTY_RATIO[rate_idx]; + pRA_Table->RATE_DOWN_RTY_RATIO[rate_idx] = value; + pRA_Table->RATE_DOWN_RTY_RATIO_modify_note[rate_idx] = 1; + } + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" Change RA Papa[%d], Rate[ %d ], ((%d)) -> ((%d)) \n", pRA_Table->para_idx, rate_idx, Pre_value, value)); + odm_RA_ParaAdjust_Send_H2C(pDM_Odm); +} + + +VOID +phydm_ra_print_msg( + IN PVOID pDM_VOID, + IN u1Byte *value, + IN u1Byte *value_default, + IN u1Byte *modify_note +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + u4Byte i; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" |Rate index| |Current-value| |Default-value| |Modify?| \n")); + for (i = 0 ; i <= (pRA_Table->rate_length); i++) { +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [ %d ] %20d %25d %20s \n", i, value[i], value_default[i], ((modify_note[i] == 1) ? "V" : " . "))); +#else + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [ %d ] %10d %14d %14s \n", i, value[i], value_default[i], ((modify_note[i] == 1) ? "V" : " . "))); +#endif + } + +} + +VOID +odm_RA_debug( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + + pRA_Table->is_ra_dbg_init = FALSE; + + if (dm_value[0] == 100) { /*1 Print RA Parameters*/ + u1Byte default_pointer_value; + u1Byte *pvalue; + u1Byte *pvalue_default; + u1Byte *pmodify_note; + + pvalue = pvalue_default = pmodify_note = &default_pointer_value; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("\n------------------------------------------------------------------------------------\n")); + + if (dm_value[1] == RADBG_RTY_PENALTY) { /* [1]*/ + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [1] RTY_PENALTY\n")); + pvalue = &(pRA_Table->RTY_P[0]); + pvalue_default = &(pRA_Table->RTY_P_default[0]); + pmodify_note = (u1Byte *)&(pRA_Table->RTY_P_modify_note[0]); + } else if (dm_value[1] == RADBG_N_HIGH) { /* [2]*/ + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [2] N_HIGH\n")); + + } else if (dm_value[1] == RADBG_N_LOW) { /*[3]*/ + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [3] N_LOW\n")); + + } else if (dm_value[1] == RADBG_RATE_UP_RTY_RATIO) { /* [8]*/ + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [8] RATE_UP_RTY_RATIO\n")); + pvalue = &(pRA_Table->RATE_UP_RTY_RATIO[0]); + pvalue_default = &(pRA_Table->RATE_UP_RTY_RATIO_default[0]); + pmodify_note = (u1Byte *)&(pRA_Table->RATE_UP_RTY_RATIO_modify_note[0]); + } else if (dm_value[1] == RADBG_RATE_DOWN_RTY_RATIO) { /* [9]*/ + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" [9] RATE_DOWN_RTY_RATIO\n")); + pvalue = &(pRA_Table->RATE_DOWN_RTY_RATIO[0]); + pvalue_default = &(pRA_Table->RATE_DOWN_RTY_RATIO_default[0]); + pmodify_note = (u1Byte *)&(pRA_Table->RATE_DOWN_RTY_RATIO_modify_note[0]); + } + + phydm_ra_print_msg(pDM_Odm, pvalue, pvalue_default, pmodify_note); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("\n------------------------------------------------------------------------------------\n\n")); + + } else if (dm_value[0] == 101) { + pRA_Table->para_idx = (u1Byte)dm_value[1]; + + pRA_Table->RA_Para_feedback_req = 1; + odm_RA_ParaAdjust_Send_H2C(pDM_Odm); + } else { + pRA_Table->para_idx = (u1Byte)dm_value[0]; + pRA_Table->rate_idx = (u1Byte)dm_value[1]; + pRA_Table->value = (u1Byte)dm_value[2]; + + odm_RA_ParaAdjust(pDM_Odm); + } + +} + +VOID +odm_RA_ParaAdjust_init( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + u1Byte i; + u1Byte ra_para_pool_u8[3] = { RADBG_RTY_PENALTY, RADBG_RATE_UP_RTY_RATIO, RADBG_RATE_DOWN_RTY_RATIO}; + /* + RTY_PENALTY = 1, //u8 + N_HIGH = 2, + N_LOW = 3, + RATE_UP_TABLE = 4, + RATE_DOWN_TABLE = 5, + TRYING_NECESSARY = 6, + DROPING_NECESSARY = 7, + RATE_UP_RTY_RATIO = 8, //u8 + RATE_DOWN_RTY_RATIO= 9, //u8 + ALL_PARA = 0xff + + */ + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("odm_RA_ParaAdjust_init \n")); + + pRA_Table->is_ra_dbg_init = TRUE; + for (i = 0; i < 3; i++) { + pRA_Table->RA_Para_feedback_req = 1; + pRA_Table->para_idx = ra_para_pool_u8[i]; + odm_RA_ParaAdjust_Send_H2C(pDM_Odm); + } + + if (pDM_Odm->SupportICType == ODM_RTL8192E) + pRA_Table->rate_length = ODM_RATEMCS15; + else if ((pDM_Odm->SupportICType == ODM_RTL8723B) || (pDM_Odm->SupportICType == ODM_RTL8188E)) + pRA_Table->rate_length = ODM_RATEMCS7; + else if ((pDM_Odm->SupportICType == ODM_RTL8821) || (pDM_Odm->SupportICType == ODM_RTL8881A)) + pRA_Table->rate_length = ODM_RATEVHTSS1MCS9; + else if (pDM_Odm->SupportICType == ODM_RTL8812) + pRA_Table->rate_length = ODM_RATEVHTSS2MCS9; + else if (pDM_Odm->SupportICType == ODM_RTL8814A) + pRA_Table->rate_length = ODM_RATEVHTSS3MCS9; + else + pRA_Table->rate_length = ODM_RATEVHTSS4MCS9; + +} + +#else + +VOID +ODM_C2HRaParaReportHandler( + IN PVOID pDM_VOID, + IN pu1Byte CmdBuf, + IN u1Byte CmdLen +) +{ +} + +VOID +odm_RA_debug( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value +) +{ +} + +VOID +odm_RA_ParaAdjust_init( + IN PVOID pDM_VOID +) + +{ +} + +#endif //#if (defined(CONFIG_RA_DBG_CMD)) + +VOID +phydm_ra_dynamic_retry_count( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + PSTA_INFO_T pEntry; + u1Byte i, retry_offset; + u4Byte ma_rx_tp; + /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("pDM_Odm->pre_b_noisy = %d\n", pDM_Odm->pre_b_noisy ));*/ + if (pDM_Odm->pre_b_noisy != pDM_Odm->NoisyDecision) { + + if (pDM_Odm->NoisyDecision) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("->Noisy Env. RA fallback value\n")); + ODM_SetMACReg(pDM_Odm, 0x430, bMaskDWord, 0x0); + ODM_SetMACReg(pDM_Odm, 0x434, bMaskDWord, 0x04030201); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("->Clean Env. RA fallback value\n")); + ODM_SetMACReg(pDM_Odm, 0x430, bMaskDWord, 0x02010000); + ODM_SetMACReg(pDM_Odm, 0x434, bMaskDWord, 0x06050403); + } + pDM_Odm->pre_b_noisy = pDM_Odm->NoisyDecision; + } +} + +#if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) + +VOID +phydm_retry_limit_table_bound( + IN PVOID pDM_VOID, + IN u1Byte *retry_limit, + IN u1Byte offset +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + + if (*retry_limit > offset) { + + *retry_limit -= offset; + + if (*retry_limit < pRA_Table->retrylimit_low) + *retry_limit = pRA_Table->retrylimit_low; + else if (*retry_limit > pRA_Table->retrylimit_high) + *retry_limit = pRA_Table->retrylimit_high; + } else + *retry_limit = pRA_Table->retrylimit_low; +} + +VOID +phydm_reset_retry_limit_table( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + u1Byte i; + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) /*support all IC platform*/ + + #else + #if ((RTL8192E_SUPPORT == 1) || (RTL8723B_SUPPORT == 1) || (RTL8188E_SUPPORT == 1)) + u1Byte per_rate_retrylimit_table_20M[ODM_RATEMCS15+1] = { + 1, 1, 2, 4, /*CCK*/ + 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/ + 2, 4, 6, 8, 12, 18, 20, 22, /*20M HT-1SS*/ + 2, 4, 6, 8, 12, 18, 20, 22 /*20M HT-2SS*/ + }; + u1Byte per_rate_retrylimit_table_40M[ODM_RATEMCS15+1] = { + 1, 1, 2, 4, /*CCK*/ + 2, 2, 4, 6, 8, 12, 16, 18, /*OFDM*/ + 4, 8, 12, 16, 24, 32, 32, 32, /*40M HT-1SS*/ + 4, 8, 12, 16, 24, 32, 32, 32 /*40M HT-2SS*/ + }; + + #elif (RTL8821A_SUPPORT == 1) || (RTL8881A_SUPPORT == 1) + + #elif (RTL8812A_SUPPORT == 1) + + #elif(RTL8814A_SUPPORT == 1) + + #else + + #endif + #endif + + memcpy(&(pRA_Table->per_rate_retrylimit_20M[0]), &(per_rate_retrylimit_table_20M[0]), ODM_NUM_RATE_IDX); + memcpy(&(pRA_Table->per_rate_retrylimit_40M[0]), &(per_rate_retrylimit_table_40M[0]), ODM_NUM_RATE_IDX); + + for (i = 0; i < ODM_NUM_RATE_IDX; i++) { + phydm_retry_limit_table_bound(pDM_Odm, &(pRA_Table->per_rate_retrylimit_20M[i]), 0); + phydm_retry_limit_table_bound(pDM_Odm, &(pRA_Table->per_rate_retrylimit_40M[i]), 0); + } +} + +VOID +phydm_ra_dynamic_retry_limit( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + PSTA_INFO_T pEntry; + u1Byte i, retry_offset; + u4Byte ma_rx_tp; + + + if (pDM_Odm->pre_number_active_client == pDM_Odm->number_active_client) { + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, (" pre_number_active_client == number_active_client\n")); + return; + + } else { + if (pDM_Odm->number_active_client == 1) { + phydm_reset_retry_limit_table(pDM_Odm); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("one client only->reset to default value\n")); + } else { + + retry_offset = pDM_Odm->number_active_client * pRA_Table->retry_descend_num; + + for (i = 0; i < ODM_NUM_RATE_IDX; i++) { + + phydm_retry_limit_table_bound(pDM_Odm, &(pRA_Table->per_rate_retrylimit_20M[i]), retry_offset); + phydm_retry_limit_table_bound(pDM_Odm, &(pRA_Table->per_rate_retrylimit_40M[i]), retry_offset); + } + } + } +} + +VOID +phydm_ra_dynamic_retry_limit_init( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + + pRA_Table->retry_descend_num = RA_RETRY_DESCEND_NUM; + pRA_Table->retrylimit_low = RA_RETRY_LIMIT_LOW; + pRA_Table->retrylimit_high = RA_RETRY_LIMIT_HIGH; + + phydm_reset_retry_limit_table(pDM_Odm); + +} +#else +VOID +phydm_ra_dynamic_retry_limit( + IN PVOID pDM_VOID +) +{ +} +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +VOID +phydm_ra_dynamic_rate_id_on_assoc( + IN PVOID pDM_VOID, + IN u1Byte wireless_mode, + IN u1Byte init_rate_id +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[ON ASSOC] rf_mode = ((0x%x)), wireless_mode = ((0x%x)), init_rate_id = ((0x%x))\n", pDM_Odm->RFType, wireless_mode, init_rate_id)); + + if ((pDM_Odm->RFType == ODM_2T2R) | (pDM_Odm->RFType == ODM_2T2R_GREEN) | (pDM_Odm->RFType == ODM_2T3R) | (pDM_Odm->RFType == ODM_2T4R)) { + + if ((pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8192E)) && + (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G)) + ){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[ON ASSOC] set N-2SS ARFR5 table\n")); + ODM_SetMACReg(pDM_Odm, 0x4a4, bMaskDWord, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/ + ODM_SetMACReg(pDM_Odm, 0x4a8, bMaskDWord, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/ + } else if ((pDM_Odm->SupportICType & (ODM_RTL8812)) && + (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY)) + ){ + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[ON ASSOC] set AC-2SS ARFR0 table\n")); + ODM_SetMACReg(pDM_Odm, 0x444, bMaskDWord, 0x0fff); /*AC-2SS, ARFR0, rate_id = 0x9*/ + ODM_SetMACReg(pDM_Odm, 0x448, bMaskDWord, 0xff01f000); /*AC-2SS, ARFR0, rate_id = 0x9*/ + } + } + +} + +VOID +phydm_ra_dynamic_rate_id_init( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8192E)) { + + ODM_SetMACReg(pDM_Odm, 0x4a4, bMaskDWord, 0xfc1ffff); /*N-2SS, ARFR5, rate_id = 0xe*/ + ODM_SetMACReg(pDM_Odm, 0x4a8, bMaskDWord, 0x0); /*N-2SS, ARFR5, rate_id = 0xe*/ + + ODM_SetMACReg(pDM_Odm, 0x444, bMaskDWord, 0x0fff); /*AC-2SS, ARFR0, rate_id = 0x9*/ + ODM_SetMACReg(pDM_Odm, 0x448, bMaskDWord, 0xff01f000); /*AC-2SS, ARFR0, rate_id = 0x9*/ + } +} + +VOID +phydm_update_rate_id( + IN PVOID pDM_VOID, + IN u1Byte rate, + IN u1Byte platform_macid +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + u1Byte current_tx_ss; + u1Byte rate_idx = rate & 0x7f; /*remove bit7 SGI*/ + u1Byte wireless_mode; + u1Byte phydm_macid; + PSTA_INFO_T pEntry; + + if (rate_idx >= ODM_RATEVHTSS2MCS0) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate[%d]: (( VHT2SS-MCS%d ))\n", platform_macid, (rate_idx-ODM_RATEVHTSS2MCS0))); + /*dummy for SD4 check patch*/ + } else if (rate_idx >= ODM_RATEVHTSS1MCS0) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate[%d]: (( VHT1SS-MCS%d ))\n", platform_macid, (rate_idx-ODM_RATEVHTSS1MCS0))); + /*dummy for SD4 check patch*/ + } else if (rate_idx >= ODM_RATEMCS0) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate[%d]: (( HT-MCS%d ))\n", platform_macid, (rate_idx-ODM_RATEMCS0))); + /*dummy for SD4 check patch*/ + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Rate[%d]: (( HT-MCS%d ))\n", platform_macid, rate_idx)); + /*dummy for SD4 check patch*/ + } + + phydm_macid = pDM_Odm->platform2phydm_macid_table[platform_macid]; + pEntry = pDM_Odm->pODM_StaInfo[phydm_macid]; + + if (IS_STA_VALID(pEntry)) { + wireless_mode = pEntry->WirelessMode; + + if ((pDM_Odm->RFType == ODM_2T2R) | (pDM_Odm->RFType == ODM_2T2R_GREEN) | (pDM_Odm->RFType == ODM_2T3R) | (pDM_Odm->RFType == ODM_2T4R)) { + + pEntry->ratr_idx = pEntry->ratr_idx_init; + if (wireless_mode & (ODM_WM_N24G | ODM_WM_N5G)) { /*N mode*/ + if (rate_idx >= ODM_RATEMCS8 && rate_idx <= ODM_RATEMCS15) { /*2SS mode*/ + + pEntry->ratr_idx = ARFR_5_RATE_ID; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("ARFR_5\n")); + } + } else if (wireless_mode & (ODM_WM_AC_5G | ODM_WM_AC_24G | ODM_WM_AC_ONLY)) {/*AC mode*/ + if (rate_idx >= ODM_RATEVHTSS2MCS0 && rate_idx <= ODM_RATEVHTSS2MCS9) {/*2SS mode*/ + + pEntry->ratr_idx = ARFR_0_RATE_ID; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("ARFR_0\n")); + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("UPdate_RateID[%d]: (( 0x%x ))\n", platform_macid, pEntry->ratr_idx)); + } + } + +} +#endif + +VOID +phydm_c2h_ra_report_handler( + IN PVOID pDM_VOID, + IN pu1Byte CmdBuf, + IN u1Byte CmdLen +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + u1Byte legacy_table[12] = {1,2,5,11,6,9,12,18,24,36,48,54}; + u1Byte macid = CmdBuf[1]; + + u1Byte rate = CmdBuf[0]; + u1Byte rate_idx = rate & 0x7f; /*remove bit7 SGI*/ + u1Byte vht_en=(rate_idx >= ODM_RATEVHTSS1MCS0)? 1 :0; + u1Byte b_sgi = (rate & 0x80)>>7; + + u1Byte pre_rate = pRA_Table->link_tx_rate[macid]; + u1Byte pre_rate_idx = pre_rate & 0x7f; /*remove bit7 SGI*/ + u1Byte pre_vht_en=(pre_rate_idx >= ODM_RATEVHTSS1MCS0)? 1 :0; + u1Byte pre_b_sgi = (pre_rate & 0x80)>>7; + + #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + + GET_HAL_DATA(Adapter)->CurrentRARate = HwRateToMRate(rate_idx); + #endif + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + ODM_UpdateInitRate(pDM_Odm, rate_idx); + #endif + + /*ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD,("RA: rate_idx=0x%x , sgi = %d\n", rate_idx, b_sgi));*/ + /*if (pDM_Odm->SupportICType & (ODM_RTL8703B))*/ + { + if (CmdLen >= 4) { + if (CmdBuf[3] == 0) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("Init-Rate Update\n")); + /**/ + } else if (CmdBuf[3] == 0xff) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("FW Level: Fix rate\n")); + /**/ + } else if (CmdBuf[3] == 1) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("Try Success\n")); + /**/ + } else if (CmdBuf[3] == 2) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("Try Fail & Try Again\n")); + /**/ + } else if (CmdBuf[3] == 3) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("Rate Back\n")); + /**/ + } else if (CmdBuf[3] == 4) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("start rate by RSSI\n")); + /**/ + } else if (CmdBuf[3] == 5) { + ODM_RT_TRACE(pDM_Odm, ODM_FW_DEBUG_TRACE, ODM_DBG_LOUD, ("Try rate\n")); + /**/ + } + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("Tx Rate Update, MACID[%d] ( %s%s%s%s%d%s%s ) -> ( %s%s%s%s%d%s%s)\n", + macid, + ((pre_rate_idx >= ODM_RATEVHTSS1MCS0) && (pre_rate_idx <= ODM_RATEVHTSS1MCS9)) ? "VHT 1ss " : "", + ((pre_rate_idx >= ODM_RATEVHTSS2MCS0) && (pre_rate_idx <= ODM_RATEVHTSS2MCS9)) ? "VHT 2ss " : "", + ((pre_rate_idx >= ODM_RATEVHTSS3MCS0) && (pre_rate_idx <= ODM_RATEVHTSS3MCS9)) ? "VHT 3ss " : "", + (pre_rate_idx >= ODM_RATEMCS0) ? "MCS " : "", + (pre_vht_en) ? ((pre_rate_idx - ODM_RATEVHTSS1MCS0)%10) : ((pre_rate_idx >= ODM_RATEMCS0)? (pre_rate_idx - ODM_RATEMCS0) : ((pre_rate_idx <= ODM_RATE54M)?legacy_table[pre_rate_idx]:0)), + (pre_b_sgi) ? "-S" : " ", + (pre_rate_idx >= ODM_RATEMCS0) ? "" : "M", + ((rate_idx >= ODM_RATEVHTSS1MCS0) && (rate_idx <= ODM_RATEVHTSS1MCS9)) ? "VHT 1ss " : "", + ((rate_idx >= ODM_RATEVHTSS2MCS0) && (rate_idx <= ODM_RATEVHTSS2MCS9)) ? "VHT 2ss " : "", + ((rate_idx >= ODM_RATEVHTSS3MCS0) && (rate_idx <= ODM_RATEVHTSS3MCS9)) ? "VHT 3ss " : "", + (rate_idx >= ODM_RATEMCS0) ? "MCS " : "", + (vht_en) ? ((rate_idx - ODM_RATEVHTSS1MCS0)%10) : ((rate_idx >= ODM_RATEMCS0)? (rate_idx - ODM_RATEMCS0) : ((rate_idx <= ODM_RATE54M)?legacy_table[rate_idx]:0)), + (b_sgi) ? "-S" : " ", + (rate_idx >= ODM_RATEMCS0) ? "" : "M" )); + + pRA_Table->link_tx_rate[macid] = rate; + + + #if (DM_ODM_SUPPORT_TYPE == ODM_AP) + if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8192E)) + phydm_update_rate_id(pDM_Odm, rate, macid); + #endif + +} + +VOID +odm_RSSIMonitorInit( + IN PVOID pDM_VOID +) +{ +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + pRA_Table->firstconnect = FALSE; + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + pRA_Table->PT_collision_pre = TRUE; //used in ODM_DynamicARFBSelect(WIN only) +#endif +#endif +} + +VOID +ODM_RAPostActionOnAssoc( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + pDM_Odm->H2C_RARpt_connect = 1; + odm_RSSIMonitorCheck(pDM_Odm); + pDM_Odm->H2C_RARpt_connect = 0; +} + +VOID +odm_RSSIMonitorCheck( + IN PVOID pDM_VOID +) +{ + // + // For AP/ADSL use prtl8192cd_priv + // For CE/NIC use PADAPTER + // + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR)) + return; + + // + // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate + // at the same time. In the stage2/3, we need to prive universal interface and merge all + // HW dynamic mechanism. + // + switch (pDM_Odm->SupportPlatform) { + case ODM_WIN: + odm_RSSIMonitorCheckMP(pDM_Odm); + break; + + case ODM_CE: + odm_RSSIMonitorCheckCE(pDM_Odm); + break; + + case ODM_AP: + odm_RSSIMonitorCheckAP(pDM_Odm); + break; + + case ODM_ADSL: + //odm_DIGAP(pDM_Odm); + break; + } + +} // odm_RSSIMonitorCheck + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +s4Byte +phydm_FindMinimumRSSI( +IN PDM_ODM_T pDM_Odm, +IN PADAPTER pAdapter, +IN OUT BOOLEAN *pbLink_temp + + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMGNT_INFO pMgntInfo = &(pAdapter->MgntInfo); + BOOLEAN act_as_ap = ACTING_AS_AP(pAdapter); + + /*DbgPrint("bMediaConnect = %d, ACTING_AS_AP = %d , EntryMinUndecoratedSmoothedPWDB = %d\n", + pMgntInfo->bMediaConnect,act_as_ap,pHalData->EntryMinUndecoratedSmoothedPWDB);*/ + + + /* 1.Determine the minimum RSSI */ + if ((!pMgntInfo->bMediaConnect) || + (act_as_ap && (pHalData->EntryMinUndecoratedSmoothedPWDB == 0))) {/* We should check AP mode and Entry info.into consideration, revised by Roger, 2013.10.18*/ + + pHalData->MinUndecoratedPWDBForDM = 0; + *pbLink_temp = FALSE; + + } else + *pbLink_temp = TRUE; + + + if (pMgntInfo->bMediaConnect) { /* Default port*/ + + if (act_as_ap || pMgntInfo->mIbss) { + pHalData->MinUndecoratedPWDBForDM = pHalData->EntryMinUndecoratedSmoothedPWDB; + /**/ + } else { + pHalData->MinUndecoratedPWDBForDM = pHalData->UndecoratedSmoothedPWDB; + /**/ + } + } else { /* associated entry pwdb*/ + pHalData->MinUndecoratedPWDBForDM = pHalData->EntryMinUndecoratedSmoothedPWDB; + /**/ + } + + return pHalData->MinUndecoratedPWDBForDM; +} + +#endif + +VOID +odm_RSSIMonitorCheckMP( + IN PVOID pDM_VOID +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte H2C_Parameter[4] = {0}; + u4Byte i; + BOOLEAN bExtRAInfo = FALSE; + u1Byte cmdlen = 3; + u1Byte TxBF_EN = 0, stbc_en = 0; + + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PRT_WLAN_STA pEntry = NULL; + s4Byte tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff; + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + PMGNT_INFO pDefaultMgntInfo = &Adapter->MgntInfo; + u8Byte curTxOkCnt = 0, curRxOkCnt = 0; + //BOOLEAN FirstConnect = 0; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + +#if (BEAMFORMING_SUPPORT == 1) + BEAMFORMING_CAP Beamform_cap = BEAMFORMING_CAP_NONE; +#endif + + PADAPTER pLoopAdapter = GetDefaultAdapter(Adapter); + + if (pDM_Odm->SupportICType & EXT_RA_INFO_SUPPORT_IC) { + bExtRAInfo = TRUE; + cmdlen = 4; + } + + //FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE); + //pRA_Table->firstconnect = pHalData->bLinked; + + + /* + if(pDM_Odm->SupportICType == ODM_RTL8188E && (pDefaultMgntInfo->CustomerID==RT_CID_819x_HP)) + { + if(curRxOkCnt >(curTxOkCnt*6)) + PlatformEFIOWrite4Byte(Adapter, REG_ARFR0, 0x8f015); + else + PlatformEFIOWrite4Byte(Adapter, REG_ARFR0, 0xff015); + } + + + if(pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8821 || + pDM_Odm->SupportICType == ODM_RTL8814A|| pDM_Odm->SupportICType == ODM_RTL8822B) + { + if(curRxOkCnt >(curTxOkCnt*6)) + H2C_Parameter[3]|=RAINFO_BE_RX_STATE; + } + */ + + while (pLoopAdapter) { + + if (pLoopAdapter != NULL) { + pMgntInfo = &pLoopAdapter->MgntInfo; + curTxOkCnt = pLoopAdapter->TxStats.NumTxBytesUnicast - pMgntInfo->lastTxOkCnt; + curRxOkCnt = pLoopAdapter->RxStats.NumRxBytesUnicast - pMgntInfo->lastRxOkCnt; + pMgntInfo->lastTxOkCnt = curTxOkCnt; + pMgntInfo->lastRxOkCnt = curRxOkCnt; + } + + for (i = 0; i < ASSOCIATE_ENTRY_NUM; i++) { + + if (IsAPModeExist(pLoopAdapter)) { + if (GetFirstExtAdapter(pLoopAdapter) != NULL && + GetFirstExtAdapter(pLoopAdapter) == pLoopAdapter) + pEntry = AsocEntry_EnumStation(pLoopAdapter, i); + else if (GetFirstGOPort(pLoopAdapter) != NULL && + IsFirstGoAdapter(pLoopAdapter)) + pEntry = AsocEntry_EnumStation(pLoopAdapter, i); + } else { + if (GetDefaultAdapter(pLoopAdapter) == pLoopAdapter) + pEntry = AsocEntry_EnumStation(pLoopAdapter, i); + } + + if (pEntry != NULL) { + if (pEntry->bAssociated) { + + RT_DISP_ADDR(FDM, DM_PWDB, ("pEntry->MacAddr ="), pEntry->MacAddr); + RT_DISP(FDM, DM_PWDB, ("pEntry->rssi = 0x%x(%d)\n", + pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntry->rssi_stat.UndecoratedSmoothedPWDB)); + + //2 BF_en +#if (BEAMFORMING_SUPPORT) + Beamform_cap = phydm_Beamforming_GetEntryBeamCapByMacId(pDM_Odm, pEntry->AssociatedMacId); + if (Beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) + TxBF_EN = 1; +#endif + //2 STBC_en + if ((IS_WIRELESS_MODE_AC(Adapter) && TEST_FLAG(pEntry->VHTInfo.STBC, STBC_VHT_ENABLE_TX)) || + TEST_FLAG(pEntry->HTInfo.STBC, STBC_HT_ENABLE_TX)) + stbc_en = 1; + + if (pEntry->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB) + tmpEntryMinPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; + if (pEntry->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB) + tmpEntryMaxPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; + + if (bExtRAInfo) { + if (curRxOkCnt > (curTxOkCnt * 6)) + H2C_Parameter[3] |= RAINFO_BE_RX_STATE; + + if (TxBF_EN) + H2C_Parameter[3] |= RAINFO_BF_STATE; + else { + if (stbc_en) + H2C_Parameter[3] |= RAINFO_STBC_STATE; + } + + if ( pDM_Odm->NoisyDecision ) + { + H2C_Parameter[3] |= RAINFO_NOISY_STATE; // BIT2 + } + else + H2C_Parameter[3] &= (~RAINFO_NOISY_STATE); + + if (pDM_Odm->H2C_RARpt_connect) + H2C_Parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; + } + + H2C_Parameter[2] = (u1Byte)(pEntry->rssi_stat.UndecoratedSmoothedPWDB & 0xFF); + //H2C_Parameter[1] = 0x20; // fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1 + H2C_Parameter[0] = (pEntry->AssociatedMacId); + + ODM_FillH2CCmd(pDM_Odm, ODM_H2C_RSSI_REPORT, cmdlen, H2C_Parameter); + } + } else + break; + } + + pLoopAdapter = GetNextExtAdapter(pLoopAdapter); + } + + if (tmpEntryMaxPWDB != 0) { // If associated entry is found + pHalData->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB; + RT_DISP(FDM, DM_PWDB, ("EntryMaxPWDB = 0x%x(%d)\n", tmpEntryMaxPWDB, tmpEntryMaxPWDB)); + } else + pHalData->EntryMaxUndecoratedSmoothedPWDB = 0; + + if (tmpEntryMinPWDB != 0xff) { // If associated entry is found + pHalData->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB; + RT_DISP(FDM, DM_PWDB, ("EntryMinPWDB = 0x%x(%d)\n", tmpEntryMinPWDB, tmpEntryMinPWDB)); + + } else + pHalData->EntryMinUndecoratedSmoothedPWDB = 0; + + // Indicate Rx signal strength to FW. + if (pHalData->bUseRAMask) { + PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pDefaultMgntInfo); + PRT_VERY_HIGH_THROUGHPUT pVHTInfo = GET_VHT_INFO(pDefaultMgntInfo); + + //2 BF_en +#if (BEAMFORMING_SUPPORT == 1) + Beamform_cap = phydm_Beamforming_GetEntryBeamCapByMacId(pDM_Odm, pDefaultMgntInfo->mMacId); + + if (Beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) + TxBF_EN = 1; +#endif + + //2 STBC_en + if ((IS_WIRELESS_MODE_AC(Adapter) && TEST_FLAG(pVHTInfo->VhtCurStbc, STBC_VHT_ENABLE_TX)) || + TEST_FLAG(pHTInfo->HtCurStbc, STBC_HT_ENABLE_TX)) + stbc_en = 1; + + if (bExtRAInfo) { + if (TxBF_EN) + H2C_Parameter[3] |= RAINFO_BF_STATE; + else { + if (stbc_en) + H2C_Parameter[3] |= RAINFO_STBC_STATE; + } + + if (pDM_Odm->H2C_RARpt_connect) + H2C_Parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; + + if ( pDM_Odm->NoisyDecision==1 ) + { + H2C_Parameter[3] |= RAINFO_NOISY_STATE; // BIT2 + ODM_RT_TRACE(pDM_Odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD, ("[RSSIMonitorCheckMP] Send H2C to FW\n")); + } + else + H2C_Parameter[3] &= (~RAINFO_NOISY_STATE); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_NOISY_DETECT, ODM_DBG_LOUD, ("[RSSIMonitorCheckMP] H2C_Parameter=%x\n", H2C_Parameter[3])); + } + + H2C_Parameter[2] = (u1Byte)(pHalData->UndecoratedSmoothedPWDB & 0xFF); + //H2C_Parameter[1] = 0x20; // fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1 + H2C_Parameter[0] = 0; // fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1 + + ODM_FillH2CCmd(pDM_Odm, ODM_H2C_RSSI_REPORT, cmdlen, H2C_Parameter); + + // BT 3.0 HS mode Rssi + if (pDM_Odm->bBtHsOperation) { + H2C_Parameter[2] = pDM_Odm->btHsRssi; + //H2C_Parameter[1] = 0x0; + H2C_Parameter[0] = 2; + + ODM_FillH2CCmd(pDM_Odm, ODM_H2C_RSSI_REPORT, cmdlen, H2C_Parameter); + } + } else + PlatformEFIOWrite1Byte(Adapter, 0x4fe, (u1Byte)pHalData->UndecoratedSmoothedPWDB); + + if ((pDM_Odm->SupportICType == ODM_RTL8812) || (pDM_Odm->SupportICType == ODM_RTL8192E)) + odm_RSSIDumpToRegister(pDM_Odm); + + + { + PADAPTER pLoopAdapter = GetDefaultAdapter(Adapter); + BOOLEAN default_pointer_value, *pbLink_temp = &default_pointer_value; + s4Byte GlobalRSSI_min = 0xFF, LocalRSSI_Min; + BOOLEAN bLink = FALSE; + + while (pLoopAdapter) { + LocalRSSI_Min = phydm_FindMinimumRSSI(pDM_Odm, pLoopAdapter, pbLink_temp); + //DbgPrint("pHalData->bLinked=%d, LocalRSSI_Min=%d\n", pHalData->bLinked, LocalRSSI_Min); + if ((LocalRSSI_Min < GlobalRSSI_min) && (LocalRSSI_Min != 0)) + GlobalRSSI_min = LocalRSSI_Min; + + if (*pbLink_temp) + bLink = TRUE; + + pLoopAdapter = GetNextExtAdapter(pLoopAdapter); + } + + pHalData->bLinked = bLink; + ODM_CmnInfoUpdate(&pHalData->DM_OutSrc , ODM_CMNINFO_LINK, (u8Byte)bLink); + + if (bLink) + ODM_CmnInfoUpdate(&pHalData->DM_OutSrc, ODM_CMNINFO_RSSI_MIN, (u8Byte)GlobalRSSI_min); + else + ODM_CmnInfoUpdate(&pHalData->DM_OutSrc, ODM_CMNINFO_RSSI_MIN, 0); + + } + +#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +/*H2C_RSSI_REPORT*/ +s8 phydm_rssi_report(PDM_ODM_T pDM_Odm, u8 mac_id) +{ + PADAPTER Adapter = pDM_Odm->Adapter; + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u8 H2C_Parameter[4] = {0}; + u8 UL_DL_STATE = 0, STBC_TX = 0, TxBF_EN = 0; + u8 cmdlen = 4, first_connect = _FALSE; + u64 curTxOkCnt = 0, curRxOkCnt = 0; + PSTA_INFO_T pEntry = pDM_Odm->pODM_StaInfo[mac_id]; + + if (!IS_STA_VALID(pEntry)) + return _FAIL; + + if (mac_id != pEntry->mac_id) { + DBG_871X("%s mac_id:%u:%u invalid\n", __func__, mac_id, pEntry->mac_id); + rtw_warn_on(1); + return _FAIL; + } + + if (IS_MCAST(pEntry->hwaddr)) /*if(psta->mac_id ==1)*/ + return _FAIL; + + if (pEntry->rssi_stat.UndecoratedSmoothedPWDB == (-1)) { + DBG_871X("%s mac_id:%u, mac:"MAC_FMT", rssi == -1\n", __func__, pEntry->mac_id, MAC_ARG(pEntry->hwaddr)); + return _FAIL; + } + + curTxOkCnt = pdvobjpriv->traffic_stat.cur_tx_bytes; + curRxOkCnt = pdvobjpriv->traffic_stat.cur_rx_bytes; + if (curRxOkCnt > (curTxOkCnt * 6)) + UL_DL_STATE = 1; + else + UL_DL_STATE = 0; + + #ifdef CONFIG_BEAMFORMING + { + #if (BEAMFORMING_SUPPORT == 1) + BEAMFORMING_CAP Beamform_cap = phydm_Beamforming_GetEntryBeamCapByMacId(pDM_Odm, pEntry->mac_id); + #else/*for drv beamforming*/ + BEAMFORMING_CAP Beamform_cap = beamforming_get_entry_beam_cap_by_mac_id(&Adapter->mlmepriv, pEntry->mac_id); + #endif + + if (Beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMER_CAP_VHT_SU)) + TxBF_EN = 1; + else + TxBF_EN = 0; + } + #endif /*#ifdef CONFIG_BEAMFORMING*/ + + if (TxBF_EN) + STBC_TX = 0; + else { + #ifdef CONFIG_80211AC_VHT + if (IsSupportedVHT(pEntry->wireless_mode)) + STBC_TX = TEST_FLAG(pEntry->vhtpriv.stbc_cap, STBC_VHT_ENABLE_TX); + else + #endif + STBC_TX = TEST_FLAG(pEntry->htpriv.stbc_cap, STBC_HT_ENABLE_TX); + } + + H2C_Parameter[0] = (u8)(pEntry->mac_id & 0xFF); + H2C_Parameter[2] = pEntry->rssi_stat.UndecoratedSmoothedPWDB & 0x7F; + + if (UL_DL_STATE) + H2C_Parameter[3] |= RAINFO_BE_RX_STATE; + + if (TxBF_EN) + H2C_Parameter[3] |= RAINFO_BF_STATE; + if (STBC_TX) + H2C_Parameter[3] |= RAINFO_STBC_STATE; + if (pDM_Odm->NoisyDecision) + H2C_Parameter[3] |= RAINFO_NOISY_STATE; + + if (pEntry->ra_rpt_linked == _FALSE) { + H2C_Parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; + pEntry->ra_rpt_linked = _TRUE; + first_connect = _TRUE; + } + + #if 1 + if (first_connect) { + DBG_871X("%s mac_id:%u, mac:"MAC_FMT", rssi:%d\n", __func__, + pEntry->mac_id, MAC_ARG(pEntry->hwaddr), pEntry->rssi_stat.UndecoratedSmoothedPWDB); + + DBG_871X("%s RAINFO - TP:%s, TxBF:%s, STBC:%s, Noisy:%s, Firstcont:%s\n", __func__, + (UL_DL_STATE) ? "DL" : "UL", (TxBF_EN) ? "EN" : "DIS", (STBC_TX) ? "EN" : "DIS", + (pDM_Odm->NoisyDecision) ? "True" : "False", (first_connect) ? "True" : "False"); + } + #endif + + if (pHalData->fw_ractrl == _TRUE) { + #if (RTL8188E_SUPPORT == 1) + if (pDM_Odm->SupportICType == ODM_RTL8188E) + cmdlen = 3; + #endif + ODM_FillH2CCmd(pDM_Odm, ODM_H2C_RSSI_REPORT, cmdlen, H2C_Parameter); + } else { + #if ((RTL8188E_SUPPORT == 1) && (RATE_ADAPTIVE_SUPPORT == 1)) + if (pDM_Odm->SupportICType == ODM_RTL8188E) + ODM_RA_SetRSSI_8188E(pDM_Odm, (u8)(pEntry->mac_id & 0xFF), pEntry->rssi_stat.UndecoratedSmoothedPWDB & 0x7F); + #endif + } + return _SUCCESS; +} + +void phydm_ra_rssi_rpt_wk_hdl(PVOID pContext) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pContext; + int i; + u8 mac_id = 0xFF; + PSTA_INFO_T pEntry = NULL; + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + pEntry = pDM_Odm->pODM_StaInfo[i]; + if (IS_STA_VALID(pEntry)) { + if (IS_MCAST(pEntry->hwaddr)) /*if(psta->mac_id ==1)*/ + continue; + if (pEntry->ra_rpt_linked == _FALSE) { + mac_id = i; + break; + } + } + } + if (mac_id != 0xFF) + phydm_rssi_report(pDM_Odm, mac_id); +} +void phydm_ra_rssi_rpt_wk(PVOID pContext) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pContext; + + rtw_run_in_thread_cmd(pDM_Odm->Adapter, phydm_ra_rssi_rpt_wk_hdl, pDM_Odm); +} +#endif + +VOID +odm_RSSIMonitorCheckCE( + IN PVOID pDM_VOID +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PSTA_INFO_T pEntry; + int i; + int tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff; + u8 sta_cnt = 0; + + if (pDM_Odm->bLinked != _TRUE) + return; + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + pEntry = pDM_Odm->pODM_StaInfo[i]; + if (IS_STA_VALID(pEntry)) { + if (IS_MCAST(pEntry->hwaddr)) /*if(psta->mac_id ==1)*/ + continue; + + if (pEntry->rssi_stat.UndecoratedSmoothedPWDB == (-1)) + continue; + + if (pEntry->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB) + tmpEntryMinPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; + + if (pEntry->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB) + tmpEntryMaxPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB; + + if (phydm_rssi_report(pDM_Odm, i)) + sta_cnt++; + } + } + /*DBG_871X("%s==> sta_cnt(%d)\n", __func__, sta_cnt);*/ + + if (tmpEntryMaxPWDB != 0) // If associated entry is found + pHalData->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB; + else + pHalData->EntryMaxUndecoratedSmoothedPWDB = 0; + + if (tmpEntryMinPWDB != 0xff) // If associated entry is found + pHalData->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB; + else + pHalData->EntryMinUndecoratedSmoothedPWDB = 0; + + FindMinimumRSSI(Adapter);//get pdmpriv->MinUndecoratedPWDBForDM + + pDM_Odm->RSSI_Min = pHalData->MinUndecoratedPWDBForDM; + //ODM_CmnInfoUpdate(&pHalData->odmpriv ,ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM); +#endif//if (DM_ODM_SUPPORT_TYPE == ODM_CE) +} + + +VOID +odm_RSSIMonitorCheckAP( + IN PVOID pDM_VOID +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) +#if (RTL8812A_SUPPORT||RTL8881A_SUPPORT||RTL8192E_SUPPORT||RTL8814A_SUPPORT) + + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte H2C_Parameter[4] = {0}; + u4Byte i; + BOOLEAN bExtRAInfo = FALSE; + u1Byte cmdlen = 3 ; + u1Byte TxBF_EN = 0, stbc_en = 0; + + prtl8192cd_priv priv = pDM_Odm->priv; + PSTA_INFO_T pstat; + BOOLEAN act_bfer = FALSE; + +#ifdef BEAMFORMING_SUPPORT +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) + pBDC_T pDM_BdcTable = &pDM_Odm->DM_BdcTable; + pDM_BdcTable->num_Txbfee_Client = 0; + pDM_BdcTable->num_Txbfer_Client = 0; +#endif +#endif + + if (pDM_Odm->H2C_RARpt_connect) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[RA Init] First Connected\n")); + /**/ + } else if (priv->up_time % 2) + return; + + if (pDM_Odm->SupportICType & EXT_RA_INFO_SUPPORT_IC) { + bExtRAInfo = TRUE; + cmdlen = 4; + } + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + pstat = pDM_Odm->pODM_StaInfo[i]; + + if (IS_STA_VALID(pstat)) { + if (pstat->sta_in_firmware != 1) + continue; + + //2 BF_en +#ifdef BEAMFORMING_SUPPORT + BEAMFORMING_CAP Beamform_cap = Beamforming_GetEntryBeamCapByMacId(priv, pstat->aid); + + if (Beamform_cap == BEAMFORMER_CAP_HT_EXPLICIT || Beamform_cap == BEAMFORMER_CAP_VHT_SU || + Beamform_cap == (BEAMFORMER_CAP_HT_EXPLICIT | BEAMFORMEE_CAP_HT_EXPLICIT) || + Beamform_cap == (BEAMFORMER_CAP_VHT_SU | BEAMFORMEE_CAP_VHT_SU)) { + TxBF_EN = 1; + act_bfer = TRUE; + } + +#if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY)) /*BDC*/ + + if (act_bfer == TRUE) { + pDM_BdcTable->w_BFee_Client[i] = 1; //AP act as BFer + pDM_BdcTable->num_Txbfee_Client++; + } else { + pDM_BdcTable->w_BFee_Client[i] = 0; //AP act as BFer + } + + if ((Beamform_cap & BEAMFORMEE_CAP_HT_EXPLICIT) || (Beamform_cap & BEAMFORMEE_CAP_VHT_SU)) { + pDM_BdcTable->w_BFer_Client[i] = 1; //AP act as BFee + pDM_BdcTable->num_Txbfer_Client++; + } else { + pDM_BdcTable->w_BFer_Client[i] = 0; //AP act as BFer + } +#endif +#endif + + //2 STBC_en + if ((priv->pmib->dot11nConfigEntry.dot11nSTBC) && + ((pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_RX_STBC_CAP_)) +#ifdef RTK_AC_SUPPORT + || (pstat->vht_cap_buf.vht_cap_info & cpu_to_le32(_VHTCAP_RX_STBC_CAP_)) +#endif + )) + stbc_en = 1; + + //2 RAINFO + + if (bExtRAInfo) { + if ((pstat->rx_avarage) > ((pstat->tx_avarage) * 6)) + H2C_Parameter[3] |= RAINFO_BE_RX_STATE; + + if (TxBF_EN) + H2C_Parameter[3] |= RAINFO_BF_STATE; + else { + if (stbc_en) + H2C_Parameter[3] |= RAINFO_STBC_STATE; + } + + if ( pDM_Odm->NoisyDecision ) + { + H2C_Parameter[3] |= RAINFO_NOISY_STATE; // BIT2 + } + else + H2C_Parameter[3] &= (~RAINFO_NOISY_STATE); + + if (pDM_Odm->H2C_RARpt_connect) { + H2C_Parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RATE_ADAPTIVE, ODM_DBG_LOUD, ("[RA Init] set Init rate by RSSI\n")); + } + + /*ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[RAINFO] H2C_Para[3] = %x\n",H2C_Parameter[3]));*/ + } + + H2C_Parameter[2] = (u1Byte)(pstat->rssi & 0xFF); + H2C_Parameter[0] = REMAP_AID(pstat); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, + ("H2C_Parameter[3]=%d\n", H2C_Parameter[3])); + + //ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[RSSI] H2C_Para[2] = %x, \n",H2C_Parameter[2])); + //ODM_RT_TRACE(pDM_Odm,PHYDM_COMP_RA_DBG, ODM_DBG_LOUD, ("[MACID] H2C_Para[0] = %x, \n",H2C_Parameter[0])); + + ODM_FillH2CCmd(pDM_Odm, ODM_H2C_RSSI_REPORT, cmdlen, H2C_Parameter); + + } + } + +#endif +#endif + +} + + +VOID +odm_RateAdaptiveMaskInit( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PODM_RATE_ADAPTIVE pOdmRA = &pDM_Odm->RateAdaptive; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMGNT_INFO pMgntInfo = &pDM_Odm->Adapter->MgntInfo; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pDM_Odm->Adapter); + + pMgntInfo->Ratr_State = DM_RATR_STA_INIT; + + if (pMgntInfo->DM_Type == DM_Type_ByDriver) + pHalData->bUseRAMask = TRUE; + else + pHalData->bUseRAMask = FALSE; + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + pOdmRA->Type = DM_Type_ByDriver; + if (pOdmRA->Type == DM_Type_ByDriver) + pDM_Odm->bUseRAMask = _TRUE; + else + pDM_Odm->bUseRAMask = _FALSE; +#endif + + pOdmRA->RATRState = DM_RATR_STA_INIT; + +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + if (pDM_Odm->SupportICType == ODM_RTL8812) + pOdmRA->LdpcThres = 50; + else + pOdmRA->LdpcThres = 35; + + pOdmRA->RtsThres = 35; + +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + pOdmRA->LdpcThres = 35; + pOdmRA->bUseLdpc = FALSE; + +#else + pOdmRA->UltraLowRSSIThresh = 9; + +#endif + + pOdmRA->HighRSSIThresh = 50; +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && \ + ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + pOdmRA->LowRSSIThresh = 23; +#else + pOdmRA->LowRSSIThresh = 20; +#endif +} +/*----------------------------------------------------------------------------- + * Function: odm_RefreshRateAdaptiveMask() + * + * Overview: Update rate table mask according to rssi + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 05/27/2009 hpfan Create Version 0. + * + *---------------------------------------------------------------------------*/ +VOID +odm_RefreshRateAdaptiveMask( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("odm_RefreshRateAdaptiveMask()---------->\n")); + if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK)) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("odm_RefreshRateAdaptiveMask(): Return cos not supported\n")); + return; + } + // + // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate + // at the same time. In the stage2/3, we need to prive universal interface and merge all + // HW dynamic mechanism. + // + switch (pDM_Odm->SupportPlatform) { + case ODM_WIN: + odm_RefreshRateAdaptiveMaskMP(pDM_Odm); + break; + + case ODM_CE: + odm_RefreshRateAdaptiveMaskCE(pDM_Odm); + break; + + case ODM_AP: + case ODM_ADSL: + odm_RefreshRateAdaptiveMaskAPADSL(pDM_Odm); + break; + } + +} + +VOID +odm_RefreshRateAdaptiveMaskMP( + IN PVOID pDM_VOID +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER pAdapter = pDM_Odm->Adapter; + PADAPTER pTargetAdapter = NULL; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PMGNT_INFO pMgntInfo = GetDefaultMgntInfo(pAdapter); + + if (pAdapter->bDriverStopped) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n")); + return; + } + + if (!pHalData->bUseRAMask) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n")); + return; + } + + // if default port is connected, update RA table for default port (infrastructure mode only) + if (pMgntInfo->mAssoc && (!ACTING_AS_AP(pAdapter))) { + odm_RefreshLdpcRtsMP(pAdapter, pDM_Odm, pMgntInfo->mMacId, pMgntInfo->IOTPeer, pHalData->UndecoratedSmoothedPWDB); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_RefreshRateAdaptiveMask(): Infrasture Mode\n")); + if (ODM_RAStateCheck(pDM_Odm, pHalData->UndecoratedSmoothedPWDB, pMgntInfo->bSetTXPowerTrainingByOid, &pMgntInfo->Ratr_State)) { + ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr : "), pMgntInfo->Bssid); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pHalData->UndecoratedSmoothedPWDB, pMgntInfo->Ratr_State)); + pAdapter->HalFunc.UpdateHalRAMaskHandler(pAdapter, pMgntInfo->mMacId, NULL, pMgntInfo->Ratr_State); + } else if (pDM_Odm->bChangeState) { + ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr : "), pMgntInfo->Bssid); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Change Power Training State, bDisablePowerTraining = %d\n", pDM_Odm->bDisablePowerTraining)); + pAdapter->HalFunc.UpdateHalRAMaskHandler(pAdapter, pMgntInfo->mMacId, NULL, pMgntInfo->Ratr_State); + } + } + + // + // The following part configure AP/VWifi/IBSS rate adaptive mask. + // + + if (pMgntInfo->mIbss) // Target: AP/IBSS peer. + pTargetAdapter = GetDefaultAdapter(pAdapter); + else + pTargetAdapter = GetFirstAPAdapter(pAdapter); + + // if extension port (softap) is started, updaet RA table for more than one clients associate + if (pTargetAdapter != NULL) { + int i; + PRT_WLAN_STA pEntry; + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + pEntry = AsocEntry_EnumStation(pTargetAdapter, i); + if (NULL != pEntry) { + if (pEntry->bAssociated) { + odm_RefreshLdpcRtsMP(pAdapter, pDM_Odm, pEntry->AssociatedMacId, pEntry->IOTPeer, pEntry->rssi_stat.UndecoratedSmoothedPWDB); + + if (ODM_RAStateCheck(pDM_Odm, pEntry->rssi_stat.UndecoratedSmoothedPWDB, pMgntInfo->bSetTXPowerTrainingByOid, &pEntry->Ratr_State)) { + ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), pEntry->MacAddr); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntry->Ratr_State)); + pAdapter->HalFunc.UpdateHalRAMaskHandler(pTargetAdapter, pEntry->AssociatedMacId, pEntry, pEntry->Ratr_State); + } else if (pDM_Odm->bChangeState) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Change Power Training State, bDisablePowerTraining = %d\n", pDM_Odm->bDisablePowerTraining)); + pAdapter->HalFunc.UpdateHalRAMaskHandler(pAdapter, pMgntInfo->mMacId, NULL, pMgntInfo->Ratr_State); + } + } + } + } + } + + if (pMgntInfo->bSetTXPowerTrainingByOid) + pMgntInfo->bSetTXPowerTrainingByOid = FALSE; +#endif // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +} + + +VOID +odm_RefreshRateAdaptiveMaskCE( + IN PVOID pDM_VOID +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i; + PADAPTER pAdapter = pDM_Odm->Adapter; + PODM_RATE_ADAPTIVE pRA = &pDM_Odm->RateAdaptive; + + if (RTW_CANNOT_RUN(pAdapter)) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n")); + return; + } + + if (!pDM_Odm->bUseRAMask) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n")); + return; + } + + //printk("==> %s \n",__FUNCTION__); + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + PSTA_INFO_T pstat = pDM_Odm->pODM_StaInfo[i]; + if (IS_STA_VALID(pstat)) { + if (IS_MCAST(pstat->hwaddr)) //if(psta->mac_id ==1) + continue; + +#if((RTL8812A_SUPPORT==1)||(RTL8821A_SUPPORT==1)) + if ((pDM_Odm->SupportICType == ODM_RTL8812) || (pDM_Odm->SupportICType == ODM_RTL8821)) { + if (pstat->rssi_stat.UndecoratedSmoothedPWDB < pRA->LdpcThres) { + pRA->bUseLdpc = TRUE; + pRA->bLowerRtsRate = TRUE; + if ((pDM_Odm->SupportICType == ODM_RTL8821) && (pDM_Odm->CutVersion == ODM_CUT_A)) + Set_RA_LDPC_8812(pstat, TRUE); + //DbgPrint("RSSI=%d, bUseLdpc = TRUE\n", pHalData->UndecoratedSmoothedPWDB); + } else if (pstat->rssi_stat.UndecoratedSmoothedPWDB > (pRA->LdpcThres - 5)) { + pRA->bUseLdpc = FALSE; + pRA->bLowerRtsRate = FALSE; + if ((pDM_Odm->SupportICType == ODM_RTL8821) && (pDM_Odm->CutVersion == ODM_CUT_A)) + Set_RA_LDPC_8812(pstat, FALSE); + //DbgPrint("RSSI=%d, bUseLdpc = FALSE\n", pHalData->UndecoratedSmoothedPWDB); + } + } +#endif + + if (TRUE == ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, FALSE , &pstat->rssi_level)) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level)); + //printk("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level); + rtw_hal_update_ra_mask(pstat, pstat->rssi_level); + } else if (pDM_Odm->bChangeState) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Change Power Training State, bDisablePowerTraining = %d\n", pDM_Odm->bDisablePowerTraining)); + rtw_hal_update_ra_mask(pstat, pstat->rssi_level); + } + + } + } + +#endif +} + +VOID +odm_RefreshRateAdaptiveMaskAPADSL( + IN PVOID pDM_VOID +) +{ +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + struct rtl8192cd_priv *priv = pDM_Odm->priv; + struct aid_obj *aidarray; + u4Byte i; + PSTA_INFO_T pstat; + + if (priv->up_time % 2) + return; + + for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) { + pstat = pDM_Odm->pODM_StaInfo[i]; + + if (IS_STA_VALID(pstat)) { +#if defined(UNIVERSAL_REPEATER) || defined(MBSSID) + aidarray = container_of(pstat, struct aid_obj, station); + priv = aidarray->priv; +#endif + + if (!priv->pmib->dot11StationConfigEntry.autoRate) + continue; + + if (ODM_RAStateCheck(pDM_Odm, (s4Byte)pstat->rssi, FALSE, &pstat->rssi_level)) { + ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), pstat->hwaddr); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi, pstat->rssi_level)); + +#ifdef CONFIG_WLAN_HAL + if (IS_HAL_CHIP(priv)) { +#ifdef WDS +// if(!(pstat->state & WIFI_WDS))//if WDS donot setting +#endif + GET_HAL_INTERFACE(priv)->UpdateHalRAMaskHandler(priv, pstat, pstat->rssi_level); + } else +#endif +#ifdef CONFIG_RTL_8812_SUPPORT + if (GET_CHIP_VER(priv) == VERSION_8812E) + UpdateHalRAMask8812(priv, pstat, 3); + else +#endif +#ifdef CONFIG_RTL_88E_SUPPORT + if (GET_CHIP_VER(priv) == VERSION_8188E) { +#ifdef TXREPORT + add_RATid(priv, pstat); +#endif + } else +#endif + { +#if defined(CONFIG_RTL_92D_SUPPORT) || defined(CONFIG_RTL_92C_SUPPORT) + add_update_RATid(priv, pstat); +#endif + } + } + } + } +#endif +} + + +// Return Value: BOOLEAN +// - TRUE: RATRState is changed. +BOOLEAN +ODM_RAStateCheck( + IN PVOID pDM_VOID, + IN s4Byte RSSI, + IN BOOLEAN bForceUpdate, + OUT pu1Byte pRATRState +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PODM_RATE_ADAPTIVE pRA = &pDM_Odm->RateAdaptive; + const u1Byte GoUpGap = 5; + u1Byte HighRSSIThreshForRA = pRA->HighRSSIThresh; + u1Byte LowRSSIThreshForRA = pRA->LowRSSIThresh; + u1Byte RATRState; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI= (( %d )), Current_RSSI_level = (( %d ))\n", RSSI, *pRATRState)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("[Ori RA RSSI Thresh] High= (( %d )), Low = (( %d ))\n", HighRSSIThreshForRA, LowRSSIThreshForRA)); + // Threshold Adjustment: + // when RSSI state trends to go up one or two levels, make sure RSSI is high enough. + // Here GoUpGap is added to solve the boundary's level alternation issue. +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + u1Byte UltraLowRSSIThreshForRA = pRA->UltraLowRSSIThresh; + if (pDM_Odm->SupportICType == ODM_RTL8881A) + LowRSSIThreshForRA = 30; // for LDPC / BCC switch +#endif + + switch (*pRATRState) { + case DM_RATR_STA_INIT: + case DM_RATR_STA_HIGH: + break; + + case DM_RATR_STA_MIDDLE: + HighRSSIThreshForRA += GoUpGap; + break; + + case DM_RATR_STA_LOW: + HighRSSIThreshForRA += GoUpGap; + LowRSSIThreshForRA += GoUpGap; + break; + +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + case DM_RATR_STA_ULTRA_LOW: + HighRSSIThreshForRA += GoUpGap; + LowRSSIThreshForRA += GoUpGap; + UltraLowRSSIThreshForRA += GoUpGap; + break; +#endif + + default: + ODM_RT_ASSERT(pDM_Odm, FALSE, ("wrong rssi level setting %d !", *pRATRState)); + break; + } + + // Decide RATRState by RSSI. + if (RSSI > HighRSSIThreshForRA) + RATRState = DM_RATR_STA_HIGH; + else if (RSSI > LowRSSIThreshForRA) + RATRState = DM_RATR_STA_MIDDLE; + +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL)) + else if (RSSI > UltraLowRSSIThreshForRA) + RATRState = DM_RATR_STA_LOW; + else + RATRState = DM_RATR_STA_ULTRA_LOW; +#else + else + RATRState = DM_RATR_STA_LOW; +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("[Mod RA RSSI Thresh] High= (( %d )), Low = (( %d ))\n", HighRSSIThreshForRA, LowRSSIThreshForRA)); + /*printk("==>%s,RATRState:0x%02x ,RSSI:%d\n",__FUNCTION__,RATRState,RSSI);*/ + + if (*pRATRState != RATRState || bForceUpdate) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("[RSSI Level Update] %d -> %d\n", *pRATRState, RATRState)); + *pRATRState = RATRState; + return TRUE; + } + + return FALSE; +} + +VOID +odm_RefreshBasicRateMask( + IN PVOID pDM_VOID +) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + static u1Byte Stage = 0; + u1Byte CurStage = 0; + OCTET_STRING osRateSet; + PMGNT_INFO pMgntInfo = GetDefaultMgntInfo(Adapter); + u1Byte RateSet[5] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M, MGN_6M}; + + if (pDM_Odm->SupportICType != ODM_RTL8812 && pDM_Odm->SupportICType != ODM_RTL8821) + return; + + if (pDM_Odm->bLinked == FALSE) // unlink Default port information + CurStage = 0; + else if (pDM_Odm->RSSI_Min < 40) // link RSSI < 40% + CurStage = 1; + else if (pDM_Odm->RSSI_Min > 45) // link RSSI > 45% + CurStage = 3; + else + CurStage = 2; // link 25% <= RSSI <= 30% + + if (CurStage != Stage) { + if (CurStage == 1) { + FillOctetString(osRateSet, RateSet, 5); + FilterSupportRate(pMgntInfo->mBrates, &osRateSet, FALSE); + Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_BASIC_RATE, (pu1Byte)&osRateSet); + } else if (CurStage == 3 && (Stage == 1 || Stage == 2)) + Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_BASIC_RATE, (pu1Byte)(&pMgntInfo->mBrates)); + } + + Stage = CurStage; +#endif +} + + +VOID +phydm_ra_info_init( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + #if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) + phydm_ra_dynamic_retry_limit_init(pDM_Odm); + #endif + #if (DM_ODM_SUPPORT_TYPE == ODM_AP) + phydm_ra_dynamic_rate_id_init(pDM_Odm); + #endif + + /*phydm_fw_trace_en_h2c(pDM_Odm, 1, 0, 0);*/ +} + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) +u1Byte +odm_Find_RTS_Rate( + IN PVOID pDM_VOID, + IN u1Byte Tx_Rate, + IN BOOLEAN bErpProtect +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte RTS_Ini_Rate = ODM_RATE6M; + + if (bErpProtect) /* use CCK rate as RTS*/ + RTS_Ini_Rate = ODM_RATE1M; + else { + switch (Tx_Rate) { + case ODM_RATEVHTSS3MCS9: + case ODM_RATEVHTSS3MCS8: + case ODM_RATEVHTSS3MCS7: + case ODM_RATEVHTSS3MCS6: + case ODM_RATEVHTSS3MCS5: + case ODM_RATEVHTSS3MCS4: + case ODM_RATEVHTSS3MCS3: + case ODM_RATEVHTSS2MCS9: + case ODM_RATEVHTSS2MCS8: + case ODM_RATEVHTSS2MCS7: + case ODM_RATEVHTSS2MCS6: + case ODM_RATEVHTSS2MCS5: + case ODM_RATEVHTSS2MCS4: + case ODM_RATEVHTSS2MCS3: + case ODM_RATEVHTSS1MCS9: + case ODM_RATEVHTSS1MCS8: + case ODM_RATEVHTSS1MCS7: + case ODM_RATEVHTSS1MCS6: + case ODM_RATEVHTSS1MCS5: + case ODM_RATEVHTSS1MCS4: + case ODM_RATEVHTSS1MCS3: + case ODM_RATEMCS15: + case ODM_RATEMCS14: + case ODM_RATEMCS13: + case ODM_RATEMCS12: + case ODM_RATEMCS11: + case ODM_RATEMCS7: + case ODM_RATEMCS6: + case ODM_RATEMCS5: + case ODM_RATEMCS4: + case ODM_RATEMCS3: + case ODM_RATE54M: + case ODM_RATE48M: + case ODM_RATE36M: + case ODM_RATE24M: + RTS_Ini_Rate = ODM_RATE24M; + break; + case ODM_RATEVHTSS3MCS2: + case ODM_RATEVHTSS3MCS1: + case ODM_RATEVHTSS2MCS2: + case ODM_RATEVHTSS2MCS1: + case ODM_RATEVHTSS1MCS2: + case ODM_RATEVHTSS1MCS1: + case ODM_RATEMCS10: + case ODM_RATEMCS9: + case ODM_RATEMCS2: + case ODM_RATEMCS1: + case ODM_RATE18M: + case ODM_RATE12M: + RTS_Ini_Rate = ODM_RATE12M; + break; + case ODM_RATEVHTSS3MCS0: + case ODM_RATEVHTSS2MCS0: + case ODM_RATEVHTSS1MCS0: + case ODM_RATEMCS8: + case ODM_RATEMCS0: + case ODM_RATE9M: + case ODM_RATE6M: + RTS_Ini_Rate = ODM_RATE6M; + break; + case ODM_RATE11M: + case ODM_RATE5_5M: + case ODM_RATE2M: + case ODM_RATE1M: + RTS_Ini_Rate = ODM_RATE1M; + break; + default: + RTS_Ini_Rate = ODM_RATE6M; + break; + } + } + + if (*pDM_Odm->pBandType == 1) { + if (RTS_Ini_Rate < ODM_RATE6M) + RTS_Ini_Rate = ODM_RATE6M; + } + return RTS_Ini_Rate; + +} + +VOID +odm_Set_RA_DM_ARFB_by_Noisy( + IN PDM_ODM_T pDM_Odm +) +{ + /*DbgPrint("DM_ARFB ====>\n");*/ + if (pDM_Odm->bNoisyState) { + ODM_Write4Byte(pDM_Odm, 0x430, 0x00000000); + ODM_Write4Byte(pDM_Odm, 0x434, 0x05040200); + /*DbgPrint("DM_ARFB ====> Noisy State\n");*/ + } else { + ODM_Write4Byte(pDM_Odm, 0x430, 0x02010000); + ODM_Write4Byte(pDM_Odm, 0x434, 0x07050403); + /*DbgPrint("DM_ARFB ====> Clean State\n");*/ + } + +} + +VOID +ODM_UpdateNoisyState( + IN PVOID pDM_VOID, + IN BOOLEAN bNoisyStateFromC2H +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + /*DbgPrint("Get C2H Command! NoisyState=0x%x\n ", bNoisyStateFromC2H);*/ + if (pDM_Odm->SupportICType == ODM_RTL8821 || pDM_Odm->SupportICType == ODM_RTL8812 || + pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8188E) + pDM_Odm->bNoisyState = bNoisyStateFromC2H; + odm_Set_RA_DM_ARFB_by_Noisy(pDM_Odm); +}; + +u4Byte +Set_RA_DM_Ratrbitmap_by_Noisy( + IN PVOID pDM_VOID, + IN WIRELESS_MODE WirelessMode, + IN u4Byte ratr_bitmap, + IN u1Byte rssi_level +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte ret_bitmap = ratr_bitmap; + + return ret_bitmap; + + switch (WirelessMode) { + case WIRELESS_MODE_AC_24G: + case WIRELESS_MODE_AC_5G: + case WIRELESS_MODE_AC_ONLY: + if (pDM_Odm->bNoisyState) { /*in Noisy State*/ + if (rssi_level == 1) + ret_bitmap &= 0xfc3e0c08; // Reserve MCS 5-9 + else if (rssi_level == 2) + ret_bitmap &= 0xfe3f8e08; // Reserve MCS 3-9 + else if (rssi_level == 3) + ret_bitmap &= 0xffffffff; + else + ret_bitmap &= 0xffffffff; + } else { /* in SNR State*/ + if (rssi_level == 1) + ret_bitmap &= 0xfe3f0e08; // Reserve MCS 4-9 + else if (rssi_level == 2) + ret_bitmap &= 0xff3fcf8c; // Reserve MCS 2-9 + else if (rssi_level == 3) + ret_bitmap &= 0xffffffff; + else + ret_bitmap &= 0xffffffff; + } + break; + case WIRELESS_MODE_B: + case WIRELESS_MODE_A: + case WIRELESS_MODE_G: + case WIRELESS_MODE_N_24G: + case WIRELESS_MODE_N_5G: + if (pDM_Odm->bNoisyState) { + if (rssi_level == 1) + ret_bitmap &= 0x0f0e0c08; // Reserve MCS 4-7; MCS12-15 + else if (rssi_level == 2) + ret_bitmap &= 0x0fcfce0c; // Reserve MCS 2-7; MCS10-15 + else if (rssi_level == 3) + ret_bitmap &= 0xffffffff; + else + ret_bitmap &= 0xffffffff; + } else { + if (rssi_level == 1) + ret_bitmap &= 0x0f8f8e08; // Reserve MCS 3-7; MCS11-15 + else if (rssi_level == 2) + ret_bitmap &= 0x0fefef8c; // Reserve MCS 1-7; MCS9-15 + else if (rssi_level == 3) + ret_bitmap &= 0xffffffff; + else + ret_bitmap &= 0xffffffff; + } + break; + default: + break; + } + /*DbgPrint("DM_RAMask ====> rssi_LV = %d, BITMAP = %x\n", rssi_level, ret_bitmap);*/ + return ret_bitmap; + +} + +VOID +ODM_UpdateInitRate( + IN PVOID pDM_VOID, + IN u1Byte Rate +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte p = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Get C2H Command! Rate=0x%x\n", Rate)); + + pDM_Odm->TxRate = Rate; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#if DEV_BUS_TYPE == RT_PCI_INTERFACE +#if USE_WORKITEM + PlatformScheduleWorkItem(&pDM_Odm->RaRptWorkitem); +#else + if (pDM_Odm->SupportICType == ODM_RTL8821) { +#if (RTL8821A_SUPPORT == 1) + ODM_TxPwrTrackSetPwr8821A(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0); +#endif + } else if (pDM_Odm->SupportICType == ODM_RTL8812) { + for (p = ODM_RF_PATH_A; p < MAX_PATH_NUM_8812A; p++) { +#if (RTL8812A_SUPPORT == 1) + ODM_TxPwrTrackSetPwr8812A(pDM_Odm, MIX_MODE, p, 0); +#endif + } + } else if (pDM_Odm->SupportICType == ODM_RTL8723B) { +#if (RTL8723B_SUPPORT == 1) + ODM_TxPwrTrackSetPwr_8723B(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0); +#endif + } else if (pDM_Odm->SupportICType == ODM_RTL8192E) { + for (p = ODM_RF_PATH_A; p < MAX_PATH_NUM_8192E; p++) { +#if (RTL8192E_SUPPORT == 1) + ODM_TxPwrTrackSetPwr92E(pDM_Odm, MIX_MODE, p, 0); +#endif + } + } else if (pDM_Odm->SupportICType == ODM_RTL8188E) { +#if (RTL8188E_SUPPORT == 1) + ODM_TxPwrTrackSetPwr88E(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0); +#endif + } +#endif +#else + PlatformScheduleWorkItem(&pDM_Odm->RaRptWorkitem); +#endif +#endif + +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +VOID +odm_RSSIDumpToRegister( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + + if (pDM_Odm->SupportICType == ODM_RTL8812) { + PlatformEFIOWrite1Byte(Adapter, rA_RSSIDump_Jaguar, Adapter->RxStats.RxRSSIPercentage[0]); + PlatformEFIOWrite1Byte(Adapter, rB_RSSIDump_Jaguar, Adapter->RxStats.RxRSSIPercentage[1]); + + /* Rx EVM*/ + PlatformEFIOWrite1Byte(Adapter, rS1_RXevmDump_Jaguar, Adapter->RxStats.RxEVMdbm[0]); + PlatformEFIOWrite1Byte(Adapter, rS2_RXevmDump_Jaguar, Adapter->RxStats.RxEVMdbm[1]); + + /* Rx SNR*/ + PlatformEFIOWrite1Byte(Adapter, rA_RXsnrDump_Jaguar, (u1Byte)(Adapter->RxStats.RxSNRdB[0])); + PlatformEFIOWrite1Byte(Adapter, rB_RXsnrDump_Jaguar, (u1Byte)(Adapter->RxStats.RxSNRdB[1])); + + /* Rx Cfo_Short*/ + PlatformEFIOWrite2Byte(Adapter, rA_CfoShortDump_Jaguar, Adapter->RxStats.RxCfoShort[0]); + PlatformEFIOWrite2Byte(Adapter, rB_CfoShortDump_Jaguar, Adapter->RxStats.RxCfoShort[1]); + + /* Rx Cfo_Tail*/ + PlatformEFIOWrite2Byte(Adapter, rA_CfoLongDump_Jaguar, Adapter->RxStats.RxCfoTail[0]); + PlatformEFIOWrite2Byte(Adapter, rB_CfoLongDump_Jaguar, Adapter->RxStats.RxCfoTail[1]); + } else if (pDM_Odm->SupportICType == ODM_RTL8192E) { + PlatformEFIOWrite1Byte(Adapter, rA_RSSIDump_92E, Adapter->RxStats.RxRSSIPercentage[0]); + PlatformEFIOWrite1Byte(Adapter, rB_RSSIDump_92E, Adapter->RxStats.RxRSSIPercentage[1]); + /* Rx EVM*/ + PlatformEFIOWrite1Byte(Adapter, rS1_RXevmDump_92E, Adapter->RxStats.RxEVMdbm[0]); + PlatformEFIOWrite1Byte(Adapter, rS2_RXevmDump_92E, Adapter->RxStats.RxEVMdbm[1]); + /* Rx SNR*/ + PlatformEFIOWrite1Byte(Adapter, rA_RXsnrDump_92E, (u1Byte)(Adapter->RxStats.RxSNRdB[0])); + PlatformEFIOWrite1Byte(Adapter, rB_RXsnrDump_92E, (u1Byte)(Adapter->RxStats.RxSNRdB[1])); + /* Rx Cfo_Short*/ + PlatformEFIOWrite2Byte(Adapter, rA_CfoShortDump_92E, Adapter->RxStats.RxCfoShort[0]); + PlatformEFIOWrite2Byte(Adapter, rB_CfoShortDump_92E, Adapter->RxStats.RxCfoShort[1]); + /* Rx Cfo_Tail*/ + PlatformEFIOWrite2Byte(Adapter, rA_CfoLongDump_92E, Adapter->RxStats.RxCfoTail[0]); + PlatformEFIOWrite2Byte(Adapter, rB_CfoLongDump_92E, Adapter->RxStats.RxCfoTail[1]); + } +} + +VOID +odm_RefreshLdpcRtsMP( + IN PADAPTER pAdapter, + IN PDM_ODM_T pDM_Odm, + IN u1Byte mMacId, + IN u1Byte IOTPeer, + IN s4Byte UndecoratedSmoothedPWDB +) +{ + BOOLEAN bCtlLdpc = FALSE; + PMGNT_INFO pMgntInfo = GetDefaultMgntInfo(pAdapter); + PODM_RATE_ADAPTIVE pRA = &pDM_Odm->RateAdaptive; + + if (pDM_Odm->SupportICType != ODM_RTL8821 && pDM_Odm->SupportICType != ODM_RTL8812) + return; + + if ((pDM_Odm->SupportICType == ODM_RTL8821) && (pDM_Odm->CutVersion == ODM_CUT_A)) + bCtlLdpc = TRUE; + else if (pDM_Odm->SupportICType == ODM_RTL8812 && + IOTPeer == HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP) + bCtlLdpc = TRUE; + + if (bCtlLdpc) { + if (UndecoratedSmoothedPWDB < (pRA->LdpcThres - 5)) + MgntSet_TX_LDPC(pAdapter, mMacId, TRUE); + else if (UndecoratedSmoothedPWDB > pRA->LdpcThres) + MgntSet_TX_LDPC(pAdapter, mMacId, FALSE); + } + + if (UndecoratedSmoothedPWDB < (pRA->RtsThres - 5)) + pRA->bLowerRtsRate = TRUE; + else if (UndecoratedSmoothedPWDB > pRA->RtsThres) + pRA->bLowerRtsRate = FALSE; +} + +VOID +ODM_DynamicARFBSelect( + IN PVOID pDM_VOID, + IN u1Byte rate, + IN BOOLEAN Collision_State +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRA_T pRA_Table = &pDM_Odm->DM_RA_Table; + + if (pDM_Odm->SupportICType != ODM_RTL8192E) + return; + + if (Collision_State == pRA_Table->PT_collision_pre) + return; + + if (rate >= DESC_RATEMCS8 && rate <= DESC_RATEMCS12) { + if (Collision_State == 1) { + if (rate == DESC_RATEMCS12) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x07060501); + } else if (rate == DESC_RATEMCS11) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x07070605); + } else if (rate == DESC_RATEMCS10) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x08080706); + } else if (rate == DESC_RATEMCS9) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x08080707); + } else { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x09090808); + } + } else { /* Collision_State == 0*/ + if (rate == DESC_RATEMCS12) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x05010000); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x09080706); + } else if (rate == DESC_RATEMCS11) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x06050000); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x09080807); + } else if (rate == DESC_RATEMCS10) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x07060000); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x0a090908); + } else if (rate == DESC_RATEMCS9) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x07070000); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x0a090808); + } else { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x08080000); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x0b0a0909); + } + } + } else { /* MCS13~MCS15, 1SS, G-mode*/ + if (Collision_State == 1) { + if (rate == DESC_RATEMCS15) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x00000000); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x05040302); + } else if (rate == DESC_RATEMCS14) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x00000000); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x06050302); + } else if (rate == DESC_RATEMCS13) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x00000000); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x07060502); + } else { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x00000000); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x06050402); + } + } else { // Collision_State == 0 + if (rate == DESC_RATEMCS15) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x03020000); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x07060504); + } else if (rate == DESC_RATEMCS14) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x03020000); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x08070605); + } else if (rate == DESC_RATEMCS13) { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x05020000); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x09080706); + } else { + + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x04020000); + ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x08070605); + } + + + } + + } + pRA_Table->PT_collision_pre = Collision_State; +} + +VOID +ODM_RateAdaptiveStateApInit( + IN PVOID PADAPTER_VOID, + IN PRT_WLAN_STA pEntry +) +{ + PADAPTER Adapter = (PADAPTER)PADAPTER_VOID; + pEntry->Ratr_State = DM_RATR_STA_INIT; +} +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) /*#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)*/ + +static void +FindMinimumRSSI( + IN PADAPTER pAdapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + + /*Determine the minimum RSSI*/ + + if ((pDM_Odm->bLinked != _TRUE) && + (pHalData->EntryMinUndecoratedSmoothedPWDB == 0)) { + pHalData->MinUndecoratedPWDBForDM = 0; + /*ODM_RT_TRACE(pDM_Odm,COMP_BB_POWERSAVING, DBG_LOUD, ("Not connected to any\n"));*/ + } else + pHalData->MinUndecoratedPWDBForDM = pHalData->EntryMinUndecoratedSmoothedPWDB; + + /*DBG_8192C("%s=>MinUndecoratedPWDBForDM(%d)\n",__FUNCTION__,pdmpriv->MinUndecoratedPWDBForDM);*/ + /*ODM_RT_TRACE(pDM_Odm,COMP_DIG, DBG_LOUD, ("MinUndecoratedPWDBForDM =%d\n",pHalData->MinUndecoratedPWDBForDM));*/ +} + +u8Byte +PhyDM_Get_Rate_Bitmap_Ex( + IN PVOID pDM_VOID, + IN u4Byte macid, + IN u8Byte ra_mask, + IN u1Byte rssi_level, + OUT u8Byte *dm_RA_Mask, + OUT u1Byte *dm_RteID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PSTA_INFO_T pEntry; + u8Byte rate_bitmap = 0; + u1Byte WirelessMode; + + pEntry = pDM_Odm->pODM_StaInfo[macid]; + if (!IS_STA_VALID(pEntry)) + return ra_mask; + WirelessMode = pEntry->wireless_mode; + switch (WirelessMode) { + case ODM_WM_B: + if (ra_mask & 0x000000000000000c) /* 11M or 5.5M enable */ + rate_bitmap = 0x000000000000000d; + else + rate_bitmap = 0x000000000000000f; + break; + + case (ODM_WM_G): + case (ODM_WM_A): + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x0000000000000f00; + else + rate_bitmap = 0x0000000000000ff0; + break; + + case (ODM_WM_B|ODM_WM_G): + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x0000000000000f00; + else if (rssi_level == DM_RATR_STA_MIDDLE) + rate_bitmap = 0x0000000000000ff0; + else + rate_bitmap = 0x0000000000000ff5; + break; + + case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G): + case (ODM_WM_B|ODM_WM_N24G): + case (ODM_WM_G|ODM_WM_N24G): + case (ODM_WM_A|ODM_WM_N5G): { + if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) { + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x00000000000f0000; + else if (rssi_level == DM_RATR_STA_MIDDLE) + rate_bitmap = 0x00000000000ff000; + else { + if (*(pDM_Odm->pBandWidth) == ODM_BW40M) + rate_bitmap = 0x00000000000ff015; + else + rate_bitmap = 0x00000000000ff005; + } + } else if (pDM_Odm->RFType == ODM_2T2R || pDM_Odm->RFType == ODM_2T3R || pDM_Odm->RFType == ODM_2T4R) { + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x000000000f8f0000; + else if (rssi_level == DM_RATR_STA_MIDDLE) + rate_bitmap = 0x000000000f8ff000; + else { + if (*(pDM_Odm->pBandWidth) == ODM_BW40M) + rate_bitmap = 0x000000000f8ff015; + else + rate_bitmap = 0x000000000f8ff005; + } + } else { + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x0000000f0f0f0000; + else if (rssi_level == DM_RATR_STA_MIDDLE) + rate_bitmap = 0x0000000fcfcfe000; + else { + if (*(pDM_Odm->pBandWidth) == ODM_BW40M) + rate_bitmap = 0x0000000ffffff015; + else + rate_bitmap = 0x0000000ffffff005; + } + } + } + break; + + case (ODM_WM_AC|ODM_WM_G): + if (rssi_level == 1) + rate_bitmap = 0x00000000fc3f0000; + else if (rssi_level == 2) + rate_bitmap = 0x00000000fffff000; + else + rate_bitmap = 0x00000000ffffffff; + break; + + case (ODM_WM_AC|ODM_WM_A): + + if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) { + if (rssi_level == 1) /* add by Gary for ac-series */ + rate_bitmap = 0x00000000003f8000; + else if (rssi_level == 2) + rate_bitmap = 0x00000000003fe000; + else + rate_bitmap = 0x00000000003ff010; + } else if (pDM_Odm->RFType == ODM_2T2R || pDM_Odm->RFType == ODM_2T3R || pDM_Odm->RFType == ODM_2T4R) { + if (rssi_level == 1) /* add by Gary for ac-series */ + rate_bitmap = 0x00000000fe3f8000; /* VHT 2SS MCS3~9 */ + else if (rssi_level == 2) + rate_bitmap = 0x00000000fffff000; /* VHT 2SS MCS0~9 */ + else + rate_bitmap = 0x00000000fffff010; /* All */ + } else { + if (rssi_level == 1) /* add by Gary for ac-series */ + rate_bitmap = 0x000003f8fe3f8000ULL; /* VHT 3SS MCS3~9 */ + else if (rssi_level == 2) + rate_bitmap = 0x000003fffffff000ULL; /* VHT3SS MCS0~9 */ + else + rate_bitmap = 0x000003fffffff010ULL; /* All */ + } + break; + + default: + if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) + rate_bitmap = 0x00000000000fffff; + else if (pDM_Odm->RFType == ODM_2T2R || pDM_Odm->RFType == ODM_2T3R || pDM_Odm->RFType == ODM_2T4R) + rate_bitmap = 0x000000000fffffff; + else + rate_bitmap = 0x0000003fffffffffULL; + break; + + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%016llx\n", rssi_level, WirelessMode, rate_bitmap)); + + return (ra_mask & rate_bitmap); +} + + +u4Byte +ODM_Get_Rate_Bitmap( + IN PVOID pDM_VOID, + IN u4Byte macid, + IN u4Byte ra_mask, + IN u1Byte rssi_level +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PSTA_INFO_T pEntry; + u4Byte rate_bitmap = 0; + u1Byte WirelessMode; + //u1Byte WirelessMode =*(pDM_Odm->pWirelessMode); + + + pEntry = pDM_Odm->pODM_StaInfo[macid]; + if (!IS_STA_VALID(pEntry)) + return ra_mask; + + WirelessMode = pEntry->wireless_mode; + + switch (WirelessMode) { + case ODM_WM_B: + if (ra_mask & 0x0000000c) //11M or 5.5M enable + rate_bitmap = 0x0000000d; + else + rate_bitmap = 0x0000000f; + break; + + case (ODM_WM_G): + case (ODM_WM_A): + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x00000f00; + else + rate_bitmap = 0x00000ff0; + break; + + case (ODM_WM_B|ODM_WM_G): + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x00000f00; + else if (rssi_level == DM_RATR_STA_MIDDLE) + rate_bitmap = 0x00000ff0; + else + rate_bitmap = 0x00000ff5; + break; + + case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G) : + case (ODM_WM_B|ODM_WM_N24G) : + case (ODM_WM_G|ODM_WM_N24G) : + case (ODM_WM_A|ODM_WM_N5G) : { + if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) { + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x000f0000; + else if (rssi_level == DM_RATR_STA_MIDDLE) + rate_bitmap = 0x000ff000; + else { + if (*(pDM_Odm->pBandWidth) == ODM_BW40M) + rate_bitmap = 0x000ff015; + else + rate_bitmap = 0x000ff005; + } + } else { + if (rssi_level == DM_RATR_STA_HIGH) + rate_bitmap = 0x0f8f0000; + else if (rssi_level == DM_RATR_STA_MIDDLE) + rate_bitmap = 0x0f8ff000; + else { + if (*(pDM_Odm->pBandWidth) == ODM_BW40M) + rate_bitmap = 0x0f8ff015; + else + rate_bitmap = 0x0f8ff005; + } + } + } + break; + + case (ODM_WM_AC|ODM_WM_G): + if (rssi_level == 1) + rate_bitmap = 0xfc3f0000; + else if (rssi_level == 2) + rate_bitmap = 0xfffff000; + else + rate_bitmap = 0xffffffff; + break; + + case (ODM_WM_AC|ODM_WM_A): + + if (pDM_Odm->RFType == RF_1T1R) { + if (rssi_level == 1) // add by Gary for ac-series + rate_bitmap = 0x003f8000; + else if (rssi_level == 2) + rate_bitmap = 0x003ff000; + else + rate_bitmap = 0x003ff010; + } else { + if (rssi_level == 1) // add by Gary for ac-series + rate_bitmap = 0xfe3f8000; // VHT 2SS MCS3~9 + else if (rssi_level == 2) + rate_bitmap = 0xfffff000; // VHT 2SS MCS0~9 + else + rate_bitmap = 0xfffff010; // All + } + break; + + default: + if (pDM_Odm->RFType == RF_1T2R) + rate_bitmap = 0x000fffff; + else + rate_bitmap = 0x0fffffff; + break; + + } + + DBG_871X("%s ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x\n", __func__, rssi_level, WirelessMode, rate_bitmap); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x\n", rssi_level, WirelessMode, rate_bitmap)); + + return (ra_mask & rate_bitmap); + +} + +#endif //#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + +#endif /*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))*/ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_rainfo.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_rainfo.h new file mode 100644 index 000000000..da7869526 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_rainfo.h @@ -0,0 +1,445 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __PHYDMRAINFO_H__ +#define __PHYDMRAINFO_H__ + +/*#define RAINFO_VERSION "2.0" //2014.11.04*/ +/*#define RAINFO_VERSION "3.0" //2015.01.13 Dino*/ +/*#define RAINFO_VERSION "3.1" //2015.01.14 Dino*/ +#define RAINFO_VERSION "3.2" /*2015.01.14 Dino*/ + +#define HIGH_RSSI_THRESH 50 +#define LOW_RSSI_THRESH 20 + +#define ACTIVE_TP_THRESHOLD 150 +#define RA_RETRY_DESCEND_NUM 2 +#define RA_RETRY_LIMIT_LOW 4 +#define RA_RETRY_LIMIT_HIGH 32 + +#define PHYDM_IC_8051_SERIES (ODM_RTL8881A|ODM_RTL8812|ODM_RTL8821|ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E|ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8703B|ODM_RTL8188F) +#define PHYDM_IC_3081_SERIES (ODM_RTL8814A|ODM_RTL8821B|ODM_RTL8822B) + +#define RAINFO_BE_RX_STATE BIT0 // 1:RX //ULDL +#define RAINFO_STBC_STATE BIT1 +//#define RAINFO_LDPC_STATE BIT2 +#define RAINFO_NOISY_STATE BIT2 // set by Noisy_Detection +#define RAINFO_SHURTCUT_STATE BIT3 +#define RAINFO_SHURTCUT_FLAG BIT4 +#define RAINFO_INIT_RSSI_RATE_STATE BIT5 +#define RAINFO_BF_STATE BIT6 +#define RAINFO_BE_TX_STATE BIT7 // 1:TX + +#define RA_MASK_CCK 0xf +#define RA_MASK_OFDM 0xff0 +#define RA_MASK_HT1SS 0xff000 +#define RA_MASK_HT2SS 0xff00000 +/*#define RA_MASK_MCS3SS */ +#define RA_MASK_HT4SS 0xff0 +#define RA_MASK_VHT1SS 0x3ff000 +#define RA_MASK_VHT2SS 0xffc00000 + +#if(DM_ODM_SUPPORT_TYPE == ODM_AP) +#define EXT_RA_INFO_SUPPORT_IC (ODM_RTL8881A |ODM_RTL8192E |ODM_RTL8812 |ODM_RTL8814A|ODM_RTL8822B) +#define RA_FIRST_MACID 1 +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#define EXT_RA_INFO_SUPPORT_IC (ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8723B | ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8703B) +#define RA_FIRST_MACID 0 +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +/*#define EXT_RA_INFO_SUPPORT_IC (ODM_RTL8192E|ODM_RTL8812|ODM_RTL8821|ODM_RTL8723B|ODM_RTL8814A|ODM_RTL8822B|ODM_RTL8703B) */ +#define RA_FIRST_MACID 0 +#endif + + +#define AP_InitRateAdaptiveState ODM_RateAdaptiveStateApInit + +#define DM_RATR_STA_INIT 0 +#define DM_RATR_STA_HIGH 1 +#define DM_RATR_STA_MIDDLE 2 +#define DM_RATR_STA_LOW 3 +#if(DM_ODM_SUPPORT_TYPE & ODM_AP) +#define DM_RATR_STA_ULTRA_LOW 4 +#endif + +#define DM_RA_RATE_UP 1 +#define DM_RA_RATE_DOWN 2 + +typedef enum _phydm_arfr_num { + ARFR_0_RATE_ID = 0x9, + ARFR_1_RATE_ID = 0xa, + ARFR_2_RATE_ID = 0xb, + ARFR_3_RATE_ID = 0xc, + ARFR_4_RATE_ID = 0xd, + ARFR_5_RATE_ID = 0xe +} PHYDM_RA_ARFR_NUM_E; + +typedef enum _Phydm_ra_dbg_para { + RADBG_RTY_PENALTY = 1, //u8 + RADBG_N_HIGH = 2, + RADBG_N_LOW = 3, + RADBG_TRATE_UP_TABLE = 4, + RADBG_TRATE_DOWN_TABLE = 5, + RADBG_TRYING_NECESSARY = 6, + RADBG_TDROPING_NECESSARY = 7, + RADBG_RATE_UP_RTY_RATIO = 8, //u8 + RADBG_RATE_DOWN_RTY_RATIO = 9, //u8 + + RADBG_DEBUG_MONITOR1 = 0xc, + RADBG_DEBUG_MONITOR2 = 0xd, + RADBG_DEBUG_MONITOR3 = 0xe, + RADBG_DEBUG_MONITOR4 = 0xf, + NUM_RA_PARA +} PHYDM_RA_DBG_PARA_E; + + +#if (RATE_ADAPTIVE_SUPPORT == 1)//88E RA +typedef struct _ODM_RA_Info_ { + u1Byte RateID; + u4Byte RateMask; + u4Byte RAUseRate; + u1Byte RateSGI; + u1Byte RssiStaRA; + u1Byte PreRssiStaRA; + u1Byte SGIEnable; + u1Byte DecisionRate; + u1Byte PreRate; + u1Byte HighestRate; + u1Byte LowestRate; + u4Byte NscUp; + u4Byte NscDown; + u2Byte RTY[5]; + u4Byte TOTAL; + u2Byte DROP; + u1Byte Active; + u2Byte RptTime; + u1Byte RAWaitingCounter; + u1Byte RAPendingCounter; +#if 1 //POWER_TRAINING_ACTIVE == 1 // For compile pass only~! + u1Byte PTActive; // on or off + u1Byte PTTryState; // 0 trying state, 1 for decision state + u1Byte PTStage; // 0~6 + u1Byte PTStopCount; //Stop PT counter + u1Byte PTPreRate; // if rate change do PT + u1Byte PTPreRssi; // if RSSI change 5% do PT + u1Byte PTModeSS; // decide whitch rate should do PT + u1Byte RAstage; // StageRA, decide how many times RA will be done between PT + u1Byte PTSmoothFactor; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_AP) && ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + u1Byte RateDownCounter; + u1Byte RateUpCounter; + u1Byte RateDirection; + u1Byte BoundingType; + u1Byte BoundingCounter; + u1Byte BoundingLearningTime; + u1Byte RateDownStartTime; +#endif +} ODM_RA_INFO_T, *PODM_RA_INFO_T; +#endif + + +typedef struct _Rate_Adaptive_Table_ { + u1Byte firstconnect; +#if(DM_ODM_SUPPORT_TYPE==ODM_WIN) + BOOLEAN PT_collision_pre; +#endif + +#if (defined(CONFIG_RA_DBG_CMD)) + BOOLEAN is_ra_dbg_init; + + u1Byte RTY_P[ODM_NUM_RATE_IDX]; + u1Byte RTY_P_default[ODM_NUM_RATE_IDX]; + BOOLEAN RTY_P_modify_note[ODM_NUM_RATE_IDX]; + + u1Byte RATE_UP_RTY_RATIO[ODM_NUM_RATE_IDX]; + u1Byte RATE_UP_RTY_RATIO_default[ODM_NUM_RATE_IDX]; + BOOLEAN RATE_UP_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX]; + + u1Byte RATE_DOWN_RTY_RATIO[ODM_NUM_RATE_IDX]; + u1Byte RATE_DOWN_RTY_RATIO_default[ODM_NUM_RATE_IDX]; + BOOLEAN RATE_DOWN_RTY_RATIO_modify_note[ODM_NUM_RATE_IDX]; + + BOOLEAN RA_Para_feedback_req; + + u1Byte para_idx; + u1Byte rate_idx; + u1Byte value; + u2Byte value_16; + u1Byte rate_length; +#endif + u1Byte link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM]; + + #if (defined(CONFIG_RA_DYNAMIC_RTY_LIMIT)) + u1Byte per_rate_retrylimit_20M[ODM_NUM_RATE_IDX]; + u1Byte per_rate_retrylimit_40M[ODM_NUM_RATE_IDX]; + u1Byte retry_descend_num; + u1Byte retrylimit_low; + u1Byte retrylimit_high; + #endif + + +} RA_T, *pRA_T; + +typedef struct _ODM_RATE_ADAPTIVE { + u1Byte Type; // DM_Type_ByFW/DM_Type_ByDriver + u1Byte HighRSSIThresh; // if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH + u1Byte LowRSSIThresh; // if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW + u1Byte RATRState; // Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW + +#if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE)) + u1Byte LdpcThres; // if RSSI > LdpcThres => switch from LPDC to BCC + BOOLEAN bLowerRtsRate; +#endif + +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + u1Byte RtsThres; +#elif(DM_ODM_SUPPORT_TYPE & ODM_CE) + BOOLEAN bUseLdpc; +#else + u1Byte UltraLowRSSIThresh; + u4Byte LastRATR; // RATR Register Content +#endif + +} ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE; + +VOID +ODM_C2HRaParaReportHandler( + IN PVOID pDM_VOID, + IN pu1Byte CmdBuf, + IN u1Byte CmdLen +); + +VOID +odm_RA_ParaAdjust_Send_H2C( + IN PVOID pDM_VOID +); + +VOID +odm_RA_debug( + IN PVOID pDM_VOID, + IN u4Byte *const dm_value +); + +VOID +odm_RA_ParaAdjust_init( + IN PVOID pDM_VOID +); + +VOID +odm_RA_ParaAdjust( + IN PVOID pDM_VOID +); + +VOID +phydm_ra_dynamic_retry_count( + IN PVOID pDM_VOID +); + +VOID +phydm_ra_dynamic_retry_limit( + IN PVOID pDM_VOID +); + +VOID +phydm_ra_dynamic_rate_id_on_assoc( + IN PVOID pDM_VOID, + IN u1Byte wireless_mode, + IN u1Byte init_rate_id +); + +VOID +phydm_c2h_ra_report_handler( + IN PVOID pDM_VOID, + IN pu1Byte CmdBuf, + IN u1Byte CmdLen +); + +VOID +phydm_ra_info_init( + IN PVOID pDM_VOID +); + +VOID +odm_RSSIMonitorInit( + IN PVOID pDM_VOID +); + +VOID +odm_RSSIMonitorCheck( + IN PVOID pDM_VOID +); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +s4Byte +phydm_FindMinimumRSSI( +IN PDM_ODM_T pDM_Odm, +IN PADAPTER pAdapter, +IN OUT BOOLEAN *pbLink_temp + + ); +#endif + +VOID +odm_RSSIMonitorCheckMP( + IN PVOID pDM_VOID +); + +VOID +odm_RSSIMonitorCheckCE( + IN PVOID pDM_VOID +); + +VOID +odm_RSSIMonitorCheckAP( + IN PVOID pDM_VOID +); + + +VOID +odm_RateAdaptiveMaskInit( + IN PVOID pDM_VOID +); + +VOID +odm_RefreshRateAdaptiveMask( + IN PVOID pDM_VOID +); + +VOID +odm_RefreshRateAdaptiveMaskMP( + IN PVOID pDM_VOID +); + +VOID +odm_RefreshRateAdaptiveMaskCE( + IN PVOID pDM_VOID +); + +VOID +odm_RefreshRateAdaptiveMaskAPADSL( + IN PVOID pDM_VOID +); + +BOOLEAN +ODM_RAStateCheck( + IN PVOID pDM_VOID, + IN s4Byte RSSI, + IN BOOLEAN bForceUpdate, + OUT pu1Byte pRATRState +); + +VOID +odm_RefreshBasicRateMask( + IN PVOID pDM_VOID +); +VOID +ODM_RAPostActionOnAssoc( + IN PVOID pDM_Odm +); + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + +u1Byte +odm_Find_RTS_Rate( + IN PVOID pDM_VOID, + IN u1Byte Tx_Rate, + IN BOOLEAN bErpProtect +); + +VOID +ODM_UpdateNoisyState( + IN PVOID pDM_VOID, + IN BOOLEAN bNoisyStateFromC2H +); + +u4Byte +Set_RA_DM_Ratrbitmap_by_Noisy( + IN PVOID pDM_VOID, + IN WIRELESS_MODE WirelessMode, + IN u4Byte ratr_bitmap, + IN u1Byte rssi_level +); + +VOID +ODM_UpdateInitRate( + IN PVOID pDM_VOID, + IN u1Byte Rate +); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +VOID +odm_RSSIDumpToRegister( + IN PVOID pDM_VOID +); + +VOID +odm_RefreshLdpcRtsMP( + IN PADAPTER pAdapter, + IN PDM_ODM_T pDM_Odm, + IN u1Byte mMacId, + IN u1Byte IOTPeer, + IN s4Byte UndecoratedSmoothedPWDB +); + +VOID +ODM_DynamicARFBSelect( + IN PVOID pDM_VOID, + IN u1Byte rate, + IN BOOLEAN Collision_State +); + +VOID +ODM_RateAdaptiveStateApInit( + IN PVOID PADAPTER_VOID, + IN PRT_WLAN_STA pEntry +); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + +static void +FindMinimumRSSI( + IN PADAPTER pAdapter +); + +u8Byte +PhyDM_Get_Rate_Bitmap_Ex( + IN PVOID pDM_VOID, + IN u4Byte macid, + IN u8Byte ra_mask, + IN u1Byte rssi_level, + OUT u8Byte *dm_RA_Mask, + OUT u1Byte *dm_RteID +); +u4Byte +ODM_Get_Rate_Bitmap( + IN PVOID pDM_VOID, + IN u4Byte macid, + IN u4Byte ra_mask, + IN u1Byte rssi_level +); +void phydm_ra_rssi_rpt_wk(PVOID pContext); + +#endif/*#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)*/ + +#endif/*#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))*/ + +#endif /*#ifndef __ODMRAINFO_H__*/ + + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_reg.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_reg.h new file mode 100644 index 000000000..e8424139b --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_reg.h @@ -0,0 +1,208 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +//============================================================ +// File Name: odm_reg.h +// +// Description: +// +// This file is for general register definition. +// +// +//============================================================ +#ifndef __HAL_ODM_REG_H__ +#define __HAL_ODM_REG_H__ + +// +// Register Definition +// + +//MAC REG +#define ODM_BB_RESET 0x002 +#define ODM_DUMMY 0x4fe +#define RF_T_METER_OLD 0x24 +#define RF_T_METER_NEW 0x42 + +#define ODM_EDCA_VO_PARAM 0x500 +#define ODM_EDCA_VI_PARAM 0x504 +#define ODM_EDCA_BE_PARAM 0x508 +#define ODM_EDCA_BK_PARAM 0x50C +#define ODM_TXPAUSE 0x522 + +//BB REG +#define ODM_FPGA_PHY0_PAGE8 0x800 +#define ODM_PSD_SETTING 0x808 +#define ODM_AFE_SETTING 0x818 +#define ODM_TXAGC_B_6_18 0x830 +#define ODM_TXAGC_B_24_54 0x834 +#define ODM_TXAGC_B_MCS32_5 0x838 +#define ODM_TXAGC_B_MCS0_MCS3 0x83c +#define ODM_TXAGC_B_MCS4_MCS7 0x848 +#define ODM_TXAGC_B_MCS8_MCS11 0x84c +#define ODM_ANALOG_REGISTER 0x85c +#define ODM_RF_INTERFACE_OUTPUT 0x860 +#define ODM_TXAGC_B_MCS12_MCS15 0x868 +#define ODM_TXAGC_B_11_A_2_11 0x86c +#define ODM_AD_DA_LSB_MASK 0x874 +#define ODM_ENABLE_3_WIRE 0x88c +#define ODM_PSD_REPORT 0x8b4 +#define ODM_R_ANT_SELECT 0x90c +#define ODM_CCK_ANT_SELECT 0xa07 +#define ODM_CCK_PD_THRESH 0xa0a +#define ODM_CCK_RF_REG1 0xa11 +#define ODM_CCK_MATCH_FILTER 0xa20 +#define ODM_CCK_RAKE_MAC 0xa2e +#define ODM_CCK_CNT_RESET 0xa2d +#define ODM_CCK_TX_DIVERSITY 0xa2f +#define ODM_CCK_FA_CNT_MSB 0xa5b +#define ODM_CCK_FA_CNT_LSB 0xa5c +#define ODM_CCK_NEW_FUNCTION 0xa75 +#define ODM_OFDM_PHY0_PAGE_C 0xc00 +#define ODM_OFDM_RX_ANT 0xc04 +#define ODM_R_A_RXIQI 0xc14 +#define ODM_R_A_AGC_CORE1 0xc50 +#define ODM_R_A_AGC_CORE2 0xc54 +#define ODM_R_B_AGC_CORE1 0xc58 +#define ODM_R_AGC_PAR 0xc70 +#define ODM_R_HTSTF_AGC_PAR 0xc7c +#define ODM_TX_PWR_TRAINING_A 0xc90 +#define ODM_TX_PWR_TRAINING_B 0xc98 +#define ODM_OFDM_FA_CNT1 0xcf0 +#define ODM_OFDM_PHY0_PAGE_D 0xd00 +#define ODM_OFDM_FA_CNT2 0xda0 +#define ODM_OFDM_FA_CNT3 0xda4 +#define ODM_OFDM_FA_CNT4 0xda8 +#define ODM_TXAGC_A_6_18 0xe00 +#define ODM_TXAGC_A_24_54 0xe04 +#define ODM_TXAGC_A_1_MCS32 0xe08 +#define ODM_TXAGC_A_MCS0_MCS3 0xe10 +#define ODM_TXAGC_A_MCS4_MCS7 0xe14 +#define ODM_TXAGC_A_MCS8_MCS11 0xe18 +#define ODM_TXAGC_A_MCS12_MCS15 0xe1c + +//RF REG +#define ODM_GAIN_SETTING 0x00 +#define ODM_CHANNEL 0x18 +#define ODM_RF_T_METER 0x24 +#define ODM_RF_T_METER_92D 0x42 +#define ODM_RF_T_METER_88E 0x42 +#define ODM_RF_T_METER_92E 0x42 +#define ODM_RF_T_METER_8812 0x42 + +//Ant Detect Reg +#define ODM_DPDT 0x300 + +//PSD Init +#define ODM_PSDREG 0x808 + +//92D Path Div +#define PATHDIV_REG 0xB30 +#define PATHDIV_TRI 0xBA0 + + +// +// Bitmap Definition +// +#if(DM_ODM_SUPPORT_TYPE & (ODM_AP)) +// TX AGC +#define rTxAGC_A_CCK11_CCK1_JAguar 0xc20 +#define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24 +#define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28 +#define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c +#define rTxAGC_A_MCS7_MCS4_JAguar 0xc30 +#define rTxAGC_A_MCS11_MCS8_JAguar 0xc34 +#define rTxAGC_A_MCS15_MCS12_JAguar 0xc38 +#define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c +#define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40 +#define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44 +#define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48 +#define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c +#if defined(CONFIG_WLAN_HAL_8814AE) +#define rTxAGC_A_MCS19_MCS16_JAguar 0xcd8 +#define rTxAGC_A_MCS23_MCS20_JAguar 0xcdc +#define rTxAGC_A_Nss3Index3_Nss3Index0_JAguar 0xce0 +#define rTxAGC_A_Nss3Index7_Nss3Index4_JAguar 0xce4 +#define rTxAGC_A_Nss3Index9_Nss3Index8_JAguar 0xce8 +#endif +#define rTxAGC_B_CCK11_CCK1_JAguar 0xe20 +#define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24 +#define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28 +#define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c +#define rTxAGC_B_MCS7_MCS4_JAguar 0xe30 +#define rTxAGC_B_MCS11_MCS8_JAguar 0xe34 +#define rTxAGC_B_MCS15_MCS12_JAguar 0xe38 +#define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c +#define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40 +#define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44 +#define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48 +#define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c +#if defined(CONFIG_WLAN_HAL_8814AE) +#define rTxAGC_B_MCS19_MCS16_JAguar 0xed8 +#define rTxAGC_B_MCS23_MCS20_JAguar 0xedc +#define rTxAGC_B_Nss3Index3_Nss3Index0_JAguar 0xee0 +#define rTxAGC_B_Nss3Index7_Nss3Index4_JAguar 0xee4 +#define rTxAGC_B_Nss3Index9_Nss3Index8_JAguar 0xee8 +#define rTxAGC_C_CCK11_CCK1_JAguar 0x1820 +#define rTxAGC_C_Ofdm18_Ofdm6_JAguar 0x1824 +#define rTxAGC_C_Ofdm54_Ofdm24_JAguar 0x1828 +#define rTxAGC_C_MCS3_MCS0_JAguar 0x182c +#define rTxAGC_C_MCS7_MCS4_JAguar 0x1830 +#define rTxAGC_C_MCS11_MCS8_JAguar 0x1834 +#define rTxAGC_C_MCS15_MCS12_JAguar 0x1838 +#define rTxAGC_C_Nss1Index3_Nss1Index0_JAguar 0x183c +#define rTxAGC_C_Nss1Index7_Nss1Index4_JAguar 0x1840 +#define rTxAGC_C_Nss2Index1_Nss1Index8_JAguar 0x1844 +#define rTxAGC_C_Nss2Index5_Nss2Index2_JAguar 0x1848 +#define rTxAGC_C_Nss2Index9_Nss2Index6_JAguar 0x184c +#define rTxAGC_C_MCS19_MCS16_JAguar 0x18d8 +#define rTxAGC_C_MCS23_MCS20_JAguar 0x18dc +#define rTxAGC_C_Nss3Index3_Nss3Index0_JAguar 0x18e0 +#define rTxAGC_C_Nss3Index7_Nss3Index4_JAguar 0x18e4 +#define rTxAGC_C_Nss3Index9_Nss3Index8_JAguar 0x18e8 +#define rTxAGC_D_CCK11_CCK1_JAguar 0x1a20 +#define rTxAGC_D_Ofdm18_Ofdm6_JAguar 0x1a24 +#define rTxAGC_D_Ofdm54_Ofdm24_JAguar 0x1a28 +#define rTxAGC_D_MCS3_MCS0_JAguar 0x1a2c +#define rTxAGC_D_MCS7_MCS4_JAguar 0x1a30 +#define rTxAGC_D_MCS11_MCS8_JAguar 0x1a34 +#define rTxAGC_D_MCS15_MCS12_JAguar 0x1a38 +#define rTxAGC_D_Nss1Index3_Nss1Index0_JAguar 0x1a3c +#define rTxAGC_D_Nss1Index7_Nss1Index4_JAguar 0x1a40 +#define rTxAGC_D_Nss2Index1_Nss1Index8_JAguar 0x1a44 +#define rTxAGC_D_Nss2Index5_Nss2Index2_JAguar 0x1a48 +#define rTxAGC_D_Nss2Index9_Nss2Index6_JAguar 0x1a4c +#define rTxAGC_D_MCS19_MCS16_JAguar 0x1ad8 +#define rTxAGC_D_MCS23_MCS20_JAguar 0x1adc +#define rTxAGC_D_Nss3Index3_Nss3Index0_JAguar 0x1ae0 +#define rTxAGC_D_Nss3Index7_Nss3Index4_JAguar 0x1ae4 +#define rTxAGC_D_Nss3Index9_Nss3Index8_JAguar 0x1ae8 +#endif + +#define bTxAGC_byte0_Jaguar 0xff +#define bTxAGC_byte1_Jaguar 0xff00 +#define bTxAGC_byte2_Jaguar 0xff0000 +#define bTxAGC_byte3_Jaguar 0xff000000 +#endif + +#define BIT_FA_RESET BIT0 + + + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_regdefine11ac.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_regdefine11ac.h new file mode 100644 index 000000000..c8a551d1c --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_regdefine11ac.h @@ -0,0 +1,90 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __ODM_REGDEFINE11AC_H__ +#define __ODM_REGDEFINE11AC_H__ + +//2 RF REG LIST + + + +//2 BB REG LIST +//PAGE 8 +#define ODM_REG_CCK_RPT_FORMAT_11AC 0x804 +#define ODM_REG_BB_RX_PATH_11AC 0x808 +#define ODM_REG_BB_TX_PATH_11AC 0x80c +#define ODM_REG_BB_ATC_11AC 0x860 +#define ODM_REG_EDCCA_POWER_CAL 0x8dc +#define ODM_REG_DBG_RPT_11AC 0x8fc +//PAGE 9 +#define ODM_REG_EDCCA_DOWN_OPT 0x900 +#define ODM_REG_ACBB_EDCCA_ENHANCE 0x944 +#define ODM_REG_OFDM_FA_RST_11AC 0x9A4 +#define ODM_REG_NHM_TIMER_11AC 0x990 +#define ODM_REG_CLM_TIME_PERIOD_11AC 0x990 +#define ODM_REG_NHM_TH9_TH10_11AC 0x994 +#define ODM_REG_CLM_11AC 0x994 +#define ODM_REG_NHM_TH3_TO_TH0_11AC 0x998 +#define ODM_REG_NHM_TH7_TO_TH4_11AC 0x99c +#define ODM_REG_NHM_TH8_11AC 0x9a0 +#define ODM_REG_NHM_9E8_11AC 0x9e8 +#define ODM_REG_CSI_CONTENT_VALUE 0x9b4 +//PAGE A +#define ODM_REG_CCK_CCA_11AC 0xA0A +#define ODM_REG_CCK_FA_RST_11AC 0xA2C +#define ODM_REG_CCK_FA_11AC 0xA5C +//PAGE B +#define ODM_REG_RST_RPT_11AC 0xB58 +//PAGE C +#define ODM_REG_TRMUX_11AC 0xC08 +#define ODM_REG_IGI_A_11AC 0xC50 +//PAGE E +#define ODM_REG_IGI_B_11AC 0xE50 +#define ODM_REG_TRMUX_11AC_B 0xE08 +//PAGE F +#define ODM_REG_CCK_CCA_CNT_11AC 0xF08 +#define ODM_REG_OFDM_FA_11AC 0xF48 +#define ODM_REG_RPT_11AC 0xfa0 +#define ODM_REG_CLM_RESULT_11AC 0xfa4 +#define ODM_REG_NHM_CNT_11AC 0xfa8 +#define ODM_REG_NHM_DUR_READY_11AC 0xfb4 + +#define ODM_REG_NHM_CNT7_TO_CNT4_11AC 0xfac +#define ODM_REG_NHM_CNT11_TO_CNT8_11AC 0xfb0 +#define ODM_REG_OFDM_FA_TYPE2_11AC 0xFD0 +//PAGE 18 +#define ODM_REG_IGI_C_11AC 0x1850 +//PAGE 1A +#define ODM_REG_IGI_D_11AC 0x1A50 + +//2 MAC REG LIST +#define ODM_REG_RESP_TX_11AC 0x6D8 + + + +//DIG Related +#define ODM_BIT_IGI_11AC 0xFFFFFFFF +#define ODM_BIT_CCK_RPT_FORMAT_11AC BIT16 +#define ODM_BIT_BB_RX_PATH_11AC 0xF +#define ODM_BIT_BB_TX_PATH_11AC 0xF +#define ODM_BIT_BB_ATC_11AC BIT14 + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_regdefine11n.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_regdefine11n.h new file mode 100644 index 000000000..8826dfb20 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_regdefine11n.h @@ -0,0 +1,199 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __ODM_REGDEFINE11N_H__ +#define __ODM_REGDEFINE11N_H__ + + +//2 RF REG LIST +#define ODM_REG_RF_MODE_11N 0x00 +#define ODM_REG_RF_0B_11N 0x0B +#define ODM_REG_CHNBW_11N 0x18 +#define ODM_REG_T_METER_11N 0x24 +#define ODM_REG_RF_25_11N 0x25 +#define ODM_REG_RF_26_11N 0x26 +#define ODM_REG_RF_27_11N 0x27 +#define ODM_REG_RF_2B_11N 0x2B +#define ODM_REG_RF_2C_11N 0x2C +#define ODM_REG_RXRF_A3_11N 0x3C +#define ODM_REG_T_METER_92D_11N 0x42 +#define ODM_REG_T_METER_88E_11N 0x42 + + + +//2 BB REG LIST +//PAGE 8 +#define ODM_REG_BB_CTRL_11N 0x800 +#define ODM_REG_RF_PIN_11N 0x804 +#define ODM_REG_PSD_CTRL_11N 0x808 +#define ODM_REG_TX_ANT_CTRL_11N 0x80C +#define ODM_REG_BB_PWR_SAV5_11N 0x818 +#define ODM_REG_CCK_RPT_FORMAT_11N 0x824 +#define ODM_REG_CCK_RPT_FORMAT_11N_B 0x82C +#define ODM_REG_RX_DEFUALT_A_11N 0x858 +#define ODM_REG_RX_DEFUALT_B_11N 0x85A +#define ODM_REG_BB_PWR_SAV3_11N 0x85C +#define ODM_REG_ANTSEL_CTRL_11N 0x860 +#define ODM_REG_RX_ANT_CTRL_11N 0x864 +#define ODM_REG_PIN_CTRL_11N 0x870 +#define ODM_REG_BB_PWR_SAV1_11N 0x874 +#define ODM_REG_ANTSEL_PATH_11N 0x878 +#define ODM_REG_BB_3WIRE_11N 0x88C +#define ODM_REG_SC_CNT_11N 0x8C4 +#define ODM_REG_PSD_DATA_11N 0x8B4 +#define ODM_REG_PSD_DATA_11N 0x8B4 +#define ODM_REG_NHM_TIMER_11N 0x894 +#define ODM_REG_CLM_TIME_PERIOD_11N 0x894 +#define ODM_REG_NHM_TH9_TH10_11N 0x890 +#define ODM_REG_CLM_11N 0x890 +#define ODM_REG_NHM_TH3_TO_TH0_11N 0x898 +#define ODM_REG_NHM_TH7_TO_TH4_11N 0x89c +#define ODM_REG_NHM_TH8_11N 0xe28 +#define ODM_REG_CLM_READY_11N 0x8b4 +#define ODM_REG_CLM_RESULT_11N 0x8d0 +#define ODM_REG_NHM_CNT_11N 0x8d8 + +// For ACS, Jeffery, 2014-12-26 +#define ODM_REG_NHM_CNT7_TO_CNT4_11N 0x8dc +#define ODM_REG_NHM_CNT9_TO_CNT8_11N 0x8d0 +#define ODM_REG_NHM_CNT10_11N 0x8d4 + + + +//PAGE 9 +#define ODM_REG_DBG_RPT_11N 0x908 +#define ODM_REG_BB_TX_PATH_11N 0x90c +#define ODM_REG_ANT_MAPPING1_11N 0x914 +#define ODM_REG_ANT_MAPPING2_11N 0x918 +#define ODM_REG_EDCCA_DOWN_OPT_11N 0x948 + +//PAGE A +#define ODM_REG_CCK_ANTDIV_PARA1_11N 0xA00 +#define ODM_REG_CCK_CCA_11N 0xA0A +#define ODM_REG_CCK_ANTDIV_PARA2_11N 0xA0C +#define ODM_REG_CCK_ANTDIV_PARA3_11N 0xA10 +#define ODM_REG_CCK_ANTDIV_PARA4_11N 0xA14 +#define ODM_REG_CCK_FILTER_PARA1_11N 0xA22 +#define ODM_REG_CCK_FILTER_PARA2_11N 0xA23 +#define ODM_REG_CCK_FILTER_PARA3_11N 0xA24 +#define ODM_REG_CCK_FILTER_PARA4_11N 0xA25 +#define ODM_REG_CCK_FILTER_PARA5_11N 0xA26 +#define ODM_REG_CCK_FILTER_PARA6_11N 0xA27 +#define ODM_REG_CCK_FILTER_PARA7_11N 0xA28 +#define ODM_REG_CCK_FILTER_PARA8_11N 0xA29 +#define ODM_REG_CCK_FA_RST_11N 0xA2C +#define ODM_REG_CCK_FA_MSB_11N 0xA58 +#define ODM_REG_CCK_FA_LSB_11N 0xA5C +#define ODM_REG_CCK_CCA_CNT_11N 0xA60 +#define ODM_REG_BB_PWR_SAV4_11N 0xA74 +//PAGE B +#define ODM_REG_LNA_SWITCH_11N 0xB2C +#define ODM_REG_PATH_SWITCH_11N 0xB30 +#define ODM_REG_RSSI_CTRL_11N 0xB38 +#define ODM_REG_CONFIG_ANTA_11N 0xB68 +#define ODM_REG_RSSI_BT_11N 0xB9C +//PAGE C +#define ODM_REG_OFDM_FA_HOLDC_11N 0xC00 +#define ODM_REG_BB_RX_PATH_11N 0xC04 +#define ODM_REG_TRMUX_11N 0xC08 +#define ODM_REG_OFDM_FA_RSTC_11N 0xC0C +#define ODM_REG_RXIQI_MATRIX_11N 0xC14 +#define ODM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C +#define ODM_REG_IGI_A_11N 0xC50 +#define ODM_REG_ANTDIV_PARA2_11N 0xC54 +#define ODM_REG_IGI_B_11N 0xC58 +#define ODM_REG_ANTDIV_PARA3_11N 0xC5C +#define ODM_REG_L1SBD_PD_CH_11N 0XC6C +#define ODM_REG_BB_PWR_SAV2_11N 0xC70 +#define ODM_REG_RX_OFF_11N 0xC7C +#define ODM_REG_TXIQK_MATRIXA_11N 0xC80 +#define ODM_REG_TXIQK_MATRIXB_11N 0xC88 +#define ODM_REG_TXIQK_MATRIXA_LSB2_11N 0xC94 +#define ODM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C +#define ODM_REG_RXIQK_MATRIX_LSB_11N 0xCA0 +#define ODM_REG_ANTDIV_PARA1_11N 0xCA4 +#define ODM_REG_OFDM_FA_TYPE1_11N 0xCF0 +//PAGE D +#define ODM_REG_OFDM_FA_RSTD_11N 0xD00 +#define ODM_REG_BB_ATC_11N 0xD2C +#define ODM_REG_OFDM_FA_TYPE2_11N 0xDA0 +#define ODM_REG_OFDM_FA_TYPE3_11N 0xDA4 +#define ODM_REG_OFDM_FA_TYPE4_11N 0xDA8 +#define ODM_REG_RPT_11N 0xDF4 +//PAGE E +#define ODM_REG_TXAGC_A_6_18_11N 0xE00 +#define ODM_REG_TXAGC_A_24_54_11N 0xE04 +#define ODM_REG_TXAGC_A_1_MCS32_11N 0xE08 +#define ODM_REG_TXAGC_A_MCS0_3_11N 0xE10 +#define ODM_REG_TXAGC_A_MCS4_7_11N 0xE14 +#define ODM_REG_TXAGC_A_MCS8_11_11N 0xE18 +#define ODM_REG_TXAGC_A_MCS12_15_11N 0xE1C +#define ODM_REG_EDCCA_DCNF_11N 0xE24 +#define ODM_REG_FPGA0_IQK_11N 0xE28 +#define ODM_REG_TXIQK_TONE_A_11N 0xE30 +#define ODM_REG_RXIQK_TONE_A_11N 0xE34 +#define ODM_REG_TXIQK_PI_A_11N 0xE38 +#define ODM_REG_RXIQK_PI_A_11N 0xE3C +#define ODM_REG_TXIQK_11N 0xE40 +#define ODM_REG_RXIQK_11N 0xE44 +#define ODM_REG_IQK_AGC_PTS_11N 0xE48 +#define ODM_REG_IQK_AGC_RSP_11N 0xE4C +#define ODM_REG_BLUETOOTH_11N 0xE6C +#define ODM_REG_RX_WAIT_CCA_11N 0xE70 +#define ODM_REG_TX_CCK_RFON_11N 0xE74 +#define ODM_REG_TX_CCK_BBON_11N 0xE78 +#define ODM_REG_OFDM_RFON_11N 0xE7C +#define ODM_REG_OFDM_BBON_11N 0xE80 +#define ODM_REG_TX2RX_11N 0xE84 +#define ODM_REG_TX2TX_11N 0xE88 +#define ODM_REG_RX_CCK_11N 0xE8C +#define ODM_REG_RX_OFDM_11N 0xED0 +#define ODM_REG_RX_WAIT_RIFS_11N 0xED4 +#define ODM_REG_RX2RX_11N 0xED8 +#define ODM_REG_STANDBY_11N 0xEDC +#define ODM_REG_SLEEP_11N 0xEE0 +#define ODM_REG_PMPD_ANAEN_11N 0xEEC +#define ODM_REG_IGI_C_11N 0xF84 +#define ODM_REG_IGI_D_11N 0xF88 + +//2 MAC REG LIST +#define ODM_REG_BB_RST_11N 0x02 +#define ODM_REG_ANTSEL_PIN_11N 0x4C +#define ODM_REG_EARLY_MODE_11N 0x4D0 +#define ODM_REG_RSSI_MONITOR_11N 0x4FE +#define ODM_REG_EDCA_VO_11N 0x500 +#define ODM_REG_EDCA_VI_11N 0x504 +#define ODM_REG_EDCA_BE_11N 0x508 +#define ODM_REG_EDCA_BK_11N 0x50C +#define ODM_REG_TXPAUSE_11N 0x522 +#define ODM_REG_RESP_TX_11N 0x6D8 +#define ODM_REG_ANT_TRAIN_PARA1_11N 0x7b0 +#define ODM_REG_ANT_TRAIN_PARA2_11N 0x7b4 + + +//DIG Related +#define ODM_BIT_IGI_11N 0x0000007F +#define ODM_BIT_CCK_RPT_FORMAT_11N BIT9 +#define ODM_BIT_BB_RX_PATH_11N 0xF +#define ODM_BIT_BB_TX_PATH_11N 0xF +#define ODM_BIT_BB_ATC_11N BIT11 + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_rxhp.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_rxhp.c new file mode 100644 index 000000000..9451d5523 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_rxhp.c @@ -0,0 +1,1692 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +//============================================================ +// include files +//============================================================ +#include "mp_precomp.h" +#include "phydm_precomp.h" + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +#define AFH_PSD 1 //0:normal PSD scan, 1: only do 20 pts PSD +#define MODE_40M 0 //0:20M, 1:40M +#define PSD_TH2 3 +#define PSD_CHMIN 20 // Minimum channel number for BT AFH +#define SIR_STEP_SIZE 3 +#define Smooth_Size_1 5 +#define Smooth_TH_1 3 +#define Smooth_Size_2 10 +#define Smooth_TH_2 4 +#define Smooth_Size_3 20 +#define Smooth_TH_3 4 +#define Smooth_Step_Size 5 +#define Adaptive_SIR 1 +#define SCAN_INTERVAL 1500 //ms +#define SYN_Length 5 // for 92D + +#define LNA_Low_Gain_1 0x64 +#define LNA_Low_Gain_2 0x5A +#define LNA_Low_Gain_3 0x58 + +#define pw_th_10dB 0x0 +#define pw_th_16dB 0x3 + +#define FA_RXHP_TH1 5000 +#define FA_RXHP_TH2 1500 +#define FA_RXHP_TH3 800 +#define FA_RXHP_TH4 600 +#define FA_RXHP_TH5 500 + +#define Idle_Mode 0 +#define High_TP_Mode 1 +#define Low_TP_Mode 2 + + +VOID +odm_PSDMonitorInit( + IN PVOID pDM_VOID + ) +{ +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)|(DEV_BUS_TYPE == RT_USB_INTERFACE) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + //PSD Monitor Setting + //Which path in ADC/DAC is turnned on for PSD: both I/Q + ODM_SetBBReg(pDM_Odm, ODM_PSDREG, BIT10|BIT11, 0x3); + //Ageraged number: 8 + ODM_SetBBReg(pDM_Odm, ODM_PSDREG, BIT12|BIT13, 0x1); + pDM_Odm->bPSDinProcess = FALSE; + pDM_Odm->bUserAssignLevel = FALSE; + pDM_Odm->bPSDactive = FALSE; + //pDM_Odm->bDMInitialGainEnable=TRUE; //change the initialization to DIGinit + //Set Debug Port + //PHY_SetBBReg(Adapter, 0x908, bMaskDWord, 0x803); + //PHY_SetBBReg(Adapter, 0xB34, bMaskByte0, 0x00); // pause PSD + //PHY_SetBBReg(Adapter, 0xB38, bMaskByte0, 10); //rescan + //PHY_SetBBReg(Adapter, 0xB38, bMaskByte2|bMaskByte3, 100); //interval + + //PlatformSetTimer( Adapter, &pHalData->PSDTriggerTimer, 0); //ms +#endif +} + +VOID +PatchDCTone( + IN PVOID pDM_VOID, + pu4Byte PSD_report, + u1Byte initial_gain_psd +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + //PADAPTER pAdapter; + + u4Byte psd_report; + + //2 Switch to CH11 to patch CH9 and CH13 DC tone + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, 11); + + if(pDM_Odm->SupportICType== ODM_RTL8192D) + { + if((*(pDM_Odm->pMacPhyMode) == ODM_SMSP)||(*(pDM_Odm->pMacPhyMode) == ODM_DMSP)) + { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_CHNLBW, 0x3FF, 11); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x25, 0xfffff, 0x643BC); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x26, 0xfffff, 0xFC038); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x27, 0xfffff, 0x77C1A); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2B, 0xfffff, 0x41289); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2C, 0xfffff, 0x01840); + } + else + { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x25, 0xfffff, 0x643BC); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x26, 0xfffff, 0xFC038); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x27, 0xfffff, 0x77C1A); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2B, 0xfffff, 0x41289); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2C, 0xfffff, 0x01840); + } + } + + //Ch9 DC tone patch + psd_report = GetPSDData(pDM_Odm, 96, initial_gain_psd); + PSD_report[50] = psd_report; + //Ch13 DC tone patch + psd_report = GetPSDData(pDM_Odm, 32, initial_gain_psd); + PSD_report[70] = psd_report; + + //2 Switch to CH3 to patch CH1 and CH5 DC tone + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, 3); + + + if(pDM_Odm->SupportICType==ODM_RTL8192D) + { + if((*(pDM_Odm->pMacPhyMode) == ODM_SMSP)||(*(pDM_Odm->pMacPhyMode) == ODM_DMSP)) + { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_CHNLBW, 0x3FF, 3); + //PHY_SetRFReg(Adapter, ODM_RF_PATH_B, 0x25, 0xfffff, 0x643BC); + //PHY_SetRFReg(Adapter, ODM_RF_PATH_B, 0x26, 0xfffff, 0xFC038); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x27, 0xfffff, 0x07C1A); + //PHY_SetRFReg(Adapter, ODM_RF_PATH_B, 0x2B, 0xfffff, 0x61289); + //PHY_SetRFReg(Adapter, ODM_RF_PATH_B, 0x2C, 0xfffff, 0x01C41); + } + else + { + //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x25, 0xfffff, 0x643BC); + //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x26, 0xfffff, 0xFC038); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x27, 0xfffff, 0x07C1A); + //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x2B, 0xfffff, 0x61289); + //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x2C, 0xfffff, 0x01C41); + } + } + + //Ch1 DC tone patch + psd_report = GetPSDData(pDM_Odm, 96, initial_gain_psd); + PSD_report[10] = psd_report; + //Ch5 DC tone patch + psd_report = GetPSDData(pDM_Odm, 32, initial_gain_psd); + PSD_report[30] = psd_report; + +} + + +VOID +GoodChannelDecision( + IN PVOID pDM_VOID, + pu4Byte PSD_report, + pu1Byte PSD_bitmap, + u1Byte RSSI_BT, + pu1Byte PSD_bitmap_memory) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table; + //s4Byte TH1 = SSBT-0x15; // modify TH by Neil Chen + s4Byte TH1= RSSI_BT+0x14; + s4Byte TH2 = RSSI_BT+85; + //u2Byte TH3; +// s4Byte RegB34; + u1Byte bitmap, Smooth_size[3], Smooth_TH[3]; + //u1Byte psd_bit; + u4Byte i,n,j, byte_idx, bit_idx, good_cnt, good_cnt_smoothing, Smooth_Interval[3]; + int start_byte_idx,start_bit_idx,cur_byte_idx, cur_bit_idx,NOW_byte_idx ; + +// RegB34 = PHY_QueryBBReg(Adapter,0xB34, bMaskDWord)&0xFF; + + if((pDM_Odm->SupportICType == ODM_RTL8192C)||(pDM_Odm->SupportICType == ODM_RTL8192D)) + { + TH1 = RSSI_BT + 0x14; + } + + Smooth_size[0]=Smooth_Size_1; + Smooth_size[1]=Smooth_Size_2; + Smooth_size[2]=Smooth_Size_3; + Smooth_TH[0]=Smooth_TH_1; + Smooth_TH[1]=Smooth_TH_2; + Smooth_TH[2]=Smooth_TH_3; + Smooth_Interval[0]=16; + Smooth_Interval[1]=15; + Smooth_Interval[2]=13; + good_cnt = 0; + if(pDM_Odm->SupportICType==ODM_RTL8723A) + { + //2 Threshold + + if(RSSI_BT >=41) + TH1 = 113; + else if(RSSI_BT >=38) // >= -15dBm + TH1 = 105; //0x69 + else if((RSSI_BT >=33)&(RSSI_BT <38)) + TH1 = 99+(RSSI_BT-33); //0x63 + else if((RSSI_BT >=26)&(RSSI_BT<33)) + TH1 = 99-(33-RSSI_BT)+2; //0x5e + else if((RSSI_BT >=24)&(RSSI_BT<26)) + TH1 = 88-((RSSI_BT-24)*3); //0x58 + else if((RSSI_BT >=18)&(RSSI_BT<24)) + TH1 = 77+((RSSI_BT-18)*2); + else if((RSSI_BT >=14)&(RSSI_BT<18)) + TH1 = 63+((RSSI_BT-14)*2); + else if((RSSI_BT >=8)&(RSSI_BT<14)) + TH1 = 58+((RSSI_BT-8)*2); + else if((RSSI_BT >=3)&(RSSI_BT<8)) + TH1 = 52+(RSSI_BT-3); + else + TH1 = 51; + } + + for (i = 0; i< 10; i++) + PSD_bitmap[i] = 0; + + + // Add By Gary + for (i=0; i<80; i++) + pRX_HP_Table->PSD_bitmap_RXHP[i] = 0; + // End + + + + if(pDM_Odm->SupportICType==ODM_RTL8723A) + { + TH1 =TH1-SIR_STEP_SIZE; + } + while (good_cnt < PSD_CHMIN) + { + good_cnt = 0; + if(pDM_Odm->SupportICType==ODM_RTL8723A) + { + if(TH1 ==TH2) + break; + if((TH1+SIR_STEP_SIZE) < TH2) + TH1 += SIR_STEP_SIZE; + else + TH1 = TH2; + } + else + { + if(TH1==(RSSI_BT+0x1E)) + break; + if((TH1+2) < (RSSI_BT+0x1E)) + TH1+=3; + else + TH1 = RSSI_BT+0x1E; + + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD,DBG_LOUD,("PSD: decision threshold is: %d", TH1)); + + for (i = 0; i< 80; i++) + { + if((s4Byte)(PSD_report[i]) < TH1) + { + byte_idx = i / 8; + bit_idx = i -8*byte_idx; + bitmap = PSD_bitmap[byte_idx]; + PSD_bitmap[byte_idx] = bitmap | (u1Byte) (1 << bit_idx); + } + } + +#if DBG + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: before smoothing\n")); + for(n=0;n<10;n++) + { + //DbgPrint("PSD_bitmap[%u]=%x\n", n, PSD_bitmap[n]); + for (i = 0; i<8; i++) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD_bitmap[%u] = %d\n", 2402+n*8+i, (PSD_bitmap[n]&BIT(i))>>i)); + } +#endif + + //1 Start of smoothing function + + for (j=0;j<3;j++) + { + start_byte_idx=0; + start_bit_idx=0; + for(n=0; n 7 ) + { + start_byte_idx= start_byte_idx+start_bit_idx/8; + start_bit_idx = start_bit_idx%8; + } + } + + ODM_RT_TRACE( pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: after %u smoothing", j+1)); + for(n=0;n<10;n++) + { + for (i = 0; i<8; i++) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD_bitmap[%u] = %d\n", 2402+n*8+i, (PSD_bitmap[n]&BIT(i))>>i)); + + if ( ((PSD_bitmap[n]&BIT(i))>>i) ==1) //----- Add By Gary + { + pRX_HP_Table->PSD_bitmap_RXHP[8*n+i] = 1; + } // ------end by Gary + } + } + + } + + + good_cnt = 0; + for ( i = 0; i < 10; i++) + { + for (n = 0; n < 8; n++) + if((PSD_bitmap[i]& BIT(n)) != 0) + good_cnt++; + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, ODM_COMP_PSD,("PSD: good channel cnt = %u",good_cnt)); + } + + //RT_TRACE(ODM_COMP_PSD, DBG_LOUD,("PSD: SSBT=%d, TH2=%d, TH1=%d",SSBT,TH2,TH1)); + for (i = 0; i <10; i++) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: PSD_bitmap[%u]=%x",i,PSD_bitmap[i])); +/* + //Update bitmap memory + for(i = 0; i < 80; i++) + { + byte_idx = i / 8; + bit_idx = i -8*byte_idx; + psd_bit = (PSD_bitmap[byte_idx] & BIT(bit_idx)) >> bit_idx; + bitmap = PSD_bitmap_memory[i]; + PSD_bitmap_memory[i] = (bitmap << 1) |psd_bit; + } +*/ +} + + + +VOID +odm_PSD_Monitor( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + //PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + unsigned int pts, start_point, stop_point; + u1Byte initial_gain ; + static u1Byte PSD_bitmap_memory[80], init_memory = 0; + static u1Byte psd_cnt=0; + static u4Byte PSD_report[80], PSD_report_tmp; + static u8Byte lastTxOkCnt=0, lastRxOkCnt=0; + u1Byte H2C_PSD_DATA[5]={0,0,0,0,0}; + static u1Byte H2C_PSD_DATA_last[5] ={0,0,0,0,0}; + u1Byte idx[20]={96,99,102,106,109,112,115,118,122,125, + 0,3,6,10,13,16,19,22,26,29}; + u1Byte n, i, channel, BBReset,tone_idx; + u1Byte PSD_bitmap[10], SSBT=0,initial_gain_psd=0, RSSI_BT=0, initialGainUpper; + s4Byte PSD_skip_start, PSD_skip_stop; + u4Byte CurrentChannel, RXIQI, RxIdleLowPwr, wlan_channel; + u4Byte ReScan, Interval, Is40MHz; + u8Byte curTxOkCnt, curRxOkCnt; + int cur_byte_idx, cur_bit_idx; + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; + + + if(*pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("pbDriverIsGoingToPnpSetPowerSleep!!!!!!!!!!!!!!!\n")); + return; + } + + + if( (*(pDM_Odm->pbScanInProcess)) || + pDM_Odm->bLinkInProcess) + { + if((pDM_Odm->SupportICType==ODM_RTL8723A)&(pDM_Odm->SupportInterface==ODM_ITRF_PCIE)) + { + ODM_SetTimer( pDM_Odm, &pDM_Odm->PSDTimer, 1500); //ms + //psd_cnt=0; + } + return; + } + + if(pDM_Odm->bBtHsOperation) + { + ReScan = 1; + Interval = SCAN_INTERVAL; + } + else + { + ReScan = PSD_RESCAN; + Interval = SCAN_INTERVAL; + } + + //1 Initialization + if(init_memory == 0) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Init memory\n")); + for(i = 0; i < 80; i++) + PSD_bitmap_memory[i] = 0xFF; // channel is always good + init_memory = 1; + } + if(psd_cnt == 0) + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Enter dm_PSD_Monitor\n")); + for(i = 0; i < 80; i++) + PSD_report[i] = 0; + } + + //1 Backup Current Settings + CurrentChannel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); +/* + if(pDM_Odm->SupportICType==ODM_RTL8192D) + { + //2 Record Current synthesizer parameters based on current channel + if((*pDM_Odm->MacPhyMode92D == SINGLEMAC_SINGLEPHY)||(*pDM_Odm->MacPhyMode92D == DUALMAC_SINGLEPHY)) + { + SYN_RF25 = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x25, bMaskDWord); + SYN_RF26 = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x26, bMaskDWord); + SYN_RF27 = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x27, bMaskDWord); + SYN_RF2B = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x2B, bMaskDWord); + SYN_RF2C = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x2C, bMaskDWord); + } + else // DualMAC_DualPHY 2G + { + SYN_RF25 = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x25, bMaskDWord); + SYN_RF26 = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x26, bMaskDWord); + SYN_RF27 = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x27, bMaskDWord); + SYN_RF2B = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x2B, bMaskDWord); + SYN_RF2C = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x2C, bMaskDWord); + } + } +*/ + //RXIQI = PHY_QueryBBReg(Adapter, 0xC14, bMaskDWord); + RXIQI = ODM_GetBBReg(pDM_Odm, 0xC14, bMaskDWord); + + //RxIdleLowPwr = (PHY_QueryBBReg(Adapter, 0x818, bMaskDWord)&BIT28)>>28; + RxIdleLowPwr = (ODM_GetBBReg(pDM_Odm, 0x818, bMaskDWord)&BIT28)>>28; + + //2??? + if(CHNL_RUN_ABOVE_40MHZ(pMgntInfo)) + Is40MHz = TRUE; + else + Is40MHz = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_PSD, DBG_LOUD,("PSD Scan Start\n")); + //1 Turn off CCK + //PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT24, 0); + ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0); + //1 Turn off TX + //Pause TX Queue + //PlatformEFIOWrite1Byte(Adapter, REG_TXPAUSE, 0xFF); + ODM_Write1Byte(pDM_Odm,REG_TXPAUSE, 0xFF); + + //Force RX to stop TX immediately + //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13); + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13); + //1 Turn off RX + //Rx AGC off RegC70[0]=0, RegC7C[20]=0 + //PHY_SetBBReg(Adapter, 0xC70, BIT0, 0); + //PHY_SetBBReg(Adapter, 0xC7C, BIT20, 0); + + ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 0); + ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 0); + + + //Turn off CCA + //PHY_SetBBReg(Adapter, 0xC14, bMaskDWord, 0x0); + ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0); + + //BB Reset + //BBReset = PlatformEFIORead1Byte(Adapter, 0x02); + BBReset = ODM_Read1Byte(pDM_Odm, 0x02); + + //PlatformEFIOWrite1Byte(Adapter, 0x02, BBReset&(~BIT0)); + //PlatformEFIOWrite1Byte(Adapter, 0x02, BBReset|BIT0); + ODM_SetBBReg(pDM_Odm, 0x87C, BIT31, 1); //clock gated to prevent from AGC table mess + ODM_Write1Byte(pDM_Odm, 0x02, BBReset&(~BIT0)); + ODM_Write1Byte(pDM_Odm, 0x02, BBReset|BIT0); + ODM_SetBBReg(pDM_Odm, 0x87C, BIT31, 0); + + //1 Leave RX idle low power + //PHY_SetBBReg(Adapter, 0x818, BIT28, 0x0); + + ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); + //1 Fix initial gain + //if (IS_HARDWARE_TYPE_8723AE(Adapter)) + //RSSI_BT = pHalData->RSSI_BT; + //else if((IS_HARDWARE_TYPE_8192C(Adapter))||(IS_HARDWARE_TYPE_8192D(Adapter))) // Add by Gary + // RSSI_BT = RSSI_BT_new; + + if((pDM_Odm->SupportICType==ODM_RTL8723A)&(pDM_Odm->SupportInterface==ODM_ITRF_PCIE)) + RSSI_BT=pDM_Odm->RSSI_BT; //need to check C2H to pDM_Odm RSSI BT + + if(RSSI_BT>=47) + RSSI_BT=47; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT)); + + if(pDM_Odm->SupportICType==ODM_RTL8723A) + { + //Neil add--2011--10--12 + //2 Initial Gain index + if(RSSI_BT >=35) // >= -15dBm + initial_gain_psd = RSSI_BT*2; + else if((RSSI_BT >=33)&(RSSI_BT<35)) + initial_gain_psd = RSSI_BT*2+6; + else if((RSSI_BT >=24)&(RSSI_BT<33)) + initial_gain_psd = 70-(33-RSSI_BT); + else if((RSSI_BT >=19)&(RSSI_BT<24)) + initial_gain_psd = 64-((24-RSSI_BT)*4); + else if((RSSI_BT >=14)&(RSSI_BT<19)) + initial_gain_psd = 44-((18-RSSI_BT)*2); + else if((RSSI_BT >=8)&(RSSI_BT<14)) + initial_gain_psd = 35-(14-RSSI_BT); + else + initial_gain_psd = 0x1B; + } + else + { + + //need to do + initial_gain_psd = pDM_Odm->RSSI_Min; // PSD report based on RSSI + //} + } + //if(RSSI_BT<0x17) + // RSSI_BT +=3; + //DbgPrint("PSD: RSSI_BT= %d\n", RSSI_BT); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT)); + + //initialGainUpper = 0x5E; //Modify by neil chen + + if(pDM_Odm->bUserAssignLevel) + { + pDM_Odm->bUserAssignLevel = FALSE; + initialGainUpper = 0x7f; + } + else + { + initialGainUpper = 0x5E; + } + + /* + if (initial_gain_psd < 0x1a) + initial_gain_psd = 0x1a; + if (initial_gain_psd > initialGainUpper) + initial_gain_psd = initialGainUpper; + */ + + //if(pDM_Odm->SupportICType==ODM_RTL8723A) + SSBT = RSSI_BT * 2 +0x3E; + + + //if(IS_HARDWARE_TYPE_8723AE(Adapter)) + // SSBT = RSSI_BT * 2 +0x3E; + //else if((IS_HARDWARE_TYPE_8192C(Adapter))||(IS_HARDWARE_TYPE_8192D(Adapter))) // Add by Gary + //{ + // RSSI_BT = initial_gain_psd; + // SSBT = RSSI_BT; + //} + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: SSBT= %d\n", SSBT)); + ODM_RT_TRACE( pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: initial gain= 0x%x\n", initial_gain_psd)); + //DbgPrint("PSD: SSBT= %d", SSBT); + //need to do + pDM_Odm->bDMInitialGainEnable = FALSE; + initial_gain =(u1Byte) (ODM_GetBBReg(pDM_Odm, 0xc50, bMaskDWord) & 0x7F); + + // make sure the initial gain is under the correct range. + //initial_gain_psd &= 0x7f; + ODM_Write_DIG(pDM_Odm, initial_gain_psd); + //1 Turn off 3-wire + ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0xF); + + //pts value = 128, 256, 512, 1024 + pts = 128; + + if(pts == 128) + { + ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0); + start_point = 64; + stop_point = 192; + } + else if(pts == 256) + { + ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x1); + start_point = 128; + stop_point = 384; + } + else if(pts == 512) + { + ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x2); + start_point = 256; + stop_point = 768; + } + else + { + ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x3); + start_point = 512; + stop_point = 1536; + } + + +//3 Skip WLAN channels if WLAN busy + + curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - lastTxOkCnt; + curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - lastRxOkCnt; + lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast); + lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast); + + PSD_skip_start=80; + PSD_skip_stop = 0; + wlan_channel = CurrentChannel & 0x0f; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD,DBG_LOUD,("PSD: current channel: %x, BW:%d \n", wlan_channel, Is40MHz)); + if(pDM_Odm->SupportICType==ODM_RTL8723A) + { + if(pDM_Odm->bBtHsOperation) + { + if(pDM_Odm->bLinked) + { + if(Is40MHz) + { + PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-2; // Modify by Neil to add 10 chs to mask + PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+4; + } + else + { + PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-10; // Modify by Neil to add 10 chs to mask + PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+18; + } + } + else + { + // mask for 40MHz + PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-2; // Modify by Neil to add 10 chs to mask + PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+4; + } + if(PSD_skip_start < 0) + PSD_skip_start = 0; + if(PSD_skip_stop >80) + PSD_skip_stop = 80; + } + else + { + if((curRxOkCnt+curTxOkCnt) > 5) + { + if(Is40MHz) + { + PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-2; // Modify by Neil to add 10 chs to mask + PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+4; + } + else + { + PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-10; // Modify by Neil to add 10 chs to mask + PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+18; + } + + if(PSD_skip_start < 0) + PSD_skip_start = 0; + if(PSD_skip_stop >80) + PSD_skip_stop = 80; + } + } + } +#if 0 + else + { + if((curRxOkCnt+curTxOkCnt) > 1000) + { + PSD_skip_start = (wlan_channel-1)*5 -Is40MHz*10; + PSD_skip_stop = PSD_skip_start + (1+Is40MHz)*20; + } + } +#endif //Reove RXHP Issue + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD,DBG_LOUD,("PSD: Skip tone from %d to %d \n", PSD_skip_start, PSD_skip_stop)); + + for (n=0;n<80;n++) + { + if((n%20)==0) + { + channel = (n/20)*4 + 1; + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, channel); + } + tone_idx = n%20; + if ((n>=PSD_skip_start) && (n PSD_report[n]) + PSD_report[n] = PSD_report_tmp; + + } + } + + PatchDCTone(pDM_Odm, PSD_report, initial_gain_psd); + + //----end + //1 Turn on RX + //Rx AGC on + ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 1); + ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 1); + //CCK on + ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 1); + //1 Turn on TX + //Resume TX Queue + + ODM_Write1Byte(pDM_Odm,REG_TXPAUSE, 0x00); + //Turn on 3-wire + ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0x0); + //1 Restore Current Settings + //Resume DIG + pDM_Odm->bDMInitialGainEnable = TRUE; + + ODM_Write_DIG(pDM_Odm, initial_gain); + + // restore originl center frequency + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel); + + //Turn on CCA + ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, RXIQI); + //Restore RX idle low power + if(RxIdleLowPwr == TRUE) + ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 1); + + psd_cnt++; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD:psd_cnt = %d \n",psd_cnt)); + if (psd_cnt < ReScan) + ODM_SetTimer(pDM_Odm, &pDM_Odm->PSDTimer, Interval); + else + { + psd_cnt = 0; + for(i=0;i<80;i++) + //DbgPrint("psd_report[%d]= %d \n", 2402+i, PSD_report[i]); + RT_TRACE( ODM_COMP_PSD, DBG_LOUD,("psd_report[%d]= %d \n", 2402+i, PSD_report[i])); + + + GoodChannelDecision(pDM_Odm, PSD_report, PSD_bitmap,RSSI_BT, PSD_bitmap_memory); + + if(pDM_Odm->SupportICType==ODM_RTL8723A) + { + cur_byte_idx=0; + cur_bit_idx=0; + + //2 Restore H2C PSD Data to Last Data + H2C_PSD_DATA_last[0] = H2C_PSD_DATA[0]; + H2C_PSD_DATA_last[1] = H2C_PSD_DATA[1]; + H2C_PSD_DATA_last[2] = H2C_PSD_DATA[2]; + H2C_PSD_DATA_last[3] = H2C_PSD_DATA[3]; + H2C_PSD_DATA_last[4] = H2C_PSD_DATA[4]; + + + //2 Translate 80bit channel map to 40bit channel + for ( i=0;i<5;i++) + { + for(n=0;n<8;n++) + { + cur_byte_idx = i*2 + n/4; + cur_bit_idx = (n%4)*2; + if ( ((PSD_bitmap[cur_byte_idx]& BIT(cur_bit_idx)) != 0) && ((PSD_bitmap[cur_byte_idx]& BIT(cur_bit_idx+1)) != 0)) + H2C_PSD_DATA[i] = H2C_PSD_DATA[i] | (u1Byte) (1 << n); + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("H2C_PSD_DATA[%d]=0x%x\n" ,i, H2C_PSD_DATA[i])); + } + + //3 To Compare the difference + for ( i=0;i<5;i++) + { + if(H2C_PSD_DATA[i] !=H2C_PSD_DATA_last[i]) + { + FillH2CCmd92C(Adapter, H2C_92C_PSD_RESULT, 5, H2C_PSD_DATA); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_PSD, DBG_LOUD,("Need to Update the AFH Map \n")); + break; + } + else + { + if(i==5) + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Not need to Update\n")); + } + } + if(pDM_Odm->bBtHsOperation) + { + ODM_SetTimer(pDM_Odm, &pDM_Odm->PSDTimer, 10000); + ODM_RT_TRACE( pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Leave dm_PSD_Monitor\n")); + } + else + { + ODM_SetTimer(pDM_Odm, &pDM_Odm->PSDTimer, 1500); + ODM_RT_TRACE( pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Leave dm_PSD_Monitor\n")); + } + } + } +} +/* +//Neil for Get BT RSSI +// Be Triggered by BT C2H CMD +VOID +ODM_PSDGetRSSI( + IN u1Byte RSSI_BT) +{ + + +} + +*/ + +VOID +ODM_PSDMonitor( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + //if(IS_HARDWARE_TYPE_8723AE(Adapter)) + + if(pDM_Odm->SupportICType == ODM_RTL8723A) //may need to add other IC type + { + if(pDM_Odm->SupportInterface==ODM_ITRF_PCIE) + { + if(!pDM_Odm->bBtEnabled) //need to check upper layer connection + { + pDM_Odm->bPSDactive=FALSE; + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD, ("odm_PSDMonitor, return for BT is disabled!!!\n")); + return; + } + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD, ("odm_PSDMonitor\n")); + //{ + pDM_Odm->bPSDinProcess = TRUE; + pDM_Odm->bPSDactive=TRUE; + odm_PSD_Monitor(pDM_Odm); + pDM_Odm->bPSDinProcess = FALSE; + } + } + +} +VOID +odm_PSDMonitorCallback( + PRT_TIMER pTimer +) +{ + PADAPTER Adapter = (PADAPTER)pTimer->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformScheduleWorkItem(&pHalData->PSDMonitorWorkitem); +} + +VOID +odm_PSDMonitorWorkItemCallback( + IN PVOID pContext + ) +{ + PADAPTER Adapter = (PADAPTER)pContext; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + ODM_PSDMonitor(pDM_Odm); +} + + + //cosa debug tool need to modify + +VOID +ODM_PSDDbgControl( + IN PADAPTER Adapter, + IN u4Byte mode, + IN u4Byte btRssi + ) +{ +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD, (" Monitor mode=%d, btRssi=%d\n", mode, btRssi)); + if(mode) + { + pDM_Odm->RSSI_BT = (u1Byte)btRssi; + pDM_Odm->bUserAssignLevel = TRUE; + ODM_SetTimer( pDM_Odm, &pDM_Odm->PSDTimer, 0); //ms + } + else + { + ODM_CancelTimer(pDM_Odm, &pDM_Odm->PSDTimer); + } +#endif +} + + +//#if(DEV_BUS_TYPE == RT_PCI_INTERFACE)|(DEV_BUS_TYPE == RT_USB_INTERFACE) + +void odm_RXHPInit( + IN PVOID pDM_VOID) +{ +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE)|(DEV_BUS_TYPE == RT_USB_INTERFACE) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table; + u1Byte index; + + pRX_HP_Table->RXHP_enable = TRUE; + pRX_HP_Table->RXHP_flag = 0; + pRX_HP_Table->PSD_func_trigger = 0; + pRX_HP_Table->Pre_IGI = 0x20; + pRX_HP_Table->Cur_IGI = 0x20; + pRX_HP_Table->Cur_pw_th = pw_th_10dB; + pRX_HP_Table->Pre_pw_th = pw_th_10dB; + for(index=0; index<80; index++) + pRX_HP_Table->PSD_bitmap_RXHP[index] = 1; + +#if(DEV_BUS_TYPE == RT_USB_INTERFACE) + pRX_HP_Table->TP_Mode = Idle_Mode; +#endif +#endif +} + +VOID +odm_PSD_RXHP( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table; + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + unsigned int pts, start_point, stop_point, initial_gain ; + static u1Byte PSD_bitmap_memory[80], init_memory = 0; + static u1Byte psd_cnt=0; + static u4Byte PSD_report[80], PSD_report_tmp; + static u8Byte lastTxOkCnt=0, lastRxOkCnt=0; + u1Byte idx[20]={96,99,102,106,109,112,115,118,122,125, + 0,3,6,10,13,16,19,22,26,29}; + u1Byte n, i, channel, BBReset,tone_idx; + u1Byte PSD_bitmap[10]/*, SSBT=0*/,initial_gain_psd=0, RSSI_BT=0, initialGainUpper; + s4Byte PSD_skip_start, PSD_skip_stop; + u4Byte CurrentChannel, RXIQI, RxIdleLowPwr, wlan_channel; + u4Byte ReScan, Interval, Is40MHz; + u8Byte curTxOkCnt, curRxOkCnt; + //--------------2G band synthesizer for 92D switch RF channel using----------------- + u1Byte group_idx=0; + u4Byte SYN_RF25=0, SYN_RF26=0, SYN_RF27=0, SYN_RF2B=0, SYN_RF2C=0; + u4Byte SYN[5] = {0x25, 0x26, 0x27, 0x2B, 0x2C}; // synthesizer RF register for 2G channel + u4Byte SYN_group[3][5] = {{0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840}, // For CH1,2,4,9,10.11.12 {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840} + {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840}, // For CH3,13,14 + {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}}; // For Ch5,6,7,8 + //--------------------- Add by Gary for Debug setting ---------------------- + u1Byte RSSI_BT_new = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xB9C, 0xFF); + u1Byte rssi_ctrl = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xB38, 0xFF); + //--------------------------------------------------------------------- + + if(pMgntInfo->bScanInProgress) + { + return; + } + + ReScan = PSD_RESCAN; + Interval = SCAN_INTERVAL; + + + //1 Initialization + if(init_memory == 0) + { + RT_TRACE( ODM_COMP_PSD, DBG_LOUD,("Init memory\n")); + for(i = 0; i < 80; i++) + PSD_bitmap_memory[i] = 0xFF; // channel is always good + init_memory = 1; + } + if(psd_cnt == 0) + { + RT_TRACE(ODM_COMP_PSD, DBG_LOUD,("Enter dm_PSD_Monitor\n")); + for(i = 0; i < 80; i++) + PSD_report[i] = 0; + } + + //1 Backup Current Settings + CurrentChannel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); + if(pDM_Odm->SupportICType == ODM_RTL8192D) + { + //2 Record Current synthesizer parameters based on current channel + if((*(pDM_Odm->pMacPhyMode)==ODM_SMSP)||(*(pDM_Odm->pMacPhyMode)==ODM_DMSP)) + { + SYN_RF25 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x25, bMaskDWord); + SYN_RF26 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x26, bMaskDWord); + SYN_RF27 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x27, bMaskDWord); + SYN_RF2B = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2B, bMaskDWord); + SYN_RF2C = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2C, bMaskDWord); + } + else // DualMAC_DualPHY 2G + { + SYN_RF25 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x25, bMaskDWord); + SYN_RF26 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x26, bMaskDWord); + SYN_RF27 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x27, bMaskDWord); + SYN_RF2B = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2B, bMaskDWord); + SYN_RF2C = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2C, bMaskDWord); + } + } + RXIQI = ODM_GetBBReg(pDM_Odm, 0xC14, bMaskDWord); + RxIdleLowPwr = (ODM_GetBBReg(pDM_Odm, 0x818, bMaskDWord)&BIT28)>>28; + Is40MHz = *(pDM_Odm->pBandWidth); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_PSD, DBG_LOUD,("PSD Scan Start\n")); + //1 Turn off CCK + ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0); + //1 Turn off TX + //Pause TX Queue + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); + //Force RX to stop TX immediately + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13); + //1 Turn off RX + //Rx AGC off RegC70[0]=0, RegC7C[20]=0 + ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 0); + ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 0); + //Turn off CCA + ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0); + //BB Reset + ODM_SetBBReg(pDM_Odm, 0x87C, BIT31, 1); //clock gated to prevent from AGC table mess + BBReset = ODM_Read1Byte(pDM_Odm, 0x02); + ODM_Write1Byte(pDM_Odm, 0x02, BBReset&(~BIT0)); + ODM_Write1Byte(pDM_Odm, 0x02, BBReset|BIT0); + ODM_SetBBReg(pDM_Odm, 0x87C, BIT31, 0); + //1 Leave RX idle low power + ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); + //1 Fix initial gain + RSSI_BT = RSSI_BT_new; + RT_TRACE(ODM_COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT)); + + if(rssi_ctrl == 1) // just for debug!! + initial_gain_psd = RSSI_BT_new; + else + initial_gain_psd = pDM_Odm->RSSI_Min; // PSD report based on RSSI + + RT_TRACE(ODM_COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT)); + + initialGainUpper = 0x54; + + RSSI_BT = initial_gain_psd; + //SSBT = RSSI_BT; + + //RT_TRACE( ODM_COMP_PSD, DBG_LOUD,("PSD: SSBT= %d\n", SSBT)); + RT_TRACE( ODM_COMP_PSD, DBG_LOUD,("PSD: initial gain= 0x%x\n", initial_gain_psd)); + + pDM_Odm->bDMInitialGainEnable = FALSE; + initial_gain = ODM_GetBBReg(pDM_Odm, 0xc50, bMaskDWord) & 0x7F; + //ODM_SetBBReg(pDM_Odm, 0xc50, 0x7F, initial_gain_psd); + ODM_Write_DIG(pDM_Odm, initial_gain_psd); + //1 Turn off 3-wire + ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0xF); + + //pts value = 128, 256, 512, 1024 + pts = 128; + + if(pts == 128) + { + ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0); + start_point = 64; + stop_point = 192; + } + else if(pts == 256) + { + ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x1); + start_point = 128; + stop_point = 384; + } + else if(pts == 512) + { + ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x2); + start_point = 256; + stop_point = 768; + } + else + { + ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x3); + start_point = 512; + stop_point = 1536; + } + + +//3 Skip WLAN channels if WLAN busy + curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - lastTxOkCnt; + curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - lastRxOkCnt; + lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast); + lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast); + + PSD_skip_start=80; + PSD_skip_stop = 0; + wlan_channel = CurrentChannel & 0x0f; + + RT_TRACE(ODM_COMP_PSD,DBG_LOUD,("PSD: current channel: %x, BW:%d \n", wlan_channel, Is40MHz)); + + if((curRxOkCnt+curTxOkCnt) > 1000) + { + PSD_skip_start = (wlan_channel-1)*5 -Is40MHz*10; + PSD_skip_stop = PSD_skip_start + (1+Is40MHz)*20; + } + + RT_TRACE(ODM_COMP_PSD,DBG_LOUD,("PSD: Skip tone from %d to %d \n", PSD_skip_start, PSD_skip_stop)); + + for (n=0;n<80;n++) + { + if((n%20)==0) + { + channel = (n/20)*4 + 1; + if(pDM_Odm->SupportICType == ODM_RTL8192D) + { + switch(channel) + { + case 1: + case 9: + group_idx = 0; + break; + case 5: + group_idx = 2; + break; + case 13: + group_idx = 1; + break; + } + if((*(pDM_Odm->pMacPhyMode)==ODM_SMSP)||(*(pDM_Odm->pMacPhyMode)==ODM_DMSP)) + { + for(i = 0; i < SYN_Length; i++) + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, SYN[i], bMaskDWord, SYN_group[group_idx][i]); + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, channel); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_CHNLBW, 0x3FF, channel); + } + else // DualMAC_DualPHY 2G + { + for(i = 0; i < SYN_Length; i++) + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, SYN[i], bMaskDWord, SYN_group[group_idx][i]); + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, channel); + } + } + else + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, channel); + } + tone_idx = n%20; + if ((n>=PSD_skip_start) && (n PSD_report[n]) + PSD_report[n] = PSD_report_tmp; + + } + } + + PatchDCTone(pDM_Odm, PSD_report, initial_gain_psd); + + //----end + //1 Turn on RX + //Rx AGC on + ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 1); + ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 1); + //CCK on + ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 1); + //1 Turn on TX + //Resume TX Queue + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); + //Turn on 3-wire + ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0x0); + //1 Restore Current Settings + //Resume DIG + pDM_Odm->bDMInitialGainEnable= TRUE; + //ODM_SetBBReg(pDM_Odm, 0xc50, 0x7F, initial_gain); + ODM_Write_DIG(pDM_Odm,(u1Byte) initial_gain); + // restore originl center frequency + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel); + if(pDM_Odm->SupportICType == ODM_RTL8192D) + { + if((*(pDM_Odm->pMacPhyMode)==ODM_SMSP)||(*(pDM_Odm->pMacPhyMode)==ODM_DMSP)) + { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_CHNLBW, bMaskDWord, CurrentChannel); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x25, bMaskDWord, SYN_RF25); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x26, bMaskDWord, SYN_RF26); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x27, bMaskDWord, SYN_RF27); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2B, bMaskDWord, SYN_RF2B); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2C, bMaskDWord, SYN_RF2C); + } + else // DualMAC_DualPHY + { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x25, bMaskDWord, SYN_RF25); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x26, bMaskDWord, SYN_RF26); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x27, bMaskDWord, SYN_RF27); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2B, bMaskDWord, SYN_RF2B); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2C, bMaskDWord, SYN_RF2C); + } + } + //Turn on CCA + ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, RXIQI); + //Restore RX idle low power + if(RxIdleLowPwr == TRUE) + ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 1); + + psd_cnt++; + //gPrint("psd cnt=%d\n", psd_cnt); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD:psd_cnt = %d \n",psd_cnt)); + if (psd_cnt < ReScan) + { + ODM_SetTimer(pDM_Odm, &pRX_HP_Table->PSDTimer, Interval); //ms + } + else + { + psd_cnt = 0; + for(i=0;i<80;i++) + RT_TRACE( ODM_COMP_PSD, DBG_LOUD,("psd_report[%d]= %d \n", 2402+i, PSD_report[i])); + //DbgPrint("psd_report[%d]= %d \n", 2402+i, PSD_report[i]); + + GoodChannelDecision(pDM_Odm, PSD_report, PSD_bitmap,RSSI_BT, PSD_bitmap_memory); + + } +} + +void odm_Write_RXHP( + IN PVOID pDM_VOID) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table; + u4Byte currentIGI; + + if(pRX_HP_Table->Cur_IGI != pRX_HP_Table->Pre_IGI) + { + ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI); + ODM_SetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI); + } + + if(pRX_HP_Table->Cur_pw_th != pRX_HP_Table->Pre_pw_th) +{ + ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore2, BIT8|BIT9, pRX_HP_Table->Cur_pw_th); // RegC54[9:8]=2'b11: AGC Flow 3 + } + + if(pRX_HP_Table->RXHP_flag == 0) + { + pRX_HP_Table->Cur_IGI = 0x20; + } + else + { + currentIGI = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0); + if(currentIGI<0x50) + { + ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI); + ODM_SetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI); + } + } + pRX_HP_Table->Pre_IGI = pRX_HP_Table->Cur_IGI; + pRX_HP_Table->Pre_pw_th = pRX_HP_Table->Cur_pw_th; + +} + + +void odm_RXHP( + IN PVOID pDM_VOID) +{ +#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN)) +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) | (DEV_BUS_TYPE == RT_USB_INTERFACE) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table; + PFALSE_ALARM_STATISTICS FalseAlmCnt = (PFALSE_ALARM_STATISTICS)PhyDM_Get_Structure(pDM_Odm, PHYDM_FALSEALMCNT); + + u1Byte i, j, sum; + u1Byte Is40MHz; + s1Byte Intf_diff_idx, MIN_Intf_diff_idx = 16; + s4Byte cur_channel; + u1Byte ch_map_intf_5M[17] = {0}; + static u4Byte FA_TH = 0; + static u1Byte psd_intf_flag = 0; + static s4Byte curRssi = 0; + static s4Byte preRssi = 0; + static u1Byte PSDTriggerCnt = 1; + + u1Byte RX_HP_enable = (u1Byte)(ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore2, bMaskDWord)>>31); // for debug!! + +#if(DEV_BUS_TYPE == RT_USB_INTERFACE) + static s8Byte lastTxOkCnt = 0, lastRxOkCnt = 0; + s8Byte curTxOkCnt, curRxOkCnt; + s8Byte curTPOkCnt; + s8Byte TP_Acc3, TP_Acc5; + static s8Byte TP_Buff[5] = {0}; + static u1Byte pre_state = 0, pre_state_flag = 0; + static u1Byte Intf_HighTP_flag = 0, De_counter = 16; + static u1Byte TP_Degrade_flag = 0; +#endif + static u1Byte LatchCnt = 0; + + if(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8188E)) + return; + //AGC RX High Power Mode is only applied on 2G band in 92D!!! + if(pDM_Odm->SupportICType == ODM_RTL8192D) + { + if(*(pDM_Odm->pBandType) != ODM_BAND_2_4G) + return; + } + + if(!(pDM_Odm->SupportAbility & ODM_BB_RXHP)) + return; + + + //RX HP ON/OFF + if(RX_HP_enable == 1) + pRX_HP_Table->RXHP_enable = FALSE; + else + pRX_HP_Table->RXHP_enable = TRUE; + + if(pRX_HP_Table->RXHP_enable == FALSE) + { + if(pRX_HP_Table->RXHP_flag == 1) + { + pRX_HP_Table->RXHP_flag = 0; + psd_intf_flag = 0; + } + return; + } + +#if(DEV_BUS_TYPE == RT_USB_INTERFACE) + //2 Record current TP for USB interface + curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast)-lastTxOkCnt; + curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast)-lastRxOkCnt; + lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast); + lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast); + + curTPOkCnt = curTxOkCnt+curRxOkCnt; + TP_Buff[0] = curTPOkCnt; // current TP + TP_Acc3 = PlatformDivision64((TP_Buff[1]+TP_Buff[2]+TP_Buff[3]), 3); + TP_Acc5 = PlatformDivision64((TP_Buff[0]+TP_Buff[1]+TP_Buff[2]+TP_Buff[3]+TP_Buff[4]), 5); + + if(TP_Acc5 < 1000) + pRX_HP_Table->TP_Mode = Idle_Mode; + else if((1000 < TP_Acc5)&&(TP_Acc5 < 3750000)) + pRX_HP_Table->TP_Mode = Low_TP_Mode; + else + pRX_HP_Table->TP_Mode = High_TP_Mode; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP TP Mode = %d\n", pRX_HP_Table->TP_Mode)); + // Since TP result would be sampled every 2 sec, it needs to delay 4sec to wait PSD processing. + // When LatchCnt = 0, we would Get PSD result. + if(TP_Degrade_flag == 1) + { + LatchCnt--; + if(LatchCnt == 0) + { + TP_Degrade_flag = 0; + } + } + // When PSD function triggered by TP degrade 20%, and Interference Flag = 1 + // Set a De_counter to wait IGI = upper bound. If time is UP, the Interference flag will be pull down. + if(Intf_HighTP_flag == 1) + { + De_counter--; + if(De_counter == 0) + { + Intf_HighTP_flag = 0; + psd_intf_flag = 0; + } + } +#endif + + //2 AGC RX High Power Mode by PSD only applied to STA Mode + //3 NOT applied 1. Ad Hoc Mode. + //3 NOT applied 2. AP Mode + if ((pMgntInfo->mAssoc) && (!pMgntInfo->mIbss) && (!ACTING_AS_AP(Adapter))) + { + Is40MHz = *(pDM_Odm->pBandWidth); + curRssi = pDM_Odm->RSSI_Min; + cur_channel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x0fff) & 0x0f; + + /* check illegal channel and bandwidth */ + if (Is40MHz && ((cur_channel < 3) || (cur_channel > 12))) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("illegal channel setting, 40MHz channel = %d\n", cur_channel)); + return; + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP RX HP flag = %d\n", pRX_HP_Table->RXHP_flag)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP FA = %d\n", FalseAlmCnt->Cnt_all)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP cur RSSI = %d, pre RSSI=%d\n", curRssi, preRssi)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP current CH = %d\n", cur_channel)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP Is 40MHz = %d\n", Is40MHz)); + //2 PSD function would be triggered + //3 1. Every 4 sec for PCIE + //3 2. Before TP Mode (Idle TP<4kbps) for USB + //3 3. After TP Mode (High TP) for USB + if((curRssi > 68) && (pRX_HP_Table->RXHP_flag == 0)) // Only RSSI>TH and RX_HP_flag=0 will Do PSD process + { +#if (DEV_BUS_TYPE == RT_USB_INTERFACE) + //2 Before TP Mode ==> PSD would be trigger every 4 sec + if(pRX_HP_Table->TP_Mode == Idle_Mode) //2.1 less wlan traffic <4kbps + { +#endif + if(PSDTriggerCnt == 1) + { + odm_PSD_RXHP(pDM_Odm); + pRX_HP_Table->PSD_func_trigger = 1; + PSDTriggerCnt = 0; + } + else + { + PSDTriggerCnt++; + } +#if(DEV_BUS_TYPE == RT_USB_INTERFACE) + } + //2 After TP Mode ==> Check if TP degrade larger than 20% would trigger PSD function + if(pRX_HP_Table->TP_Mode == High_TP_Mode) + { + if((pre_state_flag == 0)&&(LatchCnt == 0)) + { + // TP var < 5% + if((((curTPOkCnt-TP_Acc3)*20)<(TP_Acc3))&&(((curTPOkCnt-TP_Acc3)*20)>(-TP_Acc3))) + { + pre_state++; + if(pre_state == 3) // hit pre_state condition => consecutive 3 times + { + pre_state_flag = 1; + pre_state = 0; + } + + } + else + { + pre_state = 0; + } + } + //3 If pre_state_flag=1 ==> start to monitor TP degrade 20% + if(pre_state_flag == 1) + { + if(((TP_Acc3-curTPOkCnt)*5)>(TP_Acc3)) // degrade 20% + { + odm_PSD_RXHP(pDM_Odm); + pRX_HP_Table->PSD_func_trigger = 1; + TP_Degrade_flag = 1; + LatchCnt = 2; + pre_state_flag = 0; + } + else if(((TP_Buff[2]-curTPOkCnt)*5)>TP_Buff[2]) + { + odm_PSD_RXHP(pDM_Odm); + pRX_HP_Table->PSD_func_trigger = 1; + TP_Degrade_flag = 1; + LatchCnt = 2; + pre_state_flag = 0; + } + else if(((TP_Buff[3]-curTPOkCnt)*5)>TP_Buff[3]) + { + odm_PSD_RXHP(pDM_Odm); + pRX_HP_Table->PSD_func_trigger = 1; + TP_Degrade_flag = 1; + LatchCnt = 2; + pre_state_flag = 0; + } + } + } +#endif +} + +#if (DEV_BUS_TYPE == RT_USB_INTERFACE) + for (i=0;i<4;i++) + { + TP_Buff[4-i] = TP_Buff[3-i]; + } +#endif + //2 Update PSD bitmap according to PSD report + if((pRX_HP_Table->PSD_func_trigger == 1)&&(LatchCnt == 0)) + { + //2 Separate 80M bandwidth into 16 group with smaller 5M BW. + for (i = 0 ; i < 16 ; i++) + { + sum = 0; + for(j = 0; j < 5 ; j++) + sum += pRX_HP_Table->PSD_bitmap_RXHP[5*i + j]; + + if(sum < 5) + { + ch_map_intf_5M[i] = 1; // interference flag + } + } + //=============just for debug========================= + //for(i=0;i<16;i++) + //DbgPrint("RX HP: ch_map_intf_5M[%d] = %d\n", i, ch_map_intf_5M[i]); + //=============================================== + //2 Mask target channel 5M index + for(i = 0; i < (4+4*Is40MHz) ; i++) + { + ch_map_intf_5M[cur_channel - (1+2*Is40MHz) + i] = 0; + } + + psd_intf_flag = 0; + for(i = 0; i < 16; i++) + { + if(ch_map_intf_5M[i] == 1) + { + psd_intf_flag = 1; // interference is detected!!! + break; + } + } + +#if (DEV_BUS_TYPE == RT_USB_INTERFACE) + if(pRX_HP_Table->TP_Mode!=Idle_Mode) + { + if(psd_intf_flag == 1) // to avoid psd_intf_flag always 1 + { + Intf_HighTP_flag = 1; + De_counter = 32; // 0x1E -> 0x3E needs 32 times by each IGI step =1 + } + } +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP psd_intf_flag = %d\n", psd_intf_flag)); + //2 Distance between target channel and interference + for(i = 0; i < 16; i++) + { + if(ch_map_intf_5M[i] == 1) + { + Intf_diff_idx = ((cur_channel+Is40MHz-(i+1))>0) ? (s1Byte)(cur_channel-2*Is40MHz-(i-2)) : (s1Byte)((i+1)-(cur_channel+2*Is40MHz)); + if(Intf_diff_idx < MIN_Intf_diff_idx) + MIN_Intf_diff_idx = Intf_diff_idx; // the min difference index between interference and target + } + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP MIN_Intf_diff_idx = %d\n", MIN_Intf_diff_idx)); + //2 Choose False Alarm Threshold + switch (MIN_Intf_diff_idx){ + case 0: + case 1: + case 2: + case 3: + FA_TH = FA_RXHP_TH1; + break; + case 4: // CH5 + case 5: // CH6 + FA_TH = FA_RXHP_TH2; + break; + case 6: // CH7 + case 7: // CH8 + FA_TH = FA_RXHP_TH3; + break; + case 8: // CH9 + case 9: //CH10 + FA_TH = FA_RXHP_TH4; + break; + case 10: + case 11: + case 12: + case 13: + case 14: + case 15: + FA_TH = FA_RXHP_TH5; + break; + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP FA_TH = %d\n", FA_TH)); + pRX_HP_Table->PSD_func_trigger = 0; + } + //1 Monitor RSSI variation to choose the suitable IGI or Exit AGC RX High Power Mode + if(pRX_HP_Table->RXHP_flag == 1) + { + if ((curRssi > 80)&&(preRssi < 80)) + { + pRX_HP_Table->Cur_IGI = LNA_Low_Gain_1; + } + else if ((curRssi < 80)&&(preRssi > 80)) + { + pRX_HP_Table->Cur_IGI = LNA_Low_Gain_2; + } + else if ((curRssi > 72)&&(preRssi < 72)) + { + pRX_HP_Table->Cur_IGI = LNA_Low_Gain_2; + } + else if ((curRssi < 72)&&( preRssi > 72)) + { + pRX_HP_Table->Cur_IGI = LNA_Low_Gain_3; + } + else if (curRssi < 68) //RSSI is NOT large enough!!==> Exit AGC RX High Power Mode + { + pRX_HP_Table->Cur_pw_th = pw_th_10dB; + pRX_HP_Table->RXHP_flag = 0; // Back to Normal DIG Mode + psd_intf_flag = 0; + } + } + else // pRX_HP_Table->RXHP_flag == 0 + { + //1 Decide whether to enter AGC RX High Power Mode + if ((curRssi > 70) && (psd_intf_flag == 1) && (FalseAlmCnt->Cnt_all > FA_TH) && + (pDM_DigTable->CurIGValue == pDM_DigTable->rx_gain_range_max)) + { + if (curRssi > 80) + { + pRX_HP_Table->Cur_IGI = LNA_Low_Gain_1; + } + else if (curRssi > 72) + { + pRX_HP_Table->Cur_IGI = LNA_Low_Gain_2; + } + else + { + pRX_HP_Table->Cur_IGI = LNA_Low_Gain_3; + } + pRX_HP_Table->Cur_pw_th = pw_th_16dB; //RegC54[9:8]=2'b11: to enter AGC Flow 3 + pRX_HP_Table->First_time_enter = TRUE; + pRX_HP_Table->RXHP_flag = 1; // RXHP_flag=1: AGC RX High Power Mode, RXHP_flag=0: Normal DIG Mode + } + } + preRssi = curRssi; + odm_Write_RXHP(pDM_Odm); + } +#endif //#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN)) +#endif //#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) | (DEV_BUS_TYPE == RT_USB_INTERFACE) +} + + +VOID +odm_PSD_RXHPCallback( + PRT_TIMER pTimer +) +{ + PADAPTER Adapter = (PADAPTER)pTimer->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + pRXHP_T pRX_HP_Table = &pDM_Odm->DM_RXHP_Table; + +#if DEV_BUS_TYPE==RT_PCI_INTERFACE + #if USE_WORKITEM + ODM_ScheduleWorkItem(&pRX_HP_Table->PSDTimeWorkitem); + #else + odm_PSD_RXHP(pDM_Odm); + #endif +#else + ODM_ScheduleWorkItem(&pRX_HP_Table->PSDTimeWorkitem); +#endif + + } + +VOID +odm_PSD_RXHPWorkitemCallback( + IN PVOID pContext + ) +{ + PADAPTER pAdapter = (PADAPTER)pContext; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + odm_PSD_RXHP(pDM_Odm); +} + +#endif //#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + + + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_rxhp.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_rxhp.h new file mode 100644 index 000000000..98b3aa6ab --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_rxhp.h @@ -0,0 +1,105 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __PHYDMRXHP_H__ +#define __PHYDMRXHP_H__ + +#define RXHP_VERSION "1.0" + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + +#define AFH_PSD 1 //0:normal PSD scan, 1: only do 20 pts PSD +#define MODE_40M 0 //0:20M, 1:40M +#define PSD_TH2 3 +#define PSD_CHMIN 20 // Minimum channel number for BT AFH +#define SIR_STEP_SIZE 3 +#define Smooth_Size_1 5 +#define Smooth_TH_1 3 +#define Smooth_Size_2 10 +#define Smooth_TH_2 4 +#define Smooth_Size_3 20 +#define Smooth_TH_3 4 +#define Smooth_Step_Size 5 +#define Adaptive_SIR 1 +#define PSD_RESCAN 4 +#define PSD_SCAN_INTERVAL 700 //ms + +typedef struct _RX_High_Power_ +{ + u1Byte RXHP_flag; + u1Byte PSD_func_trigger; + u1Byte PSD_bitmap_RXHP[80]; + u1Byte Pre_IGI; + u1Byte Cur_IGI; + u1Byte Pre_pw_th; + u1Byte Cur_pw_th; + BOOLEAN First_time_enter; + BOOLEAN RXHP_enable; + u1Byte TP_Mode; + RT_TIMER PSDTimer; + #if USE_WORKITEM + RT_WORK_ITEM PSDTimeWorkitem; + #endif +}RXHP_T, *pRXHP_T; + +#define dm_PSDMonitorCallback odm_PSDMonitorCallback +VOID odm_PSDMonitorCallback(PRT_TIMER pTimer); + +VOID +odm_PSDMonitorInit( + IN PVOID pDM_VOID + ); + +void odm_RXHPInit( + IN PVOID pDM_VOID); + +void odm_RXHP( + IN PVOID pDM_VOID); + +VOID +odm_PSD_RXHPCallback( + PRT_TIMER pTimer +); + + VOID +ODM_PSDDbgControl( + IN PADAPTER Adapter, + IN u4Byte mode, + IN u4Byte btRssi + ); + + VOID +odm_PSD_RXHPCallback( + PRT_TIMER pTimer +); + +VOID +odm_PSD_RXHPWorkitemCallback( + IN PVOID pContext + ); + +VOID +odm_PSDMonitorWorkItemCallback( + IN PVOID pContext + ); + + #endif + + #endif + \ No newline at end of file diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_types.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_types.h new file mode 100644 index 000000000..ff47bb406 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/phydm_types.h @@ -0,0 +1,259 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __ODM_TYPES_H__ +#define __ODM_TYPES_H__ + + +/*Define Different SW team support*/ +#define ODM_AP 0x01 /*BIT0*/ +#define ODM_ADSL 0x02 +#define ODM_CE 0x04 /*BIT2*/ +#define ODM_WIN 0x08 /*BIT3*/ + +/*Deifne HW endian support*/ +#define ODM_ENDIAN_BIG 0 +#define ODM_ENDIAN_LITTLE 1 + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#define GET_PDM_ODM(__pAdapter) ((PDM_ODM_T)(&((GET_HAL_DATA(__pAdapter))->DM_OutSrc))) +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) +#define GET_PDM_ODM(__pAdapter) ((PDM_ODM_T)(&((GET_HAL_DATA(__pAdapter))->odmpriv))) +#endif + +#if (DM_ODM_SUPPORT_TYPE != ODM_WIN) +#define RT_PCI_INTERFACE 1 +#define RT_USB_INTERFACE 2 +#define RT_SDIO_INTERFACE 3 +#endif + +typedef enum _HAL_STATUS{ + HAL_STATUS_SUCCESS, + HAL_STATUS_FAILURE, + /*RT_STATUS_PENDING, + RT_STATUS_RESOURCE, + RT_STATUS_INVALID_CONTEXT, + RT_STATUS_INVALID_PARAMETER, + RT_STATUS_NOT_SUPPORT, + RT_STATUS_OS_API_FAILED,*/ +}HAL_STATUS,*PHAL_STATUS; + +#if( DM_ODM_SUPPORT_TYPE == ODM_AP) +#define MP_DRIVER 0 +#endif +#if(DM_ODM_SUPPORT_TYPE != ODM_WIN) + +#define VISTA_USB_RX_REVISE 0 + +// +// Declare for ODM spin lock defintion temporarily fro compile pass. +// +typedef enum _RT_SPINLOCK_TYPE{ + RT_TX_SPINLOCK = 1, + RT_RX_SPINLOCK = 2, + RT_RM_SPINLOCK = 3, + RT_CAM_SPINLOCK = 4, + RT_SCAN_SPINLOCK = 5, + RT_LOG_SPINLOCK = 7, + RT_BW_SPINLOCK = 8, + RT_CHNLOP_SPINLOCK = 9, + RT_RF_OPERATE_SPINLOCK = 10, + RT_INITIAL_SPINLOCK = 11, + RT_RF_STATE_SPINLOCK = 12, // For RF state. Added by Bruce, 2007-10-30. +#if VISTA_USB_RX_REVISE + RT_USBRX_CONTEXT_SPINLOCK = 13, + RT_USBRX_POSTPROC_SPINLOCK = 14, // protect data of Adapter->IndicateW/ IndicateR +#endif + //Shall we define Ndis 6.2 SpinLock Here ? + RT_PORT_SPINLOCK=16, + RT_VNIC_SPINLOCK=17, + RT_HVL_SPINLOCK=18, + RT_H2C_SPINLOCK = 20, // For H2C cmd. Added by tynli. 2009.11.09. + + RT_BTData_SPINLOCK=25, + + RT_WAPI_OPTION_SPINLOCK=26, + RT_WAPI_RX_SPINLOCK=27, + + // add for 92D CCK control issue + RT_CCK_PAGEA_SPINLOCK = 28, + RT_BUFFER_SPINLOCK = 29, + RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30, + RT_GEN_TEMP_BUF_SPINLOCK = 31, + RT_AWB_SPINLOCK = 32, + RT_FW_PS_SPINLOCK = 33, + RT_HW_TIMER_SPIN_LOCK = 34, + RT_MPT_WI_SPINLOCK = 35, + RT_P2P_SPIN_LOCK = 36, // Protect P2P context + RT_DBG_SPIN_LOCK = 37, + RT_IQK_SPINLOCK = 38, + RT_PENDED_OID_SPINLOCK = 39, + RT_CHNLLIST_SPINLOCK = 40, + RT_INDIC_SPINLOCK = 41, //protect indication + RT_RFD_SPINLOCK = 42, + RT_SYNC_IO_CNT_SPINLOCK = 43, + RT_LAST_SPINLOCK, +}RT_SPINLOCK_TYPE; + +#endif + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + #define STA_INFO_T RT_WLAN_STA + #define PSTA_INFO_T PRT_WLAN_STA + #define __func__ __FUNCTION__ + #define PHYDM_TESTCHIP_SUPPORT TESTCHIP_SUPPORT + #define bMaskH3Bytes 0xffffff00 + #define SUCCESS 0 + #define FAIL (-1) + +#elif (DM_ODM_SUPPORT_TYPE == ODM_AP) + + // To let ADSL/AP project compile ok; it should be removed after all conflict are solved. Added by Annie, 2011-10-07. + #define ADSL_AP_BUILD_WORKAROUND + #define AP_BUILD_WORKAROUND + + #ifdef AP_BUILD_WORKAROUND + #include "../typedef.h" + #else + typedef void VOID,*PVOID; + typedef unsigned char BOOLEAN,*PBOOLEAN; + typedef unsigned char u1Byte,*pu1Byte; + typedef unsigned short u2Byte,*pu2Byte; + typedef unsigned int u4Byte,*pu4Byte; + typedef unsigned long long u8Byte,*pu8Byte; +#if 1 +/* In ARM platform, system would use the type -- "char" as "unsigned char" + * And we only use s1Byte/ps1Byte as INT8 now, so changes the type of s1Byte.*/ + typedef signed char s1Byte,*ps1Byte; +#else + typedef char s1Byte,*ps1Byte; +#endif + typedef short s2Byte,*ps2Byte; + typedef long s4Byte,*ps4Byte; + typedef long long s8Byte,*ps8Byte; + #endif + + typedef struct rtl8192cd_priv *prtl8192cd_priv; + typedef struct stat_info STA_INFO_T,*PSTA_INFO_T; + typedef _timer RT_TIMER, *PRT_TIMER; + typedef void * RT_TIMER_CALL_BACK; + +#ifdef CONFIG_PCI_HCI + #define DEV_BUS_TYPE RT_PCI_INTERFACE +#endif + + #define _TRUE 1 + #define _FALSE 0 + + #if (defined(TESTCHIP_SUPPORT)) + #define PHYDM_TESTCHIP_SUPPORT 1 + #else + #define PHYDM_TESTCHIP_SUPPORT 0 + #endif + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + #include +#if 0 + typedef u8 u1Byte, *pu1Byte; + typedef u16 u2Byte,*pu2Byte; + typedef u32 u4Byte,*pu4Byte; + typedef u64 u8Byte,*pu8Byte; + typedef s8 s1Byte,*ps1Byte; + typedef s16 s2Byte,*ps2Byte; + typedef s32 s4Byte,*ps4Byte; + typedef s64 s8Byte,*ps8Byte; +#else + #define u1Byte u8 + #define pu1Byte u8* + + #define u2Byte u16 + #define pu2Byte u16* + + #define u4Byte u32 + #define pu4Byte u32* + + #define u8Byte u64 + #define pu8Byte u64* + + #define s1Byte s8 + #define ps1Byte s8* + + #define s2Byte s16 + #define ps2Byte s16* + + #define s4Byte s32 + #define ps4Byte s32* + + #define s8Byte s64 + #define ps8Byte s64* + +#endif + #ifdef CONFIG_USB_HCI + #define DEV_BUS_TYPE RT_USB_INTERFACE + #elif defined(CONFIG_PCI_HCI) + #define DEV_BUS_TYPE RT_PCI_INTERFACE + #elif defined(CONFIG_SDIO_HCI) + #define DEV_BUS_TYPE RT_SDIO_INTERFACE + #elif defined(CONFIG_GSPI_HCI) + #define DEV_BUS_TYPE RT_SDIO_INTERFACE + #endif + + + #if defined(CONFIG_LITTLE_ENDIAN) + #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE + #elif defined (CONFIG_BIG_ENDIAN) + #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG + #endif + + typedef _timer RT_TIMER, *PRT_TIMER; + typedef void * RT_TIMER_CALL_BACK; + #define STA_INFO_T struct sta_info + #define PSTA_INFO_T struct sta_info * + + + + #define TRUE _TRUE + #define FALSE _FALSE + + + #define SET_TX_DESC_ANTSEL_A_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 1, __Value) + #define SET_TX_DESC_ANTSEL_B_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 25, 1, __Value) + #define SET_TX_DESC_ANTSEL_C_88E(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 29, 1, __Value) + + //define useless flag to avoid compile warning + #define USE_WORKITEM 0 + #define FOR_BRAZIL_PRETEST 0 + /*#define BT_30_SUPPORT 0*/ + #define FPGA_TWO_MAC_VERIFICATION 0 + #define RTL8881A_SUPPORT 0 + + #if (defined(TESTCHIP_SUPPORT)) + #define PHYDM_TESTCHIP_SUPPORT 1 + #else + #define PHYDM_TESTCHIP_SUPPORT 0 + #endif +#endif + +#define READ_NEXT_PAIR(v1, v2, i) do { if (i+2 >= ArrayLen) break; i += 2; v1 = Array[i]; v2 = Array[i+1]; } while(0) +#define COND_ELSE 2 +#define COND_ENDIF 3 + +#endif // __ODM_TYPES_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtchnlplan.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtchnlplan.c new file mode 100644 index 000000000..d2a762df5 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtchnlplan.c @@ -0,0 +1,480 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +/****************************************************************************** + + History: + Data Who Remark (Internal History) + + 05/14/2012 MH Collect RTK inernal infromation and generate channel plan draft. + +******************************************************************************/ + +//============================================================ +// include files +//============================================================ +#include "mp_precomp.h" +#include "rtchnlplan.h" + + + +// +// Channel Plan Domain Code +// + +/* + Channel Plan Contents + Domain Code EEPROM Countries in Specific Domain + 2G RD 5G RD Bit[6:0] 2G 5G + Case Old Define 00h~1Fh Old Define Old Define + 1 2G_WORLD 5G_NULL 20h Worldwird 13 NA + 2 2G_ETSI1 5G_NULL 21h Europe 2G NA + 3 2G_FCC1 5G_NULL 22h US 2G NA + 4 2G_MKK1 5G_NULL 23h Japan 2G NA + 5 2G_ETSI2 5G_NULL 24h France 2G NA + 6 2G_FCC1 5G_FCC1 25h US 2G US 5G Kj{ + 7 2G_WORLD 5G_ETSI1 26h Worldwird 13 Europe Kj{ + 8 2G_MKK1 5G_MKK1 27h Japan 2G Japan 5G Kj{ + 9 2G_WORLD 5G_KCC1 28h Worldwird 13 Korea Kj{ + 10 2G_WORLD 5G_FCC2 29h Worldwird 13 US o/w DFS Channels + 11 2G_WORLD 5G_FCC3 30h Worldwird 13 India, Mexico + 12 2G_WORLD 5G_FCC4 31h Worldwird 13 Venezuela + 13 2G_WORLD 5G_FCC5 32h Worldwird 13 China + 14 2G_WORLD 5G_FCC6 33h Worldwird 13 Israel + 15 2G_FCC1 5G_FCC7 34h US 2G US/Canada Kj{ + 16 2G_WORLD 5G_ETSI2 35h Worldwird 13 Australia, New Zealand Kj{ + 17 2G_WORLD 5G_ETSI3 36h Worldwird 13 Russia + 18 2G_MKK1 5G_MKK2 37h Japan 2G Japan (W52, W53) + 19 2G_MKK1 5G_MKK3 38h Japan 2G Japan (W56) + 20 2G_FCC1 5G_NCC1 39h US 2G Taiwan Kj{ + + NA 2G_WORLD 5G_FCC1 7F FCC FCC DFS Channels Realtek Define + + + + + + 2.4G Regulatory Domains + Case 2G RD Regulation Channels Frequencyes Note Countries in Specific Domain + 1 2G_WORLD ETSI 1~13 2412~2472 Passive scan CH 12, 13 Worldwird 13 + 2 2G_ETSI1 ETSI 1~13 2412~2472 Europe + 3 2G_FCC1 FCC 1~11 2412~2462 US + 4 2G_MKK1 MKK 1~13, 14 2412~2472, 2484 Japan + 5 2G_ETSI2 ETSI 10~13 2457~2472 France + + + + + 5G Regulatory Domains + Case 5G RD Regulation Channels Frequencyes Note Countries in Specific Domain + 1 5G_NULL NA NA NA Do not support 5GHz + 2 5G_ETSI1 ETSI "36~48, 52~64, + 100~140" "5180~5240, 5260~5230 + 5500~5700" Band1, Ban2, Band3 Europe + 3 5G_ETSI2 ETSI "36~48, 52~64, + 100~140, 149~165" "5180~5240, 5260~5230 + 5500~5700, 5745~5825" Band1, Ban2, Band3, Band4 Australia, New Zealand + 4 5G_ETSI3 ETSI "36~48, 52~64, + 100~132, 149~165" + "5180~5240, 5260~5230 + 5500~5660, 5745~5825" Band1, Ban2, Band3(except CH 136, 140), Band4" Russia + 5 5G_FCC1 FCC "36~48, 52~64, + 100~140, 149~165" + "5180~5240, 5260~5230 + 5500~5700, 5745~5825" Band1(5150~5250MHz), + Band2(5250~5350MHz), + Band3(5470~5725MHz), + Band4(5725~5850MHz)" US + 6 5G_FCC2 FCC 36~48, 149~165 5180~5240, 5745~5825 Band1, Band4 FCC o/w DFS Channels + 7 5G_FCC3 FCC "36~48, 52~64, + 149~165" "5180~5240, 5260~5230 + 5745~5825" Band1, Ban2, Band4 India, Mexico + 8 5G_FCC4 FCC "36~48, 52~64, + 149~161" "5180~5240, 5260~5230 + 5745~5805" Band1, Ban2, + Band4(except CH 165)" Venezuela + 9 5G_FCC5 FCC 149~165 5745~5825 Band4 China + 10 5G_FCC6 FCC 36~48, 52~64 5180~5240, 5260~5230 Band1, Band2 Israel + 11 5G_FCC7 + 5G_IC1 FCC + IC" "36~48, 52~64, + 100~116, 136, 140, + 149~165" "5180~5240, 5260~5230 + 5500~5580, 5680, 5700, + 5745~5825" "Band1, Band2, + Band3(except 5600~5650MHz), + Band4" "US + Canada" + 12 5G_KCC1 KCC "36~48, 52~64, + 100~124, 149~165" "5180~5240, 5260~5230 + 5500~5620, 5745~5825" "Band1, Ban2, + Band3(5470~5650MHz), + Band4" Korea + 13 5G_MKK1 MKK "36~48, 52~64, + 100~140" "5180~5240, 5260~5230 + 5500~5700" W52, W53, W56 Japan + 14 5G_MKK2 MKK 36~48, 52~64 5180~5240, 5260~5230 W52, W53 Japan (W52, W53) + 15 5G_MKK3 MKK 100~140 5500~5700 W56 Japan (W56) + 16 5G_NCC1 NCC "56~64, + 100~116, 136, 140, + 149~165" "5260~5320 + 5500~5580, 5680, 5700, + 5745~5825" "Band2(except CH 52), + Band3(except 5600~5650MHz), + Band4" Taiwan + + +*/ + +// +// 2.4G CHannel +// +/* + + 2.4G Band Regulatory Domains RTL8192D + Channel Number Channel Frequency US Canada Europe Spain France Japan Japan 20M 40M + (MHz) (FCC) (IC) (ETSI) (MPHPT) + 1 2412 v v v v v + 2 2417 v v v v v + 3 2422 v v v v v v + 4 2427 v v v v v v + 5 2432 v v v v v v + 6 2437 v v v v v v + 7 2442 v v v v v v + 8 2447 v v v v v v + 9 2452 v v v v v v + 10 2457 v v v v v v v v + 11 2462 v v v v v v v v + 12 2467 v v v v v + 13 2472 v v v v + 14 2484 v v + + +*/ + + +// +// 5G Operating Channel +// +/* + + 5G Band RTL8192D RTL8195 (Jaguar) Jaguar 2 Regulatory Domains + Channel Number Channel Frequency Global Global Global "US +(FCC 15.407)" "Canada +(FCC, except 5.6~5.65GHz)" Argentina, Australia, New Zealand, Brazil, S. Africa (FCC/ETSI) "Europe +(CE 301 893)" China India, Mexico, Singapore Israel, Turkey "Japan +(MIC Item 19-3, 19-3-2)" Korea Russia, Ukraine "Taiwan +(NCC)" Venezuela + (MHz) (20MHz) (20MHz) (40MHz) (80MHz) (160MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) (20MHz) +"Band 1 +5.15GHz +~ +5.25GHz" 36 5180 v v v v v Indoor Indoor v Indoor v Indoor Indoor v v v + 40 5200 v v v Indoor Indoor v Indoor v Indoor Indoor v v v + 44 5220 v v v v Indoor Indoor v Indoor v Indoor Indoor v v v + 48 5240 v v v Indoor Indoor v Indoor v Indoor Indoor v v v +"Band 2 +5.25GHz +~ +5.35GHz +(DFS)" 52 5260 v v v v v v v v Indoor v Indoor Indoor v v v + 56 5280 v v v v v v Indoor v Indoor Indoor v v Indoor v + 60 5300 v v v v v v v Indoor v Indoor Indoor v v Indoor v + 64 5320 v v v v v v Indoor v Indoor Indoor v v Indoor v + +"Band 3 +5.47GHz +~ +5.725GHz +(DFS)" 100 5500 v v v v v v v v v v v v v + 104 5520 v v v v v v v v v v v + 108 5540 v v v v v v v v v v v v + 112 5560 v v v v v v v v v v v + 116 5580 v v v v v v v v v v v v v + 120 5600 v v v Indoor v Indoor v v v + 124 5620 v v v v Indoor v Indoor v v v + 128 5640 v v v Indoor v Indoor v v + 132 5660 v v v E v Indoor v Indoor v v + 136 5680 v v v v v v v v v + 140 5700 v v E v v v v v v v + 144 5720 E E E +"Band 4 +5.725GHz +~ +5.85GHz +(~5.9GHz)" 149 5745 v v v v v v v v v v v v v v + 153 5765 v v v v v v v v v v v v + 157 5785 v v v v v v v v v v v v v + 161 5805 v v v v v v v v v v v v + 165 5825 v v P P v v v v v v v v v + 169 5845 P P P + 173 5865 P P P P + 177 5885 P P P +Channel Count 28 28 14 7 0 28 24 20 24 19 5 13 8 19 20 22 15 12 + E: FCC accepted the ask for CH144 from Accord. PS: 160MHz 80MHz+80MHz{H Argentina Belgium (Q) India Israel Russia + P: Customer's requirement from James. Australia The Netherlands () Mexico Turkey Ukraine + New Zealand UK (^) Singapore + Brazil Switzerland (h) + + +*/ + +/*---------------------------Define Local Constant---------------------------*/ + + +// define Maximum Power v.s each band for each region +// ISRAEL +// Format: +// RT_CHANNEL_DOMAIN_Region ={{{Chnl_Start, Chnl_end, Pwr_dB_Max}, {Chn2_Start, Chn2_end, Pwr_dB_Max}, {Chn3_Start, Chn3_end, Pwr_dB_Max}, {Chn4_Start, Chn4_end, Pwr_dB_Max}, {Chn5_Start, Chn5_end, Pwr_dB_Max}}, Limit_Num} */ +// RT_CHANNEL_DOMAIN_FCC ={{{01,11,30}, {36,48,17}, {52,64,24}, {100,140,24}, {149,165,30}}, 5} +// "NR" is non-release channle. +// Issue--- Israel--Russia--New Zealand +// DOMAIN_01= (2G_WORLD, 5G_NULL) +// DOMAIN_02= (2G_ETSI1, 5G_NULL) +// DOMAIN_03= (2G_FCC1, 5G_NULL) +// DOMAIN_04= (2G_MKK1, 5G_NULL) +// DOMAIN_05= (2G_ETSI2, 5G_NULL) +// DOMAIN_06= (2G_FCC1, 5G_FCC1) +// DOMAIN_07= (2G_WORLD, 5G_ETSI1) +// DOMAIN_08= (2G_MKK1, 5G_MKK1) +// DOMAIN_09= (2G_WORLD, 5G_KCC1) +// DOMAIN_10= (2G_WORLD, 5G_FCC2) +// DOMAIN_11= (2G_WORLD, 5G_FCC3)----india +// DOMAIN_12= (2G_WORLD, 5G_FCC4)----Venezuela +// DOMAIN_13= (2G_WORLD, 5G_FCC5)----China +// DOMAIN_14= (2G_WORLD, 5G_FCC6)----Israel +// DOMAIN_15= (2G_FCC1, 5G_FCC7)-----Canada +// DOMAIN_16= (2G_WORLD, 5G_ETSI2)---Australia +// DOMAIN_17= (2G_WORLD, 5G_ETSI3)---Russia +// DOMAIN_18= (2G_MKK1, 5G_MKK2)-----Japan +// DOMAIN_19= (2G_MKK1, 5G_MKK3)-----Japan +// DOMAIN_20= (2G_FCC1, 5G_NCC1)-----Taiwan +// DOMAIN_21= (2G_FCC1, 5G_NCC1)-----Taiwan + + +static RT_CHANNEL_PLAN_MAXPWR ChnlPlanPwrMax_2G[] = { + + // 2G_WORLD, + {{1, 13, 20}, 1}, + + // 2G_ETSI1 + {{1, 13, 20}, 1}, + + /* RT_CHANNEL_DOMAIN_ETSI */ + {{{1, 11, 17}, {40, 56, 17}, {60, 128, 17}, {0, 0, 0}, {149, 165, 17}}, 4}, + + // RT_CHANNEL_DOMAIN_MKK + {{{1, 11, 17}, {0, 0, 0}, {0, 0, 0}, {0, 0, 0}, {0, 0, 0}}, 1}, + + // Add new channel plan mex power table. + // ...... + }; + + +/* +//===========================================1:(2G_WORLD, 5G_NULL) + +RT_CHANNEL_PLAN_MAXPWR RT_DOMAIN_01 ={{{01,13,20}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}}, 1} + +//===========================================2:(2G_ETSI1, 5G_NULL) + +RT_DOMAIN_02 ={{{01,13,20}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}}, 1} + +//===========================================3:(2G_FCC1, 5G_NULL) + +RT_DOMAIN_03 ={{{01,11,30}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}}, 1} + +//===========================================4:(2G_MKK1, 5G_NULL) + +RT_DOMAIN_04 ={{{01,14,23}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}}, 1} + +//===========================================5:(2G_ETSI2, 5G_NULL) + +RT_DOMAIN_05 ={{{10,13,20}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}}, 1} + +//===========================================6:(2G_FCC1, 5G_FCC1) + +RT_DOMAIN_06 ={{{01,13,30}, {36,48,17}, {52,64,24}, {100,140,24}, {149,165,30}}, 5} + +//===========================================7:(2G_WORLD, 5G_ETSI1) + +RT_DOMAIN_07 ={{{01,13,20}, {36,48,23}, {52,64,23}, {100,140,30}, {NR,NR,0}}, 4} + +//===========================================8:(2G_MKK1, 5G_MKK1) + +RT_DOMAIN_08 ={{{01,14,23}, {36,48,23}, {52,64,23}, {100,140,23}, {NR,NR,0}}, 4} + +//===========================================9:(2G_WORLD, 5G_KCC1) + +RT_DOMAIN_09 ={{{01,13,20}, {36,48,17}, {52,64,23}, {100,124,23}, {149,165,23}}, 5} + +//===========================================10:(2G_WORLD, 5G_FCC2) + +RT_DOMAIN_10 ={{{01,13,20}, {36,48,17}, {NR,NR,0}, {NR,NR,0}, {149,165,30}}, 3} + +//===========================================11:(2G_WORLD, 5G_FCC3) +RT_DOMAIN_11 ={{{01,13,20}, {36,48,23}, {52,64,23}, {NR,NR,0}, {149,165,23}}, 4} + +//===========================================12:(2G_WORLD, 5G_FCC4) +RT_DOMAIN_12 ={{{01,13,20}, {36,48,24}, {52,64,24}, {NR,NR,0}, {149,161,27}}, 4} + +//===========================================13:(2G_WORLD, 5G_FCC5) +RT_DOMAIN_13 ={{{01,13,20}, {NR,NR,0}, {NR,NR,0}, {NR,NR,0}, {149,165,27}}, 2} + +//===========================================14:(2G_WORLD, 5G_FCC6) +RT_DOMAIN_14 ={{{01,13,20}, {36,48,17}, {52,64,17}, {NR,NR,0}, {NR,NR,0}}, 3} + +//===========================================15:(2G_FCC1, 5G_FCC7) +RT_DOMAIN_15 ={{{01,11,30}, {36,48,23}, {52,64,24}, {100,140,24}, {149,165,30}}, 5} + +//===========================================16:(2G_WORLD, 5G_ETSI2) +RT_DOMAIN_16 ={{{01,13,20}, {36,48,23}, {52,64,23}, {100,140,30}, {149,165,30}}, 5} + +//===========================================17:(2G_WORLD, 5G_ETSI3) +RT_DOMAIN_17 ={{{01,13,20}, {36,48,23}, {52,64,23}, {100,132,30}, {149,165,20}}, 5} + +//===========================================18:(2G_MKK1, 5G_MKK2) +RT_DOMAIN_18 ={{{01,14,23}, {36,48,23}, {52,64,23}, {NR,NR,0}, {NR,NR,0}}, 3} + +//===========================================19:(2G_MKK1, 5G_MKK3) +RT_DOMAIN_19 ={{{01,14,23}, {NR,NR,0}, {NR,NR,0}, {100,140,23}, {NR,NR,0}}, 2} + +//===========================================20:(2G_FCC1, 5G_NCC1) +RT_DOMAIN_20 ={{{01,11,30}, {NR,NR,0}, {56,64,23}, {100,140,24}, {149,165,30}}, 4} + +//===========================================21:(2G_FCC1, 5G_NCC2) +RT_DOMAIN_21 ={{{01,11,30}, {NR,NR,0}, {56,64,23}, {NR,NR,0}, {149,165,30}}, 3} + +//===========================================22:(2G_WORLD, 5G_FCC3) +RT_DOMAIN_22 ={{{01,13,24}, {36,48,20}, {52,64,24}, {NR,NR,0}, {149,165,30}}, 4} + +//===========================================23:(2G_WORLD, 5G_ETSI2) +RT_DOMAIN_23 ={{{01,13,20}, {36,48,23}, {52,64,23}, {100,140,30}, {149,165,30}}, 5} + +*/ + +// +// Counter & Realtek Channel plan transfer table. +// +RT_CHNL_CTRY_TBL RtCtryChnlTbl[] = +{ + + { + RT_CTRY_AL, // "Albaniaڥ" + "AL", + RT_2G_WORLD, + RT_5G_WORLD, + RT_CHANNEL_DOMAIN_UNDEFINED // 2G/5G world. + }, +#if 0 + { + RT_CTRY_BB, // "Barbadosڤڦh" + "BB", + RT_2G_WORLD, + RT_5G_NULL, + RT_CHANNEL_DOMAIN_EFUSE_0x20 // 2G world. 5G_NULL + }, + + { + RT_CTRY_DE, // "Germanyw" + "DE", + RT_2G_WORLD, + RT_5G_ETSI1, + RT_CHANNEL_DOMAIN_EFUSE_0x26 + }, + + { + RT_CTRY_US, // "Germanyw" + "US", + RT_2G_FCC1, + RT_5G_FCC7, + RT_CHANNEL_DOMAIN_EFUSE_0x34 + }, + + { + RT_CTRY_JP, // "Germanyw" + "JP", + RT_2G_MKK1, + RT_5G_MKK1, + RT_CHANNEL_DOMAIN_EFUSE_0x34 + }, + + { + RT_CTRY_TW, // "Germanyw" + "TW", + RT_2G_FCC1, + RT_5G_NCC1, + RT_CHANNEL_DOMAIN_EFUSE_0x39 + }, +#endif + +}; // RtCtryChnlTbl + +// +// Realtek Defined Channel plan. +// +#if 0 + +static RT_CHANNEL_PLAN_NEW RtChnlPlan[] = +{ + // Channel Plan 0x20. + { + &RtCtryChnlTbl[1], // RT_CHNL_CTRY_TBL Country & channel plan transfer table. + RT_CHANNEL_DOMAIN_EFUSE_0x20, // RT_CHANNEL_DOMAIN RT Channel Plan Define + RT_2G_WORLD, // RT_REGULATION_2G + RT_5G_NULL, // RT_REGULATION_5G + RT_WORLD, // RT_REGULATION_CMN RT Regulatory domain definition. + RT_SREQ_NA, // RT Channel plan special & customerize requirement. + + CHNL_RT_2G_WORLD, + CHNL_RT_2G_WORLD_SCAN_TYPE, + &ChnlPlanPwrMax_2G[0], + + CHNL_RT_5G_NULL, + CHNL_RT_5G_NULL_SCAN_TYPE, + + + }, + + // Channel Plan 0x26. + { + &RtCtryChnlTbl[1], // RT_CHNL_CTRY_TBL Country & channel plan transfer table. + RT_CHANNEL_DOMAIN_EFUSE_0x26, // RT_CHANNEL_DOMAIN RT Channel Plan Define + RT_2G_WORLD, // RT_REGULATION_2G + RT_5G_ETSI1, // RT_REGULATION_5G + RT_WORLD, // RT_REGULATION_CMN RT Regulatory domain definition. + RT_SREQ_NA, // RT Channel plan special & customerize requirement. + + CHNL_RT_2G_WORLD, // 2G workd cannel + CHNL_RT_2G_WORLD_SCAN_TYPE, + &ChnlPlanPwrMax_2G[1], + + CHNL_RT_5G_ETSI1, + CHNL_RT_5G_ETSI1_SCAN_TYPE, + + } + + +}; +#endif + + + + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtchnlplan.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtchnlplan.h new file mode 100644 index 000000000..78a31dcd1 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtchnlplan.h @@ -0,0 +1,699 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __RT_CHANNELPLAN_H__ +#define __RT_CHANNELPLAN_H__ + +typedef enum _RT_CHANNEL_DOMAIN_NEW +{ + + //===== Add new channel plan above this line ===============// + + // For new architecture we define different 2G/5G CH area for all country. + // 2.4 G only + RT_CHANNEL_DOMAIN_2G_WORLD_5G_NULL = 0x20, + RT_CHANNEL_DOMAIN_2G_ETSI1_5G_NULL = 0x21, + RT_CHANNEL_DOMAIN_2G_FCC1_5G_NULL = 0x22, + RT_CHANNEL_DOMAIN_2G_MKK1_5G_NULL = 0x23, + RT_CHANNEL_DOMAIN_2G_ETSI2_5G_NULL = 0x24, + // 2.4 G + 5G type 1 + RT_CHANNEL_DOMAIN_2G_FCC1_5G_FCC1 = 0x25, + RT_CHANNEL_DOMAIN_2G_WORLD_5G_ETSI1 = 0x26, + //RT_CHANNEL_DOMAIN_2G_WORLD_5G_ETSI1 = 0x27, + // ..... + + RT_CHANNEL_DOMAIN_MAX_NEW, + +}RT_CHANNEL_DOMAIN_NEW, *PRT_CHANNEL_DOMAIN_NEW; + + +#if 0 +#define DOMAIN_CODE_2G_WORLD \ + {1,2,3,4,5,6,7,8,9,10,11,12,13}, 13 +#define DOMAIN_CODE_2G_ETSI1 \ + {1,2,3,4,5,6,7,8,9,10,11,12,13}, 13 +#define DOMAIN_CODE_2G_ETSI2 \ + {1,2,3,4,5,6,7,8,9,10,11}, 11 +#define DOMAIN_CODE_2G_FCC1 \ + {1,2,3,4,5,6,7,8,9,10,11,12,13,14}, 14 +#define DOMAIN_CODE_2G_MKK1 \ + {10,11,12,13}, 4 + +#define DOMAIN_CODE_5G_ETSI1 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19 +#define DOMAIN_CODE_5G_ETSI2 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24 +#define DOMAIN_CODE_5G_ETSI3 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,149,153,157,161,165}, 22 +#define DOMAIN_CODE_5G_FCC1 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24 +#define DOMAIN_CODE_5G_FCC2 \ + {36,40,44,48,149,153,157,161,165}, 9 +#define DOMAIN_CODE_5G_FCC3 \ + {36,40,44,48,52,56,60,64,149,153,157,161,165}, 13 +#define DOMAIN_CODE_5G_FCC4 \ + {36,40,44,48,52,56,60,64,149,153,157,161}, 12 +#define DOMAIN_CODE_5G_FCC5 \ + {149,153,157,161,165}, 5 +#define DOMAIN_CODE_5G_FCC6 \ + {36,40,44,48,52,56,60,64}, 8 +#define DOMAIN_CODE_5G_FCC7 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 +#define DOMAIN_CODE_5G_IC1 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 +#define DOMAIN_CODE_5G_KCC1 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,149,153,157,161,165}, 20 +#define DOMAIN_CODE_5G_MKK1 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19 +#define DOMAIN_CODE_5G_MKK2 \ + {36,40,44,48,52,56,60,64}, 8 +#define DOMAIN_CODE_5G_MKK3 \ + {100,104,108,112,116,120,124,128,132,136,140}, 11 +#define DOMAIN_CODE_5G_NCC1 \ + {56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 24 +#define DOMAIN_CODE_5G_NCC2 \ + {56,60,64,149,153,157,161,165}, 8 +#define UNDEFINED \ + {0}, 0 +#endif + +// +// +// +/* + +Countries "Country Abbreviation" Domain Code SKU's Ch# of 20MHz + 2G 5G Ch# of 40MHz +"Albaniaڥ" AL Local Test + +"AlgeriaΧQ" DZ CE TCF + +"Antigua & Barbudawʮq&ڥF" AG 2G_WORLD FCC TCF + +"Argentinaڧ" AR 2G_WORLD Local Test + +"ArmeniaȬ" AM 2G_WORLD ETSI + +"Aruba|ڮq" AW 2G_WORLD FCC TCF + +"AustraliaDw" AU 2G_WORLD 5G_ETSI2 + +"AustriaaQ" AT 2G_WORLD 5G_ETSI1 CE + +"Azerbaijan" AZ 2G_WORLD CE TCF + +"Bahamasګ" BS 2G_WORLD + +"Barbadosڤڦh" BB 2G_WORLD FCC TCF + +"BelgiumQ" BE 2G_WORLD 5G_ETSI1 CE + +"Bermudaʼ}F" BM 2G_WORLD FCC TCF + +"Brazilڦ" BR 2G_WORLD Local Test + +"BulgariaO[Q" BG 2G_WORLD 5G_ETSI1 CE + +"Canada[j" CA 2G_FCC1 5G_FCC7 IC / FCC IC / FCC + +"Cayman Islands}Ҹsq" KY 2G_WORLD 5G_ETSI1 CE + +"ChileQ" CL 2G_WORLD FCC TCF + +"China" CN 2G_WORLD 5G_FCC5 H?i2002j353? + +"Columbiaۤ" CO 2G_WORLD Voluntary + +"Costa RicaF[" CR 2G_WORLD FCC TCF + +"Cyprus" CY 2G_WORLD 5G_ETSI1 CE + +"Czech J" CZ 2G_WORLD 5G_ETSI1 CE + +"Denmark" DK 2G_WORLD 5G_ETSI1 CE + +"Dominican Republich[@M" DO 2G_WORLD FCC TCF + +"EgyptJ" EG 2G_WORLD CE T CF + +"El Salvadorĺ˦h" SV 2G_WORLD Voluntary + +"EstoniaRF" EE 2G_WORLD 5G_ETSI1 CE + +"Finland" FI 2G_WORLD 5G_ETSI1 CE + +"Francek" FR 5G_E TSI1 CE + +"Germanyw" DE 2G_WORLD 5G_ETSI1 CE + +"Greece þ" GR 2G_WORLD 5G_ETSI1 CE + +"Guamq" GU 2G_WORLD + +"Guatemalaʦa" GT 2G_WORLD + +"Haitia" HT 2G_WORLD FCC TCF + +"HondurasԴ" HN 2G_WORLD FCC TCF + +"HungaryIQ" HU 2G_WORLD 5G_ETSI1 CE + +"IcelandBq" IS 2G_WORLD 5G_ETSI1 CE + +"IndiaL" IN 2G_WORLD 5G_FCC3 FCC/CE TCF + +"IrelandR" IE 2G_WORLD 5G_ETSI1 CE + +"IsraelHC" IL 5G_F CC6 CE TCF + +"ItalyqjQ" IT 2G_WORLD 5G_ETSI1 CE + +"Japan饻" JP 2G_MKK1 5G_MKK1 MKK MKK + +"Korea" KR 2G_WORLD 5G_KCC1 KCC KCC + +"LatviaԲ" LV 2G_WORLD 5G_ETSI1 CE + +"Lithuania߳{" LT 2G_WORLD 5G_ETSI1 CE + +"Luxembourgc˳" LU 2G_WORLD 5G_ETSI1 CE + +"MalaysiaӦ" MY 2G_WORLD Local Test + +"MaltaL" MT 2G_WORLD 5G_ETSI1 CE + +"Mexico" MX 2G_WORLD 5G_FCC3 Local Test + +"Morocco" MA CE TCF + +"Netherlands" NL 2G_WORLD 5G_ETSI1 CE + +"New Zealandæ" NZ 2G_WORLD 5G_ETSI2 + +"Norway" NO 2G_WORLD 5G_ETSI1 CE + +"Panamaڮ " PA 2G_FCC1 Voluntary + +"Philippines߻" PH 2G_WORLD FCC TCF + +"Polandi" PL 2G_WORLD 5G_ETSI1 CE + +"Portugal" PT 2G_WORLD 5G_ETSI1 CE + +"Romaniaù" RO 2G_WORLD 5G_ETSI1 CE + +"RussiaXù" RU 2G_WORLD 5G_ETSI3 CE TCF + +"Saudi ArabiaFaԧB" SA 2G_WORLD CE TCF + +"Singapores[Y" SG 2G_WORLD + +"SlovakiaJ" SK 2G_WORLD 5G_ETSI1 CE + +"Slovenia" SI 2G_WORLD 5G_ETSI1 CE + +"South AfricanD" ZA 2G_WORLD CE TCF + +"SpainZ" ES 5G_ETSI1 CE + +"Sweden" SE 2G_WORLD 5G_ETSI1 CE + +"Switzerlandh" CH 2G_WORLD 5G_ETSI1 CE + +"TaiwanOW" TW 2G_FCC1 5G_NCC1 NCC + +"Thailand" TH 2G_WORLD FCC/CE TCF + +"Turkeygը" TR 2G_WORLD + +"UkraineQJ" UA 2G_WORLD Local Test + +"United Kingdom^" GB 2G_WORLD 5G_ETSI1 CE ETSI + +"United States" US 2G_FCC1 5G_FCC7 FCC FCC + +"Venezuelae" VE 2G_WORLD 5G_FCC4 FCC TCF + +"VietnamVn" VN 2G_WORLD FCC/CE TCF + + + +*/ + +// Counter abbervation. +typedef enum _RT_COUNTRY_DEFINE_NUM +{ + RT_CTRY_AL, // "Albaniaڥ" + RT_CTRY_DZ, // "AlgeriaΧQ" + RT_CTRY_AG, // "Antigua & Barbudawʮq&ڥF" + RT_CTRY_AR, // "Argentinaڧ" + RT_CTRY_AM, // "ArmeniaȬ" + RT_CTRY_AW, // "Aruba|ڮq" + RT_CTRY_AU, // "AustraliaDw" + RT_CTRY_AT, // "AustriaaQ" + RT_CTRY_AZ, // "Azerbaijan" + RT_CTRY_BS, // "Bahamasګ" + RT_CTRY_BB, // "Barbadosڤڦh" + RT_CTRY_BE, // "BelgiumQ" + RT_CTRY_BM, // "Bermudaʼ}F" + RT_CTRY_BR, // "Brazilڦ" + RT_CTRY_BG, // "BulgariaO[Q" + RT_CTRY_CA, // "Canada[j" + RT_CTRY_KY, // "Cayman Islands}Ҹsq" + RT_CTRY_CL, // "ChileQ" + RT_CTRY_CN, // "China" + RT_CTRY_CO, // "Columbiaۤ" + RT_CTRY_CR, // "Costa RicaF[" + RT_CTRY_CY, // "Cyprus" + RT_CTRY_CZ, // "Czech J" + RT_CTRY_DK, // "Denmark" + RT_CTRY_DO, // "Dominican Republich[@M" + RT_CTRY_CE, // "EgyptJ" EG 2G_WORLD + RT_CTRY_SV, // "El Salvadorĺ˦h" + RT_CTRY_EE, // "EstoniaRF" + RT_CTRY_FI, // "Finland" + RT_CTRY_FR, // "Francek" + RT_CTRY_DE, // "Germanyw" + RT_CTRY_GR, // "Greece þ" + RT_CTRY_GU, // "Guamq" + RT_CTRY_GT, // "Guatemalaʦa" + RT_CTRY_HT, // "Haitia" + RT_CTRY_HN, // "HondurasԴ" + RT_CTRY_HU, // "HungaryIQ" + RT_CTRY_IS, // "IcelandBq" + RT_CTRY_IN, // "IndiaL" + RT_CTRY_IE, // "IrelandR" + RT_CTRY_IL, // "IsraelHC" + RT_CTRY_IT, // "ItalyqjQ" + RT_CTRY_JP, // "Japan饻" + RT_CTRY_KR, // "Korea" + RT_CTRY_LV, // "LatviaԲ" + RT_CTRY_LT, // "Lithuania߳{" + RT_CTRY_LU, // "Luxembourgc˳" + RT_CTRY_MY, // "MalaysiaӦ" + RT_CTRY_MT, // "MaltaL" + RT_CTRY_MX, // "Mexico" + RT_CTRY_MA, // "Morocco" + RT_CTRY_NL, // "Netherlands" + RT_CTRY_NZ, // "New Zealandæ" + RT_CTRY_NO, // "Norway" + RT_CTRY_PA, // "Panamaڮ " + RT_CTRY_PH, // "Philippines߻" + RT_CTRY_PL, // "Polandi" + RT_CTRY_PT, // "Portugal" + RT_CTRY_RO, // "Romaniaù" + RT_CTRY_RU, // "RussiaXù" + RT_CTRY_SA, // "Saudi ArabiaFaԧB" + RT_CTRY_SG, // "Singapores[Y" + RT_CTRY_SK, // "SlovakiaJ" + RT_CTRY_SI, // "Slovenia" + RT_CTRY_ZA, // "South AfricanD" + RT_CTRY_ES, // "SpainZ" + RT_CTRY_SE, // "Sweden" + RT_CTRY_CH, // "Switzerlandh" + RT_CTRY_TW, // "TaiwanOW" + RT_CTRY_TH, // "Thailand" + RT_CTRY_TR, // "Turkeygը" + RT_CTRY_UA, // "UkraineQJ" + RT_CTRY_GB, // "United Kingdom^" + RT_CTRY_US, // "United States" + RT_CTRY_VE, // "Venezuelae" + RT_CTRY_VN, // "VietnamVn" + RT_CTRY_MAX, // + +}RT_COUNTRY_NAME, *PRT_COUNTRY_NAME; + +// Scan type including active and passive scan. +typedef enum _RT_SCAN_TYPE_NEW +{ + SCAN_NULL, + SCAN_ACT, + SCAN_PAS, + SCAN_BOTH, +}RT_SCAN_TYPE_NEW, *PRT_SCAN_TYPE_NEW; + + +// Power table sample. + +typedef struct _RT_CHNL_PLAN_LIMIT +{ + u2Byte Chnl_Start; + u2Byte Chnl_end; + + u2Byte Freq_Start; + u2Byte Freq_end; +}RT_CHNL_PLAN_LIMIT, *PRT_CHNL_PLAN_LIMIT; + + +// +// 2.4G Regulatory Domains +// +typedef enum _RT_REGULATION_DOMAIN_2G +{ + RT_2G_NULL, + RT_2G_WORLD, + RT_2G_ETSI1, + RT_2G_FCC1, + RT_2G_MKK1, + RT_2G_ETSI2 + +}RT_REGULATION_2G, *PRT_REGULATION_2G; + + +//typedef struct _RT_CHANNEL_BEHAVIOR +//{ +// u1Byte Chnl; +// RT_SCAN_TYPE_NEW +// +//}RT_CHANNEL_BEHAVIOR, *PRT_CHANNEL_BEHAVIOR; + +//typedef struct _RT_CHANNEL_PLAN_TYPE +//{ +// RT_CHANNEL_BEHAVIOR +// u1Byte Chnl_num; +//}RT_CHNL_PLAN_TYPE, *PRT_CHNL_PLAN_TYPE; + +// +// 2.4G Channel Number +// Channel definition & number +// +#define CHNL_RT_2G_NULL \ + {0}, 0 +#define CHNL_RT_2G_WORLD \ + {1,2,3,4,5,6,7,8,9,10,11,12,13}, 13 +#define CHNL_RT_2G_WORLD_TEST \ + {1,2,3,4,5,6,7,8,9,10,11,12,13}, 13 + +#define CHNL_RT_2G_EFSI1 \ + {1,2,3,4,5,6,7,8,9,10,11,12,13}, 13 +#define CHNL_RT_2G_FCC1 \ + {1,2,3,4,5,6,7,8,9,10,11}, 11 +#define CHNL_RT_2G_MKK1 \ + {1,2,3,4,5,6,7,8,9,10,11,12,13,14}, 14 +#define CHNL_RT_2G_ETSI2 \ + {10,11,12,13}, 4 + +// +// 2.4G Channel Active or passive scan. +// +#define CHNL_RT_2G_NULL_SCAN_TYPE \ + {SCAN_NULL} +#define CHNL_RT_2G_WORLD_SCAN_TYPE \ + {1,1,1,1,1,1,1,1,1,1,1,0,0} +#define CHNL_RT_2G_EFSI1_SCAN_TYPE \ + {1,1,1,1,1,1,1,1,1,1,1,1,1} +#define CHNL_RT_2G_FCC1_SCAN_TYPE \ + {1,1,1,1,1,1,1,1,1,1,1} +#define CHNL_RT_2G_MKK1_SCAN_TYPE \ + {1,1,1,1,1,1,1,1,1,1,1,1,1,1} +#define CHNL_RT_2G_ETSI2_SCAN_TYPE \ + {1,1,1,1} + + +// +// 2.4G Band & Frequency Section +// Freqency start & end / band number +// +#define FREQ_RT_2G_NULL \ + {0}, 0 + // Passive scan CH 12, 13 +#define FREQ_RT_2G_WORLD \ + {2412, 2472}, 1 +#define FREQ_RT_2G_EFSI1 \ + {2412, 2472}, 1 +#define FREQ_RT_2G_FCC1 \ + {2412, 2462}, 1 +#define FREQ_RT_2G_MKK1 \ + {2412, 2484}, 1 +#define FREQ_RT_2G_ETSI2 \ + {2457, 2472}, 1 + + +// +// 5G Regulatory Domains +// +typedef enum _RT_REGULATION_DOMAIN_5G +{ + RT_5G_NULL, + RT_5G_WORLD, + RT_5G_ETSI1, + RT_5G_ETSI2, + RT_5G_ETSI3, + RT_5G_FCC1, + RT_5G_FCC2, + RT_5G_FCC3, + RT_5G_FCC4, + RT_5G_FCC5, + RT_5G_FCC6, + RT_5G_FCC7, + RT_5G_IC1, + RT_5G_KCC1, + RT_5G_MKK1, + RT_5G_MKK2, + RT_5G_MKK3, + RT_5G_NCC1, + +}RT_REGULATION_5G, *PRT_REGULATION_5G; + +// +// 5G Channel Number +// +#define CHNL_RT_5G_NULL \ + {0}, 0 +#define CHNL_RT_5G_WORLD \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19 +#define CHNL_RT_5G_ETSI1 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24 +#define CHNL_RT_5G_ETSI2 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,149,153,157,161,165}, 22 +#define CHNL_RT_5G_ETSI3 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24 +#define CHNL_RT_5G_FCC1 \ + {36,40,44,48,149,153,157,161,165}, 9 +#define CHNL_RT_5G_FCC2 \ + {36,40,44,48,52,56,60,64,149,153,157,161,165}, 13 +#define CHNL_RT_5G_FCC3 \ + {36,40,44,48,52,56,60,64,149,153,157,161}, 12 +#define CHNL_RT_5G_FCC4 \ + {149,153,157,161,165}, 5 +#define CHNL_RT_5G_FCC5 \ + {36,40,44,48,52,56,60,64}, 8 +#define CHNL_RT_5G_FCC6 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 +#define CHNL_RT_5G_FCC7 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 +#define CHNL_RT_5G_IC1 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,149,153,157,161,165}, 20 +#define CHNL_RT_5G_KCC1 \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19 +#define CHNL_RT_5G_MKK1 \ + {36,40,44,48,52,56,60,64}, 8 +#define CHNL_RT_5G_MKK2 \ + {100,104,108,112,116,120,124,128,132,136,140}, 11 +#define CHNL_RT_5G_MKK3 \ + {56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 24 +#define CHNL_RT_5G_NCC1 \ + {56,60,64,149,153,157,161,165}, 8 + +// +// 5G Channel Active or passive scan. +// +#define CHNL_RT_5G_NULL_SCAN_TYPE \ + {SCAN_NULL} +#define CHNL_RT_5G_WORLD_SCAN_TYPE \ + {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1} +#define CHNL_RT_5G_ETSI1_SCAN_TYPE \ + {1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1} +#define CHNL_RT_5G_ETSI2_SCAN_TYPE \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,149,153,157,161,165}, 22 +#define CHNL_RT_5G_ETSI3_SCAN_TYPE \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165}, 24 +#define CHNL_RT_5G_FCC1_SCAN_TYPE \ + {36,40,44,48,149,153,157,161,165}, 9 +#define CHNL_RT_5G_FCC2_SCAN_TYPE \ + {36,40,44,48,52,56,60,64,149,153,157,161,165}, 13 +#define CHNL_RT_5G_FCC3_SCAN_TYPE \ + {36,40,44,48,52,56,60,64,149,153,157,161}, 12 +#define CHNL_RT_5G_FCC4_SCAN_TYPE \ + {149,153,157,161,165}, 5 +#define CHNL_RT_5G_FCC5_SCAN_TYPE \ + {36,40,44,48,52,56,60,64}, 8 +#define CHNL_RT_5G_FCC6_SCAN_TYPE \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 +#define CHNL_RT_5G_FCC7_SCAN_TYPE \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 20 +#define CHNL_RT_5G_IC1_SCAN_TYPE \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,149,153,157,161,165}, 20 +#define CHNL_RT_5G_KCC1_SCAN_TYPE \ + {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140}, 19 +#define CHNL_RT_5G_MKK1_SCAN_TYPE \ + {36,40,44,48,52,56,60,64}, 8 +#define CHNL_RT_5G_MKK2_SCAN_TYPE \ + {100,104,108,112,116,120,124,128,132,136,140}, 11 +#define CHNL_RT_5G_MKK3_SCAN_TYPE \ + {56,60,64,100,104,108,112,116,136,140,149,153,157,161,165}, 24 +#define CHNL_RT_5G_NCC1_SCAN_TYPE \ + {56,60,64,149,153,157,161,165}, 8 + +// +// Global Regulation +// +typedef enum _RT_REGULATION_COMMON +{ + RT_WORLD, + RT_FCC, + RT_MKK, + RT_ETSI, + RT_IC, + RT_CE, + RT_NCC, + +}RT_REGULATION_CMN, *PRT_REGULATION_CMN; + + + +// +// Special requirement for different regulation domain. +// For internal test or customerize special request. +// +typedef enum _RT_CHNLPLAN_SREQ +{ + RT_SREQ_NA = 0x0, + RT_SREQ_2G_ADHOC_11N = 0x00000001, + RT_SREQ_2G_ADHOC_11B = 0x00000002, + RT_SREQ_2G_ALL_PASS = 0x00000004, + RT_SREQ_2G_ALL_ACT = 0x00000008, + RT_SREQ_5G_ADHOC_11N = 0x00000010, + RT_SREQ_5G_ADHOC_11AC = 0x00000020, + RT_SREQ_5G_ALL_PASS = 0x00000040, + RT_SREQ_5G_ALL_ACT = 0x00000080, + RT_SREQ_C1_PLAN = 0x00000100, + RT_SREQ_C2_PLAN = 0x00000200, + RT_SREQ_C3_PLAN = 0x00000400, + RT_SREQ_C4_PLAN = 0x00000800, + RT_SREQ_NFC_ON = 0x00001000, + RT_SREQ_MASK = 0x0000FFFF, /* Requirements bit mask */ + +}RT_CHNLPLAN_SREQ, *PRT_CHNLPLAN_SREQ; + + +// +// RT_COUNTRY_NAME & RT_REGULATION_2G & RT_REGULATION_5G transfer table +// +// +typedef struct _RT_CHANNEL_PLAN_COUNTRY_TRANSFER_TABLE +{ + // + // Define countery domain and corresponding + // + RT_COUNTRY_NAME Country_Enum; + char Country_Name[3]; + + //char Domain_Name[12]; + RT_REGULATION_2G Domain_2G; + + RT_REGULATION_5G Domain_5G; + + RT_CHANNEL_DOMAIN RtChDomain; + //u1Byte Country_Area; + +}RT_CHNL_CTRY_TBL, *PRT_CHNL_CTRY_TBL; + + +#define RT_MAX_CHNL_NUM_2G 13 +#define RT_MAX_CHNL_NUM_5G 44 + +// Power table sample. + +typedef struct _RT_CHNL_PLAN_PWR_LIMIT +{ + u2Byte Chnl_Start; + u2Byte Chnl_end; + u1Byte dB_Max; + u2Byte mW_Max; +}RT_CHNL_PWR_LIMIT, *PRT_CHNL_PWR_LIMIT; + + +#define RT_MAX_BAND_NUM 5 + +typedef struct _RT_CHANNEL_PLAN_MAXPWR +{ +// STRING_T + RT_CHNL_PWR_LIMIT Chnl[RT_MAX_BAND_NUM]; + u1Byte Band_Useful_Num; + + +}RT_CHANNEL_PLAN_MAXPWR, *PRT_CHANNEL_PLAN_MAXPWR; + + +// +// Power By Rate Table. +// + + + +typedef struct _RT_CHANNEL_PLAN_NEW +{ + // + // Define countery domain and corresponding + // + //char Country_Name[36]; + //u1Byte Country_Enum; + + //char Domain_Name[12]; + + + PRT_CHNL_CTRY_TBL pCtryTransfer; + + RT_CHANNEL_DOMAIN RtChDomain; + + RT_REGULATION_2G Domain_2G; + + RT_REGULATION_5G Domain_5G; + + RT_REGULATION_CMN Regulator; + + RT_CHNLPLAN_SREQ ChnlSreq; + + //RT_CHNL_PLAN_LIMIT RtChnl; + + u1Byte Chnl2G[MAX_CHANNEL_NUM]; // CHNL_RT_2G_WORLD + u1Byte Len2G; + u1Byte Chnl2GScanTp[MAX_CHANNEL_NUM]; // CHNL_RT_2G_WORLD_SCAN_TYPE + //u1Byte Freq2G[2]; // FREQ_RT_2G_WORLD + + u1Byte Chnl5G[MAX_CHANNEL_NUM]; + u1Byte Len5G; + u1Byte Chnl5GScanTp[MAX_CHANNEL_NUM]; + //u1Byte Freq2G[2]; // FREQ_RT_2G_WORLD + + RT_CHANNEL_PLAN_MAXPWR ChnlMaxPwr; + + +}RT_CHANNEL_PLAN_NEW, *PRT_CHANNEL_PLAN_NEW; + + +#endif // __RT_CHANNELPLAN_H__ + + + + + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/hal8188freg.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/hal8188freg.h new file mode 100644 index 000000000..6284f863b --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/hal8188freg.h @@ -0,0 +1,863 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/***************************************************************************** + * Copyright(c) 2009, RealTEK Technology Inc. All Right Reserved. + * + * Module: __INC_HAL8188FREG_H + * + * + * Note: 1. Define Mac register address and corresponding bit mask map + * + * + * Export: Constants, macro, functions(API), global variables(None). + * + * Abbrev: + * + * History: + * Data Who Remark + * + *****************************************************************************/ +#ifndef __INC_HAL8188FREG_H +#define __INC_HAL8188FREG_H + + + +//============================================================ +// +//============================================================ + +//----------------------------------------------------- +// +// 0x0000h ~ 0x00FFh System Configuration +// +//----------------------------------------------------- +#define REG_SYS_ISO_CTRL_8188F 0x0000 // 2 Byte +#define REG_SYS_FUNC_EN_8188F 0x0002 // 2 Byte +#define REG_APS_FSMCO_8188F 0x0004 // 4 Byte +#define REG_SYS_CLKR_8188F 0x0008 // 2 Byte +#define REG_9346CR_8188F 0x000A // 2 Byte +#define REG_EE_VPD_8188F 0x000C // 2 Byte +#define REG_AFE_MISC_8188F 0x0010 // 1 Byte +#define REG_SPS0_CTRL_8188F 0x0011 // 7 Byte +#define REG_SPS_OCP_CFG_8188F 0x0018 // 4 Byte +#define REG_RSV_CTRL_8188F 0x001C // 3 Byte +#define REG_RF_CTRL_8188F 0x001F // 1 Byte +#define REG_LPLDO_CTRL_8188F 0x0023 // 1 Byte +#define REG_AFE_XTAL_CTRL_8188F 0x0024 // 4 Byte +#define REG_AFE_PLL_CTRL_8188F 0x0028 // 4 Byte +#define REG_MAC_PLL_CTRL_EXT_8188F 0x002c // 4 Byte +#define REG_EFUSE_CTRL_8188F 0x0030 +#define REG_EFUSE_TEST_8188F 0x0034 +#define REG_PWR_DATA_8188F 0x0038 +#define REG_CAL_TIMER_8188F 0x003C +#define REG_ACLK_MON_8188F 0x003E +#define REG_GPIO_MUXCFG_8188F 0x0040 +#define REG_GPIO_IO_SEL_8188F 0x0042 +#define REG_MAC_PINMUX_CFG_8188F 0x0043 +#define REG_GPIO_PIN_CTRL_8188F 0x0044 +#define REG_GPIO_INTM_8188F 0x0048 +#define REG_LEDCFG0_8188F 0x004C +#define REG_LEDCFG1_8188F 0x004D +#define REG_LEDCFG2_8188F 0x004E +#define REG_LEDCFG3_8188F 0x004F +#define REG_FSIMR_8188F 0x0050 +#define REG_FSISR_8188F 0x0054 +#define REG_HSIMR_8188F 0x0058 +#define REG_HSISR_8188F 0x005c +#define REG_GPIO_EXT_CTRL 0x0060 +#define REG_MULTI_FUNC_CTRL_8188F 0x0068 +#define REG_GPIO_STATUS_8188F 0x006C +#define REG_SDIO_CTRL_8188F 0x0070 +#define REG_OPT_CTRL_8188F 0x0074 +#define REG_AFE_XTAL_CTRL_EXT_8188F 0x0078 +#define REG_MCUFWDL_8188F 0x0080 +#define REG_FW_DBG_STATUS_8188F 0x0088 +#define REG_FW_DBG_CTRL_8188F 0x008F +#define REG_WLLPS_CTRL_8188F 0x0090 +#define REG_HIMR0_8188F 0x00B0 +#define REG_HISR0_8188F 0x00B4 +#define REG_HIMR1_8188F 0x00B8 +#define REG_HISR1_8188F 0x00BC +#define REG_PMC_DBG_CTRL2_8188F 0x00CC +#define REG_EFUSE_BURN_GNT_8188F 0x00CF +#define REG_HPON_FSM_8188F 0x00EC +#define REG_SYS_CFG_8188F 0x00F0 +#define REG_SYS_CFG1_8188F 0x00FC +#define REG_ROM_VERSION 0x00FD + +//----------------------------------------------------- +// +// 0x0100h ~ 0x01FFh MACTOP General Configuration +// +//----------------------------------------------------- +#define REG_CR_8188F 0x0100 +#define REG_PBP_8188F 0x0104 +#define REG_PKT_BUFF_ACCESS_CTRL_8188F 0x0106 +#define REG_TRXDMA_CTRL_8188F 0x010C +#define REG_TRXFF_BNDY_8188F 0x0114 +#define REG_TRXFF_STATUS_8188F 0x0118 +#define REG_RXFF_PTR_8188F 0x011C +#define REG_CPWM_8188F 0x012F +#define REG_FWIMR_8188F 0x0130 +#define REG_FWISR_8188F 0x0134 +#define REG_FTIMR_8188F 0x0138 +#define REG_PKTBUF_DBG_CTRL_8188F 0x0140 +#define REG_RXPKTBUF_CTRL_8188F 0x0142 +#define REG_PKTBUF_DBG_DATA_L_8188F 0x0144 +#define REG_PKTBUF_DBG_DATA_H_8188F 0x0148 + +#define REG_TC0_CTRL_8188F 0x0150 +#define REG_TC1_CTRL_8188F 0x0154 +#define REG_TC2_CTRL_8188F 0x0158 +#define REG_TC3_CTRL_8188F 0x015C +#define REG_TC4_CTRL_8188F 0x0160 +#define REG_TCUNIT_BASE_8188F 0x0164 +#define REG_RSVD3_8188F 0x0168 +#define REG_32K_CAL_REG1_8188F 0x0198 +#define REG_C2HEVT_MSG_NORMAL_8188F 0x01A0 +#define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 +#define REG_C2hEVT_CMD_CONTENT_88XX 0x01A2 +#define REG_C2HEVT_CMD_LEN_88XX 0x01AE +#define REG_C2HEVT_CLEAR_8188F 0x01AF +#define REG_MCUTST_1_8188F 0x01C0 +#define REG_MCUTST_WOWLAN_8188F 0x01C7 +#define REG_FMETHR_8188F 0x01C8 +#define REG_HMETFR_8188F 0x01CC +#define REG_HMEBOX_0_8188F 0x01D0 +#define REG_HMEBOX_1_8188F 0x01D4 +#define REG_HMEBOX_2_8188F 0x01D8 +#define REG_HMEBOX_3_8188F 0x01DC +#define REG_LLT_INIT_8188F 0x01E0 +#define REG_HMEBOX_EXT0_8188F 0x01F0 +#define REG_HMEBOX_EXT1_8188F 0x01F4 +#define REG_HMEBOX_EXT2_8188F 0x01F8 +#define REG_HMEBOX_EXT3_8188F 0x01FC + +//----------------------------------------------------- +// +// 0x0200h ~ 0x027Fh TXDMA Configuration +// +//----------------------------------------------------- +#define REG_RQPN_8188F 0x0200 +#define REG_FIFOPAGE_8188F 0x0204 +#define REG_TDECTRL_8188F 0x0208 +#define REG_DWBCN0_CTRL_8188F REG_TDECTRL +#define REG_TXDMA_OFFSET_CHK_8188F 0x020C +#define REG_TXDMA_STATUS_8188F 0x0210 +#define REG_RQPN_NPQ_8188F 0x0214 +#define REG_AUTO_LLT_8188F 0x0224 +#define REG_TDECTRL1_8188F 0x0228 +#define REG_DWBCN1_CTRL_8188F 0x0228 + +//----------------------------------------------------- +// +// 0x0280h ~ 0x02FFh RXDMA Configuration +// +//----------------------------------------------------- +#define REG_RXDMA_AGG_PG_TH_8188F 0x0280 +#define REG_FW_UPD_RDPTR_8188F 0x0284 // FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 +#define REG_RXDMA_CONTROL_8188F 0x0286 // Control the RX DMA. +#define REG_RXPKT_NUM_8188F 0x0287 // The number of packets in RXPKTBUF. +#define REG_RXDMA_STATUS_8188F 0x0288 +#define REG_RXDMA_PRO_8188F 0x0290 +#define REG_EARLY_MODE_CONTROL_8188F 0x02BC +#define REG_RSVD5_8188F 0x02F0 +#define REG_RSVD6_8188F 0x02F4 + + +//----------------------------------------------------- +// +// 0x0300h ~ 0x03FFh PCIe +// +//----------------------------------------------------- +#define REG_PCIE_CTRL_REG_8188F 0x0300 +#define REG_INT_MIG_8188F 0x0304 // Interrupt Migration +#define REG_BCNQ_DESA_8188F 0x0308 // TX Beacon Descriptor Address +#define REG_HQ_DESA_8188F 0x0310 // TX High Queue Descriptor Address +#define REG_MGQ_DESA_8188F 0x0318 // TX Manage Queue Descriptor Address +#define REG_VOQ_DESA_8188F 0x0320 // TX VO Queue Descriptor Address +#define REG_VIQ_DESA_8188F 0x0328 // TX VI Queue Descriptor Address +#define REG_BEQ_DESA_8188F 0x0330 // TX BE Queue Descriptor Address +#define REG_BKQ_DESA_8188F 0x0338 // TX BK Queue Descriptor Address +#define REG_RX_DESA_8188F 0x0340 // RX Queue Descriptor Address +#define REG_DBI_WDATA_8188F 0x0348 // DBI Write Data +#define REG_DBI_RDATA_8188F 0x034C // DBI Read Data +#define REG_DBI_ADDR_8188F 0x0350 // DBI Address +#define REG_DBI_FLAG_8188F 0x0352 // DBI Read/Write Flag +#define REG_MDIO_WDATA_8188F 0x0354 // MDIO for Write PCIE PHY +#define REG_MDIO_RDATA_8188F 0x0356 // MDIO for Reads PCIE PHY +#define REG_MDIO_CTL_8188F 0x0358 // MDIO for Control +#define REG_DBG_SEL_8188F 0x0360 // Debug Selection Register +#define REG_PCIE_HRPWM_8188F 0x0361 //PCIe RPWM +#define REG_PCIE_HCPWM_8188F 0x0363 //PCIe CPWM +#define REG_PCIE_MULTIFET_CTRL_8188F 0x036A //PCIE Multi-Fethc Control + +#define REG_MGQ_TXBD_NUM_8188F 0x0380 + +// spec version 11 +//----------------------------------------------------- +// +// 0x0400h ~ 0x047Fh Protocol Configuration +// +//----------------------------------------------------- +#define REG_VOQ_INFORMATION_8188F 0x0400 +#define REG_VIQ_INFORMATION_8188F 0x0404 +#define REG_BEQ_INFORMATION_8188F 0x0408 +#define REG_BKQ_INFORMATION_8188F 0x040C +#define REG_MGQ_INFORMATION_8188F 0x0410 +#define REG_HGQ_INFORMATION_8188F 0x0414 +#define REG_BCNQ_INFORMATION_8188F 0x0418 +#define REG_TXPKT_EMPTY_8188F 0x041A + +#define REG_FWHW_TXQ_CTRL_8188F 0x0420 +#define REG_HWSEQ_CTRL_8188F 0x0423 +#define REG_TXPKTBUF_BCNQ_BDNY_8188F 0x0424 +#define REG_TXPKTBUF_MGQ_BDNY_8188F 0x0425 +#define REG_LIFECTRL_CTRL_8188F 0x0426 +#define REG_MULTI_BCNQ_OFFSET_8188F 0x0427 +#define REG_SPEC_SIFS_8188F 0x0428 +#define REG_RL_8188F 0x042A +#define REG_TXBF_CTRL_8188F 0x042C +#define REG_DARFRC_8188F 0x0430 +#define REG_RARFRC_8188F 0x0438 +#define REG_RRSR_8188F 0x0440 +#define REG_ARFR0_8188F 0x0444 +#define REG_ARFR1_8188F 0x044C +#define REG_CCK_CHECK_8188F 0x0454 +#define REG_AMPDU_MAX_TIME_8188F 0x0456 +#define REG_TXPKTBUF_BCNQ_BDNY1_8188F 0x0457 + +#define REG_AMPDU_MAX_LENGTH_8188F 0x0458 +#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8188F 0x045D +#define REG_NDPA_OPT_CTRL_8188F 0x045F +#define REG_FAST_EDCA_CTRL_8188F 0x0460 +#define REG_RD_RESP_PKT_TH_8188F 0x0463 +#define REG_DATA_SC_8188F 0x0483 +#define REG_TXRPT_START_OFFSET 0x04AC +#define REG_POWER_STAGE1_8188F 0x04B4 +#define REG_POWER_STAGE2_8188F 0x04B8 +#define REG_AMPDU_BURST_MODE_8188F 0x04BC +#define REG_PKT_VO_VI_LIFE_TIME_8188F 0x04C0 +#define REG_PKT_BE_BK_LIFE_TIME_8188F 0x04C2 +#define REG_STBC_SETTING_8188F 0x04C4 +#define REG_HT_SINGLE_AMPDU_8188F 0x04C7 +#define REG_PROT_MODE_CTRL_8188F 0x04C8 +#define REG_MAX_AGGR_NUM_8188F 0x04CA +#define REG_RTS_MAX_AGGR_NUM_8188F 0x04CB +#define REG_BAR_MODE_CTRL_8188F 0x04CC +#define REG_RA_TRY_RATE_AGG_LMT_8188F 0x04CF +#define REG_MACID_PKT_DROP0_8188F 0x04D0 +#define REG_MACID_PKT_SLEEP_8188F 0x04D4 + +//----------------------------------------------------- +// +// 0x0500h ~ 0x05FFh EDCA Configuration +// +//----------------------------------------------------- +#define REG_EDCA_VO_PARAM_8188F 0x0500 +#define REG_EDCA_VI_PARAM_8188F 0x0504 +#define REG_EDCA_BE_PARAM_8188F 0x0508 +#define REG_EDCA_BK_PARAM_8188F 0x050C +#define REG_BCNTCFG_8188F 0x0510 +#define REG_PIFS_8188F 0x0512 +#define REG_RDG_PIFS_8188F 0x0513 +#define REG_SIFS_CTX_8188F 0x0514 +#define REG_SIFS_TRX_8188F 0x0516 +#define REG_AGGR_BREAK_TIME_8188F 0x051A +#define REG_SLOT_8188F 0x051B +#define REG_TX_PTCL_CTRL_8188F 0x0520 +#define REG_TXPAUSE_8188F 0x0522 +#define REG_DIS_TXREQ_CLR_8188F 0x0523 +#define REG_RD_CTRL_8188F 0x0524 +// +// Format for offset 540h-542h: +// [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. +// [7:4]: Reserved. +// [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. +// [23:20]: Reserved +// Description: +// | +// |<--Setup--|--Hold------------>| +// --------------|---------------------- +// | +// TBTT +// Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. +// Described by Designer Tim and Bruce, 2011-01-14. +// +#define REG_TBTT_PROHIBIT_8188F 0x0540 +#define REG_RD_NAV_NXT_8188F 0x0544 +#define REG_NAV_PROT_LEN_8188F 0x0546 +#define REG_BCN_CTRL_8188F 0x0550 +#define REG_BCN_CTRL_1_8188F 0x0551 +#define REG_MBID_NUM_8188F 0x0552 +#define REG_DUAL_TSF_RST_8188F 0x0553 +#define REG_BCN_INTERVAL_8188F 0x0554 +#define REG_DRVERLYINT_8188F 0x0558 +#define REG_BCNDMATIM_8188F 0x0559 +#define REG_ATIMWND_8188F 0x055A +#define REG_USTIME_TSF_8188F 0x055C +#define REG_BCN_MAX_ERR_8188F 0x055D +#define REG_RXTSF_OFFSET_CCK_8188F 0x055E +#define REG_RXTSF_OFFSET_OFDM_8188F 0x055F +#define REG_TSFTR_8188F 0x0560 +#define REG_CTWND_8188F 0x0572 +#define REG_SECONDARY_CCA_CTRL_8188F 0x0577 +#define REG_PSTIMER_8188F 0x0580 +#define REG_TIMER0_8188F 0x0584 +#define REG_TIMER1_8188F 0x0588 +#define REG_ACMHWCTRL_8188F 0x05C0 +#define REG_SCH_TXCMD_8188F 0x05F8 + +//----------------------------------------------------- +// +// 0x0600h ~ 0x07FFh WMAC Configuration +// +//----------------------------------------------------- +#define REG_MAC_CR_8188F 0x0600 +#define REG_TCR_8188F 0x0604 +#define REG_RCR_8188F 0x0608 +#define REG_RX_PKT_LIMIT_8188F 0x060C +#define REG_RX_DLK_TIME_8188F 0x060D +#define REG_RX_DRVINFO_SZ_8188F 0x060F + +#define REG_MACID_8188F 0x0610 +#define REG_BSSID_8188F 0x0618 +#define REG_MAR_8188F 0x0620 +#define REG_MBIDCAMCFG_8188F 0x0628 + +#define REG_USTIME_EDCA_8188F 0x0638 +#define REG_MAC_SPEC_SIFS_8188F 0x063A +#define REG_RESP_SIFP_CCK_8188F 0x063C +#define REG_RESP_SIFS_OFDM_8188F 0x063E +#define REG_ACKTO_8188F 0x0640 +#define REG_CTS2TO_8188F 0x0641 +#define REG_EIFS_8188F 0x0642 + +#define REG_NAV_UPPER_8188F 0x0652 // unit of 128 +#define REG_TRXPTCL_CTL_8188F 0x0668 + +// Security +#define REG_CAMCMD_8188F 0x0670 +#define REG_CAMWRITE_8188F 0x0674 +#define REG_CAMREAD_8188F 0x0678 +#define REG_CAMDBG_8188F 0x067C +#define REG_SECCFG_8188F 0x0680 + +// Power +#define REG_WOW_CTRL_8188F 0x0690 +#define REG_PS_RX_INFO_8188F 0x0692 +#define REG_UAPSD_TID_8188F 0x0693 +#define REG_WKFMCAM_CMD_8188F 0x0698 +#define REG_WKFMCAM_NUM_8188F 0x0698 +#define REG_WKFMCAM_RWD_8188F 0x069C +#define REG_RXFLTMAP0_8188F 0x06A0 +#define REG_RXFLTMAP1_8188F 0x06A2 +#define REG_RXFLTMAP2_8188F 0x06A4 +#define REG_BCN_PSR_RPT_8188F 0x06A8 +#define REG_BT_COEX_TABLE_8188F 0x06C0 +#define REG_BFMER0_INFO_8188F 0x06E4 +#define REG_BFMER1_INFO_8188F 0x06EC +#define REG_CSI_RPT_PARAM_BW20_8188F 0x06F4 +#define REG_CSI_RPT_PARAM_BW40_8188F 0x06F8 +#define REG_CSI_RPT_PARAM_BW80_8188F 0x06FC + +// Hardware Port 2 +#define REG_MACID1_8188F 0x0700 +#define REG_BSSID1_8188F 0x0708 +#define REG_BFMEE_SEL_8188F 0x0714 +#define REG_SND_PTCL_CTRL_8188F 0x0718 + +// LTE_COEX +#define REG_LTECOEX_CTRL 0x07C0 +#define REG_LTECOEX_WRITE_DATA 0x07C4 + +//----------------------------------------------------- +// +// Redifine 8192C register definition for compatibility +// +//----------------------------------------------------- + +// TODO: use these definition when using REG_xxx naming rule. +// NOTE: DO NOT Remove these definition. Use later. +#define EFUSE_CTRL_8188F REG_EFUSE_CTRL_8188F // E-Fuse Control. +#define EFUSE_TEST_8188F REG_EFUSE_TEST_8188F // E-Fuse Test. +#define MSR_8188F (REG_CR_8188F + 2) // Media Status register +#define ISR_8188F REG_HISR0_8188F +#define TSFR_8188F REG_TSFTR_8188F // Timing Sync Function Timer Register. + +#define PBP_8188F REG_PBP_8188F + +// Redifine MACID register, to compatible prior ICs. +#define IDR0_8188F REG_MACID_8188F // MAC ID Register, Offset 0x0050-0x0053 +#define IDR4_8188F (REG_MACID_8188F + 4) // MAC ID Register, Offset 0x0054-0x0055 + + +// +// 9. Security Control Registers (Offset: ) +// +#define RWCAM_8188F REG_CAMCMD_8188F //IN 8190 Data Sheet is called CAMcmd +#define WCAMI_8188F REG_CAMWRITE_8188F // Software write CAM input content +#define RCAMO_8188F REG_CAMREAD_8188F // Software read/write CAM config +#define CAMDBG_8188F REG_CAMDBG_8188F +#define SECR_8188F REG_SECCFG_8188F //Security Configuration Register + + +//---------------------------------------------------------------------------- +// 8195 IMR/ISR bits (offset 0xB0, 8bits) +//---------------------------------------------------------------------------- +#define IMR_DISABLED_8188F 0 +// IMR DW0(0x00B0-00B3) Bit 0-31 +#define IMR_TIMER2_8188F BIT31 // Timeout interrupt 2 +#define IMR_TIMER1_8188F BIT30 // Timeout interrupt 1 +#define IMR_PSTIMEOUT_8188F BIT29 // Power Save Time Out Interrupt +#define IMR_GTINT4_8188F BIT28 // When GTIMER4 expires, this bit is set to 1 +#define IMR_GTINT3_8188F BIT27 // When GTIMER3 expires, this bit is set to 1 +#define IMR_TXBCN0ERR_8188F BIT26 // Transmit Beacon0 Error +#define IMR_TXBCN0OK_8188F BIT25 // Transmit Beacon0 OK +#define IMR_TSF_BIT32_TOGGLE_8188F BIT24 // TSF Timer BIT32 toggle indication interrupt +#define IMR_BCNDMAINT0_8188F BIT20 // Beacon DMA Interrupt 0 +#define IMR_BCNDERR0_8188F BIT16 // Beacon Queue DMA OK0 +#define IMR_HSISR_IND_ON_INT_8188F BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) +#define IMR_BCNDMAINT_E_8188F BIT14 // Beacon DMA Interrupt Extension for Win7 +#define IMR_ATIMEND_8188F BIT12 // CTWidnow End or ATIM Window End +#define IMR_C2HCMD_8188F BIT10 // CPU to Host Command INT Status, Write 1 clear +#define IMR_CPWM2_8188F BIT9 // CPU power Mode exchange INT Status, Write 1 clear +#define IMR_CPWM_8188F BIT8 // CPU power Mode exchange INT Status, Write 1 clear +#define IMR_HIGHDOK_8188F BIT7 // High Queue DMA OK +#define IMR_MGNTDOK_8188F BIT6 // Management Queue DMA OK +#define IMR_BKDOK_8188F BIT5 // AC_BK DMA OK +#define IMR_BEDOK_8188F BIT4 // AC_BE DMA OK +#define IMR_VIDOK_8188F BIT3 // AC_VI DMA OK +#define IMR_VODOK_8188F BIT2 // AC_VO DMA OK +#define IMR_RDU_8188F BIT1 // Rx Descriptor Unavailable +#define IMR_ROK_8188F BIT0 // Receive DMA OK + +// IMR DW1(0x00B4-00B7) Bit 0-31 +#define IMR_BCNDMAINT7_8188F BIT27 // Beacon DMA Interrupt 7 +#define IMR_BCNDMAINT6_8188F BIT26 // Beacon DMA Interrupt 6 +#define IMR_BCNDMAINT5_8188F BIT25 // Beacon DMA Interrupt 5 +#define IMR_BCNDMAINT4_8188F BIT24 // Beacon DMA Interrupt 4 +#define IMR_BCNDMAINT3_8188F BIT23 // Beacon DMA Interrupt 3 +#define IMR_BCNDMAINT2_8188F BIT22 // Beacon DMA Interrupt 2 +#define IMR_BCNDMAINT1_8188F BIT21 // Beacon DMA Interrupt 1 +#define IMR_BCNDOK7_8188F BIT20 // Beacon Queue DMA OK Interrup 7 +#define IMR_BCNDOK6_8188F BIT19 // Beacon Queue DMA OK Interrup 6 +#define IMR_BCNDOK5_8188F BIT18 // Beacon Queue DMA OK Interrup 5 +#define IMR_BCNDOK4_8188F BIT17 // Beacon Queue DMA OK Interrup 4 +#define IMR_BCNDOK3_8188F BIT16 // Beacon Queue DMA OK Interrup 3 +#define IMR_BCNDOK2_8188F BIT15 // Beacon Queue DMA OK Interrup 2 +#define IMR_BCNDOK1_8188F BIT14 // Beacon Queue DMA OK Interrup 1 +#define IMR_ATIMEND_E_8188F BIT13 // ATIM Window End Extension for Win7 +#define IMR_TXERR_8188F BIT11 // Tx Error Flag Interrupt Status, write 1 clear. +#define IMR_RXERR_8188F BIT10 // Rx Error Flag INT Status, Write 1 clear +#define IMR_TXFOVW_8188F BIT9 // Transmit FIFO Overflow +#define IMR_RXFOVW_8188F BIT8 // Receive FIFO Overflow + + + + + +/*=================================================================== +===================================================================== +Here the register defines are for 92C. When the define is as same with 92C, +we will use the 92C's define for the consistency +So the following defines for 92C is not entire!!!!!! +===================================================================== +=====================================================================*/ +/* +Based on Datasheet V33---090401 +Register Summary +Current IOREG MAP +0x0000h ~ 0x00FFh System Configuration (256 Bytes) +0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) +0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) +0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) +0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) +0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) +0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) +0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) +0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) +*/ +//---------------------------------------------------------------------------- +// 8195 (TXPAUSE) transmission pause (Offset 0x522, 8 bits) +//---------------------------------------------------------------------------- +/* +#define StopBecon BIT6 +#define StopHigh BIT5 +#define StopMgt BIT4 +#define StopVO BIT3 +#define StopVI BIT2 +#define StopBE BIT1 +#define StopBK BIT0 +*/ + + +//============================================================================ +// 8192C Regsiter Bit and Content definition +//============================================================================ +//----------------------------------------------------- +// +// 0x0000h ~ 0x00FFh System Configuration +// +//----------------------------------------------------- +/* +//2 SYS_ISO_CTRL +#define ISO_MD2PP BIT(0) +#define ISO_UA2USB BIT(1) +#define ISO_UD2CORE BIT(2) +#define ISO_PA2PCIE BIT(3) +#define ISO_PD2CORE BIT(4) +#define ISO_IP2MAC BIT(5) +#define ISO_DIOP BIT(6) +#define ISO_DIOE BIT(7) +#define ISO_EB2CORE BIT(8) +#define ISO_DIOR BIT(9) +#define PWC_EV12V BIT(15) + + +//2 SYS_FUNC_EN +#define FEN_BBRSTB BIT(0) +#define FEN_BB_GLB_RSTn BIT(1) +#define FEN_USBA BIT(2) +#define FEN_UPLL BIT(3) +#define FEN_USBD BIT(4) +#define FEN_DIO_PCIE BIT(5) +#define FEN_PCIEA BIT(6) +#define FEN_PPLL BIT(7) +#define FEN_PCIED BIT(8) +#define FEN_DIOE BIT(9) +#define FEN_CPUEN BIT(10) +#define FEN_DCORE BIT(11) +#define FEN_ELDR BIT(12) +#define FEN_DIO_RF BIT(13) +#define FEN_HWPDN BIT(14) +#define FEN_MREGEN BIT(15) + +//2 APS_FSMCO +#define PFM_LDALL BIT(0) +#define PFM_ALDN BIT(1) +#define PFM_LDKP BIT(2) +#define PFM_WOWL BIT(3) +#define EnPDN BIT(4) +#define PDN_PL BIT(5) +#define APFM_ONMAC BIT(8) +#define APFM_OFF BIT(9) +#define APFM_RSM BIT(10) +#define AFSM_HSUS BIT(11) +#define AFSM_PCIE BIT(12) +#define APDM_MAC BIT(13) +#define APDM_HOST BIT(14) +#define APDM_HPDN BIT(15) +#define RDY_MACON BIT(16) +#define SUS_HOST BIT(17) +#define ROP_ALD BIT(20) +#define ROP_PWR BIT(21) +#define ROP_SPS BIT(22) +#define SOP_MRST BIT(25) +#define SOP_FUSE BIT(26) +#define SOP_ABG BIT(27) +#define SOP_AMB BIT(28) +#define SOP_RCK BIT(29) +#define SOP_A8M BIT(30) +#define XOP_BTCK BIT(31) + +//2 SYS_CLKR +#define ANAD16V_EN BIT(0) +#define ANA8M BIT(1) +#define MACSLP BIT(4) +#define LOADER_CLK_EN BIT(5) + + +//2 9346CR + +#define BOOT_FROM_EEPROM BIT(4) +#define EEPROM_EN BIT(5) + + +//2 RF_CTRL +#define RF_EN BIT(0) +#define RF_RSTB BIT(1) +#define RF_SDMRSTB BIT(2) + +//2 LDOV12D_CTRL +#define LDV12_EN BIT(0) +#define LDV12_SDBY BIT(1) +#define LPLDO_HSM BIT(2) +#define LPLDO_LSM_DIS BIT(3) +#define _LDV12_VADJ(x) (((x) & 0xF) << 4) + + +//2 EFUSE_TEST (For RTL8188 partially) +#define EF_TRPT BIT(7) +#define EF_CELL_SEL (BIT(8)|BIT(9)) // 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 +#define LDOE25_EN BIT(31) +#define EFUSE_SEL(x) (((x) & 0x3) << 8) +#define EFUSE_SEL_MASK 0x300 +#define EFUSE_WIFI_SEL_0 0x0 +#define EFUSE_BT_SEL_0 0x1 +#define EFUSE_BT_SEL_1 0x2 +#define EFUSE_BT_SEL_2 0x3 + + +//2 8051FWDL +//2 MCUFWDL +#define MCUFWDL_EN BIT(0) +#define MCUFWDL_RDY BIT(1) +#define FWDL_ChkSum_rpt BIT(2) +#define MACINI_RDY BIT(3) +#define BBINI_RDY BIT(4) +#define RFINI_RDY BIT(5) +#define WINTINI_RDY BIT(6) +#define RAM_DL_SEL BIT(7) +#define ROM_DLEN BIT(19) +#define CPRST BIT(23) + + + +//2 REG_SYS_CFG +#define XCLK_VLD BIT(0) +#define ACLK_VLD BIT(1) +#define UCLK_VLD BIT(2) +#define PCLK_VLD BIT(3) +#define PCIRSTB BIT(4) +#define V15_VLD BIT(5) +#define TRP_B15V_EN BIT(7) +#define SIC_IDLE BIT(8) +#define BD_MAC2 BIT(9) +#define BD_MAC1 BIT(10) +#define IC_MACPHY_MODE BIT(11) +#define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) +#define BT_FUNC BIT(16) +#define VENDOR_ID BIT(19) +#define PAD_HWPD_IDN BIT(22) +#define TRP_VAUX_EN BIT(23) // RTL ID +#define TRP_BT_EN BIT(24) +#define BD_PKG_SEL BIT(25) +#define BD_HCI_SEL BIT(26) +#define TYPE_ID BIT(27) + +#define CHIP_VER_RTL_MASK 0xF000 //Bit 12 ~ 15 +#define CHIP_VER_RTL_SHIFT 12 + +*/ +//----------------------------------------------------- +// +// 0x0100h ~ 0x01FFh MACTOP General Configuration +// +//----------------------------------------------------- +/* + +//2 Function Enable Registers +//2 CR 0x0100-0x0103 + + +#define HCI_TXDMA_EN BIT(0) +#define HCI_RXDMA_EN BIT(1) +#define TXDMA_EN BIT(2) +#define RXDMA_EN BIT(3) +#define PROTOCOL_EN BIT(4) +#define SCHEDULE_EN BIT(5) +#define MACTXEN BIT(6) +#define MACRXEN BIT(7) +#define ENSWBCN BIT(8) +#define ENSEC BIT(9) +#define CALTMR_EN BIT(10) // 32k CAL TMR enable + +// Network type +#define _NETTYPE(x) (((x) & 0x3) << 16) +#define MASK_NETTYPE 0x30000 +#define NT_NO_LINK 0x0 +#define NT_LINK_AD_HOC 0x1 +#define NT_LINK_AP 0x2 +#define NT_AS_AP 0x3 + + +//2 PBP - Page Size Register 0x0104 +#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) +#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) +#define _PSRX_MASK 0xF +#define _PSTX_MASK 0xF0 +#define _PSRX(x) (x) +#define _PSTX(x) ((x) << 4) + +#define PBP_64 0x0 +#define PBP_128 0x1 +#define PBP_256 0x2 +#define PBP_512 0x3 +#define PBP_1024 0x4 + + +//2 TX/RXDMA 0x010C +#define RXDMA_ARBBW_EN BIT(0) +#define RXSHFT_EN BIT(1) +#define RXDMA_AGG_EN BIT(2) +#define QS_VO_QUEUE BIT(8) +#define QS_VI_QUEUE BIT(9) +#define QS_BE_QUEUE BIT(10) +#define QS_BK_QUEUE BIT(11) +#define QS_MANAGER_QUEUE BIT(12) +#define QS_HIGH_QUEUE BIT(13) + +#define HQSEL_VOQ BIT(0) +#define HQSEL_VIQ BIT(1) +#define HQSEL_BEQ BIT(2) +#define HQSEL_BKQ BIT(3) +#define HQSEL_MGTQ BIT(4) +#define HQSEL_HIQ BIT(5) + +// For normal driver, 0x10C +#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) +#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) +#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) +#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 ) +#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 ) +#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 ) + +#define QUEUE_LOW 1 +#define QUEUE_NORMAL 2 +#define QUEUE_HIGH 3 + + +//2 REG_C2HEVT_CLEAR 0x01AF +#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message +#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. + + + +//2 LLT_INIT 0x01E0 +#define _LLT_NO_ACTIVE 0x0 +#define _LLT_WRITE_ACCESS 0x1 +#define _LLT_READ_ACCESS 0x2 + +#define _LLT_INIT_DATA(x) ((x) & 0xFF) +#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) +#define _LLT_OP(x) (((x) & 0x3) << 30) +#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) + +*/ +//----------------------------------------------------- +// +// 0x0200h ~ 0x027Fh TXDMA Configuration +// +//----------------------------------------------------- +/* +//2 TDECTL 0x0208 +#define BLK_DESC_NUM_SHIFT 4 +#define BLK_DESC_NUM_MASK 0xF + + +//2 TXDMA_OFFSET_CHK 0x020C +#define DROP_DATA_EN BIT(9) +*/ +//----------------------------------------------------- +// +// 0x0280h ~ 0x028Bh RX DMA Configuration +// +//----------------------------------------------------- +/* +//2 REG_RXDMA_CONTROL, 0x0286h + +// Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before +// this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear. +#define RXPKT_RELEASE_POLL BIT(0) +// Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in +// this bit. FW can start releasing packets after RXDMA entering idle mode. +#define RXDMA_IDLE BIT(1) +// When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host +// completed, and stop DMA packet to host. RXDMA will then report Default: 0; +#define RW_RELEASE_EN BIT(2) +*/ +//----------------------------------------------------- +// +// 0x0400h ~ 0x047Fh Protocol Configuration +// +//----------------------------------------------------- +/* +//2 FWHW_TXQ_CTRL 0x0420 +#define EN_AMPDU_RTY_NEW BIT(7) + + +//2 REG_LIFECTRL_CTRL 0x0426 +#define HAL92C_EN_PKT_LIFE_TIME_BK BIT3 +#define HAL92C_EN_PKT_LIFE_TIME_BE BIT2 +#define HAL92C_EN_PKT_LIFE_TIME_VI BIT1 +#define HAL92C_EN_PKT_LIFE_TIME_VO BIT0 + +#define HAL92C_MSDU_LIFE_TIME_UNIT 128 // in us, said by Tim. + + +//2 SPEC SIFS 0x0428 +#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) +#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) + +//2 RL 0x042A +#define RETRY_LIMIT_SHORT_SHIFT 8 +#define RETRY_LIMIT_LONG_SHIFT 0 + +#define _LRL(x) ((x) & 0x3F) +#define _SRL(x) (((x) & 0x3F) << 8) +*/ + +//----------------------------------------------------- +// +// 0x0500h ~ 0x05FFh EDCA Configuration +// +//----------------------------------------------------- +/* +//2 EDCA setting 0x050C +#define AC_PARAM_TXOP_LIMIT_OFFSET 16 +#define AC_PARAM_ECW_MAX_OFFSET 12 +#define AC_PARAM_ECW_MIN_OFFSET 8 +#define AC_PARAM_AIFS_OFFSET 0 + + +//2 BCN_CTRL 0x0550 +#define EN_TXBCN_RPT BIT(2) +#define EN_BCN_FUNCTION BIT(3) + +//2 TxPause 0x0522 +#define STOP_BCNQ BIT(6) +*/ + + +//2 ACMHWCTRL 0x05C0 +#define AcmHw_HwEn_8188F BIT(0) +#define AcmHw_VoqEn_8188F BIT(1) +#define AcmHw_ViqEn_8188F BIT(2) +#define AcmHw_BeqEn_8188F BIT(3) +#define AcmHw_VoqStatus_8188F BIT(5) +#define AcmHw_ViqStatus_8188F BIT(6) +#define AcmHw_BeqStatus_8188F BIT(7) + + + +//----------------------------------------------------- +// +// 0x0600h ~ 0x07FFh WMAC Configuration +// +//----------------------------------------------------- +/* + +//2 TCR 0x0604 +#define DIS_GCLK BIT(1) +#define PAD_SEL BIT(2) +#define PWR_ST BIT(6) +#define PWRBIT_OW_EN BIT(7) +#define ACRC BIT(8) +#define CFENDFORM BIT(9) +#define ICV BIT(10) +*/ + +//---------------------------------------------------------------------------- +// 8195 (RCR) Receive Configuration Register (Offset 0x608, 32 bits) +//---------------------------------------------------------------------------- +/* +#define RCR_APPFCS BIT31 // WMAC append FCS after pauload +#define RCR_APP_MIC BIT30 // MACRX will retain the MIC at the bottom of the packet. +#define RCR_APP_ICV BIT29 // MACRX will retain the ICV at the bottom of the packet. +#define RCR_APP_PHYST_RXFF BIT28 // HY Status is appended before RX packet in RXFF +#define RCR_APP_BA_SSN BIT27 // SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. +#define RCR_RSVD_BIT26 BIT26 // Reserved +*/ +#define RCR_TCPOFLD_EN BIT25 // Enable TCP checksum offload + +#endif // #ifndef __INC_HAL8188FREG_H diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_bb.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_bb.c new file mode 100644 index 000000000..7465b885c --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_bb.c @@ -0,0 +1,594 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8188F_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +u4Byte Array_MP_8188F_AGC_TAB[] = { + 0xC78, 0xFC000001, + 0xC78, 0xFB010001, + 0xC78, 0xFA020001, + 0xC78, 0xF9030001, + 0xC78, 0xF8040001, + 0xC78, 0xF7050001, + 0xC78, 0xF6060001, + 0xC78, 0xF5070001, + 0xC78, 0xF4080001, + 0xC78, 0xF3090001, + 0xC78, 0xF20A0001, + 0xC78, 0xF10B0001, + 0xC78, 0xF00C0001, + 0xC78, 0xEF0D0001, + 0xC78, 0xEE0E0001, + 0xC78, 0xED0F0001, + 0xC78, 0xEC100001, + 0xC78, 0xEB110001, + 0xC78, 0xEA120001, + 0xC78, 0xE9130001, + 0xC78, 0xE8140001, + 0xC78, 0xE7150001, + 0xC78, 0xE6160001, + 0xC78, 0xE5170001, + 0xC78, 0xE4180001, + 0xC78, 0xE3190001, + 0xC78, 0xE21A0001, + 0xC78, 0xE11B0001, + 0xC78, 0xE01C0001, + 0xC78, 0xC21D0001, + 0xC78, 0xC11E0001, + 0xC78, 0xC01F0001, + 0xC78, 0xA5200001, + 0xC78, 0xA4210001, + 0xC78, 0xA3220001, + 0xC78, 0xA2230001, + 0xC78, 0xA1240001, + 0xC78, 0xA0250001, + 0xC78, 0x65260001, + 0xC78, 0x64270001, + 0xC78, 0x63280001, + 0xC78, 0x62290001, + 0xC78, 0x612A0001, + 0xC78, 0x442B0001, + 0xC78, 0x432C0001, + 0xC78, 0x422D0001, + 0xC78, 0x412E0001, + 0xC78, 0x402F0001, + 0xC78, 0x21300001, + 0xC78, 0x20310001, + 0xC78, 0x05320001, + 0xC78, 0x04330001, + 0xC78, 0x03340001, + 0xC78, 0x02350001, + 0xC78, 0x01360001, + 0xC78, 0x00370001, + 0xC78, 0x00380001, + 0xC78, 0x00390001, + 0xC78, 0x003A0001, + 0xC78, 0x003B0001, + 0xC78, 0x003C0001, + 0xC78, 0x003D0001, + 0xC78, 0x003E0001, + 0xC78, 0x003F0001, + 0xC50, 0x69553422, + 0xC50, 0x69553420, + +}; + +void +ODM_ReadAndConfig_MP_8188F_AGC_TAB( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8188F_AGC_TAB)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8188F_AGC_TAB; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188F_AGC_TAB\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_AGC_8188F(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8188F_AGC_TAB(void) +{ + return 31; +} + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +u4Byte Array_MP_8188F_PHY_REG[] = { + 0x800, 0x80045700, + 0x804, 0x00000001, + 0x808, 0x0000FC00, + 0x80C, 0x0000000A, + 0x810, 0x10001331, + 0x814, 0x020C3D10, + 0x818, 0x00200385, + 0x81C, 0x00000000, + 0x820, 0x01000100, + 0x824, 0x00390204, + 0x828, 0x00000000, + 0x82C, 0x00000000, + 0x830, 0x00000000, + 0x834, 0x00000000, + 0x838, 0x00000000, + 0x83C, 0x00000000, + 0x840, 0x00010000, + 0x844, 0x00000000, + 0x848, 0x00000000, + 0x84C, 0x00000000, + 0x850, 0x00030000, + 0x854, 0x00000000, + 0x858, 0x569A569A, + 0x85C, 0x569A569A, + 0x860, 0x00000130, + 0x864, 0x00000000, + 0x868, 0x00000000, + 0x86C, 0x27272700, + 0x870, 0x00000000, + 0x874, 0x25004000, + 0x878, 0x00000808, + 0x87C, 0x004F0201, + 0x880, 0xB0000B1E, + 0x884, 0x00000007, + 0x888, 0x00000000, + 0x88C, 0xCCC000C0, + 0x890, 0x00000800, + 0x894, 0xFFFFFFFE, + 0x898, 0x40302010, + 0x89C, 0x00706050, + 0x900, 0x00000000, + 0x904, 0x00000023, + 0x908, 0x00000000, + 0x90C, 0x81121111, + 0x910, 0x00000002, + 0x914, 0x00000201, + 0x948, 0x99000000, + 0x94C, 0x00000010, + 0x950, 0x20003000, + 0x954, 0x4A880000, + 0x958, 0x4BC5D87A, + 0x95C, 0x04EB9B79, + 0x96C, 0x00000003, + 0xA00, 0x00D047C8, + 0xA04, 0x80FF800C, + 0x80000400, 0x00000000, 0x40000000, 0x00000000, + 0xA08, 0x8C038300, + 0xA0000000, 0x00000000, + 0xA08, 0x8C898300, + 0xB0000000, 0x00000000, + 0xA0C, 0x2E7F120F, + 0xA10, 0x9500BB78, + 0xA14, 0x1114D028, + 0xA18, 0x00881117, + 0xA1C, 0x89140F00, + 0xA20, 0xD1D80000, + 0xA24, 0x5A7DA0BD, + 0xA28, 0x0000223B, + 0xA2C, 0x00D30000, + 0xA70, 0x101FBF00, + 0xA74, 0x00000007, + 0x80000400, 0x00000000, 0x40000000, 0x00000000, + 0xA78, 0x00008900, + 0xA0000000, 0x00000000, + 0xA78, 0x00000900, + 0xB0000000, 0x00000000, + 0xA7C, 0x225B0606, + 0xA80, 0x218075B1, + 0xA84, 0x00120000, + 0xA88, 0x040C0000, + 0xA8C, 0x12345678, + 0xA90, 0xABCDEF00, + 0xA94, 0x001B1B89, + 0xA98, 0x05100000, + 0xA9C, 0x3F000000, + 0xAA0, 0x00000000, + 0xB2C, 0x00000000, + 0xC00, 0x48071D40, + 0xC04, 0x03A05611, + 0xC08, 0x000000E4, + 0xC0C, 0x6C6C6C6C, + 0xC10, 0x18800000, + 0xC14, 0x40000100, + 0xC18, 0x08800000, + 0xC1C, 0x40000100, + 0xC20, 0x00000000, + 0xC24, 0x00000000, + 0xC28, 0x00000000, + 0xC2C, 0x00000000, + 0xC30, 0x69E9CC4A, + 0xC34, 0x31000040, + 0xC38, 0x21688080, + 0xC3C, 0x00001714, + 0xC40, 0x1F78403F, + 0xC44, 0x00010036, + 0xC48, 0xEC020107, + 0xC4C, 0x007F037F, + 0xC50, 0x69553420, + 0xC54, 0x43BC0094, + 0xC58, 0x00013169, + 0xC5C, 0x00250492, + 0xC60, 0x00000000, + 0xC64, 0x7112848B, + 0xC68, 0x47C07BFF, + 0xC6C, 0x00000036, + 0xC70, 0x2C7F000D, + 0xC74, 0x020600DB, + 0xC78, 0x0000001F, + 0xC7C, 0x00B91612, + 0xC80, 0x390000E4, + 0x80000400, 0x00000000, 0x40000000, 0x00000000, + 0xC84, 0x21F60000, + 0xA0000000, 0x00000000, + 0xC84, 0x11F60000, + 0xB0000000, 0x00000000, + 0xC88, 0x40000100, + 0xC8C, 0x20200000, + 0xC90, 0x00091521, + 0xC94, 0x00000000, + 0xC98, 0x00121820, + 0xC9C, 0x00007F7F, + 0xCA0, 0x00000000, + 0xCA4, 0x000300A0, + 0xCA8, 0x00000000, + 0xCAC, 0x00000000, + 0xCB0, 0x00000000, + 0xCB4, 0x00000000, + 0xCB8, 0x00000000, + 0xCBC, 0x28000000, + 0xCC0, 0x00000000, + 0xCC4, 0x00000000, + 0xCC8, 0x00000000, + 0xCCC, 0x00000000, + 0xCD0, 0x00000000, + 0xCD4, 0x00000000, + 0xCD8, 0x64B22427, + 0xCDC, 0x00766932, + 0xCE0, 0x00222222, + 0xCE4, 0x10000000, + 0xCE8, 0x37644302, + 0xCEC, 0x2F97D40C, + 0xD00, 0x04030740, + 0xD04, 0x40020401, + 0xD08, 0x0000907F, + 0xD0C, 0x20010201, + 0xD10, 0xA0633333, + 0xD14, 0x3333BC53, + 0xD18, 0x7A8F5B6F, + 0xD2C, 0xCB979975, + 0xD30, 0x00000000, + 0xD34, 0x80608000, + 0xD38, 0x98000000, + 0xD3C, 0x40127353, + 0xD40, 0x00000000, + 0xD44, 0x00000000, + 0xD48, 0x00000000, + 0xD4C, 0x00000000, + 0xD50, 0x6437140A, + 0xD54, 0x00000000, + 0xD58, 0x00000282, + 0xD5C, 0x30032064, + 0xD60, 0x4653DE68, + 0xD64, 0x04518A3C, + 0xD68, 0x00002101, + 0xD6C, 0x2A201C16, + 0xD70, 0x1812362E, + 0xD74, 0x322C2220, + 0xD78, 0x000E3C24, + 0xE00, 0x2D2D2D2D, + 0xE04, 0x2D2D2D2D, + 0xE08, 0x0390272D, + 0xE10, 0x2D2D2D2D, + 0xE14, 0x2D2D2D2D, + 0xE18, 0x2D2D2D2D, + 0xE1C, 0x2D2D2D2D, + 0xE28, 0x00000000, + 0xE30, 0x1000DC1F, + 0xE34, 0x10008C1F, + 0xE38, 0x02140102, + 0xE3C, 0x681604C2, + 0xE40, 0x01007C00, + 0xE44, 0x01004800, + 0xE48, 0xFB000000, + 0xE4C, 0x000028D1, + 0xE50, 0x1000DC1F, + 0xE54, 0x10008C1F, + 0xE58, 0x02140102, + 0xE5C, 0x28160D05, + 0xE60, 0x00000008, + 0xE60, 0x021400A0, + 0xE64, 0x281600A0, + 0xE6C, 0x01C00010, + 0xE70, 0x01C00010, + 0xE74, 0x02000010, + 0xE78, 0x02000010, + 0xE7C, 0x02000010, + 0xE80, 0x02000010, + 0xE84, 0x01C00010, + 0xE88, 0x02000010, + 0xE8C, 0x01C00010, + 0xED0, 0x01C00010, + 0xED4, 0x01C00010, + 0xED8, 0x01C00010, + 0xEDC, 0x00000010, + 0xEE0, 0x00000010, + 0xEEC, 0x03C00010, + 0xF14, 0x00000003, + 0xF4C, 0x00000000, + 0xF00, 0x00000300, + +}; + +void +ODM_ReadAndConfig_MP_8188F_PHY_REG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8188F_PHY_REG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8188F_PHY_REG; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188F_PHY_REG\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigBB_PHY_8188F(pDM_Odm, v1, bMaskDWord, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8188F_PHY_REG(void) +{ + return 31; +} + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +u4Byte Array_MP_8188F_PHY_REG_PG[] = { + 0, 0, 0, 0x00000e08, 0x0000ff00, 0x00003200, + 0, 0, 0, 0x0000086c, 0xffffff00, 0x32323200, + 0, 0, 0, 0x00000e00, 0xffffffff, 0x34363636, + 0, 0, 0, 0x00000e04, 0xffffffff, 0x28303234, + 0, 0, 0, 0x00000e10, 0xffffffff, 0x30343434, + 0, 0, 0, 0x00000e14, 0xffffffff, 0x26262830 +}; + +void +ODM_ReadAndConfig_MP_8188F_PHY_REG_PG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8188F_PHY_REG_PG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8188F_PHY_REG_PG; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrByRate, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrByRate = ArrayLen/6; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188F_PHY_REG_PG\n")); + + pDM_Odm->PhyRegPgVersion = 1; + pDM_Odm->PhyRegPgValueType = PHY_REG_PG_EXACT_VALUE; + + for (i = 0; i < ArrayLen; i += 6) { + u4Byte v1 = Array[i]; + u4Byte v2 = Array[i+1]; + u4Byte v3 = Array[i+2]; + u4Byte v4 = Array[i+3]; + u4Byte v5 = Array[i+4]; + u4Byte v6 = Array[i+5]; + + odm_ConfigBB_PHY_REG_PG_8188F(pDM_Odm, v1, v2, v3, v4, v5, v6); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrByRate[i/6], 100, "%s, %s, %s, 0x%X, 0x%08X, 0x%08X,", + (v1 == 0?"2.4G":" 5G"), (v2 == 0?"A":"B"), (v3 == 0?"1Tx":"2Tx"), v4, v5, v6); +#endif + } +} + + + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_bb.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_bb.h new file mode 100644 index 000000000..f0a4aa015 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_bb.h @@ -0,0 +1,59 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#if (RTL8188F_SUPPORT == 1) +#ifndef __INC_MP_BB_HW_IMG_8188F_H +#define __INC_MP_BB_HW_IMG_8188F_H + + +/****************************************************************************** +* AGC_TAB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188F_AGC_TAB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188F_AGC_TAB(void); + +/****************************************************************************** +* PHY_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188F_PHY_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188F_PHY_REG(void); + +/****************************************************************************** +* PHY_REG_PG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188F_PHY_REG_PG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188F_PHY_REG_PG(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_fw.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_fw.c new file mode 100644 index 000000000..505a9ea77 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_fw.c @@ -0,0 +1,2683 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8188F_SUPPORT == 1) + + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) || (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + + +u1Byte Array_MP_8188F_FW_NIC[] = { +0xF1, 0x88, 0x10, 0x00, 0x04, 0x00, 0x00, 0x00, +0x08, 0x22, 0x17, 0x36, 0xFC, 0x51, 0x02, 0x00, +0xBC, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x87, 0x7D, 0x02, 0xC8, 0x55, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0xB5, 0x27, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0xC8, 0xA7, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0xC8, 0x56, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0xC2, 0x21, 0x00, 0x00, +0x00, 0x00, 0x00, 0x02, 0xC8, 0xA6, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x02, 0x88, 0x18, 0x02, 0x8A, 0xD9, 0x02, 0x80, +0x86, 0x02, 0x80, 0x89, 0x02, 0xA9, 0x59, 0x02, +0xA3, 0x0C, 0x02, 0xB6, 0x62, 0x02, 0x80, 0x95, +0x02, 0x80, 0x98, 0x02, 0x80, 0x9B, 0x02, 0x80, +0x9E, 0x02, 0x80, 0xA1, 0x02, 0x80, 0xA4, 0x02, +0x80, 0xA7, 0x02, 0x80, 0xAA, 0x02, 0x80, 0xAD, +0x02, 0x80, 0xB0, 0x02, 0xA0, 0x3D, 0x02, 0x80, +0xB6, 0x02, 0x80, 0xB9, 0x02, 0xB3, 0x1B, 0x02, +0xB8, 0xCD, 0x02, 0xB8, 0x52, 0x02, 0xB7, 0xF9, +0x02, 0xB1, 0x62, 0x02, 0xB3, 0x7C, 0x02, 0x80, +0xCE, 0x02, 0x80, 0xD1, 0x02, 0x80, 0xD4, 0x02, +0x80, 0xD7, 0x00, 0x00, 0x00, 0x02, 0x80, 0xDD, +0x02, 0x80, 0xE0, 0x02, 0x80, 0xE3, 0x02, 0x80, +0xE6, 0x02, 0x80, 0xE9, 0x02, 0x80, 0xEC, 0x02, +0x80, 0xEF, 0x02, 0x80, 0xF2, 0x02, 0x80, 0xF5, +0x02, 0x80, 0xF8, 0x02, 0x80, 0xFB, 0x02, 0x80, +0xFE, 0x02, 0x81, 0x01, 0x02, 0x81, 0x04, 0x02, +0x81, 0x07, 0x02, 0x81, 0x0A, 0x02, 0x81, 0x0D, +0x02, 0x81, 0x10, 0x02, 0x81, 0x13, 0x02, 0x81, +0x16, 0x02, 0x81, 0x19, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x02, 0xBF, 0x8B, 0x02, +0xC9, 0x2D, 0x02, 0x96, 0xEE, 0x02, 0x98, 0xE3, +0x02, 0x81, 0x40, 0x02, 0xA4, 0x6B, 0x02, 0xCD, +0xF1, 0x02, 0x81, 0x49, 0x02, 0x81, 0x4C, 0x02, +0x81, 0x4F, 0x02, 0x81, 0x52, 0x02, 0x81, 0x55, +0x02, 0x81, 0x58, 0x02, 0x81, 0x5B, 0x02, 0x99, +0xF8, 0x02, 0x81, 0x61, 0x02, 0x81, 0x64, 0x02, +0xC6, 0xB7, 0x02, 0xCF, 0xE8, 0x02, 0xD0, 0x1D, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x15, 0xF0, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x15, +0xF0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x05, 0xF0, +0xFF, 0x0F, 0x00, 0x00, 0x00, 0x05, 0xF0, 0x0F, +0x00, 0x00, 0x00, 0x00, 0x10, 0xF0, 0xFF, 0x0F, +0x00, 0x00, 0x00, 0x10, 0xF0, 0x0F, 0x00, 0x00, +0x00, 0x00, 0xF5, 0x0F, 0x00, 0x00, 0x00, 0x00, +0x00, 0xF0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, +0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, +0x08, 0x03, 0x03, 0x00, 0x04, 0x09, 0x07, 0x03, +0x03, 0x00, 0x04, 0x08, 0x06, 0x03, 0x02, 0x00, +0x04, 0x08, 0x05, 0x03, 0x01, 0x00, 0x04, 0x0D, +0x0A, 0x07, 0x05, 0x00, 0x08, 0x0C, 0x0A, 0x07, +0x04, 0x00, 0x08, 0x0B, 0x0A, 0x06, 0x05, 0x00, +0x08, 0x0B, 0x0A, 0x05, 0x03, 0x00, 0x08, 0x0B, +0x0A, 0x03, 0x02, 0x00, 0x08, 0x14, 0x12, 0x0C, +0x04, 0x00, 0x10, 0x14, 0x12, 0x09, 0x04, 0x00, +0x10, 0x24, 0x22, 0x1C, 0x12, 0x00, 0x20, 0x24, +0x22, 0x18, 0x0C, 0x00, 0x20, 0x24, 0x22, 0x14, +0x06, 0x00, 0x20, 0x24, 0x22, 0x0F, 0x04, 0x00, +0x20, 0x24, 0x21, 0x0A, 0x04, 0x00, 0x20, 0x23, +0x21, 0x0C, 0x04, 0x00, 0x20, 0x23, 0x1F, 0x0A, +0x04, 0x00, 0x20, 0x22, 0x1F, 0x0F, 0x04, 0x00, +0x20, 0x21, 0x1F, 0x16, 0x0C, 0x00, 0x20, 0x31, +0x2F, 0x20, 0x14, 0x00, 0x30, 0x31, 0x2F, 0x18, +0x10, 0x00, 0x30, 0x31, 0x2C, 0x18, 0x0C, 0x00, +0x30, 0x31, 0x2A, 0x14, 0x0C, 0x00, 0x30, 0x31, +0x28, 0x14, 0x00, 0x00, 0x30, 0x31, 0x24, 0x14, +0x00, 0x00, 0x30, 0x31, 0x1E, 0x14, 0x00, 0x00, +0x30, 0x02, 0x02, 0x03, 0x04, 0x04, 0x08, 0x09, +0x09, 0x0C, 0x0E, 0x10, 0x12, 0x02, 0x09, 0x0B, +0x0E, 0x0D, 0x0F, 0x10, 0x12, 0x00, 0x04, 0x00, +0x04, 0x00, 0x08, 0x00, 0x10, 0x00, 0x23, 0x00, +0x2D, 0x00, 0x50, 0x00, 0x91, 0x00, 0xC3, 0x01, +0x27, 0x01, 0x31, 0x01, 0x5E, 0x00, 0x8C, 0x00, +0xC8, 0x00, 0xDC, 0x01, 0x5E, 0x01, 0x68, 0x01, +0x9A, 0x01, 0xCC, 0x01, 0xEA, 0x02, 0x02, 0x04, +0x08, 0x0C, 0x12, 0x18, 0x24, 0x30, 0x48, 0x60, +0x6C, 0x14, 0x28, 0x32, 0x50, 0x78, 0xA0, 0xC8, +0xE6, 0x01, 0x01, 0x01, 0x02, 0x01, 0x01, 0x02, +0x02, 0x03, 0x03, 0x04, 0x04, 0x02, 0x04, 0x06, +0x07, 0x07, 0x08, 0x08, 0x08, 0x01, 0x01, 0x01, +0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, +0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x02, +0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, +0x02, 0x03, 0x03, 0x04, 0x05, 0x01, 0x02, 0x03, +0x04, 0x05, 0x06, 0x07, 0x08, 0x03, 0x03, 0x03, +0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x02, 0x02, +0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, +0x02, 0x19, 0x06, 0x04, 0x02, 0x00, 0x18, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +0xC2, 0xAF, 0x80, 0xFE, 0x32, 0x12, 0x84, 0x04, +0x85, 0xD0, 0x0B, 0x75, 0xD0, 0x08, 0xAA, 0xE0, +0xC2, 0x8C, 0xE5, 0x8A, 0x24, 0x67, 0xF5, 0x8A, +0xE5, 0x8C, 0x34, 0x79, 0xF5, 0x8C, 0xD2, 0x8C, +0xEC, 0x24, 0x87, 0xF8, 0xE6, 0xBC, 0x02, 0x02, +0x74, 0xFF, 0xC3, 0x95, 0x81, 0xB4, 0x40, 0x00, +0x40, 0xCE, 0x79, 0x03, 0x78, 0x80, 0x16, 0xE6, +0x08, 0x70, 0x0B, 0xC2, 0xAF, 0xE6, 0x30, 0xE1, +0x03, 0x44, 0x18, 0xF6, 0xD2, 0xAF, 0x08, 0xD9, +0xED, 0xEA, 0x8B, 0xD0, 0x22, 0xE5, 0x0C, 0xFF, +0x23, 0x24, 0x81, 0xF8, 0x0F, 0x08, 0x08, 0xBF, +0x03, 0x04, 0x7F, 0x00, 0x78, 0x81, 0xE6, 0x30, +0xE4, 0xF2, 0x00, 0xE5, 0x0C, 0xC3, 0x9F, 0x50, +0x20, 0x05, 0x0C, 0x74, 0x86, 0x25, 0x0C, 0xF8, +0xE6, 0xFD, 0xA6, 0x81, 0x08, 0xE6, 0xAE, 0x0C, +0xBE, 0x02, 0x02, 0x74, 0xFF, 0xCD, 0xF8, 0xE8, +0x6D, 0x60, 0xE0, 0x08, 0xE6, 0xC0, 0xE0, 0x80, +0xF6, 0xE5, 0x0C, 0xD3, 0x9F, 0x40, 0x27, 0xE5, +0x0C, 0x24, 0x87, 0xF8, 0xE6, 0xAE, 0x0C, 0xBE, +0x02, 0x02, 0x74, 0xFF, 0xFD, 0x18, 0xE6, 0xCD, +0xF8, 0xE5, 0x81, 0x6D, 0x60, 0x06, 0xD0, 0xE0, +0xF6, 0x18, 0x80, 0xF5, 0xE5, 0x0C, 0x24, 0x86, +0xC8, 0xF6, 0x15, 0x0C, 0x80, 0xD3, 0xE5, 0x0C, +0x23, 0x24, 0x81, 0xF8, 0x7F, 0x04, 0xC2, 0xAF, +0xE6, 0x30, 0xE0, 0x03, 0x10, 0xE2, 0x0C, 0x7F, +0x00, 0x30, 0xE1, 0x07, 0x30, 0xE3, 0x04, 0x7F, +0x08, 0x54, 0xF4, 0x54, 0x7C, 0xC6, 0xD2, 0xAF, +0x54, 0x80, 0x42, 0x07, 0x22, 0x78, 0x86, 0xA6, +0x81, 0x74, 0x02, 0x60, 0x06, 0xFF, 0x08, 0x76, +0xFF, 0xDF, 0xFB, 0x7F, 0x03, 0xE4, 0x78, 0x80, +0xF6, 0x08, 0xF6, 0x08, 0xDF, 0xFA, 0x78, 0x81, +0x76, 0x30, 0x90, 0x88, 0x0D, 0x74, 0x01, 0x93, +0xC0, 0xE0, 0xE4, 0x93, 0xC0, 0xE0, 0x43, 0x89, +0x01, 0x75, 0x8A, 0x60, 0x75, 0x8C, 0x79, 0xD2, +0x8C, 0xD2, 0xAF, 0x22, 0x02, 0xEF, 0xD3, 0x94, +0x02, 0x40, 0x03, 0x7F, 0xFF, 0x22, 0x74, 0x81, +0x2F, 0x2F, 0xF8, 0xE6, 0x20, 0xE5, 0xF4, 0xC2, +0xAF, 0xE6, 0x44, 0x30, 0xF6, 0xD2, 0xAF, 0xAE, +0x0C, 0xEE, 0xC3, 0x9F, 0x50, 0x21, 0x0E, 0x74, +0x86, 0x2E, 0xF8, 0xE6, 0xF9, 0x08, 0xE6, 0x18, +0xBE, 0x02, 0x02, 0x74, 0xFF, 0xFD, 0xED, 0x69, +0x60, 0x09, 0x09, 0xE7, 0x19, 0x19, 0xF7, 0x09, +0x09, 0x80, 0xF3, 0x16, 0x16, 0x80, 0xDA, 0xEE, +0xD3, 0x9F, 0x40, 0x04, 0x05, 0x81, 0x05, 0x81, +0xEE, 0xD3, 0x9F, 0x40, 0x22, 0x74, 0x86, 0x2E, +0xF8, 0x08, 0xE6, 0xF9, 0xEE, 0xB5, 0x0C, 0x02, +0xA9, 0x81, 0x18, 0x06, 0x06, 0xE6, 0xFD, 0xED, +0x69, 0x60, 0x09, 0x19, 0x19, 0xE7, 0x09, 0x09, +0xF7, 0x19, 0x80, 0xF3, 0x1E, 0x80, 0xD9, 0xEF, +0x24, 0x86, 0xF8, 0xE6, 0x04, 0xF8, 0xEF, 0x2F, +0x04, 0x90, 0x88, 0x0D, 0x93, 0xF6, 0x08, 0xEF, +0x2F, 0x93, 0xF6, 0x7F, 0x00, 0x22, 0xEF, 0xD3, +0x94, 0x02, 0x40, 0x03, 0x7F, 0xFF, 0x22, 0xEF, +0x23, 0x24, 0x81, 0xF8, 0xE6, 0x30, 0xE5, 0xF4, +0xC2, 0xAF, 0xE6, 0x54, 0x8C, 0xF6, 0xD2, 0xAF, +0xE5, 0x0C, 0xB5, 0x07, 0x0A, 0x74, 0x86, 0x2F, +0xF8, 0xE6, 0xF5, 0x81, 0x02, 0x84, 0x4D, 0x50, +0x2E, 0x74, 0x87, 0x2F, 0xF8, 0xE6, 0xBF, 0x02, +0x02, 0x74, 0xFF, 0xFD, 0x18, 0xE6, 0xF9, 0x74, +0x86, 0x2F, 0xF8, 0xFB, 0xE6, 0xFC, 0xE9, 0x6C, +0x60, 0x08, 0xA8, 0x05, 0xE7, 0xF6, 0x1D, 0x19, +0x80, 0xF4, 0xA8, 0x03, 0xA6, 0x05, 0x1F, 0xE5, +0x0C, 0xB5, 0x07, 0xE3, 0x7F, 0x00, 0x22, 0x74, +0x87, 0x2F, 0xF8, 0xE6, 0xFD, 0x18, 0x86, 0x01, +0x0F, 0x74, 0x86, 0x2F, 0xF8, 0xA6, 0x01, 0x08, +0x86, 0x04, 0xE5, 0x0C, 0xB5, 0x07, 0x02, 0xAC, +0x81, 0xED, 0x6C, 0x60, 0x08, 0x0D, 0x09, 0xA8, +0x05, 0xE6, 0xF7, 0x80, 0xF4, 0xE5, 0x0C, 0xB5, +0x07, 0xDE, 0x89, 0x81, 0x7F, 0x00, 0x22, 0xEF, +0xD3, 0x94, 0x02, 0x40, 0x03, 0x7F, 0xFF, 0x22, +0xEF, 0x23, 0x24, 0x81, 0xF8, 0xC2, 0xAF, 0xE6, +0x30, 0xE5, 0x05, 0x30, 0xE0, 0x02, 0xD2, 0xE4, +0xD2, 0xE2, 0xC6, 0xD2, 0xAF, 0x7F, 0x00, 0x30, +0xE2, 0x01, 0x0F, 0x02, 0x84, 0x4C, 0x8F, 0xF0, +0xE4, 0xFF, 0xFE, 0xE5, 0x0C, 0x23, 0x24, 0x80, +0xF8, 0xC2, 0xA9, 0x30, 0xF7, 0x0D, 0x7F, 0x08, +0xE6, 0x60, 0x0B, 0x2D, 0xF6, 0x60, 0x30, 0x50, +0x2E, 0x80, 0x07, 0x30, 0xF1, 0x06, 0xED, 0xF6, +0x60, 0x25, 0x7E, 0x02, 0x08, 0x30, 0xF0, 0x10, +0xC2, 0xAF, 0xE6, 0x10, 0xE7, 0x23, 0x0E, 0x30, +0xE2, 0x0C, 0xD2, 0xAF, 0x7F, 0x04, 0x80, 0x12, +0xC2, 0xAF, 0xE6, 0x10, 0xE7, 0x13, 0x54, 0xEC, +0x4E, 0xF6, 0xD2, 0xAF, 0x02, 0x84, 0x4D, 0x7F, +0x08, 0x08, 0xEF, 0x44, 0x83, 0xF4, 0xC2, 0xAF, +0x56, 0xC6, 0xD2, 0xAF, 0x54, 0x80, 0x4F, 0xFF, +0x22, 0xEF, 0x2B, 0xFF, 0xEE, 0x3A, 0xFE, 0xED, +0x39, 0xFD, 0xEC, 0x38, 0xFC, 0x22, 0xC3, 0xEF, +0x9B, 0xFF, 0xEE, 0x9A, 0xFE, 0xED, 0x99, 0xFD, +0xEC, 0x98, 0xFC, 0x22, 0xE8, 0x8F, 0xF0, 0xA4, +0xCC, 0x8B, 0xF0, 0xA4, 0x2C, 0xFC, 0xE9, 0x8E, +0xF0, 0xA4, 0x2C, 0xFC, 0x8A, 0xF0, 0xED, 0xA4, +0x2C, 0xFC, 0xEA, 0x8E, 0xF0, 0xA4, 0xCD, 0xA8, +0xF0, 0x8B, 0xF0, 0xA4, 0x2D, 0xCC, 0x38, 0x25, +0xF0, 0xFD, 0xE9, 0x8F, 0xF0, 0xA4, 0x2C, 0xCD, +0x35, 0xF0, 0xFC, 0xEB, 0x8E, 0xF0, 0xA4, 0xFE, +0xA9, 0xF0, 0xEB, 0x8F, 0xF0, 0xA4, 0xCF, 0xC5, +0xF0, 0x2E, 0xCD, 0x39, 0xFE, 0xE4, 0x3C, 0xFC, +0xEA, 0xA4, 0x2D, 0xCE, 0x35, 0xF0, 0xFD, 0xE4, +0x3C, 0xFC, 0x22, 0xEF, 0x5B, 0xFF, 0xEE, 0x5A, +0xFE, 0xED, 0x59, 0xFD, 0xEC, 0x58, 0xFC, 0x22, +0xEF, 0x4B, 0xFF, 0xEE, 0x4A, 0xFE, 0xED, 0x49, +0xFD, 0xEC, 0x48, 0xFC, 0x22, 0xE0, 0xFC, 0xA3, +0xE0, 0xFD, 0xA3, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, +0x22, 0xE0, 0xF8, 0xA3, 0xE0, 0xF9, 0xA3, 0xE0, +0xFA, 0xA3, 0xE0, 0xFB, 0x22, 0xE0, 0xFB, 0xA3, +0xE0, 0xFA, 0xA3, 0xE0, 0xF9, 0x22, 0xEB, 0xF0, +0xA3, 0xEA, 0xF0, 0xA3, 0xE9, 0xF0, 0x22, 0xD0, +0x83, 0xD0, 0x82, 0xF8, 0xE4, 0x93, 0x70, 0x12, +0x74, 0x01, 0x93, 0x70, 0x0D, 0xA3, 0xA3, 0x93, +0xF8, 0x74, 0x01, 0x93, 0xF5, 0x82, 0x88, 0x83, +0xE4, 0x73, 0x74, 0x02, 0x93, 0x68, 0x60, 0xEF, +0xA3, 0xA3, 0xA3, 0x80, 0xDF, 0x02, 0x87, 0xBB, +0x02, 0x84, 0xDD, 0xE4, 0x93, 0xA3, 0xF8, 0xE4, +0x93, 0xA3, 0x40, 0x03, 0xF6, 0x80, 0x01, 0xF2, +0x08, 0xDF, 0xF4, 0x80, 0x29, 0xE4, 0x93, 0xA3, +0xF8, 0x54, 0x07, 0x24, 0x0C, 0xC8, 0xC3, 0x33, +0xC4, 0x54, 0x0F, 0x44, 0x20, 0xC8, 0x83, 0x40, +0x04, 0xF4, 0x56, 0x80, 0x01, 0x46, 0xF6, 0xDF, +0xE4, 0x80, 0x0B, 0x01, 0x02, 0x04, 0x08, 0x10, +0x20, 0x40, 0x80, 0x90, 0x88, 0x00, 0xE4, 0x7E, +0x01, 0x93, 0x60, 0xBC, 0xA3, 0xFF, 0x54, 0x3F, +0x30, 0xE5, 0x09, 0x54, 0x1F, 0xFE, 0xE4, 0x93, +0xA3, 0x60, 0x01, 0x0E, 0xCF, 0x54, 0xC0, 0x25, +0xE0, 0x60, 0xA8, 0x40, 0xB8, 0xE4, 0x93, 0xA3, +0xFA, 0xE4, 0x93, 0xA3, 0xF8, 0xE4, 0x93, 0xA3, +0xC8, 0xC5, 0x82, 0xC8, 0xCA, 0xC5, 0x83, 0xCA, +0xF0, 0xA3, 0xC8, 0xC5, 0x82, 0xC8, 0xCA, 0xC5, +0x83, 0xCA, 0xDF, 0xE9, 0xDE, 0xE7, 0x80, 0xBE, +0x41, 0x95, 0x11, 0x00, 0x41, 0x95, 0x12, 0x00, +0x41, 0x95, 0x19, 0x00, 0x00, 0xBB, 0x20, 0xC0, +0x66, 0xC8, 0x01, 0x12, 0x5E, 0x10, 0x7F, 0x04, +0x90, 0x95, 0x17, 0xEF, 0xF0, 0x7F, 0x02, 0x12, +0x86, 0x27, 0x90, 0x84, 0xC1, 0xE0, 0xFF, 0x90, +0x95, 0x17, 0xE0, 0xFE, 0xEF, 0x4E, 0x90, 0x84, +0xC1, 0xF0, 0x22, 0x90, 0x93, 0xFB, 0xEF, 0xF0, +0x51, 0x7E, 0x7F, 0xF4, 0x7E, 0x00, 0x12, 0x64, +0x37, 0xBF, 0x01, 0x08, 0x90, 0x94, 0x1A, 0xE0, +0x90, 0x94, 0x1C, 0xF0, 0x51, 0x7E, 0x7F, 0xF5, +0x7E, 0x00, 0x12, 0x64, 0x37, 0xBF, 0x01, 0x08, +0x90, 0x94, 0x1A, 0xE0, 0x90, 0x94, 0x1D, 0xF0, +0x51, 0x7E, 0x7F, 0xF6, 0x7E, 0x00, 0x12, 0x64, +0x37, 0xBF, 0x01, 0x08, 0x90, 0x94, 0x1A, 0xE0, +0x90, 0x94, 0x1E, 0xF0, 0x51, 0x7E, 0x7F, 0xF7, +0x7E, 0x00, 0x12, 0x64, 0x37, 0xBF, 0x01, 0x08, +0x90, 0x94, 0x1A, 0xE0, 0x90, 0x94, 0x1F, 0xF0, +0x51, 0x7E, 0x7F, 0xF8, 0x7E, 0x00, 0x12, 0x64, +0x37, 0xBF, 0x01, 0x08, 0x90, 0x94, 0x1A, 0xE0, +0x90, 0x94, 0x20, 0xF0, 0x51, 0x7E, 0x12, 0xBF, +0x6C, 0xBF, 0x01, 0x08, 0x90, 0x94, 0x1A, 0xE0, +0x90, 0x94, 0x21, 0xF0, 0x51, 0x7E, 0x51, 0x85, +0x70, 0x52, 0x90, 0x94, 0x1A, 0xE0, 0x90, 0x94, +0x22, 0xF0, 0x54, 0x07, 0x60, 0x08, 0x90, 0x94, +0x1A, 0xE0, 0x54, 0xE0, 0x70, 0x3E, 0x7B, 0x01, +0x7A, 0x94, 0x79, 0x1B, 0x7F, 0xFA, 0x51, 0x87, +0x70, 0x32, 0x90, 0x94, 0x1A, 0xE0, 0xFC, 0x54, +0x07, 0x70, 0x12, 0x90, 0x94, 0x22, 0xE0, 0xFE, +0x90, 0x94, 0x1B, 0xE0, 0x54, 0x07, 0xFD, 0xEE, +0x4D, 0x90, 0x94, 0x22, 0xF0, 0xEC, 0x54, 0xE0, +0x70, 0x12, 0x90, 0x94, 0x22, 0xE0, 0xFF, 0x90, +0x94, 0x1B, 0xE0, 0x54, 0xE0, 0xFE, 0xEF, 0x4E, +0x90, 0x94, 0x22, 0xF0, 0x51, 0x7E, 0x7F, 0xFD, +0x51, 0x87, 0x70, 0x47, 0x90, 0x94, 0x1A, 0xE0, +0xFE, 0x54, 0xCC, 0x90, 0x94, 0x23, 0xF0, 0xEE, +0x54, 0x0C, 0xFF, 0x60, 0x08, 0x90, 0x94, 0x1A, +0xE0, 0x54, 0xC0, 0x70, 0x2E, 0xEF, 0x70, 0x12, +0x90, 0x94, 0x23, 0xE0, 0xFF, 0x90, 0x94, 0x1A, +0xE0, 0x54, 0x03, 0x12, 0xD1, 0xCA, 0x90, 0x94, +0x23, 0xF0, 0x90, 0x94, 0x1A, 0xE0, 0xFF, 0x54, +0xC0, 0x70, 0x10, 0x90, 0x94, 0x23, 0xE0, 0xFE, +0xEF, 0x54, 0x30, 0x25, 0xE0, 0x25, 0xE0, 0xFF, +0xEE, 0x4F, 0xF0, 0x51, 0x7E, 0x7F, 0xF0, 0x7E, +0x00, 0x12, 0x64, 0x37, 0xBF, 0x01, 0x08, 0x90, +0x94, 0x1A, 0xE0, 0x90, 0x94, 0x24, 0xF0, 0x51, +0x7E, 0x7F, 0xF1, 0x7E, 0x00, 0x12, 0x64, 0x37, +0xBF, 0x01, 0x08, 0x90, 0x94, 0x1A, 0xE0, 0x90, +0x94, 0x25, 0xF0, 0x51, 0x7E, 0x7F, 0xF2, 0x7E, +0x00, 0x12, 0x64, 0x37, 0xBF, 0x01, 0x08, 0x90, +0x94, 0x1A, 0xE0, 0x90, 0x94, 0x26, 0xF0, 0x51, +0x7E, 0x7F, 0xF3, 0x7E, 0x00, 0x12, 0x64, 0x37, +0xBF, 0x01, 0x08, 0x90, 0x94, 0x1A, 0xE0, 0x90, +0x94, 0x27, 0xF0, 0x51, 0x7E, 0x7F, 0xFC, 0x7E, +0x00, 0x12, 0x64, 0x37, 0xBF, 0x01, 0x08, 0x90, +0x94, 0x1A, 0xE0, 0x90, 0x94, 0x28, 0xF0, 0x90, +0x93, 0xFC, 0x74, 0x19, 0xF0, 0x90, 0x94, 0x0A, +0x74, 0x08, 0xF0, 0x90, 0x94, 0x1C, 0xE0, 0x90, +0x93, 0xFE, 0xF0, 0x90, 0x94, 0x1D, 0xE0, 0x90, +0x93, 0xFF, 0xF0, 0x90, 0x94, 0x1E, 0xE0, 0x90, +0x94, 0x00, 0xF0, 0x90, 0x94, 0x1F, 0xE0, 0x90, +0x94, 0x01, 0xF0, 0x90, 0x94, 0x20, 0xE0, 0x90, +0x94, 0x02, 0xF0, 0x90, 0x94, 0x21, 0xE0, 0x90, +0x94, 0x03, 0xF0, 0x90, 0x94, 0x22, 0xE0, 0x90, +0x94, 0x04, 0xF0, 0x90, 0x94, 0x23, 0xE0, 0x90, +0x94, 0x05, 0xF0, 0x90, 0x94, 0x0B, 0x74, 0x1A, +0xF0, 0x90, 0x94, 0x19, 0x74, 0x05, 0xF0, 0x90, +0x94, 0x24, 0xE0, 0x90, 0x94, 0x0D, 0xF0, 0x90, +0x94, 0x25, 0xE0, 0x90, 0x94, 0x0E, 0xF0, 0x90, +0x94, 0x26, 0xE0, 0x90, 0x94, 0x0F, 0xF0, 0x90, +0x94, 0x27, 0xE0, 0x90, 0x94, 0x10, 0xF0, 0x90, +0x94, 0x28, 0xE0, 0x90, 0x94, 0x11, 0xF0, 0x90, +0x93, 0xFB, 0xE0, 0xB4, 0x01, 0x16, 0x7B, 0x01, +0x7A, 0x93, 0x79, 0xFC, 0x12, 0x5E, 0x10, 0x7B, +0x01, 0x7A, 0x94, 0x79, 0x0B, 0x12, 0x5E, 0x10, +0x7F, 0x04, 0x01, 0x18, 0x75, 0x1B, 0x01, 0x75, +0x1C, 0x93, 0x75, 0x1D, 0xFC, 0x75, 0x1E, 0x0A, +0x7B, 0x01, 0x7A, 0x01, 0x79, 0xA0, 0x12, 0x6A, +0x21, 0x75, 0x1B, 0x01, 0x75, 0x1C, 0x94, 0x75, +0x1D, 0x0D, 0x75, 0x1E, 0x05, 0x7B, 0x01, 0x7A, +0x01, 0x79, 0xAA, 0x02, 0x6A, 0x21, 0x7B, 0x01, +0x7A, 0x94, 0x79, 0x1A, 0x22, 0x7F, 0xFB, 0x7E, +0x00, 0x12, 0x64, 0x37, 0xEF, 0x64, 0x01, 0x22, +0x12, 0xA0, 0x37, 0x12, 0x02, 0xF6, 0xFF, 0xF1, +0x73, 0xFE, 0x54, 0x03, 0xFD, 0xEE, 0x13, 0x13, +0x54, 0x07, 0xFB, 0xC0, 0x03, 0xF1, 0x58, 0xF1, +0xF3, 0x12, 0xD0, 0x6A, 0xD0, 0x03, 0x12, 0xA9, +0x59, 0xF1, 0x58, 0xF1, 0x73, 0x71, 0xBE, 0x90, +0x93, 0xC6, 0x74, 0x10, 0xF0, 0x90, 0x93, 0xD4, +0x74, 0x07, 0xF0, 0xF1, 0x58, 0x12, 0x02, 0xF6, +0x90, 0x93, 0xC8, 0xF0, 0x7B, 0x01, 0x7A, 0x93, +0x79, 0xC6, 0x12, 0x5E, 0x10, 0x7F, 0x04, 0x01, +0x18, 0x90, 0x93, 0xC0, 0x12, 0x87, 0x4E, 0x90, +0x93, 0xBF, 0xEF, 0xF0, 0x12, 0x87, 0x57, 0x8B, +0x33, 0x00, 0x8B, 0x37, 0x01, 0x8B, 0x3C, 0x06, +0x8B, 0x4D, 0x10, 0x8B, 0x52, 0x11, 0x8B, 0x57, +0x12, 0x8B, 0x5C, 0x14, 0x8B, 0xA9, 0x15, 0x8B, +0x61, 0x16, 0x8B, 0x65, 0x18, 0x8B, 0x6A, 0x19, +0x8B, 0x6F, 0x1C, 0x8B, 0x73, 0x20, 0x8B, 0x78, +0x24, 0x8B, 0x7D, 0x25, 0x8B, 0x82, 0x27, 0x8B, +0x87, 0x40, 0x8B, 0x8C, 0x42, 0x8B, 0xA9, 0x47, +0x8B, 0x91, 0x49, 0x8B, 0x96, 0xC3, 0x8B, 0x41, +0xC6, 0x8B, 0x41, 0xC7, 0x8B, 0x41, 0xC8, 0x00, +0x00, 0x8B, 0x9A, 0x71, 0xAA, 0xE1, 0xF9, 0x71, +0xAA, 0x02, 0x98, 0x09, 0x71, 0xAA, 0x02, 0xB9, +0x3F, 0x90, 0x93, 0xBF, 0xE0, 0xFF, 0xA3, 0x12, +0x87, 0x45, 0x02, 0xB9, 0xDA, 0x71, 0xAA, 0x02, +0x9F, 0xFF, 0x71, 0xAA, 0x02, 0x91, 0x0F, 0x71, +0xAA, 0x02, 0xB0, 0x32, 0x71, 0xAA, 0x02, 0xB1, +0x0C, 0x71, 0xAA, 0xE1, 0xCA, 0x71, 0xAA, 0x02, +0xA8, 0x01, 0x71, 0xAA, 0x02, 0xAF, 0xED, 0x71, +0xAA, 0x41, 0x90, 0x71, 0xAA, 0x02, 0x90, 0x3F, +0x71, 0xAA, 0x02, 0xA4, 0xB6, 0x71, 0xAA, 0x02, +0xB1, 0x1B, 0x71, 0xAA, 0x02, 0xB1, 0x23, 0x71, +0xAA, 0x02, 0xA0, 0x3D, 0x71, 0xAA, 0x02, 0x4E, +0x29, 0x71, 0xAA, 0x02, 0xCA, 0xE1, 0x71, 0xAA, +0xE1, 0xB5, 0x90, 0x01, 0xC0, 0xE0, 0x44, 0x01, +0xF0, 0x90, 0x93, 0xBF, 0xE0, 0x90, 0x01, 0xC2, +0xF0, 0x22, 0x90, 0x93, 0xC0, 0x02, 0x87, 0x45, +0x75, 0xF0, 0x1B, 0xA4, 0x24, 0x38, 0xF5, 0x82, +0xE4, 0x34, 0x92, 0xF5, 0x83, 0xE0, 0xFE, 0x54, +0x03, 0xFF, 0xEE, 0x13, 0x13, 0x54, 0x07, 0xFD, +0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, +0x95, 0x15, 0xED, 0xF0, 0xE4, 0xA3, 0xF0, 0xEF, +0x14, 0x60, 0x02, 0x81, 0xAF, 0x90, 0x06, 0x03, +0xE0, 0x54, 0xFB, 0xF0, 0x90, 0x95, 0x15, 0xE0, +0xFB, 0xC4, 0x33, 0x54, 0xE0, 0xFE, 0x90, 0x04, +0x42, 0xE0, 0x54, 0x9F, 0x4E, 0xFE, 0xF0, 0xE4, +0xFD, 0x12, 0xCD, 0x05, 0x90, 0x95, 0x16, 0xEF, +0xF0, 0x90, 0x04, 0x83, 0xF0, 0x90, 0x94, 0xD3, +0x12, 0x04, 0xF7, 0x00, 0x00, 0x00, 0x01, 0x90, +0x94, 0xD7, 0x12, 0x04, 0xF7, 0x00, 0x00, 0x00, +0x01, 0xB1, 0x82, 0x12, 0x04, 0xF7, 0x00, 0x00, +0x00, 0x01, 0x90, 0x94, 0xD7, 0x12, 0x04, 0xF7, +0x00, 0x00, 0x00, 0x01, 0x7F, 0x00, 0x7E, 0x09, +0xB1, 0x86, 0x12, 0x04, 0xF7, 0x00, 0x00, 0x00, +0x10, 0x90, 0x95, 0x15, 0xB1, 0xA5, 0xEF, 0x54, +0x03, 0xFF, 0xE4, 0x78, 0x01, 0x12, 0x04, 0xC5, +0x78, 0x04, 0xF1, 0x64, 0x7F, 0x00, 0x7E, 0x0A, +0xB1, 0x86, 0x12, 0x04, 0xF7, 0x00, 0x00, 0x0C, +0x00, 0x90, 0x95, 0x15, 0xB1, 0xA5, 0xEF, 0x54, +0x03, 0xFF, 0xE4, 0x78, 0x0A, 0xF1, 0x64, 0x7F, +0x00, 0x7E, 0x0D, 0xB1, 0x86, 0x12, 0x04, 0xF7, +0x0C, 0x00, 0x00, 0x00, 0x90, 0x95, 0x16, 0xB1, +0xA5, 0xEF, 0x54, 0x03, 0xFF, 0xE4, 0x78, 0x1A, +0xF1, 0x64, 0x7F, 0x18, 0xB1, 0x84, 0x12, 0x04, +0xF7, 0x00, 0x00, 0x0C, 0x00, 0x90, 0x94, 0xD7, +0x12, 0x04, 0xF7, 0x00, 0x00, 0x00, 0x00, 0xB1, +0x18, 0x90, 0x94, 0xC1, 0x12, 0x04, 0xF7, 0x00, +0x00, 0x0C, 0x00, 0x90, 0x94, 0xC5, 0x12, 0x04, +0xF7, 0x00, 0x00, 0x04, 0x00, 0x80, 0x5B, 0x90, +0x06, 0x03, 0xE0, 0x44, 0x04, 0xF0, 0x90, 0x94, +0xD3, 0x12, 0x04, 0xF7, 0x00, 0x00, 0x00, 0x01, +0x90, 0x94, 0xD7, 0x12, 0x04, 0xF7, 0x00, 0x00, +0x00, 0x00, 0xB1, 0x82, 0x12, 0x04, 0xF7, 0x00, +0x00, 0x00, 0x01, 0x90, 0x94, 0xD7, 0x12, 0x04, +0xF7, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x00, 0x7E, +0x09, 0xB1, 0x86, 0x12, 0x04, 0xF7, 0x00, 0x00, +0x0C, 0x00, 0x90, 0x94, 0xD7, 0x12, 0x04, 0xF7, +0x00, 0x00, 0x0C, 0x00, 0xB1, 0x18, 0x90, 0x94, +0xC1, 0x12, 0x04, 0xF7, 0x00, 0x00, 0x0C, 0x00, +0x90, 0x94, 0xC5, 0x12, 0x04, 0xF7, 0x00, 0x00, +0x0C, 0x00, 0x7D, 0x18, 0x7C, 0x00, 0xE4, 0xFF, +0x12, 0xA9, 0xD2, 0xD0, 0xD0, 0x92, 0xAF, 0x22, +0x7F, 0x84, 0x7E, 0x08, 0xD3, 0x10, 0xAF, 0x01, +0xC3, 0xC0, 0xD0, 0x90, 0x94, 0xD1, 0xEE, 0xF0, +0xA3, 0xEF, 0xF0, 0x12, 0x70, 0x61, 0x90, 0x94, +0xDB, 0x12, 0x04, 0xEB, 0x90, 0x94, 0xD3, 0x12, +0x87, 0x2D, 0x12, 0x04, 0xA7, 0x90, 0x94, 0xDB, +0xF1, 0x5E, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, +0xC0, 0x07, 0x90, 0x94, 0xD3, 0x12, 0x87, 0x2D, +0x90, 0x94, 0xD7, 0xF1, 0x5E, 0xD0, 0x03, 0xD0, +0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x87, 0x20, +0x90, 0x94, 0xDF, 0x12, 0x04, 0xEB, 0x90, 0x94, +0xDF, 0x12, 0x87, 0x2D, 0x90, 0x91, 0x66, 0x12, +0x04, 0xEB, 0x90, 0x94, 0xD1, 0xE0, 0xFE, 0xA3, +0xE0, 0xFF, 0x12, 0x71, 0x18, 0xD0, 0xD0, 0x92, +0xAF, 0x22, 0x7F, 0x00, 0x7E, 0x08, 0xB1, 0x1C, +0x90, 0x94, 0xD3, 0x22, 0x90, 0x05, 0x61, 0xE0, +0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0x78, 0x08, 0x12, +0x04, 0xD8, 0xA8, 0x04, 0xA9, 0x05, 0xAA, 0x06, +0xAB, 0x07, 0x90, 0x05, 0x60, 0xE0, 0xFF, 0xE4, +0xFC, 0xFD, 0xFE, 0x22, 0x90, 0x92, 0x0A, 0xE0, +0x20, 0xE0, 0x02, 0xE1, 0x49, 0x90, 0x92, 0xB6, +0xE0, 0x04, 0xF0, 0x12, 0x94, 0x0E, 0x04, 0xFF, +0x90, 0x94, 0x6F, 0xF0, 0x90, 0x92, 0x0B, 0xE0, +0xB5, 0x07, 0x05, 0xE4, 0x90, 0x94, 0x6F, 0xF0, +0x90, 0x92, 0xB4, 0xE0, 0xFF, 0x60, 0x17, 0x90, +0x94, 0x6F, 0xF1, 0x7C, 0xE0, 0xC3, 0x9F, 0x90, +0x91, 0x6F, 0x12, 0xAF, 0x91, 0xFB, 0xFD, 0x7F, +0x50, 0x7E, 0x01, 0x12, 0x61, 0x41, 0x90, 0x94, +0x6F, 0xE0, 0xFF, 0xF1, 0xA6, 0x54, 0x07, 0xFE, +0x64, 0x02, 0x60, 0x03, 0xEE, 0x70, 0x11, 0xEF, +0xF1, 0x7D, 0xE0, 0x24, 0xFC, 0xFF, 0xE4, 0x90, +0x91, 0x6E, 0xF0, 0xA3, 0xEF, 0x12, 0xC6, 0x20, +0x90, 0x92, 0x0A, 0xE0, 0xF1, 0xA2, 0x54, 0x07, +0xFF, 0x14, 0x60, 0x0F, 0x14, 0x60, 0x07, 0x14, +0x60, 0x09, 0x24, 0x03, 0x70, 0x0B, 0x12, 0xCC, +0x5E, 0x80, 0x03, 0x12, 0x97, 0xEE, 0x12, 0x94, +0x17, 0x90, 0x92, 0xB3, 0xE0, 0xFF, 0x90, 0x92, +0xB6, 0xE0, 0xD3, 0x9F, 0x40, 0x02, 0xE1, 0x49, +0xB1, 0x8C, 0x12, 0x87, 0x20, 0xC0, 0x04, 0xC0, +0x05, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x05, 0x62, +0xB1, 0xA5, 0x78, 0x10, 0x12, 0x04, 0xD8, 0xD0, +0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, +0x87, 0x20, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, +0xC0, 0x07, 0xA3, 0xB1, 0xA5, 0x78, 0x18, 0x12, +0x04, 0xD8, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, +0xD0, 0x00, 0x12, 0x87, 0x20, 0x90, 0x94, 0x70, +0x12, 0x04, 0xEB, 0x90, 0x05, 0x65, 0xB1, 0xA5, +0x12, 0xAE, 0x80, 0x90, 0x05, 0x64, 0xB1, 0xA5, +0x12, 0x87, 0x20, 0xC0, 0x04, 0xC0, 0x05, 0xC0, +0x06, 0xC0, 0x07, 0x90, 0x05, 0x66, 0xB1, 0xA5, +0x78, 0x10, 0x12, 0x04, 0xD8, 0xD0, 0x03, 0xD0, +0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x87, 0x20, +0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, +0xA3, 0xB1, 0xA5, 0x78, 0x18, 0x12, 0x04, 0xD8, +0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, +0x12, 0x87, 0x20, 0x90, 0x94, 0x74, 0x12, 0x04, +0xEB, 0x90, 0x94, 0x6F, 0xF1, 0x7C, 0xB1, 0xA5, +0x12, 0xAF, 0xA6, 0x90, 0x94, 0x70, 0x12, 0x87, +0x39, 0x12, 0x86, 0xA9, 0x90, 0x94, 0x78, 0x12, +0x04, 0xEB, 0x90, 0x94, 0x70, 0x12, 0x87, 0x2D, +0x90, 0x94, 0x78, 0x12, 0xAF, 0x9F, 0x50, 0x11, +0xF1, 0x4C, 0x12, 0xB9, 0x37, 0xE4, 0x3D, 0xFD, +0xE4, 0x3C, 0xFC, 0x90, 0x94, 0x74, 0x12, 0x04, +0xEB, 0xF1, 0x4C, 0x12, 0xAF, 0xB7, 0xF1, 0x4A, +0x12, 0xAF, 0xC0, 0xF1, 0x4A, 0x12, 0xAF, 0xC9, +0xF1, 0x4A, 0x90, 0x05, 0x88, 0xEF, 0xF0, 0x90, +0x94, 0x78, 0x12, 0x87, 0x2D, 0x12, 0xAF, 0xD2, +0xEF, 0xF0, 0x90, 0x94, 0x78, 0x12, 0x87, 0x2D, +0x12, 0xAF, 0xDB, 0xEF, 0xF0, 0x90, 0x94, 0x78, +0x12, 0x87, 0x2D, 0x12, 0xAF, 0xE4, 0xEF, 0xF0, +0x90, 0x94, 0x78, 0x12, 0x87, 0x2D, 0x12, 0xD1, +0x1F, 0x22, 0xEF, 0xF0, 0x90, 0x94, 0x74, 0x02, +0x87, 0x2D, 0x24, 0x03, 0xFF, 0xE4, 0x33, 0xFE, +0x90, 0x93, 0xC3, 0x02, 0x87, 0x45, 0x12, 0x87, +0x39, 0x02, 0x87, 0x13, 0x12, 0x04, 0xD8, 0x90, +0x94, 0xD7, 0x02, 0x04, 0xEB, 0xAB, 0x5B, 0xAA, +0x5C, 0xA9, 0x5D, 0x90, 0x00, 0x01, 0x02, 0x03, +0x0F, 0x90, 0x94, 0x7E, 0xE0, 0x75, 0xF0, 0x1B, +0xA4, 0x24, 0x39, 0xF5, 0x82, 0xE4, 0x34, 0x92, +0xF5, 0x83, 0x22, 0xF1, 0x8F, 0xA1, 0xAC, 0x90, +0x92, 0x09, 0xE0, 0x30, 0xE0, 0x0B, 0x12, 0xAF, +0x8A, 0xE4, 0x90, 0x92, 0x0C, 0xF0, 0x12, 0xC5, +0xF1, 0x22, 0xC3, 0x13, 0x54, 0x07, 0x75, 0xF0, +0x1B, 0xA4, 0x24, 0x3A, 0xF5, 0x82, 0xE4, 0x34, +0x92, 0xF5, 0x83, 0xE0, 0x22, 0x12, 0x02, 0xF6, +0xFF, 0x90, 0x92, 0xBC, 0xF0, 0xBF, 0x01, 0x09, +0x7F, 0x01, 0x11, 0x33, 0xE4, 0x90, 0x92, 0xBC, +0xF0, 0x22, 0x12, 0xAF, 0xAE, 0x90, 0x92, 0x3C, +0xF0, 0xF1, 0x73, 0x90, 0x92, 0x3D, 0xF1, 0xF2, +0x90, 0x92, 0x57, 0xF0, 0x12, 0x91, 0x09, 0x90, +0x92, 0x58, 0xF0, 0x12, 0x97, 0xE7, 0x90, 0x92, +0x72, 0x12, 0x97, 0xF5, 0x90, 0x92, 0x73, 0xF0, +0x22, 0x4F, 0xF0, 0x90, 0x00, 0x02, 0x02, 0x03, +0x0F, 0x90, 0x02, 0x09, 0xE0, 0xF5, 0x5B, 0x12, +0x02, 0xF6, 0x25, 0x5B, 0x90, 0x84, 0xC6, 0xF0, +0x12, 0x8F, 0x73, 0x25, 0x5B, 0x90, 0x84, 0xC7, +0x12, 0x8F, 0xF2, 0x25, 0x5B, 0x90, 0x84, 0xC8, +0xF0, 0x31, 0x09, 0x25, 0x5B, 0x90, 0x84, 0xC9, +0xF0, 0xF1, 0xE7, 0x25, 0x5B, 0x90, 0x84, 0xCA, +0xF1, 0xF5, 0x25, 0x5B, 0x90, 0x84, 0xCB, 0xF0, +0x11, 0x39, 0x25, 0x5B, 0x90, 0x84, 0xCC, 0xF0, +0x22, 0x90, 0x00, 0x06, 0x02, 0x03, 0x0F, 0x12, +0xA0, 0x37, 0x12, 0x02, 0xF6, 0xFF, 0x54, 0x7F, +0x90, 0x85, 0xC5, 0xF0, 0xEF, 0x12, 0xA3, 0x01, +0xA3, 0xF0, 0x12, 0x8F, 0x73, 0xFD, 0x54, 0xF0, +0xC4, 0x54, 0x0F, 0xFF, 0x90, 0x85, 0xC3, 0xE0, +0x54, 0xF0, 0x4F, 0xF0, 0x31, 0x09, 0xFC, 0x54, +0x01, 0x25, 0xE0, 0xFF, 0x90, 0x85, 0xC1, 0xE0, +0x54, 0xFD, 0x4F, 0xF0, 0xEC, 0x54, 0x04, 0xFF, +0x90, 0x92, 0xC9, 0xE0, 0x54, 0xFB, 0x4F, 0xF0, +0xED, 0x54, 0x0F, 0xC4, 0x54, 0xF0, 0xFF, 0x12, +0xB7, 0xDC, 0x12, 0x8F, 0xF1, 0x90, 0x85, 0xC4, +0xF0, 0x11, 0x39, 0x30, 0xE0, 0x50, 0xC3, 0x13, +0x54, 0x07, 0xFF, 0xC3, 0x94, 0x04, 0x90, 0x85, +0xD8, 0x50, 0x04, 0xEF, 0xF0, 0x80, 0x27, 0x74, +0x03, 0xF0, 0x12, 0x8F, 0x58, 0xE9, 0x24, 0x06, +0x12, 0xA7, 0xEE, 0xFF, 0x74, 0x03, 0x24, 0xFD, +0xFE, 0xEF, 0xC4, 0x54, 0x0F, 0xFD, 0xEF, 0x54, +0x0F, 0xFF, 0xED, 0x2E, 0x54, 0x0F, 0xFE, 0xC4, +0x54, 0xF0, 0x4F, 0x12, 0x03, 0x3C, 0x12, 0x8F, +0x58, 0x11, 0x39, 0xC4, 0x54, 0x0F, 0xFF, 0xC3, +0x94, 0x04, 0x90, 0x85, 0xCD, 0x50, 0x05, 0x74, +0x04, 0xF0, 0x80, 0x02, 0xEF, 0xF0, 0x12, 0x8F, +0x58, 0xF1, 0xE7, 0xFD, 0x7F, 0x02, 0x12, 0x57, +0x82, 0x12, 0x8F, 0x58, 0x12, 0x71, 0xCB, 0x12, +0xC2, 0xD4, 0xF0, 0x90, 0x85, 0xC5, 0x12, 0xD1, +0x6E, 0x12, 0xB7, 0xDB, 0x90, 0x01, 0xBE, 0xF0, +0x22, 0x90, 0x00, 0x03, 0x02, 0x03, 0x0F, 0x12, +0xAF, 0xAE, 0xC4, 0x54, 0x0F, 0xFF, 0xBF, 0x0F, +0x15, 0x90, 0x92, 0x09, 0xE0, 0x54, 0xFE, 0xF0, +0x12, 0xAF, 0x8A, 0x12, 0x98, 0xD7, 0x54, 0x0F, +0xFF, 0x51, 0xC7, 0x02, 0xBC, 0x2F, 0x12, 0x8F, +0x6D, 0x12, 0xD1, 0xF1, 0xF1, 0xFC, 0xF5, 0x83, +0xEF, 0x12, 0x8F, 0xF2, 0x54, 0x03, 0xFF, 0x51, +0xB7, 0x54, 0xFC, 0x12, 0x8F, 0xF1, 0x54, 0x1C, +0xFF, 0xEE, 0x54, 0x0F, 0xFE, 0x51, 0xB8, 0x54, +0xE3, 0x12, 0x8F, 0xF1, 0x54, 0xE0, 0xFF, 0xEE, +0x51, 0xB8, 0x54, 0x1F, 0x4F, 0xF0, 0xF1, 0xE7, +0xFF, 0x12, 0x02, 0xF6, 0x54, 0x0F, 0xFD, 0xE4, +0xFB, 0x51, 0xAE, 0xF1, 0xF6, 0xFF, 0x12, 0x02, +0xF6, 0x54, 0x0F, 0xFD, 0x7B, 0x01, 0x51, 0xAE, +0x31, 0x09, 0x33, 0x33, 0x33, 0x54, 0xF8, 0x12, +0xD1, 0xF1, 0xFD, 0x75, 0xF0, 0x0E, 0xA4, 0x24, +0x16, 0xF5, 0x82, 0xE4, 0x34, 0x92, 0xF5, 0x83, +0xEF, 0xF0, 0x31, 0x09, 0xC4, 0x13, 0x54, 0x07, +0xFF, 0xED, 0x75, 0xF0, 0x0E, 0xA4, 0x24, 0x17, +0xF5, 0x82, 0xE4, 0x34, 0x92, 0xF5, 0x83, 0xEF, +0xF0, 0xEE, 0xC4, 0x54, 0x0F, 0xFF, 0x14, 0x6D, +0x70, 0x21, 0x90, 0x92, 0x0B, 0xEF, 0xF0, 0x11, +0x39, 0x54, 0x0F, 0xC4, 0x54, 0xF0, 0xFF, 0x90, +0x92, 0x0A, 0xE0, 0x54, 0x0F, 0x4F, 0xF0, 0x54, +0xF1, 0xF0, 0x90, 0x92, 0x09, 0xE0, 0x44, 0x01, +0x12, 0xD1, 0x23, 0x22, 0x8F, 0x5E, 0x8D, 0x5F, +0xAE, 0x03, 0x74, 0x1F, 0xC3, 0x95, 0x5E, 0x40, +0x0A, 0x51, 0xA6, 0xE4, 0xFD, 0x51, 0x9E, 0x24, +0xD4, 0x80, 0x31, 0x74, 0x3F, 0xC3, 0x95, 0x5E, +0x40, 0x0A, 0x51, 0xA6, 0x7D, 0x20, 0x51, 0x9C, +0x24, 0x88, 0x80, 0x20, 0x74, 0x5F, 0xC3, 0x95, +0x5E, 0x40, 0x0A, 0x51, 0xA6, 0x7D, 0x40, 0x51, +0x9C, 0x24, 0xD0, 0x80, 0x0F, 0x74, 0x7F, 0xC3, +0x95, 0x5E, 0x40, 0x20, 0x51, 0xA6, 0x7D, 0x60, +0x51, 0x9C, 0x24, 0x84, 0xFD, 0xE4, 0x34, 0x04, +0xFC, 0xE5, 0x5F, 0x12, 0xD1, 0x13, 0xF5, 0x83, +0x75, 0xF0, 0x03, 0xEE, 0x12, 0x05, 0x28, 0xEC, +0xF0, 0xA3, 0xED, 0xF0, 0x22, 0xC3, 0xEF, 0x9D, +0xF5, 0x60, 0xC3, 0x94, 0x08, 0x50, 0x1C, 0xE4, +0xF5, 0x61, 0x71, 0x9F, 0xC0, 0x83, 0xC0, 0x82, +0x90, 0x93, 0xC7, 0xE0, 0xD0, 0x82, 0xD0, 0x83, +0x75, 0xF0, 0x03, 0x12, 0x05, 0x28, 0xE5, 0x60, +0xF0, 0x80, 0x3E, 0xE5, 0x60, 0xC3, 0x94, 0x10, +0x50, 0x09, 0x75, 0x61, 0x01, 0xE5, 0x60, 0x24, +0xF8, 0x80, 0x17, 0xE5, 0x60, 0xC3, 0x94, 0x18, +0x50, 0x09, 0x75, 0x61, 0x02, 0xE5, 0x60, 0x24, +0xF0, 0x80, 0x07, 0x75, 0x61, 0x03, 0xE5, 0x60, +0x24, 0xE8, 0xFF, 0x71, 0x9F, 0xC0, 0x83, 0xC0, +0x82, 0x90, 0x93, 0xC7, 0xE0, 0xD0, 0x82, 0xD0, +0x83, 0x75, 0xF0, 0x03, 0x12, 0x05, 0x28, 0xEF, +0xF0, 0xAF, 0x61, 0x22, 0xAF, 0x5E, 0x51, 0x35, +0x90, 0x93, 0xC3, 0xEF, 0xF0, 0x22, 0x90, 0x93, +0xC7, 0xEE, 0xF0, 0xAB, 0x5F, 0x22, 0x31, 0xD4, +0xAB, 0x5B, 0xAA, 0x5C, 0xA9, 0x5D, 0x22, 0xED, +0x75, 0xF0, 0x0E, 0xA4, 0x24, 0x0E, 0xF5, 0x82, +0xE4, 0x34, 0x92, 0xF5, 0x83, 0xE0, 0x22, 0x8F, +0x5E, 0xD1, 0xE6, 0xE5, 0x5E, 0xF1, 0xFD, 0xF5, +0x83, 0xE0, 0xFC, 0xE5, 0x5E, 0x51, 0xB8, 0x12, +0xD0, 0x5A, 0xAF, 0x04, 0x12, 0xA9, 0x59, 0xE5, +0x5E, 0x51, 0xB8, 0x12, 0x8B, 0xBE, 0xE5, 0x5E, +0x12, 0xAA, 0xE3, 0xFD, 0xB1, 0x92, 0xB1, 0x82, +0xAD, 0x5E, 0x7F, 0x01, 0x80, 0x00, 0xD3, 0x10, +0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x94, 0xF9, +0xEF, 0xF0, 0xA3, 0xED, 0xF0, 0xE4, 0xA3, 0xF0, +0x90, 0x94, 0xFB, 0xE0, 0xFF, 0xC3, 0x94, 0x03, +0x40, 0x02, 0x61, 0x9A, 0x90, 0x94, 0xFA, 0xE0, +0xFE, 0x12, 0xD1, 0x13, 0xF5, 0x83, 0x75, 0xF0, +0x03, 0xEF, 0x12, 0xD1, 0x7B, 0xE0, 0x90, 0x94, +0xFC, 0xF0, 0x90, 0x94, 0xF9, 0xE0, 0xFC, 0xB4, +0x02, 0x20, 0x90, 0x94, 0xFC, 0xE0, 0xFD, 0xEE, +0x71, 0xA0, 0xC0, 0x83, 0xC0, 0x82, 0x90, 0x94, +0xFB, 0xE0, 0xD0, 0x82, 0xD0, 0x83, 0x12, 0xB2, +0x7B, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0x4D, +0x80, 0x20, 0xEC, 0xB4, 0x01, 0x20, 0x12, 0xD1, +0x9D, 0x71, 0xA0, 0xC0, 0x83, 0xC0, 0x82, 0x90, +0x94, 0xFB, 0xE0, 0xD0, 0x82, 0xD0, 0x83, 0x12, +0xB2, 0x7B, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, +0xF4, 0x5F, 0x90, 0x94, 0xFC, 0xF0, 0x12, 0xD1, +0x9D, 0x12, 0xD1, 0x13, 0xF5, 0x83, 0xC0, 0x83, +0xC0, 0x82, 0x90, 0x94, 0xFB, 0xE0, 0xD0, 0x82, +0xD0, 0x83, 0x75, 0xF0, 0x03, 0x12, 0xD1, 0x7B, +0xEF, 0xF0, 0x90, 0x94, 0xFB, 0xE0, 0x04, 0xF0, +0x61, 0x08, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xEB, +0x75, 0xF0, 0x0E, 0xA4, 0x24, 0x11, 0xF5, 0x82, +0xE4, 0x34, 0x92, 0xF5, 0x83, 0x22, 0x12, 0xD0, +0xA7, 0xB5, 0x07, 0x04, 0xEE, 0x54, 0xF1, 0xF0, +0x12, 0xC5, 0xF1, 0xE4, 0x90, 0x92, 0x0C, 0xF0, +0xD1, 0xEE, 0x12, 0xD0, 0xBE, 0xF1, 0xFC, 0xF5, +0x83, 0xE0, 0xFA, 0x51, 0xB7, 0xFC, 0x54, 0x03, +0xFD, 0xEC, 0x13, 0x13, 0x54, 0x07, 0xFB, 0xEE, +0x12, 0xD0, 0x69, 0xAF, 0x02, 0x12, 0xA9, 0x59, +0x91, 0x0E, 0x51, 0xB8, 0x12, 0x8B, 0xBE, 0x91, +0x0E, 0xFF, 0x75, 0xF0, 0x0E, 0xA4, 0x24, 0x18, +0xF5, 0x82, 0xE4, 0x34, 0x92, 0xF5, 0x83, 0xE0, +0x04, 0xF0, 0x12, 0xAA, 0xE2, 0xFD, 0xB1, 0x92, +0xE4, 0xFB, 0xFD, 0x91, 0x0A, 0xFD, 0x7F, 0x01, +0x41, 0xF6, 0x7F, 0xFF, 0xB1, 0x87, 0x90, 0x92, +0x0A, 0xE0, 0xC3, 0x13, 0x54, 0x07, 0x22, 0xE4, +0x90, 0x94, 0x7F, 0xF0, 0x90, 0x92, 0x0A, 0xE0, +0xFF, 0x20, 0xE0, 0x02, 0xA1, 0x81, 0x12, 0x8F, +0xA2, 0x54, 0x07, 0x90, 0x94, 0x7C, 0xF0, 0x60, +0x07, 0xE0, 0x64, 0x02, 0x60, 0x02, 0xA1, 0x25, +0x90, 0x92, 0x0C, 0xE0, 0x70, 0x2E, 0x12, 0xD1, +0xB0, 0x7B, 0x4E, 0x7D, 0x6F, 0x91, 0x0A, 0xF1, +0xD9, 0xE0, 0xFF, 0x7E, 0x00, 0x7B, 0x04, 0x7D, +0x01, 0xB1, 0x92, 0xBF, 0x01, 0x0D, 0xF1, 0x5A, +0xE0, 0x44, 0x01, 0xF0, 0x90, 0x92, 0x0C, 0x74, +0x01, 0xF0, 0x22, 0x90, 0x94, 0x7D, 0xE0, 0xFD, +0x7B, 0x4F, 0x81, 0xFD, 0x90, 0x92, 0x0C, 0xE0, +0x64, 0x01, 0x60, 0x02, 0xA1, 0x16, 0x91, 0x0E, +0xFF, 0x12, 0x8F, 0xA6, 0xFE, 0xC4, 0x54, 0x0F, +0x30, 0xE0, 0x02, 0xA1, 0x14, 0xEF, 0xF1, 0x62, +0xE0, 0xFF, 0x30, 0xE0, 0x08, 0x90, 0x94, 0x7F, +0x74, 0x01, 0xF0, 0x80, 0x17, 0xEF, 0xC3, 0x13, +0x20, 0xE0, 0x11, 0x90, 0x94, 0x7F, 0x74, 0x01, +0xF0, 0x12, 0xD1, 0xB0, 0x7B, 0x50, 0x7D, 0x6F, +0x7F, 0xFF, 0xB1, 0x87, 0x90, 0x94, 0x7F, 0xE0, +0x60, 0x64, 0x90, 0x92, 0xBB, 0xE0, 0xFF, 0x90, +0x92, 0xBA, 0xE0, 0x6F, 0x60, 0x43, 0xE0, 0x04, +0xF0, 0xE0, 0xD3, 0x94, 0x01, 0x40, 0x08, 0x90, +0x94, 0x80, 0x74, 0x04, 0xF0, 0x80, 0x05, 0xE4, +0x90, 0x94, 0x80, 0xF0, 0x91, 0x0E, 0xF1, 0xD9, +0xE0, 0xFF, 0x7E, 0x00, 0x90, 0x94, 0x80, 0xE0, +0xFB, 0x7D, 0x01, 0xB1, 0x92, 0xBF, 0x01, 0x0E, +0x12, 0xD1, 0x57, 0xF0, 0xE4, 0xFB, 0xFD, 0x7F, +0x58, 0x7E, 0x01, 0x02, 0x61, 0x41, 0x90, 0x94, +0x7D, 0xE0, 0xFD, 0x7B, 0x51, 0xE4, 0xFF, 0xA1, +0x87, 0xE4, 0x90, 0x92, 0xBA, 0xF1, 0xED, 0x90, +0x92, 0x0A, 0xE0, 0xFF, 0xF1, 0x5E, 0xE0, 0x54, +0xFB, 0xF0, 0x80, 0x02, 0xF1, 0xEE, 0x90, 0x92, +0x0C, 0xE0, 0x64, 0x05, 0x70, 0x63, 0xD1, 0x37, +0xEF, 0x70, 0x5E, 0x80, 0x57, 0x90, 0x94, 0x7C, +0xE0, 0xFF, 0x64, 0x03, 0x60, 0x05, 0xEF, 0x64, +0x01, 0x70, 0x4E, 0x90, 0x92, 0x0C, 0xE0, 0x64, +0x05, 0x70, 0x46, 0x90, 0x94, 0x7C, 0xE0, 0x64, +0x01, 0x70, 0x2C, 0x12, 0x8F, 0x79, 0xE0, 0xD3, +0x94, 0x1F, 0x90, 0x92, 0x0A, 0xE0, 0x40, 0x0A, +0xF1, 0xD6, 0xE0, 0xFF, 0x7D, 0x00, 0x7C, 0x7C, +0x80, 0x12, 0xC3, 0xF1, 0xD6, 0xE0, 0xFB, 0x12, +0x8F, 0x79, 0xE0, 0x7D, 0x00, 0x25, 0xE0, 0x25, +0xE0, 0xFC, 0xAF, 0x03, 0x12, 0x98, 0xEE, 0x91, +0x0E, 0xFD, 0x7F, 0x02, 0x12, 0xAA, 0x52, 0xD1, +0x37, 0xEF, 0x70, 0x05, 0x7F, 0x06, 0x12, 0xAA, +0xF7, 0x22, 0xE4, 0xFB, 0xFD, 0x7F, 0xFF, 0x90, +0x05, 0x22, 0xED, 0xF0, 0x90, 0x92, 0x01, 0xEB, +0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, +0xD0, 0x90, 0x94, 0xF2, 0xEE, 0xF0, 0xA3, 0x12, +0xB1, 0x03, 0x90, 0x04, 0x1D, 0xE0, 0x60, 0x27, +0x90, 0x05, 0x22, 0xE0, 0x90, 0x94, 0xF8, 0xF0, +0x7B, 0x14, 0xD1, 0xE8, 0xEF, 0x64, 0x01, 0x70, +0x05, 0x12, 0xD0, 0x71, 0x80, 0x04, 0x7F, 0x00, +0x80, 0x15, 0x90, 0x94, 0xF8, 0xE0, 0xFD, 0x7B, +0x15, 0xE4, 0xFF, 0xB1, 0x87, 0x80, 0x03, 0x12, +0xD0, 0x71, 0x12, 0x9F, 0xF8, 0x7F, 0x01, 0xD0, +0xD0, 0x92, 0xAF, 0x22, 0x90, 0x92, 0x09, 0xE0, +0x30, 0xE0, 0x53, 0x90, 0x92, 0x0C, 0xE0, 0x70, +0x25, 0x7B, 0x16, 0x7D, 0x6F, 0xD1, 0xEA, 0x91, +0x0E, 0x12, 0xAA, 0xE3, 0x7D, 0x01, 0xB1, 0x92, +0x91, 0x0E, 0x12, 0xC5, 0x01, 0xE0, 0x44, 0x01, +0xF0, 0x12, 0xD1, 0x57, 0x12, 0xC6, 0x20, 0x90, +0x92, 0x0C, 0x74, 0x01, 0xF0, 0x22, 0x90, 0x92, +0x0C, 0xE0, 0x64, 0x01, 0x70, 0x1E, 0x91, 0x0E, +0x12, 0xC5, 0x00, 0xE0, 0x30, 0xE0, 0x15, 0x12, +0xAA, 0xE2, 0x7D, 0x01, 0xB1, 0x92, 0x12, 0xD1, +0x57, 0xF0, 0xE4, 0xFB, 0xFD, 0x7F, 0x54, 0x7E, +0x01, 0x02, 0x61, 0x41, 0x71, 0xAE, 0x22, 0xD1, +0xEE, 0xEF, 0x70, 0x02, 0xFF, 0x22, 0x91, 0x0E, +0x90, 0x92, 0x88, 0xF0, 0x12, 0xD0, 0xA7, 0xB5, +0x07, 0x04, 0xEE, 0x54, 0xF1, 0xF0, 0x91, 0x0E, +0xF5, 0x77, 0xE4, 0x90, 0x92, 0x0C, 0xF0, 0xE5, +0x77, 0x75, 0xF0, 0x1B, 0xA4, 0x24, 0x3B, 0xF5, +0x82, 0xE4, 0x34, 0x92, 0xF5, 0x83, 0xE0, 0x30, +0xE0, 0x27, 0xF1, 0x4E, 0xE0, 0x24, 0x8B, 0xF5, +0x82, 0xE4, 0x34, 0x92, 0xF5, 0x83, 0xE0, 0xFF, +0x12, 0xAA, 0xD2, 0xEF, 0xF1, 0x4D, 0xE0, 0x04, +0xF1, 0x4D, 0xE0, 0xFF, 0x90, 0x92, 0x8A, 0xE0, +0xFE, 0xEF, 0xB5, 0x06, 0x04, 0xF1, 0x4E, 0xE4, +0xF0, 0x12, 0xAA, 0xD2, 0xE0, 0xFC, 0x90, 0x92, +0x88, 0xE0, 0x12, 0xAA, 0xD4, 0xE0, 0x6C, 0x60, +0x0F, 0xE5, 0x77, 0x12, 0xD0, 0x4C, 0xAF, 0x04, +0x12, 0xA9, 0x59, 0xE5, 0x77, 0x12, 0x8B, 0xB0, +0xE5, 0x77, 0x12, 0x8F, 0xA6, 0x54, 0x07, 0xFF, +0x60, 0x03, 0xBF, 0x02, 0x0E, 0xE5, 0x77, 0xF1, +0xD9, 0xE0, 0xFF, 0x7E, 0x00, 0x7B, 0x04, 0xE4, +0xFD, 0xB1, 0x92, 0xAD, 0x77, 0x7F, 0x01, 0x12, +0xAA, 0x52, 0x90, 0x92, 0x89, 0xE0, 0xC3, 0x13, +0x54, 0x03, 0xFF, 0xBF, 0x02, 0x05, 0xE4, 0xFF, +0x12, 0xAA, 0xF7, 0x7F, 0x01, 0x22, 0x7B, 0x17, +0x7D, 0xFF, 0x7F, 0xFF, 0xB1, 0x87, 0xE4, 0x90, +0x95, 0x05, 0xF0, 0xA3, 0xF0, 0x90, 0x05, 0x22, +0xE0, 0x90, 0x95, 0x07, 0xF0, 0x7D, 0x47, 0x7F, +0xFF, 0x12, 0x98, 0xE3, 0x90, 0x05, 0xF8, 0xE0, +0x70, 0x15, 0xA3, 0xE0, 0x70, 0x11, 0xA3, 0xE0, +0x70, 0x0D, 0xA3, 0xE0, 0x70, 0x09, 0x12, 0xD1, +0xE9, 0x12, 0x98, 0xE3, 0x7F, 0x01, 0x22, 0xD3, +0x90, 0x95, 0x06, 0xE0, 0x94, 0xE8, 0x90, 0x95, +0x05, 0xE0, 0x94, 0x03, 0x40, 0x10, 0x90, 0x01, +0xC0, 0xE0, 0x44, 0x20, 0xF0, 0x12, 0xD1, 0xE9, +0x12, 0x98, 0xE3, 0x7F, 0x00, 0x22, 0x7F, 0x32, +0x7E, 0x00, 0x12, 0x7C, 0x9F, 0x90, 0x95, 0x05, +0x12, 0xBD, 0xFF, 0x80, 0xB7, 0xF0, 0x74, 0xAE, +0x25, 0x77, 0xF5, 0x82, 0xE4, 0x34, 0x92, 0xF5, +0x83, 0x22, 0x90, 0x92, 0x0A, 0xE0, 0xC3, 0x13, +0x54, 0x07, 0x75, 0xF0, 0x1B, 0xA4, 0x24, 0x3E, +0xF5, 0x82, 0xE4, 0x34, 0x92, 0xF5, 0x83, 0x22, +0xE4, 0x90, 0x94, 0x6F, 0xF0, 0x90, 0x92, 0x0A, +0xE0, 0x30, 0xE0, 0x59, 0xC3, 0x13, 0x54, 0x07, +0xFF, 0xF1, 0x62, 0xE0, 0xFE, 0x30, 0xE0, 0x4D, +0xEF, 0xF1, 0x62, 0xEE, 0x54, 0xFE, 0xF0, 0xEF, +0xF1, 0x62, 0x12, 0xC4, 0xB9, 0x30, 0xE0, 0x11, +0x90, 0x92, 0x0A, 0xE0, 0xFE, 0xF1, 0x5E, 0xEF, +0x54, 0xFB, 0xF0, 0x90, 0x94, 0x6F, 0x74, 0x01, +0xF0, 0x90, 0x04, 0xE0, 0xE0, 0x30, 0xE1, 0x1D, +0xF1, 0xEE, 0xF1, 0x5A, 0xE0, 0x44, 0x02, 0xF0, +0xE4, 0x90, 0x92, 0xBA, 0xF0, 0x91, 0x0E, 0xFD, +0x7F, 0x02, 0x12, 0xAA, 0x52, 0x90, 0x94, 0x6F, +0xE0, 0x60, 0x0A, 0x81, 0x17, 0xF1, 0x5A, 0xE0, +0x54, 0xFD, 0xF0, 0xB1, 0x82, 0x22, 0x13, 0x54, +0x07, 0x75, 0xF0, 0x1B, 0xA4, 0x24, 0x40, 0xF5, +0x82, 0xE4, 0x34, 0x92, 0xF5, 0x83, 0x22, 0x90, +0x00, 0x04, 0x02, 0x03, 0x0F, 0xF0, 0x90, 0x92, +0x0C, 0x74, 0x05, 0xF0, 0x22, 0xF0, 0x90, 0x00, +0x05, 0x02, 0x03, 0x0F, 0xFD, 0x75, 0xF0, 0x0E, +0xA4, 0x24, 0x0D, 0xF5, 0x82, 0xE4, 0x34, 0x92, +0x22, 0x8B, 0x5B, 0x8A, 0x5C, 0x89, 0x5D, 0x90, +0x92, 0xBD, 0xE0, 0x70, 0x10, 0x12, 0x02, 0xF6, +0x13, 0x13, 0x54, 0x3F, 0x30, 0xE0, 0x06, 0x90, +0x92, 0xC3, 0x74, 0x01, 0xF0, 0x90, 0x92, 0xBF, +0xE0, 0x70, 0x0F, 0x11, 0xD7, 0xC4, 0x54, 0x0F, +0xFF, 0xBF, 0x05, 0x06, 0x90, 0x92, 0xC4, 0x74, +0x01, 0xF0, 0x12, 0x8F, 0x6D, 0xFF, 0xF5, 0x5F, +0x12, 0x02, 0xF6, 0xFE, 0xC3, 0x13, 0x30, 0xE0, +0x07, 0x12, 0x8F, 0xF3, 0xF5, 0x60, 0x80, 0x02, +0x8F, 0x60, 0x85, 0x5F, 0x5E, 0xE5, 0x5E, 0xD3, +0x95, 0x60, 0x50, 0x28, 0x11, 0xD7, 0x54, 0x01, +0xFD, 0xAF, 0x5E, 0x12, 0x6E, 0x5F, 0xAF, 0x5E, +0x12, 0x77, 0x39, 0xEF, 0xAF, 0x5E, 0x70, 0x04, +0x11, 0x9F, 0x80, 0x02, 0xF1, 0xE0, 0x90, 0x92, +0xC4, 0xE0, 0x60, 0x04, 0xAF, 0x5E, 0x11, 0x9F, +0x05, 0x5E, 0x80, 0xD1, 0xE5, 0x5F, 0x70, 0x16, +0xFF, 0x12, 0x77, 0x39, 0xEF, 0x70, 0x0F, 0x12, +0xBF, 0x8B, 0x12, 0x79, 0x61, 0x12, 0xC6, 0xA5, +0x54, 0xBF, 0xF0, 0x54, 0x7F, 0xF0, 0x22, 0x7D, +0x01, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, +0x90, 0x93, 0xC3, 0xEF, 0xF0, 0xA3, 0xED, 0xF0, +0x7D, 0x44, 0x7F, 0x6F, 0x51, 0x81, 0x90, 0x93, +0xC4, 0xE0, 0x90, 0x93, 0xC3, 0xB4, 0x01, 0x09, +0xE0, 0x51, 0xBC, 0xE0, 0x44, 0x04, 0xF0, 0x80, +0x07, 0xE0, 0x51, 0xBC, 0xE0, 0x54, 0xFB, 0xF0, +0x11, 0xE0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xAB, +0x5B, 0xAA, 0x5C, 0xA9, 0x5D, 0x02, 0x02, 0xF6, +0xE4, 0xFD, 0xFF, 0x90, 0x05, 0x22, 0xEF, 0xF0, +0x90, 0x92, 0x01, 0xED, 0xF0, 0x22, 0xD3, 0x10, +0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x94, 0x81, +0xEF, 0xF0, 0xA3, 0xEC, 0xF0, 0xA3, 0xED, 0xF0, +0x90, 0x04, 0x1D, 0xE0, 0x60, 0x1C, 0x90, 0x05, +0x22, 0xE0, 0x90, 0x94, 0x86, 0xF0, 0x7D, 0x36, +0x51, 0x7F, 0xBF, 0x01, 0x02, 0x31, 0xD4, 0x90, +0x94, 0x86, 0xE0, 0xFF, 0x7D, 0x37, 0x11, 0xE3, +0x80, 0x02, 0x31, 0xD4, 0x90, 0x05, 0x22, 0xE0, +0x54, 0x6F, 0xFF, 0x7D, 0x38, 0x11, 0xE3, 0xF1, +0xF8, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xD3, 0x10, +0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x94, 0xFE, +0xED, 0xF0, 0xA3, 0xEB, 0xF0, 0x90, 0x94, 0xFD, +0xEF, 0xF0, 0xE4, 0xFD, 0xFC, 0x12, 0x7B, 0x2A, +0x7C, 0x00, 0xAD, 0x07, 0x90, 0x94, 0xFD, 0xE0, +0x90, 0x04, 0x25, 0xF0, 0x90, 0x94, 0xFE, 0xE0, +0x60, 0x05, 0x51, 0xAC, 0x44, 0x80, 0xF0, 0xAF, +0x05, 0x74, 0x20, 0x2F, 0xF5, 0x82, 0xE4, 0x34, +0xFC, 0xF5, 0x83, 0xE0, 0x54, 0xC0, 0xF0, 0x51, +0xAC, 0x54, 0xC0, 0xF0, 0x90, 0x95, 0x00, 0xE0, +0xFF, 0xAE, 0x05, 0x74, 0x18, 0x2E, 0xF5, 0x82, +0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xEF, 0xF0, 0x51, +0x8E, 0xF5, 0x83, 0xE0, 0x20, 0xE1, 0x17, 0x54, +0x01, 0xFF, 0x90, 0x94, 0xFF, 0xE0, 0x25, 0xE0, +0x25, 0xE0, 0xFB, 0xEF, 0x44, 0x02, 0x4B, 0xFF, +0x51, 0x8E, 0xF5, 0x83, 0xEF, 0xF0, 0xAF, 0x05, +0x74, 0x11, 0x2F, 0xF5, 0x82, 0xE4, 0x34, 0xFC, +0xF5, 0x83, 0x74, 0xFF, 0xF0, 0x74, 0x29, 0x2F, +0xF5, 0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, +0x54, 0xF7, 0xF0, 0xAE, 0x04, 0xAF, 0x05, 0xD0, +0xD0, 0x92, 0xAF, 0x22, 0x90, 0x94, 0x81, 0xE0, +0xFF, 0x90, 0x95, 0x00, 0x74, 0x0C, 0xF0, 0xE4, +0xFB, 0x7D, 0x01, 0x31, 0x36, 0x90, 0x94, 0x84, +0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x90, 0x94, 0x82, +0xE0, 0xFC, 0xA3, 0xE0, 0xFD, 0x02, 0x77, 0xD8, +0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, +0x94, 0x92, 0xEF, 0xF0, 0xA3, 0xED, 0xF0, 0x90, +0x84, 0xC3, 0xE0, 0x04, 0xF0, 0x90, 0x04, 0x1D, +0xE0, 0x60, 0x35, 0x90, 0x05, 0x22, 0xE0, 0x90, +0x94, 0x96, 0xF0, 0x7D, 0x26, 0x51, 0x7F, 0xEF, +0x64, 0x01, 0x70, 0x17, 0x51, 0x97, 0xFB, 0x7D, +0x01, 0x12, 0x3A, 0xC2, 0x12, 0xD0, 0xFC, 0x20, +0xE0, 0x09, 0x90, 0x92, 0x09, 0xE0, 0x20, 0xE0, +0x02, 0x51, 0xA1, 0x90, 0x94, 0x96, 0xE0, 0xFF, +0x7D, 0x27, 0x11, 0xE3, 0x51, 0x86, 0x80, 0x1E, +0x51, 0x86, 0x51, 0x97, 0xFB, 0x90, 0x95, 0x00, +0x74, 0x0A, 0xF0, 0x7D, 0x01, 0x31, 0x36, 0x12, +0xD0, 0xFC, 0x20, 0xE0, 0x09, 0x90, 0x92, 0x09, +0xE0, 0x20, 0xE0, 0x02, 0x51, 0xA1, 0xF1, 0xF8, +0x90, 0x84, 0xBF, 0xA3, 0xE0, 0x24, 0x7F, 0xF5, +0x82, 0xE4, 0x34, 0x82, 0xF5, 0x83, 0x74, 0x01, +0xF0, 0xFF, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x7F, +0xFF, 0x11, 0xE3, 0x02, 0x96, 0xEE, 0x90, 0x94, +0x92, 0xE0, 0xFF, 0x02, 0x5C, 0xA3, 0x74, 0x12, +0x2E, 0xF5, 0x82, 0xE4, 0x34, 0xFC, 0x22, 0x90, +0x84, 0xC8, 0xE0, 0xFF, 0x90, 0x94, 0x93, 0xE0, +0x22, 0x90, 0x94, 0x94, 0xE0, 0xFE, 0xA3, 0xE0, +0xFF, 0x02, 0x50, 0xD7, 0x74, 0x21, 0x2F, 0xF5, +0x82, 0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xE0, 0x22, +0xE0, 0xFD, 0xE5, 0x76, 0xC4, 0x54, 0xF0, 0x24, +0x05, 0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, +0x22, 0x8D, 0x76, 0xEF, 0x30, 0xE6, 0x1A, 0x71, +0x48, 0x51, 0xB8, 0xE0, 0x54, 0x03, 0x90, 0x91, +0x0B, 0xF0, 0xE4, 0xFB, 0xAF, 0x76, 0x12, 0x27, +0x3D, 0x71, 0x3B, 0xD1, 0x5D, 0x74, 0x01, 0x80, +0x49, 0xD1, 0x64, 0x04, 0xF0, 0xD1, 0x64, 0x64, +0x02, 0x70, 0x1E, 0x74, 0xA9, 0x25, 0x76, 0xF1, +0x41, 0xE0, 0xFD, 0xF4, 0x60, 0x02, 0x80, 0x04, +0x71, 0x48, 0xE0, 0xFD, 0x51, 0xBA, 0x12, 0xD1, +0x3B, 0x71, 0x48, 0xD1, 0x5D, 0x74, 0x02, 0x80, +0x21, 0xD1, 0x64, 0xD3, 0x94, 0x03, 0x40, 0x0D, +0xAF, 0x76, 0x12, 0x6D, 0x94, 0x71, 0x3B, 0xD1, +0x5D, 0x74, 0x03, 0x80, 0x0D, 0x71, 0x48, 0x51, +0xB8, 0x12, 0xD1, 0x3B, 0x71, 0x48, 0xD1, 0x5D, +0x74, 0x02, 0xF0, 0xAB, 0x76, 0xE4, 0xFD, 0xFF, +0x02, 0x52, 0xC3, 0x74, 0xBC, 0x25, 0x76, 0xF5, +0x82, 0xE4, 0x34, 0x90, 0xF5, 0x83, 0xE4, 0xF0, +0xE5, 0x76, 0xC4, 0x54, 0xF0, 0x24, 0x00, 0xF5, +0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0x22, 0x90, +0x04, 0x85, 0xE0, 0xF5, 0x6B, 0x90, 0x94, 0xA8, +0xE0, 0x04, 0xF0, 0xE4, 0xF5, 0x63, 0x90, 0x85, +0xBB, 0xE0, 0xFF, 0xE5, 0x63, 0xC3, 0x9F, 0x40, +0x02, 0xC1, 0x44, 0xE5, 0x63, 0x71, 0x4A, 0xE0, +0xF5, 0x6D, 0x12, 0xD1, 0x87, 0xE0, 0x65, 0x6D, +0x60, 0x16, 0x90, 0x8A, 0x71, 0xE5, 0x6D, 0xF0, +0xE4, 0xA3, 0xF0, 0xAB, 0x63, 0xFD, 0xFF, 0x12, +0x52, 0xC3, 0x12, 0xD1, 0x87, 0xE5, 0x6D, 0xF0, +0x90, 0x04, 0xA0, 0xE0, 0x64, 0x01, 0x70, 0x4C, +0xA3, 0xE0, 0x65, 0x63, 0x70, 0x46, 0xA3, 0xE0, +0xF5, 0x64, 0xA3, 0xE0, 0x90, 0x94, 0x45, 0xF0, +0xE5, 0x63, 0x71, 0x4A, 0xE0, 0x65, 0x64, 0x70, +0x02, 0xC1, 0x40, 0xE5, 0x63, 0x71, 0x4A, 0xE5, +0x64, 0xF0, 0xE5, 0x63, 0x51, 0xBC, 0xE0, 0x54, +0xFC, 0xFF, 0x90, 0x94, 0x45, 0xE0, 0x54, 0x03, +0x4F, 0xFF, 0xE5, 0x63, 0x51, 0xBC, 0xEF, 0xF0, +0x90, 0x8A, 0x71, 0xE5, 0x64, 0xF0, 0xA3, 0x74, +0xFF, 0xF0, 0xAB, 0x63, 0xE4, 0xFD, 0xFF, 0x12, +0x52, 0xC3, 0xC1, 0x40, 0xAF, 0x63, 0x12, 0x77, +0x39, 0xEF, 0x70, 0x02, 0xC1, 0x40, 0x75, 0xF0, +0x12, 0xE5, 0x63, 0x12, 0xA1, 0x8F, 0x12, 0xA3, +0x01, 0x30, 0xE0, 0x02, 0xC1, 0x40, 0xE5, 0x63, +0x13, 0x13, 0x13, 0x54, 0x1F, 0x24, 0x75, 0x12, +0xB3, 0x11, 0x7C, 0x00, 0xE5, 0x63, 0x12, 0xB2, +0x90, 0x80, 0x05, 0xC3, 0x33, 0xCE, 0x33, 0xCE, +0xD8, 0xF9, 0xFF, 0xEE, 0x5C, 0xFE, 0xEF, 0x5D, +0x4E, 0x60, 0x02, 0xC1, 0x40, 0xF1, 0xD5, 0xE0, +0xFE, 0xA3, 0xE0, 0x4E, 0x70, 0x07, 0xF1, 0xCA, +0xE0, 0x70, 0x02, 0xC1, 0x40, 0xE5, 0x63, 0x75, +0xF0, 0x12, 0xA4, 0x24, 0x44, 0xF9, 0x74, 0x89, +0x35, 0xF0, 0xFA, 0x7B, 0x01, 0x90, 0x94, 0x40, +0x12, 0x87, 0x4E, 0x90, 0x00, 0x02, 0x12, 0x04, +0x18, 0xFF, 0x12, 0x03, 0xED, 0x2F, 0xFF, 0x12, +0xD1, 0xE1, 0xFF, 0x12, 0xD1, 0xB9, 0x90, 0x00, +0x08, 0x12, 0x04, 0x18, 0x2F, 0xF5, 0x6C, 0xF1, +0xD5, 0xE0, 0xF5, 0x68, 0xA3, 0xE0, 0xF5, 0x69, +0xF1, 0xCA, 0xE0, 0xFF, 0x90, 0x94, 0x43, 0xE4, +0xF0, 0xA3, 0xEF, 0xF0, 0xE5, 0x63, 0x71, 0x4A, +0xE0, 0xF5, 0x64, 0x54, 0x80, 0xFF, 0xE5, 0x64, +0x54, 0x7F, 0xF5, 0x65, 0x75, 0xF0, 0x12, 0xE5, +0x63, 0x12, 0xB5, 0x17, 0xFE, 0xE5, 0x65, 0xD3, +0x9E, 0x40, 0x07, 0x8E, 0x65, 0xE5, 0x65, 0x4F, +0xF5, 0x64, 0x74, 0x7C, 0x25, 0x63, 0xF5, 0x82, +0xE4, 0x34, 0x90, 0xF5, 0x83, 0xE0, 0xC3, 0x94, +0x05, 0x40, 0x02, 0xC1, 0x3D, 0xE5, 0x65, 0x90, +0x82, 0xE1, 0x93, 0xF5, 0x6A, 0xEF, 0x60, 0x04, +0x05, 0x6A, 0x05, 0x6A, 0xE5, 0x65, 0xC3, 0x94, +0x0C, 0x40, 0x21, 0x74, 0x98, 0x25, 0x63, 0xF5, +0x82, 0xE4, 0x34, 0x94, 0xF5, 0x83, 0xE0, 0xFF, +0x54, 0x7F, 0xFE, 0xEF, 0x30, 0xE7, 0x06, 0xE5, +0x6A, 0x2E, 0xFF, 0x80, 0x05, 0xC3, 0xE5, 0x6A, +0x9E, 0xFF, 0x8F, 0x6A, 0xE5, 0x6A, 0xD3, 0x94, +0x1A, 0xAF, 0x6A, 0x40, 0x02, 0x7F, 0x1A, 0x8F, +0x6A, 0xE5, 0x64, 0x90, 0x83, 0x59, 0x93, 0xFF, +0xD3, 0x90, 0x94, 0x44, 0xE0, 0x9F, 0x90, 0x94, +0x43, 0xE0, 0x94, 0x00, 0x40, 0x02, 0xA1, 0xFD, +0xC3, 0xE5, 0x69, 0x94, 0x0A, 0xE5, 0x68, 0x94, +0x00, 0x40, 0x02, 0xA1, 0xB8, 0xD1, 0x45, 0xE0, +0xC3, 0x94, 0x01, 0x40, 0x05, 0xD1, 0x45, 0xE0, +0x14, 0xF0, 0x90, 0x94, 0x40, 0x12, 0x87, 0x45, +0x90, 0x00, 0x08, 0x12, 0x04, 0x18, 0xFF, 0x90, +0x94, 0x44, 0xE0, 0x2F, 0xFF, 0x90, 0x94, 0x43, +0xE0, 0x35, 0xF0, 0xFE, 0x12, 0xD1, 0xB9, 0xEE, +0x35, 0xF0, 0xFE, 0x12, 0xD1, 0xE1, 0xFD, 0xEE, +0x35, 0xF0, 0xFC, 0xE5, 0x68, 0xC3, 0x13, 0xFE, +0xE5, 0x69, 0x13, 0xFF, 0xD3, 0xED, 0x9F, 0xEC, +0x9E, 0x40, 0x0D, 0xE5, 0x63, 0x94, 0x05, 0x50, +0x05, 0xD1, 0x45, 0x74, 0x03, 0xF0, 0xA1, 0xFD, +0x90, 0x94, 0x40, 0x12, 0x87, 0x45, 0x12, 0x03, +0xED, 0x65, 0x6C, 0x70, 0x02, 0xE5, 0xF0, 0x70, +0x2A, 0xE5, 0x63, 0xC3, 0x94, 0x05, 0x50, 0x0A, +0xD1, 0x45, 0xE0, 0xD3, 0x94, 0x00, 0x40, 0x02, +0x80, 0x07, 0xE5, 0x6C, 0xC3, 0x94, 0x03, 0x50, +0x08, 0x7D, 0x06, 0xAF, 0x63, 0xF1, 0x6F, 0xC1, +0x40, 0xE4, 0xFD, 0xAF, 0x63, 0xD1, 0x71, 0xF1, +0x6B, 0xC1, 0x3D, 0x12, 0xD1, 0xD2, 0xC1, 0x3D, +0xD1, 0x45, 0xE4, 0xF0, 0x90, 0x94, 0x4A, 0x74, +0x02, 0xF0, 0xAB, 0x6A, 0xAD, 0x63, 0xAF, 0x69, +0xAE, 0x68, 0x12, 0xCB, 0x6F, 0x8E, 0x66, 0x8F, +0x67, 0x12, 0xD1, 0x49, 0xC3, 0x74, 0x01, 0x93, +0x95, 0x67, 0xE4, 0x93, 0x95, 0x66, 0x50, 0x0C, +0xD1, 0x51, 0xE4, 0xF0, 0x7D, 0x01, 0xAF, 0x63, +0xD1, 0x71, 0x80, 0x51, 0x12, 0xD1, 0xD9, 0xC3, +0xE5, 0x67, 0x9F, 0xE5, 0x66, 0x94, 0x00, 0x50, +0x0D, 0xD1, 0x51, 0xE4, 0xF0, 0x7D, 0x01, 0xAF, +0x63, 0x12, 0xB4, 0x58, 0x80, 0x37, 0xF1, 0x6B, +0xD1, 0x51, 0xE0, 0x04, 0xF0, 0xE5, 0x65, 0x90, +0x83, 0x6D, 0x93, 0xFF, 0xD1, 0x51, 0xE0, 0xC3, +0x9F, 0x40, 0x22, 0xD1, 0x51, 0xE4, 0xF0, 0x12, +0xD1, 0xD9, 0x12, 0xD1, 0x49, 0x74, 0x01, 0x93, +0x2F, 0xFF, 0xE4, 0x93, 0x34, 0x00, 0xC3, 0x13, +0xFE, 0xEF, 0x13, 0xFF, 0xE5, 0x63, 0xF1, 0x5F, +0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x12, 0xD1, 0xD2, +0x05, 0x63, 0x61, 0x66, 0x22, 0x74, 0xB9, 0x25, +0x63, 0xF5, 0x82, 0xE4, 0x34, 0x94, 0xF5, 0x83, +0x22, 0x74, 0xAC, 0x25, 0x63, 0xF5, 0x82, 0xE4, +0x34, 0x8F, 0xF5, 0x83, 0x22, 0xE0, 0x90, 0x8A, +0x71, 0xF0, 0xA3, 0x22, 0x74, 0xBC, 0x25, 0x76, +0xF5, 0x82, 0xE4, 0x34, 0x90, 0xF5, 0x83, 0xE0, +0x22, 0x8F, 0x6E, 0x8D, 0x6F, 0xEF, 0x71, 0x4A, +0xE0, 0xFD, 0x54, 0x7F, 0xF5, 0x70, 0xED, 0x54, +0x80, 0xF5, 0x71, 0x75, 0xF0, 0x12, 0xEF, 0x12, +0xB5, 0x17, 0xF5, 0x73, 0x75, 0xF0, 0x12, 0xEF, +0x12, 0xA1, 0x8F, 0xC4, 0x54, 0x03, 0xF5, 0x74, +0xF1, 0x3D, 0x74, 0xFF, 0xF0, 0xF1, 0x49, 0xEE, +0xF0, 0xA3, 0xEF, 0xF0, 0xE5, 0x71, 0x4D, 0xFF, +0x12, 0xB5, 0x0B, 0xEF, 0xF0, 0xE5, 0x6E, 0x51, +0xBC, 0xE0, 0x54, 0x03, 0xF5, 0x72, 0x74, 0x4C, +0x25, 0x6E, 0x12, 0xB5, 0x1F, 0xE5, 0x72, 0xF0, +0xE5, 0x70, 0x65, 0x73, 0x70, 0x27, 0x75, 0xF0, +0x12, 0xE5, 0x6E, 0x12, 0xA2, 0xEE, 0xC4, 0x13, +0x54, 0x07, 0x30, 0xE0, 0x0B, 0xE5, 0x71, 0x70, +0x07, 0xE5, 0x70, 0x44, 0x80, 0xFD, 0x80, 0x50, +0xF1, 0x49, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x7D, +0x07, 0xAF, 0x6E, 0xE1, 0x6F, 0xE5, 0x70, 0xC3, +0x95, 0x73, 0x50, 0x35, 0xAB, 0x6E, 0xAD, 0x73, +0xAF, 0x70, 0x12, 0x72, 0xEA, 0xAD, 0x07, 0xE5, +0x70, 0xC3, 0x94, 0x0C, 0x40, 0x2A, 0x75, 0xF0, +0x12, 0xE5, 0x6E, 0x12, 0xA2, 0xEE, 0xFE, 0xC4, +0x13, 0x54, 0x07, 0x30, 0xE0, 0x1A, 0xE5, 0x6F, +0x60, 0x16, 0xE5, 0x71, 0x70, 0x12, 0xE5, 0x70, +0x44, 0x80, 0xFD, 0xF1, 0x3D, 0xEF, 0xF0, 0x80, +0x07, 0x12, 0xB5, 0x0B, 0xE5, 0x73, 0xF0, 0xFD, +0x90, 0x91, 0x0B, 0xE5, 0x72, 0xF0, 0xAB, 0x6F, +0xAF, 0x6E, 0x02, 0x27, 0x3D, 0x74, 0xA9, 0x25, +0x6E, 0xF5, 0x82, 0xE4, 0x34, 0x94, 0xF5, 0x83, +0x22, 0xE5, 0x70, 0x25, 0xE0, 0x24, 0xF5, 0xF5, +0x82, 0xE4, 0x34, 0x82, 0xF5, 0x83, 0xE4, 0x93, +0xFE, 0x74, 0x01, 0x93, 0xFF, 0xE5, 0x6E, 0x25, +0xE0, 0x24, 0x7B, 0xF5, 0x82, 0xE4, 0x34, 0x8F, +0xF5, 0x83, 0x22, 0x7D, 0x07, 0xAF, 0x63, 0xED, +0x30, 0xE0, 0x22, 0x75, 0xF0, 0x12, 0xEF, 0x90, +0x89, 0x44, 0xF1, 0xBE, 0x90, 0x89, 0x46, 0xF1, +0xBE, 0x90, 0x89, 0x48, 0xF1, 0xBE, 0x90, 0x89, +0x4A, 0xF1, 0xBE, 0x90, 0x89, 0x4C, 0x12, 0x05, +0x28, 0xE4, 0xF0, 0xA3, 0xF0, 0xED, 0x30, 0xE1, +0x0A, 0x75, 0xF0, 0x12, 0xEF, 0xF1, 0xDA, 0xE4, +0xF0, 0xA3, 0xF0, 0xED, 0x30, 0xE2, 0x08, 0x75, +0xF0, 0x12, 0xEF, 0xF1, 0xCF, 0xE4, 0xF0, 0x12, +0xD1, 0x60, 0xE0, 0x54, 0xBF, 0x44, 0x80, 0xFE, +0x12, 0xD1, 0x60, 0xEE, 0xF0, 0x22, 0x12, 0x05, +0x28, 0xE4, 0xF0, 0xA3, 0xF0, 0x75, 0xF0, 0x12, +0xEF, 0x22, 0x75, 0xF0, 0x12, 0xE5, 0x63, 0x90, +0x89, 0x42, 0x02, 0x05, 0x28, 0x75, 0xF0, 0x12, +0xE5, 0x63, 0x90, 0x89, 0x40, 0x02, 0x05, 0x28, +0xE4, 0xFD, 0x01, 0xA1, 0x7D, 0x1F, 0x7F, 0x6F, +0x11, 0xE3, 0x90, 0x05, 0x27, 0xE0, 0x54, 0xBF, +0xF0, 0x90, 0x85, 0xBF, 0x74, 0x04, 0xF0, 0x22, +0x90, 0x04, 0x1F, 0x74, 0x20, 0xF0, 0x22, 0x11, +0x37, 0x90, 0x04, 0x24, 0xE0, 0xF5, 0x5B, 0xE4, +0xFF, 0x12, 0x8F, 0x58, 0x11, 0x2A, 0x75, 0xF0, +0x0E, 0xA4, 0x24, 0x19, 0xF5, 0x82, 0xE4, 0x34, +0x92, 0xF5, 0x83, 0xEE, 0xF0, 0x11, 0x2A, 0x12, +0x97, 0xD9, 0xEE, 0xF0, 0x0F, 0xEF, 0xB4, 0x03, +0xE0, 0x22, 0x8F, 0x82, 0x75, 0x83, 0x00, 0x12, +0x03, 0x0F, 0x25, 0x5B, 0xFE, 0xEF, 0x22, 0x90, +0x93, 0xC3, 0x02, 0x87, 0x4E, 0x11, 0x37, 0x12, +0x8F, 0x58, 0x12, 0x02, 0xF6, 0x54, 0x7F, 0xFD, +0x12, 0x8F, 0x73, 0xFE, 0x54, 0x1F, 0x90, 0x93, +0xC7, 0x51, 0xFD, 0x90, 0x93, 0xC6, 0x12, 0x8F, +0xF2, 0xFE, 0x54, 0x03, 0xFC, 0xEE, 0x54, 0x30, +0xC4, 0x54, 0x0F, 0x90, 0x93, 0xC9, 0x12, 0x8F, +0xF2, 0xFE, 0x54, 0x40, 0xC4, 0x13, 0x13, 0x54, +0x03, 0x90, 0x93, 0xC8, 0x51, 0xFD, 0xFF, 0x12, +0x8F, 0xF3, 0xFB, 0x54, 0x08, 0x13, 0x13, 0x13, +0x54, 0x1F, 0x90, 0x93, 0xCB, 0xF0, 0xFA, 0xEB, +0x54, 0x04, 0x13, 0x13, 0x54, 0x3F, 0xA3, 0xF0, +0xEF, 0x54, 0x01, 0xC4, 0x33, 0x33, 0x33, 0x54, +0x80, 0x31, 0x8A, 0x54, 0x7F, 0x4F, 0xF0, 0x90, +0x93, 0xC8, 0xE0, 0x54, 0x01, 0xC4, 0x33, 0x33, +0x54, 0xC0, 0x31, 0x8A, 0x54, 0xBF, 0x4F, 0xF0, +0xEA, 0x60, 0x02, 0x21, 0x89, 0x90, 0x93, 0xC7, +0xE0, 0x54, 0x1F, 0x51, 0xE9, 0x54, 0xE0, 0x4F, +0xF0, 0xEC, 0x54, 0x03, 0x31, 0x8A, 0x54, 0xFC, +0x4F, 0xF0, 0xEC, 0x54, 0x03, 0x25, 0xE0, 0x25, +0xE0, 0x31, 0x8A, 0x54, 0xF3, 0x4F, 0xF0, 0x90, +0x93, 0xC6, 0xE0, 0x54, 0x01, 0xC4, 0x33, 0x54, +0xE0, 0x51, 0xE9, 0x54, 0xDF, 0x4F, 0xF0, 0x90, +0x93, 0xC9, 0xE0, 0x54, 0x03, 0xC4, 0x54, 0xF0, +0x31, 0x8A, 0x54, 0xCF, 0x4F, 0xF1, 0x24, 0xE0, +0x54, 0xFB, 0xF1, 0x24, 0xC0, 0x83, 0xC0, 0x82, +0xE0, 0xFF, 0x90, 0x93, 0xCC, 0xE0, 0x12, 0xD1, +0xCA, 0xD0, 0x82, 0xD0, 0x83, 0xF0, 0x90, 0x92, +0xC3, 0xE0, 0x60, 0x31, 0x12, 0x8F, 0x58, 0xE9, +0x24, 0x03, 0xF1, 0xEE, 0x54, 0x1F, 0x12, 0x03, +0x3C, 0x90, 0x93, 0xCA, 0x74, 0x01, 0xF0, 0x90, +0x93, 0xCA, 0xE0, 0xFF, 0xC3, 0x94, 0x04, 0x50, +0x14, 0xEF, 0x12, 0x8F, 0x52, 0x8F, 0x82, 0x8E, +0x83, 0xE4, 0x12, 0x03, 0x4E, 0x90, 0x93, 0xCA, +0xE0, 0x04, 0xF0, 0x80, 0xE2, 0x90, 0x92, 0xC1, +0xE0, 0x54, 0x07, 0xFF, 0xBF, 0x05, 0x0A, 0xEC, +0xB4, 0x01, 0x06, 0x90, 0x92, 0xC6, 0x74, 0x01, +0xF0, 0xE4, 0x90, 0x93, 0xCA, 0xF0, 0x90, 0x93, +0xCA, 0xE0, 0xFC, 0x12, 0x8F, 0x52, 0x8F, 0x82, +0x8E, 0x83, 0x12, 0x03, 0x0F, 0xFF, 0xED, 0xF1, +0xF5, 0xF5, 0x83, 0xE5, 0x82, 0x2C, 0xF1, 0x36, +0xEF, 0xF0, 0x90, 0x93, 0xCA, 0xE0, 0x04, 0xF0, +0xE0, 0xB4, 0x04, 0xDA, 0xAF, 0x05, 0x12, 0x17, +0x8E, 0x22, 0xFF, 0x75, 0xF0, 0x12, 0xED, 0x90, +0x89, 0x3F, 0x12, 0x05, 0x28, 0xE0, 0x22, 0xD3, +0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0xD1, 0x14, +0x20, 0xE6, 0x02, 0x41, 0xB0, 0x90, 0x00, 0x8C, +0xE0, 0x90, 0x95, 0x08, 0xF0, 0x7F, 0x8D, 0x12, +0x7B, 0x51, 0x90, 0x95, 0x09, 0xEF, 0xF0, 0x90, +0x00, 0x8E, 0xE0, 0x90, 0x95, 0x0A, 0xF0, 0x90, +0x95, 0x09, 0xE0, 0x24, 0xFC, 0x60, 0x0F, 0x24, +0x03, 0x60, 0x02, 0x41, 0xA9, 0x90, 0x95, 0x08, +0xE0, 0xFF, 0xD1, 0x1B, 0x41, 0xA9, 0x90, 0x95, +0x08, 0xE0, 0x24, 0xDC, 0xF5, 0x82, 0xE4, 0x34, +0x8F, 0x51, 0xF6, 0xFF, 0x51, 0xE2, 0x75, 0xF0, +0x12, 0x31, 0x8F, 0x13, 0x13, 0x54, 0x03, 0xFB, +0x0D, 0xE4, 0xFF, 0x51, 0xE2, 0x75, 0xF0, 0x12, +0x31, 0x8F, 0x71, 0x01, 0xFB, 0x0D, 0xE4, 0xFF, +0x51, 0xE2, 0x75, 0xF0, 0x12, 0x31, 0x8F, 0xC4, +0x54, 0x03, 0xFB, 0x0D, 0xE4, 0xFF, 0x51, 0xE2, +0x75, 0xF0, 0x12, 0x12, 0xB5, 0x17, 0xFB, 0xE4, +0xFD, 0x0F, 0x51, 0xE2, 0x75, 0xF0, 0x12, 0x90, +0x89, 0x3D, 0x12, 0x05, 0x28, 0x51, 0xDF, 0x75, +0xF0, 0x12, 0x51, 0xEE, 0xC4, 0x13, 0x54, 0x01, +0xFB, 0x0D, 0x7F, 0x01, 0x51, 0xE2, 0x75, 0xF0, +0x12, 0x51, 0xEE, 0x54, 0x1F, 0x51, 0xE0, 0xF1, +0xF5, 0x51, 0xF6, 0x0F, 0x51, 0xE2, 0x75, 0xF0, +0x08, 0xA4, 0x24, 0x01, 0xF5, 0x82, 0xE4, 0x34, +0x82, 0x51, 0xDD, 0x75, 0xF0, 0x08, 0xA4, 0x24, +0x02, 0xF5, 0x82, 0xE4, 0x34, 0x82, 0x51, 0xDD, +0x75, 0xF0, 0x08, 0xA4, 0x24, 0x03, 0xF5, 0x82, +0xE4, 0x34, 0x82, 0x51, 0xDD, 0x75, 0xF0, 0x08, +0xA4, 0x24, 0x04, 0xF5, 0x82, 0xE4, 0x34, 0x82, +0x51, 0xF6, 0x0F, 0x51, 0xE2, 0x75, 0xF0, 0x08, +0xA4, 0x24, 0x05, 0xF5, 0x82, 0xE4, 0x34, 0x82, +0x51, 0xDD, 0x75, 0xF0, 0x08, 0xA4, 0x24, 0x06, +0xF5, 0x82, 0xE4, 0x34, 0x82, 0x51, 0xDD, 0x75, +0xF0, 0x08, 0xA4, 0x24, 0x07, 0xF5, 0x82, 0xE4, +0x34, 0x82, 0xF5, 0x83, 0xE0, 0xFB, 0x0D, 0x51, +0xB5, 0xD1, 0x14, 0x30, 0xE0, 0x02, 0xF1, 0xD2, +0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xEF, 0x70, 0x04, +0x74, 0xF0, 0x80, 0x16, 0xEF, 0xB4, 0x01, 0x04, +0x74, 0xF4, 0x80, 0x0E, 0xEF, 0xB4, 0x02, 0x04, +0x74, 0xF8, 0x80, 0x06, 0xEF, 0xB4, 0x03, 0x0C, +0x74, 0xFC, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0x02, +0xF5, 0x83, 0xEB, 0xF0, 0x22, 0xF5, 0x83, 0xE0, +0xFB, 0x0D, 0x51, 0xB5, 0x90, 0x95, 0x08, 0xE0, +0x22, 0xFF, 0x75, 0xF0, 0x12, 0xED, 0x90, 0x89, +0x3E, 0x12, 0x05, 0x28, 0xE0, 0x22, 0xF5, 0x83, +0xE0, 0xFB, 0xE4, 0xFD, 0x22, 0xF0, 0xEE, 0x54, +0x80, 0xC4, 0x13, 0x13, 0x13, 0x54, 0x01, 0x22, +0x7D, 0x01, 0x7F, 0x04, 0xD3, 0x10, 0xAF, 0x01, +0xC3, 0xC0, 0xD0, 0x90, 0x95, 0x1B, 0xED, 0xF0, +0x90, 0x85, 0xC1, 0xE0, 0xFE, 0xC4, 0x13, 0x13, +0x54, 0x03, 0x30, 0xE0, 0x02, 0x81, 0x66, 0xEE, +0x71, 0x01, 0x30, 0xE0, 0x02, 0x81, 0x66, 0x90, +0x85, 0xC8, 0xE0, 0xFE, 0x6F, 0x70, 0x02, 0x81, +0x66, 0xEF, 0x70, 0x02, 0x61, 0xD1, 0x24, 0xFE, +0x70, 0x02, 0x81, 0x0E, 0x24, 0xFE, 0x60, 0x4D, +0x24, 0xFC, 0x70, 0x02, 0x81, 0x4D, 0x24, 0xFC, +0x60, 0x02, 0x81, 0x5F, 0xEE, 0xB4, 0x0E, 0x03, +0x12, 0x74, 0x93, 0x90, 0x85, 0xC8, 0xE0, 0x70, +0x05, 0x7F, 0x01, 0x12, 0x79, 0x80, 0x90, 0x85, +0xC8, 0xE0, 0xB4, 0x06, 0x03, 0x12, 0x73, 0x8E, +0x90, 0x85, 0xC8, 0xE0, 0xB4, 0x04, 0x0F, 0x90, +0x95, 0x1B, 0xE0, 0xFF, 0x60, 0x05, 0x12, 0x6D, +0x4C, 0x80, 0x03, 0x12, 0x79, 0x61, 0x90, 0x85, +0xC8, 0xE0, 0x64, 0x08, 0x60, 0x02, 0x81, 0x5F, +0x12, 0x7A, 0xB9, 0x81, 0x5F, 0x90, 0x85, 0xC8, +0xE0, 0x70, 0x05, 0x7F, 0x01, 0x12, 0x79, 0x80, +0x90, 0x85, 0xC8, 0xE0, 0xB4, 0x06, 0x03, 0x12, +0x73, 0x8E, 0x90, 0x85, 0xC8, 0xE0, 0xB4, 0x0E, +0x08, 0x91, 0x6B, 0xBF, 0x01, 0x03, 0x12, 0x74, +0x93, 0x90, 0x85, 0xC8, 0xE0, 0x64, 0x0C, 0x60, +0x02, 0x81, 0x5F, 0x91, 0x6B, 0xEF, 0x64, 0x01, +0x60, 0x02, 0x81, 0x5F, 0x12, 0x70, 0x9E, 0x81, +0x5F, 0x90, 0x85, 0xC8, 0xE0, 0xB4, 0x0E, 0x08, +0x91, 0x6B, 0xBF, 0x01, 0x03, 0x12, 0x74, 0x93, +0x90, 0x85, 0xC8, 0xE0, 0xB4, 0x06, 0x03, 0x12, +0x73, 0x8E, 0x90, 0x85, 0xC8, 0xE0, 0xB4, 0x0C, +0x08, 0x91, 0x6B, 0xBF, 0x01, 0x03, 0x12, 0x70, +0x9E, 0x90, 0x85, 0xC8, 0xE0, 0x64, 0x04, 0x70, +0x5E, 0x12, 0xCD, 0xF1, 0xEF, 0x64, 0x01, 0x70, +0x56, 0x12, 0x77, 0xFE, 0x80, 0x51, 0x90, 0x85, +0xC8, 0xE0, 0xB4, 0x0E, 0x08, 0x91, 0x6B, 0xBF, +0x01, 0x03, 0x12, 0x74, 0x93, 0x90, 0x85, 0xC8, +0xE0, 0xB4, 0x06, 0x03, 0x12, 0x73, 0x8E, 0x90, +0x85, 0xC8, 0xE0, 0xB4, 0x0C, 0x08, 0x91, 0x6B, +0xBF, 0x01, 0x03, 0x12, 0x70, 0x9E, 0x90, 0x85, +0xC8, 0xE0, 0x70, 0x05, 0x7F, 0x01, 0x12, 0x79, +0x80, 0x90, 0x85, 0xC8, 0xE0, 0xB4, 0x04, 0x17, +0x12, 0x79, 0xF3, 0x80, 0x12, 0x90, 0x85, 0xC8, +0xE0, 0xB4, 0x0C, 0x0B, 0x12, 0xC3, 0x4E, 0x54, +0x3F, 0x30, 0xE0, 0x03, 0x12, 0x7A, 0x8A, 0x90, +0x85, 0xC8, 0x12, 0xD1, 0x6E, 0xF0, 0xD0, 0xD0, +0x92, 0xAF, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, +0xC0, 0xD0, 0x12, 0x7A, 0x29, 0xEF, 0x64, 0x01, +0x60, 0x05, 0x75, 0x0F, 0x01, 0x80, 0x24, 0x90, +0x85, 0xC1, 0xE0, 0x13, 0x13, 0x13, 0x54, 0x1F, +0x30, 0xE0, 0x05, 0x75, 0x0F, 0x02, 0x80, 0x13, +0x90, 0x85, 0xC7, 0xE0, 0xD3, 0x94, 0x04, 0x40, +0x05, 0x75, 0x0F, 0x08, 0x80, 0x05, 0x12, 0xBF, +0x73, 0x80, 0x0E, 0x90, 0x01, 0xB9, 0x74, 0x02, +0xF0, 0x90, 0x01, 0xB8, 0xE5, 0x0F, 0xF0, 0x7F, +0x00, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xD3, 0x10, +0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x8B, 0x5B, 0x8A, +0x5C, 0x89, 0x5D, 0x90, 0x05, 0x27, 0xE0, 0xF5, +0x5E, 0x8B, 0x1B, 0x8A, 0x1C, 0x89, 0x1D, 0x75, +0x1E, 0x01, 0x7B, 0x01, 0x7A, 0x85, 0x79, 0xBC, +0x12, 0x6A, 0x21, 0x12, 0x98, 0xD7, 0xFF, 0xC3, +0x13, 0x20, 0xE0, 0x02, 0xA1, 0x6B, 0x90, 0x85, +0xBC, 0xE0, 0x30, 0xE0, 0x6C, 0xD1, 0x69, 0x75, +0x5E, 0x21, 0xD1, 0x79, 0x30, 0xE0, 0x05, 0x12, +0xD1, 0x2B, 0x80, 0x0D, 0xE4, 0x90, 0x85, 0xBD, +0xF0, 0xA3, 0xF0, 0x7D, 0x40, 0xFF, 0x12, 0x7C, +0x41, 0xD1, 0x70, 0x54, 0x1F, 0x30, 0xE0, 0x03, +0x43, 0x5E, 0x12, 0xEF, 0xC4, 0x54, 0x0F, 0x30, +0xE0, 0x03, 0x43, 0x5E, 0x14, 0x90, 0x85, 0xBC, +0xE0, 0xC4, 0x13, 0x54, 0x07, 0x30, 0xE0, 0x03, +0x43, 0x5E, 0x80, 0xF1, 0xE2, 0x20, 0xE0, 0x03, +0x43, 0x5E, 0x40, 0xD1, 0x0D, 0x90, 0x85, 0xBF, +0xE0, 0x70, 0x05, 0x7F, 0x01, 0x12, 0xC9, 0x5E, +0xD1, 0x82, 0x30, 0xE0, 0x04, 0x7F, 0x04, 0x80, +0x0B, 0xD1, 0x8D, 0xEF, 0x60, 0x04, 0x7F, 0x01, +0x80, 0x02, 0x7F, 0x02, 0x12, 0xC9, 0x5E, 0x80, +0x7E, 0xD1, 0x0A, 0x90, 0x85, 0xBF, 0xE0, 0x64, +0x04, 0x60, 0x02, 0xC1, 0x05, 0xFF, 0x12, 0xC9, +0x5E, 0xC1, 0x05, 0x90, 0x85, 0xBC, 0xE0, 0x30, +0xE0, 0x6D, 0xD1, 0x69, 0x43, 0x5E, 0x31, 0xD1, +0x79, 0x30, 0xE0, 0x05, 0x12, 0xD1, 0x2B, 0x80, +0x07, 0x7D, 0x40, 0xE4, 0xFF, 0x12, 0x7C, 0x41, +0xD1, 0x70, 0x54, 0x1F, 0x30, 0xE0, 0x03, 0x43, +0x5E, 0x02, 0xEF, 0xC4, 0x54, 0x0F, 0x30, 0xE0, +0x03, 0x43, 0x5E, 0x04, 0xD1, 0x0D, 0xD1, 0x82, +0x30, 0xE0, 0x0A, 0xF1, 0x6C, 0x60, 0x30, 0xE4, +0xFD, 0x7F, 0x02, 0x80, 0x1E, 0x12, 0xCA, 0xC2, +0x90, 0x85, 0xC0, 0xE0, 0xB4, 0x02, 0x18, 0x12, +0x7A, 0xA2, 0xD1, 0x8D, 0xBF, 0x01, 0x09, 0x90, +0x85, 0xC7, 0xE0, 0xFF, 0x7D, 0x01, 0x80, 0x03, +0xE4, 0xFD, 0xFF, 0x71, 0x0C, 0x80, 0x08, 0x90, +0x85, 0xC8, 0xE0, 0x90, 0x85, 0xC0, 0xF0, 0x90, +0x05, 0x40, 0x74, 0x22, 0xF0, 0x80, 0x26, 0xD1, +0x0A, 0x90, 0x85, 0xC0, 0xE0, 0xB4, 0x02, 0x06, +0x7D, 0x01, 0x7F, 0x04, 0x80, 0x0B, 0x90, 0x85, +0xC0, 0xE0, 0xB4, 0x08, 0x06, 0x7D, 0x01, 0x7F, +0x0C, 0x71, 0x0C, 0xF1, 0xD9, 0x90, 0x85, 0xC7, +0xF1, 0xCC, 0x12, 0xCD, 0x91, 0xD0, 0xD0, 0x92, +0xAF, 0x22, 0x75, 0x5E, 0x01, 0x90, 0x05, 0x27, +0xE5, 0x5E, 0xF0, 0x22, 0x7F, 0x8F, 0x12, 0x7B, +0x51, 0xEF, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, +0xC0, 0xD0, 0x90, 0x95, 0x13, 0xEF, 0xF0, 0xD1, +0x14, 0x30, 0xE6, 0x38, 0x7F, 0x8D, 0x12, 0x7B, +0x51, 0xEF, 0x64, 0x01, 0x70, 0x2E, 0x90, 0x95, +0x14, 0xF0, 0x90, 0x95, 0x14, 0xE0, 0xFD, 0x90, +0x95, 0x13, 0xE0, 0x12, 0x9B, 0x4A, 0xE5, 0x82, +0x2D, 0xF1, 0x36, 0xE0, 0xFB, 0xE4, 0xFF, 0x51, +0xB5, 0x90, 0x95, 0x14, 0xE0, 0x04, 0xF0, 0xE0, +0xC3, 0x94, 0x10, 0x40, 0xDD, 0xD1, 0x14, 0x30, +0xE0, 0x02, 0xF1, 0xD2, 0xD0, 0xD0, 0x92, 0xAF, +0x22, 0x7D, 0x03, 0x7F, 0x02, 0x02, 0x7B, 0xFD, +0x90, 0x85, 0xBC, 0xE0, 0xFF, 0x13, 0x13, 0x13, +0x22, 0x90, 0x85, 0xBC, 0xE0, 0x13, 0x13, 0x54, +0x3F, 0x22, 0x90, 0x85, 0xBC, 0xE0, 0xFF, 0xC4, +0x13, 0x13, 0x54, 0x03, 0x22, 0x90, 0x05, 0x43, +0xE0, 0x7F, 0x00, 0x30, 0xE7, 0x02, 0x7F, 0x01, +0x22, 0xE4, 0xF5, 0x75, 0x90, 0x85, 0xC5, 0xE0, +0x60, 0x6F, 0x12, 0xC4, 0x67, 0x70, 0x6A, 0x12, +0xC7, 0xC0, 0x75, 0x75, 0x01, 0x90, 0x85, 0xBC, +0xE0, 0x30, 0xE0, 0x11, 0x90, 0x85, 0xC0, 0xE0, +0xB4, 0x02, 0x03, 0xE4, 0xF5, 0x75, 0xD1, 0x8D, +0xEF, 0x70, 0x02, 0xF5, 0x75, 0xE5, 0x75, 0x60, +0x48, 0x90, 0x85, 0xC8, 0xE0, 0x20, 0xE2, 0x02, +0x71, 0x08, 0x90, 0x85, 0xC9, 0xE0, 0x44, 0x10, +0xF0, 0x90, 0x85, 0xCE, 0xE0, 0x60, 0x04, 0x64, +0x01, 0x70, 0x17, 0xE4, 0x90, 0x91, 0x6E, 0xF0, +0x90, 0x85, 0xCE, 0xE0, 0xF1, 0x12, 0x90, 0x91, +0x6F, 0x12, 0xC6, 0x20, 0x90, 0x85, 0xCE, 0xE0, +0x80, 0x11, 0xE4, 0x90, 0x91, 0x6E, 0xF0, 0xF1, +0x19, 0xF1, 0x12, 0x90, 0x91, 0x6F, 0x12, 0xC6, +0x20, 0xF1, 0x19, 0xF1, 0x12, 0x90, 0x85, 0xDE, +0xF0, 0x22, 0xFF, 0x90, 0x85, 0xCD, 0xE0, 0x2F, +0x22, 0x90, 0x85, 0xCE, 0xE0, 0x75, 0xF0, 0x03, +0xA4, 0x24, 0xFE, 0x22, 0xF0, 0x74, 0xCC, 0x2D, +0xF5, 0x82, 0xE4, 0x34, 0x8F, 0xF5, 0x83, 0x22, +0x12, 0x05, 0x28, 0xE5, 0x82, 0x29, 0xF5, 0x82, +0xE4, 0x35, 0x83, 0xF5, 0x83, 0x22, 0xAE, 0x07, +0xD1, 0x8D, 0xBF, 0x01, 0x0E, 0xF1, 0xE2, 0x20, +0xE0, 0x09, 0xAF, 0x06, 0x7D, 0x01, 0x71, 0x0C, +0x7F, 0x01, 0x22, 0x7F, 0x00, 0x22, 0xD1, 0x82, +0x30, 0xE0, 0x0A, 0xF1, 0x6C, 0x60, 0x06, 0x7D, +0x01, 0x7F, 0x02, 0x71, 0x0C, 0xF1, 0x6C, 0x60, +0x02, 0xF1, 0x73, 0x22, 0x90, 0x85, 0xC0, 0xE0, +0x64, 0x02, 0x22, 0x90, 0x85, 0xC5, 0xE0, 0x64, +0x02, 0x60, 0x10, 0x12, 0xB7, 0xDC, 0x60, 0x0B, +0x12, 0x7A, 0x29, 0xEF, 0x70, 0x05, 0xFD, 0x7F, +0x0C, 0x71, 0x0C, 0x22, 0x90, 0x85, 0xC5, 0xE0, +0x64, 0x01, 0x70, 0x19, 0x12, 0xB7, 0xDC, 0x60, +0x0C, 0xE4, 0xFD, 0x7F, 0x0C, 0x71, 0x0C, 0x12, +0x98, 0xE0, 0x02, 0x6B, 0x98, 0x90, 0x85, 0xC8, +0xE0, 0x70, 0x02, 0x71, 0x08, 0x22, 0x90, 0x85, +0xC5, 0xE0, 0x70, 0x07, 0x90, 0x85, 0xBC, 0xE0, +0x30, 0xE0, 0x10, 0x90, 0x85, 0xBC, 0xE0, 0x30, +0xE0, 0x07, 0xD1, 0x8D, 0xBF, 0x01, 0x04, 0x80, +0xAA, 0xF1, 0x8C, 0x22, 0xE0, 0xFF, 0x7D, 0x01, +0x61, 0x0C, 0xE4, 0xFD, 0x7F, 0x8D, 0x02, 0x7B, +0x3E, 0x12, 0x7A, 0x29, 0xEF, 0x70, 0x02, 0xF1, +0x8C, 0x22, 0x90, 0x85, 0xBC, 0xE0, 0xC4, 0x13, +0x13, 0x54, 0x03, 0x22, 0x21, 0x97, 0xF9, 0xE4, +0x3A, 0xFA, 0x02, 0x02, 0xF6, 0x75, 0xF0, 0x08, +0xA4, 0x24, 0x00, 0xF5, 0x82, 0xE4, 0x34, 0x82, +0x22, 0xF1, 0xAE, 0xFF, 0x54, 0x0F, 0xF5, 0x5E, +0xEF, 0xC4, 0x54, 0x0F, 0x64, 0x0F, 0x70, 0x3B, +0x90, 0x92, 0x0A, 0xE0, 0x54, 0xFE, 0xFF, 0xF0, +0xE5, 0x5E, 0x54, 0x07, 0x25, 0xE0, 0xFE, 0xEF, +0x54, 0xF1, 0x4E, 0xF0, 0x12, 0x97, 0xE7, 0xC4, +0x13, 0x54, 0x07, 0x90, 0x92, 0xBB, 0x20, 0xE0, +0x05, 0x74, 0x06, 0xF0, 0x80, 0x03, 0x74, 0x01, +0xF0, 0xF1, 0x8A, 0xAF, 0x5E, 0x31, 0x03, 0xBF, +0x01, 0x05, 0xE4, 0xFD, 0xFF, 0x51, 0x52, 0x7F, +0x02, 0x21, 0x00, 0xE5, 0x5E, 0x75, 0xF0, 0x1B, +0xA4, 0x24, 0x37, 0xF9, 0x74, 0x92, 0x35, 0xF0, +0xFA, 0x7B, 0x01, 0xC0, 0x02, 0xC0, 0x01, 0xE5, +0x5D, 0x24, 0x01, 0xF9, 0xE4, 0x35, 0x5C, 0x85, +0x5B, 0x1B, 0xF5, 0x1C, 0x89, 0x1D, 0x75, 0x1E, +0x04, 0xD0, 0x01, 0xD0, 0x02, 0x12, 0x6A, 0x21, +0xE5, 0x5E, 0x12, 0x8F, 0xA6, 0x54, 0xF7, 0xF0, +0x12, 0x98, 0xD7, 0xC4, 0x54, 0x0F, 0x14, 0x65, +0x5E, 0x70, 0x77, 0x90, 0x85, 0xC5, 0xE0, 0x70, +0x07, 0x90, 0x85, 0xBC, 0xE0, 0x30, 0xE0, 0x04, +0x7F, 0x05, 0x80, 0x64, 0x12, 0x98, 0xD7, 0xC4, +0x54, 0x0F, 0x90, 0x92, 0x0B, 0xF0, 0x12, 0x90, +0x39, 0xFC, 0x54, 0x0F, 0xC4, 0x54, 0xF0, 0xFE, +0x90, 0x92, 0x0A, 0xE0, 0x54, 0x0F, 0x4E, 0xF0, +0xEC, 0x54, 0x60, 0xC4, 0x54, 0x0F, 0xFF, 0x90, +0x92, 0x89, 0xE0, 0x54, 0xF9, 0x4F, 0xF0, 0x90, +0x92, 0x0A, 0xE0, 0x54, 0xF1, 0xF0, 0x90, 0x05, +0x58, 0x74, 0x02, 0xF0, 0x90, 0x92, 0xB1, 0xE0, +0x90, 0x92, 0xB5, 0x30, 0xE0, 0x0B, 0xE0, 0x54, +0xFE, 0xF0, 0x54, 0xC1, 0x44, 0x02, 0xF0, 0x80, +0x07, 0xE0, 0x44, 0x01, 0xF0, 0x54, 0xC1, 0xF0, +0x90, 0x92, 0xB5, 0xE0, 0x54, 0xBF, 0xF0, 0x90, +0x92, 0x0A, 0xE0, 0x44, 0x01, 0xF0, 0x7F, 0x03, +0x51, 0xF7, 0x22, 0x8F, 0x5F, 0x90, 0x05, 0x22, +0xE0, 0x90, 0x93, 0xC3, 0xF0, 0x12, 0x96, 0xE6, +0xEF, 0x64, 0x01, 0x70, 0x35, 0xE5, 0x5F, 0x51, +0xD4, 0xE0, 0xFC, 0xE5, 0x5F, 0x12, 0xD0, 0x4C, +0xAF, 0x04, 0x31, 0x59, 0xE5, 0x5F, 0x12, 0x8B, +0xB0, 0xE5, 0x5F, 0x12, 0x8F, 0xA6, 0x54, 0x07, +0xFF, 0x60, 0x03, 0xBF, 0x02, 0x0B, 0xE5, 0x5F, +0x12, 0x97, 0xD9, 0x51, 0xF0, 0xFD, 0x12, 0x95, +0x92, 0xAD, 0x5F, 0x7F, 0x01, 0x51, 0x52, 0x7F, +0x01, 0x22, 0x90, 0x93, 0xC3, 0xE0, 0xFD, 0x7B, +0x49, 0xE4, 0xFF, 0x12, 0x95, 0x87, 0x7F, 0x00, +0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, +0x90, 0x95, 0x01, 0xEF, 0xF0, 0xED, 0x64, 0x01, +0x70, 0x2E, 0xEB, 0xB4, 0x01, 0x07, 0xE0, 0x24, +0x02, 0xF5, 0x0E, 0x80, 0x08, 0x90, 0x95, 0x01, +0xE0, 0x24, 0xFE, 0xF5, 0x0E, 0x90, 0x94, 0xC1, +0x12, 0x04, 0xF7, 0x00, 0x00, 0x00, 0xFF, 0xAF, +0x0E, 0x31, 0xC3, 0x51, 0x4A, 0x12, 0x04, 0xF7, +0x00, 0x00, 0x00, 0xFF, 0xAF, 0x0E, 0x80, 0x20, +0x90, 0x94, 0xC1, 0x12, 0x04, 0xF7, 0x00, 0x00, +0x00, 0xFF, 0x90, 0x95, 0x01, 0x12, 0x8D, 0xA5, +0x31, 0xC7, 0x51, 0x4A, 0x12, 0x04, 0xF7, 0x00, +0x00, 0x00, 0xFF, 0x90, 0x95, 0x01, 0xE0, 0xFF, +0x31, 0xC3, 0x7F, 0x01, 0x31, 0xD2, 0xD0, 0xD0, +0x92, 0xAF, 0x22, 0xE4, 0xFC, 0xFD, 0xFE, 0x90, +0x94, 0xC5, 0x12, 0x04, 0xEB, 0x7D, 0x18, 0x7C, +0x00, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, +0xD0, 0x90, 0x94, 0xBF, 0xEC, 0xF0, 0xA3, 0xED, +0xF0, 0x90, 0x94, 0xBE, 0xEF, 0xF0, 0xA3, 0xA3, +0xE0, 0xFD, 0x12, 0x7B, 0xE0, 0x90, 0x94, 0xC9, +0x12, 0x04, 0xEB, 0x90, 0x94, 0xC1, 0x12, 0x87, +0x2D, 0x12, 0x04, 0xA7, 0x90, 0x94, 0xC9, 0x12, +0x8F, 0x5E, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, +0xC0, 0x07, 0x90, 0x94, 0xC1, 0x12, 0x87, 0x2D, +0x90, 0x94, 0xC5, 0x12, 0x8F, 0x5E, 0xD0, 0x03, +0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x87, +0x20, 0x90, 0x94, 0xCD, 0x12, 0x04, 0xEB, 0x90, +0x94, 0xBF, 0xA3, 0xE0, 0xFD, 0xC0, 0x05, 0x90, +0x94, 0xCD, 0x12, 0x87, 0x2D, 0x90, 0x8D, 0x9D, +0x12, 0x04, 0xEB, 0x90, 0x94, 0xBE, 0xE0, 0xFF, +0xD0, 0x05, 0x12, 0x78, 0xDD, 0xD0, 0xD0, 0x92, +0xAF, 0x22, 0xE4, 0xFF, 0x31, 0xD2, 0x90, 0x94, +0xC1, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, +0xD0, 0x90, 0x94, 0x82, 0xED, 0xF0, 0x90, 0x94, +0x81, 0xEF, 0xF0, 0x64, 0x02, 0x70, 0x24, 0x90, +0x05, 0x22, 0xE0, 0x90, 0x94, 0x83, 0xF0, 0x7B, +0x4A, 0x7D, 0x6F, 0x12, 0x96, 0xEA, 0xBF, 0x01, +0x07, 0x90, 0x04, 0xD4, 0x74, 0xFF, 0x80, 0x48, +0x90, 0x94, 0x83, 0xE0, 0xFD, 0x7B, 0x46, 0x31, +0x51, 0x80, 0x42, 0x90, 0x94, 0x81, 0xE0, 0x64, +0x01, 0x70, 0x31, 0x12, 0x95, 0x83, 0x90, 0x94, +0x82, 0xE0, 0xFF, 0x75, 0xF0, 0x1B, 0xA4, 0x24, +0x3C, 0xF5, 0x82, 0xE4, 0x34, 0x92, 0xF5, 0x83, +0xE0, 0xF4, 0x90, 0x04, 0xD4, 0xF0, 0xEF, 0x75, +0xF0, 0x1B, 0xA4, 0x24, 0x3D, 0xF5, 0x82, 0xE4, +0x34, 0x92, 0xF5, 0x83, 0xE0, 0xF4, 0x90, 0x04, +0xD5, 0xF0, 0x80, 0x07, 0x90, 0x04, 0xD4, 0xE4, +0xF0, 0xA3, 0xF0, 0x7F, 0x01, 0xD0, 0xD0, 0x92, +0xAF, 0x22, 0xE5, 0x77, 0x75, 0xF0, 0x1B, 0xA4, +0x24, 0x37, 0xF5, 0x82, 0xE4, 0x34, 0x92, 0xF5, +0x83, 0x22, 0xEF, 0x75, 0xF0, 0x0E, 0xA4, 0x24, +0x19, 0xF5, 0x82, 0xE4, 0x34, 0x92, 0xF5, 0x83, +0xE0, 0xFF, 0x7E, 0x00, 0xE4, 0xFB, 0x22, 0xD3, +0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0xAD, 0x07, +0x90, 0x05, 0x63, 0xE0, 0xFE, 0x90, 0x05, 0x62, +0xE0, 0x7A, 0x00, 0x24, 0x00, 0xFF, 0xEA, 0x3E, +0x90, 0x94, 0x90, 0xF0, 0xA3, 0xEF, 0xF0, 0x90, +0x05, 0x61, 0xE0, 0xFE, 0x90, 0x05, 0x60, 0xE0, +0x24, 0x00, 0xFF, 0xEA, 0x3E, 0xFE, 0xED, 0xB4, +0x08, 0x0A, 0x90, 0x05, 0x58, 0xE0, 0xFC, 0x2F, +0xFF, 0xEA, 0x3E, 0xFE, 0x90, 0x94, 0x81, 0x74, +0x17, 0xF0, 0x90, 0x94, 0x8F, 0x74, 0x06, 0xF0, +0x90, 0x94, 0x83, 0xED, 0xF0, 0x90, 0x92, 0x0A, +0xE0, 0xFD, 0xC3, 0x13, 0x54, 0x07, 0x51, 0xD4, +0xE0, 0x90, 0x94, 0x84, 0xF0, 0xA3, 0xEF, 0xF0, +0xEE, 0xA3, 0xF0, 0x90, 0x94, 0x90, 0xE0, 0xFE, +0xA3, 0xE0, 0x90, 0x94, 0x87, 0xF0, 0xEE, 0xA3, +0xF0, 0x7B, 0x01, 0x7A, 0x94, 0x79, 0x81, 0x12, +0x88, 0x13, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90, +0x92, 0x0A, 0xE0, 0xFF, 0x20, 0xE0, 0x02, 0xC1, +0x4D, 0x90, 0x92, 0xB5, 0xE0, 0xFE, 0x20, 0xE0, +0x02, 0x81, 0xBB, 0x90, 0x92, 0xB3, 0xE0, 0xFD, +0x90, 0x92, 0xB6, 0xE0, 0xD3, 0x9D, 0x50, 0x02, +0x81, 0xBB, 0x90, 0x05, 0x58, 0xE0, 0x90, 0x94, +0x5D, 0xF0, 0xEF, 0x12, 0x8F, 0xA3, 0x54, 0x07, +0xFF, 0x64, 0x02, 0x60, 0x03, 0xEF, 0x70, 0x23, +0xEE, 0xC4, 0x13, 0x13, 0x54, 0x03, 0x20, 0xE0, +0x1A, 0x90, 0x92, 0xB5, 0xE0, 0x44, 0x40, 0xF1, +0x91, 0x90, 0x94, 0x5D, 0xE0, 0xFF, 0x90, 0x92, +0xB2, 0xE0, 0x2F, 0x24, 0xFD, 0x90, 0x91, 0x6F, +0x12, 0xC6, 0x20, 0x12, 0x8D, 0x8C, 0x12, 0x87, +0x20, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, +0x07, 0x90, 0x05, 0x62, 0x12, 0x8D, 0xA5, 0x78, +0x10, 0x12, 0x04, 0xD8, 0xD0, 0x03, 0xD0, 0x02, +0xD0, 0x01, 0xD0, 0x00, 0x12, 0x87, 0x20, 0xC0, +0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0xA3, +0x12, 0x8D, 0xA5, 0x78, 0x18, 0x12, 0x04, 0xD8, +0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, +0x12, 0x87, 0x20, 0x90, 0x94, 0x51, 0x12, 0x04, +0xEB, 0x90, 0x05, 0x65, 0x12, 0x8D, 0xA5, 0xD1, +0x80, 0x90, 0x05, 0x64, 0x12, 0x8D, 0xA5, 0x12, +0x87, 0x20, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, +0xC0, 0x07, 0x90, 0x05, 0x66, 0x12, 0x8D, 0xA5, +0x78, 0x10, 0x12, 0x04, 0xD8, 0xD0, 0x03, 0xD0, +0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x87, 0x20, +0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, +0xA3, 0x12, 0x8D, 0xA5, 0x78, 0x18, 0x12, 0x04, +0xD8, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, +0x00, 0x12, 0x87, 0x20, 0xD1, 0x7A, 0x90, 0x92, +0xB2, 0xE0, 0xFB, 0xE4, 0xFA, 0xF9, 0xF8, 0x90, +0x94, 0x5D, 0x12, 0x8D, 0xA5, 0x12, 0x86, 0xA9, +0xE4, 0xFB, 0x7A, 0x04, 0x12, 0x86, 0xC4, 0xD1, +0x67, 0x12, 0x86, 0xA9, 0x90, 0x94, 0x59, 0xD1, +0x5E, 0x90, 0x94, 0x59, 0xF1, 0x9F, 0x50, 0x04, +0xD1, 0x50, 0xD1, 0x6D, 0xD1, 0x50, 0xF1, 0xB7, +0xD1, 0x4E, 0xF1, 0xC0, 0xD1, 0x4E, 0xF1, 0xC9, +0xD1, 0x4E, 0x90, 0x05, 0x88, 0xD1, 0x56, 0xF1, +0xD2, 0xD1, 0x56, 0xF1, 0xDB, 0xD1, 0x56, 0xF1, +0xE4, 0xD1, 0x56, 0x12, 0xD1, 0x1F, 0xE4, 0x90, +0x92, 0xB6, 0xF0, 0x90, 0x92, 0xB1, 0xE0, 0x20, +0xE0, 0x02, 0xC1, 0x4D, 0x90, 0x92, 0xB5, 0xE0, +0xFF, 0xC3, 0x13, 0xFE, 0x54, 0x1F, 0x70, 0x02, +0xC1, 0x4D, 0xEF, 0x54, 0xC1, 0xFF, 0xEE, 0x14, +0x54, 0x1F, 0xFE, 0x25, 0xE0, 0x4F, 0xF0, 0xE0, +0xC3, 0x13, 0x54, 0x1F, 0x60, 0x02, 0xC1, 0x4D, +0x90, 0x05, 0x22, 0xE0, 0x44, 0x40, 0xFD, 0x7B, +0x58, 0x7F, 0x40, 0x12, 0x95, 0x87, 0x90, 0x05, +0x50, 0xE0, 0x54, 0xF7, 0xF0, 0x90, 0x05, 0x69, +0x12, 0x8D, 0xA5, 0xD1, 0x80, 0x90, 0x05, 0x68, +0x12, 0x8D, 0xA5, 0x12, 0x87, 0x20, 0xC0, 0x04, +0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x05, +0x6A, 0x12, 0x8D, 0xA5, 0x78, 0x10, 0x12, 0x04, +0xD8, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, +0x00, 0x12, 0x87, 0x20, 0xC0, 0x04, 0xC0, 0x05, +0xC0, 0x06, 0xC0, 0x07, 0xA3, 0x12, 0x8D, 0xA5, +0x78, 0x18, 0x12, 0x04, 0xD8, 0xD0, 0x03, 0xD0, +0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x87, 0x20, +0x90, 0x94, 0x51, 0xD1, 0x5E, 0x90, 0x94, 0x59, +0x12, 0x04, 0xEB, 0x90, 0x05, 0x6D, 0x12, 0x8D, +0xA5, 0xD1, 0x80, 0x90, 0x05, 0x6C, 0x12, 0x8D, +0xA5, 0x12, 0x87, 0x20, 0xC0, 0x04, 0xC0, 0x05, +0xC0, 0x06, 0xC0, 0x07, 0x90, 0x05, 0x6E, 0x12, +0x8D, 0xA5, 0x78, 0x10, 0x12, 0x04, 0xD8, 0xD0, +0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, +0x87, 0x20, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, +0xC0, 0x07, 0xA3, 0x12, 0x8D, 0xA5, 0x78, 0x18, +0x12, 0x04, 0xD8, 0xD0, 0x03, 0xD0, 0x02, 0xD0, +0x01, 0xD0, 0x00, 0x12, 0x87, 0x20, 0xD1, 0x7A, +0xD1, 0x67, 0xC0, 0x00, 0xC0, 0x01, 0xC0, 0x02, +0xC0, 0x03, 0x90, 0x92, 0xB1, 0xE0, 0xC3, 0x13, +0x54, 0x7F, 0xFF, 0xE4, 0xFC, 0xFD, 0xFE, 0xF1, +0xA6, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, +0x00, 0x12, 0x86, 0xA9, 0x90, 0x94, 0x51, 0x12, +0x04, 0xEB, 0xD1, 0x58, 0xD1, 0x67, 0xC3, 0x12, +0x04, 0xB4, 0x50, 0x04, 0xD1, 0x50, 0xD1, 0x6D, +0xD1, 0x50, 0x78, 0x18, 0x12, 0x04, 0xC5, 0x90, +0x05, 0x67, 0xD1, 0x4E, 0x78, 0x10, 0x12, 0x04, +0xC5, 0x90, 0x05, 0x66, 0xD1, 0x4E, 0x78, 0x08, +0x12, 0x04, 0xC5, 0x90, 0x05, 0x65, 0xD1, 0x4E, +0x90, 0x05, 0x64, 0xEF, 0xF0, 0xD1, 0x61, 0x78, +0x18, 0x12, 0x04, 0xC5, 0x90, 0x05, 0x63, 0xEF, +0xF0, 0xD1, 0x61, 0x78, 0x10, 0x12, 0x04, 0xC5, +0x90, 0x05, 0x62, 0xEF, 0xF0, 0xD1, 0x61, 0x78, +0x08, 0x12, 0x04, 0xC5, 0x90, 0x05, 0x61, 0xEF, +0xF0, 0xD1, 0x61, 0x90, 0x05, 0x60, 0xEF, 0xF0, +0x90, 0x05, 0x50, 0xE0, 0x44, 0x08, 0xF0, 0x90, +0x05, 0x22, 0xE0, 0x54, 0xBF, 0xFD, 0x7B, 0x59, +0x7F, 0x40, 0x12, 0x95, 0x87, 0x7F, 0x08, 0x51, +0xF7, 0x90, 0x92, 0xB5, 0xE0, 0x54, 0xC1, 0x44, +0x28, 0xF0, 0x44, 0x01, 0xF0, 0x22, 0xEF, 0xF0, +0x90, 0x94, 0x55, 0x02, 0x87, 0x2D, 0xEF, 0xF0, +0x90, 0x94, 0x59, 0x02, 0x87, 0x2D, 0x12, 0x04, +0xEB, 0x90, 0x94, 0x51, 0x02, 0x87, 0x2D, 0x90, +0x94, 0x51, 0x02, 0x87, 0x39, 0xEF, 0x24, 0x01, +0xFF, 0xE4, 0x3E, 0xFE, 0xE4, 0x3D, 0xFD, 0xE4, +0x3C, 0xFC, 0x90, 0x94, 0x55, 0x02, 0x04, 0xEB, +0x78, 0x08, 0x12, 0x04, 0xD8, 0xA8, 0x04, 0xA9, +0x05, 0xAA, 0x06, 0xAB, 0x07, 0x22, 0x90, 0x85, +0xBC, 0xE0, 0x30, 0xE0, 0x10, 0xA3, 0x74, 0x01, +0xF0, 0x90, 0x85, 0xBC, 0xE0, 0xFF, 0xC3, 0x13, +0x30, 0xE0, 0x02, 0xD1, 0xAE, 0x12, 0xA6, 0x99, +0xE4, 0xFF, 0xD1, 0xC9, 0x61, 0x77, 0xD3, 0x10, +0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x12, 0xA6, 0x8D, +0xBF, 0x01, 0x04, 0x7F, 0x01, 0x80, 0x02, 0x7F, +0x02, 0x12, 0xC9, 0x5E, 0xD0, 0xD0, 0x92, 0xAF, +0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, +0x90, 0x92, 0xC9, 0xE0, 0xFE, 0x13, 0x13, 0x54, +0x3F, 0x30, 0xE0, 0x1F, 0x90, 0x94, 0xE3, 0x74, +0x1E, 0xF0, 0x90, 0x94, 0xF1, 0x74, 0x01, 0xF0, +0x90, 0x94, 0xE5, 0xEF, 0xF0, 0x7B, 0x01, 0x7A, +0x94, 0x79, 0xE3, 0x12, 0x5E, 0x10, 0x7F, 0x04, +0x12, 0xB6, 0x62, 0xD0, 0xD0, 0x92, 0xAF, 0x22, +0x12, 0xC5, 0x8A, 0xF1, 0x7A, 0x7F, 0x01, 0xD1, +0xC9, 0x90, 0x92, 0x04, 0xE0, 0x30, 0xE0, 0x14, +0xF1, 0x81, 0x90, 0x92, 0x07, 0xE0, 0x60, 0x05, +0x14, 0xF0, 0x02, 0x7A, 0x8A, 0x12, 0xB1, 0x58, +0xE4, 0xFF, 0xF1, 0x25, 0x22, 0xD3, 0x10, 0xAF, +0x01, 0xC3, 0xC0, 0xD0, 0xEF, 0x64, 0x01, 0x70, +0x1A, 0xF1, 0x72, 0x60, 0x09, 0xF1, 0x6B, 0x12, +0x7B, 0xFD, 0xF1, 0x81, 0x80, 0x08, 0xF1, 0x6B, +0x12, 0x7B, 0xBF, 0x12, 0xB7, 0x2F, 0x12, 0x7A, +0x8A, 0x80, 0x17, 0xF1, 0x72, 0x60, 0x07, 0xF1, +0x6B, 0x12, 0x7B, 0xFD, 0x80, 0x05, 0xF1, 0x6B, +0x12, 0x7B, 0xBF, 0xF1, 0x7A, 0xF1, 0x98, 0x12, +0x7A, 0xB9, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xF0, +0x90, 0x01, 0x3F, 0x74, 0x10, 0xF0, 0xFD, 0x7F, +0x03, 0x22, 0x90, 0x92, 0x06, 0xE0, 0x90, 0x01, +0x3F, 0x22, 0x7D, 0x02, 0x7F, 0x02, 0x02, 0x7C, +0xA9, 0x90, 0x92, 0x06, 0xE0, 0x90, 0x05, 0x73, +0xF0, 0x22, 0x7D, 0x20, 0xE4, 0xFF, 0x02, 0x7B, +0xBF, 0xF0, 0xE4, 0x90, 0x91, 0x6E, 0xF0, 0x22, +0x7D, 0x01, 0x7F, 0x02, 0x02, 0x7C, 0xA9, 0x12, +0x87, 0x39, 0xD3, 0x02, 0x04, 0xB4, 0xFB, 0x7A, +0x04, 0xF9, 0xF8, 0x02, 0x86, 0xC4, 0x8B, 0x5B, +0x8A, 0x5C, 0x89, 0x5D, 0x02, 0x02, 0xF6, 0x78, +0x18, 0x12, 0x04, 0xC5, 0x90, 0x05, 0x8B, 0x22, +0x78, 0x10, 0x12, 0x04, 0xC5, 0x90, 0x05, 0x8A, +0x22, 0x78, 0x08, 0x12, 0x04, 0xC5, 0x90, 0x05, +0x89, 0x22, 0x78, 0x18, 0x12, 0x04, 0xC5, 0x90, +0x05, 0x87, 0x22, 0x78, 0x10, 0x12, 0x04, 0xC5, +0x90, 0x05, 0x86, 0x22, 0x78, 0x08, 0x12, 0x04, +0xC5, 0x90, 0x05, 0x85, 0x22, 0xF1, 0xAE, 0xFF, +0x54, 0x01, 0xFE, 0x90, 0x92, 0xB1, 0x12, 0xB1, +0x50, 0x54, 0xFE, 0xFF, 0xEE, 0x54, 0x01, 0x4F, +0xF0, 0x12, 0x8F, 0x73, 0x90, 0x92, 0xB2, 0x12, +0x8F, 0xF2, 0x90, 0x92, 0xB3, 0xF0, 0xE4, 0xA3, +0xF0, 0x90, 0x92, 0xB3, 0xE0, 0xFF, 0xB4, 0x64, +0x05, 0x74, 0x01, 0xF0, 0x80, 0x0A, 0xEF, 0xB4, +0x96, 0x06, 0x90, 0x92, 0xB3, 0x74, 0x03, 0xF0, +0x90, 0x92, 0xB3, 0xE0, 0x04, 0x90, 0x92, 0xB6, +0xF0, 0x22, 0x12, 0x02, 0xF6, 0xFF, 0x90, 0x92, +0x03, 0xF0, 0xBF, 0x01, 0x07, 0x11, 0x45, 0xE4, +0x90, 0x92, 0x03, 0xF0, 0x22, 0x7B, 0x01, 0x7A, +0x93, 0x79, 0xC3, 0x7F, 0xEF, 0x7E, 0x00, 0x12, +0x64, 0x37, 0xBF, 0x01, 0x06, 0x90, 0x93, 0xC3, +0xE0, 0xA3, 0xF0, 0x7B, 0x01, 0x7A, 0x93, 0x79, +0xC3, 0x7F, 0xEE, 0x7E, 0x00, 0x12, 0x64, 0x37, +0xBF, 0x01, 0x08, 0x90, 0x93, 0xC3, 0xE0, 0x90, +0x93, 0xC5, 0xF0, 0x7B, 0x01, 0x7A, 0x93, 0x79, +0xC3, 0x7F, 0xED, 0x7E, 0x00, 0x12, 0x64, 0x37, +0xBF, 0x01, 0x08, 0x90, 0x93, 0xC3, 0xE0, 0x90, +0x93, 0xC6, 0xF0, 0x7B, 0x01, 0x7A, 0x93, 0x79, +0xC3, 0x7F, 0xEC, 0x7E, 0x00, 0x12, 0x64, 0x37, +0xBF, 0x01, 0x08, 0x90, 0x93, 0xC3, 0xE0, 0x90, +0x93, 0xC7, 0xF0, 0x7B, 0x01, 0x7A, 0x93, 0x79, +0xC3, 0x7F, 0xEB, 0x7E, 0x00, 0x12, 0x64, 0x37, +0xBF, 0x01, 0x08, 0x90, 0x93, 0xC3, 0xE0, 0x90, +0x93, 0xC8, 0xF0, 0x90, 0x93, 0xC4, 0xE0, 0xFF, +0xA3, 0xE0, 0xFD, 0xA3, 0xE0, 0xFB, 0xA3, 0xE0, +0x90, 0x93, 0xCC, 0xF0, 0x90, 0x93, 0xC8, 0xE0, +0x90, 0x93, 0xCD, 0xF0, 0x90, 0x93, 0xCE, 0x74, +0x12, 0xF0, 0x90, 0x93, 0xDC, 0x74, 0x05, 0xF0, +0x90, 0x93, 0xD0, 0x31, 0x03, 0x90, 0x93, 0xCC, +0xE0, 0x90, 0x93, 0xD3, 0xF0, 0x90, 0x93, 0xCD, +0xE0, 0x90, 0x93, 0xD4, 0xF0, 0x7B, 0x01, 0x7A, +0x93, 0x79, 0xCE, 0x12, 0x5E, 0x10, 0x7F, 0x04, +0x02, 0x88, 0x18, 0xEF, 0xF0, 0xA3, 0xED, 0xF0, +0xA3, 0xEB, 0xF0, 0x22, 0x12, 0x02, 0xF6, 0x54, +0x01, 0xFF, 0x90, 0x92, 0xC8, 0xE0, 0x54, 0xFE, +0x4F, 0xF0, 0x22, 0x12, 0x02, 0xF6, 0x90, 0x86, +0x71, 0xF0, 0x22, 0x12, 0x02, 0xF6, 0xFF, 0x54, +0x01, 0xFE, 0x90, 0x92, 0x04, 0x31, 0x50, 0x54, +0x02, 0xFF, 0xEE, 0x54, 0xFD, 0x4F, 0xF0, 0x12, +0x8F, 0x73, 0x90, 0x92, 0x05, 0x12, 0x8F, 0xF2, +0x90, 0x92, 0x06, 0xF0, 0x31, 0x58, 0x90, 0x92, +0x04, 0xE0, 0x54, 0x01, 0xFF, 0x02, 0xAF, 0x25, +0xE0, 0x54, 0xFE, 0x4E, 0xFE, 0xF0, 0xEF, 0x22, +0x90, 0x92, 0x05, 0xE0, 0x14, 0x90, 0x92, 0x07, +0xF0, 0x22, 0x90, 0x01, 0xCC, 0xE0, 0x54, 0x0F, +0x90, 0x93, 0xBD, 0xF0, 0x90, 0x93, 0xBD, 0xE0, +0xFD, 0x70, 0x02, 0x41, 0x5F, 0x90, 0x85, 0x1D, +0xE0, 0xFF, 0x70, 0x06, 0xA3, 0xE0, 0x64, 0x09, +0x60, 0x0A, 0xEF, 0x14, 0xFF, 0x90, 0x85, 0x1E, +0xE0, 0xB5, 0x07, 0x04, 0x7F, 0x01, 0x80, 0x02, +0x7F, 0x00, 0xEF, 0x60, 0x08, 0x90, 0x01, 0xC1, +0xE0, 0x44, 0x01, 0xF0, 0x22, 0x90, 0x95, 0x11, +0xE0, 0x51, 0x92, 0x80, 0x05, 0xC3, 0x33, 0xCE, +0x33, 0xCE, 0xD8, 0xF9, 0xFF, 0xEF, 0x5D, 0x70, +0x02, 0x41, 0x42, 0xE4, 0x90, 0x93, 0xBE, 0xF0, +0x90, 0x93, 0xBE, 0xE0, 0xF9, 0xC3, 0x94, 0x04, +0x50, 0x36, 0x51, 0x61, 0xA4, 0xFF, 0xE9, 0xFD, +0x7C, 0x00, 0x2F, 0xFF, 0xEC, 0x35, 0xF0, 0xFE, +0x74, 0xD0, 0x51, 0x69, 0x90, 0x84, 0xCD, 0x12, +0xA7, 0x30, 0xEF, 0x51, 0x60, 0xA4, 0x2D, 0xFF, +0xEC, 0x35, 0xF0, 0xFE, 0x74, 0xF0, 0x51, 0x69, +0x90, 0x84, 0xD1, 0x12, 0xA7, 0x30, 0xEF, 0xF0, +0x90, 0x93, 0xBE, 0xE0, 0x04, 0xF0, 0x80, 0xC0, +0x90, 0x93, 0xBD, 0xE0, 0xFF, 0x90, 0x95, 0x11, +0x51, 0x81, 0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, +0xF4, 0x5F, 0x90, 0x93, 0xBD, 0xF0, 0x90, 0x95, +0x11, 0xE0, 0xFF, 0x74, 0x01, 0xA8, 0x07, 0x08, +0x80, 0x02, 0xC3, 0x33, 0xD8, 0xFC, 0x90, 0x01, +0xCC, 0xF0, 0x90, 0x95, 0x11, 0xE0, 0x04, 0xF0, +0xE0, 0x54, 0x03, 0xF0, 0x90, 0x85, 0x1E, 0x51, +0x89, 0xB4, 0x0A, 0x02, 0x7F, 0x01, 0xEF, 0x70, +0x02, 0x21, 0x6C, 0xE4, 0x90, 0x85, 0x1E, 0xF0, +0x21, 0x6C, 0x90, 0x01, 0xC0, 0xE0, 0x44, 0x02, +0xF0, 0x90, 0x95, 0x11, 0xE0, 0x44, 0x80, 0x90, +0x00, 0x8A, 0x51, 0x60, 0x90, 0x01, 0xD0, 0x12, +0x05, 0x28, 0xE0, 0x90, 0x01, 0xC3, 0xF0, 0x22, +0xF0, 0x90, 0x95, 0x11, 0xE0, 0x75, 0xF0, 0x04, +0x22, 0x2F, 0xF5, 0x82, 0x74, 0x01, 0x3E, 0xF5, +0x83, 0xE0, 0xFF, 0x90, 0x85, 0x1E, 0xE0, 0x75, +0xF0, 0x08, 0x22, 0x75, 0xF0, 0x03, 0x12, 0x05, +0x28, 0xE0, 0xFE, 0x74, 0x01, 0xA8, 0x06, 0x08, +0x22, 0xE0, 0x04, 0xF0, 0xE0, 0x7F, 0x00, 0x22, +0x54, 0x07, 0xFF, 0x74, 0x01, 0x7E, 0x00, 0xA8, +0x07, 0x08, 0x22, 0xE4, 0xF5, 0x75, 0x90, 0x85, +0xBB, 0xE0, 0xFF, 0xE5, 0x75, 0xC3, 0x9F, 0x50, +0x65, 0xAF, 0x75, 0x12, 0x77, 0x39, 0xEF, 0x60, +0x59, 0xE5, 0x75, 0x13, 0x13, 0x13, 0x54, 0x1F, +0xFF, 0xE5, 0x75, 0x54, 0x07, 0xFE, 0x74, 0x75, +0x2F, 0x71, 0x11, 0xAF, 0x06, 0x51, 0x93, 0x80, +0x05, 0xC3, 0x33, 0xCE, 0x33, 0xCE, 0xD8, 0xF9, +0xFF, 0xEF, 0x5D, 0x60, 0x35, 0xE5, 0x75, 0xC4, +0x54, 0xF0, 0x24, 0x01, 0xF5, 0x82, 0xE4, 0x34, +0x81, 0xF5, 0x83, 0xE0, 0x20, 0xE7, 0x02, 0x80, +0x13, 0xE5, 0x75, 0xC4, 0x54, 0xF0, 0x24, 0x02, +0xF5, 0x82, 0xE4, 0x34, 0x81, 0xF5, 0x83, 0xE0, +0xFF, 0x20, 0xE7, 0x09, 0x90, 0x01, 0xC1, 0xE0, +0x44, 0x20, 0xF0, 0x80, 0x05, 0xAD, 0x75, 0x12, +0x9A, 0xC9, 0x05, 0x75, 0x80, 0x90, 0x22, 0x80, +0x8A, 0xF5, 0x82, 0xE4, 0x34, 0x8F, 0xF5, 0x83, +0xE0, 0xFD, 0x22, 0x90, 0x85, 0xB5, 0xE0, 0xFF, +0x70, 0x06, 0xA3, 0xE0, 0x64, 0x09, 0x60, 0x0A, +0xEF, 0x14, 0xFF, 0x90, 0x85, 0xB6, 0xE0, 0xB5, +0x07, 0x04, 0x7F, 0x01, 0x80, 0x02, 0x7F, 0x00, +0xEF, 0x60, 0x08, 0x90, 0x01, 0xC1, 0xE0, 0x44, +0x02, 0xF0, 0x22, 0xC0, 0x01, 0x90, 0x85, 0xB6, +0xE0, 0x75, 0xF0, 0x0F, 0xA4, 0x24, 0x1F, 0xF9, +0x74, 0x85, 0x35, 0xF0, 0xA8, 0x01, 0xFC, 0x7D, +0x01, 0xD0, 0x01, 0x7E, 0x00, 0x7F, 0x0F, 0x12, +0x02, 0xD0, 0x7D, 0xCC, 0x7F, 0xFE, 0x12, 0x7B, +0x3E, 0x90, 0x85, 0xB6, 0x51, 0x89, 0xB4, 0x0A, +0x02, 0x7F, 0x01, 0xEF, 0x60, 0x05, 0xE4, 0x90, +0x85, 0xB6, 0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, +0xC3, 0xC0, 0xD0, 0x90, 0x85, 0x1E, 0xE0, 0xFF, +0x90, 0x85, 0x1D, 0xE0, 0xB5, 0x07, 0x04, 0x7F, +0x01, 0x80, 0x02, 0x7F, 0x00, 0xEF, 0x70, 0x47, +0x90, 0x85, 0x1D, 0xE0, 0xFE, 0x75, 0xF0, 0x08, +0x90, 0x84, 0xCD, 0x12, 0x05, 0x28, 0xE0, 0xFD, +0xEE, 0x75, 0xF0, 0x08, 0xA4, 0x24, 0xCE, 0xF9, +0x74, 0x84, 0x35, 0xF0, 0xFA, 0x7B, 0x01, 0xAF, +0x05, 0x12, 0x8A, 0xD9, 0x90, 0x85, 0x1D, 0x51, +0x89, 0xB4, 0x0A, 0x02, 0x7F, 0x01, 0xEF, 0x60, +0x05, 0xE4, 0x90, 0x85, 0x1D, 0xF0, 0x7D, 0x68, +0x7F, 0xFE, 0x12, 0x7B, 0x3E, 0x12, 0x40, 0xB9, +0x90, 0x84, 0xC1, 0xE0, 0x44, 0x02, 0xF0, 0xD0, +0xD0, 0x92, 0xAF, 0x22, 0xE4, 0xF5, 0x73, 0xEF, +0x14, 0xF5, 0x72, 0xED, 0xFF, 0xE5, 0x72, 0xF5, +0x82, 0x33, 0x95, 0xE0, 0xF5, 0x83, 0xC3, 0xE5, +0x82, 0x9F, 0x74, 0x80, 0xF8, 0x65, 0x83, 0x98, +0x40, 0x53, 0xE5, 0x72, 0x78, 0x03, 0xA2, 0xE7, +0x13, 0xD8, 0xFB, 0xFF, 0x33, 0x95, 0xE0, 0xFE, +0xEB, 0x12, 0xA7, 0xF5, 0xF5, 0x83, 0xE5, 0x82, +0x2F, 0xF5, 0x82, 0xE5, 0x83, 0x3E, 0xF5, 0x83, +0xE0, 0xF5, 0x82, 0x75, 0x83, 0x00, 0xE5, 0x72, +0x51, 0x90, 0x80, 0x05, 0xC3, 0x33, 0xCE, 0x33, +0xCE, 0xD8, 0xF9, 0xFF, 0xEE, 0x55, 0x83, 0xFE, +0xEF, 0x55, 0x82, 0x4E, 0x60, 0x13, 0x85, 0x72, +0x74, 0x05, 0x73, 0x90, 0x94, 0x4B, 0xE0, 0x65, +0x73, 0x60, 0x0A, 0xE5, 0x74, 0xD3, 0x9D, 0x40, +0x04, 0x15, 0x72, 0x80, 0x96, 0xAF, 0x74, 0x22, +0xAA, 0x07, 0xA9, 0x05, 0xEA, 0x12, 0x9B, 0x4A, +0xE0, 0xF5, 0x6E, 0x54, 0x7F, 0xF5, 0x70, 0x75, +0xF0, 0x12, 0xEA, 0x90, 0x89, 0x3D, 0x12, 0x05, +0x28, 0xE0, 0x90, 0x94, 0x47, 0xF0, 0x75, 0xF0, +0x12, 0xEA, 0xB1, 0x17, 0xFF, 0xEA, 0x12, 0x9A, +0xBC, 0xE0, 0x54, 0x03, 0xF5, 0x6F, 0xE5, 0x70, +0x90, 0x83, 0x1D, 0x93, 0xFD, 0xEA, 0x12, 0x9F, +0x5F, 0xE4, 0xF0, 0xA3, 0xED, 0xF0, 0x75, 0xF0, +0x12, 0xEA, 0x12, 0xA1, 0x8F, 0xFE, 0xC4, 0x54, +0x03, 0x90, 0x94, 0x46, 0xF0, 0x74, 0xCC, 0x2A, +0xB1, 0x0F, 0xE5, 0x70, 0xF0, 0x74, 0x4C, 0x2A, +0xB1, 0x1F, 0xE5, 0x6F, 0xF0, 0xE5, 0x70, 0xD3, +0x9F, 0x40, 0x04, 0x8F, 0x70, 0x8F, 0x6E, 0x89, +0x71, 0xE4, 0xFF, 0xEF, 0xC3, 0x95, 0x71, 0x50, +0x33, 0xE5, 0x6E, 0x30, 0xE7, 0x09, 0x85, 0x70, +0x6E, 0x19, 0xE9, 0x70, 0x24, 0x80, 0x25, 0x90, +0x94, 0x47, 0xE0, 0xFD, 0xE5, 0x70, 0xD3, 0x9D, +0x40, 0x0F, 0xAB, 0x02, 0x90, 0x94, 0x4B, 0xE9, +0xF0, 0xAF, 0x70, 0x71, 0xE4, 0x8F, 0x6E, 0x80, +0x0B, 0x90, 0x94, 0x47, 0xE0, 0xF5, 0x6E, 0x80, +0x03, 0x0F, 0x80, 0xC7, 0xAF, 0x02, 0x90, 0x91, +0x0B, 0xE5, 0x6F, 0xF0, 0xE4, 0xFB, 0xAD, 0x6E, +0x02, 0x27, 0x3D, 0x74, 0xCC, 0x25, 0x6E, 0xF5, +0x82, 0xE4, 0x34, 0x90, 0xF5, 0x83, 0x22, 0x90, +0x89, 0x3C, 0x12, 0x05, 0x28, 0xE0, 0x22, 0xF5, +0x82, 0xE4, 0x34, 0x90, 0xF5, 0x83, 0x22, 0xC0, +0xE0, 0xC0, 0xF0, 0xC0, 0x83, 0xC0, 0x82, 0xC0, +0xD0, 0x75, 0xD0, 0x00, 0xC0, 0x00, 0xC0, 0x01, +0xC0, 0x02, 0xC0, 0x03, 0xC0, 0x04, 0xC0, 0x05, +0xC0, 0x06, 0xC0, 0x07, 0x90, 0x01, 0xC4, 0x74, +0x27, 0xF0, 0x74, 0xB5, 0xA3, 0xF0, 0x12, 0x71, +0x90, 0xE5, 0x4C, 0x30, 0xE1, 0x02, 0xB1, 0xDF, +0xE5, 0x4C, 0x30, 0xE4, 0x02, 0xD1, 0x5D, 0xE5, +0x4C, 0x30, 0xE5, 0x03, 0x12, 0xCC, 0xC9, 0xE5, +0x4C, 0x30, 0xE6, 0x03, 0x12, 0xC8, 0xD8, 0xE5, +0x4E, 0x30, 0xE0, 0x03, 0x12, 0xAE, 0x8E, 0xE5, +0x4E, 0x30, 0xE1, 0x02, 0xD1, 0x71, 0xE5, 0x4E, +0x30, 0xE2, 0x03, 0x12, 0xC7, 0x9E, 0xE5, 0x4E, +0x30, 0xE3, 0x02, 0xF1, 0x3D, 0xE5, 0x4E, 0x30, +0xE4, 0x03, 0x12, 0xC1, 0x8D, 0xE5, 0x4E, 0x30, +0xE5, 0x02, 0xF1, 0x71, 0xE5, 0x4E, 0x30, 0xE6, +0x02, 0xF1, 0x51, 0xE5, 0x4F, 0x30, 0xE1, 0x03, +0x12, 0xA7, 0xAE, 0xE5, 0x4F, 0x30, 0xE4, 0x02, +0xF1, 0xE3, 0xE5, 0x4F, 0x30, 0xE5, 0x02, 0x71, +0x0F, 0x74, 0x27, 0x04, 0x90, 0x01, 0xC4, 0xF0, +0x74, 0xB5, 0xA3, 0xF0, 0xD0, 0x07, 0xD0, 0x06, +0xD0, 0x05, 0xD0, 0x04, 0xD0, 0x03, 0xD0, 0x02, +0xD0, 0x01, 0xD0, 0x00, 0xD0, 0xD0, 0xD0, 0x82, +0xD0, 0x83, 0xD0, 0xF0, 0xD0, 0xE0, 0x32, 0xE4, +0xFF, 0x90, 0x94, 0x51, 0xEF, 0xF0, 0x90, 0x04, +0x7E, 0xE0, 0xFF, 0xA3, 0xE0, 0x90, 0x94, 0x61, +0xF0, 0xE0, 0xFE, 0x6F, 0x60, 0x66, 0x90, 0x94, +0x52, 0x74, 0x03, 0xF0, 0x90, 0x94, 0x60, 0x74, +0x08, 0xF0, 0xEE, 0x04, 0x54, 0x0F, 0xFF, 0xE4, +0xFE, 0xEF, 0x75, 0xF0, 0x08, 0xA4, 0x24, 0x00, +0xF5, 0x82, 0xE4, 0x34, 0x80, 0xF5, 0x83, 0xE5, +0x82, 0x2E, 0x12, 0xA7, 0x36, 0xE0, 0xFD, 0x74, +0x54, 0x2E, 0xF5, 0x82, 0xE4, 0x34, 0x94, 0xF5, +0x83, 0xED, 0xF0, 0x0E, 0xEE, 0xB4, 0x08, 0xD9, +0x7B, 0x01, 0x7A, 0x94, 0x79, 0x52, 0x12, 0x5E, +0x10, 0x90, 0x94, 0x61, 0xE0, 0x04, 0x54, 0x0F, +0xFF, 0xF0, 0xBF, 0x0F, 0x02, 0xE4, 0xF0, 0x90, +0x94, 0x61, 0xE0, 0x90, 0x04, 0x7F, 0xF0, 0x90, +0x94, 0x51, 0xE0, 0x7F, 0x04, 0x70, 0x02, 0x80, +0x09, 0x12, 0x88, 0x18, 0x22, 0x12, 0x40, 0xB9, +0x7F, 0x02, 0x8F, 0x0D, 0x7F, 0x02, 0x12, 0x86, +0x27, 0x90, 0x84, 0xC1, 0xE0, 0x45, 0x0D, 0xF0, +0x22, 0x90, 0x85, 0xBC, 0xE0, 0x30, 0xE0, 0x06, +0x90, 0x85, 0xBE, 0x74, 0x01, 0xF0, 0x90, 0x85, +0xC5, 0xE0, 0x70, 0x02, 0xE1, 0x1A, 0x90, 0x85, +0xDC, 0xE0, 0x04, 0xF0, 0x12, 0x8D, 0x8C, 0x12, +0x87, 0x20, 0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, +0xC0, 0x07, 0x90, 0x05, 0x62, 0x12, 0x8D, 0xA5, +0x78, 0x10, 0x12, 0x04, 0xD8, 0xD0, 0x03, 0xD0, +0x02, 0xD0, 0x01, 0xD0, 0x00, 0x12, 0x87, 0x20, +0xC0, 0x04, 0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, +0xA3, 0x12, 0x8D, 0xA5, 0x78, 0x18, 0x12, 0x04, +0xD8, 0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, +0x00, 0x12, 0x87, 0x20, 0x90, 0x85, 0xFC, 0xEE, +0xF0, 0xA3, 0xEF, 0xF0, 0x90, 0x92, 0xC9, 0xE0, +0x54, 0xFE, 0xF0, 0xE0, 0xC3, 0x13, 0x30, 0xE0, +0x0D, 0x12, 0xC7, 0x7D, 0x12, 0x51, 0x7D, 0x90, +0x92, 0xC9, 0xE0, 0x54, 0xFD, 0xF0, 0x90, 0x85, +0xC2, 0xE0, 0x13, 0x13, 0x13, 0x54, 0x1F, 0x30, +0xE0, 0x09, 0x90, 0x01, 0x3B, 0xE0, 0x30, 0xE4, +0x02, 0xF1, 0x2F, 0x90, 0x95, 0x18, 0xE0, 0x04, +0xF0, 0xE0, 0xC3, 0x94, 0x80, 0x40, 0x0B, 0x90, +0x01, 0x98, 0xE0, 0x54, 0xFE, 0xF0, 0xE0, 0x44, +0x01, 0xF0, 0x7F, 0x01, 0xD1, 0x62, 0x90, 0x92, +0x04, 0xE0, 0x30, 0xE0, 0x09, 0x90, 0x01, 0x3B, +0xE0, 0x30, 0xE4, 0x02, 0xF1, 0x2F, 0x22, 0x7D, +0x02, 0x7F, 0x02, 0x12, 0x7C, 0x41, 0x7D, 0x01, +0x7F, 0x02, 0x02, 0x7C, 0x41, 0x12, 0xC4, 0x67, +0x70, 0x0E, 0x90, 0x85, 0xC5, 0xE0, 0x60, 0x08, +0x12, 0xC4, 0x80, 0xF1, 0xEB, 0x12, 0xC6, 0x20, +0x22, 0xE4, 0xFF, 0x12, 0x77, 0x39, 0xBF, 0x01, +0x0F, 0x90, 0x85, 0xC5, 0xE0, 0x60, 0x09, 0xF1, +0x69, 0x54, 0x07, 0x70, 0x03, 0x12, 0xC1, 0x7B, +0x22, 0x90, 0x85, 0xC9, 0xE0, 0x54, 0xFE, 0xF0, +0x22, 0xE4, 0xFF, 0x12, 0x77, 0x39, 0xBF, 0x01, +0x12, 0x90, 0x85, 0xC5, 0xE0, 0x60, 0x0C, 0xF1, +0xDC, 0x64, 0x02, 0x60, 0x03, 0x02, 0x77, 0x61, +0x12, 0x79, 0x41, 0x22, 0xE4, 0xF5, 0x75, 0x90, +0x06, 0xA9, 0xE0, 0xF5, 0x75, 0x54, 0xC0, 0x70, +0x08, 0xF1, 0x69, 0x54, 0xFD, 0xF0, 0x02, 0xC1, +0x7B, 0xE5, 0x75, 0x30, 0xE6, 0x18, 0x90, 0x85, +0xC5, 0xE0, 0x64, 0x01, 0x70, 0x12, 0xF1, 0xD5, +0x64, 0x02, 0x60, 0x05, 0x12, 0x77, 0x61, 0x80, +0x07, 0x12, 0x79, 0x41, 0x80, 0x02, 0xF1, 0x69, +0xE5, 0x75, 0x90, 0x85, 0xC9, 0x30, 0xE7, 0x08, +0xF1, 0xE8, 0x12, 0xC6, 0x20, 0x02, 0xC6, 0x9D, +0xE0, 0x54, 0xFD, 0xF0, 0x22, 0x90, 0x85, 0xC9, +0xE0, 0x44, 0x01, 0xF0, 0x90, 0x85, 0xC3, 0xE0, +0x54, 0x0F, 0x22, 0xE4, 0xFF, 0x02, 0x2D, 0xBD, +0xE0, 0x44, 0x02, 0xF0, 0xE4, 0x90, 0x91, 0x6E, +0xF0, 0x90, 0x86, 0x6E, 0xE0, 0x90, 0x91, 0x6F, +0x22, 0xE4, 0xFC, 0xED, 0x2C, 0x24, 0x00, 0x11, +0x4A, 0xE4, 0xF0, 0x0C, 0xEC, 0xB4, 0x18, 0xF3, +0x74, 0x00, 0x2D, 0x11, 0x4A, 0xEF, 0xF0, 0xEE, +0x54, 0x3F, 0xFF, 0x74, 0x01, 0x2D, 0xF5, 0x82, +0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xEF, 0xF0, 0x74, +0x02, 0x2D, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, +0x83, 0xE0, 0x54, 0xF0, 0xF0, 0x74, 0x03, 0x2D, +0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, +0x44, 0x80, 0xF0, 0x74, 0x0B, 0x2D, 0xF5, 0x82, +0xE4, 0x34, 0xFB, 0xF5, 0x83, 0xE0, 0x44, 0x10, +0xF0, 0x22, 0xF5, 0x82, 0xE4, 0x34, 0xFB, 0xF5, +0x83, 0x22, 0x90, 0x93, 0xF3, 0xEF, 0xF0, 0xA3, +0x12, 0x87, 0x4E, 0x90, 0x95, 0x12, 0xE0, 0xFE, +0x04, 0xF0, 0x90, 0x00, 0x01, 0xEE, 0x12, 0x03, +0x4E, 0x74, 0x00, 0x2F, 0xF9, 0xE4, 0x34, 0xFB, +0xFA, 0x7B, 0x01, 0xC0, 0x03, 0xC0, 0x02, 0xC0, +0x01, 0x90, 0x93, 0xF4, 0x12, 0x87, 0x45, 0x8B, +0x1B, 0x8A, 0x1C, 0x89, 0x1D, 0x75, 0x1E, 0x02, +0xD0, 0x01, 0xD0, 0x02, 0xD0, 0x03, 0x12, 0x6A, +0x21, 0x90, 0x93, 0xF3, 0xE0, 0x24, 0x02, 0xF9, +0xE4, 0x34, 0xFB, 0xFA, 0x7B, 0x01, 0xC0, 0x03, +0xC0, 0x02, 0xC0, 0x01, 0xA3, 0x12, 0x87, 0x45, +0xE9, 0x24, 0x02, 0xF9, 0xE4, 0x3A, 0x8B, 0x1B, +0xF5, 0x1C, 0x89, 0x1D, 0x90, 0x93, 0xF4, 0x11, +0xC4, 0xF5, 0x1E, 0xD0, 0x01, 0xD0, 0x02, 0xD0, +0x03, 0x02, 0x6A, 0x21, 0x12, 0x87, 0x45, 0x90, +0x00, 0x0E, 0x02, 0x03, 0x0F, 0xD3, 0x10, 0xAF, +0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x93, 0xF7, 0x12, +0x87, 0x4E, 0x7F, 0x96, 0x7E, 0x02, 0x12, 0x66, +0x80, 0xEF, 0x60, 0x4E, 0x90, 0x01, 0x17, 0xE0, +0xFE, 0x90, 0x01, 0x16, 0xE0, 0x7C, 0x00, 0x24, +0x00, 0xFF, 0xEC, 0x3E, 0xFE, 0x31, 0x37, 0x90, +0x93, 0xFA, 0xEF, 0xF0, 0xEE, 0xFF, 0x90, 0xFD, +0x11, 0xF0, 0x90, 0x93, 0xFA, 0xE0, 0xFD, 0x90, +0x02, 0x94, 0xF0, 0xA3, 0xEF, 0xF0, 0x90, 0x93, +0xF7, 0x11, 0xC4, 0x24, 0x02, 0xFF, 0xE4, 0x33, +0xFE, 0x12, 0x5A, 0xA5, 0x90, 0x93, 0xFA, 0xE0, +0x24, 0x18, 0xFF, 0x90, 0x93, 0xF7, 0x12, 0x87, +0x45, 0x12, 0x56, 0xF4, 0x90, 0x02, 0x96, 0x74, +0x01, 0xF0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xEF, +0x24, 0x01, 0xFF, 0xE4, 0x3E, 0xFE, 0x22, 0x12, +0x02, 0xF6, 0x64, 0x01, 0x60, 0x02, 0x21, 0xD0, +0x90, 0x93, 0xE2, 0xF0, 0x90, 0x93, 0xE2, 0xE0, +0xFF, 0xC3, 0x94, 0x10, 0x50, 0x27, 0xEF, 0x31, +0xD1, 0x7A, 0x93, 0x79, 0xE1, 0x12, 0x64, 0x37, +0xBF, 0x01, 0x12, 0x90, 0x93, 0xE1, 0xE0, 0xFF, +0xA3, 0xE0, 0x24, 0xE3, 0xF5, 0x82, 0xE4, 0x34, +0x93, 0xF5, 0x83, 0xEF, 0xF0, 0x90, 0x93, 0xE2, +0xE0, 0x04, 0xF0, 0x80, 0xCF, 0x75, 0x1B, 0x01, +0x75, 0x1C, 0x93, 0x75, 0x1D, 0xE3, 0x75, 0x1E, +0x08, 0x7B, 0x01, 0x7A, 0x93, 0x79, 0xC5, 0x12, +0x6A, 0x21, 0x90, 0x93, 0xC3, 0x74, 0x24, 0xF0, +0x90, 0x93, 0xD1, 0x74, 0x08, 0xF0, 0x75, 0x1B, +0x01, 0x75, 0x1C, 0x93, 0x75, 0x1D, 0xEB, 0xF5, +0x1E, 0x7B, 0x01, 0x7A, 0x93, 0x79, 0xD4, 0x12, +0x6A, 0x21, 0x90, 0x93, 0xD2, 0x74, 0x25, 0xF0, +0x90, 0x93, 0xE0, 0x74, 0x08, 0xF0, 0x7B, 0x01, +0x7A, 0x93, 0x79, 0xC3, 0x12, 0x5E, 0x10, 0x7B, +0x01, 0x7A, 0x93, 0x79, 0xD2, 0x12, 0x88, 0x13, +0x22, 0x24, 0xDE, 0xFF, 0xE4, 0x33, 0xFE, 0x7B, +0x01, 0x22, 0x12, 0xA0, 0x37, 0x12, 0x02, 0xF6, +0x64, 0x01, 0x60, 0x02, 0x41, 0x6E, 0xEF, 0x24, +0x39, 0x60, 0x12, 0x14, 0x60, 0x19, 0x24, 0x02, +0x70, 0x1F, 0xE4, 0x90, 0x93, 0xC9, 0xF0, 0xA3, +0x74, 0x06, 0xF0, 0x80, 0x14, 0x90, 0x93, 0xC9, +0x74, 0x06, 0xF0, 0xA3, 0xF0, 0x80, 0x0A, 0x90, +0x93, 0xC9, 0x74, 0x0C, 0xF0, 0xA3, 0x74, 0x04, +0xF0, 0x51, 0x81, 0xF0, 0x51, 0x6F, 0x40, 0x1C, +0x90, 0x93, 0xC7, 0xE0, 0x31, 0xD1, 0x7A, 0x93, +0x79, 0xC6, 0x12, 0x64, 0x37, 0xBF, 0x01, 0x07, +0x90, 0x93, 0xC6, 0xE0, 0xF4, 0x70, 0x3F, 0x51, +0x77, 0xF0, 0x80, 0xE0, 0x51, 0x81, 0xF0, 0x51, +0x6F, 0x40, 0x33, 0x90, 0x93, 0xC7, 0xE0, 0xFD, +0x7C, 0x00, 0x24, 0xDE, 0xFF, 0xEC, 0x33, 0xFE, +0xED, 0x24, 0x01, 0xFD, 0xEC, 0x33, 0xFC, 0x90, +0x93, 0xC9, 0xE0, 0xFB, 0xC3, 0xED, 0x9B, 0xFD, +0xEC, 0x94, 0x00, 0xFC, 0x12, 0x8F, 0x58, 0x8D, +0x82, 0x8C, 0x83, 0x12, 0x03, 0x0F, 0xFD, 0x51, +0x91, 0x51, 0x77, 0xF0, 0x80, 0xC9, 0x22, 0x90, +0x93, 0xC8, 0xE0, 0xD3, 0x94, 0x00, 0x22, 0x90, +0x93, 0xC7, 0xE0, 0x04, 0xF0, 0xA3, 0xE0, 0x14, +0x22, 0x90, 0x93, 0xC9, 0xE0, 0x90, 0x93, 0xC7, +0xF0, 0x90, 0x93, 0xCA, 0xE0, 0x90, 0x93, 0xC8, +0x22, 0x8E, 0x5B, 0x8F, 0x5C, 0x8D, 0x5D, 0xE4, +0x90, 0x93, 0xCB, 0xF0, 0x90, 0x00, 0x37, 0xE0, +0x44, 0x80, 0xFD, 0x7F, 0x37, 0x12, 0x7B, 0x3E, +0x7D, 0x69, 0x7F, 0xCF, 0x12, 0x7B, 0x3E, 0xE5, +0x5C, 0xFD, 0x7F, 0x31, 0x12, 0x7B, 0x3E, 0xE5, +0x5B, 0x54, 0x03, 0xFF, 0x90, 0x00, 0x32, 0xE0, +0x54, 0xFC, 0x4F, 0xFD, 0x7F, 0x32, 0x12, 0x7B, +0x3E, 0xAD, 0x5D, 0x7F, 0x30, 0x12, 0x7B, 0x3E, +0x90, 0x00, 0x33, 0xE0, 0x44, 0x80, 0xFD, 0x7F, +0x33, 0x12, 0x7B, 0x3E, 0x90, 0x00, 0x33, 0xE0, +0x30, 0xE7, 0x09, 0x71, 0x08, 0x50, 0x05, 0xE0, +0x04, 0xF0, 0x80, 0xF0, 0xE4, 0xFD, 0x7F, 0xCF, +0x12, 0x7B, 0x3E, 0x90, 0x00, 0x37, 0xE0, 0x54, +0x7F, 0xFD, 0x7F, 0x37, 0x12, 0x7B, 0x3E, 0x71, +0x08, 0x7F, 0x00, 0x50, 0x02, 0x7F, 0x01, 0x22, +0x90, 0x93, 0xCB, 0xE0, 0xC3, 0x94, 0x64, 0x22, +0xE4, 0x90, 0x84, 0xC1, 0xF0, 0xA3, 0xF0, 0xA3, +0xF0, 0xA3, 0xF0, 0x90, 0x92, 0x01, 0xF0, 0x22, +0x90, 0x00, 0x80, 0xE0, 0x44, 0x80, 0xFD, 0x7F, +0x80, 0x12, 0x7B, 0x3E, 0x12, 0xC7, 0xE8, 0x12, +0xCC, 0x75, 0x12, 0x7B, 0x9C, 0x91, 0x43, 0x71, +0x10, 0x7F, 0x01, 0x12, 0x85, 0x15, 0x90, 0x92, +0x08, 0x74, 0x02, 0xF0, 0xFF, 0x12, 0x85, 0x15, +0x90, 0x92, 0x08, 0xE0, 0x04, 0xF0, 0x91, 0x68, +0x91, 0x1D, 0x90, 0x01, 0xCC, 0x74, 0x0F, 0xF0, +0x90, 0x00, 0x80, 0xE0, 0x44, 0x40, 0xFD, 0x7F, +0x80, 0x12, 0x7B, 0x3E, 0x75, 0x20, 0xFF, 0x12, +0x7C, 0xCD, 0x90, 0x01, 0xA0, 0xE0, 0xB4, 0xFD, +0x05, 0xE4, 0xFF, 0x12, 0x88, 0x33, 0x91, 0xCD, +0x90, 0x00, 0x81, 0xE0, 0x44, 0x04, 0xFD, 0x7F, +0x81, 0x12, 0x7B, 0x3E, 0x12, 0xC0, 0x2B, 0x71, +0x8E, 0xE4, 0xFF, 0x02, 0x85, 0x9E, 0x7E, 0x00, +0x7F, 0x0B, 0x7D, 0x00, 0x7B, 0x01, 0x7A, 0x92, +0x79, 0xBD, 0x12, 0x06, 0xDE, 0x91, 0x16, 0xF1, +0x6C, 0xBF, 0x01, 0x1C, 0x90, 0x93, 0xFB, 0xE0, +0xFE, 0x54, 0x01, 0x90, 0x92, 0xBD, 0xF0, 0xEE, +0x54, 0x04, 0x90, 0x92, 0xBF, 0xF0, 0x90, 0x93, +0xFB, 0xE0, 0x54, 0x08, 0x90, 0x92, 0xBE, 0xF0, +0x91, 0x16, 0x12, 0x8A, 0x85, 0x70, 0x34, 0x90, +0x93, 0xFB, 0xE0, 0x54, 0x07, 0x70, 0x14, 0x7B, +0x01, 0x7A, 0x93, 0x79, 0xFC, 0x7F, 0xFA, 0xFE, +0x12, 0x64, 0x37, 0xBF, 0x01, 0x0F, 0x90, 0x93, +0xFC, 0x80, 0x03, 0x90, 0x93, 0xFB, 0xE0, 0x54, +0x07, 0x90, 0x92, 0xC1, 0xF0, 0x90, 0x93, 0xFB, +0xE0, 0x54, 0xE0, 0xC4, 0x13, 0x54, 0x07, 0x90, +0x92, 0xC0, 0xF0, 0x91, 0x16, 0x7F, 0xFD, 0x7E, +0x00, 0x12, 0x64, 0x37, 0xBF, 0x01, 0x0E, 0x90, +0x93, 0xFB, 0xE0, 0x54, 0x0C, 0x13, 0x13, 0x54, +0x3F, 0x90, 0x92, 0xC2, 0xF0, 0x22, 0x7B, 0x01, +0x7A, 0x93, 0x79, 0xFB, 0x22, 0xB1, 0xF9, 0x12, +0x7B, 0xEF, 0x12, 0x3C, 0x03, 0x12, 0xCA, 0xE9, +0x12, 0xCD, 0x91, 0xB1, 0x1E, 0x91, 0x3E, 0x7E, +0x00, 0x7F, 0xB3, 0x7D, 0x00, 0x7B, 0x01, 0x7A, +0x92, 0x79, 0x09, 0x02, 0x06, 0xDE, 0xB1, 0xEC, +0x02, 0x06, 0xDE, 0x90, 0x00, 0x00, 0xE0, 0x54, +0xFB, 0xFD, 0xE4, 0xFF, 0xF1, 0x7B, 0x44, 0x04, +0xFD, 0x7F, 0x01, 0x12, 0x7B, 0x3E, 0x90, 0x01, +0x98, 0x74, 0x80, 0xF0, 0xA3, 0x74, 0x88, 0xF0, +0xA3, 0xE4, 0xF0, 0xA3, 0x74, 0x80, 0xF0, 0x22, +0x12, 0x7C, 0x4E, 0x90, 0x84, 0xC5, 0xEF, 0xF0, +0x91, 0x9C, 0x90, 0x01, 0x64, 0x74, 0x01, 0xF0, +0x90, 0x04, 0x23, 0xE0, 0x44, 0x80, 0xF0, 0x90, +0x00, 0x17, 0xE0, 0x54, 0xFC, 0x44, 0x04, 0xFD, +0x7F, 0x17, 0x12, 0x7B, 0x3E, 0x90, 0x00, 0x38, +0xE0, 0x44, 0x40, 0xFD, 0x7F, 0x38, 0x12, 0x7B, +0x3E, 0x02, 0x68, 0xE2, 0x12, 0x75, 0xB6, 0x12, +0x75, 0x58, 0xF1, 0xE5, 0x12, 0xC0, 0x0C, 0xE4, +0xF5, 0x40, 0xF5, 0x41, 0xF5, 0x42, 0x75, 0x43, +0x80, 0xAD, 0x40, 0x7F, 0x50, 0x12, 0x7B, 0x3E, +0xAD, 0x41, 0x7F, 0x51, 0x12, 0x7B, 0x3E, 0xAD, +0x42, 0x7F, 0x52, 0x12, 0x7B, 0x3E, 0xAD, 0x43, +0x7F, 0x53, 0x02, 0x7B, 0x3E, 0xE4, 0x90, 0x93, +0xFB, 0xF0, 0xA3, 0xF0, 0x12, 0xCC, 0xA0, 0xEF, +0x64, 0x01, 0x60, 0x3B, 0xC3, 0x90, 0x93, 0xFC, +0xE0, 0x94, 0x88, 0x90, 0x93, 0xFB, 0xE0, 0x94, +0x13, 0x40, 0x0F, 0x90, 0x01, 0xC1, 0xE0, 0x44, +0x10, 0xF0, 0x90, 0x01, 0xC7, 0x74, 0xFD, 0xF0, +0x80, 0x1D, 0x90, 0x93, 0xFB, 0xB1, 0xFF, 0xD1, +0x57, 0xD3, 0x90, 0x93, 0xFC, 0xE0, 0x94, 0x32, +0x90, 0x93, 0xFB, 0xE0, 0x94, 0x00, 0x40, 0xC4, +0x90, 0x01, 0xC6, 0xE0, 0x30, 0xE3, 0xBD, 0x90, +0x01, 0xC7, 0x74, 0xFE, 0xF0, 0x22, 0x7E, 0x00, +0x7F, 0xAC, 0x7D, 0x00, 0x7B, 0x01, 0x7A, 0x85, +0x79, 0xC1, 0x12, 0x06, 0xDE, 0xB1, 0xEC, 0x12, +0x06, 0xDE, 0x90, 0x85, 0xC4, 0x74, 0x02, 0xF0, +0x90, 0x85, 0xCB, 0x14, 0xF0, 0xA3, 0xF0, 0xA3, +0x74, 0x0A, 0xF0, 0x90, 0x85, 0xD1, 0xE4, 0xF0, +0xA3, 0x74, 0x02, 0xB1, 0xDC, 0x12, 0xCE, 0x89, +0xE4, 0xFD, 0xFF, 0x12, 0x57, 0x82, 0x7D, 0x0C, +0x7F, 0x02, 0x12, 0x57, 0x82, 0x7D, 0x0C, 0x7F, +0x01, 0x12, 0x57, 0x82, 0x90, 0x84, 0xC5, 0xE0, +0xFF, 0xB4, 0x01, 0x08, 0x90, 0x85, 0xD0, 0x74, +0xDD, 0xF0, 0x80, 0x0F, 0xEF, 0x90, 0x85, 0xD0, +0xB4, 0x03, 0x05, 0x74, 0xD4, 0xF0, 0x80, 0x03, +0x74, 0x40, 0xF0, 0x7F, 0x2C, 0x12, 0x7B, 0x51, +0xEF, 0x54, 0x0F, 0xFF, 0xBF, 0x05, 0x08, 0x90, +0x85, 0xFB, 0x74, 0x02, 0xF0, 0x80, 0x05, 0xE4, +0x90, 0x85, 0xFB, 0xF0, 0x90, 0x86, 0x6D, 0x74, +0x02, 0xF0, 0xA3, 0x74, 0x0F, 0xF0, 0xA3, 0xE0, +0x54, 0x01, 0x44, 0x28, 0xF0, 0xA3, 0x74, 0x07, +0xB1, 0xDC, 0xE4, 0x90, 0x85, 0xD7, 0xF0, 0xA3, +0xF0, 0x7F, 0x01, 0x12, 0x69, 0x33, 0x90, 0x05, +0x58, 0x74, 0x02, 0xF0, 0x90, 0x06, 0x04, 0xE0, +0x54, 0x7F, 0xF0, 0x90, 0x06, 0x0A, 0xE0, 0x54, +0xF8, 0xF0, 0x90, 0x05, 0x22, 0xE4, 0xF0, 0x90, +0x86, 0x71, 0xF0, 0x22, 0xF0, 0x90, 0x85, 0xFB, +0xE0, 0x24, 0x04, 0x90, 0x85, 0xDD, 0xF0, 0xA3, +0x74, 0x0A, 0xF0, 0x22, 0x7E, 0x00, 0x7F, 0x04, +0x7D, 0x00, 0x7B, 0x01, 0x7A, 0x92, 0x79, 0x04, +0x22, 0xE4, 0xFD, 0xFF, 0x02, 0x6E, 0x5F, 0xE4, +0x75, 0xF0, 0x01, 0x02, 0x07, 0x0A, 0x90, 0x95, +0x0B, 0xEF, 0xF0, 0xE4, 0xA3, 0xF0, 0xA3, 0xF0, +0x90, 0x01, 0x09, 0xE0, 0x7F, 0x00, 0x30, 0xE7, +0x02, 0x7F, 0x01, 0x90, 0x95, 0x0B, 0xE0, 0x6F, +0x60, 0x34, 0xC3, 0x90, 0x95, 0x0D, 0xE0, 0x94, +0x88, 0x90, 0x95, 0x0C, 0xE0, 0x94, 0x13, 0x40, +0x08, 0x90, 0x01, 0xC0, 0xE0, 0x44, 0x10, 0xF0, +0x22, 0x90, 0x95, 0x0C, 0xB1, 0xFF, 0xD1, 0x57, +0xD3, 0x90, 0x95, 0x0D, 0xE0, 0x94, 0x32, 0x90, +0x95, 0x0C, 0xE0, 0x94, 0x00, 0x40, 0xC1, 0x90, +0x01, 0xC6, 0xE0, 0x30, 0xE0, 0xBA, 0x22, 0x7F, +0x14, 0x7E, 0x00, 0x02, 0x7C, 0x9F, 0x12, 0xCD, +0x72, 0x7F, 0x08, 0x12, 0x7B, 0x51, 0xEF, 0x54, +0xEF, 0xFD, 0x7F, 0x08, 0x12, 0x7B, 0x3E, 0xE4, +0xFF, 0xD1, 0x06, 0x7D, 0x35, 0x7F, 0x27, 0x12, +0x7B, 0x3E, 0x90, 0x85, 0xC2, 0xE0, 0x54, 0xEF, +0xF0, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, +0xD0, 0xD1, 0x92, 0xD1, 0x5E, 0xD0, 0xD0, 0x92, +0xAF, 0x22, 0x90, 0x85, 0xC2, 0xE0, 0x44, 0x10, +0xF0, 0x90, 0x85, 0xD0, 0xE0, 0xFD, 0x7F, 0x93, +0x12, 0x7B, 0x3E, 0x90, 0x85, 0xC6, 0xE0, 0x60, +0x12, 0x90, 0x01, 0x2F, 0xE0, 0x30, 0xE7, 0x05, +0x74, 0x10, 0xF0, 0x80, 0x06, 0x90, 0x01, 0x2F, +0x74, 0x90, 0xF0, 0x7F, 0x08, 0x12, 0x7B, 0x51, +0xEF, 0x44, 0x10, 0xFD, 0x7F, 0x08, 0x12, 0x7B, +0x3E, 0x7F, 0x01, 0xD1, 0x06, 0x7D, 0x34, 0x7F, +0x27, 0x12, 0x7B, 0x3E, 0x7F, 0x90, 0xF1, 0x83, +0x7F, 0x90, 0x12, 0x7B, 0x3E, 0x7F, 0x14, 0x7E, +0x00, 0x02, 0x7C, 0x9F, 0x90, 0x85, 0xC8, 0xE0, +0xFF, 0x60, 0x03, 0xB4, 0x08, 0x0D, 0xF1, 0x1D, +0xBF, 0x01, 0x08, 0xD1, 0x82, 0x90, 0x01, 0xE5, +0xE0, 0x04, 0xF0, 0x22, 0x90, 0x85, 0xC1, 0xE0, +0x30, 0xE0, 0x19, 0x90, 0x85, 0xBC, 0xE0, 0xFF, +0x30, 0xE0, 0x0F, 0xC3, 0x13, 0x30, 0xE0, 0x08, +0x12, 0xCD, 0xB3, 0xBF, 0x01, 0x06, 0x80, 0x02, +0x80, 0x00, 0xD1, 0xE4, 0x22, 0x90, 0x92, 0x04, +0xE0, 0xC3, 0x13, 0x20, 0xE0, 0x35, 0x90, 0x02, +0x87, 0xE0, 0x60, 0x02, 0x80, 0x08, 0x90, 0x01, +0x00, 0xE0, 0x64, 0x3F, 0x60, 0x05, 0x75, 0x62, +0x01, 0x80, 0x22, 0x90, 0x02, 0x96, 0xE0, 0x60, +0x05, 0x75, 0x62, 0x10, 0x80, 0x17, 0x90, 0x02, +0x86, 0xE0, 0x20, 0xE1, 0x02, 0x80, 0x07, 0x90, +0x02, 0x86, 0xE0, 0x30, 0xE3, 0x05, 0x75, 0x62, +0x04, 0x80, 0x02, 0x80, 0x16, 0x90, 0x01, 0xB9, +0x74, 0x08, 0xF0, 0x90, 0x01, 0xB8, 0xE5, 0x62, +0xF0, 0x7F, 0x00, 0x22, 0x7F, 0xF9, 0x7E, 0x00, +0x02, 0x64, 0x37, 0x90, 0x01, 0xB8, 0xE4, 0xF0, +0x7F, 0x01, 0x22, 0x12, 0x7B, 0x3E, 0x90, 0x01, +0x01, 0xE0, 0x22, 0x12, 0x7B, 0x51, 0xEF, 0x44, +0x01, 0xFD, 0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, +0xC0, 0xD0, 0x7F, 0x02, 0xF1, 0x83, 0x7F, 0x02, +0xF1, 0x7B, 0x44, 0x02, 0xF0, 0x90, 0x01, 0x00, +0x74, 0xFF, 0xF0, 0x90, 0x06, 0xB7, 0x74, 0x09, +0xF0, 0x90, 0x06, 0xB4, 0x74, 0x86, 0xF0, 0xD0, +0xD0, 0x92, 0xAF, 0x22, 0xF1, 0x8B, 0x12, 0xCA, +0xA8, 0x74, 0x01, 0xF0, 0x22, 0xF1, 0xB4, 0x90, +0x05, 0x27, 0xE0, 0x54, 0xBF, 0xF0, 0xE4, 0x90, +0x85, 0xBF, 0xF0, 0x22, 0xF1, 0xD0, 0x80, 0xEF, +0xE4, 0xFD, 0xFF, 0x12, 0x98, 0xE3, 0x12, 0xCA, +0xC2, 0x90, 0x85, 0xBF, 0x74, 0x01, 0xF0, 0x22, +0x12, 0xCA, 0xA2, 0x80, 0xDA, 0x75, 0x48, 0x12, +0xE4, 0xF5, 0x49, 0x75, 0x4A, 0x07, 0x75, 0x4B, +0x32, 0xF5, 0x50, 0x90, 0x01, 0x30, 0xE5, 0x48, +0xF0, 0xA3, 0xE5, 0x49, 0xF0, 0xA3, 0xE5, 0x4A, +0xF0, 0xA3, 0xE5, 0x4B, 0xF0, 0x90, 0x01, 0x20, +0xE5, 0x50, 0xF0, 0x22, 0x75, 0x52, 0x06, 0x75, +0x53, 0x01, 0x75, 0x54, 0x03, 0x75, 0x55, 0x62, +0x90, 0x01, 0x38, 0xE5, 0x52, 0xF0, 0xA3, 0xE5, +0x53, 0xF0, 0xA3, 0xE5, 0x54, 0xF0, 0xA3, 0xE5, +0x55, 0xF0, 0x22, 0x90, 0x01, 0xE4, 0x74, 0x04, +0xF0, 0xA3, 0xE4, 0xF0, 0x22, 0x7D, 0x02, 0x90, +0x01, 0xC4, 0x74, 0x35, 0xF0, 0x74, 0xC0, 0xA3, +0xF0, 0x90, 0x92, 0x08, 0xE0, 0xFF, 0xED, 0xC3, +0x9F, 0x50, 0x18, 0xED, 0x25, 0xE0, 0x24, 0x81, +0xF8, 0xE6, 0x30, 0xE4, 0x0B, 0x90, 0x01, 0xB8, +0x74, 0x08, 0xF0, 0xA3, 0xF0, 0x7F, 0x00, 0x22, +0x0D, 0x80, 0xDE, 0x7F, 0x01, 0x22, 0xE4, 0x90, +0x94, 0x29, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0x90, +0x94, 0x29, 0xE0, 0x64, 0x01, 0xF0, 0x90, 0x92, +0xC6, 0xE0, 0x70, 0x18, 0x90, 0x92, 0xC3, 0xE0, +0x70, 0x12, 0xA3, 0xE0, 0x70, 0x0E, 0x90, 0x94, +0x29, 0xE0, 0x24, 0x66, 0x90, 0x01, 0xC4, 0xF0, +0x74, 0xC0, 0xA3, 0xF0, 0x12, 0x7C, 0x66, 0xBF, +0x01, 0x03, 0x12, 0x5B, 0x25, 0x90, 0x85, 0xC5, +0xE0, 0x60, 0x0E, 0x90, 0x85, 0xC8, 0xE0, 0xFF, +0x90, 0x85, 0xC7, 0xE0, 0x6F, 0x60, 0x02, 0x31, +0x7B, 0xC2, 0xAF, 0x11, 0x35, 0xBF, 0x01, 0x03, +0x12, 0xBE, 0xFC, 0xD2, 0xAF, 0x11, 0xC7, 0x12, +0xA7, 0xEC, 0x12, 0x84, 0x4D, 0x80, 0xA8, 0xD3, +0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x92, +0xC3, 0xE0, 0x60, 0x25, 0x7F, 0x54, 0x7E, 0x09, +0x12, 0x70, 0x61, 0x31, 0x6F, 0xEF, 0x44, 0xFE, +0xFF, 0xEE, 0x44, 0x03, 0xFE, 0xED, 0x44, 0x04, +0xFD, 0xEC, 0x31, 0x6F, 0x90, 0x91, 0x66, 0x12, +0x04, 0xEB, 0x7F, 0x54, 0x7E, 0x09, 0x12, 0x71, +0x18, 0x90, 0x92, 0xBE, 0xE0, 0x70, 0x24, 0x90, +0x07, 0xCC, 0xE0, 0x30, 0xE0, 0x1D, 0xE4, 0xF0, +0x90, 0x94, 0x30, 0x74, 0x22, 0xF0, 0x90, 0x94, +0x3E, 0x74, 0x01, 0xF0, 0x90, 0x94, 0x32, 0x74, +0x03, 0xF0, 0x7B, 0x01, 0x7A, 0x94, 0x79, 0x30, +0x12, 0x88, 0x13, 0x90, 0x92, 0xC6, 0xE0, 0xFF, +0x70, 0x0A, 0x90, 0x92, 0xC3, 0xE0, 0x70, 0x04, +0xA3, 0xE0, 0x60, 0x15, 0x90, 0x00, 0x1F, 0xE0, +0x54, 0xF0, 0xF0, 0x90, 0x01, 0xC5, 0x74, 0xEA, +0xF0, 0xA3, 0x74, 0xEF, 0xF0, 0xA3, 0x74, 0xFD, +0xF0, 0xEF, 0x60, 0x06, 0x90, 0x01, 0xC4, 0x74, +0x07, 0xF0, 0x90, 0x92, 0xC3, 0xE0, 0x60, 0x06, +0x90, 0x01, 0xC4, 0x74, 0x01, 0xF0, 0x90, 0x92, +0xC4, 0xE0, 0x60, 0x06, 0x90, 0x01, 0xC4, 0x74, +0x02, 0xF0, 0xD0, 0xD0, 0x92, 0xAF, 0x22, 0x90, +0x94, 0x2C, 0x12, 0x04, 0xEB, 0x90, 0x94, 0x2C, +0x02, 0x87, 0x2D, 0x90, 0x85, 0xBC, 0xE0, 0x90, +0x85, 0xC7, 0x30, 0xE0, 0x05, 0xE0, 0xFF, 0x02, +0xA7, 0x3E, 0x02, 0xA7, 0xCC, 0x91, 0x67, 0x70, +0x15, 0x90, 0x85, 0xC5, 0xE0, 0x60, 0x0F, 0x91, +0x80, 0xF0, 0x90, 0x85, 0xC1, 0xE0, 0x91, 0xAE, +0x54, 0x07, 0x70, 0x02, 0x31, 0x7B, 0x22, 0x90, +0x85, 0xC5, 0xE0, 0x60, 0x10, 0x90, 0x06, 0x92, +0xE0, 0x30, 0xE1, 0x05, 0x12, 0x6B, 0x98, 0x80, +0x04, 0xD1, 0xA5, 0x31, 0x7B, 0x90, 0x92, 0x0C, +0xE0, 0xB4, 0x01, 0x03, 0x12, 0x94, 0x17, 0x22, +0x90, 0x85, 0xC1, 0x12, 0xA6, 0x85, 0x30, 0xE0, +0x19, 0xEF, 0x54, 0xBF, 0x51, 0xCB, 0x30, 0xE0, +0x06, 0xE0, 0x44, 0x01, 0xF0, 0x80, 0x09, 0xE0, +0x54, 0xFE, 0xF0, 0x51, 0xD4, 0x74, 0x04, 0xF0, +0x31, 0x7B, 0x22, 0x90, 0x85, 0xC1, 0xE0, 0xFF, +0x12, 0xA3, 0x01, 0x30, 0xE0, 0x1E, 0xEF, 0x54, +0x7F, 0x51, 0xCB, 0x30, 0xE1, 0x06, 0xE0, 0x44, +0x02, 0xF0, 0x80, 0x08, 0xE0, 0x54, 0xFD, 0xF0, +0x51, 0xD4, 0x04, 0xF0, 0x90, 0x85, 0xC5, 0xE0, +0x60, 0x02, 0x31, 0x7B, 0x90, 0x04, 0xE0, 0xE0, +0x30, 0xE1, 0x05, 0x91, 0xD9, 0x12, 0x97, 0x70, +0x22, 0xC0, 0xE0, 0xC0, 0xF0, 0xC0, 0x83, 0xC0, +0x82, 0xC0, 0xD0, 0x75, 0xD0, 0x00, 0xC0, 0x00, +0xC0, 0x01, 0xC0, 0x02, 0xC0, 0x03, 0xC0, 0x04, +0xC0, 0x05, 0xC0, 0x06, 0xC0, 0x07, 0x90, 0x01, +0xC4, 0x74, 0x21, 0xF0, 0x74, 0xC2, 0xA3, 0xF0, +0x12, 0x75, 0x28, 0xE5, 0x56, 0x30, 0xE0, 0x02, +0xF1, 0x8B, 0xE5, 0x56, 0x30, 0xE1, 0x02, 0x51, +0xDE, 0xE5, 0x56, 0x30, 0xE2, 0x02, 0x31, 0xA7, +0xE5, 0x56, 0x30, 0xE5, 0x03, 0x12, 0x8F, 0x8B, +0xE5, 0x57, 0x30, 0xE0, 0x02, 0xB1, 0x0F, 0xE5, +0x58, 0x30, 0xE1, 0x02, 0xB1, 0x42, 0xE5, 0x58, +0x30, 0xE0, 0x03, 0x12, 0xC8, 0xE5, 0xE5, 0x58, +0x30, 0xE4, 0x02, 0xD1, 0x9C, 0xE5, 0x59, 0x30, +0xE1, 0x05, 0x7F, 0x04, 0x12, 0xB6, 0x62, 0xE5, +0x59, 0x30, 0xE4, 0x03, 0x12, 0xAF, 0x00, 0xE5, +0x59, 0x30, 0xE5, 0x02, 0x31, 0xC8, 0xE5, 0x59, +0x30, 0xE6, 0x02, 0x31, 0xEB, 0x74, 0x21, 0x04, +0x90, 0x01, 0xC4, 0xF0, 0x74, 0xC2, 0xA3, 0xF0, +0xD0, 0x07, 0xD0, 0x06, 0xD0, 0x05, 0xD0, 0x04, +0xD0, 0x03, 0xD0, 0x02, 0xD0, 0x01, 0xD0, 0x00, +0xD0, 0xD0, 0xD0, 0x82, 0xD0, 0x83, 0xD0, 0xF0, +0xD0, 0xE0, 0x32, 0xF0, 0x90, 0x04, 0xE0, 0xE0, +0x90, 0x85, 0xC2, 0x22, 0x90, 0x01, 0xB9, 0x74, +0x01, 0xF0, 0x90, 0x01, 0xB8, 0x22, 0x90, 0x85, +0xC5, 0xE0, 0x60, 0x02, 0x51, 0xEC, 0x12, 0x95, +0xDC, 0x02, 0x94, 0x17, 0x71, 0x4E, 0x13, 0x54, +0x1F, 0x30, 0xE0, 0x0B, 0xEF, 0xC4, 0x13, 0x13, +0x54, 0x03, 0x30, 0xE0, 0x02, 0x91, 0x79, 0x90, +0x85, 0xC1, 0x91, 0xB9, 0x30, 0xE0, 0x09, 0xEF, +0x91, 0xAE, 0x54, 0x07, 0x70, 0x37, 0x80, 0x33, +0x91, 0xC0, 0x40, 0x2F, 0x91, 0x67, 0x70, 0x2D, +0x12, 0xB7, 0xDC, 0x70, 0x05, 0x12, 0x70, 0xDB, +0x80, 0x24, 0x12, 0x70, 0xDB, 0x90, 0x85, 0xCF, +0xE0, 0x04, 0xF0, 0xE0, 0xD3, 0x94, 0x02, 0x40, +0x09, 0x71, 0x46, 0xE4, 0x90, 0x85, 0xCF, 0xF0, +0x80, 0x03, 0x12, 0x79, 0x41, 0xE4, 0x90, 0x85, +0xCE, 0xF0, 0x22, 0x31, 0x7B, 0x22, 0x90, 0x85, +0xC2, 0xE0, 0x54, 0xFB, 0xF0, 0x22, 0x90, 0x85, +0xC2, 0xE0, 0xFF, 0x13, 0x13, 0x22, 0x91, 0x67, +0x60, 0x02, 0x81, 0x4B, 0x90, 0x85, 0xC5, 0xE0, +0x70, 0x02, 0x81, 0x4B, 0x90, 0x05, 0x63, 0xE0, +0x90, 0x92, 0xCE, 0xF0, 0x90, 0x05, 0x62, 0xE0, +0x90, 0x92, 0xCF, 0xF0, 0x90, 0x05, 0x61, 0xE0, +0x90, 0x92, 0xD0, 0xF0, 0x90, 0x05, 0x60, 0xE0, +0x90, 0x92, 0xD1, 0xF0, 0x91, 0x80, 0xF0, 0x90, +0x85, 0xC9, 0xE0, 0x54, 0xEC, 0xF0, 0x91, 0x70, +0x24, 0xFD, 0x50, 0x02, 0x80, 0x0E, 0x90, 0x85, +0xBC, 0xE0, 0x30, 0xE0, 0x04, 0xD1, 0x2B, 0x80, +0x03, 0x12, 0xB7, 0x8C, 0x91, 0x70, 0x64, 0x01, +0x70, 0x30, 0x90, 0x06, 0xAB, 0xE0, 0x90, 0x85, +0xCC, 0xF0, 0x90, 0x06, 0xA9, 0xE0, 0x30, 0xE5, +0x05, 0xA3, 0xE0, 0xFF, 0x80, 0x05, 0x90, 0x85, +0xCB, 0xE0, 0xFF, 0x90, 0x85, 0xCB, 0xEF, 0xF0, +0xA3, 0xE0, 0xFF, 0x70, 0x08, 0x90, 0x85, 0xCB, +0xE0, 0xFE, 0xFF, 0x80, 0x00, 0x90, 0x85, 0xCC, +0xEF, 0xF0, 0x12, 0xCE, 0xA1, 0xE4, 0x90, 0x85, +0xCE, 0xF0, 0xD1, 0xAD, 0x71, 0x4E, 0x13, 0x54, +0x1F, 0x30, 0xE0, 0x5D, 0xEF, 0xC4, 0x13, 0x13, +0x54, 0x03, 0x20, 0xE0, 0x24, 0x91, 0x5F, 0x6F, +0x70, 0x4F, 0xEF, 0x60, 0x4C, 0x90, 0x85, 0xC2, +0xE0, 0x44, 0x40, 0xF0, 0xB1, 0xE9, 0x12, 0xAF, +0x67, 0x12, 0x7B, 0xFD, 0x12, 0xB7, 0x36, 0x91, +0x79, 0x90, 0x85, 0xCC, 0xE0, 0x14, 0xF0, 0x80, +0x30, 0x90, 0x85, 0xC3, 0xE0, 0xC4, 0x54, 0x0F, +0x64, 0x01, 0x70, 0x25, 0x91, 0x5F, 0xFE, 0x6F, +0x60, 0x1F, 0x90, 0x05, 0x73, 0xE0, 0xFF, 0xEE, +0x6F, 0x60, 0x16, 0x71, 0x4E, 0x54, 0x3F, 0x30, +0xE0, 0x0F, 0xEF, 0x54, 0xBF, 0x12, 0xAF, 0x67, +0x12, 0x7B, 0xBF, 0x12, 0xAF, 0x98, 0x12, 0xAF, +0x7A, 0x91, 0x57, 0x90, 0x85, 0xBC, 0xE0, 0xC3, +0x13, 0x20, 0xE0, 0x02, 0x91, 0x57, 0x22, 0x90, +0x85, 0xC2, 0xE0, 0x44, 0x04, 0xF0, 0x22, 0x90, +0x85, 0xCB, 0xE0, 0xFF, 0xA3, 0xE0, 0x22, 0xE4, +0xFF, 0x12, 0x77, 0x39, 0xEF, 0x64, 0x01, 0x22, +0x90, 0x85, 0xC3, 0xE0, 0xFF, 0xC4, 0x54, 0x0F, +0x22, 0x7D, 0x02, 0x7F, 0x02, 0x02, 0x7C, 0x41, +0x90, 0x01, 0x57, 0xE4, 0xF0, 0x90, 0x01, 0x3C, +0x74, 0x02, 0x22, 0x90, 0x01, 0x57, 0xE0, 0x60, +0x1C, 0x91, 0x83, 0xF0, 0x90, 0x85, 0xC1, 0x91, +0xB9, 0x30, 0xE0, 0x03, 0xEF, 0x80, 0x0F, 0x91, +0xC0, 0x40, 0x0A, 0xE4, 0xFF, 0x12, 0x77, 0x39, +0xBF, 0x01, 0x02, 0x71, 0x46, 0x22, 0x54, 0xFB, +0xF0, 0x90, 0x85, 0xC9, 0xE0, 0x54, 0xFD, 0xF0, +0x22, 0xE0, 0xFF, 0x13, 0x13, 0x54, 0x3F, 0x22, +0x90, 0x85, 0xCE, 0xE0, 0x04, 0xF0, 0x90, 0x85, +0xC9, 0xE0, 0x54, 0xEF, 0xF0, 0x90, 0x86, 0x6D, +0xE0, 0xFF, 0x90, 0x85, 0xCE, 0xE0, 0xD3, 0x9F, +0x22, 0x90, 0x92, 0x09, 0xE0, 0x30, 0xE0, 0x1F, +0xA3, 0xE0, 0xC3, 0x13, 0x54, 0x07, 0xB1, 0x00, +0xE0, 0xFE, 0x30, 0xE0, 0x12, 0xEF, 0xB1, 0x01, +0xEE, 0x54, 0xFE, 0x12, 0x97, 0xED, 0x12, 0x94, +0x0E, 0xFD, 0x7F, 0x02, 0x12, 0x92, 0xF6, 0x22, +0xFF, 0x75, 0xF0, 0x0E, 0xA4, 0x24, 0x15, 0xF5, +0x82, 0xE4, 0x34, 0x92, 0xF5, 0x83, 0x22, 0x12, +0xCD, 0x2D, 0x90, 0x94, 0x6F, 0xEF, 0xF0, 0x30, +0xE0, 0x05, 0x7D, 0x01, 0xE4, 0x80, 0x02, 0xE4, +0xFD, 0xFF, 0x12, 0x57, 0x82, 0x90, 0x94, 0x6F, +0xE0, 0x30, 0xE6, 0x11, 0x90, 0x01, 0x2F, 0xE0, +0x30, 0xE7, 0x04, 0xE4, 0xF0, 0x80, 0x06, 0x90, +0x01, 0x2F, 0x74, 0x80, 0xF0, 0xF1, 0x7D, 0x02, +0x51, 0x7D, 0x90, 0x85, 0xBC, 0xE0, 0xFF, 0x30, +0xE0, 0x3F, 0x90, 0x85, 0xC0, 0xE0, 0x7E, 0x00, +0xB4, 0x02, 0x02, 0x7E, 0x01, 0x90, 0x85, 0xBF, +0xE0, 0x7D, 0x00, 0xB4, 0x04, 0x02, 0x7D, 0x01, +0xED, 0x4E, 0x70, 0x25, 0xEF, 0xC3, 0x13, 0x30, +0xE0, 0x03, 0x02, 0xAE, 0xAE, 0x91, 0x8B, 0x90, +0x85, 0xC0, 0xE0, 0xB4, 0x0C, 0x06, 0xE4, 0xFD, +0x7F, 0x08, 0x80, 0x0A, 0x90, 0x85, 0xC0, 0xE0, +0xB4, 0x04, 0x06, 0xE4, 0xFD, 0xFF, 0x12, 0xA3, +0x0C, 0x22, 0xE4, 0x90, 0x94, 0x6F, 0xF0, 0x90, +0x85, 0xC5, 0xE0, 0x60, 0x53, 0x91, 0x67, 0x70, +0x4F, 0xB1, 0xE9, 0xF0, 0xF1, 0xC0, 0x90, 0x94, +0x6F, 0x74, 0x01, 0xF0, 0xE4, 0x90, 0x85, 0xCC, +0xF0, 0x90, 0x85, 0xBC, 0xE0, 0x30, 0xE0, 0x16, +0x90, 0x85, 0xC0, 0xE0, 0xB4, 0x02, 0x05, 0xE4, +0x90, 0x94, 0x6F, 0xF0, 0x12, 0xA6, 0x8D, 0xEF, +0x70, 0x04, 0x90, 0x94, 0x6F, 0xF0, 0x90, 0x94, +0x6F, 0xE0, 0x60, 0x1C, 0x90, 0x85, 0xC8, 0xE0, +0x20, 0xE2, 0x03, 0x12, 0xA3, 0x08, 0x90, 0x85, +0xC9, 0xE0, 0x44, 0x10, 0x12, 0xAF, 0x91, 0x90, +0x85, 0xCD, 0xE0, 0x90, 0x91, 0x6F, 0xD1, 0x20, +0x22, 0x90, 0x85, 0xCB, 0xE0, 0x90, 0x05, 0x73, +0x22, 0x90, 0x92, 0x0A, 0xE0, 0xC3, 0x13, 0x54, +0x07, 0xFF, 0x75, 0xF0, 0x0E, 0xA4, 0x24, 0x17, +0xF5, 0x82, 0xE4, 0x34, 0x92, 0xF5, 0x83, 0xE0, +0xFE, 0xEF, 0x75, 0xF0, 0x0E, 0xA4, 0x24, 0x16, +0xF5, 0x82, 0xE4, 0x34, 0x92, 0xF5, 0x83, 0xE0, +0x90, 0x91, 0x6F, 0xF0, 0x90, 0x91, 0x6E, 0xEE, +0xF0, 0xE4, 0xFB, 0xFD, 0x7F, 0x54, 0x7E, 0x01, +0x02, 0x61, 0x41, 0x90, 0x06, 0xA9, 0xE0, 0x90, +0x94, 0x51, 0xF0, 0xE0, 0xFD, 0x54, 0xC0, 0x70, +0x05, 0x12, 0xB7, 0x69, 0x80, 0x5A, 0xED, 0x30, +0xE6, 0x41, 0x90, 0x85, 0xC5, 0xE0, 0x64, 0x02, +0x70, 0x28, 0x90, 0x85, 0xC1, 0xE0, 0xFF, 0xC3, +0x13, 0x20, 0xE0, 0x09, 0x90, 0x85, 0xC9, 0xE0, +0x44, 0x01, 0xF0, 0x80, 0x1C, 0x12, 0xB7, 0xDC, +0x64, 0x01, 0x70, 0x22, 0x90, 0x85, 0xC9, 0xE0, +0x44, 0x04, 0xF0, 0x7F, 0x01, 0x12, 0x62, 0x8E, +0x80, 0x14, 0x12, 0xB7, 0xD5, 0x64, 0x02, 0x60, +0x05, 0x12, 0x77, 0x61, 0x80, 0x08, 0x12, 0x79, +0x41, 0x80, 0x03, 0x12, 0xB7, 0x69, 0x90, 0x94, +0x51, 0xE0, 0x90, 0x85, 0xC9, 0x30, 0xE7, 0x07, +0x12, 0xB7, 0xE8, 0xD1, 0x20, 0x80, 0x06, 0xE0, +0x54, 0xFD, 0xF0, 0x22, 0x22, 0x90, 0x85, 0xC1, +0xE0, 0x44, 0x04, 0xF0, 0x22, 0x90, 0x85, 0xC1, +0xE0, 0x54, 0xF7, 0xF0, 0x22, 0x90, 0x85, 0xD1, +0xA3, 0xE0, 0x90, 0x05, 0x58, 0xF0, 0x22, 0xAC, +0x07, 0x90, 0x92, 0xC9, 0xE0, 0xF9, 0x30, 0xE0, +0x02, 0xE1, 0x6B, 0x90, 0x85, 0xC1, 0xE0, 0x30, +0xE0, 0x16, 0x90, 0x85, 0xFB, 0xE0, 0x24, 0x04, +0x90, 0x85, 0xDA, 0xF0, 0x90, 0x85, 0xFB, 0xE0, +0x24, 0x03, 0x90, 0x85, 0xD9, 0xF0, 0x80, 0x0D, +0x90, 0x85, 0xDA, 0x74, 0x02, 0xF0, 0x90, 0x85, +0xD9, 0x14, 0xF0, 0x0B, 0x0B, 0x90, 0x85, 0xD9, +0xE0, 0xFA, 0x90, 0x85, 0xD8, 0xE0, 0xD3, 0x9A, +0x50, 0x0E, 0x90, 0x85, 0xCD, 0xEB, 0xF0, 0x90, +0x85, 0xDA, 0xE0, 0xC3, 0x9D, 0x2C, 0x80, 0x11, +0xC3, 0xED, 0x9A, 0x2B, 0x90, 0x85, 0xCD, 0xF0, +0x90, 0x85, 0xD9, 0xE0, 0xFF, 0xA3, 0xE0, 0xC3, +0x9F, 0x90, 0x85, 0xDD, 0xF0, 0x90, 0x85, 0xDA, +0xE0, 0xFF, 0x24, 0x0A, 0xFD, 0xE4, 0x33, 0xFC, +0x90, 0x85, 0xDD, 0xF1, 0x73, 0x98, 0x40, 0x04, +0xEF, 0x24, 0x0A, 0xF0, 0x90, 0x85, 0xDD, 0xE0, +0xFF, 0x24, 0x23, 0xFD, 0xE4, 0x33, 0xFC, 0x90, +0x85, 0xCD, 0xF1, 0x73, 0x98, 0x40, 0x04, 0xEF, +0x24, 0x23, 0xF0, 0x90, 0x85, 0xDD, 0xE0, 0xFF, +0x7E, 0x00, 0x90, 0x85, 0xD1, 0xEE, 0xF0, 0xA3, +0xEF, 0xF0, 0x90, 0x05, 0x58, 0xE0, 0x6F, 0x70, +0x01, 0xE4, 0x60, 0x02, 0xD1, 0xAD, 0xE9, 0x54, +0xFD, 0x80, 0x03, 0xE9, 0x44, 0x02, 0x90, 0x92, +0xC9, 0xF0, 0x22, 0xE0, 0xD3, 0x9D, 0xEC, 0x64, +0x80, 0xF8, 0x74, 0x80, 0x22, 0x90, 0x85, 0xD7, +0xE0, 0xFF, 0xA3, 0xE0, 0xFD, 0x90, 0x85, 0xDE, +0xE0, 0xFB, 0x22, 0x90, 0x92, 0x0A, 0xE0, 0x30, +0xE0, 0x0B, 0x90, 0x92, 0xB4, 0xE0, 0x60, 0x05, +0x7F, 0x07, 0x12, 0xAA, 0xF7, 0x22, 0x90, 0x85, +0xBC, 0xE0, 0xFF, 0x30, 0xE0, 0x05, 0x12, 0xA7, +0x6C, 0x60, 0x14, 0x90, 0x85, 0xC5, 0xE0, 0x70, +0x04, 0xEF, 0x30, 0xE0, 0x0A, 0x90, 0x85, 0xC8, +0xE0, 0x64, 0x02, 0x60, 0x02, 0x71, 0x56, 0x22, +0x90, 0x05, 0x63, 0xE0, 0x90, 0x92, 0xD2, 0xF0, +0x90, 0x05, 0x62, 0xE0, 0x90, 0x92, 0xD3, 0xF0, +0x90, 0x05, 0x61, 0xE0, 0x90, 0x92, 0xD4, 0xF0, +0x90, 0x05, 0x60, 0xE0, 0x90, 0x92, 0xD5, 0xF0, +0x90, 0x92, 0xC9, 0xE0, 0x44, 0x01, 0xF0, 0x22, +0x90, 0x84, 0xA1, 0x74, 0x02, 0xF0, 0xA3, 0x74, +0x9A, 0xF0, 0xA3, 0x74, 0x26, 0xF0, 0x90, 0x84, +0xA7, 0x74, 0x80, 0xF0, 0xA3, 0x74, 0x03, 0xF0, +0x22, 0xE4, 0xFB, 0xFA, 0xFD, 0x7F, 0x01, 0x12, +0x86, 0x4E, 0x90, 0x94, 0x3F, 0xEF, 0xF0, 0x60, +0xF0, 0x90, 0x84, 0xC1, 0xE0, 0xFF, 0x70, 0x04, +0xA3, 0xE0, 0x60, 0xE5, 0xC2, 0xAF, 0xEF, 0x30, +0xE0, 0x0F, 0x90, 0x84, 0xC1, 0xE0, 0x54, 0xFE, +0xF0, 0xE4, 0xFF, 0x12, 0x2D, 0xBD, 0x12, 0x9B, +0x57, 0x11, 0x4B, 0x30, 0xE1, 0x06, 0x54, 0xFD, +0xF0, 0x12, 0x60, 0x5D, 0x11, 0x4B, 0x30, 0xE2, +0x06, 0x54, 0xFB, 0xF0, 0x12, 0x6A, 0x6D, 0xD2, +0xAF, 0x80, 0xC6, 0xD2, 0xAF, 0xC2, 0xAF, 0x90, +0x84, 0xC1, 0xE0, 0xFF, 0x22, 0x32, 0xC0, 0xE0, +0xC0, 0xF0, 0xC0, 0x83, 0xC0, 0x82, 0xC0, 0xD0, +0x75, 0xD0, 0x00, 0xC0, 0x00, 0xC0, 0x01, 0xC0, +0x02, 0xC0, 0x03, 0xC0, 0x04, 0xC0, 0x05, 0xC0, +0x06, 0xC0, 0x07, 0x90, 0x01, 0xC4, 0x74, 0x56, +0xF0, 0x74, 0xC8, 0xA3, 0xF0, 0x12, 0x6C, 0xBC, +0x74, 0x56, 0x04, 0x90, 0x01, 0xC4, 0xF0, 0x74, +0xC8, 0xA3, 0xF0, 0xD0, 0x07, 0xD0, 0x06, 0xD0, +0x05, 0xD0, 0x04, 0xD0, 0x03, 0xD0, 0x02, 0xD0, +0x01, 0xD0, 0x00, 0xD0, 0xD0, 0xD0, 0x82, 0xD0, +0x83, 0xD0, 0xF0, 0xD0, 0xE0, 0x32, 0x32, 0xC0, +0xE0, 0xC0, 0x83, 0xC0, 0x82, 0xC0, 0xD0, 0x75, +0xD0, 0x00, 0xC0, 0x05, 0xC0, 0x07, 0x7D, 0xA7, +0x90, 0x01, 0xC4, 0xED, 0xF0, 0x74, 0xC8, 0xFF, +0xA3, 0xF0, 0xED, 0x04, 0x90, 0x01, 0xC4, 0xF0, +0xA3, 0xEF, 0xF0, 0xD0, 0x07, 0xD0, 0x05, 0xD0, +0xD0, 0xD0, 0x82, 0xD0, 0x83, 0xD0, 0xE0, 0x32, +0x90, 0x85, 0xBC, 0xE0, 0x30, 0xE0, 0x05, 0xE4, +0xA3, 0xF0, 0xA3, 0xF0, 0x22, 0x90, 0x85, 0xBC, +0xE0, 0xFF, 0x30, 0xE0, 0x3F, 0x90, 0x85, 0xC0, +0xE0, 0x7E, 0x00, 0xB4, 0x02, 0x02, 0x7E, 0x01, +0x90, 0x85, 0xBF, 0xE0, 0x7D, 0x00, 0xB4, 0x04, +0x02, 0x7D, 0x01, 0xED, 0x4E, 0x70, 0x25, 0xEF, +0xC3, 0x13, 0x30, 0xE0, 0x03, 0x02, 0xAE, 0xAE, +0x12, 0xA7, 0x56, 0x90, 0x85, 0xC0, 0xE0, 0xB4, +0x08, 0x06, 0xE4, 0xFD, 0x7F, 0x0C, 0x80, 0x09, +0x90, 0x85, 0xC0, 0xE0, 0x70, 0x06, 0xFD, 0x7F, +0x04, 0x12, 0xA3, 0x0C, 0x22, 0xD3, 0x10, 0xAF, +0x01, 0xC3, 0xC0, 0xD0, 0x12, 0x96, 0xEE, 0x7F, +0x02, 0x12, 0x7B, 0x51, 0xEF, 0x54, 0xFE, 0xFD, +0x7F, 0x02, 0x12, 0x7B, 0x3E, 0x90, 0x01, 0x00, +0x74, 0x3F, 0xF0, 0xA3, 0xE0, 0x54, 0xFD, 0xF0, +0x90, 0x05, 0x53, 0xE0, 0x44, 0x20, 0xF0, 0xD0, +0xD0, 0x92, 0xAF, 0x22, 0x41, 0x77, 0xD3, 0x10, +0xAF, 0x01, 0xC3, 0xC0, 0xD0, 0x90, 0x85, 0xBF, +0xE0, 0x90, 0x95, 0x1A, 0xF0, 0x6F, 0x70, 0x02, +0x41, 0x6B, 0xEF, 0x14, 0x60, 0x46, 0x14, 0x60, +0x72, 0x14, 0x70, 0x02, 0x41, 0x16, 0x14, 0x70, +0x02, 0x41, 0x41, 0x24, 0x04, 0x60, 0x02, 0x41, +0x6B, 0x90, 0x95, 0x1A, 0xE0, 0xB4, 0x04, 0x05, +0x12, 0xBF, 0xCC, 0x41, 0x6B, 0x90, 0x95, 0x1A, +0xE0, 0xB4, 0x02, 0x05, 0x12, 0xBF, 0xBD, 0x41, +0x6B, 0x90, 0x95, 0x1A, 0xE0, 0xB4, 0x03, 0x05, +0x12, 0xBF, 0xE0, 0x41, 0x6B, 0x90, 0x95, 0x1A, +0xE0, 0x64, 0x01, 0x60, 0x02, 0x41, 0x6B, 0x12, +0xBF, 0xBF, 0x41, 0x6B, 0x90, 0x95, 0x1A, 0xE0, +0xB4, 0x04, 0x05, 0x12, 0xBF, 0xD0, 0x41, 0x6B, +0x90, 0x95, 0x1A, 0xE0, 0xB4, 0x02, 0x05, 0x12, +0xBF, 0xB4, 0x41, 0x6B, 0x90, 0x95, 0x1A, 0xE0, +0xB4, 0x03, 0x04, 0x51, 0xA2, 0x41, 0x6B, 0x90, +0x95, 0x1A, 0xE0, 0x60, 0x02, 0x41, 0x6B, 0x51, +0x8F, 0x41, 0x6B, 0x90, 0x95, 0x1A, 0xE0, 0xB4, +0x04, 0x04, 0x51, 0x80, 0x80, 0x75, 0x90, 0x95, +0x1A, 0xE0, 0xB4, 0x01, 0x04, 0x51, 0x70, 0x80, +0x6A, 0x90, 0x95, 0x1A, 0xE0, 0xB4, 0x03, 0x04, +0x31, 0x5C, 0x80, 0x5F, 0x90, 0x95, 0x1A, 0xE0, +0x70, 0x59, 0x51, 0x86, 0x80, 0x55, 0x90, 0x95, +0x1A, 0xE0, 0xB4, 0x04, 0x04, 0x51, 0xB2, 0x80, +0x4A, 0x90, 0x95, 0x1A, 0xE0, 0xB4, 0x01, 0x04, +0x51, 0x98, 0x80, 0x3F, 0x90, 0x95, 0x1A, 0xE0, +0xB4, 0x02, 0x04, 0x51, 0xD7, 0x80, 0x34, 0x90, +0x95, 0x1A, 0xE0, 0x70, 0x2E, 0x51, 0x96, 0x80, +0x2A, 0x90, 0x95, 0x1A, 0xE0, 0xB4, 0x03, 0x04, +0x51, 0xCA, 0x80, 0x1F, 0x90, 0x95, 0x1A, 0xE0, +0xB4, 0x01, 0x05, 0x12, 0x9F, 0xE4, 0x80, 0x13, +0x90, 0x95, 0x1A, 0xE0, 0xB4, 0x02, 0x04, 0x51, +0xCF, 0x80, 0x08, 0x90, 0x95, 0x1A, 0xE0, 0x70, +0x02, 0x51, 0x8A, 0xD0, 0xD0, 0x92, 0xAF, 0x22, +0x7D, 0x20, 0x7F, 0xFF, 0x12, 0x98, 0xE3, 0x31, +0x2D, 0x90, 0x85, 0xBF, 0x74, 0x02, 0xF0, 0x22, +0x51, 0xC2, 0x7D, 0x23, 0x80, 0xEC, 0x51, 0x8F, +0x80, 0xE6, 0x51, 0x8F, 0x02, 0x9F, 0xE4, 0x90, +0x85, 0xBF, 0x74, 0x01, 0xF0, 0x22, 0x51, 0x8F, +0x7D, 0x21, 0x7F, 0xFF, 0x51, 0xAB, 0x74, 0x03, +0xF0, 0x22, 0x51, 0xA8, 0x74, 0x01, 0xF0, 0x22, +0xE4, 0xFD, 0xFF, 0x12, 0x98, 0xE3, 0x90, 0x85, +0xBF, 0x22, 0x7D, 0x22, 0x7F, 0xFF, 0x12, 0x98, +0xE3, 0x51, 0xC2, 0x90, 0x85, 0xBF, 0x74, 0x03, +0xF0, 0x22, 0x90, 0x05, 0x27, 0xE0, 0x44, 0x40, +0xF0, 0x22, 0x7D, 0x25, 0x02, 0x9F, 0xE6, 0x12, +0xBF, 0x8B, 0x7D, 0x24, 0x02, 0x9F, 0xE6, 0x12, +0xBF, 0x8B, 0x90, 0x85, 0xBF, 0x74, 0x03, 0xF0, +0x22, 0x12, 0x02, 0xF6, 0x90, 0x94, 0x97, 0xF0, +0x22, 0x7B, 0x00, 0x7A, 0x00, 0x79, 0x00, 0x90, +0x89, 0x1B, 0x12, 0x87, 0x4E, 0x7B, 0xFF, 0x7A, +0x82, 0x79, 0x00, 0x90, 0x89, 0x1E, 0x12, 0x87, +0x4E, 0x7A, 0x82, 0x79, 0x3F, 0x90, 0x89, 0x21, +0x12, 0x87, 0x4E, 0x7A, 0x82, 0x79, 0xE1, 0x90, +0x89, 0x27, 0x12, 0x87, 0x4E, 0x7A, 0x82, 0x79, +0xF5, 0x90, 0x89, 0x2A, 0x12, 0x87, 0x4E, 0x7A, +0x83, 0x79, 0x1D, 0x90, 0x89, 0x2D, 0x12, 0x87, +0x4E, 0x7A, 0x83, 0x79, 0x31, 0x90, 0x89, 0x33, +0x12, 0x87, 0x4E, 0x7A, 0x83, 0x79, 0x59, 0x90, +0x89, 0x36, 0x12, 0x87, 0x4E, 0x7A, 0x83, 0x79, +0x81, 0x90, 0x89, 0x39, 0x12, 0x87, 0x4E, 0xE4, +0x90, 0x94, 0xA8, 0xF0, 0x90, 0x94, 0x97, 0xF0, +0x90, 0x93, 0xFB, 0xF0, 0x90, 0x93, 0xFB, 0xE0, +0xFF, 0xC3, 0x94, 0x05, 0x50, 0x10, 0x74, 0xB9, +0x2F, 0x12, 0x9E, 0x49, 0xE4, 0xF0, 0x90, 0x93, +0xFB, 0xE0, 0x04, 0xF0, 0x80, 0xE6, 0x22, 0x90, +0x94, 0x46, 0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0xA3, +0xED, 0xF0, 0xEB, 0x75, 0xF0, 0x06, 0xA4, 0xFF, +0x90, 0x89, 0x21, 0x12, 0x87, 0x45, 0xE9, 0x2F, +0xF9, 0xEA, 0x35, 0xF0, 0xFA, 0x90, 0x94, 0x4E, +0x12, 0x87, 0x4E, 0x90, 0x94, 0x48, 0xE0, 0x12, +0x9F, 0x5F, 0xE0, 0xFF, 0xA3, 0xE0, 0x90, 0x94, +0x4B, 0xCF, 0xF0, 0xA3, 0xEF, 0xF0, 0xE4, 0xA3, +0xF0, 0x90, 0x94, 0x4E, 0x12, 0x87, 0x45, 0x90, +0x94, 0x4D, 0xE0, 0xFF, 0xF5, 0x82, 0x75, 0x83, +0x00, 0x12, 0x03, 0x0F, 0xFD, 0x7C, 0x00, 0x90, +0x94, 0x48, 0xE0, 0x75, 0xF0, 0x12, 0x90, 0x89, +0x44, 0x12, 0x05, 0x28, 0x75, 0xF0, 0x02, 0xEF, +0x12, 0x05, 0x28, 0xE0, 0xFE, 0xA3, 0xE0, 0xFF, +0x90, 0x94, 0x4A, 0xE0, 0xFB, 0xEF, 0xA8, 0x03, +0x08, 0x80, 0x05, 0xCE, 0xC3, 0x13, 0xCE, 0x13, +0xD8, 0xF9, 0x91, 0x56, 0xEE, 0x8F, 0xF0, 0x12, +0x07, 0x0A, 0x90, 0x94, 0x4D, 0xE0, 0x04, 0xF0, +0xE0, 0xB4, 0x05, 0xAD, 0x90, 0x94, 0x4E, 0x12, +0x87, 0x45, 0x12, 0x97, 0xF6, 0xFD, 0x7C, 0x00, +0x90, 0x94, 0x4A, 0xE0, 0xFF, 0x90, 0x94, 0x46, +0xE0, 0xFE, 0xA3, 0xE0, 0xA8, 0x07, 0x08, 0x80, +0x05, 0xCE, 0xC3, 0x13, 0xCE, 0x13, 0xD8, 0xF9, +0x91, 0x56, 0xE0, 0xFC, 0xA3, 0xE0, 0xFD, 0xD3, +0x9F, 0xEC, 0x9E, 0x40, 0x08, 0xED, 0x9F, 0xFF, +0xEC, 0x9E, 0xFE, 0x80, 0x04, 0x7E, 0x00, 0x7F, +0x00, 0x90, 0x94, 0x4B, 0xEE, 0xF0, 0xA3, 0xEF, +0xF0, 0x90, 0x94, 0x4B, 0xE0, 0xFE, 0xA3, 0xE0, +0xFF, 0x90, 0x94, 0x48, 0xE0, 0x12, 0x9F, 0x5F, +0xEE, 0xF0, 0xA3, 0xEF, 0xF0, 0x22, 0xFF, 0x12, +0x03, 0x70, 0x90, 0x94, 0x4B, 0x22, 0x12, 0x97, +0x5A, 0xE0, 0x20, 0xE0, 0x08, 0xC3, 0x13, 0x30, +0xE0, 0x0A, 0x02, 0x97, 0xEE, 0x12, 0x97, 0x5A, +0xE0, 0x44, 0x04, 0xF0, 0x22, 0x90, 0x01, 0x94, +0xE0, 0x44, 0x01, 0xF0, 0x90, 0x01, 0xC7, 0xE4, +0xF0, 0x22, 0x90, 0x01, 0x9A, 0xE0, 0x54, 0xC0, +0x44, 0x0B, 0xF0, 0x7F, 0x0A, 0x7E, 0x00, 0x12, +0x7C, 0x9F, 0x90, 0x01, 0x98, 0xE0, 0x54, 0xC0, +0x7F, 0x00, 0xB4, 0x40, 0x02, 0x7F, 0x01, 0x22, +0x90, 0x01, 0x98, 0xE4, 0xF0, 0xA3, 0xF0, 0xA3, +0x74, 0x11, 0xF0, 0xA3, 0xE4, 0xF0, 0x7F, 0x0A, +0xFE, 0x12, 0x7C, 0x9F, 0x90, 0x01, 0x99, 0xE0, +0x54, 0x30, 0xFF, 0x64, 0x10, 0x60, 0x04, 0xEF, +0xB4, 0x20, 0x03, 0x7F, 0x01, 0x22, 0x7F, 0x00, +0x22, 0x90, 0x01, 0xCF, 0xE0, 0x90, 0x94, 0x51, +0xF0, 0xE0, 0xFF, 0x30, 0xE0, 0x07, 0x90, 0x01, +0xCF, 0xE0, 0x54, 0xFE, 0xF0, 0xEF, 0x30, 0xE5, +0x23, 0x90, 0x01, 0xCF, 0xE0, 0x54, 0xDF, 0xF0, +0x90, 0x01, 0x34, 0x74, 0x20, 0xF0, 0xE4, 0xF5, +0xA8, 0xF5, 0xE8, 0x12, 0x75, 0xB6, 0x90, 0x00, +0x03, 0xE0, 0x54, 0xFB, 0xFD, 0x7F, 0x03, 0x12, +0x7B, 0x3E, 0x80, 0xFE, 0x22, 0xD3, 0x10, 0xAF, +0x01, 0xC3, 0xC0, 0xD0, 0xE4, 0xFE, 0xFD, 0xEF, +0xB4, 0x01, 0x0D, 0xEB, 0xB4, 0x02, 0x03, 0x0D, +0x80, 0x06, 0xEB, 0xB4, 0x01, 0x02, 0x7D, 0x02, +0xAF, 0x06, 0xEF, 0xC4, 0x54, 0xF0, 0x4D, 0xFF, +0xD0, 0xD0, 0x92, 0xAF, 0x22, 0xE4, 0x90, 0x94, +0x71, 0xF0, 0xA3, 0xF0, 0x7F, 0x83, 0x12, 0x7B, +0x51, 0x90, 0x94, 0x70, 0xEF, 0xF0, 0x7F, 0x83, +0x12, 0x7B, 0x51, 0xAE, 0x07, 0x90, 0x94, 0x70, +0xE0, 0xFF, 0xB5, 0x06, 0x01, 0x22, 0xC3, 0x90, +0x94, 0x72, 0xE0, 0x94, 0x64, 0x90, 0x94, 0x71, +0xE0, 0x94, 0x00, 0x40, 0x0D, 0x90, 0x01, 0xC0, +0xE0, 0x44, 0x40, 0xF0, 0x90, 0x94, 0x70, 0xE0, +0xFF, 0x22, 0x90, 0x94, 0x71, 0x12, 0xBD, 0xFF, +0x80, 0xC2, 0x90, 0x01, 0xC4, 0x74, 0x72, 0xF0, +0x74, 0xCD, 0xA3, 0xF0, 0x7F, 0x90, 0x12, 0x7B, +0x51, 0xEF, 0x20, 0xE0, 0xF7, 0x74, 0x72, 0x04, +0x90, 0x01, 0xC4, 0xF0, 0x74, 0xCD, 0xA3, 0xF0, +0x22, 0x7E, 0x00, 0x7F, 0x01, 0x7D, 0x00, 0x7B, +0x01, 0x7A, 0x85, 0x79, 0xBC, 0x12, 0x06, 0xDE, +0x90, 0x85, 0xBC, 0xE0, 0x54, 0xFD, 0xF0, 0xE4, +0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xA3, 0x74, +0x0C, 0xF0, 0x22, 0x90, 0x85, 0xBF, 0xE0, 0x64, +0x02, 0x7F, 0x01, 0x60, 0x02, 0x7F, 0x00, 0x22, +0x90, 0x95, 0x0E, 0x12, 0x87, 0x4E, 0x12, 0x71, +0x54, 0x90, 0x85, 0xC5, 0xE0, 0xFF, 0x12, 0x60, +0xD0, 0x90, 0x85, 0xC5, 0xE0, 0x60, 0x19, 0x90, +0x95, 0x0E, 0x12, 0x87, 0x45, 0x12, 0x8F, 0x73, +0x54, 0x0F, 0xFF, 0x12, 0x8F, 0xF3, 0xFD, 0x12, +0x6A, 0xB8, 0x12, 0xC7, 0x7D, 0x12, 0x51, 0x7D, +0x22, 0xD3, 0x10, 0xAF, 0x01, 0xC3, 0xC0, 0xD0, +0x12, 0x7A, 0x29, 0xEF, 0x64, 0x01, 0x60, 0x05, +0x75, 0x10, 0x01, 0x80, 0x71, 0x90, 0x85, 0xC9, +0xE0, 0xFF, 0x54, 0x03, 0x60, 0x05, 0x75, 0x10, +0x02, 0x80, 0x63, 0x90, 0x85, 0xC7, 0xE0, 0xFE, +0xE4, 0xC3, 0x9E, 0x50, 0x05, 0x75, 0x10, 0x04, +0x80, 0x54, 0xEF, 0x30, 0xE2, 0x05, 0x75, 0x10, +0x08, 0x80, 0x4B, 0x90, 0x85, 0xC9, 0xE0, 0x30, +0xE4, 0x05, 0x75, 0x10, 0x10, 0x80, 0x3F, 0x90, +0x85, 0xC2, 0xE0, 0x13, 0x13, 0x54, 0x3F, 0x20, +0xE0, 0x05, 0x75, 0x10, 0x20, 0x80, 0x2F, 0x90, +0x86, 0x71, 0xE0, 0x60, 0x05, 0x75, 0x10, 0x80, +0x80, 0x24, 0x90, 0x06, 0x62, 0xE0, 0x30, 0xE1, +0x05, 0x75, 0x10, 0x11, 0x80, 0x18, 0x90, 0x06, +0x62, 0xE0, 0x30, 0xE0, 0x0C, 0xE0, 0x54, 0xFC, +0xFF, 0xBF, 0x80, 0x05, 0x75, 0x10, 0x12, 0x80, +0x05, 0x12, 0xBF, 0x73, 0x80, 0x0E, 0x90, 0x01, +0xB9, 0x74, 0x04, 0xF0, 0x90, 0x01, 0xB8, 0xE5, +0x10, 0xF0, 0x7F, 0x00, 0xD0, 0xD0, 0x92, 0xAF, +0x22, 0x90, 0x93, 0x03, 0x74, 0x04, 0xF0, 0x14, +0xF0, 0xA3, 0xF0, 0xA3, 0xE4, 0xF0, 0xA3, 0x74, +0x64, 0xF0, 0xA3, 0x74, 0x05, 0xF0, 0xA3, 0xF0, +0x22, 0xE4, 0x90, 0x94, 0x51, 0xF0, 0xA3, 0xF0, +0xA3, 0xF0, 0x90, 0x92, 0xD2, 0x12, 0x87, 0x2D, +0x90, 0x92, 0xCE, 0x12, 0x87, 0x39, 0xC3, 0x12, +0x04, 0xB4, 0x40, 0x49, 0x90, 0x85, 0xC1, 0xE0, +0x90, 0x92, 0xD2, 0x30, 0xE0, 0x10, 0x12, 0xD0, +0xC8, 0x90, 0x85, 0xFB, 0xE0, 0x24, 0x04, 0x2F, +0xFF, 0x90, 0x93, 0x03, 0x80, 0x06, 0x12, 0xD0, +0xC8, 0x90, 0x93, 0x04, 0xE0, 0xFE, 0xC3, 0xEF, +0x9E, 0x90, 0x94, 0x52, 0xF0, 0x90, 0x94, 0x52, +0xE0, 0xFF, 0xC3, 0x94, 0x2D, 0x50, 0x16, 0x74, +0xD6, 0x2F, 0x12, 0xD0, 0x44, 0xE0, 0x04, 0xF0, +0x90, 0x85, 0xDB, 0xE0, 0x04, 0xF0, 0xE0, 0xFD, +0x7F, 0xFE, 0x12, 0x7B, 0x3E, 0x90, 0x85, 0xDB, +0xE0, 0xFF, 0xD3, 0x90, 0x93, 0x06, 0xE0, 0x9F, +0x90, 0x93, 0x05, 0xE0, 0x94, 0x00, 0x40, 0x02, +0xE1, 0xE7, 0x12, 0xD1, 0x93, 0x12, 0xD1, 0xA7, +0x50, 0x1E, 0x12, 0xD0, 0xE5, 0xFF, 0x90, 0x94, +0x53, 0xE0, 0xD3, 0x9F, 0x40, 0x0A, 0x90, 0x94, +0x51, 0xE0, 0x90, 0x94, 0x54, 0xF0, 0x80, 0x08, +0x90, 0x94, 0x51, 0xE0, 0x04, 0xF0, 0x80, 0xDD, +0x12, 0xD1, 0x93, 0x12, 0xD1, 0xA7, 0x50, 0x2E, +0x12, 0xD0, 0xE5, 0xFF, 0xC3, 0x90, 0x93, 0x06, +0xE0, 0x9F, 0xFF, 0x90, 0x93, 0x05, 0xE0, 0x94, +0x00, 0xFE, 0x90, 0x94, 0x53, 0xE0, 0xD3, 0x9F, +0xE4, 0x9E, 0x40, 0x0A, 0x90, 0x94, 0x51, 0xE0, +0x90, 0x94, 0x55, 0xF0, 0x80, 0x08, 0x90, 0x94, +0x51, 0xE0, 0x04, 0xF0, 0x80, 0xCD, 0x90, 0x94, +0x54, 0xE0, 0x90, 0x85, 0xE0, 0xF0, 0x90, 0x94, +0x55, 0xE0, 0x90, 0x85, 0xE1, 0x12, 0xD1, 0xC2, +0x94, 0x0A, 0x40, 0x0A, 0xEF, 0x24, 0xF6, 0x90, +0x85, 0xD8, 0xF0, 0xE4, 0x80, 0x0A, 0xE4, 0x90, +0x85, 0xD8, 0x12, 0xD1, 0xC2, 0x74, 0x0A, 0x9F, +0x90, 0x85, 0xD7, 0xF0, 0x90, 0x85, 0xE0, 0xE0, +0xFF, 0xA3, 0xE0, 0xC3, 0x9F, 0x90, 0x85, 0xDE, +0xF0, 0x90, 0x85, 0xC1, 0xE0, 0x30, 0xE0, 0x05, +0x90, 0x93, 0x03, 0x80, 0x03, 0x90, 0x93, 0x04, +0xE0, 0xFF, 0x90, 0x85, 0xDE, 0xE0, 0x2F, 0x04, +0xF0, 0x90, 0x85, 0xDE, 0xE0, 0xC3, 0x94, 0x0A, +0x50, 0x03, 0x74, 0x0A, 0xF0, 0x90, 0x85, 0xDE, +0xE0, 0x24, 0x02, 0xF0, 0x12, 0xC7, 0x7D, 0x12, +0x51, 0x7D, 0xE4, 0xFF, 0x12, 0x69, 0x33, 0x22, +0x12, 0xC4, 0xCD, 0x40, 0x2F, 0x90, 0x85, 0xDF, +0xE0, 0x04, 0xF0, 0x90, 0x93, 0x08, 0xE0, 0xFF, +0x90, 0x85, 0xDF, 0xE0, 0xD3, 0x9F, 0x50, 0x1C, +0x90, 0x85, 0xD7, 0xE0, 0x04, 0xF0, 0x12, 0xA7, +0x19, 0x12, 0xA7, 0x12, 0x90, 0x85, 0xDE, 0xF0, +0xFB, 0x90, 0x85, 0xD7, 0xE0, 0xFF, 0xA3, 0xE0, +0xFD, 0x12, 0x51, 0x7D, 0x22, 0xE4, 0xFE, 0x74, +0xD6, 0x2E, 0x11, 0x44, 0xE4, 0xF0, 0x0E, 0xEE, +0xB4, 0x2D, 0xF4, 0xE4, 0x90, 0x85, 0xDC, 0xF0, +0x90, 0x85, 0xDB, 0xF0, 0x90, 0x85, 0xDF, 0xF0, +0xEF, 0xB4, 0x01, 0x07, 0xA3, 0x74, 0x2D, 0xF0, +0xE4, 0xA3, 0xF0, 0x22, 0xF5, 0x82, 0xE4, 0x34, +0x92, 0xF5, 0x83, 0x22, 0x75, 0xF0, 0x1B, 0xA4, +0x24, 0x38, 0xF5, 0x82, 0xE4, 0x34, 0x92, 0xF5, +0x83, 0xE0, 0xFE, 0x54, 0x03, 0xFD, 0xEE, 0x13, +0x13, 0x54, 0x07, 0xFB, 0x90, 0x92, 0x0A, 0xE0, +0xFE, 0xC4, 0x54, 0x0F, 0x90, 0x95, 0x04, 0xF0, +0x22, 0x90, 0x94, 0xF2, 0xA3, 0xE0, 0xFF, 0x90, +0x95, 0x00, 0x74, 0x03, 0xF0, 0x7B, 0x06, 0x7D, +0x01, 0x12, 0x99, 0x36, 0x90, 0x94, 0xF6, 0xEE, +0xF0, 0xFC, 0xA3, 0xEF, 0xF0, 0xFD, 0x90, 0x94, +0xF5, 0xE0, 0xFF, 0x74, 0x10, 0x2D, 0xF5, 0x82, +0xE4, 0x34, 0xFC, 0xF5, 0x83, 0xEF, 0xF0, 0x90, +0x94, 0xF4, 0xE0, 0xFF, 0x02, 0x65, 0x61, 0x90, +0x92, 0x0A, 0xE0, 0xFF, 0xC3, 0x13, 0xFE, 0xEF, +0x54, 0xF1, 0xFF, 0xEE, 0x04, 0x54, 0x07, 0x25, +0xE0, 0x4F, 0xF0, 0xA3, 0xE0, 0xFF, 0x90, 0x92, +0x0A, 0xE0, 0xFE, 0xC3, 0x13, 0x54, 0x07, 0x22, +0x12, 0x87, 0x39, 0x90, 0x92, 0xCE, 0x12, 0x87, +0x2D, 0x12, 0x86, 0xB6, 0x78, 0x0A, 0x12, 0x04, +0xC5, 0x90, 0x85, 0xDD, 0xE0, 0xFE, 0xC3, 0x74, +0x0A, 0x9E, 0x2F, 0xFF, 0x22, 0x74, 0xD6, 0x2F, +0xF5, 0x82, 0xE4, 0x34, 0x92, 0xF5, 0x83, 0xE0, +0xFF, 0x90, 0x94, 0x53, 0xE0, 0x2F, 0xF0, 0x90, +0x93, 0x07, 0xE0, 0x22, 0x90, 0x94, 0x94, 0xEE, +0xF0, 0xFC, 0xA3, 0xEF, 0xF0, 0xFD, 0x90, 0x94, +0x92, 0xE0, 0xFF, 0x12, 0x65, 0x61, 0x90, 0x92, +0x0A, 0xE0, 0x22, 0x75, 0xF0, 0x0E, 0xA4, 0x24, +0x0F, 0xF5, 0x82, 0xE4, 0x34, 0x92, 0x22, 0x90, +0x05, 0x84, 0xEF, 0xF0, 0x7D, 0x20, 0xE4, 0xFF, +0x02, 0x7B, 0xFD, 0x90, 0x01, 0x34, 0x74, 0x40, +0xF0, 0xFD, 0xE4, 0xFF, 0x12, 0x7C, 0xA9, 0x43, +0x5E, 0x08, 0x22, 0xE0, 0x54, 0x03, 0x90, 0x91, +0x0B, 0xF0, 0x7B, 0x01, 0xAF, 0x76, 0x02, 0x27, +0x3D, 0xE5, 0x65, 0x25, 0xE0, 0x24, 0xF5, 0xF5, +0x82, 0xE4, 0x34, 0x82, 0xF5, 0x83, 0x22, 0xE4, +0x90, 0x91, 0x6E, 0xF0, 0xA3, 0x74, 0x03, 0x22, +0xEF, 0xC4, 0x54, 0xF0, 0x24, 0x03, 0xF5, 0x82, +0xE4, 0x34, 0x81, 0xF5, 0x83, 0x22, 0xE0, 0x90, +0x01, 0xBA, 0xF0, 0x90, 0x85, 0xC7, 0xE0, 0x90, +0x01, 0xBB, 0x22, 0x12, 0x05, 0x28, 0xE0, 0xFC, +0xA3, 0xE0, 0xF5, 0x82, 0x8C, 0x83, 0x22, 0x74, +0xBC, 0x25, 0x63, 0xF5, 0x82, 0xE4, 0x34, 0x8F, +0xF5, 0x83, 0x22, 0xE4, 0x90, 0x94, 0x53, 0xF0, +0x90, 0x94, 0x51, 0xF0, 0x22, 0x90, 0x94, 0xFC, +0xE0, 0xFF, 0x90, 0x94, 0xFA, 0xE0, 0x22, 0x90, +0x94, 0x51, 0xE0, 0xFF, 0xC3, 0x94, 0x2D, 0x22, +0x90, 0x05, 0x22, 0xE0, 0x90, 0x94, 0x7D, 0xF0, +0x22, 0x90, 0x00, 0x06, 0x12, 0x04, 0x18, 0x2F, +0xFF, 0x22, 0xF0, 0x90, 0x85, 0xE0, 0xE0, 0xFF, +0xC3, 0x22, 0x25, 0xE0, 0x25, 0xE0, 0xFE, 0xEF, +0x4E, 0x22, 0x7D, 0x01, 0xAF, 0x63, 0x02, 0x65, +0xC2, 0xE5, 0x65, 0x90, 0x83, 0x1D, 0x93, 0xFF, +0x22, 0x90, 0x00, 0x04, 0x12, 0x04, 0x18, 0x2F, +0x22, 0x90, 0x95, 0x07, 0xE0, 0xFF, 0x7D, 0x48, +0x22, 0xFF, 0x12, 0x02, 0xF6, 0xFE, 0x54, 0x0F, +0x22, 0x00, 0x69, 0x2A +}; +u4Byte ArrayLength_MP_8188F_FW_NIC = 21020; + + +void +ODM_ReadFirmware_MP_8188F_FW_NIC( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE)) + *((SIZE_PTR *)pFirmware) = (SIZE_PTR)Array_MP_8188F_FW_NIC; +#else + ODM_MoveMemory(pDM_Odm, pFirmware, Array_MP_8188F_FW_NIC, ArrayLength_MP_8188F_FW_NIC); +#endif + *pFirmwareSize = ArrayLength_MP_8188F_FW_NIC; +} + +#endif /* end of (defined(CONFIG_AP_WOWLAN) || (DM_ODM_SUPPORT_TYPE & (ODM_AP)))*/ + + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_fw.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_fw.h new file mode 100644 index 000000000..f203a75fe --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_fw.h @@ -0,0 +1,39 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.16*/ +#if (RTL8188F_SUPPORT == 1) +#ifndef __INC_MP_FW_HW_IMG_8188F_H +#define __INC_MP_FW_HW_IMG_8188F_H + +/****************************************************************************** +* FW_NIC.TXT +******************************************************************************/ + +void +ODM_ReadFirmware_MP_8188F_FW_NIC( + IN PDM_ODM_T pDM_Odm, + OUT u1Byte *pFirmware, + OUT u4Byte *pFirmwareSize +); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_mac.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_mac.c new file mode 100644 index 000000000..e57d90ce6 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_mac.c @@ -0,0 +1,288 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8188F_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +u4Byte Array_MP_8188F_MAC_REG[] = { + 0x024, 0x000000DF, + 0x025, 0x00000007, + 0x02B, 0x0000001C, + 0x283, 0x00000020, + 0x421, 0x0000000F, + 0x428, 0x0000000A, + 0x429, 0x00000010, + 0x430, 0x00000000, + 0x431, 0x00000000, + 0x432, 0x00000000, + 0x433, 0x00000001, + 0x434, 0x00000004, + 0x435, 0x00000005, + 0x436, 0x00000007, + 0x437, 0x00000008, + 0x43C, 0x00000004, + 0x43D, 0x00000005, + 0x43E, 0x00000007, + 0x43F, 0x00000008, + 0x440, 0x0000005D, + 0x441, 0x00000001, + 0x442, 0x00000000, + 0x444, 0x00000010, + 0x445, 0x00000000, + 0x446, 0x00000000, + 0x447, 0x00000000, + 0x448, 0x00000000, + 0x449, 0x000000F0, + 0x44A, 0x0000000F, + 0x44B, 0x0000003E, + 0x44C, 0x00000010, + 0x44D, 0x00000000, + 0x44E, 0x00000000, + 0x44F, 0x00000000, + 0x450, 0x00000000, + 0x451, 0x000000F0, + 0x452, 0x0000000F, + 0x453, 0x00000000, + 0x456, 0x0000005E, + 0x460, 0x00000044, + 0x461, 0x00000044, + 0x4BC, 0x000000C0, + 0x4C8, 0x000000FF, + 0x4C9, 0x00000008, + 0x4CC, 0x000000FF, + 0x4CD, 0x000000FF, + 0x4CE, 0x00000001, + 0x500, 0x00000026, + 0x501, 0x000000A2, + 0x502, 0x0000002F, + 0x503, 0x00000000, + 0x504, 0x00000028, + 0x505, 0x000000A3, + 0x506, 0x0000005E, + 0x507, 0x00000000, + 0x508, 0x0000002B, + 0x509, 0x000000A4, + 0x50A, 0x0000005E, + 0x50B, 0x00000000, + 0x50C, 0x0000004F, + 0x50D, 0x000000A4, + 0x50E, 0x00000000, + 0x50F, 0x00000000, + 0x512, 0x0000001C, + 0x514, 0x0000000A, + 0x516, 0x0000000A, + 0x525, 0x0000004F, + 0x550, 0x00000010, + 0x551, 0x00000010, + 0x559, 0x00000002, + 0x55C, 0x00000028, + 0x55D, 0x000000FF, + 0x605, 0x00000030, + 0x608, 0x0000000E, + 0x609, 0x0000002A, + 0x620, 0x000000FF, + 0x621, 0x000000FF, + 0x622, 0x000000FF, + 0x623, 0x000000FF, + 0x624, 0x000000FF, + 0x625, 0x000000FF, + 0x626, 0x000000FF, + 0x627, 0x000000FF, + 0x638, 0x00000028, + 0x63C, 0x0000000A, + 0x63D, 0x0000000A, + 0x63E, 0x0000000E, + 0x63F, 0x0000000E, + 0x640, 0x00000040, + 0x642, 0x00000040, + 0x643, 0x00000000, + 0x652, 0x000000C8, + 0x66E, 0x00000005, + 0x700, 0x00000021, + 0x701, 0x00000043, + 0x702, 0x00000065, + 0x703, 0x00000087, + 0x708, 0x00000021, + 0x709, 0x00000043, + 0x70A, 0x00000065, + 0x70B, 0x00000087, + +}; + +void +ODM_ReadAndConfig_MP_8188F_MAC_REG( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8188F_MAC_REG)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8188F_MAC_REG; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188F_MAC_REG\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigMAC_8188F(pDM_Odm, v1, (u1Byte)v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8188F_MAC_REG(void) +{ + return 31; +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_mac.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_mac.h new file mode 100644 index 000000000..8dd1f8ea3 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_mac.h @@ -0,0 +1,39 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#if (RTL8188F_SUPPORT == 1) +#ifndef __INC_MP_MAC_HW_IMG_8188F_H +#define __INC_MP_MAC_HW_IMG_8188F_H + + +/****************************************************************************** +* MAC_REG.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188F_MAC_REG(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188F_MAC_REG(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_rf.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_rf.c new file mode 100644 index 000000000..9d0bba561 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_rf.c @@ -0,0 +1,1143 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8188F_SUPPORT == 1) +static BOOLEAN +CheckPositive( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2, + IN const u4Byte Condition3, + IN const u4Byte Condition4 +) +{ + u1Byte _BoardType = ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA*/ + ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA*/ + ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA*/ + ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ + ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT*/ + + u4Byte cond1 = Condition1, cond2 = Condition2, cond3 = Condition3, cond4 = Condition4; + u4Byte driver1 = pDM_Odm->CutVersion << 24 | + (pDM_Odm->SupportInterface & 0xF0) << 16 | + pDM_Odm->SupportPlatform << 16 | + pDM_Odm->PackageType << 12 | + (pDM_Odm->SupportInterface & 0x0F) << 8 | + _BoardType; + + u4Byte driver2 = (pDM_Odm->TypeGLNA & 0xFF) << 0 | + (pDM_Odm->TypeGPA & 0xFF) << 8 | + (pDM_Odm->TypeALNA & 0xFF) << 16 | + (pDM_Odm->TypeAPA & 0xFF) << 24; + +u4Byte driver3 = 0; + + u4Byte driver4 = (pDM_Odm->TypeGLNA & 0xFF00) >> 8 | + (pDM_Odm->TypeGPA & 0xFF00) | + (pDM_Odm->TypeALNA & 0xFF00) << 8 | + (pDM_Odm->TypeAPA & 0xFF00) << 16; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (cond1, cond2, cond3, cond4) = (0x%X 0x%X 0x%X 0x%X)\n", cond1, cond2, cond3, cond4)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + ("===> CheckPositive (driver1, driver2, driver3, driver4) = (0x%X 0x%X 0x%X 0x%X)\n", driver1, driver2, driver3, driver4)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Platform, Interface) = (0x%X, 0x%X)\n", pDM_Odm->SupportPlatform, pDM_Odm->SupportInterface)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_TRACE, + (" (Board, Package) = (0x%X, 0x%X)\n", pDM_Odm->BoardType, pDM_Odm->PackageType)); + + + /*============== Value Defined Check ===============*/ + /*QFN Type [15:12] and Cut Version [27:24] need to do value check*/ + + if (((cond1 & 0x0000F000) != 0) && ((cond1 & 0x0000F000) != (driver1 & 0x0000F000))) + return FALSE; + if (((cond1 & 0x0F000000) != 0) && ((cond1 & 0x0F000000) != (driver1 & 0x0F000000))) + return FALSE; + + /*=============== Bit Defined Check ================*/ + /* We don't care [31:28] */ + + cond1 &= 0x00FF0FFF; + driver1 &= 0x00FF0FFF; + + if ((cond1 & driver1) == cond1) { + u4Byte bitMask = 0; + + if ((cond1 & 0x0F) == 0) /* BoardType is DONTCARE*/ + return TRUE; + + if ((cond1 & BIT0) != 0) /*GLNA*/ + bitMask |= 0x000000FF; + if ((cond1 & BIT1) != 0) /*GPA*/ + bitMask |= 0x0000FF00; + if ((cond1 & BIT2) != 0) /*ALNA*/ + bitMask |= 0x00FF0000; + if ((cond1 & BIT3) != 0) /*APA*/ + bitMask |= 0xFF000000; + + if (((cond2 & bitMask) == (driver2 & bitMask)) && ((cond4 & bitMask) == (driver4 & bitMask))) /* BoardType of each RF path is matched*/ + return TRUE; + else + return FALSE; + } else + return FALSE; +} +static BOOLEAN +CheckNegative( + IN PDM_ODM_T pDM_Odm, + IN const u4Byte Condition1, + IN const u4Byte Condition2 +) +{ + return TRUE; +} + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +u4Byte Array_MP_8188F_RadioA[] = { + 0x000, 0x00030000, + 0x008, 0x00008400, + 0x018, 0x00000407, + 0x019, 0x00000012, + 0x80000400, 0x00000000, 0x40000000, 0x00000000, + 0x01B, 0x00000C6C, + 0xA0000000, 0x00000000, + 0x01B, 0x00001C6C, + 0xB0000000, 0x00000000, + 0x01E, 0x00080009, + 0x01F, 0x00000880, + 0x02F, 0x0001A060, + 0x03F, 0x00028000, + 0x042, 0x000060C0, + 0x057, 0x000D0000, + 0x058, 0x000C0160, + 0x067, 0x00001552, + 0x083, 0x00000000, + 0x0B0, 0x000FF9F0, + 0x0B1, 0x00022218, + 0x0B2, 0x00034C00, + 0x0B4, 0x0004484B, + 0x0B5, 0x0000112A, + 0x0B6, 0x0000053E, + 0x0B7, 0x00010408, + 0x0B8, 0x00010200, + 0x0B9, 0x00080001, + 0x0BA, 0x00040001, + 0x0BB, 0x00000400, + 0x0BF, 0x000C0000, + 0x0C2, 0x00002400, + 0x0C3, 0x00000009, + 0x0C4, 0x00040C91, + 0x0C5, 0x00099999, + 0x0C6, 0x000000A3, + 0x0C7, 0x0008F820, + 0x0C8, 0x00076C06, + 0x0C9, 0x00000000, + 0x0CA, 0x00080000, + 0x0DF, 0x00000180, + 0x0EF, 0x000001A0, + 0x81000000, 0x00000000, 0x40000000, 0x00000000, + 0x051, 0x000E8231, + 0xA0000000, 0x00000000, + 0x051, 0x000E8333, + 0xB0000000, 0x00000000, + 0x80000400, 0x00000000, 0x40000000, 0x00000000, + 0x052, 0x000FAC88, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x052, 0x000FAC2C, + 0xA0000000, 0x00000000, + 0x052, 0x000FAC2C, + 0xB0000000, 0x00000000, + 0x81000000, 0x00000000, 0x40000000, 0x00000000, + 0x053, 0x00000141, + 0xA0000000, 0x00000000, + 0x053, 0x00000103, + 0xB0000000, 0x00000000, + 0x056, 0x000517F0, + 0x81000000, 0x00000000, 0x40000000, 0x00000000, + 0x035, 0x00000090, + 0x035, 0x00000190, + 0x035, 0x00000290, + 0x036, 0x00001064, + 0x036, 0x00009064, + 0x036, 0x00011064, + 0x036, 0x00019064, + 0xA0000000, 0x00000000, + 0x035, 0x00000099, + 0x035, 0x00000199, + 0x035, 0x00000299, + 0x036, 0x00000064, + 0x036, 0x00008064, + 0x036, 0x00010064, + 0x036, 0x00018064, + 0xB0000000, 0x00000000, + 0x018, 0x00000C07, + 0x05A, 0x00048000, + 0x019, 0x000739D0, + 0x80000400, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000ADD2, + 0x034, 0x00009DCF, + 0x034, 0x00008CF2, + 0x034, 0x00007CEF, + 0x034, 0x00006CEC, + 0x034, 0x00005CE9, + 0x034, 0x00004CCE, + 0x034, 0x00003CCB, + 0x034, 0x00002CC8, + 0x034, 0x00001C4B, + 0x034, 0x00000C48, + 0x91000000, 0x00000000, 0x40000000, 0x00000000, + 0x034, 0x0000ADD2, + 0x034, 0x00009DD0, + 0x034, 0x00008CF3, + 0x034, 0x00007CF0, + 0x034, 0x00006CED, + 0x034, 0x00005CD2, + 0x034, 0x00004CCF, + 0x034, 0x00003CCC, + 0x034, 0x00002CC9, + 0x034, 0x00001C4C, + 0x034, 0x00000C49, + 0xA0000000, 0x00000000, + 0x034, 0x0000ADD6, + 0x034, 0x00009DD3, + 0x034, 0x00008CF4, + 0x034, 0x00007CF1, + 0x034, 0x00006CEE, + 0x034, 0x00005CEB, + 0x034, 0x00004CCE, + 0x034, 0x00003CCB, + 0x034, 0x00002CC8, + 0x034, 0x00001C4B, + 0x034, 0x00000C48, + 0xB0000000, 0x00000000, + 0x000, 0x00030159, + 0x084, 0x00048000, + 0x086, 0x0000002A, + 0x087, 0x00000025, + 0x08E, 0x00065540, + 0x08F, 0x00088000, + 0x0EF, 0x000020A0, + 0x03B, 0x000F0F00, + 0x03B, 0x000E0B00, + 0x03B, 0x000D0900, + 0x03B, 0x000C0700, + 0x03B, 0x000B0600, + 0x03B, 0x000A0400, + 0x03B, 0x00090200, + 0x03B, 0x00080000, + 0x03B, 0x0007BF00, + 0x03B, 0x00060B00, + 0x03B, 0x0005C900, + 0x03B, 0x00040700, + 0x03B, 0x00030600, + 0x03B, 0x0002D500, + 0x03B, 0x00010200, + 0x03B, 0x0000E000, + 0x0EF, 0x000000A0, + 0x0EF, 0x00000010, + 0x03B, 0x0000C0A8, + 0x03B, 0x00010400, + 0x0EF, 0x00000000, + 0x0EF, 0x00080000, + 0x030, 0x00010000, + 0x031, 0x0000000F, + 0x032, 0x00007EFE, + 0x0EF, 0x00000000, + 0x000, 0x00010159, + 0x018, 0x0000FC07, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0x01F, 0x00080003, + 0xFFE, 0x00000000, + 0xFFE, 0x00000000, + 0x01E, 0x00000001, + 0x01F, 0x00080000, + 0x000, 0x00033D95, + +}; + +void +ODM_ReadAndConfig_MP_8188F_RadioA( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u1Byte cCond; + BOOLEAN bMatched = TRUE, bSkipped = FALSE; + u4Byte ArrayLen = sizeof(Array_MP_8188F_RadioA)/sizeof(u4Byte); + pu4Byte Array = Array_MP_8188F_RadioA; + + u4Byte v1 = 0, v2 = 0, pre_v1 = 0, pre_v2 = 0; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188F_RadioA\n")); + + while ((i + 1) < ArrayLen) { + v1 = Array[i]; + v2 = Array[i + 1]; + + if (v1 & (BIT31 | BIT30)) {/*positive & negative condition*/ + if (v1 & BIT31) {/* positive condition*/ + cCond = (u1Byte)((v1 & (BIT29|BIT28)) >> 28); + if (cCond == COND_ENDIF) {/*end*/ + bMatched = TRUE; + bSkipped = FALSE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ENDIF\n")); + } else if (cCond == COND_ELSE) { /*else*/ + bMatched = bSkipped?FALSE:TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ELSE\n")); + } else {/*if , else if*/ + pre_v1 = v1; + pre_v2 = v2; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("IF or ELSE IF\n")); + } + } else if (v1 & BIT30) { /*negative condition*/ + if (bSkipped == FALSE) { + if (CheckPositive(pDM_Odm, pre_v1, pre_v2, v1, v2)) { + bMatched = TRUE; + bSkipped = TRUE; + } else { + bMatched = FALSE; + bSkipped = FALSE; + } + } else + bMatched = FALSE; + } + } else { + if (bMatched) + odm_ConfigRF_RadioA_8188F(pDM_Odm, v1, v2); + } + i = i + 2; + } +} + +u4Byte +ODM_GetVersion_MP_8188F_RadioA(void) +{ + return 31; +} + +/****************************************************************************** +* TxPowerTrack_AP.TXT +******************************************************************************/ + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_AP_8188F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_AP_8188F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_AP_8188F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_AP_8188F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_AP_8188F[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_AP_8188F[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_AP_8188F[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_AP_8188F[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_AP_8188F[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 9, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_AP_8188F[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_AP_8188F[] = {0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 5, 6, 6, 6, 7, 8, 8, 9, 9, 9, 10, 10, 10, 10, 11, 11}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_AP_8188F[] = {0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9}; +#endif + +void +ODM_ReadAndConfig_MP_8188F_TxPowerTrack_AP( + IN PDM_ODM_T pDM_Odm +) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8188F\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_AP_8188F, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TxPowerTrack_SDIO.TXT +******************************************************************************/ + +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8188F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8188F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8188F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8188F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8188F[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8188F[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 7, 8, 8, 8, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8188F[] = {0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 9, 10, 11, 12, 13, 14, 15, 16, 17, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8188F[] = {0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8188F[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8188F[] = {0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 6, 7, 7}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8188F[] = {0, 1, 2, 3, 4, 6, 7, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 16, 16, 17, 18, 18, 18, 18, 18, 18, 18, 18, 18}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8188F[] = {0, 0, 1, 2, 2, 3, 3, 4, 5, 5, 6, 7, 8, 9, 10, 11, 12, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14, 14}; +#endif + +void +ODM_ReadAndConfig_MP_8188F_TxPowerTrack_SDIO( + IN PDM_ODM_T pDM_Odm +) +{ +#if DEV_BUS_TYPE == RT_SDIO_INTERFACE + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8188F\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_SDIO_8188F, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TxPowerTrack_USB.TXT +******************************************************************************/ + +#if DEV_BUS_TYPE == RT_USB_INTERFACE +u1Byte gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8188F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8188F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8188F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 16, 17, 17, 17, 17, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, + {0, 1, 2, 3, 3, 5, 5, 6, 6, 7, 8, 9, 10, 11, 11, 12, 13, 14, 14, 15, 15, 16, 16, 17, 17, 18, 18, 18, 18, 18}, +}; +u1Byte gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8188F[][DELTA_SWINGIDX_SIZE] = { + {0, 1, 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, + {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}, +}; +u1Byte gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8188F[] = {0, 0, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 5, 5, 5, 6, 6, 7, 7, 8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8188F[] = {0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 5, 6, 7, 8, 8, 8, 8}; +u1Byte gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8188F[] = {0, 1, 1, 2, 3, 4, 4, 4, 5, 6, 7, 8, 8, 9, 10, 11, 12, 13, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8188F[] = {0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 10, 11, 12, 13, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8188F[] = {0, 1, 2, 2, 3, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 6, 6, 7, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8188F[] = {0, 0, 0, 0, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 6, 7, 7}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8188F[] = {0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14, 14, 15, 15, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16}; +u1Byte gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8188F[] = {0, 0, 1, 2, 2, 3, 3, 4, 6, 6, 7, 8, 8, 10, 10, 11, 13, 14, 14, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15}; +#endif + +void +ODM_ReadAndConfig_MP_8188F_TxPowerTrack_USB( + IN PDM_ODM_T pDM_Odm +) +{ +#if DEV_BUS_TYPE == RT_USB_INTERFACE + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_MP_8188F\n")); + + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P, gDeltaSwingTableIdx_MP_2GA_P_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N, gDeltaSwingTableIdx_MP_2GA_N_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P, gDeltaSwingTableIdx_MP_2GB_P_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N, gDeltaSwingTableIdx_MP_2GB_N_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P, gDeltaSwingTableIdx_MP_2GCCKA_P_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N, gDeltaSwingTableIdx_MP_2GCCKA_N_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P, gDeltaSwingTableIdx_MP_2GCCKB_P_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N, gDeltaSwingTableIdx_MP_2GCCKB_N_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE); + + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P, gDeltaSwingTableIdx_MP_5GA_P_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N, gDeltaSwingTableIdx_MP_5GA_N_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P, gDeltaSwingTableIdx_MP_5GB_P_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE*3); + ODM_MoveMemory(pDM_Odm, pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N, gDeltaSwingTableIdx_MP_5GB_N_TxPowerTrack_USB_8188F, DELTA_SWINGIDX_SIZE*3); +#endif +} + +/****************************************************************************** +* TXPWR_LMT.TXT +******************************************************************************/ + +const char *Array_MP_8188F_TXPWR_LMT[] = { + "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "01", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "02", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "02", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "02", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "03", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "03", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "03", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "04", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "04", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "04", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "05", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "05", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "05", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "06", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "06", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "06", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "07", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "07", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "07", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "08", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "08", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "08", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "09", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "09", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "09", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "10", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "10", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "10", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "11", "32", + "ETSI", "2.4G", "20M", "CCK", "1T", "11", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "11", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "12", "30", + "ETSI", "2.4G", "20M", "CCK", "1T", "12", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "12", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "13", "26", + "ETSI", "2.4G", "20M", "CCK", "1T", "13", "26", + "MKK", "2.4G", "20M", "CCK", "1T", "13", "32", + "FCC", "2.4G", "20M", "CCK", "1T", "14", "63", + "ETSI", "2.4G", "20M", "CCK", "1T", "14", "63", + "MKK", "2.4G", "20M", "CCK", "1T", "14", "32", + "FCC", "2.4G", "20M", "OFDM", "1T", "01", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "01", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "01", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "02", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "02", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "02", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "03", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "03", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "03", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "04", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "04", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "04", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "05", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "05", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "05", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "06", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "06", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "06", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "07", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "07", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "07", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "08", "30", + "ETSI", "2.4G", "20M", "OFDM", "1T", "08", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "08", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "09", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "09", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "09", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "10", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "10", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "10", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "11", "28", + "ETSI", "2.4G", "20M", "OFDM", "1T", "11", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "11", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "12", "24", + "ETSI", "2.4G", "20M", "OFDM", "1T", "12", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "12", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "13", "16", + "ETSI", "2.4G", "20M", "OFDM", "1T", "13", "30", + "MKK", "2.4G", "20M", "OFDM", "1T", "13", "30", + "FCC", "2.4G", "20M", "OFDM", "1T", "14", "63", + "ETSI", "2.4G", "20M", "OFDM", "1T", "14", "63", + "MKK", "2.4G", "20M", "OFDM", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "1T", "01", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "01", "30", + "MKK", "2.4G", "20M", "HT", "1T", "01", "30", + "FCC", "2.4G", "20M", "HT", "1T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "02", "30", + "MKK", "2.4G", "20M", "HT", "1T", "02", "30", + "FCC", "2.4G", "20M", "HT", "1T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "03", "30", + "MKK", "2.4G", "20M", "HT", "1T", "03", "30", + "FCC", "2.4G", "20M", "HT", "1T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "04", "30", + "MKK", "2.4G", "20M", "HT", "1T", "04", "30", + "FCC", "2.4G", "20M", "HT", "1T", "05", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "05", "30", + "MKK", "2.4G", "20M", "HT", "1T", "05", "30", + "FCC", "2.4G", "20M", "HT", "1T", "06", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "06", "30", + "MKK", "2.4G", "20M", "HT", "1T", "06", "30", + "FCC", "2.4G", "20M", "HT", "1T", "07", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "07", "30", + "MKK", "2.4G", "20M", "HT", "1T", "07", "30", + "FCC", "2.4G", "20M", "HT", "1T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "1T", "08", "30", + "MKK", "2.4G", "20M", "HT", "1T", "08", "30", + "FCC", "2.4G", "20M", "HT", "1T", "09", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "09", "30", + "MKK", "2.4G", "20M", "HT", "1T", "09", "30", + "FCC", "2.4G", "20M", "HT", "1T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "10", "30", + "MKK", "2.4G", "20M", "HT", "1T", "10", "30", + "FCC", "2.4G", "20M", "HT", "1T", "11", "28", + "ETSI", "2.4G", "20M", "HT", "1T", "11", "30", + "MKK", "2.4G", "20M", "HT", "1T", "11", "30", + "FCC", "2.4G", "20M", "HT", "1T", "12", "24", + "ETSI", "2.4G", "20M", "HT", "1T", "12", "30", + "MKK", "2.4G", "20M", "HT", "1T", "12", "30", + "FCC", "2.4G", "20M", "HT", "1T", "13", "16", + "ETSI", "2.4G", "20M", "HT", "1T", "13", "30", + "MKK", "2.4G", "20M", "HT", "1T", "13", "30", + "FCC", "2.4G", "20M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "1T", "14", "63", + "MKK", "2.4G", "20M", "HT", "1T", "14", "63", + "FCC", "2.4G", "20M", "HT", "2T", "01", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "01", "30", + "MKK", "2.4G", "20M", "HT", "2T", "01", "30", + "FCC", "2.4G", "20M", "HT", "2T", "02", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "02", "30", + "MKK", "2.4G", "20M", "HT", "2T", "02", "30", + "FCC", "2.4G", "20M", "HT", "2T", "03", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "03", "30", + "MKK", "2.4G", "20M", "HT", "2T", "03", "30", + "FCC", "2.4G", "20M", "HT", "2T", "04", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "04", "30", + "MKK", "2.4G", "20M", "HT", "2T", "04", "30", + "FCC", "2.4G", "20M", "HT", "2T", "05", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "05", "30", + "MKK", "2.4G", "20M", "HT", "2T", "05", "30", + "FCC", "2.4G", "20M", "HT", "2T", "06", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "06", "30", + "MKK", "2.4G", "20M", "HT", "2T", "06", "30", + "FCC", "2.4G", "20M", "HT", "2T", "07", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "07", "30", + "MKK", "2.4G", "20M", "HT", "2T", "07", "30", + "FCC", "2.4G", "20M", "HT", "2T", "08", "30", + "ETSI", "2.4G", "20M", "HT", "2T", "08", "30", + "MKK", "2.4G", "20M", "HT", "2T", "08", "30", + "FCC", "2.4G", "20M", "HT", "2T", "09", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "09", "30", + "MKK", "2.4G", "20M", "HT", "2T", "09", "30", + "FCC", "2.4G", "20M", "HT", "2T", "10", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "10", "30", + "MKK", "2.4G", "20M", "HT", "2T", "10", "30", + "FCC", "2.4G", "20M", "HT", "2T", "11", "28", + "ETSI", "2.4G", "20M", "HT", "2T", "11", "30", + "MKK", "2.4G", "20M", "HT", "2T", "11", "30", + "FCC", "2.4G", "20M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "12", "30", + "MKK", "2.4G", "20M", "HT", "2T", "12", "30", + "FCC", "2.4G", "20M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "13", "30", + "MKK", "2.4G", "20M", "HT", "2T", "13", "30", + "FCC", "2.4G", "20M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "20M", "HT", "2T", "14", "63", + "MKK", "2.4G", "20M", "HT", "2T", "14", "63", + "FCC", "2.4G", "40M", "HT", "1T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "01", "63", + "MKK", "2.4G", "40M", "HT", "1T", "01", "63", + "FCC", "2.4G", "40M", "HT", "1T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "02", "63", + "MKK", "2.4G", "40M", "HT", "1T", "02", "63", + "FCC", "2.4G", "40M", "HT", "1T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "03", "26", + "MKK", "2.4G", "40M", "HT", "1T", "03", "26", + "FCC", "2.4G", "40M", "HT", "1T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "04", "26", + "MKK", "2.4G", "40M", "HT", "1T", "04", "26", + "FCC", "2.4G", "40M", "HT", "1T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "05", "26", + "MKK", "2.4G", "40M", "HT", "1T", "05", "26", + "FCC", "2.4G", "40M", "HT", "1T", "06", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "06", "26", + "MKK", "2.4G", "40M", "HT", "1T", "06", "26", + "FCC", "2.4G", "40M", "HT", "1T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "07", "26", + "MKK", "2.4G", "40M", "HT", "1T", "07", "26", + "FCC", "2.4G", "40M", "HT", "1T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "08", "26", + "MKK", "2.4G", "40M", "HT", "1T", "08", "26", + "FCC", "2.4G", "40M", "HT", "1T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "1T", "09", "26", + "MKK", "2.4G", "40M", "HT", "1T", "09", "26", + "FCC", "2.4G", "40M", "HT", "1T", "10", "24", + "ETSI", "2.4G", "40M", "HT", "1T", "10", "26", + "MKK", "2.4G", "40M", "HT", "1T", "10", "26", + "FCC", "2.4G", "40M", "HT", "1T", "11", "10", + "ETSI", "2.4G", "40M", "HT", "1T", "11", "26", + "MKK", "2.4G", "40M", "HT", "1T", "11", "26", + "FCC", "2.4G", "40M", "HT", "1T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "12", "26", + "MKK", "2.4G", "40M", "HT", "1T", "12", "26", + "FCC", "2.4G", "40M", "HT", "1T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "13", "26", + "MKK", "2.4G", "40M", "HT", "1T", "13", "26", + "FCC", "2.4G", "40M", "HT", "1T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "1T", "14", "63", + "MKK", "2.4G", "40M", "HT", "1T", "14", "63", + "FCC", "2.4G", "40M", "HT", "2T", "01", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "01", "63", + "MKK", "2.4G", "40M", "HT", "2T", "01", "63", + "FCC", "2.4G", "40M", "HT", "2T", "02", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "02", "63", + "MKK", "2.4G", "40M", "HT", "2T", "02", "63", + "FCC", "2.4G", "40M", "HT", "2T", "03", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "03", "26", + "MKK", "2.4G", "40M", "HT", "2T", "03", "26", + "FCC", "2.4G", "40M", "HT", "2T", "04", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "04", "26", + "MKK", "2.4G", "40M", "HT", "2T", "04", "26", + "FCC", "2.4G", "40M", "HT", "2T", "05", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "05", "26", + "MKK", "2.4G", "40M", "HT", "2T", "05", "26", + "FCC", "2.4G", "40M", "HT", "2T", "06", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "06", "26", + "MKK", "2.4G", "40M", "HT", "2T", "06", "26", + "FCC", "2.4G", "40M", "HT", "2T", "07", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "07", "26", + "MKK", "2.4G", "40M", "HT", "2T", "07", "26", + "FCC", "2.4G", "40M", "HT", "2T", "08", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "08", "26", + "MKK", "2.4G", "40M", "HT", "2T", "08", "26", + "FCC", "2.4G", "40M", "HT", "2T", "09", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "09", "26", + "MKK", "2.4G", "40M", "HT", "2T", "09", "26", + "FCC", "2.4G", "40M", "HT", "2T", "10", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "10", "26", + "MKK", "2.4G", "40M", "HT", "2T", "10", "26", + "FCC", "2.4G", "40M", "HT", "2T", "11", "26", + "ETSI", "2.4G", "40M", "HT", "2T", "11", "26", + "MKK", "2.4G", "40M", "HT", "2T", "11", "26", + "FCC", "2.4G", "40M", "HT", "2T", "12", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "12", "26", + "MKK", "2.4G", "40M", "HT", "2T", "12", "26", + "FCC", "2.4G", "40M", "HT", "2T", "13", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "13", "26", + "MKK", "2.4G", "40M", "HT", "2T", "13", "26", + "FCC", "2.4G", "40M", "HT", "2T", "14", "63", + "ETSI", "2.4G", "40M", "HT", "2T", "14", "63", + "MKK", "2.4G", "40M", "HT", "2T", "14", "63", + "FCC", "5G", "20M", "OFDM", "1T", "36", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "36", "32", + "MKK", "5G", "20M", "OFDM", "1T", "36", "32", + "FCC", "5G", "20M", "OFDM", "1T", "40", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "40", "32", + "MKK", "5G", "20M", "OFDM", "1T", "40", "32", + "FCC", "5G", "20M", "OFDM", "1T", "44", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "44", "32", + "MKK", "5G", "20M", "OFDM", "1T", "44", "32", + "FCC", "5G", "20M", "OFDM", "1T", "48", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "48", "32", + "MKK", "5G", "20M", "OFDM", "1T", "48", "32", + "FCC", "5G", "20M", "OFDM", "1T", "52", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "52", "32", + "MKK", "5G", "20M", "OFDM", "1T", "52", "32", + "FCC", "5G", "20M", "OFDM", "1T", "56", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "56", "32", + "MKK", "5G", "20M", "OFDM", "1T", "56", "32", + "FCC", "5G", "20M", "OFDM", "1T", "60", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "60", "32", + "MKK", "5G", "20M", "OFDM", "1T", "60", "32", + "FCC", "5G", "20M", "OFDM", "1T", "64", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "64", "32", + "MKK", "5G", "20M", "OFDM", "1T", "64", "32", + "FCC", "5G", "20M", "OFDM", "1T", "100", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "100", "32", + "MKK", "5G", "20M", "OFDM", "1T", "100", "32", + "FCC", "5G", "20M", "OFDM", "1T", "114", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "114", "32", + "MKK", "5G", "20M", "OFDM", "1T", "114", "32", + "FCC", "5G", "20M", "OFDM", "1T", "108", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "108", "32", + "MKK", "5G", "20M", "OFDM", "1T", "108", "32", + "FCC", "5G", "20M", "OFDM", "1T", "112", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "112", "32", + "MKK", "5G", "20M", "OFDM", "1T", "112", "32", + "FCC", "5G", "20M", "OFDM", "1T", "116", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "116", "32", + "MKK", "5G", "20M", "OFDM", "1T", "116", "32", + "FCC", "5G", "20M", "OFDM", "1T", "120", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "120", "32", + "MKK", "5G", "20M", "OFDM", "1T", "120", "32", + "FCC", "5G", "20M", "OFDM", "1T", "124", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "124", "32", + "MKK", "5G", "20M", "OFDM", "1T", "124", "32", + "FCC", "5G", "20M", "OFDM", "1T", "128", "32", + "ETSI", "5G", "20M", "OFDM", "1T", "128", "32", + "MKK", "5G", "20M", "OFDM", "1T", "128", "32", + "FCC", "5G", "20M", "OFDM", "1T", "132", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "132", "32", + "MKK", "5G", "20M", "OFDM", "1T", "132", "32", + "FCC", "5G", "20M", "OFDM", "1T", "136", "30", + "ETSI", "5G", "20M", "OFDM", "1T", "136", "32", + "MKK", "5G", "20M", "OFDM", "1T", "136", "32", + "FCC", "5G", "20M", "OFDM", "1T", "140", "28", + "ETSI", "5G", "20M", "OFDM", "1T", "140", "32", + "MKK", "5G", "20M", "OFDM", "1T", "140", "32", + "FCC", "5G", "20M", "OFDM", "1T", "149", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "149", "32", + "MKK", "5G", "20M", "OFDM", "1T", "149", "63", + "FCC", "5G", "20M", "OFDM", "1T", "153", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "153", "32", + "MKK", "5G", "20M", "OFDM", "1T", "153", "63", + "FCC", "5G", "20M", "OFDM", "1T", "157", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "157", "32", + "MKK", "5G", "20M", "OFDM", "1T", "157", "63", + "FCC", "5G", "20M", "OFDM", "1T", "161", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "161", "32", + "MKK", "5G", "20M", "OFDM", "1T", "161", "63", + "FCC", "5G", "20M", "OFDM", "1T", "165", "34", + "ETSI", "5G", "20M", "OFDM", "1T", "165", "32", + "MKK", "5G", "20M", "OFDM", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "1T", "36", "30", + "ETSI", "5G", "20M", "HT", "1T", "36", "32", + "MKK", "5G", "20M", "HT", "1T", "36", "32", + "FCC", "5G", "20M", "HT", "1T", "40", "30", + "ETSI", "5G", "20M", "HT", "1T", "40", "32", + "MKK", "5G", "20M", "HT", "1T", "40", "32", + "FCC", "5G", "20M", "HT", "1T", "44", "30", + "ETSI", "5G", "20M", "HT", "1T", "44", "32", + "MKK", "5G", "20M", "HT", "1T", "44", "32", + "FCC", "5G", "20M", "HT", "1T", "48", "30", + "ETSI", "5G", "20M", "HT", "1T", "48", "32", + "MKK", "5G", "20M", "HT", "1T", "48", "32", + "FCC", "5G", "20M", "HT", "1T", "52", "34", + "ETSI", "5G", "20M", "HT", "1T", "52", "32", + "MKK", "5G", "20M", "HT", "1T", "52", "32", + "FCC", "5G", "20M", "HT", "1T", "56", "34", + "ETSI", "5G", "20M", "HT", "1T", "56", "32", + "MKK", "5G", "20M", "HT", "1T", "56", "32", + "FCC", "5G", "20M", "HT", "1T", "60", "32", + "ETSI", "5G", "20M", "HT", "1T", "60", "32", + "MKK", "5G", "20M", "HT", "1T", "60", "32", + "FCC", "5G", "20M", "HT", "1T", "64", "28", + "ETSI", "5G", "20M", "HT", "1T", "64", "32", + "MKK", "5G", "20M", "HT", "1T", "64", "32", + "FCC", "5G", "20M", "HT", "1T", "100", "30", + "ETSI", "5G", "20M", "HT", "1T", "100", "32", + "MKK", "5G", "20M", "HT", "1T", "100", "32", + "FCC", "5G", "20M", "HT", "1T", "114", "30", + "ETSI", "5G", "20M", "HT", "1T", "114", "32", + "MKK", "5G", "20M", "HT", "1T", "114", "32", + "FCC", "5G", "20M", "HT", "1T", "108", "32", + "ETSI", "5G", "20M", "HT", "1T", "108", "32", + "MKK", "5G", "20M", "HT", "1T", "108", "32", + "FCC", "5G", "20M", "HT", "1T", "112", "34", + "ETSI", "5G", "20M", "HT", "1T", "112", "32", + "MKK", "5G", "20M", "HT", "1T", "112", "32", + "FCC", "5G", "20M", "HT", "1T", "116", "34", + "ETSI", "5G", "20M", "HT", "1T", "116", "32", + "MKK", "5G", "20M", "HT", "1T", "116", "32", + "FCC", "5G", "20M", "HT", "1T", "120", "34", + "ETSI", "5G", "20M", "HT", "1T", "120", "32", + "MKK", "5G", "20M", "HT", "1T", "120", "32", + "FCC", "5G", "20M", "HT", "1T", "124", "34", + "ETSI", "5G", "20M", "HT", "1T", "124", "32", + "MKK", "5G", "20M", "HT", "1T", "124", "32", + "FCC", "5G", "20M", "HT", "1T", "128", "32", + "ETSI", "5G", "20M", "HT", "1T", "128", "32", + "MKK", "5G", "20M", "HT", "1T", "128", "32", + "FCC", "5G", "20M", "HT", "1T", "132", "30", + "ETSI", "5G", "20M", "HT", "1T", "132", "32", + "MKK", "5G", "20M", "HT", "1T", "132", "32", + "FCC", "5G", "20M", "HT", "1T", "136", "30", + "ETSI", "5G", "20M", "HT", "1T", "136", "32", + "MKK", "5G", "20M", "HT", "1T", "136", "32", + "FCC", "5G", "20M", "HT", "1T", "140", "28", + "ETSI", "5G", "20M", "HT", "1T", "140", "32", + "MKK", "5G", "20M", "HT", "1T", "140", "32", + "FCC", "5G", "20M", "HT", "1T", "149", "34", + "ETSI", "5G", "20M", "HT", "1T", "149", "32", + "MKK", "5G", "20M", "HT", "1T", "149", "63", + "FCC", "5G", "20M", "HT", "1T", "153", "34", + "ETSI", "5G", "20M", "HT", "1T", "153", "32", + "MKK", "5G", "20M", "HT", "1T", "153", "63", + "FCC", "5G", "20M", "HT", "1T", "157", "34", + "ETSI", "5G", "20M", "HT", "1T", "157", "32", + "MKK", "5G", "20M", "HT", "1T", "157", "63", + "FCC", "5G", "20M", "HT", "1T", "161", "34", + "ETSI", "5G", "20M", "HT", "1T", "161", "32", + "MKK", "5G", "20M", "HT", "1T", "161", "63", + "FCC", "5G", "20M", "HT", "1T", "165", "34", + "ETSI", "5G", "20M", "HT", "1T", "165", "32", + "MKK", "5G", "20M", "HT", "1T", "165", "63", + "FCC", "5G", "20M", "HT", "2T", "36", "28", + "ETSI", "5G", "20M", "HT", "2T", "36", "30", + "MKK", "5G", "20M", "HT", "2T", "36", "30", + "FCC", "5G", "20M", "HT", "2T", "40", "28", + "ETSI", "5G", "20M", "HT", "2T", "40", "30", + "MKK", "5G", "20M", "HT", "2T", "40", "30", + "FCC", "5G", "20M", "HT", "2T", "44", "28", + "ETSI", "5G", "20M", "HT", "2T", "44", "30", + "MKK", "5G", "20M", "HT", "2T", "44", "30", + "FCC", "5G", "20M", "HT", "2T", "48", "28", + "ETSI", "5G", "20M", "HT", "2T", "48", "30", + "MKK", "5G", "20M", "HT", "2T", "48", "30", + "FCC", "5G", "20M", "HT", "2T", "52", "34", + "ETSI", "5G", "20M", "HT", "2T", "52", "30", + "MKK", "5G", "20M", "HT", "2T", "52", "30", + "FCC", "5G", "20M", "HT", "2T", "56", "32", + "ETSI", "5G", "20M", "HT", "2T", "56", "30", + "MKK", "5G", "20M", "HT", "2T", "56", "30", + "FCC", "5G", "20M", "HT", "2T", "60", "30", + "ETSI", "5G", "20M", "HT", "2T", "60", "30", + "MKK", "5G", "20M", "HT", "2T", "60", "30", + "FCC", "5G", "20M", "HT", "2T", "64", "26", + "ETSI", "5G", "20M", "HT", "2T", "64", "30", + "MKK", "5G", "20M", "HT", "2T", "64", "30", + "FCC", "5G", "20M", "HT", "2T", "100", "28", + "ETSI", "5G", "20M", "HT", "2T", "100", "30", + "MKK", "5G", "20M", "HT", "2T", "100", "30", + "FCC", "5G", "20M", "HT", "2T", "114", "28", + "ETSI", "5G", "20M", "HT", "2T", "114", "30", + "MKK", "5G", "20M", "HT", "2T", "114", "30", + "FCC", "5G", "20M", "HT", "2T", "108", "30", + "ETSI", "5G", "20M", "HT", "2T", "108", "30", + "MKK", "5G", "20M", "HT", "2T", "108", "30", + "FCC", "5G", "20M", "HT", "2T", "112", "32", + "ETSI", "5G", "20M", "HT", "2T", "112", "30", + "MKK", "5G", "20M", "HT", "2T", "112", "30", + "FCC", "5G", "20M", "HT", "2T", "116", "32", + "ETSI", "5G", "20M", "HT", "2T", "116", "30", + "MKK", "5G", "20M", "HT", "2T", "116", "30", + "FCC", "5G", "20M", "HT", "2T", "120", "34", + "ETSI", "5G", "20M", "HT", "2T", "120", "30", + "MKK", "5G", "20M", "HT", "2T", "120", "30", + "FCC", "5G", "20M", "HT", "2T", "124", "32", + "ETSI", "5G", "20M", "HT", "2T", "124", "30", + "MKK", "5G", "20M", "HT", "2T", "124", "30", + "FCC", "5G", "20M", "HT", "2T", "128", "30", + "ETSI", "5G", "20M", "HT", "2T", "128", "30", + "MKK", "5G", "20M", "HT", "2T", "128", "30", + "FCC", "5G", "20M", "HT", "2T", "132", "28", + "ETSI", "5G", "20M", "HT", "2T", "132", "30", + "MKK", "5G", "20M", "HT", "2T", "132", "30", + "FCC", "5G", "20M", "HT", "2T", "136", "28", + "ETSI", "5G", "20M", "HT", "2T", "136", "30", + "MKK", "5G", "20M", "HT", "2T", "136", "30", + "FCC", "5G", "20M", "HT", "2T", "140", "26", + "ETSI", "5G", "20M", "HT", "2T", "140", "30", + "MKK", "5G", "20M", "HT", "2T", "140", "30", + "FCC", "5G", "20M", "HT", "2T", "149", "34", + "ETSI", "5G", "20M", "HT", "2T", "149", "30", + "MKK", "5G", "20M", "HT", "2T", "149", "63", + "FCC", "5G", "20M", "HT", "2T", "153", "34", + "ETSI", "5G", "20M", "HT", "2T", "153", "30", + "MKK", "5G", "20M", "HT", "2T", "153", "63", + "FCC", "5G", "20M", "HT", "2T", "157", "34", + "ETSI", "5G", "20M", "HT", "2T", "157", "30", + "MKK", "5G", "20M", "HT", "2T", "157", "63", + "FCC", "5G", "20M", "HT", "2T", "161", "34", + "ETSI", "5G", "20M", "HT", "2T", "161", "30", + "MKK", "5G", "20M", "HT", "2T", "161", "63", + "FCC", "5G", "20M", "HT", "2T", "165", "34", + "ETSI", "5G", "20M", "HT", "2T", "165", "30", + "MKK", "5G", "20M", "HT", "2T", "165", "63", + "FCC", "5G", "40M", "HT", "1T", "38", "30", + "ETSI", "5G", "40M", "HT", "1T", "38", "32", + "MKK", "5G", "40M", "HT", "1T", "38", "32", + "FCC", "5G", "40M", "HT", "1T", "46", "30", + "ETSI", "5G", "40M", "HT", "1T", "46", "32", + "MKK", "5G", "40M", "HT", "1T", "46", "32", + "FCC", "5G", "40M", "HT", "1T", "54", "32", + "ETSI", "5G", "40M", "HT", "1T", "54", "32", + "MKK", "5G", "40M", "HT", "1T", "54", "32", + "FCC", "5G", "40M", "HT", "1T", "62", "32", + "ETSI", "5G", "40M", "HT", "1T", "62", "32", + "MKK", "5G", "40M", "HT", "1T", "62", "32", + "FCC", "5G", "40M", "HT", "1T", "102", "28", + "ETSI", "5G", "40M", "HT", "1T", "102", "32", + "MKK", "5G", "40M", "HT", "1T", "102", "32", + "FCC", "5G", "40M", "HT", "1T", "110", "32", + "ETSI", "5G", "40M", "HT", "1T", "110", "32", + "MKK", "5G", "40M", "HT", "1T", "110", "32", + "FCC", "5G", "40M", "HT", "1T", "118", "34", + "ETSI", "5G", "40M", "HT", "1T", "118", "32", + "MKK", "5G", "40M", "HT", "1T", "118", "32", + "FCC", "5G", "40M", "HT", "1T", "126", "34", + "ETSI", "5G", "40M", "HT", "1T", "126", "32", + "MKK", "5G", "40M", "HT", "1T", "126", "32", + "FCC", "5G", "40M", "HT", "1T", "134", "32", + "ETSI", "5G", "40M", "HT", "1T", "134", "32", + "MKK", "5G", "40M", "HT", "1T", "134", "32", + "FCC", "5G", "40M", "HT", "1T", "151", "34", + "ETSI", "5G", "40M", "HT", "1T", "151", "32", + "MKK", "5G", "40M", "HT", "1T", "151", "63", + "FCC", "5G", "40M", "HT", "1T", "159", "34", + "ETSI", "5G", "40M", "HT", "1T", "159", "32", + "MKK", "5G", "40M", "HT", "1T", "159", "63", + "FCC", "5G", "40M", "HT", "2T", "38", "28", + "ETSI", "5G", "40M", "HT", "2T", "38", "30", + "MKK", "5G", "40M", "HT", "2T", "38", "30", + "FCC", "5G", "40M", "HT", "2T", "46", "28", + "ETSI", "5G", "40M", "HT", "2T", "46", "30", + "MKK", "5G", "40M", "HT", "2T", "46", "30", + "FCC", "5G", "40M", "HT", "2T", "54", "30", + "ETSI", "5G", "40M", "HT", "2T", "54", "30", + "MKK", "5G", "40M", "HT", "2T", "54", "30", + "FCC", "5G", "40M", "HT", "2T", "62", "30", + "ETSI", "5G", "40M", "HT", "2T", "62", "30", + "MKK", "5G", "40M", "HT", "2T", "62", "30", + "FCC", "5G", "40M", "HT", "2T", "102", "26", + "ETSI", "5G", "40M", "HT", "2T", "102", "30", + "MKK", "5G", "40M", "HT", "2T", "102", "30", + "FCC", "5G", "40M", "HT", "2T", "110", "30", + "ETSI", "5G", "40M", "HT", "2T", "110", "30", + "MKK", "5G", "40M", "HT", "2T", "110", "30", + "FCC", "5G", "40M", "HT", "2T", "118", "34", + "ETSI", "5G", "40M", "HT", "2T", "118", "30", + "MKK", "5G", "40M", "HT", "2T", "118", "30", + "FCC", "5G", "40M", "HT", "2T", "126", "32", + "ETSI", "5G", "40M", "HT", "2T", "126", "30", + "MKK", "5G", "40M", "HT", "2T", "126", "30", + "FCC", "5G", "40M", "HT", "2T", "134", "30", + "ETSI", "5G", "40M", "HT", "2T", "134", "30", + "MKK", "5G", "40M", "HT", "2T", "134", "30", + "FCC", "5G", "40M", "HT", "2T", "151", "34", + "ETSI", "5G", "40M", "HT", "2T", "151", "30", + "MKK", "5G", "40M", "HT", "2T", "151", "63", + "FCC", "5G", "40M", "HT", "2T", "159", "34", + "ETSI", "5G", "40M", "HT", "2T", "159", "30", + "MKK", "5G", "40M", "HT", "2T", "159", "63", + "FCC", "5G", "80M", "VHT", "1T", "42", "30", + "ETSI", "5G", "80M", "VHT", "1T", "42", "32", + "MKK", "5G", "80M", "VHT", "1T", "42", "32", + "FCC", "5G", "80M", "VHT", "1T", "58", "28", + "ETSI", "5G", "80M", "VHT", "1T", "58", "32", + "MKK", "5G", "80M", "VHT", "1T", "58", "32", + "FCC", "5G", "80M", "VHT", "1T", "106", "30", + "ETSI", "5G", "80M", "VHT", "1T", "106", "32", + "MKK", "5G", "80M", "VHT", "1T", "106", "32", + "FCC", "5G", "80M", "VHT", "1T", "122", "34", + "ETSI", "5G", "80M", "VHT", "1T", "122", "32", + "MKK", "5G", "80M", "VHT", "1T", "122", "32", + "FCC", "5G", "80M", "VHT", "1T", "155", "34", + "ETSI", "5G", "80M", "VHT", "1T", "155", "32", + "MKK", "5G", "80M", "VHT", "1T", "155", "63", + "FCC", "5G", "80M", "VHT", "2T", "42", "28", + "ETSI", "5G", "80M", "VHT", "2T", "42", "30", + "MKK", "5G", "80M", "VHT", "2T", "42", "30", + "FCC", "5G", "80M", "VHT", "2T", "58", "26", + "ETSI", "5G", "80M", "VHT", "2T", "58", "30", + "MKK", "5G", "80M", "VHT", "2T", "58", "30", + "FCC", "5G", "80M", "VHT", "2T", "106", "28", + "ETSI", "5G", "80M", "VHT", "2T", "106", "30", + "MKK", "5G", "80M", "VHT", "2T", "106", "30", + "FCC", "5G", "80M", "VHT", "2T", "122", "32", + "ETSI", "5G", "80M", "VHT", "2T", "122", "30", + "MKK", "5G", "80M", "VHT", "2T", "122", "30", + "FCC", "5G", "80M", "VHT", "2T", "155", "34", + "ETSI", "5G", "80M", "VHT", "2T", "155", "30", + "MKK", "5G", "80M", "VHT", "2T", "155", "63" +}; + +void +ODM_ReadAndConfig_MP_8188F_TXPWR_LMT( + IN PDM_ODM_T pDM_Odm +) +{ + u4Byte i = 0; + u4Byte ArrayLen = sizeof(Array_MP_8188F_TXPWR_LMT)/sizeof(pu1Byte); + pu1Byte *Array = (pu1Byte *)Array_MP_8188F_TXPWR_LMT; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PADAPTER Adapter = pDM_Odm->Adapter; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + PlatformZeroMemory(pHalData->BufOfLinesPwrLmt, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); + pHalData->nLinesReadPwrLmt = ArrayLen/7; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ReadAndConfig_MP_8188F_TXPWR_LMT\n")); + + for (i = 0; i < ArrayLen; i += 7) { + pu1Byte regulation = Array[i]; + pu1Byte band = Array[i+1]; + pu1Byte bandwidth = Array[i+2]; + pu1Byte rate = Array[i+3]; + pu1Byte rfPath = Array[i+4]; + pu1Byte chnl = Array[i+5]; + pu1Byte val = Array[i+6]; + + odm_ConfigBB_TXPWR_LMT_8188F(pDM_Odm, regulation, band, bandwidth, rate, rfPath, chnl, val); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + rsprintf((char *)pHalData->BufOfLinesPwrLmt[i/7], 100, "\"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\", \"%s\",", + regulation, band, bandwidth, rate, rfPath, chnl, val); +#endif + } + +} + +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_rf.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_rf.h new file mode 100644 index 000000000..417b3b856 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halhwimg8188f_rf.h @@ -0,0 +1,79 @@ +/****************************************************************************** +* +* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms of version 2 of the GNU General Public License as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +* +* You should have received a copy of the GNU General Public License along with +* this program; if not, write to the Free Software Foundation, Inc., +* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA +* +* +******************************************************************************/ + +/*Image2HeaderVersion: 2.18*/ +#if (RTL8188F_SUPPORT == 1) +#ifndef __INC_MP_RF_HW_IMG_8188F_H +#define __INC_MP_RF_HW_IMG_8188F_H + + +/****************************************************************************** +* RadioA.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188F_RadioA(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188F_RadioA(void); + +/****************************************************************************** +* TxPowerTrack_AP.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188F_TxPowerTrack_AP(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188F_TxPowerTrack_AP(void); + +/****************************************************************************** +* TxPowerTrack_SDIO.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188F_TxPowerTrack_SDIO(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188F_TxPowerTrack_SDIO(void); + +/****************************************************************************** +* TxPowerTrack_USB.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188F_TxPowerTrack_USB(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188F_TxPowerTrack_USB(void); + +/****************************************************************************** +* TXPWR_LMT.TXT +******************************************************************************/ + +void +ODM_ReadAndConfig_MP_8188F_TXPWR_LMT(/* TC: Test Chip, MP: MP Chip*/ + IN PDM_ODM_T pDM_Odm +); +u4Byte ODM_GetVersion_MP_8188F_TXPWR_LMT(void); + +#endif +#endif /* end of HWIMG_SUPPORT*/ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halphyrf_8188f.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halphyrf_8188f.c new file mode 100644 index 000000000..26e373e00 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halphyrf_8188f.c @@ -0,0 +1,3590 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#define bMaskH3Bytes 0xffffff00 + +//#define SUCCESS 0 +//#define FAIL -1 + + +/*---------------------------Define Local Constant---------------------------*/ +// 2010/04/25 MH Define the max tx power tracking tx agc power. +#define ODM_TXPWRTRACK_MAX_IDX8188F 6 + +// MACRO definition for pRFCalibrateInfo->TxIQC_8188F[0] +#define PATH_S0 1 // RF_PATH_B +#define IDX_0xC94 0 +#define IDX_0xC80 1 +#define IDX_0xC4C 2 +#define IDX_0xC14 0 +#define IDX_0xCA0 1 +#define KEY 0 +#define VAL 1 + +// MACRO definition for pRFCalibrateInfo->TxIQC_8188F[1] +#define PATH_S1 0 // RF_PATH_A +#define IDX_0xC9C 0 +#define IDX_0xC88 1 +#define IDX_0xC4C 2 +#define IDX_0xC1C 0 +#define IDX_0xC78 1 + + + +/*---------------------------Define Local Constant---------------------------*/ + + +//3============================================================ +//3 Tx Power Tracking +//3============================================================ + + +void setIqkMatrix_8188F( + PDM_ODM_T pDM_Odm, + s1Byte OFDM_index, + u1Byte RFPath, + s4Byte IqkResult_X, + s4Byte IqkResult_Y +) +{ + s4Byte ele_A = 0, ele_D, ele_C = 0, value32; + + if (OFDM_index >= OFDM_TABLE_SIZE) + OFDM_index = OFDM_TABLE_SIZE - 1; + else if (OFDM_index < 0) + OFDM_index = 0; + + ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000) >> 22; + + //new element A = element D x X + if ((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) { + if ((IqkResult_X & 0x00000200) != 0) //consider minus + IqkResult_X = IqkResult_X | 0xFFFFFC00; + ele_A = ((IqkResult_X * ele_D) >> 8) & 0x000003FF; + + //new element C = element D x Y + if ((IqkResult_Y & 0x00000200) != 0) + IqkResult_Y = IqkResult_Y | 0xFFFFFC00; + ele_C = ((IqkResult_Y * ele_D) >> 8) & 0x000003FF; + + if (RFPath == ODM_RF_PATH_A) + switch (RFPath) { + case ODM_RF_PATH_A: + //wirte new elements A, C, D to regC80 and regC94, element B is always 0 + value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C & 0x000003C0) >> 6; + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32); + + value32 = ((IqkResult_X * ele_D) >> 7) & 0x01; + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32); + break; + case ODM_RF_PATH_B: + //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 + value32 = (ele_D << 22) | ((ele_C & 0x3F) << 16) | ele_A; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); + + value32 = (ele_C & 0x000003C0) >> 6; + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32); + + value32 = ((IqkResult_X * ele_D) >> 7) & 0x01; + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32); + + break; + default: + break; + } + } else { + switch (RFPath) { + case ODM_RF_PATH_A: + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00); + break; + + case ODM_RF_PATH_B: + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00); + break; + + default: + break; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", + (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y)); +} + +void DoIQK_8188F( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold +) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); +#endif +#if(DM_ODM_SUPPORT_TYPE & ODM_CE) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); +#endif +#endif + + ODM_ResetIQKResult(pDM_Odm); + +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) +#if USE_WORKITEM + PlatformAcquireMutex(&pHalData->mxChnlBwControl); +#else + PlatformAcquireSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); +#endif +#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + PlatformAcquireMutex(&pHalData->mxChnlBwControl); +#endif +#endif + + + pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = ThermalValue; +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_IQCalibrate_8188F(pDM_Odm, FALSE, FALSE); +#else + PHY_IQCalibrate_8188F(Adapter, FALSE, FALSE); +#endif + +#if(DM_ODM_SUPPORT_TYPE & ODM_WIN) +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) +#if USE_WORKITEM + PlatformReleaseMutex(&pHalData->mxChnlBwControl); +#else + PlatformReleaseSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK); +#endif +#elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE)) + PlatformReleaseMutex(&pHalData->mxChnlBwControl); +#endif +#endif +} + +/*----------------------------------------------------------------------------- + * Function: odm_TxPwrTrackSetPwr88E() + * + * Overview: 88E change all channel tx power accordign to flag. + * OFDM & CCK are all different. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 04/23/2012 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +VOID +ODM_TxPwrTrackSetPwr_8188F( + IN PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + u1Byte PwrTrackingLimit_OFDM = 34; //+0dB + u1Byte PwrTrackingLimit_CCK = CCK_TABLE_SIZE_88F-1; //-2dB + u1Byte TxRate = 0xFF; + s1Byte Final_OFDM_Swing_Index = 0; + s1Byte Final_CCK_Swing_Index = 0; +// u1Byte i = 0; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + +#if 0 +#if (MP_DRIVER==1) + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); +#else + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + if (!pMgntInfo->ForcedDataRate) { //auto rate + if (pDM_Odm->TxRate != 0xFF) + TxRate = HwRateToMRate8812(pDM_Odm->TxRate); + } else //force rate + TxRate = (u1Byte) pMgntInfo->ForcedDataRate; +#endif +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("===>ODM_TxPwrTrackSetPwr8188F\n")); + + if (TxRate != 0xFF) { + //2 CCK + if ((TxRate >= MGN_1M) && (TxRate <= MGN_11M)) + PwrTrackingLimit_CCK = CCK_TABLE_SIZE_88F-1; //-2dB + //2 OFDM + else if ((TxRate >= MGN_6M) && (TxRate <= MGN_48M)) + PwrTrackingLimit_OFDM = 36; //+3dB + else if (TxRate == MGN_54M) + PwrTrackingLimit_OFDM = 34; //+2dB + + //2 HT + else if ((TxRate >= MGN_MCS0) && (TxRate <= MGN_MCS2)) //QPSK/BPSK + PwrTrackingLimit_OFDM = 38; //+4dB + else if ((TxRate >= MGN_MCS3) && (TxRate <= MGN_MCS4)) //16QAM + PwrTrackingLimit_OFDM = 36; //+3dB + else if ((TxRate >= MGN_MCS5) && (TxRate <= MGN_MCS7)) //64QAM + PwrTrackingLimit_OFDM = 34; //+2dB + + else + PwrTrackingLimit_OFDM = pRFCalibrateInfo->DefaultOfdmIndex; //Default OFDM index = 30 + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxRate=0x%x, PwrTrackingLimit=%d\n", TxRate, PwrTrackingLimit_OFDM)); + + RT_TRACE(COMP_CMD, DBG_LOUD, ("Method=%d\n", Method)); + + if (Method == TXAGC) + { + //u1Byte rf = 0; +#if (MP_DRIVER == 1) + u4Byte pwr = 0, TxAGC = 0; +#endif + PADAPTER Adapter = pDM_Odm->Adapter; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr8188F CH=%d\n", *(pDM_Odm->pChannel))); + + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + + #if (MP_DRIVER == 1) + if ( (pDM_Odm->mp_mode) == 1) { + pwr = PHY_QueryBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte1); + pwr += pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_A]; + PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr); //CCK 1M + + if (pwr>0x3F) + pwr=0x3F; //add by Mingzhi.Guo 2015-04-10 + else if(pwr <= 0) + pwr=0; + + TxAGC = (pwr<<16)|(pwr<<8)|(pwr); + + PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC); //CCK 2~11M + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr8188F: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); + + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += (pRFCalibrateInfo->BbSwingIdxOfdm[ODM_RF_PATH_A] - pRFCalibrateInfo->BbSwingIdxOfdmBase[ODM_RF_PATH_A]); + TxAGC |= ((pwr << 24) | (pwr << 16) | (pwr << 8) | pwr); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); + // PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); + // PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr8188F: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); + } else +#endif + { + //PHY_SetTxPowerLevelByPath8188F(Adapter, pHalData->CurrentChannel, ODM_RF_PATH_A); + //PHY_SetTxPowerLevel8188F(pDM_Odm->Adapter, *pDM_Odm->pChannel); + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + + if (RFPath == ODM_RF_PATH_A) { + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7); + } + } + +#endif +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + //PHY_RF6052SetCCKTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); + //PHY_RF6052SetOFDMTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel)); +#endif + + } else if (Method == BBSWING) { + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + + // Adjust BB swing by OFDM IQ matrix + if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM) + Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM; + else if (Final_OFDM_Swing_Index <= 0) + Final_OFDM_Swing_Index = 0; + + if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE_88F) + Final_CCK_Swing_Index = CCK_TABLE_SIZE_88F - 1; + else if ((s1Byte)pRFCalibrateInfo->BbSwingIdxCck < 0) + Final_CCK_Swing_Index = 0; + + if (RFPath == ODM_RF_PATH_A) + { + + setIqkMatrix_8188F(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][7]); + ODM_Write1Byte(pDM_Odm, 0xa9a, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][8]); + ODM_Write1Byte(pDM_Odm, 0xa9b, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][9]); + ODM_Write1Byte(pDM_Odm, 0xa9c, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][10]); + ODM_Write1Byte(pDM_Odm, 0xa9d, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][11]); + ODM_Write1Byte(pDM_Odm, 0xaa0, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][12]); + ODM_Write1Byte(pDM_Odm, 0xaa1, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][13]); + ODM_Write1Byte(pDM_Odm, 0xaa2, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][14]); + ODM_Write1Byte(pDM_Odm, 0xaa3, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][15]); + } + + } + else if (Method == MIX_MODE) + { + #if (MP_DRIVER == 1) + //u4Byte pwr = 0, TxAGC = 0; + u4Byte TxAGC=0; //add by Mingzhi.Guo 2015-04-10 + s4Byte pwr=0; + #endif + RT_TRACE(COMP_CMD, DBG_LOUD, ("Method is MIX_MODE ====> \n")); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("pRFCalibrateInfo->DefaultOfdmIndex=%d, pRFCalibrateInfo->DefaultCCKIndex=%d, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", + pRFCalibrateInfo->DefaultOfdmIndex, pRFCalibrateInfo->DefaultCckIndex, pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath],RFPath )); + + Final_OFDM_Swing_Index = pRFCalibrateInfo->DefaultOfdmIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + Final_CCK_Swing_Index = pRFCalibrateInfo->DefaultCckIndex + pRFCalibrateInfo->Absolute_OFDMSwingIdx[RFPath]; + if (RFPath == ODM_RF_PATH_A) { + if (Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM) { //BBSwing higher then Limit + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM; + + setIqkMatrix_8188F(pDM_Odm, PwrTrackingLimit_OFDM, RFPath, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + + //Set TxAGC Page C{}; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n", + PwrTrackingLimit_OFDM, pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } else if (Final_OFDM_Swing_Index < pRFCalibrateInfo->DefaultOfdmIndex) { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - pRFCalibrateInfo->DefaultOfdmIndex; + setIqkMatrix_8188F(pDM_Odm, pRFCalibrateInfo->DefaultOfdmIndex, ODM_RF_PATH_A, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA = TRUE; + /* Set TxAGC Page C{}; */ + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A Lower then BBSwing lower bound 28 , Remnant TxAGC Value = %d\n", + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } + + /* + else if (Final_OFDM_Swing_Index < 0) + { + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index ; + setIqkMatrix_8188F(pDM_Odm, 0, ODM_RF_PATH_A, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA=TRUE; + //Set TxAGC Page C{}; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d\n", + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath])); + } + */ + else { + setIqkMatrix_8188F(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, + ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d\n", Final_OFDM_Swing_Index)); + + if (pRFCalibrateInfo->Modify_TxAGC_Flag_PathA) { //If TxAGC has changed, reset TxAGC again + pRFCalibrateInfo->Remnant_OFDMSwingIdx[RFPath] = 0; + } + } + #if (MP_DRIVER == 1) && (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + if ( (pDM_Odm->mp_mode) == 1) { + pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF); + pwr += (pRFCalibrateInfo->Remnant_OFDMSwingIdx[ODM_RF_PATH_A] - pRFCalibrateInfo->Modify_TxAGC_Value_OFDM); + + if (pwr>0x3F) pwr=0x3F; //add by Mingzhi.Guo 2015-04-10 + else if(pwr<0) pwr=0; + + TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); + //PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); + //PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr8188F: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC)); + + + } + else + #endif + { + //Set TxAGC Page C{}; + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM ); + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 ); + } + pRFCalibrateInfo->Modify_TxAGC_Value_OFDM=pRFCalibrateInfo->Remnant_OFDMSwingIdx[ODM_RF_PATH_A] ; //add by Mingzhi.Guo + + + //MIX mode: CCK + if(Final_CCK_Swing_Index > PwrTrackingLimit_CCK) + { + pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d \n", PwrTrackingLimit_CCK, pRFCalibrateInfo->Remnant_CCKSwingIdx)); + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch14_88F[PwrTrackingLimit_CCK][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch14_88F[PwrTrackingLimit_CCK][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch14_88F[PwrTrackingLimit_CCK][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch14_88F[PwrTrackingLimit_CCK][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch14_88F[PwrTrackingLimit_CCK][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch14_88F[PwrTrackingLimit_CCK][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch14_88F[PwrTrackingLimit_CCK][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch14_88F[PwrTrackingLimit_CCK][7]); + ODM_Write1Byte(pDM_Odm, 0xa9a, CCKSwingTable_Ch1_Ch14_88F[PwrTrackingLimit_CCK][8]); + ODM_Write1Byte(pDM_Odm, 0xa9b, CCKSwingTable_Ch1_Ch14_88F[PwrTrackingLimit_CCK][9]); + ODM_Write1Byte(pDM_Odm, 0xa9c, CCKSwingTable_Ch1_Ch14_88F[PwrTrackingLimit_CCK][10]); + ODM_Write1Byte(pDM_Odm, 0xa9d, CCKSwingTable_Ch1_Ch14_88F[PwrTrackingLimit_CCK][11]); + ODM_Write1Byte(pDM_Odm, 0xaa0, CCKSwingTable_Ch1_Ch14_88F[PwrTrackingLimit_CCK][12]); + ODM_Write1Byte(pDM_Odm, 0xaa1, CCKSwingTable_Ch1_Ch14_88F[PwrTrackingLimit_CCK][13]); + ODM_Write1Byte(pDM_Odm, 0xaa2, CCKSwingTable_Ch1_Ch14_88F[PwrTrackingLimit_CCK][14]); + ODM_Write1Byte(pDM_Odm, 0xaa3, CCKSwingTable_Ch1_Ch14_88F[PwrTrackingLimit_CCK][15]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + + } + else if(Final_CCK_Swing_Index < 0) // Lowest CCK Index = 0 + { + pRFCalibrateInfo->Remnant_CCKSwingIdx = Final_CCK_Swing_Index; + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pRFCalibrateInfo->Remnant_CCKSwingIdx = %d \n", 0, pRFCalibrateInfo->Remnant_CCKSwingIdx)); + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch14_88F[0][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch14_88F[0][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch14_88F[0][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch14_88F[0][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch14_88F[0][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch14_88F[0][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch14_88F[0][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch14_88F[0][7]); + ODM_Write1Byte(pDM_Odm, 0xa9a, CCKSwingTable_Ch1_Ch14_88F[0][8]); + ODM_Write1Byte(pDM_Odm, 0xa9b, CCKSwingTable_Ch1_Ch14_88F[0][9]); + ODM_Write1Byte(pDM_Odm, 0xa9c, CCKSwingTable_Ch1_Ch14_88F[0][10]); + ODM_Write1Byte(pDM_Odm, 0xa9d, CCKSwingTable_Ch1_Ch14_88F[0][11]); + ODM_Write1Byte(pDM_Odm, 0xaa0, CCKSwingTable_Ch1_Ch14_88F[0][12]); + ODM_Write1Byte(pDM_Odm, 0xaa1, CCKSwingTable_Ch1_Ch14_88F[0][13]); + ODM_Write1Byte(pDM_Odm, 0xaa2, CCKSwingTable_Ch1_Ch14_88F[0][14]); + ODM_Write1Byte(pDM_Odm, 0xaa3, CCKSwingTable_Ch1_Ch14_88F[0][15]); + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK = TRUE; + + } + + else + { + ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d \n", Final_CCK_Swing_Index)); + ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][0]); + ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][1]); + ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][2]); + ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][3]); + ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][4]); + ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][5]); + ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][6]); + ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][7]); + ODM_Write1Byte(pDM_Odm, 0xa9a, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][8]); + ODM_Write1Byte(pDM_Odm, 0xa9b, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][9]); + ODM_Write1Byte(pDM_Odm, 0xa9c, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][10]); + ODM_Write1Byte(pDM_Odm, 0xa9d, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][11]); + ODM_Write1Byte(pDM_Odm, 0xaa0, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][12]); + ODM_Write1Byte(pDM_Odm, 0xaa1, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][13]); + ODM_Write1Byte(pDM_Odm, 0xaa2, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][14]); + ODM_Write1Byte(pDM_Odm, 0xaa3, CCKSwingTable_Ch1_Ch14_88F[Final_CCK_Swing_Index][15]); + + pRFCalibrateInfo->Modify_TxAGC_Flag_PathA_CCK=FALSE; + pRFCalibrateInfo->Remnant_CCKSwingIdx = 0; + + } + #if (MP_DRIVER == 1) && (DM_ODM_SUPPORT_TYPE & (ODM_WIN)) + if ( (pDM_Odm->mp_mode) == 1) { + pwr = PHY_QueryBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte1); + pwr +=pRFCalibrateInfo->Remnant_CCKSwingIdx-pRFCalibrateInfo->Modify_TxAGC_Value_CCK; + + if (pwr>0x3F) pwr=0x3F; //add by Mingzhi.Guo 2015-04-10 + else if(pwr<0) pwr=0; + + PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr); //CCK 1M + TxAGC = (pwr<<16)|(pwr<<8)|(pwr); + PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC); //CCK 2~11M + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("ODM_TxPwrTrackSetPwr8188F: CCK Tx-rf(A) Power = 0x%x\n", TxAGC)); + } + else + #endif + { + //Set TxAGC Page C{}; + PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK ); + } + pRFCalibrateInfo->Modify_TxAGC_Value_CCK = pRFCalibrateInfo->Remnant_CCKSwingIdx; + + } + } + else + return; +} // odm_TxPwrTrackSetPwr8188F + + +VOID +GetDeltaSwingTable_8188F( + IN PVOID pDM_VOID, + OUT pu1Byte *TemperatureUP_A, + OUT pu1Byte *TemperatureDOWN_A, + OUT pu1Byte *TemperatureUP_B, + OUT pu1Byte *TemperatureDOWN_B +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + u1Byte TxRate = 0xFF; + u1Byte channel = pHalData->CurrentChannel; + + if (pDM_Odm->mp_mode == TRUE) { + #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + #if (MP_DRIVER == 1) + PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + PMPT_CONTEXT pMptCtx = &(Adapter->mppriv.MptCtx); + + TxRate = MptToMgntRate(pMptCtx->MptRateIndex); + #endif + #endif + } else { + u2Byte rate = *(pDM_Odm->pForcedDataRate); + + if (!rate) { /*auto rate*/ + if (rate != 0xFF) { + #if (DM_ODM_SUPPORT_TYPE & ODM_WIN) + TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate); + #elif (DM_ODM_SUPPORT_TYPE & ODM_CE) + TxRate = HwRateToMRate(pDM_Odm->TxRate); + #endif + } + } else { /*force rate*/ + TxRate = (u1Byte)rate; + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("Power Tracking TxRate=0x%X\n", TxRate)); + + + RT_TRACE(COMP_CMD, DBG_LOUD, ("GetDeltaSwingTable_8188F ====> channel is %d\n", channel)); + + if ( 1 <= channel && channel <= 14) { + if (IS_CCK_RATE(TxRate)) { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; + } else { + *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; + *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; + *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; + *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; + } + } else { + *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E; + *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E; + } + + return; +} + + +void ConfigureTxpowerTrack_8188F( + PTXPWRTRACK_CFG pConfig +) +{ + RT_TRACE(COMP_CMD, DBG_LOUD, ("ConfigureTxpowerTrack_8188F ====> \n")); + pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE_88F; + pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE; + pConfig->Threshold_IQK = IQK_THRESHOLD; + pConfig->AverageThermalNum = AVG_THERMAL_NUM_8188F; + pConfig->RfPathCount = MAX_PATH_NUM_8188F; + pConfig->ThermalRegAddr = RF_T_METER_8188F; + + pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr_8188F; + pConfig->DoIQK = DoIQK_8188F; + pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8188F; + pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8188F; +} + +//1 7. IQK +#define MAX_TOLERANCE 5 +#define IQK_DELAY_TIME 1 //ms + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathA_IQK_8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB +) +{ + u4Byte regEAC, regE94, regE9C/*, regEA4*/; + u1Byte result = 0x00; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n")); + + // enable path A PA in TXIQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0x07ff7); //0x07f77 + //PA,PAD gain adjust + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x5102a); //0x5111e0 + + + //enter IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + + + //1 Tx IQK + //path-A IQK setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n")); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x821403ff); //0x821403e0 + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + + //One shot, path A LOK & IQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8188F)); +//PlatformStallExecution(IQK_DELAY_TIME_8188F*1000); + ODM_delay_ms(IQK_DELAY_TIME_8188F); + + //reload RF 0xdf + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180); + + //save LOK result + pDM_Odm->RFCalibrateInfo.LOK_Result = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8, bRFRegOffsetMask); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); + //monitor image power before & after IQK + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + if (!(regEAC & BIT28) && + (((regE94 & 0x03FF0000) >> 16) != 0x142) && + (((regE9C & 0x03FF0000) >> 16) != 0x42)) + result |= 0x01; + + return result; + + +} + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathA_RxIQK8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB +) +{ + u4Byte regEAC, regE94, regE9C, regEA4, u4tmp; + u1Byte result = 0x00; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n")); + + //1 Get TXIMR setting + //modify RXIQK mode table +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf1173); //0xf117b + + //PA,PAD gain adjust + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x5102a); //0x510f0 + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-A IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160fff); //0x821603e0 + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + + //One shot, path A LOK & IQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8188F)); +//PlatformStallExecution(IQK_DELAY_TIME_8188F*1000); + ODM_delay_ms(IQK_DELAY_TIME_8188F); + + + //reload RF 0xdf + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180); + + + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); + //monitor image power before & after IQK + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + if (!(regEAC & BIT28) && + (((regE94 & 0x03FF0000) >> 16) != 0x142) && + (((regE9C & 0x03FF0000) >> 16) != 0x42)) + result |= 0x01; + else //if Tx not OK, ignore Rx + return result; + + u4tmp = 0x80007C00 | (regE94 & 0x3FF0000) | ((regE9C & 0x3FF0000) >> 16); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x\n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); + + + //1 RX IQK + //modify RXIQK mode table +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); // 0xEF[19] = 0x1 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); // 0x30[19:0] = 0x18000 + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f); // 0x31[19:0] = 0x0000f + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ff2); // 0x32[19:0] = 0xf7ffa + + //PA,PAD gain adjust + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000); //0x51000 + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-A IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x30008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160000); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x281613ff); //0x281603e0 + + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + //One shot, path A LOK & IQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8188F)); +//PlatformStallExecution(IQK_DELAY_TIME_8188F*1000); + ODM_delay_ms(IQK_DELAY_TIME_8188F); + + //reload RF 0xdf + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180); + + //reload LOK value + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.LOK_Result); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEA4 = ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC)); + //monitor image power before & after IQK + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xea0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xea8, bMaskDWord))); + + + if (!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK + (((regEA4 & 0x03FF0000) >> 16) != 0x132) && + (((regEAC & 0x03FF0000) >> 16) != 0x36)) + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n")); + + return result; + + +} + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathB_IQK_8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif +) +{ + u4Byte regEAC, regE94, regE9C/*, regEC4, regECC*/; + u1Byte result = 0x00; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n")); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + //switch to path B + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, 0x00000080); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xefff0); + // in TXIQK mode +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 ); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000 ); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f ); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87 ); +// enable path B PA in TXIQK mode +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xed, bRFRegOffsetMask, 0x00020 ); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40fc1 ); + + + //1 Tx IQK + //path-A IQK setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B IQK setting!\n")); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82140102); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000); + + //LO calibration setting +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); + + + //enter IQK mode + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + + //One shot, path B LOK & IQK +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); + + // delay x ms +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_8188F)); +//PlatformStallExecution(IQK_DELAY_TIME_8188F*1000); + ODM_delay_ms(IQK_DELAY_TIME_8188F); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0x948 = 0x%x\n", ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord))); + + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord); + regE9C = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); + //monitor image power before & after IQK + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xe90, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xe98, bMaskDWord))); + + + if (!(regEAC & BIT28) && + (((regE94 & 0x03FF0000) >> 16) != 0x142) && + (((regE9C & 0x03FF0000) >> 16) != 0x42)) + result |= 0x01; + else + return result; +#if 0 + if (!(regEAC & BIT30) && + (((regEC4 & 0x03FF0000) >> 16) != 0x132) && + (((regECC & 0x03FF0000) >> 16) != 0x36)) + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n")); + +#endif + return result; +} + + + +u1Byte //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK +phy_PathB_RxIQK8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN configPathB +) +{ + u4Byte regEAC, regEB4, regEBC, regECC, regEC4, u4tmp; + u1Byte result = 0x00; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK!\n")); + + //1 Get TXIMR setting + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Get RXIQK TXIMR!\n")); + //modify RXIQK mode table +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); +// ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 ); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 ); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f ); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf117B ); +// ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800); + + //path-B IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x10008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x30008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82130804); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x68130000); + + //LO calibration setting + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + //One shot, path B LOK & IQK + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000002); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000000); + + // delay x ms + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8188F)); + //PlatformStallExecution(IQK_DELAY_TIME_8188F*1000); + ODM_delay_ms(IQK_DELAY_TIME_8188F); + + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord); + regEBC = ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb4 = 0x%x, 0xebc = 0x%x\n", regEB4, regEBC)); + //monitor image power before & after IQK + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeb0(before IQK)= 0x%x, 0xeb8(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xeb0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xeb8, bMaskDWord))); + + + if (!(regEAC & BIT31) && + (((regEB4 & 0x03FF0000) >> 16) != 0x142) && + (((regEBC & 0x03FF0000) >> 16) != 0x42)) + result |= 0x01; + else //if Tx not OK, ignore Rx + return result; + + u4tmp = 0x80007C00 | (regEB4 & 0x3FF0000) | ((regEBC & 0x3FF0000) >> 16); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x\n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp)); + + + //1 RX IQK + //modify RXIQK mode table +// ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n")); +// ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 ); + + //<20121009, Kordan> RF Mode = 3 +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); // 0xEF[19] = 0x1 +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000 ); // 0x30[19:0] = 0x18000 +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f ); // 0x31[19:0] = 0x0000f +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa ); // 0x32[19:0] = 0xf7ffa +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); // 0xEF[19] = 0x0 +// ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + + //IQK setting + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + //path-B IQK setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x30008c1c); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x10008c1c); + ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_B, bMaskDWord, 0x82130c05); + ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_B, bMaskDWord, 0x68130c05); + + //LO calibration setting + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); + + //One shot, path B LOK & IQK + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000002); + ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000000); + + // delay x ms + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8188F)); + //PlatformStallExecution(IQK_DELAY_TIME_8188F*1000); + ODM_delay_ms(IQK_DELAY_TIME_8188F); + + // Check failed + regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord); + regEC4 = ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord);; + regECC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec4 = 0x%x, 0xecc = 0x%x\n", regEC4, regECC)); + //monitor image power before & after IQK + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec0(before IQK)= 0x%x, 0xec8(afer IQK) = 0x%x\n", + ODM_GetBBReg(pDM_Odm, 0xec0, bMaskDWord), ODM_GetBBReg(pDM_Odm, 0xec8, bMaskDWord))); + + // PA/PAD controlled by 0x0 + //leave IQK mode +// ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); +// ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180 ); + + + +#if 0 + if (!(regEAC & BIT31) && + (((regEB4 & 0x03FF0000) >> 16) != 0x142) && + (((regEBC & 0x03FF0000) >> 16) != 0x42)) + result |= 0x01; + else //if Tx not OK, ignore Rx + return result; +#endif + + if (!(regEAC & BIT30) && //if Tx is OK, check whether Rx is OK + (((regEC4 & 0x03FF0000) >> 16) != 0x132) && + (((regECC & 0x03FF0000) >> 16) != 0x36)) + result |= 0x02; + else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n")); + + return result; + + +} + + +VOID +_PHY_PathAFillIQKMatrix8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly +) +{ + u4Byte Oldval_0, X, TX0_A, reg; + s4Byte Y, TX0_C; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n", (bIQKOK) ? "Success" : "Failed")); + + if (final_candidate == 0xFF) + return; + + else if (bIQKOK) { + Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][0]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX0_A = (X * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X * Oldval_0 >> 7) & 0x1)); + + Y = result[final_candidate][1]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + //2 Tx IQC + TX0_C = (Y * Oldval_0) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); + ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C & 0x3C0) >> 6)); + pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY] = rOFDM0_XCTxAFE; + pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskDWord); + + ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C & 0x3F)); + pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance; + pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y * Oldval_0 >> 7) & 0x1)); + pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold; + pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord); + + if (bTxOnly) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix8188F only Tx OK\n")); + + // <20130226, Kordan> Saving RxIQC, otherwise not initialized. + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord); + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, bMaskDWord); + return; + } + + reg = result[final_candidate][2]; +#if (DM_ODM_SUPPORT_TYPE==ODM_AP) + if (RTL_ABS(reg, 0x100) >= 16) + reg = 0x100; +#endif + + //2 Rx IQC + ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg); + reg = result[final_candidate][3] & 0x3F; + ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg); + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, bMaskDWord); + + reg = (result[final_candidate][3] >> 6) & 0xF; + ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg); + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; + pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, bMaskDWord); + + } +} + +VOID +_PHY_PathBFillIQKMatrix8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bIQKOK, + IN s4Byte result[][8], + IN u1Byte final_candidate, + IN BOOLEAN bTxOnly //do Tx only +) +{ + u4Byte Oldval_1, X, TX1_A, reg; + s4Byte Y, TX1_C; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n", (bIQKOK) ? "Success" : "Failed")); + + if (final_candidate == 0xFF) + return; + + else if (bIQKOK) { + Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; + + X = result[final_candidate][4]; + if ((X & 0x00000200) != 0) + X = X | 0xFFFFFC00; + TX1_A = (X * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); + + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X * Oldval_1 >> 7) & 0x1)); + + Y = result[final_candidate][5]; + if ((Y & 0x00000200) != 0) + Y = Y | 0xFFFFFC00; + + TX1_C = (Y * Oldval_1) >> 8; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); + + //2 Tx IQC + ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C & 0x3C0) >> 6)); + pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][KEY] = rOFDM0_XDTxAFE; + pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskDWord); + + ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C & 0x3F)); + pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC88][KEY] = rOFDM0_XBTxIQImbalance; + pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC88][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord); + + ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y * Oldval_1 >> 7) & 0x1)); + pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold; + pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, bMaskDWord); + + if (bTxOnly) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathBFillIQKMatrix8188F only Tx OK\n")); + + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC1C][KEY] = rOFDM0_XBRxIQImbalance; + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC1C][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, bMaskDWord); + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC78][KEY] = rOFDM0_AGCRSSITable; + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC78][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, bMaskDWord); + return; + } + + //2 Rx IQC + reg = result[final_candidate][6]; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg); + reg = result[final_candidate][7] & 0x3F; + ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg); + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC1C][KEY] = rOFDM0_XBRxIQImbalance; + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC1C][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, bMaskDWord); + + reg = (result[final_candidate][7] >> 6) & 0xF; + ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg); + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC78][KEY] = rOFDM0_AGCRSSITable; + pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC78][VAL] = ODM_GetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, bMaskDWord); + } +} + +// +// 2011/07/26 MH Add an API for testing IQK fail case. +// +// MP Already declare in odm.c +#if !(DM_ODM_SUPPORT_TYPE & ODM_WIN) +BOOLEAN +ODM_CheckPowerStatus( + IN PADAPTER Adapter) +{ + /* + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + RT_RF_POWER_STATE rtState; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + + // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence. + if (pMgntInfo->init_adpt_in_progress == TRUE) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter")); + return TRUE; + } + + // + // 2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK. + // + Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState)); + if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff) + { + ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", + Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState)); + return FALSE; + } + */ + return TRUE; +} +#endif + +VOID +_PHY_SaveADDARegisters8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum +) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif + + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); + for (i = 0; i < RegisterNum; i++) + ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord); +} + + +VOID +_PHY_SaveMACRegisters8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup +) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); + for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) + MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]); + MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]); + +} + + +VOID +_PHY_ReloadADDARegisters8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegiesterNum +) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); + for (i = 0; i < RegiesterNum; i++) + ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]); +} + +VOID +_PHY_ReloadMACRegisters8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup +) +{ + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload MAC parameters !\n")); + for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]); + ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]); +} + + +VOID +_PHY_PathADDAOn8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T +) +{ + u4Byte pathOn; + u4Byte i; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); + + pathOn = isPathAOn ? 0x03c00014 : 0x03c00014; + if (FALSE == is2T) { + pathOn = 0x03c00014; + ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x03c00014); + } else + ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, pathOn); + + for (i = 1; i < IQK_ADDA_REG_NUM; i++) + ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, pathOn); + +} + +VOID +_PHY_MACSettingCalibration8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup +) +{ + u4Byte i = 0; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); + +#if 0 + ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F); + + for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++) + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i] & (~BIT3))); + ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i] & (~BIT5))); +#else + + ODM_SetBBReg(pDM_Odm, 0x520, 0x00ff0000, 0xff); +#endif +} + +VOID +_PHY_PathAStandBy8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif +) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A standby mode!\n")); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); +//Allen + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + //ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000); +// + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); +} + +VOID +_PHY_PIModeSwitch8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN PIMode +) +{ + u4Byte mode; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI"))); + + mode = PIMode ? 0x01000100 : 0x01000000; + ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode); + ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode); +} + +BOOLEAN +phy_SimularityCompare_8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s4Byte result[][8], + IN u1Byte c1, + IN u1Byte c2 +) +{ + u4Byte i, j, diff, SimularityBitMap, bound = 0; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +#if DBG + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif +#endif + u1Byte final_candidate[2] = { 0xFF, 0xFF }; //for path A and path B + BOOLEAN bResult = TRUE; +//#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +// BOOLEAN is2T = IS_92C_SERIAL( pHalData->VersionID); +//#else + BOOLEAN is2T = TRUE; +//#endif + + s4Byte tmp1 = 0, tmp2 = 0; + + if (is2T) + bound = 8; + else + bound = 4; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8192E c1 %d c2 %d!!!\n", c1, c2)); + + + SimularityBitMap = 0; + + for (i = 0; i < bound; i++) { + + if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) { + if ((result[c1][i] & 0x00000200) != 0) + tmp1 = result[c1][i] | 0xFFFFFC00; + else + tmp1 = result[c1][i]; + + if ((result[c2][i] & 0x00000200) != 0) + tmp2 = result[c2][i] | 0xFFFFFC00; + else + tmp2 = result[c2][i]; + } else { + tmp1 = result[c1][i]; + tmp2 = result[c2][i]; + } + + diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); + + if (diff > MAX_TOLERANCE) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:differnece overflow %d index %d compare1 0x%x compare2 0x%x!!!\n", diff, i, result[c1][i], result[c2][i])); + + if ((i == 2 || i == 6) && !SimularityBitMap) { + if (result[c1][i] + result[c1][i + 1] == 0) + final_candidate[(i / 4)] = c2; + else if (result[c2][i] + result[c2][i + 1] == 0) + final_candidate[(i / 4)] = c1; + else + SimularityBitMap = SimularityBitMap | (1 << i); + } else + SimularityBitMap = SimularityBitMap | (1 << i); + } + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8192E SimularityBitMap %x !!!\n", SimularityBitMap)); + + if (SimularityBitMap == 0) { + for (i = 0; i < (bound / 4); i++) { + if (final_candidate[i] != 0xFF) { + for (j = i * 4; j < (i + 1) * 4 - 2; j++) result[3][j] = result[final_candidate[i]][j]; + bResult = FALSE; + } + } + return bResult; + } else { + + if (!(SimularityBitMap & 0x03)) { //path A TX OK + for (i = 0; i < 2; i++) result[3][i] = result[c1][i]; + } + + if (!(SimularityBitMap & 0x0c)) { //path A RX OK + for (i = 2; i < 4; i++) result[3][i] = result[c1][i]; + } + + if (!(SimularityBitMap & 0x30)) { //path B TX OK + for (i = 4; i < 6; i++) result[3][i] = result[c1][i]; + + } + + if (!(SimularityBitMap & 0xc0)) { //path B RX OK + for (i = 6; i < 8; i++) result[3][i] = result[c1][i]; + } + return FALSE; + } +} + + + +VOID +phy_IQCalibrate_8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s4Byte result[][8], + IN u1Byte t, + IN BOOLEAN is2T +) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + u4Byte i; + u1Byte PathAOK, PathBOK; + u1Byte tmp0xc50 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC50, bMaskByte0); + u1Byte tmp0xc58 = (u1Byte)ODM_GetBBReg(pDM_Odm, 0xC58, bMaskByte0); + u4Byte ADDA_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN + }; + u4Byte IQK_MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG + }; + + //since 92C & 92D have the different define in IQK_BB_REG + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD + }; + + u4Byte Path_SEL_BB, Path_SEL_RF; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) + u4Byte retryCount = 2; +#else +#if MP_DRIVER + const u4Byte retryCount = 9; +#else + const u4Byte retryCount = 2; +#endif +#endif + + // Note: IQ calibration must be performed after loading + // PHY_REG.txt , and radio_a, radio_b.txt + + //u4Byte bbvalue; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_AP)) +#ifdef MP_TEST + if (pDM_Odm->priv->pshare->rf_ft_var.mp_specific) + retryCount = 9; +#endif +#endif + + + if (t == 0) { +// bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord); +// RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188F()==>0x%08x\n",bbvalue)); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); + + // Save ADDA parameters, turn Path A ADDA on +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveADDARegisters8188F(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters8188F(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + _PHY_SaveADDARegisters8188F(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#else + _PHY_SaveADDARegisters8188F(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + _PHY_SaveMACRegisters8188F(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + _PHY_SaveADDARegisters8188F(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#endif + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + _PHY_PathADDAOn8188F(pAdapter, ADDA_REG, TRUE, is2T); +#else + _PHY_PathADDAOn8188F(pDM_Odm, ADDA_REG, TRUE, is2T); +#endif + + + if (t == 0) + pDM_Odm->RFCalibrateInfo.bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8)); + +#if 0 + if (!pDM_Odm->RFCalibrateInfo.bRfPiEnable) { + // Switch BB to PI mode to do IQ Calibration. +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PIModeSwitch8188F(pAdapter, TRUE); +#else + _PHY_PIModeSwitch8188F(pDM_Odm, TRUE); +#endif + } +#endif + + //save RF path + Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); + Path_SEL_RF = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff); + + + //BB setting + /*ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00);*/ + ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); + ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); + ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x25204000); + + //external switch control +// ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); +// ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); +// ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); +// ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); + + + if (is2T) { + //Allen + // ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000); + // ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); + } + + //MAC settings +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration8188F(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); +#else + _PHY_MACSettingCalibration8188F(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); +#endif + + + //Page B init + //AP or IQK +// ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000); + + if (is2T) { +// ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x0f600000); + } + + // IQ calibration setting + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x808000); + ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800); + + for (i = 0; i < retryCount; i++) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathAOK = phy_PathA_IQK_8188F(pAdapter, is2T); +#else + PathAOK = phy_PathA_IQK_8188F(pDM_Odm, is2T); +#endif +// if(PathAOK == 0x03){ + if (PathAOK == 0x01) { //Path A Tx IQK Success + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x8, bRFRegOffsetMask); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n")); + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; + break; + } +#if 0 + else if (i == (retryCount - 1) && PathAOK == 0x01) { //Tx IQK OK + RT_DISP(FINIT, INIT_IQK, ("Path A IQK Only Tx Success!!\n")); + + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; + } +#endif + } + +//bypass RXQIK +#if 1 + + for (i = 0; i < retryCount; i++) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathAOK = phy_PathA_RxIQK8188F(pAdapter, is2T); +#else + PathAOK = phy_PathA_RxIQK8188F(pDM_Odm, is2T); +#endif + if (PathAOK == 0x03) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n")); +// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; +// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord) & 0x3FF0000) >> 16; + result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord) & 0x3FF0000) >> 16; + break; + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n")); + } +#endif + + + if (0x00 == PathAOK) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n")); + + if (is2T) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PathAStandBy8188F(pAdapter); + + // Turn Path B ADDA on + _PHY_PathADDAOn8188F(pAdapter, ADDA_REG, FALSE, is2T); +#else + _PHY_PathAStandBy8188F(pDM_Odm); + + // Turn Path B ADDA on + _PHY_PathADDAOn8188F(pDM_Odm, ADDA_REG, FALSE, is2T); +#endif +//Allen + for (i = 0; i < retryCount; i++) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathBOK = phy_PathB_IQK_8188F(pAdapter); +#else + PathBOK = phy_PathB_IQK_8188F(pDM_Odm); +#endif +// if(PathBOK == 0x03){ + if (PathBOK == 0x01) { //Path B Tx IQK Success + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_B] = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x8, bRFRegOffsetMask); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Tx IQK Success!!\n")); + result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; + result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord) & 0x3FF0000) >> 16; + break; + } +#if 0 + else if (i == (retryCount - 1) && PathAOK == 0x01) { //Tx IQK OK + RT_DISP(FINIT, INIT_IQK, ("Path B IQK Only Tx Success!!\n")); + + result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; + result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord) & 0x3FF0000) >> 16; + } +#endif + } + +//bypass RXQIK +#if 0 + + for (i = 0; i < retryCount; i++) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PathBOK = phy_PathB_RxIQK8188F(pAdapter, is2T); +#else + PathBOK = phy_PathB_RxIQK8188F(pDM_Odm, is2T); +#endif + if (PathBOK == 0x03) { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Success!!\n")); +// result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; +// result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; + result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord) & 0x3FF0000) >> 16; + result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord) & 0x3FF0000) >> 16; + break; + } else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Fail!!\n")); + } + +#endif + +////////Allen end ///////// + if (0x00 == PathBOK) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n")); + } + + //Back to BB mode, load original value + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n")); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0); + + if (t != 0) { + if (!pDM_Odm->RFCalibrateInfo.bRfPiEnable) { + // Switch back BB to SI mode after finish IQ Calibration. +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PIModeSwitch8188F(pAdapter, FALSE); +#else + _PHY_PIModeSwitch8188F(pDM_Odm, FALSE); +#endif + } +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + // Reload ADDA power saving parameters + _PHY_ReloadADDARegisters8188F(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + + // Reload MAC parameters + _PHY_ReloadMACRegisters8188F(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + + _PHY_ReloadADDARegisters8188F(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#else + // Reload ADDA power saving parameters + _PHY_ReloadADDARegisters8188F(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); + + // Reload MAC parameters + _PHY_ReloadMACRegisters8188F(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); + + _PHY_ReloadADDARegisters8188F(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); +#endif + + + //Reload RF path + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); + + //Allen initial gain 0xc50 + // Restore RX initial gain + ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, 0x50); + ODM_SetBBReg(pDM_Odm, 0xc50, bMaskByte0, tmp0xc50); + if (is2T) { + ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, 0x50); + ODM_SetBBReg(pDM_Odm, 0xc58, bMaskByte0, tmp0xc58); + } + + //load 0xe30 IQC default value + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8188F() <==\n")); + +} + + +VOID +phy_LCCalibrate_8188F( + IN PDM_ODM_T pDM_Odm, + IN BOOLEAN is2T +) +{ + u1Byte tmpReg; + u4Byte RF_Amode = 0, RF_Bmode = 0, LC_Cal, cnt; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PADAPTER pAdapter = pDM_Odm->Adapter; +#endif + + /*Check continuous TX and Packet TX*/ + tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03); + + if ((tmpReg & 0x70) != 0) /*Deal with contisuous TX case*/ + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg & 0x8F); /*disable all continuous TX*/ + else /* Deal with Packet TX case*/ + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF); /* block all queues*/ + + + /*backup RF0x18*/ + LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); + + /*Start LCK*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal|0x08000); + + for(cnt=0;cnt<100;cnt++) + { + if(ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x8000) != 0x1) + break; + ODM_delay_ms(10); + } + + /*Recover channel number*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, LC_Cal); + + + /*Restore original situation*/ + if ((tmpReg&0x70) != 0) { + /*Deal with contisuous TX case*/ + ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg); + } else { + /* Deal with Packet TX case*/ + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00); + } + +} + +//Analog Pre-distortion calibration +#define APK_BB_REG_NUM 8 +#define APK_CURVE_REG_NUM 4 +#define PATH_NUM 2 + +VOID +phy_APCalibrate_8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PADAPTER pAdapter, +#else + IN PDM_ODM_T pDM_Odm, + IN PADAPTER pAdapter, +#endif + IN s1Byte delta, + IN BOOLEAN is2T +) +{ +#if 0 +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) && (DBG != 0) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + +#if MP_DRIVER == 1 +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + u4Byte regD[PATH_NUM]; +#endif + u4Byte tmpReg, index, offset, apkbound; + u1Byte path, i; + u1Byte pathbound = PATH_NUM; + u4Byte BB_backup[APK_BB_REG_NUM]; + u4Byte BB_REG[APK_BB_REG_NUM] = { + rFPGA1_TxBlock, rOFDM0_TRxPathEnable, + rFPGA0_RFMOD, rOFDM0_TRMuxPar, + rFPGA0_XCD_RFInterfaceSW, rFPGA0_XAB_RFInterfaceSW, + rFPGA0_XA_RFInterfaceOE, rFPGA0_XB_RFInterfaceOE + }; + u4Byte BB_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x00204000 + }; + u4Byte BB_normal_AP_MODE[APK_BB_REG_NUM] = { + 0x00000020, 0x00a05430, 0x02040000, + 0x000800e4, 0x22204000 + }; + + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN + }; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG + }; + + u4Byte APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, + {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} + }; + + u4Byte APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { + {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings + {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} + }; + + u4Byte APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, + {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} + }; + + u4Byte APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings + {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} + }; + + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4 + }; //path A on path B off / path A off path B on + + u4Byte APK_offset[PATH_NUM] = { + rConfig_AntA, rConfig_AntB + }; + + u4Byte APK_normal_offset[PATH_NUM] = { + rConfig_Pmpd_AntA, rConfig_Pmpd_AntB + }; + + u4Byte APK_value[PATH_NUM] = { + 0x92fc0000, 0x12fc0000 + }; + + u4Byte APK_normal_value[PATH_NUM] = { + 0x92680000, 0x12680000 + }; + + s1Byte APK_delta_mapping[APK_BB_REG_NUM][13] = { + { -4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + { -4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + { -6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + { -1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, + { -11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} + }; + + u4Byte APK_normal_setting_value_1[13] = { + 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, + 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, + 0x12680000, 0x00880000, 0x00880000 + }; + + u4Byte APK_normal_setting_value_2[16] = { + 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, + 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, + 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, + 0x00050006 + }; + + u4Byte APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a +// u4Byte AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; + + s4Byte BB_offset, delta_V, delta_offset; + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); +#else + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); +#endif + pMptCtx->APK_bound[0] = 45; + pMptCtx->APK_bound[1] = 52; + +#endif + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188F() delta %d\n", delta)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); +#if MP_DRIVER == 1 + if (!is2T) + pathbound = 1; +#endif + //2 FOR NORMAL CHIP SETTINGS + +// Temporarily do not allow normal driver to do the following settings because these offset +// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal +// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the +// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. +#if MP_DRIVER != 1 + return; +//#endif +#else + //settings adjust for normal chip + for (index = 0; index < PATH_NUM; index ++) { + APK_offset[index] = APK_normal_offset[index]; + APK_value[index] = APK_normal_value[index]; + AFE_on_off[index] = 0x6fdb25a4; + } + + for (index = 0; index < APK_BB_REG_NUM; index ++) { + for (path = 0; path < pathbound; path++) { + APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; + APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; + } + BB_AP_MODE[index] = BB_normal_AP_MODE[index]; + } + + apkbound = 6; + + //save BB default value + for (index = 0; index < APK_BB_REG_NUM; index++) { + if (index == 0) //skip + continue; + BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); + } + + //save MAC default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveMACRegisters8188F(pAdapter, MAC_REG, MAC_backup); + + //save AFE default value + _PHY_SaveADDARegisters8188F(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#else + _PHY_SaveMACRegisters8188F(pDM_Odm, MAC_REG, MAC_backup); + + //save AFE default value + _PHY_SaveADDARegisters8188F(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#endif + + for (path = 0; path < pathbound; path++) { + + + if (path == ODM_RF_PATH_A) { + //path A APK + //load APK setting + //path-A + offset = rPdp_AntA; + for (index = 0; index < 11; index ++) { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188F() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); + + offset = rConfig_AntA; + for (; index < 13; index ++) { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188F() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); + + //path A + offset = rPdp_AntA; + for (index = 0; index < 16; index++) { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188F() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + } else if (path == ODM_RF_PATH_B) { + //path B APK + //load APK setting + //path-B + offset = rPdp_AntB; + for (index = 0; index < 10; index ++) { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188F() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); +#else + PHY_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000); +#endif + + offset = rConfig_AntA; + index = 11; + for (; index < 13; index ++) { //offset 0xb68, 0xb6c + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188F() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + + //page-B1 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); + + //path B + offset = 0xb60; + for (index = 0; index < 16; index++) { + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188F() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord))); + + offset += 0x04; + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0); + } + + //save RF default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord); +#else + regD[path] = ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord); +#endif + + //Path A AFE all on, path B AFE All off or vise versa + for (index = 0; index < IQK_ADDA_REG_NUM; index++) + ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188F() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord))); + + //BB to AP mode + if (path == 0) { + for (index = 0; index < APK_BB_REG_NUM; index++) { + + if (index == 0) //skip + continue; + else if (index < 5) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); + else if (BB_REG[index] == 0x870) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index] | BIT10 | BIT26); + else + ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0); + } + + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + } else { //path B + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); + + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188F() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord))); + + //MAC settings +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration8188F(pAdapter, MAC_REG, MAC_backup); +#else + _PHY_MACSettingCalibration8188F(pDM_Odm, MAC_REG, MAC_backup); +#endif + + if (path == ODM_RF_PATH_A) //Path B to standby mode + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); + else { //Path A to standby mode + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103); + } + + delta_offset = ((delta + 14) / 2); + if (delta_offset < 0) + delta_offset = 0; + else if (delta_offset > 12) + delta_offset = 12; + + //AP calibration + for (index = 0; index < APK_BB_REG_NUM; index++) { + if (index != 1) //only DO PA11+PAD01001, AP RF setting + continue; + + tmpReg = APK_RF_init_value[path][index]; +#if 1 + if (!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore) { + BB_offset = (tmpReg & 0xF0000) >> 16; + + if (!(tmpReg & BIT15)) //sign bit 0 + BB_offset = -BB_offset; + + delta_V = APK_delta_mapping[index][delta_offset]; + + BB_offset += delta_V; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188F() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset)); + + if (BB_offset < 0) { + tmpReg = tmpReg & (~BIT15); + BB_offset = -BB_offset; + } else + tmpReg = tmpReg | BIT15; + tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); + } +#endif + + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_IPA_A, bMaskDWord, 0x8992e); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188F() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188F() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord, tmpReg); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188F() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord))); +#else + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188F() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188F() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord))); + ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188F() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord))); +#endif + + // PA11+PAD01111, one shot + i = 0; + do { + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x800000); + { + ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188F() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); + ODM_delay_ms(3); + ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188F() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord))); + + ODM_delay_ms(20); + } + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + if (path == ODM_RF_PATH_A) + tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000); + else + tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188F() offset 0xbd8[25:21] %x\n", tmpReg)); + + + i++; + } while (tmpReg > apkbound && i < 4); + + APK_result[path][index] = tmpReg; + } + } + + //reload MAC default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadMACRegisters8188F(pAdapter, MAC_REG, MAC_backup); +#else + _PHY_ReloadMACRegisters8188F(pDM_Odm, MAC_REG, MAC_backup); +#endif + + //reload BB default value + for (index = 0; index < APK_BB_REG_NUM; index++) { + + if (index == 0) //skip + continue; + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); + } + + //reload AFE default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters8188F(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#else + _PHY_ReloadADDARegisters8188F(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#endif + + //reload RF path default value + for (path = 0; path < pathbound; path++) { + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0xd, bMaskDWord, regD[path]); + if (path == ODM_RF_PATH_B) { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); + } + + //note no index == 0 + if (APK_result[path][1] > 6) + APK_result[path][1] = 6; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); + } + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\n")); + + + for (path = 0; path < pathbound; path++) { + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x3, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); + if (path == ODM_RF_PATH_A) + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); + else + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, + ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (!IS_HARDWARE_TYPE_8723A(pAdapter)) + ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G9_G11, bMaskDWord, + ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); +#endif + } + + pDM_Odm->RFCalibrateInfo.bAPKdone = TRUE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188F()\n")); +#endif //MP_DRIVER != 1 +#endif +} + + + +#define DP_BB_REG_NUM 7 +#define DP_RF_REG_NUM 1 +#define DP_RETRY_LIMIT 10 +#define DP_PATH_NUM 2 +#define DP_DPK_NUM 3 +#define DP_DPK_VALUE_NUM 2 + + + + +VOID +PHY_IQCalibrate_8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bReCovery, + IN BOOLEAN bRestore +) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#else // (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif + +#if (MP_DRIVER == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); +#else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); +#endif +#endif//(MP_DRIVER == 1) +#endif + + s4Byte result[4][8]; //last is final result + u1Byte i, final_candidate, Indexforchannel; + BOOLEAN bPathAOK, bPathBOK; +#if DBG + s4Byte RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; +#else + s4Byte RegE94, RegEA4, RegEB4, RegEC4, RegTmp = 0; +#endif + BOOLEAN is12simular, is13simular, is23simular; +#if MP_DRIVER == 1 + BOOLEAN bStartContTx = FALSE; +#endif + BOOLEAN bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte IQK_BB_REG_92C[IQK_BB_REG_NUM] = { + rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, + rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, + rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, + rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, + rOFDM0_RxIQExtAnta + }; + u4Byte Path_SEL_BB = 0, Path_SEL_RF = 0; + +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) ) + if (ODM_CheckPowerStatus(pAdapter) == FALSE) + return; +#else + prtl8192cd_priv priv = pDM_Odm->priv; + +#ifdef MP_TEST + if (priv->pshare->rf_ft_var.mp_specific) { + if ((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST)) + return; + } +#endif + + if (priv->pshare->IQK_88E_done) + bReCovery = 1; + priv->pshare->IQK_88E_done = 1; + +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + return; +#endif + +#if MP_DRIVER == 1 + bStartContTx = pMptCtx->bStartContTx; + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; +#endif + + // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) + if (bSingleTone || bCarrierSuppression) + return; + +#if DISABLE_BB_RF + return; +#endif + + if (bRestore) { + u4Byte offset, data; + u1Byte path, bResult = SUCCESS; + PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); + + //#define PATH_S0 1 // RF_PATH_B + //#define PATH_S1 0 // RF_PATH_A + + path = (ODM_GetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskByte0) == 0x00) ? ODM_RF_PATH_A : ODM_RF_PATH_B; + //Restore TX IQK + for (i = 0; i < 3; ++i) { + offset = pRFCalibrateInfo->TxIQC_8723B[path][i][0]; + data = pRFCalibrateInfo->TxIQC_8723B[path][i][1]; + if ((offset == 0) || (data == 0)) { + //DBG_871X("%s =>path:%s Restore TX IQK result failed\n",__FUNCTION__,(path==ODM_RF_PATH_A)?"A":"B"); + bResult = FAIL; + break; + } + RT_TRACE(COMP_MP, DBG_TRACE, ("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data)); + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, data); + } + //Restore RX IQK + for (i = 0; i < 2; ++i) { + offset = pRFCalibrateInfo->RxIQC_8723B[path][i][0]; + data = pRFCalibrateInfo->RxIQC_8723B[path][i][1]; + if ((offset == 0) || (data == 0)) { + //DBG_871X("%s =>path:%s Restore RX IQK result failed\n",__FUNCTION__,(path==ODM_RF_PATH_A)?"A":"B"); + bResult = FAIL; + break; + } + RT_TRACE(COMP_MP, DBG_TRACE, ("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data)); + ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, data); + } + + if (pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A] == 0) { + //DBG_871X("%s => Restore Path-A TxLOK result failed\n",__FUNCTION__); + bResult = FAIL; + } else { + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A]); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_B]); + } + + if (bResult == SUCCESS) + return; + + } + +#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP)) + if (bReCovery) +#else//for ODM_WIN + if (bReCovery && (!pAdapter->bInHctTest)) //YJ,add for PowerTest,120405 +#endif + { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_8188F: Return due to bReCovery!\n")); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters8188F(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); +#else + _PHY_ReloadADDARegisters8188F(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); +#endif + return; + } + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n")); + + + // Save RF Path + Path_SEL_BB = ODM_GetBBReg(pDM_Odm, 0x948, bMaskDWord); + Path_SEL_RF = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff); + + + for (i = 0; i < 8; i++) { + result[0][i] = 0; + result[1][i] = 0; + result[2][i] = 0; + result[3][i] = 0; + } + final_candidate = 0xff; + bPathAOK = FALSE; + bPathBOK = FALSE; + is12simular = FALSE; + is23simular = FALSE; + is13simular = FALSE; + + + for (i = 0; i < 3; i++) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + + phy_IQCalibrate_8188F(pAdapter, result, i, FALSE); + +#else + phy_IQCalibrate_8188F(pDM_Odm, result, i, FALSE); +#endif + + + if (i == 1) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is12simular = phy_SimularityCompare_8188F(pAdapter, result, 0, 1); +#else + is12simular = phy_SimularityCompare_8188F(pDM_Odm, result, 0, 1); +#endif + if (is12simular) { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n", final_candidate)); + break; + } + } + + if (i == 2) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is13simular = phy_SimularityCompare_8188F(pAdapter, result, 0, 2); +#else + is13simular = phy_SimularityCompare_8188F(pDM_Odm, result, 0, 2); +#endif + if (is13simular) { + final_candidate = 0; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n", final_candidate)); + + break; + } +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + is23simular = phy_SimularityCompare_8188F(pAdapter, result, 1, 2); +#else + is23simular = phy_SimularityCompare_8188F(pDM_Odm, result, 1, 2); +#endif + if (is23simular) { + final_candidate = 1; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n", final_candidate)); + } else { + for (i = 0; i < 8; i++) RegTmp += result[3][i]; + + if (RegTmp != 0) + final_candidate = 3; + else + final_candidate = 0xFF; + } + } + } +// RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate\n")); + + for (i = 0; i < 4; i++) { + RegE94 = result[i][0]; + RegEA4 = result[i][2]; + RegEB4 = result[i][4]; + RegEC4 = result[i][6]; +#if DBG + RegE9C = result[i][1]; + RegEAC = result[i][3]; + RegEBC = result[i][5]; + RegECC = result[i][7]; +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%04x RegE9C=%04x RegEA4=%04x RegEAC=%04x RegEB4=%04x RegEBC=%04x RegEC4=%04x RegECC=%04x\n", + RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + } + + if (final_candidate != 0xff) { + pDM_Odm->RFCalibrateInfo.RegE94 = result[final_candidate][0]; + pDM_Odm->RFCalibrateInfo.RegE9C = result[final_candidate][1]; + pDM_Odm->RFCalibrateInfo.RegEB4 = result[final_candidate][4]; + pDM_Odm->RFCalibrateInfo.RegEBC = result[final_candidate][5]; + + RegE94 = result[final_candidate][0]; + RegEA4 = result[final_candidate][2]; + RegEB4 = result[final_candidate][4]; + RegEC4 = result[final_candidate][6]; +#if DBG + RegE9C = result[final_candidate][1]; + RegEAC = result[final_candidate][3]; + RegEBC = result[final_candidate][5]; + RegECC = result[final_candidate][7]; +#endif + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: final_candidate is %x\n", final_candidate)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%04x RegE9C=%04x RegEA4=%04x RegEAC=%04x RegEB4=%04x RegEBC=%04x RegEC4=%04x RegECC=%04x\n", + RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); + bPathAOK = bPathBOK = TRUE; + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: FAIL use default value\n")); + + pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; //X default value + pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; //Y default value + } + +#if MP_DRIVER == 1 + if ((pMptCtx->MptRfPath == ODM_RF_PATH_A) || ((pDM_Odm->mp_mode) == 0)) +#endif + { + if (RegE94 != 0) { +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_PathAFillIQKMatrix8188F(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); +#else + _PHY_PathAFillIQKMatrix8188F(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0)); +#endif + } + } + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +#if MP_DRIVER == 1 + if ((pMptCtx->MptRfPath == ODM_RF_PATH_A) || ((pDM_Odm->mp_mode) == 0)) +#endif + { + if (RegEB4 != 0) + _PHY_PathBFillIQKMatrix8188F(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); + } +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); +#else + Indexforchannel = 0; +#endif + +//To Fix BSOD when final_candidate is 0xff +//by sherry 20120321 + if (final_candidate < 4) { + for (i = 0; i < IQK_Matrix_REG_NUM; i++) pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; + pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE; + } + //RT_DISP(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + _PHY_SaveADDARegisters8188F(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); +#else + _PHY_SaveADDARegisters8188F(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM); +#endif + + // Restore RF Path + ODM_SetBBReg(pDM_Odm, 0x948, bMaskDWord, Path_SEL_BB); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished 8188F\n")); + + +} + + +VOID +PHY_LCCalibrate_8188F( + PVOID pDM_VOID +) +{ +#if MP_DRIVER == 1 + BOOLEAN bStartContTx = FALSE; +#endif + BOOLEAN bSingleTone = FALSE, bCarrierSuppression = FALSE; + u4Byte timeout = 2000, timecount = 0; + + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +#if MP_DRIVER == 1 + PADAPTER pAdapter = pDM_Odm->Adapter; + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PMPT_CONTEXT pMptCtx = &(pAdapter->MptCtx); +#else// (DM_ODM_SUPPORT_TYPE == ODM_CE) + PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); +#endif +#endif +#endif + +#if MP_DRIVER == 1 + bStartContTx = pMptCtx->bStartContTx; + bSingleTone = pMptCtx->bSingleTone; + bCarrierSuppression = pMptCtx->bCarrierSuppression; +#endif + + +#if DISABLE_BB_RF + return; +#endif + +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + return; +#endif + // 20120213 Turn on when continuous Tx to pass lab testing. (required by Edlu) + if (bSingleTone || bCarrierSuppression) + return; + + while (*(pDM_Odm->pbScanInProcess) && timecount < timeout) { + ODM_delay_ms(50); + timecount += 50; + } + + pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE; + + + phy_LCCalibrate_8188F(pDM_Odm, FALSE); + + + pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE; + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d 8188F\n", pDM_Odm->InterfaceIndex)); + +} + +VOID +PHY_APCalibrate_8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta +) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) +#if DBG + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif +#endif +#if DISABLE_BB_RF + return; +#endif + + return; +#if 0 +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) + return; +#endif + +#if FOR_BRAZIL_PRETEST != 1 + if (pDM_Odm->RFCalibrateInfo.bAPKdone) +#endif + return; + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + if (IS_2T2R(pHalData->VersionID)) + phy_APCalibrate_8188F(pAdapter, delta, TRUE); + else +#endif + { + // For 88C 1T1R +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_APCalibrate_8188F(pAdapter, delta, FALSE); +#else + phy_APCalibrate_8188F(pDM_Odm, delta, FALSE); +#endif + } +#endif +} + +VOID phy_SetRFPathSwitch_8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain, + IN BOOLEAN is2T +) +{ + + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif + + if (bMain) // Left antenna + ODM_SetBBReg(pDM_Odm, 0x92C, bMaskDWord, 0x1); + else + ODM_SetBBReg(pDM_Odm, 0x92C, bMaskDWord, 0x2); +} + +VOID PHY_SetRFPathSwitch_8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN bMain +) +{ + +#if DISABLE_BB_RF + return; +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + phy_SetRFPathSwitch_8188F(pAdapter, bMain, TRUE); +#endif + +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +//digital predistortion +VOID +phy_DigitalPredistortion8188F( +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PADAPTER pAdapter, +#else + IN PDM_ODM_T pDM_Odm, +#endif + IN BOOLEAN is2T +) +{ +#if (RT_PLATFORM == PLATFORM_WINDOWS) +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + + u4Byte tmpReg, tmpReg2, index, i; + u1Byte path, pathbound = PATH_NUM; + u4Byte AFE_backup[IQK_ADDA_REG_NUM]; + u4Byte AFE_REG[IQK_ADDA_REG_NUM] = { + rFPGA0_XCD_SwitchControl, rBlue_Tooth, + rRx_Wait_CCA, rTx_CCK_RFON, + rTx_CCK_BBON, rTx_OFDM_RFON, + rTx_OFDM_BBON, rTx_To_Rx, + rTx_To_Tx, rRx_CCK, + rRx_OFDM, rRx_Wait_RIFS, + rRx_TO_Rx, rStandby, + rSleep, rPMPD_ANAEN + }; + + u4Byte BB_backup[DP_BB_REG_NUM]; + u4Byte BB_REG[DP_BB_REG_NUM] = { + rOFDM0_TRxPathEnable, rFPGA0_RFMOD, + rOFDM0_TRMuxPar, rFPGA0_XCD_RFInterfaceSW, + rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, + rFPGA0_XB_RFInterfaceOE + }; + u4Byte BB_settings[DP_BB_REG_NUM] = { + 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, + 0x0, 0x0, 0x0 + }; + + u4Byte RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; + u4Byte RF_REG[DP_RF_REG_NUM] = { + RF_TXBIAS_A + }; + + u4Byte MAC_backup[IQK_MAC_REG_NUM]; + u4Byte MAC_REG[IQK_MAC_REG_NUM] = { + REG_TXPAUSE, REG_BCN_CTRL, + REG_BCN_CTRL_1, REG_GPIO_MUXCFG + }; + + u4Byte Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = { + { 0x1e1e1e1e, 0x03901e1e }, + { 0x18181818, 0x03901818 }, + { 0x0e0e0e0e, 0x03900e0e } + }; + + u4Byte AFE_on_off[PATH_NUM] = { + 0x04db25a4, 0x0b1b25a4 + }; //path A on path B off / path A off path B on + + u1Byte RetryCount = 0; + + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion8188F()\n")); + + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion8188F for %s\n", (is2T ? "2T2R" : "1T1R"))); + + //save BB default value + for (index = 0; index < DP_BB_REG_NUM; index++) BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord); + + //save MAC default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveMACRegisters8188F(pAdapter, BB_REG, MAC_backup); +#else + _PHY_SaveMACRegisters8188F(pDM_Odm, BB_REG, MAC_backup); +#endif + + //save RF default value + for (path = 0; path < DP_PATH_NUM; path++) { + for (index = 0; index < DP_RF_REG_NUM; index++) +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + RF_backup[path][index] = PHY_QueryRFReg(pAdapter, path, RF_REG[index], bMaskDWord); +#else + RF_backup[path][index] = ODM_GetRFReg(pAdapter, path, RF_REG[index], bMaskDWord); +#endif + } + + //save AFE default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_SaveADDARegisters8188F(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#else + _PHY_SaveADDARegisters8188F(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); +#endif + + //Path A/B AFE all on + for (index = 0; index < IQK_ADDA_REG_NUM; index++) ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, 0x6fdb25a4); + + //BB register setting + for (index = 0; index < DP_BB_REG_NUM; index++) { + if (index < 4) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_settings[index]); + else if (index == 4) + ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index] | BIT10 | BIT26); + else + ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x00); + } + + //MAC register setting +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_MACSettingCalibration8188F(pAdapter, MAC_REG, MAC_backup); +#else + _PHY_MACSettingCalibration8188F(pDM_Odm, MAC_REG, MAC_backup); +#endif + + //PAGE-E IQC setting + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00); + ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00); + + //path_A DPK + //Path B to standby mode + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000); + + // PA gain = 11 & PAD1 => tx_agc 1f ~11 + // PA gain = 11 & PAD2 => tx_agc 10~0e + // PA gain = 01 => tx_agc 0b~0d + // PA gain = 00 => tx_agc 0a~00 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); + ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + //do inner loopback DPK 3 times + for (i = 0; i < 3; i++) { + //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 + for (index = 0; index < 3; index++) ODM_SetBBReg(pDM_Odm, 0xe00 + index * 4, bMaskDWord, Tx_AGC[i][0]); + ODM_SetBBReg(pDM_Odm, 0xe00 + index * 4, bMaskDWord, Tx_AGC[i][1]); + for (index = 0; index < 4; index++) ODM_SetBBReg(pDM_Odm, 0xe10 + index * 4, bMaskDWord, Tx_AGC[i][0]); + + // PAGE_B for Path-A inner loopback DPK setting + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02097098); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); + + //----send one shot signal----// + // Path A + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x80047788); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788); + ODM_delay_ms(50); + } + + //PA gain = 11 => tx_agc = 1a + for (index = 0; index < 3; index++) ODM_SetBBReg(pDM_Odm, 0xe00 + index * 4, bMaskDWord, 0x34343434); + ODM_SetBBReg(pDM_Odm, 0xe08 + index * 4, bMaskDWord, 0x03903434); + for (index = 0; index < 4; index++) ODM_SetBBReg(pDM_Odm, 0xe10 + index * 4, bMaskDWord, 0x34343434); + + //==================================== + // PAGE_B for Path-A DPK setting + //==================================== + // open inner loopback @ b00[19]:10 od 0xb00 0x01097018 + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); + + //rf_lpbk_setup + //1.rf 00:5205a, rf 0d:0e52c + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0c, bMaskDWord, 0x8992b); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bMaskDWord, 0x5205a); + + //----send one shot signal----// + // Path A + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + + while (RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK) { + //----read back measurement results----// + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018); + tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord); + ODM_delay_ms(10); + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f); + tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord); + ODM_delay_ms(10); + + tmpReg = (tmpReg & bMaskHWord) >> 16; + tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; + if (tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) { + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x800000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + RetryCount++; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2)); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n")); + pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE; + break; + } + } + RetryCount = 0; + + //DPP path A + if (pDM_Odm->RFCalibrateInfo.bDPPathAOK) { + // DP settings + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); + + for (i = rPdp_AntA; i <= 0xb3c; i += 4) { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i)); + } + + //pwsf + ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040); + ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040); + ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920); + + for (i = 0xb4c; i <= 0xb5c; i += 4) + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); + + //TX_AGC boundary + ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + } else { + ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000); + } + + //DPK path B + if (is2T) { + //Path A to standby mode + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000); + + // LUTs => tx_agc + // PA gain = 11 & PAD1, => tx_agc 1f ~11 + // PA gain = 11 & PAD2, => tx_agc 10 ~0e + // PA gain = 01 => tx_agc 0b ~0d + // PA gain = 00 => tx_agc 0a ~00 + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); + ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + //do inner loopback DPK 3 times + for (i = 0; i < 3; i++) { + //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 + for (index = 0; index < 4; index++) ODM_SetBBReg(pDM_Odm, 0x830 + index * 4, bMaskDWord, Tx_AGC[i][0]); + for (index = 0; index < 2; index++) ODM_SetBBReg(pDM_Odm, 0x848 + index * 4, bMaskDWord, Tx_AGC[i][0]); + for (index = 0; index < 2; index++) ODM_SetBBReg(pDM_Odm, 0x868 + index * 4, bMaskDWord, Tx_AGC[i][0]); + + // PAGE_B for Path-A inner loopback DPK setting + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + //----send one shot signal----// + // Path B + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x80047788); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788); + ODM_delay_ms(50); + } + + // PA gain = 11 => tx_agc = 1a + for (index = 0; index < 4; index++) ODM_SetBBReg(pDM_Odm, 0x830 + index * 4, bMaskDWord, 0x34343434); + for (index = 0; index < 2; index++) ODM_SetBBReg(pDM_Odm, 0x848 + index * 4, bMaskDWord, 0x34343434); + for (index = 0; index < 2; index++) ODM_SetBBReg(pDM_Odm, 0x868 + index * 4, bMaskDWord, 0x34343434); + + // PAGE_B for Path-B DPK setting + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + // RF lpbk switches on + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f); + ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103); + + //Path-B RF lpbk + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0c, bMaskDWord, 0x8992b); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c); + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); + + //----send one shot signal----// + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + + while (RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK) { + //----read back measurement results----// + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018); + tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord); + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f); + tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord); + + tmpReg = (tmpReg & bMaskHWord) >> 16; + tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; + + if (tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) { + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x800000); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0); + ODM_delay_ms(1); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0); + ODM_delay_ms(50); + RetryCount++; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2)); + } else { + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n")); + pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE; + break; + } + } + + //DPP path B + if (pDM_Odm->RFCalibrateInfo.bDPPathBOK) { + // DP setting + // LUT by SRAM + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84); + ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87); + ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000); + + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x400000); + for (i = 0xb60; i <= 0xb9c; i += 4) { + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000); + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i)); + } + + // PWSF + ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040); + ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050); + ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920); + + for (i = 0xbac; i <= 0xbbc; i += 4) + ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c); + + // tx_agc boundary + ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f); + ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskH3Bytes, 0x000000); + + } else { + ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000); + } + } + + //reload BB default value + for (index = 0; index < DP_BB_REG_NUM; index++) ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]); + + //reload RF default value + for (path = 0; path < DP_PATH_NUM; path++) { + for (i = 0; i < DP_RF_REG_NUM; i++) + ODM_SetRFReg(pDM_Odm, path, RF_REG[i], bMaskDWord, RF_backup[path][i]); + } + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f); //standby mode + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101); //RF lpbk switches off + + //reload AFE default value +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + _PHY_ReloadADDARegisters8188F(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + + //reload MAC default value + _PHY_ReloadMACRegisters8188F(pAdapter, MAC_REG, MAC_backup); +#else + _PHY_ReloadADDARegisters8188F(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); + + //reload MAC default value + _PHY_ReloadMACRegisters8188F(pDM_Odm, MAC_REG, MAC_backup); +#endif + + pDM_Odm->RFCalibrateInfo.bDPdone = TRUE; + ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion8188F()\n")); +#endif +} + +VOID +PHY_DigitalPredistortion_8188F( +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PADAPTER pAdapter +#else + IN PDM_ODM_T pDM_Odm +#endif +) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif +#if DISABLE_BB_RF + return; +#endif + + return; + + if (pDM_Odm->RFCalibrateInfo.bDPdone) + return; +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + + if (IS_92C_SERIAL(pHalData->VersionID)) + phy_DigitalPredistortion8188F(pAdapter, TRUE); + else +#endif + { + // For 88C 1T1R + phy_DigitalPredistortion8188F(pAdapter, FALSE); + } +} + + + +//return value TRUE => Main; FALSE => Aux + +BOOLEAN phy_QueryRFPathSwitch_8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN BOOLEAN is2T +) +{ +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#endif +#endif + + + if (ODM_GetBBReg(pDM_Odm, 0x92C, bMaskDWord) == 0x01) + return TRUE; + else + return FALSE; + +} + + + +//return value TRUE => Main; FALSE => Aux +BOOLEAN PHY_QueryRFPathSwitch_8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + +#if DISABLE_BB_RF + return TRUE; +#endif + +#if !(DM_ODM_SUPPORT_TYPE & ODM_AP) + return phy_QueryRFPathSwitch_8188F(pAdapter, FALSE); +#else + return phy_QueryRFPathSwitch_8188F(pDM_Odm, FALSE); +#endif + +} +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halphyrf_8188f.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halphyrf_8188f.h new file mode 100644 index 000000000..9d384b9c5 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/halphyrf_8188f.h @@ -0,0 +1,135 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PHY_RF_8188F_H__ +#define __HAL_PHY_RF_8188F_H__ + + +/*--------------------------Define Parameters-------------------------------*/ +#define IQK_DELAY_TIME_8188F 25 /* ms */ +#define IQK_DEFERRED_TIME_8188F 4 +#define index_mapping_NUM_8188F 15 +#define AVG_THERMAL_NUM_8188F 4 +#define RF_T_METER_8188F 0x42 + + +void ConfigureTxpowerTrack_8188F( + PTXPWRTRACK_CFG pConfig + ); + +void DoIQK_8188F( + PVOID pDM_VOID, + u1Byte DeltaThermalIndex, + u1Byte ThermalValue, + u1Byte Threshold + ); + +VOID +ODM_TxPwrTrackSetPwr_8188F( + IN PVOID pDM_VOID, + PWRTRACK_METHOD Method, + u1Byte RFPath, + u1Byte ChannelMappedIndex + ); + +//1 7. IQK + +void +PHY_IQCalibrate_8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER Adapter, +#endif + IN BOOLEAN bReCovery, + IN BOOLEAN bRestore); + + +// +// LC calibrate +// +void +PHY_LCCalibrate_8188F( + IN PVOID pDM_VOID +); + +// +// AP calibrate +// +void +PHY_APCalibrate_8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN s1Byte delta); +void +PHY_DigitalPredistortion_8188F( IN PADAPTER pAdapter); + + +VOID +_PHY_SaveADDARegisters_8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN pu4Byte ADDABackup, + IN u4Byte RegisterNum + ); + +VOID +_PHY_PathADDAOn_8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte ADDAReg, + IN BOOLEAN isPathAOn, + IN BOOLEAN is2T + ); + +VOID +_PHY_MACSettingCalibration_8188F( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm, +#else + IN PADAPTER pAdapter, +#endif + IN pu4Byte MACReg, + IN pu4Byte MACBackup + ); + + +VOID +_PHY_PathAStandBy( +#if (DM_ODM_SUPPORT_TYPE & ODM_AP) + IN PDM_ODM_T pDM_Odm +#else + IN PADAPTER pAdapter +#endif + ); + + +#endif // #ifndef __HAL_PHY_RF_8188E_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/phydm_regconfig8188f.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/phydm_regconfig8188f.c new file mode 100644 index 000000000..e7c8716ce --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/phydm_regconfig8188f.c @@ -0,0 +1,233 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8188F_SUPPORT == 1) + +void +odm_ConfigRFReg_8188F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ) +{ + if(Addr == 0xfe || Addr == 0xffe) + { + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + } + else + { + ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + + //For disable/enable test in high temperature, the B6 value will fail to fill. Suggestion by BB Stanley, 2013.06.25. + if(Addr == 0xb6) + { + u4Byte getvalue=0; + u1Byte count =0; + getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord); + + ODM_delay_us(1); + + while((getvalue>>8)!=(Data>>8)) + { + count++; + ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); + ODM_delay_us(1); + getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [B6] getvalue 0x%x, Data 0x%x, count %d\n", getvalue, Data,count)); + if(count>5) + break; + } + } + + if(Addr == 0xb2) + { + u4Byte getvalue=0; + u1Byte count =0; + getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord); + + ODM_delay_us(1); + + while(getvalue!=Data) + { + count++; + ODM_SetRFReg(pDM_Odm, RF_PATH, RegAddr, bRFRegOffsetMask, Data); + ODM_delay_us(1); + //Do LCK againg + ODM_SetRFReg(pDM_Odm, RF_PATH, 0x18, bRFRegOffsetMask, 0x0fc07); + ODM_delay_us(1); + getvalue = ODM_GetRFReg(pDM_Odm, RF_PATH, Addr, bMaskDWord); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [B2] getvalue 0x%x, Data 0x%x, count %d\n", getvalue, Data,count)); + if(count>5) + break; + } + } + } +} + + +void +odm_ConfigRF_RadioA_8188F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1000; // RF_Content: radioa_txt + u4Byte maskforPhySet= (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8188F(pDM_Odm, Addr, Data, ODM_RF_PATH_A, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioA] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigRF_RadioB_8188F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ) +{ + u4Byte content = 0x1001; // RF_Content: radiob_txt + u4Byte maskforPhySet= (u4Byte)(content&0xE000); + + odm_ConfigRFReg_8188F(pDM_Odm, Addr, Data, ODM_RF_PATH_B, Addr|maskforPhySet); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigRFWithHeaderFile: [RadioB] %08X %08X\n", Addr, Data)); + +} + +void +odm_ConfigMAC_8188F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ) +{ + ODM_Write1Byte(pDM_Odm, Addr, Data); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigMACWithHeaderFile: [MAC_REG] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_AGC_8188F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [AGC_TAB] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_PHY_REG_PG_8188F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Band, + IN u4Byte RfPath, + IN u4Byte TxNum, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) + +{ + if (Addr == 0xfe || Addr == 0xffe) + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + else + { +#if !(DM_ODM_SUPPORT_TYPE&ODM_AP) + PHY_StoreTxPowerByRate(pDM_Odm->Adapter, Band, RfPath, TxNum, Addr, Bitmask, Data); +#endif + } + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_LOUD, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X %08X\n", Addr, Bitmask, Data)); +} + +void +odm_ConfigBB_PHY_8188F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ) +{ + if (Addr == 0xfe) + #ifdef CONFIG_LONG_DELAY_ISSUE + ODM_sleep_ms(50); + #else + ODM_delay_ms(50); + #endif + else if (Addr == 0xfd) + ODM_delay_ms(5); + else if (Addr == 0xfc) + ODM_delay_ms(1); + else if (Addr == 0xfb) + ODM_delay_us(50); + else if (Addr == 0xfa) + ODM_delay_us(5); + else if (Addr == 0xf9) + ODM_delay_us(1); + else + { + ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data); + } + + // Add 1us delay between BB/RF register setting. + ODM_delay_us(1); + ODM_RT_TRACE(pDM_Odm,ODM_COMP_INIT, ODM_DBG_TRACE, ("===> ODM_ConfigBBWithHeaderFile: [PHY_REG] %08X %08X\n", Addr, Data)); +} + +void +odm_ConfigBB_TXPWR_LMT_8188F( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte Regulation, + IN pu1Byte Band, + IN pu1Byte Bandwidth, + IN pu1Byte RateSection, + IN pu1Byte RfPath, + IN pu1Byte Channel, + IN pu1Byte PowerLimit + ) +{ +#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE)) + PHY_SetTxPowerLimit(pDM_Odm, Regulation, Band, + Bandwidth, RateSection, RfPath, Channel, PowerLimit); +#endif +} + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/phydm_regconfig8188f.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/phydm_regconfig8188f.h new file mode 100644 index 000000000..106e6ab90 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/phydm_regconfig8188f.h @@ -0,0 +1,96 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __INC_ODM_REGCONFIG_H_8188F +#define __INC_ODM_REGCONFIG_H_8188F + +#if (RTL8188F_SUPPORT == 1) + +void +odm_ConfigRFReg_8188F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data, + IN ODM_RF_RADIO_PATH_E RF_PATH, + IN u4Byte RegAddr + ); + +void +odm_ConfigRF_RadioA_8188F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigRF_RadioB_8188F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Data + ); + +void +odm_ConfigMAC_8188F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u1Byte Data + ); + +void +odm_ConfigBB_AGC_8188F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_REG_PG_8188F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Band, + IN u4Byte RfPath, + IN u4Byte TxNum, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_PHY_8188F( + IN PDM_ODM_T pDM_Odm, + IN u4Byte Addr, + IN u4Byte Bitmask, + IN u4Byte Data + ); + +void +odm_ConfigBB_TXPWR_LMT_8188F( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte Regulation, + IN pu1Byte Band, + IN pu1Byte Bandwidth, + IN pu1Byte RateSection, + IN pu1Byte RfPath, + IN pu1Byte Channel, + IN pu1Byte PowerLimit + ); + +#endif +#endif // end of SUPPORT + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/phydm_rtl8188f.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/phydm_rtl8188f.c new file mode 100644 index 000000000..2fcbab4e4 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/phydm_rtl8188f.c @@ -0,0 +1,72 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +//============================================================ +// include files +//============================================================ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (RTL8188F_SUPPORT == 1) + + s1Byte +odm_CCKRSSI_8188F( + IN u1Byte LNA_idx, + IN u1Byte VGA_idx + ) +{ + s1Byte rx_pwr_all=0x00; + switch(LNA_idx) + { + case 7: + if (VGA_idx <= 27) + rx_pwr_all = -100 + 2 * (27 - VGA_idx); + else + rx_pwr_all = -100; + break; + + case 5: + rx_pwr_all = -74 + 2 * (21 - VGA_idx); + break; + + case 3: + rx_pwr_all = -60 + 2 * (20 - VGA_idx); + break; + + case 1: + rx_pwr_all = -44 + 2 * (19 - VGA_idx); + break; + + default: + break; + } + return rx_pwr_all; +} + +#endif // end if RTL8188F + + + + + + + + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/phydm_rtl8188f.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/phydm_rtl8188f.h new file mode 100644 index 000000000..714b78a09 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/phydm_rtl8188f.h @@ -0,0 +1,29 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __ODM_RTL8188F_H__ +#define __ODM_RTL8188F_H__ + +s1Byte +odm_CCKRSSI_8188F( + IN u1Byte LNA_idx, + IN u1Byte VGA_idx + ); + +#endif diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/version_rtl8188f.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/version_rtl8188f.h new file mode 100644 index 000000000..c63d93c6d --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/rtl8188f/version_rtl8188f.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*RTL8188F PHY Parameters*/ +/* +[Caution] + Since 01/Aug/2015, the commit rules will be simplified. + You do not need to fill up the version.h anymore, + only the maintenance supervisor fills it before formal release. +*/ +#define RELEASE_DATE_8188F 20160624 +#define COMMIT_BY_8188F "BB_David" +#define RELEASE_VERSION_8188F 31 diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/halcomtxbf.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/halcomtxbf.c new file mode 100644 index 000000000..3766e5213 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/halcomtxbf.c @@ -0,0 +1,552 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//============================================================ +// Description: +// +// This file is for TXBF mechanism +// +//============================================================ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (BEAMFORMING_SUPPORT == 1) +/*Beamforming halcomtxbf API create by YuChen 2015/05*/ + +VOID +halComTxbf_beamformInit( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (pDM_Odm->SupportICType & ODM_RTL8822B) + HalTxbf8822B_Init(pDM_Odm); +} + +/*Only used for MU BFer Entry when get GID management frame (self is as MU STA)*/ +VOID +halComTxbf_ConfigGtab( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (pDM_Odm->SupportICType & ODM_RTL8822B) + HalTxbf8822B_ConfigGtab(pDM_Odm); +} + +VOID +phydm_beamformSetSoundingEnter( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + + if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_EnterWorkItem)) == FALSE) + PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_EnterWorkItem)); +#else + halComTxbf_EnterWorkItemCallback(pDM_Odm); +#endif +} + +VOID +phydm_beamformSetSoundingLeave( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + + if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_LeaveWorkItem)) == FALSE) + PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_LeaveWorkItem)); +#else + halComTxbf_LeaveWorkItemCallback(pDM_Odm); +#endif +} + +VOID +phydm_beamformSetSoundingRate( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + + if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_RateWorkItem)) == FALSE) + PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_RateWorkItem)); +#else + halComTxbf_RateWorkItemCallback(pDM_Odm); +#endif +} + +VOID +phydm_beamformSetSoundingStatus( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + + if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_StatusWorkItem)) == FALSE) + PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_StatusWorkItem)); +#else + halComTxbf_StatusWorkItemCallback(pDM_Odm); +#endif +} + +VOID +phydm_beamformSetSoundingFwNdpa( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + + if (*pDM_Odm->pbFwDwRsvdPageInProgress) + ODM_SetTimer(pDM_Odm, &(pTxbfInfo->Txbf_FwNdpaTimer), 5); + else + PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_FwNdpaWorkItem)); +#else + halComTxbf_FwNdpaWorkItemCallback(pDM_Odm); +#endif +} + +VOID +phydm_beamformSetSoundingClk( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + + if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_ClkWorkItem)) == FALSE) + PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_ClkWorkItem)); +#elif(DM_ODM_SUPPORT_TYPE == ODM_CE) + PADAPTER padapter = pDM_Odm->Adapter; + + rtw_run_in_thread_cmd(padapter, halComTxbf_ClkWorkItemCallback, padapter); +#else + halComTxbf_ClkWorkItemCallback(pDM_Odm); +#endif +} + +VOID +phydm_beamformSetResetTxPath( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + + if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_ResetTxPathWorkItem)) == FALSE) + PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_ResetTxPathWorkItem)); +#else + halComTxbf_ResetTxPathWorkItemCallback(pDM_Odm); +#endif +} + +VOID +phydm_beamformSetGetTxRate( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + + if (PlatformIsWorkItemScheduled(&(pTxbfInfo->Txbf_GetTxRateWorkItem)) == FALSE) + PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_GetTxRateWorkItem)); +#else + halComTxbf_GetTxRateWorkItemCallback(pDM_Odm); +#endif +} + +VOID +halComTxbf_EnterWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#else + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#endif + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + u1Byte Idx = pTxbfInfo->TXBFIdx; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821)) + HalTxbfJaguar_Enter(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8192E) + HalTxbf8192E_Enter(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8814A) + HalTxbf8814A_Enter(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8821B) + HalTxbf8821B_Enter(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8822B) + HalTxbf8822B_Enter(pDM_Odm, Idx); +} + +VOID +halComTxbf_LeaveWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#else + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#endif + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + + u1Byte Idx = pTxbfInfo->TXBFIdx; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821)) + HalTxbfJaguar_Leave(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8192E) + HalTxbf8192E_Leave(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8814A) + HalTxbf8814A_Leave(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8821B) + HalTxbf8821B_Leave(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8822B) + HalTxbf8822B_Leave(pDM_Odm, Idx); +} + + +VOID +halComTxbf_FwNdpaWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#else + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#endif + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + u1Byte Idx = pTxbfInfo->NdpaIdx; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821)) + HalTxbfJaguar_FwTxBF(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8192E) + HalTxbf8192E_FwTxBF(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8814A) + HalTxbf8814A_FwTxBF(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8821B) + HalTxbf8821B_FwTxBF(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8822B) + HalTxbf8822B_FwTxBF(pDM_Odm, Idx); +} + +VOID +halComTxbf_ClkWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#else + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#endif + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (pDM_Odm->SupportICType & ODM_RTL8812) + HalTxbfJaguar_Clk_8812A(pDM_Odm); +} + + + +VOID +halComTxbf_RateWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#else + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#endif + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + u1Byte BW = pTxbfInfo->BW; + u1Byte Rate = pTxbfInfo->Rate; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (pDM_Odm->SupportICType & ODM_RTL8812) + HalTxbf8812A_setNDPArate(pDM_Odm, BW, Rate); + else if (pDM_Odm->SupportICType & ODM_RTL8192E) + HalTxbf8192E_setNDPArate(pDM_Odm, BW, Rate); + else if (pDM_Odm->SupportICType & ODM_RTL8814A) + HalTxbf8814A_setNDPArate(pDM_Odm, BW, Rate); + +} + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +halComTxbf_FwNdpaTimerCallback( + IN PRT_TIMER pTimer + ) +{ + + PADAPTER Adapter = (PADAPTER)pTimer->Adapter; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (*pDM_Odm->pbFwDwRsvdPageInProgress) + ODM_SetTimer(pDM_Odm, &(pTxbfInfo->Txbf_FwNdpaTimer), 5); + else + PlatformScheduleWorkItem(&(pTxbfInfo->Txbf_FwNdpaWorkItem)); +} +#endif + + +VOID +halComTxbf_StatusWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#else + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#endif + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + + u1Byte Idx = pTxbfInfo->TXBFIdx; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (pDM_Odm->SupportICType & (ODM_RTL8812|ODM_RTL8821)) + HalTxbfJaguar_Status(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8192E) + HalTxbf8192E_Status(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8814A) + HalTxbf8814A_Status(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8821B) + HalTxbf8821B_Status(pDM_Odm, Idx); + else if (pDM_Odm->SupportICType & ODM_RTL8822B) + HalTxbf8822B_Status(pDM_Odm, Idx); +} + +VOID +halComTxbf_ResetTxPathWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#else + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#endif + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + + u1Byte Idx = pTxbfInfo->TXBFIdx; + + if (pDM_Odm->SupportICType & ODM_RTL8814A) + HalTxbf8814A_ResetTxPath(pDM_Odm, Idx); + +} + +VOID +halComTxbf_GetTxRateWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ) +{ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#else + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#endif + + if (pDM_Odm->SupportICType & ODM_RTL8814A) + HalTxbf8814A_GetTxRate(pDM_Odm); +} + + +BOOLEAN +HalComTxbf_Set( + IN PVOID pDM_VOID, + IN u1Byte setType, + IN PVOID pInBuf + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PBOOLEAN pBoolean=(PBOOLEAN)pInBuf; + pu1Byte pU1Tmp=(pu1Byte)pInBuf; + pu4Byte pU4Tmp=(pu4Byte)pInBuf; + PHAL_TXBF_INFO pTxbfInfo = &pDM_Odm->BeamformingInfo.TxbfInfo; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] setType = 0x%X\n", __func__, setType)); + + switch(setType){ + case TXBF_SET_SOUNDING_ENTER: + pTxbfInfo->TXBFIdx = *pU1Tmp; + phydm_beamformSetSoundingEnter(pDM_Odm); + break; + + case TXBF_SET_SOUNDING_LEAVE: + pTxbfInfo->TXBFIdx = *pU1Tmp; + phydm_beamformSetSoundingLeave(pDM_Odm); + break; + + case TXBF_SET_SOUNDING_RATE: + pTxbfInfo->BW = pU1Tmp[0]; + pTxbfInfo->Rate = pU1Tmp[1]; + phydm_beamformSetSoundingRate(pDM_Odm); + break; + + case TXBF_SET_SOUNDING_STATUS: + pTxbfInfo->TXBFIdx = *pU1Tmp; + phydm_beamformSetSoundingStatus(pDM_Odm); + break; + + case TXBF_SET_SOUNDING_FW_NDPA: + pTxbfInfo->NdpaIdx = *pU1Tmp; + phydm_beamformSetSoundingFwNdpa(pDM_Odm); + break; + + case TXBF_SET_SOUNDING_CLK: + phydm_beamformSetSoundingClk(pDM_Odm); + break; + + case TXBF_SET_TX_PATH_RESET: + pTxbfInfo->TXBFIdx = *pU1Tmp; + phydm_beamformSetResetTxPath(pDM_Odm); + break; + + case TXBF_SET_GET_TX_RATE: + phydm_beamformSetGetTxRate(pDM_Odm); + break; + + } + + return TRUE; +} + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +BOOLEAN +HalComTxbf_Get( + IN PADAPTER Adapter, + IN u1Byte getType, + OUT PVOID pOutBuf + ) +{ + PHAL_DATA_TYPE pHalData=GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + PBOOLEAN pBoolean=(PBOOLEAN)pOutBuf; + ps4Byte pS4Tmp=(ps4Byte)pOutBuf; + pu4Byte pU4Tmp=(pu4Byte)pOutBuf; + pu1Byte pU1Tmp=(pu1Byte)pOutBuf; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (getType == TXBF_GET_EXPLICIT_BEAMFORMEE) { + if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(Adapter)) + *pBoolean = FALSE; + else if (/*IS_HARDWARE_TYPE_8822B(Adapter) ||*/ + IS_HARDWARE_TYPE_8821B(Adapter) || + IS_HARDWARE_TYPE_8192E(Adapter) || + IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(Adapter)) + *pBoolean = TRUE; + else + *pBoolean = FALSE; + } else if (getType == TXBF_GET_EXPLICIT_BEAMFORMER) { + if (IS_HARDWARE_TYPE_OLDER_THAN_8812A(Adapter)) + *pBoolean = FALSE; + else if (/*IS_HARDWARE_TYPE_8822B(Adapter) ||*/ + IS_HARDWARE_TYPE_8821B(Adapter) || + IS_HARDWARE_TYPE_8192E(Adapter) || + IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(Adapter)) { + if(pHalData->RF_Type == RF_2T2R || pHalData->RF_Type == RF_3T3R) + *pBoolean = TRUE; + else + *pBoolean = FALSE; + } else + *pBoolean = FALSE; + } else if (getType == TXBF_GET_MU_MIMO_STA) { +#if (RTL8822B_SUPPORT == 1) + if (/*pDM_Odm->SupportICType & (ODM_RTL8822B)*/ + IS_HARDWARE_TYPE_8822B(Adapter)) + *pBoolean = TRUE; + else +#endif + *pBoolean = FALSE; + + + } else if (getType == TXBF_GET_MU_MIMO_AP) { +#if (RTL8822B_SUPPORT == 1) + if (/*pDM_Odm->SupportICType & (ODM_RTL8822B)*/ + IS_HARDWARE_TYPE_8822B(Adapter)) + *pBoolean = TRUE; + else +#endif + *pBoolean = FALSE; + } + + return TRUE; +} +#endif + + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/halcomtxbf.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/halcomtxbf.h new file mode 100644 index 000000000..d7693cb5b --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/halcomtxbf.h @@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __HAL_COM_TXBF_H__ +#define __HAL_COM_TXBF_H__ + +/* +typedef BOOLEAN +(*TXBF_GET)( + IN PVOID pAdapter, + IN u1Byte getType, + OUT PVOID pOutBuf + ); + +typedef BOOLEAN +(*TXBF_SET)( + IN PVOID pAdapter, + IN u1Byte setType, + OUT PVOID pInBuf + ); +*/ +#define TxBF_Nr(a, b) ((a > b) ? (b) : (a)) + +typedef enum _TXBF_SET_TYPE{ + TXBF_SET_SOUNDING_ENTER, + TXBF_SET_SOUNDING_LEAVE, + TXBF_SET_SOUNDING_RATE, + TXBF_SET_SOUNDING_STATUS, + TXBF_SET_SOUNDING_FW_NDPA, + TXBF_SET_SOUNDING_CLK, + TXBF_SET_TX_PATH_RESET, + TXBF_SET_GET_TX_RATE +}TXBF_SET_TYPE,*PTXBF_SET_TYPE; + + +typedef enum _TXBF_GET_TYPE{ + TXBF_GET_EXPLICIT_BEAMFORMEE, + TXBF_GET_EXPLICIT_BEAMFORMER, + TXBF_GET_MU_MIMO_STA, + TXBF_GET_MU_MIMO_AP +}TXBF_GET_TYPE,*PTXBF_GET_TYPE; + + + +//2 HAL TXBF related +typedef struct _HAL_TXBF_INFO { + u1Byte TXBFIdx; + u1Byte NdpaIdx; + u1Byte BW; + u1Byte Rate; + + RT_TIMER Txbf_FwNdpaTimer; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + RT_WORK_ITEM Txbf_EnterWorkItem; + RT_WORK_ITEM Txbf_LeaveWorkItem; + RT_WORK_ITEM Txbf_FwNdpaWorkItem; + RT_WORK_ITEM Txbf_ClkWorkItem; + RT_WORK_ITEM Txbf_StatusWorkItem; + RT_WORK_ITEM Txbf_RateWorkItem; + RT_WORK_ITEM Txbf_ResetTxPathWorkItem; + RT_WORK_ITEM Txbf_GetTxRateWorkItem; +#endif + +} HAL_TXBF_INFO, *PHAL_TXBF_INFO; + +#if (BEAMFORMING_SUPPORT == 1) + +VOID +halComTxbf_beamformInit( + IN PVOID pDM_VOID + ); + +VOID +halComTxbf_ConfigGtab( + IN PVOID pDM_VOID + ); + +VOID +halComTxbf_EnterWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ); + +VOID +halComTxbf_LeaveWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ); + +VOID +halComTxbf_FwNdpaWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ); + +VOID +halComTxbf_ClkWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ); + +VOID +halComTxbf_ResetTxPathWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ); + +VOID +halComTxbf_GetTxRateWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ); + +VOID +halComTxbf_RateWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ); + +VOID +halComTxbf_FwNdpaTimerCallback( + IN PRT_TIMER pTimer + ); + +VOID +halComTxbf_StatusWorkItemCallback( +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN PADAPTER Adapter +#else + IN PVOID pDM_VOID +#endif + ); + +BOOLEAN +HalComTxbf_Set( + IN PVOID pDM_VOID, + IN u1Byte setType, + IN PVOID pInBuf + ); + +BOOLEAN +HalComTxbf_Get( + IN PADAPTER Adapter, + IN u1Byte getType, + OUT PVOID pOutBuf + ); + +#else +#define halComTxbf_beamformInit(pDM_VOID) NULL +#define halComTxbf_ConfigGtab(pDM_VOID) NULL +#define halComTxbf_EnterWorkItemCallback(_Adapter) NULL +#define halComTxbf_LeaveWorkItemCallback(_Adapter) NULL +#define halComTxbf_FwNdpaWorkItemCallback(_Adapter) NULL +#define halComTxbf_ClkWorkItemCallback(_Adapter) NULL +#define halComTxbf_RateWorkItemCallback(_Adapter) NULL +#define halComTxbf_FwNdpaTimerCallback(_Adapter) NULL +#define halComTxbf_StatusWorkItemCallback(_Adapter) NULL +#define HalComTxbf_Get(_Adapter, _getType, _pOutBuf) + +#endif + +#endif // #ifndef __HAL_COM_TXBF_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8192e.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8192e.c new file mode 100644 index 000000000..56f0c4930 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8192e.c @@ -0,0 +1,393 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//============================================================ +// Description: +// +// This file is for 8192E TXBF mechanism +// +//============================================================ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (BEAMFORMING_SUPPORT == 1) +#if (RTL8192E_SUPPORT == 1) + +VOID +HalTxbf8192E_setNDPArate( + IN PVOID pDM_VOID, + IN u1Byte BW, + IN u1Byte Rate +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8192E, (Rate << 2 | BW)); + +} + +VOID +halTxbf8192E_RfMode( + IN PVOID pDM_VOID, + IN PRT_BEAMFORMING_INFO pBeamInfo +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + BOOLEAN bSelfBeamformer = FALSE; + BOOLEAN bSelfBeamformee = FALSE; + BEAMFORMING_CAP BeamformCap = BEAMFORMING_CAP_NONE; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (pDM_Odm->RFType == ODM_1T1R) + return; + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); /*RF Mode table write enable*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, 0x80000, 0x1); /*RF Mode table write enable*/ + + if (pBeamInfo->beamformee_su_cnt > 0) { + /*Path_A*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode 0x30=0x18000*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0x77fc2); /*Enable TXIQGEN in RX mode*/ + /*Path_B*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0x77fc2); /*Enable TXIQGEN in RX mode*/ + } else { + /*Path_A*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0x77f82); /*Disable TXIQGEN in RX mode*/ + /*Path_B*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0xfffff, 0x18000); /*Select RX mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x0000f); /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0x77f82); /*Disable TXIQGEN in RX mode*/ + } + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); /*RF Mode table write disable*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WE_LUT, 0x80000, 0x0); /*RF Mode table write disable*/ + + if (pBeamInfo->beamformee_su_cnt > 0) { + ODM_SetBBReg(pDM_Odm, rFPGA1_TxInfo, bMaskDWord, 0x83321333); + ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, bMaskByte3, 0xc1); + } else + ODM_SetBBReg(pDM_Odm, rFPGA1_TxInfo, bMaskDWord, 0x81121313); +} + + + +VOID +halTxbf8192E_FwTxBFCmd( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte Idx, Period0 = 0, Period1 = 0; + u1Byte PageNum0 = 0xFF, PageNum1 = 0xFF; + u1Byte u1TxBFParm[3] = {0}; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + + for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { + if (pBeamInfo->BeamformeeEntry[Idx].BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (Idx == 0) { + if (pBeamInfo->BeamformeeEntry[Idx].bSound) + PageNum0 = 0xFE; + else + PageNum0 = 0xFF; //stop sounding + Period0 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod); + } else if (Idx == 1) { + if (pBeamInfo->BeamformeeEntry[Idx].bSound) + PageNum1 = 0xFE; + else + PageNum1 = 0xFF; //stop sounding + Period1 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod); + } + } + } + + u1TxBFParm[0] = PageNum0; + u1TxBFParm[1] = PageNum1; + u1TxBFParm[2] = (Period1 << 4) | Period0; + ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_TXBF, 3, u1TxBFParm); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, + ("[%s] PageNum0 = %d Period0 = %d, PageNum1 = %d Period1 %d\n", __func__, PageNum0, Period0, PageNum1, Period1)); +} + + +VOID +halTxbf8192E_DownloadNDPA( + IN PVOID pDM_VOID, + IN u1Byte Idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte u1bTmp = 0, tmpReg422 = 0, Head_Page; + u1Byte BcnValidReg = 0, count = 0, DLBcnCount = 0; + BOOLEAN bSendBeacon = FALSE; + PADAPTER Adapter = pDM_Odm->Adapter; + u1Byte TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; + /*default reseved 1 page for the IC type which is undefined.*/ + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + *pDM_Odm->pbFwDwRsvdPageInProgress = TRUE; +#endif + if (Idx == 0) + Head_Page = 0xFE; + else + Head_Page = 0xFE; + + Adapter->HalFunc.GetHalDefVarHandler(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (pu1Byte)&TxPageBndy); + + /*Set REG_CR bit 8. DMA beacon by SW.*/ + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8192E+1); + ODM_Write1Byte(pDM_Odm, REG_CR_8192E+1, (u1bTmp | BIT0)); + + /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/ + tmpReg422 = ODM_Read1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8192E+2); + ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8192E+2, tmpReg422 & (~BIT6)); + + if (tmpReg422 & BIT6) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_WARNING, ("%s There is an Adapter is sending beacon.\n", __func__)); + bSendBeacon = TRUE; + } + + /*TDECTRL[15:8] 0x209[7:0] = 0xFE/0xFD NDPA Head for TXDMA*/ + ODM_Write1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+1, Head_Page); + + do { + /*Clear beacon valid check bit.*/ + BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2); + ODM_Write1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2, (BcnValidReg | BIT0)); + + // download NDPA rsvd page. + Beamforming_SendHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->SoundBW, BEACON_QUEUE); + +#if(DEV_BUS_TYPE == RT_PCI_INTERFACE) + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_MGQ_TXBD_NUM_8192E+3); + count = 0; + while ((count < 20) && (u1bTmp & BIT4)) { + count++; + ODM_delay_us(10); + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_MGQ_TXBD_NUM_8192E+3); + } + ODM_Write1Byte(pDM_Odm, REG_MGQ_TXBD_NUM_8192E+3, u1bTmp | BIT4); +#endif + + /*check rsvd page download OK.*/ + BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2); + count = 0; + while (!(BcnValidReg & BIT0) && count < 20) { + count++; + ODM_delay_us(10); + BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+2); + } + DLBcnCount++; + } while (!(BcnValidReg & BIT0) && DLBcnCount < 5); + + if (!(BcnValidReg & BIT0)) + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_WARNING, ("%s Download RSVD page failed!\n", __func__)); + + /*TDECTRL[15:8] 0x209[7:0] = 0xF9 Beacon Head for TXDMA*/ + ODM_Write1Byte(pDM_Odm, REG_DWBCN0_CTRL_8192E+1, TxPageBndy); + + /*To make sure that if there exists an adapter which would like to send beacon.*/ + /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ + /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/ + /*the beacon cannot be sent by HW.*/ + /*2010.06.23. Added by tynli.*/ + if (bSendBeacon) + ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8192E+2, tmpReg422); + + /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ + /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8192E+1); + ODM_Write1Byte(pDM_Odm, REG_CR_8192E+1, (u1bTmp & (~BIT0))); + + pBeamEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + *pDM_Odm->pbFwDwRsvdPageInProgress = FALSE; +#endif +} + + +VOID +HalTxbf8192E_Enter( + IN PVOID pDM_VOID, + IN u1Byte BFerBFeeIdx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i = 0; + u1Byte BFerIdx = (BFerBFeeIdx & 0xF0) >> 4; + u1Byte BFeeIdx = (BFerBFeeIdx & 0xF); + u4Byte CSI_Param; + PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + RT_BEAMFORMEE_ENTRY BeamformeeEntry; + RT_BEAMFORMER_ENTRY BeamformerEntry; + u2Byte STAid = 0; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + halTxbf8192E_RfMode(pDM_Odm, pBeamformingInfo); + + if (pDM_Odm->RFType == ODM_2T2R) + ODM_Write4Byte(pDM_Odm, 0xd80, 0x00000000); /*Nc =2*/ + + if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) { + BeamformerEntry = pBeamformingInfo->BeamformerEntry[BFerIdx]; + + /*Sounding protocol control*/ + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8192E, 0xCB); + + /*MAC address/Partial AID of Beamformer*/ + if (BFerIdx == 0) { + for (i = 0; i < 6 ; i++) + ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8192E+i), BeamformerEntry.MacAddr[i]); + } else { + for (i = 0; i < 6 ; i++) + ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER1_INFO_8192E+i), BeamformerEntry.MacAddr[i]); + } + + /*CSI report parameters of Beamformer Default use Nc = 2*/ + CSI_Param = 0x03090309; + + ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8192E, CSI_Param); + ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8192E, CSI_Param); + ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8192E, CSI_Param); + + /*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us, MP chip)*/ + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8192E+3, 0x50); + + } + + if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) { + BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[BFeeIdx]; + + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) + STAid = BeamformeeEntry.MacId; + else + STAid = BeamformeeEntry.P_AID; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s], STAid=0x%X\n", __func__, STAid)); + + /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ + if (BFeeIdx == 0) { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E, STAid); + ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8192E+3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8192E+3) | BIT4 | BIT6 | BIT7); + } else + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E+2, STAid | BIT12 | BIT14 | BIT15); + + /*CSI report parameters of Beamformee*/ + if (BFeeIdx == 0) { + /*Get BIT24 & BIT25*/ + u1Byte tmp = ODM_Read1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+3) & 0x3; + + ODM_Write1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+3, tmp | 0x60); + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E, STAid | BIT9); + } else { + /*Set BIT25*/ + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, STAid | 0xE200); + } + phydm_Beamforming_Notify(pDM_Odm); + + } +} + + +VOID +HalTxbf8192E_Leave( + IN PVOID pDM_VOID, + IN u1Byte Idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + + halTxbf8192E_RfMode(pDM_Odm, pBeamInfo); + + /* Clear P_AID of Beamformee + * Clear MAC addresss of Beamformer + * Clear Associated Bfmee Sel + */ + if (pBeamInfo->BeamformCap == BEAMFORMING_CAP_NONE) + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8192E, 0xC8); + + if (Idx == 0) { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E, 0); + ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8192E, 0); + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8192E+4, 0); + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E, 0); + } else { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8192E+2, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8192E+2) & 0xF000); + ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8192E, 0); + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8192E+4, 0); + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2, ODM_Read2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8192E+2) & 0x60); + } + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Idx %d\n", __func__, Idx)); +} + + +VOID +HalTxbf8192E_Status( + IN PVOID pDM_VOID, + IN u1Byte Idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u2Byte BeamCtrlVal; + u4Byte BeamCtrlReg; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + RT_BEAMFORMEE_ENTRY BeamformEntry = pBeamInfo->BeamformeeEntry[Idx]; + + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) + BeamCtrlVal = BeamformEntry.MacId; + else + BeamCtrlVal = BeamformEntry.P_AID; + + if (Idx == 0) + BeamCtrlReg = REG_TXBF_CTRL_8192E; + else { + BeamCtrlReg = REG_TXBF_CTRL_8192E+2; + BeamCtrlVal |= BIT12 | BIT14 | BIT15; + } + + if (BeamformEntry.BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (BeamformEntry.SoundBW == CHANNEL_WIDTH_20) + BeamCtrlVal |= BIT9; + else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_40) + BeamCtrlVal |= BIT10; + } else + BeamCtrlVal &= ~(BIT9 | BIT10 | BIT11); + + ODM_Write2Byte(pDM_Odm, BeamCtrlReg, BeamCtrlVal); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Idx %d BeamCtrlReg %x BeamCtrlVal %x\n", __func__, Idx, BeamCtrlReg, BeamCtrlVal)); +} + + +VOID +HalTxbf8192E_FwTxBF( + IN PVOID pDM_VOID, + IN u1Byte Idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (pBeamEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING) + halTxbf8192E_DownloadNDPA(pDM_Odm, Idx); + + halTxbf8192E_FwTxBFCmd(pDM_Odm); +} + +#endif /* #if (RTL8192E_SUPPORT == 1)*/ + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8192e.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8192e.h new file mode 100644 index 000000000..70357590c --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8192e.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __HAL_TXBF_8192E_H__ +#define __HAL_TXBF_8192E_H__ + +#if (BEAMFORMING_SUPPORT == 1) +#if (RTL8192E_SUPPORT == 1) +VOID +HalTxbf8192E_setNDPArate( + IN PVOID pDM_VOID, + IN u1Byte BW, + IN u1Byte Rate +); + +VOID +HalTxbf8192E_Enter( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + + +VOID +HalTxbf8192E_Leave( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + + +VOID +HalTxbf8192E_Status( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + + +VOID +HalTxbf8192E_FwTxBF( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); +#else + +#define HalTxbf8192E_setNDPArate(pDM_VOID, BW, Rate) +#define HalTxbf8192E_Enter(pDM_VOID, Idx) +#define HalTxbf8192E_Leave(pDM_VOID, Idx) +#define HalTxbf8192E_Status(pDM_VOID, Idx) +#define HalTxbf8192E_FwTxBF(pDM_VOID, Idx) + +#endif + +#endif + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8814a.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8814a.c new file mode 100644 index 000000000..96c6db906 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8814a.c @@ -0,0 +1,654 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//============================================================ +// Description: +// +// This file is for 8814A TXBF mechanism +// +//============================================================ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (BEAMFORMING_SUPPORT == 1) +#if (RTL8814A_SUPPORT == 1) + +VOID +HalTxbf8814A_setNDPArate( + IN PVOID pDM_VOID, + IN u1Byte BW, + IN u1Byte Rate +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8814A, BW); + ODM_Write1Byte(pDM_Odm, REG_NDPA_RATE_8814A, (u1Byte) Rate); + +} + +#define PHYDM_MEMORY_MAP_BUF_READ 0x8000 +#define PHYDM_CTRL_INFO_PAGE 0x660 + +VOID +phydm_DataRate_8814A( + IN PDM_ODM_T pDM_Odm, + IN u1Byte macId, + OUT pu4Byte data, + IN u1Byte dataLen + ) +{ + u1Byte i = 0; + u2Byte XReadDataAddr = 0; + + ODM_Write2Byte(pDM_Odm, REG_PKTBUF_DBG_CTRL_8814A, PHYDM_CTRL_INFO_PAGE); + XReadDataAddr = PHYDM_MEMORY_MAP_BUF_READ + macId*32; /*Ctrl Info: 32Bytes for each macid(n)*/ + + if ((XReadDataAddr < PHYDM_MEMORY_MAP_BUF_READ) || (XReadDataAddr > 0x8FFF)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("XReadDataAddr(0x%x) is not correct!\n", XReadDataAddr)); + return; + } + + /* Read data */ + for (i = 0; i < dataLen; i++) + *(data+i) = ODM_Read2Byte(pDM_Odm, XReadDataAddr+i); + +} + +VOID +HalTxbf8814A_GetTxRate( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMEE_ENTRY pEntry; + u4Byte TxRptData = 0; + u1Byte DataRate = 0xFF; + + pEntry = &(pBeamInfo->BeamformeeEntry[pBeamInfo->BeamformeeCurIdx]); + + phydm_DataRate_8814A(pDM_Odm, (u1Byte)pEntry->MacId, &TxRptData, 1); + DataRate = (u1Byte)TxRptData; + DataRate &= bMask7bits; /*Bit7 indicates SGI*/ + + pDM_Odm->TxBfDataRate = DataRate; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] pDM_Odm->TxBfDataRate = 0x%x\n", __func__, pDM_Odm->TxBfDataRate)); +} + +VOID +HalTxbf8814A_ResetTxPath( + IN PVOID pDM_VOID, + IN u1Byte idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; +#if DEV_BUS_TYPE == RT_USB_INTERFACE + + PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + RT_BEAMFORMEE_ENTRY BeamformeeEntry; + u1Byte Nr_index = 0; + + if (idx < BEAMFORMEE_ENTRY_NUM) + BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[idx]; + else + return; + + if ((pDM_Odm->LastUSBHub) != (*pDM_Odm->HubUsbMode)) { + Nr_index = TxBF_Nr(halTxbf8814A_GetNtx(pDM_Odm), BeamformeeEntry.CompSteeringNumofBFer); + + if (idx == 0) { + switch (Nr_index) { + case 0: + break; + + case 1: /*Nsts = 2 BC*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0, bMaskByte3LowNibble | bMaskL3Bytes, 0x9366); /*tx2path, BC*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1, bMaskL3Bytes, 0x936); + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2, bMaskLWord, 0x9360); + break; + + case 2: /*Nsts = 3 BCD*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0, bMaskByte3LowNibble | bMaskL3Bytes, 0x93e93ee); /*tx3path, BCD*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1, bMaskByte3 | bMaskByte2HighNibble, 0x93e); + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2, bMaskDWord, 0x93e93e0); + break; + + default: /*Nr>3, same as Case 3*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0, bMaskByte3LowNibble | bMaskL3Bytes, 0x93f93ff); /*tx4path, ABCD*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1, bMaskByte3 | bMaskByte2HighNibble, 0x93f); + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1, bMaskDWord, 0x93f93f0); + break; + } + } else { + switch (Nr_index) { + case 0: + break; + + case 1: /*Nsts = 2 BC*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1, bMaskByte3LowNibble | bMaskL3Bytes, 0x9366); /*tx2path, BC*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1, bMaskByte3 | bMaskByte2HighNibble, 0x936); + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2, bMaskLWord, 0x9360); + break; + + case 2: /*Nsts = 3 BCD*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1, bMaskByte3LowNibble | bMaskL3Bytes, 0x93e93ee); /*tx3path, BCD*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1, bMaskByte3 | bMaskByte2HighNibble, 0x93e); + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2, bMaskDWord, 0x93e93e0); + break; + + default: /*Nr>3, same as Case 3*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1, bMaskByte3LowNibble | bMaskL3Bytes, 0x93f93ff); /*tx4path, ABCD*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1, bMaskByte3 | bMaskByte2HighNibble, 0x93f); + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2, bMaskDWord, 0x93f93f0); + break; + } + } + + pDM_Odm->LastUSBHub = *pDM_Odm->HubUsbMode; + } else + return; +#endif +} + + +u1Byte +halTxbf8814A_GetNtx( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte Ntx = 0; + +#if DEV_BUS_TYPE == RT_USB_INTERFACE + if (pDM_Odm->SupportInterface == ODM_ITRF_USB) { + if (*pDM_Odm->HubUsbMode == 2) {/*USB3.0*/ + if (pDM_Odm->RFType == ODM_4T4R) + Ntx = 3; + else if (pDM_Odm->RFType == ODM_3T3R) + Ntx = 2; + else + Ntx = 1; + } else if (*pDM_Odm->HubUsbMode == 1) /*USB 2.0 always 2Tx*/ + Ntx = 1; + else + Ntx = 1; + } else +#endif + { + if (pDM_Odm->RFType == ODM_4T4R) + Ntx = 3; + else if (pDM_Odm->RFType == ODM_3T3R) + Ntx = 2; + else + Ntx = 1; + } + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Ntx = %d\n", __func__, Ntx)); + return Ntx; +} + +u1Byte +halTxbf8814A_GetNrx( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte Nrx = 0; + + if (pDM_Odm->RFType == ODM_4T4R) + Nrx = 3; + else if (pDM_Odm->RFType == ODM_3T3R) + Nrx = 2; + else if (pDM_Odm->RFType == ODM_2T2R) + Nrx = 1; + else if (pDM_Odm->RFType == ODM_2T3R) + Nrx = 2; + else if (pDM_Odm->RFType == ODM_2T4R) + Nrx = 3; + else if (pDM_Odm->RFType == ODM_1T1R) + Nrx = 0; + else if (pDM_Odm->RFType == ODM_1T2R) + Nrx = 1; + else + Nrx = 0; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Nrx = %d\n", __func__, Nrx)); + return Nrx; +} + +VOID +halTxbf8814A_RfMode( + IN PVOID pDM_VOID, + IN PRT_BEAMFORMING_INFO pBeamformingInfo, + IN u1Byte idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i, Nr_index = 0; + RT_BEAMFORMEE_ENTRY BeamformeeEntry; + + if (idx < BEAMFORMEE_ENTRY_NUM) + BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[idx]; + else + return; + + Nr_index = TxBF_Nr(halTxbf8814A_GetNtx(pDM_Odm), BeamformeeEntry.CompSteeringNumofBFer); + + if (pDM_Odm->RFType == ODM_1T1R) + return; + + for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++) { + ODM_SetRFReg(pDM_Odm, i, RF_WeLut_Jaguar, 0x80000, 0x1); + /*RF Mode table write enable*/ + } + + if (pBeamformingInfo->beamformee_su_cnt > 0) { + for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++) { + ODM_SetRFReg(pDM_Odm, i, RF_ModeTableAddr, 0xfffff, 0x18000); + /*Select RX mode*/ + ODM_SetRFReg(pDM_Odm, i, RF_ModeTableData0, 0xfffff, 0xBE77F); + /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, i, RF_ModeTableData1, 0xfffff, 0x226BF); + /*Enable TXIQGEN in RX mode*/ + } + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xE26BF); + /*Enable TXIQGEN in RX mode*/ + } + + for (i = ODM_RF_PATH_A; i < MAX_RF_PATH; i++) { + ODM_SetRFReg(pDM_Odm, i, RF_WeLut_Jaguar, 0x80000, 0x0); + /*RF Mode table write disable*/ + } + + if (pBeamformingInfo->beamformee_su_cnt > 0) { +#if DEV_BUS_TYPE == RT_USB_INTERFACE + pDM_Odm->LastUSBHub = *pDM_Odm->HubUsbMode; +#endif + + /*for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1, BIT28 | BIT29, 0x2); /*enable BB TxBF ant mapping register*/ + + if (idx == 0) { + switch (Nr_index) { + case 0: + break; + + case 1: /*Nsts = 2 BC*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0, bMaskByte3LowNibble | bMaskL3Bytes, 0x9366); /*tx2path, BC*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1, bMaskL3Bytes, 0x936); + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2, bMaskLWord, 0x9360); + break; + + case 2: /*Nsts = 3 BCD*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0, bMaskByte3LowNibble | bMaskL3Bytes, 0x93e93ee); /*tx3path, BCD*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1, bMaskByte3 | bMaskByte2HighNibble, 0x93e); + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2, bMaskDWord, 0x93e93e0); + break; + + default: /*Nr>3, same as Case 3*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0, bMaskByte3LowNibble | bMaskL3Bytes, 0x93f93ff); /*tx4path, ABCD*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1, bMaskByte3 | bMaskByte2HighNibble, 0x93f); + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1, bMaskDWord, 0x93f93f0); + break; + } + } else { + switch (Nr_index) { + case 0: + break; + + case 1: /*Nsts = 2 BC*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1, bMaskByte3LowNibble | bMaskL3Bytes, 0x9366); /*tx2path, BC*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1, bMaskByte3 | bMaskByte2HighNibble, 0x936); + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2, bMaskLWord, 0x9360); + break; + + case 2: /*Nsts = 3 BCD*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1, bMaskByte3LowNibble | bMaskL3Bytes, 0x93e93ee); /*tx3path, BCD*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1, bMaskByte3 | bMaskByte2HighNibble, 0x93e); + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2, bMaskDWord, 0x93e93e0); + break; + + default: /*Nr>3, same as Case 3*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1, bMaskByte3LowNibble | bMaskL3Bytes, 0x93f93ff); /*tx4path, ABCD*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1, bMaskByte3 | bMaskByte2HighNibble, 0x93f); + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2, bMaskDWord, 0x93f93f0); + break; + } + } + } + + if ((pBeamformingInfo->beamformee_su_cnt == 0) && (pBeamformingInfo->beamformer_su_cnt == 0)) { + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1, bMaskByte3 | bMaskByte2HighNibble, 0x932); /*set TxPath selection for 8814a BFer bug refine*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2, bMaskDWord, 0x93e9360); + } +} +#if 0 +VOID +halTxbf8814A_DownloadNDPA( + IN PADAPTER Adapter, + IN u1Byte Idx +) +{ + u1Byte u1bTmp = 0, tmpReg422 = 0; + u1Byte BcnValidReg = 0, count = 0, DLBcnCount = 0; + u2Byte Head_Page = 0x7FE; + BOOLEAN bSendBeacon = FALSE; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u2Byte TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*default reseved 1 page for the IC type which is undefined.*/ + PRT_BEAMFORMING_INFO pBeamInfo = GET_BEAMFORM_INFO(Adapter); + PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx; + + pHalData->bFwDwRsvdPageInProgress = TRUE; + Adapter->HalFunc.GetHalDefVarHandler(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (pu2Byte)&TxPageBndy); + + /*Set REG_CR bit 8. DMA beacon by SW.*/ + u1bTmp = PlatformEFIORead1Byte(Adapter, REG_CR_8814A + 1); + PlatformEFIOWrite1Byte(Adapter, REG_CR_8814A + 1, (u1bTmp | BIT0)); + + + /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/ + tmpReg422 = PlatformEFIORead1Byte(Adapter, REG_FWHW_TXQ_CTRL_8814A + 2); + PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL_8814A + 2, tmpReg422 & (~BIT6)); + + if (tmpReg422 & BIT6) { + RT_TRACE(COMP_INIT, DBG_LOUD, ("SetBeamformDownloadNDPA_8814A(): There is an Adapter is sending beacon.\n")); + bSendBeacon = TRUE; + } + + /*0x204[11:0] Beacon Head for TXDMA*/ + PlatformEFIOWrite2Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A, Head_Page); + + do { + /*Clear beacon valid check bit.*/ + BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A + 1); + PlatformEFIOWrite1Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A + 1, (BcnValidReg | BIT7)); + + /*download NDPA rsvd page.*/ + if (pBeamEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU) + Beamforming_SendVHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->AID, pBeamEntry->SoundBW, BEACON_QUEUE); + else + Beamforming_SendHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->SoundBW, BEACON_QUEUE); + + /*check rsvd page download OK.*/ + BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A + 1); + count = 0; + while (!(BcnValidReg & BIT7) && count < 20) { + count++; + delay_us(10); + BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A + 2); + } + DLBcnCount++; + } while (!(BcnValidReg & BIT7) && DLBcnCount < 5); + + if (!(BcnValidReg & BIT0)) + RT_DISP(FBEAM, FBEAM_ERROR, ("%s Download RSVD page failed!\n", __func__)); + + /*0x204[11:0] Beacon Head for TXDMA*/ + PlatformEFIOWrite2Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A, TxPageBndy); + + /*To make sure that if there exists an adapter which would like to send beacon.*/ + /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ + /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */ + /*the beacon cannot be sent by HW.*/ + /*2010.06.23. Added by tynli.*/ + if (bSendBeacon) + PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL_8814A + 2, tmpReg422); + + /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ + /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ + u1bTmp = PlatformEFIORead1Byte(Adapter, REG_CR_8814A + 1); + PlatformEFIOWrite1Byte(Adapter, REG_CR_8814A + 1, (u1bTmp & (~BIT0))); + + pBeamEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED; + + pHalData->bFwDwRsvdPageInProgress = FALSE; +} + +VOID +halTxbf8814A_FwTxBFCmd( + IN PADAPTER Adapter +) +{ + u1Byte Idx, Period = 0; + u1Byte PageNum0 = 0xFF, PageNum1 = 0xFF; + u1Byte u1TxBFParm[3] = {0}; + + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + PRT_BEAMFORMING_INFO pBeamInfo = GET_BEAMFORM_INFO(Adapter); + + for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { + if (pBeamInfo->BeamformeeEntry[Idx].bUsed && pBeamInfo->BeamformeeEntry[Idx].BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (pBeamInfo->BeamformeeEntry[Idx].bSound) { + PageNum0 = 0xFE; + PageNum1 = 0x07; + Period = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod); + } else if (PageNum0 == 0xFF) { + PageNum0 = 0xFF; /*stop sounding*/ + PageNum1 = 0x0F; + } + } + } + + u1TxBFParm[0] = PageNum0; + u1TxBFParm[1] = PageNum1; + u1TxBFParm[2] = Period; + FillH2CCmd(Adapter, PHYDM_H2C_TXBF, 3, u1TxBFParm); + + RT_DISP(FBEAM, FBEAM_FUN, ("@%s End, PageNum0 = 0x%x, PageNum1 = 0x%x Period = %d", __func__, PageNum0, PageNum1, Period)); +} +#endif +VOID +HalTxbf8814A_Enter( + IN PVOID pDM_VOID, + IN u1Byte BFerBFeeIdx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i = 0; + u1Byte BFerIdx = (BFerBFeeIdx & 0xF0) >> 4; + u1Byte BFeeIdx = (BFerBFeeIdx & 0xF); + PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + RT_BEAMFORMEE_ENTRY BeamformeeEntry; + RT_BEAMFORMER_ENTRY BeamformerEntry; + u2Byte STAid = 0, CSI_Param = 0; + u1Byte Nc_index = 0, Nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BFerIdx=%d, BFeeIdx=%d\n", __func__, BFerIdx, BFeeIdx)); + ODM_SetMACReg(pDM_Odm, REG_SND_PTCL_CTRL_8814A, bMaskByte1 | bMaskByte2, 0x0202); + + if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) { + BeamformerEntry = pBeamformingInfo->BeamformerEntry[BFerIdx]; + /*Sounding protocol control*/ + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8814A, 0xDB); + + /*MAC address/Partial AID of Beamformer*/ + if (BFerIdx == 0) { + for (i = 0; i < 6 ; i++) + ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8814A + i), BeamformerEntry.MacAddr[i]); + } else { + for (i = 0; i < 6 ; i++) + ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER1_INFO_8814A + i), BeamformerEntry.MacAddr[i]); + } + + /*CSI report parameters of Beamformer*/ + Nc_index = halTxbf8814A_GetNrx(pDM_Odm); /*for 8814A Nrx = 3(4 Ant), min=0(1 Ant)*/ + Nr_index = BeamformerEntry.NumofSoundingDim; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so Nr_index don't care*/ + + grouping = 0; + + /*for ac = 1, for n = 3*/ + if (BeamformerEntry.BeamformEntryCap & BEAMFORMEE_CAP_VHT_SU) + codebookinfo = 1; + else if (BeamformerEntry.BeamformEntryCap & BEAMFORMEE_CAP_HT_EXPLICIT) + codebookinfo = 3; + + coefficientsize = 3; + + CSI_Param = (u2Byte)((coefficientsize << 10) | (codebookinfo << 8) | (grouping << 6) | (Nr_index << 3) | (Nc_index)); + + if (BFerIdx == 0) + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8814A, CSI_Param); + else + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8814A + 2, CSI_Param); + /*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/ + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8814A + 3, 0x40); + + } + + if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) { + BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[BFeeIdx]; + + halTxbf8814A_RfMode(pDM_Odm, pBeamformingInfo, BFeeIdx); + + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) + STAid = BeamformeeEntry.MacId; + else + STAid = BeamformeeEntry.P_AID; + + /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ + if (BFeeIdx == 0) { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A, STAid); + ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 3) | BIT4 | BIT6 | BIT7); + } else + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 2, STAid | BIT14 | BIT15 | BIT12); + + /*CSI report parameters of Beamformee*/ + if (BFeeIdx == 0) { + /*Get BIT24 & BIT25*/ + u1Byte tmp = ODM_Read1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3) & 0x3; + + ODM_Write1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 3, tmp | 0x60); + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A, STAid | BIT9); + } else + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, STAid | 0xE200); /*Set BIT25*/ + + phydm_Beamforming_Notify(pDM_Odm); + } + +} + + +VOID +HalTxbf8814A_Leave( + IN PVOID pDM_VOID, + IN u1Byte Idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + RT_BEAMFORMER_ENTRY BeamformerEntry; + RT_BEAMFORMEE_ENTRY BeamformeeEntry; + + if (Idx < BEAMFORMER_ENTRY_NUM) { + BeamformerEntry = pBeamformingInfo->BeamformerEntry[Idx]; + BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[Idx]; + } else + return; + + /*Clear P_AID of Beamformee*/ + /*Clear MAC address of Beamformer*/ + /*Clear Associated Bfmee Sel*/ + + if (BeamformerEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) { + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8814A, 0xD8); + if (Idx == 0) { + ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8814A, 0); + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8814A + 4, 0); + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8814A, 0); + } else { + ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8814A, 0); + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8814A + 4, 0); + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8814A + 2, 0); + } + } + + if (BeamformeeEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) { + halTxbf8814A_RfMode(pDM_Odm, pBeamformingInfo, Idx); + if (Idx == 0) { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A, 0x0); + ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 3) | BIT4 | BIT6 | BIT7); + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A, 0); + } else { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A + 2, 0x0 | BIT14 | BIT15 | BIT12); + + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2, ODM_Read2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8814A + 2) & 0x60); + } + } +} + +VOID +HalTxbf8814A_Status( + IN PVOID pDM_VOID, + IN u1Byte Idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u2Byte BeamCtrlVal, tmpVal; + u4Byte BeamCtrlReg; + PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + RT_BEAMFORMEE_ENTRY BeamformEntry; + + if (Idx < BEAMFORMEE_ENTRY_NUM) + BeamformEntry = pBeamformingInfo->BeamformeeEntry[Idx]; + else + return; + + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) + BeamCtrlVal = BeamformEntry.MacId; + else + BeamCtrlVal = BeamformEntry.P_AID; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, BeamformEntry.BeamformEntryState = %d", __func__, BeamformEntry.BeamformEntryState)); + + if (Idx == 0) + BeamCtrlReg = REG_TXBF_CTRL_8814A; + else { + BeamCtrlReg = REG_TXBF_CTRL_8814A + 2; + BeamCtrlVal |= BIT12 | BIT14 | BIT15; + } + + if (BeamformEntry.BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (BeamformEntry.SoundBW == CHANNEL_WIDTH_20) + BeamCtrlVal |= BIT9; + else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_40) + BeamCtrlVal |= (BIT9 | BIT10); + else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_80) + BeamCtrlVal |= (BIT9 | BIT10 | BIT11); + } else { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, Don't apply Vmatrix", __func__)); + BeamCtrlVal &= ~(BIT9 | BIT10 | BIT11); + } + + ODM_Write2Byte(pDM_Odm, BeamCtrlReg, BeamCtrlVal); + /*disable NDP packet use beamforming */ + tmpVal = ODM_Read2Byte(pDM_Odm, REG_TXBF_CTRL_8814A); + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8814A, tmpVal | BIT15); + +} + + + + + +VOID +HalTxbf8814A_FwTxBF( + IN PVOID pDM_VOID, + IN u1Byte Idx +) +{ +#if 0 + PRT_BEAMFORMING_INFO pBeamInfo = GET_BEAMFORM_INFO(Adapter); + PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx; + + if (pBeamEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING) + halTxbf8814A_DownloadNDPA(Adapter, Idx); + + halTxbf8814A_FwTxBFCmd(Adapter); +#endif +} + +#endif /* (RTL8814A_SUPPORT == 1)*/ + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8814a.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8814a.h new file mode 100644 index 000000000..d06ecc21c --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8814a.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __HAL_TXBF_8814A_H__ +#define __HAL_TXBF_8814A_H__ + +#if (BEAMFORMING_SUPPORT == 1) +#if (RTL8814A_SUPPORT == 1) +VOID +HalTxbf8814A_setNDPArate( + IN PVOID pDM_VOID, + IN u1Byte BW, + IN u1Byte Rate +); + +u1Byte +halTxbf8814A_GetNtx( + IN PVOID pDM_VOID + ); + +VOID +HalTxbf8814A_Enter( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + + +VOID +HalTxbf8814A_Leave( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + + +VOID +HalTxbf8814A_Status( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + +VOID +HalTxbf8814A_ResetTxPath( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + + +VOID +HalTxbf8814A_GetTxRate( + IN PVOID pDM_VOID + ); + +VOID +HalTxbf8814A_FwTxBF( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); +#else + +#define HalTxbf8814A_setNDPArate(pDM_VOID, BW, Rate) +#define halTxbf8814A_GetNtx(pDM_VOID) 0 +#define HalTxbf8814A_Enter(pDM_VOID, Idx) +#define HalTxbf8814A_Leave(pDM_VOID, Idx) +#define HalTxbf8814A_Status(pDM_VOID, Idx) +#define HalTxbf8814A_ResetTxPath(pDM_VOID, Idx) +#define HalTxbf8814A_GetTxRate(pDM_VOID) +#define HalTxbf8814A_FwTxBF(pDM_VOID, Idx) +#endif + +#endif + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8821b.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8821b.c new file mode 100644 index 000000000..7ebe707f7 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8821b.c @@ -0,0 +1,401 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*============================================================*/ +/*Description:*/ +/*This file is for 8812/8821/8811 TXBF mechanism*/ +/*============================================================*/ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (BEAMFORMING_SUPPORT == 1) +#if (RTL8821B_SUPPORT == 1) + +VOID +halTxbf8821B_RfMode( + IN PVOID pDM_VOID, + IN PRT_BEAMFORMING_INFO pBeamInfo +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (pDM_Odm->RFType == ODM_1T1R) + return; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] set TxIQGen\n", __func__)); + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WeLut_Jaguar, 0x80000, 0x1); /*RF Mode table write enable*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WeLut_Jaguar, 0x80000, 0x1); /*RF Mode table write enable*/ + + if (pBeamInfo->beamformee_su_cnt > 0) { + /*Path_A*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/ + /*Path_B*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/ + } else { + /*Path_A*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xC26BF); /*Disable TXIQGEN in RX mode*/ + /*Path_B*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0xC26BF); /*Disable TXIQGEN in RX mode*/ + } + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WeLut_Jaguar, 0x80000, 0x0); /*RF Mode table write disable*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WeLut_Jaguar, 0x80000, 0x0); /*RF Mode table write disable*/ + + if (pBeamInfo->beamformee_su_cnt > 0) + ODM_SetBBReg(pDM_Odm, rTxPath_Jaguar, bMaskByte1, 0x33); + else + ODM_SetBBReg(pDM_Odm, rTxPath_Jaguar, bMaskByte1, 0x11); +} + +#if 0 +VOID +halTxbf8821B_DownloadNDPA( + IN PDM_ODM_T pDM_Odm, + IN u1Byte Idx +) +{ + u1Byte u1bTmp = 0, tmpReg422 = 0, Head_Page; + u1Byte BcnValidReg = 0, count = 0, DLBcnCount = 0; + BOOLEAN bSendBeacon = FALSE; + u1Byte TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; /*default reseved 1 page for the IC type which is undefined.*/ + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pDM_Odm->Adapter); + PADAPTER Adapter = pDM_Odm->Adapter; + + pHalData->bFwDwRsvdPageInProgress = TRUE; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (Idx == 0) + Head_Page = 0xFE; + else + Head_Page = 0xFE; + + Adapter->HalFunc.GetHalDefVarHandler(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (pu1Byte)&TxPageBndy); + + /*Set REG_CR bit 8. DMA beacon by SW.*/ + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8821B + 1); + ODM_Write1Byte(pDM_Odm, REG_CR_8821B + 1, (u1bTmp | BIT0)); + + + /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/ + tmpReg422 = ODM_Read1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8821B + 2); + ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8821B + 2, tmpReg422 & (~BIT6)); + + if (tmpReg422 & BIT6) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("SetBeamformDownloadNDPA_8812(): There is an Adapter is sending beacon.\n")); + bSendBeacon = TRUE; + } + + /*TDECTRL[15:8] 0x209[7:0] = 0xF6 Beacon Head for TXDMA*/ + ODM_Write1Byte(pDM_Odm, REG_TDECTRL_8812A + 1, Head_Page); + + do { + /*Clear beacon valid check bit.*/ + BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_TDECTRL_8812A + 2); + ODM_Write1Byte(pDM_Odm, REG_TDECTRL_8812A + 2, (BcnValidReg | BIT0)); + + /*download NDPA rsvd page.*/ + if (pBeamEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU) + Beamforming_SendVHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->AID, pBeamEntry->SoundBW, BEACON_QUEUE); + else + Beamforming_SendHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->SoundBW, BEACON_QUEUE); + + /*check rsvd page download OK.*/ + BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_TDECTRL_8812A + 2); + count = 0; + while (!(BcnValidReg & BIT0) && count < 20) { + count++; + ODM_delay_ms(10); + BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_TDECTRL_8812A + 2); + } + DLBcnCount++; + } while (!(BcnValidReg & BIT0) && DLBcnCount < 5); + + if (!(BcnValidReg & BIT0)) + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Download RSVD page failed!\n", __func__)); + + /*TDECTRL[15:8] 0x209[7:0] = 0xF6 Beacon Head for TXDMA*/ + ODM_Write1Byte(pDM_Odm, REG_TDECTRL_8812A + 1, TxPageBndy); + + /*To make sure that if there exists an adapter which would like to send beacon.*/ + /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ + /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/ + /*the beacon cannot be sent by HW.*/ + /*2010.06.23. Added by tynli.*/ + if (bSendBeacon) + ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8821B + 2, tmpReg422); + + /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ + /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8821B + 1); + ODM_Write1Byte(pDM_Odm, REG_CR_8821B + 1, (u1bTmp & (~BIT0))); + + pBeamEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED; + + pHalData->bFwDwRsvdPageInProgress = FALSE; +} + + +VOID +halTxbf8821B_FwTxBFCmd( + IN PDM_ODM_T pDM_Odm +) +{ + u1Byte Idx, Period0 = 0, Period1 = 0; + u1Byte PageNum0 = 0xFF, PageNum1 = 0xFF; + u1Byte u1TxBFParm[3] = {0}; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + + for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { + /*Modified by David*/ + if (pBeamInfo->BeamformeeEntry[Idx].bUsed && pBeamInfo->BeamformeeEntry[Idx].BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (Idx == 0) { + if (pBeamInfo->BeamformeeEntry[Idx].bSound) + PageNum0 = 0xFE; + else + PageNum0 = 0xFF; /*stop sounding*/ + Period0 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod); + } else if (Idx == 1) { + if (pBeamInfo->BeamformeeEntry[Idx].bSound) + PageNum1 = 0xFE; + else + PageNum1 = 0xFF; /*stop sounding*/ + Period1 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod); + } + } + } + + u1TxBFParm[0] = PageNum0; + u1TxBFParm[1] = PageNum1; + u1TxBFParm[2] = (Period1 << 4) | Period0; + FillH2CCmd(Adapter, PHYDM_H2C_TXBF, 3, u1TxBFParm); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, + ("[%s] PageNum0 = %d Period0 = %d, PageNum1 = %d Period1 %d\n", __func__, PageNum0, Period0, PageNum1, Period1)); +} + +#endif +VOID +HalTxbf8821B_Enter( + IN PVOID pDM_VOID, + IN u1Byte BFerBFeeIdx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i = 0; + u1Byte BFerIdx = (BFerBFeeIdx & 0xF0) >> 4; + u1Byte BFeeIdx = (BFerBFeeIdx & 0xF); + u4Byte CSI_Param; + PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + RT_BEAMFORMEE_ENTRY BeamformeeEntry; + RT_BEAMFORMER_ENTRY BeamformerEntry; + u2Byte STAid = 0; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Start!\n", __func__)); + + halTxbf8821B_RfMode(pDM_Odm, pBeamformingInfo); + + if (pDM_Odm->RFType == ODM_2T2R) + ODM_SetBBReg(pDM_Odm, ODM_REG_CSI_CONTENT_VALUE, bMaskDWord, 0x00000000); /*Nc =2*/ + else + ODM_SetBBReg(pDM_Odm, ODM_REG_CSI_CONTENT_VALUE, bMaskDWord, 0x01081008); /*Nc =1*/ + + if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) { + BeamformerEntry = pBeamformingInfo->BeamformerEntry[BFerIdx]; + + /*Sounding protocol control*/ + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8821B, 0xCB); + + /*MAC address/Partial AID of Beamformer*/ + if (BFerIdx == 0) { + for (i = 0; i < 6 ; i++) + ODM_Write1Byte(pDM_Odm, (REG_BFMER0_INFO_8812A + i), BeamformerEntry.MacAddr[i]); + /*CSI report use legacy ofdm so don't need to fill P_AID. */ + /*PlatformEFIOWrite2Byte(Adapter, REG_BFMER0_INFO_8821B+6, BeamformEntry.P_AID); */ + } else { + for (i = 0; i < 6 ; i++) + ODM_Write1Byte(pDM_Odm, (REG_BFMER1_INFO_8812A + i), BeamformerEntry.MacAddr[i]); + /*CSI report use legacy ofdm so don't need to fill P_AID.*/ + /*PlatformEFIOWrite2Byte(Adapter, REG_BFMER1_INFO_8821B+6, BeamformEntry.P_AID);*/ + } + + /*CSI report parameters of Beamformee*/ + if (BeamformerEntry.BeamformEntryCap & BEAMFORMEE_CAP_VHT_SU) { + if (pDM_Odm->RFType == ODM_2T2R) + CSI_Param = 0x01090109; + else + CSI_Param = 0x01080108; + } else { + if (pDM_Odm->RFType == ODM_2T2R) + CSI_Param = 0x03090309; + else + CSI_Param = 0x03080308; + } + + ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8821B, CSI_Param); + ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8821B, CSI_Param); + ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8821B, CSI_Param); + + /*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us, MP chip)*/ + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8821B + 3, 0x50); + } + + + if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) { + BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[BFeeIdx]; + + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) + STAid = BeamformeeEntry.MacId; + else + STAid = BeamformeeEntry.P_AID; + + /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ + if (BFeeIdx == 0) { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8821B, STAid); + ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8821B + 3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8821B + 3) | BIT4 | BIT6 | BIT7); + } else + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8821B + 2, STAid | BIT12 | BIT14 | BIT15); + + /*CSI report parameters of Beamformee*/ + if (BFeeIdx == 0) { + /*Get BIT24 & BIT25*/ + u1Byte tmp = ODM_Read1Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 3) & 0x3; + + ODM_Write1Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 3, tmp | 0x60); + ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A, STAid | BIT9); + } else { + /*Set BIT25*/ + ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 2, STAid | 0xE200); + } + phydm_Beamforming_Notify(pDM_Odm); + } +} + + +VOID +HalTxbf8821B_Leave( + IN PVOID pDM_VOID, + IN u1Byte Idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + RT_BEAMFORMER_ENTRY BeamformerEntry; + RT_BEAMFORMEE_ENTRY BeamformeeEntry; + + if (Idx < BEAMFORMER_ENTRY_NUM) { + BeamformerEntry = pBeamformingInfo->BeamformerEntry[Idx]; + BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[Idx]; + } else + return; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Start!, IDx = %d\n", __func__, Idx)); + + /*Clear P_AID of Beamformee*/ + /*Clear MAC address of Beamformer*/ + /*Clear Associated Bfmee Sel*/ + + if (BeamformerEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) { + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8821B, 0xC8); + if (Idx == 0) { + ODM_Write4Byte(pDM_Odm, REG_BFMER0_INFO_8812A, 0); + ODM_Write2Byte(pDM_Odm, REG_BFMER0_INFO_8812A + 4, 0); + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8821B, 0); + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8821B, 0); + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8821B, 0); + } else { + ODM_Write4Byte(pDM_Odm, REG_BFMER1_INFO_8812A, 0); + ODM_Write2Byte(pDM_Odm, REG_BFMER1_INFO_8812A + 4, 0); + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8821B, 0); + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8821B, 0); + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8821B, 0); + } + } + + if (BeamformeeEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) { + halTxbf8821B_RfMode(pDM_Odm, pBeamformingInfo); + if (Idx == 0) { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8821B, 0x0); + ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A, 0); + } else { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8821B + 2, ODM_Read2Byte(pDM_Odm, REG_TXBF_CTRL_8821B + 2) & 0xF000); + ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 2, ODM_Read2Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 2) & 0x60); + } + } + +} + + +VOID +HalTxbf8821B_Status( + IN PVOID pDM_VOID, + IN u1Byte Idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u2Byte BeamCtrlVal; + u4Byte BeamCtrlReg; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + RT_BEAMFORMEE_ENTRY BeamformEntry = pBeamInfo->BeamformeeEntry[Idx]; + + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) + BeamCtrlVal = BeamformEntry.MacId; + else + BeamCtrlVal = BeamformEntry.P_AID; + + if (Idx == 0) + BeamCtrlReg = REG_TXBF_CTRL_8821B; + else { + BeamCtrlReg = REG_TXBF_CTRL_8821B + 2; + BeamCtrlVal |= BIT12 | BIT14 | BIT15; + } + + if (BeamformEntry.BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (BeamformEntry.SoundBW == CHANNEL_WIDTH_20) + BeamCtrlVal |= BIT9; + else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_40) + BeamCtrlVal |= BIT10; + else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_80) + BeamCtrlVal |= BIT11; + } else + BeamCtrlVal &= ~(BIT9 | BIT10 | BIT11); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BeamCtrlVal = 0x%x!\n", __func__, BeamCtrlVal)); + + ODM_Write2Byte(pDM_Odm, BeamCtrlReg, BeamCtrlVal); +} + + + +VOID +HalTxbf8821B_FwTxBF( + IN PVOID pDM_VOID, + IN u1Byte Idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); +#if 0 + if (pBeamEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING) + halTxbf8821B_DownloadNDPA(pDM_Odm, Idx); + + halTxbf8821B_FwTxBFCmd(pDM_Odm); +#endif +} + +#endif + + +#endif diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8821b.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8821b.h new file mode 100644 index 000000000..149a8a405 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8821b.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __HAL_TXBF_8821B_H__ +#define __HAL_TXBF_8821B_H__ +#if (BEAMFORMING_SUPPORT == 1) +#if (RTL8821B_SUPPORT == 1) +VOID +HalTxbf8821B_Enter( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + + +VOID +HalTxbf8821B_Leave( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + + +VOID +HalTxbf8821B_Status( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + + +VOID +HalTxbf8821B_FwTxBF( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + +#else +#define HalTxbf8821B_Enter(pDM_VOID, Idx) +#define HalTxbf8821B_Leave(pDM_VOID, Idx) +#define HalTxbf8821B_Status(pDM_VOID, Idx) +#define HalTxbf8821B_FwTxBF(pDM_VOID, Idx) +#endif + + +#endif + +#endif // #ifndef __HAL_TXBF_8821B_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8822b.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8822b.c new file mode 100644 index 000000000..4708546fc --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8822b.c @@ -0,0 +1,1100 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*============================================================*/ +/* Description: */ +/* */ +/* This file is for 8814A TXBF mechanism */ +/* */ +/*============================================================*/ + +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (BEAMFORMING_SUPPORT == 1) +#if (RTL8822B_SUPPORT == 1) + +#if 0 +VOID +HalTxbf8814A_GetBeamformcap( + IN PADAPTER Adapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + PRT_BEAMFORMING_INFO pBeamformingInfo = GET_BEAMFORM_INFO(Adapter); + BEAMFORMING_CAP BeamformCap = BEAMFORMING_CAP_NONE; + + BeamformCap = phydm_Beamforming_GetBeamCap(pDM_Odm, pBeamformingInfo); + + if (BeamformCap == pBeamformingInfo->BeamformCap) + return; + else + pBeamformingInfo->BeamformCap = BeamformCap; + +} + +VOID +HalTxbf8814A_GetTxRate( + IN PADAPTER Adapter +) +{ + + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + PRT_BEAMFORMING_INFO pBeamInfo = GET_BEAMFORM_INFO(Adapter); + PRT_BEAMFORMEE_ENTRY pEntry; + u4Byte TxRptData = 0; + u1Byte DataRate = 0xFF; + + pEntry = &(pBeamInfo->BeamformeeEntry[pBeamInfo->BeamformeeCurIdx]); + + ReadSdramData_8814A(Adapter, (u1Byte)pEntry->MacId, LOC_8814A_CTRL_INFO, &TxRptData, 1); + DataRate = (u1Byte)TxRptData; + DataRate &= bMask7bits; /*Bit7 indicates SGI*/ + + pDM_Odm->TxBfDataRate = DataRate; + +} + +VOID +HalTxbf8814A_ResetTxPath( + IN PADAPTER Adapter, + IN u1Byte idx +) +{ +#if DEV_BUS_TYPE == RT_USB_INTERFACE + + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + PRT_BEAMFORMING_INFO pBeamformingInfo = GET_BEAMFORM_INFO(Adapter); + RT_BEAMFORMEE_ENTRY BeamformeeEntry; + u1Byte Nr_index = 0; + + if (idx < BEAMFORMEE_ENTRY_NUM) + BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[idx]; + else + return; + + if ((pDM_Odm->LastUSBHub) != (RT_GetHubUSBMode(Adapter))) { + Nr_index = TxBF_Nr(halTxbf8814A_GetNtx(Adapter), BeamformeeEntry.CompSteeringNumofBFer); + + if (idx == 0) { + switch (Nr_index) { + case 0: + break; + + case 1: /*Nsts = 2 BC*/ + PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, BIT3|BIT2|BIT1|BIT0, 0x6); /*1ss*/ + PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, BIT7|BIT6|BIT5|BIT4, 0x6); /*2ss*/ + PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, 0x0000ff00, 0x10); /*BC*/ + PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_1, BIT23|BIT22|BIT21|BIT20, 0x6); /*set TxPath selection for 8814a BFer bug refine*/ + PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_1, bMaskByte3, 0x10); /*if Bfer enable, always use 3Tx for all Spatial stream*/ + PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_2, bMaskLWord, 0x1060); + break; + + case 2: /*Nsts = 3 BCD*/ + PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, BIT3|BIT2|BIT1|BIT0, 0xe); /*1ss*/ + PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, BIT7|BIT6|BIT5|BIT4, 0xe); /*2ss*/ + PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, 0x0000ff00, 0x90); /*BCD*/ + PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, BIT19|BIT18|BIT17|BIT16, 0xe); /*3ss*/ + PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, 0xff00000, 0x90); /*bcd*/ + PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_1, BIT23|BIT22|BIT21|BIT20, 0xe); /*set TxPath selection for 8814a BFer bug refine*/ + PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_1, bMaskByte3, 0x90); /*if Bfer enable, always use 3Tx for all Spatial stream*/ + PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_2, bMaskDWord, 0x90e90e0); + break; + + default: /*Nr>3, same as Case 3*/ + PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, BIT3|BIT2|BIT1|BIT0, 0xf); /*1ss*/ + PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, BIT7|BIT6|BIT5|BIT4, 0xf); /*2ss*/ + PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, 0x0000ff00, 0x93); /*BC*/ + PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, BIT19|BIT18|BIT17|BIT16, 0xf); /*3ss*/ + PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF0, 0xff00000, 0x93); /*bcd*/ + PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_1, BIT23|BIT22|BIT21|BIT20, 0xf); /*set TxPath selection for 8814a BFer bug refine*/ + PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_1, bMaskByte3, 0x93); /*if Bfer enable, always use 3Tx for all Spatial stream*/ + PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_2, bMaskDWord, 0x93f93f0); + break; + } + } else { + switch (Nr_index) { + case 0: + break; + + case 1: /*Nsts = 2 BC*/ + PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF1, BIT3|BIT2|BIT1|BIT0, 0x6); /*1ss*/ + PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF1, BIT7|BIT6|BIT5|BIT4, 0x6); /*2ss*/ + PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF1, 0x0000ff00, 0x10); /*BC*/ + PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_1, BIT23|BIT22|BIT21|BIT20, 0x6); /*set TxPath selection for 8814a BFer bug refine*/ + PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_1, bMaskByte3, 0x10); /*if Bfer enable, always use 3Tx for all Spatial stream*/ + PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_2, bMaskLWord, 0x1060); + break; + + case 2: /*Nsts = 3 BCD*/ + PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF1, BIT3|BIT2|BIT1|BIT0, 0xe); /*1ss*/ + PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF1, BIT7|BIT6|BIT5|BIT4, 0xe); /*2ss*/ + PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF1, 0x0000ff00, 0x90); /*BC*/ + PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF1, BIT19|BIT18|BIT17|BIT16, 0xe); /*3ss*/ + PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF1, 0xff00000, 0x90); /*bcd*/ + PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_1, BIT23|BIT22|BIT21|BIT20, 0xe); /*set TxPath selection for 8814a BFer bug refine*/ + PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_1, bMaskByte3, 0x90); /*if Bfer enable, always use 3Tx for all Spatial stream*/ + PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_2, bMaskDWord, 0x90e90e0); + break; + + default: /*Nr>3, same as Case 3*/ + PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF1, BIT3|BIT2|BIT1|BIT0, 0xf); /*1ss*/ + PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF1, BIT7|BIT6|BIT5|BIT4, 0xf); /*2ss*/ + PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF1, 0x0000ff00, 0x93); /*BC*/ + PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF1, BIT19|BIT18|BIT17|BIT16, 0xf); /*3ss*/ + PHY_SetBBReg(Adapter, REG_BB_TXBF_ANT_SET_BF1, 0xff00000, 0x93); /*bcd*/ + PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_1, BIT23|BIT22|BIT21|BIT20, 0xf); /*set TxPath selection for 8814a BFer bug refine*/ + PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_1, bMaskByte3, 0x93); /*if Bfer enable, always use 3Tx for all Spatial stream*/ + PHY_SetBBReg(Adapter, REG_BB_TX_PATH_SEL_2, bMaskDWord, 0x93f93f0); + break; + + } + } + + pDM_Odm->LastUSBHub = RT_GetHubUSBMode(Adapter); + } + else + return; +#endif +} +#endif + +u1Byte +halTxbf8822B_GetNtx( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte Ntx = 0; + +#if DEV_BUS_TYPE == RT_USB_INTERFACE + if (pDM_Odm->SupportInterface == ODM_ITRF_USB) { + if (*pDM_Odm->HubUsbMode == 2) {/*USB3.0*/ + if (pDM_Odm->RFType == ODM_4T4R) + Ntx = 3; + else if (pDM_Odm->RFType == ODM_3T3R) + Ntx = 2; + else + Ntx = 1; + } else if (*pDM_Odm->HubUsbMode == 1) /*USB 2.0 always 2Tx*/ + Ntx = 1; + else + Ntx = 1; + } else +#endif + { + if (pDM_Odm->RFType == ODM_4T4R) + Ntx = 3; + else if (pDM_Odm->RFType == ODM_3T3R) + Ntx = 2; + else + Ntx = 1; + } + + return Ntx; + +} + +u1Byte +halTxbf8822B_GetNrx( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte Nrx = 0; + + if (pDM_Odm->RFType == ODM_4T4R) + Nrx = 3; + else if (pDM_Odm->RFType == ODM_3T3R) + Nrx = 2; + else if (pDM_Odm->RFType == ODM_2T2R) + Nrx = 1; + else if (pDM_Odm->RFType == ODM_2T3R) + Nrx = 2; + else if (pDM_Odm->RFType == ODM_2T4R) + Nrx = 3; + else if (pDM_Odm->RFType == ODM_1T1R) + Nrx = 0; + else if (pDM_Odm->RFType == ODM_1T2R) + Nrx = 1; + else + Nrx = 0; + + return Nrx; + +} + +/***************SU & MU BFee Entry********************/ +VOID +halTxbf8822B_RfMode( + IN PVOID pDM_VOID, + IN PRT_BEAMFORMING_INFO pBeamformingInfo, + IN u1Byte idx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i, Nr_index = 0; + BOOLEAN bSelfBeamformer = FALSE; + BOOLEAN bSelfBeamformee = FALSE; + RT_BEAMFORMEE_ENTRY BeamformeeEntry; + + if (idx < BEAMFORMEE_ENTRY_NUM) + BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[idx]; + else + return; + + if (pDM_Odm->RFType == ODM_1T1R) + return; + + for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_B; i++) { + ODM_SetRFReg(pDM_Odm, i, RF_WeLut_Jaguar, 0x80000, 0x1); + /*RF Mode table write enable*/ + } + + if ((pBeamformingInfo->beamformee_su_cnt > 0) || (pBeamformingInfo->beamformee_mu_cnt > 0)) { + for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_B; i++) { + ODM_SetRFReg(pDM_Odm, i, RF_ModeTableAddr, 0xfffff, 0x18000); + /*Select RX mode*/ + ODM_SetRFReg(pDM_Odm, i, RF_ModeTableData0, 0xfffff, 0xBE77F); + /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, i, RF_ModeTableData1, 0xfffff, 0x226BF); + /*Enable TXIQGEN in RX mode*/ + } + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xE26BF); + /*Enable TXIQGEN in RX mode*/ + } + + for (i = ODM_RF_PATH_A; i < ODM_RF_PATH_B; i++) { + ODM_SetRFReg(pDM_Odm, i, RF_WeLut_Jaguar, 0x80000, 0x0); + /*RF Mode table write disable*/ + } + + if (pBeamformingInfo->beamformee_su_cnt > 0) { + + /*for 8814 19ac(idx 1), 19b4(idx 0), different Tx ant setting*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1, BIT28|BIT29, 0x2); /*enable BB TxBF ant mapping register*/ + + if (idx == 0) { + /*Nsts = 2 AB*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF0, 0xffff, 0x0433); + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1, 0xfff00000, 0x043); + /*ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2, bMaskLWord, 0x430);*/ + + } else {/*IDX =1*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1, 0xffff, 0x0433); + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1, 0xfff00000, 0x043); + /*ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2, bMaskLWord, 0x430;*/ + } + } else { + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1, 0xfff00000, 0x1); /*1SS by path-A*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_2, bMaskLWord, 0x430); /*2SS by path-A,B*/ + } + + if (pBeamformingInfo->beamformee_mu_cnt > 0) { + /*MU STAs share the common setting*/ + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1, BIT31, 1); + ODM_SetBBReg(pDM_Odm, REG_BB_TXBF_ANT_SET_BF1, 0xffff, 0x0433); + ODM_SetBBReg(pDM_Odm, REG_BB_TX_PATH_SEL_1, 0xfff00000, 0x043); + } + +} +#if 0 +VOID +halTxbf8822B_DownloadNDPA( + IN PADAPTER Adapter, + IN u1Byte Idx + ) +{ + u1Byte u1bTmp = 0, tmpReg422 = 0; + u1Byte BcnValidReg = 0, count = 0, DLBcnCount = 0; + u2Byte Head_Page = 0x7FE; + BOOLEAN bSendBeacon = FALSE; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u2Byte TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8814A; /*default reseved 1 page for the IC type which is undefined.*/ + PRT_BEAMFORMING_INFO pBeamInfo = GET_BEAMFORM_INFO(Adapter); + PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry+Idx; + + pHalData->bFwDwRsvdPageInProgress = TRUE; + Adapter->HalFunc.GetHalDefVarHandler(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (pu2Byte)&TxPageBndy); + + /*Set REG_CR bit 8. DMA beacon by SW.*/ + u1bTmp = PlatformEFIORead1Byte(Adapter, REG_CR_8814A+1); + PlatformEFIOWrite1Byte(Adapter, REG_CR_8814A+1, (u1bTmp|BIT0)); + + + /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/ + tmpReg422 = PlatformEFIORead1Byte(Adapter, REG_FWHW_TXQ_CTRL_8814A+2); + PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL_8814A+2, tmpReg422&(~BIT6)); + + if (tmpReg422 & BIT6) { + RT_TRACE(COMP_INIT, DBG_LOUD, ("SetBeamformDownloadNDPA_8814A(): There is an Adapter is sending beacon.\n")); + bSendBeacon = TRUE; + } + + /*0x204[11:0] Beacon Head for TXDMA*/ + PlatformEFIOWrite2Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A, Head_Page); + + do { + /*Clear beacon valid check bit.*/ + BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A+1); + PlatformEFIOWrite1Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A+1, (BcnValidReg|BIT7)); + + /*download NDPA rsvd page.*/ + if (pBeamEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU) + Beamforming_SendVHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->AID, pBeamEntry->SoundBW, BEACON_QUEUE); + else + Beamforming_SendHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->SoundBW, BEACON_QUEUE); + + /*check rsvd page download OK.*/ + BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A + 1); + count = 0; + while (!(BcnValidReg & BIT7) && count < 20) { + count++; + delay_us(10); + BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A+2); + } + DLBcnCount++; + } while (!(BcnValidReg & BIT7) && DLBcnCount < 5); + + if (!(BcnValidReg & BIT0)) + RT_DISP(FBEAM, FBEAM_ERROR, ("%s Download RSVD page failed!\n", __func__)); + + /*0x204[11:0] Beacon Head for TXDMA*/ + PlatformEFIOWrite2Byte(Adapter, REG_FIFOPAGE_CTRL_2_8814A, TxPageBndy); + + /*To make sure that if there exists an adapter which would like to send beacon.*/ + /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ + /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */ + /*the beacon cannot be sent by HW.*/ + /*2010.06.23. Added by tynli.*/ + if (bSendBeacon) + PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL_8814A+2, tmpReg422); + + /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ + /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ + u1bTmp = PlatformEFIORead1Byte(Adapter, REG_CR_8814A+1); + PlatformEFIOWrite1Byte(Adapter, REG_CR_8814A+1, (u1bTmp&(~BIT0))); + + pBeamEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED; + + pHalData->bFwDwRsvdPageInProgress = FALSE; +} + +VOID +halTxbf8822B_FwTxBFCmd( + IN PADAPTER Adapter + ) +{ + u1Byte Idx, Period = 0; + u1Byte PageNum0 = 0xFF, PageNum1 = 0xFF; + u1Byte u1TxBFParm[3] = {0}; + + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + PRT_BEAMFORMING_INFO pBeamInfo = GET_BEAMFORM_INFO(Adapter); + + for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { + if (pBeamInfo->BeamformeeEntry[Idx].bUsed && pBeamInfo->BeamformeeEntry[Idx].BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (pBeamInfo->BeamformeeEntry[Idx].bSound) { + PageNum0 = 0xFE; + PageNum1 = 0x07; + Period = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod); + } else if (PageNum0 == 0xFF) { + PageNum0 = 0xFF; /*stop sounding*/ + PageNum1 = 0x0F; + } + } + } + + u1TxBFParm[0] = PageNum0; + u1TxBFParm[1] = PageNum1; + u1TxBFParm[2] = Period; + FillH2CCmd(Adapter, PHYDM_H2C_TXBF, 3, u1TxBFParm); + + RT_DISP(FBEAM, FBEAM_FUN, ("@%s End, PageNum0 = 0x%x, PageNum1 = 0x%x Period = %d", __func__, PageNum0, PageNum1, Period)); +} +#endif + +VOID +HalTxbf8822B_Init( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte u1bTmp; + PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + + ODM_SetBBReg(pDM_Odm, 0x14c0 , BIT16, 1); /*Enable P1 aggr new packet according to P0 transfer time*/ + ODM_SetBBReg(pDM_Odm, 0x14c0 , BIT15|BIT14|BIT13|BIT12, 1); /*MU Retry Limit*/ + ODM_SetBBReg(pDM_Odm, 0x14c0 , BIT7, 0); /*Disable Tx MU-MIMO until sounding done*/ + ODM_SetBBReg(pDM_Odm, 0x14c0 , 0x3F, 0); /* Clear validity of MU STAs */ + ODM_Write1Byte(pDM_Odm, 0x167c , 0x70); /*MU-MIMO Option as default value*/ + ODM_Write2Byte(pDM_Odm, 0x1680 , 0); /*MU-MIMO Control as default value*/ + + /* Set MU NDPA rate & BW source */ + /* 0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */ + u1bTmp = ODM_Read1Byte(pDM_Odm, 0x42C); + ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8822B, (u1bTmp|BIT6)); + /* 0x45F[7:0] = 0x10 (Rate=OFDM_6M, BW20) */ + ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8822B, 0x10); + + /* Init HW variable */ + pBeamformingInfo->RegMUTxCtrl = ODM_Read4Byte(pDM_Odm, 0x14c0); +} + +VOID +HalTxbf8822B_Enter( + IN PVOID pDM_VOID, + IN u1Byte BFerBFeeIdx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i = 0; + u1Byte BFerIdx = (BFerBFeeIdx & 0xF0)>>4; + u1Byte BFeeIdx = (BFerBFeeIdx & 0xF); + u2Byte CSI_Param = 0; + PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMEE_ENTRY pBeamformeeEntry; + PRT_BEAMFORMER_ENTRY pBeamformerEntry; + u2Byte value16, STAid = 0; + u1Byte Nc_index = 0, Nr_index = 0, grouping = 0, codebookinfo = 0, coefficientsize = 0; + u4Byte gid_valid, user_position_l, user_position_h; + u4Byte mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e}; + u1Byte u1bTmp; + u4Byte u4bTmp; + + RT_DISP(FBEAM, FBEAM_FUN, ("%s: BFerBFeeIdx=%d, BFerIdx=%d, BFeeIdx=%d\n", __func__, BFerBFeeIdx, BFerIdx, BFeeIdx)); + + /*************SU BFer Entry Init*************/ + if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) { + pBeamformerEntry = &pBeamformingInfo->BeamformerEntry[BFerIdx]; + pBeamformerEntry->is_mu_ap = FALSE; + /*Sounding protocol control*/ + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B, 0xDB); + + + for (i = 0; i < MAX_BEAMFORMER_SU; i++) { + if ((pBeamformingInfo->beamformer_su_reg_maping & BIT(i)) == 0) { + pBeamformingInfo->beamformer_su_reg_maping |= BIT(i); + pBeamformerEntry->su_reg_index = i; + break; + } + } + + /*MAC address/Partial AID of Beamformer*/ + if (pBeamformerEntry->su_reg_index == 0) { + for (i = 0; i < 6 ; i++) + ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8822B+i), pBeamformerEntry->MacAddr[i]); + } else { + for (i = 0; i < 6 ; i++) + ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER1_INFO_8822B+i), pBeamformerEntry->MacAddr[i]); + } + + /*CSI report parameters of Beamformer*/ + Nc_index = halTxbf8822B_GetNrx(pDM_Odm); /*for 8814A Nrx = 3(4 Ant), min=0(1 Ant)*/ + Nr_index = pBeamformerEntry->NumofSoundingDim; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so Nr_index don't care*/ + + grouping = 0; + + /*for ac = 1, for n = 3*/ + if (pBeamformerEntry->BeamformEntryCap & BEAMFORMEE_CAP_VHT_SU) + codebookinfo = 1; + else if (pBeamformerEntry->BeamformEntryCap & BEAMFORMEE_CAP_HT_EXPLICIT) + codebookinfo = 3; + + coefficientsize = 3; + + CSI_Param = (u2Byte)((coefficientsize<<10)|(codebookinfo<<8)|(grouping<<6)|(Nr_index<<3)|(Nc_index)); + + if (BFerIdx == 0) + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8822B, CSI_Param); + else + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8822B+2, CSI_Param); + /*ndp_rx_standby_timer, 8814 need > 0x56, suggest from Dvaid*/ + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8814A+3, 0x70); + + } + + /*************SU BFee Entry Init*************/ + if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) { + pBeamformeeEntry = &pBeamformingInfo->BeamformeeEntry[BFeeIdx]; + pBeamformeeEntry->is_mu_sta = FALSE; + halTxbf8822B_RfMode(pDM_Odm, pBeamformingInfo, BFeeIdx); + + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) + STAid = pBeamformeeEntry->MacId; + else + STAid = pBeamformeeEntry->P_AID; + + for (i = 0; i < MAX_BEAMFORMEE_SU; i++) { + if ((pBeamformingInfo->beamformee_su_reg_maping & BIT(i)) == 0) { + pBeamformingInfo->beamformee_su_reg_maping |= BIT(i); + pBeamformeeEntry->su_reg_index = i; + break; + } + } + + /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ + if (pBeamformeeEntry->su_reg_index == 0) { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8822B, STAid); + ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3)|BIT4|BIT6|BIT7); + } else { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8822B+2, STAid | BIT14 | BIT15 | BIT12); + } + + /*CSI report parameters of Beamformee*/ + if (pBeamformeeEntry->su_reg_index == 0) { + /*Get BIT24 & BIT25*/ + u1Byte tmp = ODM_Read1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B+3) & 0x3; + + ODM_Write1Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B + 3, tmp | 0x60); + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B, STAid | BIT9); + } else + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B+2, STAid | 0xE200); /*Set BIT25*/ + + phydm_Beamforming_Notify(pDM_Odm); + } + + /*************MU BFer Entry Init*************/ + if ((pBeamformingInfo->beamformer_mu_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) { + pBeamformerEntry = &pBeamformingInfo->BeamformerEntry[BFerIdx]; + pBeamformingInfo->mu_ap_index = BFerIdx; + pBeamformerEntry->is_mu_ap = TRUE; + for (i = 0; i < 8; i++) + pBeamformerEntry->gid_valid[i] = 0; + for (i = 0; i < 16; i++) + pBeamformerEntry->user_position[i] = 0; + + /*Sounding protocol control*/ + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B, 0xDB); + + /* MAC address */ + for (i = 0; i < 6 ; i++) + ODM_Write1Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8822B+i), pBeamformerEntry->MacAddr[i]); + + /* Set partial AID */ + ODM_Write2Byte(pDM_Odm, (REG_ASSOCIATED_BFMER0_INFO_8822B+6), pBeamformerEntry->P_AID); + + /* Fill our AID to 0x1680[11:0] and [13:12] = 2b'00, BF report segment select to 3895 bytes*/ + u1bTmp = ODM_Read1Byte(pDM_Odm, 0x1680); + u1bTmp = (pBeamformerEntry->AID)&0xFFF; + ODM_Write1Byte(pDM_Odm, 0x1680, u1bTmp); + + /* Set 80us for leaving ndp_rx_standby_state */ + ODM_Write1Byte(pDM_Odm, 0x71B, 0x50); + + /* Set 0x6A0[14] = 1 to accept action_no_ack */ + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_RXFLTMAP0_8822B+1); + u1bTmp |= 0x40; + ODM_Write1Byte(pDM_Odm, REG_RXFLTMAP0_8822B+1, u1bTmp); + /* Set 0x6A2[5:4] = 1 to NDPA and BF report poll */ + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_RXFLTMAP1_8822B); + u1bTmp |= 0x30; + ODM_Write1Byte(pDM_Odm, REG_RXFLTMAP1_8822B, u1bTmp); + + /*CSI report parameters of Beamformer*/ + Nc_index = halTxbf8822B_GetNrx(pDM_Odm); /* Depend on RF type */ + Nr_index = 1; /*0x718[7] = 1 use Nsts, 0x718[7] = 0 use reg setting. as Bfee, we use Nsts, so Nr_index don't care*/ + grouping = 0; /*no grouping*/ + codebookinfo = 1; /*7 bit for psi, 9 bit for phi*/ + coefficientsize = 0; /*This is nothing really matter*/ + CSI_Param = (u2Byte)((coefficientsize<<10)|(codebookinfo<<8)|(grouping<<6)|(Nr_index<<3)|(Nc_index)); + ODM_Write2Byte(pDM_Odm, 0x6F4, CSI_Param); + + } + + /*************MU BFee Entry Init*************/ + if ((pBeamformingInfo->beamformee_mu_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) { + pBeamformeeEntry = &pBeamformingInfo->BeamformeeEntry[BFeeIdx]; + pBeamformeeEntry->is_mu_sta = TRUE; + for (i = 0; i < MAX_BEAMFORMEE_MU; i++) { + if ((pBeamformingInfo->beamformee_mu_reg_maping & BIT(i)) == 0) { + pBeamformingInfo->beamformee_mu_reg_maping |= BIT(i); + pBeamformeeEntry->mu_reg_index = i; + break; + } + } + + if (pBeamformeeEntry->mu_reg_index == 0xFF) { + /* There is no valid bit in beamformee_mu_reg_maping */ + RT_DISP(FBEAM, FBEAM_FUN, ("%s: ERROR! There is no valid bit in beamformee_mu_reg_maping!\n", __func__)); + return; + } + + /*User position table*/ + switch (pBeamformeeEntry->mu_reg_index) { + case 0: + gid_valid = 0x7fe; + user_position_l = 0x111110; + user_position_h = 0x0; + break; + case 1: + gid_valid = 0x7f806; + user_position_l = 0x11000004; + user_position_h = 0x11; + break; + case 2: + gid_valid = 0x1f81818; + user_position_l = 0x400040; + user_position_h = 0x11100; + break; + case 3: + gid_valid = 0x1e186060; + user_position_l = 0x4000400; + user_position_h = 0x1100040; + break; + case 4: + gid_valid = 0x66618180; + user_position_l = 0x40004000; + user_position_h = 0x10040400; + break; + case 5: + gid_valid = 0x79860600; + user_position_l = 0x40000; + user_position_h = 0x4404004; + break; + } + + for (i = 0; i < 8; i++) { + if (i < 4) { + pBeamformeeEntry->gid_valid[i] = (u1Byte)(gid_valid & 0xFF); + gid_valid = (gid_valid >> 8); + } else + pBeamformeeEntry->gid_valid[i] = 0; + } + for (i = 0; i < 16; i++) { + if (i < 4) { + pBeamformeeEntry->user_position[i] = (u1Byte)(user_position_l & 0xFF); + user_position_l = user_position_l >> 8; + } else if (i < 8) { + pBeamformeeEntry->user_position[i] = (u1Byte)(user_position_h & 0xFF); + user_position_h = user_position_h >> 8; + } else + pBeamformeeEntry->user_position[i] = 0; + } + + /*Sounding protocol control*/ + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B, 0xDB); + + /*select MU STA table*/ + pBeamformingInfo->RegMUTxCtrl &= ~(BIT8|BIT9|BIT10); + pBeamformingInfo->RegMUTxCtrl |= (pBeamformeeEntry->mu_reg_index << 8)&(BIT8|BIT9|BIT10); + ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); + + ODM_SetBBReg(pDM_Odm, 0x14c4 , bMaskDWord, 0); /*Reset gid_valid table*/ + ODM_SetBBReg(pDM_Odm, 0x14c8 , bMaskDWord, user_position_l); + ODM_SetBBReg(pDM_Odm, 0x14cc , bMaskDWord, user_position_h); + + /*set validity of MU STAs*/ + pBeamformingInfo->RegMUTxCtrl &= 0xFFFFFFC0; + pBeamformingInfo->RegMUTxCtrl |= pBeamformingInfo->beamformee_mu_reg_maping&0x3F; + ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); + + value16 = ODM_Read2Byte(pDM_Odm, mu_reg[pBeamformeeEntry->mu_reg_index]); + value16 &= 0xFE00; /*Clear PAID*/ + value16 |= BIT9; /*Enable MU BFee*/ + value16 |= pBeamformeeEntry->P_AID; + ODM_Write2Byte(pDM_Odm, mu_reg[pBeamformeeEntry->mu_reg_index] , value16); + + /* 0x42C[30] = 1 (0: from Tx desc, 1: from 0x45F) */ + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3); + u1bTmp |= 0xD0; /* Set bit 28, 30, 31 to 3b'111*/ + ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3, u1bTmp); + /* Set NDPA to 6M*/ + ODM_Write1Byte(pDM_Odm, REG_NDPA_RATE_8822B, 0x4); /* 6M */ + + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8822B); + u1bTmp &= 0xFC; /* Clear bit 0, 1*/ + ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8822B, u1bTmp); + + u4bTmp = ODM_Read4Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B); + u4bTmp = ((u4bTmp & 0xFF0000FF) | 0x020200); /* Set [23:8] to 0x0202 */ + ODM_Write4Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B, u4bTmp); + + /* Set 0x6A0[14] = 1 to accept action_no_ack */ + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_RXFLTMAP0_8822B+1); + u1bTmp |= 0x40; + ODM_Write1Byte(pDM_Odm, REG_RXFLTMAP0_8822B+1, u1bTmp); + /* End of MAC registers setting */ + + halTxbf8822B_RfMode(pDM_Odm, pBeamformingInfo, BFeeIdx); +#if (SUPPORT_MU_BF == 1) + /*Special for plugfest*/ + delay_ms(50); /* wait for 4-way handshake ending*/ + SendSWVHTGIDMgntFrame(pDM_Odm, pBeamformeeEntry->MacAddr, BFeeIdx); +#endif + + phydm_Beamforming_Notify(pDM_Odm); + + } + +} + + +VOID +HalTxbf8822B_Leave( + IN PVOID pDM_VOID, + IN u1Byte Idx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMER_ENTRY pBeamformerEntry; + PRT_BEAMFORMEE_ENTRY pBeamformeeEntry; + u4Byte mu_reg[6] = {0x1684, 0x1686, 0x1688, 0x168a, 0x168c, 0x168e}; + + if (Idx < BEAMFORMER_ENTRY_NUM) { + pBeamformerEntry = &pBeamformingInfo->BeamformerEntry[Idx]; + pBeamformeeEntry = &pBeamformingInfo->BeamformeeEntry[Idx]; + } else + return; + + /*Clear P_AID of Beamformee*/ + /*Clear MAC address of Beamformer*/ + /*Clear Associated Bfmee Sel*/ + + if (pBeamformerEntry->BeamformEntryCap == BEAMFORMING_CAP_NONE) { + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8822B, 0xD8); + if (pBeamformerEntry->is_mu_ap == 0) { /*SU BFer */ + if (pBeamformerEntry->su_reg_index == 0) { + ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8822B, 0); + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER0_INFO_8822B+4, 0); + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8822B, 0); + } else { + ODM_Write4Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8822B, 0); + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMER1_INFO_8822B+4, 0); + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8822B+2, 0); + } + pBeamformingInfo->beamformer_su_reg_maping &= ~(BIT(pBeamformerEntry->su_reg_index)); + pBeamformerEntry->su_reg_index = 0xFF; + } else { /*MU BFer */ + /*set validity of MU STA0 and MU STA1*/ + pBeamformingInfo->RegMUTxCtrl &= 0xFFFFFFC0; + ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); + + ODM_Memory_Set(pDM_Odm, pBeamformerEntry->gid_valid, 0, 8); + ODM_Memory_Set(pDM_Odm, pBeamformerEntry->user_position, 0, 16); + pBeamformerEntry->is_mu_ap = FALSE; + } + } + + if (pBeamformeeEntry->BeamformEntryCap == BEAMFORMING_CAP_NONE) { + halTxbf8822B_RfMode(pDM_Odm, pBeamformingInfo, Idx); + if (pBeamformeeEntry->is_mu_sta == 0) { /*SU BFee*/ + if (pBeamformeeEntry->su_reg_index == 0) { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8822B, 0x0); + ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8822B+3)|BIT4|BIT6|BIT7); + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B, 0); + } else { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8822B+2, 0x0 | BIT14 | BIT15 | BIT12); + + ODM_Write2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B+2, + ODM_Read2Byte(pDM_Odm, REG_ASSOCIATED_BFMEE_SEL_8822B+2) & 0x60); + } + pBeamformingInfo->beamformee_su_reg_maping &= ~(BIT(pBeamformeeEntry->su_reg_index)); + pBeamformeeEntry->su_reg_index = 0xFF; + } else { /*MU BFee */ + /*Disable sending NDPA & BF-rpt-poll to this BFee*/ + ODM_Write2Byte(pDM_Odm, mu_reg[pBeamformeeEntry->mu_reg_index] , 0); + /*set validity of MU STA*/ + pBeamformingInfo->RegMUTxCtrl &= ~(BIT(pBeamformeeEntry->mu_reg_index)); + ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); + + + pBeamformeeEntry->is_mu_sta = FALSE; + pBeamformingInfo->beamformee_mu_reg_maping &= ~(BIT(pBeamformeeEntry->mu_reg_index)); + pBeamformeeEntry->mu_reg_index = 0xFF; + } + } +} + + +/***********SU & MU BFee Entry Only when souding done****************/ +VOID +HalTxbf8822B_Status( + IN PVOID pDM_VOID, + IN u1Byte Idx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u2Byte BeamCtrlVal, tmpVal; + u4Byte BeamCtrlReg; + PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMEE_ENTRY pBeamformEntry; + BOOLEAN is_mu_sounding = pBeamformingInfo->is_mu_sounding, is_bitmap_ready = FALSE; + u16 bitmap; + u8 idx, gid, i; + u8 id1, id0; + u32 gid_valid[6] = {0}; + u32 user_position_lsb[6] = {0}; + u32 user_position_msb[6] = {0}; + u32 value32; + + if (Idx < BEAMFORMEE_ENTRY_NUM) + pBeamformEntry = &pBeamformingInfo->BeamformeeEntry[Idx]; + else + return; + + /*SU sounding done */ + if (is_mu_sounding == FALSE) { + + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) + BeamCtrlVal = pBeamformEntry->MacId; + else + BeamCtrlVal = pBeamformEntry->P_AID; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, BeamformEntry.BeamformEntryState = %d", __func__, pBeamformEntry->BeamformEntryState)); + + if (pBeamformEntry->su_reg_index == 0) { + BeamCtrlReg = REG_TXBF_CTRL_8822B; + } else { + BeamCtrlReg = REG_TXBF_CTRL_8822B+2; + BeamCtrlVal |= BIT12|BIT14|BIT15; + } + + if (pBeamformEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (pBeamformEntry->SoundBW == CHANNEL_WIDTH_20) + BeamCtrlVal |= BIT9; + else if (pBeamformEntry->SoundBW == CHANNEL_WIDTH_40) + BeamCtrlVal |= (BIT9|BIT10); + else if (pBeamformEntry->SoundBW == CHANNEL_WIDTH_80) + BeamCtrlVal |= (BIT9|BIT10|BIT11); + } else { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("@%s, Don't apply Vmatrix", __func__)); + BeamCtrlVal &= ~(BIT9|BIT10|BIT11); + } + + ODM_Write2Byte(pDM_Odm, BeamCtrlReg, BeamCtrlVal); + /*disable NDP packet use beamforming */ + tmpVal = ODM_Read2Byte(pDM_Odm, REG_TXBF_CTRL_8822B); + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8822B, tmpVal|BIT15); + } else { + /*MU sounding done */ + if (pBeamformEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + /*value32 = ODM_GetBBReg(pDM_Odm, 0xF4C, 0xFFFF0000);*/ + value32 = 1; + + is_bitmap_ready = (BOOLEAN)((value32 & BIT15) >> 15); + bitmap = (u16)(value32 & 0x3FFF); + + for (idx = 0; idx < 15; idx++) { + if (idx < 5) {/*bit0~4*/ + id0 = 0; + id1 = (u8)(idx + 1); + } else if (idx < 9) { /*bit5~8*/ + id0 = 1; + id1 = (u8)(idx - 3); + } else if (idx < 12) { /*bit9~11*/ + id0 = 2; + id1 = (u8)(idx - 6); + } else if (idx < 14) { /*bit12~13*/ + id0 = 3; + id1 = (u8)(idx - 8); + } else { /*bit14*/ + id0 = 4; + id1 = (u8)(idx - 9); + } + if (bitmap & BIT(idx)) { + /*Pair 1*/ + gid = (idx << 1) + 1; + gid_valid[id0] |= (BIT(gid)); + gid_valid[id1] |= (BIT(gid)); + /*Pair 2*/ + gid += 1; + gid_valid[id0] |= (BIT(gid)); + gid_valid[id1] |= (BIT(gid)); + } else { + /*Pair 1*/ + gid = (idx << 1) + 1; + gid_valid[id0] &= ~(BIT(gid)); + gid_valid[id1] &= ~(BIT(gid)); + /*Pair 2*/ + gid += 1; + gid_valid[id0] &= ~(BIT(gid)); + gid_valid[id1] &= ~(BIT(gid)); + } + } + + for (i = 0; i < BEAMFORMEE_ENTRY_NUM; i++) { + pBeamformEntry = &pBeamformingInfo->BeamformeeEntry[i]; + if ((pBeamformEntry->is_mu_sta) && (pBeamformEntry->mu_reg_index < 6)) { + value32 = gid_valid[pBeamformEntry->mu_reg_index]; + for (idx = 0; idx < 4; idx++) { + pBeamformEntry->gid_valid[idx] = (u8)(value32 & 0xFF); + value32 = (value32 >> 8); + } + } + } + + for (idx = 0; idx < 6; idx++) { + pBeamformingInfo->RegMUTxCtrl |= ~(BIT8|BIT9|BIT10); + pBeamformingInfo->RegMUTxCtrl |= ((idx<<8)&(BIT8|BIT9|BIT10)); + ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); + ODM_SetMACReg(pDM_Odm, 0x14C4, bMaskDWord, gid_valid[idx]); /*set MU STA gid valid table*/ + } + + /*Enable TxMU PPDU*/ + pBeamformingInfo->RegMUTxCtrl |= BIT7; + ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); + } + } +} + +/*Only used for MU BFer Entry when get GID management frame (self is as MU STA)*/ +VOID +HalTxbf8822B_ConfigGtab( + IN PVOID pDM_VOID + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMER_ENTRY pBeamformerEntry = NULL; + u4Byte gid_valid = 0, user_position_l = 0, user_position_h = 0, i; + + if (pBeamformingInfo->mu_ap_index < BEAMFORMER_ENTRY_NUM) + pBeamformerEntry = &pBeamformingInfo->BeamformerEntry[pBeamformingInfo->mu_ap_index]; + else + return; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s==>\n", __func__)); + + /*For GID 0~31*/ + for (i = 0; i < 4; i++) + gid_valid |= (pBeamformerEntry->gid_valid[i] << (i<<3)); + for (i = 0; i < 8; i++) { + if (i < 4) + user_position_l |= (pBeamformerEntry->user_position[i] << (i << 3)); + else + user_position_h |= (pBeamformerEntry->user_position[i] << ((i - 4)<<3)); + } + /*select MU STA0 table*/ + pBeamformingInfo->RegMUTxCtrl &= ~(BIT8|BIT9|BIT10); + ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); + ODM_SetBBReg(pDM_Odm, 0x14c4, bMaskDWord, gid_valid); + ODM_SetBBReg(pDM_Odm, 0x14c8, bMaskDWord, user_position_l); + ODM_SetBBReg(pDM_Odm, 0x14cc, bMaskDWord, user_position_h); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: STA0: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", + __func__, gid_valid, user_position_l, user_position_h)); + + gid_valid = 0; + user_position_l = 0; + user_position_h = 0; + + /*For GID 32~64*/ + for (i = 4; i < 8; i++) + gid_valid |= (pBeamformerEntry->gid_valid[i] << ((i - 4)<<3)); + for (i = 8; i < 16; i++) { + if (i < 4) + user_position_l |= (pBeamformerEntry->user_position[i] << ((i - 8) << 3)); + else + user_position_h |= (pBeamformerEntry->user_position[i] << ((i - 12) << 3)); + } + /*select MU STA1 table*/ + pBeamformingInfo->RegMUTxCtrl &= ~(BIT8|BIT9|BIT10); + pBeamformingInfo->RegMUTxCtrl |= BIT8; + ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); + ODM_SetBBReg(pDM_Odm, 0x14c4, bMaskDWord, gid_valid); + ODM_SetBBReg(pDM_Odm, 0x14c8, bMaskDWord, user_position_l); + ODM_SetBBReg(pDM_Odm, 0x14cc, bMaskDWord, user_position_h); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s: STA1: gid_valid = 0x%x, user_position_l = 0x%x, user_position_h = 0x%x\n", + __func__, gid_valid, user_position_l, user_position_h)); + + /* Set validity of MU STA0 and MU STA1*/ + pBeamformingInfo->RegMUTxCtrl &= 0xFFFFFFC0; + pBeamformingInfo->RegMUTxCtrl |= 0x3; /* STA0, STA1*/ + ODM_Write4Byte(pDM_Odm, 0x14c0, pBeamformingInfo->RegMUTxCtrl); + +} + + + +#if 0 +/*This function translate the bitmap to GTAB*/ +VOID +haltxbf8822b_gtab_translation( + IN PDM_ODM_T pDM_Odm +) +{ + u8 idx, gid; + u8 id1, id0; + u32 gid_valid[6] = {0}; + u32 user_position_lsb[6] = {0}; + u32 user_position_msb[6] = {0}; + + for (idx = 0; idx < 15; idx++) { + if (idx < 5) {/*bit0~4*/ + id0 = 0; + id1 = (u8)(idx + 1); + } else if (idx < 9) { /*bit5~8*/ + id0 = 1; + id1 = (u8)(idx - 3); + } else if (idx < 12) { /*bit9~11*/ + id0 = 2; + id1 = (u8)(idx - 6); + } else if (idx < 14) { /*bit12~13*/ + id0 = 3; + id1 = (u8)(idx - 8); + } else { /*bit14*/ + id0 = 4; + id1 = (u8)(idx - 9); + } + + /*Pair 1*/ + gid = (idx << 1) + 1; + gid_valid[id0] |= (1 << gid); + gid_valid[id1] |= (1 << gid); + if (gid < 16) { + /*user_position_lsb[id0] |= (0 << (gid << 1));*/ + user_position_lsb[id1] |= (1 << (gid << 1)); + } else { + /*user_position_msb[id0] |= (0 << ((gid - 16) << 1));*/ + user_position_msb[id1] |= (1 << ((gid - 16) << 1)); + } + + /*Pair 2*/ + gid += 1; + gid_valid[id0] |= (1 << gid); + gid_valid[id1] |= (1 << gid); + if (gid < 16) { + user_position_lsb[id0] |= (1 << (gid << 1)); + /*user_position_lsb[id1] |= (0 << (gid << 1));*/ + } else { + user_position_msb[id0] |= (1 << ((gid - 16) << 1)); + /*user_position_msb[id1] |= (0 << ((gid - 16) << 1));*/ + } + + } + + + for (idx = 0; idx < 6; idx++) { + /*DbgPrint("gid_valid[%d] = 0x%x\n", idx, gid_valid[idx]); + DbgPrint("user_position[%d] = 0x%x %x\n", idx, user_position_msb[idx], user_position_lsb[idx]);*/ + } +} +#endif + +VOID +HalTxbf8822B_FwTxBF( + IN PVOID pDM_VOID, + IN u1Byte Idx + ) +{ +#if 0 + PRT_BEAMFORMING_INFO pBeamInfo = GET_BEAMFORM_INFO(Adapter); + PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry+Idx; + + if (pBeamEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING) + halTxbf8822B_DownloadNDPA(Adapter, Idx); + + halTxbf8822B_FwTxBFCmd(Adapter); +#endif +} + +#else /* (RTL8822B_SUPPORT == 1)*/ + +#endif /* (RTL8822B_SUPPORT == 1)*/ + +#endif /*(BEAMFORMING_SUPPORT == 1)*/ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8822b.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8822b.h new file mode 100644 index 000000000..2d4ddb3a8 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbf8822b.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __HAL_TXBF_8822B_H__ +#define __HAL_TXBF_8822B_H__ +#if (BEAMFORMING_SUPPORT == 1) +#if (RTL8822B_SUPPORT == 1) + +VOID +HalTxbf8822B_Init( + IN PVOID pDM_VOID + ); + +VOID +HalTxbf8822B_Enter( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + + +VOID +HalTxbf8822B_Leave( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + + +VOID +HalTxbf8822B_Status( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + +VOID +HalTxbf8822B_ConfigGtab( + IN PVOID pDM_VOID + ); + +VOID +HalTxbf8822B_FwTxBF( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); +#else +#define HalTxbf8822B_Init(pDM_VOID) +#define HalTxbf8822B_Enter(pDM_VOID, Idx) +#define HalTxbf8822B_Leave(pDM_VOID, Idx) +#define HalTxbf8822B_Status(pDM_VOID, Idx) +#define HalTxbf8822B_FwTxBF(pDM_VOID, Idx) +#define HalTxbf8822B_ConfigGtab(pDM_VOID) +#endif + + +#endif +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbfinterface.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbfinterface.c new file mode 100644 index 000000000..0305a6b9c --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbfinterface.c @@ -0,0 +1,1385 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//============================================================ +// Description: +// +// This file is for TXBF interface mechanism +// +//============================================================ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (BEAMFORMING_SUPPORT == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +Beamforming_GidPAid( + PADAPTER Adapter, + PRT_TCB pTcb +) +{ + u1Byte Idx = 0; + u1Byte RA[6] ={0}; + pu1Byte pHeader = GET_FRAME_OF_FIRST_FRAG(Adapter, pTcb); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + + if (Adapter->HardwareType < HARDWARE_TYPE_RTL8192EE) + return; + else if (IS_WIRELESS_MODE_N(Adapter) == FALSE) + return; + +#if (SUPPORT_MU_BF == 1) + if (pTcb->TxBFPktType == RT_BF_PKT_TYPE_BROADCAST_NDPA) { /* MU NDPA */ +#else + if (0) { +#endif + /* Fill G_ID and P_AID */ + pTcb->G_ID = 63; + if (pBeamInfo->FirstMUBFeeIndex < BEAMFORMEE_ENTRY_NUM) { + pTcb->P_AID = pBeamInfo->BeamformeeEntry[pBeamInfo->FirstMUBFeeIndex].P_AID; + RT_DISP(FBEAM, FBEAM_FUN, ("[David]@%s End, G_ID=0x%X, P_AID=0x%X\n", __func__, pTcb->G_ID, pTcb->P_AID)); + } + } else { + GET_80211_HDR_ADDRESS1(pHeader, &RA); + + // VHT SU PPDU carrying one or more group addressed MPDUs or + // Transmitting a VHT NDP intended for multiple recipients + if (MacAddr_isBcst(RA) || MacAddr_isMulticast(RA) || pTcb->macId == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST) { + pTcb->G_ID = 63; + pTcb->P_AID = 0; + } else if (ACTING_AS_AP(Adapter)) { + u2Byte AID = (u2Byte) (MacIdGetOwnerAssociatedClientAID(Adapter, pTcb->macId) & 0x1ff); /*AID[0:8]*/ + + /*RT_DISP(FBEAM, FBEAM_FUN, ("@%s pTcb->macId=0x%X, AID=0x%X\n", __func__, pTcb->macId, AID));*/ + pTcb->G_ID = 63; + + if (AID == 0) /*A PPDU sent by an AP to a non associated STA*/ + pTcb->P_AID = 0; + else { /*Sent by an AP and addressed to a STA associated with that AP*/ + u2Byte BSSID = 0; + GET_80211_HDR_ADDRESS2(pHeader, &RA); + BSSID = ((RA[5] & 0xf0) >> 4) ^ (RA[5] & 0xf); /*BSSID[44:47] xor BSSID[40:43]*/ + pTcb->P_AID = (AID + BSSID *32) & 0x1ff; /*(dec(A) + dec(B)*32) mod 512*/ + } + } else if (ACTING_AS_IBSS(Adapter)) { + pTcb->G_ID = 63; + /*P_AID for infrasturcture mode; MACID for ad-hoc mode. */ + pTcb->P_AID = pTcb->macId; + } else if (MgntLinkStatusQuery(Adapter)) { /*Addressed to AP*/ + pTcb->G_ID = 0; + GET_80211_HDR_ADDRESS1(pHeader, &RA); + pTcb->P_AID = RA[5]; /*RA[39:47]*/ + pTcb->P_AID = (pTcb->P_AID << 1) | (RA[4] >> 7 ); + } else { + pTcb->G_ID = 63; + pTcb->P_AID = 0; + } + /*RT_DISP(FBEAM, FBEAM_FUN, ("[David]@%s End, G_ID=0x%X, P_AID=0x%X\n", __func__, pTcb->G_ID, pTcb->P_AID));*/ + } +} + + +RT_STATUS +Beamforming_GetReportFrame( + IN PADAPTER Adapter, + IN PRT_RFD pRfd, + IN POCTET_STRING pPduOS + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + PRT_BEAMFORMEE_ENTRY pBeamformEntry = NULL; + pu1Byte pMIMOCtrlField, pCSIReport, pCSIMatrix; + u1Byte Idx, Nc, Nr, CH_W; + u2Byte CSIMatrixLen = 0; + + ACT_PKT_TYPE pktType = ACT_PKT_TYPE_UNKNOWN; + + //Memory comparison to see if CSI report is the same with previous one + pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, Frame_Addr2(*pPduOS), &Idx); + + if (pBeamformEntry == NULL) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Beamforming_GetReportFrame: Cannot find entry by addr\n")); + return RT_STATUS_FAILURE; + } + + pktType = PacketGetActionFrameType(pPduOS); + + //-@ Modified by David + if (pktType == ACT_PKT_VHT_COMPRESSED_BEAMFORMING) { + pMIMOCtrlField = pPduOS->Octet + 26; + Nc = ((*pMIMOCtrlField) & 0x7) + 1; + Nr = (((*pMIMOCtrlField) & 0x38) >> 3) + 1; + CH_W = (((*pMIMOCtrlField) & 0xC0) >> 6); + pCSIMatrix = pMIMOCtrlField + 3 + Nc; //24+(1+1+3)+2 MAC header+(Category+ActionCode+MIMOControlField) +SNR(Nc=2) + CSIMatrixLen = pPduOS->Length - 26 -3 -Nc; + } else if (pktType == ACT_PKT_HT_COMPRESSED_BEAMFORMING) { + pMIMOCtrlField = pPduOS->Octet + 26; + Nc = ((*pMIMOCtrlField) & 0x3) + 1; + Nr = (((*pMIMOCtrlField) & 0xC) >> 2) + 1; + CH_W = (((*pMIMOCtrlField) & 0x10) >> 4); + pCSIMatrix = pMIMOCtrlField + 6 + Nr; //24+(1+1+6)+2 MAC header+(Category+ActionCode+MIMOControlField) +SNR(Nc=2) + CSIMatrixLen = pPduOS->Length - 26 -6 -Nr; + } else + return RT_STATUS_SUCCESS; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] idx=%d, pkt type=%d, Nc=%d, Nr=%d, CH_W=%d\n", __func__, Idx, pktType, Nc, Nr, CH_W)); + + return RT_STATUS_SUCCESS; +} + + +VOID +ConstructHTNDPAPacket( + PADAPTER Adapter, + pu1Byte RA, + pu1Byte Buffer, + pu4Byte pLength, + CHANNEL_WIDTH BW + ) +{ + u2Byte Duration= 0; + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + OCTET_STRING pNDPAFrame,ActionContent; + u1Byte ActionHdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c}; + + PlatformZeroMemory(Buffer, 32); + + SET_80211_HDR_FRAME_CONTROL(Buffer,0); + + SET_80211_HDR_ORDER(Buffer, 1); + SET_80211_HDR_TYPE_AND_SUBTYPE(Buffer,Type_Action_No_Ack); + + SET_80211_HDR_ADDRESS1(Buffer, RA); + SET_80211_HDR_ADDRESS2(Buffer, Adapter->CurrentAddress); + SET_80211_HDR_ADDRESS3(Buffer, pMgntInfo->Bssid); + + Duration = 2*aSifsTime + 40; + + if (BW == CHANNEL_WIDTH_40) + Duration+= 87; + else + Duration+= 180; + + SET_80211_HDR_DURATION(Buffer, Duration); + + //HT control field + SET_HT_CTRL_CSI_STEERING(Buffer+sMacHdrLng, 3); + SET_HT_CTRL_NDP_ANNOUNCEMENT(Buffer+sMacHdrLng, 1); + + FillOctetString(pNDPAFrame, Buffer, sMacHdrLng+sHTCLng); + + FillOctetString(ActionContent, ActionHdr, 4); + PacketAppendData(&pNDPAFrame, ActionContent); + + *pLength = 32; +} + + + + +BOOLEAN +SendFWHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN CHANNEL_WIDTH BW + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PRT_TCB pTcb; + PRT_TX_LOCAL_BUFFER pBuf; + BOOLEAN ret = TRUE; + u4Byte BufLen; + pu1Byte BufAddr; + u1Byte DescLen = 0, Idx = 0, NDPTxRate; + PADAPTER pDefAdapter = GetDefaultAdapter(Adapter); + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (pBeamformEntry == NULL) + return FALSE; + + NDPTxRate = Beamforming_GetHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); + PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); + + if (MgntGetFWBuffer(pDefAdapter, &pTcb, &pBuf)) { +#if(DEV_BUS_TYPE != RT_PCI_INTERFACE) + DescLen = Adapter->HWDescHeadLength - pHalData->USBALLDummyLength; +#endif + BufAddr = pBuf->Buffer.VirtualAddress + DescLen; + + ConstructHTNDPAPacket( + Adapter, + RA, + BufAddr, + &BufLen, + BW + ); + + pTcb->PacketLength = BufLen + DescLen; + + pTcb->bTxEnableSwCalcDur = TRUE; + + pTcb->BWOfPacket = BW; + + if(ACTING_AS_IBSS(Adapter) || ACTING_AS_AP(Adapter)) + pTcb->G_ID = 63; + + pTcb->P_AID = pBeamformEntry->P_AID; + pTcb->DataRate = NDPTxRate; /*rate of NDP decide by Nr*/ + + Adapter->HalFunc.CmdSendPacketHandler(Adapter, pTcb, pBuf, pTcb->PacketLength, DESC_PACKET_TYPE_NORMAL, FALSE); + } else + ret = FALSE; + + PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); + + if (ret) + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); + + return ret; +} + + +BOOLEAN +SendSWHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN CHANNEL_WIDTH BW + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PRT_TCB pTcb; + PRT_TX_LOCAL_BUFFER pBuf; + BOOLEAN ret = TRUE; + u1Byte Idx = 0, NDPTxRate = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + NDPTxRate = Beamforming_GetHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); + + PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); + + if (MgntGetBuffer(Adapter, &pTcb, &pBuf)) { + ConstructHTNDPAPacket( + Adapter, + RA, + pBuf->Buffer.VirtualAddress, + &pTcb->PacketLength, + BW + ); + + pTcb->bTxEnableSwCalcDur = TRUE; + + pTcb->BWOfPacket = BW; + + MgntSendPacket(Adapter, pTcb, pBuf, pTcb->PacketLength, NORMAL_QUEUE, NDPTxRate); + } else + ret = FALSE; + + PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); + + if (ret) + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); + + return ret; +} + + + +VOID +ConstructVHTNDPAPacket( + IN PDM_ODM_T pDM_Odm, + pu1Byte RA, + u2Byte AID, + pu1Byte Buffer, + pu4Byte pLength, + CHANNEL_WIDTH BW + ) +{ + u2Byte Duration= 0; + u1Byte Sequence = 0; + pu1Byte pNDPAFrame = Buffer; + RT_NDPA_STA_INFO STAInfo; + PADAPTER Adapter = pDM_Odm->Adapter; + u1Byte Idx = 0; + PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); + // Frame control. + SET_80211_HDR_FRAME_CONTROL(pNDPAFrame, 0); + SET_80211_HDR_TYPE_AND_SUBTYPE(pNDPAFrame, Type_NDPA); + + SET_80211_HDR_ADDRESS1(pNDPAFrame, RA); + SET_80211_HDR_ADDRESS2(pNDPAFrame, pBeamformEntry->MyMacAddr); + + Duration = 2*aSifsTime + 44; + + if (BW == CHANNEL_WIDTH_80) + Duration += 40; + else if(BW == CHANNEL_WIDTH_40) + Duration+= 87; + else + Duration+= 180; + + SET_80211_HDR_DURATION(pNDPAFrame, Duration); + + Sequence = *(pDM_Odm->pSoundingSeq) << 2; + ODM_MoveMemory(pDM_Odm, pNDPAFrame+16, &Sequence, 1); + + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS) || phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_AP) == FALSE) + AID = 0; + + STAInfo.AID = AID; + STAInfo.FeedbackType = 0; + STAInfo.NcIndex = 0; + + ODM_MoveMemory(pDM_Odm, pNDPAFrame+17, (pu1Byte)&STAInfo, 2); + + *pLength = 19; +} + + +BOOLEAN +SendFWVHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN u2Byte AID, + IN CHANNEL_WIDTH BW + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PRT_TCB pTcb; + PRT_TX_LOCAL_BUFFER pBuf; + BOOLEAN ret = TRUE; + u4Byte BufLen; + pu1Byte BufAddr; + u1Byte DescLen = 0, Idx = 0, NDPTxRate = 0; + PADAPTER pDefAdapter = GetDefaultAdapter(Adapter); + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PRT_BEAMFORMEE_ENTRY pBeamformEntry =phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (pBeamformEntry == NULL) + return FALSE; + + NDPTxRate = Beamforming_GetVHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); + + PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); + + if (MgntGetFWBuffer(pDefAdapter, &pTcb, &pBuf)) { +#if(DEV_BUS_TYPE != RT_PCI_INTERFACE) + DescLen = Adapter->HWDescHeadLength - pHalData->USBALLDummyLength; +#endif + BufAddr = pBuf->Buffer.VirtualAddress + DescLen; + + ConstructVHTNDPAPacket( + pDM_Odm, + RA, + AID, + BufAddr, + &BufLen, + BW + ); + + pTcb->PacketLength = BufLen + DescLen; + + pTcb->bTxEnableSwCalcDur = TRUE; + + pTcb->BWOfPacket = BW; + + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS) || phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_AP)) + pTcb->G_ID = 63; + + pTcb->P_AID = pBeamformEntry->P_AID; + pTcb->DataRate = NDPTxRate; /*decide by Nr*/ + + Adapter->HalFunc.CmdSendPacketHandler(Adapter, pTcb, pBuf, pTcb->PacketLength, DESC_PACKET_TYPE_NORMAL, FALSE); + } else + ret = FALSE; + + PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] End, ret=%d\n", __func__, ret)); + + if (ret) + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); + + return ret; +} + + + +BOOLEAN +SendSWVHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN u2Byte AID, + IN CHANNEL_WIDTH BW + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + PRT_TCB pTcb; + PRT_TX_LOCAL_BUFFER pBuf; + BOOLEAN ret = TRUE; + u1Byte Idx = 0, NDPTxRate = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); + + NDPTxRate = Beamforming_GetVHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); + + PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); + + if (MgntGetBuffer(Adapter, &pTcb, &pBuf)) { + ConstructVHTNDPAPacket( + pDM_Odm, + RA, + AID, + pBuf->Buffer.VirtualAddress, + &pTcb->PacketLength, + BW + ); + + pTcb->bTxEnableSwCalcDur = TRUE; + pTcb->BWOfPacket = BW; + + /*rate of NDP decide by Nr*/ + MgntSendPacket(Adapter, pTcb, pBuf, pTcb->PacketLength, NORMAL_QUEUE, NDPTxRate); + } else + ret = FALSE; + + PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); + + if (ret) + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); + + return ret; +} + +#ifdef SUPPORT_MU_BF +#if (SUPPORT_MU_BF == 1) +/* +// Description: On VHT GID management frame by an MU beamformee. +// +// 2015.05.20. Created by tynli. +*/ +RT_STATUS +Beamforming_GetVHTGIDMgntFrame( + IN PADAPTER Adapter, + IN PRT_RFD pRfd, + IN POCTET_STRING pPduOS + ) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; + RT_STATUS rtStatus = RT_STATUS_SUCCESS; + pu1Byte pBuffer = NULL; + pu1Byte pRaddr = NULL; + u1Byte MemStatus[8] = {0}, UserPos[16] = {0}; + u1Byte idx; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PRT_BEAMFORMER_ENTRY pBeamformEntry = &pBeamInfo->BeamformerEntry[pBeamInfo->mu_ap_index]; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] On VHT GID mgnt frame!\n", __func__)); + + /* Check length*/ + if (pPduOS->Length < (FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY+16)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Beamforming_GetVHTGIDMgntFrame(): Invalid length (%d)\n", pPduOS->Length)); + return RT_STATUS_INVALID_LENGTH; + } + + /* Check RA*/ + pRaddr = (pu1Byte)(pPduOS->Octet)+4; + if (!eqMacAddr(pRaddr, Adapter->CurrentAddress)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Beamforming_GetVHTGIDMgntFrame(): Drop because of RA error.\n")); + return RT_STATUS_PKT_DROP; + } + + RT_DISP_DATA(FBEAM, FBEAM_DATA, "On VHT GID Mgnt Frame ==>:\n", pPduOS->Octet, pPduOS->Length); + + /*Parsing Membership Status Array*/ + pBuffer = pPduOS->Octet + FRAME_OFFSET_VHT_GID_MGNT_MEMBERSHIP_STATUS_ARRAY; + for (idx = 0; idx < 8; idx++) { + MemStatus[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(pBuffer+idx); + pBeamformEntry->gid_valid[idx] = GET_VHT_GID_MGNT_INFO_MEMBERSHIP_STATUS(pBuffer+idx); + } + + RT_DISP_DATA(FBEAM, FBEAM_DATA, "MemStatus: ", MemStatus, 8); + + /* Parsing User Position Array*/ + pBuffer = pPduOS->Octet + FRAME_OFFSET_VHT_GID_MGNT_USER_POSITION_ARRAY; + for (idx = 0; idx < 16; idx++) { + UserPos[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(pBuffer+idx); + pBeamformEntry->user_position[idx] = GET_VHT_GID_MGNT_INFO_USER_POSITION(pBuffer+idx); + } + + RT_DISP_DATA(FBEAM, FBEAM_DATA, "UserPos: ", UserPos, 16); + + /* Group ID detail printed*/ + { + u1Byte i, j; + u1Byte tmpVal; + u2Byte tmpVal2; + + for (i = 0; i < 8; i++) { + tmpVal = MemStatus[i]; + tmpVal2 = ((UserPos[i*2 + 1] << 8) & 0xFF00) + (UserPos[i * 2] & 0xFF); + for (j = 0; j < 8; j++) { + if ((tmpVal >> j) & BIT0) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("Use Group ID (%d), User Position (%d)\n", + (i*8+j), (tmpVal2 >> 2 * j)&0x3)); + } + } + } + } + + /* Indicate GID frame to IHV service. */ + { + u1Byte Indibuffer[24] = {0}; + u1Byte Indioffset = 0; + + PlatformMoveMemory(Indibuffer + Indioffset, pBeamformEntry->gid_valid, 8); + Indioffset += 8; + PlatformMoveMemory(Indibuffer + Indioffset, pBeamformEntry->user_position, 16); + Indioffset += 16; + + PlatformIndicateCustomStatus( + Adapter, + RT_CUSTOM_EVENT_VHT_RECV_GID_MGNT_FRAME, + RT_CUSTOM_INDI_TARGET_IHV, + Indibuffer, + Indioffset); + } + + /* Config HW GID table */ + halComTxbf_ConfigGtab(pDM_Odm); + + return rtStatus; +} + +/* +// Description: Construct VHT Group ID (GID) management frame. +// +// 2015.05.20. Created by tynli. +*/ +VOID +ConstructVHTGIDMgntFrame( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte RA, + IN PRT_BEAMFORMEE_ENTRY pBeamformEntry, + OUT pu1Byte Buffer, + OUT pu4Byte pLength + +) +{ + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PADAPTER Adapter = pBeamInfo->SourceAdapter; + OCTET_STRING osFTMFrame, tmp; + + FillOctetString(osFTMFrame, Buffer, 0); + *pLength = 0; + + ConstructMaFrameHdr( + Adapter, + RA, + ACT_CAT_VHT, + ACT_VHT_GROUPID_MANAGEMENT, + &osFTMFrame); + + /* Membership Status Array*/ + FillOctetString(tmp, pBeamformEntry->gid_valid, 8); + PacketAppendData(&osFTMFrame, tmp); + + /* User Position Array*/ + FillOctetString(tmp, pBeamformEntry->user_position, 16); + PacketAppendData(&osFTMFrame, tmp); + + *pLength = osFTMFrame.Length; + + RT_DISP_DATA(FBEAM, FBEAM_DATA, "ConstructVHTGIDMgntFrame():\n", Buffer, *pLength); +} + +BOOLEAN +SendSWVHTGIDMgntFrame( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN u1Byte Idx + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_TCB pTcb; + PRT_TX_LOCAL_BUFFER pBuf; + BOOLEAN ret = TRUE; + u1Byte DataRate = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PRT_BEAMFORMEE_ENTRY pBeamformEntry = &pBeamInfo->BeamformeeEntry[Idx]; + PADAPTER Adapter = pBeamInfo->SourceAdapter; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); + + if (MgntGetBuffer(Adapter, &pTcb, &pBuf)) { + ConstructVHTGIDMgntFrame( + pDM_Odm, + RA, + pBeamformEntry, + pBuf->Buffer.VirtualAddress, + &pTcb->PacketLength + ); + + pTcb->BWOfPacket = CHANNEL_WIDTH_20; + DataRate = MGN_6M; + MgntSendPacket(Adapter, pTcb, pBuf, pTcb->PacketLength, NORMAL_QUEUE, DataRate); + } else + ret = FALSE; + + PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); + + if (ret) + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); + + return ret; +} + + +/* +// Description: Construct VHT beamforming report poll. +// +// 2015.05.20. Created by tynli. +*/ +VOID +ConstructVHTBFReportPoll( + IN PDM_ODM_T pDM_Odm, + IN pu1Byte RA, + OUT pu1Byte Buffer, + OUT pu4Byte pLength +) +{ + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PADAPTER Adapter = pBeamInfo->SourceAdapter; + pu1Byte pBFRptPoll = Buffer; + + /* Frame control*/ + SET_80211_HDR_FRAME_CONTROL(pBFRptPoll, 0); + SET_80211_HDR_TYPE_AND_SUBTYPE(pBFRptPoll, Type_Beamforming_Report_Poll); + + /* Duration*/ + SET_80211_HDR_DURATION(pBFRptPoll, 100); + + /* RA*/ + SET_VHT_BF_REPORT_POLL_RA(pBFRptPoll, RA); + + /* TA*/ + SET_VHT_BF_REPORT_POLL_TA(pBFRptPoll, Adapter->CurrentAddress); + + /* Feedback Segment Retransmission Bitmap*/ + SET_VHT_BF_REPORT_POLL_FEEDBACK_SEG_RETRAN_BITMAP(pBFRptPoll, 0xFF); + + *pLength = 17; + + RT_DISP_DATA(FBEAM, FBEAM_DATA, "ConstructVHTBFReportPoll():\n", Buffer, *pLength); + +} + +BOOLEAN +SendSWVHTBFReportPoll( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN BOOLEAN bFinalPoll + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_TCB pTcb; + PRT_TX_LOCAL_BUFFER pBuf; + BOOLEAN ret = TRUE; + u1Byte Idx = 0, DataRate = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); + PADAPTER Adapter = pBeamInfo->SourceAdapter; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); + + if (MgntGetBuffer(Adapter, &pTcb, &pBuf)) { + ConstructVHTBFReportPoll( + pDM_Odm, + RA, + pBuf->Buffer.VirtualAddress, + &pTcb->PacketLength + ); + + pTcb->bTxEnableSwCalcDur = TRUE; /* need?*/ + pTcb->BWOfPacket = CHANNEL_WIDTH_20; + + if (bFinalPoll) + pTcb->TxBFPktType = RT_BF_PKT_TYPE_FINAL_BF_REPORT_POLL; + else + pTcb->TxBFPktType = RT_BF_PKT_TYPE_BF_REPORT_POLL; + + DataRate = MGN_6M; /* Legacy OFDM rate*/ + MgntSendPacket(Adapter, pTcb, pBuf, pTcb->PacketLength, NORMAL_QUEUE, DataRate); + } else + ret = FALSE; + + PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); + + if (ret) + RT_DISP_DATA(FBEAM, FBEAM_DATA, "SendSWVHTBFReportPoll():\n", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); + + return ret; + +} + + +/* +// Description: Construct VHT MU NDPA packet. +// We should combine this function with ConstructVHTNDPAPacket() in the future. +// +// 2015.05.21. Created by tynli. +*/ +VOID +ConstructVHTMUNDPAPacket( + IN PDM_ODM_T pDM_Odm, + IN CHANNEL_WIDTH BW, + OUT pu1Byte Buffer, + OUT pu4Byte pLength + ) +{ + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PADAPTER Adapter = pBeamInfo->SourceAdapter; + u2Byte Duration = 0; + u1Byte Sequence = 0; + pu1Byte pNDPAFrame = Buffer; + RT_NDPA_STA_INFO STAInfo; + u1Byte idx; + u1Byte DestAddr[6] = {0}; + PRT_BEAMFORMEE_ENTRY pEntry = NULL; + + /* Fill the first MU BFee entry (STA1) MAC addr to destination address then + HW will change A1 to broadcast addr. 2015.05.28. Suggested by SD1 Chunchu. */ + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + pEntry = &(pBeamInfo->BeamformeeEntry[idx]); + if (pEntry->is_mu_sta) { + cpMacAddr(DestAddr, pEntry->MacAddr); + break; + } + } + if (pEntry == NULL) + return; + + /* Frame control.*/ + SET_80211_HDR_FRAME_CONTROL(pNDPAFrame, 0); + SET_80211_HDR_TYPE_AND_SUBTYPE(pNDPAFrame, Type_NDPA); + + SET_80211_HDR_ADDRESS1(pNDPAFrame, DestAddr); + SET_80211_HDR_ADDRESS2(pNDPAFrame, pEntry->MyMacAddr); + + /*--------------------------------------------*/ + /* Need to modify "Duration" to MU consideration. */ + Duration = 2*aSifsTime + 44; + + if (BW == CHANNEL_WIDTH_80) + Duration += 40; + else if(BW == CHANNEL_WIDTH_40) + Duration+= 87; + else + Duration+= 180; + /*--------------------------------------------*/ + + SET_80211_HDR_DURATION(pNDPAFrame, Duration); + + Sequence = *(pDM_Odm->pSoundingSeq) << 2; + ODM_MoveMemory(pDM_Odm, pNDPAFrame + 16, &Sequence, 1); + + *pLength = 17; + + /* Construct STA info. for multiple STAs*/ + for (idx = 0; idx < BEAMFORMEE_ENTRY_NUM; idx++) { + pEntry = &(pBeamInfo->BeamformeeEntry[idx]); + if (pEntry->is_mu_sta) { + STAInfo.AID = pEntry->AID; + STAInfo.FeedbackType = 1; /* 1'b1: MU*/ + STAInfo.NcIndex = 0; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Get BeamformeeEntry idx(%d), AID =%d\n", __func__, idx, pEntry->AID)); + + ODM_MoveMemory(pDM_Odm, pNDPAFrame+(*pLength), (pu1Byte)&STAInfo, 2); + *pLength += 2; + } + } + +} + +BOOLEAN +SendSWVHTMUNDPAPacket( + IN PVOID pDM_VOID, + IN CHANNEL_WIDTH BW + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_TCB pTcb; + PRT_TX_LOCAL_BUFFER pBuf; + BOOLEAN ret = TRUE; + u1Byte NDPTxRate = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PADAPTER Adapter = pBeamInfo->SourceAdapter; + + NDPTxRate = MGN_VHT2SS_MCS0; + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); + + PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); + + if (MgntGetBuffer(Adapter, &pTcb, &pBuf)) { + ConstructVHTMUNDPAPacket( + pDM_Odm, + BW, + pBuf->Buffer.VirtualAddress, + &pTcb->PacketLength + ); + + pTcb->bTxEnableSwCalcDur = TRUE; + pTcb->BWOfPacket = BW; + pTcb->TxBFPktType = RT_BF_PKT_TYPE_BROADCAST_NDPA; + + /*rate of NDP decide by Nr*/ + MgntSendPacket(Adapter, pTcb, pBuf, pTcb->PacketLength, NORMAL_QUEUE, NDPTxRate); + } else + ret = FALSE; + + PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); + + if (ret) + RT_DISP_DATA(FBEAM, FBEAM_DATA, "", pBuf->Buffer.VirtualAddress, pTcb->PacketLength); + + return ret; +} + +#endif /*#if (SUPPORT_MU_BF == 1)*/ +#endif /*#ifdef SUPPORT_MU_BF*/ + + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + +u4Byte +Beamforming_GetReportFrame( + IN PVOID pDM_VOID, + union recv_frame *precv_frame + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u4Byte ret = _SUCCESS; + PRT_BEAMFORMEE_ENTRY pBeamformEntry = NULL; + pu1Byte pframe = precv_frame->u.hdr.rx_data; + u4Byte frame_len = precv_frame->u.hdr.len; + pu1Byte TA; + u1Byte Idx, offset; + + /*DBG_871X("beamforming_get_report_frame\n");*/ + + /*Memory comparison to see if CSI report is the same with previous one*/ + TA = GetAddr2Ptr(pframe); + pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, TA, &Idx); + if(pBeamformEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU) + offset = 31; /*24+(1+1+3)+2 MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)*/ + else if(pBeamformEntry->BeamformEntryCap & BEAMFORMER_CAP_HT_EXPLICIT) + offset = 34; /*24+(1+1+6)+2 MAC header+(Category+ActionCode+MIMOControlField)+SNR(Nc=2)*/ + else + return ret; + + /*DBG_871X("%s MacId %d offset=%d\n", __FUNCTION__, pBeamformEntry->mac_id, offset);*/ + + return ret; +} + + +BOOLEAN +SendFWHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN CHANNEL_WIDTH BW + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct rtw_ieee80211_hdr *pwlanhdr; + struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u1Byte ActionHdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c}; + u1Byte *pframe; + u2Byte *fctrl; + u2Byte duration = 0; + u1Byte aSifsTime = 0, NDPTxRate = 0, Idx = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + + if (pmgntframe == NULL) { + DBG_871X("%s, alloc mgnt frame fail\n", __func__); + return _FALSE; + } + + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(Adapter, pattrib); + + pattrib->qsel = QSLT_BEACON; + NDPTxRate = Beamforming_GetHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); + pattrib->rate = NDPTxRate; + pattrib->bwmode = BW; + pattrib->order = 1; + pattrib->subtype = WIFI_ACTION_NOACK; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + + pwlanhdr = (struct rtw_ieee80211_hdr*)pframe; + + fctrl = &pwlanhdr->frame_ctl; + *(fctrl) = 0; + + SetOrderBit(pframe); + SetFrameSubType(pframe, WIFI_ACTION_NOACK); + + _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pBeamformEntry->MyMacAddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + if( pmlmeext->cur_wireless_mode == WIRELESS_11B) + aSifsTime = 10; + else + aSifsTime = 16; + + duration = 2*aSifsTime + 40; + + if(BW == CHANNEL_WIDTH_40) + duration+= 87; + else + duration+= 180; + + SetDuration(pframe, duration); + + //HT control field + SET_HT_CTRL_CSI_STEERING(pframe+24, 3); + SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe+24, 1); + + _rtw_memcpy(pframe+28, ActionHdr, 4); + + pattrib->pktlen = 32; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(Adapter, pmgntframe); + + return _TRUE; +} + + +BOOLEAN +SendSWHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN CHANNEL_WIDTH BW + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct rtw_ieee80211_hdr *pwlanhdr; + struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u1Byte ActionHdr[4] = {ACT_CAT_VENDOR, 0x00, 0xe0, 0x4c}; + pu1Byte pframe; + pu2Byte fctrl; + u2Byte duration = 0; + u1Byte aSifsTime = 0, NDPTxRate = 0, Idx = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); + + NDPTxRate = Beamforming_GetHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + + if (pmgntframe == NULL) { + DBG_871X("%s, alloc mgnt frame fail\n", __func__); + return _FALSE; + } + + /*update attribute*/ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(Adapter, pattrib); + pattrib->qsel = QSLT_MGNT; + pattrib->rate = NDPTxRate; + pattrib->bwmode = BW; + pattrib->order = 1; + pattrib->subtype = WIFI_ACTION_NOACK; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &pwlanhdr->frame_ctl; + *(fctrl) = 0; + + SetOrderBit(pframe); + SetFrameSubType(pframe, WIFI_ACTION_NOACK); + + _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pBeamformEntry->MyMacAddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + if (pmlmeext->cur_wireless_mode == WIRELESS_11B) + aSifsTime = 10; + else + aSifsTime = 16; + + duration = 2*aSifsTime + 40; + + if (BW == CHANNEL_WIDTH_40) + duration += 87; + else + duration += 180; + + SetDuration(pframe, duration); + + /*HT control field*/ + SET_HT_CTRL_CSI_STEERING(pframe+24, 3); + SET_HT_CTRL_NDP_ANNOUNCEMENT(pframe+24, 1); + + _rtw_memcpy(pframe+28, ActionHdr, 4); + + pattrib->pktlen = 32; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(Adapter, pmgntframe); + + return _TRUE; +} + + +BOOLEAN +SendFWVHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN u2Byte AID, + IN CHANNEL_WIDTH BW + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct rtw_ieee80211_hdr *pwlanhdr; + struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + pu1Byte pframe; + pu2Byte fctrl; + u2Byte duration = 0; + u1Byte sequence = 0, aSifsTime = 0, NDPTxRate= 0, Idx = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); + RT_NDPA_STA_INFO sta_info; + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + + if (pmgntframe == NULL) { + DBG_871X("%s, alloc mgnt frame fail\n", __func__); + return _FALSE; + } + + //update attribute + pattrib = &pmgntframe->attrib; + _rtw_memcpy(pattrib->ra, RA, ETH_ALEN); + update_mgntframe_attrib(Adapter, pattrib); + + pattrib->qsel = QSLT_BEACON; + NDPTxRate = Beamforming_GetVHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); + pattrib->rate = NDPTxRate; + pattrib->bwmode = BW; + pattrib->subtype = WIFI_NDPA; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + + pwlanhdr = (struct rtw_ieee80211_hdr*)pframe; + + fctrl = &pwlanhdr->frame_ctl; + *(fctrl) = 0; + + SetFrameSubType(pframe, WIFI_NDPA); + + _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pBeamformEntry->MyMacAddr, ETH_ALEN); + + if (IsSupported5G(pmlmeext->cur_wireless_mode) || IsSupportedHT(pmlmeext->cur_wireless_mode)) + aSifsTime = 16; + else + aSifsTime = 10; + + duration = 2*aSifsTime + 44; + + if(BW == CHANNEL_WIDTH_80) + duration += 40; + else if(BW == CHANNEL_WIDTH_40) + duration+= 87; + else + duration+= 180; + + SetDuration(pframe, duration); + + sequence = pBeamInfo->SoundingSequence<< 2; + if (pBeamInfo->SoundingSequence >= 0x3f) + pBeamInfo->SoundingSequence = 0; + else + pBeamInfo->SoundingSequence++; + + _rtw_memcpy(pframe+16, &sequence,1); + + if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)) + AID = 0; + + sta_info.AID = AID; + sta_info.FeedbackType = 0; + sta_info.NcIndex= 0; + + _rtw_memcpy(pframe+17, (u8 *)&sta_info, 2); + + pattrib->pktlen = 19; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(Adapter, pmgntframe); + + return _TRUE; +} + + + +BOOLEAN +SendSWVHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN u2Byte AID, + IN CHANNEL_WIDTH BW + ) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + struct rtw_ieee80211_hdr *pwlanhdr; + struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + RT_NDPA_STA_INFO ndpa_sta_info; + u1Byte NDPTxRate = 0, sequence = 0, aSifsTime = 0, Idx = 0; + pu1Byte pframe; + pu2Byte fctrl; + u2Byte duration = 0; + PRT_BEAMFORMING_INFO pBeamInfo = &(pDM_Odm->BeamformingInfo); + PRT_BEAMFORMEE_ENTRY pBeamformEntry = phydm_Beamforming_GetBFeeEntryByAddr(pDM_Odm, RA, &Idx); + + NDPTxRate = Beamforming_GetVHTNDPTxRate(pDM_Odm, pBeamformEntry->CompSteeringNumofBFer); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] NDPTxRate =%d\n", __func__, NDPTxRate)); + + pmgntframe = alloc_mgtxmitframe(pxmitpriv); + + if (pmgntframe == NULL) { + DBG_871X("%s, alloc mgnt frame fail\n", __func__); + return _FALSE; + } + + /*update attribute*/ + pattrib = &pmgntframe->attrib; + _rtw_memcpy(pattrib->ra, RA, ETH_ALEN); + update_mgntframe_attrib(Adapter, pattrib); + pattrib->qsel = QSLT_MGNT; + pattrib->rate = NDPTxRate; + pattrib->bwmode = BW; + pattrib->subtype = WIFI_NDPA; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &pwlanhdr->frame_ctl; + *(fctrl) = 0; + + SetFrameSubType(pframe, WIFI_NDPA); + + _rtw_memcpy(pwlanhdr->addr1, RA, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, pBeamformEntry->MyMacAddr, ETH_ALEN); + + if (IsSupported5G(pmlmeext->cur_wireless_mode) || IsSupportedHT(pmlmeext->cur_wireless_mode)) + aSifsTime = 16; + else + aSifsTime = 10; + + duration = 2*aSifsTime + 44; + + if (BW == CHANNEL_WIDTH_80) + duration += 40; + else if (BW == CHANNEL_WIDTH_40) + duration += 87; + else + duration += 180; + + SetDuration(pframe, duration); + + sequence = pBeamInfo->SoundingSequence << 2; + if (pBeamInfo->SoundingSequence >= 0x3f) + pBeamInfo->SoundingSequence = 0; + else + pBeamInfo->SoundingSequence++; + + _rtw_memcpy(pframe+16, &sequence, 1); + if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)) + AID = 0; + + ndpa_sta_info.AID = AID; + ndpa_sta_info.FeedbackType = 0; + ndpa_sta_info.NcIndex = 0; + + _rtw_memcpy(pframe+17, (u8 *)&ndpa_sta_info, 2); + + pattrib->pktlen = 19; + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(Adapter, pmgntframe); + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] [%d]\n", __func__, __LINE__)); + + return _TRUE; +} + + +#endif + + +VOID +Beamforming_GetNDPAFrame( + IN PVOID pDM_VOID, +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN OCTET_STRING pduOS +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + union recv_frame *precv_frame +#endif +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PADAPTER Adapter = pDM_Odm->Adapter; + pu1Byte TA ; + u1Byte Idx, Sequence; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + pu1Byte pNDPAFrame = pduOS.Octet; +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + pu1Byte pNDPAFrame = precv_frame->u.hdr.rx_data; +#endif + PRT_BEAMFORMER_ENTRY pBeamformerEntry = NULL; /*Modified By Jeffery @2014-10-29*/ + + +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + RT_DISP_DATA(FBEAM, FBEAM_DATA, "Beamforming_GetNDPAFrame\n", pduOS.Octet, pduOS.Length); + if (IsCtrlNDPA(pNDPAFrame) == FALSE) +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + if (GetFrameSubType(pNDPAFrame) != WIFI_NDPA) +#endif + return; + else if (!(pDM_Odm->SupportICType & (ODM_RTL8812 | ODM_RTL8821))) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] not 8812 or 8821A, return\n", __func__)); + return; + } +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + TA = Frame_Addr2(pduOS); +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + TA = GetAddr2Ptr(pNDPAFrame); +#endif + /*Remove signaling TA. */ + TA[0] = TA[0] & 0xFE; + + pBeamformerEntry = phydm_Beamforming_GetBFerEntryByAddr(pDM_Odm, TA, &Idx); // Modified By Jeffery @2014-10-29 + + /*Break options for Clock Reset*/ + if (pBeamformerEntry == NULL) + return; + else if (!(pBeamformerEntry->BeamformEntryCap & BEAMFORMEE_CAP_VHT_SU)) + return; + /*LogSuccess: As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is NO LONGER needed !2015-04-10, Jeffery*/ + /*ClockResetTimes: While BFer entry always doesn't receive our CSI, clock will reset again and again.So ClockResetTimes is limited to 5 times.2015-04-13, Jeffery*/ + else if ((pBeamformerEntry->LogSuccess == 1) || (pBeamformerEntry->ClockResetTimes == 5)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] LogSeq=%d, PreLogSeq=%d, LogRetryCnt=%d, LogSuccess=%d, ClockResetTimes=%d, clock reset is no longer needed.\n", + __func__, pBeamformerEntry->LogSeq, pBeamformerEntry->PreLogSeq, pBeamformerEntry->LogRetryCnt, pBeamformerEntry->LogSuccess, pBeamformerEntry->ClockResetTimes)); + + return; + } + + Sequence = (pNDPAFrame[16]) >> 2; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start, Sequence=%d, LogSeq=%d, PreLogSeq=%d, LogRetryCnt=%d, ClockResetTimes=%d, LogSuccess=%d\n", + __func__, Sequence, pBeamformerEntry->LogSeq, pBeamformerEntry->PreLogSeq, pBeamformerEntry->LogRetryCnt, pBeamformerEntry->ClockResetTimes, pBeamformerEntry->LogSuccess)); + + if ((pBeamformerEntry->LogSeq != 0) && (pBeamformerEntry->PreLogSeq != 0)) { + /*Success condition*/ + if ((pBeamformerEntry->LogSeq != Sequence) && (pBeamformerEntry->PreLogSeq != pBeamformerEntry->LogSeq)) { + /* break option for clcok reset, 2015-03-30, Jeffery */ + pBeamformerEntry->LogRetryCnt = 0; + /*As long as 8812A receive NDPA and feedback CSI succeed once, clock reset is no longer needed.*/ + /*That is, LogSuccess is NOT needed to be reset to zero, 2015-04-13, Jeffery*/ + pBeamformerEntry->LogSuccess = 1; + + } else {/*Fail condition*/ + + if (pBeamformerEntry->LogRetryCnt == 5) { + pBeamformerEntry->ClockResetTimes++; + pBeamformerEntry->LogRetryCnt = 0; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Clock Reset!!! ClockResetTimes=%d\n", + __func__, pBeamformerEntry->ClockResetTimes)); + HalComTxbf_Set(pDM_Odm, TXBF_SET_SOUNDING_CLK, NULL); + + } else + pBeamformerEntry->LogRetryCnt++; + } + } + + /*Update LogSeq & PreLogSeq*/ + pBeamformerEntry->PreLogSeq = pBeamformerEntry->LogSeq; + pBeamformerEntry->LogSeq = Sequence; + +} + + + +#endif diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbfinterface.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbfinterface.h new file mode 100644 index 000000000..16a62f92c --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbfinterface.h @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __HAL_TXBF_INTERFACE_H__ +#define __HAL_TXBF_INTERFACE_H__ + +#if (BEAMFORMING_SUPPORT == 1) +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) +VOID +Beamforming_GidPAid( + PADAPTER Adapter, + PRT_TCB pTcb + ); + +RT_STATUS +Beamforming_GetReportFrame( + IN PADAPTER Adapter, + IN PRT_RFD pRfd, + IN POCTET_STRING pPduOS + ); + +VOID +Beamforming_GetNDPAFrame( + IN PVOID pDM_VOID, + IN OCTET_STRING pduOS + ); + +BOOLEAN +SendFWHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN CHANNEL_WIDTH BW + ); + +BOOLEAN +SendFWVHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN u2Byte AID, + IN CHANNEL_WIDTH BW + ); + +BOOLEAN +SendSWVHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN u2Byte AID, + IN CHANNEL_WIDTH BW + ); + +BOOLEAN +SendSWHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN CHANNEL_WIDTH BW + ); + +#ifdef SUPPORT_MU_BF +#if (SUPPORT_MU_BF == 1) +RT_STATUS +Beamforming_GetVHTGIDMgntFrame( + IN PADAPTER Adapter, + IN PRT_RFD pRfd, + IN POCTET_STRING pPduOS + ); + +BOOLEAN +SendSWVHTGIDMgntFrame( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN u1Byte Idx + ); + +BOOLEAN +SendSWVHTBFReportPoll( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN BOOLEAN bFinalPoll + ); + +BOOLEAN +SendSWVHTMUNDPAPacket( + IN PVOID pDM_VOID, + IN CHANNEL_WIDTH BW + ); +#else +#define Beamforming_GetVHTGIDMgntFrame(Adapter, pRfd, pPduOS) RT_STATUS_FAILURE +#define SendSWVHTGIDMgntFrame(pDM_VOID, RA) +#define SendSWVHTBFReportPoll(pDM_VOID, RA, bFinalPoll) +#define SendSWVHTMUNDPAPacket(pDM_VOID, BW) +#endif +#endif + + +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + +u4Byte +Beamforming_GetReportFrame( + IN PVOID pDM_VOID, + union recv_frame *precv_frame + ); + +BOOLEAN +SendFWHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN CHANNEL_WIDTH BW + ); + +BOOLEAN +SendSWHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN CHANNEL_WIDTH BW + ); + +BOOLEAN +SendFWVHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN u2Byte AID, + IN CHANNEL_WIDTH BW + ); + +BOOLEAN +SendSWVHTNDPAPacket( + IN PVOID pDM_VOID, + IN pu1Byte RA, + IN u2Byte AID, + IN CHANNEL_WIDTH BW + ); +#endif + +VOID +Beamforming_GetNDPAFrame( + IN PVOID pDM_VOID, +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + IN OCTET_STRING pduOS +#elif (DM_ODM_SUPPORT_TYPE == ODM_CE) + union recv_frame *precv_frame +#endif +); + +#else +#define Beamforming_GetNDPAFrame(pDM_Odm, _PduOS) +#if (DM_ODM_SUPPORT_TYPE == ODM_CE) +#define Beamforming_GetReportFrame(Adapter, precv_frame) RT_STATUS_FAILURE +#elif (DM_ODM_SUPPORT_TYPE == ODM_WIN) +#define Beamforming_GetReportFrame(Adapter, pRfd, pPduOS) RT_STATUS_FAILURE +#define Beamforming_GetVHTGIDMgntFrame(Adapter, pRfd, pPduOS) RT_STATUS_FAILURE +#endif +#define SendFWHTNDPAPacket(pDM_VOID, RA, BW) +#define SendSWHTNDPAPacket(pDM_VOID, RA, BW) +#define SendFWVHTNDPAPacket(pDM_VOID, RA, AID, BW) +#define SendSWVHTNDPAPacket(pDM_VOID, RA, AID, BW) +#define SendSWVHTGIDMgntFrame(pDM_VOID, RA, idx) +#define SendSWVHTBFReportPoll(pDM_VOID, RA, bFinalPoll) +#define SendSWVHTMUNDPAPacket(pDM_VOID, BW) +#endif + +#endif diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbfjaguar.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbfjaguar.c new file mode 100644 index 000000000..69cc49419 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbfjaguar.c @@ -0,0 +1,528 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +//============================================================ +// Description: +// +// This file is for 8812/8821/8811 TXBF mechanism +// +//============================================================ +#include "mp_precomp.h" +#include "../phydm_precomp.h" + +#if (BEAMFORMING_SUPPORT == 1) +#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) +VOID +HalTxbf8812A_setNDPArate( + IN PVOID pDM_VOID, + IN u1Byte BW, + IN u1Byte Rate +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + ODM_Write1Byte(pDM_Odm, REG_NDPA_OPT_CTRL_8812A, (Rate << 2 | BW)); + +} + +VOID +halTxbfJaguar_RfMode( + IN PVOID pDM_VOID, + IN PRT_BEAMFORMING_INFO pBeamInfo +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + + if (pDM_Odm->RFType == ODM_1T1R) + return; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] set TxIQGen\n", __func__)); + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WeLut_Jaguar, 0x80000, 0x1); /*RF Mode table write enable*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WeLut_Jaguar, 0x80000, 0x1); /*RF Mode table write enable*/ + + if (pBeamInfo->beamformee_su_cnt > 0) { + // Paath_A + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/ + // Path_B + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0xE26BF); /*Enable TXIQGEN in RX mode*/ + } else { + // Paath_A + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_ModeTableData1, 0xfffff, 0xC26BF); /*Disable TXIQGEN in RX mode*/ + // Path_B + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableAddr, 0x78000, 0x3); /*Select RX mode*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData0, 0xfffff, 0x3F7FF); /*Set Table data*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_ModeTableData1, 0xfffff, 0xC26BF); /*Disable TXIQGEN in RX mode*/ + } + + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WeLut_Jaguar, 0x80000, 0x0); /*RF Mode table write disable*/ + ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_WeLut_Jaguar, 0x80000, 0x0); /*RF Mode table write disable*/ + + if (pBeamInfo->beamformee_su_cnt > 0) + ODM_SetBBReg(pDM_Odm, rTxPath_Jaguar, bMaskByte1, 0x33); + else + ODM_SetBBReg(pDM_Odm, rTxPath_Jaguar, bMaskByte1, 0x11); +} + + +VOID +halTxbfJaguar_DownloadNDPA( + IN PVOID pDM_VOID, + IN u1Byte Idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte u1bTmp = 0, tmpReg422 = 0, Head_Page; + u1Byte BcnValidReg = 0, count = 0, DLBcnCount = 0; + BOOLEAN bSendBeacon = FALSE; + u1Byte TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8812; /*default reseved 1 page for the IC type which is undefined.*/ + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx; + PADAPTER Adapter = pDM_Odm->Adapter; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + *pDM_Odm->pbFwDwRsvdPageInProgress = TRUE; +#endif + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (Idx == 0) + Head_Page = 0xFE; + else + Head_Page = 0xFE; + + Adapter->HalFunc.GetHalDefVarHandler(Adapter, HAL_DEF_TX_PAGE_BOUNDARY, (pu1Byte)&TxPageBndy); + + /*Set REG_CR bit 8. DMA beacon by SW.*/ + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8812A + 1); + ODM_Write1Byte(pDM_Odm, REG_CR_8812A + 1, (u1bTmp | BIT0)); + + + /*Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.*/ + tmpReg422 = ODM_Read1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8812A + 2); + ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8812A + 2, tmpReg422 & (~BIT6)); + + if (tmpReg422 & BIT6) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("SetBeamformDownloadNDPA_8812(): There is an Adapter is sending beacon.\n")); + bSendBeacon = TRUE; + } + + /*TDECTRL[15:8] 0x209[7:0] = 0xF6 Beacon Head for TXDMA*/ + ODM_Write1Byte(pDM_Odm, REG_TDECTRL_8812A + 1, Head_Page); + + do { + /*Clear beacon valid check bit.*/ + BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_TDECTRL_8812A + 2); + ODM_Write1Byte(pDM_Odm, REG_TDECTRL_8812A + 2, (BcnValidReg | BIT0)); + + /*download NDPA rsvd page.*/ + if (pBeamEntry->BeamformEntryCap & BEAMFORMER_CAP_VHT_SU) + Beamforming_SendVHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->AID, pBeamEntry->SoundBW, BEACON_QUEUE); + else + Beamforming_SendHTNDPAPacket(pDM_Odm, pBeamEntry->MacAddr, pBeamEntry->SoundBW, BEACON_QUEUE); + + /*check rsvd page download OK.*/ + BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_TDECTRL_8812A + 2); + count = 0; + while (!(BcnValidReg & BIT0) && count < 20) { + count++; + ODM_delay_ms(10); + BcnValidReg = ODM_Read1Byte(pDM_Odm, REG_TDECTRL_8812A + 2); + } + DLBcnCount++; + } while (!(BcnValidReg & BIT0) && DLBcnCount < 5); + + if (!(BcnValidReg & BIT0)) + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("%s Download RSVD page failed!\n", __func__)); + + /*TDECTRL[15:8] 0x209[7:0] = 0xF6 Beacon Head for TXDMA*/ + ODM_Write1Byte(pDM_Odm, REG_TDECTRL_8812A + 1, TxPageBndy); + + /*To make sure that if there exists an adapter which would like to send beacon.*/ + /*If exists, the origianl value of 0x422[6] will be 1, we should check this to*/ + /*prevent from setting 0x422[6] to 0 after download reserved page, or it will cause*/ + /*the beacon cannot be sent by HW.*/ + /*2010.06.23. Added by tynli.*/ + if (bSendBeacon) + ODM_Write1Byte(pDM_Odm, REG_FWHW_TXQ_CTRL_8812A + 2, tmpReg422); + + /*Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.*/ + /*Clear CR[8] or beacon packet will not be send to TxBuf anymore.*/ + u1bTmp = ODM_Read1Byte(pDM_Odm, REG_CR_8812A + 1); + ODM_Write1Byte(pDM_Odm, REG_CR_8812A + 1, (u1bTmp & (~BIT0))); + + pBeamEntry->BeamformEntryState = BEAMFORMING_ENTRY_STATE_PROGRESSED; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + *pDM_Odm->pbFwDwRsvdPageInProgress = FALSE; +#endif +} + + +VOID +halTxbfJaguar_FwTxBFCmd( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte Idx, Period0 = 0, Period1 = 0; + u1Byte PageNum0 = 0xFF, PageNum1 = 0xFF; + u1Byte u1TxBFParm[3] = {0}; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + + for (Idx = 0; Idx < BEAMFORMEE_ENTRY_NUM; Idx++) { + /*Modified by David*/ + if (pBeamInfo->BeamformeeEntry[Idx].bUsed && pBeamInfo->BeamformeeEntry[Idx].BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (Idx == 0) { + if (pBeamInfo->BeamformeeEntry[Idx].bSound) + PageNum0 = 0xFE; + else + PageNum0 = 0xFF; /*stop sounding*/ + Period0 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod); + } else if (Idx == 1) { + if (pBeamInfo->BeamformeeEntry[Idx].bSound) + PageNum1 = 0xFE; + else + PageNum1 = 0xFF; /*stop sounding*/ + Period1 = (u1Byte)(pBeamInfo->BeamformeeEntry[Idx].SoundPeriod); + } + } + } + + u1TxBFParm[0] = PageNum0; + u1TxBFParm[1] = PageNum1; + u1TxBFParm[2] = (Period1 << 4) | Period0; + ODM_FillH2CCmd(pDM_Odm, PHYDM_H2C_TXBF, 3, u1TxBFParm); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, + ("[%s] PageNum0 = %d Period0 = %d, PageNum1 = %d Period1 %d\n", __func__, PageNum0, Period0, PageNum1, Period1)); +} + + +VOID +HalTxbfJaguar_Enter( + IN PVOID pDM_VOID, + IN u1Byte BFerBFeeIdx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u1Byte i = 0; + u1Byte BFerIdx = (BFerBFeeIdx & 0xF0) >> 4; + u1Byte BFeeIdx = (BFerBFeeIdx & 0xF); + u4Byte CSI_Param; + PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + RT_BEAMFORMEE_ENTRY BeamformeeEntry; + RT_BEAMFORMER_ENTRY BeamformerEntry; + u2Byte STAid = 0; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Start!\n", __func__)); + + halTxbfJaguar_RfMode(pDM_Odm, pBeamformingInfo); + + if (pDM_Odm->RFType == ODM_2T2R) + ODM_SetBBReg(pDM_Odm, ODM_REG_CSI_CONTENT_VALUE, bMaskDWord, 0x00000000); /*Nc =2*/ + else + ODM_SetBBReg(pDM_Odm, ODM_REG_CSI_CONTENT_VALUE, bMaskDWord, 0x01081008); /*Nc =1*/ + + if ((pBeamformingInfo->beamformer_su_cnt > 0) && (BFerIdx < BEAMFORMER_ENTRY_NUM)) { + BeamformerEntry = pBeamformingInfo->BeamformerEntry[BFerIdx]; + + /*Sounding protocol control*/ + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xCB); + + /*MAC address/Partial AID of Beamformer*/ + if (BFerIdx == 0) { + for (i = 0; i < 6 ; i++) + ODM_Write1Byte(pDM_Odm, (REG_BFMER0_INFO_8812A + i), BeamformerEntry.MacAddr[i]); + /*CSI report use legacy ofdm so don't need to fill P_AID. */ + /*PlatformEFIOWrite2Byte(Adapter, REG_BFMER0_INFO_8812A+6, BeamformEntry.P_AID); */ + } else { + for (i = 0; i < 6 ; i++) + ODM_Write1Byte(pDM_Odm, (REG_BFMER1_INFO_8812A + i), BeamformerEntry.MacAddr[i]); + /*CSI report use legacy ofdm so don't need to fill P_AID.*/ + /*PlatformEFIOWrite2Byte(Adapter, REG_BFMER1_INFO_8812A+6, BeamformEntry.P_AID);*/ + } + + /*CSI report parameters of Beamformee*/ + if (BeamformerEntry.BeamformEntryCap & BEAMFORMEE_CAP_VHT_SU) { + if (pDM_Odm->RFType == ODM_2T2R) + CSI_Param = 0x01090109; + else + CSI_Param = 0x01080108; + } else { + if (pDM_Odm->RFType == ODM_2T2R) + CSI_Param = 0x03090309; + else + CSI_Param = 0x03080308; + } + + ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8812A, CSI_Param); + ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8812A, CSI_Param); + ODM_Write4Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8812A, CSI_Param); + + /*Timeout value for MAC to leave NDP_RX_standby_state (60 us, Test chip) (80 us, MP chip)*/ + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A + 3, 0x50); + } + + + if ((pBeamformingInfo->beamformee_su_cnt > 0) && (BFeeIdx < BEAMFORMEE_ENTRY_NUM)) { + BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[BFeeIdx]; + + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) + STAid = BeamformeeEntry.MacId; + else + STAid = BeamformeeEntry.P_AID; + + /*P_AID of Beamformee & enable NDPA transmission & enable NDPA interrupt*/ + if (BFeeIdx == 0) { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A, STAid); + ODM_Write1Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 3, ODM_Read1Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 3) | BIT4 | BIT6 | BIT7); + } else + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 2, STAid | BIT12 | BIT14 | BIT15); + + /*CSI report parameters of Beamformee*/ + if (BFeeIdx == 0) { + /*Get BIT24 & BIT25*/ + u1Byte tmp = ODM_Read1Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 3) & 0x3; + + ODM_Write1Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 3, tmp | 0x60); + ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A, STAid | BIT9); + } else { + /*Set BIT25*/ + ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 2, STAid | 0xE200); + } + phydm_Beamforming_Notify(pDM_Odm); + } +} + + +VOID +HalTxbfJaguar_Leave( + IN PVOID pDM_VOID, + IN u1Byte Idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamformingInfo = &pDM_Odm->BeamformingInfo; + RT_BEAMFORMER_ENTRY BeamformerEntry; + RT_BEAMFORMEE_ENTRY BeamformeeEntry; + + if (Idx < BEAMFORMER_ENTRY_NUM) { + BeamformerEntry = pBeamformingInfo->BeamformerEntry[Idx]; + BeamformeeEntry = pBeamformingInfo->BeamformeeEntry[Idx]; + } else + return; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s]Start!, IDx = %d\n", __func__, Idx)); + + /*Clear P_AID of Beamformee*/ + /*Clear MAC address of Beamformer*/ + /*Clear Associated Bfmee Sel*/ + + if (BeamformerEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) { + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xC8); + if (Idx == 0) { + ODM_Write4Byte(pDM_Odm, REG_BFMER0_INFO_8812A, 0); + ODM_Write2Byte(pDM_Odm, REG_BFMER0_INFO_8812A + 4, 0); + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8812A, 0); + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8812A, 0); + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8812A, 0); + } else { + ODM_Write4Byte(pDM_Odm, REG_BFMER1_INFO_8812A, 0); + ODM_Write2Byte(pDM_Odm, REG_BFMER1_INFO_8812A + 4, 0); + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW20_8812A, 0); + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW40_8812A, 0); + ODM_Write2Byte(pDM_Odm, REG_CSI_RPT_PARAM_BW80_8812A, 0); + } + } + + if (BeamformeeEntry.BeamformEntryCap == BEAMFORMING_CAP_NONE) { + halTxbfJaguar_RfMode(pDM_Odm, pBeamformingInfo); + if (Idx == 0) { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A, 0x0); + ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A, 0); + } else { + ODM_Write2Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 2, ODM_Read2Byte(pDM_Odm, REG_TXBF_CTRL_8812A + 2) & 0xF000); + ODM_Write2Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 2, ODM_Read2Byte(pDM_Odm, REG_BFMEE_SEL_8812A + 2) & 0x60); + } + } + +} + + +VOID +HalTxbfJaguar_Status( + IN PVOID pDM_VOID, + IN u1Byte Idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u2Byte BeamCtrlVal; + u4Byte BeamCtrlReg; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + RT_BEAMFORMEE_ENTRY BeamformEntry = pBeamInfo->BeamformeeEntry[Idx]; + + if (phydm_actingDetermine(pDM_Odm, PhyDM_ACTING_AS_IBSS)) + BeamCtrlVal = BeamformEntry.MacId; + else + BeamCtrlVal = BeamformEntry.P_AID; + + if (Idx == 0) + BeamCtrlReg = REG_TXBF_CTRL_8812A; + else { + BeamCtrlReg = REG_TXBF_CTRL_8812A + 2; + BeamCtrlVal |= BIT12 | BIT14 | BIT15; + } + + if (BeamformEntry.BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSED) { + if (BeamformEntry.SoundBW == CHANNEL_WIDTH_20) + BeamCtrlVal |= BIT9; + else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_40) + BeamCtrlVal |= (BIT9 | BIT10); + else if (BeamformEntry.SoundBW == CHANNEL_WIDTH_80) + BeamCtrlVal |= (BIT9 | BIT10 | BIT11); + } else + BeamCtrlVal &= ~(BIT9 | BIT10 | BIT11); + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] BeamCtrlVal = 0x%x!\n", __func__, BeamCtrlVal)); + + ODM_Write2Byte(pDM_Odm, BeamCtrlReg, BeamCtrlVal); +} + + + +VOID +HalTxbfJaguar_FwTxBF( + IN PVOID pDM_VOID, + IN u1Byte Idx +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + PRT_BEAMFORMEE_ENTRY pBeamEntry = pBeamInfo->BeamformeeEntry + Idx; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (pBeamEntry->BeamformEntryState == BEAMFORMING_ENTRY_STATE_PROGRESSING) + halTxbfJaguar_DownloadNDPA(pDM_Odm, Idx); + + halTxbfJaguar_FwTxBFCmd(pDM_Odm); +} + + +VOID +HalTxbfJaguar_Patch( + IN PVOID pDM_VOID, + IN u1Byte Operation +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + PRT_BEAMFORMING_INFO pBeamInfo = &pDM_Odm->BeamformingInfo; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (pBeamInfo->BeamformCap == BEAMFORMING_CAP_NONE) + return; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + if (Operation == SCAN_OPT_BACKUP_BAND0) + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xC8); + else if (Operation == SCAN_OPT_RESTORE) + ODM_Write1Byte(pDM_Odm, REG_SND_PTCL_CTRL_8812A, 0xCB); +#endif +} + +VOID +HalTxbfJaguar_Clk_8812A( + IN PVOID pDM_VOID +) +{ + PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID; + u2Byte u2btmp; + u1Byte Count = 0, u1btmp; + PADAPTER Adapter = pDM_Odm->Adapter; + + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] Start!\n", __func__)); + + if (*(pDM_Odm->pbScanInProcess)) { + ODM_RT_TRACE(pDM_Odm, PHYDM_COMP_TXBF, ODM_DBG_LOUD, ("[%s] return by Scan\n", __func__)); + return; + } +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + /*Stop PCIe TxDMA*/ + ODM_Write1Byte(pDM_Odm, REG_PCIE_CTRL_REG_8812A + 1, 0xFE); +#endif + + /*Stop Usb TxDMA*/ +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + RT_DISABLE_FUNC(Adapter, DF_TX_BIT); + PlatformReturnAllPendingTxPackets(Adapter); +#else + rtw_write_port_cancel(Adapter); +#endif + + /*Wait TXFF empty*/ + for (Count = 0; Count < 100; Count++) { + u2btmp = ODM_Read2Byte(pDM_Odm, REG_TXPKT_EMPTY_8812A); + u2btmp = u2btmp & 0xfff; + if (u2btmp != 0xfff) { + ODM_delay_ms(10); + continue; + } else + break; + } + + /*TX pause*/ + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812A, 0xFF); + + /*Wait TX State Machine OK*/ + for (Count = 0; Count < 100; Count++) { + if (ODM_Read4Byte(pDM_Odm, REG_SCH_TXCMD_8812A) != 0) + continue; + else + break; + } + + + /*Stop RX DMA path*/ + u1btmp = ODM_Read1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A); + ODM_Write1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A, u1btmp | BIT2); + + for (Count = 0; Count < 100; Count++) { + u1btmp = ODM_Read1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A); + if (u1btmp & BIT1) + break; + else + ODM_delay_ms(10); + } + + /*Disable clock*/ + ODM_Write1Byte(pDM_Odm, REG_SYS_CLKR_8812A + 1, 0xf0); + /*Disable 320M*/ + ODM_Write1Byte(pDM_Odm, REG_AFE_PLL_CTRL_8812A + 3, 0x8); + /*Enable 320M*/ + ODM_Write1Byte(pDM_Odm, REG_AFE_PLL_CTRL_8812A + 3, 0xa); + /*Enable clock*/ + ODM_Write1Byte(pDM_Odm, REG_SYS_CLKR_8812A + 1, 0xfc); + + + /*Release Tx pause*/ + ODM_Write1Byte(pDM_Odm, REG_TXPAUSE_8812A, 0); + + /*Enable RX DMA path*/ + u1btmp = ODM_Read1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A); + ODM_Write1Byte(pDM_Odm, REG_RXDMA_CONTROL_8812A, u1btmp & (~BIT2)); +#if DEV_BUS_TYPE == RT_PCI_INTERFACE + /*Enable PCIe TxDMA*/ + ODM_Write1Byte(pDM_Odm, REG_PCIE_CTRL_REG_8812A + 1, 0); +#endif + /*Start Usb TxDMA*/ + RT_ENABLE_FUNC(Adapter, DF_TX_BIT); +} + +#endif + + + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbfjaguar.h b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbfjaguar.h new file mode 100644 index 000000000..8b10e0e7f --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/phydm/txbf/haltxbfjaguar.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __HAL_TXBF_JAGUAR_H__ +#define __HAL_TXBF_JAGUAR_H__ + +#if (BEAMFORMING_SUPPORT == 1) +#if ((RTL8812A_SUPPORT == 1) || (RTL8821A_SUPPORT == 1)) +VOID +HalTxbf8812A_setNDPArate( + IN PVOID pDM_VOID, + IN u1Byte BW, + IN u1Byte Rate +); + + +VOID +HalTxbfJaguar_Enter( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + + +VOID +HalTxbfJaguar_Leave( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + + +VOID +HalTxbfJaguar_Status( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + + +VOID +HalTxbfJaguar_FwTxBF( + IN PVOID pDM_VOID, + IN u1Byte Idx + ); + + +VOID +HalTxbfJaguar_Patch( + IN PVOID pDM_VOID, + IN u1Byte Operation + ); + + +VOID +HalTxbfJaguar_Clk_8812A( + IN PVOID pDM_VOID + ); + +#else + +#define HalTxbf8812A_setNDPArate(pDM_VOID, BW, Rate) +#define HalTxbfJaguar_Enter(pDM_VOID, Idx) +#define HalTxbfJaguar_Leave(pDM_VOID, Idx) +#define HalTxbfJaguar_Status(pDM_VOID, Idx) +#define HalTxbfJaguar_FwTxBF(pDM_VOID, Idx) +#define HalTxbfJaguar_Patch(pDM_VOID, Operation) +#define HalTxbfJaguar_Clk_8812A(pDM_VOID) +#endif + +#endif +#endif // #ifndef __HAL_TXBF_JAGUAR_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/Hal8188FPwrSeq.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/Hal8188FPwrSeq.c new file mode 100644 index 000000000..13f210a6f --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/Hal8188FPwrSeq.c @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/*++ +Copyright (c) Realtek Semiconductor Corp. All rights reserved. + +Module Name: + Hal8188FPwrSeq.c + +Abstract: + This file includes all kinds of Power Action event for RTL8188F and corresponding hardware configurtions which are released from HW SD. + +Major Change History: + When What + ------------------- --------------- + 2014-08-18 Create. + +--*/ + +#include "Hal8188FPwrSeq.h" + + +/* + drivers should parse below arrays and do the corresponding actions +*/ +/*3 Power on Array */ +WLAN_PWR_CFG rtl8188F_power_on_flow[RTL8188F_TRANS_CARDEMU_TO_ACT_STEPS + RTL8188F_TRANS_END_STEPS] = { + RTL8188F_TRANS_CARDEMU_TO_ACT + RTL8188F_TRANS_END +}; + +/*3Radio off GPIO Array */ +WLAN_PWR_CFG rtl8188F_radio_off_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_END_STEPS] = { + RTL8188F_TRANS_ACT_TO_CARDEMU + RTL8188F_TRANS_END +}; + +/*3Card Disable Array */ +WLAN_PWR_CFG rtl8188F_card_disable_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188F_TRANS_END_STEPS] = { + RTL8188F_TRANS_ACT_TO_CARDEMU + RTL8188F_TRANS_CARDEMU_TO_CARDDIS + RTL8188F_TRANS_END +}; + +/*3 Card Enable Array */ +WLAN_PWR_CFG rtl8188F_card_enable_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188F_TRANS_END_STEPS] = { + RTL8188F_TRANS_CARDDIS_TO_CARDEMU + RTL8188F_TRANS_CARDEMU_TO_ACT + RTL8188F_TRANS_END +}; + +/*3Suspend Array */ +WLAN_PWR_CFG rtl8188F_suspend_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_SUS_STEPS + RTL8188F_TRANS_END_STEPS] = { + RTL8188F_TRANS_ACT_TO_CARDEMU + RTL8188F_TRANS_CARDEMU_TO_SUS + RTL8188F_TRANS_END +}; + +/*3 Resume Array */ +WLAN_PWR_CFG rtl8188F_resume_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_SUS_STEPS + RTL8188F_TRANS_END_STEPS] = { + RTL8188F_TRANS_SUS_TO_CARDEMU + RTL8188F_TRANS_CARDEMU_TO_ACT + RTL8188F_TRANS_END +}; + + + +/*3HWPDN Array */ +WLAN_PWR_CFG rtl8188F_hwpdn_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188F_TRANS_END_STEPS] = { + RTL8188F_TRANS_ACT_TO_CARDEMU + RTL8188F_TRANS_CARDEMU_TO_PDN + RTL8188F_TRANS_END +}; + +/*3 Enter LPS */ +WLAN_PWR_CFG rtl8188F_enter_lps_flow[RTL8188F_TRANS_ACT_TO_LPS_STEPS + RTL8188F_TRANS_END_STEPS] = { + /*FW behavior */ + RTL8188F_TRANS_ACT_TO_LPS + RTL8188F_TRANS_END +}; + +/*3 Leave LPS */ +WLAN_PWR_CFG rtl8188F_leave_lps_flow[RTL8188F_TRANS_LPS_TO_ACT_STEPS + RTL8188F_TRANS_END_STEPS] = { + /*FW behavior */ + RTL8188F_TRANS_LPS_TO_ACT + RTL8188F_TRANS_END +}; + +/*3 Enter SW LPS */ +WLAN_PWR_CFG rtl8188F_enter_swlps_flow[RTL8188F_TRANS_ACT_TO_SWLPS_STEPS + RTL8188F_TRANS_END_STEPS] = { + /*SW behavior */ + RTL8188F_TRANS_ACT_TO_SWLPS + RTL8188F_TRANS_END +}; + +/*3 Leave SW LPS */ +WLAN_PWR_CFG rtl8188F_leave_swlps_flow[RTL8188F_TRANS_SWLPS_TO_ACT_STEPS + RTL8188F_TRANS_END_STEPS] = { + /*SW behavior */ + RTL8188F_TRANS_SWLPS_TO_ACT + RTL8188F_TRANS_END +}; diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_cmd.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_cmd.c new file mode 100644 index 000000000..eb5aaeca4 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_cmd.c @@ -0,0 +1,1299 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTL8188F_CMD_C_ + +#include +#include "hal_com_h2c.h" + +#define MAX_H2C_BOX_NUMS 4 +#define MESSAGE_BOX_SIZE 4 + +#define RTL8188F_MAX_CMD_LEN 7 +#define RTL8188F_EX_MESSAGE_BOX_SIZE 4 + +static u8 _is_fw_read_cmd_down(_adapter *padapter, u8 msgbox_num) +{ + u8 read_down = _FALSE; + int retry_cnts = 100; + + u8 valid; + + /*DBG_8192C(" _is_fw_read_cmd_down ,reg_1cc(%x),msg_box(%d)...\n",rtw_read8(padapter,REG_HMETFR),msgbox_num); */ + + do { + valid = rtw_read8(padapter, REG_HMETFR) & BIT(msgbox_num); + if (0 == valid) + read_down = _TRUE; + else + rtw_msleep_os(1); + } while ((!read_down) && (retry_cnts--)); + + return read_down; + +} + + +/***************************************** +* H2C Msg format : +*| 31 - 8 |7-5 | 4 - 0 | +*| h2c_msg |Class |CMD_ID | +*| 31-0 | +*| Ext msg | +* +******************************************/ +s32 FillH2CCmd8188F(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer) +{ + u8 h2c_box_num; + u32 msgbox_addr; + u32 msgbox_ex_addr = 0; + PHAL_DATA_TYPE pHalData; + u32 h2c_cmd = 0; + u32 h2c_cmd_ex = 0; + s32 ret = _FAIL; + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + _func_enter_; + + padapter = GET_PRIMARY_ADAPTER(padapter); + pHalData = GET_HAL_DATA(padapter); +#ifdef DBG_CHECK_FW_PS_STATE +#ifdef DBG_CHECK_FW_PS_STATE_H2C + if (rtw_fw_ps_state(padapter) == _FAIL) { + DBG_871X("%s: h2c doesn't leave 32k ElementID=%02x\n", __func__, ElementID); + pdbgpriv->dbg_h2c_leave32k_fail_cnt++; + } + + /*DBG_871X("H2C ElementID=%02x , pHalData->LastHMEBoxNum=%02x\n", ElementID, pHalData->LastHMEBoxNum); */ +#endif /*DBG_CHECK_FW_PS_STATE_H2C */ +#endif /*DBG_CHECK_FW_PS_STATE */ + _enter_critical_mutex(&(adapter_to_dvobj(padapter)->h2c_fwcmd_mutex), NULL); + + if (!pCmdBuffer) + goto exit; + if (CmdLen > RTL8188F_MAX_CMD_LEN) + goto exit; + if (rtw_is_surprise_removed(padapter)) + goto exit; + + /*pay attention to if race condition happened in H2C cmd setting. */ + do { + h2c_box_num = pHalData->LastHMEBoxNum; + + if (!_is_fw_read_cmd_down(padapter, h2c_box_num)) { + DBG_8192C(" fw read cmd failed...\n"); +#ifdef DBG_CHECK_FW_PS_STATE + DBG_871X("MAC_1C0=%08x, MAC_1C4=%08x, MAC_1C8=%08x, MAC_1CC=%08x\n", rtw_read32(padapter, 0x1c0), rtw_read32(padapter, 0x1c4) + , rtw_read32(padapter, 0x1c8), rtw_read32(padapter, 0x1cc)); +#endif /*DBG_CHECK_FW_PS_STATE */ + /*DBG_8192C(" 0x1c0: 0x%8x\n", rtw_read32(padapter, 0x1c0)); */ + /*DBG_8192C(" 0x1c4: 0x%8x\n", rtw_read32(padapter, 0x1c4)); */ + goto exit; + } + + if (CmdLen <= 3) + _rtw_memcpy((u8 *)(&h2c_cmd) + 1, pCmdBuffer, CmdLen); + else { + _rtw_memcpy((u8 *)(&h2c_cmd) + 1, pCmdBuffer, 3); + _rtw_memcpy((u8 *)(&h2c_cmd_ex), pCmdBuffer + 3, CmdLen - 3); + /**(u8*)(&h2c_cmd) |= BIT(7); */ + } + + *(u8 *)(&h2c_cmd) |= ElementID; + + if (CmdLen > 3) { + msgbox_ex_addr = REG_HMEBOX_EXT0_8188F + (h2c_box_num * RTL8188F_EX_MESSAGE_BOX_SIZE); + h2c_cmd_ex = le32_to_cpu(h2c_cmd_ex); + rtw_write32(padapter, msgbox_ex_addr, h2c_cmd_ex); + } + msgbox_addr = REG_HMEBOX_0 + (h2c_box_num * MESSAGE_BOX_SIZE); + h2c_cmd = le32_to_cpu(h2c_cmd); + rtw_write32(padapter, msgbox_addr, h2c_cmd); + + /*DBG_8192C("MSG_BOX:%d, CmdLen(%d), CmdID(0x%x), reg:0x%x =>h2c_cmd:0x%.8x, reg:0x%x =>h2c_cmd_ex:0x%.8x\n" */ + /* ,pHalData->LastHMEBoxNum , CmdLen, ElementID, msgbox_addr, h2c_cmd, msgbox_ex_addr, h2c_cmd_ex); */ + + pHalData->LastHMEBoxNum = (h2c_box_num + 1) % MAX_H2C_BOX_NUMS; + + } while (0); + + ret = _SUCCESS; + +exit: + + _exit_critical_mutex(&(adapter_to_dvobj(padapter)->h2c_fwcmd_mutex), NULL); + + _func_exit_; + + return ret; +} + +static void ConstructBeacon(_adapter *padapter, u8 *pframe, u32 *pLength) +{ + struct rtw_ieee80211_hdr *pwlanhdr; + u16 *fctrl; + u32 rate_len, pktlen; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); + u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + + + /*DBG_871X("%s\n", __func__); */ + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN); + + SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/); + /*pmlmeext->mgnt_seq++; */ + SetFrameSubType(pframe, WIFI_BEACON); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + /*timestamp will be inserted by hardware */ + pframe += 8; + pktlen += 8; + + /* beacon interval: 2 bytes */ + _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2); + + pframe += 2; + pktlen += 2; + + /* capability info: 2 bytes */ + _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); + + pframe += 2; + pktlen += 2; + + if ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE) { + /*DBG_871X("ie len=%d\n", cur_network->IELength); */ + pktlen += cur_network->IELength - sizeof(NDIS_802_11_FIXED_IEs); + _rtw_memcpy(pframe, cur_network->IEs + sizeof(NDIS_802_11_FIXED_IEs), pktlen); + + goto _ConstructBeacon; + } + + /*below for ad-hoc mode */ + + /* SSID */ + pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen); + + /* supported rates... */ + rate_len = rtw_get_rateset_len(cur_network->SupportedRates); + pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8) ? 8 : rate_len), cur_network->SupportedRates, &pktlen); + + /* DS parameter set */ + pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *) &(cur_network->Configuration.DSConfig), &pktlen); + + if ((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) { + u32 ATIMWindow; + /* IBSS Parameter Set... */ + /*ATIMWindow = cur->Configuration.ATIMWindow; */ + ATIMWindow = 0; + pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen); + } + + + /*todo: ERP IE */ + + + /* EXTERNDED SUPPORTED RATE */ + if (rate_len > 8) + pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen); + + + /*todo:HT for adhoc */ + +_ConstructBeacon: + + if ((pktlen + TXDESC_SIZE) > 512) { + DBG_871X("beacon frame too large\n"); + return; + } + + *pLength = pktlen; + + /*DBG_871X("%s bcn_sz=%d\n", __func__, pktlen); */ + +} + +static void ConstructPSPoll(_adapter *padapter, u8 *pframe, u32 *pLength) +{ + struct rtw_ieee80211_hdr *pwlanhdr; + u16 *fctrl; + u32 pktlen; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + /*DBG_871X("%s\n", __func__); */ + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + /* Frame control. */ + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + SetPwrMgt(fctrl); + SetFrameSubType(pframe, WIFI_PSPOLL); + + /* AID. */ + SetDuration(pframe, (pmlmeinfo->aid | 0xc000)); + + /* BSSID. */ + _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + /* TA. */ + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + + *pLength = 16; +} + +static void ConstructNullFunctionData( + PADAPTER padapter, + u8 *pframe, + u32 *pLength, + u8 *StaAddr, + u8 bQoS, + u8 AC, + u8 bEosp, + u8 bForcePowerSave) +{ + struct rtw_ieee80211_hdr *pwlanhdr; + u16 *fctrl; + u32 pktlen; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wlan_network *cur_network = &pmlmepriv->cur_network; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + + /*DBG_871X("%s:%d\n", __func__, bForcePowerSave); */ + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &pwlanhdr->frame_ctl; + *(fctrl) = 0; + if (bForcePowerSave) + SetPwrMgt(fctrl); + + switch (cur_network->network.InfrastructureMode) { + case Ndis802_11Infrastructure: + SetToDs(fctrl); + _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, StaAddr, ETH_ALEN); + break; + case Ndis802_11APMode: + SetFrDs(fctrl); + _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, adapter_mac_addr(padapter), ETH_ALEN); + break; + case Ndis802_11IBSS: + default: + _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + break; + } + + SetSeqNum(pwlanhdr, 0); + + if (bQoS == _TRUE) { + struct rtw_ieee80211_hdr_3addr_qos *pwlanqoshdr; + + SetFrameSubType(pframe, WIFI_QOS_DATA_NULL); + + pwlanqoshdr = (struct rtw_ieee80211_hdr_3addr_qos *)pframe; + SetPriority(&pwlanqoshdr->qc, AC); + SetEOSP(&pwlanqoshdr->qc, bEosp); + + pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos); + } else { + SetFrameSubType(pframe, WIFI_DATA_NULL); + + pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + } + + *pLength = pktlen; +} + +/* To check if reserved page content is destroyed by beacon because beacon is too large. */ +/* 2010.06.23. Added by tynli. */ +VOID +CheckFwRsvdPageContent( + IN PADAPTER Adapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u32 MaxBcnPageNum; + + if (pHalData->FwRsvdPageStartOffset != 0) { + /*MaxBcnPageNum = PageNum_128(pMgntInfo->MaxBeaconSize); + RT_ASSERT((MaxBcnPageNum <= pHalData->FwRsvdPageStartOffset), + ("CheckFwRsvdPageContent(): The reserved page content has been"\ + "destroyed by beacon!!! MaxBcnPageNum(%d) FwRsvdPageStartOffset(%d)\n!", + MaxBcnPageNum, pHalData->FwRsvdPageStartOffset));*/ + } +} + +/* */ +/* Description: Get the reserved page number in Tx packet buffer. */ +/* Retrun value: the page number. */ +/* 2012.08.09, by tynli. */ +/* */ +u8 GetTxBufferRsvdPageNum8188F(_adapter *padapter, bool wowlan) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8 RsvdPageNum = 0; + /* default reseved 1 page for the IC type which is undefined. */ + u8 TxPageBndy = LAST_ENTRY_OF_TX_PKT_BUFFER_8188F; + + rtw_hal_get_def_var(padapter, HAL_DEF_TX_PAGE_BOUNDARY, (u8 *)&TxPageBndy); + + RsvdPageNum = LAST_ENTRY_OF_TX_PKT_BUFFER_8188F - TxPageBndy + 1; + + return RsvdPageNum; +} + +static void rtl8188f_set_FwRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc) +{ + u8 u1H2CRsvdPageParm[H2C_RSVDPAGE_LOC_LEN] = {0}; + + DBG_871X("8188FRsvdPageLoc: ProbeRsp=%d PsPoll=%d Null=%d QoSNull=%d BTNull=%d\n", + rsvdpageloc->LocProbeRsp, rsvdpageloc->LocPsPoll, + rsvdpageloc->LocNullData, rsvdpageloc->LocQosNull, + rsvdpageloc->LocBTQosNull); + + SET_8188F_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1H2CRsvdPageParm, rsvdpageloc->LocProbeRsp); + SET_8188F_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1H2CRsvdPageParm, rsvdpageloc->LocPsPoll); + SET_8188F_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocNullData); + SET_8188F_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocQosNull); + SET_8188F_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(u1H2CRsvdPageParm, rsvdpageloc->LocBTQosNull); + + RT_PRINT_DATA(_module_hal_init_c_, _drv_always_, "u1H2CRsvdPageParm:", u1H2CRsvdPageParm, H2C_RSVDPAGE_LOC_LEN); + FillH2CCmd8188F(padapter, H2C_8188F_RSVD_PAGE, H2C_RSVDPAGE_LOC_LEN, u1H2CRsvdPageParm); +} + +static void rtl8188f_set_FwAoacRsvdPage_cmd(PADAPTER padapter, PRSVDPAGE_LOC rsvdpageloc) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + u8 res = 0, count = 0; +} + +static void rtl8188f_set_FwKeepAlive_cmd(PADAPTER padapter, u8 benable, u8 pkt_type) +{ + u8 u1H2CKeepAliveParm[H2C_KEEP_ALIVE_CTRL_LEN] = {0}; + u8 adopt = 1; +#ifdef CONFIG_PLATFORM_INTEL_BYT + u8 check_period = 10; +#else + u8 check_period = 5; +#endif + + DBG_871X("%s(): benable = %d\n", __func__, benable); + SET_8188F_H2CCMD_KEEPALIVE_PARM_ENABLE(u1H2CKeepAliveParm, benable); + SET_8188F_H2CCMD_KEEPALIVE_PARM_ADOPT(u1H2CKeepAliveParm, adopt); + SET_8188F_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(u1H2CKeepAliveParm, pkt_type); + SET_8188F_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(u1H2CKeepAliveParm, check_period); + + RT_PRINT_DATA(_module_hal_init_c_, _drv_always_, "u1H2CKeepAliveParm:", u1H2CKeepAliveParm, H2C_KEEP_ALIVE_CTRL_LEN); + + FillH2CCmd8188F(padapter, H2C_8188F_KEEP_ALIVE, H2C_KEEP_ALIVE_CTRL_LEN, u1H2CKeepAliveParm); +} + +static void rtl8188f_set_FwDisconDecision_cmd(PADAPTER padapter, u8 benable) +{ + u8 u1H2CDisconDecisionParm[H2C_DISCON_DECISION_LEN] = {0}; + u8 adopt = 1, check_period = 10, trypkt_num = 0; + + DBG_871X("%s(): benable = %d\n", __func__, benable); + SET_8188F_H2CCMD_DISCONDECISION_PARM_ENABLE(u1H2CDisconDecisionParm, benable); + SET_8188F_H2CCMD_DISCONDECISION_PARM_ADOPT(u1H2CDisconDecisionParm, adopt); + SET_8188F_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(u1H2CDisconDecisionParm, check_period); + SET_8188F_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(u1H2CDisconDecisionParm, trypkt_num); + + RT_PRINT_DATA(_module_hal_init_c_, _drv_always_, "u1H2CDisconDecisionParm:", u1H2CDisconDecisionParm, H2C_DISCON_DECISION_LEN); + + FillH2CCmd8188F(padapter, H2C_8188F_DISCON_DECISION, H2C_DISCON_DECISION_LEN, u1H2CDisconDecisionParm); +} + +void rtl8188f_set_FwMacIdConfig_cmd(_adapter *padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8 u1H2CMacIdConfigParm[H2C_MACID_CFG_LEN] = {0}; + + DBG_871X("%s(): mac_id=%d raid=0x%x bw=%d mask=0x%x\n", __func__, mac_id, raid, bw, mask); + + _func_enter_; + + SET_8188F_H2CCMD_MACID_CFG_MACID(u1H2CMacIdConfigParm, mac_id); + SET_8188F_H2CCMD_MACID_CFG_RAID(u1H2CMacIdConfigParm, raid); + SET_8188F_H2CCMD_MACID_CFG_SGI_EN(u1H2CMacIdConfigParm, (sgi) ? 1 : 0); + SET_8188F_H2CCMD_MACID_CFG_BW(u1H2CMacIdConfigParm, bw); + + /*DisableTXPowerTraining */ + if (pHalData->bDisableTXPowerTraining) { + SET_8188F_H2CCMD_MACID_CFG_DISPT(u1H2CMacIdConfigParm, 1); + DBG_871X("%s,Disable PWT by driver\n", __func__); + } else { + PDM_ODM_T pDM_OutSrc = &pHalData->odmpriv; + + if (pDM_OutSrc->bDisablePowerTraining) { + SET_8188F_H2CCMD_MACID_CFG_DISPT(u1H2CMacIdConfigParm, 1); + DBG_871X("%s,Disable PWT by DM\n", __func__); + } + } + + SET_8188F_H2CCMD_MACID_CFG_RATE_MASK0(u1H2CMacIdConfigParm, (u8)(mask & 0x000000ff)); + SET_8188F_H2CCMD_MACID_CFG_RATE_MASK1(u1H2CMacIdConfigParm, (u8)((mask & 0x0000ff00) >> 8)); + SET_8188F_H2CCMD_MACID_CFG_RATE_MASK2(u1H2CMacIdConfigParm, (u8)((mask & 0x00ff0000) >> 16)); + SET_8188F_H2CCMD_MACID_CFG_RATE_MASK3(u1H2CMacIdConfigParm, (u8)((mask & 0xff000000) >> 24)); + + RT_PRINT_DATA(_module_hal_init_c_, _drv_always_, "u1H2CMacIdConfigParm:", u1H2CMacIdConfigParm, H2C_MACID_CFG_LEN); + FillH2CCmd8188F(padapter, H2C_8188F_MACID_CFG, H2C_MACID_CFG_LEN, u1H2CMacIdConfigParm); + + _func_exit_; +} + +void rtl8188f_set_FwRssiSetting_cmd(_adapter *padapter, u8 *param) +{ + u8 u1H2CRssiSettingParm[H2C_RSSI_SETTING_LEN] = {0}; + u8 mac_id = *param; + u8 rssi = *(param + 2); + u8 uldl_state = 0; + + _func_enter_; + /*DBG_871X("%s(): param=%.2x-%.2x-%.2x\n", __func__, *param, *(param+1), *(param+2)); */ + /*DBG_871X("%s(): mac_id=%d rssi=%d\n", __func__, mac_id, rssi); */ + + SET_8188F_H2CCMD_RSSI_SETTING_MACID(u1H2CRssiSettingParm, mac_id); + SET_8188F_H2CCMD_RSSI_SETTING_RSSI(u1H2CRssiSettingParm, rssi); + SET_8188F_H2CCMD_RSSI_SETTING_ULDL_STATE(u1H2CRssiSettingParm, uldl_state); + + RT_PRINT_DATA(_module_hal_init_c_, _drv_notice_, "u1H2CRssiSettingParm:", u1H2CRssiSettingParm, H2C_RSSI_SETTING_LEN); + FillH2CCmd8188F(padapter, H2C_8188F_RSSI_SETTING, H2C_RSSI_SETTING_LEN, u1H2CRssiSettingParm); + + _func_exit_; +} + +void rtl8188f_set_FwAPReqRPT_cmd(PADAPTER padapter, u32 need_ack) +{ + u8 u1H2CApReqRptParm[H2C_AP_REQ_TXRPT_LEN] = {0}; + u8 macid1 = 1, macid2 = 0; + + DBG_871X("%s(): need_ack = %d\n", __func__, need_ack); + + SET_8188F_H2CCMD_APREQRPT_PARM_MACID1(u1H2CApReqRptParm, macid1); + SET_8188F_H2CCMD_APREQRPT_PARM_MACID2(u1H2CApReqRptParm, macid2); + + RT_PRINT_DATA(_module_hal_init_c_, _drv_always_, "u1H2CApReqRptParm:", u1H2CApReqRptParm, H2C_AP_REQ_TXRPT_LEN); + FillH2CCmd8188F(padapter, H2C_8188F_AP_REQ_TXRPT, H2C_AP_REQ_TXRPT_LEN, u1H2CApReqRptParm); +} + +void rtl8188f_set_FwPwrMode_cmd(PADAPTER padapter, u8 psmode) +{ + int i; + u8 smart_ps = 0; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + u8 u1H2CPwrModeParm[H2C_PWRMODE_LEN] = {0}; + u8 PowerState = 0, awake_intvl = 1, byte5 = 0, rlbm = 0; +#ifdef CONFIG_P2P + struct wifidirect_info *wdinfo = &(padapter->wdinfo); +#endif /* CONFIG_P2P */ + + _func_enter_; + +#ifdef CONFIG_PLATFORM_INTEL_BYT + if (psmode == PS_MODE_DTIM) + psmode = PS_MODE_MAX; +#endif /*CONFIG_PLATFORM_INTEL_BYT */ + + + if (pwrpriv->dtim > 0) + DBG_871X("%s(): FW LPS mode = %d, SmartPS=%d, dtim=%d\n", __func__, psmode, pwrpriv->smart_ps, pwrpriv->dtim); + else + DBG_871X("%s(): FW LPS mode = %d, SmartPS=%d\n", __func__, psmode, pwrpriv->smart_ps); + + if (psmode == PS_MODE_MIN) { + rlbm = 0; + awake_intvl = 2; + smart_ps = pwrpriv->smart_ps; + } else if (psmode == PS_MODE_MAX) { + rlbm = 1; + awake_intvl = 2; + smart_ps = pwrpriv->smart_ps; + } else if (psmode == PS_MODE_DTIM) { /*For WOWLAN LPS, DTIM = (awake_intvl - 1) */ + if (pwrpriv->dtim > 0 && pwrpriv->dtim < 16) + awake_intvl = pwrpriv->dtim + 1; /*DTIM = (awake_intvl - 1) */ + else + awake_intvl = 4;/*DTIM=3 */ + + + rlbm = 2; + smart_ps = pwrpriv->smart_ps; + } else { + rlbm = 2; + awake_intvl = 4; + smart_ps = pwrpriv->smart_ps; + } + +#ifdef CONFIG_P2P + if (!rtw_p2p_chk_state(wdinfo, P2P_STATE_NONE)) { + awake_intvl = 2; + rlbm = 1; + } +#endif /* CONFIG_P2P */ + + if (padapter->registrypriv.wifi_spec == 1) { + awake_intvl = 2; + rlbm = 1; + } + + if (psmode > 0) { +#ifdef CONFIG_BT_COEXIST + if (rtw_btcoex_IsBtControlLps(padapter) == _TRUE) { + PowerState = rtw_btcoex_RpwmVal(padapter); + byte5 = rtw_btcoex_LpsVal(padapter); + + if ((rlbm == 2) && (byte5 & BIT(4))) { + /* Keep awake interval to 1 to prevent from */ + /* decreasing coex performance */ + awake_intvl = 2; + rlbm = 2; + } + } else +#endif /* CONFIG_BT_COEXIST */ + { + PowerState = 0x00;/* AllON(0x0C), RFON(0x04), RFOFF(0x00) */ + byte5 = 0x40; + } + } else { + PowerState = 0x0C;/* AllON(0x0C), RFON(0x04), RFOFF(0x00) */ + byte5 = 0x40; + } + + SET_8188F_H2CCMD_PWRMODE_PARM_MODE(u1H2CPwrModeParm, (psmode > 0) ? 1 : 0); + SET_8188F_H2CCMD_PWRMODE_PARM_SMART_PS(u1H2CPwrModeParm, smart_ps); + SET_8188F_H2CCMD_PWRMODE_PARM_RLBM(u1H2CPwrModeParm, rlbm); + SET_8188F_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(u1H2CPwrModeParm, awake_intvl); + SET_8188F_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(u1H2CPwrModeParm, padapter->registrypriv.uapsd_enable); + SET_8188F_H2CCMD_PWRMODE_PARM_PWR_STATE(u1H2CPwrModeParm, PowerState); + SET_8188F_H2CCMD_PWRMODE_PARM_BYTE5(u1H2CPwrModeParm, byte5); +#ifdef CONFIG_LPS_LCLK + if (psmode != PS_MODE_ACTIVE) { + if (pmlmeext->adaptive_tsf_done == _FALSE && pmlmeext->bcn_cnt > 0) { + u8 ratio_20_delay, ratio_80_delay; + + /*byte 6 for adaptive_early_32k */ + /*[0:3] = DrvBcnEarly (ms) , [4:7] = DrvBcnTimeOut (ms) */ + /* 20% for DrvBcnEarly, 80% for DrvBcnTimeOut */ + ratio_20_delay = 0; + ratio_80_delay = 0; + pmlmeext->DrvBcnEarly = 0xff; + pmlmeext->DrvBcnTimeOut = 0xff; + + /*DBG_871X("%s(): bcn_cnt = %d\n", __func__, pmlmeext->bcn_cnt); */ + + for (i = 0; i < 9; i++) { + pmlmeext->bcn_delay_ratio[i] = (pmlmeext->bcn_delay_cnt[i] * 100) / pmlmeext->bcn_cnt; + + /*DBG_871X("%s(): bcn_delay_cnt[%d]=%d, bcn_delay_ratio[%d] = %d\n", __func__, i, pmlmeext->bcn_delay_cnt[i] */ + /* ,i ,pmlmeext->bcn_delay_ratio[i]); */ + + ratio_20_delay += pmlmeext->bcn_delay_ratio[i]; + ratio_80_delay += pmlmeext->bcn_delay_ratio[i]; + + if (ratio_20_delay > 20 && pmlmeext->DrvBcnEarly == 0xff) { + pmlmeext->DrvBcnEarly = i; + /*DBG_871X("%s(): DrvBcnEarly = %d\n", __func__, pmlmeext->DrvBcnEarly); */ + } + + if (ratio_80_delay > 80 && pmlmeext->DrvBcnTimeOut == 0xff) { + pmlmeext->DrvBcnTimeOut = i; + /*DBG_871X("%s(): DrvBcnTimeOut = %d\n", __func__, pmlmeext->DrvBcnTimeOut); */ + } + + /*reset adaptive_early_32k cnt */ + pmlmeext->bcn_delay_cnt[i] = 0; + pmlmeext->bcn_delay_ratio[i] = 0; + + } + + pmlmeext->bcn_cnt = 0; + pmlmeext ->adaptive_tsf_done = _TRUE; + + } else { + /*DBG_871X("%s(): DrvBcnEarly = %d\n", __func__, pmlmeext->DrvBcnEarly); */ + /*DBG_871X("%s(): DrvBcnTimeOut = %d\n", __func__, pmlmeext->DrvBcnTimeOut); */ + } + + /* offload to FW if fw version > v15.10 + pmlmeext->DrvBcnEarly=0; + pmlmeext->DrvBcnTimeOut=7; + + if((pmlmeext->DrvBcnEarly!=0Xff) && (pmlmeext->DrvBcnTimeOut!=0xff)) + u1H2CPwrModeParm[H2C_PWRMODE_LEN-1] = BIT(0) | ((pmlmeext->DrvBcnEarly<<1)&0x0E) |((pmlmeext->DrvBcnTimeOut<<4)&0xf0); + */ + + } +#endif + +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_RecordPwrMode(padapter, u1H2CPwrModeParm, H2C_PWRMODE_LEN); +#endif /* CONFIG_BT_COEXIST */ + + RT_PRINT_DATA(_module_hal_init_c_, _drv_always_, "u1H2CPwrModeParm:", u1H2CPwrModeParm, H2C_PWRMODE_LEN); + + FillH2CCmd8188F(padapter, H2C_8188F_SET_PWR_MODE, H2C_PWRMODE_LEN, u1H2CPwrModeParm); + _func_exit_; +} + +#ifdef CONFIG_TDLS +#ifdef CONFIG_TDLS_CH_SW +void rtl8188f_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable) +{ + u8 u1H2CSetPwrMode[H2C_PWRMODE_LEN] = {0}; + + SET_8188F_H2CCMD_PWRMODE_PARM_MODE(u1H2CSetPwrMode, 1); + SET_8188F_H2CCMD_PWRMODE_PARM_RLBM(u1H2CSetPwrMode, 1); + SET_8188F_H2CCMD_PWRMODE_PARM_SMART_PS(u1H2CSetPwrMode, 0); + SET_8188F_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(u1H2CSetPwrMode, 0); + SET_8188F_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(u1H2CSetPwrMode, 0); + SET_8188F_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(u1H2CSetPwrMode, enable); + SET_8188F_H2CCMD_PWRMODE_PARM_PWR_STATE(u1H2CSetPwrMode, 0x0C); + SET_8188F_H2CCMD_PWRMODE_PARM_BYTE5(u1H2CSetPwrMode, 0); + FillH2CCmd8188F(padapter, H2C_8188F_SET_PWR_MODE, sizeof(u1H2CSetPwrMode), u1H2CSetPwrMode); +} +#endif +#endif + +void rtl8188f_set_FwPsTuneParam_cmd(PADAPTER padapter) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + u8 u1H2CPsTuneParm[H2C_PSTUNEPARAM_LEN] = {0}; + u8 bcn_to_limit = 10; /*10 * 100 * awakeinterval (ms) */ + u8 dtim_timeout = 5; /*ms //wait broadcast data timer */ + u8 ps_timeout = 20; /*ms //Keep awake when tx */ + u8 dtim_period = 3; + + _func_enter_; + /*DBG_871X("%s(): FW LPS mode = %d\n", __func__, psmode); */ + + SET_8188F_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(u1H2CPsTuneParm, bcn_to_limit); + SET_8188F_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(u1H2CPsTuneParm, dtim_timeout); + SET_8188F_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(u1H2CPsTuneParm, ps_timeout); + SET_8188F_H2CCMD_PSTUNE_PARM_ADOPT(u1H2CPsTuneParm, 1); + SET_8188F_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(u1H2CPsTuneParm, dtim_period); + + RT_PRINT_DATA(_module_hal_init_c_, _drv_always_, "u1H2CPsTuneParm:", u1H2CPsTuneParm, H2C_PSTUNEPARAM_LEN); + + FillH2CCmd8188F(padapter, H2C_8188F_PS_TUNING_PARA, H2C_PSTUNEPARAM_LEN, u1H2CPsTuneParm); + _func_exit_; +} + +void rtl8188f_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param) +{ + u8 u1H2CBtMpOperParm[H2C_BTMP_OPER_LEN] = {0}; + + _func_enter_; + + DBG_8192C("%s: idx=%d ver=%d reqnum=%d param1=0x%02x param2=0x%02x\n", __func__, idx, ver, reqnum, param[0], param[1]); + + SET_8188F_H2CCMD_BT_MPOPER_VER(u1H2CBtMpOperParm, ver); + SET_8188F_H2CCMD_BT_MPOPER_REQNUM(u1H2CBtMpOperParm, reqnum); + SET_8188F_H2CCMD_BT_MPOPER_IDX(u1H2CBtMpOperParm, idx); + SET_8188F_H2CCMD_BT_MPOPER_PARAM1(u1H2CBtMpOperParm, param[0]); + SET_8188F_H2CCMD_BT_MPOPER_PARAM2(u1H2CBtMpOperParm, param[1]); + SET_8188F_H2CCMD_BT_MPOPER_PARAM3(u1H2CBtMpOperParm, param[2]); + + RT_PRINT_DATA(_module_hal_init_c_, _drv_always_, "u1H2CBtMpOperParm:", u1H2CBtMpOperParm, H2C_BTMP_OPER_LEN); + + FillH2CCmd8188F(padapter, H2C_8188F_BT_MP_OPER, H2C_BTMP_OPER_LEN, u1H2CBtMpOperParm); + _func_exit_; +} + +void rtl8188f_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param) +{ + /*u8 cmd_param; //BIT0:enable, BIT1:NoConnect32k */ + + DBG_871X("%s()\n", __func__); + + cmd_param = cmd_param; + + FillH2CCmd8188F(padapter, H2C_8188F_FWLPS_IN_IPS_, 1, &cmd_param); + +} + + +static s32 rtl8188f_set_FwLowPwrLps_cmd(PADAPTER padapter, u8 enable) +{ + /*TODO */ + return _FALSE; +} + + +void rtl8188f_download_rsvd_page(PADAPTER padapter, u8 mstatus) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + BOOLEAN bcn_valid = _FALSE; + u8 DLBcnCount = 0; + u32 poll = 0; + u8 val8; + + _func_enter_; + + DBG_8192C("+" FUNC_ADPT_FMT ": iface_type=%d mstatus(%x)\n", + FUNC_ADPT_ARG(padapter), get_iface_type(padapter), mstatus); + + if (mstatus == RT_MEDIA_CONNECT) { + BOOLEAN bRecover = _FALSE; + u8 v8; + + /* We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C. */ + /* Suggested by filen. Added by tynli. */ + rtw_write16(padapter, REG_BCN_PSR_RPT, (0xC000 | pmlmeinfo->aid)); + + /* set REG_CR bit 8 */ + v8 = rtw_read8(padapter, REG_CR + 1); + v8 |= BIT(0); /* ENSWBCN */ + rtw_write8(padapter, REG_CR + 1, v8); + + /* Disable Hw protection for a time which revserd for Hw sending beacon. */ + /* Fix download reserved page packet fail that access collision with the protection time. */ + /* 2010.05.11. Added by tynli. */ + val8 = rtw_read8(padapter, REG_BCN_CTRL); + val8 &= ~EN_BCN_FUNCTION; + val8 |= DIS_TSF_UDT; + rtw_write8(padapter, REG_BCN_CTRL, val8); + + /* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. */ + if (pHalData->RegFwHwTxQCtrl & BIT(6)) + bRecover = _TRUE; + + /* To tell Hw the packet is not a real beacon frame. */ + rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, pHalData->RegFwHwTxQCtrl & ~BIT(6)); + pHalData->RegFwHwTxQCtrl &= ~BIT(6); + + /* Clear beacon valid check bit. */ + rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL); + rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL); + + DLBcnCount = 0; + poll = 0; + do { + rtw_hal_set_fw_rsvd_page(padapter, 0); + + DLBcnCount++; + do { + rtw_yield_os(); + /*rtw_mdelay_os(10); */ + /* check rsvd page download OK. */ + rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8 *)(&bcn_valid)); + poll++; + } while (!bcn_valid && (poll%10) != 0 && !RTW_CANNOT_RUN(padapter)); + + } while (!bcn_valid && DLBcnCount <= 100 && !RTW_CANNOT_RUN(padapter)); + + if (RTW_CANNOT_RUN(padapter)) + ; + else if (!bcn_valid) + DBG_871X(ADPT_FMT": 1 DL RSVD page failed! DLBcnCount:%u, poll:%u\n", + ADPT_ARG(padapter) , DLBcnCount, poll); + else { + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); + pwrctl->fw_psmode_iface_id = padapter->iface_id; + DBG_871X(ADPT_FMT": 1 DL RSVD page success! DLBcnCount:%u, poll:%u\n", + ADPT_ARG(padapter), DLBcnCount, poll); + } + + /* 2010.05.11. Added by tynli. */ + val8 = rtw_read8(padapter, REG_BCN_CTRL); + val8 |= EN_BCN_FUNCTION; + val8 &= ~DIS_TSF_UDT; + rtw_write8(padapter, REG_BCN_CTRL, val8); + + /* To make sure that if there exists an adapter which would like to send beacon. */ + /* If exists, the origianl value of 0x422[6] will be 1, we should check this to */ + /* prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */ + /* the beacon cannot be sent by HW. */ + /* 2010.06.23. Added by tynli. */ + if (bRecover) { + rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, pHalData->RegFwHwTxQCtrl | BIT(6)); + pHalData->RegFwHwTxQCtrl |= BIT(6); + } + + /* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */ + v8 = rtw_read8(padapter, REG_CR + 1); + v8 &= ~BIT(0); /* ~ENSWBCN */ + rtw_write8(padapter, REG_CR + 1, v8); + } + + _func_exit_; +} + +void rtl8188f_set_rssi_cmd(_adapter *padapter, u8 *param) +{ + rtl8188f_set_FwRssiSetting_cmd(padapter, param); +} + +void rtl8188f_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus) +{ + struct sta_info *psta = NULL; + struct pwrctrl_priv *ppwrpriv = adapter_to_pwrctl(padapter); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + if (mstatus == 1) + rtl8188f_download_rsvd_page(padapter, RT_MEDIA_CONNECT); +} + +/*arg[0] = macid */ +/*arg[1] = raid */ +/*arg[2] = shortGIrate */ +/*arg[3] = init_rate */ +void rtl8188f_Add_RateATid(PADAPTER pAdapter, u64 rate_bitmap, u8 *arg, u8 rssi_level) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + struct macid_ctl_t *macid_ctl = &pAdapter->dvobj->macid_ctl; + struct sta_info *psta = NULL; + u8 mac_id = arg[0]; + u8 raid = arg[1]; + u8 shortGI = arg[2]; + u8 bw; + u32 bitmap = (u32) rate_bitmap; + u32 mask = bitmap & 0x0FFFFFFF; + + if (mac_id < macid_ctl->num) + psta = macid_ctl->sta[mac_id]; + if (psta == NULL) { + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" macid:%u, sta is NULL\n" + , FUNC_ADPT_ARG(pAdapter), mac_id); + return; + } + + bw = psta->bw_mode; + + if (rssi_level != DM_RATR_STA_INIT) + mask = ODM_Get_Rate_Bitmap(&pHalData->odmpriv, mac_id, mask, rssi_level); + + DBG_871X("%s(): mac_id=%d raid=0x%x bw=%d mask=0x%x\n", __func__, mac_id, raid, bw, mask); + rtl8188f_set_FwMacIdConfig_cmd(pAdapter, mac_id, raid, bw, shortGI, mask); +} + +#if 0 +void rtl8188f_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack) +{ + rtl8188f_set_FwAPReqRPT_cmd(padapter, need_ack); +} +#endif + +#ifdef CONFIG_BT_COEXIST +static void ConstructBtNullFunctionData( + PADAPTER padapter, + u8 *pframe, + u32 *pLength, + u8 *StaAddr, + u8 bQoS, + u8 AC, + u8 bEosp, + u8 bForcePowerSave) +{ + struct rtw_ieee80211_hdr *pwlanhdr; + u16 *fctrl; + u32 pktlen; + struct mlme_ext_priv *pmlmeext; + struct mlme_ext_info *pmlmeinfo; + u8 bssid[ETH_ALEN]; + + + DBG_871X("+" FUNC_ADPT_FMT ": qos=%d eosp=%d ps=%d\n", + FUNC_ADPT_ARG(padapter), bQoS, bEosp, bForcePowerSave); + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + pmlmeext = &padapter->mlmeextpriv; + pmlmeinfo = &pmlmeext->mlmext_info; + + if (NULL == StaAddr) { + _rtw_memcpy(bssid, myid(&padapter->eeprompriv), ETH_ALEN); + StaAddr = bssid; + } + + fctrl = &pwlanhdr->frame_ctl; + *fctrl = 0; + if (bForcePowerSave) + SetPwrMgt(fctrl); + + SetFrDs(fctrl); + _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, myid(&padapter->eeprompriv), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, myid(&padapter->eeprompriv), ETH_ALEN); + + SetDuration(pwlanhdr, 0); + SetSeqNum(pwlanhdr, 0); + + if (bQoS == _TRUE) { + struct rtw_ieee80211_hdr_3addr_qos *pwlanqoshdr; + + SetFrameSubType(pframe, WIFI_QOS_DATA_NULL); + + pwlanqoshdr = (struct rtw_ieee80211_hdr_3addr_qos *)pframe; + SetPriority(&pwlanqoshdr->qc, AC); + SetEOSP(&pwlanqoshdr->qc, bEosp); + + pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos); + } else { + SetFrameSubType(pframe, WIFI_DATA_NULL); + + pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + } + + *pLength = pktlen; +} + +static void SetFwRsvdPagePkt_BTCoex(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData; + struct xmit_frame *pcmdframe; + struct pkt_attrib *pattrib; + struct xmit_priv *pxmitpriv; + struct mlme_ext_priv *pmlmeext; + struct mlme_ext_info *pmlmeinfo; + u32 BeaconLength = 0; + u32 BTQosNullLength = 0; + u8 *ReservedPagePacket; + u8 TxDescLen, TxDescOffset; + u8 TotalPageNum = 0, CurtPktPageNum = 0, RsvdPageNum = 0; + u16 BufIndex, PageSize; + u32 TotalPacketLen, MaxRsvdPageBufSize = 0; + RSVDPAGE_LOC RsvdPageLoc; + + + /*DBG_8192C("+" FUNC_ADPT_FMT "\n", FUNC_ADPT_ARG(padapter)); */ + + pHalData = GET_HAL_DATA(padapter); + pxmitpriv = &padapter->xmitpriv; + pmlmeext = &padapter->mlmeextpriv; + pmlmeinfo = &pmlmeext->mlmext_info; + TxDescLen = TXDESC_SIZE; + TxDescOffset = TXDESC_OFFSET; + PageSize = PAGE_SIZE_TX_8188F; + + RsvdPageNum = BCNQ_PAGE_NUM_8188F; + MaxRsvdPageBufSize = RsvdPageNum * PageSize; + + pcmdframe = rtw_alloc_cmdxmitframe(pxmitpriv); + if (pcmdframe == NULL) { + DBG_8192C("%s: alloc ReservedPagePacket fail!\n", __func__); + return; + } + + ReservedPagePacket = pcmdframe->buf_addr; + _rtw_memset(&RsvdPageLoc, 0, sizeof(RSVDPAGE_LOC)); + + /*3 (1) beacon */ + BufIndex = TxDescOffset; + ConstructBeacon(padapter, &ReservedPagePacket[BufIndex], &BeaconLength); + + /* When we count the first page size, we need to reserve description size for the RSVD */ + /* packet, it will be filled in front of the packet in TXPKTBUF. */ + CurtPktPageNum = (u8)PageNum_128(TxDescLen + BeaconLength); + /*If we don't add 1 more page, the WOWLAN function has a problem. Baron thinks it's a bug of firmware */ + if (CurtPktPageNum == 1) + CurtPktPageNum += 1; + TotalPageNum += CurtPktPageNum; + + BufIndex += (CurtPktPageNum * PageSize); + + /* Jump to lastest page */ + if (BufIndex < (MaxRsvdPageBufSize - PageSize)) { + BufIndex = TxDescOffset + (MaxRsvdPageBufSize - PageSize); + TotalPageNum = BCNQ_PAGE_NUM_8188F - 1; + } + + /*3 (6) BT Qos null data */ + RsvdPageLoc.LocBTQosNull = TotalPageNum; + ConstructBtNullFunctionData( + padapter, + &ReservedPagePacket[BufIndex], + &BTQosNullLength, + NULL, + _TRUE, 0, 0, _FALSE); + rtl8188f_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex - TxDescLen], BTQosNullLength, _FALSE, _TRUE, _FALSE); + + CurtPktPageNum = (u8)PageNum_128(TxDescLen + BTQosNullLength); + + TotalPageNum += CurtPktPageNum; + + TotalPacketLen = BufIndex + BTQosNullLength; + if (TotalPacketLen > MaxRsvdPageBufSize) { + DBG_8192C(FUNC_ADPT_FMT ": ERROR: The rsvd page size is not enough!!TotalPacketLen %d, MaxRsvdPageBufSize %d\n", + FUNC_ADPT_ARG(padapter), TotalPacketLen, MaxRsvdPageBufSize); + goto error; + } + + /* update attribute */ + pattrib = &pcmdframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + pattrib->qsel = QSLT_BEACON; + pattrib->pktlen = pattrib->last_txcmdsz = TotalPacketLen - TxDescOffset; +#ifdef CONFIG_PCI_HCI + dump_mgntframe(padapter, pcmdframe); +#else + dump_mgntframe_and_wait(padapter, pcmdframe, 100); +#endif + + /*DBG_8192C(FUNC_ADPT_FMT ": Set RSVD page location to Fw, TotalPacketLen(%d), TotalPageNum(%d)\n", */ + /* FUNC_ADPT_ARG(padapter), TotalPacketLen, TotalPageNum); */ + rtl8188f_set_FwRsvdPage_cmd(padapter, &RsvdPageLoc); + rtl8188f_set_FwAoacRsvdPage_cmd(padapter, &RsvdPageLoc); + + return; + +error: + rtw_free_xmitframe(pxmitpriv, pcmdframe); +} + +void rtl8188f_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData; + struct mlme_ext_priv *pmlmeext; + struct mlme_ext_info *pmlmeinfo; + u8 bRecover = _FALSE; + u8 bcn_valid = _FALSE; + u8 DLBcnCount = 0; + u32 poll = 0; + u8 val8; + + + DBG_8192C("+" FUNC_ADPT_FMT ": iface_type=%d fw_state=0x%08X\n", + FUNC_ADPT_ARG(padapter), get_iface_type(padapter), get_fwstate(&padapter->mlmepriv)); + +#ifdef CONFIG_DEBUG + if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _FALSE) { + DBG_8192C(FUNC_ADPT_FMT ": [WARNING] not in AP mode!!\n", + FUNC_ADPT_ARG(padapter)); + } +#endif /* CONFIG_DEBUG */ + + pHalData = GET_HAL_DATA(padapter); + pmlmeext = &padapter->mlmeextpriv; + pmlmeinfo = &pmlmeext->mlmext_info; + + /* We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C. */ + /* Suggested by filen. Added by tynli. */ + rtw_write16(padapter, REG_BCN_PSR_RPT, (0xC000 | pmlmeinfo->aid)); + + /* set REG_CR bit 8 */ + val8 = rtw_read8(padapter, REG_CR + 1); + val8 |= BIT(0); /* ENSWBCN */ + rtw_write8(padapter, REG_CR + 1, val8); + + /* Disable Hw protection for a time which revserd for Hw sending beacon. */ + /* Fix download reserved page packet fail that access collision with the protection time. */ + /* 2010.05.11. Added by tynli. */ + val8 = rtw_read8(padapter, REG_BCN_CTRL); + val8 &= ~EN_BCN_FUNCTION; + val8 |= DIS_TSF_UDT; + rtw_write8(padapter, REG_BCN_CTRL, val8); + + /* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. */ + if (pHalData->RegFwHwTxQCtrl & BIT(6)) + bRecover = _TRUE; + + /* To tell Hw the packet is not a real beacon frame. */ + pHalData->RegFwHwTxQCtrl &= ~BIT(6); + rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, pHalData->RegFwHwTxQCtrl); + + /* Clear beacon valid check bit. */ + rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL); + rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL); + + DLBcnCount = 0; + poll = 0; + do { + SetFwRsvdPagePkt_BTCoex(padapter); + DLBcnCount++; + do { + rtw_yield_os(); + /*rtw_mdelay_os(10); */ + /* check rsvd page download OK. */ + rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, &bcn_valid); + poll++; + } while (!bcn_valid && (poll % 10) != 0 && !RTW_CANNOT_RUN(padapter)); + } while (!bcn_valid && (DLBcnCount <= 100) && !RTW_CANNOT_RUN(padapter)); + + if (_TRUE == bcn_valid) { + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); + pwrctl->fw_psmode_iface_id = padapter->iface_id; + DBG_8192C(ADPT_FMT": DL RSVD page success! DLBcnCount:%d, poll:%d\n", + ADPT_ARG(padapter), DLBcnCount, poll); + } else { + DBG_871X(ADPT_FMT": DL RSVD page fail! DLBcnCount:%d, poll:%d\n", + ADPT_ARG(padapter), DLBcnCount, poll); + DBG_871X(ADPT_FMT": DL RSVD page fail! bSurpriseRemoved=%s\n", + ADPT_ARG(padapter), rtw_is_surprise_removed(padapter)?"True":"False"); + DBG_871X(ADPT_FMT": DL RSVD page fail! bDriverStopped=%s\n", + ADPT_ARG(padapter), rtw_is_drv_stopped(padapter)?"True":"False"); + } + + /* 2010.05.11. Added by tynli. */ + val8 = rtw_read8(padapter, REG_BCN_CTRL); + val8 |= EN_BCN_FUNCTION; + val8 &= ~DIS_TSF_UDT; + rtw_write8(padapter, REG_BCN_CTRL, val8); + + /* To make sure that if there exists an adapter which would like to send beacon. */ + /* If exists, the origianl value of 0x422[6] will be 1, we should check this to */ + /* prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */ + /* the beacon cannot be sent by HW. */ + /* 2010.06.23. Added by tynli. */ + if (bRecover) { + pHalData->RegFwHwTxQCtrl |= BIT(6); + rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, pHalData->RegFwHwTxQCtrl); + } + + /* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */ + val8 = rtw_read8(padapter, REG_CR + 1); + val8 &= ~BIT(0); /* ~ENSWBCN */ + rtw_write8(padapter, REG_CR + 1, val8); +} +#endif /* CONFIG_BT_COEXIST */ + +#ifdef CONFIG_P2P +void rtl8188f_set_p2p_ps_offload_cmd(_adapter *padapter, u8 p2p_ps_state) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + struct P2P_PS_Offload_t *p2p_ps_offload = (struct P2P_PS_Offload_t *)(&pHalData->p2p_ps_offload); + u8 i; + + _func_enter_; + +#if 1 + switch (p2p_ps_state) { + case P2P_PS_DISABLE: + DBG_8192C("P2P_PS_DISABLE\n"); + _rtw_memset(p2p_ps_offload, 0 , 1); + break; + case P2P_PS_ENABLE: + DBG_8192C("P2P_PS_ENABLE\n"); + /* update CTWindow value. */ + if (pwdinfo->ctwindow > 0) { + p2p_ps_offload->CTWindow_En = 1; + rtw_write8(padapter, REG_P2P_CTWIN, pwdinfo->ctwindow); + } + + /* hw only support 2 set of NoA */ + for (i = 0; i < pwdinfo->noa_num; i++) { + /* To control the register setting for which NOA */ + rtw_write8(padapter, REG_NOA_DESC_SEL, (i << 4)); + if (i == 0) + p2p_ps_offload->NoA0_En = 1; + else + p2p_ps_offload->NoA1_En = 1; + + /* config P2P NoA Descriptor Register */ + /*DBG_8192C("%s(): noa_duration = %x\n",__func__,pwdinfo->noa_duration[i]); */ + rtw_write32(padapter, REG_NOA_DESC_DURATION, pwdinfo->noa_duration[i]); + + /*DBG_8192C("%s(): noa_interval = %x\n",__func__,pwdinfo->noa_interval[i]); */ + rtw_write32(padapter, REG_NOA_DESC_INTERVAL, pwdinfo->noa_interval[i]); + + /*DBG_8192C("%s(): start_time = %x\n",__func__,pwdinfo->noa_start_time[i]); */ + rtw_write32(padapter, REG_NOA_DESC_START, pwdinfo->noa_start_time[i]); + + /*DBG_8192C("%s(): noa_count = %x\n",__func__,pwdinfo->noa_count[i]); */ + rtw_write8(padapter, REG_NOA_DESC_COUNT, pwdinfo->noa_count[i]); + } + + if ((pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0)) { + /* rst p2p circuit */ + rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(4)); + + p2p_ps_offload->Offload_En = 1; + + if (pwdinfo->role == P2P_ROLE_GO) { + p2p_ps_offload->role = 1; + p2p_ps_offload->AllStaSleep = 0; + } else + p2p_ps_offload->role = 0; + + p2p_ps_offload->discovery = 0; + } + break; + case P2P_PS_SCAN: + DBG_8192C("P2P_PS_SCAN\n"); + p2p_ps_offload->discovery = 1; + break; + case P2P_PS_SCAN_DONE: + DBG_8192C("P2P_PS_SCAN_DONE\n"); + p2p_ps_offload->discovery = 0; + pwdinfo->p2p_ps_state = P2P_PS_ENABLE; + break; + default: + break; + } + + FillH2CCmd8188F(padapter, H2C_8188F_P2P_PS_OFFLOAD, 1, (u8 *)p2p_ps_offload); +#endif + + _func_exit_; + +} +#endif /*CONFIG_P2P */ + + +#ifdef CONFIG_TSF_RESET_OFFLOAD +/* + ask FW to Reset sync register at Beacon early interrupt +*/ +u8 rtl8188f_reset_tsf(_adapter *padapter, u8 reset_port) +{ + u8 buf[2]; + u8 res = _SUCCESS; + + _func_enter_; + if (IFACE_PORT0 == reset_port) { + buf[0] = 0x1; + buf[1] = 0; + + } else { + buf[0] = 0x0; + buf[1] = 0x1; + } + FillH2CCmd8188F(padapter, H2C_8188F_RESET_TSF, 2, buf); + _func_exit_; + + return res; +} +#endif /* CONFIG_TSF_RESET_OFFLOAD */ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_dm.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_dm.c new file mode 100644 index 000000000..9d5b0d435 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_dm.c @@ -0,0 +1,619 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +/*============================================================ */ +/* Description: */ +/* */ +/* This file is for 92CE/92CU dynamic mechanism only */ +/* */ +/* */ +/*============================================================ */ +#define _RTL8188F_DM_C_ + +/*============================================================ */ +/* include files */ +/*============================================================ */ +#include + +/*============================================================ */ +/* Global var */ +/*============================================================ */ + + +static VOID +dm_CheckProtection( + IN PADAPTER Adapter +) +{ +#if 0 + PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); + u1Byte CurRate, RateThreshold; + + if (pMgntInfo->pHTInfo->bCurBW40MHz) + RateThreshold = MGN_MCS1; + else + RateThreshold = MGN_MCS3; + + if (Adapter->TxStats.CurrentInitTxRate <= RateThreshold) { + pMgntInfo->bDmDisableProtect = TRUE; + DbgPrint("Forced disable protect: %x\n", Adapter->TxStats.CurrentInitTxRate); + } else { + pMgntInfo->bDmDisableProtect = FALSE; + DbgPrint("Enable protect: %x\n", Adapter->TxStats.CurrentInitTxRate); + } +#endif +} + +static VOID +dm_CheckStatistics( + IN PADAPTER Adapter +) +{ +#if 0 + if (!Adapter->MgntInfo.bMediaConnect) + return; + + /*2008.12.10 tynli Add for getting Current_Tx_Rate_Reg flexibly. */ + rtw_hal_get_hwreg(Adapter, HW_VAR_INIT_TX_RATE, (pu1Byte)(&Adapter->TxStats.CurrentInitTxRate)); + + /* Calculate current Tx Rate(Successful transmited!!) */ + + /* Calculate current Rx Rate(Successful received!!) */ + + /*for tx tx retry count */ + rtw_hal_get_hwreg(Adapter, HW_VAR_RETRY_COUNT, (pu1Byte)(&Adapter->TxStats.NumTxRetryCount)); +#endif +} +#ifdef CONFIG_SUPPORT_HW_WPS_PBC +static void dm_CheckPbcGPIO(_adapter *padapter) +{ + u8 tmp1byte; + u8 bPbcPressed = _FALSE; + + if (!padapter->registrypriv.hw_wps_pbc) + return; + +#ifdef CONFIG_USB_HCI + tmp1byte = rtw_read8(padapter, GPIO_IO_SEL); + tmp1byte |= (HAL_8192C_HW_GPIO_WPS_BIT); + rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); /*enable GPIO[2] as output mode */ + + tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT); + rtw_write8(padapter, GPIO_IN, tmp1byte); /*reset the floating voltage level */ + + tmp1byte = rtw_read8(padapter, GPIO_IO_SEL); + tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT); + rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); /*enable GPIO[2] as input mode */ + + tmp1byte = rtw_read8(padapter, GPIO_IN); + + if (tmp1byte == 0xff) + return; + + if (tmp1byte & HAL_8192C_HW_GPIO_WPS_BIT) + bPbcPressed = _TRUE; +#else + tmp1byte = rtw_read8(padapter, GPIO_IN); + /*RT_TRACE(COMP_IO, DBG_TRACE, ("dm_CheckPbcGPIO - %x\n", tmp1byte)); */ + + if (tmp1byte == 0xff || padapter->init_adpt_in_progress) + return; + + if ((tmp1byte & HAL_8192C_HW_GPIO_WPS_BIT) == 0) + bPbcPressed = _TRUE; +#endif + + if (_TRUE == bPbcPressed) { + /* Here we only set bPbcPressed to true */ + /* After trigger PBC, the variable will be set to false */ + DBG_8192C("CheckPbcGPIO - PBC is pressed\n"); + rtw_request_wps_pbc_event(padapter); + } +} +#endif /*#ifdef CONFIG_SUPPORT_HW_WPS_PBC */ + + +#ifdef CONFIG_PCI_HCI +/* */ +/* Description: */ +/* Perform interrupt migration dynamically to reduce CPU utilization. */ +/* */ +/* Assumption: */ +/* 1. Do not enable migration under WIFI test. */ +/* */ +/* Created by Roger, 2010.03.05. */ +/* */ +VOID +dm_InterruptMigration( + IN PADAPTER Adapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + BOOLEAN bCurrentIntMt, bCurrentACIntDisable; + BOOLEAN IntMtToSet = _FALSE; + BOOLEAN ACIntToSet = _FALSE; + + + /* Retrieve current interrupt migration and Tx four ACs IMR settings first. */ + bCurrentIntMt = pHalData->bInterruptMigration; + bCurrentACIntDisable = pHalData->bDisableTxInt; + + /* */ + /* Currently we use busy traffic for reference instead of RxIntOK counts to prevent non-linear Rx statistics */ + /* when interrupt migration is set before. 2010.03.05. */ + /* */ + if (!Adapter->registrypriv.wifi_spec && + (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) && + pmlmepriv->LinkDetectInfo.bHigherBusyTraffic) { + IntMtToSet = _TRUE; + + /* To check whether we should disable Tx interrupt or not. */ + if (pmlmepriv->LinkDetectInfo.bHigherBusyRxTraffic) + ACIntToSet = _TRUE; + } + + /*Update current settings. */ + if (bCurrentIntMt != IntMtToSet) { + DBG_8192C("%s(): Update interrupt migration(%d)\n", __func__, IntMtToSet); + if (IntMtToSet) { + /* */ + /* Set interrupt migration timer and corresponging Tx/Rx counter. */ + /* timer 25ns*0xfa0=100us for 0xf packets. */ + /* 2010.03.05. */ + /* */ + rtw_write32(Adapter, REG_INT_MIG, 0xff000fa0);/* 0x306:Rx, 0x307:Tx */ + pHalData->bInterruptMigration = IntMtToSet; + } else { + /* Reset all interrupt migration settings. */ + rtw_write32(Adapter, REG_INT_MIG, 0); + pHalData->bInterruptMigration = IntMtToSet; + } + } + +#if 0 /* mask */ + if (bCurrentACIntDisable != ACIntToSet) { + DBG_8192C("%s(): Update AC interrupt(%d)\n", __func__, ACIntToSet); + if (ACIntToSet) { /* Disable four ACs interrupts. */ + /* */ + /* Disable VO, VI, BE and BK four AC interrupts to gain more efficient CPU utilization. */ + /* When extremely highly Rx OK occurs, we will disable Tx interrupts. */ + /* 2010.03.05. */ + /* */ + UpdateInterruptMask8192CE(Adapter, 0, RT_AC_INT_MASKS); + pHalData->bDisableTxInt = ACIntToSet; + } else { /* Enable four ACs interrupts. */ + UpdateInterruptMask8192CE(Adapter, RT_AC_INT_MASKS, 0); + pHalData->bDisableTxInt = ACIntToSet; + } + } +#endif + +} + +#endif + +/* */ +/* Initialize GPIO setting registers */ +/* */ +static void +dm_InitGPIOSetting( + IN PADAPTER Adapter +) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + + u8 tmp1byte; + + tmp1byte = rtw_read8(Adapter, REG_GPIO_MUXCFG); + tmp1byte &= (GPIOSEL_GPIO | ~GPIOSEL_ENBT); + + rtw_write8(Adapter, REG_GPIO_MUXCFG, tmp1byte); +} +/*============================================================ */ +/* functions */ +/*============================================================ */ +static void Init_ODM_ComInfo_8188f(PADAPTER Adapter) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + u32 SupportAbility = 0; + u8 cut_ver, fab_ver; + + Init_ODM_ComInfo(Adapter); + + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_PACKAGE_TYPE, pHalData->PackageType); + + fab_ver = ODM_TSMC; + cut_ver = GET_CVID_CUT_VERSION(pHalData->VersionID); + + DBG_871X("%s(): fab_ver=%d cut_ver=%d\n", __func__, fab_ver, cut_ver); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_FAB_VER, fab_ver); + ODM_CmnInfoInit(pDM_Odm, ODM_CMNINFO_CUT_VER, cut_ver); + +#ifdef CONFIG_DISABLE_ODM + SupportAbility = 0; +#else + SupportAbility = ODM_RF_CALIBRATION | + ODM_RF_TX_PWR_TRACK /*| */ + ; +#endif + + ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, SupportAbility); +} + +static void Update_ODM_ComInfo_8188f(PADAPTER Adapter) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + u32 SupportAbility = 0; + + SupportAbility = 0 + | ODM_BB_DIG + | ODM_BB_RA_MASK + | ODM_BB_DYNAMIC_TXPWR + | ODM_BB_FA_CNT + | ODM_BB_RSSI_MONITOR + | ODM_BB_CCK_PD + /* | ODM_BB_PWR_SAVE */ + | ODM_BB_CFO_TRACKING + | ODM_MAC_EDCA_TURBO + | ODM_RF_TX_PWR_TRACK + | ODM_RF_CALIBRATION + | ODM_BB_NHM_CNT + /*| ODM_BB_PWR_TRAIN */ + ; + + if (rtw_odm_adaptivity_needed(Adapter) == _TRUE) { + rtw_odm_adaptivity_config_msg(RTW_DBGDUMP, Adapter); + SupportAbility |= ODM_BB_ADAPTIVITY; + } + +#ifdef CONFIG_ANTENNA_DIVERSITY + if (pHalData->AntDivCfg) + SupportAbility |= ODM_BB_ANT_DIV; +#endif + +#if (MP_DRIVER==1) + if (Adapter->registrypriv.mp_mode == 1) { + SupportAbility = 0 + | ODM_RF_CALIBRATION + | ODM_RF_TX_PWR_TRACK + ; + } +#endif/*(MP_DRIVER==1) */ + +#ifdef CONFIG_DISABLE_ODM + SupportAbility = 0; +#endif/*CONFIG_DISABLE_ODM */ + + ODM_CmnInfoUpdate(pDM_Odm, ODM_CMNINFO_ABILITY, SupportAbility); +} + +void +rtl8188f_InitHalDm( + IN PADAPTER Adapter +) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + + u8 i; + +#ifdef CONFIG_USB_HCI + dm_InitGPIOSetting(Adapter); +#endif + + pHalData->DM_Type = DM_Type_ByDriver; + + Update_ODM_ComInfo_8188f(Adapter); + + ODM_DMInit(pDM_Odm); + +} + +#if 0 /* function never used */ +static void +FindMinimumRSSI_8188f( + IN PADAPTER pAdapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + struct mlme_priv *pmlmepriv = &pAdapter->mlmepriv; + + /*1 1.Determine the minimum RSSI */ + + +#ifdef CONFIG_CONCURRENT_MODE + /* FindMinimumRSSI() per-adapter */ + { + PADAPTER pbuddy_adapter = pAdapter->pbuddy_adapter; + PHAL_DATA_TYPE pbuddy_HalData = GET_HAL_DATA(pbuddy_adapter); + struct dm_priv *pbuddy_dmpriv = &pbuddy_HalData->dmpriv; + + if ((pHalData->EntryMinUndecoratedSmoothedPWDB != 0) && + (pbuddy_dmpriv->EntryMinUndecoratedSmoothedPWDB != 0)) { + + if (pHalData->EntryMinUndecoratedSmoothedPWDB > pbuddy_dmpriv->EntryMinUndecoratedSmoothedPWDB) + pHalData->EntryMinUndecoratedSmoothedPWDB = pbuddy_dmpriv->EntryMinUndecoratedSmoothedPWDB; + } else { + if (pHalData->EntryMinUndecoratedSmoothedPWDB == 0) + pHalData->EntryMinUndecoratedSmoothedPWDB = pbuddy_dmpriv->EntryMinUndecoratedSmoothedPWDB; + + } +#if 0 + if ((pHalData->UndecoratedSmoothedPWDB != (-1)) && + (pbuddy_dmpriv->UndecoratedSmoothedPWDB != (-1))) { + + if ((pHalData->UndecoratedSmoothedPWDB > pbuddy_dmpriv->UndecoratedSmoothedPWDB) && + (pbuddy_dmpriv->UndecoratedSmoothedPWDB != 0)) + pHalData->UndecoratedSmoothedPWDB = pbuddy_dmpriv->UndecoratedSmoothedPWDB; + } else { + if ((pHalData->UndecoratedSmoothedPWDB == (-1)) && (pbuddy_dmpriv->UndecoratedSmoothedPWDB != 0)) + pHalData->UndecoratedSmoothedPWDB = pbuddy_dmpriv->UndecoratedSmoothedPWDB; + } +#endif + } +#endif + + if ((check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) && + (pHalData->EntryMinUndecoratedSmoothedPWDB == 0)) { + pHalData->MinUndecoratedPWDBForDM = 0; + /*ODM_RT_TRACE(pDM_Odm,COMP_BB_POWERSAVING, DBG_LOUD, ("Not connected to any\n")); */ + } + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { /* Default port */ +#if 0 + if ((check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) { + pHalData->MinUndecoratedPWDBForDM = pHalData->EntryMinUndecoratedSmoothedPWDB; + /*ODM_RT_TRACE(pDM_Odm,COMP_BB_POWERSAVING, DBG_LOUD, ("AP Client PWDB = 0x%x\n", pHalData->MinUndecoratedPWDBForDM)); */ + } else { /*for STA mode */ + pHalData->MinUndecoratedPWDBForDM = pHalData->UndecoratedSmoothedPWDB; + /*ODM_RT_TRACE(pDM_Odm,COMP_BB_POWERSAVING, DBG_LOUD, ("STA Default Port PWDB = 0x%x\n", pHalData->MinUndecoratedPWDBForDM)); */ + } +#else + pHalData->MinUndecoratedPWDBForDM = pHalData->EntryMinUndecoratedSmoothedPWDB; +#endif + } else { /* associated entry pwdb */ + pHalData->MinUndecoratedPWDBForDM = pHalData->EntryMinUndecoratedSmoothedPWDB; + /*ODM_RT_TRACE(pDM_Odm,COMP_BB_POWERSAVING, DBG_LOUD, ("AP Ext Port or disconnect PWDB = 0x%x\n", pHalData->MinUndecoratedPWDBForDM)); */ + } + + /*odm_FindMinimumRSSI_Dmsp(pAdapter); */ + /*DBG_8192C("%s=>MinUndecoratedPWDBForDM(%d)\n",__func__,pHalData->MinUndecoratedPWDBForDM); */ + /*ODM_RT_TRACE(pDM_Odm,COMP_DIG, DBG_LOUD, ("MinUndecoratedPWDBForDM =%d\n",pHalData->MinUndecoratedPWDBForDM)); */ +} +#endif + +VOID +rtl8188f_HalDmWatchDog( + IN PADAPTER Adapter +) +{ + BOOLEAN bFwCurrentInPSMode = _FALSE; + BOOLEAN bFwPSAwake = _TRUE; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + +#ifdef CONFIG_CONCURRENT_MODE + PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter; +#endif /*CONFIG_CONCURRENT_MODE */ + + if (Adapter->registrypriv.mp_mode == 1 && Adapter->mppriv.mp_dm == 0) /* for MP power tracking */ + return; + + + if (!rtw_is_hw_init_completed(Adapter)) + goto skip_dm; + +#ifdef CONFIG_LPS + bFwCurrentInPSMode = adapter_to_pwrctl(Adapter)->bFwCurrentInPSMode; + rtw_hal_get_hwreg(Adapter, HW_VAR_FWLPS_RF_ON, (u8 *)(&bFwPSAwake)); +#endif + +#ifdef CONFIG_P2P + /* Fw is under p2p powersaving mode, driver should stop dynamic mechanism. */ + /* modifed by thomas. 2011.06.11. */ + if (Adapter->wdinfo.p2p_ps_mode) + bFwPSAwake = _FALSE; +#endif /*CONFIG_P2P */ + + if ((rtw_is_hw_init_completed(Adapter)) + && ((!bFwCurrentInPSMode) && bFwPSAwake)) { + /* */ + /* Calculate Tx/Rx statistics. */ + /* */ + dm_CheckStatistics(Adapter); + rtw_hal_check_rxfifo_full(Adapter); + /* */ + /* Dynamically switch RTS/CTS protection. */ + /* */ + /*dm_CheckProtection(Adapter); */ + +#ifdef CONFIG_PCI_HCI + /* 20100630 Joseph: Disable Interrupt Migration mechanism temporarily because it degrades Rx throughput. */ + /* Tx Migration settings. */ + /*dm_InterruptMigration(Adapter); */ + + /*if(Adapter->HalFunc.TxCheckStuckHandler(Adapter)) */ + /* PlatformScheduleWorkItem(&(GET_HAL_DATA(Adapter)->HalResetWorkItem)); */ +#endif + } + + /*ODM */ + if (rtw_is_hw_init_completed(Adapter)) { + u8 bLinked = _FALSE; + u8 bsta_state = _FALSE; + u8 bBtDisabled = _TRUE; + + if (rtw_linked_check(Adapter)) { + bLinked = _TRUE; + if (check_fwstate(&Adapter->mlmepriv, WIFI_STATION_STATE)) + bsta_state = _TRUE; + } + +#ifdef CONFIG_CONCURRENT_MODE + if (pbuddy_adapter && rtw_linked_check(pbuddy_adapter)) { + bLinked = _TRUE; + if (pbuddy_adapter && check_fwstate(&pbuddy_adapter->mlmepriv, WIFI_STATION_STATE)) + bsta_state = _TRUE; + } +#endif /*CONFIG_CONCURRENT_MODE */ + + ODM_CmnInfoUpdate(&pHalData->odmpriv , ODM_CMNINFO_LINK, bLinked); + ODM_CmnInfoUpdate(&pHalData->odmpriv , ODM_CMNINFO_STATION_STATE, bsta_state); + + /*FindMinimumRSSI_8188f(Adapter); */ + /*ODM_CmnInfoUpdate(&pHalData->odmpriv ,ODM_CMNINFO_RSSI_MIN, pHalData->MinUndecoratedPWDBForDM); */ + +#ifdef CONFIG_BT_COEXIST + bBtDisabled = rtw_btcoex_IsBtDisabled(Adapter); +#endif /* CONFIG_BT_COEXIST */ + ODM_CmnInfoUpdate(&pHalData->odmpriv, ODM_CMNINFO_BT_ENABLED, ((bBtDisabled == _TRUE) ? _FALSE : _TRUE)); + + ODM_DMWatchdog(&pHalData->odmpriv); + } + +skip_dm: + + /* Check GPIO to determine current RF on/off and Pbc status. */ + /* Check Hardware Radio ON/OFF or not */ + /*if(Adapter->MgntInfo.PowerSaveControl.bGpioRfSw) */ + /*{ */ + /*RTPRINT(FPWR, PWRHW, ("dm_CheckRfCtrlGPIO\n")); */ + /* dm_CheckRfCtrlGPIO(Adapter); */ + /*} */ +#ifdef CONFIG_SUPPORT_HW_WPS_PBC + dm_CheckPbcGPIO(Adapter); +#endif + return; +} + +void rtl8188f_hal_dm_in_lps(PADAPTER padapter) +{ + u32 PWDB_rssi = 0; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta = NULL; + + DBG_871X("%s, RSSI_Min=%d\n", __func__, pDM_Odm->RSSI_Min); + + /*update IGI */ + ODM_Write_DIG(pDM_Odm, pDM_Odm->RSSI_Min); + + + /*set rssi to fw */ + psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); + if (psta && (psta->rssi_stat.UndecoratedSmoothedPWDB > 0)) { + PWDB_rssi = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB << 16)); + + rtl8188f_set_rssi_cmd(padapter, (u8 *)&PWDB_rssi); + } + +} + +void rtl8188f_HalDmWatchDog_in_LPS(IN PADAPTER Adapter) +{ + u8 bLinked = _FALSE; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable; + struct sta_priv *pstapriv = &Adapter->stapriv; + struct sta_info *psta = NULL; +#ifdef CONFIG_CONCURRENT_MODE + PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter; +#endif /*CONFIG_CONCURRENT_MODE */ + + if (!rtw_is_hw_init_completed(Adapter)) + goto skip_lps_dm; + + + if (rtw_linked_check(Adapter)) + bLinked = _TRUE; + +#ifdef CONFIG_CONCURRENT_MODE + if (pbuddy_adapter && rtw_linked_check(pbuddy_adapter)) + bLinked = _TRUE; +#endif /*CONFIG_CONCURRENT_MODE */ + + ODM_CmnInfoUpdate(&pHalData->odmpriv , ODM_CMNINFO_LINK, bLinked); + + if (bLinked == _FALSE) + goto skip_lps_dm; + + if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR)) + goto skip_lps_dm; + + + /*ODM_DMWatchdog(&pHalData->odmpriv); */ + /*Do DIG by RSSI In LPS-32K */ + + /*.1 Find MIN-RSSI */ + psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); + if (psta == NULL) + goto skip_lps_dm; + + pHalData->EntryMinUndecoratedSmoothedPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; + + DBG_871X("CurIGValue=%d, EntryMinUndecoratedSmoothedPWDB = %d\n", pDM_DigTable->CurIGValue, pHalData->EntryMinUndecoratedSmoothedPWDB); + + if (pHalData->EntryMinUndecoratedSmoothedPWDB <= 0) + goto skip_lps_dm; + + pHalData->MinUndecoratedPWDBForDM = pHalData->EntryMinUndecoratedSmoothedPWDB; + + pDM_Odm->RSSI_Min = pHalData->MinUndecoratedPWDBForDM; + + /*if(pDM_DigTable->CurIGValue != pDM_Odm->RSSI_Min) */ + if ((pDM_DigTable->CurIGValue > pDM_Odm->RSSI_Min + 5) || + (pDM_DigTable->CurIGValue < pDM_Odm->RSSI_Min - 5)) + + { +#ifdef CONFIG_LPS + rtw_dm_in_lps_wk_cmd(Adapter); +#endif + } + + +skip_lps_dm: + + return; + +} + +void rtl8188f_init_dm_priv(IN PADAPTER Adapter) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T podmpriv = &pHalData->odmpriv; + Init_ODM_ComInfo_8188f(Adapter); + ODM_InitAllTimers(podmpriv); +} + +void rtl8188f_deinit_dm_priv(IN PADAPTER Adapter) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + PDM_ODM_T podmpriv = &pHalData->odmpriv; + ODM_CancelAllTimers(podmpriv); + +} + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_hal_init.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_hal_init.c new file mode 100644 index 000000000..4ebf83347 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_hal_init.c @@ -0,0 +1,7054 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _HAL_INIT_C_ + +#include +#include "hal_com_h2c.h" +#include + +#if 0 /* FW tx packet write */ +#define FW_DOWNLOAD_SIZE_8188F 8192 +#endif + +static VOID +_FWDownloadEnable( + IN PADAPTER padapter, + IN BOOLEAN enable +) +{ + u8 tmp, count = 0; + + if (enable) { + /* 8051 enable */ + tmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1); + rtw_write8(padapter, REG_SYS_FUNC_EN + 1, tmp | 0x04); + + tmp = rtw_read8(padapter, REG_MCUFWDL); + rtw_write8(padapter, REG_MCUFWDL, tmp | 0x01); + + do { + tmp = rtw_read8(padapter, REG_MCUFWDL); + if (tmp & 0x01) + break; + rtw_write8(padapter, REG_MCUFWDL, tmp | 0x01); + rtw_msleep_os(1); + } while (count++ < 100); + if (count > 0) + DBG_871X("%s: !!!!!!!!Write 0x80 Fail!: count = %d\n", __func__, count); + + /* 8051 reset */ + tmp = rtw_read8(padapter, REG_MCUFWDL + 2); + rtw_write8(padapter, REG_MCUFWDL + 2, tmp & 0xf7); + } else { + /* MCU firmware download disable. */ + tmp = rtw_read8(padapter, REG_MCUFWDL); + rtw_write8(padapter, REG_MCUFWDL, tmp & 0xfe); + } +} + +static int +_BlockWrite( + IN PADAPTER padapter, + IN PVOID buffer, + IN u32 buffSize +) +{ + int ret = _SUCCESS; + + u32 blockSize_p1 = 4; /* (Default) Phase #1 : PCI muse use 4-byte write to download FW */ + u32 blockSize_p2 = 8; /* Phase #2 : Use 8-byte, if Phase#1 use big size to write FW. */ + u32 blockSize_p3 = 1; /* Phase #3 : Use 1-byte, the remnant of FW image. */ + u32 blockCount_p1 = 0, blockCount_p2 = 0, blockCount_p3 = 0; + u32 remainSize_p1 = 0, remainSize_p2 = 0; + u8 *bufferPtr = (u8 *)buffer; + u32 i = 0, offset = 0; +#ifdef CONFIG_PCI_HCI + u8 remainFW[4] = {0, 0, 0, 0}; + u8 *p = NULL; +#endif + +#ifdef CONFIG_USB_HCI + blockSize_p1 = 196; // the same as 8188e +#endif + + /*printk("====>%s %d\n", __func__, __LINE__); */ + + /*3 Phase #1 */ + blockCount_p1 = buffSize / blockSize_p1; + remainSize_p1 = buffSize % blockSize_p1; + + if (blockCount_p1) { + RT_TRACE(_module_hal_init_c_, _drv_notice_, + ("_BlockWrite: [P1] buffSize(%d) blockSize_p1(%d) blockCount_p1(%d) remainSize_p1(%d)\n", + buffSize, blockSize_p1, blockCount_p1, remainSize_p1)); + } + + for (i = 0; i < blockCount_p1; i++) { +#ifdef CONFIG_USB_HCI + ret = rtw_writeN(padapter, (FW_8188F_START_ADDRESS + i * blockSize_p1), blockSize_p1, (bufferPtr + i * blockSize_p1)); +#else + ret = rtw_write32(padapter, (FW_8188F_START_ADDRESS + i * blockSize_p1), le32_to_cpu(*((u32 *)(bufferPtr + i * blockSize_p1)))); +#endif + if (ret == _FAIL) { + printk("====>%s %d i:%d\n", __func__, __LINE__, i); + goto exit; + } + } + +#ifdef CONFIG_PCI_HCI + p = (u8 *)((u32 *)(bufferPtr + blockCount_p1 * blockSize_p1)); + if (remainSize_p1) { + switch (remainSize_p1) { + case 0: + break; + case 3: + remainFW[2] = *(p + 2); + case 2: + remainFW[1] = *(p + 1); + case 1: + remainFW[0] = *(p); + ret = rtw_write32(padapter, (FW_8188F_START_ADDRESS + blockCount_p1 * blockSize_p1), + le32_to_cpu(*(u32 *)remainFW)); + } + return ret; + } +#endif + + /*3 Phase #2 */ + if (remainSize_p1) { + offset = blockCount_p1 * blockSize_p1; + + blockCount_p2 = remainSize_p1 / blockSize_p2; + remainSize_p2 = remainSize_p1 % blockSize_p2; + + if (blockCount_p2) { + RT_TRACE(_module_hal_init_c_, _drv_notice_, + ("_BlockWrite: [P2] buffSize_p2(%d) blockSize_p2(%d) blockCount_p2(%d) remainSize_p2(%d)\n", + (buffSize - offset), blockSize_p2 , blockCount_p2, remainSize_p2)); + } + +#ifdef CONFIG_USB_HCI + for (i = 0; i < blockCount_p2; i++) { + ret = rtw_writeN(padapter, (FW_8188F_START_ADDRESS + offset + i * blockSize_p2), blockSize_p2, (bufferPtr + offset + i * blockSize_p2)); + + if (ret == _FAIL) + goto exit; + } +#endif + } + + /*3 Phase #3 */ + if (remainSize_p2) { + offset = (blockCount_p1 * blockSize_p1) + (blockCount_p2 * blockSize_p2); + + blockCount_p3 = remainSize_p2 / blockSize_p3; + + RT_TRACE(_module_hal_init_c_, _drv_notice_, + ("_BlockWrite: [P3] buffSize_p3(%d) blockSize_p3(%d) blockCount_p3(%d)\n", + (buffSize - offset), blockSize_p3, blockCount_p3)); + + for (i = 0; i < blockCount_p3; i++) { + ret = rtw_write8(padapter, (FW_8188F_START_ADDRESS + offset + i), *(bufferPtr + offset + i)); + + if (ret == _FAIL) { + printk("====>%s %d i:%d\n", __func__, __LINE__, i); + goto exit; + } + } + } +exit: + return ret; +} + +static int +_PageWrite( + IN PADAPTER padapter, + IN u32 page, + IN PVOID buffer, + IN u32 size +) +{ + u8 value8; + u8 u8Page = (u8)(page & 0x07); + + value8 = (rtw_read8(padapter, REG_MCUFWDL + 2) & 0xF8) | u8Page; + rtw_write8(padapter, REG_MCUFWDL + 2, value8); + + return _BlockWrite(padapter, buffer, size); +} + +static VOID +_FillDummy( + u8 *pFwBuf, + u32 *pFwLen +) +{ + u32 FwLen = *pFwLen; + u8 remain = (u8)(FwLen % 4); + + remain = (remain == 0) ? 0 : (4 - remain); + + while (remain > 0) { + pFwBuf[FwLen] = 0; + FwLen++; + remain--; + } + + *pFwLen = FwLen; +} + +static int +_WriteFW( + IN PADAPTER padapter, + IN PVOID buffer, + IN u32 size +) +{ + /* Since we need dynamic decide method of dwonload fw, so we call this function to get chip version. */ + int ret = _SUCCESS; + u32 pageNums, remainSize; + u32 page, offset; + u8 *bufferPtr = (u8 *)buffer; + +#ifdef CONFIG_PCI_HCI + /* 20100120 Joseph: Add for 88CE normal chip. */ + /* Fill in zero to make firmware image to dword alignment. */ + _FillDummy(bufferPtr, &size); +#endif + + pageNums = size / MAX_DLFW_PAGE_SIZE; + /*RT_ASSERT((pageNums <= 4), ("Page numbers should not greater then 4\n")); */ + remainSize = size % MAX_DLFW_PAGE_SIZE; + + for (page = 0; page < pageNums; page++) { + offset = page * MAX_DLFW_PAGE_SIZE; + ret = _PageWrite(padapter, page, bufferPtr + offset, MAX_DLFW_PAGE_SIZE); + + if (ret == _FAIL) { + printk("====>%s %d\n", __func__, __LINE__); + goto exit; + } + } + if (remainSize) { + offset = pageNums * MAX_DLFW_PAGE_SIZE; + page = pageNums; + ret = _PageWrite(padapter, page, bufferPtr + offset, remainSize); + + if (ret == _FAIL) { + printk("====>%s %d\n", __func__, __LINE__); + goto exit; + } + } + RT_TRACE(_module_hal_init_c_, _drv_info_, ("_WriteFW Done- for Normal chip.\n")); + +exit: + return ret; +} + +void _8051Reset8188(PADAPTER padapter) +{ + u8 cpu_rst; + u8 io_rst; + +#if 0 + io_rst = rtw_read8(padapter, REG_RSV_CTRL); + rtw_write8(padapter, REG_RSV_CTRL, io_rst & (~BIT1)); +#endif + + /* Reset 8051(WLMCU) IO wrapper */ + /* 0x1c[8] = 0 */ + /* Suggested by Isaac@SD1 and Gimmy@SD1, coding by Lucas@20130624 */ + io_rst = rtw_read8(padapter, REG_RSV_CTRL + 1); + io_rst &= ~BIT(0); + rtw_write8(padapter, REG_RSV_CTRL + 1, io_rst); + + cpu_rst = rtw_read8(padapter, REG_SYS_FUNC_EN + 1); + cpu_rst &= ~BIT(2); + rtw_write8(padapter, REG_SYS_FUNC_EN + 1, cpu_rst); + +#if 0 + io_rst = rtw_read8(padapter, REG_RSV_CTRL); + rtw_write8(padapter, REG_RSV_CTRL, io_rst & (~BIT1)); +#endif + + /* Enable 8051 IO wrapper */ + /* 0x1c[8] = 1 */ + io_rst = rtw_read8(padapter, REG_RSV_CTRL + 1); + io_rst |= BIT(0); + rtw_write8(padapter, REG_RSV_CTRL + 1, io_rst); + + cpu_rst = rtw_read8(padapter, REG_SYS_FUNC_EN + 1); + cpu_rst |= BIT(2); + rtw_write8(padapter, REG_SYS_FUNC_EN + 1, cpu_rst); + + DBG_8192C("%s: Finish\n", __func__); +} + +static s32 polling_fwdl_chksum(_adapter *adapter, u32 min_cnt, u32 timeout_ms) +{ + s32 ret = _FAIL; + u32 value32; + u32 start = rtw_get_current_time(); + u32 cnt = 0; + + /* polling CheckSum report */ + do { + cnt++; + value32 = rtw_read32(adapter, REG_MCUFWDL); + if (value32 & FWDL_ChkSum_rpt || RTW_CANNOT_IO(adapter)) + break; + rtw_yield_os(); + } while (rtw_get_passing_time_ms(start) < timeout_ms || cnt < min_cnt); + + if (!(value32 & FWDL_ChkSum_rpt)) + goto exit; + + if (rtw_fwdl_test_trigger_chksum_fail()) + goto exit; + + ret = _SUCCESS; + +exit: + DBG_871X("%s: Checksum report %s! (%u, %dms), REG_MCUFWDL:0x%08x\n", __func__ + , (ret == _SUCCESS) ? "OK" : "Fail", cnt, rtw_get_passing_time_ms(start), value32); + + return ret; +} + +static s32 _FWFreeToGo(_adapter *adapter, u32 min_cnt, u32 timeout_ms) +{ + s32 ret = _FAIL; + u32 value32; + u32 start = rtw_get_current_time(); + u32 cnt = 0; + u32 value_to_check = 0; + u32 value_expected = (MCUFWDL_RDY | FWDL_ChkSum_rpt | WINTINI_RDY | RAM_DL_SEL); + + value32 = rtw_read32(adapter, REG_MCUFWDL); + value32 |= MCUFWDL_RDY; + value32 &= ~WINTINI_RDY; + rtw_write32(adapter, REG_MCUFWDL, value32); + + _8051Reset8188(adapter); + + /* polling for FW ready */ + do { + cnt++; + value32 = rtw_read32(adapter, REG_MCUFWDL); + value_to_check = value32 & value_expected; + if ((value_to_check == value_expected) || RTW_CANNOT_IO(adapter)) + break; + rtw_yield_os(); + } while (rtw_get_passing_time_ms(start) < timeout_ms || cnt < min_cnt); + + if (value_to_check != value_expected) + goto exit; + + if (rtw_fwdl_test_trigger_wintint_rdy_fail()) + goto exit; + + ret = _SUCCESS; + +exit: + DBG_871X("%s: Polling FW ready %s! (%u, %dms), REG_MCUFWDL:0x%08x\n", __func__ + , (ret == _SUCCESS) ? "OK" : "Fail", cnt, rtw_get_passing_time_ms(start), value32); + + return ret; +} + +#define IS_FW_81xxC(padapter) (((GET_HAL_DATA(padapter))->FirmwareSignature & 0xFFF0) == 0x88C0) + +void rtl8188f_FirmwareSelfReset(PADAPTER padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8 u1bTmp; + u8 Delay = 100; + + if (!(IS_FW_81xxC(padapter) && + ((pHalData->FirmwareVersion < 0x21) || + (pHalData->FirmwareVersion == 0x21 && + pHalData->FirmwareSubVersion < 0x01)))) { /* after 88C Fw v33.1 */ + /*0x1cf=0x20. Inform 8051 to reset. 2009.12.25. tynli_test */ + rtw_write8(padapter, REG_HMETFR + 3, 0x20); + + u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1); + while (u1bTmp & BIT2) { + Delay--; + if (Delay == 0) + break; + rtw_udelay_os(50); + u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1); + } + RT_TRACE(_module_hal_init_c_, _drv_notice_, ("-%s: 8051 reset success (%d)\n", __func__, Delay)); + + if (Delay == 0) { + RT_TRACE(_module_hal_init_c_, _drv_notice_, ("%s: Force 8051 reset!!!\n", __func__)); + /*force firmware reset */ + u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1); + rtw_write8(padapter, REG_SYS_FUNC_EN + 1, u1bTmp & (~BIT2)); + } + } +} + +#ifdef CONFIG_FILE_FWIMG +extern char *rtw_fw_file_path; +extern char *rtw_fw_wow_file_path; +#ifdef CONFIG_MP_INCLUDED +extern char *rtw_fw_mp_bt_file_path; +#endif /* CONFIG_MP_INCLUDED */ +u8 FwBuffer[FW_8188F_SIZE]; +#endif /* CONFIG_FILE_FWIMG */ + +#ifdef CONFIG_MP_INCLUDED +int _WriteBTFWtoTxPktBuf8188F( + IN PADAPTER Adapter, + IN PVOID buffer, + IN u4Byte FwBufLen, + IN u1Byte times +) +{ + int rtStatus = _SUCCESS; + /*u4Byte value32; */ + /*u1Byte numHQ, numLQ, numPubQ;//, txpktbuf_bndy; */ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + /*PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); */ + u1Byte BcnValidReg; + u1Byte count = 0, DLBcnCount = 0; + pu1Byte FwbufferPtr = (pu1Byte)buffer; + /*PRT_TCB pTcb, ptempTcb; */ + /*PRT_TX_LOCAL_BUFFER pBuf; */ + BOOLEAN bRecover = _FALSE; + pu1Byte ReservedPagePacket = NULL; + pu1Byte pGenBufReservedPagePacket = NULL; + u4Byte TotalPktLen, txpktbuf_bndy; + /*u1Byte tmpReg422; */ + /*u1Byte u1bTmp; */ + u8 *pframe; + struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + u8 txdesc_offset = TXDESC_OFFSET; + u8 val8; +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + u8 u1bTmp; +#endif + +#if 1/*(DEV_BUS_TYPE == RT_PCI_INTERFACE) */ + TotalPktLen = FwBufLen; +#else + TotalPktLen = FwBufLen + pHalData->HWDescHeadLength; +#endif + + if ((TotalPktLen + TXDESC_OFFSET) > MAX_CMDBUF_SZ) { + DBG_871X(" WARNING %s => Total packet len = %d > MAX_CMDBUF_SZ:%d\n" + , __func__, (TotalPktLen + TXDESC_OFFSET), MAX_CMDBUF_SZ); + return _FAIL; + } + + pGenBufReservedPagePacket = rtw_zmalloc(TotalPktLen);/*GetGenTempBuffer (Adapter, TotalPktLen); */ + if (!pGenBufReservedPagePacket) + return _FAIL; + + ReservedPagePacket = (u1Byte *)pGenBufReservedPagePacket; + + _rtw_memset(ReservedPagePacket, 0, TotalPktLen); + +#if 1/*(DEV_BUS_TYPE == RT_PCI_INTERFACE) */ + _rtw_memcpy(ReservedPagePacket, FwbufferPtr, FwBufLen); + +#else + PlatformMoveMemory(ReservedPagePacket + Adapter->HWDescHeadLength , FwbufferPtr, FwBufLen); +#endif + + /*--------------------------------------------------------- */ + /* 1. Pause BCN */ + /*--------------------------------------------------------- */ + /*Set REG_CR bit 8. DMA beacon by SW. */ +#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) + u1bTmp = PlatformEFIORead1Byte(Adapter, REG_CR + 1); + PlatformEFIOWrite1Byte(Adapter, REG_CR + 1, (u1bTmp | BIT0)); +#else + /* Remove for temparaily because of the code on v2002 is not sync to MERGE_TMEP for USB/SDIO. */ + /* De not remove this part on MERGE_TEMP. by tynli. */ + /*pHalData->RegCR_1 |= (BIT0); */ + /*PlatformEFIOWrite1Byte(Adapter, REG_CR+1, pHalData->RegCR_1); */ +#endif + + /* Disable Hw protection for a time which revserd for Hw sending beacon. */ + /* Fix download reserved page packet fail that access collision with the protection time. */ + /* 2010.05.11. Added by tynli. */ + val8 = rtw_read8(Adapter, REG_BCN_CTRL); + val8 &= ~EN_BCN_FUNCTION; + val8 |= DIS_TSF_UDT; + rtw_write8(Adapter, REG_BCN_CTRL, val8); + +#if 0/*(DEV_BUS_TYPE == RT_PCI_INTERFACE) */ + tmpReg422 = PlatformEFIORead1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2); + if (tmpReg422 & BIT6) + bRecover = TRUE; + PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2, tmpReg422 & (~BIT6)); +#else + /* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. */ + if (pHalData->RegFwHwTxQCtrl & BIT(6)) + bRecover = _TRUE; + PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2, (pHalData->RegFwHwTxQCtrl & (~BIT(6)))); + pHalData->RegFwHwTxQCtrl &= (~ BIT(6)); +#endif + + /*--------------------------------------------------------- */ + /* 2. Adjust LLT table to an even boundary. */ + /*--------------------------------------------------------- */ +#if 0/*(DEV_BUS_TYPE == RT_SDIO_INTERFACE) */ + txpktbuf_bndy = 10; /* rsvd page start address should be an even value. */ + rtStatus = InitLLTTable8188FS(Adapter, txpktbuf_bndy); + if (RT_STATUS_SUCCESS != rtStatus) { + DBG_8192C("_CheckWLANFwPatchBTFwReady_8188F(): Failed to init LLT!\n"); + return RT_STATUS_FAILURE; + } + + /* Init Tx boundary. */ + PlatformEFIOWrite1Byte(Adapter, REG_DWBCN0_CTRL_8188F + 1, (u1Byte)txpktbuf_bndy); +#endif + + + /*--------------------------------------------------------- */ + /* 3. Write Fw to Tx packet buffer by reseverd page. */ + /*--------------------------------------------------------- */ + do { + /* download rsvd page. */ + /* Clear beacon valid check bit. */ + BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_TDECTRL + 2); + PlatformEFIOWrite1Byte(Adapter, REG_TDECTRL + 2, BcnValidReg & (~BIT(0))); + + /*BT patch is big, we should set 0x209 < 0x40 suggested from Gimmy */ + RT_TRACE(_module_mp_, _drv_info_, ("0x209:%x\n", + PlatformEFIORead1Byte(Adapter, REG_TDECTRL + 1))); /*209 < 0x40 */ + + PlatformEFIOWrite1Byte(Adapter, REG_TDECTRL + 1, (0x90 - 0x20 * (times - 1))); + DBG_871X("0x209:0x%x\n", PlatformEFIORead1Byte(Adapter, REG_TDECTRL + 1)); + RT_TRACE(_module_mp_, _drv_info_, ("0x209:%x\n", + PlatformEFIORead1Byte(Adapter, REG_TDECTRL + 1))); + +#if 0 + /* Acquice TX spin lock before GetFwBuf and send the packet to prevent system deadlock. */ + /* Advertised by Roger. Added by tynli. 2010.02.22. */ + PlatformAcquireSpinLock(Adapter, RT_TX_SPINLOCK); + if (MgntGetFWBuffer(Adapter, &pTcb, &pBuf)) { + PlatformMoveMemory(pBuf->Buffer.VirtualAddress, ReservedPagePacket, TotalPktLen); + CmdSendPacket(Adapter, pTcb, pBuf, TotalPktLen, DESC_PACKET_TYPE_NORMAL, FALSE); + } else + dbgdump("SetFwRsvdPagePkt(): MgntGetFWBuffer FAIL!!!!!!!!.\n"); + PlatformReleaseSpinLock(Adapter, RT_TX_SPINLOCK); +#else + /*--------------------------------------------------------- + tx reserved_page_packet + ----------------------------------------------------------*/ + pmgntframe = rtw_alloc_cmdxmitframe(pxmitpriv); + if (pmgntframe == NULL) { + rtStatus = _FAIL; + goto exit; + } + /*update attribute */ + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(Adapter, pattrib); + + pattrib->qsel = QSLT_BEACON; + pattrib->pktlen = pattrib->last_txcmdsz = FwBufLen; + + /*_rtw_memset(pmgntframe->buf_addr, 0, TotalPktLen+txdesc_size); */ + /*pmgntframe->buf_addr = ReservedPagePacket; */ + + _rtw_memcpy((u8 *)(pmgntframe->buf_addr + txdesc_offset), ReservedPagePacket, FwBufLen); + DBG_871X("[%d]===>TotalPktLen + TXDESC_OFFSET TotalPacketLen:%d\n", DLBcnCount, (FwBufLen + txdesc_offset)); + +#ifdef CONFIG_PCI_HCI + dump_mgntframe(Adapter, pmgntframe); +#else + dump_mgntframe_and_wait(Adapter, pmgntframe, 100); +#endif + +#endif +#if 1 + /* check rsvd page download OK. */ + BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_TDECTRL + 2); + while (!(BcnValidReg & BIT(0)) && count < 200) { + count++; + /*PlatformSleepUs(10); */ + rtw_msleep_os(1); + BcnValidReg = PlatformEFIORead1Byte(Adapter, REG_TDECTRL + 2); + RT_TRACE(_module_mp_, _drv_notice_, ("Poll 0x20A = %x\n", BcnValidReg)); + } + DLBcnCount++; + /*DBG_871X("##0x208:%08x,0x210=%08x\n",PlatformEFIORead4Byte(Adapter, REG_TDECTRL),PlatformEFIORead4Byte(Adapter, 0x210)); */ + + PlatformEFIOWrite1Byte(Adapter, REG_TDECTRL + 2, BcnValidReg); + + } while ((!(BcnValidReg & BIT(0))) && DLBcnCount < 5); + + +#endif + if (DLBcnCount >= 5) { + DBG_871X(" check rsvd page download OK DLBcnCount =%d\n", DLBcnCount); + rtStatus = _FAIL; + goto exit; + } + + if (!(BcnValidReg & BIT(0))) { + DBG_871X("_WriteFWtoTxPktBuf(): 1 Download RSVD page failed!\n"); + rtStatus = _FAIL; + goto exit; + } + + /*--------------------------------------------------------- */ + /* 4. Set Tx boundary to the initial value */ + /*--------------------------------------------------------- */ + + + /*--------------------------------------------------------- */ + /* 5. Reset beacon setting to the initial value. */ + /* After _CheckWLANFwPatchBTFwReady(). */ + /*--------------------------------------------------------- */ + +exit: + + if (pGenBufReservedPagePacket) { + DBG_871X("_WriteBTFWtoTxPktBuf8188F => rtw_mfree pGenBufReservedPagePacket!\n"); + rtw_mfree((u8 *)pGenBufReservedPagePacket, TotalPktLen); + } + return rtStatus; +} + + + +/* */ +/* Description: Determine the contents of H2C BT_FW_PATCH Command sent to FW. */ +/* 2011.10.20 by tynli */ +/* */ +void +SetFwBTFwPatchCmd( + IN PADAPTER Adapter, + IN u16 FwSize +) +{ + u8 u1BTFwPatchParm[H2C_BT_FW_PATCH_LEN] = {0}; + u8 addr0 = 0; + u8 addr1 = 0xa0; + u8 addr2 = 0x10; + u8 addr3 = 0x80; + + RT_TRACE(_module_mp_, _drv_notice_, ("SetFwBTFwPatchCmd(): FwSize = %d\n", FwSize)); + + SET_8188F_H2CCMD_BT_FW_PATCH_SIZE(u1BTFwPatchParm, FwSize); + SET_8188F_H2CCMD_BT_FW_PATCH_ADDR0(u1BTFwPatchParm, addr0); + SET_8188F_H2CCMD_BT_FW_PATCH_ADDR1(u1BTFwPatchParm, addr1); + SET_8188F_H2CCMD_BT_FW_PATCH_ADDR2(u1BTFwPatchParm, addr2); + SET_8188F_H2CCMD_BT_FW_PATCH_ADDR3(u1BTFwPatchParm, addr3); + + FillH2CCmd8188F(Adapter, H2C_8188F_BT_FW_PATCH, H2C_BT_FW_PATCH_LEN, u1BTFwPatchParm); + + RT_TRACE(_module_mp_, _drv_notice_, ("<----SetFwBTFwPatchCmd(): FwSize = %d\n", FwSize)); +} + +void +SetFwBTPwrCmd( + IN PADAPTER Adapter, + IN u1Byte PwrIdx +) +{ + u1Byte u1BTPwrIdxParm[H2C_FORCE_BT_TXPWR_LEN] = {0}; + + RT_TRACE(_module_mp_, _drv_info_, ("SetFwBTPwrCmd(): idx = %d\n", PwrIdx)); + SET_8188F_H2CCMD_BT_PWR_IDX(u1BTPwrIdxParm, PwrIdx); + + RT_TRACE(_module_mp_, _drv_info_, ("SetFwBTPwrCmd(): %x %x %x\n", + u1BTPwrIdxParm[0], u1BTPwrIdxParm[1], u1BTPwrIdxParm[2])); + + FillH2CCmd8188F(Adapter, H2C_8188F_FORCE_BT_TXPWR, H2C_FORCE_BT_TXPWR_LEN, u1BTPwrIdxParm); +} + +/* */ +/* Description: WLAN Fw will write BT Fw to BT XRAM and signal driver. */ +/* */ +/* 2011.10.20. by tynli. */ +/* */ +int +_CheckWLANFwPatchBTFwReady( + IN PADAPTER Adapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u4Byte count = 0; + u1Byte u1bTmp; + int ret = _FAIL; + + /*--------------------------------------------------------- */ + /* Check if BT FW patch procedure is ready. */ + /*--------------------------------------------------------- */ + do { + u1bTmp = PlatformEFIORead1Byte(Adapter, REG_HMEBOX_DBG_0_8188F); + if ((u1bTmp & BIT6) || (u1bTmp & BIT7)) { + ret = _SUCCESS; + break; + } + + count++; + RT_TRACE(_module_mp_, _drv_info_, ("0x88=%x, wait for 50 ms (%d) times.\n", + u1bTmp, count)); + rtw_msleep_os(50); /* 50ms */ + } while (!((u1bTmp & BIT6) || (u1bTmp & BIT7)) && count < 50); + + RT_TRACE(_module_mp_, _drv_notice_, + ("_CheckWLANFwPatchBTFwReady(): Polling ready bit 0x88[7] for %d times.\n", count)); + + if (count >= 50) { + RT_TRACE(_module_mp_, _drv_notice_, + ("_CheckWLANFwPatchBTFwReady(): Polling ready bit 0x88[7] FAIL!!\n")); + } + + /*--------------------------------------------------------- */ + /* Reset beacon setting to the initial value. */ + /*--------------------------------------------------------- */ +#if 0/*(DEV_BUS_TYPE == RT_PCI_INTERFACE) */ + if (LLT_table_init(Adapter, FALSE, 0) == RT_STATUS_FAILURE) { + dbgdump("Init self define for BT Fw patch LLT table fail.\n"); + /*return RT_STATUS_FAILURE; */ + } +#endif + u1bTmp = rtw_read8(Adapter, REG_BCN_CTRL); + u1bTmp |= EN_BCN_FUNCTION; + u1bTmp &= ~DIS_TSF_UDT; + rtw_write8(Adapter, REG_BCN_CTRL, u1bTmp); + + /* To make sure that if there exists an adapter which would like to send beacon. */ + /* If exists, the origianl value of 0x422[6] will be 1, we should check this to */ + /* prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */ + /* the beacon cannot be sent by HW. */ + /* 2010.06.23. Added by tynli. */ +#if 0/*(DEV_BUS_TYPE == RT_PCI_INTERFACE) */ + u1bTmp = PlatformEFIORead1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2); + PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2, (u1bTmp | BIT6)); +#else + PlatformEFIOWrite1Byte(Adapter, REG_FWHW_TXQ_CTRL + 2, (pHalData->RegFwHwTxQCtrl | BIT(6))); + pHalData->RegFwHwTxQCtrl |= BIT(6); +#endif + + /* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */ + u1bTmp = PlatformEFIORead1Byte(Adapter, REG_CR_8188F + 1); + PlatformEFIOWrite1Byte(Adapter, REG_CR_8188F + 1, (u1bTmp & (~BIT0))); + + return ret; +} + +int ReservedPage_Compare(PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware, u32 BTPatchSize) +{ + u8 temp, ret, lastBTsz; + u32 u1bTmp = 0, address_start = 0, count = 0, i = 0; + u8 *myBTFwBuffer = NULL; + + myBTFwBuffer = rtw_zmalloc(BTPatchSize); + if (myBTFwBuffer == NULL) { + DBG_871X("%s can't be executed due to the failed malloc.\n", __func__); + Adapter->mppriv.bTxBufCkFail = _TRUE; + return _FALSE; + } + + temp = rtw_read8(Adapter, 0x209); + + address_start = (temp * 128) / 8; + + rtw_write32(Adapter, 0x140, 0x00000000); + rtw_write32(Adapter, 0x144, 0x00000000); + rtw_write32(Adapter, 0x148, 0x00000000); + + rtw_write8(Adapter, 0x106, 0x69); + + for (i = 0; i < (BTPatchSize / 8); i++) { + rtw_write32(Adapter, 0x140, address_start + 5 + i); + + /*polling until reg 0x140[23]=1; */ + do { + u1bTmp = rtw_read32(Adapter, 0x140); + if (u1bTmp & BIT(23)) { + ret = _SUCCESS; + break; + } + count++; + DBG_871X("0x140=%x, wait for 10 ms (%d) times.\n", u1bTmp, count); + rtw_msleep_os(10); /* 10ms */ + } while (!(u1bTmp & BIT(23)) && count < 50); + + myBTFwBuffer[i * 8 + 0] = rtw_read8(Adapter, 0x144); + myBTFwBuffer[i * 8 + 1] = rtw_read8(Adapter, 0x145); + myBTFwBuffer[i * 8 + 2] = rtw_read8(Adapter, 0x146); + myBTFwBuffer[i * 8 + 3] = rtw_read8(Adapter, 0x147); + myBTFwBuffer[i * 8 + 4] = rtw_read8(Adapter, 0x148); + myBTFwBuffer[i * 8 + 5] = rtw_read8(Adapter, 0x149); + myBTFwBuffer[i * 8 + 6] = rtw_read8(Adapter, 0x14a); + myBTFwBuffer[i * 8 + 7] = rtw_read8(Adapter, 0x14b); + } + + rtw_write32(Adapter, 0x140, address_start + 5 + BTPatchSize / 8); + + lastBTsz = BTPatchSize % 8; + + /*polling until reg 0x140[23]=1; */ + u1bTmp = 0; + count = 0; + do { + u1bTmp = rtw_read32(Adapter, 0x140); + if (u1bTmp & BIT(23)) { + ret = _SUCCESS; + break; + } + count++; + DBG_871X("0x140=%x, wait for 10 ms (%d) times.\n", u1bTmp, count); + rtw_msleep_os(10); /* 10ms */ + } while (!(u1bTmp & BIT(23)) && count < 50); + + for (i = 0; i < lastBTsz; i++) + myBTFwBuffer[(BTPatchSize / 8) * 8 + i] = rtw_read8(Adapter, (0x144 + i)); + + + for (i = 0; i < BTPatchSize; i++) { + if (myBTFwBuffer[i] != pFirmware->szFwBuffer[i]) { + DBG_871X(" In direct myBTFwBuffer[%d]=%x , pFirmware->szFwBuffer=%x\n", i, myBTFwBuffer[i], pFirmware->szFwBuffer[i]); + Adapter->mppriv.bTxBufCkFail = _TRUE; + break; + } + } + + if (myBTFwBuffer != NULL) + rtw_mfree(myBTFwBuffer, BTPatchSize); + + return _TRUE; +} + +#ifdef CONFIG_BT_COEXIST +/* As the size of bt firmware is more than 16k which is too big for some platforms, we divide it + * into four parts to transfer. The last parameter of _WriteBTFWtoTxPktBuf8188F is used to indicate + * the location of every part. We call the first 4096 byte of bt firmware as part 1, the second 4096 + * part as part 2, the third 4096 part as part 3, the remain as part 4. First we transform the part + * 4 and set the register 0x209 to 0x90, then the 32 bytes description are added to the head of part + * 4, and those bytes are putted at the location 0x90. Second we transform the part 3 and set the + * register 0x209 to 0x70. The 32 bytes description and part 3(4196 bytes) are putted at the location + * 0x70. It can contain 4196 bytes between 0x70 and 0x90. So the last 32 bytes os part 3 will cover the + * 32 bytes description of part4. Using this method, we can put the whole bt firmware to 0x30 and only + * has 32 bytes descrption at the head of part 1. +*/ +s32 FirmwareDownloadBT(PADAPTER padapter, PRT_MP_FIRMWARE pFirmware) +{ + s32 rtStatus; + u8 *pBTFirmwareBuf; + u32 BTFirmwareLen; + u8 download_time; + s8 i; + + + rtStatus = _SUCCESS; + pBTFirmwareBuf = NULL; + BTFirmwareLen = 0; + + /* */ + /* Patch BT Fw. Download BT RAM code to Tx packet buffer. */ + /* */ + if (padapter->bBTFWReady) { + DBG_8192C("%s: BT Firmware is ready!!\n", __func__); + return _FAIL; + } + +#ifdef CONFIG_FILE_FWIMG + if (rtw_is_file_readable(rtw_fw_mp_bt_file_path) == _TRUE) { + DBG_8192C("%s: acquire MP BT FW from file:%s\n", __func__, rtw_fw_mp_bt_file_path); + + rtStatus = rtw_retrieve_from_file(rtw_fw_mp_bt_file_path, FwBuffer, FW_8188F_SIZE); + BTFirmwareLen = rtStatus >= 0 ? rtStatus : 0; + pBTFirmwareBuf = FwBuffer; + } else +#endif /* CONFIG_FILE_FWIMG */ + { +#ifdef CONFIG_EMBEDDED_FWIMG + DBG_8192C("%s: Download MP BT FW from header\n", __func__); + + pBTFirmwareBuf = (u8 *)Rtl8188FFwBTImgArray; + BTFirmwareLen = Rtl8188FFwBTImgArrayLength; + pFirmware->szFwBuffer = pBTFirmwareBuf; + pFirmware->ulFwLength = BTFirmwareLen; +#endif /* CONFIG_EMBEDDED_FWIMG */ + } + + DBG_8192C("%s: MP BT Firmware size=%d\n", __func__, BTFirmwareLen); + + /* for h2c cam here should be set to true */ + padapter->bFWReady = _TRUE; + + download_time = (BTFirmwareLen + 4095) / 4096; + DBG_8192C("%s: download_time is %d\n", __func__, download_time); + + /* Download BT patch Fw. */ + for (i = (download_time - 1); i >= 0; i--) { + if (i == (download_time - 1)) { + rtStatus = _WriteBTFWtoTxPktBuf8188F(padapter, pBTFirmwareBuf + (4096 * i), (BTFirmwareLen - (4096 * i)), 1); + DBG_8192C("%s: start %d, len %d, time 1\n", __func__, 4096 * i, BTFirmwareLen - (4096 * i)); + } else { + rtStatus = _WriteBTFWtoTxPktBuf8188F(padapter, pBTFirmwareBuf + (4096 * i), 4096, (download_time - i)); + DBG_8192C("%s: start %d, len 4096, time %d\n", __func__, 4096 * i, download_time - i); + } + + if (rtStatus != _SUCCESS) { + DBG_8192C("%s: BT Firmware download to Tx packet buffer fail!\n", __func__); + padapter->bBTFWReady = _FALSE; + return rtStatus; + } + } + + ReservedPage_Compare(padapter, pFirmware, BTFirmwareLen); + + padapter->bBTFWReady = _TRUE; + SetFwBTFwPatchCmd(padapter, (u16)BTFirmwareLen); + rtStatus = _CheckWLANFwPatchBTFwReady(padapter); + + DBG_8192C("<===%s: return %s!\n", __func__, rtStatus == _SUCCESS ? "SUCCESS" : "FAIL"); + + return rtStatus; +} +#endif /* CONFIG_BT_COEXIST */ +#endif /* CONFIG_MP_INCLUDED */ + +#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) +void rtl8188f_cal_txdesc_chksum(struct tx_desc *ptxdesc) +{ + u16 *usPtr = (u16 *)ptxdesc; + u32 count; + u32 index; + u16 checksum = 0; + + + /* Clear first */ + ptxdesc->txdw7 &= cpu_to_le32(0xffff0000); + + /* checksume is always calculated by first 32 bytes, */ + /* and it doesn't depend on TX DESC length. */ + /* Thomas,Lucas@SD4,20130515 */ + count = 16; + + for (index = 0; index < count; index++) + checksum ^= le16_to_cpu(*(usPtr + index)); + + ptxdesc->txdw7 |= cpu_to_le32(checksum & 0x0000ffff); +} +#endif + +#if 0 /* FW tx packet write */ +u8 send_fw_packet(PADAPTER padapter, u8 *pRam_code, u32 length) +{ + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct xmit_buf xmit_buf_tmp; + struct submit_ctx sctx_tmp; + u8 *pTx_data_buffer = NULL; + u8 *pTmp_buffer = NULL; + u32 modify_ram_size; + u32 tmp_size, tmp_value; + u8 value8; + u32 i, counter; + u8 bRet; + u32 dwDataLength, writeLength; + + /* Due to SDIO can not send 32K packet */ + if (FW_DOWNLOAD_SIZE_8188F == length) + length--; + + modify_ram_size = length << 2; + pTx_data_buffer = rtw_zmalloc(modify_ram_size); + + if (NULL == pTx_data_buffer) { + DBG_871X("Allocate buffer fail!!\n"); + return _FALSE; + } + + _rtw_memset(pTx_data_buffer, 0, modify_ram_size); + + /* Transfer to new format */ + tmp_size = length >> 1; + for (i = 0; i <= tmp_size; i++) { + *(pTx_data_buffer + i * 8) = *(pRam_code + i * 2); + *(pTx_data_buffer + i * 8 + 1) = *(pRam_code + i * 2 + 1); + } + + /* Gen TX_DESC */ + _rtw_memset(pTx_data_buffer, 0, TXDESC_SIZE); + pTmp_buffer = pTx_data_buffer; +#if 0 + pTmp_buffer->qsel = BcnQsel; + pTmp_buffer->txpktsize = modify_ram_size - TXDESC_SIZE; + pTmp_buffer->offset = TXDESC_SIZE; +#else + SET_TX_DESC_QUEUE_SEL_8188F(pTmp_buffer, QSLT_BEACON); + SET_TX_DESC_PKT_SIZE_8188F(pTmp_buffer, modify_ram_size - TXDESC_SIZE); + SET_TX_DESC_OFFSET_8188F(pTmp_buffer, TXDESC_SIZE); +#endif + rtl8188f_cal_txdesc_chksum((struct tx_desc *)pTmp_buffer); + + + /* Send packet */ +#if 0 + dwDataLength = modify_ram_size; + overlap.Offset = 0; + overlap.OffsetHigh = 0; + overlap.hEvent = CreateEvent(NULL, FALSE, FALSE, NULL); + bRet = WriteFile(HalVari.hFile_Queue[TX_BCNQ]->handle, pTx_data_buffer, dwDataLength, &writeLength, &overlap); + if (WaitForSingleObject(overlap.hEvent, INFINITE) == WAIT_OBJECT_0) { + + GetOverlappedResult(HalVari.hFile_Queue[TX_BCNQ]->handle, &overlap, &writeLength, FALSE); + if (writeLength != dwDataLength) { + TCHAR editbuf[100]; + + sprintf(editbuf, "DL FW Length Err: Write length error:bRet %d writeLength %ld dwDataLength %ld, Error Code:%ld", bRet, writeLength, dwDataLength, GetLastError()); + AfxMessageBox(editbuf, MB_OK | MB_ICONERROR); + return FALSE; + } + } + CloseHandle(overlap.hEvent); +#else + xmit_buf_tmp.pdata = pTx_data_buffer; + xmit_buf_tmp.len = modify_ram_size; + rtw_sctx_init(&sctx_tmp, 10); + xmit_buf_tmp.sctx = &sctx_tmp; + if (rtw_write_port(padapter, pdvobjpriv->Queue2Pipe[BCN_QUEUE_INX], xmit_buf_tmp.len, (u8 *)&xmit_buf_tmp) == _FAIL) { + DBG_871X("rtw_write_port fail\n"); + return _FAIL; + } +#endif + + /* check if DMA is OK */ + counter = 100; + do { + if (0 == counter) { + DBG_871X("DMA time out!!\n"); + return _FALSE; + } + value8 = rtw_read8(padapter, REG_DWBCN0_CTRL_8188F + 2); + counter--; + } while (0 == (value8 & BIT(0))); + + rtw_write8(padapter, REG_DWBCN0_CTRL_8188F + 2, value8); + + /* Modify ram code by IO method */ + tmp_value = rtw_read8(padapter, REG_MCUFWDL + 1); + /* Disable DMA */ + rtw_write8(padapter, REG_MCUFWDL + 1, (u8)tmp_value & ~(BIT(5))); + tmp_value = (tmp_value >> 6) << 1; + /* Set page start address */ + rtw_write8(padapter, REG_MCUFWDL + 2, (rtw_read8(padapter, REG_MCUFWDL + 2) & 0xF8) | tmp_value); + tmp_size = TXDESC_SIZE >> 2; /* 10bytes */ +#if 0 + IO_Func.WriteRegister(0x1000, (u2Byte)tmp_size, pRam_code); +#else + _BlockWrite(padapter, pRam_code, tmp_size); +#endif + + if (pTmp_buffer != NULL) + rtw_mfree((u8 *)pTmp_buffer, modify_ram_size); + + return _TRUE; +} +#endif + +/* */ +/* Description: */ +/* Download 8192C firmware code. */ +/* */ +/* */ + +MODULE_FIRMWARE("rtlwifi/rtl8188fufw.bin"); + +s32 rtl8188f_FirmwareDownload(PADAPTER padapter, BOOLEAN bUsedqFw) +{ + s32 rtStatus = _SUCCESS; + u8 write_fw = 0; + u32 fwdl_start_time; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + u8 *FwImage; + u32 FwImageLen; + u8 *pucMappedFile = NULL; + PRT_8188F_FIRMWARE_HDR pFwHdr = NULL; + u8 *pFirmwareBuf; + u32 FirmwareLen; + char *fw_name = "rtlwifi/rtl8188fufw.bin"; + const struct firmware *fw; + u8 value8; + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + + RT_TRACE(_module_hal_init_c_, _drv_info_, ("+%s\n", __func__)); + + { + u8 tmp_ps = 0, tmp_rf = 0; + + tmp_ps = rtw_read8(padapter, 0xa3); + tmp_ps &= 0xf8; + tmp_ps |= 0x02; + /*1. write 0xA3[:2:0] = 3b'010 */ + rtw_write8(padapter, 0xa3, tmp_ps); + /*2. read power_state = 0xA0[1:0] */ + tmp_ps = rtw_read8(padapter, 0xa0); + tmp_ps &= 0x03; + if (tmp_ps != 0x01) { + DBG_871X(FUNC_ADPT_FMT" tmp_ps=%x\n", FUNC_ADPT_ARG(padapter), tmp_ps); + pdbgpriv->dbg_downloadfw_pwr_state_cnt++; + } + } + +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_PreLoadFirmware(padapter); +#endif + + dev_info(&psdpriv->pusbdev->dev, "request firmware %s\n",fw_name); + if (request_firmware(&fw, fw_name, &psdpriv->pusbdev->dev)) { + dev_err(&psdpriv->pusbdev->dev, "Firmware %s not available\n", fw_name); + goto exit; + } + + dev_info(&psdpriv->pusbdev->dev, "request firmware %s loaded\n",fw_name); + + + if (fw->size > FW_8188F_SIZE) { + rtStatus = _FAIL; + DBG_871X_LEVEL(_drv_emerg_, "Firmware size:%u exceed %u\n", (int) fw->size, FW_8188F_SIZE); + goto exit; + } + + pFirmwareBuf = (u8 *) fw->data; + FirmwareLen = fw->size; + + /* To Check Fw header. Added by tynli. 2009.12.04. */ + pFwHdr = (PRT_8188F_FIRMWARE_HDR)pFirmwareBuf; + + pHalData->FirmwareVersion = le16_to_cpu(pFwHdr->Version); + pHalData->FirmwareSubVersion = le16_to_cpu(pFwHdr->Subversion); + pHalData->FirmwareSignature = le16_to_cpu(pFwHdr->Signature); + + DBG_871X("%s: fw_ver=%x fw_subver=%04x sig=0x%x, Month=%02x, Date=%02x, Hour=%02x, Minute=%02x\n", + __func__, pHalData->FirmwareVersion, pHalData->FirmwareSubVersion, pHalData->FirmwareSignature + , pFwHdr->Month, pFwHdr->Date, pFwHdr->Hour, pFwHdr->Minute); + + if (IS_FW_HEADER_EXIST_8188F(pFwHdr)) { + DBG_871X("%s(): Shift for fw header!\n", __func__); + /* Shift 32 bytes for FW header */ + pFirmwareBuf = pFirmwareBuf + 32; + FirmwareLen = FirmwareLen - 32; + } + + fwdl_start_time = rtw_get_current_time(); + +#if 1 + DBG_871X("%s by IO write!\n", __func__); + + /* + * Suggested by Filen. If 8051 is running in RAM code, driver should inform Fw to reset by itself, + * or it will cause download Fw fail. 2010.02.01. by tynli. + */ + if (rtw_read8(padapter, REG_MCUFWDL) & RAM_DL_SEL) { + rtw_write8(padapter, REG_MCUFWDL, 0x00); + _8051Reset8188(padapter); + } + + _FWDownloadEnable(padapter, _TRUE); + + while (!RTW_CANNOT_IO(padapter) + && (write_fw++ < 3 || rtw_get_passing_time_ms(fwdl_start_time) < 500)) { + /* reset FWDL chksum */ + rtw_write8(padapter, REG_MCUFWDL, rtw_read8(padapter, REG_MCUFWDL) | FWDL_ChkSum_rpt); + + rtStatus = _WriteFW(padapter, pFirmwareBuf, FirmwareLen); + if (rtStatus != _SUCCESS) + continue; + + rtStatus = polling_fwdl_chksum(padapter, 5, 50); + if (rtStatus == _SUCCESS) + break; + } +#else + DBG_871X("%s by Tx pkt write!\n", __func__); + + if ((rtw_read8(padapter, REG_MCUFWDL) & MCUFWDL_RDY) == 0) { + /* DLFW use HIQ only */ + value32 = 0xFF | BIT(31); + rtw_write32(padapter, REG_RQPN, value32); + + /* Set beacon boundary to TXFIFO header */ + rtw_write8(padapter, REG_BCNQ_BDNY, 0); + rtw_write16(padapter, REG_DWBCN0_CTRL_8188F + 1, BIT(8)); + + /* SDIO need read this register before send packet */ + rtw_read32(padapter, 0x10250020); + + _FWDownloadEnable(padapter, _TRUE); + + /* Get original check sum */ + new_chk_sum = *(pFirmwareBuf + FirmwareLen - 2) | ((u16) *(pFirmwareBuf + FirmwareLen - 1) << 8); + + /* Send ram code flow */ + dma_iram_sel = 0; + mem_offset = 0; + pkt_size_tmp = FirmwareLen; + while (0 != pkt_size_tmp) { + if (pkt_size_tmp >= FW_DOWNLOAD_SIZE_8188F) { + send_pkt_size = FW_DOWNLOAD_SIZE_8188F; + /* Modify check sum value */ + new_chk_sum = (u16)(new_chk_sum ^ (((send_pkt_size - 1) << 2) - TXDESC_SIZE)); + } else { + send_pkt_size = pkt_size_tmp; + new_chk_sum = (u16)(new_chk_sum ^ ((send_pkt_size << 2) - TXDESC_SIZE)); + + } + + if (send_pkt_size == pkt_size_tmp) { + /* last partition packet, write new check sum to ram code file */ + *(pFirmwareBuf + FirmwareLen - 2) = new_chk_sum & 0xFF; + *(pFirmwareBuf + FirmwareLen - 1) = (new_chk_sum & 0xFF00) >> 8; + } + + /* IRAM select */ + rtw_write8(padapter, REG_MCUFWDL + 1, (rtw_read8(padapter, REG_MCUFWDL + 1) & 0x3F) | (dma_iram_sel << 6)); + /* Enable DMA */ + rtw_write8(padapter, REG_MCUFWDL + 1, rtw_read8(padapter, REG_MCUFWDL + 1) | BIT(5)); + + if (_FALSE == send_fw_packet(padapter, pFirmwareBuf + mem_offset, send_pkt_size)) { + DBG_871X("%s: Send FW fail !\n", __func__); + rtStatus = _FAIL; + goto DLFW_FAIL; + } + + dma_iram_sel++; + mem_offset += send_pkt_size; + pkt_size_tmp -= send_pkt_size; + } + } else { + DBG_871X("%s: Download FW fail since MCUFWDL_RDY is not set!\n", __func__); + rtStatus = _FAIL; + goto DLFW_FAIL; + } +#endif + + _FWDownloadEnable(padapter, _FALSE); + + rtStatus = _FWFreeToGo(padapter, 10, 200); + if (_SUCCESS != rtStatus) + goto DLFW_FAIL; + + DBG_871X("%s: DLFW OK !\n", __func__); + +DLFW_FAIL: + if (rtStatus == _FAIL) { + /* Disable FWDL_EN */ + value8 = rtw_read8(padapter, REG_MCUFWDL); + value8 = (value8 & ~(BIT(0)) & ~(BIT(1))); + rtw_write8(padapter, REG_MCUFWDL, value8); + } + + DBG_871X("%s %s. write_fw:%u, %dms\n" + , __func__, (rtStatus == _SUCCESS) ? "success" : "fail" + , write_fw + , rtw_get_passing_time_ms(fwdl_start_time) + ); + +exit: + release_firmware(fw); + + rtl8188f_InitializeFirmwareVars(padapter); + + DBG_871X(" <=== %s()\n", __func__); + + return rtStatus; +} + +void rtl8188f_InitializeFirmwareVars(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + + /* Init Fw LPS related. */ + adapter_to_pwrctl(padapter)->bFwCurrentInPSMode = _FALSE; + + /*Init H2C cmd. */ + rtw_write8(padapter, REG_HMETFR, 0x0f); + + /* Init H2C counter. by tynli. 2009.12.09. */ + pHalData->LastHMEBoxNum = 0; + /*pHalData->H2CQueueHead = 0; */ + /*pHalData->H2CQueueTail = 0; */ + /*pHalData->H2CStopInsertQueue = _FALSE; */ +} + +/*=========================================================== */ +/* Efuse related code */ +/*=========================================================== */ +static u8 +hal_EfuseSwitchToBank( + PADAPTER padapter, + u8 bank, + u8 bPseudoTest) +{ + u8 bRet = _FALSE; + u32 value32 = 0; +#ifdef HAL_EFUSE_MEMORY + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; +#endif + + + DBG_8192C("%s: Efuse switch bank to %d\n", __func__, bank); + if (bPseudoTest) { +#ifdef HAL_EFUSE_MEMORY + pEfuseHal->fakeEfuseBank = bank; +#else + fakeEfuseBank = bank; +#endif + bRet = _TRUE; + } else { + value32 = rtw_read32(padapter, EFUSE_TEST); + bRet = _TRUE; + switch (bank) { + case 0: + value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); + break; + case 1: + value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_0); + break; + case 2: + value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_1); + break; + case 3: + value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_2); + break; + default: + value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); + bRet = _FALSE; + break; + } + rtw_write32(padapter, EFUSE_TEST, value32); + } + + return bRet; +} + +static void +Hal_GetEfuseDefinition( + PADAPTER padapter, + u8 efuseType, + u8 type, + void *pOut, + u8 bPseudoTest) +{ + switch (type) { + case TYPE_EFUSE_MAX_SECTION: { + u8 *pMax_section; + + pMax_section = (u8 *)pOut; + + if (efuseType == EFUSE_WIFI) + *pMax_section = EFUSE_MAX_SECTION_8188F; + else + *pMax_section = EFUSE_BT_MAX_SECTION; + } + break; + + case TYPE_EFUSE_REAL_CONTENT_LEN: { + u16 *pu2Tmp; + + pu2Tmp = (u16 *)pOut; + + if (efuseType == EFUSE_WIFI) + *pu2Tmp = EFUSE_REAL_CONTENT_LEN_8188F; + else + *pu2Tmp = EFUSE_BT_REAL_CONTENT_LEN; + } + break; + + case TYPE_AVAILABLE_EFUSE_BYTES_BANK: { + u16 *pu2Tmp; + + pu2Tmp = (u16 *)pOut; + + if (efuseType == EFUSE_WIFI) + *pu2Tmp = (EFUSE_REAL_CONTENT_LEN_8188F - EFUSE_OOB_PROTECT_BYTES); + else + *pu2Tmp = (EFUSE_BT_REAL_BANK_CONTENT_LEN - EFUSE_PROTECT_BYTES_BANK); + } + break; + + case TYPE_AVAILABLE_EFUSE_BYTES_TOTAL: { + u16 *pu2Tmp; + + pu2Tmp = (u16 *)pOut; + + if (efuseType == EFUSE_WIFI) + *pu2Tmp = (EFUSE_REAL_CONTENT_LEN_8188F - EFUSE_OOB_PROTECT_BYTES); + else + *pu2Tmp = (EFUSE_BT_REAL_CONTENT_LEN - (EFUSE_PROTECT_BYTES_BANK * 3)); + } + break; + + case TYPE_EFUSE_MAP_LEN: { + u16 *pu2Tmp; + + pu2Tmp = (u16 *)pOut; + + if (efuseType == EFUSE_WIFI) + *pu2Tmp = EFUSE_MAP_LEN_8188F; + else + *pu2Tmp = EFUSE_BT_MAP_LEN; + } + break; + + case TYPE_EFUSE_PROTECT_BYTES_BANK: { + u8 *pu1Tmp; + + pu1Tmp = (u8 *)pOut; + + if (efuseType == EFUSE_WIFI) + *pu1Tmp = EFUSE_OOB_PROTECT_BYTES; + else + *pu1Tmp = EFUSE_PROTECT_BYTES_BANK; + } + break; + + case TYPE_EFUSE_CONTENT_LEN_BANK: { + u16 *pu2Tmp; + + pu2Tmp = (u16 *)pOut; + + if (efuseType == EFUSE_WIFI) + *pu2Tmp = EFUSE_REAL_CONTENT_LEN_8188F; + else + *pu2Tmp = EFUSE_BT_REAL_BANK_CONTENT_LEN; + } + break; + + default: { + u8 *pu1Tmp; + + pu1Tmp = (u8 *)pOut; + *pu1Tmp = 0; + } + break; + } +} + +#define VOLTAGE_V25 0x03 +#define LDOE25_SHIFT 28 + +/*================================================================= */ +/* The following is for compile ok */ +/* That should be merged with the original in the future */ +/*================================================================= */ +#define EFUSE_ACCESS_ON_8188 0x69 /* For RTL8188 only. */ +#define EFUSE_ACCESS_OFF_8188 0x00 /* For RTL8188 only. */ +#define REG_EFUSE_ACCESS_8188 0x00CF /* Efuse access protection for RTL8188 */ + +/*================================================================= */ +static void Hal_BT_EfusePowerSwitch( + PADAPTER padapter, + u8 bWrite, + u8 PwrState) +{ + u8 tempval; + if (PwrState == _TRUE) { + /* enable BT power cut */ + /* 0x6A[14] = 1 */ + tempval = rtw_read8(padapter, 0x6B); + tempval |= BIT(6); + rtw_write8(padapter, 0x6B, tempval); + + /* Attention!! Between 0x6A[14] and 0x6A[15] setting need 100us delay */ + /* So don't write 0x6A[14]=1 and 0x6A[15]=0 together! */ + rtw_usleep_os(100); + /* disable BT output isolation */ + /* 0x6A[15] = 0 */ + tempval = rtw_read8(padapter, 0x6B); + tempval &= ~BIT(7); + rtw_write8(padapter, 0x6B, tempval); + } else { + /* enable BT output isolation */ + /* 0x6A[15] = 1 */ + tempval = rtw_read8(padapter, 0x6B); + tempval |= BIT(7); + rtw_write8(padapter, 0x6B, tempval); + + /* Attention!! Between 0x6A[14] and 0x6A[15] setting need 100us delay */ + /* So don't write 0x6A[14]=1 and 0x6A[15]=0 together! */ + + /* disable BT power cut */ + /* 0x6A[14] = 1 */ + tempval = rtw_read8(padapter, 0x6B); + tempval &= ~BIT(6); + rtw_write8(padapter, 0x6B, tempval); + } + +} +static void +Hal_EfusePowerSwitch( + PADAPTER padapter, + u8 bWrite, + u8 PwrState) +{ + u8 tempval; + u16 tmpV16; + + + if (PwrState == _TRUE) { +#ifdef CONFIG_SDIO_HCI + /* To avoid cannot access efuse regsiters after disable/enable several times during DTM test. */ + /* Suggested by SD1 IsaacHsu. 2013.07.08, added by tynli. */ + tempval = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HSUS_CTRL); + if (tempval & BIT(0)) { /* SDIO local register is suspend */ + u8 count = 0; + + + tempval &= ~BIT(0); + rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HSUS_CTRL, tempval); + + /* check 0x86[1:0]=10'2h, wait power state to leave suspend */ + do { + tempval = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HSUS_CTRL); + tempval &= 0x3; + if (tempval == 0x02) + break; + + count++; + if (count >= 100) + break; + + rtw_mdelay_os(10); + } while (1); + + if (count >= 100) { + DBG_8192C(FUNC_ADPT_FMT ": Leave SDIO local register suspend fail! Local 0x86=%#X\n", + FUNC_ADPT_ARG(padapter), tempval); + } else { + DBG_8192C(FUNC_ADPT_FMT ": Leave SDIO local register suspend OK! Local 0x86=%#X\n", + FUNC_ADPT_ARG(padapter), tempval); + } + } +#endif /* CONFIG_SDIO_HCI */ + + rtw_write8(padapter, REG_EFUSE_ACCESS_8188, EFUSE_ACCESS_ON_8188); + + /* Reset: 0x0000h[28], default valid */ + tmpV16 = rtw_read16(padapter, REG_SYS_FUNC_EN); + if (!(tmpV16 & FEN_ELDR)) { + tmpV16 |= FEN_ELDR; + rtw_write16(padapter, REG_SYS_FUNC_EN, tmpV16); + } + + /* Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock from ANA, default valid */ + tmpV16 = rtw_read16(padapter, REG_SYS_CLKR); + if ((!(tmpV16 & LOADER_CLK_EN)) || (!(tmpV16 & ANA8M))) { + tmpV16 |= (LOADER_CLK_EN | ANA8M); + rtw_write16(padapter, REG_SYS_CLKR, tmpV16); + } + + if (bWrite == _TRUE) { + /* Enable LDO 2.5V before read/write action */ + tempval = rtw_read8(padapter, EFUSE_TEST + 3); + rtw_write8(padapter, EFUSE_TEST + 3, (tempval | 0x80)); + } + } else { + rtw_write8(padapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF); + + if (bWrite == _TRUE) { + /* Disable LDO 2.5V after read/write action */ + tempval = rtw_read8(padapter, EFUSE_TEST + 3); + rtw_write8(padapter, EFUSE_TEST + 3, (tempval & 0x7F)); + } + + } +} + +static void +hal_ReadEFuse_WiFi( + PADAPTER padapter, + u16 _offset, + u16 _size_byte, + u8 *pbuf, + u8 bPseudoTest) +{ +#ifdef HAL_EFUSE_MEMORY + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; +#endif + u8 *efuseTbl = NULL; + u16 eFuse_Addr = 0; + u8 offset, wden; + u8 efuseHeader, efuseExtHdr, efuseData; + u16 i, total, used; + u8 efuse_usage = 0; + + /*DBG_871X("YJ: ====>%s():_offset=%d _size_byte=%d bPseudoTest=%d\n", __func__, _offset, _size_byte, bPseudoTest); */ + /* */ + /* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */ + /* */ + if ((_offset + _size_byte) > EFUSE_MAX_MAP_LEN) { + DBG_8192C("%s: Invalid offset(%#x) with read bytes(%#x)!!\n", __func__, _offset, _size_byte); + return; + } + + efuseTbl = (u8 *)rtw_malloc(EFUSE_MAX_MAP_LEN); + if (efuseTbl == NULL) { + DBG_8192C("%s: alloc efuseTbl fail!\n", __func__); + return; + } + /* 0xff will be efuse default value instead of 0x00. */ + _rtw_memset(efuseTbl, 0xFF, EFUSE_MAX_MAP_LEN); + + +#ifdef CONFIG_DEBUG + if (0) { + for (i = 0; i < 256; i++) + /*ReadEFuseByte(padapter, i, &efuseTbl[i], _FALSE); */ + efuse_OneByteRead(padapter, i, &efuseTbl[i], _FALSE); + DBG_871X("Efuse Content:\n"); + for (i = 0; i < 256; i++) + printk("%02X%s", efuseTbl[i], (((i + 1) % 16) == 0)?"\n":" "); + } +#endif + + + /* switch bank back to bank 0 for later BT and wifi use. */ + hal_EfuseSwitchToBank(padapter, 0, bPseudoTest); + + while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) { + /*ReadEFuseByte(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest); */ + efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest); + if (efuseHeader == 0xFF) { + DBG_8192C("%s: data end at address=%#x\n", __func__, eFuse_Addr - 1); + break; + } + /*DBG_8192C("%s: efuse[0x%X]=0x%02X\n", __func__, eFuse_Addr-1, efuseHeader); */ + + /* Check PG header for section num. */ + if (EXT_HEADER(efuseHeader)) { /*extended header */ + offset = GET_HDR_OFFSET_2_0(efuseHeader); + /*DBG_8192C("%s: extended header offset=0x%X\n", __func__, offset); */ + + /*ReadEFuseByte(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest); */ + efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest); + /*DBG_8192C("%s: efuse[0x%X]=0x%02X\n", __func__, eFuse_Addr-1, efuseExtHdr); */ + if (ALL_WORDS_DISABLED(efuseExtHdr)) + continue; + + offset |= ((efuseExtHdr & 0xF0) >> 1); + wden = (efuseExtHdr & 0x0F); + } else { + offset = ((efuseHeader >> 4) & 0x0f); + wden = (efuseHeader & 0x0f); + } + /*DBG_8192C("%s: Offset=%d Worden=0x%X\n", __func__, offset, wden); */ + + if (offset < EFUSE_MAX_SECTION_8188F) { + u16 addr; + /* Get word enable value from PG header */ + /*DBG_8192C("%s: Offset=%d Worden=0x%X\n", __func__, offset, wden); */ + + addr = offset * PGPKT_DATA_SIZE; + for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { + /* Check word enable condition in the section */ + if (!(wden & (0x01 << i))) { + efuseData = 0; + /*ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */ + efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest); + /*DBG_8192C("%s: efuse[%#X]=0x%02X\n", __func__, eFuse_Addr-1, efuseData); */ + efuseTbl[addr] = efuseData; + + efuseData = 0; + /*ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */ + efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest); + /*DBG_8192C("%s: efuse[%#X]=0x%02X\n", __func__, eFuse_Addr-1, efuseData); */ + efuseTbl[addr + 1] = efuseData; + } + addr += 2; + } + } else { + DBG_8192C(KERN_ERR "%s: offset(%d) is illegal!!\n", __func__, offset); + eFuse_Addr += Efuse_CalculateWordCnts(wden) * 2; + } + } + + /* Copy from Efuse map to output pointer memory!!! */ + for (i = 0; i < _size_byte; i++) + pbuf[i] = efuseTbl[_offset + i]; + +#if 0 +#ifdef CONFIG_DEBUG + if (1) { + DBG_871X("Efuse Realmap:\n"); + for (i = 0; i < _size_byte; i++) + printk("%02X%s", pbuf[i], (((i + 1) % 16) == 0)?"\n":" "); + } +#endif +#endif + /* Calculate Efuse utilization */ + total = 0; + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total, bPseudoTest); + used = eFuse_Addr - 1; + if (total) + efuse_usage = (u8)((used * 100) / total); + else + efuse_usage = 100; + if (bPseudoTest) { +#ifdef HAL_EFUSE_MEMORY + pEfuseHal->fakeEfuseUsedBytes = used; +#else + fakeEfuseUsedBytes = used; +#endif + } else { + rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&used); + rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_USAGE, (u8 *)&efuse_usage); + } + + if (efuseTbl) + rtw_mfree(efuseTbl, EFUSE_MAX_MAP_LEN); +} + +static VOID +hal_ReadEFuse_BT( + PADAPTER padapter, + u16 _offset, + u16 _size_byte, + u8 *pbuf, + u8 bPseudoTest +) +{ +#ifdef HAL_EFUSE_MEMORY + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; +#endif + u8 *efuseTbl; + u8 bank; + u16 eFuse_Addr; + u8 efuseHeader, efuseExtHdr, efuseData; + u8 offset, wden; + u16 i, total, used; + u8 efuse_usage; + + + /* */ + /* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */ + /* */ + if ((_offset + _size_byte) > EFUSE_BT_MAP_LEN) { + DBG_8192C("%s: Invalid offset(%#x) with read bytes(%#x)!!\n", __func__, _offset, _size_byte); + return; + } + + efuseTbl = rtw_malloc(EFUSE_BT_MAP_LEN); + if (efuseTbl == NULL) { + DBG_8192C("%s: efuseTbl malloc fail!\n", __func__); + return; + } + /* 0xff will be efuse default value instead of 0x00. */ + _rtw_memset(efuseTbl, 0xFF, EFUSE_BT_MAP_LEN); + + total = 0; + EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &total, bPseudoTest); + + for (bank = 1; bank < 3; bank++) { /* 8188F Max bake 0~2 */ + if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == _FALSE) { + DBG_8192C("%s: hal_EfuseSwitchToBank Fail!!\n", __func__); + goto exit; + } + + eFuse_Addr = 0; + + while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) { + /*ReadEFuseByte(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest); */ + efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest); + if (efuseHeader == 0xFF) break; + DBG_8192C("%s: efuse[%#X]=0x%02x (header)\n", __func__, (((bank - 1)*EFUSE_REAL_CONTENT_LEN_8188F) + eFuse_Addr - 1), efuseHeader); + + /* Check PG header for section num. */ + if (EXT_HEADER(efuseHeader)) { /*extended header */ + offset = GET_HDR_OFFSET_2_0(efuseHeader); + DBG_8192C("%s: extended header offset_2_0=0x%X\n", __func__, offset); + + /*ReadEFuseByte(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest); */ + efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest); + DBG_8192C("%s: efuse[%#X]=0x%02x (ext header)\n", __func__, (((bank - 1)*EFUSE_REAL_CONTENT_LEN_8188F) + eFuse_Addr - 1), efuseExtHdr); + if (ALL_WORDS_DISABLED(efuseExtHdr)) + continue; + + offset |= ((efuseExtHdr & 0xF0) >> 1); + wden = (efuseExtHdr & 0x0F); + } else { + offset = ((efuseHeader >> 4) & 0x0f); + wden = (efuseHeader & 0x0f); + } + + if (offset < EFUSE_BT_MAX_SECTION) { + u16 addr; + + /* Get word enable value from PG header */ + DBG_8192C("%s: Offset=%d Worden=%#X\n", __func__, offset, wden); + + addr = offset * PGPKT_DATA_SIZE; + for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { + /* Check word enable condition in the section */ + if (!(wden & (0x01 << i))) { + efuseData = 0; + /*ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */ + efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest); + DBG_8192C("%s: efuse[%#X]=0x%02X\n", __func__, eFuse_Addr - 1, efuseData); + efuseTbl[addr] = efuseData; + + efuseData = 0; + /*ReadEFuseByte(padapter, eFuse_Addr++, &efuseData, bPseudoTest); */ + efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest); + DBG_8192C("%s: efuse[%#X]=0x%02X\n", __func__, eFuse_Addr - 1, efuseData); + efuseTbl[addr + 1] = efuseData; + } + addr += 2; + } + } else { + DBG_8192C("%s: offset(%d) is illegal!!\n", __func__, offset); + eFuse_Addr += Efuse_CalculateWordCnts(wden) * 2; + } + } + + if ((eFuse_Addr - 1) < total) { + DBG_8192C("%s: bank(%d) data end at %#x\n", __func__, bank, eFuse_Addr - 1); + break; + } + } + + /* switch bank back to bank 0 for later BT and wifi use. */ + hal_EfuseSwitchToBank(padapter, 0, bPseudoTest); + + /* Copy from Efuse map to output pointer memory!!! */ + for (i = 0; i < _size_byte; i++) + pbuf[i] = efuseTbl[_offset + i]; + + /* */ + /* Calculate Efuse utilization. */ + /* */ + EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total, bPseudoTest); + used = (EFUSE_BT_REAL_BANK_CONTENT_LEN * (bank - 1)) + eFuse_Addr - 1; + DBG_8192C("%s: bank(%d) data end at %#x ,used =%d\n", __func__, bank, eFuse_Addr - 1, used); + efuse_usage = (u8)((used * 100) / total); + if (bPseudoTest) { +#ifdef HAL_EFUSE_MEMORY + pEfuseHal->fakeBTEfuseUsedBytes = used; +#else + fakeBTEfuseUsedBytes = used; +#endif + } else { + rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&used); + rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BT_USAGE, (u8 *)&efuse_usage); + } + +exit: + if (efuseTbl) + rtw_mfree(efuseTbl, EFUSE_BT_MAP_LEN); +} + +static void +Hal_ReadEFuse( + PADAPTER padapter, + u8 efuseType, + u16 _offset, + u16 _size_byte, + u8 *pbuf, + u8 bPseudoTest) +{ + if (efuseType == EFUSE_WIFI) + hal_ReadEFuse_WiFi(padapter, _offset, _size_byte, pbuf, bPseudoTest); + else + hal_ReadEFuse_BT(padapter, _offset, _size_byte, pbuf, bPseudoTest); +} + +static u16 +hal_EfuseGetCurrentSize_WiFi( + PADAPTER padapter, + u8 bPseudoTest) +{ +#ifdef HAL_EFUSE_MEMORY + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; +#endif + u16 efuse_addr = 0; + u16 start_addr = 0; /* for debug */ + u8 hoffset = 0, hworden = 0; + u8 efuse_data, word_cnts = 0; + u32 count = 0; /* for debug */ + + + if (bPseudoTest) { +#ifdef HAL_EFUSE_MEMORY + efuse_addr = (u16)pEfuseHal->fakeEfuseUsedBytes; +#else + efuse_addr = (u16)fakeEfuseUsedBytes; +#endif + } else + rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr); + start_addr = efuse_addr; + DBG_8192C("%s: start_efuse_addr=0x%X\n", __func__, efuse_addr); + + /* switch bank back to bank 0 for later BT and wifi use. */ + hal_EfuseSwitchToBank(padapter, 0, bPseudoTest); + +#if 0 /* for debug test */ + efuse_OneByteRead(padapter, 0x1FF, &efuse_data, bPseudoTest); + DBG_8192C(FUNC_ADPT_FMT ": efuse raw 0x1FF=0x%02X\n", + FUNC_ADPT_ARG(padapter), efuse_data); + efuse_data = 0xFF; +#endif /* for debug test */ + + count = 0; + while (AVAILABLE_EFUSE_ADDR(efuse_addr)) { +#if 1 + if (efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest) == _FALSE) { + DBG_8192C(KERN_ERR "%s: efuse_OneByteRead Fail! addr=0x%X !!\n", __func__, efuse_addr); + goto error; + } +#else + ReadEFuseByte(padapter, efuse_addr, &efuse_data, bPseudoTest); +#endif + + if (efuse_data == 0xFF) break; + + if ((start_addr != 0) && (efuse_addr == start_addr)) { + count++; + DBG_8192C(FUNC_ADPT_FMT ": [WARNING] efuse raw 0x%X=0x%02X not 0xFF!!(%d times)\n", + FUNC_ADPT_ARG(padapter), efuse_addr, efuse_data, count); + + efuse_data = 0xFF; + if (count < 4) { + /* try again! */ + + if (count > 2) { + /* try again form address 0 */ + efuse_addr = 0; + start_addr = 0; + } + + continue; + } + + goto error; + } + + if (EXT_HEADER(efuse_data)) { + hoffset = GET_HDR_OFFSET_2_0(efuse_data); + efuse_addr++; + efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest); + if (ALL_WORDS_DISABLED(efuse_data)) + continue; + + hoffset |= ((efuse_data & 0xF0) >> 1); + hworden = efuse_data & 0x0F; + } else { + hoffset = (efuse_data >> 4) & 0x0F; + hworden = efuse_data & 0x0F; + } + + word_cnts = Efuse_CalculateWordCnts(hworden); + efuse_addr += (word_cnts * 2) + 1; + } + + if (bPseudoTest) { +#ifdef HAL_EFUSE_MEMORY + pEfuseHal->fakeEfuseUsedBytes = efuse_addr; +#else + fakeEfuseUsedBytes = efuse_addr; +#endif + } else + rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr); + + goto exit; + +error: + /* report max size to prevent write efuse */ + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_addr, bPseudoTest); + +exit: + DBG_8192C("%s: CurrentSize=%d\n", __func__, efuse_addr); + + return efuse_addr; +} + +static u16 +hal_EfuseGetCurrentSize_BT( + PADAPTER padapter, + u8 bPseudoTest) +{ +#ifdef HAL_EFUSE_MEMORY + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; +#endif + u16 btusedbytes; + u16 efuse_addr; + u8 bank, startBank; + u8 hoffset = 0, hworden = 0; + u8 efuse_data, word_cnts = 0; + u16 retU2 = 0; + u8 bContinual = _TRUE; + + + if (bPseudoTest) { +#ifdef HAL_EFUSE_MEMORY + btusedbytes = pEfuseHal->fakeBTEfuseUsedBytes; +#else + btusedbytes = fakeBTEfuseUsedBytes; +#endif + } else { + btusedbytes = 0; + rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&btusedbytes); + } + efuse_addr = (u16)((btusedbytes % EFUSE_BT_REAL_BANK_CONTENT_LEN)); + startBank = (u8)(1 + (btusedbytes / EFUSE_BT_REAL_BANK_CONTENT_LEN)); + + DBG_8192C("%s: start from bank=%d addr=0x%X\n", __func__, startBank, efuse_addr); + + EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &retU2, bPseudoTest); + + for (bank = startBank; bank < 3; bank++) { + if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == _FALSE) { + DBG_8192C(KERN_ERR "%s: switch bank(%d) Fail!!\n", __func__, bank); + /*bank = EFUSE_MAX_BANK; */ + break; + } + + /* only when bank is switched we have to reset the efuse_addr. */ + if (bank != startBank) + efuse_addr = 0; +#if 1 + + while (AVAILABLE_EFUSE_ADDR(efuse_addr)) { + if (efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest) == _FALSE) { + DBG_8192C(KERN_ERR "%s: efuse_OneByteRead Fail! addr=0x%X !!\n", __func__, efuse_addr); + /*bank = EFUSE_MAX_BANK; */ + break; + } + DBG_8192C("%s: efuse_OneByteRead ! addr=0x%X !efuse_data=0x%X! bank =%d\n", __func__, efuse_addr, efuse_data, bank); + + if (efuse_data == 0xFF) break; + + if (EXT_HEADER(efuse_data)) { + hoffset = GET_HDR_OFFSET_2_0(efuse_data); + efuse_addr++; + efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest); + DBG_8192C("%s: efuse_OneByteRead EXT_HEADER ! addr=0x%X !efuse_data=0x%X! bank =%d\n", __func__, efuse_addr, efuse_data, bank); + + if (ALL_WORDS_DISABLED(efuse_data)) { + efuse_addr++; + continue; + } + + /*hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1); */ + hoffset |= ((efuse_data & 0xF0) >> 1); + hworden = efuse_data & 0x0F; + } else { + hoffset = (efuse_data >> 4) & 0x0F; + hworden = efuse_data & 0x0F; + } + + DBG_8192C(FUNC_ADPT_FMT": Offset=%d Worden=%#X\n", + FUNC_ADPT_ARG(padapter), hoffset, hworden); + + word_cnts = Efuse_CalculateWordCnts(hworden); + /*read next header */ + efuse_addr += (word_cnts * 2) + 1; + } +#else + while (bContinual && + efuse_OneByteRead(padapter, efuse_addr , &efuse_data, bPseudoTest) && + AVAILABLE_EFUSE_ADDR(efuse_addr)) { + if (efuse_data != 0xFF) { + if ((efuse_data & 0x1F) == 0x0F) { /*extended header */ + hoffset = efuse_data; + efuse_addr++; + efuse_OneByteRead(padapter, efuse_addr , &efuse_data, bPseudoTest); + if ((efuse_data & 0x0F) == 0x0F) { + efuse_addr++; + continue; + } else { + hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1); + hworden = efuse_data & 0x0F; + } + } else { + hoffset = (efuse_data >> 4) & 0x0F; + hworden = efuse_data & 0x0F; + } + word_cnts = Efuse_CalculateWordCnts(hworden); + /*read next header */ + efuse_addr = efuse_addr + (word_cnts * 2) + 1; + } else + bContinual = _FALSE; + } +#endif + + + /* Check if we need to check next bank efuse */ + if (efuse_addr < retU2) { + /* don't need to check next bank. */ + break; + } + } +#if 0 + retU2 = ((bank - 1) * EFUSE_BT_REAL_BANK_CONTENT_LEN) + efuse_addr; + if (bPseudoTest) { +#ifdef HAL_EFUSE_MEMORY + pEfuseHal->fakeBTEfuseUsedBytes = retU2; +#else + fakeBTEfuseUsedBytes = retU2; +#endif + } else + rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&retU2); +#else + retU2 = ((bank - 1) * EFUSE_BT_REAL_BANK_CONTENT_LEN) + efuse_addr; + if (bPseudoTest) { + pEfuseHal->fakeBTEfuseUsedBytes = retU2; + /*RT_DISP(FEEPROM, EFUSE_PG, ("Hal_EfuseGetCurrentSize_BT92C(), already use %u bytes\n", pEfuseHal->fakeBTEfuseUsedBytes)); */ + } else { + pEfuseHal->BTEfuseUsedBytes = retU2; + /*RT_DISP(FEEPROM, EFUSE_PG, ("Hal_EfuseGetCurrentSize_BT92C(), already use %u bytes\n", pEfuseHal->BTEfuseUsedBytes)); */ + } +#endif + + DBG_8192C("%s: CurrentSize=%d\n", __func__, retU2); + return retU2; +} + +static u16 +Hal_EfuseGetCurrentSize( + PADAPTER pAdapter, + u8 efuseType, + u8 bPseudoTest) +{ + u16 ret = 0; + + if (efuseType == EFUSE_WIFI) + ret = hal_EfuseGetCurrentSize_WiFi(pAdapter, bPseudoTest); + else + ret = hal_EfuseGetCurrentSize_BT(pAdapter, bPseudoTest); + + return ret; +} + +static u8 +Hal_EfuseWordEnableDataWrite( + PADAPTER padapter, + u16 efuse_addr, + u8 word_en, + u8 *data, + u8 bPseudoTest) +{ + u16 tmpaddr = 0; + u16 start_addr = efuse_addr; + u8 badworden = 0x0F; + u8 tmpdata[PGPKT_DATA_SIZE]; + + + /*DBG_8192C("%s: efuse_addr=%#x word_en=%#x\n", __func__, efuse_addr, word_en); */ + _rtw_memset(tmpdata, 0xFF, PGPKT_DATA_SIZE); + + if (!(word_en & BIT(0))) { + tmpaddr = start_addr; + efuse_OneByteWrite(padapter, start_addr++, data[0], bPseudoTest); + efuse_OneByteWrite(padapter, start_addr++, data[1], bPseudoTest); + PHY_SetMacReg(padapter, EFUSE_TEST, BIT26, 0); + efuse_OneByteRead(padapter, tmpaddr, &tmpdata[0], bPseudoTest); + efuse_OneByteRead(padapter, tmpaddr + 1, &tmpdata[1], bPseudoTest); + PHY_SetMacReg(padapter, EFUSE_TEST, BIT26, 1); + if ((data[0] != tmpdata[0]) || (data[1] != tmpdata[1])) + badworden &= (~BIT(0)); + } + if (!(word_en & BIT(1))) { + tmpaddr = start_addr; + efuse_OneByteWrite(padapter, start_addr++, data[2], bPseudoTest); + efuse_OneByteWrite(padapter, start_addr++, data[3], bPseudoTest); + PHY_SetMacReg(padapter, EFUSE_TEST, BIT26, 0); + efuse_OneByteRead(padapter, tmpaddr, &tmpdata[2], bPseudoTest); + efuse_OneByteRead(padapter, tmpaddr + 1, &tmpdata[3], bPseudoTest); + PHY_SetMacReg(padapter, EFUSE_TEST, BIT26, 1); + if ((data[2] != tmpdata[2]) || (data[3] != tmpdata[3])) + badworden &= (~BIT(1)); + } + if (!(word_en & BIT(2))) { + tmpaddr = start_addr; + efuse_OneByteWrite(padapter, start_addr++, data[4], bPseudoTest); + efuse_OneByteWrite(padapter, start_addr++, data[5], bPseudoTest); + PHY_SetMacReg(padapter, EFUSE_TEST, BIT26, 0); + efuse_OneByteRead(padapter, tmpaddr, &tmpdata[4], bPseudoTest); + efuse_OneByteRead(padapter, tmpaddr + 1, &tmpdata[5], bPseudoTest); + PHY_SetMacReg(padapter, EFUSE_TEST, BIT26, 1); + if ((data[4] != tmpdata[4]) || (data[5] != tmpdata[5])) + badworden &= (~BIT(2)); + } + if (!(word_en & BIT(3))) { + tmpaddr = start_addr; + efuse_OneByteWrite(padapter, start_addr++, data[6], bPseudoTest); + efuse_OneByteWrite(padapter, start_addr++, data[7], bPseudoTest); + PHY_SetMacReg(padapter, EFUSE_TEST, BIT26, 0); + efuse_OneByteRead(padapter, tmpaddr, &tmpdata[6], bPseudoTest); + efuse_OneByteRead(padapter, tmpaddr + 1, &tmpdata[7], bPseudoTest); + PHY_SetMacReg(padapter, EFUSE_TEST, BIT26, 1); + if ((data[6] != tmpdata[6]) || (data[7] != tmpdata[7])) + badworden &= (~BIT(3)); + } + + return badworden; +} + +static s32 +Hal_EfusePgPacketRead( + PADAPTER padapter, + u8 offset, + u8 *data, + u8 bPseudoTest) +{ + u8 bDataEmpty = _TRUE; + u8 efuse_data, word_cnts = 0; + u16 efuse_addr = 0; + u8 hoffset = 0, hworden = 0; + u8 i; + u8 max_section = 0; + s32 ret; + + + if (data == NULL) + return _FALSE; + + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAX_SECTION, &max_section, bPseudoTest); + if (offset > max_section) { + DBG_8192C("%s: Packet offset(%d) is illegal(>%d)!\n", __func__, offset, max_section); + return _FALSE; + } + + _rtw_memset(data, 0xFF, PGPKT_DATA_SIZE); + ret = _TRUE; + + /* */ + /* Efuse has been pre-programmed dummy 5Bytes at the end of Efuse by CP. */ + /* Skip dummy parts to prevent unexpected data read from Efuse. */ + /* By pass right now. 2009.02.19. */ + /* */ + while (AVAILABLE_EFUSE_ADDR(efuse_addr)) { + if (efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest) == _FALSE) { + ret = _FALSE; + break; + } + + if (efuse_data == 0xFF) break; + + if (EXT_HEADER(efuse_data)) { + hoffset = GET_HDR_OFFSET_2_0(efuse_data); + efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest); + if (ALL_WORDS_DISABLED(efuse_data)) { + DBG_8192C("%s: Error!! All words disabled!\n", __func__); + continue; + } + + hoffset |= ((efuse_data & 0xF0) >> 1); + hworden = efuse_data & 0x0F; + } else { + hoffset = (efuse_data >> 4) & 0x0F; + hworden = efuse_data & 0x0F; + } + + if (hoffset == offset) { + for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { + /* Check word enable condition in the section */ + if (!(hworden & (0x01 << i))) { + /*ReadEFuseByte(padapter, efuse_addr++, &efuse_data, bPseudoTest); */ + efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest); + /*DBG_8192C("%s: efuse[%#X]=0x%02X\n", __func__, efuse_addr+tmpidx, efuse_data); */ + data[i * 2] = efuse_data; + + /*ReadEFuseByte(padapter, efuse_addr++, &efuse_data, bPseudoTest); */ + efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest); + /*DBG_8192C("%s: efuse[%#X]=0x%02X\n", __func__, efuse_addr+tmpidx, efuse_data); */ + data[(i * 2) + 1] = efuse_data; + } + } + } else { + word_cnts = Efuse_CalculateWordCnts(hworden); + efuse_addr += word_cnts * 2; + } + } + + return ret; +} + +static u8 +hal_EfusePgCheckAvailableAddr( + PADAPTER pAdapter, + u8 efuseType, + u8 bPseudoTest) +{ + u16 max_available = 0; + u16 current_size; + + + EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &max_available, bPseudoTest); + /*DBG_8192C("%s: max_available=%d\n", __func__, max_available); */ + + current_size = Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest); + if (current_size >= max_available) { + DBG_8192C("%s: Error!! current_size(%d)>max_available(%d)\n", __func__, current_size, max_available); + return _FALSE; + } + return _TRUE; +} + +static void +hal_EfuseConstructPGPkt( + u8 offset, + u8 word_en, + u8 *pData, + PPGPKT_STRUCT pTargetPkt) +{ + _rtw_memset(pTargetPkt->data, 0xFF, PGPKT_DATA_SIZE); + pTargetPkt->offset = offset; + pTargetPkt->word_en = word_en; + efuse_WordEnableDataRead(word_en, pData, pTargetPkt->data); + pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en); +} + +#if 0 +static u8 +wordEnMatched( + PPGPKT_STRUCT pTargetPkt, + PPGPKT_STRUCT pCurPkt, + u8 *pWden) +{ + u8 match_word_en = 0x0F; /* default all words are disabled */ + u8 i; + + /* check if the same words are enabled both target and current PG packet */ + if (((pTargetPkt->word_en & BIT(0)) == 0) && + ((pCurPkt->word_en & BIT(0)) == 0)) { + match_word_en &= ~BIT(0); /* enable word 0 */ + } + if (((pTargetPkt->word_en & BIT(1)) == 0) && + ((pCurPkt->word_en & BIT(1)) == 0)) { + match_word_en &= ~BIT(1); /* enable word 1 */ + } + if (((pTargetPkt->word_en & BIT(2)) == 0) && + ((pCurPkt->word_en & BIT(2)) == 0)) { + match_word_en &= ~BIT(2); /* enable word 2 */ + } + if (((pTargetPkt->word_en & BIT(3)) == 0) && + ((pCurPkt->word_en & BIT(3)) == 0)) { + match_word_en &= ~BIT(3); /* enable word 3 */ + } + + *pWden = match_word_en; + + if (match_word_en != 0xf) + return _TRUE; + else + return _FALSE; +} + +static u8 +hal_EfuseCheckIfDatafollowed( + PADAPTER pAdapter, + u8 word_cnts, + u16 startAddr, + u8 bPseudoTest) +{ + u8 bRet = _FALSE; + u8 i, efuse_data; + + for (i = 0; i < (word_cnts * 2); i++) { + if (efuse_OneByteRead(pAdapter, (startAddr + i) , &efuse_data, bPseudoTest) == _FALSE) { + DBG_8192C("%s: efuse_OneByteRead FAIL!!\n", __func__); + bRet = _TRUE; + break; + } + + if (efuse_data != 0xFF) { + bRet = _TRUE; + break; + } + } + + return bRet; +} +#endif + +static u8 +hal_EfusePartialWriteCheck( + PADAPTER padapter, + u8 efuseType, + u16 *pAddr, + PPGPKT_STRUCT pTargetPkt, + u8 bPseudoTest) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; + u8 bRet = _FALSE; + u16 startAddr = 0, efuse_max_available_len = 0, efuse_max = 0; + u8 efuse_data = 0; +#if 0 + u8 i, cur_header = 0; + u8 new_wden = 0, matched_wden = 0, badworden = 0; + PGPKT_STRUCT curPkt; +#endif + + + EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_max_available_len, bPseudoTest); + EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_CONTENT_LEN_BANK, &efuse_max, bPseudoTest); + + if (efuseType == EFUSE_WIFI) { + if (bPseudoTest) { +#ifdef HAL_EFUSE_MEMORY + startAddr = (u16)pEfuseHal->fakeEfuseUsedBytes; +#else + startAddr = (u16)fakeEfuseUsedBytes; +#endif + } else + rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&startAddr); + } else { + if (bPseudoTest) { +#ifdef HAL_EFUSE_MEMORY + startAddr = (u16)pEfuseHal->fakeBTEfuseUsedBytes; +#else + startAddr = (u16)fakeBTEfuseUsedBytes; +#endif + } else + rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&startAddr); + } + startAddr %= efuse_max; + DBG_8192C("%s: startAddr=%#X\n", __func__, startAddr); + + while (1) { + if (startAddr >= efuse_max_available_len) { + bRet = _FALSE; + DBG_8192C("%s: startAddr(%d) >= efuse_max_available_len(%d)\n", + __func__, startAddr, efuse_max_available_len); + break; + } + + if (efuse_OneByteRead(padapter, startAddr, &efuse_data, bPseudoTest) && (efuse_data != 0xFF)) { +#if 1 + bRet = _FALSE; + DBG_8192C("%s: Something Wrong! last bytes(%#X=0x%02X) is not 0xFF\n", + __func__, startAddr, efuse_data); + break; +#else + if (EXT_HEADER(efuse_data)) { + cur_header = efuse_data; + startAddr++; + efuse_OneByteRead(padapter, startAddr, &efuse_data, bPseudoTest); + if (ALL_WORDS_DISABLED(efuse_data)) { + DBG_8192C("%s: Error condition, all words disabled!", __func__); + bRet = _FALSE; + break; + } else { + curPkt.offset = ((cur_header & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1); + curPkt.word_en = efuse_data & 0x0F; + } + } else { + cur_header = efuse_data; + curPkt.offset = (cur_header >> 4) & 0x0F; + curPkt.word_en = cur_header & 0x0F; + } + + curPkt.word_cnts = Efuse_CalculateWordCnts(curPkt.word_en); + /* if same header is found but no data followed */ + /* write some part of data followed by the header. */ + if ((curPkt.offset == pTargetPkt->offset) && + (hal_EfuseCheckIfDatafollowed(padapter, curPkt.word_cnts, startAddr + 1, bPseudoTest) == _FALSE) && + wordEnMatched(pTargetPkt, &curPkt, &matched_wden) == _TRUE) { + DBG_8192C("%s: Need to partial write data by the previous wrote header\n", __func__); + /* Here to write partial data */ + badworden = Efuse_WordEnableDataWrite(padapter, startAddr + 1, matched_wden, pTargetPkt->data, bPseudoTest); + if (badworden != 0x0F) { + u32 PgWriteSuccess = 0; + /* if write fail on some words, write these bad words again */ + if (efuseType == EFUSE_WIFI) + PgWriteSuccess = Efuse_PgPacketWrite(padapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest); + else + PgWriteSuccess = Efuse_PgPacketWrite_BT(padapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest); + + if (!PgWriteSuccess) { + bRet = _FALSE; /* write fail, return */ + break; + } + } + /* partial write ok, update the target packet for later use */ + for (i = 0; i < 4; i++) { + if ((matched_wden & (0x1 << i)) == 0) { /* this word has been written */ + pTargetPkt->word_en |= (0x1 << i); /* disable the word */ + } + } + pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en); + } + /* read from next header */ + startAddr = startAddr + (curPkt.word_cnts * 2) + 1; +#endif + } else { + /* not used header, 0xff */ + *pAddr = startAddr; + /*DBG_8192C("%s: Started from unused header offset=%d\n", __func__, startAddr)); */ + bRet = _TRUE; + break; + } + } + + return bRet; +} + +BOOLEAN +hal_EfuseFixHeaderProcess( + IN PADAPTER pAdapter, + IN u1Byte efuseType, + IN PPGPKT_STRUCT pFixPkt, + IN pu2Byte pAddr, + IN BOOLEAN bPseudoTest +) +{ + u1Byte originaldata[8], badworden=0; + u2Byte efuse_addr=*pAddr; + u4Byte PgWriteSuccess=0; + + _rtw_memset((PVOID)originaldata, 8, 0xff); + + if (Efuse_PgPacketRead(pAdapter, pFixPkt->offset, originaldata, bPseudoTest)) { + badworden = Hal_EfuseWordEnableDataWrite(pAdapter, efuse_addr+1, pFixPkt->word_en, originaldata, bPseudoTest); + + if (badworden != 0xf) { + + PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pFixPkt->offset, badworden, originaldata, bPseudoTest); + if (!PgWriteSuccess) + return FALSE; + else + efuse_addr = Hal_EfuseGetCurrentSize(pAdapter, efuseType, bPseudoTest); + } else { + efuse_addr = efuse_addr + (pFixPkt->word_cnts*2) +1; + } + } else { + efuse_addr = efuse_addr + (pFixPkt->word_cnts*2) +1; + } + + *pAddr = efuse_addr; + return TRUE; +} + +static u8 +hal_EfusePgPacketWrite1ByteHeader( + PADAPTER pAdapter, + u8 efuseType, + u16 *pAddr, + PPGPKT_STRUCT pTargetPkt, + u8 bPseudoTest) +{ + u8 bRet = _FALSE; + u8 pg_header = 0, tmp_header = 0; + u16 efuse_addr = *pAddr; + u8 repeatcnt = 0; + + + /* RTW_INFO("%s\n", __FUNCTION__); */ + pg_header = ((pTargetPkt->offset << 4) & 0xf0) | pTargetPkt->word_en; + if (IS_HARDWARE_TYPE_8723BE(pAdapter)) + efuse_OneByteWrite(pAdapter, 0x1FF, 00, FALSE); /* increase current */ + + efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest); + + PHY_SetMacReg(pAdapter, EFUSE_TEST, BIT26, 0); + + efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest); + + PHY_SetMacReg(pAdapter, EFUSE_TEST, BIT26, 1); + + while (tmp_header == 0xFF || pg_header != tmp_header) { + if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) { + DBG_8192C("retry %d times fail!!\n", repeatcnt); + return _FALSE; + } + efuse_OneByteWrite(pAdapter,efuse_addr, pg_header, bPseudoTest); + efuse_OneByteRead(pAdapter,efuse_addr, &tmp_header, bPseudoTest); + DBG_8192C("===>%s: Keep %d-th retrying,pg_header = 0x%X tmp_header = 0x%X\n", __FUNCTION__,repeatcnt, pg_header, tmp_header); + } + + if (pg_header == tmp_header) + bRet = _TRUE; + else { + PGPKT_STRUCT fixPkt; + + DBG_8192C(" pg_header(0x%X) != tmp_header(0x%X)\n", pg_header, tmp_header); + DBG_8192C("Error condition for fixed PG packet, need to cover the existed data: (Addr, Data) = (0x%X, 0x%X)\n", + efuse_addr, tmp_header); + fixPkt.offset = (tmp_header>>4) & 0x0F; + fixPkt.word_en = tmp_header & 0x0F; + fixPkt.word_cnts = Efuse_CalculateWordCnts(fixPkt.word_en); + if (!hal_EfuseFixHeaderProcess(pAdapter, efuseType, &fixPkt, &efuse_addr, bPseudoTest)) + return _FALSE; + } + + *pAddr = efuse_addr; + + return _TRUE; +} + +static u8 +hal_EfusePgPacketWrite2ByteHeader( + PADAPTER padapter, + u8 efuseType, + u16 *pAddr, + PPGPKT_STRUCT pTargetPkt, + u8 bPseudoTest) +{ + u16 efuse_addr, efuse_max_available_len = 0; + u8 pg_header = 0, tmp_header = 0, pg_header_temp = 0; + u8 repeatcnt = 0; + + + /* RTW_INFO("%s\n", __FUNCTION__); */ + EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &efuse_max_available_len, bPseudoTest); + + efuse_addr = *pAddr; + + if (efuse_addr >= efuse_max_available_len) { + DBG_8192C("%s: addr(%d) over avaliable(%d)!!\n", __FUNCTION__, efuse_addr, efuse_max_available_len); + return _FALSE; + } + + while (efuse_addr < efuse_max_available_len) { + pg_header = ((pTargetPkt->offset & 0x07) << 5) | 0x0F; + efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest); + PHY_SetMacReg(padapter, EFUSE_TEST, BIT26, 0); + efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest); + PHY_SetMacReg(padapter, EFUSE_TEST, BIT26, 1); + + while (tmp_header == 0xFF || pg_header != tmp_header) { + if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) { + DBG_8192C("%s, Repeat over limit for pg_header!!\n", __FUNCTION__); + return _FALSE; + } + + efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest); + efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest); + } + + /*to write ext_header*/ + if (tmp_header == pg_header) { + efuse_addr++; + pg_header_temp = pg_header; + pg_header = ((pTargetPkt->offset & 0x78) << 1) | pTargetPkt->word_en; + + efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest); + PHY_SetMacReg(padapter, EFUSE_TEST, BIT26, 0); + efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest); + PHY_SetMacReg(padapter, EFUSE_TEST, BIT26, 1); + + while (tmp_header == 0xFF || pg_header != tmp_header) { + if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) { + DBG_8192C("%s, Repeat over limit for ext_header!!\n", __FUNCTION__); + return _FALSE; + } + + efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest); + efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest); + } + + if ((tmp_header & 0x0F) == 0x0F) { + if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) { + DBG_8192C("Repeat over limit for word_en!!\n"); + return _FALSE; + } else { + efuse_addr++; + continue; + } + } else if (pg_header != tmp_header) { + PGPKT_STRUCT fixPkt; + DBG_8192C("Error, efuse_PgPacketWrite2ByteHeader(), offset PG fail, need to cover the existed data!!\n"); + DBG_8192C("Error condition for offset PG fail, need to cover the existed data\n"); + fixPkt.offset = ((pg_header_temp & 0xE0) >> 5) | ((tmp_header & 0xF0) >> 1); + fixPkt.word_en = tmp_header & 0x0F; + fixPkt.word_cnts = Efuse_CalculateWordCnts(fixPkt.word_en); + if (!hal_EfuseFixHeaderProcess(padapter, efuseType, &fixPkt, &efuse_addr, bPseudoTest)) + return _FALSE; + } else + break; + } else if ((tmp_header & 0x1F) == 0x0F) {/*wrong extended header*/ + efuse_addr += 2; + continue; + } + } + + *pAddr = efuse_addr; + + return _TRUE; +} + +static u8 +hal_EfusePgPacketWriteHeader( + PADAPTER padapter, + u8 efuseType, + u16 *pAddr, + PPGPKT_STRUCT pTargetPkt, + u8 bPseudoTest) +{ + u8 bRet = _FALSE; + + if (pTargetPkt->offset >= EFUSE_MAX_SECTION_BASE) + bRet = hal_EfusePgPacketWrite2ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest); + else + bRet = hal_EfusePgPacketWrite1ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest); + + return bRet; +} + +static u8 +hal_EfusePgPacketWriteData( + PADAPTER pAdapter, + u8 efuseType, + u16 *pAddr, + PPGPKT_STRUCT pTargetPkt, + u8 bPseudoTest) +{ + u16 efuse_addr; + u8 badworden; + u8 PgWriteSuccess = 0; + + + efuse_addr = *pAddr; + badworden = Efuse_WordEnableDataWrite(pAdapter, efuse_addr + 1, pTargetPkt->word_en, pTargetPkt->data, bPseudoTest); + if (badworden == 0x0F) { + DBG_8192C("%s: OK!!\n", __FUNCTION__); + return _TRUE; + } else { /* Reorganize other pg packet */ + DBG_8192C ("Error, efuse_PgPacketWriteData(), wirte data fail!!\n"); + DBG_8192C ("efuse_PgPacketWriteData Fail!!\n"); + PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest); + if (!PgWriteSuccess) + return FALSE; + else + return TRUE; + } + + return _TRUE; +} + +static s32 +Hal_EfusePgPacketWrite( + PADAPTER padapter, + u8 offset, + u8 word_en, + u8 *pData, + u8 bPseudoTest) +{ + PGPKT_STRUCT targetPkt; + u16 startAddr = 0; + u8 efuseType = EFUSE_WIFI; + + if (!hal_EfusePgCheckAvailableAddr(padapter, efuseType, bPseudoTest)) + return _FALSE; + + hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt); + + if (!hal_EfusePartialWriteCheck(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) + return _FALSE; + + if (!hal_EfusePgPacketWriteHeader(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) + return _FALSE; + + if (!hal_EfusePgPacketWriteData(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) + return _FALSE; + + return _TRUE; +} + +static u8 +Hal_EfusePgPacketWrite_BT( + PADAPTER pAdapter, + u8 offset, + u8 word_en, + u8 *pData, + u8 bPseudoTest) +{ + PGPKT_STRUCT targetPkt; + u16 startAddr = 0; + u8 efuseType = EFUSE_BT; + + if (!hal_EfusePgCheckAvailableAddr(pAdapter, efuseType, bPseudoTest)) + return _FALSE; + + hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt); + + if (!hal_EfusePartialWriteCheck(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) + return _FALSE; + + if (!hal_EfusePgPacketWriteHeader(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) + return _FALSE; + + if (!hal_EfusePgPacketWriteData(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) + return _FALSE; + + return _TRUE; +} + + +static void rtl8188f_read_chip_version(PADAPTER padapter) +{ + u32 value32; + HAL_DATA_TYPE *pHalData; + u8 tmpvdr; + pHalData = GET_HAL_DATA(padapter); + + value32 = rtw_read32(padapter, REG_SYS_CFG); + pHalData->VersionID.ICType = CHIP_8188F; + pHalData->VersionID.ChipType = ((value32 & RTL_ID) ? TEST_CHIP : NORMAL_CHIP); + pHalData->VersionID.RFType = RF_TYPE_1T1R; + + tmpvdr = (value32 & EXT_VENDOR_ID) >> EXT_VENDOR_ID_SHIFT; + if (tmpvdr == 0x00) + pHalData->VersionID.VendorType = CHIP_VENDOR_TSMC; + else if (tmpvdr == 0x01) + pHalData->VersionID.VendorType = CHIP_VENDOR_SMIC; + else if (tmpvdr == 0x02) + pHalData->VersionID.VendorType = CHIP_VENDOR_UMC; + + pHalData->VersionID.CUTVersion = (value32 & CHIP_VER_RTL_MASK) >> CHIP_VER_RTL_SHIFT; /* IC version (CUT) */ + + #if 0 + /* For regulator mode. by tynli. 2011.01.14 */ + pHalData->RegulatorMode = ((value32 & SPS_SEL) ? RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR); + #endif + + #if 0 + value32 = rtw_read32(padapter, REG_GPIO_OUTSTS); + pHalData->VersionID.ROMVer = ((value32 & RF_RL_ID) >> 20); /* ROM code version. */ + #endif + + #if 0 + /* For multi-function consideration. Added by Roger, 2010.10.06. */ + pHalData->MultiFunc = RT_MULTI_FUNC_NONE; + value32 = rtw_read32(padapter, REG_MULTI_FUNC_CTRL); + pHalData->MultiFunc |= ((value32 & WL_FUNC_EN) ? RT_MULTI_FUNC_WIFI : 0); + pHalData->MultiFunc |= ((value32 & BT_FUNC_EN) ? RT_MULTI_FUNC_BT : 0); + pHalData->MultiFunc |= ((value32 & GPS_FUNC_EN) ? RT_MULTI_FUNC_GPS : 0); + pHalData->PolarityCtl = ((value32 & WL_HWPDN_SL) ? RT_POLARITY_HIGH_ACT : RT_POLARITY_LOW_ACT); + #endif + + rtw_hal_config_rftype(padapter); + +#if 0 /* mark for chage to use efuse */ + if (IS_B_CUT(pHalData->VersionID) || IS_C_CUT(pHalData->VersionID)) { + MSG_8192C(" IS_B/C_CUT SWR up 1 level !!!!!!!!!!!!!!!!!\n"); + PHY_SetMacReg(padapter, 0x14, BIT23 | BIT22 | BIT21 | BIT20, 0x5); /* MAC reg 0x14[23:20] = 4b'0101 (SWR 1.220V) */ + } else if (IS_D_CUT(pHalData->VersionID)) + MSG_8192C(" IS_D_CUT SKIP SWR !!!!!!!!!!!!!!!!!\n"); +#endif /* mark for chage to use efuse */ + +#if 1 + dump_chip_info(pHalData->VersionID); +#endif + +} + + +void rtl8188f_InitBeaconParameters(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + u16 val16; + u8 val8; + + + val8 = DIS_TSF_UDT; + val16 = val8 | (val8 << 8); /* port0 and port1 */ +#ifdef CONFIG_BT_COEXIST + /* Enable prot0 beacon function for PSTDMA */ + val16 |= EN_BCN_FUNCTION; +#endif + rtw_write16(padapter, REG_BCN_CTRL, val16); + + /* TODO: Remove these magic number */ + rtw_write16(padapter, REG_TBTT_PROHIBIT, 0x6404);/* ms */ + /* Firmware will control REG_DRVERLYINT when power saving is enable, */ + /* so don't set this register on STA mode. */ + if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _FALSE) + rtw_write8(padapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME_8188F); /* 5ms */ + rtw_write8(padapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME_8188F); /* 2ms */ + + /* Suggested by designer timchen. Change beacon AIFS to the largest number */ + /* beacause test chip does not contension before sending beacon. by tynli. 2009.11.03 */ + rtw_write16(padapter, REG_BCNTCFG, 0x660F); + + pHalData->RegBcnCtrlVal = rtw_read8(padapter, REG_BCN_CTRL); + pHalData->RegTxPause = rtw_read8(padapter, REG_TXPAUSE); + pHalData->RegFwHwTxQCtrl = rtw_read8(padapter, REG_FWHW_TXQ_CTRL + 2); + pHalData->RegReg542 = rtw_read8(padapter, REG_TBTT_PROHIBIT + 2); + pHalData->RegCR_1 = rtw_read8(padapter, REG_CR + 1); +} + +void rtl8188f_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode) +{ +#ifdef CONFIG_ADHOC_WORKAROUND_SETTING + rtw_write8(padapter, REG_BCN_MAX_ERR, 0xFF); +#else + /*rtw_write8(Adapter, REG_BCN_MAX_ERR, (InfraMode ? 0xFF : 0x10)); */ +#endif +} + +void _InitBurstPktLen_8188FS(PADAPTER Adapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + rtw_write8(Adapter, 0x4c7, rtw_read8(Adapter, 0x4c7) | BIT(7)); /*enable single pkt ampdu */ + rtw_write8(Adapter, REG_RX_PKT_LIMIT_8188F, 0x18); /*for VHT packet length 11K */ + rtw_write8(Adapter, REG_MAX_AGGR_NUM_8188F, 0x1F); + rtw_write8(Adapter, REG_PIFS_8188F, 0x00); + rtw_write8(Adapter, REG_FWHW_TXQ_CTRL_8188F, rtw_read8(Adapter, REG_FWHW_TXQ_CTRL) & (~BIT(7))); + if (pHalData->AMPDUBurstMode) + rtw_write8(Adapter, REG_AMPDU_BURST_MODE_8188F, 0x5F); + rtw_write8(Adapter, REG_AMPDU_MAX_TIME_8188F, 0x70); + + /* ARFB table 9 for 11ac 5G 2SS */ + rtw_write32(Adapter, REG_ARFR0_8188F, 0x00000010); + if (IS_NORMAL_CHIP(pHalData->VersionID)) + rtw_write32(Adapter, REG_ARFR0_8188F + 4, 0xfffff000); + else + rtw_write32(Adapter, REG_ARFR0_8188F + 4, 0x3e0ff000); + + /* ARFB table 10 for 11ac 5G 1SS */ + rtw_write32(Adapter, REG_ARFR1_8188F, 0x00000010); + rtw_write32(Adapter, REG_ARFR1_8188F + 4, 0x003ff000); +} + +static void ResumeTxBeacon(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + + + /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */ + /* which should be read from register to a global variable. */ + + RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+ResumeTxBeacon\n")); + + pHalData->RegFwHwTxQCtrl |= BIT(6); + rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, pHalData->RegFwHwTxQCtrl); + rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, 0xff); + pHalData->RegReg542 |= BIT(0); + rtw_write8(padapter, REG_TBTT_PROHIBIT + 2, pHalData->RegReg542); +} + +static void StopTxBeacon(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + + + /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */ + /* which should be read from register to a global variable. */ + + RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+StopTxBeacon\n")); + + pHalData->RegFwHwTxQCtrl &= ~BIT(6); + rtw_write8(padapter, REG_FWHW_TXQ_CTRL + 2, pHalData->RegFwHwTxQCtrl); + rtw_write8(padapter, REG_TBTT_PROHIBIT + 1, 0x64); + pHalData->RegReg542 &= ~BIT(0); + rtw_write8(padapter, REG_TBTT_PROHIBIT + 2, pHalData->RegReg542); + + CheckFwRsvdPageContent(padapter); /* 2010.06.23. Added by tynli. */ +} + +static void _BeaconFunctionEnable(PADAPTER padapter, u8 Enable, u8 Linked) +{ + rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB); + rtw_write8(padapter, REG_RD_CTRL + 1, 0x6F); +} + +static void rtl8188f_SetBeaconRelatedRegisters(PADAPTER padapter) +{ + u8 val8; + u32 value32; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + u32 bcn_ctrl_reg; + + /*reset TSF, enable update TSF, correcting TSF On Beacon */ + + /*REG_BCN_INTERVAL */ + /*REG_BCNDMATIM */ + /*REG_ATIMWND */ + /*REG_TBTT_PROHIBIT */ + /*REG_DRVERLYINT */ + /*REG_BCN_MAX_ERR */ + /*REG_BCNTCFG //(0x510) */ + /*REG_DUAL_TSF_RST */ + /*REG_BCN_CTRL //(0x550) */ + + + bcn_ctrl_reg = REG_BCN_CTRL; +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->iface_type == IFACE_PORT1) + bcn_ctrl_reg = REG_BCN_CTRL_1; +#endif + + /* */ + /* ATIM window */ + /* */ + rtw_write16(padapter, REG_ATIMWND, 2); + + /* */ + /* Beacon interval (in unit of TU). */ + /* */ + rtw_write16(padapter, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval); + + rtl8188f_InitBeaconParameters(padapter); + + rtw_write8(padapter, REG_SLOT, 0x09); + + /* */ + /* Reset TSF Timer to zero, added by Roger. 2008.06.24 */ + /* */ + value32 = rtw_read32(padapter, REG_TCR); + value32 &= ~TSFRST; + rtw_write32(padapter, REG_TCR, value32); + + value32 |= TSFRST; + rtw_write32(padapter, REG_TCR, value32); + + /* NOTE: Fix test chip's bug (about contention windows's randomness) */ + if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE | WIFI_AP_STATE) == _TRUE) { + rtw_write8(padapter, REG_RXTSF_OFFSET_CCK, 0x50); + rtw_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50); + } + + _BeaconFunctionEnable(padapter, _TRUE, _TRUE); + + ResumeTxBeacon(padapter); + val8 = rtw_read8(padapter, bcn_ctrl_reg); + val8 |= DIS_BCNQ_SUB; + rtw_write8(padapter, bcn_ctrl_reg, val8); +} + +void hal_notch_filter_8188f(_adapter *adapter, bool enable) +{ + if (enable) { + DBG_871X("Enable notch filter\n"); + rtw_write8(adapter, rOFDM0_RxDSP + 1, rtw_read8(adapter, rOFDM0_RxDSP + 1) | BIT1); + } else { + DBG_871X("Disable notch filter\n"); + rtw_write8(adapter, rOFDM0_RxDSP + 1, rtw_read8(adapter, rOFDM0_RxDSP + 1) & ~BIT1); + } +} + +u8 rtl8188f_MRateIdxToARFRId(PADAPTER padapter, u8 rate_idx) +{ + u8 ret = 0; + RT_RF_TYPE_DEF_E rftype = (RT_RF_TYPE_DEF_E)GET_RF_TYPE(padapter); + switch (rate_idx) { + + case RATR_INX_WIRELESS_NGB: + if (rftype == RF_1T1R) + ret = 1; + else + ret = 0; + break; + + case RATR_INX_WIRELESS_N: + case RATR_INX_WIRELESS_NG: + if (rftype == RF_1T1R) + ret = 5; + else + ret = 4; + break; + + case RATR_INX_WIRELESS_NB: + if (rftype == RF_1T1R) + ret = 3; + else + ret = 2; + break; + + case RATR_INX_WIRELESS_GB: + ret = 6; + break; + + case RATR_INX_WIRELESS_G: + ret = 7; + break; + + case RATR_INX_WIRELESS_B: + ret = 8; + break; + + case RATR_INX_WIRELESS_MC: + if (padapter->mlmeextpriv.cur_wireless_mode & WIRELESS_11BG_24N) + ret = 6; + else + ret = 7; + break; + case RATR_INX_WIRELESS_AC_N: + if (rftype == RF_1T1R) /* || padapter->MgntInfo.VHTHighestOperaRate <= MGN_VHT1SS_MCS9) */ + ret = 10; + else + ret = 9; + break; + + default: + ret = 0; + break; + } + + return ret; +} + +void UpdateHalRAMask8188F(PADAPTER padapter, u32 mac_id, u8 rssi_level) +{ + u32 mask, rate_bitmap; + u8 shortGIrate = _FALSE; + struct sta_info *psta = NULL; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct macid_ctl_t *macid_ctl = &padapter->dvobj->macid_ctl; + + if (mac_id < macid_ctl->num) + psta = macid_ctl->sta[mac_id]; + if (psta == NULL) { + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" macid:%u, sta is NULL\n" + , FUNC_ADPT_ARG(padapter), mac_id); + return; + } + + shortGIrate = query_ra_short_GI(psta); + + mask = psta->ra_mask; + + rate_bitmap = 0xffffffff; + rate_bitmap = ODM_Get_Rate_Bitmap(&pHalData->odmpriv, mac_id, mask, rssi_level); + DBG_871X("%s => mac_id:%d, networkType:0x%02x, mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n", + __func__, mac_id, psta->wireless_mode, mask, rssi_level, rate_bitmap); + + mask &= rate_bitmap; + +#ifdef CONFIG_BT_COEXIST + rate_bitmap = rtw_btcoex_GetRaMask(padapter); + mask &= ~rate_bitmap; +#endif /* CONFIG_BT_COEXIST */ + +#ifdef CONFIG_CMCC_TEST +#ifdef CONFIG_BT_COEXIST + if (pmlmeext->cur_wireless_mode & WIRELESS_11G) { + if (mac_id == 0) { + DBG_871X("CMCC_BT update raid entry, mask=0x%x\n", mask); + /*mask &=0xffffffc0; //disable CCK & <12M OFDM rate for 11G mode for CMCC */ + mask &= 0xffffff00; /*disable CCK & <24M OFDM rate for 11G mode for CMCC */ + DBG_871X("CMCC_BT update raid entry, mask=0x%x\n", mask); + } + } +#endif +#endif + + if (pHalData->fw_ractrl == _TRUE) + rtl8188f_set_FwMacIdConfig_cmd(padapter, mac_id, psta->raid, psta->bw_mode, shortGIrate, mask); + + /*set correct initial date rate for each mac_id */ + pHalData->INIDATA_RATE[mac_id] = psta->init_rate; + DBG_871X("%s(): mac_id=%d raid=0x%x bw=%d mask=0x%x init_rate=0x%x\n", __func__, mac_id, psta->raid, psta->bw_mode, mask, psta->init_rate); +} + +/* */ +/* Description: In normal chip, we should send some packet to Hw which will be used by Fw */ +/* in FW LPS mode. The function is to fill the Tx descriptor of this packets, then */ +/* Fw can tell Hw to send these packet derectly. */ +/* Added by tynli. 2009.10.15. */ +/* */ +/*type1:pspoll, type2:null */ +void rtl8188f_fill_fake_txdesc( + PADAPTER padapter, + u8 *pDesc, + u32 BufferLen, + u8 IsPsPoll, + u8 IsBTQosNull, + u8 bDataFrame) +{ + /* Clear all status */ + _rtw_memset(pDesc, 0, TXDESC_SIZE); + + SET_TX_DESC_FIRST_SEG_8188F(pDesc, 1); /*bFirstSeg; */ + SET_TX_DESC_LAST_SEG_8188F(pDesc, 1); /*bLastSeg; */ + + SET_TX_DESC_OFFSET_8188F(pDesc, 0x28); /* Offset = 32 */ + + SET_TX_DESC_PKT_SIZE_8188F(pDesc, BufferLen); /* Buffer size + command header */ + SET_TX_DESC_QUEUE_SEL_8188F(pDesc, QSLT_MGNT); /* Fixed queue of Mgnt queue */ + + /* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by Hw. */ + if (_TRUE == IsPsPoll) { + /* Nothing */ + SET_TX_DESC_NAV_USE_HDR_8188F(pDesc, 1); + } else { + SET_TX_DESC_HWSEQ_EN_8188F(pDesc, 1); /* Hw set sequence number */ + SET_TX_DESC_HWSEQ_SEL_8188F(pDesc, 0); + } + + if (_TRUE == IsBTQosNull) + SET_TX_DESC_BT_INT_8188F(pDesc, 1); + + SET_TX_DESC_USE_RATE_8188F(pDesc, 1); /* use data rate which is set by Sw */ + SET_TX_DESC_OWN_8188F((pu1Byte)pDesc, 1); + + SET_TX_DESC_TX_RATE_8188F(pDesc, DESC8188F_RATE1M); + + /* */ + /* Encrypt the data frame if under security mode excepct null data. Suggested by CCW. */ + /* */ + if (_TRUE == bDataFrame) { + u32 EncAlg; + + EncAlg = padapter->securitypriv.dot11PrivacyAlgrthm; + switch (EncAlg) { + case _NO_PRIVACY_: + SET_TX_DESC_SEC_TYPE_8188F(pDesc, 0x0); + break; + case _WEP40_: + case _WEP104_: + case _TKIP_: + SET_TX_DESC_SEC_TYPE_8188F(pDesc, 0x1); + break; + case _SMS4_: + SET_TX_DESC_SEC_TYPE_8188F(pDesc, 0x2); + break; + case _AES_: + SET_TX_DESC_SEC_TYPE_8188F(pDesc, 0x3); + break; + default: + SET_TX_DESC_SEC_TYPE_8188F(pDesc, 0x0); + break; + } + } + +#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + /* USB interface drop packet if the checksum of descriptor isn't correct. */ + /* Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.). */ + rtl8188f_cal_txdesc_chksum((struct tx_desc *)pDesc); +#endif +} + +void rtl8188f_set_hal_ops(struct hal_ops *pHalFunc) +{ + pHalFunc->dm_init = &rtl8188f_init_dm_priv; + pHalFunc->dm_deinit = &rtl8188f_deinit_dm_priv; + + pHalFunc->read_chip_version = &rtl8188f_read_chip_version; + + pHalFunc->UpdateRAMaskHandler = &UpdateHalRAMask8188F; + pHalFunc->set_bwmode_handler = &PHY_SetBWMode8188F; + pHalFunc->set_channel_handler = &PHY_SwChnl8188F; + pHalFunc->set_chnl_bw_handler = &PHY_SetSwChnlBWMode8188F; + + pHalFunc->set_tx_power_level_handler = &PHY_SetTxPowerLevel8188F; + pHalFunc->get_tx_power_level_handler = &PHY_GetTxPowerLevel8188F; + + pHalFunc->hal_dm_watchdog = &rtl8188f_HalDmWatchDog; +#ifdef CONFIG_LPS_LCLK_WD_TIMER + pHalFunc->hal_dm_watchdog_in_lps = &rtl8188f_HalDmWatchDog_in_LPS; +#endif /* CONFIG_LPS_LCLK_WD_TIMER */ + +#ifdef CONFIG_C2H_PACKET_EN + pHalFunc->SetHwRegHandlerWithBuf = &SetHwRegWithBuf8188F; +#endif /* CONFIG_C2H_PACKET_EN */ + + pHalFunc->SetBeaconRelatedRegistersHandler = &rtl8188f_SetBeaconRelatedRegisters; + + pHalFunc->Add_RateATid = &rtl8188f_Add_RateATid; + + pHalFunc->run_thread = &rtl8188f_start_thread; + pHalFunc->cancel_thread = &rtl8188f_stop_thread; + + pHalFunc->read_bbreg = &PHY_QueryBBReg_8188F; + pHalFunc->write_bbreg = &PHY_SetBBReg_8188F; + pHalFunc->read_rfreg = &PHY_QueryRFReg_8188F; + pHalFunc->write_rfreg = &PHY_SetRFReg_8188F; + + /* Efuse related function */ + pHalFunc->BTEfusePowerSwitch = &Hal_BT_EfusePowerSwitch; + pHalFunc->EfusePowerSwitch = &Hal_EfusePowerSwitch; + pHalFunc->ReadEFuse = &Hal_ReadEFuse; + pHalFunc->EFUSEGetEfuseDefinition = &Hal_GetEfuseDefinition; + pHalFunc->EfuseGetCurrentSize = &Hal_EfuseGetCurrentSize; + pHalFunc->Efuse_PgPacketRead = &Hal_EfusePgPacketRead; + pHalFunc->Efuse_PgPacketWrite = &Hal_EfusePgPacketWrite; + pHalFunc->Efuse_WordEnableDataWrite = &Hal_EfuseWordEnableDataWrite; + pHalFunc->Efuse_PgPacketWrite_BT = &Hal_EfusePgPacketWrite_BT; + +#ifdef DBG_CONFIG_ERROR_DETECT + pHalFunc->sreset_init_value = &sreset_init_value; + pHalFunc->sreset_reset_value = &sreset_reset_value; + pHalFunc->silentreset = &sreset_reset; + pHalFunc->sreset_xmit_status_check = &rtl8188f_sreset_xmit_status_check; + pHalFunc->sreset_linked_status_check = &rtl8188f_sreset_linked_status_check; + pHalFunc->sreset_get_wifi_status = &sreset_get_wifi_status; + pHalFunc->sreset_inprogress = &sreset_inprogress; +#endif + pHalFunc->GetHalODMVarHandler = GetHalODMVar; + pHalFunc->SetHalODMVarHandler = SetHalODMVar; + +#ifdef CONFIG_XMIT_THREAD_MODE + pHalFunc->xmit_thread_handler = &hal_xmit_handler; +#endif + pHalFunc->hal_notch_filter = &hal_notch_filter_8188f; + + pHalFunc->c2h_handler = c2h_handler_8188f; + pHalFunc->c2h_id_filter_ccx = c2h_id_filter_ccx_8188f; + + pHalFunc->fill_h2c_cmd = &FillH2CCmd8188F; + pHalFunc->fill_fake_txdesc = &rtl8188f_fill_fake_txdesc; + pHalFunc->fw_dl = &rtl8188f_FirmwareDownload; + pHalFunc->hal_get_tx_buff_rsvd_page_num = &GetTxBufferRsvdPageNum8188F; +} + +void rtl8188f_InitAntenna_Selection(PADAPTER padapter) +{ +#ifdef CONFIG_ANTENNA_DIVERSITY + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + if (pHalData->AntDivCfg == 0) + return; + + /* LED(GPIO4) disable for AntDiv */ + PHY_SetMacReg(padapter, 0x4C, BIT21, 0x0); +#endif +} + +void rtl8188f_CheckAntenna_Selection(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData; + u8 val; + + + pHalData = GET_HAL_DATA(padapter); + + val = rtw_read8(padapter, REG_LEDCFG2); + /* Let 8051 take control antenna stetting */ + if (!(val & BIT(7))) { + val |= BIT(7); /* DPDT_SEL_EN, 0x4C[23] */ + rtw_write8(padapter, REG_LEDCFG2, val); + } +} +void rtl8188f_DeinitAntenna_Selection(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData; + u8 val; + + + pHalData = GET_HAL_DATA(padapter); + val = rtw_read8(padapter, REG_LEDCFG2); + /* Let 8051 take control antenna stetting */ + val &= ~BIT(7); /* DPDT_SEL_EN, clear 0x4C[23] */ + rtw_write8(padapter, REG_LEDCFG2, val); + +} + +void init_hal_spec_8188f(_adapter *adapter) +{ + struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter); + + hal_spec->ic_name = "rtl8188f"; + hal_spec->macid_num = MACID_NUM_8188F; + hal_spec->sec_cam_ent_num = SEC_CAM_ENT_NUM_8188F; + hal_spec->sec_cap = 0; + hal_spec->nss_num = NSS_NUM_8188F; + hal_spec->band_cap = BAND_CAP_8188F; + hal_spec->bw_cap = BW_CAP_8188F; + hal_spec->proto_cap = PROTO_CAP_8188F; + + hal_spec->wl_func = 0 + | WL_FUNC_P2P + | WL_FUNC_MIRACAST + | WL_FUNC_TDLS + ; +} + +void rtl8188f_init_default_value(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData; + u8 i; + pHalData = GET_HAL_DATA(padapter); + + /* init default value */ + pHalData->fw_ractrl = _FALSE; + if (!adapter_to_pwrctl(padapter)->bkeepfwalive) + pHalData->LastHMEBoxNum = 0; + + padapter->registrypriv.wireless_mode = WIRELESS_11BG_24N; + + /*init phydm default value */ + pHalData->bIQKInitialized = _FALSE; + pHalData->odmpriv.RFCalibrateInfo.TM_Trigger = 0;/*for IQK */ + pHalData->odmpriv.RFCalibrateInfo.ThermalValue_HP_index = 0; + for (i = 0; i < HP_THERMAL_NUM; i++) + pHalData->odmpriv.RFCalibrateInfo.ThermalValue_HP[i] = 0; + +#if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI) + pHalData->IntrMask[0] = (u32)( + /* IMR_ROK | */ + /* IMR_RDU | */ + /* IMR_VODOK | */ + /* IMR_VIDOK | */ + /* IMR_BEDOK | */ + /* IMR_BKDOK | */ + /* IMR_MGNTDOK | */ + /* IMR_HIGHDOK | */ + /* IMR_CPWM | */ + /* IMR_CPWM2 | */ + /* IMR_C2HCMD | */ + /* IMR_HISR1_IND_INT | */ + /* IMR_ATIMEND | */ + /* IMR_BCNDMAINT_E | */ + /* IMR_HSISR_IND_ON_INT | */ + /* IMR_BCNDOK0 | */ + /* IMR_BCNDMAINT0 | */ + /* IMR_TSF_BIT32_TOGGLE | */ + /* IMR_TXBCN0OK | */ + /* IMR_TXBCN0ERR | */ + /* IMR_GTINT3 | */ + /* IMR_GTINT4 | */ + /* IMR_TXCCK | */ + 0); + + pHalData->IntrMask[1] = (u32)( + /* IMR_RXFOVW | */ + /* IMR_TXFOVW | */ + /* IMR_RXERR | */ + /* IMR_TXERR | */ + /* IMR_ATIMEND_E | */ + /* IMR_BCNDOK1 | */ + /* IMR_BCNDOK2 | */ + /* IMR_BCNDOK3 | */ + /* IMR_BCNDOK4 | */ + /* IMR_BCNDOK5 | */ + /* IMR_BCNDOK6 | */ + /* IMR_BCNDOK7 | */ + /* IMR_BCNDMAINT1 | */ + /* IMR_BCNDMAINT2 | */ + /* IMR_BCNDMAINT3 | */ + /* IMR_BCNDMAINT4 | */ + /* IMR_BCNDMAINT5 | */ + /* IMR_BCNDMAINT6 | */ + /* IMR_BCNDMAINT7 | */ + 0); +#endif + + /* init Efuse variables */ + pHalData->EfuseUsedBytes = 0; + pHalData->EfuseUsedPercentage = 0; +#ifdef HAL_EFUSE_MEMORY + pHalData->EfuseHal.fakeEfuseBank = 0; + pHalData->EfuseHal.fakeEfuseUsedBytes = 0; + _rtw_memset(pHalData->EfuseHal.fakeEfuseContent, 0xFF, EFUSE_MAX_HW_SIZE); + _rtw_memset(pHalData->EfuseHal.fakeEfuseInitMap, 0xFF, EFUSE_MAX_MAP_LEN); + _rtw_memset(pHalData->EfuseHal.fakeEfuseModifiedMap, 0xFF, EFUSE_MAX_MAP_LEN); + pHalData->EfuseHal.BTEfuseUsedBytes = 0; + pHalData->EfuseHal.BTEfuseUsedPercentage = 0; + _rtw_memset(pHalData->EfuseHal.BTEfuseContent, 0xFF, EFUSE_MAX_BT_BANK * EFUSE_MAX_HW_SIZE); + _rtw_memset(pHalData->EfuseHal.BTEfuseInitMap, 0xFF, EFUSE_BT_MAX_MAP_LEN); + _rtw_memset(pHalData->EfuseHal.BTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN); + pHalData->EfuseHal.fakeBTEfuseUsedBytes = 0; + _rtw_memset(pHalData->EfuseHal.fakeBTEfuseContent, 0xFF, EFUSE_MAX_BT_BANK * EFUSE_MAX_HW_SIZE); + _rtw_memset(pHalData->EfuseHal.fakeBTEfuseInitMap, 0xFF, EFUSE_BT_MAX_MAP_LEN); + _rtw_memset(pHalData->EfuseHal.fakeBTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN); +#endif +} + +u8 GetEEPROMSize8188F(PADAPTER padapter) +{ + u8 size = 0; + u32 cr; + + cr = rtw_read16(padapter, REG_9346CR); + /* 6: EEPROM used is 93C46, 4: boot from E-Fuse. */ + size = (cr & BOOT_FROM_EEPROM) ? 6 : 4; + + MSG_8192C("EEPROM type is %s\n", size == 4 ? "E-FUSE" : "93C46"); + + return size; +} + +/*------------------------------------------------------------------------- */ +/* */ +/* LLT R/W/Init function */ +/* */ +/*------------------------------------------------------------------------- */ +s32 rtl8188f_InitLLTTable(PADAPTER padapter) +{ + u32 start, passing_time; + u32 val32; + s32 ret; + + + ret = _FAIL; + + val32 = rtw_read32(padapter, REG_AUTO_LLT); + val32 |= BIT_AUTO_INIT_LLT; + rtw_write32(padapter, REG_AUTO_LLT, val32); + + start = rtw_get_current_time(); + + do { + val32 = rtw_read32(padapter, REG_AUTO_LLT); + if (!(val32 & BIT_AUTO_INIT_LLT)) { + ret = _SUCCESS; + break; + } + + passing_time = rtw_get_passing_time_ms(start); + if (passing_time > 1000) { + DBG_8192C("%s: FAIL!! REG_AUTO_LLT(0x%X)=%08x\n", + __func__, REG_AUTO_LLT, val32); + break; + } + + rtw_usleep_os(2); + } while (1); + + return ret; +} + +#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) +void _DisableGPIO(PADAPTER padapter) +{ + /* + * j. GPIO_PIN_CTRL 0x44[31:0]=0x000 + * k.Value = GPIO_PIN_CTRL[7:0] + * l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write external PIN level + * m. GPIO_MUXCFG 0x42 [15:0] = 0x0780 + * n. LEDCFG 0x4C[15:0] = 0x8080 + */ + u8 value8; + u16 value16; + u32 value32; + u32 u4bTmp; + + + /*1. Disable GPIO[7:0] */ + rtw_write16(padapter, REG_GPIO_PIN_CTRL + 2, 0x0000); + value32 = rtw_read32(padapter, REG_GPIO_PIN_CTRL) & 0xFFFF00FF; + u4bTmp = value32 & 0x000000FF; + value32 |= ((u4bTmp << 8) | 0x00FF0000); + rtw_write32(padapter, REG_GPIO_PIN_CTRL, value32); + + + /*2. Disable GPIO[10:8] */ + rtw_write8(padapter, REG_MAC_PINMUX_CFG, 0x00); + value16 = rtw_read16(padapter, REG_GPIO_IO_SEL) & 0xFF0F; + value8 = (u8)(value16 & 0x000F); + value16 |= ((value8 << 4) | 0x0780); + rtw_write16(padapter, REG_GPIO_IO_SEL, value16); + + + /*3. Disable LED0 & 1 */ + rtw_write16(padapter, REG_LEDCFG0, 0x8080); + + /*RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Disable GPIO and LED.\n")); */ +} /*end of _DisableGPIO() */ + +void _DisableRFAFEAndResetBB8188F(PADAPTER padapter) +{ + /* + * a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue + * b. RF path 0 offset 0x00 = 0x00 disable RF + * c. APSD_CTRL 0x600[7:0] = 0x40 + * d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine + * e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine + */ + u8 eRFPath = 0, value8 = 0; + + rtw_write8(padapter, REG_TXPAUSE, 0xFF); + + PHY_SetRFReg(padapter, (RF_PATH)eRFPath, 0x0, bMaskByte0, 0x0); + + value8 |= APSDOFF; + rtw_write8(padapter, REG_APSD_CTRL, value8);/*0x40 */ + + /* Set BB reset at first */ + value8 = 0; + value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn); + rtw_write8(padapter, REG_SYS_FUNC_EN, value8); /*0x16 */ + + /* Set global reset. */ + value8 &= ~FEN_BB_GLB_RSTn; + rtw_write8(padapter, REG_SYS_FUNC_EN, value8); /*0x14 */ + + /* 2010/08/12 MH We need to set BB/GLBAL reset to save power for SS mode. */ + + /*RT_TRACE(COMP_INIT, DBG_LOUD, ("======> RF off and reset BB.\n")); */ +} + +void _DisableRFAFEAndResetBB(PADAPTER padapter) +{ + _DisableRFAFEAndResetBB8188F(padapter); +} + +void _ResetDigitalProcedure1_8188F(PADAPTER padapter, BOOLEAN bWithoutHWSM) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + if (IS_FW_81xxC(padapter) && (pHalData->FirmwareVersion <= 0x20)) { +#if 0 + /* + * f. SYS_FUNC_EN 0x03[7:0]=0x54 reset MAC register, DCORE + * g. MCUFWDL 0x80[7:0]=0 reset MCU ready status + */ + u32 value32 = 0; + + rtw_write8(padapter, REG_SYS_FUNC_EN + 1, 0x54); + rtw_write8(padapter, REG_MCUFWDL, 0); +#else + /* + * f. MCUFWDL 0x80[7:0]=0 reset MCU ready status + * g. SYS_FUNC_EN 0x02[10]= 0 reset MCU register, (8051 reset) + * h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC register, DCORE + * i. SYS_FUNC_EN 0x02[10]= 1 enable MCU register, (8051 enable) + */ + u16 valu16 = 0; + + rtw_write8(padapter, REG_MCUFWDL, 0); + + valu16 = rtw_read16(padapter, REG_SYS_FUNC_EN); + rtw_write16(padapter, REG_SYS_FUNC_EN, (valu16 & (~FEN_CPUEN)));/*reset MCU ,8051 */ + + valu16 = rtw_read16(padapter, REG_SYS_FUNC_EN) & 0x0FFF; + rtw_write16(padapter, REG_SYS_FUNC_EN, (valu16 | (FEN_HWPDN | FEN_ELDR))); /*reset MAC */ + + valu16 = rtw_read16(padapter, REG_SYS_FUNC_EN); + rtw_write16(padapter, REG_SYS_FUNC_EN, (valu16 | FEN_CPUEN));/*enable MCU ,8051 */ +#endif + } else { + u8 retry_cnts = 0; + + /* 2010/08/12 MH For USB SS, we can not stop 8051 when we are trying to */ + /* enter IPS/HW&SW radio off. For S3/S4/S5/Disable, we can stop 8051 because */ + /* we will init FW when power on again. */ + /*if(!pDevice->RegUsbSS) */ + { + /* If we want to SS mode, we can not reset 8051. */ + if (rtw_read8(padapter, REG_MCUFWDL) & BIT1) { + /*IF fw in RAM code, do reset */ + + + if (padapter->bFWReady) { + /* 2010/08/25 MH According to RD alfred's suggestion, we need to disable other */ + /* HRCV INT to influence 8051 reset. */ + rtw_write8(padapter, REG_FWIMR, 0x20); + /* 2011/02/15 MH According to Alex's suggestion, close mask to prevent incorrect FW write operation. */ + rtw_write8(padapter, REG_FTIMR, 0x00); + rtw_write8(padapter, REG_FSIMR, 0x00); + + rtw_write8(padapter, REG_HMETFR + 3, 0x20); /*8051 reset by self */ + + while ((retry_cnts++ < 100) && (FEN_CPUEN & rtw_read16(padapter, REG_SYS_FUNC_EN))) { + rtw_udelay_os(50);/*us */ + /* 2010/08/25 For test only We keep on reset 5051 to prevent fail. */ + /*rtw_write8(padapter, REG_HMETFR+3, 0x20);//8051 reset by self */ + } + /*RT_ASSERT((retry_cnts < 100), ("8051 reset failed!\n")); */ + + if (retry_cnts >= 100) { + /* if 8051 reset fail we trigger GPIO 0 for LA */ + /*rtw_write32( padapter, */ + /* REG_GPIO_PIN_CTRL, */ + /* 0x00010100); */ + /* 2010/08/31 MH According to Filen's info, if 8051 reset fail, reset MAC directly. */ + rtw_write8(padapter, REG_SYS_FUNC_EN + 1, 0x50); /*Reset MAC and Enable 8051 */ + rtw_mdelay_os(10); + } + /*else */ + /* RT_TRACE(COMP_INIT, DBG_LOUD, ("=====> 8051 reset success (%d) .\n",retry_cnts)); */ + } + } + /*else */ + /*{ */ + /* RT_TRACE(COMP_INIT, DBG_LOUD, ("=====> 8051 in ROM.\n")); */ + /*} */ + rtw_write8(padapter, REG_SYS_FUNC_EN + 1, 0x54); /*Reset MAC and Enable 8051 */ + rtw_write8(padapter, REG_MCUFWDL, 0); + } + } + + /*if(pDevice->RegUsbSS) */ + /*bWithoutHWSM = TRUE; // Sugest by Filen and Issau. */ + + if (bWithoutHWSM) { + /*HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); */ + /* + * Without HW auto state machine + * SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock + * h. AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL + * i. AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK + * j. SYS_ISO_CTRL 0x00[7:0] = 0xF9 isolated digital to PON + */ + /*rtw_write16(padapter, REG_SYS_CLKR, 0x30A3); */ + /*if(!pDevice->RegUsbSS) */ + /* 2011/01/26 MH SD4 Scott suggest to fix UNC-B cut bug. */ + rtw_write16(padapter, REG_SYS_CLKR, 0x70A3); /*modify to 0x70A3 by Scott. */ + rtw_write8(padapter, REG_AFE_PLL_CTRL, 0x80); + rtw_write16(padapter, REG_AFE_XTAL_CTRL, 0x880F); + /*if(!pDevice->RegUsbSS) */ + rtw_write8(padapter, REG_SYS_ISO_CTRL, 0xF9); + } else { + /* Disable all RF/BB power */ + rtw_write8(padapter, REG_RF_CTRL, 0x00); + } + /*RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Reset Digital.\n")); */ + +} + +void _ResetDigitalProcedure1(PADAPTER padapter, BOOLEAN bWithoutHWSM) +{ + _ResetDigitalProcedure1_8188F(padapter, bWithoutHWSM); +} + +void _ResetDigitalProcedure2(PADAPTER padapter) +{ + /*HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); */ + /* + * k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction + * l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock + * m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON + */ + /*rtw_write8(padapter, REG_SYS_FUNC_EN+1, 0x44); //marked by Scott. */ + /* 2011/01/26 MH SD4 Scott suggest to fix UNC-B cut bug. */ + rtw_write16(padapter, REG_SYS_CLKR, 0x70a3); /*modify to 0x70a3 by Scott. */ + rtw_write8(padapter, REG_SYS_ISO_CTRL + 1, 0x82); /*modify to 0x82 by Scott. */ +} + +void _DisableAnalog(PADAPTER padapter, BOOLEAN bWithoutHWSM) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u16 value16 = 0; + u8 value8 = 0; + + + if (bWithoutHWSM) { + /* + * n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power + * o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power + * r. When driver call disable, the ASIC will turn off remaining clock automatically + */ + + rtw_write8(padapter, REG_LDOA15_CTRL, 0x04); + /*rtw_write8(padapter, REG_LDOV12D_CTRL, 0x54); */ + + value8 = rtw_read8(padapter, REG_LDOV12D_CTRL); + value8 &= (~LDV12_EN); + rtw_write8(padapter, REG_LDOV12D_CTRL, value8); + /*RT_TRACE(COMP_INIT, DBG_LOUD, (" REG_LDOV12D_CTRL Reg0x21:0x%02x.\n",value8)); */ + } + + /* + * h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode + * i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend + */ + value8 = 0x23; + + rtw_write8(padapter, REG_SPS0_CTRL, value8); + + if (bWithoutHWSM) { + /*value16 |= (APDM_HOST | PFM_ALDN); */ + /* 2010/08/31 According to Filen description, we need to use HW to shut down 8051 automatically. */ + /* Because suspend operation need the asistance of 8051 to wait for 3ms. */ + value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN); + } else + value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN); + + rtw_write16(padapter, REG_APS_FSMCO, value16);/*0x4802 */ + + rtw_write8(padapter, REG_RSV_CTRL, 0x0e); + +#if 0 + /*tynli_test for suspend mode. */ + if (!bWithoutHWSM) + rtw_write8(padapter, 0xfe10, 0x19); +#endif + + /*RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Disable Analog Reg0x04:0x%04x.\n",value16)); */ +} + +/* HW Auto state machine */ +s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU) +{ + int rtStatus = _SUCCESS; + + + if (RTW_CANNOT_RUN(padapter)) + return rtStatus; + /*==== RF Off Sequence ==== */ + _DisableRFAFEAndResetBB(padapter); + + /* ==== Reset digital sequence ====== */ + _ResetDigitalProcedure1(padapter, _FALSE); + + /* ==== Pull GPIO PIN to balance level and LED control ====== */ + _DisableGPIO(padapter); + + /* ==== Disable analog sequence === */ + _DisableAnalog(padapter, _FALSE); + + RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("======> Card disable finished.\n")); + + return rtStatus; +} + +/* without HW Auto state machine */ +s32 CardDisableWithoutHWSM(PADAPTER padapter) +{ + s32 rtStatus = _SUCCESS; + + + /*RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Card Disable Without HWSM .\n")); */ + if (RTW_CANNOT_RUN(padapter)) + return rtStatus; + + /*==== RF Off Sequence ==== */ + _DisableRFAFEAndResetBB(padapter); + + /* ==== Reset digital sequence ====== */ + _ResetDigitalProcedure1(padapter, _TRUE); + + /* ==== Pull GPIO PIN to balance level and LED control ====== */ + _DisableGPIO(padapter); + + /* ==== Reset digital sequence ====== */ + _ResetDigitalProcedure2(padapter); + + /* ==== Disable analog sequence === */ + _DisableAnalog(padapter, _TRUE); + + /*RT_TRACE(COMP_INIT, DBG_LOUD, ("<====== Card Disable Without HWSM .\n")); */ + return rtStatus; +} +#endif /* CONFIG_USB_HCI || CONFIG_SDIO_HCI || CONFIG_GSPI_HCI */ + +BOOLEAN +Hal_GetChnlGroup8188F( + IN u8 Channel, + OUT u8 *pGroup +) +{ + BOOLEAN bIn24G = TRUE; + + if (Channel <= 14) { + bIn24G = TRUE; + + if (1 <= Channel && Channel <= 2) + *pGroup = 0; + else if (3 <= Channel && Channel <= 5) + *pGroup = 1; + else if (6 <= Channel && Channel <= 8) + *pGroup = 2; + else if (9 <= Channel && Channel <= 11) + *pGroup = 3; + else if (12 <= Channel && Channel <= 14) + *pGroup = 4; + else + RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("==>Hal_GetChnlGroup8188F in 2.4 G, but Channel %d in Group not found\n", Channel)); + } else { + bIn24G = FALSE; + + if (36 <= Channel && Channel <= 42) + *pGroup = 0; + else if (44 <= Channel && Channel <= 48) *pGroup = 1; + else if (50 <= Channel && Channel <= 58) *pGroup = 2; + else if (60 <= Channel && Channel <= 64) *pGroup = 3; + else if (100 <= Channel && Channel <= 106) *pGroup = 4; + else if (108 <= Channel && Channel <= 114) *pGroup = 5; + else if (116 <= Channel && Channel <= 122) *pGroup = 6; + else if (124 <= Channel && Channel <= 130) *pGroup = 7; + else if (132 <= Channel && Channel <= 138) *pGroup = 8; + else if (140 <= Channel && Channel <= 144) *pGroup = 9; + else if (149 <= Channel && Channel <= 155) *pGroup = 10; + else if (157 <= Channel && Channel <= 161) *pGroup = 11; + else if (165 <= Channel && Channel <= 171) *pGroup = 12; + else if (173 <= Channel && Channel <= 177) *pGroup = 13; + else + RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("==>Hal_GetChnlGroup8188F in 5G, but Channel %d in Group not found\n", Channel)); + + } + RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("<==Hal_GetChnlGroup8188F, (%s) Channel = %d, Group =%d,\n", + (bIn24G) ? "2.4G" : "5G", Channel, *pGroup)); + return bIn24G; +} + +void +Hal_InitPGData( + PADAPTER padapter, + u8 *PROMContent) +{ + + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u32 i; + u16 value16; + + if (_FALSE == pHalData->bautoload_fail_flag) { + /* autoload OK. */ + /*if (IS_BOOT_FROM_EEPROM(padapter)) */ + if (_TRUE == pHalData->EepromOrEfuse) { + /* Read all Content from EEPROM or EFUSE. */ + for (i = 0; i < HWSET_MAX_SIZE_8188F; i += 2) { + /*value16 = EF2Byte(ReadEEprom(pAdapter, (u2Byte) (i>>1))); */ + /**((u16*)(&PROMContent[i])) = value16; */ + } + } else { + /* Read EFUSE real map to shadow. */ + EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, _FALSE); + _rtw_memcpy((void *)PROMContent, (void *)pHalData->efuse_eeprom_data, HWSET_MAX_SIZE_8188F); + } + } else { + /*autoload fail */ + RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("AutoLoad Fail reported from CR9346!!\n")); + /*pHalData->AutoloadFailFlag = _TRUE; */ + /*update to default value 0xFF */ + if (_FALSE == pHalData->EepromOrEfuse) + EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, _FALSE); + _rtw_memcpy((void *)PROMContent, (void *)pHalData->efuse_eeprom_data, HWSET_MAX_SIZE_8188F); + } + +#ifdef CONFIG_EFUSE_CONFIG_FILE + if (check_phy_efuse_tx_power_info_valid(padapter) == _FALSE) { + if (Hal_readPGDataFromConfigFile(padapter) != _SUCCESS) + DBG_871X_LEVEL(_drv_err_, "invalid phy efuse and read from file fail, will use driver default!!\n"); + } +#endif +} + +void +Hal_EfuseParseIDCode( + IN PADAPTER padapter, + IN u8 *hwinfo +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u16 EEPROMId; + + + /* Checl 0x8129 again for making sure autoload status!! */ + EEPROMId = le16_to_cpu(*((u16 *)hwinfo)); + if (EEPROMId != RTL_EEPROM_ID) { + DBG_8192C("EEPROM ID(%#x) is invalid!!\n", EEPROMId); + pHalData->bautoload_fail_flag = _TRUE; + } else + pHalData->bautoload_fail_flag = _FALSE; + + RT_TRACE(_module_hal_init_c_, _drv_notice_, ("EEPROM ID=0x%04x\n", EEPROMId)); +} + +static void +Hal_EEValueCheck( + IN u8 EEType, + IN PVOID pInValue, + OUT PVOID pOutValue +) +{ + switch (EEType) { + case EETYPE_TX_PWR: { + u8 *pIn, *pOut; + + pIn = (u8 *)pInValue; + pOut = (u8 *)pOutValue; + + if (*pIn <= 63) + *pOut = *pIn; + else { + RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("EETYPE_TX_PWR, value=%d is invalid, set to default=0x%x\n", + *pIn, EEPROM_Default_TxPowerLevel)); + *pOut = EEPROM_Default_TxPowerLevel; + } + } + break; + default: + break; + } +} + +static u8 +Hal_GetChnlGroup( + IN u8 chnl +) +{ + u8 group = 0; + + if (chnl < 3) /* Cjanel 1-3 */ + group = 0; + else if (chnl < 9) /* Channel 4-9 */ + group = 1; + else /* Channel 10-14 */ + group = 2; + + return group; +} + +void +Hal_ReadPowerValueFromPROM_8188F( + IN PADAPTER Adapter, + IN PTxPowerInfo24G pwrInfo24G, + IN u8 *PROMContent, + IN BOOLEAN AutoLoadFail +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u4Byte rfPath, eeAddr = EEPROM_TX_PWR_INX_8188F, group, TxCount = 0; + + _rtw_memset(pwrInfo24G, 0, sizeof(TxPowerInfo24G)); + + if (0xFF == PROMContent[eeAddr + 1]) + AutoLoadFail = TRUE; + + if (AutoLoadFail) { + DBG_871X("%s(): Use Default value!\n", __func__); + for (rfPath = 0; rfPath < MAX_RF_PATH; rfPath++) { + /*2.4G default value */ + for (group = 0; group < MAX_CHNL_GROUP_24G; group++) { + pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX; + pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX; + } + for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { + if (TxCount == 0) { + pwrInfo24G->BW20_Diff[rfPath][0] = EEPROM_DEFAULT_24G_HT20_DIFF; + pwrInfo24G->OFDM_Diff[rfPath][0] = EEPROM_DEFAULT_24G_OFDM_DIFF; + } else { + pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; + pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; + pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; + pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; + } + } + } + + return; + } + + pHalData->bTXPowerDataReadFromEEPORM = TRUE; /*YJ,move,120316 */ + + for (rfPath = 0; rfPath < MAX_RF_PATH; rfPath++) { + /*2 2.4G default value */ + for (group = 0; group < MAX_CHNL_GROUP_24G; group++) { + pwrInfo24G->IndexCCK_Base[rfPath][group] = PROMContent[eeAddr++]; + if (pwrInfo24G->IndexCCK_Base[rfPath][group] == 0xFF) + pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX; + } + for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) { + pwrInfo24G->IndexBW40_Base[rfPath][group] = PROMContent[eeAddr++]; + if (pwrInfo24G->IndexBW40_Base[rfPath][group] == 0xFF) + pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX; + } + for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { + if (TxCount == 0) { + pwrInfo24G->BW40_Diff[rfPath][TxCount] = 0; + pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr] & 0xf0) >> 4; + if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) /*4bit sign number to 8 bit sign number*/ + pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0; + + pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr] & 0x0f); + if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) /*4bit sign number to 8 bit sign number*/ + pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0; + + pwrInfo24G->CCK_Diff[rfPath][TxCount] = 0; + eeAddr++; + } else { + pwrInfo24G->BW40_Diff[rfPath][TxCount] = (PROMContent[eeAddr] & 0xf0) >> 4; + if (pwrInfo24G->BW40_Diff[rfPath][TxCount] & BIT3) /*4bit sign number to 8 bit sign number*/ + pwrInfo24G->BW40_Diff[rfPath][TxCount] |= 0xF0; + + pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr] & 0x0f); + if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) /*4bit sign number to 8 bit sign number*/ + pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0; + + eeAddr++; + + pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr] & 0xf0) >> 4; + if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) /*4bit sign number to 8 bit sign number*/ + pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0; + + + pwrInfo24G->CCK_Diff[rfPath][TxCount] = (PROMContent[eeAddr] & 0x0f); + if (pwrInfo24G->CCK_Diff[rfPath][TxCount] & BIT3) /*4bit sign number to 8 bit sign number*/ + pwrInfo24G->CCK_Diff[rfPath][TxCount] |= 0xF0; + + eeAddr++; + } + } + + /* Ignore the unnecessary 5G parameters parsing, but still consider the efuse address offset */ +#define TX_PWR_DIFF_OFFSET_5G 10 + eeAddr += (MAX_CHNL_GROUP_5G + TX_PWR_DIFF_OFFSET_5G); + } +} + + +void +Hal_EfuseParseTxPowerInfo_8188F( + IN PADAPTER padapter, + IN u8 *PROMContent, + IN BOOLEAN AutoLoadFail +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + TxPowerInfo24G pwrInfo24G; + u8 rfPath, ch, group, TxCount = 1; + + /*RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("%s(): AutoLoadFail = %d\n", __func__, AutoLoadFail)); */ + Hal_ReadPowerValueFromPROM_8188F(padapter, &pwrInfo24G, PROMContent, AutoLoadFail); + for (rfPath = 0; rfPath < MAX_RF_PATH; rfPath++) { + for (ch = 0; ch < CENTER_CH_2G_NUM; ch++) { + Hal_GetChnlGroup8188F(ch + 1, &group); + + if (ch == 14 - 1) { + pHalData->Index24G_CCK_Base[rfPath][ch] = pwrInfo24G.IndexCCK_Base[rfPath][5]; + pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][group]; + } else { + pHalData->Index24G_CCK_Base[rfPath][ch] = pwrInfo24G.IndexCCK_Base[rfPath][group]; + pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][group]; + } +#ifdef CONFIG_DEBUG + RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("======= Path %d, ChannelIndex %d, Group %d=======\n", rfPath, ch, group)); + RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Index24G_CCK_Base[%d][%d] = 0x%x\n", rfPath, ch , pHalData->Index24G_CCK_Base[rfPath][ch])); + RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Index24G_BW40_Base[%d][%d] = 0x%x\n", rfPath, ch, pHalData->Index24G_BW40_Base[rfPath][ch])); +#endif + } + + for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { + pHalData->CCK_24G_Diff[rfPath][TxCount] = pwrInfo24G.CCK_Diff[rfPath][TxCount]; + pHalData->OFDM_24G_Diff[rfPath][TxCount] = pwrInfo24G.OFDM_Diff[rfPath][TxCount]; + pHalData->BW20_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW20_Diff[rfPath][TxCount]; + pHalData->BW40_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW40_Diff[rfPath][TxCount]; + +#ifdef CONFIG_DEBUG + RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("--------------------------------------- 2.4G ---------------------------------------\n")); + RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("CCK_24G_Diff[%d][%d]= %d\n", rfPath, TxCount, pHalData->CCK_24G_Diff[rfPath][TxCount])); + RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("OFDM_24G_Diff[%d][%d]= %d\n", rfPath, TxCount, pHalData->OFDM_24G_Diff[rfPath][TxCount])); + RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("BW20_24G_Diff[%d][%d]= %d\n", rfPath, TxCount, pHalData->BW20_24G_Diff[rfPath][TxCount])); + RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("BW40_24G_Diff[%d][%d]= %d\n", rfPath, TxCount, pHalData->BW40_24G_Diff[rfPath][TxCount])); +#endif + } + } + + /* 2010/10/19 MH Add Regulator recognize for CU. */ + if (!AutoLoadFail) { + pHalData->EEPROMRegulatory = (PROMContent[EEPROM_RF_BOARD_OPTION_8188F] & 0x7); /*bit0~2 */ + if (PROMContent[EEPROM_RF_BOARD_OPTION_8188F] == 0xFF) + pHalData->EEPROMRegulatory = (EEPROM_DEFAULT_BOARD_OPTION & 0x7); /*bit0~2 */ + } else + pHalData->EEPROMRegulatory = 0; + RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("EEPROMRegulatory = 0x%x\n", pHalData->EEPROMRegulatory)); +} + +VOID +Hal_EfuseParseEEPROMVer_8188F( + IN PADAPTER padapter, + IN u8 *hwinfo, + IN BOOLEAN AutoLoadFail +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + /*RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("%s(): AutoLoadFail = %d\n", __func__, AutoLoadFail)); */ + if (!AutoLoadFail) + pHalData->EEPROMVersion = hwinfo[EEPROM_VERSION_8188F]; + else + pHalData->EEPROMVersion = 1; + RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("Hal_EfuseParseEEPROMVer(), EEVer = %d\n", + pHalData->EEPROMVersion)); +} + +#if 0 /* Do not need for rtl8188f */ +VOID +Hal_EfuseParseVoltage_8188F( + IN PADAPTER pAdapter, + IN u8 *hwinfo, + IN BOOLEAN AutoLoadFail +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + /*_rtw_memcpy(pEEPROM->adjuseVoltageVal, &hwinfo[EEPROM_Voltage_ADDR_8188F], 1); */ + DBG_871X("%s hwinfo[EEPROM_Voltage_ADDR_8188F] =%02x\n", __func__, hwinfo[EEPROM_Voltage_ADDR_8188F]); + pHalData->adjuseVoltageVal = (hwinfo[EEPROM_Voltage_ADDR_8188F] & 0xf0) >> 4; + DBG_871X("%s pHalData->adjuseVoltageVal =%x\n", __func__, pHalData->adjuseVoltageVal); +} +#endif + +VOID +Hal_EfuseParseChnlPlan_8188F( + IN PADAPTER padapter, + IN u8 *hwinfo, + IN BOOLEAN AutoLoadFail +) +{ + padapter->mlmepriv.ChannelPlan = hal_com_config_channel_plan( + padapter + , hwinfo ? &hwinfo[EEPROM_COUNTRY_CODE_8188F] : NULL + , hwinfo ? hwinfo[EEPROM_ChannelPlan_8188F] : 0xFF + , padapter->registrypriv.alpha2 + , padapter->registrypriv.channel_plan + , RTW_CHPLAN_WORLD_NULL + , AutoLoadFail + ); +} + +VOID +Hal_EfuseParseCustomerID_8188F( + IN PADAPTER padapter, + IN u8 *hwinfo, + IN BOOLEAN AutoLoadFail +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + /*RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("%s(): AutoLoadFail = %d\n", __func__, AutoLoadFail)); */ + if (!AutoLoadFail) + pHalData->EEPROMCustomerID = hwinfo[EEPROM_CustomID_8188F]; + else + pHalData->EEPROMCustomerID = 0; + RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("EEPROM Customer ID: 0x%2x\n", pHalData->EEPROMCustomerID)); +} + +VOID +Hal_EfuseParsePowerSavingMode_8188F( + IN PADAPTER padapter, + IN u8 *hwinfo, + IN BOOLEAN AutoLoadFail +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); + u8 tmpvalue; + + if (AutoLoadFail) { + pwrctl->bHWPowerdown = _FALSE; + pwrctl->bSupportRemoteWakeup = _FALSE; + } else { + + /* hw power down mode selection , 0:rf-off ; 1:power down */ + + if (padapter->registrypriv.hwpdn_mode == 2) + pwrctl->bHWPowerdown = (hwinfo[EEPROM_FEATURE_OPTION_8188F] & BIT4); + else + pwrctl->bHWPowerdown = padapter->registrypriv.hwpdn_mode; + + /* decide hw if support remote wakeup function */ + /* if hw supported, 8051 (SIE) will generate WeakUP signal( D+/D- toggle) when autoresume */ +#ifdef CONFIG_USB_HCI + pwrctl->bSupportRemoteWakeup = (hwinfo[EEPROM_USB_OPTIONAL_FUNCTION0_8188FU] & BIT1) ? _TRUE : _FALSE; +#endif /* CONFIG_USB_HCI */ + + DBG_871X("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) ,bSupportRemoteWakeup(%x)\n" + , __FUNCTION__, pwrctl->bHWPwrPindetect, pwrctl->bHWPowerdown, pwrctl->bSupportRemoteWakeup); + + DBG_871X("### PS params=> power_mgnt(%x),usbss_enable(%x) ###\n" + , padapter->registrypriv.power_mgnt, padapter->registrypriv.usbss_enable); + + } +} + +VOID +Hal_EfuseParseAntennaDiversity_8188F( + IN PADAPTER pAdapter, + IN u8 *hwinfo, + IN BOOLEAN AutoLoadFail +) +{ +#ifdef CONFIG_ANTENNA_DIVERSITY + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); + struct registry_priv *registry_par = &pAdapter->registrypriv; + + /* default:rtw_antdiv_cfg, 0:OFF, 1:ON, 2:By EFUSE */ + if (registry_par->antdiv_cfg == 2) { + if (0x01 == hwinfo[EEPROM_RF_ANTENNA_OPT_8188F]) + pHalData->AntDivCfg = 1; + else + pHalData->AntDivCfg = 0; + } else if (registry_par->antdiv_cfg == 1) + pHalData->AntDivCfg = 1; + else + pHalData->AntDivCfg = 0; + + /* If TRxAntDivType is AUTO in advanced setting, use EFUSE value instead. */ + /* default:rtw_antdiv_type */ + if (registry_par->antdiv_type == 0) { +#if 0 + pHalData->TRxAntDivType = hwinfo[EEPROM_RFE_OPTION_8188F]; + if (pHalData->TRxAntDivType == 0xFF) + pHalData->TRxAntDivType = S0S1_SW_ANTDIV; + else + DBG_8192C("%s: efuse[0x%x]=0x%02x is unknown type\n", + __func__, EEPROM_RFE_OPTION_8188F, pHalData->TRxAntDivType); +#else + /* 8188F only intrnal switch S0S1 */ + pHalData->TRxAntDivType = S0S1_SW_ANTDIV; +#endif + } else { + /* 8188F only intrnal switch S0S1 */ + pHalData->TRxAntDivType = S0S1_SW_ANTDIV; + } + + DBG_8192C("%s: AntDivCfg=%d, AntDivType=%d\n", + __func__, pHalData->AntDivCfg, pHalData->TRxAntDivType); +#endif +} + +VOID +Hal_EfuseParseXtal_8188F( + IN PADAPTER pAdapter, + IN u8 *hwinfo, + IN BOOLEAN AutoLoadFail +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + /*RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("%s(): AutoLoadFail = %d\n", __func__, AutoLoadFail)); */ + if (!AutoLoadFail) { + pHalData->CrystalCap = hwinfo[EEPROM_XTAL_8188F]; + if (pHalData->CrystalCap == 0xFF) + pHalData->CrystalCap = EEPROM_Default_CrystalCap_8188F; /*what value should 8812 set? */ + } else + pHalData->CrystalCap = EEPROM_Default_CrystalCap_8188F; + RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("EEPROM CrystalCap: 0x%2x\n", pHalData->CrystalCap)); +} + + +void +Hal_EfuseParseThermalMeter_8188F( + PADAPTER padapter, + u8 *PROMContent, + u8 AutoLoadFail +) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + + /*RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("%s(): AutoLoadFail = %d\n", __func__, AutoLoadFail)); */ + /* */ + /* ThermalMeter from EEPROM */ + /* */ + if (_FALSE == AutoLoadFail) + pHalData->EEPROMThermalMeter = PROMContent[EEPROM_THERMAL_METER_8188F]; + else + pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_8188F; + + if ((pHalData->EEPROMThermalMeter == 0xff) || (_TRUE == AutoLoadFail)) { + pHalData->odmpriv.RFCalibrateInfo.bAPKThermalMeterIgnore = _TRUE; + pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_8188F; + } + + RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("EEPROM ThermalMeter=0x%x\n", pHalData->EEPROMThermalMeter)); +} + + +void Hal_EfuseParseKFreeData_8188F( + IN PADAPTER Adapter, + IN u8 *PROMContent, + IN BOOLEAN AutoloadFail) +{ +#ifdef CONFIG_RF_POWER_TRIM +#define THERMAL_K_MEAN_OFFSET_8188F 5 /* 8188F FT thermal K mean value has +5 offset, it's special case */ + + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct kfree_data_t *kfree_data = &pHalData->kfree_data; + u8 pg_pwrtrim = 0xFF, pg_therm = 0xFF; + + pg_pwrtrim = EFUSE_Read1Byte(Adapter, PPG_BB_GAIN_2G_TXA_OFFSET_8188F); + pg_therm = EFUSE_Read1Byte(Adapter, PPG_THERMAL_OFFSET_8188F); + + if (pg_pwrtrim != 0xFF) { + kfree_data->bb_gain[BB_GAIN_2G][RF_PATH_A] + = KFREE_BB_GAIN_2G_TX_OFFSET(pg_pwrtrim & PPG_BB_GAIN_2G_TX_OFFSET_MASK); + kfree_data->flag |= KFREE_FLAG_ON; + } + + if (pg_therm != 0xFF) { + kfree_data->thermal + = KFREE_THERMAL_OFFSET(pg_therm & PPG_THERMAL_OFFSET_MASK) - THERMAL_K_MEAN_OFFSET_8188F; + if (GET_PG_KFREE_THERMAL_K_ON_8188F(PROMContent)) + kfree_data->flag |= KFREE_FLAG_THERMAL_K_ON; + } + + if (kfree_data->flag & KFREE_FLAG_THERMAL_K_ON) + pHalData->EEPROMThermalMeter -= kfree_data->thermal; + + DBG_871X("kfree Pwr Trim flag:%u\n", kfree_data->flag); + if (kfree_data->flag & KFREE_FLAG_ON) + DBG_871X("bb_gain:%d\n", kfree_data->bb_gain[BB_GAIN_2G][RF_PATH_A]); + if (kfree_data->flag & KFREE_FLAG_THERMAL_K_ON) + DBG_871X("thermal:%d\n", kfree_data->thermal); + +#endif /*CONFIG_RF_POWER_TRIM */ +} + +u8 +BWMapping_8188F( + IN PADAPTER Adapter, + IN struct pkt_attrib *pattrib +) +{ + u8 BWSettingOfDesc = 0; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + + /*DBG_871X("BWMapping pHalData->CurrentChannelBW %d, pattrib->bwmode %d\n",pHalData->CurrentChannelBW,pattrib->bwmode); */ + + if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_80) { + if (pattrib->bwmode == CHANNEL_WIDTH_80) + BWSettingOfDesc = 2; + else if (pattrib->bwmode == CHANNEL_WIDTH_40) + BWSettingOfDesc = 1; + else + BWSettingOfDesc = 0; + } else if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) { + if ((pattrib->bwmode == CHANNEL_WIDTH_40) || (pattrib->bwmode == CHANNEL_WIDTH_80)) + BWSettingOfDesc = 1; + else + BWSettingOfDesc = 0; + } else + BWSettingOfDesc = 0; + + /*if(pTcb->bBTTxPacket) */ + /* BWSettingOfDesc = 0; */ + + return BWSettingOfDesc; +} + +u8 SCMapping_8188F(PADAPTER Adapter, struct pkt_attrib *pattrib) +{ + u8 SCSettingOfDesc = 0; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + + /*DBG_871X("SCMapping: pHalData->CurrentChannelBW %d, pHalData->nCur80MhzPrimeSC %d, pHalData->nCur40MhzPrimeSC %d\n",pHalData->CurrentChannelBW,pHalData->nCur80MhzPrimeSC,pHalData->nCur40MhzPrimeSC); */ + + if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_80) { + if (pattrib->bwmode == CHANNEL_WIDTH_80) + SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE; + else if (pattrib->bwmode == CHANNEL_WIDTH_40) { + if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) + SCSettingOfDesc = VHT_DATA_SC_40_LOWER_OF_80MHZ; + else if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) + SCSettingOfDesc = VHT_DATA_SC_40_UPPER_OF_80MHZ; + else + DBG_871X("SCMapping: DONOT CARE Mode Setting\n"); + } else { + if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)) + SCSettingOfDesc = VHT_DATA_SC_20_LOWEST_OF_80MHZ; + else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)) + SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ; + else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)) + SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ; + else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)) + SCSettingOfDesc = VHT_DATA_SC_20_UPPERST_OF_80MHZ; + else + DBG_871X("SCMapping: DONOT CARE Mode Setting\n"); + } + } else if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) { + /*DBG_871X("SCMapping: HT Case: pHalData->CurrentChannelBW %d, pHalData->nCur40MhzPrimeSC %d\n",pHalData->CurrentChannelBW,pHalData->nCur40MhzPrimeSC); */ + + if (pattrib->bwmode == CHANNEL_WIDTH_40) + SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE; + else if (pattrib->bwmode == CHANNEL_WIDTH_20) { + if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) + SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ; + else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) + SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ; + else + SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE; + } + } else + SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE; + + return SCSettingOfDesc; +} + + +static u8 fill_txdesc_sectype(struct pkt_attrib *pattrib) +{ + u8 sectype = 0; + if ((pattrib->encrypt > 0) && !pattrib->bswenc) { + switch (pattrib->encrypt) { + /* SEC_TYPE */ + case _WEP40_: + case _WEP104_: + case _TKIP_: + case _TKIP_WTMIC_: + sectype = 1; + break; + +#ifdef CONFIG_WAPI_SUPPORT + case _SMS4_: + sectype = 2; + break; +#endif + case _AES_: + sectype = 3; + break; + + case _NO_PRIVACY_: + default: + break; + } + } + return sectype; +} + +static void fill_txdesc_vcs_8188f(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc) +{ + /*DBG_8192C("cvs_mode=%d\n", pattrib->vcs_mode); */ + + SET_TX_DESC_HW_RTS_ENABLE_8188F(ptxdesc, 0); + + switch (pattrib->vcs_mode) { + case RTS_CTS: + SET_TX_DESC_RTS_ENABLE_8188F(ptxdesc, 1); + break; + case CTS_TO_SELF: + SET_TX_DESC_CTS2SELF_8188F(ptxdesc, 1); + break; + case NONE_VCS: + default: + break; + } + +#if 1 /* TODO: */ + /* Protection mode related */ + if (pattrib->vcs_mode) { + /* SET_TX_DESC_CCA_RTS_8188F(ptxdesc, pTcb->RTSCCA); */ + SET_TX_DESC_RTS_RATE_8188F(ptxdesc, 8); /*TODO: Hardcode?, RTS Rate=24M (8) */ + SET_TX_DESC_RTS_RATE_FB_LIMIT_8188F(ptxdesc, 0xF); /* TODO: PROTECTION_MODE ?? */ + + if (padapter->mlmeextpriv.mlmext_info.preamble_mode == PREAMBLE_SHORT) + SET_TX_DESC_RTS_SHORT_8188F(ptxdesc, 1); + + /* Set RTS BW */ + if (pattrib->ht_en) + SET_TX_DESC_RTS_SC_8188F(ptxdesc, SCMapping_8188F(padapter, pattrib)); + } +#endif +} + +static void fill_txdesc_phy_8188f(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc) +{ + /*DBG_8192C("bwmode=%d, ch_off=%d\n", pattrib->bwmode, pattrib->ch_offset); */ + + if (pattrib->ht_en) { + SET_TX_DESC_DATA_BW_8188F(ptxdesc, BWMapping_8188F(padapter, pattrib)); + SET_TX_DESC_DATA_SC_8188F(ptxdesc, SCMapping_8188F(padapter, pattrib)); + } +} + +static void rtl8188f_fill_default_txdesc( + struct xmit_frame *pxmitframe, + u8 *pbuf) +{ + PADAPTER padapter; + HAL_DATA_TYPE *pHalData; + struct mlme_ext_priv *pmlmeext; + struct mlme_ext_info *pmlmeinfo; + struct pkt_attrib *pattrib; + s32 bmcst; + + _rtw_memset(pbuf, 0, TXDESC_SIZE); + + padapter = pxmitframe->padapter; + pHalData = GET_HAL_DATA(padapter); + pmlmeext = &padapter->mlmeextpriv; + pmlmeinfo = &(pmlmeext->mlmext_info); + + pattrib = &pxmitframe->attrib; + bmcst = IS_MCAST(pattrib->ra); + + if (pxmitframe->frame_tag == DATA_FRAMETAG) { + u8 drv_userate = 0; + + SET_TX_DESC_MACID_8188F(pbuf, pattrib->mac_id); + SET_TX_DESC_RATE_ID_8188F(pbuf, pattrib->raid); + SET_TX_DESC_QUEUE_SEL_8188F(pbuf, pattrib->qsel); + SET_TX_DESC_SEQ_8188F(pbuf, pattrib->seqnum); + + SET_TX_DESC_SEC_TYPE_8188F(pbuf, fill_txdesc_sectype(pattrib)); + fill_txdesc_vcs_8188f(padapter, pattrib, pbuf); + +#ifdef CONFIG_P2P + if (!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE)) { + if (pattrib->icmp_pkt == 1 && padapter->registrypriv.wifi_spec == 1) + drv_userate = 1; + } +#endif + + if ((pattrib->ether_type != 0x888e) && + (pattrib->ether_type != 0x0806) && + (pattrib->ether_type != 0x88B4) && + (pattrib->dhcp_pkt != 1) && + (drv_userate != 1) +#ifdef CONFIG_AUTO_AP_MODE + && (pattrib->pctrl != _TRUE) +#endif + ) { + /* Non EAP & ARP & DHCP type data packet */ + + if (pattrib->ampdu_en == _TRUE) { + SET_TX_DESC_AGG_ENABLE_8188F(pbuf, 1); + SET_TX_DESC_MAX_AGG_NUM_8188F(pbuf, 0x1F); + SET_TX_DESC_AMPDU_DENSITY_8188F(pbuf, pattrib->ampdu_spacing); + } else + SET_TX_DESC_AGG_BREAK_8188F(pbuf, 1); + + fill_txdesc_phy_8188f(padapter, pattrib, pbuf); + + SET_TX_DESC_DATA_RATE_FB_LIMIT_8188F(pbuf, 0x1F); + + if (pHalData->fw_ractrl == _FALSE) { + SET_TX_DESC_USE_RATE_8188F(pbuf, 1); + + if (pHalData->INIDATA_RATE[pattrib->mac_id] & BIT(7)) + SET_TX_DESC_DATA_SHORT_8188F(pbuf, 1); + + SET_TX_DESC_TX_RATE_8188F(pbuf, pHalData->INIDATA_RATE[pattrib->mac_id] & 0x7F); + } + + /* modify data rate by iwpriv */ + if (padapter->fix_rate != 0xFF) { + SET_TX_DESC_USE_RATE_8188F(pbuf, 1); + if (padapter->fix_rate & BIT(7)) + SET_TX_DESC_DATA_SHORT_8188F(pbuf, 1); + SET_TX_DESC_TX_RATE_8188F(pbuf, padapter->fix_rate & 0x7F); + if (!padapter->data_fb) + SET_TX_DESC_DISABLE_FB_8188F(pbuf, 1); + } + + if (pattrib->ldpc) + SET_TX_DESC_DATA_LDPC_8188F(pbuf, 1); + + if (pattrib->stbc) + SET_TX_DESC_DATA_STBC_8188F(pbuf, 1); + +#ifdef CONFIG_CMCC_TEST + SET_TX_DESC_DATA_SHORT_8188F(pbuf, 1); /* use cck short premble */ +#endif + } else { + /* EAP data packet and ARP packet. */ + /* Use the 1M data rate to send the EAP/ARP packet. */ + /* This will maybe make the handshake smooth. */ + + SET_TX_DESC_AGG_BREAK_8188F(pbuf, 1); + SET_TX_DESC_USE_RATE_8188F(pbuf, 1); + if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT) + SET_TX_DESC_DATA_SHORT_8188F(pbuf, 1); + SET_TX_DESC_TX_RATE_8188F(pbuf, MRateToHwRate(pmlmeext->tx_rate)); + + DBG_8192C(FUNC_ADPT_FMT ": SP Packet(0x%04X) rate=0x%x\n", + FUNC_ADPT_ARG(padapter), pattrib->ether_type, MRateToHwRate(pmlmeext->tx_rate)); + } + +#if defined(CONFIG_USB_TX_AGGREGATION) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + SET_TX_DESC_USB_TXAGG_NUM_8188F(pbuf, pxmitframe->agg_num); +#endif + +#ifdef CONFIG_TDLS +#ifdef CONFIG_XMIT_ACK + /* CCX-TXRPT ack for xmit mgmt frames. */ + if (pxmitframe->ack_report) { +#ifdef DBG_CCX + DBG_8192C("%s set spe_rpt\n", __func__); +#endif + SET_TX_DESC_SPE_RPT_8188F(pbuf, 1); + SET_TX_DESC_SW_DEFINE_8188F(pbuf, (u8)(GET_PRIMARY_ADAPTER(padapter)->xmitpriv.seq_no)); + } +#endif /* CONFIG_XMIT_ACK */ +#endif + } else if (pxmitframe->frame_tag == MGNT_FRAMETAG) { + /* RT_TRACE(_module_hal_xmit_c_, _drv_notice_, ("%s: MGNT_FRAMETAG\n", __func__)); */ + + SET_TX_DESC_MACID_8188F(pbuf, pattrib->mac_id); + SET_TX_DESC_QUEUE_SEL_8188F(pbuf, pattrib->qsel); + SET_TX_DESC_RATE_ID_8188F(pbuf, pattrib->raid); + SET_TX_DESC_SEQ_8188F(pbuf, pattrib->seqnum); + SET_TX_DESC_USE_RATE_8188F(pbuf, 1); + + SET_TX_DESC_MBSSID_8188F(pbuf, pattrib->mbssid & 0xF); + + SET_TX_DESC_RETRY_LIMIT_ENABLE_8188F(pbuf, 1); + if (pattrib->retry_ctrl == _TRUE) { + /* Nothing */ + SET_TX_DESC_DATA_RETRY_LIMIT_8188F(pbuf, 6); + } else { + /* Nothing */ + SET_TX_DESC_DATA_RETRY_LIMIT_8188F(pbuf, 12); + } + +#ifdef CONFIG_INTEL_PROXIM + if ((padapter->proximity.proxim_on == _TRUE) && (pattrib->intel_proxim == _TRUE)) { + DBG_871X("\n %s pattrib->rate=%d\n", __func__, pattrib->rate); + SET_TX_DESC_TX_RATE_8188F(pbuf, pattrib->rate); + } else +#endif + { + SET_TX_DESC_TX_RATE_8188F(pbuf, MRateToHwRate(pmlmeext->tx_rate)); + } + +#ifdef CONFIG_XMIT_ACK + /* CCX-TXRPT ack for xmit mgmt frames. */ + if (pxmitframe->ack_report) { +#ifdef DBG_CCX + DBG_8192C("%s set spe_rpt\n", __func__); +#endif + SET_TX_DESC_SPE_RPT_8188F(pbuf, 1); + SET_TX_DESC_SW_DEFINE_8188F(pbuf, (u8)(GET_PRIMARY_ADAPTER(padapter)->xmitpriv.seq_no)); + } +#endif /* CONFIG_XMIT_ACK */ + } else if (pxmitframe->frame_tag == TXAGG_FRAMETAG) + RT_TRACE(_module_hal_xmit_c_, _drv_warning_, ("%s: TXAGG_FRAMETAG\n", __func__)); +#ifdef CONFIG_MP_INCLUDED + else if (pxmitframe->frame_tag == MP_FRAMETAG) { + RT_TRACE(_module_hal_xmit_c_, _drv_notice_, ("%s: MP_FRAMETAG\n", __func__)); + fill_txdesc_for_mp(padapter, pbuf); + } +#endif + else { + RT_TRACE(_module_hal_xmit_c_, _drv_warning_, ("%s: frame_tag=0x%x\n", __func__, pxmitframe->frame_tag)); + + SET_TX_DESC_MACID_8188F(pbuf, pattrib->mac_id); + SET_TX_DESC_RATE_ID_8188F(pbuf, pattrib->raid); + SET_TX_DESC_QUEUE_SEL_8188F(pbuf, pattrib->qsel); + SET_TX_DESC_SEQ_8188F(pbuf, pattrib->seqnum); + SET_TX_DESC_USE_RATE_8188F(pbuf, 1); + SET_TX_DESC_TX_RATE_8188F(pbuf, MRateToHwRate(pmlmeext->tx_rate)); + } + + SET_TX_DESC_PKT_SIZE_8188F(pbuf, pattrib->last_txcmdsz); + + { + u8 pkt_offset, offset; + + pkt_offset = 0; + offset = TXDESC_SIZE; +#ifdef CONFIG_USB_HCI + pkt_offset = pxmitframe->pkt_offset; + offset += (pxmitframe->pkt_offset >> 3); +#endif /* CONFIG_USB_HCI */ + +#ifdef CONFIG_TX_EARLY_MODE + if (pxmitframe->frame_tag == DATA_FRAMETAG) { + pkt_offset = 1; + offset += EARLY_MODE_INFO_SIZE; + } +#endif /* CONFIG_TX_EARLY_MODE */ + + SET_TX_DESC_PKT_OFFSET_8188F(pbuf, pkt_offset); + SET_TX_DESC_OFFSET_8188F(pbuf, offset); + } + + if (bmcst) + SET_TX_DESC_BMC_8188F(pbuf, 1); + + /* 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS. */ + /* (1) The sequence number of each non-Qos frame / broadcast / multicast / */ + /* mgnt frame should be controlled by Hw because Fw will also send null data */ + /* which we cannot control when Fw LPS enable. */ + /* --> default enable non-Qos data sequense number. 2010.06.23. by tynli. */ + /* (2) Enable HW SEQ control for beacon packet, because we use Hw beacon. */ + /* (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets. */ + /* 2010.06.23. Added by tynli. */ + if (!pattrib->qos_en) + SET_TX_DESC_HWSEQ_EN_8188F(pbuf, 1); +} + +/* + * Description: + * + * Parameters: + * pxmitframe xmitframe + * pbuf where to fill tx desc + */ +void rtl8188f_update_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) +{ + PADAPTER padapter = pxmitframe->padapter; + rtl8188f_fill_default_txdesc(pxmitframe, pbuf); + +#ifdef CONFIG_ANTENNA_DIVERSITY + ODM_SetTxAntByTxInfo(&GET_HAL_DATA(padapter)->odmpriv, pbuf, pxmitframe->attrib.mac_id); +#endif /* CONFIG_ANTENNA_DIVERSITY */ + +#if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + rtl8188f_cal_txdesc_chksum((struct tx_desc *)pbuf); +#endif +} + +#ifdef CONFIG_TSF_RESET_OFFLOAD +int reset_tsf(PADAPTER Adapter, u8 reset_port) +{ + u8 reset_cnt_before = 0, reset_cnt_after = 0, loop_cnt = 0; + u32 reg_reset_tsf_cnt = (IFACE_PORT0 == reset_port) ? + REG_FW_RESET_TSF_CNT_0 : REG_FW_RESET_TSF_CNT_1; + + rtw_scan_abort(Adapter->pbuddy_adapter); /* site survey will cause reset_tsf fail */ + reset_cnt_after = reset_cnt_before = rtw_read8(Adapter, reg_reset_tsf_cnt); + rtl8188f_reset_tsf(Adapter, reset_port); + + while ((reset_cnt_after == reset_cnt_before) && (loop_cnt < 10)) { + rtw_msleep_os(100); + loop_cnt++; + reset_cnt_after = rtw_read8(Adapter, reg_reset_tsf_cnt); + } + + return (loop_cnt >= 10) ? _FAIL : _TRUE; +} +#endif /* CONFIG_TSF_RESET_OFFLOAD */ + +static void hw_var_set_monitor(PADAPTER Adapter, u8 variable, u8 *val) +{ + u32 value_rcr, rcr_bits; + u16 value_rxfltmap2; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); + + if (*((u8 *)val) == _HW_STATE_MONITOR_) { + + /* Leave IPS */ + rtw_pm_set_ips(Adapter, IPS_NONE); + LeaveAllPowerSaveMode(Adapter); + + /* Receive all type */ + rcr_bits = RCR_AAP | RCR_APM | RCR_AM | RCR_AB | RCR_APWRMGT | RCR_ADF | RCR_ACF | RCR_AMF | RCR_APP_PHYST_RXFF; + + /* Append FCS */ + rcr_bits |= RCR_APPFCS; + +#if 0 + /* + CRC and ICV packet will drop in recvbuf2recvframe() + We no turn on it. + */ + rcr_bits |= (RCR_ACRC32 | RCR_AICV); +#endif + + /* Receive all data frames */ + value_rxfltmap2 = 0xFFFF; + + value_rcr = rcr_bits; + rtw_write32(Adapter, REG_RCR, value_rcr); + + rtw_write16(Adapter, REG_RXFLTMAP2, value_rxfltmap2); + +#if 0 + /* tx pause */ + rtw_write8(padapter, REG_TXPAUSE, 0xFF); +#endif + } else { + /* do nothing */ + } + +} + +static void hw_var_set_opmode(PADAPTER padapter, u8 variable, u8 *val) +{ + u8 val8; + u8 mode = *((u8 *)val); + static u8 isMonitor = _FALSE; + + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + + if (isMonitor == _TRUE) { + /* reset RCR */ + rtw_write32(padapter, REG_RCR, pHalData->ReceiveConfig); + isMonitor = _FALSE; + } + + if (mode == _HW_STATE_MONITOR_) { + isMonitor = _TRUE; + /* set net_type */ + Set_MSR(padapter, _HW_STATE_NOLINK_); + + hw_var_set_monitor(padapter, variable, val); + return; + } + +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->iface_type == IFACE_PORT1) { + /* disable Port1 TSF update */ + val8 = rtw_read8(padapter, REG_BCN_CTRL_1); + val8 |= DIS_TSF_UDT; + rtw_write8(padapter, REG_BCN_CTRL_1, val8); + + Set_MSR(padapter, mode); + + DBG_871X("#### %s()-%d iface_type(%d) mode=%d ####\n", + __func__, __LINE__, padapter->iface_type, mode); + + if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) { + if (!check_buddy_mlmeinfo_state(padapter, WIFI_FW_AP_STATE)) { + StopTxBeacon(padapter); +#ifdef CONFIG_PCI_HCI + UpdateInterruptMask8188FE(padapter, 0, 0, RT_BCN_INT_MASKS, 0); +#else /* !CONFIG_PCI_HCI */ +#ifdef CONFIG_INTERRUPT_BASED_TXBCN + +#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT + rtw_write8(padapter, REG_DRVERLYINT, 0x05);/*restore early int time to 5ms */ + UpdateInterruptMask8188FU(padapter, _TRUE, 0, IMR_BCNDMAINT0_8188F); +#endif /* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */ + +#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR + UpdateInterruptMask8188FU(padapter, _TRUE , 0, (IMR_TXBCN0ERR_8188F | IMR_TXBCN0OK_8188F)); +#endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */ + +#endif /* CONFIG_INTERRUPT_BASED_TXBCN */ +#endif /* !CONFIG_PCI_HCI */ + } + + /* disable atim wnd and disable beacon function */ + rtw_write8(padapter, REG_BCN_CTRL_1, DIS_TSF_UDT | DIS_ATIM); + } else if ((mode == _HW_STATE_ADHOC_) /*|| (mode == _HW_STATE_AP_)*/) { + ResumeTxBeacon(padapter); + rtw_write8(padapter, REG_BCN_CTRL_1, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB); + } else if (mode == _HW_STATE_AP_) { +#ifdef CONFIG_PCI_HCI + UpdateInterruptMask8188FE(padapter, RT_BCN_INT_MASKS, 0, 0, 0); +#else /* !CONFIG_PCI_HCI */ +#ifdef CONFIG_INTERRUPT_BASED_TXBCN + +#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT + UpdateInterruptMask8188FU(padapter, _TRUE, IMR_BCNDMAINT0_8188F, 0); +#endif /* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */ + +#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR + UpdateInterruptMask8188FU(padapter, _TRUE, (IMR_TXBCN0ERR_8188F | IMR_TXBCN0OK_8188F), 0); +#endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */ + +#endif /* CONFIG_INTERRUPT_BASED_TXBCN */ +#endif /* !CONFIG_PCI_HCI */ + + ResumeTxBeacon(padapter); + + rtw_write8(padapter, REG_BCN_CTRL_1, DIS_TSF_UDT | DIS_BCNQ_SUB); + + /* Set RCR */ + /*rtw_write32(padapter, REG_RCR, 0x70002a8e);//CBSSID_DATA must set to 0 */ + /*rtw_write32(padapter, REG_RCR, 0x7000228e);//CBSSID_DATA must set to 0 */ + rtw_write32(padapter, REG_RCR, 0x7000208e);/*CBSSID_DATA must set to 0,reject ICV_ERR packet */ + /* enable to rx data frame */ + rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF); + /* enable to rx ps-poll */ + rtw_write16(padapter, REG_RXFLTMAP1, 0x0400); + + /* Beacon Control related register for first time */ + rtw_write8(padapter, REG_BCNDMATIM, 0x02); /* 2ms */ + + /*rtw_write8(padapter, REG_BCN_MAX_ERR, 0xFF); */ + rtw_write8(padapter, REG_ATIMWND_1, 0x0a); /* 10ms for port1 */ + rtw_write16(padapter, REG_BCNTCFG, 0x00); + rtw_write16(padapter, REG_TBTT_PROHIBIT, 0xff04); + rtw_write16(padapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */ + + /* reset TSF2 */ + rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(1)); + + /* enable BCN1 Function for if2 */ + /* don't enable update TSF1 for if2 (due to TSF update when beacon/probe rsp are received) */ + rtw_write8(padapter, REG_BCN_CTRL_1, (DIS_TSF_UDT | EN_BCN_FUNCTION | EN_TXBCN_RPT | DIS_BCNQ_SUB)); + + /*SW_BCN_SEL - Port1 */ + /*rtw_write8(Adapter, REG_DWBCN1_CTRL_8192E+2, rtw_read8(Adapter, REG_DWBCN1_CTRL_8192E+2)|BIT4); */ + rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL); + + /* select BCN on port 1 */ + rtw_write8(padapter, REG_CCK_CHECK_8188F, + (rtw_read8(padapter, REG_CCK_CHECK_8188F) | BIT_BCN_PORT_SEL)); + + if (check_buddy_fwstate(padapter, WIFI_FW_NULL_STATE)) { + val8 = rtw_read8(padapter, REG_BCN_CTRL); + val8 &= ~EN_BCN_FUNCTION; + rtw_write8(padapter, REG_BCN_CTRL, val8); + } + + /*BCN1 TSF will sync to BCN0 TSF with offset(0x518) if if1_sta linked */ + /*rtw_write8(padapter, REG_BCN_CTRL_1, rtw_read8(padapter, REG_BCN_CTRL_1)|BIT(5)); */ + /*rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(3)); */ + + /*dis BCN0 ATIM WND if if1 is station */ + rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL) | DIS_ATIM); + +#ifdef CONFIG_TSF_RESET_OFFLOAD + /* Reset TSF for STA+AP concurrent mode */ + if (check_buddy_fwstate(padapter, (WIFI_STATION_STATE | WIFI_ASOC_STATE))) { + if (reset_tsf(padapter, IFACE_PORT1) == _FALSE) + DBG_871X("ERROR! %s()-%d: Reset port1 TSF fail\n", + __func__, __LINE__); + } +#endif /* CONFIG_TSF_RESET_OFFLOAD */ + } + } else /*else for port0 */ +#endif /* CONFIG_CONCURRENT_MODE */ + { + /* disable Port0 TSF update */ + val8 = rtw_read8(padapter, REG_BCN_CTRL); + val8 |= DIS_TSF_UDT; + rtw_write8(padapter, REG_BCN_CTRL, val8); + + /* set net_type */ + Set_MSR(padapter, mode); + DBG_871X("#### %s() -%d iface_type(0) mode = %d ####\n", __func__, __LINE__, mode); + + if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) { +#ifdef CONFIG_CONCURRENT_MODE + if (!check_buddy_mlmeinfo_state(padapter, WIFI_FW_AP_STATE)) { + /* suspect code indent for conditional statements */ +#else + { +#endif /* CONFIG_CONCURRENT_MODE */ + StopTxBeacon(padapter); +#ifdef CONFIG_PCI_HCI + UpdateInterruptMask8188FE(padapter, 0, 0, RT_BCN_INT_MASKS, 0); +#else /* !CONFIG_PCI_HCI */ +#ifdef CONFIG_INTERRUPT_BASED_TXBCN +#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT + rtw_write8(padapter, REG_DRVERLYINT, 0x05); /* restore early int time to 5ms */ + UpdateInterruptMask8812AU(padapter, _TRUE, 0, IMR_BCNDMAINT0_8188F); +#endif /* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */ + +#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR + UpdateInterruptMask8812AU(padapter, _TRUE , 0, (IMR_TXBCN0ERR_8188F | IMR_TXBCN0OK_8188F)); +#endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */ + +#endif /* CONFIG_INTERRUPT_BASED_TXBCN */ +#endif /* !CONFIG_PCI_HCI */ + } + + /* disable atim wnd */ + rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_ATIM); + /*rtw_write8(padapter,REG_BCN_CTRL, 0x18); */ + } else if ((mode == _HW_STATE_ADHOC_) /*|| (mode == _HW_STATE_AP_)*/) { + ResumeTxBeacon(padapter); + rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB); + } else if (mode == _HW_STATE_AP_) { +#ifdef CONFIG_PCI_HCI + UpdateInterruptMask8188FE(padapter, RT_BCN_INT_MASKS, 0, 0, 0); +#else /* !CONFIG_PCI_HCI */ +#ifdef CONFIG_INTERRUPT_BASED_TXBCN +#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT + UpdateInterruptMask8188FU(padapter, _TRUE , IMR_BCNDMAINT0_8188F, 0); +#endif /* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */ + +#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR + UpdateInterruptMask8188FU(padapter, _TRUE , (IMR_TXBCN0ERR_8188F | IMR_TXBCN0OK_8188F), 0); +#endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */ + +#endif /* CONFIG_INTERRUPT_BASED_TXBCN */ +#endif + + ResumeTxBeacon(padapter); + + rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT | DIS_BCNQ_SUB); + + /*Set RCR */ + /*rtw_write32(padapter, REG_RCR, 0x70002a8e);//CBSSID_DATA must set to 0 */ + /*rtw_write32(padapter, REG_RCR, 0x7000228e);//CBSSID_DATA must set to 0 */ + rtw_write32(padapter, REG_RCR, 0x7000208e);/*CBSSID_DATA must set to 0,reject ICV_ERR packet */ + /*enable to rx data frame */ + rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF); + /*enable to rx ps-poll */ + rtw_write16(padapter, REG_RXFLTMAP1, 0x0400); + + /*Beacon Control related register for first time */ + rtw_write8(padapter, REG_BCNDMATIM, 0x02); /* 2ms */ + + /*rtw_write8(padapter, REG_BCN_MAX_ERR, 0xFF); */ + rtw_write8(padapter, REG_ATIMWND, 0x0a); /* 10ms */ + rtw_write16(padapter, REG_BCNTCFG, 0x00); + rtw_write16(padapter, REG_TBTT_PROHIBIT, 0xff04); + rtw_write16(padapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */ + + /*reset TSF */ + rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(0)); + + /*enable BCN0 Function for if1 */ + /*don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received) */ + rtw_write8(padapter, REG_BCN_CTRL, (DIS_TSF_UDT | EN_BCN_FUNCTION | EN_TXBCN_RPT | DIS_BCNQ_SUB)); + + /*SW_BCN_SEL - Port0 */ + /*rtw_write8(Adapter, REG_DWBCN1_CTRL_8192E+2, rtw_read8(Adapter, REG_DWBCN1_CTRL_8192E+2) & ~BIT4); */ + rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL); + + /* select BCN on port 0 */ + rtw_write8(padapter, REG_CCK_CHECK_8188F, + (rtw_read8(padapter, REG_CCK_CHECK_8188F) & ~BIT_BCN_PORT_SEL)); + +#ifdef CONFIG_CONCURRENT_MODE + if (check_buddy_fwstate(padapter, WIFI_FW_NULL_STATE)) { + val8 = rtw_read8(padapter, REG_BCN_CTRL_1); + val8 &= ~EN_BCN_FUNCTION; + rtw_write8(padapter, REG_BCN_CTRL_1, val8); + } +#endif /* CONFIG_CONCURRENT_MODE */ + + /* dis BCN1 ATIM WND if if2 is station */ + val8 = rtw_read8(padapter, REG_BCN_CTRL_1); + val8 |= DIS_ATIM; + rtw_write8(padapter, REG_BCN_CTRL_1, val8); +#ifdef CONFIG_TSF_RESET_OFFLOAD + /* Reset TSF for STA+AP concurrent mode */ + if (check_buddy_fwstate(padapter, (WIFI_STATION_STATE | WIFI_ASOC_STATE))) { + if (reset_tsf(padapter, IFACE_PORT0) == _FALSE) + DBG_871X("ERROR! %s()-%d: Reset port0 TSF fail\n", + __func__, __LINE__); + } +#endif /* CONFIG_TSF_RESET_OFFLOAD */ + } + } +} + +static void hw_var_set_macaddr(PADAPTER padapter, u8 variable, u8 *val) +{ + u8 idx = 0; + u32 reg_macid; + +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->iface_type == IFACE_PORT1) + reg_macid = REG_MACID1; + else +#endif + { + reg_macid = REG_MACID; + } + + for (idx = 0; idx < 6; idx++) + rtw_write8(GET_PRIMARY_ADAPTER(padapter), (reg_macid + idx), val[idx]); +} + +static void hw_var_set_bssid(PADAPTER padapter, u8 variable, u8 *val) +{ + u8 idx = 0; + u32 reg_bssid; + +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->iface_type == IFACE_PORT1) + reg_bssid = REG_BSSID1; + else +#endif + { + reg_bssid = REG_BSSID; + } + + for (idx = 0; idx < 6; idx++) + rtw_write8(padapter, (reg_bssid + idx), val[idx]); +} + +static void hw_var_set_bcn_func(PADAPTER padapter, u8 variable, u8 *val) +{ + u32 bcn_ctrl_reg; + +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->iface_type == IFACE_PORT1) + bcn_ctrl_reg = REG_BCN_CTRL_1; + else +#endif + { + bcn_ctrl_reg = REG_BCN_CTRL; + } + + if (*(u8 *)val) + rtw_write8(padapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT)); + else { + u8 val8; + val8 = rtw_read8(padapter, bcn_ctrl_reg); + val8 &= ~(EN_BCN_FUNCTION | EN_TXBCN_RPT); +#ifdef CONFIG_BT_COEXIST + /* Always enable port0 beacon function for PSTDMA */ + if (REG_BCN_CTRL == bcn_ctrl_reg) + val8 |= EN_BCN_FUNCTION; +#endif + rtw_write8(padapter, bcn_ctrl_reg, val8); + } +} + +static void hw_var_set_correct_tsf(PADAPTER padapter, u8 variable, u8 *val) +{ + u8 val8; + u64 tsf; + struct mlme_ext_priv *pmlmeext; + struct mlme_ext_info *pmlmeinfo; + + + pmlmeext = &padapter->mlmeextpriv; + pmlmeinfo = &pmlmeext->mlmext_info; + + tsf = pmlmeext->TSFValue - rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval * 1024)) - 1024; /*us */ + + if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) || + ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) + StopTxBeacon(padapter); + +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->iface_type == IFACE_PORT1) { + /* disable related TSF function */ + val8 = rtw_read8(padapter, REG_BCN_CTRL_1); + val8 &= ~EN_BCN_FUNCTION; + rtw_write8(padapter, REG_BCN_CTRL_1, val8); + + rtw_write32(padapter, REG_TSFTR1, tsf); + rtw_write32(padapter, REG_TSFTR1 + 4, tsf >> 32); + + + /* enable related TSF function */ + val8 = rtw_read8(padapter, REG_BCN_CTRL_1); + val8 |= EN_BCN_FUNCTION; + rtw_write8(padapter, REG_BCN_CTRL_1, val8); + + /* Update buddy port's TSF if it is SoftAP for beacon TX issue! */ + if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE + && check_buddy_fwstate(padapter, WIFI_AP_STATE) + ) { + /* disable related TSF function */ + val8 = rtw_read8(padapter, REG_BCN_CTRL); + val8 &= ~EN_BCN_FUNCTION; + rtw_write8(padapter, REG_BCN_CTRL, val8); + + rtw_write32(padapter, REG_TSFTR, tsf); + rtw_write32(padapter, REG_TSFTR + 4, tsf >> 32); + + /* enable related TSF function */ + val8 = rtw_read8(padapter, REG_BCN_CTRL); + val8 |= EN_BCN_FUNCTION; + rtw_write8(padapter, REG_BCN_CTRL, val8); +#ifdef CONFIG_TSF_RESET_OFFLOAD + /* Update buddy port's TSF(TBTT) if it is SoftAP for beacon TX issue! */ + if (reset_tsf(padapter, IFACE_PORT0) == _FALSE) + DBG_871X("ERROR! %s()-%d: Reset port0 TSF fail\n", + __func__, __LINE__); + +#endif /* CONFIG_TSF_RESET_OFFLOAD */ + } + } else +#endif /* CONFIG_CONCURRENT_MODE */ + { + /* disable related TSF function */ + val8 = rtw_read8(padapter, REG_BCN_CTRL); + val8 &= ~EN_BCN_FUNCTION; + rtw_write8(padapter, REG_BCN_CTRL, val8); + + rtw_write32(padapter, REG_TSFTR, tsf); + rtw_write32(padapter, REG_TSFTR + 4, tsf >> 32); + + /* enable related TSF function */ + val8 = rtw_read8(padapter, REG_BCN_CTRL); + val8 |= EN_BCN_FUNCTION; + rtw_write8(padapter, REG_BCN_CTRL, val8); + +#ifdef CONFIG_CONCURRENT_MODE + /* Update buddy port's TSF if it is SoftAP for beacon TX issue! */ + if ((pmlmeinfo->state & 0x03) == WIFI_FW_STATION_STATE + && check_buddy_fwstate(padapter, WIFI_AP_STATE)) { + /* disable related TSF function */ + val8 = rtw_read8(padapter, REG_BCN_CTRL_1); + val8 &= ~EN_BCN_FUNCTION; + rtw_write8(padapter, REG_BCN_CTRL_1, val8); + + rtw_write32(padapter, REG_TSFTR1, tsf); + rtw_write32(padapter, REG_TSFTR1 + 4, tsf >> 32); + + /* enable related TSF function */ + val8 = rtw_read8(padapter, REG_BCN_CTRL_1); + val8 |= EN_BCN_FUNCTION; + rtw_write8(padapter, REG_BCN_CTRL_1, val8); + +#ifdef CONFIG_TSF_RESET_OFFLOAD + /* Update buddy port's TSF if it is SoftAP for beacon TX issue! */ + if (reset_tsf(padapter, IFACE_PORT1) == _FALSE) { + DBG_871X("ERROR! %s()-%d: Reset port1 TSF fail\n", + __func__, __LINE__); + } +#endif /* CONFIG_TSF_RESET_OFFLOAD */ + } +#endif /* CONFIG_CONCURRENT_MODE */ + } + + if (((pmlmeinfo->state & 0x03) == WIFI_FW_ADHOC_STATE) + || ((pmlmeinfo->state & 0x03) == WIFI_FW_AP_STATE)) + ResumeTxBeacon(padapter); +} + +static void hw_var_set_mlme_disconnect(PADAPTER padapter, u8 variable, u8 *val) +{ + u8 val8; + +#ifdef CONFIG_CONCURRENT_MODE + if (check_buddy_mlmeinfo_state(padapter, _HW_STATE_NOLINK_)) +#endif + { + /* Set RCR to not to receive data frame when NO LINK state */ + /*rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR) & ~RCR_ADF); */ + /* reject all data frames */ + rtw_write16(padapter, REG_RXFLTMAP2, 0); + } + +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->iface_type == IFACE_PORT1) { + /* reset TSF1 */ + rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(1)); + + /* disable update TSF1 */ + val8 = rtw_read8(padapter, REG_BCN_CTRL_1); + val8 |= DIS_TSF_UDT; + rtw_write8(padapter, REG_BCN_CTRL_1, val8); + + /* disable Port1's beacon function */ + val8 = rtw_read8(padapter, REG_BCN_CTRL_1); + val8 &= ~EN_BCN_FUNCTION; + rtw_write8(padapter, REG_BCN_CTRL_1, val8); + } else +#endif + { + /* reset TSF */ + rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(0)); + + /* disable update TSF */ + val8 = rtw_read8(padapter, REG_BCN_CTRL); + val8 |= DIS_TSF_UDT; + rtw_write8(padapter, REG_BCN_CTRL, val8); + } +} + +static void hw_var_set_mlme_sitesurvey(PADAPTER padapter, u8 variable, u8 *val) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + u32 value_rcr, rcr_clear_bit, reg_bcn_ctl; + u16 value_rxfltmap2; + u8 val8; + PHAL_DATA_TYPE pHalData; + struct mlme_priv *pmlmepriv; + u8 ap_num; + +#ifdef CONFIG_CONCURRENT_MODE + u32 buddy_reg_bcn_ctl; +#endif + + pHalData = GET_HAL_DATA(padapter); + pmlmepriv = &padapter->mlmepriv; + +#ifdef CONFIG_CONCURRENT_MODE + + if (padapter->iface_type == IFACE_PORT1) { + reg_bcn_ctl = REG_BCN_CTRL_1; + buddy_reg_bcn_ctl = REG_BCN_CTRL; + } else { + reg_bcn_ctl = REG_BCN_CTRL; + buddy_reg_bcn_ctl = REG_BCN_CTRL_1; + } +#else + reg_bcn_ctl = REG_BCN_CTRL; +#endif + + rtw_dev_iface_status(padapter, NULL, NULL, NULL, &ap_num, NULL); + +#ifdef CONFIG_FIND_BEST_CHANNEL + rcr_clear_bit = (RCR_CBSSID_BCN | RCR_CBSSID_DATA); + + /* Receive all data frames */ + value_rxfltmap2 = 0xFFFF; +#else /* CONFIG_FIND_BEST_CHANNEL */ + + rcr_clear_bit = RCR_CBSSID_BCN; + + /* config RCR to receive different BSSID & not to receive data frame */ + value_rxfltmap2 = 0; + +#endif /* CONFIG_FIND_BEST_CHANNEL */ + + if ((check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) +#ifdef CONFIG_CONCURRENT_MODE + || (check_buddy_fwstate(padapter, WIFI_AP_STATE) == _TRUE) +#endif + ) + rcr_clear_bit = RCR_CBSSID_BCN; +#ifdef CONFIG_TDLS + /* TDLS will clear RCR_CBSSID_DATA bit for connection. */ + else if (padapter->tdlsinfo.link_established == _TRUE) + rcr_clear_bit = RCR_CBSSID_BCN; +#endif /* CONFIG_TDLS */ + + value_rcr = rtw_read32(padapter, REG_RCR); + + if (*((u8 *)val)) { + /* under sitesurvey */ + /* + * 1. configure REG_RXFLTMAP2 + * 2. disable TSF update & buddy TSF update to avoid updating wrong TSF due to clear RCR_CBSSID_BCN + * 3. config RCR to receive different BSSID BCN or probe rsp + */ + + rtw_write16(padapter, REG_RXFLTMAP2, value_rxfltmap2); + + if (rtw_linked_check(padapter) && + check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) { + /* disable update TSF */ + rtw_write8(padapter, reg_bcn_ctl, rtw_read8(padapter, reg_bcn_ctl)|DIS_TSF_UDT); + padapter->mlmeextpriv.en_hw_update_tsf = _FALSE; + } + +#ifdef CONFIG_CONCURRENT_MODE + if (rtw_linked_check(padapter->pbuddy_adapter) && + check_fwstate(&padapter->pbuddy_adapter->mlmepriv, WIFI_AP_STATE) != _TRUE) { + /* disable update buddy TSF to avoid updating wrong TSF due to clear RCR_CBSSID_BCN */ + rtw_write8(padapter->pbuddy_adapter, buddy_reg_bcn_ctl, + rtw_read8(padapter->pbuddy_adapter, buddy_reg_bcn_ctl)|DIS_TSF_UDT); + padapter->pbuddy_adapter->mlmeextpriv.en_hw_update_tsf = _FALSE; + } +#endif + value_rcr &= ~(rcr_clear_bit); + rtw_write32(padapter, REG_RCR, value_rcr); + + /* Save orignal RRSR setting. */ + pHalData->RegRRSR = rtw_read16(padapter, REG_RRSR); + + if (ap_num) + StopTxBeacon(padapter); + } else { + /* + * 1. enable rx data frame + * 2. config RCR not to receive different BSSID BCN or probe rsp + * 3. doesn't enable TSF update & buddy TSF right now to avoid HW conflict + * so, we enable TSF update when rx first BCN after sitesurvey done + */ + + /* sitesurvey done */ + if (check_fwstate(pmlmepriv, (_FW_LINKED | WIFI_AP_STATE)) +#ifdef CONFIG_CONCURRENT_MODE + || check_buddy_fwstate(padapter, (_FW_LINKED | WIFI_AP_STATE)) +#endif + ) { + /* enable to rx data frame */ + rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF); + } + + value_rcr |= rcr_clear_bit; + rtw_write32(padapter, REG_RCR, value_rcr); + + if (rtw_linked_check(padapter) && + check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + padapter->mlmeextpriv.en_hw_update_tsf = _TRUE; + +#ifdef CONFIG_CONCURRENT_MODE + if (rtw_linked_check(padapter->pbuddy_adapter) && + check_fwstate(&padapter->pbuddy_adapter->mlmepriv, WIFI_AP_STATE) != _TRUE) + /* disable update buddy TSF to avoid updating wrong TSF due to clear RCR_CBSSID_BCN */ + padapter->pbuddy_adapter->mlmeextpriv.en_hw_update_tsf = _TRUE; +#endif + + /* Restore orignal RRSR setting. */ + rtw_write16(padapter, REG_RRSR, pHalData->RegRRSR); + + if (ap_num) { + int i; + _adapter *iface; + + ResumeTxBeacon(padapter); + for (i = 0; i < dvobj->iface_nums; i++) { + iface = dvobj->padapters[i]; + if (!iface) + continue; + + if (check_fwstate(&iface->mlmepriv, WIFI_AP_STATE) == _TRUE + && check_fwstate(&iface->mlmepriv, WIFI_ASOC_STATE) == _TRUE + ) { + iface->mlmepriv.update_bcn = _TRUE; + #ifndef CONFIG_INTERRUPT_BASED_TXBCN + #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + tx_beacon_hdl(iface, NULL); + #endif + #endif + + } + } + } + } +} + +static void hw_var_set_mlme_join(PADAPTER padapter, u8 variable, u8 *val) +{ + u8 val8; + u16 val16; + u32 val32; + u8 RetryLimit; + u8 type; + PHAL_DATA_TYPE pHalData; + struct mlme_priv *pmlmepriv; + + RetryLimit = 0x30; + type = *(u8 *)val; + pHalData = GET_HAL_DATA(padapter); + pmlmepriv = &padapter->mlmepriv; + +#ifdef CONFIG_CONCURRENT_MODE + if (type == 0) { + /* prepare to join */ + if (check_buddy_mlmeinfo_state(padapter, WIFI_FW_AP_STATE) && + check_buddy_fwstate(padapter, _FW_LINKED)) + StopTxBeacon(padapter); + + /* enable to rx data frame.Accept all data frame */ + rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF); + + if (check_buddy_mlmeinfo_state(padapter, WIFI_FW_AP_STATE)) { + val32 = rtw_read32(padapter, REG_RCR); + val32 |= RCR_CBSSID_BCN; + rtw_write32(padapter, REG_RCR, val32); + } else { + val32 = rtw_read32(padapter, REG_RCR); + val32 |= RCR_CBSSID_DATA | RCR_CBSSID_BCN; + rtw_write32(padapter, REG_RCR, val32); + } + + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) + RetryLimit = (pHalData->CustomerID == RT_CID_CCX) ? 7 : 48; + else /* Ad-hoc Mode */ + RetryLimit = 0x7; + } else if (type == 1) { + /* joinbss_event call back when join res < 0 */ + if (check_buddy_mlmeinfo_state(padapter, _HW_STATE_NOLINK_)) + rtw_write16(padapter, REG_RXFLTMAP2, 0x00); + + if (check_buddy_mlmeinfo_state(padapter, WIFI_FW_AP_STATE) && + check_buddy_fwstate(padapter, _FW_LINKED)) { + ResumeTxBeacon(padapter); + + /* reset TSF 1/2 after ResumeTxBeacon */ + rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(1) | BIT(0)); + } + } else if (type == 2) { + /* sta add event call back */ + + /* enable update TSF */ + if (padapter->iface_type == IFACE_PORT1) { + val8 = rtw_read8(padapter, REG_BCN_CTRL_1); + val8 &= ~DIS_TSF_UDT; + rtw_write8(padapter, REG_BCN_CTRL_1, val8); + } else { + val8 = rtw_read8(padapter, REG_BCN_CTRL); + val8 &= ~DIS_TSF_UDT; + rtw_write8(padapter, REG_BCN_CTRL, val8); + } + + if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) { + rtw_write8(padapter, 0x542 , 0x02); + RetryLimit = 0x7; + } + + if (check_buddy_mlmeinfo_state(padapter, WIFI_FW_AP_STATE) && + check_buddy_fwstate(padapter, _FW_LINKED)) { + ResumeTxBeacon(padapter); + + /* reset TSF 1/2 after ResumeTxBeacon */ + rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(1) | BIT(0)); + } + } + + val16 = (RetryLimit << RETRY_LIMIT_SHORT_SHIFT) | (RetryLimit << RETRY_LIMIT_LONG_SHIFT); + rtw_write16(padapter, REG_RL, val16); +#else /* !CONFIG_CONCURRENT_MODE */ + if (type == 0) { /* prepare to join */ + /*enable to rx data frame.Accept all data frame */ + /*rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF); */ + rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF); + + val32 = rtw_read32(padapter, REG_RCR); + if (padapter->in_cta_test) + val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);/*| RCR_ADF */ + else + val32 |= RCR_CBSSID_DATA | RCR_CBSSID_BCN; + rtw_write32(padapter, REG_RCR, val32); + + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) + RetryLimit = (pHalData->CustomerID == RT_CID_CCX) ? 7 : 48; + else /* Ad-hoc Mode */ + RetryLimit = 0x7; + } else if (type == 1) /*joinbss_event call back when join res < 0 */ + rtw_write16(padapter, REG_RXFLTMAP2, 0x00); + else if (type == 2) { /*sta add event call back */ + /*enable update TSF */ + val8 = rtw_read8(padapter, REG_BCN_CTRL); + val8 &= ~DIS_TSF_UDT; + rtw_write8(padapter, REG_BCN_CTRL, val8); + + if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) + RetryLimit = 0x7; + } + + val16 = (RetryLimit << RETRY_LIMIT_SHORT_SHIFT) | (RetryLimit << RETRY_LIMIT_LONG_SHIFT); + rtw_write16(padapter, REG_RL, val16); +#endif /* !CONFIG_CONCURRENT_MODE */ +} + +static void hw_var_set_hw_update_tsf(PADAPTER padapter) +{ + + u16 reg_bcn_ctl; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->iface_type == IFACE_PORT1) + reg_bcn_ctl = REG_BCN_CTRL_1; + else + reg_bcn_ctl = REG_BCN_CTRL; +#else + reg_bcn_ctl = REG_BCN_CTRL; +#endif + + if (!pmlmeext->en_hw_update_tsf) + return; + + /* check REG_RCR bit is set */ + if (!(rtw_read32(padapter, REG_RCR) & RCR_CBSSID_BCN)) { + pmlmeext->en_hw_update_tsf = _FALSE; + return; + } + + + /* enable hw update tsf function for non-AP */ + if (rtw_linked_check(padapter) && + check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + /* enable update buddy TSF */ + rtw_write8(padapter, reg_bcn_ctl, rtw_read8(padapter, reg_bcn_ctl)&(~DIS_TSF_UDT)); + + pmlmeext->en_hw_update_tsf = _FALSE; +} + +void CCX_FwC2HTxRpt_8188f(PADAPTER padapter, u8 *pdata, u8 len) +{ + u8 seq_no; + +#define GET_8188F_C2H_TX_RPT_LIFE_TIME_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 6, 1) +#define GET_8188F_C2H_TX_RPT_RETRY_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 7, 1) + + /*DBG_871X("%s, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, */ + /* *pdata, *(pdata+1), *(pdata+2), *(pdata+3), *(pdata+4), *(pdata+5), *(pdata+6), *(pdata+7)); */ + + seq_no = *(pdata + 6); + +#ifdef CONFIG_XMIT_ACK + if (GET_8188F_C2H_TX_RPT_RETRY_OVER(pdata) | GET_8188F_C2H_TX_RPT_LIFE_TIME_OVER(pdata)) + rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL); + /* + else if(seq_no != padapter->xmitpriv.seq_no) { + DBG_871X("tx_seq_no=%d, rpt_seq_no=%d\n", padapter->xmitpriv.seq_no, seq_no); + rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL); + } + */ + else + rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_SUCCESS); +#endif +} + +#ifdef CONFIG_FW_C2H_DEBUG +/* + * C2H RX package original is 128. + * If enable CONFIG_FW_C2H_DEBUG, it should increase to 256. + * C2H FW debug message: + * without aggregate: + * {C2H CmdID, Seq, SubID, Len, Content[0~n]} + * Content[0~n] = { 'a' , 'b' , 'c' ,..., 'z' , '\n'} + * + * with aggregate: + * {C2H CmdID, Seq, SubID, Len, Content[0~n]} + * Content[0~n] = { 'a' , 'b' , 'c' ,..., 'z', '\n' , Extend C2H pkt 2...} + * Extend C2H pkt 2 = {C2H CmdID, Seq, SubID, Len, Content = { 'a' , 'b' , 'c' ,..., 'z' , '\n'}} + * + * Author: Isaac + */ +void Debug_FwC2H_8188f(PADAPTER padapter, u8 *pdata, u8 len) +{ + int i = 0; + int cnt = 0, total_length = 0; + u8 buf[128] = {0}; + u8 more_data = _FALSE; + u8 *nextdata = NULL; + u8 test = 0; + + u8 data_len; + u8 seq_no; + + nextdata = pdata; +#if 0 + for (i = 0; i < len; i++) { + printk("%02x ", pdata[i]); + if ((i + 1) % 8 == 0) + printk("\n"); + } + printk("\n"); +#endif + do { + data_len = *(nextdata + 1); + seq_no = *(nextdata + 2); + + for (i = 0; i < data_len - 2; i++) { + cnt += sprintf((buf + cnt), "%c", nextdata[3 + i]); + + if (nextdata[3 + i] == 0x0a && nextdata[4 + i] == 0xff) + more_data = _TRUE; + else if (nextdata[3 + i] == 0x0a && nextdata[4 + i] != 0xff) + more_data = _FALSE; + } + + DBG_871X("[RTKFW, SEQ=%d]: %s", seq_no, buf); + data_len += 3; + total_length += data_len; + + if (more_data == _TRUE) { + _rtw_memset(buf, '\0', 128); + cnt = 0; + nextdata = (pdata + total_length); + } + } while (more_data == _TRUE); +} +#endif /*CONFIG_FW_C2H_DEBUG */ + +s32 c2h_id_filter_ccx_8188f(u8 *buf) +{ + struct c2h_evt_hdr_88xx *c2h_evt = (struct c2h_evt_hdr_88xx *)buf; + s32 ret = _FALSE; + if (c2h_evt->id == C2H_CCX_TX_RPT) + ret = _TRUE; + + return ret; +} + + +s32 c2h_handler_8188f(PADAPTER padapter, u8 *buf) +{ + struct c2h_evt_hdr_88xx *pC2hEvent = (struct c2h_evt_hdr_88xx *)buf; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + s32 ret = _SUCCESS; + u8 index = 0; + + if (pC2hEvent == NULL) { + DBG_8192C("%s(): pC2hEventis NULL\n", __func__); + ret = _FAIL; + goto exit; + } + + switch (pC2hEvent->id) { + case C2H_DBG: { + RT_TRACE(_module_hal_init_c_, _drv_info_, ("c2h_handler_8188f: %s\n", pC2hEvent->payload)); + } + break; + + case C2H_CCX_TX_RPT: + /*CCX_FwC2HTxRpt(padapter, QueueID, pC2hEvent->payload); */ + break; + +#ifdef CONFIG_BT_COEXIST + case C2H_BT_INFO: + rtw_btcoex_BtInfoNotify(padapter, pC2hEvent->plen, pC2hEvent->payload); + break; +#endif + +#ifdef CONFIG_RTW_CUSTOMER_STR + case C2H_CUSTOMER_STR_RPT: + c2h_customer_str_rpt_hdl(padapter, pC2hEvent->payload, pC2hEvent->plen); + break; + case C2H_CUSTOMER_STR_RPT_2: + c2h_customer_str_rpt_2_hdl(padapter, pC2hEvent->payload, pC2hEvent->plen); + break; +#endif + +/* +#ifdef CONFIG_MP_INCLUDED + case C2H_BT_MP_INFO: + DBG_8192C(" %s, C2H_BT_MP_INFO pC2hEvent->plen=%d\n", __func__, pC2hEvent->plen); + MPTBT_FwC2hBtMpCtrl(padapter, pC2hEvent->payload, pC2hEvent->plen); + break; +#endif +*/ + + default: + break; + } + + /* Clear event to notify FW we have read the command. */ + /* Note: */ + /* If this field isn't clear, the FW won't update the next command message. */ + /*rtw_write8(padapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE); */ +exit: + return ret; +} + +static void process_c2h_event(PADAPTER padapter, PC2H_EVT_HDR pC2hEvent, u8 *c2hBuf) +{ + u8 index = 0; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + + if (c2hBuf == NULL) { + DBG_8192C("%s c2hbuff is NULL\n", __func__); + return; + } + + switch (pC2hEvent->CmdID) { + case C2H_CCX_TX_RPT: + CCX_FwC2HTxRpt_8188f(padapter, c2hBuf, pC2hEvent->CmdLen); + break; + + +#ifdef CONFIG_BT_COEXIST + case C2H_BT_INFO: + rtw_btcoex_BtInfoNotify(padapter, pC2hEvent->CmdLen, c2hBuf); + break; +#endif + +/* +#ifdef CONFIG_MP_INCLUDED + case C2H_BT_MP_INFO: + MPTBT_FwC2hBtMpCtrl(padapter, c2hBuf, pC2hEvent->CmdLen); + break; +#endif +*/ +#ifdef CONFIG_FW_C2H_DEBUG + case C2H_EXTEND: + Debug_FwC2H_8188f(padapter, c2hBuf, pC2hEvent->CmdLen); + break; +#endif /* CONFIG_FW_C2H_DEBUG */ + +#ifdef CONFIG_RTW_CUSTOMER_STR + case C2H_CUSTOMER_STR_RPT: + c2h_customer_str_rpt_hdl(padapter, c2hBuf, pC2hEvent->CmdLen); + break; + case C2H_CUSTOMER_STR_RPT_2: + c2h_customer_str_rpt_2_hdl(padapter, c2hBuf, pC2hEvent->CmdLen); + break; +#endif + + default: + if (!(phydm_c2H_content_parsing(pDM_Odm, pC2hEvent->CmdID, pC2hEvent->CmdLen, c2hBuf))) + RT_TRACE(_module_hal_init_c_, _drv_info_, ("%s: [WARNING] unknown C2H(0x%02x)\n", __func__, c2hCmdId)); + + break; + + } + +#ifndef CONFIG_C2H_PACKET_EN + /* Clear event to notify FW we have read the command. */ + /* Note: */ + /* If this field isn't clear, the FW won't update the next command message. */ + rtw_write8(padapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE); +#endif +} + +#ifdef CONFIG_C2H_PACKET_EN + +static void C2HPacketHandler_8188F(PADAPTER padapter, u8 *pbuffer, u16 length) +{ + C2H_EVT_HDR C2hEvent; + u8 *tmpBuf = NULL; + C2hEvent.CmdID = pbuffer[0]; + C2hEvent.CmdSeq = pbuffer[1]; + C2hEvent.CmdLen = length - 2; + tmpBuf = pbuffer + 2; + + /*DBG_871X("%s C2hEvent.CmdID:%x C2hEvent.CmdLen:%x C2hEvent.CmdSeq:%x\n", */ + /* __func__, C2hEvent.CmdID, C2hEvent.CmdLen, C2hEvent.CmdSeq); */ + RT_PRINT_DATA(_module_hal_init_c_, _drv_notice_, "C2HPacketHandler_8188F(): Command Content:\n", tmpBuf, C2hEvent.CmdLen); + + process_c2h_event(padapter, &C2hEvent, tmpBuf); + /*c2h_handler_8188f(padapter,&C2hEvent); */ + return; +} + +void rtl8188f_c2h_packet_handler(PADAPTER padapter, u8 *pbuf, u16 length) +{ + C2H_EVT_HDR C2hEvent; + u8 *pdata; + + + if (length == 0) + return; + + C2hEvent.CmdID = pbuf[0]; + C2hEvent.CmdSeq = pbuf[1]; + C2hEvent.CmdLen = length - 2; + pdata = pbuf + 2; + + DBG_8192C("%s: C2H, ID=%d seq=%d len=%d\n", + __func__, C2hEvent.CmdID, C2hEvent.CmdSeq, C2hEvent.CmdLen); + + switch (C2hEvent.CmdID) { + case C2H_CCX_TX_RPT: +#ifdef CONFIG_FW_C2H_DEBUG + case C2H_EXTEND: +#endif /* CONFIG_FW_C2H_DEBUG */ + process_c2h_event(padapter, &C2hEvent, pdata); + break; + + case C2H_BCN_EARLY_RPT: +#ifdef CONFIG_TDLS +#ifdef CONFIG_TDLS_CH_SW + rtw_tdls_ch_sw_back_to_base_chnl(padapter); +#endif +#endif + break; + + case C2H_FW_CHNL_SWITCH_COMPLETE: +#ifdef CONFIG_TDLS +#ifdef CONFIG_TDLS_CH_SW + rtw_tdls_chsw_oper_done(padapter); +#endif +#endif + break; + + default: + rtw_c2h_packet_wk_cmd(padapter, pbuf, length); + break; + } +} + +#else /* !CONFIG_C2H_PACKET_EN */ +/* */ +/*C2H event format: */ +/* Field TRIGGER CONTENT CMD_SEQ CMD_LEN CMD_ID */ +/* BITS [127:120] [119:16] [15:8] [7:4] [3:0] */ +/*2009.10.08. by tynli. */ +static void C2HCommandHandler(PADAPTER padapter) +{ + C2H_EVT_HDR C2hEvent; +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + + u8 *tmpBuf = NULL; + u8 index = 0; + u8 bCmdMsgReady = _FALSE; + u8 U1bTmp = 0; + /*u8 QueueID = 0; */ + + _rtw_memset(&C2hEvent, 0, sizeof(C2H_EVT_HDR)); + + C2hEvent.CmdID = rtw_read8(padapter, REG_C2HEVT_CMD_ID_8188F); + C2hEvent.CmdLen = rtw_read8(padapter, REG_C2HEVT_CMD_LEN_8188F); + C2hEvent.CmdSeq = rtw_read8(padapter, REG_C2HEVT_CMD_ID_8188F + 1); + + RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "C2HCommandHandler(): ", + &C2hEvent , sizeof(C2hEvent)); + + U1bTmp = rtw_read8(padapter, REG_C2HEVT_CLEAR); + DBG_871X("%s C2hEvent.CmdID:%x C2hEvent.CmdLen:%x C2hEvent.CmdSeq:%x\n", + __func__, C2hEvent.CmdID, C2hEvent.CmdLen, C2hEvent.CmdSeq); + + if (U1bTmp == C2H_EVT_HOST_CLOSE) { + /* Not ready. */ + return; + } else if (U1bTmp == C2H_EVT_FW_CLOSE) + bCmdMsgReady = _TRUE; + else { + /* Not a valid value, reset the clear event. */ + goto exit; + } + + if (C2hEvent.CmdLen == 0) + goto exit; + tmpBuf = rtw_zmalloc(C2hEvent.CmdLen); + if (tmpBuf == NULL) + goto exit; + + /* Read the content */ + for (index = 0; index < C2hEvent.CmdLen; index++) + tmpBuf[index] = rtw_read8(padapter, REG_C2HEVT_CMD_ID_8188F + 2 + index); + + RT_PRINT_DATA(_module_hal_init_c_, _drv_notice_, "C2HCommandHandler(): Command Content:\n", tmpBuf, C2hEvent.CmdLen); + + /*process_c2h_event(padapter,&C2hEvent, tmpBuf); */ + c2h_handler_8188f(padapter, &C2hEvent); + if (tmpBuf) + rtw_mfree(tmpBuf, C2hEvent.CmdLen); +#endif /* CONFIG_SDIO_HCI || CONFIG_GSPI_HCI */ + +#ifdef CONFIG_USB_HCI + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + _rtw_memset(&C2hEvent, 0, sizeof(C2H_EVT_HDR)); + C2hEvent.CmdID = pHalData->C2hArray[USB_C2H_CMDID_OFFSET] & 0xF; + C2hEvent.CmdLen = (pHalData->C2hArray[USB_C2H_CMDID_OFFSET] & 0xF0) >> 4; + C2hEvent.CmdSeq = pHalData->C2hArray[USB_C2H_SEQ_OFFSET]; + c2h_handler_8188f(padapter, (u8 *)&C2hEvent); + /*process_c2h_event(padapter,&C2hEvent,&pHalData->C2hArray[USB_C2H_EVENT_OFFSET]); */ +#endif /* CONFIG_USB_HCI */ + + /*REG_C2HEVT_CLEAR have done in process_c2h_event */ + return; +exit: + rtw_write8(padapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE); + return; +} + +#endif /* !CONFIG_C2H_PACKET_EN */ + +void rtl8188f_set_pll_ref_clk_sel(_adapter *adapter, u8 sel) +{ + u8 value8; + + value8 = rtw_read8(adapter, REG_MAC_PLL_CTRL_EXT_8188F); + if ((value8 & 0x0F) != (sel & 0x0F)) { + u16 value16; + u8 ori_bit_wlock_2c; + + value16 = rtw_read16(adapter, REG_RSV_CTRL_8188F); + ori_bit_wlock_2c = (value16 & BIT8) ? 1 : 0; + if (ori_bit_wlock_2c) { + value16 &= ~BIT8; + rtw_write16(adapter, REG_RSV_CTRL_8188F, value16); + } + + DBG_871X_LEVEL(_drv_always_, "switch pll_ref_clk_sel from 0x%x to 0x%x\n" + , (value8 & 0x0F), (sel & 0x0F)); + value8 = (value8 & 0xF0) | (sel & 0x0F); + rtw_write8(adapter, REG_MAC_PLL_CTRL_EXT_8188F, value8); + + if (ori_bit_wlock_2c) { + value16 |= BIT8; + rtw_write16(adapter, REG_RSV_CTRL_8188F, value16); + } + } +} + +void SetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + u8 val8; + u16 val16; + u32 val32; + + _func_enter_; + + switch (variable) { + case HW_VAR_MEDIA_STATUS: + val8 = rtw_read8(padapter, MSR) & 0x0c; + val8 |= *val; + rtw_write8(padapter, MSR, val8); + break; + + case HW_VAR_MEDIA_STATUS1: + val8 = rtw_read8(padapter, MSR) & 0x03; + val8 |= *val << 2; + rtw_write8(padapter, MSR, val8); + break; + + case HW_VAR_SET_OPMODE: + hw_var_set_opmode(padapter, variable, val); + break; + + case HW_VAR_MAC_ADDR: + hw_var_set_macaddr(padapter, variable, val); + break; + + case HW_VAR_BSSID: + hw_var_set_bssid(padapter, variable, val); + break; + + case HW_VAR_BASIC_RATE: { + struct mlme_ext_info *mlmext_info = &padapter->mlmeextpriv.mlmext_info; + u16 input_b = 0, masked = 0, ioted = 0, BrateCfg = 0; + u16 rrsr_2g_force_mask = RRSR_CCK_RATES; + u16 rrsr_2g_allow_mask = (RRSR_24M | RRSR_12M | RRSR_6M | RRSR_CCK_RATES); + + HalSetBrateCfg(padapter, val, &BrateCfg); + input_b = BrateCfg; + + /* apply force and allow mask */ + BrateCfg |= rrsr_2g_force_mask; + BrateCfg &= rrsr_2g_allow_mask; + masked = BrateCfg; + +#ifdef CONFIG_CMCC_TEST + BrateCfg |= (RRSR_11M | RRSR_5_5M | RRSR_1M); /* use 11M to send ACK */ + BrateCfg |= (RRSR_24M | RRSR_18M | RRSR_12M); /*CMCC_OFDM_ACK 12/18/24M */ +#endif + + /* IOT consideration */ + if (mlmext_info->assoc_AP_vendor == HT_IOT_PEER_CISCO) { + /* if peer is cisco and didn't use ofdm rate, we enable 6M ack */ + if ((BrateCfg & (RRSR_24M | RRSR_12M | RRSR_6M)) == 0) + BrateCfg |= RRSR_6M; + } + ioted = BrateCfg; + + pHalData->BasicRateSet = BrateCfg; + + DBG_8192C("HW_VAR_BASIC_RATE: %#x -> %#x -> %#x\n", input_b, masked, ioted); + + /* Set RRSR rate table. */ + rtw_write16(padapter, REG_RRSR, BrateCfg); + rtw_write8(padapter, REG_RRSR + 2, rtw_read8(padapter, REG_RRSR + 2) & 0xf0); + } + break; + + case HW_VAR_TXPAUSE: + rtw_write8(padapter, REG_TXPAUSE, *val); + break; + + case HW_VAR_BCN_FUNC: + hw_var_set_bcn_func(padapter, variable, val); + break; + + case HW_VAR_CORRECT_TSF: + hw_var_set_correct_tsf(padapter, variable, val); + break; + + case HW_VAR_CHECK_BSSID: { + u32 val32; + + val32 = rtw_read32(padapter, REG_RCR); + if (*val) + val32 |= RCR_CBSSID_DATA | RCR_CBSSID_BCN; + else + val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN); + rtw_write32(padapter, REG_RCR, val32); + } + break; + + case HW_VAR_MLME_DISCONNECT: + hw_var_set_mlme_disconnect(padapter, variable, val); + break; + + case HW_VAR_MLME_SITESURVEY: + hw_var_set_mlme_sitesurvey(padapter, variable, val); + +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_ScanNotify(padapter, *val ? _TRUE : _FALSE); +#endif /* CONFIG_BT_COEXIST */ + break; + + case HW_VAR_MLME_JOIN: + hw_var_set_mlme_join(padapter, variable, val); + +#ifdef CONFIG_BT_COEXIST + switch (*val) { + case 0: + /* prepare to join */ + rtw_btcoex_ConnectNotify(padapter, _TRUE); + break; + case 1: + /* joinbss_event callback when join res < 0 */ + rtw_btcoex_ConnectNotify(padapter, _FALSE); + break; + case 2: + /* sta add event callback */ + /*rtw_btcoex_MediaStatusNotify(padapter, RT_MEDIA_CONNECT); */ + break; + } +#endif /* CONFIG_BT_COEXIST */ + break; + + case HW_VAR_ON_RCR_AM: + val32 = rtw_read32(padapter, REG_RCR); + val32 |= RCR_AM; + rtw_write32(padapter, REG_RCR, val32); + DBG_8192C("%s, %d, RCR= %x\n", __func__, __LINE__, rtw_read32(padapter, REG_RCR)); + break; + + case HW_VAR_OFF_RCR_AM: + val32 = rtw_read32(padapter, REG_RCR); + val32 &= ~RCR_AM; + rtw_write32(padapter, REG_RCR, val32); + DBG_8192C("%s, %d, RCR= %x\n", __func__, __LINE__, rtw_read32(padapter, REG_RCR)); + break; + + case HW_VAR_BEACON_INTERVAL: + rtw_write16(padapter, REG_BCN_INTERVAL, *((u16 *)val)); + break; + + case HW_VAR_SLOT_TIME: + rtw_write8(padapter, REG_SLOT, *val); + break; + + case HW_VAR_RESP_SIFS: +#if 0 + /* SIFS for OFDM Data ACK */ + rtw_write8(padapter, REG_SIFS_CTX + 1, val[0]); + /* SIFS for OFDM consecutive tx like CTS data! */ + rtw_write8(padapter, REG_SIFS_TRX + 1, val[1]); + + rtw_write8(padapter, REG_SPEC_SIFS + 1, val[0]); + rtw_write8(padapter, REG_MAC_SPEC_SIFS + 1, val[0]); + + /* 20100719 Joseph: Revise SIFS setting due to Hardware register definition change. */ + rtw_write8(padapter, REG_R2T_SIFS + 1, val[0]); + rtw_write8(padapter, REG_T2T_SIFS + 1, val[0]); + +#else + /*SIFS_Timer = 0x0a0a0808; */ + /*RESP_SIFS for CCK */ + rtw_write8(padapter, REG_RESP_SIFS_CCK, val[0]); /* SIFS_T2T_CCK (0x08) */ + rtw_write8(padapter, REG_RESP_SIFS_CCK + 1, val[1]); /*SIFS_R2T_CCK(0x08) */ + /*RESP_SIFS for OFDM */ + rtw_write8(padapter, REG_RESP_SIFS_OFDM, val[2]); /*SIFS_T2T_OFDM (0x0a) */ + rtw_write8(padapter, REG_RESP_SIFS_OFDM + 1, val[3]); /*SIFS_R2T_OFDM(0x0a) */ +#endif + break; + + case HW_VAR_ACK_PREAMBLE: { + u8 regTmp; + u8 bShortPreamble = *val; + + /* Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily) */ + /*regTmp = (pHalData->nCur40MhzPrimeSC)<<5; */ + regTmp = 0; + if (bShortPreamble) + regTmp |= 0x80; + rtw_write8(padapter, REG_RRSR + 2, regTmp); + } + break; + + case HW_VAR_CAM_EMPTY_ENTRY: { + u8 ucIndex = *val; + u8 i; + u32 ulCommand = 0; + u32 ulContent = 0; + u32 ulEncAlgo = CAM_AES; + + for (i = 0; i < CAM_CONTENT_COUNT; i++) { + /* filled id in CAM config 2 byte */ + if (i == 0) { + ulContent |= (ucIndex & 0x03) | ((u16)(ulEncAlgo) << 2); + /*ulContent |= CAM_VALID; */ + } else + ulContent = 0; + /* polling bit, and No Write enable, and address */ + ulCommand = CAM_CONTENT_COUNT * ucIndex + i; + ulCommand = ulCommand | CAM_POLLINIG | CAM_WRITE; + /* write content 0 is equall to mark invalid */ + rtw_write32(padapter, WCAMI, ulContent); /*delay_ms(40); */ + /*RT_TRACE(COMP_SEC, DBG_LOUD, ("CAM_empty_entry(): WRITE A4: %lx\n",ulContent)); */ + rtw_write32(padapter, RWCAM, ulCommand); /*delay_ms(40); */ + /*RT_TRACE(COMP_SEC, DBG_LOUD, ("CAM_empty_entry(): WRITE A0: %lx\n",ulCommand)); */ + } + } + break; + + case HW_VAR_CAM_INVALID_ALL: + rtw_write32(padapter, RWCAM, BIT(31) | BIT(30)); + break; + + case HW_VAR_AC_PARAM_VO: + rtw_write32(padapter, REG_EDCA_VO_PARAM, *((u32 *)val)); + break; + + case HW_VAR_AC_PARAM_VI: + rtw_write32(padapter, REG_EDCA_VI_PARAM, *((u32 *)val)); + break; + + case HW_VAR_AC_PARAM_BE: + pHalData->AcParam_BE = ((u32 *)(val))[0]; + rtw_write32(padapter, REG_EDCA_BE_PARAM, *((u32 *)val)); + break; + + case HW_VAR_AC_PARAM_BK: + rtw_write32(padapter, REG_EDCA_BK_PARAM, *((u32 *)val)); + break; + + case HW_VAR_ACM_CTRL: { + u8 ctrl = *((u8 *)val); + u8 hwctrl = 0; + + if (ctrl != 0) { + hwctrl |= AcmHw_HwEn; + + if (ctrl & BIT(1)) /* BE */ + hwctrl |= AcmHw_BeqEn; + + if (ctrl & BIT(2)) /* VI */ + hwctrl |= AcmHw_ViqEn; + + if (ctrl & BIT(3)) /* VO */ + hwctrl |= AcmHw_VoqEn; + } + + DBG_8192C("[HW_VAR_ACM_CTRL] Write 0x%02X\n", hwctrl); + rtw_write8(padapter, REG_ACMHWCTRL, hwctrl); + } + break; + + case HW_VAR_AMPDU_FACTOR: { + u32 AMPDULen = (*((u8 *)val)); + + if (AMPDULen < HT_AGG_SIZE_32K) + AMPDULen = (0x2000 << (*((u8 *)val))) - 1; + else + AMPDULen = 0x7fff; + + rtw_write32(padapter, REG_AMPDU_MAX_LENGTH_8188F, AMPDULen); + } + break; + +#if 0 + case HW_VAR_RXDMA_AGG_PG_TH: + rtw_write8(padapter, REG_RXDMA_AGG_PG_TH, *val); + break; +#endif + + case HW_VAR_H2C_FW_PWRMODE: { + u8 psmode = *val; + + /* Forece leave RF low power mode for 1T1R to prevent conficting setting in Fw power */ + /* saving sequence. 2010.06.07. Added by tynli. Suggested by SD3 yschang. */ + if (psmode != PS_MODE_ACTIVE) + ODM_RF_Saving(&pHalData->odmpriv, _TRUE); + + /*if (psmode != PS_MODE_ACTIVE) { */ + /* rtl8188f_set_lowpwr_lps_cmd(padapter, _TRUE); */ + /*} else { */ + /* rtl8188f_set_lowpwr_lps_cmd(padapter, _FALSE); */ + /*} */ + rtl8188f_set_FwPwrMode_cmd(padapter, psmode); + } + break; + case HW_VAR_H2C_PS_TUNE_PARAM: + rtl8188f_set_FwPsTuneParam_cmd(padapter); + break; + + case HW_VAR_H2C_FW_JOINBSSRPT: + rtl8188f_set_FwJoinBssRpt_cmd(padapter, *val); + break; + +#ifdef CONFIG_P2P + case HW_VAR_H2C_FW_P2P_PS_OFFLOAD: + rtl8188f_set_p2p_ps_offload_cmd(padapter, *val); + break; +#endif /*CONFIG_P2P */ +#ifdef CONFIG_TDLS + case HW_VAR_TDLS_WRCR: + rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR) & (~RCR_CBSSID_DATA)); + break; + case HW_VAR_TDLS_RS_RCR: + rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR) | (RCR_CBSSID_DATA)); + break; +#endif /*CONFIG_TDLS */ + + case HW_VAR_EFUSE_USAGE: + pHalData->EfuseUsedPercentage = *val; + break; + + case HW_VAR_EFUSE_BYTES: + pHalData->EfuseUsedBytes = *((u16 *)val); + break; + + case HW_VAR_EFUSE_BT_USAGE: +#ifdef HAL_EFUSE_MEMORY + pHalData->EfuseHal.BTEfuseUsedPercentage = *val; +#endif + break; + + case HW_VAR_EFUSE_BT_BYTES: +#ifdef HAL_EFUSE_MEMORY + pHalData->EfuseHal.BTEfuseUsedBytes = *((u16 *)val); +#else + BTEfuseUsedBytes = *((u16 *)val); +#endif + break; + + case HW_VAR_FIFO_CLEARN_UP: { +#define RW_RELEASE_EN BIT(18) +#define RXDMA_IDLE BIT(17) + + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + u8 trycnt = 100; + + /* pause tx */ + rtw_write8(padapter, REG_TXPAUSE, 0xff); + + /* keep sn */ + padapter->xmitpriv.nqos_ssn = rtw_read16(padapter, REG_NQOS_SEQ); + + if (pwrpriv->bkeepfwalive != _TRUE) { + /* RX DMA stop */ + val32 = rtw_read32(padapter, REG_RXPKT_NUM); + val32 |= RW_RELEASE_EN; + rtw_write32(padapter, REG_RXPKT_NUM, val32); + do { + val32 = rtw_read32(padapter, REG_RXPKT_NUM); + val32 &= RXDMA_IDLE; + if (val32) + break; + + DBG_871X("%s: [HW_VAR_FIFO_CLEARN_UP] val=%x times:%d\n", __func__, val32, trycnt); + } while (--trycnt); + if (trycnt == 0) + DBG_8192C("[HW_VAR_FIFO_CLEARN_UP] Stop RX DMA failed......\n"); + + /* RQPN Load 0 */ + rtw_write16(padapter, REG_RQPN_NPQ, 0); + rtw_write32(padapter, REG_RQPN, 0x80000000); + rtw_mdelay_os(2); + } + } + break; + + case HW_VAR_RESTORE_HW_SEQ: + /* restore Sequence No. */ + rtw_write8(padapter, 0x4dc, padapter->xmitpriv.nqos_ssn); + break; + +#ifdef CONFIG_CONCURRENT_MODE + case HW_VAR_CHECK_TXBUF: { + u32 i; + u8 RetryLimit = 0x01; + u32 reg_200, reg_204; + + val16 = RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT; + rtw_write16(padapter, REG_RL, val16); + + for (i = 0; i < 200; i++) { /* polling 200x10=2000 msec */ + reg_200 = rtw_read32(padapter, 0x200); + reg_204 = rtw_read32(padapter, 0x204); + if (reg_200 != reg_204) { + /*DBG_871X("packet in tx packet buffer - 0x204=%x, 0x200=%x (%d)\n", rtw_read32(padapter, 0x204), rtw_read32(padapter, 0x200), i); */ + rtw_msleep_os(10); + } else { + DBG_871X("[HW_VAR_CHECK_TXBUF] no packet in tx packet buffer (%d)\n", i); + break; + } + } + + if (reg_200 != reg_204) + DBG_871X("packets in tx buffer - 0x204=%x, 0x200=%x\n", reg_204, reg_200); + + RetryLimit = 0x30; + val16 = RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT; + rtw_write16(padapter, REG_RL, val16); + } + break; +#endif /* CONFIG_CONCURRENT_MODE */ + + case HW_VAR_APFM_ON_MAC: + pHalData->bMacPwrCtrlOn = *val; + DBG_871X("%s: bMacPwrCtrlOn=%d\n", __func__, pHalData->bMacPwrCtrlOn); + break; + + case HW_VAR_HCI_SUS_STATE: + pHalData->hci_sus_state = *val; + DBG_871X("%s: hci_sus_state=%u\n", __func__, pHalData->hci_sus_state); + break; + + case HW_VAR_NAV_UPPER: { + u32 usNavUpper = *((u32 *)val); + + if (usNavUpper > HAL_NAV_UPPER_UNIT_8188F * 0xFF) { + RT_TRACE(_module_hal_init_c_, _drv_notice_, ("The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n", usNavUpper, HAL_NAV_UPPER_UNIT_8188F)); + break; + } + + /* The value of ((usNavUpper + HAL_NAV_UPPER_UNIT_8188F - 1) / HAL_NAV_UPPER_UNIT_8188F) */ + /* is getting the upper integer. */ + usNavUpper = (usNavUpper + HAL_NAV_UPPER_UNIT_8188F - 1) / HAL_NAV_UPPER_UNIT_8188F; + rtw_write8(padapter, REG_NAV_UPPER, (u8)usNavUpper); + } + break; + +#ifndef CONFIG_C2H_PACKET_EN + case HW_VAR_C2H_HANDLE: + C2HCommandHandler(padapter); + break; +#endif + + case HW_VAR_BCN_VALID: +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->iface_type == IFACE_PORT1) { + val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8188F + 2); + val8 |= BIT(0); + rtw_write8(padapter, REG_DWBCN1_CTRL_8188F + 2, val8); + } else +#endif /* CONFIG_CONCURRENT_MODE */ + { + /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw */ + val8 = rtw_read8(padapter, REG_TDECTRL + 2); + val8 |= BIT(0); + rtw_write8(padapter, REG_TDECTRL + 2, val8); + } + break; + + case HW_VAR_DL_BCN_SEL: +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->iface_type == IFACE_PORT1) { + /* SW_BCN_SEL - Port1 */ + val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8188F + 2); + val8 |= BIT(4); + rtw_write8(padapter, REG_DWBCN1_CTRL_8188F + 2, val8); + } else +#endif /* CONFIG_CONCURRENT_MODE */ + { + /* SW_BCN_SEL - Port0 */ + val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8188F + 2); + val8 &= ~BIT(4); + rtw_write8(padapter, REG_DWBCN1_CTRL_8188F + 2, val8); + } + break; + + case HW_VAR_DO_IQK: + if (*val) + pHalData->bNeedIQK = _TRUE; + else + pHalData->bNeedIQK = _FALSE; + break; + + case HW_VAR_DL_RSVD_PAGE: +#ifdef CONFIG_BT_COEXIST + if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) + rtl8188f_download_BTCoex_AP_mode_rsvd_page(padapter); + else +#endif /* CONFIG_BT_COEXIST */ + { + rtl8188f_download_rsvd_page(padapter, RT_MEDIA_CONNECT); + } + break; + + case HW_VAR_MACID_SLEEP: { + /* TODO: 16 MACID? */ + u32 reg_macid_sleep; + u8 bit_shift; + u8 id = *(u8 *)val; + + if (id < 32) { + reg_macid_sleep = REG_MACID_SLEEP; + bit_shift = id; + } else if (id < 64) { + reg_macid_sleep = REG_MACID_SLEEP_1; + bit_shift = id - 32; + } else if (id < 96) { + reg_macid_sleep = REG_MACID_SLEEP_2; + bit_shift = id - 64; + } else if (id < 128) { + reg_macid_sleep = REG_MACID_SLEEP_3; + bit_shift = id - 96; + } else { + rtw_warn_on(1); + break; + } + + val32 = rtw_read32(padapter, reg_macid_sleep); + DBG_8192C(FUNC_ADPT_FMT ": [HW_VAR_MACID_SLEEP] macid=%d, org reg_0x%03x=0x%08X\n", + FUNC_ADPT_ARG(padapter), id, reg_macid_sleep, val32); + + if (val32 & BIT(bit_shift)) + break; + + val32 |= BIT(bit_shift); + rtw_write32(padapter, reg_macid_sleep, val32); + } + break; + + case HW_VAR_MACID_WAKEUP: { + /* TODO: 16 MACID? */ + u32 reg_macid_sleep; + u8 bit_shift; + u8 id = *(u8 *)val; + + if (id < 32) { + reg_macid_sleep = REG_MACID_SLEEP; + bit_shift = id; + } else if (id < 64) { + reg_macid_sleep = REG_MACID_SLEEP_1; + bit_shift = id - 32; + } else if (id < 96) { + reg_macid_sleep = REG_MACID_SLEEP_2; + bit_shift = id - 64; + } else if (id < 128) { + reg_macid_sleep = REG_MACID_SLEEP_3; + bit_shift = id - 96; + } else { + rtw_warn_on(1); + break; + } + + val32 = rtw_read32(padapter, reg_macid_sleep); + DBG_8192C(FUNC_ADPT_FMT ": [HW_VAR_MACID_WAKEUP] macid=%d, org reg_0x%03x=0x%08X\n", + FUNC_ADPT_ARG(padapter), id, reg_macid_sleep, val32); + + if (!(val32 & BIT(bit_shift))) + break; + + val32 &= ~BIT(bit_shift); + rtw_write32(padapter, reg_macid_sleep, val32); + } + break; +#ifdef CONFIG_GPIO_WAKEUP + case HW_SET_GPIO_WL_CTRL: { + u8 enable = *val; + u8 value = rtw_read8(padapter, 0x4e); + + if (enable && (value & BIT(6))) { + value &= ~BIT(6); + rtw_write8(padapter, 0x4e, value); + } else if (enable == _FALSE) { + value |= BIT(6); + rtw_write8(padapter, 0x4e, value); + } + DBG_871X("%s: set WL control, 0x4E=0x%02X\n", + __func__, rtw_read8(padapter, 0x4e)); + } + break; +#endif + case HW_VAR_EN_HW_UPDATE_TSF: + hw_var_set_hw_update_tsf(padapter); + break; +#ifdef CONFIG_TDLS +#ifdef CONFIG_TDLS_CH_SW + case HW_VAR_TDLS_BCN_EARLY_C2H_RPT: + rtl8188f_set_BcnEarly_C2H_Rpt_cmd(padapter, *val); + break; +#endif +#endif + default: + SetHwReg(padapter, variable, val); + break; + } + + _func_exit_; +} + +struct qinfo_8188f { + u32 head: 8; + u32 pkt_num: 7; + u32 tail: 8; + u32 ac: 2; + u32 macid: 7; +}; + +struct bcn_qinfo_8188f { + u16 head: 8; + u16 pkt_num: 8; +}; + +void dump_qinfo_8188f(void *sel, struct qinfo_8188f *info, const char *tag) +{ + /*if (info->pkt_num) */ + DBG_871X_SEL_NL(sel, "%shead:0x%02x, tail:0x%02x, pkt_num:%u, macid:%u, ac:%u\n" + , tag ? tag : "", info->head, info->tail, info->pkt_num, info->macid, info->ac + ); +} + +void dump_bcn_qinfo_8188f(void *sel, struct bcn_qinfo_8188f *info, const char *tag) +{ + /*if (info->pkt_num) */ + DBG_871X_SEL_NL(sel, "%shead:0x%02x, pkt_num:%u\n" + , tag ? tag : "", info->head, info->pkt_num + ); +} + +void dump_mac_qinfo_8188f(void *sel, _adapter *adapter) +{ + u32 q0_info; + u32 q1_info; + u32 q2_info; + u32 q3_info; + u32 q4_info; + u32 q5_info; + u32 q6_info; + u32 q7_info; + u32 mg_q_info; + u32 hi_q_info; + u16 bcn_q_info; + + q0_info = rtw_read32(adapter, REG_Q0_INFO); + q1_info = rtw_read32(adapter, REG_Q1_INFO); + q2_info = rtw_read32(adapter, REG_Q2_INFO); + q3_info = rtw_read32(adapter, REG_Q3_INFO); + q4_info = rtw_read32(adapter, REG_Q4_INFO); + q5_info = rtw_read32(adapter, REG_Q5_INFO); + q6_info = rtw_read32(adapter, REG_Q6_INFO); + q7_info = rtw_read32(adapter, REG_Q7_INFO); + mg_q_info = rtw_read32(adapter, REG_MGQ_INFO); + hi_q_info = rtw_read32(adapter, REG_HGQ_INFO); + bcn_q_info = rtw_read16(adapter, REG_BCNQ_INFO); + + dump_qinfo_8188f(sel, (struct qinfo_8188f *)&q0_info, "Q0 "); + dump_qinfo_8188f(sel, (struct qinfo_8188f *)&q1_info, "Q1 "); + dump_qinfo_8188f(sel, (struct qinfo_8188f *)&q2_info, "Q2 "); + dump_qinfo_8188f(sel, (struct qinfo_8188f *)&q3_info, "Q3 "); + dump_qinfo_8188f(sel, (struct qinfo_8188f *)&q4_info, "Q4 "); + dump_qinfo_8188f(sel, (struct qinfo_8188f *)&q5_info, "Q5 "); + dump_qinfo_8188f(sel, (struct qinfo_8188f *)&q6_info, "Q6 "); + dump_qinfo_8188f(sel, (struct qinfo_8188f *)&q7_info, "Q7 "); + dump_qinfo_8188f(sel, (struct qinfo_8188f *)&mg_q_info, "MG "); + dump_qinfo_8188f(sel, (struct qinfo_8188f *)&hi_q_info, "HI "); + dump_bcn_qinfo_8188f(sel, (struct bcn_qinfo_8188f *)&bcn_q_info, "BCN "); +} + +void GetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + u8 val8; + u16 val16; + u32 val32; + + + switch (variable) { + case HW_VAR_TXPAUSE: + *val = rtw_read8(padapter, REG_TXPAUSE); + break; + + case HW_VAR_BCN_VALID: +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->iface_type == IFACE_PORT1) { + val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8188F + 2); + *val = (BIT(0) & val8) ? _TRUE : _FALSE; + } else +#endif + { + /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2 */ + val8 = rtw_read8(padapter, REG_TDECTRL + 2); + *val = (BIT(0) & val8) ? _TRUE : _FALSE; + } + break; + + case HW_VAR_FWLPS_RF_ON: { + /* When we halt NIC, we should check if FW LPS is leave. */ + u32 valRCR; + + if ((rtw_is_surprise_removed(padapter)) || + (adapter_to_pwrctl(padapter)->rf_pwrstate == rf_off)) { + /* If it is in HW/SW Radio OFF or IPS state, we do not check Fw LPS Leave, */ + /* because Fw is unload. */ + *val = _TRUE; + } else { + valRCR = rtw_read32(padapter, REG_RCR); + valRCR &= 0x00070000; + if (valRCR) + *val = _FALSE; + else + *val = _TRUE; + } + } + break; + + case HW_VAR_EFUSE_USAGE: + *val = pHalData->EfuseUsedPercentage; + break; + + case HW_VAR_EFUSE_BYTES: + *((u16 *)val) = pHalData->EfuseUsedBytes; + break; + + case HW_VAR_EFUSE_BT_USAGE: +#ifdef HAL_EFUSE_MEMORY + *val = pHalData->EfuseHal.BTEfuseUsedPercentage; +#endif + break; + + case HW_VAR_EFUSE_BT_BYTES: +#ifdef HAL_EFUSE_MEMORY + *((u16 *)val) = pHalData->EfuseHal.BTEfuseUsedBytes; +#else + *((u16 *)val) = BTEfuseUsedBytes; +#endif + break; + + case HW_VAR_APFM_ON_MAC: + *val = pHalData->bMacPwrCtrlOn; + break; + case HW_VAR_HCI_SUS_STATE: + *val = pHalData->hci_sus_state; + break; + case HW_VAR_CHK_HI_QUEUE_EMPTY: + val16 = rtw_read16(padapter, REG_TXPKT_EMPTY); + *val = (val16 & BIT(10)) ? _TRUE : _FALSE; + break; + case HW_VAR_DUMP_MAC_QUEUE_INFO: + dump_mac_qinfo_8188f(val, padapter); + break; + default: + GetHwReg(padapter, variable, val); + break; + } +} + +/* + * Description: + * Change default setting of specified variable. + */ +u8 SetHalDefVar8188F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval) +{ + PHAL_DATA_TYPE pHalData; + u8 bResult; + + + pHalData = GET_HAL_DATA(padapter); + bResult = _SUCCESS; + + switch (variable) { + default: + bResult = SetHalDefVar(padapter, variable, pval); + break; + } + + return bResult; +} + +#ifdef CONFIG_C2H_PACKET_EN +void SetHwRegWithBuf8188F(PADAPTER padapter, u8 variable, u8 *pbuf, int len) +{ + PHAL_DATA_TYPE pHalData; + + _func_enter_; + + pHalData = GET_HAL_DATA(padapter); + + switch (variable) { + case HW_VAR_C2H_HANDLE: + C2HPacketHandler_8188F(padapter, pbuf, len); + break; + + default: + break; + } + _func_exit_; +} +#endif /* CONFIG_C2H_PACKET_EN */ + +void hal_ra_info_dump(_adapter *padapter , void *sel) +{ + int i; + u8 mac_id; + u32 cmd; + u32 ra_info1, ra_info2, bw_set; + u32 rate_mask1, rate_mask2; + u8 curr_tx_rate, curr_tx_sgi, hight_rate, lowest_rate; + HAL_DATA_TYPE *HalData = GET_HAL_DATA(padapter); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + + for (i = 0; i < macid_ctl->num; i++) { + + if (rtw_macid_is_used(macid_ctl, i) && !rtw_macid_is_bmc(macid_ctl, i)) { + + mac_id = (u8) i; + DBG_871X_SEL(sel , "============ RA status check Mac_id:%d ===================\n", mac_id); + + cmd = 0x40000100 | mac_id; + rtw_write32(padapter, REG_HMEBOX_DBG_2_8188F, cmd); + rtw_msleep_os(10); + ra_info1 = rtw_read32(padapter, 0x2F0); + curr_tx_rate = ra_info1 & 0x7F; + curr_tx_sgi = (ra_info1 >> 7) & 0x01; + + DBG_871X_SEL(sel , "[ ra_info1:0x%08x ] =>cur_tx_rate= %s,cur_sgi:%d\n" , ra_info1 , HDATA_RATE(curr_tx_rate), curr_tx_sgi); + DBG_871X_SEL(sel , "[ ra_info1:0x%08x ] => PWRSTS = 0x%02x\n", ra_info1, (ra_info1 >> 8) & 0x07); + + cmd = 0x40000400 | mac_id; + rtw_write32(padapter, REG_HMEBOX_DBG_2_8188F, cmd); + rtw_msleep_os(10); + ra_info1 = rtw_read32(padapter, 0x2F0); + ra_info2 = rtw_read32(padapter, 0x2F4); + rate_mask1 = rtw_read32(padapter, 0x2F8); + rate_mask2 = rtw_read32(padapter, 0x2FC); + hight_rate = ra_info2 & 0xFF; + lowest_rate = (ra_info2 >> 8) & 0xFF; + bw_set = (ra_info1 >> 8) & 0xFF; + + DBG_871X_SEL(sel , "[ ra_info1:0x%08x ] => VHT_EN=0x%02x, ", ra_info1, (ra_info1>>24) & 0xFF); + + switch (bw_set) { + + case CHANNEL_WIDTH_20: + DBG_871X_SEL(sel , "BW_setting=20M\n"); + break; + + case CHANNEL_WIDTH_40: + DBG_871X_SEL(sel , "BW_setting=40M\n"); + break; + + case CHANNEL_WIDTH_80: + DBG_871X_SEL(sel , "BW_setting=80M\n"); + break; + + case CHANNEL_WIDTH_160: + DBG_871X_SEL(sel , "BW_setting=160M\n"); + break; + + default: + DBG_871X_SEL(sel , "BW_setting=0x%02x\n", bw_set); + break; + + } + + DBG_871X_SEL(sel , "[ ra_info1:0x%08x ] =>RSSI=%d, DISRA=0x%02x\n", + ra_info1, + ra_info1 & 0xFF, + (ra_info1 >> 16) & 0xFF); + + DBG_871X_SEL(sel , "[ ra_info2:0x%08x ] =>hight_rate=%s, lowest_rate=%s, SGI=0x%02x, RateID=%d\n", + ra_info2, + HDATA_RATE(hight_rate), + HDATA_RATE(lowest_rate), + (ra_info2 >> 16) & 0xFF, + (ra_info2 >> 24) & 0xFF); + + DBG_871X_SEL(sel , "rate_mask2=0x%08x, rate_mask1=0x%08x\n", rate_mask2, rate_mask1); + + + } + } +} + +/* + * Description: + * Query setting of specified variable. + */ +u8 GetHalDefVar8188F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval) +{ + PHAL_DATA_TYPE pHalData; + u8 bResult; + + + pHalData = GET_HAL_DATA(padapter); + bResult = _SUCCESS; + + switch (variable) { + case HAL_DEF_MAX_RECVBUF_SZ: + *((u32 *)pval) = MAX_RECVBUF_SZ; + break; + + case HAL_DEF_RX_PACKET_OFFSET: + *((u32 *)pval) = RXDESC_SIZE + DRVINFO_SZ * 8; + break; + + case HW_VAR_MAX_RX_AMPDU_FACTOR: + /* Stanley@BB.SD3 suggests 16K can get stable performance */ + /* The experiment was done on SDIO interface */ + /* coding by Lucas@20130730 */ + *(HT_CAP_AMPDU_FACTOR *)pval = MAX_AMPDU_FACTOR_16K; + break; + case HW_VAR_BEST_AMPDU_DENSITY: + *((u32 *)pval) = AMPDU_DENSITY_VALUE_7; + break; + case HAL_DEF_TX_LDPC: + case HAL_DEF_RX_LDPC: + *((u8 *)pval) = _FALSE; + break; + case HAL_DEF_TX_STBC: + *((u8 *)pval) = 0; + break; + case HAL_DEF_RX_STBC: + *((u8 *)pval) = 1; + break; + case HAL_DEF_EXPLICIT_BEAMFORMER: + case HAL_DEF_EXPLICIT_BEAMFORMEE: + *((u8 *)pval) = _FALSE; + break; + + case HW_DEF_RA_INFO_DUMP: + hal_ra_info_dump(padapter, pval); + break; + + case HAL_DEF_TX_PAGE_BOUNDARY: + if (!padapter->registrypriv.wifi_spec) + *(u8 *)pval = TX_PAGE_BOUNDARY_8188F; + else + *(u8 *)pval = WMM_NORMAL_TX_PAGE_BOUNDARY_8188F; + break; + + case HAL_DEF_MACID_SLEEP: + *(u8 *)pval = _TRUE; /* support macid sleep */ + break; + case HAL_DEF_TX_PAGE_SIZE: + *((u32 *)pval) = PAGE_SIZE_128; + break; + case HAL_DEF_RX_DMA_SZ_WOW: + *(u32 *)pval = RX_DMA_SIZE_8188F - RESV_FMWF; + break; + case HAL_DEF_RX_DMA_SZ: + *(u32 *)pval = RX_DMA_BOUNDARY_8188F + 1; + break; + case HAL_DEF_RX_PAGE_SIZE: + *((u32 *)pval) = 8; + break; + default: + bResult = GetHalDefVar(padapter, variable, pval); + break; + } + + return bResult; +} + + +void rtl8188f_start_thread(_adapter *padapter) +{ +#if (defined CONFIG_SDIO_HCI) || (defined CONFIG_GSPI_HCI) +#ifndef CONFIG_SDIO_TX_TASKLET + struct xmit_priv *xmitpriv = &padapter->xmitpriv; + + xmitpriv->SdioXmitThread = kthread_run(rtl8188fs_xmit_thread, padapter, "RTWHALXT"); + if (IS_ERR(xmitpriv->SdioXmitThread)) + RT_TRACE(_module_hal_xmit_c_, _drv_err_, ("%s: start rtl8188fs_xmit_thread FAIL!!\n", __func__)); +#endif +#endif +} + +void rtl8188f_stop_thread(_adapter *padapter) +{ +#if (defined CONFIG_SDIO_HCI) || (defined CONFIG_GSPI_HCI) +#ifndef CONFIG_SDIO_TX_TASKLET + struct xmit_priv *xmitpriv = &padapter->xmitpriv; + + /* stop xmit_buf_thread */ + if (xmitpriv->SdioXmitThread) { + _rtw_up_sema(&xmitpriv->SdioXmitSema); + _rtw_down_sema(&xmitpriv->SdioXmitTerminateSema); + xmitpriv->SdioXmitThread = 0; + } +#endif +#endif +} + +#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST) +extern void check_bt_status_work(void *data); +void rtl8188fs_init_checkbthang_workqueue(_adapter *adapter) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) + adapter->priv_checkbt_wq = alloc_workqueue("sdio_wq", 0, 0); +#else + adapter->priv_checkbt_wq = create_workqueue("sdio_wq"); +#endif + INIT_DELAYED_WORK(&adapter->checkbt_work, (void *)check_bt_status_work); +} + +void rtl8188fs_free_checkbthang_workqueue(_adapter *adapter) +{ + if (adapter->priv_checkbt_wq) { + cancel_delayed_work_sync(&adapter->checkbt_work); + flush_workqueue(adapter->priv_checkbt_wq); + destroy_workqueue(adapter->priv_checkbt_wq); + adapter->priv_checkbt_wq = NULL; + } +} + +void rtl8188fs_cancle_checkbthang_workqueue(_adapter *adapter) +{ + if (adapter->priv_checkbt_wq) + cancel_delayed_work_sync(&adapter->checkbt_work); +} + +void rtl8188fs_hal_check_bt_hang(_adapter *adapter) +{ + if (adapter->priv_checkbt_wq) + queue_delayed_work(adapter->priv_checkbt_wq, &(adapter->checkbt_work), 0); +} +#endif + + + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_phycfg.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_phycfg.c new file mode 100644 index 000000000..40fe483db --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_phycfg.c @@ -0,0 +1,1487 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTL8188F_PHYCFG_C_ + +#include + + +/*---------------------------Define Local Constant---------------------------*/ +/* Channel switch:The size of command tables for switch channel*/ +#define MAX_PRECMD_CNT 16 +#define MAX_RFDEPENDCMD_CNT 16 +#define MAX_POSTCMD_CNT 16 + +#define MAX_DOZE_WAITING_TIMES_9x 64 + +/*---------------------------Define Local Constant---------------------------*/ + + +/*------------------------Define global variable-----------------------------*/ + +/*------------------------Define local variable------------------------------*/ + + +/*--------------------Define export function prototype-----------------------*/ +/* Please refer to header file */ +/*--------------------Define export function prototype-----------------------*/ + +/*----------------------------Function Body----------------------------------*/ +/* */ +/* 1. BB register R/W API */ +/* */ + +/** +* Function: phy_CalculateBitShift +* +* OverView: Get shifted position of the BitMask +* +* Input: +* u4Byte BitMask, +* +* Output: none +* Return: u4Byte Return the shift bit bit position of the mask +*/ +static u32 +phy_CalculateBitShift( + u32 BitMask +) +{ + u32 i; + + for (i = 0; i <= 31; i++) { + if (((BitMask >> i) & 0x1) == 1) + break; + } + + return (i); +} + + +/** +* Function: PHY_QueryBBReg +* +* OverView: Read "sepcific bits" from BB register +* +* Input: +* PADAPTER Adapter, +* u4Byte RegAddr, The target address to be readback +* u4Byte BitMask The target bit position in the target address +* to be readback +* Output: None +* Return: u4Byte Data The readback register value +* Note: This function is equal to "GetRegSetting" in PHY programming guide +*/ +u32 +PHY_QueryBBReg_8188F( + IN PADAPTER Adapter, + IN u32 RegAddr, + IN u32 BitMask +) +{ + u32 ReturnValue = 0, OriginalValue, BitShift; + u16 BBWaitCounter = 0; + +#if (DISABLE_BB_RF == 1) + return 0; +#endif + + /*RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx)\n", RegAddr, BitMask)); */ + + OriginalValue = rtw_read32(Adapter, RegAddr); + BitShift = phy_CalculateBitShift(BitMask); + ReturnValue = (OriginalValue & BitMask) >> BitShift; + + return (ReturnValue); + +} + + +/** + * Function: PHY_SetBBReg + * + * OverView: Write "Specific bits" to BB register (page 8~) + * + * Input: + * PADAPTER Adapter, + * u4Byte RegAddr, The target address to be modified + * u4Byte BitMask The target bit position in the target address + * to be modified + * u4Byte Data The new register value in the target bit position + * of the target address + * + * Output: None + * Return: None + * Note: This function is equal to "PutRegSetting" in PHY programming guide + */ + +VOID +PHY_SetBBReg_8188F( + IN PADAPTER Adapter, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Data +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + /*u16 BBWaitCounter = 0; */ + u32 OriginalValue, BitShift; + +#if (DISABLE_BB_RF == 1) + return; +#endif + + /*RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data)); */ + + if (BitMask != bMaskDWord) { /*if not "double word" write */ + OriginalValue = rtw_read32(Adapter, RegAddr); + BitShift = phy_CalculateBitShift(BitMask); + Data = ((OriginalValue & (~BitMask)) | ((Data << BitShift) & BitMask)); + } + + rtw_write32(Adapter, RegAddr, Data); +} + + +/* */ +/* 2. RF register R/W API */ +/* */ + +/*----------------------------------------------------------------------------- + * Function: phy_FwRFSerialRead() + * + * Overview: We support firmware to execute RF-R/W. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 01/21/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +static u32 +phy_FwRFSerialRead( + IN PADAPTER Adapter, + IN RF_PATH eRFPath, + IN u32 Offset) +{ + u32 retValue = 0; + /*RT_ASSERT(FALSE,("deprecate!\n")); */ + return (retValue); + +} /* phy_FwRFSerialRead */ + + +/*----------------------------------------------------------------------------- + * Function: phy_FwRFSerialWrite() + * + * Overview: We support firmware to execute RF-R/W. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 01/21/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +static VOID +phy_FwRFSerialWrite( + IN PADAPTER Adapter, + IN RF_PATH eRFPath, + IN u32 Offset, + IN u32 Data) +{ + /*RT_ASSERT(FALSE,("deprecate!\n")); */ +} + +static u32 +phy_RFSerialRead_8188F( + IN PADAPTER Adapter, + IN RF_PATH eRFPath, + IN u32 Offset +) +{ + u32 retValue = 0; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath]; + u32 NewOffset; + u32 tmplong, tmplong2; + u8 RfPiEnable = 0; + u4Byte MaskforPhySet = 0; + int i = 0; + + _enter_critical_mutex(&(adapter_to_dvobj(Adapter)->rf_read_reg_mutex) , NULL); + /* */ + /* Make sure RF register offset is correct */ + /* */ + Offset &= 0xff; + + NewOffset = Offset; + + if (eRFPath == RF_PATH_A) { + tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord); + tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge; /*T65 RF */ + PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge)); + } else { + tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord); + tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset << 23) | bLSSIReadEdge; /*T65 RF */ + PHY_SetBBReg(Adapter, rFPGA0_XB_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge)); + } + + tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord); + PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge)); + PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2 | MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge); + + rtw_udelay_os(10); + + for (i = 0; i < 2; i++) + rtw_udelay_os(MAX_STALL_TIME); + rtw_udelay_os(10); + + if (eRFPath == RF_PATH_A) + RfPiEnable = (u1Byte)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1 | MaskforPhySet, BIT8); + else if (eRFPath == RF_PATH_B) + RfPiEnable = (u1Byte)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1 | MaskforPhySet, BIT8); + + if (RfPiEnable) { + /* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */ + retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi | MaskforPhySet, bLSSIReadBackData); + + /*RT_DISP(FINIT, INIT_RF, ("Readback from RF-PI : 0x%x\n", retValue)); */ + } else { + /*Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */ + retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack | MaskforPhySet, bLSSIReadBackData); + + /*RT_DISP(FINIT, INIT_RF,("Readback from RF-SI : 0x%x\n", retValue)); */ + } + _exit_critical_mutex(&(adapter_to_dvobj(Adapter)->rf_read_reg_mutex) , NULL); + return retValue; + +} + +/** + * Function: phy_RFSerialWrite_8188F + * + * OverView: Write data to RF register (page 8~) + * + * Input: + * PADAPTER Adapter, + * RF_PATH RFPath, Radio path of A/B/C/D + * u4Byte Offset, The target address to be read + * u4Byte Data The new register Data in the target bit position + * of the target to be read + * + * Output: None + * Return: None + * Note: Threre are three types of serial operations: + * 1. Software serial write + * 2. Hardware LSSI-Low Speed Serial Interface + * 3. Hardware HSSI-High speed + * serial write. Driver need to implement (1) and (2). + * This function is equal to the combination of RF_ReadReg() and RFLSSIRead() + * + * Note: For RF8256 only + * The total count of RTL8256(Zebra4) register is around 36 bit it only employs + * 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10]) + * to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration + * programming guide" for more details. + * Thus, we define a sub-finction for RTL8526 register address conversion + * =========================================================== + * Register Mode RegCTL[1] RegCTL[0] Note + * (Reg00[12]) (Reg00[10]) + * =========================================================== + * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf) + * ------------------------------------------------------------------ + * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf) + * ------------------------------------------------------------------ + * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf) + * ------------------------------------------------------------------ + * + * 2008/09/02 MH Add 92S RF definition + * + * + * +*/ +static VOID +phy_RFSerialWrite_8188F( + IN PADAPTER Adapter, + IN RF_PATH eRFPath, + IN u32 Offset, + IN u32 Data +) +{ + u32 DataAndAddr = 0; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath]; + u32 NewOffset; + + Offset &= 0xff; + + /* */ + /* Shadow Update */ + /* */ + /*PHY_RFShadowWrite(Adapter, eRFPath, Offset, Data); */ + + /* */ + /* Switch page for 8256 RF IC */ + /* */ + NewOffset = Offset; + + /* */ + /* Put write addr in [5:0] and write data in [31:16] */ + /* */ + /*DataAndAddr = (Data<<16) | (NewOffset&0x3f); */ + DataAndAddr = ((NewOffset << 20) | (Data & 0x000fffff)) & 0x0fffffff; /* T65 RF */ + + /* */ + /* Write Operation */ + /* */ + PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); + /*RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]=0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr)); */ + +} + + +/** + * Function: PHY_QueryRFReg + * + * OverView: Query "Specific bits" to RF register (page 8~) + * + * Input: + * PADAPTER Adapter, + * RF_PATH eRFPath, Radio path of A/B/C/D + * u4Byte RegAddr, The target address to be read + * u4Byte BitMask The target bit position in the target address + * to be read + * + * Output: None + * Return: u4Byte Readback value + * Note: This function is equal to "GetRFRegSetting" in PHY programming guide + */ +u32 +PHY_QueryRFReg_8188F( + IN PADAPTER Adapter, + IN u8 eRFPath, + IN u32 RegAddr, + IN u32 BitMask +) +{ + u32 Original_Value, Readback_Value, BitShift; + +#if (DISABLE_BB_RF == 1) + return 0; +#endif + + Original_Value = phy_RFSerialRead_8188F(Adapter, eRFPath, RegAddr); + + BitShift = phy_CalculateBitShift(BitMask); + Readback_Value = (Original_Value & BitMask) >> BitShift; + + return (Readback_Value); +} + +/** +* Function: PHY_SetRFReg +* +* OverView: Write "Specific bits" to RF register (page 8~) +* +* Input: +* PADAPTER Adapter, +* RF_PATH eRFPath, Radio path of A/B/C/D +* u4Byte RegAddr, The target address to be modified +* u4Byte BitMask The target bit position in the target address +* to be modified +* u4Byte Data The new register Data in the target bit position +* of the target address +* +* Output: None +* Return: None +* Note: This function is equal to "PutRFRegSetting" in PHY programming guide +*/ +VOID +PHY_SetRFReg_8188F( + IN PADAPTER Adapter, + IN u8 eRFPath, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Data +) +{ + u32 Original_Value, BitShift; + +#if (DISABLE_BB_RF == 1) + return; +#endif + + /* RF data is 12 bits only */ + if (BitMask != bRFRegOffsetMask) { + Original_Value = phy_RFSerialRead_8188F(Adapter, eRFPath, RegAddr); + BitShift = phy_CalculateBitShift(BitMask); + Data = ((Original_Value & (~BitMask)) | (Data << BitShift)); + } + + phy_RFSerialWrite_8188F(Adapter, eRFPath, RegAddr, Data); +} + + +/* */ +/* 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt. */ +/* */ + + +/*----------------------------------------------------------------------------- + * Function: PHY_MACConfig8192C + * + * Overview: Condig MAC by header file or parameter file. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 08/12/2008 MHC Create Version 0. + * + *---------------------------------------------------------------------------*/ +s32 PHY_MACConfig8188F(PADAPTER Adapter) +{ + int rtStatus = _SUCCESS; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + /* */ + /* Config MAC */ + /* */ +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + rtStatus = phy_ConfigMACWithParaFile(Adapter, PHY_FILE_MAC_REG); + if (rtStatus == _FAIL) +#endif + { +#ifdef CONFIG_EMBEDDED_FWIMG + ODM_ConfigMACWithHeaderFile(&pHalData->odmpriv); + rtStatus = _SUCCESS; +#endif/*CONFIG_EMBEDDED_FWIMG */ + } + + return rtStatus; +} + +/** +* Function: phy_InitBBRFRegisterDefinition +* +* OverView: Initialize Register definition offset for Radio Path A/B/C/D +* +* Input: +* PADAPTER Adapter, +* +* Output: None +* Return: None +* Note: The initialization value is constant and it should never be changes +*/ +static VOID +phy_InitBBRFRegisterDefinition( + IN PADAPTER Adapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + /* RF Interface Sowrtware Control */ + pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from 0x870 */ + pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ + + /* RF Interface Output (and Enable) */ + pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x860 */ + pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x864 */ + + /* RF Interface (Output and) Enable */ + pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */ + pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */ + + pHalData->PHYRegDef[ODM_RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; /*LSSI Parameter */ + pHalData->PHYRegDef[ODM_RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; + + pHalData->PHYRegDef[ODM_RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; /*wire control parameter2 */ + pHalData->PHYRegDef[ODM_RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; /*wire control parameter2 */ + + /* Tranceiver Readback LSSI/HSPI mode */ + pHalData->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; + pHalData->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; + pHalData->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback; + pHalData->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback; + +} + +static int +phy_BB8188f_Config_ParaFile( + IN PADAPTER Adapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + int rtStatus = _SUCCESS; + + /* */ + /* 1. Read PHY_REG.TXT BB INIT!! */ + /* */ +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + if (phy_ConfigBBWithParaFile(Adapter, PHY_FILE_PHY_REG, CONFIG_BB_PHY_REG) == _FAIL) +#endif + { +#ifdef CONFIG_EMBEDDED_FWIMG + if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG)) + rtStatus = _FAIL; +#endif + } + + if (rtStatus != _SUCCESS) { + DBG_8192C("%s():Write BB Reg Fail!!", __func__); + goto phy_BB8190_Config_ParaFile_Fail; + } + +#if MP_DRIVER == 1 + if (Adapter->registrypriv.mp_mode == 1) { + /* */ + /* 1.1 Read PHY_REG_MP.TXT BB INIT!! */ + /* */ +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + if (phy_ConfigBBWithMpParaFile(Adapter, PHY_FILE_PHY_REG_MP) == _FAIL) +#endif + { +#ifdef CONFIG_EMBEDDED_FWIMG + if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG_MP)) + rtStatus = _FAIL; +#endif + } + + if (rtStatus != _SUCCESS) { + DBG_8192C("%s():Write BB Reg MP Fail!!", __func__); + goto phy_BB8190_Config_ParaFile_Fail; + } + } +#endif /* #if (MP_DRIVER == 1) */ + + /* */ + /* 2. Read BB AGC table Initialization */ + /* */ +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + if (phy_ConfigBBWithParaFile(Adapter, PHY_FILE_AGC_TAB, CONFIG_BB_AGC_TAB) == _FAIL) +#endif + { +#ifdef CONFIG_EMBEDDED_FWIMG + if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_AGC_TAB)) + rtStatus = _FAIL; +#endif + } + + if (rtStatus != _SUCCESS) { + DBG_8192C("%s():AGC Table Fail\n", __func__); + goto phy_BB8190_Config_ParaFile_Fail; + } + +phy_BB8190_Config_ParaFile_Fail: + + return rtStatus; +} + + +int +PHY_BBConfig8188F( + IN PADAPTER Adapter +) +{ + int rtStatus = _SUCCESS; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u32 RegVal; + u8 TmpU1B = 0; + u8 value8; + + phy_InitBBRFRegisterDefinition(Adapter); + + /* Enable BB and RF */ + RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN); + rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal | BIT13 | BIT0 | BIT1)); + +#if 0 /* TODO: [BB]. reg 948 is only use for bt_coex */ +#ifdef CONFIG_USB_HCI + rtw_write32(Adapter, 0x948, 0x0); /* USB use Antenna S0 */ +#else + if (pHalData->ant_path == ODM_RF_PATH_A) + rtw_write32(Adapter, 0x948, 0x280); + else + rtw_write32(Adapter, 0x948, 0x0); +#endif + +#endif + rtw_write8(Adapter, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB); + + rtw_usleep_os(10); + + PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x1, 0xfffff, 0x780); + +#if 0 + /* 20090923 Joseph: Advised by Steven and Jenyu. Power sequence before init RF. */ + rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x83); + rtw_write8(Adapter, REG_AFE_PLL_CTRL + 1, 0xdb); +#endif + + /* rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB); */ + rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn | FEN_BBRSTB); + + /* Config BB and AGC */ + rtStatus = phy_BB8188f_Config_ParaFile(Adapter); + + hal_set_crystal_cap(Adapter, pHalData->CrystalCap); + + return rtStatus; +} + +#if 0 +/* Block & Path enable */ +#define rOFDMCCKEN_Jaguar 0x808 /* OFDM/CCK block enable */ +#define bOFDMEN_Jaguar 0x20000000 +#define bCCKEN_Jaguar 0x10000000 +#define rRxPath_Jaguar 0x808 /* Rx antenna */ +#define bRxPath_Jaguar 0xff +#define rTxPath_Jaguar 0x80c /* Tx antenna */ +#define bTxPath_Jaguar 0x0fffffff +#define rCCK_RX_Jaguar 0xa04 /* for cck rx path selection */ +#define bCCK_RX_Jaguar 0x0c000000 +#define rVhtlen_Use_Lsig_Jaguar 0x8c3 /* Use LSIG for VHT length */ +VOID +PHY_BB8188F_Config_1T( + IN PADAPTER Adapter +) +{ + /* BB OFDM RX Path_A */ + PHY_SetBBReg(Adapter, rRxPath_Jaguar, bRxPath_Jaguar, 0x11); + /* BB OFDM TX Path_A */ + PHY_SetBBReg(Adapter, rTxPath_Jaguar, bMaskLWord, 0x1111); + /* BB CCK R/Rx Path_A */ + PHY_SetBBReg(Adapter, rCCK_RX_Jaguar, bCCK_RX_Jaguar, 0x0); + /* MCS support */ + PHY_SetBBReg(Adapter, 0x8bc, 0xc0000060, 0x4); + /* RF Path_B HSSI OFF */ + PHY_SetBBReg(Adapter, 0xe00, 0xf, 0x4); + /* RF Path_B Power Down */ + PHY_SetBBReg(Adapter, 0xe90, bMaskDWord, 0); + /* ADDA Path_B OFF */ + PHY_SetBBReg(Adapter, 0xe60, bMaskDWord, 0); + PHY_SetBBReg(Adapter, 0xe64, bMaskDWord, 0); +} +#endif + +int +PHY_RFConfig8188F( + IN PADAPTER Adapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + int rtStatus = _SUCCESS; + + /* */ + /* RF config */ + /* */ + rtStatus = PHY_RF6052_Config8188F(Adapter); + + /*PHY_BB8188F_Config_1T(Adapter); */ + + return rtStatus; +} + +/*----------------------------------------------------------------------------- + * Function: PHY_ConfigRFWithParaFile() + * + * Overview: This function read RF parameters from general file format, and do RF 3-wire + * + * Input: PADAPTER Adapter + * ps1Byte pFileName + * RF_PATH eRFPath + * + * Output: NONE + * + * Return: RT_STATUS_SUCCESS: configuration file exist + * + * Note: Delay may be required for RF configuration + *---------------------------------------------------------------------------*/ +int +PHY_ConfigRFWithParaFile_8188F( + IN PADAPTER Adapter, + IN u8 *pFileName, + RF_PATH eRFPath +) +{ + return _SUCCESS; +} + +/***************************************** */ +/*----------------------------------------------------------------------------- + * Function: PHY_ConfigRFWithHeaderFile() + * + * Overview: This function read RF parameters from general file format, and do RF 3-wire + * + * Input: PADAPTER Adapter + * ps1Byte pFileName + * RF_PATH eRFPath + * + * Output: NONE + * + * Return: RT_STATUS_SUCCESS: configuration file exist + * + * Note: Delay may be required for RF configuration + *---------------------------------------------------------------------------*/ +void phy_PowerIndexCheck8188F( + IN PADAPTER Adapter, + IN u8 channel, + IN OUT u8 *cckPowerLevel, + IN OUT u8 *ofdmPowerLevel, + IN OUT u8 *BW20PowerLevel, + IN OUT u8 *BW40PowerLevel +) +{ + + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + pHalData->CurrentCckTxPwrIdx = cckPowerLevel[0]; + pHalData->CurrentOfdm24GTxPwrIdx = ofdmPowerLevel[0]; + pHalData->CurrentBW2024GTxPwrIdx = BW20PowerLevel[0]; + pHalData->CurrentBW4024GTxPwrIdx = BW40PowerLevel[0]; + + RT_TRACE(_module_hal_init_c_, _drv_info_, + ("PHY_SetTxPowerLevel8188F(): CurrentCckTxPwrIdx : 0x%x,CurrentOfdm24GTxPwrIdx: 0x%x\n", + pHalData->CurrentCckTxPwrIdx, pHalData->CurrentOfdm24GTxPwrIdx)); +} + +/************************************************************************************************************** + * Description: + * The low-level interface to set TxAGC , called by both MP and Normal Driver. + * + * <20120830, Kordan> + **************************************************************************************************************/ + +VOID +PHY_SetTxPowerIndex_8188F( + IN PADAPTER Adapter, + IN u32 PowerIndex, + IN u8 RFPath, + IN u8 Rate +) +{ + if (RFPath == ODM_RF_PATH_A || RFPath == ODM_RF_PATH_B) { + switch (Rate) { + case MGN_1M: + PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, PowerIndex); + break; + case MGN_2M: + PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte1, PowerIndex); + break; + case MGN_5_5M: + PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte2, PowerIndex); + break; + case MGN_11M: + PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte3, PowerIndex); + break; + + case MGN_6M: + PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte0, PowerIndex); + break; + case MGN_9M: + PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte1, PowerIndex); + break; + case MGN_12M: + PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte2, PowerIndex); + break; + case MGN_18M: + PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte3, PowerIndex); + break; + + case MGN_24M: + PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte0, PowerIndex); + break; + case MGN_36M: + PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte1, PowerIndex); + break; + case MGN_48M: + PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte2, PowerIndex); + break; + case MGN_54M: + PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte3, PowerIndex); + break; + + case MGN_MCS0: + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte0, PowerIndex); + break; + case MGN_MCS1: + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte1, PowerIndex); + break; + case MGN_MCS2: + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte2, PowerIndex); + break; + case MGN_MCS3: + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte3, PowerIndex); + break; + + case MGN_MCS4: + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte0, PowerIndex); + break; + case MGN_MCS5: + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte1, PowerIndex); + break; + case MGN_MCS6: + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte2, PowerIndex); + break; + case MGN_MCS7: + PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte3, PowerIndex); + break; + + default: + DBG_871X("Invalid Rate!!\n"); + break; + } + } else + RT_TRACE(_module_hal_init_c_, _drv_err_, ("Invalid RFPath!!\n")); +} + +u8 +phy_GetCurrentTxNum_8188F( + IN PADAPTER pAdapter +) +{ + return RF_TX_NUM_NONIMPLEMENT; +} + +u8 +PHY_GetTxPowerIndex_8188F( + IN PADAPTER pAdapter, + IN u8 RFPath, + IN u8 Rate, + IN CHANNEL_WIDTH BandWidth, + IN u8 Channel +) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter); + s8 txPower = 0, powerDiffByRate = 0, limit = 0; + BOOLEAN bIn24G = _FALSE; + + /*DBG_871X("===>%s\n", __func__ ); */ + + txPower = (s8) PHY_GetTxPowerIndexBase(pAdapter, RFPath, Rate, BandWidth, Channel, &bIn24G); + powerDiffByRate = PHY_GetTxPowerByRate(pAdapter, BAND_ON_2_4G, ODM_RF_PATH_A, RF_1TX, Rate); + + limit = PHY_GetTxPowerLimit(pAdapter, pAdapter->registrypriv.RegPwrTblSel, (u8)(!bIn24G), pHalData->CurrentChannelBW, RFPath, Rate, pHalData->CurrentChannel); + + powerDiffByRate = powerDiffByRate > limit ? limit : powerDiffByRate; + txPower += powerDiffByRate; + + txPower += PHY_GetTxPowerTrackingOffset(pAdapter, RFPath, Rate); + + if (txPower > MAX_POWER_INDEX) + txPower = MAX_POWER_INDEX; + + /*DBG_871X("Final Tx Power(RF-%c, Channel: %d) = %d(0x%X)\n", ((RFPath==0)?'A':'B'), Channel, txPower, txPower)); */ + return (u8) txPower; +} + +VOID +PHY_SetTxPowerLevel8188F( + IN PADAPTER Adapter, + IN u8 Channel +) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + u8 cur_antenna; + u8 RFPath = ODM_RF_PATH_A; + +#ifdef CONFIG_ANTENNA_DIVERSITY + rtw_hal_get_odm_var(Adapter, HAL_ODM_ANTDIV_SELECT, &cur_antenna, NULL); + + if (pHalData->AntDivCfg) /* antenna diversity Enable */ + RFPath = ((cur_antenna == MAIN_ANT) ? ODM_RF_PATH_A : ODM_RF_PATH_B); + else /* antenna diversity disable */ +#endif + RFPath = pHalData->ant_path; + + RT_TRACE(_module_hal_init_c_, _drv_info_, ("==>PHY_SetTxPowerLevel8188F()\n")); + + PHY_SetTxPowerLevelByPath(Adapter, Channel, RFPath); + + RT_TRACE(_module_hal_init_c_, _drv_info_, ("<==PHY_SetTxPowerLevel8188F()\n")); +} + +VOID +PHY_GetTxPowerLevel8188F( + IN PADAPTER Adapter, + OUT s32 *powerlevel +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + s32 TxPwrDbm = 13; +#if 0 + RT_TRACE(COMP_TXAGC, DBG_LOUD, ("PHY_GetTxPowerLevel8188F(): TxPowerLevel: %#x\n", TxPwrDbm)); + + if (pMgntInfo->ClientConfigPwrInDbm != UNSPECIFIED_PWR_DBM) + *powerlevel = pMgntInfo->ClientConfigPwrInDbm; + else + *powerlevel = TxPwrDbm; +#endif +} + + +/* A workaround to eliminate the 2400MHz, 2440MHz, 2480MHz spur of 8188F. (Asked by David.) */ +VOID +phy_SpurCalibration_8188F( + IN PADAPTER pAdapter, + IN u1Byte ToChannel, + IN u1Byte threshold +) +{ + u4Byte freq[7] = {0xFCCD, 0xFC4D, 0xFFCD, 0xFF4D, 0xFCCD, 0xFF9A, 0xFDCD}; /* {chnl 5, 6, 7, 8, 13, 14 , 11} */ + u1Byte idx = 0; + u1Byte b_doNotch = FALSE; + u1Byte initial_gain; + BOOLEAN bHW_Ctrl = FALSE, bSW_Ctrl = FALSE, bHW_Ctrl_S1 = FALSE, bSW_Ctrl_S1 = FALSE; + u4Byte reg948; + + /* add for notch */ + u4Byte wlan_channel, CurrentChannel, Is40MHz; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); + + ODM_SetBBReg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0x1F); + ODM_SetBBReg(pDM_Odm, 0xC40, BIT9, 0x1); /*enable notch filter */ + /* check threshold */ + if (threshold <= 0x0) + threshold = 0x16; + + /* DBG_8192C("===> phy_SpurCalibration_8188F: Channel = %d\n", ToChannel); */ + + if (ToChannel == 5) + idx = 0; + else if (ToChannel == 6) + idx = 1; + else if (ToChannel == 7) + idx = 2; + else if (ToChannel == 8) + idx = 3; + else if (ToChannel == 13) + idx = 4; + else if (ToChannel == 14) + idx = 5; + else if (ToChannel == 11) + idx = 6; + else + idx = 10; + + reg948 = PHY_QueryBBReg(pAdapter, rS0S1_PathSwitch, bMaskDWord); + if ((reg948 & BIT6) == 0x0) + bSW_Ctrl = TRUE; + else + bHW_Ctrl = TRUE; + + if (bHW_Ctrl) + bHW_Ctrl_S1 = (PHY_QueryBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5 | BIT4 | BIT3) == 0x1) ? TRUE : FALSE; + else if (bSW_Ctrl) + bSW_Ctrl_S1 = ((reg948 & BIT9) == 0x0) ? TRUE : FALSE; + + /* If wlan at S1 (both HW control & SW control) and current channel=5,6,7,8,13,14 */ + if ((bHW_Ctrl_S1 || bSW_Ctrl_S1) && (idx <= 6)) { + initial_gain = (u1Byte)(ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0) & 0x7f); + PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, BIT24, 0); /* Disable CCK block */ + ODM_Write_DIG(pDM_Odm, 0x30); + PHY_SetBBReg(pAdapter, rFPGA0_AnalogParameter4, bMaskDWord, 0xccf000c0); /* disable 3-wire */ + + PHY_SetBBReg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, freq[idx]); /* Setup PSD */ + PHY_SetBBReg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, 0x400000 | freq[idx]); /* Start PSD */ + + rtw_msleep_os(30); + + if (PHY_QueryBBReg(pAdapter, rFPGA0_PSDReport, bMaskDWord) >= threshold) + b_doNotch = TRUE; + + PHY_SetBBReg(pAdapter, rFPGA0_PSDFunction, bMaskDWord, freq[idx]); /* turn off PSD */ + + PHY_SetBBReg(pAdapter, rFPGA0_AnalogParameter4, bMaskDWord, 0xccc000c0); /* enable 3-wire */ + PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, BIT24, 1); /* Enable CCK block */ + ODM_Write_DIG(pDM_Odm, initial_gain); + } + + /* --- Notch Filter --- Asked by Rock */ + if (b_doNotch) { + CurrentChannel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask); + wlan_channel = CurrentChannel & 0x0f; /*Get center frequency */ + + switch (wlan_channel) { /*Set notch filter */ + case 5: + case 13: + // ODM_SetBBReg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0xB); + // ODM_SetBBReg(pDM_Odm, 0xC40, BIT9, 0x1); /*enable notch filter */ + ODM_SetBBReg(pDM_Odm, 0xD40, bMaskDWord, 0x06000000); + ODM_SetBBReg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, 0xD2C, BIT28, 0x1); /*enable CSI mask */ + break; + case 6: + // ODM_SetBBReg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0x4); + // ODM_SetBBReg(pDM_Odm, 0xC40, BIT9, 0x1); /*enable notch filter */ + ODM_SetBBReg(pDM_Odm, 0xD40, bMaskDWord, 0x00000600); + ODM_SetBBReg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, 0xD2C, BIT28, 0x1); /*enable CSI mask */ + break; + case 7: + // ODM_SetBBReg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0x3); + // ODM_SetBBReg(pDM_Odm, 0xC40, BIT9, 0x1); /*enable notch filter */ + ODM_SetBBReg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, 0xD4C, bMaskDWord, 0x06000000); + ODM_SetBBReg(pDM_Odm, 0xD2C, BIT28, 0x1); /*enable CSI mask */ + break; + case 8: + // ODM_SetBBReg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0xA); + // ODM_SetBBReg(pDM_Odm, 0xC40, BIT9, 0x1); /*enable notch filter */ + ODM_SetBBReg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000380); + ODM_SetBBReg(pDM_Odm, 0xD2C, BIT28, 0x1); /*enable CSI mask */ + break; + case 11: + // ODM_SetBBReg(pDM_Odm, 0xC40, BIT28|BIT27|BIT26|BIT25|BIT24, 0x19); + // ODM_SetBBReg(pDM_Odm, 0xC40, BIT9, 0x1); //enable notch filter + ODM_SetBBReg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, 0xD44, bMaskDWord, 0x04000000); + ODM_SetBBReg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, 0xD4C, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, 0xD2C, BIT28, 0x1); //enable CSI mask + break; + case 14: + // ODM_SetBBReg(pDM_Odm, 0xC40, BIT28 | BIT27 | BIT26 | BIT25 | BIT24, 0x5); + // ODM_SetBBReg(pDM_Odm, 0xC40, BIT9, 0x1); /*enable notch filter */ + ODM_SetBBReg(pDM_Odm, 0xD40, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, 0xD44, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, 0xD48, bMaskDWord, 0x00000000); + ODM_SetBBReg(pDM_Odm, 0xD4C, bMaskDWord, 0x00180000); + ODM_SetBBReg(pDM_Odm, 0xD2C, BIT28, 0x1); /*enable CSI mask */ + break; + default: + // ODM_SetBBReg(pDM_Odm, 0xC40, BIT9, 0x0); /*disable notch filter */ + ODM_SetBBReg(pDM_Odm, 0xD2C, BIT28, 0x0); /*disable CSI mask function */ + break; + } /*switch(wlan_channel) */ + return; + } + + // ODM_SetBBReg(pDM_Odm, 0xC40, BIT9, 0x0); /*disable notch filter */ + ODM_SetBBReg(pDM_Odm, 0xD2C, BIT28, 0x0); /*disable CSI mask */ + +} + +VOID +phy_SetRegBW_8188F( + IN PADAPTER Adapter, + CHANNEL_WIDTH CurrentBW +) +{ + u16 RegRfMod_BW, u2tmp = 0; + RegRfMod_BW = rtw_read16(Adapter, REG_TRXPTCL_CTL_8188F); + + switch (CurrentBW) { + case CHANNEL_WIDTH_20: + rtw_write16(Adapter, REG_TRXPTCL_CTL_8188F, (RegRfMod_BW & 0xFE7F)); /* BIT 7 = 0, BIT 8 = 0 */ + break; + + case CHANNEL_WIDTH_40: + u2tmp = RegRfMod_BW | BIT7; + rtw_write16(Adapter, REG_TRXPTCL_CTL_8188F, (u2tmp & 0xFEFF)); /* BIT 7 = 1, BIT 8 = 0 */ + break; + + case CHANNEL_WIDTH_80: + u2tmp = RegRfMod_BW | BIT8; + rtw_write16(Adapter, REG_TRXPTCL_CTL_8188F, (u2tmp & 0xFF7F)); /* BIT 7 = 0, BIT 8 = 1 */ + break; + + default: + DBG_871X("phy_PostSetBWMode8188F(): unknown Bandwidth: %#X\n", CurrentBW); + break; + } +} + +u8 +phy_GetSecondaryChnl_8188F( + IN PADAPTER Adapter +) +{ + u8 SCSettingOf40 = 0, SCSettingOf20 = 0; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + + RT_TRACE(_module_hal_init_c_, _drv_info_, ("SCMapping: VHT Case: pHalData->CurrentChannelBW %d, pHalData->nCur80MhzPrimeSC %d, pHalData->nCur40MhzPrimeSC %d\n", pHalData->CurrentChannelBW, + pHalData->nCur80MhzPrimeSC, pHalData->nCur40MhzPrimeSC)); + if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_80) { + if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) + SCSettingOf40 = VHT_DATA_SC_40_LOWER_OF_80MHZ; + else if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) + SCSettingOf40 = VHT_DATA_SC_40_UPPER_OF_80MHZ; + else + RT_TRACE(_module_hal_init_c_, _drv_err_, ("SCMapping: Not Correct Primary40MHz Setting\n")); + + if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)) + SCSettingOf20 = VHT_DATA_SC_20_LOWEST_OF_80MHZ; + else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)) + SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ; + else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)) + SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ; + else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)) + SCSettingOf20 = VHT_DATA_SC_20_UPPERST_OF_80MHZ; + else + RT_TRACE(_module_hal_init_c_, _drv_err_, ("SCMapping: Not Correct Primary40MHz Setting\n")); + } else if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) { + RT_TRACE(_module_hal_init_c_, _drv_info_, ("SCMapping: VHT Case: pHalData->CurrentChannelBW %d, pHalData->nCur40MhzPrimeSC %d\n", pHalData->CurrentChannelBW, pHalData->nCur40MhzPrimeSC)); + + if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) + SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ; + else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) + SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ; + else + RT_TRACE(_module_hal_init_c_, _drv_err_, ("SCMapping: Not Correct Primary40MHz Setting\n")); + } + + RT_TRACE(_module_hal_init_c_, _drv_info_, ("SCMapping: SC Value %x\n", ((SCSettingOf40 << 4) | SCSettingOf20))); + return ((SCSettingOf40 << 4) | SCSettingOf20); +} + +VOID +phy_PostSetBwMode8188F( + IN PADAPTER Adapter +) +{ + u1Byte SubChnlNum = 0; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + /* DBG_8192C("===>%s: CurrentChannelBW = %s Mhz\n", __func__, pHalData->CurrentChannelBW?"40":"20"); */ + + switch (pHalData->CurrentChannelBW) { + case CHANNEL_WIDTH_20: + /* + 0x800[0]=1'b0 + 0x900[0]=1'b0 + 0x800[10:8]=3'b111(80M) + 0x800[14:12]=3'b101(80M) + 0xCE4[31:30]=2'b00 + 0xCE4[29:28]=2'b01 + 0xc10[29:28]=1 + 0x954[19]=1'b0 + 0x954[23:20]=3 + */ + PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT0, 0x0); + PHY_SetBBReg(Adapter, rFPGA1_RFMOD, BIT0, 0x0); + PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT10 | BIT9 | BIT8, 0x7); /* RXADC CLK */ + PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT14 | BIT13 | BIT12, 0x5); /* TXDAC CLK */ + PHY_SetBBReg(Adapter, rOFDM0_TxPseudoNoiseWgt, BIT31 | BIT30, 0x0); /* small BW */ + PHY_SetBBReg(Adapter, rOFDM0_TxPseudoNoiseWgt, BIT29 | BIT28, 0x1); /* adc buffer clk(TBD) */ + PHY_SetBBReg(Adapter, rOFDM0_XARxAFE, BIT29 | BIT28, 0x1); /* adc buffer clk(TBD) */ + PHY_SetBBReg(Adapter, BBrx_DFIR, BIT19, 0x0); /* OFDM RX DFIR */ + PHY_SetBBReg(Adapter, BBrx_DFIR, BIT23 | BIT22 | BIT21 | BIT20, 0x3); /* OFDM RX DFIR */ + break; + + case CHANNEL_WIDTH_40: + /* + 0x800[0]=1'b1 + 0x900[0]=1'b1 + 0x800[10:8]=3'b111(80M) + 0x800[14:12]=3'b101(80M) + 0xCE4[31:30]=2'b00 + 0xCE4[29:28]=2'b01 + 0xc10[29:28]: 1 + 0x954[19]=1'b0 + 0x954[23:20]=0x6(For ACPR) + + 0xa00[4]=1/0 + + 0x483[3:0]=1/2 + 0x440[22:21]=2'b00 + + 0xc84[31:28]=0x2 (SDIO) + 0xc84[31:28]=0x7 (USB) + */ + PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT0, 0x1); + PHY_SetBBReg(Adapter, rFPGA1_RFMOD, BIT0, 0x1); + PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT10 | BIT9 | BIT8, 0x7); /* RXADC CLK */ + PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT14 | BIT13 | BIT12, 0x5); /* TXDAC CLK */ + PHY_SetBBReg(Adapter, rOFDM0_TxPseudoNoiseWgt, BIT31 | BIT30, 0x0); /* small BW */ + PHY_SetBBReg(Adapter, rOFDM0_TxPseudoNoiseWgt, BIT29 | BIT28, 0x1); /* adc buffer clk(TBD) */ + PHY_SetBBReg(Adapter, rOFDM0_XARxAFE, BIT29 | BIT28, 0x1); /* adc buffer clk(TBD) */ + PHY_SetBBReg(Adapter, BBrx_DFIR, BIT19, 0x0); /* OFDM RX DFIR */ + PHY_SetBBReg(Adapter, BBrx_DFIR, BIT23 | BIT22 | BIT21 | BIT20, 0x6); /* OFDM RX DFIR */ + + PHY_SetBBReg(Adapter, rCCK0_System, BIT4, (pHalData->nCur40MhzPrimeSC >> 1)); /* primary channel (CCK RXSC) */ + + SubChnlNum = phy_GetSecondaryChnl_8188F(Adapter); + PHY_SetMacReg(Adapter, REG_DATA_SC_8188F, BIT3 | BIT2 | BIT1 | BIT0, SubChnlNum); /* txsc_20 */ + PHY_SetMacReg(Adapter, REG_RRSR_8188F, BIT22 | BIT21, 0x0); /* RRSR_RSC */ + + if (0) + DBG_871X("%s: REG_DATA_SC_8188F(%d) nCur40MhzPrimeSC(%d)\n", __func__, SubChnlNum, pHalData->nCur40MhzPrimeSC); + break; + + default: + RT_TRACE(COMP_DBG, DBG_LOUD, ("phy_SetBWMode8188F(): unknown Bandwidth: %#X\n"\ + , pHalData->CurrentChannelBW)); + break; + } + + /*3<3>Set RF related register */ + PHY_RF6052SetBandwidth8188F(Adapter, pHalData->CurrentChannelBW); +} + +VOID +phy_SwChnl8188F( + IN PADAPTER pAdapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + u8 channelToSW = pHalData->CurrentChannel; +#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) + PDM_ODM_T pDM_Odm = &pHalData->DM_OutSrc; +#else /* (DM_ODM_SUPPORT_TYPE == ODM_CE) */ + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; +#endif + + if (pHalData->rf_chip == RF_PSEUDO_11N) { + /*RT_TRACE(COMP_MLME,DBG_LOUD,("phy_SwChnl8188F: return for PSEUDO\n")); */ + return; + } + + pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff00) | channelToSW); + PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0]); + /* PHY_SetRFReg(pAdapter, ODM_RF_PATH_B, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0] ); */ + + /* DBG_8192C("===>phy_SwChnl8188F: Channel = %d\n", channelToSW); */ + + phy_SpurCalibration_8188F(pAdapter, channelToSW, 0x16); +} + +VOID +phy_SwChnlAndSetBwMode8188F( + IN PADAPTER Adapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + /*RT_TRACE(COMP_SCAN, DBG_LOUD, ("phy_SwChnlAndSetBwMode8188F(): bSwChnl %d, bSetChnlBW %d\n", pHalData->bSwChnl, pHalData->bSetChnlBW)); */ + if (Adapter->bNotifyChannelChange) { + DBG_871X("[%s] bSwChnl=%d, ch=%d, bSetChnlBW=%d, bw=%d\n", + __func__, + pHalData->bSwChnl, + pHalData->CurrentChannel, + pHalData->bSetChnlBW, + pHalData->CurrentChannelBW); + } + + if (RTW_CANNOT_RUN(Adapter)) + return; + + if (pHalData->bSwChnl) { + phy_SwChnl8188F(Adapter); + pHalData->bSwChnl = _FALSE; + } + + if (pHalData->bSetChnlBW) { + phy_PostSetBwMode8188F(Adapter); + pHalData->bSetChnlBW = _FALSE; + } + + PHY_SetTxPowerLevel8188F(Adapter, pHalData->CurrentChannel); +} + +VOID +PHY_HandleSwChnlAndSetBW8188F( + IN PADAPTER Adapter, + IN BOOLEAN bSwitchChannel, + IN BOOLEAN bSetBandWidth, + IN u8 ChannelNum, + IN CHANNEL_WIDTH ChnlWidth, + IN EXTCHNL_OFFSET ExtChnlOffsetOf40MHz, + IN EXTCHNL_OFFSET ExtChnlOffsetOf80MHz, + IN u8 CenterFrequencyIndex1 +) +{ + /*static BOOLEAN bInitialzed = _FALSE; */ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + u8 tmpChannel = pHalData->CurrentChannel; + CHANNEL_WIDTH tmpBW = pHalData->CurrentChannelBW; + u8 tmpnCur40MhzPrimeSC = pHalData->nCur40MhzPrimeSC; + u8 tmpnCur80MhzPrimeSC = pHalData->nCur80MhzPrimeSC; + u8 tmpCenterFrequencyIndex1 = pHalData->CurrentCenterFrequencyIndex1; + struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; + + /* DBG_871X("=> PHY_HandleSwChnlAndSetBW8188F: bSwitchChannel %d, bSetBandWidth %d\n", bSwitchChannel, bSetBandWidth); */ + /* DBG_871X("=> %s: ChnlWidth %d\n", __func__, ChnlWidth); */ + + /*check is swchnl or setbw */ + if (!bSwitchChannel && !bSetBandWidth) { + DBG_871X("PHY_HandleSwChnlAndSetBW8188F: not switch channel and not set bandwidth\n"); + return; + } + + /*skip change for channel or bandwidth is the same */ + if (bSwitchChannel) { + /*if(pHalData->CurrentChannel != ChannelNum) */ + { + if (HAL_IsLegalChannel(Adapter, ChannelNum)) + pHalData->bSwChnl = _TRUE; + } + } + + if (bSetBandWidth) { +#if 0 + if (bInitialzed == _FALSE) { + bInitialzed = _TRUE; + pHalData->bSetChnlBW = _TRUE; + } else if ((pHalData->CurrentChannelBW != ChnlWidth) || (pHalData->nCur40MhzPrimeSC != ExtChnlOffsetOf40MHz) || (pHalData->CurrentCenterFrequencyIndex1 != CenterFrequencyIndex1)) + pHalData->bSetChnlBW = _TRUE; +#else + pHalData->bSetChnlBW = _TRUE; +#endif + } + + if (!pHalData->bSetChnlBW && !pHalData->bSwChnl) { + /* DBG_871X("<= PHY_HandleSwChnlAndSetBW8188F: bSwChnl %d, bSetChnlBW %d\n", pHalData->bSwChnl, pHalData->bSetChnlBW); */ + return; + } + + + if (pHalData->bSwChnl) { + pHalData->CurrentChannel = ChannelNum; + pHalData->CurrentCenterFrequencyIndex1 = ChannelNum; + } + + + if (pHalData->bSetChnlBW) { + pHalData->CurrentChannelBW = ChnlWidth; +#if 0 + if (ExtChnlOffsetOf40MHz == EXTCHNL_OFFSET_LOWER) + pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; + else if (ExtChnlOffsetOf40MHz == EXTCHNL_OFFSET_UPPER) + pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; + else + pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + + if (ExtChnlOffsetOf80MHz == EXTCHNL_OFFSET_LOWER) + pHalData->nCur80MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; + else if (ExtChnlOffsetOf80MHz == EXTCHNL_OFFSET_UPPER) + pHalData->nCur80MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; + else + pHalData->nCur80MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; +#else + pHalData->nCur40MhzPrimeSC = ExtChnlOffsetOf40MHz; + pHalData->nCur80MhzPrimeSC = ExtChnlOffsetOf80MHz; +#endif + + pHalData->CurrentCenterFrequencyIndex1 = CenterFrequencyIndex1; + } + + /*Switch workitem or set timer to do switch channel or setbandwidth operation */ + if (!RTW_CANNOT_RUN(Adapter)) + phy_SwChnlAndSetBwMode8188F(Adapter); + else { + if (pHalData->bSwChnl) { + pHalData->CurrentChannel = tmpChannel; + pHalData->CurrentCenterFrequencyIndex1 = tmpChannel; + } + if (pHalData->bSetChnlBW) { + pHalData->CurrentChannelBW = tmpBW; + pHalData->nCur40MhzPrimeSC = tmpnCur40MhzPrimeSC; + pHalData->nCur80MhzPrimeSC = tmpnCur80MhzPrimeSC; + pHalData->CurrentCenterFrequencyIndex1 = tmpCenterFrequencyIndex1; + } + } + + /*DBG_871X("Channel %d ChannelBW %d ",pHalData->CurrentChannel, pHalData->CurrentChannelBW); */ + /*DBG_871X("40MhzPrimeSC %d 80MhzPrimeSC %d ",pHalData->nCur40MhzPrimeSC, pHalData->nCur80MhzPrimeSC); */ + /*DBG_871X("CenterFrequencyIndex1 %d\n",pHalData->CurrentCenterFrequencyIndex1); */ + + /*DBG_871X("<= PHY_HandleSwChnlAndSetBW8188F: bSwChnl %d, bSetChnlBW %d\n",pHalData->bSwChnl,pHalData->bSetChnlBW); */ + +} + +VOID +PHY_SetBWMode8188F( + IN PADAPTER Adapter, + /* 20M or 40M */ + IN CHANNEL_WIDTH Bandwidth, + /* Upper, Lower, or Don't care */ + IN u8 Offset +) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + + PHY_HandleSwChnlAndSetBW8188F(Adapter, _FALSE, _TRUE, pHalData->CurrentChannel, Bandwidth, Offset, Offset, pHalData->CurrentChannel); +} + +VOID +PHY_SwChnl8188F( + /* Call after initialization */ + IN PADAPTER Adapter, + IN u8 channel +) +{ + PHY_HandleSwChnlAndSetBW8188F(Adapter, _TRUE, _FALSE, channel, 0, 0, 0, channel); +} + +VOID +PHY_SetSwChnlBWMode8188F( + IN PADAPTER Adapter, + IN u8 channel, + IN CHANNEL_WIDTH Bandwidth, + IN u8 Offset40, + IN u8 Offset80 +) +{ + /*DBG_871X("%s()===>\n",__func__); */ + + PHY_HandleSwChnlAndSetBW8188F(Adapter, _TRUE, _TRUE, channel, Bandwidth, Offset40, Offset80, channel); + + /*DBG_871X("<==%s()\n",__func__); */ +} + +static VOID +_PHY_DumpRFReg_8188F(IN PADAPTER pAdapter) +{ + u32 rfRegValue, rfRegOffset; + + RT_TRACE(_module_hal_init_c_, _drv_info_, ("_PHY_DumpRFReg_8188F()====>\n")); + + for (rfRegOffset = 0x00; rfRegOffset <= 0x30; rfRegOffset++) { + rfRegValue = PHY_QueryRFReg_8188F(pAdapter, RF_PATH_A, rfRegOffset, bMaskDWord); + RT_TRACE(_module_hal_init_c_, _drv_info_, (" 0x%02x = 0x%08x\n", rfRegOffset, rfRegValue)); + } + RT_TRACE(_module_hal_init_c_, _drv_info_, ("<===== _PHY_DumpRFReg_8188F()\n")); +} + + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_rf6052.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_rf6052.c new file mode 100644 index 000000000..60c3d440d --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_rf6052.c @@ -0,0 +1,292 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +/****************************************************************************** + * + * + * Module: rtl8192c_rf6052.c ( Source C File) + * + * Note: Provide RF 6052 series relative API. + * + * Function: + * + * Export: + * + * Abbrev: + * + * History: + * Data Who Remark + * + * 09/25/2008 MHC Create initial version. + * 11/05/2008 MHC Add API for tw power setting. + * + * +******************************************************************************/ + +#include + +/*---------------------------Define Local Constant---------------------------*/ +/*---------------------------Define Local Constant---------------------------*/ + + +/*------------------------Define global variable-----------------------------*/ +/*------------------------Define global variable-----------------------------*/ + + +/*------------------------Define local variable------------------------------*/ +/* 2008/11/20 MH For Debug only, RF */ +/*static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG] = {0}; */ +static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG]; +/*------------------------Define local variable------------------------------*/ + +/*----------------------------------------------------------------------------- + * Function: PHY_RF6052SetBandwidth() + * + * Overview: This function is called by SetBWModeCallback8190Pci() only + * + * Input: PADAPTER Adapter + * WIRELESS_BANDWIDTH_E Bandwidth 20M or 40M + * + * Output: NONE + * + * Return: NONE + * + * Note: For RF type 0222D + *---------------------------------------------------------------------------*/ +VOID +PHY_RF6052SetBandwidth8188F( + IN PADAPTER Adapter, + IN CHANNEL_WIDTH Bandwidth) /*20M or 40M */ +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + switch (Bandwidth) { + case CHANNEL_WIDTH_20: + /* + RF_A_reg 0x18[11:10]=2'b11 + RF_A_reg 0x87=0x00065 + RF_A_reg 0x1c=0x00000 + RF_A_reg 0xDF=0x00140 + RF_A_reg 0x1b=0x00c6c (for SDIO) + RF_A_reg 0x1b=0x01c6c (for USB) + */ + pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10 | BIT11); + PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); /* RF TRX_BW */ + + PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x87, bRFRegOffsetMask, 0x00065); /* FILTER BW&RC Corner (ACPR) */ + PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x1C, bRFRegOffsetMask, 0x00000); /* FILTER BW&RC Corner (ACPR) */ + + PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0xDF, bRFRegOffsetMask, 0x00140); /* RC Corner */ +#ifdef CONFIG_SDIO_HCI + PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x1B, bRFRegOffsetMask, 0x00C6C); /* RC Corner */ +#endif /* CONFIG_SDIO_HCI */ +#ifdef CONFIG_USB_HCI + PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x1B, bRFRegOffsetMask, 0x01C6C); /* RC Corner */ +#endif + break; + + case CHANNEL_WIDTH_40: + /* + RF_A_reg 0x18[11:10]=2'b01 + RF_A_reg 0x87=0x00025 + RF_A_reg 0x1c=0x00800 (for SDIO) + RF_A_reg 0x1c=0x01000 (for USB) + RF_A_reg 0xDF=0x00140 + RF_A_reg 0x1b=0x00c6c (for SDIO) + RF_A_reg 0x1b=0x01c6c (for USB) + */ + pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | BIT10); + PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x18, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); /* RF TRX_BW */ + + PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x87, bRFRegOffsetMask, 0x00025); /* FILTER BW&RC Corner (ACPR) */ +#ifdef CONFIG_SDIO_HCI + PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x1C, bRFRegOffsetMask, 0x00800); /* FILTER BW&RC Corner (ACPR) */ + PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0xDF, bRFRegOffsetMask, 0x00140); /* RC Corner */ + PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x1B, bRFRegOffsetMask, 0x00C6C); /* RC Corner */ +#endif /* CONFIG_SDIO_HCI */ +#ifdef CONFIG_USB_HCI + PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x1C, bRFRegOffsetMask, 0x01000); /* FILTER BW&RC Corner (ACPR) */ + PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0xDF, bRFRegOffsetMask, 0x00140); /* RC Corner */ + PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x1B, bRFRegOffsetMask, 0x01C6C); /* RC Corner */ +#endif + break; + + default: + /*RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth )); */ + break; + } + +} + +static VOID +phy_RF6052_Config_HardCode( + IN PADAPTER Adapter +) +{ + + /* Set Default Bandwidth to 20M */ + /*Adapter->HalFunc .SetBWModeHandler(Adapter, CHANNEL_WIDTH_20); */ + + /* TODO: Set Default Channel to channel one for RTL8225 */ + +} + +static int +phy_RF6052_Config_ParaFile( + IN PADAPTER Adapter +) +{ + u32 u4RegValue = 0; + u8 eRFPath; + BB_REGISTER_DEFINITION_T *pPhyReg; + + int rtStatus = _SUCCESS; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + /*3//----------------------------------------------------------------- */ + /*3// <2> Initialize RF */ + /*3//----------------------------------------------------------------- */ + /*for(eRFPath = RF_PATH_A; eRFPath NumTotalRFPath; eRFPath++) */ + for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) { + + pPhyReg = &pHalData->PHYRegDef[eRFPath]; + + /*----Store original RFENV control type----*/ + switch (eRFPath) { + case RF_PATH_A: + case RF_PATH_C: + u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV); + break; + case RF_PATH_B : + case RF_PATH_D: + u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV << 16); + break; + } + + /*----Set RF_ENV enable----*/ + PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV << 16, 0x1); + rtw_udelay_os(1);/*PlatformStallExecution(1); */ + + /*----Set RF_ENV output high----*/ + PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); + rtw_udelay_os(1);/*PlatformStallExecution(1); */ + + /* Set bit number of Address and Data for RF register */ + PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); /* Set 1 to 4 bits for 8255 */ + rtw_udelay_os(1);/*PlatformStallExecution(1); */ + + PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); /* Set 0 to 12 bits for 8255 */ + rtw_udelay_os(1);/*PlatformStallExecution(1); */ + + /*----Initialize RF fom connfiguration file----*/ + switch (eRFPath) { + case RF_PATH_A: +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + if (PHY_ConfigRFWithParaFile(Adapter, PHY_FILE_RADIO_A, eRFPath) == _FAIL) +#endif + { +#ifdef CONFIG_EMBEDDED_FWIMG + if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, CONFIG_RF_RADIO, (ODM_RF_RADIO_PATH_E)eRFPath)) + rtStatus = _FAIL; +#endif + } + break; + case RF_PATH_B: +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + if (PHY_ConfigRFWithParaFile(Adapter, PHY_FILE_RADIO_B, eRFPath) == _FAIL) +#endif + { +#ifdef CONFIG_EMBEDDED_FWIMG + if (HAL_STATUS_FAILURE == ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, CONFIG_RF_RADIO, (ODM_RF_RADIO_PATH_E)eRFPath)) + rtStatus = _FAIL; +#endif + } + break; + case RF_PATH_C: + break; + case RF_PATH_D: + break; + } + + /*----Restore RFENV control type----*/; + switch (eRFPath) { + case RF_PATH_A: + case RF_PATH_C: + PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); + break; + case RF_PATH_B : + case RF_PATH_D: + PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV << 16, u4RegValue); + break; + } + + if (rtStatus != _SUCCESS) { + /*RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath)); */ + goto phy_RF6052_Config_ParaFile_Fail; + } + + } + + /*3 ----------------------------------------------------------------- */ + /*3 Configuration of Tx Power Tracking */ + /*3 ----------------------------------------------------------------- */ + +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + if (PHY_ConfigRFWithTxPwrTrackParaFile(Adapter, PHY_FILE_TXPWR_TRACK) == _FAIL) +#endif + { +#ifdef CONFIG_EMBEDDED_FWIMG + ODM_ConfigRFWithTxPwrTrackHeaderFile(&pHalData->odmpriv); +#endif + } + + /*RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n")); */ + return rtStatus; + +phy_RF6052_Config_ParaFile_Fail: + return rtStatus; +} + + +int +PHY_RF6052_Config8188F( + IN PADAPTER Adapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + int rtStatus = _SUCCESS; + + /* */ + /* Initialize general global value */ + /* */ + /* TODO: Extend RF_PATH_C and RF_PATH_D in the future */ + if (pHalData->rf_type == RF_1T1R) + pHalData->NumTotalRFPath = 1; + else + pHalData->NumTotalRFPath = 2; + + /* */ + /* Config BB and RF */ + /* */ + rtStatus = phy_RF6052_Config_ParaFile(Adapter); + return rtStatus; + +} + +/* End of HalRf6052.c */ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_rxdesc.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_rxdesc.c new file mode 100644 index 000000000..de910607e --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_rxdesc.c @@ -0,0 +1,69 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTL8188F_REDESC_C_ + +#include + +void rtl8188f_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc) +{ + struct rx_pkt_attrib *pattrib; + + + pattrib = &precvframe->u.hdr.attrib; + _rtw_memset(pattrib, 0, sizeof(struct rx_pkt_attrib)); + + pattrib->pkt_len = (u16)GET_RX_STATUS_DESC_PKT_LEN_8188F(pdesc); + pattrib->pkt_rpt_type = GET_RX_STATUS_DESC_RPT_SEL_8188F(pdesc) ? C2H_PACKET : NORMAL_RX; + + if (pattrib->pkt_rpt_type == NORMAL_RX) { + /* Offset 0 */ + pattrib->crc_err = (u8)GET_RX_STATUS_DESC_CRC32_8188F(pdesc); + pattrib->icv_err = (u8)GET_RX_STATUS_DESC_ICV_8188F(pdesc); + pattrib->drvinfo_sz = (u8)GET_RX_STATUS_DESC_DRVINFO_SIZE_8188F(pdesc) << 3; + pattrib->encrypt = (u8)GET_RX_STATUS_DESC_SECURITY_8188F(pdesc); + pattrib->qos = (u8)GET_RX_STATUS_DESC_QOS_8188F(pdesc); + pattrib->shift_sz = (u8)GET_RX_STATUS_DESC_SHIFT_8188F(pdesc); + pattrib->physt = (u8)GET_RX_STATUS_DESC_PHY_STATUS_8188F(pdesc); + pattrib->bdecrypted = (u8)GET_RX_STATUS_DESC_SWDEC_8188F(pdesc) ? 0 : 1; + + /* Offset 4 */ + pattrib->priority = (u8)GET_RX_STATUS_DESC_TID_8188F(pdesc); + pattrib->amsdu = (u8)GET_RX_STATUS_DESC_AMSDU_8188F(pdesc); + pattrib->mdata = (u8)GET_RX_STATUS_DESC_MORE_DATA_8188F(pdesc); + pattrib->mfrag = (u8)GET_RX_STATUS_DESC_MORE_FRAG_8188F(pdesc); + + /* Offset 8 */ + pattrib->seq_num = (u16)GET_RX_STATUS_DESC_SEQ_8188F(pdesc); + pattrib->frag_num = (u8)GET_RX_STATUS_DESC_FRAG_8188F(pdesc); + + /* Offset 12 */ + pattrib->data_rate = (u8)GET_RX_STATUS_DESC_RX_RATE_8188F(pdesc); + + /* Offset 16 */ + pattrib->sgi = (u8)GET_RX_STATUS_DESC_SPLCP_8188F(pdesc); + pattrib->ldpc = (u8)GET_RX_STATUS_DESC_LDPC_8188F(pdesc); + pattrib->stbc = (u8)GET_RX_STATUS_DESC_STBC_8188F(pdesc); + pattrib->bw = (u8)GET_RX_STATUS_DESC_BW_8188F(pdesc); + + /* Offset 20 */ + /* pattrib->tsfl=(u8)GET_RX_STATUS_DESC_TSFL_8188F(pdesc); */ + } +} + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_sreset.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_sreset.c new file mode 100644 index 000000000..e7f7e3bf7 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/rtl8188f_sreset.c @@ -0,0 +1,109 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTL8188F_SRESET_C_ + +#include + + +#ifdef DBG_CONFIG_ERROR_DETECT +void rtl8188f_sreset_xmit_status_check(_adapter *padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct sreset_priv *psrtpriv = &pHalData->srestpriv; + + unsigned long current_time; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + unsigned int diff_time; + u32 txdma_status; + + txdma_status = rtw_read32(padapter, REG_TXDMA_STATUS); + if (txdma_status != 0x00 && txdma_status != 0xeaeaeaea) { + DBG_871X("%s REG_TXDMA_STATUS:0x%08x\n", __func__, txdma_status); + rtw_hal_sreset_reset(padapter); + } + +#ifdef CONFIG_USB_HCI + /*total xmit irp = 4 */ + /*DBG_8192C("==>%s free_xmitbuf_cnt(%d),txirp_cnt(%d)\n",__func__,pxmitpriv->free_xmitbuf_cnt,pxmitpriv->txirp_cnt); */ + /*if(pxmitpriv->txirp_cnt == NR_XMITBUFF+1) */ + current_time = rtw_get_current_time(); + + if (0 == pxmitpriv->free_xmitbuf_cnt || 0 == pxmitpriv->free_xmit_extbuf_cnt) { + + diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_time); + + if (diff_time > 2000) { + if (psrtpriv->last_tx_complete_time == 0) + psrtpriv->last_tx_complete_time = current_time; + else { + diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_complete_time); + if (diff_time > 4000) { + u32 ability = 0; + + /*padapter->Wifi_Error_Status = WIFI_TX_HANG; */ + ability = rtw_phydm_ability_get(padapter); + DBG_871X("%s tx hang %s\n", __func__, + (ability & ODM_BB_ADAPTIVITY) ? "ODM_BB_ADAPTIVITY" : ""); + + if (!(ability & ODM_BB_ADAPTIVITY)) + rtw_hal_sreset_reset(padapter); + } + } + } + } +#endif /* #ifdef CONFIG_USB_HCI */ + + if (psrtpriv->dbg_trigger_point == SRESET_TGP_XMIT_STATUS) { + psrtpriv->dbg_trigger_point = SRESET_TGP_NULL; + rtw_hal_sreset_reset(padapter); + return; + } +} + +void rtl8188f_sreset_linked_status_check(_adapter *padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct sreset_priv *psrtpriv = &pHalData->srestpriv; +#if 0 + u32 regc50, regc58, reg824, reg800; + + regc50 = rtw_read32(padapter, 0xc50); + regc58 = rtw_read32(padapter, 0xc58); + reg824 = rtw_read32(padapter, 0x824); + reg800 = rtw_read32(padapter, 0x800); + if (((regc50 & 0xFFFFFF00) != 0x69543400) || + ((regc58 & 0xFFFFFF00) != 0x69543400) || + (((reg824 & 0xFFFFFF00) != 0x00390000) && (((reg824 & 0xFFFFFF00) != 0x80390000))) || + (((reg800 & 0xFFFFFF00) != 0x03040000) && ((reg800 & 0xFFFFFF00) != 0x83040000))) { + DBG_8192C("%s regc50:0x%08x, regc58:0x%08x, reg824:0x%08x, reg800:0x%08x,\n", __func__, + regc50, regc58, reg824, reg800); + rtw_hal_sreset_reset(padapter); + } +#endif + + if (psrtpriv->dbg_trigger_point == SRESET_TGP_LINK_STATUS) { + psrtpriv->dbg_trigger_point = SRESET_TGP_NULL; + rtw_hal_sreset_reset(padapter); + return; + } +} + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/usb/rtl8188fu_led.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/usb/rtl8188fu_led.c new file mode 100644 index 000000000..fc41ed581 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/usb/rtl8188fu_led.c @@ -0,0 +1,130 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#include "rtl8188f_hal.h" + +/* + * ================================================================================ + * LED object. + * ================================================================================ + */ + + +/* + * ================================================================================ + * Prototype of protected function. + * ================================================================================ + */ + +/* + * ================================================================================ + * LED_819xUsb routines. + * ================================================================================ + */ + +/* + * Description: + * Turn on LED according to LedPin specified. + */ +void +SwLedOn_8188FU( + PADAPTER padapter, + PLED_USB pLed +) +{ + u8 LedCfg; + + if (RTW_CANNOT_RUN(padapter)) + return; + + pLed->bLedOn = _TRUE; + +} + + +/* + * Description: + * Turn off LED according to LedPin specified. + */ +void +SwLedOff_8188FU( + PADAPTER padapter, + PLED_USB pLed +) +{ + u8 LedCfg; + + if (RTW_CANNOT_RUN(padapter)) + goto exit; + +exit: + pLed->bLedOn = _FALSE; + +} + +/* + * ================================================================================ + * Interface to manipulate LED objects. + * ================================================================================ + */ + +/* + * ================================================================================ + * Default LED behavior. + * ================================================================================ + */ + +/* + * Description: + * Initialize all LED_871x objects. + */ +void +rtl8188fu_InitSwLeds( + PADAPTER padapter +) +{ + struct led_priv *pledpriv = &(padapter->ledpriv); + + pledpriv->LedControlHandler = LedControlUSB; + + pledpriv->SwLedOn = SwLedOn_8188FU; + pledpriv->SwLedOff = SwLedOff_8188FU; + + InitLed(padapter, &(pledpriv->SwLed0), LED_PIN_LED0); + + InitLed(padapter, &(pledpriv->SwLed1), LED_PIN_LED1); +} + + +/* + * Description: + * DeInitialize all LED_819xUsb objects. + */ + +void +rtl8188fu_DeInitSwLeds( + PADAPTER padapter +) +{ + struct led_priv *ledpriv = &(padapter->ledpriv); + + DeInitLed(&(ledpriv->SwLed0)); + DeInitLed(&(ledpriv->SwLed1)); +} + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/usb/rtl8188fu_recv.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/usb/rtl8188fu_recv.c new file mode 100644 index 000000000..dc11e703a --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/usb/rtl8188fu_recv.c @@ -0,0 +1,33 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RTL8188FU_RECV_C_ + +#include + +int rtl8188fu_init_recv_priv(_adapter *padapter) +{ + return usb_init_recv_priv(padapter, USB_INTR_CONTENT_LENGTH); +} + +void rtl8188fu_free_recv_priv(_adapter *padapter) +{ + usb_free_recv_priv(padapter, USB_INTR_CONTENT_LENGTH); +} + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/usb/rtl8188fu_xmit.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/usb/rtl8188fu_xmit.c new file mode 100644 index 000000000..823c5182c --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/usb/rtl8188fu_xmit.c @@ -0,0 +1,932 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#define _RTL8188FU_XMIT_C_ + +#include + + +s32 rtl8188fu_init_xmit_priv(_adapter *padapter) +{ + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + +#ifdef PLATFORM_LINUX + tasklet_init(&pxmitpriv->xmit_tasklet, + (void(*)(unsigned long))rtl8188fu_xmit_tasklet, + (unsigned long)padapter); +#endif + return _SUCCESS; +} + +void rtl8188fu_free_xmit_priv(_adapter *padapter) +{ +} + +void _dbg_dump_tx_info(_adapter *padapter, int frame_tag, struct tx_desc *ptxdesc) +{ + u8 bDumpTxPkt; + u8 bDumpTxDesc = _FALSE; + rtw_hal_get_def_var(padapter, HAL_DEF_DBG_DUMP_TXPKT, &(bDumpTxPkt)); + + if (bDumpTxPkt == 1) { /*dump txdesc for data frame */ + DBG_871X("dump tx_desc for data frame\n"); + if ((frame_tag & 0x0f) == DATA_FRAMETAG) + bDumpTxDesc = _TRUE; + } else if (bDumpTxPkt == 2) { /*dump txdesc for mgnt frame */ + DBG_871X("dump tx_desc for mgnt frame\n"); + if ((frame_tag & 0x0f) == MGNT_FRAMETAG) + bDumpTxDesc = _TRUE; + } else if (bDumpTxPkt == 3) { /*dump early info */ + } + + if (bDumpTxDesc) { + DBG_8192C("=====================================\n"); + DBG_8192C("txdw0(0x%08x)\n", ptxdesc->txdw0); + DBG_8192C("txdw1(0x%08x)\n", ptxdesc->txdw1); + DBG_8192C("txdw2(0x%08x)\n", ptxdesc->txdw2); + DBG_8192C("txdw3(0x%08x)\n", ptxdesc->txdw3); + DBG_8192C("txdw4(0x%08x)\n", ptxdesc->txdw4); + DBG_8192C("txdw5(0x%08x)\n", ptxdesc->txdw5); + DBG_8192C("txdw6(0x%08x)\n", ptxdesc->txdw6); + DBG_8192C("txdw7(0x%08x)\n", ptxdesc->txdw7); + DBG_8192C("txdw8(0x%08x)\n", ptxdesc->txdw8); + DBG_8192C("txdw9(0x%08x)\n", ptxdesc->txdw9); + DBG_8192C("=====================================\n"); + } + +} + +int urb_zero_packet_chk(_adapter *padapter, int sz) +{ + u8 blnSetTxDescOffset; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + blnSetTxDescOffset = (((sz + TXDESC_SIZE) % pHalData->UsbBulkOutSize) == 0) ? 1 : 0; + + return blnSetTxDescOffset; +} +void fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc) +{ + if ((pattrib->encrypt > 0) && !pattrib->bswenc) { + switch (pattrib->encrypt) { + /*SEC_TYPE */ + case _WEP40_: + case _WEP104_: + ptxdesc->txdw1 |= cpu_to_le32((0x01 << 22) & 0x00c00000); + break; + case _TKIP_: + case _TKIP_WTMIC_: + /*ptxdesc->txdw1 |= cpu_to_le32((0x02<<22)&0x00c00000); */ + ptxdesc->txdw1 |= cpu_to_le32((0x01 << 22) & 0x00c00000); + break; + case _AES_: + ptxdesc->txdw1 |= cpu_to_le32((0x03 << 22) & 0x00c00000); + break; + case _NO_PRIVACY_: + default: + break; + + } + + } + +} + +void fill_txdesc_vcs(struct pkt_attrib *pattrib, u32 *pdw) +{ + /*DBG_8192C("cvs_mode=%d\n", pattrib->vcs_mode); */ + + switch (pattrib->vcs_mode) { + case RTS_CTS: + *pdw |= cpu_to_le32(BIT(12)); + break; + case CTS_TO_SELF: + *pdw |= cpu_to_le32(BIT(11)); + break; + case NONE_VCS: + default: + break; + } + + if (pattrib->vcs_mode) { + *pdw |= cpu_to_le32(BIT(13)); + + /* Set RTS BW */ + if (pattrib->ht_en) { + *pdw |= (pattrib->bwmode & CHANNEL_WIDTH_40) ? cpu_to_le32(BIT(27)) : 0; + + if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER) + *pdw |= cpu_to_le32((0x01 << 28) & 0x30000000); + else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER) + *pdw |= cpu_to_le32((0x02 << 28) & 0x30000000); + else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) + *pdw |= 0; + else + *pdw |= cpu_to_le32((0x03 << 28) & 0x30000000); + } + } +} + +void fill_txdesc_phy(struct pkt_attrib *pattrib, u32 *pdw) +{ + /*DBG_8192C("bwmode=%d, ch_off=%d\n", pattrib->bwmode, pattrib->ch_offset); */ + + if (pattrib->ht_en) { + *pdw |= (pattrib->bwmode & CHANNEL_WIDTH_40) ? cpu_to_le32(BIT(25)) : 0; + + if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER) + *pdw |= cpu_to_le32((0x01 << 20) & 0x003f0000); + else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER) + *pdw |= cpu_to_le32((0x02 << 20) & 0x003f0000); + else if (pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) + *pdw |= 0; + else + *pdw |= cpu_to_le32((0x03 << 20) & 0x003f0000); + } +} + +static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz, u8 bagg_pkt) +{ + int pull = 0; + + + _adapter *padapter = pxmitframe->padapter; + struct tx_desc *ptxdesc = (struct tx_desc *)pmem; +#if 0 + uint qsel; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct dm_priv *pdmpriv = &pHalData->dmpriv; + + struct ht_priv *phtpriv = &pmlmepriv->htpriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + sint bmcst = IS_MCAST(pattrib->ra); +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &padapter->wdinfo; +#endif /*CONFIG_P2P */ +#endif +#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX + if ((PACKET_OFFSET_SZ != 0) + && (_FALSE == bagg_pkt) + && (urb_zero_packet_chk(padapter, sz) == 0)) { + ptxdesc = (struct tx_desc *)(pmem + PACKET_OFFSET_SZ); + pull = 1; + pxmitframe->pkt_offset --; + } +#endif /* CONFIG_USE_USB_BUFFER_ALLOC_TX */ + + _rtw_memset(ptxdesc, 0, sizeof(struct tx_desc)); + + rtl8188f_update_txdesc(pxmitframe, (u8 *)ptxdesc); + _dbg_dump_tx_info(padapter, pxmitframe->frame_tag, ptxdesc); + return pull; + +} + +#ifdef CONFIG_XMIT_THREAD_MODE +/* + * Description + * Transmit xmitbuf to hardware tx fifo + * + * Return + * _SUCCESS ok + * _FAIL something error + */ +s32 rtl8188fu_xmit_buf_handler(PADAPTER padapter) +{ + /*PHAL_DATA_TYPE phal; */ + struct xmit_priv *pxmitpriv; + struct xmit_buf *pxmitbuf; + s32 ret; + + + /*phal = GET_HAL_DATA(padapter); */ + pxmitpriv = &padapter->xmitpriv; + + ret = _rtw_down_sema(&pxmitpriv->xmit_sema); + if (_FAIL == ret) { + RT_TRACE(_module_hal_xmit_c_, _drv_emerg_, + ("%s: down SdioXmitBufSema fail!\n", __func__)); + return _FAIL; + } + if (RTW_CANNOT_RUN(padapter)) { + RT_TRACE(_module_hal_xmit_c_, _drv_notice_ + , ("%s: bDriverStopped(%s) bSurpriseRemoved(%s)!\n" + , __func__ + , rtw_is_drv_stopped(padapter)?"True":"False" + , rtw_is_surprise_removed(padapter)?"True":"False"); + return _FAIL; + } + + if (check_pending_xmitbuf(pxmitpriv) == _FALSE) + return _SUCCESS; + +#ifdef CONFIG_LPS_LCLK + ret = rtw_register_tx_alive(padapter); + if (ret != _SUCCESS) { + RT_TRACE(_module_hal_xmit_c_, _drv_notice_, + ("%s: wait to leave LPS_LCLK\n", __func__)); + return _SUCCESS; + } +#endif + + do { + pxmitbuf = dequeue_pending_xmitbuf(pxmitpriv); + if (pxmitbuf == NULL) break; + + rtw_write_port(padapter, pxmitbuf->ff_hwaddr, pxmitbuf->len, (unsigned char *)pxmitbuf); + + } while (1); + +#ifdef CONFIG_LPS_LCLK + rtw_unregister_tx_alive(padapter); +#endif + + return _SUCCESS; +} +#endif + + +static s32 rtw_dump_xframe(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + s32 ret = _SUCCESS; + s32 inner_ret = _SUCCESS; + int t, sz, w_sz, pull = 0; + u8 *mem_addr; + u32 ff_hwaddr; + struct xmit_buf *pxmitbuf = pxmitframe->pxmitbuf; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + + if ((pxmitframe->frame_tag == DATA_FRAMETAG) && + (pxmitframe->attrib.ether_type != 0x0806) && + (pxmitframe->attrib.ether_type != 0x888e) && + (pxmitframe->attrib.dhcp_pkt != 1)) + rtw_issue_addbareq_cmd(padapter, pxmitframe); + + mem_addr = pxmitframe->buf_addr; + + RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_dump_xframe()\n")); + + for (t = 0; t < pattrib->nr_frags; t++) { + if (inner_ret != _SUCCESS && ret == _SUCCESS) + ret = _FAIL; + + if (t != (pattrib->nr_frags - 1)) { + RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("pattrib->nr_frags=%d\n", pattrib->nr_frags)); + + sz = pxmitpriv->frag_len; + sz = sz - 4 - (psecuritypriv->sw_encrypt ? 0 : pattrib->icv_len); + } else /*no frag */ + sz = pattrib->last_txcmdsz; + + pull = update_txdesc(pxmitframe, mem_addr, sz, _FALSE); +/* rtl8188f_update_txdesc(pxmitframe, mem_addr+PACKET_OFFSET_SZ); */ + + if (pull) { + mem_addr += PACKET_OFFSET_SZ; /*pull txdesc head */ + + /*pxmitbuf ->pbuf = mem_addr; */ + pxmitframe->buf_addr = mem_addr; + + w_sz = sz + TXDESC_SIZE; + } else + w_sz = sz + TXDESC_SIZE + PACKET_OFFSET_SZ; + + ff_hwaddr = rtw_get_ff_hwaddr(pxmitframe); +#ifdef CONFIG_XMIT_THREAD_MODE + pxmitbuf->len = w_sz; + pxmitbuf->ff_hwaddr = ff_hwaddr; + enqueue_pending_xmitbuf(pxmitpriv, pxmitbuf); +#else + inner_ret = rtw_write_port(padapter, ff_hwaddr, w_sz, (unsigned char *)pxmitbuf); +#endif + rtw_count_tx_stats(padapter, pxmitframe, sz); + + + RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_write_port, w_sz=%d\n", w_sz)); + /*DBG_8192C("rtw_write_port, w_sz=%d, sz=%d, txdesc_sz=%d, tid=%d\n", w_sz, sz, w_sz-sz, pattrib->priority); */ + + mem_addr += w_sz; + + mem_addr = (u8 *)RND4(((SIZE_PTR)(mem_addr))); + + } + + rtw_free_xmitframe(pxmitpriv, pxmitframe); + + if (ret != _SUCCESS) + rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_UNKNOWN); + + return ret; +} + +#ifdef CONFIG_USB_TX_AGGREGATION +static u32 xmitframe_need_length(struct xmit_frame *pxmitframe) +{ + struct pkt_attrib *pattrib = &pxmitframe->attrib; + + u32 len = 0; + + /* no consider fragement */ + len = pattrib->hdrlen + pattrib->iv_len + + SNAP_SIZE + sizeof(u16) + + pattrib->pktlen + + ((pattrib->bswenc) ? pattrib->icv_len : 0); + + if (pattrib->encrypt == _TKIP_) + len += 8; + + return len; +} + +#define IDEA_CONDITION 1 /* check all packets before enqueue */ +s32 rtl8188fu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct xmit_frame *pxmitframe = NULL; + struct xmit_frame *pfirstframe = NULL; + + /* aggregate variable */ + struct hw_xmit *phwxmit; + struct sta_info *psta = NULL; + struct tx_servq *ptxservq = NULL; + + _irqL irqL; + _list *xmitframe_plist = NULL, *xmitframe_phead = NULL; + + u32 pbuf; /* next pkt address */ + u32 pbuf_tail; /* last pkt tail */ + u32 len; /* packet length, except TXDESC_SIZE and PKT_OFFSET */ + + u32 bulkSize = pHalData->UsbBulkOutSize; + u8 descCount; + u32 bulkPtr; + + /* dump frame variable */ + u32 ff_hwaddr; + + _list *sta_plist, *sta_phead; + u8 single_sta_in_queue = _FALSE; + +#ifndef IDEA_CONDITION + int res = _SUCCESS; +#endif + + RT_TRACE(_module_rtl8192c_xmit_c_, _drv_info_, ("+xmitframe_complete\n")); + + + /* check xmitbuffer is ok */ + if (pxmitbuf == NULL) { + pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv); + if (pxmitbuf == NULL) return _FALSE; + } + + + /*3 1. pick up first frame */ + do { + rtw_free_xmitframe(pxmitpriv, pxmitframe); + + pxmitframe = rtw_dequeue_xframe(pxmitpriv, pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry); + if (pxmitframe == NULL) { + /* no more xmit frame, release xmit buffer */ + rtw_free_xmitbuf(pxmitpriv, pxmitbuf); + return _FALSE; + } + + +#ifndef IDEA_CONDITION + if (pxmitframe->frame_tag != DATA_FRAMETAG) { + RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_, + ("xmitframe_complete: frame tag(%d) is not DATA_FRAMETAG(%d)!\n", + pxmitframe->frame_tag, DATA_FRAMETAG)); +/* rtw_free_xmitframe(pxmitpriv, pxmitframe); */ + continue; + } + + /* TID 0~15 */ + if ((pxmitframe->attrib.priority < 0) || + (pxmitframe->attrib.priority > 15)) { + RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_, + ("xmitframe_complete: TID(%d) should be 0~15!\n", + pxmitframe->attrib.priority)); +/* rtw_free_xmitframe(pxmitpriv, pxmitframe); */ + continue; + } +#endif + + pxmitframe->pxmitbuf = pxmitbuf; + pxmitframe->buf_addr = pxmitbuf->pbuf; + pxmitbuf->priv_data = pxmitframe; + + /* pxmitframe->agg_num = 1; */ /* alloc xmitframe should assign to 1. */ + /* pxmitframe->pkt_offset = 1; */ /* first frame of aggregation, reserve offset */ + pxmitframe->pkt_offset = (PACKET_OFFSET_SZ/8); + + if (rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe) == _FALSE) { + DBG_871X("%s coalesce 1st xmitframe failed\n", __func__); + continue; + } + + + /* always return ndis_packet after rtw_xmitframe_coalesce */ + rtw_os_xmit_complete(padapter, pxmitframe); + + break; + } while (1); + + /*3 2. aggregate same priority and same DA(AP or STA) frames */ + pfirstframe = pxmitframe; + len = xmitframe_need_length(pfirstframe) + TXDESC_OFFSET; + pbuf_tail = len; + pbuf = _RND8(pbuf_tail); + + /* check pkt amount in one bluk */ + descCount = 0; + bulkPtr = bulkSize; + if (pbuf < bulkPtr) + descCount++; + else { + descCount = 0; + bulkPtr = ((pbuf / bulkSize) + 1) * bulkSize; /* round to next bulkSize */ + } + + /* dequeue same priority packet from station tx queue */ + psta = pfirstframe->attrib.psta; + switch (pfirstframe->attrib.priority) { + case 1: + case 2: + ptxservq = &(psta->sta_xmitpriv.bk_q); + phwxmit = pxmitpriv->hwxmits + 3; + break; + + case 4: + case 5: + ptxservq = &(psta->sta_xmitpriv.vi_q); + phwxmit = pxmitpriv->hwxmits + 1; + break; + + case 6: + case 7: + ptxservq = &(psta->sta_xmitpriv.vo_q); + phwxmit = pxmitpriv->hwxmits; + break; + + case 0: + case 3: + default: + ptxservq = &(psta->sta_xmitpriv.be_q); + phwxmit = pxmitpriv->hwxmits + 2; + break; + } + + _enter_critical_bh(&pxmitpriv->lock, &irqL); + + sta_phead = get_list_head(phwxmit->sta_queue); + sta_plist = get_next(sta_phead); + single_sta_in_queue = rtw_end_of_queue_search(sta_phead, get_next(sta_plist)); + + xmitframe_phead = get_list_head(&ptxservq->sta_pending); + xmitframe_plist = get_next(xmitframe_phead); + while (rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist) == _FALSE) { + pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); + xmitframe_plist = get_next(xmitframe_plist); + + if (_FAIL == rtw_hal_busagg_qsel_check(padapter, pfirstframe->attrib.qsel, pxmitframe->attrib.qsel)) + break; + + len = xmitframe_need_length(pxmitframe) + TXDESC_SIZE; /* no offset */ + if (pbuf + len > MAX_XMITBUF_SZ) break; + + rtw_list_delete(&pxmitframe->list); + ptxservq->qcnt--; + phwxmit->accnt--; + +#ifndef IDEA_CONDITION + /* suppose only data frames would be in queue */ + if (pxmitframe->frame_tag != DATA_FRAMETAG) { + RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_, + ("xmitframe_complete: frame tag(%d) is not DATA_FRAMETAG(%d)!\n", + pxmitframe->frame_tag, DATA_FRAMETAG)); + rtw_free_xmitframe(pxmitpriv, pxmitframe); + continue; + } + + /* TID 0~15 */ + if ((pxmitframe->attrib.priority < 0) || + (pxmitframe->attrib.priority > 15)) { + RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_, + ("xmitframe_complete: TID(%d) should be 0~15!\n", + pxmitframe->attrib.priority)); + rtw_free_xmitframe(pxmitpriv, pxmitframe); + continue; + } +#endif + +/* pxmitframe->pxmitbuf = pxmitbuf; */ + pxmitframe->buf_addr = pxmitbuf->pbuf + pbuf; + + pxmitframe->agg_num = 0; /* not first frame of aggregation */ + pxmitframe->pkt_offset = 0; /* not first frame of aggregation, no need to reserve offset */ + + if (rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe) == _FALSE) { + DBG_871X("%s coalesce failed\n", __func__); + rtw_free_xmitframe(pxmitpriv, pxmitframe); + continue; + } + + + /* always return ndis_packet after rtw_xmitframe_coalesce */ + rtw_os_xmit_complete(padapter, pxmitframe); + + /* (len - TXDESC_SIZE) == pxmitframe->attrib.last_txcmdsz */ + update_txdesc(pxmitframe, pxmitframe->buf_addr, pxmitframe->attrib.last_txcmdsz, _TRUE); + + /* don't need xmitframe any more */ + rtw_free_xmitframe(pxmitpriv, pxmitframe); + + /* handle pointer and stop condition */ + pbuf_tail = pbuf + len; + pbuf = _RND8(pbuf_tail); + + pfirstframe->agg_num++; + if (MAX_TX_AGG_PACKET_NUMBER == pfirstframe->agg_num) + break; + + if (pbuf < bulkPtr) { + descCount++; + if (descCount == pHalData->UsbTxAggDescNum) + break; + } else { + descCount = 0; + bulkPtr = ((pbuf / bulkSize) + 1) * bulkSize; + } + } + if (_rtw_queue_empty(&ptxservq->sta_pending) == _TRUE) + rtw_list_delete(&ptxservq->tx_pending); + else if (single_sta_in_queue == _FALSE) { + /* Re-arrange the order of stations in this ac queue to balance the service for these stations */ + rtw_list_delete(&ptxservq->tx_pending); + rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(phwxmit->sta_queue)); + } + + _exit_critical_bh(&pxmitpriv->lock, &irqL); + + if ((pfirstframe->attrib.ether_type != 0x0806) && + (pfirstframe->attrib.ether_type != 0x888e) && + (pfirstframe->attrib.dhcp_pkt != 1)) + rtw_issue_addbareq_cmd(padapter, pfirstframe); + +#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX + /*3 3. update first frame txdesc */ + if ((PACKET_OFFSET_SZ != 0) + && (pbuf_tail % bulkSize) == 0) { + /* remove pkt_offset */ + pbuf_tail -= PACKET_OFFSET_SZ; + pfirstframe->buf_addr += PACKET_OFFSET_SZ; + pfirstframe->pkt_offset = 0; + } +#endif /* CONFIG_USE_USB_BUFFER_ALLOC_TX */ + update_txdesc(pfirstframe, pfirstframe->buf_addr, pfirstframe->attrib.last_txcmdsz, _TRUE); + + /*3 4. write xmit buffer to USB FIFO */ + ff_hwaddr = rtw_get_ff_hwaddr(pfirstframe); + + /* xmit address == ((xmit_frame*)pxmitbuf->priv_data)->buf_addr */ + rtw_write_port(padapter, ff_hwaddr, pbuf_tail, (u8 *)pxmitbuf); + + + /*3 5. update statisitc */ + pbuf_tail -= (pfirstframe->agg_num * TXDESC_SIZE); + if (pfirstframe->pkt_offset == 1) pbuf_tail -= PACKET_OFFSET_SZ; + + rtw_count_tx_stats(padapter, pfirstframe, pbuf_tail); + + rtw_free_xmitframe(pxmitpriv, pfirstframe); + + return _TRUE; +} + +#else + +s32 rtl8188fu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) +{ + + struct hw_xmit *phwxmits; + sint hwentry; + struct xmit_frame *pxmitframe = NULL; + int res = _SUCCESS, xcnt = 0; + + phwxmits = pxmitpriv->hwxmits; + hwentry = pxmitpriv->hwxmit_entry; + + RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("xmitframe_complete()\n")); + + if (pxmitbuf == NULL) { + pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv); + if (!pxmitbuf) + return _FALSE; + } + + + do { + pxmitframe = rtw_dequeue_xframe(pxmitpriv, phwxmits, hwentry); + + if (pxmitframe) { + pxmitframe->pxmitbuf = pxmitbuf; + + pxmitframe->buf_addr = pxmitbuf->pbuf; + + pxmitbuf->priv_data = pxmitframe; + + if ((pxmitframe->frame_tag & 0x0f) == DATA_FRAMETAG) { + if (pxmitframe->attrib.priority <= 15) /*TID0~15 */ + res = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe); + + rtw_os_xmit_complete(padapter, pxmitframe);/*always return ndis_packet after rtw_xmitframe_coalesce */ + } + + + RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("xmitframe_complete(): rtw_dump_xframe\n")); + + + if (res == _SUCCESS) + rtw_dump_xframe(padapter, pxmitframe); + else { + rtw_free_xmitbuf(pxmitpriv, pxmitbuf); + rtw_free_xmitframe(pxmitpriv, pxmitframe); + } + + xcnt++; + + } else { + rtw_free_xmitbuf(pxmitpriv, pxmitbuf); + return _FALSE; + } + + break; + + } while (0/*xcnt < (NR_XMITFRAME >> 3)*/); + + return _TRUE; + +} +#endif + + + +static s32 xmitframe_direct(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + s32 res = _SUCCESS; + + + res = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe); + if (res == _SUCCESS) + rtw_dump_xframe(padapter, pxmitframe); + + return res; +} + +/* + * Return + * _TRUE dump packet directly + * _FALSE enqueue packet + */ +static s32 pre_xmitframe(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + _irqL irqL; + s32 res; + struct xmit_buf *pxmitbuf = NULL; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + u8 lg_sta_num; + + _enter_critical_bh(&pxmitpriv->lock, &irqL); + + if (rtw_txframes_sta_ac_pending(padapter, pattrib) > 0) + goto enqueue; + + if (rtw_xmit_ac_blocked(padapter) == _TRUE) + goto enqueue; + + rtw_dev_iface_status(padapter, NULL, NULL , &lg_sta_num, NULL, NULL); + if (lg_sta_num) + goto enqueue; + + pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv); + if (pxmitbuf == NULL) + goto enqueue; + + _exit_critical_bh(&pxmitpriv->lock, &irqL); + + pxmitframe->pxmitbuf = pxmitbuf; + pxmitframe->buf_addr = pxmitbuf->pbuf; + pxmitbuf->priv_data = pxmitframe; + + if (xmitframe_direct(padapter, pxmitframe) != _SUCCESS) { + rtw_free_xmitbuf(pxmitpriv, pxmitbuf); + rtw_free_xmitframe(pxmitpriv, pxmitframe); + } + + return _TRUE; + +enqueue: + res = rtw_xmitframe_enqueue(padapter, pxmitframe); + _exit_critical_bh(&pxmitpriv->lock, &irqL); + + if (res != _SUCCESS) { + RT_TRACE(_module_xmit_osdep_c_, _drv_err_, ("pre_xmitframe: enqueue xmitframe fail\n")); + rtw_free_xmitframe(pxmitpriv, pxmitframe); + + pxmitpriv->tx_drop++; + return _TRUE; + } + + return _FALSE; +} + +s32 rtl8188fu_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe) +{ + return rtw_dump_xframe(padapter, pmgntframe); +} + +/* + * Return + * _TRUE dump packet directly ok + * _FALSE temporary can't transmit packets to hardware + */ +s32 rtl8188fu_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + return pre_xmitframe(padapter, pxmitframe); +} + +s32 rtl8188fu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe) +{ + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + s32 err; + + err = rtw_xmitframe_enqueue(padapter, pxmitframe); + if (err != _SUCCESS) { + rtw_free_xmitframe(pxmitpriv, pxmitframe); + + pxmitpriv->tx_drop++; + } else { +#ifdef PLATFORM_LINUX + tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); +#endif + } + + return err; + +} + + +#ifdef CONFIG_HOSTAPD_MLME + +static void rtl8188fu_hostap_mgnt_xmit_cb(struct urb *urb) +{ +#ifdef PLATFORM_LINUX + struct sk_buff *skb = (struct sk_buff *)urb->context; + + /*DBG_8192C("%s\n", __func__); */ + + rtw_skb_free(skb); +#endif +} + +s32 rtl8188fu_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt) +{ +#ifdef PLATFORM_LINUX + u16 fc; + int rc, len, pipe; + unsigned int bmcst, tid, qsel; + struct sk_buff *skb, *pxmit_skb; + struct urb *urb; + unsigned char *pxmitbuf; + struct tx_desc *ptxdesc; + struct ieee80211_hdr *tx_hdr; + struct hostapd_priv *phostapdpriv = padapter->phostapdpriv; + struct net_device *pnetdev = padapter->pnetdev; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter); + + + /*DBG_8192C("%s\n", __func__); */ + + skb = pkt; + + len = skb->len; + tx_hdr = (struct ieee80211_hdr *)(skb->data); + fc = le16_to_cpu(tx_hdr->frame_ctl); + bmcst = IS_MCAST(tx_hdr->addr1); + + if ((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_MGMT) + goto _exit; + + pxmit_skb = rtw_skb_alloc(len + TXDESC_SIZE); + + if (!pxmit_skb) + goto _exit; + + pxmitbuf = pxmit_skb->data; + + urb = usb_alloc_urb(0, GFP_ATOMIC); + if (!urb) + goto _exit; + + /* ----- fill tx desc ----- */ + ptxdesc = (struct tx_desc *)pxmitbuf; + _rtw_memset(ptxdesc, 0, sizeof(*ptxdesc)); + + /*offset 0 */ + ptxdesc->txdw0 |= cpu_to_le32(len & 0x0000ffff); + ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00ff0000); /*default = 32 bytes for TX Desc */ + ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG); + + if (bmcst) + ptxdesc->txdw0 |= cpu_to_le32(BIT(24)); + + /*offset 4 */ + ptxdesc->txdw1 |= cpu_to_le32(0x00);/*MAC_ID */ + + ptxdesc->txdw1 |= cpu_to_le32((0x12 << QSEL_SHT) & 0x00001f00); + + ptxdesc->txdw1 |= cpu_to_le32((0x06 << 16) & 0x000f0000); /*b mode */ + + /*offset 8 */ + + /*offset 12 */ + ptxdesc->txdw3 |= cpu_to_le32((le16_to_cpu(tx_hdr->seq_ctl) << 16) & 0xffff0000); + + /*offset 16 */ + ptxdesc->txdw4 |= cpu_to_le32(BIT(8));/*driver uses rate */ + + /*offset 20 */ + + + /*HW append seq */ + ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); /* Hw set sequence number */ + ptxdesc->txdw3 |= cpu_to_le32((8 << 28)); /*set bit3 to 1. Suugested by TimChen. 2009.12.29. */ + + + rtl8192cu_cal_txdesc_chksum(ptxdesc); + /* ----- end of fill tx desc ----- */ + + /* */ + skb_put(pxmit_skb, len + TXDESC_SIZE); + pxmitbuf = pxmitbuf + TXDESC_SIZE; + _rtw_memcpy(pxmitbuf, skb->data, len); + + /*DBG_8192C("mgnt_xmit, len=%x\n", pxmit_skb->len); */ + + + /* ----- prepare urb for submit ----- */ + + /*translate DMA FIFO addr to pipehandle */ + /*pipe = ffaddr2pipehdl(pdvobj, MGT_QUEUE_INX); */ + pipe = usb_sndbulkpipe(pdvobj->pusbdev, pHalData->Queue2EPNum[(u8)MGT_QUEUE_INX] & 0x0f); + + usb_fill_bulk_urb(urb, pdvobj->pusbdev, pipe, + pxmit_skb->data, pxmit_skb->len, rtl8192cu_hostap_mgnt_xmit_cb, pxmit_skb); + + urb->transfer_flags |= URB_ZERO_PACKET; + usb_anchor_urb(urb, &phostapdpriv->anchored); + rc = usb_submit_urb(urb, GFP_ATOMIC); + if (rc < 0) { + usb_unanchor_urb(urb); + kfree_skb(skb); + } + usb_free_urb(urb); + + +_exit: + + rtw_skb_free(skb); + +#endif + + return 0; + +} +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/usb/usb_halinit.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/usb/usb_halinit.c new file mode 100644 index 000000000..edb8e5ca9 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/usb/usb_halinit.c @@ -0,0 +1,2556 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#define _USB_HALINIT_C_ + +#include + +static void _dbg_dump_macreg(_adapter *padapter) +{ + u32 offset = 0; + u32 val32 = 0; + u32 index = 0; + + for (index = 0; index < 64; index++) { + offset = index * 4; + val32 = rtw_read32(padapter, offset); + DBG_8192C("offset : 0x%02x ,val:0x%08x\n", offset, val32); + } +} + +static VOID +_ConfigChipOutEP_8188F( + IN PADAPTER pAdapter, + IN u8 NumOutPipe +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + + pHalData->OutEpQueueSel = 0; + pHalData->OutEpNumber = 0; + + switch (NumOutPipe) { + case 4: + pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ | TX_SELE_NQ; + pHalData->OutEpNumber = 4; + break; + case 3: + pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ | TX_SELE_NQ; + pHalData->OutEpNumber = 3; + break; + case 2: + pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_NQ; + pHalData->OutEpNumber = 2; + break; + case 1: + pHalData->OutEpQueueSel = TX_SELE_HQ; + pHalData->OutEpNumber = 1; + break; + default: + break; + + } + DBG_871X("%s OutEpQueueSel(0x%02x), OutEpNumber(%d)\n", __func__, pHalData->OutEpQueueSel, pHalData->OutEpNumber); + +} + +static BOOLEAN HalUsbSetQueuePipeMapping8188FUsb( + IN PADAPTER pAdapter, + IN u8 NumInPipe, + IN u8 NumOutPipe +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + BOOLEAN result = _FALSE; + + _ConfigChipOutEP_8188F(pAdapter, NumOutPipe); + + /* Normal chip with one IN and one OUT doesn't have interrupt IN EP. */ + if (1 == pHalData->OutEpNumber) { + if (1 != NumInPipe) + return result; + } + + /* All config other than above support one Bulk IN and one Interrupt IN. */ + /*if(2 != NumInPipe){ */ + /* return result; */ + /*} */ + + result = Hal_MappingOutPipe(pAdapter, NumOutPipe); + + return result; + +} + +void rtl8188fu_interface_configure(_adapter *padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + + if (IS_HIGH_SPEED_USB(padapter)) { + /* HIGH SPEED */ + pHalData->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE;/*512 bytes */ + } else { + /* FULL SPEED */ + pHalData->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE;/*64 bytes */ + } + + pHalData->interfaceIndex = pdvobjpriv->InterfaceNumber; + +#ifdef CONFIG_USB_TX_AGGREGATION + pHalData->UsbTxAggMode = 1; + pHalData->UsbTxAggDescNum = 0x6; /* only 4 bits */ +#endif + +#ifdef CONFIG_USB_RX_AGGREGATION + pHalData->UsbRxAggMode = USB_RX_AGG_USB; + pHalData->UsbRxAggBlockCount = 0x5; /* unit: 4KB */ + pHalData->UsbRxAggBlockTimeout = 0x20; /* unit: 32us */ + pHalData->UsbRxAggPageCount = 0xF; /* uint: 1KB */ + pHalData->UsbRxAggPageTimeout = 0x20; /* unit: 32us */ +#endif + + HalUsbSetQueuePipeMapping8188FUsb(padapter, + pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes); + +} + +static u32 _InitPowerOn_8188FU(PADAPTER padapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct registry_priv *regsty = dvobj_to_regsty(dvobj); + u32 status = _SUCCESS; + u16 value16 = 0; + u8 value8 = 0; + u32 value32; + + /* check to apply user defined pll_ref_clk_sel */ + if ((regsty->pll_ref_clk_sel & 0x0F) != 0x0F) + rtl8188f_set_pll_ref_clk_sel(padapter, regsty->pll_ref_clk_sel); + + /* HW Power on sequence */ + if (!HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, rtl8188F_card_enable_flow)) + return _FAIL; + + /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */ + /* Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31. */ + rtw_write8(padapter, REG_CR_8188F, 0x00); /*suggseted by zhouzhou, by page, 20111230 */ + value16 = rtw_read16(padapter, REG_CR_8188F); + value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN + | PROTOCOL_EN | SCHEDULE_EN | ENSEC | CALTMR_EN); + rtw_write16(padapter, REG_CR_8188F, value16); + +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_PowerOnSetting(padapter); + + /* external switch to S1 */ + /* 0x38[11] = 0x1 */ + /* 0x4c[23] = 0x1 */ + /* 0x64[0] = 0 */ + value16 = rtw_read16(padapter, REG_PWR_DATA); + /* Switch the control of EESK, EECS to RFC for DPDT or Antenna switch */ + value16 |= BIT(11); /* BIT_EEPRPAD_RFE_CTRL_EN */ + rtw_write16(padapter, REG_PWR_DATA, value16); + /*DBG_8192C("%s: REG_PWR_DATA(0x%x)=0x%04X\n", __func__, REG_PWR_DATA, rtw_read16(padapter, REG_PWR_DATA)); */ + + value32 = rtw_read32(padapter, REG_LEDCFG0); + value32 |= BIT(23); /* DPDT_SEL_EN, 1 for SW control */ + rtw_write32(padapter, REG_LEDCFG0, value32); + /*DBG_8192C("%s: REG_LEDCFG0(0x%x)=0x%08X\n", __func__, REG_LEDCFG0, rtw_read32(padapter, REG_LEDCFG0)); */ + + value8 = rtw_read8(padapter, REG_PAD_CTRL1_8188F); + value8 &= ~BIT(0); /* BIT_SW_DPDT_SEL_DATA, DPDT_SEL default configuration */ + rtw_write8(padapter, REG_PAD_CTRL1_8188F, value8); + /*DBG_8192C("%s: REG_PAD_CTRL1(0x%x)=0x%02X\n", __func__, REG_PAD_CTRL1_8188F, rtw_read8(padapter, REG_PAD_CTRL1_8188F)); */ +#endif /* CONFIG_BT_COEXIST */ + + return status; +} + + + +/*------------------------------------------------------------------------- */ +/* */ +/* LLT R/W/Init function */ +/* */ +/*------------------------------------------------------------------------- */ +static u8 _LLTWrite( + IN PADAPTER Adapter, + IN u32 address, + IN u32 data +) +{ + u8 status = _SUCCESS; + s8 count = POLLING_LLT_THRESHOLD; + u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS); + + rtw_write32(Adapter, REG_LLT_INIT, value); + + /*polling */ + do { + value = rtw_read32(Adapter, REG_LLT_INIT); + if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) + break; + } while (--count); + + if (count <= 0) { + DBG_871X("Failed to polling write LLT done at address %d!\n", address); + status = _FAIL; + } + return status; + +} + + + +/*--------------------------------------------------------------- */ +/* */ +/* MAC init functions */ +/* */ +/*--------------------------------------------------------------- */ +/* + * USB has no hardware interrupt, + * so no need to initialize HIMR. + */ +static void _InitInterrupt(PADAPTER padapter) +{ +#ifdef CONFIG_SUPPORT_USB_INT + /* clear interrupt, write 1 clear */ + rtw_write32(padapter, REG_HISR0_8188F, 0xFFFFFFFF); + rtw_write32(padapter, REG_HISR1_8188F, 0xFFFFFFFF); +#endif /* CONFIG_SUPPORT_USB_INT */ +} + +static void _InitQueueReservedPage(PADAPTER padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct registry_priv *pregistrypriv = &padapter->registrypriv; + u32 outEPNum = (u32)pHalData->OutEpNumber; + u32 numHQ = 0; + u32 numLQ = 0; + u32 numNQ = 0; + u32 numPubQ; + u32 value32; + u8 value8; + BOOLEAN bWiFiConfig = pregistrypriv->wifi_spec; + + if (pHalData->OutEpQueueSel & TX_SELE_HQ) + numHQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_HPQ_8188F : NORMAL_PAGE_NUM_HPQ_8188F; + + if (pHalData->OutEpQueueSel & TX_SELE_LQ) + numLQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_LPQ_8188F : NORMAL_PAGE_NUM_LPQ_8188F; + + /* NOTE: This step shall be proceed before writing REG_RQPN. */ + if (pHalData->OutEpQueueSel & TX_SELE_NQ) + numNQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_NPQ_8188F : NORMAL_PAGE_NUM_NPQ_8188F; + value8 = (u8)_NPQ(numNQ); + rtw_write8(padapter, REG_RQPN_NPQ, value8); + + numPubQ = TX_TOTAL_PAGE_NUMBER_8188F - numHQ - numLQ - numNQ; + + /* TX DMA */ + value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN; + rtw_write32(padapter, REG_RQPN, value32); + +} + +static void _InitTxBufferBoundary(PADAPTER padapter) +{ + struct registry_priv *pregistrypriv = &padapter->registrypriv; +#ifdef CONFIG_CONCURRENT_MODE + u8 val8; +#endif /* CONFIG_CONCURRENT_MODE */ + + /*u16 txdmactrl; */ + u8 txpktbuf_bndy; + + if (!pregistrypriv->wifi_spec) + txpktbuf_bndy = TX_PAGE_BOUNDARY_8188F; + else { + /*for WMM */ + txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_8188F; + } + + rtw_write8(padapter, REG_TXPKTBUF_BCNQ_BDNY_8188F, txpktbuf_bndy); + rtw_write8(padapter, REG_TXPKTBUF_MGQ_BDNY_8188F, txpktbuf_bndy); + rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD_8188F, txpktbuf_bndy); + rtw_write8(padapter, REG_TRXFF_BNDY, txpktbuf_bndy); + rtw_write8(padapter, REG_TDECTRL + 1, txpktbuf_bndy); + +#ifdef CONFIG_CONCURRENT_MODE + val8 = txpktbuf_bndy + 8; + rtw_write8(padapter, REG_BCNQ1_BDNY, val8); + rtw_write8(padapter, REG_DWBCN1_CTRL_8188F + 1, val8); /* BCN1_HEAD */ + + val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8188F + 2); + val8 |= BIT(1); /* BIT1- BIT_SW_BCN_SEL_EN */ + rtw_write8(padapter, REG_DWBCN1_CTRL_8188F + 2, val8); +#endif /* CONFIG_CONCURRENT_MODE */ +} + + +VOID +_InitTransferPageSize_8188fu( + PADAPTER Adapter +) +{ + + u1Byte value8; + value8 = _PSRX(PBP_256) | _PSTX(PBP_256); + + rtw_write8(Adapter, REG_PBP_8188F, value8); +} + + +static VOID +_InitNormalChipRegPriority( + IN PADAPTER Adapter, + IN u16 beQ, + IN u16 bkQ, + IN u16 viQ, + IN u16 voQ, + IN u16 mgtQ, + IN u16 hiQ +) +{ + u16 value16 = (rtw_read16(Adapter, REG_TRXDMA_CTRL_8188F) & 0x7); + + value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) | + _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) | + _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ); + + rtw_write16(Adapter, REG_TRXDMA_CTRL_8188F, value16); +} + + +static VOID +_InitNormalChipTwoOutEpPriority( + IN PADAPTER Adapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct registry_priv *pregistrypriv = &Adapter->registrypriv; + u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ; + + + u16 valueHi = 0; + u16 valueLow = 0; + + switch (pHalData->OutEpQueueSel) { + case (TX_SELE_HQ | TX_SELE_LQ): + valueHi = QUEUE_HIGH; + valueLow = QUEUE_LOW; + break; + case (TX_SELE_NQ | TX_SELE_LQ): + valueHi = QUEUE_NORMAL; + valueLow = QUEUE_LOW; + break; + case (TX_SELE_HQ | TX_SELE_NQ): + valueHi = QUEUE_HIGH; + valueLow = QUEUE_NORMAL; + break; + default: + /*RT_ASSERT(FALSE,("Shall not reach here!\n")); */ + break; + } + + if (!pregistrypriv->wifi_spec) { + beQ = valueLow; + bkQ = valueLow; + viQ = valueHi; + voQ = valueHi; + mgtQ = valueHi; + hiQ = valueHi; + } else { /*for WMM ,CONFIG_OUT_EP_WIFI_MODE */ + beQ = valueLow; + bkQ = valueHi; + viQ = valueHi; + voQ = valueLow; + mgtQ = valueHi; + hiQ = valueHi; + } + + _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ); + +} + +static VOID +_InitNormalChipThreeOutEpPriority( + IN PADAPTER padapter +) +{ + struct registry_priv *pregistrypriv = &padapter->registrypriv; + u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ; + + if (!pregistrypriv->wifi_spec) { /* typical setting */ + beQ = QUEUE_LOW; + bkQ = QUEUE_LOW; + viQ = QUEUE_NORMAL; + voQ = QUEUE_HIGH; + mgtQ = QUEUE_HIGH; + hiQ = QUEUE_HIGH; + } else { /* for WMM */ + beQ = QUEUE_LOW; + bkQ = QUEUE_NORMAL; + viQ = QUEUE_NORMAL; + voQ = QUEUE_HIGH; + mgtQ = QUEUE_HIGH; + hiQ = QUEUE_HIGH; + } + _InitNormalChipRegPriority(padapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ); +} + +static void _InitQueuePriority(PADAPTER padapter) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + switch (pHalData->OutEpNumber) { + case 2: + _InitNormalChipTwoOutEpPriority(padapter); + break; + case 3: + case 4: + _InitNormalChipThreeOutEpPriority(padapter); + break; + default: + /*RT_ASSERT(FALSE,("Shall not reach here!\n")); */ + break; + } + +} + + +static void _InitPageBoundary(PADAPTER padapter) +{ + /* RX Page Boundary */ + u16 rxff_bndy = RX_DMA_BOUNDARY_8188F; + + rtw_write16(padapter, (REG_TRXFF_BNDY + 2), rxff_bndy); + + /* TODO: ?? shall we set tx boundary? */ +} + +static VOID +_InitHardwareDropIncorrectBulkOut( + IN PADAPTER Adapter +) +{ + u32 value32 = rtw_read32(Adapter, REG_TXDMA_OFFSET_CHK); + value32 |= DROP_DATA_EN; + rtw_write32(Adapter, REG_TXDMA_OFFSET_CHK, value32); +} + +static VOID +_InitNetworkType( + IN PADAPTER Adapter +) +{ + u32 value32; + + value32 = rtw_read32(Adapter, REG_CR); + + /* TODO: use the other function to set network type */ +#if 0/*RTL8191C_FPGA_NETWORKTYPE_ADHOC */ + value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC); +#else + value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP); +#endif + rtw_write32(Adapter, REG_CR, value32); +/* RASSERT(pIoBase->rtw_read8(REG_CR + 2) == 0x2); */ +} + + +static VOID +_InitDriverInfoSize( + IN PADAPTER Adapter, + IN u8 drvInfoSize +) +{ + rtw_write8(Adapter, REG_RX_DRVINFO_SZ, drvInfoSize); +} + +static VOID +_InitWMACSetting( + IN PADAPTER Adapter +) +{ + /*u4Byte value32; */ + u16 value16; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + +/* pHalData->ReceiveConfig = AAP | APM | AM |AB |ADD3|APWRMGT| APP_ICV | APP_MIC |APP_FCS|ADF |ACF|AMF|HTC_LOC_CTRL|APP_PHYSTS; */ +/* pHalData->ReceiveConfig = AAP | APM | AM | AB | ADD3 | APWRMGT | APP_ICV | APP_MIC | ADF | ACF | AMF | HTC_LOC_CTRL | APP_PHYSTS; */ + pHalData->ReceiveConfig = RCR_APM | RCR_AM | RCR_AB | RCR_CBSSID_DATA | RCR_CBSSID_BCN | RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYST_RXFF; + + rtw_write32(Adapter, REG_RCR, pHalData->ReceiveConfig); + + /* Accept all data frames */ + value16 = 0xFFFF; + rtw_write16(Adapter, REG_RXFLTMAP2_8188F, value16); + + /* 2010.09.08 hpfan */ + /* Since ADF is removed from RCR, ps-poll will not be indicate to driver, */ + /* RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. */ + + value16 = 0x400; + rtw_write16(Adapter, REG_RXFLTMAP1_8188F, value16); + + /* Accept all management frames */ + value16 = 0xFFFF; + rtw_write16(Adapter, REG_RXFLTMAP0_8188F, value16); + +} + +static VOID +_InitAdaptiveCtrl( + IN PADAPTER Adapter +) +{ + u16 value16; + u32 value32; + + /* Response Rate Set */ + value32 = rtw_read32(Adapter, REG_RRSR); + value32 &= ~RATE_BITMAP_ALL; + value32 |= RATE_RRSR_CCK_ONLY_1M; + rtw_write32(Adapter, REG_RRSR, value32); + + /* CF-END Threshold */ + /*m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1); */ + + /* SIFS (used in NAV) */ + value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10); + rtw_write16(Adapter, REG_SPEC_SIFS, value16); + + /* Retry Limit */ + value16 = _LRL(0x30) | _SRL(0x30); + rtw_write16(Adapter, REG_RL, value16); + +} + +static VOID +_InitRateFallback( + IN PADAPTER Adapter +) +{ + /* Set Data Auto Rate Fallback Retry Count register. */ + rtw_write32(Adapter, REG_DARFRC, 0x00000000); + rtw_write32(Adapter, REG_DARFRC + 4, 0x10080404); + rtw_write32(Adapter, REG_RARFRC, 0x04030201); + rtw_write32(Adapter, REG_RARFRC + 4, 0x08070605); + +} + + +static VOID +_InitEDCA( + IN PADAPTER Adapter +) +{ + /* Set Spec SIFS (used in NAV) */ + rtw_write16(Adapter, REG_SPEC_SIFS, 0x100a); + rtw_write16(Adapter, REG_MAC_SPEC_SIFS, 0x100a); + + /* Set SIFS for CCK */ + rtw_write16(Adapter, REG_SIFS_CTX, 0x100a); + + /* Set SIFS for OFDM */ + rtw_write16(Adapter, REG_SIFS_TRX, 0x100a); + + /* TXOP */ + rtw_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B); + rtw_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F); + rtw_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324); + rtw_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226); +} + +#ifdef CONFIG_LED +static void _InitHWLed(PADAPTER Adapter) +{ + struct led_priv *pledpriv = &(Adapter->ledpriv); + + if (pledpriv->LedStrategy != HW_LED) + return; + +/* HW led control */ +/* to do .... */ +/*must consider cases of antenna diversity/ commbo card/solo card/mini card */ + +} +#endif /*CONFIG_LED */ + +static VOID +_InitRDGSetting_8188fu( + IN PADAPTER Adapter +) +{ + rtw_write8(Adapter, REG_RD_CTRL_8188F, 0xFF); + rtw_write16(Adapter, REG_RD_NAV_NXT_8188F, 0x200); + rtw_write8(Adapter, REG_RD_RESP_PKT_TH_8188F, 0x05); +} + +static VOID +_InitRetryFunction( + IN PADAPTER Adapter +) +{ + u8 value8; + + value8 = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL); + value8 |= EN_AMPDU_RTY_NEW; + rtw_write8(Adapter, REG_FWHW_TXQ_CTRL, value8); + + /* Set ACK timeout */ + rtw_write8(Adapter, REG_ACKTO, 0x40); +} + +static void _InitBurstPktLen(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + u8 tmp8; + + + tmp8 = rtw_read8(padapter, REG_RXDMA_PRO_8188F); + tmp8 &= ~(BIT(4) | BIT(5)); + switch (pHalData->UsbBulkOutSize) { + case USB_HIGH_SPEED_BULK_SIZE: + tmp8 |= BIT(4); /* set burst pkt len=512B */ + break; + case USB_FULL_SPEED_BULK_SIZE: + default: + tmp8 |= BIT(5); /* set burst pkt len=64B */ + break; + } + tmp8 |= BIT(1) | BIT(2) | BIT(3); + rtw_write8(padapter, REG_RXDMA_PRO_8188F, tmp8); + + pHalData->bSupportUSB3 = _FALSE; + + tmp8 = rtw_read8(padapter, REG_HT_SINGLE_AMPDU_8188F); + tmp8 |= BIT(7); /* enable single pkt ampdu */ + rtw_write8(padapter, REG_HT_SINGLE_AMPDU_8188F, tmp8); + rtw_write16(padapter, REG_MAX_AGGR_NUM_8188F, 0x0C14); + rtw_write8(padapter, REG_AMPDU_MAX_TIME_8188F, 0x70); + rtw_write32(padapter, REG_AMPDU_MAX_LENGTH_8188F, 0xffffffff); + if (pHalData->AMPDUBurstMode) + rtw_write8(padapter, REG_AMPDU_BURST_MODE_8188F, 0x5F); + + /* for VHT packet length 11K */ + rtw_write8(padapter, REG_RX_PKT_LIMIT_8188F, 0x18); + + rtw_write8(padapter, REG_PIFS_8188F, 0x00); + rtw_write8(padapter, REG_FWHW_TXQ_CTRL_8188F, 0x80); + rtw_write32(padapter, REG_FAST_EDCA_CTRL_8188F, 0x03086666); + rtw_write8(padapter, REG_USTIME_TSF_8188F, 0x28); + rtw_write8(padapter, REG_USTIME_EDCA_8188F, 0x28); + + /* to prevent mac is reseted by bus. 20111208, by Page */ + tmp8 = rtw_read8(padapter, REG_RSV_CTRL_8188F); + tmp8 |= BIT(5) | BIT(6); + rtw_write8(padapter, REG_RSV_CTRL_8188F, tmp8); +} + +/*----------------------------------------------------------------------------- + * Function: usb_AggSettingTxUpdate() + * + * Overview: Separate TX/RX parameters update independent for TP detection and + * dynamic TX/RX aggreagtion parameters update. + * + * Input: PADAPTER + * + * Output/Return: NONE + * + * Revised History: + * When Who Remark + * 12/10/2010 MHC Separate to smaller function. + * + *---------------------------------------------------------------------------*/ +static VOID +usb_AggSettingTxUpdate( + IN PADAPTER Adapter +) +{ +#ifdef CONFIG_USB_TX_AGGREGATION + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + /*PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); */ + u32 value32; + + if (Adapter->registrypriv.wifi_spec) + pHalData->UsbTxAggMode = _FALSE; + + if (pHalData->UsbTxAggMode) { + value32 = rtw_read32(Adapter, REG_DWBCN0_CTRL_8188F); + value32 = value32 & ~(BLK_DESC_NUM_MASK << BLK_DESC_NUM_SHIFT); + value32 |= ((pHalData->UsbTxAggDescNum & BLK_DESC_NUM_MASK) << BLK_DESC_NUM_SHIFT); + + rtw_write32(Adapter, REG_DWBCN0_CTRL_8188F, value32); + rtw_write8(Adapter, REG_DWBCN1_CTRL_8188F, pHalData->UsbTxAggDescNum << 1); + } + +#endif +} /* usb_AggSettingTxUpdate */ + + +/*----------------------------------------------------------------------------- + * Function: usb_AggSettingRxUpdate() + * + * Overview: Separate TX/RX parameters update independent for TP detection and + * dynamic TX/RX aggreagtion parameters update. + * + * Input: PADAPTER + * + * Output/Return: NONE + * + *---------------------------------------------------------------------------*/ +static void usb_AggSettingRxUpdate(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData; + u8 aggctrl; + u32 aggrx, rxdmamode; + + + pHalData = GET_HAL_DATA(padapter); + + aggctrl = rtw_read8(padapter, REG_TRXDMA_CTRL); + aggctrl &= ~RXDMA_AGG_EN; + + aggrx = rtw_read32(padapter, REG_RXDMA_AGG_PG_TH); + aggrx &= ~BIT_USB_RXDMA_AGG_EN; + aggrx &= ~0xFF0F; /* reset agg size and timeout */ + + rxdmamode = rtw_read8(padapter, REG_RXDMA_MODE); + +#ifdef CONFIG_USB_RX_AGGREGATION + switch (pHalData->UsbRxAggMode) { + case USB_RX_AGG_DMA: + aggctrl |= RXDMA_AGG_EN; + aggrx |= BIT_USB_RXDMA_AGG_EN; + aggrx |= (pHalData->UsbRxAggPageCount & 0xF); + aggrx |= (pHalData->UsbRxAggPageTimeout << 8); + rxdmamode |= BIT_DMA_MODE; + DBG_8192C("%s: RX Aggregation DMA mode, size=%dKB, timeout=%dus\n", + __func__, pHalData->UsbRxAggPageCount & 0xF, pHalData->UsbRxAggPageTimeout * 32); + break; + + case USB_RX_AGG_USB: + case USB_RX_AGG_MIX: + aggctrl |= RXDMA_AGG_EN; + aggrx &= ~BIT_USB_RXDMA_AGG_EN; + aggrx |= (pHalData->UsbRxAggBlockCount & 0xF); + aggrx |= (pHalData->UsbRxAggBlockTimeout << 8); + rxdmamode |= BIT_DMA_MODE; + DBG_8192C("%s: RX Aggregation USB mode, size=%dKB, timeout=%dus\n", + __func__, (pHalData->UsbRxAggBlockCount & 0xF) * 4, pHalData->UsbRxAggBlockTimeout * 32); + break; + + case USB_RX_AGG_DISABLE: + aggctrl &= ~RXDMA_AGG_EN; + aggrx &= ~BIT_USB_RXDMA_AGG_EN; + rxdmamode &= ~BIT_DMA_MODE; +#if defined(fallthrough) + fallthrough; +#endif + default: + DBG_8192C("%s: RX Aggregation Disable!\n", __func__); + break; + } +#endif /* CONFIG_USB_RX_AGGREGATION */ + + rtw_write8(padapter, REG_TRXDMA_CTRL, aggctrl); + rtw_write32(padapter, REG_RXDMA_AGG_PG_TH, aggrx); + rtw_write8(padapter, REG_RXDMA_MODE, rxdmamode); +} + +static VOID +_initUsbAggregationSetting( + IN PADAPTER Adapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + /* Tx aggregation setting */ + usb_AggSettingTxUpdate(Adapter); + + /* Rx aggregation setting */ + usb_AggSettingRxUpdate(Adapter); + + /* 201/12/10 MH Add for USB agg mode dynamic switch. */ + pHalData->UsbRxHighSpeedMode = _FALSE; +} + +static VOID +PHY_InitAntennaSelection8188F( + PADAPTER Adapter +) +{ + /* TODO: <20130114, Kordan> The following setting is only for DPDT and Fixed board type. */ + /* TODO: A better solution is configure it according EFUSE during the run-time. */ + PHY_SetMacReg(Adapter, 0x64, BIT20, 0x0); /*0x66[4]=0 */ + PHY_SetMacReg(Adapter, 0x64, BIT24, 0x0); /*0x66[8]=0 */ + PHY_SetMacReg(Adapter, 0x40, BIT4, 0x0); /*0x40[4]=0 */ + PHY_SetMacReg(Adapter, 0x40, BIT3, 0x1); /*0x40[3]=1 */ + PHY_SetMacReg(Adapter, 0x4C, BIT24, 0x1); /*0x4C[24:23]=10 */ + PHY_SetMacReg(Adapter, 0x4C, BIT23, 0x0); /*0x4C[24:23]=10 */ + PHY_SetBBReg(Adapter, 0x944, BIT1 | BIT0, 0x3); /*0x944[1:0]=11 */ + PHY_SetBBReg(Adapter, 0x930, bMaskByte0, 0x77); /*0x930[7:0]=77 */ + PHY_SetMacReg(Adapter, 0x38, BIT11, 0x1); /*0x38[11]=1 */ +} + +static VOID _InitAdhocWorkaroundParams(IN PADAPTER Adapter) +{ +#ifdef RTL8192CU_ADHOC_WORKAROUND_SETTING + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + pHalData->RegBcnCtrlVal = rtw_read8(Adapter, REG_BCN_CTRL); + pHalData->RegTxPause = rtw_read8(Adapter, REG_TXPAUSE); + pHalData->RegFwHwTxQCtrl = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL + 2); + pHalData->RegReg542 = rtw_read8(Adapter, REG_TBTT_PROHIBIT + 2); +#endif +} + +/* Set CCK and OFDM Block "ON" */ +static VOID _BBTurnOnBlock( + IN PADAPTER Adapter +) +{ +#if (DISABLE_BB_RF) + return; +#endif + + PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1); + PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1); +} + +#define MgntActSet_RF_State(...) + +enum { + Antenna_Lfet = 1, + Antenna_Right = 2, +}; + +/* */ +/* 2010/08/09 MH Add for power down check. */ +/* */ +static BOOLEAN +HalDetectPwrDownMode( + IN PADAPTER Adapter +) +{ + u8 tmpvalue; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter); + + EFUSE_ShadowRead(Adapter, 1, EEPROM_FEATURE_OPTION_8188F, (u32 *)&tmpvalue); + + /* 2010/08/25 MH INF priority > PDN Efuse value. */ + if (tmpvalue & BIT4 && pwrctrlpriv->reg_pdnmode) + pHalData->pwrdown = _TRUE; + else + pHalData->pwrdown = _FALSE; + + DBG_8192C("HalDetectPwrDownMode(): PDN=%d\n", pHalData->pwrdown); + return pHalData->pwrdown; + +} /* HalDetectPwrDownMode */ + + +/* */ +/* 2010/08/26 MH Add for selective suspend mode check. */ +/* If Efuse 0x0e bit1 is not enabled, we can not support selective suspend for Minicard and */ +/* slim card. */ +/* */ +static VOID +HalDetectSelectiveSuspendMode( + IN PADAPTER Adapter +) +{ +#if 0 /*amyma */ + u8 tmpvalue; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(Adapter); + + /* If support HW radio detect, we need to enable WOL ability, otherwise, we */ + /* can not use FW to notify host the power state switch. */ + + EFUSE_ShadowRead(Adapter, 1, EEPROM_USB_OPTIONAL1, (u32 *)&tmpvalue); + + DBG_8192C("HalDetectSelectiveSuspendMode(): SS "); + if (tmpvalue & BIT1) + DBG_8192C("Enable\n"); + else { + DBG_8192C("Disable\n"); + pdvobjpriv->RegUsbSS = _FALSE; + } + + /* 2010/09/01 MH According to Dongle Selective Suspend INF. We can switch SS mode. */ + if (pdvobjpriv->RegUsbSS && !SUPPORT_HW_RADIO_DETECT(pHalData)) { + /*PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); */ + + /*if (!pMgntInfo->bRegDongleSS) */ + /*{ */ + /* RT_TRACE(COMP_INIT, DBG_LOUD, ("Dongle disable SS\n")); */ + pdvobjpriv->RegUsbSS = _FALSE; + /*} */ + } +#endif +} /* HalDetectSelectiveSuspendMode */ +/*----------------------------------------------------------------------------- + * Function: HwSuspendModeEnable92Cu() + * + * Overview: HW suspend mode switch. + * + * Input: NONE + * + * Output: NONE + * + * Return: NONE + * + * Revised History: + * When Who Remark + * 08/23/2010 MHC HW suspend mode switch test.. + *---------------------------------------------------------------------------*/ +static VOID +HwSuspendModeEnable92Cu( + IN PADAPTER pAdapter, + IN u8 Type +) +{ + /*PRT_USB_DEVICE pDevice = GET_RT_USB_DEVICE(pAdapter); */ + u16 reg = rtw_read16(pAdapter, REG_GPIO_MUXCFG); + + /*if (!pDevice->RegUsbSS) */ + { + return; + } + + /* */ + /* 2010/08/23 MH According to Alfred's suggestion, we need to to prevent HW */ + /* to enter suspend mode automatically. Otherwise, it will shut down major power */ + /* domain and 8051 will stop. When we try to enter selective suspend mode, we */ + /* need to prevent HW to enter D2 mode aumotmatically. Another way, Host will */ + /* issue a S10 signal to power domain. Then it will cleat SIC setting(from Yngli). */ + /* We need to enable HW suspend mode when enter S3/S4 or disable. We need */ + /* to disable HW suspend mode for IPS/radio_off. */ + /* */ + /*RT_TRACE(COMP_RF, DBG_LOUD, ("HwSuspendModeEnable92Cu = %d\n", Type)); */ + if (Type == _FALSE) { + reg |= BIT14; + /*RT_TRACE(COMP_RF, DBG_LOUD, ("REG_GPIO_MUXCFG = %x\n", reg)); */ + rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg); + reg |= BIT12; + /*RT_TRACE(COMP_RF, DBG_LOUD, ("REG_GPIO_MUXCFG = %x\n", reg)); */ + rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg); + } else { + reg &= (~BIT12); + rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg); + reg &= (~BIT14); + rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg); + } + +} /* HwSuspendModeEnable92Cu */ +rt_rf_power_state RfOnOffDetect(IN PADAPTER pAdapter) +{ + /*HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); */ + u8 val8; + rt_rf_power_state rfpowerstate = rf_off; + + if (adapter_to_pwrctl(pAdapter)->bHWPowerdown) { + val8 = rtw_read8(pAdapter, REG_HSISR); + DBG_8192C("pwrdown, 0x5c(BIT7)=%02x\n", val8); + rfpowerstate = (val8 & BIT7) ? rf_off : rf_on; + } else { /* rf on/off */ + rtw_write8(pAdapter, REG_MAC_PINMUX_CFG, rtw_read8(pAdapter, REG_MAC_PINMUX_CFG) & ~(BIT3)); + val8 = rtw_read8(pAdapter, REG_GPIO_IO_SEL); + DBG_8192C("GPIO_IN=%02x\n", val8); + rfpowerstate = (val8 & BIT3) ? rf_on : rf_off; + } + return rfpowerstate; +} /* HalDetectPwrDownMode */ + +void _ps_open_RF(_adapter *padapter); + +#ifdef CONFIG_8188FTV_SOLUTION_D +/* +Write corresponding register of efuse. Indirect Write. +Offset: reg offset. +Value: u8 value +*/ +VOID WriteUSB2PHYReg(PADAPTER Adapter, u8 Offset, u8 Value) +{ + rtw_write8(Adapter, 0xFE41, Value); + rtw_write8(Adapter, 0xFE40, Offset); + rtw_write8(Adapter, 0xFE42, 0x81); +} + +/* +Read corresponding register of efuse. Indirect Read. +Offset: reg offset. +*/ +u1Byte ReadUSB2PHYReg(PADAPTER Adapter, u8 Offset) +{ + u8 value = 0; + rtw_write8(Adapter, 0xFE40, Offset); + rtw_write8(Adapter, 0xFE42, 0x81); + value = rtw_read8(Adapter, 0xFE43); + + return value; +} + +void rtl8188fu_solution_d(PADAPTER Adapter) +{ + u8 reg_val[6] = {0}; + u16 reg0mask = BIT(10) | BIT(11) | BIT(12) | BIT(13); + u16 reg1mask = BIT(0) | BIT(1) | BIT(2) | BIT(3); + + reg_val[0] = PHY_QueryMacReg(Adapter, 0x10, reg0mask); /* efuse 0x3 */ + reg_val[1] = PHY_QueryMacReg(Adapter, 0xC4, reg1mask); /* efuse 0xd */ + reg_val[2] = ReadUSB2PHYReg(Adapter, 0xC1); /* efuse 0x131 */ + reg_val[3] = PHY_QueryMacReg(Adapter, 0x4, BIT(11)); /* efuse 0xa */ + reg_val[4] = ReadUSB2PHYReg(Adapter, 0xD2); /* efuse 0x13a */ + reg_val[5] = ReadUSB2PHYReg(Adapter, 0xD3); /* efuse 0x13b */ + + if(!(reg_val[3] == 0 && reg_val[4] == 0 && reg_val[5] == 0x31)) /* solution "EP" not applied */ + { + if((reg_val[0] == 0xC && reg_val[1] == 0xC && reg_val[2] == 0xAE) /* solution O */ + ||(reg_val[0] == 0xF && reg_val[1] == 0xC && reg_val[2] == 0xAE) /* solution A */ + ||(reg_val[0] == 0xC && reg_val[1] == 0xB && reg_val[2] == 0xAE) /* solution B */ + ||(reg_val[0] == 0xC && reg_val[1] == 0xC && reg_val[2] == 0xBE)) /* solution C */ + { + /* apply solution D */ + PHY_SetMacReg(Adapter, 0x10, reg0mask, 0xF); + PHY_SetMacReg(Adapter, 0xC4, reg1mask, 0x7); + WriteUSB2PHYReg(Adapter, 0xE1, 0xB6); + DBG_871X("%s, Aplly Solution D\n", __func__); + } + else if(reg_val[0] == 0xF && reg_val[1] == 0x7 && reg_val[2] == 0xB6) + DBG_871X("%s, Solution D already apllied\n", __func__); + else + DBG_871X("%s, Unexpected efuse content\n", __func__); + } + else + DBG_871X("%s, Solution EP already applied\n", __func__); +} +#endif + +u32 rtl8188fu_hal_init(PADAPTER padapter) +{ + u8 value8 = 0, u1bRegCR; + u32 boundary, status = _SUCCESS; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + struct registry_priv *pregistrypriv = &padapter->registrypriv; + rt_rf_power_state eRfPowerStateToSet; + u32 NavUpper = WiFiNavUpperUs; + u32 value32; + u32 init_start_time = rtw_get_current_time(); + + +#ifdef DBG_HAL_INIT_PROFILING + + enum HAL_INIT_STAGES { + HAL_INIT_STAGES_BEGIN = 0, + HAL_INIT_STAGES_INIT_PW_ON, + HAL_INIT_STAGES_INIT_LLTT, + HAL_INIT_STAGES_MISC01, + HAL_INIT_STAGES_DOWNLOAD_FW, + HAL_INIT_STAGES_MAC, + HAL_INIT_STAGES_BB, + HAL_INIT_STAGES_RF, + HAL_INIT_STAGES_MISC02, + HAL_INIT_STAGES_TURN_ON_BLOCK, + HAL_INIT_STAGES_INIT_SECURITY, + HAL_INIT_STAGES_MISC11, + /*HAL_INIT_STAGES_RF_PS, */ + HAL_INIT_STAGES_INIT_HAL_DM, +/* HAL_INIT_STAGES_IQK, */ +/* HAL_INIT_STAGES_PW_TRACK, */ +/* HAL_INIT_STAGES_LCK, */ + HAL_INIT_STAGES_MISC21, + /*HAL_INIT_STAGES_INIT_PABIAS, */ + HAL_INIT_STAGES_BT_COEXIST, + /*HAL_INIT_STAGES_ANTENNA_SEL, */ + HAL_INIT_STAGES_MISC31, + HAL_INIT_STAGES_END, + HAL_INIT_STAGES_NUM + }; + + static char * const hal_init_stages_str[] = { + "HAL_INIT_STAGES_BEGIN", + "HAL_INIT_STAGES_INIT_PW_ON", + "HAL_INIT_STAGES_INIT_LLTT", + "HAL_INIT_STAGES_MISC01", + "HAL_INIT_STAGES_DOWNLOAD_FW", + "HAL_INIT_STAGES_MAC", + "HAL_INIT_STAGES_BB", + "HAL_INIT_STAGES_RF", + "HAL_INIT_STAGES_MISC02", + "HAL_INIT_STAGES_TURN_ON_BLOCK", + "HAL_INIT_STAGES_INIT_SECURITY", + "HAL_INIT_STAGES_MISC11", + /*"HAL_INIT_STAGES_RF_PS", */ + "HAL_INIT_STAGES_INIT_HAL_DM", +/* "HAL_INIT_STAGES_IQK", */ +/* "HAL_INIT_STAGES_PW_TRACK", */ +/* "HAL_INIT_STAGES_LCK", */ + "HAL_INIT_STAGES_MISC21", + /*"HAL_INIT_STAGES_INIT_PABIAS", */ + "HAL_INIT_STAGES_BT_COEXIST", + /*"HAL_INIT_STAGES_ANTENNA_SEL", */ + "HAL_INIT_STAGES_MISC31", + "HAL_INIT_STAGES_END", + }; + + int hal_init_profiling_i; + u32 hal_init_stages_timestamp[HAL_INIT_STAGES_NUM]; /*used to record the time of each stage's starting point */ + + for (hal_init_profiling_i = 0; hal_init_profiling_i < HAL_INIT_STAGES_NUM; hal_init_profiling_i++) + hal_init_stages_timestamp[hal_init_profiling_i] = 0; + +#define HAL_INIT_PROFILE_TAG(stage) { hal_init_stages_timestamp[(stage)] = rtw_get_current_time(); } +#else +#define HAL_INIT_PROFILE_TAG(stage) do {} while (0) +#endif /*DBG_HAL_INIT_PROFILING */ + + + + _func_enter_; + + HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN); + +/* if (rtw_is_surprise_removed(Adapter)) */ +/* return RT_STATUS_FAILURE; */ + +#if 0 /* To prevent Pomelo hanging. Added by tianzeyum. 2014.11.02 */ +#define REG_USB_ACCESS_TIMEOUT 0xFE4C + rtw_write8(padapter, REG_USB_ACCESS_TIMEOUT, 0x80); +#undef REG_USB_ACCESS_TIMEOUT +#endif + + + HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON); + status = rtw_hal_power_on(padapter); + if (status == _FAIL) { + RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init power on!\n")); + goto exit; + } + + /* Check if MAC has already power on. */ + value8 = rtw_read8(padapter, REG_SYS_CLKR_8188F + 1); + u1bRegCR = rtw_read8(padapter, REG_CR_8188F); + DBG_871X(" power-on :REG_SYS_CLKR 0x09=0x%02x. REG_CR 0x100=0x%02x.\n", value8, u1bRegCR); + if ((value8 & BIT3) && (u1bRegCR != 0 && u1bRegCR != 0xEA)) + DBG_871X(" MAC has already power on.\n"); + else { + /* Set FwPSState to ALL_ON mode to prevent from the I/O be return because of 32k */ + /* state which is set before sleep under wowlan mode. 2012.01.04. by tynli. */ + /*pHalData->FwPSState = FW_PS_STATE_ALL_ON_88E; */ + DBG_871X(" MAC has not been powered on yet.\n"); + } + + HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT); + if (!pregistrypriv->wifi_spec) + boundary = TX_PAGE_BOUNDARY_8188F; + else { + /* for WMM */ + boundary = WMM_NORMAL_TX_PAGE_BOUNDARY_8188F; + } + status = rtl8188f_InitLLTTable(padapter); + if (status == _FAIL) { + RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init LLT table\n")); + goto exit; + } + + HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01); + if (pHalData->bRDGEnable) + _InitRDGSetting_8188fu(padapter); + + + /*Enable TX Report */ + /*Enable Tx Report Timer */ + value8 = rtw_read8(padapter, REG_TX_RPT_CTRL); + rtw_write8(padapter, REG_TX_RPT_CTRL, value8 | BIT1); + /*Set MAX RPT MACID */ + rtw_write8(padapter, REG_TX_RPT_CTRL + 1, 2); + /*Tx RPT Timer. Unit: 32us */ + rtw_write16(padapter, REG_TX_RPT_TIME, 0xCdf0); + +#ifdef CONFIG_TX_EARLY_MODE + if (pHalData->AMPDUBurstMode) { + RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("EarlyMode Enabled!!!\n")); + + value8 = rtw_read8(padapter, REG_EARLY_MODE_CONTROL_8188F); +#if RTL8188F_EARLY_MODE_PKT_NUM_10 == 1 + value8 = value8 | 0x1f; +#else + value8 = value8 | 0xf; +#endif + rtw_write8(padapter, REG_EARLY_MODE_CONTROL_8188F, value8); + + rtw_write8(padapter, REG_EARLY_MODE_CONTROL_8188F + 3, 0x80); + + value8 = rtw_read8(padapter, REG_TCR_8188F + 1); + value8 = value8 | 0x40; + rtw_write8(padapter, REG_TCR_8188F + 1, value8); + } else + rtw_write8(padapter, REG_EARLY_MODE_CONTROL_8188F, 0); +#endif + + /* InitHalDm should be put ahead of FirmwareDownload. (HWConfig flow: FW->MAC->-BB->RF) */ + /*InitHalDm(Adapter); */ + + HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW); + if (padapter->registrypriv.mp_mode == 0 + #if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR) + || padapter->registrypriv.mp_customer_str + #endif + ) { + status = rtl8188f_FirmwareDownload(padapter, _FALSE); + if (status != _SUCCESS) { + padapter->bFWReady = _FALSE; + pHalData->fw_ractrl = _FALSE; + DBG_871X("fw download fail!\n"); + goto exit; + } else { + padapter->bFWReady = _TRUE; + pHalData->fw_ractrl = _TRUE; + DBG_871X("fw download ok!\n"); + } + } + + if (pwrctrlpriv->reg_rfoff == _TRUE) + pwrctrlpriv->rf_pwrstate = rf_off; + + /* Set RF type for BB/RF configuration */ + /*_InitRFType(Adapter); */ + + /* We should call the function before MAC/BB configuration. */ + PHY_InitAntennaSelection8188F(padapter); + + + + HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC); +#if (HAL_MAC_ENABLE == 1) + status = PHY_MACConfig8188F(padapter); + if (status == _FAIL) { + DBG_871X("PHY_MACConfig8188F fault !!\n"); + goto exit; + } +#endif + DBG_871X("PHY_MACConfig8188F OK!\n"); + + + HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB); + /* */ + /*d. Initialize BB related configurations. */ + /* */ +#if (HAL_BB_ENABLE == 1) + status = PHY_BBConfig8188F(padapter); + if (status == _FAIL) { + DBG_871X("PHY_BBConfig8188F fault !!\n"); + goto exit; + } +#endif + + DBG_871X("PHY_BBConfig8188F OK!\n"); + + + + HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF); +#if (HAL_RF_ENABLE == 1) + status = PHY_RFConfig8188F(padapter); + + if (status == _FAIL) { + DBG_871X("PHY_RFConfig8188F fault !!\n"); + goto exit; + } + + DBG_871X("PHY_RFConfig8188F OK!\n"); + + +#endif + + + + HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02); + _InitQueueReservedPage(padapter); + _InitTxBufferBoundary(padapter); + _InitQueuePriority(padapter); + _InitPageBoundary(padapter); + _InitTransferPageSize_8188fu(padapter); + + + /* Get Rx PHY status in order to report RSSI and others. */ + _InitDriverInfoSize(padapter, DRVINFO_SZ); + + _InitInterrupt(padapter); + hal_init_macaddr(padapter);/*set mac_address */ + _InitNetworkType(padapter);/*set msr */ + _InitWMACSetting(padapter); + _InitAdaptiveCtrl(padapter); + _InitEDCA(padapter); + _InitRateFallback(padapter); + _InitRetryFunction(padapter); +/* _InitOperationMode(Adapter);//todo */ + rtl8188f_InitBeaconParameters(padapter); + rtl8188f_InitBeaconMaxError(padapter, _TRUE); + + _InitBurstPktLen(padapter); + _initUsbAggregationSetting(padapter); + +#ifdef ENABLE_USB_DROP_INCORRECT_OUT + _InitHardwareDropIncorrectBulkOut(padapter); +#endif + +#if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_TX_MCAST2UNI) + +#ifdef CONFIG_CHECK_AC_LIFETIME + /* Enable lifetime check for the four ACs */ + rtw_write8(padapter, REG_LIFETIME_CTRL, 0x0F); +#endif /* CONFIG_CHECK_AC_LIFETIME */ + +#ifdef CONFIG_TX_MCAST2UNI + rtw_write16(padapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */ + rtw_write16(padapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */ +#else /* CONFIG_TX_MCAST2UNI */ + rtw_write16(padapter, REG_PKT_VO_VI_LIFE_TIME, 0x3000); /* unit: 256us. 3s */ + rtw_write16(padapter, REG_PKT_BE_BK_LIFE_TIME, 0x3000); /* unit: 256us. 3s */ +#endif /* CONFIG_TX_MCAST2UNI */ +#endif /* CONFIG_CONCURRENT_MODE || CONFIG_TX_MCAST2UNI */ + + +#ifdef CONFIG_LED + _InitHWLed(padapter); +#endif /*CONFIG_LED */ + + HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK); + _BBTurnOnBlock(padapter); + /*NicIFSetMacAddress(padapter, padapter->PermanentAddress); */ + + + rtw_hal_set_chnl_bw(padapter, padapter->registrypriv.channel, + CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HAL_PRIME_CHNL_OFFSET_DONT_CARE); + + HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY); + invalidate_cam_all(padapter); + + HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11); + /* 2010/12/17 MH We need to set TX power according to EFUSE content at first. */ + /*PHY_SetTxPowerLevel8188F(padapter, pHalData->CurrentChannel); */ + rtl8188f_InitAntenna_Selection(padapter); + + /* HW SEQ CTRL */ + /*set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */ + rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF); + + /* */ + /* Disable BAR, suggested by Scott */ + /* 2010.04.09 add by hpfan */ + /* */ + rtw_write32(padapter, REG_BAR_MODE_CTRL, 0x0201ffff); + + if (pregistrypriv->wifi_spec) + rtw_write16(padapter, REG_FAST_EDCA_CTRL , 0); + + /* Move by Neo for USB SS from above setp */ + +/* _RfPowerSave(Adapter); */ + + HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM); + rtl8188f_InitHalDm(padapter); + +#if (MP_DRIVER == 1) + if (padapter->registrypriv.mp_mode == 1) { + padapter->mppriv.channel = pHalData->CurrentChannel; + MPT_InitializeAdapter(padapter, padapter->mppriv.channel); + } else +#endif + { + pwrctrlpriv->rf_pwrstate = rf_on; + + if (pwrctrlpriv->rf_pwrstate == rf_on) { + struct pwrctrl_priv *pwrpriv; + u32 start_time; + u8 restore_iqk_rst; + u8 h2cCmdBuf; + + pwrpriv = adapter_to_pwrctl(padapter); + + PHY_LCCalibrate_8188F(&pHalData->odmpriv); + +#ifdef CONFIG_BT_COEXIST + /* Inform WiFi FW that it is the beginning of IQK */ + h2cCmdBuf = 1; + FillH2CCmd8188F(padapter, H2C_8188F_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf); + + start_time = rtw_get_current_time(); + do { + if (rtw_read8(padapter, 0x1e7) & 0x01) + break; + + rtw_msleep_os(50); + } while (rtw_get_passing_time_ms(start_time) <= 400); + + + rtw_btcoex_IQKNotify(padapter, _TRUE); +#endif + + restore_iqk_rst = (pwrpriv->bips_processing == _TRUE) ? _TRUE : _FALSE; + PHY_IQCalibrate_8188F(padapter, _FALSE, restore_iqk_rst); + pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = _TRUE; + +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_IQKNotify(padapter, _FALSE); + + /* Inform WiFi FW that it is the finish of IQK */ + h2cCmdBuf = 0; + FillH2CCmd8188F(padapter, H2C_8188F_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf); +#endif + + ODM_TXPowerTrackingCheck(&pHalData->odmpriv); + } + } + + + HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC21); + +/*HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS); */ +/* _InitPABias(Adapter); */ + + HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BT_COEXIST); +#ifdef CONFIG_BT_COEXIST + /* Init BT hw config. */ + rtw_btcoex_HAL_Initialize(padapter, _FALSE); +#else + /* rtw_btcoex_HAL_Initialize(padapter, _TRUE); // For Test. */ +#endif + +#if 0 + /* 2010/05/20 MH We need to init timer after update setting. Otherwise, we can not get correct inf setting. */ + /* 2010/05/18 MH For SE series only now. Init GPIO detect time */ + if (pDevice->RegUsbSS) { + RT_TRACE(COMP_INIT, DBG_LOUD, (" call GpioDetectTimerStart8192CU\n")); + GpioDetectTimerStart8192CU(Adapter); /* Disable temporarily */ + } + + /* 2010/08/23 MH According to Alfred's suggestion, we need to to prevent HW enter */ + /* suspend mode automatically. */ + HwSuspendModeEnable92Cu(Adapter, _FALSE); +#endif + + HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC31); + rtw_hal_set_hwreg(padapter, HW_VAR_NAV_UPPER, (u8 *)&NavUpper); + +#ifdef CONFIG_XMIT_ACK + /*ack for xmit mgmt frames. */ + rtw_write32(padapter, REG_FWHW_TXQ_CTRL, rtw_read32(padapter, REG_FWHW_TXQ_CTRL) | BIT(12)); +#endif /*CONFIG_XMIT_ACK */ + + /* Enable MACTXEN/MACRXEN block */ + u1bRegCR = rtw_read8(padapter, REG_CR); + u1bRegCR |= (MACTXEN | MACRXEN); + rtw_write8(padapter, REG_CR, u1bRegCR); + +/* #if RTL8188F_USB_MAC_LOOPBACK */ +#if 0 + rtw_write8(padapter, REG_CR_8188F + 3, 0x0B); + DBG_871X("MAC loopback: REG_CR_8188F=%#X.\n", rtw_read32(padapter, REG_CR_8188F)); +#endif + +#if FPGA_TWO_MAC_VERIFICATION +/* #if 1 */ + /* Enable BB */ + value8 = rtw_read8(padapter, REG_SYS_FUNC_EN_8188F); + DBG_871X("RJZ: open 2-MAC mode: REG_SYS_FUNC_EN_8188F = %#x.\n", value8); + rtw_write8(padapter, REG_SYS_FUNC_EN_8188F, value8 | BIT0 | BIT1 | BIT2); + value8 = rtw_read8(padapter, REG_SYS_FUNC_EN_8188F); + DBG_871X("RJZ: open 2-MAC mode: REG_SYS_FUNC_EN_8188F = %#x.\n", value8); + + /* Use 40MHz */ + value8 = rtw_read8(padapter, REG_SYS_CLKR_8188F); + rtw_write8(padapter, REG_SYS_CLKR_8188F, value8 & ~BIT4); + value8 = rtw_read8(padapter, REG_SYS_CLKR_8188F); + + /* Clear 970~976. */ + rtw_write32(padapter, 0x0970, 0); + rtw_write16(padapter, 0x0974, 0); + rtw_write8(padapter, 0x0976, 0); + + /* Set the microsecond time unit used by MAC TSF clock. */ + rtw_write8(padapter, REG_USTIME_TSF_8188F, 0x28); +#endif + + /*_dbg_dump_macreg(Adapter); */ + +exit: + HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END); + + DBG_871X("%s in %dms\n", __func__, rtw_get_passing_time_ms(init_start_time)); + +#ifdef DBG_HAL_INIT_PROFILING + hal_init_stages_timestamp[HAL_INIT_STAGES_END] = rtw_get_current_time(); + + for (hal_init_profiling_i = 0; hal_init_profiling_i < HAL_INIT_STAGES_NUM - 1; hal_init_profiling_i++) { + DBG_871X("DBG_HAL_INIT_PROFILING: %35s, %u, %5u, %5u\n" + , hal_init_stages_str[hal_init_profiling_i] + , hal_init_stages_timestamp[hal_init_profiling_i] + , (hal_init_stages_timestamp[hal_init_profiling_i + 1] - hal_init_stages_timestamp[hal_init_profiling_i]) + , rtw_get_time_interval_ms(hal_init_stages_timestamp[hal_init_profiling_i], hal_init_stages_timestamp[hal_init_profiling_i + 1]) + ); + } +#endif + + _func_exit_; + + return status; +} + + +static VOID +_DisableGPIO( + IN PADAPTER Adapter +) +{ + /* + * j. GPIO_PIN_CTRL 0x44[31:0]=0x000 + * k. Value = GPIO_PIN_CTRL[7:0] + * l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write external PIN level + * m. GPIO_MUXCFG 0x42 [15:0] = 0x0780 + * n. LEDCFG 0x4C[15:0] = 0x8080 + */ + u8 value8; + u16 value16; + u32 value32; + + /*1. Disable GPIO[7:0] */ + rtw_write16(Adapter, REG_GPIO_PIN_CTRL + 2, 0x0000); + value32 = rtw_read32(Adapter, REG_GPIO_PIN_CTRL) & 0xFFFF00FF; + value8 = (u8)(value32 & 0x000000FF); + value32 |= ((value8 << 8) | 0x00FF0000); + rtw_write32(Adapter, REG_GPIO_PIN_CTRL, value32); + + /*2. Disable GPIO[10:8] */ + rtw_write8(Adapter, REG_GPIO_MUXCFG + 3, 0x00); + value16 = rtw_read16(Adapter, REG_GPIO_MUXCFG + 2) & 0xFF0F; + value8 = (u8)(value16 & 0x000F); + value16 |= ((value8 << 4) | 0x0780); + rtw_write16(Adapter, REG_GPIO_MUXCFG + 2, value16); + + /*3. Disable LED0 & 1 */ + rtw_write16(Adapter, REG_LEDCFG0, 0x8080); + + /*RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Disable GPIO and LED.\n")); */ + +} /*end of _DisableGPIO() */ + +static VOID +_ResetFWDownloadRegister( + IN PADAPTER Adapter +) +{ + u32 value32; + + value32 = rtw_read32(Adapter, REG_MCUFWDL); + value32 &= ~(MCUFWDL_EN | MCUFWDL_RDY); + rtw_write32(Adapter, REG_MCUFWDL, value32); + /*RT_TRACE(COMP_INIT, DBG_LOUD, ("Reset FW download register.\n")); */ +} + +static VOID +_ResetBB( + IN PADAPTER Adapter +) +{ + u16 value16; + + /*reset BB */ + value16 = rtw_read16(Adapter, REG_SYS_FUNC_EN); + value16 &= ~(FEN_BBRSTB | FEN_BB_GLB_RSTn); + rtw_write16(Adapter, REG_SYS_FUNC_EN, value16); + /*RT_TRACE(COMP_INIT, DBG_LOUD, ("Reset BB.\n")); */ +} + +static VOID +_ResetMCU( + IN PADAPTER Adapter +) +{ + u16 value16; + + /* reset MCU */ + value16 = rtw_read16(Adapter, REG_SYS_FUNC_EN); + value16 &= ~FEN_CPUEN; + rtw_write16(Adapter, REG_SYS_FUNC_EN, value16); + /*RT_TRACE(COMP_INIT, DBG_LOUD, ("Reset MCU.\n")); */ +} + +static VOID +_DisableMAC_AFE_PLL( + IN PADAPTER Adapter +) +{ + u32 value32; + + /*disable MAC/ AFE PLL */ + value32 = rtw_read32(Adapter, REG_APS_FSMCO); + value32 |= APDM_MAC; + rtw_write32(Adapter, REG_APS_FSMCO, value32); + + value32 |= APFM_OFF; + rtw_write32(Adapter, REG_APS_FSMCO, value32); + /*RT_TRACE(COMP_INIT, DBG_LOUD, ("Disable MAC, AFE PLL.\n")); */ +} + +static VOID +_AutoPowerDownToHostOff( + IN PADAPTER Adapter +) +{ + u32 value32; + rtw_write8(Adapter, REG_SPS0_CTRL, 0x22); + + value32 = rtw_read32(Adapter, REG_APS_FSMCO); + + value32 |= APDM_HOST;/*card disable */ + rtw_write32(Adapter, REG_APS_FSMCO, value32); + /*RT_TRACE(COMP_INIT, DBG_LOUD, ("Auto Power Down to Host-off state.\n")); */ + + /* set USB suspend */ + value32 = rtw_read32(Adapter, REG_APS_FSMCO); + value32 &= ~AFSM_PCIE; + rtw_write32(Adapter, REG_APS_FSMCO, value32); + +} + +static VOID +_SetUsbSuspend( + IN PADAPTER Adapter +) +{ + u32 value32; + + value32 = rtw_read32(Adapter, REG_APS_FSMCO); + + /* set USB suspend */ + value32 |= AFSM_HSUS; + rtw_write32(Adapter, REG_APS_FSMCO, value32); + + /*RT_ASSERT(0 == (rtw_read32(Adapter, REG_APS_FSMCO) & BIT(12)),("")); */ + /*RT_TRACE(COMP_INIT, DBG_LOUD, ("Set USB suspend.\n")); */ + +} + +static VOID +_DisableRFAFEAndResetBB( + IN PADAPTER Adapter +) +{ + /* + * a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue + * b. RF path 0 offset 0x00 = 0x00 disable RF + * c. APSD_CTRL 0x600[7:0] = 0x40 + * d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine + * e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine + */ + u8 eRFPath = 0, value8 = 0; + rtw_write8(Adapter, REG_TXPAUSE, 0xFF); + PHY_SetRFReg(Adapter, eRFPath, 0x0, bMaskByte0, 0x0); + + value8 |= APSDOFF; + rtw_write8(Adapter, REG_APSD_CTRL, value8);/*0x40 */ + + value8 = 0; + value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn); + rtw_write8(Adapter, REG_SYS_FUNC_EN, value8);/*0x16 */ + + value8 &= (~FEN_BB_GLB_RSTn); + rtw_write8(Adapter, REG_SYS_FUNC_EN, value8); /*0x14 */ + + /*RT_TRACE(COMP_INIT, DBG_LOUD, ("======> RF off and reset BB.\n")); */ +} + +static VOID +_ResetDigitalProcedure1( + IN PADAPTER Adapter, + IN BOOLEAN bWithoutHWSM +) +{ + + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + if (pHalData->FirmwareVersion <= 0x20) { +#if 0 + /* + * f. SYS_FUNC_EN 0x03[7:0]=0x54 reset MAC register, DCORE + * g. MCUFWDL 0x80[7:0]=0 reset MCU ready status + */ + u4Byte value32 = 0; + PlatformIOWrite1Byte(Adapter, REG_SYS_FUNC_EN + 1, 0x54); + PlatformIOWrite1Byte(Adapter, REG_MCUFWDL, 0); +#else + /* + * i. MCUFWDL 0x80[7:0]=0 reset MCU ready status + * g. SYS_FUNC_EN 0x02[10]= 0 reset MCU register, (8051 reset) + * h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC register, DCORE + * i. SYS_FUNC_EN 0x02[10]= 1 enable MCU register, (8051 enable) + */ + u16 valu16 = 0; + + rtw_write8(Adapter, REG_MCUFWDL, 0); + + valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN); + rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 & (~FEN_CPUEN)));/*reset MCU ,8051 */ + + valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN) & 0x0FFF; + rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 | (FEN_HWPDN | FEN_ELDR))); /*reset MAC */ + +#ifdef DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE + { + u8 val; + + val = rtw_read8(Adapter, REG_MCUFWDL) + + if (val) { + DBG_871X("DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE %s:%d REG_MCUFWDL:0x%02x\n", + __func__, __LINE__, val); + } + } +#endif + + + valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN); + rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 | FEN_CPUEN));/*enable MCU ,8051 */ + + +#endif + } else { + u8 retry_cnts = 0; + + if (rtw_read8(Adapter, REG_MCUFWDL) & BIT1) { + /*IF fw in RAM code, do reset */ + + rtw_write8(Adapter, REG_MCUFWDL, 0); + if (Adapter->bFWReady) { + /* 2010/08/25 MH According to RD alfred's suggestion, we need to disable other */ + /* HRCV INT to influence 8051 reset. */ + rtw_write8(Adapter, REG_FWIMR, 0x20); + + rtw_write8(Adapter, REG_HMETFR + 3, 0x20); /*8051 reset by self */ + + while ((retry_cnts++ < 100) && (FEN_CPUEN & rtw_read16(Adapter, REG_SYS_FUNC_EN))) { + /*PlatformStallExecution(50); //us */ + rtw_udelay_os(50); + } + + if (retry_cnts >= 100) { + DBG_8192C("%s #####=> 8051 reset failed!.........................\n", __func__); + /* if 8051 reset fail we trigger GPIO 0 for LA */ + /*PlatformEFIOWrite4Byte( Adapter, */ + /* REG_GPIO_PIN_CTRL, */ + /* 0x00010100); */ + /* 2010/08/31 MH According to Filen's info, if 8051 reset fail, reset MAC directly. */ + rtw_write8(Adapter, REG_SYS_FUNC_EN + 1, 0x50); /*Reset MAC and Enable 8051 */ + rtw_mdelay_os(10); + } else { + /*DBG_871X("%s =====> 8051 reset success (%d) .\n", __func__, retry_cnts); */ + } + } else + DBG_871X("%s =====> 8051 in RAM but !Adapter->bFWReady\n", __func__); + } else { + /*DBG_871X("%s =====> 8051 in ROM.\n", __func__); */ + } + +#ifdef DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE + { + u8 val; + val = rtw_read8(Adapter, REG_MCUFWDL) + + if (val) { + DBG_871X("DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE %s:%d REG_MCUFWDL:0x%02x\n", + __func__, __LINE__, val); + } + } +#endif + + rtw_write8(Adapter, REG_SYS_FUNC_EN + 1, 0x54); /*Reset MAC and Enable 8051 */ + } + + /* Clear rpwm value for initial toggle bit trigger. */ + rtw_write8(Adapter, REG_USB_HRPWM, 0x00); + + if (bWithoutHWSM) { + /* + * Without HW auto state machine + * g. SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock + * h. AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL + * i. AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK + * j. SYS_ISO_CTRL 0x00[7:0] = 0xF9 isolated digital to PON + */ + /*rtw_write16(Adapter, REG_SYS_CLKR, 0x30A3); */ + rtw_write16(Adapter, REG_SYS_CLKR, 0x70A3);/*modify to 0x70A3 by Scott. */ + rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x80); + rtw_write16(Adapter, REG_AFE_XTAL_CTRL, 0x880F); + rtw_write8(Adapter, REG_SYS_ISO_CTRL, 0xF9); + } else { + /* Disable all RF/BB power */ + rtw_write8(Adapter, REG_RF_CTRL, 0x00); + } + /*RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Reset Digital.\n")); */ + +} + +static VOID +_ResetDigitalProcedure2( + IN PADAPTER Adapter +) +{ + /* + * k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction + * l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock + * m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON + */ + /*rtw_write8(Adapter, REG_SYS_FUNC_EN+1, 0x44);//marked by Scott. */ + /*rtw_write16(Adapter, REG_SYS_CLKR, 0x3083); */ + /*rtw_write8(Adapter, REG_SYS_ISO_CTRL+1, 0x83); */ + + rtw_write16(Adapter, REG_SYS_CLKR, 0x70a3); /*modify to 0x70a3 by Scott. */ + rtw_write8(Adapter, REG_SYS_ISO_CTRL + 1, 0x82); /*modify to 0x82 by Scott. */ +} + +static VOID +_DisableAnalog( + IN PADAPTER Adapter, + IN BOOLEAN bWithoutHWSM +) +{ + u16 value16 = 0; + u8 value8 = 0; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + + if (bWithoutHWSM) { + /* + * n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power + * o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power + * r. When driver call disable, the ASIC will turn off remaining clock automatically + */ + + rtw_write8(Adapter, REG_LDOA15_CTRL, 0x04); + /*PlatformIOWrite1Byte(Adapter, REG_LDOV12D_CTRL, 0x54); */ + + value8 = rtw_read8(Adapter, REG_LDOV12D_CTRL); + value8 &= (~LDV12_EN); + rtw_write8(Adapter, REG_LDOV12D_CTRL, value8); + /*RT_TRACE(COMP_INIT, DBG_LOUD, (" REG_LDOV12D_CTRL Reg0x21:0x%02x.\n",value8)); */ + } + + /* + * h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode + * i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend + */ + + + value8 = 0x23; + + rtw_write8(Adapter, REG_SPS0_CTRL, value8); + + + if (bWithoutHWSM) { + /* 2010/08/31 According to Filen description, we need to use HW to shut down 8051 automatically. */ + /* Because suspend operation need the asistance of 8051 to wait for 3ms. */ + value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN); + } else + value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN); + + rtw_write16(Adapter, REG_APS_FSMCO, value16);/*0x4802 */ + + rtw_write8(Adapter, REG_RSV_CTRL, 0x0e); + +#if 0 + /*tynli_test for suspend mode. */ + if (!bWithoutHWSM) + rtw_write8(Adapter, 0xfe10, 0x19); +#endif + + /*RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Disable Analog Reg0x04:0x%04x.\n",value16)); */ +} + +static void rtl8188fu_hw_power_down(_adapter *padapter) +{ + u8 u1bTmp; + + DBG_8192C("PowerDownRTL8188FU\n"); + + + /* 1. Run Card Disable Flow */ + /* Done before this function call. */ + + /* 2. 0x04[16] = 0 // reset WLON */ + u1bTmp = rtw_read8(padapter, REG_APS_FSMCO + 2); + rtw_write8(padapter, REG_APS_FSMCO + 2, (u1bTmp & (~BIT0))); + + /* 3. 0x04[12:11] = 2b'11 // enable suspend */ + /* Done before this function call. */ + + /* 4. 0x04[15] = 1 // enable PDN */ + u1bTmp = rtw_read8(padapter, REG_APS_FSMCO + 1); + rtw_write8(padapter, REG_APS_FSMCO + 1, (u1bTmp | BIT7)); +} + +/* */ +/* Description: RTL8188F card disable power sequence v003 which suggested by Scott. */ +/* First created by tynli. 2011.01.28. */ +/* */ +VOID +CardDisableRTL8188FU( + PADAPTER Adapter +) +{ + u8 u1bTmp; +/* PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); */ + + DBG_8192C("CardDisableRTL8188FU\n"); + + /*Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */ + u1bTmp = rtw_read8(Adapter, REG_TX_RPT_CTRL); + rtw_write8(Adapter, REG_TX_RPT_CTRL, u1bTmp & (~BIT1)); + + /* stop rx */ + rtw_write8(Adapter, REG_CR_8188F, 0x0); + if ((rtw_read8(Adapter, REG_MCUFWDL_8188F)&BIT7) && + Adapter->bFWReady) /*8051 RAM code */ + rtl8188f_FirmwareSelfReset(Adapter); + + /* 1. Run LPS WL RFOFF flow */ + HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, rtl8188F_enter_lps_flow); + + /* Reset MCU. Suggested by Filen. 2011.01.26. by tynli. */ + u1bTmp = rtw_read8(Adapter, REG_SYS_FUNC_EN_8188F + 1); + rtw_write8(Adapter, REG_SYS_FUNC_EN_8188F + 1, (u1bTmp & (~BIT2))); + + /* MCUFWDL 0x80[1:0]=0 // reset MCU ready status */ + rtw_write8(Adapter, REG_MCUFWDL_8188F, 0x00); + + /* Card disable power action flow */ + HalPwrSeqCmdParsing(Adapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, rtl8188F_card_disable_flow); + + Adapter->bFWReady = _FALSE; +} + +u32 rtl8188fu_hal_deinit(PADAPTER Adapter) +{ + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(Adapter); + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + + DBG_871X("==> %s\n", __func__); + + rtw_write16(Adapter, REG_GPIO_MUXCFG, rtw_read16(Adapter, REG_GPIO_MUXCFG) & (~BIT12)); + + rtw_write32(Adapter, REG_HISR0_8188F, 0xFFFFFFFF); + rtw_write32(Adapter, REG_HISR1_8188F, 0xFFFFFFFF); + +#if 0 + /* USB only need to clear HISR, no need to set HIMR, because there's no hardware interrupt for USB. */ + rtw_write32(Adapter, REG_HIMR0_8188F, IMR_DISABLED_8188F); + rtw_write32(Adapter, REG_HIMR1_8188F, IMR_DISABLED_8188F); +#endif + +#ifdef CONFIG_MP_INCLUDED + if (Adapter->registrypriv.mp_mode == 1) + MPT_DeInitAdapter(Adapter); +#endif + +#ifdef SUPPORT_HW_RFOFF_DETECTED + DBG_871X("%s: bkeepfwalive(%x)\n", __func__, pwrctl->bkeepfwalive); + + if (pwrctl->bkeepfwalive) { + _ps_close_RF(Adapter); + if ((pwrctl->bHWPwrPindetect) && (pwrctl->bHWPowerdown)) + rtl8188fu_hw_power_down(Adapter); + } else +#endif + { + if (rtw_is_hw_init_completed(Adapter)) { + rtw_hal_power_off(Adapter); + + if ((pwrctl->bHWPwrPindetect) && (pwrctl->bHWPowerdown)) + rtl8188fu_hw_power_down(Adapter); + } + pHalData->bMacPwrCtrlOn = _FALSE; + } + return _SUCCESS; +} + +unsigned int rtl8188fu_inirp_init(PADAPTER Adapter) +{ + u8 i; + struct recv_buf *precvbuf; + uint status; + struct dvobj_priv *pdev = adapter_to_dvobj(Adapter); + struct intf_hdl *pintfhdl = &Adapter->iopriv.intf; + struct recv_priv *precvpriv = &(Adapter->recvpriv); + + u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); +#ifdef CONFIG_USB_INTERRUPT_IN_PIPE + u32 (*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); +#endif /*CONFIG_USB_INTERRUPT_IN_PIPE */ + + _func_enter_; + + _read_port = pintfhdl->io_ops._read_port; + + status = _SUCCESS; + + RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("===> usb_inirp_init\n")); + + precvpriv->ff_hwaddr = RECV_BULK_IN_ADDR; + + /*issue Rx irp to receive data */ + precvbuf = (struct recv_buf *)precvpriv->precv_buf; + for (i = 0; i < NR_RECVBUFF; i++) { + if (_read_port(pintfhdl, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf) == _FALSE) { + RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("usb_rx_init: usb_read_port error\n")); + status = _FAIL; + goto exit; + } + + precvbuf++; + precvpriv->free_recv_buf_queue_cnt--; + } + +#ifdef CONFIG_USB_INTERRUPT_IN_PIPE + _read_interrupt = pintfhdl->io_ops._read_interrupt; + if (_read_interrupt(pintfhdl, RECV_INT_IN_ADDR) == _FALSE) { + RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("usb_rx_init: usb_read_interrupt error\n")); + status = _FAIL; + } + pHalData->IntrMask[0] = rtw_read32(Adapter, REG_USB_HIMR); + MSG_8192C("pHalData->IntrMask = 0x%04x\n", pHalData->IntrMask[0]); + pHalData->IntrMask[0] |= UHIMR_C2HCMD | UHIMR_CPWM; + rtw_write32(Adapter, REG_USB_HIMR, pHalData->IntrMask[0]); +#endif /*CONFIG_USB_INTERRUPT_IN_PIPE */ + +exit: + + RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("<=== usb_inirp_init\n")); + + _func_exit_; + + return status; + +} + +unsigned int rtl8188fu_inirp_deinit(PADAPTER Adapter) +{ +#ifdef CONFIG_USB_INTERRUPT_IN_PIPE + u32 (*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); +#endif /*CONFIG_USB_INTERRUPT_IN_PIPE */ + RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("\n ===> usb_rx_deinit\n")); + + rtw_read_port_cancel(Adapter); +#ifdef CONFIG_USB_INTERRUPT_IN_PIPE + pHalData->IntrMask[0] = rtw_read32(Adapter, REG_USB_HIMR); + MSG_8192C("%s pHalData->IntrMask = 0x%04x\n", __func__, pHalData->IntrMask[0]); + pHalData->IntrMask[0] = 0x0; + rtw_write32(Adapter, REG_USB_HIMR, pHalData->IntrMask[0]); + RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("\n <=== usb_rx_deinit\n")); +#endif /*CONFIG_USB_INTERRUPT_IN_PIPE */ + return _SUCCESS; +} + + +static u32 +_GetChannelGroup( + IN u32 channel +) +{ + /*RT_ASSERT((channel < 14), ("Channel %d no is supported!\n")); */ + + if (channel < 3) /* Channel 1~3 */ + return 0; + else if (channel < 9) /* Channel 4~9 */ + return 1; + + return 2; /* Channel 10~14 */ +} + + +/*------------------------------------------------------------------- */ +/* */ +/* EEPROM/EFUSE Content Parsing */ +/* */ +/*------------------------------------------------------------------- */ +static VOID +_ReadLEDSetting( + IN PADAPTER Adapter, + IN u8 *PROMContent, + IN BOOLEAN AutoloadFail +) +{ + struct led_priv *pledpriv = &(Adapter->ledpriv); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + +#ifdef CONFIG_SW_LED + pledpriv->bRegUseLed = _TRUE; + + /* */ + /* Led mode */ + /* */ + switch (pHalData->CustomerID) { + case RT_CID_DEFAULT: + pledpriv->LedStrategy = SW_LED_MODE1; + pledpriv->bRegUseLed = _TRUE; + break; + + case RT_CID_819x_HP: + pledpriv->LedStrategy = SW_LED_MODE6; + break; + + default: + pledpriv->LedStrategy = SW_LED_MODE1; + break; + } + +/* if( BOARD_MINICARD == pHalData->BoardType ) */ +/* { */ +/* pledpriv->LedStrategy = SW_LED_MODE6; */ +/* } */ + pHalData->bLedOpenDrain = _TRUE;/* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */ +#else /* HW LED */ + pledpriv->LedStrategy = HW_LED; +#endif /*CONFIG_SW_LED */ +} + +static VOID +_ReadThermalMeter( + IN PADAPTER Adapter, + IN u8 *PROMContent, + IN BOOLEAN AutoloadFail +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u8 tempval; + + /* */ + /* ThermalMeter from EEPROM */ + /* */ + if (!AutoloadFail) + tempval = PROMContent[EEPROM_THERMAL_METER_8188F]; + else + tempval = EEPROM_Default_ThermalMeter; + + pHalData->EEPROMThermalMeter = (tempval & 0x1f); /*[4:0] */ + + if (pHalData->EEPROMThermalMeter == 0x1f || AutoloadFail) + pHalData->odmpriv.RFCalibrateInfo.bAPKThermalMeterIgnore = _TRUE; + +#if 0 + if (pHalData->EEPROMThermalMeter < 0x06 || pHalData->EEPROMThermalMeter > 0x1c) + pHalData->EEPROMThermalMeter = 0x12; +#endif + + /*pHalData->ThermalMeter[0] = pHalData->EEPROMThermalMeter; */ + + + /*RTPRINT(FINIT, INIT_TxPower, ("ThermalMeter = 0x%x\n", pHalData->EEPROMThermalMeter)); */ + +} + +VOID +Hal_EfuseParsePIDVID_8188FU( + IN PADAPTER pAdapter, + IN u8 *hwinfo, + IN BOOLEAN AutoLoadFail +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); + + if (AutoLoadFail) { + pHalData->EEPROMVID = 0; + pHalData->EEPROMPID = 0; + } else { + /* VID, PID */ + pHalData->EEPROMVID = le16_to_cpu(*(u16 *)&hwinfo[EEPROM_VID_8188FU]); + pHalData->EEPROMPID = le16_to_cpu(*(u16 *)&hwinfo[EEPROM_PID_8188FU]); + + } + + MSG_8192C("EEPROM VID = 0x%4x\n", pHalData->EEPROMVID); + MSG_8192C("EEPROM PID = 0x%4x\n", pHalData->EEPROMPID); +} + +static VOID +InitAdapterVariablesByPROM_8188FU( + IN PADAPTER padapter +) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + u8 *hwinfo = NULL; + + if (sizeof(pHalData->efuse_eeprom_data) < HWSET_MAX_SIZE_8188F) + DBG_871X("[WARNING] size of efuse_eeprom_data is less than HWSET_MAX_SIZE_8188F!\n"); + + hwinfo = pHalData->efuse_eeprom_data; + + Hal_InitPGData(padapter, hwinfo); + + Hal_EfuseParseIDCode(padapter, hwinfo); + Hal_EfuseParsePIDVID_8188FU(padapter, hwinfo, pHalData->bautoload_fail_flag); + Hal_EfuseParseEEPROMVer_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag); + hal_config_macaddr(padapter, pHalData->bautoload_fail_flag); + Hal_EfuseParseTxPowerInfo_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag); +/* Hal_EfuseParseBTCoexistInfo_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag); */ + + Hal_EfuseParseChnlPlan_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag); + Hal_EfuseParseThermalMeter_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag); +/* _ReadLEDSetting(Adapter, PROMContent, pHalData->bautoload_fail_flag); */ + Hal_EfuseParsePowerSavingMode_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag); + Hal_EfuseParseAntennaDiversity_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag); + + Hal_EfuseParseEEPROMVer_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag); + Hal_EfuseParseCustomerID_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag); +/* Hal_EfuseParseRateIndicationOption(padapter, hwinfo, pHalData->bautoload_fail_flag); */ + Hal_EfuseParseXtal_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag); + /* */ + /* The following part initialize some vars by PG info. */ + /* */ +/* Hal_InitChannelPlan(padapter); */ + + + + /*hal_CustomizedBehavior_8188FU(Adapter); */ + + Hal_EfuseParseKFreeData_8188F(padapter, hwinfo, pHalData->bautoload_fail_flag); + hal_read_mac_hidden_rpt(padapter); + +/* Adapter->bDongle = (PROMContent[EEPROM_EASY_REPLACEMENT] == 1)? 0: 1; */ + DBG_8192C("%s(): REPLACEMENT = %x\n", __func__, padapter->bDongle); +} + +static void _ReadPROMContent( + IN PADAPTER Adapter +) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + u8 eeValue; + + /* To check system boot selection. */ + eeValue = rtw_read8(Adapter, REG_SYS_EEPROM_CTRL); + pHalData->EepromOrEfuse = (eeValue & EEPROMSEL) ? _TRUE : _FALSE; + pHalData->bautoload_fail_flag = (eeValue & EEPROM_EN) ? _FALSE : _TRUE; + + DBG_8192C("Boot from %s, Autoload %s !\n", (pHalData->EepromOrEfuse ? "EEPROM" : "EFUSE"), + (pHalData->bautoload_fail_flag ? "Fail" : "OK")); + +#ifdef CONFIG_8188FTV_SOLUTION_D + rtl8188fu_solution_d(Adapter); +#endif + + InitAdapterVariablesByPROM_8188FU(Adapter); +} + +static VOID +_ReadRFType( + IN PADAPTER Adapter +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + +#if DISABLE_BB_RF + pHalData->rf_chip = RF_PSEUDO_11N; +#else + pHalData->rf_chip = RF_6052; +#endif +} + + + +/* */ +/* Description: */ +/* We should set Efuse cell selection to WiFi cell in default. */ +/* */ +/* Assumption: */ +/* PASSIVE_LEVEL */ +/* */ +/* Added by Roger, 2010.11.23. */ +/* */ +void +hal_EfuseCellSel( + IN PADAPTER Adapter +) +{ + u32 value32; + + value32 = rtw_read32(Adapter, EFUSE_TEST); + value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); + rtw_write32(Adapter, EFUSE_TEST, value32); +} + +static void ReadAdapterInfo8188FU(PADAPTER Adapter) +{ + /* Read EEPROM size before call any EEPROM function */ + Adapter->EepromAddressSize = GetEEPROMSize8188F(Adapter); + + /*Efuse_InitSomeVar(Adapter); */ + + hal_EfuseCellSel(Adapter); + + _ReadRFType(Adapter);/*rf_chip -> _InitRFType() */ + _ReadPROMContent(Adapter); +} + +#define GPIO_DEBUG_PORT_NUM 0 +static void rtl8188fu_trigger_gpio_0(_adapter *padapter) +{ + + u32 gpioctrl; + DBG_871X("==> trigger_gpio_0...\n"); + rtw_write16_async(padapter, REG_GPIO_PIN_CTRL, 0); + rtw_write8_async(padapter, REG_GPIO_PIN_CTRL + 2, 0xFF); + gpioctrl = (BIT(GPIO_DEBUG_PORT_NUM) << 24) | (BIT(GPIO_DEBUG_PORT_NUM) << 16); + rtw_write32_async(padapter, REG_GPIO_PIN_CTRL, gpioctrl); + gpioctrl |= (BIT(GPIO_DEBUG_PORT_NUM) << 8); + rtw_write32_async(padapter, REG_GPIO_PIN_CTRL, gpioctrl); + DBG_871X("<=== trigger_gpio_0...\n"); + +} + +/* + * If variable not handled here, + * some variables will be processed in SetHwReg8188FU() + */ +void SetHwReg8188FU(PADAPTER Adapter, u8 variable, u8 *val) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + + _func_enter_; + + switch (variable) { + case HW_VAR_RXDMA_AGG_PG_TH: +#ifdef CONFIG_USB_RX_AGGREGATION + { + u8 threshold = *val; + + if (threshold == 0) + threshold = pHalData->UsbRxAggPageCount; + SetHwReg8188F(Adapter, HW_VAR_RXDMA_AGG_PG_TH, &threshold); + } +#endif + break; + + case HW_VAR_SET_RPWM: + rtw_write8(Adapter, REG_USB_HRPWM, *val); + break; + + case HW_VAR_TRIGGER_GPIO_0: + rtl8188fu_trigger_gpio_0(Adapter); + break; + + default: + SetHwReg8188F(Adapter, variable, val); + break; + } + + _func_exit_; +} + +/* + * If variable not handled here, + * some variables will be processed in GetHwReg8188FU() + */ +void GetHwReg8188FU(PADAPTER Adapter, u8 variable, u8 *val) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); + + _func_enter_; + + switch (variable) { + default: + GetHwReg8188F(Adapter, variable, val); + break; + } + + _func_exit_; +} + +/* */ +/* Description: */ +/* Query setting of specified variable. */ +/* */ +u8 +GetHalDefVar8188FUsb( + IN PADAPTER Adapter, + IN HAL_DEF_VARIABLE eVariable, + IN PVOID pValue +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u8 bResult = _SUCCESS; + + switch (eVariable) { + case HAL_DEF_IS_SUPPORT_ANT_DIV: +#ifdef CONFIG_ANTENNA_DIVERSITY + *((u8 *)pValue) = (pHalData->AntDivCfg == 0) ? _FALSE : _TRUE; +#endif + break; + + case HAL_DEF_DRVINFO_SZ: + *((u32 *)pValue) = DRVINFO_SZ; + break; + case HAL_DEF_MAX_RECVBUF_SZ: + *((u32 *)pValue) = MAX_RECVBUF_SZ; + break; + case HAL_DEF_RX_PACKET_OFFSET: + *((u32 *)pValue) = RXDESC_SIZE + DRVINFO_SZ*8; + break; + case HW_VAR_MAX_RX_AMPDU_FACTOR: + *((HT_CAP_AMPDU_FACTOR *)pValue) = MAX_AMPDU_FACTOR_64K; + break; + default: + bResult = GetHalDefVar8188F(Adapter, eVariable, pValue); + break; + } + + return bResult; +} + + + + +/* */ +/* Description: */ +/* Change default setting of specified variable. */ +/* */ +u8 +SetHalDefVar8188FUsb( + IN PADAPTER Adapter, + IN HAL_DEF_VARIABLE eVariable, + IN PVOID pValue +) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); + u8 bResult = _SUCCESS; + + switch (eVariable) { + default: + bResult = SetHalDefVar8188F(Adapter, eVariable, pValue); + break; + } + + return bResult; +} + +void _update_response_rate(_adapter *padapter, unsigned int mask) +{ + u8 RateIndex = 0; + /* Set RRSR rate table. */ + rtw_write8(padapter, REG_RRSR, mask & 0xff); + rtw_write8(padapter, REG_RRSR + 1, (mask >> 8) & 0xff); + + /* Set RTS initial rate */ + while (mask > 0x1) { + mask = (mask >> 1); + RateIndex++; + } + rtw_write8(padapter, REG_INIRTS_RATE_SEL, RateIndex); +} + +static void rtl8188fu_init_default_value(PADAPTER padapter) +{ + rtl8188f_init_default_value(padapter); +} + +static u8 rtl8188fu_ps_func(PADAPTER Adapter, HAL_INTF_PS_FUNC efunc_id, u8 *val) +{ + u8 bResult = _TRUE; + switch (efunc_id) { + +#if defined(CONFIG_AUTOSUSPEND) && defined(SUPPORT_HW_RFOFF_DETECTED) + case HAL_USB_SELECT_SUSPEND: { + u8 bfwpoll = *((u8 *)val); + + rtl8188f_set_FwSelectSuspend_cmd(Adapter, bfwpoll , 500); /*note fw to support hw power down ping detect */ + } + break; +#endif /*CONFIG_AUTOSUSPEND && SUPPORT_HW_RFOFF_DETECTED */ + + default: + break; + } + return bResult; +} + +void rtl8188fu_set_hal_ops(_adapter *padapter) +{ + struct hal_ops *pHalFunc = &padapter->HalFunc; + + _func_enter_; + + rtl8188f_set_hal_ops(pHalFunc); + + pHalFunc->hal_power_on = &_InitPowerOn_8188FU; + pHalFunc->hal_power_off = &CardDisableRTL8188FU; + + pHalFunc->hal_init = &rtl8188fu_hal_init; + pHalFunc->hal_deinit = &rtl8188fu_hal_deinit; + + pHalFunc->inirp_init = &rtl8188fu_inirp_init; + pHalFunc->inirp_deinit = &rtl8188fu_inirp_deinit; + + pHalFunc->init_xmit_priv = &rtl8188fu_init_xmit_priv; + pHalFunc->free_xmit_priv = &rtl8188fu_free_xmit_priv; + + pHalFunc->init_recv_priv = &rtl8188fu_init_recv_priv; + pHalFunc->free_recv_priv = &rtl8188fu_free_recv_priv; +#ifdef CONFIG_SW_LED + pHalFunc->InitSwLeds = &rtl8188fu_InitSwLeds; + pHalFunc->DeInitSwLeds = &rtl8188fu_DeInitSwLeds; +#else /*case of hw led or no led */ + pHalFunc->InitSwLeds = NULL; + pHalFunc->DeInitSwLeds = NULL; +#endif/*CONFIG_SW_LED */ + + pHalFunc->init_default_value = &rtl8188f_init_default_value; + pHalFunc->intf_chip_configure = &rtl8188fu_interface_configure; + pHalFunc->read_adapter_info = &ReadAdapterInfo8188FU; + + pHalFunc->SetHwRegHandler = &SetHwReg8188FU; + pHalFunc->GetHwRegHandler = &GetHwReg8188FU; + pHalFunc->GetHalDefVarHandler = &GetHalDefVar8188FUsb; + pHalFunc->SetHalDefVarHandler = &SetHalDefVar8188FUsb; + + pHalFunc->hal_xmit = &rtl8188fu_hal_xmit; + pHalFunc->mgnt_xmit = &rtl8188fu_mgnt_xmit; + pHalFunc->hal_xmitframe_enqueue = &rtl8188fu_hal_xmitframe_enqueue; + +#ifdef CONFIG_HOSTAPD_MLME + pHalFunc->hostap_mgnt_xmit_entry = &rtl8188fu_hostap_mgnt_xmit_entry; +#endif + pHalFunc->interface_ps_func = &rtl8188fu_ps_func; + +#ifdef CONFIG_XMIT_THREAD_MODE + pHalFunc->xmit_thread_handler = &rtl8188fu_xmit_buf_handler; +#endif +#ifdef CONFIG_SUPPORT_USB_INT + pHalFunc->interrupt_handler = interrupt_handler_8188fu; +#endif + + _func_exit_; +} + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/usb/usb_ops.c b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/usb/usb_ops.c new file mode 100644 index 000000000..f6c8d7982 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/hal/rtl8188f/usb/usb_ops.c @@ -0,0 +1,555 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + *******************************************************************************/ +#define _USB_OPS_C_ + +#include + +#ifdef CONFIG_SUPPORT_USB_INT +void interrupt_handler_8188fu(_adapter *padapter, u16 pkt_len, u8 *pbuf) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct reportpwrstate_parm pwr_rpt; + + if (pkt_len != INTERRUPT_MSG_FORMAT_LEN) { + DBG_8192C("%s Invalid interrupt content length (%d)!\n", __func__, pkt_len); + return; + } + + /* HISR */ + _rtw_memcpy(&(pHalData->IntArray[0]), &(pbuf[USB_INTR_CONTENT_HISR_OFFSET]), 4); + _rtw_memcpy(&(pHalData->IntArray[1]), &(pbuf[USB_INTR_CONTENT_HISRE_OFFSET]), 4); + +#if 0 /*DBG */ + { + u32 hisr = 0 , hisr_ex = 0; + + _rtw_memcpy(&hisr, &(pHalData->IntArray[0]), 4); + hisr = le32_to_cpu(hisr); + + _rtw_memcpy(&hisr_ex, &(pHalData->IntArray[1]), 4); + hisr_ex = le32_to_cpu(hisr_ex); + + if ((hisr != 0) || (hisr_ex != 0)) + DBG_871X("===> %s hisr:0x%08x ,hisr_ex:0x%08x\n", __func__, hisr, hisr_ex); + } +#endif + + +#ifdef CONFIG_LPS_LCLK + if (pHalData->IntArray[0] & IMR_CPWM_88E) { + _rtw_memcpy(&pwr_rpt.state, &(pbuf[USB_INTR_CONTENT_CPWM1_OFFSET]), 1); + /*_rtw_memcpy(&pwr_rpt.state2, &(pbuf[USB_INTR_CONTENT_CPWM2_OFFSET]), 1); */ + + /*88e's cpwm value only change BIT0, so driver need to add PS_STATE_S2 for LPS flow. */ + pwr_rpt.state |= PS_STATE_S2; + _set_workitem(&(adapter_to_pwrctl(padapter)->cpwm_event)); + } +#endif/*CONFIG_LPS_LCLK */ + +#ifdef CONFIG_INTERRUPT_BASED_TXBCN +#ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT + if (pHalData->IntArray[0] & IMR_BCNDMAINT0_88E) + /* suspect code indent for conditional statements */ +#endif +#ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR + if (pHalData->IntArray[0] & (IMR_TBDER_88E | IMR_TBDOK_88E)) + /* suspect code indent for conditional statements */ +#endif + { + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; +#if 0 + if (pHalData->IntArray[0] & IMR_BCNDMAINT0_88E) + DBG_8192C("%s: HISR_BCNERLY_INT\n", __func__); + if (pHalData->IntArray[0] & IMR_TBDOK_88E) + DBG_8192C("%s: HISR_TXBCNOK\n", __func__); + if (pHalData->IntArray[0] & IMR_TBDER_88E) + DBG_8192C("%s: HISR_TXBCNERR\n", __func__); +#endif + if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + /*send_beacon(padapter); */ + if (pmlmepriv->update_bcn == _TRUE) { + /*tx_beacon_hdl(padapter, NULL); */ + set_tx_beacon_cmd(padapter); + } + } +#ifdef CONFIG_CONCURRENT_MODE + if (check_buddy_fwstate(padapter, WIFI_AP_STATE)) { + /*send_beacon(padapter); */ + if (padapter->pbuddy_adapter->mlmepriv.update_bcn == _TRUE) { + /*tx_beacon_hdl(padapter, NULL); */ + set_tx_beacon_cmd(padapter->pbuddy_adapter); + } + } +#endif + } +#endif /*CONFIG_INTERRUPT_BASED_TXBCN */ + + + + +#ifdef DBG_CONFIG_ERROR_DETECT_INT + if (pHalData->IntArray[1] & IMR_TXERR_8188F) + DBG_871X("===> %s Tx Error Flag Interrupt Status\n", __func__); + if (pHalData->IntArray[1] & IMR_RXERR_8188F) + DBG_871X("===> %s Rx Error Flag INT Status\n", __func__); + if (pHalData->IntArray[1] & IMR_TXFOVW_8188F) + DBG_871X("===> %s Transmit FIFO Overflow\n", __func__); + if (pHalData->IntArray[1] & IMR_RXFOVW_8188F) + DBG_871X("===> %s Receive FIFO Overflow\n", __func__); +#endif/*DBG_CONFIG_ERROR_DETECT_INT */ + + + /* C2H Event */ + if (pbuf[0] != 0) { + _rtw_memcpy(&(pHalData->C2hArray[0]), &(pbuf[USB_INTR_CONTENT_C2H_OFFSET]), 16); + /*rtw_c2h_wk_cmd(padapter); to do.. */ + } + +} +#endif + +static s32 pre_recv_entry(union recv_frame *precvframe, u8 *pphy_status) +{ + s32 ret = _SUCCESS; +#ifdef CONFIG_CONCURRENT_MODE + u8 *primary_myid, *secondary_myid, *paddr1; + union recv_frame *precvframe_if2 = NULL; + _adapter *primary_padapter = precvframe->u.hdr.adapter; + _adapter *secondary_padapter = primary_padapter->pbuddy_adapter; + struct recv_priv *precvpriv = &primary_padapter->recvpriv; + _queue *pfree_recv_queue = &precvpriv->free_recv_queue; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(primary_padapter); + + if (!secondary_padapter) + return ret; + + paddr1 = GetAddr1Ptr(precvframe->u.hdr.rx_data); + + if (IS_MCAST(paddr1) == _FALSE) { /*unicast packets */ + /*primary_myid = myid(&primary_padapter->eeprompriv); */ + /*secondary_myid = myid(&secondary_padapter->eeprompriv); */ + secondary_myid = adapter_mac_addr(secondary_padapter); + + if (_rtw_memcmp(paddr1, secondary_myid, ETH_ALEN)) { + /*change to secondary interface */ + precvframe->u.hdr.adapter = secondary_padapter; + } + + /*ret = recv_entry(precvframe); */ + + } else { /* Handle BC/MC Packets */ + /*clone/copy to if2 */ + _pkt *pkt_copy = NULL; + struct rx_pkt_attrib *pattrib = NULL; + + precvframe_if2 = rtw_alloc_recvframe(pfree_recv_queue); + + if (!precvframe_if2) + return _FAIL; + + precvframe_if2->u.hdr.adapter = secondary_padapter; + _rtw_memcpy(&precvframe_if2->u.hdr.attrib, &precvframe->u.hdr.attrib, sizeof(struct rx_pkt_attrib)); + pattrib = &precvframe_if2->u.hdr.attrib; + + /*driver need to set skb len for skb_copy(). */ + /*If skb->len is zero, skb_copy() will not copy data from original skb. */ + skb_put(precvframe->u.hdr.pkt, pattrib->pkt_len); + + pkt_copy = rtw_skb_copy(precvframe->u.hdr.pkt); + if (pkt_copy == NULL) { + if ((pattrib->mfrag == 1) && (pattrib->frag_num == 0)) { + DBG_8192C("pre_recv_entry(): rtw_skb_copy fail , drop frag frame\n"); + rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); + return ret; + } + + pkt_copy = rtw_skb_clone(precvframe->u.hdr.pkt); + if (pkt_copy == NULL) { + DBG_8192C("pre_recv_entry(): rtw_skb_clone fail , drop frame\n"); + rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); + return ret; + } + } + + pkt_copy->dev = secondary_padapter->pnetdev; + + precvframe_if2->u.hdr.pkt = pkt_copy; + precvframe_if2->u.hdr.rx_head = pkt_copy->head; + precvframe_if2->u.hdr.rx_data = pkt_copy->data; + precvframe_if2->u.hdr.rx_tail = skb_tail_pointer(pkt_copy); + precvframe_if2->u.hdr.rx_end = skb_end_pointer(pkt_copy); + precvframe_if2->u.hdr.len = pkt_copy->len; + + /*recvframe_put(precvframe_if2, pattrib->pkt_len); */ + + if (pHalData->ReceiveConfig & RCR_APPFCS) + recvframe_pull_tail(precvframe_if2, IEEE80211_FCS_LEN); + + if (pattrib->physt) + rx_query_phy_status(precvframe_if2, pphy_status); + + if (rtw_recv_entry(precvframe_if2) != _SUCCESS) { + RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, + ("recvbuf2recvframe: rtw_recv_entry(precvframe) != _SUCCESS\n")); + } + } + + /*if (precvframe->u.hdr.attrib.physt) */ + /* rx_query_phy_status(precvframe, pphy_status); */ + + /*ret = rtw_recv_entry(precvframe); */ +#endif + + return ret; + +} + +#if 0 +static s32 pre_recv_entry(union recv_frame *precvframe, u8 *pphy_status) +{ + s32 ret = _SUCCESS; +#ifdef CONFIG_CONCURRENT_MODE + u8 *primary_myid, *secondary_myid, *paddr1; + union recv_frame *precvframe_if2 = NULL; + _adapter *primary_padapter = precvframe->u.hdr.adapter; + _adapter *secondary_padapter = primary_padapter->pbuddy_adapter; + struct recv_priv *precvpriv = &primary_padapter->recvpriv; + _queue *pfree_recv_queue = &precvpriv->free_recv_queue; + u8 *pbuf = precvframe->u.hdr.rx_data; + + if (!secondary_padapter) + return ret; + + paddr1 = GetAddr1Ptr(pbuf); + + if (IS_MCAST(paddr1) == _FALSE) { /*unicast packets */ + /*primary_myid = myid(&primary_padapter->eeprompriv); */ + secondary_myid = myid(&secondary_padapter->eeprompriv); + + if (_rtw_memcmp(paddr1, secondary_myid, ETH_ALEN)) { + /*change to secondary interface */ + precvframe->u.hdr.adapter = secondary_padapter; + } + + /*ret = recv_entry(precvframe); */ + + } else { /* Handle BC/MC Packets */ + + u8 clone = _TRUE; +#if 0 + u8 type, subtype, *paddr2, *paddr3; + + type = GetFrameType(pbuf); + subtype = GetFrameSubType(pbuf); /*bit(7)~bit(2) */ + + switch (type) { + case WIFI_MGT_TYPE: /*Handle BC/MC mgnt Packets */ + if (subtype == WIFI_BEACON) { + paddr3 = GetAddr3Ptr(precvframe->u.hdr.rx_data); + + if (check_fwstate(&secondary_padapter->mlmepriv, _FW_LINKED) && + _rtw_memcmp(paddr3, get_bssid(&secondary_padapter->mlmepriv), ETH_ALEN)) { + /*change to secondary interface */ + precvframe->u.hdr.adapter = secondary_padapter; + clone = _FALSE; + } + + if (check_fwstate(&primary_padapter->mlmepriv, _FW_LINKED) && + _rtw_memcmp(paddr3, get_bssid(&primary_padapter->mlmepriv), ETH_ALEN)) { + if (clone == _FALSE) + clone = _TRUE; + else + clone = _FALSE; + + precvframe->u.hdr.adapter = primary_padapter; + } + + if (check_fwstate(&primary_padapter->mlmepriv, _FW_UNDER_SURVEY | _FW_UNDER_LINKING) || + check_fwstate(&secondary_padapter->mlmepriv, _FW_UNDER_SURVEY | _FW_UNDER_LINKING)) { + clone = _TRUE; + precvframe->u.hdr.adapter = primary_padapter; + } + + } else if (subtype == WIFI_PROBEREQ) { + /*probe req frame is only for interface2 */ + /*change to secondary interface */ + precvframe->u.hdr.adapter = secondary_padapter; + clone = _FALSE; + } + break; + case WIFI_CTRL_TYPE: /* Handle BC/MC ctrl Packets */ + + break; + case WIFI_DATA_TYPE: /*Handle BC/MC data Packets */ + /*Notes: AP MODE never rx BC/MC data packets */ + + paddr2 = GetAddr2Ptr(precvframe->u.hdr.rx_data); + + if (_rtw_memcmp(paddr2, get_bssid(&secondary_padapter->mlmepriv), ETH_ALEN)) { + /*change to secondary interface */ + precvframe->u.hdr.adapter = secondary_padapter; + clone = _FALSE; + } + + break; + default: + + break; + } +#endif + + if (_TRUE == clone) { + /*clone/copy to if2 */ + struct rx_pkt_attrib *pattrib = NULL; + + precvframe_if2 = rtw_alloc_recvframe(pfree_recv_queue); + if (precvframe_if2) { + precvframe_if2->u.hdr.adapter = secondary_padapter; + + _rtw_init_listhead(&precvframe_if2->u.hdr.list); + precvframe_if2->u.hdr.precvbuf = NULL; /*can't access the precvbuf for new arch. */ + precvframe_if2->u.hdr.len = 0; + + _rtw_memcpy(&precvframe_if2->u.hdr.attrib, &precvframe->u.hdr.attrib, sizeof(struct rx_pkt_attrib)); + + pattrib = &precvframe_if2->u.hdr.attrib; + + if (rtw_os_alloc_recvframe(secondary_padapter, precvframe_if2, pbuf, NULL) == _SUCCESS) { + recvframe_put(precvframe_if2, pattrib->pkt_len); + /*recvframe_pull(precvframe_if2, drvinfo_sz + RXDESC_SIZE); */ + + if (pattrib->physt && pphy_status) + rx_query_phy_status(precvframe_if2, pphy_status); + + ret = rtw_recv_entry(precvframe_if2); + } else { + rtw_free_recvframe(precvframe_if2, pfree_recv_queue); + DBG_8192C("%s()-%d: alloc_skb() failed!\n", __func__, __LINE__); + } + + } + + } + + } + /*if (precvframe->u.hdr.attrib.physt) */ + /* rx_query_phy_status(precvframe, pphy_status); */ + + /*ret = rtw_recv_entry(precvframe); */ + +#endif + + return ret; + +} +#endif + +int recvbuf2recvframe(PADAPTER padapter, void *ptr) +{ + u8 *pbuf; + u8 pkt_cnt = 0; + u32 pkt_offset; + s32 transfer_len; + u8 *pdata, *pphy_status; + union recv_frame *precvframe = NULL; + struct rx_pkt_attrib *pattrib = NULL; + PHAL_DATA_TYPE pHalData; + struct recv_priv *precvpriv; + _queue *pfree_recv_queue; + _pkt *pskb; + + + pHalData = GET_HAL_DATA(padapter); + precvpriv = &padapter->recvpriv; + pfree_recv_queue = &precvpriv->free_recv_queue; + +#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX + pskb = NULL; + transfer_len = (s32)((struct recv_buf *)ptr)->transfer_len; + pbuf = ((struct recv_buf *)ptr)->pbuf; +#else /* !CONFIG_USE_USB_BUFFER_ALLOC_RX */ + pskb = (_pkt *)ptr; + transfer_len = (s32)pskb->len; + pbuf = pskb->data; +#endif /* !CONFIG_USE_USB_BUFFER_ALLOC_RX */ + +#ifdef CONFIG_USB_RX_AGGREGATION + pkt_cnt = GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8188F(pbuf); +#endif + + do { + precvframe = rtw_alloc_recvframe(pfree_recv_queue); + if (precvframe == NULL) { + DBG_8192C("%s: rtw_alloc_recvframe() failed! RX Drop!\n", __func__); + goto _exit_recvbuf2recvframe; + } + + if (transfer_len > 1500) + _rtw_init_listhead(&precvframe->u.hdr.list); + precvframe->u.hdr.precvbuf = NULL; /*can't access the precvbuf for new arch. */ + precvframe->u.hdr.len = 0; + + rtl8188f_query_rx_desc_status(precvframe, pbuf); + + pattrib = &precvframe->u.hdr.attrib; + + if ((padapter->registrypriv.mp_mode == 0) + && ((pattrib->crc_err) || (pattrib->icv_err))) { + DBG_8192C("%s: RX Warning! crc_err=%d icv_err=%d, skip!\n", + __func__, pattrib->crc_err, pattrib->icv_err); + + rtw_free_recvframe(precvframe, pfree_recv_queue); + goto _exit_recvbuf2recvframe; + } + + pkt_offset = RXDESC_SIZE + pattrib->drvinfo_sz + pattrib->shift_sz + pattrib->pkt_len; + if ((pattrib->pkt_len <= 0) || (pkt_offset > transfer_len)) { + DBG_8192C("%s: RX Error! pkt_len=%d pkt_offset=%d transfer_len=%d\n", + __func__, pattrib->pkt_len, pkt_offset, transfer_len); + + rtw_free_recvframe(precvframe, pfree_recv_queue); + goto _exit_recvbuf2recvframe; + } + + pdata = pbuf + RXDESC_SIZE + pattrib->drvinfo_sz + pattrib->shift_sz; + if (rtw_os_alloc_recvframe(padapter, precvframe, pdata, pskb) == _FAIL) { + DBG_8192C("%s: RX Error! rtw_os_alloc_recvframe FAIL!\n", __func__); + + rtw_free_recvframe(precvframe, pfree_recv_queue); + goto _exit_recvbuf2recvframe; + } + + recvframe_put(precvframe, pattrib->pkt_len); + + if (pattrib->pkt_rpt_type == NORMAL_RX) { + if (pattrib->physt) + pphy_status = pbuf + RXDESC_OFFSET; + else + pphy_status = NULL; + +#ifdef CONFIG_CONCURRENT_MODE + if (rtw_buddy_adapter_up(padapter)) { + if (pre_recv_entry(precvframe, pphy_status) != _SUCCESS) { + /* Return fail except data frame */ + /*DBG_8192C("%s: RX Error! (concurrent)pre_recv_entry FAIL!\n", __func__); */ + } + } +#endif /* CONFIG_CONCURRENT_MODE */ + + if (pphy_status) + rx_query_phy_status(precvframe, pphy_status); + + if (rtw_recv_entry(precvframe) != _SUCCESS) { + /* Return fail except data frame */ + /*DBG_8192C("%s: RX Error! rtw_recv_entry FAIL!\n", __func__); */ + } + } else { +#ifdef CONFIG_C2H_PACKET_EN + if (pattrib->pkt_rpt_type == C2H_PACKET) + rtl8188f_c2h_packet_handler(padapter, precvframe->u.hdr.rx_data, pattrib->pkt_len); + else { + DBG_8192C("%s: [WARNNING] RX type(%d) not be handled!\n", + __func__, pattrib->pkt_rpt_type); + } +#endif /* CONFIG_C2H_PACKET_EN */ + rtw_free_recvframe(precvframe, pfree_recv_queue); + } + +#ifdef CONFIG_USB_RX_AGGREGATION + /* jaguar 8-byte alignment */ + pkt_offset = (u16)_RND8(pkt_offset); + pkt_cnt--; + pbuf += pkt_offset; +#endif + transfer_len -= pkt_offset; + precvframe = NULL; + } while (transfer_len > 0); + +_exit_recvbuf2recvframe: + + return _SUCCESS; +} + + +void rtl8188fu_xmit_tasklet(unsigned long priv) +{ + int ret = _FALSE; + _adapter *padapter = (_adapter *)priv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + while (1) { + if (RTW_CANNOT_TX(padapter)) { + DBG_8192C("xmit_tasklet => bDriverStopped or bSurpriseRemoved or bWritePortCancel\n"); + break; + } + + if (rtw_xmit_ac_blocked(padapter) == _TRUE) + break; + + ret = rtl8188fu_xmitframe_complete(padapter, pxmitpriv, NULL); + + if (ret == _FALSE) + break; + + } + +} + + + +void rtl8188fu_set_intf_ops(struct _io_ops *pops) +{ + _func_enter_; + + _rtw_memset((u8 *)pops, 0, sizeof(struct _io_ops)); + + pops->_read8 = &usb_read8; + pops->_read16 = &usb_read16; + pops->_read32 = &usb_read32; + pops->_read_mem = &usb_read_mem; + pops->_read_port = &usb_read_port; + + pops->_write8 = &usb_write8; + pops->_write16 = &usb_write16; + pops->_write32 = &usb_write32; + pops->_writeN = &usb_writeN; + +#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ + pops->_write8_async = &usb_async_write8; + pops->_write16_async = &usb_async_write16; + pops->_write32_async = &usb_async_write32; +#endif + pops->_write_mem = &usb_write_mem; + pops->_write_port = &usb_write_port; + + pops->_read_port_cancel = &usb_read_port_cancel; + pops->_write_port_cancel = &usb_write_port_cancel; + +#ifdef CONFIG_USB_INTERRUPT_IN_PIPE + pops->_read_interrupt = &usb_read_interrupt; +#endif + + _func_exit_; + +} +void rtl8188fu_set_hw_type(struct dvobj_priv *pdvobj) +{ + pdvobj->HardwareType = HARDWARE_TYPE_RTL8188FU; + DBG_871X("CHIP TYPE: RTL8188FU\n"); +} diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/Hal8188FPhyCfg.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/Hal8188FPhyCfg.h new file mode 100644 index 000000000..9d729ff99 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/Hal8188FPhyCfg.h @@ -0,0 +1,149 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __INC_HAL8188FPHYCFG_H__ +#define __INC_HAL8188FPHYCFG_H__ + +/*--------------------------Define Parameters-------------------------------*/ +#define LOOP_LIMIT 5 +#define MAX_STALL_TIME 50 //us +#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80) +#define MAX_TXPWR_IDX_NMODE_92S 63 +#define Reset_Cnt_Limit 3 + +#ifdef CONFIG_PCI_HCI +#define MAX_AGGR_NUM 0x0B +#else +#define MAX_AGGR_NUM 0x07 +#endif // CONFIG_PCI_HCI + + +/*--------------------------Define Parameters End-------------------------------*/ + + +/*------------------------------Define structure----------------------------*/ + +/*------------------------------Define structure End----------------------------*/ + +/*--------------------------Exported Function prototype---------------------*/ +u32 +PHY_QueryBBReg_8188F( + IN PADAPTER Adapter, + IN u32 RegAddr, + IN u32 BitMask + ); + +VOID +PHY_SetBBReg_8188F( + IN PADAPTER Adapter, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Data + ); + +u32 +PHY_QueryRFReg_8188F( + IN PADAPTER Adapter, + IN u8 eRFPath, + IN u32 RegAddr, + IN u32 BitMask + ); + +VOID +PHY_SetRFReg_8188F( + IN PADAPTER Adapter, + IN u8 eRFPath, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Data + ); + +/* MAC/BB/RF HAL config */ +int PHY_BBConfig8188F(PADAPTER Adapter ); + +int PHY_RFConfig8188F(PADAPTER Adapter ); + +s32 PHY_MACConfig8188F(PADAPTER padapter); + +int +PHY_ConfigRFWithParaFile_8188F( + IN PADAPTER Adapter, + IN u8* pFileName, + RF_PATH eRFPath +); + +VOID +PHY_SetTxPowerIndex_8188F( + IN PADAPTER Adapter, + IN u32 PowerIndex, + IN u8 RFPath, + IN u8 Rate + ); + +u8 +PHY_GetTxPowerIndex_8188F( + IN PADAPTER pAdapter, + IN u8 RFPath, + IN u8 Rate, + IN CHANNEL_WIDTH BandWidth, + IN u8 Channel + ); + +VOID +PHY_GetTxPowerLevel8188F( + IN PADAPTER Adapter, + OUT s32* powerlevel + ); + +VOID +PHY_SetTxPowerLevel8188F( + IN PADAPTER Adapter, + IN u8 channel + ); + +VOID +PHY_SetBWMode8188F( + IN PADAPTER Adapter, + IN CHANNEL_WIDTH Bandwidth, // 20M or 40M + IN unsigned char Offset // Upper, Lower, or Don't care +); + +VOID +PHY_SwChnl8188F( // Call after initialization + IN PADAPTER Adapter, + IN u8 channel + ); + +VOID +PHY_SetSwChnlBWMode8188F( + IN PADAPTER Adapter, + IN u8 channel, + IN CHANNEL_WIDTH Bandwidth, + IN u8 Offset40, + IN u8 Offset80 +); + +VOID PHY_SetRFPathSwitch_8188F( + IN PADAPTER pAdapter, + IN BOOLEAN bMain + ); +/*--------------------------Exported Function prototype End---------------------*/ + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/Hal8188FPhyReg.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/Hal8188FPhyReg.h new file mode 100644 index 000000000..817ff8e8a --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/Hal8188FPhyReg.h @@ -0,0 +1,1171 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __INC_HAL8188FPHYREG_H__ +#define __INC_HAL8188FPHYREG_H__ + +/*--------------------------Define Parameters-------------------------------*/ + +//============================================================ +// Regsiter offset definition +//============================================================ + +// +// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF +// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF +// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 +// 3. RF register 0x00-2E +// 4. Bit Mask for BB/RF register +// 5. Other defintion for BB/RF R/W +// + + +// +// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF +// 1. Page1(0x100) +// +#define rPMAC_Reset 0x100 +#define rPMAC_TxStart 0x104 +#define rPMAC_TxLegacySIG 0x108 +#define rPMAC_TxHTSIG1 0x10c +#define rPMAC_TxHTSIG2 0x110 +#define rPMAC_PHYDebug 0x114 +#define rPMAC_TxPacketNum 0x118 +#define rPMAC_TxIdle 0x11c +#define rPMAC_TxMACHeader0 0x120 +#define rPMAC_TxMACHeader1 0x124 +#define rPMAC_TxMACHeader2 0x128 +#define rPMAC_TxMACHeader3 0x12c +#define rPMAC_TxMACHeader4 0x130 +#define rPMAC_TxMACHeader5 0x134 +#define rPMAC_TxDataType 0x138 +#define rPMAC_TxRandomSeed 0x13c +#define rPMAC_CCKPLCPPreamble 0x140 +#define rPMAC_CCKPLCPHeader 0x144 +#define rPMAC_CCKCRC16 0x148 +#define rPMAC_OFDMRxCRC32OK 0x170 +#define rPMAC_OFDMRxCRC32Er 0x174 +#define rPMAC_OFDMRxParityEr 0x178 +#define rPMAC_OFDMRxCRC8Er 0x17c +#define rPMAC_CCKCRxRC16Er 0x180 +#define rPMAC_CCKCRxRC32Er 0x184 +#define rPMAC_CCKCRxRC32OK 0x188 +#define rPMAC_TxStatus 0x18c + +// +// 2. Page2(0x200) +// +// The following two definition are only used for USB interface. +#define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address. +#define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data. + +// +// 3. Page8(0x800) +// +#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting?? + +#define rFPGA0_TxInfo 0x804 // Status report?? +#define rFPGA0_PSDFunction 0x808 + +#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain? + +#define rFPGA0_RFTiming1 0x810 // Useless now +#define rFPGA0_RFTiming2 0x814 + +#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register +#define rFPGA0_XA_HSSIParameter2 0x824 +#define rFPGA0_XB_HSSIParameter1 0x828 +#define rFPGA0_XB_HSSIParameter2 0x82c +#define rTxAGC_B_Rate18_06 0x830 +#define rTxAGC_B_Rate54_24 0x834 +#define rTxAGC_B_CCK1_55_Mcs32 0x838 +#define rTxAGC_B_Mcs03_Mcs00 0x83c + +#define rTxAGC_B_Mcs07_Mcs04 0x848 +#define rTxAGC_B_Mcs11_Mcs08 0x84c + +#define rFPGA0_XA_LSSIParameter 0x840 +#define rFPGA0_XB_LSSIParameter 0x844 + +#define rFPGA0_RFWakeUpParameter 0x850 // Useless now +#define rFPGA0_RFSleepUpParameter 0x854 + +#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch +#define rFPGA0_XCD_SwitchControl 0x85c + +#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch +#define rFPGA0_XB_RFInterfaceOE 0x864 + +#define rTxAGC_B_Mcs15_Mcs12 0x868 +#define rTxAGC_B_CCK11_A_CCK2_11 0x86c + +#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control +#define rFPGA0_XCD_RFInterfaceSW 0x874 + +#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter +#define rFPGA0_XCD_RFParameter 0x87c + +#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? +#define rFPGA0_AnalogParameter2 0x884 +#define rFPGA0_AnalogParameter3 0x888 // Useless now +#define rFPGA0_AnalogParameter4 0x88c + +#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback +#define rFPGA0_XB_LSSIReadBack 0x8a4 +#define rFPGA0_XC_LSSIReadBack 0x8a8 +#define rFPGA0_XD_LSSIReadBack 0x8ac + +#define rFPGA0_PSDReport 0x8b4 // Useless now +#define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback +#define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback +#define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value +#define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now + +// +// 4. Page9(0x900) +// +#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting?? + +#define rFPGA1_TxBlock 0x904 // Useless now +#define rFPGA1_DebugSelect 0x908 // Useless now +#define rFPGA1_TxInfo 0x90c // Useless now // Status report?? +#define rS0S1_PathSwitch 0x948 + +// +// 5. PageA(0xA00) +// +// Set Control channel to upper or lower. These settings are required only for 40MHz +#define rCCK0_System 0xa00 + +#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI +#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain + +#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series +#define rCCK0_RxAGC2 0xa10 //AGC & DAGC + +#define rCCK0_RxHP 0xa14 + +#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold +#define rCCK0_DSPParameter2 0xa1c //SQ threshold + +#define rCCK0_TxFilter1 0xa20 +#define rCCK0_TxFilter2 0xa24 +#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 +#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report +#define rCCK0_TRSSIReport 0xa50 +#define rCCK0_RxReport 0xa54 //0xa57 +#define rCCK0_FACounterLower 0xa5c //0xa5b +#define rCCK0_FACounterUpper 0xa58 //0xa5c +// +// PageB(0xB00) +// +#define rPdp_AntA 0xb00 +#define rPdp_AntA_4 0xb04 +#define rConfig_Pmpd_AntA 0xb28 +#define rConfig_AntA 0xb68 +#define rConfig_AntB 0xb6c +#define rPdp_AntB 0xb70 +#define rPdp_AntB_4 0xb74 +#define rConfig_Pmpd_AntB 0xb98 +#define rAPK 0xbd8 + +// +// 6. PageC(0xC00) +// +#define rOFDM0_LSTF 0xc00 + +#define rOFDM0_TRxPathEnable 0xc04 +#define rOFDM0_TRMuxPar 0xc08 +#define rOFDM0_TRSWIsolation 0xc0c + +#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter +#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix +#define rOFDM0_XBRxAFE 0xc18 +#define rOFDM0_XBRxIQImbalance 0xc1c +#define rOFDM0_XCRxAFE 0xc20 +#define rOFDM0_XCRxIQImbalance 0xc24 +#define rOFDM0_XDRxAFE 0xc28 +#define rOFDM0_XDRxIQImbalance 0xc2c + +#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain +#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. +#define rOFDM0_RxDetector3 0xc38 //Frame Sync. +#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI + +#define rOFDM0_RxDSP 0xc40 //Rx Sync Path +#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC +#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold +#define rOFDM0_ECCAThreshold 0xc4c // energy CCA + +#define rOFDM0_XAAGCCore1 0xc50 // DIG +#define rOFDM0_XAAGCCore2 0xc54 +#define rOFDM0_XBAGCCore1 0xc58 +#define rOFDM0_XBAGCCore2 0xc5c +#define rOFDM0_XCAGCCore1 0xc60 +#define rOFDM0_XCAGCCore2 0xc64 +#define rOFDM0_XDAGCCore1 0xc68 +#define rOFDM0_XDAGCCore2 0xc6c + +#define rOFDM0_AGCParameter1 0xc70 +#define rOFDM0_AGCParameter2 0xc74 +#define rOFDM0_AGCRSSITable 0xc78 +#define rOFDM0_HTSTFAGC 0xc7c + +#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG +#define rOFDM0_XATxAFE 0xc84 +#define rOFDM0_XBTxIQImbalance 0xc88 +#define rOFDM0_XBTxAFE 0xc8c +#define rOFDM0_XCTxIQImbalance 0xc90 +#define rOFDM0_XCTxAFE 0xc94 +#define rOFDM0_XDTxIQImbalance 0xc98 +#define rOFDM0_XDTxAFE 0xc9c + +#define rOFDM0_RxIQExtAnta 0xca0 +#define rOFDM0_TxCoeff1 0xca4 +#define rOFDM0_TxCoeff2 0xca8 +#define rOFDM0_TxCoeff3 0xcac +#define rOFDM0_TxCoeff4 0xcb0 +#define rOFDM0_TxCoeff5 0xcb4 +#define rOFDM0_TxCoeff6 0xcb8 +#define rOFDM0_RxHPParameter 0xce0 +#define rOFDM0_TxPseudoNoiseWgt 0xce4 +#define rOFDM0_FrameSync 0xcf0 +#define rOFDM0_DFSReport 0xcf4 + +// +// 7. PageD(0xD00) +// +#define rOFDM1_LSTF 0xd00 +#define rOFDM1_TRxPathEnable 0xd04 + +#define rOFDM1_CFO 0xd08 // No setting now +#define rOFDM1_CSI1 0xd10 +#define rOFDM1_SBD 0xd14 +#define rOFDM1_CSI2 0xd18 +#define rOFDM1_CFOTracking 0xd2c +#define rOFDM1_TRxMesaure1 0xd34 +#define rOFDM1_IntfDet 0xd3c +#define rOFDM1_PseudoNoiseStateAB 0xd50 +#define rOFDM1_PseudoNoiseStateCD 0xd54 +#define rOFDM1_RxPseudoNoiseWgt 0xd58 + +#define rOFDM_PHYCounter1 0xda0 //cca, parity fail +#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail +#define rOFDM_PHYCounter3 0xda8 //MCS not support + +#define rOFDM_ShortCFOAB 0xdac // No setting now +#define rOFDM_ShortCFOCD 0xdb0 +#define rOFDM_LongCFOAB 0xdb4 +#define rOFDM_LongCFOCD 0xdb8 +#define rOFDM_TailCFOAB 0xdbc +#define rOFDM_TailCFOCD 0xdc0 +#define rOFDM_PWMeasure1 0xdc4 +#define rOFDM_PWMeasure2 0xdc8 +#define rOFDM_BWReport 0xdcc +#define rOFDM_AGCReport 0xdd0 +#define rOFDM_RxSNR 0xdd4 +#define rOFDM_RxEVMCSI 0xdd8 +#define rOFDM_SIGReport 0xddc + + +// +// 8. PageE(0xE00) +// +#define rTxAGC_A_Rate18_06 0xe00 +#define rTxAGC_A_Rate54_24 0xe04 +#define rTxAGC_A_CCK1_Mcs32 0xe08 +#define rTxAGC_A_Mcs03_Mcs00 0xe10 +#define rTxAGC_A_Mcs07_Mcs04 0xe14 +#define rTxAGC_A_Mcs11_Mcs08 0xe18 +#define rTxAGC_A_Mcs15_Mcs12 0xe1c + +#define rFPGA0_IQK 0xe28 +#define rTx_IQK_Tone_A 0xe30 +#define rRx_IQK_Tone_A 0xe34 +#define rTx_IQK_PI_A 0xe38 +#define rRx_IQK_PI_A 0xe3c + +#define rTx_IQK 0xe40 +#define rRx_IQK 0xe44 +#define rIQK_AGC_Pts 0xe48 +#define rIQK_AGC_Rsp 0xe4c +#define rTx_IQK_Tone_B 0xe50 +#define rRx_IQK_Tone_B 0xe54 +#define rTx_IQK_PI_B 0xe58 +#define rRx_IQK_PI_B 0xe5c +#define rIQK_AGC_Cont 0xe60 + +#define rBlue_Tooth 0xe6c +#define rRx_Wait_CCA 0xe70 +#define rTx_CCK_RFON 0xe74 +#define rTx_CCK_BBON 0xe78 +#define rTx_OFDM_RFON 0xe7c +#define rTx_OFDM_BBON 0xe80 +#define rTx_To_Rx 0xe84 +#define rTx_To_Tx 0xe88 +#define rRx_CCK 0xe8c + +#define rTx_Power_Before_IQK_A 0xe94 +#define rTx_Power_After_IQK_A 0xe9c + +#define rRx_Power_Before_IQK_A 0xea0 +#define rRx_Power_Before_IQK_A_2 0xea4 +#define rRx_Power_After_IQK_A 0xea8 +#define rRx_Power_After_IQK_A_2 0xeac + +#define rTx_Power_Before_IQK_B 0xeb4 +#define rTx_Power_After_IQK_B 0xebc + +#define rRx_Power_Before_IQK_B 0xec0 +#define rRx_Power_Before_IQK_B_2 0xec4 +#define rRx_Power_After_IQK_B 0xec8 +#define rRx_Power_After_IQK_B_2 0xecc + +#define rRx_OFDM 0xed0 +#define rRx_Wait_RIFS 0xed4 +#define rRx_TO_Rx 0xed8 +#define rStandby 0xedc +#define rSleep 0xee0 +#define rPMPD_ANAEN 0xeec + +// +// 7. RF Register 0x00-0x2E (RF 8256) +// RF-0222D 0x00-3F +// +//Zebra1 +#define rZebra1_HSSIEnable 0x0 // Useless now +#define rZebra1_TRxEnable1 0x1 +#define rZebra1_TRxEnable2 0x2 +#define rZebra1_AGC 0x4 +#define rZebra1_ChargePump 0x5 +#define rZebra1_Channel 0x7 // RF channel switch + +//#endif +#define rZebra1_TxGain 0x8 // Useless now +#define rZebra1_TxLPF 0x9 +#define rZebra1_RxLPF 0xb +#define rZebra1_RxHPFCorner 0xc + +//Zebra4 +#define rGlobalCtrl 0 // Useless now +#define rRTL8256_TxLPF 19 +#define rRTL8256_RxLPF 11 + +//RTL8258 +#define rRTL8258_TxLPF 0x11 // Useless now +#define rRTL8258_RxLPF 0x13 +#define rRTL8258_RSSILPF 0xa + +// +// RL6052 Register definition +// +#define RF_AC 0x00 // + +#define RF_IQADJ_G1 0x01 // +#define RF_IQADJ_G2 0x02 // +#define RF_BS_PA_APSET_G1_G4 0x03 +#define RF_BS_PA_APSET_G5_G8 0x04 +#define RF_POW_TRSW 0x05 // + +#define RF_GAIN_RX 0x06 // +#define RF_GAIN_TX 0x07 // + +#define RF_TXM_IDAC 0x08 // +#define RF_IPA_G 0x09 // +#define RF_TXBIAS_G 0x0A +#define RF_TXPA_AG 0x0B +#define RF_IPA_A 0x0C // +#define RF_TXBIAS_A 0x0D +#define RF_BS_PA_APSET_G9_G11 0x0E +#define RF_BS_IQGEN 0x0F // + +#define RF_MODE1 0x10 // +#define RF_MODE2 0x11 // + +#define RF_RX_AGC_HP 0x12 // +#define RF_TX_AGC 0x13 // +#define RF_BIAS 0x14 // +#define RF_IPA 0x15 // +#define RF_TXBIAS 0x16 // +#define RF_POW_ABILITY 0x17 // +#define RF_MODE_AG 0x18 // +#define rRfChannel 0x18 // RF channel and BW switch +#define RF_CHNLBW 0x18 // RF channel and BW switch +#define RF_TOP 0x19 // + +#define RF_RX_G1 0x1A // +#define RF_RX_G2 0x1B // + +#define RF_RX_BB2 0x1C // +#define RF_RX_BB1 0x1D // + +#define RF_RCK1 0x1E // +#define RF_RCK2 0x1F // + +#define RF_TX_G1 0x20 // +#define RF_TX_G2 0x21 // +#define RF_TX_G3 0x22 // + +#define RF_TX_BB1 0x23 // + +#define RF_T_METER 0x24 // + +#define RF_SYN_G1 0x25 // RF TX Power control +#define RF_SYN_G2 0x26 // RF TX Power control +#define RF_SYN_G3 0x27 // RF TX Power control +#define RF_SYN_G4 0x28 // RF TX Power control +#define RF_SYN_G5 0x29 // RF TX Power control +#define RF_SYN_G6 0x2A // RF TX Power control +#define RF_SYN_G7 0x2B // RF TX Power control +#define RF_SYN_G8 0x2C // RF TX Power control + +#define RF_RCK_OS 0x30 // RF TX PA control + +#define RF_TXPA_G1 0x31 // RF TX PA control +#define RF_TXPA_G2 0x32 // RF TX PA control +#define RF_TXPA_G3 0x33 // RF TX PA control +#define RF_TX_BIAS_A 0x35 +#define RF_TX_BIAS_D 0x36 +#define RF_LOBF_9 0x38 +#define RF_RXRF_A3 0x3C // +#define RF_TRSW 0x3F + +#define RF_TXRF_A2 0x41 +#define RF_TXPA_G4 0x46 +#define RF_TXPA_A4 0x4B +#define RF_0x52 0x52 +#define RF_RXG_MIX_SWBW 0x87 +#define RF_DBG_LP_RX2 0xDF +#define RF_WE_LUT 0xEF +#define RF_S0S1 0xB0 + +#define RF_TX_GAIN_OFFSET_8188F(_val) (abs((_val)) | (((_val) > 0) ? BIT5 : 0)) + +// +//Bit Mask +// +// 1. Page1(0x100) +#define bBBResetB 0x100 // Useless now? +#define bGlobalResetB 0x200 +#define bOFDMTxStart 0x4 +#define bCCKTxStart 0x8 +#define bCRC32Debug 0x100 +#define bPMACLoopback 0x10 +#define bTxLSIG 0xffffff +#define bOFDMTxRate 0xf +#define bOFDMTxReserved 0x10 +#define bOFDMTxLength 0x1ffe0 +#define bOFDMTxParity 0x20000 +#define bTxHTSIG1 0xffffff +#define bTxHTMCSRate 0x7f +#define bTxHTBW 0x80 +#define bTxHTLength 0xffff00 +#define bTxHTSIG2 0xffffff +#define bTxHTSmoothing 0x1 +#define bTxHTSounding 0x2 +#define bTxHTReserved 0x4 +#define bTxHTAggreation 0x8 +#define bTxHTSTBC 0x30 +#define bTxHTAdvanceCoding 0x40 +#define bTxHTShortGI 0x80 +#define bTxHTNumberHT_LTF 0x300 +#define bTxHTCRC8 0x3fc00 +#define bCounterReset 0x10000 +#define bNumOfOFDMTx 0xffff +#define bNumOfCCKTx 0xffff0000 +#define bTxIdleInterval 0xffff +#define bOFDMService 0xffff0000 +#define bTxMACHeader 0xffffffff +#define bTxDataInit 0xff +#define bTxHTMode 0x100 +#define bTxDataType 0x30000 +#define bTxRandomSeed 0xffffffff +#define bCCKTxPreamble 0x1 +#define bCCKTxSFD 0xffff0000 +#define bCCKTxSIG 0xff +#define bCCKTxService 0xff00 +#define bCCKLengthExt 0x8000 +#define bCCKTxLength 0xffff0000 +#define bCCKTxCRC16 0xffff +#define bCCKTxStatus 0x1 +#define bOFDMTxStatus 0x2 + +#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) + +// 2. Page8(0x800) +#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD +#define bJapanMode 0x2 +#define bCCKTxSC 0x30 +#define bCCKEn 0x1000000 +#define bOFDMEn 0x2000000 + +#define bOFDMRxADCPhase 0x10000 // Useless now +#define bOFDMTxDACPhase 0x40000 +#define bXATxAGC 0x3f + +#define bAntennaSelect 0x0300 + +#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage +#define bXCTxAGC 0xf000 +#define bXDTxAGC 0xf0000 + +#define bPAStart 0xf0000000 // Useless now +#define bTRStart 0x00f00000 +#define bRFStart 0x0000f000 +#define bBBStart 0x000000f0 +#define bBBCCKStart 0x0000000f +#define bPAEnd 0xf //Reg0x814 +#define bTREnd 0x0f000000 +#define bRFEnd 0x000f0000 +#define bCCAMask 0x000000f0 //T2R +#define bR2RCCAMask 0x00000f00 +#define bHSSI_R2TDelay 0xf8000000 +#define bHSSI_T2RDelay 0xf80000 +#define bContTxHSSI 0x400 //chane gain at continue Tx +#define bIGFromCCK 0x200 +#define bAGCAddress 0x3f +#define bRxHPTx 0x7000 +#define bRxHPT2R 0x38000 +#define bRxHPCCKIni 0xc0000 +#define bAGCTxCode 0xc00000 +#define bAGCRxCode 0x300000 + +#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 +#define b3WireAddressLength 0x400 + +#define b3WireRFPowerDown 0x1 // Useless now +//#define bHWSISelect 0x8 +#define b5GPAPEPolarity 0x40000000 +#define b2GPAPEPolarity 0x80000000 +#define bRFSW_TxDefaultAnt 0x3 +#define bRFSW_TxOptionAnt 0x30 +#define bRFSW_RxDefaultAnt 0x300 +#define bRFSW_RxOptionAnt 0x3000 +#define bRFSI_3WireData 0x1 +#define bRFSI_3WireClock 0x2 +#define bRFSI_3WireLoad 0x4 +#define bRFSI_3WireRW 0x8 +#define bRFSI_3Wire 0xf + +#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW + +#define bRFSI_TRSW 0x20 // Useless now +#define bRFSI_TRSWB 0x40 +#define bRFSI_ANTSW 0x100 +#define bRFSI_ANTSWB 0x200 +#define bRFSI_PAPE 0x400 +#define bRFSI_PAPE5G 0x800 +#define bBandSelect 0x1 +#define bHTSIG2_GI 0x80 +#define bHTSIG2_Smoothing 0x01 +#define bHTSIG2_Sounding 0x02 +#define bHTSIG2_Aggreaton 0x08 +#define bHTSIG2_STBC 0x30 +#define bHTSIG2_AdvCoding 0x40 +#define bHTSIG2_NumOfHTLTF 0x300 +#define bHTSIG2_CRC8 0x3fc +#define bHTSIG1_MCS 0x7f +#define bHTSIG1_BandWidth 0x80 +#define bHTSIG1_HTLength 0xffff +#define bLSIG_Rate 0xf +#define bLSIG_Reserved 0x10 +#define bLSIG_Length 0x1fffe +#define bLSIG_Parity 0x20 +#define bCCKRxPhase 0x4 + +#define bLSSIReadAddress 0x7f800000 // T65 RF + +#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal + +#define bLSSIReadBackData 0xfffff // T65 RF + +#define bLSSIReadOKFlag 0x1000 // Useless now +#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz +#define bRegulator0Standby 0x1 +#define bRegulatorPLLStandby 0x2 +#define bRegulator1Standby 0x4 +#define bPLLPowerUp 0x8 +#define bDPLLPowerUp 0x10 +#define bDA10PowerUp 0x20 +#define bAD7PowerUp 0x200 +#define bDA6PowerUp 0x2000 +#define bXtalPowerUp 0x4000 +#define b40MDClkPowerUP 0x8000 +#define bDA6DebugMode 0x20000 +#define bDA6Swing 0x380000 + +#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ + +#define b80MClkDelay 0x18000000 // Useless +#define bAFEWatchDogEnable 0x20000000 + +#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap +#define bXtalCap23 0x3 +#define bXtalCap92x 0x0f000000 +#define bXtalCap 0x0f000000 + +#define bIntDifClkEnable 0x400 // Useless +#define bExtSigClkEnable 0x800 +#define bBandgapMbiasPowerUp 0x10000 +#define bAD11SHGain 0xc0000 +#define bAD11InputRange 0x700000 +#define bAD11OPCurrent 0x3800000 +#define bIPathLoopback 0x4000000 +#define bQPathLoopback 0x8000000 +#define bAFELoopback 0x10000000 +#define bDA10Swing 0x7e0 +#define bDA10Reverse 0x800 +#define bDAClkSource 0x1000 +#define bAD7InputRange 0x6000 +#define bAD7Gain 0x38000 +#define bAD7OutputCMMode 0x40000 +#define bAD7InputCMMode 0x380000 +#define bAD7Current 0xc00000 +#define bRegulatorAdjust 0x7000000 +#define bAD11PowerUpAtTx 0x1 +#define bDA10PSAtTx 0x10 +#define bAD11PowerUpAtRx 0x100 +#define bDA10PSAtRx 0x1000 +#define bCCKRxAGCFormat 0x200 +#define bPSDFFTSamplepPoint 0xc000 +#define bPSDAverageNum 0x3000 +#define bIQPathControl 0xc00 +#define bPSDFreq 0x3ff +#define bPSDAntennaPath 0x30 +#define bPSDIQSwitch 0x40 +#define bPSDRxTrigger 0x400000 +#define bPSDTxTrigger 0x80000000 +#define bPSDSineToneScale 0x7f000000 +#define bPSDReport 0xffff + +// 3. Page9(0x900) +#define bOFDMTxSC 0x30000000 // Useless +#define bCCKTxOn 0x1 +#define bOFDMTxOn 0x2 +#define bDebugPage 0xfff //reset debug page and also HWord, LWord +#define bDebugItem 0xff //reset debug page and LWord +#define bAntL 0x10 +#define bAntNonHT 0x100 +#define bAntHT1 0x1000 +#define bAntHT2 0x10000 +#define bAntHT1S1 0x100000 +#define bAntNonHTS1 0x1000000 + +// 4. PageA(0xA00) +#define bCCKBBMode 0x3 // Useless +#define bCCKTxPowerSaving 0x80 +#define bCCKRxPowerSaving 0x40 + +#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch + +#define bCCKScramble 0x8 // Useless +#define bCCKAntDiversity 0x8000 +#define bCCKCarrierRecovery 0x4000 +#define bCCKTxRate 0x3000 +#define bCCKDCCancel 0x0800 +#define bCCKISICancel 0x0400 +#define bCCKMatchFilter 0x0200 +#define bCCKEqualizer 0x0100 +#define bCCKPreambleDetect 0x800000 +#define bCCKFastFalseCCA 0x400000 +#define bCCKChEstStart 0x300000 +#define bCCKCCACount 0x080000 +#define bCCKcs_lim 0x070000 +#define bCCKBistMode 0x80000000 +#define bCCKCCAMask 0x40000000 +#define bCCKTxDACPhase 0x4 +#define bCCKRxADCPhase 0x20000000 //r_rx_clk +#define bCCKr_cp_mode0 0x0100 +#define bCCKTxDCOffset 0xf0 +#define bCCKRxDCOffset 0xf +#define bCCKCCAMode 0xc000 +#define bCCKFalseCS_lim 0x3f00 +#define bCCKCS_ratio 0xc00000 +#define bCCKCorgBit_sel 0x300000 +#define bCCKPD_lim 0x0f0000 +#define bCCKNewCCA 0x80000000 +#define bCCKRxHPofIG 0x8000 +#define bCCKRxIG 0x7f00 +#define bCCKLNAPolarity 0x800000 +#define bCCKRx1stGain 0x7f0000 +#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity +#define bCCKRxAGCSatLevel 0x1f000000 +#define bCCKRxAGCSatCount 0xe0 +#define bCCKRxRFSettle 0x1f //AGCsamp_dly +#define bCCKFixedRxAGC 0x8000 +//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 +#define bCCKAntennaPolarity 0x2000 +#define bCCKTxFilterType 0x0c00 +#define bCCKRxAGCReportType 0x0300 +#define bCCKRxDAGCEn 0x80000000 +#define bCCKRxDAGCPeriod 0x20000000 +#define bCCKRxDAGCSatLevel 0x1f000000 +#define bCCKTimingRecovery 0x800000 +#define bCCKTxC0 0x3f0000 +#define bCCKTxC1 0x3f000000 +#define bCCKTxC2 0x3f +#define bCCKTxC3 0x3f00 +#define bCCKTxC4 0x3f0000 +#define bCCKTxC5 0x3f000000 +#define bCCKTxC6 0x3f +#define bCCKTxC7 0x3f00 +#define bCCKDebugPort 0xff0000 +#define bCCKDACDebug 0x0f000000 +#define bCCKFalseAlarmEnable 0x8000 +#define bCCKFalseAlarmRead 0x4000 +#define bCCKTRSSI 0x7f +#define bCCKRxAGCReport 0xfe +#define bCCKRxReport_AntSel 0x80000000 +#define bCCKRxReport_MFOff 0x40000000 +#define bCCKRxRxReport_SQLoss 0x20000000 +#define bCCKRxReport_Pktloss 0x10000000 +#define bCCKRxReport_Lockedbit 0x08000000 +#define bCCKRxReport_RateError 0x04000000 +#define bCCKRxReport_RxRate 0x03000000 +#define bCCKRxFACounterLower 0xff +#define bCCKRxFACounterUpper 0xff000000 +#define bCCKRxHPAGCStart 0xe000 +#define bCCKRxHPAGCFinal 0x1c00 +#define bCCKRxFalseAlarmEnable 0x8000 +#define bCCKFACounterFreeze 0x4000 +#define bCCKTxPathSel 0x10000000 +#define bCCKDefaultRxPath 0xc000000 +#define bCCKOptionRxPath 0x3000000 + +// 5. PageC(0xC00) +#define bNumOfSTF 0x3 // Useless +#define bShift_L 0xc0 +#define bGI_TH 0xc +#define bRxPathA 0x1 +#define bRxPathB 0x2 +#define bRxPathC 0x4 +#define bRxPathD 0x8 +#define bTxPathA 0x1 +#define bTxPathB 0x2 +#define bTxPathC 0x4 +#define bTxPathD 0x8 +#define bTRSSIFreq 0x200 +#define bADCBackoff 0x3000 +#define bDFIRBackoff 0xc000 +#define bTRSSILatchPhase 0x10000 +#define bRxIDCOffset 0xff +#define bRxQDCOffset 0xff00 +#define bRxDFIRMode 0x1800000 +#define bRxDCNFType 0xe000000 +#define bRXIQImb_A 0x3ff +#define bRXIQImb_B 0xfc00 +#define bRXIQImb_C 0x3f0000 +#define bRXIQImb_D 0xffc00000 +#define bDC_dc_Notch 0x60000 +#define bRxNBINotch 0x1f000000 +#define bPD_TH 0xf +#define bPD_TH_Opt2 0xc000 +#define bPWED_TH 0x700 +#define bIfMF_Win_L 0x800 +#define bPD_Option 0x1000 +#define bMF_Win_L 0xe000 +#define bBW_Search_L 0x30000 +#define bwin_enh_L 0xc0000 +#define bBW_TH 0x700000 +#define bED_TH2 0x3800000 +#define bBW_option 0x4000000 +#define bRatio_TH 0x18000000 +#define bWindow_L 0xe0000000 +#define bSBD_Option 0x1 +#define bFrame_TH 0x1c +#define bFS_Option 0x60 +#define bDC_Slope_check 0x80 +#define bFGuard_Counter_DC_L 0xe00 +#define bFrame_Weight_Short 0x7000 +#define bSub_Tune 0xe00000 +#define bFrame_DC_Length 0xe000000 +#define bSBD_start_offset 0x30000000 +#define bFrame_TH_2 0x7 +#define bFrame_GI2_TH 0x38 +#define bGI2_Sync_en 0x40 +#define bSarch_Short_Early 0x300 +#define bSarch_Short_Late 0xc00 +#define bSarch_GI2_Late 0x70000 +#define bCFOAntSum 0x1 +#define bCFOAcc 0x2 +#define bCFOStartOffset 0xc +#define bCFOLookBack 0x70 +#define bCFOSumWeight 0x80 +#define bDAGCEnable 0x10000 +#define bTXIQImb_A 0x3ff +#define bTXIQImb_B 0xfc00 +#define bTXIQImb_C 0x3f0000 +#define bTXIQImb_D 0xffc00000 +#define bTxIDCOffset 0xff +#define bTxQDCOffset 0xff00 +#define bTxDFIRMode 0x10000 +#define bTxPesudoNoiseOn 0x4000000 +#define bTxPesudoNoise_A 0xff +#define bTxPesudoNoise_B 0xff00 +#define bTxPesudoNoise_C 0xff0000 +#define bTxPesudoNoise_D 0xff000000 +#define bCCADropOption 0x20000 +#define bCCADropThres 0xfff00000 +#define bEDCCA_H 0xf +#define bEDCCA_L 0xf0 +#define bLambda_ED 0x300 +#define bRxInitialGain 0x7f +#define bRxAntDivEn 0x80 +#define bRxAGCAddressForLNA 0x7f00 +#define bRxHighPowerFlow 0x8000 +#define bRxAGCFreezeThres 0xc0000 +#define bRxFreezeStep_AGC1 0x300000 +#define bRxFreezeStep_AGC2 0xc00000 +#define bRxFreezeStep_AGC3 0x3000000 +#define bRxFreezeStep_AGC0 0xc000000 +#define bRxRssi_Cmp_En 0x10000000 +#define bRxQuickAGCEn 0x20000000 +#define bRxAGCFreezeThresMode 0x40000000 +#define bRxOverFlowCheckType 0x80000000 +#define bRxAGCShift 0x7f +#define bTRSW_Tri_Only 0x80 +#define bPowerThres 0x300 +#define bRxAGCEn 0x1 +#define bRxAGCTogetherEn 0x2 +#define bRxAGCMin 0x4 +#define bRxHP_Ini 0x7 +#define bRxHP_TRLNA 0x70 +#define bRxHP_RSSI 0x700 +#define bRxHP_BBP1 0x7000 +#define bRxHP_BBP2 0x70000 +#define bRxHP_BBP3 0x700000 +#define bRSSI_H 0x7f0000 //the threshold for high power +#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity +#define bRxSettle_TRSW 0x7 +#define bRxSettle_LNA 0x38 +#define bRxSettle_RSSI 0x1c0 +#define bRxSettle_BBP 0xe00 +#define bRxSettle_RxHP 0x7000 +#define bRxSettle_AntSW_RSSI 0x38000 +#define bRxSettle_AntSW 0xc0000 +#define bRxProcessTime_DAGC 0x300000 +#define bRxSettle_HSSI 0x400000 +#define bRxProcessTime_BBPPW 0x800000 +#define bRxAntennaPowerShift 0x3000000 +#define bRSSITableSelect 0xc000000 +#define bRxHP_Final 0x7000000 +#define bRxHTSettle_BBP 0x7 +#define bRxHTSettle_HSSI 0x8 +#define bRxHTSettle_RxHP 0x70 +#define bRxHTSettle_BBPPW 0x80 +#define bRxHTSettle_Idle 0x300 +#define bRxHTSettle_Reserved 0x1c00 +#define bRxHTRxHPEn 0x8000 +#define bRxHTAGCFreezeThres 0x30000 +#define bRxHTAGCTogetherEn 0x40000 +#define bRxHTAGCMin 0x80000 +#define bRxHTAGCEn 0x100000 +#define bRxHTDAGCEn 0x200000 +#define bRxHTRxHP_BBP 0x1c00000 +#define bRxHTRxHP_Final 0xe0000000 +#define bRxPWRatioTH 0x3 +#define bRxPWRatioEn 0x4 +#define bRxMFHold 0x3800 +#define bRxPD_Delay_TH1 0x38 +#define bRxPD_Delay_TH2 0x1c0 +#define bRxPD_DC_COUNT_MAX 0x600 +//#define bRxMF_Hold 0x3800 +#define bRxPD_Delay_TH 0x8000 +#define bRxProcess_Delay 0xf0000 +#define bRxSearchrange_GI2_Early 0x700000 +#define bRxFrame_Guard_Counter_L 0x3800000 +#define bRxSGI_Guard_L 0xc000000 +#define bRxSGI_Search_L 0x30000000 +#define bRxSGI_TH 0xc0000000 +#define bDFSCnt0 0xff +#define bDFSCnt1 0xff00 +#define bDFSFlag 0xf0000 +#define bMFWeightSum 0x300000 +#define bMinIdxTH 0x7f000000 +#define bDAFormat 0x40000 +#define bTxChEmuEnable 0x01000000 +#define bTRSWIsolation_A 0x7f +#define bTRSWIsolation_B 0x7f00 +#define bTRSWIsolation_C 0x7f0000 +#define bTRSWIsolation_D 0x7f000000 +#define bExtLNAGain 0x7c00 + +// 6. PageE(0xE00) +#define bSTBCEn 0x4 // Useless +#define bAntennaMapping 0x10 +#define bNss 0x20 +#define bCFOAntSumD 0x200 +#define bPHYCounterReset 0x8000000 +#define bCFOReportGet 0x4000000 +#define bOFDMContinueTx 0x10000000 +#define bOFDMSingleCarrier 0x20000000 +#define bOFDMSingleTone 0x40000000 +//#define bRxPath1 0x01 +//#define bRxPath2 0x02 +//#define bRxPath3 0x04 +//#define bRxPath4 0x08 +//#define bTxPath1 0x10 +//#define bTxPath2 0x20 +#define bHTDetect 0x100 +#define bCFOEn 0x10000 +#define bCFOValue 0xfff00000 +#define bSigTone_Re 0x3f +#define bSigTone_Im 0x7f00 +#define bCounter_CCA 0xffff +#define bCounter_ParityFail 0xffff0000 +#define bCounter_RateIllegal 0xffff +#define bCounter_CRC8Fail 0xffff0000 +#define bCounter_MCSNoSupport 0xffff +#define bCounter_FastSync 0xffff +#define bShortCFO 0xfff +#define bShortCFOTLength 12 //total +#define bShortCFOFLength 11 //fraction +#define bLongCFO 0x7ff +#define bLongCFOTLength 11 +#define bLongCFOFLength 11 +#define bTailCFO 0x1fff +#define bTailCFOTLength 13 +#define bTailCFOFLength 12 +#define bmax_en_pwdB 0xffff +#define bCC_power_dB 0xffff0000 +#define bnoise_pwdB 0xffff +#define bPowerMeasTLength 10 +#define bPowerMeasFLength 3 +#define bRx_HT_BW 0x1 +#define bRxSC 0x6 +#define bRx_HT 0x8 +#define bNB_intf_det_on 0x1 +#define bIntf_win_len_cfg 0x30 +#define bNB_Intf_TH_cfg 0x1c0 +#define bRFGain 0x3f +#define bTableSel 0x40 +#define bTRSW 0x80 +#define bRxSNR_A 0xff +#define bRxSNR_B 0xff00 +#define bRxSNR_C 0xff0000 +#define bRxSNR_D 0xff000000 +#define bSNREVMTLength 8 +#define bSNREVMFLength 1 +#define bCSI1st 0xff +#define bCSI2nd 0xff00 +#define bRxEVM1st 0xff0000 +#define bRxEVM2nd 0xff000000 +#define bSIGEVM 0xff +#define bPWDB 0xff00 +#define bSGIEN 0x10000 + +#define bSFactorQAM1 0xf // Useless +#define bSFactorQAM2 0xf0 +#define bSFactorQAM3 0xf00 +#define bSFactorQAM4 0xf000 +#define bSFactorQAM5 0xf0000 +#define bSFactorQAM6 0xf0000 +#define bSFactorQAM7 0xf00000 +#define bSFactorQAM8 0xf000000 +#define bSFactorQAM9 0xf0000000 +#define bCSIScheme 0x100000 + +#define bNoiseLvlTopSet 0x3 // Useless +#define bChSmooth 0x4 +#define bChSmoothCfg1 0x38 +#define bChSmoothCfg2 0x1c0 +#define bChSmoothCfg3 0xe00 +#define bChSmoothCfg4 0x7000 +#define bMRCMode 0x800000 +#define bTHEVMCfg 0x7000000 + +#define bLoopFitType 0x1 // Useless +#define bUpdCFO 0x40 +#define bUpdCFOOffData 0x80 +#define bAdvUpdCFO 0x100 +#define bAdvTimeCtrl 0x800 +#define bUpdClko 0x1000 +#define bFC 0x6000 +#define bTrackingMode 0x8000 +#define bPhCmpEnable 0x10000 +#define bUpdClkoLTF 0x20000 +#define bComChCFO 0x40000 +#define bCSIEstiMode 0x80000 +#define bAdvUpdEqz 0x100000 +#define bUChCfg 0x7000000 +#define bUpdEqz 0x8000000 + +//Rx Pseduo noise +#define bRxPesudoNoiseOn 0x20000000 // Useless +#define bRxPesudoNoise_A 0xff +#define bRxPesudoNoise_B 0xff00 +#define bRxPesudoNoise_C 0xff0000 +#define bRxPesudoNoise_D 0xff000000 +#define bPesudoNoiseState_A 0xffff +#define bPesudoNoiseState_B 0xffff0000 +#define bPesudoNoiseState_C 0xffff +#define bPesudoNoiseState_D 0xffff0000 + +//7. RF Register +//Zebra1 +#define bZebra1_HSSIEnable 0x8 // Useless +#define bZebra1_TRxControl 0xc00 +#define bZebra1_TRxGainSetting 0x07f +#define bZebra1_RxCorner 0xc00 +#define bZebra1_TxChargePump 0x38 +#define bZebra1_RxChargePump 0x7 +#define bZebra1_ChannelNum 0xf80 +#define bZebra1_TxLPFBW 0x400 +#define bZebra1_RxLPFBW 0x600 + +//Zebra4 +#define bRTL8256RegModeCtrl1 0x100 // Useless +#define bRTL8256RegModeCtrl0 0x40 +#define bRTL8256_TxLPFBW 0x18 +#define bRTL8256_RxLPFBW 0x600 + +//RTL8258 +#define bRTL8258_TxLPFBW 0xc // Useless +#define bRTL8258_RxLPFBW 0xc00 +#define bRTL8258_RSSILPFBW 0xc0 + + +// +// Other Definition +// + +//byte endable for sb_write +#define bByte0 0x1 // Useless +#define bByte1 0x2 +#define bByte2 0x4 +#define bByte3 0x8 +#define bWord0 0x3 +#define bWord1 0xc +#define bDWord 0xf + +//for PutRegsetting & GetRegSetting BitMask +#define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f +#define bMaskByte1 0xff00 +#define bMaskByte2 0xff0000 +#define bMaskByte3 0xff000000 +#define bMaskHWord 0xffff0000 +#define bMaskLWord 0x0000ffff +#define bMaskDWord 0xffffffff +#define bMaskH3Bytes 0xffffff00 +#define bMask12Bits 0xfff +#define bMaskH4Bits 0xf0000000 +#define bMaskOFDM_D 0xffc00000 +#define bMaskCCK 0x3f3f3f3f + + +#define bEnable 0x1 // Useless +#define bDisable 0x0 + +#define LeftAntenna 0x0 // Useless +#define RightAntenna 0x1 + +#define tCheckTxStatus 500 //500ms // Useless +#define tUpdateRxCounter 100 //100ms + +#define rateCCK 0 // Useless +#define rateOFDM 1 +#define rateHT 2 + +//define Register-End +#define bPMAC_End 0x1ff // Useless +#define bFPGAPHY0_End 0x8ff +#define bFPGAPHY1_End 0x9ff +#define bCCKPHY0_End 0xaff +#define bOFDMPHY0_End 0xcff +#define bOFDMPHY1_End 0xdff + +//define max debug item in each debug page +//#define bMaxItem_FPGA_PHY0 0x9 +//#define bMaxItem_FPGA_PHY1 0x3 +//#define bMaxItem_PHY_11B 0x16 +//#define bMaxItem_OFDM_PHY0 0x29 +//#define bMaxItem_OFDM_PHY1 0x0 + +#define bPMACControl 0x0 // Useless +#define bWMACControl 0x1 +#define bWNICControl 0x2 + +#define PathA 0x0 // Useless +#define PathB 0x1 +#define PathC 0x2 +#define PathD 0x3 + +/*--------------------------Define Parameters-------------------------------*/ + + +// BB Register Definition +// +// 4. Page9(0x900) +// +#define rDPDT_control 0x92c +#define rfe_ctrl_anta_src 0x930 +#define rS0S1_PathSwitch 0x948 +#define BBrx_DFIR 0x954 +#define AGC_table_select 0xb2c + +// +// PageB(0xB00) +// +#define rPdp_AntA 0xb00 +#define rPdp_AntA_4 0xb04 +#define rPdp_AntA_8 0xb08 +#define rPdp_AntA_C 0xb0c +#define rPdp_AntA_10 0xb10 +#define rPdp_AntA_14 0xb14 +#define rPdp_AntA_18 0xb18 +#define rPdp_AntA_1C 0xb1c +#define rPdp_AntA_20 0xb20 +#define rPdp_AntA_24 0xb24 + +#define rConfig_Pmpd_AntA 0xb28 +#define rConfig_ram64x16 0xb2c + +#define rBndA 0xb30 +#define rHssiPar 0xb34 + +#define rConfig_AntA 0xb68 +#define rConfig_AntB 0xb6c + +#define rPdp_AntB 0xb70 +#define rPdp_AntB_4 0xb74 +#define rPdp_AntB_8 0xb78 +#define rPdp_AntB_C 0xb7c +#define rPdp_AntB_10 0xb80 +#define rPdp_AntB_14 0xb84 +#define rPdp_AntB_18 0xb88 +#define rPdp_AntB_1C 0xb8c +#define rPdp_AntB_20 0xb90 +#define rPdp_AntB_24 0xb94 + +#define rConfig_Pmpd_AntB 0xb98 + +#define rBndB 0xba0 + +#define rAPK 0xbd8 +#define rPm_Rx0_AntA 0xbdc +#define rPm_Rx1_AntA 0xbe0 +#define rPm_Rx2_AntA 0xbe4 +#define rPm_Rx3_AntA 0xbe8 +#define rPm_Rx0_AntB 0xbec +#define rPm_Rx1_AntB 0xbf0 +#define rPm_Rx2_AntB 0xbf4 +#define rPm_Rx3_AntB 0xbf8 + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/Hal8188FPwrSeq.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/Hal8188FPwrSeq.h new file mode 100644 index 000000000..9686d1e33 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/Hal8188FPwrSeq.h @@ -0,0 +1,200 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef REALTEK_POWER_SEQUENCE_8188F +#define REALTEK_POWER_SEQUENCE_8188F + +#include "HalPwrSeqCmd.h" + +/* + Check document WM-20130815-JackieLau-RTL8188F_Power_Architecture v08.vsd + There are 6 HW Power States: + 0: POFF--Power Off + 1: PDN--Power Down + 2: CARDEMU--Card Emulation + 3: ACT--Active Mode + 4: LPS--Low Power State + 5: SUS--Suspend + + The transision from different states are defined below + TRANS_CARDEMU_TO_ACT + TRANS_ACT_TO_CARDEMU + TRANS_CARDEMU_TO_SUS + TRANS_SUS_TO_CARDEMU + TRANS_CARDEMU_TO_PDN + TRANS_ACT_TO_LPS + TRANS_LPS_TO_ACT + + TRANS_END +*/ +#define RTL8188F_TRANS_CARDEMU_TO_ACT_STEPS 13 +#define RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS 15 +#define RTL8188F_TRANS_CARDEMU_TO_SUS_STEPS 14 +#define RTL8188F_TRANS_SUS_TO_CARDEMU_STEPS 15 +#define RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS 15 +#define RTL8188F_TRANS_PDN_TO_CARDEMU_STEPS 15 +#define RTL8188F_TRANS_ACT_TO_LPS_STEPS 11 +#define RTL8188F_TRANS_LPS_TO_ACT_STEPS 13 +#define RTL8188F_TRANS_ACT_TO_SWLPS_STEPS 21 +#define RTL8188F_TRANS_SWLPS_TO_ACT_STEPS 14 +#define RTL8188F_TRANS_END_STEPS 1 + + +#define RTL8188F_TRANS_CARDEMU_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* disable SW LPS 0x04[10]=0*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]=0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, (BIT3), 0},/* 0x4[11]=1'b0 disable WL suspend*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/* 0x4[8]=1 polling until return 0*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT0, 0},/**/ \ + {0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x35}, /*0x27<=35 to reduce RF noise*/ + +#define RTL8188F_TRANS_ACT_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \ + {0x004E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/*0x4C[23] = 0x4E[7] = 0, switch DPDT_SEL_P output from register 0x65[2] */\ + {0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x34}, /*0x27 <= 34, xtal_qsel=0 to xtal bring up*/\ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \ + +#define RTL8188F_TRANS_CARDEMU_TO_SUS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00}, /*0x07=0x00 , SOP option to disable BG/MB*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ \ + {0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/ + +#define RTL8188F_TRANS_SUS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ \ + {0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/ + +#define RTL8188F_TRANS_CARDEMU_TO_CARDDIS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x00}, /*0x07=0x00 , SOP option to disable BG/MB*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/ \ + {0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/ + +#define RTL8188F_TRANS_CARDDIS_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \ + {0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/ \ + {0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0},/* 0xC4[4] <= 1, turn off USB APHY LDO under suspend mode*/ + + +#define RTL8188F_TRANS_CARDEMU_TO_PDN \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/ + +#define RTL8188F_TRANS_PDN_TO_CARDEMU \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/ + +#define RTL8188F_TRANS_ACT_TO_LPS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0139, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*set RPWM IMR*/ \ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \ + {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ + {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ + + +#define RTL8188F_TRANS_LPS_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_SDIO,PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\ + {0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\ + {0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xff,0x35},/*xtal_qsel=1 for low noise*/ \ + {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\ + {0x002B, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0x1c, 0x1c}, /*. 0x2b[4:2] = 3b'111 to enable BB,AFE clock*/\ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ + + + #define RTL8188F_TRANS_ACT_TO_SWLPS \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0139, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/*set RPWM IMR*/ \ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF},/*Tx Pause*/ \ + {0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Whole BB is reset*/ \ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \ + {0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \ + {0x002b, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x1C, 0x00},/*0x2b[4:2]<=0 to gated BB,AFE clock*/ \ + {0x0027, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x34},/*xtal_qsel=0 for bring up*/ \ + {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x00},/* sdio LPS option*/ \ + {0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0x83},/* usb LPS option, open bandgap, xtal*/ \ + {0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0}, /* 0xC4[5]<=0, digital LDO no standby mode*/ \ + {0x00C4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, /* 0xC4[7]<=1, on domain voltage adjust*/ \ + {0x00a7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0xe0}, /* low power LPS enable for sdio*/ \ + {0x00a7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xff, 0xe4}, /* low power LPS enable for usb*/ \ + {0x0090, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /* enable WL_LPS_EN*/ + + +#define RTL8188F_TRANS_SWLPS_TO_ACT \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT7, 0},/*polling TSF stable*/\ + {0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1, enable security engine*/\ + {0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\ + {0x06B7, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x09}, /*. reset MAC rx state machine*/\ + {0x06B4, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0x86}, /*. reset MAC rx state machine*/\ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT1, BIT1},/* set CPU RAM code ready*/ \ + {0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, 0},/*Reset CPU IO Wrapper*/ \ + {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, 0},/* Enable CPU*/ \ + {0x001D, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0},/*enable CPU IO Wrapper*/ \ + {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT2, BIT2},/* Enable CPU*/ \ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT7, BIT7},/*polling FW init ready */ \ + {0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_POLLING, BIT6, BIT6},/*polling FW init ready */ \ + {0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, BIT0, BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\ + {0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,PWR_BASEADDR_MAC,PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/ + +#define RTL8188F_TRANS_END \ + /* format */ \ + /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, // comments here*/ \ + {0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0,PWR_CMD_END, 0, 0}, // + + +extern WLAN_PWR_CFG rtl8188F_power_on_flow[RTL8188F_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188F_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8188F_radio_off_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188F_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8188F_card_disable_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188F_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8188F_card_enable_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188F_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8188F_suspend_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188F_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188F_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8188F_resume_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188F_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188F_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8188F_hwpdn_flow[RTL8188F_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188F_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188F_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8188F_enter_lps_flow[RTL8188F_TRANS_ACT_TO_LPS_STEPS+RTL8188F_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8188F_leave_lps_flow[RTL8188F_TRANS_LPS_TO_ACT_STEPS+RTL8188F_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8188F_enter_swlps_flow[RTL8188F_TRANS_ACT_TO_SWLPS_STEPS+RTL8188F_TRANS_END_STEPS]; +extern WLAN_PWR_CFG rtl8188F_leave_swlps_flow[RTL8188F_TRANS_SWLPS_TO_ACT_STEPS+RTL8188F_TRANS_END_STEPS]; +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/HalPwrSeqCmd.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/HalPwrSeqCmd.h new file mode 100644 index 000000000..24e4a54b4 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/HalPwrSeqCmd.h @@ -0,0 +1,138 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HALPWRSEQCMD_H__ +#define __HALPWRSEQCMD_H__ + +#include + +/*---------------------------------------------*/ +//3 The value of cmd: 4 bits +/*---------------------------------------------*/ +#define PWR_CMD_READ 0x00 + // offset: the read register offset + // msk: the mask of the read value + // value: N/A, left by 0 + // note: dirver shall implement this function by read & msk + +#define PWR_CMD_WRITE 0x01 + // offset: the read register offset + // msk: the mask of the write bits + // value: write value + // note: driver shall implement this cmd by read & msk after write + +#define PWR_CMD_POLLING 0x02 + // offset: the read register offset + // msk: the mask of the polled value + // value: the value to be polled, masked by the msd field. + // note: driver shall implement this cmd by + // do{ + // if( (Read(offset) & msk) == (value & msk) ) + // break; + // } while(not timeout); + +#define PWR_CMD_DELAY 0x03 + // offset: the value to delay + // msk: N/A + // value: the unit of delay, 0: us, 1: ms + +#define PWR_CMD_END 0x04 + // offset: N/A + // msk: N/A + // value: N/A + +/*---------------------------------------------*/ +//3 The value of base: 4 bits +/*---------------------------------------------*/ + // define the base address of each block +#define PWR_BASEADDR_MAC 0x00 +#define PWR_BASEADDR_USB 0x01 +#define PWR_BASEADDR_PCIE 0x02 +#define PWR_BASEADDR_SDIO 0x03 + +/*---------------------------------------------*/ +//3 The value of interface_msk: 4 bits +/*---------------------------------------------*/ +#define PWR_INTF_SDIO_MSK BIT(0) +#define PWR_INTF_USB_MSK BIT(1) +#define PWR_INTF_PCI_MSK BIT(2) +#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) + +/*---------------------------------------------*/ +//3 The value of fab_msk: 4 bits +/*---------------------------------------------*/ +#define PWR_FAB_TSMC_MSK BIT(0) +#define PWR_FAB_UMC_MSK BIT(1) +#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3)) + +/*---------------------------------------------*/ +//3 The value of cut_msk: 8 bits +/*---------------------------------------------*/ +#define PWR_CUT_TESTCHIP_MSK BIT(0) +#define PWR_CUT_A_MSK BIT(1) +#define PWR_CUT_B_MSK BIT(2) +#define PWR_CUT_C_MSK BIT(3) +#define PWR_CUT_D_MSK BIT(4) +#define PWR_CUT_E_MSK BIT(5) +#define PWR_CUT_F_MSK BIT(6) +#define PWR_CUT_G_MSK BIT(7) +#define PWR_CUT_ALL_MSK 0xFF + + +typedef enum _PWRSEQ_CMD_DELAY_UNIT_ +{ + PWRSEQ_DELAY_US, + PWRSEQ_DELAY_MS, +} PWRSEQ_DELAY_UNIT; + +typedef struct _WL_PWR_CFG_ +{ + u16 offset; + u8 cut_msk; + u8 fab_msk:4; + u8 interface_msk:4; + u8 base:4; + u8 cmd:4; + u8 msk; + u8 value; +} WLAN_PWR_CFG, *PWLAN_PWR_CFG; + + +#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset +#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk +#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk +#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk +#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base +#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd +#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk +#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value + + +//================================================================================ +// Prototype of protected function. +//================================================================================ +u8 HalPwrSeqCmdParsing( + PADAPTER padapter, + u8 CutVersion, + u8 FabVersion, + u8 InterfaceType, + WLAN_PWR_CFG PwrCfgCmd[]); + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/HalVerDef.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/HalVerDef.h new file mode 100644 index 000000000..13ff3af26 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/HalVerDef.h @@ -0,0 +1,200 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_VERSION_DEF_H__ +#define __HAL_VERSION_DEF_H__ + +#define TRUE _TRUE +#define FALSE _FALSE + +// HAL_IC_TYPE_E +typedef enum tag_HAL_IC_Type_Definition +{ + CHIP_8192S = 0, + CHIP_8188C = 1, + CHIP_8192C = 2, + CHIP_8192D = 3, + CHIP_8723A = 4, + CHIP_8188E = 5, + CHIP_8812 = 6, + CHIP_8821 = 7, + CHIP_8723B = 8, + CHIP_8192E = 9, + CHIP_8814A = 10, + CHIP_8703B = 11, + CHIP_8188F = 12, +}HAL_IC_TYPE_E; + +//HAL_CHIP_TYPE_E +typedef enum tag_HAL_CHIP_Type_Definition +{ + TEST_CHIP = 0, + NORMAL_CHIP = 1, + FPGA = 2, +}HAL_CHIP_TYPE_E; + +//HAL_CUT_VERSION_E +typedef enum tag_HAL_Cut_Version_Definition +{ + A_CUT_VERSION = 0, + B_CUT_VERSION = 1, + C_CUT_VERSION = 2, + D_CUT_VERSION = 3, + E_CUT_VERSION = 4, + F_CUT_VERSION = 5, + G_CUT_VERSION = 6, + H_CUT_VERSION = 7, + I_CUT_VERSION = 8, + J_CUT_VERSION = 9, + K_CUT_VERSION = 10, +}HAL_CUT_VERSION_E; + +// HAL_Manufacturer +typedef enum tag_HAL_Manufacturer_Version_Definition +{ + CHIP_VENDOR_TSMC = 0, + CHIP_VENDOR_UMC = 1, + CHIP_VENDOR_SMIC = 2, +}HAL_VENDOR_E; + +typedef enum tag_HAL_RF_Type_Definition +{ + RF_TYPE_1T1R = 0, + RF_TYPE_1T2R = 1, + RF_TYPE_2T2R = 2, + RF_TYPE_2T3R = 3, + RF_TYPE_2T4R = 4, + RF_TYPE_3T3R = 5, + RF_TYPE_3T4R = 6, + RF_TYPE_4T4R = 7, +}HAL_RF_TYPE_E; + +typedef struct tag_HAL_VERSION +{ + HAL_IC_TYPE_E ICType; + HAL_CHIP_TYPE_E ChipType; + HAL_CUT_VERSION_E CUTVersion; + HAL_VENDOR_E VendorType; + HAL_RF_TYPE_E RFType; + u8 ROMVer; +}HAL_VERSION,*PHAL_VERSION; + +//VERSION_8192C VersionID; +//HAL_VERSION VersionID; + +// Get element +#define GET_CVID_IC_TYPE(version) ((HAL_IC_TYPE_E)(((HAL_VERSION)version).ICType) ) +#define GET_CVID_CHIP_TYPE(version) ((HAL_CHIP_TYPE_E)(((HAL_VERSION)version).ChipType) ) +#define GET_CVID_RF_TYPE(version) ((HAL_RF_TYPE_E)(((HAL_VERSION)version).RFType)) +#define GET_CVID_MANUFACTUER(version) ((HAL_VENDOR_E)(((HAL_VERSION)version).VendorType)) +#define GET_CVID_CUT_VERSION(version) ((HAL_CUT_VERSION_E)(((HAL_VERSION)version).CUTVersion)) +#define GET_CVID_ROM_VERSION(version) ((((HAL_VERSION)version).ROMVer) & ROM_VERSION_MASK) + +//---------------------------------------------------------------------------- +//Common Macro. -- +//---------------------------------------------------------------------------- +//HAL_VERSION VersionID + +// HAL_IC_TYPE_E +#if 0 +#define IS_81XXC(version) (((GET_CVID_IC_TYPE(version) == CHIP_8192C)||(GET_CVID_IC_TYPE(version) == CHIP_8188C))? TRUE : FALSE) +#define IS_8723_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723A)? TRUE : FALSE) +#define IS_92D(version) ((GET_CVID_IC_TYPE(version) == CHIP_8192D)? TRUE : FALSE) +#endif + +#define IS_8188E(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188E)? TRUE : FALSE) +#define IS_8188F(version) ((GET_CVID_IC_TYPE(version) == CHIP_8188F) ? TRUE : FALSE) +#define IS_8192E(version) ((GET_CVID_IC_TYPE(version) == CHIP_8192E)? TRUE : FALSE) +#define IS_8812_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8812)? TRUE : FALSE) +#define IS_8821_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8821)? TRUE : FALSE) +#define IS_8814A_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8814A) ? TRUE : FALSE) +#define IS_8723B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723B)? TRUE : FALSE) +#define IS_8703B_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8703B)? TRUE : FALSE) + +//HAL_CHIP_TYPE_E +#define IS_TEST_CHIP(version) ((GET_CVID_CHIP_TYPE(version)==TEST_CHIP)? TRUE: FALSE) +#define IS_NORMAL_CHIP(version) ((GET_CVID_CHIP_TYPE(version)==NORMAL_CHIP)? TRUE: FALSE) + +//HAL_CUT_VERSION_E +#define IS_A_CUT(version) ((GET_CVID_CUT_VERSION(version) == A_CUT_VERSION) ? TRUE : FALSE) +#define IS_B_CUT(version) ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? TRUE : FALSE) +#define IS_C_CUT(version) ((GET_CVID_CUT_VERSION(version) == C_CUT_VERSION) ? TRUE : FALSE) +#define IS_D_CUT(version) ((GET_CVID_CUT_VERSION(version) == D_CUT_VERSION) ? TRUE : FALSE) +#define IS_E_CUT(version) ((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? TRUE : FALSE) +#define IS_F_CUT(version) ((GET_CVID_CUT_VERSION(version) == F_CUT_VERSION) ? TRUE : FALSE) +#define IS_I_CUT(version) ((GET_CVID_CUT_VERSION(version) == I_CUT_VERSION) ? TRUE : FALSE) +#define IS_J_CUT(version) ((GET_CVID_CUT_VERSION(version) == J_CUT_VERSION) ? TRUE : FALSE) +#define IS_K_CUT(version) ((GET_CVID_CUT_VERSION(version) == K_CUT_VERSION) ? TRUE : FALSE) + +//HAL_VENDOR_E +#define IS_CHIP_VENDOR_TSMC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_TSMC)? TRUE: FALSE) +#define IS_CHIP_VENDOR_UMC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_UMC)? TRUE: FALSE) +#define IS_CHIP_VENDOR_SMIC(version) ((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_SMIC)? TRUE: FALSE) + +//HAL_RF_TYPE_E +#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T1R)? TRUE : FALSE ) +#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)? TRUE : FALSE) +#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)? TRUE : FALSE) +#define IS_3T3R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_3T3R)? TRUE : FALSE) +#define IS_3T4R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_3T4R)? TRUE : FALSE) +#define IS_4T4R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_4T4R)? TRUE : FALSE) + + + +//---------------------------------------------------------------------------- +//Chip version Macro. -- +//---------------------------------------------------------------------------- +#if 0 +#define IS_81XXC_TEST_CHIP(version) ((IS_81XXC(version) && (!IS_NORMAL_CHIP(version)))? TRUE: FALSE) + +#define IS_92C_SERIAL(version) ((IS_81XXC(version) && IS_2T2R(version)) ? TRUE : FALSE) +#define IS_81xxC_VENDOR_UMC_A_CUT(version) (IS_81XXC(version)?(IS_CHIP_VENDOR_UMC(version) ? (IS_A_CUT(version) ? TRUE : FALSE) : FALSE): FALSE) +#define IS_81xxC_VENDOR_UMC_B_CUT(version) (IS_81XXC(version)?(IS_CHIP_VENDOR_UMC(version) ? (IS_B_CUT(version) ? TRUE : FALSE) : FALSE): FALSE) +#define IS_81xxC_VENDOR_UMC_C_CUT(version) (IS_81XXC(version)?(IS_CHIP_VENDOR_UMC(version) ? (IS_C_CUT(version) ? TRUE : FALSE) : FALSE): FALSE) + +#define IS_NORMAL_CHIP92D(version) (( IS_92D(version))?((GET_CVID_CHIP_TYPE(version)==NORMAL_CHIP)? TRUE: FALSE):FALSE) + +#define IS_92D_SINGLEPHY(version) ((IS_92D(version)) ? (IS_2T2R(version) ? TRUE: FALSE) : FALSE) +#define IS_92D_C_CUT(version) ((IS_92D(version)) ? (IS_C_CUT(version) ? TRUE : FALSE) : FALSE) +#define IS_92D_D_CUT(version) ((IS_92D(version)) ? (IS_D_CUT(version) ? TRUE : FALSE) : FALSE) +#define IS_92D_E_CUT(version) ((IS_92D(version)) ? (IS_E_CUT(version) ? TRUE : FALSE) : FALSE) + +#define IS_8723A_A_CUT(version) ((IS_8723_SERIES(version)) ? ( IS_A_CUT(version)?TRUE : FALSE) : FALSE) +#define IS_8723A_B_CUT(version) ((IS_8723_SERIES(version)) ? ( IS_B_CUT(version)?TRUE : FALSE) : FALSE) +#endif +#define IS_VENDOR_8188E_I_CUT_SERIES(_Adapter) ((IS_8188E(GET_HAL_DATA(_Adapter)->VersionID)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) >= I_CUT_VERSION) ? TRUE : FALSE) : FALSE) +#define IS_VENDOR_8812A_TEST_CHIP(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? FALSE : TRUE) : FALSE) +#define IS_VENDOR_8812A_MP_CHIP(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? TRUE : FALSE) : FALSE) +#define IS_VENDOR_8812A_C_CUT(_Adapter) ((IS_8812_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) == C_CUT_VERSION) ? TRUE : FALSE) : FALSE) + +#define IS_VENDOR_8821A_TEST_CHIP(_Adapter) ((IS_8821_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? FALSE : TRUE) : FALSE) +#define IS_VENDOR_8821A_MP_CHIP(_Adapter) ((IS_8821_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? TRUE : FALSE) : FALSE) + +#define IS_VENDOR_8192E_B_CUT(_Adapter) ((GET_CVID_CUT_VERSION(GET_HAL_DATA(_Adapter)->VersionID) == B_CUT_VERSION) ? TRUE : FALSE) + +#define IS_VENDOR_8723B_TEST_CHIP(_Adapter) ((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? FALSE : TRUE) : FALSE) +#define IS_VENDOR_8723B_MP_CHIP(_Adapter) ((IS_8723B_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? TRUE : FALSE) : FALSE) + +#define IS_VENDOR_8703B_TEST_CHIP(_Adapter) ((IS_8703B_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? FALSE : TRUE) : FALSE) +#define IS_VENDOR_8703B_MP_CHIP(_Adapter) ((IS_8703B_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? TRUE : FALSE) : FALSE) +#define IS_VENDOR_8814A_TEST_CHIP(_Adapter) ((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? FALSE : TRUE) : FALSE) +#define IS_VENDOR_8814A_MP_CHIP(_Adapter) ((IS_8814A_SERIES(GET_HAL_DATA(_Adapter)->VersionID)) ? ((IS_NORMAL_CHIP(GET_HAL_DATA(_Adapter)->VersionID)) ? TRUE : FALSE) : FALSE) + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/autoconf.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/autoconf.h new file mode 100644 index 000000000..63171deca --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/autoconf.h @@ -0,0 +1,346 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2014 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +/* + * Public General Configure + */ +#define AUTOCONF_INCLUDED + +#define RTL871X_MODULE_NAME "8188FU" +#define DRV_NAME "rtl8188fu" + +#ifndef CONFIG_RTL8188F +#define CONFIG_RTL8188F +#endif +#define CONFIG_USB_HCI + +#define PLATFORM_LINUX 1 + +#define RTL8188F_USB_MAC_LOOPBACK 0 + +/* + * Wi-Fi Functions Configure + */ +#define CONFIG_80211N_HT +#define CONFIG_RECV_REORDERING_CTRL + +/* #define CONFIG_IOCTL_CFG80211 */ /* Set from Makefile */ +#ifdef CONFIG_IOCTL_CFG80211 + /* + * Indicate new sta asoc through cfg80211_new_sta + * If kernel version >= 3.2 or + * version < 3.2 but already apply cfg80211 patch, + * RTW_USE_CFG80211_STA_EVENT must be defined! + */ + /* #define RTW_USE_CFG80211_STA_EVENT */ /* Indicate new sta asoc through cfg80211_new_sta */ + #define CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER + + /* #define CONFIG_DEBUG_CFG80211 */ + /* #define CONFIG_DRV_ISSUE_PROV_REQ */ /* IOT FOR S2 */ + + #define CONFIG_SET_SCAN_DENY_TIMER + /*#define SUPPLICANT_RTK_VERSION_LOWER_THAN_JB42*/ /* wpa_supplicant realtek version <= jb42 will be defined this */ +#endif + +#define CONFIG_AP_MODE +#ifdef CONFIG_AP_MODE + #define CONFIG_NATIVEAP_MLME + #ifndef CONFIG_NATIVEAP_MLME + #define CONFIG_HOSTAPD_MLME + #endif + /* #define CONFIG_FIND_BEST_CHANNEL */ + #define CONFIG_TX_MCAST2UNI /* Support IP multicast to unicast */ + + /* #define CONFIG_AUTO_AP_MODE */ +#endif + +#define CONFIG_P2P +#ifdef CONFIG_P2P + /* + * Added by Albert 20110812 + * The CONFIG_WFD is for supporting the Wi-Fi display + */ + #define CONFIG_WFD + + #define CONFIG_P2P_REMOVE_GROUP_INFO + + /* #define CONFIG_DBG_P2P */ + #define CONFIG_P2P_PS + #define CONFIG_P2P_OP_CHK_SOCIAL_CH + #define CONFIG_CFG80211_ONECHANNEL_UNDER_CONCURRENT /* replace CONFIG_P2P_CHK_INVITE_CH_LIST flag */ + #define CONFIG_P2P_INVITE_IOT +#endif + +/* + * Added by Kurt 20110511 + */ +#ifdef CONFIG_TDLS + #define CONFIG_TDLS_DRIVER_SETUP +/* + #ifndef CONFIG_WFD + #define CONFIG_WFD + #endif + #define CONFIG_TDLS_AUTOSETUP +*/ + #define CONFIG_TDLS_AUTOCHECKALIVE + #define CONFIG_TDLS_CH_SW /* Enable this flag only when we confirm that TDLS CH SW is supported in FW */ +#endif + +/* #define CONFIG_CONCURRENT_MODE */ /* Set from Makefile */ +#ifdef CONFIG_CONCURRENT_MODE + #define CONFIG_TSF_RESET_OFFLOAD /* For 2 PORT TSF SYNC. */ + /* #define CONFIG_HWPORT_SWAP */ /* Port0->Sec , Port1 -> Pri */ + #define CONFIG_RUNTIME_PORT_SWITCH + /* #define DBG_RUNTIME_PORT_SWITCH */ + #define CONFIG_SCAN_BACKOP + + /* #define CONFIG_MULTI_VIR_IFACES */ /* besides primary&secondary interfaces, extend to support more interfaces */ +#endif /* CONFIG_CONCURRENT_MODE */ + +#define CONFIG_LAYER2_ROAMING +#define CONFIG_LAYER2_ROAMING_RESUME + +#define CONFIG_80211D + + +/* + * Hareware/Firmware Related Configure + */ +/* #define CONFIG_ANTENNA_DIVERSITY */ /* Set from Makefile */ +/* #define SUPPORT_HW_RFOFF_DETECTED */ + +#define CONFIG_LED +#ifdef CONFIG_LED + #define CONFIG_SW_LED + #ifdef CONFIG_SW_LED + /* define CONFIG_LED_HANDLED_BY_CMD_THREAD */ + #endif +#endif /* CONFIG_LED */ + +#define CONFIG_XMIT_ACK +#ifdef CONFIG_XMIT_ACK + #define CONFIG_ACTIVE_KEEP_ALIVE_CHECK +#endif + +#define CONFIG_C2H_PACKET_EN + +#define CONFIG_RF_POWER_TRIM + +#define DISABLE_BB_RF 0 + +#define RTW_NOTCH_FILTER 0 /* 0:Disable, 1:Enable, */ + +/* + * Interface Related Configure + */ +#define CONFIG_USB_TX_AGGREGATION +#define CONFIG_USB_RX_AGGREGATION + +#define USB_INTERFERENCE_ISSUE /* this should be checked in all usb interface */ + +#define CONFIG_GLOBAL_UI_PID + +#define CONFIG_OUT_EP_WIFI_MODE + +#define ENABLE_USB_DROP_INCORRECT_OUT + +/* #define CONFIG_SUPPORT_USB_INT */ +#ifdef CONFIG_SUPPORT_USB_INT +/* #define CONFIG_USB_INTERRUPT_IN_PIPE */ +#endif + +/* #define CONFIG_REDUCE_USB_TX_INT */ /* Trade-off: Improve performance, but may cause TX URBs blocked by USB Host/Bus driver on few platforms. */ + +/* + * CONFIG_USE_USB_BUFFER_ALLOC_XX uses Linux USB Buffer alloc API and is for Linux platform only now! + */ +/* #define CONFIG_USE_USB_BUFFER_ALLOC_TX */ /* Trade-off: For TX path, improve stability on some platforms, but may cause performance degrade on other platforms. */ +/* #define CONFIG_USE_USB_BUFFER_ALLOC_RX */ /* For RX path */ + +/* + * USB VENDOR REQ BUFFER ALLOCATION METHOD + * if not set we'll use function local variable (stack memory) + */ +/* #define CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE */ +#define CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC +#define CONFIG_USB_VENDOR_REQ_MUTEX +#define CONFIG_VENDOR_REQ_RETRY +/* #define CONFIG_USB_SUPPORT_ASYNC_VDN_REQ */ + + +/* + * Others + */ +#define CONFIG_SKB_COPY /* for amsdu */ + +/* #define CONFIG_EASY_REPLACEMENT */ + +/* #define CONFIG_ADAPTOR_INFO_CACHING_FILE */ /* now just applied on 8192cu only, should make it general... */ + +/* #define CONFIG_RESUME_IN_WORKQUEUE */ + +/* #define CONFIG_SET_SCAN_DENY_TIMER */ + +#define CONFIG_NEW_SIGNAL_STAT_PROCESS + +/* #define CONFIG_SIGNAL_DISPLAY_DBM */ /* display RX signal with dbm */ +#ifdef CONFIG_SIGNAL_DISPLAY_DBM +/* #define CONFIG_BACKGROUND_NOISE_MONITOR */ +#endif + +/* #define CONFIG_CHECK_AC_LIFETIME */ /* Check packet lifetime of 4 ACs. */ + +#define CONFIG_EMBEDDED_FWIMG +/* #define CONFIG_FILE_FWIMG */ + +#define CONFIG_LONG_DELAY_ISSUE +#define CONFIG_ATTEMPT_TO_FIX_AP_BEACON_ERROR + + +/* + * Auto Configure Section + */ +#ifdef CONFIG_MINIMAL_MEMORY_USAGE + #undef CONFIG_USB_TX_AGGREGATION + #undef CONFIG_USB_RX_AGGREGATION +#endif + +#ifdef CONFIG_MP_INCLUDED + #define MP_DRIVER 1 + #define CONFIG_MP_IWPRIV_SUPPORT + /* #undef CONFIG_USB_TX_AGGREGATION */ + /* #undef CONFIG_USB_RX_AGGREGATION */ +#else /* !CONFIG_MP_INCLUDED */ + #define MP_DRIVER 0 +#endif /* !CONFIG_MP_INCLUDED */ + +#ifdef CONFIG_POWER_SAVING + #define CONFIG_IPS + #define CONFIG_LPS + + #ifdef CONFIG_IPS + /* #define CONFIG_IPS_LEVEL_2 1 */ /*enable this to set default IPS mode to IPS_LEVEL_2 */ + #endif + + #if defined(CONFIG_LPS) && defined(CONFIG_SUPPORT_USB_INT) + /* #define CONFIG_LPS_LCLK */ + #endif + + #ifdef CONFIG_LPS_LCLK + #define CONFIG_XMIT_THREAD_MODE + #endif +#endif /* CONFIG_POWER_SAVING */ + +#ifdef CONFIG_BT_COEXIST + /* for ODM and outsrc BT-Coex */ + #define BT_30_SUPPORT 1 + + #ifndef CONFIG_LPS + #define CONFIG_LPS /* download reserved page to FW */ + #endif + + #ifndef CONFIG_C2H_PACKET_EN + #define CONFIG_C2H_PACKET_EN + #endif +#else /* !ONFIG_BT_COEXIST */ + #define BT_30_SUPPORT 0 +#endif /* CONFIG_BT_COEXIST */ + +#ifdef CONFIG_GPIO_WAKEUP + #ifndef WAKEUP_GPIO_IDX + #define WAKEUP_GPIO_IDX 0 /* WIFI Chip Side */ + #endif /* !WAKEUP_GPIO_IDX */ +#endif /* CONFIG_GPIO_WAKEUP */ + +#ifdef CONFIG_AP_MODE + /* #define CONFIG_INTERRUPT_BASED_TXBCN */ /* Tx Beacon when driver BCN_OK ,BCN_ERR interrupt occurs */ + #if defined(CONFIG_CONCURRENT_MODE) && defined(CONFIG_INTERRUPT_BASED_TXBCN) + #undef CONFIG_INTERRUPT_BASED_TXBCN + #endif + #ifdef CONFIG_INTERRUPT_BASED_TXBCN + /* #define CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */ + #define CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR + #endif +#endif /* CONFIG_AP_MODE */ + +#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX + +#else + #define CONFIG_PREALLOC_RECV_SKB + #ifdef CONFIG_PREALLOC_RECV_SKB + /* #define CONFIG_FIX_NR_BULKIN_BUFFER */ /* only use PREALLOC_RECV_SKB buffer, don't alloc skb at runtime */ + #endif +#endif + +#ifdef CONFIG_USB_TX_AGGREGATION +/* #define CONFIG_TX_EARLY_MODE */ +#endif + +#ifdef CONFIG_TX_EARLY_MODE +#define RTL8188F_EARLY_MODE_PKT_NUM_10 0 +#endif + + + + +/* + * Debug Related Configure + */ +// #define CONFIG_DEBUG /* DBG_871X, etc... */ +#ifdef CONFIG_DEBUG + #define DBG 1 /* for ODM & BTCOEX debug */ + #define DBG_PHYDM_MORE 0 +#else /* !CONFIG_DEBUG */ + #define DBG 0 /* for ODM & BTCOEX debug */ + #define DBG_PHYDM_MORE 0 +#endif /* CONFIG_DEBUG */ + +#if DBG_PHYDM_MORE + #define CONFIG_DEBUG_RTL871X /* RT_TRACE, RT_PRINT_DATA, _func_enter_, _func_exit_ */ +#endif /* DBG_MORE */ + +// #define CONFIG_PROC_DEBUG + +/* +#define DBG_CONFIG_ERROR_DETECT +#define DBG_CONFIG_ERROR_DETECT_INT +#define DBG_CONFIG_ERROR_RESET + +#define DBG_IO +#define DBG_DELAY_OS +#define DBG_MEM_ALLOC +#define DBG_IOCTL + +#define DBG_TX +#define DBG_XMIT_BUF +#define DBG_XMIT_BUF_EXT +#define DBG_TX_DROP_FRAME + +#define DBG_RX_DROP_FRAME +#define DBG_RX_SEQ +#define DBG_RX_SIGNAL_DISPLAY_PROCESSING +#define DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED "rtw-ap" + +#define DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE +#define DBG_ROAMING_TEST + +#define DBG_HAL_INIT_PROFILING + +#define DBG_MEMORY_LEAK 1 +*/ diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/basic_types.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/basic_types.h new file mode 100644 index 000000000..4ce029026 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/basic_types.h @@ -0,0 +1,385 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __BASIC_TYPES_H__ +#define __BASIC_TYPES_H__ + + +#define SUCCESS 0 +#define FAIL (-1) + +#ifndef TRUE + #define _TRUE 1 +#else + #define _TRUE TRUE +#endif + +#ifndef FALSE + #define _FALSE 0 +#else + #define _FALSE FALSE +#endif + +#ifdef PLATFORM_WINDOWS + + typedef signed char s8; + typedef unsigned char u8; + + typedef signed short s16; + typedef unsigned short u16; + + typedef signed long s32; + typedef unsigned long u32; + + typedef unsigned int uint; + typedef signed int sint; + + + typedef signed long long s64; + typedef unsigned long long u64; + + #ifdef NDIS50_MINIPORT + + #define NDIS_MAJOR_VERSION 5 + #define NDIS_MINOR_VERSION 0 + + #endif + + #ifdef NDIS51_MINIPORT + + #define NDIS_MAJOR_VERSION 5 + #define NDIS_MINOR_VERSION 1 + + #endif + + typedef NDIS_PROC proc_t; + + typedef LONG atomic_t; + +#endif + + +#ifdef PLATFORM_LINUX + #include + #include + #include + #include + #include + #include + #define IN + #define OUT + #define VOID void + #define NDIS_OID uint + #define NDIS_STATUS uint + + typedef signed int sint; + + #ifndef PVOID + typedef void * PVOID; + //#define PVOID (void *) + #endif + + #define UCHAR u8 + #define USHORT u16 + #define UINT u32 + #define ULONG u32 + + #if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 19)) + typedef _Bool bool; + #endif + + typedef void (*proc_t)(void*); + + typedef __kernel_size_t SIZE_T; + typedef __kernel_ssize_t SSIZE_T; + #define FIELD_OFFSET(s,field) ((SSIZE_T)&((s*)(0))->field) + +#endif + + +#ifdef PLATFORM_FREEBSD + + typedef signed char s8; + typedef unsigned char u8; + + typedef signed short s16; + typedef unsigned short u16; + + typedef signed int s32; + typedef unsigned int u32; + + typedef unsigned int uint; + typedef signed int sint; + typedef long atomic_t; + + typedef signed long long s64; + typedef unsigned long long u64; + #define IN + #define OUT + #define VOID void + #define NDIS_OID uint + #define NDIS_STATUS uint + + #ifndef PVOID + typedef void * PVOID; + //#define PVOID (void *) + #endif + typedef u32 dma_addr_t; + #define UCHAR u8 + #define USHORT u16 + #define UINT u32 + #define ULONG u32 + + typedef void (*proc_t)(void*); + + typedef unsigned int __kernel_size_t; + typedef int __kernel_ssize_t; + + typedef __kernel_size_t SIZE_T; + typedef __kernel_ssize_t SSIZE_T; + #define FIELD_OFFSET(s,field) ((SSIZE_T)&((s*)(0))->field) + +#endif + +#define MEM_ALIGNMENT_OFFSET (sizeof (SIZE_T)) +#define MEM_ALIGNMENT_PADDING (sizeof(SIZE_T) - 1) + +#define SIZE_PTR SIZE_T +#define SSIZE_PTR SSIZE_T + +/* +* Continuous bits starting from least significant bit +* Example: +* BIT_LEN_MASK_32(0) => 0x00000000 +* BIT_LEN_MASK_32(1) => 0x00000001 +* BIT_LEN_MASK_32(2) => 0x00000003 +* BIT_LEN_MASK_32(32) => 0xFFFFFFFF +*/ +#define BIT_LEN_MASK_32(__BitLen) ((u32)(0xFFFFFFFF >> (32 - (__BitLen)))) +#define BIT_LEN_MASK_16(__BitLen) ((u16)(0xFFFF >> (16 - (__BitLen)))) +#define BIT_LEN_MASK_8(__BitLen) ((u8)(0xFF >> (8 - (__BitLen)))) + +/* +* Continuous bits starting from least significant bit +* Example: +* BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 +* BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 +*/ +#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) ((u32)(BIT_LEN_MASK_32(__BitLen) << (__BitOffset))) +#define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) ((u16)(BIT_LEN_MASK_16(__BitLen) << (__BitOffset))) +#define BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) ((u8)(BIT_LEN_MASK_8(__BitLen) << (__BitOffset))) + +/* +* Convert LE data to host byte order +*/ +#define EF1Byte (u8) +#define EF2Byte le16_to_cpu +#define EF4Byte le32_to_cpu + +/* +* Read LE data from memory to host byte order +*/ +#define ReadLE4Byte(_ptr) le32_to_cpu(*((u32 *)(_ptr))) +#define ReadLE2Byte(_ptr) le16_to_cpu(*((u16 *)(_ptr))) +#define ReadLE1Byte(_ptr) (*((u8 *)(_ptr))) + +/* +* Read BE data from memory to host byte order +*/ +#define ReadBEE4Byte(_ptr) be32_to_cpu(*((u32 *)(_ptr))) +#define ReadBE2Byte(_ptr) be16_to_cpu(*((u16 *)(_ptr))) +#define ReadBE1Byte(_ptr) (*((u8 *)(_ptr))) + +/* +* Write host byte order data to memory in LE order +*/ +#define WriteLE4Byte(_ptr, _val) (*((u32 *)(_ptr))) = cpu_to_le32(_val) +#define WriteLE2Byte(_ptr, _val) (*((u16 *)(_ptr))) = cpu_to_le16(_val) +#define WriteLE1Byte(_ptr, _val) (*((u8 *)(_ptr))) = ((u8)(_val)) + +/* +* Write host byte order data to memory in BE order +*/ +#define WriteBE4Byte(_ptr, _val) (*((u32 *)(_ptr))) = cpu_to_be32(_val) +#define WriteBE2Byte(_ptr, _val) (*((u16 *)(_ptr))) = cpu_to_be16(_val) +#define WriteBE1Byte(_ptr, _val) (*((u8 *)(_ptr))) = ((u8)(_val)) + +/* +* Return 4-byte value in host byte ordering from 4-byte pointer in litten-endian system. +*/ +#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) (le32_to_cpu(*((u32 *)(__pStart)))) +#define LE_P2BYTE_TO_HOST_2BYTE(__pStart) (le16_to_cpu(*((u16 *)(__pStart)))) +#define LE_P1BYTE_TO_HOST_1BYTE(__pStart) ((*((u8 *)(__pStart)))) + +/* +* Return 4-byte value in host byte ordering from 4-byte pointer in big-endian system. +*/ +#define BE_P4BYTE_TO_HOST_4BYTE(__pStart) (be32_to_cpu(*((u32 *)(__pStart)))) +#define BE_P2BYTE_TO_HOST_2BYTE(__pStart) (be16_to_cpu(*((u16 *)(__pStart)))) +#define BE_P1BYTE_TO_HOST_1BYTE(__pStart) ((*((u8 *)(__pStart)))) + +/* +* Translate subfield (continuous bits in little-endian) of 4-byte value in LE byte to +* 4-byte value in host byte ordering. +*/ +#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + ((LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_32(__BitLen)) + +#define LE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ + ((LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_16(__BitLen)) + +#define LE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ + ((LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_8(__BitLen)) + +/* +* Translate subfield (continuous bits in big-endian) of 4-byte value in BE byte to +* 4-byte value in host byte ordering. +*/ +#define BE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + ((BE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_32(__BitLen)) + +#define BE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ + ((BE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_16(__BitLen)) + +#define BE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ + ((BE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset)) & BIT_LEN_MASK_8(__BitLen)) + +/* +* Mask subfield (continuous bits in little-endian) of 4-byte value in LE byte oredering +* and return the result in 4-byte value in host byte ordering. +*/ +#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + (LE_P4BYTE_TO_HOST_4BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen))) + +#define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ + (LE_P2BYTE_TO_HOST_2BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen))) + +#define LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ + (LE_P1BYTE_TO_HOST_1BYTE(__pStart) & ((u8)(~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen)))) + +/* +* Mask subfield (continuous bits in big-endian) of 4-byte value in BE byte oredering +* and return the result in 4-byte value in host byte ordering. +*/ +#define BE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + (BE_P4BYTE_TO_HOST_4BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen))) + +#define BE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ + (BE_P2BYTE_TO_HOST_2BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen))) + +#define BE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ + (BE_P1BYTE_TO_HOST_1BYTE(__pStart) & (~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen))) + +/* +* Set subfield of little-endian 4-byte value to specified value. +*/ +#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \ + do { \ + if (__BitOffset == 0 && __BitLen == 32) \ + WriteLE4Byte(__pStart, __Value); \ + else { \ + WriteLE4Byte(__pStart, \ + LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + | \ + ((((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset)) \ + ); \ + } \ + } while (0) + +#define SET_BITS_TO_LE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \ + do { \ + if (__BitOffset == 0 && __BitLen == 16) \ + WriteLE2Byte(__pStart, __Value); \ + else { \ + WriteLE2Byte(__pStart, \ + LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ + | \ + ((((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset)) \ + ); \ + } \ + } while (0) + +#define SET_BITS_TO_LE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \ + do { \ + if (__BitOffset == 0 && __BitLen == 8) \ + WriteLE1Byte(__pStart, __Value); \ + else { \ + WriteLE1Byte(__pStart, \ + LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ + | \ + ((((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset)) \ + ); \ + } \ + } while (0) + +/* +* Set subfield of big-endian 4-byte value to specified value. +*/ +#define SET_BITS_TO_BE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \ + do { \ + if (__BitOffset == 0 && __BitLen == 32) \ + WriteBE4Byte(__pStart, __Value); \ + else { \ + WriteBE4Byte(__pStart, \ + BE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ + | \ + ((((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset)) \ + ); \ + } \ + } while (0) + +#define SET_BITS_TO_BE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \ + do { \ + if (__BitOffset == 0 && __BitLen == 16) \ + WriteBE2Byte(__pStart, __Value); \ + else { \ + WriteBE2Byte(__pStart, \ + BE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ + | \ + ((((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset)) \ + ); \ + } \ + } while (0) + +#define SET_BITS_TO_BE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \ + do { \ + if (__BitOffset == 0 && __BitLen == 8) \ + WriteBE1Byte(__pStart, __Value); \ + else { \ + WriteBE1Byte(__pStart, \ + BE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ + | \ + ((((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset)) \ + ); \ + } \ + } while (0) + +// Get the N-bytes aligment offset from the current length +#define N_BYTE_ALIGMENT(__Value, __Aligment) ((__Aligment == 1) ? (__Value) : (((__Value + __Aligment - 1) / __Aligment) * __Aligment)) + +typedef unsigned char BOOLEAN,*PBOOLEAN; + +#define TEST_FLAG(__Flag,__testFlag) (((__Flag) & (__testFlag)) != 0) +#define SET_FLAG(__Flag, __setFlag) ((__Flag) |= __setFlag) +#define CLEAR_FLAG(__Flag, __clearFlag) ((__Flag) &= ~(__clearFlag)) +#define CLEAR_FLAGS(__Flag) ((__Flag) = 0) +#define TEST_FLAGS(__Flag, __testFlags) (((__Flag) & (__testFlags)) == (__testFlags)) + +#endif //__BASIC_TYPES_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/byteorder/big_endian.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/byteorder/big_endian.h new file mode 100644 index 000000000..ccb31328d --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/byteorder/big_endian.h @@ -0,0 +1,88 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _LINUX_BYTEORDER_BIG_ENDIAN_H +#define _LINUX_BYTEORDER_BIG_ENDIAN_H + +#ifndef __BIG_ENDIAN +#define __BIG_ENDIAN 4321 +#endif +#ifndef __BIG_ENDIAN_BITFIELD +#define __BIG_ENDIAN_BITFIELD +#endif + +#include + +#define __constant_htonl(x) ((__u32)(x)) +#define __constant_ntohl(x) ((__u32)(x)) +#define __constant_htons(x) ((__u16)(x)) +#define __constant_ntohs(x) ((__u16)(x)) +#define __constant_cpu_to_le64(x) ___constant_swab64((x)) +#define __constant_le64_to_cpu(x) ___constant_swab64((x)) +#define __constant_cpu_to_le32(x) ___constant_swab32((x)) +#define __constant_le32_to_cpu(x) ___constant_swab32((x)) +#define __constant_cpu_to_le16(x) ___constant_swab16((x)) +#define __constant_le16_to_cpu(x) ___constant_swab16((x)) +#define __constant_cpu_to_be64(x) ((__u64)(x)) +#define __constant_be64_to_cpu(x) ((__u64)(x)) +#define __constant_cpu_to_be32(x) ((__u32)(x)) +#define __constant_be32_to_cpu(x) ((__u32)(x)) +#define __constant_cpu_to_be16(x) ((__u16)(x)) +#define __constant_be16_to_cpu(x) ((__u16)(x)) +#define __cpu_to_le64(x) __swab64((x)) +#define __le64_to_cpu(x) __swab64((x)) +#define __cpu_to_le32(x) __swab32((x)) +#define __le32_to_cpu(x) __swab32((x)) +#define __cpu_to_le16(x) __swab16((x)) +#define __le16_to_cpu(x) __swab16((x)) +#define __cpu_to_be64(x) ((__u64)(x)) +#define __be64_to_cpu(x) ((__u64)(x)) +#define __cpu_to_be32(x) ((__u32)(x)) +#define __be32_to_cpu(x) ((__u32)(x)) +#define __cpu_to_be16(x) ((__u16)(x)) +#define __be16_to_cpu(x) ((__u16)(x)) +#define __cpu_to_le64p(x) __swab64p((x)) +#define __le64_to_cpup(x) __swab64p((x)) +#define __cpu_to_le32p(x) __swab32p((x)) +#define __le32_to_cpup(x) __swab32p((x)) +#define __cpu_to_le16p(x) __swab16p((x)) +#define __le16_to_cpup(x) __swab16p((x)) +#define __cpu_to_be64p(x) (*(__u64*)(x)) +#define __be64_to_cpup(x) (*(__u64*)(x)) +#define __cpu_to_be32p(x) (*(__u32*)(x)) +#define __be32_to_cpup(x) (*(__u32*)(x)) +#define __cpu_to_be16p(x) (*(__u16*)(x)) +#define __be16_to_cpup(x) (*(__u16*)(x)) +#define __cpu_to_le64s(x) __swab64s((x)) +#define __le64_to_cpus(x) __swab64s((x)) +#define __cpu_to_le32s(x) __swab32s((x)) +#define __le32_to_cpus(x) __swab32s((x)) +#define __cpu_to_le16s(x) __swab16s((x)) +#define __le16_to_cpus(x) __swab16s((x)) +#define __cpu_to_be64s(x) do {} while (0) +#define __be64_to_cpus(x) do {} while (0) +#define __cpu_to_be32s(x) do {} while (0) +#define __be32_to_cpus(x) do {} while (0) +#define __cpu_to_be16s(x) do {} while (0) +#define __be16_to_cpus(x) do {} while (0) + +#include + +#endif /* _LINUX_BYTEORDER_BIG_ENDIAN_H */ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/byteorder/generic.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/byteorder/generic.h new file mode 100644 index 000000000..759b0c472 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/byteorder/generic.h @@ -0,0 +1,213 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _LINUX_BYTEORDER_GENERIC_H +#define _LINUX_BYTEORDER_GENERIC_H + +/* + * linux/byteorder_generic.h + * Generic Byte-reordering support + * + * Francois-Rene Rideau 19970707 + * gathered all the good ideas from all asm-foo/byteorder.h into one file, + * cleaned them up. + * I hope it is compliant with non-GCC compilers. + * I decided to put __BYTEORDER_HAS_U64__ in byteorder.h, + * because I wasn't sure it would be ok to put it in types.h + * Upgraded it to 2.1.43 + * Francois-Rene Rideau 19971012 + * Upgraded it to 2.1.57 + * to please Linus T., replaced huge #ifdef's between little/big endian + * by nestedly #include'd files. + * Francois-Rene Rideau 19971205 + * Made it to 2.1.71; now a facelift: + * Put files under include/linux/byteorder/ + * Split swab from generic support. + * + * TODO: + * = Regular kernel maintainers could also replace all these manual + * byteswap macros that remain, disseminated among drivers, + * after some grep or the sources... + * = Linus might want to rename all these macros and files to fit his taste, + * to fit his personal naming scheme. + * = it seems that a few drivers would also appreciate + * nybble swapping support... + * = every architecture could add their byteswap macro in asm/byteorder.h + * see how some architectures already do (i386, alpha, ppc, etc) + * = cpu_to_beXX and beXX_to_cpu might some day need to be well + * distinguished throughout the kernel. This is not the case currently, + * since little endian, big endian, and pdp endian machines needn't it. + * But this might be the case for, say, a port of Linux to 20/21 bit + * architectures (and F21 Linux addict around?). + */ + +/* + * The following macros are to be defined by : + * + * Conversion of long and short int between network and host format + * ntohl(__u32 x) + * ntohs(__u16 x) + * htonl(__u32 x) + * htons(__u16 x) + * It seems that some programs (which? where? or perhaps a standard? POSIX?) + * might like the above to be functions, not macros (why?). + * if that's true, then detect them, and take measures. + * Anyway, the measure is: define only ___ntohl as a macro instead, + * and in a separate file, have + * unsigned long inline ntohl(x){return ___ntohl(x);} + * + * The same for constant arguments + * __constant_ntohl(__u32 x) + * __constant_ntohs(__u16 x) + * __constant_htonl(__u32 x) + * __constant_htons(__u16 x) + * + * Conversion of XX-bit integers (16- 32- or 64-) + * between native CPU format and little/big endian format + * 64-bit stuff only defined for proper architectures + * cpu_to_[bl]eXX(__uXX x) + * [bl]eXX_to_cpu(__uXX x) + * + * The same, but takes a pointer to the value to convert + * cpu_to_[bl]eXXp(__uXX x) + * [bl]eXX_to_cpup(__uXX x) + * + * The same, but change in situ + * cpu_to_[bl]eXXs(__uXX x) + * [bl]eXX_to_cpus(__uXX x) + * + * See asm-foo/byteorder.h for examples of how to provide + * architecture-optimized versions + * + */ + + +#if defined(PLATFORM_LINUX) || defined(PLATFORM_WINDOWS) || defined(PLATFORM_MPIXEL) || defined(PLATFORM_FREEBSD) +/* + * inside the kernel, we can use nicknames; + * outside of it, we must avoid POSIX namespace pollution... + */ +#define cpu_to_le64 __cpu_to_le64 +#define le64_to_cpu __le64_to_cpu +#define cpu_to_le32 __cpu_to_le32 +#define le32_to_cpu __le32_to_cpu +#define cpu_to_le16 __cpu_to_le16 +#define le16_to_cpu __le16_to_cpu +#define cpu_to_be64 __cpu_to_be64 +#define be64_to_cpu __be64_to_cpu +#define cpu_to_be32 __cpu_to_be32 +#define be32_to_cpu __be32_to_cpu +#define cpu_to_be16 __cpu_to_be16 +#define be16_to_cpu __be16_to_cpu +#define cpu_to_le64p __cpu_to_le64p +#define le64_to_cpup __le64_to_cpup +#define cpu_to_le32p __cpu_to_le32p +#define le32_to_cpup __le32_to_cpup +#define cpu_to_le16p __cpu_to_le16p +#define le16_to_cpup __le16_to_cpup +#define cpu_to_be64p __cpu_to_be64p +#define be64_to_cpup __be64_to_cpup +#define cpu_to_be32p __cpu_to_be32p +#define be32_to_cpup __be32_to_cpup +#define cpu_to_be16p __cpu_to_be16p +#define be16_to_cpup __be16_to_cpup +#define cpu_to_le64s __cpu_to_le64s +#define le64_to_cpus __le64_to_cpus +#define cpu_to_le32s __cpu_to_le32s +#define le32_to_cpus __le32_to_cpus +#define cpu_to_le16s __cpu_to_le16s +#define le16_to_cpus __le16_to_cpus +#define cpu_to_be64s __cpu_to_be64s +#define be64_to_cpus __be64_to_cpus +#define cpu_to_be32s __cpu_to_be32s +#define be32_to_cpus __be32_to_cpus +#define cpu_to_be16s __cpu_to_be16s +#define be16_to_cpus __be16_to_cpus +#endif + + +/* + * Handle ntohl and suches. These have various compatibility + * issues - like we want to give the prototype even though we + * also have a macro for them in case some strange program + * wants to take the address of the thing or something.. + * + * Note that these used to return a "long" in libc5, even though + * long is often 64-bit these days.. Thus the casts. + * + * They have to be macros in order to do the constant folding + * correctly - if the argument passed into a inline function + * it is no longer constant according to gcc.. + */ + +#undef ntohl +#undef ntohs +#undef htonl +#undef htons + +/* + * Do the prototypes. Somebody might want to take the + * address or some such sick thing.. + */ +#if defined(PLATFORM_LINUX) || (defined (__GLIBC__) && __GLIBC__ >= 2) +extern __u32 ntohl(__u32); +extern __u32 htonl(__u32); +#else //defined(PLATFORM_LINUX) || (defined (__GLIBC__) && __GLIBC__ >= 2) +#ifndef PLATFORM_FREEBSD +extern unsigned long int ntohl(unsigned long int); +extern unsigned long int htonl(unsigned long int); +#endif +#endif +#ifndef PLATFORM_FREEBSD +extern unsigned short int ntohs(unsigned short int); +extern unsigned short int htons(unsigned short int); +#endif + +#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__) || defined(PLATFORM_MPIXEL) + +#define ___htonl(x) __cpu_to_be32(x) +#define ___htons(x) __cpu_to_be16(x) +#define ___ntohl(x) __be32_to_cpu(x) +#define ___ntohs(x) __be16_to_cpu(x) + +#if defined(PLATFORM_LINUX) || (defined (__GLIBC__) && __GLIBC__ >= 2) +#define htonl(x) ___htonl(x) +#define ntohl(x) ___ntohl(x) +#else +#define htonl(x) ((unsigned long)___htonl(x)) +#define ntohl(x) ((unsigned long)___ntohl(x)) +#endif +#define htons(x) ___htons(x) +#define ntohs(x) ___ntohs(x) + +#endif /* OPTIMIZE */ + + +#if defined (PLATFORM_WINDOWS) + +#define htonl(x) __cpu_to_be32(x) +#define ntohl(x) __be32_to_cpu(x) +#define htons(x) __cpu_to_be16(x) +#define ntohs(x) __be16_to_cpu(x) + + +#endif + +#endif /* _LINUX_BYTEORDER_GENERIC_H */ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/byteorder/little_endian.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/byteorder/little_endian.h new file mode 100644 index 000000000..5a3c8ab48 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/byteorder/little_endian.h @@ -0,0 +1,90 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _LINUX_BYTEORDER_LITTLE_ENDIAN_H +#define _LINUX_BYTEORDER_LITTLE_ENDIAN_H + +#ifndef __LITTLE_ENDIAN +#define __LITTLE_ENDIAN 1234 +#endif +#ifndef __LITTLE_ENDIAN_BITFIELD +#define __LITTLE_ENDIAN_BITFIELD +#endif + +#include + +#ifndef __constant_htonl +#define __constant_htonl(x) ___constant_swab32((x)) +#define __constant_ntohl(x) ___constant_swab32((x)) +#define __constant_htons(x) ___constant_swab16((x)) +#define __constant_ntohs(x) ___constant_swab16((x)) +#define __constant_cpu_to_le64(x) ((__u64)(x)) +#define __constant_le64_to_cpu(x) ((__u64)(x)) +#define __constant_cpu_to_le32(x) ((__u32)(x)) +#define __constant_le32_to_cpu(x) ((__u32)(x)) +#define __constant_cpu_to_le16(x) ((__u16)(x)) +#define __constant_le16_to_cpu(x) ((__u16)(x)) +#define __constant_cpu_to_be64(x) ___constant_swab64((x)) +#define __constant_be64_to_cpu(x) ___constant_swab64((x)) +#define __constant_cpu_to_be32(x) ___constant_swab32((x)) +#define __constant_be32_to_cpu(x) ___constant_swab32((x)) +#define __constant_cpu_to_be16(x) ___constant_swab16((x)) +#define __constant_be16_to_cpu(x) ___constant_swab16((x)) +#define __cpu_to_le64(x) ((__u64)(x)) +#define __le64_to_cpu(x) ((__u64)(x)) +#define __cpu_to_le32(x) ((__u32)(x)) +#define __le32_to_cpu(x) ((__u32)(x)) +#define __cpu_to_le16(x) ((__u16)(x)) +#define __le16_to_cpu(x) ((__u16)(x)) +#define __cpu_to_be64(x) __swab64((x)) +#define __be64_to_cpu(x) __swab64((x)) +#define __cpu_to_be32(x) __swab32((x)) +#define __be32_to_cpu(x) __swab32((x)) +#define __cpu_to_be16(x) __swab16((x)) +#define __be16_to_cpu(x) __swab16((x)) +#define __cpu_to_le64p(x) (*(__u64*)(x)) +#define __le64_to_cpup(x) (*(__u64*)(x)) +#define __cpu_to_le32p(x) (*(__u32*)(x)) +#define __le32_to_cpup(x) (*(__u32*)(x)) +#define __cpu_to_le16p(x) (*(__u16*)(x)) +#define __le16_to_cpup(x) (*(__u16*)(x)) +#define __cpu_to_be64p(x) __swab64p((x)) +#define __be64_to_cpup(x) __swab64p((x)) +#define __cpu_to_be32p(x) __swab32p((x)) +#define __be32_to_cpup(x) __swab32p((x)) +#define __cpu_to_be16p(x) __swab16p((x)) +#define __be16_to_cpup(x) __swab16p((x)) +#define __cpu_to_le64s(x) do {} while (0) +#define __le64_to_cpus(x) do {} while (0) +#define __cpu_to_le32s(x) do {} while (0) +#define __le32_to_cpus(x) do {} while (0) +#define __cpu_to_le16s(x) do {} while (0) +#define __le16_to_cpus(x) do {} while (0) +#define __cpu_to_be64s(x) __swab64s((x)) +#define __be64_to_cpus(x) __swab64s((x)) +#define __cpu_to_be32s(x) __swab32s((x)) +#define __be32_to_cpus(x) __swab32s((x)) +#define __cpu_to_be16s(x) __swab16s((x)) +#define __be16_to_cpus(x) __swab16s((x)) +#endif // __constant_htonl + +#include + +#endif /* _LINUX_BYTEORDER_LITTLE_ENDIAN_H */ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/byteorder/swab.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/byteorder/swab.h new file mode 100644 index 000000000..067c8e434 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/byteorder/swab.h @@ -0,0 +1,141 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _LINUX_BYTEORDER_SWAB_H +#define _LINUX_BYTEORDER_SWAB_H + +#if !defined(CONFIG_PLATFORM_MSTAR) +#ifndef __u16 +typedef unsigned short __u16; +#endif + +#ifndef __u32 +typedef unsigned int __u32; +#endif + +#ifndef __u8 +typedef unsigned char __u8; +#endif + +#ifndef __u64 +typedef unsigned long long __u64; +#endif + + +__inline static __u16 ___swab16(__u16 x) +{ + __u16 __x = x; + return + ((__u16)( + (((__u16)(__x) & (__u16)0x00ffU) << 8) | + (((__u16)(__x) & (__u16)0xff00U) >> 8) )); + +} + +__inline static __u32 ___swab32(__u32 x) +{ + __u32 __x = (x); + return ((__u32)( + (((__u32)(__x) & (__u32)0x000000ffUL) << 24) | + (((__u32)(__x) & (__u32)0x0000ff00UL) << 8) | + (((__u32)(__x) & (__u32)0x00ff0000UL) >> 8) | + (((__u32)(__x) & (__u32)0xff000000UL) >> 24) )); +} + +__inline static __u64 ___swab64(__u64 x) +{ + __u64 __x = (x); + + return + ((__u64)( \ + (__u64)(((__u64)(__x) & (__u64)0x00000000000000ffULL) << 56) | \ + (__u64)(((__u64)(__x) & (__u64)0x000000000000ff00ULL) << 40) | \ + (__u64)(((__u64)(__x) & (__u64)0x0000000000ff0000ULL) << 24) | \ + (__u64)(((__u64)(__x) & (__u64)0x00000000ff000000ULL) << 8) | \ + (__u64)(((__u64)(__x) & (__u64)0x000000ff00000000ULL) >> 8) | \ + (__u64)(((__u64)(__x) & (__u64)0x0000ff0000000000ULL) >> 24) | \ + (__u64)(((__u64)(__x) & (__u64)0x00ff000000000000ULL) >> 40) | \ + (__u64)(((__u64)(__x) & (__u64)0xff00000000000000ULL) >> 56) )); \ +} +#endif // CONFIG_PLATFORM_MSTAR + +#ifndef __arch__swab16 +__inline static __u16 __arch__swab16(__u16 x) +{ + return ___swab16(x); +} + +#endif + +#ifndef __arch__swab32 +__inline static __u32 __arch__swab32(__u32 x) +{ + __u32 __tmp = (x) ; + return ___swab32(__tmp); +} +#endif + +#ifndef __arch__swab64 + +__inline static __u64 __arch__swab64(__u64 x) +{ + __u64 __tmp = (x) ; + return ___swab64(__tmp); +} + + +#endif + +#ifndef __swab16 +#define __swab16(x) __fswab16(x) +#define __swab32(x) __fswab32(x) +#define __swab64(x) __fswab64(x) +#endif // __swab16 + +#ifdef PLATFORM_FREEBSD +__inline static __u16 __fswab16(__u16 x) +#else +__inline static const __u16 __fswab16(__u16 x) +#endif //PLATFORM_FREEBSD +{ + return __arch__swab16(x); +} +#ifdef PLATFORM_FREEBSD +__inline static __u32 __fswab32(__u32 x) +#else +__inline static const __u32 __fswab32(__u32 x) +#endif //PLATFORM_FREEBSD +{ + return __arch__swab32(x); +} + +#if defined(PLATFORM_LINUX) || defined(PLATFORM_WINDOWS) +#define swab16 __swab16 +#define swab32 __swab32 +#define swab64 __swab64 +#define swab16p __swab16p +#define swab32p __swab32p +#define swab64p __swab64p +#define swab16s __swab16s +#define swab32s __swab32s +#define swab64s __swab64s +#endif + +#endif /* _LINUX_BYTEORDER_SWAB_H */ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/byteorder/swabb.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/byteorder/swabb.h new file mode 100644 index 000000000..dbbd50f89 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/byteorder/swabb.h @@ -0,0 +1,157 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _LINUX_BYTEORDER_SWABB_H +#define _LINUX_BYTEORDER_SWABB_H + +/* + * linux/byteorder/swabb.h + * SWAp Bytes Bizarrely + * swaHHXX[ps]?(foo) + * + * Support for obNUXIous pdp-endian and other bizarre architectures. + * Will Linux ever run on such ancient beasts? if not, this file + * will be but a programming pearl. Still, it's a reminder that we + * shouldn't be making too many assumptions when trying to be portable. + * + */ + +/* + * Meaning of the names I chose (vaxlinux people feel free to correct them): + * swahw32 swap 16-bit half-words in a 32-bit word + * swahb32 swap 8-bit halves of each 16-bit half-word in a 32-bit word + * + * No 64-bit support yet. I don't know NUXI conventions for long longs. + * I guarantee it will be a mess when it's there, though :-> + * It will be even worse if there are conflicting 64-bit conventions. + * Hopefully, no one ever used 64-bit objects on NUXI machines. + * + */ + +#define ___swahw32(x) \ +({ \ + __u32 __x = (x); \ + ((__u32)( \ + (((__u32)(__x) & (__u32)0x0000ffffUL) << 16) | \ + (((__u32)(__x) & (__u32)0xffff0000UL) >> 16) )); \ +}) +#define ___swahb32(x) \ +({ \ + __u32 __x = (x); \ + ((__u32)( \ + (((__u32)(__x) & (__u32)0x00ff00ffUL) << 8) | \ + (((__u32)(__x) & (__u32)0xff00ff00UL) >> 8) )); \ +}) + +#define ___constant_swahw32(x) \ + ((__u32)( \ + (((__u32)(x) & (__u32)0x0000ffffUL) << 16) | \ + (((__u32)(x) & (__u32)0xffff0000UL) >> 16) )) +#define ___constant_swahb32(x) \ + ((__u32)( \ + (((__u32)(x) & (__u32)0x00ff00ffUL) << 8) | \ + (((__u32)(x) & (__u32)0xff00ff00UL) >> 8) )) + +/* + * provide defaults when no architecture-specific optimization is detected + */ +#ifndef __arch__swahw32 +# define __arch__swahw32(x) ___swahw32(x) +#endif +#ifndef __arch__swahb32 +# define __arch__swahb32(x) ___swahb32(x) +#endif + +#ifndef __arch__swahw32p +# define __arch__swahw32p(x) __swahw32(*(x)) +#endif +#ifndef __arch__swahb32p +# define __arch__swahb32p(x) __swahb32(*(x)) +#endif + +#ifndef __arch__swahw32s +# define __arch__swahw32s(x) do { *(x) = __swahw32p((x)); } while (0) +#endif +#ifndef __arch__swahb32s +# define __arch__swahb32s(x) do { *(x) = __swahb32p((x)); } while (0) +#endif + + +/* + * Allow constant folding + */ +#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__) +# define __swahw32(x) \ +(__builtin_constant_p((__u32)(x)) ? \ + ___swahw32((x)) : \ + __fswahw32((x))) +# define __swahb32(x) \ +(__builtin_constant_p((__u32)(x)) ? \ + ___swahb32((x)) : \ + __fswahb32((x))) +#else +# define __swahw32(x) __fswahw32(x) +# define __swahb32(x) __fswahb32(x) +#endif /* OPTIMIZE */ + + +__inline static__ __const__ __u32 __fswahw32(__u32 x) +{ + return __arch__swahw32(x); +} +__inline static__ __u32 __swahw32p(__u32 *x) +{ + return __arch__swahw32p(x); +} +__inline static__ void __swahw32s(__u32 *addr) +{ + __arch__swahw32s(addr); +} + + +__inline static__ __const__ __u32 __fswahb32(__u32 x) +{ + return __arch__swahb32(x); +} +__inline static__ __u32 __swahb32p(__u32 *x) +{ + return __arch__swahb32p(x); +} +__inline static__ void __swahb32s(__u32 *addr) +{ + __arch__swahb32s(addr); +} + +#ifdef __BYTEORDER_HAS_U64__ +/* + * Not supported yet + */ +#endif /* __BYTEORDER_HAS_U64__ */ + +#if defined(PLATFORM_LINUX) +#define swahw32 __swahw32 +#define swahb32 __swahb32 +#define swahw32p __swahw32p +#define swahb32p __swahb32p +#define swahw32s __swahw32s +#define swahb32s __swahb32s +#endif + +#endif /* _LINUX_BYTEORDER_SWABB_H */ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/circ_buf.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/circ_buf.h new file mode 100644 index 000000000..23523164c --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/circ_buf.h @@ -0,0 +1,28 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __CIRC_BUF_H_ +#define __CIRC_BUF_H_ 1 + +#define CIRC_CNT(head,tail,size) (((head) - (tail)) & ((size)-1)) + +#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size)) + +#endif //_CIRC_BUF_H_ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/cmd_osdep.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/cmd_osdep.h new file mode 100644 index 000000000..65a7253b3 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/cmd_osdep.h @@ -0,0 +1,32 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __CMD_OSDEP_H_ +#define __CMD_OSDEP_H_ + + +extern sint _rtw_init_cmd_priv (struct cmd_priv *pcmdpriv); +extern sint _rtw_init_evt_priv(struct evt_priv *pevtpriv); +extern void _rtw_free_evt_priv (struct evt_priv *pevtpriv); +extern void _rtw_free_cmd_priv (struct cmd_priv *pcmdpriv); +extern sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj, bool to_head); +extern struct cmd_obj *_rtw_dequeue_cmd(_queue *queue); + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/custom_gpio.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/custom_gpio.h new file mode 100644 index 000000000..5499a2d38 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/custom_gpio.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __CUSTOM_GPIO_H__ +#define __CUSTOM_GPIO_H___ + +#include +#include + +#ifdef PLATFORM_OS_XP +#include +#endif + +#ifdef PLATFORM_OS_CE +#include +#endif + +#ifdef PLATFORM_LINUX +#include +#endif + +typedef enum cust_gpio_modes { + WLAN_PWDN_ON, + WLAN_PWDN_OFF, + WLAN_POWER_ON, + WLAN_POWER_OFF, + WLAN_BT_PWDN_ON, + WLAN_BT_PWDN_OFF +} cust_gpio_modes_t; + +extern int rtw_wifi_gpio_init(void); +extern int rtw_wifi_gpio_deinit(void); +extern void rtw_wifi_gpio_wlan_ctrl(int onoff); + +#endif diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_conf.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_conf.h new file mode 100644 index 000000000..467862efe --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_conf.h @@ -0,0 +1,201 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __DRV_CONF_H__ +#define __DRV_CONF_H__ +#include "autoconf.h" +#include "hal_ic_cfg.h" + +#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) + +#error "Shall be Linux or Windows, but not both!\n" + +#endif + +//Older Android kernel doesn't has CONFIG_ANDROID defined, +//add this to force CONFIG_ANDROID defined +#ifdef CONFIG_PLATFORM_ANDROID +#ifndef CONFIG_ANDROID +#define CONFIG_ANDROID +#endif +#endif + +#ifdef CONFIG_ANDROID +//Some Android build will restart the UI while non-printable ascii is passed +//between java and c/c++ layer (JNI). We force CONFIG_VALIDATE_SSID +//for Android here. If you are sure there is no risk on your system about this, +//mask this macro define to support non-printable ascii ssid. +//#define CONFIG_VALIDATE_SSID + +//Android expect dbm as the rx signal strength unit +#define CONFIG_SIGNAL_DISPLAY_DBM +#endif + +/* +#if defined(CONFIG_HAS_EARLYSUSPEND) && defined (CONFIG_RESUME_IN_WORKQUEUE) + #warning "You have CONFIG_HAS_EARLYSUSPEND enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically" + #undef CONFIG_RESUME_IN_WORKQUEUE +#endif + +#if defined(CONFIG_ANDROID_POWER) && defined (CONFIG_RESUME_IN_WORKQUEUE) + #warning "You have CONFIG_ANDROID_POWER enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically" + #undef CONFIG_RESUME_IN_WORKQUEUE +#endif +*/ + +#ifdef CONFIG_RESUME_IN_WORKQUEUE //this can be removed, because there is no case for this... + #if !defined( CONFIG_WAKELOCK) && !defined(CONFIG_ANDROID_POWER) + #error "enable CONFIG_RESUME_IN_WORKQUEUE without CONFIG_WAKELOCK or CONFIG_ANDROID_POWER will suffer from the danger of wifi's unfunctionality..." + #error "If you still want to enable CONFIG_RESUME_IN_WORKQUEUE in this case, mask this preprossor checking and GOOD LUCK..." + #endif +#endif + +//About USB VENDOR REQ +#if defined(CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX) + #warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC automatically" + #define CONFIG_USB_VENDOR_REQ_MUTEX +#endif +#if defined(CONFIG_VENDOR_REQ_RETRY) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX) + #warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_VENDOR_REQ_RETRY automatically" + #define CONFIG_USB_VENDOR_REQ_MUTEX +#endif + +#if !defined(CONFIG_AP_MODE) && defined(CONFIG_DFS_MASTER) + #warning "undef CONFIG_DFS_MASTER because CONFIG_AP_MODE is not defined" + #undef CONFIG_DFS_MASTER +#endif + +#define DYNAMIC_CAMID_ALLOC + +#define RTW_SCAN_SPARSE_MIRACAST 1 +#define RTW_SCAN_SPARSE_BG 0 + +#ifndef CONFIG_RTW_HIQ_FILTER + #define CONFIG_RTW_HIQ_FILTER 1 +#endif + +#ifndef CONFIG_RTW_ADAPTIVITY_EN + #define CONFIG_RTW_ADAPTIVITY_EN 0 +#endif + +#ifndef CONFIG_RTW_ADAPTIVITY_MODE + #define CONFIG_RTW_ADAPTIVITY_MODE 0 +#endif + +#ifndef CONFIG_RTW_ADAPTIVITY_DML + #define CONFIG_RTW_ADAPTIVITY_DML 0 +#endif + +#ifndef CONFIG_RTW_ADAPTIVITY_DC_BACKOFF + #define CONFIG_RTW_ADAPTIVITY_DC_BACKOFF 2 +#endif + +#ifndef CONFIG_RTW_ADAPTIVITY_TH_L2H_INI + #define CONFIG_RTW_ADAPTIVITY_TH_L2H_INI 0 +#endif + +#ifndef CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF + #define CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF 0 +#endif + +#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_A + #define CONFIG_RTW_TARGET_TX_PWR_2G_A {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1} +#endif + +#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_B + #define CONFIG_RTW_TARGET_TX_PWR_2G_B {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1} +#endif + +#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_C + #define CONFIG_RTW_TARGET_TX_PWR_2G_C {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1} +#endif + +#ifndef CONFIG_RTW_TARGET_TX_PWR_2G_D + #define CONFIG_RTW_TARGET_TX_PWR_2G_D {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1} +#endif + +#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_A + #define CONFIG_RTW_TARGET_TX_PWR_5G_A {-1, -1, -1, -1, -1, -1, -1, -1, -1} +#endif + +#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_B + #define CONFIG_RTW_TARGET_TX_PWR_5G_B {-1, -1, -1, -1, -1, -1, -1, -1, -1} +#endif + +#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_C + #define CONFIG_RTW_TARGET_TX_PWR_5G_C {-1, -1, -1, -1, -1, -1, -1, -1, -1} +#endif + +#ifndef CONFIG_RTW_TARGET_TX_PWR_5G_D + #define CONFIG_RTW_TARGET_TX_PWR_5G_D {-1, -1, -1, -1, -1, -1, -1, -1, -1} +#endif + +#ifndef CONFIG_RTW_AMPLIFIER_TYPE_2G + #define CONFIG_RTW_AMPLIFIER_TYPE_2G 0 +#endif + +#ifndef CONFIG_RTW_AMPLIFIER_TYPE_5G + #define CONFIG_RTW_AMPLIFIER_TYPE_5G 0 +#endif + +#ifndef CONFIG_RTW_RFE_TYPE + #define CONFIG_RTW_RFE_TYPE 64 +#endif + +#ifndef CONFIG_RTW_GLNA_TYPE + #define CONFIG_RTW_GLNA_TYPE 0 +#endif + +#ifndef CONFIG_RTW_PLL_REF_CLK_SEL + #define CONFIG_RTW_PLL_REF_CLK_SEL 0x0F +#endif + +#define MACID_NUM_SW_LIMIT 32 +#define SEC_CAM_ENT_NUM_SW_LIMIT 32 + +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) + #define CONFIG_IEEE80211_BAND_5GHZ +#endif + +#ifndef RTW_DEF_MODULE_REGULATORY_CERT + #define RTW_DEF_MODULE_REGULATORY_CERT 0 +#endif + +#if RTW_DEF_MODULE_REGULATORY_CERT + /* force enable TX power by rate and TX power limit */ + #ifndef CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY + #define CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY + #endif +#endif + +/* + Mark CONFIG_DEAUTH_BEFORE_CONNECT by Arvin 2015/07/20 + If the failure of Wi-Fi connection is due to some irregular disconnection behavior (like unplug dongle, + power down etc.) in last time, we can unmark this flag to avoid some unpredictable response from AP. +*/ +/*#define CONFIG_DEAUTH_BEFORE_CONNECT */ + +/*#define CONFIG_WEXT_DONT_JOIN_BYSSID */ +//#include + + +/*#define CONFIG_DOSCAN_IN_BUSYTRAFFIC */ + +#endif // __DRV_CONF_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_types.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_types.h new file mode 100644 index 000000000..704c03238 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_types.h @@ -0,0 +1,1307 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +/*------------------------------------------------------------------------------- + + For type defines and data structure defines + +--------------------------------------------------------------------------------*/ + + +#ifndef __DRV_TYPES_H__ +#define __DRV_TYPES_H__ + +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_ARP_KEEP_ALIVE +#include +#include +#endif + +#ifdef PLATFORM_OS_XP +#include +#endif + +#ifdef PLATFORM_OS_CE +#include +#endif + +#ifdef PLATFORM_LINUX +#include +#endif + +enum _NIC_VERSION { + + RTL8711_NIC, + RTL8712_NIC, + RTL8713_NIC, + RTL8716_NIC + +}; + +typedef struct _ADAPTER _adapter, ADAPTER,*PADAPTER; + +#include +#include + +#ifdef CONFIG_80211N_HT +#include +#endif + +#ifdef CONFIG_80211AC_VHT +#include +#endif + +#ifdef CONFIG_INTEL_WIDI +#include +#endif + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_BEAMFORMING +#include +#endif + +#include +#include +#include +#include +#include +#include +#include +#include "../hal/hal_dm.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER +#include +#endif + +#include + +#ifdef CONFIG_TDLS +#include +#endif // CONFIG_TDLS + +#ifdef CONFIG_WAPI_SUPPORT +#include +#endif // CONFIG_WAPI_SUPPORT + +#ifdef CONFIG_DRVEXT_MODULE +#include +#endif // CONFIG_DRVEXT_MODULE + +#ifdef CONFIG_MP_INCLUDED +#include +#endif // CONFIG_MP_INCLUDED + +#ifdef CONFIG_BR_EXT +#include +#endif // CONFIG_BR_EXT + +#ifdef CONFIG_IOL +#include +#endif // CONFIG_IOL + +#include +#include +#include +#include + +#ifdef CONFIG_BT_COEXIST +#include +#endif // CONFIG_BT_COEXIST + +#define SPEC_DEV_ID_NONE BIT(0) +#define SPEC_DEV_ID_DISABLE_HT BIT(1) +#define SPEC_DEV_ID_ENABLE_PS BIT(2) +#define SPEC_DEV_ID_RF_CONFIG_1T1R BIT(3) +#define SPEC_DEV_ID_RF_CONFIG_2T2R BIT(4) +#define SPEC_DEV_ID_ASSIGN_IFNAME BIT(5) + +struct specific_device_id{ + + u32 flags; + + u16 idVendor; + u16 idProduct; + +}; + +struct registry_priv +{ + u8 chip_version; + u8 rfintfs; + u8 lbkmode; + u8 hci; + NDIS_802_11_SSID ssid; + u8 network_mode; //infra, ad-hoc, auto + u8 channel;//ad-hoc support requirement + u8 wireless_mode;//A, B, G, auto + u8 scan_mode;//active, passive + u8 radio_enable; + u8 preamble;//long, short, auto + u8 vrtl_carrier_sense;//Enable, Disable, Auto + u8 vcs_type;//RTS/CTS, CTS-to-self + u16 rts_thresh; + u16 frag_thresh; + u8 adhoc_tx_pwr; + u8 soft_ap; + u8 power_mgnt; + u8 ips_mode; + u8 smart_ps; + u8 usb_rxagg_mode; + u8 long_retry_lmt; + u8 short_retry_lmt; + u16 busy_thresh; + u8 ack_policy; + u8 mp_mode; +#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR) + u8 mp_customer_str; +#endif + u8 mp_dm; + u8 software_encrypt; + u8 software_decrypt; + #ifdef CONFIG_TX_EARLY_MODE + u8 early_mode; + #endif + u8 acm_method; + //UAPSD + u8 wmm_enable; + u8 uapsd_enable; + u8 uapsd_max_sp; + u8 uapsd_acbk_en; + u8 uapsd_acbe_en; + u8 uapsd_acvi_en; + u8 uapsd_acvo_en; + + WLAN_BSSID_EX dev_network; + +#ifdef CONFIG_80211N_HT + u8 ht_enable; + // 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160MHz + // 2.4G use bit 0 ~ 3, 5G use bit 4 ~ 7 + // 0x21 means enable 2.4G 40MHz & 5G 80MHz + u8 bw_mode; + u8 ampdu_enable;//for tx + u8 rx_stbc; + u8 ampdu_amsdu;//A-MPDU Supports A-MSDU is permitted + // Short GI support Bit Map + // BIT0 - 20MHz, 1: support, 0: non-support + // BIT1 - 40MHz, 1: support, 0: non-support + // BIT2 - 80MHz, 1: support, 0: non-support + // BIT3 - 160MHz, 1: support, 0: non-support + u8 short_gi; + // BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, BIT4: Enable HT LDPC Rx, BIT5: Enable HT LDPC Tx + u8 ldpc_cap; + // BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx + u8 stbc_cap; + // BIT0: Enable VHT Beamformer, BIT1: Enable VHT Beamformee, BIT4: Enable HT Beamformer, BIT5: Enable HT Beamformee + u8 beamform_cap; + u8 beamformer_rf_num; + u8 beamformee_rf_num; +#endif //CONFIG_80211N_HT + +#ifdef CONFIG_80211AC_VHT + u8 vht_enable; //0:disable, 1:enable, 2:auto + u8 ampdu_factor; + u8 vht_rate_sel; +#endif //CONFIG_80211AC_VHT + + u8 lowrate_two_xmit; + + u8 rf_config ; + u8 low_power ; + + u8 wifi_spec;// !turbo_mode + u8 special_rf_path; // 0: 2T2R ,1: only turn on path A 1T1R + char alpha2[2]; + u8 channel_plan; + u8 full_ch_in_p2p_handshake; /* 0: reply only softap channel, 1: reply full channel list*/ +#ifdef CONFIG_BT_COEXIST + u8 btcoex; + u8 bt_iso; + u8 bt_sco; + u8 bt_ampdu; + s8 ant_num; +#endif + BOOLEAN bAcceptAddbaReq; + + u8 antdiv_cfg; + u8 antdiv_type; + + u8 switch_usb3; + + u8 usbss_enable;//0:disable,1:enable + u8 hwpdn_mode;//0:disable,1:enable,2:decide by EFUSE config + u8 hwpwrp_detect;//0:disable,1:enable + + u8 hw_wps_pbc;//0:disable,1:enable + +#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE + char adaptor_info_caching_file_path[PATH_LENGTH_MAX]; +#endif + +#ifdef CONFIG_LAYER2_ROAMING + u8 max_roaming_times; // the max number driver will try to roaming +#endif + +#ifdef CONFIG_IOL + u8 fw_iol; //enable iol without other concern +#endif + +#ifdef CONFIG_80211D + u8 enable80211d; +#endif + + u8 ifname[16]; + u8 if2name[16]; + + u8 notch_filter; + +#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV + u8 force_ant;//0 normal,1 main,2 aux + u8 force_igi;//0 normal +#endif + + /* for pll reference clock selction */ + u8 pll_ref_clk_sel; + + //define for tx power adjust + u8 RegEnableTxPowerLimit; + u8 RegEnableTxPowerByRate; + u8 RegPowerBase; + u8 RegPwrTblSel; + + u8 target_tx_pwr_valid; + s8 target_tx_pwr_2g[RF_PATH_MAX][RATE_SECTION_NUM]; +#ifdef CONFIG_IEEE80211_BAND_5GHZ + s8 target_tx_pwr_5g[RF_PATH_MAX][RATE_SECTION_NUM - 1]; +#endif + + s8 TxBBSwing_2G; + s8 TxBBSwing_5G; + u8 AmplifierType_2G; + u8 AmplifierType_5G; + u8 bEn_RFE; + u8 RFE_Type; + u8 GLNA_Type; + u8 check_fw_ps; + u8 RegPwrTrimEnable; + +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + u8 load_phy_file; + u8 RegDecryptCustomFile; +#endif + +#ifdef CONFIG_MULTI_VIR_IFACES + u8 ext_iface_num;//primary/secondary iface is excluded +#endif + u8 qos_opt_enable; + + u8 hiq_filter; + u8 adaptivity_en; + u8 adaptivity_mode; + u8 adaptivity_dml; + u8 adaptivity_dc_backoff; + s8 adaptivity_th_l2h_ini; + s8 adaptivity_th_edcca_hl_diff; + + u8 boffefusemask; + BOOLEAN bFileMaskEfuse; +#ifdef CONFIG_AUTO_CHNL_SEL_NHM + u8 acs_mode; + u8 acs_auto_scan; +#endif +}; + +//For registry parameters +#define RGTRY_OFT(field) ((ULONG)FIELD_OFFSET(struct registry_priv,field)) +#define RGTRY_SZ(field) sizeof(((struct registry_priv*) 0)->field) + +#define GetRegAmplifierType2G(_Adapter) (_Adapter->registrypriv.AmplifierType_2G) +#define GetRegAmplifierType5G(_Adapter) (_Adapter->registrypriv.AmplifierType_5G) + +#define GetRegTxBBSwing_2G(_Adapter) (_Adapter->registrypriv.TxBBSwing_2G) +#define GetRegTxBBSwing_5G(_Adapter) (_Adapter->registrypriv.TxBBSwing_5G) + +#define GetRegbENRFEType(_Adapter) (_Adapter->registrypriv.bEn_RFE) +#define GetRegRFEType(_Adapter) (_Adapter->registrypriv.RFE_Type) +#define GetRegGLNAType(_Adapter) (_Adapter->registrypriv.GLNA_Type) + +#define BSSID_OFT(field) ((ULONG)FIELD_OFFSET(WLAN_BSSID_EX,field)) +#define BSSID_SZ(field) sizeof(((PWLAN_BSSID_EX) 0)->field) + +#define REGSTY_BW_2G(regsty) ((regsty)->bw_mode & 0x0F) +#define REGSTY_BW_5G(regsty) (((regsty)->bw_mode) >> 4) +#define REGSTY_IS_BW_2G_SUPPORT(regsty, bw) (REGSTY_BW_2G((regsty)) >= (bw)) +#define REGSTY_IS_BW_5G_SUPPORT(regsty, bw) (REGSTY_BW_5G((regsty)) >= (bw)) + +#define REGSTY_IS_11AC_ENABLE(regsty) ((regsty)->vht_enable != 0) +#define REGSTY_IS_11AC_AUTO(regsty) ((regsty)->vht_enable == 2) + +#ifdef CONFIG_SDIO_HCI +#include +#define INTF_DATA SDIO_DATA +#elif defined(CONFIG_GSPI_HCI) +#include +#define INTF_DATA GSPI_DATA +#elif defined(CONFIG_PCI_HCI) +#include +#endif + +#ifdef CONFIG_CONCURRENT_MODE +#define is_primary_adapter(adapter) (adapter->adapter_type == PRIMARY_ADAPTER) +#define is_vir_adapter(adapter) (adapter->adapter_type == MAX_ADAPTER) +#define get_iface_type(adapter) (adapter->iface_type) +#else +#define is_primary_adapter(adapter) (1) +#define is_vir_adapter(adapter) (0) +#define get_iface_type(adapter) (IFACE_PORT0) +#endif +#define GET_PRIMARY_ADAPTER(padapter) (((_adapter *)padapter)->dvobj->padapters[IFACE_ID0]) +#define GET_IFACE_NUMS(padapter) (((_adapter *)padapter)->dvobj->iface_nums) +#define GET_ADAPTER(padapter, iface_id) (((_adapter *)padapter)->dvobj->padapters[iface_id]) + +#define GetDefaultAdapter(padapter) padapter + +enum _IFACE_ID { + IFACE_ID0, //maping to PRIMARY_ADAPTER + IFACE_ID1, //maping to SECONDARY_ADAPTER + IFACE_ID2, + IFACE_ID3, + IFACE_ID_MAX, +}; + +#ifdef CONFIG_DBG_COUNTER + +struct rx_logs { + u32 intf_rx; + u32 intf_rx_err_recvframe; + u32 intf_rx_err_skb; + u32 intf_rx_report; + u32 core_rx; + u32 core_rx_pre; + u32 core_rx_pre_ver_err; + u32 core_rx_pre_mgmt; + u32 core_rx_pre_mgmt_err_80211w; + u32 core_rx_pre_mgmt_err; + u32 core_rx_pre_ctrl; + u32 core_rx_pre_ctrl_err; + u32 core_rx_pre_data; + u32 core_rx_pre_data_wapi_seq_err; + u32 core_rx_pre_data_wapi_key_err; + u32 core_rx_pre_data_handled; + u32 core_rx_pre_data_err; + u32 core_rx_pre_data_unknown; + u32 core_rx_pre_unknown; + u32 core_rx_enqueue; + u32 core_rx_dequeue; + u32 core_rx_post; + u32 core_rx_post_decrypt; + u32 core_rx_post_decrypt_wep; + u32 core_rx_post_decrypt_tkip; + u32 core_rx_post_decrypt_aes; + u32 core_rx_post_decrypt_wapi; + u32 core_rx_post_decrypt_hw; + u32 core_rx_post_decrypt_unknown; + u32 core_rx_post_decrypt_err; + u32 core_rx_post_defrag_err; + u32 core_rx_post_portctrl_err; + u32 core_rx_post_indicate; + u32 core_rx_post_indicate_in_oder; + u32 core_rx_post_indicate_reoder; + u32 core_rx_post_indicate_err; + u32 os_indicate; + u32 os_indicate_ap_mcast; + u32 os_indicate_ap_forward; + u32 os_indicate_ap_self; + u32 os_indicate_err; + u32 os_netif_ok; + u32 os_netif_err; +}; + +struct tx_logs { + u32 os_tx; + u32 os_tx_err_up; + u32 os_tx_err_xmit; + u32 os_tx_m2u; + u32 os_tx_m2u_ignore_fw_linked; + u32 os_tx_m2u_ignore_self; + u32 os_tx_m2u_entry; + u32 os_tx_m2u_entry_err_xmit; + u32 os_tx_m2u_entry_err_skb; + u32 os_tx_m2u_stop; + u32 core_tx; + u32 core_tx_err_pxmitframe; + u32 core_tx_err_brtx; + u32 core_tx_upd_attrib; + u32 core_tx_upd_attrib_adhoc; + u32 core_tx_upd_attrib_sta; + u32 core_tx_upd_attrib_ap; + u32 core_tx_upd_attrib_unknown; + u32 core_tx_upd_attrib_dhcp; + u32 core_tx_upd_attrib_icmp; + u32 core_tx_upd_attrib_active; + u32 core_tx_upd_attrib_err_ucast_sta; + u32 core_tx_upd_attrib_err_ucast_ap_link; + u32 core_tx_upd_attrib_err_sta; + u32 core_tx_upd_attrib_err_link; + u32 core_tx_upd_attrib_err_sec; + u32 core_tx_ap_enqueue_warn_fwstate; + u32 core_tx_ap_enqueue_warn_sta; + u32 core_tx_ap_enqueue_warn_nosta; + u32 core_tx_ap_enqueue_warn_link; + u32 core_tx_ap_enqueue_warn_trigger; + u32 core_tx_ap_enqueue_mcast; + u32 core_tx_ap_enqueue_ucast; + u32 core_tx_ap_enqueue; + u32 intf_tx; + u32 intf_tx_pending_ac; + u32 intf_tx_pending_fw_under_survey; + u32 intf_tx_pending_fw_under_linking; + u32 intf_tx_pending_xmitbuf; + u32 intf_tx_enqueue; + u32 core_tx_enqueue; + u32 core_tx_enqueue_class; + u32 core_tx_enqueue_class_err_sta; + u32 core_tx_enqueue_class_err_nosta; + u32 core_tx_enqueue_class_err_fwlink; + u32 intf_tx_direct; + u32 intf_tx_direct_err_coalesce; + u32 intf_tx_dequeue; + u32 intf_tx_dequeue_err_coalesce; + u32 intf_tx_dump_xframe; + u32 intf_tx_dump_xframe_err_txdesc; + u32 intf_tx_dump_xframe_err_port; +}; + +struct int_logs { + u32 all; + u32 err; + u32 tbdok; + u32 tbder; + u32 bcnderr; + u32 bcndma; + u32 bcndma_e; + u32 rx; + u32 rx_rdu; + u32 rx_fovw; + u32 txfovw; + u32 mgntok; + u32 highdok; + u32 bkdok; + u32 bedok; + u32 vidok; + u32 vodok; +}; + +#endif // CONFIG_DBG_COUNTER + +struct debug_priv { + u32 dbg_sdio_free_irq_error_cnt; + u32 dbg_sdio_alloc_irq_error_cnt; + u32 dbg_sdio_free_irq_cnt; + u32 dbg_sdio_alloc_irq_cnt; + u32 dbg_sdio_deinit_error_cnt; + u32 dbg_sdio_init_error_cnt; + u32 dbg_suspend_error_cnt; + u32 dbg_suspend_cnt; + u32 dbg_resume_cnt; + u32 dbg_resume_error_cnt; + u32 dbg_deinit_fail_cnt; + u32 dbg_carddisable_cnt; + u32 dbg_carddisable_error_cnt; + u32 dbg_ps_insuspend_cnt; + u32 dbg_dev_unload_inIPS_cnt; + u32 dbg_wow_leave_ps_fail_cnt; + u32 dbg_scan_pwr_state_cnt; + u32 dbg_downloadfw_pwr_state_cnt; + u32 dbg_fw_read_ps_state_fail_cnt; + u32 dbg_leave_ips_fail_cnt; + u32 dbg_leave_lps_fail_cnt; + u32 dbg_h2c_leave32k_fail_cnt; + u32 dbg_diswow_dload_fw_fail_cnt; + u32 dbg_enwow_dload_fw_fail_cnt; + u32 dbg_ips_drvopen_fail_cnt; + u32 dbg_poll_fail_cnt; + u32 dbg_rpwm_toogle_cnt; + u32 dbg_rpwm_timeout_fail_cnt; + u32 dbg_sreset_cnt; + u64 dbg_rx_fifo_last_overflow; + u64 dbg_rx_fifo_curr_overflow; + u64 dbg_rx_fifo_diff_overflow; + u64 dbg_rx_ampdu_drop_count; + u64 dbg_rx_ampdu_forced_indicate_count; + u64 dbg_rx_ampdu_loss_count; + u64 dbg_rx_dup_mgt_frame_drop_count; + u64 dbg_rx_ampdu_window_shift_cnt; + u64 dbg_rx_conflic_mac_addr_cnt; +}; + +struct rtw_traffic_statistics { + // tx statistics + u64 tx_bytes; + u64 tx_pkts; + u64 tx_drop; + u64 cur_tx_bytes; + u64 last_tx_bytes; + u32 cur_tx_tp; // Tx throughput in MBps. + + // rx statistics + u64 rx_bytes; + u64 rx_pkts; + u64 rx_drop; + u64 cur_rx_bytes; + u64 last_rx_bytes; + u32 cur_rx_tp; // Rx throughput in MBps. +}; + +#define SEC_CAP_CHK_BMC BIT0 + +#define SEC_STATUS_STA_PK_GK_CONFLICT_DIS_BMC_SEARCH BIT0 + +struct sec_cam_bmp { + u32 m0; +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 32) + u32 m1; +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 64) + u32 m2; +#endif +#if (SEC_CAM_ENT_NUM_SW_LIMIT > 96) + u32 m3; +#endif +}; + +struct cam_ctl_t { + _lock lock; + + u8 sec_cap; + u32 flags; + + u8 num; + struct sec_cam_bmp used; + + _mutex sec_cam_access_mutex; +}; + +struct sec_cam_ent { + u16 ctrl; + u8 mac[ETH_ALEN]; + u8 key[16]; +}; + +#define KEY_FMT "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x" +#define KEY_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5], \ + ((u8*)(x))[6],((u8*)(x))[7],((u8*)(x))[8],((u8*)(x))[9],((u8*)(x))[10],((u8*)(x))[11], \ + ((u8*)(x))[12],((u8*)(x))[13],((u8*)(x))[14],((u8*)(x))[15] + +struct macid_bmp { + u32 m0; +#if (MACID_NUM_SW_LIMIT > 32) + u32 m1; +#endif +#if (MACID_NUM_SW_LIMIT > 64) + u32 m2; +#endif +#if (MACID_NUM_SW_LIMIT > 96) + u32 m3; +#endif +}; + +struct macid_ctl_t { + _lock lock; + u8 num; + struct macid_bmp used; + struct macid_bmp bmc; + struct macid_bmp if_g[IFACE_ID_MAX]; + struct macid_bmp ch_g[2]; /* 2 ch concurrency */ + u8 h2c_msr[MACID_NUM_SW_LIMIT]; + struct sta_info *sta[MACID_NUM_SW_LIMIT]; +}; + +struct rf_ctl_t { + #ifdef CONFIG_DFS_MASTER + bool radar_detect_by_sta_link; + bool pre_radar_detect_by_sta_link; + bool dfs_master_enabled; + + u8 radar_detect_ch; + u8 radar_detect_bw; + u8 radar_detect_offset; + u8 pre_radar_detect_ch; + u8 pre_radar_detect_bw; + u8 pre_radar_detect_offset; + + u32 cac_end_time; + + u8 dbg_dfs_master_fake_radar_detect_cnt; + u8 dbg_dfs_master_radar_detect_trigger_non; + u8 dbg_dfs_master_choose_dfs_ch_first; + #endif +}; + +#define RTW_CAC_STOPPED 0 +#define IS_UNDER_CAC(rfctl) ((rfctl)->cac_end_time > rtw_get_current_time()) +#define IS_CAC_STOPPED(rfctl) ((rfctl)->cac_end_time == RTW_CAC_STOPPED) + +struct dvobj_priv +{ + /*-------- below is common data --------*/ + u8 chip_type; + u8 HardwareType; + u8 interface_type;/*USB,SDIO,SPI,PCI*/ + + ATOMIC_T bSurpriseRemoved; + ATOMIC_T bDriverStopped; + + s32 processing_dev_remove; + + struct debug_priv drv_dbg; + + _mutex hw_init_mutex; + _mutex h2c_fwcmd_mutex; + +#ifdef CONFIG_RTW_CUSTOMER_STR + _mutex customer_str_mutex; + struct submit_ctx *customer_str_sctx; + u8 customer_str[RTW_CUSTOMER_STR_LEN]; +#endif + + _mutex setch_mutex; + _mutex setbw_mutex; + _mutex rf_read_reg_mutex; +#ifdef CONFIG_SDIO_INDIRECT_ACCESS + _mutex sd_indirect_access_mutex; +#endif + + unsigned char oper_channel; //saved channel info when call set_channel_bw + unsigned char oper_bwmode; + unsigned char oper_ch_offset;//PRIME_CHNL_OFFSET + u32 on_oper_ch_time; + + //extend to support mulitu interface + /*padapters[IFACE_ID0] == if1 - PRIMARY_ADAPTER*/ + /*padapters[IFACE_ID1] == if2 - SECONDARY_ADAPTER*/ + _adapter *padapters[IFACE_ID_MAX]; + u8 iface_nums; // total number of ifaces used runtime + + struct macid_ctl_t macid_ctl; + + struct cam_ctl_t cam_ctl; + struct sec_cam_ent cam_cache[SEC_CAM_ENT_NUM_SW_LIMIT]; + + struct rf_ctl_t rf_ctl; + + //For 92D, DMDP have 2 interface. + u8 InterfaceNumber; + u8 NumInterfaces; + + //In /Out Pipe information + int RtInPipe[2]; + int RtOutPipe[4]; + u8 Queue2Pipe[HW_QUEUE_ENTRY];//for out pipe mapping + + u8 irq_alloc; + ATOMIC_T continual_io_error; + + ATOMIC_T disable_func; + + struct pwrctrl_priv pwrctl_priv; + + struct rtw_traffic_statistics traffic_stat; + +#if defined(CONFIG_IOCTL_CFG80211) && defined(RTW_SINGLE_WIPHY) + struct wiphy *wiphy; +#endif + +/*-------- below is for SDIO INTERFACE --------*/ + +#ifdef INTF_DATA + INTF_DATA intf_data; +#endif + +/*-------- below is for USB INTERFACE --------*/ + +#ifdef CONFIG_USB_HCI + + u8 usb_speed; // 1.1, 2.0 or 3.0 + u8 nr_endpoint; + u8 RtNumInPipes; + u8 RtNumOutPipes; + int ep_num[6]; //endpoint number + + int RegUsbSS; + + _sema usb_suspend_sema; + +#ifdef CONFIG_USB_VENDOR_REQ_MUTEX + _mutex usb_vendor_req_mutex; +#endif + +#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC + u8 * usb_alloc_vendor_req_buf; + u8 * usb_vendor_req_buf; +#endif + +#ifdef PLATFORM_WINDOWS + //related device objects + PDEVICE_OBJECT pphysdevobj;//pPhysDevObj; + PDEVICE_OBJECT pfuncdevobj;//pFuncDevObj; + PDEVICE_OBJECT pnextdevobj;//pNextDevObj; + + u8 nextdevstacksz;//unsigned char NextDeviceStackSize; //= (CHAR)CEdevice->pUsbDevObj->StackSize + 1; + + //urb for control diescriptor request + +#ifdef PLATFORM_OS_XP + struct _URB_CONTROL_DESCRIPTOR_REQUEST descriptor_urb; + PUSB_CONFIGURATION_DESCRIPTOR pconfig_descriptor;//UsbConfigurationDescriptor; +#endif + +#ifdef PLATFORM_OS_CE + WCHAR active_path[MAX_ACTIVE_REG_PATH]; // adapter regpath + USB_EXTENSION usb_extension; + + _nic_hdl pipehdls_r8192c[0x10]; +#endif + + u32 config_descriptor_len;//ULONG UsbConfigurationDescriptorLength; +#endif//PLATFORM_WINDOWS + +#ifdef PLATFORM_LINUX + struct usb_interface *pusbintf; + struct usb_device *pusbdev; +#endif//PLATFORM_LINUX + +#ifdef PLATFORM_FREEBSD + struct usb_interface *pusbintf; + struct usb_device *pusbdev; +#endif//PLATFORM_FREEBSD + +#endif//CONFIG_USB_HCI + +/*-------- below is for PCIE INTERFACE --------*/ + +#ifdef CONFIG_PCI_HCI + +#ifdef PLATFORM_LINUX + struct pci_dev *ppcidev; + + //PCI MEM map + unsigned long pci_mem_end; /* shared mem end */ + unsigned long pci_mem_start; /* shared mem start */ + + //PCI IO map + unsigned long pci_base_addr; /* device I/O address */ + + //PciBridge + struct pci_priv pcipriv; + + unsigned int irq; /* get from pci_dev.irq, store to net_device.irq */ + u16 irqline; + u8 irq_enabled; + RT_ISR_CONTENT isr_content; + _lock irq_th_lock; + + //ASPM + u8 const_pci_aspm; + u8 const_amdpci_aspm; + u8 const_hwsw_rfoff_d3; + u8 const_support_pciaspm; + // pci-e bridge */ + u8 const_hostpci_aspm_setting; + // pci-e device */ + u8 const_devicepci_aspm_setting; + u8 b_support_aspm; // If it supports ASPM, Offset[560h] = 0x40, otherwise Offset[560h] = 0x00. + u8 b_support_backdoor; + u8 bdma64; +#endif//PLATFORM_LINUX + +#endif//CONFIG_PCI_HCI +}; + +#define dvobj_to_pwrctl(dvobj) (&(dvobj->pwrctl_priv)) +#define pwrctl_to_dvobj(pwrctl) container_of(pwrctl, struct dvobj_priv, pwrctl_priv) +#define dvobj_to_macidctl(dvobj) (&(dvobj->macid_ctl)) +#define dvobj_to_regsty(dvobj) (&(dvobj->padapters[IFACE_ID0]->registrypriv)) +#if defined(CONFIG_IOCTL_CFG80211) && defined(RTW_SINGLE_WIPHY) +#define dvobj_to_wiphy(dvobj) ((dvobj)->wiphy) +#endif +#define dvobj_to_rfctl(dvobj) (&(dvobj->rf_ctl)) +#define rfctl_to_dvobj(rfctl) container_of((rfctl), struct dvobj_priv, rf_ctl) + +#ifdef PLATFORM_LINUX +static struct device *dvobj_to_dev(struct dvobj_priv *dvobj) +{ + /* todo: get interface type from dvobj and the return the dev accordingly */ +#ifdef RTW_DVOBJ_CHIP_HW_TYPE +#endif + +#ifdef CONFIG_USB_HCI + return &dvobj->pusbintf->dev; +#endif +#ifdef CONFIG_SDIO_HCI + return &dvobj->intf_data.func->dev; +#endif +#ifdef CONFIG_GSPI_HCI + return &dvobj->intf_data.func->dev; +#endif +#ifdef CONFIG_PCI_HCI + return &dvobj->ppcidev->dev; +#endif +} +#endif + +_adapter *dvobj_get_port0_adapter(struct dvobj_priv *dvobj); + +enum _IFACE_TYPE { + IFACE_PORT0, //mapping to port0 for C/D series chips + IFACE_PORT1, //mapping to port1 for C/D series chip + MAX_IFACE_PORT, +}; + +enum _ADAPTER_TYPE { + PRIMARY_ADAPTER, + SECONDARY_ADAPTER, + MAX_ADAPTER = 0xFF, +}; + +typedef enum _DRIVER_STATE{ + DRIVER_NORMAL = 0, + DRIVER_DISAPPEAR = 1, + DRIVER_REPLACE_DONGLE = 2, +}DRIVER_STATE; + +#ifdef CONFIG_INTEL_PROXIM +struct proxim { + bool proxim_support; + bool proxim_on; + + void *proximity_priv; + int (*proxim_rx)(_adapter *padapter, + union recv_frame *precv_frame); + u8 (*proxim_get_var)(_adapter* padapter, u8 type); +}; +#endif //CONFIG_INTEL_PROXIM + +#ifdef CONFIG_MAC_LOOPBACK_DRIVER +typedef struct loopbackdata +{ + _sema sema; + _thread_hdl_ lbkthread; + u8 bstop; + u32 cnt; + u16 size; + u16 txsize; + u8 txbuf[0x8000]; + u16 rxsize; + u8 rxbuf[0x8000]; + u8 msg[100]; + +}LOOPBACKDATA, *PLOOPBACKDATA; +#endif + +struct _ADAPTER{ + int DriverState;// for disable driver using module, use dongle to replace module. + int pid[3];//process id from UI, 0:wps, 1:hostapd, 2:dhcpcd + int bDongle;//build-in module or external dongle + + struct dvobj_priv *dvobj; + struct mlme_priv mlmepriv; + struct mlme_ext_priv mlmeextpriv; + struct cmd_priv cmdpriv; + struct evt_priv evtpriv; + //struct io_queue *pio_queue; + struct io_priv iopriv; + struct xmit_priv xmitpriv; + struct recv_priv recvpriv; + struct sta_priv stapriv; + struct security_priv securitypriv; + _lock security_key_mutex; // add for CONFIG_IEEE80211W, none 11w also can use + struct registry_priv registrypriv; + + struct led_priv ledpriv; + +#ifdef CONFIG_MP_INCLUDED + struct mp_priv mppriv; +#endif + +#ifdef CONFIG_DRVEXT_MODULE + struct drvext_priv drvextpriv; +#endif + +#ifdef CONFIG_AP_MODE + struct hostapd_priv *phostapdpriv; +#endif + +#ifdef CONFIG_IOCTL_CFG80211 +#ifdef CONFIG_P2P + struct cfg80211_wifidirect_info cfg80211_wdinfo; +#endif //CONFIG_P2P +#endif //CONFIG_IOCTL_CFG80211 + u32 setband; +#ifdef CONFIG_P2P + struct wifidirect_info wdinfo; +#endif //CONFIG_P2P + +#ifdef CONFIG_TDLS + struct tdls_info tdlsinfo; +#endif //CONFIG_TDLS + +#ifdef CONFIG_WAPI_SUPPORT + u8 WapiSupport; + RT_WAPI_T wapiInfo; +#endif + + +#ifdef CONFIG_WFD + struct wifi_display_info wfd_info; +#endif //CONFIG_WFD + +#ifdef CONFIG_BT_COEXIST_SOCKET_TRX + struct bt_coex_info coex_info; +#endif //CONFIG_BT_COEXIST_SOCKET_TRX + + ERROR_CODE LastError; /* <20130613, Kordan> Only the functions associated with MP records the error code by now. */ + + PVOID HalData; + u32 hal_data_sz; + struct hal_ops HalFunc; + + u32 IsrContent; + u32 ImrContent; + + u8 EepromAddressSize; + u8 bDriverIsGoingToUnload; + u8 init_adpt_in_progress; + u8 bHaltInProgress; +#ifdef CONFIG_GPIO_API + u8 pre_gpio_pin; + struct gpio_int_priv { + u8 interrupt_mode; + u8 interrupt_enable_mask; + void (*callback[8])(u8 level); + }gpiointpriv; +#endif + _thread_hdl_ cmdThread; + _thread_hdl_ evtThread; + _thread_hdl_ xmitThread; + _thread_hdl_ recvThread; + +#ifndef PLATFORM_LINUX + NDIS_STATUS (*dvobj_init)(struct dvobj_priv *dvobj); + void (*dvobj_deinit)(struct dvobj_priv *dvobj); +#endif + + u32 (*intf_init)(struct dvobj_priv *dvobj); + void (*intf_deinit)(struct dvobj_priv *dvobj); + int (*intf_alloc_irq)(struct dvobj_priv *dvobj); + void (*intf_free_irq)(struct dvobj_priv *dvobj); + + + void (*intf_start)(_adapter * adapter); + void (*intf_stop)(_adapter * adapter); + +#ifdef PLATFORM_WINDOWS + _nic_hdl hndis_adapter;//hNdisAdapter(NDISMiniportAdapterHandle); + _nic_hdl hndis_config;//hNdisConfiguration; + NDIS_STRING fw_img; + + u32 NdisPacketFilter; + u8 MCList[MAX_MCAST_LIST_NUM][6]; + u32 MCAddrCount; +#endif //end of PLATFORM_WINDOWS + + +#ifdef PLATFORM_LINUX + _nic_hdl pnetdev; + char old_ifname[IFNAMSIZ]; + + // used by rtw_rereg_nd_name related function + struct rereg_nd_name_data { + _nic_hdl old_pnetdev; + char old_ifname[IFNAMSIZ]; + u8 old_ips_mode; + u8 old_bRegUseLed; + } rereg_nd_name_priv; + + u8 ndev_unregistering; + int bup; + struct net_device_stats stats; + struct iw_statistics iwstats; + struct proc_dir_entry *dir_dev;// for proc directory + struct proc_dir_entry *dir_odm; + +#ifdef CONFIG_IOCTL_CFG80211 + struct wireless_dev *rtw_wdev; + struct rtw_wdev_priv wdev_data; + + #if !defined(RTW_SINGLE_WIPHY) + struct wiphy *wiphy; + #endif + +#endif /* CONFIG_IOCTL_CFG80211 */ + +#endif /* PLATFORM_LINUX */ + +#ifdef PLATFORM_FREEBSD + _nic_hdl pifp; + int bup; + _lock glock; +#endif //PLATFORM_FREEBSD + u8 mac_addr[ETH_ALEN]; + int net_closed; + + u8 netif_up; + + u8 bFWReady; + u8 bBTFWReady; + u8 bLinkInfoDump; + u8 bRxRSSIDisplay; + // Added by Albert 2012/10/26 + // The driver will show up the desired channel number when this flag is 1. + u8 bNotifyChannelChange; +#ifdef CONFIG_P2P + // Added by Albert 2012/12/06 + // The driver will show the current P2P status when the upper application reads it. + u8 bShowGetP2PState; +#endif +#ifdef CONFIG_AUTOSUSPEND + u8 bDisableAutosuspend; +#endif + + //pbuddy_adapter is used only in two inteface case, (iface_nums=2 in struct dvobj_priv) + //PRIMARY_ADAPTER's buddy is SECONDARY_ADAPTER + //SECONDARY_ADAPTER's buddy is PRIMARY_ADAPTER + //for iface_id > SECONDARY_ADAPTER(IFACE_ID1), refer to padapters[iface_id] in struct dvobj_priv + //and their pbuddy_adapter is PRIMARY_ADAPTER. + //for PRIMARY_ADAPTER(IFACE_ID0) can directly refer to if1 in struct dvobj_priv + _adapter *pbuddy_adapter; + +#if defined(CONFIG_CONCURRENT_MODE) + u8 isprimary; //is primary adapter or not + //notes: + // if isprimary is true, the adapter_type value is 0, iface_id is IFACE_ID0 for PRIMARY_ADAPTER + // if isprimary is false, the adapter_type value is 1, iface_id is IFACE_ID1 for SECONDARY_ADAPTER + // refer to iface_id if iface_nums>2 and isprimary is false and the adapter_type value is 0xff. + u8 adapter_type;//used only in two inteface case(PRIMARY_ADAPTER and SECONDARY_ADAPTER) . + u8 iface_type; //interface port type, it depends on HW port +#endif //CONFIG_CONCURRENT_MODE + + //extend to support multi interface + //IFACE_ID0 is equals to PRIMARY_ADAPTER + //IFACE_ID1 is equals to SECONDARY_ADAPTER + u8 iface_id; + +#ifdef CONFIG_BR_EXT + _lock br_ext_lock; + //unsigned int macclone_completed; + struct nat25_network_db_entry *nethash[NAT25_HASH_SIZE]; + int pppoe_connection_in_progress; + unsigned char pppoe_addr[MACADDRLEN]; + unsigned char scdb_mac[MACADDRLEN]; + unsigned char scdb_ip[4]; + struct nat25_network_db_entry *scdb_entry; + unsigned char br_mac[MACADDRLEN]; + unsigned char br_ip[4]; + + struct br_ext_info ethBrExtInfo; +#endif // CONFIG_BR_EXT + +#ifdef CONFIG_INTEL_PROXIM + /* intel Proximity, should be alloc mem + * in intel Proximity module and can only + * be used in intel Proximity mode */ + struct proxim proximity; +#endif //CONFIG_INTEL_PROXIM + +#ifdef CONFIG_MAC_LOOPBACK_DRIVER + PLOOPBACKDATA ploopback; +#endif + + //for debug purpose + u8 fix_rate; + u8 data_fb; /* data rate fallback, valid only when fix_rate is not 0xff */ + u8 driver_vcs_en; //Enable=1, Disable=0 driver control vrtl_carrier_sense for tx + u8 driver_vcs_type;//force 0:disable VCS, 1:RTS-CTS, 2:CTS-to-self when vcs_en=1. + u8 driver_ampdu_spacing;//driver control AMPDU Density for peer sta's rx + u8 driver_rx_ampdu_factor;//0xff: disable drv ctrl, 0:8k, 1:16k, 2:32k, 3:64k; + u8 driver_rx_ampdu_spacing; //driver control Rx AMPDU Density + u8 fix_rx_ampdu_accept; + u8 fix_rx_ampdu_size; /* 0~127, TODO:consider each sta and each TID */ + unsigned char in_cta_test; +#ifdef DBG_RX_COUNTER_DUMP + u8 dump_rx_cnt_mode;/*BIT0:drv,BIT1:mac,BIT2:phy*/ + u32 drv_rx_cnt_ok; + u32 drv_rx_cnt_crcerror; + u32 drv_rx_cnt_drop; +#endif + +#ifdef CONFIG_DBG_COUNTER + struct rx_logs rx_logs; + struct tx_logs tx_logs; + struct int_logs int_logs; +#endif +}; + +#define adapter_to_dvobj(adapter) ((adapter)->dvobj) +#define adapter_to_regsty(adapter) dvobj_to_regsty(adapter_to_dvobj((adapter))) +#define adapter_to_pwrctl(adapter) dvobj_to_pwrctl(adapter_to_dvobj((adapter))) +#define adapter_wdev_data(adapter) (&((adapter)->wdev_data)) +#if defined(RTW_SINGLE_WIPHY) +#define adapter_to_wiphy(adapter) dvobj_to_wiphy(adapter_to_dvobj(adapter)) +#else +#define adapter_to_wiphy(adapter) ((adapter)->wiphy) +#endif + +#define adapter_to_rfctl(adapter) dvobj_to_rfctl(adapter_to_dvobj((adapter))) + +#define adapter_mac_addr(adapter) (adapter->mac_addr) + +#define mlme_to_adapter(mlme) container_of((mlme), struct _ADAPTER, mlmepriv) +#define tdls_info_to_adapter(tdls) container_of((tdls), struct _ADAPTER, tdlsinfo) + +#define rtw_get_chip_type(adapter) (((PADAPTER)adapter)->dvobj->chip_type) +#define rtw_get_hw_type(adapter) (((PADAPTER)adapter)->dvobj->HardwareType) +#define rtw_get_intf_type(adapter) (((PADAPTER)adapter)->dvobj->interface_type) + +static inline void rtw_set_surprise_removed(_adapter *padapter) +{ + ATOMIC_SET(&adapter_to_dvobj(padapter)->bSurpriseRemoved, _TRUE); +} +static inline void rtw_clr_surprise_removed(_adapter *padapter) +{ + ATOMIC_SET(&adapter_to_dvobj(padapter)->bSurpriseRemoved, _FALSE); +} +static inline void rtw_set_drv_stopped(_adapter *padapter) +{ + ATOMIC_SET(&adapter_to_dvobj(padapter)->bDriverStopped, _TRUE); +} +static inline void rtw_clr_drv_stopped(_adapter *padapter) +{ + ATOMIC_SET(&adapter_to_dvobj(padapter)->bDriverStopped, _FALSE); +} +#define rtw_is_surprise_removed(padapter) (ATOMIC_READ(&adapter_to_dvobj(padapter)->bSurpriseRemoved) == _TRUE) +#define rtw_is_drv_stopped(padapter) (ATOMIC_READ(&adapter_to_dvobj(padapter)->bDriverStopped) == _TRUE) + +// +// Function disabled. +// +#define DF_TX_BIT BIT0 /*write_port_cancel*/ +#define DF_RX_BIT BIT1 /*read_port_cancel*/ +#define DF_IO_BIT BIT2 + +//#define RTW_DISABLE_FUNC(padapter, func) (ATOMIC_ADD(&adapter_to_dvobj(padapter)->disable_func, (func))) +//#define RTW_ENABLE_FUNC(padapter, func) (ATOMIC_SUB(&adapter_to_dvobj(padapter)->disable_func, (func))) +__inline static void RTW_DISABLE_FUNC(_adapter*padapter, int func_bit) +{ + int df = ATOMIC_READ(&adapter_to_dvobj(padapter)->disable_func); + df |= func_bit; + ATOMIC_SET(&adapter_to_dvobj(padapter)->disable_func, df); +} + +__inline static void RTW_ENABLE_FUNC(_adapter*padapter, int func_bit) +{ + int df = ATOMIC_READ(&adapter_to_dvobj(padapter)->disable_func); + df &= ~(func_bit); + ATOMIC_SET(&adapter_to_dvobj(padapter)->disable_func, df); +} + +#define RTW_CANNOT_RUN(padapter) \ + (rtw_is_surprise_removed(padapter) || \ + rtw_is_drv_stopped(padapter)) + +#define RTW_IS_FUNC_DISABLED(padapter, func_bit) (ATOMIC_READ(&adapter_to_dvobj(padapter)->disable_func) & (func_bit)) + +#define RTW_CANNOT_IO(padapter) \ + (rtw_is_surprise_removed(padapter) || \ + RTW_IS_FUNC_DISABLED((padapter), DF_IO_BIT)) + +#define RTW_CANNOT_RX(padapter) \ + (RTW_CANNOT_RUN(padapter) || \ + RTW_IS_FUNC_DISABLED((padapter), DF_RX_BIT)) + +#define RTW_CANNOT_TX(padapter) \ + (RTW_CANNOT_RUN(padapter) || \ + RTW_IS_FUNC_DISABLED((padapter), DF_TX_BIT)) + +#ifdef CONFIG_PNO_SUPPORT +int rtw_parse_ssid_list_tlv(char** list_str, pno_ssid_t* ssid, int max, int *bytes_left); +int rtw_dev_pno_set(struct net_device *net, pno_ssid_t* ssid, int num, + int pno_time, int pno_repeat, int pno_freq_expo_max); +#ifdef CONFIG_PNO_SET_DEBUG +void rtw_dev_pno_debug(struct net_device *net); +#endif //CONFIG_PNO_SET_DEBUG +#endif //CONFIG_PNO_SUPPORT + +// HCI Related header file +#ifdef CONFIG_USB_HCI +#include +#include +#include +#endif + +#ifdef CONFIG_SDIO_HCI +#include +#include +#include +#endif + +#ifdef CONFIG_GSPI_HCI +#include +#include +#include +#endif + +#ifdef CONFIG_PCI_HCI +#include +#include +#include +#endif + +#endif //__DRV_TYPES_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_types_ce.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_types_ce.h new file mode 100644 index 000000000..b3d35235c --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_types_ce.h @@ -0,0 +1,93 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __DRV_TYPES_CE_H__ +#define __DRV_TYPES_CE_H__ + +#include +#include + +#include + +#define MAX_ACTIVE_REG_PATH 256 + +#define MAX_MCAST_LIST_NUM 32 + + + +//for ioctl +#define MAKE_DRIVER_VERSION(_MainVer,_MinorVer) ((((u32)(_MainVer))<<16)+_MinorVer) + +#define NIC_HEADER_SIZE 14 //!< can be moved to typedef.h +#define NIC_MAX_PACKET_SIZE 1514 //!< can be moved to typedef.h +#define NIC_MAX_SEND_PACKETS 10 // max number of send packets the MiniportSendPackets function can accept, can be moved to typedef.h +#define NIC_VENDOR_DRIVER_VERSION MAKE_DRIVER_VERSION(0,001) //!< can be moved to typedef.h +#define NIC_MAX_PACKET_SIZE 1514 //!< can be moved to typedef.h + +typedef struct _MP_REG_ENTRY +{ + + NDIS_STRING RegName; // variable name text + BOOLEAN bRequired; // 1 -> required, 0 -> optional + + u8 Type; // NdisParameterInteger/NdisParameterHexInteger/NdisParameterStringle/NdisParameterMultiString + uint FieldOffset; // offset to MP_ADAPTER field + uint FieldSize; // size (in bytes) of the field + +#ifdef UNDER_AMD64 + u64 Default; +#else + u32 Default; // default value to use +#endif + + u32 Min; // minimum value allowed + u32 Max; // maximum value allowed +} MP_REG_ENTRY, *PMP_REG_ENTRY; + +#ifdef CONFIG_USB_HCI +typedef struct _USB_EXTENSION { + LPCUSB_FUNCS _lpUsbFuncs; + USB_HANDLE _hDevice; + PVOID pAdapter; + +#if 0 + USB_ENDPOINT_DESCRIPTOR _endpACLIn; + USB_ENDPOINT_DESCRIPTOR _endpACLOutHigh; + USB_ENDPOINT_DESCRIPTOR _endpACLOutNormal; + + USB_PIPE pPipeIn; + USB_PIPE pPipeOutNormal; + USB_PIPE pPipeOutHigh; +#endif + +} USB_EXTENSION, *PUSB_EXTENSION; +#endif + + +typedef struct _OCTET_STRING{ + u8 *Octet; + u16 Length; +} OCTET_STRING, *POCTET_STRING; + + + + + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_types_gspi.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_types_gspi.h new file mode 100644 index 000000000..545776b2e --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_types_gspi.h @@ -0,0 +1,56 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __DRV_TYPES_GSPI_H__ +#define __DRV_TYPES_GSPI_H__ + +// SPI Header Files +#ifdef PLATFORM_LINUX + #include + #include + #include + //#include + #include + #include + #include + #include + #include + #include + #include +#endif + + +typedef struct gspi_data +{ + u8 func_number; + + u8 tx_block_mode; + u8 rx_block_mode; + u32 block_transfer_len; + +#ifdef PLATFORM_LINUX + struct spi_device *func; + + struct workqueue_struct *priv_wq; + struct delayed_work irq_work; +#endif +} GSPI_DATA, *PGSPI_DATA; + +#endif // #ifndef __DRV_TYPES_GSPI_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_types_linux.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_types_linux.h new file mode 100644 index 000000000..db1c58569 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_types_linux.h @@ -0,0 +1,25 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __DRV_TYPES_LINUX_H__ +#define __DRV_TYPES_LINUX_H__ + + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_types_pci.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_types_pci.h new file mode 100644 index 000000000..857aaf94b --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_types_pci.h @@ -0,0 +1,273 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __DRV_TYPES_PCI_H__ +#define __DRV_TYPES_PCI_H__ + + +#ifdef PLATFORM_LINUX +#include +#endif + + +#define INTEL_VENDOR_ID 0x8086 +#define SIS_VENDOR_ID 0x1039 +#define ATI_VENDOR_ID 0x1002 +#define ATI_DEVICE_ID 0x7914 +#define AMD_VENDOR_ID 0x1022 + +#define PCI_MAX_BRIDGE_NUMBER 255 +#define PCI_MAX_DEVICES 32 +#define PCI_MAX_FUNCTION 8 + +#define PCI_CONF_ADDRESS 0x0CF8 // PCI Configuration Space Address +#define PCI_CONF_DATA 0x0CFC // PCI Configuration Space Data + +#define PCI_CLASS_BRIDGE_DEV 0x06 +#define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04 + +#define PCI_CAPABILITY_ID_PCI_EXPRESS 0x10 + +#define U1DONTCARE 0xFF +#define U2DONTCARE 0xFFFF +#define U4DONTCARE 0xFFFFFFFF + +#define PCI_VENDER_ID_REALTEK 0x10ec + +#define HAL_HW_PCI_8180_DEVICE_ID 0x8180 +#define HAL_HW_PCI_8185_DEVICE_ID 0x8185 //8185 or 8185b +#define HAL_HW_PCI_8188_DEVICE_ID 0x8188 //8185b +#define HAL_HW_PCI_8198_DEVICE_ID 0x8198 //8185b +#define HAL_HW_PCI_8190_DEVICE_ID 0x8190 //8190 +#define HAL_HW_PCI_8723E_DEVICE_ID 0x8723 //8723E +#define HAL_HW_PCI_8192_DEVICE_ID 0x8192 //8192 PCI-E +#define HAL_HW_PCI_8192SE_DEVICE_ID 0x8192 //8192 SE +#define HAL_HW_PCI_8174_DEVICE_ID 0x8174 //8192 SE +#define HAL_HW_PCI_8173_DEVICE_ID 0x8173 //8191 SE Crab +#define HAL_HW_PCI_8172_DEVICE_ID 0x8172 //8191 SE RE +#define HAL_HW_PCI_8171_DEVICE_ID 0x8171 //8191 SE Unicron +#define HAL_HW_PCI_0045_DEVICE_ID 0x0045 //8190 PCI for Ceraga +#define HAL_HW_PCI_0046_DEVICE_ID 0x0046 //8190 Cardbus for Ceraga +#define HAL_HW_PCI_0044_DEVICE_ID 0x0044 //8192e PCIE for Ceraga +#define HAL_HW_PCI_0047_DEVICE_ID 0x0047 //8192e Express Card for Ceraga +#define HAL_HW_PCI_700F_DEVICE_ID 0x700F +#define HAL_HW_PCI_701F_DEVICE_ID 0x701F +#define HAL_HW_PCI_DLINK_DEVICE_ID 0x3304 +#define HAL_HW_PCI_8188EE_DEVICE_ID 0x8179 + +#define HAL_MEMORY_MAPPED_IO_RANGE_8190PCI 0x1000 //8190 support 16 pages of IO registers +#define HAL_HW_PCI_REVISION_ID_8190PCI 0x00 +#define HAL_MEMORY_MAPPED_IO_RANGE_8192PCIE 0x4000 //8192 support 16 pages of IO registers +#define HAL_HW_PCI_REVISION_ID_8192PCIE 0x01 +#define HAL_MEMORY_MAPPED_IO_RANGE_8192SE 0x4000 //8192 support 16 pages of IO registers +#define HAL_HW_PCI_REVISION_ID_8192SE 0x10 +#define HAL_HW_PCI_REVISION_ID_8192CE 0x1 +#define HAL_MEMORY_MAPPED_IO_RANGE_8192CE 0x4000 //8192 support 16 pages of IO registers +#define HAL_HW_PCI_REVISION_ID_8192DE 0x0 +#define HAL_MEMORY_MAPPED_IO_RANGE_8192DE 0x4000 //8192 support 16 pages of IO registers + +enum pci_bridge_vendor { + PCI_BRIDGE_VENDOR_INTEL = 0x0,//0b'0000,0001 + PCI_BRIDGE_VENDOR_ATI, //= 0x02,//0b'0000,0010 + PCI_BRIDGE_VENDOR_AMD, //= 0x04,//0b'0000,0100 + PCI_BRIDGE_VENDOR_SIS ,//= 0x08,//0b'0000,1000 + PCI_BRIDGE_VENDOR_UNKNOWN, //= 0x40,//0b'0100,0000 + PCI_BRIDGE_VENDOR_MAX ,//= 0x80 +} ; + +// copy this data structor defination from MSDN SDK +typedef struct _PCI_COMMON_CONFIG { + u16 VendorID; + u16 DeviceID; + u16 Command; + u16 Status; + u8 RevisionID; + u8 ProgIf; + u8 SubClass; + u8 BaseClass; + u8 CacheLineSize; + u8 LatencyTimer; + u8 HeaderType; + u8 BIST; + + union { + struct _PCI_HEADER_TYPE_0 { + u32 BaseAddresses[6]; + u32 CIS; + u16 SubVendorID; + u16 SubSystemID; + u32 ROMBaseAddress; + u8 CapabilitiesPtr; + u8 Reserved1[3]; + u32 Reserved2; + + u8 InterruptLine; + u8 InterruptPin; + u8 MinimumGrant; + u8 MaximumLatency; + } type0; +#if 0 + struct _PCI_HEADER_TYPE_1 { + ULONG BaseAddresses[PCI_TYPE1_ADDRESSES]; + UCHAR PrimaryBusNumber; + UCHAR SecondaryBusNumber; + UCHAR SubordinateBusNumber; + UCHAR SecondaryLatencyTimer; + UCHAR IOBase; + UCHAR IOLimit; + USHORT SecondaryStatus; + USHORT MemoryBase; + USHORT MemoryLimit; + USHORT PrefetchableMemoryBase; + USHORT PrefetchableMemoryLimit; + ULONG PrefetchableMemoryBaseUpper32; + ULONG PrefetchableMemoryLimitUpper32; + USHORT IOBaseUpper; + USHORT IOLimitUpper; + ULONG Reserved2; + ULONG ExpansionROMBase; + UCHAR InterruptLine; + UCHAR InterruptPin; + USHORT BridgeControl; + } type1; + + struct _PCI_HEADER_TYPE_2 { + ULONG BaseAddress; + UCHAR CapabilitiesPtr; + UCHAR Reserved2; + USHORT SecondaryStatus; + UCHAR PrimaryBusNumber; + UCHAR CardbusBusNumber; + UCHAR SubordinateBusNumber; + UCHAR CardbusLatencyTimer; + ULONG MemoryBase0; + ULONG MemoryLimit0; + ULONG MemoryBase1; + ULONG MemoryLimit1; + USHORT IOBase0_LO; + USHORT IOBase0_HI; + USHORT IOLimit0_LO; + USHORT IOLimit0_HI; + USHORT IOBase1_LO; + USHORT IOBase1_HI; + USHORT IOLimit1_LO; + USHORT IOLimit1_HI; + UCHAR InterruptLine; + UCHAR InterruptPin; + USHORT BridgeControl; + USHORT SubVendorID; + USHORT SubSystemID; + ULONG LegacyBaseAddress; + UCHAR Reserved3[56]; + ULONG SystemControl; + UCHAR MultiMediaControl; + UCHAR GeneralStatus; + UCHAR Reserved4[2]; + UCHAR GPIO0Control; + UCHAR GPIO1Control; + UCHAR GPIO2Control; + UCHAR GPIO3Control; + ULONG IRQMuxRouting; + UCHAR RetryStatus; + UCHAR CardControl; + UCHAR DeviceControl; + UCHAR Diagnostic; + } type2; +#endif + } u; + + u8 DeviceSpecific[108]; +} PCI_COMMON_CONFIG , *PPCI_COMMON_CONFIG; + +typedef struct _RT_PCI_CAPABILITIES_HEADER { + u8 CapabilityID; + u8 Next; +} RT_PCI_CAPABILITIES_HEADER, *PRT_PCI_CAPABILITIES_HEADER; + +struct pci_priv{ + BOOLEAN pci_clk_req; + + u8 pciehdr_offset; + // PCIeCap is only differece between B-cut and C-cut. + // Configuration Space offset 72[7:4] + // 0: A/B cut + // 1: C cut and later. + u8 pcie_cap; + u8 linkctrl_reg; + + u8 busnumber; + u8 devnumber; + u8 funcnumber; + + u8 pcibridge_busnum; + u8 pcibridge_devnum; + u8 pcibridge_funcnum; + u8 pcibridge_vendor; + u16 pcibridge_vendorid; + u16 pcibridge_deviceid; + u8 pcibridge_pciehdr_offset; + u8 pcibridge_linkctrlreg; + + u8 amd_l1_patch; +}; + +typedef struct _RT_ISR_CONTENT +{ + union{ + u32 IntArray[2]; + u32 IntReg4Byte; + u16 IntReg2Byte; + }; +}RT_ISR_CONTENT, *PRT_ISR_CONTENT; + +//#define RegAddr(addr) (addr + 0xB2000000UL) +//some platform macros will def here +static inline void NdisRawWritePortUlong(u32 port, u32 val) +{ + outl(val, port); + //writel(val, (u8 *)RegAddr(port)); +} + +static inline void NdisRawWritePortUchar(u32 port, u8 val) +{ + outb(val, port); + //writeb(val, (u8 *)RegAddr(port)); +} + +static inline void NdisRawReadPortUchar(u32 port, u8 *pval) +{ + *pval = inb(port); + //*pval = readb((u8 *)RegAddr(port)); +} + +static inline void NdisRawReadPortUshort(u32 port, u16 *pval) +{ + *pval = inw(port); + //*pval = readw((u8 *)RegAddr(port)); +} + +static inline void NdisRawReadPortUlong(u32 port, u32 *pval) +{ + *pval = inl(port); + //*pval = readl((u8 *)RegAddr(port)); +} + + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_types_xp.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_types_xp.h new file mode 100644 index 000000000..2d51b1db1 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/drv_types_xp.h @@ -0,0 +1,95 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __DRV_TYPES_XP_H__ +#define __DRV_TYPES_XP_H__ + +#include +#include + + + +#define MAX_MCAST_LIST_NUM 32 + + + +//for ioctl +#define MAKE_DRIVER_VERSION(_MainVer,_MinorVer) ((((u32)(_MainVer))<<16)+_MinorVer) + +#define NIC_HEADER_SIZE 14 //!< can be moved to typedef.h +#define NIC_MAX_PACKET_SIZE 1514 //!< can be moved to typedef.h +#define NIC_MAX_SEND_PACKETS 10 // max number of send packets the MiniportSendPackets function can accept, can be moved to typedef.h +#define NIC_VENDOR_DRIVER_VERSION MAKE_DRIVER_VERSION(0,001) //!< can be moved to typedef.h +#define NIC_MAX_PACKET_SIZE 1514 //!< can be moved to typedef.h + + +#undef ON_VISTA +//added by Jackson +#ifndef ON_VISTA +// +// Bus driver versions +// + +#define SDBUS_DRIVER_VERSION_1 0x100 +#define SDBUS_DRIVER_VERSION_2 0x200 + +#define SDP_FUNCTION_TYPE 4 +#define SDP_BUS_DRIVER_VERSION 5 +#define SDP_BUS_WIDTH 6 +#define SDP_BUS_CLOCK 7 +#define SDP_BUS_INTERFACE_CONTROL 8 +#define SDP_HOST_BLOCK_LENGTH 9 +#define SDP_FUNCTION_BLOCK_LENGTH 10 +#define SDP_FN0_BLOCK_LENGTH 11 +#define SDP_FUNCTION_INT_ENABLE 12 +#endif + + +typedef struct _MP_REG_ENTRY +{ + + NDIS_STRING RegName; // variable name text + BOOLEAN bRequired; // 1 -> required, 0 -> optional + + u8 Type; // NdisParameterInteger/NdisParameterHexInteger/NdisParameterStringle/NdisParameterMultiString + uint FieldOffset; // offset to MP_ADAPTER field + uint FieldSize; // size (in bytes) of the field + +#ifdef UNDER_AMD64 + u64 Default; +#else + u32 Default; // default value to use +#endif + + u32 Min; // minimum value allowed + u32 Max; // maximum value allowed +} MP_REG_ENTRY, *PMP_REG_ENTRY; + + +typedef struct _OCTET_STRING{ + u8 *Octet; + u16 Length; +} OCTET_STRING, *POCTET_STRING; + + + + + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/ethernet.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/ethernet.h new file mode 100644 index 000000000..cadc8c1d8 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/ethernet.h @@ -0,0 +1,42 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +/*! \file */ +#ifndef __INC_ETHERNET_H +#define __INC_ETHERNET_H + +#define ETHERNET_ADDRESS_LENGTH 6 //!< Ethernet Address Length +#define ETHERNET_HEADER_SIZE 14 //!< Ethernet Header Length +#define LLC_HEADER_SIZE 6 //!< LLC Header Length +#define TYPE_LENGTH_FIELD_SIZE 2 //!< Type/Length Size +#define MINIMUM_ETHERNET_PACKET_SIZE 60 //!< Minimum Ethernet Packet Size +#define MAXIMUM_ETHERNET_PACKET_SIZE 1514 //!< Maximum Ethernet Packet Size + +#define RT_ETH_IS_MULTICAST(_pAddr) ((((UCHAR *)(_pAddr))[0]&0x01)!=0) //!< Is Multicast Address? +#define RT_ETH_IS_BROADCAST(_pAddr) ( \ + ((UCHAR *)(_pAddr))[0]==0xff && \ + ((UCHAR *)(_pAddr))[1]==0xff && \ + ((UCHAR *)(_pAddr))[2]==0xff && \ + ((UCHAR *)(_pAddr))[3]==0xff && \ + ((UCHAR *)(_pAddr))[4]==0xff && \ + ((UCHAR *)(_pAddr))[5]==0xff ) //!< Is Broadcast Address? + + +#endif // #ifndef __INC_ETHERNET_H + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/gspi_hal.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/gspi_hal.h new file mode 100644 index 000000000..758151258 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/gspi_hal.h @@ -0,0 +1,36 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __GSPI_HAL_H__ +#define __GSPI_HAL_H__ + + +void spi_int_dpc(PADAPTER padapter, u32 sdio_hisr); +u8 rtw_set_hal_ops(_adapter *padapter); + +#ifdef CONFIG_RTL8188E +void rtl8188es_set_hal_ops(PADAPTER padapter); +#endif + +#ifdef CONFIG_RTL8723B +void rtl8723bs_set_hal_ops(PADAPTER padapter); +#endif + +#endif //__GSPI_HAL_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/gspi_ops.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/gspi_ops.h new file mode 100644 index 000000000..e04c28a91 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/gspi_ops.h @@ -0,0 +1,185 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __GSPI_OPS_H__ +#define __GSPI_OPS_H__ + +/* follwing defination is based on + * GSPI spec of RTL8723, we temp + * suppose that it will be the same + * for diff chips of GSPI, if not + * we should move it to HAL folder */ +#define SPI_LOCAL_DOMAIN 0x0 +#define WLAN_IOREG_DOMAIN 0x8 +#define FW_FIFO_DOMAIN 0x4 +#define TX_HIQ_DOMAIN 0xc +#define TX_MIQ_DOMAIN 0xd +#define TX_LOQ_DOMAIN 0xe +#define RX_RXFIFO_DOMAIN 0x1f + +//IO Bus domain address mapping +#define DEFUALT_OFFSET 0x0 +#define SPI_LOCAL_OFFSET 0x10250000 +#define WLAN_IOREG_OFFSET 0x10260000 +#define FW_FIFO_OFFSET 0x10270000 +#define TX_HIQ_OFFSET 0x10310000 +#define TX_MIQ_OFFSET 0x1032000 +#define TX_LOQ_OFFSET 0x10330000 +#define RX_RXOFF_OFFSET 0x10340000 + +//SPI Local registers +#define SPI_REG_TX_CTRL 0x0000 // SPI Tx Control +#define SPI_REG_STATUS_RECOVERY 0x0004 +#define SPI_REG_INT_TIMEOUT 0x0006 +#define SPI_REG_HIMR 0x0014 // SPI Host Interrupt Mask +#define SPI_REG_HISR 0x0018 // SPI Host Interrupt Service Routine +#define SPI_REG_RX0_REQ_LEN 0x001C // RXDMA Request Length +#define SPI_REG_FREE_TXPG 0x0020 // Free Tx Buffer Page +#define SPI_REG_HCPWM1 0x0024 // HCI Current Power Mode 1 +#define SPI_REG_HCPWM2 0x0026 // HCI Current Power Mode 2 +#define SPI_REG_HTSFR_INFO 0x0030 // HTSF Informaion +#define SPI_REG_HRPWM1 0x0080 // HCI Request Power Mode 1 +#define SPI_REG_HRPWM2 0x0082 // HCI Request Power Mode 2 +#define SPI_REG_HPS_CLKR 0x0084 // HCI Power Save Clock +#define SPI_REG_HSUS_CTRL 0x0086 // SPI HCI Suspend Control +#define SPI_REG_HIMR_ON 0x0090 //SPI Host Extension Interrupt Mask Always +#define SPI_REG_HISR_ON 0x0091 //SPI Host Extension Interrupt Status Always +#define SPI_REG_CFG 0x00F0 //SPI Configuration Register + +#define SPI_TX_CTRL (SPI_REG_TX_CTRL |SPI_LOCAL_OFFSET) +#define SPI_STATUS_RECOVERY (SPI_REG_STATUS_RECOVERY |SPI_LOCAL_OFFSET) +#define SPI_INT_TIMEOUT (SPI_REG_INT_TIMEOUT |SPI_LOCAL_OFFSET) +#define SPI_HIMR (SPI_REG_HIMR |SPI_LOCAL_OFFSET) +#define SPI_HISR (SPI_REG_HISR |SPI_LOCAL_OFFSET) +#define SPI_RX0_REQ_LEN_1_BYTE (SPI_REG_RX0_REQ_LEN |SPI_LOCAL_OFFSET) +#define SPI_FREE_TXPG (SPI_REG_FREE_TXPG |SPI_LOCAL_OFFSET) + +#define SPI_HIMR_DISABLED 0 + +//SPI HIMR MASK diff with SDIO +#define SPI_HISR_RX_REQUEST BIT(0) +#define SPI_HISR_AVAL BIT(1) +#define SPI_HISR_TXERR BIT(2) +#define SPI_HISR_RXERR BIT(3) +#define SPI_HISR_TXFOVW BIT(4) +#define SPI_HISR_RXFOVW BIT(5) +#define SPI_HISR_TXBCNOK BIT(6) +#define SPI_HISR_TXBCNERR BIT(7) +#define SPI_HISR_BCNERLY_INT BIT(16) +#define SPI_HISR_ATIMEND BIT(17) +#define SPI_HISR_ATIMEND_E BIT(18) +#define SPI_HISR_CTWEND BIT(19) +#define SPI_HISR_C2HCMD BIT(20) +#define SPI_HISR_CPWM1 BIT(21) +#define SPI_HISR_CPWM2 BIT(22) +#define SPI_HISR_HSISR_IND BIT(23) +#define SPI_HISR_GTINT3_IND BIT(24) +#define SPI_HISR_GTINT4_IND BIT(25) +#define SPI_HISR_PSTIMEOUT BIT(26) +#define SPI_HISR_OCPINT BIT(27) +#define SPI_HISR_TSF_BIT32_TOGGLE BIT(29) + +#define MASK_SPI_HISR_CLEAR (SPI_HISR_TXERR |\ + SPI_HISR_RXERR |\ + SPI_HISR_TXFOVW |\ + SPI_HISR_RXFOVW |\ + SPI_HISR_TXBCNOK |\ + SPI_HISR_TXBCNERR |\ + SPI_HISR_C2HCMD |\ + SPI_HISR_CPWM1 |\ + SPI_HISR_CPWM2 |\ + SPI_HISR_HSISR_IND |\ + SPI_HISR_GTINT3_IND |\ + SPI_HISR_GTINT4_IND |\ + SPI_HISR_PSTIMEOUT |\ + SPI_HISR_OCPINT) + +#define REG_LEN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 0, 8, x)//(x<<(unsigned int)24) +#define REG_ADDR_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)//(x<<(unsigned int)16) +#define REG_DOMAIN_ID_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)//(x<<(unsigned int)0) +#define REG_FUN_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)//(x<<(unsigned int)5) +#define REG_RW_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)//(x<<(unsigned int)7) + +#define FIFO_LEN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 0, 16, x)//(x<<(unsigned int)24) +//#define FIFO_ADDR_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)//(x<<(unsigned int)16) +#define FIFO_DOMAIN_ID_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)//(x<<(unsigned int)0) +#define FIFO_FUN_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)//(x<<(unsigned int)5) +#define FIFO_RW_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)//(x<<(unsigned int)7) + + +//get status dword0 +#define GET_STATUS_PUB_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 24, 8) +#define GET_STATUS_HI_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 18, 6) +#define GET_STATUS_MID_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 12, 6) +#define GET_STATUS_LOW_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 6, 6) +#define GET_STATUS_HISR_HI6BIT(status) LE_BITS_TO_4BYTE(status, 0, 6) + +//get status dword1 +#define GET_STATUS_HISR_MID8BIT(status) LE_BITS_TO_4BYTE(status + 4, 24, 8) +#define GET_STATUS_HISR_LOW8BIT(status) LE_BITS_TO_4BYTE(status + 4, 16, 8) +#define GET_STATUS_ERROR(status) LE_BITS_TO_4BYTE(status + 4, 17, 1) +#define GET_STATUS_INT(status) LE_BITS_TO_4BYTE(status + 4, 16, 1) +#define GET_STATUS_RX_LENGTH(status) LE_BITS_TO_4BYTE(status + 4, 0, 16) + + +#define RXDESC_SIZE 24 + + +struct spi_more_data { + unsigned long more_data; + unsigned long len; +}; + +#ifdef CONFIG_RTL8188E +void rtl8188es_set_hal_ops(PADAPTER padapter); +#define set_hal_ops rtl8188es_set_hal_ops +#endif +extern void spi_set_chip_endian(PADAPTER padapter); +extern unsigned int spi_write8_endian(ADAPTER *Adapter, unsigned int addr, unsigned int buf, u32 big); +extern void spi_set_intf_ops(_adapter *padapter,struct _io_ops *pops); +extern void spi_set_chip_endian(PADAPTER padapter); +extern void InitInterrupt8723ASdio(PADAPTER padapter); +extern void InitSysInterrupt8723ASdio(PADAPTER padapter); +extern void EnableInterrupt8723ASdio(PADAPTER padapter); +extern void DisableInterrupt8723ASdio(PADAPTER padapter); +extern void spi_int_hdl(PADAPTER padapter); +extern u8 HalQueryTxBufferStatus8723ASdio(PADAPTER padapter); +#ifdef CONFIG_RTL8723B +extern void InitInterrupt8723BSdio(PADAPTER padapter); +extern void InitSysInterrupt8723BSdio(PADAPTER padapter); +extern void EnableInterrupt8723BSdio(PADAPTER padapter); +extern void DisableInterrupt8723BSdio(PADAPTER padapter); +extern u8 HalQueryTxBufferStatus8723BSdio(PADAPTER padapter); +#endif + +#ifdef CONFIG_RTL8188E +extern void InitInterrupt8188EGspi(PADAPTER padapter); +extern void EnableInterrupt8188EGspi(PADAPTER padapter); +extern void DisableInterrupt8188EGspi(PADAPTER padapter); +extern void UpdateInterruptMask8188EGspi(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR); +extern u8 HalQueryTxBufferStatus8189EGspi(PADAPTER padapter); +extern u8 HalQueryTxOQTBufferStatus8189EGspi(PADAPTER padapter); +extern void ClearInterrupt8188EGspi(PADAPTER padapter); +extern u8 CheckIPSStatus(PADAPTER padapter); +#endif // CONFIG_RTL8188E +#if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) +extern u8 RecvOnePkt(PADAPTER padapter, u32 size); +#endif // CONFIG_WOWLAN + +#endif //__GSPI_OPS_H__ diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/gspi_ops_linux.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/gspi_ops_linux.h new file mode 100644 index 000000000..6358a0fa6 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/gspi_ops_linux.h @@ -0,0 +1,24 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __SDIO_OPS_LINUX_H__ +#define __SDIO_OPS_LINUX_H__ + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/gspi_osintf.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/gspi_osintf.h new file mode 100644 index 000000000..5b57bdb66 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/gspi_osintf.h @@ -0,0 +1,31 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __SDIO_OSINTF_H__ +#define __SDIO_OSINTF_H__ + + +#ifdef PLATFORM_OS_CE +extern NDIS_STATUS ce_sd_get_dev_hdl(PADAPTER padapter); +SD_API_STATUS ce_sd_int_callback(SD_DEVICE_HANDLE hDevice, PADAPTER padapter); +extern void sd_setup_irs(PADAPTER padapter); +#endif + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/h2clbk.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/h2clbk.h new file mode 100644 index 000000000..4fa863c2d --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/h2clbk.h @@ -0,0 +1,32 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#define _H2CLBK_H_ + + +void _lbk_cmd(PADAPTER Adapter); + +void _lbk_rsp(PADAPTER Adapter); + +void _lbk_evt(IN PADAPTER Adapter); + +void h2c_event_callback(unsigned char *dev, unsigned char *pbuf); + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_btcoex.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_btcoex.h new file mode 100644 index 000000000..dd2eb84f4 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_btcoex.h @@ -0,0 +1,97 @@ +/****************************************************************************** + * + * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_BTCOEX_H__ +#define __HAL_BTCOEX_H__ + +#include + +// Some variables can't get from outsrc BT-Coex, +// so we need to save here +typedef struct _BT_COEXIST +{ + u8 bBtExist; + u8 btTotalAntNum; + u8 btChipType; + u8 bInitlized; + u8 btAntisolation; +} BT_COEXIST, *PBT_COEXIST; + +void DBG_BT_INFO(u8 *dbgmsg); + +void hal_btcoex_SetBTCoexist(PADAPTER padapter, u8 bBtExist); +u8 hal_btcoex_IsBtExist(PADAPTER padapter); +u8 hal_btcoex_IsBtDisabled(PADAPTER); +void hal_btcoex_SetChipType(PADAPTER padapter, u8 chipType); +u8 hal_btcoex_GetChipType(PADAPTER padapter); +void hal_btcoex_SetPgAntNum(PADAPTER padapter, u8 antNum); +u8 hal_btcoex_GetPgAntNum(PADAPTER padapter); +void hal_btcoex_SetSingleAntPath(PADAPTER padapter, u8 singleAntPath); + +u8 hal_btcoex_Initialize(PADAPTER padapter); +void hal_btcoex_PowerOnSetting(PADAPTER padapter); +void hal_btcoex_PreLoadFirmware(PADAPTER padapter); +void hal_btcoex_InitHwConfig(PADAPTER padapter, u8 bWifiOnly); + +void hal_btcoex_IpsNotify(PADAPTER padapter, u8 type); +void hal_btcoex_LpsNotify(PADAPTER padapter, u8 type); +void hal_btcoex_ScanNotify(PADAPTER padapter, u8 type); +void hal_btcoex_ConnectNotify(PADAPTER padapter, u8 action); +void hal_btcoex_MediaStatusNotify(PADAPTER padapter, u8 mediaStatus); +void hal_btcoex_SpecialPacketNotify(PADAPTER padapter, u8 pktType); +void hal_btcoex_IQKNotify(PADAPTER padapter, u8 state); +void hal_btcoex_BtInfoNotify(PADAPTER padapter, u8 length, u8 *tmpBuf); +void hal_btcoex_BtMpRptNotify(PADAPTER padapter, u8 length, u8 *tmpBuf); +void hal_btcoex_SuspendNotify(PADAPTER padapter, u8 state); +void hal_btcoex_HaltNotify(PADAPTER padapter); +void hal_btcoex_ScoreBoardStatusNotify(PADAPTER padapter, u8 length, u8 *tmpBuf); +void hal_btcoex_SwitchBtTRxMask(PADAPTER padapter); + +void hal_btcoex_Hanlder(PADAPTER padapter); + +s32 hal_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter); +s32 hal_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER padapter); +u32 hal_btcoex_GetAMPDUSize(PADAPTER padapter); +void hal_btcoex_SetManualControl(PADAPTER padapter, u8 bmanual); +u8 hal_btcoex_1Ant(PADAPTER padapter); +u8 hal_btcoex_IsBtControlLps(PADAPTER); +u8 hal_btcoex_IsLpsOn(PADAPTER); +u8 hal_btcoex_RpwmVal(PADAPTER); +u8 hal_btcoex_LpsVal(PADAPTER); +u32 hal_btcoex_GetRaMask(PADAPTER); +void hal_btcoex_RecordPwrMode(PADAPTER padapter, u8 *pCmdBuf, u8 cmdLen); +void hal_btcoex_DisplayBtCoexInfo(PADAPTER, u8 *pbuf, u32 bufsize); +void hal_btcoex_SetDBG(PADAPTER, u32 *pDbgModule); +u32 hal_btcoex_GetDBG(PADAPTER, u8 *pStrBuf, u32 bufSize); +u8 hal_btcoex_IncreaseScanDeviceNum(PADAPTER); +u8 hal_btcoex_IsBtLinkExist(PADAPTER); +void hal_btcoex_SetBtPatchVersion(PADAPTER,u16 btHciVer,u16 btPatchVer); +void hal_btcoex_SetHciVersion(PADAPTER, u16 hciVersion); +void hal_btcoex_SendScanNotify(PADAPTER, u8 type); +void hal_btcoex_StackUpdateProfileInfo(void); +void hal_btcoex_BTOffOnNotify(PADAPTER padapter, u8 bBTON); +void hal_btcoex_SetAntIsolationType(PADAPTER padapter, u8 anttype); +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE +int hal_btcoex_AntIsolationConfig_ParaFile(IN PADAPTER Adapter,IN char* pFileName); +int hal_btcoex_ParseAntIsolationConfigFile(PADAPTER Adapter, char* buffer); +#endif // CONFIG_LOAD_PHY_PARA_FROM_FILE +u16 hal_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data); +u16 hal_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val); +#endif // !__HAL_BTCOEX_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_com.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_com.h new file mode 100644 index 000000000..206a19359 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_com.h @@ -0,0 +1,562 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_COMMON_H__ +#define __HAL_COMMON_H__ + +#include "HalVerDef.h" +#include "hal_pg.h" +#include "hal_phy.h" +#include "hal_phy_reg.h" +#include "hal_com_reg.h" +#include "hal_com_phycfg.h" +#include "../hal/hal_com_c2h.h" + +/*------------------------------ Tx Desc definition Macro ------------------------*/ +//#pragma mark -- Tx Desc related definition. -- +//---------------------------------------------------------------------------- +//----------------------------------------------------------- +// Rate +//----------------------------------------------------------- +// CCK Rates, TxHT = 0 +#define DESC_RATE1M 0x00 +#define DESC_RATE2M 0x01 +#define DESC_RATE5_5M 0x02 +#define DESC_RATE11M 0x03 + +// OFDM Rates, TxHT = 0 +#define DESC_RATE6M 0x04 +#define DESC_RATE9M 0x05 +#define DESC_RATE12M 0x06 +#define DESC_RATE18M 0x07 +#define DESC_RATE24M 0x08 +#define DESC_RATE36M 0x09 +#define DESC_RATE48M 0x0a +#define DESC_RATE54M 0x0b + +// MCS Rates, TxHT = 1 +#define DESC_RATEMCS0 0x0c +#define DESC_RATEMCS1 0x0d +#define DESC_RATEMCS2 0x0e +#define DESC_RATEMCS3 0x0f +#define DESC_RATEMCS4 0x10 +#define DESC_RATEMCS5 0x11 +#define DESC_RATEMCS6 0x12 +#define DESC_RATEMCS7 0x13 +#define DESC_RATEMCS8 0x14 +#define DESC_RATEMCS9 0x15 +#define DESC_RATEMCS10 0x16 +#define DESC_RATEMCS11 0x17 +#define DESC_RATEMCS12 0x18 +#define DESC_RATEMCS13 0x19 +#define DESC_RATEMCS14 0x1a +#define DESC_RATEMCS15 0x1b +#define DESC_RATEMCS16 0x1C +#define DESC_RATEMCS17 0x1D +#define DESC_RATEMCS18 0x1E +#define DESC_RATEMCS19 0x1F +#define DESC_RATEMCS20 0x20 +#define DESC_RATEMCS21 0x21 +#define DESC_RATEMCS22 0x22 +#define DESC_RATEMCS23 0x23 +#define DESC_RATEMCS24 0x24 +#define DESC_RATEMCS25 0x25 +#define DESC_RATEMCS26 0x26 +#define DESC_RATEMCS27 0x27 +#define DESC_RATEMCS28 0x28 +#define DESC_RATEMCS29 0x29 +#define DESC_RATEMCS30 0x2A +#define DESC_RATEMCS31 0x2B +#define DESC_RATEVHTSS1MCS0 0x2C +#define DESC_RATEVHTSS1MCS1 0x2D +#define DESC_RATEVHTSS1MCS2 0x2E +#define DESC_RATEVHTSS1MCS3 0x2F +#define DESC_RATEVHTSS1MCS4 0x30 +#define DESC_RATEVHTSS1MCS5 0x31 +#define DESC_RATEVHTSS1MCS6 0x32 +#define DESC_RATEVHTSS1MCS7 0x33 +#define DESC_RATEVHTSS1MCS8 0x34 +#define DESC_RATEVHTSS1MCS9 0x35 +#define DESC_RATEVHTSS2MCS0 0x36 +#define DESC_RATEVHTSS2MCS1 0x37 +#define DESC_RATEVHTSS2MCS2 0x38 +#define DESC_RATEVHTSS2MCS3 0x39 +#define DESC_RATEVHTSS2MCS4 0x3A +#define DESC_RATEVHTSS2MCS5 0x3B +#define DESC_RATEVHTSS2MCS6 0x3C +#define DESC_RATEVHTSS2MCS7 0x3D +#define DESC_RATEVHTSS2MCS8 0x3E +#define DESC_RATEVHTSS2MCS9 0x3F +#define DESC_RATEVHTSS3MCS0 0x40 +#define DESC_RATEVHTSS3MCS1 0x41 +#define DESC_RATEVHTSS3MCS2 0x42 +#define DESC_RATEVHTSS3MCS3 0x43 +#define DESC_RATEVHTSS3MCS4 0x44 +#define DESC_RATEVHTSS3MCS5 0x45 +#define DESC_RATEVHTSS3MCS6 0x46 +#define DESC_RATEVHTSS3MCS7 0x47 +#define DESC_RATEVHTSS3MCS8 0x48 +#define DESC_RATEVHTSS3MCS9 0x49 +#define DESC_RATEVHTSS4MCS0 0x4A +#define DESC_RATEVHTSS4MCS1 0x4B +#define DESC_RATEVHTSS4MCS2 0x4C +#define DESC_RATEVHTSS4MCS3 0x4D +#define DESC_RATEVHTSS4MCS4 0x4E +#define DESC_RATEVHTSS4MCS5 0x4F +#define DESC_RATEVHTSS4MCS6 0x50 +#define DESC_RATEVHTSS4MCS7 0x51 +#define DESC_RATEVHTSS4MCS8 0x52 +#define DESC_RATEVHTSS4MCS9 0x53 + +#define HDATA_RATE(rate)\ +(rate == DESC_RATE1M)?"CCK_1M" :\ +(rate == DESC_RATE2M)?"CCK_2M" :\ +(rate == DESC_RATE5_5M)?"CCK5_5M" :\ +(rate == DESC_RATE11M)?"CCK_11M" :\ +(rate == DESC_RATE6M)?"OFDM_6M" :\ +(rate == DESC_RATE9M)?"OFDM_9M" :\ +(rate == DESC_RATE12M)?"OFDM_12M" :\ +(rate == DESC_RATE18M)?"OFDM_18M" :\ +(rate == DESC_RATE24M)?"OFDM_24M" :\ +(rate == DESC_RATE36M)?"OFDM_36M" :\ +(rate == DESC_RATE48M)?"OFDM_48M" :\ +(rate == DESC_RATE54M)?"OFDM_54M" :\ +(rate == DESC_RATEMCS0)?"MCS0" :\ +(rate == DESC_RATEMCS1)?"MCS1" :\ +(rate == DESC_RATEMCS2)?"MCS2" :\ +(rate == DESC_RATEMCS3)?"MCS3" :\ +(rate == DESC_RATEMCS4)?"MCS4" :\ +(rate == DESC_RATEMCS5)?"MCS5" :\ +(rate == DESC_RATEMCS6)?"MCS6" :\ +(rate == DESC_RATEMCS7)?"MCS7" :\ +(rate == DESC_RATEMCS8)?"MCS8" :\ +(rate == DESC_RATEMCS9)?"MCS9" :\ +(rate == DESC_RATEMCS10)?"MCS10" :\ +(rate == DESC_RATEMCS11)?"MCS11" :\ +(rate == DESC_RATEMCS12)?"MCS12" :\ +(rate == DESC_RATEMCS13)?"MCS13" :\ +(rate == DESC_RATEMCS14)?"MCS14" :\ +(rate == DESC_RATEMCS15)?"MCS15" :\ +(rate == DESC_RATEMCS16)?"MCS16" :\ +(rate == DESC_RATEMCS17)?"MCS17" :\ +(rate == DESC_RATEMCS18)?"MCS18" :\ +(rate == DESC_RATEMCS19)?"MCS19" :\ +(rate == DESC_RATEMCS20)?"MCS20" :\ +(rate == DESC_RATEMCS21)?"MCS21" :\ +(rate == DESC_RATEMCS22)?"MCS22" :\ +(rate == DESC_RATEMCS23)?"MCS23" :\ +(rate == DESC_RATEVHTSS1MCS0)?"VHTSS1MCS0" :\ +(rate == DESC_RATEVHTSS1MCS1)?"VHTSS1MCS1" :\ +(rate == DESC_RATEVHTSS1MCS2)?"VHTSS1MCS2" :\ +(rate == DESC_RATEVHTSS1MCS3)?"VHTSS1MCS3" :\ +(rate == DESC_RATEVHTSS1MCS4)?"VHTSS1MCS4" :\ +(rate == DESC_RATEVHTSS1MCS5)?"VHTSS1MCS5" :\ +(rate == DESC_RATEVHTSS1MCS6)?"VHTSS1MCS6" :\ +(rate == DESC_RATEVHTSS1MCS7)?"VHTSS1MCS7" :\ +(rate == DESC_RATEVHTSS1MCS8)?"VHTSS1MCS8" :\ +(rate == DESC_RATEVHTSS1MCS9)?"VHTSS1MCS9" :\ +(rate == DESC_RATEVHTSS2MCS0)?"VHTSS2MCS0" :\ +(rate == DESC_RATEVHTSS2MCS1)?"VHTSS2MCS1" :\ +(rate == DESC_RATEVHTSS2MCS2)?"VHTSS2MCS2" :\ +(rate == DESC_RATEVHTSS2MCS3)?"VHTSS2MCS3" :\ +(rate == DESC_RATEVHTSS2MCS4)?"VHTSS2MCS4" :\ +(rate == DESC_RATEVHTSS2MCS5)?"VHTSS2MCS5" :\ +(rate == DESC_RATEVHTSS2MCS6)?"VHTSS2MCS6" :\ +(rate == DESC_RATEVHTSS2MCS7)?"VHTSS2MCS7" :\ +(rate == DESC_RATEVHTSS2MCS8)?"VHTSS2MCS8" :\ +(rate == DESC_RATEVHTSS2MCS9)?"VHTSS2MCS9" :\ +(rate == DESC_RATEVHTSS3MCS0)?"VHTSS3MCS0" :\ +(rate == DESC_RATEVHTSS3MCS1)?"VHTSS3MCS1" :\ +(rate == DESC_RATEVHTSS3MCS2)?"VHTSS3MCS2" :\ +(rate == DESC_RATEVHTSS3MCS3)?"VHTSS3MCS3" :\ +(rate == DESC_RATEVHTSS3MCS4)?"VHTSS3MCS4" :\ +(rate == DESC_RATEVHTSS3MCS5)?"VHTSS3MCS5" :\ +(rate == DESC_RATEVHTSS3MCS6)?"VHTSS3MCS6" :\ +(rate == DESC_RATEVHTSS3MCS7)?"VHTSS3MCS7" :\ +(rate == DESC_RATEVHTSS3MCS8)?"VHTSS3MCS8" :\ +(rate == DESC_RATEVHTSS3MCS9)?"VHTSS3MCS9" : "UNKNOWN" + + +enum{ + UP_LINK, + DOWN_LINK, +}; +typedef enum _RT_MEDIA_STATUS { + RT_MEDIA_DISCONNECT = 0, + RT_MEDIA_CONNECT = 1 +} RT_MEDIA_STATUS; + +#define MAX_DLFW_PAGE_SIZE 4096 // @ page : 4k bytes +typedef enum _FIRMWARE_SOURCE { + FW_SOURCE_IMG_FILE = 0, + FW_SOURCE_HEADER_FILE = 1, //from header file +} FIRMWARE_SOURCE, *PFIRMWARE_SOURCE; + +typedef enum _CH_SW_USE_CASE{ + CH_SW_USE_CASE_TDLS = 0, + CH_SW_USE_CASE_MCC = 1 +} CH_SW_USE_CASE; + +// +// Queue Select Value in TxDesc +// +#define QSLT_BK 0x2//0x01 +#define QSLT_BE 0x0 +#define QSLT_VI 0x5//0x4 +#define QSLT_VO 0x7//0x6 +#define QSLT_BEACON 0x10 +#define QSLT_HIGH 0x11 +#define QSLT_MGNT 0x12 +#define QSLT_CMD 0x13 + +// BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. +//#define MAX_TX_QUEUE 9 + +#define TX_SELE_HQ BIT(0) // High Queue +#define TX_SELE_LQ BIT(1) // Low Queue +#define TX_SELE_NQ BIT(2) // Normal Queue +#define TX_SELE_EQ BIT(3) // Extern Queue + +#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0)) +#define PageNum_256(_Len) (u32)(((_Len)>>8) + ((_Len)&0xFF ? 1:0)) +#define PageNum_512(_Len) (u32)(((_Len)>>9) + ((_Len)&0x1FF ? 1:0)) +#define PageNum(_Len, _Size) (u32)(((_Len)/(_Size)) + ((_Len)&((_Size) - 1) ? 1:0)) + +struct dbg_rx_counter +{ + u32 rx_pkt_ok; + u32 rx_pkt_crc_error; + u32 rx_pkt_drop; + u32 rx_ofdm_fa; + u32 rx_cck_fa; + u32 rx_ht_fa; +}; +void rtw_dump_mac_rx_counters(_adapter* padapter,struct dbg_rx_counter *rx_counter); +void rtw_dump_phy_rx_counters(_adapter* padapter,struct dbg_rx_counter *rx_counter); +void rtw_reset_mac_rx_counters(_adapter* padapter); +void rtw_reset_phy_rx_counters(_adapter* padapter); +void rtw_reset_phy_trx_ok_counters(_adapter *padapter); + +#ifdef DBG_RX_COUNTER_DUMP +#define DUMP_DRV_RX_COUNTER BIT0 +#define DUMP_MAC_RX_COUNTER BIT1 +#define DUMP_PHY_RX_COUNTER BIT2 +#define DUMP_DRV_TRX_COUNTER_DATA BIT3 + +void rtw_dump_phy_rxcnts_preprocess(_adapter* padapter,u8 rx_cnt_mode); +void rtw_dump_rx_counters(_adapter* padapter); +#endif + +void dump_chip_info(HAL_VERSION ChipVersion); +void rtw_hal_config_rftype(PADAPTER padapter); + +#define BAND_CAP_2G BIT0 +#define BAND_CAP_5G BIT1 +#define BAND_CAP_BIT_NUM 2 + +#define BW_CAP_5M BIT0 +#define BW_CAP_10M BIT1 +#define BW_CAP_20M BIT2 +#define BW_CAP_40M BIT3 +#define BW_CAP_80M BIT4 +#define BW_CAP_160M BIT5 +#define BW_CAP_80_80M BIT6 +#define BW_CAP_BIT_NUM 7 + +#define PROTO_CAP_11B BIT0 +#define PROTO_CAP_11G BIT1 +#define PROTO_CAP_11N BIT2 +#define PROTO_CAP_11AC BIT3 +#define PROTO_CAP_BIT_NUM 4 + +#define WL_FUNC_P2P BIT0 +#define WL_FUNC_MIRACAST BIT1 +#define WL_FUNC_TDLS BIT2 +#define WL_FUNC_FTM BIT3 +#define WL_FUNC_BIT_NUM 4 + +int hal_spec_init(_adapter *adapter); +void dump_hal_spec(void *sel, _adapter *adapter); + +bool hal_chk_band_cap(_adapter *adapter, u8 cap); +bool hal_chk_bw_cap(_adapter *adapter, u8 cap); +bool hal_chk_proto_cap(_adapter *adapter, u8 cap); +bool hal_is_band_support(_adapter *adapter, u8 band); +bool hal_is_bw_support(_adapter *adapter, u8 bw); +bool hal_is_wireless_mode_support(_adapter *adapter, u8 mode); +u8 hal_largest_bw(_adapter *adapter, u8 in_bw); + +bool hal_chk_wl_func(_adapter *adapter, u8 func); + +u8 hal_com_config_channel_plan( + IN PADAPTER padapter, + IN char *hw_alpha2, + IN u8 hw_chplan, + IN char *sw_alpha2, + IN u8 sw_chplan, + IN u8 def_chplan, + IN BOOLEAN AutoLoadFail + ); + +int hal_config_macaddr(_adapter *adapter, bool autoload_fail); + +BOOLEAN +HAL_IsLegalChannel( + IN PADAPTER Adapter, + IN u32 Channel + ); + +u8 MRateToHwRate(u8 rate); + +u8 HwRateToMRate(u8 rate); + +void HalSetBrateCfg( + IN PADAPTER Adapter, + IN u8 *mBratesOS, + OUT u16 *pBrateCfg); + +BOOLEAN +Hal_MappingOutPipe( + IN PADAPTER pAdapter, + IN u8 NumOutPipe + ); + +void hal_init_macaddr(_adapter *adapter); + +void rtw_init_hal_com_default_value(PADAPTER Adapter); + +void c2h_evt_clear(_adapter *adapter); +s32 c2h_evt_read(_adapter *adapter, u8 *buf); +s32 c2h_evt_read_88xx(_adapter *adapter, u8 *buf); + +u8 rtw_hal_networktype_to_raid(_adapter *adapter, struct sta_info *psta); +u8 rtw_get_mgntframe_raid(_adapter *adapter,unsigned char network_type); +void rtw_hal_update_sta_rate_mask(PADAPTER padapter, struct sta_info *psta); + +/* access HW only */ +u32 rtw_sec_read_cam(_adapter *adapter, u8 addr); +void rtw_sec_write_cam(_adapter *adapter, u8 addr, u32 wdata); +void rtw_sec_read_cam_ent(_adapter *adapter, u8 id, u8 *ctrl, u8 *mac, u8 *key); +void rtw_sec_write_cam_ent(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key); +bool rtw_sec_read_cam_is_gk(_adapter *adapter, u8 id); + +void hw_var_port_switch(_adapter *adapter); + +void SetHwReg(PADAPTER padapter, u8 variable, u8 *val); +void GetHwReg(PADAPTER padapter, u8 variable, u8 *val); +void rtw_hal_check_rxfifo_full(_adapter *adapter); + +u8 SetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value); +u8 GetHalDefVar(_adapter *adapter, HAL_DEF_VARIABLE variable, void *value); + +BOOLEAN +eqNByte( + u8* str1, + u8* str2, + u32 num + ); + +u32 +MapCharToHexDigit( + IN char chTmp +); + +BOOLEAN +GetHexValueFromString( + IN char* szStr, + IN OUT u32* pu4bVal, + IN OUT u32* pu4bMove + ); + +BOOLEAN +GetFractionValueFromString( + IN char* szStr, + IN OUT u8* pInteger, + IN OUT u8* pFraction, + IN OUT u32* pu4bMove + ); + +BOOLEAN +IsCommentString( + IN char* szStr + ); + +BOOLEAN +ParseQualifiedString( + IN char* In, + IN OUT u32* Start, + OUT char* Out, + IN char LeftQualifier, + IN char RightQualifier + ); + +BOOLEAN +GetU1ByteIntegerFromStringInDecimal( + IN char* Str, + IN OUT u8* pInt + ); + +BOOLEAN +isAllSpaceOrTab( + u8* data, + u8 size + ); + +void linked_info_dump(_adapter *padapter,u8 benable); +#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA +void rtw_get_raw_rssi_info(void *sel, _adapter *padapter); +void rtw_store_phy_info(_adapter *padapter, union recv_frame *prframe); +void rtw_dump_raw_rssi_info(_adapter *padapter, void *sel); +#endif + +#define HWSET_MAX_SIZE 512 +#ifdef CONFIG_EFUSE_CONFIG_FILE +#define EFUSE_FILE_COLUMN_NUM 16 +u32 Hal_readPGDataFromConfigFile(PADAPTER padapter); +u32 Hal_ReadMACAddrFromFile(PADAPTER padapter, u8 *mac_addr); +#endif /* CONFIG_EFUSE_CONFIG_FILE */ + +int check_phy_efuse_tx_power_info_valid(PADAPTER padapter); +int hal_efuse_macaddr_offset(_adapter *adapter); +int Hal_GetPhyEfuseMACAddr(PADAPTER padapter, u8 *mac_addr); + +#ifdef CONFIG_RF_POWER_TRIM +void rtw_bb_rf_gain_offset(_adapter *padapter); +#endif /*CONFIG_RF_POWER_TRIM*/ + +void dm_DynamicUsbTxAgg(_adapter *padapter, u8 from_timer); +u8 rtw_hal_busagg_qsel_check(_adapter *padapter,u8 pre_qsel,u8 next_qsel); +void GetHalODMVar( + PADAPTER Adapter, + HAL_ODM_VARIABLE eVariable, + PVOID pValue1, + PVOID pValue2); +void SetHalODMVar( + PADAPTER Adapter, + HAL_ODM_VARIABLE eVariable, + PVOID pValue1, + BOOLEAN bSet); + +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR +struct noise_info +{ + u8 bPauseDIG; + u8 IGIValue; + u32 max_time;//ms + u8 chan; +}; +#endif + +void rtw_get_noise(_adapter* padapter); +u8 rtw_get_current_tx_rate(_adapter *padapter, u8 macid); +void rtw_hal_set_fw_rsvd_page(_adapter* adapter, bool finished); + +#ifdef CONFIG_TDLS +#ifdef CONFIG_TDLS_CH_SW +s32 rtw_hal_ch_sw_oper_offload(_adapter *padapter, u8 channel, u8 channel_offset, u16 bwmode); +#endif +#endif + +#ifdef CONFIG_GPIO_API +u8 rtw_hal_get_gpio(_adapter* adapter, u8 gpio_num); +int rtw_hal_set_gpio_output_value(_adapter* adapter, u8 gpio_num, bool isHigh); +int rtw_hal_config_gpio(_adapter* adapter, u8 gpio_num, bool isOutput); +int rtw_hal_register_gpio_interrupt(_adapter* adapter, int gpio_num, void(*callback)(u8 level)); +int rtw_hal_disable_gpio_interrupt(_adapter* adapter, int gpio_num); +#endif + +s8 rtw_hal_ch_sw_iqk_info_search(_adapter* padapter, u8 central_chnl, u8 bw_mode); +void rtw_hal_ch_sw_iqk_info_backup(_adapter* adapter); +void rtw_hal_ch_sw_iqk_info_restore(_adapter* padapter, u8 ch_sw_use_case); + +#ifdef CONFIG_GPIO_WAKEUP +void rtw_hal_switch_gpio_wl_ctrl(_adapter *padapter, u8 index, u8 enable); +void rtw_hal_set_output_gpio(_adapter *padapter, u8 index, u8 outputval); +#endif + +typedef enum _HAL_PHYDM_OPS { + HAL_PHYDM_DIS_ALL_FUNC, + HAL_PHYDM_FUNC_SET, + HAL_PHYDM_FUNC_CLR, + HAL_PHYDM_ABILITY_BK, + HAL_PHYDM_ABILITY_RESTORE, + HAL_PHYDM_ABILITY_SET, + HAL_PHYDM_ABILITY_GET, +} HAL_PHYDM_OPS; + + +#define DYNAMIC_FUNC_DISABLE (0x0) +u32 rtw_phydm_ability_ops(_adapter *adapter, HAL_PHYDM_OPS ops, u32 ability); + +#define rtw_phydm_func_disable_all(adapter) \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0) + +#define rtw_phydm_func_for_offchannel(adapter) \ + do { \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_DIS_ALL_FUNC, 0); \ + if (rtw_odm_adaptivity_needed(adapter)) \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ODM_BB_ADAPTIVITY); \ + } while (0) + +#define rtw_phydm_func_set(adapter, ability) \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_SET, ability) + +#define rtw_phydm_func_clr(adapter, ability) \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_FUNC_CLR, ability) + +#define rtw_phydm_ability_backup(adapter) \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_BK, 0) + +#define rtw_phydm_ability_restore(adapter) \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_RESTORE, 0) + +#define rtw_phydm_ability_set(adapter, ability) \ + rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_SET, ability) + +static inline u32 rtw_phydm_ability_get(_adapter *adapter) +{ + return rtw_phydm_ability_ops(adapter, HAL_PHYDM_ABILITY_GET, 0); +} + +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE +extern char *rtw_phy_file_path; +extern char rtw_phy_para_file_path[PATH_LENGTH_MAX]; +#define GetLineFromBuffer(buffer) strsep(&buffer, "\r\n") +#endif + +#ifdef CONFIG_FW_C2H_DEBUG +void Debug_FwC2H(PADAPTER padapter, u8 *pdata, u8 len); +#endif +/*CONFIG_FW_C2H_DEBUG*/ + +void update_IOT_info(_adapter *padapter); + +#ifdef CONFIG_AUTO_CHNL_SEL_NHM +void rtw_acs_start(_adapter *padapter, bool bStart); +#endif + +void hal_set_crystal_cap(_adapter *adapter, u8 crystal_cap); + +#ifdef CONFIG_ANTENNA_DIVERSITY +u8 rtw_hal_antdiv_before_linked(_adapter *padapter); +void rtw_hal_antdiv_rssi_compared(_adapter *padapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src); +#endif + +#endif //__HAL_COMMON_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_com_h2c.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_com_h2c.h new file mode 100644 index 000000000..4c65c7934 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_com_h2c.h @@ -0,0 +1,314 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __COMMON_H2C_H__ +#define __COMMON_H2C_H__ + +//---------------------------------------------------------------------------------------------------------// +//---------------------------------- H2C CMD DEFINITION ------------------------------------------------// +//---------------------------------------------------------------------------------------------------------// +// 88e, 8723b, 8812, 8821, 92e use the same FW code base +enum h2c_cmd{ + //Common Class: 000 + H2C_RSVD_PAGE = 0x00, + H2C_MEDIA_STATUS_RPT = 0x01, + H2C_SCAN_ENABLE = 0x02, + H2C_KEEP_ALIVE = 0x03, + H2C_DISCON_DECISION = 0x04, + H2C_PSD_OFFLOAD = 0x05, + H2C_CUSTOMER_STR_REQ = 0x06, + H2C_AP_OFFLOAD = 0x08, + H2C_BCN_RSVDPAGE = 0x09, + H2C_PROBERSP_RSVDPAGE = 0x0A, + H2C_FCS_RSVDPAGE = 0x10, + H2C_FCS_INFO = 0x11, + H2C_AP_WOW_GPIO_CTRL = 0x13, + H2C_CHNL_SWITCH_OPER_OFFLOAD = 0x1C, + + //PoweSave Class: 001 + H2C_SET_PWR_MODE = 0x20, + H2C_PS_TUNING_PARA = 0x21, + H2C_PS_TUNING_PARA2 = 0x22, + H2C_P2P_LPS_PARAM = 0x23, + H2C_P2P_PS_OFFLOAD = 0x24, + H2C_PS_SCAN_ENABLE = 0x25, + H2C_SAP_PS_ = 0x26, + H2C_INACTIVE_PS_ = 0x27, //Inactive_PS + H2C_FWLPS_IN_IPS_ = 0x28, + + //Dynamic Mechanism Class: 010 + H2C_MACID_CFG = 0x40, + H2C_TXBF = 0x41, + H2C_RSSI_SETTING = 0x42, + H2C_AP_REQ_TXRPT = 0x43, + H2C_INIT_RATE_COLLECT = 0x44, + H2C_IQ_CALIBRATION = 0x45, + + H2C_RA_MASK_3SS = 0x46,/* for 8814A */ + H2C_RA_PARA_ADJUST = 0x47,/* CONFIG_RA_DBG_CMD */ + H2C_DYNAMIC_TX_PATH = 0x48,/* for 8814A */ + + H2C_FW_TRACE_EN = 0x49, + + //BT Class: 011 + H2C_B_TYPE_TDMA = 0x60, + H2C_BT_INFO = 0x61, + H2C_FORCE_BT_TXPWR = 0x62, + H2C_BT_IGNORE_WLANACT = 0x63, + H2C_DAC_SWING_VALUE = 0x64, + H2C_ANT_SEL_RSV = 0x65, + H2C_WL_OPMODE = 0x66, + H2C_BT_MP_OPER = 0x67, + H2C_BT_CONTROL = 0x68, + H2C_BT_WIFI_CTRL = 0x69, + H2C_BT_FW_PATCH = 0x6A, + + //WOWLAN Class: 100 + H2C_WOWLAN = 0x80, + H2C_REMOTE_WAKE_CTRL = 0x81, + H2C_AOAC_GLOBAL_INFO = 0x82, + H2C_AOAC_RSVD_PAGE = 0x83, + H2C_AOAC_RSVD_PAGE2 = 0x84, + H2C_D0_SCAN_OFFLOAD_CTRL = 0x85, + H2C_D0_SCAN_OFFLOAD_INFO = 0x86, + H2C_CHNL_SWITCH_OFFLOAD = 0x87, + H2C_AOAC_RSVDPAGE3 = 0x88, + H2C_P2P_OFFLOAD_RSVD_PAGE = 0x8A, + H2C_P2P_OFFLOAD = 0x8B, + + H2C_RESET_TSF = 0xC0, + H2C_BCNHWSEQ = 0xC2, + H2C_CUSTOMER_STR_W1 = 0xC6, + H2C_CUSTOMER_STR_W2 = 0xC7, + H2C_CUSTOMER_STR_W3 = 0xC8, + H2C_MAXID, +}; + +#define H2C_INACTIVE_PS_LEN 3 +#define H2C_RSVDPAGE_LOC_LEN 5 +#define H2C_MEDIA_STATUS_RPT_LEN 3 +#define H2C_KEEP_ALIVE_CTRL_LEN 2 +#define H2C_DISCON_DECISION_LEN 3 +#define H2C_AP_OFFLOAD_LEN 3 +#define H2C_AP_WOW_GPIO_CTRL_LEN 4 +#define H2C_AP_PS_LEN 2 +#define H2C_PWRMODE_LEN 7 +#define H2C_PSTUNEPARAM_LEN 4 +#define H2C_MACID_CFG_LEN 7 +#define H2C_BTMP_OPER_LEN 5 +#define H2C_WOWLAN_LEN 5 +#define H2C_REMOTE_WAKE_CTRL_LEN 3 +#define H2C_AOAC_GLOBAL_INFO_LEN 2 +#define H2C_AOAC_RSVDPAGE_LOC_LEN 7 +#define H2C_SCAN_OFFLOAD_CTRL_LEN 4 +#define H2C_BT_FW_PATCH_LEN 6 +#define H2C_RSSI_SETTING_LEN 4 +#define H2C_AP_REQ_TXRPT_LEN 2 +#define H2C_FORCE_BT_TXPWR_LEN 3 +#define H2C_BCN_RSVDPAGE_LEN 5 +#define H2C_PROBERSP_RSVDPAGE_LEN 5 +#define H2C_P2PRSVDPAGE_LOC_LEN 5 +#define H2C_P2P_OFFLOAD_LEN 3 + +#define eqMacAddr(a,b) ( ((a)[0]==(b)[0] && (a)[1]==(b)[1] && (a)[2]==(b)[2] && (a)[3]==(b)[3] && (a)[4]==(b)[4] && (a)[5]==(b)[5]) ? 1:0 ) +#define cpMacAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3],(des)[4]=(src)[4],(des)[5]=(src)[5]) +#define cpIpAddr(des,src) ((des)[0]=(src)[0],(des)[1]=(src)[1],(des)[2]=(src)[2],(des)[3]=(src)[3]) + +//_RSVDPAGE_LOC_CMD_0x00 +#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value)SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) + +//_MEDIA_STATUS_RPT_PARM_CMD_0x01 +#define SET_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value)) +#define SET_H2CCMD_MSRRPT_PARM_MACID_IND(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 1, 1, (__Value)) +#define SET_H2CCMD_MSRRPT_PARM_MIRACAST(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 2, 1, (__Value)) +#define SET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 3, 1, (__Value)) +#define SET_H2CCMD_MSRRPT_PARM_ROLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 4, 4, (__Value)) +#define SET_H2CCMD_MSRRPT_PARM_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 1, 0, 8, (__Value)) +#define SET_H2CCMD_MSRRPT_PARM_MACID_END(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)) + 2, 0, 8, (__Value)) + +#define GET_H2CCMD_MSRRPT_PARM_OPMODE(__pH2CCmd) LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 0, 1) +#define GET_H2CCMD_MSRRPT_PARM_MIRACAST(__pH2CCmd) LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 2, 1) +#define GET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK(__pH2CCmd) LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 3, 1) +#define GET_H2CCMD_MSRRPT_PARM_ROLE(__pH2CCmd) LE_BITS_TO_1BYTE(((u8 *)(__pH2CCmd)), 4, 4) + +#define H2C_MSR_ROLE_RSVD 0 +#define H2C_MSR_ROLE_STA 1 +#define H2C_MSR_ROLE_AP 2 +#define H2C_MSR_ROLE_GC 3 +#define H2C_MSR_ROLE_GO 4 +#define H2C_MSR_ROLE_TDLS 5 +#define H2C_MSR_ROLE_ADHOC 6 +#define H2C_MSR_ROLE_MAX 7 + +extern const char * const _h2c_msr_role_str[]; +#define h2c_msr_role_str(role) (((role) >= H2C_MSR_ROLE_MAX) ? _h2c_msr_role_str[H2C_MSR_ROLE_MAX] : _h2c_msr_role_str[(role)]) + +#define H2C_MSR_FMT "%s %s%s" +#define H2C_MSR_ARG(h2c_msr) \ + GET_H2CCMD_MSRRPT_PARM_OPMODE((h2c_msr)) ? " C" : "", \ + h2c_msr_role_str(GET_H2CCMD_MSRRPT_PARM_ROLE((h2c_msr))), \ + GET_H2CCMD_MSRRPT_PARM_MIRACAST((h2c_msr)) ? (GET_H2CCMD_MSRRPT_PARM_MIRACAST_SINK((h2c_msr)) ? " MSINK" : " MSRC") : "" + +s32 rtw_hal_set_FwMediaStatusRpt_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, bool macid_ind, u8 macid_end); +s32 rtw_hal_set_FwMediaStatusRpt_single_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid); +s32 rtw_hal_set_FwMediaStatusRpt_range_cmd(_adapter *adapter, bool opmode, bool miracast, bool miracast_sink, u8 role, u8 macid, u8 macid_end); + +//_KEEP_ALIVE_CMD_0x03 +#define SET_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) +#define SET_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) + +//_DISCONNECT_DECISION_CMD_0x04 +#define SET_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) +#define SET_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value) + +#ifdef CONFIG_RTW_CUSTOMER_STR +#define RTW_CUSTOMER_STR_LEN 16 +#define RTW_CUSTOMER_STR_FMT "%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x" +#define RTW_CUSTOMER_STR_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5], \ + ((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9], ((u8 *)(x))[10], ((u8 *)(x))[11], \ + ((u8 *)(x))[12], ((u8 *)(x))[13], ((u8 *)(x))[14], ((u8 *)(x))[15] + +/* H2C_CUSTOMER_STR_REQ 0x06 */ +#define H2C_CUSTOMER_STR_REQ_LEN 1 +#define SET_H2CCMD_CUSTOMER_STR_REQ_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value)) +s32 rtw_hal_h2c_customer_str_req(_adapter *adapter); +s32 rtw_hal_customer_str_read(_adapter *adapter, u8 *cs); + +/* H2C_CUSTOMER_STR_W1 0xC6 */ +#define H2C_CUSTOMER_STR_W1_LEN 7 +#define SET_H2CCMD_CUSTOMER_STR_W1_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value)) +#define H2CCMD_CUSTOMER_STR_W1_BYTE0(__pH2CCmd) (((u8 *)(__pH2CCmd)) + 1) + +/* H2C_CUSTOMER_STR_W2 0xC7 */ +#define H2C_CUSTOMER_STR_W2_LEN 7 +#define SET_H2CCMD_CUSTOMER_STR_W2_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value)) +#define H2CCMD_CUSTOMER_STR_W2_BYTE6(__pH2CCmd) (((u8 *)(__pH2CCmd)) + 1) + +/* H2C_CUSTOMER_STR_W3 0xC8 */ +#define H2C_CUSTOMER_STR_W3_LEN 5 +#define SET_H2CCMD_CUSTOMER_STR_W3_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(((u8 *)(__pH2CCmd)), 0, 1, (__Value)) +#define H2CCMD_CUSTOMER_STR_W3_BYTE12(__pH2CCmd) (((u8 *)(__pH2CCmd)) + 1) +s32 rtw_hal_h2c_customer_str_write(_adapter *adapter, const u8 *cs); +s32 rtw_hal_customer_str_write(_adapter *adapter, const u8 *cs); +#endif /* CONFIG_RTW_CUSTOMER_STR */ + +//_AP_Offload 0x08 +#define SET_H2CCMD_AP_WOWLAN_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +//_BCN_RsvdPage 0x09 +#define SET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_BCN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +//_Probersp_RsvdPage 0x0a +#define SET_H2CCMD_AP_WOWLAN_RSVDPAGE_LOC_ProbeRsp(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +//_Probersp_RsvdPage 0x13 +#define SET_H2CCMD_AP_WOW_GPIO_CTRL_INDEX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value) +#define SET_H2CCMD_AP_WOW_GPIO_CTRL_C2H_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value) +#define SET_H2CCMD_AP_WOW_GPIO_CTRL_PLUS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value) +#define SET_H2CCMD_AP_WOW_GPIO_CTRL_HIGH_ACTIVE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value) +#define SET_H2CCMD_AP_WOW_GPIO_CTRL_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value) +#define SET_H2CCMD_AP_WOW_GPIO_CTRL_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_H2CCMD_AP_WOW_GPIO_CTRL_C2H_DURATION(__pH2CCmd, __Value)SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +//_AP_PS 0x26 +#define SET_H2CCMD_AP_WOW_PS_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_H2CCMD_AP_WOW_PS_32K_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_H2CCMD_AP_WOW_PS_RF(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) +#define SET_H2CCMD_AP_WOW_PS_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) + +// _WoWLAN PARAM_CMD_0x80 +#define SET_H2CCMD_WOWLAN_FUNC_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_H2CCMD_WOWLAN_PATTERN_MATCH_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_H2CCMD_WOWLAN_MAGIC_PKT_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) +#define SET_H2CCMD_WOWLAN_UNICAST_PKT_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value) +#define SET_H2CCMD_WOWLAN_ALL_PKT_DROP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value) +#define SET_H2CCMD_WOWLAN_GPIO_ACTIVE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value) +#define SET_H2CCMD_WOWLAN_REKEY_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value) +#define SET_H2CCMD_WOWLAN_DISCONNECT_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value) +#define SET_H2CCMD_WOWLAN_GPIONUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 7, __Value) +#define SET_H2CCMD_WOWLAN_DATAPIN_WAKE_UP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 7, 1, __Value) +#define SET_H2CCMD_WOWLAN_GPIO_DURATION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_H2CCMD_WOWLAN_GPIO_PULSE_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 1, __Value) +#define SET_H2CCMD_WOWLAN_GPIO_PULSE_COUNT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 1, 7, __Value) +#define SET_H2CCMD_WOWLAN_LOWPR_RX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 1, __Value) +#define SET_H2CCMD_WOWLAN_CHANGE_UNIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 2, 1, __Value) +// _REMOTE_WAKEUP_CMD_0x81 +#define SET_H2CCMD_REMOTE_WAKECTRL_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_H2CCMD_REMOTE_WAKE_CTRL_NDP_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) +#define SET_H2CCMD_REMOTE_WAKE_CTRL_GTK_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value) +#define SET_H2CCMD_REMOTE_WAKE_CTRL_NLO_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value) +#define SET_H2CCMD_REMOTE_WAKE_CTRL_FW_UNICAST_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 7, 1, __Value) +#define SET_H2CCMD_REMOTE_WAKE_CTRL_P2P_OFFLAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 1, __Value) +#define SET_H2CCMD_REMOTE_WAKE_CTRL_NBNS_FILTER_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 2, 1, __Value) +#define SET_H2CCMD_REMOTE_WAKE_CTRL_ARP_ACTION(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 1, __Value) +#define SET_H2CCMD_REMOTE_WAKE_CTRL_FW_PARSING_UNTIL_WAKEUP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 4, 1, __Value) + +// AOAC_GLOBAL_INFO_0x82 +#define SET_H2CCMD_AOAC_GLOBAL_INFO_PAIRWISE_ENC_ALG(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_H2CCMD_AOAC_GLOBAL_INFO_GROUP_ENC_ALG(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) + +// AOAC_RSVDPAGE_LOC_0x83 +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_REMOTE_WAKE_CTRL_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value) +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_ARP_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NEIGHBOR_ADV(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) +#ifdef CONFIG_GTK_OL +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_GTK_EXT_MEM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) +#endif //CONFIG_GTK_OL +#ifdef CONFIG_PNO_SUPPORT +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_NLO_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 0, 8, __Value) +#endif + +#ifdef CONFIG_PNO_SUPPORT +// D0_Scan_Offload_Info_0x86 +#define SET_H2CCMD_AOAC_NLO_FUN_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 3, 1, __Value) +#define SET_H2CCMD_AOAC_NLO_IPS_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd), 4, 1, __Value) +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_PROBE_PACKET(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_SCAN_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_H2CCMD_AOAC_RSVDPAGE_LOC_SSID_INFO(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#endif //CONFIG_PNO_SUPPORT + + +/* CHNL_SWITCH_OPER_OFFLOAD_0x1C */ +#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_CH_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 0, 2, __Value) +#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_40M_SC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 2, 3, __Value) +#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_BW_80M_SC(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 1, 5, 3, __Value) +#define SET_H2CCMD_CH_SW_OPER_OFFLOAD_RFE_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd) + 2, 0, 4, __Value) +//---------------------------------------------------------------------------------------------------------// +//------------------------------------------- Structure --------------------------------------------------// +//---------------------------------------------------------------------------------------------------------// +typedef struct _RSVDPAGE_LOC { + u8 LocProbeRsp; + u8 LocPsPoll; + u8 LocNullData; + u8 LocQosNull; + u8 LocBTQosNull; + u8 LocApOffloadBCN; +} RSVDPAGE_LOC, *PRSVDPAGE_LOC; + +#endif +void dump_TX_FIFO(PADAPTER padapter, u8 page_num, u16 page_size); +u8 rtw_hal_set_fw_media_status_cmd(_adapter* adapter, u8 mstatus, u8 macid); diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_com_led.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_com_led.h new file mode 100644 index 000000000..b764b5018 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_com_led.h @@ -0,0 +1,397 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_COMMON_LED_H_ +#define __HAL_COMMON_LED_H_ + + +#define MSECS(t) (HZ * ((t) / 1000) + (HZ * ((t) % 1000)) / 1000) + +//================================================================================ +// LED Behavior Constant. +//================================================================================ +// Default LED behavior. +// +#define LED_BLINK_NORMAL_INTERVAL 100 +#define LED_BLINK_SLOWLY_INTERVAL 200 +#define LED_BLINK_LONG_INTERVAL 400 +#define LED_INITIAL_INTERVAL 1800 + +// LED Customerization + +//NETTRONIX +#define LED_BLINK_NORMAL_INTERVAL_NETTRONIX 100 +#define LED_BLINK_SLOWLY_INTERVAL_NETTRONIX 2000 + +//PORNET +#define LED_BLINK_SLOWLY_INTERVAL_PORNET 1000 +#define LED_BLINK_NORMAL_INTERVAL_PORNET 100 +#define LED_BLINK_FAST_INTERVAL_BITLAND 30 + +//AzWave. +#define LED_CM2_BLINK_ON_INTERVAL 250 +#define LED_CM2_BLINK_OFF_INTERVAL 4750 +#define LED_CM8_BLINK_OFF_INTERVAL 3750 //for QMI + +//RunTop +#define LED_RunTop_BLINK_INTERVAL 300 + +//ALPHA +#define LED_BLINK_NO_LINK_INTERVAL_ALPHA 1000 +#define LED_BLINK_NO_LINK_INTERVAL_ALPHA_500MS 500 //add by ylb 20121012 for customer led for alpha +#define LED_BLINK_LINK_INTERVAL_ALPHA 500 //500 +#define LED_BLINK_SCAN_INTERVAL_ALPHA 180 //150 +#define LED_BLINK_FASTER_INTERVAL_ALPHA 50 +#define LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA 5000 + +// 111122 by hpfan: Customized for Xavi +#define LED_CM11_BLINK_INTERVAL 300 +#define LED_CM11_LINK_ON_INTERVEL 3000 + +//Netgear +#define LED_BLINK_LINK_INTERVAL_NETGEAR 500 +#define LED_BLINK_LINK_SLOWLY_INTERVAL_NETGEAR 1000 + +#define LED_WPS_BLINK_OFF_INTERVAL_NETGEAR 100 +#define LED_WPS_BLINK_ON_INTERVAL_NETGEAR 500 + +//Belkin AC950 +#define LED_BLINK_LINK_INTERVAL_ON_BELKIN 200 +#define LED_BLINK_LINK_INTERVAL_OFF_BELKIN 100 +#define LED_BLINK_ERROR_INTERVAL_BELKIN 100 + +//by chiyokolin for Azurewave +#define LED_CM12_BLINK_INTERVAL_5Mbps 160 +#define LED_CM12_BLINK_INTERVAL_10Mbps 80 +#define LED_CM12_BLINK_INTERVAL_20Mbps 50 +#define LED_CM12_BLINK_INTERVAL_40Mbps 40 +#define LED_CM12_BLINK_INTERVAL_80Mbps 30 +#define LED_CM12_BLINK_INTERVAL_MAXMbps 25 + +//Dlink +#define LED_BLINK_NO_LINK_INTERVAL 1000 +#define LED_BLINK_LINK_IDEL_INTERVAL 100 + +#define LED_BLINK_SCAN_ON_INTERVAL 30 +#define LED_BLINK_SCAN_OFF_INTERVAL 300 + +#define LED_WPS_BLINK_ON_INTERVAL_DLINK 30 +#define LED_WPS_BLINK_OFF_INTERVAL_DLINK 300 +#define LED_WPS_BLINK_LINKED_ON_INTERVAL_DLINK 5000 + +//================================================================================ +// LED object. +//================================================================================ + +typedef enum _LED_CTL_MODE{ + LED_CTL_POWER_ON = 1, + LED_CTL_LINK = 2, + LED_CTL_NO_LINK = 3, + LED_CTL_TX = 4, + LED_CTL_RX = 5, + LED_CTL_SITE_SURVEY = 6, + LED_CTL_POWER_OFF = 7, + LED_CTL_START_TO_LINK = 8, + LED_CTL_START_WPS = 9, + LED_CTL_STOP_WPS = 10, + LED_CTL_START_WPS_BOTTON = 11, //added for runtop + LED_CTL_STOP_WPS_FAIL = 12, //added for ALPHA + LED_CTL_STOP_WPS_FAIL_OVERLAP = 13, //added for BELKIN + LED_CTL_CONNECTION_NO_TRANSFER = 14, +}LED_CTL_MODE; + +typedef enum _LED_STATE{ + LED_UNKNOWN = 0, + RTW_LED_ON = 1, + RTW_LED_OFF = 2, + LED_BLINK_NORMAL = 3, + LED_BLINK_SLOWLY = 4, + LED_BLINK_POWER_ON = 5, + LED_BLINK_SCAN = 6, // LED is blinking during scanning period, the # of times to blink is depend on time for scanning. + LED_BLINK_NO_LINK = 7, // LED is blinking during no link state. + LED_BLINK_StartToBlink = 8, // Customzied for Sercomm Printer Server case + LED_BLINK_TXRX = 9, + LED_BLINK_WPS = 10, // LED is blinkg during WPS communication + LED_BLINK_WPS_STOP = 11, //for ALPHA + LED_BLINK_WPS_STOP_OVERLAP = 12, //for BELKIN + LED_BLINK_RUNTOP = 13, // Customized for RunTop + LED_BLINK_CAMEO = 14, + LED_BLINK_XAVI = 15, + LED_BLINK_ALWAYS_ON = 16, + LED_BLINK_LINK_IN_PROCESS = 17, //Customized for Belkin AC950 + LED_BLINK_AUTH_ERROR = 18, //Customized for Belkin AC950 + LED_BLINK_Azurewave_5Mbps = 19, + LED_BLINK_Azurewave_10Mbps = 20, + LED_BLINK_Azurewave_20Mbps = 21, + LED_BLINK_Azurewave_40Mbps = 22, + LED_BLINK_Azurewave_80Mbps = 23, + LED_BLINK_Azurewave_MAXMbps = 24, + LED_BLINK_LINK_IDEL = 25, + LED_BLINK_WPS_LINKED = 26, +}LED_STATE; + +typedef enum _LED_PIN{ + LED_PIN_GPIO0, + LED_PIN_LED0, + LED_PIN_LED1, + LED_PIN_LED2 +}LED_PIN; + + +//================================================================================ +// PCIE LED Definition. +//================================================================================ +#ifdef CONFIG_PCI_HCI +typedef enum _LED_STRATEGY_PCIE{ + SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option. + SW_LED_MODE1, // SW control for PCI Express + SW_LED_MODE2, // SW control for Cameo. + SW_LED_MODE3, // SW contorl for RunTop. + SW_LED_MODE4, // SW control for Netcore + SW_LED_MODE5, //added by vivi, for led new mode, DLINK + SW_LED_MODE6, //added by vivi, for led new mode, PRONET + SW_LED_MODE7, //added by chiyokolin, for Lenovo, PCI Express Minicard Spec Rev.1.2 spec + SW_LED_MODE8, //added by chiyokolin, for QMI + SW_LED_MODE9, //added by chiyokolin, for BITLAND-LENOVO, PCI Express Minicard Spec Rev.1.1 + SW_LED_MODE10, //added by chiyokolin, for Edimax-ASUS + SW_LED_MODE11, //added by hpfan, for Xavi + SW_LED_MODE12, //added by chiyokolin, for Azurewave + HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes) +}LED_STRATEGY_PCIE, *PLED_STRATEGY_PCIE; + +typedef struct _LED_PCIE{ + PADAPTER padapter; + + LED_PIN LedPin; // Identify how to implement this SW led. + + LED_STATE CurrLedState; // Current LED state. + BOOLEAN bLedOn; // TRUE if LED is ON, FALSE if LED is OFF. + + BOOLEAN bLedBlinkInProgress; // TRUE if it is blinking, FALSE o.w.. + BOOLEAN bLedWPSBlinkInProgress; // TRUE if it is blinking, FALSE o.w.. + + BOOLEAN bLedSlowBlinkInProgress;//added by vivi, for led new mode + u32 BlinkTimes; // Number of times to toggle led state for blinking. + LED_STATE BlinkingLedState; // Next state for blinking, either LED_ON or LED_OFF are. + + _timer BlinkTimer; // Timer object for led blinking. +} LED_PCIE, *PLED_PCIE; + +typedef struct _LED_PCIE LED_DATA, *PLED_DATA; +typedef enum _LED_STRATEGY_PCIE LED_STRATEGY, *PLED_STRATEGY; + +VOID +LedControlPCIE( + IN PADAPTER Adapter, + IN LED_CTL_MODE LedAction + ); + +VOID +gen_RefreshLedState( + IN PADAPTER Adapter); + +//================================================================================ +// USB LED Definition. +//================================================================================ +#elif defined(CONFIG_USB_HCI) + +#define IS_LED_WPS_BLINKING(_LED_USB) (((PLED_USB)_LED_USB)->CurrLedState==LED_BLINK_WPS \ + || ((PLED_USB)_LED_USB)->CurrLedState==LED_BLINK_WPS_STOP \ + || ((PLED_USB)_LED_USB)->bLedWPSBlinkInProgress) + +#define IS_LED_BLINKING(_LED_USB) (((PLED_USB)_LED_USB)->bLedWPSBlinkInProgress \ + ||((PLED_USB)_LED_USB)->bLedScanBlinkInProgress) + + +typedef enum _LED_STRATEGY_USB{ + SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option. + SW_LED_MODE1, // 2 LEDs, through LED0 and LED1. For ALPHA. + SW_LED_MODE2, // SW control 1 LED via GPIO0, customized for AzWave 8187 minicard. + SW_LED_MODE3, // SW control 1 LED via GPIO0, customized for Sercomm Printer Server case. + SW_LED_MODE4, //for Edimax / Belkin + SW_LED_MODE5, //for Sercomm / Belkin + SW_LED_MODE6, //for 88CU minicard, porting from ce SW_LED_MODE7 + SW_LED_MODE7, //for Netgear special requirement + SW_LED_MODE8, //for LC + SW_LED_MODE9, //for Belkin AC950 + SW_LED_MODE10, //for Netgear A6200V2 + SW_LED_MODE11, //for Edimax / ASUS + SW_LED_MODE12, //for WNC/NEC + SW_LED_MODE13, //for Netgear A6100, 8811Au + SW_LED_MODE14, //for Buffalo, DNI, 8811Au + SW_LED_MODE15, //for DLINK, 8811Au/8812AU + HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes, see MAC.CONFIG1 for details.) +}LED_STRATEGY_USB, *PLED_STRATEGY_USB; + + +typedef struct _LED_USB{ + PADAPTER padapter; + + LED_PIN LedPin; // Identify how to implement this SW led. + + LED_STATE CurrLedState; // Current LED state. + BOOLEAN bLedOn; // TRUE if LED is ON, FALSE if LED is OFF. + + BOOLEAN bSWLedCtrl; + + BOOLEAN bLedBlinkInProgress; // TRUE if it is blinking, FALSE o.w.. + // ALPHA, added by chiyoko, 20090106 + BOOLEAN bLedNoLinkBlinkInProgress; + BOOLEAN bLedLinkBlinkInProgress; + BOOLEAN bLedStartToLinkBlinkInProgress; + BOOLEAN bLedScanBlinkInProgress; + BOOLEAN bLedWPSBlinkInProgress; + + u32 BlinkTimes; // Number of times to toggle led state for blinking. + u8 BlinkCounter; //Added for turn off overlap led after blinking a while, by page, 20120821 + LED_STATE BlinkingLedState; // Next state for blinking, either LED_ON or LED_OFF are. + + _timer BlinkTimer; // Timer object for led blinking. + + _workitem BlinkWorkItem; // Workitem used by BlinkTimer to manipulate H/W to blink LED.' +} LED_USB, *PLED_USB; + +typedef struct _LED_USB LED_DATA, *PLED_DATA; +typedef enum _LED_STRATEGY_USB LED_STRATEGY, *PLED_STRATEGY; + +VOID +LedControlUSB( + IN PADAPTER Adapter, + IN LED_CTL_MODE LedAction + ); + + +//================================================================================ +// SDIO LED Definition. +//================================================================================ +#elif defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + +#define IS_LED_WPS_BLINKING(_LED_SDIO) (((PLED_SDIO)_LED_SDIO)->CurrLedState==LED_BLINK_WPS \ + || ((PLED_SDIO)_LED_SDIO)->CurrLedState==LED_BLINK_WPS_STOP \ + || ((PLED_SDIO)_LED_SDIO)->bLedWPSBlinkInProgress) + +#define IS_LED_BLINKING(_LED_SDIO) (((PLED_SDIO)_LED_SDIO)->bLedWPSBlinkInProgress \ + ||((PLED_SDIO)_LED_SDIO)->bLedScanBlinkInProgress) + + +typedef enum _LED_STRATEGY_SDIO{ + SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option. + SW_LED_MODE1, // 2 LEDs, through LED0 and LED1. For ALPHA. + SW_LED_MODE2, // SW control 1 LED via GPIO0, customized for AzWave 8187 minicard. + SW_LED_MODE3, // SW control 1 LED via GPIO0, customized for Sercomm Printer Server case. + SW_LED_MODE4, //for Edimax / Belkin + SW_LED_MODE5, //for Sercomm / Belkin + SW_LED_MODE6, //for 88CU minicard, porting from ce SW_LED_MODE7 + HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes, see MAC.CONFIG1 for details.) +}LED_STRATEGY_SDIO, *PLED_STRATEGY_SDIO; + +typedef struct _LED_SDIO{ + PADAPTER padapter; + + LED_PIN LedPin; // Identify how to implement this SW led. + + LED_STATE CurrLedState; // Current LED state. + BOOLEAN bLedOn; // TRUE if LED is ON, FALSE if LED is OFF. + + BOOLEAN bSWLedCtrl; + + BOOLEAN bLedBlinkInProgress; // TRUE if it is blinking, FALSE o.w.. + // ALPHA, added by chiyoko, 20090106 + BOOLEAN bLedNoLinkBlinkInProgress; + BOOLEAN bLedLinkBlinkInProgress; + BOOLEAN bLedStartToLinkBlinkInProgress; + BOOLEAN bLedScanBlinkInProgress; + BOOLEAN bLedWPSBlinkInProgress; + + u32 BlinkTimes; // Number of times to toggle led state for blinking. + LED_STATE BlinkingLedState; // Next state for blinking, either LED_ON or LED_OFF are. + + _timer BlinkTimer; // Timer object for led blinking. + + _workitem BlinkWorkItem; // Workitem used by BlinkTimer to manipulate H/W to blink LED. +} LED_SDIO, *PLED_SDIO; + +typedef struct _LED_SDIO LED_DATA, *PLED_DATA; +typedef enum _LED_STRATEGY_SDIO LED_STRATEGY, *PLED_STRATEGY; + +VOID +LedControlSDIO( + IN PADAPTER Adapter, + IN LED_CTL_MODE LedAction + ); + +#endif + +struct led_priv{ + /* add for led controll */ + LED_DATA SwLed0; + LED_DATA SwLed1; + LED_DATA SwLed2; + LED_STRATEGY LedStrategy; + u8 bRegUseLed; + void (*LedControlHandler)(_adapter *padapter, LED_CTL_MODE LedAction); + void (*SwLedOn)(_adapter *padapter, PLED_DATA pLed); + void (*SwLedOff)(_adapter *padapter, PLED_DATA pLed); + /* add for led controll */ +}; + +#ifdef CONFIG_SW_LED +#define rtw_led_control(adapter, LedAction) \ + do { \ + if((adapter)->ledpriv.LedControlHandler) \ + (adapter)->ledpriv.LedControlHandler((adapter), (LedAction)); \ + } while(0) +#else //CONFIG_SW_LED +#define rtw_led_control(adapter, LedAction) +#endif //CONFIG_SW_LED + +#define SwLedOn(adapter, pLed) \ + do { \ + if((adapter)->ledpriv.SwLedOn) \ + (adapter)->ledpriv.SwLedOn((adapter), (pLed)); \ + } while(0) + +#define SwLedOff(adapter, pLed) \ + do { \ + if((adapter)->ledpriv.SwLedOff) \ + (adapter)->ledpriv.SwLedOff((adapter), (pLed)); \ + } while(0) + +void BlinkTimerCallback(void *data); +void BlinkWorkItemCallback(_workitem *work); + +void ResetLedStatus(PLED_DATA pLed); + +void +InitLed( + _adapter *padapter, + PLED_DATA pLed, + LED_PIN LedPin + ); + +void +DeInitLed( + PLED_DATA pLed + ); + +//hal... +extern void BlinkHandler(PLED_DATA pLed); + +#endif //__RTW_LED_H_ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_com_phycfg.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_com_phycfg.h new file mode 100644 index 000000000..f3633550b --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_com_phycfg.h @@ -0,0 +1,303 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_COM_PHYCFG_H__ +#define __HAL_COM_PHYCFG_H__ + +#define PathA 0x0 // Useless +#define PathB 0x1 +#define PathC 0x2 +#define PathD 0x3 + +typedef enum _RF_TX_NUM { + RF_1TX = 0, + RF_2TX, + RF_3TX, + RF_4TX, + RF_MAX_TX_NUM, + RF_TX_NUM_NONIMPLEMENT, +} RF_TX_NUM; + +#define MAX_POWER_INDEX 0x3F + +typedef enum _REGULATION_TXPWR_LMT { + TXPWR_LMT_FCC = 0, + TXPWR_LMT_MKK = 1, + TXPWR_LMT_ETSI = 2, + TXPWR_LMT_WW = 3, + + TXPWR_LMT_MAX_REGULATION_NUM = 4 +} REGULATION_TXPWR_LMT; + +#define TX_PWR_LMT_REF_VHT_FROM_HT BIT0 +#define TX_PWR_LMT_REF_HT_FROM_VHT BIT1 + +/*------------------------------Define structure----------------------------*/ +typedef struct _BB_REGISTER_DEFINITION{ + u32 rfintfs; // set software control: + // 0x870~0x877[8 bytes] + + u32 rfintfo; // output data: + // 0x860~0x86f [16 bytes] + + u32 rfintfe; // output enable: + // 0x860~0x86f [16 bytes] + + u32 rf3wireOffset; // LSSI data: + // 0x840~0x84f [16 bytes] + + u32 rfHSSIPara2; // wire parameter control2 : + // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] + + u32 rfLSSIReadBack; //LSSI RF readback data SI mode + // 0x8a0~0x8af [16 bytes] + + u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B + +}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T; + + +//---------------------------------------------------------------------- +u8 +PHY_GetTxPowerByRateBase( + IN PADAPTER Adapter, + IN u8 Band, + IN u8 RfPath, + IN u8 TxNum, + IN RATE_SECTION RateSection + ); + +#ifdef TX_POWER_BY_RATE_OLD +u8 +PHY_GetRateSectionIndexOfTxPowerByRate( + IN PADAPTER pAdapter, + IN u32 RegAddr, + IN u32 BitMask + ); +#endif /* TX_POWER_BY_RATE_OLD */ + +VOID +PHY_GetRateValuesOfTxPowerByRate( + IN PADAPTER pAdapter, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Value, + OUT u8 *Rate, + OUT s8 *PwrByRateVal, + OUT u8 *RateNum + ); + +u8 +PHY_GetRateIndexOfTxPowerByRate( + IN u8 Rate + ); + +VOID +PHY_SetTxPowerIndexByRateSection( + IN PADAPTER pAdapter, + IN u8 RFPath, + IN u8 Channel, + IN u8 RateSection + ); + +s8 +_PHY_GetTxPowerByRate( + IN PADAPTER pAdapter, + IN u8 Band, + IN u8 RFPath, + IN u8 TxNum, + IN u8 RateIndex + ); + +s8 +PHY_GetTxPowerByRate( + IN PADAPTER pAdapter, + IN u8 Band, + IN u8 RFPath, + IN u8 TxNum, + IN u8 RateIndex + ); + +VOID +PHY_SetTxPowerByRate( + IN PADAPTER pAdapter, + IN u8 Band, + IN u8 RFPath, + IN u8 TxNum, + IN u8 Rate, + IN s8 Value + ); + +VOID +PHY_SetTxPowerLevelByPath( + IN PADAPTER Adapter, + IN u8 channel, + IN u8 path + ); + +VOID +PHY_SetTxPowerIndexByRateArray( + IN PADAPTER pAdapter, + IN u8 RFPath, + IN CHANNEL_WIDTH BandWidth, + IN u8 Channel, + IN u8* Rates, + IN u8 RateArraySize + ); + +VOID +PHY_InitTxPowerByRate( + IN PADAPTER pAdapter + ); + +VOID +PHY_StoreTxPowerByRate( + IN PADAPTER pAdapter, + IN u32 Band, + IN u32 RfPath, + IN u32 TxNum, + IN u32 RegAddr, + IN u32 BitMask, + IN u32 Data + ); + +VOID +PHY_TxPowerByRateConfiguration( + IN PADAPTER pAdapter + ); + +u8 +PHY_GetTxPowerIndexBase( + IN PADAPTER pAdapter, + IN u8 RFPath, + IN u8 Rate, + IN CHANNEL_WIDTH BandWidth, + IN u8 Channel, + OUT PBOOLEAN bIn24G + ); + +s8 +PHY_GetTxPowerLimit( + IN PADAPTER Adapter, + IN u32 RegPwrTblSel, + IN BAND_TYPE Band, + IN CHANNEL_WIDTH Bandwidth, + IN u8 RfPath, + IN u8 DataRate, + IN u8 Channel + ); + +VOID +PHY_ConvertTxPowerLimitToPowerIndex( + IN PADAPTER Adapter + ); + +VOID +PHY_InitTxPowerLimit( + IN PADAPTER Adapter + ); + +s8 +PHY_GetTxPowerTrackingOffset( + PADAPTER pAdapter, + u8 Rate, + u8 RFPath + ); + +u8 +PHY_GetTxPowerIndex( + IN PADAPTER pAdapter, + IN u8 RFPath, + IN u8 Rate, + IN CHANNEL_WIDTH BandWidth, + IN u8 Channel + ); + +VOID +PHY_SetTxPowerIndex( + IN PADAPTER pAdapter, + IN u32 PowerIndex, + IN u8 RFPath, + IN u8 Rate + ); + +bool phy_is_tx_power_limit_needed(_adapter *adapter); +bool phy_is_tx_power_by_rate_needed(_adapter *adapter); +int phy_load_tx_power_by_rate(_adapter *adapter, u8 chk_file); +int phy_load_tx_power_limit(_adapter *adapter, u8 chk_file); +void phy_load_tx_power_ext_info(_adapter *adapter, u8 chk_file); +void phy_reload_tx_power_ext_info(_adapter *adapter); +void phy_reload_default_tx_power_ext_info(_adapter *adapter); + +void dump_tx_power_ext_info(void *sel, _adapter *adapter); +void dump_target_tx_power(void *sel, _adapter *adapter); +void dump_tx_power_by_rate(void *sel, _adapter *adapter); +void dump_tx_power_limit(void *sel, _adapter *adapter); + +int rtw_get_phy_file_path(_adapter *adapter, const char *file_name); + +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE +#define MAC_FILE_FW_NIC "FW_NIC.bin" +#define MAC_FILE_FW_WW_IMG "FW_WoWLAN.bin" +#define PHY_FILE_MAC_REG "MAC_REG.txt" + +#define PHY_FILE_AGC_TAB "AGC_TAB.txt" +#define PHY_FILE_PHY_REG "PHY_REG.txt" +#define PHY_FILE_PHY_REG_MP "PHY_REG_MP.txt" +#define PHY_FILE_PHY_REG_PG "PHY_REG_PG.txt" + +#define PHY_FILE_RADIO_A "RadioA.txt" +#define PHY_FILE_RADIO_B "RadioB.txt" +#define PHY_FILE_RADIO_C "RadioC.txt" +#define PHY_FILE_RADIO_D "RadioD.txt" +#define PHY_FILE_TXPWR_TRACK "TxPowerTrack.txt" +#define PHY_FILE_TXPWR_LMT "TXPWR_LMT.txt" + +#define PHY_FILE_WIFI_ANT_ISOLATION "wifi_ant_isolation.txt" + +#define MAX_PARA_FILE_BUF_LEN 25600 + +#define LOAD_MAC_PARA_FILE BIT0 +#define LOAD_BB_PARA_FILE BIT1 +#define LOAD_BB_PG_PARA_FILE BIT2 +#define LOAD_BB_MP_PARA_FILE BIT3 +#define LOAD_RF_PARA_FILE BIT4 +#define LOAD_RF_TXPWR_TRACK_PARA_FILE BIT5 +#define LOAD_RF_TXPWR_LMT_PARA_FILE BIT6 + +int phy_ConfigMACWithParaFile(IN PADAPTER Adapter, IN char* pFileName); + +int phy_ConfigBBWithParaFile(IN PADAPTER Adapter, IN char* pFileName, IN u32 ConfigType); + +int phy_ConfigBBWithPgParaFile(IN PADAPTER Adapter, IN const char *pFileName); + +int phy_ConfigBBWithMpParaFile(IN PADAPTER Adapter, IN char* pFileName); + +int PHY_ConfigRFWithParaFile(IN PADAPTER Adapter, IN char* pFileName, IN u8 eRFPath); + +int PHY_ConfigRFWithTxPwrTrackParaFile(IN PADAPTER Adapter, IN char* pFileName); + +int PHY_ConfigRFWithPowerLimitTableParaFile(IN PADAPTER Adapter, IN const char *pFileName); + +void phy_free_filebuf_mask(_adapter *padapter, u8 mask); +void phy_free_filebuf(_adapter *padapter); +#endif /* CONFIG_LOAD_PHY_PARA_FROM_FILE */ + +#endif /* __HAL_COMMON_H__ */ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_com_reg.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_com_reg.h new file mode 100644 index 000000000..2ff3b2199 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_com_reg.h @@ -0,0 +1,1784 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_COMMON_REG_H__ +#define __HAL_COMMON_REG_H__ + + +#define MAC_ADDR_LEN 6 + +#define HAL_NAV_UPPER_UNIT 128 // micro-second + +// 8188E PKT_BUFF_ACCESS_CTRL value +#define TXPKT_BUF_SELECT 0x69 +#define RXPKT_BUF_SELECT 0xA5 +#define DISABLE_TRXPKT_BUF_ACCESS 0x0 + +//============================================================ +// +//============================================================ + +//----------------------------------------------------- +// +// 0x0000h ~ 0x00FFh System Configuration +// +//----------------------------------------------------- +#define REG_SYS_ISO_CTRL 0x0000 +#define REG_SYS_FUNC_EN 0x0002 +#define REG_APS_FSMCO 0x0004 +#define REG_SYS_CLKR 0x0008 +#define REG_SYS_CLK_CTRL REG_SYS_CLKR +#define REG_9346CR 0x000A +#define REG_SYS_EEPROM_CTRL 0x000A +#define REG_EE_VPD 0x000C +#define REG_AFE_MISC 0x0010 +#define REG_SPS0_CTRL 0x0011 +#define REG_SPS0_CTRL_6 0x0016 +#define REG_POWER_OFF_IN_PROCESS 0x0017 +#define REG_SPS_OCP_CFG 0x0018 +#define REG_RSV_CTRL 0x001C +#define REG_RF_CTRL 0x001F +#define REG_LDOA15_CTRL 0x0020 +#define REG_LDOV12D_CTRL 0x0021 +#define REG_LDOHCI12_CTRL 0x0022 +#define REG_LPLDO_CTRL 0x0023 +#define REG_AFE_XTAL_CTRL 0x0024 +#define REG_AFE_LDO_CTRL 0x0027 // 1.5v for 8188EE test chip, 1.4v for MP chip +#define REG_AFE_PLL_CTRL 0x0028 +#define REG_MAC_PHY_CTRL 0x002c //for 92d, DMDP,SMSP,DMSP contrl +#define REG_APE_PLL_CTRL_EXT 0x002c +#define REG_EFUSE_CTRL 0x0030 +#define REG_EFUSE_TEST 0x0034 +#define REG_PWR_DATA 0x0038 +#define REG_CAL_TIMER 0x003C +#define REG_ACLK_MON 0x003E +#define REG_GPIO_MUXCFG 0x0040 +#define REG_GPIO_IO_SEL 0x0042 +#define REG_MAC_PINMUX_CFG 0x0043 +#define REG_GPIO_PIN_CTRL 0x0044 +#define REG_GPIO_INTM 0x0048 +#define REG_LEDCFG0 0x004C +#define REG_LEDCFG1 0x004D +#define REG_LEDCFG2 0x004E +#define REG_LEDCFG3 0x004F +#define REG_FSIMR 0x0050 +#define REG_FSISR 0x0054 +#define REG_HSIMR 0x0058 +#define REG_HSISR 0x005c +#define REG_GPIO_PIN_CTRL_2 0x0060 // RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. +#define REG_GPIO_IO_SEL_2 0x0062 // RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. +#define REG_MULTI_FUNC_CTRL 0x0068 // RTL8723 WIFI/BT/GPS Multi-Function control source. +#define REG_GSSR 0x006c +#define REG_AFE_XTAL_CTRL_EXT 0x0078 //RTL8188E +#define REG_XCK_OUT_CTRL 0x007c //RTL8188E +#define REG_MCUFWDL 0x0080 +#define REG_WOL_EVENT 0x0081 //RTL8188E +#define REG_MCUTSTCFG 0x0084 +#define REG_FDHM0 0x0088 +#define REG_HOST_SUSP_CNT 0x00BC // RTL8192C Host suspend counter on FPGA platform +#define REG_SYSTEM_ON_CTRL 0x00CC // For 8723AE Reset after S3 +#define REG_EFUSE_ACCESS 0x00CF // Efuse access protection for RTL8723 +#define REG_BIST_SCAN 0x00D0 +#define REG_BIST_RPT 0x00D4 +#define REG_BIST_ROM_RPT 0x00D8 +#define REG_USB_SIE_INTF 0x00E0 +#define REG_PCIE_MIO_INTF 0x00E4 +#define REG_PCIE_MIO_INTD 0x00E8 +#define REG_HPON_FSM 0x00EC +#define REG_SYS_CFG 0x00F0 +#define REG_GPIO_OUTSTS 0x00F4 // For RTL8723 only. +#define REG_TYPE_ID 0x00FC + +// +// 2010/12/29 MH Add for 92D +// +#define REG_MAC_PHY_CTRL_NORMAL 0x00f8 + + +//----------------------------------------------------- +// +// 0x0100h ~ 0x01FFh MACTOP General Configuration +// +//----------------------------------------------------- +#define REG_CR 0x0100 +#define REG_PBP 0x0104 +#define REG_PKT_BUFF_ACCESS_CTRL 0x0106 +#define REG_TRXDMA_CTRL 0x010C +#define REG_TRXFF_BNDY 0x0114 +#define REG_TRXFF_STATUS 0x0118 +#define REG_RXFF_PTR 0x011C +#define REG_HIMR 0x0120 +#define REG_HISR 0x0124 +#define REG_HIMRE 0x0128 +#define REG_HISRE 0x012C +#define REG_CPWM 0x012F +#define REG_FWIMR 0x0130 +#define REG_FWISR 0x0134 +#define REG_FTIMR 0x0138 +#define REG_FTISR 0x013C //RTL8192C +#define REG_PKTBUF_DBG_CTRL 0x0140 +#define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL+2) +#define REG_PKTBUF_DBG_DATA_L 0x0144 +#define REG_PKTBUF_DBG_DATA_H 0x0148 + +#define REG_TC0_CTRL 0x0150 +#define REG_TC1_CTRL 0x0154 +#define REG_TC2_CTRL 0x0158 +#define REG_TC3_CTRL 0x015C +#define REG_TC4_CTRL 0x0160 +#define REG_TCUNIT_BASE 0x0164 +#define REG_MBIST_START 0x0174 +#define REG_MBIST_DONE 0x0178 +#define REG_MBIST_FAIL 0x017C +#define REG_32K_CTRL 0x0194 //RTL8188E +#define REG_C2HEVT_MSG_NORMAL 0x01A0 +#define REG_C2HEVT_CLEAR 0x01AF +#define REG_MCUTST_1 0x01c0 +#define REG_MCUTST_WOWLAN 0x01C7 // Defined after 8188E series. +#define REG_FMETHR 0x01C8 +#define REG_HMETFR 0x01CC +#define REG_HMEBOX_0 0x01D0 +#define REG_HMEBOX_1 0x01D4 +#define REG_HMEBOX_2 0x01D8 +#define REG_HMEBOX_3 0x01DC +#define REG_LLT_INIT 0x01E0 +#define REG_HMEBOX_EXT_0 0x01F0 +#define REG_HMEBOX_EXT_1 0x01F4 +#define REG_HMEBOX_EXT_2 0x01F8 +#define REG_HMEBOX_EXT_3 0x01FC + + +//----------------------------------------------------- +// +// 0x0200h ~ 0x027Fh TXDMA Configuration +// +//----------------------------------------------------- +#define REG_RQPN 0x0200 +#define REG_FIFOPAGE 0x0204 +#define REG_TDECTRL 0x0208 +#define REG_TXDMA_OFFSET_CHK 0x020C +#define REG_TXDMA_STATUS 0x0210 +#define REG_RQPN_NPQ 0x0214 +#define REG_AUTO_LLT 0x0224 + + +//----------------------------------------------------- +// +// 0x0280h ~ 0x02FFh RXDMA Configuration +// +//----------------------------------------------------- +#define REG_RXDMA_AGG_PG_TH 0x0280 +#define REG_RXPKT_NUM 0x0284 +#define REG_RXDMA_STATUS 0x0288 +#define REG_RXDMA_MODE 0x0290 + +//----------------------------------------------------- +// +// 0x0300h ~ 0x03FFh PCIe +// +//----------------------------------------------------- +#define REG_PCIE_CTRL_REG 0x0300 +#define REG_INT_MIG 0x0304 /* Interrupt Migration */ +#define REG_BCNQ_DESA 0x0308 /* TX Beacon Descriptor Address */ +#define REG_HQ_DESA 0x0310 /* TX High Queue Descriptor Address */ +#define REG_MGQ_DESA 0x0318 /* TX Manage Queue Descriptor Address */ +#define REG_VOQ_DESA 0x0320 /* TX VO Queue Descriptor Address */ +#define REG_VIQ_DESA 0x0328 /* TX VI Queue Descriptor Address */ +#define REG_BEQ_DESA 0x0330 /* TX BE Queue Descriptor Address */ +#define REG_BKQ_DESA 0x0338 /* TX BK Queue Descriptor Address */ +#define REG_RX_DESA 0x0340 /* RX Queue Descriptor Address */ +//sherry added for DBI Read/Write 20091126 +#define REG_DBI_WDATA 0x0348 /* Backdoor REG for Access Configuration */ +#define REG_DBI_RDATA 0x034C /* Backdoor REG for Access Configuration */ +#define REG_DBI_CTRL 0x0350 /* Backdoor REG for Access Configuration */ +#define REG_DBI_FLAG 0x0352 /* Backdoor REG for Access Configuration */ +#define REG_MDIO 0x0354 /* MDIO for Access PCIE PHY */ +#define REG_DBG_SEL 0x0360 /* Debug Selection Register */ +#define REG_PCIE_HRPWM 0x0361 /* PCIe RPWM */ +#define REG_PCIE_HCPWM 0x0363 /* PCIe CPWM */ +#define REG_WATCH_DOG 0x0368 +#define REG_RX_RXBD_NUM 0x0382 + +// RTL8723 series ------------------------------- +#define REG_PCIE_HISR_EN 0x0394 /* PCIE Local Interrupt Enable Register */ +#define REG_PCIE_HISR 0x03A0 +#define REG_PCIE_HISRE 0x03A4 +#define REG_PCIE_HIMR 0x03A8 +#define REG_PCIE_HIMRE 0x03AC + +#define REG_USB_HIMR 0xFE38 +#define REG_USB_HIMRE 0xFE3C +#define REG_USB_HISR 0xFE78 +#define REG_USB_HISRE 0xFE7C + + +//----------------------------------------------------- +// +// 0x0400h ~ 0x047Fh Protocol Configuration +// +//----------------------------------------------------- + +/* 92C, 92D */ +#define REG_VOQ_INFO 0x0400 +#define REG_VIQ_INFO 0x0404 +#define REG_BEQ_INFO 0x0408 +#define REG_BKQ_INFO 0x040C + +/* 88E, 8723A, 8812A, 8821A, 92E, 8723B */ +#define REG_Q0_INFO 0x400 +#define REG_Q1_INFO 0x404 +#define REG_Q2_INFO 0x408 +#define REG_Q3_INFO 0x40C + +#define REG_MGQ_INFO 0x0410 +#define REG_HGQ_INFO 0x0414 +#define REG_BCNQ_INFO 0x0418 +#define REG_TXPKT_EMPTY 0x041A +#define REG_CPU_MGQ_INFORMATION 0x041C +#define REG_FWHW_TXQ_CTRL 0x0420 +#define REG_HWSEQ_CTRL 0x0423 +#define REG_BCNQ_BDNY 0x0424 +#define REG_MGQ_BDNY 0x0425 +#define REG_LIFETIME_CTRL 0x0426 +#define REG_MULTI_BCNQ_OFFSET 0x0427 +#define REG_SPEC_SIFS 0x0428 +#define REG_RL 0x042A +#define REG_DARFRC 0x0430 +#define REG_RARFRC 0x0438 +#define REG_RRSR 0x0440 +#define REG_ARFR0 0x0444 +#define REG_ARFR1 0x0448 +#define REG_ARFR2 0x044C +#define REG_ARFR3 0x0450 +#define REG_BCNQ1_BDNY 0x0457 + +#define REG_AGGLEN_LMT 0x0458 +#define REG_AMPDU_MIN_SPACE 0x045C +#define REG_WMAC_LBK_BF_HD 0x045D +#define REG_FAST_EDCA_CTRL 0x0460 +#define REG_RD_RESP_PKT_TH 0x0463 + +/* 8723A, 8812A, 8821A, 92E, 8723B */ +#define REG_Q4_INFO 0x468 +#define REG_Q5_INFO 0x46C +#define REG_Q6_INFO 0x470 +#define REG_Q7_INFO 0x474 + +#define REG_INIRTS_RATE_SEL 0x0480 +#define REG_INIDATA_RATE_SEL 0x0484 + +/* 8723B, 92E, 8812A, 8821A*/ +#define REG_MACID_SLEEP_3 0x0484 +#define REG_MACID_SLEEP_1 0x0488 + +#define REG_POWER_STAGE1 0x04B4 +#define REG_POWER_STAGE2 0x04B8 +#define REG_PKT_VO_VI_LIFE_TIME 0x04C0 +#define REG_PKT_BE_BK_LIFE_TIME 0x04C2 +#define REG_STBC_SETTING 0x04C4 +#define REG_QUEUE_CTRL 0x04C6 +#define REG_SINGLE_AMPDU_CTRL 0x04c7 +#define REG_PROT_MODE_CTRL 0x04C8 +#define REG_MAX_AGGR_NUM 0x04CA +#define REG_RTS_MAX_AGGR_NUM 0x04CB +#define REG_BAR_MODE_CTRL 0x04CC +#define REG_RA_TRY_RATE_AGG_LMT 0x04CF + +/* 8723A */ +#define REG_MACID_DROP 0x04D0 + +/* 88E */ +#define REG_EARLY_MODE_CONTROL 0x04D0 + +/* 8723B, 92E, 8812A, 8821A */ +#define REG_MACID_SLEEP_2 0x04D0 + +/* 8723A, 8723B, 92E, 8812A, 8821A */ +#define REG_MACID_SLEEP 0x04D4 + +#define REG_NQOS_SEQ 0x04DC +#define REG_QOS_SEQ 0x04DE +#define REG_NEED_CPU_HANDLE 0x04E0 +#define REG_PKT_LOSE_RPT 0x04E1 +#define REG_PTCL_ERR_STATUS 0x04E2 +#define REG_TX_RPT_CTRL 0x04EC +#define REG_TX_RPT_TIME 0x04F0 // 2 byte +#define REG_DUMMY 0x04FC + +//----------------------------------------------------- +// +// 0x0500h ~ 0x05FFh EDCA Configuration +// +//----------------------------------------------------- +#define REG_EDCA_VO_PARAM 0x0500 +#define REG_EDCA_VI_PARAM 0x0504 +#define REG_EDCA_BE_PARAM 0x0508 +#define REG_EDCA_BK_PARAM 0x050C +#define REG_BCNTCFG 0x0510 +#define REG_PIFS 0x0512 +#define REG_RDG_PIFS 0x0513 +#define REG_SIFS_CTX 0x0514 +#define REG_SIFS_TRX 0x0516 +#define REG_TSFTR_SYN_OFFSET 0x0518 +#define REG_AGGR_BREAK_TIME 0x051A +#define REG_SLOT 0x051B +#define REG_TX_PTCL_CTRL 0x0520 +#define REG_TXPAUSE 0x0522 +#define REG_DIS_TXREQ_CLR 0x0523 +#define REG_RD_CTRL 0x0524 +// +// Format for offset 540h-542h: +// [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. +// [7:4]: Reserved. +// [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. +// [23:20]: Reserved +// Description: +// | +// |<--Setup--|--Hold------------>| +// --------------|---------------------- +// | +// TBTT +// Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. +// Described by Designer Tim and Bruce, 2011-01-14. +// +#define REG_TBTT_PROHIBIT 0x0540 +#define REG_RD_NAV_NXT 0x0544 +#define REG_NAV_PROT_LEN 0x0546 +#define REG_BCN_CTRL 0x0550 +#define REG_BCN_CTRL_1 0x0551 +#define REG_MBID_NUM 0x0552 +#define REG_DUAL_TSF_RST 0x0553 +#define REG_BCN_INTERVAL 0x0554 // The same as REG_MBSSID_BCN_SPACE +#define REG_DRVERLYINT 0x0558 +#define REG_BCNDMATIM 0x0559 +#define REG_ATIMWND 0x055A +#define REG_USTIME_TSF 0x055C +#define REG_BCN_MAX_ERR 0x055D +#define REG_RXTSF_OFFSET_CCK 0x055E +#define REG_RXTSF_OFFSET_OFDM 0x055F +#define REG_TSFTR 0x0560 +#define REG_TSFTR1 0x0568 // HW Port 1 TSF Register +#define REG_ATIMWND_1 0x0570 +#define REG_P2P_CTWIN 0x0572 // 1 Byte long (in unit of TU) +#define REG_PSTIMER 0x0580 +#define REG_TIMER0 0x0584 +#define REG_TIMER1 0x0588 +#define REG_ACMHWCTRL 0x05C0 +#define REG_NOA_DESC_SEL 0x05CF +#define REG_NOA_DESC_DURATION 0x05E0 +#define REG_NOA_DESC_INTERVAL 0x05E4 +#define REG_NOA_DESC_START 0x05E8 +#define REG_NOA_DESC_COUNT 0x05EC + +#define REG_DMC 0x05F0 //Dual MAC Co-Existence Register +#define REG_SCH_TX_CMD 0x05F8 + +#define REG_FW_RESET_TSF_CNT_1 0x05FC +#define REG_FW_RESET_TSF_CNT_0 0x05FD +#define REG_FW_BCN_DIS_CNT 0x05FE + +//----------------------------------------------------- +// +// 0x0600h ~ 0x07FFh WMAC Configuration +// +//----------------------------------------------------- +#define REG_APSD_CTRL 0x0600 +#define REG_BWOPMODE 0x0603 +#define REG_TCR 0x0604 +#define REG_RCR 0x0608 +#define REG_RX_PKT_LIMIT 0x060C +#define REG_RX_DLK_TIME 0x060D +#define REG_RX_DRVINFO_SZ 0x060F + +#define REG_MACID 0x0610 +#define REG_BSSID 0x0618 +#define REG_MAR 0x0620 +#define REG_MBIDCAMCFG 0x0628 + +#define REG_PNO_STATUS 0x0631 +#define REG_USTIME_EDCA 0x0638 +#define REG_MAC_SPEC_SIFS 0x063A +// 20100719 Joseph: Hardware register definition change. (HW datasheet v54) +#define REG_RESP_SIFS_CCK 0x063C // [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK +#define REG_RESP_SIFS_OFDM 0x063E // [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK + +#define REG_ACKTO 0x0640 +#define REG_CTS2TO 0x0641 +#define REG_EIFS 0x0642 + + +//RXERR_RPT +#define RXERR_TYPE_OFDM_PPDU 0 +#define RXERR_TYPE_OFDM_FALSE_ALARM 1 +#define RXERR_TYPE_OFDM_MPDU_OK 2 +#define RXERR_TYPE_OFDM_MPDU_FAIL 3 +#define RXERR_TYPE_CCK_PPDU 4 +#define RXERR_TYPE_CCK_FALSE_ALARM 5 +#define RXERR_TYPE_CCK_MPDU_OK 6 +#define RXERR_TYPE_CCK_MPDU_FAIL 7 +#define RXERR_TYPE_HT_PPDU 8 +#define RXERR_TYPE_HT_FALSE_ALARM 9 +#define RXERR_TYPE_HT_MPDU_TOTAL 10 +#define RXERR_TYPE_HT_MPDU_OK 11 +#define RXERR_TYPE_HT_MPDU_FAIL 12 +#define RXERR_TYPE_RX_FULL_DROP 15 + +#define RXERR_COUNTER_MASK 0xFFFFF +#define RXERR_RPT_RST BIT(27) +#define _RXERR_RPT_SEL(type) ((type) << 28) + +// +// Note: +// The NAV upper value is very important to WiFi 11n 5.2.3 NAV test. The default value is +// always too small, but the WiFi TestPlan test by 25,000 microseconds of NAV through sending +// CTS in the air. We must update this value greater than 25,000 microseconds to pass the item. +// The offset of NAV_UPPER in 8192C Spec is incorrect, and the offset should be 0x0652. Commented +// by SD1 Scott. +// By Bruce, 2011-07-18. +// +#define REG_NAV_UPPER 0x0652 // unit of 128 + +//WMA, BA, CCX +#define REG_NAV_CTRL 0x0650 +#define REG_BACAMCMD 0x0654 +#define REG_BACAMCONTENT 0x0658 +#define REG_LBDLY 0x0660 +#define REG_FWDLY 0x0661 +#define REG_RXERR_RPT 0x0664 +#define REG_WMAC_TRXPTCL_CTL 0x0668 + +// Security +#define REG_CAMCMD 0x0670 +#define REG_CAMWRITE 0x0674 +#define REG_CAMREAD 0x0678 +#define REG_CAMDBG 0x067C +#define REG_SECCFG 0x0680 + +// Power +#define REG_WOW_CTRL 0x0690 +#define REG_PS_RX_INFO 0x0692 +#define REG_UAPSD_TID 0x0693 +#define REG_WKFMCAM_CMD 0x0698 +#define REG_WKFMCAM_NUM REG_WKFMCAM_CMD +#define REG_WKFMCAM_RWD 0x069C +#define REG_RXFLTMAP0 0x06A0 +#define REG_RXFLTMAP1 0x06A2 +#define REG_RXFLTMAP2 0x06A4 +#define REG_BCN_PSR_RPT 0x06A8 +#define REG_BT_COEX_TABLE 0x06C0 + +// Hardware Port 2 +#define REG_MACID1 0x0700 +#define REG_BSSID1 0x0708 + + +//----------------------------------------------------- +// +// 0xFE00h ~ 0xFE55h USB Configuration +// +//----------------------------------------------------- +#define REG_USB_INFO 0xFE17 +#define REG_USB_SPECIAL_OPTION 0xFE55 +#define REG_USB_DMA_AGG_TO 0xFE5B +#define REG_USB_AGG_TO 0xFE5C +#define REG_USB_AGG_TH 0xFE5D + +#define REG_USB_HRPWM 0xFE58 +#define REG_USB_HCPWM 0xFE57 + +// for 92DU high_Queue low_Queue Normal_Queue select +#define REG_USB_High_NORMAL_Queue_Select_MAC0 0xFE44 +//#define REG_USB_LOW_Queue_Select_MAC0 0xFE45 +#define REG_USB_High_NORMAL_Queue_Select_MAC1 0xFE47 +//#define REG_USB_LOW_Queue_Select_MAC1 0xFE48 + +// For test chip +#define REG_TEST_USB_TXQS 0xFE48 +#define REG_TEST_SIE_VID 0xFE60 // 0xFE60~0xFE61 +#define REG_TEST_SIE_PID 0xFE62 // 0xFE62~0xFE63 +#define REG_TEST_SIE_OPTIONAL 0xFE64 +#define REG_TEST_SIE_CHIRP_K 0xFE65 +#define REG_TEST_SIE_PHY 0xFE66 // 0xFE66~0xFE6B +#define REG_TEST_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75 +#define REG_TEST_SIE_STRING 0xFE80 // 0xFE80~0xFEB9 + + +// For normal chip +#define REG_NORMAL_SIE_VID 0xFE60 // 0xFE60~0xFE61 +#define REG_NORMAL_SIE_PID 0xFE62 // 0xFE62~0xFE63 +#define REG_NORMAL_SIE_OPTIONAL 0xFE64 +#define REG_NORMAL_SIE_EP 0xFE65 // 0xFE65~0xFE67 +#define REG_NORMAL_SIE_PHY 0xFE68 // 0xFE68~0xFE6B +#define REG_NORMAL_SIE_OPTIONAL2 0xFE6C +#define REG_NORMAL_SIE_GPS_EP 0xFE6D // 0xFE6D, for RTL8723 only. +#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75 +#define REG_NORMAL_SIE_STRING 0xFE80 // 0xFE80~0xFEDF + + +//----------------------------------------------------- +// +// Redifine 8192C register definition for compatibility +// +//----------------------------------------------------- + +// TODO: use these definition when using REG_xxx naming rule. +// NOTE: DO NOT Remove these definition. Use later. + +#define EFUSE_CTRL REG_EFUSE_CTRL // E-Fuse Control. +#define EFUSE_TEST REG_EFUSE_TEST // E-Fuse Test. +#define MSR (REG_CR + 2) // Media Status register +//#define ISR REG_HISR + +#define TSFR REG_TSFTR // Timing Sync Function Timer Register. +#define TSFR1 REG_TSFTR1 // HW Port 1 TSF Register + +#define PBP REG_PBP + +// Redifine MACID register, to compatible prior ICs. +#define IDR0 REG_MACID // MAC ID Register, Offset 0x0050-0x0053 +#define IDR4 (REG_MACID + 4) // MAC ID Register, Offset 0x0054-0x0055 + + +// +// 9. Security Control Registers (Offset: ) +// +#define RWCAM REG_CAMCMD //IN 8190 Data Sheet is called CAMcmd +#define WCAMI REG_CAMWRITE // Software write CAM input content +#define RCAMO REG_CAMREAD // Software read/write CAM config +#define CAMDBG REG_CAMDBG +#define SECR REG_SECCFG //Security Configuration Register + +// Unused register +#define UnusedRegister 0x1BF +#define DCAM UnusedRegister +#define PSR UnusedRegister +#define BBAddr UnusedRegister +#define PhyDataR UnusedRegister + +// Min Spacing related settings. +#define MAX_MSS_DENSITY_2T 0x13 +#define MAX_MSS_DENSITY_1T 0x0A + +//---------------------------------------------------------------------------- +// 8192C Cmd9346CR bits (Offset 0xA, 16bit) +//---------------------------------------------------------------------------- +#define CmdEEPROM_En BIT5 // EEPROM enable when set 1 +#define CmdEERPOMSEL BIT4 // System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 +#define Cmd9346CR_9356SEL BIT4 + +//---------------------------------------------------------------------------- +// 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) +//---------------------------------------------------------------------------- +#define GPIOSEL_GPIO 0 +#define GPIOSEL_ENBT BIT5 + +//---------------------------------------------------------------------------- +// 8192C GPIO PIN Control Register (offset 0x44, 4 byte) +//---------------------------------------------------------------------------- +#define GPIO_IN REG_GPIO_PIN_CTRL // GPIO pins input value +#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) // GPIO pins output value +#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) // GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. +#define GPIO_MOD (REG_GPIO_PIN_CTRL+3) + +//---------------------------------------------------------------------------- +// 8811A GPIO PIN Control Register (offset 0x60, 4 byte) +//---------------------------------------------------------------------------- +#define GPIO_IN_8811A REG_GPIO_PIN_CTRL_2 // GPIO pins input value +#define GPIO_OUT_8811A (REG_GPIO_PIN_CTRL_2+1) // GPIO pins output value +#define GPIO_IO_SEL_8811A (REG_GPIO_PIN_CTRL_2+2) // GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. +#define GPIO_MOD_8811A (REG_GPIO_PIN_CTRL_2+3) + +//---------------------------------------------------------------------------- +// 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) +//---------------------------------------------------------------------------- +#define HSIMR_GPIO12_0_INT_EN BIT0 +#define HSIMR_SPS_OCP_INT_EN BIT5 +#define HSIMR_RON_INT_EN BIT6 +#define HSIMR_PDN_INT_EN BIT7 +#define HSIMR_GPIO9_INT_EN BIT25 + +//---------------------------------------------------------------------------- +// 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) +//---------------------------------------------------------------------------- +#define HSISR_GPIO12_0_INT BIT0 +#define HSISR_SPS_OCP_INT BIT5 +#define HSISR_RON_INT BIT6 +#define HSISR_PDNINT BIT7 +#define HSISR_GPIO9_INT BIT25 + +//---------------------------------------------------------------------------- +// 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) +//---------------------------------------------------------------------------- +/* +Network Type +00: No link +01: Link in ad hoc network +10: Link in infrastructure network +11: AP mode +Default: 00b. +*/ +#define MSR_NOLINK 0x00 +#define MSR_ADHOC 0x01 +#define MSR_INFRA 0x02 +#define MSR_AP 0x03 + +//---------------------------------------------------------------------------- +// USB INTR CONTENT +//---------------------------------------------------------------------------- +#define USB_C2H_CMDID_OFFSET 0 +#define USB_C2H_SEQ_OFFSET 1 +#define USB_C2H_EVENT_OFFSET 2 +#define USB_INTR_CPWM_OFFSET 16 +#define USB_INTR_CONTENT_C2H_OFFSET 0 +#define USB_INTR_CONTENT_CPWM1_OFFSET 16 +#define USB_INTR_CONTENT_CPWM2_OFFSET 20 +#define USB_INTR_CONTENT_HISR_OFFSET 48 +#define USB_INTR_CONTENT_HISRE_OFFSET 52 +#define USB_INTR_CONTENT_LENGTH 56 + +//---------------------------------------------------------------------------- +// Response Rate Set Register (offset 0x440, 24bits) +//---------------------------------------------------------------------------- +#define RRSR_1M BIT0 +#define RRSR_2M BIT1 +#define RRSR_5_5M BIT2 +#define RRSR_11M BIT3 +#define RRSR_6M BIT4 +#define RRSR_9M BIT5 +#define RRSR_12M BIT6 +#define RRSR_18M BIT7 +#define RRSR_24M BIT8 +#define RRSR_36M BIT9 +#define RRSR_48M BIT10 +#define RRSR_54M BIT11 +#define RRSR_MCS0 BIT12 +#define RRSR_MCS1 BIT13 +#define RRSR_MCS2 BIT14 +#define RRSR_MCS3 BIT15 +#define RRSR_MCS4 BIT16 +#define RRSR_MCS5 BIT17 +#define RRSR_MCS6 BIT18 +#define RRSR_MCS7 BIT19 + +#define RRSR_CCK_RATES (RRSR_11M|RRSR_5_5M|RRSR_2M|RRSR_1M) +#define RRSR_OFDM_RATES (RRSR_54M|RRSR_48M|RRSR_36M|RRSR_24M|RRSR_18M|RRSR_12M|RRSR_9M|RRSR_6M) + +// WOL bit information +#define HAL92C_WOL_PTK_UPDATE_EVENT BIT0 +#define HAL92C_WOL_GTK_UPDATE_EVENT BIT1 +#define HAL92C_WOL_DISASSOC_EVENT BIT2 +#define HAL92C_WOL_DEAUTH_EVENT BIT3 +#define HAL92C_WOL_FW_DISCONNECT_EVENT BIT4 + +//---------------------------------------------------------------------------- +// Rate Definition +//---------------------------------------------------------------------------- +//CCK +#define RATR_1M 0x00000001 +#define RATR_2M 0x00000002 +#define RATR_55M 0x00000004 +#define RATR_11M 0x00000008 +//OFDM +#define RATR_6M 0x00000010 +#define RATR_9M 0x00000020 +#define RATR_12M 0x00000040 +#define RATR_18M 0x00000080 +#define RATR_24M 0x00000100 +#define RATR_36M 0x00000200 +#define RATR_48M 0x00000400 +#define RATR_54M 0x00000800 +//MCS 1 Spatial Stream +#define RATR_MCS0 0x00001000 +#define RATR_MCS1 0x00002000 +#define RATR_MCS2 0x00004000 +#define RATR_MCS3 0x00008000 +#define RATR_MCS4 0x00010000 +#define RATR_MCS5 0x00020000 +#define RATR_MCS6 0x00040000 +#define RATR_MCS7 0x00080000 +//MCS 2 Spatial Stream +#define RATR_MCS8 0x00100000 +#define RATR_MCS9 0x00200000 +#define RATR_MCS10 0x00400000 +#define RATR_MCS11 0x00800000 +#define RATR_MCS12 0x01000000 +#define RATR_MCS13 0x02000000 +#define RATR_MCS14 0x04000000 +#define RATR_MCS15 0x08000000 + +//CCK +#define RATE_1M BIT(0) +#define RATE_2M BIT(1) +#define RATE_5_5M BIT(2) +#define RATE_11M BIT(3) +//OFDM +#define RATE_6M BIT(4) +#define RATE_9M BIT(5) +#define RATE_12M BIT(6) +#define RATE_18M BIT(7) +#define RATE_24M BIT(8) +#define RATE_36M BIT(9) +#define RATE_48M BIT(10) +#define RATE_54M BIT(11) +//MCS 1 Spatial Stream +#define RATE_MCS0 BIT(12) +#define RATE_MCS1 BIT(13) +#define RATE_MCS2 BIT(14) +#define RATE_MCS3 BIT(15) +#define RATE_MCS4 BIT(16) +#define RATE_MCS5 BIT(17) +#define RATE_MCS6 BIT(18) +#define RATE_MCS7 BIT(19) +//MCS 2 Spatial Stream +#define RATE_MCS8 BIT(20) +#define RATE_MCS9 BIT(21) +#define RATE_MCS10 BIT(22) +#define RATE_MCS11 BIT(23) +#define RATE_MCS12 BIT(24) +#define RATE_MCS13 BIT(25) +#define RATE_MCS14 BIT(26) +#define RATE_MCS15 BIT(27) + + +// ALL CCK Rate +#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M +#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|\ + RATR_36M|RATR_48M|RATR_54M +#define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 |\ + RATR_MCS4|RATR_MCS5|RATR_MCS6 |RATR_MCS7 +#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11|\ + RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15 + +#define RATE_BITMAP_ALL 0xFFFFF + +// Only use CCK 1M rate for ACK +#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 +#define RATE_RRSR_WITHOUT_CCK 0xFFFF0 + +//---------------------------------------------------------------------------- +// BW_OPMODE bits (Offset 0x603, 8bit) +//---------------------------------------------------------------------------- +#define BW_OPMODE_20MHZ BIT2 +#define BW_OPMODE_5G BIT1 + +//---------------------------------------------------------------------------- +// CAM Config Setting (offset 0x680, 1 byte) +//---------------------------------------------------------------------------- +#define CAM_VALID BIT15 +#define CAM_NOTVALID 0x0000 +#define CAM_USEDK BIT5 + +#define CAM_CONTENT_COUNT 8 + +#define CAM_NONE 0x0 +#define CAM_WEP40 0x01 +#define CAM_TKIP 0x02 +#define CAM_AES 0x04 +#define CAM_WEP104 0x05 +#define CAM_SMS4 0x6 + +#define TOTAL_CAM_ENTRY 32 +#define HALF_CAM_ENTRY 16 + +#define CAM_CONFIG_USEDK _TRUE +#define CAM_CONFIG_NO_USEDK _FALSE + +#define CAM_WRITE BIT16 +#define CAM_READ 0x00000000 +#define CAM_POLLINIG BIT31 + +// +// 10. Power Save Control Registers +// +#define WOW_PMEN BIT0 // Power management Enable. +#define WOW_WOMEN BIT1 // WoW function on or off. +#define WOW_MAGIC BIT2 // Magic packet +#define WOW_UWF BIT3 // Unicast Wakeup frame. + +// +// 12. Host Interrupt Status Registers +// +//---------------------------------------------------------------------------- +// 8190 IMR/ISR bits +//---------------------------------------------------------------------------- +#define IMR8190_DISABLED 0x0 +#define IMR_DISABLED 0x0 +// IMR DW0 Bit 0-31 +#define IMR_BCNDMAINT6 BIT31 // Beacon DMA Interrupt 6 +#define IMR_BCNDMAINT5 BIT30 // Beacon DMA Interrupt 5 +#define IMR_BCNDMAINT4 BIT29 // Beacon DMA Interrupt 4 +#define IMR_BCNDMAINT3 BIT28 // Beacon DMA Interrupt 3 +#define IMR_BCNDMAINT2 BIT27 // Beacon DMA Interrupt 2 +#define IMR_BCNDMAINT1 BIT26 // Beacon DMA Interrupt 1 +#define IMR_BCNDOK8 BIT25 // Beacon Queue DMA OK Interrup 8 +#define IMR_BCNDOK7 BIT24 // Beacon Queue DMA OK Interrup 7 +#define IMR_BCNDOK6 BIT23 // Beacon Queue DMA OK Interrup 6 +#define IMR_BCNDOK5 BIT22 // Beacon Queue DMA OK Interrup 5 +#define IMR_BCNDOK4 BIT21 // Beacon Queue DMA OK Interrup 4 +#define IMR_BCNDOK3 BIT20 // Beacon Queue DMA OK Interrup 3 +#define IMR_BCNDOK2 BIT19 // Beacon Queue DMA OK Interrup 2 +#define IMR_BCNDOK1 BIT18 // Beacon Queue DMA OK Interrup 1 +#define IMR_TIMEOUT2 BIT17 // Timeout interrupt 2 +#define IMR_TIMEOUT1 BIT16 // Timeout interrupt 1 +#define IMR_TXFOVW BIT15 // Transmit FIFO Overflow +#define IMR_PSTIMEOUT BIT14 // Power save time out interrupt +#define IMR_BcnInt BIT13 // Beacon DMA Interrupt 0 +#define IMR_RXFOVW BIT12 // Receive FIFO Overflow +#define IMR_RDU BIT11 // Receive Descriptor Unavailable +#define IMR_ATIMEND BIT10 // For 92C,ATIM Window End Interrupt. For 8723 and later ICs, it also means P2P CTWin End interrupt. +#define IMR_BDOK BIT9 // Beacon Queue DMA OK Interrup +#define IMR_HIGHDOK BIT8 // High Queue DMA OK Interrupt +#define IMR_TBDOK BIT7 // Transmit Beacon OK interrup +#define IMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt +#define IMR_TBDER BIT5 // For 92C,Transmit Beacon Error Interrupt +#define IMR_BKDOK BIT4 // AC_BK DMA OK Interrupt +#define IMR_BEDOK BIT3 // AC_BE DMA OK Interrupt +#define IMR_VIDOK BIT2 // AC_VI DMA OK Interrupt +#define IMR_VODOK BIT1 // AC_VO DMA Interrupt +#define IMR_ROK BIT0 // Receive DMA OK Interrupt + +// 13. Host Interrupt Status Extension Register (Offset: 0x012C-012Eh) +#define IMR_TSF_BIT32_TOGGLE BIT15 +#define IMR_BcnInt_E BIT12 +#define IMR_TXERR BIT11 +#define IMR_RXERR BIT10 +#define IMR_C2HCMD BIT9 +#define IMR_CPWM BIT8 +//RSVD [2-7] +#define IMR_OCPINT BIT1 +#define IMR_WLANOFF BIT0 + +//---------------------------------------------------------------------------- +// 8723E series PCIE Host IMR/ISR bit +//---------------------------------------------------------------------------- +// IMR DW0 Bit 0-31 +#define PHIMR_TIMEOUT2 BIT31 +#define PHIMR_TIMEOUT1 BIT30 +#define PHIMR_PSTIMEOUT BIT29 +#define PHIMR_GTINT4 BIT28 +#define PHIMR_GTINT3 BIT27 +#define PHIMR_TXBCNERR BIT26 +#define PHIMR_TXBCNOK BIT25 +#define PHIMR_TSF_BIT32_TOGGLE BIT24 +#define PHIMR_BCNDMAINT3 BIT23 +#define PHIMR_BCNDMAINT2 BIT22 +#define PHIMR_BCNDMAINT1 BIT21 +#define PHIMR_BCNDMAINT0 BIT20 +#define PHIMR_BCNDOK3 BIT19 +#define PHIMR_BCNDOK2 BIT18 +#define PHIMR_BCNDOK1 BIT17 +#define PHIMR_BCNDOK0 BIT16 +#define PHIMR_HSISR_IND_ON BIT15 +#define PHIMR_BCNDMAINT_E BIT14 +#define PHIMR_ATIMEND_E BIT13 +#define PHIMR_ATIM_CTW_END BIT12 +#define PHIMR_HISRE_IND BIT11 // RO. HISRE Indicator (HISRE & HIMRE is true, this bit is set to 1) +#define PHIMR_C2HCMD BIT10 +#define PHIMR_CPWM2 BIT9 +#define PHIMR_CPWM BIT8 +#define PHIMR_HIGHDOK BIT7 // High Queue DMA OK Interrupt +#define PHIMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt +#define PHIMR_BKDOK BIT5 // AC_BK DMA OK Interrupt +#define PHIMR_BEDOK BIT4 // AC_BE DMA OK Interrupt +#define PHIMR_VIDOK BIT3 // AC_VI DMA OK Interrupt +#define PHIMR_VODOK BIT2 // AC_VO DMA Interrupt +#define PHIMR_RDU BIT1 // Receive Descriptor Unavailable +#define PHIMR_ROK BIT0 // Receive DMA OK Interrupt + +// PCIE Host Interrupt Status Extension bit +#define PHIMR_BCNDMAINT7 BIT23 +#define PHIMR_BCNDMAINT6 BIT22 +#define PHIMR_BCNDMAINT5 BIT21 +#define PHIMR_BCNDMAINT4 BIT20 +#define PHIMR_BCNDOK7 BIT19 +#define PHIMR_BCNDOK6 BIT18 +#define PHIMR_BCNDOK5 BIT17 +#define PHIMR_BCNDOK4 BIT16 +// bit12 15: RSVD +#define PHIMR_TXERR BIT11 +#define PHIMR_RXERR BIT10 +#define PHIMR_TXFOVW BIT9 +#define PHIMR_RXFOVW BIT8 +// bit2-7: RSVD +#define PHIMR_OCPINT BIT1 +// bit0: RSVD + +#define UHIMR_TIMEOUT2 BIT31 +#define UHIMR_TIMEOUT1 BIT30 +#define UHIMR_PSTIMEOUT BIT29 +#define UHIMR_GTINT4 BIT28 +#define UHIMR_GTINT3 BIT27 +#define UHIMR_TXBCNERR BIT26 +#define UHIMR_TXBCNOK BIT25 +#define UHIMR_TSF_BIT32_TOGGLE BIT24 +#define UHIMR_BCNDMAINT3 BIT23 +#define UHIMR_BCNDMAINT2 BIT22 +#define UHIMR_BCNDMAINT1 BIT21 +#define UHIMR_BCNDMAINT0 BIT20 +#define UHIMR_BCNDOK3 BIT19 +#define UHIMR_BCNDOK2 BIT18 +#define UHIMR_BCNDOK1 BIT17 +#define UHIMR_BCNDOK0 BIT16 +#define UHIMR_HSISR_IND BIT15 +#define UHIMR_BCNDMAINT_E BIT14 +//RSVD BIT13 +#define UHIMR_CTW_END BIT12 +//RSVD BIT11 +#define UHIMR_C2HCMD BIT10 +#define UHIMR_CPWM2 BIT9 +#define UHIMR_CPWM BIT8 +#define UHIMR_HIGHDOK BIT7 // High Queue DMA OK Interrupt +#define UHIMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt +#define UHIMR_BKDOK BIT5 // AC_BK DMA OK Interrupt +#define UHIMR_BEDOK BIT4 // AC_BE DMA OK Interrupt +#define UHIMR_VIDOK BIT3 // AC_VI DMA OK Interrupt +#define UHIMR_VODOK BIT2 // AC_VO DMA Interrupt +#define UHIMR_RDU BIT1 // Receive Descriptor Unavailable +#define UHIMR_ROK BIT0 // Receive DMA OK Interrupt + +// USB Host Interrupt Status Extension bit +#define UHIMR_BCNDMAINT7 BIT23 +#define UHIMR_BCNDMAINT6 BIT22 +#define UHIMR_BCNDMAINT5 BIT21 +#define UHIMR_BCNDMAINT4 BIT20 +#define UHIMR_BCNDOK7 BIT19 +#define UHIMR_BCNDOK6 BIT18 +#define UHIMR_BCNDOK5 BIT17 +#define UHIMR_BCNDOK4 BIT16 +// bit14-15: RSVD +#define UHIMR_ATIMEND_E BIT13 +#define UHIMR_ATIMEND BIT12 +#define UHIMR_TXERR BIT11 +#define UHIMR_RXERR BIT10 +#define UHIMR_TXFOVW BIT9 +#define UHIMR_RXFOVW BIT8 +// bit2-7: RSVD +#define UHIMR_OCPINT BIT1 +// bit0: RSVD + + +#define HAL_NIC_UNPLUG_ISR 0xFFFFFFFF // The value when the NIC is unplugged for PCI. +#define HAL_NIC_UNPLUG_PCI_ISR 0xEAEAEAEA // The value when the NIC is unplugged for PCI in PCI interrupt (page 3). + +//---------------------------------------------------------------------------- +// 8188 IMR/ISR bits +//---------------------------------------------------------------------------- +#define IMR_DISABLED_88E 0x0 +// IMR DW0(0x0060-0063) Bit 0-31 +#define IMR_TXCCK_88E BIT30 // TXRPT interrupt when CCX bit of the packet is set +#define IMR_PSTIMEOUT_88E BIT29 // Power Save Time Out Interrupt +#define IMR_GTINT4_88E BIT28 // When GTIMER4 expires, this bit is set to 1 +#define IMR_GTINT3_88E BIT27 // When GTIMER3 expires, this bit is set to 1 +#define IMR_TBDER_88E BIT26 // Transmit Beacon0 Error +#define IMR_TBDOK_88E BIT25 // Transmit Beacon0 OK +#define IMR_TSF_BIT32_TOGGLE_88E BIT24 // TSF Timer BIT32 toggle indication interrupt +#define IMR_BCNDMAINT0_88E BIT20 // Beacon DMA Interrupt 0 +#define IMR_BCNDERR0_88E BIT16 // Beacon Queue DMA Error 0 +#define IMR_HSISR_IND_ON_INT_88E BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) +#define IMR_BCNDMAINT_E_88E BIT14 // Beacon DMA Interrupt Extension for Win7 +#define IMR_ATIMEND_88E BIT12 // CTWidnow End or ATIM Window End +#define IMR_HISR1_IND_INT_88E BIT11 // HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) +#define IMR_C2HCMD_88E BIT10 // CPU to Host Command INT Status, Write 1 clear +#define IMR_CPWM2_88E BIT9 // CPU power Mode exchange INT Status, Write 1 clear +#define IMR_CPWM_88E BIT8 // CPU power Mode exchange INT Status, Write 1 clear +#define IMR_HIGHDOK_88E BIT7 // High Queue DMA OK +#define IMR_MGNTDOK_88E BIT6 // Management Queue DMA OK +#define IMR_BKDOK_88E BIT5 // AC_BK DMA OK +#define IMR_BEDOK_88E BIT4 // AC_BE DMA OK +#define IMR_VIDOK_88E BIT3 // AC_VI DMA OK +#define IMR_VODOK_88E BIT2 // AC_VO DMA OK +#define IMR_RDU_88E BIT1 // Rx Descriptor Unavailable +#define IMR_ROK_88E BIT0 // Receive DMA OK + +// IMR DW1(0x00B4-00B7) Bit 0-31 +#define IMR_BCNDMAINT7_88E BIT27 // Beacon DMA Interrupt 7 +#define IMR_BCNDMAINT6_88E BIT26 // Beacon DMA Interrupt 6 +#define IMR_BCNDMAINT5_88E BIT25 // Beacon DMA Interrupt 5 +#define IMR_BCNDMAINT4_88E BIT24 // Beacon DMA Interrupt 4 +#define IMR_BCNDMAINT3_88E BIT23 // Beacon DMA Interrupt 3 +#define IMR_BCNDMAINT2_88E BIT22 // Beacon DMA Interrupt 2 +#define IMR_BCNDMAINT1_88E BIT21 // Beacon DMA Interrupt 1 +#define IMR_BCNDOK7_88E BIT20 // Beacon Queue DMA OK Interrup 7 +#define IMR_BCNDOK6_88E BIT19 // Beacon Queue DMA OK Interrup 6 +#define IMR_BCNDOK5_88E BIT18 // Beacon Queue DMA OK Interrup 5 +#define IMR_BCNDOK4_88E BIT17 // Beacon Queue DMA OK Interrup 4 +#define IMR_BCNDOK3_88E BIT16 // Beacon Queue DMA OK Interrup 3 +#define IMR_BCNDOK2_88E BIT15 // Beacon Queue DMA OK Interrup 2 +#define IMR_BCNDOK1_88E BIT14 // Beacon Queue DMA OK Interrup 1 +#define IMR_ATIMEND_E_88E BIT13 // ATIM Window End Extension for Win7 +#define IMR_TXERR_88E BIT11 // Tx Error Flag Interrupt Status, write 1 clear. +#define IMR_RXERR_88E BIT10 // Rx Error Flag INT Status, Write 1 clear +#define IMR_TXFOVW_88E BIT9 // Transmit FIFO Overflow +#define IMR_RXFOVW_88E BIT8 // Receive FIFO Overflow + +/*=================================================================== +===================================================================== +Here the register defines are for 92C. When the define is as same with 92C, +we will use the 92C's define for the consistency +So the following defines for 92C is not entire!!!!!! +===================================================================== +=====================================================================*/ +/* +Based on Datasheet V33---090401 +Register Summary +Current IOREG MAP +0x0000h ~ 0x00FFh System Configuration (256 Bytes) +0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) +0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) +0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) +0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) +0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) +0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) +0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) +0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) +*/ + //---------------------------------------------------------------------------- + // 8192C (TXPAUSE) transmission pause (Offset 0x522, 8 bits) + //---------------------------------------------------------------------------- +// Note: +// The the bits of stoping AC(VO/VI/BE/BK) queue in datasheet RTL8192S/RTL8192C are wrong, +// the correct arragement is VO - Bit0, VI - Bit1, BE - Bit2, and BK - Bit3. +// 8723 and 88E may be not correct either in the eralier version. Confirmed with DD Tim. +// By Bruce, 2011-09-22. +#define StopBecon BIT6 +#define StopHigh BIT5 +#define StopMgt BIT4 +#define StopBK BIT3 +#define StopBE BIT2 +#define StopVI BIT1 +#define StopVO BIT0 + +//---------------------------------------------------------------------------- +// 8192C (RCR) Receive Configuration Register (Offset 0x608, 32 bits) +//---------------------------------------------------------------------------- +#define RCR_APPFCS BIT31 // WMAC append FCS after pauload +#define RCR_APP_MIC BIT30 // MACRX will retain the MIC at the bottom of the packet. +#define RCR_APP_ICV BIT29 // MACRX will retain the ICV at the bottom of the packet. +#define RCR_APP_PHYST_RXFF BIT28 // PHY Status is appended before RX packet in RXFF +#define RCR_APP_BA_SSN BIT27 // SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. +#define RCR_VHT_DACK BIT26 /* This bit to control response type for vht single mpdu data packet. 1. ACK as response 0. BA as response */ +#define RCR_TCPOFLD_EN BIT25 /* Enable TCP checksum offload */ +#define RCR_ENMBID BIT24 // Enable Multiple BssId. Only response ACK to the packets whose DID(A1) matching to the addresses in the MBSSID CAM Entries. +#define RCR_LSIGEN BIT23 // Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to check if LSIGEN bit is set. +#define RCR_MFBEN BIT22 // Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then search KEYCAM to find sender's MCS Feedback function and send response. +#define RCR_DISCHKPPDLLEN BIT21 /* Do not check PPDU while the PPDU length is smaller than 14 byte. */ +#define RCR_PKTCTL_DLEN BIT20 /* While rx path dead lock occurs, reset rx path */ +#define RCR_DISGCLK BIT19 /* Disable macrx clock gating control (no used) */ +#define RCR_TIM_PARSER_EN BIT18 // RX Beacon TIM Parser. +#define RCR_BC_MD_EN BIT17 /* Broadcast data packet more data bit check interrupt enable.*/ +#define RCR_UC_MD_EN BIT16 /* Unicast data packet more data bit check interrupt enable. */ +#define RCR_RXSK_PERPKT BIT15 /* Executing key search per MPDU */ +#define RCR_HTC_LOC_CTRL BIT14 // MFC<--HTC=1 MFC-->HTC=0 +#define RCR_AMF BIT13 // Accept management type frame +#define RCR_ACF BIT12 // Accept control type frame. Control frames BA, BAR, and PS-Poll (when in AP mode) are not controlled by this bit. They are controlled by ADF. +#define RCR_ADF BIT11 // Accept data type frame. This bit also regulates BA, BAR, and PS-Poll (AP mode only). +#define RCR_DISDECMYPKT BIT10 /* This bit determines whether hw need to do decryption.1: If A1 match, do decryption.0: Do decryption. */ +#define RCR_AICV BIT9 // Accept ICV error packet +#define RCR_ACRC32 BIT8 // Accept CRC32 error packet +#define RCR_CBSSID_BCN BIT7 // Accept BSSID match packet (Rx beacon, probe rsp) +#define RCR_CBSSID_DATA BIT6 // Accept BSSID match packet (Data) +#define RCR_APWRMGT BIT5 // Accept power management packet +#define RCR_ADD3 BIT4 // Accept address 3 match packet +#define RCR_AB BIT3 // Accept broadcast packet +#define RCR_AM BIT2 // Accept multicast packet +#define RCR_APM BIT1 // Accept physical match packet +#define RCR_AAP BIT0 // Accept all unicast packet + + +//----------------------------------------------------- +// +// 0x0000h ~ 0x00FFh System Configuration +// +//----------------------------------------------------- + +//2 SYS_ISO_CTRL +#define ISO_MD2PP BIT(0) +#define ISO_UA2USB BIT(1) +#define ISO_UD2CORE BIT(2) +#define ISO_PA2PCIE BIT(3) +#define ISO_PD2CORE BIT(4) +#define ISO_IP2MAC BIT(5) +#define ISO_DIOP BIT(6) +#define ISO_DIOE BIT(7) +#define ISO_EB2CORE BIT(8) +#define ISO_DIOR BIT(9) +#define PWC_EV12V BIT(15) + + +//2 SYS_FUNC_EN +#define FEN_BBRSTB BIT(0) +#define FEN_BB_GLB_RSTn BIT(1) +#define FEN_USBA BIT(2) +#define FEN_UPLL BIT(3) +#define FEN_USBD BIT(4) +#define FEN_DIO_PCIE BIT(5) +#define FEN_PCIEA BIT(6) +#define FEN_PPLL BIT(7) +#define FEN_PCIED BIT(8) +#define FEN_DIOE BIT(9) +#define FEN_CPUEN BIT(10) +#define FEN_DCORE BIT(11) +#define FEN_ELDR BIT(12) +#define FEN_EN_25_1 BIT(13) +#define FEN_HWPDN BIT(14) +#define FEN_MREGEN BIT(15) + +//2 APS_FSMCO +#define PFM_LDALL BIT(0) +#define PFM_ALDN BIT(1) +#define PFM_LDKP BIT(2) +#define PFM_WOWL BIT(3) +#define EnPDN BIT(4) +#define PDN_PL BIT(5) +#define APFM_ONMAC BIT(8) +#define APFM_OFF BIT(9) +#define APFM_RSM BIT(10) +#define AFSM_HSUS BIT(11) +#define AFSM_PCIE BIT(12) +#define APDM_MAC BIT(13) +#define APDM_HOST BIT(14) +#define APDM_HPDN BIT(15) +#define RDY_MACON BIT(16) +#define SUS_HOST BIT(17) +#define ROP_ALD BIT(20) +#define ROP_PWR BIT(21) +#define ROP_SPS BIT(22) +#define SOP_MRST BIT(25) +#define SOP_FUSE BIT(26) +#define SOP_ABG BIT(27) +#define SOP_AMB BIT(28) +#define SOP_RCK BIT(29) +#define SOP_A8M BIT(30) +#define XOP_BTCK BIT(31) + +//2 SYS_CLKR +#define ANAD16V_EN BIT(0) +#define ANA8M BIT(1) +#define MACSLP BIT(4) +#define LOADER_CLK_EN BIT(5) + + +//2 9346CR /REG_SYS_EEPROM_CTRL +#define BOOT_FROM_EEPROM BIT(4) +#define EEPROMSEL BIT(4) +#define EEPROM_EN BIT(5) + + +//2 RF_CTRL +#define RF_EN BIT(0) +#define RF_RSTB BIT(1) +#define RF_SDMRSTB BIT(2) + + +//2 LDOV12D_CTRL +#define LDV12_EN BIT(0) +#define LDV12_SDBY BIT(1) +#define LPLDO_HSM BIT(2) +#define LPLDO_LSM_DIS BIT(3) +#define _LDV12_VADJ(x) (((x) & 0xF) << 4) + + + +//2 EFUSE_TEST (For RTL8723 partially) +#define EF_TRPT BIT(7) +#define EF_CELL_SEL (BIT(8)|BIT(9)) // 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 +#define LDOE25_EN BIT(31) +#define EFUSE_SEL(x) (((x) & 0x3) << 8) +#define EFUSE_SEL_MASK 0x300 +#define EFUSE_WIFI_SEL_0 0x0 +#define EFUSE_BT_SEL_0 0x1 +#define EFUSE_BT_SEL_1 0x2 +#define EFUSE_BT_SEL_2 0x3 + + +//2 8051FWDL +//2 MCUFWDL +#define MCUFWDL_EN BIT(0) +#define MCUFWDL_RDY BIT(1) +#define FWDL_ChkSum_rpt BIT(2) +#define MACINI_RDY BIT(3) +#define BBINI_RDY BIT(4) +#define RFINI_RDY BIT(5) +#define WINTINI_RDY BIT(6) +#define RAM_DL_SEL BIT(7) +#define CPU_DL_READY BIT(15) /* add flag by gw for fw download ready 20130826 */ +#define ROM_DLEN BIT(19) +#define CPRST BIT(23) + + +//2 REG_SYS_CFG +#define XCLK_VLD BIT(0) +#define ACLK_VLD BIT(1) +#define UCLK_VLD BIT(2) +#define PCLK_VLD BIT(3) +#define PCIRSTB BIT(4) +#define V15_VLD BIT(5) +#define SW_OFFLOAD_EN BIT(7) +#define SIC_IDLE BIT(8) +#define BD_MAC2 BIT(9) +#define BD_MAC1 BIT(10) +#define IC_MACPHY_MODE BIT(11) +#define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) +#define BT_FUNC BIT(16) +#define VENDOR_ID BIT(19) +#define EXT_VENDOR_ID (BIT(18)|BIT(19)) //Currently only for RTL8723B +#define PAD_HWPD_IDN BIT(22) +#define TRP_VAUX_EN BIT(23) // RTL ID +#define TRP_BT_EN BIT(24) +#define BD_PKG_SEL BIT(25) +#define BD_HCI_SEL BIT(26) +#define TYPE_ID BIT(27) +#define RF_TYPE_ID BIT(27) + +#define RTL_ID BIT(23) // TestChip ID, 1:Test(RLE); 0:MP(RL) +#define SPS_SEL BIT(24) // 1:LDO regulator mode; 0:Switching regulator mode + + +#define CHIP_VER_RTL_MASK 0xF000 //Bit 12 ~ 15 +#define CHIP_VER_RTL_SHIFT 12 +#define EXT_VENDOR_ID_SHIFT 18 + +//2 REG_GPIO_OUTSTS (For RTL8723 only) +#define EFS_HCI_SEL (BIT(0)|BIT(1)) +#define PAD_HCI_SEL (BIT(2)|BIT(3)) +#define HCI_SEL (BIT(4)|BIT(5)) +#define PKG_SEL_HCI BIT(6) +#define FEN_GPS BIT(7) +#define FEN_BT BIT(8) +#define FEN_WL BIT(9) +#define FEN_PCI BIT(10) +#define FEN_USB BIT(11) +#define BTRF_HWPDN_N BIT(12) +#define WLRF_HWPDN_N BIT(13) +#define PDN_BT_N BIT(14) +#define PDN_GPS_N BIT(15) +#define BT_CTL_HWPDN BIT(16) +#define GPS_CTL_HWPDN BIT(17) +#define PPHY_SUSB BIT(20) +#define UPHY_SUSB BIT(21) +#define PCI_SUSEN BIT(22) +#define USB_SUSEN BIT(23) +#define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28)) + + +//----------------------------------------------------- +// +// 0x0100h ~ 0x01FFh MACTOP General Configuration +// +//----------------------------------------------------- + +//2 Function Enable Registers +//2 CR +#define HCI_TXDMA_EN BIT(0) +#define HCI_RXDMA_EN BIT(1) +#define TXDMA_EN BIT(2) +#define RXDMA_EN BIT(3) +#define PROTOCOL_EN BIT(4) +#define SCHEDULE_EN BIT(5) +#define MACTXEN BIT(6) +#define MACRXEN BIT(7) +#define ENSWBCN BIT(8) +#define ENSEC BIT(9) +#define CALTMR_EN BIT(10) // 32k CAL TMR enable + +// Network type +#define _NETTYPE(x) (((x) & 0x3) << 16) +#define MASK_NETTYPE 0x30000 +#define NT_NO_LINK 0x0 +#define NT_LINK_AD_HOC 0x1 +#define NT_LINK_AP 0x2 +#define NT_AS_AP 0x3 + +//2 PBP - Page Size Register +#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) +#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) +#define _PSRX_MASK 0xF +#define _PSTX_MASK 0xF0 +#define _PSRX(x) (x) +#define _PSTX(x) ((x) << 4) + +#define PBP_64 0x0 +#define PBP_128 0x1 +#define PBP_256 0x2 +#define PBP_512 0x3 +#define PBP_1024 0x4 + + +//2 TX/RXDMA +#define RXDMA_ARBBW_EN BIT(0) +#define RXSHFT_EN BIT(1) +#define RXDMA_AGG_EN BIT(2) +#define QS_VO_QUEUE BIT(8) +#define QS_VI_QUEUE BIT(9) +#define QS_BE_QUEUE BIT(10) +#define QS_BK_QUEUE BIT(11) +#define QS_MANAGER_QUEUE BIT(12) +#define QS_HIGH_QUEUE BIT(13) + +#define HQSEL_VOQ BIT(0) +#define HQSEL_VIQ BIT(1) +#define HQSEL_BEQ BIT(2) +#define HQSEL_BKQ BIT(3) +#define HQSEL_MGTQ BIT(4) +#define HQSEL_HIQ BIT(5) + +// For normal driver, 0x10C +#define _TXDMA_CMQ_MAP(x) (((x)&0x3) << 16) +#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) +#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) +#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) +#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 ) +#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 ) +#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 ) + +#define QUEUE_EXTRA 0 +#define QUEUE_LOW 1 +#define QUEUE_NORMAL 2 +#define QUEUE_HIGH 3 + + +//2 TRXFF_BNDY + + +//2 LLT_INIT +#define _LLT_NO_ACTIVE 0x0 +#define _LLT_WRITE_ACCESS 0x1 +#define _LLT_READ_ACCESS 0x2 + +#define _LLT_INIT_DATA(x) ((x) & 0xFF) +#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) +#define _LLT_OP(x) (((x) & 0x3) << 30) +#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) + + +//----------------------------------------------------- +// +// 0x0200h ~ 0x027Fh TXDMA Configuration +// +//----------------------------------------------------- +//2 RQPN +#define _HPQ(x) ((x) & 0xFF) +#define _LPQ(x) (((x) & 0xFF) << 8) +#define _PUBQ(x) (((x) & 0xFF) << 16) +#define _NPQ(x) ((x) & 0xFF) // NOTE: in RQPN_NPQ register +#define _EPQ(x) (((x) & 0xFF) << 16) // NOTE: in RQPN_EPQ register + + +#define HPQ_PUBLIC_DIS BIT(24) +#define LPQ_PUBLIC_DIS BIT(25) +#define LD_RQPN BIT(31) + + +//2 TDECTL +#define BLK_DESC_NUM_SHIFT 4 +#define BLK_DESC_NUM_MASK 0xF + + +//2 TXDMA_OFFSET_CHK +#define DROP_DATA_EN BIT(9) + +//2 AUTO_LLT +#define BIT_SHIFT_TXPKTNUM 24 +#define BIT_MASK_TXPKTNUM 0xff +#define BIT_TXPKTNUM(x) (((x) & BIT_MASK_TXPKTNUM) << BIT_SHIFT_TXPKTNUM) + +#define BIT_TDE_DBG_SEL BIT(23) +#define BIT_AUTO_INIT_LLT BIT(16) + +#define BIT_SHIFT_Tx_OQT_free_space 8 +#define BIT_MASK_Tx_OQT_free_space 0xff +#define BIT_Tx_OQT_free_space(x) (((x) & BIT_MASK_Tx_OQT_free_space) << BIT_SHIFT_Tx_OQT_free_space) + + +//----------------------------------------------------- +// +// 0x0280h ~ 0x028Bh RX DMA Configuration +// +//----------------------------------------------------- + +//2 REG_RXDMA_CONTROL, 0x0286h +// Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before +// this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear. +//#define RXPKT_RELEASE_POLL BIT(0) +// Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in +// this bit. FW can start releasing packets after RXDMA entering idle mode. +//#define RXDMA_IDLE BIT(1) +// When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host +// completed, and stop DMA packet to host. RXDMA will then report Default: 0; +//#define RW_RELEASE_EN BIT(2) + +//2 REG_RXPKT_NUM, 0x0284 +#define RXPKT_RELEASE_POLL BIT(16) +#define RXDMA_IDLE BIT(17) +#define RW_RELEASE_EN BIT(18) + +//----------------------------------------------------- +// +// 0x0400h ~ 0x047Fh Protocol Configuration +// +//----------------------------------------------------- +//2 FWHW_TXQ_CTRL +#define EN_AMPDU_RTY_NEW BIT(7) + + +//2 SPEC SIFS +#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) +#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) + +//2 RL +#define RETRY_LIMIT_SHORT_SHIFT 8 +#define RETRY_LIMIT_LONG_SHIFT 0 + +//----------------------------------------------------- +// +// 0x0500h ~ 0x05FFh EDCA Configuration +// +//----------------------------------------------------- + +//2 EDCA setting +#define AC_PARAM_TXOP_LIMIT_OFFSET 16 +#define AC_PARAM_ECW_MAX_OFFSET 12 +#define AC_PARAM_ECW_MIN_OFFSET 8 +#define AC_PARAM_AIFS_OFFSET 0 + + +#define _LRL(x) ((x) & 0x3F) +#define _SRL(x) (((x) & 0x3F) << 8) + + +//2 BCN_CTRL +#define EN_TXBCN_RPT BIT(2) +#define EN_BCN_FUNCTION BIT(3) +#define STOP_BCNQ BIT(6) +#define DIS_RX_BSSID_FIT BIT(6) + +#define DIS_ATIM BIT(0) +#define DIS_BCNQ_SUB BIT(1) +#define DIS_TSF_UDT BIT(4) + +// The same function but different bit field. +#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) +#define DIS_TSF_UDT0_TEST_CHIP BIT(5) + + +//2 ACMHWCTRL +#define AcmHw_HwEn BIT(0) +#define AcmHw_BeqEn BIT(1) +#define AcmHw_ViqEn BIT(2) +#define AcmHw_VoqEn BIT(3) +#define AcmHw_BeqStatus BIT(4) +#define AcmHw_ViqStatus BIT(5) +#define AcmHw_VoqStatus BIT(6) + +//2 //REG_DUAL_TSF_RST (0x553) +#define DUAL_TSF_RST_P2P BIT(4) + +//2 // REG_NOA_DESC_SEL (0x5CF) +#define NOA_DESC_SEL_0 0 +#define NOA_DESC_SEL_1 BIT(4) + +//----------------------------------------------------- +// +// 0x0600h ~ 0x07FFh WMAC Configuration +// +//----------------------------------------------------- + +//2 APSD_CTRL +#define APSDOFF BIT(6) + +//2 TCR +#define TSFRST BIT(0) +#define DIS_GCLK BIT(1) +#define PAD_SEL BIT(2) +#define PWR_ST BIT(6) +#define PWRBIT_OW_EN BIT(7) +#define ACRC BIT(8) +#define CFENDFORM BIT(9) +#define ICV BIT(10) + + +//2 RCR +#define AAP BIT(0) +#define APM BIT(1) +#define AM BIT(2) +#define AB BIT(3) +#define ADD3 BIT(4) +#define APWRMGT BIT(5) +#define CBSSID BIT(6) +#define CBSSID_DATA BIT(6) +#define CBSSID_BCN BIT(7) +#define ACRC32 BIT(8) +#define AICV BIT(9) +#define ADF BIT(11) +#define ACF BIT(12) +#define AMF BIT(13) +#define HTC_LOC_CTRL BIT(14) +#define UC_DATA_EN BIT(16) +#define BM_DATA_EN BIT(17) +#define MFBEN BIT(22) +#define LSIGEN BIT(23) +#define EnMBID BIT(24) +#define FORCEACK BIT(26) +#define APP_BASSN BIT(27) +#define APP_PHYSTS BIT(28) +#define APP_ICV BIT(29) +#define APP_MIC BIT(30) +#define APP_FCS BIT(31) + + +//2 SECCFG +#define SCR_TxUseDK BIT(0) //Force Tx Use Default Key +#define SCR_RxUseDK BIT(1) //Force Rx Use Default Key +#define SCR_TxEncEnable BIT(2) //Enable Tx Encryption +#define SCR_RxDecEnable BIT(3) //Enable Rx Decryption +#define SCR_SKByA2 BIT(4) //Search kEY BY A2 +#define SCR_NoSKMC BIT(5) //No Key Search Multicast +#define SCR_TXBCUSEDK BIT(6) // Force Tx Broadcast packets Use Default Key +#define SCR_RXBCUSEDK BIT(7) // Force Rx Broadcast packets Use Default Key +#define SCR_CHK_KEYID BIT(8) +#define SCR_CHK_BMC BIT(9) /* add option to support a2+keyid+bcm */ + +//----------------------------------------------------- +// +// SDIO Bus Specification +// +//----------------------------------------------------- + +// I/O bus domain address mapping +#define SDIO_LOCAL_BASE 0x10250000 +#define WLAN_IOREG_BASE 0x10260000 +#define FIRMWARE_FIFO_BASE 0x10270000 +#define TX_HIQ_BASE 0x10310000 +#define TX_MIQ_BASE 0x10320000 +#define TX_LOQ_BASE 0x10330000 +#define TX_EPQ_BASE 0x10350000 +#define RX_RX0FF_BASE 0x10340000 + +//SDIO host local register space mapping. +#define SDIO_LOCAL_MSK 0x0FFF +#define WLAN_IOREG_MSK 0x7FFF +#define WLAN_FIFO_MSK 0x1FFF // Aggregation Length[12:0] +#define WLAN_RX0FF_MSK 0x0003 + +#define SDIO_WITHOUT_REF_DEVICE_ID 0 // Without reference to the SDIO Device ID +#define SDIO_LOCAL_DEVICE_ID 0 // 0b[16], 000b[15:13] +#define WLAN_TX_HIQ_DEVICE_ID 4 // 0b[16], 100b[15:13] +#define WLAN_TX_MIQ_DEVICE_ID 5 // 0b[16], 101b[15:13] +#define WLAN_TX_LOQ_DEVICE_ID 6 // 0b[16], 110b[15:13] +#define WLAN_TX_EXQ_DEVICE_ID 3 // 0b[16], 011b[15:13] +#define WLAN_RX0FF_DEVICE_ID 7 // 0b[16], 111b[15:13] +#define WLAN_IOREG_DEVICE_ID 8 // 1b[16] + +//SDIO Tx Free Page Index +#define HI_QUEUE_IDX 0 +#define MID_QUEUE_IDX 1 +#define LOW_QUEUE_IDX 2 +#define PUBLIC_QUEUE_IDX 3 + +#define SDIO_MAX_TX_QUEUE 3 // HIQ, MIQ and LOQ +#define SDIO_MAX_RX_QUEUE 1 + +#define SDIO_REG_TX_CTRL 0x0000 // SDIO Tx Control +#define SDIO_REG_HIMR 0x0014 // SDIO Host Interrupt Mask +#define SDIO_REG_HISR 0x0018 // SDIO Host Interrupt Service Routine +#define SDIO_REG_HCPWM 0x0019 // HCI Current Power Mode +#define SDIO_REG_RX0_REQ_LEN 0x001C // RXDMA Request Length +#define SDIO_REG_OQT_FREE_PG 0x001E // OQT Free Page +#define SDIO_REG_FREE_TXPG 0x0020 // Free Tx Buffer Page +#define SDIO_REG_HCPWM1 0x0024 // HCI Current Power Mode 1 +#define SDIO_REG_HCPWM2 0x0026 // HCI Current Power Mode 2 +#define SDIO_REG_FREE_TXPG_SEQ 0x0028 // Free Tx Page Sequence +#define SDIO_REG_HTSFR_INFO 0x0030 // HTSF Informaion +#define SDIO_REG_HRPWM1 0x0080 // HCI Request Power Mode 1 +#define SDIO_REG_HRPWM2 0x0082 // HCI Request Power Mode 2 +#define SDIO_REG_HPS_CLKR 0x0084 // HCI Power Save Clock +#define SDIO_REG_HSUS_CTRL 0x0086 // SDIO HCI Suspend Control +#define SDIO_REG_HIMR_ON 0x0090 //SDIO Host Extension Interrupt Mask Always +#define SDIO_REG_HISR_ON 0x0091 //SDIO Host Extension Interrupt Status Always + +#define SDIO_HIMR_DISABLED 0 + +// RTL8723/RTL8188E SDIO Host Interrupt Mask Register +#define SDIO_HIMR_RX_REQUEST_MSK BIT0 +#define SDIO_HIMR_AVAL_MSK BIT1 +#define SDIO_HIMR_TXERR_MSK BIT2 +#define SDIO_HIMR_RXERR_MSK BIT3 +#define SDIO_HIMR_TXFOVW_MSK BIT4 +#define SDIO_HIMR_RXFOVW_MSK BIT5 +#define SDIO_HIMR_TXBCNOK_MSK BIT6 +#define SDIO_HIMR_TXBCNERR_MSK BIT7 +#define SDIO_HIMR_BCNERLY_INT_MSK BIT16 +#define SDIO_HIMR_C2HCMD_MSK BIT17 +#define SDIO_HIMR_CPWM1_MSK BIT18 +#define SDIO_HIMR_CPWM2_MSK BIT19 +#define SDIO_HIMR_HSISR_IND_MSK BIT20 +#define SDIO_HIMR_GTINT3_IND_MSK BIT21 +#define SDIO_HIMR_GTINT4_IND_MSK BIT22 +#define SDIO_HIMR_PSTIMEOUT_MSK BIT23 +#define SDIO_HIMR_OCPINT_MSK BIT24 +#define SDIO_HIMR_ATIMEND_MSK BIT25 +#define SDIO_HIMR_ATIMEND_E_MSK BIT26 +#define SDIO_HIMR_CTWEND_MSK BIT27 + +//RTL8188E SDIO Specific +#define SDIO_HIMR_MCU_ERR_MSK BIT28 +#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT29 + +// SDIO Host Interrupt Service Routine +#define SDIO_HISR_RX_REQUEST BIT0 +#define SDIO_HISR_AVAL BIT1 +#define SDIO_HISR_TXERR BIT2 +#define SDIO_HISR_RXERR BIT3 +#define SDIO_HISR_TXFOVW BIT4 +#define SDIO_HISR_RXFOVW BIT5 +#define SDIO_HISR_TXBCNOK BIT6 +#define SDIO_HISR_TXBCNERR BIT7 +#define SDIO_HISR_BCNERLY_INT BIT16 +#define SDIO_HISR_C2HCMD BIT17 +#define SDIO_HISR_CPWM1 BIT18 +#define SDIO_HISR_CPWM2 BIT19 +#define SDIO_HISR_HSISR_IND BIT20 +#define SDIO_HISR_GTINT3_IND BIT21 +#define SDIO_HISR_GTINT4_IND BIT22 +#define SDIO_HISR_PSTIMEOUT BIT23 +#define SDIO_HISR_OCPINT BIT24 +#define SDIO_HISR_ATIMEND BIT25 +#define SDIO_HISR_ATIMEND_E BIT26 +#define SDIO_HISR_CTWEND BIT27 + +//RTL8188E SDIO Specific +#define SDIO_HISR_MCU_ERR BIT28 +#define SDIO_HISR_TSF_BIT32_TOGGLE BIT29 + +#define MASK_SDIO_HISR_CLEAR (SDIO_HISR_TXERR |\ + SDIO_HISR_RXERR |\ + SDIO_HISR_TXFOVW |\ + SDIO_HISR_RXFOVW |\ + SDIO_HISR_TXBCNOK |\ + SDIO_HISR_TXBCNERR |\ + SDIO_HISR_C2HCMD |\ + SDIO_HISR_CPWM1 |\ + SDIO_HISR_CPWM2 |\ + SDIO_HISR_HSISR_IND |\ + SDIO_HISR_GTINT3_IND |\ + SDIO_HISR_GTINT4_IND |\ + SDIO_HISR_PSTIMEOUT |\ + SDIO_HISR_OCPINT) + +// SDIO HCI Suspend Control Register +#define HCI_RESUME_PWR_RDY BIT1 +#define HCI_SUS_CTRL BIT0 + +// SDIO Tx FIFO related +#define SDIO_TX_FREE_PG_QUEUE 4 // The number of Tx FIFO free page +#define SDIO_TX_FIFO_PAGE_SZ 128 + +#ifdef CONFIG_SDIO_HCI + #define MAX_TX_AGG_PACKET_NUMBER 0x8 +#else + #define MAX_TX_AGG_PACKET_NUMBER 0xFF + #define MAX_TX_AGG_PACKET_NUMBER_8812 64 +#endif + +//----------------------------------------------------- +// +// 0xFE00h ~ 0xFE55h USB Configuration +// +//----------------------------------------------------- + +//2 USB Information (0xFE17) +#define USB_IS_HIGH_SPEED 0 +#define USB_IS_FULL_SPEED 1 +#define USB_SPEED_MASK BIT(5) + +#define USB_NORMAL_SIE_EP_MASK 0xF +#define USB_NORMAL_SIE_EP_SHIFT 4 + +//2 Special Option +#define USB_AGG_EN BIT(3) + +// 0; Use interrupt endpoint to upload interrupt pkt +// 1; Use bulk endpoint to upload interrupt pkt, +#define INT_BULK_SEL BIT(4) + +//2REG_C2HEVT_CLEAR +#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message +#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. + + +//2REG_MULTI_FUNC_CTRL(For RTL8723 Only) +#define WL_HWPDN_EN BIT0 // Enable GPIO[9] as WiFi HW PDn source +#define WL_HWPDN_SL BIT1 // WiFi HW PDn polarity control +#define WL_FUNC_EN BIT2 // WiFi function enable +#define WL_HWROF_EN BIT3 // Enable GPIO[9] as WiFi RF HW PDn source +#define BT_HWPDN_EN BIT16 // Enable GPIO[11] as BT HW PDn source +#define BT_HWPDN_SL BIT17 // BT HW PDn polarity control +#define BT_FUNC_EN BIT18 // BT function enable +#define BT_HWROF_EN BIT19 // Enable GPIO[11] as BT/GPS RF HW PDn source +#define GPS_HWPDN_EN BIT20 // Enable GPIO[10] as GPS HW PDn source +#define GPS_HWPDN_SL BIT21 // GPS HW PDn polarity control +#define GPS_FUNC_EN BIT22 // GPS function enable + +//3 REG_LIFECTRL_CTRL +#define HAL92C_EN_PKT_LIFE_TIME_BK BIT3 +#define HAL92C_EN_PKT_LIFE_TIME_BE BIT2 +#define HAL92C_EN_PKT_LIFE_TIME_VI BIT1 +#define HAL92C_EN_PKT_LIFE_TIME_VO BIT0 + +#define HAL92C_MSDU_LIFE_TIME_UNIT 128 // in us, said by Tim. + +//2 8192D PartNo. +#define PARTNO_92D_NIC (BIT7|BIT6) +#define PARTNO_92D_NIC_REMARK (BIT5|BIT4) +#define PARTNO_SINGLE_BAND_VS BIT3 +#define PARTNO_SINGLE_BAND_VS_REMARK BIT1 +#define PARTNO_CONCURRENT_BAND_VC (BIT3|BIT2) +#define PARTNO_CONCURRENT_BAND_VC_REMARK (BIT1|BIT0) + +//======================================================== +// General definitions +//======================================================== +#ifdef CONFIG_USB_HCI + #define LAST_ENTRY_OF_TX_PKT_BUFFER_8188E(__Adapter) (175) +#else + #define LAST_ENTRY_OF_TX_PKT_BUFFER_8188E(__Adapter) ( IS_VENDOR_8188E_I_CUT_SERIES(__Adapter) ? 255 : 175 ) +#endif +#define LAST_ENTRY_OF_TX_PKT_BUFFER_8812 255 +#define LAST_ENTRY_OF_TX_PKT_BUFFER_8723B 255 +#define LAST_ENTRY_OF_TX_PKT_BUFFER_8192C 255 +#define LAST_ENTRY_OF_TX_PKT_BUFFER_8703B 255 +#define LAST_ENTRY_OF_TX_PKT_BUFFER_DUAL_MAC 127 +#define LAST_ENTRY_OF_TX_PKT_BUFFER_8188F 255 + +#define POLLING_LLT_THRESHOLD 20 +#if defined(CONFIG_RTL8723B) && defined(CONFIG_PCI_HCI) +#define POLLING_READY_TIMEOUT_COUNT 6000 +#else +#define POLLING_READY_TIMEOUT_COUNT 1000 +#endif + + +// GPIO BIT +#define HAL_8812A_HW_GPIO_WPS_BIT BIT2 +#define HAL_8192C_HW_GPIO_WPS_BIT BIT2 +#define HAL_8192EU_HW_GPIO_WPS_BIT BIT7 +#define HAL_8188E_HW_GPIO_WPS_BIT BIT7 + +#endif //__HAL_COMMON_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_data.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_data.h new file mode 100644 index 000000000..5a41e2564 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_data.h @@ -0,0 +1,665 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_DATA_H__ +#define __HAL_DATA_H__ + +#if 1//def CONFIG_SINGLE_IMG + +#include "../hal/phydm/phydm_precomp.h" +#ifdef CONFIG_BT_COEXIST +#include +#endif + +#ifdef CONFIG_SDIO_HCI +#include +#endif +#ifdef CONFIG_GSPI_HCI +#include +#endif +// +// For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. +// +typedef enum _RT_MULTI_FUNC{ + RT_MULTI_FUNC_NONE = 0x00, + RT_MULTI_FUNC_WIFI = 0x01, + RT_MULTI_FUNC_BT = 0x02, + RT_MULTI_FUNC_GPS = 0x04, +}RT_MULTI_FUNC,*PRT_MULTI_FUNC; +// +// For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. +// +typedef enum _RT_POLARITY_CTL { + RT_POLARITY_LOW_ACT = 0, + RT_POLARITY_HIGH_ACT = 1, +} RT_POLARITY_CTL, *PRT_POLARITY_CTL; + +// For RTL8723 regulator mode. by tynli. 2011.01.14. +typedef enum _RT_REGULATOR_MODE { + RT_SWITCHING_REGULATOR = 0, + RT_LDO_REGULATOR = 1, +} RT_REGULATOR_MODE, *PRT_REGULATOR_MODE; + +// +// Interface type. +// +typedef enum _INTERFACE_SELECT_PCIE{ + INTF_SEL0_SOLO_MINICARD = 0, // WiFi solo-mCard + INTF_SEL1_BT_COMBO_MINICARD = 1, // WiFi+BT combo-mCard + INTF_SEL2_PCIe = 2, // PCIe Card +} INTERFACE_SELECT_PCIE, *PINTERFACE_SELECT_PCIE; + + +typedef enum _INTERFACE_SELECT_USB{ + INTF_SEL0_USB = 0, // USB + INTF_SEL1_USB_High_Power = 1, // USB with high power PA + INTF_SEL2_MINICARD = 2, // Minicard + INTF_SEL3_USB_Solo = 3, // USB solo-Slim module + INTF_SEL4_USB_Combo = 4, // USB Combo-Slim module + INTF_SEL5_USB_Combo_MF = 5, // USB WiFi+BT Multi-Function Combo, i.e., Proprietary layout(AS-VAU) which is the same as SDIO card +} INTERFACE_SELECT_USB, *PINTERFACE_SELECT_USB; + +typedef enum _RT_AMPDU_BRUST_MODE{ + RT_AMPDU_BRUST_NONE = 0, + RT_AMPDU_BRUST_92D = 1, + RT_AMPDU_BRUST_88E = 2, + RT_AMPDU_BRUST_8812_4 = 3, + RT_AMPDU_BRUST_8812_8 = 4, + RT_AMPDU_BRUST_8812_12 = 5, + RT_AMPDU_BRUST_8812_15 = 6, + RT_AMPDU_BRUST_8723B = 7, +}RT_AMPDU_BRUST,*PRT_AMPDU_BRUST_MODE; + +/* +#define CHANNEL_MAX_NUMBER 14+24+21 // 14 is the max channel number +*/ +#define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, ch4~9, ch10~14 total three groups */ +#define MAX_PG_GROUP 13 + +// Tx Power Limit Table Size +#define MAX_REGULATION_NUM 4 +#define MAX_RF_PATH_NUM_IN_POWER_LIMIT_TABLE 4 +#define MAX_2_4G_BANDWIDTH_NUM 2 +#define MAX_RATE_SECTION_NUM 10 +#define MAX_5G_BANDWIDTH_NUM 4 + +#define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G 10 // CCK:1,OFDM:1, HT:4, VHT:4 +#define MAX_BASE_NUM_IN_PHY_REG_PG_5G 9 // OFDM:1, HT:4, VHT:4 + + +//###### duplicate code,will move to ODM ######### +//#define IQK_MAC_REG_NUM 4 +//#define IQK_ADDA_REG_NUM 16 + +//#define IQK_BB_REG_NUM 10 +#define IQK_BB_REG_NUM_92C 9 +#define IQK_BB_REG_NUM_92D 10 +#define IQK_BB_REG_NUM_test 6 + +#define IQK_Matrix_Settings_NUM_92D 1+24+21 + +//#define HP_THERMAL_NUM 8 +//###### duplicate code,will move to ODM ######### + +#ifdef CONFIG_USB_RX_AGGREGATION +typedef enum _USB_RX_AGG_MODE{ + USB_RX_AGG_DISABLE, + USB_RX_AGG_DMA, + USB_RX_AGG_USB, + USB_RX_AGG_MIX +}USB_RX_AGG_MODE; + +//#define MAX_RX_DMA_BUFFER_SIZE 10240 // 10K for 8192C RX DMA buffer + +#endif + +/* For store initial value of BB register */ +typedef struct _BB_INIT_REGISTER { + u16 offset; + u32 value; + +} BB_INIT_REGISTER, *PBB_INIT_REGISTER; + +#define PAGE_SIZE_128 128 +#define PAGE_SIZE_256 256 +#define PAGE_SIZE_512 512 + +#define HCI_SUS_ENTER 0 +#define HCI_SUS_LEAVING 1 +#define HCI_SUS_LEAVE 2 +#define HCI_SUS_ENTERING 3 +#define HCI_SUS_ERR 4 + +#ifdef CONFIG_AUTO_CHNL_SEL_NHM +typedef enum _ACS_OP { + ACS_INIT, /*ACS - Variable init*/ + ACS_RESET, /*ACS - NHM Counter reset*/ + ACS_SELECT, /*ACS - NHM Counter Statistics */ +} ACS_OP; + +typedef enum _ACS_STATE { + ACS_DISABLE, + ACS_ENABLE, +} ACS_STATE; + +struct auto_chan_sel { + ATOMIC_T state; + u8 ch; /* previous channel*/ +}; +#endif /*CONFIG_AUTO_CHNL_SEL_NHM*/ + +#define EFUSE_FILE_UNUSED 0 +#define EFUSE_FILE_FAILED 1 +#define EFUSE_FILE_LOADED 2 + +#define MACADDR_FILE_UNUSED 0 +#define MACADDR_FILE_FAILED 1 +#define MACADDR_FILE_LOADED 2 + +#define KFREE_FLAG_ON BIT0 +#define KFREE_FLAG_THERMAL_K_ON BIT1 + +#define MAX_IQK_INFO_BACKUP_CHNL_NUM 5 +#define MAX_IQK_INFO_BACKUP_REG_NUM 10 + +struct kfree_data_t { + u8 flag; + s8 bb_gain[BB_GAIN_NUM][RF_PATH_MAX]; + +#ifdef CONFIG_IEEE80211_BAND_5GHZ + s8 pa_bias_5g[RF_PATH_MAX]; + s8 pad_bias_5g[RF_PATH_MAX]; +#endif + s8 thermal; +}; + +bool kfree_data_is_bb_gain_empty(struct kfree_data_t *data); + +struct hal_spec_t { + char *ic_name; + u8 macid_num; + + u8 sec_cam_ent_num; + u8 sec_cap; + + u8 nss_num; + u8 band_cap; /* value of BAND_CAP_XXX */ + u8 bw_cap; /* value of BW_CAP_XXX */ + u8 proto_cap; /* value of PROTO_CAP_XXX */ + + u8 wl_func; /* value of WL_FUNC_XXX */ +}; + +struct hal_iqk_reg_backup { + u8 central_chnl; + u8 bw_mode; + u32 reg_backup[MAX_RF_PATH][MAX_IQK_INFO_BACKUP_REG_NUM]; +}; + +typedef struct hal_com_data +{ + HAL_VERSION VersionID; + RT_MULTI_FUNC MultiFunc; // For multi-function consideration. + RT_POLARITY_CTL PolarityCtl; // For Wifi PDn Polarity control. + RT_REGULATOR_MODE RegulatorMode; // switching regulator or LDO + u8 hw_init_completed; + /****** FW related ******/ + u16 FirmwareVersion; + u16 FirmwareVersionRev; + u16 FirmwareSubVersion; + u16 FirmwareSignature; + u8 RegFWOffload; + u8 fw_ractrl; + u8 FwRsvdPageStartOffset; /* 2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ.*/ + u8 LastHMEBoxNum; /* H2C - for host message to fw */ + + /****** current WIFI_PHY values ******/ + WIRELESS_MODE CurrentWirelessMode; + CHANNEL_WIDTH CurrentChannelBW; + BAND_TYPE CurrentBandType; /* 0:2.4G, 1:5G */ + BAND_TYPE BandSet; + u8 CurrentChannel; + u8 CurrentCenterFrequencyIndex1; + u8 nCur40MhzPrimeSC; /* Control channel sub-carrier */ + u8 nCur80MhzPrimeSC; /* used for primary 40MHz of 80MHz mode */ + BOOLEAN bSwChnlAndSetBWInProgress; + u8 bDisableSWChannelPlan; /* flag of disable software change channel plan */ + u16 BasicRateSet; + u32 ReceiveConfig; + BOOLEAN bSwChnl; + BOOLEAN bSetChnlBW; + BOOLEAN bChnlBWInitialized; +#ifdef CONFIG_AUTO_CHNL_SEL_NHM + struct auto_chan_sel acs; +#endif + /****** rf_ctrl *****/ + u8 rf_chip; + u8 rf_type; + u8 PackageType; + u8 NumTotalRFPath; + + /****** Debug ******/ + u16 ForcedDataRate; /* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */ + u8 u1ForcedIgiLb; /* forced IGI lower bound */ + u8 bDumpRxPkt; + u8 bDumpTxPkt; + u8 bDisableTXPowerTraining; + + + /****** EEPROM setting.******/ + u8 bautoload_fail_flag; + u8 efuse_file_status; + u8 macaddr_file_status; + u8 EepromOrEfuse; + u8 efuse_eeprom_data[EEPROM_MAX_SIZE]; /*92C:256bytes, 88E:512bytes, we use union set (512bytes)*/ + u8 InterfaceSel; /* board type kept in eFuse */ + u16 CustomerID; + + u16 EEPROMVID; + u16 EEPROMSVID; +#ifdef CONFIG_USB_HCI + u16 EEPROMPID; + u16 EEPROMSDID; +#endif +#ifdef CONFIG_PCI_HCI + u16 EEPROMDID; + u16 EEPROMSMID; +#endif + + u8 EEPROMCustomerID; + u8 EEPROMSubCustomerID; + u8 EEPROMVersion; + u8 EEPROMRegulatory; + u8 EEPROMThermalMeter; + u8 EEPROMBluetoothCoexist; + u8 EEPROMBluetoothType; + u8 EEPROMBluetoothAntNum; + u8 EEPROMBluetoothAntIsolation; + u8 EEPROMBluetoothRadioShared; + u8 bTXPowerDataReadFromEEPORM; + u8 EEPROMMACAddr[ETH_ALEN]; + +#ifdef CONFIG_RF_POWER_TRIM + u8 EEPROMRFGainOffset; + u8 EEPROMRFGainVal; + struct kfree_data_t kfree_data; +#endif /*CONFIG_RF_POWER_TRIM*/ + +#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) + u8 adjuseVoltageVal; +#endif + u8 EfuseUsedPercentage; + u16 EfuseUsedBytes; + /*u8 EfuseMap[2][HWSET_MAX_SIZE_JAGUAR];*/ + EFUSE_HAL EfuseHal; + + /*---------------------------------------------------------------------------------*/ + //3 [2.4G] + u8 Index24G_CCK_Base[MAX_RF_PATH][CENTER_CH_2G_NUM]; + u8 Index24G_BW40_Base[MAX_RF_PATH][CENTER_CH_2G_NUM]; + //If only one tx, only BW20 and OFDM are used. + s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + //3 [5G] + u8 Index5G_BW40_Base[MAX_RF_PATH][CENTER_CH_5G_ALL_NUM]; + u8 Index5G_BW80_Base[MAX_RF_PATH][CENTER_CH_5G_80M_NUM]; + s8 OFDM_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW20_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW40_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW80_5G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + + u8 Regulation2_4G; + u8 Regulation5G; + + u8 TxPwrInPercentage; + + /******************************** + * TX power by rate table at most 4RF path. + * The register is + * + * VHT TX power by rate off setArray = + * Band:-2G&5G = 0 / 1 + * RF: at most 4*4 = ABCD=0/1/2/3 + * CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11 + **********************************/ + u8 TxPwrByRateTable; + u8 TxPwrByRateBand; + s8 TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_BAND] + [TX_PWR_BY_RATE_NUM_RF] + [TX_PWR_BY_RATE_NUM_RF] + [TX_PWR_BY_RATE_NUM_RATE]; + //---------------------------------------------------------------------------------// + + /* + //2 Power Limit Table + u8 TxPwrLevelCck[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; + u8 TxPwrLevelHT40_1S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr + u8 TxPwrLevelHT40_2S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr + s8 TxPwrHt20Diff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff + u8 TxPwrLegacyHtDiff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff + */ + + u8 tx_pwr_lmt_5g_20_40_ref; + + // Power Limit Table for 2.4G + s8 TxPwrLimit_2_4G[MAX_REGULATION_NUM] + [MAX_2_4G_BANDWIDTH_NUM] + [MAX_RATE_SECTION_NUM] + [CENTER_CH_2G_NUM] + [MAX_RF_PATH]; + + // Power Limit Table for 5G + s8 TxPwrLimit_5G[MAX_REGULATION_NUM] + [MAX_5G_BANDWIDTH_NUM] + [MAX_RATE_SECTION_NUM] + [CENTER_CH_5G_ALL_NUM] + [MAX_RF_PATH]; + + + // Store the original power by rate value of the base of each rate section of rf path A & B + u8 TxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF] + [TX_PWR_BY_RATE_NUM_RF] + [MAX_BASE_NUM_IN_PHY_REG_PG_2_4G]; + u8 TxPwrByRateBase5G[TX_PWR_BY_RATE_NUM_RF] + [TX_PWR_BY_RATE_NUM_RF] + [MAX_BASE_NUM_IN_PHY_REG_PG_5G]; + + u8 txpwr_by_rate_loaded:1; + u8 txpwr_by_rate_from_file:1; + u8 txpwr_limit_loaded:1; + u8 txpwr_limit_from_file:1; + + // For power group + /* + u8 PwrGroupHT20[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; + u8 PwrGroupHT40[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; + */ + u8 PGMaxGroup; + + // The current Tx Power Level + u8 CurrentCckTxPwrIdx; + u8 CurrentOfdm24GTxPwrIdx; + u8 CurrentBW2024GTxPwrIdx; + u8 CurrentBW4024GTxPwrIdx; + + // Read/write are allow for following hardware information variables + u8 pwrGroupCnt; + u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16]; + u32 CCKTxPowerLevelOriginalOffset; + + u8 CrystalCap; + + u8 PAType_2G; + u8 PAType_5G; + u8 LNAType_2G; + u8 LNAType_5G; + u8 ExternalPA_2G; + u8 ExternalLNA_2G; + u8 ExternalPA_5G; + u8 ExternalLNA_5G; + u16 TypeGLNA; + u16 TypeGPA; + u16 TypeALNA; + u16 TypeAPA; + u16 RFEType; + + u8 bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */ + u32 AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */ + + BB_REGISTER_DEFINITION_T PHYRegDef[MAX_RF_PATH]; //Radio A/B/C/D + + u32 RfRegChnlVal[MAX_RF_PATH]; + + //RDG enable + BOOLEAN bRDGEnable; + + u8 RegTxPause; + // Beacon function related global variable. + u8 RegBcnCtrlVal; + u8 RegFwHwTxQCtrl; + u8 RegReg542; + u8 RegCR_1; + u8 Reg837; + u16 RegRRSR; + + /****** antenna diversity ******/ + u8 AntDivCfg; + u8 AntDetection; + u8 TRxAntDivType; + u8 ant_path; //for 8723B s0/s1 selection + u32 AntennaTxPath; /* Antenna path Tx */ + u32 AntennaRxPath; /* Antenna path Rx */ + u8 sw_antdiv_bl_state; + + /******** PHY DM & DM Section **********/ + u8 DM_Type; + _lock IQKSpinLock; + u8 INIDATA_RATE[MACID_NUM_SW_LIMIT]; + /* Upper and Lower Signal threshold for Rate Adaptive*/ + int EntryMinUndecoratedSmoothedPWDB; + int EntryMaxUndecoratedSmoothedPWDB; + int MinUndecoratedPWDBForDM; + DM_ODM_T odmpriv; + u8 bIQKInitialized; + u8 bNeedIQK; + /******** PHY DM & DM Section **********/ + + + + // 2010/08/09 MH Add CU power down mode. + BOOLEAN pwrdown; + + // Add for dual MAC 0--Mac0 1--Mac1 + u32 interfaceIndex; + +#ifdef CONFIG_P2P + u8 p2p_ps_offload; +#endif + /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */ + u8 bMacPwrCtrlOn; + u8 hci_sus_state; + + u8 RegIQKFWOffload; + struct submit_ctx iqk_sctx; + + RT_AMPDU_BRUST AMPDUBurstMode; //92C maybe not use, but for compile successfully + + u8 OutEpQueueSel; + u8 OutEpNumber; + +#if defined (CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + // + // For SDIO Interface HAL related + // + + // + // SDIO ISR Related + // +// u32 IntrMask[1]; +// u32 IntrMaskToSet[1]; +// LOG_INTERRUPT InterruptLog; + u32 sdio_himr; + u32 sdio_hisr; + + // + // SDIO Tx FIFO related. + // + // HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg + u8 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE]; + _lock SdioTxFIFOFreePageLock; + u8 SdioTxOQTMaxFreeSpace; + u8 SdioTxOQTFreeSpace; + + // + // SDIO Rx FIFO related. + // + u8 SdioRxFIFOCnt; + u16 SdioRxFIFOSize; + + u32 sdio_tx_max_len[SDIO_MAX_TX_QUEUE];// H, N, L, used for sdio tx aggregation max length per queue +#endif //CONFIG_SDIO_HCI + +#ifdef CONFIG_USB_HCI + + // 2010/12/10 MH Add for USB aggreation mode dynamic shceme. + BOOLEAN UsbRxHighSpeedMode; + BOOLEAN UsbTxVeryHighSpeedMode; + u32 UsbBulkOutSize; + BOOLEAN bSupportUSB3; + + // Interrupt relatd register information. + u32 IntArray[3];//HISR0,HISR1,HSISR + u32 IntrMask[3]; + u8 C2hArray[16]; + #ifdef CONFIG_USB_TX_AGGREGATION + u8 UsbTxAggMode; + u8 UsbTxAggDescNum; + #endif // CONFIG_USB_TX_AGGREGATION + + #ifdef CONFIG_USB_RX_AGGREGATION + u16 HwRxPageSize; // Hardware setting + u32 MaxUsbRxAggBlock; + + USB_RX_AGG_MODE UsbRxAggMode; + u8 UsbRxAggBlockCount; /* FOR USB Mode, USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed */ + u8 UsbRxAggBlockTimeout; + u8 UsbRxAggPageCount; /* FOR DMA Mode, 8192C DMA page count*/ + u8 UsbRxAggPageTimeout; + + u8 RegAcUsbDmaSize; + u8 RegAcUsbDmaTime; + #endif//CONFIG_USB_RX_AGGREGATION +#endif //CONFIG_USB_HCI + + +#ifdef CONFIG_PCI_HCI + // + // EEPROM setting. + // + u32 TransmitConfig; + u32 IntrMaskToSet[2]; + u32 IntArray[2]; + u32 IntrMask[2]; + u32 SysIntArray[1]; + u32 SysIntrMask[1]; + u32 IntrMaskReg[2]; + u32 IntrMaskDefault[2]; + + BOOLEAN bL1OffSupport; + BOOLEAN bSupportBackDoor; + + u8 bDefaultAntenna; + + u8 bInterruptMigration; + u8 bDisableTxInt; + + u16 RxTag; +#endif //CONFIG_PCI_HCI + + +#ifdef DBG_CONFIG_ERROR_DETECT + struct sreset_priv srestpriv; +#endif //#ifdef DBG_CONFIG_ERROR_DETECT + +#ifdef CONFIG_BT_COEXIST + // For bluetooth co-existance + BT_COEXIST bt_coexist; +#endif // CONFIG_BT_COEXIST + +#if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8703B) || defined(CONFIG_RTL8188F) + #ifndef CONFIG_PCI_HCI // mutual exclusive with PCI -- so they're SDIO and GSPI + // Interrupt relatd register information. + u32 SysIntrStatus; + u32 SysIntrMask; + #endif +#endif /*endif CONFIG_RTL8723B */ + +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + char para_file_buf[MAX_PARA_FILE_BUF_LEN]; + char *mac_reg; + u32 mac_reg_len; + char *bb_phy_reg; + u32 bb_phy_reg_len; + char *bb_agc_tab; + u32 bb_agc_tab_len; + char *bb_phy_reg_pg; + u32 bb_phy_reg_pg_len; + char *bb_phy_reg_mp; + u32 bb_phy_reg_mp_len; + char *rf_radio_a; + u32 rf_radio_a_len; + char *rf_radio_b; + u32 rf_radio_b_len; + char *rf_tx_pwr_track; + u32 rf_tx_pwr_track_len; + char *rf_tx_pwr_lmt; + u32 rf_tx_pwr_lmt_len; +#endif + +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR + s16 noise[ODM_MAX_CHANNEL_NUM]; +#endif + + struct hal_spec_t hal_spec; + + u8 RfKFreeEnable; + u8 RfKFree_ch_group; + BOOLEAN bCCKinCH14; + BB_INIT_REGISTER RegForRecover[5]; + +#if defined(CONFIG_PCI_HCI) && defined(RTL8814AE_SW_BCN) + BOOLEAN bCorrectBCN; +#endif + + struct hal_iqk_reg_backup iqk_reg_backup[MAX_IQK_INFO_BACKUP_CHNL_NUM]; +} HAL_DATA_COMMON, *PHAL_DATA_COMMON; + + + +typedef struct hal_com_data HAL_DATA_TYPE, *PHAL_DATA_TYPE; +#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData)) +#define GET_HAL_SPEC(__pAdapter) (&(GET_HAL_DATA((__pAdapter))->hal_spec)) +#define GET_ODM(__pAdapter) (&(GET_HAL_DATA((__pAdapter))->odmpriv)) + +#define GET_HAL_RFPATH_NUM(__pAdapter) (((HAL_DATA_TYPE *)((__pAdapter)->HalData))->NumTotalRFPath ) +#define RT_GetInterfaceSelection(_Adapter) (GET_HAL_DATA(_Adapter)->InterfaceSel) +#define GET_RF_TYPE(__pAdapter) (GET_HAL_DATA(__pAdapter)->rf_type) +#define GET_KFREE_DATA(_adapter) (&(GET_HAL_DATA((_adapter))->kfree_data)) + +#define SUPPORT_HW_RADIO_DETECT(Adapter) ( RT_GetInterfaceSelection(Adapter) == INTF_SEL2_MINICARD ||\ + RT_GetInterfaceSelection(Adapter) == INTF_SEL3_USB_Solo ||\ + RT_GetInterfaceSelection(Adapter) == INTF_SEL4_USB_Combo) + +#define get_hal_mac_addr(adapter) (GET_HAL_DATA(adapter)->EEPROMMACAddr) +#define is_boot_from_eeprom(adapter) (GET_HAL_DATA(adapter)->EepromOrEfuse) +#define rtw_get_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed) +#define rtw_is_hw_init_completed(adapter) (GET_HAL_DATA(adapter)->hw_init_completed == _TRUE) +#endif + +#ifdef CONFIG_AUTO_CHNL_SEL_NHM +#define GET_ACS_STATE(padapter) (ATOMIC_READ(&GET_HAL_DATA(padapter)->acs.state)) +#define SET_ACS_STATE(padapter, set_state) (ATOMIC_SET(&GET_HAL_DATA(padapter)->acs.state, set_state)) +#define rtw_get_acs_channel(padapter) (GET_HAL_DATA(padapter)->acs.ch) +#define rtw_set_acs_channel(padapter, survey_ch) (GET_HAL_DATA(padapter)->acs.ch = survey_ch) +#endif /*CONFIG_AUTO_CHNL_SEL_NHM*/ + +#endif //__HAL_DATA_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_gspi.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_gspi.h new file mode 100644 index 000000000..f5880e274 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_gspi.h @@ -0,0 +1,32 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_GSPI_H_ +#define __HAL_GSPI_H_ + +#define ffaddr2deviceId(pdvobj, addr) (pdvobj->Queue2Pipe[addr]) + +u8 rtw_hal_gspi_max_txoqt_free_space(_adapter *padapter); +u8 rtw_hal_gspi_query_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum); +void rtw_hal_gspi_update_tx_freepage(_adapter *padapter, u8 PageIdx, u8 RequiredPageNum); +void rtw_hal_set_gspi_tx_max_length(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ); +u32 rtw_hal_get_gspi_tx_max_length(PADAPTER padapter, u8 queue_idx); + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_ic_cfg.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_ic_cfg.h new file mode 100644 index 000000000..0c8371eb6 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_ic_cfg.h @@ -0,0 +1,93 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_IC_CFG_H__ +#define __HAL_IC_CFG_H__ + +#define RTL8188E_SUPPORT 0 +#define RTL8812A_SUPPORT 0 +#define RTL8821A_SUPPORT 0 +#define RTL8723B_SUPPORT 0 +#define RTL8192E_SUPPORT 0 +#define RTL8814A_SUPPORT 0 +#define RTL8195A_SUPPORT 0 +#define RTL8703B_SUPPORT 0 +#define RTL8188F_SUPPORT 0 +#define RTL8822B_SUPPORT 0 +#define RTL8821B_SUPPORT 0 + +/*#if (RTL8188E_SUPPORT==1)*/ +#define RATE_ADAPTIVE_SUPPORT 0 +#define POWER_TRAINING_ACTIVE 0 + +#ifdef CONFIG_MULTIDRV +#endif + +#ifdef CONFIG_RTL8188E +#undef RTL8188E_SUPPORT +#undef RATE_ADAPTIVE_SUPPORT +#undef POWER_TRAINING_ACTIVE + +#define RTL8188E_SUPPORT 1 +#define RATE_ADAPTIVE_SUPPORT 1 +#define POWER_TRAINING_ACTIVE 1 +#endif + +#ifdef CONFIG_RTL8812A +#undef RTL8812A_SUPPORT +#define RTL8812A_SUPPORT 1 +#endif + +#ifdef CONFIG_RTL8821A +#undef RTL8821A_SUPPORT +#define RTL8821A_SUPPORT 1 +#endif + +#ifdef CONFIG_RTL8192E +#undef RTL8192E_SUPPORT +#define RTL8192E_SUPPORT 1 +#endif + +#ifdef CONFIG_RTL8723B +#undef RTL8723B_SUPPORT +#define RTL8723B_SUPPORT 1 +#endif + +#ifdef CONFIG_RTL8814A +#undef RTL8814A_SUPPORT +#define RTL8814A_SUPPORT 1 +#endif + +#ifdef CONFIG_RTL8703B +#undef RTL8703B_SUPPORT +#define RTL8703B_SUPPORT 1 +#endif + +#ifdef CONFIG_RTL8188F +#undef RTL8188F_SUPPORT +#define RTL8188F_SUPPORT 1 +#endif + +#ifdef CONFIG_RTL8822B +#undef RTL8822B_SUPPORT +#define RTL8822B_SUPPORT 1 +#endif + +#endif /*__HAL_IC_CFG_H__*/ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_intf.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_intf.h new file mode 100644 index 000000000..29a0dcf41 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_intf.h @@ -0,0 +1,673 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_INTF_H__ +#define __HAL_INTF_H__ + + +enum RTL871X_HCI_TYPE { + RTW_PCIE = BIT0, + RTW_USB = BIT1, + RTW_SDIO = BIT2, + RTW_GSPI = BIT3, +}; + +enum _CHIP_TYPE { + + NULL_CHIP_TYPE, + RTL8188E, + RTL8192E, + RTL8812, + RTL8821, //RTL8811 + RTL8723B, + RTL8814A, + RTL8703B, + RTL8188F, + MAX_CHIP_TYPE +}; + +extern const u32 _chip_type_to_odm_ic_type[]; +#define chip_type_to_odm_ic_type(chip_type) (((chip_type) >= MAX_CHIP_TYPE) ? _chip_type_to_odm_ic_type[MAX_CHIP_TYPE] : _chip_type_to_odm_ic_type[(chip_type)]) + +typedef enum _HAL_HW_TIMER_TYPE { + HAL_TIMER_NONE = 0, + HAL_TIMER_TXBF = 1, + HAL_TIMER_EARLYMODE = 2, +} HAL_HW_TIMER_TYPE, *PHAL_HW_TIMER_TYPE; + + +typedef enum _HW_VARIABLES{ + HW_VAR_MEDIA_STATUS, + HW_VAR_MEDIA_STATUS1, + HW_VAR_SET_OPMODE, + HW_VAR_MAC_ADDR, + HW_VAR_BSSID, + HW_VAR_INIT_RTS_RATE, + HW_VAR_BASIC_RATE, + HW_VAR_TXPAUSE, + HW_VAR_BCN_FUNC, + HW_VAR_CORRECT_TSF, + HW_VAR_CHECK_BSSID, + HW_VAR_MLME_DISCONNECT, + HW_VAR_MLME_SITESURVEY, + HW_VAR_MLME_JOIN, + HW_VAR_ON_RCR_AM, + HW_VAR_OFF_RCR_AM, + HW_VAR_BEACON_INTERVAL, + HW_VAR_SLOT_TIME, + HW_VAR_RESP_SIFS, + HW_VAR_ACK_PREAMBLE, + HW_VAR_SEC_CFG, + HW_VAR_SEC_DK_CFG, + HW_VAR_BCN_VALID, + HW_VAR_RF_TYPE, + /* PHYDM odm->SupportAbility */ + HW_VAR_CAM_EMPTY_ENTRY, + HW_VAR_CAM_INVALID_ALL, + HW_VAR_AC_PARAM_VO, + HW_VAR_AC_PARAM_VI, + HW_VAR_AC_PARAM_BE, + HW_VAR_AC_PARAM_BK, + HW_VAR_ACM_CTRL, + HW_VAR_AMPDU_MIN_SPACE, + HW_VAR_AMPDU_FACTOR, + HW_VAR_RXDMA_AGG_PG_TH, + HW_VAR_SET_RPWM, + HW_VAR_CPWM, + HW_VAR_H2C_FW_PWRMODE, + HW_VAR_H2C_PS_TUNE_PARAM, + HW_VAR_H2C_FW_JOINBSSRPT, + HW_VAR_FWLPS_RF_ON, + HW_VAR_H2C_FW_P2P_PS_OFFLOAD, + HW_VAR_TRIGGER_GPIO_0, + HW_VAR_BT_SET_COEXIST, + HW_VAR_BT_ISSUE_DELBA, + HW_VAR_SWITCH_EPHY_WoWLAN, + HW_VAR_EFUSE_USAGE, + HW_VAR_EFUSE_BYTES, + HW_VAR_EFUSE_BT_USAGE, + HW_VAR_EFUSE_BT_BYTES, + HW_VAR_FIFO_CLEARN_UP, + HW_VAR_RESTORE_HW_SEQ, + HW_VAR_CHECK_TXBUF, + HW_VAR_PCIE_STOP_TX_DMA, + HW_VAR_APFM_ON_MAC, //Auto FSM to Turn On, include clock, isolation, power control for MAC only + HW_VAR_HCI_SUS_STATE, + // The valid upper nav range for the HW updating, if the true value is larger than the upper range, the HW won't update it. + // Unit in microsecond. 0 means disable this function. +#ifdef CONFIG_GPIO_WAKEUP + HW_SET_GPIO_WL_CTRL, +#endif + HW_VAR_SYS_CLKR, + HW_VAR_NAV_UPPER, + HW_VAR_C2H_HANDLE, + HW_VAR_RPT_TIMER_SETTING, + HW_VAR_TX_RPT_MAX_MACID, + HW_VAR_CHK_HI_QUEUE_EMPTY, + HW_VAR_DL_BCN_SEL, + HW_VAR_AMPDU_MAX_TIME, + HW_VAR_WIRELESS_MODE, + HW_VAR_USB_MODE, + HW_VAR_PORT_SWITCH, + HW_VAR_DO_IQK, + HW_VAR_DM_IN_LPS, + HW_VAR_SET_REQ_FW_PS, + HW_VAR_FW_PS_STATE, + HW_VAR_SOUNDING_ENTER, + HW_VAR_SOUNDING_LEAVE, + HW_VAR_SOUNDING_RATE, + HW_VAR_SOUNDING_STATUS, + HW_VAR_SOUNDING_FW_NDPA, + HW_VAR_SOUNDING_CLK, +/*Add by YuChen for TXBF HW timer*/ + HW_VAR_HW_REG_TIMER_INIT, + HW_VAR_HW_REG_TIMER_RESTART, + HW_VAR_HW_REG_TIMER_START, + HW_VAR_HW_REG_TIMER_STOP, +/*Add by YuChen for TXBF HW timer*/ + HW_VAR_DL_RSVD_PAGE, + HW_VAR_MACID_LINK, + HW_VAR_MACID_NOLINK, + HW_VAR_MACID_SLEEP, + HW_VAR_MACID_WAKEUP, + HW_VAR_DUMP_MAC_QUEUE_INFO, + HW_VAR_ASIX_IOT, + HW_VAR_EN_HW_UPDATE_TSF, + HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, + HW_VAR_CH_SW_IQK_INFO_BACKUP, + HW_VAR_CH_SW_IQK_INFO_RESTORE, +#ifdef CONFIG_TDLS + HW_VAR_TDLS_WRCR, + HW_VAR_TDLS_RS_RCR, +#ifdef CONFIG_TDLS_CH_SW + HW_VAR_TDLS_BCN_EARLY_C2H_RPT +#endif +#endif +}HW_VARIABLES; + +typedef enum _HAL_DEF_VARIABLE{ + HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, + HAL_DEF_IS_SUPPORT_ANT_DIV, + HAL_DEF_DRVINFO_SZ, + HAL_DEF_MAX_RECVBUF_SZ, + HAL_DEF_RX_PACKET_OFFSET, + HAL_DEF_RX_DMA_SZ_WOW, + HAL_DEF_RX_DMA_SZ, + HAL_DEF_RX_PAGE_SIZE, + HAL_DEF_DBG_DUMP_RXPKT,//for dbg + HAL_DEF_RA_DECISION_RATE, + HAL_DEF_RA_SGI, + HAL_DEF_PT_PWR_STATUS, + HAL_DEF_TX_LDPC, // LDPC support + HAL_DEF_RX_LDPC, // LDPC support + HAL_DEF_TX_STBC, // TX STBC support + HAL_DEF_RX_STBC, // RX STBC support + HAL_DEF_EXPLICIT_BEAMFORMER,// Explicit Compressed Steering Capable + HAL_DEF_EXPLICIT_BEAMFORMEE,// Explicit Compressed Beamforming Feedback Capable + HAL_DEF_BEAMFORMER_CAP, + HAL_DEF_BEAMFORMEE_CAP, + HW_VAR_MAX_RX_AMPDU_FACTOR, + HW_DEF_RA_INFO_DUMP, + HAL_DEF_DBG_DUMP_TXPKT, + + HAL_DEF_TX_PAGE_SIZE, + HAL_DEF_TX_PAGE_BOUNDARY, + HAL_DEF_TX_PAGE_BOUNDARY_WOWLAN, + HAL_DEF_ANT_DETECT,//to do for 8723a + HAL_DEF_PCI_SUUPORT_L1_BACKDOOR, // Determine if the L1 Backdoor setting is turned on. + HAL_DEF_PCI_AMD_L1_SUPPORT, + HAL_DEF_PCI_ASPM_OSC, // Support for ASPM OSC, added by Roger, 2013.03.27. + HAL_DEF_MACID_SLEEP, // Support for MACID sleep + HAL_DEF_DBG_DIS_PWT, //disable Tx power training or not. + HAL_DEF_EFUSE_USAGE, /* Get current EFUSE utilization. 2008.12.19. Added by Roger. */ + HAL_DEF_EFUSE_BYTES, + HW_VAR_BEST_AMPDU_DENSITY, +}HAL_DEF_VARIABLE; + +typedef enum _HAL_ODM_VARIABLE{ + HAL_ODM_STA_INFO, + HAL_ODM_P2P_STATE, + HAL_ODM_WIFI_DISPLAY_STATE, + HAL_ODM_NOISE_MONITOR, + HAL_ODM_REGULATION, + HAL_ODM_INITIAL_GAIN, + HAL_ODM_FA_CNT_DUMP, + HAL_ODM_DBG_FLAG, + HAL_ODM_DBG_LEVEL, + HAL_ODM_RX_INFO_DUMP, +#ifdef CONFIG_AUTO_CHNL_SEL_NHM + HAL_ODM_AUTO_CHNL_SEL, +#endif +#ifdef CONFIG_ANTENNA_DIVERSITY + HAL_ODM_ANTDIV_SELECT +#endif +}HAL_ODM_VARIABLE; + +typedef enum _HAL_INTF_PS_FUNC{ + HAL_USB_SELECT_SUSPEND, + HAL_MAX_ID, +}HAL_INTF_PS_FUNC; + +typedef s32 (*c2h_id_filter)(u8 *c2h_evt); + +struct hal_ops { + /*** initialize section ***/ + void (*read_chip_version)(_adapter *padapter); + void (*init_default_value)(_adapter *padapter); + void (*intf_chip_configure)(_adapter *padapter); + void (*read_adapter_info)(_adapter *padapter); + u32 (*hal_power_on)(_adapter *padapter); + void (*hal_power_off)(_adapter *padapter); + u32 (*hal_init)(_adapter *padapter); + u32 (*hal_deinit)(_adapter *padapter); + void (*dm_init)(_adapter *padapter); + void (*dm_deinit)(_adapter *padapter); + + /*** xmit section ***/ + s32 (*init_xmit_priv)(_adapter *padapter); + void (*free_xmit_priv)(_adapter *padapter); + s32 (*hal_xmit)(_adapter *padapter, struct xmit_frame *pxmitframe); + /* + * mgnt_xmit should be implemented to run in interrupt context + */ + s32 (*mgnt_xmit)(_adapter *padapter, struct xmit_frame *pmgntframe); + s32 (*hal_xmitframe_enqueue)(_adapter *padapter, struct xmit_frame *pxmitframe); +#ifdef CONFIG_XMIT_THREAD_MODE + s32 (*xmit_thread_handler)(_adapter *padapter); +#endif + void (*run_thread)(_adapter *padapter); + void (*cancel_thread)(_adapter *padapter); + + /*** recv section ***/ + s32 (*init_recv_priv)(_adapter *padapter); + void (*free_recv_priv)(_adapter *padapter); +#if defined(CONFIG_USB_HCI)||defined(CONFIG_PCI_HCI) + u32 (*inirp_init)(_adapter *padapter); + u32 (*inirp_deinit)(_adapter *padapter); +#endif + /*** interrupt hdl section ***/ + void (*enable_interrupt)(_adapter *padapter); + void (*disable_interrupt)(_adapter *padapter); + u8 (*check_ips_status)(_adapter *padapter); +#if defined(CONFIG_PCI_HCI) + s32 (*interrupt_handler)(_adapter *padapter); +#endif + +#if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT) + void (*interrupt_handler)(_adapter *padapter, u16 pkt_len, u8 *pbuf); +#endif + +#if defined(CONFIG_PCI_HCI) + void (*irp_reset)(_adapter *padapter); +#endif + + /*** DM section ***/ + + void (*InitSwLeds)(_adapter *padapter); + void (*DeInitSwLeds)(_adapter *padapter); + + + void (*set_bwmode_handler)(_adapter *padapter, CHANNEL_WIDTH Bandwidth, u8 Offset); + void (*set_channel_handler)(_adapter *padapter, u8 channel); + void (*set_chnl_bw_handler)(_adapter *padapter, u8 channel, CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80); + + void (*set_tx_power_level_handler)(_adapter *padapter, u8 channel); + void (*get_tx_power_level_handler)(_adapter *padapter, s32 *powerlevel); + + void (*hal_dm_watchdog)(_adapter *padapter); +#ifdef CONFIG_LPS_LCLK_WD_TIMER + void (*hal_dm_watchdog_in_lps)(_adapter *padapter); +#endif + + void (*SetHwRegHandler)(_adapter *padapter, u8 variable,u8* val); + void (*GetHwRegHandler)(_adapter *padapter, u8 variable,u8* val); + +#ifdef CONFIG_C2H_PACKET_EN + void (*SetHwRegHandlerWithBuf)(_adapter *padapter, u8 variable, u8 * pbuf, int len); +#endif + + u8 (*GetHalDefVarHandler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue); + u8 (*SetHalDefVarHandler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue); + + void (*GetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1,PVOID pValue2); + void (*SetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1,BOOLEAN bSet); + + void (*UpdateRAMaskHandler)(_adapter *padapter, u32 mac_id, u8 rssi_level); + void (*SetBeaconRelatedRegistersHandler)(_adapter *padapter); + + void (*Add_RateATid)(_adapter *padapter, u64 bitmap, u8 *arg, u8 rssi_level); + u8 (*interface_ps_func)(_adapter *padapter,HAL_INTF_PS_FUNC efunc_id, u8* val); + + u32 (*read_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask); + void (*write_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data); + u32 (*read_rfreg)(_adapter *padapter, u8 eRFPath, u32 RegAddr, u32 BitMask); + void (*write_rfreg)(_adapter *padapter, u8 eRFPath, u32 RegAddr, u32 BitMask, u32 Data); + +#ifdef CONFIG_HOSTAPD_MLME + s32 (*hostap_mgnt_xmit_entry)(_adapter *padapter, _pkt *pkt); +#endif + + void (*EfusePowerSwitch)(_adapter *padapter, u8 bWrite, u8 PwrState); + void (*BTEfusePowerSwitch)(_adapter *padapter, u8 bWrite, u8 PwrState); + void (*ReadEFuse)(_adapter *padapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf, BOOLEAN bPseudoTest); + void (*EFUSEGetEfuseDefinition)(_adapter *padapter, u8 efuseType, u8 type, void *pOut, BOOLEAN bPseudoTest); + u16 (*EfuseGetCurrentSize)(_adapter *padapter, u8 efuseType, BOOLEAN bPseudoTest); + int (*Efuse_PgPacketRead)(_adapter *padapter, u8 offset, u8 *data, BOOLEAN bPseudoTest); + int (*Efuse_PgPacketWrite)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest); + u8 (*Efuse_WordEnableDataWrite)(_adapter *padapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest); + BOOLEAN (*Efuse_PgPacketWrite_BT)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest); + +#ifdef DBG_CONFIG_ERROR_DETECT + void (*sreset_init_value)(_adapter *padapter); + void (*sreset_reset_value)(_adapter *padapter); + void (*silentreset)(_adapter *padapter); + void (*sreset_xmit_status_check)(_adapter *padapter); + void (*sreset_linked_status_check) (_adapter *padapter); + u8 (*sreset_get_wifi_status)(_adapter *padapter); + bool (*sreset_inprogress)(_adapter *padapter); +#endif + +#ifdef CONFIG_IOL + int (*IOL_exec_cmds_sync)(_adapter *padapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt); +#endif + + void (*hal_notch_filter)(_adapter * adapter, bool enable); + s32 (*c2h_handler)(_adapter *padapter, u8 *c2h_evt); + c2h_id_filter c2h_id_filter_ccx; + s32 (*fill_h2c_cmd)(PADAPTER, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); + void (*fill_fake_txdesc)(PADAPTER, u8 *pDesc, u32 BufferLen, + u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame); + s32 (*fw_dl)(_adapter *adapter, u8 wowlan); + + u8 (*hal_get_tx_buff_rsvd_page_num)(_adapter *adapter, bool wowlan); +#ifdef CONFIG_GPIO_API + void (*update_hisr_hsisr_ind)(PADAPTER padapter, u32 flag); +#endif + void (*fw_correct_bcn)(PADAPTER padapter); +}; + +typedef enum _RT_EEPROM_TYPE{ + EEPROM_93C46, + EEPROM_93C56, + EEPROM_BOOT_EFUSE, +}RT_EEPROM_TYPE,*PRT_EEPROM_TYPE; + + + +#define RF_CHANGE_BY_INIT 0 +#define RF_CHANGE_BY_IPS BIT28 +#define RF_CHANGE_BY_PS BIT29 +#define RF_CHANGE_BY_HW BIT30 +#define RF_CHANGE_BY_SW BIT31 + +typedef enum _HARDWARE_TYPE{ + HARDWARE_TYPE_RTL8188EE, + HARDWARE_TYPE_RTL8188EU, + HARDWARE_TYPE_RTL8188ES, +// NEW_GENERATION_IC + HARDWARE_TYPE_RTL8192EE, + HARDWARE_TYPE_RTL8192EU, + HARDWARE_TYPE_RTL8192ES, + HARDWARE_TYPE_RTL8812E, + HARDWARE_TYPE_RTL8812AU, + HARDWARE_TYPE_RTL8811AU, + HARDWARE_TYPE_RTL8821E, + HARDWARE_TYPE_RTL8821U, + HARDWARE_TYPE_RTL8821S, + HARDWARE_TYPE_RTL8723BE, + HARDWARE_TYPE_RTL8723BU, + HARDWARE_TYPE_RTL8723BS, + HARDWARE_TYPE_RTL8814AE, + HARDWARE_TYPE_RTL8814AU, + HARDWARE_TYPE_RTL8814AS, + HARDWARE_TYPE_RTL8821BE, + HARDWARE_TYPE_RTL8821BU, + HARDWARE_TYPE_RTL8821BS, + HARDWARE_TYPE_RTL8822BE, + HARDWARE_TYPE_RTL8822BU, + HARDWARE_TYPE_RTL8822BS, + HARDWARE_TYPE_RTL8703BE, + HARDWARE_TYPE_RTL8703BU, + HARDWARE_TYPE_RTL8703BS, + HARDWARE_TYPE_RTL8188FE, + HARDWARE_TYPE_RTL8188FU, + HARDWARE_TYPE_RTL8188FS, + HARDWARE_TYPE_MAX, +}HARDWARE_TYPE; + +#define IS_NEW_GENERATION_IC(_Adapter) (rtw_get_hw_type(_Adapter) >= HARDWARE_TYPE_RTL8192EE) +// +// RTL8188E Series +// +#define IS_HARDWARE_TYPE_8188EE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188EE) +#define IS_HARDWARE_TYPE_8188EU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188EU) +#define IS_HARDWARE_TYPE_8188ES(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188ES) +#define IS_HARDWARE_TYPE_8188E(_Adapter) \ +(IS_HARDWARE_TYPE_8188EE(_Adapter) || IS_HARDWARE_TYPE_8188EU(_Adapter) || IS_HARDWARE_TYPE_8188ES(_Adapter)) + +// RTL8812 Series +#define IS_HARDWARE_TYPE_8812E(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8812E) +#define IS_HARDWARE_TYPE_8812AU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8812AU) +#define IS_HARDWARE_TYPE_8812(_Adapter) \ +(IS_HARDWARE_TYPE_8812E(_Adapter) || IS_HARDWARE_TYPE_8812AU(_Adapter)) + +// RTL8821 Series +#define IS_HARDWARE_TYPE_8821E(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821E) +#define IS_HARDWARE_TYPE_8811AU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8811AU) +#define IS_HARDWARE_TYPE_8821U(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821U || \ + rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8811AU) +#define IS_HARDWARE_TYPE_8821S(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821S) +#define IS_HARDWARE_TYPE_8821(_Adapter) \ +(IS_HARDWARE_TYPE_8821E(_Adapter) || IS_HARDWARE_TYPE_8821U(_Adapter)|| IS_HARDWARE_TYPE_8821S(_Adapter)) + +#define IS_HARDWARE_TYPE_JAGUAR(_Adapter) \ +(IS_HARDWARE_TYPE_8812(_Adapter) || IS_HARDWARE_TYPE_8821(_Adapter)) + +//RTL8192E Series +#define IS_HARDWARE_TYPE_8192EE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192EE) +#define IS_HARDWARE_TYPE_8192EU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192EU) +#define IS_HARDWARE_TYPE_8192ES(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192ES) + +#define IS_HARDWARE_TYPE_8192E(_Adapter) \ +(IS_HARDWARE_TYPE_8192EE(_Adapter) || IS_HARDWARE_TYPE_8192EU(_Adapter) ||IS_HARDWARE_TYPE_8192ES(_Adapter)) + +#define IS_HARDWARE_TYPE_8723BE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BE) +#define IS_HARDWARE_TYPE_8723BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BU) +#define IS_HARDWARE_TYPE_8723BS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BS) + +#define IS_HARDWARE_TYPE_8723B(_Adapter) \ + (IS_HARDWARE_TYPE_8723BE(_Adapter) || IS_HARDWARE_TYPE_8723BU(_Adapter) ||IS_HARDWARE_TYPE_8723BS(_Adapter)) + +/* RTL8814A Series */ +#define IS_HARDWARE_TYPE_8814AE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AE) +#define IS_HARDWARE_TYPE_8814AU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AU) +#define IS_HARDWARE_TYPE_8814AS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AS) + +#define IS_HARDWARE_TYPE_8814A(_Adapter) \ +(IS_HARDWARE_TYPE_8814AE(_Adapter) || IS_HARDWARE_TYPE_8814AU(_Adapter) || IS_HARDWARE_TYPE_8814AS(_Adapter)) + +#define IS_HARDWARE_TYPE_JAGUAR2(_Adapter) \ +(IS_HARDWARE_TYPE_8814A(_Adapter) || IS_HARDWARE_TYPE_8821B(_Adapter) || IS_HARDWARE_TYPE_8822B(_Adapter)) + +#define IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(_Adapter) \ +(IS_HARDWARE_TYPE_JAGUAR(_Adapter) || IS_HARDWARE_TYPE_JAGUAR2(_Adapter)) + +/* RTL8703B Series */ +#define IS_HARDWARE_TYPE_8703BE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BE) +#define IS_HARDWARE_TYPE_8703BS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BS) +#define IS_HARDWARE_TYPE_8703BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BU) +#define IS_HARDWARE_TYPE_8703B(_Adapter) \ +(IS_HARDWARE_TYPE_8703BE(_Adapter) || IS_HARDWARE_TYPE_8703BU(_Adapter) || IS_HARDWARE_TYPE_8703BS(_Adapter)) + +/* RTL8188F Series */ +#define IS_HARDWARE_TYPE_8188FE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FE) +#define IS_HARDWARE_TYPE_8188FS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FS) +#define IS_HARDWARE_TYPE_8188FU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FU) +#define IS_HARDWARE_TYPE_8188F(_Adapter) \ +(IS_HARDWARE_TYPE_8188FE(_Adapter) || IS_HARDWARE_TYPE_8188FU(_Adapter) || IS_HARDWARE_TYPE_8188FS(_Adapter)) + +#define IS_HARDWARE_TYPE_8821BE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BE) +#define IS_HARDWARE_TYPE_8821BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BU) +#define IS_HARDWARE_TYPE_8821BS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BS) + +#define IS_HARDWARE_TYPE_8821B(_Adapter) \ +(IS_HARDWARE_TYPE_8821BE(_Adapter) || IS_HARDWARE_TYPE_8821BU(_Adapter) || IS_HARDWARE_TYPE_8821BS(_Adapter)) + +#define IS_HARDWARE_TYPE_8822BE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BE) +#define IS_HARDWARE_TYPE_8822BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BU) +#define IS_HARDWARE_TYPE_8822BS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BS) +#define IS_HARDWARE_TYPE_8822B(_Adapter) \ +(IS_HARDWARE_TYPE_8822BE(_Adapter) || IS_HARDWARE_TYPE_8822BU(_Adapter) || IS_HARDWARE_TYPE_8822BS(_Adapter)) + + + +typedef enum _wowlan_subcode { + WOWLAN_ENABLE = 0, + WOWLAN_DISABLE = 1, + WOWLAN_AP_ENABLE = 2, + WOWLAN_AP_DISABLE = 3, + WOWLAN_PATTERN_CLEAN = 4 +} wowlan_subcode; + +struct wowlan_ioctl_param{ + unsigned int subcode; + unsigned int subcode_value; + unsigned int wakeup_reason; +}; + +#define Rx_Pairwisekey 0x01 +#define Rx_GTK 0x02 +#define Rx_DisAssoc 0x04 +#define Rx_DeAuth 0x08 +#define Rx_ARPReq 0x09 +#define FWDecisionDisconnect 0x10 +#define Rx_MagicPkt 0x21 +#define Rx_UnicastPkt 0x22 +#define Rx_PatternPkt 0x23 +#define RX_PNOWakeUp 0x55 +#define AP_WakeUp 0x66 + +u8 rtw_hal_data_init(_adapter *padapter); +void rtw_hal_data_deinit(_adapter *padapter); + +void rtw_hal_def_value_init(_adapter *padapter); + +void rtw_hal_free_data(_adapter *padapter); + +void rtw_hal_dm_init(_adapter *padapter); +void rtw_hal_dm_deinit(_adapter *padapter); +void rtw_hal_sw_led_init(_adapter *padapter); +void rtw_hal_sw_led_deinit(_adapter *padapter); + +u32 rtw_hal_power_on(_adapter *padapter); +void rtw_hal_power_off(_adapter *padapter); + +uint rtw_hal_init(_adapter *padapter); +uint rtw_hal_deinit(_adapter *padapter); +void rtw_hal_stop(_adapter *padapter); +void rtw_hal_set_hwreg(PADAPTER padapter, u8 variable, u8 *val); +void rtw_hal_get_hwreg(PADAPTER padapter, u8 variable, u8 *val); + +#ifdef CONFIG_C2H_PACKET_EN +void rtw_hal_set_hwreg_with_buf(_adapter *padapter, u8 variable, u8 *pbuf, int len); +#endif + +void rtw_hal_chip_configure(_adapter *padapter); +void rtw_hal_read_chip_info(_adapter *padapter); +void rtw_hal_read_chip_version(_adapter *padapter); + +u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue); +u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, PVOID pValue); + +void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1,BOOLEAN bSet); +void rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, PVOID pValue1,PVOID pValue2); + +void rtw_hal_enable_interrupt(_adapter *padapter); +void rtw_hal_disable_interrupt(_adapter *padapter); + +u8 rtw_hal_check_ips_status(_adapter *padapter); + +#if defined(CONFIG_USB_HCI)||defined(CONFIG_PCI_HCI) +u32 rtw_hal_inirp_init(_adapter *padapter); +u32 rtw_hal_inirp_deinit(_adapter *padapter); +#endif + +#if defined(CONFIG_PCI_HCI) +void rtw_hal_irp_reset(_adapter *padapter); +#endif + +u8 rtw_hal_intf_ps_func(_adapter *padapter,HAL_INTF_PS_FUNC efunc_id, u8* val); + +s32 rtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); +s32 rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe); +s32 rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe); + +s32 rtw_hal_init_xmit_priv(_adapter *padapter); +void rtw_hal_free_xmit_priv(_adapter *padapter); + +s32 rtw_hal_init_recv_priv(_adapter *padapter); +void rtw_hal_free_recv_priv(_adapter *padapter); + +void rtw_hal_update_ra_mask(struct sta_info *psta, u8 rssi_level); +void rtw_hal_add_ra_tid(_adapter *padapter, u64 bitmap, u8 *arg, u8 rssi_level); + +void rtw_hal_start_thread(_adapter *padapter); +void rtw_hal_stop_thread(_adapter *padapter); + +void rtw_hal_bcn_related_reg_setting(_adapter *padapter); + +u32 rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask); +void rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data); +u32 rtw_hal_read_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask); +void rtw_hal_write_rfreg(_adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data); + +#define PHY_QueryBBReg(Adapter, RegAddr, BitMask) rtw_hal_read_bbreg((Adapter), (RegAddr), (BitMask)) +#define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) rtw_hal_write_bbreg((Adapter), (RegAddr), (BitMask), (Data)) +#define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) rtw_hal_read_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask)) +#define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) rtw_hal_write_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data)) + +#define PHY_SetMacReg PHY_SetBBReg +#define PHY_QueryMacReg PHY_QueryBBReg + +#if defined(CONFIG_PCI_HCI) +s32 rtw_hal_interrupt_handler(_adapter *padapter); +#endif +#if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT) +void rtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf); +#endif + +void rtw_hal_set_bwmode(_adapter *padapter, CHANNEL_WIDTH Bandwidth, u8 Offset); +void rtw_hal_set_chan(_adapter *padapter, u8 channel); +void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80); +void rtw_hal_dm_watchdog(_adapter *padapter); +void rtw_hal_dm_watchdog_in_lps(_adapter *padapter); + +void rtw_hal_set_tx_power_level(_adapter *padapter, u8 channel); +void rtw_hal_get_tx_power_level(_adapter *padapter, s32 *powerlevel); + +#ifdef CONFIG_HOSTAPD_MLME +s32 rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt); +#endif + +#ifdef DBG_CONFIG_ERROR_DETECT +void rtw_hal_sreset_init(_adapter *padapter); +void rtw_hal_sreset_reset(_adapter *padapter); +void rtw_hal_sreset_reset_value(_adapter *padapter); +void rtw_hal_sreset_xmit_status_check(_adapter *padapter); +void rtw_hal_sreset_linked_status_check (_adapter *padapter); +u8 rtw_hal_sreset_get_wifi_status(_adapter *padapter); +bool rtw_hal_sreset_inprogress(_adapter *padapter); +#endif + +#ifdef CONFIG_IOL +int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt); +#endif + +#ifdef CONFIG_XMIT_THREAD_MODE +s32 rtw_hal_xmit_thread_handler(_adapter *padapter); +#endif + +void rtw_hal_notch_filter(_adapter * adapter, bool enable); + +bool rtw_hal_c2h_valid(_adapter *adapter, u8 *buf); +s32 rtw_hal_c2h_evt_read(_adapter *adapter, u8 *buf); +s32 rtw_hal_c2h_handler(_adapter *adapter, u8 *c2h_evt); +c2h_id_filter rtw_hal_c2h_id_filter_ccx(_adapter *adapter); + +s32 rtw_hal_is_disable_sw_channel_plan(PADAPTER padapter); + +s32 rtw_hal_macid_sleep(PADAPTER padapter, u8 macid); +s32 rtw_hal_macid_wakeup(PADAPTER padapter, u8 macid); + +s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); +void rtw_hal_fill_fake_txdesc(_adapter *padapter, u8 *pDesc, u32 BufferLen, + u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame); +u8 rtw_hal_get_txbuff_rsvd_page_num(_adapter *adapter, bool wowlan); + +#ifdef CONFIG_GPIO_API +void rtw_hal_update_hisr_hsisr_ind(_adapter *padapter, u32 flag); +#endif + +void rtw_hal_fw_correct_bcn(_adapter *padapter); +s32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan); + +u8 rtw_hal_ops_check(_adapter *padapter); + +#endif //__HAL_INTF_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_pg.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_pg.h new file mode 100644 index 000000000..f779d854c --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_pg.h @@ -0,0 +1,650 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __HAL_PG_H__ +#define __HAL_PG_H__ + +#define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F +#define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0 + +#define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F +#define PPG_THERMAL_OFFSET_MASK 0x1F +#define KFREE_BB_GAIN_2G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1)))) +#define KFREE_BB_GAIN_5G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1)))) +#define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1)))) + +//==================================================== +// EEPROM/Efuse PG Offset for 88EE/88EU/88ES +//==================================================== +#define EEPROM_TX_PWR_INX_88E 0x10 + +#define EEPROM_ChannelPlan_88E 0xB8 +#define EEPROM_XTAL_88E 0xB9 +#define EEPROM_THERMAL_METER_88E 0xBA +#define EEPROM_IQK_LCK_88E 0xBB + +#define EEPROM_RF_BOARD_OPTION_88E 0xC1 +#define EEPROM_RF_FEATURE_OPTION_88E 0xC2 +#define EEPROM_RF_BT_SETTING_88E 0xC3 +#define EEPROM_VERSION_88E 0xC4 +#define EEPROM_CustomID_88E 0xC5 +#define EEPROM_RF_ANTENNA_OPT_88E 0xC9 +#define EEPROM_COUNTRY_CODE_88E 0xCB +#define EEPROM_RFE_OPTION_8188E 0xCA + +// RTL88EE +#define EEPROM_MAC_ADDR_88EE 0xD0 +#define EEPROM_VID_88EE 0xD6 +#define EEPROM_DID_88EE 0xD8 +#define EEPROM_SVID_88EE 0xDA +#define EEPROM_SMID_88EE 0xDC + +//RTL88EU +#define EEPROM_MAC_ADDR_88EU 0xD7 +#define EEPROM_VID_88EU 0xD0 +#define EEPROM_PID_88EU 0xD2 +#define EEPROM_USB_OPTIONAL_FUNCTION0 0xD4 //8188EU,8192EU, 8812AU is the same +#define EEPROM_USB_OPTIONAL_FUNCTION0_8811AU 0x104 + +// RTL88ES +#define EEPROM_MAC_ADDR_88ES 0x11A +//==================================================== +// EEPROM/Efuse PG Offset for 8192EE/8192EU/8192ES +//==================================================== +#define GET_PG_KFREE_ON_8192E(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1) +#define GET_PG_KFREE_THERMAL_K_ON_8192E(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1) + +#define PPG_BB_GAIN_2G_TXA_OFFSET_8192E 0x1F6 +#define PPG_THERMAL_OFFSET_8192E 0x1F5 + +// 0x10 ~ 0x63 = TX power area. +#define EEPROM_TX_PWR_INX_8192E 0x10 + +#define EEPROM_ChannelPlan_8192E 0xB8 +#define EEPROM_XTAL_8192E 0xB9 +#define EEPROM_THERMAL_METER_8192E 0xBA +#define EEPROM_IQK_LCK_8192E 0xBB +#define EEPROM_2G_5G_PA_TYPE_8192E 0xBC +#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8192E 0xBD +#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8192E 0xBF + +#define EEPROM_RF_BOARD_OPTION_8192E 0xC1 +#define EEPROM_RF_FEATURE_OPTION_8192E 0xC2 +#define EEPROM_RF_BT_SETTING_8192E 0xC3 +#define EEPROM_VERSION_8192E 0xC4 +#define EEPROM_CustomID_8192E 0xC5 +#define EEPROM_TX_BBSWING_2G_8192E 0xC6 +#define EEPROM_TX_BBSWING_5G_8192E 0xC7 +#define EEPROM_TX_PWR_CALIBRATE_RATE_8192E 0xC8 +#define EEPROM_RF_ANTENNA_OPT_8192E 0xC9 +#define EEPROM_RFE_OPTION_8192E 0xCA +#define EEPROM_COUNTRY_CODE_8192E 0xCB + +// RTL8192EE +#define EEPROM_MAC_ADDR_8192EE 0xD0 +#define EEPROM_VID_8192EE 0xD6 +#define EEPROM_DID_8192EE 0xD8 +#define EEPROM_SVID_8192EE 0xDA +#define EEPROM_SMID_8192EE 0xDC + +//RTL8192EU +#define EEPROM_MAC_ADDR_8192EU 0xD7 +#define EEPROM_VID_8192EU 0xD0 +#define EEPROM_PID_8192EU 0xD2 +#define EEPROM_PA_TYPE_8192EU 0xBC +#define EEPROM_LNA_TYPE_2G_8192EU 0xBD +#define EEPROM_LNA_TYPE_5G_8192EU 0xBF + +// RTL8192ES +#define EEPROM_MAC_ADDR_8192ES 0x11A +//==================================================== +// EEPROM/Efuse PG Offset for 8812AE/8812AU/8812AS +//==================================================== +// 0x10 ~ 0x63 = TX power area. +#define EEPROM_USB_MODE_8812 0x08 +#define EEPROM_TX_PWR_INX_8812 0x10 + +#define EEPROM_ChannelPlan_8812 0xB8 +#define EEPROM_XTAL_8812 0xB9 +#define EEPROM_THERMAL_METER_8812 0xBA +#define EEPROM_IQK_LCK_8812 0xBB +#define EEPROM_2G_5G_PA_TYPE_8812 0xBC +#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8812 0xBD +#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8812 0xBF + +#define EEPROM_RF_BOARD_OPTION_8812 0xC1 +#define EEPROM_RF_FEATURE_OPTION_8812 0xC2 +#define EEPROM_RF_BT_SETTING_8812 0xC3 +#define EEPROM_VERSION_8812 0xC4 +#define EEPROM_CustomID_8812 0xC5 +#define EEPROM_TX_BBSWING_2G_8812 0xC6 +#define EEPROM_TX_BBSWING_5G_8812 0xC7 +#define EEPROM_TX_PWR_CALIBRATE_RATE_8812 0xC8 +#define EEPROM_RF_ANTENNA_OPT_8812 0xC9 +#define EEPROM_RFE_OPTION_8812 0xCA +#define EEPROM_COUNTRY_CODE_8812 0xCB + +// RTL8812AE +#define EEPROM_MAC_ADDR_8812AE 0xD0 +#define EEPROM_VID_8812AE 0xD6 +#define EEPROM_DID_8812AE 0xD8 +#define EEPROM_SVID_8812AE 0xDA +#define EEPROM_SMID_8812AE 0xDC + +//RTL8812AU +#define EEPROM_MAC_ADDR_8812AU 0xD7 +#define EEPROM_VID_8812AU 0xD0 +#define EEPROM_PID_8812AU 0xD2 +#define EEPROM_PA_TYPE_8812AU 0xBC +#define EEPROM_LNA_TYPE_2G_8812AU 0xBD +#define EEPROM_LNA_TYPE_5G_8812AU 0xBF + +//RTL8814AU +#define EEPROM_MAC_ADDR_8814AU 0xD8 +#define EEPROM_VID_8814AU 0xD0 +#define EEPROM_PID_8814AU 0xD2 +#define EEPROM_PA_TYPE_8814AU 0xBC +#define EEPROM_LNA_TYPE_2G_8814AU 0xBD +#define EEPROM_LNA_TYPE_5G_8814AU 0xBF + +/* RTL8814AE */ +#define EEPROM_MAC_ADDR_8814AE 0xD0 +#define EEPROM_VID_8814AE 0xD6 +#define EEPROM_DID_8814AE 0xD8 +#define EEPROM_SVID_8814AE 0xDA +#define EEPROM_SMID_8814AE 0xDC + +//==================================================== +// EEPROM/Efuse PG Offset for 8814AU +//==================================================== +#define GET_PG_KFREE_ON_8814A(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 4, 1) +#define GET_PG_KFREE_THERMAL_K_ON_8814A(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1) + +#define KFREE_GAIN_DATA_LENGTH_8814A 22 + +#define PPG_BB_GAIN_2G_TXBA_OFFSET_8814A 0x3EE + +#define PPG_THERMAL_OFFSET_8814A 0x3EF + +#define EEPROM_TX_PWR_INX_8814 0x10 +#define EEPROM_ChannelPlan_8814 0xB8 +#define EEPROM_XTAL_8814 0xB9 +#define EEPROM_THERMAL_METER_8814 0xBA +#define EEPROM_IQK_LCK_8814 0xBB + + +#define EEPROM_PA_TYPE_8814 0xBC +#define EEPROM_LNA_TYPE_AB_2G_8814 0xBD +#define EEPROM_LNA_TYPE_CD_2G_8814 0xBE +#define EEPROM_LNA_TYPE_AB_5G_8814 0xBF +#define EEPROM_LNA_TYPE_CD_5G_8814 0xC0 +#define EEPROM_RF_BOARD_OPTION_8814 0xC1 +#define EEPROM_RF_BT_SETTING_8814 0xC3 +#define EEPROM_VERSION_8814 0xC4 +#define EEPROM_CustomID_8814 0xC5 +#define EEPROM_TX_BBSWING_2G_8814 0xC6 +#define EEPROM_TX_BBSWING_5G_8814 0xC7 +#define EEPROM_TRX_ANTENNA_OPTION_8814 0xC9 +#define EEPROM_RFE_OPTION_8814 0xCA +#define EEPROM_COUNTRY_CODE_8814 0xCB + +//==================================================== +// EEPROM/Efuse PG Offset for 8821AE/8821AU/8821AS +//==================================================== + +#define GET_PG_KFREE_ON_8821A(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 4, 1) +#define GET_PG_KFREE_THERMAL_K_ON_8821A(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1) + +#define PPG_BB_GAIN_2G_TXA_OFFSET_8821A 0x1F6 +#define PPG_THERMAL_OFFSET_8821A 0x1F5 +#define PPG_BB_GAIN_5GLB1_TXA_OFFSET_8821A 0x1F4 +#define PPG_BB_GAIN_5GLB2_TXA_OFFSET_8821A 0x1F3 +#define PPG_BB_GAIN_5GMB1_TXA_OFFSET_8821A 0x1F2 +#define PPG_BB_GAIN_5GMB2_TXA_OFFSET_8821A 0x1F1 +#define PPG_BB_GAIN_5GHB_TXA_OFFSET_8821A 0x1F0 + +#define EEPROM_TX_PWR_INX_8821 0x10 + +#define EEPROM_ChannelPlan_8821 0xB8 +#define EEPROM_XTAL_8821 0xB9 +#define EEPROM_THERMAL_METER_8821 0xBA +#define EEPROM_IQK_LCK_8821 0xBB + + +#define EEPROM_RF_BOARD_OPTION_8821 0xC1 +#define EEPROM_RF_FEATURE_OPTION_8821 0xC2 +#define EEPROM_RF_BT_SETTING_8821 0xC3 +#define EEPROM_VERSION_8821 0xC4 +#define EEPROM_CustomID_8821 0xC5 +#define EEPROM_RF_ANTENNA_OPT_8821 0xC9 + +// RTL8821AE +#define EEPROM_MAC_ADDR_8821AE 0xD0 +#define EEPROM_VID_8821AE 0xD6 +#define EEPROM_DID_8821AE 0xD8 +#define EEPROM_SVID_8821AE 0xDA +#define EEPROM_SMID_8821AE 0xDC + +//RTL8821AU +#define EEPROM_PA_TYPE_8821AU 0xBC +#define EEPROM_LNA_TYPE_8821AU 0xBF + +// RTL8821AS +#define EEPROM_MAC_ADDR_8821AS 0x11A + +//RTL8821AU +#define EEPROM_MAC_ADDR_8821AU 0x107 +#define EEPROM_VID_8821AU 0x100 +#define EEPROM_PID_8821AU 0x102 + + +//==================================================== +// EEPROM/Efuse PG Offset for 8192 SE/SU +//==================================================== +#define EEPROM_VID_92SE 0x0A +#define EEPROM_DID_92SE 0x0C +#define EEPROM_SVID_92SE 0x0E +#define EEPROM_SMID_92SE 0x10 + +#define EEPROM_MAC_ADDR_92S 0x12 + +#define EEPROM_TSSI_A_92SE 0x74 +#define EEPROM_TSSI_B_92SE 0x75 + +#define EEPROM_Version_92SE 0x7C + + +#define EEPROM_VID_92SU 0x08 +#define EEPROM_PID_92SU 0x0A + +#define EEPROM_Version_92SU 0x50 +#define EEPROM_TSSI_A_92SU 0x6b +#define EEPROM_TSSI_B_92SU 0x6c + +/* ==================================================== + EEPROM/Efuse PG Offset for 8188FE/8188FU/8188FS + ==================================================== + */ + +#define GET_PG_KFREE_ON_8188F(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1) +#define GET_PG_KFREE_THERMAL_K_ON_8188F(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1) + +#define PPG_BB_GAIN_2G_TXA_OFFSET_8188F 0xEE +#define PPG_THERMAL_OFFSET_8188F 0xEF + +/* 0x10 ~ 0x63 = TX power area. */ +#define EEPROM_TX_PWR_INX_8188F 0x10 + +#define EEPROM_ChannelPlan_8188F 0xB8 +#define EEPROM_XTAL_8188F 0xB9 +#define EEPROM_THERMAL_METER_8188F 0xBA +#define EEPROM_IQK_LCK_8188F 0xBB +#define EEPROM_2G_5G_PA_TYPE_8188F 0xBC +#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8188F 0xBD +#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8188F 0xBF + +#define EEPROM_RF_BOARD_OPTION_8188F 0xC1 +#define EEPROM_FEATURE_OPTION_8188F 0xC2 +#define EEPROM_RF_BT_SETTING_8188F 0xC3 +#define EEPROM_VERSION_8188F 0xC4 +#define EEPROM_CustomID_8188F 0xC5 +#define EEPROM_TX_BBSWING_2G_8188F 0xC6 +#define EEPROM_TX_PWR_CALIBRATE_RATE_8188F 0xC8 +#define EEPROM_RF_ANTENNA_OPT_8188F 0xC9 +#define EEPROM_RFE_OPTION_8188F 0xCA +#define EEPROM_COUNTRY_CODE_8188F 0xCB +#define EEPROM_CUSTOMER_ID_8188F 0x7F +#define EEPROM_SUBCUSTOMER_ID_8188F 0x59 + +/* RTL8188FU */ +#define EEPROM_MAC_ADDR_8188FU 0xD7 +#define EEPROM_VID_8188FU 0xD0 +#define EEPROM_PID_8188FU 0xD2 +#define EEPROM_PA_TYPE_8188FU 0xBC +#define EEPROM_LNA_TYPE_2G_8188FU 0xBD +#define EEPROM_USB_OPTIONAL_FUNCTION0_8188FU 0xD4 + +/* RTL8188FS */ +#define EEPROM_MAC_ADDR_8188FS 0x11A +#define EEPROM_Voltage_ADDR_8188F 0x8 + +//==================================================== +// EEPROM/Efuse PG Offset for 8723BE/8723BU/8723BS +//==================================================== +// 0x10 ~ 0x63 = TX power area. +#define EEPROM_TX_PWR_INX_8723B 0x10 + +#define EEPROM_ChannelPlan_8723B 0xB8 +#define EEPROM_XTAL_8723B 0xB9 +#define EEPROM_THERMAL_METER_8723B 0xBA +#define EEPROM_IQK_LCK_8723B 0xBB +#define EEPROM_2G_5G_PA_TYPE_8723B 0xBC +#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8723B 0xBD +#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8723B 0xBF + +#define EEPROM_RF_BOARD_OPTION_8723B 0xC1 +#define EEPROM_FEATURE_OPTION_8723B 0xC2 +#define EEPROM_RF_BT_SETTING_8723B 0xC3 +#define EEPROM_VERSION_8723B 0xC4 +#define EEPROM_CustomID_8723B 0xC5 +#define EEPROM_TX_BBSWING_2G_8723B 0xC6 +#define EEPROM_TX_PWR_CALIBRATE_RATE_8723B 0xC8 +#define EEPROM_RF_ANTENNA_OPT_8723B 0xC9 +#define EEPROM_RFE_OPTION_8723B 0xCA +#define EEPROM_COUNTRY_CODE_8723B 0xCB + +// RTL8723BE +#define EEPROM_MAC_ADDR_8723BE 0xD0 +#define EEPROM_VID_8723BE 0xD6 +#define EEPROM_DID_8723BE 0xD8 +#define EEPROM_SVID_8723BE 0xDA +#define EEPROM_SMID_8723BE 0xDC + +//RTL8723BU +#define EEPROM_MAC_ADDR_8723BU 0x107 +#define EEPROM_VID_8723BU 0x100 +#define EEPROM_PID_8723BU 0x102 +#define EEPROM_PA_TYPE_8723BU 0xBC +#define EEPROM_LNA_TYPE_2G_8723BU 0xBD + + +//RTL8723BS +#define EEPROM_MAC_ADDR_8723BS 0x11A +#define EEPROM_Voltage_ADDR_8723B 0x8 + +//==================================================== +/* EEPROM/Efuse PG Offset for 8703B */ +//==================================================== +#define GET_PG_KFREE_ON_8703B(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1) +#define GET_PG_KFREE_THERMAL_K_ON_8703B(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1) + +#define PPG_BB_GAIN_2G_TXA_OFFSET_8703B 0xEE +#define PPG_THERMAL_OFFSET_8703B 0xEF + +#define EEPROM_TX_PWR_INX_8703B 0x10 + +#define EEPROM_ChannelPlan_8703B 0xB8 +#define EEPROM_XTAL_8703B 0xB9 +#define EEPROM_THERMAL_METER_8703B 0xBA +#define EEPROM_IQK_LCK_8703B 0xBB +#define EEPROM_2G_5G_PA_TYPE_8703B 0xBC +#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8703B 0xBD +#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8703B 0xBF + +#define EEPROM_RF_BOARD_OPTION_8703B 0xC1 +#define EEPROM_FEATURE_OPTION_8703B 0xC2 +#define EEPROM_RF_BT_SETTING_8703B 0xC3 +#define EEPROM_VERSION_8703B 0xC4 +#define EEPROM_CustomID_8703B 0xC5 +#define EEPROM_TX_BBSWING_2G_8703B 0xC6 +#define EEPROM_TX_PWR_CALIBRATE_RATE_8703B 0xC8 +#define EEPROM_RF_ANTENNA_OPT_8703B 0xC9 +#define EEPROM_RFE_OPTION_8703B 0xCA +#define EEPROM_COUNTRY_CODE_8703B 0xCB + +/* MAC Hidden */ +#define PPG_MAC_HIDDEN_START_8703B 0xF0 +#define PPG_MAC_HIDDEN_END_8703B 0xFF +#define EEPROM_HCI_AND_PACKAGE_TYPE_8703B 0xF8 +#define EEPROM_WL_FUNC_CAP_8703B 0xF9 +#define EEPROM_BW_AND_ANT_NUM_CAP_8703B 0xFB +#define GET_PMH_HCI_TYPE_8703B(_pmh_m) LE_BITS_TO_1BYTE(((u8 *)(_pmh_m)) + EEPROM_HCI_AND_PACKAGE_TYPE_8703B - PPG_MAC_HIDDEN_START_8703B, 0, 4) +#define GET_PMH_PACKAGE_TYPE_8703B(_pmh_m) LE_BITS_TO_1BYTE(((u8 *)(_pmh_m)) + EEPROM_HCI_AND_PACKAGE_TYPE_8703B - PPG_MAC_HIDDEN_START_8703B, 4, 4) +#define GET_PMH_WL_FUNC_CAP_8703B(_pmh_m) LE_BITS_TO_1BYTE(((u8 *)(_pmh_m)) + EEPROM_WL_FUNC_CAP_8703B - PPG_MAC_HIDDEN_START_8703B, 0, 4) +#define GET_PMH_BW_CAP_8703B(_pmh_m) LE_BITS_TO_1BYTE(((u8 *)(_pmh_m)) + EEPROM_BW_AND_ANT_NUM_CAP_8703B - PPG_MAC_HIDDEN_START_8703B, 0, 3) +#define GET_PMH_ANT_NUM_CAP_8703B(_pmh_m) LE_BITS_TO_1BYTE(((u8 *)(_pmh_m)) + EEPROM_BW_AND_ANT_NUM_CAP_8703B - PPG_MAC_HIDDEN_START_8703B, 5, 3) + +/* RTL8703BU */ +#define EEPROM_MAC_ADDR_8703BU 0x107 +#define EEPROM_VID_8703BU 0x100 +#define EEPROM_PID_8703BU 0x102 +#define EEPROM_USB_OPTIONAL_FUNCTION0_8703BU 0x104 +#define EEPROM_PA_TYPE_8703BU 0xBC +#define EEPROM_LNA_TYPE_2G_8703BU 0xBD + +//RTL8703BS +#define EEPROM_MAC_ADDR_8703BS 0x11A +#define EEPROM_Voltage_ADDR_8703B 0x8 + +//==================================================== +// EEPROM/Efuse Value Type +//==================================================== +#define EETYPE_TX_PWR 0x0 +//==================================================== +// EEPROM/Efuse Default Value +//==================================================== +#define EEPROM_CID_DEFAULT 0x0 +#define EEPROM_CID_DEFAULT_EXT 0xFF // Reserved for Realtek +#define EEPROM_CID_TOSHIBA 0x4 +#define EEPROM_CID_CCX 0x10 +#define EEPROM_CID_QMI 0x0D +#define EEPROM_CID_WHQL 0xFE + +#define EEPROM_CHANNEL_PLAN_FCC 0x0 +#define EEPROM_CHANNEL_PLAN_IC 0x1 +#define EEPROM_CHANNEL_PLAN_ETSI 0x2 +#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 +#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 +#define EEPROM_CHANNEL_PLAN_MKK 0x5 +#define EEPROM_CHANNEL_PLAN_MKK1 0x6 +#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 +#define EEPROM_CHANNEL_PLAN_TELEC 0x8 +#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 +#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA +#define EEPROM_CHANNEL_PLAN_NCC_TAIWAN 0xB +#define EEPROM_CHANNEL_PLAN_CHIAN 0XC +#define EEPROM_CHANNEL_PLAN_SINGAPORE_INDIA_MEXICO 0XD +#define EEPROM_CHANNEL_PLAN_KOREA 0xE +#define EEPROM_CHANNEL_PLAN_TURKEY 0xF +#define EEPROM_CHANNEL_PLAN_JAPAN 0x10 +#define EEPROM_CHANNEL_PLAN_FCC_NO_DFS 0x11 +#define EEPROM_CHANNEL_PLAN_JAPAN_NO_DFS 0x12 +#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_5G 0x13 +#define EEPROM_CHANNEL_PLAN_TAIWAN_NO_DFS 0x14 + +#define EEPROM_USB_OPTIONAL1 0xE +#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 + +#define RTL_EEPROM_ID 0x8129 +#define EEPROM_Default_TSSI 0x0 +#define EEPROM_Default_BoardType 0x02 +#define EEPROM_Default_ThermalMeter 0x12 +#define EEPROM_Default_ThermalMeter_92SU 0x7 +#define EEPROM_Default_ThermalMeter_88E 0x18 +#define EEPROM_Default_ThermalMeter_8812 0x18 +#define EEPROM_Default_ThermalMeter_8192E 0x1A +#define EEPROM_Default_ThermalMeter_8723B 0x18 +#define EEPROM_Default_ThermalMeter_8703B 0x18 +#define EEPROM_Default_ThermalMeter_8188F 0x18 +#define EEPROM_Default_ThermalMeter_8814A 0x18 + + +#define EEPROM_Default_CrystalCap 0x0 +#define EEPROM_Default_CrystalCap_8723A 0x20 +#define EEPROM_Default_CrystalCap_88E 0x20 +#define EEPROM_Default_CrystalCap_8812 0x20 +#define EEPROM_Default_CrystalCap_8814 0x20 +#define EEPROM_Default_CrystalCap_8192E 0x20 +#define EEPROM_Default_CrystalCap_8723B 0x20 +#define EEPROM_Default_CrystalCap_8703B 0x20 +#define EEPROM_Default_CrystalCap_8188F 0x20 +#define EEPROM_Default_CrystalFreq 0x0 +#define EEPROM_Default_TxPowerLevel_92C 0x22 +#define EEPROM_Default_TxPowerLevel_2G 0x2C +#define EEPROM_Default_TxPowerLevel_5G 0x22 +#define EEPROM_Default_TxPowerLevel 0x22 +#define EEPROM_Default_HT40_2SDiff 0x0 +#define EEPROM_Default_HT20_Diff 2 +#define EEPROM_Default_LegacyHTTxPowerDiff 0x3 +#define EEPROM_Default_LegacyHTTxPowerDiff_92C 0x3 +#define EEPROM_Default_LegacyHTTxPowerDiff_92D 0x4 +#define EEPROM_Default_HT40_PwrMaxOffset 0 +#define EEPROM_Default_HT20_PwrMaxOffset 0 + +#define EEPROM_Default_PID 0x1234 +#define EEPROM_Default_VID 0x5678 +#define EEPROM_Default_CustomerID 0xAB +#define EEPROM_Default_CustomerID_8188E 0x00 +#define EEPROM_Default_SubCustomerID 0xCD +#define EEPROM_Default_Version 0 + +#define EEPROM_Default_externalPA_C9 0x00 +#define EEPROM_Default_externalPA_CC 0xFF +#define EEPROM_Default_internalPA_SP3T_C9 0xAA +#define EEPROM_Default_internalPA_SP3T_CC 0xAF +#define EEPROM_Default_internalPA_SPDT_C9 0xAA +#ifdef CONFIG_PCI_HCI +#define EEPROM_Default_internalPA_SPDT_CC 0xA0 +#else +#define EEPROM_Default_internalPA_SPDT_CC 0xFA +#endif +#define EEPROM_Default_PAType 0 +#define EEPROM_Default_LNAType 0 + +//New EFUSE deafult value +#define EEPROM_DEFAULT_24G_INDEX 0x2D +#define EEPROM_DEFAULT_24G_HT20_DIFF 0X02 +#define EEPROM_DEFAULT_24G_OFDM_DIFF 0X04 + +#define EEPROM_DEFAULT_5G_INDEX 0X2A +#define EEPROM_DEFAULT_5G_HT20_DIFF 0X00 +#define EEPROM_DEFAULT_5G_OFDM_DIFF 0X04 + +#define EEPROM_DEFAULT_DIFF 0XFE +#define EEPROM_DEFAULT_CHANNEL_PLAN 0x7F +#define EEPROM_DEFAULT_BOARD_OPTION 0x00 +#define EEPROM_DEFAULT_RFE_OPTION_8192E 0xFF +#define EEPROM_DEFAULT_RFE_OPTION_8188E 0xFF +#define EEPROM_DEFAULT_RFE_OPTION 0x04 +#define EEPROM_DEFAULT_FEATURE_OPTION 0x00 +#define EEPROM_DEFAULT_BT_OPTION 0x10 + + +#define EEPROM_DEFAULT_TX_CALIBRATE_RATE 0x00 + +// PCIe related +#define EEPROM_PCIE_DEV_CAP_01 0xE0 // Express device capability in PCIe configuration space, i.e., map to offset 0x74 +#define EEPROM_PCIE_DEV_CAP_02 0xE1 // Express device capability in PCIe configuration space, i.e., map to offset 0x75 + + +// +// For VHT series TX power by rate table. +// VHT TX power by rate off setArray = +// Band:-2G&5G = 0 / 1 +// RF: at most 4*4 = ABCD=0/1/2/3 +// CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11 +// +#define TX_PWR_BY_RATE_NUM_BAND 2 +#define TX_PWR_BY_RATE_NUM_RF 4 +#define TX_PWR_BY_RATE_NUM_RATE 84 + +#define TXPWR_LMT_MAX_RF 4 + +//---------------------------------------------------------------------------- +// EEPROM/EFUSE data structure definition. +//---------------------------------------------------------------------------- + +//For 88E new structure + +/* +2.4G: +{ +{1,2}, +{3,4,5}, +{6,7,8}, +{9,10,11}, +{12,13}, +{14} +} + +5G: +{ +{36,38,40}, +{44,46,48}, +{52,54,56}, +{60,62,64}, +{100,102,104}, +{108,110,112}, +{116,118,120}, +{124,126,128}, +{132,134,136}, +{140,142,144}, +{149,151,153}, +{157,159,161}, +{173,175,177}, +} +*/ +#define MAX_RF_PATH 4 +#define RF_PATH_MAX MAX_RF_PATH +#define MAX_CHNL_GROUP_24G 6 +#define MAX_CHNL_GROUP_5G 14 + +//It must always set to 4, otherwise read efuse table secquence will be wrong. +#define MAX_TX_COUNT 4 + +typedef struct _TxPowerInfo24G{ + u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; + u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G]; + //If only one tx, only BW20 and OFDM are used. + s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT]; +}TxPowerInfo24G, *PTxPowerInfo24G; + +typedef struct _TxPowerInfo5G{ + u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_5G]; + //If only one tx, only BW20, OFDM, BW80 and BW160 are used. + s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW80_Diff[MAX_RF_PATH][MAX_TX_COUNT]; + s8 BW160_Diff[MAX_RF_PATH][MAX_TX_COUNT]; +}TxPowerInfo5G, *PTxPowerInfo5G; + + +typedef enum _BT_Ant_NUM{ + Ant_x2 = 0, + Ant_x1 = 1 +} BT_Ant_NUM, *PBT_Ant_NUM; + +typedef enum _BT_CoType{ + BT_2WIRE = 0, + BT_ISSC_3WIRE = 1, + BT_ACCEL = 2, + BT_CSR_BC4 = 3, + BT_CSR_BC8 = 4, + BT_RTL8756 = 5, + BT_RTL8723A = 6, + BT_RTL8821 = 7, + BT_RTL8723B = 8, + BT_RTL8192E = 9, + BT_RTL8814A = 10, + BT_RTL8812A = 11, + BT_RTL8703B = 12 +} BT_CoType, *PBT_CoType; + +typedef enum _BT_RadioShared{ + BT_Radio_Shared = 0, + BT_Radio_Individual = 1, +} BT_RadioShared, *PBT_RadioShared; + + +#endif diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_phy.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_phy.h new file mode 100644 index 000000000..56b50c800 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_phy.h @@ -0,0 +1,247 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_PHY_H__ +#define __HAL_PHY_H__ + + +#if DISABLE_BB_RF +#define HAL_FW_ENABLE 0 +#define HAL_MAC_ENABLE 0 +#define HAL_BB_ENABLE 0 +#define HAL_RF_ENABLE 0 +#else // FPGA_PHY and ASIC +#define HAL_FW_ENABLE 1 +#define HAL_MAC_ENABLE 1 +#define HAL_BB_ENABLE 1 +#define HAL_RF_ENABLE 1 +#endif + +#define RF6052_MAX_TX_PWR 0x3F +#define RF6052_MAX_REG_88E 0xFF +#define RF6052_MAX_REG_92C 0x7F + +#define RF6052_MAX_REG \ + (RF6052_MAX_REG_88E > RF6052_MAX_REG_92C) ? RF6052_MAX_REG_88E: RF6052_MAX_REG_92C + +#define GET_RF6052_REAL_MAX_REG(_Adapter) \ + IS_HARDWARE_TYPE_8188E(_Adapter) ? RF6052_MAX_REG_88E : RF6052_MAX_REG_92C + +#define RF6052_MAX_PATH 2 + +// +// Antenna detection method, i.e., using single tone detection or RSSI reported from each antenna detected. +// Added by Roger, 2013.05.22. +// +#define ANT_DETECT_BY_SINGLE_TONE BIT0 +#define ANT_DETECT_BY_RSSI BIT1 +#define IS_ANT_DETECT_SUPPORT_SINGLE_TONE(__Adapter) ((GET_HAL_DATA(__Adapter)->AntDetection) & ANT_DETECT_BY_SINGLE_TONE) +#define IS_ANT_DETECT_SUPPORT_RSSI(__Adapter) ((GET_HAL_DATA(__Adapter)->AntDetection) & ANT_DETECT_BY_RSSI) + + +/*--------------------------Define Parameters-------------------------------*/ +typedef enum _RF_TYPE{ + RF_TYPE_MIN = 0, // 0 + RF_8225=1, // 1 11b/g RF for verification only + RF_8256=2, // 2 11b/g/n + RF_8258=3, // 3 11a/b/g/n RF + RF_6052=4, // 4 11b/g/n RF + RF_PSEUDO_11N=5, // 5, It is a temporality RF. + RF_TYPE_MAX +}RF_TYPE_E,*PRF_TYPE_E; + +#define TX_1S 0 +#define TX_2S 1 +#define TX_3S 2 +#define TX_4S 3 + +#define RF_PATH_MAX_92C_88E 2 +#define RF_PATH_MAX_90_8812 4 //Max RF number 90 support + +typedef enum _ANTENNA_PATH{ + ANTENNA_NONE = 0, + ANTENNA_D = 1, + ANTENNA_C = 2, + ANTENNA_CD = 3, + ANTENNA_B = 4, + ANTENNA_BD = 5, + ANTENNA_BC = 6, + ANTENNA_BCD = 7, + ANTENNA_A = 8, + ANTENNA_AD = 9, + ANTENNA_AC = 10, + ANTENNA_ACD = 11, + ANTENNA_AB = 12, + ANTENNA_ABD = 13, + ANTENNA_ABC = 14, + ANTENNA_ABCD = 15 +} ANTENNA_PATH; + +typedef enum _RF_CONTENT{ + radioa_txt = 0x1000, + radiob_txt = 0x1001, + radioc_txt = 0x1002, + radiod_txt = 0x1003 +} RF_CONTENT; + +typedef enum _BaseBand_Config_Type{ + BaseBand_Config_PHY_REG = 0, //Radio Path A + BaseBand_Config_AGC_TAB = 1, //Radio Path B + BaseBand_Config_AGC_TAB_2G = 2, + BaseBand_Config_AGC_TAB_5G = 3, + BaseBand_Config_PHY_REG_PG +}BaseBand_Config_Type, *PBaseBand_Config_Type; + +typedef enum _HW_BLOCK{ + HW_BLOCK_MAC = 0, + HW_BLOCK_PHY0 = 1, + HW_BLOCK_PHY1 = 2, + HW_BLOCK_RF = 3, + HW_BLOCK_MAXIMUM = 4, // Never use this +}HW_BLOCK_E, *PHW_BLOCK_E; + +typedef enum _WIRELESS_MODE { + WIRELESS_MODE_UNKNOWN = 0x00, + WIRELESS_MODE_A = 0x01, + WIRELESS_MODE_B = 0x02, + WIRELESS_MODE_G = 0x04, + WIRELESS_MODE_AUTO = 0x08, + WIRELESS_MODE_N_24G = 0x10, + WIRELESS_MODE_N_5G = 0x20, + WIRELESS_MODE_AC_5G = 0x40, + WIRELESS_MODE_AC_24G = 0x80, + WIRELESS_MODE_AC_ONLY = 0x100, +} WIRELESS_MODE; + +typedef enum _SwChnlCmdID{ + CmdID_End, + CmdID_SetTxPowerLevel, + CmdID_BBRegWrite10, + CmdID_WritePortUlong, + CmdID_WritePortUshort, + CmdID_WritePortUchar, + CmdID_RF_WriteReg, +}SwChnlCmdID; + +typedef struct _SwChnlCmd{ + SwChnlCmdID CmdID; + u32 Para1; + u32 Para2; + u32 msDelay; +}SwChnlCmd; + +typedef struct _R_ANTENNA_SELECT_OFDM{ + u32 r_tx_antenna:4; + u32 r_ant_l:4; + u32 r_ant_non_ht:4; + u32 r_ant_ht1:4; + u32 r_ant_ht2:4; + u32 r_ant_ht_s1:4; + u32 r_ant_non_ht_s1:4; + u32 OFDM_TXSC:2; + u32 Reserved:2; +}R_ANTENNA_SELECT_OFDM; + +typedef struct _R_ANTENNA_SELECT_CCK{ + u8 r_cckrx_enable_2:2; + u8 r_cckrx_enable:2; + u8 r_ccktx_enable:4; +}R_ANTENNA_SELECT_CCK; + +typedef struct RF_Shadow_Compare_Map { + // Shadow register value + u32 Value; + // Compare or not flag + u8 Compare; + // Record If it had ever modified unpredicted + u8 ErrorOrNot; + // Recorver Flag + u8 Recorver; + // + u8 Driver_Write; +}RF_SHADOW_T; + +/*--------------------------Exported Function prototype---------------------*/ + +u32 +PHY_CalculateBitShift( + u32 BitMask + ); + +u32 +PHY_RFShadowRead( + IN PADAPTER Adapter, + IN u8 eRFPath, + IN u32 Offset); + +VOID +PHY_RFShadowWrite( + IN PADAPTER Adapter, + IN u8 eRFPath, + IN u32 Offset, + IN u32 Data); + +BOOLEAN +PHY_RFShadowCompare( + IN PADAPTER Adapter, + IN u8 eRFPath, + IN u32 Offset); + +VOID +PHY_RFShadowRecorver( + IN PADAPTER Adapter, + IN u8 eRFPath, + IN u32 Offset); + +VOID +PHY_RFShadowCompareAll( + IN PADAPTER Adapter); + +VOID +PHY_RFShadowRecorverAll( + IN PADAPTER Adapter); + +VOID +PHY_RFShadowCompareFlagSet( + IN PADAPTER Adapter, + IN u8 eRFPath, + IN u32 Offset, + IN u8 Type); + +VOID +PHY_RFShadowRecorverFlagSet( + IN PADAPTER Adapter, + IN u8 eRFPath, + IN u32 Offset, + IN u8 Type); + +VOID +PHY_RFShadowCompareFlagSetAll( + IN PADAPTER Adapter); + +VOID +PHY_RFShadowRecorverFlagSetAll( + IN PADAPTER Adapter); + +VOID +PHY_RFShadowRefresh( + IN PADAPTER Adapter); + +#endif //__HAL_COMMON_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_phy_reg.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_phy_reg.h new file mode 100644 index 000000000..723eddb64 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/hal_phy_reg.h @@ -0,0 +1,31 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __HAL_PHY_REG_H__ +#define __HAL_PHY_REG_H__ + +//for PutRFRegsetting & GetRFRegSetting BitMask +//#if (RTL92SE_FPGA_VERIFY == 1) +//#define bRFRegOffsetMask 0xfff +//#else +#define bRFRegOffsetMask 0xfffff +//#endif + +#endif //__HAL_PHY_REG_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/ieee80211.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/ieee80211.h new file mode 100644 index 000000000..a556620ad --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/ieee80211.h @@ -0,0 +1,1841 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __IEEE80211_H +#define __IEEE80211_H + + +#ifndef CONFIG_RTL8711FW + + #if defined PLATFORM_OS_XP + #include + #endif +#else + +#endif + +#define MGMT_QUEUE_NUM 5 + +#define ETH_ALEN 6 +#define ETH_TYPE_LEN 2 +#define PAYLOAD_TYPE_LEN 1 + +#ifdef CONFIG_AP_MODE + +#define RTL_IOCTL_HOSTAPD (SIOCIWFIRSTPRIV + 28) + +/* RTL871X_IOCTL_HOSTAPD ioctl() cmd: */ +enum { + RTL871X_HOSTAPD_FLUSH = 1, + RTL871X_HOSTAPD_ADD_STA = 2, + RTL871X_HOSTAPD_REMOVE_STA = 3, + RTL871X_HOSTAPD_GET_INFO_STA = 4, + /* REMOVED: PRISM2_HOSTAPD_RESET_TXEXC_STA = 5, */ + RTL871X_HOSTAPD_GET_WPAIE_STA = 5, + RTL871X_SET_ENCRYPTION = 6, + RTL871X_GET_ENCRYPTION = 7, + RTL871X_HOSTAPD_SET_FLAGS_STA = 8, + RTL871X_HOSTAPD_GET_RID = 9, + RTL871X_HOSTAPD_SET_RID = 10, + RTL871X_HOSTAPD_SET_ASSOC_AP_ADDR = 11, + RTL871X_HOSTAPD_SET_GENERIC_ELEMENT = 12, + RTL871X_HOSTAPD_MLME = 13, + RTL871X_HOSTAPD_SCAN_REQ = 14, + RTL871X_HOSTAPD_STA_CLEAR_STATS = 15, + RTL871X_HOSTAPD_SET_BEACON=16, + RTL871X_HOSTAPD_SET_WPS_BEACON = 17, + RTL871X_HOSTAPD_SET_WPS_PROBE_RESP = 18, + RTL871X_HOSTAPD_SET_WPS_ASSOC_RESP = 19, + RTL871X_HOSTAPD_SET_HIDDEN_SSID = 20, + RTL871X_HOSTAPD_SET_MACADDR_ACL = 21, + RTL871X_HOSTAPD_ACL_ADD_STA = 22, + RTL871X_HOSTAPD_ACL_REMOVE_STA = 23, +}; + +/* STA flags */ +#define WLAN_STA_AUTH BIT(0) +#define WLAN_STA_ASSOC BIT(1) +#define WLAN_STA_PS BIT(2) +#define WLAN_STA_TIM BIT(3) +#define WLAN_STA_PERM BIT(4) +#define WLAN_STA_AUTHORIZED BIT(5) +#define WLAN_STA_PENDING_POLL BIT(6) /* pending activity poll not ACKed */ +#define WLAN_STA_SHORT_PREAMBLE BIT(7) +#define WLAN_STA_PREAUTH BIT(8) +#define WLAN_STA_WME BIT(9) +#define WLAN_STA_MFP BIT(10) +#define WLAN_STA_HT BIT(11) +#define WLAN_STA_WPS BIT(12) +#define WLAN_STA_MAYBE_WPS BIT(13) +#define WLAN_STA_VHT BIT(14) +#define WLAN_STA_NONERP BIT(31) + +#endif + +#define IEEE_CMD_SET_WPA_PARAM 1 +#define IEEE_CMD_SET_WPA_IE 2 +#define IEEE_CMD_SET_ENCRYPTION 3 +#define IEEE_CMD_MLME 4 + +#define IEEE_PARAM_WPA_ENABLED 1 +#define IEEE_PARAM_TKIP_COUNTERMEASURES 2 +#define IEEE_PARAM_DROP_UNENCRYPTED 3 +#define IEEE_PARAM_PRIVACY_INVOKED 4 +#define IEEE_PARAM_AUTH_ALGS 5 +#define IEEE_PARAM_IEEE_802_1X 6 +#define IEEE_PARAM_WPAX_SELECT 7 + +#define AUTH_ALG_OPEN_SYSTEM 0x1 +#define AUTH_ALG_SHARED_KEY 0x2 +#define AUTH_ALG_LEAP 0x00000004 + +#define IEEE_MLME_STA_DEAUTH 1 +#define IEEE_MLME_STA_DISASSOC 2 + +#define IEEE_CRYPT_ERR_UNKNOWN_ALG 2 +#define IEEE_CRYPT_ERR_UNKNOWN_ADDR 3 +#define IEEE_CRYPT_ERR_CRYPT_INIT_FAILED 4 +#define IEEE_CRYPT_ERR_KEY_SET_FAILED 5 +#define IEEE_CRYPT_ERR_TX_KEY_SET_FAILED 6 +#define IEEE_CRYPT_ERR_CARD_CONF_FAILED 7 + + +#define IEEE_CRYPT_ALG_NAME_LEN 16 + +#define WPA_CIPHER_NONE BIT(0) +#define WPA_CIPHER_WEP40 BIT(1) +#define WPA_CIPHER_WEP104 BIT(2) +#define WPA_CIPHER_TKIP BIT(3) +#define WPA_CIPHER_CCMP BIT(4) + + + +#define WPA_SELECTOR_LEN 4 +extern u8 RTW_WPA_OUI_TYPE[] ; +extern u16 RTW_WPA_VERSION ; +extern u8 WPA_AUTH_KEY_MGMT_NONE[]; +extern u8 WPA_AUTH_KEY_MGMT_UNSPEC_802_1X[]; +extern u8 WPA_AUTH_KEY_MGMT_PSK_OVER_802_1X[]; +extern u8 WPA_CIPHER_SUITE_NONE[]; +extern u8 WPA_CIPHER_SUITE_WEP40[]; +extern u8 WPA_CIPHER_SUITE_TKIP[]; +extern u8 WPA_CIPHER_SUITE_WRAP[]; +extern u8 WPA_CIPHER_SUITE_CCMP[]; +extern u8 WPA_CIPHER_SUITE_WEP104[]; + + +#define RSN_HEADER_LEN 4 +#define RSN_SELECTOR_LEN 4 + +extern u16 RSN_VERSION_BSD; +extern u8 RSN_AUTH_KEY_MGMT_UNSPEC_802_1X[]; +extern u8 RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X[]; +extern u8 RSN_CIPHER_SUITE_NONE[]; +extern u8 RSN_CIPHER_SUITE_WEP40[]; +extern u8 RSN_CIPHER_SUITE_TKIP[]; +extern u8 RSN_CIPHER_SUITE_WRAP[]; +extern u8 RSN_CIPHER_SUITE_CCMP[]; +extern u8 RSN_CIPHER_SUITE_WEP104[]; + + +typedef enum _RATEID_IDX_ { + RATEID_IDX_BGN_40M_2SS = 0, + RATEID_IDX_BGN_40M_1SS = 1, + RATEID_IDX_BGN_20M_2SS_BN = 2, + RATEID_IDX_BGN_20M_1SS_BN = 3, + RATEID_IDX_GN_N2SS = 4, + RATEID_IDX_GN_N1SS = 5, + RATEID_IDX_BG = 6, + RATEID_IDX_G = 7, + RATEID_IDX_B = 8, + RATEID_IDX_VHT_2SS = 9, + RATEID_IDX_VHT_1SS = 10, + RATEID_IDX_MIX1 = 11, + RATEID_IDX_MIX2 = 12, + RATEID_IDX_VHT_3SS = 13, + RATEID_IDX_BGN_3SS = 14, +} RATEID_IDX, *PRATEID_IDX; + +typedef enum _RATR_TABLE_MODE{ + RATR_INX_WIRELESS_NGB = 0, // BGN 40 Mhz 2SS 1SS + RATR_INX_WIRELESS_NG = 1, // GN or N + RATR_INX_WIRELESS_NB = 2, // BGN 20 Mhz 2SS 1SS or BN + RATR_INX_WIRELESS_N = 3, + RATR_INX_WIRELESS_GB = 4, + RATR_INX_WIRELESS_G = 5, + RATR_INX_WIRELESS_B = 6, + RATR_INX_WIRELESS_MC = 7, + RATR_INX_WIRELESS_AC_N = 8, +}RATR_TABLE_MODE, *PRATR_TABLE_MODE; + + +enum NETWORK_TYPE +{ + WIRELESS_INVALID = 0, + //Sub-Element + WIRELESS_11B = BIT(0), // tx: cck only , rx: cck only, hw: cck + WIRELESS_11G = BIT(1), // tx: ofdm only, rx: ofdm & cck, hw: cck & ofdm + WIRELESS_11A = BIT(2), // tx: ofdm only, rx: ofdm only, hw: ofdm only + WIRELESS_11_24N = BIT(3), // tx: MCS only, rx: MCS & cck, hw: MCS & cck + WIRELESS_11_5N = BIT(4), // tx: MCS only, rx: MCS & ofdm, hw: ofdm only + WIRELESS_AUTO = BIT(5), + WIRELESS_11AC = BIT(6), + + //Combination + //Type for current wireless mode + WIRELESS_11BG = (WIRELESS_11B|WIRELESS_11G), // tx: cck & ofdm, rx: cck & ofdm & MCS, hw: cck & ofdm + WIRELESS_11G_24N = (WIRELESS_11G|WIRELESS_11_24N), // tx: ofdm & MCS, rx: ofdm & cck & MCS, hw: cck & ofdm + WIRELESS_11A_5N = (WIRELESS_11A|WIRELESS_11_5N), // tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only + WIRELESS_11B_24N = (WIRELESS_11B|WIRELESS_11_24N), // tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck + WIRELESS_11BG_24N = (WIRELESS_11B|WIRELESS_11G|WIRELESS_11_24N), // tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck + WIRELESS_11_24AC = (WIRELESS_11G|WIRELESS_11AC), + WIRELESS_11_5AC = (WIRELESS_11A|WIRELESS_11AC), + + + //Type for registry default wireless mode + WIRELESS_11AGN = (WIRELESS_11A|WIRELESS_11G|WIRELESS_11_24N|WIRELESS_11_5N), // tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only + WIRELESS_11ABGN = (WIRELESS_11A|WIRELESS_11B|WIRELESS_11G|WIRELESS_11_24N|WIRELESS_11_5N), + WIRELESS_MODE_24G = (WIRELESS_11B|WIRELESS_11G|WIRELESS_11_24N), + WIRELESS_MODE_5G = (WIRELESS_11A|WIRELESS_11_5N|WIRELESS_11AC), + WIRELESS_MODE_MAX = (WIRELESS_11A|WIRELESS_11B|WIRELESS_11G|WIRELESS_11_24N|WIRELESS_11_5N|WIRELESS_11AC), +}; + +#define SUPPORTED_24G_NETTYPE_MSK WIRELESS_MODE_24G +#define SUPPORTED_5G_NETTYPE_MSK WIRELESS_MODE_5G + +#define IsLegacyOnly(NetType) ((NetType) == ((NetType) & (WIRELESS_11BG|WIRELESS_11A))) + +#define IsSupported24G(NetType) ((NetType) & SUPPORTED_24G_NETTYPE_MSK ? _TRUE : _FALSE) +#define IsSupported5G(NetType) ((NetType) & SUPPORTED_5G_NETTYPE_MSK ? _TRUE : _FALSE) + +#define IsEnableHWCCK(NetType) IsSupported24G(NetType) +#define IsEnableHWOFDM(NetType) ((NetType) & (WIRELESS_11G|WIRELESS_11_24N|SUPPORTED_5G_NETTYPE_MSK) ? _TRUE : _FALSE) + +#define IsSupportedRxCCK(NetType) IsEnableHWCCK(NetType) +#define IsSupportedRxOFDM(NetType) IsEnableHWOFDM(NetType) +#define IsSupportedRxHT(NetType) IsEnableHWOFDM(NetType) + +#define IsSupportedTxCCK(NetType) ((NetType) & (WIRELESS_11B) ? _TRUE : _FALSE) +#define IsSupportedTxOFDM(NetType) ((NetType) & (WIRELESS_11G|WIRELESS_11A) ? _TRUE : _FALSE) +#define IsSupportedHT(NetType) ((NetType) & (WIRELESS_11_24N|WIRELESS_11_5N) ? _TRUE : _FALSE) + +#define IsSupportedVHT(NetType) ((NetType) & (WIRELESS_11AC) ? _TRUE : _FALSE) + + +typedef struct ieee_param { + u32 cmd; + u8 sta_addr[ETH_ALEN]; + union { + struct { + u8 name; + u32 value; + } wpa_param; + struct { + u32 len; + u8 reserved[32]; + u8 data[0]; + } wpa_ie; + struct{ + int command; + int reason_code; + } mlme; + struct { + u8 alg[IEEE_CRYPT_ALG_NAME_LEN]; + u8 set_tx; + u32 err; + u8 idx; + u8 seq[8]; /* sequence counter (set: RX, get: TX) */ + u16 key_len; + u8 key[0]; + } crypt; +#ifdef CONFIG_AP_MODE + struct { + u16 aid; + u16 capability; + int flags; + u8 tx_supp_rates[16]; + struct rtw_ieee80211_ht_cap ht_cap; + } add_sta; + struct { + u8 reserved[2];//for set max_num_sta + u8 buf[0]; + } bcn_ie; +#endif + + } u; +}ieee_param; + +#ifdef CONFIG_AP_MODE +typedef struct ieee_param_ex { + u32 cmd; + u8 sta_addr[ETH_ALEN]; + u8 data[0]; +}ieee_param_ex; + +struct sta_data{ + u16 aid; + u16 capability; + int flags; + u32 sta_set; + u8 tx_supp_rates[16]; + u32 tx_supp_rates_len; + struct rtw_ieee80211_ht_cap ht_cap; + u64 rx_pkts; + u64 rx_bytes; + u64 rx_drops; + u64 tx_pkts; + u64 tx_bytes; + u64 tx_drops; +}; +#endif + + +#if WIRELESS_EXT < 17 +#define IW_QUAL_QUAL_INVALID 0x10 +#define IW_QUAL_LEVEL_INVALID 0x20 +#define IW_QUAL_NOISE_INVALID 0x40 +#define IW_QUAL_QUAL_UPDATED 0x1 +#define IW_QUAL_LEVEL_UPDATED 0x2 +#define IW_QUAL_NOISE_UPDATED 0x4 +#endif + +#define IEEE80211_DATA_LEN 2304 +/* Maximum size for the MA-UNITDATA primitive, 802.11 standard section + 6.2.1.1.2. + + The figure in section 7.1.2 suggests a body size of up to 2312 + bytes is allowed, which is a bit confusing, I suspect this + represents the 2304 bytes of real data, plus a possible 8 bytes of + WEP IV and ICV. (this interpretation suggested by Ramiro Barreiro) */ + + +#define IEEE80211_HLEN 30 +#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN) + + +/* this is stolen from ipw2200 driver */ +#define IEEE_IBSS_MAC_HASH_SIZE 31 + +struct ieee_ibss_seq { + u8 mac[ETH_ALEN]; + u16 seq_num; + u16 frag_num; + unsigned long packet_time; + _list list; +}; + +#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW)||defined(PLATFORM_FREEBSD) + +struct rtw_ieee80211_hdr { + u16 frame_ctl; + u16 duration_id; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 addr3[ETH_ALEN]; + u16 seq_ctl; + u8 addr4[ETH_ALEN]; +} __attribute__ ((packed)); + +struct rtw_ieee80211_hdr_3addr { + u16 frame_ctl; + u16 duration_id; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 addr3[ETH_ALEN]; + u16 seq_ctl; +} __attribute__ ((packed)); + + +struct rtw_ieee80211_hdr_qos { + u16 frame_ctl; + u16 duration_id; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 addr3[ETH_ALEN]; + u16 seq_ctl; + u8 addr4[ETH_ALEN]; + u16 qc; +} __attribute__ ((packed)); + +struct rtw_ieee80211_hdr_3addr_qos { + u16 frame_ctl; + u16 duration_id; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 addr3[ETH_ALEN]; + u16 seq_ctl; + u16 qc; +} __attribute__ ((packed)); + +struct eapol { + u8 snap[6]; + u16 ethertype; + u8 version; + u8 type; + u16 length; +} __attribute__ ((packed)); + +#endif + + + +#ifdef PLATFORM_WINDOWS + +#pragma pack(1) +struct rtw_ieee80211_hdr { + u16 frame_ctl; + u16 duration_id; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 addr3[ETH_ALEN]; + u16 seq_ctl; + u8 addr4[ETH_ALEN]; +}; + +struct rtw_ieee80211_hdr_3addr { + u16 frame_ctl; + u16 duration_id; + u8 addr1[ETH_ALEN]; + u8 addr2[ETH_ALEN]; + u8 addr3[ETH_ALEN]; + u16 seq_ctl; +}; + + +struct rtw_ieee80211_hdr_qos { + struct rtw_ieee80211_hdr wlan_hdr; + u16 qc; +}; + +struct rtw_ieee80211_hdr_3addr_qos { + struct rtw_ieee80211_hdr_3addr wlan_hdr; + u16 qc; +}; + +struct eapol { + u8 snap[6]; + u16 ethertype; + u8 version; + u8 type; + u16 length; +}; +#pragma pack() + +#endif + + + +enum eap_type { + EAP_PACKET = 0, + EAPOL_START, + EAPOL_LOGOFF, + EAPOL_KEY, + EAPOL_ENCAP_ASF_ALERT +}; + +#define IEEE80211_3ADDR_LEN 24 +#define IEEE80211_4ADDR_LEN 30 +#define IEEE80211_FCS_LEN 4 + +#define MIN_FRAG_THRESHOLD 256U +#define MAX_FRAG_THRESHOLD 2346U + +/* Frame control field constants */ +#define RTW_IEEE80211_FCTL_VERS 0x0003 +#define RTW_IEEE80211_FCTL_FTYPE 0x000c +#define RTW_IEEE80211_FCTL_STYPE 0x00f0 +#define RTW_IEEE80211_FCTL_TODS 0x0100 +#define RTW_IEEE80211_FCTL_FROMDS 0x0200 +#define RTW_IEEE80211_FCTL_MOREFRAGS 0x0400 +#define RTW_IEEE80211_FCTL_RETRY 0x0800 +#define RTW_IEEE80211_FCTL_PM 0x1000 +#define RTW_IEEE80211_FCTL_MOREDATA 0x2000 +#define RTW_IEEE80211_FCTL_PROTECTED 0x4000 +#define RTW_IEEE80211_FCTL_ORDER 0x8000 +#define RTW_IEEE80211_FCTL_CTL_EXT 0x0f00 + +#define RTW_IEEE80211_FTYPE_MGMT 0x0000 +#define RTW_IEEE80211_FTYPE_CTL 0x0004 +#define RTW_IEEE80211_FTYPE_DATA 0x0008 +#define RTW_IEEE80211_FTYPE_EXT 0x000c + +/* management */ +#define RTW_IEEE80211_STYPE_ASSOC_REQ 0x0000 +#define RTW_IEEE80211_STYPE_ASSOC_RESP 0x0010 +#define RTW_IEEE80211_STYPE_REASSOC_REQ 0x0020 +#define RTW_IEEE80211_STYPE_REASSOC_RESP 0x0030 +#define RTW_IEEE80211_STYPE_PROBE_REQ 0x0040 +#define RTW_IEEE80211_STYPE_PROBE_RESP 0x0050 +#define RTW_IEEE80211_STYPE_BEACON 0x0080 +#define RTW_IEEE80211_STYPE_ATIM 0x0090 +#define RTW_IEEE80211_STYPE_DISASSOC 0x00A0 +#define RTW_IEEE80211_STYPE_AUTH 0x00B0 +#define RTW_IEEE80211_STYPE_DEAUTH 0x00C0 +#define RTW_IEEE80211_STYPE_ACTION 0x00D0 + +/* control */ +#define RTW_IEEE80211_STYPE_CTL_EXT 0x0060 +#define RTW_IEEE80211_STYPE_BACK_REQ 0x0080 +#define RTW_IEEE80211_STYPE_BACK 0x0090 +#define RTW_IEEE80211_STYPE_PSPOLL 0x00A0 +#define RTW_IEEE80211_STYPE_RTS 0x00B0 +#define RTW_IEEE80211_STYPE_CTS 0x00C0 +#define RTW_IEEE80211_STYPE_ACK 0x00D0 +#define RTW_IEEE80211_STYPE_CFEND 0x00E0 +#define RTW_IEEE80211_STYPE_CFENDACK 0x00F0 + +/* data */ +#define RTW_IEEE80211_STYPE_DATA 0x0000 +#define RTW_IEEE80211_STYPE_DATA_CFACK 0x0010 +#define RTW_IEEE80211_STYPE_DATA_CFPOLL 0x0020 +#define RTW_IEEE80211_STYPE_DATA_CFACKPOLL 0x0030 +#define RTW_IEEE80211_STYPE_NULLFUNC 0x0040 +#define RTW_IEEE80211_STYPE_CFACK 0x0050 +#define RTW_IEEE80211_STYPE_CFPOLL 0x0060 +#define RTW_IEEE80211_STYPE_CFACKPOLL 0x0070 +#define RTW_IEEE80211_STYPE_QOS_DATA 0x0080 +#define RTW_IEEE80211_STYPE_QOS_DATA_CFACK 0x0090 +#define RTW_IEEE80211_STYPE_QOS_DATA_CFPOLL 0x00A0 +#define RTW_IEEE80211_STYPE_QOS_DATA_CFACKPOLL 0x00B0 +#define RTW_IEEE80211_STYPE_QOS_NULLFUNC 0x00C0 +#define RTW_IEEE80211_STYPE_QOS_CFACK 0x00D0 +#define RTW_IEEE80211_STYPE_QOS_CFPOLL 0x00E0 +#define RTW_IEEE80211_STYPE_QOS_CFACKPOLL 0x00F0 + +/* sequence control field */ +#define RTW_IEEE80211_SCTL_FRAG 0x000F +#define RTW_IEEE80211_SCTL_SEQ 0xFFF0 + + +#define RTW_ERP_INFO_NON_ERP_PRESENT BIT(0) +#define RTW_ERP_INFO_USE_PROTECTION BIT(1) +#define RTW_ERP_INFO_BARKER_PREAMBLE_MODE BIT(2) + +/* QoS,QOS */ +#define NORMAL_ACK 0 +#define NO_ACK 1 +#define NON_EXPLICIT_ACK 2 +#define BLOCK_ACK 3 + +#ifndef ETH_P_PAE +#define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */ +#endif /* ETH_P_PAE */ + +#define ETH_P_PREAUTH 0x88C7 /* IEEE 802.11i pre-authentication */ + +#define ETH_P_ECONET 0x0018 + +#ifndef ETH_P_80211_RAW +#define ETH_P_80211_RAW (ETH_P_ECONET + 1) +#endif + +/* IEEE 802.11 defines */ + +#define P80211_OUI_LEN 3 + +#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) || defined(PLATFORM_FREEBSD) + +struct ieee80211_snap_hdr { + + u8 dsap; /* always 0xAA */ + u8 ssap; /* always 0xAA */ + u8 ctrl; /* always 0x03 */ + u8 oui[P80211_OUI_LEN]; /* organizational universal id */ + +} __attribute__ ((packed)); + +#endif + +#ifdef PLATFORM_WINDOWS + +#pragma pack(1) +struct ieee80211_snap_hdr { + + u8 dsap; /* always 0xAA */ + u8 ssap; /* always 0xAA */ + u8 ctrl; /* always 0x03 */ + u8 oui[P80211_OUI_LEN]; /* organizational universal id */ + +}; +#pragma pack() + +#endif + + +#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr) + +#define WLAN_FC_GET_TYPE(fc) ((fc) & RTW_IEEE80211_FCTL_FTYPE) +#define WLAN_FC_GET_STYPE(fc) ((fc) & RTW_IEEE80211_FCTL_STYPE) + +#define WLAN_QC_GET_TID(qc) ((qc) & 0x0f) + +#define WLAN_GET_SEQ_FRAG(seq) ((seq) & RTW_IEEE80211_SCTL_FRAG) +#define WLAN_GET_SEQ_SEQ(seq) ((seq) & RTW_IEEE80211_SCTL_SEQ) + +/* Authentication algorithms */ +#define WLAN_AUTH_OPEN 0 +#define WLAN_AUTH_SHARED_KEY 1 + +#define WLAN_AUTH_CHALLENGE_LEN 128 + +#define WLAN_CAPABILITY_BSS (1<<0) +#define WLAN_CAPABILITY_IBSS (1<<1) +#define WLAN_CAPABILITY_CF_POLLABLE (1<<2) +#define WLAN_CAPABILITY_CF_POLL_REQUEST (1<<3) +#define WLAN_CAPABILITY_PRIVACY (1<<4) +#define WLAN_CAPABILITY_SHORT_PREAMBLE (1<<5) +#define WLAN_CAPABILITY_PBCC (1<<6) +#define WLAN_CAPABILITY_CHANNEL_AGILITY (1<<7) +#define WLAN_CAPABILITY_SHORT_SLOT (1<<10) + +/* Status codes */ +#define WLAN_STATUS_SUCCESS 0 +#define WLAN_STATUS_UNSPECIFIED_FAILURE 1 +#define WLAN_STATUS_CAPS_UNSUPPORTED 10 +#define WLAN_STATUS_REASSOC_NO_ASSOC 11 +#define WLAN_STATUS_ASSOC_DENIED_UNSPEC 12 +#define WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG 13 +#define WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION 14 +#define WLAN_STATUS_CHALLENGE_FAIL 15 +#define WLAN_STATUS_AUTH_TIMEOUT 16 +#define WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA 17 +#define WLAN_STATUS_ASSOC_DENIED_RATES 18 +/* 802.11b */ +#define WLAN_STATUS_ASSOC_DENIED_NOSHORT 19 +#define WLAN_STATUS_ASSOC_DENIED_NOPBCC 20 +#define WLAN_STATUS_ASSOC_DENIED_NOAGILITY 21 + +/* Reason codes */ +#define WLAN_REASON_UNSPECIFIED 1 +#define WLAN_REASON_PREV_AUTH_NOT_VALID 2 +#define WLAN_REASON_DEAUTH_LEAVING 3 +#define WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY 4 +#define WLAN_REASON_DISASSOC_AP_BUSY 5 +#define WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6 +#define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7 +#define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8 +#define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9 +#define WLAN_REASON_ACTIVE_ROAM 65533 +#define WLAN_REASON_JOIN_WRONG_CHANNEL 65534 +#define WLAN_REASON_EXPIRATION_CHK 65535 + +/* Information Element IDs */ +#define WLAN_EID_SSID 0 +#define WLAN_EID_SUPP_RATES 1 +#define WLAN_EID_FH_PARAMS 2 +#define WLAN_EID_DS_PARAMS 3 +#define WLAN_EID_CF_PARAMS 4 +#define WLAN_EID_TIM 5 +#define WLAN_EID_IBSS_PARAMS 6 +#define WLAN_EID_CHALLENGE 16 +/* EIDs defined by IEEE 802.11h - START */ +#define WLAN_EID_PWR_CONSTRAINT 32 +#define WLAN_EID_PWR_CAPABILITY 33 +#define WLAN_EID_TPC_REQUEST 34 +#define WLAN_EID_TPC_REPORT 35 +#define WLAN_EID_SUPPORTED_CHANNELS 36 +#define WLAN_EID_CHANNEL_SWITCH 37 +#define WLAN_EID_MEASURE_REQUEST 38 +#define WLAN_EID_MEASURE_REPORT 39 +#define WLAN_EID_QUITE 40 +#define WLAN_EID_IBSS_DFS 41 +/* EIDs defined by IEEE 802.11h - END */ +#define WLAN_EID_ERP_INFO 42 +#define WLAN_EID_HT_CAP 45 +#define WLAN_EID_RSN 48 +#define WLAN_EID_EXT_SUPP_RATES 50 +#define WLAN_EID_MOBILITY_DOMAIN 54 +#define WLAN_EID_FAST_BSS_TRANSITION 55 +#define WLAN_EID_TIMEOUT_INTERVAL 56 +#define WLAN_EID_RIC_DATA 57 +#define WLAN_EID_HT_OPERATION 61 +#define WLAN_EID_SECONDARY_CHANNEL_OFFSET 62 +#define WLAN_EID_20_40_BSS_COEXISTENCE 72 +#define WLAN_EID_20_40_BSS_INTOLERANT 73 +#define WLAN_EID_OVERLAPPING_BSS_SCAN_PARAMS 74 +#define WLAN_EID_MMIE 76 +#define WLAN_EID_VENDOR_SPECIFIC 221 +#define WLAN_EID_GENERIC (WLAN_EID_VENDOR_SPECIFIC) +#define WLAN_EID_VHT_CAPABILITY 191 +#define WLAN_EID_VHT_OPERATION 192 +#define WLAN_EID_VHT_OP_MODE_NOTIFY 199 + +#define IEEE80211_MGMT_HDR_LEN 24 +#define IEEE80211_DATA_HDR3_LEN 24 +#define IEEE80211_DATA_HDR4_LEN 30 + + +#define IEEE80211_STATMASK_SIGNAL (1<<0) +#define IEEE80211_STATMASK_RSSI (1<<1) +#define IEEE80211_STATMASK_NOISE (1<<2) +#define IEEE80211_STATMASK_RATE (1<<3) +#define IEEE80211_STATMASK_WEMASK 0x7 + + +#define IEEE80211_CCK_MODULATION (1<<0) +#define IEEE80211_OFDM_MODULATION (1<<1) + +#define IEEE80211_24GHZ_BAND (1<<0) +#define IEEE80211_52GHZ_BAND (1<<1) + +#define IEEE80211_CCK_RATE_LEN 4 +#define IEEE80211_NUM_OFDM_RATESLEN 8 + + +#define IEEE80211_CCK_RATE_1MB 0x02 +#define IEEE80211_CCK_RATE_2MB 0x04 +#define IEEE80211_CCK_RATE_5MB 0x0B +#define IEEE80211_CCK_RATE_11MB 0x16 +#define IEEE80211_OFDM_RATE_LEN 8 +#define IEEE80211_OFDM_RATE_6MB 0x0C +#define IEEE80211_OFDM_RATE_9MB 0x12 +#define IEEE80211_OFDM_RATE_12MB 0x18 +#define IEEE80211_OFDM_RATE_18MB 0x24 +#define IEEE80211_OFDM_RATE_24MB 0x30 +#define IEEE80211_OFDM_RATE_36MB 0x48 +#define IEEE80211_OFDM_RATE_48MB 0x60 +#define IEEE80211_OFDM_RATE_54MB 0x6C +#define IEEE80211_BASIC_RATE_MASK 0x80 + +#define IEEE80211_CCK_RATE_1MB_MASK (1<<0) +#define IEEE80211_CCK_RATE_2MB_MASK (1<<1) +#define IEEE80211_CCK_RATE_5MB_MASK (1<<2) +#define IEEE80211_CCK_RATE_11MB_MASK (1<<3) +#define IEEE80211_OFDM_RATE_6MB_MASK (1<<4) +#define IEEE80211_OFDM_RATE_9MB_MASK (1<<5) +#define IEEE80211_OFDM_RATE_12MB_MASK (1<<6) +#define IEEE80211_OFDM_RATE_18MB_MASK (1<<7) +#define IEEE80211_OFDM_RATE_24MB_MASK (1<<8) +#define IEEE80211_OFDM_RATE_36MB_MASK (1<<9) +#define IEEE80211_OFDM_RATE_48MB_MASK (1<<10) +#define IEEE80211_OFDM_RATE_54MB_MASK (1<<11) + +#define IEEE80211_CCK_RATES_MASK 0x0000000F +#define IEEE80211_CCK_BASIC_RATES_MASK (IEEE80211_CCK_RATE_1MB_MASK | \ + IEEE80211_CCK_RATE_2MB_MASK) +#define IEEE80211_CCK_DEFAULT_RATES_MASK (IEEE80211_CCK_BASIC_RATES_MASK | \ + IEEE80211_CCK_RATE_5MB_MASK | \ + IEEE80211_CCK_RATE_11MB_MASK) + +#define IEEE80211_OFDM_RATES_MASK 0x00000FF0 +#define IEEE80211_OFDM_BASIC_RATES_MASK (IEEE80211_OFDM_RATE_6MB_MASK | \ + IEEE80211_OFDM_RATE_12MB_MASK | \ + IEEE80211_OFDM_RATE_24MB_MASK) +#define IEEE80211_OFDM_DEFAULT_RATES_MASK (IEEE80211_OFDM_BASIC_RATES_MASK | \ + IEEE80211_OFDM_RATE_9MB_MASK | \ + IEEE80211_OFDM_RATE_18MB_MASK | \ + IEEE80211_OFDM_RATE_36MB_MASK | \ + IEEE80211_OFDM_RATE_48MB_MASK | \ + IEEE80211_OFDM_RATE_54MB_MASK) +#define IEEE80211_DEFAULT_RATES_MASK (IEEE80211_OFDM_DEFAULT_RATES_MASK | \ + IEEE80211_CCK_DEFAULT_RATES_MASK) + +#define IEEE80211_NUM_OFDM_RATES 8 +#define IEEE80211_NUM_CCK_RATES 4 +#define IEEE80211_OFDM_SHIFT_MASK_A 4 + + +enum MGN_RATE{ + MGN_1M = 0x02, + MGN_2M = 0x04, + MGN_5_5M = 0x0B, + MGN_6M = 0x0C, + MGN_9M = 0x12, + MGN_11M = 0x16, + MGN_12M = 0x18, + MGN_18M = 0x24, + MGN_24M = 0x30, + MGN_36M = 0x48, + MGN_48M = 0x60, + MGN_54M = 0x6C, + MGN_MCS32 = 0x7F, + MGN_MCS0, + MGN_MCS1, + MGN_MCS2, + MGN_MCS3, + MGN_MCS4, + MGN_MCS5, + MGN_MCS6, + MGN_MCS7, + MGN_MCS8, + MGN_MCS9, + MGN_MCS10, + MGN_MCS11, + MGN_MCS12, + MGN_MCS13, + MGN_MCS14, + MGN_MCS15, + MGN_MCS16, + MGN_MCS17, + MGN_MCS18, + MGN_MCS19, + MGN_MCS20, + MGN_MCS21, + MGN_MCS22, + MGN_MCS23, + MGN_MCS24, + MGN_MCS25, + MGN_MCS26, + MGN_MCS27, + MGN_MCS28, + MGN_MCS29, + MGN_MCS30, + MGN_MCS31, + MGN_VHT1SS_MCS0, + MGN_VHT1SS_MCS1, + MGN_VHT1SS_MCS2, + MGN_VHT1SS_MCS3, + MGN_VHT1SS_MCS4, + MGN_VHT1SS_MCS5, + MGN_VHT1SS_MCS6, + MGN_VHT1SS_MCS7, + MGN_VHT1SS_MCS8, + MGN_VHT1SS_MCS9, + MGN_VHT2SS_MCS0, + MGN_VHT2SS_MCS1, + MGN_VHT2SS_MCS2, + MGN_VHT2SS_MCS3, + MGN_VHT2SS_MCS4, + MGN_VHT2SS_MCS5, + MGN_VHT2SS_MCS6, + MGN_VHT2SS_MCS7, + MGN_VHT2SS_MCS8, + MGN_VHT2SS_MCS9, + MGN_VHT3SS_MCS0, + MGN_VHT3SS_MCS1, + MGN_VHT3SS_MCS2, + MGN_VHT3SS_MCS3, + MGN_VHT3SS_MCS4, + MGN_VHT3SS_MCS5, + MGN_VHT3SS_MCS6, + MGN_VHT3SS_MCS7, + MGN_VHT3SS_MCS8, + MGN_VHT3SS_MCS9, + MGN_VHT4SS_MCS0, + MGN_VHT4SS_MCS1, + MGN_VHT4SS_MCS2, + MGN_VHT4SS_MCS3, + MGN_VHT4SS_MCS4, + MGN_VHT4SS_MCS5, + MGN_VHT4SS_MCS6, + MGN_VHT4SS_MCS7, + MGN_VHT4SS_MCS8, + MGN_VHT4SS_MCS9, + MGN_UNKNOWN +}; + +#define IS_HT_RATE(_rate) ((_rate) >= MGN_MCS0 && (_rate) <= MGN_MCS31) +#define IS_VHT_RATE(_rate) ((_rate) >= MGN_VHT1SS_MCS0 && (_rate) <= MGN_VHT4SS_MCS9) +#define IS_CCK_RATE(_rate) ((_rate) == MGN_1M || (_rate) == MGN_2M || (_rate) == MGN_5_5M || (_rate) == MGN_11M) +#define IS_OFDM_RATE(_rate) ((_rate) >= MGN_6M && (_rate) <= MGN_54M && (_rate) != MGN_11M) + +#define IS_HT1SS_RATE(_rate) ((_rate) >= MGN_MCS0 && (_rate) <= MGN_MCS7) +#define IS_HT2SS_RATE(_rate) ((_rate) >= MGN_MCS8 && (_rate) <= MGN_MCS15) +#define IS_HT3SS_RATE(_rate) ((_rate) >= MGN_MCS16 && (_rate) <= MGN_MCS23) +#define IS_HT4SS_RATE(_rate) ((_rate) >= MGN_MCS24 && (_rate) <= MGN_MCS31) + +#define IS_VHT1SS_RATE(_rate) ((_rate) >= MGN_VHT1SS_MCS0 && (_rate) <= MGN_VHT1SS_MCS9) +#define IS_VHT2SS_RATE(_rate) ((_rate) >= MGN_VHT2SS_MCS0 && (_rate) <= MGN_VHT2SS_MCS9) +#define IS_VHT3SS_RATE(_rate) ((_rate) >= MGN_VHT3SS_MCS0 && (_rate) <= MGN_VHT3SS_MCS9) +#define IS_VHT4SS_RATE(_rate) ((_rate) >= MGN_VHT4SS_MCS0 && (_rate) <= MGN_VHT4SS_MCS9) + +#define IS_1T_RATE(_rate) (IS_CCK_RATE((_rate)) || IS_OFDM_RATE((_rate)) || IS_HT1SS_RATE((_rate)) || IS_VHT1SS_RATE((_rate))) +#define IS_2T_RATE(_rate) (IS_HT2SS_RATE((_rate)) || IS_VHT2SS_RATE((_rate))) +#define IS_3T_RATE(_rate) (IS_HT3SS_RATE((_rate)) || IS_VHT3SS_RATE((_rate))) +#define IS_4T_RATE(_rate) (IS_HT4SS_RATE((_rate)) || IS_VHT4SS_RATE((_rate))) + +typedef enum _RATE_SECTION { + CCK = 0, + OFDM = 1, + HT_MCS0_MCS7 = 2, + HT_MCS8_MCS15 = 3, + HT_MCS16_MCS23 = 4, + HT_MCS24_MCS31 = 5, + HT_1SS = HT_MCS0_MCS7, + HT_2SS = HT_MCS8_MCS15, + HT_3SS = HT_MCS16_MCS23, + HT_4SS = HT_MCS24_MCS31, + VHT_1SSMCS0_1SSMCS9 = 6, + VHT_2SSMCS0_2SSMCS9 = 7, + VHT_3SSMCS0_3SSMCS9 = 8, + VHT_4SSMCS0_4SSMCS9 = 9, + VHT_1SS = VHT_1SSMCS0_1SSMCS9, + VHT_2SS = VHT_2SSMCS0_2SSMCS9, + VHT_3SS = VHT_3SSMCS0_3SSMCS9, + VHT_4SS = VHT_4SSMCS0_4SSMCS9, + RATE_SECTION_NUM, +} RATE_SECTION; + +const char *rate_section_str(u8 section); + +#define IS_CCK_RATE_SECTION(section) ((section) == CCK) +#define IS_OFDM_RATE_SECTION(section) ((section) == OFDM) +#define IS_HT_RATE_SECTION(section) ((section) >= HT_1SS && (section) <= HT_4SS) +#define IS_VHT_RATE_SECTION(section) ((section) >= VHT_1SS && (section) <= VHT_4SS) + +#define IS_1T_RATE_SECTION(section) ((section) == CCK || (section) == OFDM || (section) == HT_1SS || (section) == VHT_1SS) +#define IS_2T_RATE_SECTION(section) ((section) == HT_2SS || (section) == VHT_2SS) +#define IS_3T_RATE_SECTION(section) ((section) == HT_3SS || (section) == VHT_3SS) +#define IS_4T_RATE_SECTION(section) ((section) == HT_4SS || (section) == VHT_4SS) + +extern u8 mgn_rates_cck[]; +extern u8 mgn_rates_ofdm[]; +extern u8 mgn_rates_mcs0_7[]; +extern u8 mgn_rates_mcs8_15[]; +extern u8 mgn_rates_mcs16_23[]; +extern u8 mgn_rates_mcs24_31[]; +extern u8 mgn_rates_vht1ss[]; +extern u8 mgn_rates_vht2ss[]; +extern u8 mgn_rates_vht3ss[]; +extern u8 mgn_rates_vht4ss[]; + +struct rate_section_ent { + u8 tx_num; /* value of RF_TX_NUM */ + u8 rate_num; + u8 *rates; +}; + +extern struct rate_section_ent rates_by_sections[]; + +#define rate_section_to_tx_num(section) (rates_by_sections[(section)].tx_num) +#define rate_section_rate_num(section) (rates_by_sections[(section)].rate_num) + +/* NOTE: This data is for statistical purposes; not all hardware provides this + * information for frames received. Not setting these will not cause + * any adverse affects. */ +struct ieee80211_rx_stats { + //u32 mac_time[2]; + s8 rssi; + u8 signal; + u8 noise; + u8 received_channel; + u16 rate; /* in 100 kbps */ + //u8 control; + u8 mask; + u8 freq; + u16 len; +}; + +/* IEEE 802.11 requires that STA supports concurrent reception of at least + * three fragmented frames. This define can be increased to support more + * concurrent frames, but it should be noted that each entry can consume about + * 2 kB of RAM and increasing cache size will slow down frame reassembly. */ +#define IEEE80211_FRAG_CACHE_LEN 4 + +struct ieee80211_frag_entry { + u32 first_frag_time; + uint seq; + uint last_frag; + uint qos; //jackson + uint tid; //jackson + struct sk_buff *skb; + u8 src_addr[ETH_ALEN]; + u8 dst_addr[ETH_ALEN]; +}; + +#ifndef PLATFORM_FREEBSD //Baron BSD has already defined +struct ieee80211_stats { + uint tx_unicast_frames; + uint tx_multicast_frames; + uint tx_fragments; + uint tx_unicast_octets; + uint tx_multicast_octets; + uint tx_deferred_transmissions; + uint tx_single_retry_frames; + uint tx_multiple_retry_frames; + uint tx_retry_limit_exceeded; + uint tx_discards; + uint rx_unicast_frames; + uint rx_multicast_frames; + uint rx_fragments; + uint rx_unicast_octets; + uint rx_multicast_octets; + uint rx_fcs_errors; + uint rx_discards_no_buffer; + uint tx_discards_wrong_sa; + uint rx_discards_undecryptable; + uint rx_message_in_msg_fragments; + uint rx_message_in_bad_msg_fragments; +}; +#endif //PLATFORM_FREEBSD +struct ieee80211_softmac_stats{ + uint rx_ass_ok; + uint rx_ass_err; + uint rx_probe_rq; + uint tx_probe_rs; + uint tx_beacons; + uint rx_auth_rq; + uint rx_auth_rs_ok; + uint rx_auth_rs_err; + uint tx_auth_rq; + uint no_auth_rs; + uint no_ass_rs; + uint tx_ass_rq; + uint rx_ass_rq; + uint tx_probe_rq; + uint reassoc; + uint swtxstop; + uint swtxawake; +}; + +#define SEC_KEY_1 (1<<0) +#define SEC_KEY_2 (1<<1) +#define SEC_KEY_3 (1<<2) +#define SEC_KEY_4 (1<<3) +#define SEC_ACTIVE_KEY (1<<4) +#define SEC_AUTH_MODE (1<<5) +#define SEC_UNICAST_GROUP (1<<6) +#define SEC_LEVEL (1<<7) +#define SEC_ENABLED (1<<8) + +#define SEC_LEVEL_0 0 /* None */ +#define SEC_LEVEL_1 1 /* WEP 40 and 104 bit */ +#define SEC_LEVEL_2 2 /* Level 1 + TKIP */ +#define SEC_LEVEL_2_CKIP 3 /* Level 1 + CKIP */ +#define SEC_LEVEL_3 4 /* Level 2 + CCMP */ + +#define WEP_KEYS 4 +#define WEP_KEY_LEN 13 + +#ifdef CONFIG_IEEE80211W +#define BIP_MAX_KEYID 5 +#define BIP_AAD_SIZE 20 +#endif //CONFIG_IEEE80211W + +#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) + +struct ieee80211_security { + u16 active_key:2, + enabled:1, + auth_mode:2, + auth_algo:4, + unicast_uses_group:1; + u8 key_sizes[WEP_KEYS]; + u8 keys[WEP_KEYS][WEP_KEY_LEN]; + u8 level; + u16 flags; +} __attribute__ ((packed)); + +#endif + +#ifdef PLATFORM_WINDOWS + +#pragma pack(1) +struct ieee80211_security { + u16 active_key:2, + enabled:1, + auth_mode:2, + auth_algo:4, + unicast_uses_group:1; + u8 key_sizes[WEP_KEYS]; + u8 keys[WEP_KEYS][WEP_KEY_LEN]; + u8 level; + u16 flags; +} ; +#pragma pack() + +#endif + +/* + + 802.11 data frame from AP + + ,-------------------------------------------------------------------. +Bytes | 2 | 2 | 6 | 6 | 6 | 2 | 0..2312 | 4 | + |------|------|---------|---------|---------|------|---------|------| +Desc. | ctrl | dura | DA/RA | TA | SA | Sequ | frame | fcs | + | | tion | (BSSID) | | | ence | data | | + `-------------------------------------------------------------------' + +Total: 28-2340 bytes + +*/ + +struct ieee80211_header_data { + u16 frame_ctl; + u16 duration_id; + u8 addr1[6]; + u8 addr2[6]; + u8 addr3[6]; + u16 seq_ctrl; +}; + +#define BEACON_PROBE_SSID_ID_POSITION 12 + +/* Management Frame Information Element Types */ +#define MFIE_TYPE_SSID 0 +#define MFIE_TYPE_RATES 1 +#define MFIE_TYPE_FH_SET 2 +#define MFIE_TYPE_DS_SET 3 +#define MFIE_TYPE_CF_SET 4 +#define MFIE_TYPE_TIM 5 +#define MFIE_TYPE_IBSS_SET 6 +#define MFIE_TYPE_CHALLENGE 16 +#define MFIE_TYPE_ERP 42 +#define MFIE_TYPE_RSN 48 +#define MFIE_TYPE_RATES_EX 50 +#define MFIE_TYPE_GENERIC 221 + +#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) + +struct ieee80211_info_element_hdr { + u8 id; + u8 len; +} __attribute__ ((packed)); + +struct ieee80211_info_element { + u8 id; + u8 len; + u8 data[0]; +} __attribute__ ((packed)); +#endif + +#ifdef PLATFORM_WINDOWS + +#pragma pack(1) +struct ieee80211_info_element_hdr { + u8 id; + u8 len; +} ; + +struct ieee80211_info_element { + u8 id; + u8 len; + u8 data[0]; +} ; +#pragma pack() + +#endif + + +/* + * These are the data types that can make up management packets + * + u16 auth_algorithm; + u16 auth_sequence; + u16 beacon_interval; + u16 capability; + u8 current_ap[ETH_ALEN]; + u16 listen_interval; + struct { + u16 association_id:14, reserved:2; + } __attribute__ ((packed)); + u32 time_stamp[2]; + u16 reason; + u16 status; +*/ + +#define IEEE80211_DEFAULT_TX_ESSID "Penguin" +#define IEEE80211_DEFAULT_BASIC_RATE 10 + + +#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) + + +struct ieee80211_authentication { + struct ieee80211_header_data header; + u16 algorithm; + u16 transaction; + u16 status; + //struct ieee80211_info_element_hdr info_element; +} __attribute__ ((packed)); + + +struct ieee80211_probe_response { + struct ieee80211_header_data header; + u32 time_stamp[2]; + u16 beacon_interval; + u16 capability; + struct ieee80211_info_element info_element; +} __attribute__ ((packed)); + +struct ieee80211_probe_request { + struct ieee80211_header_data header; + /*struct ieee80211_info_element info_element;*/ +} __attribute__ ((packed)); + +struct ieee80211_assoc_request_frame { + struct rtw_ieee80211_hdr_3addr header; + u16 capability; + u16 listen_interval; + //u8 current_ap[ETH_ALEN]; + struct ieee80211_info_element_hdr info_element; +} __attribute__ ((packed)); + +struct ieee80211_assoc_response_frame { + struct rtw_ieee80211_hdr_3addr header; + u16 capability; + u16 status; + u16 aid; +// struct ieee80211_info_element info_element; /* supported rates */ +} __attribute__ ((packed)); +#endif + + + +#ifdef PLATFORM_WINDOWS + +#pragma pack(1) + +struct ieee80211_authentication { + struct ieee80211_header_data header; + u16 algorithm; + u16 transaction; + u16 status; + //struct ieee80211_info_element_hdr info_element; +} ; + + +struct ieee80211_probe_response { + struct ieee80211_header_data header; + u32 time_stamp[2]; + u16 beacon_interval; + u16 capability; + struct ieee80211_info_element info_element; +} ; + +struct ieee80211_probe_request { + struct ieee80211_header_data header; + /*struct ieee80211_info_element info_element;*/ +} ; + +struct ieee80211_assoc_request_frame { + struct rtw_ieee80211_hdr_3addr header; + u16 capability; + u16 listen_interval; + //u8 current_ap[ETH_ALEN]; + struct ieee80211_info_element_hdr info_element; +} ; + +struct ieee80211_assoc_response_frame { + struct rtw_ieee80211_hdr_3addr header; + u16 capability; + u16 status; + u16 aid; +// struct ieee80211_info_element info_element; /* supported rates */ +}; + +#pragma pack() + +#endif + + + + +struct ieee80211_txb { + u8 nr_frags; + u8 encrypted; + u16 reserved; + u16 frag_size; + u16 payload_size; + struct sk_buff *fragments[0]; +}; + + +/* SWEEP TABLE ENTRIES NUMBER*/ +#define MAX_SWEEP_TAB_ENTRIES 42 +#define MAX_SWEEP_TAB_ENTRIES_PER_PACKET 7 +/* MAX_RATES_LENGTH needs to be 12. The spec says 8, and many APs + * only use 8, and then use extended rates for the remaining supported + * rates. Other APs, however, stick all of their supported rates on the + * main rates information element... */ +#define MAX_RATES_LENGTH ((u8)12) +#define MAX_RATES_EX_LENGTH ((u8)16) +#define MAX_NETWORK_COUNT 128 +#define MAX_CHANNEL_NUMBER 161 +#define IEEE80211_SOFTMAC_SCAN_TIME 400 +//(HZ / 2) +#define IEEE80211_SOFTMAC_ASSOC_RETRY_TIME (HZ * 2) + +#define CRC_LENGTH 4U + +#define MAX_WPA_IE_LEN (256) +#define MAX_WPS_IE_LEN (512) +#define MAX_P2P_IE_LEN (256) +#define MAX_WFD_IE_LEN (128) + +#define NETWORK_EMPTY_ESSID (1<<0) +#define NETWORK_HAS_OFDM (1<<1) +#define NETWORK_HAS_CCK (1<<2) + +#define IEEE80211_DTIM_MBCAST 4 +#define IEEE80211_DTIM_UCAST 2 +#define IEEE80211_DTIM_VALID 1 +#define IEEE80211_DTIM_INVALID 0 + +#define IEEE80211_PS_DISABLED 0 +#define IEEE80211_PS_UNICAST IEEE80211_DTIM_UCAST +#define IEEE80211_PS_MBCAST IEEE80211_DTIM_MBCAST +#define IW_ESSID_MAX_SIZE 32 +#if 0 +struct ieee80211_network { + /* These entries are used to identify a unique network */ + u8 bssid[ETH_ALEN]; + u8 channel; + /* Ensure null-terminated for any debug msgs */ + u8 ssid[IW_ESSID_MAX_SIZE + 1]; + u8 ssid_len; + u8 rssi; //relative signal strength + u8 sq; //signal quality + + /* These are network statistics */ + //struct ieee80211_rx_stats stats; + u16 capability; + u16 aid; + u8 rates[MAX_RATES_LENGTH]; + u8 rates_len; + u8 rates_ex[MAX_RATES_EX_LENGTH]; + u8 rates_ex_len; + + u8 edca_parmsets[18]; + + u8 mode; + u8 flags; + u8 time_stamp[8]; + u16 beacon_interval; + u16 listen_interval; + u16 atim_window; + u8 wpa_ie[MAX_WPA_IE_LEN]; + size_t wpa_ie_len; + u8 rsn_ie[MAX_WPA_IE_LEN]; + size_t rsn_ie_len; + u8 country[6]; + u8 dtim_period; + u8 dtim_data; + u8 power_constraint; + u8 qosinfo; + u8 qbssload[5]; + u8 network_type; + int join_res; + unsigned long last_scanned; +}; +#endif +/* +join_res: +-1: authentication fail +-2: association fail +> 0: TID +*/ + +#ifndef PLATFORM_FREEBSD //Baron BSD has already defined + +enum ieee80211_state { + + /* the card is not linked at all */ + IEEE80211_NOLINK = 0, + + /* IEEE80211_ASSOCIATING* are for BSS client mode + * the driver shall not perform RX filtering unless + * the state is LINKED. + * The driver shall just check for the state LINKED and + * defaults to NOLINK for ALL the other states (including + * LINKED_SCANNING) + */ + + /* the association procedure will start (wq scheduling)*/ + IEEE80211_ASSOCIATING, + IEEE80211_ASSOCIATING_RETRY, + + /* the association procedure is sending AUTH request*/ + IEEE80211_ASSOCIATING_AUTHENTICATING, + + /* the association procedure has successfully authentcated + * and is sending association request + */ + IEEE80211_ASSOCIATING_AUTHENTICATED, + + /* the link is ok. the card associated to a BSS or linked + * to a ibss cell or acting as an AP and creating the bss + */ + IEEE80211_LINKED, + + /* same as LINKED, but the driver shall apply RX filter + * rules as we are in NO_LINK mode. As the card is still + * logically linked, but it is doing a syncro site survey + * then it will be back to LINKED state. + */ + IEEE80211_LINKED_SCANNING, + +}; +#endif //PLATFORM_FREEBSD + +#define DEFAULT_MAX_SCAN_AGE (15 * HZ) +#define DEFAULT_FTS 2346 +#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" +#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5] +#define IP_FMT "%d.%d.%d.%d" +#define IP_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3] +#define PORT_FMT "%u" +#define PORT_ARG(x) ntohs(*((u16 *)(x))) + +#ifdef PLATFORM_FREEBSD //Baron change func to macro +#define is_multicast_mac_addr(Addr) ((((Addr[0]) & 0x01) == 0x01) && ((Addr[0]) != 0xff)) +#define is_broadcast_mac_addr(Addr) ((((Addr[0]) & 0xff) == 0xff) && (((Addr[1]) & 0xff) == 0xff) && \ +(((Addr[2]) & 0xff) == 0xff) && (((Addr[3]) & 0xff) == 0xff) && (((Addr[4]) & 0xff) == 0xff) && \ +(((Addr[5]) & 0xff) == 0xff)) +#else +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0)) +static inline int is_multicast_mac_addr(const u8 *addr) +#else +extern __inline int is_multicast_mac_addr(const u8 *addr) +#endif +{ + return ((addr[0] != 0xff) && (0x01 & addr[0])); +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0)) +static inline int is_broadcast_mac_addr(const u8 *addr) +#else +extern __inline int is_broadcast_mac_addr(const u8 *addr) +#endif + +{ + return ((addr[0] == 0xff) && (addr[1] == 0xff) && (addr[2] == 0xff) && \ + (addr[3] == 0xff) && (addr[4] == 0xff) && (addr[5] == 0xff)); +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 18, 0)) +static inline int is_zero_mac_addr(const u8 *addr) +#else +extern __inline int is_zero_mac_addr(const u8 *addr) +#endif +{ + return ((addr[0] == 0x00) && (addr[1] == 0x00) && (addr[2] == 0x00) && \ + (addr[3] == 0x00) && (addr[4] == 0x00) && (addr[5] == 0x00)); +} +#endif //PLATFORM_FREEBSD + +#define CFG_IEEE80211_RESERVE_FCS (1<<0) +#define CFG_IEEE80211_COMPUTE_FCS (1<<1) + +typedef struct tx_pending_t{ + int frag; + struct ieee80211_txb *txb; +}tx_pending_t; + + + +#define TID_NUM 16 + +#define IEEE_A (1<<0) +#define IEEE_B (1<<1) +#define IEEE_G (1<<2) +#define IEEE_MODE_MASK (IEEE_A|IEEE_B|IEEE_G) + +//Baron move to ieee80211.c +int ieee80211_is_empty_essid(const char *essid, int essid_len); +int ieee80211_get_hdrlen(u16 fc); + +#if 0 +/* Action frame categories (IEEE 802.11-2007, 7.3.1.11, Table 7-24) */ +#define WLAN_ACTION_SPECTRUM_MGMT 0 +#define WLAN_ACTION_QOS 1 +#define WLAN_ACTION_DLS 2 +#define WLAN_ACTION_BLOCK_ACK 3 +#define WLAN_ACTION_RADIO_MEASUREMENT 5 +#define WLAN_ACTION_FT 6 +#define WLAN_ACTION_SA_QUERY 8 +#define WLAN_ACTION_WMM 17 +#endif + + +/* Action category code */ +enum rtw_ieee80211_category { + RTW_WLAN_CATEGORY_SPECTRUM_MGMT = 0, + RTW_WLAN_CATEGORY_QOS = 1, + RTW_WLAN_CATEGORY_DLS = 2, + RTW_WLAN_CATEGORY_BACK = 3, + RTW_WLAN_CATEGORY_PUBLIC = 4, //IEEE 802.11 public action frames + RTW_WLAN_CATEGORY_RADIO_MEASUREMENT = 5, + RTW_WLAN_CATEGORY_FT = 6, + RTW_WLAN_CATEGORY_HT = 7, + RTW_WLAN_CATEGORY_SA_QUERY = 8, + RTW_WLAN_CATEGORY_UNPROTECTED_WNM = 11, // add for CONFIG_IEEE80211W, none 11w also can use + RTW_WLAN_CATEGORY_TDLS = 12, + RTW_WLAN_CATEGORY_SELF_PROTECTED = 15, // add for CONFIG_IEEE80211W, none 11w also can use + RTW_WLAN_CATEGORY_WMM = 17, + RTW_WLAN_CATEGORY_VHT = 21, + RTW_WLAN_CATEGORY_P2P = 0x7f,//P2P action frames +}; + +/* SPECTRUM_MGMT action code */ +enum rtw_ieee80211_spectrum_mgmt_actioncode { + RTW_WLAN_ACTION_SPCT_MSR_REQ = 0, + RTW_WLAN_ACTION_SPCT_MSR_RPRT = 1, + RTW_WLAN_ACTION_SPCT_TPC_REQ = 2, + RTW_WLAN_ACTION_SPCT_TPC_RPRT = 3, + RTW_WLAN_ACTION_SPCT_CHL_SWITCH = 4, + RTW_WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5, +}; + +enum _PUBLIC_ACTION{ + ACT_PUBLIC_BSSCOEXIST = 0, // 20/40 BSS Coexistence + ACT_PUBLIC_DSE_ENABLE = 1, + ACT_PUBLIC_DSE_DEENABLE = 2, + ACT_PUBLIC_DSE_REG_LOCATION = 3, + ACT_PUBLIC_EXT_CHL_SWITCH = 4, + ACT_PUBLIC_DSE_MSR_REQ = 5, + ACT_PUBLIC_DSE_MSR_RPRT = 6, + ACT_PUBLIC_MP = 7, // Measurement Pilot + ACT_PUBLIC_DSE_PWR_CONSTRAINT = 8, + ACT_PUBLIC_VENDOR = 9, // for WIFI_DIRECT + ACT_PUBLIC_GAS_INITIAL_REQ = 10, + ACT_PUBLIC_GAS_INITIAL_RSP = 11, + ACT_PUBLIC_GAS_COMEBACK_REQ = 12, + ACT_PUBLIC_GAS_COMEBACK_RSP = 13, + ACT_PUBLIC_TDLS_DISCOVERY_RSP = 14, + ACT_PUBLIC_LOCATION_TRACK = 15, + ACT_PUBLIC_MAX +}; + +#ifdef CONFIG_TDLS +enum TDLS_ACTION_FIELD{ + TDLS_SETUP_REQUEST = 0, + TDLS_SETUP_RESPONSE = 1, + TDLS_SETUP_CONFIRM = 2, + TDLS_TEARDOWN = 3, + TDLS_PEER_TRAFFIC_INDICATION = 4, + TDLS_CHANNEL_SWITCH_REQUEST = 5, + TDLS_CHANNEL_SWITCH_RESPONSE = 6, + TDLS_PEER_PSM_REQUEST = 7, + TDLS_PEER_PSM_RESPONSE = 8, + TDLS_PEER_TRAFFIC_RESPONSE = 9, + TDLS_DISCOVERY_REQUEST = 10, + TDLS_DISCOVERY_RESPONSE = 14, //it's used in public action frame +}; + +#define TUNNELED_PROBE_REQ 15 +#define TUNNELED_PROBE_RSP 16 +#endif //CONFIG_TDLS + +/* BACK action code */ +enum rtw_ieee80211_back_actioncode { + RTW_WLAN_ACTION_ADDBA_REQ = 0, + RTW_WLAN_ACTION_ADDBA_RESP = 1, + RTW_WLAN_ACTION_DELBA = 2, +}; + +/* HT features action code */ +enum rtw_ieee80211_ht_actioncode { + RTW_WLAN_ACTION_HT_NOTI_CHNL_WIDTH = 0, + RTW_WLAN_ACTION_HT_SM_PS = 1, + RTW_WLAN_ACTION_HT_PSMP = 2, + RTW_WLAN_ACTION_HT_SET_PCO_PHASE = 3, + RTW_WLAN_ACTION_HT_CSI = 4, + RTW_WLAN_ACTION_HT_NON_COMPRESS_BEAMFORMING = 5, + RTW_WLAN_ACTION_HT_COMPRESS_BEAMFORMING = 6, + RTW_WLAN_ACTION_HT_ASEL_FEEDBACK = 7, +}; + +/* BACK (block-ack) parties */ +enum rtw_ieee80211_back_parties { + RTW_WLAN_BACK_RECIPIENT = 0, + RTW_WLAN_BACK_INITIATOR = 1, + RTW_WLAN_BACK_TIMER = 2, +}; + +/*20/40 BSS Coexistence element */ +#define RTW_WLAN_20_40_BSS_COEX_INFO_REQ BIT(0) +#define RTW_WLAN_20_40_BSS_COEX_40MHZ_INTOL BIT(1) +#define RTW_WLAN_20_40_BSS_COEX_20MHZ_WIDTH_REQ BIT(2) +#define RTW_WLAN_20_40_BSS_COEX_OBSS_EXEMPT_REQ BIT(3) +#define RTW_WLAN_20_40_BSS_COEX_OBSS_EXEMPT_GRNT BIT(4) + +/* VHT features action code */ +enum rtw_ieee80211_vht_actioncode{ + RTW_WLAN_ACTION_VHT_COMPRESSED_BEAMFORMING = 0, + RTW_WLAN_ACTION_VHT_GROUPID_MANAGEMENT = 1, + RTW_WLAN_ACTION_VHT_OPMODE_NOTIFICATION = 2, +}; + + +#define OUI_MICROSOFT 0x0050f2 /* Microsoft (also used in Wi-Fi specs) + * 00:50:F2 */ +#ifndef PLATFORM_FREEBSD //Baron BSD has defined +#define WME_OUI_TYPE 2 +#endif //PLATFORM_FREEBSD +#define WME_OUI_SUBTYPE_INFORMATION_ELEMENT 0 +#define WME_OUI_SUBTYPE_PARAMETER_ELEMENT 1 +#define WME_OUI_SUBTYPE_TSPEC_ELEMENT 2 +#define WME_VERSION 1 + +#define WME_ACTION_CODE_SETUP_REQUEST 0 +#define WME_ACTION_CODE_SETUP_RESPONSE 1 +#define WME_ACTION_CODE_TEARDOWN 2 + +#define WME_SETUP_RESPONSE_STATUS_ADMISSION_ACCEPTED 0 +#define WME_SETUP_RESPONSE_STATUS_INVALID_PARAMETERS 1 +#define WME_SETUP_RESPONSE_STATUS_REFUSED 3 + +#define WME_TSPEC_DIRECTION_UPLINK 0 +#define WME_TSPEC_DIRECTION_DOWNLINK 1 +#define WME_TSPEC_DIRECTION_BI_DIRECTIONAL 3 + + +#define OUI_BROADCOM 0x00904c /* Broadcom (Epigram) */ + +#define VENDOR_HT_CAPAB_OUI_TYPE 0x33 /* 00-90-4c:0x33 */ + +/** + * enum rtw_ieee80211_channel_flags - channel flags + * + * Channel flags set by the regulatory control code. + * + * @RTW_IEEE80211_CHAN_DISABLED: This channel is disabled. + * @RTW_IEEE80211_CHAN_PASSIVE_SCAN: Only passive scanning is permitted + * on this channel. + * @RTW_IEEE80211_CHAN_NO_IBSS: IBSS is not allowed on this channel. + * @RTW_IEEE80211_CHAN_RADAR: Radar detection is required on this channel. + * @RTW_IEEE80211_CHAN_NO_HT40PLUS: extension channel above this channel + * is not permitted. + * @RTW_IEEE80211_CHAN_NO_HT40MINUS: extension channel below this channel + * is not permitted. + */ + enum rtw_ieee80211_channel_flags { + RTW_IEEE80211_CHAN_DISABLED = 1<<0, + RTW_IEEE80211_CHAN_PASSIVE_SCAN = 1<<1, + RTW_IEEE80211_CHAN_NO_IBSS = 1<<2, + RTW_IEEE80211_CHAN_RADAR = 1<<3, + RTW_IEEE80211_CHAN_NO_HT40PLUS = 1<<4, + RTW_IEEE80211_CHAN_NO_HT40MINUS = 1<<5, + }; + + #define RTW_IEEE80211_CHAN_NO_HT40 \ + (RTW_IEEE80211_CHAN_NO_HT40PLUS | RTW_IEEE80211_CHAN_NO_HT40MINUS) + +/* Represent channel details, subset of ieee80211_channel */ +struct rtw_ieee80211_channel { + //enum ieee80211_band band; + //u16 center_freq; + u16 hw_value; + u32 flags; + //int max_antenna_gain; + //int max_power; + //int max_reg_power; + //bool beacon_found; + //u32 orig_flags; + //int orig_mag; + //int orig_mpwr; +}; + +#define CHAN_FMT \ + /*"band:%d, "*/ \ + /*"center_freq:%u, "*/ \ + "hw_value:%u, " \ + "flags:0x%08x" \ + /*"max_antenna_gain:%d\n"*/ \ + /*"max_power:%d\n"*/ \ + /*"max_reg_power:%d\n"*/ \ + /*"beacon_found:%u\n"*/ \ + /*"orig_flags:0x%08x\n"*/ \ + /*"orig_mag:%d\n"*/ \ + /*"orig_mpwr:%d\n"*/ + +#define CHAN_ARG(channel) \ + /*(channel)->band*/ \ + /*, (channel)->center_freq*/ \ + (channel)->hw_value \ + , (channel)->flags \ + /*, (channel)->max_antenna_gain*/ \ + /*, (channel)->max_power*/ \ + /*, (channel)->max_reg_power*/ \ + /*, (channel)->beacon_found*/ \ + /*, (channel)->orig_flags*/ \ + /*, (channel)->orig_mag*/ \ + /*, (channel)->orig_mpwr*/ \ + +/* Parsed Information Elements */ +struct rtw_ieee802_11_elems { + u8 *ssid; + u8 ssid_len; + u8 *supp_rates; + u8 supp_rates_len; + u8 *fh_params; + u8 fh_params_len; + u8 *ds_params; + u8 ds_params_len; + u8 *cf_params; + u8 cf_params_len; + u8 *tim; + u8 tim_len; + u8 *ibss_params; + u8 ibss_params_len; + u8 *challenge; + u8 challenge_len; + u8 *erp_info; + u8 erp_info_len; + u8 *ext_supp_rates; + u8 ext_supp_rates_len; + u8 *wpa_ie; + u8 wpa_ie_len; + u8 *rsn_ie; + u8 rsn_ie_len; + u8 *wme; + u8 wme_len; + u8 *wme_tspec; + u8 wme_tspec_len; + u8 *wps_ie; + u8 wps_ie_len; + u8 *power_cap; + u8 power_cap_len; + u8 *supp_channels; + u8 supp_channels_len; + u8 *mdie; + u8 mdie_len; + u8 *ftie; + u8 ftie_len; + u8 *timeout_int; + u8 timeout_int_len; + u8 *ht_capabilities; + u8 ht_capabilities_len; + u8 *ht_operation; + u8 ht_operation_len; + u8 *vendor_ht_cap; + u8 vendor_ht_cap_len; + u8 *vht_capabilities; + u8 vht_capabilities_len; + u8 *vht_operation; + u8 vht_operation_len; + u8 *vht_op_mode_notify; + u8 vht_op_mode_notify_len; +}; + +typedef enum { ParseOK = 0, ParseUnknown = 1, ParseFailed = -1 } ParseRes; + +ParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len, + struct rtw_ieee802_11_elems *elems, + int show_errors); + +u8 *rtw_set_fixed_ie(unsigned char *pbuf, unsigned int len, unsigned char *source, unsigned int *frlen); +u8 *rtw_set_ie(u8 *pbuf, sint index, uint len, u8 *source, uint *frlen); + +enum secondary_ch_offset { + SCN = 0, /* no secondary channel */ + SCA = 1, /* secondary channel above */ + SCB = 3, /* secondary channel below */ +}; +u8 secondary_ch_offset_to_hal_ch_offset(u8 ch_offset); +u8 hal_ch_offset_to_secondary_ch_offset(u8 ch_offset); +u8 *rtw_set_ie_ch_switch(u8 *buf, u32 *buf_len, u8 ch_switch_mode, u8 new_ch, u8 ch_switch_cnt); +u8 *rtw_set_ie_secondary_ch_offset(u8 *buf, u32 *buf_len, u8 secondary_ch_offset); +u8 *rtw_set_ie_mesh_ch_switch_parm(u8 *buf, u32 *buf_len, u8 ttl, u8 flags, u16 reason, u16 precedence); + +u8 *rtw_get_ie(u8*pbuf, sint index, sint *len, sint limit); +u8 *rtw_get_ie_ex(u8 *in_ie, uint in_len, u8 eid, u8 *oui, u8 oui_len, u8 *ie, uint *ielen); +int rtw_ies_remove_ie(u8 *ies, uint *ies_len, uint offset, u8 eid, u8 *oui, u8 oui_len); + +void rtw_set_supported_rate(u8* SupportedRates, uint mode) ; + +unsigned char *rtw_get_wpa_ie(unsigned char *pie, int *wpa_ie_len, int limit); +unsigned char *rtw_get_wpa2_ie(unsigned char *pie, int *rsn_ie_len, int limit); +int rtw_get_wpa_cipher_suite(u8 *s); +int rtw_get_wpa2_cipher_suite(u8 *s); +int rtw_get_wapi_ie(u8 *in_ie,uint in_len,u8 *wapi_ie,u16 *wapi_len); +int rtw_parse_wpa_ie(u8* wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x); +int rtw_parse_wpa2_ie(u8* wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher, int *is_8021x); + +int rtw_get_sec_ie(u8 *in_ie,uint in_len,u8 *rsn_ie,u16 *rsn_len,u8 *wpa_ie,u16 *wpa_len); + +u8 rtw_is_wps_ie(u8 *ie_ptr, uint *wps_ielen); +u8 *rtw_get_wps_ie_from_scan_queue(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen, u8 frame_type); +u8 *rtw_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen); +u8 *rtw_get_wps_attr(u8 *wps_ie, uint wps_ielen, u16 target_attr_id ,u8 *buf_attr, u32 *len_attr); +u8 *rtw_get_wps_attr_content(u8 *wps_ie, uint wps_ielen, u16 target_attr_id ,u8 *buf_content, uint *len_content); + +/** + * for_each_ie - iterate over continuous IEs + * @ie: + * @buf: + * @buf_len: + */ +#define for_each_ie(ie, buf, buf_len) \ + for (ie = (void*)buf; (((u8*)ie) - ((u8*)buf) + 1) < buf_len; ie = (void*)(((u8*)ie) + *(((u8*)ie)+1) + 2)) + +void dump_ies(void *sel, u8 *buf, u32 buf_len); + +#ifdef CONFIG_80211N_HT +void dump_ht_cap_ie_content(void *sel, u8 *buf, u32 buf_len); +#endif + +void dump_wps_ie(void *sel, u8 *ie, u32 ie_len); + +void rtw_ies_get_chbw(u8 *ies, int ies_len, u8 *ch, u8 *bw, u8 *offset); + +void rtw_bss_get_chbw(WLAN_BSSID_EX *bss, u8 *ch, u8 *bw, u8 *offset); + +bool rtw_is_chbw_grouped(u8 ch_a, u8 bw_a, u8 offset_a + , u8 ch_b, u8 bw_b, u8 offset_b); +void rtw_sync_chbw(u8 *req_ch, u8 *req_bw, u8 *req_offset + , u8 *g_ch, u8 *g_bw, u8 *g_offset); + +u32 rtw_get_p2p_merged_ies_len(u8 *in_ie, u32 in_len); +int rtw_p2p_merge_ies(u8 *in_ie, u32 in_len, u8 *merge_ie); +void dump_p2p_ie(void *sel, u8 *ie, u32 ie_len); +u8 *rtw_get_p2p_ie(u8 *in_ie, int in_len, u8 *p2p_ie, uint *p2p_ielen); +u8 *rtw_get_p2p_attr(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id ,u8 *buf_attr, u32 *len_attr); +u8 *rtw_get_p2p_attr_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id ,u8 *buf_content, uint *len_content); +u32 rtw_set_p2p_attr_content(u8 *pbuf, u8 attr_id, u16 attr_len, u8 *pdata_attr); +uint rtw_del_p2p_ie(u8 *ies, uint ies_len_ori, const char *msg); +uint rtw_del_p2p_attr(u8 *ie, uint ielen_ori, u8 attr_id); +u8 *rtw_bss_ex_get_p2p_ie(WLAN_BSSID_EX *bss_ex, u8 *p2p_ie, uint *p2p_ielen); +void rtw_bss_ex_del_p2p_ie(WLAN_BSSID_EX *bss_ex); +void rtw_bss_ex_del_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id); + +void dump_wfd_ie(void *sel, u8 *ie, u32 ie_len); +u8 *rtw_get_wfd_ie(u8 *in_ie, int in_len, u8 *wfd_ie, uint *wfd_ielen); +u8 *rtw_get_wfd_attr(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_attr, u32 *len_attr); +u8 *rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id, u8 *buf_content, uint *len_content); +uint rtw_del_wfd_ie(u8 *ies, uint ies_len_ori, const char *msg); +uint rtw_del_wfd_attr(u8 *ie, uint ielen_ori, u8 attr_id); +u8 *rtw_bss_ex_get_wfd_ie(WLAN_BSSID_EX *bss_ex, u8 *wfd_ie, uint *wfd_ielen); +void rtw_bss_ex_del_wfd_ie(WLAN_BSSID_EX *bss_ex); +void rtw_bss_ex_del_wfd_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id); + +uint rtw_get_rateset_len(u8 *rateset); + +struct registry_priv; +int rtw_generate_ie(struct registry_priv *pregistrypriv); + +int rtw_get_bit_value_from_ieee_value(u8 val); + +uint rtw_is_cckrates_included(u8 *rate); + +uint rtw_is_cckratesonly_included(u8 *rate); + +int rtw_check_network_type(unsigned char *rate, int ratelen, int channel); + +void rtw_get_bcn_info(struct wlan_network *pnetwork); + +u8 rtw_check_invalid_mac_address(u8 *mac_addr, u8 check_local_bit); +void rtw_macaddr_cfg(u8 *out, const u8 *hw_mac_addr); + +u16 rtw_mcs_rate(u8 rf_type, u8 bw_40MHz, u8 short_GI, unsigned char * MCS_rate); +u8 rtw_ht_mcsset_to_nss(u8 *supp_mcs_set); + +int rtw_action_frame_parse(const u8 *frame, u32 frame_len, u8* category, u8 *action); +const char *action_public_str(u8 action); + +u8 key_2char2num(u8 hch, u8 lch); +u8 str_2char2num(u8 hch, u8 lch); +void macstr2num(u8 *dst, u8 *src); +u8 convert_ip_addr(u8 hch, u8 mch, u8 lch); +int wifirate2_ratetbl_inx(unsigned char rate); + +#endif /* IEEE80211_H */ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/ieee80211_ext.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/ieee80211_ext.h new file mode 100644 index 000000000..3e55305e1 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/ieee80211_ext.h @@ -0,0 +1,477 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __IEEE80211_EXT_H +#define __IEEE80211_EXT_H + +#include +#include +#include + +#define WMM_OUI_TYPE 2 +#define WMM_OUI_SUBTYPE_INFORMATION_ELEMENT 0 +#define WMM_OUI_SUBTYPE_PARAMETER_ELEMENT 1 +#define WMM_OUI_SUBTYPE_TSPEC_ELEMENT 2 +#define WMM_VERSION 1 + +#define WPA_PROTO_WPA BIT(0) +#define WPA_PROTO_RSN BIT(1) + +#define WPA_KEY_MGMT_IEEE8021X BIT(0) +#define WPA_KEY_MGMT_PSK BIT(1) +#define WPA_KEY_MGMT_NONE BIT(2) +#define WPA_KEY_MGMT_IEEE8021X_NO_WPA BIT(3) +#define WPA_KEY_MGMT_WPA_NONE BIT(4) + + +#define WPA_CAPABILITY_PREAUTH BIT(0) +#define WPA_CAPABILITY_MGMT_FRAME_PROTECTION BIT(6) +#define WPA_CAPABILITY_PEERKEY_ENABLED BIT(9) + + +#define PMKID_LEN 16 + + +#ifdef PLATFORM_LINUX +struct wpa_ie_hdr { + u8 elem_id; + u8 len; + u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */ + u8 version[2]; /* little endian */ +}__attribute__ ((packed)); + +struct rsn_ie_hdr { + u8 elem_id; /* WLAN_EID_RSN */ + u8 len; + u8 version[2]; /* little endian */ +}__attribute__ ((packed)); + +struct wme_ac_parameter { +#if defined(CONFIG_LITTLE_ENDIAN) + /* byte 1 */ + u8 aifsn:4, + acm:1, + aci:2, + reserved:1; + + /* byte 2 */ + u8 eCWmin:4, + eCWmax:4; +#elif defined(CONFIG_BIG_ENDIAN) + /* byte 1 */ + u8 reserved:1, + aci:2, + acm:1, + aifsn:4; + + /* byte 2 */ + u8 eCWmax:4, + eCWmin:4; +#else +#error "Please fix " +#endif + + /* bytes 3 & 4 */ + u16 txopLimit; +} __attribute__ ((packed)); + +struct wme_parameter_element { + /* required fields for WME version 1 */ + u8 oui[3]; + u8 oui_type; + u8 oui_subtype; + u8 version; + u8 acInfo; + u8 reserved; + struct wme_ac_parameter ac[4]; + +} __attribute__ ((packed)); + +#endif + +#ifdef PLATFORM_WINDOWS + +#pragma pack(1) + +struct wpa_ie_hdr { + u8 elem_id; + u8 len; + u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */ + u8 version[2]; /* little endian */ +}; + +struct rsn_ie_hdr { + u8 elem_id; /* WLAN_EID_RSN */ + u8 len; + u8 version[2]; /* little endian */ +}; + +#pragma pack() + +#endif + +#define WPA_PUT_LE16(a, val) \ + do { \ + (a)[1] = ((u16) (val)) >> 8; \ + (a)[0] = ((u16) (val)) & 0xff; \ + } while (0) + +#define WPA_PUT_BE32(a, val) \ + do { \ + (a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \ + (a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \ + (a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \ + (a)[3] = (u8) (((u32) (val)) & 0xff); \ + } while (0) + +#define WPA_PUT_LE32(a, val) \ + do { \ + (a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \ + (a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff); \ + (a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \ + (a)[0] = (u8) (((u32) (val)) & 0xff); \ + } while (0) + +#define RSN_SELECTOR_PUT(a, val) WPA_PUT_BE32((u8 *) (a), (val)) +//#define RSN_SELECTOR_PUT(a, val) WPA_PUT_LE32((u8 *) (a), (val)) + + + +/* Action category code */ +enum ieee80211_category { + WLAN_CATEGORY_SPECTRUM_MGMT = 0, + WLAN_CATEGORY_QOS = 1, + WLAN_CATEGORY_DLS = 2, + WLAN_CATEGORY_BACK = 3, + WLAN_CATEGORY_HT = 7, + WLAN_CATEGORY_WMM = 17, +}; + +/* SPECTRUM_MGMT action code */ +enum ieee80211_spectrum_mgmt_actioncode { + WLAN_ACTION_SPCT_MSR_REQ = 0, + WLAN_ACTION_SPCT_MSR_RPRT = 1, + WLAN_ACTION_SPCT_TPC_REQ = 2, + WLAN_ACTION_SPCT_TPC_RPRT = 3, + WLAN_ACTION_SPCT_CHL_SWITCH = 4, + WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5, +}; + +/* BACK action code */ +enum ieee80211_back_actioncode { + WLAN_ACTION_ADDBA_REQ = 0, + WLAN_ACTION_ADDBA_RESP = 1, + WLAN_ACTION_DELBA = 2, +}; + +/* HT features action code */ +enum ieee80211_ht_actioncode { + WLAN_ACTION_NOTIFY_CH_WIDTH = 0, + WLAN_ACTION_SM_PS = 1, + WLAN_ACTION_PSPM = 2, + WLAN_ACTION_PCO_PHASE = 3, + WLAN_ACTION_MIMO_CSI_MX = 4, + WLAN_ACTION_MIMO_NONCP_BF = 5, + WLAN_ACTION_MIMP_CP_BF = 6, + WLAN_ACTION_ASEL_INDICATES_FB = 7, + WLAN_ACTION_HI_INFO_EXCHG = 8, +}; + +/* BACK (block-ack) parties */ +enum ieee80211_back_parties { + WLAN_BACK_RECIPIENT = 0, + WLAN_BACK_INITIATOR = 1, + WLAN_BACK_TIMER = 2, +}; + +#ifdef PLATFORM_LINUX + +struct ieee80211_mgmt { + u16 frame_control; + u16 duration; + u8 da[6]; + u8 sa[6]; + u8 bssid[6]; + u16 seq_ctrl; + union { + struct { + u16 auth_alg; + u16 auth_transaction; + u16 status_code; + /* possibly followed by Challenge text */ + u8 variable[0]; + } __attribute__ ((packed)) auth; + struct { + u16 reason_code; + } __attribute__ ((packed)) deauth; + struct { + u16 capab_info; + u16 listen_interval; + /* followed by SSID and Supported rates */ + u8 variable[0]; + } __attribute__ ((packed)) assoc_req; + struct { + u16 capab_info; + u16 status_code; + u16 aid; + /* followed by Supported rates */ + u8 variable[0]; + } __attribute__ ((packed)) assoc_resp, reassoc_resp; + struct { + u16 capab_info; + u16 listen_interval; + u8 current_ap[6]; + /* followed by SSID and Supported rates */ + u8 variable[0]; + } __attribute__ ((packed)) reassoc_req; + struct { + u16 reason_code; + } __attribute__ ((packed)) disassoc; + struct { + __le64 timestamp; + u16 beacon_int; + u16 capab_info; + /* followed by some of SSID, Supported rates, + * FH Params, DS Params, CF Params, IBSS Params, TIM */ + u8 variable[0]; + } __attribute__ ((packed)) beacon; + struct { + /* only variable items: SSID, Supported rates */ + u8 variable[0]; + } __attribute__ ((packed)) probe_req; + struct { + __le64 timestamp; + u16 beacon_int; + u16 capab_info; + /* followed by some of SSID, Supported rates, + * FH Params, DS Params, CF Params, IBSS Params */ + u8 variable[0]; + } __attribute__ ((packed)) probe_resp; + struct { + u8 category; + union { + struct { + u8 action_code; + u8 dialog_token; + u8 status_code; + u8 variable[0]; + } __attribute__ ((packed)) wme_action; +#if 0 + struct{ + u8 action_code; + u8 element_id; + u8 length; + struct ieee80211_channel_sw_ie sw_elem; + } __attribute__ ((packed)) chan_switch; + struct{ + u8 action_code; + u8 dialog_token; + u8 element_id; + u8 length; + struct ieee80211_msrment_ie msr_elem; + } __attribute__ ((packed)) measurement; +#endif + struct{ + u8 action_code; + u8 dialog_token; + u16 capab; + u16 timeout; + u16 start_seq_num; + } __attribute__ ((packed)) addba_req; + struct{ + u8 action_code; + u8 dialog_token; + u16 status; + u16 capab; + u16 timeout; + } __attribute__ ((packed)) addba_resp; + struct{ + u8 action_code; + u16 params; + u16 reason_code; + } __attribute__ ((packed)) delba; + struct{ + u8 action_code; + /* capab_info for open and confirm, + * reason for close + */ + u16 aux; + /* Followed in plink_confirm by status + * code, AID and supported rates, + * and directly by supported rates in + * plink_open and plink_close + */ + u8 variable[0]; + } __attribute__ ((packed)) plink_action; + struct{ + u8 action_code; + u8 variable[0]; + } __attribute__ ((packed)) mesh_action; + } __attribute__ ((packed)) u; + } __attribute__ ((packed)) action; + } __attribute__ ((packed)) u; +}__attribute__ ((packed)); + +#endif + + +#ifdef PLATFORM_WINDOWS + +#pragma pack(1) + +struct ieee80211_mgmt { + u16 frame_control; + u16 duration; + u8 da[6]; + u8 sa[6]; + u8 bssid[6]; + u16 seq_ctrl; + union { + struct { + u16 auth_alg; + u16 auth_transaction; + u16 status_code; + /* possibly followed by Challenge text */ + u8 variable[0]; + } auth; + struct { + u16 reason_code; + } deauth; + struct { + u16 capab_info; + u16 listen_interval; + /* followed by SSID and Supported rates */ + u8 variable[0]; + } assoc_req; + struct { + u16 capab_info; + u16 status_code; + u16 aid; + /* followed by Supported rates */ + u8 variable[0]; + } assoc_resp, reassoc_resp; + struct { + u16 capab_info; + u16 listen_interval; + u8 current_ap[6]; + /* followed by SSID and Supported rates */ + u8 variable[0]; + } reassoc_req; + struct { + u16 reason_code; + } disassoc; +#if 0 + struct { + __le64 timestamp; + u16 beacon_int; + u16 capab_info; + /* followed by some of SSID, Supported rates, + * FH Params, DS Params, CF Params, IBSS Params, TIM */ + u8 variable[0]; + } beacon; + struct { + /* only variable items: SSID, Supported rates */ + u8 variable[0]; + } probe_req; + + struct { + __le64 timestamp; + u16 beacon_int; + u16 capab_info; + /* followed by some of SSID, Supported rates, + * FH Params, DS Params, CF Params, IBSS Params */ + u8 variable[0]; + } probe_resp; +#endif + struct { + u8 category; + union { + struct { + u8 action_code; + u8 dialog_token; + u8 status_code; + u8 variable[0]; + } wme_action; +/* + struct{ + u8 action_code; + u8 element_id; + u8 length; + struct ieee80211_channel_sw_ie sw_elem; + } chan_switch; + struct{ + u8 action_code; + u8 dialog_token; + u8 element_id; + u8 length; + struct ieee80211_msrment_ie msr_elem; + } measurement; +*/ + struct{ + u8 action_code; + u8 dialog_token; + u16 capab; + u16 timeout; + u16 start_seq_num; + } addba_req; + struct{ + u8 action_code; + u8 dialog_token; + u16 status; + u16 capab; + u16 timeout; + } addba_resp; + struct{ + u8 action_code; + u16 params; + u16 reason_code; + } delba; + struct{ + u8 action_code; + /* capab_info for open and confirm, + * reason for close + */ + u16 aux; + /* Followed in plink_confirm by status + * code, AID and supported rates, + * and directly by supported rates in + * plink_open and plink_close + */ + u8 variable[0]; + } plink_action; + struct{ + u8 action_code; + u8 variable[0]; + } mesh_action; + } u; + } action; + } u; +} ; + +#pragma pack() + +#endif + +/* mgmt header + 1 byte category code */ +#define IEEE80211_MIN_ACTION_SIZE FIELD_OFFSET(struct ieee80211_mgmt, u.action.u) + + + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/if_ether.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/if_ether.h new file mode 100644 index 000000000..93ed096df --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/if_ether.h @@ -0,0 +1,113 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef _LINUX_IF_ETHER_H +#define _LINUX_IF_ETHER_H + +/* + * IEEE 802.3 Ethernet magic constants. The frame sizes omit the preamble + * and FCS/CRC (frame check sequence). + */ + +#define ETH_ALEN 6 /* Octets in one ethernet addr */ +#define ETH_HLEN 14 /* Total octets in header. */ +#define ETH_ZLEN 60 /* Min. octets in frame sans FCS */ +#define ETH_DATA_LEN 1500 /* Max. octets in payload */ +#define ETH_FRAME_LEN 1514 /* Max. octets in frame sans FCS */ + +/* + * These are the defined Ethernet Protocol ID's. + */ + +#define ETH_P_LOOP 0x0060 /* Ethernet Loopback packet */ +#define ETH_P_PUP 0x0200 /* Xerox PUP packet */ +#define ETH_P_PUPAT 0x0201 /* Xerox PUP Addr Trans packet */ +#define ETH_P_IP 0x0800 /* Internet Protocol packet */ +#define ETH_P_X25 0x0805 /* CCITT X.25 */ +#define ETH_P_ARP 0x0806 /* Address Resolution packet */ +#define ETH_P_BPQ 0x08FF /* G8BPQ AX.25 Ethernet Packet [ NOT AN OFFICIALLY REGISTERED ID ] */ +#define ETH_P_IEEEPUP 0x0a00 /* Xerox IEEE802.3 PUP packet */ +#define ETH_P_IEEEPUPAT 0x0a01 /* Xerox IEEE802.3 PUP Addr Trans packet */ +#define ETH_P_DEC 0x6000 /* DEC Assigned proto */ +#define ETH_P_DNA_DL 0x6001 /* DEC DNA Dump/Load */ +#define ETH_P_DNA_RC 0x6002 /* DEC DNA Remote Console */ +#define ETH_P_DNA_RT 0x6003 /* DEC DNA Routing */ +#define ETH_P_LAT 0x6004 /* DEC LAT */ +#define ETH_P_DIAG 0x6005 /* DEC Diagnostics */ +#define ETH_P_CUST 0x6006 /* DEC Customer use */ +#define ETH_P_SCA 0x6007 /* DEC Systems Comms Arch */ +#define ETH_P_RARP 0x8035 /* Reverse Addr Res packet */ +#define ETH_P_ATALK 0x809B /* Appletalk DDP */ +#define ETH_P_AARP 0x80F3 /* Appletalk AARP */ +#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */ +#define ETH_P_IPX 0x8137 /* IPX over DIX */ +#define ETH_P_IPV6 0x86DD /* IPv6 over bluebook */ +#define ETH_P_PPP_DISC 0x8863 /* PPPoE discovery messages */ +#define ETH_P_PPP_SES 0x8864 /* PPPoE session messages */ +#define ETH_P_ATMMPOA 0x884c /* MultiProtocol Over ATM */ +#define ETH_P_ATMFATE 0x8884 /* Frame-based ATM Transport + * over Ethernet + */ + +/* + * Non DIX types. Won't clash for 1500 types. + */ + +#define ETH_P_802_3 0x0001 /* Dummy type for 802.3 frames */ +#define ETH_P_AX25 0x0002 /* Dummy protocol id for AX.25 */ +#define ETH_P_ALL 0x0003 /* Every packet (be careful!!!) */ +#define ETH_P_802_2 0x0004 /* 802.2 frames */ +#define ETH_P_SNAP 0x0005 /* Internal only */ +#define ETH_P_DDCMP 0x0006 /* DEC DDCMP: Internal only */ +#define ETH_P_WAN_PPP 0x0007 /* Dummy type for WAN PPP frames*/ +#define ETH_P_PPP_MP 0x0008 /* Dummy type for PPP MP frames */ +#define ETH_P_LOCALTALK 0x0009 /* Localtalk pseudo type */ +#define ETH_P_PPPTALK 0x0010 /* Dummy type for Atalk over PPP*/ +#define ETH_P_TR_802_2 0x0011 /* 802.2 frames */ +#define ETH_P_MOBITEX 0x0015 /* Mobitex (kaz@cafe.net) */ +#define ETH_P_CONTROL 0x0016 /* Card specific control frames */ +#define ETH_P_IRDA 0x0017 /* Linux-IrDA */ +#define ETH_P_ECONET 0x0018 /* Acorn Econet */ + +/* + * This is an Ethernet frame header. + */ + +struct ethhdr +{ + unsigned char h_dest[ETH_ALEN]; /* destination eth addr */ + unsigned char h_source[ETH_ALEN]; /* source ether addr */ + unsigned short h_proto; /* packet type ID field */ +}; + +struct _vlan { + unsigned short h_vlan_TCI; // Encapsulates priority and VLAN ID + unsigned short h_vlan_encapsulated_proto; +}; + + + +#define get_vlan_id(pvlan) ((ntohs((unsigned short )pvlan->h_vlan_TCI)) & 0xfff) +#define get_vlan_priority(pvlan) ((ntohs((unsigned short )pvlan->h_vlan_TCI))>>13) +#define get_vlan_encap_proto(pvlan) (ntohs((unsigned short )pvlan->h_vlan_encapsulated_proto)) + + +#endif /* _LINUX_IF_ETHER_H */ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/ip.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/ip.h new file mode 100644 index 000000000..a637d048c --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/ip.h @@ -0,0 +1,141 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _LINUX_IP_H +#define _LINUX_IP_H + +/* SOL_IP socket options */ + +#define IPTOS_TOS_MASK 0x1E +#define IPTOS_TOS(tos) ((tos)&IPTOS_TOS_MASK) +#define IPTOS_LOWDELAY 0x10 +#define IPTOS_THROUGHPUT 0x08 +#define IPTOS_RELIABILITY 0x04 +#define IPTOS_MINCOST 0x02 + +#define IPTOS_PREC_MASK 0xE0 +#define IPTOS_PREC(tos) ((tos)&IPTOS_PREC_MASK) +#define IPTOS_PREC_NETCONTROL 0xe0 +#define IPTOS_PREC_INTERNETCONTROL 0xc0 +#define IPTOS_PREC_CRITIC_ECP 0xa0 +#define IPTOS_PREC_FLASHOVERRIDE 0x80 +#define IPTOS_PREC_FLASH 0x60 +#define IPTOS_PREC_IMMEDIATE 0x40 +#define IPTOS_PREC_PRIORITY 0x20 +#define IPTOS_PREC_ROUTINE 0x00 + + +/* IP options */ +#define IPOPT_COPY 0x80 +#define IPOPT_CLASS_MASK 0x60 +#define IPOPT_NUMBER_MASK 0x1f + +#define IPOPT_COPIED(o) ((o)&IPOPT_COPY) +#define IPOPT_CLASS(o) ((o)&IPOPT_CLASS_MASK) +#define IPOPT_NUMBER(o) ((o)&IPOPT_NUMBER_MASK) + +#define IPOPT_CONTROL 0x00 +#define IPOPT_RESERVED1 0x20 +#define IPOPT_MEASUREMENT 0x40 +#define IPOPT_RESERVED2 0x60 + +#define IPOPT_END (0 |IPOPT_CONTROL) +#define IPOPT_NOOP (1 |IPOPT_CONTROL) +#define IPOPT_SEC (2 |IPOPT_CONTROL|IPOPT_COPY) +#define IPOPT_LSRR (3 |IPOPT_CONTROL|IPOPT_COPY) +#define IPOPT_TIMESTAMP (4 |IPOPT_MEASUREMENT) +#define IPOPT_RR (7 |IPOPT_CONTROL) +#define IPOPT_SID (8 |IPOPT_CONTROL|IPOPT_COPY) +#define IPOPT_SSRR (9 |IPOPT_CONTROL|IPOPT_COPY) +#define IPOPT_RA (20|IPOPT_CONTROL|IPOPT_COPY) + +#define IPVERSION 4 +#define MAXTTL 255 +#define IPDEFTTL 64 + +/* struct timestamp, struct route and MAX_ROUTES are removed. + + REASONS: it is clear that nobody used them because: + - MAX_ROUTES value was wrong. + - "struct route" was wrong. + - "struct timestamp" had fatally misaligned bitfields and was completely unusable. + */ + +#define IPOPT_OPTVAL 0 +#define IPOPT_OLEN 1 +#define IPOPT_OFFSET 2 +#define IPOPT_MINOFF 4 +#define MAX_IPOPTLEN 40 +#define IPOPT_NOP IPOPT_NOOP +#define IPOPT_EOL IPOPT_END +#define IPOPT_TS IPOPT_TIMESTAMP + +#define IPOPT_TS_TSONLY 0 /* timestamps only */ +#define IPOPT_TS_TSANDADDR 1 /* timestamps and addresses */ +#define IPOPT_TS_PRESPEC 3 /* specified modules only */ + +#ifdef PLATFORM_LINUX + +struct ip_options { + __u32 faddr; /* Saved first hop address */ + unsigned char optlen; + unsigned char srr; + unsigned char rr; + unsigned char ts; + unsigned char is_setbyuser:1, /* Set by setsockopt? */ + is_data:1, /* Options in __data, rather than skb */ + is_strictroute:1, /* Strict source route */ + srr_is_hit:1, /* Packet destination addr was our one */ + is_changed:1, /* IP checksum more not valid */ + rr_needaddr:1, /* Need to record addr of outgoing dev */ + ts_needtime:1, /* Need to record timestamp */ + ts_needaddr:1; /* Need to record addr of outgoing dev */ + unsigned char router_alert; + unsigned char __pad1; + unsigned char __pad2; + unsigned char __data[0]; +}; + +#define optlength(opt) (sizeof(struct ip_options) + opt->optlen) +#endif + +struct iphdr { +#if defined(__LITTLE_ENDIAN_BITFIELD) + __u8 ihl:4, + version:4; +#elif defined (__BIG_ENDIAN_BITFIELD) + __u8 version:4, + ihl:4; +#else +#error "Please fix " +#endif + __u8 tos; + __u16 tot_len; + __u16 id; + __u16 frag_off; + __u8 ttl; + __u8 protocol; + __u16 check; + __u32 saddr; + __u32 daddr; + /*The options start here. */ +}; + +#endif /* _LINUX_IP_H */ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/linux/wireless.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/linux/wireless.h new file mode 100644 index 000000000..d79caeb59 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/linux/wireless.h @@ -0,0 +1,97 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef _LINUX_WIRELESS_H +#define _LINUX_WIRELESS_H + +/***************************** INCLUDES *****************************/ + +#if 0 +#include /* for __u* and __s* typedefs */ +#include /* for "struct sockaddr" et al */ +#include /* for IFNAMSIZ and co... */ +#else +#define __user +//typedef uint16_t __u16; +#include /* for "struct sockaddr" et al */ +#include /* for IFNAMSIZ and co... */ +#endif + +/****************************** TYPES ******************************/ +#ifdef CONFIG_COMPAT +struct compat_iw_point { + compat_caddr_t pointer; + __u16 length; + __u16 flags; +}; +#endif +/* --------------------------- SUBTYPES --------------------------- */ +/* + * For all data larger than 16 octets, we need to use a + * pointer to memory allocated in user space. + */ +struct iw_point +{ + void __user *pointer; /* Pointer to the data (in user space) */ + __u16 length; /* number of fields or size in bytes */ + __u16 flags; /* Optional params */ +}; + + +/* ------------------------ IOCTL REQUEST ------------------------ */ +/* + * This structure defines the payload of an ioctl, and is used + * below. + * + * Note that this structure should fit on the memory footprint + * of iwreq (which is the same as ifreq), which mean a max size of + * 16 octets = 128 bits. Warning, pointers might be 64 bits wide... + * You should check this when increasing the structures defined + * above in this file... + */ +union iwreq_data +{ + /* Config - generic */ + char name[IFNAMSIZ]; + /* Name : used to verify the presence of wireless extensions. + * Name of the protocol/provider... */ + + struct iw_point data; /* Other large parameters */ +}; + +/* + * The structure to exchange data for ioctl. + * This structure is the same as 'struct ifreq', but (re)defined for + * convenience... + * Do I need to remind you about structure size (32 octets) ? + */ +struct iwreq +{ + union + { + char ifrn_name[IFNAMSIZ]; /* if name, e.g. "eth0" */ + } ifr_ifrn; + + /* Data part (defined just above) */ + union iwreq_data u; +}; + +#endif /* _LINUX_WIRELESS_H */ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/mlme_osdep.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/mlme_osdep.h new file mode 100644 index 000000000..a740a1306 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/mlme_osdep.h @@ -0,0 +1,37 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __MLME_OSDEP_H_ +#define __MLME_OSDEP_H_ + + +#if defined(PLATFORM_WINDOWS) || defined(PLATFORM_MPIXEL) +extern int time_after(u32 now, u32 old); +#endif + +extern void rtw_init_mlme_timer(_adapter *padapter); +extern void rtw_os_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_generated); +extern void rtw_os_indicate_connect( _adapter *adapter ); +void rtw_os_indicate_scan_done( _adapter *padapter, bool aborted); +extern void rtw_report_sec_ie(_adapter *adapter,u8 authmode,u8 *sec_ie); + +void rtw_reset_securitypriv( _adapter *adapter ); + +#endif //_MLME_OSDEP_H_ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/mp_custom_oid.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/mp_custom_oid.h new file mode 100644 index 000000000..9cf1c8270 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/mp_custom_oid.h @@ -0,0 +1,354 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __CUSTOM_OID_H +#define __CUSTOM_OID_H + +// by Owen +// 0xFF818000 - 0xFF81802F RTL8180 Mass Production Kit +// 0xFF818500 - 0xFF81850F RTL8185 Setup Utility +// 0xFF818580 - 0xFF81858F RTL8185 Phy Status Utility + +// + +// by Owen for Production Kit +// For Production Kit with Agilent Equipments +// in order to make our custom oids hopefully somewhat unique +// we will use 0xFF (indicating implementation specific OID) +// 81(first byte of non zero Realtek unique identifier) +// 80 (second byte of non zero Realtek unique identifier) +// XX (the custom OID number - providing 255 possible custom oids) + +#define OID_RT_PRO_RESET_DUT 0xFF818000 +#define OID_RT_PRO_SET_DATA_RATE 0xFF818001 +#define OID_RT_PRO_START_TEST 0xFF818002 +#define OID_RT_PRO_STOP_TEST 0xFF818003 +#define OID_RT_PRO_SET_PREAMBLE 0xFF818004 +#define OID_RT_PRO_SET_SCRAMBLER 0xFF818005 +#define OID_RT_PRO_SET_FILTER_BB 0xFF818006 +#define OID_RT_PRO_SET_MANUAL_DIVERSITY_BB 0xFF818007 +#define OID_RT_PRO_SET_CHANNEL_DIRECT_CALL 0xFF818008 +#define OID_RT_PRO_SET_SLEEP_MODE_DIRECT_CALL 0xFF818009 +#define OID_RT_PRO_SET_WAKE_MODE_DIRECT_CALL 0xFF81800A + +#define OID_RT_PRO_SET_TX_ANTENNA_BB 0xFF81800D +#define OID_RT_PRO_SET_ANTENNA_BB 0xFF81800E +#define OID_RT_PRO_SET_CR_SCRAMBLER 0xFF81800F +#define OID_RT_PRO_SET_CR_NEW_FILTER 0xFF818010 +#define OID_RT_PRO_SET_TX_POWER_CONTROL 0xFF818011 +#define OID_RT_PRO_SET_CR_TX_CONFIG 0xFF818012 +#define OID_RT_PRO_GET_TX_POWER_CONTROL 0xFF818013 +#define OID_RT_PRO_GET_CR_SIGNAL_QUALITY 0xFF818014 +#define OID_RT_PRO_SET_CR_SETPOINT 0xFF818015 +#define OID_RT_PRO_SET_INTEGRATOR 0xFF818016 +#define OID_RT_PRO_SET_SIGNAL_QUALITY 0xFF818017 +#define OID_RT_PRO_GET_INTEGRATOR 0xFF818018 +#define OID_RT_PRO_GET_SIGNAL_QUALITY 0xFF818019 +#define OID_RT_PRO_QUERY_EEPROM_TYPE 0xFF81801A +#define OID_RT_PRO_WRITE_MAC_ADDRESS 0xFF81801B +#define OID_RT_PRO_READ_MAC_ADDRESS 0xFF81801C +#define OID_RT_PRO_WRITE_CIS_DATA 0xFF81801D +#define OID_RT_PRO_READ_CIS_DATA 0xFF81801E +#define OID_RT_PRO_WRITE_POWER_CONTROL 0xFF81801F +#define OID_RT_PRO_READ_POWER_CONTROL 0xFF818020 +#define OID_RT_PRO_WRITE_EEPROM 0xFF818021 +#define OID_RT_PRO_READ_EEPROM 0xFF818022 +#define OID_RT_PRO_RESET_TX_PACKET_SENT 0xFF818023 +#define OID_RT_PRO_QUERY_TX_PACKET_SENT 0xFF818024 +#define OID_RT_PRO_RESET_RX_PACKET_RECEIVED 0xFF818025 +#define OID_RT_PRO_QUERY_RX_PACKET_RECEIVED 0xFF818026 +#define OID_RT_PRO_QUERY_RX_PACKET_CRC32_ERROR 0xFF818027 +#define OID_RT_PRO_QUERY_CURRENT_ADDRESS 0xFF818028 +#define OID_RT_PRO_QUERY_PERMANENT_ADDRESS 0xFF818029 +#define OID_RT_PRO_SET_PHILIPS_RF_PARAMETERS 0xFF81802A +#define OID_RT_PRO_RECEIVE_PACKET 0xFF81802C +// added by Owen on 04/08/03 for Cameo's request +#define OID_RT_PRO_WRITE_EEPROM_BYTE 0xFF81802D +#define OID_RT_PRO_READ_EEPROM_BYTE 0xFF81802E +#define OID_RT_PRO_SET_MODULATION 0xFF81802F +// + +//Sean +#define OID_RT_DRIVER_OPTION 0xFF818080 +#define OID_RT_RF_OFF 0xFF818081 +#define OID_RT_AUTH_STATUS 0xFF818082 + +//======================================================================== +#define OID_RT_PRO_SET_CONTINUOUS_TX 0xFF81800B +#define OID_RT_PRO_SET_SINGLE_CARRIER_TX 0xFF81800C +#define OID_RT_PRO_SET_CARRIER_SUPPRESSION_TX 0xFF81802B +#define OID_RT_PRO_SET_SINGLE_TONE_TX 0xFF818043 +//======================================================================== + + +// by Owen for RTL8185 Phy Status Report Utility +#define OID_RT_UTILITY_FALSE_ALARM_COUNTERS 0xFF818580 +#define OID_RT_UTILITY_SELECT_DEBUG_MODE 0xFF818581 +#define OID_RT_UTILITY_SELECT_SUBCARRIER_NUMBER 0xFF818582 +#define OID_RT_UTILITY_GET_RSSI_STATUS 0xFF818583 +#define OID_RT_UTILITY_GET_FRAME_DETECTION_STATUS 0xFF818584 +#define OID_RT_UTILITY_GET_AGC_AND_FREQUENCY_OFFSET_ESTIMATION_STATUS 0xFF818585 +#define OID_RT_UTILITY_GET_CHANNEL_ESTIMATION_STATUS 0xFF818586 +// + +// by Owen on 03/09/19-03/09/22 for RTL8185 +#define OID_RT_WIRELESS_MODE 0xFF818500 +#define OID_RT_SUPPORTED_RATES 0xFF818501 +#define OID_RT_DESIRED_RATES 0xFF818502 +#define OID_RT_WIRELESS_MODE_STARTING_ADHOC 0xFF818503 +// + +#define OID_RT_GET_CONNECT_STATE 0xFF030001 +#define OID_RT_RESCAN 0xFF030002 +#define OID_RT_SET_KEY_LENGTH 0xFF030003 +#define OID_RT_SET_DEFAULT_KEY_ID 0xFF030004 + +#define OID_RT_SET_CHANNEL 0xFF010182 +#define OID_RT_SET_SNIFFER_MODE 0xFF010183 +#define OID_RT_GET_SIGNAL_QUALITY 0xFF010184 +#define OID_RT_GET_SMALL_PACKET_CRC 0xFF010185 +#define OID_RT_GET_MIDDLE_PACKET_CRC 0xFF010186 +#define OID_RT_GET_LARGE_PACKET_CRC 0xFF010187 +#define OID_RT_GET_TX_RETRY 0xFF010188 +#define OID_RT_GET_RX_RETRY 0xFF010189 +#define OID_RT_PRO_SET_FW_DIG_STATE 0xFF01018A//S +#define OID_RT_PRO_SET_FW_RA_STATE 0xFF01018B//S + +#define OID_RT_GET_RX_TOTAL_PACKET 0xFF010190 +#define OID_RT_GET_TX_BEACON_OK 0xFF010191 +#define OID_RT_GET_TX_BEACON_ERR 0xFF010192 +#define OID_RT_GET_RX_ICV_ERR 0xFF010193 +#define OID_RT_SET_ENCRYPTION_ALGORITHM 0xFF010194 +#define OID_RT_SET_NO_AUTO_RESCAN 0xFF010195 +#define OID_RT_GET_PREAMBLE_MODE 0xFF010196 +#define OID_RT_GET_DRIVER_UP_DELTA_TIME 0xFF010197 +#define OID_RT_GET_AP_IP 0xFF010198 +#define OID_RT_GET_CHANNELPLAN 0xFF010199 +#define OID_RT_SET_PREAMBLE_MODE 0xFF01019A +#define OID_RT_SET_BCN_INTVL 0xFF01019B +#define OID_RT_GET_RF_VENDER 0xFF01019C +#define OID_RT_DEDICATE_PROBE 0xFF01019D +#define OID_RT_PRO_RX_FILTER_PATTERN 0xFF01019E + +#define OID_RT_GET_DCST_CURRENT_THRESHOLD 0xFF01019F + +#define OID_RT_GET_CCA_ERR 0xFF0101A0 +#define OID_RT_GET_CCA_UPGRADE_THRESHOLD 0xFF0101A1 +#define OID_RT_GET_CCA_FALLBACK_THRESHOLD 0xFF0101A2 + +#define OID_RT_GET_CCA_UPGRADE_EVALUATE_TIMES 0xFF0101A3 +#define OID_RT_GET_CCA_FALLBACK_EVALUATE_TIMES 0xFF0101A4 + +// by Owen on 03/31/03 for Cameo's request +#define OID_RT_SET_RATE_ADAPTIVE 0xFF0101A5 +// +#define OID_RT_GET_DCST_EVALUATE_PERIOD 0xFF0101A5 +#define OID_RT_GET_DCST_TIME_UNIT_INDEX 0xFF0101A6 +#define OID_RT_GET_TOTAL_TX_BYTES 0xFF0101A7 +#define OID_RT_GET_TOTAL_RX_BYTES 0xFF0101A8 +#define OID_RT_CURRENT_TX_POWER_LEVEL 0xFF0101A9 +#define OID_RT_GET_ENC_KEY_MISMATCH_COUNT 0xFF0101AA +#define OID_RT_GET_ENC_KEY_MATCH_COUNT 0xFF0101AB +#define OID_RT_GET_CHANNEL 0xFF0101AC + +#define OID_RT_SET_CHANNELPLAN 0xFF0101AD +#define OID_RT_GET_HARDWARE_RADIO_OFF 0xFF0101AE +#define OID_RT_CHANNELPLAN_BY_COUNTRY 0xFF0101AF +#define OID_RT_SCAN_AVAILABLE_BSSID 0xFF0101B0 +#define OID_RT_GET_HARDWARE_VERSION 0xFF0101B1 +#define OID_RT_GET_IS_ROAMING 0xFF0101B2 +#define OID_RT_GET_IS_PRIVACY 0xFF0101B3 +#define OID_RT_GET_KEY_MISMATCH 0xFF0101B4 +#define OID_RT_SET_RSSI_ROAM_TRAFFIC_TH 0xFF0101B5 +#define OID_RT_SET_RSSI_ROAM_SIGNAL_TH 0xFF0101B6 +#define OID_RT_RESET_LOG 0xFF0101B7 +#define OID_RT_GET_LOG 0xFF0101B8 +#define OID_RT_SET_INDICATE_HIDDEN_AP 0xFF0101B9 +#define OID_RT_GET_HEADER_FAIL 0xFF0101BA +#define OID_RT_SUPPORTED_WIRELESS_MODE 0xFF0101BB +#define OID_RT_GET_CHANNEL_LIST 0xFF0101BC +#define OID_RT_GET_SCAN_IN_PROGRESS 0xFF0101BD +#define OID_RT_GET_TX_INFO 0xFF0101BE +#define OID_RT_RF_READ_WRITE_OFFSET 0xFF0101BF +#define OID_RT_RF_READ_WRITE 0xFF0101C0 + +// For Netgear request. 2005.01.13, by rcnjko. +#define OID_RT_FORCED_DATA_RATE 0xFF0101C1 +#define OID_RT_WIRELESS_MODE_FOR_SCAN_LIST 0xFF0101C2 +// For Netgear request. 2005.02.17, by rcnjko. +#define OID_RT_GET_BSS_WIRELESS_MODE 0xFF0101C3 +// For AZ project. 2005.06.27, by rcnjko. +#define OID_RT_SCAN_WITH_MAGIC_PACKET 0xFF0101C4 + +// Vincent 8185MP +#define OID_RT_PRO_RX_FILTER 0xFF0111C0 + +//Andy TEST +//#define OID_RT_PRO_WRITE_REGISTRY 0xFF0111C1 +//#define OID_RT_PRO_READ_REGISTRY 0xFF0111C2 +#define OID_CE_USB_WRITE_REGISTRY 0xFF0111C1 +#define OID_CE_USB_READ_REGISTRY 0xFF0111C2 + + +#define OID_RT_PRO_SET_INITIAL_GAIN 0xFF0111C3 +#define OID_RT_PRO_SET_BB_RF_STANDBY_MODE 0xFF0111C4 +#define OID_RT_PRO_SET_BB_RF_SHUTDOWN_MODE 0xFF0111C5 +#define OID_RT_PRO_SET_TX_CHARGE_PUMP 0xFF0111C6 +#define OID_RT_PRO_SET_RX_CHARGE_PUMP 0xFF0111C7 +#define OID_RT_PRO_RF_WRITE_REGISTRY 0xFF0111C8 +#define OID_RT_PRO_RF_READ_REGISTRY 0xFF0111C9 +#define OID_RT_PRO_QUERY_RF_TYPE 0xFF0111CA + +// AP OID +#define OID_RT_AP_GET_ASSOCIATED_STATION_LIST 0xFF010300 +#define OID_RT_AP_GET_CURRENT_TIME_STAMP 0xFF010301 +#define OID_RT_AP_SWITCH_INTO_AP_MODE 0xFF010302 +#define OID_RT_AP_SET_DTIM_PERIOD 0xFF010303 +#define OID_RT_AP_SUPPORTED 0xFF010304 // Determine if driver supports AP mode. 2004.08.27, by rcnjko. +#define OID_RT_AP_SET_PASSPHRASE 0xFF010305 // Set WPA-PSK passphrase into authenticator. 2005.07.08, byrcnjko. + +// 8187MP. 2004.09.06, by rcnjko. +#define OID_RT_PRO8187_WI_POLL 0xFF818780 +#define OID_RT_PRO_WRITE_BB_REG 0xFF818781 +#define OID_RT_PRO_READ_BB_REG 0xFF818782 +#define OID_RT_PRO_WRITE_RF_REG 0xFF818783 +#define OID_RT_PRO_READ_RF_REG 0xFF818784 + +// Meeting House. added by Annie, 2005-07-20. +#define OID_RT_MH_VENDER_ID 0xFFEDC100 + +//8711 MP OID added 20051230. +#define OID_RT_PRO8711_JOIN_BSS 0xFF871100//S + +#define OID_RT_PRO_READ_REGISTER 0xFF871101 //Q +#define OID_RT_PRO_WRITE_REGISTER 0xFF871102 //S + +#define OID_RT_PRO_BURST_READ_REGISTER 0xFF871103 //Q +#define OID_RT_PRO_BURST_WRITE_REGISTER 0xFF871104 //S + +#define OID_RT_PRO_WRITE_TXCMD 0xFF871105 //S + +#define OID_RT_PRO_READ16_EEPROM 0xFF871106 //Q +#define OID_RT_PRO_WRITE16_EEPROM 0xFF871107 //S + +#define OID_RT_PRO_H2C_SET_COMMAND 0xFF871108 //S +#define OID_RT_PRO_H2C_QUERY_RESULT 0xFF871109 //Q + +#define OID_RT_PRO8711_WI_POLL 0xFF87110A //Q +#define OID_RT_PRO8711_PKT_LOSS 0xFF87110B //Q +#define OID_RT_RD_ATTRIB_MEM 0xFF87110C//Q +#define OID_RT_WR_ATTRIB_MEM 0xFF87110D//S + + +//Method 2 for H2C/C2H +#define OID_RT_PRO_H2C_CMD_MODE 0xFF871110 //S +#define OID_RT_PRO_H2C_CMD_RSP_MODE 0xFF871111 //Q +#define OID_RT_PRO_H2C_CMD_EVENT_MODE 0xFF871112 //S +#define OID_RT_PRO_WAIT_C2H_EVENT 0xFF871113 //Q +#define OID_RT_PRO_RW_ACCESS_PROTOCOL_TEST 0xFF871114//Q + +#define OID_RT_PRO_SCSI_ACCESS_TEST 0xFF871115 //Q, S + +#define OID_RT_PRO_SCSI_TCPIPOFFLOAD_OUT 0xFF871116 //S +#define OID_RT_PRO_SCSI_TCPIPOFFLOAD_IN 0xFF871117 //Q,S +#define OID_RT_RRO_RX_PKT_VIA_IOCTRL 0xFF871118 //Q +#define OID_RT_RRO_RX_PKTARRAY_VIA_IOCTRL 0xFF871119 //Q + +#define OID_RT_RPO_SET_PWRMGT_TEST 0xFF87111A //S +#define OID_RT_PRO_QRY_PWRMGT_TEST 0XFF87111B //Q +#define OID_RT_RPO_ASYNC_RWIO_TEST 0xFF87111C //S +#define OID_RT_RPO_ASYNC_RWIO_POLL 0xFF87111D //Q +#define OID_RT_PRO_SET_RF_INTFS 0xFF87111E //S +#define OID_RT_POLL_RX_STATUS 0xFF87111F //Q + +#define OID_RT_PRO_CFG_DEBUG_MESSAGE 0xFF871120 //Q,S +#define OID_RT_PRO_SET_DATA_RATE_EX 0xFF871121//S +#define OID_RT_PRO_SET_BASIC_RATE 0xFF871122//S +#define OID_RT_PRO_READ_TSSI 0xFF871123//S +#define OID_RT_PRO_SET_POWER_TRACKING 0xFF871124//S + + +#define OID_RT_PRO_QRY_PWRSTATE 0xFF871150 //Q +#define OID_RT_PRO_SET_PWRSTATE 0xFF871151 //S + +//Method 2 , using workitem +#define OID_RT_SET_READ_REG 0xFF871181 //S +#define OID_RT_SET_WRITE_REG 0xFF871182 //S +#define OID_RT_SET_BURST_READ_REG 0xFF871183 //S +#define OID_RT_SET_BURST_WRITE_REG 0xFF871184 //S +#define OID_RT_SET_WRITE_TXCMD 0xFF871185 //S +#define OID_RT_SET_READ16_EEPROM 0xFF871186 //S +#define OID_RT_SET_WRITE16_EEPROM 0xFF871187 //S +#define OID_RT_QRY_POLL_WKITEM 0xFF871188 //Q + +//For SDIO INTERFACE only +#define OID_RT_PRO_SYNCPAGERW_SRAM 0xFF8711A0 //Q, S +#define OID_RT_PRO_871X_DRV_EXT 0xFF8711A1 + +//For USB INTERFACE only +#define OID_RT_PRO_USB_VENDOR_REQ 0xFF8711B0 //Q, S +#define OID_RT_PRO_SCSI_AUTO_TEST 0xFF8711B1 //S +#define OID_RT_PRO_USB_MAC_AC_FIFO_WRITE 0xFF8711B2 //S +#define OID_RT_PRO_USB_MAC_RX_FIFO_READ 0xFF8711B3 //Q +#define OID_RT_PRO_USB_MAC_RX_FIFO_POLLING 0xFF8711B4 //Q + +#define OID_RT_PRO_H2C_SET_RATE_TABLE 0xFF8711FB //S +#define OID_RT_PRO_H2C_GET_RATE_TABLE 0xFF8711FC //S +#define OID_RT_PRO_H2C_C2H_LBK_TEST 0xFF8711FE + +#define OID_RT_PRO_ENCRYPTION_CTRL 0xFF871200 //Q, S +#define OID_RT_PRO_ADD_STA_INFO 0xFF871201 //S +#define OID_RT_PRO_DELE_STA_INFO 0xFF871202 //S +#define OID_RT_PRO_QUERY_DR_VARIABLE 0xFF871203 //Q + +#define OID_RT_PRO_RX_PACKET_TYPE 0xFF871204 //Q, S + +#define OID_RT_PRO_READ_EFUSE 0xFF871205 //Q +#define OID_RT_PRO_WRITE_EFUSE 0xFF871206 //S +#define OID_RT_PRO_RW_EFUSE_PGPKT 0xFF871207 //Q, S +#define OID_RT_GET_EFUSE_CURRENT_SIZE 0xFF871208 //Q + +#define OID_RT_SET_BANDWIDTH 0xFF871209 //S +#define OID_RT_SET_CRYSTAL_CAP 0xFF87120A //S + +#define OID_RT_SET_RX_PACKET_TYPE 0xFF87120B //S + +#define OID_RT_GET_EFUSE_MAX_SIZE 0xFF87120C //Q + +#define OID_RT_PRO_SET_TX_AGC_OFFSET 0xFF87120D //S + +#define OID_RT_PRO_SET_PKT_TEST_MODE 0xFF87120E //S + +#define OID_RT_PRO_FOR_EVM_TEST_SETTING 0xFF87120F //S + +#define OID_RT_PRO_GET_THERMAL_METER 0xFF871210 //Q + +#define OID_RT_RESET_PHY_RX_PACKET_COUNT 0xFF871211 //S +#define OID_RT_GET_PHY_RX_PACKET_RECEIVED 0xFF871212 //Q +#define OID_RT_GET_PHY_RX_PACKET_CRC32_ERROR 0xFF871213 //Q + +#define OID_RT_SET_POWER_DOWN 0xFF871214 //S + +#define OID_RT_GET_POWER_MODE 0xFF871215 //Q + +#define OID_RT_PRO_EFUSE 0xFF871216 //Q, S +#define OID_RT_PRO_EFUSE_MAP 0xFF871217 //Q, S + +#endif //#ifndef __CUSTOM_OID_H + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/nic_spec.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/nic_spec.h new file mode 100644 index 000000000..18e7b2c09 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/nic_spec.h @@ -0,0 +1,47 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef __NIC_SPEC_H__ +#define __NIC_SPEC_H__ + +#include + +#define RTL8711_MCTRL_ (0x20000) +#define RTL8711_UART_ (0x30000) +#define RTL8711_TIMER_ (0x40000) +#define RTL8711_FINT_ (0x50000) +#define RTL8711_HINT_ (0x50000) +#define RTL8711_GPIO_ (0x60000) +#define RTL8711_WLANCTRL_ (0x200000) +#define RTL8711_WLANFF_ (0xe00000) +#define RTL8711_HCICTRL_ (0x600000) +#define RTL8711_SYSCFG_ (0x620000) +#define RTL8711_SYSCTRL_ (0x620000) +#define RTL8711_MCCTRL_ (0x020000) + + +#include + +#include + + +#endif // __RTL8711_SPEC_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/osdep_intf.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/osdep_intf.h new file mode 100644 index 000000000..761fb17d4 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/osdep_intf.h @@ -0,0 +1,170 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __OSDEP_INTF_H_ +#define __OSDEP_INTF_H_ + + +struct intf_priv { + + u8 *intf_dev; + u32 max_iosz; //USB2.0: 128, USB1.1: 64, SDIO:64 + u32 max_xmitsz; //USB2.0: unlimited, SDIO:512 + u32 max_recvsz; //USB2.0: unlimited, SDIO:512 + + volatile u8 *io_rwmem; + volatile u8 *allocated_io_rwmem; + u32 io_wsz; //unit: 4bytes + u32 io_rsz;//unit: 4bytes + u8 intf_status; + + void (*_bus_io)(u8 *priv); + +/* +Under Sync. IRP (SDIO/USB) +A protection mechanism is necessary for the io_rwmem(read/write protocol) + +Under Async. IRP (SDIO/USB) +The protection mechanism is through the pending queue. +*/ + + _mutex ioctl_mutex; + + +#ifdef PLATFORM_LINUX + #ifdef CONFIG_USB_HCI + // when in USB, IO is through interrupt in/out endpoints + struct usb_device *udev; + PURB piorw_urb; + u8 io_irp_cnt; + u8 bio_irp_pending; + _sema io_retevt; + _timer io_timer; + u8 bio_irp_timeout; + u8 bio_timer_cancel; + #endif +#endif + +#ifdef PLATFORM_OS_XP + #ifdef CONFIG_SDIO_HCI + // below is for io_rwmem... + PMDL pmdl; + PSDBUS_REQUEST_PACKET sdrp; + PSDBUS_REQUEST_PACKET recv_sdrp; + PSDBUS_REQUEST_PACKET xmit_sdrp; + + PIRP piorw_irp; + + #endif + #ifdef CONFIG_USB_HCI + PURB piorw_urb; + PIRP piorw_irp; + u8 io_irp_cnt; + u8 bio_irp_pending; + _sema io_retevt; + #endif +#endif + +}; + + +#ifdef CONFIG_R871X_TEST +int rtw_start_pseudo_adhoc(_adapter *padapter); +int rtw_stop_pseudo_adhoc(_adapter *padapter); +#endif + +struct dvobj_priv *devobj_init(void); +void devobj_deinit(struct dvobj_priv *pdvobj); + +u8 rtw_init_drv_sw(_adapter *padapter); +u8 rtw_free_drv_sw(_adapter *padapter); +u8 rtw_reset_drv_sw(_adapter *padapter); +void rtw_dev_unload(PADAPTER padapter); + +u32 rtw_start_drv_threads(_adapter *padapter); +void rtw_stop_drv_threads (_adapter *padapter); +void rtw_cancel_all_timer(_adapter *padapter); + +uint loadparam(_adapter *adapter); + +#ifdef PLATFORM_LINUX +int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); + +int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname); +struct net_device *rtw_init_netdev(_adapter *padapter); + +void rtw_os_ndev_free(_adapter *adapter); +int rtw_os_ndev_init(_adapter *adapter, char *name); +void rtw_os_ndev_deinit(_adapter *adapter); +void rtw_os_ndevs_unregister(struct dvobj_priv *dvobj); +int rtw_os_ndevs_init(struct dvobj_priv *dvobj); +void rtw_os_ndevs_deinit(struct dvobj_priv *dvobj); + +#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) +u16 rtw_recv_select_queue(struct sk_buff *skb); +#endif //LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35) + +int rtw_ndev_notifier_register(void); +void rtw_ndev_notifier_unregister(void); + +#include "../os_dep/linux/rtw_proc.h" + +#ifdef CONFIG_IOCTL_CFG80211 +#include "../os_dep/linux/ioctl_cfg80211.h" +#endif //CONFIG_IOCTL_CFG80211 + +#endif //PLATFORM_LINUX + + +#ifdef PLATFORM_FREEBSD +extern int rtw_ioctl(struct ifnet * ifp, u_long cmd, caddr_t data); +#endif + +void rtw_ips_dev_unload(_adapter *padapter); + +#ifdef CONFIG_IPS +int rtw_ips_pwr_up(_adapter *padapter); +void rtw_ips_pwr_down(_adapter *padapter); +#endif + +#ifdef CONFIG_CONCURRENT_MODE +struct _io_ops; +_adapter *rtw_drv_if2_init(_adapter *primary_padapter, void (*set_intf_ops)(_adapter *primary_padapter,struct _io_ops *pops)); +void rtw_drv_if2_free(_adapter *if2); +void rtw_drv_if2_stop(_adapter *if2); +#ifdef CONFIG_MULTI_VIR_IFACES +struct dvobj_priv; +_adapter *rtw_drv_add_vir_if(_adapter *primary_padapter, void (*set_intf_ops)(_adapter *primary_padapter,struct _io_ops *pops)); +void rtw_drv_stop_vir_ifaces(struct dvobj_priv *dvobj); +void rtw_drv_free_vir_ifaces(struct dvobj_priv *dvobj); +#endif //CONFIG_MULTI_VIR_IFACES +#endif + +void rtw_ndev_destructor(_nic_hdl ndev); + +#ifdef CONFIG_ARP_KEEP_ALIVE +int rtw_gw_addr_query(_adapter *padapter); +#endif + +int rtw_suspend_common(_adapter *padapter); +int rtw_resume_common(_adapter *padapter); + +#endif //_OSDEP_INTF_H_ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/osdep_service.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/osdep_service.h new file mode 100644 index 000000000..e601e80a7 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/osdep_service.h @@ -0,0 +1,637 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __OSDEP_SERVICE_H_ +#define __OSDEP_SERVICE_H_ + +#include +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0) +#include +#endif + +#define _FAIL 0 +#define _SUCCESS 1 +#define RTW_RX_HANDLED 2 +//#define RTW_STATUS_TIMEDOUT -110 + +#undef _TRUE +#define _TRUE 1 + +#undef _FALSE +#define _FALSE 0 + + +#ifdef PLATFORM_FREEBSD +#include +#endif + +#ifdef PLATFORM_LINUX +#include +#endif + +#ifdef PLATFORM_OS_XP +#include +#endif + +#ifdef PLATFORM_OS_CE +#include +#endif + +#define RTW_TIMER_HDL_NAME(name) rtw_##name##_timer_hdl +#define RTW_DECLARE_TIMER_HDL(name) void RTW_TIMER_HDL_NAME(name)(RTW_TIMER_HDL_ARGS) + +//#include + +#ifndef BIT + #define BIT(x) ( 1 << (x)) +#endif + +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 +#define BIT32 0x0100000000 +#define BIT33 0x0200000000 +#define BIT34 0x0400000000 +#define BIT35 0x0800000000 +#define BIT36 0x1000000000 + +extern int RTW_STATUS_CODE(int error_code); + +#ifndef RTK_DMP_PLATFORM +#define CONFIG_USE_VMALLOC +#endif + +/* flags used for rtw_mstat_update() */ +enum mstat_f { + /* type: 0x00ff */ + MSTAT_TYPE_VIR = 0x00, + MSTAT_TYPE_PHY= 0x01, + MSTAT_TYPE_SKB = 0x02, + MSTAT_TYPE_USB = 0x03, + MSTAT_TYPE_MAX = 0x04, + + /* func: 0xff00 */ + MSTAT_FUNC_UNSPECIFIED = 0x00<<8, + MSTAT_FUNC_IO = 0x01<<8, + MSTAT_FUNC_TX_IO = 0x02<<8, + MSTAT_FUNC_RX_IO = 0x03<<8, + MSTAT_FUNC_TX = 0x04<<8, + MSTAT_FUNC_RX = 0x05<<8, + MSTAT_FUNC_CFG_VENDOR = 0x06<<8, + MSTAT_FUNC_MAX = 0x07<<8, +}; + +#define mstat_tf_idx(flags) ((flags)&0xff) +#define mstat_ff_idx(flags) (((flags)&0xff00) >> 8) + +typedef enum mstat_status{ + MSTAT_ALLOC_SUCCESS = 0, + MSTAT_ALLOC_FAIL, + MSTAT_FREE +} MSTAT_STATUS; + +#ifdef DBG_MEM_ALLOC +void rtw_mstat_update(const enum mstat_f flags, const MSTAT_STATUS status, u32 sz); +void rtw_mstat_dump (void *sel); +u8* dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line); +u8* dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line); +void dbg_rtw_vmfree(u8 *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line); +u8* dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line); +u8* dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line); +void dbg_rtw_mfree(u8 *pbuf, const enum mstat_f flags, u32 sz, const char *func, const int line); + +struct sk_buff * dbg_rtw_skb_alloc(unsigned int size, const enum mstat_f flags, const char *func, const int line); +void dbg_rtw_skb_free(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line); +struct sk_buff *dbg_rtw_skb_copy(const struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line); +struct sk_buff *dbg_rtw_skb_clone(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line); +int dbg_rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line); +void dbg_rtw_skb_queue_purge(struct sk_buff_head *list, enum mstat_f flags, const char *func, int line); +#ifdef CONFIG_USB_HCI +void *dbg_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma, const enum mstat_f flags, const char *func, const int line); +void dbg_rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma, const enum mstat_f flags, const char *func, const int line); +#endif /* CONFIG_USB_HCI */ + +#ifdef CONFIG_USE_VMALLOC +#define rtw_vmalloc(sz) dbg_rtw_vmalloc((sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) +#define rtw_zvmalloc(sz) dbg_rtw_zvmalloc((sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) +#define rtw_vmfree(pbuf, sz) dbg_rtw_vmfree((pbuf), (sz), MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) +#define rtw_vmalloc_f(sz, mstat_f) dbg_rtw_vmalloc((sz), ((mstat_f)&0xff00)|MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) +#define rtw_zvmalloc_f(sz, mstat_f) dbg_rtw_zvmalloc((sz), ((mstat_f)&0xff00)|MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) +#define rtw_vmfree_f(pbuf, sz, mstat_f) dbg_rtw_vmfree((pbuf), (sz), ((mstat_f)&0xff00)|MSTAT_TYPE_VIR, __FUNCTION__, __LINE__) +#else /* CONFIG_USE_VMALLOC */ +#define rtw_vmalloc(sz) dbg_rtw_malloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_zvmalloc(sz) dbg_rtw_zmalloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_vmfree(pbuf, sz) dbg_rtw_mfree((pbuf), (sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_vmalloc_f(sz, mstat_f) dbg_rtw_malloc((sz), ((mstat_f)&0xff00)|MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_zvmalloc_f(sz, mstat_f) dbg_rtw_zmalloc((sz), ((mstat_f)&0xff00)|MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_vmfree_f(pbuf, sz, mstat_f) dbg_rtw_mfree((pbuf), (sz), ((mstat_f)&0xff00)|MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#endif /* CONFIG_USE_VMALLOC */ +#define rtw_malloc(sz) dbg_rtw_malloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_zmalloc(sz) dbg_rtw_zmalloc((sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_mfree(pbuf, sz) dbg_rtw_mfree((pbuf), (sz), MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_malloc_f(sz, mstat_f) dbg_rtw_malloc((sz), ((mstat_f)&0xff00)|MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_zmalloc_f(sz, mstat_f) dbg_rtw_zmalloc((sz), ((mstat_f)&0xff00)|MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) +#define rtw_mfree_f(pbuf, sz, mstat_f) dbg_rtw_mfree((pbuf), (sz), ((mstat_f)&0xff00)|MSTAT_TYPE_PHY, __FUNCTION__, __LINE__) + +#define rtw_skb_alloc(size) dbg_rtw_skb_alloc((size), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_free(skb) dbg_rtw_skb_free((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_alloc_f(size, mstat_f) dbg_rtw_skb_alloc((size), ((mstat_f)&0xff00)|MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_free_f(skb, mstat_f) dbg_rtw_skb_free((skb), ((mstat_f)&0xff00)|MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_copy(skb) dbg_rtw_skb_copy((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_clone(skb) dbg_rtw_skb_clone((skb), MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_copy_f(skb, mstat_f) dbg_rtw_skb_copy((skb), ((mstat_f)&0xff00)|MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_clone_f(skb, mstat_f) dbg_rtw_skb_clone((skb), ((mstat_f)&0xff00)|MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_netif_rx(ndev, skb) dbg_rtw_netif_rx(ndev, skb, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#define rtw_skb_queue_purge(sk_buff_head) dbg_rtw_skb_queue_purge(sk_buff_head, MSTAT_TYPE_SKB, __FUNCTION__, __LINE__) +#ifdef CONFIG_USB_HCI +#define rtw_usb_buffer_alloc(dev, size, dma) dbg_rtw_usb_buffer_alloc((dev), (size), (dma), MSTAT_TYPE_USB, __FUNCTION__, __LINE__) +#define rtw_usb_buffer_free(dev, size, addr, dma) dbg_rtw_usb_buffer_free((dev), (size), (addr), (dma), MSTAT_TYPE_USB, __FUNCTION__, __LINE__) +#define rtw_usb_buffer_alloc_f(dev, size, dma, mstat_f) dbg_rtw_usb_buffer_alloc((dev), (size), (dma), ((mstat_f)&0xff00)|MSTAT_TYPE_USB, __FUNCTION__, __LINE__) +#define rtw_usb_buffer_free_f(dev, size, addr, dma, mstat_f) dbg_rtw_usb_buffer_free((dev), (size), (addr), (dma), ((mstat_f)&0xff00)|MSTAT_TYPE_USB, __FUNCTION__, __LINE__) +#endif /* CONFIG_USB_HCI */ + +#else /* DBG_MEM_ALLOC */ +#define rtw_mstat_update(flag, status, sz) do {} while(0) +#define rtw_mstat_dump(sel) do {} while(0) +u8* _rtw_vmalloc(u32 sz); +u8* _rtw_zvmalloc(u32 sz); +void _rtw_vmfree(u8 *pbuf, u32 sz); +u8* _rtw_zmalloc(u32 sz); +u8* _rtw_malloc(u32 sz); +void _rtw_mfree(u8 *pbuf, u32 sz); + +struct sk_buff *_rtw_skb_alloc(u32 sz); +void _rtw_skb_free(struct sk_buff *skb); +struct sk_buff *_rtw_skb_copy(const struct sk_buff *skb); +struct sk_buff *_rtw_skb_clone(struct sk_buff *skb); +int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb); +void _rtw_skb_queue_purge(struct sk_buff_head *list); + +#ifdef CONFIG_USB_HCI +void *_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma); +void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma); +#endif /* CONFIG_USB_HCI */ + +#ifdef CONFIG_USE_VMALLOC +#define rtw_vmalloc(sz) _rtw_vmalloc((sz)) +#define rtw_zvmalloc(sz) _rtw_zvmalloc((sz)) +#define rtw_vmfree(pbuf, sz) _rtw_vmfree((pbuf), (sz)) +#define rtw_vmalloc_f(sz, mstat_f) _rtw_vmalloc((sz)) +#define rtw_zvmalloc_f(sz, mstat_f) _rtw_zvmalloc((sz)) +#define rtw_vmfree_f(pbuf, sz, mstat_f) _rtw_vmfree((pbuf), (sz)) +#else /* CONFIG_USE_VMALLOC */ +#define rtw_vmalloc(sz) _rtw_malloc((sz)) +#define rtw_zvmalloc(sz) _rtw_zmalloc((sz)) +#define rtw_vmfree(pbuf, sz) _rtw_mfree((pbuf), (sz)) +#define rtw_vmalloc_f(sz, mstat_f) _rtw_malloc((sz)) +#define rtw_zvmalloc_f(sz, mstat_f) _rtw_zmalloc((sz)) +#define rtw_vmfree_f(pbuf, sz, mstat_f) _rtw_mfree((pbuf), (sz)) +#endif /* CONFIG_USE_VMALLOC */ +#define rtw_malloc(sz) _rtw_malloc((sz)) +#define rtw_zmalloc(sz) _rtw_zmalloc((sz)) +#define rtw_mfree(pbuf, sz) _rtw_mfree((pbuf), (sz)) +#define rtw_malloc_f(sz, mstat_f) _rtw_malloc((sz)) +#define rtw_zmalloc_f(sz, mstat_f) _rtw_zmalloc((sz)) +#define rtw_mfree_f(pbuf, sz, mstat_f) _rtw_mfree((pbuf), (sz)) + +#define rtw_skb_alloc(size) _rtw_skb_alloc((size)) +#define rtw_skb_free(skb) _rtw_skb_free((skb)) +#define rtw_skb_alloc_f(size, mstat_f) _rtw_skb_alloc((size)) +#define rtw_skb_free_f(skb, mstat_f) _rtw_skb_free((skb)) +#define rtw_skb_copy(skb) _rtw_skb_copy((skb)) +#define rtw_skb_clone(skb) _rtw_skb_clone((skb)) +#define rtw_skb_copy_f(skb, mstat_f) _rtw_skb_copy((skb)) +#define rtw_skb_clone_f(skb, mstat_f) _rtw_skb_clone((skb)) +#define rtw_netif_rx(ndev, skb) _rtw_netif_rx(ndev, skb) +#define rtw_skb_queue_purge(sk_buff_head) _rtw_skb_queue_purge(sk_buff_head) +#ifdef CONFIG_USB_HCI +#define rtw_usb_buffer_alloc(dev, size, dma) _rtw_usb_buffer_alloc((dev), (size), (dma)) +#define rtw_usb_buffer_free(dev, size, addr, dma) _rtw_usb_buffer_free((dev), (size), (addr), (dma)) +#define rtw_usb_buffer_alloc_f(dev, size, dma, mstat_f) _rtw_usb_buffer_alloc((dev), (size), (dma)) +#define rtw_usb_buffer_free_f(dev, size, addr, dma, mstat_f) _rtw_usb_buffer_free((dev), (size), (addr), (dma)) +#endif /* CONFIG_USB_HCI */ +#endif /* DBG_MEM_ALLOC */ + +extern void* rtw_malloc2d(int h, int w, size_t size); +extern void rtw_mfree2d(void *pbuf, int h, int w, int size); + +extern void _rtw_memcpy(void *dec, const void *sour, u32 sz); +extern void _rtw_memmove(void *dst, const void *src, u32 sz); +extern int _rtw_memcmp(const void *dst, const void *src, u32 sz); +extern void _rtw_memset(void *pbuf, int c, u32 sz); + +extern void _rtw_init_listhead(_list *list); +extern u32 rtw_is_list_empty(_list *phead); +extern void rtw_list_insert_head(_list *plist, _list *phead); +extern void rtw_list_insert_tail(_list *plist, _list *phead); +#ifndef PLATFORM_FREEBSD +extern void rtw_list_delete(_list *plist); +#endif //PLATFORM_FREEBSD + +extern void _rtw_init_sema(_sema *sema, int init_val); +extern void _rtw_free_sema(_sema *sema); +extern void _rtw_up_sema(_sema *sema); +extern u32 _rtw_down_sema(_sema *sema); +extern void _rtw_mutex_init(_mutex *pmutex); +extern void _rtw_mutex_free(_mutex *pmutex); +#ifndef PLATFORM_FREEBSD +extern void _rtw_spinlock_init(_lock *plock); +#endif //PLATFORM_FREEBSD +extern void _rtw_spinlock_free(_lock *plock); +extern void _rtw_spinlock(_lock *plock); +extern void _rtw_spinunlock(_lock *plock); +extern void _rtw_spinlock_ex(_lock *plock); +extern void _rtw_spinunlock_ex(_lock *plock); + +extern void _rtw_init_queue(_queue *pqueue); +extern void _rtw_deinit_queue(_queue *pqueue); +extern u32 _rtw_queue_empty(_queue *pqueue); +extern u32 rtw_end_of_queue_search(_list *queue, _list *pelement); + +extern u32 rtw_get_current_time(void); +extern u32 rtw_systime_to_ms(u32 systime); +extern u32 rtw_ms_to_systime(u32 ms); +extern s32 rtw_get_passing_time_ms(u32 start); +extern s32 rtw_get_time_interval_ms(u32 start, u32 end); + +extern void rtw_sleep_schedulable(int ms); + +extern void rtw_msleep_os(int ms); +extern void rtw_usleep_os(int us); + +extern u32 rtw_atoi(u8* s); + +#ifdef DBG_DELAY_OS +#define rtw_mdelay_os(ms) _rtw_mdelay_os((ms), __FUNCTION__, __LINE__) +#define rtw_udelay_os(ms) _rtw_udelay_os((ms), __FUNCTION__, __LINE__) +extern void _rtw_mdelay_os(int ms, const char *func, const int line); +extern void _rtw_udelay_os(int us, const char *func, const int line); +#else +extern void rtw_mdelay_os(int ms); +extern void rtw_udelay_os(int us); +#endif + +extern void rtw_yield_os(void); + + +extern void rtw_init_timer(_timer *ptimer, void *padapter, void *pfunc); + + +__inline static unsigned char _cancel_timer_ex(_timer *ptimer) +{ +#ifdef PLATFORM_LINUX +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) + return del_timer_sync(&ptimer->t); +#else + return del_timer_sync(ptimer); +#endif +#endif +#ifdef PLATFORM_FREEBSD + _cancel_timer(ptimer,0); + return 0; +#endif +#ifdef PLATFORM_WINDOWS + u8 bcancelled; + + _cancel_timer(ptimer, &bcancelled); + + return bcancelled; +#endif +} + +static __inline void thread_enter(char *name) +{ +#ifdef PLATFORM_LINUX + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)) + daemonize("%s", name); + #endif + allow_signal(SIGTERM); +#endif +#ifdef PLATFORM_FREEBSD + printf("%s", "RTKTHREAD_enter"); +#endif +} + +__inline static void flush_signals_thread(void) +{ +#ifdef PLATFORM_LINUX + if (signal_pending (current)) + { + flush_signals(current); + } +#endif +} + +__inline static _OS_STATUS res_to_status(sint res) +{ + +#if defined (PLATFORM_LINUX) || defined (PLATFORM_MPIXEL) || defined (PLATFORM_FREEBSD) + return res; +#endif + +#ifdef PLATFORM_WINDOWS + + if (res == _SUCCESS) + return NDIS_STATUS_SUCCESS; + else + return NDIS_STATUS_FAILURE; + +#endif + +} + +__inline static void rtw_dump_stack(void) +{ +#ifdef PLATFORM_LINUX + dump_stack(); +#endif +} + +#ifdef PLATFORM_LINUX +#define rtw_warn_on(condition) WARN_ON(condition) +#else +#define rtw_warn_on(condition) do {} while (0) +#endif + +__inline static int rtw_bug_check(void *parg1, void *parg2, void *parg3, void *parg4) +{ + int ret = _TRUE; + +#ifdef PLATFORM_WINDOWS + if ( ((uint)parg1) <= 0x7fffffff || + ((uint)parg2) <= 0x7fffffff || + ((uint)parg3) <= 0x7fffffff || + ((uint)parg4) <= 0x7fffffff) + { + ret = _FALSE; + KeBugCheckEx(0x87110000, (ULONG_PTR)parg1, (ULONG_PTR)parg2, (ULONG_PTR)parg3, (ULONG_PTR)parg4); + } +#endif + + return ret; + +} + +#define _RND(sz, r) ((((sz)+((r)-1))/(r))*(r)) +#define RND4(x) (((x >> 2) + (((x & 3) == 0) ? 0: 1)) << 2) + +__inline static u32 _RND4(u32 sz) +{ + + u32 val; + + val = ((sz >> 2) + ((sz & 3) ? 1: 0)) << 2; + + return val; + +} + +__inline static u32 _RND8(u32 sz) +{ + + u32 val; + + val = ((sz >> 3) + ((sz & 7) ? 1: 0)) << 3; + + return val; + +} + +__inline static u32 _RND128(u32 sz) +{ + + u32 val; + + val = ((sz >> 7) + ((sz & 127) ? 1: 0)) << 7; + + return val; + +} + +__inline static u32 _RND256(u32 sz) +{ + + u32 val; + + val = ((sz >> 8) + ((sz & 255) ? 1: 0)) << 8; + + return val; + +} + +__inline static u32 _RND512(u32 sz) +{ + + u32 val; + + val = ((sz >> 9) + ((sz & 511) ? 1: 0)) << 9; + + return val; + +} + +__inline static u32 bitshift(u32 bitmask) +{ + u32 i; + + for (i = 0; i <= 31; i++) + if (((bitmask>>i) & 0x1) == 1) break; + + return i; +} + +#define rtw_min(a, b) ((a>b)?b:a) +#define rtw_is_range_a_in_b(hi_a, lo_a, hi_b, lo_b) (((hi_a) <= (hi_b)) && ((lo_a) >= (lo_b))) +#define rtw_is_range_overlap(hi_a, lo_a, hi_b, lo_b) (((hi_a) > (lo_b)) && ((lo_a) < (hi_b))) + +#ifndef MAC_FMT +#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" +#endif +#ifndef MAC_ARG +#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5] +#endif + + +extern void rtw_suspend_lock_init(void); +extern void rtw_suspend_lock_uninit(void); +extern void rtw_lock_suspend(void); +extern void rtw_unlock_suspend(void); +extern void rtw_lock_suspend_timeout(u32 timeout_ms); +extern void rtw_lock_ext_suspend_timeout(u32 timeout_ms); +extern void rtw_lock_rx_suspend_timeout(u32 timeout_ms); +extern void rtw_lock_traffic_suspend_timeout(u32 timeout_ms); +extern void rtw_lock_resume_scan_timeout(u32 timeout_ms); +extern void rtw_resume_lock_suspend(void); +extern void rtw_resume_unlock_suspend(void); + +extern void ATOMIC_SET(ATOMIC_T *v, int i); +extern int ATOMIC_READ(ATOMIC_T *v); +extern void ATOMIC_ADD(ATOMIC_T *v, int i); +extern void ATOMIC_SUB(ATOMIC_T *v, int i); +extern void ATOMIC_INC(ATOMIC_T *v); +extern void ATOMIC_DEC(ATOMIC_T *v); +extern int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i); +extern int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i); +extern int ATOMIC_INC_RETURN(ATOMIC_T *v); +extern int ATOMIC_DEC_RETURN(ATOMIC_T *v); + +//File operation APIs, just for linux now +extern int rtw_is_file_readable(char *path); +extern int rtw_retrieve_from_file(char *path, u8 *buf, u32 sz); +extern int rtw_store_to_file(char *path, u8* buf, u32 sz); + + +#ifndef PLATFORM_FREEBSD +extern void rtw_free_netdev(struct net_device * netdev); +#endif //PLATFORM_FREEBSD + + +extern u64 rtw_modular64(u64 x, u64 y); +extern u64 rtw_division64(u64 x, u64 y); +extern u32 rtw_random32(void); + +/* Macros for handling unaligned memory accesses */ + +#define RTW_GET_BE16(a) ((u16) (((a)[0] << 8) | (a)[1])) +#define RTW_PUT_BE16(a, val) \ + do { \ + (a)[0] = ((u16) (val)) >> 8; \ + (a)[1] = ((u16) (val)) & 0xff; \ + } while (0) + +#define RTW_GET_LE16(a) ((u16) (((a)[1] << 8) | (a)[0])) +#define RTW_PUT_LE16(a, val) \ + do { \ + (a)[1] = ((u16) (val)) >> 8; \ + (a)[0] = ((u16) (val)) & 0xff; \ + } while (0) + +#define RTW_GET_BE24(a) ((((u32) (a)[0]) << 16) | (((u32) (a)[1]) << 8) | \ + ((u32) (a)[2])) +#define RTW_PUT_BE24(a, val) \ + do { \ + (a)[0] = (u8) ((((u32) (val)) >> 16) & 0xff); \ + (a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \ + (a)[2] = (u8) (((u32) (val)) & 0xff); \ + } while (0) + +#define RTW_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \ + (((u32) (a)[2]) << 8) | ((u32) (a)[3])) +#define RTW_PUT_BE32(a, val) \ + do { \ + (a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \ + (a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \ + (a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \ + (a)[3] = (u8) (((u32) (val)) & 0xff); \ + } while (0) + +#define RTW_GET_LE32(a) ((((u32) (a)[3]) << 24) | (((u32) (a)[2]) << 16) | \ + (((u32) (a)[1]) << 8) | ((u32) (a)[0])) +#define RTW_PUT_LE32(a, val) \ + do { \ + (a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \ + (a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff); \ + (a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \ + (a)[0] = (u8) (((u32) (val)) & 0xff); \ + } while (0) + +#define RTW_GET_BE64(a) ((((u64) (a)[0]) << 56) | (((u64) (a)[1]) << 48) | \ + (((u64) (a)[2]) << 40) | (((u64) (a)[3]) << 32) | \ + (((u64) (a)[4]) << 24) | (((u64) (a)[5]) << 16) | \ + (((u64) (a)[6]) << 8) | ((u64) (a)[7])) +#define RTW_PUT_BE64(a, val) \ + do { \ + (a)[0] = (u8) (((u64) (val)) >> 56); \ + (a)[1] = (u8) (((u64) (val)) >> 48); \ + (a)[2] = (u8) (((u64) (val)) >> 40); \ + (a)[3] = (u8) (((u64) (val)) >> 32); \ + (a)[4] = (u8) (((u64) (val)) >> 24); \ + (a)[5] = (u8) (((u64) (val)) >> 16); \ + (a)[6] = (u8) (((u64) (val)) >> 8); \ + (a)[7] = (u8) (((u64) (val)) & 0xff); \ + } while (0) + +#define RTW_GET_LE64(a) ((((u64) (a)[7]) << 56) | (((u64) (a)[6]) << 48) | \ + (((u64) (a)[5]) << 40) | (((u64) (a)[4]) << 32) | \ + (((u64) (a)[3]) << 24) | (((u64) (a)[2]) << 16) | \ + (((u64) (a)[1]) << 8) | ((u64) (a)[0])) + +void rtw_buf_free(u8 **buf, u32 *buf_len); +void rtw_buf_update(u8 **buf, u32 *buf_len, u8 *src, u32 src_len); + +struct rtw_cbuf { + u32 write; + u32 read; + u32 size; + void *bufs[0]; +}; + +bool rtw_cbuf_full(struct rtw_cbuf *cbuf); +bool rtw_cbuf_empty(struct rtw_cbuf *cbuf); +bool rtw_cbuf_push(struct rtw_cbuf *cbuf, void *buf); +void *rtw_cbuf_pop(struct rtw_cbuf *cbuf); +struct rtw_cbuf *rtw_cbuf_alloc(u32 size); +void rtw_cbuf_free(struct rtw_cbuf *cbuf); + +// String handler + +BOOLEAN IsHexDigit(char chTmp); +BOOLEAN is_alpha(char chTmp); +char alpha_to_upper(char c); + +/* + * Write formatted output to sized buffer + */ +#ifdef PLATFORM_LINUX +#define rtw_sprintf(buf, size, format, arg...) snprintf(buf, size, format, ##arg) +#else // !PLATFORM_LINUX +#error "NOT DEFINE \"rtw_sprintf\"!!" +#endif // !PLATFORM_LINUX + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/osdep_service_bsd.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/osdep_service_bsd.h new file mode 100644 index 000000000..040225c5b --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/osdep_service_bsd.h @@ -0,0 +1,749 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __OSDEP_BSD_SERVICE_H_ +#define __OSDEP_BSD_SERVICE_H_ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include "usbdevs.h" + +#define USB_DEBUG_VAR rum_debug +#include + +#if 1 //Baron porting from linux, it's all temp solution, needs to check again +#include +#include /* XXX for PCPU_GET */ +// typedef struct semaphore _sema; + typedef struct sema _sema; +// typedef spinlock_t _lock; + typedef struct mtx _lock; + typedef struct mtx _mutex; + typedef struct timer_list _timer; + struct list_head { + struct list_head *next, *prev; + }; + struct __queue { + struct list_head queue; + _lock lock; + }; + + //typedef struct sk_buff _pkt; + typedef struct mbuf _pkt; + typedef struct mbuf _buffer; + + typedef struct __queue _queue; + typedef struct list_head _list; + typedef int _OS_STATUS; + //typedef u32 _irqL; + typedef unsigned long _irqL; + typedef struct ifnet * _nic_hdl; + + typedef pid_t _thread_hdl_; +// typedef struct thread _thread_hdl_; + typedef void thread_return; + typedef void* thread_context; + + //#define thread_exit() complete_and_exit(NULL, 0) + + #define thread_exit() do{printf("%s", "RTKTHREAD_exit");}while(0) + + typedef void timer_hdl_return; + typedef void* timer_hdl_context; + typedef struct work_struct _workitem; + +#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c)) +/* emulate a modern version */ +#define LINUX_VERSION_CODE KERNEL_VERSION(2, 6, 35) + +#define WIRELESS_EXT -1 +#define HZ hz +#define spin_lock_irqsave mtx_lock_irqsave +#define spin_lock_bh mtx_lock_irqsave +#define mtx_lock_irqsave(lock, x) mtx_lock(lock)//{local_irq_save((x)); mtx_lock_spin((lock));} +//#define IFT_RTW 0xf9 //ifnet allocate type for RTW +#define free_netdev if_free +#define LIST_CONTAINOR(ptr, type, member) \ + ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) +#define container_of(p,t,n) (t*)((p)-&(((t*)0)->n)) +/* + * Linux timers are emulated using FreeBSD callout functions + * (and taskqueue functionality). + * + * Currently no timer stats functionality. + * + * See (linux_compat) processes.c + * + */ +struct timer_list { + + /* FreeBSD callout related fields */ + struct callout callout; + + //timeout function + void (*function)(void*); + //argument + void *arg; + +}; +struct workqueue_struct; +struct work_struct; +typedef void (*work_func_t)(struct work_struct *work); +/* Values for the state of an item of work (work_struct) */ +typedef enum work_state { + WORK_STATE_UNSET = 0, + WORK_STATE_CALLOUT_PENDING = 1, + WORK_STATE_TASK_PENDING = 2, + WORK_STATE_WORK_CANCELLED = 3 +} work_state_t; + +struct work_struct { + struct task task; /* FreeBSD task */ + work_state_t state; /* the pending or otherwise state of work. */ + work_func_t func; +}; +#define spin_unlock_irqrestore mtx_unlock_irqrestore +#define spin_unlock_bh mtx_unlock_irqrestore +#define mtx_unlock_irqrestore(lock,x) mtx_unlock(lock); +extern void _rtw_spinlock_init(_lock *plock); + +//modify private structure to match freebsd +#define BITS_PER_LONG 32 +union ktime { + s64 tv64; +#if BITS_PER_LONG != 64 && !defined(CONFIG_KTIME_SCALAR) + struct { +#ifdef __BIG_ENDIAN + s32 sec, nsec; +#else + s32 nsec, sec; +#endif + } tv; +#endif +}; +#define kmemcheck_bitfield_begin(name) +#define kmemcheck_bitfield_end(name) +#define CHECKSUM_NONE 0 +typedef unsigned char *sk_buff_data_t; +typedef union ktime ktime_t; /* Kill this */ + +void rtw_mtx_lock(_lock *plock); + +void rtw_mtx_unlock(_lock *plock); + +/** + * struct sk_buff - socket buffer + * @next: Next buffer in list + * @prev: Previous buffer in list + * @sk: Socket we are owned by + * @tstamp: Time we arrived + * @dev: Device we arrived on/are leaving by + * @transport_header: Transport layer header + * @network_header: Network layer header + * @mac_header: Link layer header + * @_skb_refdst: destination entry (with norefcount bit) + * @sp: the security path, used for xfrm + * @cb: Control buffer. Free for use by every layer. Put private vars here + * @len: Length of actual data + * @data_len: Data length + * @mac_len: Length of link layer header + * @hdr_len: writable header length of cloned skb + * @csum: Checksum (must include start/offset pair) + * @csum_start: Offset from skb->head where checksumming should start + * @csum_offset: Offset from csum_start where checksum should be stored + * @local_df: allow local fragmentation + * @cloned: Head may be cloned (check refcnt to be sure) + * @nohdr: Payload reference only, must not modify header + * @pkt_type: Packet class + * @fclone: skbuff clone status + * @ip_summed: Driver fed us an IP checksum + * @priority: Packet queueing priority + * @users: User count - see {datagram,tcp}.c + * @protocol: Packet protocol from driver + * @truesize: Buffer size + * @head: Head of buffer + * @data: Data head pointer + * @tail: Tail pointer + * @end: End pointer + * @destructor: Destruct function + * @mark: Generic packet mark + * @nfct: Associated connection, if any + * @ipvs_property: skbuff is owned by ipvs + * @peeked: this packet has been seen already, so stats have been + * done for it, don't do them again + * @nf_trace: netfilter packet trace flag + * @nfctinfo: Relationship of this skb to the connection + * @nfct_reasm: netfilter conntrack re-assembly pointer + * @nf_bridge: Saved data about a bridged frame - see br_netfilter.c + * @skb_iif: ifindex of device we arrived on + * @rxhash: the packet hash computed on receive + * @queue_mapping: Queue mapping for multiqueue devices + * @tc_index: Traffic control index + * @tc_verd: traffic control verdict + * @ndisc_nodetype: router type (from link layer) + * @dma_cookie: a cookie to one of several possible DMA operations + * done by skb DMA functions + * @secmark: security marking + * @vlan_tci: vlan tag control information + */ + +struct sk_buff { + /* These two members must be first. */ + struct sk_buff *next; + struct sk_buff *prev; + + ktime_t tstamp; + + struct sock *sk; + //struct net_device *dev; + struct ifnet *dev; + + /* + * This is the control buffer. It is free to use for every + * layer. Please put your private variables there. If you + * want to keep them across layers you have to do a skb_clone() + * first. This is owned by whoever has the skb queued ATM. + */ + char cb[48] __aligned(8); + + unsigned long _skb_refdst; +#ifdef CONFIG_XFRM + struct sec_path *sp; +#endif + unsigned int len, + data_len; + u16 mac_len, + hdr_len; + union { + u32 csum; + struct { + u16 csum_start; + u16 csum_offset; + }smbol2; + }smbol1; + u32 priority; + kmemcheck_bitfield_begin(flags1); + u8 local_df:1, + cloned:1, + ip_summed:2, + nohdr:1, + nfctinfo:3; + u8 pkt_type:3, + fclone:2, + ipvs_property:1, + peeked:1, + nf_trace:1; + kmemcheck_bitfield_end(flags1); + u16 protocol; + + void (*destructor)(struct sk_buff *skb); +#if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE) + struct nf_conntrack *nfct; + struct sk_buff *nfct_reasm; +#endif +#ifdef CONFIG_BRIDGE_NETFILTER + struct nf_bridge_info *nf_bridge; +#endif + + int skb_iif; +#ifdef CONFIG_NET_SCHED + u16 tc_index; /* traffic control index */ +#ifdef CONFIG_NET_CLS_ACT + u16 tc_verd; /* traffic control verdict */ +#endif +#endif + + u32 rxhash; + + kmemcheck_bitfield_begin(flags2); + u16 queue_mapping:16; +#ifdef CONFIG_IPV6_NDISC_NODETYPE + u8 ndisc_nodetype:2, + deliver_no_wcard:1; +#else + u8 deliver_no_wcard:1; +#endif + kmemcheck_bitfield_end(flags2); + + /* 0/14 bit hole */ + +#ifdef CONFIG_NET_DMA + dma_cookie_t dma_cookie; +#endif +#ifdef CONFIG_NETWORK_SECMARK + u32 secmark; +#endif + union { + u32 mark; + u32 dropcount; + }symbol3; + + u16 vlan_tci; + + sk_buff_data_t transport_header; + sk_buff_data_t network_header; + sk_buff_data_t mac_header; + /* These elements must be at the end, see alloc_skb() for details. */ + sk_buff_data_t tail; + sk_buff_data_t end; + unsigned char *head, + *data; + unsigned int truesize; + atomic_t users; +}; +struct sk_buff_head { + /* These two members must be first. */ + struct sk_buff *next; + struct sk_buff *prev; + + u32 qlen; + _lock lock; +}; +#define skb_tail_pointer(skb) skb->tail +static inline unsigned char *skb_put(struct sk_buff *skb, unsigned int len) +{ + unsigned char *tmp = skb_tail_pointer(skb); + //SKB_LINEAR_ASSERT(skb); + skb->tail += len; + skb->len += len; + return tmp; +} + +static inline unsigned char *__skb_pull(struct sk_buff *skb, unsigned int len) +{ + skb->len -= len; + if(skb->len < skb->data_len) + printf("%s(),%d,error!\n",__FUNCTION__,__LINE__); + return skb->data += len; +} +static inline unsigned char *skb_pull(struct sk_buff *skb, unsigned int len) +{ + #ifdef PLATFORM_FREEBSD + return __skb_pull(skb, len); + #else + return unlikely(len > skb->len) ? NULL : __skb_pull(skb, len); + #endif //PLATFORM_FREEBSD +} +static inline u32 skb_queue_len(const struct sk_buff_head *list_) +{ + return list_->qlen; +} +static inline void __skb_insert(struct sk_buff *newsk, + struct sk_buff *prev, struct sk_buff *next, + struct sk_buff_head *list) +{ + newsk->next = next; + newsk->prev = prev; + next->prev = prev->next = newsk; + list->qlen++; +} +static inline void __skb_queue_before(struct sk_buff_head *list, + struct sk_buff *next, + struct sk_buff *newsk) +{ + __skb_insert(newsk, next->prev, next, list); +} +static inline void skb_queue_tail(struct sk_buff_head *list, + struct sk_buff *newsk) +{ + mtx_lock(&list->lock); + __skb_queue_before(list, (struct sk_buff *)list, newsk); + mtx_unlock(&list->lock); +} +static inline struct sk_buff *skb_peek(struct sk_buff_head *list_) +{ + struct sk_buff *list = ((struct sk_buff *)list_)->next; + if (list == (struct sk_buff *)list_) + list = NULL; + return list; +} +static inline void __skb_unlink(struct sk_buff *skb, struct sk_buff_head *list) +{ + struct sk_buff *next, *prev; + + list->qlen--; + next = skb->next; + prev = skb->prev; + skb->next = skb->prev = NULL; + next->prev = prev; + prev->next = next; +} + +static inline struct sk_buff *skb_dequeue(struct sk_buff_head *list) +{ + mtx_lock(&list->lock); + + struct sk_buff *skb = skb_peek(list); + if (skb) + __skb_unlink(skb, list); + + mtx_unlock(&list->lock); + + return skb; +} +static inline void skb_reserve(struct sk_buff *skb, int len) +{ + skb->data += len; + skb->tail += len; +} +static inline void __skb_queue_head_init(struct sk_buff_head *list) +{ + list->prev = list->next = (struct sk_buff *)list; + list->qlen = 0; +} +/* + * This function creates a split out lock class for each invocation; + * this is needed for now since a whole lot of users of the skb-queue + * infrastructure in drivers have different locking usage (in hardirq) + * than the networking core (in softirq only). In the long run either the + * network layer or drivers should need annotation to consolidate the + * main types of usage into 3 classes. + */ +static inline void skb_queue_head_init(struct sk_buff_head *list) +{ + _rtw_spinlock_init(&list->lock); + __skb_queue_head_init(list); +} +unsigned long copy_from_user(void *to, const void *from, unsigned long n); +unsigned long copy_to_user(void *to, const void *from, unsigned long n); +struct sk_buff * dev_alloc_skb(unsigned int size); +struct sk_buff *skb_clone(const struct sk_buff *skb); +void dev_kfree_skb_any(struct sk_buff *skb); +#endif //Baron porting from linux, it's all temp solution, needs to check again + + +#if 1 // kenny add Linux compatibility code for Linux USB driver +#include + +#define __init // __attribute ((constructor)) +#define __exit // __attribute ((destructor)) + +/* + * Definitions for module_init and module_exit macros. + * + * These macros will use the SYSINIT framework to call a specified + * function (with no arguments) on module loading or unloading. + * + */ + +void module_init_exit_wrapper(void *arg); + +#define module_init(initfn) \ + SYSINIT(mod_init_ ## initfn, \ + SI_SUB_KLD, SI_ORDER_FIRST, \ + module_init_exit_wrapper, initfn) + +#define module_exit(exitfn) \ + SYSUNINIT(mod_exit_ ## exitfn, \ + SI_SUB_KLD, SI_ORDER_ANY, \ + module_init_exit_wrapper, exitfn) + +/* + * The usb_register and usb_deregister functions are used to register + * usb drivers with the usb subsystem. + */ +int usb_register(struct usb_driver *driver); +int usb_deregister(struct usb_driver *driver); + +/* + * usb_get_dev and usb_put_dev - increment/decrement the reference count + * of the usb device structure. + * + * Original body of usb_get_dev: + * + * if (dev) + * get_device(&dev->dev); + * return dev; + * + * Reference counts are not currently used in this compatibility + * layer. So these functions will do nothing. + */ +static inline struct usb_device * +usb_get_dev(struct usb_device *dev) +{ + return dev; +} + +static inline void +usb_put_dev(struct usb_device *dev) +{ + return; +} + + +// rtw_usb_compat_linux +int rtw_usb_submit_urb(struct urb *urb, uint16_t mem_flags); +int rtw_usb_unlink_urb(struct urb *urb); +int rtw_usb_clear_halt(struct usb_device *dev, struct usb_host_endpoint *uhe); +int rtw_usb_control_msg(struct usb_device *dev, struct usb_host_endpoint *uhe, + uint8_t request, uint8_t requesttype, + uint16_t value, uint16_t index, void *data, + uint16_t size, usb_timeout_t timeout); +int rtw_usb_set_interface(struct usb_device *dev, uint8_t iface_no, uint8_t alt_index); +int rtw_usb_setup_endpoint(struct usb_device *dev, + struct usb_host_endpoint *uhe, usb_size_t bufsize); +struct urb *rtw_usb_alloc_urb(uint16_t iso_packets, uint16_t mem_flags); +struct usb_host_endpoint *rtw_usb_find_host_endpoint(struct usb_device *dev, uint8_t type, uint8_t ep); +struct usb_host_interface *rtw_usb_altnum_to_altsetting(const struct usb_interface *intf, uint8_t alt_index); +struct usb_interface *rtw_usb_ifnum_to_if(struct usb_device *dev, uint8_t iface_no); +void *rtw_usbd_get_intfdata(struct usb_interface *intf); +void rtw_usb_linux_register(void *arg); +void rtw_usb_linux_deregister(void *arg); +void rtw_usb_linux_free_device(struct usb_device *dev); +void rtw_usb_free_urb(struct urb *urb); +void rtw_usb_init_urb(struct urb *urb); +void rtw_usb_kill_urb(struct urb *urb); +void rtw_usb_set_intfdata(struct usb_interface *intf, void *data); +void rtw_usb_fill_bulk_urb(struct urb *urb, struct usb_device *udev, + struct usb_host_endpoint *uhe, void *buf, + int length, usb_complete_t callback, void *arg); +int rtw_usb_bulk_msg(struct usb_device *udev, struct usb_host_endpoint *uhe, + void *data, int len, uint16_t *pactlen, usb_timeout_t timeout); +void *usb_get_intfdata(struct usb_interface *intf); +int usb_linux_init_endpoints(struct usb_device *udev); + + + +typedef struct urb * PURB; + +typedef unsigned gfp_t; +#define __GFP_WAIT ((gfp_t)0x10u) /* Can wait and reschedule? */ +#define __GFP_HIGH ((gfp_t)0x20u) /* Should access emergency pools? */ +#define __GFP_IO ((gfp_t)0x40u) /* Can start physical IO? */ +#define __GFP_FS ((gfp_t)0x80u) /* Can call down to low-level FS? */ +#define __GFP_COLD ((gfp_t)0x100u) /* Cache-cold page required */ +#define __GFP_NOWARN ((gfp_t)0x200u) /* Suppress page allocation failure warning */ +#define __GFP_REPEAT ((gfp_t)0x400u) /* Retry the allocation. Might fail */ +#define __GFP_NOFAIL ((gfp_t)0x800u) /* Retry for ever. Cannot fail */ +#define __GFP_NORETRY ((gfp_t)0x1000u)/* Do not retry. Might fail */ +#define __GFP_NO_GROW ((gfp_t)0x2000u)/* Slab internal usage */ +#define __GFP_COMP ((gfp_t)0x4000u)/* Add compound page metadata */ +#define __GFP_ZERO ((gfp_t)0x8000u)/* Return zeroed page on success */ +#define __GFP_NOMEMALLOC ((gfp_t)0x10000u) /* Don't use emergency reserves */ +#define __GFP_HARDWALL ((gfp_t)0x20000u) /* Enforce hardwall cpuset memory allocs */ + +/* This equals 0, but use constants in case they ever change */ +#define GFP_NOWAIT (GFP_ATOMIC & ~__GFP_HIGH) +/* GFP_ATOMIC means both !wait (__GFP_WAIT not set) and use emergency pool */ +#define GFP_ATOMIC (__GFP_HIGH) +#define GFP_NOIO (__GFP_WAIT) +#define GFP_NOFS (__GFP_WAIT | __GFP_IO) +#define GFP_KERNEL (__GFP_WAIT | __GFP_IO | __GFP_FS) +#define GFP_USER (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL) +#define GFP_HIGHUSER (__GFP_WAIT | __GFP_IO | __GFP_FS | __GFP_HARDWALL | \ + __GFP_HIGHMEM) + + +#endif // kenny add Linux compatibility code for Linux USB + +__inline static _list *get_next(_list *list) +{ + return list->next; +} + +__inline static _list *get_list_head(_queue *queue) +{ + return (&(queue->queue)); +} + + +#define LIST_CONTAINOR(ptr, type, member) \ + ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) + + +__inline static void _enter_critical(_lock *plock, _irqL *pirqL) +{ + spin_lock_irqsave(plock, *pirqL); +} + +__inline static void _exit_critical(_lock *plock, _irqL *pirqL) +{ + spin_unlock_irqrestore(plock, *pirqL); +} + +__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL) +{ + spin_lock_irqsave(plock, *pirqL); +} + +__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL) +{ + spin_unlock_irqrestore(plock, *pirqL); +} + +__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL) +{ + spin_lock_bh(plock, *pirqL); +} + +__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL) +{ + spin_unlock_bh(plock, *pirqL); +} + +__inline static void _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) +{ + + mtx_lock(pmutex); + +} + + +__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) +{ + + mtx_unlock(pmutex); + +} +static inline void __list_del(struct list_head * prev, struct list_head * next) +{ + next->prev = prev; + prev->next = next; +} +static inline void INIT_LIST_HEAD(struct list_head *list) +{ + list->next = list; + list->prev = list; +} +__inline static void rtw_list_delete(_list *plist) +{ + __list_del(plist->prev, plist->next); + INIT_LIST_HEAD(plist); +} + +__inline static void _init_timer(_timer *ptimer,_nic_hdl padapter,void *pfunc,void* cntx) +{ + ptimer->function = pfunc; + ptimer->arg = cntx; + callout_init(&ptimer->callout, CALLOUT_MPSAFE); +} + +__inline static void _set_timer(_timer *ptimer,u32 delay_time) +{ + // mod_timer(ptimer , (jiffies+(delay_time*HZ/1000))); + if(ptimer->function && ptimer->arg){ + rtw_mtx_lock(NULL); + callout_reset(&ptimer->callout, delay_time,ptimer->function, ptimer->arg); + rtw_mtx_unlock(NULL); + } +} + +__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled) +{ + // del_timer_sync(ptimer); + // *bcancelled= _TRUE;//TRUE ==1; FALSE==0 + rtw_mtx_lock(NULL); + callout_drain(&ptimer->callout); + rtw_mtx_unlock(NULL); +} + +__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) +{ + printf("%s Not implement yet! \n",__FUNCTION__); +} + +__inline static void _set_workitem(_workitem *pwork) +{ + printf("%s Not implement yet! \n",__FUNCTION__); +// schedule_work(pwork); +} + +// +// Global Mutex: can only be used at PASSIVE level. +// + +#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ +} + +#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ +} + +#define ATOMIC_INIT(i) { (i) } + +static __inline void thread_enter(char *name); + +//Atomic integer operations +typedef uint32_t ATOMIC_T ; + +#define rtw_netdev_priv(netdev) (((struct ifnet *)netdev)->if_softc) + +#define rtw_free_netdev(netdev) if_free((netdev)) + +#define NDEV_FMT "%s" +#define NDEV_ARG(ndev) "" +#define ADPT_FMT "%s" +#define ADPT_ARG(adapter) "" +#define FUNC_NDEV_FMT "%s" +#define FUNC_NDEV_ARG(ndev) __func__ +#define FUNC_ADPT_FMT "%s" +#define FUNC_ADPT_ARG(adapter) __func__ + +#define STRUCT_PACKED + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/osdep_service_ce.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/osdep_service_ce.h new file mode 100644 index 000000000..5f2a78aef --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/osdep_service_ce.h @@ -0,0 +1,192 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __OSDEP_CE_SERVICE_H_ +#define __OSDEP_CE_SERVICE_H_ + + +#include +#include + +#ifdef CONFIG_SDIO_HCI +#include "SDCardDDK.h" +#endif + +#ifdef CONFIG_USB_HCI +#include +#endif + +typedef HANDLE _sema; +typedef LIST_ENTRY _list; +typedef NDIS_STATUS _OS_STATUS; + +typedef NDIS_SPIN_LOCK _lock; + +typedef HANDLE _rwlock; //Mutex + +typedef u32 _irqL; + +typedef NDIS_HANDLE _nic_hdl; + + +typedef NDIS_MINIPORT_TIMER _timer; + +struct __queue { + LIST_ENTRY queue; + _lock lock; +}; + +typedef NDIS_PACKET _pkt; +typedef NDIS_BUFFER _buffer; +typedef struct __queue _queue; + +typedef HANDLE _thread_hdl_; +typedef DWORD thread_return; +typedef void* thread_context; +typedef NDIS_WORK_ITEM _workitem; + +#define thread_exit() ExitThread(STATUS_SUCCESS); return 0; + + +#define SEMA_UPBND (0x7FFFFFFF) //8192 + +__inline static _list *get_prev(_list *list) +{ + return list->Blink; +} + +__inline static _list *get_next(_list *list) +{ + return list->Flink; +} + +__inline static _list *get_list_head(_queue *queue) +{ + return (&(queue->queue)); +} + +#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member) + +__inline static void _enter_critical(_lock *plock, _irqL *pirqL) +{ + NdisAcquireSpinLock(plock); +} + +__inline static void _exit_critical(_lock *plock, _irqL *pirqL) +{ + NdisReleaseSpinLock(plock); +} + +__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL) +{ + NdisDprAcquireSpinLock(plock); +} + +__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL) +{ + NdisDprReleaseSpinLock(plock); +} + + +__inline static void _enter_hwio_critical(_rwlock *prwlock, _irqL *pirqL) +{ + WaitForSingleObject(*prwlock, INFINITE ); + +} + +__inline static void _exit_hwio_critical(_rwlock *prwlock, _irqL *pirqL) +{ + ReleaseMutex(*prwlock); +} + +__inline static void rtw_list_delete(_list *plist) +{ + RemoveEntryList(plist); + InitializeListHead(plist); +} + +#define RTW_TIMER_HDL_ARGS IN PVOID SystemSpecific1, IN PVOID FunctionContext, IN PVOID SystemSpecific2, IN PVOID SystemSpecific3 + +__inline static void _init_timer(_timer *ptimer,_nic_hdl nic_hdl,void *pfunc,PVOID cntx) +{ + NdisMInitializeTimer(ptimer, nic_hdl, pfunc, cntx); +} + +__inline static void _set_timer(_timer *ptimer,u32 delay_time) +{ + NdisMSetTimer(ptimer,delay_time); +} + +__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled) +{ + NdisMCancelTimer(ptimer,bcancelled); +} + +__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) +{ + + NdisInitializeWorkItem(pwork, pfunc, cntx); +} + +__inline static void _set_workitem(_workitem *pwork) +{ + NdisScheduleWorkItem(pwork); +} + +#define ATOMIC_INIT(i) { (i) } + +// +// Global Mutex: can only be used at PASSIVE level. +// + +#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ + while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\ + { \ + NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ + NdisMSleep(10000); \ + } \ +} + +#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ + NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ +} + +// limitation of path length +#define PATH_LENGTH_MAX MAX_PATH + +//Atomic integer operations +#define ATOMIC_T LONG + +#define NDEV_FMT "%s" +#define NDEV_ARG(ndev) "" +#define ADPT_FMT "%s" +#define ADPT_ARG(adapter) "" +#define FUNC_NDEV_FMT "%s" +#define FUNC_NDEV_ARG(ndev) __func__ +#define FUNC_ADPT_FMT "%s" +#define FUNC_ADPT_ARG(adapter) __func__ + +#define STRUCT_PACKED + + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/osdep_service_linux.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/osdep_service_linux.h new file mode 100644 index 000000000..ddd2fb294 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/osdep_service_linux.h @@ -0,0 +1,459 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __OSDEP_LINUX_SERVICE_H_ +#define __OSDEP_LINUX_SERVICE_H_ + + #include + #include + #include + #include + #include + #include + #include + #include +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,5)) + #include +#endif + //#include + #include + #include + #include + #include + #include + #include + #include +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) + #include +#else + #include +#endif + #include + #include + #include + #include + #include + #include + #include + #include + #include // for struct tasklet_struct + #include + #include + #include + #include + +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,5,41)) + #include +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 7, 0)) + #include +#else + #include +#endif + +#ifdef RTK_DMP_PLATFORM +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,12)) + #include +#endif + #include +#endif + +#ifdef CONFIG_NET_RADIO + #define CONFIG_WIRELESS_EXT +#endif + + /* Monitor mode */ + #include + #include +#ifdef CONFIG_IOCTL_CFG80211 +/* #include */ + #include +#endif //CONFIG_IOCTL_CFG80211 + +#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX + #include + #include +#endif + +#ifdef CONFIG_HAS_EARLYSUSPEND + #include +#endif //CONFIG_HAS_EARLYSUSPEND + +#ifdef CONFIG_EFUSE_CONFIG_FILE + #include +#endif + +#ifdef CONFIG_USB_HCI + #include +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) + #include +#else + #include +#endif +#endif + +#ifdef CONFIG_BT_COEXIST_SOCKET_TRX + #include + #include + #include + #include + #include +#endif //CONFIG_BT_COEXIST_SOCKET_TRX + +#ifdef CONFIG_USB_HCI + typedef struct urb * PURB; +#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,22)) +#ifdef CONFIG_USB_SUSPEND +#define CONFIG_AUTOSUSPEND 1 +#endif +#endif +#endif + + typedef struct semaphore _sema; + typedef spinlock_t _lock; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) + typedef struct mutex _mutex; +#else + typedef struct semaphore _mutex; +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) + typedef struct legacy_timer_emu { + struct timer_list t; + void (*function)(unsigned long); + unsigned long data; + } _timer; +#else + typedef struct timer_list _timer; +#endif + + struct __queue { + struct list_head queue; + _lock lock; + }; + + typedef struct sk_buff _pkt; + typedef unsigned char _buffer; + + typedef struct __queue _queue; + typedef struct list_head _list; + typedef int _OS_STATUS; + //typedef u32 _irqL; + typedef unsigned long _irqL; + typedef struct net_device * _nic_hdl; + + typedef void* _thread_hdl_; + typedef int thread_return; + typedef void* thread_context; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0)) + #define thread_exit() kthread_complete_and_exit(NULL, 0) +#else + #define thread_exit() complete_and_exit(NULL, 0) +#endif + + typedef void timer_hdl_return; + typedef void* timer_hdl_context; + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41)) + typedef struct work_struct _workitem; +#else + typedef struct tq_struct _workitem; +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) + #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22)) +// Porting from linux kernel, for compatible with old kernel. +static inline unsigned char *skb_tail_pointer(const struct sk_buff *skb) +{ + return skb->tail; +} + +static inline void skb_reset_tail_pointer(struct sk_buff *skb) +{ + skb->tail = skb->data; +} + +static inline void skb_set_tail_pointer(struct sk_buff *skb, const int offset) +{ + skb->tail = skb->data + offset; +} + +static inline unsigned char *skb_end_pointer(const struct sk_buff *skb) +{ + return skb->end; +} +#endif + +__inline static _list *get_next(_list *list) +{ + return list->next; +} + +__inline static _list *get_list_head(_queue *queue) +{ + return (&(queue->queue)); +} + + +#define LIST_CONTAINOR(ptr, type, member) \ + ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) + + +__inline static void _enter_critical(_lock *plock, _irqL *pirqL) +{ + spin_lock_irqsave(plock, *pirqL); +} + +__inline static void _exit_critical(_lock *plock, _irqL *pirqL) +{ + spin_unlock_irqrestore(plock, *pirqL); +} + +__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL) +{ + spin_lock_irqsave(plock, *pirqL); +} + +__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL) +{ + spin_unlock_irqrestore(plock, *pirqL); +} + +__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL) +{ + spin_lock_bh(plock); +} + +__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL) +{ + spin_unlock_bh(plock); +} + +__inline static int _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) +{ + int ret = 0; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) + //mutex_lock(pmutex); + ret = mutex_lock_interruptible(pmutex); +#else + ret = down_interruptible(pmutex); +#endif + return ret; +} + + +__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) + mutex_unlock(pmutex); +#else + up(pmutex); +#endif +} + +__inline static void rtw_list_delete(_list *plist) +{ + list_del_init(plist); +} + +#define RTW_TIMER_HDL_ARGS void *FunctionContext + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) +static void legacy_timer_emu_func(struct timer_list *t) +{ + struct legacy_timer_emu *lt = from_timer(lt, t, t); + lt->function(lt->data); +} +#endif + +__inline static void _init_timer(_timer *ptimer,_nic_hdl nic_hdl,void *pfunc,void* cntx) +{ + //setup_timer(ptimer, pfunc,(u32)cntx); + ptimer->function = pfunc; + ptimer->data = (unsigned long)cntx; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) + timer_setup(&ptimer->t, legacy_timer_emu_func, 0); +#else + init_timer(ptimer); +#endif +} + +__inline static void _set_timer(_timer *ptimer,u32 delay_time) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) + mod_timer(&ptimer->t, (jiffies+(delay_time*HZ/1000))); +#else + mod_timer(ptimer , (jiffies+(delay_time*HZ/1000))); +#endif +} + +__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 15, 0)) + del_timer_sync(&ptimer->t); +#else + del_timer_sync(ptimer); +#endif + *bcancelled = 1; +} + + +static inline void _init_workitem(_workitem *pwork, void *pfunc, void *cntx) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) + INIT_WORK(pwork, pfunc); +#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41)) + INIT_WORK(pwork, pfunc,pwork); +#else + INIT_TQUEUE(pwork, pfunc,pwork); +#endif +} + +__inline static void _set_workitem(_workitem *pwork) +{ +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41)) + schedule_work(pwork); +#else + schedule_task(pwork); +#endif +} + +__inline static void _cancel_workitem_sync(_workitem *pwork) +{ +#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,22)) + cancel_work_sync(pwork); +#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41)) + flush_scheduled_work(); +#else + flush_scheduled_tasks(); +#endif +} +// +// Global Mutex: can only be used at PASSIVE level. +// + +#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ + while (atomic_inc_return((atomic_t *)&(_MutexCounter)) != 1)\ + { \ + atomic_dec((atomic_t *)&(_MutexCounter)); \ + msleep(10); \ + } \ +} + +#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ + atomic_dec((atomic_t *)&(_MutexCounter)); \ +} + +static inline int rtw_netif_queue_stopped(struct net_device *pnetdev) +{ +#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) + return (netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 0)) && + netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 1)) && + netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 2)) && + netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 3)) ); +#else + return netif_queue_stopped(pnetdev); +#endif +} + +static inline void rtw_netif_wake_queue(struct net_device *pnetdev) +{ +#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) + netif_tx_wake_all_queues(pnetdev); +#else + netif_wake_queue(pnetdev); +#endif +} + +static inline void rtw_netif_start_queue(struct net_device *pnetdev) +{ +#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) + netif_tx_start_all_queues(pnetdev); +#else + netif_start_queue(pnetdev); +#endif +} + +static inline void rtw_netif_stop_queue(struct net_device *pnetdev) +{ +#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) + netif_tx_stop_all_queues(pnetdev); +#else + netif_stop_queue(pnetdev); +#endif +} + +static inline int rtw_merge_string(char *dst, int dst_len, const char *src1, const char *src2) +{ + int len = 0; + len += snprintf(dst+len, dst_len - len, "%s", src1); + len += snprintf(dst+len, dst_len - len, "%s", src2); + + return len; +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)) +#define rtw_signal_process(pid, sig) kill_pid(find_vpid((pid)),(sig), 1) +#else //(LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)) +#define rtw_signal_process(pid, sig) kill_proc((pid), (sig), 1) +#endif //(LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)) + + +// Suspend lock prevent system from going suspend +#ifdef CONFIG_WAKELOCK +#include +#elif defined(CONFIG_ANDROID_POWER) +#include +#endif + +// limitation of path length +#define PATH_LENGTH_MAX PATH_MAX + +//Atomic integer operations +#define ATOMIC_T atomic_t + +#define rtw_netdev_priv(netdev) ( ((struct rtw_netdev_priv_indicator *)netdev_priv(netdev))->priv ) + +#define NDEV_FMT "%s" +#define NDEV_ARG(ndev) ndev->name +#define ADPT_FMT "%s" +#define ADPT_ARG(adapter) adapter->pnetdev->name +#define FUNC_NDEV_FMT "%s(%s)" +#define FUNC_NDEV_ARG(ndev) __func__, ndev->name +#define FUNC_ADPT_FMT "%s(%s)" +#define FUNC_ADPT_ARG(adapter) __func__, adapter->pnetdev->name + +struct rtw_netdev_priv_indicator { + void *priv; + u32 sizeof_priv; +}; +struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, void *old_priv); +extern struct net_device * rtw_alloc_etherdev(int sizeof_priv); + +#define STRUCT_PACKED __attribute__ ((packed)) + + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/osdep_service_xp.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/osdep_service_xp.h new file mode 100644 index 000000000..61b1a00f5 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/osdep_service_xp.h @@ -0,0 +1,202 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __OSDEP_LINUX_SERVICE_H_ +#define __OSDEP_LINUX_SERVICE_H_ + + #include + #include + #include + #include + +#ifdef CONFIG_USB_HCI + #include + #include + #include +#endif + + typedef KSEMAPHORE _sema; + typedef LIST_ENTRY _list; + typedef NDIS_STATUS _OS_STATUS; + + + typedef NDIS_SPIN_LOCK _lock; + + typedef KMUTEX _mutex; + + typedef KIRQL _irqL; + + // USB_PIPE for WINCE , but handle can be use just integer under windows + typedef NDIS_HANDLE _nic_hdl; + + + typedef NDIS_MINIPORT_TIMER _timer; + + struct __queue { + LIST_ENTRY queue; + _lock lock; + }; + + typedef NDIS_PACKET _pkt; + typedef NDIS_BUFFER _buffer; + typedef struct __queue _queue; + + typedef PKTHREAD _thread_hdl_; + typedef void thread_return; + typedef void* thread_context; + + typedef NDIS_WORK_ITEM _workitem; + + #define thread_exit() PsTerminateSystemThread(STATUS_SUCCESS); + + #define HZ 10000000 + #define SEMA_UPBND (0x7FFFFFFF) //8192 + +__inline static _list *get_next(_list *list) +{ + return list->Flink; +} + +__inline static _list *get_list_head(_queue *queue) +{ + return (&(queue->queue)); +} + + +#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member) + + +__inline static _enter_critical(_lock *plock, _irqL *pirqL) +{ + NdisAcquireSpinLock(plock); +} + +__inline static _exit_critical(_lock *plock, _irqL *pirqL) +{ + NdisReleaseSpinLock(plock); +} + + +__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL) +{ + NdisDprAcquireSpinLock(plock); +} + +__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL) +{ + NdisDprReleaseSpinLock(plock); +} + +__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL) +{ + NdisDprAcquireSpinLock(plock); +} + +__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL) +{ + NdisDprReleaseSpinLock(plock); +} + +__inline static _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) +{ + KeWaitForSingleObject(pmutex, Executive, KernelMode, FALSE, NULL); +} + + +__inline static _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) +{ + KeReleaseMutex(pmutex, FALSE); +} + + +__inline static void rtw_list_delete(_list *plist) +{ + RemoveEntryList(plist); + InitializeListHead(plist); +} + +#define RTW_TIMER_HDL_ARGS IN PVOID SystemSpecific1, IN PVOID FunctionContext, IN PVOID SystemSpecific2, IN PVOID SystemSpecific3 + +__inline static void _init_timer(_timer *ptimer,_nic_hdl nic_hdl,void *pfunc,PVOID cntx) +{ + NdisMInitializeTimer(ptimer, nic_hdl, pfunc, cntx); +} + +__inline static void _set_timer(_timer *ptimer,u32 delay_time) +{ + NdisMSetTimer(ptimer,delay_time); +} + +__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled) +{ + NdisMCancelTimer(ptimer,bcancelled); +} + +__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) +{ + + NdisInitializeWorkItem(pwork, pfunc, cntx); +} + +__inline static void _set_workitem(_workitem *pwork) +{ + NdisScheduleWorkItem(pwork); +} + + +#define ATOMIC_INIT(i) { (i) } + +// +// Global Mutex: can only be used at PASSIVE level. +// + +#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ + while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\ + { \ + NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ + NdisMSleep(10000); \ + } \ +} + +#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ +{ \ + NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ +} + +// limitation of path length +#define PATH_LENGTH_MAX MAX_PATH + +//Atomic integer operations +#define ATOMIC_T LONG + + +#define NDEV_FMT "%s" +#define NDEV_ARG(ndev) "" +#define ADPT_FMT "%s" +#define ADPT_ARG(adapter) "" +#define FUNC_NDEV_FMT "%s" +#define FUNC_NDEV_ARG(ndev) __func__ +#define FUNC_ADPT_FMT "%s" +#define FUNC_ADPT_ARG(adapter) __func__ + +#define STRUCT_PACKED + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/pci_hal.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/pci_hal.h new file mode 100644 index 000000000..00157707c --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/pci_hal.h @@ -0,0 +1,46 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __PCI_HAL_H__ +#define __PCI_HAL_H__ + +#ifdef CONFIG_RTL8188E +void rtl8188ee_set_hal_ops(_adapter *padapter); +#endif + +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) +void rtl8812ae_set_hal_ops(_adapter *padapter); +#endif + +#if defined(CONFIG_RTL8192E) +void rtl8192ee_set_hal_ops(_adapter *padapter); +#endif + +#ifdef CONFIG_RTL8723B +void rtl8723be_set_hal_ops(_adapter *padapter); +#endif + +#ifdef CONFIG_RTL8814A +void rtl8814ae_set_hal_ops(_adapter *padapter); +#endif + +u8 rtw_set_hal_ops(_adapter *padapter); + +#endif //__PCIE_HAL_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/pci_ops.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/pci_ops.h new file mode 100644 index 000000000..07add1684 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/pci_ops.h @@ -0,0 +1,78 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __PCI_OPS_H_ +#define __PCI_OPS_H_ + + +#ifdef CONFIG_RTL8188E +u32 rtl8188ee_init_desc_ring(_adapter *padapter); +u32 rtl8188ee_free_desc_ring(_adapter *padapter); +void rtl8188ee_reset_desc_ring(_adapter *padapter); +int rtl8188ee_interrupt(PADAPTER Adapter); +void rtl8188ee_xmit_tasklet(void *priv); +void rtl8188ee_recv_tasklet(void *priv); +void rtl8188ee_prepare_bcn_tasklet(void *priv); +void rtl8188ee_set_intf_ops(struct _io_ops *pops); +#endif + +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) +u32 rtl8812ae_init_desc_ring(_adapter *padapter); +u32 rtl8812ae_free_desc_ring(_adapter *padapter); +void rtl8812ae_reset_desc_ring(_adapter *padapter); +int rtl8812ae_interrupt(PADAPTER Adapter); +void rtl8812ae_xmit_tasklet(void *priv); +void rtl8812ae_recv_tasklet(void *priv); +void rtl8812ae_prepare_bcn_tasklet(void *priv); +void rtl8812ae_set_intf_ops(struct _io_ops *pops); +#endif + +#ifdef CONFIG_RTL8192E +u32 rtl8192ee_init_desc_ring(_adapter *padapter); +u32 rtl8192ee_free_desc_ring(_adapter *padapter); +void rtl8192ee_reset_desc_ring(_adapter *padapter); +void rtl8192ee_recv_tasklet(void *priv); +void rtl8192ee_prepare_bcn_tasklet(void *priv); +int rtl8192ee_interrupt(PADAPTER Adapter); +void rtl8192ee_set_intf_ops(struct _io_ops *pops); +#endif + +#ifdef CONFIG_RTL8723B +u32 rtl8723be_init_desc_ring(_adapter *padapter); +u32 rtl8723be_free_desc_ring(_adapter *padapter); +void rtl8723be_reset_desc_ring(_adapter *padapter); +int rtl8723be_interrupt(PADAPTER Adapter); +void rtl8723be_recv_tasklet(void *priv); +void rtl8723be_prepare_bcn_tasklet(void *priv); +void rtl8723be_set_intf_ops(struct _io_ops *pops); +#endif + +#ifdef CONFIG_RTL8814A +u32 rtl8814ae_init_desc_ring(_adapter *padapter); +u32 rtl8814ae_free_desc_ring(_adapter *padapter); +void rtl8814ae_reset_desc_ring(_adapter *padapter); +int rtl8814ae_interrupt(PADAPTER Adapter); +void rtl8814ae_xmit_tasklet(void *priv); +void rtl8814ae_recv_tasklet(void *priv); +void rtl8814ae_prepare_bcn_tasklet(void *priv); +void rtl8814ae_set_intf_ops(struct _io_ops *pops); +#endif + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/pci_osintf.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/pci_osintf.h new file mode 100644 index 000000000..9df50f733 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/pci_osintf.h @@ -0,0 +1,32 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __PCI_OSINTF_H +#define __PCI_OSINTF_H + + +void rtw_pci_disable_aspm(_adapter *padapter); +void rtw_pci_enable_aspm(_adapter *padapter); +void PlatformClearPciPMEStatus(PADAPTER Adapter); +#ifdef CONFIG_64BIT_DMA +u8 PlatformEnableDMA64(PADAPTER Adapter); +#endif + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/recv_osdep.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/recv_osdep.h new file mode 100644 index 000000000..0a65313ff --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/recv_osdep.h @@ -0,0 +1,65 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RECV_OSDEP_H_ +#define __RECV_OSDEP_H_ + + +extern sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter); +extern void _rtw_free_recv_priv (struct recv_priv *precvpriv); + + +extern s32 rtw_recv_entry(union recv_frame *precv_frame); +extern int rtw_recv_indicatepkt(_adapter *adapter, union recv_frame *precv_frame); +extern void rtw_recv_returnpacket(IN _nic_hdl cnxt, IN _pkt *preturnedpkt); + +extern int rtw_recv_monitor(_adapter *padapter, union recv_frame *precv_frame); + +extern void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame); + +struct sta_info; +extern void rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup); + + +int rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter); +void rtw_free_recv_priv (struct recv_priv *precvpriv); + + +int rtw_os_recv_resource_init(struct recv_priv *precvpriv, _adapter *padapter); +int rtw_os_recv_resource_alloc(_adapter *padapter, union recv_frame *precvframe); +void rtw_os_recv_resource_free(struct recv_priv *precvpriv); + + +int rtw_os_alloc_recvframe(_adapter *padapter, union recv_frame *precvframe, u8 *pdata, _pkt *pskb); +void rtw_os_free_recvframe(union recv_frame *precvframe); + + +int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf); +int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf); + +_pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, u16 nSubframe_Length, u8 *pdata); +void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, struct rx_pkt_attrib *pattrib); + +void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf); + +void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl); + + +#endif // + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_cmd.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_cmd.h new file mode 100644 index 000000000..66d374d6a --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_cmd.h @@ -0,0 +1,221 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTL8188F_CMD_H__ +#define __RTL8188F_CMD_H__ + +//---------------------------------------------------------------------------------------------------------// +//---------------------------------- H2C CMD DEFINITION ------------------------------------------------// +//---------------------------------------------------------------------------------------------------------// + +enum h2c_cmd_8188F{ + //Common Class: 000 + H2C_8188F_RSVD_PAGE = 0x00, + H2C_8188F_MEDIA_STATUS_RPT = 0x01, + H2C_8188F_SCAN_ENABLE = 0x02, + H2C_8188F_KEEP_ALIVE = 0x03, + H2C_8188F_DISCON_DECISION = 0x04, + H2C_8188F_PSD_OFFLOAD = 0x05, + H2C_8188F_AP_OFFLOAD = 0x08, + H2C_8188F_BCN_RSVDPAGE = 0x09, + H2C_8188F_PROBERSP_RSVDPAGE = 0x0A, + H2C_8188F_FCS_RSVDPAGE = 0x10, + H2C_8188F_FCS_INFO = 0x11, + H2C_8188F_AP_WOW_GPIO_CTRL = 0x13, + + //PoweSave Class: 001 + H2C_8188F_SET_PWR_MODE = 0x20, + H2C_8188F_PS_TUNING_PARA = 0x21, + H2C_8188F_PS_TUNING_PARA2 = 0x22, + H2C_8188F_P2P_LPS_PARAM = 0x23, + H2C_8188F_P2P_PS_OFFLOAD = 0x24, + H2C_8188F_PS_SCAN_ENABLE = 0x25, + H2C_8188F_SAP_PS_ = 0x26, + H2C_8188F_INACTIVE_PS_ = 0x27, //Inactive_PS + H2C_8188F_FWLPS_IN_IPS_ = 0x28, + + //Dynamic Mechanism Class: 010 + H2C_8188F_MACID_CFG = 0x40, + H2C_8188F_TXBF = 0x41, + H2C_8188F_RSSI_SETTING = 0x42, + H2C_8188F_AP_REQ_TXRPT = 0x43, + H2C_8188F_INIT_RATE_COLLECT = 0x44, + H2C_8188F_RA_PARA_ADJUST = 0x46, + + //BT Class: 011 + H2C_8188F_B_TYPE_TDMA = 0x60, + H2C_8188F_BT_INFO = 0x61, + H2C_8188F_FORCE_BT_TXPWR = 0x62, + H2C_8188F_BT_IGNORE_WLANACT = 0x63, + H2C_8188F_DAC_SWING_VALUE = 0x64, + H2C_8188F_ANT_SEL_RSV = 0x65, + H2C_8188F_WL_OPMODE = 0x66, + H2C_8188F_BT_MP_OPER = 0x67, + H2C_8188F_BT_CONTROL = 0x68, + H2C_8188F_BT_WIFI_CTRL = 0x69, + H2C_8188F_BT_FW_PATCH = 0x6A, + H2C_8188F_BT_WLAN_CALIBRATION = 0x6D, + + //WOWLAN Class: 100 + H2C_8188F_WOWLAN = 0x80, + H2C_8188F_REMOTE_WAKE_CTRL = 0x81, + H2C_8188F_AOAC_GLOBAL_INFO = 0x82, + H2C_8188F_AOAC_RSVD_PAGE = 0x83, + H2C_8188F_AOAC_RSVD_PAGE2 = 0x84, + H2C_8188F_D0_SCAN_OFFLOAD_CTRL = 0x85, + H2C_8188F_D0_SCAN_OFFLOAD_INFO = 0x86, + H2C_8188F_CHNL_SWITCH_OFFLOAD = 0x87, + H2C_8188F_P2P_OFFLOAD_RSVD_PAGE = 0x8A, + H2C_8188F_P2P_OFFLOAD = 0x8B, + + H2C_8188F_RESET_TSF = 0xC0, + H2C_8188F_MAXID, +}; + +//---------------------------------------------------------------------------------------------------------// +//---------------------------------- H2C CMD CONTENT --------------------------------------------------// +//---------------------------------------------------------------------------------------------------------// +//_RSVDPAGE_LOC_CMD_0x00 +#define SET_8188F_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8188F_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) +#define SET_8188F_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_8188F_H2CCMD_RSVDPAGE_LOC_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_8188F_H2CCMD_RSVDPAGE_LOC_BT_QOS_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) + +//_KEEP_ALIVE_CMD_0x03 +#define SET_8188F_H2CCMD_KEEPALIVE_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_8188F_H2CCMD_KEEPALIVE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_8188F_H2CCMD_KEEPALIVE_PARM_PKT_TYPE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) +#define SET_8188F_H2CCMD_KEEPALIVE_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) + +//_DISCONNECT_DECISION_CMD_0x04 +#define SET_8188F_H2CCMD_DISCONDECISION_PARM_ENABLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) +#define SET_8188F_H2CCMD_DISCONDECISION_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) +#define SET_8188F_H2CCMD_DISCONDECISION_PARM_CHECK_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) +#define SET_8188F_H2CCMD_DISCONDECISION_PARM_TRY_PKT_NUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value) + +// _PWR_MOD_CMD_0x20 +#define SET_8188F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8188F_H2CCMD_PWRMODE_PARM_RLBM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 4, __Value) +#define SET_8188F_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 4, 4, __Value) +#define SET_8188F_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_8188F_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_8188F_H2CCMD_PWRMODE_PARM_BCN_EARLY_C2H_RPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 2, 1, __Value) +#define SET_8188F_H2CCMD_PWRMODE_PARM_PWR_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) +#define SET_8188F_H2CCMD_PWRMODE_PARM_BYTE5(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) + +#define GET_8188F_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd) LE_BITS_TO_1BYTE(__pH2CCmd, 0, 8) + +// _PS_TUNE_PARAM_CMD_0x21 +#define SET_8188F_H2CCMD_PSTUNE_PARM_BCN_TO_LIMIT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8188F_H2CCMD_PSTUNE_PARM_DTIM_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) +#define SET_8188F_H2CCMD_PSTUNE_PARM_ADOPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 1, __Value) +#define SET_8188F_H2CCMD_PSTUNE_PARM_PS_TIMEOUT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 1, 7, __Value) +#define SET_8188F_H2CCMD_PSTUNE_PARM_DTIM_PERIOD(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) + +//_MACID_CFG_CMD_0x40 +#define SET_8188F_H2CCMD_MACID_CFG_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8188F_H2CCMD_MACID_CFG_RAID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 5, __Value) +#define SET_8188F_H2CCMD_MACID_CFG_SGI_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 7, 1, __Value) +#define SET_8188F_H2CCMD_MACID_CFG_BW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 2, __Value) +#define SET_8188F_H2CCMD_MACID_CFG_NO_UPDATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 3, 1, __Value) +#define SET_8188F_H2CCMD_MACID_CFG_VHT_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 4, 2, __Value) +#define SET_8188F_H2CCMD_MACID_CFG_DISPT(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 6, 1, __Value) +#define SET_8188F_H2CCMD_MACID_CFG_DISRA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 7, 1, __Value) +#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) +#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value) +#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+5, 0, 8, __Value) +#define SET_8188F_H2CCMD_MACID_CFG_RATE_MASK3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+6, 0, 8, __Value) + +//_RSSI_SETTING_CMD_0x42 +#define SET_8188F_H2CCMD_RSSI_SETTING_MACID(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8188F_H2CCMD_RSSI_SETTING_RSSI(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 7, __Value) +#define SET_8188F_H2CCMD_RSSI_SETTING_ULDL_STATE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) + +// _AP_REQ_TXRPT_CMD_0x43 +#define SET_8188F_H2CCMD_APREQRPT_PARM_MACID1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) +#define SET_8188F_H2CCMD_APREQRPT_PARM_MACID2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) + +// _FORCE_BT_TXPWR_CMD_0x62 +#define SET_8188F_H2CCMD_BT_PWR_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) + +// _FORCE_BT_MP_OPER_CMD_0x67 +#define SET_8188F_H2CCMD_BT_MPOPER_VER(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 4, __Value) +#define SET_8188F_H2CCMD_BT_MPOPER_REQNUM(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 4, __Value) +#define SET_8188F_H2CCMD_BT_MPOPER_IDX(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+1, 0, 8, __Value) +#define SET_8188F_H2CCMD_BT_MPOPER_PARAM1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+2, 0, 8, __Value) +#define SET_8188F_H2CCMD_BT_MPOPER_PARAM2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+3, 0, 8, __Value) +#define SET_8188F_H2CCMD_BT_MPOPER_PARAM3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd+4, 0, 8, __Value) + +// _BT_FW_PATCH_0x6A +#define SET_8188F_H2CCMD_BT_FW_PATCH_SIZE(__pH2CCmd, __Value) SET_BITS_TO_LE_2BYTE((pu1Byte)(__pH2CCmd), 0, 16, __Value) +#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) +#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+3, 0, 8, __Value) +#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR2(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+4, 0, 8, __Value) +#define SET_8188F_H2CCMD_BT_FW_PATCH_ADDR3(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+5, 0, 8, __Value) + + +//---------------------------------------------------------------------------------------------------------// +//------------------------------------------- Structure --------------------------------------------------// +//---------------------------------------------------------------------------------------------------------// + + +//---------------------------------------------------------------------------------------------------------// +//---------------------------------- Function Statement --------------------------------------------------// +//---------------------------------------------------------------------------------------------------------// + +// host message to firmware cmd +void rtl8188f_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode); +void rtl8188f_set_FwJoinBssRpt_cmd(PADAPTER padapter, u8 mstatus); +void rtl8188f_set_rssi_cmd(PADAPTER padapter, u8 *param); +void rtl8188f_Add_RateATid(PADAPTER pAdapter, u64 bitmap, u8* arg, u8 rssi_level); +void rtl8188f_fw_try_ap_cmd(PADAPTER padapter, u32 need_ack); +//s32 rtl8188f_set_lowpwr_lps_cmd(PADAPTER padapter, u8 enable); +void rtl8188f_set_FwPsTuneParam_cmd(PADAPTER padapter); +void rtl8188f_set_FwMacIdConfig_cmd(_adapter* padapter, u8 mac_id, u8 raid, u8 bw, u8 sgi, u32 mask); +void rtl8188f_set_FwBtMpOper_cmd(PADAPTER padapter, u8 idx, u8 ver, u8 reqnum, u8 *param); +void rtl8188f_download_rsvd_page(PADAPTER padapter, u8 mstatus); +#ifdef CONFIG_BT_COEXIST +void rtl8188f_download_BTCoex_AP_mode_rsvd_page(PADAPTER padapter); +#endif // CONFIG_BT_COEXIST +#ifdef CONFIG_P2P +void rtl8188f_set_p2p_ps_offload_cmd(PADAPTER padapter, u8 p2p_ps_state); +#endif //CONFIG_P2P + +void CheckFwRsvdPageContent(PADAPTER padapter); + +#ifdef CONFIG_TDLS +#ifdef CONFIG_TDLS_CH_SW +void rtl8188f_set_BcnEarly_C2H_Rpt_cmd(PADAPTER padapter, u8 enable); +#endif +#endif + +#ifdef CONFIG_P2P_WOWLAN +void rtl8188f_set_p2p_wowlan_offload_cmd(PADAPTER padapter); +#endif + +void rtl8188f_set_FwPwrModeInIPS_cmd(PADAPTER padapter, u8 cmd_param); + +#ifdef CONFIG_TSF_RESET_OFFLOAD +u8 rtl8188f_reset_tsf(_adapter *padapter, u8 reset_port); +#endif // CONFIG_TSF_RESET_OFFLOAD +s32 FillH2CCmd8188F(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); +u8 GetTxBufferRsvdPageNum8188F(_adapter *padapter, bool wowlan); +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_dm.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_dm.h new file mode 100644 index 000000000..d703ae524 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_dm.h @@ -0,0 +1,48 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTL8188F_DM_H__ +#define __RTL8188F_DM_H__ +//============================================================ +// Description: +// +// This file is for 8188F dynamic mechanism only +// +// +//============================================================ + +//============================================================ +// structure and define +//============================================================ + +//============================================================ +// function prototype +//============================================================ + +void rtl8188f_init_dm_priv(PADAPTER padapter); +void rtl8188f_deinit_dm_priv(PADAPTER padapter); + +void rtl8188f_InitHalDm(PADAPTER padapter); +void rtl8188f_HalDmWatchDog(PADAPTER padapter); +void rtl8188f_HalDmWatchDog_in_LPS(PADAPTER padapter); +void rtl8188f_hal_dm_in_lps(PADAPTER padapter); + + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_hal.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_hal.h new file mode 100644 index 000000000..22024d122 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_hal.h @@ -0,0 +1,264 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTL8188F_HAL_H__ +#define __RTL8188F_HAL_H__ + +#include "hal_data.h" + +#include "rtl8188f_spec.h" +#include "rtl8188f_rf.h" +#include "rtl8188f_dm.h" +#include "rtl8188f_recv.h" +#include "rtl8188f_xmit.h" +#include "rtl8188f_cmd.h" +#include "rtl8188f_led.h" +#include "Hal8188FPwrSeq.h" +#include "Hal8188FPhyReg.h" +#include "Hal8188FPhyCfg.h" +#ifdef DBG_CONFIG_ERROR_DETECT +#include "rtl8188f_sreset.h" +#endif + +#define FW_8188F_SIZE 0x8000 +#define FW_8188F_START_ADDRESS 0x1000 +#define FW_8188F_END_ADDRESS 0x1FFF //0x5FFF + +#define IS_FW_HEADER_EXIST_8188F(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88F0) + +// +// This structure must be cared byte-ordering +// +// Added by tynli. 2009.12.04. +typedef struct _RT_8188F_FIRMWARE_HDR +{ + // 8-byte alinment required + + //--- LONG WORD 0 ---- + u16 Signature; // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut + u8 Category; // AP/NIC and USB/PCI + u8 Function; // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions + u16 Version; // FW Version + u16 Subversion; // FW Subversion, default 0x00 + + //--- LONG WORD 1 ---- + u8 Month; // Release time Month field + u8 Date; // Release time Date field + u8 Hour; // Release time Hour field + u8 Minute; // Release time Minute field + u16 RamCodeSize; // The size of RAM code + u16 Rsvd2; + + //--- LONG WORD 2 ---- + u32 SvnIdx; // The SVN entry index + u32 Rsvd3; + + //--- LONG WORD 3 ---- + u32 Rsvd4; + u32 Rsvd5; +}RT_8188F_FIRMWARE_HDR, *PRT_8188F_FIRMWARE_HDR; + +#define DRIVER_EARLY_INT_TIME_8188F 0x05 +#define BCN_DMA_ATIME_INT_TIME_8188F 0x02 + +// for 8188F +// TX 32K, RX 16K, Page size 128B for TX, 8B for RX +#define PAGE_SIZE_TX_8188F 128 +#define PAGE_SIZE_RX_8188F 8 + +#define RX_DMA_SIZE_8188F 0x4000 // 16K +#ifdef CONFIG_FW_C2H_DEBUG +#define RX_DMA_RESERVED_SIZE_8188F 0x100 // 256B, reserved for c2h debug message +#else +#define RX_DMA_RESERVED_SIZE_8188F 0x80 // 128B, reserved for tx report +#endif + +#define RESV_FMWF 0 + +#define RX_DMA_BOUNDARY_8188F (RX_DMA_SIZE_8188F - RX_DMA_RESERVED_SIZE_8188F - 1) + +// Note: We will divide number of page equally for each queue other than public queue! + +//For General Reserved Page Number(Beacon Queue is reserved page) +//Beacon:2, PS-Poll:1, Null Data:1,Qos Null Data:1,BT Qos Null Data:1 +#define BCNQ_PAGE_NUM_8188F 0x08 +#ifdef CONFIG_CONCURRENT_MODE +#define BCNQ1_PAGE_NUM_8188F 0x08 // 0x04 +#else +#define BCNQ1_PAGE_NUM_8188F 0x00 +#endif + +#ifdef CONFIG_PNO_SUPPORT +#undef BCNQ1_PAGE_NUM_8188F +#define BCNQ1_PAGE_NUM_8188F 0x00 // 0x04 +#endif + +//For WoWLan , more reserved page +//ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, PNO: 6 +#define WOWLAN_PAGE_NUM_8188F 0x00 + +#ifdef CONFIG_PNO_SUPPORT +#undef WOWLAN_PAGE_NUM_8188F +#define WOWLAN_PAGE_NUM_8188F 0x15 +#endif + +#define TX_TOTAL_PAGE_NUMBER_8188F (0xFF - BCNQ_PAGE_NUM_8188F - BCNQ1_PAGE_NUM_8188F - WOWLAN_PAGE_NUM_8188F) +#define TX_PAGE_BOUNDARY_8188F (TX_TOTAL_PAGE_NUMBER_8188F + 1) + +#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8188F TX_TOTAL_PAGE_NUMBER_8188F +#define WMM_NORMAL_TX_PAGE_BOUNDARY_8188F (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER_8188F + 1) + +// For Normal Chip Setting +// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_8188F +#define NORMAL_PAGE_NUM_HPQ_8188F 0x0C +#define NORMAL_PAGE_NUM_LPQ_8188F 0x02 +#define NORMAL_PAGE_NUM_NPQ_8188F 0x02 + +// Note: For Normal Chip Setting, modify later +#define WMM_NORMAL_PAGE_NUM_HPQ_8188F 0x30 +#define WMM_NORMAL_PAGE_NUM_LPQ_8188F 0x20 +#define WMM_NORMAL_PAGE_NUM_NPQ_8188F 0x20 + + +#include "HalVerDef.h" +#include "hal_com.h" + +#define EFUSE_OOB_PROTECT_BYTES (34 + 1) + +#define HAL_EFUSE_MEMORY + +#define HWSET_MAX_SIZE_8188F 512 +#define EFUSE_REAL_CONTENT_LEN_8188F 256 +#define EFUSE_MAP_LEN_8188F 512 +#define EFUSE_MAX_SECTION_8188F (EFUSE_MAP_LEN_8188F / 8) + +#define EFUSE_IC_ID_OFFSET 506 //For some inferiority IC purpose. added by Roger, 2009.09.02. +#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN_8188F) + +#define EFUSE_ACCESS_ON 0x69 // For RTL8188 only. +#define EFUSE_ACCESS_OFF 0x00 // For RTL8188 only. + +//======================================================== +// EFUSE for BT definition +//======================================================== +#define EFUSE_BT_REAL_BANK_CONTENT_LEN 512 +#define EFUSE_BT_REAL_CONTENT_LEN 1536 // 512*3 +#define EFUSE_BT_MAP_LEN 1024 // 1k bytes +#define EFUSE_BT_MAX_SECTION 128 // 1024/8 + +#define EFUSE_PROTECT_BYTES_BANK 16 + +typedef struct _C2H_EVT_HDR +{ + u8 CmdID; + u8 CmdLen; + u8 CmdSeq; +} __attribute__((__packed__)) C2H_EVT_HDR, *PC2H_EVT_HDR; + +#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT) +#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS) + +// rtl8188a_hal_init.c +s32 rtl8188f_FirmwareDownload(PADAPTER padapter, BOOLEAN bUsedWoWLANFw); +void rtl8188f_FirmwareSelfReset(PADAPTER padapter); +void rtl8188f_InitializeFirmwareVars(PADAPTER padapter); + +void rtl8188f_InitAntenna_Selection(PADAPTER padapter); +void rtl8188f_DeinitAntenna_Selection(PADAPTER padapter); +void rtl8188f_CheckAntenna_Selection(PADAPTER padapter); +void rtl8188f_init_default_value(PADAPTER padapter); + +s32 rtl8188f_InitLLTTable(PADAPTER padapter); + +s32 CardDisableHWSM(PADAPTER padapter, u8 resetMCU); +s32 CardDisableWithoutHWSM(PADAPTER padapter); + +// EFuse +u8 GetEEPROMSize8188F(PADAPTER padapter); +void Hal_InitPGData(PADAPTER padapter, u8 *PROMContent); +void Hal_EfuseParseIDCode(PADAPTER padapter, u8 *hwinfo); +void Hal_EfuseParseTxPowerInfo_8188F(PADAPTER padapter, u8 *PROMContent, BOOLEAN AutoLoadFail); +/* void Hal_EfuseParseBTCoexistInfo_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); */ +void Hal_EfuseParseEEPROMVer_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); +void Hal_EfuseParseChnlPlan_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); +void Hal_EfuseParseCustomerID_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); +void Hal_EfuseParsePowerSavingMode_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); +void Hal_EfuseParseAntennaDiversity_8188F(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); +void Hal_EfuseParseXtal_8188F(PADAPTER pAdapter, u8 *hwinfo, u8 AutoLoadFail); +void Hal_EfuseParseThermalMeter_8188F(PADAPTER padapter, u8 *hwinfo, u8 AutoLoadFail); +void Hal_EfuseParseKFreeData_8188F(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); + +#if 0 /* Do not need for rtl8188f */ +VOID Hal_EfuseParseVoltage_8188F(PADAPTER pAdapter,u8* hwinfo,BOOLEAN AutoLoadFail); +#endif + +#ifdef CONFIG_C2H_PACKET_EN +void rtl8188f_c2h_packet_handler(PADAPTER padapter, u8 *pbuf, u16 length); +#endif + +void rtl8188f_set_pll_ref_clk_sel(_adapter *adapter, u8 sel); + +void rtl8188f_set_hal_ops(struct hal_ops *pHalFunc); +void init_hal_spec_8188f(_adapter *adapter); +void SetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val); +void GetHwReg8188F(PADAPTER padapter, u8 variable, u8 *val); +#ifdef CONFIG_C2H_PACKET_EN +void SetHwRegWithBuf8188F(PADAPTER padapter, u8 variable, u8 *pbuf, int len); +#endif // CONFIG_C2H_PACKET_EN +u8 SetHalDefVar8188F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); +u8 GetHalDefVar8188F(PADAPTER padapter, HAL_DEF_VARIABLE variable, void *pval); + +// register +void rtl8188f_InitBeaconParameters(PADAPTER padapter); +void rtl8188f_InitBeaconMaxError(PADAPTER padapter, u8 InfraMode); +void _InitBurstPktLen_8188FS(PADAPTER Adapter); +void _8051Reset8188(PADAPTER padapter); + +void rtl8188f_start_thread(_adapter *padapter); +void rtl8188f_stop_thread(_adapter *padapter); + +#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST) +void rtl8188fs_init_checkbthang_workqueue(_adapter * adapter); +void rtl8188fs_free_checkbthang_workqueue(_adapter * adapter); +void rtl8188fs_cancle_checkbthang_workqueue(_adapter * adapter); +void rtl8188fs_hal_check_bt_hang(_adapter * adapter); +#endif + +#ifdef CONFIG_GPIO_WAKEUP +void HalSetOutPutGPIO(PADAPTER padapter, u8 index, u8 OutPutValue); +#endif + +int FirmwareDownloadBT(IN PADAPTER Adapter, PRT_MP_FIRMWARE pFirmware); + +void CCX_FwC2HTxRpt_8188f(PADAPTER padapter, u8 *pdata, u8 len); +#ifdef CONFIG_FW_C2H_DEBUG +void Debug_FwC2H_8188f(PADAPTER padapter, u8 *pdata, u8 len); +#endif //CONFIG_FW_C2H_DEBUG +s32 c2h_id_filter_ccx_8188f(u8 *buf); +s32 c2h_handler_8188f(PADAPTER padapter, u8 *pC2hEvent); +u8 MRateToHwRate8188F(u8 rate); +u8 HwRateToMRate8188F(u8 rate); + +#ifdef CONFIG_PCI_HCI +BOOLEAN InterruptRecognized8188FE(PADAPTER Adapter); +VOID UpdateInterruptMask8188FE(PADAPTER Adapter, u32 AddMSR, u32 AddMSR1, u32 RemoveMSR, u32 RemoveMSR1); +#endif + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_led.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_led.h new file mode 100644 index 000000000..9b7bf78c5 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_led.h @@ -0,0 +1,49 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTL8188F_LED_H__ +#define __RTL8188F_LED_H__ + +#include +#include +#include + + +//================================================================================ +// Interface to manipulate LED objects. +//================================================================================ +#ifdef CONFIG_USB_HCI +void rtl8188fu_InitSwLeds(PADAPTER padapter); +void rtl8188fu_DeInitSwLeds(PADAPTER padapter); +#endif +#ifdef CONFIG_SDIO_HCI +void rtl8188fs_InitSwLeds(PADAPTER padapter); +void rtl8188fs_DeInitSwLeds(PADAPTER padapter); +#endif +#ifdef CONFIG_GSPI_HCI +void rtl8188fs_InitSwLeds(PADAPTER padapter); +void rtl8188fs_DeInitSwLeds(PADAPTER padapter); +#endif +#ifdef CONFIG_PCI_HCI +void rtl8188fe_InitSwLeds(PADAPTER padapter); +void rtl8188fe_DeInitSwLeds(PADAPTER padapter); +#endif + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_recv.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_recv.h new file mode 100644 index 000000000..8a1228cd5 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_recv.h @@ -0,0 +1,73 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTL8188F_RECV_H__ +#define __RTL8188F_RECV_H__ + +#if defined(CONFIG_USB_HCI) + #ifndef MAX_RECVBUF_SZ + #ifdef PLATFORM_OS_CE + #define MAX_RECVBUF_SZ (8192+1024) // 8K+1k + #else + #ifdef CONFIG_MINIMAL_MEMORY_USAGE + #define MAX_RECVBUF_SZ (4000) // about 4K + #else + #ifdef CONFIG_PLATFORM_MSTAR + #define MAX_RECVBUF_SZ (8192) // 8K + #elif defined(CONFIG_PLATFORM_HISILICON) + #define MAX_RECVBUF_SZ (16384) /* 16k */ + #else + #define MAX_RECVBUF_SZ (32768) /* 32k */ + #endif + //#define MAX_RECVBUF_SZ (20480) //20K + //#define MAX_RECVBUF_SZ (10240) //10K + //#define MAX_RECVBUF_SZ (16384) // 16k - 92E RX BUF :16K + //#define MAX_RECVBUF_SZ (8192+1024) // 8K+1k + #endif + #endif + #endif //!MAX_RECVBUF_SZ +#elif defined(CONFIG_PCI_HCI) + #define MAX_RECVBUF_SZ (4000) // about 4K +#elif defined(CONFIG_SDIO_HCI) + #define MAX_RECVBUF_SZ (RX_DMA_BOUNDARY_8188F + 1) +#endif /* CONFIG_SDIO_HCI */ + +// Rx smooth factor +#define Rx_Smooth_Factor (20) + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) +s32 rtl8188fs_init_recv_priv(PADAPTER padapter); +void rtl8188fs_free_recv_priv(PADAPTER padapter); +#endif + +#ifdef CONFIG_USB_HCI +int rtl8188fu_init_recv_priv(_adapter *padapter); +void rtl8188fu_free_recv_priv (_adapter *padapter); +void rtl8188fu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf); +#endif + +#ifdef CONFIG_PCI_HCI +s32 rtl8188fe_init_recv_priv(PADAPTER padapter); +void rtl8188fe_free_recv_priv(PADAPTER padapter); +#endif + +void rtl8188f_query_rx_desc_status(union recv_frame *precvframe, u8 *pdesc); + +#endif /* __RTL8188F_RECV_H__ */ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_rf.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_rf.h new file mode 100644 index 000000000..ea71ef13e --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_rf.h @@ -0,0 +1,31 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTL8188F_RF_H__ +#define __RTL8188F_RF_H__ + +int PHY_RF6052_Config8188F( IN PADAPTER Adapter ); + +VOID +PHY_RF6052SetBandwidth8188F( + IN PADAPTER Adapter, + IN CHANNEL_WIDTH Bandwidth); + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_spec.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_spec.h new file mode 100644 index 000000000..910e5f9c5 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_spec.h @@ -0,0 +1,294 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + *******************************************************************************/ +#ifndef __RTL8188F_SPEC_H__ +#define __RTL8188F_SPEC_H__ + +#include + + +#define HAL_NAV_UPPER_UNIT_8188F 128 // micro-second + +//----------------------------------------------------- +// +// 0x0000h ~ 0x00FFh System Configuration +// +//----------------------------------------------------- +#define REG_RSV_CTRL_8188F 0x001C // 3 Byte +#define REG_BT_WIFI_ANTENNA_SWITCH_8188F 0x0038 +#define REG_HSISR_8188F 0x005c +#define REG_PAD_CTRL1_8188F 0x0064 +#define REG_AFE_CTRL_4_8188F 0x0078 +#define REG_HMEBOX_DBG_0_8188F 0x0088 +#define REG_HMEBOX_DBG_1_8188F 0x008A +#define REG_HMEBOX_DBG_2_8188F 0x008C +#define REG_HMEBOX_DBG_3_8188F 0x008E +#define REG_HIMR0_8188F 0x00B0 +#define REG_HISR0_8188F 0x00B4 +#define REG_HIMR1_8188F 0x00B8 +#define REG_HISR1_8188F 0x00BC +#define REG_PMC_DBG_CTRL2_8188F 0x00CC + +//----------------------------------------------------- +// +// 0x0100h ~ 0x01FFh MACTOP General Configuration +// +//----------------------------------------------------- +#define REG_C2HEVT_CMD_ID_8188F 0x01A0 +#define REG_C2HEVT_CMD_LEN_8188F 0x01AE +#define REG_WOWLAN_WAKE_REASON 0x01C7 +#define REG_WOWLAN_GTK_DBG1 0x630 +#define REG_WOWLAN_GTK_DBG2 0x634 + +#define REG_HMEBOX_EXT0_8188F 0x01F0 +#define REG_HMEBOX_EXT1_8188F 0x01F4 +#define REG_HMEBOX_EXT2_8188F 0x01F8 +#define REG_HMEBOX_EXT3_8188F 0x01FC + +//----------------------------------------------------- +// +// 0x0200h ~ 0x027Fh TXDMA Configuration +// +//----------------------------------------------------- + +//----------------------------------------------------- +// +// 0x0280h ~ 0x02FFh RXDMA Configuration +// +//----------------------------------------------------- +#define REG_RXDMA_CONTROL_8188F 0x0286 // Control the RX DMA. +#define REG_RXDMA_MODE_CTRL_8188F 0x0290 + +//----------------------------------------------------- +// +// 0x0300h ~ 0x03FFh PCIe +// +//----------------------------------------------------- +#define REG_PCIE_CTRL_REG_8188F 0x0300 +#define REG_INT_MIG_8188F 0x0304 // Interrupt Migration +#define REG_BCNQ_DESA_8188F 0x0308 // TX Beacon Descriptor Address +#define REG_HQ_DESA_8188F 0x0310 // TX High Queue Descriptor Address +#define REG_MGQ_DESA_8188F 0x0318 // TX Manage Queue Descriptor Address +#define REG_VOQ_DESA_8188F 0x0320 // TX VO Queue Descriptor Address +#define REG_VIQ_DESA_8188F 0x0328 // TX VI Queue Descriptor Address +#define REG_BEQ_DESA_8188F 0x0330 // TX BE Queue Descriptor Address +#define REG_BKQ_DESA_8188F 0x0338 // TX BK Queue Descriptor Address +#define REG_RX_DESA_8188F 0x0340 // RX Queue Descriptor Address +#define REG_DBI_WDATA_8188F 0x0348 // DBI Write Data +#define REG_DBI_RDATA_8188F 0x034C // DBI Read Data +#define REG_DBI_ADDR_8188F 0x0350 // DBI Address +#define REG_DBI_FLAG_8188F 0x0352 // DBI Read/Write Flag +#define REG_MDIO_WDATA_8188F 0x0354 // MDIO for Write PCIE PHY +#define REG_MDIO_RDATA_8188F 0x0356 // MDIO for Reads PCIE PHY +#define REG_MDIO_CTL_8188F 0x0358 // MDIO for Control +#define REG_DBG_SEL_8188F 0x0360 // Debug Selection Register +#define REG_PCIE_HRPWM_8188F 0x0361 //PCIe RPWM +#define REG_PCIE_HCPWM_8188F 0x0363 //PCIe CPWM +#define REG_PCIE_MULTIFET_CTRL_8188F 0x036A //PCIE Multi-Fethc Control + +//----------------------------------------------------- +// +// 0x0400h ~ 0x047Fh Protocol Configuration +// +//----------------------------------------------------- +#define REG_TXPKTBUF_BCNQ_BDNY_8188F 0x0424 +#define REG_TXPKTBUF_MGQ_BDNY_8188F 0x0425 +#define REG_TXPKTBUF_WMAC_LBK_BF_HD_8188F 0x045D +#define REG_AMPDU_BURST_MODE_8188F 0x04BC + +//----------------------------------------------------- +// +// 0x0500h ~ 0x05FFh EDCA Configuration +// +//----------------------------------------------------- +#define REG_SECONDARY_CCA_CTRL_8188F 0x0577 + +//----------------------------------------------------- +// +// 0x0600h ~ 0x07FFh WMAC Configuration +// +//----------------------------------------------------- + + +//============================================================ +// SDIO Bus Specification +//============================================================ + +//----------------------------------------------------- +// SDIO CMD Address Mapping +//----------------------------------------------------- + +//----------------------------------------------------- +// I/O bus domain (Host) +//----------------------------------------------------- + +//----------------------------------------------------- +// SDIO register +//----------------------------------------------------- +#define SDIO_REG_HIQ_FREEPG_8188F 0x0020 +#define SDIO_REG_MID_FREEPG_8188F 0x0022 +#define SDIO_REG_LOW_FREEPG_8188F 0x0024 +#define SDIO_REG_PUB_FREEPG_8188F 0x0026 +#define SDIO_REG_EXQ_FREEPG_8188F 0x0028 +#define SDIO_REG_AC_OQT_FREEPG_8188F 0x002A +#define SDIO_REG_NOAC_OQT_FREEPG_8188F 0x002B + +#define SDIO_REG_HCPWM1_8188F 0x0038 + +/* indirect access */ +#define SDIO_REG_INDIRECT_REG_CFG_8188F 0x40 +#define SET_INDIRECT_REG_ADDR(_cmd, _addr) SET_BITS_TO_LE_2BYTE(((u8 *)(_cmd)) + 0, 0, 16, (_addr)) +#define SET_INDIRECT_REG_SIZE_1BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 0) +#define SET_INDIRECT_REG_SIZE_2BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 1) +#define SET_INDIRECT_REG_SIZE_4BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 2) +#define SET_INDIRECT_REG_WRITE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 2, 1, 1) +#define SET_INDIRECT_REG_READ(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 3, 1, 1) +#define GET_INDIRECT_REG_RDY(_cmd) LE_BITS_TO_1BYTE(((u8 *)(_cmd)) + 2, 4, 1) + +#define SDIO_REG_INDIRECT_REG_DATA_8188F 0x44 + +//============================================================================ +// 8188 Regsiter Bit and Content definition +//============================================================================ + +//2 HSISR +// interrupt mask which needs to clear +#define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\ + HSISR_SPS_OCP_INT |\ + HSISR_RON_INT |\ + HSISR_PDNINT |\ + HSISR_GPIO9_INT) + +//----------------------------------------------------- +// +// 0x0100h ~ 0x01FFh MACTOP General Configuration +// +//----------------------------------------------------- + + +//----------------------------------------------------- +// +// 0x0200h ~ 0x027Fh TXDMA Configuration +// +//----------------------------------------------------- + +//----------------------------------------------------- +// +// 0x0280h ~ 0x02FFh RXDMA Configuration +// +//----------------------------------------------------- +#define BIT_USB_RXDMA_AGG_EN BIT(31) +#define RXDMA_AGG_MODE_EN BIT(1) +#define BIT_DMA_MODE BIT(1) + +//----------------------------------------------------- +// +// 0x0400h ~ 0x047Fh Protocol Configuration +// +//----------------------------------------------------- + +//---------------------------------------------------------------------------- +// 8188F REG_CCK_CHECK (offset 0x454) +//---------------------------------------------------------------------------- +#define BIT_BCN_PORT_SEL BIT5 + +//----------------------------------------------------- +// +// 0x0500h ~ 0x05FFh EDCA Configuration +// +//----------------------------------------------------- + +//----------------------------------------------------- +// +// 0x0600h ~ 0x07FFh WMAC Configuration +// +//----------------------------------------------------- + +//---------------------------------------------------------------------------- +// 8195 IMR/ISR bits (offset 0xB0, 8bits) +//---------------------------------------------------------------------------- +#define IMR_DISABLED_8188F 0 +// IMR DW0(0x00B0-00B3) Bit 0-31 +#define IMR_TIMER2_8188F BIT31 // Timeout interrupt 2 +#define IMR_TIMER1_8188F BIT30 // Timeout interrupt 1 +#define IMR_PSTIMEOUT_8188F BIT29 // Power Save Time Out Interrupt +#define IMR_GTINT4_8188F BIT28 // When GTIMER4 expires, this bit is set to 1 +#define IMR_GTINT3_8188F BIT27 // When GTIMER3 expires, this bit is set to 1 +#define IMR_TXBCN0ERR_8188F BIT26 // Transmit Beacon0 Error +#define IMR_TXBCN0OK_8188F BIT25 // Transmit Beacon0 OK +#define IMR_TSF_BIT32_TOGGLE_8188F BIT24 // TSF Timer BIT32 toggle indication interrupt +#define IMR_BCNDMAINT0_8188F BIT20 // Beacon DMA Interrupt 0 +#define IMR_BCNDERR0_8188F BIT16 // Beacon Queue DMA OK0 +#define IMR_HSISR_IND_ON_INT_8188F BIT15 // HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) +#define IMR_BCNDMAINT_E_8188F BIT14 // Beacon DMA Interrupt Extension for Win7 +#define IMR_ATIMEND_8188F BIT12 // CTWidnow End or ATIM Window End +#define IMR_C2HCMD_8188F BIT10 // CPU to Host Command INT Status, Write 1 clear +#define IMR_CPWM2_8188F BIT9 // CPU power Mode exchange INT Status, Write 1 clear +#define IMR_CPWM_8188F BIT8 // CPU power Mode exchange INT Status, Write 1 clear +#define IMR_HIGHDOK_8188F BIT7 // High Queue DMA OK +#define IMR_MGNTDOK_8188F BIT6 // Management Queue DMA OK +#define IMR_BKDOK_8188F BIT5 // AC_BK DMA OK +#define IMR_BEDOK_8188F BIT4 // AC_BE DMA OK +#define IMR_VIDOK_8188F BIT3 // AC_VI DMA OK +#define IMR_VODOK_8188F BIT2 // AC_VO DMA OK +#define IMR_RDU_8188F BIT1 // Rx Descriptor Unavailable +#define IMR_ROK_8188F BIT0 // Receive DMA OK + +// IMR DW1(0x00B4-00B7) Bit 0-31 +#define IMR_BCNDMAINT7_8188F BIT27 // Beacon DMA Interrupt 7 +#define IMR_BCNDMAINT6_8188F BIT26 // Beacon DMA Interrupt 6 +#define IMR_BCNDMAINT5_8188F BIT25 // Beacon DMA Interrupt 5 +#define IMR_BCNDMAINT4_8188F BIT24 // Beacon DMA Interrupt 4 +#define IMR_BCNDMAINT3_8188F BIT23 // Beacon DMA Interrupt 3 +#define IMR_BCNDMAINT2_8188F BIT22 // Beacon DMA Interrupt 2 +#define IMR_BCNDMAINT1_8188F BIT21 // Beacon DMA Interrupt 1 +#define IMR_BCNDOK7_8188F BIT20 // Beacon Queue DMA OK Interrup 7 +#define IMR_BCNDOK6_8188F BIT19 // Beacon Queue DMA OK Interrup 6 +#define IMR_BCNDOK5_8188F BIT18 // Beacon Queue DMA OK Interrup 5 +#define IMR_BCNDOK4_8188F BIT17 // Beacon Queue DMA OK Interrup 4 +#define IMR_BCNDOK3_8188F BIT16 // Beacon Queue DMA OK Interrup 3 +#define IMR_BCNDOK2_8188F BIT15 // Beacon Queue DMA OK Interrup 2 +#define IMR_BCNDOK1_8188F BIT14 // Beacon Queue DMA OK Interrup 1 +#define IMR_ATIMEND_E_8188F BIT13 // ATIM Window End Extension for Win7 +#define IMR_TXERR_8188F BIT11 // Tx Error Flag Interrupt Status, write 1 clear. +#define IMR_RXERR_8188F BIT10 // Rx Error Flag INT Status, Write 1 clear +#define IMR_TXFOVW_8188F BIT9 // Transmit FIFO Overflow +#define IMR_RXFOVW_8188F BIT8 // Receive FIFO Overflow + +#ifdef CONFIG_PCI_HCI +//#define IMR_RX_MASK (IMR_ROK_8188F|IMR_RDU_8188F|IMR_RXFOVW_8188F) +#define IMR_TX_MASK (IMR_VODOK_8188F|IMR_VIDOK_8188F|IMR_BEDOK_8188F|IMR_BKDOK_8188F|IMR_MGNTDOK_8188F|IMR_HIGHDOK_8188F) + +#define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8188F | IMR_TXBCN0OK_8188F | IMR_TXBCN0ERR_8188F | IMR_BCNDERR0_8188F) + +#define RT_AC_INT_MASKS (IMR_VIDOK_8188F | IMR_VODOK_8188F | IMR_BEDOK_8188F|IMR_BKDOK_8188F) +#endif + +//======================================================== +// General definitions +//======================================================== + +#define MACID_NUM_8188F 16 +#define SEC_CAM_ENT_NUM_8188F 16 +#define NSS_NUM_8188F 1 +#define BAND_CAP_8188F (BAND_CAP_2G) +#define BW_CAP_8188F (BW_CAP_20M | BW_CAP_40M) +#define PROTO_CAP_8188F (PROTO_CAP_11B|PROTO_CAP_11G|PROTO_CAP_11N) + +#endif /* __RTL8188F_SPEC_H__ */ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_sreset.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_sreset.h new file mode 100644 index 000000000..8a2762415 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_sreset.h @@ -0,0 +1,30 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTL8188F_SRESET_H_ +#define _RTL8188F_SRESET_H_ + +#include + +#ifdef DBG_CONFIG_ERROR_DETECT +extern void rtl8188f_sreset_xmit_status_check(_adapter *padapter); +extern void rtl8188f_sreset_linked_status_check(_adapter *padapter); +#endif +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_xmit.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_xmit.h new file mode 100644 index 000000000..3888ceaa7 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtl8188f_xmit.h @@ -0,0 +1,336 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTL8188F_XMIT_H__ +#define __RTL8188F_XMIT_H__ + + +#define MAX_TID (15) + + +#ifndef __INC_HAL8188FDESC_H +#define __INC_HAL8188FDESC_H + +#define RX_STATUS_DESC_SIZE_8188F 24 +#define RX_DRV_INFO_SIZE_UNIT_8188F 8 + + +//DWORD 0 +#define SET_RX_STATUS_DESC_PKT_LEN_8188F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 0, 14, __Value) +#define SET_RX_STATUS_DESC_EOR_8188F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 30, 1, __Value) +#define SET_RX_STATUS_DESC_OWN_8188F(__pRxStatusDesc, __Value) SET_BITS_TO_LE_4BYTE( __pRxStatusDesc, 31, 1, __Value) + +#define GET_RX_STATUS_DESC_PKT_LEN_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 0, 14) +#define GET_RX_STATUS_DESC_CRC32_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 14, 1) +#define GET_RX_STATUS_DESC_ICV_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 15, 1) +#define GET_RX_STATUS_DESC_DRVINFO_SIZE_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 16, 4) +#define GET_RX_STATUS_DESC_SECURITY_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 20, 3) +#define GET_RX_STATUS_DESC_QOS_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 23, 1) +#define GET_RX_STATUS_DESC_SHIFT_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 24, 2) +#define GET_RX_STATUS_DESC_PHY_STATUS_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 26, 1) +#define GET_RX_STATUS_DESC_SWDEC_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 27, 1) +#define GET_RX_STATUS_DESC_LAST_SEG_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 28, 1) +#define GET_RX_STATUS_DESC_FIRST_SEG_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 29, 1) +#define GET_RX_STATUS_DESC_EOR_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 30, 1) +#define GET_RX_STATUS_DESC_OWN_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc, 31, 1) + +//DWORD 1 +#define GET_RX_STATUS_DESC_MACID_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 0, 7) +#define GET_RX_STATUS_DESC_TID_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 8, 4) +#define GET_RX_STATUS_DESC_AMSDU_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 13, 1) +#define GET_RX_STATUS_DESC_RXID_MATCH_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 14, 1) +#define GET_RX_STATUS_DESC_PAGGR_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 15, 1) +#define GET_RX_STATUS_DESC_A1_FIT_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 16, 4) +#define GET_RX_STATUS_DESC_CHKERR_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 20, 1) +#define GET_RX_STATUS_DESC_IPVER_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 21, 1) +#define GET_RX_STATUS_DESC_IS_TCPUDP__8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 22, 1) +#define GET_RX_STATUS_DESC_CHK_VLD_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+4, 23, 1) +#define GET_RX_STATUS_DESC_PAM_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 24, 1) +#define GET_RX_STATUS_DESC_PWR_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 25, 1) +#define GET_RX_STATUS_DESC_MORE_DATA_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 26, 1) +#define GET_RX_STATUS_DESC_MORE_FRAG_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 27, 1) +#define GET_RX_STATUS_DESC_TYPE_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 28, 2) +#define GET_RX_STATUS_DESC_MC_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 30, 1) +#define GET_RX_STATUS_DESC_BC_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+4, 31, 1) + +//DWORD 2 +#define GET_RX_STATUS_DESC_SEQ_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 0, 12) +#define GET_RX_STATUS_DESC_FRAG_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 12, 4) +#define GET_RX_STATUS_DESC_RX_IS_QOS_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 16, 1) +#define GET_RX_STATUS_DESC_WLANHD_IV_LEN_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 18, 6) +#define GET_RX_STATUS_DESC_RPT_SEL_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+8, 28, 1) + +//DWORD 3 +#define GET_RX_STATUS_DESC_RX_RATE_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 0, 7) +#define GET_RX_STATUS_DESC_HTC_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 10, 1) +#define GET_RX_STATUS_DESC_EOSP_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 11, 1) +#define GET_RX_STATUS_DESC_BSSID_FIT_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 12, 2) +#ifdef CONFIG_USB_RX_AGGREGATION +#define GET_RX_STATUS_DESC_USB_AGG_PKTNUM_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+12, 16, 8) +#endif +#define GET_RX_STATUS_DESC_PATTERN_MATCH_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+12, 29, 1) +#define GET_RX_STATUS_DESC_UNICAST_MATCH_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+12, 30, 1) +#define GET_RX_STATUS_DESC_MAGIC_MATCH_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+12, 31, 1) + +//DWORD 6 +#define GET_RX_STATUS_DESC_SPLCP_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 0, 1) +#define GET_RX_STATUS_DESC_LDPC_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 1, 1) +#define GET_RX_STATUS_DESC_STBC_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 2, 1) +#define GET_RX_STATUS_DESC_BW_8188F(__pRxDesc) LE_BITS_TO_4BYTE( __pRxDesc+16, 4, 2) + +//DWORD 5 +#define GET_RX_STATUS_DESC_TSFL_8188F(__pRxStatusDesc) LE_BITS_TO_4BYTE( __pRxStatusDesc+20, 0, 32) + +#define GET_RX_STATUS_DESC_BUFF_ADDR_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+24, 0, 32) +#define GET_RX_STATUS_DESC_BUFF_ADDR64_8188F(__pRxDesc) LE_BITS_TO_4BYTE(__pRxDesc+28, 0, 32) + +#define SET_RX_STATUS_DESC_BUFF_ADDR_8188F(__pRxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pRxDesc+24, 0, 32, __Value) + + +// Dword 0 +#define GET_TX_DESC_OWN_8188F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc, 31, 1) + +#define SET_TX_DESC_PKT_SIZE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value) +#define SET_TX_DESC_OFFSET_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value) +#define SET_TX_DESC_BMC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value) +#define SET_TX_DESC_HTC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value) +#define SET_TX_DESC_LAST_SEG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value) +#define SET_TX_DESC_FIRST_SEG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value) +#define SET_TX_DESC_LINIP_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value) +#define SET_TX_DESC_NO_ACM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value) +#define SET_TX_DESC_GF_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value) +#define SET_TX_DESC_OWN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value) + +// Dword 1 +#define SET_TX_DESC_MACID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value) +#define SET_TX_DESC_QUEUE_SEL_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value) +#define SET_TX_DESC_RDG_NAV_EXT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value) +#define SET_TX_DESC_LSIG_TXOP_EN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value) +#define SET_TX_DESC_PIFS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value) +#define SET_TX_DESC_RATE_ID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value) +#define SET_TX_DESC_EN_DESC_ID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value) +#define SET_TX_DESC_SEC_TYPE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value) +#define SET_TX_DESC_PKT_OFFSET_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value) + + +// Dword 2 +#define SET_TX_DESC_PAID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0, 9, __Value) +#define SET_TX_DESC_CCA_RTS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value) +#define SET_TX_DESC_AGG_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value) +#define SET_TX_DESC_RDG_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value) +#define SET_TX_DESC_AGG_BREAK_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value) +#define SET_TX_DESC_MORE_FRAG_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value) +#define SET_TX_DESC_RAW_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value) +#define SET_TX_DESC_SPE_RPT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value) +#define SET_TX_DESC_AMPDU_DENSITY_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value) +#define SET_TX_DESC_BT_INT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value) +#define SET_TX_DESC_GID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value) + + +// Dword 3 +#define SET_TX_DESC_WHEADER_LEN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value) +#define SET_TX_DESC_CHK_EN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value) +#define SET_TX_DESC_EARLY_MODE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value) +#define SET_TX_DESC_HWSEQ_SEL_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value) +#define SET_TX_DESC_USE_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value) +#define SET_TX_DESC_DISABLE_RTS_FB_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value) +#define SET_TX_DESC_DISABLE_FB_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value) +#define SET_TX_DESC_CTS2SELF_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value) +#define SET_TX_DESC_RTS_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value) +#define SET_TX_DESC_HW_RTS_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value) +#define SET_TX_DESC_NAV_USE_HDR_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value) +#define SET_TX_DESC_USE_MAX_LEN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value) +#define SET_TX_DESC_MAX_AGG_NUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value) +#define SET_TX_DESC_NDPA_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value) +#define SET_TX_DESC_AMPDU_MAX_TIME_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value) + +// Dword 4 +#define SET_TX_DESC_TX_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value) +#define SET_TX_DESC_DATA_RATE_FB_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value) +#define SET_TX_DESC_RTS_RATE_FB_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value) +#define SET_TX_DESC_RETRY_LIMIT_ENABLE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value) +#define SET_TX_DESC_DATA_RETRY_LIMIT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value) +#define SET_TX_DESC_RTS_RATE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value) + + +// Dword 5 +#define SET_TX_DESC_DATA_SC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value) +#define SET_TX_DESC_DATA_SHORT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value) +#define SET_TX_DESC_DATA_BW_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value) +#define SET_TX_DESC_DATA_LDPC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value) +#define SET_TX_DESC_DATA_STBC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value) +#define SET_TX_DESC_CTROL_STBC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value) +#define SET_TX_DESC_RTS_SHORT_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value) +#define SET_TX_DESC_RTS_SC_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value) + + +// Dword 6 +#define SET_TX_DESC_SW_DEFINE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value) +#define SET_TX_DESC_MBSSID_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value) +#define SET_TX_DESC_ANTSEL_A_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value) +#define SET_TX_DESC_ANTSEL_B_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value) +#define SET_TX_DESC_ANTSEL_C_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value) +#define SET_TX_DESC_ANTSEL_D_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value) + +// Dword 7 +#if(DEV_BUS_TYPE == RT_PCI_INTERFACE) +#define SET_TX_DESC_TX_BUFFER_SIZE_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) +#else +#define SET_TX_DESC_TX_DESC_CHECKSUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value) +#endif +#define SET_TX_DESC_USB_TXAGG_NUM_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value) +#if(DEV_BUS_TYPE == RT_SDIO_INTERFACE) +#define SET_TX_DESC_SDIO_TXSEQ_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value) +#endif + +// Dword 8 +#define SET_TX_DESC_HWSEQ_EN_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value) + +// Dword 9 +#define SET_TX_DESC_SEQ_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value) + +// Dword 10 +#define SET_TX_DESC_TX_BUFFER_ADDRESS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value) +#define GET_TX_DESC_TX_BUFFER_ADDRESS_8188F(__pTxDesc) LE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32) + +// Dword 11 +#define SET_TX_DESC_NEXT_DESC_ADDRESS_8188F(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value) + + +#define SET_EARLYMODE_PKTNUM_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value) +#define SET_EARLYMODE_LEN0_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value) +#define SET_EARLYMODE_LEN1_1_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value) +#define SET_EARLYMODE_LEN1_2_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value) +#define SET_EARLYMODE_LEN2_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15, __Value) +#define SET_EARLYMODE_LEN3_8188F(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value) + +#endif +//----------------------------------------------------------- +// +// Rate +// +//----------------------------------------------------------- +// CCK Rates, TxHT = 0 +#define DESC8188F_RATE1M 0x00 +#define DESC8188F_RATE2M 0x01 +#define DESC8188F_RATE5_5M 0x02 +#define DESC8188F_RATE11M 0x03 + +// OFDM Rates, TxHT = 0 +#define DESC8188F_RATE6M 0x04 +#define DESC8188F_RATE9M 0x05 +#define DESC8188F_RATE12M 0x06 +#define DESC8188F_RATE18M 0x07 +#define DESC8188F_RATE24M 0x08 +#define DESC8188F_RATE36M 0x09 +#define DESC8188F_RATE48M 0x0a +#define DESC8188F_RATE54M 0x0b + +// MCS Rates, TxHT = 1 +#define DESC8188F_RATEMCS0 0x0c +#define DESC8188F_RATEMCS1 0x0d +#define DESC8188F_RATEMCS2 0x0e +#define DESC8188F_RATEMCS3 0x0f +#define DESC8188F_RATEMCS4 0x10 +#define DESC8188F_RATEMCS5 0x11 +#define DESC8188F_RATEMCS6 0x12 +#define DESC8188F_RATEMCS7 0x13 +#define DESC8188F_RATEMCS8 0x14 +#define DESC8188F_RATEMCS9 0x15 +#define DESC8188F_RATEMCS10 0x16 +#define DESC8188F_RATEMCS11 0x17 +#define DESC8188F_RATEMCS12 0x18 +#define DESC8188F_RATEMCS13 0x19 +#define DESC8188F_RATEMCS14 0x1a +#define DESC8188F_RATEMCS15 0x1b +#define DESC8188F_RATEVHTSS1MCS0 0x2c +#define DESC8188F_RATEVHTSS1MCS1 0x2d +#define DESC8188F_RATEVHTSS1MCS2 0x2e +#define DESC8188F_RATEVHTSS1MCS3 0x2f +#define DESC8188F_RATEVHTSS1MCS4 0x30 +#define DESC8188F_RATEVHTSS1MCS5 0x31 +#define DESC8188F_RATEVHTSS1MCS6 0x32 +#define DESC8188F_RATEVHTSS1MCS7 0x33 +#define DESC8188F_RATEVHTSS1MCS8 0x34 +#define DESC8188F_RATEVHTSS1MCS9 0x35 +#define DESC8188F_RATEVHTSS2MCS0 0x36 +#define DESC8188F_RATEVHTSS2MCS1 0x37 +#define DESC8188F_RATEVHTSS2MCS2 0x38 +#define DESC8188F_RATEVHTSS2MCS3 0x39 +#define DESC8188F_RATEVHTSS2MCS4 0x3a +#define DESC8188F_RATEVHTSS2MCS5 0x3b +#define DESC8188F_RATEVHTSS2MCS6 0x3c +#define DESC8188F_RATEVHTSS2MCS7 0x3d +#define DESC8188F_RATEVHTSS2MCS8 0x3e +#define DESC8188F_RATEVHTSS2MCS9 0x3f + + +#define RX_HAL_IS_CCK_RATE_8188F(pDesc)\ + (GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE1M ||\ + GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE2M ||\ + GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE5_5M ||\ + GET_RX_STATUS_DESC_RX_RATE_8188F(pDesc) == DESC8188F_RATE11M) + + +void rtl8188f_update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem); +void rtl8188f_fill_fake_txdesc(PADAPTER padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame); + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) +s32 rtl8188fs_init_xmit_priv(PADAPTER padapter); +void rtl8188fs_free_xmit_priv(PADAPTER padapter); +s32 rtl8188fs_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); +s32 rtl8188fs_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); +s32 rtl8188fs_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); +s32 rtl8188fs_xmit_buf_handler(PADAPTER padapter); +thread_return rtl8188fs_xmit_thread(thread_context context); +#define hal_xmit_handler rtl8188fs_xmit_buf_handler +#endif + +#ifdef CONFIG_USB_HCI +s32 rtl8188fu_xmit_buf_handler(PADAPTER padapter); +#define hal_xmit_handler rtl8188fu_xmit_buf_handler + + +s32 rtl8188fu_init_xmit_priv(PADAPTER padapter); +void rtl8188fu_free_xmit_priv(PADAPTER padapter); +s32 rtl8188fu_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); +s32 rtl8188fu_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); +s32 rtl8188fu_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); +//s32 rtl8812au_xmit_buf_handler(PADAPTER padapter); +void rtl8188fu_xmit_tasklet(unsigned long priv); +s32 rtl8188fu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); +void _dbg_dump_tx_info(_adapter *padapter,int frame_tag,struct tx_desc *ptxdesc); +#endif + +#ifdef CONFIG_PCI_HCI +s32 rtl8188fe_init_xmit_priv(PADAPTER padapter); +void rtl8188fe_free_xmit_priv(PADAPTER padapter); +struct xmit_buf *rtl8188fe_dequeue_xmitbuf(struct rtw_tx_ring *ring); +void rtl8188fe_xmitframe_resume(_adapter *padapter); +s32 rtl8188fe_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe); +s32 rtl8188fe_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe); +s32 rtl8188fe_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); +void rtl8188fe_xmit_tasklet(void *priv); +#endif + +u8 BWMapping_8188F(PADAPTER Adapter, struct pkt_attrib *pattrib); +u8 SCMapping_8188F(PADAPTER Adapter, struct pkt_attrib *pattrib); + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_ap.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_ap.h new file mode 100644 index 000000000..f8246c673 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_ap.h @@ -0,0 +1,80 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_AP_H_ +#define __RTW_AP_H_ + + +#ifdef CONFIG_AP_MODE + +//external function +extern void rtw_indicate_sta_assoc_event(_adapter *padapter, struct sta_info *psta); +extern void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info *psta); + + +void init_mlme_ap_info(_adapter *padapter); +void free_mlme_ap_info(_adapter *padapter); +//void update_BCNTIM(_adapter *padapter); +void rtw_add_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index, u8 *data, u8 len); +void rtw_remove_bcn_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 index); +void _update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx, const char *tag); +#define update_beacon(adapter, ie_id, oui, tx) _update_beacon((adapter), (ie_id), (oui), (tx), __func__) +void add_RATid(_adapter *padapter, struct sta_info *psta, u8 rssi_level); +void expire_timeout_chk(_adapter *padapter); +void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta); +void rtw_start_bss_hdl_after_chbw_decided(_adapter *adapter); +void start_bss_network(_adapter *padapter, struct createbss_parm *parm); +int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len); +void rtw_ap_restore_network(_adapter *padapter); +void rtw_set_macaddr_acl(_adapter *padapter, int mode); +int rtw_acl_add_sta(_adapter *padapter, u8 *addr); +int rtw_acl_remove_sta(_adapter *padapter, u8 *addr); + +u8 rtw_ap_set_pairwise_key(_adapter *padapter, struct sta_info *psta); +int rtw_ap_set_group_key(_adapter *padapter, u8 *key, u8 alg, int keyid); +int rtw_ap_set_wep_key(_adapter *padapter, u8 *key, u8 keylen, int keyid, u8 set_tx); + +#ifdef CONFIG_NATIVEAP_MLME +void associated_clients_update(_adapter *padapter, u8 updated, u32 sta_info_type); +void bss_cap_update_on_sta_join(_adapter *padapter, struct sta_info *psta); +u8 bss_cap_update_on_sta_leave(_adapter *padapter, struct sta_info *psta); +void sta_info_update(_adapter *padapter, struct sta_info *psta); +void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta); +u8 ap_free_sta(_adapter *padapter, struct sta_info *psta, bool active, u16 reason, bool enqueue); +int rtw_sta_flush(_adapter *padapter, bool enqueue); +int rtw_ap_inform_ch_switch(_adapter *padapter, u8 new_ch, u8 ch_offset); +void start_ap_mode(_adapter *padapter); +void stop_ap_mode(_adapter *padapter); +#endif + +void rtw_ap_update_bss_chbw(_adapter *adapter, WLAN_BSSID_EX *bss, u8 ch, u8 bw, u8 offset); +bool rtw_ap_chbw_decision(_adapter *adapter, u8 req_ch, u8 req_bw, u8 req_offset, u8 *ch, u8 *bw, u8 *offset); + +#ifdef CONFIG_AUTO_AP_MODE +extern void rtw_start_auto_ap(_adapter *adapter); +#endif //CONFIG_AUTO_AP_MODE + +#endif //end of CONFIG_AP_MODE + +#endif +void update_bmc_sta(_adapter *padapter); + +void rtw_process_ht_action_smps(_adapter *padapter, u8 *ta, u8 ctrl_field); +void rtw_process_public_act_bsscoex(_adapter *padapter, u8 *pframe, uint frame_len); + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_beamforming.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_beamforming.h new file mode 100644 index 000000000..fde61003d --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_beamforming.h @@ -0,0 +1,150 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_BEAMFORMING_H_ +#define __RTW_BEAMFORMING_H_ + +#ifdef CONFIG_BEAMFORMING + +#if (BEAMFORMING_SUPPORT == 0) /*for diver defined beamforming*/ +#define BEAMFORMING_ENTRY_NUM 2 +#define GET_BEAMFORM_INFO(_pmlmepriv) ((struct beamforming_info *)(&(_pmlmepriv)->beamforming_info)) + + +typedef enum _BEAMFORMING_ENTRY_STATE +{ + BEAMFORMING_ENTRY_STATE_UNINITIALIZE, + BEAMFORMING_ENTRY_STATE_INITIALIZEING, + BEAMFORMING_ENTRY_STATE_INITIALIZED, + BEAMFORMING_ENTRY_STATE_PROGRESSING, + BEAMFORMING_ENTRY_STATE_PROGRESSED, +}BEAMFORMING_ENTRY_STATE, *PBEAMFORMING_ENTRY_STATE; + + +typedef enum _BEAMFORMING_STATE +{ + BEAMFORMING_STATE_IDLE, + BEAMFORMING_STATE_START, + BEAMFORMING_STATE_END, +}BEAMFORMING_STATE, *PBEAMFORMING_STATE; + + +typedef enum _BEAMFORMING_CAP +{ + BEAMFORMING_CAP_NONE = 0x0, + BEAMFORMER_CAP_HT_EXPLICIT = 0x1, + BEAMFORMEE_CAP_HT_EXPLICIT = 0x2, + BEAMFORMER_CAP_VHT_SU = 0x4, // Self has er Cap, because Reg er & peer ee + BEAMFORMEE_CAP_VHT_SU = 0x8, // Self has ee Cap, because Reg ee & peer er + BEAMFORMER_CAP = 0x10, + BEAMFORMEE_CAP = 0x20, +}BEAMFORMING_CAP, *PBEAMFORMING_CAP; + + +typedef enum _SOUNDING_MODE +{ + SOUNDING_SW_VHT_TIMER = 0x0, + SOUNDING_SW_HT_TIMER = 0x1, + SOUNDING_STOP_All_TIMER = 0x2, + SOUNDING_HW_VHT_TIMER = 0x3, + SOUNDING_HW_HT_TIMER = 0x4, + SOUNDING_STOP_OID_TIMER = 0x5, + SOUNDING_AUTO_VHT_TIMER = 0x6, + SOUNDING_AUTO_HT_TIMER = 0x7, + SOUNDING_FW_VHT_TIMER = 0x8, + SOUNDING_FW_HT_TIMER = 0x9, +}SOUNDING_MODE, *PSOUNDING_MODE; + +struct beamforming_entry { + BOOLEAN bUsed; + BOOLEAN bSound; + u16 aid; // Used to construct AID field of NDPA packet. + u16 mac_id; // Used to Set Reg42C in IBSS mode. + u16 p_aid; // Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. + u16 g_id; + u8 mac_addr[6];// Used to fill Reg6E4 to fill Mac address of CSI report frame. + CHANNEL_WIDTH sound_bw; // Sounding BandWidth + u16 sound_period; + BEAMFORMING_CAP beamforming_entry_cap; + BEAMFORMING_ENTRY_STATE beamforming_entry_state; + u8 ClockResetTimes; /*Modified by Jeffery @2015-04-10*/ + u8 PreLogSeq; /*Modified by Jeffery @2015-03-30*/ + u8 LogSeq; /*Modified by Jeffery @2014-10-29*/ + u16 LogRetryCnt:3; /*Modified by Jeffery @2014-10-29*/ + u16 LogSuccess:2; /*Modified by Jeffery @2014-10-29*/ + + u8 LogStatusFailCnt; + u8 PreCsiReport[327]; + u8 DefaultCsiCnt; + BOOLEAN bDefaultCSI; +}; + +struct sounding_info { + u8 sound_idx; + CHANNEL_WIDTH sound_bw; + SOUNDING_MODE sound_mode; + u16 sound_period; +}; + +struct beamforming_info { + BEAMFORMING_CAP beamforming_cap; + BEAMFORMING_STATE beamforming_state; + struct beamforming_entry beamforming_entry[BEAMFORMING_ENTRY_NUM]; + u8 beamforming_cur_idx; + u8 beamforming_in_progress; + u8 sounding_sequence; + struct sounding_info sounding_info; +}; + +struct rtw_ndpa_sta_info { + u16 aid:12; + u16 feedback_type:1; + u16 nc_index:3; +}; + +BEAMFORMING_CAP beamforming_get_entry_beam_cap_by_mac_id(PVOID pmlmepriv ,u8 mac_id); +void beamforming_notify(PADAPTER adapter); +BEAMFORMING_CAP beamforming_get_beamform_cap(struct beamforming_info *pBeamInfo); + +BOOLEAN beamforming_send_ht_ndpa_packet(PADAPTER Adapter, u8 *ra, CHANNEL_WIDTH bw, u8 qidx); +BOOLEAN beamforming_send_vht_ndpa_packet(PADAPTER Adapter, u8 *ra, u16 aid, CHANNEL_WIDTH bw, u8 qidx); + +void beamforming_check_sounding_success(PADAPTER Adapter,BOOLEAN status); + +void beamforming_watchdog(PADAPTER Adapter); +#endif /*#if (BEAMFORMING_SUPPORT ==0)- for diver defined beamforming*/ + +enum BEAMFORMING_CTRL_TYPE { + BEAMFORMING_CTRL_ENTER = 0, + BEAMFORMING_CTRL_LEAVE = 1, + BEAMFORMING_CTRL_START_PERIOD = 2, + BEAMFORMING_CTRL_END_PERIOD = 3, + BEAMFORMING_CTRL_SOUNDING_FAIL = 4, + BEAMFORMING_CTRL_SOUNDING_CLK = 5, +}; +u32 beamforming_get_report_frame(PADAPTER Adapter, union recv_frame *precv_frame); +void beamforming_get_ndpa_frame(PADAPTER Adapter, union recv_frame *precv_frame); + +void beamforming_wk_hdl(_adapter *padapter, u8 type, u8 *pbuf); +u8 beamforming_wk_cmd(_adapter*padapter, s32 type, u8 *pbuf, s32 size, u8 enqueue); +void update_attrib_txbf_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta); + +#endif /*#ifdef CONFIG_BEAMFORMING */ + +#endif /*__RTW_BEAMFORMING_H_*/ diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_br_ext.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_br_ext.h new file mode 100644 index 000000000..dcb51014a --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_br_ext.h @@ -0,0 +1,76 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_BR_EXT_H_ +#define _RTW_BR_EXT_H_ + +#if 1 // rtw_wifi_driver +#define CL_IPV6_PASS 1 +#define MACADDRLEN 6 +#define _DEBUG_ERR DBG_8192C +#define _DEBUG_INFO //DBG_8192C +#define DEBUG_WARN DBG_8192C +#define DEBUG_INFO //DBG_8192C +#define DEBUG_ERR DBG_8192C +//#define GET_MY_HWADDR ((GET_MIB(priv))->dot11OperationEntry.hwaddr) +#define GET_MY_HWADDR(padapter) (adapter_mac_addr(padapter)) +#endif // rtw_wifi_driver + +#define NAT25_HASH_BITS 4 +#define NAT25_HASH_SIZE (1 << NAT25_HASH_BITS) +#define NAT25_AGEING_TIME 300 + +#ifdef CL_IPV6_PASS +#define MAX_NETWORK_ADDR_LEN 17 +#else +#define MAX_NETWORK_ADDR_LEN 11 +#endif + +struct nat25_network_db_entry +{ + struct nat25_network_db_entry *next_hash; + struct nat25_network_db_entry **pprev_hash; + atomic_t use_count; + unsigned char macAddr[6]; + unsigned long ageing_timer; + unsigned char networkAddr[MAX_NETWORK_ADDR_LEN]; +}; + +enum NAT25_METHOD { + NAT25_MIN, + NAT25_CHECK, + NAT25_INSERT, + NAT25_LOOKUP, + NAT25_PARSE, + NAT25_MAX +}; + +struct br_ext_info { + unsigned int nat25_disable; + unsigned int macclone_enable; + unsigned int dhcp_bcst_disable; + int addPPPoETag; // 1: Add PPPoE relay-SID, 0: disable + unsigned char nat25_dmzMac[MACADDRLEN]; + unsigned int nat25sc_disable; +}; + +void nat25_db_cleanup(_adapter *priv); + +#endif // _RTW_BR_EXT_H_ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_bt_mp.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_bt_mp.h new file mode 100644 index 000000000..4624ccd9e --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_bt_mp.h @@ -0,0 +1,295 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef __RTW_BT_MP_H +#define __RTW_BT_MP_H + + +#if(MP_DRIVER == 1) + +#pragma pack(1) + +// definition for BT_UP_OP_BT_READY +#define MP_BT_NOT_READY 0 +#define MP_BT_READY 1 + +// definition for BT_UP_OP_BT_SET_MODE +typedef enum _MP_BT_MODE{ + MP_BT_MODE_RF_TXRX_TEST_MODE = 0, + MP_BT_MODE_BT20_DUT_TEST_MODE = 1, + MP_BT_MODE_BT40_DIRECT_TEST_MODE = 2, + MP_BT_MODE_CONNECT_TEST_MODE = 3, + MP_BT_MODE_MAX +}MP_BT_MODE,*PMP_BT_MODE; + + +// definition for BT_UP_OP_BT_SET_TX_RX_PARAMETER +typedef struct _BT_TXRX_PARAMETERS{ + u1Byte txrxChannel; + u4Byte txrxTxPktCnt; + u1Byte txrxTxPktInterval; + u1Byte txrxPayloadType; + u1Byte txrxPktType; + u2Byte txrxPayloadLen; + u4Byte txrxPktHeader; + u1Byte txrxWhitenCoeff; + u1Byte txrxBdaddr[6]; + u1Byte txrxTxGainIndex; +} BT_TXRX_PARAMETERS, *PBT_TXRX_PARAMETERS; + +// txrxPktType +typedef enum _MP_BT_PKT_TYPE{ + MP_BT_PKT_DH1 = 0, + MP_BT_PKT_DH3 = 1, + MP_BT_PKT_DH5 = 2, + MP_BT_PKT_2DH1 = 3, + MP_BT_PKT_2DH3 = 4, + MP_BT_PKT_2DH5 = 5, + MP_BT_PKT_3DH1 = 6, + MP_BT_PKT_3DH3 = 7, + MP_BT_PKT_3DH5 = 8, + MP_BT_PKT_LE = 9, + MP_BT_PKT_MAX +}MP_BT_PKT_TYPE,*PMP_BT_PKT_TYPE; +// txrxPayloadType +typedef enum _MP_BT_PAYLOAD_TYPE{ + MP_BT_PAYLOAD_01010101 = 0, + MP_BT_PAYLOAD_ALL_1 = 1, + MP_BT_PAYLOAD_ALL_0 = 2, + MP_BT_PAYLOAD_11110000 = 3, + MP_BT_PAYLOAD_PRBS9 = 4, + MP_BT_PAYLOAD_MAX = 8, +}MP_BT_PAYLOAD_TYPE,*PMP_BT_PAYLOAD_TYPE; + + +// definition for BT_UP_OP_BT_TEST_CTRL +typedef enum _MP_BT_TEST_CTRL{ + MP_BT_TEST_STOP_ALL_TESTS = 0, + MP_BT_TEST_START_RX_TEST = 1, + MP_BT_TEST_START_PACKET_TX_TEST = 2, + MP_BT_TEST_START_CONTINUOUS_TX_TEST = 3, + MP_BT_TEST_START_INQUIRY_SCAN_TEST = 4, + MP_BT_TEST_START_PAGE_SCAN_TEST = 5, + MP_BT_TEST_START_INQUIRY_PAGE_SCAN_TEST = 6, + MP_BT_TEST_START_LEGACY_CONNECT_TEST = 7, + MP_BT_TEST_START_LE_CONNECT_TEST_INITIATOR = 8, + MP_BT_TEST_START_LE_CONNECT_TEST_ADVERTISER = 9, + MP_BT_TEST_MAX +}MP_BT_TEST_CTRL,*PMP_BT_TEST_CTRL; + + +typedef enum _RTL_EXT_C2H_EVT +{ + EXT_C2H_WIFI_FW_ACTIVE_RSP = 0, + EXT_C2H_TRIG_BY_BT_FW = 1, + MAX_EXT_C2HEVENT +}RTL_EXT_C2H_EVT; + +// OP codes definition between the user layer and driver +typedef enum _BT_CTRL_OPCODE_UPPER{ + BT_UP_OP_BT_READY = 0x00, + BT_UP_OP_BT_SET_MODE = 0x01, + BT_UP_OP_BT_SET_TX_RX_PARAMETER = 0x02, + BT_UP_OP_BT_SET_GENERAL = 0x03, + BT_UP_OP_BT_GET_GENERAL = 0x04, + BT_UP_OP_BT_TEST_CTRL = 0x05, + BT_UP_OP_TEST_BT = 0x06, + BT_UP_OP_MAX +}BT_CTRL_OPCODE_UPPER,*PBT_CTRL_OPCODE_UPPER; + + +typedef enum _BT_SET_GENERAL{ + BT_GSET_REG = 0x00, + BT_GSET_RESET = 0x01, + BT_GSET_TARGET_BD_ADDR = 0x02, + BT_GSET_TX_PWR_FINETUNE = 0x03, + BT_SET_TRACKING_INTERVAL = 0x04, + BT_SET_THERMAL_METER = 0x05, + BT_ENABLE_CFO_TRACKING = 0x06, + BT_GSET_UPDATE_BT_PATCH = 0x07, + BT_GSET_MAX +}BT_SET_GENERAL,*PBT_SET_GENERAL; + +typedef enum _BT_GET_GENERAL{ + BT_GGET_REG = 0x00, + BT_GGET_STATUS = 0x01, + BT_GGET_REPORT = 0x02, + BT_GGET_AFH_MAP = 0x03, + BT_GGET_AFH_STATUS = 0x04, + BT_GGET_MAX +}BT_GET_GENERAL,*PBT_GET_GENERAL; + +// definition for BT_UP_OP_BT_SET_GENERAL +typedef enum _BT_REG_TYPE{ + BT_REG_RF = 0, + BT_REG_MODEM = 1, + BT_REG_BLUEWIZE = 2, + BT_REG_VENDOR = 3, + BT_REG_LE = 4, + BT_REG_MAX +}BT_REG_TYPE,*PBT_REG_TYPE; + +// definition for BT_LO_OP_GET_AFH_MAP +typedef enum _BT_AFH_MAP_TYPE{ + BT_AFH_MAP_RESULT = 0, + BT_AFH_MAP_WIFI_PSD_ONLY = 1, + BT_AFH_MAP_WIFI_CH_BW_ONLY = 2, + BT_AFH_MAP_BT_PSD_ONLY = 3, + BT_AFH_MAP_HOST_CLASSIFICATION_ONLY = 4, + BT_AFH_MAP_MAX +}BT_AFH_MAP_TYPE,*PBT_AFH_MAP_TYPE; + +// definition for BT_UP_OP_BT_GET_GENERAL +typedef enum _BT_REPORT_TYPE{ + BT_REPORT_RX_PACKET_CNT = 0, + BT_REPORT_RX_ERROR_BITS = 1, + BT_REPORT_RSSI = 2, + BT_REPORT_CFO_HDR_QUALITY = 3, + BT_REPORT_CONNECT_TARGET_BD_ADDR = 4, + BT_REPORT_MAX +}BT_REPORT_TYPE,*PBT_REPORT_TYPE; + +VOID +MPTBT_Test( + IN PADAPTER Adapter, + IN u1Byte opCode, + IN u1Byte byte1, + IN u1Byte byte2, + IN u1Byte byte3 + ); + +NDIS_STATUS +MPTBT_SendOidBT( + IN PADAPTER pAdapter, + IN PVOID InformationBuffer, + IN ULONG InformationBufferLength, + OUT PULONG BytesRead, + OUT PULONG BytesNeeded + ); + +VOID +MPTBT_FwC2hBtMpCtrl( + PADAPTER Adapter, + pu1Byte tmpBuf, + u1Byte length + ); + +void MPh2c_timeout_handle(void *FunctionContext); + +VOID mptbt_BtControlProcess( + PADAPTER Adapter, + PVOID pInBuf + ); + +#define BT_H2C_MAX_RETRY 1 +#define BT_MAX_C2H_LEN 20 + +typedef struct _BT_REQ_CMD{ + UCHAR opCodeVer; + UCHAR OpCode; + USHORT paraLength; + UCHAR pParamStart[100]; +} BT_REQ_CMD, *PBT_REQ_CMD; + +typedef struct _BT_RSP_CMD{ + USHORT status; + USHORT paraLength; + UCHAR pParamStart[100]; +} BT_RSP_CMD, *PBT_RSP_CMD; + + +typedef struct _BT_H2C{ + u1Byte opCodeVer:4; + u1Byte reqNum:4; + u1Byte opCode; + u1Byte buf[100]; +}BT_H2C, *PBT_H2C; + + + +typedef struct _BT_EXT_C2H{ + u1Byte extendId; + u1Byte statusCode:4; + u1Byte retLen:4; + u1Byte opCodeVer:4; + u1Byte reqNum:4; + u1Byte buf[100]; +}BT_EXT_C2H, *PBT_EXT_C2H; + + +typedef enum _BT_OPCODE_STATUS{ + BT_OP_STATUS_SUCCESS = 0x00, // Success + BT_OP_STATUS_VERSION_MISMATCH = 0x01, + BT_OP_STATUS_UNKNOWN_OPCODE = 0x02, + BT_OP_STATUS_ERROR_PARAMETER = 0x03, + BT_OP_STATUS_MAX +}BT_OPCODE_STATUS,*PBT_OPCODE_STATUS; + + + +//OP codes definition between driver and bt fw +typedef enum _BT_CTRL_OPCODE_LOWER{ + BT_LO_OP_GET_BT_VERSION = 0x00, + BT_LO_OP_RESET = 0x01, + BT_LO_OP_TEST_CTRL = 0x02, + BT_LO_OP_SET_BT_MODE = 0x03, + BT_LO_OP_SET_CHNL_TX_GAIN = 0x04, + BT_LO_OP_SET_PKT_TYPE_LEN = 0x05, + BT_LO_OP_SET_PKT_CNT_L_PL_TYPE = 0x06, + BT_LO_OP_SET_PKT_CNT_H_PKT_INTV = 0x07, + BT_LO_OP_SET_PKT_HEADER = 0x08, + BT_LO_OP_SET_WHITENCOEFF = 0x09, + BT_LO_OP_SET_BD_ADDR_L = 0x0a, + BT_LO_OP_SET_BD_ADDR_H = 0x0b, + BT_LO_OP_WRITE_REG_ADDR = 0x0c, + BT_LO_OP_WRITE_REG_VALUE = 0x0d, + BT_LO_OP_GET_BT_STATUS = 0x0e, + BT_LO_OP_GET_BD_ADDR_L = 0x0f, + BT_LO_OP_GET_BD_ADDR_H = 0x10, + BT_LO_OP_READ_REG = 0x11, + BT_LO_OP_SET_TARGET_BD_ADDR_L = 0x12, + BT_LO_OP_SET_TARGET_BD_ADDR_H = 0x13, + BT_LO_OP_SET_TX_POWER_CALIBRATION = 0x14, + BT_LO_OP_GET_RX_PKT_CNT_L = 0x15, + BT_LO_OP_GET_RX_PKT_CNT_H = 0x16, + BT_LO_OP_GET_RX_ERROR_BITS_L = 0x17, + BT_LO_OP_GET_RX_ERROR_BITS_H = 0x18, + BT_LO_OP_GET_RSSI = 0x19, + BT_LO_OP_GET_CFO_HDR_QUALITY_L = 0x1a, + BT_LO_OP_GET_CFO_HDR_QUALITY_H = 0x1b, + BT_LO_OP_GET_TARGET_BD_ADDR_L = 0x1c, + BT_LO_OP_GET_TARGET_BD_ADDR_H = 0x1d, + BT_LO_OP_GET_AFH_MAP_L = 0x1e, + BT_LO_OP_GET_AFH_MAP_M = 0x1f, + BT_LO_OP_GET_AFH_MAP_H = 0x20, + BT_LO_OP_GET_AFH_STATUS = 0x21, + BT_LO_OP_SET_TRACKING_INTERVAL = 0x22, + BT_LO_OP_SET_THERMAL_METER = 0x23, + BT_LO_OP_ENABLE_CFO_TRACKING = 0x24, + BT_LO_OP_MAX +}BT_CTRL_OPCODE_LOWER,*PBT_CTRL_OPCODE_LOWER; + + + + +#endif /* #if(MP_DRIVER == 1) */ + +#endif // #ifndef __INC_MPT_BT_H + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_btcoex.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_btcoex.h new file mode 100644 index 000000000..b1489c4b6 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_btcoex.h @@ -0,0 +1,436 @@ +/****************************************************************************** + * + * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_BTCOEX_H__ +#define __RTW_BTCOEX_H__ + +#include + +/* For H2C: H2C_BT_MP_OPER. Return status definition to the user layer */ +typedef enum _BT_CTRL_STATUS { + BT_STATUS_SUCCESS = 0x00, /* Success */ + BT_STATUS_BT_OP_SUCCESS = 0x01, /* bt fw op execution success */ + BT_STATUS_H2C_SUCCESS = 0x02, /* H2c success */ + BT_STATUS_H2C_FAIL = 0x03, /* H2c fail */ + BT_STATUS_H2C_LENGTH_EXCEEDED = 0x04, /* H2c command length exceeded */ + BT_STATUS_H2C_TIMTOUT = 0x05, /* H2c timeout */ + BT_STATUS_H2C_BT_NO_RSP = 0x06, /* H2c sent, bt no rsp */ + BT_STATUS_C2H_SUCCESS = 0x07, /* C2h success */ + BT_STATUS_C2H_REQNUM_MISMATCH = 0x08, /* bt fw wrong rsp */ + BT_STATUS_OPCODE_U_VERSION_MISMATCH = 0x08, /* Upper layer OP code version mismatch. */ + BT_STATUS_OPCODE_L_VERSION_MISMATCH = 0x0a, /* Lower layer OP code version mismatch. */ + BT_STATUS_UNKNOWN_OPCODE_U = 0x0b, /* Unknown Upper layer OP code */ + BT_STATUS_UNKNOWN_OPCODE_L = 0x0c, /* Unknown Lower layer OP code */ + BT_STATUS_PARAMETER_FORMAT_ERROR_U = 0x0d, /* Wrong parameters sent by upper layer. */ + BT_STATUS_PARAMETER_FORMAT_ERROR_L = 0x0e, /* bt fw parameter format is not consistency */ + BT_STATUS_PARAMETER_OUT_OF_RANGE_U = 0x0f, /* uppery layer parameter value is out of range */ + BT_STATUS_PARAMETER_OUT_OF_RANGE_L = 0x10, /* bt fw parameter value is out of range */ + BT_STATUS_UNKNOWN_STATUS_L = 0x11, /* bt returned an defined status code */ + BT_STATUS_UNKNOWN_STATUS_H = 0x12, /* driver need to do error handle or not handle-well. */ + BT_STATUS_WRONG_LEVEL = 0x13, /* should be under passive level */ + BT_STATUS_NOT_IMPLEMENT = 0x14, /* op code not implemented yet */ + BT_STATUS_BT_STACK_OP_SUCCESS = 0x15, /* bt stack op execution success */ + BT_STATUS_BT_STACK_NOT_SUPPORT = 0x16, /* stack version not support this. */ + BT_STATUS_BT_STACK_SEND_HCI_EVENT_FAIL = 0x17, /* send hci event fail */ + BT_STATUS_BT_STACK_NOT_BIND = 0x18, /* stack not bind wifi driver */ + BT_STATUS_BT_STACK_NO_RSP = 0x19, /* stack doesn't have any rsp. */ + BT_STATUS_MAX +} BT_CTRL_STATUS, *PBT_CTRL_STATUS; + +#define SET_BT_MP_OPER_RET(OpCode, StatusCode) ((OpCode << 8) | StatusCode) +#define GET_OP_CODE_FROM_BT_MP_OPER_RET(RetCode) ((RetCode & 0xF0) >> 8) +#define GET_STATUS_CODE_FROM_BT_MP_OPER_RET(RetCode) (RetCode & 0x0F) +#define CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(RetCode, StatusCode) (GET_STATUS_CODE_FROM_BT_MP_OPER_RET(RetCode) == StatusCode) + +#ifdef CONFIG_BT_COEXIST_SOCKET_TRX + +#define NETLINK_USER 31 +#define CONNECT_PORT 30000 +#define CONNECT_PORT_BT 30001 +#define KERNEL_SOCKET_OK 0x01 +#define NETLINK_SOCKET_OK 0x02 + +#define OTHER 0 +#define RX_ATTEND_ACK 1 +#define RX_LEAVE_ACK 2 +#define RX_BT_LEAVE 3 +#define RX_INVITE_REQ 4 +#define RX_ATTEND_REQ 5 +#define RX_INVITE_RSP 6 + +#define invite_req "INVITE_REQ" +#define invite_rsp "INVITE_RSP" +#define attend_req "ATTEND_REQ" +#define attend_ack "ATTEND_ACK" +#define wifi_leave "WIFI_LEAVE" +#define leave_ack "LEAVE_ACK" +#define bt_leave "BT_LEAVE" + +#define BT_INFO_NOTIFY_CMD 0x0106 +#define BT_INFO_LEN 8 + +typedef struct _HCI_LINK_INFO{ + u2Byte ConnectHandle; + u1Byte IncomingTrafficMode; + u1Byte OutgoingTrafficMode; + u1Byte BTProfile; + u1Byte BTCoreSpec; + s1Byte BT_RSSI; + u1Byte TrafficProfile; + u1Byte linkRole; +}HCI_LINK_INFO, *PHCI_LINK_INFO; + +#define MAX_BT_ACL_LINK_NUM 8 + +typedef struct _HCI_EXT_CONFIG{ + HCI_LINK_INFO aclLink[MAX_BT_ACL_LINK_NUM]; + u1Byte btOperationCode; + u2Byte CurrentConnectHandle; + u1Byte CurrentIncomingTrafficMode; + u1Byte CurrentOutgoingTrafficMode; + + u1Byte NumberOfACL; + u1Byte NumberOfSCO; + u1Byte CurrentBTStatus; + u2Byte HCIExtensionVer; + + BOOLEAN bEnableWifiScanNotify; +}HCI_EXT_CONFIG, *PHCI_EXT_CONFIG; + +typedef struct _HCI_PHY_LINK_BSS_INFO{ + u2Byte bdCap; // capability information + + // Qos related. Added by Annie, 2005-11-01. + //BSS_QOS BssQos; + +}HCI_PHY_LINK_BSS_INFO, *PHCI_PHY_LINK_BSS_INFO; + +typedef enum _BT_CONNECT_TYPE{ + BT_CONNECT_AUTH_REQ =0x00, + BT_CONNECT_AUTH_RSP =0x01, + BT_CONNECT_ASOC_REQ =0x02, + BT_CONNECT_ASOC_RSP =0x03, + BT_DISCONNECT =0x04 +}BT_CONNECT_TYPE,*PBT_CONNECT_TYPE; + + +typedef struct _PACKET_IRP_HCIEVENT_DATA { + u8 EventCode; + u8 Length; //total cmd length = extension event length+1(extension event code length) + u8 Data[1]; // byte1 is extension event code +} rtw_HCI_event; + + +struct btinfo_8761ATV { + u8 cid; + u8 len; + + u8 bConnection:1; + u8 bSCOeSCO:1; + u8 bInQPage:1; + u8 bACLBusy:1; + u8 bSCOBusy:1; + u8 bHID:1; + u8 bA2DP:1; + u8 bFTP:1; + + u8 retry_cnt:4; + u8 rsvd_34:1; + u8 bPage:1; + u8 TRxMask:1; + u8 Sniff_attempt:1; + + u8 rssi; + + u8 A2dp_rate:1; + u8 ReInit:1; + u8 MaxPower:1; + u8 bEnIgnoreWlanAct:1; + u8 TxPowerLow:1; + u8 TxPowerHigh:1; + u8 eSCO_SCO:1; + u8 Master_Slave:1; + + u8 ACL_TRx_TP_low; + u8 ACL_TRx_TP_high; +}; + +#define HCIOPCODE(_OCF, _OGF) ((_OGF)<<10|(_OCF)) +#define HCIOPCODELOW(_OCF, _OGF) (u8)(HCIOPCODE(_OCF, _OGF)&0x00ff) +#define HCIOPCODEHIGHT(_OCF, _OGF) (u8)(HCIOPCODE(_OCF, _OGF)>>8) +#define HCI_OGF(opCode) (unsigned char)((0xFC00 & (opCode)) >> 10) +#define HCI_OCF(opCode) ( 0x3FF & (opCode)) + + +typedef enum _HCI_STATUS{ + HCI_STATUS_SUCCESS =0x00, //Success + HCI_STATUS_UNKNOW_HCI_CMD =0x01, //Unknown HCI Command + HCI_STATUS_UNKNOW_CONNECT_ID =0X02, //Unknown Connection Identifier + HCI_STATUS_HW_FAIL =0X03, //Hardware Failure + HCI_STATUS_PAGE_TIMEOUT =0X04, //Page Timeout + HCI_STATUS_AUTH_FAIL =0X05, //Authentication Failure + HCI_STATUS_PIN_OR_KEY_MISSING =0X06, //PIN or Key Missing + HCI_STATUS_MEM_CAP_EXCEED =0X07, //Memory Capacity Exceeded + HCI_STATUS_CONNECT_TIMEOUT =0X08, //Connection Timeout + HCI_STATUS_CONNECT_LIMIT =0X09, //Connection Limit Exceeded + HCI_STATUS_SYN_CONNECT_LIMIT =0X0a, //Synchronous Connection Limit To A Device Exceeded + HCI_STATUS_ACL_CONNECT_EXISTS =0X0b, //ACL Connection Already Exists + HCI_STATUS_CMD_DISALLOW =0X0c, //Command Disallowed + HCI_STATUS_CONNECT_RJT_LIMIT_RESOURCE =0X0d, //Connection Rejected due to Limited Resources + HCI_STATUS_CONNECT_RJT_SEC_REASON =0X0e, //Connection Rejected Due To Security Reasons + HCI_STATUS_CONNECT_RJT_UNACCEPT_BD_ADDR =0X0f, //Connection Rejected due to Unacceptable BD_ADDR + HCI_STATUS_CONNECT_ACCEPT_TIMEOUT =0X10, //Connection Accept Timeout Exceeded + HCI_STATUS_UNSUPPORT_FEATURE_PARA_VALUE =0X11, //Unsupported Feature or Parameter Value + HCI_STATUS_INVALID_HCI_CMD_PARA_VALUE =0X12, //Invalid HCI Command Parameters + HCI_STATUS_REMOTE_USER_TERMINATE_CONNECT =0X13, //Remote User Terminated Connection + HCI_STATUS_REMOTE_DEV_TERMINATE_LOW_RESOURCE =0X14, //Remote Device Terminated Connection due to Low Resources + HCI_STATUS_REMOTE_DEV_TERMINATE_CONNECT_POWER_OFF =0X15, //Remote Device Terminated Connection due to Power Off + HCI_STATUS_CONNECT_TERMINATE_LOCAL_HOST =0X16, //Connection Terminated By Local Host + HCI_STATUS_REPEATE_ATTEMPT =0X17, //Repeated Attempts + HCI_STATUS_PAIR_NOT_ALLOW =0X18, //Pairing Not Allowed + HCI_STATUS_UNKNOW_LMP_PDU =0X19, //Unknown LMP PDU + HCI_STATUS_UNSUPPORT_REMOTE_LMP_FEATURE =0X1a, //Unsupported Remote Feature / Unsupported LMP Feature + HCI_STATUS_SOC_OFFSET_REJECT =0X1b, //SCO Offset Rejected + HCI_STATUS_SOC_INTERVAL_REJECT =0X1c, //SCO Interval Rejected + HCI_STATUS_SOC_AIR_MODE_REJECT =0X1d,//SCO Air Mode Rejected + HCI_STATUS_INVALID_LMP_PARA =0X1e, //Invalid LMP Parameters + HCI_STATUS_UNSPECIFIC_ERROR =0X1f, //Unspecified Error + HCI_STATUS_UNSUPPORT_LMP_PARA_VALUE =0X20, //Unsupported LMP Parameter Value + HCI_STATUS_ROLE_CHANGE_NOT_ALLOW =0X21, //Role Change Not Allowed + HCI_STATUS_LMP_RESPONSE_TIMEOUT =0X22, //LMP Response Timeout + HCI_STATUS_LMP_ERROR_TRANSACTION_COLLISION =0X23, //LMP Error Transaction Collision + HCI_STATUS_LMP_PDU_NOT_ALLOW =0X24, //LMP PDU Not Allowed + HCI_STATUS_ENCRYPTION_MODE_NOT_ALLOW =0X25, //Encryption Mode Not Acceptable + HCI_STATUS_LINK_KEY_CAN_NOT_CHANGE =0X26, //Link Key Can Not be Changed + HCI_STATUS_REQUEST_QOS_NOT_SUPPORT =0X27, //Requested QoS Not Supported + HCI_STATUS_INSTANT_PASSED =0X28, //Instant Passed + HCI_STATUS_PAIRING_UNIT_KEY_NOT_SUPPORT =0X29, //Pairing With Unit Key Not Supported + HCI_STATUS_DIFFERENT_TRANSACTION_COLLISION =0X2a, //Different Transaction Collision + HCI_STATUS_RESERVE_1 =0X2b, //Reserved + HCI_STATUS_QOS_UNACCEPT_PARA =0X2c, //QoS Unacceptable Parameter + HCI_STATUS_QOS_REJECT =0X2d, //QoS Rejected + HCI_STATUS_CHNL_CLASSIFICATION_NOT_SUPPORT =0X2e, //Channel Classification Not Supported + HCI_STATUS_INSUFFICIENT_SECURITY =0X2f, //Insufficient Security + HCI_STATUS_PARA_OUT_OF_RANGE =0x30, //Parameter Out Of Mandatory Range + HCI_STATUS_RESERVE_2 =0X31, //Reserved + HCI_STATUS_ROLE_SWITCH_PENDING =0X32, //Role Switch Pending + HCI_STATUS_RESERVE_3 =0X33, //Reserved + HCI_STATUS_RESERVE_SOLT_VIOLATION =0X34, //Reserved Slot Violation + HCI_STATUS_ROLE_SWITCH_FAIL =0X35, //Role Switch Failed + HCI_STATUS_EXTEND_INQUIRY_RSP_TOO_LARGE =0X36, //Extended Inquiry Response Too Large + HCI_STATUS_SEC_SIMPLE_PAIRING_NOT_SUPPORT =0X37, //Secure Simple Pairing Not Supported By Host. + HCI_STATUS_HOST_BUSY_PAIRING =0X38, //Host Busy - Pairing + HCI_STATUS_CONNECT_REJ_NOT_SUIT_CHNL_FOUND =0X39, //Connection Rejected due to No Suitable Channel Found + HCI_STATUS_CONTROLLER_BUSY =0X3a //CONTROLLER BUSY +}RTW_HCI_STATUS; + +#define HCI_EVENT_COMMAND_COMPLETE 0x0e + +#define OGF_EXTENSION 0X3f +typedef enum HCI_EXTENSION_COMMANDS{ + HCI_SET_ACL_LINK_DATA_FLOW_MODE =0x0010, + HCI_SET_ACL_LINK_STATUS =0x0020, + HCI_SET_SCO_LINK_STATUS =0x0030, + HCI_SET_RSSI_VALUE =0x0040, + HCI_SET_CURRENT_BLUETOOTH_STATUS =0x0041, + + //The following is for RTK8723 + HCI_EXTENSION_VERSION_NOTIFY =0x0100, + HCI_LINK_STATUS_NOTIFY =0x0101, + HCI_BT_OPERATION_NOTIFY =0x0102, + HCI_ENABLE_WIFI_SCAN_NOTIFY =0x0103, + HCI_QUERY_RF_STATUS =0x0104, + HCI_BT_ABNORMAL_NOTIFY =0x0105, + HCI_BT_INFO_NOTIFY =0x0106, + HCI_BT_COEX_NOTIFY =0x0107, + HCI_BT_PATCH_VERSION_NOTIFY =0x0108, + HCI_BT_AFH_MAP_NOTIFY =0x0109, + HCI_BT_REGISTER_VALUE_NOTIFY =0x010a, + + //The following is for IVT + HCI_WIFI_CURRENT_CHANNEL =0x0300, + HCI_WIFI_CURRENT_BANDWIDTH =0x0301, + HCI_WIFI_CONNECTION_STATUS =0x0302 +}RTW_HCI_EXT_CMD; + +#define HCI_EVENT_EXTENSION_RTK 0xfe +typedef enum HCI_EXTENSION_EVENT_RTK{ + HCI_EVENT_EXT_WIFI_SCAN_NOTIFY =0x01, + HCI_EVENT_EXT_WIFI_RF_STATUS_NOTIFY =0x02, + HCI_EVENT_EXT_BT_INFO_CONTROL =0x03, + HCI_EVENT_EXT_BT_COEX_CONTROL =0x04 +}RTW_HCI_EXT_EVENT; + +typedef enum _BT_TRAFFIC_MODE{ + BT_MOTOR_EXT_BE = 0x00, //Best Effort. Default. for HCRP, PAN, SDP, RFCOMM-based profiles like FTP,OPP, SPP, DUN, etc. + BT_MOTOR_EXT_GUL = 0x01, //Guaranteed Latency. This type of traffic is used e.g. for HID and AVRCP. + BT_MOTOR_EXT_GUB = 0X02, //Guaranteed Bandwidth. + BT_MOTOR_EXT_GULB = 0X03 //Guaranteed Latency and Bandwidth. for A2DP and VDP. +} BT_TRAFFIC_MODE; + +typedef enum _BT_TRAFFIC_MODE_PROFILE{ + BT_PROFILE_NONE, + BT_PROFILE_A2DP, + BT_PROFILE_PAN , + BT_PROFILE_HID, + BT_PROFILE_SCO +} BT_TRAFFIC_MODE_PROFILE; + +typedef enum _HCI_EXT_BT_OPERATION { + HCI_BT_OP_NONE = 0x0, + HCI_BT_OP_INQUIRY_START = 0x1, + HCI_BT_OP_INQUIRY_FINISH = 0x2, + HCI_BT_OP_PAGING_START = 0x3, + HCI_BT_OP_PAGING_SUCCESS = 0x4, + HCI_BT_OP_PAGING_UNSUCCESS = 0x5, + HCI_BT_OP_PAIRING_START = 0x6, + HCI_BT_OP_PAIRING_FINISH = 0x7, + HCI_BT_OP_BT_DEV_ENABLE = 0x8, + HCI_BT_OP_BT_DEV_DISABLE = 0x9, + HCI_BT_OP_MAX +} HCI_EXT_BT_OPERATION, *PHCI_EXT_BT_OPERATION; + +typedef struct _BT_MGNT{ + BOOLEAN bBTConnectInProgress; + BOOLEAN bLogLinkInProgress; + BOOLEAN bPhyLinkInProgress; + BOOLEAN bPhyLinkInProgressStartLL; + u1Byte BtCurrentPhyLinkhandle; + u2Byte BtCurrentLogLinkhandle; + u1Byte CurrentConnectEntryNum; + u1Byte DisconnectEntryNum; + u1Byte CurrentBTConnectionCnt; + BT_CONNECT_TYPE BTCurrentConnectType; + BT_CONNECT_TYPE BTReceiveConnectPkt; + u1Byte BTAuthCount; + u1Byte BTAsocCount; + BOOLEAN bStartSendSupervisionPkt; + BOOLEAN BtOperationOn; + BOOLEAN BTNeedAMPStatusChg; + BOOLEAN JoinerNeedSendAuth; + HCI_PHY_LINK_BSS_INFO bssDesc; + HCI_EXT_CONFIG ExtConfig; + BOOLEAN bNeedNotifyAMPNoCap; + BOOLEAN bCreateSpportQos; + BOOLEAN bSupportProfile; + u1Byte BTChannel; + BOOLEAN CheckChnlIsSuit; + BOOLEAN bBtScan; + BOOLEAN btLogoTest; + BOOLEAN bRfStatusNotified; + BOOLEAN bBtRsvedPageDownload; +}BT_MGNT, *PBT_MGNT; + +struct bt_coex_info { + /* For Kernel Socket */ + struct socket *udpsock; + struct sockaddr_in wifi_sockaddr; /*wifi socket*/ + struct sockaddr_in bt_sockaddr;/* BT socket */ + struct sock *sk_store;/*back up socket for UDP RX int*/ + + /* store which socket is OK */ + u8 sock_open; + + u8 BT_attend; + u8 is_exist; /* socket exist */ + BT_MGNT BtMgnt; + struct workqueue_struct *btcoex_wq; + struct delayed_work recvmsg_work; +}; +#endif //CONFIG_BT_COEXIST_SOCKET_TRX + +#define PACKET_NORMAL 0 +#define PACKET_DHCP 1 +#define PACKET_ARP 2 +#define PACKET_EAPOL 3 + +void rtw_btcoex_Initialize(PADAPTER); +void rtw_btcoex_PowerOnSetting(PADAPTER padapter); +void rtw_btcoex_PreLoadFirmware(PADAPTER padapter); +void rtw_btcoex_HAL_Initialize(PADAPTER padapter, u8 bWifiOnly); +void rtw_btcoex_IpsNotify(PADAPTER, u8 type); +void rtw_btcoex_LpsNotify(PADAPTER, u8 type); +void rtw_btcoex_ScanNotify(PADAPTER, u8 type); +void rtw_btcoex_ConnectNotify(PADAPTER, u8 action); +void rtw_btcoex_MediaStatusNotify(PADAPTER, u8 mediaStatus); +void rtw_btcoex_SpecialPacketNotify(PADAPTER, u8 pktType); +void rtw_btcoex_IQKNotify(PADAPTER padapter, u8 state); +void rtw_btcoex_BtInfoNotify(PADAPTER, u8 length, u8 *tmpBuf); +void rtw_btcoex_BtMpRptNotify(PADAPTER, u8 length, u8 *tmpBuf); +void rtw_btcoex_SuspendNotify(PADAPTER, u8 state); +void rtw_btcoex_HaltNotify(PADAPTER); +void rtw_btcoex_ScoreBoardStatusNotify(PADAPTER, u8 length, u8 *tmpBuf); +void rtw_btcoex_SwitchBtTRxMask(PADAPTER); +void rtw_btcoex_Switch(PADAPTER, u8 enable); +u8 rtw_btcoex_IsBtDisabled(PADAPTER); +void rtw_btcoex_Handler(PADAPTER); +s32 rtw_btcoex_IsBTCoexRejectAMPDU(PADAPTER padapter); +s32 rtw_btcoex_IsBTCoexCtrlAMPDUSize(PADAPTER); +u32 rtw_btcoex_GetAMPDUSize(PADAPTER); +void rtw_btcoex_SetManualControl(PADAPTER, u8 bmanual); +u8 rtw_btcoex_1Ant(PADAPTER); +u8 rtw_btcoex_IsBtControlLps(PADAPTER); +u8 rtw_btcoex_IsLpsOn(PADAPTER); +u8 rtw_btcoex_RpwmVal(PADAPTER); +u8 rtw_btcoex_LpsVal(PADAPTER); +void rtw_btcoex_SetBTCoexist(PADAPTER, u8 bBtExist); +void rtw_btcoex_SetChipType(PADAPTER, u8 chipType); +void rtw_btcoex_SetPGAntNum(PADAPTER, u8 antNum); +u8 rtw_btcoex_GetPGAntNum(PADAPTER); +void rtw_btcoex_SetSingleAntPath(PADAPTER padapter, u8 singleAntPath); +u32 rtw_btcoex_GetRaMask(PADAPTER); +void rtw_btcoex_RecordPwrMode(PADAPTER, u8 *pCmdBuf, u8 cmdLen); +void rtw_btcoex_DisplayBtCoexInfo(PADAPTER, u8 *pbuf, u32 bufsize); +void rtw_btcoex_SetDBG(PADAPTER, u32 *pDbgModule); +u32 rtw_btcoex_GetDBG(PADAPTER, u8 *pStrBuf, u32 bufSize); +u8 rtw_btcoex_IncreaseScanDeviceNum(PADAPTER); +u8 rtw_btcoex_IsBtLinkExist(PADAPTER); +void rtw_btcoex_BTOffOnNotify(PADAPTER padapter, u8 bBTON); +#ifdef CONFIG_BT_COEXIST_SOCKET_TRX +void rtw_btcoex_SetBtPatchVersion(PADAPTER padapter,u16 btHciVer, u16 btPatchVer); +void rtw_btcoex_SetHciVersion(PADAPTER padapter, u16 hciVersion); +void rtw_btcoex_StackUpdateProfileInfo(void); +void rtw_btcoex_init_socket(_adapter *padapter); +void rtw_btcoex_close_socket(_adapter *padapter); +void rtw_btcoex_dump_tx_msg(u8 *tx_msg, u8 len, u8 *msg_name); +u8 rtw_btcoex_sendmsgbysocket(_adapter *padapter, u8 *msg, u8 msg_size, bool force); +u8 rtw_btcoex_create_kernel_socket(_adapter *padapter); +void rtw_btcoex_close_kernel_socket(_adapter *padapter); +void rtw_btcoex_recvmsgbysocket(void *data); +u16 rtw_btcoex_parse_recv_data(u8 *msg, u8 msg_size); +u8 rtw_btcoex_btinfo_cmd(PADAPTER padapter, u8 *pbuf, u16 length); +void rtw_btcoex_parse_hci_cmd(_adapter *padapter, u8 *cmd, u16 len); +void rtw_btcoex_SendEventExtBtCoexControl(PADAPTER Adapter, u8 bNeedDbgRsp, u8 dataLen, void *pData); +void rtw_btcoex_SendEventExtBtInfoControl(PADAPTER Adapter, u8 dataLen, void *pData); +void rtw_btcoex_SendScanNotify(PADAPTER padapter, u8 scanType); +#define BT_SendEventExtBtCoexControl(Adapter, bNeedDbgRsp, dataLen, pData) rtw_btcoex_SendEventExtBtCoexControl(Adapter, bNeedDbgRsp, dataLen, pData) +#define BT_SendEventExtBtInfoControl(Adapter, dataLen, pData) rtw_btcoex_SendEventExtBtInfoControl(Adapter, dataLen, pData) +#endif //CONFIG_BT_COEXIST_SOCKET_TRX +u16 rtw_btcoex_btreg_read(PADAPTER padapter, u8 type, u16 addr, u32 *data); +u16 rtw_btcoex_btreg_write(PADAPTER padapter, u8 type, u16 addr, u16 val); + +// ================================================== +// Below Functions are called by BT-Coex +// ================================================== +void rtw_btcoex_rx_ampdu_apply(PADAPTER); +void rtw_btcoex_LPS_Enter(PADAPTER); +void rtw_btcoex_LPS_Leave(PADAPTER); + +#endif // __RTW_BTCOEX_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_byteorder.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_byteorder.h new file mode 100644 index 000000000..29c5029ce --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_byteorder.h @@ -0,0 +1,39 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTL871X_BYTEORDER_H_ +#define _RTL871X_BYTEORDER_H_ + + +#if defined (CONFIG_LITTLE_ENDIAN) && defined (CONFIG_BIG_ENDIAN) +#error "Shall be CONFIG_LITTLE_ENDIAN or CONFIG_BIG_ENDIAN, but not both!\n" +#endif + +#if defined (CONFIG_LITTLE_ENDIAN) +#ifndef CONFIG_PLATFORM_MSTAR389 +# include +#endif +#elif defined (CONFIG_BIG_ENDIAN) +# include +#else +# error "Must be LITTLE/BIG Endian Host" +#endif + +#endif /* _RTL871X_BYTEORDER_H_ */ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_cmd.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_cmd.h new file mode 100644 index 000000000..9bbc63523 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_cmd.h @@ -0,0 +1,1340 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_CMD_H_ +#define __RTW_CMD_H_ + + +#define C2H_MEM_SZ (16*1024) + +#ifndef CONFIG_RTL8711FW + + #define FREE_CMDOBJ_SZ 128 + + #define MAX_CMDSZ 1024 + #define MAX_RSPSZ 512 + #define MAX_EVTSZ 1024 + +#ifdef PLATFORM_OS_CE + #define CMDBUFF_ALIGN_SZ 4 +#else + #define CMDBUFF_ALIGN_SZ 512 +#endif + + struct cmd_obj { + _adapter *padapter; + u16 cmdcode; + u8 res; + u8 *parmbuf; + u32 cmdsz; + u8 *rsp; + u32 rspsz; + struct submit_ctx *sctx; + u8 no_io; + //_sema cmd_sem; + _list list; + }; + + /* cmd flags */ + enum { + RTW_CMDF_DIRECTLY = BIT0, + RTW_CMDF_WAIT_ACK = BIT1, + }; + + struct cmd_priv { + _sema cmd_queue_sema; + //_sema cmd_done_sema; + _sema terminate_cmdthread_sema; + _queue cmd_queue; + u8 cmd_seq; + u8 *cmd_buf; //shall be non-paged, and 4 bytes aligned + u8 *cmd_allocated_buf; + u8 *rsp_buf; //shall be non-paged, and 4 bytes aligned + u8 *rsp_allocated_buf; + u32 cmd_issued_cnt; + u32 cmd_done_cnt; + u32 rsp_cnt; + ATOMIC_T cmdthd_running; + //u8 cmdthd_running; + u8 stop_req; + _adapter *padapter; + _mutex sctx_mutex; + }; + +#ifdef CONFIG_EVENT_THREAD_MODE + struct evt_obj { + u16 evtcode; + u8 res; + u8 *parmbuf; + u32 evtsz; + _list list; + }; +#endif + + struct evt_priv { +#ifdef CONFIG_EVENT_THREAD_MODE + _sema evt_notify; + _sema terminate_evtthread_sema; + _queue evt_queue; +#endif + +#define CONFIG_C2H_WK +#ifdef CONFIG_C2H_WK + _workitem c2h_wk; + bool c2h_wk_alive; + struct rtw_cbuf *c2h_queue; + #define C2H_QUEUE_MAX_LEN 10 +#endif + +#ifdef CONFIG_H2CLBK + _sema lbkevt_done; + u8 lbkevt_limit; + u8 lbkevt_num; + u8 *cmdevt_parm; +#endif + ATOMIC_T event_seq; + u8 *evt_buf; //shall be non-paged, and 4 bytes aligned + u8 *evt_allocated_buf; + u32 evt_done_cnt; +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + u8 *c2h_mem; + u8 *allocated_c2h_mem; +#ifdef PLATFORM_OS_XP + PMDL pc2h_mdl; +#endif +#endif + + }; + +#define init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code) \ +do {\ + _rtw_init_listhead(&pcmd->list);\ + pcmd->cmdcode = code;\ + pcmd->parmbuf = (u8 *)(pparm);\ + pcmd->cmdsz = sizeof (*pparm);\ + pcmd->rsp = NULL;\ + pcmd->rspsz = 0;\ +} while(0) + +#define init_h2fwcmd_w_parm_no_parm_rsp(pcmd, code) \ +do {\ + _rtw_init_listhead(&pcmd->list);\ + pcmd->cmdcode = code;\ + pcmd->parmbuf = NULL;\ + pcmd->cmdsz = 0;\ + pcmd->rsp = NULL;\ + pcmd->rspsz = 0;\ +} while(0) + +struct c2h_evt_hdr { + u8 id:4; + u8 plen:4; + u8 seq; + u8 payload[0]; +}; + +struct c2h_evt_hdr_88xx { + u8 id; + u8 seq; + u8 payload[12]; + u8 plen; + u8 trigger; +}; + +#define c2h_evt_valid(c2h_evt) ((c2h_evt)->id || (c2h_evt)->plen) + +struct P2P_PS_Offload_t { + u8 Offload_En:1; + u8 role:1; // 1: Owner, 0: Client + u8 CTWindow_En:1; + u8 NoA0_En:1; + u8 NoA1_En:1; + u8 AllStaSleep:1; // Only valid in Owner + u8 discovery:1; + u8 rsvd:1; +}; + +struct P2P_PS_CTWPeriod_t { + u8 CTWPeriod; //TU +}; + +#ifdef CONFIG_P2P_WOWLAN + +struct P2P_WoWlan_Offload_t{ + u8 Disconnect_Wkup_Drv:1; + u8 role:2; + u8 Wps_Config[2]; +}; + +#endif //CONFIG_P2P_WOWLAN + +extern u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *obj); +extern struct cmd_obj *rtw_dequeue_cmd(struct cmd_priv *pcmdpriv); +extern void rtw_free_cmd_obj(struct cmd_obj *pcmd); + +#ifdef CONFIG_EVENT_THREAD_MODE +extern u32 rtw_enqueue_evt(struct evt_priv *pevtpriv, struct evt_obj *obj); +extern struct evt_obj *rtw_dequeue_evt(_queue *queue); +extern void rtw_free_evt_obj(struct evt_obj *pcmd); +#endif + +void rtw_stop_cmd_thread(_adapter *adapter); +thread_return rtw_cmd_thread(thread_context context); + +extern u32 rtw_init_cmd_priv (struct cmd_priv *pcmdpriv); +extern void rtw_free_cmd_priv (struct cmd_priv *pcmdpriv); + +extern u32 rtw_init_evt_priv (struct evt_priv *pevtpriv); +extern void rtw_free_evt_priv (struct evt_priv *pevtpriv); +extern void rtw_cmd_clr_isr(struct cmd_priv *pcmdpriv); +extern void rtw_evt_notify_isr(struct evt_priv *pevtpriv); +#ifdef CONFIG_P2P +u8 p2p_protocol_wk_cmd(_adapter*padapter, int intCmdType ); +#endif //CONFIG_P2P + +#else + //#include +#endif /* CONFIG_RTL8711FW */ + +enum rtw_drvextra_cmd_id +{ + NONE_WK_CID, + STA_MSTATUS_RPT_WK_CID, + DYNAMIC_CHK_WK_CID, + DM_CTRL_WK_CID, + PBC_POLLING_WK_CID, + POWER_SAVING_CTRL_WK_CID,//IPS,AUTOSuspend + LPS_CTRL_WK_CID, + ANT_SELECT_WK_CID, + P2P_PS_WK_CID, + P2P_PROTO_WK_CID, + CHECK_HIQ_WK_CID,//for softap mode, check hi queue if empty + INTEl_WIDI_WK_CID, + C2H_WK_CID, + RTP_TIMER_CFG_WK_CID, + RESET_SECURITYPRIV, // add for CONFIG_IEEE80211W, none 11w also can use + FREE_ASSOC_RESOURCES, // add for CONFIG_IEEE80211W, none 11w also can use + DM_IN_LPS_WK_CID, + DM_RA_MSK_WK_CID, //add for STA update RAMask when bandwith change. + BEAMFORMING_WK_CID, + LPS_CHANGE_DTIM_CID, + BTINFO_WK_CID, + DFS_MASTER_WK_CID, + SESSION_TRACKER_WK_CID, + EN_HW_UPDATE_TSF_WK_CID, + MP_CMD_WK_CID, + CUSTOMER_STR_WK_CID, + MAX_WK_CID +}; + +enum LPS_CTRL_TYPE +{ + LPS_CTRL_SCAN=0, + LPS_CTRL_JOINBSS=1, + LPS_CTRL_CONNECT=2, + LPS_CTRL_DISCONNECT=3, + LPS_CTRL_SPECIAL_PACKET=4, + LPS_CTRL_LEAVE=5, + LPS_CTRL_TRAFFIC_BUSY = 6, + LPS_CTRL_TX_TRAFFIC_LEAVE = 7, + LPS_CTRL_RX_TRAFFIC_LEAVE = 8, + LPS_CTRL_ENTER = 9, + LPS_CTRL_LEAVE_CFG80211_PWRMGMT = 10, +}; + +enum STAKEY_TYPE +{ + GROUP_KEY =0, + UNICAST_KEY =1, + TDLS_KEY =2, +}; + +enum RFINTFS { + SWSI, + HWSI, + HWPI, +}; + +/* +Caller Mode: Infra, Ad-HoC(C) + +Notes: To enter USB suspend mode + +Command Mode + +*/ +struct usb_suspend_parm { + u32 action;// 1: sleep, 0:resume +}; + +/* +Caller Mode: Infra, Ad-HoC + +Notes: To join a known BSS. + +Command-Event Mode + +*/ + +/* +Caller Mode: Infra, Ad-Hoc + +Notes: To join the specified bss + +Command Event Mode + +*/ +struct joinbss_parm { + WLAN_BSSID_EX network; +}; + +/* +Caller Mode: Infra, Ad-HoC(C) + +Notes: To disconnect the current associated BSS + +Command Mode + +*/ +struct disconnect_parm { + u32 deauth_timeout_ms; +}; + +/* +Caller Mode: AP, Ad-HoC(M) + +Notes: To create a BSS + +Command Mode +*/ +struct createbss_parm { + bool adhoc; + + /* used by AP mode now */ + s16 req_ch; + u8 req_bw; + u8 req_offset; +}; + +/* +Caller Mode: AP, Ad-HoC, Infra + +Notes: To set the NIC mode of RTL8711 + +Command Mode + +The definition of mode: + +#define IW_MODE_AUTO 0 // Let the driver decides which AP to join +#define IW_MODE_ADHOC 1 // Single cell network (Ad-Hoc Clients) +#define IW_MODE_INFRA 2 // Multi cell network, roaming, .. +#define IW_MODE_MASTER 3 // Synchronisation master or Access Point +#define IW_MODE_REPEAT 4 // Wireless Repeater (forwarder) +#define IW_MODE_SECOND 5 // Secondary master/repeater (backup) +#define IW_MODE_MONITOR 6 // Passive monitor (listen only) + +*/ +struct setopmode_parm { + u8 mode; + u8 rsvd[3]; +}; + +/* +Caller Mode: AP, Ad-HoC, Infra + +Notes: To ask RTL8711 performing site-survey + +Command-Event Mode + +*/ + +#define RTW_SSID_SCAN_AMOUNT 9 // for WEXT_CSCAN_AMOUNT 9 +#define RTW_CHANNEL_SCAN_AMOUNT (14+37) +struct sitesurvey_parm { + sint scan_mode; //active: 1, passive: 0 + /* sint bsslimit; // 1 ~ 48 */ + u8 ssid_num; + u8 ch_num; + NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; + struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT]; +}; + +/* +Caller Mode: Any + +Notes: To set the auth type of RTL8711. open/shared/802.1x + +Command Mode + +*/ +struct setauth_parm { + u8 mode; //0: legacy open, 1: legacy shared 2: 802.1x + u8 _1x; //0: PSK, 1: TLS + u8 rsvd[2]; +}; + +/* +Caller Mode: Infra + +a. algorithm: wep40, wep104, tkip & aes +b. keytype: grp key/unicast key +c. key contents + +when shared key ==> keyid is the camid +when 802.1x ==> keyid [0:1] ==> grp key +when 802.1x ==> keyid > 2 ==> unicast key + +*/ +struct setkey_parm { + u8 algorithm; // encryption algorithm, could be none, wep40, TKIP, CCMP, wep104 + u8 keyid; + u8 grpkey; // 1: this is the grpkey for 802.1x. 0: this is the unicast key for 802.1x + u8 set_tx; // 1: main tx key for wep. 0: other key. + u8 key[16]; // this could be 40 or 104 +}; + +/* +When in AP or Ad-Hoc mode, this is used to +allocate an sw/hw entry for a newly associated sta. + +Command + +when shared key ==> algorithm/keyid + +*/ +struct set_stakey_parm { + u8 addr[ETH_ALEN]; + u8 algorithm; + u8 keyid; + u8 key[16]; +}; + +struct set_stakey_rsp { + u8 addr[ETH_ALEN]; + u8 keyid; + u8 rsvd; +}; + +/* +Caller Ad-Hoc/AP + +Command -Rsp(AID == CAMID) mode + +This is to force fw to add an sta_data entry per driver's request. + +FW will write an cam entry associated with it. + +*/ +struct set_assocsta_parm { + u8 addr[ETH_ALEN]; +}; + +struct set_assocsta_rsp { + u8 cam_id; + u8 rsvd[3]; +}; + +/* + Caller Ad-Hoc/AP + + Command mode + + This is to force fw to del an sta_data entry per driver's request + + FW will invalidate the cam entry associated with it. + +*/ +struct del_assocsta_parm { + u8 addr[ETH_ALEN]; +}; + +/* +Caller Mode: AP/Ad-HoC(M) + +Notes: To notify fw that given staid has changed its power state + +Command Mode + +*/ +struct setstapwrstate_parm { + u8 staid; + u8 status; + u8 hwaddr[6]; +}; + +/* +Caller Mode: Any + +Notes: To setup the basic rate of RTL8711 + +Command Mode + +*/ +struct setbasicrate_parm { + u8 basicrates[NumRates]; +}; + +/* +Caller Mode: Any + +Notes: To read the current basic rate + +Command-Rsp Mode + +*/ +struct getbasicrate_parm { + u32 rsvd; +}; + +struct getbasicrate_rsp { + u8 basicrates[NumRates]; +}; + +/* +Caller Mode: Any + +Notes: To setup the data rate of RTL8711 + +Command Mode + +*/ +struct setdatarate_parm { +#ifdef MP_FIRMWARE_OFFLOAD + u32 curr_rateidx; +#else + u8 mac_id; + u8 datarates[NumRates]; +#endif +}; + +/* +Caller Mode: Any + +Notes: To read the current data rate + +Command-Rsp Mode + +*/ +struct getdatarate_parm { + u32 rsvd; + +}; +struct getdatarate_rsp { + u8 datarates[NumRates]; +}; + + +/* +Caller Mode: Any +AP: AP can use the info for the contents of beacon frame +Infra: STA can use the info when sitesurveying +Ad-HoC(M): Like AP +Ad-HoC(C): Like STA + + +Notes: To set the phy capability of the NIC + +Command Mode + +*/ + +struct setphyinfo_parm { + struct regulatory_class class_sets[NUM_REGULATORYS]; + u8 status; +}; + +struct getphyinfo_parm { + u32 rsvd; +}; + +struct getphyinfo_rsp { + struct regulatory_class class_sets[NUM_REGULATORYS]; + u8 status; +}; + +/* +Caller Mode: Any + +Notes: To set the channel/modem/band +This command will be used when channel/modem/band is changed. + +Command Mode + +*/ +struct setphy_parm { + u8 rfchannel; + u8 modem; +}; + +/* +Caller Mode: Any + +Notes: To get the current setting of channel/modem/band + +Command-Rsp Mode + +*/ +struct getphy_parm { + u32 rsvd; + +}; +struct getphy_rsp { + u8 rfchannel; + u8 modem; +}; + +struct readBB_parm { + u8 offset; +}; +struct readBB_rsp { + u8 value; +}; + +struct readTSSI_parm { + u8 offset; +}; +struct readTSSI_rsp { + u8 value; +}; + +struct readMAC_parm { + u8 len; + u32 addr; +}; + +struct writeBB_parm { + u8 offset; + u8 value; +}; + +struct readRF_parm { + u8 offset; +}; +struct readRF_rsp { + u32 value; +}; + +struct writeRF_parm { + u32 offset; + u32 value; +}; + +struct getrfintfs_parm { + u8 rfintfs; +}; + + +struct Tx_Beacon_param +{ + WLAN_BSSID_EX network; +}; + +/* + Notes: This command is used for H2C/C2H loopback testing + + mac[0] == 0 + ==> CMD mode, return H2C_SUCCESS. + The following condition must be ture under CMD mode + mac[1] == mac[4], mac[2] == mac[3], mac[0]=mac[5]= 0; + s0 == 0x1234, s1 == 0xabcd, w0 == 0x78563412, w1 == 0x5aa5def7; + s2 == (b1 << 8 | b0); + + mac[0] == 1 + ==> CMD_RSP mode, return H2C_SUCCESS_RSP + + The rsp layout shall be: + rsp: parm: + mac[0] = mac[5]; + mac[1] = mac[4]; + mac[2] = mac[3]; + mac[3] = mac[2]; + mac[4] = mac[1]; + mac[5] = mac[0]; + s0 = s1; + s1 = swap16(s0); + w0 = swap32(w1); + b0 = b1 + s2 = s0 + s1 + b1 = b0 + w1 = w0 + + mac[0] == 2 + ==> CMD_EVENT mode, return H2C_SUCCESS + The event layout shall be: + event: parm: + mac[0] = mac[5]; + mac[1] = mac[4]; + mac[2] = event's sequence number, starting from 1 to parm's marc[3] + mac[3] = mac[2]; + mac[4] = mac[1]; + mac[5] = mac[0]; + s0 = swap16(s0) - event.mac[2]; + s1 = s1 + event.mac[2]; + w0 = swap32(w0); + b0 = b1 + s2 = s0 + event.mac[2] + b1 = b0 + w1 = swap32(w1) - event.mac[2]; + + parm->mac[3] is the total event counts that host requested. + + + event will be the same with the cmd's param. + +*/ + +#ifdef CONFIG_H2CLBK + +struct seth2clbk_parm { + u8 mac[6]; + u16 s0; + u16 s1; + u32 w0; + u8 b0; + u16 s2; + u8 b1; + u32 w1; +}; + +struct geth2clbk_parm { + u32 rsv; +}; + +struct geth2clbk_rsp { + u8 mac[6]; + u16 s0; + u16 s1; + u32 w0; + u8 b0; + u16 s2; + u8 b1; + u32 w1; +}; + +#endif /* CONFIG_H2CLBK */ + +// CMD param Formart for driver extra cmd handler +struct drvextra_cmd_parm { + int ec_id; //extra cmd id + int type; // Can use this field as the type id or command size + int size; //buffer size + unsigned char *pbuf; +}; + +/*------------------- Below are used for RF/BB tunning ---------------------*/ + +struct setantenna_parm { + u8 tx_antset; + u8 rx_antset; + u8 tx_antenna; + u8 rx_antenna; +}; + +struct enrateadaptive_parm { + u32 en; +}; + +struct settxagctbl_parm { + u32 txagc[MAX_RATES_LENGTH]; +}; + +struct gettxagctbl_parm { + u32 rsvd; +}; +struct gettxagctbl_rsp { + u32 txagc[MAX_RATES_LENGTH]; +}; + +struct setagcctrl_parm { + u32 agcctrl; // 0: pure hw, 1: fw +}; + + +struct setssup_parm { + u32 ss_ForceUp[MAX_RATES_LENGTH]; +}; + +struct getssup_parm { + u32 rsvd; +}; +struct getssup_rsp { + u8 ss_ForceUp[MAX_RATES_LENGTH]; +}; + + +struct setssdlevel_parm { + u8 ss_DLevel[MAX_RATES_LENGTH]; +}; + +struct getssdlevel_parm { + u32 rsvd; +}; +struct getssdlevel_rsp { + u8 ss_DLevel[MAX_RATES_LENGTH]; +}; + +struct setssulevel_parm { + u8 ss_ULevel[MAX_RATES_LENGTH]; +}; + +struct getssulevel_parm { + u32 rsvd; +}; +struct getssulevel_rsp { + u8 ss_ULevel[MAX_RATES_LENGTH]; +}; + + +struct setcountjudge_parm { + u8 count_judge[MAX_RATES_LENGTH]; +}; + +struct getcountjudge_parm { + u32 rsvd; +}; +struct getcountjudge_rsp { + u8 count_judge[MAX_RATES_LENGTH]; +}; + + +struct setratable_parm { + u8 ss_ForceUp[NumRates]; + u8 ss_ULevel[NumRates]; + u8 ss_DLevel[NumRates]; + u8 count_judge[NumRates]; +}; + +struct getratable_parm { + uint rsvd; +}; +struct getratable_rsp { + u8 ss_ForceUp[NumRates]; + u8 ss_ULevel[NumRates]; + u8 ss_DLevel[NumRates]; + u8 count_judge[NumRates]; +}; + + +//to get TX,RX retry count +struct gettxretrycnt_parm{ + unsigned int rsvd; +}; +struct gettxretrycnt_rsp{ + unsigned long tx_retrycnt; +}; + +struct getrxretrycnt_parm{ + unsigned int rsvd; +}; +struct getrxretrycnt_rsp{ + unsigned long rx_retrycnt; +}; + +//to get BCNOK,BCNERR count +struct getbcnokcnt_parm{ + unsigned int rsvd; +}; +struct getbcnokcnt_rsp{ + unsigned long bcnokcnt; +}; + +struct getbcnerrcnt_parm{ + unsigned int rsvd; +}; +struct getbcnerrcnt_rsp{ + unsigned long bcnerrcnt; +}; + +// to get current TX power level +struct getcurtxpwrlevel_parm{ + unsigned int rsvd; +}; +struct getcurtxpwrlevel_rsp{ + unsigned short tx_power; +}; + +struct setprobereqextraie_parm { + unsigned char e_id; + unsigned char ie_len; + unsigned char ie[0]; +}; + +struct setassocreqextraie_parm { + unsigned char e_id; + unsigned char ie_len; + unsigned char ie[0]; +}; + +struct setproberspextraie_parm { + unsigned char e_id; + unsigned char ie_len; + unsigned char ie[0]; +}; + +struct setassocrspextraie_parm { + unsigned char e_id; + unsigned char ie_len; + unsigned char ie[0]; +}; + + +struct addBaReq_parm +{ + unsigned int tid; + u8 addr[ETH_ALEN]; +}; + +struct addBaRsp_parm { + unsigned int tid; + unsigned int start_seq; + u8 addr[ETH_ALEN]; + u8 status; + u8 size; +}; + +/*H2C Handler index: 46 */ +struct set_ch_parm { + u8 ch; + u8 bw; + u8 ch_offset; +}; + +#ifdef MP_FIRMWARE_OFFLOAD +/*H2C Handler index: 47 */ +struct SetTxPower_parm +{ + u8 TxPower; +}; + +/*H2C Handler index: 48 */ +struct SwitchAntenna_parm +{ + u16 antenna_tx; + u16 antenna_rx; +// R_ANTENNA_SELECT_CCK cck_txrx; + u8 cck_txrx; +}; + +/*H2C Handler index: 49 */ +struct SetCrystalCap_parm +{ + u32 curr_crystalcap; +}; + +/*H2C Handler index: 50 */ +struct SetSingleCarrierTx_parm +{ + u8 bStart; +}; + +/*H2C Handler index: 51 */ +struct SetSingleToneTx_parm +{ + u8 bStart; + u8 curr_rfpath; +}; + +/*H2C Handler index: 52 */ +struct SetCarrierSuppressionTx_parm +{ + u8 bStart; + u32 curr_rateidx; +}; + +/*H2C Handler index: 53 */ +struct SetContinuousTx_parm +{ + u8 bStart; + u8 CCK_flag; /*1:CCK 2:OFDM*/ + u32 curr_rateidx; +}; + +/*H2C Handler index: 54 */ +struct SwitchBandwidth_parm +{ + u8 curr_bandwidth; +}; + +#endif /* MP_FIRMWARE_OFFLOAD */ + +/*H2C Handler index: 59 */ +struct SetChannelPlan_param +{ + const struct country_chplan *country_ent; + u8 channel_plan; +}; + +/*H2C Handler index: 60 */ +struct LedBlink_param +{ + PVOID pLed; +}; + +/*H2C Handler index: 61 */ +struct SetChannelSwitch_param +{ + u8 new_ch_no; +}; + +/*H2C Handler index: 62 */ +struct TDLSoption_param +{ + u8 addr[ETH_ALEN]; + u8 option; +}; + +/*H2C Handler index: 64 */ +struct RunInThread_param +{ + void (*func)(void*); + void *context; +}; + + +#define GEN_CMD_CODE(cmd) cmd ## _CMD_ + + +/* + +Result: +0x00: success +0x01: sucess, and check Response. +0x02: cmd ignored due to duplicated sequcne number +0x03: cmd dropped due to invalid cmd code +0x04: reserved. + +*/ + +#define H2C_RSP_OFFSET 512 + +#define H2C_SUCCESS 0x00 +#define H2C_SUCCESS_RSP 0x01 +#define H2C_DUPLICATED 0x02 +#define H2C_DROPPED 0x03 +#define H2C_PARAMETERS_ERROR 0x04 +#define H2C_REJECTED 0x05 +#define H2C_CMD_OVERFLOW 0x06 +#define H2C_RESERVED 0x07 +#define H2C_ENQ_HEAD 0x08 +#define H2C_ENQ_HEAD_FAIL 0x09 + +extern u8 rtw_setassocsta_cmd(_adapter *padapter, u8 *mac_addr); +extern u8 rtw_setstandby_cmd(_adapter *padapter, uint action); +u8 rtw_sitesurvey_cmd(_adapter *padapter, NDIS_802_11_SSID *ssid, int ssid_num, struct rtw_ieee80211_channel *ch, int ch_num); + +u8 rtw_create_ibss_cmd(_adapter *adapter, int flags); +u8 rtw_startbss_cmd(_adapter *adapter, int flags); +u8 rtw_change_bss_chbw_cmd(_adapter *adapter, int flags, u8 req_ch, u8 req_bw, u8 req_offset); + +extern u8 rtw_setphy_cmd(_adapter *padapter, u8 modem, u8 ch); + +struct sta_info; +extern u8 rtw_setstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 key_type, bool enqueue); +extern u8 rtw_clearstakey_cmd(_adapter *padapter, struct sta_info *sta, u8 enqueue); + +extern u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network* pnetwork); +u8 rtw_disassoc_cmd(_adapter *padapter, u32 deauth_timeout_ms, bool enqueue); +extern u8 rtw_setopmode_cmd(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype, bool enqueue); +extern u8 rtw_setdatarate_cmd(_adapter *padapter, u8 *rateset); +extern u8 rtw_setbasicrate_cmd(_adapter *padapter, u8 *rateset); +extern u8 rtw_getmacreg_cmd(_adapter *padapter, u8 len, u32 addr); +extern void rtw_usb_catc_trigger_cmd(_adapter *padapter, const char *caller); +extern u8 rtw_setbbreg_cmd(_adapter * padapter, u8 offset, u8 val); +extern u8 rtw_setrfreg_cmd(_adapter * padapter, u8 offset, u32 val); +extern u8 rtw_getbbreg_cmd(_adapter * padapter, u8 offset, u8 * pval); +extern u8 rtw_getrfreg_cmd(_adapter * padapter, u8 offset, u8 * pval); +extern u8 rtw_setrfintfs_cmd(_adapter *padapter, u8 mode); +extern u8 rtw_setrttbl_cmd(_adapter *padapter, struct setratable_parm *prate_table); +extern u8 rtw_getrttbl_cmd(_adapter *padapter, struct getratable_rsp *pval); + +extern u8 rtw_gettssi_cmd(_adapter *padapter, u8 offset,u8 *pval); +extern u8 rtw_setfwdig_cmd(_adapter*padapter, u8 type); +extern u8 rtw_setfwra_cmd(_adapter*padapter, u8 type); + +extern u8 rtw_addbareq_cmd(_adapter*padapter, u8 tid, u8 *addr); +extern u8 rtw_addbarsp_cmd(_adapter *padapter, u8 *addr, u16 tid, u8 status, u8 size, u16 start_seq); +// add for CONFIG_IEEE80211W, none 11w also can use +extern u8 rtw_reset_securitypriv_cmd(_adapter*padapter); +extern u8 rtw_free_assoc_resources_cmd(_adapter *padapter); +extern u8 rtw_dynamic_chk_wk_cmd(_adapter *adapter); + +u8 rtw_lps_ctrl_wk_cmd(_adapter*padapter, u8 lps_ctrl_type, u8 enqueue); +u8 rtw_dm_in_lps_wk_cmd(_adapter*padapter); +u8 rtw_lps_change_dtim_cmd(_adapter*padapter, u8 dtim); + +#if (RATE_ADAPTIVE_SUPPORT==1) +u8 rtw_rpt_timer_cfg_cmd(_adapter*padapter, u16 minRptTime); +#endif + +#ifdef CONFIG_ANTENNA_DIVERSITY +extern u8 rtw_antenna_select_cmd(_adapter*padapter, u8 antenna,u8 enqueue); +#endif + +u8 rtw_dm_ra_mask_wk_cmd(_adapter*padapter, u8 *psta); + +extern u8 rtw_ps_cmd(_adapter*padapter); + +#ifdef CONFIG_AP_MODE +u8 rtw_chk_hi_queue_cmd(_adapter*padapter); +#ifdef CONFIG_DFS_MASTER +u8 rtw_dfs_master_cmd(_adapter *adapter, bool enqueue); +void rtw_dfs_master_timer_hdl(RTW_TIMER_HDL_ARGS); +void rtw_dfs_master_enable(_adapter *adapter, u8 ch, u8 bw, u8 offset); +void rtw_dfs_master_disable(_adapter *adapter, bool ld_sta_in_dfs); +enum { + MLME_STA_CONNECTING, + MLME_STA_CONNECTED, + MLME_STA_DISCONNECTED, + MLME_AP_STARTED, + MLME_AP_STOPPED, +}; +void rtw_dfs_master_status_apply(_adapter *adapter, u8 self_action); +#endif /* CONFIG_DFS_MASTER */ +#endif /* CONFIG_AP_MODE */ + +#ifdef CONFIG_BT_COEXIST +u8 rtw_btinfo_cmd(PADAPTER padapter, u8 *pbuf, u16 length); +#endif + +u8 rtw_enable_hw_update_tsf_cmd(_adapter *padapter); + +u8 rtw_set_ch_cmd(_adapter*padapter, u8 ch, u8 bw, u8 ch_offset, u8 enqueue); + +u8 rtw_set_chplan_cmd(_adapter *adapter, int flags, u8 chplan, u8 swconfig); +u8 rtw_set_country_cmd(_adapter *adapter, int flags, const char *country_code, u8 swconfig); + +extern u8 rtw_led_blink_cmd(_adapter*padapter, PVOID pLed); +extern u8 rtw_set_csa_cmd(_adapter*padapter, u8 new_ch_no); +extern u8 rtw_tdls_cmd(_adapter *padapter, const u8 *addr, u8 option); + +u8 rtw_mp_cmd(_adapter *adapter, u8 mp_cmd_id, u8 flags); + +#ifdef CONFIG_RTW_CUSTOMER_STR +u8 rtw_customer_str_req_cmd(_adapter *adapter); +u8 rtw_customer_str_write_cmd(_adapter *adapter, const u8 *cstr); +#endif + +//#ifdef CONFIG_C2H_PACKET_EN +extern u8 rtw_c2h_packet_wk_cmd(PADAPTER padapter, u8 *pbuf, u16 length); +//#else +extern u8 rtw_c2h_wk_cmd(PADAPTER padapter, u8 *c2h_evt); +//#endif + +u8 rtw_run_in_thread_cmd(PADAPTER padapter, void (*func)(void*), void* context); + +u8 session_tracker_chk_cmd(_adapter *adapter, struct sta_info *sta); +u8 session_tracker_add_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port); +u8 session_tracker_del_cmd(_adapter *adapter, struct sta_info *sta, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port); + +u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf); + +extern void rtw_survey_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd); +extern void rtw_disassoc_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd); +extern void rtw_joinbss_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd); +void rtw_create_ibss_post_hdl(_adapter *padapter, int status); +extern void rtw_getbbrfreg_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd); +extern void rtw_readtssi_cmdrsp_callback(_adapter* padapter, struct cmd_obj *pcmd); + +extern void rtw_setstaKey_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd); +extern void rtw_setassocsta_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd); +extern void rtw_getrttbl_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd); +extern void rtw_getmacreg_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd); + + +struct _cmd_callback { + u32 cmd_code; + void (*callback)(_adapter *padapter, struct cmd_obj *cmd); +}; + +enum rtw_h2c_cmd +{ + GEN_CMD_CODE(_Read_MACREG) , /*0*/ + GEN_CMD_CODE(_Write_MACREG) , + GEN_CMD_CODE(_Read_BBREG) , + GEN_CMD_CODE(_Write_BBREG) , + GEN_CMD_CODE(_Read_RFREG) , + GEN_CMD_CODE(_Write_RFREG) , /*5*/ + GEN_CMD_CODE(_Read_EEPROM) , + GEN_CMD_CODE(_Write_EEPROM) , + GEN_CMD_CODE(_Read_EFUSE) , + GEN_CMD_CODE(_Write_EFUSE) , + + GEN_CMD_CODE(_Read_CAM) , /*10*/ + GEN_CMD_CODE(_Write_CAM) , + GEN_CMD_CODE(_setBCNITV), + GEN_CMD_CODE(_setMBIDCFG), + GEN_CMD_CODE(_JoinBss), /*14*/ + GEN_CMD_CODE(_DisConnect) , /*15*/ + GEN_CMD_CODE(_CreateBss) , + GEN_CMD_CODE(_SetOpMode) , + GEN_CMD_CODE(_SiteSurvey), /*18*/ + GEN_CMD_CODE(_SetAuth) , + + GEN_CMD_CODE(_SetKey) , /*20*/ + GEN_CMD_CODE(_SetStaKey) , + GEN_CMD_CODE(_SetAssocSta) , + GEN_CMD_CODE(_DelAssocSta) , + GEN_CMD_CODE(_SetStaPwrState) , + GEN_CMD_CODE(_SetBasicRate) , /*25*/ + GEN_CMD_CODE(_GetBasicRate) , + GEN_CMD_CODE(_SetDataRate) , + GEN_CMD_CODE(_GetDataRate) , + GEN_CMD_CODE(_SetPhyInfo) , + + GEN_CMD_CODE(_GetPhyInfo) , /*30*/ + GEN_CMD_CODE(_SetPhy) , + GEN_CMD_CODE(_GetPhy) , + GEN_CMD_CODE(_readRssi) , + GEN_CMD_CODE(_readGain) , + GEN_CMD_CODE(_SetAtim) , /*35*/ + GEN_CMD_CODE(_SetPwrMode) , + GEN_CMD_CODE(_JoinbssRpt), + GEN_CMD_CODE(_SetRaTable) , + GEN_CMD_CODE(_GetRaTable) , + + GEN_CMD_CODE(_GetCCXReport), /*40*/ + GEN_CMD_CODE(_GetDTMReport), + GEN_CMD_CODE(_GetTXRateStatistics), + GEN_CMD_CODE(_SetUsbSuspend), + GEN_CMD_CODE(_SetH2cLbk), + GEN_CMD_CODE(_AddBAReq) , /*45*/ + GEN_CMD_CODE(_SetChannel), /*46*/ + GEN_CMD_CODE(_SetTxPower), + GEN_CMD_CODE(_SwitchAntenna), + GEN_CMD_CODE(_SetCrystalCap), + GEN_CMD_CODE(_SetSingleCarrierTx), /*50*/ + + GEN_CMD_CODE(_SetSingleToneTx),/*51*/ + GEN_CMD_CODE(_SetCarrierSuppressionTx), + GEN_CMD_CODE(_SetContinuousTx), + GEN_CMD_CODE(_SwitchBandwidth), /*54*/ + GEN_CMD_CODE(_TX_Beacon), /*55*/ + + GEN_CMD_CODE(_Set_MLME_EVT), /*56*/ + GEN_CMD_CODE(_Set_Drv_Extra), /*57*/ + GEN_CMD_CODE(_Set_H2C_MSG), /*58*/ + + GEN_CMD_CODE(_SetChannelPlan), /*59*/ + GEN_CMD_CODE(_LedBlink), /*60*/ + + GEN_CMD_CODE(_SetChannelSwitch), /*61*/ + GEN_CMD_CODE(_TDLS), /*62*/ + GEN_CMD_CODE(_ChkBMCSleepq), /*63*/ + + GEN_CMD_CODE(_RunInThreadCMD), /*64*/ + GEN_CMD_CODE(_AddBARsp) , /*65*/ + + MAX_H2CCMD +}; + +#define _GetMACReg_CMD_ _Read_MACREG_CMD_ +#define _SetMACReg_CMD_ _Write_MACREG_CMD_ +#define _GetBBReg_CMD_ _Read_BBREG_CMD_ +#define _SetBBReg_CMD_ _Write_BBREG_CMD_ +#define _GetRFReg_CMD_ _Read_RFREG_CMD_ +#define _SetRFReg_CMD_ _Write_RFREG_CMD_ + +#ifdef _RTW_CMD_C_ +struct _cmd_callback rtw_cmd_callback[] = +{ + {GEN_CMD_CODE(_Read_MACREG), &rtw_getmacreg_cmdrsp_callback}, /*0*/ + {GEN_CMD_CODE(_Write_MACREG), NULL}, + {GEN_CMD_CODE(_Read_BBREG), &rtw_getbbrfreg_cmdrsp_callback}, + {GEN_CMD_CODE(_Write_BBREG), NULL}, + {GEN_CMD_CODE(_Read_RFREG), &rtw_getbbrfreg_cmdrsp_callback}, + {GEN_CMD_CODE(_Write_RFREG), NULL}, /*5*/ + {GEN_CMD_CODE(_Read_EEPROM), NULL}, + {GEN_CMD_CODE(_Write_EEPROM), NULL}, + {GEN_CMD_CODE(_Read_EFUSE), NULL}, + {GEN_CMD_CODE(_Write_EFUSE), NULL}, + + {GEN_CMD_CODE(_Read_CAM), NULL}, /*10*/ + {GEN_CMD_CODE(_Write_CAM), NULL}, + {GEN_CMD_CODE(_setBCNITV), NULL}, + {GEN_CMD_CODE(_setMBIDCFG), NULL}, + {GEN_CMD_CODE(_JoinBss), &rtw_joinbss_cmd_callback}, /*14*/ + {GEN_CMD_CODE(_DisConnect), &rtw_disassoc_cmd_callback}, /*15*/ + {GEN_CMD_CODE(_CreateBss), NULL}, + {GEN_CMD_CODE(_SetOpMode), NULL}, + {GEN_CMD_CODE(_SiteSurvey), &rtw_survey_cmd_callback}, /*18*/ + {GEN_CMD_CODE(_SetAuth), NULL}, + + {GEN_CMD_CODE(_SetKey), NULL}, /*20*/ + {GEN_CMD_CODE(_SetStaKey), &rtw_setstaKey_cmdrsp_callback}, + {GEN_CMD_CODE(_SetAssocSta), &rtw_setassocsta_cmdrsp_callback}, + {GEN_CMD_CODE(_DelAssocSta), NULL}, + {GEN_CMD_CODE(_SetStaPwrState), NULL}, + {GEN_CMD_CODE(_SetBasicRate), NULL}, /*25*/ + {GEN_CMD_CODE(_GetBasicRate), NULL}, + {GEN_CMD_CODE(_SetDataRate), NULL}, + {GEN_CMD_CODE(_GetDataRate), NULL}, + {GEN_CMD_CODE(_SetPhyInfo), NULL}, + + {GEN_CMD_CODE(_GetPhyInfo), NULL}, /*30*/ + {GEN_CMD_CODE(_SetPhy), NULL}, + {GEN_CMD_CODE(_GetPhy), NULL}, + {GEN_CMD_CODE(_readRssi), NULL}, + {GEN_CMD_CODE(_readGain), NULL}, + {GEN_CMD_CODE(_SetAtim), NULL}, /*35*/ + {GEN_CMD_CODE(_SetPwrMode), NULL}, + {GEN_CMD_CODE(_JoinbssRpt), NULL}, + {GEN_CMD_CODE(_SetRaTable), NULL}, + {GEN_CMD_CODE(_GetRaTable) , NULL}, + + {GEN_CMD_CODE(_GetCCXReport), NULL}, /*40*/ + {GEN_CMD_CODE(_GetDTMReport), NULL}, + {GEN_CMD_CODE(_GetTXRateStatistics), NULL}, + {GEN_CMD_CODE(_SetUsbSuspend), NULL}, + {GEN_CMD_CODE(_SetH2cLbk), NULL}, + {GEN_CMD_CODE(_AddBAReq), NULL}, /*45*/ + {GEN_CMD_CODE(_SetChannel), NULL}, /*46*/ + {GEN_CMD_CODE(_SetTxPower), NULL}, + {GEN_CMD_CODE(_SwitchAntenna), NULL}, + {GEN_CMD_CODE(_SetCrystalCap), NULL}, + {GEN_CMD_CODE(_SetSingleCarrierTx), NULL}, /*50*/ + + {GEN_CMD_CODE(_SetSingleToneTx), NULL}, /*51*/ + {GEN_CMD_CODE(_SetCarrierSuppressionTx), NULL}, + {GEN_CMD_CODE(_SetContinuousTx), NULL}, + {GEN_CMD_CODE(_SwitchBandwidth), NULL}, /*54*/ + {GEN_CMD_CODE(_TX_Beacon), NULL},/*55*/ + + {GEN_CMD_CODE(_Set_MLME_EVT), NULL},/*56*/ + {GEN_CMD_CODE(_Set_Drv_Extra), NULL},/*57*/ + {GEN_CMD_CODE(_Set_H2C_MSG), NULL},/*58*/ + {GEN_CMD_CODE(_SetChannelPlan), NULL},/*59*/ + {GEN_CMD_CODE(_LedBlink), NULL},/*60*/ + + {GEN_CMD_CODE(_SetChannelSwitch), NULL},/*61*/ + {GEN_CMD_CODE(_TDLS), NULL},/*62*/ + {GEN_CMD_CODE(_ChkBMCSleepq), NULL}, /*63*/ + + {GEN_CMD_CODE(_RunInThreadCMD), NULL},/*64*/ + {GEN_CMD_CODE(_AddBARsp), NULL}, /*65*/ +}; +#endif + +#define CMD_FMT "cmd=%d,%d,%d" +#define CMD_ARG(cmd) \ + (cmd)->cmdcode, \ + (cmd)->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra) ? ((struct drvextra_cmd_parm *)(cmd)->parmbuf)->ec_id : ((cmd)->cmdcode == GEN_CMD_CODE(_Set_MLME_EVT) ? ((struct C2HEvent_Header *)(cmd)->parmbuf)->ID : 0), \ + (cmd)->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra) ? ((struct drvextra_cmd_parm *)(cmd)->parmbuf)->type : 0 + +#endif // _CMD_H_ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_debug.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_debug.h new file mode 100644 index 000000000..d96dca25c --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_debug.h @@ -0,0 +1,583 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_DEBUG_H__ +#define __RTW_DEBUG_H__ + + +#define _drv_always_ 1 +#define _drv_emerg_ 2 +#define _drv_alert_ 3 +#define _drv_crit_ 4 +#define _drv_err_ 5 +#define _drv_warning_ 6 +#define _drv_notice_ 7 +#define _drv_info_ 8 +#define _drv_dump_ 9 +#define _drv_debug_ 10 + + +#define _module_rtl871x_xmit_c_ BIT(0) +#define _module_xmit_osdep_c_ BIT(1) +#define _module_rtl871x_recv_c_ BIT(2) +#define _module_recv_osdep_c_ BIT(3) +#define _module_rtl871x_mlme_c_ BIT(4) +#define _module_mlme_osdep_c_ BIT(5) +#define _module_rtl871x_sta_mgt_c_ BIT(6) +#define _module_rtl871x_cmd_c_ BIT(7) +#define _module_cmd_osdep_c_ BIT(8) +#define _module_rtl871x_io_c_ BIT(9) +#define _module_io_osdep_c_ BIT(10) +#define _module_os_intfs_c_ BIT(11) +#define _module_rtl871x_security_c_ BIT(12) +#define _module_rtl871x_eeprom_c_ BIT(13) +#define _module_hal_init_c_ BIT(14) +#define _module_hci_hal_init_c_ BIT(15) +#define _module_rtl871x_ioctl_c_ BIT(16) +#define _module_rtl871x_ioctl_set_c_ BIT(17) +#define _module_rtl871x_ioctl_query_c_ BIT(18) +#define _module_rtl871x_pwrctrl_c_ BIT(19) +#define _module_hci_intfs_c_ BIT(20) +#define _module_hci_ops_c_ BIT(21) +#define _module_osdep_service_c_ BIT(22) +#define _module_mp_ BIT(23) +#define _module_hci_ops_os_c_ BIT(24) +#define _module_rtl871x_ioctl_os_c BIT(25) +#define _module_rtl8712_cmd_c_ BIT(26) +//#define _module_efuse_ BIT(27) +#define _module_rtl8192c_xmit_c_ BIT(28) +#define _module_hal_xmit_c_ BIT(28) +#define _module_efuse_ BIT(29) +#define _module_rtl8712_recv_c_ BIT(30) +#define _module_rtl8712_led_c_ BIT(31) + +#undef _MODULE_DEFINE_ + +#if defined _RTW_XMIT_C_ + #define _MODULE_DEFINE_ _module_rtl871x_xmit_c_ +#elif defined _XMIT_OSDEP_C_ + #define _MODULE_DEFINE_ _module_xmit_osdep_c_ +#elif defined _RTW_RECV_C_ + #define _MODULE_DEFINE_ _module_rtl871x_recv_c_ +#elif defined _RECV_OSDEP_C_ + #define _MODULE_DEFINE_ _module_recv_osdep_c_ +#elif defined _RTW_MLME_C_ + #define _MODULE_DEFINE_ _module_rtl871x_mlme_c_ +#elif defined _MLME_OSDEP_C_ + #define _MODULE_DEFINE_ _module_mlme_osdep_c_ +#elif defined _RTW_MLME_EXT_C_ + #define _MODULE_DEFINE_ 1 +#elif defined _RTW_STA_MGT_C_ + #define _MODULE_DEFINE_ _module_rtl871x_sta_mgt_c_ +#elif defined _RTW_CMD_C_ + #define _MODULE_DEFINE_ _module_rtl871x_cmd_c_ +#elif defined _CMD_OSDEP_C_ + #define _MODULE_DEFINE_ _module_cmd_osdep_c_ +#elif defined _RTW_IO_C_ + #define _MODULE_DEFINE_ _module_rtl871x_io_c_ +#elif defined _IO_OSDEP_C_ + #define _MODULE_DEFINE_ _module_io_osdep_c_ +#elif defined _OS_INTFS_C_ + #define _MODULE_DEFINE_ _module_os_intfs_c_ +#elif defined _RTW_SECURITY_C_ + #define _MODULE_DEFINE_ _module_rtl871x_security_c_ +#elif defined _RTW_EEPROM_C_ + #define _MODULE_DEFINE_ _module_rtl871x_eeprom_c_ +#elif defined _HAL_INTF_C_ + #define _MODULE_DEFINE_ _module_hal_init_c_ +#elif (defined _HCI_HAL_INIT_C_) || (defined _SDIO_HALINIT_C_) + #define _MODULE_DEFINE_ _module_hci_hal_init_c_ +#elif defined _RTL871X_IOCTL_C_ + #define _MODULE_DEFINE_ _module_rtl871x_ioctl_c_ +#elif defined _RTL871X_IOCTL_SET_C_ + #define _MODULE_DEFINE_ _module_rtl871x_ioctl_set_c_ +#elif defined _RTL871X_IOCTL_QUERY_C_ + #define _MODULE_DEFINE_ _module_rtl871x_ioctl_query_c_ +#elif defined _RTL871X_PWRCTRL_C_ + #define _MODULE_DEFINE_ _module_rtl871x_pwrctrl_c_ +#elif defined _RTW_PWRCTRL_C_ + #define _MODULE_DEFINE_ 1 +#elif defined _HCI_INTF_C_ + #define _MODULE_DEFINE_ _module_hci_intfs_c_ +#elif defined _HCI_OPS_C_ + #define _MODULE_DEFINE_ _module_hci_ops_c_ +#elif defined _SDIO_OPS_C_ + #define _MODULE_DEFINE_ 1 +#elif defined _OSDEP_HCI_INTF_C_ + #define _MODULE_DEFINE_ _module_hci_intfs_c_ +#elif defined _OSDEP_SERVICE_C_ + #define _MODULE_DEFINE_ _module_osdep_service_c_ +#elif defined _HCI_OPS_OS_C_ + #define _MODULE_DEFINE_ _module_hci_ops_os_c_ +#elif defined _RTL871X_IOCTL_LINUX_C_ + #define _MODULE_DEFINE_ _module_rtl871x_ioctl_os_c +#elif defined _RTL8712_CMD_C_ + #define _MODULE_DEFINE_ _module_rtl8712_cmd_c_ +#elif defined _RTL8192C_XMIT_C_ + #define _MODULE_DEFINE_ 1 +#elif defined _RTL8723AS_XMIT_C_ + #define _MODULE_DEFINE_ 1 +#elif defined _RTL8712_RECV_C_ + #define _MODULE_DEFINE_ _module_rtl8712_recv_c_ +#elif defined _RTL8192CU_RECV_C_ + #define _MODULE_DEFINE_ _module_rtl8712_recv_c_ +#elif defined _RTL871X_MLME_EXT_C_ + #define _MODULE_DEFINE_ _module_mlme_osdep_c_ +#elif defined _RTW_MP_C_ + #define _MODULE_DEFINE_ _module_mp_ +#elif defined _RTW_MP_IOCTL_C_ + #define _MODULE_DEFINE_ _module_mp_ +#elif defined _RTW_EFUSE_C_ + #define _MODULE_DEFINE_ _module_efuse_ +#endif + +#ifdef PLATFORM_OS_CE +extern void rtl871x_cedbg(const char *fmt, ...); +#endif + +#define RT_TRACE(_Comp, _Level, Fmt) do{}while(0) +#define _func_enter_ do{}while(0) +#define _func_exit_ do{}while(0) +#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) do{}while(0) + +#ifdef PLATFORM_WINDOWS + #define DBG_871X do {} while(0) + #define MSG_8192C do {} while(0) + #define DBG_8192C do {} while(0) + #define DBG_871X_LEVEL do {} while(0) +#else + #define DBG_871X(x, ...) do {} while(0) + #define MSG_8192C(x, ...) do {} while(0) + #define DBG_8192C(x,...) do {} while(0) + #define DBG_871X_LEVEL(x,...) do {} while(0) + #define RTW_WARN(x, ...) do {} while(0) + #define RTW_INFO(x, ...) do {} while(0) +#endif + +#undef _dbgdump +#undef _seqdump + +#ifndef _RTL871X_DEBUG_C_ + extern u32 GlobalDebugLevel; + extern u64 GlobalDebugComponents; +#endif + +#if defined(PLATFORM_WINDOWS) && defined(PLATFORM_OS_XP) + #define _dbgdump DbgPrint + #define _seqdump(sel, fmt, arg...) _dbgdump(fmt, ##arg) +#elif defined(PLATFORM_WINDOWS) && defined(PLATFORM_OS_CE) + #define _dbgdump rtl871x_cedbg + #define _seqdump(sel, fmt, arg...) _dbgdump(fmt, ##arg) +#elif defined PLATFORM_LINUX + #define _dbgdump printk + #define _seqdump seq_printf +#elif defined PLATFORM_FREEBSD + #define _dbgdump printf + #define _seqdump(sel, fmt, arg...) _dbgdump(fmt, ##arg) +#endif + +#define DRIVER_PREFIX "RTL871X: " + +#if defined(_dbgdump) + +#define DBG_871X_EXP(level, EXP) do { if (level <= GlobalDebugLevel) EXP; } while (0) + +/* with driver-defined prefix */ +#undef DBG_871X_LEVEL +#define DBG_871X_LEVEL(level, fmt, arg...) \ + do {\ + if (level <= GlobalDebugLevel) {\ + if (level <= _drv_err_ && level > _drv_always_) \ + _dbgdump(DRIVER_PREFIX"ERROR " fmt, ##arg);\ + else \ + _dbgdump(DRIVER_PREFIX fmt, ##arg);\ + }\ + }while(0) + +/* without driver-defined prefix */ +#undef _DBG_871X_LEVEL +#define _DBG_871X_LEVEL(level, fmt, arg...) \ + do {\ + if (level <= GlobalDebugLevel) {\ + if (level <= _drv_err_ && level > _drv_always_) \ + _dbgdump("ERROR " fmt, ##arg);\ + else \ + _dbgdump(fmt, ##arg);\ + }\ + }while(0) + +#if defined(_seqdump) +#define RTW_DBGDUMP 0 /* 'stream' for _dbgdump */ + +/* dump message to selected 'stream' */ +#define DBG_871X_SEL(sel, fmt, arg...) \ + do {\ + if (sel == RTW_DBGDUMP)\ + _DBG_871X_LEVEL(_drv_always_, fmt, ##arg); \ + else {\ + _seqdump(sel, fmt, ##arg); \ + } \ + }while(0) + +/* dump message to selected 'stream' with driver-defined prefix */ +#define DBG_871X_SEL_NL(sel, fmt, arg...) \ + do {\ + if (sel == RTW_DBGDUMP)\ + DBG_871X_LEVEL(_drv_always_, fmt, ##arg); \ + else {\ + _seqdump(sel, fmt, ##arg) /*rtw_warn_on(1)*/; \ + } \ + }while(0) + +#define RTW_PRINT_SEL DBG_871X_SEL_NL +#define _RTW_PRINT_SEL DBG_871X_SEL +#endif /* defined(_seqdump) */ + +#endif /* defined(_dbgdump) */ + +#ifdef CONFIG_DEBUG +#if defined(_dbgdump) + #undef DBG_871X + #define DBG_871X(...) do {\ + _dbgdump(DRIVER_PREFIX __VA_ARGS__);\ + }while(0) + + #undef MSG_8192C + #define MSG_8192C(...) do {\ + _dbgdump(DRIVER_PREFIX __VA_ARGS__);\ + }while(0) + + #undef DBG_8192C + #define DBG_8192C(...) do {\ + _dbgdump(DRIVER_PREFIX __VA_ARGS__);\ + }while(0) + + #undef RTW_WARN + #define RTW_WARN(...) do {\ + _dbgdump(DRIVER_PREFIX"WARN " __VA_ARGS__);\ + }while(0) + + #undef RTW_INFO + #define RTW_INFO DBG_871X + + #undef RTW_INFO_DUMP + #define RTW_INFO_DUMP(_TitleString, _HexData, _HexDataLen) \ + do {\ + int __i; \ + u8 *ptr = (u8 *)_HexData; \ + _dbgdump("%s", DRIVER_PREFIX); \ + _dbgdump(_TitleString); \ + for (__i = 0; __i < (int)_HexDataLen; __i++) { \ + _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ + if (((__i + 1) % 16) == 0) \ + _dbgdump("\n"); \ + } \ + _dbgdump("\n"); \ + } while (0) + + #undef RTW_PRINT_DUMP + #define RTW_PRINT_DUMP(_TitleString, _HexData, _HexDataLen) \ + do {\ + int __i; \ + u8 *ptr = (u8 *)_HexData; \ + _dbgdump("%s", DRIVER_PREFIX); \ + _dbgdump(_TitleString); \ + for (__i = 0; __i < (int)_HexDataLen; __i++) { \ + _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0) ? " " : " "); \ + if (((__i + 1) % 16) == 0) \ + _dbgdump("\n"); \ + } \ + _dbgdump("\n"); \ + } while (0) + +#endif /* defined(_dbgdump) */ +#endif /* CONFIG_DEBUG */ + +#ifdef CONFIG_DEBUG_RTL871X + +#if defined(_dbgdump) && defined(_MODULE_DEFINE_) + + #undef RT_TRACE + #define RT_TRACE(_Comp, _Level, Fmt)\ + do {\ + if((_Comp & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) {\ + _dbgdump("%s [0x%08x,%d]", DRIVER_PREFIX, (unsigned int)_Comp, _Level);\ + _dbgdump Fmt;\ + }\ + }while(0) + +#endif /* defined(_dbgdump) && defined(_MODULE_DEFINE_) */ + + +#if defined(_dbgdump) + #undef _func_enter_ + #define _func_enter_ \ + do { \ + if (GlobalDebugLevel >= _drv_debug_) \ + { \ + _dbgdump("\n %s : %s enters at %d\n", DRIVER_PREFIX, __FUNCTION__, __LINE__);\ + } \ + } while(0) + + #undef _func_exit_ + #define _func_exit_ \ + do { \ + if (GlobalDebugLevel >= _drv_debug_) \ + { \ + _dbgdump("\n %s : %s exits at %d\n", DRIVER_PREFIX, __FUNCTION__, __LINE__); \ + } \ + } while(0) + + #undef RT_PRINT_DATA + #define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) \ + if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \ + { \ + int __i; \ + u8 *ptr = (u8 *)_HexData; \ + _dbgdump("%s", DRIVER_PREFIX); \ + _dbgdump(_TitleString); \ + for( __i=0; __i<(int)_HexDataLen; __i++ ) \ + { \ + _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" "); \ + if (((__i + 1) % 16) == 0) _dbgdump("\n"); \ + } \ + _dbgdump("\n"); \ + } +#endif /* defined(_dbgdump) */ +#endif /* CONFIG_DEBUG_RTL871X */ + +#ifdef CONFIG_DBG_COUNTER +#define DBG_COUNTER(counter) counter++ +#else +#define DBG_COUNTER(counter) +#endif + +void dump_drv_version(void *sel); +void dump_log_level(void *sel); +void dump_drv_cfg(void *sel); + +#ifdef CONFIG_SDIO_HCI +void sd_f0_reg_dump(void *sel, _adapter *adapter); +void sdio_local_reg_dump(void *sel, _adapter *adapter); +#endif /* CONFIG_SDIO_HCI */ + +void mac_reg_dump(void *sel, _adapter *adapter); +void bb_reg_dump(void *sel, _adapter *adapter); +void rf_reg_dump(void *sel, _adapter *adapter); + +bool rtw_fwdl_test_trigger_chksum_fail(void); +bool rtw_fwdl_test_trigger_wintint_rdy_fail(void); +bool rtw_del_rx_ampdu_test_trigger_no_tx_fail(void); + +u32 rtw_get_wait_hiq_empty_ms(void); +void rtw_sink_rtp_seq_dbg( _adapter *adapter,_pkt *pkt); + +struct sta_info; +void sta_rx_reorder_ctl_dump(void *sel, struct sta_info *sta); + +struct dvobj_priv; +void dump_adapters_status(void *sel, struct dvobj_priv *dvobj); + +struct sec_cam_ent; +void dump_sec_cam_ent(void *sel, struct sec_cam_ent *ent, int id); +void dump_sec_cam_ent_title(void *sel, u8 has_id); +void dump_sec_cam(void *sel, _adapter *adapter); + +#ifdef CONFIG_PROC_DEBUG +ssize_t proc_set_write_reg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_read_reg(struct seq_file *m, void *v); +ssize_t proc_set_read_reg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + +int proc_get_fwstate(struct seq_file *m, void *v); +int proc_get_sec_info(struct seq_file *m, void *v); +int proc_get_mlmext_state(struct seq_file *m, void *v); +#ifdef CONFIG_LAYER2_ROAMING +int proc_get_roam_flags(struct seq_file *m, void *v); +ssize_t proc_set_roam_flags(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_roam_param(struct seq_file *m, void *v); +ssize_t proc_set_roam_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +ssize_t proc_set_roam_tgt_addr(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#endif /* CONFIG_LAYER2_ROAMING */ +int proc_get_qos_option(struct seq_file *m, void *v); +int proc_get_ht_option(struct seq_file *m, void *v); +int proc_get_rf_info(struct seq_file *m, void *v); +int proc_get_scan_param(struct seq_file *m, void *v); +ssize_t proc_set_scan_param(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_scan_abort(struct seq_file *m, void *v); +#ifdef CONFIG_SCAN_BACKOP +int proc_get_backop_flags_sta(struct seq_file *m, void *v); +ssize_t proc_set_backop_flags_sta(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_backop_flags_ap(struct seq_file *m, void *v); +ssize_t proc_set_backop_flags_ap(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#endif /* CONFIG_SCAN_BACKOP */ +int proc_get_survey_info(struct seq_file *m, void *v); +ssize_t proc_set_survey_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_ap_info(struct seq_file *m, void *v); +ssize_t proc_reset_trx_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_trx_info(struct seq_file *m, void *v); +int proc_get_rate_ctl(struct seq_file *m, void *v); +int proc_get_wifi_spec(struct seq_file *m, void *v); +ssize_t proc_set_rate_ctl(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#ifdef DBG_RX_COUNTER_DUMP +int proc_get_rx_cnt_dump(struct seq_file *m, void *v); +ssize_t proc_set_rx_cnt_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#endif +int proc_get_dis_pwt(struct seq_file *m, void *v); +ssize_t proc_set_dis_pwt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + +int proc_get_suspend_resume_info(struct seq_file *m, void *v); + +ssize_t proc_set_fwdl_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +ssize_t proc_set_del_rx_ampdu_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#ifdef CONFIG_DFS_MASTER +int proc_get_dfs_master_test_case(struct seq_file *m, void *v); +ssize_t proc_set_dfs_master_test_case(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#endif /* CONFIG_DFS_MASTER */ +ssize_t proc_set_wait_hiq_empty(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + +#ifdef CONFIG_AP_MODE +int proc_get_all_sta_info(struct seq_file *m, void *v); +#endif /* CONFIG_AP_MODE */ + +#ifdef DBG_MEMORY_LEAK +int proc_get_malloc_cnt(struct seq_file *m, void *v); +#endif /* DBG_MEMORY_LEAK */ + +#ifdef CONFIG_FIND_BEST_CHANNEL +int proc_get_best_channel(struct seq_file *m, void *v); +ssize_t proc_set_best_channel(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#endif /* CONFIG_FIND_BEST_CHANNEL */ + +int proc_get_trx_info_debug(struct seq_file *m, void *v); + +int proc_get_rx_signal(struct seq_file *m, void *v); +ssize_t proc_set_rx_signal(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_hw_status(struct seq_file *m, void *v); + +#ifdef CONFIG_80211N_HT +int proc_get_ht_enable(struct seq_file *m, void *v); +ssize_t proc_set_ht_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + +int proc_get_bw_mode(struct seq_file *m, void *v); +ssize_t proc_set_bw_mode(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + +int proc_get_ampdu_enable(struct seq_file *m, void *v); +ssize_t proc_set_ampdu_enable(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + +int proc_get_mac_rptbuf(struct seq_file *m, void *v); + +int proc_get_rx_ampdu(struct seq_file *m, void *v); +ssize_t proc_set_rx_ampdu(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + +int proc_get_rx_stbc(struct seq_file *m, void *v); +ssize_t proc_set_rx_stbc(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + + +int proc_get_rx_ampdu_factor(struct seq_file *m, void *v); +ssize_t proc_set_rx_ampdu_factor(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + +int proc_get_rx_ampdu_density(struct seq_file *m, void *v); +ssize_t proc_set_rx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + +int proc_get_tx_ampdu_density(struct seq_file *m, void *v); +ssize_t proc_set_tx_ampdu_density(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#endif /* CONFIG_80211N_HT */ + +int proc_get_en_fwps(struct seq_file *m, void *v); +ssize_t proc_set_en_fwps(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + +//int proc_get_two_path_rssi(struct seq_file *m, void *v); +//int proc_get_rssi_disp(struct seq_file *m, void *v); +//ssize_t proc_set_rssi_disp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + +#ifdef CONFIG_BT_COEXIST +int proc_get_btcoex_dbg(struct seq_file *m, void *v); +ssize_t proc_set_btcoex_dbg(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_btcoex_info(struct seq_file *m, void *v); +#endif /* CONFIG_BT_COEXIST */ + +#if defined(DBG_CONFIG_ERROR_DETECT) +int proc_get_sreset(struct seq_file *m, void *v); +ssize_t proc_set_sreset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +#endif /* DBG_CONFIG_ERROR_DETECT */ + +int proc_get_odm_dbg_comp(struct seq_file *m, void *v); +ssize_t proc_set_odm_dbg_comp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_odm_dbg_level(struct seq_file *m, void *v); +ssize_t proc_set_odm_dbg_level(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + +int proc_get_odm_adaptivity(struct seq_file *m, void *v); +ssize_t proc_set_odm_adaptivity(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + +#ifdef CONFIG_DBG_COUNTER +int proc_get_rx_logs(struct seq_file *m, void *v); +int proc_get_tx_logs(struct seq_file *m, void *v); +int proc_get_int_logs(struct seq_file *m, void *v); +#endif + +#ifdef CONFIG_PCI_HCI +int proc_get_rx_ring(struct seq_file *m, void *v); +int proc_get_tx_ring(struct seq_file *m, void *v); +#endif + +#ifdef CONFIG_GPIO_WAKEUP +int proc_get_wowlan_gpio_info(struct seq_file *m, void *v); +ssize_t proc_set_wowlan_gpio_info(struct file *file, const char __user *buffer, + size_t count, loff_t *pos, void *data); +#endif /*CONFIG_GPIO_WAKEUP*/ + +#ifdef CONFIG_P2P_WOWLAN +int proc_get_p2p_wowlan_info(struct seq_file *m, void *v); +#endif /* CONFIG_P2P_WOWLAN */ + +int proc_get_new_bcn_max(struct seq_file *m, void *v); +ssize_t proc_set_new_bcn_max(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + +#ifdef CONFIG_POWER_SAVING +int proc_get_ps_info(struct seq_file *m, void *v); +#endif //CONFIG_POWER_SAVING + +#ifdef CONFIG_TDLS +int proc_get_tdls_info(struct seq_file *m, void *v); +#endif + +int proc_get_monitor(struct seq_file *m, void *v); +ssize_t proc_set_monitor(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + + +#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER +int proc_get_rtkm_info(struct seq_file *m, void *v); +#endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */ + +#ifdef CONFIG_IEEE80211W +ssize_t proc_set_tx_sa_query(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_tx_sa_query(struct seq_file *m, void *v); +ssize_t proc_set_tx_deauth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_tx_deauth(struct seq_file *m, void *v); +ssize_t proc_set_tx_auth(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +int proc_get_tx_auth(struct seq_file *m, void *v); +#endif /* CONFIG_IEEE80211W */ + +#endif /* CONFIG_PROC_DEBUG */ + +int proc_get_efuse_map(struct seq_file *m, void *v); +ssize_t proc_set_efuse_map(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); + +#endif //__RTW_DEBUG_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_eeprom.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_eeprom.h new file mode 100644 index 000000000..2da2a67b3 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_eeprom.h @@ -0,0 +1,123 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_EEPROM_H__ +#define __RTW_EEPROM_H__ + + +#define RTL8712_EEPROM_ID 0x8712 +//#define EEPROM_MAX_SIZE 256 + +#define HWSET_MAX_SIZE_128 128 +#define HWSET_MAX_SIZE_256 256 +#define HWSET_MAX_SIZE_512 512 +#define HWSET_MAX_SIZE_1024 1024 + +#define EEPROM_MAX_SIZE HWSET_MAX_SIZE_1024 + +#define CLOCK_RATE 50 //100us + +//- EEPROM opcodes +#define EEPROM_READ_OPCODE 06 +#define EEPROM_WRITE_OPCODE 05 +#define EEPROM_ERASE_OPCODE 07 +#define EEPROM_EWEN_OPCODE 19 // Erase/write enable +#define EEPROM_EWDS_OPCODE 16 // Erase/write disable + +//Country codes +#define USA 0x555320 +#define EUROPE 0x1 //temp, should be provided later +#define JAPAN 0x2 //temp, should be provided later + +// +// Customer ID, note that: +// This variable is initiailzed through EEPROM or registry, +// however, its definition may be different with that in EEPROM for +// EEPROM size consideration. So, we have to perform proper translation between them. +// Besides, CustomerID of registry has precedence of that of EEPROM. +// defined below. 060703, by rcnjko. +// +typedef enum _RT_CUSTOMER_ID +{ + RT_CID_DEFAULT = 0, + RT_CID_8187_ALPHA0 = 1, + RT_CID_8187_SERCOMM_PS = 2, + RT_CID_8187_HW_LED = 3, + RT_CID_8187_NETGEAR = 4, + RT_CID_WHQL = 5, + RT_CID_819x_CAMEO = 6, + RT_CID_819x_RUNTOP = 7, + RT_CID_819x_Senao = 8, + RT_CID_TOSHIBA = 9, // Merge by Jacken, 2008/01/31. + RT_CID_819x_Netcore = 10, + RT_CID_Nettronix = 11, + RT_CID_DLINK = 12, + RT_CID_PRONET = 13, + RT_CID_COREGA = 14, + RT_CID_CHINA_MOBILE = 15, + RT_CID_819x_ALPHA = 16, + RT_CID_819x_Sitecom = 17, + RT_CID_CCX = 18, // It's set under CCX logo test and isn't demanded for CCX functions, but for test behavior like retry limit and tx report. By Bruce, 2009-02-17. + RT_CID_819x_Lenovo = 19, + RT_CID_819x_QMI = 20, + RT_CID_819x_Edimax_Belkin = 21, + RT_CID_819x_Sercomm_Belkin = 22, + RT_CID_819x_CAMEO1 = 23, + RT_CID_819x_MSI = 24, + RT_CID_819x_Acer = 25, + RT_CID_819x_AzWave_ASUS = 26, + RT_CID_819x_AzWave = 27, // For AzWave in PCIe, The ID is AzWave use and not only Asus + RT_CID_819x_HP = 28, + RT_CID_819x_WNC_COREGA = 29, + RT_CID_819x_Arcadyan_Belkin = 30, + RT_CID_819x_SAMSUNG = 31, + RT_CID_819x_CLEVO = 32, + RT_CID_819x_DELL = 33, + RT_CID_819x_PRONETS = 34, + RT_CID_819x_Edimax_ASUS = 35, + RT_CID_NETGEAR = 36, + RT_CID_PLANEX = 37, + RT_CID_CC_C = 38, + RT_CID_819x_Xavi = 39, + RT_CID_LENOVO_CHINA = 40, + RT_CID_INTEL_CHINA = 41, + RT_CID_TPLINK_HPWR = 42, + RT_CID_819x_Sercomm_Netgear = 43, + RT_CID_819x_ALPHA_Dlink = 44,//add by ylb 20121012 for customer led for alpha + RT_CID_WNC_NEC = 45,//add by page for NEC + RT_CID_DNI_BUFFALO = 46,//add by page for NEC +}RT_CUSTOMER_ID, *PRT_CUSTOMER_ID; + +extern void eeprom_write16(_adapter *padapter, u16 reg, u16 data); +extern u16 eeprom_read16(_adapter *padapter, u16 reg); +extern void read_eeprom_content(_adapter *padapter); +extern void eeprom_read_sz(_adapter * padapter, u16 reg,u8* data, u32 sz); + +extern void read_eeprom_content_by_attrib(_adapter * padapter ); + +#ifdef PLATFORM_LINUX +#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE +extern int isAdaptorInfoFileValid(void); +extern int storeAdaptorInfoFile(char *path, u8 *efuse_data); +extern int retriveAdaptorInfoFile(char *path, u8 *efuse_data); +#endif //CONFIG_ADAPTOR_INFO_CACHING_FILE +#endif //PLATFORM_LINUX + +#endif //__RTL871X_EEPROM_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_efuse.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_efuse.h new file mode 100644 index 000000000..945ccf700 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_efuse.h @@ -0,0 +1,220 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_EFUSE_H__ +#define __RTW_EFUSE_H__ + + +#define EFUSE_ERROE_HANDLE 1 + +#define PG_STATE_HEADER 0x01 +#define PG_STATE_WORD_0 0x02 +#define PG_STATE_WORD_1 0x04 +#define PG_STATE_WORD_2 0x08 +#define PG_STATE_WORD_3 0x10 +#define PG_STATE_DATA 0x20 + +#define PG_SWBYTE_H 0x01 +#define PG_SWBYTE_L 0x02 + +#define PGPKT_DATA_SIZE 8 + +#define EFUSE_WIFI 0 +#define EFUSE_BT 1 + +enum _EFUSE_DEF_TYPE { + TYPE_EFUSE_MAX_SECTION = 0, + TYPE_EFUSE_REAL_CONTENT_LEN = 1, + TYPE_AVAILABLE_EFUSE_BYTES_BANK = 2, + TYPE_AVAILABLE_EFUSE_BYTES_TOTAL = 3, + TYPE_EFUSE_MAP_LEN = 4, + TYPE_EFUSE_PROTECT_BYTES_BANK = 5, + TYPE_EFUSE_CONTENT_LEN_BANK = 6, +}; + +#define EFUSE_MAX_MAP_LEN 512 + +#define EFUSE_MAX_HW_SIZE 512 +#define EFUSE_MAX_SECTION_BASE 16 + +#define EXT_HEADER(header) ((header & 0x1F ) == 0x0F) +#define ALL_WORDS_DISABLED(wde) ((wde & 0x0F) == 0x0F) +#define GET_HDR_OFFSET_2_0(header) ( (header & 0xE0) >> 5) + +#define EFUSE_REPEAT_THRESHOLD_ 3 + +#define IS_MASKED_MP(ic, txt, offset) (EFUSE_IsAddressMasked_MP_##ic##txt(offset)) +#define IS_MASKED_TC(ic, txt, offset) (EFUSE_IsAddressMasked_TC_##ic##txt(offset)) +#define GET_MASK_ARRAY_LEN_MP(ic, txt) (EFUSE_GetArrayLen_MP_##ic##txt()) +#define GET_MASK_ARRAY_LEN_TC(ic, txt) (EFUSE_GetArrayLen_TC_##ic##txt()) +#define GET_MASK_ARRAY_MP(ic, txt, offset) (EFUSE_GetMaskArray_MP_##ic##txt(offset)) +#define GET_MASK_ARRAY_TC(ic, txt, offset) (EFUSE_GetMaskArray_TC_##ic##txt(offset)) + + +#define IS_MASKED(ic, txt, offset) ( IS_MASKED_MP(ic,txt, offset) ) +#define GET_MASK_ARRAY_LEN(ic, txt) ( GET_MASK_ARRAY_LEN_MP(ic,txt) ) +#define GET_MASK_ARRAY(ic, txt, out) do { GET_MASK_ARRAY_MP(ic,txt, out);} while(0) + +//============================================= +// The following is for BT Efuse definition +//============================================= +#define EFUSE_BT_MAX_MAP_LEN 1024 +#define EFUSE_MAX_BANK 4 +#define EFUSE_MAX_BT_BANK (EFUSE_MAX_BANK-1) +//============================================= +/*--------------------------Define Parameters-------------------------------*/ +#define EFUSE_MAX_WORD_UNIT 4 + +/*------------------------------Define structure----------------------------*/ +typedef struct PG_PKT_STRUCT_A{ + u8 offset; + u8 word_en; + u8 data[8]; + u8 word_cnts; +}PGPKT_STRUCT,*PPGPKT_STRUCT; + +typedef enum +{ + ERR_SUCCESS = 0, + ERR_DRIVER_FAILURE, + ERR_IO_FAILURE, + ERR_WI_TIMEOUT, + ERR_WI_BUSY, + ERR_BAD_FORMAT, + ERR_INVALID_DATA, + ERR_NOT_ENOUGH_SPACE, + ERR_WRITE_PROTECT, + ERR_READ_BACK_FAIL, + ERR_OUT_OF_RANGE +} ERROR_CODE; + +/*------------------------------Define structure----------------------------*/ +typedef struct _EFUSE_HAL{ + u8 fakeEfuseBank; + u32 fakeEfuseUsedBytes; + u8 fakeEfuseContent[EFUSE_MAX_HW_SIZE]; + u8 fakeEfuseInitMap[EFUSE_MAX_MAP_LEN]; + u8 fakeEfuseModifiedMap[EFUSE_MAX_MAP_LEN]; + u32 EfuseUsedBytes; + u8 EfuseUsedPercentage; + + u16 BTEfuseUsedBytes; + u8 BTEfuseUsedPercentage; + u8 BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; + u8 BTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN]; + u8 BTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN]; + + u16 fakeBTEfuseUsedBytes; + u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; + u8 fakeBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN]; + u8 fakeBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN]; + + // EFUSE Configuration, initialized in HAL_CmnInitPGData(). + const u16 MaxSecNum_WiFi; + const u16 MaxSecNum_BT; + const u16 WordUnit; + const u16 PhysicalLen_WiFi; + const u16 PhysicalLen_BT; + const u16 LogicalLen_WiFi; + const u16 LogicalLen_BT; + const u16 BankSize; + const u16 TotalBankNum; + const u16 BankNum_WiFi; + const u16 BankNum_BT; + const u16 OOBProtectBytes; + const u16 ProtectBytes; + const u16 BankAvailBytes; + const u16 TotalAvailBytes_WiFi; + const u16 TotalAvailBytes_BT; + const u16 HeaderRetry; + const u16 DataRetry; + + ERROR_CODE Status; + +}EFUSE_HAL, *PEFUSE_HAL; + +extern u8 maskfileBuffer[32]; + +/*------------------------Export global variable----------------------------*/ +extern u8 fakeEfuseBank; +extern u32 fakeEfuseUsedBytes; +extern u8 fakeEfuseContent[]; +extern u8 fakeEfuseInitMap[]; +extern u8 fakeEfuseModifiedMap[]; + +extern u32 BTEfuseUsedBytes; +extern u8 BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; +extern u8 BTEfuseInitMap[]; +extern u8 BTEfuseModifiedMap[]; + +extern u32 fakeBTEfuseUsedBytes; +extern u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; +extern u8 fakeBTEfuseInitMap[]; +extern u8 fakeBTEfuseModifiedMap[]; +/*------------------------Export global variable----------------------------*/ +u8 efuse_bt_GetCurrentSize(PADAPTER padapter, u16 *size); +u16 efuse_bt_GetMaxSize(PADAPTER padapter); + +u8 efuse_GetCurrentSize(PADAPTER padapter, u16 *size); +u16 efuse_GetMaxSize(PADAPTER padapter); +u8 rtw_efuse_access(PADAPTER padapter, u8 bRead, u16 start_addr, u16 cnts, u8 *data); +u8 rtw_efuse_mask_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data); +u8 rtw_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data); +u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data); +u8 rtw_BT_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data); +u8 rtw_BT_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data); + +u16 Efuse_GetCurrentSize(PADAPTER pAdapter, u8 efuseType, BOOLEAN bPseudoTest); +u8 Efuse_CalculateWordCnts(u8 word_en); +void ReadEFuseByte(PADAPTER Adapter, u16 _offset, u8 *pbuf, BOOLEAN bPseudoTest) ; +void EFUSE_GetEfuseDefinition(PADAPTER pAdapter, u8 efuseType, u8 type, void *pOut, BOOLEAN bPseudoTest); +u8 efuse_OneByteRead(PADAPTER pAdapter, u16 addr, u8 *data, BOOLEAN bPseudoTest); +u8 efuse_OneByteWrite(PADAPTER pAdapter, u16 addr, u8 data, BOOLEAN bPseudoTest); + +void BTEfuse_PowerSwitch(PADAPTER pAdapter,u8 bWrite,u8 PwrState); +void Efuse_PowerSwitch(PADAPTER pAdapter,u8 bWrite,u8 PwrState); +int Efuse_PgPacketRead(PADAPTER pAdapter, u8 offset, u8 *data, BOOLEAN bPseudoTest); +int Efuse_PgPacketWrite(PADAPTER pAdapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest); +void efuse_WordEnableDataRead(u8 word_en, u8 *sourdata, u8 *targetdata); +u8 Efuse_WordEnableDataWrite(PADAPTER pAdapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest); + +u8 EFUSE_Read1Byte(PADAPTER pAdapter, u16 Address); +void EFUSE_ShadowMapUpdate(PADAPTER pAdapter, u8 efuseType, BOOLEAN bPseudoTest); +void EFUSE_ShadowRead(PADAPTER pAdapter, u8 Type, u16 Offset, u32 *Value); +u8 rtw_efuse_file_read(PADAPTER padapter,u8 *filepatch,u8 *buf, u32 len); + +#define MAC_HIDDEN_MAX_BW_NUM 8 +extern const u8 _mac_hidden_max_bw_to_hal_bw_cap[]; +#define mac_hidden_max_bw_to_hal_bw_cap(max_bw) (((max_bw) >= MAC_HIDDEN_MAX_BW_NUM) ? 0 : _mac_hidden_max_bw_to_hal_bw_cap[(max_bw)]) + +#define MAC_HIDDEN_PROTOCOL_NUM 4 +extern const u8 _mac_hidden_proto_to_hal_proto_cap[]; +#define mac_hidden_proto_to_hal_proto_cap(proto) (((proto) >= MAC_HIDDEN_PROTOCOL_NUM) ? 0 : _mac_hidden_proto_to_hal_proto_cap[(proto)]) + +u8 mac_hidden_wl_func_to_hal_wl_func(u8 func); + +#ifdef PLATFORM_LINUX +#ifdef CONFIG_EFUSE_CONFIG_FILE +u32 rtw_read_efuse_from_file(const char *path, u8 *buf); +u32 rtw_read_macaddr_from_file(const char *path, u8 *buf); +#endif /* CONFIG_EFUSE_CONFIG_FILE */ +#endif /* PLATFORM_LINUX */ + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_event.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_event.h new file mode 100644 index 000000000..06b8612cf --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_event.h @@ -0,0 +1,138 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_EVENT_H_ +#define _RTW_EVENT_H_ + +#ifdef CONFIG_H2CLBK +#include +#endif + +/* +Used to report a bss has been scanned + +*/ +struct survey_event { + WLAN_BSSID_EX bss; +}; + +/* +Used to report that the requested site survey has been done. + +bss_cnt indicates the number of bss that has been reported. + + +*/ +struct surveydone_event { + unsigned int bss_cnt; + +}; + +/* +Used to report the link result of joinning the given bss + + +join_res: +-1: authentication fail +-2: association fail +> 0: TID + +*/ +struct joinbss_event { + struct wlan_network network; +}; + +/* +Used to report a given STA has joinned the created BSS. +It is used in AP/Ad-HoC(M) mode. + + +*/ +struct stassoc_event { + unsigned char macaddr[6]; +}; + +struct stadel_event { + unsigned char macaddr[6]; + unsigned char rsvd[2]; //for reason + unsigned char locally_generated; + int mac_id; +}; + +struct addba_event +{ + unsigned int tid; +}; + +struct wmm_event +{ + unsigned char wmm; +}; + +#ifdef CONFIG_H2CLBK +struct c2hlbk_event{ + unsigned char mac[6]; + unsigned short s0; + unsigned short s1; + unsigned int w0; + unsigned char b0; + unsigned short s2; + unsigned char b1; + unsigned int w1; +}; +#endif//CONFIG_H2CLBK + +#define GEN_EVT_CODE(event) event ## _EVT_ + + + +struct fwevent { + u32 parmsize; + void (*event_callback)(_adapter *dev, u8 *pbuf); +}; + + +#define C2HEVENT_SZ 32 + +struct event_node{ + unsigned char *node; + unsigned char evt_code; + unsigned short evt_sz; + volatile int *caller_ff_tail; + int caller_ff_sz; +}; + +struct c2hevent_queue { + volatile int head; + volatile int tail; + struct event_node nodes[C2HEVENT_SZ]; + unsigned char seq; +}; + +#define NETWORK_QUEUE_SZ 4 + +struct network_queue { + volatile int head; + volatile int tail; + WLAN_BSSID_EX networks[NETWORK_QUEUE_SZ]; +}; + + +#endif // _WLANEVENT_H_ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_ht.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_ht.h new file mode 100644 index 000000000..1509dba62 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_ht.h @@ -0,0 +1,221 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_HT_H_ +#define _RTW_HT_H_ + + +struct ht_priv +{ + u8 ht_option; + u8 ampdu_enable;//for enable Tx A-MPDU + u8 tx_amsdu_enable;//for enable Tx A-MSDU + u8 bss_coexist;//for 20/40 Bss coexist + + //u8 baddbareq_issued[16]; + u32 tx_amsdu_maxlen; // 1: 8k, 0:4k ; default:8k, for tx + u32 rx_ampdu_maxlen; //for rx reordering ctrl win_sz, updated when join_callback. + + u8 rx_ampdu_min_spacing; + + u8 ch_offset;//PRIME_CHNL_OFFSET + u8 sgi_20m; + u8 sgi_40m; + + //for processing Tx A-MPDU + u8 agg_enable_bitmap; + //u8 ADDBA_retry_count; + u8 candidate_tid_bitmap; + + u8 ldpc_cap; + u8 stbc_cap; + u8 beamform_cap; + u8 smps_cap; /*spatial multiplexing power save mode. 0:static SMPS, 1:dynamic SMPS, 3:SMPS disabled, 2:reserved*/ + + struct rtw_ieee80211_ht_cap ht_cap; + +}; + +typedef enum AGGRE_SIZE{ + HT_AGG_SIZE_8K = 0, + HT_AGG_SIZE_16K = 1, + HT_AGG_SIZE_32K = 2, + HT_AGG_SIZE_64K = 3, + VHT_AGG_SIZE_128K = 4, + VHT_AGG_SIZE_256K = 5, + VHT_AGG_SIZE_512K = 6, + VHT_AGG_SIZE_1024K = 7, +}AGGRE_SIZE_E, *PAGGRE_SIZE_E; + +typedef enum _RT_HT_INF0_CAP{ + RT_HT_CAP_USE_TURBO_AGGR = 0x01, + RT_HT_CAP_USE_LONG_PREAMBLE = 0x02, + RT_HT_CAP_USE_AMPDU = 0x04, + RT_HT_CAP_USE_WOW = 0x8, + RT_HT_CAP_USE_SOFTAP = 0x10, + RT_HT_CAP_USE_92SE = 0x20, + RT_HT_CAP_USE_88C_92C = 0x40, + RT_HT_CAP_USE_AP_CLIENT_MODE = 0x80, // AP team request to reserve this bit, by Emily +}RT_HT_INF0_CAPBILITY, *PRT_HT_INF0_CAPBILITY; + +typedef enum _RT_HT_INF1_CAP{ + RT_HT_CAP_USE_VIDEO_CLIENT = 0x01, + RT_HT_CAP_USE_JAGUAR_BCUT = 0x02, + RT_HT_CAP_USE_JAGUAR_CCUT = 0x04, +}RT_HT_INF1_CAPBILITY, *PRT_HT_INF1_CAPBILITY; + +#define LDPC_HT_ENABLE_RX BIT0 +#define LDPC_HT_ENABLE_TX BIT1 +#define LDPC_HT_TEST_TX_ENABLE BIT2 +#define LDPC_HT_CAP_TX BIT3 + +#define STBC_HT_ENABLE_RX BIT0 +#define STBC_HT_ENABLE_TX BIT1 +#define STBC_HT_TEST_TX_ENABLE BIT2 +#define STBC_HT_CAP_TX BIT3 + +#define BEAMFORMING_HT_BEAMFORMER_ENABLE BIT0 // Declare our NIC supports beamformer +#define BEAMFORMING_HT_BEAMFORMEE_ENABLE BIT1 // Declare our NIC supports beamformee +#define BEAMFORMING_HT_BEAMFORMER_TEST BIT2 // Transmiting Beamforming no matter the target supports it or not +#define BEAMFORMING_HT_BEAMFORMER_STEER_NUM (BIT4|BIT5) +#define BEAMFORMING_HT_BEAMFORMEE_CHNL_EST_CAP (BIT6|BIT7) + +//------------------------------------------------------------ +// The HT Control field +//------------------------------------------------------------ +#define SET_HT_CTRL_CSI_STEERING(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart))+2, 6, 2, _val) +#define SET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart))+3, 0, 1, _val) +#define GET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+3, 0, 1) + +// 20/40 BSS Coexist +#define SET_EXT_CAPABILITY_ELE_BSS_COEXIST(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 0, 1, _val) +#define GET_EXT_CAPABILITY_ELE_BSS_COEXIST(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 0, 1) + +/* HT Capabilities Info field */ +#define HT_CAP_ELE_CAP_INFO(_pEleStart) ((u8 *)(_pEleStart)) +#define GET_HT_CAP_ELE_LDPC_CAP(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 0, 1) +#define GET_HT_CAP_ELE_CHL_WIDTH(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 1, 1) +#define GET_HT_CAP_ELE_SM_PS(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 2, 2) +#define GET_HT_CAP_ELE_GREENFIELD(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 4, 1) +#define GET_HT_CAP_ELE_SHORT_GI20M(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 5, 1) +#define GET_HT_CAP_ELE_SHORT_GI40M(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 6, 1) +#define GET_HT_CAP_ELE_TX_STBC(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 7, 1) +#define GET_HT_CAP_ELE_RX_STBC(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 0, 2) +#define GET_HT_CAP_ELE_DELAYED_BA(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 2, 1) +#define GET_HT_CAP_ELE_MAX_AMSDU_LENGTH(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 3, 1) +#define GET_HT_CAP_ELE_DSSS_CCK_40M(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 4, 1) +#define GET_HT_CAP_ELE_FORTY_INTOLERANT(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 6, 1) +#define GET_HT_CAP_ELE_LSIG_TXOP_PROTECT(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 7, 1) + +#define SET_HT_CAP_ELE_LDPC_CAP(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 0, 1, _val) +#define SET_HT_CAP_ELE_CHL_WIDTH(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 1, 1, _val) +#define SET_HT_CAP_ELE_SM_PS(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 2, 2, _val) +#define SET_HT_CAP_ELE_GREENFIELD(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 4, 1, _val) +#define SET_HT_CAP_ELE_SHORT_GI20M(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 5, 1, _val) +#define SET_HT_CAP_ELE_SHORT_GI40M(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 6, 1, _val) +#define SET_HT_CAP_ELE_TX_STBC(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 7, 1, _val) +#define SET_HT_CAP_ELE_RX_STBC(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 0, 2, _val) +#define SET_HT_CAP_ELE_DELAYED_BA(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 2, 1, _val) +#define SET_HT_CAP_ELE_MAX_AMSDU_LENGTH(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 3, 1, _val) +#define SET_HT_CAP_ELE_DSSS_CCK_40M(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 4, 1, _val) +#define SET_HT_CAP_ELE_FORTY_INTOLERANT(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 6, 1, _val) +#define SET_HT_CAP_ELE_LSIG_TXOP_PROTECT(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 7, 1, _val) + +/* A-MPDU Parameters field */ +#define HT_CAP_ELE_AMPDU_PARA(_pEleStart) (((u8 *)(_pEleStart))+2) +#define GET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+2, 0, 2) +#define GET_HT_CAP_ELE_MIN_MPDU_S_SPACE(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+2, 2, 3) + +#define HT_AMPDU_PARA_FMT "%02x " \ + "MAX AMPDU len:%u bytes, MIN MPDU Start Spacing:%u" + +#define HT_AMPDU_PARA_ARG(x) \ + *((u8*)(x)) \ + , (1 << (13+GET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(((u8*)x)-2)))-1 \ + , GET_HT_CAP_ELE_MIN_MPDU_S_SPACE(((u8*)x)-2) + +/* Supported MCS Set field */ +#define HT_CAP_ELE_SUP_MCS_SET(_pEleStart) (((u8 *)(_pEleStart))+3) +#define HT_CAP_ELE_RX_MCS_MAP(_pEleStart) HT_CAP_ELE_SUP_MCS_SET(_pEleStart) +#define GET_HT_CAP_ELE_RX_HIGHEST_DATA_RATE(_pEleStart) LE_BITS_TO_2BYTE(((u8 *)(_pEleStart))+13, 0, 10) +#define GET_HT_CAP_ELE_TX_MCS_DEF(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 0, 1) +#define GET_HT_CAP_ELE_TRX_MCS_NEQ(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 1, 1) +#define GET_HT_CAP_ELE_TX_MAX_SS(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 2, 2) +#define GET_HT_CAP_ELE_TX_UEQM(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 4, 1) + +#define HT_SUP_MCS_SET_FMT "%02x %02x %02x %02x %02x%02x%02x%02x%02x%02x" \ + /* "\n%02x%02x%02x%02x%02x%02x" */\ + " %uMbps %s%s%s" +#define HT_SUP_MCS_SET_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5], \ + ((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9] \ + /*,((u8 *)(x))[10],((u8 *)(x))[11], ((u8 *)(x))[12],((u8 *)(x))[13],((u8 *)(x))[14],((u8 *)(x))[15] */\ + , GET_HT_CAP_ELE_RX_HIGHEST_DATA_RATE(((u8 *)x)-3) \ + , GET_HT_CAP_ELE_TX_MCS_DEF(((u8 *)x)-3) ? "TX_MCS_DEF " : "" \ + , GET_HT_CAP_ELE_TRX_MCS_NEQ(((u8 *)x)-3) ? "TRX_MCS_NEQ " : "" \ + , GET_HT_CAP_ELE_TX_UEQM(((u8 *)x)-3) ? "TX_UEQM " : "" + +//TXBF Capabilities +#define SET_HT_CAP_TXBF_RECEIVE_NDP_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 3, 1, ((u8)_val)) +#define SET_HT_CAP_TXBF_TRANSMIT_NDP_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 4, 1, ((u8)_val)) +#define SET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 10, 1, ((u8)_val)) +#define SET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 15, 2, ((u8)_val)) +#define SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 23, 2, ((u8)_val)) +#define SET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(_pEleStart, _val) SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 27, 2, ((u8)_val)) + + +#define GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(_pEleStart) LE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 10, 1) +#define GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(_pEleStart) LE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 15, 2) +#define GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(_pEleStart) LE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 23, 2) +#define GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(_pEleStart) LE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 27, 2) + +/* HT Operation element */ + +#define GET_HT_OP_ELE_PRI_CHL(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 0, 8) +#define SET_HT_OP_ELE_PRI_CHL(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 0, 8, _val) + +/* HT Operation Info field */ +#define HT_OP_ELE_OP_INFO(_pEleStart) (((u8 *)(_pEleStart)) + 1) +#define GET_HT_OP_ELE_2ND_CHL_OFFSET(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 1, 0, 2) +#define GET_HT_OP_ELE_STA_CHL_WIDTH(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 1, 2, 1) +#define GET_HT_OP_ELE_RIFS_MODE(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 1, 3, 1) +#define GET_HT_OP_ELE_HT_PROTECT(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 2, 0, 2) +#define GET_HT_OP_ELE_NON_GREEN_PRESENT(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 2, 2, 1) +#define GET_HT_OP_ELE_OBSS_NON_HT_PRESENT(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 2, 4, 1) +#define GET_HT_OP_ELE_DUAL_BEACON(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 4, 6, 1) +#define GET_HT_OP_ELE_DUAL_CTS(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 4, 7, 1) +#define GET_HT_OP_ELE_STBC_BEACON(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 0, 1) +#define GET_HT_OP_ELE_LSIG_TXOP_PROTECT(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 1, 1) +#define GET_HT_OP_ELE_PCO_ACTIVE(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 2, 1) +#define GET_HT_OP_ELE_PCO_PHASE(_pEleStart) LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 3, 1) + +#define SET_HT_OP_ELE_2ND_CHL_OFFSET(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 0, 2, _val) +#define SET_HT_OP_ELE_STA_CHL_WIDTH(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 2, 1, _val) +#define SET_HT_OP_ELE_RIFS_MODE(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 3, 1, _val) +#define SET_HT_OP_ELE_HT_PROTECT(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 0, 2, _val) +#define SET_HT_OP_ELE_NON_GREEN_PRESENT(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 2, 1, _val) +#define SET_HT_OP_ELE_OBSS_NON_HT_PRESENT(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 4, 1, _val) +#define SET_HT_OP_ELE_DUAL_BEACON(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 4, 6, 1, _val) +#define SET_HT_OP_ELE_DUAL_CTS(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 4, 7, 1, _val) +#define SET_HT_OP_ELE_STBC_BEACON(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 0, 1, _val) +#define SET_HT_OP_ELE_LSIG_TXOP_PROTECT(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 1, 1, _val) +#define SET_HT_OP_ELE_PCO_ACTIVE(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 2, 1, _val) +#define SET_HT_OP_ELE_PCO_PHASE(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 3, 1, _val) + +#endif //_RTL871X_HT_H_ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_io.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_io.h new file mode 100644 index 000000000..1b031f57e --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_io.h @@ -0,0 +1,578 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#ifndef _RTW_IO_H_ +#define _RTW_IO_H_ + +#define NUM_IOREQ 8 + +#ifdef PLATFORM_WINDOWS +#define MAX_PROT_SZ 64 +#endif +#ifdef PLATFORM_LINUX +#define MAX_PROT_SZ (64-16) +#endif + +#define _IOREADY 0 +#define _IO_WAIT_COMPLETE 1 +#define _IO_WAIT_RSP 2 + +// IO COMMAND TYPE +#define _IOSZ_MASK_ (0x7F) +#define _IO_WRITE_ BIT(7) +#define _IO_FIXED_ BIT(8) +#define _IO_BURST_ BIT(9) +#define _IO_BYTE_ BIT(10) +#define _IO_HW_ BIT(11) +#define _IO_WORD_ BIT(12) +#define _IO_SYNC_ BIT(13) +#define _IO_CMDMASK_ (0x1F80) + + +/* + For prompt mode accessing, caller shall free io_req + Otherwise, io_handler will free io_req +*/ + + + +// IO STATUS TYPE +#define _IO_ERR_ BIT(2) +#define _IO_SUCCESS_ BIT(1) +#define _IO_DONE_ BIT(0) + + +#define IO_RD32 (_IO_SYNC_ | _IO_WORD_) +#define IO_RD16 (_IO_SYNC_ | _IO_HW_) +#define IO_RD8 (_IO_SYNC_ | _IO_BYTE_) + +#define IO_RD32_ASYNC (_IO_WORD_) +#define IO_RD16_ASYNC (_IO_HW_) +#define IO_RD8_ASYNC (_IO_BYTE_) + +#define IO_WR32 (_IO_WRITE_ | _IO_SYNC_ | _IO_WORD_) +#define IO_WR16 (_IO_WRITE_ | _IO_SYNC_ | _IO_HW_) +#define IO_WR8 (_IO_WRITE_ | _IO_SYNC_ | _IO_BYTE_) + +#define IO_WR32_ASYNC (_IO_WRITE_ | _IO_WORD_) +#define IO_WR16_ASYNC (_IO_WRITE_ | _IO_HW_) +#define IO_WR8_ASYNC (_IO_WRITE_ | _IO_BYTE_) + +/* + + Only Sync. burst accessing is provided. + +*/ + +#define IO_WR_BURST(x) (_IO_WRITE_ | _IO_SYNC_ | _IO_BURST_ | ( (x) & _IOSZ_MASK_)) +#define IO_RD_BURST(x) (_IO_SYNC_ | _IO_BURST_ | ( (x) & _IOSZ_MASK_)) + + + +//below is for the intf_option bit defition... + +#define _INTF_ASYNC_ BIT(0) //support async io + +struct intf_priv; +struct intf_hdl; +struct io_queue; + +struct _io_ops +{ + u8 (*_read8)(struct intf_hdl *pintfhdl, u32 addr); + u16 (*_read16)(struct intf_hdl *pintfhdl, u32 addr); + u32 (*_read32)(struct intf_hdl *pintfhdl, u32 addr); + + int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val); + int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val); + int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val); + int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata); + + int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val); + int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val); + int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val); + + void (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); + void (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); + + void (*_sync_irp_protocol_rw)(struct io_queue *pio_q); + + u32 (*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr); + + u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); + u32 (*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); + + u32 (*_write_scsi)(struct intf_hdl *pintfhdl,u32 cnt, u8 *pmem); + + void (*_read_port_cancel)(struct intf_hdl *pintfhdl); + void (*_write_port_cancel)(struct intf_hdl *pintfhdl); + +#ifdef CONFIG_SDIO_HCI + u8 (*_sd_f0_read8)(struct intf_hdl *pintfhdl, u32 addr); + #ifdef CONFIG_SDIO_INDIRECT_ACCESS + u8 (*_sd_iread8)(struct intf_hdl *pintfhdl, u32 addr); + u16 (*_sd_iread16)(struct intf_hdl *pintfhdl, u32 addr); + u32 (*_sd_iread32)(struct intf_hdl *pintfhdl, u32 addr); + int (*_sd_iwrite8)(struct intf_hdl *pintfhdl, u32 addr, u8 val); + int (*_sd_iwrite16)(struct intf_hdl *pintfhdl, u32 addr, u16 val); + int (*_sd_iwrite32)(struct intf_hdl *pintfhdl, u32 addr, u32 val); + #endif /* CONFIG_SDIO_INDIRECT_ACCESS */ +#endif + +}; + +struct io_req { + _list list; + u32 addr; + volatile u32 val; + u32 command; + u32 status; + u8 *pbuf; + _sema sema; + +#ifdef PLATFORM_OS_CE +#ifdef CONFIG_USB_HCI + // URB handler for rtw_write_mem + USB_TRANSFER usb_transfer_write_mem; +#endif +#endif + + void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt); + u8 *cnxt; + +#ifdef PLATFORM_OS_XP + PMDL pmdl; + PIRP pirp; + +#ifdef CONFIG_SDIO_HCI + PSDBUS_REQUEST_PACKET sdrp; +#endif + +#endif + + +}; + +struct intf_hdl { + +/* + u32 intf_option; + u32 bus_status; + u32 do_flush; + u8 *adapter; + u8 *intf_dev; + struct intf_priv *pintfpriv; + u8 cnt; + void (*intf_hdl_init)(u8 *priv); + void (*intf_hdl_unload)(u8 *priv); + void (*intf_hdl_open)(u8 *priv); + void (*intf_hdl_close)(u8 *priv); + struct _io_ops io_ops; + //u8 intf_status;//moved to struct intf_priv + u16 len; + u16 done_len; +*/ + _adapter *padapter; + struct dvobj_priv *pintf_dev;// pointer to &(padapter->dvobjpriv); + + struct _io_ops io_ops; + +}; + +struct reg_protocol_rd { + +#ifdef CONFIG_LITTLE_ENDIAN + + //DW1 + u32 NumOfTrans:4; + u32 Reserved1:4; + u32 Reserved2:24; + //DW2 + u32 ByteCount:7; + u32 WriteEnable:1; //0:read, 1:write + u32 FixOrContinuous:1; //0:continuous, 1: Fix + u32 BurstMode:1; + u32 Byte1Access:1; + u32 Byte2Access:1; + u32 Byte4Access:1; + u32 Reserved3:3; + u32 Reserved4:16; + //DW3 + u32 BusAddress; + //DW4 + //u32 Value; +#else + + +//DW1 + u32 Reserved1 :4; + u32 NumOfTrans :4; + + u32 Reserved2 :24; + + //DW2 + u32 WriteEnable : 1; + u32 ByteCount :7; + + + u32 Reserved3 : 3; + u32 Byte4Access : 1; + + u32 Byte2Access : 1; + u32 Byte1Access : 1; + u32 BurstMode :1 ; + u32 FixOrContinuous : 1; + + u32 Reserved4 : 16; + + //DW3 + u32 BusAddress; + + //DW4 + //u32 Value; + +#endif + +}; + + +struct reg_protocol_wt { + + +#ifdef CONFIG_LITTLE_ENDIAN + + //DW1 + u32 NumOfTrans:4; + u32 Reserved1:4; + u32 Reserved2:24; + //DW2 + u32 ByteCount:7; + u32 WriteEnable:1; //0:read, 1:write + u32 FixOrContinuous:1; //0:continuous, 1: Fix + u32 BurstMode:1; + u32 Byte1Access:1; + u32 Byte2Access:1; + u32 Byte4Access:1; + u32 Reserved3:3; + u32 Reserved4:16; + //DW3 + u32 BusAddress; + //DW4 + u32 Value; + +#else + //DW1 + u32 Reserved1 :4; + u32 NumOfTrans :4; + + u32 Reserved2 :24; + + //DW2 + u32 WriteEnable : 1; + u32 ByteCount :7; + + u32 Reserved3 : 3; + u32 Byte4Access : 1; + + u32 Byte2Access : 1; + u32 Byte1Access : 1; + u32 BurstMode :1 ; + u32 FixOrContinuous : 1; + + u32 Reserved4 : 16; + + //DW3 + u32 BusAddress; + + //DW4 + u32 Value; + +#endif + +}; +#ifdef CONFIG_PCI_HCI +#define MAX_CONTINUAL_IO_ERR 4 +#endif + +#ifdef CONFIG_USB_HCI +#define MAX_CONTINUAL_IO_ERR 4 +#endif + +#ifdef CONFIG_SDIO_HCI +#define SD_IO_TRY_CNT (8) +#define MAX_CONTINUAL_IO_ERR SD_IO_TRY_CNT +#endif + +#ifdef CONFIG_GSPI_HCI +#define SD_IO_TRY_CNT (8) +#define MAX_CONTINUAL_IO_ERR SD_IO_TRY_CNT +#endif + + +int rtw_inc_and_chk_continual_io_error(struct dvobj_priv *dvobj); +void rtw_reset_continual_io_error(struct dvobj_priv *dvobj); + +/* +Below is the data structure used by _io_handler + +*/ + +struct io_queue { + _lock lock; + _list free_ioreqs; + _list pending; //The io_req list that will be served in the single protocol read/write. + _list processing; + u8 *free_ioreqs_buf; // 4-byte aligned + u8 *pallocated_free_ioreqs_buf; + struct intf_hdl intf; +}; + +struct io_priv{ + + _adapter *padapter; + + struct intf_hdl intf; + +}; + +extern uint ioreq_flush(_adapter *adapter, struct io_queue *ioqueue); +extern void sync_ioreq_enqueue(struct io_req *preq,struct io_queue *ioqueue); +extern uint sync_ioreq_flush(_adapter *adapter, struct io_queue *ioqueue); + + +extern uint free_ioreq(struct io_req *preq, struct io_queue *pio_queue); +extern struct io_req *alloc_ioreq(struct io_queue *pio_q); + +extern uint register_intf_hdl(u8 *dev, struct intf_hdl *pintfhdl); +extern void unregister_intf_hdl(struct intf_hdl *pintfhdl); + +extern void _rtw_attrib_read(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); +extern void _rtw_attrib_write(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); + +extern u8 _rtw_read8(_adapter *adapter, u32 addr); +extern u16 _rtw_read16(_adapter *adapter, u32 addr); +extern u32 _rtw_read32(_adapter *adapter, u32 addr); +extern void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); +extern void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); +extern void _rtw_read_port_cancel(_adapter *adapter); + + +extern int _rtw_write8(_adapter *adapter, u32 addr, u8 val); +extern int _rtw_write16(_adapter *adapter, u32 addr, u16 val); +extern int _rtw_write32(_adapter *adapter, u32 addr, u32 val); +extern int _rtw_writeN(_adapter *adapter, u32 addr, u32 length, u8 *pdata); + +#ifdef CONFIG_SDIO_HCI +u8 _rtw_sd_f0_read8(_adapter *adapter, u32 addr); +#ifdef CONFIG_SDIO_INDIRECT_ACCESS +u8 _rtw_sd_iread8(_adapter *adapter, u32 addr); +u16 _rtw_sd_iread16(_adapter *adapter, u32 addr); +u32 _rtw_sd_iread32(_adapter *adapter, u32 addr); +int _rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val); +int _rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val); +int _rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val); +#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ +#endif /* CONFIG_SDIO_HCI */ + +extern int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val); +extern int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val); +extern int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val); + +extern void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); +extern u32 _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); +u32 _rtw_write_port_and_wait(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem, int timeout_ms); +extern void _rtw_write_port_cancel(_adapter *adapter); + +#ifdef DBG_IO +bool match_read_sniff_ranges(u32 addr, u16 len); +bool match_write_sniff_ranges(u32 addr, u16 len); +bool match_rf_read_sniff_ranges(u8 path, u32 addr, u32 mask); +bool match_rf_write_sniff_ranges(u8 path, u32 addr, u32 mask); + +extern u8 dbg_rtw_read8(_adapter *adapter, u32 addr, const char *caller, const int line); +extern u16 dbg_rtw_read16(_adapter *adapter, u32 addr, const char *caller, const int line); +extern u32 dbg_rtw_read32(_adapter *adapter, u32 addr, const char *caller, const int line); + +extern int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line); +extern int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line); +extern int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line); +extern int dbg_rtw_writeN(_adapter *adapter, u32 addr ,u32 length , u8 *data, const char *caller, const int line); + +#ifdef CONFIG_SDIO_HCI +u8 dbg_rtw_sd_f0_read8(_adapter *adapter, u32 addr, const char *caller, const int line); +#ifdef CONFIG_SDIO_INDIRECT_ACCESS +u8 dbg_rtw_sd_iread8(_adapter *adapter, u32 addr, const char *caller, const int line); +u16 dbg_rtw_sd_iread16(_adapter *adapter, u32 addr, const char *caller, const int line); +u32 dbg_rtw_sd_iread32(_adapter *adapter, u32 addr, const char *caller, const int line); +int dbg_rtw_sd_iwrite8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line); +int dbg_rtw_sd_iwrite16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line); +int dbg_rtw_sd_iwrite32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line); +#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ +#endif /* CONFIG_SDIO_HCI */ + +#define rtw_read8(adapter, addr) dbg_rtw_read8((adapter), (addr), __FUNCTION__, __LINE__) +#define rtw_read16(adapter, addr) dbg_rtw_read16((adapter), (addr), __FUNCTION__, __LINE__) +#define rtw_read32(adapter, addr) dbg_rtw_read32((adapter), (addr), __FUNCTION__, __LINE__) +#define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem)) +#define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem)) +#define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter)) + +#define rtw_write8(adapter, addr, val) dbg_rtw_write8((adapter), (addr), (val), __FUNCTION__, __LINE__) +#define rtw_write16(adapter, addr, val) dbg_rtw_write16((adapter), (addr), (val), __FUNCTION__, __LINE__) +#define rtw_write32(adapter, addr, val) dbg_rtw_write32((adapter), (addr), (val), __FUNCTION__, __LINE__) +#define rtw_writeN(adapter, addr, length, data) dbg_rtw_writeN((adapter), (addr), (length), (data), __FUNCTION__, __LINE__) + +#define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val)) +#define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val)) +#define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val)) + +#define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), addr, cnt, mem) +#define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port(adapter, addr, cnt, mem) +#define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms)) +#define rtw_write_port_cancel(adapter) _rtw_write_port_cancel(adapter) + +#ifdef CONFIG_SDIO_HCI +#define rtw_sd_f0_read8(adapter, addr) dbg_rtw_sd_f0_read8((adapter), (addr), __func__, __LINE__) +#ifdef CONFIG_SDIO_INDIRECT_ACCESS +#define rtw_sd_iread8(adapter, addr) dbg_rtw_sd_iread8((adapter), (addr), __func__, __LINE__) +#define rtw_sd_iread16(adapter, addr) dbg_rtw_sd_iread16((adapter), (addr), __func__, __LINE__) +#define rtw_sd_iread32(adapter, addr) dbg_rtw_sd_iread32((adapter), (addr), __func__, __LINE__) +#define rtw_sd_iwrite8(adapter, addr, val) dbg_rtw_sd_iwrite8((adapter), (addr), (val), __func__, __LINE__) +#define rtw_sd_iwrite16(adapter, addr, val) dbg_rtw_sd_iwrite16((adapter), (addr), (val), __func__, __LINE__) +#define rtw_sd_iwrite32(adapter, addr, val) dbg_rtw_sd_iwrite32((adapter), (addr), (val), __func__, __LINE__) +#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ +#endif /* CONFIG_SDIO_HCI */ + +#else /* DBG_IO */ +#define match_read_sniff_ranges(addr, len) _FALSE +#define match_write_sniff_ranges(addr, len) _FALSE +#define match_rf_read_sniff_ranges(path, addr, mask) _FALSE +#define match_rf_write_sniff_ranges(path, addr, mask) _FALSE +#define rtw_read8(adapter, addr) _rtw_read8((adapter), (addr)) +#define rtw_read16(adapter, addr) _rtw_read16((adapter), (addr)) +#define rtw_read32(adapter, addr) _rtw_read32((adapter), (addr)) +#define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem)) +#define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem)) +#define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter)) + +#define rtw_write8(adapter, addr, val) _rtw_write8((adapter), (addr), (val)) +#define rtw_write16(adapter, addr, val) _rtw_write16((adapter), (addr), (val)) +#define rtw_write32(adapter, addr, val) _rtw_write32((adapter), (addr), (val)) +#define rtw_writeN(adapter, addr, length, data) _rtw_writeN((adapter), (addr), (length), (data)) + +#define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val)) +#define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val)) +#define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val)) + +#define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), (addr), (cnt), (mem)) +#define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port((adapter), (addr), (cnt), (mem)) +#define rtw_write_port_and_wait(adapter, addr, cnt, mem, timeout_ms) _rtw_write_port_and_wait((adapter), (addr), (cnt), (mem), (timeout_ms)) +#define rtw_write_port_cancel(adapter) _rtw_write_port_cancel((adapter)) + +#ifdef CONFIG_SDIO_HCI +#define rtw_sd_f0_read8(adapter, addr) _rtw_sd_f0_read8((adapter), (addr)) +#ifdef CONFIG_SDIO_INDIRECT_ACCESS +#define rtw_sd_iread8(adapter, addr) _rtw_sd_iread8((adapter), (addr)) +#define rtw_sd_iread16(adapter, addr) _rtw_sd_iread16((adapter), (addr)) +#define rtw_sd_iread32(adapter, addr) _rtw_sd_iread32((adapter), (addr)) +#define rtw_sd_iwrite8(adapter, addr, val) _rtw_sd_iwrite8((adapter), (addr), (val)) +#define rtw_sd_iwrite16(adapter, addr, val) _rtw_sd_iwrite16((adapter), (addr), (val)) +#define rtw_sd_iwrite32(adapter, addr, val) _rtw_sd_iwrite32((adapter), (addr), (val)) +#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ +#endif /* CONFIG_SDIO_HCI */ + +#endif /* DBG_IO */ + +extern void rtw_write_scsi(_adapter *adapter, u32 cnt, u8 *pmem); + +//ioreq +extern void ioreq_read8(_adapter *adapter, u32 addr, u8 *pval); +extern void ioreq_read16(_adapter *adapter, u32 addr, u16 *pval); +extern void ioreq_read32(_adapter *adapter, u32 addr, u32 *pval); +extern void ioreq_write8(_adapter *adapter, u32 addr, u8 val); +extern void ioreq_write16(_adapter *adapter, u32 addr, u16 val); +extern void ioreq_write32(_adapter *adapter, u32 addr, u32 val); + + +extern uint async_read8(_adapter *adapter, u32 addr, u8 *pbuff, + void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); +extern uint async_read16(_adapter *adapter, u32 addr, u8 *pbuff, + void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); +extern uint async_read32(_adapter *adapter, u32 addr, u8 *pbuff, + void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); + +extern void async_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); +extern void async_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); + +extern void async_write8(_adapter *adapter, u32 addr, u8 val, + void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); +extern void async_write16(_adapter *adapter, u32 addr, u16 val, + void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); +extern void async_write32(_adapter *adapter, u32 addr, u32 val, + void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); + +extern void async_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); +extern void async_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); + + +int rtw_init_io_priv(_adapter *padapter, void (*set_intf_ops)(_adapter *padapter,struct _io_ops *pops)); + + +extern uint alloc_io_queue(_adapter *adapter); +extern void free_io_queue(_adapter *adapter); +extern void async_bus_io(struct io_queue *pio_q); +extern void bus_sync_io(struct io_queue *pio_q); +extern u32 _ioreq2rwmem(struct io_queue *pio_q); +extern void dev_power_down(_adapter * Adapter, u8 bpwrup); + +/* +#define RTL_R8(reg) rtw_read8(padapter, reg) +#define RTL_R16(reg) rtw_read16(padapter, reg) +#define RTL_R32(reg) rtw_read32(padapter, reg) +#define RTL_W8(reg, val8) rtw_write8(padapter, reg, val8) +#define RTL_W16(reg, val16) rtw_write16(padapter, reg, val16) +#define RTL_W32(reg, val32) rtw_write32(padapter, reg, val32) +*/ + +/* +#define RTL_W8_ASYNC(reg, val8) rtw_write32_async(padapter, reg, val8) +#define RTL_W16_ASYNC(reg, val16) rtw_write32_async(padapter, reg, val16) +#define RTL_W32_ASYNC(reg, val32) rtw_write32_async(padapter, reg, val32) + +#define RTL_WRITE_BB(reg, val32) phy_SetUsbBBReg(padapter, reg, val32) +#define RTL_READ_BB(reg) phy_QueryUsbBBReg(padapter, reg) +*/ + +#define PlatformEFIOWrite1Byte(_a,_b,_c) \ + rtw_write8(_a,_b,_c) +#define PlatformEFIOWrite2Byte(_a,_b,_c) \ + rtw_write16(_a,_b,_c) +#define PlatformEFIOWrite4Byte(_a,_b,_c) \ + rtw_write32(_a,_b,_c) + +#define PlatformEFIORead1Byte(_a,_b) \ + rtw_read8(_a,_b) +#define PlatformEFIORead2Byte(_a,_b) \ + rtw_read16(_a,_b) +#define PlatformEFIORead4Byte(_a,_b) \ + rtw_read32(_a,_b) + +#endif //_RTL8711_IO_H_ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_ioctl.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_ioctl.h new file mode 100644 index 000000000..3a82c6d5a --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_ioctl.h @@ -0,0 +1,329 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_IOCTL_H_ +#define _RTW_IOCTL_H_ + +#ifndef PLATFORM_WINDOWS +// 00 - Success +// 11 - Error +#define STATUS_SUCCESS (0x00000000L) +#define STATUS_PENDING (0x00000103L) + +#define STATUS_UNSUCCESSFUL (0xC0000001L) +#define STATUS_INSUFFICIENT_RESOURCES (0xC000009AL) +#define STATUS_NOT_SUPPORTED (0xC00000BBL) + +#define NDIS_STATUS_SUCCESS ((NDIS_STATUS)STATUS_SUCCESS) +#define NDIS_STATUS_PENDING ((NDIS_STATUS)STATUS_PENDING) +#define NDIS_STATUS_NOT_RECOGNIZED ((NDIS_STATUS)0x00010001L) +#define NDIS_STATUS_NOT_COPIED ((NDIS_STATUS)0x00010002L) +#define NDIS_STATUS_NOT_ACCEPTED ((NDIS_STATUS)0x00010003L) +#define NDIS_STATUS_CALL_ACTIVE ((NDIS_STATUS)0x00010007L) + +#define NDIS_STATUS_FAILURE ((NDIS_STATUS)STATUS_UNSUCCESSFUL) +#define NDIS_STATUS_RESOURCES ((NDIS_STATUS)STATUS_INSUFFICIENT_RESOURCES) +#define NDIS_STATUS_CLOSING ((NDIS_STATUS)0xC0010002L) +#define NDIS_STATUS_BAD_VERSION ((NDIS_STATUS)0xC0010004L) +#define NDIS_STATUS_BAD_CHARACTERISTICS ((NDIS_STATUS)0xC0010005L) +#define NDIS_STATUS_ADAPTER_NOT_FOUND ((NDIS_STATUS)0xC0010006L) +#define NDIS_STATUS_OPEN_FAILED ((NDIS_STATUS)0xC0010007L) +#define NDIS_STATUS_DEVICE_FAILED ((NDIS_STATUS)0xC0010008L) +#define NDIS_STATUS_MULTICAST_FULL ((NDIS_STATUS)0xC0010009L) +#define NDIS_STATUS_MULTICAST_EXISTS ((NDIS_STATUS)0xC001000AL) +#define NDIS_STATUS_MULTICAST_NOT_FOUND ((NDIS_STATUS)0xC001000BL) +#define NDIS_STATUS_REQUEST_ABORTED ((NDIS_STATUS)0xC001000CL) +#define NDIS_STATUS_RESET_IN_PROGRESS ((NDIS_STATUS)0xC001000DL) +#define NDIS_STATUS_CLOSING_INDICATING ((NDIS_STATUS)0xC001000EL) +#define NDIS_STATUS_NOT_SUPPORTED ((NDIS_STATUS)STATUS_NOT_SUPPORTED) +#define NDIS_STATUS_INVALID_PACKET ((NDIS_STATUS)0xC001000FL) +#define NDIS_STATUS_OPEN_LIST_FULL ((NDIS_STATUS)0xC0010010L) +#define NDIS_STATUS_ADAPTER_NOT_READY ((NDIS_STATUS)0xC0010011L) +#define NDIS_STATUS_ADAPTER_NOT_OPEN ((NDIS_STATUS)0xC0010012L) +#define NDIS_STATUS_NOT_INDICATING ((NDIS_STATUS)0xC0010013L) +#define NDIS_STATUS_INVALID_LENGTH ((NDIS_STATUS)0xC0010014L) +#define NDIS_STATUS_INVALID_DATA ((NDIS_STATUS)0xC0010015L) +#define NDIS_STATUS_BUFFER_TOO_SHORT ((NDIS_STATUS)0xC0010016L) +#define NDIS_STATUS_INVALID_OID ((NDIS_STATUS)0xC0010017L) +#define NDIS_STATUS_ADAPTER_REMOVED ((NDIS_STATUS)0xC0010018L) +#define NDIS_STATUS_UNSUPPORTED_MEDIA ((NDIS_STATUS)0xC0010019L) +#define NDIS_STATUS_GROUP_ADDRESS_IN_USE ((NDIS_STATUS)0xC001001AL) +#define NDIS_STATUS_FILE_NOT_FOUND ((NDIS_STATUS)0xC001001BL) +#define NDIS_STATUS_ERROR_READING_FILE ((NDIS_STATUS)0xC001001CL) +#define NDIS_STATUS_ALREADY_MAPPED ((NDIS_STATUS)0xC001001DL) +#define NDIS_STATUS_RESOURCE_CONFLICT ((NDIS_STATUS)0xC001001EL) +#define NDIS_STATUS_NO_CABLE ((NDIS_STATUS)0xC001001FL) + +#define NDIS_STATUS_INVALID_SAP ((NDIS_STATUS)0xC0010020L) +#define NDIS_STATUS_SAP_IN_USE ((NDIS_STATUS)0xC0010021L) +#define NDIS_STATUS_INVALID_ADDRESS ((NDIS_STATUS)0xC0010022L) +#define NDIS_STATUS_VC_NOT_ACTIVATED ((NDIS_STATUS)0xC0010023L) +#define NDIS_STATUS_DEST_OUT_OF_ORDER ((NDIS_STATUS)0xC0010024L) // cause 27 +#define NDIS_STATUS_VC_NOT_AVAILABLE ((NDIS_STATUS)0xC0010025L) // cause 35,45 +#define NDIS_STATUS_CELLRATE_NOT_AVAILABLE ((NDIS_STATUS)0xC0010026L) // cause 37 +#define NDIS_STATUS_INCOMPATABLE_QOS ((NDIS_STATUS)0xC0010027L) // cause 49 +#define NDIS_STATUS_AAL_PARAMS_UNSUPPORTED ((NDIS_STATUS)0xC0010028L) // cause 93 +#define NDIS_STATUS_NO_ROUTE_TO_DESTINATION ((NDIS_STATUS)0xC0010029L) // cause 3 +#endif /* #ifndef PLATFORM_WINDOWS */ + + +#ifndef OID_802_11_CAPABILITY + #define OID_802_11_CAPABILITY 0x0d010122 +#endif + +#ifndef OID_802_11_PMKID + #define OID_802_11_PMKID 0x0d010123 +#endif + + +// For DDK-defined OIDs +#define OID_NDIS_SEG1 0x00010100 +#define OID_NDIS_SEG2 0x00010200 +#define OID_NDIS_SEG3 0x00020100 +#define OID_NDIS_SEG4 0x01010100 +#define OID_NDIS_SEG5 0x01020100 +#define OID_NDIS_SEG6 0x01020200 +#define OID_NDIS_SEG7 0xFD010100 +#define OID_NDIS_SEG8 0x0D010100 +#define OID_NDIS_SEG9 0x0D010200 +#define OID_NDIS_SEG10 0x0D020200 + +#define SZ_OID_NDIS_SEG1 23 +#define SZ_OID_NDIS_SEG2 3 +#define SZ_OID_NDIS_SEG3 6 +#define SZ_OID_NDIS_SEG4 6 +#define SZ_OID_NDIS_SEG5 4 +#define SZ_OID_NDIS_SEG6 8 +#define SZ_OID_NDIS_SEG7 7 +#define SZ_OID_NDIS_SEG8 36 +#define SZ_OID_NDIS_SEG9 24 +#define SZ_OID_NDIS_SEG10 19 + +// For Realtek-defined OIDs +#define OID_MP_SEG1 0xFF871100 +#define OID_MP_SEG2 0xFF818000 + +#define OID_MP_SEG3 0xFF818700 +#define OID_MP_SEG4 0xFF011100 + +#define DEBUG_OID(dbg, str) \ + if((!dbg)) \ + { \ + RT_TRACE(_module_rtl871x_ioctl_c_,_drv_info_,("%s(%d): %s", __FUNCTION__, __LINE__, str)); \ + } + + +enum oid_type +{ + QUERY_OID, + SET_OID +}; + +struct oid_funs_node { + unsigned int oid_start; //the starting number for OID + unsigned int oid_end; //the ending number for OID + struct oid_obj_priv *node_array; + unsigned int array_sz; //the size of node_array + int query_counter; //count the number of query hits for this segment + int set_counter; //count the number of set hits for this segment +}; + +struct oid_par_priv +{ + void *adapter_context; + NDIS_OID oid; + void *information_buf; + u32 information_buf_len; + u32 *bytes_rw; + u32 *bytes_needed; + enum oid_type type_of_oid; + u32 dbg; +}; + +struct oid_obj_priv { + unsigned char dbg; // 0: without OID debug message 1: with OID debug message + NDIS_STATUS (*oidfuns)(struct oid_par_priv *poid_par_priv); +}; + +#if (defined(CONFIG_MP_INCLUDED) && defined(_RTW_MP_IOCTL_C_)) || \ + (defined(PLATFORM_WINDOWS) && defined(_RTW_IOCTL_RTL_C_)) +static NDIS_STATUS oid_null_function(struct oid_par_priv* poid_par_priv) +{ + _func_enter_; + _func_exit_; + return NDIS_STATUS_SUCCESS; +} +#endif + +#ifdef PLATFORM_WINDOWS + +int TranslateNdisPsToRtPs(IN NDIS_802_11_POWER_MODE ndisPsMode); + +//OID Handler for Segment 1 +NDIS_STATUS oid_gen_supported_list_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_gen_hardware_status_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_gen_media_supported_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_gen_media_in_use_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_gen_maximum_lookahead_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_gen_maximum_frame_size_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_gen_link_speed_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_gen_transmit_buffer_space_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_gen_receive_buffer_space_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_gen_transmit_block_size_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_gen_receive_block_size_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_gen_vendor_id_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_gen_vendor_description_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_gen_current_packet_filter_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_gen_current_lookahead_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_gen_driver_version_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_gen_maximum_total_size_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_gen_protocol_options_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_gen_mac_options_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_gen_media_connect_status_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_gen_maximum_send_packets_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_gen_vendor_driver_version_hdl(struct oid_par_priv* poid_par_priv); + + +//OID Handler for Segment 2 +NDIS_STATUS oid_gen_physical_medium_hdl(struct oid_par_priv* poid_par_priv); + +//OID Handler for Segment 3 +NDIS_STATUS oid_gen_xmit_ok_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_gen_rcv_ok_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_gen_xmit_error_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_gen_rcv_error_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_gen_rcv_no_buffer_hdl(struct oid_par_priv* poid_par_priv); + + +//OID Handler for Segment 4 +NDIS_STATUS oid_802_3_permanent_address_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_3_current_address_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_3_multicast_list_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_3_maximum_list_size_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_3_mac_options_hdl(struct oid_par_priv* poid_par_priv); + + + +//OID Handler for Segment 5 +NDIS_STATUS oid_802_3_rcv_error_alignment_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_3_xmit_one_collision_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_3_xmit_more_collisions_hdl(struct oid_par_priv* poid_par_priv); + + +//OID Handler for Segment 6 +NDIS_STATUS oid_802_3_xmit_deferred_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_3_xmit_max_collisions_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_3_rcv_overrun_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_3_xmit_underrun_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_3_xmit_heartbeat_failure_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_3_xmit_times_crs_lost_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_3_xmit_late_collisions_hdl(struct oid_par_priv* poid_par_priv); + + + +//OID Handler for Segment 7 +NDIS_STATUS oid_pnp_capabilities_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_pnp_set_power_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_pnp_query_power_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_pnp_add_wake_up_pattern_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_pnp_remove_wake_up_pattern_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_pnp_wake_up_pattern_list_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_pnp_enable_wake_up_hdl(struct oid_par_priv* poid_par_priv); + + + +//OID Handler for Segment 8 +NDIS_STATUS oid_802_11_bssid_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_ssid_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_infrastructure_mode_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_add_wep_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_remove_wep_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_disassociate_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_authentication_mode_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_privacy_filter_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_bssid_list_scan_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_encryption_status_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_reload_defaults_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_add_key_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_remove_key_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_association_information_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_test_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_media_stream_mode_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_capability_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_pmkid_hdl(struct oid_par_priv* poid_par_priv); + + + + + +//OID Handler for Segment 9 +NDIS_STATUS oid_802_11_network_types_supported_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_network_type_in_use_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_tx_power_level_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_rssi_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_rssi_trigger_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_fragmentation_threshold_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_rts_threshold_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_number_of_antennas_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_rx_antenna_selected_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_tx_antenna_selected_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_supported_rates_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_desired_rates_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_configuration_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_power_mode_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_802_11_bssid_list_hdl(struct oid_par_priv* poid_par_priv); + + +//OID Handler for Segment 10 +NDIS_STATUS oid_802_11_statistics_hdl(struct oid_par_priv* poid_par_priv); + + +//OID Handler for Segment ED +NDIS_STATUS oid_rt_mh_vender_id_hdl(struct oid_par_priv* poid_par_priv); + +void Set_802_3_MULTICAST_LIST(ADAPTER *pAdapter, UCHAR *MCListbuf, ULONG MCListlen, BOOLEAN bAcceptAllMulticast); + +#endif// end of PLATFORM_WINDOWS + +#if defined(PLATFORM_LINUX) && defined(CONFIG_WIRELESS_EXT) +extern struct iw_handler_def rtw_handlers_def; +#endif + +extern void rtw_request_wps_pbc_event(_adapter *padapter); + +extern NDIS_STATUS drv_query_info( + IN _nic_hdl MiniportAdapterContext, + IN NDIS_OID Oid, + IN void * InformationBuffer, + IN u32 InformationBufferLength, + OUT u32* BytesWritten, + OUT u32* BytesNeeded + ); + +extern NDIS_STATUS drv_set_info( + IN _nic_hdl MiniportAdapterContext, + IN NDIS_OID Oid, + IN void * InformationBuffer, + IN u32 InformationBufferLength, + OUT u32* BytesRead, + OUT u32* BytesNeeded + ); + +#endif // #ifndef __INC_CEINFO_ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_ioctl_query.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_ioctl_query.h new file mode 100644 index 000000000..d91d35f99 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_ioctl_query.h @@ -0,0 +1,33 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_IOCTL_QUERY_H_ +#define _RTW_IOCTL_QUERY_H_ + + +#ifdef PLATFORM_WINDOWS + +u8 query_802_11_capability(_adapter* padapter,u8* pucBuf,u32 * pulOutLen); +u8 query_802_11_association_information (_adapter * padapter, PNDIS_802_11_ASSOCIATION_INFORMATION pAssocInfo); + +#endif + + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_ioctl_rtl.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_ioctl_rtl.h new file mode 100644 index 000000000..a1b3491f5 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_ioctl_rtl.h @@ -0,0 +1,81 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_IOCTL_RTL_H_ +#define _RTW_IOCTL_RTL_H_ + + +//************** oid_rtl_seg_01_01 ************** +NDIS_STATUS oid_rt_get_signal_quality_hdl(struct oid_par_priv* poid_par_priv);//84 +NDIS_STATUS oid_rt_get_small_packet_crc_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_get_middle_packet_crc_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_get_large_packet_crc_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_get_tx_retry_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_get_rx_retry_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_get_rx_total_packet_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_get_tx_beacon_ok_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_get_tx_beacon_err_hdl(struct oid_par_priv* poid_par_priv); + +NDIS_STATUS oid_rt_pro_set_fw_dig_state_hdl(struct oid_par_priv* poid_par_priv); //8a +NDIS_STATUS oid_rt_pro_set_fw_ra_state_hdl(struct oid_par_priv* poid_par_priv); //8b + +NDIS_STATUS oid_rt_get_rx_icv_err_hdl(struct oid_par_priv* poid_par_priv);//93 +NDIS_STATUS oid_rt_set_encryption_algorithm_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_get_preamble_mode_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_get_ap_ip_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_get_channelplan_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_set_channelplan_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_set_preamble_mode_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_set_bcn_intvl_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_dedicate_probe_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_get_total_tx_bytes_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_get_total_rx_bytes_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_current_tx_power_level_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_get_enc_key_mismatch_count_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_get_enc_key_match_count_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_get_channel_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_get_hardware_radio_off_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_get_key_mismatch_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_supported_wireless_mode_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_get_channel_list_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_get_scan_in_progress_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_forced_data_rate_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_wireless_mode_for_scan_list_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_get_bss_wireless_mode_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_scan_with_magic_packet_hdl(struct oid_par_priv* poid_par_priv); + +//************** oid_rtl_seg_01_03 section start ************** +NDIS_STATUS oid_rt_ap_get_associated_station_list_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_ap_switch_into_ap_mode_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_ap_supported_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_ap_set_passphrase_hdl(struct oid_par_priv* poid_par_priv); + +// oid_rtl_seg_01_11 +NDIS_STATUS oid_rt_pro_rf_write_registry_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_rf_read_registry_hdl(struct oid_par_priv* poid_par_priv); + +//************** oid_rtl_seg_03_00 section start ************** +NDIS_STATUS oid_rt_get_connect_state_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_set_default_key_id_hdl(struct oid_par_priv* poid_par_priv); + + + + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_ioctl_set.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_ioctl_set.h new file mode 100644 index 000000000..1b7184688 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_ioctl_set.h @@ -0,0 +1,76 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_IOCTL_SET_H_ +#define __RTW_IOCTL_SET_H_ + + +typedef u8 NDIS_802_11_PMKID_VALUE[16]; + +typedef struct _BSSIDInfo { + NDIS_802_11_MAC_ADDRESS BSSID; + NDIS_802_11_PMKID_VALUE PMKID; +} BSSIDInfo, *PBSSIDInfo; + + +#ifdef PLATFORM_OS_XP +typedef struct _NDIS_802_11_PMKID { + u32 Length; + u32 BSSIDInfoCount; + BSSIDInfo BSSIDInfo[1]; +} NDIS_802_11_PMKID, *PNDIS_802_11_PMKID; +#endif + + +#ifdef PLATFORM_WINDOWS +u8 rtw_set_802_11_reload_defaults(_adapter * padapter, NDIS_802_11_RELOAD_DEFAULTS reloadDefaults); +u8 rtw_set_802_11_test(_adapter * padapter, NDIS_802_11_TEST * test); +u8 rtw_set_802_11_pmkid(_adapter *pdapter, NDIS_802_11_PMKID *pmkid); + +u8 rtw_pnp_set_power_sleep(_adapter* padapter); +u8 rtw_pnp_set_power_wakeup(_adapter* padapter); + +void rtw_pnp_resume_wk(void *context); +void rtw_pnp_sleep_wk(void * context); + +#endif + +u8 rtw_set_802_11_add_key(_adapter * padapter, NDIS_802_11_KEY * key); +u8 rtw_set_802_11_authentication_mode(_adapter *pdapter, NDIS_802_11_AUTHENTICATION_MODE authmode); +u8 rtw_set_802_11_bssid(_adapter* padapter, u8 *bssid); +u8 rtw_set_802_11_add_wep(_adapter * padapter, NDIS_802_11_WEP * wep); +u8 rtw_set_802_11_disassociate(_adapter * padapter); +u8 rtw_set_802_11_bssid_list_scan(_adapter* padapter, NDIS_802_11_SSID *pssid, int ssid_max_num); +u8 rtw_set_802_11_infrastructure_mode(_adapter * padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype); +u8 rtw_set_802_11_remove_wep(_adapter * padapter, u32 keyindex); +u8 rtw_set_802_11_ssid(_adapter * padapter, NDIS_802_11_SSID * ssid); +u8 rtw_set_802_11_connect(_adapter* padapter, u8 *bssid, NDIS_802_11_SSID *ssid); +u8 rtw_set_802_11_remove_key(_adapter * padapter, NDIS_802_11_REMOVE_KEY * key); + +u8 rtw_validate_bssid(u8 *bssid); +u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid); + +u16 rtw_get_cur_max_rate(_adapter *adapter); +int rtw_set_scan_mode(_adapter *adapter, RT_SCAN_TYPE scan_mode); +int rtw_set_channel_plan(_adapter *adapter, u8 channel_plan); +int rtw_set_country(_adapter *adapter, const char *country_code); +int rtw_set_band(_adapter *adapter, u8 band); + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_iol.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_iol.h new file mode 100644 index 000000000..128668c41 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_iol.h @@ -0,0 +1,137 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_IOL_H_ +#define __RTW_IOL_H_ + + +struct xmit_frame *rtw_IOL_accquire_xmit_frame(ADAPTER *adapter); +int rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, u32 cmd_len); +int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary); +int rtw_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt); +bool rtw_IOL_applied(ADAPTER *adapter); +int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us); +int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms); +int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame); + + +#ifdef CONFIG_IOL_NEW_GENERATION +#define IOREG_CMD_END_LEN 4 + +struct ioreg_cfg{ + u8 length; + u8 cmd_id; + u16 address; + u32 data; + u32 mask; +}; +enum ioreg_cmd{ + IOREG_CMD_LLT = 0x01, + IOREG_CMD_REFUSE = 0x02, + IOREG_CMD_EFUSE_PATH = 0x03, + IOREG_CMD_WB_REG = 0x04, + IOREG_CMD_WW_REG = 0x05, + IOREG_CMD_WD_REG = 0x06, + IOREG_CMD_W_RF = 0x07, + IOREG_CMD_DELAY_US = 0x10, + IOREG_CMD_DELAY_MS = 0x11, + IOREG_CMD_END = 0xFF, +}; +void read_efuse_from_txpktbuf(ADAPTER *adapter, int bcnhead, u8 *content, u16 *size); + +int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, u8 mask); +int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, u16 mask); +int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, u32 mask); +int _rtw_IOL_append_WRF_cmd(struct xmit_frame *xmit_frame, u8 rf_path, u16 addr, u32 value, u32 mask); +#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value,mask) _rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value) ,(mask)) +#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value,mask) _rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value),(mask)) +#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value,mask) _rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value),(mask)) +#define rtw_IOL_append_WRF_cmd(xmit_frame, rf_path, addr, value,mask) _rtw_IOL_append_WRF_cmd((xmit_frame),(rf_path), (addr), (value),(mask)) + +u8 rtw_IOL_cmd_boundary_handle(struct xmit_frame *pxmit_frame); +void rtw_IOL_cmd_buf_dump(ADAPTER *Adapter,int buf_len,u8 *pbuf); + +#ifdef CONFIG_IOL_IOREG_CFG_DBG + struct cmd_cmp{ + u16 addr; + u32 value; + }; +#endif + +#else //CONFIG_IOL_NEW_GENERATION + +typedef struct _io_offload_cmd { + u8 rsvd0; + u8 cmd; + u16 address; + u32 value; +} IO_OFFLOAD_CMD, IOL_CMD; + +#define IOL_CMD_LLT 0x00 +//#define IOL_CMD_R_EFUSE 0x01 +#define IOL_CMD_WB_REG 0x02 +#define IOL_CMD_WW_REG 0x03 +#define IOL_CMD_WD_REG 0x04 +//#define IOL_CMD_W_RF 0x05 +#define IOL_CMD_DELAY_US 0x80 +#define IOL_CMD_DELAY_MS 0x81 +//#define IOL_CMD_DELAY_S 0x82 +#define IOL_CMD_END 0x83 + +/***************************************************** +CMD Address Value +(B1) (B2/B3:H/L addr) (B4:B7 : MSB:LSB) +****************************************************** +IOL_CMD_LLT - B7: PGBNDY +//IOL_CMD_R_EFUSE - - +IOL_CMD_WB_REG 0x0~0xFFFF B7 +IOL_CMD_WW_REG 0x0~0xFFFF B6~B7 +IOL_CMD_WD_REG 0x0~0xFFFF B4~B7 +//IOL_CMD_W_RF RF Reg B5~B7 +IOL_CMD_DELAY_US - B6~B7 +IOL_CMD_DELAY_MS - B6~B7 +//IOL_CMD_DELAY_S - B6~B7 +IOL_CMD_END - - +******************************************************/ +int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value); +int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value); +int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value); + + +int rtw_IOL_exec_cmd_array_sync(PADAPTER adapter, u8 *IOL_cmds, u32 cmd_num, u32 max_wating_ms); +int rtw_IOL_exec_empty_cmds_sync(ADAPTER *adapter, u32 max_wating_ms); + +#ifdef DBG_IO +int dbg_rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, const char *caller, const int line); +int dbg_rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, const char *caller, const int line); +int dbg_rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, const char *caller, const int line); +#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__) +#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__) +#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__) +#else +#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value) _rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value)) +#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value) _rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value)) +#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value) _rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value)) +#endif // DBG_IO +#endif // CONFIG_IOL_NEW_GENERATION + + + +#endif //__RTW_IOL_H_ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_mem.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_mem.h new file mode 100644 index 000000000..8017e6ae6 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_mem.h @@ -0,0 +1,42 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_MEM_H__ +#define __RTW_MEM_H__ + +#include +#include +#include + +#ifdef CONFIG_PLATFORM_MSTAR_HIGH +#define MAX_RTKM_RECVBUF_SZ (31744) /* 31k */ +#else +#define MAX_RTKM_RECVBUF_SZ (15360) /* 15k */ +#endif /* CONFIG_PLATFORM_MSTAR_HIGH */ +#define MAX_RTKM_NR_PREALLOC_RECV_SKB 16 + +u16 rtw_rtkm_get_buff_size(void); +u8 rtw_rtkm_get_nr_recv_skb(void); +struct u8* rtw_alloc_revcbuf_premem(void); +struct sk_buff *rtw_alloc_skb_premem(u16 in_size); +int rtw_free_skb_premem(struct sk_buff *pskb); + + +#endif //__RTW_MEM_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_mlme.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_mlme.h new file mode 100644 index 000000000..5b1666aaa --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_mlme.h @@ -0,0 +1,1080 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_MLME_H_ +#define __RTW_MLME_H_ + + +#define MAX_BSS_CNT 128 +//#define MAX_JOIN_TIMEOUT 2000 +//#define MAX_JOIN_TIMEOUT 2500 +#define MAX_JOIN_TIMEOUT 6500 + +// Commented by Albert 20101105 +// Increase the scanning timeout because of increasing the SURVEY_TO value. + +#define SCANNING_TIMEOUT 8000 +#ifdef CONFIG_SCAN_BACKOP +#define CONC_SCANNING_TIMEOUT_SINGLE_BAND 10000 +#define CONC_SCANNING_TIMEOUT_DUAL_BAND 15000 +#endif + +#ifdef PALTFORM_OS_WINCE +#define SCANQUEUE_LIFETIME 12000000 // unit:us +#else +#define SCANQUEUE_LIFETIME 20000 // 20sec, unit:msec +#endif + +#define WIFI_NULL_STATE 0x00000000 +#define WIFI_ASOC_STATE 0x00000001 /* Linked */ +#define WIFI_REASOC_STATE 0x00000002 +#define WIFI_SLEEP_STATE 0x00000004 +#define WIFI_STATION_STATE 0x00000008 +#define WIFI_AP_STATE 0x00000010 +#define WIFI_ADHOC_STATE 0x00000020 +#define WIFI_ADHOC_MASTER_STATE 0x00000040 +#define WIFI_UNDER_LINKING 0x00000080 +#define WIFI_UNDER_WPS 0x00000100 +/*#define WIFI_UNDEFINED_STATE 0x00000200*/ +#define WIFI_STA_ALIVE_CHK_STATE 0x00000400 +#define WIFI_SITE_MONITOR 0x00000800 /* under site surveying */ +#define WIFI_WDS 0x00001000 +#define WIFI_WDS_RX_BEACON 0x00002000 /* already rx WDS AP beacon */ +#define WIFI_AUTOCONF 0x00004000 +#define WIFI_AUTOCONF_IND 0x00008000 +#define WIFI_MP_STATE 0x00010000 +#define WIFI_MP_CTX_BACKGROUND 0x00020000 /* in continuous tx background */ +#define WIFI_MP_CTX_ST 0x00040000 /* in continuous tx with single-tone */ +#define WIFI_MP_CTX_BACKGROUND_PENDING 0x00080000 /* pending in continuous tx background due to out of skb */ +#define WIFI_MP_CTX_CCK_HW 0x00100000 /* in continuous tx */ +#define WIFI_MP_CTX_CCK_CS 0x00200000 /* in continuous tx with carrier suppression */ +#define WIFI_MP_LPBK_STATE 0x00400000 +#define WIFI_OP_CH_SWITCHING 0x00800000 +/*#define WIFI_UNDEFINED_STATE 0x01000000*/ +/*#define WIFI_UNDEFINED_STATE 0x02000000*/ +/*#define WIFI_UNDEFINED_STATE 0x04000000*/ +/*#define WIFI_UNDEFINED_STATE 0x08000000*/ +/*#define WIFI_UNDEFINED_STATE 0x10000000*/ +/*#define WIFI_UNDEFINED_STATE 0x20000000*/ +/*#define WIFI_UNDEFINED_STATE 0x40000000*/ +#define WIFI_MONITOR_STATE 0x80000000 + +#define MIRACAST_DISABLED 0 +#define MIRACAST_SOURCE BIT0 +#define MIRACAST_SINK BIT1 + +#define MIRACAST_MODE_REVERSE(mode) \ + ((((mode) & MIRACAST_SOURCE) ? MIRACAST_SINK : 0) | (((mode) & MIRACAST_SINK) ? MIRACAST_SOURCE : 0)) + +bool is_miracast_enabled(_adapter *adapter); +bool rtw_chk_miracast_mode(_adapter *adapter, u8 mode); +const char *get_miracast_mode_str(int mode); +void rtw_wfd_st_switch(struct sta_info *sta, bool on); + +#define MLME_STATE(adapter) get_fwstate(&((adapter)->mlmepriv)) + +#define MLME_IS_STA(adapter) (MLME_STATE((adapter)) & WIFI_STATION_STATE) +#define MLME_IS_AP(adapter) (MLME_STATE((adapter)) & WIFI_AP_STATE) +#define MLME_IS_ADHOC(adapter) (MLME_STATE((adapter)) & WIFI_ADHOC_STATE) +#define MLME_IS_ADHOC_MASTER(adapter) (MLME_STATE((adapter)) & WIFI_ADHOC_MASTER_STATE) +#define MLME_IS_MONITOR(adapter) (MLME_STATE((adapter)) & WIFI_MONITOR_STATE) +#define MLME_IS_MP(adapter) (MLME_STATE((adapter)) & WIFI_MP_STATE) +#ifdef CONFIG_P2P +#define MLME_IS_GC(adapter) rtw_p2p_chk_role(&(adapter)->wdinfo, P2P_ROLE_CLIENT) +#define MLME_IS_GO(adapter) rtw_p2p_chk_role(&(adapter)->wdinfo, P2P_ROLE_GO) +#else /* !CONFIG_P2P */ +#define MLME_IS_GC(adapter) 0 +#define MLME_IS_GO(adapter) 0 +#endif /* !CONFIG_P2P */ +#define MLME_IS_MSRC(adapter) rtw_chk_miracast_mode((adapter), MIRACAST_SOURCE) +#define MLME_IS_MSINK(adapter) rtw_chk_miracast_mode((adapter), MIRACAST_SINK) + +#define MLME_STATE_FMT "%s%s%s%s%s%s%s%s%s%s%s%s%s%s" +#define MLME_STATE_ARG(adapter) \ + MLME_IS_STA((adapter)) ? (MLME_IS_GC((adapter)) ? " GC" : " STA") : "", \ + MLME_IS_AP((adapter)) ? (MLME_IS_GO((adapter)) ? " GO" : " AP") : "", \ + MLME_IS_ADHOC((adapter)) ? " ADHOC" : "", \ + MLME_IS_ADHOC_MASTER((adapter)) ? " ADHOC_M" : "", \ + MLME_IS_MONITOR((adapter)) ? " MONITOR" : "", \ + MLME_IS_MP((adapter)) ? " MP" : "", \ + MLME_IS_MSRC((adapter)) ? " MSRC" : "", \ + MLME_IS_MSINK((adapter)) ? " MSINK" : "", \ + (MLME_STATE((adapter)) & WIFI_SITE_MONITOR) ? " SCAN" : "", \ + (MLME_STATE((adapter)) & WIFI_UNDER_LINKING) ? " LINKING" : "", \ + (MLME_STATE((adapter)) & WIFI_ASOC_STATE) ? " ASOC" : "", \ + (MLME_STATE((adapter)) & WIFI_OP_CH_SWITCHING) ? " OP_CH_SW" : "", \ + (MLME_STATE((adapter)) & WIFI_UNDER_WPS) ? " WPS" : "", \ + (MLME_STATE((adapter)) & WIFI_SLEEP_STATE) ? " SLEEP" : "" + +#define _FW_UNDER_LINKING WIFI_UNDER_LINKING +#define _FW_LINKED WIFI_ASOC_STATE +#define _FW_UNDER_SURVEY WIFI_SITE_MONITOR + + +enum dot11AuthAlgrthmNum { + dot11AuthAlgrthm_Open = 0, + dot11AuthAlgrthm_Shared, + dot11AuthAlgrthm_8021X, + dot11AuthAlgrthm_Auto, + dot11AuthAlgrthm_WAPI, + dot11AuthAlgrthm_MaxNum +}; + +// Scan type including active and passive scan. +typedef enum _RT_SCAN_TYPE +{ + SCAN_PASSIVE, + SCAN_ACTIVE, + SCAN_MIX, +}RT_SCAN_TYPE, *PRT_SCAN_TYPE; + +#define WIFI_FREQUENCY_BAND_AUTO 0 +#define WIFI_FREQUENCY_BAND_5GHZ 1 +#define WIFI_FREQUENCY_BAND_2GHZ 2 + +#define rtw_band_valid(band) ((band) <= WIFI_FREQUENCY_BAND_2GHZ) + +enum DriverInterface { + DRIVER_WEXT = 1, + DRIVER_CFG80211 = 2 +}; + +enum SCAN_RESULT_TYPE +{ + SCAN_RESULT_P2P_ONLY = 0, // Will return all the P2P devices. + SCAN_RESULT_ALL = 1, // Will return all the scanned device, include AP. + SCAN_RESULT_WFD_TYPE = 2 // Will just return the correct WFD device. + // If this device is Miracast sink device, it will just return all the Miracast source devices. +}; + +/* + +there are several "locks" in mlme_priv, +since mlme_priv is a shared resource between many threads, +like ISR/Call-Back functions, the OID handlers, and even timer functions. + + +Each _queue has its own locks, already. +Other items are protected by mlme_priv.lock. + +To avoid possible dead lock, any thread trying to modifiying mlme_priv +SHALL not lock up more than one locks at a time! + +*/ + + +#define traffic_threshold 10 +#define traffic_scan_period 500 + +struct sitesurvey_ctrl { + u64 last_tx_pkts; + uint last_rx_pkts; + sint traffic_busy; + _timer sitesurvey_ctrl_timer; +}; + +typedef struct _RT_LINK_DETECT_T{ + u32 NumTxOkInPeriod; + u32 NumRxOkInPeriod; + u32 NumRxUnicastOkInPeriod; + BOOLEAN bBusyTraffic; + BOOLEAN bTxBusyTraffic; + BOOLEAN bRxBusyTraffic; + BOOLEAN bHigherBusyTraffic; // For interrupt migration purpose. + BOOLEAN bHigherBusyRxTraffic; // We may disable Tx interrupt according as Rx traffic. + BOOLEAN bHigherBusyTxTraffic; // We may disable Tx interrupt according as Tx traffic. + //u8 TrafficBusyState; + u8 TrafficTransitionCount; + u32 LowPowerTransitionCount; +}RT_LINK_DETECT_T, *PRT_LINK_DETECT_T; + +struct profile_info { + u8 ssidlen; + u8 ssid[ WLAN_SSID_MAXLEN ]; + u8 peermac[ ETH_ALEN ]; +}; + +struct tx_invite_req_info{ + u8 token; + u8 benable; + u8 go_ssid[ WLAN_SSID_MAXLEN ]; + u8 ssidlen; + u8 go_bssid[ ETH_ALEN ]; + u8 peer_macaddr[ ETH_ALEN ]; + u8 operating_ch; // This information will be set by using the p2p_set op_ch=x + u8 peer_ch; // The listen channel for peer P2P device + +}; + +struct tx_invite_resp_info{ + u8 token; // Used to record the dialog token of p2p invitation request frame. +}; + +#ifdef CONFIG_WFD + +struct wifi_display_info{ + u16 wfd_enable; // Eanble/Disable the WFD function. + u16 init_rtsp_ctrlport; /* init value of rtsp_ctrlport when WFD enable */ + u16 rtsp_ctrlport; /* TCP port number at which the this WFD device listens for RTSP messages, 0 when WFD disable */ + u16 tdls_rtsp_ctrlport; /* rtsp_ctrlport used by tdls, will sync when rtsp_ctrlport is changed by user */ + u16 peer_rtsp_ctrlport; // TCP port number at which the peer WFD device listens for RTSP messages + // This filed should be filled when receiving the gropu negotiation request + + u8 peer_session_avail; // WFD session is available or not for the peer wfd device. + // This variable will be set when sending the provisioning discovery request to peer WFD device. + // And this variable will be reset when it is read by using the iwpriv p2p_get wfd_sa command. + u8 ip_address[4]; + u8 peer_ip_address[4]; + u8 wfd_pc; // WFD preferred connection + // 0 -> Prefer to use the P2P for WFD connection on peer side. + // 1 -> Prefer to use the TDLS for WFD connection on peer side. + + u8 wfd_device_type; // WFD Device Type + // 0 -> WFD Source Device + // 1 -> WFD Primary Sink Device + enum SCAN_RESULT_TYPE scan_result_type; // Used when P2P is enable. This parameter will impact the scan result. + u8 op_wfd_mode; + u8 stack_wfd_mode; +}; +#endif //CONFIG_WFD + +struct tx_provdisc_req_info{ + u16 wps_config_method_request; // Used when sending the provisioning request frame + u16 peer_channel_num[2]; // The channel number which the receiver stands. + NDIS_802_11_SSID ssid; + u8 peerDevAddr[ ETH_ALEN ]; // Peer device address + u8 peerIFAddr[ ETH_ALEN ]; // Peer interface address + u8 benable; // This provision discovery request frame is trigger to send or not +}; + +struct rx_provdisc_req_info{ //When peer device issue prov_disc_req first, we should store the following informations + u8 peerDevAddr[ ETH_ALEN ]; // Peer device address + u8 strconfig_method_desc_of_prov_disc_req[4]; // description for the config method located in the provisioning discovery request frame. + // The UI must know this information to know which config method the remote p2p device is requiring. +}; + +struct tx_nego_req_info{ + u16 peer_channel_num[2]; // The channel number which the receiver stands. + u8 peerDevAddr[ ETH_ALEN ]; // Peer device address + u8 benable; // This negoitation request frame is trigger to send or not + u8 peer_ch; /* The listen channel for peer P2P device */ +}; + +struct group_id_info{ + u8 go_device_addr[ ETH_ALEN ]; // The GO's device address of this P2P group + u8 ssid[ WLAN_SSID_MAXLEN ]; // The SSID of this P2P group +}; + +struct scan_limit_info{ + u8 scan_op_ch_only; // When this flag is set, the driver should just scan the operation channel +#ifndef CONFIG_P2P_OP_CHK_SOCIAL_CH + u8 operation_ch[2]; // Store the operation channel of invitation request frame +#else + u8 operation_ch[5]; // Store additional channel 1,6,11 for Android 4.2 IOT & Nexus 4 +#endif //CONFIG_P2P_OP_CHK_SOCIAL_CH +}; + +#ifdef CONFIG_IOCTL_CFG80211 +struct cfg80211_wifidirect_info{ + _timer remain_on_ch_timer; + u8 restore_channel; + struct ieee80211_channel remain_on_ch_channel; + enum nl80211_channel_type remain_on_ch_type; + ATOMIC_T ro_ch_cookie_gen; + u64 remain_on_ch_cookie; + bool is_ro_ch; + u32 last_ro_ch_time; /* this will be updated at the beginning and end of ro_ch */ +}; +#endif //CONFIG_IOCTL_CFG80211 + +#ifdef CONFIG_P2P_WOWLAN + +enum P2P_WOWLAN_RECV_FRAME_TYPE +{ + P2P_WOWLAN_RECV_NEGO_REQ = 0, + P2P_WOWLAN_RECV_INVITE_REQ = 1, + P2P_WOWLAN_RECV_PROVISION_REQ = 2, +}; + +struct p2p_wowlan_info{ + + u8 is_trigger; + enum P2P_WOWLAN_RECV_FRAME_TYPE wowlan_recv_frame_type; + u8 wowlan_peer_addr[ETH_ALEN]; + u16 wowlan_peer_wpsconfig; + u8 wowlan_peer_is_persistent; + u8 wowlan_peer_invitation_type; +}; + +#endif //CONFIG_P2P_WOWLAN + +struct wifidirect_info{ + _adapter* padapter; + _timer find_phase_timer; + _timer restore_p2p_state_timer; + + // Used to do the scanning. After confirming the peer is availalble, the driver transmits the P2P frame to peer. + _timer pre_tx_scan_timer; + _timer reset_ch_sitesurvey; + _timer reset_ch_sitesurvey2; // Just for resetting the scan limit function by using p2p nego +#ifdef CONFIG_CONCURRENT_MODE + // Used to switch the channel between legacy AP and listen state. + _timer ap_p2p_switch_timer; +#endif + struct tx_provdisc_req_info tx_prov_disc_info; + struct rx_provdisc_req_info rx_prov_disc_info; + struct tx_invite_req_info invitereq_info; + struct profile_info profileinfo[ P2P_MAX_PERSISTENT_GROUP_NUM ]; // Store the profile information of persistent group + struct tx_invite_resp_info inviteresp_info; + struct tx_nego_req_info nego_req_info; + struct group_id_info groupid_info; // Store the group id information when doing the group negotiation handshake. + struct scan_limit_info rx_invitereq_info; // Used for get the limit scan channel from the Invitation procedure + struct scan_limit_info p2p_info; // Used for get the limit scan channel from the P2P negotiation handshake +#ifdef CONFIG_WFD + struct wifi_display_info *wfd_info; +#endif + +#ifdef CONFIG_P2P_WOWLAN + struct p2p_wowlan_info p2p_wow_info; +#endif //CONFIG_P2P_WOWLAN + + enum P2P_ROLE role; + enum P2P_STATE pre_p2p_state; + enum P2P_STATE p2p_state; + u8 device_addr[ETH_ALEN]; // The device address should be the mac address of this device. + u8 interface_addr[ETH_ALEN]; + u8 social_chan[4]; + u8 listen_channel; + u8 operating_channel; + u8 listen_dwell; // This value should be between 1 and 3 + u8 support_rate[8]; + u8 p2p_wildcard_ssid[P2P_WILDCARD_SSID_LEN]; + u8 intent; // should only include the intent value. + u8 p2p_peer_interface_addr[ ETH_ALEN ]; + u8 p2p_peer_device_addr[ ETH_ALEN ]; + u8 peer_intent; // Included the intent value and tie breaker value. + u8 device_name[ WPS_MAX_DEVICE_NAME_LEN ]; // Device name for displaying on searching device screen + u8 device_name_len; + u8 profileindex; // Used to point to the index of profileinfo array + u8 peer_operating_ch; + u8 find_phase_state_exchange_cnt; + u16 device_password_id_for_nego; // The device password ID for group negotation + u8 negotiation_dialog_token; + u8 nego_ssid[ WLAN_SSID_MAXLEN ]; // SSID information for group negotitation + u8 nego_ssidlen; + u8 p2p_group_ssid[WLAN_SSID_MAXLEN]; + u8 p2p_group_ssid_len; + u8 persistent_supported; // Flag to know the persistent function should be supported or not. + // In the Sigma test, the Sigma will provide this enable from the sta_set_p2p CAPI. + // 0: disable + // 1: enable + u8 session_available; // Flag to set the WFD session available to enable or disable "by Sigma" + // In the Sigma test, the Sigma will disable the session available by using the sta_preset CAPI. + // 0: disable + // 1: enable + + u8 wfd_tdls_enable; // Flag to enable or disable the TDLS by WFD Sigma + // 0: disable + // 1: enable + u8 wfd_tdls_weaksec; // Flag to enable or disable the weak security function for TDLS by WFD Sigma + // 0: disable + // In this case, the driver can't issue the tdsl setup request frame. + // 1: enable + // In this case, the driver can issue the tdls setup request frame + // even the current security is weak security. + + enum P2P_WPSINFO ui_got_wps_info; // This field will store the WPS value (PIN value or PBC) that UI had got from the user. + u16 supported_wps_cm; // This field describes the WPS config method which this driver supported. + // The value should be the combination of config method defined in page104 of WPS v2.0 spec. + u8 external_uuid; // UUID flag + u8 uuid[16]; // UUID + uint channel_list_attr_len; // This field will contain the length of body of P2P Channel List attribute of group negotitation response frame. + u8 channel_list_attr[100]; // This field will contain the body of P2P Channel List attribute of group negotitation response frame. + // We will use the channel_cnt and channel_list fields when constructing the group negotitation confirm frame. + u8 driver_interface; // Indicate DRIVER_WEXT or DRIVER_CFG80211 + +#ifdef CONFIG_CONCURRENT_MODE + u16 ext_listen_interval; // The interval to be available with legacy AP (ms) + u16 ext_listen_period; // The time period to be available for P2P listen state (ms) +#endif +#ifdef CONFIG_P2P_PS + enum P2P_PS_MODE p2p_ps_mode; // indicate p2p ps mode + enum P2P_PS_STATE p2p_ps_state; // indicate p2p ps state + u8 noa_index; // Identifies and instance of Notice of Absence timing. + u8 ctwindow; // Client traffic window. A period of time in TU after TBTT. + u8 opp_ps; // opportunistic power save. + u8 noa_num; // number of NoA descriptor in P2P IE. + u8 noa_count[P2P_MAX_NOA_NUM]; // Count for owner, Type of client. + u32 noa_duration[P2P_MAX_NOA_NUM]; // Max duration for owner, preferred or min acceptable duration for client. + u32 noa_interval[P2P_MAX_NOA_NUM]; // Length of interval for owner, preferred or max acceptable interval of client. + u32 noa_start_time[P2P_MAX_NOA_NUM]; // schedule expressed in terms of the lower 4 bytes of the TSF timer. +#endif // CONFIG_P2P_PS +}; + +struct tdls_ss_record{ //signal strength record + u8 macaddr[ETH_ALEN]; + u8 RxPWDBAll; + u8 is_tdls_sta; // _TRUE: direct link sta, _FALSE: else +}; + +struct tdls_temp_mgmt{ + u8 initiator; // 0: None, 1: we initiate, 2: peer initiate + u8 peer_addr[ETH_ALEN]; +}; + +#ifdef CONFIG_TDLS_CH_SW +struct tdls_ch_switch{ + u32 ch_sw_state; + ATOMIC_T chsw_on; + u8 addr[ETH_ALEN]; + u8 off_ch_num; + u8 ch_offset; + u32 cur_time; + u8 delay_switch_back; + u8 dump_stack; + struct submit_ctx chsw_sctx; +}; +#endif + +struct tdls_info{ + u8 ap_prohibited; + u8 ch_switch_prohibited; + u8 link_established; + u8 sta_cnt; + u8 sta_maximum; /* 1:tdls sta is equal (NUM_STA-1), reach max direct link number; 0: else; */ + struct tdls_ss_record ss_record; +#ifdef CONFIG_TDLS_CH_SW + struct tdls_ch_switch chsw_info; +#endif + + u8 ch_sensing; + u8 cur_channel; + u8 collect_pkt_num[MAX_CHANNEL_NUM]; + _lock cmd_lock; + _lock hdl_lock; + u8 watchdog_count; + u8 dev_discovered; /* WFD_TDLS: for sigma test */ + u8 tdls_enable; + + /* Let wpa_supplicant to setup*/ + u8 driver_setup; +#ifdef CONFIG_WFD + struct wifi_display_info *wfd_info; +#endif +}; + +struct tdls_txmgmt { + u8 peer[ETH_ALEN]; + u8 action_code; + u8 dialog_token; + u16 status_code; + u8 *buf; + size_t len; +}; + +/* used for mlme_priv.roam_flags */ +enum { + RTW_ROAM_ON_EXPIRED = BIT0, + RTW_ROAM_ON_RESUME = BIT1, + RTW_ROAM_ACTIVE = BIT2, +}; + +struct beacon_keys { + u8 ssid[IW_ESSID_MAX_SIZE]; + u32 ssid_len; + u8 bcn_channel; + u16 ht_cap_info; + u8 ht_info_infos_0_sco; // bit0 & bit1 in infos[0] is second channel offset + int encryp_protocol; + int pairwise_cipher; + int group_cipher; + int is_8021x; +}; + +struct mlme_priv { + + _lock lock; + sint fw_state; //shall we protect this variable? maybe not necessarily... + u8 bScanInProcess; + u8 to_join; //flag + #ifdef CONFIG_LAYER2_ROAMING + u8 to_roam; /* roaming trying times */ + struct wlan_network *roam_network; /* the target of active roam */ + u8 roam_flags; + u8 roam_rssi_diff_th; /* rssi difference threshold for active scan candidate selection */ + u32 roam_scan_int_ms; /* scan interval for active roam */ + u32 roam_scanr_exp_ms; /* scan result expire time in ms for roam */ + u8 roam_tgt_addr[ETH_ALEN]; /* request to roam to speicific target without other consideration */ + #endif + + u8 *nic_hdl; + + #ifdef SUPPLICANT_RTK_VERSION_LOWER_THAN_JB42 + u8 not_indic_disco; + #endif + _list *pscanned; + _queue free_bss_pool; + _queue scanned_queue; + u8 *free_bss_buf; + u32 num_of_scanned; + + NDIS_802_11_SSID assoc_ssid; + u8 assoc_bssid[6]; + + struct wlan_network cur_network; + struct wlan_network *cur_network_scanned; + + // bcn check info + struct beacon_keys cur_beacon_keys; // save current beacon keys + struct beacon_keys new_beacon_keys; // save new beacon keys + u8 new_beacon_cnts; // if new_beacon_cnts >= threshold, ap beacon is changed + +#ifdef CONFIG_ARP_KEEP_ALIVE + // for arp offload keep alive + u8 bGetGateway; + u8 gw_mac_addr[6]; + u8 gw_ip[4]; +#endif + + //uint wireless_mode; no used, remove it + + u32 auto_scan_int_ms; + + _timer assoc_timer; + + uint assoc_by_bssid; + uint assoc_by_rssi; + + _timer scan_to_timer; // driver itself handles scan_timeout status. + u32 scan_start_time; // used to evaluate the time spent in scanning + + #ifdef CONFIG_SET_SCAN_DENY_TIMER + _timer set_scan_deny_timer; + ATOMIC_T set_scan_deny; //0: allowed, 1: deny + #endif + + struct qos_priv qospriv; + +#ifdef CONFIG_80211N_HT + + /* Number of non-HT AP/stations */ + int num_sta_no_ht; + + /* Number of HT AP/stations 20 MHz */ + //int num_sta_ht_20mhz; + + + int num_FortyMHzIntolerant; + + struct ht_priv htpriv; + +#endif + +#ifdef CONFIG_80211AC_VHT + struct vht_priv vhtpriv; +#endif +#ifdef CONFIG_BEAMFORMING +#if (BEAMFORMING_SUPPORT == 0)/*for driver beamforming*/ + struct beamforming_info beamforming_info; +#endif +#endif + +#ifdef CONFIG_DFS + u8 handle_dfs; +#endif +#ifdef CONFIG_DFS_MASTER + /* TODO: move to rfctl */ + _timer dfs_master_timer; +#endif + + RT_LINK_DETECT_T LinkDetectInfo; + _timer dynamic_chk_timer; //dynamic/periodic check timer + + u8 acm_mask; // for wmm acm mask + const struct country_chplan *country_ent; + u8 ChannelPlan; + RT_SCAN_TYPE scan_mode; // active: 1, passive: 0 + + u8 *wps_probe_req_ie; + u32 wps_probe_req_ie_len; + + u8 ext_capab_ie_data[8];/*currently for ap mode only*/ + u8 ext_capab_ie_len; + +#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) + /* Number of associated Non-ERP stations (i.e., stations using 802.11b + * in 802.11g BSS) */ + int num_sta_non_erp; + + /* Number of associated stations that do not support Short Slot Time */ + int num_sta_no_short_slot_time; + + /* Number of associated stations that do not support Short Preamble */ + int num_sta_no_short_preamble; + + int olbc; /* Overlapping Legacy BSS Condition (Legacy b/g)*/ + + /* Number of HT associated stations that do not support greenfield */ + int num_sta_ht_no_gf; + + /* Number of associated non-HT stations */ + //int num_sta_no_ht; + + /* Number of HT associated stations 20 MHz */ + int num_sta_ht_20mhz; + + /* number of associated stations 40MHz intolerant */ + int num_sta_40mhz_intolerant; + + /* Overlapping BSS information */ + int olbc_ht; + +#ifdef CONFIG_80211N_HT + int ht_20mhz_width_req; + int ht_intolerant_ch_reported; + u16 ht_op_mode; + u8 sw_to_20mhz; /*switch to 20Mhz BW*/ +#endif /* CONFIG_80211N_HT */ + + u8 *assoc_req; + u32 assoc_req_len; + u8 *assoc_rsp; + u32 assoc_rsp_len; + + u8 *wps_beacon_ie; + //u8 *wps_probe_req_ie; + u8 *wps_probe_resp_ie; + u8 *wps_assoc_resp_ie; // for CONFIG_IOCTL_CFG80211, this IE could include p2p ie / wfd ie + + u32 wps_beacon_ie_len; + //u32 wps_probe_req_ie_len; + u32 wps_probe_resp_ie_len; + u32 wps_assoc_resp_ie_len; // for CONFIG_IOCTL_CFG80211, this IE len could include p2p ie / wfd ie + + u8 *p2p_beacon_ie; + u8 *p2p_probe_req_ie; + u8 *p2p_probe_resp_ie; + u8 *p2p_go_probe_resp_ie; //for GO + u8 *p2p_assoc_req_ie; + u8 *p2p_assoc_resp_ie; + + u32 p2p_beacon_ie_len; + u32 p2p_probe_req_ie_len; + u32 p2p_probe_resp_ie_len; + u32 p2p_go_probe_resp_ie_len; //for GO + u32 p2p_assoc_req_ie_len; + u32 p2p_assoc_resp_ie_len; + + _lock bcn_update_lock; + u8 update_bcn; + + u8 ori_ch; + u8 ori_bw; + u8 ori_offset; +#endif //#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) + +#if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211) + + u8 *wfd_beacon_ie; + u8 *wfd_probe_req_ie; + u8 *wfd_probe_resp_ie; + u8 *wfd_go_probe_resp_ie; //for GO + u8 *wfd_assoc_req_ie; + u8 *wfd_assoc_resp_ie; + + u32 wfd_beacon_ie_len; + u32 wfd_probe_req_ie_len; + u32 wfd_probe_resp_ie_len; + u32 wfd_go_probe_resp_ie_len; //for GO + u32 wfd_assoc_req_ie_len; + u32 wfd_assoc_resp_ie_len; + +#endif + +#ifdef RTK_DMP_PLATFORM + // DMP kobject_hotplug function signal need in passive level + _workitem Linkup_workitem; + _workitem Linkdown_workitem; +#endif + +#ifdef CONFIG_INTEL_WIDI + int widi_state; + int listen_state; + _timer listen_timer; + ATOMIC_T rx_probe_rsp; // 1:receive probe respone from RDS source. + u8 *l2sdTaBuffer; + u8 channel_idx; + u8 group_cnt; //In WiDi 3.5, they specified another scan algo. for WFD/RDS co-existed + u8 sa_ext[L2SDTA_SERVICE_VE_LEN]; + + u8 widi_enable; + /** + * For WiDi 4; upper layer would set + * p2p_primary_device_type_category_id + * p2p_primary_device_type_sub_category_id + * p2p_secondary_device_type_category_id + * p2p_secondary_device_type_sub_category_id + */ + u16 p2p_pdt_cid; + u16 p2p_pdt_scid; + u8 num_p2p_sdt; + u16 p2p_sdt_cid[MAX_NUM_P2P_SDT]; + u16 p2p_sdt_scid[MAX_NUM_P2P_SDT]; + u8 p2p_reject_disable; //When starting NL80211 wpa_supplicant/hostapd, it will call netdev_close + //such that it will cause p2p disabled. Use this flag to reject. +#endif // CONFIG_INTEL_WIDI + +#ifdef CONFIG_CONCURRENT_MODE + u8 scanning_via_buddy_intf; +#endif + +// u8 NumOfBcnInfoChkFail; +// u32 timeBcnInfoChkStart; +}; + +#define mlme_set_scan_to_timer(mlme, ms) \ + do { \ + /* DBG_871X("%s set_scan_to_timer(%p, %d)\n", __FUNCTION__, (mlme), (ms)); */ \ + _set_timer(&(mlme)->scan_to_timer, (ms)); \ + } while(0) + +#define rtw_mlme_set_auto_scan_int(adapter, ms) \ + do { \ + adapter->mlmepriv.auto_scan_int_ms = ms; \ + } while (0) + +void rtw_mlme_reset_auto_scan_int(_adapter *adapter); + +#ifdef CONFIG_AP_MODE + +struct hostapd_priv +{ + _adapter *padapter; + +#ifdef CONFIG_HOSTAPD_MLME + struct net_device *pmgnt_netdev; + struct usb_anchor anchored; +#endif + +}; + +extern int hostapd_mode_init(_adapter *padapter); +extern void hostapd_mode_unload(_adapter *padapter); +#endif + + +extern void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf); +extern void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf); +extern void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf); +extern void rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf); +extern void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf); +extern void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf); +void rtw_sta_mstatus_report(_adapter *adapter); +extern void rtw_atimdone_event_callback(_adapter *adapter, u8 *pbuf); +extern void rtw_cpwm_event_callback(_adapter *adapter, u8 *pbuf); +extern void rtw_wmm_event_callback(PADAPTER padapter, u8 *pbuf); +#ifdef CONFIG_IEEE80211W +void rtw_sta_timeout_event_callback(_adapter *adapter, u8 *pbuf); +#endif /* CONFIG_IEEE80211W */ +extern void rtw_join_timeout_handler(RTW_TIMER_HDL_ARGS); +extern void _rtw_scan_timeout_handler(RTW_TIMER_HDL_ARGS); + +thread_return event_thread(thread_context context); + +extern void rtw_free_network_queue(_adapter *adapter,u8 isfreeall); +extern int rtw_init_mlme_priv(_adapter *adapter);// (struct mlme_priv *pmlmepriv); + +extern void rtw_free_mlme_priv (struct mlme_priv *pmlmepriv); + + +extern sint rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv); +extern sint rtw_set_key(_adapter *adapter,struct security_priv *psecuritypriv,sint keyid, u8 set_tx, bool enqueue); +extern sint rtw_set_auth(_adapter *adapter,struct security_priv *psecuritypriv); + +__inline static u8 *get_bssid(struct mlme_priv *pmlmepriv) +{ //if sta_mode:pmlmepriv->cur_network.network.MacAddress=> bssid + // if adhoc_mode:pmlmepriv->cur_network.network.MacAddress=> ibss mac address + return pmlmepriv->cur_network.network.MacAddress; +} + +__inline static sint check_fwstate(struct mlme_priv *pmlmepriv, sint state) +{ + if (pmlmepriv->fw_state & state) + return _TRUE; + + return _FALSE; +} + +__inline static sint get_fwstate(struct mlme_priv *pmlmepriv) +{ + return pmlmepriv->fw_state; +} + +/* + * No Limit on the calling context, + * therefore set it to be the critical section... + * + * ### NOTE:#### (!!!!) + * MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock + */ +__inline static void set_fwstate(struct mlme_priv *pmlmepriv, sint state) +{ + pmlmepriv->fw_state |= state; + //FOR HW integration + if(_FW_UNDER_SURVEY==state){ + pmlmepriv->bScanInProcess = _TRUE; + } +} + +__inline static void _clr_fwstate_(struct mlme_priv *pmlmepriv, sint state) +{ + pmlmepriv->fw_state &= ~state; + //FOR HW integration + if(_FW_UNDER_SURVEY==state){ + pmlmepriv->bScanInProcess = _FALSE; + } +} + +/* + * No Limit on the calling context, + * therefore set it to be the critical section... + */ +__inline static void clr_fwstate(struct mlme_priv *pmlmepriv, sint state) +{ + _irqL irqL; + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + _clr_fwstate_(pmlmepriv, state); + _exit_critical_bh(&pmlmepriv->lock, &irqL); +} + +__inline static void up_scanned_network(struct mlme_priv *pmlmepriv) +{ + _irqL irqL; + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + pmlmepriv->num_of_scanned++; + _exit_critical_bh(&pmlmepriv->lock, &irqL); +} + +#ifdef CONFIG_CONCURRENT_MODE +sint rtw_buddy_adapter_up(_adapter *padapter); +sint check_buddy_fwstate(_adapter *padapter, sint state); +u8 rtw_get_buddy_bBusyTraffic(_adapter *padapter); +#endif //CONFIG_CONCURRENT_MODE + +__inline static void down_scanned_network(struct mlme_priv *pmlmepriv) +{ + _irqL irqL; + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + pmlmepriv->num_of_scanned--; + _exit_critical_bh(&pmlmepriv->lock, &irqL); +} + +__inline static void set_scanned_network_val(struct mlme_priv *pmlmepriv, sint val) +{ + _irqL irqL; + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + pmlmepriv->num_of_scanned = val; + _exit_critical_bh(&pmlmepriv->lock, &irqL); +} + +extern u16 rtw_get_capability(WLAN_BSSID_EX *bss); +extern void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target); +extern void rtw_disconnect_hdl_under_linked(_adapter* adapter, struct sta_info *psta, u8 free_assoc); +extern void rtw_generate_random_ibss(u8 *pibss); +extern struct wlan_network* rtw_find_network(_queue *scanned_queue, u8 *addr); +extern struct wlan_network* rtw_get_oldest_wlan_network(_queue *scanned_queue); +struct wlan_network *_rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network); +struct wlan_network *rtw_find_same_network(_queue *scanned_queue, struct wlan_network *network); + +extern void rtw_free_assoc_resources(_adapter* adapter, int lock_scanned_queue); +extern void rtw_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_generated); +extern void rtw_indicate_connect(_adapter* adapter); +void rtw_indicate_scan_done( _adapter *padapter, bool aborted); + +void rtw_drv_scan_by_self(_adapter *padapter); +void rtw_scan_wait_completed(_adapter *adapter); +u32 rtw_scan_abort_timeout(_adapter *adapter, u32 timeout_ms); +void rtw_scan_abort_no_wait(_adapter *adapter); +void rtw_scan_abort(_adapter *adapter); + +extern int rtw_restruct_sec_ie(_adapter *adapter,u8 *in_ie,u8 *out_ie,uint in_len); +extern int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, uint initial_out_len); +extern void rtw_init_registrypriv_dev_network(_adapter *adapter); + +extern void rtw_update_registrypriv_dev_network(_adapter *adapter); + +extern void rtw_get_encrypt_decrypt_from_registrypriv(_adapter *adapter); + +extern void _rtw_join_timeout_handler(_adapter *adapter); +extern void rtw_scan_timeout_handler(_adapter *adapter); + +extern void rtw_dynamic_check_timer_handlder(_adapter *adapter); +#ifdef CONFIG_SET_SCAN_DENY_TIMER +bool rtw_is_scan_deny(_adapter *adapter); +void rtw_clear_scan_deny(_adapter *adapter); +void rtw_set_scan_deny_timer_hdl(_adapter *adapter); +void rtw_set_scan_deny(_adapter *adapter, u32 ms); +#else +#define rtw_is_scan_deny(adapter) _FALSE +#define rtw_clear_scan_deny(adapter) do {} while (0) +#define rtw_set_scan_deny_timer_hdl(adapter) do {} while (0) +#define rtw_set_scan_deny(adapter, ms) do {} while (0) +#endif + +void rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv); + +#define MLME_BEACON_IE 0 +#define MLME_PROBE_REQ_IE 1 +#define MLME_PROBE_RESP_IE 2 +#define MLME_GO_PROBE_RESP_IE 3 +#define MLME_ASSOC_REQ_IE 4 +#define MLME_ASSOC_RESP_IE 5 + +#if defined(CONFIG_WFD) && defined(CONFIG_IOCTL_CFG80211) +int rtw_mlme_update_wfd_ie_data(struct mlme_priv *mlme, u8 type, u8 *ie, u32 ie_len); +#endif + +extern int _rtw_init_mlme_priv(_adapter *padapter); +extern void _rtw_free_mlme_priv(struct mlme_priv *pmlmepriv); + +extern int _rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork); + +//extern struct wlan_network* _rtw_dequeue_network(_queue *queue); + +extern struct wlan_network* _rtw_alloc_network(struct mlme_priv *pmlmepriv); + + +extern void _rtw_free_network(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork, u8 isfreeall); +extern void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork); + + +extern struct wlan_network* _rtw_find_network(_queue *scanned_queue, u8 *addr); + +extern void _rtw_free_network_queue(_adapter* padapter, u8 isfreeall); + +extern sint rtw_if_up(_adapter *padapter); + +sint rtw_linked_check(_adapter *padapter); + +u8 *rtw_get_capability_from_ie(u8 *ie); +u8 *rtw_get_timestampe_from_ie(u8 *ie); +u8 *rtw_get_beacon_interval_from_ie(u8 *ie); + + +void rtw_joinbss_reset(_adapter *padapter); + +#ifdef CONFIG_80211N_HT +void rtw_ht_use_default_setting(_adapter *padapter); +void rtw_build_wmm_ie_ht(_adapter *padapter, u8 *out_ie, uint *pout_len); +unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len, u8 channel); +void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len, u8 channel); +void rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe); +void rtw_append_exented_cap(_adapter *padapter, u8 *out_ie, uint *pout_len); +#endif + +int rtw_is_same_ibss(_adapter *adapter, struct wlan_network *pnetwork); +int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst, u8 feature); + +#ifdef CONFIG_LAYER2_ROAMING +#define rtw_roam_flags(adapter) ((adapter)->mlmepriv.roam_flags) +#define rtw_chk_roam_flags(adapter, flags) ((adapter)->mlmepriv.roam_flags & flags) +#define rtw_clr_roam_flags(adapter, flags) \ + do { \ + ((adapter)->mlmepriv.roam_flags &= ~flags); \ + } while (0) + +#define rtw_set_roam_flags(adapter, flags) \ + do { \ + ((adapter)->mlmepriv.roam_flags |= flags); \ + } while (0) + +#define rtw_assign_roam_flags(adapter, flags) \ + do { \ + ((adapter)->mlmepriv.roam_flags = flags); \ + } while (0) + +void _rtw_roaming(_adapter *adapter, struct wlan_network *tgt_network); +void rtw_roaming(_adapter *adapter, struct wlan_network *tgt_network); +void rtw_set_to_roam(_adapter *adapter, u8 to_roam); +u8 rtw_dec_to_roam(_adapter *adapter); +u8 rtw_to_roam(_adapter *adapter); +int rtw_select_roaming_candidate(struct mlme_priv *pmlmepriv); +#else +#define rtw_roam_flags(adapter) 0 +#define rtw_chk_roam_flags(adapter, flags) 0 +#define rtw_clr_roam_flags(adapter, flags) do {} while (0) +#define rtw_set_roam_flags(adapter, flags) do {} while (0) +#define rtw_assign_roam_flags(adapter, flags) do {} while (0) +#define _rtw_roaming(adapter, tgt_network) do {} while(0) +#define rtw_roaming(adapter, tgt_network) do {} while(0) +#define rtw_set_to_roam(adapter, to_roam) do {} while(0) +#define rtw_dec_to_roam(adapter) 0 +#define rtw_to_roam(adapter) 0 +#define rtw_select_roaming_candidate(mlme) _FAIL +#endif /* CONFIG_LAYER2_ROAMING */ + +bool rtw_adjust_chbw(_adapter *adapter, u8 req_ch, u8 *req_bw, u8 *req_offset); + +struct sta_media_status_rpt_cmd_parm { + struct sta_info *sta; + bool connected; +}; + +void rtw_sta_media_status_rpt(_adapter *adapter, struct sta_info *sta, bool connected); +u8 rtw_sta_media_status_rpt_cmd(_adapter *adapter, struct sta_info *sta, bool connected); +void rtw_sta_media_status_rpt_cmd_hdl(_adapter *adapter, struct sta_media_status_rpt_cmd_parm *parm); + +#ifdef CONFIG_INTEL_PROXIM +void rtw_proxim_enable(_adapter *padapter); +void rtw_proxim_disable(_adapter *padapter); +void rtw_proxim_send_packet(_adapter *padapter,u8 *pbuf,u16 len,u8 hw_rate); +#endif //CONFIG_INTEL_PROXIM + +#define IPV4_SRC(_iphdr) (((u8 *)(_iphdr)) + 12) +#define IPV4_DST(_iphdr) (((u8 *)(_iphdr)) + 16) +#define GET_IPV4_IHL(_iphdr) BE_BITS_TO_1BYTE(((u8 *)(_iphdr)) + 0, 0, 4) +#define GET_IPV4_PROTOCOL(_iphdr) BE_BITS_TO_1BYTE(((u8 *)(_iphdr)) + 9, 0, 8) +#define GET_IPV4_SRC(_iphdr) BE_BITS_TO_4BYTE(((u8 *)(_iphdr)) + 12, 0, 32) +#define GET_IPV4_DST(_iphdr) BE_BITS_TO_4BYTE(((u8 *)(_iphdr)) + 16, 0, 32) + +#define GET_UDP_SRC(_udphdr) BE_BITS_TO_2BYTE(((u8 *)(_udphdr)) + 0, 0, 16) +#define GET_UDP_DST(_udphdr) BE_BITS_TO_2BYTE(((u8 *)(_udphdr)) + 2, 0, 16) + +#define TCP_SRC(_tcphdr) (((u8 *)(_tcphdr)) + 0) +#define TCP_DST(_tcphdr) (((u8 *)(_tcphdr)) + 2) +#define GET_TCP_SRC(_tcphdr) BE_BITS_TO_2BYTE(((u8 *)(_tcphdr)) + 0, 0, 16) +#define GET_TCP_DST(_tcphdr) BE_BITS_TO_2BYTE(((u8 *)(_tcphdr)) + 2, 0, 16) +#define GET_TCP_SEQ(_tcphdr) BE_BITS_TO_4BYTE(((u8 *)(_tcphdr)) + 4, 0, 32) +#define GET_TCP_ACK_SEQ(_tcphdr) BE_BITS_TO_4BYTE(((u8 *)(_tcphdr)) + 8, 0, 32) +#define GET_TCP_DOFF(_tcphdr) BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 12, 4, 4) +#define GET_TCP_FIN(_tcphdr) BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 0, 1) +#define GET_TCP_SYN(_tcphdr) BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 1, 1) +#define GET_TCP_RST(_tcphdr) BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 2, 1) +#define GET_TCP_PSH(_tcphdr) BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 3, 1) +#define GET_TCP_ACK(_tcphdr) BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 4, 1) +#define GET_TCP_URG(_tcphdr) BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 5, 1) +#define GET_TCP_ECE(_tcphdr) BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 6, 1) +#define GET_TCP_CWR(_tcphdr) BE_BITS_TO_1BYTE(((u8 *)(_tcphdr)) + 13, 7, 1) + +#endif //__RTL871X_MLME_H_ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_mlme_ext.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_mlme_ext.h new file mode 100644 index 000000000..9fdb560f3 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_mlme_ext.h @@ -0,0 +1,1241 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_MLME_EXT_H_ +#define __RTW_MLME_EXT_H_ + + +// Commented by Albert 20101105 +// Increase the SURVEY_TO value from 100 to 150 ( 100ms to 150ms ) +// The Realtek 8188CE SoftAP will spend around 100ms to send the probe response after receiving the probe request. +// So, this driver tried to extend the dwell time for each scanning channel. +// This will increase the chance to receive the probe response from SoftAP. + +#define SURVEY_TO (100) +#define REAUTH_TO (300) //(50) +#define REASSOC_TO (300) //(50) +//#define DISCONNECT_TO (3000) +#define ADDBA_TO (2000) + +#define LINKED_TO (1) //unit:2 sec, 1x2=2 sec + +#define REAUTH_LIMIT (4) +#define REASSOC_LIMIT (4) +#define READDBA_LIMIT (2) + +#ifdef CONFIG_GSPI_HCI + #define ROAMING_LIMIT 5 +#else + #define ROAMING_LIMIT 8 +#endif +//#define IOCMD_REG0 0x10250370 +//#define IOCMD_REG1 0x10250374 +//#define IOCMD_REG2 0x10250378 + +//#define FW_DYNAMIC_FUN_SWITCH 0x10250364 + +//#define WRITE_BB_CMD 0xF0000001 +//#define SET_CHANNEL_CMD 0xF3000000 +//#define UPDATE_RA_CMD 0xFD0000A2 + +#define _HW_STATE_NOLINK_ 0x00 +#define _HW_STATE_ADHOC_ 0x01 +#define _HW_STATE_STATION_ 0x02 +#define _HW_STATE_AP_ 0x03 +#define _HW_STATE_MONITOR_ 0x04 + + +#define _1M_RATE_ 0 +#define _2M_RATE_ 1 +#define _5M_RATE_ 2 +#define _11M_RATE_ 3 +#define _6M_RATE_ 4 +#define _9M_RATE_ 5 +#define _12M_RATE_ 6 +#define _18M_RATE_ 7 +#define _24M_RATE_ 8 +#define _36M_RATE_ 9 +#define _48M_RATE_ 10 +#define _54M_RATE_ 11 + +/******************************************************** +MCS rate definitions +*********************************************************/ +#define MCS_RATE_1R (0x000000ff) +#define MCS_RATE_2R (0x0000ffff) +#define MCS_RATE_3R (0x00ffffff) +#define MCS_RATE_4R (0xffffffff) +#define MCS_RATE_2R_13TO15_OFF (0x00001fff) + + +extern unsigned char RTW_WPA_OUI[]; +extern unsigned char WMM_OUI[]; +extern unsigned char WPS_OUI[]; +extern unsigned char WFD_OUI[]; +extern unsigned char P2P_OUI[]; + +extern unsigned char WMM_INFO_OUI[]; +extern unsigned char WMM_PARA_OUI[]; + +typedef enum _RT_CHANNEL_DOMAIN +{ + /* ===== 0x00 ~ 0x1F, legacy channel plan ===== */ + RTW_CHPLAN_FCC = 0x00, + RTW_CHPLAN_IC = 0x01, + RTW_CHPLAN_ETSI = 0x02, + RTW_CHPLAN_SPAIN = 0x03, + RTW_CHPLAN_FRANCE = 0x04, + RTW_CHPLAN_MKK = 0x05, + RTW_CHPLAN_MKK1 = 0x06, + RTW_CHPLAN_ISRAEL = 0x07, + RTW_CHPLAN_TELEC = 0x08, + RTW_CHPLAN_GLOBAL_DOAMIN = 0x09, + RTW_CHPLAN_WORLD_WIDE_13 = 0x0A, + RTW_CHPLAN_TAIWAN = 0x0B, + RTW_CHPLAN_CHINA = 0x0C, + RTW_CHPLAN_SINGAPORE_INDIA_MEXICO = 0x0D, + RTW_CHPLAN_KOREA = 0x0E, + RTW_CHPLAN_TURKEY = 0x0F, + RTW_CHPLAN_JAPAN = 0x10, + RTW_CHPLAN_FCC_NO_DFS = 0x11, + RTW_CHPLAN_JAPAN_NO_DFS = 0x12, + RTW_CHPLAN_WORLD_WIDE_5G = 0x13, + RTW_CHPLAN_TAIWAN_NO_DFS = 0x14, + + /* ===== 0x20 ~ 0x7F, new channel plan ===== */ + RTW_CHPLAN_WORLD_NULL = 0x20, + RTW_CHPLAN_ETSI1_NULL = 0x21, + RTW_CHPLAN_FCC1_NULL = 0x22, + RTW_CHPLAN_MKK1_NULL = 0x23, + RTW_CHPLAN_ETSI2_NULL = 0x24, + RTW_CHPLAN_FCC1_FCC1 = 0x25, + RTW_CHPLAN_WORLD_ETSI1 = 0x26, + RTW_CHPLAN_MKK1_MKK1 = 0x27, + RTW_CHPLAN_WORLD_KCC1 = 0x28, + RTW_CHPLAN_WORLD_FCC2 = 0x29, + RTW_CHPLAN_FCC2_NULL = 0x2A, + RTW_CHPLAN_WORLD_FCC3 = 0x30, + RTW_CHPLAN_WORLD_FCC4 = 0x31, + RTW_CHPLAN_WORLD_FCC5 = 0x32, + RTW_CHPLAN_WORLD_FCC6 = 0x33, + RTW_CHPLAN_FCC1_FCC7 = 0x34, + RTW_CHPLAN_WORLD_ETSI2 = 0x35, + RTW_CHPLAN_WORLD_ETSI3 = 0x36, + RTW_CHPLAN_MKK1_MKK2 = 0x37, + RTW_CHPLAN_MKK1_MKK3 = 0x38, + RTW_CHPLAN_FCC1_NCC1 = 0x39, + RTW_CHPLAN_FCC1_NCC2 = 0x40, + RTW_CHPLAN_GLOBAL_NULL = 0x41, + RTW_CHPLAN_ETSI1_ETSI4 = 0x42, + RTW_CHPLAN_FCC1_FCC2 = 0x43, + RTW_CHPLAN_FCC1_NCC3 = 0x44, + RTW_CHPLAN_WORLD_ETSI5 = 0x45, + RTW_CHPLAN_FCC1_FCC8 = 0x46, + RTW_CHPLAN_WORLD_ETSI6 = 0x47, + RTW_CHPLAN_WORLD_ETSI7 = 0x48, + RTW_CHPLAN_WORLD_ETSI8 = 0x49, + RTW_CHPLAN_WORLD_ETSI9 = 0x50, + RTW_CHPLAN_WORLD_ETSI10 = 0x51, + RTW_CHPLAN_WORLD_ETSI11 = 0x52, + RTW_CHPLAN_FCC1_NCC4 = 0x53, + RTW_CHPLAN_WORLD_ETSI12 = 0x54, + RTW_CHPLAN_FCC1_FCC9 = 0x55, + RTW_CHPLAN_WORLD_ETSI13 = 0x56, + RTW_CHPLAN_FCC1_FCC10 = 0x57, + RTW_CHPLAN_MKK2_MKK4 = 0x58, + RTW_CHPLAN_WORLD_ETSI14 = 0x59, + RTW_CHPLAN_FCC1_FCC5 = 0x60, + + RTW_CHPLAN_MAX, + RTW_CHPLAN_REALTEK_DEFINE = 0x7F, +}RT_CHANNEL_DOMAIN, *PRT_CHANNEL_DOMAIN; + +typedef enum _RT_CHANNEL_DOMAIN_2G +{ + RTW_RD_2G_NULL = 0, + RTW_RD_2G_WORLD = 1, /* Worldwird 13 */ + RTW_RD_2G_ETSI1 = 2, /* Europe */ + RTW_RD_2G_FCC1 = 3, /* US */ + RTW_RD_2G_MKK1 = 4, /* Japan */ + RTW_RD_2G_ETSI2 = 5, /* France */ + RTW_RD_2G_GLOBAL = 6, /* Global domain */ + RTW_RD_2G_MKK2 = 7, /* Japan */ + RTW_RD_2G_FCC2 = 8, /* US */ + + RTW_RD_2G_MAX, +}RT_CHANNEL_DOMAIN_2G, *PRT_CHANNEL_DOMAIN_2G; + +typedef enum _RT_CHANNEL_DOMAIN_5G +{ + RTW_RD_5G_NULL = 0, /* */ + RTW_RD_5G_ETSI1 = 1, /* Europe */ + RTW_RD_5G_ETSI2 = 2, /* Australia, New Zealand */ + RTW_RD_5G_ETSI3 = 3, /* Russia */ + RTW_RD_5G_FCC1 = 4, /* US */ + RTW_RD_5G_FCC2 = 5, /* FCC w/o DFS Channels */ + RTW_RD_5G_FCC3 = 6, /* Bolivia, Chile, El Salvador, Venezuela */ + RTW_RD_5G_FCC4 = 7, /* Venezuela */ + RTW_RD_5G_FCC5 = 8, /* China */ + RTW_RD_5G_FCC6 = 9, /* */ + RTW_RD_5G_FCC7 = 10, /* US Canada(w/o Weather radar) */ + RTW_RD_5G_KCC1 = 11, /* Korea */ + RTW_RD_5G_MKK1 = 12, /* Japan */ + RTW_RD_5G_MKK2 = 13, /* Japan (W52, W53) */ + RTW_RD_5G_MKK3 = 14, /* Japan (W56) */ + RTW_RD_5G_NCC1 = 15, /* Taiwan, (w/o Weather radar) */ + RTW_RD_5G_NCC2 = 16, /* Taiwan, Band2, Band4 */ + RTW_RD_5G_NCC3 = 17, /* Taiwan w/o DFS, Band4 only */ + RTW_RD_5G_ETSI4 = 18, /* Europe w/o DFS, Band1 only */ + RTW_RD_5G_ETSI5 = 19, /* Australia, New Zealand(w/o Weather radar) */ + RTW_RD_5G_FCC8 = 20, /* Latin America */ + RTW_RD_5G_ETSI6 = 21, /* Israel, Bahrain, Egypt, India, China, Malaysia */ + RTW_RD_5G_ETSI7 = 22, /* China */ + RTW_RD_5G_ETSI8 = 23, /* Jordan */ + RTW_RD_5G_ETSI9 = 24, /* Lebanon */ + RTW_RD_5G_ETSI10 = 25, /* Qatar */ + RTW_RD_5G_ETSI11 = 26, /* Russia */ + RTW_RD_5G_NCC4 = 27, /* Taiwan, (w/o Weather radar) */ + RTW_RD_5G_ETSI12 = 28, /* Indonesia */ + RTW_RD_5G_FCC9 = 29, /* (w/o Weather radar) */ + RTW_RD_5G_ETSI13 = 30, /* (w/o Weather radar) */ + RTW_RD_5G_FCC10 = 31, /* Argentina(w/o Weather radar) */ + RTW_RD_5G_MKK4 = 32, /* Japan (W52) */ + RTW_RD_5G_ETSI14 = 33, /* Russia */ + + /* === Below are driver defined for legacy channel plan compatible, DON'T assign index ==== */ + RTW_RD_5G_OLD_FCC1, + RTW_RD_5G_OLD_NCC1, + RTW_RD_5G_OLD_KCC1, + + RTW_RD_5G_MAX, +}RT_CHANNEL_DOMAIN_5G, *PRT_CHANNEL_DOMAIN_5G; + +bool rtw_chplan_is_empty(u8 id); +#define rtw_is_channel_plan_valid(chplan) (((chplan) < RTW_CHPLAN_MAX || (chplan) == RTW_CHPLAN_REALTEK_DEFINE) && !rtw_chplan_is_empty(chplan)) +#define rtw_is_legacy_channel_plan(chplan) ((chplan) < 0x20) + +typedef struct _RT_CHANNEL_PLAN +{ + unsigned char Channel[MAX_CHANNEL_NUM]; + unsigned char Len; +}RT_CHANNEL_PLAN, *PRT_CHANNEL_PLAN; + +typedef struct _RT_CHANNEL_PLAN_2G +{ + unsigned char Channel[MAX_CHANNEL_NUM_2G]; + unsigned char Len; +}RT_CHANNEL_PLAN_2G, *PRT_CHANNEL_PLAN_2G; + +typedef struct _RT_CHANNEL_PLAN_5G +{ + unsigned char Channel[MAX_CHANNEL_NUM_5G]; + unsigned char Len; +}RT_CHANNEL_PLAN_5G, *PRT_CHANNEL_PLAN_5G; + +typedef struct _RT_CHANNEL_PLAN_MAP +{ + u8 Index2G; + u8 Index5G; + u8 regd; /* value of REGULATION_TXPWR_LMT */ +}RT_CHANNEL_PLAN_MAP, *PRT_CHANNEL_PLAN_MAP; + +enum Associated_AP +{ + atherosAP = 0, + broadcomAP = 1, + ciscoAP = 2, + marvellAP = 3, + ralinkAP = 4, + realtekAP = 5, + airgocapAP = 6, + unknownAP = 7, + maxAP, +}; + +typedef enum _HT_IOT_PEER +{ + HT_IOT_PEER_UNKNOWN = 0, + HT_IOT_PEER_REALTEK = 1, + HT_IOT_PEER_REALTEK_92SE = 2, + HT_IOT_PEER_BROADCOM = 3, + HT_IOT_PEER_RALINK = 4, + HT_IOT_PEER_ATHEROS = 5, + HT_IOT_PEER_CISCO = 6, + HT_IOT_PEER_MERU = 7, + HT_IOT_PEER_MARVELL = 8, + HT_IOT_PEER_REALTEK_SOFTAP = 9,// peer is RealTek SOFT_AP, by Bohn, 2009.12.17 + HT_IOT_PEER_SELF_SOFTAP = 10, // Self is SoftAP + HT_IOT_PEER_AIRGO = 11, + HT_IOT_PEER_INTEL = 12, + HT_IOT_PEER_RTK_APCLIENT = 13, + HT_IOT_PEER_REALTEK_81XX = 14, + HT_IOT_PEER_REALTEK_WOW = 15, + HT_IOT_PEER_REALTEK_JAGUAR_BCUTAP = 16, + HT_IOT_PEER_REALTEK_JAGUAR_CCUTAP = 17, + HT_IOT_PEER_MAX = 18 +}HT_IOT_PEER_E, *PHTIOT_PEER_E; + +struct mlme_handler { + unsigned int num; + char* str; + unsigned int (*func)(_adapter *padapter, union recv_frame *precv_frame); +}; + +struct action_handler { + unsigned int num; + char* str; + unsigned int (*func)(_adapter *padapter, union recv_frame *precv_frame); +}; + +enum SCAN_STATE +{ + SCAN_DISABLE = 0, + SCAN_START = 1, + SCAN_PS_ANNC_WAIT = 2, + SCAN_ENTER = 3, + SCAN_PROCESS = 4, + + /* backop */ + SCAN_BACKING_OP = 5, + SCAN_BACK_OP = 6, + SCAN_LEAVING_OP = 7, + SCAN_LEAVE_OP = 8, + + /* SW antenna diversity (before linked) */ + SCAN_SW_ANTDIV_BL = 9, + + /* legacy p2p */ + SCAN_TO_P2P_LISTEN = 10, + SCAN_P2P_LISTEN = 11, + + SCAN_COMPLETE = 12, + SCAN_STATE_MAX, +}; + +const char *scan_state_str(u8 state); + +enum ss_backop_flag { + SS_BACKOP_EN = BIT0, /* backop when linked */ + SS_BACKOP_EN_NL = BIT1, /* backop even when no linked */ + + SS_BACKOP_PS_ANNC = BIT4, + SS_BACKOP_TX_RESUME = BIT5, +}; + +struct ss_res { + u8 state; + u8 next_state; /* will set to state on next cmd hdl */ + int bss_cnt; + int channel_idx; + int scan_mode; + u16 scan_ch_ms; + u8 rx_ampdu_accept; + u8 rx_ampdu_size; + u8 igi_scan; + u8 igi_before_scan; /* used for restoring IGI value without enable DIG & FA_CNT */ +#ifdef CONFIG_SCAN_BACKOP + u8 backop_flags_sta; /* policy for station mode*/ + u8 backop_flags_ap; /* policy for ap mode */ + u8 backop_flags; /* per backop runtime decision */ + u8 scan_cnt; + u8 scan_cnt_max; + u32 backop_time; /* the start time of backop */ + u16 backop_ms; +#endif +#if defined(CONFIG_ANTENNA_DIVERSITY) || defined(DBG_SCAN_SW_ANTDIV_BL) + u8 is_sw_antdiv_bl_scan; +#endif + u8 ssid_num; + u8 ch_num; + NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; + struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT]; +}; + +//#define AP_MODE 0x0C +//#define STATION_MODE 0x08 +//#define AD_HOC_MODE 0x04 +//#define NO_LINK_MODE 0x00 + +#define WIFI_FW_NULL_STATE _HW_STATE_NOLINK_ +#define WIFI_FW_STATION_STATE _HW_STATE_STATION_ +#define WIFI_FW_AP_STATE _HW_STATE_AP_ +#define WIFI_FW_ADHOC_STATE _HW_STATE_ADHOC_ + +#define WIFI_FW_AUTH_NULL 0x00000100 +#define WIFI_FW_AUTH_STATE 0x00000200 +#define WIFI_FW_AUTH_SUCCESS 0x00000400 + +#define WIFI_FW_ASSOC_STATE 0x00002000 +#define WIFI_FW_ASSOC_SUCCESS 0x00004000 + +#define WIFI_FW_LINKING_STATE (WIFI_FW_AUTH_NULL | WIFI_FW_AUTH_STATE | WIFI_FW_AUTH_SUCCESS |WIFI_FW_ASSOC_STATE) + +#ifdef CONFIG_TDLS +enum TDLS_option +{ + TDLS_ESTABLISHED = 1, + TDLS_ISSUE_PTI, + TDLS_CH_SW_RESP, + TDLS_CH_SW_PREPARE, + TDLS_CH_SW_START, + TDLS_CH_SW_TO_OFF_CHNL, + TDLS_CH_SW_TO_BASE_CHNL_UNSOLICITED, + TDLS_CH_SW_TO_BASE_CHNL, + TDLS_CH_SW_END_TO_BASE_CHNL, + TDLS_CH_SW_END, + TDLS_RS_RCR, + TDLS_TEARDOWN_STA, + TDLS_TEARDOWN_STA_LOCALLY, + maxTDLS, +}; + +#endif //CONFIG_TDLS + +/* + * Usage: + * When one iface acted as AP mode and the other iface is STA mode and scanning, + * it should switch back to AP's operating channel periodically. + * Parameters info: + * When the driver scanned RTW_SCAN_NUM_OF_CH channels, it would switch back to AP's operating channel for + * RTW_BACK_OP_CH_MS milliseconds. + * Example: + * For chip supports 2.4G + 5GHz and AP mode is operating in channel 1, + * RTW_SCAN_NUM_OF_CH is 8, RTW_BACK_OP_CH_MS is 300 + * When it's STA mode gets set_scan command, + * it would + * 1. Doing the scan on channel 1.2.3.4.5.6.7.8 + * 2. Back to channel 1 for 300 milliseconds + * 3. Go through doing site survey on channel 9.10.11.36.40.44.48.52 + * 4. Back to channel 1 for 300 milliseconds + * 5. ... and so on, till survey done. + */ +#if defined(CONFIG_ATMEL_RC_PATCH) +#define RTW_SCAN_NUM_OF_CH 2 +#define RTW_BACK_OP_CH_MS 200 +#else +#define RTW_SCAN_NUM_OF_CH 3 +#define RTW_BACK_OP_CH_MS 400 +#endif + +struct mlme_ext_info +{ + u32 state; + u32 reauth_count; + u32 reassoc_count; + u32 link_count; + u32 auth_seq; + u32 auth_algo; // 802.11 auth, could be open, shared, auto + u32 authModeToggle; + u32 enc_algo;//encrypt algorithm; + u32 key_index; // this is only valid for legendary wep, 0~3 for key id. + u32 iv; + u8 chg_txt[128]; + u16 aid; + u16 bcn_interval; + u16 capability; + u8 assoc_AP_vendor; + u8 slotTime; + u8 preamble_mode; + u8 WMM_enable; + u8 ERP_enable; + u8 ERP_IE; + u8 HT_enable; + u8 HT_caps_enable; + u8 HT_info_enable; + u8 HT_protection; + u8 turboMode_cts2self; + u8 turboMode_rtsen; + u8 SM_PS; + u8 agg_enable_bitmap; + u8 ADDBA_retry_count; + u8 candidate_tid_bitmap; + u8 dialogToken; + // Accept ADDBA Request + BOOLEAN bAcceptAddbaReq; + u8 bwmode_updated; + u8 hidden_ssid_mode; + u8 VHT_enable; + + struct ADDBA_request ADDBA_req; + struct WMM_para_element WMM_param; + struct HT_caps_element HT_caps; + struct HT_info_element HT_info; + WLAN_BSSID_EX network;//join network or bss_network, if in ap mode, it is the same to cur_network.network +}; + +// The channel information about this channel including joining, scanning, and power constraints. +typedef struct _RT_CHANNEL_INFO +{ + u8 ChannelNum; // The channel number. + RT_SCAN_TYPE ScanType; // Scan type such as passive or active scan. + //u16 ScanPeriod; // Listen time in millisecond in this channel. + //s32 MaxTxPwrDbm; // Max allowed tx power. + //u32 ExInfo; // Extended Information for this channel. +#ifdef CONFIG_FIND_BEST_CHANNEL + u32 rx_count; +#endif +#ifdef CONFIG_DFS_MASTER + u32 non_ocp_end_time; +#endif +}RT_CHANNEL_INFO, *PRT_CHANNEL_INFO; + +#define DFS_MASTER_TIMER_MS 100 +#define CAC_TIME_MS (60*1000) +#define CAC_TIME_CE_MS (10*60*1000) +#define NON_OCP_TIME_MS (30*60*1000) + +#ifdef CONFIG_DFS_MASTER +struct rf_ctl_t; +#define CH_IS_NON_OCP(rt_ch_info) ((rt_ch_info)->non_ocp_end_time > rtw_get_current_time()) +void rtw_rfctl_reset_cac(struct rf_ctl_t *rfctl); +bool rtw_is_cac_reset_needed(_adapter *adapter); +bool _rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset); +bool rtw_rfctl_overlap_radar_detect_ch(struct rf_ctl_t *rfctl); +bool rtw_rfctl_is_tx_blocked_by_cac(struct rf_ctl_t *rfctl); +bool rtw_chset_is_ch_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset); +void rtw_chset_update_non_ocp(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset); +void rtw_chset_update_non_ocp_ms(RT_CHANNEL_INFO *ch_set, u8 ch, u8 bw, u8 offset, int ms); +#else +#define CH_IS_NON_OCP(rt_ch_info) 0 +#define rtw_chset_is_ch_non_ocp(ch_set, ch, bw, offset) _FALSE +#define rtw_rfctl_is_tx_blocked_by_cac(rfctl) _FALSE +#endif + +enum { + RTW_CHF_2G = BIT0, + RTW_CHF_5G = BIT1, + RTW_CHF_DFS = BIT2, + RTW_CHF_LONG_CAC = BIT3, + RTW_CHF_NON_DFS = BIT4, + RTW_CHF_NON_LONG_CAC = BIT5, +}; +bool rtw_choose_available_chbw(_adapter *adapter, u8 req_bw, u8 *dec_ch, u8 *dec_bw, u8 *dec_offset, u8 d_flags); +void dump_country_chplan(void *sel, const struct country_chplan *ent); +void dump_country_chplan_map(void *sel); +void dump_chplan_id_list(void *sel); +void dump_chplan_test(void *sel); +void dump_chset(void *sel, RT_CHANNEL_INFO *ch_set); +void dump_cur_chset(void *sel, _adapter *adapter); + +int rtw_ch_set_search_ch(RT_CHANNEL_INFO *ch_set, const u32 ch); +bool rtw_mlme_band_check(_adapter *adapter, const u32 ch); + +// P2P_MAX_REG_CLASSES - Maximum number of regulatory classes +#define P2P_MAX_REG_CLASSES 10 + +// P2P_MAX_REG_CLASS_CHANNELS - Maximum number of channels per regulatory class +#define P2P_MAX_REG_CLASS_CHANNELS 20 + +// struct p2p_channels - List of supported channels +struct p2p_channels { + // struct p2p_reg_class - Supported regulatory class + struct p2p_reg_class { + // reg_class - Regulatory class (IEEE 802.11-2007, Annex J) + u8 reg_class; + + // channel - Supported channels + u8 channel[P2P_MAX_REG_CLASS_CHANNELS]; + + // channels - Number of channel entries in use + size_t channels; + } reg_class[P2P_MAX_REG_CLASSES]; + + // reg_classes - Number of reg_class entries in use + size_t reg_classes; +}; + +struct p2p_oper_class_map { + enum hw_mode {IEEE80211G,IEEE80211A} mode; + u8 op_class; + u8 min_chan; + u8 max_chan; + u8 inc; + enum { BW20, BW40PLUS, BW40MINUS } bw; +}; + +struct mlme_ext_priv +{ + _adapter *padapter; + u8 mlmeext_init; + ATOMIC_T event_seq; + u16 mgnt_seq; +#ifdef CONFIG_IEEE80211W + u16 sa_query_seq; + u64 mgnt_80211w_IPN; + u64 mgnt_80211w_IPN_rx; +#endif //CONFIG_IEEE80211W + //struct fw_priv fwpriv; + + unsigned char cur_channel; + unsigned char cur_bwmode; + unsigned char cur_ch_offset;//PRIME_CHNL_OFFSET + unsigned char cur_wireless_mode; // NETWORK_TYPE + + unsigned char max_chan_nums; + RT_CHANNEL_INFO channel_set[MAX_CHANNEL_NUM]; + struct p2p_channels channel_list; + unsigned char basicrate[NumRates]; + unsigned char datarate[NumRates]; +#ifdef CONFIG_80211N_HT + unsigned char default_supported_mcs_set[16]; +#endif + + struct ss_res sitesurvey_res; + struct mlme_ext_info mlmext_info;//for sta/adhoc mode, including current scanning/connecting/connected related info. + //for ap mode, network includes ap's cap_info + _timer survey_timer; + _timer link_timer; + + //_timer ADDBA_timer; + u32 last_scan_time; + u8 scan_abort; + u8 tx_rate; // TXRATE when USERATE is set. + + u32 retry; //retry for issue probereq + + u64 TSFValue; + + //for LPS-32K to adaptive bcn early and timeout + u8 adaptive_tsf_done; + u32 bcn_delay_cnt[9]; + u32 bcn_delay_ratio[9]; + u32 bcn_cnt; + u8 DrvBcnEarly; + u8 DrvBcnTimeOut; + +#ifdef CONFIG_AP_MODE + unsigned char bstart_bss; +#endif + +#ifdef CONFIG_80211D + u8 update_channel_plan_by_ap_done; +#endif + //recv_decache check for Action_public frame + u8 action_public_dialog_token; + u16 action_public_rxseq; + +//#ifdef CONFIG_ACTIVE_KEEP_ALIVE_CHECK + u8 active_keep_alive_check; +//#endif +#ifdef DBG_FIXED_CHAN + u8 fixed_chan; +#endif + /* set hw sync bcn tsf register or not */ + u8 en_hw_update_tsf; +}; + +#define mlmeext_msr(mlmeext) ((mlmeext)->mlmext_info.state & 0x03) +#define mlmeext_scan_state(mlmeext) ((mlmeext)->sitesurvey_res.state) +#define mlmeext_scan_state_str(mlmeext) scan_state_str((mlmeext)->sitesurvey_res.state) +#define mlmeext_chk_scan_state(mlmeext, _state) ((mlmeext)->sitesurvey_res.state == (_state)) +#define mlmeext_set_scan_state(mlmeext, _state) \ + do { \ + ((mlmeext)->sitesurvey_res.state = (_state)); \ + ((mlmeext)->sitesurvey_res.next_state = (_state)); \ + /* DBG_871X("set_scan_state:%s\n", scan_state_str(_state)); */ \ + } while (0) + +#define mlmeext_scan_next_state(mlmeext) ((mlmeext)->sitesurvey_res.next_state) +#define mlmeext_set_scan_next_state(mlmeext, _state) \ + do { \ + ((mlmeext)->sitesurvey_res.next_state = (_state)); \ + /* DBG_871X("set_scan_next_state:%s\n", scan_state_str(_state)); */ \ + } while (0) + +#ifdef CONFIG_SCAN_BACKOP +#define mlmeext_scan_backop_flags(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags) +#define mlmeext_chk_scan_backop_flags(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags & (flags)) +#define mlmeext_assign_scan_backop_flags(mlmeext, flags) \ + do { \ + ((mlmeext)->sitesurvey_res.backop_flags = (flags)); \ + DBG_871X("assign_scan_backop_flags:0x%02x\n", (mlmeext)->sitesurvey_res.backop_flags); \ + } while (0) + +#define mlmeext_scan_backop_flags_sta(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags_sta) +#define mlmeext_chk_scan_backop_flags_sta(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags_sta & (flags)) +#define mlmeext_assign_scan_backop_flags_sta(mlmeext, flags) \ + do { \ + ((mlmeext)->sitesurvey_res.backop_flags_sta = (flags)); \ + } while (0) + +#define mlmeext_scan_backop_flags_ap(mlmeext) ((mlmeext)->sitesurvey_res.backop_flags_ap) +#define mlmeext_chk_scan_backop_flags_ap(mlmeext, flags) ((mlmeext)->sitesurvey_res.backop_flags_ap & (flags)) +#define mlmeext_assign_scan_backop_flags_ap(mlmeext, flags) \ + do { \ + ((mlmeext)->sitesurvey_res.backop_flags_ap = (flags)); \ + } while (0) +#else +#define mlmeext_scan_backop_flags(mlmeext) (0) +#define mlmeext_chk_scan_backop_flags(mlmeext, flags) (0) +#define mlmeext_assign_scan_backop_flags(mlmeext, flags) do {} while (0) + +#define mlmeext_scan_backop_flags_sta(mlmeext) (0) +#define mlmeext_chk_scan_backop_flags_sta(mlmeext, flags) (0) +#define mlmeext_assign_scan_backop_flags_sta(mlmeext, flags) do {} while (0) + +#define mlmeext_scan_backop_flags_ap(mlmeext) (0) +#define mlmeext_chk_scan_backop_flags_ap(mlmeext, flags) (0) +#define mlmeext_assign_scan_backop_flags_ap(mlmeext, flags) do {} while (0) +#endif + +void init_mlme_default_rate_set(_adapter* padapter); +int init_mlme_ext_priv(_adapter* padapter); +int init_hw_mlme_ext(_adapter *padapter); +void free_mlme_ext_priv (struct mlme_ext_priv *pmlmeext); +extern void init_mlme_ext_timer(_adapter *padapter); +extern void init_addba_retry_timer(_adapter *padapter, struct sta_info *psta); +extern struct xmit_frame *alloc_mgtxmitframe(struct xmit_priv *pxmitpriv); +struct xmit_frame *alloc_mgtxmitframe_once(struct xmit_priv *pxmitpriv); + +//void fill_fwpriv(_adapter * padapter, struct fw_priv *pfwpriv); + +unsigned char networktype_to_raid(_adapter *adapter,struct sta_info *psta); +unsigned char networktype_to_raid_ex(_adapter *adapter, struct sta_info *psta); + +u8 judge_network_type(_adapter *padapter, unsigned char *rate, int ratelen); +void get_rate_set(_adapter *padapter, unsigned char *pbssrate, int *bssrate_len); +void set_mcs_rate_by_mask(u8 *mcs_set, u32 mask); +void UpdateBrateTbl(_adapter *padapter,u8 *mBratesOS); +void UpdateBrateTblForSoftAP(u8 *bssrateset, u32 bssratelen); +void change_band_update_ie(_adapter *padapter, WLAN_BSSID_EX *pnetwork, u8 ch); + +//void Set_NETYPE1_MSR(_adapter *padapter, u8 type); +//void Set_NETYPE0_MSR(_adapter *padapter, u8 type); +void Set_MSR(_adapter *padapter, u8 type); + +u8 rtw_get_oper_ch(_adapter *adapter); +void rtw_set_oper_ch(_adapter *adapter, u8 ch); +u8 rtw_get_oper_bw(_adapter *adapter); +void rtw_set_oper_bw(_adapter *adapter, u8 bw); +u8 rtw_get_oper_choffset(_adapter *adapter); +void rtw_set_oper_choffset(_adapter *adapter, u8 offset); +u8 rtw_get_center_ch(u8 channel, u8 chnl_bw, u8 chnl_offset); +u32 rtw_get_on_oper_ch_time(_adapter *adapter); +u32 rtw_get_on_cur_ch_time(_adapter *adapter); + +u8 rtw_get_offset_by_ch(u8 channel); + +void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char channel_offset, unsigned short bwmode); +void SelectChannel(_adapter *padapter, unsigned char channel); +void SetBWMode(_adapter *padapter, unsigned short bwmode, unsigned char channel_offset); + +unsigned int decide_wait_for_beacon_timeout(unsigned int bcn_interval); + +void _clear_cam_entry(_adapter *padapter, u8 entry); +void write_cam_from_cache(_adapter *adapter, u8 id); + +/* modify both HW and cache */ +void write_cam(_adapter *padapter, u8 id, u16 ctrl, u8 *mac, u8 *key); +void clear_cam_entry(_adapter *padapter, u8 id); + +/* modify cache only */ +void write_cam_cache(_adapter *adapter, u8 id, u16 ctrl, u8 *mac, u8 *key); +void clear_cam_cache(_adapter *adapter, u8 id); + +void invalidate_cam_all(_adapter *padapter); +void CAM_empty_entry(PADAPTER Adapter, u8 ucIndex); + +void flush_all_cam_entry(_adapter *padapter); + +BOOLEAN IsLegal5GChannel(PADAPTER Adapter, u8 channel); + +void site_survey(_adapter *padapter, u8 survey_channel, RT_SCAN_TYPE ScanType); +u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSID_EX *bssid); +void update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src, _adapter * padapter, bool update_ie); + +int get_bsstype(unsigned short capability); +u8* get_my_bssid(WLAN_BSSID_EX *pnetwork); +u16 get_beacon_interval(WLAN_BSSID_EX *bss); + +int is_client_associated_to_ap(_adapter *padapter); +int is_client_associated_to_ibss(_adapter *padapter); +int is_IBSS_empty(_adapter *padapter); + +unsigned char check_assoc_AP(u8 *pframe, uint len); + +int WMM_param_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +#ifdef CONFIG_WFD +void rtw_process_wfd_ie(_adapter *adapter, u8 *ie, u8 ie_len, const char *tag); +void rtw_process_wfd_ies(_adapter *adapter, u8 *ies, u8 ies_len, const char *tag); +#endif +void WMMOnAssocRsp(_adapter *padapter); + +void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +void HT_info_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +void HTOnAssocRsp(_adapter *padapter); + +void ERP_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +void VCS_update(_adapter *padapter, struct sta_info *psta); +void update_ldpc_stbc_cap(struct sta_info *psta); + +int rtw_get_bcn_keys(ADAPTER *Adapter, u8 *pframe, u32 packet_len, + struct beacon_keys *recv_beacon); +void rtw_dump_bcn_keys(struct beacon_keys *recv_beacon); +int rtw_check_bcn_info(ADAPTER *Adapter, u8 *pframe, u32 packet_len); +void update_beacon_info(_adapter *padapter, u8 *pframe, uint len, struct sta_info *psta); +#ifdef CONFIG_DFS +void process_csa_ie(_adapter *padapter, u8 *pframe, uint len); +#endif //CONFIG_DFS +void update_capinfo(PADAPTER Adapter, u16 updateCap); +void update_wireless_mode(_adapter * padapter); +void update_tx_basic_rate(_adapter *padapter, u8 modulation); +void update_sta_basic_rate(struct sta_info *psta, u8 wireless_mode); +int rtw_ies_get_supported_rate(u8 *ies, uint ies_len, u8 *rate_set, u8 *rate_num); + +//for sta/adhoc mode +void update_sta_info(_adapter *padapter, struct sta_info *psta); +unsigned int update_basic_rate(unsigned char *ptn, unsigned int ptn_sz); +unsigned int update_supported_rate(unsigned char *ptn, unsigned int ptn_sz); +unsigned int update_MCS_rate(struct HT_caps_element *pHT_caps); +void Update_RA_Entry(_adapter *padapter, struct sta_info *psta); +void set_sta_rate(_adapter *padapter, struct sta_info *psta); + +unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, u8 locally_generated); + +unsigned char get_highest_rate_idx(u32 mask); +int support_short_GI(_adapter *padapter, struct HT_caps_element *pHT_caps, u8 bwmode); +unsigned int is_ap_in_tkip(_adapter *padapter); +unsigned int is_ap_in_wep(_adapter *padapter); +unsigned int should_forbid_n_rate(_adapter * padapter); + +s16 rtw_get_camid(_adapter *adapter, struct sta_info* sta, s16 kid); +bool _rtw_camctl_chk_cap(_adapter *adapter, u8 cap); +void _rtw_camctl_set_flags(_adapter *adapter, u32 flags); +void rtw_camctl_set_flags(_adapter *adapter, u32 flags); +void _rtw_camctl_clr_flags(_adapter *adapter, u32 flags); +void rtw_camctl_clr_flags(_adapter *adapter, u32 flags); +bool _rtw_camctl_chk_flags(_adapter *adapter, u32 flags); + +struct sec_cam_bmp; +void dump_sec_cam_map(void *sel, struct sec_cam_bmp *map, u8 max_num); +void rtw_sec_cam_map_clr_all(struct sec_cam_bmp *map); + +bool _rtw_camid_is_gk(_adapter *adapter, u8 cam_id); +bool rtw_camid_is_gk(_adapter *adapter, u8 cam_id); +s16 rtw_camid_search(_adapter *adapter, u8 *addr, s16 kid, s8 gk); +s16 rtw_camid_alloc(_adapter *adapter, struct sta_info *sta, u8 kid, bool *used); +void rtw_camid_free(_adapter *adapter, u8 cam_id); + +struct macid_bmp; +struct macid_ctl_t; +void dump_macid_map(void *sel, struct macid_bmp *map, u8 max_num); +bool rtw_macid_is_set(struct macid_bmp *map, u8 id); +bool rtw_macid_is_used(struct macid_ctl_t *macid_ctl, u8 id); +bool rtw_macid_is_bmc(struct macid_ctl_t *macid_ctl, u8 id); +s8 rtw_macid_get_if_g(struct macid_ctl_t *macid_ctl, u8 id); +s8 rtw_macid_get_ch_g(struct macid_ctl_t *macid_ctl, u8 id); +void rtw_alloc_macid(_adapter *padapter, struct sta_info *psta); +void rtw_release_macid(_adapter *padapter, struct sta_info *psta); +u8 rtw_search_max_mac_id(_adapter *padapter); +void rtw_macid_ctl_set_h2c_msr(struct macid_ctl_t *macid_ctl, u8 id, u8 h2c_msr); +void rtw_macid_ctl_init(struct macid_ctl_t *macid_ctl); +void rtw_macid_ctl_deinit(struct macid_ctl_t *macid_ctl); + +u32 report_join_res(_adapter *padapter, int res); +void report_survey_event(_adapter *padapter, union recv_frame *precv_frame); +void report_surveydone_event(_adapter *padapter); +u32 report_del_sta_event(_adapter *padapter, unsigned char *MacAddr, unsigned short reason, bool enqueue, u8 locally_generated); +void report_add_sta_event(_adapter *padapter, unsigned char *MacAddr); +bool rtw_port_switch_chk(_adapter *adapter); +void report_wmm_edca_update(_adapter *padapter); + +void beacon_timing_control(_adapter *padapter); +u8 chk_bmc_sleepq_cmd(_adapter* padapter); +extern u8 set_tx_beacon_cmd(_adapter*padapter); +unsigned int setup_beacon_frame(_adapter *padapter, unsigned char *beacon_frame); +void update_mgnt_tx_rate(_adapter *padapter, u8 rate); +void update_monitor_frame_attrib(_adapter *padapter, struct pkt_attrib *pattrib); +void update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib); +void update_mgntframe_attrib_addr(_adapter *padapter, struct xmit_frame *pmgntframe); +void dump_mgntframe(_adapter *padapter, struct xmit_frame *pmgntframe); +s32 dump_mgntframe_and_wait(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms); +s32 dump_mgntframe_and_wait_ack(_adapter *padapter, struct xmit_frame *pmgntframe); +s32 dump_mgntframe_and_wait_ack_timeout(_adapter *padapter, struct xmit_frame *pmgntframe, int timeout_ms); + +#ifdef CONFIG_P2P +void issue_probersp_p2p(_adapter *padapter, unsigned char *da); +void issue_p2p_provision_request( _adapter *padapter, u8* pssid, u8 ussidlen, u8* pdev_raddr); +void issue_p2p_GO_request(_adapter *padapter, u8* raddr); +void issue_probereq_p2p(_adapter *padapter, u8 *da); +int issue_probereq_p2p_ex(_adapter *adapter, u8 *da, int try_cnt, int wait_ms); +void issue_p2p_invitation_response(_adapter *padapter, u8* raddr, u8 dialogToken, u8 success); +void issue_p2p_invitation_request(_adapter *padapter, u8* raddr ); +#endif //CONFIG_P2P +void issue_beacon(_adapter *padapter, int timeout_ms); +void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probereq); +void issue_assocreq(_adapter *padapter); +void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *pstat, int pkt_type); +void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status); +void issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 *da); +s32 issue_probereq_ex(_adapter *padapter, NDIS_802_11_SSID *pssid, u8* da, u8 ch, bool append_wps, int try_cnt, int wait_ms); +int issue_nulldata(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms); +s32 issue_nulldata_in_interrupt(PADAPTER padapter, u8 *da, unsigned int power_mode); +int issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid, int try_cnt, int wait_ms); +int issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason); +int issue_deauth_ex(_adapter *padapter, u8 *da, unsigned short reason, int try_cnt, int wait_ms); +void issue_action_spct_ch_switch(_adapter *padapter, u8 *ra, u8 new_ch, u8 ch_offset); +void issue_addba_req(_adapter *adapter, unsigned char *ra, u8 tid); +void issue_addba_rsp(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size); +u8 issue_addba_rsp_wait_ack(_adapter *adapter, unsigned char *ra, u8 tid, u16 status, u8 size, int try_cnt, int wait_ms); +void issue_del_ba(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator); +int issue_del_ba_ex(_adapter *adapter, unsigned char *ra, u8 tid, u16 reason, u8 initiator, int try_cnt, int wait_ms); + +#ifdef CONFIG_IEEE80211W +void issue_action_SA_Query(_adapter *padapter, unsigned char *raddr, unsigned char action, unsigned short tid, u8 key_type); +int issue_deauth_11w(_adapter *padapter, unsigned char *da, unsigned short reason, u8 key_type); +extern void init_dot11w_expire_timer(_adapter *padapter, struct sta_info *psta); +#endif //CONFIG_IEEE80211W +int issue_action_SM_PS(_adapter *padapter , unsigned char *raddr , u8 NewMimoPsMode); +int issue_action_SM_PS_wait_ack(_adapter *padapter, unsigned char *raddr, u8 NewMimoPsMode, int try_cnt, int wait_ms); + +unsigned int send_delba_sta_tid(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid, u8 force); +unsigned int send_delba_sta_tid_wait_ack(_adapter *adapter, u8 initiator, struct sta_info *sta, u8 tid, u8 force); + +unsigned int send_delba(_adapter *padapter, u8 initiator, u8 *addr); +unsigned int send_beacon(_adapter *padapter); + +void start_clnt_assoc(_adapter *padapter); +void start_clnt_auth(_adapter* padapter); +void start_clnt_join(_adapter* padapter); +void start_create_ibss(_adapter* padapter); + +unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame); +unsigned int DoReserved(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAtim(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAction(_adapter *padapter, union recv_frame *precv_frame); + +unsigned int on_action_spct(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAction_qos(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAction_dls(_adapter *padapter, union recv_frame *precv_frame); + +#define RX_AMPDU_ACCEPT_INVALID 0xFF +#define RX_AMPDU_SIZE_INVALID 0xFF + +enum rx_ampdu_reason { + RX_AMPDU_DRV_FIXED = 1, + RX_AMPDU_BTCOEX = 2, /* not used, because BTCOEX has its own variable management */ + RX_AMPDU_DRV_SCAN = 3, +}; +u8 rtw_rx_ampdu_size(_adapter *adapter); +bool rtw_rx_ampdu_is_accept(_adapter *adapter); +bool rtw_rx_ampdu_set_size(_adapter *adapter, u8 size, u8 reason); +bool rtw_rx_ampdu_set_accept(_adapter *adapter, u8 accept, u8 reason); +u8 rx_ampdu_apply_sta_tid(_adapter *adapter, struct sta_info *sta, u8 tid, u8 accept, u8 size); +u8 rx_ampdu_apply_sta(_adapter *adapter, struct sta_info *sta, u8 accept, u8 size); +u16 rtw_rx_ampdu_apply(_adapter *adapter); + +unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame); +unsigned int on_action_public(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame); +#ifdef CONFIG_IEEE80211W +unsigned int OnAction_sa_query(_adapter *padapter, union recv_frame *precv_frame); +#endif //CONFIG_IEEE80211W +unsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAction_vht(_adapter *padapter, union recv_frame *precv_frame); +unsigned int OnAction_p2p(_adapter *padapter, union recv_frame *precv_frame); + + +void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res); +void mlmeext_sta_del_event_callback(_adapter *padapter); +void mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta); + +void linked_status_chk(_adapter *padapter, u8 from_timer); + +void _linked_info_dump(_adapter *padapter); + +void survey_timer_hdl (_adapter *padapter); +void link_timer_hdl (_adapter *padapter); +void addba_timer_hdl(struct sta_info *psta); +#ifdef CONFIG_IEEE80211W +void sa_query_timer_hdl(struct sta_info *psta); +#endif //CONFIG_IEEE80211W +//void reauth_timer_hdl(_adapter *padapter); +//void reassoc_timer_hdl(_adapter *padapter); + +#define set_survey_timer(mlmeext, ms) \ + do { \ + /*DBG_871X("%s set_survey_timer(%p, %d)\n", __FUNCTION__, (mlmeext), (ms));*/ \ + _set_timer(&(mlmeext)->survey_timer, (ms)); \ + } while(0) + +#define set_link_timer(mlmeext, ms) \ + do { \ + /*DBG_871X("%s set_link_timer(%p, %d)\n", __FUNCTION__, (mlmeext), (ms));*/ \ + _set_timer(&(mlmeext)->link_timer, (ms)); \ + } while(0) + +extern int cckrates_included(unsigned char *rate, int ratelen); +extern int cckratesonly_included(unsigned char *rate, int ratelen); + +extern void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr); + +extern void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len); +extern void correct_TSF(_adapter *padapter, struct mlme_ext_priv *pmlmeext); +extern void adaptive_early_32k(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len); +extern u8 traffic_status_watchdog(_adapter *padapter, u8 from_timer); + + +#ifdef CONFIG_CONCURRENT_MODE +sint check_buddy_mlmeinfo_state(_adapter *padapter, u32 state); +#endif + +void rtw_join_done_chk_ch(_adapter *padapter, int join_res); + +int rtw_chk_start_clnt_join(_adapter *padapter, u8 *ch, u8 *bw, u8 *offset); +int rtw_get_ch_setting_union(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset); +int rtw_get_ch_setting_union_no_self(_adapter *adapter, u8 *ch, u8 *bw, u8 *offset); + +void rtw_dev_iface_status(_adapter *adapter, u8 *sta_num, u8 *ld_sta_num, u8 *lg_sta_num + , u8 *ap_num, u8 *ld_ap_num); +void rtw_dev_iface_status_no_self(_adapter *adapter, u8 *sta_num, u8 *ld_sta_num, u8 *lg_sta_num + , u8 *ap_num, u8 *ld_ap_num); + +struct cmd_hdl { + uint parmsize; + u8 (*h2cfuns)(struct _ADAPTER *padapter, u8 *pbuf); +}; + + +u8 read_macreg_hdl(_adapter *padapter, u8 *pbuf); +u8 write_macreg_hdl(_adapter *padapter, u8 *pbuf); +u8 read_bbreg_hdl(_adapter *padapter, u8 *pbuf); +u8 write_bbreg_hdl(_adapter *padapter, u8 *pbuf); +u8 read_rfreg_hdl(_adapter *padapter, u8 *pbuf); +u8 write_rfreg_hdl(_adapter *padapter, u8 *pbuf); + + +u8 NULL_hdl(_adapter *padapter, u8 *pbuf); +u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf); +u8 disconnect_hdl(_adapter *padapter, u8 *pbuf); +u8 createbss_hdl(_adapter *padapter, u8 *pbuf); +u8 setopmode_hdl(_adapter *padapter, u8 *pbuf); +u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf); +u8 setauth_hdl(_adapter *padapter, u8 *pbuf); +u8 setkey_hdl(_adapter *padapter, u8 *pbuf); +u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf); +u8 set_assocsta_hdl(_adapter *padapter, u8 *pbuf); +u8 del_assocsta_hdl(_adapter *padapter, u8 *pbuf); +u8 add_ba_hdl(_adapter *padapter, unsigned char *pbuf); +u8 add_ba_rsp_hdl(_adapter *padapter, unsigned char *pbuf); + +u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf); +u8 h2c_msg_hdl(_adapter *padapter, unsigned char *pbuf); +u8 chk_bmc_sleepq_hdl(_adapter *padapter, unsigned char *pbuf); +u8 tx_beacon_hdl(_adapter *padapter, unsigned char *pbuf); +u8 set_ch_hdl(_adapter *padapter, u8 *pbuf); +u8 set_chplan_hdl(_adapter *padapter, unsigned char *pbuf); +u8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf); +u8 set_csa_hdl(_adapter *padapter, unsigned char *pbuf); //Kurt: Handling DFS channel switch announcement ie. +u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf); +u8 run_in_thread_hdl(_adapter *padapter, u8 *pbuf); +u8 rtw_getmacreg_hdl(_adapter *padapter, u8 *pbuf); + +#define GEN_DRV_CMD_HANDLER(size, cmd) {size, &cmd ## _hdl}, +#define GEN_MLME_EXT_HANDLER(size, cmd) {size, cmd}, + +#ifdef _RTW_CMD_C_ + +struct cmd_hdl wlancmds[] = +{ + GEN_DRV_CMD_HANDLER(sizeof(struct readMAC_parm), rtw_getmacreg) /*0*/ + GEN_DRV_CMD_HANDLER(0, NULL) + GEN_DRV_CMD_HANDLER(0, NULL) + GEN_DRV_CMD_HANDLER(0, NULL) + GEN_DRV_CMD_HANDLER(0, NULL) + GEN_DRV_CMD_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) /*10*/ + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(sizeof (struct joinbss_parm), join_cmd_hdl) /*14*/ + GEN_MLME_EXT_HANDLER(sizeof (struct disconnect_parm), disconnect_hdl) + GEN_MLME_EXT_HANDLER(sizeof (struct createbss_parm), createbss_hdl) + GEN_MLME_EXT_HANDLER(sizeof (struct setopmode_parm), setopmode_hdl) + GEN_MLME_EXT_HANDLER(sizeof (struct sitesurvey_parm), sitesurvey_cmd_hdl) /*18*/ + GEN_MLME_EXT_HANDLER(sizeof (struct setauth_parm), setauth_hdl) + GEN_MLME_EXT_HANDLER(sizeof (struct setkey_parm), setkey_hdl) /*20*/ + GEN_MLME_EXT_HANDLER(sizeof (struct set_stakey_parm), set_stakey_hdl) + GEN_MLME_EXT_HANDLER(sizeof (struct set_assocsta_parm), NULL) + GEN_MLME_EXT_HANDLER(sizeof (struct del_assocsta_parm), NULL) + GEN_MLME_EXT_HANDLER(sizeof (struct setstapwrstate_parm), NULL) + GEN_MLME_EXT_HANDLER(sizeof (struct setbasicrate_parm), NULL) + GEN_MLME_EXT_HANDLER(sizeof (struct getbasicrate_parm), NULL) + GEN_MLME_EXT_HANDLER(sizeof (struct setdatarate_parm), NULL) + GEN_MLME_EXT_HANDLER(sizeof (struct getdatarate_parm), NULL) + GEN_MLME_EXT_HANDLER(sizeof (struct setphyinfo_parm), NULL) + GEN_MLME_EXT_HANDLER(sizeof (struct getphyinfo_parm), NULL) /*30*/ + GEN_MLME_EXT_HANDLER(sizeof (struct setphy_parm), NULL) + GEN_MLME_EXT_HANDLER(sizeof (struct getphy_parm), NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) /*40*/ + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(sizeof(struct addBaReq_parm), add_ba_hdl) + GEN_MLME_EXT_HANDLER(sizeof(struct set_ch_parm), set_ch_hdl) /* 46 */ + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) /*50*/ + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(0, NULL) + GEN_MLME_EXT_HANDLER(sizeof(struct Tx_Beacon_param), tx_beacon_hdl) /*55*/ + + GEN_MLME_EXT_HANDLER(0, mlme_evt_hdl) /*56*/ + GEN_MLME_EXT_HANDLER(0, rtw_drvextra_cmd_hdl) /*57*/ + + GEN_MLME_EXT_HANDLER(0, h2c_msg_hdl) /*58*/ + GEN_MLME_EXT_HANDLER(sizeof(struct SetChannelPlan_param), set_chplan_hdl) /*59*/ + GEN_MLME_EXT_HANDLER(sizeof(struct LedBlink_param), led_blink_hdl) /*60*/ + + GEN_MLME_EXT_HANDLER(sizeof(struct SetChannelSwitch_param), set_csa_hdl) /*61*/ + GEN_MLME_EXT_HANDLER(sizeof(struct TDLSoption_param), tdls_hdl) /*62*/ + GEN_MLME_EXT_HANDLER(0, chk_bmc_sleepq_hdl) /*63*/ + GEN_MLME_EXT_HANDLER(sizeof(struct RunInThread_param), run_in_thread_hdl) /*64*/ + GEN_MLME_EXT_HANDLER(sizeof(struct addBaRsp_parm), add_ba_rsp_hdl) /* 65 */ +}; + +#endif + +struct C2HEvent_Header +{ + +#ifdef CONFIG_LITTLE_ENDIAN + + unsigned int len:16; + unsigned int ID:8; + unsigned int seq:8; + +#elif defined(CONFIG_BIG_ENDIAN) + + unsigned int seq:8; + unsigned int ID:8; + unsigned int len:16; + +#else + +# error "Must be LITTLE or BIG Endian" + +#endif + + unsigned int rsvd; + +}; + +void rtw_dummy_event_callback(_adapter *adapter , u8 *pbuf); +void rtw_fwdbg_event_callback(_adapter *adapter , u8 *pbuf); + +enum rtw_c2h_event +{ + GEN_EVT_CODE(_Read_MACREG)=0, /*0*/ + GEN_EVT_CODE(_Read_BBREG), + GEN_EVT_CODE(_Read_RFREG), + GEN_EVT_CODE(_Read_EEPROM), + GEN_EVT_CODE(_Read_EFUSE), + GEN_EVT_CODE(_Read_CAM), /*5*/ + GEN_EVT_CODE(_Get_BasicRate), + GEN_EVT_CODE(_Get_DataRate), + GEN_EVT_CODE(_Survey), /*8*/ + GEN_EVT_CODE(_SurveyDone), /*9*/ + + GEN_EVT_CODE(_JoinBss) , /*10*/ + GEN_EVT_CODE(_AddSTA), + GEN_EVT_CODE(_DelSTA), + GEN_EVT_CODE(_AtimDone) , + GEN_EVT_CODE(_TX_Report), + GEN_EVT_CODE(_CCX_Report), /*15*/ + GEN_EVT_CODE(_DTM_Report), + GEN_EVT_CODE(_TX_Rate_Statistics), + GEN_EVT_CODE(_C2HLBK), + GEN_EVT_CODE(_FWDBG), + GEN_EVT_CODE(_C2HFEEDBACK), /*20*/ + GEN_EVT_CODE(_ADDBA), + GEN_EVT_CODE(_C2HBCN), + GEN_EVT_CODE(_ReportPwrState), //filen: only for PCIE, USB + GEN_EVT_CODE(_CloseRF), //filen: only for PCIE, work around ASPM + GEN_EVT_CODE(_WMM), /*25*/ +#ifdef CONFIG_IEEE80211W + GEN_EVT_CODE(_TimeoutSTA), +#endif /* CONFIG_IEEE80211W */ + MAX_C2HEVT +}; + + +#ifdef _RTW_MLME_EXT_C_ + +static struct fwevent wlanevents[] = +{ + {0, rtw_dummy_event_callback}, /*0*/ + {0, NULL}, + {0, NULL}, + {0, NULL}, + {0, NULL}, + {0, NULL}, + {0, NULL}, + {0, NULL}, + {0, &rtw_survey_event_callback}, /*8*/ + {sizeof (struct surveydone_event), &rtw_surveydone_event_callback}, /*9*/ + + {0, &rtw_joinbss_event_callback}, /*10*/ + {sizeof(struct stassoc_event), &rtw_stassoc_event_callback}, + {sizeof(struct stadel_event), &rtw_stadel_event_callback}, + {0, &rtw_atimdone_event_callback}, + {0, rtw_dummy_event_callback}, + {0, NULL}, /*15*/ + {0, NULL}, + {0, NULL}, + {0, NULL}, + {0, rtw_fwdbg_event_callback}, + {0, NULL}, /*20*/ + {0, NULL}, + {0, NULL}, + {0, &rtw_cpwm_event_callback}, + {0, NULL}, + {0, &rtw_wmm_event_callback}, /*25*/ +#ifdef CONFIG_IEEE80211W + {sizeof(struct stadel_event), &rtw_sta_timeout_event_callback}, +#endif /* CONFIG_IEEE80211W */ + +}; + +#endif//_RTW_MLME_EXT_C_ + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_mp.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_mp.h new file mode 100644 index 000000000..a0e3c2644 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_mp.h @@ -0,0 +1,979 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_MP_H_ +#define _RTW_MP_H_ + +#define RTWPRIV_VER_INFO 1 + +#define MAX_MP_XMITBUF_SZ 2048 +#define NR_MP_XMITFRAME 8 + +struct mp_xmit_frame +{ + _list list; + + struct pkt_attrib attrib; + + _pkt *pkt; + + int frame_tag; + + _adapter *padapter; + +#ifdef CONFIG_USB_HCI + + //insert urb, irp, and irpcnt info below... + //max frag_cnt = 8 + + u8 *mem_addr; + u32 sz[8]; + +#if defined(PLATFORM_OS_XP) || defined(PLATFORM_LINUX) + PURB pxmit_urb[8]; +#endif + +#ifdef PLATFORM_OS_XP + PIRP pxmit_irp[8]; +#endif + + u8 bpending[8]; + sint ac_tag[8]; + sint last[8]; + uint irpcnt; + uint fragcnt; +#endif /* CONFIG_USB_HCI */ + + uint mem[(MAX_MP_XMITBUF_SZ >> 2)]; +}; + +struct mp_wiparam +{ + u32 bcompleted; + u32 act_type; + u32 io_offset; + u32 io_value; +}; + +typedef void(*wi_act_func)(void* padapter); + +#ifdef PLATFORM_WINDOWS +struct mp_wi_cntx +{ + u8 bmpdrv_unload; + + // Work Item + NDIS_WORK_ITEM mp_wi; + NDIS_EVENT mp_wi_evt; + _lock mp_wi_lock; + u8 bmp_wi_progress; + wi_act_func curractfunc; + // Variable needed in each implementation of CurrActFunc. + struct mp_wiparam param; +}; +#endif + +struct mp_tx +{ + u8 stop; + u32 count, sended; + u8 payload; + struct pkt_attrib attrib; + //struct tx_desc desc; + //u8 resvdtx[7]; + u8 desc[TXDESC_SIZE]; + u8 *pallocated_buf; + u8 *buf; + u32 buf_size, write_size; + _thread_hdl_ PktTxThread; +}; + +#define MP_MAX_LINES 1000 +#define MP_MAX_LINES_BYTES 256 +#define u1Byte u8 +#define s1Byte s8 +#define u4Byte u32 +#define s4Byte s32 +#define u1Byte u8 +#define pu1Byte u8* + +#define u2Byte u16 +#define pu2Byte u16* + +#define u4Byte u32 +#define pu4Byte u32* + +#define u8Byte u64 +#define pu8Byte u64* + +#define s1Byte s8 +#define ps1Byte s8* + +#define s2Byte s16 +#define ps2Byte s16* + +#define s4Byte s32 +#define ps4Byte s32* + +#define s8Byte s64 +#define ps8Byte s64* + +#define UCHAR u8 +#define USHORT u16 +#define UINT u32 +#define ULONG u32 +#define PULONG u32* + +typedef struct _RT_PMAC_PKT_INFO { + UCHAR MCS; + UCHAR Nss; + UCHAR Nsts; + UINT N_sym; + UCHAR SIGA2B3; +} RT_PMAC_PKT_INFO, *PRT_PMAC_PKT_INFO; + +typedef struct _RT_PMAC_TX_INFO { + u8 bEnPMacTx:1; /* 0: Disable PMac 1: Enable PMac */ + u8 Mode:3; /* 0: Packet TX 3:Continuous TX */ + u8 Ntx:4; /* 0-7 */ + u8 TX_RATE; /* MPT_RATE_E */ + u8 TX_RATE_HEX; + u8 TX_SC; + u8 bSGI:1; + u8 bSPreamble:1; + u8 bSTBC:1; + u8 bLDPC:1; + u8 NDP_sound:1; + u8 BandWidth:3; /* 0: 20 1:40 2:80Mhz */ + u8 m_STBC; /* bSTBC + 1 */ + USHORT PacketPeriod; + UINT PacketCount; + UINT PacketLength; + u8 PacketPattern; + USHORT SFD; + u8 SignalField; + u8 ServiceField; + USHORT LENGTH; + u8 CRC16[2]; + u8 LSIG[3]; + u8 HT_SIG[6]; + u8 VHT_SIG_A[6]; + u8 VHT_SIG_B[4]; + u8 VHT_SIG_B_CRC; + u8 VHT_Delimiter[4]; + u8 MacAddress[6]; +} RT_PMAC_TX_INFO, *PRT_PMAC_TX_INFO; + + +typedef VOID (*MPT_WORK_ITEM_HANDLER)(IN PVOID Adapter); +typedef struct _MPT_CONTEXT +{ + // Indicate if we have started Mass Production Test. + BOOLEAN bMassProdTest; + + // Indicate if the driver is unloading or unloaded. + BOOLEAN bMptDrvUnload; + + _sema MPh2c_Sema; + _timer MPh2c_timeout_timer; +// Event used to sync H2c for BT control + + BOOLEAN MptH2cRspEvent; + BOOLEAN MptBtC2hEvent; + BOOLEAN bMPh2c_timeout; + + /* 8190 PCI does not support NDIS_WORK_ITEM. */ + // Work Item for Mass Production Test. + //NDIS_WORK_ITEM MptWorkItem; +// RT_WORK_ITEM MptWorkItem; + // Event used to sync the case unloading driver and MptWorkItem is still in progress. +// NDIS_EVENT MptWorkItemEvent; + // To protect the following variables. +// NDIS_SPIN_LOCK MptWorkItemSpinLock; + // Indicate a MptWorkItem is scheduled and not yet finished. + BOOLEAN bMptWorkItemInProgress; + // An instance which implements function and context of MptWorkItem. + MPT_WORK_ITEM_HANDLER CurrMptAct; + + // 1=Start, 0=Stop from UI. + ULONG MptTestStart; + // _TEST_MODE, defined in MPT_Req2.h + ULONG MptTestItem; + // Variable needed in each implementation of CurrMptAct. + ULONG MptActType; // Type of action performed in CurrMptAct. + // The Offset of IO operation is depend of MptActType. + ULONG MptIoOffset; + // The Value of IO operation is depend of MptActType. + ULONG MptIoValue; + // The RfPath of IO operation is depend of MptActType. + ULONG MptRfPath; + + WIRELESS_MODE MptWirelessModeToSw; // Wireless mode to switch. + u8 MptChannelToSw; // Channel to switch. + u8 MptInitGainToSet; // Initial gain to set. + //ULONG bMptAntennaA; // TRUE if we want to use antenna A. + ULONG MptBandWidth; // bandwidth to switch. + ULONG MptRateIndex; // rate index. + // Register value kept for Single Carrier Tx test. + u8 btMpCckTxPower; + // Register value kept for Single Carrier Tx test. + u8 btMpOfdmTxPower; + // For MP Tx Power index + u8 TxPwrLevel[4]; /* rf-A, rf-B*/ + u32 RegTxPwrLimit; + // Content of RCR Regsiter for Mass Production Test. + ULONG MptRCR; + // TRUE if we only receive packets with specific pattern. + BOOLEAN bMptFilterPattern; + // Rx OK count, statistics used in Mass Production Test. + ULONG MptRxOkCnt; + // Rx CRC32 error count, statistics used in Mass Production Test. + ULONG MptRxCrcErrCnt; + + BOOLEAN bCckContTx; // TRUE if we are in CCK Continuous Tx test. + BOOLEAN bOfdmContTx; // TRUE if we are in OFDM Continuous Tx test. + BOOLEAN bStartContTx; // TRUE if we have start Continuous Tx test. + // TRUE if we are in Single Carrier Tx test. + BOOLEAN bSingleCarrier; + // TRUE if we are in Carrier Suppression Tx Test. + BOOLEAN bCarrierSuppression; + //TRUE if we are in Single Tone Tx test. + BOOLEAN bSingleTone; + + // ACK counter asked by K.Y.. + BOOLEAN bMptEnableAckCounter; + ULONG MptAckCounter; + + // SD3 Willis For 8192S to save 1T/2T RF table for ACUT Only fro ACUT delete later ~~~! + //s1Byte BufOfLines[2][MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; + //s1Byte BufOfLines[2][MP_MAX_LINES][MP_MAX_LINES_BYTES]; + //s4Byte RfReadLine[2]; + + u8 APK_bound[2]; //for APK path A/path B + BOOLEAN bMptIndexEven; + + u8 backup0xc50; + u8 backup0xc58; + u8 backup0xc30; + u8 backup0x52_RF_A; + u8 backup0x52_RF_B; + + u4Byte backup0x58_RF_A; + u4Byte backup0x58_RF_B; + + u1Byte h2cReqNum; + u1Byte c2hBuf[32]; + + u1Byte btInBuf[100]; + ULONG mptOutLen; + u1Byte mptOutBuf[100]; + RT_PMAC_TX_INFO PMacTxInfo; + RT_PMAC_PKT_INFO PMacPktInfo; + u8 HWTxmode; + + BOOLEAN bldpc; + BOOLEAN bstbc; +}MPT_CONTEXT, *PMPT_CONTEXT; +//#endif + +/* E-Fuse */ +#ifdef CONFIG_RTL8188E +#define EFUSE_MAP_SIZE 512 +#endif +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) +#define EFUSE_MAP_SIZE 512 +#endif +#ifdef CONFIG_RTL8192E +#define EFUSE_MAP_SIZE 512 +#endif +#ifdef CONFIG_RTL8723B +#define EFUSE_MAP_SIZE 512 +#endif +#ifdef CONFIG_RTL8814A +#define EFUSE_MAP_SIZE 512 +#endif +#ifdef CONFIG_RTL8703B +#define EFUSE_MAP_SIZE 512 +#endif +#ifdef CONFIG_RTL8188F +#define EFUSE_MAP_SIZE 512 +#endif + +#if defined(CONFIG_RTL8814A) +#define EFUSE_MAX_SIZE 1024 +#elif defined(CONFIG_RTL8188E) || defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8703B) +#define EFUSE_MAX_SIZE 256 +#else +#define EFUSE_MAX_SIZE 512 +#endif +/* end of E-Fuse */ + +//#define RTPRIV_IOCTL_MP ( SIOCIWFIRSTPRIV + 0x17) +enum { + WRITE_REG = 1, + READ_REG, + WRITE_RF, + READ_RF, + MP_START, + MP_STOP, + MP_RATE, + MP_CHANNEL, + MP_BANDWIDTH, + MP_TXPOWER, + MP_ANT_TX, + MP_ANT_RX, + MP_CTX, + MP_QUERY, + MP_ARX, + MP_PSD, + MP_PWRTRK, + MP_THER, + MP_IOCTL, + EFUSE_GET, + EFUSE_SET, + MP_RESET_STATS, + MP_DUMP, + MP_PHYPARA, + MP_SetRFPathSwh, + MP_QueryDrvStats, + MP_SetBT, + CTA_TEST, + MP_DISABLE_BT_COEXIST, + MP_PwrCtlDM, + MP_GETVER, + MP_MON, + EFUSE_MASK, + EFUSE_FILE, + MP_TX, + MP_RX, + MP_HW_TX_MODE, + MP_CUSTOMER_STR, + MP_NULL, + MP_GET_TXPOWER_INX, + + MP_SD_IREAD, + MP_SD_IWRITE, +}; + +struct mp_priv +{ + _adapter *papdater; + + //Testing Flag + u32 mode;//0 for normal type packet, 1 for loopback packet (16bytes TXCMD) + + u32 prev_fw_state; + + //OID cmd handler + struct mp_wiparam workparam; +// u8 act_in_progress; + + //Tx Section + u8 TID; + u32 tx_pktcount; + u32 pktInterval; + u32 pktLength; + struct mp_tx tx; + + //Rx Section + u32 rx_bssidpktcount; + u32 rx_pktcount; + u32 rx_pktcount_filter_out; + u32 rx_crcerrpktcount; + u32 rx_pktloss; + BOOLEAN rx_bindicatePkt; + struct recv_stat rxstat; + + //RF/BB relative + u8 channel; + u8 bandwidth; + u8 prime_channel_offset; + u8 txpoweridx; + u8 rateidx; + u32 preamble; +// u8 modem; + u32 CrystalCap; +// u32 curr_crystalcap; + + u16 antenna_tx; + u16 antenna_rx; +// u8 curr_rfpath; + + u8 check_mp_pkt; + + u8 bSetTxPower; +// uint ForcedDataRate; + u8 mp_dm; + u8 mac_filter[ETH_ALEN]; + u8 bmac_filter; + + struct wlan_network mp_network; + NDIS_802_11_MAC_ADDRESS network_macaddr; + +#ifdef PLATFORM_WINDOWS + u32 rx_testcnt; + u32 rx_testcnt1; + u32 rx_testcnt2; + u32 tx_testcnt; + u32 tx_testcnt1; + + struct mp_wi_cntx wi_cntx; + + u8 h2c_result; + u8 h2c_seqnum; + u16 h2c_cmdcode; + u8 h2c_resp_parambuf[512]; + _lock h2c_lock; + _lock wkitm_lock; + u32 h2c_cmdcnt; + NDIS_EVENT h2c_cmd_evt; + NDIS_EVENT c2h_set; + NDIS_EVENT h2c_clr; + NDIS_EVENT cpwm_int; + + NDIS_EVENT scsir_full_evt; + NDIS_EVENT scsiw_empty_evt; +#endif + + u8 *pallocated_mp_xmitframe_buf; + u8 *pmp_xmtframe_buf; + _queue free_mp_xmitqueue; + u32 free_mp_xmitframe_cnt; + BOOLEAN bSetRxBssid; + BOOLEAN bTxBufCkFail; + BOOLEAN bRTWSmbCfg; + BOOLEAN bloopback; + MPT_CONTEXT MptCtx; + + u8 *TXradomBuffer; +}; + +typedef struct _IOCMD_STRUCT_ { + u8 cmdclass; + u16 value; + u8 index; +}IOCMD_STRUCT; + +struct rf_reg_param { + u32 path; + u32 offset; + u32 value; +}; + +struct bb_reg_param { + u32 offset; + u32 value; +}; + +typedef struct _MP_FIRMWARE { + FIRMWARE_SOURCE eFWSource; +#ifdef CONFIG_EMBEDDED_FWIMG + u8* szFwBuffer; +#else + u8 szFwBuffer[0x8000]; +#endif + u32 ulFwLength; +} RT_MP_FIRMWARE, *PRT_MP_FIRMWARE; + + + + +//======================================================================= + +#define LOWER _TRUE +#define RAISE _FALSE + +/* Hardware Registers */ +#if 0 +#if 0 +#define IOCMD_CTRL_REG 0x102502C0 +#define IOCMD_DATA_REG 0x102502C4 +#else +#define IOCMD_CTRL_REG 0x10250370 +#define IOCMD_DATA_REG 0x10250374 +#endif + +#define IOCMD_GET_THERMAL_METER 0xFD000028 + +#define IOCMD_CLASS_BB_RF 0xF0 +#define IOCMD_BB_READ_IDX 0x00 +#define IOCMD_BB_WRITE_IDX 0x01 +#define IOCMD_RF_READ_IDX 0x02 +#define IOCMD_RF_WRIT_IDX 0x03 +#endif +#define BB_REG_BASE_ADDR 0x800 + +/* MP variables */ +#if 0 +#define _2MAC_MODE_ 0 +#define _LOOPBOOK_MODE_ 1 +#endif +typedef enum _MP_MODE_ { + MP_OFF, + MP_ON, + MP_ERR, + MP_CONTINUOUS_TX, + MP_SINGLE_CARRIER_TX, + MP_CARRIER_SUPPRISSION_TX, + MP_SINGLE_TONE_TX, + MP_PACKET_TX, + MP_PACKET_RX +} MP_MODE; + +typedef enum _TEST_MODE { + TEST_NONE , + PACKETS_TX , + PACKETS_RX , + CONTINUOUS_TX , + OFDM_Single_Tone_TX , + CCK_Carrier_Suppression_TX +} TEST_MODE; + + +typedef enum _MPT_BANDWIDTH { + MPT_BW_20MHZ = 0, + MPT_BW_40MHZ_DUPLICATE = 1, + MPT_BW_40MHZ_ABOVE = 2, + MPT_BW_40MHZ_BELOW = 3, + MPT_BW_40MHZ = 4, + MPT_BW_80MHZ = 5, + MPT_BW_80MHZ_20_ABOVE = 6, + MPT_BW_80MHZ_20_BELOW = 7, + MPT_BW_80MHZ_20_BOTTOM = 8, + MPT_BW_80MHZ_20_TOP = 9, + MPT_BW_80MHZ_40_ABOVE = 10, + MPT_BW_80MHZ_40_BELOW = 11, +} MPT_BANDWIDTHE, *PMPT_BANDWIDTH; + +#define MAX_RF_PATH_NUMS RF_PATH_MAX + + +extern u8 mpdatarate[NumRates]; + +/* MP set force data rate base on the definition. */ +typedef enum _MPT_RATE_INDEX +{ + /* CCK rate. */ + MPT_RATE_1M = 1 , /* 0 */ + MPT_RATE_2M, + MPT_RATE_55M, + MPT_RATE_11M, /* 3 */ + + /* OFDM rate. */ + MPT_RATE_6M, /* 4 */ + MPT_RATE_9M, + MPT_RATE_12M, + MPT_RATE_18M, + MPT_RATE_24M, + MPT_RATE_36M, + MPT_RATE_48M, + MPT_RATE_54M, /* 11 */ + + /* HT rate. */ + MPT_RATE_MCS0, /* 12 */ + MPT_RATE_MCS1, + MPT_RATE_MCS2, + MPT_RATE_MCS3, + MPT_RATE_MCS4, + MPT_RATE_MCS5, + MPT_RATE_MCS6, + MPT_RATE_MCS7, /* 19 */ + MPT_RATE_MCS8, + MPT_RATE_MCS9, + MPT_RATE_MCS10, + MPT_RATE_MCS11, + MPT_RATE_MCS12, + MPT_RATE_MCS13, + MPT_RATE_MCS14, + MPT_RATE_MCS15, /* 27 */ + MPT_RATE_MCS16, + MPT_RATE_MCS17, // #29 + MPT_RATE_MCS18, + MPT_RATE_MCS19, + MPT_RATE_MCS20, + MPT_RATE_MCS21, + MPT_RATE_MCS22, // #34 + MPT_RATE_MCS23, + MPT_RATE_MCS24, + MPT_RATE_MCS25, + MPT_RATE_MCS26, + MPT_RATE_MCS27, // #39 + MPT_RATE_MCS28, // #40 + MPT_RATE_MCS29, // #41 + MPT_RATE_MCS30, // #42 + MPT_RATE_MCS31, // #43 + /* VHT rate. Total: 20*/ + MPT_RATE_VHT1SS_MCS0 = 100,/* #44*/ + MPT_RATE_VHT1SS_MCS1, // # + MPT_RATE_VHT1SS_MCS2, + MPT_RATE_VHT1SS_MCS3, + MPT_RATE_VHT1SS_MCS4, + MPT_RATE_VHT1SS_MCS5, + MPT_RATE_VHT1SS_MCS6, // # + MPT_RATE_VHT1SS_MCS7, + MPT_RATE_VHT1SS_MCS8, + MPT_RATE_VHT1SS_MCS9, //#53 + MPT_RATE_VHT2SS_MCS0, //#54 + MPT_RATE_VHT2SS_MCS1, + MPT_RATE_VHT2SS_MCS2, + MPT_RATE_VHT2SS_MCS3, + MPT_RATE_VHT2SS_MCS4, + MPT_RATE_VHT2SS_MCS5, + MPT_RATE_VHT2SS_MCS6, + MPT_RATE_VHT2SS_MCS7, + MPT_RATE_VHT2SS_MCS8, + MPT_RATE_VHT2SS_MCS9, //#63 + MPT_RATE_VHT3SS_MCS0, + MPT_RATE_VHT3SS_MCS1, + MPT_RATE_VHT3SS_MCS2, + MPT_RATE_VHT3SS_MCS3, + MPT_RATE_VHT3SS_MCS4, + MPT_RATE_VHT3SS_MCS5, + MPT_RATE_VHT3SS_MCS6, // #126 + MPT_RATE_VHT3SS_MCS7, + MPT_RATE_VHT3SS_MCS8, + MPT_RATE_VHT3SS_MCS9, + MPT_RATE_VHT4SS_MCS0, + MPT_RATE_VHT4SS_MCS1, // #131 + MPT_RATE_VHT4SS_MCS2, + MPT_RATE_VHT4SS_MCS3, + MPT_RATE_VHT4SS_MCS4, + MPT_RATE_VHT4SS_MCS5, + MPT_RATE_VHT4SS_MCS6, // #136 + MPT_RATE_VHT4SS_MCS7, + MPT_RATE_VHT4SS_MCS8, + MPT_RATE_VHT4SS_MCS9, + MPT_RATE_LAST +}MPT_RATE_E, *PMPT_RATE_E; + +#define MAX_TX_PWR_INDEX_N_MODE 64 // 0x3F + +#define MPT_IS_CCK_RATE(_value) (MPT_RATE_1M <= _value && _value <= MPT_RATE_11M) +#define MPT_IS_OFDM_RATE(_value) (MPT_RATE_6M <= _value && _value <= MPT_RATE_54M) +#define MPT_IS_HT_RATE(_value) (MPT_RATE_MCS0 <= _value && _value <= MPT_RATE_MCS31) +#define MPT_IS_HT_1S_RATE(_value) (MPT_RATE_MCS0 <= _value && _value <= MPT_RATE_MCS7) +#define MPT_IS_HT_2S_RATE(_value) (MPT_RATE_MCS8 <= _value && _value <= MPT_RATE_MCS15) +#define MPT_IS_HT_3S_RATE(_value) (MPT_RATE_MCS16 <= _value && _value <= MPT_RATE_MCS23) +#define MPT_IS_HT_4S_RATE(_value) (MPT_RATE_MCS24 <= _value && _value <= MPT_RATE_MCS31) + +#define MPT_IS_VHT_RATE(_value) (MPT_RATE_VHT1SS_MCS0 <= _value && _value <= MPT_RATE_VHT4SS_MCS9) +#define MPT_IS_VHT_1S_RATE(_value) (MPT_RATE_VHT1SS_MCS0 <= _value && _value <= MPT_RATE_VHT1SS_MCS9) +#define MPT_IS_VHT_2S_RATE(_value) (MPT_RATE_VHT2SS_MCS0 <= _value && _value <= MPT_RATE_VHT2SS_MCS9) +#define MPT_IS_VHT_3S_RATE(_value) (MPT_RATE_VHT3SS_MCS0 <= _value && _value <= MPT_RATE_VHT3SS_MCS9) +#define MPT_IS_VHT_4S_RATE(_value) (MPT_RATE_VHT4SS_MCS0 <= _value && _value <= MPT_RATE_VHT4SS_MCS9) + +#define MPT_IS_2SS_RATE(_rate) ((MPT_RATE_MCS8 <= _rate && _rate <= MPT_RATE_MCS15) ||\ + (MPT_RATE_VHT2SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT2SS_MCS9)) +#define MPT_IS_3SS_RATE(_rate) ((MPT_RATE_MCS16 <= _rate && _rate <= MPT_RATE_MCS23) ||\ + (MPT_RATE_VHT3SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT3SS_MCS9)) +#define MPT_IS_4SS_RATE(_rate) ((MPT_RATE_MCS24 <= _rate && _rate <= MPT_RATE_MCS31) ||\ + (MPT_RATE_VHT4SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT4SS_MCS9)) + +typedef enum _POWER_MODE_ { + POWER_LOW = 0, + POWER_NORMAL +}POWER_MODE; + +// The following enumeration is used to define the value of Reg0xD00[30:28] or JaguarReg0x914[18:16]. +typedef enum _OFDM_TX_MODE { + OFDM_ALL_OFF = 0, + OFDM_ContinuousTx = 1, + OFDM_SingleCarrier = 2, + OFDM_SingleTone = 4, +} OFDM_TX_MODE; + + +#define RX_PKT_BROADCAST 1 +#define RX_PKT_DEST_ADDR 2 +#define RX_PKT_PHY_MATCH 3 + +#define Mac_OFDM_OK 0x00000000 +#define Mac_OFDM_Fail 0x10000000 +#define Mac_OFDM_FasleAlarm 0x20000000 +#define Mac_CCK_OK 0x30000000 +#define Mac_CCK_Fail 0x40000000 +#define Mac_CCK_FasleAlarm 0x50000000 +#define Mac_HT_OK 0x60000000 +#define Mac_HT_Fail 0x70000000 +#define Mac_HT_FasleAlarm 0x90000000 +#define Mac_DropPacket 0xA0000000 + +typedef enum _ENCRY_CTRL_STATE_ { + HW_CONTROL, //hw encryption& decryption + SW_CONTROL, //sw encryption& decryption + HW_ENCRY_SW_DECRY, //hw encryption & sw decryption + SW_ENCRY_HW_DECRY //sw encryption & hw decryption +}ENCRY_CTRL_STATE; + +typedef enum _MPT_TXPWR_DEF{ + MPT_CCK, + MPT_OFDM, // L and HT OFDM + MPT_OFDM_AND_HT, + MPT_HT, + MPT_VHT +}MPT_TXPWR_DEF; + +#ifdef CONFIG_RF_POWER_TRIM + +#if defined(CONFIG_RTL8723B) + #define REG_RF_BB_GAIN_OFFSET 0x7f + #define RF_GAIN_OFFSET_MASK 0xfffff +#elif defined(CONFIG_RTL8188E) + #define REG_RF_BB_GAIN_OFFSET 0x55 + #define RF_GAIN_OFFSET_MASK 0xfffff +#else + #define REG_RF_BB_GAIN_OFFSET 0x55 + #define RF_GAIN_OFFSET_MASK 0xfffff +#endif //CONFIG_RTL8723B + +#endif /*CONFIG_RF_POWER_TRIM*/ + +#define IS_MPT_HT_RATE(_rate) (_rate >= MPT_RATE_MCS0 && _rate <= MPT_RATE_MCS31) +#define IS_MPT_VHT_RATE(_rate) (_rate >= MPT_RATE_VHT1SS_MCS0 && _rate <= MPT_RATE_VHT4SS_MCS9) +#define IS_MPT_CCK_RATE(_rate) (_rate >= MPT_RATE_1M && _rate <= MPT_RATE_11M) +#define IS_MPT_OFDM_RATE(_rate) (_rate >= MPT_RATE_6M && _rate <= MPT_RATE_54M) +//======================================================================= +//extern struct mp_xmit_frame *alloc_mp_xmitframe(struct mp_priv *pmp_priv); +//extern int free_mp_xmitframe(struct xmit_priv *pxmitpriv, struct mp_xmit_frame *pmp_xmitframe); + +extern s32 init_mp_priv(PADAPTER padapter); +extern void free_mp_priv(struct mp_priv *pmp_priv); +extern s32 MPT_InitializeAdapter(PADAPTER padapter, u8 Channel); +extern void MPT_DeInitAdapter(PADAPTER padapter); +extern s32 mp_start_test(PADAPTER padapter); +extern void mp_stop_test(PADAPTER padapter); + +extern u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask); +extern void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val); + +extern u32 read_macreg(_adapter *padapter, u32 addr, u32 sz); +extern void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz); +extern u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask); +extern void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val); +extern u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr); +extern void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val); + +void SetChannel(PADAPTER pAdapter); +void SetBandwidth(PADAPTER pAdapter); +int SetTxPower(PADAPTER pAdapter); +void SetAntenna(PADAPTER pAdapter); +void SetDataRate(PADAPTER pAdapter); +void SetAntenna(PADAPTER pAdapter); +s32 SetThermalMeter(PADAPTER pAdapter, u8 target_ther); +void GetThermalMeter(PADAPTER pAdapter, u8 *value); +void SetContinuousTx(PADAPTER pAdapter, u8 bStart); +void SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart); +void SetSingleToneTx(PADAPTER pAdapter, u8 bStart); +void SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart); +void PhySetTxPowerLevel(PADAPTER pAdapter); +void fill_txdesc_for_mp(PADAPTER padapter, u8 *ptxdesc); +void SetPacketTx(PADAPTER padapter); +void SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB); +void ResetPhyRxPktCount(PADAPTER pAdapter); +u32 GetPhyRxPktReceived(PADAPTER pAdapter); +u32 GetPhyRxPktCRC32Error(PADAPTER pAdapter); +s32 SetPowerTracking(PADAPTER padapter, u8 enable); +void GetPowerTracking(PADAPTER padapter, u8 *enable); +u32 mp_query_psd(PADAPTER pAdapter, u8 *data); + + + +void hal_mpt_SwitchRfSetting(PADAPTER pAdapter); +s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable); +void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable); +void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14); +void hal_mpt_SetChannel(PADAPTER pAdapter); +void hal_mpt_SetBandwidth(PADAPTER pAdapter); +void hal_mpt_SetTxPower(PADAPTER pAdapter); +void hal_mpt_SetDataRate(PADAPTER pAdapter); +void hal_mpt_SetAntenna(PADAPTER pAdapter); +s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther); +void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter); +u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter); +void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 *value); +void hal_mpt_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven); +void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart); +void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart); +void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart); +void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart); +void hal_mpt_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart); +void hal_mpt_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart); +void mpt_ProSetPMacTx(PADAPTER Adapter); + +void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter , BOOLEAN bMain); +ULONG mpt_ProQueryCalTxPower(PADAPTER pAdapter, u8 RfPath); +void MPT_PwrCtlDM(PADAPTER padapter, u32 bstart); +u8 MptToMgntRate(u32 MptRateIdx); +u8 rtw_mpRateParseFunc(PADAPTER pAdapter, u8 *targetStr); +u32 mp_join(PADAPTER padapter, u8 mode); +u32 hal_mpt_query_phytxok(PADAPTER pAdapter); + +void +PMAC_Get_Pkt_Param( + PRT_PMAC_TX_INFO pPMacTxInfo, + PRT_PMAC_PKT_INFO pPMacPktInfo + ); +void +CCK_generator( + PRT_PMAC_TX_INFO pPMacTxInfo, + PRT_PMAC_PKT_INFO pPMacPktInfo + ); +void +PMAC_Nsym_generator( + PRT_PMAC_TX_INFO pPMacTxInfo, + PRT_PMAC_PKT_INFO pPMacPktInfo + ); +void +L_SIG_generator( + UINT N_SYM, /* Max: 750*/ + PRT_PMAC_TX_INFO pPMacTxInfo, + PRT_PMAC_PKT_INFO pPMacPktInfo + ); + +void HT_SIG_generator( + PRT_PMAC_TX_INFO pPMacTxInfo, + PRT_PMAC_PKT_INFO pPMacPktInfo); + +void VHT_SIG_A_generator( + PRT_PMAC_TX_INFO pPMacTxInfo, + PRT_PMAC_PKT_INFO pPMacPktInfo); + +void VHT_SIG_B_generator( + PRT_PMAC_TX_INFO pPMacTxInfo); + +void VHT_Delimiter_generator( + PRT_PMAC_TX_INFO pPMacTxInfo); + + +int rtw_mp_write_reg(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_read_reg(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_write_rf(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_read_rf(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_start(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_stop(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_rate(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_channel(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_bandwidth(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_txpower_index(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_txpower(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_txpower(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_ant_tx(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_ant_rx(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_set_ctx_destAddr(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_ctx(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_disable_bt_coexist(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int rtw_mp_disable_bt_coexist(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int rtw_mp_arx(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_trx_query(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_pwrtrk(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_psd(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_thermal(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_reset_stats(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_dump(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_phypara(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_SetRFPath(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_QueryDrv(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int rtw_mp_PwrCtlDM(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra); +int rtw_mp_getver(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int rtw_mp_mon(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int rtw_efuse_mask_file(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int rtw_efuse_file_map(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int rtw_mp_SetBT(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int rtw_mp_pretx_proc(PADAPTER padapter, u8 bStartTest, char *extra); +int rtw_mp_tx(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int rtw_mp_rx(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +int rtw_mp_hwtx(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +u8 HwRateToMPTRate(u8 rate); + +#endif //_RTW_MP_H_ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_mp_ioctl.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_mp_ioctl.h new file mode 100644 index 000000000..cd6303c2d --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_mp_ioctl.h @@ -0,0 +1,591 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_MP_IOCTL_H_ +#define _RTW_MP_IOCTL_H_ + +#include +#include + +#if 0 +#define TESTFWCMDNUMBER 1000000 +#define TEST_H2CINT_WAIT_TIME 500 +#define TEST_C2HINT_WAIT_TIME 500 +#define HCI_TEST_SYSCFG_HWMASK 1 +#define _BUSCLK_40M (4 << 2) +#endif +//------------------------------------------------------------------------------ +typedef struct CFG_DBG_MSG_STRUCT { + u32 DebugLevel; + u32 DebugComponent_H32; + u32 DebugComponent_L32; +}CFG_DBG_MSG_STRUCT,*PCFG_DBG_MSG_STRUCT; + +typedef struct _RW_REG { + u32 offset; + u32 width; + u32 value; +}mp_rw_reg,RW_Reg, *pRW_Reg; + +//for OID_RT_PRO_READ16_EEPROM & OID_RT_PRO_WRITE16_EEPROM +typedef struct _EEPROM_RW_PARAM { + u32 offset; + u16 value; +}eeprom_rw_param,EEPROM_RWParam, *pEEPROM_RWParam; + +typedef struct _EFUSE_ACCESS_STRUCT_ { + u16 start_addr; + u16 cnts; + u8 data[0]; +}EFUSE_ACCESS_STRUCT, *PEFUSE_ACCESS_STRUCT; + +typedef struct _BURST_RW_REG { + u32 offset; + u32 len; + u8 Data[256]; +}burst_rw_reg,Burst_RW_Reg, *pBurst_RW_Reg; + +typedef struct _USB_VendorReq{ + u8 bRequest; + u16 wValue; + u16 wIndex; + u16 wLength; + u8 u8Dir;//0:OUT, 1:IN + u8 u8InData; +}usb_vendor_req, USB_VendorReq, *pUSB_VendorReq; + +typedef struct _DR_VARIABLE_STRUCT_ { + u8 offset; + u32 variable; +}DR_VARIABLE_STRUCT; + +//int mp_start_joinbss(_adapter *padapter, NDIS_802_11_SSID *pssid); + +//void _irqlevel_changed_(_irqL *irqlevel, /*BOOLEAN*/unsigned char bLower); +#ifdef PLATFORM_OS_XP +static void _irqlevel_changed_(_irqL *irqlevel, u8 bLower) +{ + + if (bLower == LOWER) { + *irqlevel = KeGetCurrentIrql(); + + if (*irqlevel > PASSIVE_LEVEL) { + KeLowerIrql(PASSIVE_LEVEL); + } + } else { + if (KeGetCurrentIrql() == PASSIVE_LEVEL) { + KeRaiseIrql(DISPATCH_LEVEL, irqlevel); + } + } + +} +#else +#define _irqlevel_changed_(a,b) +#endif + +//oid_rtl_seg_81_80_00 +NDIS_STATUS oid_rt_pro_set_data_rate_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_start_test_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_stop_test_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_set_channel_direct_call_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_set_antenna_bb_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_set_tx_power_control_hdl(struct oid_par_priv* poid_par_priv); +//oid_rtl_seg_81_80_20 +NDIS_STATUS oid_rt_pro_query_tx_packet_sent_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_query_rx_packet_received_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_query_rx_packet_crc32_error_hdl(struct oid_par_priv* poid_par_priv); + +NDIS_STATUS oid_rt_pro_reset_tx_packet_sent_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_reset_rx_packet_received_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_set_modulation_hdl(struct oid_par_priv* poid_par_priv); + +NDIS_STATUS oid_rt_pro_set_continuous_tx_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_set_single_carrier_tx_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_set_carrier_suppression_tx_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_set_single_tone_tx_hdl(struct oid_par_priv* poid_par_priv); + + +//oid_rtl_seg_81_87 +NDIS_STATUS oid_rt_pro_write_bb_reg_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_read_bb_reg_hdl(struct oid_par_priv* poid_par_priv); + +NDIS_STATUS oid_rt_pro_write_rf_reg_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_read_rf_reg_hdl(struct oid_par_priv* poid_par_priv); + + +//oid_rtl_seg_81_85 +NDIS_STATUS oid_rt_wireless_mode_hdl(struct oid_par_priv* poid_par_priv); + + +// oid_rtl_seg_87_11_00 +NDIS_STATUS oid_rt_pro8711_join_bss_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_read_register_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_write_register_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_burst_read_register_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_burst_write_register_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_write_txcmd_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_read16_eeprom_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_write16_eeprom_hdl (struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro8711_wi_poll_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro8711_pkt_loss_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_rd_attrib_mem_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_wr_attrib_mem_hdl (struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_set_rf_intfs_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_poll_rx_status_hdl(struct oid_par_priv* poid_par_priv); +// oid_rtl_seg_87_11_20 +NDIS_STATUS oid_rt_pro_cfg_debug_message_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_set_data_rate_ex_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_set_basic_rate_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_read_tssi_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_set_power_tracking_hdl(struct oid_par_priv* poid_par_priv); +//oid_rtl_seg_87_11_50 +NDIS_STATUS oid_rt_pro_qry_pwrstate_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_set_pwrstate_hdl(struct oid_par_priv* poid_par_priv); +//oid_rtl_seg_87_11_F0 +NDIS_STATUS oid_rt_pro_h2c_set_rate_table_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_h2c_get_rate_table_hdl(struct oid_par_priv* poid_par_priv); + + +//oid_rtl_seg_87_12_00 +NDIS_STATUS oid_rt_pro_encryption_ctrl_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_add_sta_info_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_dele_sta_info_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_query_dr_variable_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_rx_packet_type_hdl(struct oid_par_priv* poid_par_priv); + +NDIS_STATUS oid_rt_pro_read_efuse_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_write_efuse_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_rw_efuse_pgpkt_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_get_efuse_current_size_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_efuse_hdl(struct oid_par_priv *poid_par_priv); +NDIS_STATUS oid_rt_pro_efuse_map_hdl(struct oid_par_priv *poid_par_priv); + +NDIS_STATUS oid_rt_set_bandwidth_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_set_crystal_cap_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_set_rx_packet_type_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_get_efuse_max_size_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_pro_set_tx_agc_offset_hdl(struct oid_par_priv* poid_par_priv); + +NDIS_STATUS oid_rt_pro_set_pkt_test_mode_hdl(struct oid_par_priv* poid_par_priv); + +NDIS_STATUS oid_rt_get_thermal_meter_hdl(struct oid_par_priv* poid_par_priv); + +NDIS_STATUS oid_rt_reset_phy_rx_packet_count_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_get_phy_rx_packet_received_hdl(struct oid_par_priv* poid_par_priv); +NDIS_STATUS oid_rt_get_phy_rx_packet_crc32_error_hdl(struct oid_par_priv* poid_par_priv); + +NDIS_STATUS oid_rt_set_power_down_hdl(struct oid_par_priv* poid_par_priv); + +NDIS_STATUS oid_rt_get_power_mode_hdl(struct oid_par_priv* poid_par_priv); + +NDIS_STATUS oid_rt_pro_trigger_gpio_hdl(struct oid_par_priv *poid_par_priv); + +#ifdef _RTW_MP_IOCTL_C_ + +const struct oid_obj_priv oid_rtl_seg_81_80_00[] = +{ + {1, &oid_null_function}, //0x00 OID_RT_PRO_RESET_DUT + {1, &oid_rt_pro_set_data_rate_hdl}, //0x01 + {1, &oid_rt_pro_start_test_hdl}, //0x02 + {1, &oid_rt_pro_stop_test_hdl}, //0x03 + {1, &oid_null_function}, //0x04 OID_RT_PRO_SET_PREAMBLE + {1, &oid_null_function}, //0x05 OID_RT_PRO_SET_SCRAMBLER + {1, &oid_null_function}, //0x06 OID_RT_PRO_SET_FILTER_BB + {1, &oid_null_function}, //0x07 OID_RT_PRO_SET_MANUAL_DIVERSITY_BB + {1, &oid_rt_pro_set_channel_direct_call_hdl}, //0x08 + {1, &oid_null_function}, //0x09 OID_RT_PRO_SET_SLEEP_MODE_DIRECT_CALL + {1, &oid_null_function}, //0x0A OID_RT_PRO_SET_WAKE_MODE_DIRECT_CALL + {1, &oid_rt_pro_set_continuous_tx_hdl}, //0x0B OID_RT_PRO_SET_TX_CONTINUOUS_DIRECT_CALL + {1, &oid_rt_pro_set_single_carrier_tx_hdl}, //0x0C OID_RT_PRO_SET_SINGLE_CARRIER_TX_CONTINUOUS + {1, &oid_null_function}, //0x0D OID_RT_PRO_SET_TX_ANTENNA_BB + {1, &oid_rt_pro_set_antenna_bb_hdl}, //0x0E + {1, &oid_null_function}, //0x0F OID_RT_PRO_SET_CR_SCRAMBLER + {1, &oid_null_function}, //0x10 OID_RT_PRO_SET_CR_NEW_FILTER + {1, &oid_rt_pro_set_tx_power_control_hdl}, //0x11 OID_RT_PRO_SET_TX_POWER_CONTROL + {1, &oid_null_function}, //0x12 OID_RT_PRO_SET_CR_TX_CONFIG + {1, &oid_null_function}, //0x13 OID_RT_PRO_GET_TX_POWER_CONTROL + {1, &oid_null_function}, //0x14 OID_RT_PRO_GET_CR_SIGNAL_QUALITY + {1, &oid_null_function}, //0x15 OID_RT_PRO_SET_CR_SETPOINT + {1, &oid_null_function}, //0x16 OID_RT_PRO_SET_INTEGRATOR + {1, &oid_null_function}, //0x17 OID_RT_PRO_SET_SIGNAL_QUALITY + {1, &oid_null_function}, //0x18 OID_RT_PRO_GET_INTEGRATOR + {1, &oid_null_function}, //0x19 OID_RT_PRO_GET_SIGNAL_QUALITY + {1, &oid_null_function}, //0x1A OID_RT_PRO_QUERY_EEPROM_TYPE + {1, &oid_null_function}, //0x1B OID_RT_PRO_WRITE_MAC_ADDRESS + {1, &oid_null_function}, //0x1C OID_RT_PRO_READ_MAC_ADDRESS + {1, &oid_null_function}, //0x1D OID_RT_PRO_WRITE_CIS_DATA + {1, &oid_null_function}, //0x1E OID_RT_PRO_READ_CIS_DATA + {1, &oid_null_function} //0x1F OID_RT_PRO_WRITE_POWER_CONTROL + +}; + +const struct oid_obj_priv oid_rtl_seg_81_80_20[] = +{ + {1, &oid_null_function}, //0x20 OID_RT_PRO_READ_POWER_CONTROL + {1, &oid_null_function}, //0x21 OID_RT_PRO_WRITE_EEPROM + {1, &oid_null_function}, //0x22 OID_RT_PRO_READ_EEPROM + {1, &oid_rt_pro_reset_tx_packet_sent_hdl}, //0x23 + {1, &oid_rt_pro_query_tx_packet_sent_hdl}, //0x24 + {1, &oid_rt_pro_reset_rx_packet_received_hdl}, //0x25 + {1, &oid_rt_pro_query_rx_packet_received_hdl}, //0x26 + {1, &oid_rt_pro_query_rx_packet_crc32_error_hdl}, //0x27 + {1, &oid_null_function}, //0x28 OID_RT_PRO_QUERY_CURRENT_ADDRESS + {1, &oid_null_function}, //0x29 OID_RT_PRO_QUERY_PERMANENT_ADDRESS + {1, &oid_null_function}, //0x2A OID_RT_PRO_SET_PHILIPS_RF_PARAMETERS + {1, &oid_rt_pro_set_carrier_suppression_tx_hdl},//0x2B OID_RT_PRO_SET_CARRIER_SUPPRESSION_TX + {1, &oid_null_function}, //0x2C OID_RT_PRO_RECEIVE_PACKET + {1, &oid_null_function}, //0x2D OID_RT_PRO_WRITE_EEPROM_BYTE + {1, &oid_null_function}, //0x2E OID_RT_PRO_READ_EEPROM_BYTE + {1, &oid_rt_pro_set_modulation_hdl} //0x2F + +}; + +const struct oid_obj_priv oid_rtl_seg_81_80_40[] = +{ + {1, &oid_null_function}, //0x40 + {1, &oid_null_function}, //0x41 + {1, &oid_null_function}, //0x42 + {1, &oid_rt_pro_set_single_tone_tx_hdl}, //0x43 + {1, &oid_null_function}, //0x44 + {1, &oid_null_function} //0x45 +}; + +const struct oid_obj_priv oid_rtl_seg_81_80_80[] = +{ + {1, &oid_null_function}, //0x80 OID_RT_DRIVER_OPTION + {1, &oid_null_function}, //0x81 OID_RT_RF_OFF + {1, &oid_null_function} //0x82 OID_RT_AUTH_STATUS + +}; + +const struct oid_obj_priv oid_rtl_seg_81_85[] = +{ + {1, &oid_rt_wireless_mode_hdl} //0x00 OID_RT_WIRELESS_MODE +}; + +struct oid_obj_priv oid_rtl_seg_81_87[] = +{ + {1, &oid_null_function}, //0x80 OID_RT_PRO8187_WI_POLL + {1, &oid_rt_pro_write_bb_reg_hdl}, //0x81 + {1, &oid_rt_pro_read_bb_reg_hdl}, //0x82 + {1, &oid_rt_pro_write_rf_reg_hdl}, //0x82 + {1, &oid_rt_pro_read_rf_reg_hdl} //0x83 +}; + +struct oid_obj_priv oid_rtl_seg_87_11_00[] = +{ + {1, &oid_rt_pro8711_join_bss_hdl}, //0x00 //S + {1, &oid_rt_pro_read_register_hdl}, //0x01 + {1, &oid_rt_pro_write_register_hdl}, //0x02 + {1, &oid_rt_pro_burst_read_register_hdl}, //0x03 + {1, &oid_rt_pro_burst_write_register_hdl}, //0x04 + {1, &oid_rt_pro_write_txcmd_hdl}, //0x05 + {1, &oid_rt_pro_read16_eeprom_hdl}, //0x06 + {1, &oid_rt_pro_write16_eeprom_hdl}, //0x07 + {1, &oid_null_function}, //0x08 OID_RT_PRO_H2C_SET_COMMAND + {1, &oid_null_function}, //0x09 OID_RT_PRO_H2C_QUERY_RESULT + {1, &oid_rt_pro8711_wi_poll_hdl}, //0x0A + {1, &oid_rt_pro8711_pkt_loss_hdl}, //0x0B + {1, &oid_rt_rd_attrib_mem_hdl}, //0x0C + {1, &oid_rt_wr_attrib_mem_hdl}, //0x0D + {1, &oid_null_function}, //0x0E + {1, &oid_null_function}, //0x0F + {1, &oid_null_function}, //0x10 OID_RT_PRO_H2C_CMD_MODE + {1, &oid_null_function}, //0x11 OID_RT_PRO_H2C_CMD_RSP_MODE + {1, &oid_null_function}, //0X12 OID_RT_PRO_WAIT_C2H_EVENT + {1, &oid_null_function}, //0X13 OID_RT_PRO_RW_ACCESS_PROTOCOL_TEST + {1, &oid_null_function}, //0X14 OID_RT_PRO_SCSI_ACCESS_TEST + {1, &oid_null_function}, //0X15 OID_RT_PRO_SCSI_TCPIPOFFLOAD_OUT + {1, &oid_null_function}, //0X16 OID_RT_PRO_SCSI_TCPIPOFFLOAD_IN + {1, &oid_null_function}, //0X17 OID_RT_RRO_RX_PKT_VIA_IOCTRL + {1, &oid_null_function}, //0X18 OID_RT_RRO_RX_PKTARRAY_VIA_IOCTRL + {1, &oid_null_function}, //0X19 OID_RT_RPO_SET_PWRMGT_TEST + {1, &oid_null_function}, //0X1A + {1, &oid_null_function}, //0X1B OID_RT_PRO_QRY_PWRMGT_TEST + {1, &oid_null_function}, //0X1C OID_RT_RPO_ASYNC_RWIO_TEST + {1, &oid_null_function}, //0X1D OID_RT_RPO_ASYNC_RWIO_POLL + {1, &oid_rt_pro_set_rf_intfs_hdl}, //0X1E + {1, &oid_rt_poll_rx_status_hdl} //0X1F +}; + +struct oid_obj_priv oid_rtl_seg_87_11_20[] = +{ + {1, &oid_rt_pro_cfg_debug_message_hdl}, //0x20 + {1, &oid_rt_pro_set_data_rate_ex_hdl}, //0x21 + {1, &oid_rt_pro_set_basic_rate_hdl}, //0x22 + {1, &oid_rt_pro_read_tssi_hdl}, //0x23 + {1, &oid_rt_pro_set_power_tracking_hdl} //0x24 +}; + + +struct oid_obj_priv oid_rtl_seg_87_11_50[] = +{ + {1, &oid_rt_pro_qry_pwrstate_hdl}, //0x50 + {1, &oid_rt_pro_set_pwrstate_hdl} //0x51 +}; + +struct oid_obj_priv oid_rtl_seg_87_11_80[] = +{ + {1, &oid_null_function} //0x80 +}; + +struct oid_obj_priv oid_rtl_seg_87_11_B0[] = +{ + {1, &oid_null_function} //0xB0 +}; + +struct oid_obj_priv oid_rtl_seg_87_11_F0[] = +{ + {1, &oid_null_function}, //0xF0 + {1, &oid_null_function}, //0xF1 + {1, &oid_null_function}, //0xF2 + {1, &oid_null_function}, //0xF3 + {1, &oid_null_function}, //0xF4 + {1, &oid_null_function}, //0xF5 + {1, &oid_null_function}, //0xF6 + {1, &oid_null_function}, //0xF7 + {1, &oid_null_function}, //0xF8 + {1, &oid_null_function}, //0xF9 + {1, &oid_null_function}, //0xFA + {1, &oid_rt_pro_h2c_set_rate_table_hdl}, //0xFB + {1, &oid_rt_pro_h2c_get_rate_table_hdl}, //0xFC + {1, &oid_null_function}, //0xFD + {1, &oid_null_function}, //0xFE OID_RT_PRO_H2C_C2H_LBK_TEST + {1, &oid_null_function} //0xFF + +}; + +struct oid_obj_priv oid_rtl_seg_87_12_00[]= +{ + {1, &oid_rt_pro_encryption_ctrl_hdl}, //0x00 Q&S + {1, &oid_rt_pro_add_sta_info_hdl}, //0x01 S + {1, &oid_rt_pro_dele_sta_info_hdl}, //0x02 S + {1, &oid_rt_pro_query_dr_variable_hdl}, //0x03 Q + {1, &oid_rt_pro_rx_packet_type_hdl}, //0x04 Q,S + {1, &oid_rt_pro_read_efuse_hdl}, //0x05 Q OID_RT_PRO_READ_EFUSE + {1, &oid_rt_pro_write_efuse_hdl}, //0x06 S OID_RT_PRO_WRITE_EFUSE + {1, &oid_rt_pro_rw_efuse_pgpkt_hdl}, //0x07 Q,S + {1, &oid_rt_get_efuse_current_size_hdl}, //0x08 Q + {1, &oid_rt_set_bandwidth_hdl}, //0x09 + {1, &oid_rt_set_crystal_cap_hdl}, //0x0a + {1, &oid_rt_set_rx_packet_type_hdl}, //0x0b S + {1, &oid_rt_get_efuse_max_size_hdl}, //0x0c + {1, &oid_rt_pro_set_tx_agc_offset_hdl}, //0x0d + {1, &oid_rt_pro_set_pkt_test_mode_hdl}, //0x0e + {1, &oid_null_function}, //0x0f OID_RT_PRO_FOR_EVM_TEST_SETTING + {1, &oid_rt_get_thermal_meter_hdl}, //0x10 Q OID_RT_PRO_GET_THERMAL_METER + {1, &oid_rt_reset_phy_rx_packet_count_hdl}, //0x11 S OID_RT_RESET_PHY_RX_PACKET_COUNT + {1, &oid_rt_get_phy_rx_packet_received_hdl}, //0x12 Q OID_RT_GET_PHY_RX_PACKET_RECEIVED + {1, &oid_rt_get_phy_rx_packet_crc32_error_hdl}, //0x13 Q OID_RT_GET_PHY_RX_PACKET_CRC32_ERROR + {1, &oid_rt_set_power_down_hdl}, //0x14 Q OID_RT_SET_POWER_DOWN + {1, &oid_rt_get_power_mode_hdl} //0x15 Q OID_RT_GET_POWER_MODE +}; + +#else /* _RTL871X_MP_IOCTL_C_ */ + +extern struct oid_obj_priv oid_rtl_seg_81_80_00[32]; +extern struct oid_obj_priv oid_rtl_seg_81_80_20[16]; +extern struct oid_obj_priv oid_rtl_seg_81_80_40[6]; +extern struct oid_obj_priv oid_rtl_seg_81_80_80[3]; + +extern struct oid_obj_priv oid_rtl_seg_81_85[1]; +extern struct oid_obj_priv oid_rtl_seg_81_87[5]; + +extern struct oid_obj_priv oid_rtl_seg_87_11_00[32]; +extern struct oid_obj_priv oid_rtl_seg_87_11_20[5]; +extern struct oid_obj_priv oid_rtl_seg_87_11_50[2]; +extern struct oid_obj_priv oid_rtl_seg_87_11_80[1]; +extern struct oid_obj_priv oid_rtl_seg_87_11_B0[1]; +extern struct oid_obj_priv oid_rtl_seg_87_11_F0[16]; + +extern struct oid_obj_priv oid_rtl_seg_87_12_00[32]; + +#endif /* _RTL871X_MP_IOCTL_C_ */ + +struct rwreg_param{ + u32 offset; + u32 width; + u32 value; +}; + +struct bbreg_param{ + u32 offset; + u32 phymask; + u32 value; +}; +/* +struct rfchannel_param{ + u32 ch; + u32 modem; +}; +*/ +struct txpower_param{ + u32 pwr_index; +}; + + +struct datarate_param{ + u32 rate_index; +}; + + +struct rfintfs_parm { + u32 rfintfs; +}; + +typedef struct _mp_xmit_parm_ { + u8 enable; + u32 count; + u16 length; + u8 payload_type; + u8 da[ETH_ALEN]; +}MP_XMIT_PARM, *PMP_XMIT_PARM; + +struct mp_xmit_packet { + u32 len; + u32 mem[MAX_MP_XMITBUF_SZ >> 2]; +}; + +struct psmode_param { + u32 ps_mode; + u32 smart_ps; +}; + +//for OID_RT_PRO_READ16_EEPROM & OID_RT_PRO_WRITE16_EEPROM +struct eeprom_rw_param { + u32 offset; + u16 value; +}; + +struct mp_ioctl_handler { + u32 paramsize; + u32 (*handler)(struct oid_par_priv* poid_par_priv); + u32 oid; +}; + +struct mp_ioctl_param{ + u32 subcode; + u32 len; + u8 data[0]; +}; + +#define GEN_MP_IOCTL_SUBCODE(code) _MP_IOCTL_ ## code ## _CMD_ + +enum RTL871X_MP_IOCTL_SUBCODE { + GEN_MP_IOCTL_SUBCODE(MP_START), /*0*/ + GEN_MP_IOCTL_SUBCODE(MP_STOP), + GEN_MP_IOCTL_SUBCODE(READ_REG), + GEN_MP_IOCTL_SUBCODE(WRITE_REG), + GEN_MP_IOCTL_SUBCODE(READ_BB_REG), + GEN_MP_IOCTL_SUBCODE(WRITE_BB_REG), /*5*/ + GEN_MP_IOCTL_SUBCODE(READ_RF_REG), + GEN_MP_IOCTL_SUBCODE(WRITE_RF_REG), + GEN_MP_IOCTL_SUBCODE(SET_CHANNEL), + GEN_MP_IOCTL_SUBCODE(SET_TXPOWER), + GEN_MP_IOCTL_SUBCODE(SET_DATARATE), /*10*/ + GEN_MP_IOCTL_SUBCODE(SET_BANDWIDTH), + GEN_MP_IOCTL_SUBCODE(SET_ANTENNA), + GEN_MP_IOCTL_SUBCODE(CNTU_TX), + GEN_MP_IOCTL_SUBCODE(SC_TX), + GEN_MP_IOCTL_SUBCODE(CS_TX), /*15*/ + GEN_MP_IOCTL_SUBCODE(ST_TX), + GEN_MP_IOCTL_SUBCODE(IOCTL_XMIT_PACKET), + GEN_MP_IOCTL_SUBCODE(SET_RX_PKT_TYPE), + GEN_MP_IOCTL_SUBCODE(RESET_PHY_RX_PKT_CNT), + GEN_MP_IOCTL_SUBCODE(GET_PHY_RX_PKT_RECV), /*20*/ + GEN_MP_IOCTL_SUBCODE(GET_PHY_RX_PKT_ERROR), + GEN_MP_IOCTL_SUBCODE(READ16_EEPROM), + GEN_MP_IOCTL_SUBCODE(WRITE16_EEPROM), + GEN_MP_IOCTL_SUBCODE(EFUSE), + GEN_MP_IOCTL_SUBCODE(EFUSE_MAP), /*25*/ + GEN_MP_IOCTL_SUBCODE(GET_EFUSE_MAX_SIZE), + GEN_MP_IOCTL_SUBCODE(GET_EFUSE_CURRENT_SIZE), + GEN_MP_IOCTL_SUBCODE(GET_THERMAL_METER), + GEN_MP_IOCTL_SUBCODE(SET_PTM), + GEN_MP_IOCTL_SUBCODE(SET_POWER_DOWN), /*30*/ + GEN_MP_IOCTL_SUBCODE(TRIGGER_GPIO), + GEN_MP_IOCTL_SUBCODE(SET_DM_BT), /*32*/ + GEN_MP_IOCTL_SUBCODE(DEL_BA), /*33*/ + GEN_MP_IOCTL_SUBCODE(GET_WIFI_STATUS), /*34*/ + MAX_MP_IOCTL_SUBCODE, +}; + +u32 mp_ioctl_xmit_packet_hdl(struct oid_par_priv* poid_par_priv); + +#ifdef _RTW_MP_IOCTL_C_ + +#define GEN_MP_IOCTL_HANDLER(sz, hdl, oid) {sz, hdl, oid}, + +#define EXT_MP_IOCTL_HANDLER(sz, subcode, oid) {sz, mp_ioctl_ ## subcode ## _hdl, oid}, + + +struct mp_ioctl_handler mp_ioctl_hdl[] = { + +/*0*/ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_start_test_hdl, OID_RT_PRO_START_TEST) + GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_stop_test_hdl, OID_RT_PRO_STOP_TEST) + + GEN_MP_IOCTL_HANDLER(sizeof(struct rwreg_param), oid_rt_pro_read_register_hdl, OID_RT_PRO_READ_REGISTER) + GEN_MP_IOCTL_HANDLER(sizeof(struct rwreg_param), oid_rt_pro_write_register_hdl, OID_RT_PRO_WRITE_REGISTER) + GEN_MP_IOCTL_HANDLER(sizeof(struct bb_reg_param), oid_rt_pro_read_bb_reg_hdl, OID_RT_PRO_READ_BB_REG) +/*5*/ GEN_MP_IOCTL_HANDLER(sizeof(struct bb_reg_param), oid_rt_pro_write_bb_reg_hdl, OID_RT_PRO_WRITE_BB_REG) + GEN_MP_IOCTL_HANDLER(sizeof(struct rf_reg_param), oid_rt_pro_read_rf_reg_hdl, OID_RT_PRO_RF_READ_REGISTRY) + GEN_MP_IOCTL_HANDLER(sizeof(struct rf_reg_param), oid_rt_pro_write_rf_reg_hdl, OID_RT_PRO_RF_WRITE_REGISTRY) + + GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_channel_direct_call_hdl, OID_RT_PRO_SET_CHANNEL_DIRECT_CALL) + GEN_MP_IOCTL_HANDLER(sizeof(struct txpower_param), oid_rt_pro_set_tx_power_control_hdl, OID_RT_PRO_SET_TX_POWER_CONTROL) +/*10*/ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_data_rate_hdl, OID_RT_PRO_SET_DATA_RATE) + GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_set_bandwidth_hdl, OID_RT_SET_BANDWIDTH) + GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_antenna_bb_hdl, OID_RT_PRO_SET_ANTENNA_BB) + + GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_continuous_tx_hdl, OID_RT_PRO_SET_CONTINUOUS_TX) + GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_single_carrier_tx_hdl, OID_RT_PRO_SET_SINGLE_CARRIER_TX) +/*15*/ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_carrier_suppression_tx_hdl, OID_RT_PRO_SET_CARRIER_SUPPRESSION_TX) + GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_single_tone_tx_hdl, OID_RT_PRO_SET_SINGLE_TONE_TX) + + EXT_MP_IOCTL_HANDLER(0, xmit_packet, 0) + + GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_set_rx_packet_type_hdl, OID_RT_SET_RX_PACKET_TYPE) + GEN_MP_IOCTL_HANDLER(0, oid_rt_reset_phy_rx_packet_count_hdl, OID_RT_RESET_PHY_RX_PACKET_COUNT) +/*20*/ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_get_phy_rx_packet_received_hdl, OID_RT_GET_PHY_RX_PACKET_RECEIVED) + GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_get_phy_rx_packet_crc32_error_hdl, OID_RT_GET_PHY_RX_PACKET_CRC32_ERROR) + + GEN_MP_IOCTL_HANDLER(sizeof(struct eeprom_rw_param), NULL, 0) + GEN_MP_IOCTL_HANDLER(sizeof(struct eeprom_rw_param), NULL, 0) + GEN_MP_IOCTL_HANDLER(sizeof(EFUSE_ACCESS_STRUCT), oid_rt_pro_efuse_hdl, OID_RT_PRO_EFUSE) +/*25*/ GEN_MP_IOCTL_HANDLER(0, oid_rt_pro_efuse_map_hdl, OID_RT_PRO_EFUSE_MAP) + GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_get_efuse_max_size_hdl, OID_RT_GET_EFUSE_MAX_SIZE) + GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_get_efuse_current_size_hdl, OID_RT_GET_EFUSE_CURRENT_SIZE) + + GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_get_thermal_meter_hdl, OID_RT_PRO_GET_THERMAL_METER) + GEN_MP_IOCTL_HANDLER(sizeof(u8), oid_rt_pro_set_power_tracking_hdl, OID_RT_PRO_SET_POWER_TRACKING) +/*30*/ GEN_MP_IOCTL_HANDLER(sizeof(u8), oid_rt_set_power_down_hdl, OID_RT_SET_POWER_DOWN) +/*31*/ GEN_MP_IOCTL_HANDLER(0, oid_rt_pro_trigger_gpio_hdl, 0) + GEN_MP_IOCTL_HANDLER(0, NULL, 0) + GEN_MP_IOCTL_HANDLER(0, NULL, 0) + GEN_MP_IOCTL_HANDLER(0, NULL, 0) +}; + +#else /* _RTW_MP_IOCTL_C_ */ + +extern struct mp_ioctl_handler mp_ioctl_hdl[]; + +#endif /* _RTW_MP_IOCTL_C_ */ + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_mp_phy_regdef.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_mp_phy_regdef.h new file mode 100644 index 000000000..340015cd3 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_mp_phy_regdef.h @@ -0,0 +1,1100 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +/***************************************************************************** + * + * Module: __RTW_MP_PHY_REGDEF_H_ + * + * + * Note: 1. Define PMAC/BB register map + * 2. Define RF register map + * 3. PMAC/BB register bit mask. + * 4. RF reg bit mask. + * 5. Other BB/RF relative definition. + * + * + * Export: Constants, macro, functions(API), global variables(None). + * + * Abbrev: + * + * History: + * Data Who Remark + * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. + * 2. Reorganize code architecture. + * 09/25/2008 MH 1. Add RL6052 register definition + * + *****************************************************************************/ +#ifndef __RTW_MP_PHY_REGDEF_H_ +#define __RTW_MP_PHY_REGDEF_H_ + + +/*--------------------------Define Parameters-------------------------------*/ + +//============================================================ +// 8192S Regsiter offset definition +//============================================================ + +// +// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF +// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF +// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 +// 3. RF register 0x00-2E +// 4. Bit Mask for BB/RF register +// 5. Other defintion for BB/RF R/W +// + + +// +// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF +// 1. Page1(0x100) +// +#define rPMAC_Reset 0x100 +#define rPMAC_TxStart 0x104 +#define rPMAC_TxLegacySIG 0x108 +#define rPMAC_TxHTSIG1 0x10c +#define rPMAC_TxHTSIG2 0x110 +#define rPMAC_PHYDebug 0x114 +#define rPMAC_TxPacketNum 0x118 +#define rPMAC_TxIdle 0x11c +#define rPMAC_TxMACHeader0 0x120 +#define rPMAC_TxMACHeader1 0x124 +#define rPMAC_TxMACHeader2 0x128 +#define rPMAC_TxMACHeader3 0x12c +#define rPMAC_TxMACHeader4 0x130 +#define rPMAC_TxMACHeader5 0x134 +#define rPMAC_TxDataType 0x138 +#define rPMAC_TxRandomSeed 0x13c +#define rPMAC_CCKPLCPPreamble 0x140 +#define rPMAC_CCKPLCPHeader 0x144 +#define rPMAC_CCKCRC16 0x148 +#define rPMAC_OFDMRxCRC32OK 0x170 +#define rPMAC_OFDMRxCRC32Er 0x174 +#define rPMAC_OFDMRxParityEr 0x178 +#define rPMAC_OFDMRxCRC8Er 0x17c +#define rPMAC_CCKCRxRC16Er 0x180 +#define rPMAC_CCKCRxRC32Er 0x184 +#define rPMAC_CCKCRxRC32OK 0x188 +#define rPMAC_TxStatus 0x18c + +// +// 2. Page2(0x200) +// +// The following two definition are only used for USB interface. +//#define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address. +//#define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data. + +// +// 3. Page8(0x800) +// +#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting?? + +#define rFPGA0_TxInfo 0x804 // Status report?? +#define rFPGA0_PSDFunction 0x808 + +#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain? + +#define rFPGA0_RFTiming1 0x810 // Useless now +#define rFPGA0_RFTiming2 0x814 +//#define rFPGA0_XC_RFTiming 0x818 +//#define rFPGA0_XD_RFTiming 0x81c + +#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register +#define rFPGA0_XA_HSSIParameter2 0x824 +#define rFPGA0_XB_HSSIParameter1 0x828 +#define rFPGA0_XB_HSSIParameter2 0x82c +#define rFPGA0_XC_HSSIParameter1 0x830 +#define rFPGA0_XC_HSSIParameter2 0x834 +#define rFPGA0_XD_HSSIParameter1 0x838 +#define rFPGA0_XD_HSSIParameter2 0x83c +#define rFPGA0_XA_LSSIParameter 0x840 +#define rFPGA0_XB_LSSIParameter 0x844 +#define rFPGA0_XC_LSSIParameter 0x848 +#define rFPGA0_XD_LSSIParameter 0x84c + +#define rFPGA0_RFWakeUpParameter 0x850 // Useless now +#define rFPGA0_RFSleepUpParameter 0x854 + +#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch +#define rFPGA0_XCD_SwitchControl 0x85c + +#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch +#define rFPGA0_XB_RFInterfaceOE 0x864 +#define rFPGA0_XC_RFInterfaceOE 0x868 +#define rFPGA0_XD_RFInterfaceOE 0x86c + +#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control +#define rFPGA0_XCD_RFInterfaceSW 0x874 + +#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter +#define rFPGA0_XCD_RFParameter 0x87c + +#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? +#define rFPGA0_AnalogParameter2 0x884 +#define rFPGA0_AnalogParameter3 0x888 // Useless now +#define rFPGA0_AnalogParameter4 0x88c + +#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback +#define rFPGA0_XB_LSSIReadBack 0x8a4 +#define rFPGA0_XC_LSSIReadBack 0x8a8 +#define rFPGA0_XD_LSSIReadBack 0x8ac + +#define rFPGA0_PSDReport 0x8b4 // Useless now +#define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value +#define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now + +// +// 4. Page9(0x900) +// +#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting?? + +#define rFPGA1_TxBlock 0x904 // Useless now +#define rFPGA1_DebugSelect 0x908 // Useless now +#define rFPGA1_TxInfo 0x90c // Useless now // Status report?? +#define rS0S1_PathSwitch 0x948 + +// +// 5. PageA(0xA00) +// +// Set Control channel to upper or lower. These settings are required only for 40MHz +#define rCCK0_System 0xa00 + +#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI +#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain + +#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series +#define rCCK0_RxAGC2 0xa10 //AGC & DAGC + +#define rCCK0_RxHP 0xa14 + +#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold +#define rCCK0_DSPParameter2 0xa1c //SQ threshold + +#define rCCK0_TxFilter1 0xa20 +#define rCCK0_TxFilter2 0xa24 +#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 +#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report +#define rCCK0_TRSSIReport 0xa50 +#define rCCK0_RxReport 0xa54 //0xa57 +#define rCCK0_FACounterLower 0xa5c //0xa5b +#define rCCK0_FACounterUpper 0xa58 //0xa5c + +// +// 6. PageC(0xC00) +// +#define rOFDM0_LSTF 0xc00 + +#define rOFDM0_TRxPathEnable 0xc04 +#define rOFDM0_TRMuxPar 0xc08 +#define rOFDM0_TRSWIsolation 0xc0c + +#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter +#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix +#define rOFDM0_XBRxAFE 0xc18 +#define rOFDM0_XBRxIQImbalance 0xc1c +#define rOFDM0_XCRxAFE 0xc20 +#define rOFDM0_XCRxIQImbalance 0xc24 +#define rOFDM0_XDRxAFE 0xc28 +#define rOFDM0_XDRxIQImbalance 0xc2c + +#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain +#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. +#define rOFDM0_RxDetector3 0xc38 //Frame Sync. +#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI + +#define rOFDM0_RxDSP 0xc40 //Rx Sync Path +#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC +#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold +#define rOFDM0_ECCAThreshold 0xc4c // energy CCA + +#define rOFDM0_XAAGCCore1 0xc50 // DIG +#define rOFDM0_XAAGCCore2 0xc54 +#define rOFDM0_XBAGCCore1 0xc58 +#define rOFDM0_XBAGCCore2 0xc5c +#define rOFDM0_XCAGCCore1 0xc60 +#define rOFDM0_XCAGCCore2 0xc64 +#define rOFDM0_XDAGCCore1 0xc68 +#define rOFDM0_XDAGCCore2 0xc6c + +#define rOFDM0_AGCParameter1 0xc70 +#define rOFDM0_AGCParameter2 0xc74 +#define rOFDM0_AGCRSSITable 0xc78 +#define rOFDM0_HTSTFAGC 0xc7c + +#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG +#define rOFDM0_XATxAFE 0xc84 +#define rOFDM0_XBTxIQImbalance 0xc88 +#define rOFDM0_XBTxAFE 0xc8c +#define rOFDM0_XCTxIQImbalance 0xc90 +#define rOFDM0_XCTxAFE 0xc94 +#define rOFDM0_XDTxIQImbalance 0xc98 +#define rOFDM0_XDTxAFE 0xc9c +#define rOFDM0_RxIQExtAnta 0xca0 + +#define rOFDM0_RxHPParameter 0xce0 +#define rOFDM0_TxPseudoNoiseWgt 0xce4 +#define rOFDM0_FrameSync 0xcf0 +#define rOFDM0_DFSReport 0xcf4 +#define rOFDM0_TxCoeff1 0xca4 +#define rOFDM0_TxCoeff2 0xca8 +#define rOFDM0_TxCoeff3 0xcac +#define rOFDM0_TxCoeff4 0xcb0 +#define rOFDM0_TxCoeff5 0xcb4 +#define rOFDM0_TxCoeff6 0xcb8 + + +// +// 7. PageD(0xD00) +// +#define rOFDM1_LSTF 0xd00 +#define rOFDM1_TRxPathEnable 0xd04 + +#define rOFDM1_CFO 0xd08 // No setting now +#define rOFDM1_CSI1 0xd10 +#define rOFDM1_SBD 0xd14 +#define rOFDM1_CSI2 0xd18 +#define rOFDM1_CFOTracking 0xd2c +#define rOFDM1_TRxMesaure1 0xd34 +#define rOFDM1_IntfDet 0xd3c +#define rOFDM1_PseudoNoiseStateAB 0xd50 +#define rOFDM1_PseudoNoiseStateCD 0xd54 +#define rOFDM1_RxPseudoNoiseWgt 0xd58 + +#define rOFDM_PHYCounter1 0xda0 //cca, parity fail +#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail +#define rOFDM_PHYCounter3 0xda8 //MCS not support + +#define rOFDM_ShortCFOAB 0xdac // No setting now +#define rOFDM_ShortCFOCD 0xdb0 +#define rOFDM_LongCFOAB 0xdb4 +#define rOFDM_LongCFOCD 0xdb8 +#define rOFDM_TailCFOAB 0xdbc +#define rOFDM_TailCFOCD 0xdc0 +#define rOFDM_PWMeasure1 0xdc4 +#define rOFDM_PWMeasure2 0xdc8 +#define rOFDM_BWReport 0xdcc +#define rOFDM_AGCReport 0xdd0 +#define rOFDM_RxSNR 0xdd4 +#define rOFDM_RxEVMCSI 0xdd8 +#define rOFDM_SIGReport 0xddc + + +// +// 8. PageE(0xE00) +// +#define rTxAGC_Rate18_06 0xe00 +#define rTxAGC_Rate54_24 0xe04 +#define rTxAGC_CCK_Mcs32 0xe08 +#define rTxAGC_Mcs03_Mcs00 0xe10 +#define rTxAGC_Mcs07_Mcs04 0xe14 +#define rTxAGC_Mcs11_Mcs08 0xe18 +#define rTxAGC_Mcs15_Mcs12 0xe1c + +// Analog- control in RX_WAIT_CCA : REG: EE0 [Analog- Power & Control Register] +#define rRx_Wait_CCCA 0xe70 +#define rAnapar_Ctrl_BB 0xee0 + +// +// 7. RF Register 0x00-0x2E (RF 8256) +// RF-0222D 0x00-3F +// +//Zebra1 +#define RTL92SE_FPGA_VERIFY 0 +#define rZebra1_HSSIEnable 0x0 // Useless now +#define rZebra1_TRxEnable1 0x1 +#define rZebra1_TRxEnable2 0x2 +#define rZebra1_AGC 0x4 +#define rZebra1_ChargePump 0x5 +//#if (RTL92SE_FPGA_VERIFY == 1) +#define rZebra1_Channel 0x7 // RF channel switch +//#else + +//#endif +#define rZebra1_TxGain 0x8 // Useless now +#define rZebra1_TxLPF 0x9 +#define rZebra1_RxLPF 0xb +#define rZebra1_RxHPFCorner 0xc + +//Zebra4 +#define rGlobalCtrl 0 // Useless now +#define rRTL8256_TxLPF 19 +#define rRTL8256_RxLPF 11 + +//RTL8258 +#define rRTL8258_TxLPF 0x11 // Useless now +#define rRTL8258_RxLPF 0x13 +#define rRTL8258_RSSILPF 0xa + +// +// RL6052 Register definition +// +#define RF_AC 0x00 // + +#define RF_IQADJ_G1 0x01 // +#define RF_IQADJ_G2 0x02 // +#define RF_POW_TRSW 0x05 // + +#define RF_GAIN_RX 0x06 // +#define RF_GAIN_TX 0x07 // + +#define RF_TXM_IDAC 0x08 // +#define RF_BS_IQGEN 0x0F // + +#define RF_MODE1 0x10 // +#define RF_MODE2 0x11 // + +#define RF_RX_AGC_HP 0x12 // +#define RF_TX_AGC 0x13 // +#define RF_BIAS 0x14 // +#define RF_IPA 0x15 // +#define RF_TXBIAS 0x16 // +#define RF_POW_ABILITY 0x17 // +#define RF_MODE_AG 0x18 // +#define rRfChannel 0x18 // RF channel and BW switch +#define RF_CHNLBW 0x18 // RF channel and BW switch +#define RF_TOP 0x19 // + +#define RF_RX_G1 0x1A // +#define RF_RX_G2 0x1B // + +#define RF_RX_BB2 0x1C // +#define RF_RX_BB1 0x1D // + +#define RF_RCK1 0x1E // +#define RF_RCK2 0x1F // + +#define RF_TX_G1 0x20 // +#define RF_TX_G2 0x21 // +#define RF_TX_G3 0x22 // + +#define RF_TX_BB1 0x23 // + +#define RF_T_METER 0x24 // + +#define RF_SYN_G1 0x25 // RF TX Power control +#define RF_SYN_G2 0x26 // RF TX Power control +#define RF_SYN_G3 0x27 // RF TX Power control +#define RF_SYN_G4 0x28 // RF TX Power control +#define RF_SYN_G5 0x29 // RF TX Power control +#define RF_SYN_G6 0x2A // RF TX Power control +#define RF_SYN_G7 0x2B // RF TX Power control +#define RF_SYN_G8 0x2C // RF TX Power control + +#define RF_RCK_OS 0x30 // RF TX PA control + +#define RF_TXPA_G1 0x31 // RF TX PA control +#define RF_TXPA_G2 0x32 // RF TX PA control +#define RF_TXPA_G3 0x33 // RF TX PA control + +// +//Bit Mask +// +// 1. Page1(0x100) +#define bBBResetB 0x100 // Useless now? +#define bGlobalResetB 0x200 +#define bOFDMTxStart 0x4 +#define bCCKTxStart 0x8 +#define bCRC32Debug 0x100 +#define bPMACLoopback 0x10 +#define bTxLSIG 0xffffff +#define bOFDMTxRate 0xf +#define bOFDMTxReserved 0x10 +#define bOFDMTxLength 0x1ffe0 +#define bOFDMTxParity 0x20000 +#define bTxHTSIG1 0xffffff +#define bTxHTMCSRate 0x7f +#define bTxHTBW 0x80 +#define bTxHTLength 0xffff00 +#define bTxHTSIG2 0xffffff +#define bTxHTSmoothing 0x1 +#define bTxHTSounding 0x2 +#define bTxHTReserved 0x4 +#define bTxHTAggreation 0x8 +#define bTxHTSTBC 0x30 +#define bTxHTAdvanceCoding 0x40 +#define bTxHTShortGI 0x80 +#define bTxHTNumberHT_LTF 0x300 +#define bTxHTCRC8 0x3fc00 +#define bCounterReset 0x10000 +#define bNumOfOFDMTx 0xffff +#define bNumOfCCKTx 0xffff0000 +#define bTxIdleInterval 0xffff +#define bOFDMService 0xffff0000 +#define bTxMACHeader 0xffffffff +#define bTxDataInit 0xff +#define bTxHTMode 0x100 +#define bTxDataType 0x30000 +#define bTxRandomSeed 0xffffffff +#define bCCKTxPreamble 0x1 +#define bCCKTxSFD 0xffff0000 +#define bCCKTxSIG 0xff +#define bCCKTxService 0xff00 +#define bCCKLengthExt 0x8000 +#define bCCKTxLength 0xffff0000 +#define bCCKTxCRC16 0xffff +#define bCCKTxStatus 0x1 +#define bOFDMTxStatus 0x2 + +#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) + +// 2. Page8(0x800) +#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD +#define bJapanMode 0x2 +#define bCCKTxSC 0x30 +#define bCCKEn 0x1000000 +#define bOFDMEn 0x2000000 + +#define bOFDMRxADCPhase 0x10000 // Useless now +#define bOFDMTxDACPhase 0x40000 +#define bXATxAGC 0x3f + +#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage +#define bXCTxAGC 0xf000 +#define bXDTxAGC 0xf0000 + +#define bPAStart 0xf0000000 // Useless now +#define bTRStart 0x00f00000 +#define bRFStart 0x0000f000 +#define bBBStart 0x000000f0 +#define bBBCCKStart 0x0000000f +#define bPAEnd 0xf //Reg0x814 +#define bTREnd 0x0f000000 +#define bRFEnd 0x000f0000 +#define bCCAMask 0x000000f0 //T2R +#define bR2RCCAMask 0x00000f00 +#define bHSSI_R2TDelay 0xf8000000 +#define bHSSI_T2RDelay 0xf80000 +#define bContTxHSSI 0x400 //chane gain at continue Tx +#define bIGFromCCK 0x200 +#define bAGCAddress 0x3f +#define bRxHPTx 0x7000 +#define bRxHPT2R 0x38000 +#define bRxHPCCKIni 0xc0000 +#define bAGCTxCode 0xc00000 +#define bAGCRxCode 0x300000 + +#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 +#define b3WireAddressLength 0x400 + +#define b3WireRFPowerDown 0x1 // Useless now +//#define bHWSISelect 0x8 +#define b5GPAPEPolarity 0x40000000 +#define b2GPAPEPolarity 0x80000000 +#define bRFSW_TxDefaultAnt 0x3 +#define bRFSW_TxOptionAnt 0x30 +#define bRFSW_RxDefaultAnt 0x300 +#define bRFSW_RxOptionAnt 0x3000 +#define bRFSI_3WireData 0x1 +#define bRFSI_3WireClock 0x2 +#define bRFSI_3WireLoad 0x4 +#define bRFSI_3WireRW 0x8 +#define bRFSI_3Wire 0xf + +#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW + +#define bRFSI_TRSW 0x20 // Useless now +#define bRFSI_TRSWB 0x40 +#define bRFSI_ANTSW 0x100 +#define bRFSI_ANTSWB 0x200 +#define bRFSI_PAPE 0x400 +#define bRFSI_PAPE5G 0x800 +#define bBandSelect 0x1 +#define bHTSIG2_GI 0x80 +#define bHTSIG2_Smoothing 0x01 +#define bHTSIG2_Sounding 0x02 +#define bHTSIG2_Aggreaton 0x08 +#define bHTSIG2_STBC 0x30 +#define bHTSIG2_AdvCoding 0x40 +#define bHTSIG2_NumOfHTLTF 0x300 +#define bHTSIG2_CRC8 0x3fc +#define bHTSIG1_MCS 0x7f +#define bHTSIG1_BandWidth 0x80 +#define bHTSIG1_HTLength 0xffff +#define bLSIG_Rate 0xf +#define bLSIG_Reserved 0x10 +#define bLSIG_Length 0x1fffe +#define bLSIG_Parity 0x20 +#define bCCKRxPhase 0x4 +#if (RTL92SE_FPGA_VERIFY == 1) +#define bLSSIReadAddress 0x3f000000 //LSSI "Read" Address // Reg 0x824 rFPGA0_XA_HSSIParameter2 +#else +#define bLSSIReadAddress 0x7f800000 // T65 RF +#endif +#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal +#if (RTL92SE_FPGA_VERIFY == 1) +#define bLSSIReadBackData 0xfff // Reg 0x8a0 rFPGA0_XA_LSSIReadBack +#else +#define bLSSIReadBackData 0xfffff // T65 RF +#endif +#define bLSSIReadOKFlag 0x1000 // Useless now +#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz +#define bRegulator0Standby 0x1 +#define bRegulatorPLLStandby 0x2 +#define bRegulator1Standby 0x4 +#define bPLLPowerUp 0x8 +#define bDPLLPowerUp 0x10 +#define bDA10PowerUp 0x20 +#define bAD7PowerUp 0x200 +#define bDA6PowerUp 0x2000 +#define bXtalPowerUp 0x4000 +#define b40MDClkPowerUP 0x8000 +#define bDA6DebugMode 0x20000 +#define bDA6Swing 0x380000 + +#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ + +#define b80MClkDelay 0x18000000 // Useless +#define bAFEWatchDogEnable 0x20000000 + +#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap +#define bXtalCap23 0x3 +#define bXtalCap92x 0x0f000000 +#define bXtalCap 0x0f000000 + +#define bIntDifClkEnable 0x400 // Useless +#define bExtSigClkEnable 0x800 +#define bBandgapMbiasPowerUp 0x10000 +#define bAD11SHGain 0xc0000 +#define bAD11InputRange 0x700000 +#define bAD11OPCurrent 0x3800000 +#define bIPathLoopback 0x4000000 +#define bQPathLoopback 0x8000000 +#define bAFELoopback 0x10000000 +#define bDA10Swing 0x7e0 +#define bDA10Reverse 0x800 +#define bDAClkSource 0x1000 +#define bAD7InputRange 0x6000 +#define bAD7Gain 0x38000 +#define bAD7OutputCMMode 0x40000 +#define bAD7InputCMMode 0x380000 +#define bAD7Current 0xc00000 +#define bRegulatorAdjust 0x7000000 +#define bAD11PowerUpAtTx 0x1 +#define bDA10PSAtTx 0x10 +#define bAD11PowerUpAtRx 0x100 +#define bDA10PSAtRx 0x1000 +#define bCCKRxAGCFormat 0x200 +#define bPSDFFTSamplepPoint 0xc000 +#define bPSDAverageNum 0x3000 +#define bIQPathControl 0xc00 +#define bPSDFreq 0x3ff +#define bPSDAntennaPath 0x30 +#define bPSDIQSwitch 0x40 +#define bPSDRxTrigger 0x400000 +#define bPSDTxTrigger 0x80000000 +#define bPSDSineToneScale 0x7f000000 +#define bPSDReport 0xffff + +// 3. Page9(0x900) +#define bOFDMTxSC 0x30000000 // Useless +#define bCCKTxOn 0x1 +#define bOFDMTxOn 0x2 +#define bDebugPage 0xfff //reset debug page and also HWord, LWord +#define bDebugItem 0xff //reset debug page and LWord +#define bAntL 0x10 +#define bAntNonHT 0x100 +#define bAntHT1 0x1000 +#define bAntHT2 0x10000 +#define bAntHT1S1 0x100000 +#define bAntNonHTS1 0x1000000 + +// 4. PageA(0xA00) +#define bCCKBBMode 0x3 // Useless +#define bCCKTxPowerSaving 0x80 +#define bCCKRxPowerSaving 0x40 + +#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch + +#define bCCKScramble 0x8 // Useless +#define bCCKAntDiversity 0x8000 +#define bCCKCarrierRecovery 0x4000 +#define bCCKTxRate 0x3000 +#define bCCKDCCancel 0x0800 +#define bCCKISICancel 0x0400 +#define bCCKMatchFilter 0x0200 +#define bCCKEqualizer 0x0100 +#define bCCKPreambleDetect 0x800000 +#define bCCKFastFalseCCA 0x400000 +#define bCCKChEstStart 0x300000 +#define bCCKCCACount 0x080000 +#define bCCKcs_lim 0x070000 +#define bCCKBistMode 0x80000000 +#define bCCKCCAMask 0x40000000 +#define bCCKTxDACPhase 0x4 +#define bCCKRxADCPhase 0x20000000 //r_rx_clk +#define bCCKr_cp_mode0 0x0100 +#define bCCKTxDCOffset 0xf0 +#define bCCKRxDCOffset 0xf +#define bCCKCCAMode 0xc000 +#define bCCKFalseCS_lim 0x3f00 +#define bCCKCS_ratio 0xc00000 +#define bCCKCorgBit_sel 0x300000 +#define bCCKPD_lim 0x0f0000 +#define bCCKNewCCA 0x80000000 +#define bCCKRxHPofIG 0x8000 +#define bCCKRxIG 0x7f00 +#define bCCKLNAPolarity 0x800000 +#define bCCKRx1stGain 0x7f0000 +#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity +#define bCCKRxAGCSatLevel 0x1f000000 +#define bCCKRxAGCSatCount 0xe0 +#define bCCKRxRFSettle 0x1f //AGCsamp_dly +#define bCCKFixedRxAGC 0x8000 +//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 +#define bCCKAntennaPolarity 0x2000 +#define bCCKTxFilterType 0x0c00 +#define bCCKRxAGCReportType 0x0300 +#define bCCKRxDAGCEn 0x80000000 +#define bCCKRxDAGCPeriod 0x20000000 +#define bCCKRxDAGCSatLevel 0x1f000000 +#define bCCKTimingRecovery 0x800000 +#define bCCKTxC0 0x3f0000 +#define bCCKTxC1 0x3f000000 +#define bCCKTxC2 0x3f +#define bCCKTxC3 0x3f00 +#define bCCKTxC4 0x3f0000 +#define bCCKTxC5 0x3f000000 +#define bCCKTxC6 0x3f +#define bCCKTxC7 0x3f00 +#define bCCKDebugPort 0xff0000 +#define bCCKDACDebug 0x0f000000 +#define bCCKFalseAlarmEnable 0x8000 +#define bCCKFalseAlarmRead 0x4000 +#define bCCKTRSSI 0x7f +#define bCCKRxAGCReport 0xfe +#define bCCKRxReport_AntSel 0x80000000 +#define bCCKRxReport_MFOff 0x40000000 +#define bCCKRxRxReport_SQLoss 0x20000000 +#define bCCKRxReport_Pktloss 0x10000000 +#define bCCKRxReport_Lockedbit 0x08000000 +#define bCCKRxReport_RateError 0x04000000 +#define bCCKRxReport_RxRate 0x03000000 +#define bCCKRxFACounterLower 0xff +#define bCCKRxFACounterUpper 0xff000000 +#define bCCKRxHPAGCStart 0xe000 +#define bCCKRxHPAGCFinal 0x1c00 +#define bCCKRxFalseAlarmEnable 0x8000 +#define bCCKFACounterFreeze 0x4000 +#define bCCKTxPathSel 0x10000000 +#define bCCKDefaultRxPath 0xc000000 +#define bCCKOptionRxPath 0x3000000 + +// 5. PageC(0xC00) +#define bNumOfSTF 0x3 // Useless +#define bShift_L 0xc0 +#define bGI_TH 0xc +#define bRxPathA 0x1 +#define bRxPathB 0x2 +#define bRxPathC 0x4 +#define bRxPathD 0x8 +#define bTxPathA 0x1 +#define bTxPathB 0x2 +#define bTxPathC 0x4 +#define bTxPathD 0x8 +#define bTRSSIFreq 0x200 +#define bADCBackoff 0x3000 +#define bDFIRBackoff 0xc000 +#define bTRSSILatchPhase 0x10000 +#define bRxIDCOffset 0xff +#define bRxQDCOffset 0xff00 +#define bRxDFIRMode 0x1800000 +#define bRxDCNFType 0xe000000 +#define bRXIQImb_A 0x3ff +#define bRXIQImb_B 0xfc00 +#define bRXIQImb_C 0x3f0000 +#define bRXIQImb_D 0xffc00000 +#define bDC_dc_Notch 0x60000 +#define bRxNBINotch 0x1f000000 +#define bPD_TH 0xf +#define bPD_TH_Opt2 0xc000 +#define bPWED_TH 0x700 +#define bIfMF_Win_L 0x800 +#define bPD_Option 0x1000 +#define bMF_Win_L 0xe000 +#define bBW_Search_L 0x30000 +#define bwin_enh_L 0xc0000 +#define bBW_TH 0x700000 +#define bED_TH2 0x3800000 +#define bBW_option 0x4000000 +#define bRatio_TH 0x18000000 +#define bWindow_L 0xe0000000 +#define bSBD_Option 0x1 +#define bFrame_TH 0x1c +#define bFS_Option 0x60 +#define bDC_Slope_check 0x80 +#define bFGuard_Counter_DC_L 0xe00 +#define bFrame_Weight_Short 0x7000 +#define bSub_Tune 0xe00000 +#define bFrame_DC_Length 0xe000000 +#define bSBD_start_offset 0x30000000 +#define bFrame_TH_2 0x7 +#define bFrame_GI2_TH 0x38 +#define bGI2_Sync_en 0x40 +#define bSarch_Short_Early 0x300 +#define bSarch_Short_Late 0xc00 +#define bSarch_GI2_Late 0x70000 +#define bCFOAntSum 0x1 +#define bCFOAcc 0x2 +#define bCFOStartOffset 0xc +#define bCFOLookBack 0x70 +#define bCFOSumWeight 0x80 +#define bDAGCEnable 0x10000 +#define bTXIQImb_A 0x3ff +#define bTXIQImb_B 0xfc00 +#define bTXIQImb_C 0x3f0000 +#define bTXIQImb_D 0xffc00000 +#define bTxIDCOffset 0xff +#define bTxQDCOffset 0xff00 +#define bTxDFIRMode 0x10000 +#define bTxPesudoNoiseOn 0x4000000 +#define bTxPesudoNoise_A 0xff +#define bTxPesudoNoise_B 0xff00 +#define bTxPesudoNoise_C 0xff0000 +#define bTxPesudoNoise_D 0xff000000 +#define bCCADropOption 0x20000 +#define bCCADropThres 0xfff00000 +#define bEDCCA_H 0xf +#define bEDCCA_L 0xf0 +#define bLambda_ED 0x300 +#define bRxInitialGain 0x7f +#define bRxAntDivEn 0x80 +#define bRxAGCAddressForLNA 0x7f00 +#define bRxHighPowerFlow 0x8000 +#define bRxAGCFreezeThres 0xc0000 +#define bRxFreezeStep_AGC1 0x300000 +#define bRxFreezeStep_AGC2 0xc00000 +#define bRxFreezeStep_AGC3 0x3000000 +#define bRxFreezeStep_AGC0 0xc000000 +#define bRxRssi_Cmp_En 0x10000000 +#define bRxQuickAGCEn 0x20000000 +#define bRxAGCFreezeThresMode 0x40000000 +#define bRxOverFlowCheckType 0x80000000 +#define bRxAGCShift 0x7f +#define bTRSW_Tri_Only 0x80 +#define bPowerThres 0x300 +#define bRxAGCEn 0x1 +#define bRxAGCTogetherEn 0x2 +#define bRxAGCMin 0x4 +#define bRxHP_Ini 0x7 +#define bRxHP_TRLNA 0x70 +#define bRxHP_RSSI 0x700 +#define bRxHP_BBP1 0x7000 +#define bRxHP_BBP2 0x70000 +#define bRxHP_BBP3 0x700000 +#define bRSSI_H 0x7f0000 //the threshold for high power +#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity +#define bRxSettle_TRSW 0x7 +#define bRxSettle_LNA 0x38 +#define bRxSettle_RSSI 0x1c0 +#define bRxSettle_BBP 0xe00 +#define bRxSettle_RxHP 0x7000 +#define bRxSettle_AntSW_RSSI 0x38000 +#define bRxSettle_AntSW 0xc0000 +#define bRxProcessTime_DAGC 0x300000 +#define bRxSettle_HSSI 0x400000 +#define bRxProcessTime_BBPPW 0x800000 +#define bRxAntennaPowerShift 0x3000000 +#define bRSSITableSelect 0xc000000 +#define bRxHP_Final 0x7000000 +#define bRxHTSettle_BBP 0x7 +#define bRxHTSettle_HSSI 0x8 +#define bRxHTSettle_RxHP 0x70 +#define bRxHTSettle_BBPPW 0x80 +#define bRxHTSettle_Idle 0x300 +#define bRxHTSettle_Reserved 0x1c00 +#define bRxHTRxHPEn 0x8000 +#define bRxHTAGCFreezeThres 0x30000 +#define bRxHTAGCTogetherEn 0x40000 +#define bRxHTAGCMin 0x80000 +#define bRxHTAGCEn 0x100000 +#define bRxHTDAGCEn 0x200000 +#define bRxHTRxHP_BBP 0x1c00000 +#define bRxHTRxHP_Final 0xe0000000 +#define bRxPWRatioTH 0x3 +#define bRxPWRatioEn 0x4 +#define bRxMFHold 0x3800 +#define bRxPD_Delay_TH1 0x38 +#define bRxPD_Delay_TH2 0x1c0 +#define bRxPD_DC_COUNT_MAX 0x600 +//#define bRxMF_Hold 0x3800 +#define bRxPD_Delay_TH 0x8000 +#define bRxProcess_Delay 0xf0000 +#define bRxSearchrange_GI2_Early 0x700000 +#define bRxFrame_Guard_Counter_L 0x3800000 +#define bRxSGI_Guard_L 0xc000000 +#define bRxSGI_Search_L 0x30000000 +#define bRxSGI_TH 0xc0000000 +#define bDFSCnt0 0xff +#define bDFSCnt1 0xff00 +#define bDFSFlag 0xf0000 +#define bMFWeightSum 0x300000 +#define bMinIdxTH 0x7f000000 +#define bDAFormat 0x40000 +#define bTxChEmuEnable 0x01000000 +#define bTRSWIsolation_A 0x7f +#define bTRSWIsolation_B 0x7f00 +#define bTRSWIsolation_C 0x7f0000 +#define bTRSWIsolation_D 0x7f000000 +#define bExtLNAGain 0x7c00 + +// 6. PageE(0xE00) +#define bSTBCEn 0x4 // Useless +#define bAntennaMapping 0x10 +#define bNss 0x20 +#define bCFOAntSumD 0x200 +#define bPHYCounterReset 0x8000000 +#define bCFOReportGet 0x4000000 +#define bOFDMContinueTx 0x10000000 +#define bOFDMSingleCarrier 0x20000000 +#define bOFDMSingleTone 0x40000000 +//#define bRxPath1 0x01 +//#define bRxPath2 0x02 +//#define bRxPath3 0x04 +//#define bRxPath4 0x08 +//#define bTxPath1 0x10 +//#define bTxPath2 0x20 +#define bHTDetect 0x100 +#define bCFOEn 0x10000 +#define bCFOValue 0xfff00000 +#define bSigTone_Re 0x3f +#define bSigTone_Im 0x7f00 +#define bCounter_CCA 0xffff +#define bCounter_ParityFail 0xffff0000 +#define bCounter_RateIllegal 0xffff +#define bCounter_CRC8Fail 0xffff0000 +#define bCounter_MCSNoSupport 0xffff +#define bCounter_FastSync 0xffff +#define bShortCFO 0xfff +#define bShortCFOTLength 12 //total +#define bShortCFOFLength 11 //fraction +#define bLongCFO 0x7ff +#define bLongCFOTLength 11 +#define bLongCFOFLength 11 +#define bTailCFO 0x1fff +#define bTailCFOTLength 13 +#define bTailCFOFLength 12 +#define bmax_en_pwdB 0xffff +#define bCC_power_dB 0xffff0000 +#define bnoise_pwdB 0xffff +#define bPowerMeasTLength 10 +#define bPowerMeasFLength 3 +#define bRx_HT_BW 0x1 +#define bRxSC 0x6 +#define bRx_HT 0x8 +#define bNB_intf_det_on 0x1 +#define bIntf_win_len_cfg 0x30 +#define bNB_Intf_TH_cfg 0x1c0 +#define bRFGain 0x3f +#define bTableSel 0x40 +#define bTRSW 0x80 +#define bRxSNR_A 0xff +#define bRxSNR_B 0xff00 +#define bRxSNR_C 0xff0000 +#define bRxSNR_D 0xff000000 +#define bSNREVMTLength 8 +#define bSNREVMFLength 1 +#define bCSI1st 0xff +#define bCSI2nd 0xff00 +#define bRxEVM1st 0xff0000 +#define bRxEVM2nd 0xff000000 +#define bSIGEVM 0xff +#define bPWDB 0xff00 +#define bSGIEN 0x10000 + +#define bSFactorQAM1 0xf // Useless +#define bSFactorQAM2 0xf0 +#define bSFactorQAM3 0xf00 +#define bSFactorQAM4 0xf000 +#define bSFactorQAM5 0xf0000 +#define bSFactorQAM6 0xf0000 +#define bSFactorQAM7 0xf00000 +#define bSFactorQAM8 0xf000000 +#define bSFactorQAM9 0xf0000000 +#define bCSIScheme 0x100000 + +#define bNoiseLvlTopSet 0x3 // Useless +#define bChSmooth 0x4 +#define bChSmoothCfg1 0x38 +#define bChSmoothCfg2 0x1c0 +#define bChSmoothCfg3 0xe00 +#define bChSmoothCfg4 0x7000 +#define bMRCMode 0x800000 +#define bTHEVMCfg 0x7000000 + +#define bLoopFitType 0x1 // Useless +#define bUpdCFO 0x40 +#define bUpdCFOOffData 0x80 +#define bAdvUpdCFO 0x100 +#define bAdvTimeCtrl 0x800 +#define bUpdClko 0x1000 +#define bFC 0x6000 +#define bTrackingMode 0x8000 +#define bPhCmpEnable 0x10000 +#define bUpdClkoLTF 0x20000 +#define bComChCFO 0x40000 +#define bCSIEstiMode 0x80000 +#define bAdvUpdEqz 0x100000 +#define bUChCfg 0x7000000 +#define bUpdEqz 0x8000000 + +#define bTxAGCRate18_06 0x7f7f7f7f // Useless +#define bTxAGCRate54_24 0x7f7f7f7f +#define bTxAGCRateMCS32 0x7f +#define bTxAGCRateCCK 0x7f00 +#define bTxAGCRateMCS3_MCS0 0x7f7f7f7f +#define bTxAGCRateMCS7_MCS4 0x7f7f7f7f +#define bTxAGCRateMCS11_MCS8 0x7f7f7f7f +#define bTxAGCRateMCS15_MCS12 0x7f7f7f7f + +//Rx Pseduo noise +#define bRxPesudoNoiseOn 0x20000000 // Useless +#define bRxPesudoNoise_A 0xff +#define bRxPesudoNoise_B 0xff00 +#define bRxPesudoNoise_C 0xff0000 +#define bRxPesudoNoise_D 0xff000000 +#define bPesudoNoiseState_A 0xffff +#define bPesudoNoiseState_B 0xffff0000 +#define bPesudoNoiseState_C 0xffff +#define bPesudoNoiseState_D 0xffff0000 + +//7. RF Register +//Zebra1 +#define bZebra1_HSSIEnable 0x8 // Useless +#define bZebra1_TRxControl 0xc00 +#define bZebra1_TRxGainSetting 0x07f +#define bZebra1_RxCorner 0xc00 +#define bZebra1_TxChargePump 0x38 +#define bZebra1_RxChargePump 0x7 +#define bZebra1_ChannelNum 0xf80 +#define bZebra1_TxLPFBW 0x400 +#define bZebra1_RxLPFBW 0x600 + +//Zebra4 +#define bRTL8256RegModeCtrl1 0x100 // Useless +#define bRTL8256RegModeCtrl0 0x40 +#define bRTL8256_TxLPFBW 0x18 +#define bRTL8256_RxLPFBW 0x600 + +//RTL8258 +#define bRTL8258_TxLPFBW 0xc // Useless +#define bRTL8258_RxLPFBW 0xc00 +#define bRTL8258_RSSILPFBW 0xc0 + + +// +// Other Definition +// + +//byte endable for sb_write +#define bByte0 0x1 // Useless +#define bByte1 0x2 +#define bByte2 0x4 +#define bByte3 0x8 +#define bWord0 0x3 +#define bWord1 0xc +#define bDWord 0xf + +//for PutRegsetting & GetRegSetting BitMask +#define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f +#define bMaskByte1 0xff00 +#define bMaskByte2 0xff0000 +#define bMaskByte3 0xff000000 +#define bMaskHWord 0xffff0000 +#define bMaskLWord 0x0000ffff +#define bMaskDWord 0xffffffff +#define bMaskH4Bits 0xf0000000 +#define bMaskH3Bytes 0xffffff00 +#define bMaskOFDM_D 0xffc00000 +#define bMaskCCK 0x3f3f3f3f +#define bMask12Bits 0xfff + +//for PutRFRegsetting & GetRFRegSetting BitMask +#if (RTL92SE_FPGA_VERIFY == 1) +//#define bMask12Bits 0xfff // RF Reg mask bits +//#define bMask20Bits 0xfff // RF Reg mask bits T65 RF +#define bRFRegOffsetMask 0xfff +#else +//#define bMask12Bits 0xfffff // RF Reg mask bits +//#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF +#define bRFRegOffsetMask 0xfffff +#endif +#define bEnable 0x1 // Useless +#define bDisable 0x0 + +#define LeftAntenna 0x0 // Useless +#define RightAntenna 0x1 + +#define tCheckTxStatus 500 //500ms // Useless +#define tUpdateRxCounter 100 //100ms + +#define rateCCK 0 // Useless +#define rateOFDM 1 +#define rateHT 2 + +//define Register-End +#define bPMAC_End 0x1ff // Useless +#define bFPGAPHY0_End 0x8ff +#define bFPGAPHY1_End 0x9ff +#define bCCKPHY0_End 0xaff +#define bOFDMPHY0_End 0xcff +#define bOFDMPHY1_End 0xdff + +//define max debug item in each debug page +//#define bMaxItem_FPGA_PHY0 0x9 +//#define bMaxItem_FPGA_PHY1 0x3 +//#define bMaxItem_PHY_11B 0x16 +//#define bMaxItem_OFDM_PHY0 0x29 +//#define bMaxItem_OFDM_PHY1 0x0 + +#define bPMACControl 0x0 // Useless +#define bWMACControl 0x1 +#define bWNICControl 0x2 + +#if 0 +#define ANTENNA_A 0x1 // Useless +#define ANTENNA_B 0x2 +#define ANTENNA_AB 0x3 // ANTENNA_A|ANTENNA_B + +#define ANTENNA_C 0x4 +#define ANTENNA_D 0x8 +#endif + +#define RCR_AAP BIT(0) // accept all physical address +#define RCR_APM BIT(1) // accept physical match +#define RCR_AM BIT(2) // accept multicast +#define RCR_AB BIT(3) // accept broadcast +#define RCR_ACRC32 BIT(5) // accept error packet +#define RCR_9356SEL BIT(6) +#define RCR_AICV BIT(9) // Accept ICV error packet +#define RCR_RXFTH0 (BIT(13)|BIT(14)|BIT(15)) // Rx FIFO threshold +#define RCR_ADF BIT(18) // Accept Data(frame type) frame +#define RCR_ACF BIT(19) // Accept control frame +#define RCR_AMF BIT(20) // Accept management frame +#define RCR_ADD3 BIT(21) +#define RCR_APWRMGT BIT(22) // Accept power management packet +#define RCR_CBSSID BIT(23) // Accept BSSID match packet +#define RCR_ENMARP BIT(28) // enable mac auto reset phy +#define RCR_EnCS1 BIT(29) // enable carrier sense method 1 +#define RCR_EnCS2 BIT(30) // enable carrier sense method 2 +#define RCR_OnlyErlPkt BIT(31) // Rx Early mode is performed for packet size greater than 1536 + +/*--------------------------Define Parameters-------------------------------*/ + + +#endif //__INC_HAL8192SPHYREG_H + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_odm.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_odm.h new file mode 100644 index 000000000..8375fe14a --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_odm.h @@ -0,0 +1,55 @@ +/****************************************************************************** + * + * Copyright(c) 2013 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_ODM_H__ +#define __RTW_ODM_H__ + +#include +#include "../hal/phydm/phydm_types.h" +/* +* This file provides utilities/wrappers for rtw driver to use ODM +*/ + +void rtw_odm_dbg_comp_msg(void *sel,_adapter *adapter); +void rtw_odm_dbg_comp_set(_adapter *adapter, u64 comps); +void rtw_odm_dbg_level_msg(void *sel,_adapter *adapter); +void rtw_odm_dbg_level_set(_adapter *adapter, u32 level); + +void rtw_odm_ability_msg(void *sel, _adapter *adapter); +void rtw_odm_ability_set(_adapter *adapter, u32 ability); + +void rtw_odm_init_ic_type(_adapter *adapter); + +void rtw_odm_adaptivity_config_msg(void *sel, _adapter *adapter); + +bool rtw_odm_adaptivity_needed(_adapter *adapter); +void rtw_odm_adaptivity_parm_msg(void *sel,_adapter *adapter); +void rtw_odm_adaptivity_parm_set(_adapter *adapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff, s8 TH_L2H_ini_mode2, s8 TH_EDCCA_HL_diff_mode2, u8 EDCCA_enable); +void rtw_odm_get_perpkt_rssi(void *sel, _adapter *adapter); +void rtw_odm_acquirespinlock(_adapter *adapter, RT_SPINLOCK_TYPE type); +void rtw_odm_releasespinlock(_adapter *adapter, RT_SPINLOCK_TYPE type); + +#ifdef CONFIG_DFS_MASTER +VOID rtw_odm_radar_detect_reset(_adapter *adapter); +VOID rtw_odm_radar_detect_disable(_adapter *adapter); +VOID rtw_odm_radar_detect_enable(_adapter *adapter); +BOOLEAN rtw_odm_radar_detect(_adapter *adapter); +#endif /* CONFIG_DFS_MASTER */ +#endif // __RTW_ODM_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_p2p.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_p2p.h new file mode 100644 index 000000000..ab3f4c87d --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_p2p.h @@ -0,0 +1,179 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_P2P_H_ +#define __RTW_P2P_H_ + + +u32 build_beacon_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_probe_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_prov_disc_request_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8* pssid, u8 ussidlen, u8* pdev_raddr ); +u32 build_assoc_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 status_code); +u32 build_deauth_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +#ifdef CONFIG_WFD +int rtw_init_wifi_display_info(_adapter *padapter); +void rtw_wfd_enable(_adapter *adapter, bool on); +void rtw_wfd_set_ctrl_port(_adapter *adapter, u16 port); +void rtw_tdls_wfd_enable(_adapter *adapter, bool on); + +u32 build_probe_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 tunneled); +u32 build_beacon_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_nego_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_nego_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_nego_confirm_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_invitation_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_invitation_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_assoc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_assoc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_provdisc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); +u32 build_provdisc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); + +u32 rtw_append_beacon_wfd_ie(_adapter *adapter, u8 *pbuf); +u32 rtw_append_probe_req_wfd_ie(_adapter *adapter, u8 *pbuf); +u32 rtw_append_probe_resp_wfd_ie(_adapter *adapter, u8 *pbuf); +u32 rtw_append_assoc_req_wfd_ie(_adapter *adapter, u8 *pbuf); +u32 rtw_append_assoc_resp_wfd_ie(_adapter *adapter, u8 *pbuf); +#endif /*CONFIG_WFD */ + +void rtw_xframe_chk_wfd_ie(struct xmit_frame *xframe); + +u32 process_probe_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); +u32 process_assoc_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len, struct sta_info *psta); +u32 process_p2p_devdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); +u32 process_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); +u8 process_p2p_provdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); +u8 process_p2p_provdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe); +u8 process_p2p_group_negotation_req( struct wifidirect_info *pwdinfo, u8 *pframe, uint len ); +u8 process_p2p_group_negotation_resp( struct wifidirect_info *pwdinfo, u8 *pframe, uint len ); +u8 process_p2p_group_negotation_confirm( struct wifidirect_info *pwdinfo, u8 *pframe, uint len ); +u8 process_p2p_presence_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); +int process_p2p_cross_connect_ie(PADAPTER padapter, u8 *IEs, u32 IELength); + +void p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType); + +#ifdef CONFIG_P2P_PS +void process_p2p_ps_ie(PADAPTER padapter, u8 *IEs, u32 IELength); +void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state); +u8 p2p_ps_wk_cmd(_adapter*padapter, u8 p2p_ps_state, u8 enqueue); +#endif // CONFIG_P2P_PS + +#ifdef CONFIG_IOCTL_CFG80211 +void rtw_init_cfg80211_wifidirect_info( _adapter* padapter); +int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx); +#endif /* CONFIG_IOCTL_CFG80211 */ + +void reset_global_wifidirect_info( _adapter* padapter ); +void rtw_init_wifidirect_timers(_adapter* padapter); +void rtw_init_wifidirect_addrs(_adapter* padapter, u8 *dev_addr, u8 *iface_addr); +void init_wifidirect_info( _adapter* padapter, enum P2P_ROLE role); +int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role); + +static inline void _rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state) +{ + if(wdinfo->p2p_state != state) { + //wdinfo->pre_p2p_state = wdinfo->p2p_state; + wdinfo->p2p_state = state; + } +} +static inline void _rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state) +{ + if(wdinfo->pre_p2p_state != state) { + wdinfo->pre_p2p_state = state; + } +} +#if 0 +static inline void _rtw_p2p_restore_state(struct wifidirect_info *wdinfo) +{ + if(wdinfo->pre_p2p_state != -1) { + wdinfo->p2p_state = wdinfo->pre_p2p_state; + wdinfo->pre_p2p_state = -1; + } +} +#endif +static inline void _rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role) +{ + if(wdinfo->role != role) { + wdinfo->role = role; + } +} +static inline int _rtw_p2p_state(struct wifidirect_info *wdinfo) +{ + return wdinfo->p2p_state; +} +static inline int _rtw_p2p_pre_state(struct wifidirect_info *wdinfo) +{ + return wdinfo->pre_p2p_state; +} +static inline int _rtw_p2p_role(struct wifidirect_info *wdinfo) +{ + return wdinfo->role; +} +static inline bool _rtw_p2p_chk_state(struct wifidirect_info *wdinfo, enum P2P_STATE state) +{ + return wdinfo->p2p_state == state; +} +static inline bool _rtw_p2p_chk_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role) +{ + return wdinfo->role == role; +} + +#ifdef CONFIG_DBG_P2P +void dbg_rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line); +void dbg_rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line); +//void dbg_rtw_p2p_restore_state(struct wifidirect_info *wdinfo, const char *caller, int line); +void dbg_rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role, const char *caller, int line); +#define rtw_p2p_set_state(wdinfo, state) dbg_rtw_p2p_set_state(wdinfo, state, __FUNCTION__, __LINE__) +#define rtw_p2p_set_pre_state(wdinfo, state) dbg_rtw_p2p_set_pre_state(wdinfo, state, __FUNCTION__, __LINE__) +#define rtw_p2p_set_role(wdinfo, role) dbg_rtw_p2p_set_role(wdinfo, role, __FUNCTION__, __LINE__) +//#define rtw_p2p_restore_state(wdinfo) dbg_rtw_p2p_restore_state(wdinfo, __FUNCTION__, __LINE__) +#else //CONFIG_DBG_P2P +#define rtw_p2p_set_state(wdinfo, state) _rtw_p2p_set_state(wdinfo, state) +#define rtw_p2p_set_pre_state(wdinfo, state) _rtw_p2p_set_pre_state(wdinfo, state) +#define rtw_p2p_set_role(wdinfo, role) _rtw_p2p_set_role(wdinfo, role) +//#define rtw_p2p_restore_state(wdinfo) _rtw_p2p_restore_state(wdinfo) +#endif //CONFIG_DBG_P2P + +#define rtw_p2p_state(wdinfo) _rtw_p2p_state(wdinfo) +#define rtw_p2p_pre_state(wdinfo) _rtw_p2p_pre_state(wdinfo) +#define rtw_p2p_role(wdinfo) _rtw_p2p_role(wdinfo) +#define rtw_p2p_chk_state(wdinfo, state) _rtw_p2p_chk_state(wdinfo, state) +#define rtw_p2p_chk_role(wdinfo, role) _rtw_p2p_chk_role(wdinfo, role) + +#define rtw_p2p_findphase_ex_set(wdinfo, value) \ + (wdinfo)->find_phase_state_exchange_cnt = (value) + +#ifdef CONFIG_P2P +//is this find phase exchange for social channel scan? +#define rtw_p2p_findphase_ex_is_social(wdinfo) \ + (wdinfo)->find_phase_state_exchange_cnt >= P2P_FINDPHASE_EX_SOCIAL_FIRST + +//should we need find phase exchange anymore? +#define rtw_p2p_findphase_ex_is_needed(wdinfo) \ + ((wdinfo)->find_phase_state_exchange_cnt < P2P_FINDPHASE_EX_MAX && \ + (wdinfo)->find_phase_state_exchange_cnt != P2P_FINDPHASE_EX_NONE && \ + !(wdinfo)->rx_invitereq_info.scan_op_ch_only && \ + !(wdinfo)->p2p_info.scan_op_ch_only) +#else +#define rtw_p2p_findphase_ex_is_social(wdinfo) 0 +#define rtw_p2p_findphase_ex_is_needed(wdinfo) 0 +#endif /* CONFIG_P2P */ + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_pwrctrl.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_pwrctrl.h new file mode 100644 index 000000000..61f4905a2 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_pwrctrl.h @@ -0,0 +1,461 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_PWRCTRL_H_ +#define __RTW_PWRCTRL_H_ + + +#define FW_PWR0 0 +#define FW_PWR1 1 +#define FW_PWR2 2 +#define FW_PWR3 3 + + +#define HW_PWR0 7 +#define HW_PWR1 6 +#define HW_PWR2 2 +#define HW_PWR3 0 +#define HW_PWR4 8 + +#define FW_PWRMSK 0x7 + + +#define XMIT_ALIVE BIT(0) +#define RECV_ALIVE BIT(1) +#define CMD_ALIVE BIT(2) +#define EVT_ALIVE BIT(3) +#ifdef CONFIG_BT_COEXIST +#define BTCOEX_ALIVE BIT(4) +#endif // CONFIG_BT_COEXIST + +enum Power_Mgnt +{ + PS_MODE_ACTIVE = 0 , + PS_MODE_MIN , + PS_MODE_MAX , + PS_MODE_DTIM , //PS_MODE_SELF_DEFINED + PS_MODE_VOIP , + PS_MODE_UAPSD_WMM , + PS_MODE_UAPSD , + PS_MODE_IBSS , + PS_MODE_WWLAN , + PM_Radio_Off , + PM_Card_Disable , + PS_MODE_NUM, +}; + +#ifdef CONFIG_PNO_SUPPORT +#define MAX_PNO_LIST_COUNT 16 +#define MAX_SCAN_LIST_COUNT 14 //2.4G only +#define MAX_HIDDEN_AP 8 //8 hidden AP +#endif + +/* + BIT[2:0] = HW state + BIT[3] = Protocol PS state, 0: register active state , 1: register sleep state + BIT[4] = sub-state +*/ + +#define PS_DPS BIT(0) +#define PS_LCLK (PS_DPS) +#define PS_RF_OFF BIT(1) +#define PS_ALL_ON BIT(2) +#define PS_ST_ACTIVE BIT(3) + +#define PS_ISR_ENABLE BIT(4) +#define PS_IMR_ENABLE BIT(5) +#define PS_ACK BIT(6) +#define PS_TOGGLE BIT(7) + +#define PS_STATE_MASK (0x0F) +#define PS_STATE_HW_MASK (0x07) +#define PS_SEQ_MASK (0xc0) + +#define PS_STATE(x) (PS_STATE_MASK & (x)) +#define PS_STATE_HW(x) (PS_STATE_HW_MASK & (x)) +#define PS_SEQ(x) (PS_SEQ_MASK & (x)) + +#define PS_STATE_S0 (PS_DPS) +#define PS_STATE_S1 (PS_LCLK) +#define PS_STATE_S2 (PS_RF_OFF) +#define PS_STATE_S3 (PS_ALL_ON) +#define PS_STATE_S4 ((PS_ST_ACTIVE) | (PS_ALL_ON)) + + +#define PS_IS_RF_ON(x) ((x) & (PS_ALL_ON)) +#define PS_IS_ACTIVE(x) ((x) & (PS_ST_ACTIVE)) +#define CLR_PS_STATE(x) ((x) = ((x) & (0xF0))) + + +struct reportpwrstate_parm { + unsigned char mode; + unsigned char state; //the CPWM value + unsigned short rsvd; +}; + + +typedef _sema _pwrlock; + + +__inline static void _init_pwrlock(_pwrlock *plock) +{ + _rtw_init_sema(plock, 1); +} + +__inline static void _free_pwrlock(_pwrlock *plock) +{ + _rtw_free_sema(plock); +} + + +__inline static void _enter_pwrlock(_pwrlock *plock) +{ + _rtw_down_sema(plock); +} + + +__inline static void _exit_pwrlock(_pwrlock *plock) +{ + _rtw_up_sema(plock); +} + +#define LPS_DELAY_TIME 1*HZ // 1 sec + +#define EXE_PWR_NONE 0x01 +#define EXE_PWR_IPS 0x02 +#define EXE_PWR_LPS 0x04 + +// RF state. +typedef enum _rt_rf_power_state +{ + rf_on, // RF is on after RFSleep or RFOff + rf_sleep, // 802.11 Power Save mode + rf_off, // HW/SW Radio OFF or Inactive Power Save + //=====Add the new RF state above this line=====// + rf_max +}rt_rf_power_state; + +// RF Off Level for IPS or HW/SW radio off +#define RT_RF_OFF_LEVL_ASPM BIT(0) // PCI ASPM +#define RT_RF_OFF_LEVL_CLK_REQ BIT(1) // PCI clock request +#define RT_RF_OFF_LEVL_PCI_D3 BIT(2) // PCI D3 mode +#define RT_RF_OFF_LEVL_HALT_NIC BIT(3) // NIC halt, re-initialize hw parameters +#define RT_RF_OFF_LEVL_FREE_FW BIT(4) // FW free, re-download the FW +#define RT_RF_OFF_LEVL_FW_32K BIT(5) // FW in 32k +#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) // Always enable ASPM and Clock Req in initialization. +#define RT_RF_LPS_DISALBE_2R BIT(30) // When LPS is on, disable 2R if no packet is received or transmittd. +#define RT_RF_LPS_LEVEL_ASPM BIT(31) // LPS with ASPM + +#define RT_IN_PS_LEVEL(ppsc, _PS_FLAG) ((ppsc->cur_ps_level & _PS_FLAG) ? _TRUE : _FALSE) +#define RT_CLEAR_PS_LEVEL(ppsc, _PS_FLAG) (ppsc->cur_ps_level &= (~(_PS_FLAG))) +#define RT_SET_PS_LEVEL(ppsc, _PS_FLAG) (ppsc->cur_ps_level |= _PS_FLAG) + +// ASPM OSC Control bit, added by Roger, 2013.03.29. +#define RT_PCI_ASPM_OSC_IGNORE 0 // PCI ASPM ignore OSC control in default +#define RT_PCI_ASPM_OSC_ENABLE BIT0 // PCI ASPM controlled by OS according to ACPI Spec 5.0 +#define RT_PCI_ASPM_OSC_DISABLE BIT1 // PCI ASPM controlled by driver or BIOS, i.e., force enable ASPM + + +enum _PS_BBRegBackup_ { + PSBBREG_RF0 = 0, + PSBBREG_RF1, + PSBBREG_RF2, + PSBBREG_AFE0, + PSBBREG_TOTALCNT +}; + +enum { // for ips_mode + IPS_NONE=0, + IPS_NORMAL, + IPS_LEVEL_2, + IPS_NUM +}; + +// Design for pwrctrl_priv.ips_deny, 32 bits for 32 reasons at most +typedef enum _PS_DENY_REASON +{ + PS_DENY_DRV_INITIAL = 0, + PS_DENY_SCAN, + PS_DENY_JOIN, + PS_DENY_DISCONNECT, + PS_DENY_SUSPEND, + PS_DENY_IOCTL, + PS_DENY_MGNT_TX, + PS_DENY_DRV_REMOVE = 30, + PS_DENY_OTHERS = 31 +} PS_DENY_REASON; + +#ifdef CONFIG_PNO_SUPPORT +typedef struct pno_nlo_info +{ + u32 fast_scan_period; //Fast scan period + u8 ssid_num; //number of entry + u8 hidden_ssid_num; + u32 slow_scan_period; //slow scan period + u32 fast_scan_iterations; //Fast scan iterations + u8 ssid_length[MAX_PNO_LIST_COUNT]; //SSID Length Array + u8 ssid_cipher_info[MAX_PNO_LIST_COUNT]; //Cipher information for security + u8 ssid_channel_info[MAX_PNO_LIST_COUNT]; //channel information + u8 loc_probe_req[MAX_HIDDEN_AP]; //loc_probeReq +}pno_nlo_info_t; + +typedef struct pno_ssid { + u32 SSID_len; + u8 SSID[32]; +} pno_ssid_t; + +typedef struct pno_ssid_list { + pno_ssid_t node[MAX_PNO_LIST_COUNT]; +}pno_ssid_list_t; + +typedef struct pno_scan_channel_info +{ + u8 channel; + u8 tx_power; + u8 timeout; + u8 active; //set 1 means active scan, or pasivite scan. +}pno_scan_channel_info_t; + +typedef struct pno_scan_info +{ + u8 enableRFE; //Enable RFE + u8 period_scan_time; //exclusive with fast_scan_period and slow_scan_period + u8 periodScan; //exclusive with fast_scan_period and slow_scan_period + u8 orig_80_offset; //original channel 80 offset + u8 orig_40_offset; //original channel 40 offset + u8 orig_bw; //original bandwidth + u8 orig_ch; //original channel + u8 channel_num; //number of channel + u64 rfe_type; //rfe_type && 0x00000000000000ff + pno_scan_channel_info_t ssid_channel_info[MAX_SCAN_LIST_COUNT]; +}pno_scan_info_t; +#endif //CONFIG_PNO_SUPPORT + +struct pwrctrl_priv +{ + _pwrlock lock; + _pwrlock check_32k_lock; + volatile u8 rpwm; // requested power state for fw + volatile u8 cpwm; // fw current power state. updated when 1. read from HCPWM 2. driver lowers power level + volatile u8 tog; // toggling + volatile u8 cpwm_tog; // toggling + + u8 pwr_mode; + u8 smart_ps; + u8 bcn_ant_mode; + u8 dtim; + + u32 alives; + _workitem cpwm_event; +#ifdef CONFIG_LPS_RPWM_TIMER + u8 brpwmtimeout; + _workitem rpwmtimeoutwi; + _timer pwr_rpwm_timer; +#endif // CONFIG_LPS_RPWM_TIMER + u8 bpower_saving; //for LPS/IPS + + u8 b_hw_radio_off; + u8 reg_rfoff; + u8 reg_pdnmode; //powerdown mode + u32 rfoff_reason; + + //RF OFF Level + u32 cur_ps_level; + u32 reg_rfps_level; + + uint ips_enter_cnts; + uint ips_leave_cnts; + uint lps_enter_cnts; + uint lps_leave_cnts; + + u8 ips_mode; + u8 ips_org_mode; + u8 ips_mode_req; // used to accept the mode setting request, will update to ipsmode later + uint bips_processing; + u32 ips_deny_time; /* will deny IPS when system time is smaller than this */ + u8 pre_ips_type;// 0: default flow, 1: carddisbale flow + + // ps_deny: if 0, power save is free to go; otherwise deny all kinds of power save. + // Use PS_DENY_REASON to decide reason. + // Don't access this variable directly without control function, + // and this variable should be protected by lock. + u32 ps_deny; + + u8 ps_processing; /* temporarily used to mark whether in rtw_ps_processor */ + + u8 fw_psmode_iface_id; + u8 bLeisurePs; + u8 LpsIdleCount; + u8 power_mgnt; + u8 org_power_mgnt; + u8 bFwCurrentInPSMode; + u32 DelayLPSLastTimeStamp; + s32 pnp_current_pwr_state; + u8 pnp_bstop_trx; + + + u8 bInternalAutoSuspend; + u8 bInSuspend; +#ifdef CONFIG_BT_COEXIST + u8 bAutoResume; + u8 autopm_cnt; +#endif + u8 bSupportRemoteWakeup; + u8 wowlan_wake_reason; + u8 wowlan_ap_mode; + u8 wowlan_mode; + u8 wowlan_p2p_mode; + u8 wowlan_pno_enable; +#ifdef CONFIG_GPIO_WAKEUP + u8 is_high_active; +#endif /* CONFIG_GPIO_WAKEUP */ + _timer pwr_state_check_timer; + int pwr_state_check_interval; + u8 pwr_state_check_cnts; + + int ps_flag; /* used by autosuspend */ + + rt_rf_power_state rf_pwrstate;//cur power state, only for IPS + //rt_rf_power_state current_rfpwrstate; + rt_rf_power_state change_rfpwrstate; + + u8 bHWPowerdown; /* power down mode selection. 0:radio off, 1:power down */ + u8 bHWPwrPindetect; /* come from registrypriv.hwpwrp_detect. enable power down function. 0:disable, 1:enable */ + u8 bkeepfwalive; + u8 brfoffbyhw; + unsigned long PS_BBRegBackup[PSBBREG_TOTALCNT]; + + #ifdef CONFIG_RESUME_IN_WORKQUEUE + struct workqueue_struct *rtw_workqueue; + _workitem resume_work; + #endif + + #ifdef CONFIG_HAS_EARLYSUSPEND + struct early_suspend early_suspend; + u8 do_late_resume; + #endif //CONFIG_HAS_EARLYSUSPEND + + #ifdef CONFIG_ANDROID_POWER + android_early_suspend_t early_suspend; + u8 do_late_resume; + #endif + + #ifdef CONFIG_INTEL_PROXIM + u8 stored_power_mgnt; + #endif +}; + +#define rtw_get_ips_mode_req(pwrctl) \ + (pwrctl)->ips_mode_req + +#define rtw_ips_mode_req(pwrctl, ips_mode) \ + (pwrctl)->ips_mode_req = (ips_mode) + +#define RTW_PWR_STATE_CHK_INTERVAL 2000 + +#define _rtw_set_pwr_state_check_timer(pwrctl, ms) \ + do { \ + /*DBG_871X("%s _rtw_set_pwr_state_check_timer(%p, %d)\n", __FUNCTION__, (pwrctl), (ms));*/ \ + _set_timer(&(pwrctl)->pwr_state_check_timer, (ms)); \ + } while(0) + +#define rtw_set_pwr_state_check_timer(pwrctl) \ + _rtw_set_pwr_state_check_timer((pwrctl), (pwrctl)->pwr_state_check_interval) + +extern void rtw_init_pwrctrl_priv(_adapter *adapter); +extern void rtw_free_pwrctrl_priv(_adapter * adapter); + +#ifdef CONFIG_LPS_LCLK +s32 rtw_register_task_alive(PADAPTER, u32 task); +void rtw_unregister_task_alive(PADAPTER, u32 task); +extern s32 rtw_register_tx_alive(PADAPTER padapter); +extern void rtw_unregister_tx_alive(PADAPTER padapter); +extern s32 rtw_register_rx_alive(PADAPTER padapter); +extern void rtw_unregister_rx_alive(PADAPTER padapter); +extern s32 rtw_register_cmd_alive(PADAPTER padapter); +extern void rtw_unregister_cmd_alive(PADAPTER padapter); +extern s32 rtw_register_evt_alive(PADAPTER padapter); +extern void rtw_unregister_evt_alive(PADAPTER padapter); +extern void cpwm_int_hdl(PADAPTER padapter, struct reportpwrstate_parm *preportpwrstate); +extern void LPS_Leave_check(PADAPTER padapter); +#endif + +extern void LeaveAllPowerSaveMode(PADAPTER Adapter); +extern void LeaveAllPowerSaveModeDirect(PADAPTER Adapter); +#ifdef CONFIG_IPS +void _ips_enter(_adapter * padapter); +void ips_enter(_adapter * padapter); +int _ips_leave(_adapter * padapter); +int ips_leave(_adapter * padapter); +#endif + +void rtw_ps_processor(_adapter*padapter); + +#ifdef CONFIG_AUTOSUSPEND +int autoresume_enter(_adapter* padapter); +#endif +#ifdef SUPPORT_HW_RFOFF_DETECTED +rt_rf_power_state RfOnOffDetect(IN PADAPTER pAdapter ); +#endif + + +int rtw_fw_ps_state(PADAPTER padapter); + +#ifdef CONFIG_LPS +s32 LPS_RF_ON_check(PADAPTER padapter, u32 delay_ms); +void LPS_Enter(PADAPTER padapter, const char *msg); +void LPS_Leave(PADAPTER padapter, const char *msg); +void traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets); +void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode, const char *msg); +void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable); +void rtw_set_rpwm(_adapter * padapter, u8 val8); +#endif + +#ifdef CONFIG_RESUME_IN_WORKQUEUE +void rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv); +#endif //CONFIG_RESUME_IN_WORKQUEUE + +#if defined(CONFIG_HAS_EARLYSUSPEND ) || defined(CONFIG_ANDROID_POWER) +bool rtw_is_earlysuspend_registered(struct pwrctrl_priv *pwrpriv); +bool rtw_is_do_late_resume(struct pwrctrl_priv *pwrpriv); +void rtw_set_do_late_resume(struct pwrctrl_priv *pwrpriv, bool enable); +void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv); +void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv); +#else +#define rtw_is_earlysuspend_registered(pwrpriv) _FALSE +#define rtw_is_do_late_resume(pwrpriv) _FALSE +#define rtw_set_do_late_resume(pwrpriv, enable) do {} while (0) +#define rtw_register_early_suspend(pwrpriv) do {} while (0) +#define rtw_unregister_early_suspend(pwrpriv) do {} while (0) +#endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */ + +u8 rtw_interface_ps_func(_adapter *padapter,HAL_INTF_PS_FUNC efunc_id,u8* val); +void rtw_set_ips_deny(_adapter *padapter, u32 ms); +int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller); +#define rtw_pwr_wakeup(adapter) _rtw_pwr_wakeup(adapter, RTW_PWR_STATE_CHK_INTERVAL, __FUNCTION__) +#define rtw_pwr_wakeup_ex(adapter, ips_deffer_ms) _rtw_pwr_wakeup(adapter, ips_deffer_ms, __FUNCTION__) +int rtw_pm_set_ips(_adapter *padapter, u8 mode); +int rtw_pm_set_lps(_adapter *padapter, u8 mode); + +void rtw_ps_deny(PADAPTER padapter, PS_DENY_REASON reason); +void rtw_ps_deny_cancel(PADAPTER padapter, PS_DENY_REASON reason); +u32 rtw_ps_deny_get(PADAPTER padapter); + +#endif //__RTL871X_PWRCTRL_H_ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_qos.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_qos.h new file mode 100644 index 000000000..cc5fcea51 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_qos.h @@ -0,0 +1,35 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#ifndef _RTW_QOS_H_ +#define _RTW_QOS_H_ + + + +struct qos_priv { + + unsigned int qos_option; //bit mask option: u-apsd, s-apsd, ts, block ack... + +}; + + +#endif //_RTL871X_QOS_H_ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_recv.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_recv.h new file mode 100644 index 000000000..498e88a07 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_recv.h @@ -0,0 +1,880 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_RECV_H_ +#define _RTW_RECV_H_ + +#ifdef PLATFORM_OS_XP + #ifdef CONFIG_SDIO_HCI + #define NR_RECVBUFF 1024//512//128 + #else + #define NR_RECVBUFF (16) + #endif +#elif defined(PLATFORM_OS_CE) + #ifdef CONFIG_SDIO_HCI + #define NR_RECVBUFF (128) + #else + #define NR_RECVBUFF (4) + #endif +#else //PLATFORM_LINUX /PLATFORM_BSD + + #ifdef CONFIG_SINGLE_RECV_BUF + #define NR_RECVBUFF (1) + #else + #if defined(CONFIG_GSPI_HCI) + #define NR_RECVBUFF (32) + #elif defined(CONFIG_SDIO_HCI) + #define NR_RECVBUFF (8) + #else + #define NR_RECVBUFF (8) + #endif + #endif //CONFIG_SINGLE_RECV_BUF + #ifdef CONFIG_PREALLOC_RX_SKB_BUFFER + #define NR_PREALLOC_RECV_SKB (rtw_rtkm_get_nr_recv_skb()>>1) + #else /*!CONFIG_PREALLOC_RX_SKB_BUFFER */ + #define NR_PREALLOC_RECV_SKB 8 + #endif /* CONFIG_PREALLOC_RX_SKB_BUFFER */ + +#endif + +#define NR_RECVFRAME 256 + +#define RXFRAME_ALIGN 8 +#define RXFRAME_ALIGN_SZ (1<network.PhyInfo.SignalStrength); + #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA + struct rx_raw_rssi raw_rssi_info; + #endif + //s8 rxpwdb; + s16 noise; + //int RxSNRdB[2]; + //s8 RxRssi[2]; + //int FalseAlmCnt_all; + + +#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS + _timer signal_stat_timer; + u32 signal_stat_sampling_interval; + //u32 signal_stat_converging_constant; + struct signal_stat signal_qual_data; + struct signal_stat signal_strength_data; +#else //CONFIG_NEW_SIGNAL_STAT_PROCESS + struct smooth_rssi_data signal_qual_data; + struct smooth_rssi_data signal_strength_data; +#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS + u16 sink_udpport,pre_rtp_rxseq,cur_rtp_rxseq; +}; + +#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS +#define rtw_set_signal_stat_timer(recvpriv) _set_timer(&(recvpriv)->signal_stat_timer, (recvpriv)->signal_stat_sampling_interval) +#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS + +struct sta_recv_priv { + + _lock lock; + sint option; + + //_queue blk_strms[MAX_RX_NUMBLKS]; + _queue defrag_q; //keeping the fragment frame until defrag + + struct stainfo_rxcache rxcache; + + //uint sta_rx_bytes; + //uint sta_rx_pkts; + //uint sta_rx_fail; + +}; + + +struct recv_buf +{ + _list list; + + _lock recvbuf_lock; + + u32 ref_cnt; + + PADAPTER adapter; + + u8 *pbuf; + u8 *pallocated_buf; + + u32 len; + u8 *phead; + u8 *pdata; + u8 *ptail; + u8 *pend; + +#ifdef CONFIG_USB_HCI + + #if defined(PLATFORM_OS_XP)||defined(PLATFORM_LINUX)||defined(PLATFORM_FREEBSD) + PURB purb; + dma_addr_t dma_transfer_addr; /* (in) dma addr for transfer_buffer */ + u32 alloc_sz; + #endif + + #ifdef PLATFORM_OS_XP + PIRP pirp; + #endif + + #ifdef PLATFORM_OS_CE + USB_TRANSFER usb_transfer_read_port; + #endif + + u8 irp_pending; + int transfer_len; + +#endif + +#ifdef PLATFORM_LINUX + _pkt *pskb; +#endif +#ifdef PLATFORM_FREEBSD //skb solution + struct sk_buff *pskb; +#endif //PLATFORM_FREEBSD //skb solution +}; + + +/* + head -----> + + data -----> + + payload + + tail -----> + + + end -----> + + len = (unsigned int )(tail - data); + +*/ +struct recv_frame_hdr +{ + _list list; +#ifndef CONFIG_BSD_RX_USE_MBUF + struct sk_buff *pkt; + struct sk_buff *pkt_newalloc; +#else // CONFIG_BSD_RX_USE_MBUF + _pkt *pkt; + _pkt *pkt_newalloc; +#endif // CONFIG_BSD_RX_USE_MBUF + + _adapter *adapter; + + u8 fragcnt; + + int frame_tag; + + struct rx_pkt_attrib attrib; + + uint len; + u8 *rx_head; + u8 *rx_data; + u8 *rx_tail; + u8 *rx_end; + + void *precvbuf; + + + // + struct sta_info *psta; + + //for A-MPDU Rx reordering buffer control + struct recv_reorder_ctrl *preorder_ctrl; + +#ifdef CONFIG_WAPI_SUPPORT + u8 UserPriority; + u8 WapiTempPN[16]; + u8 WapiSrcAddr[6]; + u8 bWapiCheckPNInDecrypt; + u8 bIsWaiPacket; +#endif + +}; + + +union recv_frame{ + + union{ + _list list; + struct recv_frame_hdr hdr; + uint mem[RECVFRAME_HDR_ALIGN>>2]; + }u; + + //uint mem[MAX_RXSZ>>2]; + +}; + +bool rtw_rframe_del_wfd_ie(union recv_frame *rframe, u8 ies_offset); + +typedef enum _RX_PACKET_TYPE{ + NORMAL_RX,//Normal rx packet + TX_REPORT1,//CCX + TX_REPORT2,//TX RPT + HIS_REPORT,// USB HISR RPT + C2H_PACKET +}RX_PACKET_TYPE, *PRX_PACKET_TYPE; + +extern union recv_frame *_rtw_alloc_recvframe (_queue *pfree_recv_queue); //get a free recv_frame from pfree_recv_queue +extern union recv_frame *rtw_alloc_recvframe (_queue *pfree_recv_queue); //get a free recv_frame from pfree_recv_queue +extern void rtw_init_recvframe(union recv_frame *precvframe ,struct recv_priv *precvpriv); +extern int rtw_free_recvframe(union recv_frame *precvframe, _queue *pfree_recv_queue); + +#define rtw_dequeue_recvframe(queue) rtw_alloc_recvframe(queue) +extern int _rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue); +extern int rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue); + +extern void rtw_free_recvframe_queue(_queue *pframequeue, _queue *pfree_recv_queue); +u32 rtw_free_uc_swdec_pending_queue(_adapter *adapter); + +sint rtw_enqueue_recvbuf_to_head(struct recv_buf *precvbuf, _queue *queue); +sint rtw_enqueue_recvbuf(struct recv_buf *precvbuf, _queue *queue); +struct recv_buf *rtw_dequeue_recvbuf (_queue *queue); + +void rtw_reordering_ctrl_timeout_handler(void *pcontext); + +void rx_query_phy_status(union recv_frame *rframe, u8 *phy_stat); +int rtw_inc_and_chk_continual_no_rx_packet(struct sta_info *sta, int tid_index); +void rtw_reset_continual_no_rx_packet(struct sta_info *sta, int tid_index); + +__inline static u8 *get_rxmem(union recv_frame *precvframe) +{ + //always return rx_head... + if(precvframe==NULL) + return NULL; + + return precvframe->u.hdr.rx_head; +} + +__inline static u8 *get_rx_status(union recv_frame *precvframe) +{ + + return get_rxmem(precvframe); + +} + +__inline static u8 *get_recvframe_data(union recv_frame *precvframe) +{ + + //alwasy return rx_data + if(precvframe==NULL) + return NULL; + + return precvframe->u.hdr.rx_data; + +} + +__inline static u8 *recvframe_push(union recv_frame *precvframe, sint sz) +{ + // append data before rx_data + + /* add data to the start of recv_frame + * + * This function extends the used data area of the recv_frame at the buffer + * start. rx_data must be still larger than rx_head, after pushing. + */ + + if(precvframe==NULL) + return NULL; + + + precvframe->u.hdr.rx_data -= sz ; + if( precvframe->u.hdr.rx_data < precvframe->u.hdr.rx_head ) + { + precvframe->u.hdr.rx_data += sz ; + return NULL; + } + + precvframe->u.hdr.len +=sz; + + return precvframe->u.hdr.rx_data; + +} + + +__inline static u8 *recvframe_pull(union recv_frame *precvframe, sint sz) +{ + // rx_data += sz; move rx_data sz bytes hereafter + + //used for extract sz bytes from rx_data, update rx_data and return the updated rx_data to the caller + + + if(precvframe==NULL) + return NULL; + + + precvframe->u.hdr.rx_data += sz; + + if(precvframe->u.hdr.rx_data > precvframe->u.hdr.rx_tail) + { + precvframe->u.hdr.rx_data -= sz; + return NULL; + } + + precvframe->u.hdr.len -=sz; + + return precvframe->u.hdr.rx_data; + +} + +__inline static u8 *recvframe_put(union recv_frame *precvframe, sint sz) +{ + // rx_tai += sz; move rx_tail sz bytes hereafter + + //used for append sz bytes from ptr to rx_tail, update rx_tail and return the updated rx_tail to the caller + //after putting, rx_tail must be still larger than rx_end. + unsigned char * prev_rx_tail; + + /* DBG_871X("recvframe_put: len=%d\n", sz); */ + + if(precvframe==NULL) + return NULL; + + prev_rx_tail = precvframe->u.hdr.rx_tail; + + precvframe->u.hdr.rx_tail += sz; + + if(precvframe->u.hdr.rx_tail > precvframe->u.hdr.rx_end) + { + precvframe->u.hdr.rx_tail -= sz; + return NULL; + } + + precvframe->u.hdr.len +=sz; + + return precvframe->u.hdr.rx_tail; + +} + + + +__inline static u8 *recvframe_pull_tail(union recv_frame *precvframe, sint sz) +{ + // rmv data from rx_tail (by yitsen) + + //used for extract sz bytes from rx_end, update rx_end and return the updated rx_end to the caller + //after pulling, rx_end must be still larger than rx_data. + + if(precvframe==NULL) + return NULL; + + precvframe->u.hdr.rx_tail -= sz; + + if(precvframe->u.hdr.rx_tail < precvframe->u.hdr.rx_data) + { + precvframe->u.hdr.rx_tail += sz; + return NULL; + } + + precvframe->u.hdr.len -=sz; + + return precvframe->u.hdr.rx_tail; + +} + + + +__inline static _buffer * get_rxbuf_desc(union recv_frame *precvframe) +{ + _buffer * buf_desc; + + if(precvframe==NULL) + return NULL; +#ifdef PLATFORM_WINDOWS + NdisQueryPacket(precvframe->u.hdr.pkt, NULL, NULL, &buf_desc, NULL); +#endif + + return buf_desc; +} + + +__inline static union recv_frame *rxmem_to_recvframe(u8 *rxmem) +{ + //due to the design of 2048 bytes alignment of recv_frame, we can reference the union recv_frame + //from any given member of recv_frame. + // rxmem indicates the any member/address in recv_frame + + return (union recv_frame*)(((SIZE_PTR)rxmem >> RXFRAME_ALIGN) << RXFRAME_ALIGN); + +} + +__inline static union recv_frame *pkt_to_recvframe(_pkt *pkt) +{ + + u8 * buf_star; + union recv_frame * precv_frame; +#ifdef PLATFORM_WINDOWS + _buffer * buf_desc; + uint len; + + NdisQueryPacket(pkt, NULL, NULL, &buf_desc, &len); + NdisQueryBufferSafe(buf_desc, &buf_star, &len, HighPagePriority); +#endif + precv_frame = rxmem_to_recvframe((unsigned char*)buf_star); + + return precv_frame; +} + +__inline static u8 *pkt_to_recvmem(_pkt *pkt) +{ + // return the rx_head + + union recv_frame * precv_frame = pkt_to_recvframe(pkt); + + return precv_frame->u.hdr.rx_head; + +} + +__inline static u8 *pkt_to_recvdata(_pkt *pkt) +{ + // return the rx_data + + union recv_frame * precv_frame =pkt_to_recvframe(pkt); + + return precv_frame->u.hdr.rx_data; + +} + + +__inline static sint get_recvframe_len(union recv_frame *precvframe) +{ + return precvframe->u.hdr.len; +} + + +__inline static s32 translate_percentage_to_dbm(u32 SignalStrengthIndex) +{ + s32 SignalPower; // in dBm. + +#ifdef CONFIG_SIGNAL_SCALE_MAPPING + /* Translate to dBm (x=0.5y-95). */ + SignalPower = (s32)((SignalStrengthIndex + 1) >> 1); + SignalPower -= 95; +#else + /* Translate to dBm (x=y-100) */ + SignalPower = SignalStrengthIndex - 100; +#endif + + return SignalPower; +} + + +struct sta_info; + +extern void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv); + +extern void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame); + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_rf.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_rf.h new file mode 100644 index 000000000..d4dd6a29e --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_rf.h @@ -0,0 +1,271 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_RF_H_ +#define __RTW_RF_H_ + + +#define OFDM_PHY 1 +#define MIXED_PHY 2 +#define CCK_PHY 3 + +#define NumRates (13) + +// slot time for 11g +#define SHORT_SLOT_TIME 9 +#define NON_SHORT_SLOT_TIME 20 + +#define RTL8711_RF_MAX_SENS 6 +#define RTL8711_RF_DEF_SENS 4 + +// +// We now define the following channels as the max channels in each channel plan. +// 2G, total 14 chnls +// {1,2,3,4,5,6,7,8,9,10,11,12,13,14} +// 5G, total 24 chnls +// {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165} +#define MAX_CHANNEL_NUM_2G 14 +#define MAX_CHANNEL_NUM_5G 24 +#define MAX_CHANNEL_NUM 38//14+24 + +#define CENTER_CH_2G_NUM 14 +#define CENTER_CH_5G_20M_NUM 28 /* 20M center channels */ +#define CENTER_CH_5G_40M_NUM 14 /* 40M center channels */ +#define CENTER_CH_5G_80M_NUM 7 /* 80M center channels */ +#define CENTER_CH_5G_ALL_NUM (CENTER_CH_5G_20M_NUM + CENTER_CH_5G_40M_NUM + CENTER_CH_5G_80M_NUM) + +extern u8 center_ch_5g_20m[CENTER_CH_5G_20M_NUM]; +extern u8 center_ch_5g_40m[CENTER_CH_5G_40M_NUM]; +extern u8 center_ch_5g_80m[CENTER_CH_5G_80M_NUM]; +extern u8 center_ch_5g_all[CENTER_CH_5G_ALL_NUM]; + +u8 center_chs_5g_num(u8 bw); +u8 center_chs_5g(u8 bw, u8 id); + +//#define NUM_REGULATORYS 21 +#define NUM_REGULATORYS 1 + +//Country codes +#define USA 0x555320 +#define EUROPE 0x1 //temp, should be provided later +#define JAPAN 0x2 //temp, should be provided later + +struct regulatory_class { + u32 starting_freq; //MHz, + u8 channel_set[MAX_CHANNEL_NUM]; + u8 channel_cck_power[MAX_CHANNEL_NUM];//dbm + u8 channel_ofdm_power[MAX_CHANNEL_NUM];//dbm + u8 txpower_limit; //dbm + u8 channel_spacing; //MHz + u8 modem; +}; + +typedef enum _CAPABILITY{ + cESS = 0x0001, + cIBSS = 0x0002, + cPollable = 0x0004, + cPollReq = 0x0008, + cPrivacy = 0x0010, + cShortPreamble = 0x0020, + cPBCC = 0x0040, + cChannelAgility = 0x0080, + cSpectrumMgnt = 0x0100, + cQos = 0x0200, // For HCCA, use with CF-Pollable and CF-PollReq + cShortSlotTime = 0x0400, + cAPSD = 0x0800, + cRM = 0x1000, // RRM (Radio Request Measurement) + cDSSS_OFDM = 0x2000, + cDelayedBA = 0x4000, + cImmediateBA = 0x8000, +}CAPABILITY, *PCAPABILITY; + +enum _REG_PREAMBLE_MODE{ + PREAMBLE_LONG = 1, + PREAMBLE_AUTO = 2, + PREAMBLE_SHORT = 3, +}; + + +enum _RTL8712_RF_MIMO_CONFIG_{ + RTL8712_RFCONFIG_1T=0x10, + RTL8712_RFCONFIG_2T=0x20, + RTL8712_RFCONFIG_1R=0x01, + RTL8712_RFCONFIG_2R=0x02, + RTL8712_RFCONFIG_1T1R=0x11, + RTL8712_RFCONFIG_1T2R=0x12, + RTL8712_RFCONFIG_TURBO=0x92, + RTL8712_RFCONFIG_2T2R=0x22 +}; + +typedef enum _RF_PATH { + RF_PATH_A = 0, + RF_PATH_B = 1, + RF_PATH_C = 2, + RF_PATH_D = 3, +} RF_PATH, *PRF_PATH; + +#define rf_path_char(path) (((path) >= RF_PATH_MAX) ? 'X' : 'A' + (path)) + +// Bandwidth Offset +#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 +#define HAL_PRIME_CHNL_OFFSET_LOWER 1 +#define HAL_PRIME_CHNL_OFFSET_UPPER 2 + +typedef enum _BAND_TYPE { + BAND_ON_2_4G = 0, + BAND_ON_5G = 1, + BAND_ON_BOTH = 2, + BAND_MAX = 3, +} BAND_TYPE, *PBAND_TYPE; + +extern const char * const _band_str[]; +#define band_str(band) (((band) >= BAND_MAX) ? _band_str[BAND_MAX] : _band_str[(band)]) + +extern const u8 _band_to_band_cap[]; +#define band_to_band_cap(band) (((band) >= BAND_MAX) ? _band_to_band_cap[BAND_MAX] : _band_to_band_cap[(band)]) + +// Represent Channel Width in HT Capabilities +// +typedef enum _CHANNEL_WIDTH{ + CHANNEL_WIDTH_20 = 0, + CHANNEL_WIDTH_40 = 1, + CHANNEL_WIDTH_80 = 2, + CHANNEL_WIDTH_160 = 3, + CHANNEL_WIDTH_80_80 = 4, + CHANNEL_WIDTH_MAX = 5, +}CHANNEL_WIDTH, *PCHANNEL_WIDTH; + +extern const char * const _ch_width_str[]; +#define ch_width_str(bw) (((bw) >= CHANNEL_WIDTH_MAX) ? _ch_width_str[CHANNEL_WIDTH_MAX] : _ch_width_str[(bw)]) + +extern const u8 _ch_width_to_bw_cap[]; +#define ch_width_to_bw_cap(bw) (((bw) >= CHANNEL_WIDTH_MAX) ? _ch_width_to_bw_cap[CHANNEL_WIDTH_MAX] : _ch_width_to_bw_cap[(bw)]) + +// +// Represent Extention Channel Offset in HT Capabilities +// This is available only in 40Mhz mode. +// +typedef enum _EXTCHNL_OFFSET{ + EXTCHNL_OFFSET_NO_EXT = 0, + EXTCHNL_OFFSET_UPPER = 1, + EXTCHNL_OFFSET_NO_DEF = 2, + EXTCHNL_OFFSET_LOWER = 3, +}EXTCHNL_OFFSET, *PEXTCHNL_OFFSET; + +typedef enum _VHT_DATA_SC{ + VHT_DATA_SC_DONOT_CARE = 0, + VHT_DATA_SC_20_UPPER_OF_80MHZ = 1, + VHT_DATA_SC_20_LOWER_OF_80MHZ = 2, + VHT_DATA_SC_20_UPPERST_OF_80MHZ = 3, + VHT_DATA_SC_20_LOWEST_OF_80MHZ = 4, + VHT_DATA_SC_20_RECV1 = 5, + VHT_DATA_SC_20_RECV2 = 6, + VHT_DATA_SC_20_RECV3 = 7, + VHT_DATA_SC_20_RECV4 = 8, + VHT_DATA_SC_40_UPPER_OF_80MHZ = 9, + VHT_DATA_SC_40_LOWER_OF_80MHZ = 10, +}VHT_DATA_SC, *PVHT_DATA_SC_E; + +typedef enum _PROTECTION_MODE{ + PROTECTION_MODE_AUTO = 0, + PROTECTION_MODE_FORCE_ENABLE = 1, + PROTECTION_MODE_FORCE_DISABLE = 2, +}PROTECTION_MODE, *PPROTECTION_MODE; + +typedef enum _RT_RF_TYPE_DEFINITION +{ + RF_1T2R = 0, + RF_2T4R = 1, + RF_2T2R = 2, + RF_1T1R = 3, + RF_2T2R_GREEN = 4, + RF_2T3R = 5, + RF_3T3R = 6, + RF_3T4R = 7, + RF_4T4R = 8, + + RF_MAX_TYPE = 0xF, /* u1Byte */ +}RT_RF_TYPE_DEF_E; + +int rtw_ch2freq(int chan); +int rtw_freq2ch(int freq); +bool rtw_chbw_to_freq_range(u8 ch, u8 bw, u8 offset, u32 *hi, u32 *lo); + +#define RTW_MODULE_RTL8821AE_HMC_M2 BIT0 /* RTL8821AE(HMC+M.2) */ +#define RTW_MODULE_RTL8821AU BIT1 /* RTL8821AU */ +#define RTW_MODULE_RTL8812AENF_NGFF BIT2 /* RTL8812AENF(8812AE+8761)_NGFF */ +#define RTW_MODULE_RTL8812AEBT_HMC BIT3 /* RTL8812AEBT(8812AE+8761)_HMC */ +#define RTW_MODULE_RTL8188EE_HMC_M2 BIT4 /* RTL8188EE(HMC+M.2) */ +#define RTW_MODULE_RTL8723BE_HMC_M2 BIT5 /* RTL8723BE(HMC+M.2) */ +#define RTW_MODULE_RTL8723BS_NGFF1216 BIT6 /* RTL8723BS(NGFF1216) */ +#define RTW_MODULE_RTL8192EEBT_HMC_M2 BIT7 /* RTL8192EEBT(8192EE+8761AU)_(HMC+M.2) */ + +#define IS_ALPHA2_NO_SPECIFIED(_alpha2) ((*((u16 *)(_alpha2))) == 0xFFFF) + +struct country_chplan { + char alpha2[2]; + u8 chplan; +#ifdef CONFIG_80211AC_VHT + u8 en_11ac; +#endif +#if RTW_DEF_MODULE_REGULATORY_CERT + u8 def_module_flags; /* RTW_MODULE_RTLXXX */ +#endif +}; + +#ifdef CONFIG_80211AC_VHT +#define COUNTRY_CHPLAN_EN_11AC(_ent) ((_ent)->en_11ac) +#else +#define COUNTRY_CHPLAN_EN_11AC(_ent) 0 +#endif + +#if RTW_DEF_MODULE_REGULATORY_CERT +#define COUNTRY_CHPLAN_DEF_MODULE_FALGS(_ent) ((_ent)->def_module_flags) +#else +#define COUNTRY_CHPLAN_DEF_MODULE_FALGS(_ent) 0 +#endif + +const struct country_chplan *rtw_get_chplan_from_country(const char *country_code); + +#define BB_GAIN_2G 0 +#ifdef CONFIG_IEEE80211_BAND_5GHZ +#define BB_GAIN_5GLB1 1 +#define BB_GAIN_5GLB2 2 +#define BB_GAIN_5GMB1 3 +#define BB_GAIN_5GMB2 4 +#define BB_GAIN_5GHB 5 +#endif + +#ifdef CONFIG_IEEE80211_BAND_5GHZ +#define BB_GAIN_NUM 6 +#else +#define BB_GAIN_NUM 1 +#endif + +int rtw_ch_to_bb_gain_sel(int ch); +void rtw_rf_set_tx_gain_offset(_adapter *adapter, u8 path, s8 offset); +void rtw_rf_apply_tx_gain_offset(_adapter *adapter, u8 ch); + +bool rtw_is_dfs_range(u32 hi, u32 lo); +bool rtw_is_dfs_ch(u8 ch, u8 bw, u8 offset); +bool rtw_is_long_cac_range(u32 hi, u32 lo); +bool rtw_is_long_cac_ch(u8 ch, u8 bw, u8 offset); + +#endif //_RTL8711_RF_H_ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_security.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_security.h new file mode 100644 index 000000000..72138cb95 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_security.h @@ -0,0 +1,486 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_SECURITY_H_ +#define __RTW_SECURITY_H_ + + +#define _NO_PRIVACY_ 0x0 +#define _WEP40_ 0x1 +#define _TKIP_ 0x2 +#define _TKIP_WTMIC_ 0x3 +#define _AES_ 0x4 +#define _WEP104_ 0x5 +#define _WEP_WPA_MIXED_ 0x07 // WEP + WPA +#define _SMS4_ 0x06 +#ifdef CONFIG_IEEE80211W +#define _BIP_ 0x8 +#endif //CONFIG_IEEE80211W +/* 802.11W use wrong key */ +#define IEEE80211W_RIGHT_KEY 0x0 +#define IEEE80211W_WRONG_KEY 0x1 +#define IEEE80211W_NO_KEY 0x2 + +#define is_wep_enc(alg) (((alg) == _WEP40_) || ((alg) == _WEP104_)) + +const char *security_type_str(u8 value); + +#define _WPA_IE_ID_ 0xdd +#define _WPA2_IE_ID_ 0x30 + +#define SHA256_MAC_LEN 32 +#define AES_BLOCK_SIZE 16 +#define AES_PRIV_SIZE (4 * 44) + +#define RTW_KEK_LEN 16 +#define RTW_KCK_LEN 16 +#define RTW_REPLAY_CTR_LEN 8 + +typedef enum { + ENCRYP_PROTOCOL_OPENSYS, //open system + ENCRYP_PROTOCOL_WEP, //WEP + ENCRYP_PROTOCOL_WPA, //WPA + ENCRYP_PROTOCOL_WPA2, //WPA2 + ENCRYP_PROTOCOL_WAPI, //WAPI: Not support in this version + ENCRYP_PROTOCOL_MAX +}ENCRYP_PROTOCOL_E; + + +#ifndef Ndis802_11AuthModeWPA2 +#define Ndis802_11AuthModeWPA2 (Ndis802_11AuthModeWPANone + 1) +#endif + +#ifndef Ndis802_11AuthModeWPA2PSK +#define Ndis802_11AuthModeWPA2PSK (Ndis802_11AuthModeWPANone + 2) +#endif + +union pn48 { + + u64 val; + +#ifdef CONFIG_LITTLE_ENDIAN + +struct { + u8 TSC0; + u8 TSC1; + u8 TSC2; + u8 TSC3; + u8 TSC4; + u8 TSC5; + u8 TSC6; + u8 TSC7; +} _byte_; + +#elif defined(CONFIG_BIG_ENDIAN) + +struct { + u8 TSC7; + u8 TSC6; + u8 TSC5; + u8 TSC4; + u8 TSC3; + u8 TSC2; + u8 TSC1; + u8 TSC0; +} _byte_; + +#endif + +}; + +union Keytype { + u8 skey[16]; + u32 lkey[4]; +}; + + +typedef struct _RT_PMKID_LIST +{ + u8 bUsed; + u8 Bssid[6]; + u8 PMKID[16]; + u8 SsidBuf[33]; + u8* ssid_octet; + u16 ssid_length; +} RT_PMKID_LIST, *PRT_PMKID_LIST; + + +struct security_priv +{ + u32 dot11AuthAlgrthm; // 802.11 auth, could be open, shared, 8021x and authswitch + u32 dot11PrivacyAlgrthm; // This specify the privacy for shared auth. algorithm. + + /* WEP */ + u32 dot11PrivacyKeyIndex; // this is only valid for legendary wep, 0~3 for key id. (tx key index) + union Keytype dot11DefKey[4]; // this is only valid for def. key + u32 dot11DefKeylen[4]; + u8 key_mask; /* use to restore wep key after hal_init */ + + u32 dot118021XGrpPrivacy; // This specify the privacy algthm. used for Grp key + u32 dot118021XGrpKeyid; // key id used for Grp Key ( tx key index) + union Keytype dot118021XGrpKey[4]; // 802.1x Group Key, for inx0 and inx1 + union Keytype dot118021XGrptxmickey[4]; + union Keytype dot118021XGrprxmickey[4]; + union pn48 dot11Grptxpn; // PN48 used for Grp Key xmit. + union pn48 dot11Grprxpn; // PN48 used for Grp Key recv. +#ifdef CONFIG_IEEE80211W + u32 dot11wBIPKeyid; // key id used for BIP Key ( tx key index) + union Keytype dot11wBIPKey[6]; // BIP Key, for index4 and index5 + union pn48 dot11wBIPtxpn; // PN48 used for Grp Key xmit. + union pn48 dot11wBIPrxpn; // PN48 used for Grp Key recv. +#endif //CONFIG_IEEE80211W +#ifdef CONFIG_AP_MODE + //extend security capabilities for AP_MODE + unsigned int dot8021xalg;//0:disable, 1:psk, 2:802.1x + unsigned int wpa_psk;//0:disable, bit(0): WPA, bit(1):WPA2 + unsigned int wpa_group_cipher; + unsigned int wpa2_group_cipher; + unsigned int wpa_pairwise_cipher; + unsigned int wpa2_pairwise_cipher; +#endif + + u8 wps_ie[MAX_WPS_IE_LEN];//added in assoc req + int wps_ie_len; + + + u8 binstallGrpkey; +#ifdef CONFIG_GTK_OL + u8 binstallKCK_KEK; +#endif //CONFIG_GTK_OL +#ifdef CONFIG_IEEE80211W + u8 binstallBIPkey; +#endif //CONFIG_IEEE80211W + u8 busetkipkey; + //_timer tkip_timer; + u8 bcheck_grpkey; + u8 bgrpkey_handshake; + + //u8 packet_cnt;//unused, removed + + s32 sw_encrypt;//from registry_priv + s32 sw_decrypt;//from registry_priv + + s32 hw_decrypted;//if the rx packets is hw_decrypted==_FALSE, it means the hw has not been ready. + + + //keeps the auth_type & enc_status from upper layer ioctl(wpa_supplicant or wzc) + u32 ndisauthtype; // NDIS_802_11_AUTHENTICATION_MODE + u32 ndisencryptstatus; // NDIS_802_11_ENCRYPTION_STATUS + + NDIS_802_11_WEP ndiswep; +#ifdef PLATFORM_WINDOWS + u8 KeyMaterial[16];// variable length depending on above field. +#endif + + u8 assoc_info[600]; + u8 szofcapability[256]; //for wpa2 usage + u8 oidassociation[512]; //for wpa/wpa2 usage + u8 authenticator_ie[256]; //store ap security information element + u8 supplicant_ie[256]; //store sta security information element + + + //for tkip countermeasure + u32 last_mic_err_time; + u8 btkip_countermeasure; + u8 btkip_wait_report; + u32 btkip_countermeasure_time; + + //--------------------------------------------------------------------------- + // For WPA2 Pre-Authentication. + //--------------------------------------------------------------------------- + //u8 RegEnablePreAuth; // Default value: Pre-Authentication enabled or not, from registry "EnablePreAuth". Added by Annie, 2005-11-01. + //u8 EnablePreAuthentication; // Current Value: Pre-Authentication enabled or not. + RT_PMKID_LIST PMKIDList[NUM_PMKID_CACHE]; // Renamed from PreAuthKey[NUM_PRE_AUTH_KEY]. Annie, 2006-10-13. + u8 PMKIDIndex; + //u32 PMKIDCount; // Added by Annie, 2006-10-13. + //u8 szCapability[256]; // For WPA2-PSK using zero-config, by Annie, 2005-09-20. + + u8 bWepDefaultKeyIdxSet; + +#define DBG_SW_SEC_CNT +#ifdef DBG_SW_SEC_CNT + u64 wep_sw_enc_cnt_bc; + u64 wep_sw_enc_cnt_mc; + u64 wep_sw_enc_cnt_uc; + u64 wep_sw_dec_cnt_bc; + u64 wep_sw_dec_cnt_mc; + u64 wep_sw_dec_cnt_uc; + + u64 tkip_sw_enc_cnt_bc; + u64 tkip_sw_enc_cnt_mc; + u64 tkip_sw_enc_cnt_uc; + u64 tkip_sw_dec_cnt_bc; + u64 tkip_sw_dec_cnt_mc; + u64 tkip_sw_dec_cnt_uc; + + u64 aes_sw_enc_cnt_bc; + u64 aes_sw_enc_cnt_mc; + u64 aes_sw_enc_cnt_uc; + u64 aes_sw_dec_cnt_bc; + u64 aes_sw_dec_cnt_mc; + u64 aes_sw_dec_cnt_uc; +#endif /* DBG_SW_SEC_CNT */ +}; + +struct rtw_sha256_state { + u64 length; + u32 state[8], curlen; + u8 buf[64]; +}; + +#define GET_ENCRY_ALGO(psecuritypriv, psta, encry_algo, bmcst)\ +do{\ + switch(psecuritypriv->dot11AuthAlgrthm)\ + {\ + case dot11AuthAlgrthm_Open:\ + case dot11AuthAlgrthm_Shared:\ + case dot11AuthAlgrthm_Auto:\ + encry_algo = (u8)psecuritypriv->dot11PrivacyAlgrthm;\ + break;\ + case dot11AuthAlgrthm_8021X:\ + if(bmcst)\ + encry_algo = (u8)psecuritypriv->dot118021XGrpPrivacy;\ + else\ + encry_algo =(u8) psta->dot118021XPrivacy;\ + break;\ + case dot11AuthAlgrthm_WAPI:\ + encry_algo = (u8)psecuritypriv->dot11PrivacyAlgrthm;\ + break;\ + }\ +}while(0) + +#define _AES_IV_LEN_ 8 + +#define SET_ICE_IV_LEN( iv_len, icv_len, encrypt)\ +do{\ + switch(encrypt)\ + {\ + case _WEP40_:\ + case _WEP104_:\ + iv_len = 4;\ + icv_len = 4;\ + break;\ + case _TKIP_:\ + iv_len = 8;\ + icv_len = 4;\ + break;\ + case _AES_:\ + iv_len = 8;\ + icv_len = 8;\ + break;\ + case _SMS4_:\ + iv_len = 18;\ + icv_len = 16;\ + break;\ + default:\ + iv_len = 0;\ + icv_len = 0;\ + break;\ + }\ +}while(0) + + +#define GET_TKIP_PN(iv,dot11txpn)\ +do{\ + dot11txpn._byte_.TSC0=iv[2];\ + dot11txpn._byte_.TSC1=iv[0];\ + dot11txpn._byte_.TSC2=iv[4];\ + dot11txpn._byte_.TSC3=iv[5];\ + dot11txpn._byte_.TSC4=iv[6];\ + dot11txpn._byte_.TSC5=iv[7];\ +}while(0) + + +#define ROL32( A, n ) ( ((A) << (n)) | ( ((A)>>(32-(n))) & ( (1UL << (n)) - 1 ) ) ) +#define ROR32( A, n ) ROL32( (A), 32-(n) ) + +struct mic_data +{ + u32 K0, K1; // Key + u32 L, R; // Current state + u32 M; // Message accumulator (single word) + u32 nBytesInM; // # bytes in M +}; + +extern const u32 Te0[256]; +extern const u32 Te1[256]; +extern const u32 Te2[256]; +extern const u32 Te3[256]; +extern const u32 Te4[256]; +extern const u32 Td0[256]; +extern const u32 Td1[256]; +extern const u32 Td2[256]; +extern const u32 Td3[256]; +extern const u32 Td4[256]; +extern const u32 rcon[10]; +extern const u8 Td4s[256]; +extern const u8 rcons[10]; + +#define RCON(i) (rcons[(i)] << 24) + +static inline u32 rotr(u32 val, int bits) +{ + return (val >> bits) | (val << (32 - bits)); +} + +#define TE0(i) Te0[((i) >> 24) & 0xff] +#define TE1(i) rotr(Te0[((i) >> 16) & 0xff], 8) +#define TE2(i) rotr(Te0[((i) >> 8) & 0xff], 16) +#define TE3(i) rotr(Te0[(i) & 0xff], 24) +#define TE41(i) ((Te0[((i) >> 24) & 0xff] << 8) & 0xff000000) +#define TE42(i) (Te0[((i) >> 16) & 0xff] & 0x00ff0000) +#define TE43(i) (Te0[((i) >> 8) & 0xff] & 0x0000ff00) +#define TE44(i) ((Te0[(i) & 0xff] >> 8) & 0x000000ff) +#define TE421(i) ((Te0[((i) >> 16) & 0xff] << 8) & 0xff000000) +#define TE432(i) (Te0[((i) >> 8) & 0xff] & 0x00ff0000) +#define TE443(i) (Te0[(i) & 0xff] & 0x0000ff00) +#define TE414(i) ((Te0[((i) >> 24) & 0xff] >> 8) & 0x000000ff) +#define TE4(i) ((Te0[(i)] >> 8) & 0x000000ff) + +#define TD0(i) Td0[((i) >> 24) & 0xff] +#define TD1(i) rotr(Td0[((i) >> 16) & 0xff], 8) +#define TD2(i) rotr(Td0[((i) >> 8) & 0xff], 16) +#define TD3(i) rotr(Td0[(i) & 0xff], 24) +#define TD41(i) (Td4s[((i) >> 24) & 0xff] << 24) +#define TD42(i) (Td4s[((i) >> 16) & 0xff] << 16) +#define TD43(i) (Td4s[((i) >> 8) & 0xff] << 8) +#define TD44(i) (Td4s[(i) & 0xff]) +#define TD0_(i) Td0[(i) & 0xff] +#define TD1_(i) rotr(Td0[(i) & 0xff], 8) +#define TD2_(i) rotr(Td0[(i) & 0xff], 16) +#define TD3_(i) rotr(Td0[(i) & 0xff], 24) + +#define GETU32(pt) (((u32)(pt)[0] << 24) ^ ((u32)(pt)[1] << 16) ^ \ + ((u32)(pt)[2] << 8) ^ ((u32)(pt)[3])) + +#define PUTU32(ct, st) { \ +(ct)[0] = (u8)((st) >> 24); (ct)[1] = (u8)((st) >> 16); \ +(ct)[2] = (u8)((st) >> 8); (ct)[3] = (u8)(st); } + +#define WPA_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \ + (((u32) (a)[2]) << 8) | ((u32) (a)[3])) + +#define WPA_PUT_LE16(a, val) \ + do { \ + (a)[1] = ((u16) (val)) >> 8; \ + (a)[0] = ((u16) (val)) & 0xff; \ + } while (0) + +#define WPA_PUT_BE32(a, val) \ + do { \ + (a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \ + (a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \ + (a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \ + (a)[3] = (u8) (((u32) (val)) & 0xff); \ + } while (0) + +#define WPA_PUT_BE64(a, val) \ + do { \ + (a)[0] = (u8) (((u64) (val)) >> 56); \ + (a)[1] = (u8) (((u64) (val)) >> 48); \ + (a)[2] = (u8) (((u64) (val)) >> 40); \ + (a)[3] = (u8) (((u64) (val)) >> 32); \ + (a)[4] = (u8) (((u64) (val)) >> 24); \ + (a)[5] = (u8) (((u64) (val)) >> 16); \ + (a)[6] = (u8) (((u64) (val)) >> 8); \ + (a)[7] = (u8) (((u64) (val)) & 0xff); \ + } while (0) + +/* ===== start - public domain SHA256 implementation ===== */ + +/* This is based on SHA256 implementation in LibTomCrypt that was released into + * public domain by Tom St Denis. */ + +/* the K array */ +static const unsigned long K[64] = { + 0x428a2f98UL, 0x71374491UL, 0xb5c0fbcfUL, 0xe9b5dba5UL, 0x3956c25bUL, + 0x59f111f1UL, 0x923f82a4UL, 0xab1c5ed5UL, 0xd807aa98UL, 0x12835b01UL, + 0x243185beUL, 0x550c7dc3UL, 0x72be5d74UL, 0x80deb1feUL, 0x9bdc06a7UL, + 0xc19bf174UL, 0xe49b69c1UL, 0xefbe4786UL, 0x0fc19dc6UL, 0x240ca1ccUL, + 0x2de92c6fUL, 0x4a7484aaUL, 0x5cb0a9dcUL, 0x76f988daUL, 0x983e5152UL, + 0xa831c66dUL, 0xb00327c8UL, 0xbf597fc7UL, 0xc6e00bf3UL, 0xd5a79147UL, + 0x06ca6351UL, 0x14292967UL, 0x27b70a85UL, 0x2e1b2138UL, 0x4d2c6dfcUL, + 0x53380d13UL, 0x650a7354UL, 0x766a0abbUL, 0x81c2c92eUL, 0x92722c85UL, + 0xa2bfe8a1UL, 0xa81a664bUL, 0xc24b8b70UL, 0xc76c51a3UL, 0xd192e819UL, + 0xd6990624UL, 0xf40e3585UL, 0x106aa070UL, 0x19a4c116UL, 0x1e376c08UL, + 0x2748774cUL, 0x34b0bcb5UL, 0x391c0cb3UL, 0x4ed8aa4aUL, 0x5b9cca4fUL, + 0x682e6ff3UL, 0x748f82eeUL, 0x78a5636fUL, 0x84c87814UL, 0x8cc70208UL, + 0x90befffaUL, 0xa4506cebUL, 0xbef9a3f7UL, 0xc67178f2UL +}; + + +/* Various logical functions */ +#define RORc(x, y) \ +( ((((unsigned long) (x) & 0xFFFFFFFFUL) >> (unsigned long) ((y) & 31)) | \ + ((unsigned long) (x) << (unsigned long) (32 - ((y) & 31)))) & 0xFFFFFFFFUL) +#define Ch(x,y,z) (z ^ (x & (y ^ z))) +#define Maj(x,y,z) (((x | y) & z) | (x & y)) +#define S(x, n) RORc((x), (n)) +#define R(x, n) (((x)&0xFFFFFFFFUL)>>(n)) +#define Sigma0(x) (S(x, 2) ^ S(x, 13) ^ S(x, 22)) +#define Sigma1(x) (S(x, 6) ^ S(x, 11) ^ S(x, 25)) +#define Gamma0(x) (S(x, 7) ^ S(x, 18) ^ R(x, 3)) +#define Gamma1(x) (S(x, 17) ^ S(x, 19) ^ R(x, 10)) +#ifndef MIN +#define MIN(x, y) (((x) < (y)) ? (x) : (y)) +#endif +#ifdef CONFIG_IEEE80211W +int omac1_aes_128(u8 *key, u8 *data, size_t data_len, u8 *mac); +#endif //CONFIG_IEEE80211W +void rtw_secmicsetkey(struct mic_data *pmicdata, u8 * key ); +void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b ); +void rtw_secmicappend(struct mic_data *pmicdata, u8 * src, u32 nBytes ); +void rtw_secgetmic(struct mic_data *pmicdata, u8 * dst ); + +void rtw_seccalctkipmic( + u8 * key, + u8 *header, + u8 *data, + u32 data_len, + u8 *Miccode, + u8 priority); + +u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe); +u32 rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe); +void rtw_wep_encrypt(_adapter *padapter, u8 *pxmitframe); + +u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe); +u32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe); +void rtw_wep_decrypt(_adapter *padapter, u8 *precvframe); +#ifdef CONFIG_IEEE80211W +u32 rtw_BIP_verify(_adapter *padapter, u8 *precvframe); +#endif //CONFIG_IEEE80211W +#ifdef CONFIG_TDLS +void wpa_tdls_generate_tpk(_adapter *padapter, PVOID sta); +int wpa_tdls_ftie_mic(u8 *kck, u8 trans_seq, + u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie, + u8 *mic); +int wpa_tdls_teardown_ftie_mic(u8 *kck, u8 *lnkid, u16 reason, + u8 dialog_token, u8 trans_seq, u8 *ftie, u8 *mic); +int tdls_verify_mic(u8 *kck, u8 trans_seq, + u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie); +#endif //CONFIG_TDLS + +void rtw_use_tkipkey_handler(RTW_TIMER_HDL_ARGS); + +void rtw_sec_restore_wep_key(_adapter *adapter); +u8 rtw_handle_tkip_countermeasure(_adapter* adapter, const char *caller); + + +#endif //__RTL871X_SECURITY_H_ diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_sreset.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_sreset.h new file mode 100644 index 000000000..4a225589a --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_sreset.h @@ -0,0 +1,61 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_SRESET_H_ +#define _RTW_SRESET_H_ + +//#include + +enum { + SRESET_TGP_NULL = 0, + SRESET_TGP_XMIT_STATUS = 1, + SRESET_TGP_LINK_STATUS = 2, +}; + +struct sreset_priv { + _mutex silentreset_mutex; + u8 silent_reset_inprogress; + u8 Wifi_Error_Status; + unsigned long last_tx_time; + unsigned long last_tx_complete_time; + + s32 dbg_trigger_point; +}; + + + +#define WIFI_STATUS_SUCCESS 0 +#define USB_VEN_REQ_CMD_FAIL BIT0 +#define USB_READ_PORT_FAIL BIT1 +#define USB_WRITE_PORT_FAIL BIT2 +#define WIFI_MAC_TXDMA_ERROR BIT3 +#define WIFI_TX_HANG BIT4 +#define WIFI_RX_HANG BIT5 +#define WIFI_IF_NOT_EXIST BIT6 + +void sreset_init_value(_adapter *padapter); +void sreset_reset_value(_adapter *padapter); +u8 sreset_get_wifi_status(_adapter *padapter); +void sreset_set_wifi_error_status(_adapter *padapter, u32 status); +void sreset_set_trigger_point(_adapter *padapter, s32 tgp); +bool sreset_inprogress(_adapter *padapter); +void sreset_reset(_adapter *padapter); + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_tdls.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_tdls.h new file mode 100644 index 000000000..42795cee3 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_tdls.h @@ -0,0 +1,175 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_TDLS_H_ +#define __RTW_TDLS_H_ + + +#ifdef CONFIG_TDLS +/* TDLS STA state */ + + +/* TDLS Diect Link Establishment */ +#define TDLS_STATE_NONE 0x00000000 /* Default state */ +#define TDLS_INITIATOR_STATE BIT(28) /* 0x10000000 */ +#define TDLS_RESPONDER_STATE BIT(29) /* 0x20000000 */ +#define TDLS_LINKED_STATE BIT(30) /* 0x40000000 */ +/* TDLS PU Buffer STA */ +#define TDLS_WAIT_PTR_STATE BIT(24) /* 0x01000000 */ /* Waiting peer's TDLS_PEER_TRAFFIC_RESPONSE frame */ +/* TDLS Check ALive */ +#define TDLS_ALIVE_STATE BIT(20) /* 0x00100000 */ /* Check if peer sta is alived. */ +/* TDLS Channel Switch */ +#define TDLS_CH_SWITCH_PREPARE_STATE BIT(15) /* 0x00008000 */ +#define TDLS_CH_SWITCH_ON_STATE BIT(16) /* 0x00010000 */ +#define TDLS_PEER_AT_OFF_STATE BIT(17) /* 0x00020000 */ /* Could send pkt on target ch */ +#define TDLS_CH_SW_INITIATOR_STATE BIT(18) /* 0x00040000 */ /* Avoid duplicated or unconditional ch. switch rsp. */ +#define TDLS_WAIT_CH_RSP_STATE BIT(19) /* 0x00080000 */ /* Wait Ch. response as we are TDLS channel switch initiator */ + + +#define TDLS_TPK_RESEND_COUNT 86400 /*Unit: seconds */ +#define TDLS_CH_SWITCH_TIME 15 +#define TDLS_CH_SWITCH_TIMEOUT 30 +#define TDLS_CH_SWITCH_OPER_OFFLOAD_TIMEOUT 10 +#define TDLS_SIGNAL_THRESH 0x20 +#define TDLS_WATCHDOG_PERIOD 10 /* Periodically sending tdls discovery request in TDLS_WATCHDOG_PERIOD * 2 sec */ +#define TDLS_HANDSHAKE_TIME 3000 +#define TDLS_PTI_TIME 7000 + +#define TDLS_CH_SW_STAY_ON_BASE_CHNL_TIMEOUT 20 /* ms */ +#define TDLS_CH_SW_MONITOR_TIMEOUT 2000 /*ms */ + +#define TDLS_MIC_LEN 16 +#define WPA_NONCE_LEN 32 +#define TDLS_TIMEOUT_LEN 4 + +enum TDLS_CH_SW_CHNL{ + TDLS_CH_SW_BASE_CHNL = 0, + TDLS_CH_SW_OFF_CHNL +}; + +struct wpa_tdls_ftie { + u8 ie_type; /* FTIE */ + u8 ie_len; + u8 mic_ctrl[2]; + u8 mic[TDLS_MIC_LEN]; + u8 Anonce[WPA_NONCE_LEN]; /* Responder Nonce in TDLS */ + u8 Snonce[WPA_NONCE_LEN]; /* Initiator Nonce in TDLS */ + /* followed by optional elements */ +} ; + +struct wpa_tdls_lnkid { + u8 ie_type; /* Link Identifier IE */ + u8 ie_len; + u8 bssid[ETH_ALEN]; + u8 init_sta[ETH_ALEN]; + u8 resp_sta[ETH_ALEN]; +} ; + +static u8 TDLS_RSNIE[20]={ 0x01, 0x00, /* Version shall be set to 1 */ + 0x00, 0x0f, 0xac, 0x07, /* Group sipher suite */ + 0x01, 0x00, /* Pairwise cipher suite count */ + 0x00, 0x0f, 0xac, 0x04, /* Pairwise cipher suite list; CCMP only */ + 0x01, 0x00, /* AKM suite count */ + 0x00, 0x0f, 0xac, 0x07, /* TPK Handshake */ + 0x0c, 0x02, + /* PMKID shall not be present */ + }; + +static u8 TDLS_WMMIE[]={0x00, 0x50, 0xf2, 0x02, 0x00, 0x01, 0x00}; /* Qos info all set zero */ + +static u8 TDLS_WMM_PARAM_IE[] = {0x00, 0x00, 0x03, 0xa4, 0x00, 0x00, 0x27, 0xa4, 0x00, 0x00, 0x42, 0x43, 0x5e, 0x00, 0x62, 0x32, 0x2f, 0x00}; + +static u8 TDLS_EXT_CAPIE[] = {0x00, 0x00, 0x00, 0x50, 0x20, 0x00, 0x00, 0x00}; /* bit(28), bit(30), bit(37) */ + +/* SRC: Supported Regulatory Classes */ +static u8 TDLS_SRC[] = { 0x01, 0x01, 0x02, 0x03, 0x04, 0x0c, 0x16, 0x17, 0x18, 0x19, 0x1b, 0x1c, 0x1d, 0x1e, 0x20, 0x21 }; + +int check_ap_tdls_prohibited(u8 *pframe, u8 pkt_len); +int check_ap_tdls_ch_switching_prohibited(u8 *pframe, u8 pkt_len); + +u8 rtw_tdls_is_setup_allowed(_adapter *padapter); +#ifdef CONFIG_TDLS_CH_SW +u8 rtw_tdls_is_chsw_allowed(_adapter *padapter); +#endif + +void rtw_reset_tdls_info(_adapter* padapter); +int rtw_init_tdls_info(_adapter* padapter); +void rtw_free_tdls_info(struct tdls_info *ptdlsinfo); +int issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, unsigned char *da, unsigned int power_mode, int try_cnt, int wait_ms); +void rtw_init_tdls_timer(_adapter *padapter, struct sta_info *psta); +void rtw_free_tdls_timer(struct sta_info *psta); +void free_tdls_sta(_adapter *padapter, struct sta_info *ptdls_sta); + +#ifdef CONFIG_TDLS_CH_SW +void rtw_tdls_set_ch_sw_oper_control(_adapter *padapter, u8 enable); +void rtw_tdls_ch_sw_back_to_base_chnl(_adapter *padapter); +s32 rtw_tdls_do_ch_sw(_adapter *padapter, struct sta_info *ptdls_sta, u8 chnl_type, u8 channel, u8 channel_offset, u16 bwmode, u16 ch_switch_time); +void rtw_tdls_chsw_oper_done(_adapter* padapter); +#endif + +#ifdef CONFIG_WFD +int issue_tunneled_probe_req(_adapter *padapter); +int issue_tunneled_probe_rsp(_adapter *padapter, union recv_frame *precv_frame); +#endif /* CONFIG_WFD */ +int issue_tdls_dis_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt); +int issue_tdls_setup_req(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wait_ack); +int issue_tdls_setup_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt); +int issue_tdls_setup_cfm(_adapter *padapter, struct tdls_txmgmt *ptxmgmt); +int issue_tdls_dis_rsp(_adapter * padapter, struct tdls_txmgmt *ptxmgmt, u8 privacy); +int issue_tdls_teardown(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, u8 wait_ack); +int issue_tdls_peer_traffic_rsp(_adapter *padapter, struct sta_info *psta, struct tdls_txmgmt *ptxmgmt); +int issue_tdls_peer_traffic_indication(_adapter *padapter, struct sta_info *psta); +#ifdef CONFIG_TDLS_CH_SW +int issue_tdls_ch_switch_req(_adapter *padapter, struct sta_info *ptdls_sta); +int issue_tdls_ch_switch_rsp(_adapter *padapter, struct tdls_txmgmt *ptxmgmt, int wait_ack); +#endif +sint On_TDLS_Dis_Rsp(_adapter *adapter, union recv_frame *precv_frame); +sint On_TDLS_Setup_Req(_adapter *adapter, union recv_frame *precv_frame); +int On_TDLS_Setup_Rsp(_adapter *adapter, union recv_frame *precv_frame); +int On_TDLS_Setup_Cfm(_adapter *adapter, union recv_frame *precv_frame); +int On_TDLS_Dis_Req(_adapter *adapter, union recv_frame *precv_frame); +int On_TDLS_Teardown(_adapter *adapter, union recv_frame *precv_frame); +int On_TDLS_Peer_Traffic_Indication(_adapter *adapter, union recv_frame *precv_frame); +int On_TDLS_Peer_Traffic_Rsp(_adapter *adapter, union recv_frame *precv_frame); +#ifdef CONFIG_TDLS_CH_SW +sint On_TDLS_Ch_Switch_Req(_adapter *adapter, union recv_frame *precv_frame); +sint On_TDLS_Ch_Switch_Rsp(_adapter *adapter, union recv_frame *precv_frame); +void rtw_build_tdls_ch_switch_req_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); +void rtw_build_tdls_ch_switch_rsp_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); +#endif +void rtw_build_tdls_setup_req_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); +void rtw_build_tdls_setup_rsp_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); +void rtw_build_tdls_setup_cfm_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); +void rtw_build_tdls_teardown_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); +void rtw_build_tdls_dis_req_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); +void rtw_build_tdls_dis_rsp_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt, u8 privacy); +void rtw_build_tdls_peer_traffic_rsp_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); +void rtw_build_tdls_peer_traffic_indication_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, struct tdls_txmgmt *ptxmgmt); +void rtw_build_tunneled_probe_req_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe); +void rtw_build_tunneled_probe_rsp_ies(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe); + +u8 update_sgi_tdls(_adapter *padapter, struct sta_info *psta); +u32 update_mask_tdls(_adapter *padapter, struct sta_info *psta); +int rtw_tdls_is_driver_setup(_adapter *padapter); +void rtw_tdls_set_key(_adapter *padapter, struct sta_info *ptdls_sta); +const char * rtw_tdls_action_txt(enum TDLS_ACTION_FIELD action); +#endif /* CONFIG_TDLS */ + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_version.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_version.h new file mode 100644 index 000000000..e4510e151 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_version.h @@ -0,0 +1,2 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#define DRIVERVERSION "v4.3.23.6_20964.20170110" diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_vht.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_vht.h new file mode 100644 index 000000000..def791ab6 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_vht.h @@ -0,0 +1,143 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _RTW_VHT_H_ +#define _RTW_VHT_H_ + +#define LDPC_VHT_ENABLE_RX BIT0 +#define LDPC_VHT_ENABLE_TX BIT1 +#define LDPC_VHT_TEST_TX_ENABLE BIT2 +#define LDPC_VHT_CAP_TX BIT3 + +#define STBC_VHT_ENABLE_RX BIT0 +#define STBC_VHT_ENABLE_TX BIT1 +#define STBC_VHT_TEST_TX_ENABLE BIT2 +#define STBC_VHT_CAP_TX BIT3 + +#define BEAMFORMING_VHT_BEAMFORMER_ENABLE BIT0 // Declare our NIC supports beamformer +#define BEAMFORMING_VHT_BEAMFORMEE_ENABLE BIT1 // Declare our NIC supports beamformee +#define BEAMFORMING_VHT_MU_MIMO_AP_ENABLE BIT2 /*Declare our NIC support MU-MIMO AP mode*/ +#define BEAMFORMING_VHT_MU_MIMO_STA_ENABLE BIT3 /*Declare our NIC support MU-MIMO STA mode*/ +#define BEAMFORMING_VHT_BEAMFORMER_TEST BIT4 /*Transmiting Beamforming no matter the target supports it or not*/ +#define BEAMFORMING_VHT_BEAMFORMER_STS_CAP (BIT8|BIT9|BIT10) /*Asoc rsp cap*/ +#define BEAMFORMING_VHT_BEAMFORMEE_SOUND_DIM (BIT12|BIT13|BIT14) /*Asoc rsp cap*/ + + +//VHT capability info +#define SET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 2, _val) +#define SET_VHT_CAPABILITY_ELE_CHL_WIDTH(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart, 2, 2, _val) +#define SET_VHT_CAPABILITY_ELE_RX_LDPC(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart, 4, 1, _val) +#define SET_VHT_CAPABILITY_ELE_SHORT_GI80M(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart, 5, 1, _val) +#define SET_VHT_CAPABILITY_ELE_SHORT_GI160M(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart, 6, 1, _val) +#define SET_VHT_CAPABILITY_ELE_TX_STBC(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart, 7, 1, _val) +#define SET_VHT_CAPABILITY_ELE_RX_STBC(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+1, 0, 3, _val) +#define SET_VHT_CAPABILITY_ELE_SU_BFER(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+1, 3, 1, _val) +#define SET_VHT_CAPABILITY_ELE_SU_BFEE(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+1, 4, 1, _val) +#define SET_VHT_CAPABILITY_ELE_BFER_ANT_SUPP(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+1, 5, 3, _val) +#define SET_VHT_CAPABILITY_ELE_SOUNDING_DIMENSIONS(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 0, 3, _val) + +#define SET_VHT_CAPABILITY_ELE_MU_BFER(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 3, 1, _val) +#define SET_VHT_CAPABILITY_ELE_MU_BFEE(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 4, 1, _val) +#define SET_VHT_CAPABILITY_ELE_TXOP_PS(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 5, 1, _val) +#define SET_VHT_CAPABILITY_ELE_HTC_VHT(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 6, 1, _val) +#define SET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(_pEleStart, _val) SET_BITS_TO_LE_2BYTE((_pEleStart)+2, 7, 3, _val) //B23~B25 +#define SET_VHT_CAPABILITY_ELE_LINK_ADAPTION(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+2, 2, 2, _val) +#define SET_VHT_CAPABILITY_ELE_MCS_RX_MAP(_pEleStart, _val) SET_BITS_TO_LE_2BYTE((_pEleStart)+4, 0, 16, _val) /* B0~B15 indicate Rx MCS MAP, we write 0 to indicate MCS0~7. by page */ +#define SET_VHT_CAPABILITY_ELE_MCS_RX_HIGHEST_RATE(_pEleStart, _val) SET_BITS_TO_LE_2BYTE((_pEleStart)+6, 0, 13, _val) +#define SET_VHT_CAPABILITY_ELE_MCS_TX_MAP(_pEleStart, _val) SET_BITS_TO_LE_2BYTE((_pEleStart)+8, 0, 16, _val) /* B0~B15 indicate Tx MCS MAP, we write 0 to indicate MCS0~7. by page */ +#define SET_VHT_CAPABILITY_ELE_MCS_TX_HIGHEST_RATE(_pEleStart, _val) SET_BITS_TO_LE_2BYTE((_pEleStart)+10, 0, 13, _val) + + +#define GET_VHT_CAPABILITY_ELE_MAX_MPDU_LENGTH(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 0, 2) +#define GET_VHT_CAPABILITY_ELE_CHL_WIDTH(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 2, 2) +#define GET_VHT_CAPABILITY_ELE_RX_LDPC(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 4, 1) +#define GET_VHT_CAPABILITY_ELE_SHORT_GI80M(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 5, 1) +#define GET_VHT_CAPABILITY_ELE_SHORT_GI160M(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 6, 1) +#define GET_VHT_CAPABILITY_ELE_TX_STBC(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 7, 1) +#define GET_VHT_CAPABILITY_ELE_RX_STBC(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+1, 0, 3) +#define GET_VHT_CAPABILITY_ELE_SU_BFER(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+1, 3, 1) +#define GET_VHT_CAPABILITY_ELE_SU_BFEE(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+1, 4, 1) +/*phydm-beamforming*/ +#define GET_VHT_CAPABILITY_ELE_SU_BFEE_STS_CAP(_pEleStart) LE_BITS_TO_2BYTE((_pEleStart)+1, 5, 3) +#define GET_VHT_CAPABILITY_ELE_SU_BFER_SOUND_DIM_NUM(_pEleStart) LE_BITS_TO_2BYTE((_pEleStart)+2, 0, 3) +#define GET_VHT_CAPABILITY_ELE_TXOP_PS(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+2, 5, 1) +#define GET_VHT_CAPABILITY_ELE_MAX_RXAMPDU_FACTOR(_pEleStart) LE_BITS_TO_2BYTE((_pEleStart)+2, 7, 3) +#define GET_VHT_CAPABILITY_ELE_RX_MCS(_pEleStart) ((_pEleStart)+4) +#define GET_VHT_CAPABILITY_ELE_MCS_RX_HIGHEST_RATE(_pEleStart) LE_BITS_TO_2BYTE((_pEleStart)+6, 0, 13) +#define GET_VHT_CAPABILITY_ELE_TX_MCS(_pEleStart) ((_pEleStart)+8) +#define GET_VHT_CAPABILITY_ELE_MCS_TX_HIGHEST_RATE(_pEleStart) LE_BITS_TO_2BYTE((_pEleStart)+10, 0, 13) + + +//VHT Operation Information Element +#define SET_VHT_OPERATION_ELE_CHL_WIDTH(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 8, _val) +#define SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ1(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart+1, 0, 8, _val) +#define SET_VHT_OPERATION_ELE_CHL_CENTER_FREQ2(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart+2, 0, 8, _val) +#define SET_VHT_OPERATION_ELE_BASIC_MCS_SET(_pEleStart, _val) SET_BITS_TO_LE_2BYTE((_pEleStart)+3, 0, 16, _val) + +#define GET_VHT_OPERATION_ELE_CHL_WIDTH(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart,0,8) +#define GET_VHT_OPERATION_ELE_CENTER_FREQ1(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+1,0,8) +#define GET_VHT_OPERATION_ELE_CENTER_FREQ2(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+2,0,8) + +//VHT Operating Mode +#define SET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart, 0, 2, _val) +#define SET_VHT_OPERATING_MODE_FIELD_RX_NSS(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart, 4, 3, _val) +#define SET_VHT_OPERATING_MODE_FIELD_RX_NSS_TYPE(_pEleStart, _val) SET_BITS_TO_LE_1BYTE(_pEleStart, 7, 1, _val) +#define GET_VHT_OPERATING_MODE_FIELD_CHNL_WIDTH(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 0, 2) +#define GET_VHT_OPERATING_MODE_FIELD_RX_NSS(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 4, 3) +#define GET_VHT_OPERATING_MODE_FIELD_RX_NSS_TYPE(_pEleStart) LE_BITS_TO_1BYTE(_pEleStart, 7, 1) + +#define SET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(_pEleStart, _val) SET_BITS_TO_LE_1BYTE((_pEleStart)+7, 6, 1, _val) +#define GET_EXT_CAPABILITY_ELE_OP_MODE_NOTIF(_pEleStart) LE_BITS_TO_1BYTE((_pEleStart)+7, 6, 1) + +struct vht_priv +{ + u8 vht_option; + + u8 ldpc_cap; + u8 stbc_cap; + u16 beamform_cap; + + u8 sgi_80m;//short GI + u8 ampdu_len; + + u8 vht_op_mode_notify; + u8 vht_highest_rate; + u8 vht_mcs_map[2]; + + u8 vht_cap[32]; +}; + +u8 rtw_get_vht_highest_rate(u8 *pvht_mcs_map); +u16 rtw_vht_mcs_to_data_rate(u8 bw, u8 short_GI, u8 vht_mcs_rate); +u64 rtw_vht_rate_to_bitmap(u8 *pVHTRate); +void rtw_vht_use_default_setting(_adapter *padapter); +u32 rtw_build_vht_operation_ie(_adapter *padapter, u8 *pbuf, u8 channel); +u32 rtw_build_vht_op_mode_notify_ie(_adapter *padapter, u8 *pbuf, u8 bw); +u32 rtw_build_vht_cap_ie(_adapter *padapter, u8 *pbuf); +void update_sta_vht_info_apmode(_adapter *padapter, PVOID psta); +void update_hw_vht_param(_adapter *padapter); +void VHT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +void VHT_operation_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE); +void rtw_process_vht_op_mode_notify(_adapter *padapter, u8 *pframe, PVOID sta); +u32 rtw_restructure_vht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len); +void VHTOnAssocRsp(_adapter *padapter); +u8 rtw_vht_mcsmap_to_nss(u8 *pvht_mcs_map); + +#endif //_RTW_VHT_H_ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_wapi.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_wapi.h new file mode 100644 index 000000000..32bd96516 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/rtw_wapi.h @@ -0,0 +1,223 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __INC_WAPI_H +#define __INC_WAPI_H + + +#define CONFIG_WAPI_SW_SMS4 +#define WAPI_DEBUG + +#define SMS4_MIC_LEN 16 +#define WAPI_EXT_LEN 18 +#define MAX_WAPI_IE_LEN 256 +#define sMacHdrLng 24 // octets in data header, no WEP + +#ifdef WAPI_DEBUG + +/* WAPI trace debug */ +extern u32 wapi_debug_component; + +static inline void dump_buf(u8 *buf, u32 len) +{ + u32 i; + printk("-----------------Len %d----------------\n", len); + for(i=0; i4096), HW will execute + // memoryR/W CRC error. And then all DMA fetch will fail. We must decrease descriptor + // number or enlarge descriptor size as 64 bytes. + unsigned int txdw12; + unsigned int txdw13; + unsigned int txdw14; + unsigned int txdw15; +#endif +}; +#endif + +union txdesc { + struct tx_desc txdesc; + unsigned int value[TXDESC_SIZE>>2]; +}; + +#ifdef CONFIG_PCI_HCI +#define PCI_MAX_TX_QUEUE_COUNT 8 + +struct rtw_tx_ring { + unsigned char qid; + struct tx_desc *desc; + dma_addr_t dma; + unsigned int idx; + unsigned int entries; + _queue queue; + u32 qlen; +}; +#endif + +struct hw_xmit { + //_lock xmit_lock; + //_list pending; + _queue *sta_queue; + //struct hw_txqueue *phwtxqueue; + //sint txcmdcnt; + int accnt; +}; + +#if 0 +struct pkt_attrib +{ + u8 type; + u8 subtype; + u8 bswenc; + u8 dhcp_pkt; + u16 ether_type; + int pktlen; //the original 802.3 pkt raw_data len (not include ether_hdr data) + int pkt_hdrlen; //the original 802.3 pkt header len + int hdrlen; //the WLAN Header Len + int nr_frags; + int last_txcmdsz; + int encrypt; //when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith + u8 iv[8]; + int iv_len; + u8 icv[8]; + int icv_len; + int priority; + int ack_policy; + int mac_id; + int vcs_mode; //virtual carrier sense method + + u8 dst[ETH_ALEN]; + u8 src[ETH_ALEN]; + u8 ta[ETH_ALEN]; + u8 ra[ETH_ALEN]; + + u8 key_idx; + + u8 qos_en; + u8 ht_en; + u8 raid;//rate adpative id + u8 bwmode; + u8 ch_offset;//PRIME_CHNL_OFFSET + u8 sgi;//short GI + u8 ampdu_en;//tx ampdu enable + u8 mdata;//more data bit + u8 eosp; + + u8 triggered;//for ap mode handling Power Saving sta + + u32 qsel; + u16 seqnum; + + struct sta_info * psta; +#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX + u8 hw_tcp_csum; +#endif +}; +#else +//reduce size +struct pkt_attrib +{ + u8 type; + u8 subtype; + u8 bswenc; + u8 dhcp_pkt; + u16 ether_type; + u16 seqnum; + u8 hw_ssn_sel; //for HW_SEQ0,1,2,3 + u16 pkt_hdrlen; //the original 802.3 pkt header len + u16 hdrlen; //the WLAN Header Len + u32 pktlen; //the original 802.3 pkt raw_data len (not include ether_hdr data) + u32 last_txcmdsz; + u8 nr_frags; + u8 encrypt; //when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith + u8 iv_len; + u8 icv_len; + u8 iv[18]; + u8 icv[16]; + u8 priority; + u8 ack_policy; + u8 mac_id; + u8 vcs_mode; //virtual carrier sense method + u8 dst[ETH_ALEN]; + u8 src[ETH_ALEN]; + u8 ta[ETH_ALEN]; + u8 ra[ETH_ALEN]; + u8 key_idx; + u8 qos_en; + u8 ht_en; + u8 raid;//rate adpative id + u8 bwmode; + u8 ch_offset;//PRIME_CHNL_OFFSET + u8 sgi;//short GI + u8 ampdu_en;//tx ampdu enable + u8 ampdu_spacing; //ampdu_min_spacing for peer sta's rx + u8 mdata;//more data bit + u8 pctrl;//per packet txdesc control enable + u8 triggered;//for ap mode handling Power Saving sta + u8 qsel; + u8 order;//order bit + u8 eosp; + u8 rate; + u8 intel_proxim; + u8 retry_ctrl; + u8 mbssid; + u8 ldpc; + u8 stbc; + struct sta_info * psta; +#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX + u8 hw_tcp_csum; +#endif + + u8 rtsen; + u8 cts2self; + union Keytype dot11tkiptxmickey; + //union Keytype dot11tkiprxmickey; + union Keytype dot118021x_UncstKey; + +#ifdef CONFIG_TDLS + u8 direct_link; + struct sta_info *ptdls_sta; +#endif //CONFIG_TDLS + u8 key_type; + + u8 icmp_pkt; + +#ifdef CONFIG_BEAMFORMING + u16 txbf_p_aid;/*beamforming Partial_AID*/ + u16 txbf_g_id;/*beamforming Group ID*/ + #endif + +}; +#endif + +#define WLANHDR_OFFSET 64 + +#define NULL_FRAMETAG (0x0) +#define DATA_FRAMETAG 0x01 +#define L2_FRAMETAG 0x02 +#define MGNT_FRAMETAG 0x03 +#define AMSDU_FRAMETAG 0x04 + +#define EII_FRAMETAG 0x05 +#define IEEE8023_FRAMETAG 0x06 + +#define MP_FRAMETAG 0x07 + +#define TXAGG_FRAMETAG 0x08 + +enum { + XMITBUF_DATA = 0, + XMITBUF_MGNT = 1, + XMITBUF_CMD = 2, +}; + +bool rtw_xmit_ac_blocked(_adapter *adapter); + +struct submit_ctx{ + u32 submit_time; /* */ + u32 timeout_ms; /* <0: not synchronous, 0: wait forever, >0: up to ms waiting */ + int status; /* status for operation */ +#ifdef PLATFORM_LINUX + struct completion done; +#endif +}; + +enum { + RTW_SCTX_SUBMITTED = -1, + RTW_SCTX_DONE_SUCCESS = 0, + RTW_SCTX_DONE_UNKNOWN, + RTW_SCTX_DONE_TIMEOUT, + RTW_SCTX_DONE_BUF_ALLOC, + RTW_SCTX_DONE_BUF_FREE, + RTW_SCTX_DONE_WRITE_PORT_ERR, + RTW_SCTX_DONE_TX_DESC_NA, + RTW_SCTX_DONE_TX_DENY, + RTW_SCTX_DONE_CCX_PKT_FAIL, + RTW_SCTX_DONE_DRV_STOP, + RTW_SCTX_DONE_DEV_REMOVE, + RTW_SCTX_DONE_CMD_ERROR, + RTX_SCTX_CSTR_WAIT_RPT2, +}; + + +void rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms); +int rtw_sctx_wait(struct submit_ctx *sctx, const char *msg); +void rtw_sctx_done_err(struct submit_ctx **sctx, int status); +void rtw_sctx_done(struct submit_ctx **sctx); + +struct xmit_buf +{ + _list list; + + _adapter *padapter; + + u8 *pallocated_buf; + + u8 *pbuf; + + void *priv_data; + + u16 buf_tag; // 0: Normal xmitbuf, 1: extension xmitbuf, 2:cmd xmitbuf + u16 flags; + u32 alloc_sz; + + u32 len; + + struct submit_ctx *sctx; + +#ifdef CONFIG_USB_HCI + + //u32 sz[8]; + u32 ff_hwaddr; + +#if defined(PLATFORM_OS_XP)||defined(PLATFORM_LINUX) || defined(PLATFORM_FREEBSD) + PURB pxmit_urb[8]; + dma_addr_t dma_transfer_addr; /* (in) dma addr for transfer_buffer */ +#endif + +#ifdef PLATFORM_OS_XP + PIRP pxmit_irp[8]; +#endif + +#ifdef PLATFORM_OS_CE + USB_TRANSFER usb_transfer_write_port; +#endif + + u8 bpending[8]; + + sint last[8]; + +#endif + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + u8 *phead; + u8 *pdata; + u8 *ptail; + u8 *pend; + u32 ff_hwaddr; + u8 pg_num; + u8 agg_num; +#ifdef PLATFORM_OS_XP + PMDL pxmitbuf_mdl; + PIRP pxmitbuf_irp; + PSDBUS_REQUEST_PACKET pxmitbuf_sdrp; +#endif +#endif + +#ifdef CONFIG_PCI_HCI + struct tx_desc *desc; +#endif + +#if defined(DBG_XMIT_BUF )|| defined(DBG_XMIT_BUF_EXT) + u8 no; +#endif + +}; + + +struct xmit_frame +{ + _list list; + + struct pkt_attrib attrib; + + _pkt *pkt; + + int frame_tag; + + _adapter *padapter; + + u8 *buf_addr; + + struct xmit_buf *pxmitbuf; + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + u8 pg_num; + u8 agg_num; +#endif + +#ifdef CONFIG_USB_HCI +#ifdef CONFIG_USB_TX_AGGREGATION + u8 agg_num; +#endif + s8 pkt_offset; +#endif + +#ifdef CONFIG_XMIT_ACK + u8 ack_report; +#endif + + u8 *alloc_addr; /* the actual address this xmitframe allocated */ + u8 ext_tag; /* 0:data, 1:mgmt */ + +}; + +struct tx_servq { + _list tx_pending; + _queue sta_pending; + int qcnt; +}; + + +struct sta_xmit_priv +{ + _lock lock; + sint option; + sint apsd_setting; //When bit mask is on, the associated edca queue supports APSD. + + + //struct tx_servq blk_q[MAX_NUMBLKS]; + struct tx_servq be_q; //priority == 0,3 + struct tx_servq bk_q; //priority == 1,2 + struct tx_servq vi_q; //priority == 4,5 + struct tx_servq vo_q; //priority == 6,7 + _list legacy_dz; + _list apsd; + + u16 txseq_tid[16]; + + //uint sta_tx_bytes; + //u64 sta_tx_pkts; + //uint sta_tx_fail; + + +}; + + +struct hw_txqueue { + volatile sint head; + volatile sint tail; + volatile sint free_sz; //in units of 64 bytes + volatile sint free_cmdsz; + volatile sint txsz[8]; + uint ff_hwaddr; + uint cmd_hwaddr; + sint ac_tag; +}; + +struct agg_pkt_info{ + u16 offset; + u16 pkt_len; +}; + +enum cmdbuf_type { + CMDBUF_BEACON = 0x00, + CMDBUF_RSVD, + CMDBUF_MAX +}; + +u8 rtw_get_hwseq_no(_adapter *padapter); + +struct xmit_priv { + + _lock lock; + + _sema xmit_sema; + _sema terminate_xmitthread_sema; + + //_queue blk_strms[MAX_NUMBLKS]; + _queue be_pending; + _queue bk_pending; + _queue vi_pending; + _queue vo_pending; + _queue bm_pending; + + //_queue legacy_dz_queue; + //_queue apsd_queue; + + u8 *pallocated_frame_buf; + u8 *pxmit_frame_buf; + uint free_xmitframe_cnt; + _queue free_xmit_queue; + + //uint mapping_addr; + //uint pkt_sz; + + u8 *xframe_ext_alloc_addr; + u8 *xframe_ext; + uint free_xframe_ext_cnt; + _queue free_xframe_ext_queue; + + //struct hw_txqueue be_txqueue; + //struct hw_txqueue bk_txqueue; + //struct hw_txqueue vi_txqueue; + //struct hw_txqueue vo_txqueue; + //struct hw_txqueue bmc_txqueue; + + uint frag_len; + + _adapter *adapter; + + u8 vcs_setting; + u8 vcs; + u8 vcs_type; + //u16 rts_thresh; + + u64 tx_bytes; + u64 tx_pkts; + u64 tx_drop; + u64 last_tx_pkts; + + struct hw_xmit *hwxmits; + u8 hwxmit_entry; + + u8 wmm_para_seq[4];//sequence for wmm ac parameter strength from large to small. it's value is 0->vo, 1->vi, 2->be, 3->bk. + +#ifdef CONFIG_USB_HCI + _sema tx_retevt;//all tx return event; + u8 txirp_cnt;// + +#ifdef PLATFORM_OS_CE + USB_TRANSFER usb_transfer_write_port; +// USB_TRANSFER usb_transfer_write_mem; +#endif +#ifdef PLATFORM_LINUX + struct tasklet_struct xmit_tasklet; +#endif +#ifdef PLATFORM_FREEBSD + struct task xmit_tasklet; +#endif + //per AC pending irp + int beq_cnt; + int bkq_cnt; + int viq_cnt; + int voq_cnt; + +#endif + +#ifdef CONFIG_PCI_HCI + // Tx + struct rtw_tx_ring tx_ring[PCI_MAX_TX_QUEUE_COUNT]; + int txringcount[PCI_MAX_TX_QUEUE_COUNT]; + u8 beaconDMAing; //flag of indicating beacon is transmiting to HW by DMA +#ifdef PLATFORM_LINUX + struct tasklet_struct xmit_tasklet; +#endif +#endif + +#if defined (CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) +#ifdef CONFIG_SDIO_TX_TASKLET + #ifdef PLATFORM_LINUX + struct tasklet_struct xmit_tasklet; + #endif /* PLATFORM_LINUX */ +#else + _thread_hdl_ SdioXmitThread; + _sema SdioXmitSema; + _sema SdioXmitTerminateSema; +#endif /* CONFIG_SDIO_TX_TASKLET */ +#endif /* CONFIG_SDIO_HCI */ + + _queue free_xmitbuf_queue; + _queue pending_xmitbuf_queue; + u8 *pallocated_xmitbuf; + u8 *pxmitbuf; + uint free_xmitbuf_cnt; + + _queue free_xmit_extbuf_queue; + u8 *pallocated_xmit_extbuf; + u8 *pxmit_extbuf; + uint free_xmit_extbuf_cnt; + + struct xmit_buf pcmd_xmitbuf[CMDBUF_MAX]; + u8 hw_ssn_seq_no;//mapping to REG_HW_SEQ 0,1,2,3 + u16 nqos_ssn; + #ifdef CONFIG_TX_EARLY_MODE + + #ifdef CONFIG_SDIO_HCI + #define MAX_AGG_PKT_NUM 20 + #else + #define MAX_AGG_PKT_NUM 256 //Max tx ampdu coounts + #endif + + struct agg_pkt_info agg_pkt[MAX_AGG_PKT_NUM]; + #endif + +#ifdef CONFIG_XMIT_ACK + int ack_tx; + _mutex ack_tx_mutex; + struct submit_ctx ack_tx_ops; + u8 seq_no; +#endif + _lock lock_sctx; +}; + +extern struct xmit_frame *__rtw_alloc_cmdxmitframe(struct xmit_priv *pxmitpriv, + enum cmdbuf_type buf_type); +#define rtw_alloc_cmdxmitframe(p) __rtw_alloc_cmdxmitframe(p, CMDBUF_RSVD) +#if defined(CONFIG_RTL8192E) && defined(CONFIG_PCI_HCI) +extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8192ee(struct xmit_priv *pxmitpriv, + enum cmdbuf_type buf_type); +#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8192ee(p, CMDBUF_BEACON) +#else +#define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe(p, CMDBUF_BEACON) +#endif + +extern struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv); +extern s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); + +extern struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv); +extern s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); + +void rtw_count_tx_stats(_adapter *padapter, struct xmit_frame *pxmitframe, int sz); +extern void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len); +static s32 update_attrib_sec_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta); +static void update_attrib_phy_info(_adapter *padapter, struct pkt_attrib *pattrib, struct sta_info *psta); +extern s32 rtw_make_wlanhdr(_adapter *padapter, u8 *hdr, struct pkt_attrib *pattrib); +extern s32 rtw_put_snap(u8 *data, u16 h_proto); + +extern struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv); +struct xmit_frame *rtw_alloc_xmitframe_ext(struct xmit_priv *pxmitpriv); +struct xmit_frame *rtw_alloc_xmitframe_once(struct xmit_priv *pxmitpriv); +extern s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe); +extern void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue); +struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, sint up, u8 *ac); +extern s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); +extern struct xmit_frame* rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, sint entry); + +extern s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe); +extern u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib); +#define rtw_wlan_pkt_size(f) rtw_calculate_wlan_pkt_size_by_attribue(&f->attrib) +extern s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe); +#ifdef CONFIG_IEEE80211W +extern s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe); +#endif //CONFIG_IEEE80211W +#ifdef CONFIG_TDLS +extern struct tdls_txmgmt *ptxmgmt; +s32 rtw_xmit_tdls_coalesce(_adapter *padapter, struct xmit_frame *pxmitframe, struct tdls_txmgmt *ptxmgmt); +s32 update_tdls_attrib(_adapter *padapter, struct pkt_attrib *pattrib); +#endif +s32 _rtw_init_hw_txqueue(struct hw_txqueue* phw_txqueue, u8 ac_tag); +void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv); + + +s32 rtw_txframes_pending(_adapter *padapter); +s32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib); +void rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry); + + +s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter); +void _rtw_free_xmit_priv (struct xmit_priv *pxmitpriv); + + +void rtw_alloc_hwxmits(_adapter *padapter); +void rtw_free_hwxmits(_adapter *padapter); + +s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev); + +s32 rtw_xmit(_adapter *padapter, _pkt **pkt); +bool xmitframe_hiq_filter(struct xmit_frame *xmitframe); +#if defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS) +sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe); +void stop_sta_xmit(_adapter *padapter, struct sta_info *psta); +void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta); +void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta); +#endif + +u8 query_ra_short_GI(struct sta_info *psta); + +u8 qos_acm(u8 acm_mask, u8 priority); + +#ifdef CONFIG_XMIT_THREAD_MODE +void enqueue_pending_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); +void enqueue_pending_xmitbuf_to_head(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); +struct xmit_buf* dequeue_pending_xmitbuf(struct xmit_priv *pxmitpriv); +struct xmit_buf* dequeue_pending_xmitbuf_under_survey(struct xmit_priv *pxmitpriv); +sint check_pending_xmitbuf(struct xmit_priv *pxmitpriv); +thread_return rtw_xmit_thread(thread_context context); +#endif + +static void do_queue_select(_adapter * padapter, struct pkt_attrib * pattrib); +u32 rtw_get_ff_hwaddr(struct xmit_frame *pxmitframe); + +#ifdef CONFIG_XMIT_ACK +int rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms); +void rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status); +#endif //CONFIG_XMIT_ACK + + +//include after declaring struct xmit_buf, in order to avoid warning +#include + +#endif //_RTL871X_XMIT_H_ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/sta_info.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/sta_info.h new file mode 100644 index 000000000..7cd5e61ea --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/sta_info.h @@ -0,0 +1,593 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __STA_INFO_H_ +#define __STA_INFO_H_ + + +#define IBSS_START_MAC_ID 2 +#define NUM_STA MACID_NUM_SW_LIMIT +#define NUM_ACL 16 + +#ifdef CONFIG_TDLS +#define MAX_ALLOWED_TDLS_STA_NUM 4 +#endif + +enum sta_info_update_type { + STA_INFO_UPDATE_NONE = 0, + STA_INFO_UPDATE_BW = BIT(0), + STA_INFO_UPDATE_RATE = BIT(1), + STA_INFO_UPDATE_PROTECTION_MODE = BIT(2), + STA_INFO_UPDATE_CAP = BIT(3), + STA_INFO_UPDATE_HT_CAP = BIT(4), + STA_INFO_UPDATE_VHT_CAP = BIT(5), + STA_INFO_UPDATE_ALL = STA_INFO_UPDATE_BW + |STA_INFO_UPDATE_RATE + |STA_INFO_UPDATE_PROTECTION_MODE + |STA_INFO_UPDATE_CAP + |STA_INFO_UPDATE_HT_CAP + |STA_INFO_UPDATE_VHT_CAP, + STA_INFO_UPDATE_MAX +}; + +//if mode ==0, then the sta is allowed once the addr is hit. +//if mode ==1, then the sta is rejected once the addr is non-hit. +struct rtw_wlan_acl_node { + _list list; + u8 addr[ETH_ALEN]; + u8 valid; +}; + +//mode=0, disable +//mode=1, accept unless in deny list +//mode=2, deny unless in accept list +struct wlan_acl_pool { + int mode; + int num; + struct rtw_wlan_acl_node aclnode[NUM_ACL]; + _queue acl_node_q; +}; + +typedef struct _RSSI_STA{ + s32 UndecoratedSmoothedPWDB; + s32 UndecoratedSmoothedCCK; + s32 UndecoratedSmoothedOFDM; + u32 OFDM_pkt; + u64 PacketMap; + u8 ValidBit; +}RSSI_STA, *PRSSI_STA; + +struct stainfo_stats { + + u64 rx_mgnt_pkts; + u64 rx_beacon_pkts; + u64 rx_probereq_pkts; + u64 rx_probersp_pkts; + u64 rx_probersp_bm_pkts; + u64 rx_probersp_uo_pkts; + u64 rx_ctrl_pkts; + u64 rx_data_pkts; + u64 rx_data_qos_pkts[TID_NUM]; + u64 last_rx_mgnt_pkts; + u64 last_rx_beacon_pkts; + u64 last_rx_probereq_pkts; + u64 last_rx_probersp_pkts; + u64 last_rx_probersp_bm_pkts; + u64 last_rx_probersp_uo_pkts; + u64 last_rx_ctrl_pkts; + u64 last_rx_data_pkts; + u64 last_rx_data_qos_pkts[TID_NUM]; +#ifdef CONFIG_TDLS + u64 rx_tdls_disc_rsp_pkts; + u64 last_rx_tdls_disc_rsp_pkts; +#endif + u64 rx_bytes; + u64 rx_drops; + + u64 tx_pkts; + u64 tx_bytes; + u64 tx_drops; +}; + +#ifndef DBG_SESSION_TRACKER +#define DBG_SESSION_TRACKER 0 +#endif + +/* session tracker status */ +#define ST_STATUS_NONE 0 +#define ST_STATUS_CHECK BIT0 +#define ST_STATUS_ESTABLISH BIT1 +#define ST_STATUS_EXPIRE BIT2 + +#define ST_EXPIRE_MS (10 * 1000) + +struct session_tracker { + _list list; /* session_tracker_queue */ + u32 local_naddr; + u16 local_port; + u32 remote_naddr; + u16 remote_port; + u32 set_time; + u8 status; +}; + +/* session tracker cmd */ +#define ST_CMD_ADD 0 +#define ST_CMD_DEL 1 +#define ST_CMD_CHK 2 + +struct st_cmd_parm { + u8 cmd; + struct sta_info *sta; + u32 local_naddr; /* TODO: IPV6 */ + u16 local_port; + u32 remote_naddr; /* TODO: IPV6 */ + u16 remote_port; +}; + +typedef bool (*st_match_rule)(_adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port); + +struct st_register { + u8 s_proto; + st_match_rule rule; +}; + +#define SESSION_TRACKER_REG_ID_WFD 0 +#define SESSION_TRACKER_REG_ID_NUM 1 + +struct st_ctl_t { + struct st_register reg[SESSION_TRACKER_REG_ID_NUM]; + _queue tracker_q; +}; + +void rtw_st_ctl_init(struct st_ctl_t *st_ctl); +void rtw_st_ctl_deinit(struct st_ctl_t *st_ctl); +void rtw_st_ctl_register(struct st_ctl_t *st_ctl, u8 st_reg_id, struct st_register *reg); +void rtw_st_ctl_unregister(struct st_ctl_t *st_ctl, u8 st_reg_id); +bool rtw_st_ctl_chk_reg_s_proto(struct st_ctl_t *st_ctl, u8 s_proto); +bool rtw_st_ctl_chk_reg_rule(struct st_ctl_t *st_ctl, _adapter *adapter, u8 *local_naddr, u8 *local_port, u8 *remote_naddr, u8 *remote_port); +void dump_st_ctl(void *sel, struct st_ctl_t *st_ctl); + +#ifdef CONFIG_TDLS +struct TDLS_PeerKey { + u8 kck[16]; /* TPK-KCK */ + u8 tk[16]; /* TPK-TK; only CCMP will be used */ +} ; +#endif //CONFIG_TDLS + +struct sta_info { + + _lock lock; + _list list; //free_sta_queue + _list hash_list; //sta_hash + //_list asoc_list; //20061114 + //_list sleep_list;//sleep_q + //_list wakeup_list;//wakeup_q + _adapter *padapter; + + struct sta_xmit_priv sta_xmitpriv; + struct sta_recv_priv sta_recvpriv; + + _queue sleep_q; + unsigned int sleepq_len; + + uint state; + uint aid; + uint mac_id; + uint qos_option; + u8 hwaddr[ETH_ALEN]; + u16 hwseq; + u8 ra_rpt_linked; + + uint ieee8021x_blocked; //0: allowed, 1:blocked + uint dot118021XPrivacy; //aes, tkip... + union Keytype dot11tkiptxmickey; + union Keytype dot11tkiprxmickey; + union Keytype dot118021x_UncstKey; + union pn48 dot11txpn; // PN48 used for Unicast xmit +#ifdef CONFIG_GTK_OL + u8 kek[RTW_KEK_LEN]; + u8 kck[RTW_KCK_LEN]; + u8 replay_ctr[RTW_REPLAY_CTR_LEN]; +#endif //CONFIG_GTK_OL +#ifdef CONFIG_IEEE80211W + union pn48 dot11wtxpn; // PN48 used for Unicast mgmt xmit. + _timer dot11w_expire_timer; +#endif //CONFIG_IEEE80211W + union pn48 dot11rxpn; // PN48 used for Unicast recv. + + + u8 bssrateset[16]; + u32 bssratelen; + s32 rssi; + s32 signal_quality; + + u8 cts2self; + u8 rtsen; + + u8 raid; + u8 init_rate; + u64 ra_mask; + u8 wireless_mode; // NETWORK_TYPE + u8 bw_mode; + + u8 ldpc; + u8 stbc; + +#ifdef CONFIG_BEAMFORMING + u16 txbf_paid; + u16 txbf_gid; +#endif + + struct stainfo_stats sta_stats; + +#ifdef CONFIG_TDLS + u32 tdls_sta_state; + u8 SNonce[32]; + u8 ANonce[32]; + u32 TDLS_PeerKey_Lifetime; + u32 TPK_count; + _timer TPK_timer; + struct TDLS_PeerKey tpk; +#ifdef CONFIG_TDLS_CH_SW + u16 ch_switch_time; + u16 ch_switch_timeout; + //u8 option; + _timer ch_sw_timer; + _timer delay_timer; + _timer stay_on_base_chnl_timer; + _timer ch_sw_monitor_timer; +#endif + _timer handshake_timer; + u8 alive_count; + _timer pti_timer; + u8 TDLS_RSNIE[20]; /* Save peer's RSNIE, used for sending TDLS_SETUP_RSP */ +#endif /* CONFIG_TDLS */ + + //for A-MPDU TX, ADDBA timeout check + _timer addba_retry_timer; + + //for A-MPDU Rx reordering buffer control + struct recv_reorder_ctrl recvreorder_ctrl[TID_NUM]; + ATOMIC_T continual_no_rx_packet[TID_NUM]; + //for A-MPDU Tx + //unsigned char ampdu_txen_bitmap; + u16 BA_starting_seqctrl[16]; + + +#ifdef CONFIG_80211N_HT + struct ht_priv htpriv; +#endif + +#ifdef CONFIG_80211AC_VHT + struct vht_priv vhtpriv; +#endif + + //Notes: + //STA_Mode: + //curr_network(mlme_priv/security_priv/qos/ht) + sta_info: (STA & AP) CAP/INFO + //scan_q: AP CAP/INFO + + //AP_Mode: + //curr_network(mlme_priv/security_priv/qos/ht) : AP CAP/INFO + //sta_info: (AP & STA) CAP/INFO + + unsigned int expire_to; + +#ifdef CONFIG_AP_MODE + + _list asoc_list; + _list auth_list; + + unsigned int auth_seq; + unsigned int authalg; + unsigned char chg_txt[128]; + + u16 capability; + int flags; + + int dot8021xalg;//0:disable, 1:psk, 2:802.1x + int wpa_psk;//0:disable, bit(0): WPA, bit(1):WPA2 + int wpa_group_cipher; + int wpa2_group_cipher; + int wpa_pairwise_cipher; + int wpa2_pairwise_cipher; + + u8 bpairwise_key_installed; + +#ifdef CONFIG_NATIVEAP_MLME + u8 wpa_ie[32]; + + u8 nonerp_set; + u8 no_short_slot_time_set; + u8 no_short_preamble_set; + u8 no_ht_gf_set; + u8 no_ht_set; + u8 ht_20mhz_set; + u8 ht_40mhz_intolerant; +#endif // CONFIG_NATIVEAP_MLME + +#ifdef CONFIG_ATMEL_RC_PATCH + u8 flag_atmel_rc; +#endif + + u8 qos_info; + + u8 max_sp_len; + u8 uapsd_bk;//BIT(0): Delivery enabled, BIT(1): Trigger enabled + u8 uapsd_be; + u8 uapsd_vi; + u8 uapsd_vo; + + u8 has_legacy_ac; + unsigned int sleepq_ac_len; + +#ifdef CONFIG_P2P + //p2p priv data + u8 is_p2p_device; + u8 p2p_status_code; + + //p2p client info + u8 dev_addr[ETH_ALEN]; + //u8 iface_addr[ETH_ALEN];//= hwaddr[ETH_ALEN] + u8 dev_cap; + u16 config_methods; + u8 primary_dev_type[8]; + u8 num_of_secdev_type; + u8 secdev_types_list[32];// 32/8 == 4; + u16 dev_name_len; + u8 dev_name[32]; +#endif //CONFIG_P2P + +#ifdef CONFIG_WFD + u8 op_wfd_mode; +#endif + +#ifdef CONFIG_TX_MCAST2UNI + u8 under_exist_checking; +#endif // CONFIG_TX_MCAST2UNI + + u8 keep_alive_trycnt; + +#ifdef CONFIG_AUTO_AP_MODE + u8 isrc; //this device is rc + u16 pid; // pairing id +#endif + +#endif // CONFIG_AP_MODE + +#ifdef CONFIG_IOCTL_CFG80211 + u8 *passoc_req; + u32 assoc_req_len; +#endif + + //for DM + RSSI_STA rssi_stat; + + //ODM_STA_INFO_T + // ================ODM Relative Info======================= + // Please be care, dont declare too much structure here. It will cost memory * STA support num. + // + // + // 2011/10/20 MH Add for ODM STA info. + // + // Driver Write + u8 bValid; // record the sta status link or not? + //u8 WirelessMode; // + u8 IOTPeer; // Enum value. HT_IOT_PEER_E + // ODM Write + //1 PHY_STATUS_INFO + u8 RSSI_Path[4]; // + u8 RSSI_Ave; + u8 RXEVM[4]; + u8 RXSNR[4]; + + u8 rssi_level; //for Refresh RA mask + // ODM Write + //1 TX_INFO (may changed by IC) + //TX_INFO_T pTxInfo; // Define in IC folder. Move lower layer. + // + // ================ODM Relative Info======================= + // + + /* To store the sequence number of received management frame */ + u16 RxMgmtFrameSeqNum; + + struct st_ctl_t st_ctl; +}; + +#define sta_rx_pkts(sta) \ + (sta->sta_stats.rx_mgnt_pkts \ + + sta->sta_stats.rx_ctrl_pkts \ + + sta->sta_stats.rx_data_pkts) + +#define sta_last_rx_pkts(sta) \ + (sta->sta_stats.last_rx_mgnt_pkts \ + + sta->sta_stats.last_rx_ctrl_pkts \ + + sta->sta_stats.last_rx_data_pkts) + +#define sta_rx_data_pkts(sta) \ + (sta->sta_stats.rx_data_pkts) + +#define sta_rx_data_qos_pkts(sta, i) \ + (sta->sta_stats.rx_data_qos_pkts[i]) + +#define sta_last_rx_data_pkts(sta) \ + (sta->sta_stats.last_rx_data_pkts) + +#define sta_last_rx_data_qos_pkts(sta, i) \ + (sta->sta_stats.last_rx_data_qos_pkts[i]) + +#define sta_rx_mgnt_pkts(sta) \ + (sta->sta_stats.rx_mgnt_pkts) + +#define sta_last_rx_mgnt_pkts(sta) \ + (sta->sta_stats.last_rx_mgnt_pkts) + +#define sta_rx_beacon_pkts(sta) \ + (sta->sta_stats.rx_beacon_pkts) + +#define sta_last_rx_beacon_pkts(sta) \ + (sta->sta_stats.last_rx_beacon_pkts) + +#define sta_rx_probereq_pkts(sta) \ + (sta->sta_stats.rx_probereq_pkts) + +#define sta_last_rx_probereq_pkts(sta) \ + (sta->sta_stats.last_rx_probereq_pkts) + +#define sta_rx_probersp_pkts(sta) \ + (sta->sta_stats.rx_probersp_pkts) + +#define sta_last_rx_probersp_pkts(sta) \ + (sta->sta_stats.last_rx_probersp_pkts) + +#define sta_rx_probersp_bm_pkts(sta) \ + (sta->sta_stats.rx_probersp_bm_pkts) + +#define sta_last_rx_probersp_bm_pkts(sta) \ + (sta->sta_stats.last_rx_probersp_bm_pkts) + +#define sta_rx_probersp_uo_pkts(sta) \ + (sta->sta_stats.rx_probersp_uo_pkts) + +#define sta_last_rx_probersp_uo_pkts(sta) \ + (sta->sta_stats.last_rx_probersp_uo_pkts) + +#define sta_update_last_rx_pkts(sta) \ + do { \ + sta->sta_stats.last_rx_mgnt_pkts = sta->sta_stats.rx_mgnt_pkts; \ + sta->sta_stats.last_rx_beacon_pkts = sta->sta_stats.rx_beacon_pkts; \ + sta->sta_stats.last_rx_probereq_pkts = sta->sta_stats.rx_probereq_pkts; \ + sta->sta_stats.last_rx_probersp_pkts = sta->sta_stats.rx_probersp_pkts; \ + sta->sta_stats.last_rx_probersp_bm_pkts = sta->sta_stats.rx_probersp_bm_pkts; \ + sta->sta_stats.last_rx_probersp_uo_pkts = sta->sta_stats.rx_probersp_uo_pkts; \ + sta->sta_stats.last_rx_ctrl_pkts = sta->sta_stats.rx_ctrl_pkts; \ + sta->sta_stats.last_rx_data_pkts = sta->sta_stats.rx_data_pkts; \ + } while(0) + +#define STA_RX_PKTS_ARG(sta) \ + sta->sta_stats.rx_mgnt_pkts \ + , sta->sta_stats.rx_ctrl_pkts \ + , sta->sta_stats.rx_data_pkts + +#define STA_LAST_RX_PKTS_ARG(sta) \ + sta->sta_stats.last_rx_mgnt_pkts \ + , sta->sta_stats.last_rx_ctrl_pkts \ + , sta->sta_stats.last_rx_data_pkts + +#define STA_RX_PKTS_DIFF_ARG(sta) \ + sta->sta_stats.rx_mgnt_pkts - sta->sta_stats.last_rx_mgnt_pkts \ + , sta->sta_stats.rx_ctrl_pkts - sta->sta_stats.last_rx_ctrl_pkts \ + , sta->sta_stats.rx_data_pkts -sta->sta_stats.last_rx_data_pkts + +#define STA_PKTS_FMT "(m:%llu, c:%llu, d:%llu)" + +#ifdef CONFIG_WFD +#define STA_OP_WFD_MODE(sta) (sta)->op_wfd_mode +#define STA_SET_OP_WFD_MODE(sta, mode) (sta)->op_wfd_mode = (mode) +#else +#define STA_OP_WFD_MODE(sta) 0 +#define STA_SET_OP_WFD_MODE(sta, mode) do {} while (0) +#endif + +struct sta_priv { + + u8 *pallocated_stainfo_buf; + u8 *pstainfo_buf; + _queue free_sta_queue; + + _lock sta_hash_lock; + _list sta_hash[NUM_STA]; + int asoc_sta_count; + _queue sleep_q; + _queue wakeup_q; + + _adapter *padapter; + + u32 adhoc_expire_to; + +#ifdef CONFIG_AP_MODE + _list asoc_list; + _list auth_list; + _lock asoc_list_lock; + _lock auth_list_lock; + u8 asoc_list_cnt; + u8 auth_list_cnt; + + unsigned int auth_to; //sec, time to expire in authenticating. + unsigned int assoc_to; //sec, time to expire before associating. + unsigned int expire_to; //sec , time to expire after associated. + + /* pointers to STA info; based on allocated AID or NULL if AID free + * AID is in the range 1-2007, so sta_aid[0] corresponders to AID 1 + * and so on + */ + struct sta_info *sta_aid[NUM_STA]; + + u16 sta_dz_bitmap;//only support 15 stations, staion aid bitmap for sleeping sta. + u16 tim_bitmap;//only support 15 stations, aid=0~15 mapping bit0~bit15 + + u16 max_num_sta; + + struct wlan_acl_pool acl_list; +#endif + +#ifdef CONFIG_ATMEL_RC_PATCH + u8 atmel_rc_pattern [6]; +#endif + +}; + + +static inline u32 wifi_mac_hash(const u8 *mac) +{ + u32 x; + + x = mac[0]; + x = (x << 2) ^ mac[1]; + x = (x << 2) ^ mac[2]; + x = (x << 2) ^ mac[3]; + x = (x << 2) ^ mac[4]; + x = (x << 2) ^ mac[5]; + + x ^= x >> 8; + x = x & (NUM_STA - 1); + + return x; +} + + +extern u32 _rtw_init_sta_priv(struct sta_priv *pstapriv); +extern u32 _rtw_free_sta_priv(struct sta_priv *pstapriv); + +#define stainfo_offset_valid(offset) (offset < NUM_STA && offset >= 0) +int rtw_stainfo_offset(struct sta_priv *stapriv, struct sta_info *sta); +struct sta_info *rtw_get_stainfo_by_offset(struct sta_priv *stapriv, int offset); + +extern struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr); +extern u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta); +extern void rtw_free_all_stainfo(_adapter *padapter); +extern struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, const u8 *hwaddr); +extern u32 rtw_init_bcmc_stainfo(_adapter* padapter); +extern struct sta_info* rtw_get_bcmc_stainfo(_adapter* padapter); +extern u8 rtw_access_ctrl(_adapter *padapter, u8 *mac_addr); + +#endif //_STA_INFO_H_ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/usb_hal.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/usb_hal.h new file mode 100644 index 000000000..8d500eb50 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/usb_hal.h @@ -0,0 +1,61 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __USB_HAL_H__ +#define __USB_HAL_H__ + +int usb_init_recv_priv(_adapter *padapter, u16 ini_in_buf_sz); +void usb_free_recv_priv (_adapter *padapter, u16 ini_in_buf_sz); + +u8 rtw_set_hal_ops(_adapter *padapter); + +#ifdef CONFIG_RTL8188E +void rtl8188eu_set_hal_ops(_adapter * padapter); +#endif + +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) +void rtl8812au_set_hal_ops(_adapter * padapter); +#endif + +#ifdef CONFIG_RTL8192E +void rtl8192eu_set_hal_ops(_adapter * padapter); +#endif + + +#ifdef CONFIG_RTL8723B +void rtl8723bu_set_hal_ops(_adapter * padapter); +#endif + +#ifdef CONFIG_RTL8814A +void rtl8814au_set_hal_ops(_adapter * padapter); +#endif /* CONFIG_RTL8814A */ + +#ifdef CONFIG_RTL8188F +void rtl8188fu_set_hal_ops(_adapter *padapter); +#endif + +#ifdef CONFIG_RTL8703B +void rtl8703bu_set_hal_ops(_adapter *padapter); +#endif + +#ifdef CONFIG_INTEL_PROXIM +extern _adapter *rtw_usb_get_sw_pointer(void); +#endif //CONFIG_INTEL_PROXIM +#endif //__USB_HAL_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/usb_ops.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/usb_ops.h new file mode 100644 index 000000000..d89b9748a --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/usb_ops.h @@ -0,0 +1,148 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __USB_OPS_H_ +#define __USB_OPS_H_ + + +#define REALTEK_USB_VENQT_READ 0xC0 +#define REALTEK_USB_VENQT_WRITE 0x40 +#define REALTEK_USB_VENQT_CMD_REQ 0x05 +#define REALTEK_USB_VENQT_CMD_IDX 0x00 +#define REALTEK_USB_IN_INT_EP_IDX 1 + +enum{ + VENDOR_WRITE = 0x00, + VENDOR_READ = 0x01, +}; +#define ALIGNMENT_UNIT 16 +#define MAX_VENDOR_REQ_CMD_SIZE 254 //8188cu SIE Support +#define MAX_USB_IO_CTL_SIZE (MAX_VENDOR_REQ_CMD_SIZE +ALIGNMENT_UNIT) + +#ifdef PLATFORM_LINUX +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,12)) +#define rtw_usb_control_msg(dev, pipe, request, requesttype, value, index, data, size, timeout_ms) \ + usb_control_msg((dev), (pipe), (request), (requesttype), (value), (index), (data), (size), (timeout_ms)) +#define rtw_usb_bulk_msg(usb_dev, pipe, data, len, actual_length, timeout_ms) \ + usb_bulk_msg((usb_dev), (pipe), (data), (len), (actual_length), (timeout_ms)) +#else +#define rtw_usb_control_msg(dev, pipe, request, requesttype, value, index, data, size,timeout_ms) \ + usb_control_msg((dev), (pipe), (request), (requesttype), (value), (index), (data), (size), \ + ((timeout_ms) == 0) ||((timeout_ms)*HZ/1000>0)?((timeout_ms)*HZ/1000):1) +#define rtw_usb_bulk_msg(usb_dev, pipe, data, len, actual_length, timeout_ms) \ + usb_bulk_msg((usb_dev), (pipe), (data), (len), (actual_length), \ + ((timeout_ms) == 0) ||((timeout_ms)*HZ/1000>0)?((timeout_ms)*HZ/1000):1) +#endif +#include +#endif //PLATFORM_LINUX + +#ifdef CONFIG_RTL8188E +void rtl8188eu_set_hw_type(struct dvobj_priv *pdvobj); +void rtl8188eu_set_intf_ops(struct _io_ops *pops); +#ifdef CONFIG_SUPPORT_USB_INT +void interrupt_handler_8188eu(_adapter *padapter, u16 pkt_len, u8 *pbuf); +#endif +#endif + +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) +void rtl8812au_set_hw_type(struct dvobj_priv *pdvobj); +void rtl8812au_set_intf_ops(struct _io_ops *pops); +#ifdef CONFIG_SUPPORT_USB_INT +void interrupt_handler_8812au(_adapter *padapter, u16 pkt_len, u8 *pbuf); +#endif +#endif + +#ifdef CONFIG_RTL8814A +void rtl8814au_set_hw_type(struct dvobj_priv *pdvobj); +void rtl8814au_set_intf_ops(struct _io_ops *pops); +#ifdef CONFIG_SUPPORT_USB_INT +void interrupt_handler_8814au(_adapter *padapter, u16 pkt_len, u8 *pbuf); +#endif +#endif /* CONFIG_RTL8814 */ + +#ifdef CONFIG_RTL8192E +void rtl8192eu_set_hw_type(struct dvobj_priv *pdvobj); +void rtl8192eu_set_intf_ops(struct _io_ops *pops); +#ifdef CONFIG_SUPPORT_USB_INT +void interrupt_handler_8192eu(_adapter *padapter, u16 pkt_len, u8 *pbuf); +#endif + +#endif + +#ifdef CONFIG_RTL8188F +void rtl8188fu_set_hw_type(struct dvobj_priv *pdvobj); +void rtl8188fu_set_intf_ops(struct _io_ops *pops); +void rtl8188fu_recv_tasklet(void *priv); +void rtl8188fu_xmit_tasklet(unsigned long priv); +#ifdef CONFIG_SUPPORT_USB_INT +void interrupt_handler_8188fu(_adapter *padapter, u16 pkt_len, u8 *pbuf); +#endif +#endif + +#ifdef CONFIG_RTL8723B +void rtl8723bu_set_hw_type(struct dvobj_priv *pdvobj); +void rtl8723bu_set_intf_ops(struct _io_ops *pops); +void rtl8723bu_recv_tasklet(void *priv); +void rtl8723bu_xmit_tasklet(void *priv); +#ifdef CONFIG_SUPPORT_USB_INT +void interrupt_handler_8723bu(_adapter *padapter, u16 pkt_len, u8 *pbuf); +#endif +#endif + +#ifdef CONFIG_RTL8703B +void rtl8703bu_set_hw_type(struct dvobj_priv *pdvobj); +void rtl8703bu_set_intf_ops(struct _io_ops *pops); +void rtl8703bu_recv_tasklet(void *priv); +void rtl8703bu_xmit_tasklet(void *priv); +#ifdef CONFIG_SUPPORT_USB_INT +void interrupt_handler_8703bu(_adapter *padapter, u16 pkt_len, u8 *pbuf); +#endif /* CONFIG_SUPPORT_USB_INT */ +#endif /* CONFIG_RTL8703B */ + +enum RTW_USB_SPEED { + RTW_USB_SPEED_UNKNOWN = 0, + RTW_USB_SPEED_1_1 = 1, + RTW_USB_SPEED_2 = 2, + RTW_USB_SPEED_3 = 3, +}; + +#define IS_FULL_SPEED_USB(Adapter) (adapter_to_dvobj(Adapter)->usb_speed == RTW_USB_SPEED_1_1) +#define IS_HIGH_SPEED_USB(Adapter) (adapter_to_dvobj(Adapter)->usb_speed == RTW_USB_SPEED_2) +#define IS_SUPER_SPEED_USB(Adapter) (adapter_to_dvobj(Adapter)->usb_speed == RTW_USB_SPEED_3) + +#define USB_SUPER_SPEED_BULK_SIZE 1024 // usb 3.0 +#define USB_HIGH_SPEED_BULK_SIZE 512 // usb 2.0 +#define USB_FULL_SPEED_BULK_SIZE 64 // usb 1.1 + +static inline u8 rtw_usb_bulk_size_boundary(_adapter * padapter,int buf_len) +{ + u8 rst = _TRUE; + + if (IS_SUPER_SPEED_USB(padapter)) + rst = (0 == (buf_len) % USB_SUPER_SPEED_BULK_SIZE)?_TRUE:_FALSE; + if (IS_HIGH_SPEED_USB(padapter)) + rst = (0 == (buf_len) % USB_HIGH_SPEED_BULK_SIZE)?_TRUE:_FALSE; + else + rst = (0 == (buf_len) % USB_FULL_SPEED_BULK_SIZE)?_TRUE:_FALSE; + return rst; +} + + +#endif //__USB_OPS_H_ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/usb_ops_linux.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/usb_ops_linux.h new file mode 100644 index 000000000..c124efe45 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/usb_ops_linux.h @@ -0,0 +1,89 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __USB_OPS_LINUX_H__ +#define __USB_OPS_LINUX_H__ + +#define VENDOR_CMD_MAX_DATA_LEN 254 +#define FW_START_ADDRESS 0x1000 + +#define RTW_USB_CONTROL_MSG_TIMEOUT_TEST 10//ms +#define RTW_USB_CONTROL_MSG_TIMEOUT 500//ms + +#define RECV_BULK_IN_ADDR 0x80//assign by drv,not real address +#define RECV_INT_IN_ADDR 0x81//assign by drv,not real address + +#define INTERRUPT_MSG_FORMAT_LEN 60 + +#if defined(CONFIG_VENDOR_REQ_RETRY) && defined(CONFIG_USB_VENDOR_REQ_MUTEX) +/* vendor req retry should be in the situation when each vendor req is atomically submitted from others */ +#define MAX_USBCTRL_VENDORREQ_TIMES 10 +#else +#define MAX_USBCTRL_VENDORREQ_TIMES 1 +#endif + +#define RTW_USB_BULKOUT_TIMEOUT 5000//ms + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) || (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18)) +#define _usbctrl_vendorreq_async_callback(urb, regs) _usbctrl_vendorreq_async_callback(urb) +#define usb_bulkout_zero_complete(purb, regs) usb_bulkout_zero_complete(purb) +#define usb_write_mem_complete(purb, regs) usb_write_mem_complete(purb) +#define usb_write_port_complete(purb, regs) usb_write_port_complete(purb) +#define usb_read_port_complete(purb, regs) usb_read_port_complete(purb) +#define usb_read_interrupt_complete(purb, regs) usb_read_interrupt_complete(purb) +#endif + +#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ +int usb_async_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val); +int usb_async_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val); +int usb_async_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val); +#endif /* CONFIG_USB_SUPPORT_ASYNC_VDN_REQ */ + +unsigned int ffaddr2pipehdl(struct dvobj_priv *pdvobj, u32 addr); + +void usb_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem); +void usb_write_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem); + +void usb_read_port_cancel(struct intf_hdl *pintfhdl); + +u32 usb_write_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem); +void usb_write_port_cancel(struct intf_hdl *pintfhdl); + +int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u16 index, void *pdata, u16 len, u8 requesttype); +#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ +int _usbctrl_vendorreq_async_write(struct usb_device *udev, u8 request, + u16 value, u16 index, void *pdata, u16 len, u8 requesttype); +#endif /* CONFIG_USB_SUPPORT_ASYNC_VDN_REQ */ + +u8 usb_read8(struct intf_hdl *pintfhdl, u32 addr); +u16 usb_read16(struct intf_hdl *pintfhdl, u32 addr); +u32 usb_read32(struct intf_hdl *pintfhdl, u32 addr); +int usb_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val); +int usb_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val); +int usb_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val); +int usb_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata); +u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem); +void usb_recv_tasklet(unsigned long priv); + +#ifdef CONFIG_USB_INTERRUPT_IN_PIPE +void usb_read_interrupt_complete(struct urb *purb, struct pt_regs *regs); +u32 usb_read_interrupt(struct intf_hdl *pintfhdl, u32 addr); +#endif +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/usb_osintf.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/usb_osintf.h new file mode 100644 index 000000000..62dc44aab --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/usb_osintf.h @@ -0,0 +1,32 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __USB_OSINTF_H +#define __USB_OSINTF_H + +#include + +#define USBD_HALTED(Status) ((ULONG)(Status) >> 30 == 3) + + +u8 usbvendorrequest(struct dvobj_priv *pdvobjpriv, RT_USB_BREQUEST brequest, RT_USB_WVALUE wvalue, u8 windex, void* data, u8 datalen, u8 isdirectionin); + + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/usb_vendor_req.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/usb_vendor_req.h new file mode 100644 index 000000000..b60eeface --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/usb_vendor_req.h @@ -0,0 +1,60 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _USB_VENDOR_REQUEST_H_ +#define _USB_VENDOR_REQUEST_H_ + +//4 Set/Get Register related wIndex/Data +#define RT_USB_RESET_MASK_OFF 0 +#define RT_USB_RESET_MASK_ON 1 +#define RT_USB_SLEEP_MASK_OFF 0 +#define RT_USB_SLEEP_MASK_ON 1 +#define RT_USB_LDO_ON 1 +#define RT_USB_LDO_OFF 0 + +//4 Set/Get SYSCLK related wValue or Data +#define RT_USB_SYSCLK_32KHZ 0 +#define RT_USB_SYSCLK_40MHZ 1 +#define RT_USB_SYSCLK_60MHZ 2 + + +typedef enum _RT_USB_BREQUEST { + RT_USB_SET_REGISTER = 1, + RT_USB_SET_SYSCLK = 2, + RT_USB_GET_SYSCLK = 3, + RT_USB_GET_REGISTER = 4 +} RT_USB_BREQUEST; + + +typedef enum _RT_USB_WVALUE { + RT_USB_RESET_MASK = 1, + RT_USB_SLEEP_MASK = 2, + RT_USB_USB_HRCPWM = 3, + RT_USB_LDO = 4, + RT_USB_BOOT_TYPE = 5 +} RT_USB_WVALUE; + + +//BOOLEAN usbvendorrequest(PCE_USB_DEVICE CEdevice, RT_USB_BREQUEST bRequest, RT_USB_WVALUE wValue, UCHAR wIndex, PVOID Data, UCHAR DataLength, BOOLEAN isDirectionIn); +//BOOLEAN CEusbGetStatusRequest(PCE_USB_DEVICE CEdevice, IN USHORT Op, IN USHORT Index, PVOID Data); +//BOOLEAN CEusbFeatureRequest(PCE_USB_DEVICE CEdevice, IN USHORT Op, IN USHORT FeatureSelector, IN USHORT Index); +//BOOLEAN CEusbGetDescriptorRequest(PCE_USB_DEVICE CEdevice, IN short urbLength, IN UCHAR DescriptorType, IN UCHAR Index, IN USHORT LanguageId, IN PVOID TransferBuffer, IN ULONG TransferBufferLength); + +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/wifi.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/wifi.h new file mode 100644 index 000000000..585efef7e --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/wifi.h @@ -0,0 +1,1401 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef _WIFI_H_ +#define _WIFI_H_ + + +#ifdef BIT +//#error "BIT define occurred earlier elsewhere!\n" +#undef BIT +#endif +#define BIT(x) (1 << (x)) + + +#define WLAN_ETHHDR_LEN 14 +#define WLAN_ETHADDR_LEN 6 +#define WLAN_IEEE_OUI_LEN 3 +#define WLAN_ADDR_LEN 6 +#define WLAN_CRC_LEN 4 +#define WLAN_BSSID_LEN 6 +#define WLAN_BSS_TS_LEN 8 +#define WLAN_HDR_A3_LEN 24 +#define WLAN_HDR_A4_LEN 30 +#define WLAN_HDR_A3_QOS_LEN 26 +#define WLAN_HDR_A4_QOS_LEN 32 +#define WLAN_SSID_MAXLEN 32 +#define WLAN_DATA_MAXLEN 2312 + +#define WLAN_A3_PN_OFFSET 24 +#define WLAN_A4_PN_OFFSET 30 + +#define WLAN_MIN_ETHFRM_LEN 60 +#define WLAN_MAX_ETHFRM_LEN 1514 +#define WLAN_ETHHDR_LEN 14 +#define WLAN_WMM_LEN 24 + +#define P80211CAPTURE_VERSION 0x80211001 + +// This value is tested by WiFi 11n Test Plan 5.2.3. +// This test verifies the WLAN NIC can update the NAV through sending the CTS with large duration. +#define WiFiNavUpperUs 30000 // 30 ms + +#ifdef GREEN_HILL +#pragma pack(1) +#endif + +enum WIFI_FRAME_TYPE { + WIFI_MGT_TYPE = (0), + WIFI_CTRL_TYPE = (BIT(2)), + WIFI_DATA_TYPE = (BIT(3)), + WIFI_QOS_DATA_TYPE = (BIT(7)|BIT(3)), //!< QoS Data +}; + +enum WIFI_FRAME_SUBTYPE { + + // below is for mgt frame + WIFI_ASSOCREQ = (0 | WIFI_MGT_TYPE), + WIFI_ASSOCRSP = (BIT(4) | WIFI_MGT_TYPE), + WIFI_REASSOCREQ = (BIT(5) | WIFI_MGT_TYPE), + WIFI_REASSOCRSP = (BIT(5) | BIT(4) | WIFI_MGT_TYPE), + WIFI_PROBEREQ = (BIT(6) | WIFI_MGT_TYPE), + WIFI_PROBERSP = (BIT(6) | BIT(4) | WIFI_MGT_TYPE), + WIFI_BEACON = (BIT(7) | WIFI_MGT_TYPE), + WIFI_ATIM = (BIT(7) | BIT(4) | WIFI_MGT_TYPE), + WIFI_DISASSOC = (BIT(7) | BIT(5) | WIFI_MGT_TYPE), + WIFI_AUTH = (BIT(7) | BIT(5) | BIT(4) | WIFI_MGT_TYPE), + WIFI_DEAUTH = (BIT(7) | BIT(6) | WIFI_MGT_TYPE), + WIFI_ACTION = (BIT(7) | BIT(6) | BIT(4) | WIFI_MGT_TYPE), + WIFI_ACTION_NOACK = (BIT(7) | BIT(6) | BIT(5) | WIFI_MGT_TYPE), + + // below is for control frame + WIFI_NDPA = (BIT(6) | BIT(4) | WIFI_CTRL_TYPE), + WIFI_PSPOLL = (BIT(7) | BIT(5) | WIFI_CTRL_TYPE), + WIFI_RTS = (BIT(7) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE), + WIFI_CTS = (BIT(7) | BIT(6) | WIFI_CTRL_TYPE), + WIFI_ACK = (BIT(7) | BIT(6) | BIT(4) | WIFI_CTRL_TYPE), + WIFI_CFEND = (BIT(7) | BIT(6) | BIT(5) | WIFI_CTRL_TYPE), + WIFI_CFEND_CFACK = (BIT(7) | BIT(6) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE), + + // below is for data frame + WIFI_DATA = (0 | WIFI_DATA_TYPE), + WIFI_DATA_CFACK = (BIT(4) | WIFI_DATA_TYPE), + WIFI_DATA_CFPOLL = (BIT(5) | WIFI_DATA_TYPE), + WIFI_DATA_CFACKPOLL = (BIT(5) | BIT(4) | WIFI_DATA_TYPE), + WIFI_DATA_NULL = (BIT(6) | WIFI_DATA_TYPE), + WIFI_CF_ACK = (BIT(6) | BIT(4) | WIFI_DATA_TYPE), + WIFI_CF_POLL = (BIT(6) | BIT(5) | WIFI_DATA_TYPE), + WIFI_CF_ACKPOLL = (BIT(6) | BIT(5) | BIT(4) | WIFI_DATA_TYPE), + WIFI_QOS_DATA_NULL = (BIT(6) | WIFI_QOS_DATA_TYPE), +}; + +enum WIFI_REASON_CODE { + _RSON_RESERVED_ = 0, + _RSON_UNSPECIFIED_ = 1, + _RSON_AUTH_NO_LONGER_VALID_ = 2, + _RSON_DEAUTH_STA_LEAVING_ = 3, + _RSON_INACTIVITY_ = 4, + _RSON_UNABLE_HANDLE_ = 5, + _RSON_CLS2_ = 6, + _RSON_CLS3_ = 7, + _RSON_DISAOC_STA_LEAVING_ = 8, + _RSON_ASOC_NOT_AUTH_ = 9, + + // WPA reason + _RSON_INVALID_IE_ = 13, + _RSON_MIC_FAILURE_ = 14, + _RSON_4WAY_HNDSHK_TIMEOUT_ = 15, + _RSON_GROUP_KEY_UPDATE_TIMEOUT_ = 16, + _RSON_DIFF_IE_ = 17, + _RSON_MLTCST_CIPHER_NOT_VALID_ = 18, + _RSON_UNICST_CIPHER_NOT_VALID_ = 19, + _RSON_AKMP_NOT_VALID_ = 20, + _RSON_UNSUPPORT_RSNE_VER_ = 21, + _RSON_INVALID_RSNE_CAP_ = 22, + _RSON_IEEE_802DOT1X_AUTH_FAIL_ = 23, + + //belowing are Realtek definition + _RSON_PMK_NOT_AVAILABLE_ = 24, + _RSON_TDLS_TEAR_TOOFAR_ = 25, + _RSON_TDLS_TEAR_UN_RSN_ = 26, +}; + +/* Reason codes (IEEE 802.11-2007, 7.3.1.7, Table 7-22) */ +#if 0 +#define WLAN_REASON_UNSPECIFIED 1 +#define WLAN_REASON_PREV_AUTH_NOT_VALID 2 +#define WLAN_REASON_DEAUTH_LEAVING 3 +#define WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY 4 +#define WLAN_REASON_DISASSOC_AP_BUSY 5 +#define WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6 +#define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7 +#define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8 +#define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9 +#endif +/* IEEE 802.11h */ +#define WLAN_REASON_PWR_CAPABILITY_NOT_VALID 10 +#define WLAN_REASON_SUPPORTED_CHANNEL_NOT_VALID 11 +#if 0 +/* IEEE 802.11i */ +#define WLAN_REASON_INVALID_IE 13 +#define WLAN_REASON_MICHAEL_MIC_FAILURE 14 +#define WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT 15 +#define WLAN_REASON_GROUP_KEY_UPDATE_TIMEOUT 16 +#define WLAN_REASON_IE_IN_4WAY_DIFFERS 17 +#define WLAN_REASON_GROUP_CIPHER_NOT_VALID 18 +#define WLAN_REASON_PAIRWISE_CIPHER_NOT_VALID 19 +#define WLAN_REASON_AKMP_NOT_VALID 20 +#define WLAN_REASON_UNSUPPORTED_RSN_IE_VERSION 21 +#define WLAN_REASON_INVALID_RSN_IE_CAPAB 22 +#define WLAN_REASON_IEEE_802_1X_AUTH_FAILED 23 +#define WLAN_REASON_CIPHER_SUITE_REJECTED 24 +#endif + +enum WIFI_STATUS_CODE { + _STATS_SUCCESSFUL_ = 0, + _STATS_FAILURE_ = 1, + _STATS_SEC_DISABLED_ = 5, + _STATS_NOT_IN_SAME_BSS_ = 7, + _STATS_CAP_FAIL_ = 10, + _STATS_NO_ASOC_ = 11, + _STATS_OTHER_ = 12, + _STATS_NO_SUPP_ALG_ = 13, + _STATS_OUT_OF_AUTH_SEQ_ = 14, + _STATS_CHALLENGE_FAIL_ = 15, + _STATS_AUTH_TIMEOUT_ = 16, + _STATS_UNABLE_HANDLE_STA_ = 17, + _STATS_RATE_FAIL_ = 18, + _STATS_REFUSED_TEMPORARILY_ = 30, + _STATS_DECLINE_REQ_ = 37, + _STATS_INVALID_PARAMETERS_ = 38, + _STATS_INVALID_RSNIE_ = 72, +}; + +/* Status codes (IEEE 802.11-2007, 7.3.1.9, Table 7-23) */ +#if 0 +#define WLAN_STATUS_SUCCESS 0 +#define WLAN_STATUS_UNSPECIFIED_FAILURE 1 +#define WLAN_STATUS_CAPS_UNSUPPORTED 10 +#define WLAN_STATUS_REASSOC_NO_ASSOC 11 +#define WLAN_STATUS_ASSOC_DENIED_UNSPEC 12 +#define WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG 13 +#define WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION 14 +#define WLAN_STATUS_CHALLENGE_FAIL 15 +#define WLAN_STATUS_AUTH_TIMEOUT 16 +#define WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA 17 +#define WLAN_STATUS_ASSOC_DENIED_RATES 18 +#endif +//entended +/* IEEE 802.11b */ +#define WLAN_STATUS_ASSOC_DENIED_NOSHORT 19 +#define WLAN_STATUS_ASSOC_DENIED_NOPBCC 20 +#define WLAN_STATUS_ASSOC_DENIED_NOAGILITY 21 +/* IEEE 802.11h */ +#define WLAN_STATUS_SPEC_MGMT_REQUIRED 22 +#define WLAN_STATUS_PWR_CAPABILITY_NOT_VALID 23 +#define WLAN_STATUS_SUPPORTED_CHANNEL_NOT_VALID 24 +/* IEEE 802.11g */ +#define WLAN_STATUS_ASSOC_DENIED_NO_SHORT_SLOT_TIME 25 +#define WLAN_STATUS_ASSOC_DENIED_NO_ER_PBCC 26 +#define WLAN_STATUS_ASSOC_DENIED_NO_DSSS_OFDM 27 +/* IEEE 802.11w */ +#define WLAN_STATUS_ASSOC_REJECTED_TEMPORARILY 30 +#define WLAN_STATUS_ROBUST_MGMT_FRAME_POLICY_VIOLATION 31 +/* IEEE 802.11i */ +#define WLAN_STATUS_INVALID_IE 40 +#define WLAN_STATUS_GROUP_CIPHER_NOT_VALID 41 +#define WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID 42 +#define WLAN_STATUS_AKMP_NOT_VALID 43 +#define WLAN_STATUS_UNSUPPORTED_RSN_IE_VERSION 44 +#define WLAN_STATUS_INVALID_RSN_IE_CAPAB 45 +#define WLAN_STATUS_CIPHER_REJECTED_PER_POLICY 46 +#define WLAN_STATUS_TS_NOT_CREATED 47 +#define WLAN_STATUS_DIRECT_LINK_NOT_ALLOWED 48 +#define WLAN_STATUS_DEST_STA_NOT_PRESENT 49 +#define WLAN_STATUS_DEST_STA_NOT_QOS_STA 50 +#define WLAN_STATUS_ASSOC_DENIED_LISTEN_INT_TOO_LARGE 51 +/* IEEE 802.11r */ +#define WLAN_STATUS_INVALID_FT_ACTION_FRAME_COUNT 52 +#define WLAN_STATUS_INVALID_PMKID 53 +#define WLAN_STATUS_INVALID_MDIE 54 +#define WLAN_STATUS_INVALID_FTIE 55 + + +enum WIFI_REG_DOMAIN { + DOMAIN_FCC = 1, + DOMAIN_IC = 2, + DOMAIN_ETSI = 3, + DOMAIN_SPAIN = 4, + DOMAIN_FRANCE = 5, + DOMAIN_MKK = 6, + DOMAIN_ISRAEL = 7, + DOMAIN_MKK1 = 8, + DOMAIN_MKK2 = 9, + DOMAIN_MKK3 = 10, + DOMAIN_MAX +}; + +#define _TO_DS_ BIT(8) +#define _FROM_DS_ BIT(9) +#define _MORE_FRAG_ BIT(10) +#define _RETRY_ BIT(11) +#define _PWRMGT_ BIT(12) +#define _MORE_DATA_ BIT(13) +#define _PRIVACY_ BIT(14) +#define _ORDER_ BIT(15) + +#define SetToDs(pbuf) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16(_TO_DS_); \ + } while(0) + +#define GetToDs(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_TO_DS_)) != 0) + +#define ClearToDs(pbuf) \ + do { \ + *(unsigned short *)(pbuf) &= (~cpu_to_le16(_TO_DS_)); \ + } while(0) + +#define SetFrDs(pbuf) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16(_FROM_DS_); \ + } while(0) + +#define GetFrDs(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_FROM_DS_)) != 0) + +#define ClearFrDs(pbuf) \ + do { \ + *(unsigned short *)(pbuf) &= (~cpu_to_le16(_FROM_DS_)); \ + } while(0) + +#define get_tofr_ds(pframe) ((GetToDs(pframe) << 1) | GetFrDs(pframe)) + + +#define SetMFrag(pbuf) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16(_MORE_FRAG_); \ + } while(0) + +#define GetMFrag(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_MORE_FRAG_)) != 0) + +#define ClearMFrag(pbuf) \ + do { \ + *(unsigned short *)(pbuf) &= (~cpu_to_le16(_MORE_FRAG_)); \ + } while(0) + +#define SetRetry(pbuf) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16(_RETRY_); \ + } while(0) + +#define GetRetry(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_RETRY_)) != 0) + +#define ClearRetry(pbuf) \ + do { \ + *(unsigned short *)(pbuf) &= (~cpu_to_le16(_RETRY_)); \ + } while(0) + +#define SetPwrMgt(pbuf) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16(_PWRMGT_); \ + } while(0) + +#define GetPwrMgt(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_PWRMGT_)) != 0) + +#define ClearPwrMgt(pbuf) \ + do { \ + *(unsigned short *)(pbuf) &= (~cpu_to_le16(_PWRMGT_)); \ + } while(0) + +#define SetMData(pbuf) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16(_MORE_DATA_); \ + } while(0) + +#define GetMData(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_MORE_DATA_)) != 0) + +#define ClearMData(pbuf) \ + do { \ + *(unsigned short *)(pbuf) &= (~cpu_to_le16(_MORE_DATA_)); \ + } while(0) + +#define SetPrivacy(pbuf) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16(_PRIVACY_); \ + } while(0) + +#define GetPrivacy(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_PRIVACY_)) != 0) + +#define ClearPrivacy(pbuf) \ + do { \ + *(unsigned short *)(pbuf) &= (~cpu_to_le16(_PRIVACY_)); \ + } while(0) + + +#define GetOrder(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_ORDER_)) != 0) + +#define GetFrameType(pbuf) (le16_to_cpu(*(unsigned short *)(pbuf)) & (BIT(3) | BIT(2))) + +#define SetFrameType(pbuf,type) \ + do { \ + *(unsigned short *)(pbuf) &= __constant_cpu_to_le16(~(BIT(3) | BIT(2))); \ + *(unsigned short *)(pbuf) |= __constant_cpu_to_le16(type); \ + } while(0) + +#define GetFrameSubType(pbuf) (cpu_to_le16(*(unsigned short *)(pbuf)) & (BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2))) + +#define SetFrameSubType(pbuf,type) \ + do { \ + *(unsigned short *)(pbuf) &= cpu_to_le16(~(BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2))); \ + *(unsigned short *)(pbuf) |= cpu_to_le16(type); \ + } while(0) + +#define GetSequence(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) >> 4) + +#define GetFragNum(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & 0x0f) + +#define GetTupleCache(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22))) + +#define SetFragNum(pbuf, num) \ + do { \ + *(unsigned short *)((SIZE_PTR)(pbuf) + 22) = \ + ((*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & le16_to_cpu(~(0x000f))) | \ + cpu_to_le16(0x0f & (num)); \ + } while(0) + +#define SetSeqNum(pbuf, num) \ + do { \ + *(unsigned short *)((SIZE_PTR)(pbuf) + 22) = \ + ((*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & le16_to_cpu((unsigned short)~0xfff0)) | \ + le16_to_cpu((unsigned short)(0xfff0 & (num << 4))); \ + } while(0) + +#define SetDuration(pbuf, dur) \ + do { \ + *(unsigned short *)((SIZE_PTR)(pbuf) + 2) = cpu_to_le16(0xffff & (dur)); \ + } while(0) + + +#define SetPriority(pbuf, tid) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16(tid & 0xf); \ + } while(0) + +#define GetPriority(pbuf) ((le16_to_cpu(*(unsigned short *)(pbuf))) & 0xf) + +#define SetEOSP(pbuf, eosp) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16( (eosp & 1) << 4); \ + } while(0) + +#define SetAckpolicy(pbuf, ack) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16( (ack & 3) << 5); \ + } while(0) + +#define GetAckpolicy(pbuf) (((le16_to_cpu(*(unsigned short *)pbuf)) >> 5) & 0x3) + +#define GetAMsdu(pbuf) (((le16_to_cpu(*(unsigned short *)pbuf)) >> 7) & 0x1) + +#define SetAMsdu(pbuf, amsdu) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16( (amsdu & 1) << 7); \ + } while(0) + +#define GetAid(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 2)) & 0x3fff) + +#define GetTid(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + (((GetToDs(pbuf)<<1)|GetFrDs(pbuf))==3?30:24))) & 0x000f) + +#define GetAddr1Ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 4)) + +#define GetAddr2Ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 10)) + +#define GetAddr3Ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 16)) + +#define GetAddr4Ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 24)) + +#define MacAddr_isBcst(addr) \ +( \ + ( (addr[0] == 0xff) && (addr[1] == 0xff) && \ + (addr[2] == 0xff) && (addr[3] == 0xff) && \ + (addr[4] == 0xff) && (addr[5] == 0xff) ) ? _TRUE : _FALSE \ +) + +__inline static int IS_MCAST(unsigned char *da) +{ + if ((*da) & 0x01) + return _TRUE; + else + return _FALSE; +} + +__inline static unsigned char * get_ra(unsigned char *pframe) +{ + unsigned char *ra; + ra = GetAddr1Ptr(pframe); + return ra; +} +__inline static unsigned char * get_ta(unsigned char *pframe) +{ + unsigned char *ta; + ta = GetAddr2Ptr(pframe); + return ta; +} + +__inline static unsigned char * get_da(unsigned char *pframe) +{ + unsigned char *da; + unsigned int to_fr_ds = (GetToDs(pframe) << 1) | GetFrDs(pframe); + + switch (to_fr_ds) { + case 0x00: // ToDs=0, FromDs=0 + da = GetAddr1Ptr(pframe); + break; + case 0x01: // ToDs=0, FromDs=1 + da = GetAddr1Ptr(pframe); + break; + case 0x02: // ToDs=1, FromDs=0 + da = GetAddr3Ptr(pframe); + break; + default: // ToDs=1, FromDs=1 + da = GetAddr3Ptr(pframe); + break; + } + + return da; +} + + +__inline static unsigned char * get_sa(unsigned char *pframe) +{ + unsigned char *sa; + unsigned int to_fr_ds = (GetToDs(pframe) << 1) | GetFrDs(pframe); + + switch (to_fr_ds) { + case 0x00: // ToDs=0, FromDs=0 + sa = GetAddr2Ptr(pframe); + break; + case 0x01: // ToDs=0, FromDs=1 + sa = GetAddr3Ptr(pframe); + break; + case 0x02: // ToDs=1, FromDs=0 + sa = GetAddr2Ptr(pframe); + break; + default: // ToDs=1, FromDs=1 + sa = GetAddr4Ptr(pframe); + break; + } + + return sa; +} + +__inline static unsigned char * get_hdr_bssid(unsigned char *pframe) +{ + unsigned char *sa = NULL; + unsigned int to_fr_ds = (GetToDs(pframe) << 1) | GetFrDs(pframe); + + switch (to_fr_ds) { + case 0x00: // ToDs=0, FromDs=0 + sa = GetAddr3Ptr(pframe); + break; + case 0x01: // ToDs=0, FromDs=1 + sa = GetAddr2Ptr(pframe); + break; + case 0x02: // ToDs=1, FromDs=0 + sa = GetAddr1Ptr(pframe); + break; + case 0x03: // ToDs=1, FromDs=1 + sa = GetAddr1Ptr(pframe); + break; + } + + return sa; +} + + +__inline static int IsFrameTypeCtrl(unsigned char *pframe) +{ + if(WIFI_CTRL_TYPE == GetFrameType(pframe)) + return _TRUE; + else + return _FALSE; +} +/*----------------------------------------------------------------------------- + Below is for the security related definition +------------------------------------------------------------------------------*/ +#define _RESERVED_FRAME_TYPE_ 0 +#define _SKB_FRAME_TYPE_ 2 +#define _PRE_ALLOCMEM_ 1 +#define _PRE_ALLOCHDR_ 3 +#define _PRE_ALLOCLLCHDR_ 4 +#define _PRE_ALLOCICVHDR_ 5 +#define _PRE_ALLOCMICHDR_ 6 + +#define _SIFSTIME_ ((priv->pmib->dot11BssType.net_work_type&WIRELESS_11A)?16:10) +#define _ACKCTSLNG_ 14 //14 bytes long, including crclng +#define _CRCLNG_ 4 + +#define _ASOCREQ_IE_OFFSET_ 4 // excluding wlan_hdr +#define _ASOCRSP_IE_OFFSET_ 6 +#define _REASOCREQ_IE_OFFSET_ 10 +#define _REASOCRSP_IE_OFFSET_ 6 +#define _PROBEREQ_IE_OFFSET_ 0 +#define _PROBERSP_IE_OFFSET_ 12 +#define _AUTH_IE_OFFSET_ 6 +#define _DEAUTH_IE_OFFSET_ 0 +#define _BEACON_IE_OFFSET_ 12 +#define _PUBLIC_ACTION_IE_OFFSET_ 8 + +#define _FIXED_IE_LENGTH_ _BEACON_IE_OFFSET_ + +#define _SSID_IE_ 0 +#define _SUPPORTEDRATES_IE_ 1 +#define _DSSET_IE_ 3 +#define _TIM_IE_ 5 +#define _IBSS_PARA_IE_ 6 +#define _COUNTRY_IE_ 7 +#define _CHLGETXT_IE_ 16 +#define _SUPPORTED_CH_IE_ 36 +#define _CH_SWTICH_ANNOUNCE_ 37 //Secondary Channel Offset +#define _RSN_IE_2_ 48 +#define _SSN_IE_1_ 221 +#define _ERPINFO_IE_ 42 +#define _EXT_SUPPORTEDRATES_IE_ 50 + +#define _HT_CAPABILITY_IE_ 45 +#define _FTIE_ 55 +#define _TIMEOUT_ITVL_IE_ 56 +#define _SRC_IE_ 59 +#define _HT_EXTRA_INFO_IE_ 61 +#define _HT_ADD_INFO_IE_ 61 //_HT_EXTRA_INFO_IE_ +#define _WAPI_IE_ 68 + + +//#define EID_BSSCoexistence 72 // 20/40 BSS Coexistence +//#define EID_BSSIntolerantChlReport 73 +#define _RIC_Descriptor_IE_ 75 +#ifdef CONFIG_IEEE80211W +#define _MME_IE_ 76 //802.11w Management MIC element +#endif //CONFIG_IEEE80211W +#define _LINK_ID_IE_ 101 +#define _CH_SWITCH_TIMING_ 104 +#define _PTI_BUFFER_STATUS_ 106 +#define _EXT_CAP_IE_ 127 +#define _VENDOR_SPECIFIC_IE_ 221 + +#define _RESERVED47_ 47 + +typedef enum _ELEMENT_ID{ + EID_SsId = 0, /* service set identifier (0:32) */ + EID_SupRates = 1, /* supported rates (1:8) */ + EID_FHParms = 2, /* FH parameter set (5) */ + EID_DSParms = 3, /* DS parameter set (1) */ + EID_CFParms = 4, /* CF parameter set (6) */ + EID_Tim = 5, /* Traffic Information Map (4:254) */ + EID_IbssParms = 6, /* IBSS parameter set (2) */ + EID_Country = 7, /* */ + + // Form 7.3.2: Information elements in 802.11E/D13.0, page 46. + EID_QBSSLoad = 11, + EID_EDCAParms = 12, + EID_TSpec = 13, + EID_TClass = 14, + EID_Schedule = 15, + // + + EID_Ctext = 16, /* challenge text*/ + EID_POWER_CONSTRAINT = 32, /* Power Constraint*/ + + //vivi for WIFITest, 802.11h AP, 20100427 + // 2010/12/26 MH The definition we can declare always!! + EID_PowerCap = 33, + EID_SupportedChannels = 36, + EID_ChlSwitchAnnounce = 37, + + EID_MeasureRequest = 38, // Measurement Request + EID_MeasureReport = 39, // Measurement Report + + EID_ERPInfo = 42, + + // Form 7.3.2: Information elements in 802.11E/D13.0, page 46. + EID_TSDelay = 43, + EID_TCLASProc = 44, + EID_HTCapability = 45, + EID_QoSCap = 46, + // + + EID_WPA2 = 48, + EID_ExtSupRates = 50, + + EID_FTIE = 55, // Defined in 802.11r + EID_Timeout = 56, // Defined in 802.11r + + EID_SupRegulatory = 59, // Supported Requlatory Classes 802.11y + EID_HTInfo = 61, + EID_SecondaryChnlOffset = 62, + + EID_BSSCoexistence = 72, // 20/40 BSS Coexistence + EID_BSSIntolerantChlReport = 73, + EID_OBSS = 74, // Overlapping BSS Scan Parameters + + EID_LinkIdentifier = 101, // Defined in 802.11z + EID_WakeupSchedule = 102, // Defined in 802.11z + EID_ChnlSwitchTimeing = 104, // Defined in 802.11z + EID_PTIControl = 105, // Defined in 802.11z + EID_PUBufferStatus = 106, // Defined in 802.11z + + EID_EXTCapability = 127, // Extended Capabilities + // From S19:Aironet IE and S21:AP IP address IE in CCX v1.13, p16 and p18. + EID_Aironet = 133, // 0x85: Aironet Element for Cisco CCX + EID_CiscoIP = 149, // 0x95: IP Address IE for Cisco CCX + + EID_CellPwr = 150, // 0x96: Cell Power Limit IE. Ref. 0x96. + + EID_CCKM = 156, + + EID_Vendor = 221, // 0xDD: Vendor Specific + + EID_WAPI = 68, + EID_VHTCapability = 191, // Based on 802.11ac D2.0 + EID_VHTOperation = 192, // Based on 802.11ac D2.0 + EID_AID = 197, /* Based on 802.11ac D4.0 */ + EID_OpModeNotification = 199, // Based on 802.11ac D3.0 +}ELEMENT_ID, *PELEMENT_ID; + +/* --------------------------------------------------------------------------- + Below is the fixed elements... +-----------------------------------------------------------------------------*/ +#define _AUTH_ALGM_NUM_ 2 +#define _AUTH_SEQ_NUM_ 2 +#define _BEACON_ITERVAL_ 2 +#define _CAPABILITY_ 2 +#define _CURRENT_APADDR_ 6 +#define _LISTEN_INTERVAL_ 2 +#define _RSON_CODE_ 2 +#define _ASOC_ID_ 2 +#define _STATUS_CODE_ 2 +#define _TIMESTAMP_ 8 + +#define AUTH_ODD_TO 0 +#define AUTH_EVEN_TO 1 + +#define WLAN_ETHCONV_ENCAP 1 +#define WLAN_ETHCONV_RFC1042 2 +#define WLAN_ETHCONV_8021h 3 + +#define cap_ESS BIT(0) +#define cap_IBSS BIT(1) +#define cap_CFPollable BIT(2) +#define cap_CFRequest BIT(3) +#define cap_Privacy BIT(4) +#define cap_ShortPremble BIT(5) +#define cap_PBCC BIT(6) +#define cap_ChAgility BIT(7) +#define cap_SpecMgmt BIT(8) +#define cap_QoS BIT(9) +#define cap_ShortSlot BIT(10) + +/*----------------------------------------------------------------------------- + Below is the definition for 802.11i / 802.1x +------------------------------------------------------------------------------*/ +#define _IEEE8021X_MGT_ 1 // WPA +#define _IEEE8021X_PSK_ 2 // WPA with pre-shared key + +/* +#define _NO_PRIVACY_ 0 +#define _WEP_40_PRIVACY_ 1 +#define _TKIP_PRIVACY_ 2 +#define _WRAP_PRIVACY_ 3 +#define _CCMP_PRIVACY_ 4 +#define _WEP_104_PRIVACY_ 5 +#define _WEP_WPA_MIXED_PRIVACY_ 6 // WEP + WPA +*/ + +#ifdef CONFIG_IEEE80211W +#define _MME_IE_LENGTH_ 18 +#endif //CONFIG_IEEE80211W +/*----------------------------------------------------------------------------- + Below is the definition for WMM +------------------------------------------------------------------------------*/ +#define _WMM_IE_Length_ 7 // for WMM STA +#define _WMM_Para_Element_Length_ 24 + + +/*----------------------------------------------------------------------------- + Below is the definition for 802.11n +------------------------------------------------------------------------------*/ + +//#ifdef CONFIG_80211N_HT + +#define SetOrderBit(pbuf) \ + do { \ + *(unsigned short *)(pbuf) |= cpu_to_le16(_ORDER_); \ + } while(0) + +#define GetOrderBit(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_ORDER_)) != 0) + +#define ACT_CAT_VENDOR 0x7F/* 127 */ + +/** + * struct rtw_ieee80211_bar - HT Block Ack Request + * + * This structure refers to "HT BlockAckReq" as + * described in 802.11n draft section 7.2.1.7.1 + */ + #if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8712FW) +struct rtw_ieee80211_bar { + unsigned short frame_control; + unsigned short duration; + unsigned char ra[6]; + unsigned char ta[6]; + unsigned short control; + unsigned short start_seq_num; +} __attribute__((packed)); + #endif + +/* 802.11 BAR control masks */ +#define IEEE80211_BAR_CTRL_ACK_POLICY_NORMAL 0x0000 +#define IEEE80211_BAR_CTRL_CBMTID_COMPRESSED_BA 0x0004 + + + #if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8712FW) || defined(PLATFORM_FREEBSD) + + + + /** + * struct rtw_ieee80211_ht_cap - HT capabilities + * + * This structure refers to "HT capabilities element" as + * described in 802.11n draft section 7.3.2.52 + */ + +struct rtw_ieee80211_ht_cap { + unsigned short cap_info; + unsigned char ampdu_params_info; + unsigned char supp_mcs_set[16]; + unsigned short extended_ht_cap_info; + unsigned int tx_BF_cap_info; + unsigned char antenna_selection_info; +} __attribute__ ((packed)); + +/** + * struct rtw_ieee80211_ht_cap - HT additional information + * + * This structure refers to "HT information element" as + * described in 802.11n draft section 7.3.2.53 + */ +struct ieee80211_ht_addt_info { + unsigned char control_chan; + unsigned char ht_param; + unsigned short operation_mode; + unsigned short stbc_param; + unsigned char basic_set[16]; +} __attribute__ ((packed)); + + +struct HT_caps_element +{ + union + { + struct + { + unsigned short HT_caps_info; + unsigned char AMPDU_para; + unsigned char MCS_rate[16]; + unsigned short HT_ext_caps; + unsigned int Beamforming_caps; + unsigned char ASEL_caps; + } HT_cap_element; + unsigned char HT_cap[26]; + }u; +} __attribute__ ((packed)); + +struct HT_info_element +{ + unsigned char primary_channel; + unsigned char infos[5]; + unsigned char MCS_rate[16]; +} __attribute__ ((packed)); + +struct AC_param +{ + unsigned char ACI_AIFSN; + unsigned char CW; + unsigned short TXOP_limit; +} __attribute__ ((packed)); + +struct WMM_para_element +{ + unsigned char QoS_info; + unsigned char reserved; + struct AC_param ac_param[4]; +} __attribute__ ((packed)); + +struct ADDBA_request +{ + unsigned char dialog_token; + unsigned short BA_para_set; + unsigned short BA_timeout_value; + unsigned short BA_starting_seqctrl; +} __attribute__ ((packed)); + + + +#endif + + +#ifdef PLATFORM_WINDOWS + +#pragma pack(1) + +struct rtw_ieee80211_ht_cap { + unsigned short cap_info; + unsigned char ampdu_params_info; + unsigned char supp_mcs_set[16]; + unsigned short extended_ht_cap_info; + unsigned int tx_BF_cap_info; + unsigned char antenna_selection_info; +}; + + +struct ieee80211_ht_addt_info { + unsigned char control_chan; + unsigned char ht_param; + unsigned short operation_mode; + unsigned short stbc_param; + unsigned char basic_set[16]; +}; + +struct HT_caps_element +{ + union + { + struct + { + unsigned short HT_caps_info; + unsigned char AMPDU_para; + unsigned char MCS_rate[16]; + unsigned short HT_ext_caps; + unsigned int Beamforming_caps; + unsigned char ASEL_caps; + } HT_cap_element; + unsigned char HT_cap[26]; + }; +}; + +struct HT_info_element +{ + unsigned char primary_channel; + unsigned char infos[5]; + unsigned char MCS_rate[16]; +}; + +struct AC_param +{ + unsigned char ACI_AIFSN; + unsigned char CW; + unsigned short TXOP_limit; +}; + +struct WMM_para_element +{ + unsigned char QoS_info; + unsigned char reserved; + struct AC_param ac_param[4]; +}; + +struct ADDBA_request +{ + unsigned char dialog_token; + unsigned short BA_para_set; + unsigned short BA_timeout_value; + unsigned short BA_starting_seqctrl; +}; + + +#pragma pack() + +#endif + +typedef enum _HT_CAP_AMPDU_FACTOR { + MAX_AMPDU_FACTOR_8K = 0, + MAX_AMPDU_FACTOR_16K = 1, + MAX_AMPDU_FACTOR_32K = 2, + MAX_AMPDU_FACTOR_64K = 3, +}HT_CAP_AMPDU_FACTOR; + + +typedef enum _HT_CAP_AMPDU_DENSITY { + AMPDU_DENSITY_VALUE_0 = 0 , /* For no restriction */ + AMPDU_DENSITY_VALUE_1 = 1 , /* For 1/4 us */ + AMPDU_DENSITY_VALUE_2 = 2 , /* For 1/2 us */ + AMPDU_DENSITY_VALUE_3 = 3 , /* For 1 us */ + AMPDU_DENSITY_VALUE_4 = 4 , /* For 2 us */ + AMPDU_DENSITY_VALUE_5 = 5 , /* For 4 us */ + AMPDU_DENSITY_VALUE_6 = 6 , /* For 8 us */ + AMPDU_DENSITY_VALUE_7 = 7 , /* For 16 us */ +} HT_CAP_AMPDU_DENSITY; + +/* 802.11n HT capabilities masks */ +#define IEEE80211_HT_CAP_LDPC_CODING 0x0001 +#define IEEE80211_HT_CAP_SUP_WIDTH 0x0002 +#define IEEE80211_HT_CAP_SM_PS 0x000C +#define IEEE80211_HT_CAP_GRN_FLD 0x0010 +#define IEEE80211_HT_CAP_SGI_20 0x0020 +#define IEEE80211_HT_CAP_SGI_40 0x0040 +#define IEEE80211_HT_CAP_TX_STBC 0x0080 +#define IEEE80211_HT_CAP_RX_STBC_1R 0x0100 +#define IEEE80211_HT_CAP_RX_STBC_2R 0x0200 +#define IEEE80211_HT_CAP_RX_STBC_3R 0x0300 +#define IEEE80211_HT_CAP_DELAY_BA 0x0400 +#define IEEE80211_HT_CAP_MAX_AMSDU 0x0800 +#define IEEE80211_HT_CAP_DSSSCCK40 0x1000 +#define RTW_IEEE80211_HT_CAP_40MHZ_INTOLERANT ((u16) BIT(14)) +/* 802.11n HT capability AMPDU settings */ +#define IEEE80211_HT_CAP_AMPDU_FACTOR 0x03 +#define IEEE80211_HT_CAP_AMPDU_DENSITY 0x1C +/* 802.11n HT capability MSC set */ +#define IEEE80211_SUPP_MCS_SET_UEQM 4 +#define IEEE80211_HT_CAP_MAX_STREAMS 4 +#define IEEE80211_SUPP_MCS_SET_LEN 10 +/* maximum streams the spec allows */ +#define IEEE80211_HT_CAP_MCS_TX_DEFINED 0x01 +#define IEEE80211_HT_CAP_MCS_TX_RX_DIFF 0x02 +#define IEEE80211_HT_CAP_MCS_TX_STREAMS 0x0C +#define IEEE80211_HT_CAP_MCS_TX_UEQM 0x10 +/* 802.11n HT capability TXBF capability */ +#define IEEE80211_HT_CAP_TXBF_RX_NDP 0x00000008 +#define IEEE80211_HT_CAP_TXBF_TX_NDP 0x00000010 +#define IEEE80211_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP 0x00000400 + +/* 802.11n HT IE masks */ +#define IEEE80211_HT_IE_CHA_SEC_OFFSET 0x03 +#define IEEE80211_HT_IE_CHA_SEC_NONE 0x00 +#define IEEE80211_HT_IE_CHA_SEC_ABOVE 0x01 +#define IEEE80211_HT_IE_CHA_SEC_BELOW 0x03 +#define IEEE80211_HT_IE_CHA_WIDTH 0x04 +#define IEEE80211_HT_IE_HT_PROTECTION 0x0003 +#define IEEE80211_HT_IE_NON_GF_STA_PRSNT 0x0004 +#define IEEE80211_HT_IE_NON_HT_STA_PRSNT 0x0010 + +/* block-ack parameters */ +#define IEEE80211_ADDBA_PARAM_POLICY_MASK 0x0002 +#define IEEE80211_ADDBA_PARAM_TID_MASK 0x003C +#define RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK 0xFFC0 +#define IEEE80211_DELBA_PARAM_TID_MASK 0xF000 +#define IEEE80211_DELBA_PARAM_INITIATOR_MASK 0x0800 + + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 18, 0)) + +/* + * A-PMDU buffer sizes + * According to IEEE802.11n spec size varies from 8K to 64K (in powers of 2) + */ +#define IEEE80211_MIN_AMPDU_BUF 0x8 +#define IEEE80211_MAX_AMPDU_BUF 0x40 +#endif + + +/* Spatial Multiplexing Power Save Modes */ +#define WLAN_HT_CAP_SM_PS_STATIC 0 +#define WLAN_HT_CAP_SM_PS_DYNAMIC 1 +#define WLAN_HT_CAP_SM_PS_INVALID 2 +#define WLAN_HT_CAP_SM_PS_DISABLED 3 + + +#define OP_MODE_PURE 0 +#define OP_MODE_MAY_BE_LEGACY_STAS 1 +#define OP_MODE_20MHZ_HT_STA_ASSOCED 2 +#define OP_MODE_MIXED 3 + +#define HT_INFO_HT_PARAM_SECONDARY_CHNL_OFF_MASK ((u8) BIT(0) | BIT(1)) +#define HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE ((u8) BIT(0)) +#define HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW ((u8) BIT(0) | BIT(1)) +#define HT_INFO_HT_PARAM_REC_TRANS_CHNL_WIDTH ((u8) BIT(2)) +#define HT_INFO_HT_PARAM_RIFS_MODE ((u8) BIT(3)) +#define HT_INFO_HT_PARAM_CTRL_ACCESS_ONLY ((u8) BIT(4)) +#define HT_INFO_HT_PARAM_SRV_INTERVAL_GRANULARITY ((u8) BIT(5)) + +#define HT_INFO_OPERATION_MODE_OP_MODE_MASK \ + ((u16) (0x0001 | 0x0002)) +#define HT_INFO_OPERATION_MODE_OP_MODE_OFFSET 0 +#define HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT ((u8) BIT(2)) +#define HT_INFO_OPERATION_MODE_TRANSMIT_BURST_LIMIT ((u8) BIT(3)) +#define HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT ((u8) BIT(4)) + +#define HT_INFO_STBC_PARAM_DUAL_BEACON ((u16) BIT(6)) +#define HT_INFO_STBC_PARAM_DUAL_STBC_PROTECT ((u16) BIT(7)) +#define HT_INFO_STBC_PARAM_SECONDARY_BCN ((u16) BIT(8)) +#define HT_INFO_STBC_PARAM_LSIG_TXOP_PROTECT_ALLOWED ((u16) BIT(9)) +#define HT_INFO_STBC_PARAM_PCO_ACTIVE ((u16) BIT(10)) +#define HT_INFO_STBC_PARAM_PCO_PHASE ((u16) BIT(11)) + + + +//#endif + +// ===============WPS Section=============== +// For WPSv1.0 +#define WPSOUI 0x0050f204 +// WPS attribute ID +#define WPS_ATTR_VER1 0x104A +#define WPS_ATTR_SIMPLE_CONF_STATE 0x1044 +#define WPS_ATTR_RESP_TYPE 0x103B +#define WPS_ATTR_UUID_E 0x1047 +#define WPS_ATTR_MANUFACTURER 0x1021 +#define WPS_ATTR_MODEL_NAME 0x1023 +#define WPS_ATTR_MODEL_NUMBER 0x1024 +#define WPS_ATTR_SERIAL_NUMBER 0x1042 +#define WPS_ATTR_PRIMARY_DEV_TYPE 0x1054 +#define WPS_ATTR_SEC_DEV_TYPE_LIST 0x1055 +#define WPS_ATTR_DEVICE_NAME 0x1011 +#define WPS_ATTR_CONF_METHOD 0x1008 +#define WPS_ATTR_RF_BANDS 0x103C +#define WPS_ATTR_DEVICE_PWID 0x1012 +#define WPS_ATTR_REQUEST_TYPE 0x103A +#define WPS_ATTR_ASSOCIATION_STATE 0x1002 +#define WPS_ATTR_CONFIG_ERROR 0x1009 +#define WPS_ATTR_VENDOR_EXT 0x1049 +#define WPS_ATTR_SELECTED_REGISTRAR 0x1041 + +// Value of WPS attribute "WPS_ATTR_DEVICE_NAME +#define WPS_MAX_DEVICE_NAME_LEN 32 + +// Value of WPS Request Type Attribute +#define WPS_REQ_TYPE_ENROLLEE_INFO_ONLY 0x00 +#define WPS_REQ_TYPE_ENROLLEE_OPEN_8021X 0x01 +#define WPS_REQ_TYPE_REGISTRAR 0x02 +#define WPS_REQ_TYPE_WLAN_MANAGER_REGISTRAR 0x03 + +// Value of WPS Response Type Attribute +#define WPS_RESPONSE_TYPE_INFO_ONLY 0x00 +#define WPS_RESPONSE_TYPE_8021X 0x01 +#define WPS_RESPONSE_TYPE_REGISTRAR 0x02 +#define WPS_RESPONSE_TYPE_AP 0x03 + +// Value of WPS WiFi Simple Configuration State Attribute +#define WPS_WSC_STATE_NOT_CONFIG 0x01 +#define WPS_WSC_STATE_CONFIG 0x02 + +// Value of WPS Version Attribute +#define WPS_VERSION_1 0x10 + +// Value of WPS Configuration Method Attribute +#define WPS_CONFIG_METHOD_FLASH 0x0001 +#define WPS_CONFIG_METHOD_ETHERNET 0x0002 +#define WPS_CONFIG_METHOD_LABEL 0x0004 +#define WPS_CONFIG_METHOD_DISPLAY 0x0008 +#define WPS_CONFIG_METHOD_E_NFC 0x0010 +#define WPS_CONFIG_METHOD_I_NFC 0x0020 +#define WPS_CONFIG_METHOD_NFC 0x0040 +#define WPS_CONFIG_METHOD_PBC 0x0080 +#define WPS_CONFIG_METHOD_KEYPAD 0x0100 +#define WPS_CONFIG_METHOD_VPBC 0x0280 +#define WPS_CONFIG_METHOD_PPBC 0x0480 +#define WPS_CONFIG_METHOD_VDISPLAY 0x2008 +#define WPS_CONFIG_METHOD_PDISPLAY 0x4008 + +// Value of Category ID of WPS Primary Device Type Attribute +#define WPS_PDT_CID_DISPLAYS 0x0007 +#define WPS_PDT_CID_MULIT_MEDIA 0x0008 +#define WPS_PDT_CID_RTK_WIDI WPS_PDT_CID_MULIT_MEDIA + +// Value of Sub Category ID of WPS Primary Device Type Attribute +#define WPS_PDT_SCID_MEDIA_SERVER 0x0005 +#define WPS_PDT_SCID_RTK_DMP WPS_PDT_SCID_MEDIA_SERVER + +// Value of Device Password ID +#define WPS_DPID_PIN 0x0000 +#define WPS_DPID_USER_SPEC 0x0001 +#define WPS_DPID_MACHINE_SPEC 0x0002 +#define WPS_DPID_REKEY 0x0003 +#define WPS_DPID_PBC 0x0004 +#define WPS_DPID_REGISTRAR_SPEC 0x0005 + +// Value of WPS RF Bands Attribute +#define WPS_RF_BANDS_2_4_GHZ 0x01 +#define WPS_RF_BANDS_5_GHZ 0x02 + +// Value of WPS Association State Attribute +#define WPS_ASSOC_STATE_NOT_ASSOCIATED 0x00 +#define WPS_ASSOC_STATE_CONNECTION_SUCCESS 0x01 +#define WPS_ASSOC_STATE_CONFIGURATION_FAILURE 0x02 +#define WPS_ASSOC_STATE_ASSOCIATION_FAILURE 0x03 +#define WPS_ASSOC_STATE_IP_FAILURE 0x04 + +// =====================P2P Section===================== +// For P2P +#define P2POUI 0x506F9A09 + +// P2P Attribute ID +#define P2P_ATTR_STATUS 0x00 +#define P2P_ATTR_MINOR_REASON_CODE 0x01 +#define P2P_ATTR_CAPABILITY 0x02 +#define P2P_ATTR_DEVICE_ID 0x03 +#define P2P_ATTR_GO_INTENT 0x04 +#define P2P_ATTR_CONF_TIMEOUT 0x05 +#define P2P_ATTR_LISTEN_CH 0x06 +#define P2P_ATTR_GROUP_BSSID 0x07 +#define P2P_ATTR_EX_LISTEN_TIMING 0x08 +#define P2P_ATTR_INTENTED_IF_ADDR 0x09 +#define P2P_ATTR_MANAGEABILITY 0x0A +#define P2P_ATTR_CH_LIST 0x0B +#define P2P_ATTR_NOA 0x0C +#define P2P_ATTR_DEVICE_INFO 0x0D +#define P2P_ATTR_GROUP_INFO 0x0E +#define P2P_ATTR_GROUP_ID 0x0F +#define P2P_ATTR_INTERFACE 0x10 +#define P2P_ATTR_OPERATING_CH 0x11 +#define P2P_ATTR_INVITATION_FLAGS 0x12 + +// Value of Status Attribute +#define P2P_STATUS_SUCCESS 0x00 +#define P2P_STATUS_FAIL_INFO_UNAVAILABLE 0x01 +#define P2P_STATUS_FAIL_INCOMPATIBLE_PARAM 0x02 +#define P2P_STATUS_FAIL_LIMIT_REACHED 0x03 +#define P2P_STATUS_FAIL_INVALID_PARAM 0x04 +#define P2P_STATUS_FAIL_REQUEST_UNABLE 0x05 +#define P2P_STATUS_FAIL_PREVOUS_PROTO_ERR 0x06 +#define P2P_STATUS_FAIL_NO_COMMON_CH 0x07 +#define P2P_STATUS_FAIL_UNKNOWN_P2PGROUP 0x08 +#define P2P_STATUS_FAIL_BOTH_GOINTENT_15 0x09 +#define P2P_STATUS_FAIL_INCOMPATIBLE_PROVSION 0x0A +#define P2P_STATUS_FAIL_USER_REJECT 0x0B + +// Value of Inviation Flags Attribute +#define P2P_INVITATION_FLAGS_PERSISTENT BIT(0) + +#define DMP_P2P_DEVCAP_SUPPORT (P2P_DEVCAP_SERVICE_DISCOVERY | \ + P2P_DEVCAP_CLIENT_DISCOVERABILITY | \ + P2P_DEVCAP_CONCURRENT_OPERATION | \ + P2P_DEVCAP_INVITATION_PROC) + +#define DMP_P2P_GRPCAP_SUPPORT (P2P_GRPCAP_INTRABSS) + +// Value of Device Capability Bitmap +#define P2P_DEVCAP_SERVICE_DISCOVERY BIT(0) +#define P2P_DEVCAP_CLIENT_DISCOVERABILITY BIT(1) +#define P2P_DEVCAP_CONCURRENT_OPERATION BIT(2) +#define P2P_DEVCAP_INFRA_MANAGED BIT(3) +#define P2P_DEVCAP_DEVICE_LIMIT BIT(4) +#define P2P_DEVCAP_INVITATION_PROC BIT(5) + +// Value of Group Capability Bitmap +#define P2P_GRPCAP_GO BIT(0) +#define P2P_GRPCAP_PERSISTENT_GROUP BIT(1) +#define P2P_GRPCAP_GROUP_LIMIT BIT(2) +#define P2P_GRPCAP_INTRABSS BIT(3) +#define P2P_GRPCAP_CROSS_CONN BIT(4) +#define P2P_GRPCAP_PERSISTENT_RECONN BIT(5) +#define P2P_GRPCAP_GROUP_FORMATION BIT(6) + +// P2P Public Action Frame ( Management Frame ) +#define P2P_PUB_ACTION_ACTION 0x09 + +// P2P Public Action Frame Type +#define P2P_GO_NEGO_REQ 0 +#define P2P_GO_NEGO_RESP 1 +#define P2P_GO_NEGO_CONF 2 +#define P2P_INVIT_REQ 3 +#define P2P_INVIT_RESP 4 +#define P2P_DEVDISC_REQ 5 +#define P2P_DEVDISC_RESP 6 +#define P2P_PROVISION_DISC_REQ 7 +#define P2P_PROVISION_DISC_RESP 8 + +// P2P Action Frame Type +#define P2P_NOTICE_OF_ABSENCE 0 +#define P2P_PRESENCE_REQUEST 1 +#define P2P_PRESENCE_RESPONSE 2 +#define P2P_GO_DISC_REQUEST 3 + + +#define P2P_MAX_PERSISTENT_GROUP_NUM 10 + +#define P2P_PROVISIONING_SCAN_CNT 3 + +#define P2P_WILDCARD_SSID_LEN 7 + +#define P2P_FINDPHASE_EX_NONE 0 // default value, used when: (1)p2p disabed or (2)p2p enabled but only do 1 scan phase +#define P2P_FINDPHASE_EX_FULL 1 // used when p2p enabled and want to do 1 scan phase and P2P_FINDPHASE_EX_MAX-1 find phase +#define P2P_FINDPHASE_EX_SOCIAL_FIRST (P2P_FINDPHASE_EX_FULL+1) +#define P2P_FINDPHASE_EX_MAX 4 +#define P2P_FINDPHASE_EX_SOCIAL_LAST P2P_FINDPHASE_EX_MAX + +#define P2P_PROVISION_TIMEOUT 5000 // 5 seconds timeout for sending the provision discovery request +#define P2P_CONCURRENT_PROVISION_TIMEOUT 3000 // 3 seconds timeout for sending the provision discovery request under concurrent mode +#define P2P_GO_NEGO_TIMEOUT 5000 // 5 seconds timeout for receiving the group negotation response +#define P2P_CONCURRENT_GO_NEGO_TIMEOUT 3000 // 3 seconds timeout for sending the negotiation request under concurrent mode +#define P2P_TX_PRESCAN_TIMEOUT 100 // 100ms +#define P2P_INVITE_TIMEOUT 5000 // 5 seconds timeout for sending the invitation request +#define P2P_CONCURRENT_INVITE_TIMEOUT 3000 // 3 seconds timeout for sending the invitation request under concurrent mode +#define P2P_RESET_SCAN_CH 25000 // 25 seconds timeout to reset the scan channel ( based on channel plan ) +#define P2P_MAX_INTENT 15 + +#define P2P_MAX_NOA_NUM 2 + +// WPS Configuration Method +#define WPS_CM_NONE 0x0000 +#define WPS_CM_LABEL 0x0004 +#define WPS_CM_DISPLYA 0x0008 +#define WPS_CM_EXTERNAL_NFC_TOKEN 0x0010 +#define WPS_CM_INTEGRATED_NFC_TOKEN 0x0020 +#define WPS_CM_NFC_INTERFACE 0x0040 +#define WPS_CM_PUSH_BUTTON 0x0080 +#define WPS_CM_KEYPAD 0x0100 +#define WPS_CM_SW_PUHS_BUTTON 0x0280 +#define WPS_CM_HW_PUHS_BUTTON 0x0480 +#define WPS_CM_SW_DISPLAY_PIN 0x2008 +#define WPS_CM_LCD_DISPLAY_PIN 0x4008 + +enum P2P_ROLE { + P2P_ROLE_DISABLE = 0, + P2P_ROLE_DEVICE = 1, + P2P_ROLE_CLIENT = 2, + P2P_ROLE_GO = 3 +}; + +enum P2P_STATE { + P2P_STATE_NONE = 0, // P2P disable + P2P_STATE_IDLE = 1, // P2P had enabled and do nothing + P2P_STATE_LISTEN = 2, // In pure listen state + P2P_STATE_SCAN = 3, // In scan phase + P2P_STATE_FIND_PHASE_LISTEN = 4, // In the listen state of find phase + P2P_STATE_FIND_PHASE_SEARCH = 5, // In the search state of find phase + P2P_STATE_TX_PROVISION_DIS_REQ = 6, // In P2P provisioning discovery + P2P_STATE_RX_PROVISION_DIS_RSP = 7, + P2P_STATE_RX_PROVISION_DIS_REQ = 8, + P2P_STATE_GONEGO_ING = 9, // Doing the group owner negoitation handshake + P2P_STATE_GONEGO_OK = 10, // finish the group negoitation handshake with success + P2P_STATE_GONEGO_FAIL = 11, // finish the group negoitation handshake with failure + P2P_STATE_RECV_INVITE_REQ_MATCH = 12, // receiving the P2P Inviation request and match with the profile. + P2P_STATE_PROVISIONING_ING = 13, // Doing the P2P WPS + P2P_STATE_PROVISIONING_DONE = 14, // Finish the P2P WPS + P2P_STATE_TX_INVITE_REQ = 15, // Transmit the P2P Invitation request + P2P_STATE_RX_INVITE_RESP_OK = 16, // Receiving the P2P Invitation response + P2P_STATE_RECV_INVITE_REQ_DISMATCH = 17, // receiving the P2P Inviation request and dismatch with the profile. + P2P_STATE_RECV_INVITE_REQ_GO = 18, // receiving the P2P Inviation request and this wifi is GO. + P2P_STATE_RECV_INVITE_REQ_JOIN = 19, // receiving the P2P Inviation request to join an existing P2P Group. + P2P_STATE_RX_INVITE_RESP_FAIL = 20, // recveing the P2P Inviation response with failure + P2P_STATE_RX_INFOR_NOREADY = 21, // receiving p2p negoitation response with information is not available + P2P_STATE_TX_INFOR_NOREADY = 22, // sending p2p negoitation response with information is not available +}; + +enum P2P_WPSINFO { + P2P_NO_WPSINFO = 0, + P2P_GOT_WPSINFO_PEER_DISPLAY_PIN = 1, + P2P_GOT_WPSINFO_SELF_DISPLAY_PIN = 2, + P2P_GOT_WPSINFO_PBC = 3, +}; + +#define P2P_PRIVATE_IOCTL_SET_LEN 64 + +enum P2P_PROTO_WK_ID +{ + P2P_FIND_PHASE_WK = 0, + P2P_RESTORE_STATE_WK = 1, + P2P_PRE_TX_PROVDISC_PROCESS_WK = 2, + P2P_PRE_TX_NEGOREQ_PROCESS_WK = 3, + P2P_PRE_TX_INVITEREQ_PROCESS_WK = 4, + P2P_AP_P2P_CH_SWITCH_PROCESS_WK =5, + P2P_RO_CH_WK = 6, +}; + +#ifdef CONFIG_P2P_PS +enum P2P_PS_STATE +{ + P2P_PS_DISABLE = 0, + P2P_PS_ENABLE = 1, + P2P_PS_SCAN = 2, + P2P_PS_SCAN_DONE = 3, + P2P_PS_ALLSTASLEEP = 4, // for P2P GO +}; + +enum P2P_PS_MODE +{ + P2P_PS_NONE = 0, + P2P_PS_CTWINDOW = 1, + P2P_PS_NOA = 2, + P2P_PS_MIX = 3, // CTWindow and NoA +}; +#endif // CONFIG_P2P_PS + +// =====================WFD Section===================== +// For Wi-Fi Display +#define WFD_ATTR_DEVICE_INFO 0x00 +#define WFD_ATTR_ASSOC_BSSID 0x01 +#define WFD_ATTR_COUPLED_SINK_INFO 0x06 +#define WFD_ATTR_LOCAL_IP_ADDR 0x08 +#define WFD_ATTR_SESSION_INFO 0x09 +#define WFD_ATTR_ALTER_MAC 0x0a + +// For WFD Device Information Attribute +#define WFD_DEVINFO_SOURCE 0x0000 +#define WFD_DEVINFO_PSINK 0x0001 +#define WFD_DEVINFO_SSINK 0x0002 +#define WFD_DEVINFO_DUAL 0x0003 + +#define WFD_DEVINFO_SESSION_AVAIL 0x0010 +#define WFD_DEVINFO_WSD 0x0040 +#define WFD_DEVINFO_PC_TDLS 0x0080 +#define WFD_DEVINFO_HDCP_SUPPORT 0x0100 + +#ifdef CONFIG_TX_MCAST2UNI +#define IP_MCAST_MAC(mac) ((mac[0]==0x01)&&(mac[1]==0x00)&&(mac[2]==0x5e)) +#define ICMPV6_MCAST_MAC(mac) ((mac[0]==0x33)&&(mac[1]==0x33)&&(mac[2]!=0xff)) +#endif // CONFIG_TX_MCAST2UNI + +#ifdef CONFIG_IOCTL_CFG80211 +/* Regulatroy Domain */ +struct regd_pair_mapping { + u16 reg_dmnenum; + u16 reg_5ghz_ctl; + u16 reg_2ghz_ctl; +}; + +struct rtw_regulatory { + char alpha2[2]; + u16 country_code; + u16 max_power_level; + u32 tp_scale; + u16 current_rd; + u16 current_rd_ext; + int16_t power_limit; + struct regd_pair_mapping *regpair; +}; +#endif + +#ifdef CONFIG_WAPI_SUPPORT +#ifndef IW_AUTH_WAPI_VERSION_1 +#define IW_AUTH_WAPI_VERSION_1 0x00000008 +#endif +#ifndef IW_AUTH_KEY_MGMT_WAPI_PSK +#define IW_AUTH_KEY_MGMT_WAPI_PSK 0x04 +#endif +#ifndef IW_AUTH_WAPI_ENABLED +#define IW_AUTH_WAPI_ENABLED 0x20 +#endif +#ifndef IW_ENCODE_ALG_SM4 +#define IW_ENCODE_ALG_SM4 0x20 +#endif +#endif + +#endif // _WIFI_H_ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/wlan_bssdef.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/wlan_bssdef.h new file mode 100644 index 000000000..bd5237a75 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/wlan_bssdef.h @@ -0,0 +1,748 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __WLAN_BSSDEF_H__ +#define __WLAN_BSSDEF_H__ + + +#define MAX_IE_SZ 768 + + +#ifdef PLATFORM_LINUX + +#define NDIS_802_11_LENGTH_SSID 32 +#define NDIS_802_11_LENGTH_RATES 8 +#define NDIS_802_11_LENGTH_RATES_EX 16 + +typedef unsigned char NDIS_802_11_MAC_ADDRESS[6]; +typedef long NDIS_802_11_RSSI; // in dBm +typedef unsigned char NDIS_802_11_RATES[NDIS_802_11_LENGTH_RATES]; // Set of 8 data rates +typedef unsigned char NDIS_802_11_RATES_EX[NDIS_802_11_LENGTH_RATES_EX]; // Set of 16 data rates + + +typedef ULONG NDIS_802_11_KEY_INDEX; +typedef unsigned long long NDIS_802_11_KEY_RSC; + + +typedef struct _NDIS_802_11_SSID +{ + ULONG SsidLength; + UCHAR Ssid[32]; +} NDIS_802_11_SSID, *PNDIS_802_11_SSID; + +typedef enum _NDIS_802_11_NETWORK_TYPE +{ + Ndis802_11FH, + Ndis802_11DS, + Ndis802_11OFDM5, + Ndis802_11OFDM24, + Ndis802_11NetworkTypeMax // not a real type, defined as an upper bound +} NDIS_802_11_NETWORK_TYPE, *PNDIS_802_11_NETWORK_TYPE; + +typedef struct _NDIS_802_11_CONFIGURATION_FH +{ + ULONG Length; // Length of structure + ULONG HopPattern; // As defined by 802.11, MSB set + ULONG HopSet; // to one if non-802.11 + ULONG DwellTime; // units are Kusec +} NDIS_802_11_CONFIGURATION_FH, *PNDIS_802_11_CONFIGURATION_FH; + + +/* + FW will only save the channel number in DSConfig. + ODI Handler will convert the channel number to freq. number. +*/ +typedef struct _NDIS_802_11_CONFIGURATION +{ + ULONG Length; // Length of structure + ULONG BeaconPeriod; // units are Kusec + ULONG ATIMWindow; // units are Kusec + ULONG DSConfig; /* channel number */ + NDIS_802_11_CONFIGURATION_FH FHConfig; +} NDIS_802_11_CONFIGURATION, *PNDIS_802_11_CONFIGURATION; + + + +typedef enum _NDIS_802_11_NETWORK_INFRASTRUCTURE +{ + Ndis802_11IBSS, + Ndis802_11Infrastructure, + Ndis802_11AutoUnknown, + Ndis802_11InfrastructureMax, // Not a real value, defined as upper bound + Ndis802_11APMode, + Ndis802_11Monitor, +} NDIS_802_11_NETWORK_INFRASTRUCTURE, *PNDIS_802_11_NETWORK_INFRASTRUCTURE; + + + + + +typedef struct _NDIS_802_11_FIXED_IEs +{ + UCHAR Timestamp[8]; + USHORT BeaconInterval; + USHORT Capabilities; +} NDIS_802_11_FIXED_IEs, *PNDIS_802_11_FIXED_IEs; + + + +typedef struct _NDIS_802_11_VARIABLE_IEs +{ + UCHAR ElementID; + UCHAR Length; + UCHAR data[1]; +} NDIS_802_11_VARIABLE_IEs, *PNDIS_802_11_VARIABLE_IEs; + + + +/* + + + +Length is the 4 bytes multiples of the sume of + sizeof (NDIS_802_11_MAC_ADDRESS) + 2 + sizeof (NDIS_802_11_SSID) + sizeof (ULONG) ++ sizeof (NDIS_802_11_RSSI) + sizeof (NDIS_802_11_NETWORK_TYPE) + sizeof (NDIS_802_11_CONFIGURATION) ++ sizeof (NDIS_802_11_RATES_EX) + IELength + +Except the IELength, all other fields are fixed length. Therefore, we can define a marco to present the +partial sum. + +*/ +#if 0 +typedef struct _NDIS_WLAN_BSSID_EX +{ + ULONG Length; + NDIS_802_11_MAC_ADDRESS MacAddress; + UCHAR Reserved[2];//[0]: IS beacon frame, [1]:optimum_antenna=>For antenna diversity; + NDIS_802_11_SSID Ssid; + ULONG Privacy; + NDIS_802_11_RSSI Rssi; + NDIS_802_11_NETWORK_TYPE NetworkTypeInUse; + NDIS_802_11_CONFIGURATION Configuration; + NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode; + NDIS_802_11_RATES_EX SupportedRates; + ULONG IELength; + UCHAR IEs[MAX_IE_SZ]; //(timestamp, beacon interval, and capability information) +} NDIS_WLAN_BSSID_EX, *PNDIS_WLAN_BSSID_EX; + + +typedef struct _NDIS_802_11_BSSID_LIST_EX +{ + ULONG NumberOfItems; + NDIS_WLAN_BSSID_EX Bssid[1]; +} NDIS_802_11_BSSID_LIST_EX, *PNDIS_802_11_BSSID_LIST_EX; +#endif + +typedef enum _NDIS_802_11_AUTHENTICATION_MODE +{ + Ndis802_11AuthModeOpen, + Ndis802_11AuthModeShared, + Ndis802_11AuthModeAutoSwitch, + Ndis802_11AuthModeWPA, + Ndis802_11AuthModeWPAPSK, + Ndis802_11AuthModeWPANone, + Ndis802_11AuthModeWAPI, + Ndis802_11AuthModeMax // Not a real mode, defined as upper bound +} NDIS_802_11_AUTHENTICATION_MODE, *PNDIS_802_11_AUTHENTICATION_MODE; + +typedef enum _NDIS_802_11_WEP_STATUS +{ + Ndis802_11WEPEnabled, + Ndis802_11Encryption1Enabled = Ndis802_11WEPEnabled, + Ndis802_11WEPDisabled, + Ndis802_11EncryptionDisabled = Ndis802_11WEPDisabled, + Ndis802_11WEPKeyAbsent, + Ndis802_11Encryption1KeyAbsent = Ndis802_11WEPKeyAbsent, + Ndis802_11WEPNotSupported, + Ndis802_11EncryptionNotSupported = Ndis802_11WEPNotSupported, + Ndis802_11Encryption2Enabled, + Ndis802_11Encryption2KeyAbsent, + Ndis802_11Encryption3Enabled, + Ndis802_11Encryption3KeyAbsent, + Ndis802_11_EncrypteionWAPI +} NDIS_802_11_WEP_STATUS, *PNDIS_802_11_WEP_STATUS, + NDIS_802_11_ENCRYPTION_STATUS, *PNDIS_802_11_ENCRYPTION_STATUS; + + +#define NDIS_802_11_AI_REQFI_CAPABILITIES 1 +#define NDIS_802_11_AI_REQFI_LISTENINTERVAL 2 +#define NDIS_802_11_AI_REQFI_CURRENTAPADDRESS 4 + +#define NDIS_802_11_AI_RESFI_CAPABILITIES 1 +#define NDIS_802_11_AI_RESFI_STATUSCODE 2 +#define NDIS_802_11_AI_RESFI_ASSOCIATIONID 4 + +typedef struct _NDIS_802_11_AI_REQFI +{ + USHORT Capabilities; + USHORT ListenInterval; + NDIS_802_11_MAC_ADDRESS CurrentAPAddress; +} NDIS_802_11_AI_REQFI, *PNDIS_802_11_AI_REQFI; + +typedef struct _NDIS_802_11_AI_RESFI +{ + USHORT Capabilities; + USHORT StatusCode; + USHORT AssociationId; +} NDIS_802_11_AI_RESFI, *PNDIS_802_11_AI_RESFI; + +typedef struct _NDIS_802_11_ASSOCIATION_INFORMATION +{ + ULONG Length; + USHORT AvailableRequestFixedIEs; + NDIS_802_11_AI_REQFI RequestFixedIEs; + ULONG RequestIELength; + ULONG OffsetRequestIEs; + USHORT AvailableResponseFixedIEs; + NDIS_802_11_AI_RESFI ResponseFixedIEs; + ULONG ResponseIELength; + ULONG OffsetResponseIEs; +} NDIS_802_11_ASSOCIATION_INFORMATION, *PNDIS_802_11_ASSOCIATION_INFORMATION; + +typedef enum _NDIS_802_11_RELOAD_DEFAULTS +{ + Ndis802_11ReloadWEPKeys +} NDIS_802_11_RELOAD_DEFAULTS, *PNDIS_802_11_RELOAD_DEFAULTS; + + +// Key mapping keys require a BSSID +typedef struct _NDIS_802_11_KEY +{ + ULONG Length; // Length of this structure + ULONG KeyIndex; + ULONG KeyLength; // length of key in bytes + NDIS_802_11_MAC_ADDRESS BSSID; + NDIS_802_11_KEY_RSC KeyRSC; + UCHAR KeyMaterial[32]; // variable length depending on above field +} NDIS_802_11_KEY, *PNDIS_802_11_KEY; + +typedef struct _NDIS_802_11_REMOVE_KEY +{ + ULONG Length; // Length of this structure + ULONG KeyIndex; + NDIS_802_11_MAC_ADDRESS BSSID; +} NDIS_802_11_REMOVE_KEY, *PNDIS_802_11_REMOVE_KEY; + +typedef struct _NDIS_802_11_WEP +{ + ULONG Length; // Length of this structure + ULONG KeyIndex; // 0 is the per-client key, 1-N are the global keys + ULONG KeyLength; // length of key in bytes + UCHAR KeyMaterial[16];// variable length depending on above field +} NDIS_802_11_WEP, *PNDIS_802_11_WEP; + +typedef struct _NDIS_802_11_AUTHENTICATION_REQUEST +{ + ULONG Length; // Length of structure + NDIS_802_11_MAC_ADDRESS Bssid; + ULONG Flags; +} NDIS_802_11_AUTHENTICATION_REQUEST, *PNDIS_802_11_AUTHENTICATION_REQUEST; + +typedef enum _NDIS_802_11_STATUS_TYPE +{ + Ndis802_11StatusType_Authentication, + Ndis802_11StatusType_MediaStreamMode, + Ndis802_11StatusType_PMKID_CandidateList, + Ndis802_11StatusTypeMax // not a real type, defined as an upper bound +} NDIS_802_11_STATUS_TYPE, *PNDIS_802_11_STATUS_TYPE; + +typedef struct _NDIS_802_11_STATUS_INDICATION +{ + NDIS_802_11_STATUS_TYPE StatusType; +} NDIS_802_11_STATUS_INDICATION, *PNDIS_802_11_STATUS_INDICATION; + +// mask for authentication/integrity fields +#define NDIS_802_11_AUTH_REQUEST_AUTH_FIELDS 0x0f +#define NDIS_802_11_AUTH_REQUEST_REAUTH 0x01 +#define NDIS_802_11_AUTH_REQUEST_KEYUPDATE 0x02 +#define NDIS_802_11_AUTH_REQUEST_PAIRWISE_ERROR 0x06 +#define NDIS_802_11_AUTH_REQUEST_GROUP_ERROR 0x0E + +// MIC check time, 60 seconds. +#define MIC_CHECK_TIME 60000000 + +typedef struct _NDIS_802_11_AUTHENTICATION_EVENT +{ + NDIS_802_11_STATUS_INDICATION Status; + NDIS_802_11_AUTHENTICATION_REQUEST Request[1]; +} NDIS_802_11_AUTHENTICATION_EVENT, *PNDIS_802_11_AUTHENTICATION_EVENT; + +typedef struct _NDIS_802_11_TEST +{ + ULONG Length; + ULONG Type; + union + { + NDIS_802_11_AUTHENTICATION_EVENT AuthenticationEvent; + NDIS_802_11_RSSI RssiTrigger; + }tt; +} NDIS_802_11_TEST, *PNDIS_802_11_TEST; + + +#endif //end of #ifdef PLATFORM_LINUX + +#ifdef PLATFORM_FREEBSD + +#define NDIS_802_11_LENGTH_SSID 32 +#define NDIS_802_11_LENGTH_RATES 8 +#define NDIS_802_11_LENGTH_RATES_EX 16 + +typedef unsigned char NDIS_802_11_MAC_ADDRESS[6]; +typedef long NDIS_802_11_RSSI; // in dBm +typedef unsigned char NDIS_802_11_RATES[NDIS_802_11_LENGTH_RATES]; // Set of 8 data rates +typedef unsigned char NDIS_802_11_RATES_EX[NDIS_802_11_LENGTH_RATES_EX]; // Set of 16 data rates + + +typedef ULONG NDIS_802_11_KEY_INDEX; +typedef unsigned long long NDIS_802_11_KEY_RSC; + + +typedef struct _NDIS_802_11_SSID +{ + ULONG SsidLength; + UCHAR Ssid[32]; +} NDIS_802_11_SSID, *PNDIS_802_11_SSID; + +typedef enum _NDIS_802_11_NETWORK_TYPE +{ + Ndis802_11FH, + Ndis802_11DS, + Ndis802_11OFDM5, + Ndis802_11OFDM24, + Ndis802_11NetworkTypeMax // not a real type, defined as an upper bound +} NDIS_802_11_NETWORK_TYPE, *PNDIS_802_11_NETWORK_TYPE; + +typedef struct _NDIS_802_11_CONFIGURATION_FH +{ + ULONG Length; // Length of structure + ULONG HopPattern; // As defined by 802.11, MSB set + ULONG HopSet; // to one if non-802.11 + ULONG DwellTime; // units are Kusec +} NDIS_802_11_CONFIGURATION_FH, *PNDIS_802_11_CONFIGURATION_FH; + + +/* + FW will only save the channel number in DSConfig. + ODI Handler will convert the channel number to freq. number. +*/ +typedef struct _NDIS_802_11_CONFIGURATION +{ + ULONG Length; // Length of structure + ULONG BeaconPeriod; // units are Kusec + ULONG ATIMWindow; // units are Kusec + ULONG DSConfig; /* channel number */ + NDIS_802_11_CONFIGURATION_FH FHConfig; +} NDIS_802_11_CONFIGURATION, *PNDIS_802_11_CONFIGURATION; + + + +typedef enum _NDIS_802_11_NETWORK_INFRASTRUCTURE +{ + Ndis802_11IBSS, + Ndis802_11Infrastructure, + Ndis802_11AutoUnknown, + Ndis802_11InfrastructureMax, // Not a real value, defined as upper bound + Ndis802_11APMode +} NDIS_802_11_NETWORK_INFRASTRUCTURE, *PNDIS_802_11_NETWORK_INFRASTRUCTURE; + + + + + +typedef struct _NDIS_802_11_FIXED_IEs +{ + UCHAR Timestamp[8]; + USHORT BeaconInterval; + USHORT Capabilities; +} NDIS_802_11_FIXED_IEs, *PNDIS_802_11_FIXED_IEs; + + + +typedef struct _NDIS_802_11_VARIABLE_IEs +{ + UCHAR ElementID; + UCHAR Length; + UCHAR data[1]; +} NDIS_802_11_VARIABLE_IEs, *PNDIS_802_11_VARIABLE_IEs; + + + +/* + + + +Length is the 4 bytes multiples of the sume of + sizeof (NDIS_802_11_MAC_ADDRESS) + 2 + sizeof (NDIS_802_11_SSID) + sizeof (ULONG) ++ sizeof (NDIS_802_11_RSSI) + sizeof (NDIS_802_11_NETWORK_TYPE) + sizeof (NDIS_802_11_CONFIGURATION) ++ sizeof (NDIS_802_11_RATES_EX) + IELength + +Except the IELength, all other fields are fixed length. Therefore, we can define a marco to present the +partial sum. + +*/ +#if 0 +typedef struct _NDIS_WLAN_BSSID_EX +{ + ULONG Length; + NDIS_802_11_MAC_ADDRESS MacAddress; + UCHAR Reserved[2];//[0]: IS beacon frame, [1]:optimum_antenna=>For antenna diversity; + NDIS_802_11_SSID Ssid; + ULONG Privacy; + NDIS_802_11_RSSI Rssi; + NDIS_802_11_NETWORK_TYPE NetworkTypeInUse; + NDIS_802_11_CONFIGURATION Configuration; + NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode; + NDIS_802_11_RATES_EX SupportedRates; + ULONG IELength; + UCHAR IEs[MAX_IE_SZ]; //(timestamp, beacon interval, and capability information) +} NDIS_WLAN_BSSID_EX, *PNDIS_WLAN_BSSID_EX; + + +typedef struct _NDIS_802_11_BSSID_LIST_EX +{ + ULONG NumberOfItems; + NDIS_WLAN_BSSID_EX Bssid[1]; +} NDIS_802_11_BSSID_LIST_EX, *PNDIS_802_11_BSSID_LIST_EX; +#endif + +typedef enum _NDIS_802_11_AUTHENTICATION_MODE +{ + Ndis802_11AuthModeOpen, + Ndis802_11AuthModeShared, + Ndis802_11AuthModeAutoSwitch, + Ndis802_11AuthModeWPA, + Ndis802_11AuthModeWPAPSK, + Ndis802_11AuthModeWPANone, + Ndis802_11AuthModeMax // Not a real mode, defined as upper bound +} NDIS_802_11_AUTHENTICATION_MODE, *PNDIS_802_11_AUTHENTICATION_MODE; + +typedef enum _NDIS_802_11_WEP_STATUS +{ + Ndis802_11WEPEnabled, + Ndis802_11Encryption1Enabled = Ndis802_11WEPEnabled, + Ndis802_11WEPDisabled, + Ndis802_11EncryptionDisabled = Ndis802_11WEPDisabled, + Ndis802_11WEPKeyAbsent, + Ndis802_11Encryption1KeyAbsent = Ndis802_11WEPKeyAbsent, + Ndis802_11WEPNotSupported, + Ndis802_11EncryptionNotSupported = Ndis802_11WEPNotSupported, + Ndis802_11Encryption2Enabled, + Ndis802_11Encryption2KeyAbsent, + Ndis802_11Encryption3Enabled, + Ndis802_11Encryption3KeyAbsent +} NDIS_802_11_WEP_STATUS, *PNDIS_802_11_WEP_STATUS, + NDIS_802_11_ENCRYPTION_STATUS, *PNDIS_802_11_ENCRYPTION_STATUS; + + +#define NDIS_802_11_AI_REQFI_CAPABILITIES 1 +#define NDIS_802_11_AI_REQFI_LISTENINTERVAL 2 +#define NDIS_802_11_AI_REQFI_CURRENTAPADDRESS 4 + +#define NDIS_802_11_AI_RESFI_CAPABILITIES 1 +#define NDIS_802_11_AI_RESFI_STATUSCODE 2 +#define NDIS_802_11_AI_RESFI_ASSOCIATIONID 4 + +typedef struct _NDIS_802_11_AI_REQFI +{ + USHORT Capabilities; + USHORT ListenInterval; + NDIS_802_11_MAC_ADDRESS CurrentAPAddress; +} NDIS_802_11_AI_REQFI, *PNDIS_802_11_AI_REQFI; + +typedef struct _NDIS_802_11_AI_RESFI +{ + USHORT Capabilities; + USHORT StatusCode; + USHORT AssociationId; +} NDIS_802_11_AI_RESFI, *PNDIS_802_11_AI_RESFI; + +typedef struct _NDIS_802_11_ASSOCIATION_INFORMATION +{ + ULONG Length; + USHORT AvailableRequestFixedIEs; + NDIS_802_11_AI_REQFI RequestFixedIEs; + ULONG RequestIELength; + ULONG OffsetRequestIEs; + USHORT AvailableResponseFixedIEs; + NDIS_802_11_AI_RESFI ResponseFixedIEs; + ULONG ResponseIELength; + ULONG OffsetResponseIEs; +} NDIS_802_11_ASSOCIATION_INFORMATION, *PNDIS_802_11_ASSOCIATION_INFORMATION; + +typedef enum _NDIS_802_11_RELOAD_DEFAULTS +{ + Ndis802_11ReloadWEPKeys +} NDIS_802_11_RELOAD_DEFAULTS, *PNDIS_802_11_RELOAD_DEFAULTS; + + +// Key mapping keys require a BSSID +typedef struct _NDIS_802_11_KEY +{ + ULONG Length; // Length of this structure + ULONG KeyIndex; + ULONG KeyLength; // length of key in bytes + NDIS_802_11_MAC_ADDRESS BSSID; + NDIS_802_11_KEY_RSC KeyRSC; + UCHAR KeyMaterial[32]; // variable length depending on above field +} NDIS_802_11_KEY, *PNDIS_802_11_KEY; + +typedef struct _NDIS_802_11_REMOVE_KEY +{ + ULONG Length; // Length of this structure + ULONG KeyIndex; + NDIS_802_11_MAC_ADDRESS BSSID; +} NDIS_802_11_REMOVE_KEY, *PNDIS_802_11_REMOVE_KEY; + +typedef struct _NDIS_802_11_WEP +{ + ULONG Length; // Length of this structure + ULONG KeyIndex; // 0 is the per-client key, 1-N are the global keys + ULONG KeyLength; // length of key in bytes + UCHAR KeyMaterial[16];// variable length depending on above field +} NDIS_802_11_WEP, *PNDIS_802_11_WEP; + +typedef struct _NDIS_802_11_AUTHENTICATION_REQUEST +{ + ULONG Length; // Length of structure + NDIS_802_11_MAC_ADDRESS Bssid; + ULONG Flags; +} NDIS_802_11_AUTHENTICATION_REQUEST, *PNDIS_802_11_AUTHENTICATION_REQUEST; + +typedef enum _NDIS_802_11_STATUS_TYPE +{ + Ndis802_11StatusType_Authentication, + Ndis802_11StatusType_MediaStreamMode, + Ndis802_11StatusType_PMKID_CandidateList, + Ndis802_11StatusTypeMax // not a real type, defined as an upper bound +} NDIS_802_11_STATUS_TYPE, *PNDIS_802_11_STATUS_TYPE; + +typedef struct _NDIS_802_11_STATUS_INDICATION +{ + NDIS_802_11_STATUS_TYPE StatusType; +} NDIS_802_11_STATUS_INDICATION, *PNDIS_802_11_STATUS_INDICATION; + +// mask for authentication/integrity fields +#define NDIS_802_11_AUTH_REQUEST_AUTH_FIELDS 0x0f +#define NDIS_802_11_AUTH_REQUEST_REAUTH 0x01 +#define NDIS_802_11_AUTH_REQUEST_KEYUPDATE 0x02 +#define NDIS_802_11_AUTH_REQUEST_PAIRWISE_ERROR 0x06 +#define NDIS_802_11_AUTH_REQUEST_GROUP_ERROR 0x0E + +// MIC check time, 60 seconds. +#define MIC_CHECK_TIME 60000000 + +typedef struct _NDIS_802_11_AUTHENTICATION_EVENT +{ + NDIS_802_11_STATUS_INDICATION Status; + NDIS_802_11_AUTHENTICATION_REQUEST Request[1]; +} NDIS_802_11_AUTHENTICATION_EVENT, *PNDIS_802_11_AUTHENTICATION_EVENT; + +typedef struct _NDIS_802_11_TEST +{ + ULONG Length; + ULONG Type; + union + { + NDIS_802_11_AUTHENTICATION_EVENT AuthenticationEvent; + NDIS_802_11_RSSI RssiTrigger; + }tt; +} NDIS_802_11_TEST, *PNDIS_802_11_TEST; + + +#endif //PLATFORM_FREEBSD +#ifndef Ndis802_11APMode +#define Ndis802_11APMode (Ndis802_11InfrastructureMax+1) +#endif + +typedef struct _WLAN_PHY_INFO +{ + u8 SignalStrength;//(in percentage) + u8 SignalQuality;//(in percentage) + u8 Optimum_antenna; //for Antenna diversity + u8 Reserved_0; +}WLAN_PHY_INFO,*PWLAN_PHY_INFO; + +typedef struct _WLAN_BCN_INFO +{ + /* these infor get from rtw_get_encrypt_info when + * * translate scan to UI */ + u8 encryp_protocol;//ENCRYP_PROTOCOL_E: OPEN/WEP/WPA/WPA2/WAPI + int group_cipher; //WPA/WPA2 group cipher + int pairwise_cipher;////WPA/WPA2/WEP pairwise cipher + int is_8021x; + + /* bwmode 20/40 and ch_offset UP/LOW */ + unsigned short ht_cap_info; + unsigned char ht_info_infos_0; +}WLAN_BCN_INFO,*PWLAN_BCN_INFO; + +/* temporally add #pragma pack for structure alignment issue of +* WLAN_BSSID_EX and get_WLAN_BSSID_EX_sz() +*/ +#ifdef PLATFORM_WINDOWS +#pragma pack(push) +#pragma pack(1) +#endif +typedef struct _WLAN_BSSID_EX +{ + ULONG Length; + NDIS_802_11_MAC_ADDRESS MacAddress; + UCHAR Reserved[2];//[0]: IS beacon frame + NDIS_802_11_SSID Ssid; + ULONG Privacy; + NDIS_802_11_RSSI Rssi;//(in dBM,raw data ,get from PHY) + NDIS_802_11_NETWORK_TYPE NetworkTypeInUse; + NDIS_802_11_CONFIGURATION Configuration; + NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode; + NDIS_802_11_RATES_EX SupportedRates; + WLAN_PHY_INFO PhyInfo; + ULONG IELength; + UCHAR IEs[MAX_IE_SZ]; //(timestamp, beacon interval, and capability information) +} +#ifndef PLATFORM_WINDOWS +__attribute__((packed)) +#endif +WLAN_BSSID_EX, *PWLAN_BSSID_EX; +#ifdef PLATFORM_WINDOWS +#pragma pack(pop) +#endif + +#define BSS_EX_IES(bss_ex) ((bss_ex)->IEs) +#define BSS_EX_IES_LEN(bss_ex) ((bss_ex)->IELength) +#define BSS_EX_FIXED_IE_OFFSET(bss_ex) ((bss_ex)->Reserved[0] == 2 ? 0 : 12) +#define BSS_EX_TLV_IES(bss_ex) (BSS_EX_IES((bss_ex)) + BSS_EX_FIXED_IE_OFFSET((bss_ex))) +#define BSS_EX_TLV_IES_LEN(bss_ex) (BSS_EX_IES_LEN((bss_ex)) - BSS_EX_FIXED_IE_OFFSET((bss_ex))) + +__inline static uint get_WLAN_BSSID_EX_sz(WLAN_BSSID_EX *bss) +{ +#if 0 + uint t_len; + + t_len = sizeof (ULONG) + + sizeof (NDIS_802_11_MAC_ADDRESS) + + 2 + + sizeof (NDIS_802_11_SSID) + + sizeof (ULONG) + + sizeof (NDIS_802_11_RSSI) + + sizeof (NDIS_802_11_NETWORK_TYPE) + + sizeof (NDIS_802_11_CONFIGURATION) + + sizeof (NDIS_802_11_NETWORK_INFRASTRUCTURE) + + sizeof (NDIS_802_11_RATES_EX) + //all new member add here + + sizeof(WLAN_PHY_INFO) + //all new member add here + + sizeof (ULONG) + + bss->IELength; + return t_len; +#else + return (sizeof(WLAN_BSSID_EX) -MAX_IE_SZ + bss->IELength); +#endif +} + +struct wlan_network { + _list list; + int network_type; //refer to ieee80211.h for WIRELESS_11A/B/G + int fixed; // set to fixed when not to be removed as site-surveying + unsigned long last_scanned; //timestamp for the network + int aid; //will only be valid when a BSS is joinned. + int join_res; + WLAN_BSSID_EX network; //must be the last item + WLAN_BCN_INFO BcnInfo; +#ifdef PLATFORM_WINDOWS + unsigned char iebuf[MAX_IE_SZ]; +#endif + +}; + +enum VRTL_CARRIER_SENSE +{ + DISABLE_VCS, + ENABLE_VCS, + AUTO_VCS +}; + +enum VCS_TYPE +{ + NONE_VCS, + RTS_CTS, + CTS_TO_SELF +}; + + + + +#define PWR_CAM 0 +#define PWR_MINPS 1 +#define PWR_MAXPS 2 +#define PWR_UAPSD 3 +#define PWR_VOIP 4 + + +enum UAPSD_MAX_SP +{ + NO_LIMIT, + TWO_MSDU, + FOUR_MSDU, + SIX_MSDU +}; + + +//john +#define NUM_PRE_AUTH_KEY 16 +#define NUM_PMKID_CACHE NUM_PRE_AUTH_KEY + +/* +* WPA2 +*/ + +#ifndef PLATFORM_OS_CE +typedef struct _PMKID_CANDIDATE { + NDIS_802_11_MAC_ADDRESS BSSID; + ULONG Flags; +} PMKID_CANDIDATE, *PPMKID_CANDIDATE; + +typedef struct _NDIS_802_11_PMKID_CANDIDATE_LIST +{ + ULONG Version; // Version of the structure + ULONG NumCandidates; // No. of pmkid candidates + PMKID_CANDIDATE CandidateList[1]; +} NDIS_802_11_PMKID_CANDIDATE_LIST, *PNDIS_802_11_PMKID_CANDIDATE_LIST; + + +typedef struct _NDIS_802_11_AUTHENTICATION_ENCRYPTION +{ + NDIS_802_11_AUTHENTICATION_MODE AuthModeSupported; + NDIS_802_11_ENCRYPTION_STATUS EncryptStatusSupported; + +} NDIS_802_11_AUTHENTICATION_ENCRYPTION, *PNDIS_802_11_AUTHENTICATION_ENCRYPTION; + +typedef struct _NDIS_802_11_CAPABILITY +{ + ULONG Length; + ULONG Version; + ULONG NoOfPMKIDs; + ULONG NoOfAuthEncryptPairsSupported; + NDIS_802_11_AUTHENTICATION_ENCRYPTION AuthenticationEncryptionSupported[1]; + +} NDIS_802_11_CAPABILITY, *PNDIS_802_11_CAPABILITY; +#endif + + +#endif //#ifndef WLAN_BSSDEF_H_ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/include/xmit_osdep.h b/src/little/linux/drivers/net/wireless/rtl8188fu/include/xmit_osdep.h new file mode 100644 index 000000000..d489ebfcf --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/include/xmit_osdep.h @@ -0,0 +1,100 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __XMIT_OSDEP_H_ +#define __XMIT_OSDEP_H_ + + +struct pkt_file { + _pkt *pkt; + SIZE_T pkt_len; //the remainder length of the open_file + _buffer *cur_buffer; + u8 *buf_start; + u8 *cur_addr; + SIZE_T buf_len; +}; + +#ifdef PLATFORM_WINDOWS + +#ifdef PLATFORM_OS_XP +#ifdef CONFIG_USB_HCI +#include +#include +#include +#endif +#endif + +#ifdef CONFIG_GSPI_HCI +#define NR_XMITFRAME 64 +#else +#define NR_XMITFRAME 128 +#endif + +#define ETH_ALEN 6 + +extern NDIS_STATUS rtw_xmit_entry( +IN _nic_hdl cnxt, +IN NDIS_PACKET *pkt, +IN UINT flags +); + +#endif + +#ifdef PLATFORM_FREEBSD +#define NR_XMITFRAME 256 +extern int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev); +extern void rtw_xmit_entry_wrap (struct ifnet * pifp); +#endif //PLATFORM_FREEBSD + +#ifdef PLATFORM_LINUX + +#define NR_XMITFRAME 256 + +struct xmit_priv; +struct pkt_attrib; +struct sta_xmit_priv; +struct xmit_frame; +struct xmit_buf; + +extern int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev); +extern int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev); + +#endif + +void rtw_os_xmit_schedule(_adapter *padapter); + +int rtw_os_xmit_resource_alloc(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 alloc_sz, u8 flag); +void rtw_os_xmit_resource_free(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 free_sz, u8 flag); + +extern void rtw_set_tx_chksum_offload(_pkt *pkt, struct pkt_attrib *pattrib); + +extern uint rtw_remainder_len(struct pkt_file *pfile); +extern void _rtw_open_pktfile(_pkt *pkt, struct pkt_file *pfile); +extern uint _rtw_pktfile_read (struct pkt_file *pfile, u8 *rmem, uint rlen); +extern sint rtw_endofpktfile (struct pkt_file *pfile); + +extern void rtw_os_pkt_complete(_adapter *padapter, _pkt *pkt); +extern void rtw_os_xmit_complete(_adapter *padapter, struct xmit_frame *pxframe); + +void rtw_os_wake_queue_at_free_stainfo(_adapter *padapter, int *qcnt_freed); + +void dump_os_queue(void *sel, _adapter *padapter); + +#endif //__XMIT_OSDEP_H_ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/custom_gpio_linux.c b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/custom_gpio_linux.c new file mode 100644 index 000000000..418d7932e --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/custom_gpio_linux.c @@ -0,0 +1,356 @@ +/****************************************************************************** + * Customer code to add GPIO control during WLAN start/stop + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#include "drv_types.h" + +#ifdef CONFIG_PLATFORM_SPRD + +//gspi func & GPIO define +#include //0915 +#include + +#if !(defined ANDROID_2X) + +#ifdef CONFIG_RTL8188E +#include +#include +#endif // CONFIG_RTL8188E + +#ifndef GPIO_WIFI_POWER +#define GPIO_WIFI_POWER -1 +#endif // !GPIO_WIFI_POWER + +#ifndef GPIO_WIFI_RESET +#define GPIO_WIFI_RESET -1 +#endif // !GPIO_WIFI_RESET + +#ifndef GPIO_WIFI_PWDN +#define GPIO_WIFI_PWDN -1 +#endif // !GPIO_WIFI_RESET +#ifdef CONFIG_GSPI_HCI +extern unsigned int oob_irq; +#endif // CONFIG_GSPI_HCI + +#ifdef CONFIG_SDIO_HCI +extern int rtw_mp_mode; +#else // !CONFIG_SDIO_HCI +#endif // !CONFIG_SDIO_HCI + +int rtw_wifi_gpio_init(void) +{ +#ifdef CONFIG_GSPI_HCI + if (GPIO_WIFI_IRQ > 0) { + gpio_request(GPIO_WIFI_IRQ, "oob_irq"); + gpio_direction_input(GPIO_WIFI_IRQ); + + oob_irq = gpio_to_irq(GPIO_WIFI_IRQ); + + DBG_8192C("%s oob_irq:%d\n", __func__, oob_irq); + } +#endif + if (GPIO_WIFI_RESET > 0) + gpio_request(GPIO_WIFI_RESET , "wifi_rst"); + if (GPIO_WIFI_POWER > 0) + gpio_request(GPIO_WIFI_POWER, "wifi_power"); + +#ifdef CONFIG_SDIO_HCI +#if (defined(CONFIG_RTL8723B)) && (MP_DRIVER == 1) + if(rtw_mp_mode==1){ + DBG_871X("%s GPIO_BT_RESET pin special for mp_test\n", __func__); + if (GPIO_BT_RESET > 0) + gpio_request(GPIO_BT_RESET , "bt_rst"); + } +#endif +#endif + return 0; +} + +int rtw_wifi_gpio_deinit(void) +{ +#ifdef CONFIG_GSPI_HCI + if (GPIO_WIFI_IRQ > 0) + gpio_free(GPIO_WIFI_IRQ); +#endif + if (GPIO_WIFI_RESET > 0) + gpio_free(GPIO_WIFI_RESET ); + if (GPIO_WIFI_POWER > 0) + gpio_free(GPIO_WIFI_POWER); + +#ifdef CONFIG_SDIO_HCI +#if ( defined(CONFIG_RTL8723B)) && (MP_DRIVER == 1) + if(rtw_mp_mode==1){ + DBG_871X("%s GPIO_BT_RESET pin special for mp_test\n", __func__); + if (GPIO_BT_RESET > 0) + gpio_free(GPIO_BT_RESET); + } +#endif +#endif + return 0; +} + +/* Customer function to control hw specific wlan gpios */ +void rtw_wifi_gpio_wlan_ctrl(int onoff) +{ + switch (onoff) + { + case WLAN_PWDN_OFF: + DBG_8192C("%s: call customer specific GPIO(%d) to set wifi power down pin to 0\n", + __FUNCTION__, GPIO_WIFI_RESET); + +#ifndef CONFIG_DONT_BUS_SCAN + if (GPIO_WIFI_RESET > 0) + gpio_direction_output(GPIO_WIFI_RESET , 0); +#endif + break; + + case WLAN_PWDN_ON: + DBG_8192C("%s: callc customer specific GPIO(%d) to set wifi power down pin to 1\n", + __FUNCTION__, GPIO_WIFI_RESET); + + if (GPIO_WIFI_RESET > 0) + gpio_direction_output(GPIO_WIFI_RESET , 1); + break; + + case WLAN_POWER_OFF: + break; + + case WLAN_POWER_ON: + break; +#ifdef CONFIG_SDIO_HCI +#if ( defined(CONFIG_RTL8723B)) && (MP_DRIVER == 1) + case WLAN_BT_PWDN_OFF: + if(rtw_mp_mode==1) + { + DBG_871X("%s: call customer specific GPIO to set wifi power down pin to 0\n", + __FUNCTION__); + if (GPIO_BT_RESET > 0) + gpio_direction_output(GPIO_BT_RESET , 0); + } + break; + + case WLAN_BT_PWDN_ON: + if(rtw_mp_mode==1) + { + DBG_871X("%s: callc customer specific GPIO to set wifi power down pin to 1 %x\n", + __FUNCTION__, GPIO_BT_RESET); + + if (GPIO_BT_RESET > 0) + gpio_direction_output(GPIO_BT_RESET , 1); + } + break; +#endif +#endif + } +} + +#else //ANDROID_2X + +#include + +#ifdef CONFIG_RTL8188E +extern int sprd_3rdparty_gpio_wifi_power; +#endif +extern int sprd_3rdparty_gpio_wifi_pwd; +#if defined(CONFIG_RTL8723B) +extern int sprd_3rdparty_gpio_bt_reset; +#endif + +int rtw_wifi_gpio_init(void) +{ +#if defined(CONFIG_RTL8723B) + if (sprd_3rdparty_gpio_bt_reset > 0) + gpio_direction_output(sprd_3rdparty_gpio_bt_reset, 1); +#endif + + return 0; +} + +int rtw_wifi_gpio_deinit(void) +{ + return 0; +} + +/* Customer function to control hw specific wlan gpios */ +void rtw_wifi_gpio_wlan_ctrl(int onoff) +{ + switch (onoff) + { + case WLAN_PWDN_OFF: + DBG_8192C("%s: call customer specific GPIO to set wifi power down pin to 0\n", + __FUNCTION__); + if (sprd_3rdparty_gpio_wifi_pwd > 0) + { + gpio_set_value(sprd_3rdparty_gpio_wifi_pwd, 0); + } + + if (sprd_3rdparty_gpio_wifi_pwd == 60) { + DBG_8192C("%s: turn off VSIM2 2.8V\n", __func__); + LDO_TurnOffLDO(LDO_LDO_SIM2); + } + break; + + case WLAN_PWDN_ON: + DBG_8192C("%s: callc customer specific GPIO to set wifi power down pin to 1\n", + __FUNCTION__); + if (sprd_3rdparty_gpio_wifi_pwd == 60) { + DBG_8192C("%s: turn on VSIM2 2.8V\n", __func__); + LDO_SetVoltLevel(LDO_LDO_SIM2, LDO_VOLT_LEVEL0); + LDO_TurnOnLDO(LDO_LDO_SIM2); + } + if (sprd_3rdparty_gpio_wifi_pwd > 0) + { + gpio_set_value(sprd_3rdparty_gpio_wifi_pwd, 1); + } + break; + + case WLAN_POWER_OFF: +#ifdef CONFIG_RTL8188E +#ifdef CONFIG_WIF1_LDO + DBG_8192C("%s: turn off VDD-WIFI0 1.2V\n", __FUNCTION__); + LDO_TurnOffLDO(LDO_LDO_WIF1); +#endif //CONFIG_WIF1_LDO + + DBG_8192C("%s: turn off VDD-WIFI0 3.3V\n", __FUNCTION__); + LDO_TurnOffLDO(LDO_LDO_WIF0); + + DBG_8192C("%s: call customer specific GPIO(%d) to turn off wifi power\n", + __FUNCTION__, sprd_3rdparty_gpio_wifi_power); + if (sprd_3rdparty_gpio_wifi_power != 65535) + gpio_set_value(sprd_3rdparty_gpio_wifi_power, 0); +#endif + break; + + case WLAN_POWER_ON: +#ifdef CONFIG_RTL8188E + DBG_8192C("%s: call customer specific GPIO(%d) to turn on wifi power\n", + __FUNCTION__, sprd_3rdparty_gpio_wifi_power); + if (sprd_3rdparty_gpio_wifi_power != 65535) + gpio_set_value(sprd_3rdparty_gpio_wifi_power, 1); + + DBG_8192C("%s: turn on VDD-WIFI0 3.3V\n", __FUNCTION__); + LDO_TurnOnLDO(LDO_LDO_WIF0); + LDO_SetVoltLevel(LDO_LDO_WIF0,LDO_VOLT_LEVEL1); + +#ifdef CONFIG_WIF1_LDO + DBG_8192C("%s: turn on VDD-WIFI1 1.2V\n", __func__); + LDO_TurnOnLDO(LDO_LDO_WIF1); + LDO_SetVoltLevel(LDO_LDO_WIF1,LDO_VOLT_LEVEL3); +#endif //CONFIG_WIF1_LDO +#endif + break; + + case WLAN_BT_PWDN_OFF: + DBG_8192C("%s: call customer specific GPIO to set bt power down pin to 0\n", + __FUNCTION__); +#if defined(CONFIG_RTL8723B) + if (sprd_3rdparty_gpio_bt_reset > 0) + gpio_set_value(sprd_3rdparty_gpio_bt_reset, 0); +#endif + break; + + case WLAN_BT_PWDN_ON: + DBG_8192C("%s: callc customer specific GPIO to set bt power down pin to 1\n", + __FUNCTION__); +#if defined(CONFIG_RTL8723B) + if (sprd_3rdparty_gpio_bt_reset > 0) + gpio_set_value(sprd_3rdparty_gpio_bt_reset, 1); +#endif + break; + } +} +#endif //ANDROID_2X + +#elif defined(CONFIG_PLATFORM_ARM_RK3066) +#include + +#define GPIO_WIFI_IRQ RK30_PIN2_PC2 +extern unsigned int oob_irq; +int rtw_wifi_gpio_init(void) +{ +#ifdef CONFIG_GSPI_HCI + if (GPIO_WIFI_IRQ > 0) { + rk30_mux_api_set(GPIO2C2_LCDC1DATA18_SMCBLSN1_HSADCDATA5_NAME, GPIO2C_GPIO2C2);//jacky_test + gpio_request(GPIO_WIFI_IRQ, "oob_irq"); + gpio_direction_input(GPIO_WIFI_IRQ); + + oob_irq = gpio_to_irq(GPIO_WIFI_IRQ); + + DBG_8192C("%s oob_irq:%d\n", __func__, oob_irq); + } +#endif + return 0; +} + + +int rtw_wifi_gpio_deinit(void) +{ +#ifdef CONFIG_GSPI_HCI + if (GPIO_WIFI_IRQ > 0) + gpio_free(GPIO_WIFI_IRQ); +#endif + return 0; +} + +void rtw_wifi_gpio_wlan_ctrl(int onoff) +{ +} + +#ifdef CONFIG_GPIO_API +//this is a demo for extending GPIO pin[7] as interrupt mode +struct net_device * rtl_net; +extern int rtw_register_gpio_interrupt(struct net_device *netdev, int gpio_num, void(*callback)(u8 level)); +extern int rtw_disable_gpio_interrupt(struct net_device *netdev, int gpio_num); +void gpio_int(u8 is_high) +{ + DBG_8192C("%s level=%d\n",__func__, is_high); +} +int register_net_gpio_init(void) +{ + rtl_net = dev_get_by_name(&init_net,"wlan0"); + if(!rtl_net) + { + DBG_871X_LEVEL(_drv_always_, "rtl_net init fail!\n"); + return -1; + } + return rtw_register_gpio_interrupt(rtl_net,7, gpio_int); +} +int unregister_net_gpio_init(void) +{ + rtl_net = dev_get_by_name(&init_net,"wlan0"); + if(!rtl_net) + { + DBG_871X_LEVEL(_drv_always_, "rtl_net init fail!\n"); + return -1; + } + return rtw_disable_gpio_interrupt(rtl_net,7); +} +#endif + +#else + +int rtw_wifi_gpio_init(void) +{ + return 0; +} + +void rtw_wifi_gpio_wlan_ctrl(int onoff) +{ +} +#endif //CONFIG_PLATFORM_SPRD diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/ioctl_cfg80211.c b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/ioctl_cfg80211.c new file mode 100644 index 000000000..ebc537693 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/ioctl_cfg80211.c @@ -0,0 +1,7013 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _IOCTL_CFG80211_C_ + +#include + +#ifdef CONFIG_IOCTL_CFG80211 + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0)) +#define ieee80211_band nl80211_band +#define IEEE80211_BAND_2GHZ NL80211_BAND_2GHZ +#define IEEE80211_BAND_5GHZ NL80211_BAND_5GHZ +#define IEEE80211_NUM_BANDS NUM_NL80211_BANDS +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 0, 0)) +#define STATION_INFO_SIGNAL BIT(NL80211_STA_INFO_SIGNAL) +#define STATION_INFO_TX_BITRATE BIT(NL80211_STA_INFO_TX_BITRATE) +#define STATION_INFO_RX_PACKETS BIT(NL80211_STA_INFO_RX_PACKETS) +#define STATION_INFO_TX_PACKETS BIT(NL80211_STA_INFO_TX_PACKETS) +#define STATION_INFO_ASSOC_REQ_IES 0 +#endif /* Linux kernel >= 4.0.0 */ + +#include + +#define RTW_MAX_MGMT_TX_CNT (8) +#define RTW_MAX_MGMT_TX_MS_GAS (500) + +#define RTW_SCAN_IE_LEN_MAX 2304 +#define RTW_MAX_REMAIN_ON_CHANNEL_DURATION 5000 //ms +#define RTW_MAX_NUM_PMKIDS 4 + +#define RTW_CH_MAX_2G_CHANNEL 14 /* Max channel in 2G band */ + +#ifdef CONFIG_WAPI_SUPPORT + +#ifndef WLAN_CIPHER_SUITE_SMS4 +#define WLAN_CIPHER_SUITE_SMS4 0x00147201 +#endif + +#ifndef WLAN_AKM_SUITE_WAPI_PSK +#define WLAN_AKM_SUITE_WAPI_PSK 0x000FAC04 +#endif + +#ifndef WLAN_AKM_SUITE_WAPI_CERT +#define WLAN_AKM_SUITE_WAPI_CERT 0x000FAC12 +#endif + +#ifndef NL80211_WAPI_VERSION_1 +#define NL80211_WAPI_VERSION_1 (1 << 2) +#endif + +#endif + +#ifdef CONFIG_PLATFORM_ARM_SUN8I +#define BUSY_TRAFFIC_SCAN_DENY_PERIOD 8000 +#else +#define BUSY_TRAFFIC_SCAN_DENY_PERIOD 12000 +#endif + +static const u32 rtw_cipher_suites[] = { + WLAN_CIPHER_SUITE_WEP40, + WLAN_CIPHER_SUITE_WEP104, + WLAN_CIPHER_SUITE_TKIP, + WLAN_CIPHER_SUITE_CCMP, +#ifdef CONFIG_WAPI_SUPPORT + WLAN_CIPHER_SUITE_SMS4, +#endif // CONFIG_WAPI_SUPPORT +#ifdef CONFIG_IEEE80211W + WLAN_CIPHER_SUITE_AES_CMAC, +#endif //CONFIG_IEEE80211W +}; + +#define RATETAB_ENT(_rate, _rateid, _flags) \ + { \ + .bitrate = (_rate), \ + .hw_value = (_rateid), \ + .flags = (_flags), \ + } + +#define CHAN2G(_channel, _freq, _flags) { \ + .band = IEEE80211_BAND_2GHZ, \ + .center_freq = (_freq), \ + .hw_value = (_channel), \ + .flags = (_flags), \ + .max_antenna_gain = 0, \ + .max_power = 30, \ +} + +#define CHAN5G(_channel, _flags) { \ + .band = IEEE80211_BAND_5GHZ, \ + .center_freq = 5000 + (5 * (_channel)), \ + .hw_value = (_channel), \ + .flags = (_flags), \ + .max_antenna_gain = 0, \ + .max_power = 30, \ +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) +/* if wowlan is not supported, kernel generate a disconnect at each suspend + * cf: /net/wireless/sysfs.c, so register a stub wowlan. + * Moreover wowlan has to be enabled via a the nl80211_set_wowlan callback. + * (from user space, e.g. iw phy0 wowlan enable) + */ +static const struct wiphy_wowlan_support wowlan_stub = { + .flags = WIPHY_WOWLAN_ANY, + .n_patterns = 0, + .pattern_max_len = 0, + .pattern_min_len = 0, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 10, 0)) + .max_pkt_offset = 0, +#endif +}; +#endif + +static struct ieee80211_rate rtw_rates[] = { + RATETAB_ENT(10, 0x1, 0), + RATETAB_ENT(20, 0x2, 0), + RATETAB_ENT(55, 0x4, 0), + RATETAB_ENT(110, 0x8, 0), + RATETAB_ENT(60, 0x10, 0), + RATETAB_ENT(90, 0x20, 0), + RATETAB_ENT(120, 0x40, 0), + RATETAB_ENT(180, 0x80, 0), + RATETAB_ENT(240, 0x100, 0), + RATETAB_ENT(360, 0x200, 0), + RATETAB_ENT(480, 0x400, 0), + RATETAB_ENT(540, 0x800, 0), +}; + +#define rtw_a_rates (rtw_rates + 4) +#define RTW_A_RATES_NUM 8 +#define rtw_g_rates (rtw_rates + 0) +#define RTW_G_RATES_NUM 12 + +#define RTW_2G_CHANNELS_NUM 14 +#define RTW_5G_CHANNELS_NUM 37 + +static struct ieee80211_channel rtw_2ghz_channels[] = { + CHAN2G(1, 2412, 0), + CHAN2G(2, 2417, 0), + CHAN2G(3, 2422, 0), + CHAN2G(4, 2427, 0), + CHAN2G(5, 2432, 0), + CHAN2G(6, 2437, 0), + CHAN2G(7, 2442, 0), + CHAN2G(8, 2447, 0), + CHAN2G(9, 2452, 0), + CHAN2G(10, 2457, 0), + CHAN2G(11, 2462, 0), + CHAN2G(12, 2467, 0), + CHAN2G(13, 2472, 0), + CHAN2G(14, 2484, 0), +}; + +static struct ieee80211_channel rtw_5ghz_a_channels[] = { + CHAN5G(34, 0), CHAN5G(36, 0), + CHAN5G(38, 0), CHAN5G(40, 0), + CHAN5G(42, 0), CHAN5G(44, 0), + CHAN5G(46, 0), CHAN5G(48, 0), + CHAN5G(52, 0), CHAN5G(56, 0), + CHAN5G(60, 0), CHAN5G(64, 0), + CHAN5G(100, 0), CHAN5G(104, 0), + CHAN5G(108, 0), CHAN5G(112, 0), + CHAN5G(116, 0), CHAN5G(120, 0), + CHAN5G(124, 0), CHAN5G(128, 0), + CHAN5G(132, 0), CHAN5G(136, 0), + CHAN5G(140, 0), CHAN5G(149, 0), + CHAN5G(153, 0), CHAN5G(157, 0), + CHAN5G(161, 0), CHAN5G(165, 0), + CHAN5G(184, 0), CHAN5G(188, 0), + CHAN5G(192, 0), CHAN5G(196, 0), + CHAN5G(200, 0), CHAN5G(204, 0), + CHAN5G(208, 0), CHAN5G(212, 0), + CHAN5G(216, 0), +}; + + +void rtw_2g_channels_init(struct ieee80211_channel *channels) +{ + _rtw_memcpy((void*)channels, (void*)rtw_2ghz_channels, + sizeof(struct ieee80211_channel)*RTW_2G_CHANNELS_NUM + ); +} + +void rtw_5g_channels_init(struct ieee80211_channel *channels) +{ + _rtw_memcpy((void*)channels, (void*)rtw_5ghz_a_channels, + sizeof(struct ieee80211_channel)*RTW_5G_CHANNELS_NUM + ); +} + +void rtw_2g_rates_init(struct ieee80211_rate *rates) +{ + _rtw_memcpy(rates, rtw_g_rates, + sizeof(struct ieee80211_rate)*RTW_G_RATES_NUM + ); +} + +void rtw_5g_rates_init(struct ieee80211_rate *rates) +{ + _rtw_memcpy(rates, rtw_a_rates, + sizeof(struct ieee80211_rate)*RTW_A_RATES_NUM + ); +} + +struct ieee80211_supported_band *rtw_spt_band_alloc( + enum ieee80211_band band + ) +{ + struct ieee80211_supported_band *spt_band = NULL; + int n_channels, n_bitrates; + + if(band == IEEE80211_BAND_2GHZ) + { + n_channels = RTW_2G_CHANNELS_NUM; + n_bitrates = RTW_G_RATES_NUM; + } + else if(band == IEEE80211_BAND_5GHZ) + { + n_channels = RTW_5G_CHANNELS_NUM; + n_bitrates = RTW_A_RATES_NUM; + } + else + { + goto exit; + } + + spt_band = (struct ieee80211_supported_band *)rtw_zmalloc( + sizeof(struct ieee80211_supported_band) + + sizeof(struct ieee80211_channel)*n_channels + + sizeof(struct ieee80211_rate)*n_bitrates + ); + if(!spt_band) + goto exit; + + spt_band->channels = (struct ieee80211_channel*)(((u8*)spt_band)+sizeof(struct ieee80211_supported_band)); + spt_band->bitrates= (struct ieee80211_rate*)(((u8*)spt_band->channels)+sizeof(struct ieee80211_channel)*n_channels); + spt_band->band = band; + spt_band->n_channels = n_channels; + spt_band->n_bitrates = n_bitrates; + + if(band == IEEE80211_BAND_2GHZ) + { + rtw_2g_channels_init(spt_band->channels); + rtw_2g_rates_init(spt_band->bitrates); + } + else if(band == IEEE80211_BAND_5GHZ) + { + rtw_5g_channels_init(spt_band->channels); + rtw_5g_rates_init(spt_band->bitrates); + } + + //spt_band.ht_cap + +exit: + + return spt_band; +} + +void rtw_spt_band_free(struct ieee80211_supported_band *spt_band) +{ + u32 size = 0; + + if(!spt_band) + return; + + if(spt_band->band == IEEE80211_BAND_2GHZ) + { + size = sizeof(struct ieee80211_supported_band) + + sizeof(struct ieee80211_channel)*RTW_2G_CHANNELS_NUM + + sizeof(struct ieee80211_rate)*RTW_G_RATES_NUM; + } + else if(spt_band->band == IEEE80211_BAND_5GHZ) + { + size = sizeof(struct ieee80211_supported_band) + + sizeof(struct ieee80211_channel)*RTW_5G_CHANNELS_NUM + + sizeof(struct ieee80211_rate)*RTW_A_RATES_NUM; + } + else + { + + } + rtw_mfree((u8*)spt_band, size); +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) +static const struct ieee80211_txrx_stypes +rtw_cfg80211_default_mgmt_stypes[NUM_NL80211_IFTYPES] = { + [NL80211_IFTYPE_ADHOC] = { + .tx = 0xffff, + .rx = BIT(IEEE80211_STYPE_ACTION >> 4) + }, + [NL80211_IFTYPE_STATION] = { + .tx = 0xffff, + .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | + BIT(IEEE80211_STYPE_PROBE_REQ >> 4) + }, + [NL80211_IFTYPE_AP] = { + .tx = 0xffff, + .rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) | + BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) | + BIT(IEEE80211_STYPE_PROBE_REQ >> 4) | + BIT(IEEE80211_STYPE_DISASSOC >> 4) | + BIT(IEEE80211_STYPE_AUTH >> 4) | + BIT(IEEE80211_STYPE_DEAUTH >> 4) | + BIT(IEEE80211_STYPE_ACTION >> 4) + }, + [NL80211_IFTYPE_AP_VLAN] = { + /* copy AP */ + .tx = 0xffff, + .rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) | + BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) | + BIT(IEEE80211_STYPE_PROBE_REQ >> 4) | + BIT(IEEE80211_STYPE_DISASSOC >> 4) | + BIT(IEEE80211_STYPE_AUTH >> 4) | + BIT(IEEE80211_STYPE_DEAUTH >> 4) | + BIT(IEEE80211_STYPE_ACTION >> 4) + }, + [NL80211_IFTYPE_P2P_CLIENT] = { + .tx = 0xffff, + .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | + BIT(IEEE80211_STYPE_PROBE_REQ >> 4) + }, + [NL80211_IFTYPE_P2P_GO] = { + .tx = 0xffff, + .rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) | + BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) | + BIT(IEEE80211_STYPE_PROBE_REQ >> 4) | + BIT(IEEE80211_STYPE_DISASSOC >> 4) | + BIT(IEEE80211_STYPE_AUTH >> 4) | + BIT(IEEE80211_STYPE_DEAUTH >> 4) | + BIT(IEEE80211_STYPE_ACTION >> 4) + }, +}; +#endif + +static u64 rtw_get_systime_us(void) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,39)) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,20,0)) + struct timespec64 ts; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,0,0)) + ktime_get_coarse_real_ts64(&ts); +#else + ts = current_kernel_time64(); +#endif +#else + struct timespec ts; + get_monotonic_boottime(&ts); +#endif + return ((u64)ts.tv_sec*1000000) + ts.tv_nsec / 1000; +#else + struct timeval tv; + do_gettimeofday(&tv); + return ((u64)tv.tv_sec*1000000) + tv.tv_usec; +#endif +} + +#define MAX_BSSINFO_LEN 1000 +struct cfg80211_bss *rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_network *pnetwork) +{ + struct ieee80211_channel *notify_channel; + struct cfg80211_bss *bss = NULL; + //struct ieee80211_supported_band *band; + u16 channel; + u32 freq; + u64 notify_timestamp; + u16 notify_capability; + u16 notify_interval; + u8 *notify_ie; + size_t notify_ielen; + s32 notify_signal; + //u8 buf[MAX_BSSINFO_LEN]; + + u8 *pbuf; + size_t buf_size = MAX_BSSINFO_LEN; + size_t len,bssinf_len=0; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + + struct wireless_dev *wdev = padapter->rtw_wdev; + struct wiphy *wiphy = wdev->wiphy; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + pbuf = rtw_zmalloc(buf_size); + if(pbuf == NULL){ + DBG_871X("%s pbuf allocate failed !! \n",__FUNCTION__); + return bss; + } + + //DBG_8192C("%s\n", __func__); + + bssinf_len = pnetwork->network.IELength+sizeof (struct rtw_ieee80211_hdr_3addr); + if(bssinf_len > buf_size){ + DBG_871X("%s IE Length too long > %zu byte \n",__FUNCTION__,buf_size); + goto exit; + } + +#ifndef CONFIG_WAPI_SUPPORT + { + u16 wapi_len = 0; + + if(rtw_get_wapi_ie(pnetwork->network.IEs, pnetwork->network.IELength, NULL, &wapi_len)>0) + { + if(wapi_len > 0) + { + DBG_871X("%s, no support wapi!\n",__FUNCTION__); + goto exit; + } + } + } +#endif //!CONFIG_WAPI_SUPPORT + + //To reduce PBC Overlap rate + //_enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL); + if(adapter_wdev_data(padapter)->scan_request != NULL) + { + u8 *psr=NULL, sr = 0; + NDIS_802_11_SSID *pssid = &pnetwork->network.Ssid; + struct cfg80211_scan_request *request = adapter_wdev_data(padapter)->scan_request; + struct cfg80211_ssid *ssids = request->ssids; + u32 wpsielen=0; + u8 *wpsie=NULL; + + wpsie = rtw_get_wps_ie(pnetwork->network.IEs+_FIXED_IE_LENGTH_, pnetwork->network.IELength-_FIXED_IE_LENGTH_, NULL, &wpsielen); + + if(wpsie && wpsielen>0) + psr = rtw_get_wps_attr_content(wpsie, wpsielen, WPS_ATTR_SELECTED_REGISTRAR, (u8*)(&sr), NULL); + + if (sr != 0) + { + if(request->n_ssids == 1 && request->n_channels == 1) // it means under processing WPS + { + DBG_8192C("ssid=%s, len=%d\n", pssid->Ssid, pssid->SsidLength); + + if (ssids[0].ssid_len == 0) { + } + else if(pssid->SsidLength == ssids[0].ssid_len && + _rtw_memcmp(pssid->Ssid, ssids[0].ssid, ssids[0].ssid_len)) + { + DBG_871X("%s, got sr and ssid match!\n", __func__); + } + else + { + if(psr !=NULL) + *psr = 0; //clear sr + +#if 0 + WLAN_BSSID_EX *pselect_network = &pnetwork->network; + struct cfg80211_bss *pselect_bss = NULL; + struct ieee80211_channel *notify_channel = NULL; + u32 freq; + + DBG_871X("%s, got sr, but ssid mismatch, to remove this bss\n", __func__); + + freq = rtw_ch2freq(pselect_network->Configuration.DSConfig); + notify_channel = ieee80211_get_channel(wiphy, freq); + pselect_bss = cfg80211_get_bss(wiphy, NULL/*notify_channel*/, + pselect_network->MacAddress, pselect_network->Ssid.Ssid, + pselect_network->Ssid.SsidLength, 0/*WLAN_CAPABILITY_ESS*/, + 0/*WLAN_CAPABILITY_ESS*/); + + if(pselect_bss) + { + DBG_871X("%s, got bss for cfg80211 for unlinking bss\n", __func__); + + cfg80211_unlink_bss(wiphy, pselect_bss); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) + cfg80211_put_bss(wiphy, pselect_bss); +#else + cfg80211_put_bss(pselect_bss); +#endif + + } + + goto exit; +#endif + } + } + } + } + //_exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL); + + + channel = pnetwork->network.Configuration.DSConfig; + freq = rtw_ch2freq(channel); + notify_channel = ieee80211_get_channel(wiphy, freq); + + if (0) + notify_timestamp = le64_to_cpu(*(u64*)rtw_get_timestampe_from_ie(pnetwork->network.IEs)); + else + notify_timestamp = rtw_get_systime_us(); + + notify_interval = le16_to_cpu(*(u16*)rtw_get_beacon_interval_from_ie(pnetwork->network.IEs)); + notify_capability = le16_to_cpu(*(u16*)rtw_get_capability_from_ie(pnetwork->network.IEs)); + + notify_ie = pnetwork->network.IEs+_FIXED_IE_LENGTH_; + notify_ielen = pnetwork->network.IELength-_FIXED_IE_LENGTH_; + + //We've set wiphy's signal_type as CFG80211_SIGNAL_TYPE_MBM: signal strength in mBm (100*dBm) + if ( check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE && + is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)) { + notify_signal = 100*translate_percentage_to_dbm(padapter->recvpriv.signal_strength);//dbm + } else { + notify_signal = 100*translate_percentage_to_dbm(pnetwork->network.PhyInfo.SignalStrength);//dbm + } + + #if 0 + DBG_8192C("bssid: "MAC_FMT"\n", MAC_ARG(pnetwork->network.MacAddress)); + DBG_8192C("Channel: %d(%d)\n", channel, freq); + DBG_8192C("Capability: %X\n", notify_capability); + DBG_8192C("Beacon interval: %d\n", notify_interval); + DBG_8192C("Signal: %d\n", notify_signal); + DBG_8192C("notify_timestamp: %llu\n", notify_timestamp); + #endif + + //pbuf = buf; + + pwlanhdr = (struct rtw_ieee80211_hdr *)pbuf; + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/); + //pmlmeext->mgnt_seq++; + + if (pnetwork->network.Reserved[0] == 1) { // WIFI_BEACON + _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); + SetFrameSubType(pbuf, WIFI_BEACON); + } else { + _rtw_memcpy(pwlanhdr->addr1, adapter_mac_addr(padapter), ETH_ALEN); + SetFrameSubType(pbuf, WIFI_PROBERSP); + } + + _rtw_memcpy(pwlanhdr->addr2, pnetwork->network.MacAddress, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, pnetwork->network.MacAddress, ETH_ALEN); + + + //pbuf += sizeof(struct rtw_ieee80211_hdr_3addr); + len = sizeof (struct rtw_ieee80211_hdr_3addr); + _rtw_memcpy((pbuf+len), pnetwork->network.IEs, pnetwork->network.IELength); + *((u64*)(pbuf+len)) = cpu_to_le64(notify_timestamp); + + len += pnetwork->network.IELength; + + //#ifdef CONFIG_P2P + //if(rtw_get_p2p_ie(pnetwork->network.IEs+12, pnetwork->network.IELength-12, NULL, NULL)) + //{ + // DBG_8192C("%s, got p2p_ie\n", __func__); + //} + //#endif + +#if 1 + bss = cfg80211_inform_bss_frame(wiphy, notify_channel, (struct ieee80211_mgmt *)pbuf, + len, notify_signal, GFP_ATOMIC); +#else + + bss = cfg80211_inform_bss(wiphy, notify_channel, (const u8 *)pnetwork->network.MacAddress, + notify_timestamp, notify_capability, notify_interval, notify_ie, + notify_ielen, notify_signal, GFP_ATOMIC/*GFP_KERNEL*/); +#endif + + if (unlikely(!bss)) { + DBG_8192C(FUNC_ADPT_FMT" bss NULL\n", FUNC_ADPT_ARG(padapter)); + goto exit; + } + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38)) +#ifndef COMPAT_KERNEL_RELEASE + //patch for cfg80211, update beacon ies to information_elements + if (pnetwork->network.Reserved[0] == 1) { // WIFI_BEACON + + if(bss->len_information_elements != bss->len_beacon_ies) + { + bss->information_elements = bss->beacon_ies; + bss->len_information_elements = bss->len_beacon_ies; + } + } +#endif //COMPAT_KERNEL_RELEASE +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38) + +/* + { + if( bss->information_elements == bss->proberesp_ies) + { + if( bss->len_information_elements != bss->len_proberesp_ies) + { + DBG_8192C("error!, len_information_elements != bss->len_proberesp_ies\n"); + } + + } + else if(bss->len_information_elements < bss->len_beacon_ies) + { + bss->information_elements = bss->beacon_ies; + bss->len_information_elements = bss->len_beacon_ies; + } + } +*/ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) + cfg80211_put_bss(wiphy, bss); +#else + cfg80211_put_bss(bss); +#endif + +exit: + if(pbuf) + rtw_mfree(pbuf, buf_size); + return bss; + +} + +/* + Check the given bss is valid by kernel API cfg80211_get_bss() + @padapter : the given adapter + + return _TRUE if bss is valid, _FALSE for not found. +*/ +int rtw_cfg80211_check_bss(_adapter *padapter) +{ + WLAN_BSSID_EX *pnetwork = &(padapter->mlmeextpriv.mlmext_info.network); + struct cfg80211_bss *bss = NULL; + struct ieee80211_channel *notify_channel = NULL; + u32 freq; + + if (!(pnetwork) || !(padapter->rtw_wdev)) + return _FALSE; + + freq = rtw_ch2freq(pnetwork->Configuration.DSConfig); + notify_channel = ieee80211_get_channel(padapter->rtw_wdev->wiphy, freq); + bss = cfg80211_get_bss(padapter->rtw_wdev->wiphy, notify_channel, + pnetwork->MacAddress, pnetwork->Ssid.Ssid, + pnetwork->Ssid.SsidLength, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) + pnetwork->InfrastructureMode == Ndis802_11Infrastructure?IEEE80211_BSS_TYPE_ESS:IEEE80211_BSS_TYPE_IBSS, + IEEE80211_PRIVACY(pnetwork->Privacy)); +#else + pnetwork->InfrastructureMode == Ndis802_11Infrastructure?WLAN_CAPABILITY_ESS:WLAN_CAPABILITY_IBSS, pnetwork->InfrastructureMode == Ndis802_11Infrastructure?WLAN_CAPABILITY_ESS:WLAN_CAPABILITY_IBSS); +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) + cfg80211_put_bss(padapter->rtw_wdev->wiphy, bss); +#else + cfg80211_put_bss(bss); +#endif + + return (bss!=NULL); +} + +void rtw_cfg80211_ibss_indicate_connect(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wlan_network *cur_network = &(pmlmepriv->cur_network); + struct wireless_dev *pwdev = padapter->rtw_wdev; + struct cfg80211_bss *bss = NULL; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)) + struct wiphy *wiphy = pwdev->wiphy; + int freq = 2412; + struct ieee80211_channel *notify_channel; +#endif + + DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)) + freq = rtw_ch2freq(cur_network->network.Configuration.DSConfig); + + if (0) + DBG_871X("chan: %d, freq: %d\n", cur_network->network.Configuration.DSConfig, freq); +#endif + + if (pwdev->iftype != NL80211_IFTYPE_ADHOC) + { + return; + } + + if (!rtw_cfg80211_check_bss(padapter)) { + WLAN_BSSID_EX *pnetwork = &(padapter->mlmeextpriv.mlmext_info.network); + struct wlan_network *scanned = pmlmepriv->cur_network_scanned; + + if(check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)==_TRUE) + { + + _rtw_memcpy(&cur_network->network, pnetwork, sizeof(WLAN_BSSID_EX)); + if(cur_network) + { + if (!rtw_cfg80211_inform_bss(padapter,cur_network)) + DBG_871X(FUNC_ADPT_FMT" inform fail !!\n", FUNC_ADPT_ARG(padapter)); + else + DBG_871X(FUNC_ADPT_FMT" inform success !!\n", FUNC_ADPT_ARG(padapter)); + } + else + { + DBG_871X("cur_network is not exist!!!\n"); + return ; + } + } + else + { + if(scanned == NULL) + rtw_warn_on(1); + + if (_rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE + && _rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE + ) { + if (!rtw_cfg80211_inform_bss(padapter,scanned)) { + DBG_871X(FUNC_ADPT_FMT" inform fail !!\n", FUNC_ADPT_ARG(padapter)); + } else { + //DBG_871X(FUNC_ADPT_FMT" inform success !!\n", FUNC_ADPT_ARG(padapter)); + } + } else { + DBG_871X("scanned & pnetwork compare fail\n"); + rtw_warn_on(1); + } + } + + if (!rtw_cfg80211_check_bss(padapter)) + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" BSS not found !!\n", FUNC_ADPT_ARG(padapter)); + } + //notify cfg80211 that device joined an IBSS +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)) + notify_channel = ieee80211_get_channel(wiphy, freq); + cfg80211_ibss_joined(padapter->pnetdev, cur_network->network.MacAddress, notify_channel, GFP_ATOMIC); +#else + cfg80211_ibss_joined(padapter->pnetdev, cur_network->network.MacAddress, GFP_ATOMIC); +#endif +} + +void rtw_cfg80211_indicate_connect(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wlan_network *cur_network = &(pmlmepriv->cur_network); + struct wireless_dev *pwdev = padapter->rtw_wdev; +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); +#endif + struct cfg80211_bss *bss = NULL; + + DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + if (pwdev->iftype != NL80211_IFTYPE_STATION + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) + && pwdev->iftype != NL80211_IFTYPE_P2P_CLIENT + #endif + ) { + return; + } + + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + return; + +#ifdef CONFIG_P2P + if(pwdinfo->driver_interface == DRIVER_CFG80211 ) + { + if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + { + rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); + rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); + DBG_8192C("%s, role=%d, p2p_state=%d, pre_p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), rtw_p2p_pre_state(pwdinfo)); + } + } +#endif //CONFIG_P2P + + if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) != _TRUE) { + WLAN_BSSID_EX *pnetwork = &(padapter->mlmeextpriv.mlmext_info.network); + struct wlan_network *scanned = pmlmepriv->cur_network_scanned; + + //DBG_871X(FUNC_ADPT_FMT" BSS not found\n", FUNC_ADPT_ARG(padapter)); + + if(scanned == NULL) { + rtw_warn_on(1); + goto check_bss; + } + + if (_rtw_memcmp(scanned->network.MacAddress, pnetwork->MacAddress, sizeof(NDIS_802_11_MAC_ADDRESS)) == _TRUE + && _rtw_memcmp(&(scanned->network.Ssid), &(pnetwork->Ssid), sizeof(NDIS_802_11_SSID)) == _TRUE + ) { + if (!rtw_cfg80211_inform_bss(padapter,scanned)) { + DBG_871X(FUNC_ADPT_FMT" inform fail !!\n", FUNC_ADPT_ARG(padapter)); + } else { + //DBG_871X(FUNC_ADPT_FMT" inform success !!\n", FUNC_ADPT_ARG(padapter)); + } + } else { + DBG_871X("scanned: %s("MAC_FMT"), cur: %s("MAC_FMT")\n", + scanned->network.Ssid.Ssid, MAC_ARG(scanned->network.MacAddress), + pnetwork->Ssid.Ssid, MAC_ARG(pnetwork->MacAddress) + ); + rtw_warn_on(1); + } + } + +check_bss: + if (!rtw_cfg80211_check_bss(padapter)) + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" BSS not found !!\n", FUNC_ADPT_ARG(padapter)); + + if (rtw_to_roam(padapter) > 0) { + #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39) || defined(COMPAT_KERNEL_RELEASE) + struct wiphy *wiphy = pwdev->wiphy; + struct ieee80211_channel *notify_channel; + u32 freq; + u16 channel = cur_network->network.Configuration.DSConfig; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0)) + struct cfg80211_roam_info roam_info; +#endif + + freq = rtw_ch2freq(channel); + notify_channel = ieee80211_get_channel(wiphy, freq); + #endif + + DBG_871X(FUNC_ADPT_FMT" call cfg80211_roamed\n", FUNC_ADPT_ARG(padapter)); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0)) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0)) + roam_info.links[0].bssid = cur_network->network.MacAddress; +#else + roam_info.bssid = cur_network->network.MacAddress; +#endif + roam_info.req_ie = pmlmepriv->assoc_req+sizeof(struct rtw_ieee80211_hdr_3addr)+2; + roam_info.req_ie_len = pmlmepriv->assoc_req_len-sizeof(struct rtw_ieee80211_hdr_3addr)-2; + roam_info.resp_ie = pmlmepriv->assoc_rsp+sizeof(struct rtw_ieee80211_hdr_3addr)+6, + roam_info.resp_ie_len = pmlmepriv->assoc_rsp_len-sizeof(struct rtw_ieee80211_hdr_3addr)-6; + + cfg80211_roamed(padapter->pnetdev, &roam_info, GFP_KERNEL); +#else + cfg80211_roamed(padapter->pnetdev + #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39) || defined(COMPAT_KERNEL_RELEASE) + , notify_channel + #endif + , cur_network->network.MacAddress + , pmlmepriv->assoc_req+sizeof(struct rtw_ieee80211_hdr_3addr)+2 + , pmlmepriv->assoc_req_len-sizeof(struct rtw_ieee80211_hdr_3addr)-2 + , pmlmepriv->assoc_rsp+sizeof(struct rtw_ieee80211_hdr_3addr)+6 + , pmlmepriv->assoc_rsp_len-sizeof(struct rtw_ieee80211_hdr_3addr)-6 + , GFP_ATOMIC); +#endif + } + else + { + #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE) + DBG_8192C("pwdev->sme_state(b)=%d\n", pwdev->sme_state); + #endif + cfg80211_connect_result(padapter->pnetdev, cur_network->network.MacAddress + , pmlmepriv->assoc_req+sizeof(struct rtw_ieee80211_hdr_3addr)+2 + , pmlmepriv->assoc_req_len-sizeof(struct rtw_ieee80211_hdr_3addr)-2 + , pmlmepriv->assoc_rsp+sizeof(struct rtw_ieee80211_hdr_3addr)+6 + , pmlmepriv->assoc_rsp_len-sizeof(struct rtw_ieee80211_hdr_3addr)-6 + , WLAN_STATUS_SUCCESS, GFP_ATOMIC); + #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE) + DBG_8192C("pwdev->sme_state(a)=%d\n", pwdev->sme_state); + #endif + } +} + +void rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generated) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct wireless_dev *pwdev = padapter->rtw_wdev; +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); +#endif + + DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + + /*always replace privated definitions with wifi reserved value 0*/ + if ((reason == WLAN_REASON_ACTIVE_ROAM) || (reason == WLAN_REASON_JOIN_WRONG_CHANNEL) || (reason == WLAN_REASON_EXPIRATION_CHK)) { + reason = 0; + } + + if (pwdev->iftype != NL80211_IFTYPE_STATION + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) + && pwdev->iftype != NL80211_IFTYPE_P2P_CLIENT + #endif + ) { + return; + } + + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + return; + +#ifdef CONFIG_P2P + if( pwdinfo->driver_interface == DRIVER_CFG80211 ) + { + if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + { + rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); + + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE) + if (pwdev->iftype != NL80211_IFTYPE_P2P_CLIENT) + #endif + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); + + DBG_8192C("%s, role=%d, p2p_state=%d, pre_p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), rtw_p2p_pre_state(pwdinfo)); + } + } +#endif //CONFIG_P2P + + #ifdef SUPPLICANT_RTK_VERSION_LOWER_THAN_JB42 + if (!padapter->mlmepriv.not_indic_disco || padapter->ndev_unregistering) { + #else + { + #endif + #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) || defined(COMPAT_KERNEL_RELEASE) + DBG_8192C("pwdev->sme_state(b)=%d\n", pwdev->sme_state); + + if(pwdev->sme_state==CFG80211_SME_CONNECTING) + cfg80211_connect_result(padapter->pnetdev, NULL, NULL, 0, NULL, 0, + WLAN_STATUS_UNSPECIFIED_FAILURE, GFP_ATOMIC/*GFP_KERNEL*/); + else if (pwdev->sme_state == CFG80211_SME_CONNECTED) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0)) + cfg80211_disconnected(padapter->pnetdev, reason, NULL, 0, locally_generated, GFP_ATOMIC); +#else + cfg80211_disconnected(padapter->pnetdev, 0, NULL, 0, GFP_ATOMIC); +#endif + } + //else + //DBG_8192C("pwdev->sme_state=%d\n", pwdev->sme_state); + + DBG_8192C("pwdev->sme_state(a)=%d\n", pwdev->sme_state); + #else + + if (check_fwstate(&padapter->mlmepriv, _FW_LINKED)) { +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0)) + DBG_871X(FUNC_ADPT_FMT" call cfg80211_disconnected\n", FUNC_ADPT_ARG(padapter)); + cfg80211_disconnected(padapter->pnetdev, reason, NULL, 0, locally_generated, GFP_ATOMIC); +#else + DBG_871X(FUNC_ADPT_FMT" call cfg80211_disconnected\n", FUNC_ADPT_ARG(padapter)); + cfg80211_disconnected(padapter->pnetdev, 0, NULL, 0, GFP_ATOMIC); +#endif + } else { + DBG_871X(FUNC_ADPT_FMT" call cfg80211_connect_result\n", FUNC_ADPT_ARG(padapter)); + cfg80211_connect_result(padapter->pnetdev, NULL, NULL, 0, NULL, 0, + WLAN_STATUS_UNSPECIFIED_FAILURE, GFP_ATOMIC); + } + #endif + } +} + + +#ifdef CONFIG_AP_MODE +static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) +{ + int ret = 0; + u32 wep_key_idx, wep_key_len,wep_total_len; + struct sta_info *psta = NULL, *pbcmc_sta = NULL; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv* psecuritypriv=&(padapter->securitypriv); + struct sta_priv *pstapriv = &padapter->stapriv; + + DBG_8192C("%s\n", __FUNCTION__); + + param->u.crypt.err = 0; + param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0'; + + //sizeof(struct ieee_param) = 64 bytes; + //if (param_len != (u32) ((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) + if (param_len != sizeof(struct ieee_param) + param->u.crypt.key_len) + { + ret = -EINVAL; + goto exit; + } + + if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) + { + if (param->u.crypt.idx >= WEP_KEYS +#ifdef CONFIG_IEEE80211W + && param->u.crypt.idx > BIP_MAX_KEYID +#endif /* CONFIG_IEEE80211W */ + ) + { + ret = -EINVAL; + goto exit; + } + } + else + { + psta = rtw_get_stainfo(pstapriv, param->sta_addr); + if(!psta) + { + //ret = -EINVAL; + DBG_8192C("rtw_set_encryption(), sta has already been removed or never been added\n"); + goto exit; + } + } + + if (strcmp(param->u.crypt.alg, "none") == 0 && (psta==NULL)) + { + //todo:clear default encryption keys + + DBG_8192C("clear default encryption keys, keyid=%d\n", param->u.crypt.idx); + + goto exit; + } + + + if (strcmp(param->u.crypt.alg, "WEP") == 0 && (psta==NULL)) + { + DBG_8192C("r871x_set_encryption, crypt.alg = WEP\n"); + + wep_key_idx = param->u.crypt.idx; + wep_key_len = param->u.crypt.key_len; + + DBG_8192C("r871x_set_encryption, wep_key_idx=%d, len=%d\n", wep_key_idx, wep_key_len); + + if((wep_key_idx >= WEP_KEYS) || (wep_key_len<=0)) + { + ret = -EINVAL; + goto exit; + } + + if (wep_key_len > 0) + { + wep_key_len = wep_key_len <= 5 ? 5 : 13; + } + + if (psecuritypriv->bWepDefaultKeyIdxSet == 0) + { + //wep default key has not been set, so use this key index as default key. + + psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Auto; + psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled; + psecuritypriv->dot11PrivacyAlgrthm=_WEP40_; + psecuritypriv->dot118021XGrpPrivacy=_WEP40_; + + if(wep_key_len == 13) + { + psecuritypriv->dot11PrivacyAlgrthm=_WEP104_; + psecuritypriv->dot118021XGrpPrivacy=_WEP104_; + } + + psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx; + } + + _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), param->u.crypt.key, wep_key_len); + + psecuritypriv->dot11DefKeylen[wep_key_idx] = wep_key_len; + + rtw_ap_set_wep_key(padapter, param->u.crypt.key, wep_key_len, wep_key_idx, 1); + + goto exit; + + } + + + if(!psta && check_fwstate(pmlmepriv, WIFI_AP_STATE)) // //group key + { + if(param->u.crypt.set_tx == 0) //group key + { + if(strcmp(param->u.crypt.alg, "WEP") == 0) + { + DBG_8192C("%s, set group_key, WEP\n", __FUNCTION__); + + _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); + + psecuritypriv->dot118021XGrpPrivacy = _WEP40_; + if(param->u.crypt.key_len==13) + { + psecuritypriv->dot118021XGrpPrivacy = _WEP104_; + } + + } + else if(strcmp(param->u.crypt.alg, "TKIP") == 0) + { + DBG_8192C("%s, set group_key, TKIP\n", __FUNCTION__); + + psecuritypriv->dot118021XGrpPrivacy = _TKIP_; + + _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); + + //DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); + //set mic key + _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); + _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); + + psecuritypriv->busetkipkey = _TRUE; + + } + else if(strcmp(param->u.crypt.alg, "CCMP") == 0) + { + DBG_8192C("%s, set group_key, CCMP\n", __FUNCTION__); + + psecuritypriv->dot118021XGrpPrivacy = _AES_; + + _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); + } +#ifdef CONFIG_IEEE80211W + else if (strcmp(param->u.crypt.alg, "BIP") == 0) { + int no; + + DBG_871X("BIP key_len=%d , index=%d\n", param->u.crypt.key_len, param->u.crypt.idx); + /* save the IGTK key, length 16 bytes */ + _rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16:param->u.crypt.key_len)); + /* DBG_871X("IGTK key below:\n"); + for(no=0;no<16;no++) + printk(" %02x ", padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey[no]); + DBG_871X("\n"); */ + padapter->securitypriv.dot11wBIPKeyid = param->u.crypt.idx; + padapter->securitypriv.binstallBIPkey = _TRUE; + DBG_871X(" ~~~~set sta key:IGKT\n"); + goto exit; + } +#endif /* CONFIG_IEEE80211W */ + else + { + DBG_8192C("%s, set group_key, none\n", __FUNCTION__); + + psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; + } + + psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx; + + psecuritypriv->binstallGrpkey = _TRUE; + + psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;//!!! + + rtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); + + pbcmc_sta=rtw_get_bcmc_stainfo(padapter); + if(pbcmc_sta) + { + pbcmc_sta->ieee8021x_blocked = _FALSE; + pbcmc_sta->dot118021XPrivacy= psecuritypriv->dot118021XGrpPrivacy;//rx will use bmc_sta's dot118021XPrivacy + } + + } + + goto exit; + + } + + if(psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X && psta) // psk/802_1x + { + if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) + { + if(param->u.crypt.set_tx ==1) //pairwise key + { + _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); + + if(strcmp(param->u.crypt.alg, "WEP") == 0) + { + DBG_8192C("%s, set pairwise key, WEP\n", __FUNCTION__); + + psta->dot118021XPrivacy = _WEP40_; + if(param->u.crypt.key_len==13) + { + psta->dot118021XPrivacy = _WEP104_; + } + } + else if(strcmp(param->u.crypt.alg, "TKIP") == 0) + { + DBG_8192C("%s, set pairwise key, TKIP\n", __FUNCTION__); + + psta->dot118021XPrivacy = _TKIP_; + + //DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); + //set mic key + _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); + _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); + + psecuritypriv->busetkipkey = _TRUE; + + } + else if(strcmp(param->u.crypt.alg, "CCMP") == 0) + { + + DBG_8192C("%s, set pairwise key, CCMP\n", __FUNCTION__); + + psta->dot118021XPrivacy = _AES_; + } + else + { + DBG_8192C("%s, set pairwise key, none\n", __FUNCTION__); + + psta->dot118021XPrivacy = _NO_PRIVACY_; + } + + rtw_ap_set_pairwise_key(padapter, psta); + + psta->ieee8021x_blocked = _FALSE; + + psta->bpairwise_key_installed = _TRUE; + + } + else//group key??? + { + if(strcmp(param->u.crypt.alg, "WEP") == 0) + { + _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); + + psecuritypriv->dot118021XGrpPrivacy = _WEP40_; + if(param->u.crypt.key_len==13) + { + psecuritypriv->dot118021XGrpPrivacy = _WEP104_; + } + } + else if(strcmp(param->u.crypt.alg, "TKIP") == 0) + { + psecuritypriv->dot118021XGrpPrivacy = _TKIP_; + + _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); + + //DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); + //set mic key + _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); + _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); + + psecuritypriv->busetkipkey = _TRUE; + + } + else if(strcmp(param->u.crypt.alg, "CCMP") == 0) + { + psecuritypriv->dot118021XGrpPrivacy = _AES_; + + _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); + } + else + { + psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; + } + + psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx; + + psecuritypriv->binstallGrpkey = _TRUE; + + psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;//!!! + + rtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); + + pbcmc_sta=rtw_get_bcmc_stainfo(padapter); + if(pbcmc_sta) + { + pbcmc_sta->ieee8021x_blocked = _FALSE; + pbcmc_sta->dot118021XPrivacy= psecuritypriv->dot118021XGrpPrivacy;//rx will use bmc_sta's dot118021XPrivacy + } + + } + + } + + } + +exit: + + return ret; + +} +#endif + +static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) +{ + int ret = 0; + u32 wep_key_idx, wep_key_len,wep_total_len; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; +#ifdef CONFIG_P2P + struct wifidirect_info* pwdinfo = &padapter->wdinfo; +#endif //CONFIG_P2P + +_func_enter_; + + DBG_8192C("%s\n", __func__); + + param->u.crypt.err = 0; + param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0'; + + if (param_len < (u32) ((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) + { + ret = -EINVAL; + goto exit; + } + + if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) + { + if (param->u.crypt.idx >= WEP_KEYS +#ifdef CONFIG_IEEE80211W + && param->u.crypt.idx > BIP_MAX_KEYID +#endif //CONFIG_IEEE80211W + ) + { + ret = -EINVAL; + goto exit; + } + } else { +#ifdef CONFIG_WAPI_SUPPORT + if (strcmp(param->u.crypt.alg, "SMS4")) +#endif + { + ret = -EINVAL; + goto exit; + } + } + + if (strcmp(param->u.crypt.alg, "WEP") == 0) + { + RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("wpa_set_encryption, crypt.alg = WEP\n")); + DBG_8192C("wpa_set_encryption, crypt.alg = WEP\n"); + + wep_key_idx = param->u.crypt.idx; + wep_key_len = param->u.crypt.key_len; + + if ((wep_key_idx > WEP_KEYS) || (wep_key_len <= 0)) + { + ret = -EINVAL; + goto exit; + } + + if (psecuritypriv->bWepDefaultKeyIdxSet == 0) + { + //wep default key has not been set, so use this key index as default key. + + wep_key_len = wep_key_len <= 5 ? 5 : 13; + + psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled; + psecuritypriv->dot11PrivacyAlgrthm = _WEP40_; + psecuritypriv->dot118021XGrpPrivacy = _WEP40_; + + if(wep_key_len==13) + { + psecuritypriv->dot11PrivacyAlgrthm = _WEP104_; + psecuritypriv->dot118021XGrpPrivacy = _WEP104_; + } + + psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx; + } + + _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), param->u.crypt.key, wep_key_len); + + psecuritypriv->dot11DefKeylen[wep_key_idx] = wep_key_len; + + rtw_set_key(padapter, psecuritypriv, wep_key_idx, 0, _TRUE); + + goto exit; + } + + if(padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) // 802_1x + { + struct sta_info * psta,*pbcmc_sta; + struct sta_priv * pstapriv = &padapter->stapriv; + + //DBG_8192C("%s, : dot11AuthAlgrthm == dot11AuthAlgrthm_8021X \n", __func__); + + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_MP_STATE) == _TRUE) //sta mode + { + psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); + if (psta == NULL) { + //DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail \n")); + DBG_8192C("%s, : Obtain Sta_info fail \n", __func__); + } + else + { + //Jeff: don't disable ieee8021x_blocked while clearing key + if (strcmp(param->u.crypt.alg, "none") != 0) + psta->ieee8021x_blocked = _FALSE; + + + if((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled)|| + (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled)) + { + psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; + } + + if(param->u.crypt.set_tx ==1)//pairwise key + { + + DBG_8192C("%s, : param->u.crypt.set_tx ==1 \n", __func__); + + _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); + + if(strcmp(param->u.crypt.alg, "TKIP") == 0)//set mic key + { + //DEBUG_ERR(("\nset key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len)); + _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); + _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); + + padapter->securitypriv.busetkipkey=_FALSE; + //_set_timer(&padapter->securitypriv.tkip_timer, 50); + } + psta->bpairwise_key_installed = _TRUE; + //DEBUG_ERR((" param->u.crypt.key_len=%d\n",param->u.crypt.key_len)); + DBG_871X(" ~~~~set sta key:unicastkey\n"); + + rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _TRUE); + } + else//group key + { + if(strcmp(param->u.crypt.alg, "TKIP") == 0 || strcmp(param->u.crypt.alg, "CCMP") == 0) + { + _rtw_memcpy(padapter->securitypriv.dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key,(param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); + _rtw_memcpy(padapter->securitypriv.dot118021XGrptxmickey[param->u.crypt.idx].skey,&(param->u.crypt.key[16]),8); + _rtw_memcpy(padapter->securitypriv.dot118021XGrprxmickey[param->u.crypt.idx].skey,&(param->u.crypt.key[24]),8); + padapter->securitypriv.binstallGrpkey = _TRUE; + //DEBUG_ERR((" param->u.crypt.key_len=%d\n", param->u.crypt.key_len)); + DBG_871X(" ~~~~set sta key:groupkey\n"); + + padapter->securitypriv.dot118021XGrpKeyid = param->u.crypt.idx; + rtw_set_key(padapter,&padapter->securitypriv,param->u.crypt.idx, 1, _TRUE); + } +#ifdef CONFIG_IEEE80211W + else if(strcmp(param->u.crypt.alg, "BIP") == 0) + { + int no; + //DBG_871X("BIP key_len=%d , index=%d @@@@@@@@@@@@@@@@@@\n", param->u.crypt.key_len, param->u.crypt.idx); + //save the IGTK key, length 16 bytes + _rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key,(param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); + /*DBG_871X("IGTK key below:\n"); + for(no=0;no<16;no++) + printk(" %02x ", padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey[no]); + DBG_871X("\n");*/ + padapter->securitypriv.dot11wBIPKeyid = param->u.crypt.idx; + padapter->securitypriv.binstallBIPkey = _TRUE; + DBG_871X(" ~~~~set sta key:IGKT\n"); + } +#endif //CONFIG_IEEE80211W + +#ifdef CONFIG_P2P + if(pwdinfo->driver_interface == DRIVER_CFG80211 ) + { + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING)) + { + rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_DONE); + } + } +#endif //CONFIG_P2P + + } + } + + pbcmc_sta=rtw_get_bcmc_stainfo(padapter); + if(pbcmc_sta==NULL) + { + //DEBUG_ERR( ("Set OID_802_11_ADD_KEY: bcmc stainfo is null \n")); + } + else + { + //Jeff: don't disable ieee8021x_blocked while clearing key + if (strcmp(param->u.crypt.alg, "none") != 0) + pbcmc_sta->ieee8021x_blocked = _FALSE; + + if((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled)|| + (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled)) + { + pbcmc_sta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; + } + } + } + else if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) //adhoc mode + { + } + } + +#ifdef CONFIG_WAPI_SUPPORT + if (strcmp(param->u.crypt.alg, "SMS4") == 0) + { + PRT_WAPI_T pWapiInfo = &padapter->wapiInfo; + PRT_WAPI_STA_INFO pWapiSta; + u8 WapiASUEPNInitialValueSrc[16] = {0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; + u8 WapiAEPNInitialValueSrc[16] = {0x37,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; + u8 WapiAEMultiCastPNInitialValueSrc[16] = {0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; + + if(param->u.crypt.set_tx == 1) + { + list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { + if(_rtw_memcmp(pWapiSta->PeerMacAddr,param->sta_addr,6)) + { + _rtw_memcpy(pWapiSta->lastTxUnicastPN,WapiASUEPNInitialValueSrc,16); + + pWapiSta->wapiUsk.bSet = true; + _rtw_memcpy(pWapiSta->wapiUsk.dataKey,param->u.crypt.key,16); + _rtw_memcpy(pWapiSta->wapiUsk.micKey,param->u.crypt.key+16,16); + pWapiSta->wapiUsk.keyId = param->u.crypt.idx ; + pWapiSta->wapiUsk.bTxEnable = true; + + _rtw_memcpy(pWapiSta->lastRxUnicastPNBEQueue,WapiAEPNInitialValueSrc,16); + _rtw_memcpy(pWapiSta->lastRxUnicastPNBKQueue,WapiAEPNInitialValueSrc,16); + _rtw_memcpy(pWapiSta->lastRxUnicastPNVIQueue,WapiAEPNInitialValueSrc,16); + _rtw_memcpy(pWapiSta->lastRxUnicastPNVOQueue,WapiAEPNInitialValueSrc,16); + _rtw_memcpy(pWapiSta->lastRxUnicastPN,WapiAEPNInitialValueSrc,16); + pWapiSta->wapiUskUpdate.bTxEnable = false; + pWapiSta->wapiUskUpdate.bSet = false; + + if (psecuritypriv->sw_encrypt== false || psecuritypriv->sw_decrypt == false) + { + //set unicast key for ASUE + rtw_wapi_set_key(padapter, &pWapiSta->wapiUsk, pWapiSta, false, false); + } + } + } + } + else + { + list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { + if(_rtw_memcmp(pWapiSta->PeerMacAddr,get_bssid(pmlmepriv),6)) + { + pWapiSta->wapiMsk.bSet = true; + _rtw_memcpy(pWapiSta->wapiMsk.dataKey,param->u.crypt.key,16); + _rtw_memcpy(pWapiSta->wapiMsk.micKey,param->u.crypt.key+16,16); + pWapiSta->wapiMsk.keyId = param->u.crypt.idx ; + pWapiSta->wapiMsk.bTxEnable = false; + if(!pWapiSta->bSetkeyOk) + pWapiSta->bSetkeyOk = true; + pWapiSta->bAuthenticateInProgress = false; + + _rtw_memcpy(pWapiSta->lastRxMulticastPN, WapiAEMultiCastPNInitialValueSrc, 16); + + if (psecuritypriv->sw_decrypt == false) + { + //set rx broadcast key for ASUE + rtw_wapi_set_key(padapter, &pWapiSta->wapiMsk, pWapiSta, true, false); + } + } + + } + } + } +#endif + + +exit: + + DBG_8192C("%s, ret=%d\n", __func__, ret); + + _func_exit_; + + return ret; +} + +static int cfg80211_rtw_add_key(struct wiphy *wiphy, struct net_device *ndev, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,1,0)) + int link_id, +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) + u8 key_index, bool pairwise, const u8 *mac_addr, +#else // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) + u8 key_index, const u8 *mac_addr, +#endif // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) + struct key_params *params) +{ + char *alg_name; + u32 param_len; + struct ieee_param *param = NULL; + int ret=0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct wireless_dev *rtw_wdev = padapter->rtw_wdev; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; +#ifdef CONFIG_TDLS + struct sta_info *ptdls_sta; +#endif /* CONFIG_TDLS */ + + DBG_871X(FUNC_NDEV_FMT" adding key for %pM\n", FUNC_NDEV_ARG(ndev), mac_addr); + DBG_871X("cipher=0x%x\n", params->cipher); + DBG_871X("key_len=0x%x\n", params->key_len); + DBG_871X("seq_len=0x%x\n", params->seq_len); + DBG_871X("key_index=%d\n", key_index); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) + DBG_871X("pairwise=%d\n", pairwise); +#endif // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) + + param_len = sizeof(struct ieee_param) + params->key_len; + param = (struct ieee_param *)rtw_malloc(param_len); + if (param == NULL) + return -1; + + _rtw_memset(param, 0, param_len); + + param->cmd = IEEE_CMD_SET_ENCRYPTION; + _rtw_memset(param->sta_addr, 0xff, ETH_ALEN); + + switch (params->cipher) { + case IW_AUTH_CIPHER_NONE: + //todo: remove key + //remove = 1; + alg_name = "none"; + break; + case WLAN_CIPHER_SUITE_WEP40: + case WLAN_CIPHER_SUITE_WEP104: + alg_name = "WEP"; + break; + case WLAN_CIPHER_SUITE_TKIP: + alg_name = "TKIP"; + break; + case WLAN_CIPHER_SUITE_CCMP: + alg_name = "CCMP"; + break; +#ifdef CONFIG_IEEE80211W + case WLAN_CIPHER_SUITE_AES_CMAC: + alg_name = "BIP"; + break; +#endif //CONFIG_IEEE80211W +#ifdef CONFIG_WAPI_SUPPORT + case WLAN_CIPHER_SUITE_SMS4: + alg_name= "SMS4"; + if(pairwise == NL80211_KEYTYPE_PAIRWISE) { + if (key_index != 0 && key_index != 1) { + ret = -ENOTSUPP; + goto addkey_end; + } + _rtw_memcpy((void*)param->sta_addr, (void*)mac_addr, ETH_ALEN); + } else { + DBG_871X("mac_addr is null \n"); + } + DBG_871X("rtw_wx_set_enc_ext: SMS4 case \n"); + break; +#endif + + default: + ret = -ENOTSUPP; + goto addkey_end; + } + + strncpy((char *)param->u.crypt.alg, alg_name, IEEE_CRYPT_ALG_NAME_LEN); + + + if (!mac_addr || is_broadcast_ether_addr(mac_addr)) + { + param->u.crypt.set_tx = 0; //for wpa/wpa2 group key + } else { + param->u.crypt.set_tx = 1; //for wpa/wpa2 pairwise key + } + + + //param->u.crypt.idx = key_index - 1; + param->u.crypt.idx = key_index; + + if (params->seq_len && params->seq) + { + _rtw_memcpy(param->u.crypt.seq, (u8 *)params->seq, params->seq_len); + } + + if(params->key_len && params->key) + { + param->u.crypt.key_len = params->key_len; + _rtw_memcpy(param->u.crypt.key, (u8 *)params->key, params->key_len); + } + + if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) + { +#ifdef CONFIG_TDLS + if (rtw_tdls_is_driver_setup(padapter) == _FALSE && mac_addr) { + ptdls_sta = rtw_get_stainfo(&padapter->stapriv, (void *)mac_addr); + if (ptdls_sta != NULL && ptdls_sta->tdls_sta_state) { + _rtw_memcpy(ptdls_sta->tpk.tk, params->key, params->key_len); + rtw_tdls_set_key(padapter, ptdls_sta); + goto addkey_end; + } + } +#endif /* CONFIG_TDLS */ + + ret = rtw_cfg80211_set_encryption(ndev, param, param_len); + } + else if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + { +#ifdef CONFIG_AP_MODE + if(mac_addr) + _rtw_memcpy(param->sta_addr, (void*)mac_addr, ETH_ALEN); + + ret = rtw_cfg80211_ap_set_encryption(ndev, param, param_len); +#endif + } + else if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE + || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) + { + //DBG_8192C("@@@@@@@@@@ fw_state=0x%x, iftype=%d\n", pmlmepriv->fw_state, rtw_wdev->iftype); + ret = rtw_cfg80211_set_encryption(ndev, param, param_len); + } + else + { + DBG_8192C("error! fw_state=0x%x, iftype=%d\n", pmlmepriv->fw_state, rtw_wdev->iftype); + + } + +addkey_end: + if(param) + { + rtw_mfree((u8*)param, param_len); + } + + return ret; + +} + +static int cfg80211_rtw_get_key(struct wiphy *wiphy, struct net_device *ndev, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,1,0)) + int link_id, +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) + u8 key_index, bool pairwise, const u8 *mac_addr, +#else // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) + u8 key_index, const u8 *mac_addr, +#endif // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) + void *cookie, + void (*callback)(void *cookie, + struct key_params*)) +{ +#if 0 + struct iwm_priv *iwm = ndev_to_iwm(ndev); + struct iwm_key *key = &iwm->keys[key_index]; + struct key_params params; + + IWM_DBG_WEXT(iwm, DBG, "Getting key %d\n", key_index); + + memset(¶ms, 0, sizeof(params)); + + params.cipher = key->cipher; + params.key_len = key->key_len; + params.seq_len = key->seq_len; + params.seq = key->seq; + params.key = key->key; + + callback(cookie, ¶ms); + + return key->key_len ? 0 : -ENOENT; +#endif + DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + return 0; +} + +static int cfg80211_rtw_del_key(struct wiphy *wiphy, struct net_device *ndev, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,1,0)) + int link_id, +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) + u8 key_index, bool pairwise, const u8 *mac_addr) +#else // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) + u8 key_index, const u8 *mac_addr) +#endif // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct security_priv *psecuritypriv = &padapter->securitypriv; + + DBG_871X(FUNC_NDEV_FMT" key_index=%d\n", FUNC_NDEV_ARG(ndev), key_index); + + if (key_index == psecuritypriv->dot11PrivacyKeyIndex) + { + //clear the flag of wep default key set. + psecuritypriv->bWepDefaultKeyIdxSet = 0; + } + + return 0; +} + +static int cfg80211_rtw_set_default_key(struct wiphy *wiphy, + struct net_device *ndev, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,1,0)) + int link_id, +#endif + u8 key_index + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) || defined(COMPAT_KERNEL_RELEASE) + , bool unicast, bool multicast + #endif + ) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct security_priv *psecuritypriv = &padapter->securitypriv; + +#define SET_DEF_KEY_PARAM_FMT " key_index=%d" +#define SET_DEF_KEY_PARAM_ARG , key_index +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 38)) || defined(COMPAT_KERNEL_RELEASE) + #define SET_DEF_KEY_PARAM_FMT_2_6_38 ", unicast=%d, multicast=%d" + #define SET_DEF_KEY_PARAM_ARG_2_6_38 , unicast, multicast +#else + #define SET_DEF_KEY_PARAM_FMT_2_6_38 "" + #define SET_DEF_KEY_PARAM_ARG_2_6_38 +#endif + + DBG_871X(FUNC_NDEV_FMT + SET_DEF_KEY_PARAM_FMT + SET_DEF_KEY_PARAM_FMT_2_6_38 + "\n", FUNC_NDEV_ARG(ndev) + SET_DEF_KEY_PARAM_ARG + SET_DEF_KEY_PARAM_ARG_2_6_38 + ); + + if ((key_index < WEP_KEYS) && ((psecuritypriv->dot11PrivacyAlgrthm == _WEP40_) || (psecuritypriv->dot11PrivacyAlgrthm == _WEP104_))) //set wep default key + { + psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled; + + psecuritypriv->dot11PrivacyKeyIndex = key_index; + + psecuritypriv->dot11PrivacyAlgrthm = _WEP40_; + psecuritypriv->dot118021XGrpPrivacy = _WEP40_; + if (psecuritypriv->dot11DefKeylen[key_index] == 13) + { + psecuritypriv->dot11PrivacyAlgrthm = _WEP104_; + psecuritypriv->dot118021XGrpPrivacy = _WEP104_; + } + + psecuritypriv->bWepDefaultKeyIdxSet = 1; //set the flag to represent that wep default key has been set + } + + return 0; + +} +#if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0)) +static int cfg80211_rtw_set_rekey_data(struct wiphy *wiphy, + struct net_device *ndev, + struct cfg80211_gtk_rekey_data *data) +{ + /*int i;*/ + struct sta_info *psta; + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct sta_priv *pstapriv = &padapter->stapriv; + struct security_priv *psecuritypriv = &(padapter->securitypriv); + + psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); + if (psta == NULL) { + DBG_871X("%s, : Obtain Sta_info fail\n", __func__); + return -1; + } + + _rtw_memcpy(psta->kek, data->kek, NL80211_KEK_LEN); + /*printk("\ncfg80211_rtw_set_rekey_data KEK:"); + for(i=0;ikek[i]);*/ + _rtw_memcpy(psta->kck, data->kck, NL80211_KCK_LEN); + /*printk("\ncfg80211_rtw_set_rekey_data KCK:"); + for(i=0;ikck[i]);*/ + _rtw_memcpy(psta->replay_ctr, data->replay_ctr, NL80211_REPLAY_CTR_LEN); + psecuritypriv->binstallKCK_KEK = _TRUE; + /*printk("\nREPLAY_CTR: "); + for(i=0;ireplay_ctr[i]);*/ + + return 0; +} +#endif /*CONFIG_GTK_OL*/ +static int cfg80211_rtw_get_station(struct wiphy *wiphy, + struct net_device *ndev, +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,16,0)) + u8 *mac, +#else + const u8 *mac, +#endif + struct station_info *sinfo) +{ + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct sta_info *psta = NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + + sinfo->filled = 0; + + if (!mac) { + DBG_871X(FUNC_NDEV_FMT" mac==%p\n", FUNC_NDEV_ARG(ndev), mac); + ret = -ENOENT; + goto exit; + } + + psta = rtw_get_stainfo(pstapriv, (u8 *)mac); + if (psta == NULL) { + DBG_8192C("%s, sta_info is null\n", __func__); + ret = -ENOENT; + goto exit; + } + +#ifdef CONFIG_DEBUG_CFG80211 + DBG_871X(FUNC_NDEV_FMT" mac="MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(mac)); +#endif + + //for infra./P2PClient mode + if( check_fwstate(pmlmepriv, WIFI_STATION_STATE) + && check_fwstate(pmlmepriv, _FW_LINKED) + ) + { + struct wlan_network *cur_network = &(pmlmepriv->cur_network); + + if (_rtw_memcmp((u8 *)mac, cur_network->network.MacAddress, ETH_ALEN) == _FALSE) { + DBG_871X("%s, mismatch bssid="MAC_FMT"\n", __func__, MAC_ARG(cur_network->network.MacAddress)); + ret = -ENOENT; + goto exit; + } + + sinfo->filled |= STATION_INFO_SIGNAL; + sinfo->signal = translate_percentage_to_dbm(padapter->recvpriv.signal_strength); + + sinfo->filled |= STATION_INFO_TX_BITRATE; + sinfo->txrate.legacy = rtw_get_cur_max_rate(padapter); + + sinfo->filled |= STATION_INFO_RX_PACKETS; + sinfo->rx_packets = sta_rx_data_pkts(psta); + + sinfo->filled |= STATION_INFO_TX_PACKETS; + sinfo->tx_packets = psta->sta_stats.tx_pkts; + + } + + //for Ad-Hoc/AP mode + if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) + ||check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) + ||check_fwstate(pmlmepriv, WIFI_AP_STATE)) + && check_fwstate(pmlmepriv, _FW_LINKED) + ) + { + //TODO: should acquire station info... + } + +exit: + return ret; +} + +extern int netdev_open(struct net_device *pnetdev); +#ifdef CONFIG_CONCURRENT_MODE +extern int netdev_if2_open(struct net_device *pnetdev); +#endif + +/* +enum nl80211_iftype { + NL80211_IFTYPE_UNSPECIFIED, + NL80211_IFTYPE_ADHOC, //1 + NL80211_IFTYPE_STATION, //2 + NL80211_IFTYPE_AP, //3 + NL80211_IFTYPE_AP_VLAN, + NL80211_IFTYPE_WDS, + NL80211_IFTYPE_MONITOR, //6 + NL80211_IFTYPE_MESH_POINT, + NL80211_IFTYPE_P2P_CLIENT, //8 + NL80211_IFTYPE_P2P_GO, //9 + //keep last + NUM_NL80211_IFTYPES, + NL80211_IFTYPE_MAX = NUM_NL80211_IFTYPES - 1 +}; +*/ +static int cfg80211_rtw_change_iface(struct wiphy *wiphy, + struct net_device *ndev, + enum nl80211_iftype type, +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,12,0)) + u32 *flags, +#endif + struct vif_params *params) +{ + enum nl80211_iftype old_type; + NDIS_802_11_NETWORK_INFRASTRUCTURE networkType; + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct wireless_dev *rtw_wdev = padapter->rtw_wdev; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); +#endif + int ret = 0; + u8 change = _FALSE; + + DBG_871X(FUNC_NDEV_FMT" type=%d\n", FUNC_NDEV_ARG(ndev), type); + + if(adapter_to_dvobj(padapter)->processing_dev_remove == _TRUE) + { + ret= -EPERM; + goto exit; + } + +#ifdef CONFIG_CONCURRENT_MODE + if(padapter->adapter_type == SECONDARY_ADAPTER) + { + DBG_871X(FUNC_NDEV_FMT" call netdev_if2_open\n", FUNC_NDEV_ARG(ndev)); + if(netdev_if2_open(ndev) != 0) { + DBG_871X(FUNC_NDEV_FMT" call netdev_if2_open fail\n", FUNC_NDEV_ARG(ndev)); + ret= -EPERM; + goto exit; + } + } + else if(padapter->adapter_type == PRIMARY_ADAPTER) +#endif //CONFIG_CONCURRENT_MODE + { + DBG_871X(FUNC_NDEV_FMT" call netdev_open\n", FUNC_NDEV_ARG(ndev)); + if(netdev_open(ndev) != 0) { + DBG_871X(FUNC_NDEV_FMT" call netdev_open fail\n", FUNC_NDEV_ARG(ndev)); + ret= -EPERM; + goto exit; + } + } + + if(_FAIL == rtw_pwr_wakeup(padapter)) { + DBG_871X(FUNC_NDEV_FMT" call rtw_pwr_wakeup fail\n", FUNC_NDEV_ARG(ndev)); + ret= -EPERM; + goto exit; + } + + old_type = rtw_wdev->iftype; + DBG_871X(FUNC_NDEV_FMT" old_iftype=%d, new_iftype=%d\n", + FUNC_NDEV_ARG(ndev), old_type, type); + + if(old_type != type) + { + change = _TRUE; + pmlmeext->action_public_rxseq = 0xffff; + pmlmeext->action_public_dialog_token = 0xff; + } + + /* initial default type */ + ndev->type = ARPHRD_ETHER; + + switch (type) { + case NL80211_IFTYPE_ADHOC: + networkType = Ndis802_11IBSS; + break; +#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)) + case NL80211_IFTYPE_P2P_CLIENT: +#endif + case NL80211_IFTYPE_STATION: + networkType = Ndis802_11Infrastructure; + #ifdef CONFIG_P2P + if(pwdinfo->driver_interface == DRIVER_CFG80211 ) + { + if(change && rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) + { + //it means remove GO and change mode from AP(GO) to station(P2P DEVICE) + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); + rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); + + DBG_8192C("%s, role=%d, p2p_state=%d, pre_p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), rtw_p2p_pre_state(pwdinfo)); + } + #if ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) + if (type == NL80211_IFTYPE_P2P_CLIENT) + rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); + else { + /* NL80211_IFTYPE_STATION */ + if (rtw_p2p_role(pwdinfo) == P2P_ROLE_CLIENT) + rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); + } + #endif + } + #endif //CONFIG_P2P + break; +#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)) + case NL80211_IFTYPE_P2P_GO: +#endif + case NL80211_IFTYPE_AP: + networkType = Ndis802_11APMode; + #ifdef CONFIG_P2P + if(pwdinfo->driver_interface == DRIVER_CFG80211 ) + { + if(change && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + { + //it means P2P Group created, we will be GO and change mode from P2P DEVICE to AP(GO) + rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); + } + } + #endif //CONFIG_P2P + break; + case NL80211_IFTYPE_MONITOR: + networkType = Ndis802_11Monitor; +#if 0 + ndev->type = ARPHRD_IEEE80211; /* IEEE 802.11 : 801 */ +#endif + ndev->type = ARPHRD_IEEE80211_RADIOTAP; /* IEEE 802.11 + radiotap header : 803 */ + break; + default: + ret = -EOPNOTSUPP; + goto exit; + } + + rtw_wdev->iftype = type; + + if (rtw_set_802_11_infrastructure_mode(padapter, networkType) ==_FALSE) + { + rtw_wdev->iftype = old_type; + ret = -EPERM; + goto exit; + } + + rtw_setopmode_cmd(padapter, networkType, _TRUE); + +exit: + + DBG_871X(FUNC_NDEV_FMT" ret:%d\n", FUNC_NDEV_ARG(ndev), ret); + return ret; +} + +void rtw_cfg80211_indicate_scan_done(_adapter *adapter, bool aborted) +{ + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter); + _irqL irqL; +#if (KERNEL_VERSION(4, 7, 0) <= LINUX_VERSION_CODE) + struct cfg80211_scan_info info; + + memset(&info, 0, sizeof(info)); + info.aborted = aborted; +#endif + + + + _enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL); + if (pwdev_priv->scan_request != NULL) { + #ifdef CONFIG_DEBUG_CFG80211 + DBG_871X("%s with scan req\n", __FUNCTION__); + #endif + + /* avoid WARN_ON(request != wiphy_to_dev(request->wiphy)->scan_req); */ + if(pwdev_priv->scan_request->wiphy != pwdev_priv->rtw_wdev->wiphy) + { + DBG_8192C("error wiphy compare\n"); + } + else + { +#if (KERNEL_VERSION(4, 7, 0) <= LINUX_VERSION_CODE) + cfg80211_scan_done(pwdev_priv->scan_request, &info); +#else + cfg80211_scan_done(pwdev_priv->scan_request, aborted); +#endif + } + + pwdev_priv->scan_request = NULL; + } else { + #ifdef CONFIG_DEBUG_CFG80211 + DBG_871X("%s without scan req\n", __FUNCTION__); + #endif + } + _exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL); +} + +u32 rtw_cfg80211_wait_scan_req_empty(_adapter *adapter, u32 timeout_ms) +{ + struct rtw_wdev_priv *wdev_priv = adapter_wdev_data(adapter); + u8 empty = _FALSE; + u32 start; + u32 pass_ms; + + start = rtw_get_current_time(); + + while (rtw_get_passing_time_ms(start) <= timeout_ms) { + + if (RTW_CANNOT_RUN(adapter)) + break; + + if (!wdev_priv->scan_request) { + empty = _TRUE; + break; + } + + rtw_msleep_os(10); + } + + pass_ms = rtw_get_passing_time_ms(start); + + if (empty == _FALSE && pass_ms > timeout_ms) + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" pass_ms:%u, timeout\n" + , FUNC_ADPT_ARG(adapter), pass_ms); + + return pass_ms; +} + +void rtw_cfg80211_unlink_bss(_adapter *padapter, struct wlan_network *pnetwork) +{ + struct wireless_dev *pwdev = padapter->rtw_wdev; + struct wiphy *wiphy = pwdev->wiphy; + struct cfg80211_bss *bss = NULL; + WLAN_BSSID_EX select_network = pnetwork->network; + + bss = cfg80211_get_bss(wiphy, NULL/*notify_channel*/, + select_network.MacAddress, select_network.Ssid.Ssid, + select_network.Ssid.SsidLength, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0) + select_network.InfrastructureMode == Ndis802_11Infrastructure?IEEE80211_BSS_TYPE_ESS:IEEE80211_BSS_TYPE_IBSS, + IEEE80211_PRIVACY(select_network.Privacy)); +#else + select_network.InfrastructureMode == Ndis802_11Infrastructure?WLAN_CAPABILITY_ESS:WLAN_CAPABILITY_IBSS, + select_network.InfrastructureMode == Ndis802_11Infrastructure?WLAN_CAPABILITY_ESS:WLAN_CAPABILITY_IBSS); +#endif + + if (bss) { + cfg80211_unlink_bss(wiphy, bss); + DBG_8192C("%s(): cfg80211_unlink %s!! () ",__func__,select_network.Ssid.Ssid ); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 9, 0) + cfg80211_put_bss(padapter->rtw_wdev->wiphy, bss); +#else + cfg80211_put_bss(bss); +#endif + } + return; +} + +void rtw_cfg80211_surveydone_event_callback(_adapter *padapter) +{ + _irqL irqL; + _list *plist, *phead; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + u32 cnt=0; + u32 wait_for_surveydone; + sint wait_status; +#ifdef CONFIG_P2P + struct wifidirect_info* pwdinfo = &padapter->wdinfo; +#endif //CONFIG_P2P + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); + +#ifdef CONFIG_DEBUG_CFG80211 + DBG_8192C("%s\n", __func__); +#endif + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + while(1) + { + if (rtw_end_of_queue_search(phead,plist)== _TRUE) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + + //report network only if the current channel set contains the channel to which this network belongs + if(rtw_ch_set_search_ch(padapter->mlmeextpriv.channel_set, pnetwork->network.Configuration.DSConfig) >= 0 + && rtw_mlme_band_check(padapter, pnetwork->network.Configuration.DSConfig) == _TRUE + && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid)) + ) + { + //ev=translate_scan(padapter, a, pnetwork, ev, stop); + rtw_cfg80211_inform_bss(padapter, pnetwork); + } + /* //check ralink testbed RSN IE length + { + if(_rtw_memcmp(pnetwork->network.Ssid.Ssid, "Ralink_11n_AP",13)) + { + uint ie_len=0; + u8 *p=NULL; + p = rtw_get_ie(pnetwork->network.IEs + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, (pnetwork->network.IELength - _BEACON_IE_OFFSET_)); + DBG_871X("ie_len=%d\n", ie_len); + } + }*/ + plist = get_next(plist); + + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); +} + +static int rtw_cfg80211_set_probe_req_wpsp2pie(_adapter *padapter, char *buf, int len) +{ + int ret = 0; + uint wps_ielen = 0; + u8 *wps_ie; + u32 p2p_ielen = 0; + u8 *p2p_ie; + u32 wfd_ielen = 0; + u8 *wfd_ie; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + +#ifdef CONFIG_DEBUG_CFG80211 + DBG_8192C("%s, ielen=%d\n", __func__, len); +#endif + + if(len>0) + { + if((wps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen))) + { + #ifdef CONFIG_DEBUG_CFG80211 + DBG_8192C("probe_req_wps_ielen=%d\n", wps_ielen); + #endif + + if(pmlmepriv->wps_probe_req_ie) + { + u32 free_len = pmlmepriv->wps_probe_req_ie_len; + pmlmepriv->wps_probe_req_ie_len = 0; + rtw_mfree(pmlmepriv->wps_probe_req_ie, free_len); + pmlmepriv->wps_probe_req_ie = NULL; + } + + pmlmepriv->wps_probe_req_ie = rtw_malloc(wps_ielen); + if ( pmlmepriv->wps_probe_req_ie == NULL) { + DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + return -EINVAL; + + } + _rtw_memcpy(pmlmepriv->wps_probe_req_ie, wps_ie, wps_ielen); + pmlmepriv->wps_probe_req_ie_len = wps_ielen; + } + + //buf += wps_ielen; + //len -= wps_ielen; + + #ifdef CONFIG_P2P + if((p2p_ie=rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen))) + { + struct wifidirect_info *wdinfo = &padapter->wdinfo; + u32 attr_contentlen = 0; + u8 listen_ch_attr[5]; + + #ifdef CONFIG_DEBUG_CFG80211 + DBG_8192C("probe_req_p2p_ielen=%d\n", p2p_ielen); + #endif + + if(pmlmepriv->p2p_probe_req_ie) + { + u32 free_len = pmlmepriv->p2p_probe_req_ie_len; + pmlmepriv->p2p_probe_req_ie_len = 0; + rtw_mfree(pmlmepriv->p2p_probe_req_ie, free_len); + pmlmepriv->p2p_probe_req_ie = NULL; + } + + pmlmepriv->p2p_probe_req_ie = rtw_malloc(p2p_ielen); + if ( pmlmepriv->p2p_probe_req_ie == NULL) { + DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + return -EINVAL; + + } + _rtw_memcpy(pmlmepriv->p2p_probe_req_ie, p2p_ie, p2p_ielen); + pmlmepriv->p2p_probe_req_ie_len = p2p_ielen; + + if(rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_LISTEN_CH, (u8*)listen_ch_attr, (uint*) &attr_contentlen) + && attr_contentlen == 5) + { + if (wdinfo->listen_channel != listen_ch_attr[4]) { + DBG_871X(FUNC_ADPT_FMT" listen channel - country:%c%c%c, class:%u, ch:%u\n", + FUNC_ADPT_ARG(padapter), listen_ch_attr[0], listen_ch_attr[1], listen_ch_attr[2], + listen_ch_attr[3], listen_ch_attr[4]); + wdinfo->listen_channel = listen_ch_attr[4]; + } + } + } + #endif //CONFIG_P2P + + #ifdef CONFIG_WFD + wfd_ie = rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen); + if (wfd_ie) { + #ifdef CONFIG_DEBUG_CFG80211 + DBG_8192C("probe_req_wfd_ielen=%d\n", wfd_ielen); + #endif + + if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_PROBE_REQ_IE, wfd_ie, wfd_ielen) != _SUCCESS) + return -EINVAL; + } + #endif /* CONFIG_WFD */ + } + + return ret; + +} + +static int cfg80211_rtw_scan(struct wiphy *wiphy + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0)) + , struct net_device *ndev + #endif + , struct cfg80211_scan_request *request) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0)) + struct net_device *ndev = wdev_to_ndev(request->wdev); +#endif + int i; + u8 _status = _FALSE; + int ret = 0; + NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; + struct rtw_ieee80211_channel ch[RTW_CHANNEL_SCAN_AMOUNT]; + _irqL irqL; + u8 *wps_ie=NULL; + uint wps_ielen=0; + u8 *p2p_ie=NULL; + uint p2p_ielen=0; + u8 survey_times=3; + u8 survey_times_for_one_ch=6; + struct cfg80211_ssid *ssids = request->ssids; + int social_channel = 0, j = 0; + bool need_indicate_scan_done = _FALSE; + bool ps_denied = _FALSE; + + _adapter *padapter; + struct rtw_wdev_priv *pwdev_priv; + struct mlme_priv *pmlmepriv; +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo; +#endif //CONFIG_P2P +#ifdef CONFIG_CONCURRENT_MODE + PADAPTER pbuddy_adapter = NULL; + struct mlme_priv *pbuddy_mlmepriv = NULL; +#endif //CONFIG_CONCURRENT_MODE + + if (ndev == NULL) { + ret = -EINVAL; + goto exit; + } + + padapter = (_adapter *)rtw_netdev_priv(ndev); + pwdev_priv = adapter_wdev_data(padapter); + pmlmepriv= &padapter->mlmepriv; +#ifdef CONFIG_P2P + pwdinfo= &(padapter->wdinfo); +#endif //CONFIG_P2P + +//#ifdef CONFIG_DEBUG_CFG80211 + DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); +//#endif + +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->pbuddy_adapter) { + pbuddy_adapter = padapter->pbuddy_adapter; + pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv); + } +#endif //CONFIG_CONCURRENT_MODE + +#ifdef CONFIG_MP_INCLUDED +if (padapter->registrypriv.mp_mode == 1) +{ + DBG_871X(FUNC_ADPT_FMT ": MP mode block Scan request\n", FUNC_ADPT_ARG(padapter)); + ret = -EPERM; + goto exit; +} +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->pbuddy_adapter) { + if (padapter->pbuddy_adapter->registrypriv.mp_mode == 1) + { + DBG_871X(FUNC_ADPT_FMT ": MP mode block Scan request\n", FUNC_ADPT_ARG(padapter->pbuddy_adapter)); + ret = -EPERM; + goto exit; + } + } +#endif //CONFIG_CONCURRENT_MODE +#endif + + _enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL); + pwdev_priv->scan_request = request; + _exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL); + + if (adapter_wdev_data(padapter)->block_scan == _TRUE) { + DBG_871X(FUNC_ADPT_FMT" wdev_priv.block_scan is set\n", FUNC_ADPT_ARG(padapter)); + need_indicate_scan_done = _TRUE; + goto check_need_indicate_scan_done; + } + + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + { +#ifdef CONFIG_DEBUG_CFG80211 + DBG_871X("%s under WIFI_AP_STATE\n", __FUNCTION__); +#endif + + if (check_fwstate(pmlmepriv, WIFI_UNDER_WPS|_FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE) + { + DBG_8192C("%s, fwstate=0x%x\n", __func__, pmlmepriv->fw_state); + + if(check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) + { + DBG_8192C("AP mode process WPS \n"); + } + + need_indicate_scan_done = _TRUE; + goto check_need_indicate_scan_done; + } + } + + rtw_ps_deny(padapter, PS_DENY_SCAN); + ps_denied = _TRUE; + if(_FAIL == rtw_pwr_wakeup(padapter)) { + need_indicate_scan_done = _TRUE; + goto check_need_indicate_scan_done; + } + + #ifdef CONFIG_P2P + if( pwdinfo->driver_interface == DRIVER_CFG80211 ) + { + if(ssids->ssid != NULL + && _rtw_memcmp(ssids->ssid, "DIRECT-", 7) + && rtw_get_p2p_ie((u8 *)request->ie, request->ie_len, NULL, NULL) + ) + { + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + { + rtw_p2p_enable(padapter, P2P_ROLE_DEVICE); + adapter_wdev_data(padapter)->p2p_enabled = _TRUE; + } + else + { + rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); + #ifdef CONFIG_DEBUG_CFG80211 + DBG_8192C("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo)); + #endif + } + rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN); + + if(request->n_channels == 3 && + request->channels[0]->hw_value == 1 && + request->channels[1]->hw_value == 6 && + request->channels[2]->hw_value == 11 + ) + { + social_channel = 1; + } + } + } + #endif //CONFIG_P2P + + if(request->ie && request->ie_len>0) + { + rtw_cfg80211_set_probe_req_wpsp2pie(padapter, (u8 *)request->ie, request->ie_len ); + } + + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) { + DBG_8192C("%s, fwstate=0x%x\n", __func__, pmlmepriv->fw_state); + need_indicate_scan_done = _TRUE; + goto check_need_indicate_scan_done; + } else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) { + DBG_8192C("%s, fwstate=0x%x\n", __func__, pmlmepriv->fw_state); + ret = -EBUSY; + goto check_need_indicate_scan_done; + } + + if (pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE) + { +#if 1 // Miracast can't do AP scan + static u32 lastscantime = 0; + u32 passtime; + + passtime = rtw_get_passing_time_ms(lastscantime); + lastscantime = rtw_get_current_time(); + if (passtime > BUSY_TRAFFIC_SCAN_DENY_PERIOD) +#endif + { + DBG_871X("%s: bBusyTraffic == _TRUE\n", __FUNCTION__); + need_indicate_scan_done = _TRUE; + goto check_need_indicate_scan_done; + } + } + + if (rtw_is_scan_deny(padapter)){ + DBG_871X(FUNC_ADPT_FMT ": scan deny\n", FUNC_ADPT_ARG(padapter)); + need_indicate_scan_done = _TRUE; + goto check_need_indicate_scan_done; + } + +#ifdef CONFIG_CONCURRENT_MODE + if(pbuddy_mlmepriv && (pbuddy_mlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE)) + { +#if 1 // Miracast can't do AP scan + static u32 buddylastscantime = 0; + u32 passtime; + + passtime = rtw_get_passing_time_ms(buddylastscantime); + buddylastscantime = rtw_get_current_time(); + if ((passtime > BUSY_TRAFFIC_SCAN_DENY_PERIOD) +//#ifdef CONFIG_P2P +// ||(!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE)) +//#endif //CONFIG_P2P + ) +#endif + { + DBG_871X("%s: bBusyTraffic == _TRUE at buddy_intf\n", __FUNCTION__); + need_indicate_scan_done = _TRUE; + goto check_need_indicate_scan_done; + } + } + + if (check_buddy_fwstate(padapter, _FW_UNDER_LINKING|WIFI_UNDER_WPS) == _TRUE) { + DBG_871X("buddy_intf's mlme state:0x%x\n", pbuddy_mlmepriv->fw_state); + need_indicate_scan_done = _TRUE; + goto check_need_indicate_scan_done; + + } else if (check_buddy_fwstate(padapter, _FW_UNDER_SURVEY)) { + bool scan_via_buddy = _FALSE; + struct rtw_wdev_priv *buddy_wdev_priv = adapter_wdev_data(pbuddy_adapter); + + _enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL); + _enter_critical_bh(&buddy_wdev_priv->scan_req_lock, &irqL); + if (buddy_wdev_priv->scan_request) { + DBG_871X("scan via buddy\n"); + pmlmepriv->scanning_via_buddy_intf = _TRUE; + _enter_critical_bh(&pmlmepriv->lock, &irqL); + set_fwstate(pmlmepriv, _FW_UNDER_SURVEY); + _exit_critical_bh(&pmlmepriv->lock, &irqL); + scan_via_buddy = _TRUE; + } + _exit_critical_bh(&buddy_wdev_priv->scan_req_lock, &irqL); + _exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL); + + if (scan_via_buddy == _FALSE) + need_indicate_scan_done = _TRUE; + + goto check_need_indicate_scan_done; + } +#endif /* CONFIG_CONCURRENT_MODE */ + +#ifdef CONFIG_P2P + if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) + { + rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH); + rtw_free_network_queue(padapter, _TRUE); + + if(social_channel == 0) + rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE); + else + rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_SOCIAL_LAST); + } +#endif //CONFIG_P2P + + + _rtw_memset(ssid, 0, sizeof(NDIS_802_11_SSID)*RTW_SSID_SCAN_AMOUNT); + //parsing request ssids, n_ssids + for (i = 0; i < request->n_ssids && i < RTW_SSID_SCAN_AMOUNT; i++) { + #ifdef CONFIG_DEBUG_CFG80211 + DBG_8192C("ssid=%s, len=%d\n", ssids[i].ssid, ssids[i].ssid_len); + #endif + _rtw_memcpy(ssid[i].Ssid, ssids[i].ssid, ssids[i].ssid_len); + ssid[i].SsidLength = ssids[i].ssid_len; + } + + /* parsing channels, n_channels */ + _rtw_memset(ch, 0, sizeof(struct rtw_ieee80211_channel)*RTW_CHANNEL_SCAN_AMOUNT); + for (i=0;in_channels && ichannels[i])); + #endif + ch[i].hw_value = request->channels[i]->hw_value; + ch[i].flags = request->channels[i]->flags; + } + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + if (request->n_channels == 1) { + for(i=1;in_channels <= 4) { + for(j=request->n_channels-1;j>=0;j--) + for(i=0;in_channels); + } else { + _status = rtw_sitesurvey_cmd(padapter, ssid, RTW_SSID_SCAN_AMOUNT, ch, request->n_channels); + } + _exit_critical_bh(&pmlmepriv->lock, &irqL); + + + if(_status == _FALSE) + { + ret = -1; + } + +check_need_indicate_scan_done: + if (_TRUE == need_indicate_scan_done) + { + rtw_cfg80211_surveydone_event_callback(padapter); + rtw_cfg80211_indicate_scan_done(padapter, _FALSE); + } + +cancel_ps_deny: + if (ps_denied == _TRUE) + rtw_ps_deny_cancel(padapter, PS_DENY_SCAN); + +exit: + return ret; + +} + +static int cfg80211_rtw_set_wiphy_params(struct wiphy *wiphy, u32 changed) +{ +#if 0 + struct iwm_priv *iwm = wiphy_to_iwm(wiphy); + + if (changed & WIPHY_PARAM_RTS_THRESHOLD && + (iwm->conf.rts_threshold != wiphy->rts_threshold)) { + int ret; + + iwm->conf.rts_threshold = wiphy->rts_threshold; + + ret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_CFG_FIX, + CFG_RTS_THRESHOLD, + iwm->conf.rts_threshold); + if (ret < 0) + return ret; + } + + if (changed & WIPHY_PARAM_FRAG_THRESHOLD && + (iwm->conf.frag_threshold != wiphy->frag_threshold)) { + int ret; + + iwm->conf.frag_threshold = wiphy->frag_threshold; + + ret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_FA_CFG_FIX, + CFG_FRAG_THRESHOLD, + iwm->conf.frag_threshold); + if (ret < 0) + return ret; + } +#endif + DBG_8192C("%s\n", __func__); + return 0; +} + + + +static int rtw_cfg80211_set_wpa_version(struct security_priv *psecuritypriv, u32 wpa_version) +{ + DBG_8192C("%s, wpa_version=%d\n", __func__, wpa_version); + + if (!wpa_version) { + psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen; + return 0; + } + + + if (wpa_version & (NL80211_WPA_VERSION_1 | NL80211_WPA_VERSION_2)) + { + psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPAPSK; + } + +/* + if (wpa_version & NL80211_WPA_VERSION_2) + { + psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPA2PSK; + } +*/ + + #ifdef CONFIG_WAPI_SUPPORT + if (wpa_version & NL80211_WAPI_VERSION_1) + { + psecuritypriv->ndisauthtype = Ndis802_11AuthModeWAPI; + } + #endif + + return 0; + +} + +static int rtw_cfg80211_set_auth_type(struct security_priv *psecuritypriv, + enum nl80211_auth_type sme_auth_type) +{ + DBG_8192C("%s, nl80211_auth_type=%d\n", __func__, sme_auth_type); + + + switch (sme_auth_type) { + case NL80211_AUTHTYPE_AUTOMATIC: + + psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Auto; + + break; + case NL80211_AUTHTYPE_OPEN_SYSTEM: + + psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; + + if(psecuritypriv->ndisauthtype>Ndis802_11AuthModeWPA) + psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; + +#ifdef CONFIG_WAPI_SUPPORT + if(psecuritypriv->ndisauthtype == Ndis802_11AuthModeWAPI) + psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI; +#endif + + break; + case NL80211_AUTHTYPE_SHARED_KEY: + + psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Shared; + + psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled; + + + break; + default: + psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; + //return -ENOTSUPP; + } + + return 0; + +} + +static int rtw_cfg80211_set_cipher(struct security_priv *psecuritypriv, u32 cipher, bool ucast) +{ + u32 ndisencryptstatus = Ndis802_11EncryptionDisabled; + + u32 *profile_cipher = ucast ? &psecuritypriv->dot11PrivacyAlgrthm : + &psecuritypriv->dot118021XGrpPrivacy; + + DBG_8192C("%s, ucast=%d, cipher=0x%x\n", __func__, ucast, cipher); + + + if (!cipher) { + *profile_cipher = _NO_PRIVACY_; + psecuritypriv->ndisencryptstatus = ndisencryptstatus; + return 0; + } + + switch (cipher) { + case IW_AUTH_CIPHER_NONE: + *profile_cipher = _NO_PRIVACY_; + ndisencryptstatus = Ndis802_11EncryptionDisabled; +#ifdef CONFIG_WAPI_SUPPORT + if(psecuritypriv->dot11PrivacyAlgrthm ==_SMS4_ ) + { + *profile_cipher = _SMS4_; + } +#endif + break; + case WLAN_CIPHER_SUITE_WEP40: + *profile_cipher = _WEP40_; + ndisencryptstatus = Ndis802_11Encryption1Enabled; + break; + case WLAN_CIPHER_SUITE_WEP104: + *profile_cipher = _WEP104_; + ndisencryptstatus = Ndis802_11Encryption1Enabled; + break; + case WLAN_CIPHER_SUITE_TKIP: + *profile_cipher = _TKIP_; + ndisencryptstatus = Ndis802_11Encryption2Enabled; + break; + case WLAN_CIPHER_SUITE_CCMP: + *profile_cipher = _AES_; + ndisencryptstatus = Ndis802_11Encryption3Enabled; + break; +#ifdef CONFIG_WAPI_SUPPORT + case WLAN_CIPHER_SUITE_SMS4: + *profile_cipher = _SMS4_; + ndisencryptstatus = Ndis802_11_EncrypteionWAPI; + break; +#endif + default: + DBG_8192C("Unsupported cipher: 0x%x\n", cipher); + return -ENOTSUPP; + } + + if(ucast) + { + psecuritypriv->ndisencryptstatus = ndisencryptstatus; + + //if(psecuritypriv->dot11PrivacyAlgrthm >= _AES_) + // psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPA2PSK; + } + + return 0; +} + +static int rtw_cfg80211_set_key_mgt(struct security_priv *psecuritypriv, u32 key_mgt) +{ + DBG_8192C("%s, key_mgt=0x%x\n", __func__, key_mgt); + + if (key_mgt == WLAN_AKM_SUITE_8021X) + //*auth_type = UMAC_AUTH_TYPE_8021X; + psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; + else if (key_mgt == WLAN_AKM_SUITE_PSK) { + psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; + } +#ifdef CONFIG_WAPI_SUPPORT + else if(key_mgt ==WLAN_AKM_SUITE_WAPI_PSK){ + psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI; + } + else if(key_mgt ==WLAN_AKM_SUITE_WAPI_CERT){ + psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI; + } +#endif + + + else { + DBG_8192C("Invalid key mgt: 0x%x\n", key_mgt); + //return -EINVAL; + } + + return 0; +} + +static int rtw_cfg80211_set_wpa_ie(_adapter *padapter, u8 *pie, size_t ielen) +{ + u8 *buf=NULL, *pos=NULL; + u32 left; + int group_cipher = 0, pairwise_cipher = 0; + int ret = 0; + int wpa_ielen=0; + int wpa2_ielen=0; + u8 *pwpa, *pwpa2; + u8 null_addr[]= {0,0,0,0,0,0}; + + if (pie == NULL || !ielen) { + /* Treat this as normal case, but need to clear WIFI_UNDER_WPS */ + _clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS); + goto exit; + } + + if (ielen > MAX_WPA_IE_LEN+MAX_WPS_IE_LEN+MAX_P2P_IE_LEN) { + ret = -EINVAL; + goto exit; + } + + buf = rtw_zmalloc(ielen); + if (buf == NULL){ + ret = -ENOMEM; + goto exit; + } + + _rtw_memcpy(buf, pie , ielen); + + //dump + { + int i; + DBG_8192C("set wpa_ie(length:%zu):\n", ielen); + for(i=0;i0) + { + if(rtw_parse_wpa_ie(pwpa, wpa_ielen+2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) + { + padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_8021X; + padapter->securitypriv.ndisauthtype=Ndis802_11AuthModeWPAPSK; + _rtw_memcpy(padapter->securitypriv.supplicant_ie, &pwpa[0], wpa_ielen+2); + + DBG_8192C("got wpa_ie, wpa_ielen:%u\n", wpa_ielen); + } + } + + pwpa2 = rtw_get_wpa2_ie(buf, &wpa2_ielen, ielen); + if(pwpa2 && wpa2_ielen>0) + { + if(rtw_parse_wpa2_ie(pwpa2, wpa2_ielen+2, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) + { + padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_8021X; + padapter->securitypriv.ndisauthtype=Ndis802_11AuthModeWPA2PSK; + _rtw_memcpy(padapter->securitypriv.supplicant_ie, &pwpa2[0], wpa2_ielen+2); + + DBG_8192C("got wpa2_ie, wpa2_ielen:%u\n", wpa2_ielen); + } + } + + if (group_cipher == 0) + { + group_cipher = WPA_CIPHER_NONE; + } + if (pairwise_cipher == 0) + { + pairwise_cipher = WPA_CIPHER_NONE; + } + + switch(group_cipher) + { + case WPA_CIPHER_NONE: + padapter->securitypriv.dot118021XGrpPrivacy=_NO_PRIVACY_; + padapter->securitypriv.ndisencryptstatus=Ndis802_11EncryptionDisabled; + break; + case WPA_CIPHER_WEP40: + padapter->securitypriv.dot118021XGrpPrivacy=_WEP40_; + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; + break; + case WPA_CIPHER_TKIP: + padapter->securitypriv.dot118021XGrpPrivacy=_TKIP_; + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled; + break; + case WPA_CIPHER_CCMP: + padapter->securitypriv.dot118021XGrpPrivacy=_AES_; + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled; + break; + case WPA_CIPHER_WEP104: + padapter->securitypriv.dot118021XGrpPrivacy=_WEP104_; + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; + break; + } + + switch(pairwise_cipher) + { + case WPA_CIPHER_NONE: + padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_; + padapter->securitypriv.ndisencryptstatus=Ndis802_11EncryptionDisabled; + break; + case WPA_CIPHER_WEP40: + padapter->securitypriv.dot11PrivacyAlgrthm=_WEP40_; + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; + break; + case WPA_CIPHER_TKIP: + padapter->securitypriv.dot11PrivacyAlgrthm=_TKIP_; + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled; + break; + case WPA_CIPHER_CCMP: + padapter->securitypriv.dot11PrivacyAlgrthm=_AES_; + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled; + break; + case WPA_CIPHER_WEP104: + padapter->securitypriv.dot11PrivacyAlgrthm=_WEP104_; + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; + break; + } + + {/* handle wps_ie */ + uint wps_ielen; + u8 *wps_ie; + + wps_ie = rtw_get_wps_ie(buf, ielen, NULL, &wps_ielen); + if (wps_ie && wps_ielen > 0) { + DBG_8192C("got wps_ie, wps_ielen:%u\n", wps_ielen); + padapter->securitypriv.wps_ie_len = wps_ielensecuritypriv.wps_ie, wps_ie, padapter->securitypriv.wps_ie_len); + set_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS); + } else { + _clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS); + } + } + + #ifdef CONFIG_P2P + {//check p2p_ie for assoc req; + uint p2p_ielen=0; + u8 *p2p_ie; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + if((p2p_ie=rtw_get_p2p_ie(buf, ielen, NULL, &p2p_ielen))) + { + #ifdef CONFIG_DEBUG_CFG80211 + DBG_8192C("%s p2p_assoc_req_ielen=%d\n", __FUNCTION__, p2p_ielen); + #endif + + if(pmlmepriv->p2p_assoc_req_ie) + { + u32 free_len = pmlmepriv->p2p_assoc_req_ie_len; + pmlmepriv->p2p_assoc_req_ie_len = 0; + rtw_mfree(pmlmepriv->p2p_assoc_req_ie, free_len); + pmlmepriv->p2p_assoc_req_ie = NULL; + } + + pmlmepriv->p2p_assoc_req_ie = rtw_malloc(p2p_ielen); + if ( pmlmepriv->p2p_assoc_req_ie == NULL) { + DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + goto exit; + } + _rtw_memcpy(pmlmepriv->p2p_assoc_req_ie, p2p_ie, p2p_ielen); + pmlmepriv->p2p_assoc_req_ie_len = p2p_ielen; + } + } + #endif //CONFIG_P2P + + #ifdef CONFIG_WFD + { + uint wfd_ielen=0; + u8 *wfd_ie; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + wfd_ie = rtw_get_wfd_ie(buf, ielen, NULL, &wfd_ielen); + if (wfd_ie) { + #ifdef CONFIG_DEBUG_CFG80211 + DBG_8192C("%s wfd_assoc_req_ielen=%d\n", __FUNCTION__, wfd_ielen); + #endif + + if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_ASSOC_REQ_IE, wfd_ie, wfd_ielen) != _SUCCESS) + goto exit; + } + } + #endif /* CONFIG_WFD */ + + //TKIP and AES disallow multicast packets until installing group key + if(padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_ + || padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_WTMIC_ + || padapter->securitypriv.dot11PrivacyAlgrthm == _AES_) + //WPS open need to enable multicast + //|| check_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS) == _TRUE) + rtw_hal_set_hwreg(padapter, HW_VAR_OFF_RCR_AM, null_addr); + + RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, + ("rtw_set_wpa_ie: pairwise_cipher=0x%08x padapter->securitypriv.ndisencryptstatus=%d padapter->securitypriv.ndisauthtype=%d\n", + pairwise_cipher, padapter->securitypriv.ndisencryptstatus, padapter->securitypriv.ndisauthtype)); + +exit: + if (buf) + rtw_mfree(buf, ielen); + if (ret) + _clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS); + return ret; +} + +static int cfg80211_rtw_join_ibss(struct wiphy *wiphy, struct net_device *ndev, + struct cfg80211_ibss_params *params) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + NDIS_802_11_SSID ndis_ssid; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network)); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) + struct cfg80211_chan_def *pch_def; +#endif + struct ieee80211_channel *pch; + int ret=0; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) + pch_def = (struct cfg80211_chan_def *)(¶ms->chandef); + pch = (struct ieee80211_channel *) pch_def->chan; +#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31)) + pch = (struct ieee80211_channel *)(params->channel); +#endif + + if(_FAIL == rtw_pwr_wakeup(padapter)) { + ret= -EPERM; + goto exit; + } + + if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + ret = -EPERM; + goto exit; + } + +#ifdef CONFIG_CONCURRENT_MODE + if (check_buddy_fwstate(padapter, _FW_UNDER_LINKING) == _TRUE) { + DBG_8192C("%s, but buddy_intf is under linking\n", __FUNCTION__); + ret = -EINVAL; + goto exit; + } + if (check_buddy_fwstate(padapter, _FW_UNDER_SURVEY) == _TRUE) { + rtw_scan_abort(padapter->pbuddy_adapter); + } +#endif //CONFIG_CONCURRENT_MODE + + if (!params->ssid || !params->ssid_len) + { + ret = -EINVAL; + goto exit; + } + + if (params->ssid_len > IW_ESSID_MAX_SIZE){ + + ret= -E2BIG; + goto exit; + } + + _rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID)); + ndis_ssid.SsidLength = params->ssid_len; + _rtw_memcpy(ndis_ssid.Ssid, (u8 *)params->ssid, params->ssid_len); + + //DBG_8192C("ssid=%s, len=%zu\n", ndis_ssid.Ssid, params->ssid_len); + + psecuritypriv->ndisencryptstatus = Ndis802_11EncryptionDisabled; + psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_; + psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; + psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; //open system + psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen; + + ret = rtw_cfg80211_set_auth_type(psecuritypriv, NL80211_AUTHTYPE_OPEN_SYSTEM); + rtw_set_802_11_authentication_mode(padapter, psecuritypriv->ndisauthtype); + + DBG_871X("%s: center_freq = %d\n", __func__, pch->center_freq); + pmlmeext->cur_channel = rtw_freq2ch(pch->center_freq); + + if (rtw_set_802_11_ssid(padapter, &ndis_ssid) == _FALSE) + { + ret = -1; + goto exit; + } + +exit: + return ret; +} + +static int cfg80211_rtw_leave_ibss(struct wiphy *wiphy, struct net_device *ndev) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct wireless_dev *rtw_wdev = padapter->rtw_wdev; + enum nl80211_iftype old_type; + int ret = 0; + + DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + + #ifdef SUPPLICANT_RTK_VERSION_LOWER_THAN_JB42 + padapter->mlmepriv.not_indic_disco = _TRUE; + #endif + + old_type = rtw_wdev->iftype; + + rtw_set_to_roam(padapter, 0); + + if(check_fwstate(&padapter->mlmepriv, _FW_LINKED)) + { + rtw_scan_abort(padapter); + LeaveAllPowerSaveMode(padapter); + + rtw_wdev->iftype = NL80211_IFTYPE_STATION; + + if (rtw_set_802_11_infrastructure_mode(padapter, Ndis802_11Infrastructure) ==_FALSE) + { + rtw_wdev->iftype = old_type; + ret = -EPERM; + goto leave_ibss; + } + rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure,_TRUE); + } + +leave_ibss: + #ifdef SUPPLICANT_RTK_VERSION_LOWER_THAN_JB42 + padapter->mlmepriv.not_indic_disco = _FALSE; + #endif + + return 0; +} + +static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *ndev, + struct cfg80211_connect_params *sme) +{ + int ret=0; + _irqL irqL; + _list *phead; + struct wlan_network *pnetwork = NULL; + NDIS_802_11_AUTHENTICATION_MODE authmode; + NDIS_802_11_SSID ndis_ssid; + u8 *dst_ssid, *src_ssid; + u8 *dst_bssid, *src_bssid; + //u8 matched_by_bssid=_FALSE; + //u8 matched_by_ssid=_FALSE; + u8 matched=_FALSE; + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + _queue *queue = &pmlmepriv->scanned_queue; + + #ifdef SUPPLICANT_RTK_VERSION_LOWER_THAN_JB42 + padapter->mlmepriv.not_indic_disco = _TRUE; + #endif + + DBG_871X("=>"FUNC_NDEV_FMT" - Start to Connection\n", FUNC_NDEV_ARG(ndev)); + DBG_871X("privacy=%d, key=%p, key_len=%d, key_idx=%d, auth_type=%d\n", + sme->privacy, sme->key, sme->key_len, sme->key_idx, sme->auth_type); + + + if(adapter_wdev_data(padapter)->block == _TRUE) + { + ret = -EBUSY; + DBG_871X("%s wdev_priv.block is set\n", __FUNCTION__); + goto exit; + } + +#ifdef CONFIG_PLATFORM_MSTAR_SCAN_BEFORE_CONNECT + printk("MStar Android!\n"); + if(adapter_wdev_data(padapter)->bandroid_scan == _FALSE) + { +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) +#endif //CONFIG_P2P + { + ret = -EBUSY; + printk("Android hasn't attached yet!\n"); + goto exit; + } + } +#endif + + rtw_ps_deny(padapter, PS_DENY_JOIN); + if(_FAIL == rtw_pwr_wakeup(padapter)) { + ret= -EPERM; + goto exit; + } + + if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + ret = -EPERM; + goto exit; + } + +#ifdef CONFIG_CONCURRENT_MODE + if (check_buddy_fwstate(padapter, _FW_UNDER_LINKING) == _TRUE) { + DBG_8192C("%s, but buddy_intf is under linking\n", __FUNCTION__); + ret = -EINVAL; + goto exit; + } + if (check_buddy_fwstate(padapter, _FW_UNDER_SURVEY) == _TRUE) { + rtw_scan_abort(padapter->pbuddy_adapter); + } +#endif + + if (!sme->ssid || !sme->ssid_len) + { + ret = -EINVAL; + goto exit; + } + + if (sme->ssid_len > IW_ESSID_MAX_SIZE){ + + ret= -E2BIG; + goto exit; + } + + _rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID)); + ndis_ssid.SsidLength = sme->ssid_len; + _rtw_memcpy(ndis_ssid.Ssid, (u8 *)sme->ssid, sme->ssid_len); + + DBG_8192C("ssid=%s, len=%zu\n", ndis_ssid.Ssid, sme->ssid_len); + + + if (sme->bssid) + DBG_8192C("bssid="MAC_FMT"\n", MAC_ARG(sme->bssid)); + + + if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) { + ret = -EBUSY; + DBG_8192C("%s, fw_state=0x%x, goto exit\n", __FUNCTION__, pmlmepriv->fw_state); + goto exit; + } + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) { + rtw_scan_abort(padapter); + } + + psecuritypriv->ndisencryptstatus = Ndis802_11EncryptionDisabled; + psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_; + psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; + psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; //open system + psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen; + +#ifdef CONFIG_WAPI_SUPPORT + padapter->wapiInfo.bWapiEnable = false; +#endif + + ret = rtw_cfg80211_set_wpa_version(psecuritypriv, sme->crypto.wpa_versions); + if (ret < 0) + goto exit; + +#ifdef CONFIG_WAPI_SUPPORT + if(sme->crypto.wpa_versions & NL80211_WAPI_VERSION_1) + { + padapter->wapiInfo.bWapiEnable = true; + padapter->wapiInfo.extra_prefix_len = WAPI_EXT_LEN; + padapter->wapiInfo.extra_postfix_len = SMS4_MIC_LEN; + } +#endif + + ret = rtw_cfg80211_set_auth_type(psecuritypriv, sme->auth_type); + +#ifdef CONFIG_WAPI_SUPPORT + if(psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_WAPI) + padapter->mlmeextpriv.mlmext_info.auth_algo = psecuritypriv->dot11AuthAlgrthm; +#endif + + + if (ret < 0) + goto exit; + + DBG_8192C("%s, ie_len=%zu\n", __func__, sme->ie_len); + + ret = rtw_cfg80211_set_wpa_ie(padapter, (u8 *)sme->ie, sme->ie_len); + if (ret < 0) + goto exit; + + if (sme->crypto.n_ciphers_pairwise) { + ret = rtw_cfg80211_set_cipher(psecuritypriv, sme->crypto.ciphers_pairwise[0], _TRUE); + if (ret < 0) + goto exit; + } + + //For WEP Shared auth + if (sme->key_len > 0 && sme->key) + { + u32 wep_key_idx, wep_key_len,wep_total_len; + NDIS_802_11_WEP *pwep = NULL; + DBG_871X("%s(): Shared/Auto WEP\n",__FUNCTION__); + + wep_key_idx = sme->key_idx; + wep_key_len = sme->key_len; + + if (sme->key_idx > WEP_KEYS) { + ret = -EINVAL; + goto exit; + } + + if (wep_key_len > 0) + { + wep_key_len = wep_key_len <= 5 ? 5 : 13; + wep_total_len = wep_key_len + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial); + pwep =(NDIS_802_11_WEP *) rtw_malloc(wep_total_len); + if(pwep == NULL){ + DBG_871X(" wpa_set_encryption: pwep allocate fail !!!\n"); + ret = -ENOMEM; + goto exit; + } + + _rtw_memset(pwep, 0, wep_total_len); + + pwep->KeyLength = wep_key_len; + pwep->Length = wep_total_len; + + if(wep_key_len==13) + { + padapter->securitypriv.dot11PrivacyAlgrthm=_WEP104_; + padapter->securitypriv.dot118021XGrpPrivacy=_WEP104_; + } + } + else { + ret = -EINVAL; + goto exit; + } + + pwep->KeyIndex = wep_key_idx; + pwep->KeyIndex |= 0x80000000; + + _rtw_memcpy(pwep->KeyMaterial, (void *)sme->key, pwep->KeyLength); + + if(rtw_set_802_11_add_wep(padapter, pwep) == (u8)_FAIL) + { + ret = -EOPNOTSUPP ; + } + + if (pwep) { + rtw_mfree((u8 *)pwep,wep_total_len); + } + + if(ret < 0) + goto exit; + } + + ret = rtw_cfg80211_set_cipher(psecuritypriv, sme->crypto.cipher_group, _FALSE); + if (ret < 0) + return ret; + + if (sme->crypto.n_akm_suites) { + ret = rtw_cfg80211_set_key_mgt(psecuritypriv, sme->crypto.akm_suites[0]); + if (ret < 0) + goto exit; + } + +#ifdef CONFIG_WAPI_SUPPORT + if(sme->crypto.akm_suites[0] ==WLAN_AKM_SUITE_WAPI_PSK){ + padapter->wapiInfo.bWapiPSK = true; + } + else if(sme->crypto.akm_suites[0] ==WLAN_AKM_SUITE_WAPI_CERT){ + padapter->wapiInfo.bWapiPSK = false; + } +#endif + + authmode = psecuritypriv->ndisauthtype; + rtw_set_802_11_authentication_mode(padapter, authmode); + + //rtw_set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); + + if (rtw_set_802_11_connect(padapter, (u8 *)sme->bssid, &ndis_ssid) == _FALSE) { + ret = -1; + goto exit; + } + + DBG_8192C("set ssid:dot11AuthAlgrthm=%d, dot11PrivacyAlgrthm=%d, dot118021XGrpPrivacy=%d\n", psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm, psecuritypriv->dot118021XGrpPrivacy); + +exit: + + rtw_ps_deny_cancel(padapter, PS_DENY_JOIN); + + DBG_8192C("<=%s, ret %d\n",__FUNCTION__, ret); + + #ifdef SUPPLICANT_RTK_VERSION_LOWER_THAN_JB42 + padapter->mlmepriv.not_indic_disco = _FALSE; + #endif + + return ret; +} + +static int cfg80211_rtw_disconnect(struct wiphy *wiphy, struct net_device *ndev, + u16 reason_code) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + + DBG_871X(FUNC_NDEV_FMT" - Start to Disconnect\n", FUNC_NDEV_ARG(ndev)); + + #ifdef SUPPLICANT_RTK_VERSION_LOWER_THAN_JB42 + padapter->mlmepriv.not_indic_disco = _TRUE; + #endif + + rtw_set_to_roam(padapter, 0); + + //if(check_fwstate(&padapter->mlmepriv, _FW_LINKED)) + { + rtw_scan_abort(padapter); + LeaveAllPowerSaveMode(padapter); + rtw_disassoc_cmd(padapter, 500, _FALSE); + rtw_sta_mstatus_report(padapter); + + DBG_871X("%s...call rtw_indicate_disconnect\n", __func__); + + rtw_free_assoc_resources(padapter, 1); + rtw_indicate_disconnect(padapter, 0, _TRUE); + rtw_pwr_wakeup(padapter); + } + + #ifdef SUPPLICANT_RTK_VERSION_LOWER_THAN_JB42 + padapter->mlmepriv.not_indic_disco = _FALSE; + #endif + + DBG_871X(FUNC_NDEV_FMT" return 0\n", FUNC_NDEV_ARG(ndev)); + return 0; +} + +static int cfg80211_rtw_set_txpower(struct wiphy *wiphy, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0)) + struct wireless_dev *wdev, +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36)) || defined(COMPAT_KERNEL_RELEASE) + enum nl80211_tx_power_setting type, int mbm) +#else + enum tx_power_setting type, int dbm) +#endif +{ +#if 0 + struct iwm_priv *iwm = wiphy_to_iwm(wiphy); + int ret; + + switch (type) { + case NL80211_TX_POWER_AUTOMATIC: + return 0; + case NL80211_TX_POWER_FIXED: + if (mbm < 0 || (mbm % 100)) + return -EOPNOTSUPP; + + if (!test_bit(IWM_STATUS_READY, &iwm->status)) + return 0; + + ret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_CFG_FIX, + CFG_TX_PWR_LIMIT_USR, + MBM_TO_DBM(mbm) * 2); + if (ret < 0) + return ret; + + return iwm_tx_power_trigger(iwm); + default: + IWM_ERR(iwm, "Unsupported power type: %d\n", type); + return -EOPNOTSUPP; + } +#endif + DBG_8192C("%s\n", __func__); + return 0; +} + +static int cfg80211_rtw_get_txpower(struct wiphy *wiphy, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0)) + struct wireless_dev *wdev, +#endif + int *dbm) +{ + DBG_8192C("%s\n", __func__); + + *dbm = (12); + + return 0; +} + +inline bool rtw_cfg80211_pwr_mgmt(_adapter *adapter) +{ + struct rtw_wdev_priv *rtw_wdev_priv = adapter_wdev_data(adapter); + return rtw_wdev_priv->power_mgmt; +} + +static int cfg80211_rtw_set_power_mgmt(struct wiphy *wiphy, + struct net_device *ndev, + bool enabled, int timeout) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct rtw_wdev_priv *rtw_wdev_priv = adapter_wdev_data(padapter); + + DBG_871X(FUNC_NDEV_FMT" enabled:%u, timeout:%d\n", FUNC_NDEV_ARG(ndev), + enabled, timeout); + + rtw_wdev_priv->power_mgmt = enabled; + + #ifdef CONFIG_LPS + if (!enabled) + rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE_CFG80211_PWRMGMT, 1); + #endif + + return 0; +} + +static int cfg80211_rtw_set_pmksa(struct wiphy *wiphy, + struct net_device *ndev, + struct cfg80211_pmksa *pmksa) +{ + u8 index,blInserted = _FALSE; + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct mlme_priv *mlme = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + u8 strZeroMacAddress[ ETH_ALEN ] = { 0x00 }; + + DBG_871X(FUNC_NDEV_FMT" "MAC_FMT" "KEY_FMT"\n", FUNC_NDEV_ARG(ndev) + , MAC_ARG(pmksa->bssid), KEY_ARG(pmksa->pmkid)); + + if ( _rtw_memcmp((u8 *)pmksa->bssid, strZeroMacAddress, ETH_ALEN ) == _TRUE ) + { + return -EINVAL; + } + + if (check_fwstate(mlme, _FW_LINKED) == _FALSE) { + DBG_871X(FUNC_NDEV_FMT" not set pmksa cause not in linked state\n", FUNC_NDEV_ARG(ndev)); + return -EINVAL; + } + + blInserted = _FALSE; + + //overwrite PMKID + for(index=0 ; indexPMKIDList[index].Bssid, (u8 *)pmksa->bssid, ETH_ALEN) ==_TRUE ) + { // BSSID is matched, the same AP => rewrite with new PMKID. + DBG_871X(FUNC_NDEV_FMT" BSSID exists in the PMKList.\n", FUNC_NDEV_ARG(ndev)); + + _rtw_memcpy( psecuritypriv->PMKIDList[index].PMKID, (u8 *)pmksa->pmkid, WLAN_PMKID_LEN); + psecuritypriv->PMKIDList[index].bUsed = _TRUE; + psecuritypriv->PMKIDIndex = index+1; + blInserted = _TRUE; + break; + } + } + + if(!blInserted) + { + // Find a new entry + DBG_871X(FUNC_NDEV_FMT" Use the new entry index = %d for this PMKID.\n", + FUNC_NDEV_ARG(ndev), psecuritypriv->PMKIDIndex ); + + _rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].Bssid, (u8 *)pmksa->bssid, ETH_ALEN); + _rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].PMKID, (u8 *)pmksa->pmkid, WLAN_PMKID_LEN); + + psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].bUsed = _TRUE; + psecuritypriv->PMKIDIndex++ ; + if(psecuritypriv->PMKIDIndex==16) + { + psecuritypriv->PMKIDIndex =0; + } + } + + return 0; +} + +static int cfg80211_rtw_del_pmksa(struct wiphy *wiphy, + struct net_device *ndev, + struct cfg80211_pmksa *pmksa) +{ + u8 index, bMatched = _FALSE; + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct security_priv *psecuritypriv = &padapter->securitypriv; + + DBG_871X(FUNC_NDEV_FMT" "MAC_FMT" "KEY_FMT"\n", FUNC_NDEV_ARG(ndev) + , MAC_ARG(pmksa->bssid), KEY_ARG(pmksa->pmkid)); + + for(index=0 ; indexPMKIDList[index].Bssid, (u8 *)pmksa->bssid, ETH_ALEN) ==_TRUE ) + { // BSSID is matched, the same AP => Remove this PMKID information and reset it. + _rtw_memset(psecuritypriv->PMKIDList[index].Bssid, 0x00, ETH_ALEN ); + _rtw_memset(psecuritypriv->PMKIDList[index].PMKID, 0x00, WLAN_PMKID_LEN ); + psecuritypriv->PMKIDList[index].bUsed = _FALSE; + bMatched = _TRUE; + DBG_871X(FUNC_NDEV_FMT" clear id:%hhu\n", FUNC_NDEV_ARG(ndev), index); + break; + } + } + + if(_FALSE == bMatched) + { + DBG_871X(FUNC_NDEV_FMT" do not have matched BSSID\n" + , FUNC_NDEV_ARG(ndev)); + return -EINVAL; + } + + return 0; +} + +static int cfg80211_rtw_flush_pmksa(struct wiphy *wiphy, + struct net_device *ndev) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct security_priv *psecuritypriv = &padapter->securitypriv; + + DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + + _rtw_memset( &psecuritypriv->PMKIDList[ 0 ], 0x00, sizeof( RT_PMKID_LIST ) * NUM_PMKID_CACHE ); + psecuritypriv->PMKIDIndex = 0; + + return 0; +} + +#ifdef CONFIG_AP_MODE +void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len) +{ + s32 freq; + int channel; + struct wireless_dev *pwdev = padapter->rtw_wdev; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct net_device *ndev = padapter->pnetdev; + + DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + +#if defined(RTW_USE_CFG80211_STA_EVENT) || defined(COMPAT_KERNEL_RELEASE) + { + struct station_info sinfo; + u8 ie_offset; + if (GetFrameSubType(pmgmt_frame) == WIFI_ASSOCREQ) + ie_offset = _ASOCREQ_IE_OFFSET_; + else // WIFI_REASSOCREQ + ie_offset = _REASOCREQ_IE_OFFSET_; + + memset(&sinfo, 0, sizeof(sinfo)); + sinfo.filled = STATION_INFO_ASSOC_REQ_IES; + sinfo.assoc_req_ies = pmgmt_frame + WLAN_HDR_A3_LEN + ie_offset; + sinfo.assoc_req_ies_len = frame_len - WLAN_HDR_A3_LEN - ie_offset; + cfg80211_new_sta(ndev, GetAddr2Ptr(pmgmt_frame), &sinfo, GFP_ATOMIC); + } +#else /* defined(RTW_USE_CFG80211_STA_EVENT) */ + channel = pmlmeext->cur_channel; + freq = rtw_ch2freq(channel); + + #ifdef COMPAT_KERNEL_RELEASE + rtw_cfg80211_rx_mgmt(padapter, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC); + #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) + rtw_cfg80211_rx_mgmt(padapter, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC); + #else //COMPAT_KERNEL_RELEASE + { + //to avoid WARN_ON(wdev->iftype != NL80211_IFTYPE_STATION) when calling cfg80211_send_rx_assoc() + #ifndef CONFIG_PLATFORM_MSTAR + pwdev->iftype = NL80211_IFTYPE_STATION; + #endif //CONFIG_PLATFORM_MSTAR + DBG_8192C("iftype=%d before call cfg80211_send_rx_assoc()\n", pwdev->iftype); + rtw_cfg80211_send_rx_assoc(padapter, NULL, pmgmt_frame, frame_len); + DBG_8192C("iftype=%d after call cfg80211_send_rx_assoc()\n", pwdev->iftype); + pwdev->iftype = NL80211_IFTYPE_AP; + //cfg80211_rx_action(padapter->pnetdev, freq, pmgmt_frame, frame_len, GFP_ATOMIC); + } + #endif //COMPAT_KERNEL_RELEASE +#endif /* defined(RTW_USE_CFG80211_STA_EVENT) */ + +} + +void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, unsigned char *da, unsigned short reason) +{ + s32 freq; + int channel; + u8 *pmgmt_frame; + uint frame_len; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + u8 mgmt_buf[128] = {0}; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct net_device *ndev = padapter->pnetdev; + + DBG_871X(FUNC_ADPT_FMT"\n", FUNC_ADPT_ARG(padapter)); + +#if defined(RTW_USE_CFG80211_STA_EVENT) || defined(COMPAT_KERNEL_RELEASE) + cfg80211_del_sta(ndev, da, GFP_ATOMIC); +#else /* defined(RTW_USE_CFG80211_STA_EVENT) */ + channel = pmlmeext->cur_channel; + freq = rtw_ch2freq(channel); + + pmgmt_frame = mgmt_buf; + pwlanhdr = (struct rtw_ieee80211_hdr *)pmgmt_frame; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, da, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(pmgmt_frame, WIFI_DEAUTH); + + pmgmt_frame += sizeof(struct rtw_ieee80211_hdr_3addr); + frame_len = sizeof(struct rtw_ieee80211_hdr_3addr); + + reason = cpu_to_le16(reason); + pmgmt_frame = rtw_set_fixed_ie(pmgmt_frame, _RSON_CODE_ , (unsigned char *)&reason, &frame_len); + + #ifdef COMPAT_KERNEL_RELEASE + rtw_cfg80211_rx_mgmt(padapter, freq, 0, mgmt_buf, frame_len, GFP_ATOMIC); + #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) + rtw_cfg80211_rx_mgmt(padapter, freq, 0, mgmt_buf, frame_len, GFP_ATOMIC); + #else //COMPAT_KERNEL_RELEASE + cfg80211_send_disassoc(padapter->pnetdev, mgmt_buf, frame_len); + //cfg80211_rx_action(padapter->pnetdev, freq, mgmt_buf, frame_len, GFP_ATOMIC); + #endif //COMPAT_KERNEL_RELEASE +#endif /* defined(RTW_USE_CFG80211_STA_EVENT) */ +} + +static int rtw_cfg80211_monitor_if_open(struct net_device *ndev) +{ + int ret = 0; + + DBG_8192C("%s\n", __func__); + + return ret; +} + +static int rtw_cfg80211_monitor_if_close(struct net_device *ndev) +{ + int ret = 0; + + DBG_8192C("%s\n", __func__); + + return ret; +} + +static int rtw_cfg80211_monitor_if_xmit_entry(struct sk_buff *skb, struct net_device *ndev) +{ + int ret = 0; + int rtap_len; + int qos_len = 0; + int dot11_hdr_len = 24; + int snap_len = 6; + unsigned char *pdata; + u16 frame_ctl; + unsigned char src_mac_addr[6]; + unsigned char dst_mac_addr[6]; + struct rtw_ieee80211_hdr *dot11_hdr; + struct ieee80211_radiotap_header *rtap_hdr; + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + + DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + + if (skb) + rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, skb->truesize); + + if (unlikely(skb->len < sizeof(struct ieee80211_radiotap_header))) + goto fail; + + rtap_hdr = (struct ieee80211_radiotap_header *)skb->data; + if (unlikely(rtap_hdr->it_version)) + goto fail; + + rtap_len = ieee80211_get_radiotap_len(skb->data); + if (unlikely(skb->len < rtap_len)) + goto fail; + + if(rtap_len != 14) + { + DBG_8192C("radiotap len (should be 14): %d\n", rtap_len); + goto fail; + } + + /* Skip the ratio tap header */ + skb_pull(skb, rtap_len); + + dot11_hdr = (struct rtw_ieee80211_hdr *)skb->data; + frame_ctl = le16_to_cpu(dot11_hdr->frame_ctl); + /* Check if the QoS bit is set */ + if ((frame_ctl & RTW_IEEE80211_FCTL_FTYPE) == RTW_IEEE80211_FTYPE_DATA) { + /* Check if this ia a Wireless Distribution System (WDS) frame + * which has 4 MAC addresses + */ + if (dot11_hdr->frame_ctl & 0x0080) + qos_len = 2; + if ((dot11_hdr->frame_ctl & 0x0300) == 0x0300) + dot11_hdr_len += 6; + + memcpy(dst_mac_addr, dot11_hdr->addr1, sizeof(dst_mac_addr)); + memcpy(src_mac_addr, dot11_hdr->addr2, sizeof(src_mac_addr)); + + /* Skip the 802.11 header, QoS (if any) and SNAP, but leave spaces for + * for two MAC addresses + */ + skb_pull(skb, dot11_hdr_len + qos_len + snap_len - sizeof(src_mac_addr) * 2); + pdata = (unsigned char*)skb->data; + memcpy(pdata, dst_mac_addr, sizeof(dst_mac_addr)); + memcpy(pdata + sizeof(dst_mac_addr), src_mac_addr, sizeof(src_mac_addr)); + + DBG_8192C("should be eapol packet\n"); + + /* Use the real net device to transmit the packet */ + ret = _rtw_xmit_entry(skb, padapter->pnetdev); + + return ret; + + } + else if ((frame_ctl & (RTW_IEEE80211_FCTL_FTYPE|RTW_IEEE80211_FCTL_STYPE)) + == (RTW_IEEE80211_FTYPE_MGMT|RTW_IEEE80211_STYPE_ACTION) + ) + { + //only for action frames + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + //u8 category, action, OUI_Subtype, dialogToken=0; + //unsigned char *frame_body; + struct rtw_ieee80211_hdr *pwlanhdr; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + u8 *buf = skb->data; + u32 len = skb->len; + u8 category, action; + int type = -1; + + if (rtw_action_frame_parse(buf, len, &category, &action) == _FALSE) { + DBG_8192C(FUNC_NDEV_FMT" frame_control:0x%x\n", FUNC_NDEV_ARG(ndev), + le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)buf)->frame_ctl)); + goto fail; + } + + DBG_8192C("RTW_Tx:da="MAC_FMT" via "FUNC_NDEV_FMT"\n", + MAC_ARG(GetAddr1Ptr(buf)), FUNC_NDEV_ARG(ndev)); + #ifdef CONFIG_P2P + if((type = rtw_p2p_check_frames(padapter, buf, len, _TRUE)) >= 0) + goto dump; + #endif + if (category == RTW_WLAN_CATEGORY_PUBLIC) + DBG_871X("RTW_Tx:%s\n", action_public_str(action)); + else + DBG_871X("RTW_Tx:category(%u), action(%u)\n", category, action); + +dump: + //starting alloc mgmt frame to dump it + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + { + goto fail; + } + + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + pattrib->retry_ctrl = _FALSE; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + + _rtw_memcpy(pframe, (void*)buf, len); + pattrib->pktlen = len; + +#ifdef CONFIG_P2P + if (type >= 0) + rtw_xframe_chk_wfd_ie(pmgntframe); +#endif /* CONFIG_P2P */ + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + //update seq number + pmlmeext->mgnt_seq = GetSequence(pwlanhdr); + pattrib->seqnum = pmlmeext->mgnt_seq; + pmlmeext->mgnt_seq++; + + + pattrib->last_txcmdsz = pattrib->pktlen; + + dump_mgntframe(padapter, pmgntframe); + + } + else + { + DBG_8192C("frame_ctl=0x%x\n", frame_ctl & (RTW_IEEE80211_FCTL_FTYPE|RTW_IEEE80211_FCTL_STYPE)); + } + + +fail: + + rtw_skb_free(skb); + + return 0; + +} + +static void rtw_cfg80211_monitor_if_set_multicast_list(struct net_device *ndev) +{ + DBG_8192C("%s\n", __func__); +} + +static int rtw_cfg80211_monitor_if_set_mac_address(struct net_device *ndev, void *addr) +{ + int ret = 0; + + DBG_8192C("%s\n", __func__); + + return ret; +} + +#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29)) +static const struct net_device_ops rtw_cfg80211_monitor_if_ops = { + .ndo_open = rtw_cfg80211_monitor_if_open, + .ndo_stop = rtw_cfg80211_monitor_if_close, + .ndo_start_xmit = rtw_cfg80211_monitor_if_xmit_entry, + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0)) + .ndo_set_multicast_list = rtw_cfg80211_monitor_if_set_multicast_list, + #endif + .ndo_set_mac_address = rtw_cfg80211_monitor_if_set_mac_address, +}; +#endif + +static int rtw_cfg80211_add_monitor_if(_adapter *padapter, char *name, struct net_device **ndev) +{ + int ret = 0; + struct net_device* mon_ndev = NULL; + struct wireless_dev* mon_wdev = NULL; + struct rtw_netdev_priv_indicator *pnpi; + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); + + if (!name) { + DBG_871X(FUNC_ADPT_FMT" without specific name\n", FUNC_ADPT_ARG(padapter)); + ret = -EINVAL; + goto out; + } + + if (pwdev_priv->pmon_ndev) { + DBG_871X(FUNC_ADPT_FMT" monitor interface exist: "NDEV_FMT"\n", + FUNC_ADPT_ARG(padapter), NDEV_ARG(pwdev_priv->pmon_ndev)); + ret = -EBUSY; + goto out; + } + + mon_ndev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator)); + if (!mon_ndev) { + DBG_871X(FUNC_ADPT_FMT" allocate ndev fail\n", FUNC_ADPT_ARG(padapter)); + ret = -ENOMEM; + goto out; + } + + mon_ndev->type = ARPHRD_IEEE80211_RADIOTAP; + strncpy(mon_ndev->name, name, IFNAMSIZ); + mon_ndev->name[IFNAMSIZ - 1] = 0; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,11,9)) + mon_ndev->needs_free_netdev = true; + mon_ndev->priv_destructor = rtw_ndev_destructor; +#else + mon_ndev->destructor = rtw_ndev_destructor; +#endif + +#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29)) + mon_ndev->netdev_ops = &rtw_cfg80211_monitor_if_ops; +#else + mon_ndev->open = rtw_cfg80211_monitor_if_open; + mon_ndev->stop = rtw_cfg80211_monitor_if_close; + mon_ndev->hard_start_xmit = rtw_cfg80211_monitor_if_xmit_entry; + mon_ndev->set_mac_address = rtw_cfg80211_monitor_if_set_mac_address; +#endif + + pnpi = netdev_priv(mon_ndev); + pnpi->priv = padapter; + pnpi->sizeof_priv = sizeof(_adapter); + + /* wdev */ + mon_wdev = (struct wireless_dev *)rtw_zmalloc(sizeof(struct wireless_dev)); + if (!mon_wdev) { + DBG_871X(FUNC_ADPT_FMT" allocate mon_wdev fail\n", FUNC_ADPT_ARG(padapter)); + ret = -ENOMEM; + goto out; + } + + mon_wdev->wiphy = padapter->rtw_wdev->wiphy; + mon_wdev->netdev = mon_ndev; + mon_wdev->iftype = NL80211_IFTYPE_MONITOR; + mon_ndev->ieee80211_ptr = mon_wdev; + + ret = register_netdevice(mon_ndev); + if (ret) { + goto out; + } + + *ndev = pwdev_priv->pmon_ndev = mon_ndev; + _rtw_memcpy(pwdev_priv->ifname_mon, name, IFNAMSIZ+1); + +out: + if (ret && mon_wdev) { + rtw_mfree((u8*)mon_wdev, sizeof(struct wireless_dev)); + mon_wdev = NULL; + } + + if (ret && mon_ndev) { + free_netdev(mon_ndev); + *ndev = mon_ndev = NULL; + } + + return ret; +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0)) +static struct wireless_dev * +#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) || defined(COMPAT_KERNEL_RELEASE) +static struct net_device * +#else +static int +#endif + cfg80211_rtw_add_virtual_intf( + struct wiphy *wiphy, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,7,0)) + const char *name, + #else + char *name, + #endif + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) + unsigned char name_assign_type, + #endif + enum nl80211_iftype type, +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,12,0)) + u32 *flags, +#endif + struct vif_params *params) +{ + int ret = 0; + struct net_device* ndev = NULL; + _adapter *padapter = wiphy_to_adapter(wiphy); + + DBG_871X("%s wiphy:%s, name:%s, type:%d\n", + __func__, wiphy_name(wiphy), name, type); + + switch (type) { + case NL80211_IFTYPE_ADHOC: + case NL80211_IFTYPE_AP_VLAN: + case NL80211_IFTYPE_WDS: + case NL80211_IFTYPE_MESH_POINT: + ret = -ENODEV; + break; + case NL80211_IFTYPE_MONITOR: + ret = rtw_cfg80211_add_monitor_if(padapter, (char *)name, &ndev); + break; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) + case NL80211_IFTYPE_P2P_CLIENT: +#endif + case NL80211_IFTYPE_STATION: + ret = -ENODEV; + break; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) + case NL80211_IFTYPE_P2P_GO: +#endif + case NL80211_IFTYPE_AP: + ret = -ENODEV; + break; + default: + ret = -ENODEV; + DBG_871X("Unsupported interface type\n"); + break; + } + + DBG_871X("%s ndev:%p, ret:%d\n", __func__, ndev, ret); + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0)) + return ndev ? ndev->ieee80211_ptr : ERR_PTR(ret); +#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) || defined(COMPAT_KERNEL_RELEASE) + return ndev ? ndev : ERR_PTR(ret); +#else + return ret; +#endif +} + +static int cfg80211_rtw_del_virtual_intf(struct wiphy *wiphy, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0)) + struct wireless_dev *wdev +#else + struct net_device *ndev +#endif +) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0)) + struct net_device *ndev = wdev_to_ndev(wdev); +#endif + int ret = 0; + _adapter *adapter; + struct rtw_wdev_priv *pwdev_priv; + + if (!ndev) { + ret = -EINVAL; + goto exit; + } + + adapter = (_adapter *)rtw_netdev_priv(ndev); + pwdev_priv = adapter_wdev_data(adapter); + + unregister_netdevice(ndev); + + if (ndev == pwdev_priv->pmon_ndev) { + pwdev_priv->pmon_ndev = NULL; + pwdev_priv->ifname_mon[0] = '\0'; + DBG_871X(FUNC_NDEV_FMT" remove monitor interface\n", FUNC_NDEV_ARG(ndev)); + } + +exit: + return ret; +} + +static int rtw_add_beacon(_adapter *adapter, const u8 *head, size_t head_len, const u8 *tail, size_t tail_len) +{ + int ret=0; + u8 *pbuf = NULL; + uint len, wps_ielen=0; + uint p2p_ielen=0; + u8 *p2p_ie; + u8 got_p2p_ie = _FALSE; + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); + //struct sta_priv *pstapriv = &padapter->stapriv; + + + DBG_8192C("%s beacon_head_len=%zu, beacon_tail_len=%zu\n", __FUNCTION__, head_len, tail_len); + + + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + return -EINVAL; + + if(head_len<24) + return -EINVAL; + + + pbuf = rtw_zmalloc(head_len+tail_len); + if(!pbuf) + return -ENOMEM; + + + //_rtw_memcpy(&pstapriv->max_num_sta, param->u.bcn_ie.reserved, 2); + + //if((pstapriv->max_num_sta>NUM_STA) || (pstapriv->max_num_sta<=0)) + // pstapriv->max_num_sta = NUM_STA; + + + _rtw_memcpy(pbuf, (void *)head+24, head_len-24);// 24=beacon header len. + _rtw_memcpy(pbuf+head_len-24, (void *)tail, tail_len); + + len = head_len+tail_len-24; + + //check wps ie if inclued + if(rtw_get_wps_ie(pbuf+_FIXED_IE_LENGTH_, len-_FIXED_IE_LENGTH_, NULL, &wps_ielen)) + DBG_8192C("add bcn, wps_ielen=%d\n", wps_ielen); + +#ifdef CONFIG_P2P + if( adapter->wdinfo.driver_interface == DRIVER_CFG80211 ) + { + //check p2p if enable + if(rtw_get_p2p_ie(pbuf+_FIXED_IE_LENGTH_, len-_FIXED_IE_LENGTH_, NULL, &p2p_ielen)) + { + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct wifidirect_info *pwdinfo= &(adapter->wdinfo); + + DBG_8192C("got p2p_ie, len=%d\n", p2p_ielen); + + got_p2p_ie = _TRUE; + + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + { + DBG_8192C("Enable P2P function for the first time\n"); + rtw_p2p_enable(adapter, P2P_ROLE_GO); + adapter_wdev_data(adapter)->p2p_enabled = _TRUE; + + adapter->stapriv.expire_to = 3; // 3x2 = 6 sec in p2p mode + } + else + { + DBG_8192C("enter GO Mode, p2p_ielen=%d\n", p2p_ielen); + + rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); + pwdinfo->intent = 15; + } + } + } +#endif // CONFIG_P2P + + /* pbss_network->IEs will not include p2p_ie, wfd ie */ + rtw_ies_remove_ie(pbuf, &len, _BEACON_IE_OFFSET_, _VENDOR_SPECIFIC_IE_, P2P_OUI, 4); + rtw_ies_remove_ie(pbuf, &len, _BEACON_IE_OFFSET_, _VENDOR_SPECIFIC_IE_, WFD_OUI, 4); + + if (rtw_check_beacon_data(adapter, pbuf, len) == _SUCCESS) + { +#ifdef CONFIG_P2P + //check p2p if enable + if(got_p2p_ie == _TRUE) + { + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + struct wifidirect_info *pwdinfo= &(adapter->wdinfo); + pwdinfo->operating_channel = pmlmeext->cur_channel; + } +#endif //CONFIG_P2P + ret = 0; + } + else + { + ret = -EINVAL; + } + + + rtw_mfree(pbuf, head_len+tail_len); + + return ret; +} + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) && !defined(COMPAT_KERNEL_RELEASE) +static int cfg80211_rtw_add_beacon(struct wiphy *wiphy, struct net_device *ndev, + struct beacon_parameters *info) +{ + int ret=0; + _adapter *adapter = (_adapter *)rtw_netdev_priv(ndev); + + DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + ret = rtw_add_beacon(adapter, info->head, info->head_len, info->tail, info->tail_len); + + return ret; +} + +static int cfg80211_rtw_set_beacon(struct wiphy *wiphy, struct net_device *ndev, + struct beacon_parameters *info) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(ndev); + struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); + + DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + + pmlmeext->bstart_bss = _TRUE; + + cfg80211_rtw_add_beacon(wiphy, ndev, info); + + return 0; +} + +static int cfg80211_rtw_del_beacon(struct wiphy *wiphy, struct net_device *ndev) +{ + DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + + return 0; +} +#else +static int cfg80211_rtw_start_ap(struct wiphy *wiphy, struct net_device *ndev, + struct cfg80211_ap_settings *settings) +{ + int ret = 0; + _adapter *adapter = (_adapter *)rtw_netdev_priv(ndev); + + DBG_871X(FUNC_NDEV_FMT" hidden_ssid:%d, auth_type:%d\n", FUNC_NDEV_ARG(ndev), + settings->hidden_ssid, settings->auth_type); + + ret = rtw_add_beacon(adapter, settings->beacon.head, settings->beacon.head_len, + settings->beacon.tail, settings->beacon.tail_len); + + adapter->mlmeextpriv.mlmext_info.hidden_ssid_mode = settings->hidden_ssid; + + if (settings->ssid && settings->ssid_len) { + WLAN_BSSID_EX *pbss_network = &adapter->mlmepriv.cur_network.network; + WLAN_BSSID_EX *pbss_network_ext = &adapter->mlmeextpriv.mlmext_info.network; + + if(0) + DBG_871X(FUNC_ADPT_FMT" ssid:(%s,%zu), from ie:(%s,%d)\n", FUNC_ADPT_ARG(adapter), + settings->ssid, settings->ssid_len, + pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength); + + _rtw_memcpy(pbss_network->Ssid.Ssid, (void *)settings->ssid, settings->ssid_len); + pbss_network->Ssid.SsidLength = settings->ssid_len; + _rtw_memcpy(pbss_network_ext->Ssid.Ssid, (void *)settings->ssid, settings->ssid_len); + pbss_network_ext->Ssid.SsidLength = settings->ssid_len; + + if(0) + DBG_871X(FUNC_ADPT_FMT" after ssid:(%s,%d), (%s,%d)\n", FUNC_ADPT_ARG(adapter), + pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength, + pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength); + } + + return ret; +} + +static int cfg80211_rtw_change_beacon(struct wiphy *wiphy, struct net_device *ndev, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 7, 0) + struct cfg80211_ap_update *params) +#else + struct cfg80211_beacon_data *info) +#endif +{ + int ret = 0; + _adapter *adapter = (_adapter *)rtw_netdev_priv(ndev); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 7, 0) + struct cfg80211_beacon_data *info = ¶ms->beacon; +#endif + + DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + + ret = rtw_add_beacon(adapter, info->head, info->head_len, info->tail, info->tail_len); + + return ret; +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0)) +static int cfg80211_rtw_stop_ap(struct wiphy *wiphy, struct net_device *ndev, unsigned int link_id) +#else +static int cfg80211_rtw_stop_ap(struct wiphy *wiphy, struct net_device *ndev) +#endif +{ + DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + return 0; +} + +#endif //(LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) + +static int cfg80211_rtw_add_station(struct wiphy *wiphy, struct net_device *ndev, +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,16,0)) + u8 *mac, +#else + const u8 *mac, +#endif + struct station_parameters *params) +{ + int ret = 0; +#ifdef CONFIG_TDLS + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct sta_priv *pstapriv = &padapter->stapriv; + struct sta_info *psta; +#endif /* CONFIG_TDLS */ + DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + +#ifdef CONFIG_TDLS + psta = rtw_get_stainfo(pstapriv, (u8 *)mac); + if (psta == NULL) { + psta = rtw_alloc_stainfo(pstapriv, (u8 *)mac); + if (psta ==NULL) { + DBG_871X("[%s] Alloc station for "MAC_FMT" fail\n", __FUNCTION__, MAC_ARG(mac)); + ret =-EOPNOTSUPP; + goto exit; + } + } +#endif /* CONFIG_TDLS */ + +exit: + return ret; +} + +static int cfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *ndev, +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,16,0)) + u8 *mac +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0)) + const u8 *mac +#else + struct station_del_parameters *params +#endif + ) +{ + int ret=0; + _irqL irqL; + _list *phead, *plist; + u8 updated = _FALSE; + const u8 *target_mac; + struct sta_info *psta = NULL; + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sta_priv *pstapriv = &padapter->stapriv; + + DBG_871X("+"FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 19, 0)) + target_mac = mac; +#else + target_mac = params->mac; +#endif + + if(check_fwstate(pmlmepriv, (_FW_LINKED|WIFI_AP_STATE)) != _TRUE) + { + DBG_8192C("%s, fw_state != FW_LINKED|WIFI_AP_STATE\n", __func__); + return -EINVAL; + } + + + if (!target_mac) + { + DBG_8192C("flush all sta, and cam_entry\n"); + + flush_all_cam_entry(padapter); //clear CAM + + ret = rtw_sta_flush(padapter, _TRUE); + + return ret; + } + + + DBG_8192C("free sta macaddr =" MAC_FMT "\n", MAC_ARG(target_mac)); + + if (target_mac[0] == 0xff && target_mac[1] == 0xff && + target_mac[2] == 0xff && target_mac[3] == 0xff && + target_mac[4] == 0xff && target_mac[5] == 0xff) + { + return -EINVAL; + } + + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + phead = &pstapriv->asoc_list; + plist = get_next(phead); + + //check asoc_queue + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) + { + psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + + plist = get_next(plist); + + if (_rtw_memcmp((u8 *)target_mac, psta->hwaddr, ETH_ALEN)) + { + if(psta->dot8021xalg == 1 && psta->bpairwise_key_installed == _FALSE) + { + DBG_8192C("%s, sta's dot8021xalg = 1 and key_installed = _FALSE\n", __func__); + } + else + { + DBG_8192C("free psta=%p, aid=%d\n", psta, psta->aid); + + rtw_list_delete(&psta->asoc_list); + pstapriv->asoc_list_cnt--; + + //_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + if (check_fwstate(pmlmepriv, (WIFI_AP_STATE)) == _TRUE) + updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_PREV_AUTH_NOT_VALID, _TRUE); + else + updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, _TRUE); + //_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + psta = NULL; + + break; + } + + } + + } + + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL); + + DBG_871X("-"FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + + return ret; + +} + +static int cfg80211_rtw_change_station(struct wiphy *wiphy, struct net_device *ndev, +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,16,0)) + u8 *mac, +#else + const u8 *mac, +#endif + struct station_parameters *params) +{ + DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + + return 0; +} + +struct sta_info *rtw_sta_info_get_by_idx(const int idx, struct sta_priv *pstapriv) + +{ + + _list *phead, *plist; + struct sta_info *psta = NULL; + int i = 0; + + phead = &pstapriv->asoc_list; + plist = get_next(phead); + + //check asoc_queue + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) + { + if(idx == i) psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + plist = get_next(plist); + i++; + } + return psta; +} + +static int cfg80211_rtw_dump_station(struct wiphy *wiphy, struct net_device *ndev, + int idx, u8 *mac, struct station_info *sinfo) +{ + + int ret = 0; + _irqL irqL; + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct sta_info *psta = NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + psta = rtw_sta_info_get_by_idx(idx, pstapriv); + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + if(NULL == psta) + { + DBG_871X("Station is not found\n"); + ret = -ENOENT; + goto exit; + } + _rtw_memcpy(mac, psta->hwaddr, ETH_ALEN); + sinfo->filled = 0; + sinfo->filled |= STATION_INFO_SIGNAL; + sinfo->signal = psta->rssi; + +exit: + return ret; +} + +static int cfg80211_rtw_change_bss(struct wiphy *wiphy, struct net_device *ndev, + struct bss_parameters *params) +{ + u8 i; + + DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); +/* + DBG_8192C("use_cts_prot=%d\n", params->use_cts_prot); + DBG_8192C("use_short_preamble=%d\n", params->use_short_preamble); + DBG_8192C("use_short_slot_time=%d\n", params->use_short_slot_time); + DBG_8192C("ap_isolate=%d\n", params->ap_isolate); + + DBG_8192C("basic_rates_len=%d\n", params->basic_rates_len); + for(i=0; ibasic_rates_len; i++) + { + DBG_8192C("basic_rates=%d\n", params->basic_rates[i]); + + } +*/ + return 0; + +} + +static int cfg80211_rtw_set_channel(struct wiphy *wiphy + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) + , struct net_device *ndev + #endif + , struct ieee80211_channel *chan, enum nl80211_channel_type channel_type) +{ + int chan_target = (u8) ieee80211_frequency_to_channel(chan->center_freq); + int chan_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + int chan_width = CHANNEL_WIDTH_20; + _adapter *padapter = wiphy_to_adapter(wiphy); + + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) + DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + #endif + + switch (channel_type) { + case NL80211_CHAN_NO_HT: + case NL80211_CHAN_HT20: + chan_width = CHANNEL_WIDTH_20; + chan_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; + case NL80211_CHAN_HT40MINUS: + chan_width = CHANNEL_WIDTH_40; + chan_offset = HAL_PRIME_CHNL_OFFSET_UPPER; + break; + case NL80211_CHAN_HT40PLUS: + chan_width = CHANNEL_WIDTH_40; + chan_offset = HAL_PRIME_CHNL_OFFSET_LOWER; + break; + default: + chan_width = CHANNEL_WIDTH_20; + chan_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; + } + + set_channel_bwmode(padapter, chan_target, chan_offset, chan_width); + + return 0; +} + +static int cfg80211_rtw_set_monitor_channel(struct wiphy *wiphy +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) + , struct cfg80211_chan_def *chandef +#else + , struct ieee80211_channel *chan + , enum nl80211_channel_type channel_type +#endif + ) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) + struct ieee80211_channel *chan = chandef->chan; +#endif + + _adapter *padapter = wiphy_to_adapter(wiphy); + int target_channal = chan->hw_value; + int target_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + int target_width = CHANNEL_WIDTH_20; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) +#ifdef CONFIG_DEBUG_CFG80211 + DBG_8192C("center_freq %u Mhz ch %u width %u freq1 %u freq2 %u\n" + , chan->center_freq + , chan->hw_value + , chandef->width + , chandef->center_freq1 + , chandef->center_freq2); +#endif /* CONFIG_DEBUG_CFG80211 */ + + switch (chandef->width) { + case NL80211_CHAN_WIDTH_20_NOHT: + case NL80211_CHAN_WIDTH_20: + target_width = CHANNEL_WIDTH_20; + target_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; + case NL80211_CHAN_WIDTH_40: + target_width = CHANNEL_WIDTH_40; + if (chandef->center_freq1 > chan->center_freq) + target_offset = HAL_PRIME_CHNL_OFFSET_LOWER; + else + target_offset = HAL_PRIME_CHNL_OFFSET_UPPER; + break; + case NL80211_CHAN_WIDTH_80: + target_width = CHANNEL_WIDTH_80; + target_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; + case NL80211_CHAN_WIDTH_80P80: + target_width = CHANNEL_WIDTH_80_80; + target_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; + case NL80211_CHAN_WIDTH_160: + target_width = CHANNEL_WIDTH_160; + target_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) + case NL80211_CHAN_WIDTH_5: + case NL80211_CHAN_WIDTH_10: +#endif + default: + target_width = CHANNEL_WIDTH_20; + target_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; + } +#else +#ifdef CONFIG_DEBUG_CFG80211 + DBG_8192C("center_freq %u Mhz ch %u channel_type %u\n" + , chan->center_freq + , chan->hw_value + , channel_type); +#endif /* CONFIG_DEBUG_CFG80211 */ + + switch (channel_type) { + case NL80211_CHAN_NO_HT: + case NL80211_CHAN_HT20: + target_width = CHANNEL_WIDTH_20; + target_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; + case NL80211_CHAN_HT40MINUS: + target_width = CHANNEL_WIDTH_40; + target_offset = HAL_PRIME_CHNL_OFFSET_UPPER; + break; + case NL80211_CHAN_HT40PLUS: + target_width = CHANNEL_WIDTH_40; + target_offset = HAL_PRIME_CHNL_OFFSET_LOWER; + break; + default: + target_width = CHANNEL_WIDTH_20; + target_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; + } +#endif + + set_channel_bwmode(padapter, target_channal, target_offset, target_width); + + return 0; +} + +static int cfg80211_rtw_auth(struct wiphy *wiphy, struct net_device *ndev, + struct cfg80211_auth_request *req) +{ + DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + + return 0; +} + +static int cfg80211_rtw_assoc(struct wiphy *wiphy, struct net_device *ndev, + struct cfg80211_assoc_request *req) +{ + DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + + return 0; +} +#endif //CONFIG_AP_MODE + +void rtw_cfg80211_rx_probe_request(_adapter *adapter, u8 *frame, uint frame_len) +{ + s32 freq; + int channel; + struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter); + u8 category, action; + + channel = rtw_get_oper_ch(adapter); + freq = rtw_ch2freq(channel); + +#ifdef CONFIG_DEBUG_CFG80211 + DBG_8192C("RTW_Rx: probe request, cur_ch=%d\n", channel); +#endif /* CONFIG_DEBUG_CFG80211 */ + rtw_cfg80211_rx_mgmt(adapter, freq, 0, frame, frame_len, GFP_ATOMIC); +} + +void rtw_cfg80211_rx_action_p2p(_adapter *padapter, u8 *pmgmt_frame, uint frame_len) +{ + int type; + s32 freq; + int channel; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + u8 category, action; + + channel = rtw_get_oper_ch(padapter); + + DBG_8192C("RTW_Rx:cur_ch=%d\n", channel); + #ifdef CONFIG_P2P + type = rtw_p2p_check_frames(padapter, pmgmt_frame, frame_len, _FALSE); + if (type >= 0) + goto indicate; + #endif + rtw_action_frame_parse(pmgmt_frame, frame_len, &category, &action); + DBG_871X("RTW_Rx:category(%u), action(%u)\n", category, action); + +indicate: + freq = rtw_ch2freq(channel); + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) + rtw_cfg80211_rx_mgmt(padapter, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC); +#else + cfg80211_rx_action(padapter->pnetdev, freq, pmgmt_frame, frame_len, GFP_ATOMIC); +#endif +} + +void rtw_cfg80211_rx_p2p_action_public(_adapter *padapter, u8 *pmgmt_frame, uint frame_len) +{ + int type; + s32 freq; + int channel; + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + u8 category, action; + + channel = rtw_get_oper_ch(padapter); + + DBG_8192C("RTW_Rx:cur_ch=%d\n", channel); + #ifdef CONFIG_P2P + type = rtw_p2p_check_frames(padapter, pmgmt_frame, frame_len, _FALSE); + if (type >= 0) { + switch (type) { + case P2P_GO_NEGO_CONF: + case P2P_PROVISION_DISC_RESP: + case P2P_INVIT_RESP: + rtw_set_scan_deny(padapter, 2000); + rtw_clear_scan_deny(padapter); + } + goto indicate; + } + #endif + rtw_action_frame_parse(pmgmt_frame, frame_len, &category, &action); + DBG_871X("RTW_Rx:category(%u), action(%u)\n", category, action); + +indicate: + freq = rtw_ch2freq(channel); + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) + rtw_cfg80211_rx_mgmt(padapter, freq, 0, pmgmt_frame, frame_len, GFP_ATOMIC); +#else + cfg80211_rx_action(padapter->pnetdev, freq, pmgmt_frame, frame_len, GFP_ATOMIC); +#endif +} + +void rtw_cfg80211_rx_action(_adapter *adapter, u8 *frame, uint frame_len, const char*msg) +{ + s32 freq; + int channel; + struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(adapter); + u8 category, action; + + channel = rtw_get_oper_ch(adapter); + + rtw_action_frame_parse(frame, frame_len, &category, &action); + + if (action == ACT_PUBLIC_GAS_INITIAL_REQ) { + rtw_set_scan_deny(adapter, 200); + rtw_scan_abort_no_wait(adapter); + #ifdef CONFIG_CONCURRENT_MODE + if (rtw_buddy_adapter_up(adapter)) + rtw_scan_abort_no_wait(adapter->pbuddy_adapter); + #endif + } + + freq = rtw_ch2freq(channel); + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) + rtw_cfg80211_rx_mgmt(adapter, freq, 0, frame, frame_len, GFP_ATOMIC); +#else + cfg80211_rx_action(adapter->pnetdev, freq, frame, frame_len, GFP_ATOMIC); +#endif + + DBG_8192C("RTW_Rx:cur_ch=%d\n", channel); + if (msg) + DBG_871X("RTW_Rx:%s\n", msg); + else + DBG_871X("RTW_Rx:category(%u), action(%u)\n", category, action); +} + +#ifdef CONFIG_P2P +void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len) +{ + u16 wps_devicepassword_id = 0x0000; + uint wps_devicepassword_id_len = 0; + u8 wpsie[ 255 ] = { 0x00 }, p2p_ie[ 255 ] = { 0x00 }; + uint p2p_ielen = 0; + uint wpsielen = 0; + u32 devinfo_contentlen = 0; + u8 devinfo_content[64] = { 0x00 }; + u16 capability = 0; + uint capability_len = 0; + + unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; + u8 action = P2P_PUB_ACTION_ACTION; + u8 dialogToken = 1; + u32 p2poui = cpu_to_be32(P2POUI); + u8 oui_subtype = P2P_PROVISION_DISC_REQ; + u32 p2pielen = 0; +#ifdef CONFIG_WFD + u32 wfdielen = 0; +#endif + + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + struct rtw_ieee80211_hdr *pwlanhdr; + unsigned short *fctrl; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + u8 *frame_body = (unsigned char *)(buf + sizeof(struct rtw_ieee80211_hdr_3addr)); + size_t frame_body_len = len - sizeof(struct rtw_ieee80211_hdr_3addr); + + + DBG_871X( "[%s] In\n", __FUNCTION__ ); + + //prepare for building provision_request frame + _rtw_memcpy(pwdinfo->tx_prov_disc_info.peerIFAddr, GetAddr1Ptr(buf), ETH_ALEN); + _rtw_memcpy(pwdinfo->tx_prov_disc_info.peerDevAddr, GetAddr1Ptr(buf), ETH_ALEN); + + pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON; + + rtw_get_wps_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, frame_body_len - _PUBLIC_ACTION_IE_OFFSET_, wpsie, &wpsielen); + rtw_get_wps_attr_content( wpsie, wpsielen, WPS_ATTR_DEVICE_PWID, (u8*) &wps_devicepassword_id, &wps_devicepassword_id_len); + wps_devicepassword_id = be16_to_cpu( wps_devicepassword_id ); + + switch(wps_devicepassword_id) + { + case WPS_DPID_PIN: + pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_LABEL; + break; + case WPS_DPID_USER_SPEC: + pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_DISPLYA; + break; + case WPS_DPID_MACHINE_SPEC: + break; + case WPS_DPID_REKEY: + break; + case WPS_DPID_PBC: + pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON; + break; + case WPS_DPID_REGISTRAR_SPEC: + pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_KEYPAD; + break; + default: + break; + } + + + if ( rtw_get_p2p_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, frame_body_len - _PUBLIC_ACTION_IE_OFFSET_, p2p_ie, &p2p_ielen ) ) + { + + rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO, devinfo_content, &devinfo_contentlen); + rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8*)&capability, &capability_len); + + } + + + //start to build provision_request frame + _rtw_memset(wpsie, 0, sizeof(wpsie)); + _rtw_memset(p2p_ie, 0, sizeof(p2p_ie)); + p2p_ielen = 0; + + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + { + return; + } + + + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + + fctrl = &(pwlanhdr->frame_ctl); + *(fctrl) = 0; + + _rtw_memcpy(pwlanhdr->addr1, pwdinfo->tx_prov_disc_info.peerDevAddr, ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr2, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pwlanhdr->addr3, pwdinfo->tx_prov_disc_info.peerDevAddr, ETH_ALEN); + + SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); + pmlmeext->mgnt_seq++; + SetFrameSubType(pframe, WIFI_ACTION); + + pframe += sizeof(struct rtw_ieee80211_hdr_3addr); + pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); + + pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); + pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); + + + //build_prov_disc_request_p2p_ie + // P2P OUI + p2pielen = 0; + p2p_ie[ p2pielen++ ] = 0x50; + p2p_ie[ p2pielen++ ] = 0x6F; + p2p_ie[ p2pielen++ ] = 0x9A; + p2p_ie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 + + // Commented by Albert 20110301 + // According to the P2P Specification, the provision discovery request frame should contain 3 P2P attributes + // 1. P2P Capability + // 2. Device Info + // 3. Group ID ( When joining an operating P2P Group ) + + // P2P Capability ATTR + // Type: + p2p_ie[ p2pielen++ ] = P2P_ATTR_CAPABILITY; + + // Length: + //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); + RTW_PUT_LE16(p2p_ie + p2pielen, 0x0002); + p2pielen += 2; + + // Value: + // Device Capability Bitmap, 1 byte + // Group Capability Bitmap, 1 byte + _rtw_memcpy(p2p_ie + p2pielen, &capability, 2); + p2pielen += 2; + + + // Device Info ATTR + // Type: + p2p_ie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO; + + // Length: + // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) + // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) + //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); + RTW_PUT_LE16(p2p_ie + p2pielen, devinfo_contentlen); + p2pielen += 2; + + // Value: + _rtw_memcpy(p2p_ie + p2pielen, devinfo_content, devinfo_contentlen); + p2pielen += devinfo_contentlen; + + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2p_ie, &p2p_ielen); + //p2pielen = build_prov_disc_request_p2p_ie( pwdinfo, pframe, NULL, 0, pwdinfo->tx_prov_disc_info.peerDevAddr); + //pframe += p2pielen; + pattrib->pktlen += p2p_ielen; + + wpsielen = 0; + // WPS OUI + *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); + wpsielen += 4; + + // WPS version + // Type: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 ); + wpsielen += 2; + + // Length: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); + wpsielen += 2; + + // Value: + wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0 + + // Config Method + // Type: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD ); + wpsielen += 2; + + // Length: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); + wpsielen += 2; + + // Value: + *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( pwdinfo->tx_prov_disc_info.wps_config_method_request ); + wpsielen += 2; + + pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen ); + + +#ifdef CONFIG_WFD + wfdielen = build_provdisc_req_wfd_ie(pwdinfo, pframe); + pframe += wfdielen; + pattrib->pktlen += wfdielen; +#endif + + pattrib->last_txcmdsz = pattrib->pktlen; + + //dump_mgntframe(padapter, pmgntframe); + if (dump_mgntframe_and_wait_ack(padapter, pmgntframe) != _SUCCESS) + DBG_8192C("%s, ack to\n", __func__); + + //if(wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC) + //{ + // DBG_8192C("waiting for p2p peer key-in PIN CODE\n"); + // rtw_msleep_os(15000); // 15 sec for key in PIN CODE, workaround for GS2 before issuing Nego Req. + //} + +} + +static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0)) + struct wireless_dev *wdev, +#else + struct net_device *ndev, +#endif + struct ieee80211_channel * channel, +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0)) + enum nl80211_channel_type channel_type, +#endif + unsigned int duration, u64 *cookie) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0)) + struct net_device *ndev = wdev_to_ndev(wdev); +#endif + s32 err = 0; + u8 remain_ch = (u8) ieee80211_frequency_to_channel(channel->center_freq); + u8 ready_on_channel = _FALSE; + _adapter *padapter; + struct rtw_wdev_priv *pwdev_priv; + struct mlme_ext_priv *pmlmeext; + struct wifidirect_info *pwdinfo; + struct cfg80211_wifidirect_info *pcfg80211_wdinfo; + u8 is_p2p_find = _FALSE; + +#ifndef CONFIG_RADIO_WORK + #define RTW_ROCH_DURATION_ENLARGE + #define RTW_ROCH_BACK_OP +#endif + + if (ndev == NULL) { + return -EINVAL; + } + + padapter = (_adapter *)rtw_netdev_priv(ndev); + pwdev_priv = adapter_wdev_data(padapter); + pmlmeext = &padapter->mlmeextpriv; + pwdinfo = &padapter->wdinfo; + pcfg80211_wdinfo = &padapter->cfg80211_wdinfo; + #ifdef CONFIG_CONCURRENT_MODE + is_p2p_find=(duration < (pwdinfo->ext_listen_interval))? _TRUE : _FALSE; + #endif + + *cookie = ATOMIC_INC_RETURN(&pcfg80211_wdinfo->ro_ch_cookie_gen); + + DBG_871X(FUNC_ADPT_FMT" ch:%u duration:%d, cookie:0x%llx\n", FUNC_ADPT_ARG(padapter), remain_ch, duration, *cookie); + +#ifdef CONFIG_MP_INCLUDED + if (padapter->registrypriv.mp_mode == 1) { + DBG_871X(FUNC_ADPT_FMT ": MP mode block remain_on_channel request\n", FUNC_ADPT_ARG(padapter)); + err = -EFAULT; + goto exit; + } +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->pbuddy_adapter) { + if (padapter->pbuddy_adapter->registrypriv.mp_mode == 1) { + DBG_871X(FUNC_ADPT_FMT ": MP mode block remain_on_channel request\n", FUNC_ADPT_ARG(padapter->pbuddy_adapter)); + err = -EFAULT; + goto exit; + } + } +#endif +#endif + + if(pcfg80211_wdinfo->is_ro_ch == _TRUE) + { + DBG_8192C("%s, cancel ro ch timer\n", __func__); + _cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer); + #ifdef CONFIG_CONCURRENT_MODE + ATOMIC_SET(&pwdev_priv->ro_ch_to, 1); + #endif //CONFIG_CONCURRENT_MODE + p2p_protocol_wk_hdl(padapter, P2P_RO_CH_WK); + } + + pcfg80211_wdinfo->is_ro_ch = _TRUE; + pcfg80211_wdinfo->last_ro_ch_time = rtw_get_current_time(); + + if(_FAIL == rtw_pwr_wakeup(padapter)) { + err = -EFAULT; + goto exit; + } + + _rtw_memcpy(&pcfg80211_wdinfo->remain_on_ch_channel, channel, sizeof(struct ieee80211_channel)); + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0)) + pcfg80211_wdinfo->remain_on_ch_type= channel_type; + #endif + pcfg80211_wdinfo->remain_on_ch_cookie= *cookie; + + rtw_scan_abort(padapter); +#ifdef CONFIG_CONCURRENT_MODE + if ((rtw_buddy_adapter_up(padapter)) && is_p2p_find) //don't scan_abort during p2p_listen. + rtw_scan_abort(padapter->pbuddy_adapter); +#endif //CONFIG_CONCURRENT_MODE + + if (check_fwstate(&padapter->mlmepriv, _FW_UNDER_LINKING|WIFI_UNDER_WPS) == _TRUE) + { + DBG_871X("mlme state:0x%x\n", get_fwstate(&padapter->mlmepriv)); + remain_ch = padapter->mlmeextpriv.cur_channel; + } +#ifdef CONFIG_CONCURRENT_MODE + if (check_buddy_fwstate(padapter, _FW_UNDER_LINKING|WIFI_UNDER_WPS) == _TRUE) + { + DBG_871X("buddy_intf's mlme state:0x%x\n", get_fwstate(&(padapter->pbuddy_adapter->mlmepriv))); + remain_ch = padapter->pbuddy_adapter->mlmeextpriv.cur_channel; + } +#endif /* CONFIG_CONCURRENT_MODE */ + + //if(!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) && !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + { + rtw_p2p_enable(padapter, P2P_ROLE_DEVICE); + adapter_wdev_data(padapter)->p2p_enabled = _TRUE; + padapter->wdinfo.listen_channel = remain_ch; + } else if (rtw_p2p_chk_state(pwdinfo , P2P_STATE_LISTEN)) { + padapter->wdinfo.listen_channel = remain_ch; + } else { + rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); +#ifdef CONFIG_DEBUG_CFG80211 + DBG_8192C("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo)); +#endif + } + + + rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN); + + #ifdef RTW_ROCH_DURATION_ENLARGE + if (duration < 400) + duration = duration * 3; /* extend from exper */ + #endif + +#ifdef RTW_ROCH_BACK_OP +#ifdef CONFIG_CONCURRENT_MODE + if (check_buddy_fwstate(padapter, _FW_LINKED)) { + if (is_p2p_find) /* p2p_find , duration<1000 */ + duration = duration + pwdinfo->ext_listen_interval; + else /* p2p_listen, duration=5000 */ + duration = pwdinfo->ext_listen_interval + (pwdinfo->ext_listen_interval / 4); + } +#endif +#endif /* RTW_ROCH_BACK_OP */ + + pcfg80211_wdinfo->restore_channel = rtw_get_oper_ch(padapter); + + if(rtw_ch_set_search_ch(pmlmeext->channel_set, remain_ch) >= 0) { +#ifdef CONFIG_CONCURRENT_MODE + if ( check_buddy_fwstate(padapter, _FW_LINKED) ) + { + PADAPTER pbuddy_adapter = padapter->pbuddy_adapter; + struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; + + if((remain_ch != pbuddy_mlmeext->cur_channel) && !check_fwstate(&padapter->mlmepriv, _FW_LINKED)) + { + if(ATOMIC_READ(&pwdev_priv->switch_ch_to)==1 || + (remain_ch != pmlmeext->cur_channel)) + { + if (check_buddy_fwstate(padapter, WIFI_FW_STATION_STATE)) { + DBG_8192C("%s, issue nulldata pwrbit=1\n", __func__); + issue_nulldata(padapter->pbuddy_adapter, NULL, 1, 3, 500); + } + + ATOMIC_SET(&pwdev_priv->switch_ch_to, 0); + + #ifdef RTW_ROCH_BACK_OP + DBG_8192C("%s, set switch ch timer, duration=%d\n", __func__, duration-pwdinfo->ext_listen_interval); + _set_timer(&pwdinfo->ap_p2p_switch_timer, duration-pwdinfo->ext_listen_interval); + #endif + } + } + + ready_on_channel = _TRUE; + //pmlmeext->cur_channel = remain_ch; + //set_channel_bwmode(padapter, remain_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + }else +#endif //CONFIG_CONCURRENT_MODE + if(remain_ch != rtw_get_oper_ch(padapter) ) + { + ready_on_channel = _TRUE; + //pmlmeext->cur_channel = remain_ch; + //set_channel_bwmode(padapter, remain_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + } + } else { + DBG_871X("%s remain_ch:%u not in channel plan!!!!\n", __FUNCTION__, remain_ch); + } + + + //call this after other things have been done +#ifdef CONFIG_CONCURRENT_MODE + if(ATOMIC_READ(&pwdev_priv->ro_ch_to)==1 || + (remain_ch != rtw_get_oper_ch(padapter))) + { + u8 co_channel = 0xff; + ATOMIC_SET(&pwdev_priv->ro_ch_to, 0); +#endif + + if(ready_on_channel == _TRUE) + { + if ( !check_fwstate(&padapter->mlmepriv, _FW_LINKED ) ) + { + pmlmeext->cur_channel = remain_ch; + +#ifdef CONFIG_CONCURRENT_MODE + co_channel = rtw_get_oper_ch(padapter); + + if(co_channel !=remain_ch) +#endif + { + //if (!padapter->mlmepriv.LinkDetectInfo.bBusyTraffic) + set_channel_bwmode(padapter, remain_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + } + } + } + DBG_8192C("%s, set ro ch timer, duration=%d\n", __func__, duration); + _set_timer( &pcfg80211_wdinfo->remain_on_ch_timer, duration); + +#ifdef CONFIG_CONCURRENT_MODE + } +#endif + + rtw_cfg80211_ready_on_channel(padapter, *cookie, channel, channel_type, duration, GFP_KERNEL); + +exit: + if (err) { + pcfg80211_wdinfo->is_ro_ch = _FALSE; + pcfg80211_wdinfo->last_ro_ch_time = rtw_get_current_time(); + } + + return err; +} + +static s32 cfg80211_rtw_cancel_remain_on_channel(struct wiphy *wiphy, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0)) + struct wireless_dev *wdev, +#else + struct net_device *ndev, +#endif + u64 cookie) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0)) + struct net_device *ndev = wdev_to_ndev(wdev); +#endif + s32 err = 0; + _adapter *padapter; + struct rtw_wdev_priv *pwdev_priv; + struct wifidirect_info *pwdinfo; + struct cfg80211_wifidirect_info *pcfg80211_wdinfo; + + if (ndev == NULL) { + err = -EINVAL; + goto exit; + } + + padapter = (_adapter *)rtw_netdev_priv(ndev); + pwdev_priv = adapter_wdev_data(padapter); + pwdinfo = &padapter->wdinfo; + pcfg80211_wdinfo = &padapter->cfg80211_wdinfo; + + DBG_871X(FUNC_ADPT_FMT" cookie:0x%llx\n", FUNC_ADPT_ARG(padapter), cookie); + + if (pcfg80211_wdinfo->is_ro_ch == _TRUE) { + DBG_8192C("%s, cancel ro ch timer\n", __func__); + _cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer); + #ifdef CONFIG_CONCURRENT_MODE + ATOMIC_SET(&pwdev_priv->ro_ch_to, 1); + #endif + p2p_protocol_wk_hdl(padapter, P2P_RO_CH_WK); + } + + #if 0 + // Disable P2P Listen State + if(!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) && !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) + { + if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + { + rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE); + _rtw_memset(pwdinfo, 0x00, sizeof(struct wifidirect_info)); + } + } + else + #endif + { + rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); +#ifdef CONFIG_DEBUG_CFG80211 + DBG_8192C("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo)); +#endif + } + + pcfg80211_wdinfo->is_ro_ch = _FALSE; + pcfg80211_wdinfo->last_ro_ch_time = rtw_get_current_time(); + +exit: + return err; +} + +#endif //CONFIG_P2P + +static int _cfg80211_rtw_mgmt_tx(_adapter *padapter, u8 tx_ch, const u8 *buf, size_t len, int wait_ack) +{ + struct xmit_frame *pmgntframe; + struct pkt_attrib *pattrib; + unsigned char *pframe; + int ret = _FAIL; + bool ack = _TRUE; + struct rtw_ieee80211_hdr *pwlanhdr; + struct rtw_wdev_priv *pwdev_priv = adapter_wdev_data(padapter); + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &padapter->wdinfo; +#endif //CONFIG_P2P + //struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo; + + rtw_set_scan_deny(padapter, 1000); + + rtw_scan_abort(padapter); + #ifdef CONFIG_CONCURRENT_MODE + if(rtw_buddy_adapter_up(padapter)) + rtw_scan_abort(padapter->pbuddy_adapter); + #endif /* CONFIG_CONCURRENT_MODE */ +#ifdef CONFIG_P2P + if (padapter->cfg80211_wdinfo.is_ro_ch == _TRUE) { + //DBG_8192C("%s, cancel ro ch timer\n", __func__); + //_cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer); + //padapter->cfg80211_wdinfo.is_ro_ch = _FALSE; + #ifdef CONFIG_CONCURRENT_MODE + if (!check_fwstate(&padapter->mlmepriv, _FW_LINKED )) + { + DBG_8192C("%s, extend ro ch time\n", __func__); + _set_timer( &padapter->cfg80211_wdinfo.remain_on_ch_timer, pwdinfo->ext_listen_period); + } + #endif //CONFIG_CONCURRENT_MODE + } +#endif //CONFIG_P2P +#ifdef CONFIG_CONCURRENT_MODE + if (check_buddy_fwstate(padapter, _FW_LINKED )) { + u8 co_channel=0xff; + PADAPTER pbuddy_adapter = padapter->pbuddy_adapter; + struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; + + co_channel = rtw_get_oper_ch(padapter); + + if (tx_ch != pbuddy_mlmeext->cur_channel) { + + u16 ext_listen_period; + + if (ATOMIC_READ(&pwdev_priv->switch_ch_to)==1) { + if (check_buddy_fwstate(padapter, WIFI_FW_STATION_STATE)) { + DBG_8192C("%s, issue nulldata pwrbit=1\n", __func__); + issue_nulldata(padapter->pbuddy_adapter, NULL, 1, 3, 500); + } + + ATOMIC_SET(&pwdev_priv->switch_ch_to, 0); + + //DBG_8192C("%s, set switch ch timer, period=%d\n", __func__, pwdinfo->ext_listen_period); + //_set_timer(&pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_period); + } + + if (check_fwstate(&padapter->mlmepriv, _FW_LINKED )) + { + ext_listen_period = 500;// 500ms + } + else + { + ext_listen_period = pwdinfo->ext_listen_period; + } + + DBG_8192C("%s, set switch ch timer, period=%d\n", __func__, ext_listen_period); + _set_timer(&pwdinfo->ap_p2p_switch_timer, ext_listen_period); + + } + + if (!check_fwstate(&padapter->mlmepriv, _FW_LINKED )) + pmlmeext->cur_channel = tx_ch; + + if (tx_ch != co_channel) + set_channel_bwmode(padapter, tx_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + }else +#endif //CONFIG_CONCURRENT_MODE + //if (tx_ch != pmlmeext->cur_channel) { + if(tx_ch != rtw_get_oper_ch(padapter)) { + if (!check_fwstate(&padapter->mlmepriv, _FW_LINKED )) + pmlmeext->cur_channel = tx_ch; + set_channel_bwmode(padapter, tx_ch, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + } + + //starting alloc mgmt frame to dump it + if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) + { + //ret = -ENOMEM; + ret = _FAIL; + goto exit; + } + + //update attribute + pattrib = &pmgntframe->attrib; + update_mgntframe_attrib(padapter, pattrib); + pattrib->retry_ctrl = _FALSE; + + _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); + + pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; + + _rtw_memcpy(pframe, (void*)buf, len); + pattrib->pktlen = len; + + pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; + //update seq number + pmlmeext->mgnt_seq = GetSequence(pwlanhdr); + pattrib->seqnum = pmlmeext->mgnt_seq; + pmlmeext->mgnt_seq++; + +#ifdef CONFIG_P2P + rtw_xframe_chk_wfd_ie(pmgntframe); +#endif /* CONFIG_P2P */ + + pattrib->last_txcmdsz = pattrib->pktlen; + + if (wait_ack) { + if (dump_mgntframe_and_wait_ack(padapter, pmgntframe) != _SUCCESS) { + ack = _FALSE; + ret = _FAIL; + +#ifdef CONFIG_DEBUG_CFG80211 + DBG_8192C("%s, ack == _FAIL\n", __func__); +#endif + } else { + +#ifdef CONFIG_XMIT_ACK + rtw_msleep_os(50); +#endif +#ifdef CONFIG_DEBUG_CFG80211 + DBG_8192C("%s, ack=%d, ok!\n", __func__, ack); +#endif + ret = _SUCCESS; + } + } else { + dump_mgntframe(padapter, pmgntframe); + ret = _SUCCESS; + } +exit: + + #ifdef CONFIG_DEBUG_CFG80211 + DBG_8192C("%s, ret=%d\n", __func__, ret); + #endif + + return ret; + +} + +static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0)) + struct wireless_dev *wdev, +#else + struct net_device *ndev, +#endif +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0)) || defined(COMPAT_KERNEL_RELEASE) + struct ieee80211_channel *chan, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) || defined(COMPAT_KERNEL_RELEASE) + bool offchan, + #endif + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0)) + enum nl80211_channel_type channel_type, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) + bool channel_type_valid, + #endif + #endif + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) || defined(COMPAT_KERNEL_RELEASE) + unsigned int wait, + #endif + const u8 *buf, size_t len, + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0)) + bool no_cck, + #endif + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,3,0)) + bool dont_wait_for_ack, + #endif +#else + struct cfg80211_mgmt_tx_params *params, +#endif + u64 *cookie) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0)) + struct net_device *ndev = wdev_to_ndev(wdev); +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) || defined(COMPAT_KERNEL_RELEASE) + struct ieee80211_channel *chan = params->chan; + bool offchan = params->offchan; + unsigned int wait = params->wait; + const u8 *buf = params->buf; + size_t len = params->len; + bool no_cck = params->no_cck; + bool dont_wait_for_ack = params->dont_wait_for_ack; +#endif + int ret = 0; + int tx_ret; + int wait_ack = 1; + u32 dump_limit = RTW_MAX_MGMT_TX_CNT; + u32 dump_cnt = 0; + bool ack = _TRUE; + u8 tx_ch; + u8 category, action; + u8 frame_styp; + int type = (-1); + u32 start = rtw_get_current_time(); + _adapter *padapter; + struct rtw_wdev_priv *pwdev_priv; + + if ((ndev == NULL) || (chan == NULL)) { + ret = -EINVAL; + goto exit; + } + + tx_ch = (u8)ieee80211_frequency_to_channel(chan->center_freq); + + padapter = (_adapter *)rtw_netdev_priv(ndev); + pwdev_priv = adapter_wdev_data(padapter); + + /* cookie generation */ + *cookie = (unsigned long) buf; + +#ifdef CONFIG_DEBUG_CFG80211 + DBG_871X(FUNC_ADPT_FMT" len=%zu, ch=%d" + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0)) + ", ch_type=%d" + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) + ", channel_type_valid=%d" + #endif + #endif + "\n", FUNC_ADPT_ARG(padapter), + len, tx_ch + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0)) + , channel_type + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) + , channel_type_valid + #endif + #endif + ); +#endif /* CONFIG_DEBUG_CFG80211 */ + + /* indicate ack before issue frame to avoid racing with rsp frame */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) + rtw_cfg80211_mgmt_tx_status(padapter, *cookie, buf, len, ack, GFP_KERNEL); +#elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,34) && LINUX_VERSION_CODE<=KERNEL_VERSION(2,6,35)) + cfg80211_action_tx_status(ndev, *cookie, buf, len, ack, GFP_KERNEL); +#endif + + frame_styp = le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)buf)->frame_ctl) & IEEE80211_FCTL_STYPE; + if (IEEE80211_STYPE_PROBE_RESP == frame_styp) { +#ifdef CONFIG_DEBUG_CFG80211 + DBG_8192C("RTW_Tx: probe_resp tx_ch=%d, da="MAC_FMT"\n", tx_ch, MAC_ARG(GetAddr1Ptr(buf))); +#endif /* CONFIG_DEBUG_CFG80211 */ + wait_ack = 0; + goto dump; + } + + if (rtw_action_frame_parse(buf, len, &category, &action) == _FALSE) { + DBG_8192C(FUNC_ADPT_FMT" frame_control:0x%x\n", FUNC_ADPT_ARG(padapter), + le16_to_cpu(((struct rtw_ieee80211_hdr_3addr *)buf)->frame_ctl)); + goto exit; + } + + DBG_8192C("RTW_Tx:tx_ch=%d, da="MAC_FMT"\n", tx_ch, MAC_ARG(GetAddr1Ptr(buf))); + #ifdef CONFIG_P2P + if((type = rtw_p2p_check_frames(padapter, buf, len, _TRUE)) >= 0) { + goto dump; + } + #endif + if (category == RTW_WLAN_CATEGORY_PUBLIC) + DBG_871X("RTW_Tx:%s\n", action_public_str(action)); + else + DBG_871X("RTW_Tx:category(%u), action(%u)\n", category, action); + +dump: + + rtw_ps_deny(padapter, PS_DENY_MGNT_TX); + if(_FAIL == rtw_pwr_wakeup(padapter)) { + ret = -EFAULT; + goto cancel_ps_deny; + } + + while (1) { + u32 sleep_ms = 0; + u32 retry_guarantee_ms = 0; + + dump_cnt++; + tx_ret = _cfg80211_rtw_mgmt_tx(padapter, tx_ch, buf, len, wait_ack); + + switch (action) { + case ACT_PUBLIC_GAS_INITIAL_REQ: + case ACT_PUBLIC_GAS_INITIAL_RSP: + sleep_ms = 50; + retry_guarantee_ms = RTW_MAX_MGMT_TX_MS_GAS; + } + + if (tx_ret == _SUCCESS + || (dump_cnt >= dump_limit && rtw_get_passing_time_ms(start) >= retry_guarantee_ms)) + break; + + if (sleep_ms > 0) + rtw_msleep_os(sleep_ms); + } + + if (tx_ret != _SUCCESS || dump_cnt > 1) { + DBG_871X(FUNC_ADPT_FMT" %s (%d/%d) in %d ms\n", FUNC_ADPT_ARG(padapter), + tx_ret==_SUCCESS?"OK":"FAIL", dump_cnt, dump_limit, rtw_get_passing_time_ms(start)); + } + + switch (type) { + case P2P_GO_NEGO_CONF: + rtw_clear_scan_deny(padapter); + break; + case P2P_INVIT_RESP: + if (pwdev_priv->invit_info.flags & BIT(0) + && pwdev_priv->invit_info.status == 0) + { + DBG_871X(FUNC_ADPT_FMT" agree with invitation of persistent group\n", + FUNC_ADPT_ARG(padapter)); + rtw_set_scan_deny(padapter, 5000); + rtw_pwr_wakeup_ex(padapter, 5000); + rtw_clear_scan_deny(padapter); + } + break; + } + +cancel_ps_deny: + rtw_ps_deny_cancel(padapter, PS_DENY_MGNT_TX); +exit: + return ret; +} + +static void cfg80211_rtw_mgmt_frame_register(struct wiphy *wiphy, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + struct wireless_dev *wdev, +#else + struct net_device *ndev, +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0)) + struct mgmt_frame_regs *upd) +#else + u16 frame_type, bool reg) +#endif +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6 ,0)) + struct net_device *ndev = wdev_to_ndev(wdev); +#endif + _adapter *adapter; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0)) + u16 frame_type = BIT(upd->global_stypes << 4); + bool reg = false; +#endif + + struct rtw_wdev_priv *pwdev_priv; + + if (ndev == NULL) + goto exit; + + adapter = (_adapter *)rtw_netdev_priv(ndev); + pwdev_priv = adapter_wdev_data(adapter); + +#ifdef CONFIG_DEBUG_CFG80211 + DBG_871X(FUNC_ADPT_FMT" frame_type:%x, reg:%d\n", FUNC_ADPT_ARG(adapter), + frame_type, reg); +#endif + + /* Wait QC Verify */ + return; + + switch (frame_type) { + case IEEE80211_STYPE_PROBE_REQ: /* 0x0040 */ + SET_CFG80211_REPORT_MGMT(pwdev_priv, IEEE80211_STYPE_PROBE_REQ, reg); + break; + case IEEE80211_STYPE_ACTION: /* 0x00D0 */ + SET_CFG80211_REPORT_MGMT(pwdev_priv, IEEE80211_STYPE_ACTION, reg); + break; + default: + break; + } + +exit: + return; +} + +#if defined(CONFIG_TDLS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0)) +static int cfg80211_rtw_tdls_mgmt(struct wiphy *wiphy, + struct net_device *ndev, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) + const u8 *peer, +#else + u8 *peer, +#endif + u8 action_code, + u8 dialog_token, + u16 status_code, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 15, 0)) + u32 peer_capability, +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 17, 0)) + bool initiator, +#endif + const u8 *buf, + size_t len) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; + int ret = 0; + struct tdls_txmgmt txmgmt; + + if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) { + DBG_871X("Discard tdls action:%d, since hal doesn't support tdls\n", action_code); + goto discard; + } + + if (rtw_tdls_is_driver_setup(padapter)) { + DBG_871X("Discard tdls action:%d, let driver to set up direct link\n", action_code); + goto discard; + } + + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); + _rtw_memcpy(txmgmt.peer, peer, ETH_ALEN); + txmgmt.action_code = action_code; + txmgmt.dialog_token= dialog_token; + txmgmt.status_code = status_code; + txmgmt.len = len; + txmgmt.buf = (u8 *)rtw_malloc(txmgmt.len); + if (txmgmt.buf == NULL) { + ret = -ENOMEM; + goto bad; + } + _rtw_memcpy(txmgmt.buf, (void*)buf, txmgmt.len); + +/* Debug purpose */ +#if 1 + DBG_871X("%s %d\n", __FUNCTION__, __LINE__); + DBG_871X("peer:"MAC_FMT", action code:%d, dialog:%d, status code:%d\n", + MAC_ARG(txmgmt.peer), txmgmt.action_code, + txmgmt.dialog_token, txmgmt.status_code); + if (txmgmt.len > 0) { + int i=0; + for(;i < len; i++) + printk("%02x ", *(txmgmt.buf+i)); + DBG_871X("len:%d\n", (u32)txmgmt.len); + } +#endif + + switch (txmgmt.action_code) { + case TDLS_SETUP_REQUEST: + issue_tdls_setup_req(padapter, &txmgmt, _TRUE); + break; + case TDLS_SETUP_RESPONSE: + issue_tdls_setup_rsp(padapter, &txmgmt); + break; + case TDLS_SETUP_CONFIRM: + issue_tdls_setup_cfm(padapter, &txmgmt); + break; + case TDLS_TEARDOWN: + issue_tdls_teardown(padapter, &txmgmt, _TRUE); + break; + case TDLS_DISCOVERY_REQUEST: + issue_tdls_dis_req(padapter, &txmgmt); + break; + case TDLS_DISCOVERY_RESPONSE: + issue_tdls_dis_rsp(padapter, &txmgmt, pmlmeinfo->enc_algo? _TRUE : _FALSE); + break; + } + +bad: + if (txmgmt.buf) + rtw_mfree(txmgmt.buf, txmgmt.len); + +discard: + return ret; +} + +static int cfg80211_rtw_tdls_oper(struct wiphy *wiphy, + struct net_device *ndev, +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 16, 0)) + const u8 *peer, +#else + u8 *peer, +#endif + enum nl80211_tdls_operation oper) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + struct tdls_txmgmt txmgmt; + struct sta_info *ptdls_sta = NULL; + + DBG_871X(FUNC_NDEV_FMT", nl80211_tdls_operation:%d\n", FUNC_NDEV_ARG(ndev), oper); + + if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) { + DBG_871X("Discard tdls oper:%d, since hal doesn't support tdls\n", oper); + return 0; + } + +#ifdef CONFIG_LPS + rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_LEAVE, 1); +#endif //CONFIG_LPS + + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); + if (peer) + _rtw_memcpy(txmgmt.peer, peer, ETH_ALEN); + + if (rtw_tdls_is_driver_setup(padapter)) { + /* these two cases are done by driver itself */ + if (oper == NL80211_TDLS_ENABLE_LINK || oper == NL80211_TDLS_DISABLE_LINK) + return 0; + } + + switch (oper) { + case NL80211_TDLS_DISCOVERY_REQ: + issue_tdls_dis_req(padapter, &txmgmt); + break; + case NL80211_TDLS_SETUP: +#ifdef CONFIG_WFD + if ( _AES_ != padapter->securitypriv.dot11PrivacyAlgrthm ) { + if ( padapter->wdinfo.wfd_tdls_weaksec == _TRUE) + issue_tdls_setup_req(padapter, &txmgmt, _TRUE); + else + DBG_871X( "[%s] Current link is not AES, SKIP sending the tdls setup request!!\n", __FUNCTION__ ); + } else +#endif // CONFIG_WFD + { + issue_tdls_setup_req(padapter, &txmgmt, _TRUE); + } + break; + case NL80211_TDLS_TEARDOWN: + ptdls_sta = rtw_get_stainfo( &(padapter->stapriv), txmgmt.peer); + if (ptdls_sta != NULL) { + txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_; + issue_tdls_teardown(padapter, &txmgmt, _TRUE); + }else { + DBG_871X( "TDLS peer not found\n"); + } + break; + case NL80211_TDLS_ENABLE_LINK: + DBG_871X(FUNC_NDEV_FMT", NL80211_TDLS_ENABLE_LINK;mac:"MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(peer)); + ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), (u8 *)peer); + if (ptdls_sta != NULL) { + ptdlsinfo->link_established = _TRUE; + ptdls_sta->tdls_sta_state |= TDLS_LINKED_STATE; + ptdls_sta->state |= _FW_LINKED; + rtw_tdls_cmd(padapter, txmgmt.peer, TDLS_ESTABLISHED); + } + break; + case NL80211_TDLS_DISABLE_LINK: + DBG_871X(FUNC_NDEV_FMT", NL80211_TDLS_DISABLE_LINK;mac:"MAC_FMT"\n", FUNC_NDEV_ARG(ndev), MAC_ARG(peer)); + ptdls_sta = rtw_get_stainfo(&(padapter->stapriv), (u8 *)peer); + if (ptdls_sta != NULL) { + rtw_tdls_cmd(padapter, (u8 *)peer, TDLS_TEARDOWN_STA_LOCALLY); + } + break; + } + return 0; +} +#endif /* CONFIG_TDLS */ + +#if defined(CONFIG_PNO_SUPPORT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)) +static int cfg80211_rtw_sched_scan_start(struct wiphy *wiphy, + struct net_device *dev, + struct cfg80211_sched_scan_request *request) { + + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u8 ret; + + if (padapter->bup == _FALSE) { + DBG_871X("%s: net device is down.\n", __func__); + return -EIO; + } + + if(check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE || + check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE || + check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) { + DBG_871X("%s: device is busy.\n", __func__); + rtw_scan_abort(padapter); + } + + if (request == NULL) { + DBG_871X("%s: invalid cfg80211_requests parameters.\n", __func__); + return -EINVAL; + } + + ret = rtw_android_cfg80211_pno_setup(dev, request->ssids, + request->n_ssids, request->interval); + + if (ret < 0) { + DBG_871X("%s ret: %d\n", __func__, ret); + goto exit; + } + + ret = rtw_android_pno_enable(dev, _TRUE); + if (ret < 0) { + DBG_871X("%s ret: %d\n", __func__, ret); + goto exit; + } +exit: + return ret; +} + +static int cfg80211_rtw_sched_scan_stop(struct wiphy *wiphy, + struct net_device *dev) { + return rtw_android_pno_enable(dev, _FALSE); +} +#endif /* CONFIG_PNO_SUPPORT */ + +static int rtw_cfg80211_set_beacon_wpsp2pie(struct net_device *ndev, char *buf, int len) +{ + int ret = 0; + uint wps_ielen = 0; + u8 *wps_ie; + u32 p2p_ielen = 0; + u8 wps_oui[8]={0x0,0x50,0xf2,0x04}; + u8 *p2p_ie; + u32 wfd_ielen = 0; + u8 *wfd_ie; + _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + + DBG_871X(FUNC_NDEV_FMT" ielen=%d\n", FUNC_NDEV_ARG(ndev), len); + + if(len>0) + { + if((wps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen))) + { + #ifdef CONFIG_DEBUG_CFG80211 + DBG_8192C("bcn_wps_ielen=%d\n", wps_ielen); + #endif + + if(pmlmepriv->wps_beacon_ie) + { + u32 free_len = pmlmepriv->wps_beacon_ie_len; + pmlmepriv->wps_beacon_ie_len = 0; + rtw_mfree(pmlmepriv->wps_beacon_ie, free_len); + pmlmepriv->wps_beacon_ie = NULL; + } + + pmlmepriv->wps_beacon_ie = rtw_malloc(wps_ielen); + if ( pmlmepriv->wps_beacon_ie == NULL) { + DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + return -EINVAL; + + } + + _rtw_memcpy(pmlmepriv->wps_beacon_ie, wps_ie, wps_ielen); + pmlmepriv->wps_beacon_ie_len = wps_ielen; + + update_beacon(padapter, _VENDOR_SPECIFIC_IE_, wps_oui, _TRUE); + + } + + //buf += wps_ielen; + //len -= wps_ielen; + + #ifdef CONFIG_P2P + if((p2p_ie=rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen))) + { + #ifdef CONFIG_DEBUG_CFG80211 + DBG_8192C("bcn_p2p_ielen=%d\n", p2p_ielen); + #endif + + if(pmlmepriv->p2p_beacon_ie) + { + u32 free_len = pmlmepriv->p2p_beacon_ie_len; + pmlmepriv->p2p_beacon_ie_len = 0; + rtw_mfree(pmlmepriv->p2p_beacon_ie, free_len); + pmlmepriv->p2p_beacon_ie = NULL; + } + + pmlmepriv->p2p_beacon_ie = rtw_malloc(p2p_ielen); + if ( pmlmepriv->p2p_beacon_ie == NULL) { + DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + return -EINVAL; + + } + + _rtw_memcpy(pmlmepriv->p2p_beacon_ie, p2p_ie, p2p_ielen); + pmlmepriv->p2p_beacon_ie_len = p2p_ielen; + + } + #endif //CONFIG_P2P + + + #ifdef CONFIG_WFD + wfd_ie = rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen); + if (wfd_ie) { + #ifdef CONFIG_DEBUG_CFG80211 + DBG_8192C("bcn_wfd_ielen=%d\n", wfd_ielen); + #endif + + if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_BEACON_IE, wfd_ie, wfd_ielen) != _SUCCESS) + return -EINVAL; + } + #endif /* CONFIG_WFD */ + + pmlmeext->bstart_bss = _TRUE; + + } + + return ret; + +} + +static int rtw_cfg80211_set_probe_resp_wpsp2pie(struct net_device *net, char *buf, int len) +{ + int ret = 0; + uint wps_ielen = 0; + u8 *wps_ie; + u32 p2p_ielen = 0; + u8 *p2p_ie; + u32 wfd_ielen = 0; + u8 *wfd_ie; + _adapter *padapter = (_adapter *)rtw_netdev_priv(net); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + +#ifdef CONFIG_DEBUG_CFG80211 + DBG_8192C("%s, ielen=%d\n", __func__, len); +#endif + + if(len>0) + { + if((wps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen))) + { + uint attr_contentlen = 0; + u16 uconfig_method, *puconfig_method = NULL; + + #ifdef CONFIG_DEBUG_CFG80211 + DBG_8192C("probe_resp_wps_ielen=%d\n", wps_ielen); + #endif + + if(check_fwstate(pmlmepriv, WIFI_UNDER_WPS)) + { + u8 sr = 0; + rtw_get_wps_attr_content(wps_ie, wps_ielen, WPS_ATTR_SELECTED_REGISTRAR, (u8*)(&sr), NULL); + + if (sr != 0) + { + DBG_871X("%s, got sr\n", __func__); + } + else + { + DBG_8192C("GO mode process WPS under site-survey, sr no set\n"); + return ret; + } + } + + if(pmlmepriv->wps_probe_resp_ie) + { + u32 free_len = pmlmepriv->wps_probe_resp_ie_len; + pmlmepriv->wps_probe_resp_ie_len = 0; + rtw_mfree(pmlmepriv->wps_probe_resp_ie, free_len); + pmlmepriv->wps_probe_resp_ie = NULL; + } + + pmlmepriv->wps_probe_resp_ie = rtw_malloc(wps_ielen); + if ( pmlmepriv->wps_probe_resp_ie == NULL) { + DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + return -EINVAL; + + } + + //add PUSH_BUTTON config_method by driver self in wpsie of probe_resp at GO Mode + if ( (puconfig_method = (u16*)rtw_get_wps_attr_content( wps_ie, wps_ielen, WPS_ATTR_CONF_METHOD , NULL, &attr_contentlen)) != NULL ) + { + //struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct wireless_dev *wdev = padapter->rtw_wdev; + + #ifdef CONFIG_DEBUG_CFG80211 + //printk("config_method in wpsie of probe_resp = 0x%x\n", be16_to_cpu(*puconfig_method)); + #endif + + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) + /* for WIFI-DIRECT LOGO 4.2.2, AUTO GO can't set PUSH_BUTTON flags */ + if (wdev->iftype == NL80211_IFTYPE_P2P_GO) { + uconfig_method = WPS_CM_PUSH_BUTTON; + uconfig_method = cpu_to_be16(uconfig_method); + + *puconfig_method &= ~uconfig_method; + } + #endif + } + + _rtw_memcpy(pmlmepriv->wps_probe_resp_ie, wps_ie, wps_ielen); + pmlmepriv->wps_probe_resp_ie_len = wps_ielen; + + } + + //buf += wps_ielen; + //len -= wps_ielen; + + #ifdef CONFIG_P2P + if((p2p_ie=rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen))) + { + u8 is_GO = _FALSE; + u32 attr_contentlen = 0; + u16 cap_attr=0; + + #ifdef CONFIG_DEBUG_CFG80211 + DBG_8192C("probe_resp_p2p_ielen=%d\n", p2p_ielen); + #endif + + //Check P2P Capability ATTR + if( rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8*)&cap_attr, (uint*) &attr_contentlen) ) + { + u8 grp_cap=0; + //DBG_8192C( "[%s] Got P2P Capability Attr!!\n", __FUNCTION__ ); + cap_attr = le16_to_cpu(cap_attr); + grp_cap = (u8)((cap_attr >> 8)&0xff); + + is_GO = (grp_cap&BIT(0)) ? _TRUE:_FALSE; + + if(is_GO) + DBG_8192C("Got P2P Capability Attr, grp_cap=0x%x, is_GO\n", grp_cap); + } + + + if(is_GO == _FALSE) + { + if(pmlmepriv->p2p_probe_resp_ie) + { + u32 free_len = pmlmepriv->p2p_probe_resp_ie_len; + pmlmepriv->p2p_probe_resp_ie_len = 0; + rtw_mfree(pmlmepriv->p2p_probe_resp_ie, free_len); + pmlmepriv->p2p_probe_resp_ie = NULL; + } + + pmlmepriv->p2p_probe_resp_ie = rtw_malloc(p2p_ielen); + if ( pmlmepriv->p2p_probe_resp_ie == NULL) { + DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + return -EINVAL; + + } + _rtw_memcpy(pmlmepriv->p2p_probe_resp_ie, p2p_ie, p2p_ielen); + pmlmepriv->p2p_probe_resp_ie_len = p2p_ielen; + } + else + { + if(pmlmepriv->p2p_go_probe_resp_ie) + { + u32 free_len = pmlmepriv->p2p_go_probe_resp_ie_len; + pmlmepriv->p2p_go_probe_resp_ie_len = 0; + rtw_mfree(pmlmepriv->p2p_go_probe_resp_ie, free_len); + pmlmepriv->p2p_go_probe_resp_ie = NULL; + } + + pmlmepriv->p2p_go_probe_resp_ie = rtw_malloc(p2p_ielen); + if ( pmlmepriv->p2p_go_probe_resp_ie == NULL) { + DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + return -EINVAL; + + } + _rtw_memcpy(pmlmepriv->p2p_go_probe_resp_ie, p2p_ie, p2p_ielen); + pmlmepriv->p2p_go_probe_resp_ie_len = p2p_ielen; + } + + } + #endif //CONFIG_P2P + + + #ifdef CONFIG_WFD + wfd_ie = rtw_get_wfd_ie(buf, len, NULL, &wfd_ielen); + if (wfd_ie) { + #ifdef CONFIG_DEBUG_CFG80211 + DBG_8192C("probe_resp_wfd_ielen=%d\n", wfd_ielen); + #endif + + if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_PROBE_RESP_IE, wfd_ie, wfd_ielen) != _SUCCESS) + return -EINVAL; + } + #endif /* CONFIG_WFD */ + + } + + return ret; + +} + +static int rtw_cfg80211_set_assoc_resp_wpsp2pie(struct net_device *net, char *buf, int len) +{ + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(net); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u8 *ie; + u32 ie_len; + + DBG_8192C("%s, ielen=%d\n", __func__, len); + + if (len <= 0) + goto exit; + + ie = rtw_get_wps_ie(buf, len, NULL, &ie_len); + if (ie && ie_len) { + if (pmlmepriv->wps_assoc_resp_ie) { + u32 free_len = pmlmepriv->wps_assoc_resp_ie_len; + + pmlmepriv->wps_assoc_resp_ie_len = 0; + rtw_mfree(pmlmepriv->wps_assoc_resp_ie, free_len); + pmlmepriv->wps_assoc_resp_ie = NULL; + } + + pmlmepriv->wps_assoc_resp_ie = rtw_malloc(ie_len); + if (pmlmepriv->wps_assoc_resp_ie == NULL) { + DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + return -EINVAL; + } + _rtw_memcpy(pmlmepriv->wps_assoc_resp_ie, ie, ie_len); + pmlmepriv->wps_assoc_resp_ie_len = ie_len; + } + + ie = rtw_get_p2p_ie(buf, len, NULL, &ie_len); + if (ie && ie_len) { + if (pmlmepriv->p2p_assoc_resp_ie) { + u32 free_len = pmlmepriv->p2p_assoc_resp_ie_len; + + pmlmepriv->p2p_assoc_resp_ie_len = 0; + rtw_mfree(pmlmepriv->p2p_assoc_resp_ie, free_len); + pmlmepriv->p2p_assoc_resp_ie = NULL; + } + + pmlmepriv->p2p_assoc_resp_ie = rtw_malloc(ie_len); + if (pmlmepriv->p2p_assoc_resp_ie == NULL) { + DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + return -EINVAL; + } + _rtw_memcpy(pmlmepriv->p2p_assoc_resp_ie, ie, ie_len); + pmlmepriv->p2p_assoc_resp_ie_len = ie_len; + } + +#ifdef CONFIG_WFD + ie = rtw_get_wfd_ie(buf, len, NULL, &ie_len); + if (rtw_mlme_update_wfd_ie_data(pmlmepriv, MLME_ASSOC_RESP_IE, ie, ie_len) != _SUCCESS) + return -EINVAL; +#endif + +exit: + return ret; +} + +int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, + int type) +{ + int ret = 0; + uint wps_ielen = 0; + u32 p2p_ielen = 0; + +#ifdef CONFIG_DEBUG_CFG80211 + DBG_8192C("%s, ielen=%d\n", __func__, len); +#endif + + if( (rtw_get_wps_ie(buf, len, NULL, &wps_ielen) && (wps_ielen>0)) + #ifdef CONFIG_P2P + || (rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen) && (p2p_ielen>0)) + #endif + ) + { + if (net != NULL) + { + switch (type) + { + case 0x1: //BEACON + ret = rtw_cfg80211_set_beacon_wpsp2pie(net, buf, len); + break; + case 0x2: //PROBE_RESP + ret = rtw_cfg80211_set_probe_resp_wpsp2pie(net, buf, len); + break; + case 0x4: //ASSOC_RESP + ret = rtw_cfg80211_set_assoc_resp_wpsp2pie(net, buf, len); + break; + } + } + } + + return ret; + +} + +static void rtw_cfg80211_init_ht_capab_ex(_adapter *padapter, struct ieee80211_sta_ht_cap *ht_cap, enum ieee80211_band band, u8 rf_type) +{ + struct registry_priv *pregistrypriv = &padapter->registrypriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct ht_priv *phtpriv = &pmlmepriv->htpriv; + u8 stbc_rx_enable = _FALSE; + + rtw_ht_use_default_setting(padapter); + + /* RX LDPC */ + if (TEST_FLAG(phtpriv->ldpc_cap, LDPC_HT_ENABLE_RX)) + ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; + + /* TX STBC */ + if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_TX)) + ht_cap->cap |= IEEE80211_HT_CAP_TX_STBC; + + /* RX STBC */ + if (TEST_FLAG(phtpriv->stbc_cap, STBC_HT_ENABLE_RX)) { + /*rtw_rx_stbc 0: disable, bit(0):enable 2.4g, bit(1):enable 5g*/ + if (IEEE80211_BAND_2GHZ == band) + stbc_rx_enable = (pregistrypriv->rx_stbc & BIT(0))?_TRUE:_FALSE; + if (IEEE80211_BAND_5GHZ == band) + stbc_rx_enable = (pregistrypriv->rx_stbc & BIT(1))?_TRUE:_FALSE; + + if (stbc_rx_enable) { + switch (rf_type) { + case RF_1T1R: + ht_cap->cap |= IEEE80211_HT_CAP_RX_STBC_1R;/*RX STBC One spatial stream*/ + break; + + case RF_2T2R: + case RF_1T2R: + ht_cap->cap |= IEEE80211_HT_CAP_RX_STBC_1R;/* Only one spatial-stream STBC RX is supported */ + break; + case RF_3T3R: + case RF_3T4R: + case RF_4T4R: + ht_cap->cap |= IEEE80211_HT_CAP_RX_STBC_1R;/* Only one spatial-stream STBC RX is supported */ + break; + default: + DBG_871X("[warning] rf_type %d is not expected\n", rf_type); + break; + } + } + } +} + +static void rtw_cfg80211_init_ht_capab(_adapter *padapter, struct ieee80211_sta_ht_cap *ht_cap, enum ieee80211_band band, u8 rf_type) +{ +#define MAX_BIT_RATE_40MHZ_MCS23 450 /* Mbps */ +#define MAX_BIT_RATE_40MHZ_MCS15 300 /* Mbps */ +#define MAX_BIT_RATE_40MHZ_MCS7 150 /* Mbps */ + + ht_cap->ht_supported = _TRUE; + + ht_cap->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | + IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20 | + IEEE80211_HT_CAP_DSSSCCK40 | IEEE80211_HT_CAP_MAX_AMSDU; + rtw_cfg80211_init_ht_capab_ex(padapter, ht_cap, band, rf_type); + + /* + *Maximum length of AMPDU that the STA can receive. + *Length = 2 ^ (13 + max_ampdu_length_exp) - 1 (octets) + */ + ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; + + /*Minimum MPDU start spacing , */ + ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_16; + + ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; + + /* + *hw->wiphy->bands[IEEE80211_BAND_2GHZ] + *base on ant_num + *rx_mask: RX mask + *if rx_ant =1 rx_mask[0]=0xff;==>MCS0-MCS7 + *if rx_ant =2 rx_mask[1]=0xff;==>MCS8-MCS15 + *if rx_ant >=3 rx_mask[2]=0xff; + *if BW_40 rx_mask[4]=0x01; + *highest supported RX rate + */ + if (rf_type == RF_1T1R) { + ht_cap->mcs.rx_mask[0] = 0xFF; + + ht_cap->mcs.rx_highest = MAX_BIT_RATE_40MHZ_MCS7; + } else if ((rf_type == RF_1T2R) || (rf_type == RF_2T2R) || (rf_type == RF_2T2R_GREEN)) { + ht_cap->mcs.rx_mask[0] = 0xFF; + ht_cap->mcs.rx_mask[1] = 0xFF; + + ht_cap->mcs.rx_highest = MAX_BIT_RATE_40MHZ_MCS15; + } else if ((rf_type == RF_2T3R) || (rf_type == RF_3T3R)) { + ht_cap->mcs.rx_mask[0] = 0xFF; + ht_cap->mcs.rx_mask[1] = 0xFF; + ht_cap->mcs.rx_mask[2] = 0xFF; + + ht_cap->mcs.rx_highest = MAX_BIT_RATE_40MHZ_MCS23; + } else { + rtw_warn_on(1); + DBG_8192C("%s, error rf_type=%d\n", __func__, rf_type); + } + +} + +void rtw_cfg80211_init_wiphy(_adapter *padapter) +{ + u8 rf_type; + struct ieee80211_supported_band *bands; + struct wireless_dev *pwdev = padapter->rtw_wdev; + struct wiphy *wiphy = pwdev->wiphy; + + rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); + + DBG_8192C("%s:rf_type=%d\n", __func__, rf_type); + + if (IsSupported24G(padapter->registrypriv.wireless_mode)) { + bands = wiphy->bands[IEEE80211_BAND_2GHZ]; + if(bands) + rtw_cfg80211_init_ht_capab(padapter, &bands->ht_cap, IEEE80211_BAND_2GHZ, rf_type); + } +#ifdef CONFIG_IEEE80211_BAND_5GHZ + if (IsSupported5G(padapter->registrypriv.wireless_mode)) { + bands = wiphy->bands[IEEE80211_BAND_5GHZ]; + if(bands) + rtw_cfg80211_init_ht_capab(padapter, &bands->ht_cap, IEEE80211_BAND_5GHZ, rf_type); + } +#endif + + /* copy mac_addr to wiphy */ + _rtw_memcpy(wiphy->perm_addr, adapter_mac_addr(padapter), ETH_ALEN); + +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) +struct ieee80211_iface_limit rtw_limits[] = { + { .max = 2, + .types = BIT(NL80211_IFTYPE_STATION) + #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) + | BIT(NL80211_IFTYPE_P2P_CLIENT) + #endif + }, + #ifdef CONFIG_AP_MODE + { .max = 1, + .types = BIT(NL80211_IFTYPE_AP) + #if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 37)) || defined(COMPAT_KERNEL_RELEASE)) + | BIT(NL80211_IFTYPE_P2P_GO) + #endif + }, + #endif +}; + +struct ieee80211_iface_combination rtw_combinations[] = { + { .limits = rtw_limits, + .n_limits = ARRAY_SIZE(rtw_limits), + .max_interfaces = 2, + .num_different_channels = 1, + }, +}; +#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) */ + +static void rtw_cfg80211_preinit_wiphy(_adapter *adapter, struct wiphy *wiphy) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct registry_priv *regsty = dvobj_to_regsty(dvobj); + + wiphy->signal_type = CFG80211_SIGNAL_TYPE_MBM; + + wiphy->max_scan_ssids = RTW_SSID_SCAN_AMOUNT; + wiphy->max_scan_ie_len = RTW_SCAN_IE_LEN_MAX; + wiphy->max_num_pmkids = RTW_MAX_NUM_PMKIDS; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) || defined(COMPAT_KERNEL_RELEASE) + wiphy->max_remain_on_channel_duration = RTW_MAX_REMAIN_ON_CHANNEL_DURATION; +#endif + + wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) + | BIT(NL80211_IFTYPE_ADHOC) +#ifdef CONFIG_AP_MODE + | BIT(NL80211_IFTYPE_AP) + #ifdef CONFIG_WIFI_MONITOR + | BIT(NL80211_IFTYPE_MONITOR) + #endif +#endif +#if defined(CONFIG_P2P) && ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE)) + | BIT(NL80211_IFTYPE_P2P_CLIENT) + | BIT(NL80211_IFTYPE_P2P_GO) +#endif + ; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) +#ifdef CONFIG_AP_MODE + wiphy->mgmt_stypes = rtw_cfg80211_default_mgmt_stypes; +#endif //CONFIG_AP_MODE +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)) + #ifdef CONFIG_WIFI_MONITOR + wiphy->software_iftypes |= BIT(NL80211_IFTYPE_MONITOR); + #endif +#endif + + #if defined(RTW_SINGLE_WIPHY) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) + wiphy->iface_combinations = rtw_combinations; + wiphy->n_iface_combinations = ARRAY_SIZE(rtw_combinations); + #endif + + wiphy->cipher_suites = rtw_cipher_suites; + wiphy->n_cipher_suites = ARRAY_SIZE(rtw_cipher_suites); + + if (IsSupported24G(adapter->registrypriv.wireless_mode)) + wiphy->bands[IEEE80211_BAND_2GHZ] = rtw_spt_band_alloc(IEEE80211_BAND_2GHZ); + +#ifdef CONFIG_IEEE80211_BAND_5GHZ + if (IsSupported5G(adapter->registrypriv.wireless_mode)) + wiphy->bands[IEEE80211_BAND_5GHZ] = rtw_spt_band_alloc(IEEE80211_BAND_5GHZ); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38) && LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0)) + wiphy->flags |= WIPHY_FLAG_SUPPORTS_SEPARATE_DEFAULT_KEYS; +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,3,0)) + wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL; + wiphy->flags |= WIPHY_FLAG_HAVE_AP_SME; + /* remove WIPHY_FLAG_OFFCHAN_TX, because we not support this feature */ + /* wiphy->flags |= WIPHY_FLAG_OFFCHAN_TX | WIPHY_FLAG_HAVE_AP_SME; */ +#endif + +#if defined(CONFIG_PM) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,12,0)) + wiphy->max_sched_scan_reqs = 1; +#else + wiphy->flags |= WIPHY_FLAG_SUPPORTS_SCHED_SCAN; +#endif +#ifdef CONFIG_PNO_SUPPORT + wiphy->max_sched_scan_ssids = MAX_PNO_LIST_COUNT; +#endif +#endif + +#if defined(CONFIG_PM) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)) +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,11,0)) + wiphy->wowlan = wowlan_stub; +#else + wiphy->wowlan = &wowlan_stub; +#endif +#endif + +#if defined(CONFIG_TDLS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0)) + wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS; +#ifndef CONFIG_TDLS_DRIVER_SETUP + wiphy->flags |= WIPHY_FLAG_TDLS_EXTERNAL_SETUP; //Driver handles key exchange + wiphy->flags |= NL80211_ATTR_HT_CAPABILITY; +#endif //CONFIG_TDLS_DRIVER_SETUP +#endif /* CONFIG_TDLS */ + + if (regsty->power_mgnt != PS_MODE_ACTIVE) + wiphy->flags |= WIPHY_FLAG_PS_ON_BY_DEFAULT; + else + wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0)) + //wiphy->flags |= WIPHY_FLAG_SUPPORTS_FW_ROAM; +#endif +} + +static struct cfg80211_ops rtw_cfg80211_ops = { + .change_virtual_intf = cfg80211_rtw_change_iface, + .add_key = cfg80211_rtw_add_key, + .get_key = cfg80211_rtw_get_key, + .del_key = cfg80211_rtw_del_key, + .set_default_key = cfg80211_rtw_set_default_key, +#if defined(CONFIG_GTK_OL) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0)) + .set_rekey_data = cfg80211_rtw_set_rekey_data, +#endif /*CONFIG_GTK_OL*/ + .get_station = cfg80211_rtw_get_station, + .scan = cfg80211_rtw_scan, + .set_wiphy_params = cfg80211_rtw_set_wiphy_params, + .connect = cfg80211_rtw_connect, + .disconnect = cfg80211_rtw_disconnect, + .join_ibss = cfg80211_rtw_join_ibss, + .leave_ibss = cfg80211_rtw_leave_ibss, + .set_tx_power = cfg80211_rtw_set_txpower, + .get_tx_power = cfg80211_rtw_get_txpower, + .set_power_mgmt = cfg80211_rtw_set_power_mgmt, + .set_pmksa = cfg80211_rtw_set_pmksa, + .del_pmksa = cfg80211_rtw_del_pmksa, + .flush_pmksa = cfg80211_rtw_flush_pmksa, + +#ifdef CONFIG_AP_MODE + .add_virtual_intf = cfg80211_rtw_add_virtual_intf, + .del_virtual_intf = cfg80211_rtw_del_virtual_intf, + + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) && !defined(COMPAT_KERNEL_RELEASE) + .add_beacon = cfg80211_rtw_add_beacon, + .set_beacon = cfg80211_rtw_set_beacon, + .del_beacon = cfg80211_rtw_del_beacon, + #else + .start_ap = cfg80211_rtw_start_ap, + .change_beacon = cfg80211_rtw_change_beacon, + .stop_ap = cfg80211_rtw_stop_ap, + #endif + + .add_station = cfg80211_rtw_add_station, + .del_station = cfg80211_rtw_del_station, + .change_station = cfg80211_rtw_change_station, + .dump_station = cfg80211_rtw_dump_station, + .change_bss = cfg80211_rtw_change_bss, + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 6, 0)) + .set_channel = cfg80211_rtw_set_channel, + #endif + //.auth = cfg80211_rtw_auth, + //.assoc = cfg80211_rtw_assoc, +#endif //CONFIG_AP_MODE + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 6, 0)) + .set_monitor_channel = cfg80211_rtw_set_monitor_channel, +#endif + +#ifdef CONFIG_P2P + .remain_on_channel = cfg80211_rtw_remain_on_channel, + .cancel_remain_on_channel = cfg80211_rtw_cancel_remain_on_channel, +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) + .mgmt_tx = cfg80211_rtw_mgmt_tx, +#elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,34) && LINUX_VERSION_CODE<=KERNEL_VERSION(2,6,35)) + .action = cfg80211_rtw_mgmt_tx, +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0)) + .update_mgmt_frame_registrations = cfg80211_rtw_mgmt_frame_register, +#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) || defined(COMPAT_KERNEL_RELEASE) + .mgmt_frame_register = cfg80211_rtw_mgmt_frame_register, +#endif + +#if defined(CONFIG_TDLS) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0)) + .tdls_mgmt = cfg80211_rtw_tdls_mgmt, + .tdls_oper = cfg80211_rtw_tdls_oper, +#endif /* CONFIG_TDLS */ + +#if defined(CONFIG_PNO_SUPPORT) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)) + .sched_scan_start = cfg80211_rtw_sched_scan_start, + .sched_scan_stop = cfg80211_rtw_sched_scan_stop, +#endif /* CONFIG_PNO_SUPPORT */ +}; + +struct wiphy *rtw_wiphy_alloc(_adapter *padapter, struct device *dev) +{ + struct wiphy *wiphy; + struct rtw_wiphy_data *wiphy_data; + + /* wiphy */ + wiphy = wiphy_new(&rtw_cfg80211_ops, sizeof(_adapter*)); + if (!wiphy) { + DBG_8192C("Couldn't allocate wiphy device\n"); + goto exit; + } + set_wiphy_dev(wiphy, dev); + *((_adapter**)wiphy_priv(wiphy)) = padapter; + + rtw_cfg80211_preinit_wiphy(padapter, wiphy); + + /* init regulary domain */ + rtw_regd_init(wiphy); + + DBG_871X(FUNC_WIPHY_FMT"\n", FUNC_WIPHY_ARG(wiphy)); + +exit: + return wiphy; +} + +void rtw_wiphy_free(struct wiphy *wiphy) +{ + if (!wiphy) + return; + + DBG_871X(FUNC_WIPHY_FMT"\n", FUNC_WIPHY_ARG(wiphy)); + + if (wiphy->bands[IEEE80211_BAND_2GHZ]) { + rtw_spt_band_free(wiphy->bands[IEEE80211_BAND_2GHZ]); + wiphy->bands[IEEE80211_BAND_2GHZ] = NULL; + } + if (wiphy->bands[IEEE80211_BAND_5GHZ]) { + rtw_spt_band_free(wiphy->bands[IEEE80211_BAND_5GHZ]); + wiphy->bands[IEEE80211_BAND_5GHZ] = NULL; + } + + wiphy_free(wiphy); +} + +int rtw_wiphy_register(struct wiphy *wiphy) +{ + DBG_871X(FUNC_WIPHY_FMT"\n", FUNC_WIPHY_ARG(wiphy)); + + return wiphy_register(wiphy); +} + +void rtw_wiphy_unregister(struct wiphy *wiphy) +{ + DBG_871X(FUNC_WIPHY_FMT"\n", FUNC_WIPHY_ARG(wiphy)); + + return wiphy_unregister(wiphy); +} + +int rtw_wdev_alloc(_adapter *padapter, struct wiphy *wiphy) +{ + int ret = 0; + struct net_device *pnetdev = padapter->pnetdev; + struct wireless_dev *wdev; + struct rtw_wdev_priv *pwdev_priv; + + DBG_8192C("%s(padapter=%p)\n", __func__, padapter); + + /* wdev */ + wdev = (struct wireless_dev *)rtw_zmalloc(sizeof(struct wireless_dev)); + if (!wdev) { + DBG_8192C("Couldn't allocate wireless device\n"); + ret = -ENOMEM; + goto exit; + } + wdev->wiphy = wiphy; + wdev->netdev = pnetdev; + + wdev->iftype = NL80211_IFTYPE_STATION; // will be init in rtw_hal_init() + // Must sync with _rtw_init_mlme_priv() + // pmlmepriv->fw_state = WIFI_STATION_STATE + //wdev->iftype = NL80211_IFTYPE_MONITOR; // for rtw_setopmode_cmd() in cfg80211_rtw_change_iface() + padapter->rtw_wdev = wdev; + pnetdev->ieee80211_ptr = wdev; + + //init pwdev_priv + pwdev_priv = adapter_wdev_data(padapter); + pwdev_priv->rtw_wdev = wdev; + pwdev_priv->pmon_ndev = NULL; + pwdev_priv->ifname_mon[0] = '\0'; + pwdev_priv->padapter = padapter; + pwdev_priv->scan_request = NULL; + _rtw_spinlock_init(&pwdev_priv->scan_req_lock); + + pwdev_priv->p2p_enabled = _FALSE; + pwdev_priv->provdisc_req_issued = _FALSE; + rtw_wdev_invit_info_init(&pwdev_priv->invit_info); + rtw_wdev_nego_info_init(&pwdev_priv->nego_info); + + pwdev_priv->bandroid_scan = _FALSE; + + if(padapter->registrypriv.power_mgnt != PS_MODE_ACTIVE) + pwdev_priv->power_mgmt = _TRUE; + else + pwdev_priv->power_mgmt = _FALSE; + +#ifdef CONFIG_CONCURRENT_MODE + ATOMIC_SET(&pwdev_priv->switch_ch_to, 1); + ATOMIC_SET(&pwdev_priv->ro_ch_to, 1); +#endif + +exit: + return ret; +} + +void rtw_wdev_free(struct wireless_dev *wdev) +{ + DBG_8192C("%s(wdev=%p)\n", __func__, wdev); + + if (!wdev) + return; + + rtw_mfree((u8*)wdev, sizeof(struct wireless_dev)); +} + +void rtw_wdev_unregister(struct wireless_dev *wdev) +{ + struct net_device *ndev; + _adapter *adapter; + struct rtw_wdev_priv *pwdev_priv; + + DBG_8192C("%s(wdev=%p)\n", __func__, wdev); + + if (!wdev) + return; + + if(!(ndev = wdev_to_ndev(wdev))) + return; + + adapter = (_adapter *)rtw_netdev_priv(ndev); + pwdev_priv = adapter_wdev_data(adapter); + + rtw_cfg80211_indicate_scan_done(adapter, _TRUE); + + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0)) + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0)) + if (wdev->links[0].client.current_bss) { + #elif (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0)) + if (wdev->connected) { + #else + if (wdev->current_bss) { + #endif + u8 locally_generated = 1; + DBG_871X(FUNC_ADPT_FMT" clear current_bss by cfg80211_disconnected\n", FUNC_ADPT_ARG(adapter)); + cfg80211_disconnected(adapter->pnetdev, 0, NULL, 0, locally_generated, GFP_ATOMIC); + } + #elif ((LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(4, 2, 0))) || defined(COMPAT_KERNEL_RELEASE) + if (wdev->current_bss) { + DBG_871X(FUNC_ADPT_FMT" clear current_bss by cfg80211_disconnected\n", FUNC_ADPT_ARG(adapter)); + cfg80211_disconnected(adapter->pnetdev, 0, NULL, 0, GFP_ATOMIC); + } + #endif + + if (pwdev_priv->pmon_ndev) { + DBG_8192C("%s, unregister monitor interface\n", __func__); + unregister_netdev(pwdev_priv->pmon_ndev); + } +} + +int rtw_cfg80211_ndev_res_alloc(_adapter *adapter) +{ + int ret = _FAIL; + +#if !defined(RTW_SINGLE_WIPHY) + struct wiphy *wiphy; + struct device *dev = dvobj_to_dev(adapter_to_dvobj(adapter)); + + wiphy = rtw_wiphy_alloc(adapter, dev); + if (wiphy == NULL) + goto exit; + + adapter->wiphy = wiphy; +#endif + + if (rtw_wdev_alloc(adapter, adapter_to_wiphy(adapter)) == 0) + ret = _SUCCESS; + +#if !defined(RTW_SINGLE_WIPHY) + if (ret != _SUCCESS) { + rtw_wiphy_free(wiphy); + adapter->wiphy = NULL; + } +#endif + +exit: + return ret; +} + +void rtw_cfg80211_ndev_res_free(_adapter *adapter) +{ + rtw_wdev_free(adapter->rtw_wdev); +#if !defined(RTW_SINGLE_WIPHY) + rtw_wiphy_free(adapter_to_wiphy(adapter)); + adapter->wiphy = NULL; +#endif +} + +int rtw_cfg80211_ndev_res_register(_adapter *adapter) +{ + int ret = _FAIL; + +#if !defined(RTW_SINGLE_WIPHY) + if (rtw_wiphy_register(adapter_to_wiphy(adapter)) < 0) { + DBG_871X("%s rtw_wiphy_register fail for if%d\n", __func__, (adapter->iface_id+1)); + goto exit; + } +#endif + + ret = _SUCCESS; + +exit: + return ret; +} + +void rtw_cfg80211_ndev_res_unregister(_adapter *adapter) +{ + rtw_wdev_unregister(adapter->rtw_wdev); +} + +int rtw_cfg80211_dev_res_alloc(struct dvobj_priv *dvobj) +{ + int ret = _FAIL; + +#if defined(RTW_SINGLE_WIPHY) + struct wiphy *wiphy; + struct device *dev = dvobj_to_dev(dvobj); + + wiphy = rtw_wiphy_alloc(dvobj->padapters[IFACE_ID0], dev); + if (wiphy == NULL) + goto exit; + + dvobj->wiphy = wiphy; +#endif + + ret = _SUCCESS; + +exit: + return ret; +} + +void rtw_cfg80211_dev_res_free(struct dvobj_priv *dvobj) +{ +#if defined(RTW_SINGLE_WIPHY) + rtw_wiphy_free(dvobj_to_wiphy(dvobj)); + dvobj->wiphy = NULL; +#endif +} + +int rtw_cfg80211_dev_res_register(struct dvobj_priv *dvobj) +{ + int ret = _FAIL; + +#if defined(RTW_SINGLE_WIPHY) + if (rtw_wiphy_register(dvobj_to_wiphy(dvobj)) != 0) + goto exit; +#endif + + ret = _SUCCESS; + +exit: + return ret; +} + +void rtw_cfg80211_dev_res_unregister(struct dvobj_priv *dvobj) +{ +#if defined(RTW_SINGLE_WIPHY) + rtw_wiphy_unregister(dvobj_to_wiphy(dvobj)); +#endif +} + +#endif /* CONFIG_IOCTL_CFG80211 */ diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/ioctl_cfg80211.h b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/ioctl_cfg80211.h new file mode 100644 index 000000000..452d2239a --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/ioctl_cfg80211.h @@ -0,0 +1,210 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __IOCTL_CFG80211_H__ +#define __IOCTL_CFG80211_H__ + + +#if defined(RTW_USE_CFG80211_STA_EVENT) + #undef CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER +#endif + +struct rtw_wdev_invit_info { + u8 state; /* 0: req, 1:rep */ + u8 peer_mac[ETH_ALEN]; + u8 active; + u8 token; + u8 flags; + u8 status; + u8 req_op_ch; + u8 rsp_op_ch; +}; + +#define rtw_wdev_invit_info_init(invit_info) \ + do { \ + (invit_info)->state = 0xff; \ + _rtw_memset((invit_info)->peer_mac, 0, ETH_ALEN); \ + (invit_info)->active = 0xff; \ + (invit_info)->token = 0; \ + (invit_info)->flags = 0x00; \ + (invit_info)->status = 0xff; \ + (invit_info)->req_op_ch = 0; \ + (invit_info)->rsp_op_ch = 0; \ + } while (0) + +struct rtw_wdev_nego_info { + u8 state; /* 0: req, 1:rep, 2:conf */ + u8 peer_mac[ETH_ALEN]; + u8 active; + u8 token; + u8 status; + u8 req_intent; + u8 req_op_ch; + u8 req_listen_ch; + u8 rsp_intent; + u8 rsp_op_ch; + u8 conf_op_ch; +}; + +#define rtw_wdev_nego_info_init(nego_info) \ + do { \ + (nego_info)->state = 0xff; \ + _rtw_memset((nego_info)->peer_mac, 0, ETH_ALEN); \ + (nego_info)->active = 0xff; \ + (nego_info)->token = 0; \ + (nego_info)->status = 0xff; \ + (nego_info)->req_intent = 0xff; \ + (nego_info)->req_op_ch = 0; \ + (nego_info)->req_listen_ch = 0; \ + (nego_info)->rsp_intent = 0xff; \ + (nego_info)->rsp_op_ch = 0; \ + (nego_info)->conf_op_ch = 0; \ + } while (0) + +struct rtw_wdev_priv +{ + struct wireless_dev *rtw_wdev; + + _adapter *padapter; + + struct cfg80211_scan_request *scan_request; + _lock scan_req_lock; + + struct net_device *pmon_ndev;//for monitor interface + char ifname_mon[IFNAMSIZ + 1]; //interface name for monitor interface + + u8 p2p_enabled; + + u8 provdisc_req_issued; + + struct rtw_wdev_invit_info invit_info; + struct rtw_wdev_nego_info nego_info; + + u8 bandroid_scan; + bool block; + bool block_scan; + bool power_mgmt; + + /* report mgmt_frame registered */ + u16 report_mgmt; + +#ifdef CONFIG_CONCURRENT_MODE + ATOMIC_T ro_ch_to; + ATOMIC_T switch_ch_to; +#endif + +}; + +#define wiphy_to_adapter(x) (*((_adapter**)wiphy_priv(x))) + +#define wdev_to_ndev(w) ((w)->netdev) +#define wdev_to_wiphy(w) ((w)->wiphy) +#define ndev_to_wdev(n) ((n)->ieee80211_ptr) + +#define WIPHY_FMT "%s" +#define WIPHY_ARG(wiphy) wiphy_name(wiphy) +#define FUNC_WIPHY_FMT "%s("WIPHY_FMT")" +#define FUNC_WIPHY_ARG(wiphy) __func__, WIPHY_ARG(wiphy) + +#define SET_CFG80211_REPORT_MGMT(w, t, v) (w->report_mgmt |= (v?BIT(t >> 4):0)) +#define GET_CFG80211_REPORT_MGMT(w, t) ((w->report_mgmt & BIT(t >> 4)) > 0) + +struct wiphy *rtw_wiphy_alloc(_adapter *padapter, struct device *dev); +void rtw_wiphy_free(struct wiphy *wiphy); +int rtw_wiphy_register(struct wiphy *wiphy); +void rtw_wiphy_unregister(struct wiphy *wiphy); + +int rtw_wdev_alloc(_adapter *padapter, struct wiphy *wiphy); +void rtw_wdev_free(struct wireless_dev *wdev); +void rtw_wdev_unregister(struct wireless_dev *wdev); + +int rtw_cfg80211_ndev_res_alloc(_adapter *adapter); +void rtw_cfg80211_ndev_res_free(_adapter *adapter); +int rtw_cfg80211_ndev_res_register(_adapter *adapter); +void rtw_cfg80211_ndev_res_unregister(_adapter *adapter); + +int rtw_cfg80211_dev_res_alloc(struct dvobj_priv *dvobj); +void rtw_cfg80211_dev_res_free(struct dvobj_priv *dvobj); +int rtw_cfg80211_dev_res_register(struct dvobj_priv *dvobj); +void rtw_cfg80211_dev_res_unregister(struct dvobj_priv *dvobj); + +void rtw_cfg80211_init_wiphy(_adapter *padapter); + +void rtw_cfg80211_unlink_bss(_adapter *padapter, struct wlan_network *pnetwork); +void rtw_cfg80211_surveydone_event_callback(_adapter *padapter); +struct cfg80211_bss *rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_network *pnetwork); +int rtw_cfg80211_check_bss(_adapter *padapter); +void rtw_cfg80211_ibss_indicate_connect(_adapter *padapter); +void rtw_cfg80211_indicate_connect(_adapter *padapter); +void rtw_cfg80211_indicate_disconnect(_adapter *padapter, u16 reason, u8 locally_generated); +void rtw_cfg80211_indicate_scan_done(_adapter *adapter, bool aborted); +u32 rtw_cfg80211_wait_scan_req_empty(_adapter *adapter, u32 timeout_ms); + +#ifdef CONFIG_AP_MODE +void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len); +void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, unsigned char *da, unsigned short reason); +#endif //CONFIG_AP_MODE + +void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len); +void rtw_cfg80211_rx_p2p_action_public(_adapter *padapter, u8 *pmgmt_frame, uint frame_len); +void rtw_cfg80211_rx_action_p2p(_adapter *padapter, u8 *pmgmt_frame, uint frame_len); +void rtw_cfg80211_rx_action(_adapter *adapter, u8 *frame, uint frame_len, const char*msg); +void rtw_cfg80211_rx_probe_request(_adapter *padapter, u8 *pmgmt_frame, uint frame_len); + +int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, int type); + +bool rtw_cfg80211_pwr_mgmt(_adapter *adapter); + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) && !defined(COMPAT_KERNEL_RELEASE) +#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->pnetdev, freq, buf, len, gfp) +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0)) +#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->pnetdev, freq, sig_dbm, buf, len, gfp) +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3,12,0)) +#define rtw_cfg80211_rx_mgmt(adapter, freq, sig_dbm, buf, len, gfp) cfg80211_rx_mgmt((adapter)->rtw_wdev, freq, sig_dbm, buf, len, gfp) +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3 , 18 , 0)) +#define rtw_cfg80211_rx_mgmt(adapter , freq , sig_dbm , buf , len , gfp) cfg80211_rx_mgmt((adapter)->rtw_wdev , freq , sig_dbm , buf , len , 0 , gfp) +#else +#define rtw_cfg80211_rx_mgmt(adapter , freq , sig_dbm , buf , len , gfp) cfg80211_rx_mgmt((adapter)->rtw_wdev , freq , sig_dbm , buf , len , 0) +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,4,0)) && !defined(COMPAT_KERNEL_RELEASE) +#define rtw_cfg80211_send_rx_assoc(adapter, bss, buf, len) cfg80211_send_rx_assoc((adapter)->pnetdev, buf, len) +#else +#define rtw_cfg80211_send_rx_assoc(adapter, bss, buf, len) cfg80211_send_rx_assoc((adapter)->pnetdev, bss, buf, len) +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0)) +#define rtw_cfg80211_mgmt_tx_status(adapter, cookie, buf, len, ack, gfp) cfg80211_mgmt_tx_status((adapter)->pnetdev, cookie, buf, len, ack, gfp) +#else +#define rtw_cfg80211_mgmt_tx_status(adapter, cookie, buf, len, ack, gfp) cfg80211_mgmt_tx_status((adapter)->rtw_wdev, cookie, buf, len, ack, gfp) +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0)) +#define rtw_cfg80211_ready_on_channel(adapter, cookie, chan, channel_type, duration, gfp) cfg80211_ready_on_channel((adapter)->pnetdev, cookie, chan, channel_type, duration, gfp) +#define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired((adapter)->pnetdev, cookie, chan, chan_type, gfp) +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(3,8,0)) +#define rtw_cfg80211_ready_on_channel(adapter, cookie, chan, channel_type, duration, gfp) cfg80211_ready_on_channel((adapter)->rtw_wdev, cookie, chan, channel_type, duration, gfp) +#define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired((adapter)->rtw_wdev, cookie, chan, chan_type, gfp) +#else +#define rtw_cfg80211_ready_on_channel(adapter, cookie, chan, channel_type, duration, gfp) cfg80211_ready_on_channel((adapter)->rtw_wdev, cookie, chan, duration, gfp) +#define rtw_cfg80211_remain_on_channel_expired(adapter, cookie, chan, chan_type, gfp) cfg80211_remain_on_channel_expired((adapter)->rtw_wdev, cookie, chan, gfp) +#endif + +#endif //__IOCTL_CFG80211_H__ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/ioctl_linux.c b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/ioctl_linux.c new file mode 100644 index 000000000..ce3833c31 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/ioctl_linux.c @@ -0,0 +1,13645 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _IOCTL_LINUX_C_ + +#include +#include +#include +#include "../../hal/phydm/phydm_precomp.h" + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27)) +#define iwe_stream_add_event(a, b, c, d, e) iwe_stream_add_event(b, c, d, e) +#define iwe_stream_add_point(a, b, c, d, e) iwe_stream_add_point(b, c, d, e) +#endif + +#ifdef CONFIG_80211N_HT +extern int rtw_ht_enable; +#endif + + +#define RTL_IOCTL_WPA_SUPPLICANT SIOCIWFIRSTPRIV+30 + +#define SCAN_ITEM_SIZE 768 +#define MAX_CUSTOM_LEN 64 +#define RATE_COUNT 4 + +#ifdef CONFIG_GLOBAL_UI_PID +extern int ui_pid[3]; +#endif + +// combo scan +#define WEXT_CSCAN_AMOUNT 9 +#define WEXT_CSCAN_BUF_LEN 360 +#define WEXT_CSCAN_HEADER "CSCAN S\x01\x00\x00S\x00" +#define WEXT_CSCAN_HEADER_SIZE 12 +#define WEXT_CSCAN_SSID_SECTION 'S' +#define WEXT_CSCAN_CHANNEL_SECTION 'C' +#define WEXT_CSCAN_NPROBE_SECTION 'N' +#define WEXT_CSCAN_ACTV_DWELL_SECTION 'A' +#define WEXT_CSCAN_PASV_DWELL_SECTION 'P' +#define WEXT_CSCAN_HOME_DWELL_SECTION 'H' +#define WEXT_CSCAN_TYPE_SECTION 'T' + + +extern u8 key_2char2num(u8 hch, u8 lch); +extern u8 str_2char2num(u8 hch, u8 lch); +extern void macstr2num(u8 *dst, u8 *src); +extern u8 convert_ip_addr(u8 hch, u8 mch, u8 lch); + +u32 rtw_rates[] = {1000000,2000000,5500000,11000000, + 6000000,9000000,12000000,18000000,24000000,36000000,48000000,54000000}; + +static const char * const iw_operation_mode[] = +{ + "Auto", "Ad-Hoc", "Managed", "Master", "Repeater", "Secondary", "Monitor" +}; + +static int hex2num_i(char c) +{ + if (c >= '0' && c <= '9') + return c - '0'; + if (c >= 'a' && c <= 'f') + return c - 'a' + 10; + if (c >= 'A' && c <= 'F') + return c - 'A' + 10; + return -1; +} + +static int hex2byte_i(const char *hex) +{ + int a, b; + a = hex2num_i(*hex++); + if (a < 0) + return -1; + b = hex2num_i(*hex++); + if (b < 0) + return -1; + return (a << 4) | b; +} + +/** + * hwaddr_aton - Convert ASCII string to MAC address + * @txt: MAC address as a string (e.g., "00:11:22:33:44:55") + * @addr: Buffer for the MAC address (ETH_ALEN = 6 bytes) + * Returns: 0 on success, -1 on failure (e.g., string not a MAC address) + */ +static int hwaddr_aton_i(const char *txt, u8 *addr) +{ + int i; + + for (i = 0; i < 6; i++) { + int a, b; + + a = hex2num_i(*txt++); + if (a < 0) + return -1; + b = hex2num_i(*txt++); + if (b < 0) + return -1; + *addr++ = (a << 4) | b; + if (i < 5 && *txt++ != ':') + return -1; + } + + return 0; +} + +static void indicate_wx_custom_event(_adapter *padapter, char *msg) +{ + u8 *buff, *p; + union iwreq_data wrqu; + + if (strlen(msg) > IW_CUSTOM_MAX) { + DBG_871X("%s strlen(msg):%zu > IW_CUSTOM_MAX:%u\n", __FUNCTION__ , strlen(msg), IW_CUSTOM_MAX); + return; + } + + buff = rtw_zmalloc(IW_CUSTOM_MAX+1); + if(!buff) + return; + + _rtw_memcpy(buff, msg, strlen(msg)); + + _rtw_memset(&wrqu,0,sizeof(wrqu)); + wrqu.data.length = strlen(msg); + + DBG_871X("%s %s\n", __FUNCTION__, buff); +#ifndef CONFIG_IOCTL_CFG80211 + wireless_send_event(padapter->pnetdev, IWEVCUSTOM, &wrqu, buff); +#endif + + rtw_mfree(buff, IW_CUSTOM_MAX+1); + +} + + +static void request_wps_pbc_event(_adapter *padapter) +{ + u8 *buff, *p; + union iwreq_data wrqu; + + + buff = rtw_malloc(IW_CUSTOM_MAX); + if(!buff) + return; + + _rtw_memset(buff, 0, IW_CUSTOM_MAX); + + p=buff; + + p+=sprintf(p, "WPS_PBC_START.request=TRUE"); + + _rtw_memset(&wrqu,0,sizeof(wrqu)); + + wrqu.data.length = p-buff; + + wrqu.data.length = (wrqu.data.lengthpnetdev, IWEVCUSTOM, &wrqu, buff); +#endif + + if(buff) + { + rtw_mfree(buff, IW_CUSTOM_MAX); + } + +} + +#ifdef CONFIG_SUPPORT_HW_WPS_PBC +void rtw_request_wps_pbc_event(_adapter *padapter) +{ +#ifdef RTK_DMP_PLATFORM +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,12)) + kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_NET_PBC); +#else + kobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_NET_PBC); +#endif +#else + + if ( padapter->pid[0] == 0 ) + { // 0 is the default value and it means the application monitors the HW PBC doesn't privde its pid to driver. + return; + } + + rtw_signal_process(padapter->pid[0], SIGUSR1); + +#endif + + rtw_led_control(padapter, LED_CTL_START_WPS_BOTTON); +} +#endif//#ifdef CONFIG_SUPPORT_HW_WPS_PBC + +void indicate_wx_scan_complete_event(_adapter *padapter) +{ + union iwreq_data wrqu; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + _rtw_memset(&wrqu, 0, sizeof(union iwreq_data)); + + //DBG_871X("+rtw_indicate_wx_scan_complete_event\n"); +#ifndef CONFIG_IOCTL_CFG80211 + wireless_send_event(padapter->pnetdev, SIOCGIWSCAN, &wrqu, NULL); +#endif +} + + +void rtw_indicate_wx_assoc_event(_adapter *padapter) +{ + union iwreq_data wrqu; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network)); + + _rtw_memset(&wrqu, 0, sizeof(union iwreq_data)); + + wrqu.ap_addr.sa_family = ARPHRD_ETHER; + + if(check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)==_TRUE ) + _rtw_memcpy(wrqu.ap_addr.sa_data, pnetwork->MacAddress, ETH_ALEN); + else + _rtw_memcpy(wrqu.ap_addr.sa_data, pmlmepriv->cur_network.network.MacAddress, ETH_ALEN); + + DBG_871X_LEVEL(_drv_always_, "assoc success\n"); +#ifndef CONFIG_IOCTL_CFG80211 + wireless_send_event(padapter->pnetdev, SIOCGIWAP, &wrqu, NULL); +#endif +} + +void rtw_indicate_wx_disassoc_event(_adapter *padapter) +{ + union iwreq_data wrqu; + + _rtw_memset(&wrqu, 0, sizeof(union iwreq_data)); + + wrqu.ap_addr.sa_family = ARPHRD_ETHER; + _rtw_memset(wrqu.ap_addr.sa_data, 0, ETH_ALEN); + +#ifndef CONFIG_IOCTL_CFG80211 + DBG_871X_LEVEL(_drv_always_, "indicate disassoc\n"); + wireless_send_event(padapter->pnetdev, SIOCGIWAP, &wrqu, NULL); +#endif +} + +/* +uint rtw_is_cckrates_included(u8 *rate) +{ + u32 i = 0; + + while(rate[i]!=0) + { + if ( (((rate[i]) & 0x7f) == 2) || (((rate[i]) & 0x7f) == 4) || + (((rate[i]) & 0x7f) == 11) || (((rate[i]) & 0x7f) == 22) ) + return _TRUE; + i++; + } + + return _FALSE; +} + +uint rtw_is_cckratesonly_included(u8 *rate) +{ + u32 i = 0; + + while(rate[i]!=0) + { + if ( (((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) && + (((rate[i]) & 0x7f) != 11) && (((rate[i]) & 0x7f) != 22) ) + return _FALSE; + i++; + } + + return _TRUE; +} +*/ + +static int search_p2p_wfd_ie(_adapter *padapter, + struct iw_request_info* info, struct wlan_network *pnetwork, + char *start, char *stop) +{ +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo = &padapter->wdinfo; +#ifdef CONFIG_WFD + if ( SCAN_RESULT_ALL == pwdinfo->wfd_info->scan_result_type ) + { + + } + else if ( ( SCAN_RESULT_P2P_ONLY == pwdinfo->wfd_info->scan_result_type ) || + ( SCAN_RESULT_WFD_TYPE == pwdinfo->wfd_info->scan_result_type ) ) +#endif // CONFIG_WFD + { + if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + { + u32 blnGotP2PIE = _FALSE; + + // User is doing the P2P device discovery + // The prefix of SSID should be "DIRECT-" and the IE should contains the P2P IE. + // If not, the driver should ignore this AP and go to the next AP. + + // Verifying the SSID + if ( _rtw_memcmp( pnetwork->network.Ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN ) ) + { + u32 p2pielen = 0; + + // Verifying the P2P IE + if (rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen)) + blnGotP2PIE = _TRUE; + } + + if ( blnGotP2PIE == _FALSE ) + { + return _FALSE; + } + + } + } + +#ifdef CONFIG_WFD + if ( SCAN_RESULT_WFD_TYPE == pwdinfo->wfd_info->scan_result_type ) + { + u32 blnGotWFD = _FALSE; + u8 *wfd_ie; + uint wfd_ielen = 0; + + wfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen); + if (wfd_ie) { + u8 *wfd_devinfo; + uint wfd_devlen; + + wfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen); + if (wfd_devinfo) { + if ( pwdinfo->wfd_info->wfd_device_type == WFD_DEVINFO_PSINK ) + { + // the first two bits will indicate the WFD device type + if ( ( wfd_devinfo[ 1 ] & 0x03 ) == WFD_DEVINFO_SOURCE ) + { + // If this device is Miracast PSink device, the scan reuslt should just provide the Miracast source. + blnGotWFD = _TRUE; + } + } + else if ( pwdinfo->wfd_info->wfd_device_type == WFD_DEVINFO_SOURCE ) + { + // the first two bits will indicate the WFD device type + if ( ( wfd_devinfo[ 1 ] & 0x03 ) == WFD_DEVINFO_PSINK ) + { + // If this device is Miracast source device, the scan reuslt should just provide the Miracast PSink. + // Todo: How about the SSink?! + blnGotWFD = _TRUE; + } + } + } + } + + if ( blnGotWFD == _FALSE ) + { + return _FALSE; + } + } +#endif // CONFIG_WFD + +#endif //CONFIG_P2P + return _TRUE; +} + static inline char *iwe_stream_mac_addr_proess(_adapter *padapter, + struct iw_request_info* info, struct wlan_network *pnetwork, + char *start, char *stop,struct iw_event *iwe) +{ + /* AP MAC address */ + iwe->cmd = SIOCGIWAP; + iwe->u.ap_addr.sa_family = ARPHRD_ETHER; + + _rtw_memcpy(iwe->u.ap_addr.sa_data, pnetwork->network.MacAddress, ETH_ALEN); + start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_ADDR_LEN); + return start; +} + static inline char * iwe_stream_essid_proess(_adapter *padapter, + struct iw_request_info* info, struct wlan_network *pnetwork, + char *start, char *stop,struct iw_event *iwe) +{ + + /* Add the ESSID */ + iwe->cmd = SIOCGIWESSID; + iwe->u.data.flags = 1; + iwe->u.data.length = min((u16)pnetwork->network.Ssid.SsidLength, (u16)32); + start = iwe_stream_add_point(info, start, stop, iwe, pnetwork->network.Ssid.Ssid); + return start; +} + + static inline char * iwe_stream_chan_process(_adapter *padapter, + struct iw_request_info* info, struct wlan_network *pnetwork, + char *start, char *stop,struct iw_event *iwe) +{ + if(pnetwork->network.Configuration.DSConfig<1 /*|| pnetwork->network.Configuration.DSConfig>14*/) + pnetwork->network.Configuration.DSConfig = 1; + + /* Add frequency/channel */ + iwe->cmd = SIOCGIWFREQ; + iwe->u.freq.m = rtw_ch2freq(pnetwork->network.Configuration.DSConfig) * 100000; + iwe->u.freq.e = 1; + iwe->u.freq.i = pnetwork->network.Configuration.DSConfig; + start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_FREQ_LEN); + return start; +} + static inline char * iwe_stream_mode_process(_adapter *padapter, + struct iw_request_info* info, struct wlan_network *pnetwork, + char *start, char *stop,struct iw_event *iwe,u16 cap) +{ + /* Add mode */ + if(cap & (WLAN_CAPABILITY_IBSS |WLAN_CAPABILITY_BSS)){ + iwe->cmd = SIOCGIWMODE; + if (cap & WLAN_CAPABILITY_BSS) + iwe->u.mode = IW_MODE_MASTER; + else + iwe->u.mode = IW_MODE_ADHOC; + + start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_UINT_LEN); + } + return start; + } + static inline char * iwe_stream_encryption_process(_adapter *padapter, + struct iw_request_info* info, struct wlan_network *pnetwork, + char *start, char *stop,struct iw_event *iwe,u16 cap) +{ + + /* Add encryption capability */ + iwe->cmd = SIOCGIWENCODE; + if (cap & WLAN_CAPABILITY_PRIVACY) + iwe->u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY; + else + iwe->u.data.flags = IW_ENCODE_DISABLED; + iwe->u.data.length = 0; + start = iwe_stream_add_point(info, start, stop, iwe, pnetwork->network.Ssid.Ssid); + return start; + +} + + static inline char * iwe_stream_protocol_process(_adapter *padapter, + struct iw_request_info* info, struct wlan_network *pnetwork, + char *start, char *stop,struct iw_event *iwe) + { + u16 ht_cap=_FALSE,vht_cap = _FALSE; + u32 ht_ielen = 0, vht_ielen = 0; + char *p; + u8 ie_offset = (pnetwork->network.Reserved[0] == 2? 0:12);// Probe Request + + //parsing HT_CAP_IE + p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], _HT_CAPABILITY_IE_, &ht_ielen, pnetwork->network.IELength-ie_offset); + if(p && ht_ielen>0) + ht_cap = _TRUE; + + #ifdef CONFIG_80211AC_VHT + //parsing VHT_CAP_IE + p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], EID_VHTCapability, &vht_ielen, pnetwork->network.IELength-ie_offset); + if(p && vht_ielen>0) + vht_cap = _TRUE; + #endif + /* Add the protocol name */ + iwe->cmd = SIOCGIWNAME; + if ((rtw_is_cckratesonly_included((u8*)&pnetwork->network.SupportedRates)) == _TRUE) + { + if(ht_cap == _TRUE) + snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11bn"); + else + snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11b"); + } + else if ((rtw_is_cckrates_included((u8*)&pnetwork->network.SupportedRates)) == _TRUE) + { + if(ht_cap == _TRUE) + snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11bgn"); + else + snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11bg"); + } + else + { + if(pnetwork->network.Configuration.DSConfig > 14) + { + #ifdef CONFIG_80211AC_VHT + if(vht_cap == _TRUE){ + snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11AC"); + } + else + #endif + { + if(ht_cap == _TRUE) + snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11an"); + else + snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11a"); + } + } + else + { + if(ht_cap == _TRUE) + snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11gn"); + else + snprintf(iwe->u.name, IFNAMSIZ, "IEEE 802.11g"); + } + } + start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_CHAR_LEN); + return start; + } + + static inline char * iwe_stream_rate_process(_adapter *padapter, + struct iw_request_info* info, struct wlan_network *pnetwork, + char *start, char *stop,struct iw_event *iwe) +{ + u32 ht_ielen = 0, vht_ielen = 0; + char *p; + u16 max_rate=0, rate, ht_cap=_FALSE, vht_cap = _FALSE; + u32 i = 0; + u8 bw_40MHz=0, short_GI=0, bw_160MHz=0, vht_highest_rate = 0; + u16 mcs_rate=0, vht_data_rate=0; + char custom[MAX_CUSTOM_LEN]={0}; + u8 ie_offset = (pnetwork->network.Reserved[0] == 2? 0:12);// Probe Request + + //parsing HT_CAP_IE + p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], _HT_CAPABILITY_IE_, &ht_ielen, pnetwork->network.IELength-ie_offset); + if(p && ht_ielen>0) + { + struct rtw_ieee80211_ht_cap *pht_capie; + ht_cap = _TRUE; + pht_capie = (struct rtw_ieee80211_ht_cap *)(p+2); + _rtw_memcpy(&mcs_rate , pht_capie->supp_mcs_set, 2); + bw_40MHz = (pht_capie->cap_info&IEEE80211_HT_CAP_SUP_WIDTH) ? 1:0; + short_GI = (pht_capie->cap_info&(IEEE80211_HT_CAP_SGI_20|IEEE80211_HT_CAP_SGI_40)) ? 1:0; + } + +#ifdef CONFIG_80211AC_VHT + //parsing VHT_CAP_IE + p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], EID_VHTCapability, &vht_ielen, pnetwork->network.IELength-ie_offset); + if(p && vht_ielen>0) + { + u8 mcs_map[2]; + + vht_cap = _TRUE; + bw_160MHz = GET_VHT_CAPABILITY_ELE_CHL_WIDTH(p+2); + if(bw_160MHz) + short_GI = GET_VHT_CAPABILITY_ELE_SHORT_GI160M(p+2); + else + short_GI = GET_VHT_CAPABILITY_ELE_SHORT_GI80M(p+2); + + _rtw_memcpy(mcs_map, GET_VHT_CAPABILITY_ELE_TX_MCS(p+2), 2); + + vht_highest_rate = rtw_get_vht_highest_rate(mcs_map); + vht_data_rate = rtw_vht_mcs_to_data_rate(CHANNEL_WIDTH_80, short_GI, vht_highest_rate); + } +#endif + + /*Add basic and extended rates */ + p = custom; + p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), " Rates (Mb/s): "); + while(pnetwork->network.SupportedRates[i]!=0) + { + rate = pnetwork->network.SupportedRates[i]&0x7F; + if (rate > max_rate) + max_rate = rate; + p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), + "%d%s ", rate >> 1, (rate & 1) ? ".5" : ""); + i++; + } +#ifdef CONFIG_80211AC_VHT + if(vht_cap == _TRUE) { + max_rate = vht_data_rate; + } + else +#endif + if(ht_cap == _TRUE) + { + if(mcs_rate&0x8000)//MCS15 + { + max_rate = (bw_40MHz) ? ((short_GI)?300:270):((short_GI)?144:130); + + } + else if(mcs_rate&0x0080)//MCS7 + { + max_rate = (bw_40MHz) ? ((short_GI)?150:135):((short_GI)?72:65); + } + else//default MCS7 + { + //DBG_871X("wx_get_scan, mcs_rate_bitmap=0x%x\n", mcs_rate); + max_rate = (bw_40MHz) ? ((short_GI)?150:135):((short_GI)?72:65); + } + + max_rate = max_rate*2;//Mbps/2; + } + + iwe->cmd = SIOCGIWRATE; + iwe->u.bitrate.fixed = iwe->u.bitrate.disabled = 0; + iwe->u.bitrate.value = max_rate * 500000; + start =iwe_stream_add_event(info, start, stop, iwe, IW_EV_PARAM_LEN); + return start ; +} + +static inline char * iwe_stream_wpa_wpa2_process(_adapter *padapter, + struct iw_request_info* info, struct wlan_network *pnetwork, + char *start, char *stop,struct iw_event *iwe) +{ + int buf_size = MAX_WPA_IE_LEN*2; + //u8 pbuf[buf_size]={0}; + u8 *pbuf = rtw_zmalloc(buf_size); + + u8 wpa_ie[255]={0},rsn_ie[255]={0}; + u16 i, wpa_len=0,rsn_len=0; + u8 *p; + sint out_len=0; + + + if(pbuf){ + p=pbuf; + + //parsing WPA/WPA2 IE + if (pnetwork->network.Reserved[0] != 2) // Probe Request + { + out_len=rtw_get_sec_ie(pnetwork->network.IEs ,pnetwork->network.IELength,rsn_ie,&rsn_len,wpa_ie,&wpa_len); + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_scan: ssid=%s\n",pnetwork->network.Ssid.Ssid)); + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_scan: wpa_len=%d rsn_len=%d\n",wpa_len,rsn_len)); + + if (wpa_len > 0){ + + _rtw_memset(pbuf, 0, buf_size); + p += sprintf(p, "wpa_ie="); + for (i = 0; i < wpa_len; i++) { + p += sprintf(p, "%02x", wpa_ie[i]); + } + + if (wpa_len > 100) { + printk("-----------------Len %d----------------\n", wpa_len); + for (i = 0; i < wpa_len; i++) { + printk("%02x ", wpa_ie[i]); + } + printk("\n"); + printk("-----------------Len %d----------------\n", wpa_len); + } + + _rtw_memset(iwe, 0, sizeof(*iwe)); + iwe->cmd = IWEVCUSTOM; + iwe->u.data.length = strlen(pbuf); + start = iwe_stream_add_point(info, start, stop, iwe,pbuf); + + _rtw_memset(iwe, 0, sizeof(*iwe)); + iwe->cmd =IWEVGENIE; + iwe->u.data.length = wpa_len; + start = iwe_stream_add_point(info, start, stop, iwe, wpa_ie); + } + if (rsn_len > 0){ + + _rtw_memset(pbuf, 0, buf_size); + p += sprintf(p, "rsn_ie="); + for (i = 0; i < rsn_len; i++) { + p += sprintf(p, "%02x", rsn_ie[i]); + } + _rtw_memset(iwe, 0, sizeof(*iwe)); + iwe->cmd = IWEVCUSTOM; + iwe->u.data.length = strlen(pbuf); + start = iwe_stream_add_point(info, start, stop, iwe,pbuf); + + _rtw_memset(iwe, 0, sizeof(*iwe)); + iwe->cmd =IWEVGENIE; + iwe->u.data.length = rsn_len; + start = iwe_stream_add_point(info, start, stop, iwe, rsn_ie); + } + } + + rtw_mfree(pbuf, buf_size); + } + return start; +} + +static inline char * iwe_stream_wps_process(_adapter *padapter, + struct iw_request_info* info, struct wlan_network *pnetwork, + char *start, char *stop,struct iw_event *iwe) +{ + //parsing WPS IE + uint cnt = 0,total_ielen; + u8 *wpsie_ptr=NULL; + uint wps_ielen = 0; + u8 ie_offset = (pnetwork->network.Reserved[0] == 2? 0:12); + + u8 *ie_ptr = pnetwork->network.IEs + ie_offset; + total_ielen= pnetwork->network.IELength - ie_offset; + + if (pnetwork->network.Reserved[0] == 2) // Probe Request + { + ie_ptr = pnetwork->network.IEs; + total_ielen = pnetwork->network.IELength; + } + else // Beacon or Probe Respones + { + ie_ptr = pnetwork->network.IEs + _FIXED_IE_LENGTH_; + total_ielen = pnetwork->network.IELength - _FIXED_IE_LENGTH_; + } + while(cnt < total_ielen) + { + if(rtw_is_wps_ie(&ie_ptr[cnt], &wps_ielen) && (wps_ielen>2)) + { + wpsie_ptr = &ie_ptr[cnt]; + iwe->cmd =IWEVGENIE; + iwe->u.data.length = (u16)wps_ielen; + start = iwe_stream_add_point(info, start, stop,iwe, wpsie_ptr); + } + cnt+=ie_ptr[cnt+1]+2; //goto next + } + return start; +} + +static inline char * iwe_stream_wapi_process(_adapter *padapter, + struct iw_request_info* info, struct wlan_network *pnetwork, + char *start, char *stop,struct iw_event *iwe) +{ +#ifdef CONFIG_WAPI_SUPPORT + char *p; + + if (pnetwork->network.Reserved[0] != 2) // Probe Request + { + sint out_len_wapi=0; + /* here use static for stack size */ + static u8 buf_wapi[MAX_WAPI_IE_LEN*2]={0}; + static u8 wapi_ie[MAX_WAPI_IE_LEN]={0}; + u16 wapi_len=0; + u16 i; + + out_len_wapi=rtw_get_wapi_ie(pnetwork->network.IEs ,pnetwork->network.IELength,wapi_ie,&wapi_len); + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_scan: ssid=%s\n",pnetwork->network.Ssid.Ssid)); + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_scan: wapi_len=%d \n",wapi_len)); + + DBG_871X("rtw_wx_get_scan: %s ",pnetwork->network.Ssid.Ssid); + DBG_871X("rtw_wx_get_scan: ssid = %d ",wapi_len); + + + if (wapi_len > 0) + { + p=buf_wapi; + //_rtw_memset(buf_wapi, 0, MAX_WAPI_IE_LEN*2); + p += sprintf(p, "wapi_ie="); + for (i = 0; i < wapi_len; i++) { + p += sprintf(p, "%02x", wapi_ie[i]); + } + + _rtw_memset(iwe, 0, sizeof(*iwe)); + iwe->cmd = IWEVCUSTOM; + iwe->u.data.length = strlen(buf_wapi); + start = iwe_stream_add_point(info, start, stop, iwe,buf_wapi); + + _rtw_memset(iwe, 0, sizeof(*iwe)); + iwe->cmd =IWEVGENIE; + iwe->u.data.length = wapi_len; + start = iwe_stream_add_point(info, start, stop, iwe, wapi_ie); + } + } +#endif//#ifdef CONFIG_WAPI_SUPPORT + return start; +} + +static inline char * iwe_stream_rssi_process(_adapter *padapter, + struct iw_request_info* info, struct wlan_network *pnetwork, + char *start, char *stop,struct iw_event *iwe) +{ + u8 ss, sq; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + /* Add quality statistics */ + iwe->cmd = IWEVQUAL; + iwe->u.qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_UPDATED + #if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) + | IW_QUAL_NOISE_UPDATED + #else + | IW_QUAL_NOISE_INVALID + #endif + #ifdef CONFIG_SIGNAL_DISPLAY_DBM + | IW_QUAL_DBM + #endif + ; + + if ( check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE && + is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)){ + ss = padapter->recvpriv.signal_strength; + sq = padapter->recvpriv.signal_qual; + } else { + ss = pnetwork->network.PhyInfo.SignalStrength; + sq = pnetwork->network.PhyInfo.SignalQuality; + } + + + #ifdef CONFIG_SIGNAL_DISPLAY_DBM + iwe->u.qual.level = (u8) translate_percentage_to_dbm(ss); /* dbm */ + #else + #ifdef CONFIG_SIGNAL_SCALE_MAPPING + iwe->u.qual.level = (u8)ss; /* % */ + #else + { + /* Do signal scale mapping when using percentage as the unit of signal strength, since the scale mapping is skipped in odm */ + + HAL_DATA_TYPE *pHal = GET_HAL_DATA(padapter); + + iwe->u.qual.level = (u8)odm_SignalScaleMapping(&pHal->odmpriv, ss); + } + #endif + #endif + + iwe->u.qual.qual = (u8)sq; // signal quality + + #ifdef CONFIG_PLATFORM_ROCKCHIPS + iwe->u.qual.noise = -100; // noise level suggest by zhf@rockchips + #else + #if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) + { + s16 tmp_noise=0; + rtw_hal_get_odm_var(padapter, HAL_ODM_NOISE_MONITOR,&(pnetwork->network.Configuration.DSConfig), &(tmp_noise)); + iwe->u.qual.noise = tmp_noise ; + } + #else + iwe->u.qual.noise = 0; // noise level + #endif + #endif //CONFIG_PLATFORM_ROCKCHIPS + + //DBG_871X("iqual=%d, ilevel=%d, inoise=%d, iupdated=%d\n", iwe.u.qual.qual, iwe.u.qual.level , iwe.u.qual.noise, iwe.u.qual.updated); + + start = iwe_stream_add_event(info, start, stop, iwe, IW_EV_QUAL_LEN); + return start; +} + +static inline char * iwe_stream_net_rsv_process(_adapter *padapter, + struct iw_request_info* info, struct wlan_network *pnetwork, + char *start, char *stop,struct iw_event *iwe) +{ + u8 buf[32] = {0}; + u8 * p,*pos; + int len; + p = buf; + pos = pnetwork->network.Reserved; + + p += sprintf(p, "fm=%02X%02X", pos[1], pos[0]); + _rtw_memset(iwe, 0, sizeof(*iwe)); + iwe->cmd = IWEVCUSTOM; + iwe->u.data.length = strlen(buf); + start = iwe_stream_add_point(info, start, stop,iwe, buf); + return start; +} + +#if 1 +static char *translate_scan(_adapter *padapter, + struct iw_request_info* info, struct wlan_network *pnetwork, + char *start, char *stop) +{ + struct iw_event iwe; + u16 cap = 0; + _rtw_memset(&iwe, 0, sizeof(iwe)); + + if(_FALSE == search_p2p_wfd_ie(padapter,info,pnetwork,start,stop)) + return start; + + start = iwe_stream_mac_addr_proess(padapter,info,pnetwork,start,stop,&iwe); + start = iwe_stream_essid_proess(padapter,info,pnetwork,start,stop,&iwe); + start = iwe_stream_protocol_process(padapter,info,pnetwork,start,stop,&iwe); + if (pnetwork->network.Reserved[0] == 2) // Probe Request + { + cap = 0; + } + else + { + _rtw_memcpy((u8 *)&cap, rtw_get_capability_from_ie(pnetwork->network.IEs), 2); + cap = le16_to_cpu(cap); + } + + start = iwe_stream_mode_process(padapter,info,pnetwork,start,stop,&iwe,cap); + start = iwe_stream_chan_process(padapter,info,pnetwork,start,stop,&iwe); + start = iwe_stream_encryption_process(padapter,info,pnetwork,start,stop,&iwe,cap); + start = iwe_stream_rate_process(padapter,info,pnetwork,start,stop,&iwe); + start = iwe_stream_wpa_wpa2_process(padapter,info,pnetwork,start,stop,&iwe); + start = iwe_stream_wps_process(padapter,info,pnetwork,start,stop,&iwe); + start = iwe_stream_wapi_process(padapter,info,pnetwork,start,stop,&iwe); + start = iwe_stream_rssi_process(padapter,info,pnetwork,start,stop,&iwe); + start = iwe_stream_net_rsv_process(padapter,info,pnetwork,start,stop,&iwe); + + return start; +} +#else +static char *translate_scan(_adapter *padapter, + struct iw_request_info* info, struct wlan_network *pnetwork, + char *start, char *stop) +{ + struct iw_event iwe; + u16 cap; + u32 ht_ielen = 0, vht_ielen = 0; + char custom[MAX_CUSTOM_LEN]; + char *p; + u16 max_rate=0, rate, ht_cap=_FALSE, vht_cap = _FALSE; + u32 i = 0; + char *current_val; + long rssi; + u8 bw_40MHz=0, short_GI=0, bw_160MHz=0, vht_highest_rate = 0; + u16 mcs_rate=0, vht_data_rate=0; + u8 ie_offset = (pnetwork->network.Reserved[0] == 2? 0:12); + struct registry_priv *pregpriv = &padapter->registrypriv; + + if(_FALSE == search_p2p_wfd_ie(padapter,info,pnetwork,start,stop)) + return start; + + /* AP MAC address */ + iwe.cmd = SIOCGIWAP; + iwe.u.ap_addr.sa_family = ARPHRD_ETHER; + + _rtw_memcpy(iwe.u.ap_addr.sa_data, pnetwork->network.MacAddress, ETH_ALEN); + start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_ADDR_LEN); + + /* Add the ESSID */ + iwe.cmd = SIOCGIWESSID; + iwe.u.data.flags = 1; + iwe.u.data.length = min((u16)pnetwork->network.Ssid.SsidLength, (u16)32); + start = iwe_stream_add_point(info, start, stop, &iwe, pnetwork->network.Ssid.Ssid); + + //parsing HT_CAP_IE + if (pnetwork->network.Reserved[0] == 2) // Probe Request + { + p = rtw_get_ie(&pnetwork->network.IEs[0], _HT_CAPABILITY_IE_, &ht_ielen, pnetwork->network.IELength); + } + else + { + p = rtw_get_ie(&pnetwork->network.IEs[12], _HT_CAPABILITY_IE_, &ht_ielen, pnetwork->network.IELength-12); + } + if(p && ht_ielen>0) + { + struct rtw_ieee80211_ht_cap *pht_capie; + ht_cap = _TRUE; + pht_capie = (struct rtw_ieee80211_ht_cap *)(p+2); + _rtw_memcpy(&mcs_rate , pht_capie->supp_mcs_set, 2); + bw_40MHz = (pht_capie->cap_info&IEEE80211_HT_CAP_SUP_WIDTH) ? 1:0; + short_GI = (pht_capie->cap_info&(IEEE80211_HT_CAP_SGI_20|IEEE80211_HT_CAP_SGI_40)) ? 1:0; + } + +#ifdef CONFIG_80211AC_VHT + //parsing VHT_CAP_IE + p = rtw_get_ie(&pnetwork->network.IEs[ie_offset], EID_VHTCapability, &vht_ielen, pnetwork->network.IELength-ie_offset); + if(p && vht_ielen>0) + { + u8 mcs_map[2]; + + vht_cap = _TRUE; + bw_160MHz = GET_VHT_CAPABILITY_ELE_CHL_WIDTH(p+2); + if(bw_160MHz) + short_GI = GET_VHT_CAPABILITY_ELE_SHORT_GI160M(p+2); + else + short_GI = GET_VHT_CAPABILITY_ELE_SHORT_GI80M(p+2); + + _rtw_memcpy(mcs_map, GET_VHT_CAPABILITY_ELE_TX_MCS(p+2), 2); + + vht_highest_rate = rtw_get_vht_highest_rate(mcs_map); + vht_data_rate = rtw_vht_mcs_to_data_rate(CHANNEL_WIDTH_80, short_GI, vht_highest_rate); + } +#endif + + /* Add the protocol name */ + iwe.cmd = SIOCGIWNAME; + if ((rtw_is_cckratesonly_included((u8*)&pnetwork->network.SupportedRates)) == _TRUE) + { + if(ht_cap == _TRUE) + snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11bn"); + else + snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11b"); + } + else if ((rtw_is_cckrates_included((u8*)&pnetwork->network.SupportedRates)) == _TRUE) + { + if(ht_cap == _TRUE) + snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11bgn"); + else + snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11bg"); + } + else + { + if(pnetwork->network.Configuration.DSConfig > 14) + { + if(vht_cap == _TRUE) + snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11AC"); + else if(ht_cap == _TRUE) + snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11an"); + else + snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11a"); + } + else + { + if(ht_cap == _TRUE) + snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11gn"); + else + snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11g"); + } + } + + start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_CHAR_LEN); + + /* Add mode */ + if (pnetwork->network.Reserved[0] == 2) // Probe Request + { + cap = 0; + } + else + { + iwe.cmd = SIOCGIWMODE; + _rtw_memcpy((u8 *)&cap, rtw_get_capability_from_ie(pnetwork->network.IEs), 2); + cap = le16_to_cpu(cap); + } + + if(cap & (WLAN_CAPABILITY_IBSS |WLAN_CAPABILITY_BSS)){ + if (cap & WLAN_CAPABILITY_BSS) + iwe.u.mode = IW_MODE_MASTER; + else + iwe.u.mode = IW_MODE_ADHOC; + + start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_UINT_LEN); + } + + if(pnetwork->network.Configuration.DSConfig<1 /*|| pnetwork->network.Configuration.DSConfig>14*/) + pnetwork->network.Configuration.DSConfig = 1; + + /* Add frequency/channel */ + iwe.cmd = SIOCGIWFREQ; + iwe.u.freq.m = rtw_ch2freq(pnetwork->network.Configuration.DSConfig) * 100000; + iwe.u.freq.e = 1; + iwe.u.freq.i = pnetwork->network.Configuration.DSConfig; + start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_FREQ_LEN); + + /* Add encryption capability */ + iwe.cmd = SIOCGIWENCODE; + if (cap & WLAN_CAPABILITY_PRIVACY) + iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY; + else + iwe.u.data.flags = IW_ENCODE_DISABLED; + iwe.u.data.length = 0; + start = iwe_stream_add_point(info, start, stop, &iwe, pnetwork->network.Ssid.Ssid); + + /*Add basic and extended rates */ + max_rate = 0; + p = custom; + p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), " Rates (Mb/s): "); + while(pnetwork->network.SupportedRates[i]!=0) + { + rate = pnetwork->network.SupportedRates[i]&0x7F; + if (rate > max_rate) + max_rate = rate; + p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), + "%d%s ", rate >> 1, (rate & 1) ? ".5" : ""); + i++; + } + + if(vht_cap == _TRUE) { + max_rate = vht_data_rate; + } + else if(ht_cap == _TRUE) + { + if(mcs_rate&0x8000)//MCS15 + { + max_rate = (bw_40MHz) ? ((short_GI)?300:270):((short_GI)?144:130); + + } + else if(mcs_rate&0x0080)//MCS7 + { + max_rate = (bw_40MHz) ? ((short_GI)?150:135):((short_GI)?72:65); + } + else//default MCS7 + { + //DBG_871X("wx_get_scan, mcs_rate_bitmap=0x%x\n", mcs_rate); + max_rate = (bw_40MHz) ? ((short_GI)?150:135):((short_GI)?72:65); + } + + max_rate = max_rate*2;//Mbps/2; + } + + iwe.cmd = SIOCGIWRATE; + iwe.u.bitrate.fixed = iwe.u.bitrate.disabled = 0; + iwe.u.bitrate.value = max_rate * 500000; + start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_PARAM_LEN); + + //parsing WPA/WPA2 IE + if (pnetwork->network.Reserved[0] != 2) // Probe Request + { + u8 buf[MAX_WPA_IE_LEN*2]; + u8 wpa_ie[255],rsn_ie[255]; + u16 wpa_len=0,rsn_len=0; + u8 *p; + sint out_len=0; + out_len=rtw_get_sec_ie(pnetwork->network.IEs ,pnetwork->network.IELength,rsn_ie,&rsn_len,wpa_ie,&wpa_len); + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_scan: ssid=%s\n",pnetwork->network.Ssid.Ssid)); + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_scan: wpa_len=%d rsn_len=%d\n",wpa_len,rsn_len)); + + if (wpa_len > 0) + { + p=buf; + _rtw_memset(buf, 0, MAX_WPA_IE_LEN*2); + p += sprintf(p, "wpa_ie="); + for (i = 0; i < wpa_len; i++) { + p += sprintf(p, "%02x", wpa_ie[i]); + } + + if (wpa_len > 100) { + printk("-----------------Len %d----------------\n", wpa_len); + for (i = 0; i < wpa_len; i++) { + printk("%02x ", wpa_ie[i]); + } + printk("\n"); + printk("-----------------Len %d----------------\n", wpa_len); + } + + _rtw_memset(&iwe, 0, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = strlen(buf); + start = iwe_stream_add_point(info, start, stop, &iwe,buf); + + _rtw_memset(&iwe, 0, sizeof(iwe)); + iwe.cmd =IWEVGENIE; + iwe.u.data.length = wpa_len; + start = iwe_stream_add_point(info, start, stop, &iwe, wpa_ie); + } + if (rsn_len > 0) + { + p = buf; + _rtw_memset(buf, 0, MAX_WPA_IE_LEN*2); + p += sprintf(p, "rsn_ie="); + for (i = 0; i < rsn_len; i++) { + p += sprintf(p, "%02x", rsn_ie[i]); + } + _rtw_memset(&iwe, 0, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = strlen(buf); + start = iwe_stream_add_point(info, start, stop, &iwe,buf); + + _rtw_memset(&iwe, 0, sizeof(iwe)); + iwe.cmd =IWEVGENIE; + iwe.u.data.length = rsn_len; + start = iwe_stream_add_point(info, start, stop, &iwe, rsn_ie); + } + } + + { //parsing WPS IE + uint cnt = 0,total_ielen; + u8 *wpsie_ptr=NULL; + uint wps_ielen = 0; + + u8 *ie_ptr = pnetwork->network.IEs + ie_offset; + total_ielen= pnetwork->network.IELength - ie_offset; + + if (pnetwork->network.Reserved[0] == 2) // Probe Request + { + ie_ptr = pnetwork->network.IEs; + total_ielen = pnetwork->network.IELength; + } + else // Beacon or Probe Respones + { + ie_ptr = pnetwork->network.IEs + _FIXED_IE_LENGTH_; + total_ielen = pnetwork->network.IELength - _FIXED_IE_LENGTH_; + } + + while(cnt < total_ielen) + { + if(rtw_is_wps_ie(&ie_ptr[cnt], &wps_ielen) && (wps_ielen>2)) + { + wpsie_ptr = &ie_ptr[cnt]; + iwe.cmd =IWEVGENIE; + iwe.u.data.length = (u16)wps_ielen; + start = iwe_stream_add_point(info, start, stop, &iwe, wpsie_ptr); + } + cnt+=ie_ptr[cnt+1]+2; //goto next + } + } + +#ifdef CONFIG_WAPI_SUPPORT + if (pnetwork->network.Reserved[0] != 2) // Probe Request + { + sint out_len_wapi=0; + /* here use static for stack size */ + static u8 buf_wapi[MAX_WAPI_IE_LEN*2]; + static u8 wapi_ie[MAX_WAPI_IE_LEN]; + u16 wapi_len=0; + u16 i; + + _rtw_memset(buf_wapi, 0, MAX_WAPI_IE_LEN); + _rtw_memset(wapi_ie, 0, MAX_WAPI_IE_LEN); + + out_len_wapi=rtw_get_wapi_ie(pnetwork->network.IEs ,pnetwork->network.IELength,wapi_ie,&wapi_len); + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_scan: ssid=%s\n",pnetwork->network.Ssid.Ssid)); + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_scan: wapi_len=%d \n",wapi_len)); + + DBG_871X("rtw_wx_get_scan: %s ",pnetwork->network.Ssid.Ssid); + DBG_871X("rtw_wx_get_scan: ssid = %d ",wapi_len); + + + if (wapi_len > 0) + { + p=buf_wapi; + _rtw_memset(buf_wapi, 0, MAX_WAPI_IE_LEN*2); + p += sprintf(p, "wapi_ie="); + for (i = 0; i < wapi_len; i++) { + p += sprintf(p, "%02x", wapi_ie[i]); + } + + _rtw_memset(&iwe, 0, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = strlen(buf_wapi); + start = iwe_stream_add_point(info, start, stop, &iwe,buf_wapi); + + _rtw_memset(&iwe, 0, sizeof(iwe)); + iwe.cmd =IWEVGENIE; + iwe.u.data.length = wapi_len; + start = iwe_stream_add_point(info, start, stop, &iwe, wapi_ie); + } + } +#endif + +{ + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u8 ss, sq; + + /* Add quality statistics */ + iwe.cmd = IWEVQUAL; + iwe.u.qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_UPDATED + #if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) + | IW_QUAL_NOISE_UPDATED + #else + | IW_QUAL_NOISE_INVALID + #endif + #ifdef CONFIG_SIGNAL_DISPLAY_DBM + | IW_QUAL_DBM + #endif + ; + + if ( check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE && + is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network, 0)){ + ss = padapter->recvpriv.signal_strength; + sq = padapter->recvpriv.signal_qual; + } else { + ss = pnetwork->network.PhyInfo.SignalStrength; + sq = pnetwork->network.PhyInfo.SignalQuality; + } + + + #ifdef CONFIG_SIGNAL_DISPLAY_DBM + iwe.u.qual.level = (u8) translate_percentage_to_dbm(ss); /* dbm */ + #else + #ifdef CONFIG_SIGNAL_SCALE_MAPPING + iwe.u.qual.level = (u8)ss; /* % */ + #else + { + /* Do signal scale mapping when using percentage as the unit of signal strength, since the scale mapping is skipped in odm */ + + HAL_DATA_TYPE *pHal = GET_HAL_DATA(padapter); + + iwe.u.qual.level = (u8)odm_SignalScaleMapping(&pHal->odmpriv, ss); + } + #endif + #endif + + iwe.u.qual.qual = (u8)sq; // signal quality + + #ifdef CONFIG_PLATFORM_ROCKCHIPS + iwe.u.qual.noise = -100; // noise level suggest by zhf@rockchips + #else + #if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR) + { + s16 tmp_noise=0; + rtw_hal_get_odm_var(padapter, HAL_ODM_NOISE_MONITOR,&(pnetwork->network.Configuration.DSConfig), &(tmp_noise)); + iwe.u.qual.noise = tmp_noise ; + } + #else + iwe.u.qual.noise = 0; // noise level + #endif + #endif //CONFIG_PLATFORM_ROCKCHIPS + + //DBG_871X("iqual=%d, ilevel=%d, inoise=%d, iupdated=%d\n", iwe.u.qual.qual, iwe.u.qual.level , iwe.u.qual.noise, iwe.u.qual.updated); + + start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_QUAL_LEN); +} + + { + u8 buf[MAX_WPA_IE_LEN]; + u8 * p,*pos; + int len; + p = buf; + pos = pnetwork->network.Reserved; + _rtw_memset(buf, 0, MAX_WPA_IE_LEN); + p += sprintf(p, "fm=%02X%02X", pos[1], pos[0]); + _rtw_memset(&iwe, 0, sizeof(iwe)); + iwe.cmd = IWEVCUSTOM; + iwe.u.data.length = strlen(buf); + start = iwe_stream_add_point(info, start, stop, &iwe, buf); + } + + return start; +} +#endif + +static int wpa_set_auth_algs(struct net_device *dev, u32 value) +{ + _adapter *padapter = (_adapter *) rtw_netdev_priv(dev); + int ret = 0; + + if ((value & AUTH_ALG_SHARED_KEY)&&(value & AUTH_ALG_OPEN_SYSTEM)) + { + DBG_871X("wpa_set_auth_algs, AUTH_ALG_SHARED_KEY and AUTH_ALG_OPEN_SYSTEM [value:0x%x]\n",value); + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; + padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeAutoSwitch; + padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto; + } + else if (value & AUTH_ALG_SHARED_KEY) + { + DBG_871X("wpa_set_auth_algs, AUTH_ALG_SHARED_KEY [value:0x%x]\n",value); + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; + +#ifdef CONFIG_PLATFORM_MT53XX + padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeAutoSwitch; + padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto; +#else + padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeShared; + padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Shared; +#endif + } + else if(value & AUTH_ALG_OPEN_SYSTEM) + { + DBG_871X("wpa_set_auth_algs, AUTH_ALG_OPEN_SYSTEM\n"); + //padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled; + if(padapter->securitypriv.ndisauthtype < Ndis802_11AuthModeWPAPSK) + { +#ifdef CONFIG_PLATFORM_MT53XX + padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeAutoSwitch; + padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto; +#else + padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen; + padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open; +#endif + } + + } + else if(value & AUTH_ALG_LEAP) + { + DBG_871X("wpa_set_auth_algs, AUTH_ALG_LEAP\n"); + } + else + { + DBG_871X("wpa_set_auth_algs, error!\n"); + ret = -EINVAL; + } + + return ret; + +} + +static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) +{ + int ret = 0; + u32 wep_key_idx, wep_key_len,wep_total_len; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; +#ifdef CONFIG_P2P + struct wifidirect_info* pwdinfo = &padapter->wdinfo; +#endif //CONFIG_P2P + +_func_enter_; + + param->u.crypt.err = 0; + param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0'; + + if (param_len < (u32) ((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) + { + ret = -EINVAL; + goto exit; + } + + if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) + { + + if (param->u.crypt.idx >= WEP_KEYS +#ifdef CONFIG_IEEE80211W + && param->u.crypt.idx > BIP_MAX_KEYID +#endif //CONFIG_IEEE80211W + ) + { + ret = -EINVAL; + goto exit; + } + } + else + { +#ifdef CONFIG_WAPI_SUPPORT + if (strcmp(param->u.crypt.alg, "SMS4")) +#endif + { + ret = -EINVAL; + goto exit; + } + } + + if (strcmp(param->u.crypt.alg, "WEP") == 0) + { + RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("wpa_set_encryption, crypt.alg = WEP\n")); + DBG_871X("wpa_set_encryption, crypt.alg = WEP\n"); + + wep_key_idx = param->u.crypt.idx; + wep_key_len = param->u.crypt.key_len; + + if ((wep_key_idx > WEP_KEYS) || (wep_key_len <= 0)) + { + ret = -EINVAL; + goto exit; + } + + if (psecuritypriv->bWepDefaultKeyIdxSet == 0) { + /* wep default key has not been set, so use this key index as default key.*/ + + wep_key_len = wep_key_len <= 5 ? 5 : 13; + + psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled; + psecuritypriv->dot11PrivacyAlgrthm = _WEP40_; + psecuritypriv->dot118021XGrpPrivacy = _WEP40_; + + if (wep_key_len == 13) + { + psecuritypriv->dot11PrivacyAlgrthm = _WEP104_; + psecuritypriv->dot118021XGrpPrivacy = _WEP104_; + } + + psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx; + } + + _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), param->u.crypt.key, wep_key_len); + + psecuritypriv->dot11DefKeylen[wep_key_idx] = wep_key_len; + + psecuritypriv->key_mask |= BIT(wep_key_idx); + + goto exit; + } + + if(padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) // 802_1x + { + struct sta_info * psta,*pbcmc_sta; + struct sta_priv * pstapriv = &padapter->stapriv; + + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_MP_STATE) == _TRUE) //sta mode + { + psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); + if (psta == NULL) { + //DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail \n")); + } + else + { + //Jeff: don't disable ieee8021x_blocked while clearing key + if (strcmp(param->u.crypt.alg, "none") != 0) + psta->ieee8021x_blocked = _FALSE; + + if((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled)|| + (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled)) + { + psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; + } + + if(param->u.crypt.set_tx ==1)//pairwise key + { + _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); + + if(strcmp(param->u.crypt.alg, "TKIP") == 0)//set mic key + { + //DEBUG_ERR(("\nset key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len)); + _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); + _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); + + padapter->securitypriv.busetkipkey=_FALSE; + //_set_timer(&padapter->securitypriv.tkip_timer, 50); + } + + //DEBUG_ERR((" param->u.crypt.key_len=%d\n",param->u.crypt.key_len)); + DBG_871X(" ~~~~set sta key:unicastkey\n"); + + rtw_setstakey_cmd(padapter, psta, UNICAST_KEY, _TRUE); + + psta->bpairwise_key_installed = _TRUE; + + } + else//group key + { + if(strcmp(param->u.crypt.alg, "TKIP") == 0 || strcmp(param->u.crypt.alg, "CCMP") == 0) + { + _rtw_memcpy(padapter->securitypriv.dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key,(param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); + //only TKIP group key need to install this + if(param->u.crypt.key_len > 16) + { + _rtw_memcpy(padapter->securitypriv.dot118021XGrptxmickey[param->u.crypt.idx].skey,&(param->u.crypt.key[16]),8); + _rtw_memcpy(padapter->securitypriv.dot118021XGrprxmickey[param->u.crypt.idx].skey,&(param->u.crypt.key[24]),8); + } + padapter->securitypriv.binstallGrpkey = _TRUE; + //DEBUG_ERR((" param->u.crypt.key_len=%d\n", param->u.crypt.key_len)); + DBG_871X(" ~~~~set sta key:groupkey\n"); + + padapter->securitypriv.dot118021XGrpKeyid = param->u.crypt.idx; + + rtw_set_key(padapter,&padapter->securitypriv,param->u.crypt.idx, 1, _TRUE); + } +#ifdef CONFIG_IEEE80211W + else if(strcmp(param->u.crypt.alg, "BIP") == 0) + { + int no; + //printk("BIP key_len=%d , index=%d @@@@@@@@@@@@@@@@@@\n", param->u.crypt.key_len, param->u.crypt.idx); + //save the IGTK key, length 16 bytes + _rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key,(param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); + /*printk("IGTK key below:\n"); + for(no=0;no<16;no++) + printk(" %02x ", padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey[no]); + printk("\n");*/ + padapter->securitypriv.dot11wBIPKeyid = param->u.crypt.idx; + padapter->securitypriv.binstallBIPkey = _TRUE; + DBG_871X(" ~~~~set sta key:IGKT\n"); + } +#endif //CONFIG_IEEE80211W + +#ifdef CONFIG_P2P + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING)) + { + rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_DONE); + } +#endif //CONFIG_P2P + + } + } + + pbcmc_sta=rtw_get_bcmc_stainfo(padapter); + if(pbcmc_sta==NULL) + { + //DEBUG_ERR( ("Set OID_802_11_ADD_KEY: bcmc stainfo is null \n")); + } + else + { + //Jeff: don't disable ieee8021x_blocked while clearing key + if (strcmp(param->u.crypt.alg, "none") != 0) + pbcmc_sta->ieee8021x_blocked = _FALSE; + + if((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled)|| + (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled)) + { + pbcmc_sta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; + } + } + } + else if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) //adhoc mode + { + } + } + +#ifdef CONFIG_WAPI_SUPPORT + if (strcmp(param->u.crypt.alg, "SMS4") == 0) + { + PRT_WAPI_T pWapiInfo = &padapter->wapiInfo; + PRT_WAPI_STA_INFO pWapiSta; + u8 WapiASUEPNInitialValueSrc[16] = {0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; + u8 WapiAEPNInitialValueSrc[16] = {0x37,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; + u8 WapiAEMultiCastPNInitialValueSrc[16] = {0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C,0x36,0x5C} ; + + if(param->u.crypt.set_tx == 1) + { + list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { + if(_rtw_memcmp(pWapiSta->PeerMacAddr,param->sta_addr,6)) + { + _rtw_memcpy(pWapiSta->lastTxUnicastPN,WapiASUEPNInitialValueSrc,16); + + pWapiSta->wapiUsk.bSet = true; + _rtw_memcpy(pWapiSta->wapiUsk.dataKey,param->u.crypt.key,16); + _rtw_memcpy(pWapiSta->wapiUsk.micKey,param->u.crypt.key+16,16); + pWapiSta->wapiUsk.keyId = param->u.crypt.idx ; + pWapiSta->wapiUsk.bTxEnable = true; + + _rtw_memcpy(pWapiSta->lastRxUnicastPNBEQueue,WapiAEPNInitialValueSrc,16); + _rtw_memcpy(pWapiSta->lastRxUnicastPNBKQueue,WapiAEPNInitialValueSrc,16); + _rtw_memcpy(pWapiSta->lastRxUnicastPNVIQueue,WapiAEPNInitialValueSrc,16); + _rtw_memcpy(pWapiSta->lastRxUnicastPNVOQueue,WapiAEPNInitialValueSrc,16); + _rtw_memcpy(pWapiSta->lastRxUnicastPN,WapiAEPNInitialValueSrc,16); + pWapiSta->wapiUskUpdate.bTxEnable = false; + pWapiSta->wapiUskUpdate.bSet = false; + + if (psecuritypriv->sw_encrypt== false || psecuritypriv->sw_decrypt == false) + { + //set unicast key for ASUE + rtw_wapi_set_key(padapter, &pWapiSta->wapiUsk, pWapiSta, false, false); + } + } + } + } + else + { + list_for_each_entry(pWapiSta, &pWapiInfo->wapiSTAUsedList, list) { + if(_rtw_memcmp(pWapiSta->PeerMacAddr,get_bssid(pmlmepriv),6)) + { + pWapiSta->wapiMsk.bSet = true; + _rtw_memcpy(pWapiSta->wapiMsk.dataKey,param->u.crypt.key,16); + _rtw_memcpy(pWapiSta->wapiMsk.micKey,param->u.crypt.key+16,16); + pWapiSta->wapiMsk.keyId = param->u.crypt.idx ; + pWapiSta->wapiMsk.bTxEnable = false; + if(!pWapiSta->bSetkeyOk) + pWapiSta->bSetkeyOk = true; + pWapiSta->bAuthenticateInProgress = false; + + _rtw_memcpy(pWapiSta->lastRxMulticastPN, WapiAEMultiCastPNInitialValueSrc, 16); + + if (psecuritypriv->sw_decrypt == false) + { + //set rx broadcast key for ASUE + rtw_wapi_set_key(padapter, &pWapiSta->wapiMsk, pWapiSta, true, false); + } + } + + } + } + } +#endif + +exit: + +_func_exit_; + + return ret; +} + +static int rtw_set_wpa_ie(_adapter *padapter, char *pie, unsigned short ielen) +{ + u8 *buf=NULL, *pos=NULL; + u32 left; + int group_cipher = 0, pairwise_cipher = 0; + int ret = 0; + u8 null_addr[]= {0,0,0,0,0,0}; +#ifdef CONFIG_P2P + struct wifidirect_info* pwdinfo = &padapter->wdinfo; +#endif //CONFIG_P2P + + if((ielen > MAX_WPA_IE_LEN) || (pie == NULL)){ + _clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS); + if(pie == NULL) + return ret; + else + return -EINVAL; + } + + if(ielen) + { + buf = rtw_zmalloc(ielen); + if (buf == NULL){ + ret = -ENOMEM; + goto exit; + } + + _rtw_memcpy(buf, pie , ielen); + + //dump + { + int i; + DBG_871X("\n wpa_ie(length:%d):\n", ielen); + for(i=0;i= RSN_SELECTOR_LEN){ + pos += RSN_SELECTOR_LEN; + left -= RSN_SELECTOR_LEN; + } + else if (left > 0){ + RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("Ie length mismatch, %u too much \n", left)); + ret =-1; + goto exit; + } +#endif + + if(rtw_parse_wpa_ie(buf, ielen, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) + { + padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_8021X; + padapter->securitypriv.ndisauthtype=Ndis802_11AuthModeWPAPSK; + _rtw_memcpy(padapter->securitypriv.supplicant_ie, &buf[0], ielen); + } + + if(rtw_parse_wpa2_ie(buf, ielen, &group_cipher, &pairwise_cipher, NULL) == _SUCCESS) + { + padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_8021X; + padapter->securitypriv.ndisauthtype=Ndis802_11AuthModeWPA2PSK; + _rtw_memcpy(padapter->securitypriv.supplicant_ie, &buf[0], ielen); + } + + if (group_cipher == 0) + { + group_cipher = WPA_CIPHER_NONE; + } + if (pairwise_cipher == 0) + { + pairwise_cipher = WPA_CIPHER_NONE; + } + + switch(group_cipher) + { + case WPA_CIPHER_NONE: + padapter->securitypriv.dot118021XGrpPrivacy=_NO_PRIVACY_; + padapter->securitypriv.ndisencryptstatus=Ndis802_11EncryptionDisabled; + break; + case WPA_CIPHER_WEP40: + padapter->securitypriv.dot118021XGrpPrivacy=_WEP40_; + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; + break; + case WPA_CIPHER_TKIP: + padapter->securitypriv.dot118021XGrpPrivacy=_TKIP_; + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled; + break; + case WPA_CIPHER_CCMP: + padapter->securitypriv.dot118021XGrpPrivacy=_AES_; + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled; + break; + case WPA_CIPHER_WEP104: + padapter->securitypriv.dot118021XGrpPrivacy=_WEP104_; + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; + break; + } + + switch(pairwise_cipher) + { + case WPA_CIPHER_NONE: + padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_; + padapter->securitypriv.ndisencryptstatus=Ndis802_11EncryptionDisabled; + break; + case WPA_CIPHER_WEP40: + padapter->securitypriv.dot11PrivacyAlgrthm=_WEP40_; + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; + break; + case WPA_CIPHER_TKIP: + padapter->securitypriv.dot11PrivacyAlgrthm=_TKIP_; + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled; + break; + case WPA_CIPHER_CCMP: + padapter->securitypriv.dot11PrivacyAlgrthm=_AES_; + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled; + break; + case WPA_CIPHER_WEP104: + padapter->securitypriv.dot11PrivacyAlgrthm=_WEP104_; + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; + break; + } + + _clr_fwstate_(&padapter->mlmepriv, WIFI_UNDER_WPS); + {//set wps_ie + u16 cnt = 0; + u8 eid, wps_oui[4]={0x0,0x50,0xf2,0x04}; + + while( cnt < ielen ) + { + eid = buf[cnt]; + + if((eid==_VENDOR_SPECIFIC_IE_)&&(_rtw_memcmp(&buf[cnt+2], wps_oui, 4)==_TRUE)) + { + DBG_871X("SET WPS_IE\n"); + + padapter->securitypriv.wps_ie_len = ((buf[cnt+1]+2) < MAX_WPS_IE_LEN) ? (buf[cnt+1]+2):MAX_WPS_IE_LEN; + + _rtw_memcpy(padapter->securitypriv.wps_ie, &buf[cnt], padapter->securitypriv.wps_ie_len); + + set_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS); + +#ifdef CONFIG_P2P + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_OK)) + { + rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_ING); + } +#endif //CONFIG_P2P + cnt += buf[cnt+1]+2; + + break; + } else { + cnt += buf[cnt+1]+2; //goto next + } + } + } + } + + //TKIP and AES disallow multicast packets until installing group key + if(padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_ + || padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_WTMIC_ + || padapter->securitypriv.dot11PrivacyAlgrthm == _AES_) + //WPS open need to enable multicast + //|| check_fwstate(&padapter->mlmepriv, WIFI_UNDER_WPS) == _TRUE) + rtw_hal_set_hwreg(padapter, HW_VAR_OFF_RCR_AM, null_addr); + + RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, + ("rtw_set_wpa_ie: pairwise_cipher=0x%08x padapter->securitypriv.ndisencryptstatus=%d padapter->securitypriv.ndisauthtype=%d\n", + pairwise_cipher, padapter->securitypriv.ndisencryptstatus, padapter->securitypriv.ndisauthtype)); + +exit: + + if (buf) rtw_mfree(buf, ielen); + + return ret; +} + +static int rtw_wx_get_name(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u16 cap; + u32 ht_ielen = 0; + char *p; + u8 ht_cap=_FALSE, vht_cap=_FALSE; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network; + NDIS_802_11_RATES_EX* prates = NULL; + + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("cmd_code=%x\n", info->cmd)); + + _func_enter_; + + if (check_fwstate(pmlmepriv, _FW_LINKED|WIFI_ADHOC_MASTER_STATE) == _TRUE) + { + //parsing HT_CAP_IE + p = rtw_get_ie(&pcur_bss->IEs[12], _HT_CAPABILITY_IE_, &ht_ielen, pcur_bss->IELength-12); + if(p && ht_ielen>0) + { + ht_cap = _TRUE; + } + +#ifdef CONFIG_80211AC_VHT + if(pmlmepriv->vhtpriv.vht_option == _TRUE) + vht_cap = _TRUE; +#endif + + prates = &pcur_bss->SupportedRates; + + if (rtw_is_cckratesonly_included((u8*)prates) == _TRUE) + { + if(ht_cap == _TRUE) + snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bn"); + else + snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11b"); + } + else if ((rtw_is_cckrates_included((u8*)prates)) == _TRUE) + { + if(ht_cap == _TRUE) + snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bgn"); + else + snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bg"); + } + else + { + if(pcur_bss->Configuration.DSConfig > 14) + { + #ifdef CONFIG_80211AC_VHT + if(vht_cap == _TRUE){ + snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11AC"); + } + else + #endif + { + if(ht_cap == _TRUE) + snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11an"); + else + snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11a"); + } + } + else + { + if(ht_cap == _TRUE) + snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11gn"); + else + snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11g"); + } + } + } + else + { + //prates = &padapter->registrypriv.dev_network.SupportedRates; + //snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11g"); + snprintf(wrqu->name, IFNAMSIZ, "unassociated"); + } + + _func_exit_; + + return 0; +} + +static int rtw_wx_set_freq(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(padapter); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct wlan_network *cur_network = &(pmlmepriv->cur_network); + int exp = 1, freq = 0, div = 0; + + _func_enter_; + + RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, ("+rtw_wx_set_freq\n")); + + if (wrqu->freq.m <= 1000) { + if (wrqu->freq.flags == IW_FREQ_AUTO) { + if (rtw_ch_set_search_ch(padapter->mlmeextpriv.channel_set, wrqu->freq.m) > 0) { + padapter->mlmeextpriv.cur_channel = wrqu->freq.m; + DBG_871X("%s: channel is auto, set to channel %d\n", __func__, wrqu->freq.m); + } else { + padapter->mlmeextpriv.cur_channel = 1; + DBG_871X("%s: channel is auto, Channel Plan don't match just set to channel 1\n", __func__); + } + } else { + padapter->mlmeextpriv.cur_channel = wrqu->freq.m; + DBG_871X("%s: set to channel %d\n", __func__, padapter->mlmeextpriv.cur_channel); + } + } else { + while (wrqu->freq.e) { + exp *= 10; + wrqu->freq.e--; + } + + freq = wrqu->freq.m; + + while (!(freq%10)) { + freq /= 10; + exp *= 10; + } + + /* freq unit is MHz here */ + div = 1000000/exp; + + if (div) + freq /= div; + else { + div = exp/1000000; + freq *= div; + } + + /* If freq is invalid, rtw_freq2ch() will return channel 1 */ + padapter->mlmeextpriv.cur_channel = rtw_freq2ch(freq); + DBG_871X("%s: set to channel %d\n", __func__, padapter->mlmeextpriv.cur_channel); + } + + set_channel_bwmode(padapter, padapter->mlmeextpriv.cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + + _func_exit_; + + return 0; +} + +static int rtw_wx_get_freq(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network; + + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE && check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) != _TRUE) { + + wrqu->freq.m = rtw_ch2freq(pcur_bss->Configuration.DSConfig) * 100000; + wrqu->freq.e = 1; + wrqu->freq.i = pcur_bss->Configuration.DSConfig; + + } else { + wrqu->freq.m = rtw_ch2freq(padapter->mlmeextpriv.cur_channel) * 100000; + wrqu->freq.e = 1; + wrqu->freq.i = padapter->mlmeextpriv.cur_channel; + } + + return 0; +} + +static int rtw_wx_set_mode(struct net_device *dev, struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + NDIS_802_11_NETWORK_INFRASTRUCTURE networkType ; + int ret = 0; + + _func_enter_; + + if(_FAIL == rtw_pwr_wakeup(padapter)) { + ret= -EPERM; + goto exit; + } + + if (!rtw_is_hw_init_completed(padapter)) { + ret = -EPERM; + goto exit; + } + + /* initial default type */ + dev->type = ARPHRD_ETHER; + + switch(wrqu->mode) + { + case IW_MODE_MONITOR: + networkType = Ndis802_11Monitor; +#if 0 + dev->type = ARPHRD_IEEE80211; /* IEEE 802.11 : 801 */ +#endif + dev->type = ARPHRD_IEEE80211_RADIOTAP; /* IEEE 802.11 + radiotap header : 803 */ + DBG_871X("set_mode = IW_MODE_MONITOR\n"); + break; + + case IW_MODE_AUTO: + networkType = Ndis802_11AutoUnknown; + DBG_871X("set_mode = IW_MODE_AUTO\n"); + break; + case IW_MODE_ADHOC: + networkType = Ndis802_11IBSS; + DBG_871X("set_mode = IW_MODE_ADHOC\n"); + break; + case IW_MODE_MASTER: + networkType = Ndis802_11APMode; + DBG_871X("set_mode = IW_MODE_MASTER\n"); + //rtw_setopmode_cmd(padapter, networkType,_TRUE); + break; + case IW_MODE_INFRA: + networkType = Ndis802_11Infrastructure; + DBG_871X("set_mode = IW_MODE_INFRA\n"); + break; + + default : + ret = -EINVAL;; + RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("\n Mode: %s is not supported \n", iw_operation_mode[wrqu->mode])); + goto exit; + } + +/* + if(Ndis802_11APMode == networkType) + { + rtw_setopmode_cmd(padapter, networkType,_TRUE); + } + else + { + rtw_setopmode_cmd(padapter, Ndis802_11AutoUnknown,_TRUE); + } +*/ + + if (rtw_set_802_11_infrastructure_mode(padapter, networkType) ==_FALSE){ + + ret = -EPERM; + goto exit; + + } + + rtw_setopmode_cmd(padapter, networkType,_TRUE); + + if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE) + rtw_indicate_connect(padapter); + +exit: + + _func_exit_; + + return ret; + +} + +static int rtw_wx_get_mode(struct net_device *dev, struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,(" rtw_wx_get_mode \n")); + + _func_enter_; + + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) + { + wrqu->mode = IW_MODE_INFRA; + } + else if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) + + { + wrqu->mode = IW_MODE_ADHOC; + } + else if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + { + wrqu->mode = IW_MODE_MASTER; + } else if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE) + wrqu->mode = IW_MODE_MONITOR; + else + wrqu->mode = IW_MODE_AUTO; + + _func_exit_; + + return 0; + +} + + +static int rtw_wx_set_pmkid(struct net_device *dev, + struct iw_request_info *a, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u8 j,blInserted = _FALSE; + int intReturn = _FALSE; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct iw_pmksa* pPMK = ( struct iw_pmksa* ) extra; + u8 strZeroMacAddress[ ETH_ALEN ] = { 0x00 }; + u8 strIssueBssid[ ETH_ALEN ] = { 0x00 }; + +/* + struct iw_pmksa + { + __u32 cmd; + struct sockaddr bssid; + __u8 pmkid[IW_PMKID_LEN]; //IW_PMKID_LEN=16 + } + There are the BSSID information in the bssid.sa_data array. + If cmd is IW_PMKSA_FLUSH, it means the wpa_suppplicant wants to clear all the PMKID information. + If cmd is IW_PMKSA_ADD, it means the wpa_supplicant wants to add a PMKID/BSSID to driver. + If cmd is IW_PMKSA_REMOVE, it means the wpa_supplicant wants to remove a PMKID/BSSID from driver. + */ + + _rtw_memcpy( strIssueBssid, pPMK->bssid.sa_data, ETH_ALEN); + if ( pPMK->cmd == IW_PMKSA_ADD ) + { + DBG_871X( "[rtw_wx_set_pmkid] IW_PMKSA_ADD!\n" ); + if ( _rtw_memcmp( strIssueBssid, strZeroMacAddress, ETH_ALEN ) == _TRUE ) + { + return( intReturn ); + } + else + { + intReturn = _TRUE; + } + blInserted = _FALSE; + + //overwrite PMKID + for(j=0 ; jPMKIDList[j].Bssid, strIssueBssid, ETH_ALEN) ==_TRUE ) + { // BSSID is matched, the same AP => rewrite with new PMKID. + + DBG_871X( "[rtw_wx_set_pmkid] BSSID exists in the PMKList.\n" ); + + _rtw_memcpy( psecuritypriv->PMKIDList[j].PMKID, pPMK->pmkid, IW_PMKID_LEN); + psecuritypriv->PMKIDList[ j ].bUsed = _TRUE; + psecuritypriv->PMKIDIndex = j+1; + blInserted = _TRUE; + break; + } + } + + if(!blInserted) + { + // Find a new entry + DBG_871X( "[rtw_wx_set_pmkid] Use the new entry index = %d for this PMKID.\n", + psecuritypriv->PMKIDIndex ); + + _rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].Bssid, strIssueBssid, ETH_ALEN); + _rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].PMKID, pPMK->pmkid, IW_PMKID_LEN); + + psecuritypriv->PMKIDList[ psecuritypriv->PMKIDIndex ].bUsed = _TRUE; + psecuritypriv->PMKIDIndex++ ; + if(psecuritypriv->PMKIDIndex==16) + { + psecuritypriv->PMKIDIndex =0; + } + } + } + else if ( pPMK->cmd == IW_PMKSA_REMOVE ) + { + DBG_871X( "[rtw_wx_set_pmkid] IW_PMKSA_REMOVE!\n" ); + intReturn = _TRUE; + for(j=0 ; jPMKIDList[j].Bssid, strIssueBssid, ETH_ALEN) ==_TRUE ) + { // BSSID is matched, the same AP => Remove this PMKID information and reset it. + _rtw_memset( psecuritypriv->PMKIDList[ j ].Bssid, 0x00, ETH_ALEN ); + psecuritypriv->PMKIDList[ j ].bUsed = _FALSE; + break; + } + } + } + else if ( pPMK->cmd == IW_PMKSA_FLUSH ) + { + DBG_871X( "[rtw_wx_set_pmkid] IW_PMKSA_FLUSH!\n" ); + _rtw_memset( &psecuritypriv->PMKIDList[ 0 ], 0x00, sizeof( RT_PMKID_LIST ) * NUM_PMKID_CACHE ); + psecuritypriv->PMKIDIndex = 0; + intReturn = _TRUE; + } + return( intReturn ); +} + +static int rtw_wx_get_sens(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + #ifdef CONFIG_PLATFORM_ROCKCHIPS + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + /* + * 20110311 Commented by Jeff + * For rockchip platform's wpa_driver_wext_get_rssi + */ + if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { + //wrqu->sens.value=-padapter->recvpriv.signal_strength; + wrqu->sens.value=-padapter->recvpriv.rssi; + //DBG_871X("%s: %d\n", __FUNCTION__, wrqu->sens.value); + wrqu->sens.fixed = 0; /* no auto select */ + } else + #endif + { + wrqu->sens.value = 0; + wrqu->sens.fixed = 0; /* no auto select */ + wrqu->sens.disabled = 1; + } + return 0; +} + +static int rtw_wx_get_range(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + struct iw_range *range = (struct iw_range *)extra; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + u16 val; + int i; + + _func_enter_; + + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_range. cmd_code=%x\n", info->cmd)); + + wrqu->data.length = sizeof(*range); + _rtw_memset(range, 0, sizeof(*range)); + + /* Let's try to keep this struct in the same order as in + * linux/include/wireless.h + */ + + /* TODO: See what values we can set, and remove the ones we can't + * set, or fill them with some default data. + */ + + /* ~5 Mb/s real (802.11b) */ + range->throughput = 5 * 1000 * 1000; + + // TODO: Not used in 802.11b? +// range->min_nwid; /* Minimal NWID we are able to set */ + // TODO: Not used in 802.11b? +// range->max_nwid; /* Maximal NWID we are able to set */ + + /* Old Frequency (backward compat - moved lower ) */ +// range->old_num_channels; +// range->old_num_frequency; +// range->old_freq[6]; /* Filler to keep "version" at the same offset */ + + /* signal level threshold range */ + + /* Quality of link & SNR stuff */ + /* Quality range (link, level, noise) + * If the quality is absolute, it will be in the range [0 ; max_qual], + * if the quality is dBm, it will be in the range [max_qual ; 0]. + * Don't forget that we use 8 bit arithmetics... + * + * If percentage range is 0~100 + * Signal strength dbm range logical is -100 ~ 0 + * but usually value is -90 ~ -20 + * When CONFIG_SIGNAL_SCALE_MAPPING is defined, dbm range is -95 ~ -45 + */ + range->max_qual.qual = 100; +#ifdef CONFIG_SIGNAL_DISPLAY_DBM + range->max_qual.level = (u8)-100; + range->max_qual.noise = (u8)-100; + range->max_qual.updated = IW_QUAL_ALL_UPDATED; /* Updated all three */ + range->max_qual.updated |= IW_QUAL_DBM; +#else /* !CONFIG_SIGNAL_DISPLAY_DBM */ + //percent values between 0 and 100. + range->max_qual.level = 100; + range->max_qual.noise = 100; + range->max_qual.updated = IW_QUAL_ALL_UPDATED; /* Updated all three */ +#endif /* !CONFIG_SIGNAL_DISPLAY_DBM */ + + /* This should contain the average/typical values of the quality + * indicator. This should be the threshold between a "good" and + * a "bad" link (example : monitor going from green to orange). + * Currently, user space apps like quality monitors don't have any + * way to calibrate the measurement. With this, they can split + * the range between 0 and max_qual in different quality level + * (using a geometric subdivision centered on the average). + * I expect that people doing the user space apps will feedback + * us on which value we need to put in each driver... */ + range->avg_qual.qual = 92; /* > 8% missed beacons is 'bad' */ +#ifdef CONFIG_SIGNAL_DISPLAY_DBM + /* TODO: Find real 'good' to 'bad' threshold value for RSSI */ + range->avg_qual.level = (u8)-70; + range->avg_qual.noise = 0; + range->avg_qual.updated = IW_QUAL_ALL_UPDATED; /* Updated all three */ + range->avg_qual.updated |= IW_QUAL_DBM; +#else /* !CONFIG_SIGNAL_DISPLAY_DBM */ + /* TODO: Find real 'good' to 'bad' threshol value for RSSI */ + range->avg_qual.level = 30; + range->avg_qual.noise = 100; + range->avg_qual.updated = IW_QUAL_ALL_UPDATED; /* Updated all three */ +#endif /* !CONFIG_SIGNAL_DISPLAY_DBM */ + + range->num_bitrates = RATE_COUNT; + + for (i = 0; i < RATE_COUNT && i < IW_MAX_BITRATES; i++) { + range->bitrate[i] = rtw_rates[i]; + } + + range->min_frag = MIN_FRAG_THRESHOLD; + range->max_frag = MAX_FRAG_THRESHOLD; + + range->pm_capa = 0; + + range->we_version_compiled = WIRELESS_EXT; + range->we_version_source = 16; + +// range->retry_capa; /* What retry options are supported */ +// range->retry_flags; /* How to decode max/min retry limit */ +// range->r_time_flags; /* How to decode max/min retry life */ +// range->min_retry; /* Minimal number of retries */ +// range->max_retry; /* Maximal number of retries */ +// range->min_r_time; /* Minimal retry lifetime */ +// range->max_r_time; /* Maximal retry lifetime */ + + for (i = 0, val = 0; i < MAX_CHANNEL_NUM; i++) { + + // Include only legal frequencies for some countries + if(pmlmeext->channel_set[i].ChannelNum != 0) + { + range->freq[val].i = pmlmeext->channel_set[i].ChannelNum; + range->freq[val].m = rtw_ch2freq(pmlmeext->channel_set[i].ChannelNum) * 100000; + range->freq[val].e = 1; + val++; + } + + if (val == IW_MAX_FREQUENCIES) + break; + } + + range->num_channels = val; + range->num_frequency = val; + +// Commented by Albert 2009/10/13 +// The following code will proivde the security capability to network manager. +// If the driver doesn't provide this capability to network manager, +// the WPA/WPA2 routers can't be choosen in the network manager. + +/* +#define IW_SCAN_CAPA_NONE 0x00 +#define IW_SCAN_CAPA_ESSID 0x01 +#define IW_SCAN_CAPA_BSSID 0x02 +#define IW_SCAN_CAPA_CHANNEL 0x04 +#define IW_SCAN_CAPA_MODE 0x08 +#define IW_SCAN_CAPA_RATE 0x10 +#define IW_SCAN_CAPA_TYPE 0x20 +#define IW_SCAN_CAPA_TIME 0x40 +*/ + +#if WIRELESS_EXT > 17 + range->enc_capa = IW_ENC_CAPA_WPA|IW_ENC_CAPA_WPA2| + IW_ENC_CAPA_CIPHER_TKIP|IW_ENC_CAPA_CIPHER_CCMP; +#endif + +#ifdef IW_SCAN_CAPA_ESSID //WIRELESS_EXT > 21 + range->scan_capa = IW_SCAN_CAPA_ESSID | IW_SCAN_CAPA_TYPE |IW_SCAN_CAPA_BSSID| + IW_SCAN_CAPA_CHANNEL|IW_SCAN_CAPA_MODE|IW_SCAN_CAPA_RATE; +#endif + + + _func_exit_; + + return 0; + +} + +//set bssid flow +//s1. rtw_set_802_11_infrastructure_mode() +//s2. rtw_set_802_11_authentication_mode() +//s3. set_802_11_encryption_mode() +//s4. rtw_set_802_11_bssid() +static int rtw_wx_set_wap(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *awrq, + char *extra) +{ + _irqL irqL; + uint ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct sockaddr *temp = (struct sockaddr *)awrq; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + _list *phead; + u8 *dst_bssid, *src_bssid; + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + NDIS_802_11_AUTHENTICATION_MODE authmode; + + _func_enter_; +/* +#ifdef CONFIG_CONCURRENT_MODE + if(padapter->iface_type > PRIMARY_IFACE) + { + ret = -EINVAL; + goto exit; + } +#endif +*/ + +#ifdef CONFIG_CONCURRENT_MODE + if (check_buddy_fwstate(padapter, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE) + { + DBG_871X("set bssid, but buddy_intf is under scanning or linking\n"); + + ret = -EINVAL; + + goto exit; + } +#endif + + rtw_ps_deny(padapter, PS_DENY_JOIN); + if(_FAIL == rtw_pwr_wakeup(padapter)) + { + ret= -1; + goto exit; + } + + if(!padapter->bup){ + ret = -1; + goto exit; + } + + + if (temp->sa_family != ARPHRD_ETHER){ + ret = -EINVAL; + goto exit; + } + + authmode = padapter->securitypriv.ndisauthtype; + _enter_critical_bh(&queue->lock, &irqL); + phead = get_list_head(queue); + pmlmepriv->pscanned = get_next(phead); + + while (1) + { + + if ((rtw_end_of_queue_search(phead, pmlmepriv->pscanned)) == _TRUE) + { +#if 0 + ret = -EINVAL; + goto exit; + + if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) + { + rtw_set_802_11_bssid(padapter, temp->sa_data); + goto exit; + } + else + { + ret = -EINVAL; + goto exit; + } +#endif + + break; + } + + pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list); + + pmlmepriv->pscanned = get_next(pmlmepriv->pscanned); + + dst_bssid = pnetwork->network.MacAddress; + + src_bssid = temp->sa_data; + + if ((_rtw_memcmp(dst_bssid, src_bssid, ETH_ALEN)) == _TRUE) + { + if(!rtw_set_802_11_infrastructure_mode(padapter, pnetwork->network.InfrastructureMode)) + { + ret = -1; + _exit_critical_bh(&queue->lock, &irqL); + goto exit; + } + + break; + } + + } + _exit_critical_bh(&queue->lock, &irqL); + + rtw_set_802_11_authentication_mode(padapter, authmode); + //set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); + if (rtw_set_802_11_bssid(padapter, temp->sa_data) == _FALSE) { + ret = -1; + goto exit; + } + +exit: + + rtw_ps_deny_cancel(padapter, PS_DENY_JOIN); + + _func_exit_; + + return ret; +} + +static int rtw_wx_get_wap(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network; + + wrqu->ap_addr.sa_family = ARPHRD_ETHER; + + _rtw_memset(wrqu->ap_addr.sa_data, 0, ETH_ALEN); + + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_wap\n")); + + _func_enter_; + + if ( ((check_fwstate(pmlmepriv, _FW_LINKED)) == _TRUE) || + ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) == _TRUE) || + ((check_fwstate(pmlmepriv, WIFI_AP_STATE)) == _TRUE) ) + { + + _rtw_memcpy(wrqu->ap_addr.sa_data, pcur_bss->MacAddress, ETH_ALEN); + } + else + { + _rtw_memset(wrqu->ap_addr.sa_data, 0, ETH_ALEN); + } + + _func_exit_; + + return 0; + +} + +static int rtw_wx_set_mlme(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ +#if 0 +/* SIOCSIWMLME data */ +struct iw_mlme +{ + __u16 cmd; /* IW_MLME_* */ + __u16 reason_code; + struct sockaddr addr; +}; +#endif + + int ret=0; + u16 reason; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_mlme *mlme = (struct iw_mlme *) extra; + + + if(mlme==NULL) + return -1; + + DBG_871X("%s\n", __FUNCTION__); + + reason = cpu_to_le16(mlme->reason_code); + + + DBG_871X("%s, cmd=%d, reason=%d\n", __FUNCTION__, mlme->cmd, reason); + + + switch (mlme->cmd) + { + case IW_MLME_DEAUTH: + if(!rtw_set_802_11_disassociate(padapter)) + ret = -1; + break; + + case IW_MLME_DISASSOC: + if(!rtw_set_802_11_disassociate(padapter)) + ret = -1; + + break; + + default: + return -EOPNOTSUPP; + } + + return ret; +} + +static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, + union iwreq_data *wrqu, char *extra) +{ + u8 _status = _FALSE; + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv= &padapter->mlmepriv; + NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; + _irqL irqL; +#ifdef CONFIG_P2P + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); +#endif //CONFIG_P2P + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_set_scan\n")); + +_func_enter_; + + #ifdef DBG_IOCTL + DBG_871X("DBG_IOCTL %s:%d\n",__FUNCTION__, __LINE__); + #endif +/* +#ifdef CONFIG_CONCURRENT_MODE + if(padapter->iface_type > PRIMARY_IFACE) + { + ret = -1; + goto exit; + } +#endif +*/ +#ifdef CONFIG_MP_INCLUDED + if (padapter->registrypriv.mp_mode == 1) + { + DBG_871X(FUNC_ADPT_FMT ": MP mode block Scan request\n", FUNC_ADPT_ARG(padapter)); + ret = -1; + goto exit; + } +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->pbuddy_adapter) { + if (padapter->pbuddy_adapter->registrypriv.mp_mode == 1) + { + DBG_871X(FUNC_ADPT_FMT ": MP mode block Scan request\n", FUNC_ADPT_ARG(padapter->pbuddy_adapter)); + ret = -1; + goto exit; + } + } +#endif //CONFIG_CONCURRENT_MODE +#endif + + rtw_ps_deny(padapter, PS_DENY_SCAN); + if(_FAIL == rtw_pwr_wakeup(padapter)) + { + ret= -1; + goto exit; + } + + if (rtw_is_drv_stopped(padapter)) { + DBG_871X("%s bDriverStopped=_TRUE\n", __func__); + ret= -1; + goto exit; + } + + if(!padapter->bup){ + ret = -1; + goto exit; + } + + if (!rtw_is_hw_init_completed(padapter)) { + ret = -1; + goto exit; + } + +#ifndef CONFIG_DOSCAN_IN_BUSYTRAFFIC + // When Busy Traffic, driver do not site survey. So driver return success. + // wpa_supplicant will not issue SIOCSIWSCAN cmd again after scan timeout. + // modify by thomas 2011-02-22. + if (pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE +#ifdef CONFIG_CONCURRENT_MODE + || rtw_get_buddy_bBusyTraffic(padapter) == _TRUE +#endif //CONFIG_CONCURRENT_MODE + ) + { + indicate_wx_scan_complete_event(padapter); + goto exit; + } +#endif + + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE) + { + indicate_wx_scan_complete_event(padapter); + goto exit; + } + +#ifdef CONFIG_CONCURRENT_MODE + if (check_buddy_fwstate(padapter, + _FW_UNDER_SURVEY|_FW_UNDER_LINKING|WIFI_UNDER_WPS) == _TRUE) + { + indicate_wx_scan_complete_event(padapter); + goto exit; + } +#endif + +#ifdef CONFIG_P2P + if ( pwdinfo->p2p_state != P2P_STATE_NONE ) + { + rtw_p2p_set_pre_state( pwdinfo, rtw_p2p_state( pwdinfo ) ); + rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH); + rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_FULL); + rtw_free_network_queue(padapter, _TRUE); + } +#endif //CONFIG_P2P + + _rtw_memset(ssid, 0, sizeof(NDIS_802_11_SSID)*RTW_SSID_SCAN_AMOUNT); + +#if WIRELESS_EXT >= 17 + if (wrqu->data.length == sizeof(struct iw_scan_req)) + { + struct iw_scan_req *req = (struct iw_scan_req *)extra; + + if (wrqu->data.flags & IW_SCAN_THIS_ESSID) + { + int len = min((int)req->essid_len, IW_ESSID_MAX_SIZE); + + _rtw_memcpy(ssid[0].Ssid, req->essid, len); + ssid[0].SsidLength = len; + + DBG_871X("IW_SCAN_THIS_ESSID, ssid=%s, len=%d\n", req->essid, req->essid_len); + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + + _status = rtw_sitesurvey_cmd(padapter, ssid, 1, NULL, 0); + + _exit_critical_bh(&pmlmepriv->lock, &irqL); + + } + else if (req->scan_type == IW_SCAN_TYPE_PASSIVE) + { + DBG_871X("rtw_wx_set_scan, req->scan_type == IW_SCAN_TYPE_PASSIVE\n"); + } + + } + else +#endif + + if( wrqu->data.length >= WEXT_CSCAN_HEADER_SIZE + && _rtw_memcmp(extra, WEXT_CSCAN_HEADER, WEXT_CSCAN_HEADER_SIZE) == _TRUE + ) + { + int len = wrqu->data.length -WEXT_CSCAN_HEADER_SIZE; + char *pos = extra+WEXT_CSCAN_HEADER_SIZE; + char section; + char sec_len; + int ssid_index = 0; + + //DBG_871X("%s COMBO_SCAN header is recognized\n", __FUNCTION__); + + while(len >= 1) { + section = *(pos++); len-=1; + + switch(section) { + case WEXT_CSCAN_SSID_SECTION: + //DBG_871X("WEXT_CSCAN_SSID_SECTION\n"); + if(len < 1) { + len = 0; + break; + } + + sec_len = *(pos++); len-=1; + + if(sec_len>0 && sec_len<=len) { + ssid[ssid_index].SsidLength = sec_len; + _rtw_memcpy(ssid[ssid_index].Ssid, pos, ssid[ssid_index].SsidLength); + //DBG_871X("%s COMBO_SCAN with specific ssid:%s, %d\n", __FUNCTION__ + // , ssid[ssid_index].Ssid, ssid[ssid_index].SsidLength); + ssid_index++; + } + + pos+=sec_len; len-=sec_len; + break; + + + case WEXT_CSCAN_CHANNEL_SECTION: + //DBG_871X("WEXT_CSCAN_CHANNEL_SECTION\n"); + pos+=1; len-=1; + break; + case WEXT_CSCAN_ACTV_DWELL_SECTION: + //DBG_871X("WEXT_CSCAN_ACTV_DWELL_SECTION\n"); + pos+=2; len-=2; + break; + case WEXT_CSCAN_PASV_DWELL_SECTION: + //DBG_871X("WEXT_CSCAN_PASV_DWELL_SECTION\n"); + pos+=2; len-=2; + break; + case WEXT_CSCAN_HOME_DWELL_SECTION: + //DBG_871X("WEXT_CSCAN_HOME_DWELL_SECTION\n"); + pos+=2; len-=2; + break; + case WEXT_CSCAN_TYPE_SECTION: + //DBG_871X("WEXT_CSCAN_TYPE_SECTION\n"); + pos+=1; len-=1; + break; + #if 0 + case WEXT_CSCAN_NPROBE_SECTION: + DBG_871X("WEXT_CSCAN_NPROBE_SECTION\n"); + break; + #endif + + default: + //DBG_871X("Unknown CSCAN section %c\n", section); + len = 0; // stop parsing + } + //DBG_871X("len:%d\n", len); + + } + + //jeff: it has still some scan paramater to parse, we only do this now... + _status = rtw_set_802_11_bssid_list_scan(padapter, ssid, RTW_SSID_SCAN_AMOUNT); + + } else + + { + _status = rtw_set_802_11_bssid_list_scan(padapter, NULL, 0); + } + + if(_status == _FALSE) + ret = -1; + +exit: + + rtw_ps_deny_cancel(padapter, PS_DENY_SCAN); + + #ifdef DBG_IOCTL + DBG_871X("DBG_IOCTL %s:%d return %d\n",__FUNCTION__, __LINE__, ret); + #endif + +_func_exit_; + + return ret; +} + +static int rtw_wx_get_scan(struct net_device *dev, struct iw_request_info *a, + union iwreq_data *wrqu, char *extra) +{ + _irqL irqL; + _list *plist, *phead; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + char *ev = extra; + char *stop = ev + wrqu->data.length; + u32 ret = 0; + u32 cnt=0; + u32 wait_for_surveydone; + sint wait_status; +#ifdef CONFIG_CONCURRENT_MODE + //PADAPTER pbuddy_adapter = padapter->pbuddy_adapter; + //struct mlme_priv *pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv); +#endif +#ifdef CONFIG_P2P + struct wifidirect_info* pwdinfo = &padapter->wdinfo; +#endif //CONFIG_P2P + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_scan\n")); + RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_, (" Start of Query SIOCGIWSCAN .\n")); + + _func_enter_; + + #ifdef DBG_IOCTL + DBG_871X("DBG_IOCTL %s:%d\n",__FUNCTION__, __LINE__); + #endif +/* +#ifdef CONFIG_CONCURRENT_MODE + if(padapter->iface_type > PRIMARY_IFACE) + { + ret = -EINVAL; + goto exit; + } +#endif +*/ + if (adapter_to_pwrctl(padapter)->brfoffbyhw && rtw_is_drv_stopped(padapter)) { + ret = -EINVAL; + goto exit; + } + +#ifdef CONFIG_P2P + if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + { + wait_for_surveydone = 200; + } + else + { + // P2P is disabled + wait_for_surveydone = 100; + } +#else + { + wait_for_surveydone = 100; + } +#endif //CONFIG_P2P + +#if 1 // Wireless Extension use EAGAIN to try + wait_status = _FW_UNDER_SURVEY +#ifndef CONFIG_ANDROID + | _FW_UNDER_LINKING +#endif + ; + + while (check_fwstate(pmlmepriv, wait_status) == _TRUE) + { + return -EAGAIN; + } +#else + wait_status = _FW_UNDER_SURVEY + #ifndef CONFIG_ANDROID + |_FW_UNDER_LINKING + #endif + ; + + while(check_fwstate(pmlmepriv, wait_status) == _TRUE) + { + rtw_msleep_os(30); + cnt++; + if(cnt > wait_for_surveydone ) + break; + } +#endif + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + while(1) + { + if (rtw_end_of_queue_search(phead,plist)== _TRUE) + break; + + if((stop - ev) < SCAN_ITEM_SIZE) { + ret = -E2BIG; + break; + } + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + + //report network only if the current channel set contains the channel to which this network belongs + if(rtw_ch_set_search_ch(padapter->mlmeextpriv.channel_set, pnetwork->network.Configuration.DSConfig) >= 0 + && rtw_mlme_band_check(padapter, pnetwork->network.Configuration.DSConfig) == _TRUE + && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid)) + ) + { + ev=translate_scan(padapter, a, pnetwork, ev, stop); + } + + plist = get_next(plist); + + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + wrqu->data.length = ev-extra; + wrqu->data.flags = 0; + +exit: + + _func_exit_; + + #ifdef DBG_IOCTL + DBG_871X("DBG_IOCTL %s:%d return %d\n",__FUNCTION__, __LINE__, ret); + #endif + + return ret ; + +} + +//set ssid flow +//s1. rtw_set_802_11_infrastructure_mode() +//s2. set_802_11_authenticaion_mode() +//s3. set_802_11_encryption_mode() +//s4. rtw_set_802_11_ssid() +static int rtw_wx_set_essid(struct net_device *dev, + struct iw_request_info *a, + union iwreq_data *wrqu, char *extra) +{ + _irqL irqL; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + _queue *queue = &pmlmepriv->scanned_queue; + _list *phead; + s8 status = _TRUE; + struct wlan_network *pnetwork = NULL; + NDIS_802_11_AUTHENTICATION_MODE authmode; + NDIS_802_11_SSID ndis_ssid; + u8 *dst_ssid, *src_ssid; + + uint ret = 0, len; + + _func_enter_; + + #ifdef DBG_IOCTL + DBG_871X("DBG_IOCTL %s:%d\n",__FUNCTION__, __LINE__); + #endif + #ifdef CONFIG_WEXT_DONT_JOIN_BYSSID + DBG_871X("%s: CONFIG_WEXT_DONT_JOIN_BYSSID be defined!! only allow bssid joining\n", __func__); + return -EPERM; + #endif +/* +#ifdef CONFIG_CONCURRENT_MODE + if(padapter->iface_type > PRIMARY_IFACE) + { + ret = -EINVAL; + goto exit; + } +#endif +*/ + +#ifdef CONFIG_CONCURRENT_MODE + if (check_buddy_fwstate(padapter, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE) + { + DBG_871X("set ssid, but buddy_intf is under scanning or linking\n"); + + ret = -EINVAL; + + goto exit; + } +#endif + + RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, + ("+rtw_wx_set_essid: fw_state=0x%08x\n", get_fwstate(pmlmepriv))); + + rtw_ps_deny(padapter, PS_DENY_JOIN); + if(_FAIL == rtw_pwr_wakeup(padapter)) + { + ret = -1; + goto exit; + } + + if(!padapter->bup){ + ret = -1; + goto exit; + } + +#if WIRELESS_EXT <= 20 + if ((wrqu->essid.length-1) > IW_ESSID_MAX_SIZE){ +#else + if (wrqu->essid.length > IW_ESSID_MAX_SIZE){ +#endif + ret= -E2BIG; + goto exit; + } + + if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + ret = -1; + goto exit; + } + + authmode = padapter->securitypriv.ndisauthtype; + DBG_871X("=>%s\n",__FUNCTION__); + if (wrqu->essid.flags && wrqu->essid.length) + { + // Commented by Albert 20100519 + // We got the codes in "set_info" function of iwconfig source code. + // ========================================= + // wrq.u.essid.length = strlen(essid) + 1; + // if(we_kernel_version > 20) + // wrq.u.essid.length--; + // ========================================= + // That means, if the WIRELESS_EXT less than or equal to 20, the correct ssid len should subtract 1. +#if WIRELESS_EXT <= 20 + len = ((wrqu->essid.length-1) < IW_ESSID_MAX_SIZE) ? (wrqu->essid.length-1) : IW_ESSID_MAX_SIZE; +#else + len = (wrqu->essid.length < IW_ESSID_MAX_SIZE) ? wrqu->essid.length : IW_ESSID_MAX_SIZE; +#endif + + if( wrqu->essid.length != 33 ) + DBG_871X("ssid=%s, len=%d\n", extra, wrqu->essid.length); + + _rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID)); + ndis_ssid.SsidLength = len; + _rtw_memcpy(ndis_ssid.Ssid, extra, len); + src_ssid = ndis_ssid.Ssid; + + RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, ("rtw_wx_set_essid: ssid=[%s]\n", src_ssid)); + _enter_critical_bh(&queue->lock, &irqL); + phead = get_list_head(queue); + pmlmepriv->pscanned = get_next(phead); + + while (1) + { + if (rtw_end_of_queue_search(phead, pmlmepriv->pscanned) == _TRUE) + { +#if 0 + if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) + { + rtw_set_802_11_ssid(padapter, &ndis_ssid); + + goto exit; + } + else + { + RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_,("rtw_wx_set_ssid(): scanned_queue is empty\n")); + ret = -EINVAL; + goto exit; + } +#endif + RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_warning_, + ("rtw_wx_set_essid: scan_q is empty, set ssid to check if scanning again!\n")); + + break; + } + + pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list); + + pmlmepriv->pscanned = get_next(pmlmepriv->pscanned); + + dst_ssid = pnetwork->network.Ssid.Ssid; + + RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, + ("rtw_wx_set_essid: dst_ssid=%s\n", + pnetwork->network.Ssid.Ssid)); + + if ((_rtw_memcmp(dst_ssid, src_ssid, ndis_ssid.SsidLength) == _TRUE) && + (pnetwork->network.Ssid.SsidLength==ndis_ssid.SsidLength)) + { + RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, + ("rtw_wx_set_essid: find match, set infra mode\n")); + + if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) + { + if(pnetwork->network.InfrastructureMode != pmlmepriv->cur_network.network.InfrastructureMode) + continue; + } + + if (rtw_set_802_11_infrastructure_mode(padapter, pnetwork->network.InfrastructureMode) == _FALSE) + { + ret = -1; + _exit_critical_bh(&queue->lock, &irqL); + goto exit; + } + + break; + } + } + _exit_critical_bh(&queue->lock, &irqL); + RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, + ("set ssid: set_802_11_auth. mode=%d\n", authmode)); + rtw_set_802_11_authentication_mode(padapter, authmode); + //set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); + if (rtw_set_802_11_ssid(padapter, &ndis_ssid) == _FALSE) { + ret = -1; + goto exit; + } + } + +exit: + + rtw_ps_deny_cancel(padapter, PS_DENY_JOIN); + + DBG_871X("<=%s, ret %d\n",__FUNCTION__, ret); + + #ifdef DBG_IOCTL + DBG_871X("DBG_IOCTL %s:%d return %d\n",__FUNCTION__, __LINE__, ret); + #endif + + _func_exit_; + + return ret; +} + +static int rtw_wx_get_essid(struct net_device *dev, + struct iw_request_info *a, + union iwreq_data *wrqu, char *extra) +{ + u32 len,ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network; + + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_essid\n")); + + _func_enter_; + + if ( (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) + { + len = pcur_bss->Ssid.SsidLength; + + wrqu->essid.length = len; + + _rtw_memcpy(extra, pcur_bss->Ssid.Ssid, len); + + wrqu->essid.flags = 1; + } + else + { + ret = -1; + goto exit; + } + +exit: + + _func_exit_; + + return ret; + +} + +static int rtw_wx_set_rate(struct net_device *dev, + struct iw_request_info *a, + union iwreq_data *wrqu, char *extra) +{ + int i, ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u8 datarates[NumRates]; + u32 target_rate = wrqu->bitrate.value; + u32 fixed = wrqu->bitrate.fixed; + u32 ratevalue = 0; + u8 mpdatarate[NumRates]={11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 0xff}; + +_func_enter_; + + RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,(" rtw_wx_set_rate \n")); + RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_,("target_rate = %d, fixed = %d\n",target_rate,fixed)); + + if(target_rate == -1){ + ratevalue = 11; + goto set_rate; + } + target_rate = target_rate/100000; + + switch(target_rate){ + case 10: + ratevalue = 0; + break; + case 20: + ratevalue = 1; + break; + case 55: + ratevalue = 2; + break; + case 60: + ratevalue = 3; + break; + case 90: + ratevalue = 4; + break; + case 110: + ratevalue = 5; + break; + case 120: + ratevalue = 6; + break; + case 180: + ratevalue = 7; + break; + case 240: + ratevalue = 8; + break; + case 360: + ratevalue = 9; + break; + case 480: + ratevalue = 10; + break; + case 540: + ratevalue = 11; + break; + default: + ratevalue = 11; + break; + } + +set_rate: + + for(i=0; ibitrate.fixed = 0; /* no auto select */ + wrqu->bitrate.value = max_rate * 100000; + + return 0; +} + +static int rtw_wx_set_rts(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + _func_enter_; + + if (wrqu->rts.disabled) + padapter->registrypriv.rts_thresh = 2347; + else { + if (wrqu->rts.value < 0 || + wrqu->rts.value > 2347) + return -EINVAL; + + padapter->registrypriv.rts_thresh = wrqu->rts.value; + } + + DBG_871X("%s, rts_thresh=%d\n", __func__, padapter->registrypriv.rts_thresh); + + _func_exit_; + + return 0; + +} + +static int rtw_wx_get_rts(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + _func_enter_; + + DBG_871X("%s, rts_thresh=%d\n", __func__, padapter->registrypriv.rts_thresh); + + wrqu->rts.value = padapter->registrypriv.rts_thresh; + wrqu->rts.fixed = 0; /* no auto select */ + //wrqu->rts.disabled = (wrqu->rts.value == DEFAULT_RTS_THRESHOLD); + + _func_exit_; + + return 0; +} + +static int rtw_wx_set_frag(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + _func_enter_; + + if (wrqu->frag.disabled) + padapter->xmitpriv.frag_len = MAX_FRAG_THRESHOLD; + else { + if (wrqu->frag.value < MIN_FRAG_THRESHOLD || + wrqu->frag.value > MAX_FRAG_THRESHOLD) + return -EINVAL; + + padapter->xmitpriv.frag_len = wrqu->frag.value & ~0x1; + } + + DBG_871X("%s, frag_len=%d\n", __func__, padapter->xmitpriv.frag_len); + + _func_exit_; + + return 0; + +} + +static int rtw_wx_get_frag(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + _func_enter_; + + DBG_871X("%s, frag_len=%d\n", __func__, padapter->xmitpriv.frag_len); + + wrqu->frag.value = padapter->xmitpriv.frag_len; + wrqu->frag.fixed = 0; /* no auto select */ + //wrqu->frag.disabled = (wrqu->frag.value == DEFAULT_FRAG_THRESHOLD); + + _func_exit_; + + return 0; +} + +static int rtw_wx_get_retry(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + //_adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + + wrqu->retry.value = 7; + wrqu->retry.fixed = 0; /* no auto select */ + wrqu->retry.disabled = 1; + + return 0; + +} + +#if 0 +#define IW_ENCODE_INDEX 0x00FF /* Token index (if needed) */ +#define IW_ENCODE_FLAGS 0xFF00 /* Flags defined below */ +#define IW_ENCODE_MODE 0xF000 /* Modes defined below */ +#define IW_ENCODE_DISABLED 0x8000 /* Encoding disabled */ +#define IW_ENCODE_ENABLED 0x0000 /* Encoding enabled */ +#define IW_ENCODE_RESTRICTED 0x4000 /* Refuse non-encoded packets */ +#define IW_ENCODE_OPEN 0x2000 /* Accept non-encoded packets */ +#define IW_ENCODE_NOKEY 0x0800 /* Key is write only, so not present */ +#define IW_ENCODE_TEMP 0x0400 /* Temporary key */ +/* +iwconfig wlan0 key on -> flags = 0x6001 -> maybe it means auto +iwconfig wlan0 key off -> flags = 0x8800 +iwconfig wlan0 key open -> flags = 0x2800 +iwconfig wlan0 key open 1234567890 -> flags = 0x2000 +iwconfig wlan0 key restricted -> flags = 0x4800 +iwconfig wlan0 key open [3] 1234567890 -> flags = 0x2003 +iwconfig wlan0 key restricted [2] 1234567890 -> flags = 0x4002 +iwconfig wlan0 key open [3] -> flags = 0x2803 +iwconfig wlan0 key restricted [2] -> flags = 0x4802 +*/ +#endif + +static int rtw_wx_set_enc(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *keybuf) +{ + u32 key, ret = 0; + u32 keyindex_provided; + NDIS_802_11_WEP wep; + NDIS_802_11_AUTHENTICATION_MODE authmode; + + struct iw_point *erq = &(wrqu->encoding); + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + DBG_871X("+rtw_wx_set_enc, flags=0x%x\n", erq->flags); + + _rtw_memset(&wep, 0, sizeof(NDIS_802_11_WEP)); + + key = erq->flags & IW_ENCODE_INDEX; + + _func_enter_; + + if (erq->flags & IW_ENCODE_DISABLED) + { + DBG_871X("EncryptionDisabled\n"); + padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled; + padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_; + padapter->securitypriv.dot118021XGrpPrivacy=_NO_PRIVACY_; + padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_Open; //open system + authmode = Ndis802_11AuthModeOpen; + padapter->securitypriv.ndisauthtype=authmode; + + goto exit; + } + + if (key) { + if (key > WEP_KEYS) + return -EINVAL; + key--; + keyindex_provided = 1; + } + else + { + keyindex_provided = 0; + key = padapter->securitypriv.dot11PrivacyKeyIndex; + DBG_871X("rtw_wx_set_enc, key=%d\n", key); + } + + //set authentication mode + if(erq->flags & IW_ENCODE_OPEN) + { + DBG_871X("rtw_wx_set_enc():IW_ENCODE_OPEN\n"); + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;//Ndis802_11EncryptionDisabled; + +#ifdef CONFIG_PLATFORM_MT53XX + padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto; +#else + padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_Open; +#endif + + padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_; + padapter->securitypriv.dot118021XGrpPrivacy=_NO_PRIVACY_; + authmode = Ndis802_11AuthModeOpen; + padapter->securitypriv.ndisauthtype=authmode; + } + else if(erq->flags & IW_ENCODE_RESTRICTED) + { + DBG_871X("rtw_wx_set_enc():IW_ENCODE_RESTRICTED\n"); + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; + +#ifdef CONFIG_PLATFORM_MT53XX + padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto; +#else + padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_Shared; +#endif + + padapter->securitypriv.dot11PrivacyAlgrthm=_WEP40_; + padapter->securitypriv.dot118021XGrpPrivacy=_WEP40_; + authmode = Ndis802_11AuthModeShared; + padapter->securitypriv.ndisauthtype=authmode; + } + else + { + DBG_871X("rtw_wx_set_enc():erq->flags=0x%x\n", erq->flags); + + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;//Ndis802_11EncryptionDisabled; + padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_Open; //open system + padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_; + padapter->securitypriv.dot118021XGrpPrivacy=_NO_PRIVACY_; + authmode = Ndis802_11AuthModeOpen; + padapter->securitypriv.ndisauthtype=authmode; + } + + wep.KeyIndex = key; + if (erq->length > 0) + { + wep.KeyLength = erq->length <= 5 ? 5 : 13; + + wep.Length = wep.KeyLength + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial); + } + else + { + wep.KeyLength = 0 ; + + if(keyindex_provided == 1)// set key_id only, no given KeyMaterial(erq->length==0). + { + padapter->securitypriv.dot11PrivacyKeyIndex = key; + + DBG_871X("(keyindex_provided == 1), keyid=%d, key_len=%d\n", key, padapter->securitypriv.dot11DefKeylen[key]); + + switch(padapter->securitypriv.dot11DefKeylen[key]) + { + case 5: + padapter->securitypriv.dot11PrivacyAlgrthm=_WEP40_; + break; + case 13: + padapter->securitypriv.dot11PrivacyAlgrthm=_WEP104_; + break; + default: + padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_; + break; + } + + goto exit; + + } + + } + + wep.KeyIndex |= 0x80000000; + + _rtw_memcpy(wep.KeyMaterial, keybuf, wep.KeyLength); + + if (rtw_set_802_11_add_wep(padapter, &wep) == _FALSE) { + if(rf_on == pwrpriv->rf_pwrstate ) + ret = -EOPNOTSUPP; + goto exit; + } + +exit: + + _func_exit_; + + return ret; + +} + +static int rtw_wx_get_enc(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *keybuf) +{ + uint key, ret =0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *erq = &(wrqu->encoding); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + _func_enter_; + + if(check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) + { + if(check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) != _TRUE) + { + erq->length = 0; + erq->flags |= IW_ENCODE_DISABLED; + return 0; + } + } + + + key = erq->flags & IW_ENCODE_INDEX; + + if (key) { + if (key > WEP_KEYS) + return -EINVAL; + key--; + } else + { + key = padapter->securitypriv.dot11PrivacyKeyIndex; + } + + erq->flags = key + 1; + + //if(padapter->securitypriv.ndisauthtype == Ndis802_11AuthModeOpen) + //{ + // erq->flags |= IW_ENCODE_OPEN; + //} + + switch(padapter->securitypriv.ndisencryptstatus) + { + case Ndis802_11EncryptionNotSupported: + case Ndis802_11EncryptionDisabled: + + erq->length = 0; + erq->flags |= IW_ENCODE_DISABLED; + + break; + + case Ndis802_11Encryption1Enabled: + + erq->length = padapter->securitypriv.dot11DefKeylen[key]; + + if(erq->length) + { + _rtw_memcpy(keybuf, padapter->securitypriv.dot11DefKey[key].skey, padapter->securitypriv.dot11DefKeylen[key]); + + erq->flags |= IW_ENCODE_ENABLED; + + if(padapter->securitypriv.ndisauthtype == Ndis802_11AuthModeOpen) + { + erq->flags |= IW_ENCODE_OPEN; + } + else if(padapter->securitypriv.ndisauthtype == Ndis802_11AuthModeShared) + { + erq->flags |= IW_ENCODE_RESTRICTED; + } + } + else + { + erq->length = 0; + erq->flags |= IW_ENCODE_DISABLED; + } + + break; + + case Ndis802_11Encryption2Enabled: + case Ndis802_11Encryption3Enabled: + + erq->length = 16; + erq->flags |= (IW_ENCODE_ENABLED | IW_ENCODE_OPEN | IW_ENCODE_NOKEY); + + break; + + default: + erq->length = 0; + erq->flags |= IW_ENCODE_DISABLED; + + break; + + } + + _func_exit_; + + return ret; + +} + +static int rtw_wx_get_power(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + //_adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + wrqu->power.value = 0; + wrqu->power.fixed = 0; /* no auto select */ + wrqu->power.disabled = 1; + + return 0; + +} + +static int rtw_wx_set_gen_ie(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + ret = rtw_set_wpa_ie(padapter, extra, wrqu->data.length); + + return ret; +} + +static int rtw_wx_set_auth(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_param *param = (struct iw_param*)&(wrqu->param); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + u32 value = param->value; + int ret = 0; + + switch (param->flags & IW_AUTH_INDEX) { + + case IW_AUTH_WPA_VERSION: +#ifdef CONFIG_WAPI_SUPPORT +#ifndef CONFIG_IOCTL_CFG80211 + padapter->wapiInfo.bWapiEnable = false; + if(value == IW_AUTH_WAPI_VERSION_1) + { + padapter->wapiInfo.bWapiEnable = true; + psecuritypriv->dot11PrivacyAlgrthm = _SMS4_; + psecuritypriv->dot118021XGrpPrivacy = _SMS4_; + psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_WAPI; + pmlmeinfo->auth_algo = psecuritypriv->dot11AuthAlgrthm; + padapter->wapiInfo.extra_prefix_len = WAPI_EXT_LEN; + padapter->wapiInfo.extra_postfix_len = SMS4_MIC_LEN; + } +#endif +#endif + break; + case IW_AUTH_CIPHER_PAIRWISE: + + break; + case IW_AUTH_CIPHER_GROUP: + + break; + case IW_AUTH_KEY_MGMT: +#ifdef CONFIG_WAPI_SUPPORT +#ifndef CONFIG_IOCTL_CFG80211 + DBG_871X("rtw_wx_set_auth: IW_AUTH_KEY_MGMT case \n"); + if(value == IW_AUTH_KEY_MGMT_WAPI_PSK) + padapter->wapiInfo.bWapiPSK = true; + else + padapter->wapiInfo.bWapiPSK = false; + DBG_871X("rtw_wx_set_auth: IW_AUTH_KEY_MGMT bwapipsk %d \n",padapter->wapiInfo.bWapiPSK); +#endif +#endif + /* + * ??? does not use these parameters + */ + break; + + case IW_AUTH_TKIP_COUNTERMEASURES: + { + if ( param->value ) + { // wpa_supplicant is enabling the tkip countermeasure. + padapter->securitypriv.btkip_countermeasure = _TRUE; + } + else + { // wpa_supplicant is disabling the tkip countermeasure. + padapter->securitypriv.btkip_countermeasure = _FALSE; + } + break; + } + case IW_AUTH_DROP_UNENCRYPTED: + { + /* HACK: + * + * wpa_supplicant calls set_wpa_enabled when the driver + * is loaded and unloaded, regardless of if WPA is being + * used. No other calls are made which can be used to + * determine if encryption will be used or not prior to + * association being expected. If encryption is not being + * used, drop_unencrypted is set to false, else true -- we + * can use this to determine if the CAP_PRIVACY_ON bit should + * be set. + */ + + if(padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption1Enabled) + { + break;//it means init value, or using wep, ndisencryptstatus = Ndis802_11Encryption1Enabled, + // then it needn't reset it; + } + + if(param->value){ + padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled; + padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_; + padapter->securitypriv.dot118021XGrpPrivacy=_NO_PRIVACY_; + padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_Open; //open system + padapter->securitypriv.ndisauthtype=Ndis802_11AuthModeOpen; + } + + break; + } + + case IW_AUTH_80211_AUTH_ALG: + + #if defined(CONFIG_ANDROID) || 1 + /* + * It's the starting point of a link layer connection using wpa_supplicant + */ + if(check_fwstate(&padapter->mlmepriv, _FW_LINKED)) { + LeaveAllPowerSaveMode(padapter); + rtw_disassoc_cmd(padapter, 500, _FALSE); + DBG_871X("%s...call rtw_indicate_disconnect\n ",__FUNCTION__); + rtw_indicate_disconnect(padapter, 0, _FALSE); + rtw_free_assoc_resources(padapter, 1); + } + #endif + + + ret = wpa_set_auth_algs(dev, (u32)param->value); + + break; + + case IW_AUTH_WPA_ENABLED: + + //if(param->value) + // padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; //802.1x + //else + // padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open;//open system + + //_disassociate(priv); + + break; + + case IW_AUTH_RX_UNENCRYPTED_EAPOL: + //ieee->ieee802_1x = param->value; + break; + + case IW_AUTH_PRIVACY_INVOKED: + //ieee->privacy_invoked = param->value; + break; + +#ifdef CONFIG_WAPI_SUPPORT +#ifndef CONFIG_IOCTL_CFG80211 + case IW_AUTH_WAPI_ENABLED: + break; +#endif +#endif + + default: + return -EOPNOTSUPP; + + } + + return ret; + +} + +static int rtw_wx_set_enc_ext(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + char *alg_name; + u32 param_len; + struct ieee_param *param = NULL; + struct iw_point *pencoding = &wrqu->encoding; + struct iw_encode_ext *pext = (struct iw_encode_ext *)extra; + int ret=0; + + param_len = sizeof(struct ieee_param) + pext->key_len; + param = (struct ieee_param *)rtw_malloc(param_len); + if (param == NULL) + return -1; + + _rtw_memset(param, 0, param_len); + + param->cmd = IEEE_CMD_SET_ENCRYPTION; + _rtw_memset(param->sta_addr, 0xff, ETH_ALEN); + + + switch (pext->alg) { + case IW_ENCODE_ALG_NONE: + //todo: remove key + //remove = 1; + alg_name = "none"; + break; + case IW_ENCODE_ALG_WEP: + alg_name = "WEP"; + break; + case IW_ENCODE_ALG_TKIP: + alg_name = "TKIP"; + break; + case IW_ENCODE_ALG_CCMP: + alg_name = "CCMP"; + break; +#ifdef CONFIG_IEEE80211W + case IW_ENCODE_ALG_AES_CMAC: + alg_name = "BIP"; + break; +#endif //CONFIG_IEEE80211W +#ifdef CONFIG_WAPI_SUPPORT +#ifndef CONFIG_IOCTL_CFG80211 + case IW_ENCODE_ALG_SM4: + alg_name= "SMS4"; + _rtw_memcpy(param->sta_addr, pext->addr.sa_data, ETH_ALEN); + DBG_871X("rtw_wx_set_enc_ext: SMS4 case \n"); + break; +#endif +#endif + default: + ret = -1; + goto exit; + } + + strncpy((char *)param->u.crypt.alg, alg_name, IEEE_CRYPT_ALG_NAME_LEN); + + if (pext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) + { + param->u.crypt.set_tx = 1; + } + + /* cliW: WEP does not have group key + * just not checking GROUP key setting + */ + if ((pext->alg != IW_ENCODE_ALG_WEP) && + ((pext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) +#ifdef CONFIG_IEEE80211W + || (pext->ext_flags & IW_ENCODE_ALG_AES_CMAC) +#endif //CONFIG_IEEE80211W + )) + { + param->u.crypt.set_tx = 0; + } + + param->u.crypt.idx = (pencoding->flags&0x00FF) -1 ; + + if (pext->ext_flags & IW_ENCODE_EXT_RX_SEQ_VALID) + { +#ifdef CONFIG_WAPI_SUPPORT +#ifndef CONFIG_IOCTL_CFG80211 + if(pext->alg == IW_ENCODE_ALG_SM4) + _rtw_memcpy(param->u.crypt.seq, pext->rx_seq, 16); + else +#endif //CONFIG_IOCTL_CFG80211 +#endif //CONFIG_WAPI_SUPPORT + _rtw_memcpy(param->u.crypt.seq, pext->rx_seq, 8); + } + + if(pext->key_len) + { + param->u.crypt.key_len = pext->key_len; + //_rtw_memcpy(param + 1, pext + 1, pext->key_len); + _rtw_memcpy(param->u.crypt.key, pext + 1, pext->key_len); + } + + if (pencoding->flags & IW_ENCODE_DISABLED) + { + //todo: remove key + //remove = 1; + } + + ret = wpa_set_encryption(dev, param, param_len); + +exit: + if(param) + { + rtw_mfree((u8*)param, param_len); + } + + return ret; +} + + +static int rtw_wx_get_nick(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + //_adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + //struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + //struct security_priv *psecuritypriv = &padapter->securitypriv; + + if(extra) + { + wrqu->data.length = 14; + wrqu->data.flags = 1; + _rtw_memcpy(extra, "", 14); + } + + //rtw_signal_process(pid, SIGUSR1); //for test + + //dump debug info here +/* + u32 dot11AuthAlgrthm; // 802.11 auth, could be open, shared, and 8021x + u32 dot11PrivacyAlgrthm; // This specify the privacy for shared auth. algorithm. + u32 dot118021XGrpPrivacy; // This specify the privacy algthm. used for Grp key + u32 ndisauthtype; + u32 ndisencryptstatus; +*/ + + //DBG_871X("auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\n", + // psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm, + // psecuritypriv->ndisauthtype, psecuritypriv->ndisencryptstatus); + + //DBG_871X("enc_alg=0x%x\n", psecuritypriv->dot11PrivacyAlgrthm); + //DBG_871X("auth_type=0x%x\n", psecuritypriv->ndisauthtype); + //DBG_871X("enc_type=0x%x\n", psecuritypriv->ndisencryptstatus); + +#if 0 + DBG_871X("dbg(0x210)=0x%x\n", rtw_read32(padapter, 0x210)); + DBG_871X("dbg(0x608)=0x%x\n", rtw_read32(padapter, 0x608)); + DBG_871X("dbg(0x280)=0x%x\n", rtw_read32(padapter, 0x280)); + DBG_871X("dbg(0x284)=0x%x\n", rtw_read32(padapter, 0x284)); + DBG_871X("dbg(0x288)=0x%x\n", rtw_read32(padapter, 0x288)); + + DBG_871X("dbg(0x664)=0x%x\n", rtw_read32(padapter, 0x664)); + + + DBG_871X("\n"); + + DBG_871X("dbg(0x430)=0x%x\n", rtw_read32(padapter, 0x430)); + DBG_871X("dbg(0x438)=0x%x\n", rtw_read32(padapter, 0x438)); + + DBG_871X("dbg(0x440)=0x%x\n", rtw_read32(padapter, 0x440)); + + DBG_871X("dbg(0x458)=0x%x\n", rtw_read32(padapter, 0x458)); + + DBG_871X("dbg(0x484)=0x%x\n", rtw_read32(padapter, 0x484)); + DBG_871X("dbg(0x488)=0x%x\n", rtw_read32(padapter, 0x488)); + + DBG_871X("dbg(0x444)=0x%x\n", rtw_read32(padapter, 0x444)); + DBG_871X("dbg(0x448)=0x%x\n", rtw_read32(padapter, 0x448)); + DBG_871X("dbg(0x44c)=0x%x\n", rtw_read32(padapter, 0x44c)); + DBG_871X("dbg(0x450)=0x%x\n", rtw_read32(padapter, 0x450)); +#endif + + return 0; + +} + +static int rtw_wx_read32(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + PADAPTER padapter; + struct iw_point *p; + u16 len; + u32 addr; + u32 data32; + u32 bytes; + u8 *ptmp; + int ret; + + + ret = 0; + padapter = (PADAPTER)rtw_netdev_priv(dev); + p = &wrqu->data; + len = p->length; + if (0 == len) + return -EINVAL; + + ptmp = (u8*)rtw_malloc(len); + if (NULL == ptmp) + return -ENOMEM; + + if (copy_from_user(ptmp, p->pointer, len)) { + ret = -EFAULT; + goto exit; + } + + bytes = 0; + addr = 0; + sscanf(ptmp, "%d,%x", &bytes, &addr); + + switch (bytes) { + case 1: + data32 = rtw_read8(padapter, addr); + sprintf(extra, "0x%02X", data32); + break; + case 2: + data32 = rtw_read16(padapter, addr); + sprintf(extra, "0x%04X", data32); + break; + case 4: + data32 = rtw_read32(padapter, addr); + sprintf(extra, "0x%08X", data32); + break; + default: + DBG_871X(KERN_INFO "%s: usage> read [bytes],[address(hex)]\n", __func__); + ret = -EINVAL; + goto exit; + } + DBG_871X(KERN_INFO "%s: addr=0x%08X data=%s\n", __func__, addr, extra); + +exit: + rtw_mfree(ptmp, len); + + return 0; +} + +static int rtw_wx_write32(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + PADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev); + + u32 addr; + u32 data32; + u32 bytes; + + + bytes = 0; + addr = 0; + data32 = 0; + sscanf(extra, "%d,%x,%x", &bytes, &addr, &data32); + + switch (bytes) { + case 1: + rtw_write8(padapter, addr, (u8)data32); + DBG_871X(KERN_INFO "%s: addr=0x%08X data=0x%02X\n", __func__, addr, (u8)data32); + break; + case 2: + rtw_write16(padapter, addr, (u16)data32); + DBG_871X(KERN_INFO "%s: addr=0x%08X data=0x%04X\n", __func__, addr, (u16)data32); + break; + case 4: + rtw_write32(padapter, addr, data32); + DBG_871X(KERN_INFO "%s: addr=0x%08X data=0x%08X\n", __func__, addr, data32); + break; + default: + DBG_871X(KERN_INFO "%s: usage> write [bytes],[address(hex)],[data(hex)]\n", __func__); + return -EINVAL; + } + + return 0; +} + +static int rtw_wx_read_rf(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u32 path, addr, data32; + + + path = *(u32*)extra; + addr = *((u32*)extra + 1); + data32 = rtw_hal_read_rfreg(padapter, path, addr, 0xFFFFF); +// DBG_871X("%s: path=%d addr=0x%02x data=0x%05x\n", __func__, path, addr, data32); + /* + * IMPORTANT!! + * Only when wireless private ioctl is at odd order, + * "extra" would be copied to user space. + */ + sprintf(extra, "0x%05x", data32); + + return 0; +} + +static int rtw_wx_write_rf(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u32 path, addr, data32; + + + path = *(u32*)extra; + addr = *((u32*)extra + 1); + data32 = *((u32*)extra + 2); +// DBG_871X("%s: path=%d addr=0x%02x data=0x%05x\n", __func__, path, addr, data32); + rtw_hal_write_rfreg(padapter, path, addr, 0xFFFFF, data32); + + return 0; +} + +static int rtw_wx_priv_null(struct net_device *dev, struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + return -1; +} + +static int dummy(struct net_device *dev, struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ + //_adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + //struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + //DBG_871X("cmd_code=%x, fwstate=0x%x\n", a->cmd, get_fwstate(pmlmepriv)); + + return -1; + +} + +static int rtw_wx_set_channel_plan(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + u8 channel_plan_req = (u8) (*((int *)wrqu)); + + if (_SUCCESS != rtw_set_channel_plan(padapter, channel_plan_req)) + return -EPERM; + + return 0; +} + +static int rtw_wx_set_mtk_wps_probe_ie(struct net_device *dev, + struct iw_request_info *a, + union iwreq_data *wrqu, char *b) +{ +#ifdef CONFIG_PLATFORM_MT53XX + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_notice_, + ("WLAN IOCTL: cmd_code=%x, fwstate=0x%x\n", + a->cmd, get_fwstate(pmlmepriv))); +#endif + return 0; +} + +static int rtw_wx_get_sensitivity(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *buf) +{ +#ifdef CONFIG_PLATFORM_MT53XX + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + // Modified by Albert 20110914 + // This is in dbm format for MTK platform. + wrqu->qual.level = padapter->recvpriv.rssi; + DBG_871X(" level = %u\n", wrqu->qual.level ); +#endif + return 0; +} + +static int rtw_wx_set_mtk_wps_ie(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ +#ifdef CONFIG_PLATFORM_MT53XX + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + return rtw_set_wpa_ie(padapter, wrqu->data.pointer, wrqu->data.length); +#else + return 0; +#endif +} + +/* +typedef int (*iw_handler)(struct net_device *dev, struct iw_request_info *info, + union iwreq_data *wrqu, char *extra); +*/ +/* + * For all data larger than 16 octets, we need to use a + * pointer to memory allocated in user space. + */ +static int rtw_drvext_hdl(struct net_device *dev, struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + #if 0 +struct iw_point +{ + void __user *pointer; /* Pointer to the data (in user space) */ + __u16 length; /* number of fields or size in bytes */ + __u16 flags; /* Optional params */ +}; + #endif + +#ifdef CONFIG_DRVEXT_MODULE + u8 res; + struct drvext_handler *phandler; + struct drvext_oidparam *poidparam; + int ret; + u16 len; + u8 *pparmbuf, bset; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *p = &wrqu->data; + + if( (!p->length) || (!p->pointer)){ + ret = -EINVAL; + goto _rtw_drvext_hdl_exit; + } + + + bset = (u8)(p->flags&0xFFFF); + len = p->length; + pparmbuf = (u8*)rtw_malloc(len); + if (pparmbuf == NULL){ + ret = -ENOMEM; + goto _rtw_drvext_hdl_exit; + } + + if(bset)//set info + { + if (copy_from_user(pparmbuf, p->pointer,len)) { + rtw_mfree(pparmbuf, len); + ret = -EFAULT; + goto _rtw_drvext_hdl_exit; + } + } + else//query info + { + + } + + + // + poidparam = (struct drvext_oidparam *)pparmbuf; + + RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_,("drvext set oid subcode [%d], len[%d], InformationBufferLength[%d]\r\n", + poidparam->subcode, poidparam->len, len)); + + + //check subcode + if ( poidparam->subcode >= MAX_DRVEXT_HANDLERS) + { + RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("no matching drvext handlers\r\n")); + ret = -EINVAL; + goto _rtw_drvext_hdl_exit; + } + + + if ( poidparam->subcode >= MAX_DRVEXT_OID_SUBCODES) + { + RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("no matching drvext subcodes\r\n")); + ret = -EINVAL; + goto _rtw_drvext_hdl_exit; + } + + + phandler = drvextoidhandlers + poidparam->subcode; + + if (poidparam->len != phandler->parmsize) + { + RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("no matching drvext param size %d vs %d\r\n", + poidparam->len , phandler->parmsize)); + ret = -EINVAL; + goto _rtw_drvext_hdl_exit; + } + + + res = phandler->handler(&padapter->drvextpriv, bset, poidparam->data); + + if(res==0) + { + ret = 0; + + if (bset == 0x00) {//query info + //_rtw_memcpy(p->pointer, pparmbuf, len); + if (copy_to_user(p->pointer, pparmbuf, len)) + ret = -EFAULT; + } + } + else + ret = -EFAULT; + + +_rtw_drvext_hdl_exit: + + return ret; + +#endif + + return 0; + +} + +static void rtw_dbg_mode_hdl(_adapter *padapter, u32 id, u8 *pdata, u32 len) +{ + pRW_Reg RegRWStruct; + struct rf_reg_param *prfreg; + u8 path; + u8 offset; + u32 value; + + DBG_871X("%s\n", __FUNCTION__); + + switch(id) + { + case GEN_MP_IOCTL_SUBCODE(MP_START): + DBG_871X("871x_driver is only for normal mode, can't enter mp mode\n"); + break; + case GEN_MP_IOCTL_SUBCODE(READ_REG): + RegRWStruct = (pRW_Reg)pdata; + switch (RegRWStruct->width) + { + case 1: + RegRWStruct->value = rtw_read8(padapter, RegRWStruct->offset); + break; + case 2: + RegRWStruct->value = rtw_read16(padapter, RegRWStruct->offset); + break; + case 4: + RegRWStruct->value = rtw_read32(padapter, RegRWStruct->offset); + break; + default: + break; + } + + break; + case GEN_MP_IOCTL_SUBCODE(WRITE_REG): + RegRWStruct = (pRW_Reg)pdata; + switch (RegRWStruct->width) + { + case 1: + rtw_write8(padapter, RegRWStruct->offset, (u8)RegRWStruct->value); + break; + case 2: + rtw_write16(padapter, RegRWStruct->offset, (u16)RegRWStruct->value); + break; + case 4: + rtw_write32(padapter, RegRWStruct->offset, (u32)RegRWStruct->value); + break; + default: + break; + } + + break; + case GEN_MP_IOCTL_SUBCODE(READ_RF_REG): + + prfreg = (struct rf_reg_param *)pdata; + + path = (u8)prfreg->path; + offset = (u8)prfreg->offset; + + value = rtw_hal_read_rfreg(padapter, path, offset, 0xffffffff); + + prfreg->value = value; + + break; + case GEN_MP_IOCTL_SUBCODE(WRITE_RF_REG): + + prfreg = (struct rf_reg_param *)pdata; + + path = (u8)prfreg->path; + offset = (u8)prfreg->offset; + value = prfreg->value; + + rtw_hal_write_rfreg(padapter, path, offset, 0xffffffff, value); + + break; + case GEN_MP_IOCTL_SUBCODE(TRIGGER_GPIO): + DBG_871X("==> trigger gpio 0\n"); + rtw_hal_set_hwreg(padapter, HW_VAR_TRIGGER_GPIO_0, 0); + break; +#ifdef CONFIG_BT_COEXIST + case GEN_MP_IOCTL_SUBCODE(SET_DM_BT): + DBG_871X("==> set dm_bt_coexist:%x\n",*(u8 *)pdata); + rtw_hal_set_hwreg(padapter, HW_VAR_BT_SET_COEXIST, pdata); + break; + case GEN_MP_IOCTL_SUBCODE(DEL_BA): + DBG_871X("==> delete ba:%x\n",*(u8 *)pdata); + rtw_hal_set_hwreg(padapter, HW_VAR_BT_ISSUE_DELBA, pdata); + break; +#endif +#ifdef DBG_CONFIG_ERROR_DETECT + case GEN_MP_IOCTL_SUBCODE(GET_WIFI_STATUS): + *pdata = rtw_hal_sreset_get_wifi_status(padapter); + break; +#endif + + default: + break; + } + +} + +static int rtw_mp_ioctl_hdl(struct net_device *dev, struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + u32 BytesRead, BytesWritten, BytesNeeded; + struct oid_par_priv oid_par; + struct mp_ioctl_handler *phandler; + struct mp_ioctl_param *poidparam; + uint status=0; + u16 len; + u8 *pparmbuf = NULL, bset; + PADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev); + struct iw_point *p = &wrqu->data; + + //DBG_871X("+rtw_mp_ioctl_hdl\n"); + + //mutex_lock(&ioctl_mutex); + + if ((!p->length) || (!p->pointer)) { + ret = -EINVAL; + goto _rtw_mp_ioctl_hdl_exit; + } + + pparmbuf = NULL; + bset = (u8)(p->flags & 0xFFFF); + len = p->length; + pparmbuf = (u8*)rtw_malloc(len); + if (pparmbuf == NULL){ + ret = -ENOMEM; + goto _rtw_mp_ioctl_hdl_exit; + } + + if (copy_from_user(pparmbuf, p->pointer, len)) { + ret = -EFAULT; + goto _rtw_mp_ioctl_hdl_exit; + } + + poidparam = (struct mp_ioctl_param *)pparmbuf; + RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, + ("rtw_mp_ioctl_hdl: subcode [%d], len[%d], buffer_len[%d]\r\n", + poidparam->subcode, poidparam->len, len)); + + if (poidparam->subcode >= MAX_MP_IOCTL_SUBCODE) { + RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_err_, ("no matching drvext subcodes\r\n")); + ret = -EINVAL; + goto _rtw_mp_ioctl_hdl_exit; + } + + //DBG_871X("%s: %d\n", __func__, poidparam->subcode); +#ifdef CONFIG_MP_INCLUDED +if (padapter->registrypriv.mp_mode == 1) +{ + phandler = mp_ioctl_hdl + poidparam->subcode; + + if ((phandler->paramsize != 0) && (poidparam->len < phandler->paramsize)) + { + RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_err_, + ("no matching drvext param size %d vs %d\r\n", + poidparam->len, phandler->paramsize)); + ret = -EINVAL; + goto _rtw_mp_ioctl_hdl_exit; + } + + if (phandler->handler) + { + oid_par.adapter_context = padapter; + oid_par.oid = phandler->oid; + oid_par.information_buf = poidparam->data; + oid_par.information_buf_len = poidparam->len; + oid_par.dbg = 0; + + BytesWritten = 0; + BytesNeeded = 0; + + if (bset) { + oid_par.bytes_rw = &BytesRead; + oid_par.bytes_needed = &BytesNeeded; + oid_par.type_of_oid = SET_OID; + } else { + oid_par.bytes_rw = &BytesWritten; + oid_par.bytes_needed = &BytesNeeded; + oid_par.type_of_oid = QUERY_OID; + } + + status = phandler->handler(&oid_par); + + //todo:check status, BytesNeeded, etc. + } + else { + DBG_871X("rtw_mp_ioctl_hdl(): err!, subcode=%d, oid=%d, handler=%p\n", + poidparam->subcode, phandler->oid, phandler->handler); + ret = -EFAULT; + goto _rtw_mp_ioctl_hdl_exit; + } +} +else +#endif +{ + rtw_dbg_mode_hdl(padapter, poidparam->subcode, poidparam->data, poidparam->len); +} + + if (bset == 0x00) {//query info + if (copy_to_user(p->pointer, pparmbuf, len)) + ret = -EFAULT; + } + + if (status) { + ret = -EFAULT; + goto _rtw_mp_ioctl_hdl_exit; + } + +_rtw_mp_ioctl_hdl_exit: + + if (pparmbuf) + rtw_mfree(pparmbuf, len); + + //mutex_unlock(&ioctl_mutex); + + return ret; +} + +static int rtw_get_ap_info(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int bssid_match, ret = 0; + u32 cnt=0, wpa_ielen; + _irqL irqL; + _list *plist, *phead; + unsigned char *pbuf; + u8 bssid[ETH_ALEN]; + char data[32]; + struct wlan_network *pnetwork = NULL; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + _queue *queue = &(pmlmepriv->scanned_queue); + struct iw_point *pdata = &wrqu->data; + + DBG_871X("+rtw_get_aplist_info\n"); + + if (rtw_is_drv_stopped(padapter) || (pdata == NULL)) { + ret= -EINVAL; + goto exit; + } + + while((check_fwstate(pmlmepriv, (_FW_UNDER_SURVEY|_FW_UNDER_LINKING))) == _TRUE) + { + rtw_msleep_os(30); + cnt++; + if(cnt > 100) + break; + } + + + //pdata->length = 0;//? + pdata->flags = 0; + if(pdata->length>=32) + { + if(copy_from_user(data, pdata->pointer, 32)) + { + ret= -EINVAL; + goto exit; + } + } + else + { + ret= -EINVAL; + goto exit; + } + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + while(1) + { + if (rtw_end_of_queue_search(phead,plist)== _TRUE) + break; + + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + + //if(hwaddr_aton_i(pdata->pointer, bssid)) + if(hwaddr_aton_i(data, bssid)) + { + DBG_871X("Invalid BSSID '%s'.\n", (u8*)data); + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + return -EINVAL; + } + + + if(_rtw_memcmp(bssid, pnetwork->network.MacAddress, ETH_ALEN) == _TRUE)//BSSID match, then check if supporting wpa/wpa2 + { + DBG_871X("BSSID:" MAC_FMT "\n", MAC_ARG(bssid)); + + pbuf = rtw_get_wpa_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength-12); + if(pbuf && (wpa_ielen>0)) + { + pdata->flags = 1; + break; + } + + pbuf = rtw_get_wpa2_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength-12); + if(pbuf && (wpa_ielen>0)) + { + pdata->flags = 2; + break; + } + + } + + plist = get_next(plist); + + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + if(pdata->length>=34) + { + if(copy_to_user((u8*)pdata->pointer+32, (u8*)&pdata->flags, 1)) + { + ret= -EINVAL; + goto exit; + } + } + +exit: + + return ret; + +} + +static int rtw_set_pid(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = rtw_netdev_priv(dev); + int *pdata = (int *)wrqu; + int selector; + + if (rtw_is_drv_stopped(padapter) || (pdata == NULL)) { + ret= -EINVAL; + goto exit; + } + + selector = *pdata; + if(selector < 3 && selector >=0) { + padapter->pid[selector] = *(pdata+1); + #ifdef CONFIG_GLOBAL_UI_PID + ui_pid[selector] = *(pdata+1); + #endif + DBG_871X("%s set pid[%d]=%d\n", __FUNCTION__, selector ,padapter->pid[selector]); + } + else + DBG_871X("%s selector %d error\n", __FUNCTION__, selector); + +exit: + + return ret; + +} + +static int rtw_wps_start(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + u32 u32wps_start = 0; + unsigned int uintRet = 0; + + if (RTW_CANNOT_RUN(padapter) || (NULL == pdata)) { + ret= -EINVAL; + goto exit; + } + + uintRet = copy_from_user( ( void* ) &u32wps_start, pdata->pointer, 4 ); + if ( u32wps_start == 0 ) + { + u32wps_start = *extra; + } + + DBG_871X( "[%s] wps_start = %d\n", __FUNCTION__, u32wps_start ); + + if ( u32wps_start == 1 ) // WPS Start + { + rtw_led_control(padapter, LED_CTL_START_WPS); + } + else if ( u32wps_start == 2 ) // WPS Stop because of wps success + { + rtw_led_control(padapter, LED_CTL_STOP_WPS); + } + else if ( u32wps_start == 3 ) // WPS Stop because of wps fail + { + rtw_led_control(padapter, LED_CTL_STOP_WPS_FAIL); + } + +#ifdef CONFIG_INTEL_WIDI + process_intel_widi_wps_status(padapter, u32wps_start); +#endif //CONFIG_INTEL_WIDI + +exit: + + return ret; + +} + +#ifdef CONFIG_P2P +static int rtw_wext_p2p_enable(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + enum P2P_ROLE init_role = P2P_ROLE_DISABLE; + + if(*extra == '0' ) + init_role = P2P_ROLE_DISABLE; + else if(*extra == '1') + init_role = P2P_ROLE_DEVICE; + else if(*extra == '2') + init_role = P2P_ROLE_CLIENT; + else if(*extra == '3') + init_role = P2P_ROLE_GO; + + if(_FAIL == rtw_p2p_enable(padapter, init_role)) + { + ret = -EFAULT; + goto exit; + } + + //set channel/bandwidth + if(init_role != P2P_ROLE_DISABLE) + { + u8 channel, ch_offset; + u16 bwmode; + + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN)) + { + // Stay at the listen state and wait for discovery. + channel = pwdinfo->listen_channel; + pwdinfo->operating_channel = pwdinfo->listen_channel; + ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + bwmode = CHANNEL_WIDTH_20; + } +#ifdef CONFIG_CONCURRENT_MODE + else if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) + { + _adapter *pbuddy_adapter = padapter->pbuddy_adapter; + //struct wifidirect_info *pbuddy_wdinfo = &pbuddy_adapter->wdinfo; + struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv; + struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; + + _set_timer( &pwdinfo->ap_p2p_switch_timer, pwdinfo->ext_listen_interval ); + if ( check_fwstate( pbuddy_mlmepriv, _FW_LINKED ) ) + { + pwdinfo->operating_channel = pbuddy_mlmeext->cur_channel; + // How about the ch_offset and bwmode ?? + } + else + { + pwdinfo->operating_channel = pwdinfo->listen_channel; + } + + channel = pbuddy_mlmeext->cur_channel; + ch_offset = pbuddy_mlmeext->cur_ch_offset; + bwmode = pbuddy_mlmeext->cur_bwmode; + } +#endif + else + { + pwdinfo->operating_channel = pmlmeext->cur_channel; + + channel = pwdinfo->operating_channel; + ch_offset = pmlmeext->cur_ch_offset; + bwmode = pmlmeext->cur_bwmode; + } + + set_channel_bwmode(padapter, channel, ch_offset, bwmode); + } + +exit: + return ret; + +} + +static int rtw_p2p_set_go_nego_ssid(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); + + DBG_871X( "[%s] ssid = %s, len = %zu\n", __FUNCTION__, extra, strlen( extra ) ); + _rtw_memcpy( pwdinfo->nego_ssid, extra, strlen( extra ) ); + pwdinfo->nego_ssidlen = strlen( extra ); + + return ret; + +} + + +static int rtw_p2p_set_intent(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); + u8 intent = pwdinfo->intent; + + extra[ wrqu->data.length ] = 0x00; + + intent = rtw_atoi( extra ); + + if ( intent <= 15 ) + { + pwdinfo->intent= intent; + } + else + { + ret = -1; + } + + DBG_871X( "[%s] intent = %d\n", __FUNCTION__, intent); + + return ret; + +} + +static int rtw_p2p_set_listen_ch(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); + u8 listen_ch = pwdinfo->listen_channel; // Listen channel number + + extra[ wrqu->data.length ] = 0x00; + listen_ch = rtw_atoi( extra ); + + if ( ( listen_ch == 1 ) || ( listen_ch == 6 ) || ( listen_ch == 11 ) ) + { + pwdinfo->listen_channel = listen_ch; + set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + } + else + { + ret = -1; + } + + DBG_871X( "[%s] listen_ch = %d\n", __FUNCTION__, pwdinfo->listen_channel ); + + return ret; + +} + +static int rtw_p2p_set_op_ch(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ +// Commented by Albert 20110524 +// This function is used to set the operating channel if the driver will become the group owner + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); + u8 op_ch = pwdinfo->operating_channel; // Operating channel number + + extra[ wrqu->data.length ] = 0x00; + + op_ch = ( u8 ) rtw_atoi( extra ); + if ( op_ch > 0 ) + { + pwdinfo->operating_channel = op_ch; + } + else + { + ret = -1; + } + + DBG_871X( "[%s] op_ch = %d\n", __FUNCTION__, pwdinfo->operating_channel ); + + return ret; + +} + + +static int rtw_p2p_profilefound(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); + + // Comment by Albert 2010/10/13 + // Input data format: + // Ex: 0 + // Ex: 1XX:XX:XX:XX:XX:XXYYSSID + // 0 => Reflush the profile record list. + // 1 => Add the profile list + // XX:XX:XX:XX:XX:XX => peer's MAC Address ( ex: 00:E0:4C:00:00:01 ) + // YY => SSID Length + // SSID => SSID for persistence group + + DBG_871X( "[%s] In value = %s, len = %d \n", __FUNCTION__, extra, wrqu->data.length -1); + + + // The upper application should pass the SSID to driver by using this rtw_p2p_profilefound function. + if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + { + if ( extra[ 0 ] == '0' ) + { + // Remove all the profile information of wifidirect_info structure. + _rtw_memset( &pwdinfo->profileinfo[ 0 ], 0x00, sizeof( struct profile_info ) * P2P_MAX_PERSISTENT_GROUP_NUM ); + pwdinfo->profileindex = 0; + } + else + { + if ( pwdinfo->profileindex >= P2P_MAX_PERSISTENT_GROUP_NUM ) + { + ret = -1; + } + else + { + int jj, kk; + + // Add this profile information into pwdinfo->profileinfo + // Ex: 1XX:XX:XX:XX:XX:XXYYSSID + for( jj = 0, kk = 1; jj < ETH_ALEN; jj++, kk += 3 ) + { + pwdinfo->profileinfo[ pwdinfo->profileindex ].peermac[ jj ] = key_2char2num(extra[ kk ], extra[ kk+ 1 ]); + } + + //pwdinfo->profileinfo[ pwdinfo->profileindex ].ssidlen = ( extra[18] - '0' ) * 10 + ( extra[ 19 ] - '0' ); + //_rtw_memcpy( pwdinfo->profileinfo[ pwdinfo->profileindex ].ssid, &extra[ 20 ], pwdinfo->profileinfo[ pwdinfo->profileindex ].ssidlen ); + pwdinfo->profileindex++; + } + } + } + + return ret; + +} + +static int rtw_p2p_setDN(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); + + + DBG_871X( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); + _rtw_memset( pwdinfo->device_name, 0x00, WPS_MAX_DEVICE_NAME_LEN ); + _rtw_memcpy( pwdinfo->device_name, extra, wrqu->data.length - 1 ); + pwdinfo->device_name_len = wrqu->data.length - 1; + + return ret; + +} + + +static int rtw_p2p_get_status(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); +#ifdef CONFIG_CONCURRENT_MODE + _adapter *pbuddy_adapter = padapter->pbuddy_adapter; + struct wifidirect_info *pbuddy_wdinfo = &pbuddy_adapter->wdinfo; + struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv; + struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; +#endif + + if ( padapter->bShowGetP2PState ) + { + DBG_871X( "[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), + pwdinfo->p2p_peer_interface_addr[ 0 ], pwdinfo->p2p_peer_interface_addr[ 1 ], pwdinfo->p2p_peer_interface_addr[ 2 ], + pwdinfo->p2p_peer_interface_addr[ 3 ], pwdinfo->p2p_peer_interface_addr[ 4 ], pwdinfo->p2p_peer_interface_addr[ 5 ]); + } + + // Commented by Albert 2010/10/12 + // Because of the output size limitation, I had removed the "Role" information. + // About the "Role" information, we will use the new private IOCTL to get the "Role" information. + sprintf( extra, "\n\nStatus=%.2d\n", rtw_p2p_state(pwdinfo) ); + wrqu->data.length = strlen( extra ); + + return ret; + +} + +// Commented by Albert 20110520 +// This function will return the config method description +// This config method description will show us which config method the remote P2P device is intented to use +// by sending the provisioning discovery request frame. + +static int rtw_p2p_get_req_cm(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); + + sprintf( extra, "\n\nCM=%s\n", pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req ); + wrqu->data.length = strlen( extra ); + return ret; + +} + + +static int rtw_p2p_get_role(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); + + + DBG_871X( "[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), + pwdinfo->p2p_peer_interface_addr[ 0 ], pwdinfo->p2p_peer_interface_addr[ 1 ], pwdinfo->p2p_peer_interface_addr[ 2 ], + pwdinfo->p2p_peer_interface_addr[ 3 ], pwdinfo->p2p_peer_interface_addr[ 4 ], pwdinfo->p2p_peer_interface_addr[ 5 ]); + + sprintf( extra, "\n\nRole=%.2d\n", rtw_p2p_role(pwdinfo) ); + wrqu->data.length = strlen( extra ); + return ret; + +} + + +static int rtw_p2p_get_peer_ifaddr(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); + + + DBG_871X( "[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), + pwdinfo->p2p_peer_interface_addr[ 0 ], pwdinfo->p2p_peer_interface_addr[ 1 ], pwdinfo->p2p_peer_interface_addr[ 2 ], + pwdinfo->p2p_peer_interface_addr[ 3 ], pwdinfo->p2p_peer_interface_addr[ 4 ], pwdinfo->p2p_peer_interface_addr[ 5 ]); + + sprintf( extra, "\nMAC %.2X:%.2X:%.2X:%.2X:%.2X:%.2X", + pwdinfo->p2p_peer_interface_addr[ 0 ], pwdinfo->p2p_peer_interface_addr[ 1 ], pwdinfo->p2p_peer_interface_addr[ 2 ], + pwdinfo->p2p_peer_interface_addr[ 3 ], pwdinfo->p2p_peer_interface_addr[ 4 ], pwdinfo->p2p_peer_interface_addr[ 5 ]); + wrqu->data.length = strlen( extra ); + return ret; + +} + +static int rtw_p2p_get_peer_devaddr(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) + +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); + + DBG_871X( "[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), + pwdinfo->rx_prov_disc_info.peerDevAddr[ 0 ], pwdinfo->rx_prov_disc_info.peerDevAddr[ 1 ], + pwdinfo->rx_prov_disc_info.peerDevAddr[ 2 ], pwdinfo->rx_prov_disc_info.peerDevAddr[ 3 ], + pwdinfo->rx_prov_disc_info.peerDevAddr[ 4 ], pwdinfo->rx_prov_disc_info.peerDevAddr[ 5 ]); + sprintf( extra, "\n%.2X%.2X%.2X%.2X%.2X%.2X", + pwdinfo->rx_prov_disc_info.peerDevAddr[ 0 ], pwdinfo->rx_prov_disc_info.peerDevAddr[ 1 ], + pwdinfo->rx_prov_disc_info.peerDevAddr[ 2 ], pwdinfo->rx_prov_disc_info.peerDevAddr[ 3 ], + pwdinfo->rx_prov_disc_info.peerDevAddr[ 4 ], pwdinfo->rx_prov_disc_info.peerDevAddr[ 5 ]); + wrqu->data.length = strlen( extra ); + return ret; + +} + +static int rtw_p2p_get_peer_devaddr_by_invitation(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) + +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); + + DBG_871X( "[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), + pwdinfo->p2p_peer_device_addr[ 0 ], pwdinfo->p2p_peer_device_addr[ 1 ], + pwdinfo->p2p_peer_device_addr[ 2 ], pwdinfo->p2p_peer_device_addr[ 3 ], + pwdinfo->p2p_peer_device_addr[ 4 ], pwdinfo->p2p_peer_device_addr[ 5 ]); + sprintf( extra, "\nMAC %.2X:%.2X:%.2X:%.2X:%.2X:%.2X", + pwdinfo->p2p_peer_device_addr[ 0 ], pwdinfo->p2p_peer_device_addr[ 1 ], + pwdinfo->p2p_peer_device_addr[ 2 ], pwdinfo->p2p_peer_device_addr[ 3 ], + pwdinfo->p2p_peer_device_addr[ 4 ], pwdinfo->p2p_peer_device_addr[ 5 ]); + wrqu->data.length = strlen( extra ); + return ret; + +} + +static int rtw_p2p_get_groupid(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) + +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); + + sprintf( extra, "\n%.2X:%.2X:%.2X:%.2X:%.2X:%.2X %s", + pwdinfo->groupid_info.go_device_addr[ 0 ], pwdinfo->groupid_info.go_device_addr[ 1 ], + pwdinfo->groupid_info.go_device_addr[ 2 ], pwdinfo->groupid_info.go_device_addr[ 3 ], + pwdinfo->groupid_info.go_device_addr[ 4 ], pwdinfo->groupid_info.go_device_addr[ 5 ], + pwdinfo->groupid_info.ssid); + wrqu->data.length = strlen( extra ); + return ret; + +} + +static int rtw_p2p_get_op_ch(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) + +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); + + + DBG_871X( "[%s] Op_ch = %02x\n", __FUNCTION__, pwdinfo->operating_channel); + + sprintf( extra, "\n\nOp_ch=%.2d\n", pwdinfo->operating_channel ); + wrqu->data.length = strlen( extra ); + return ret; + +} + +static int rtw_p2p_get_wps_configmethod(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra, char *subcmd) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u8 peerMAC[ETH_ALEN] = { 0x00 }; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + _irqL irqL; + _list * plist,*phead; + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + u8 blnMatch = 0; + u16 attr_content = 0; + uint attr_contentlen = 0; + u8 attr_content_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 }; + + // Commented by Albert 20110727 + // The input data is the MAC address which the application wants to know its WPS config method. + // After knowing its WPS config method, the application can decide the config method for provisioning discovery. + // Format: iwpriv wlanx p2p_get_wpsCM 00:E0:4C:00:00:05 + + DBG_871X("[%s] data = %s\n", __FUNCTION__, subcmd); + + macstr2num(peerMAC, subcmd); + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + while (1) + { + if (rtw_end_of_queue_search(phead, plist) == _TRUE) break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) + { + u8 *wpsie; + uint wpsie_len = 0; + + // The mac address is matched. + + if ( (wpsie=rtw_get_wps_ie_from_scan_queue( &pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &wpsie_len, pnetwork->network.Reserved[0])) ) + { + rtw_get_wps_attr_content(wpsie, wpsie_len, WPS_ATTR_CONF_METHOD, (u8 *)&attr_content, &attr_contentlen); + if (attr_contentlen) + { + attr_content = be16_to_cpu(attr_content); + sprintf(attr_content_str, "\n\nM=%.4d", attr_content); + blnMatch = 1; + } + } + + break; + } + + plist = get_next(plist); + + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + if (!blnMatch) + { + sprintf(attr_content_str, "\n\nM=0000"); + } + + wrqu->data.length = strlen(attr_content_str); + _rtw_memcpy(extra, attr_content_str, wrqu->data.length); + + return ret; + +} + +#ifdef CONFIG_WFD +static int rtw_p2p_get_peer_wfd_port(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); + + DBG_871X( "[%s] p2p_state = %d\n", __FUNCTION__, rtw_p2p_state(pwdinfo) ); + + sprintf( extra, "\n\nPort=%d\n", pwdinfo->wfd_info->peer_rtsp_ctrlport ); + DBG_871X( "[%s] remote port = %d\n", __FUNCTION__, pwdinfo->wfd_info->peer_rtsp_ctrlport ); + + wrqu->data.length = strlen( extra ); + return ret; + +} + +static int rtw_p2p_get_peer_wfd_preferred_connection(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); + + sprintf( extra, "\n\nwfd_pc=%d\n", pwdinfo->wfd_info->wfd_pc ); + DBG_871X( "[%s] wfd_pc = %d\n", __FUNCTION__, pwdinfo->wfd_info->wfd_pc ); + + wrqu->data.length = strlen( extra ); + pwdinfo->wfd_info->wfd_pc = _FALSE; // Reset the WFD preferred connection to P2P + return ret; + +} + +static int rtw_p2p_get_peer_wfd_session_available(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); + + sprintf( extra, "\n\nwfd_sa=%d\n", pwdinfo->wfd_info->peer_session_avail ); + DBG_871X( "[%s] wfd_sa = %d\n", __FUNCTION__, pwdinfo->wfd_info->peer_session_avail ); + + wrqu->data.length = strlen( extra ); + pwdinfo->wfd_info->peer_session_avail = _TRUE; // Reset the WFD session available + return ret; + +} +#endif /* CONFIG_WFD */ + +static int rtw_p2p_get_go_device_address(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra, char *subcmd) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u8 peerMAC[ETH_ALEN] = { 0x00 }; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + _irqL irqL; + _list *plist, *phead; + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + u8 blnMatch = 0; + u8 *p2pie; + uint p2pielen = 0, attr_contentlen = 0; + u8 attr_content[100] = { 0x00 }; + u8 go_devadd_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 }; + + // Commented by Albert 20121209 + // The input data is the GO's interface address which the application wants to know its device address. + // Format: iwpriv wlanx p2p_get2 go_devadd=00:E0:4C:00:00:05 + + DBG_871X("[%s] data = %s\n", __FUNCTION__, subcmd); + + macstr2num(peerMAC, subcmd); + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + while (1) + { + if (rtw_end_of_queue_search(phead, plist) == _TRUE) break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) + { + // Commented by Albert 2011/05/18 + // Match the device address located in the P2P IE + // This is for the case that the P2P device address is not the same as the P2P interface address. + + p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen); + if (p2pie) { + while (p2pie) + { + // The P2P Device ID attribute is included in the Beacon frame. + // The P2P Device Info attribute is included in the probe response frame. + + _rtw_memset(attr_content, 0x00, 100); + if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen)) + { + // Handle the P2P Device ID attribute of Beacon first + blnMatch = 1; + break; + + } else if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen)) + { + // Handle the P2P Device Info attribute of probe response + blnMatch = 1; + break; + } + + //Get the next P2P IE + p2pie = rtw_get_p2p_ie(p2pie + p2pielen, BSS_EX_TLV_IES_LEN(&pnetwork->network) - (p2pie + p2pielen - BSS_EX_TLV_IES(&pnetwork->network)), NULL, &p2pielen); + } + } + } + + plist = get_next(plist); + + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + if (!blnMatch) + { + sprintf(go_devadd_str, "\n\ndev_add=NULL"); + } else + { + sprintf(go_devadd_str, "\n\ndev_add=%.2X:%.2X:%.2X:%.2X:%.2X:%.2X", + attr_content[0], attr_content[1], attr_content[2], attr_content[3], attr_content[4], attr_content[5]); + } + + wrqu->data.length = strlen(go_devadd_str); + _rtw_memcpy(extra, go_devadd_str, wrqu->data.length); + + return ret; + +} + +static int rtw_p2p_get_device_type(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra, char *subcmd) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u8 peerMAC[ETH_ALEN] = { 0x00 }; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + _irqL irqL; + _list *plist, *phead; + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + u8 blnMatch = 0; + u8 dev_type[8] = { 0x00 }; + uint dev_type_len = 0; + u8 dev_type_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 }; // +9 is for the str "dev_type=", we have to clear it at wrqu->data.pointer + + // Commented by Albert 20121209 + // The input data is the MAC address which the application wants to know its device type. + // Such user interface could know the device type. + // Format: iwpriv wlanx p2p_get2 dev_type=00:E0:4C:00:00:05 + + DBG_871X("[%s] data = %s\n", __FUNCTION__, subcmd); + + macstr2num(peerMAC, subcmd); + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + while (1) + { + if (rtw_end_of_queue_search(phead, plist) == _TRUE) break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) + { + u8 *wpsie; + uint wpsie_len = 0; + + // The mac address is matched. + + if ( (wpsie=rtw_get_wps_ie_from_scan_queue( &pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &wpsie_len, pnetwork->network.Reserved[0])) ) + { + rtw_get_wps_attr_content(wpsie, wpsie_len, WPS_ATTR_PRIMARY_DEV_TYPE, dev_type, &dev_type_len); + if (dev_type_len) + { + u16 type = 0; + + _rtw_memcpy(&type, dev_type, 2); + type = be16_to_cpu(type); + sprintf(dev_type_str, "\n\nN=%.2d", type); + blnMatch = 1; + } + } + break; + } + + plist = get_next(plist); + + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + if (!blnMatch) + { + sprintf(dev_type_str, "\n\nN=00"); + } + + wrqu->data.length = strlen(dev_type_str); + _rtw_memcpy(extra, dev_type_str, wrqu->data.length); + + return ret; + +} + +static int rtw_p2p_get_device_name(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra, char *subcmd) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u8 peerMAC[ETH_ALEN] = { 0x00 }; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + _irqL irqL; + _list *plist, *phead; + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + u8 blnMatch = 0; + u8 dev_name[WPS_MAX_DEVICE_NAME_LEN] = { 0x00 }; + uint dev_len = 0; + u8 dev_name_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 }; + + // Commented by Albert 20121225 + // The input data is the MAC address which the application wants to know its device name. + // Such user interface could show peer device's device name instead of ssid. + // Format: iwpriv wlanx p2p_get2 devN=00:E0:4C:00:00:05 + + DBG_871X("[%s] data = %s\n", __FUNCTION__, subcmd); + + macstr2num(peerMAC, subcmd); + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + while (1) + { + if (rtw_end_of_queue_search(phead, plist) == _TRUE) break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) + { + u8 *wpsie; + uint wpsie_len = 0; + + // The mac address is matched. + + if ( (wpsie=rtw_get_wps_ie_from_scan_queue( &pnetwork->network.IEs[0], pnetwork->network.IELength, NULL, &wpsie_len, pnetwork->network.Reserved[0])) ) + { + rtw_get_wps_attr_content(wpsie, wpsie_len, WPS_ATTR_DEVICE_NAME, dev_name, &dev_len); + if (dev_len) + { + sprintf(dev_name_str, "\n\nN=%s", dev_name); + blnMatch = 1; + } + } + break; + } + + plist = get_next(plist); + + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + if (!blnMatch) + { + sprintf(dev_name_str, "\n\nN=0000"); + } + + wrqu->data.length = strlen(dev_name_str); + _rtw_memcpy(extra, dev_name_str, wrqu->data.length); + + return ret; + +} + +static int rtw_p2p_get_invitation_procedure(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra, char *subcmd) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u8 peerMAC[ETH_ALEN] = { 0x00 }; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + _irqL irqL; + _list *plist, *phead; + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + u8 blnMatch = 0; + u8 *p2pie; + uint p2pielen = 0, attr_contentlen = 0; + u8 attr_content[2] = { 0x00 }; + u8 inv_proc_str[P2P_PRIVATE_IOCTL_SET_LEN] = { 0x00 }; + + // Commented by Ouden 20121226 + // The application wants to know P2P initation procedure is support or not. + // Format: iwpriv wlanx p2p_get2 InvProc=00:E0:4C:00:00:05 + + DBG_871X("[%s] data = %s\n", __FUNCTION__, subcmd); + + macstr2num(peerMAC, subcmd); + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + while (1) + { + if (rtw_end_of_queue_search(phead, plist) == _TRUE) break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + if (_rtw_memcmp(pnetwork->network.MacAddress, peerMAC, ETH_ALEN)) + { + // Commented by Albert 20121226 + // Match the device address located in the P2P IE + // This is for the case that the P2P device address is not the same as the P2P interface address. + + p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen); + if (p2pie) { + while (p2pie) + { + //_rtw_memset( attr_content, 0x00, 2); + if (rtw_get_p2p_attr_content(p2pie, p2pielen, P2P_ATTR_CAPABILITY, attr_content, &attr_contentlen)) + { + // Handle the P2P capability attribute + blnMatch = 1; + break; + + } + + //Get the next P2P IE + p2pie = rtw_get_p2p_ie(p2pie + p2pielen, BSS_EX_TLV_IES_LEN(&pnetwork->network) - (p2pie + p2pielen - BSS_EX_TLV_IES(&pnetwork->network)), NULL, &p2pielen); + } + } + } + + plist = get_next(plist); + + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + if (!blnMatch) + { + sprintf(inv_proc_str, "\nIP=-1"); + } else + { + if ((attr_content[0] & 0x20) == 0x20) + sprintf(inv_proc_str, "\nIP=1"); + else + sprintf(inv_proc_str, "\nIP=0"); + } + + wrqu->data.length = strlen(inv_proc_str); + _rtw_memcpy(extra, inv_proc_str, wrqu->data.length); + + return ret; + +} + +static int rtw_p2p_connect(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); + u8 peerMAC[ ETH_ALEN ] = { 0x00 }; + int jj,kk; + u8 peerMACStr[ ETH_ALEN * 2 ] = { 0x00 }; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + _irqL irqL; + _list *plist, *phead; + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + uint uintPeerChannel = 0; +#ifdef CONFIG_CONCURRENT_MODE + _adapter *pbuddy_adapter = padapter->pbuddy_adapter; + struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv; + struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; +#endif // CONFIG_CONCURRENT_MODE + + // Commented by Albert 20110304 + // The input data contains two informations. + // 1. First information is the MAC address which wants to formate with + // 2. Second information is the WPS PINCode or "pbc" string for push button method + // Format: 00:E0:4C:00:00:05 + // Format: 00:E0:4C:00:00:05 + + DBG_871X( "[%s] data = %s\n", __FUNCTION__, extra ); + + if ( pwdinfo->p2p_state == P2P_STATE_NONE ) + { + DBG_871X( "[%s] WiFi Direct is disable!\n", __FUNCTION__ ); + return ret; + } + +#ifdef CONFIG_INTEL_WIDI + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) { + DBG_871X( "[%s] WiFi is under survey!\n", __FUNCTION__ ); + return ret; + } +#endif //CONFIG_INTEL_WIDI + + if ( pwdinfo->ui_got_wps_info == P2P_NO_WPSINFO ) + { + return -1; + } + + for( jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3 ) + { + peerMAC[ jj ] = key_2char2num( extra[kk], extra[kk+ 1] ); + } + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + while(1) + { + if (rtw_end_of_queue_search(phead,plist)== _TRUE) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + if ( _rtw_memcmp( pnetwork->network.MacAddress, peerMAC, ETH_ALEN ) ) + { + if (pnetwork->network.Configuration.DSConfig != 0) + uintPeerChannel = pnetwork->network.Configuration.DSConfig; + else if (pwdinfo->nego_req_info.peer_ch != 0) + uintPeerChannel = pnetwork->network.Configuration.DSConfig = pwdinfo->nego_req_info.peer_ch; + else{ + /* Unexpected case */ + uintPeerChannel = 0; + DBG_871X("%s uintPeerChannel = 0\n", __func__); + } + break; + } + + plist = get_next(plist); + + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + if ( uintPeerChannel ) + { +#ifdef CONFIG_CONCURRENT_MODE + if ( check_fwstate( pbuddy_mlmepriv, _FW_LINKED ) ) + { + _cancel_timer_ex( &pwdinfo->ap_p2p_switch_timer ); + } +#endif // CONFIG_CONCURRENT_MODE + + _rtw_memset( &pwdinfo->nego_req_info, 0x00, sizeof( struct tx_nego_req_info ) ); + _rtw_memset( &pwdinfo->groupid_info, 0x00, sizeof( struct group_id_info ) ); + + pwdinfo->nego_req_info.peer_channel_num[ 0 ] = uintPeerChannel; + _rtw_memcpy( pwdinfo->nego_req_info.peerDevAddr, pnetwork->network.MacAddress, ETH_ALEN ); + pwdinfo->nego_req_info.benable = _TRUE; + + _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer ); + if ( rtw_p2p_state(pwdinfo) != P2P_STATE_GONEGO_OK ) + { + // Restore to the listen state if the current p2p state is not nego OK + rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN ); + } + + rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); + rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_ING); + +#ifdef CONFIG_CONCURRENT_MODE + if ( check_fwstate( pbuddy_mlmepriv, _FW_LINKED ) ) + { + // Have to enter the power saving with the AP + set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode); + + issue_nulldata(pbuddy_adapter, NULL, 1, 3, 500); + } +#endif // CONFIG_CONCURRENT_MODE + + DBG_871X( "[%s] Start PreTx Procedure!\n", __FUNCTION__ ); + _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); +#ifdef CONFIG_CONCURRENT_MODE + if ( check_fwstate( pbuddy_mlmepriv, _FW_LINKED ) ) + { + _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_CONCURRENT_GO_NEGO_TIMEOUT ); + } + else + { + _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_GO_NEGO_TIMEOUT ); + } +#else + _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_GO_NEGO_TIMEOUT ); +#endif // CONFIG_CONCURRENT_MODE + + } + else + { + DBG_871X( "[%s] Not Found in Scanning Queue~\n", __FUNCTION__ ); +#ifdef CONFIG_INTEL_WIDI + _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer ); + rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH); + rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE); + rtw_free_network_queue(padapter, _TRUE); + /** + * For WiDi, if we can't find candidate device in scanning queue, + * driver will do scanning itself + */ + _enter_critical_bh(&pmlmepriv->lock, &irqL); + rtw_sitesurvey_cmd(padapter, NULL, 0, NULL, 0); + _exit_critical_bh(&pmlmepriv->lock, &irqL); +#endif //CONFIG_INTEL_WIDI + ret = -1; + } +exit: + return ret; +} + +static int rtw_p2p_invite_req(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); + int jj,kk; + u8 peerMACStr[ ETH_ALEN * 2 ] = { 0x00 }; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + _list *plist, *phead; + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + uint uintPeerChannel = 0; + u8 attr_content[50] = { 0x00 }, _status = 0; + u8 *p2pie; + uint p2pielen = 0, attr_contentlen = 0; + _irqL irqL; + struct tx_invite_req_info* pinvite_req_info = &pwdinfo->invitereq_info; +#ifdef CONFIG_CONCURRENT_MODE + _adapter *pbuddy_adapter = padapter->pbuddy_adapter; + struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv; + struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; +#endif // CONFIG_CONCURRENT_MODE + + // Commented by Albert 20120321 + // The input data contains two informations. + // 1. First information is the P2P device address which you want to send to. + // 2. Second information is the group id which combines with GO's mac address, space and GO's ssid. + // Command line sample: iwpriv wlan0 p2p_set invite="00:11:22:33:44:55 00:E0:4C:00:00:05 DIRECT-xy" + // Format: 00:11:22:33:44:55 00:E0:4C:00:00:05 DIRECT-xy + + DBG_871X( "[%s] data = %s\n", __FUNCTION__, extra ); + + if ( wrqu->data.length <= 37 ) + { + DBG_871X( "[%s] Wrong format!\n", __FUNCTION__ ); + return ret; + } + + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + { + DBG_871X( "[%s] WiFi Direct is disable!\n", __FUNCTION__ ); + return ret; + } + else + { + // Reset the content of struct tx_invite_req_info + pinvite_req_info->benable = _FALSE; + _rtw_memset( pinvite_req_info->go_bssid, 0x00, ETH_ALEN ); + _rtw_memset( pinvite_req_info->go_ssid, 0x00, WLAN_SSID_MAXLEN ); + pinvite_req_info->ssidlen = 0x00; + pinvite_req_info->operating_ch = pwdinfo->operating_channel; + _rtw_memset( pinvite_req_info->peer_macaddr, 0x00, ETH_ALEN ); + pinvite_req_info->token = 3; + } + + for( jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3 ) + { + pinvite_req_info->peer_macaddr[ jj ] = key_2char2num( extra[kk], extra[kk+ 1] ); + } + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + while(1) + { + if (rtw_end_of_queue_search(phead,plist)== _TRUE) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + + // Commented by Albert 2011/05/18 + // Match the device address located in the P2P IE + // This is for the case that the P2P device address is not the same as the P2P interface address. + + p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen); + if (p2pie) { + // The P2P Device ID attribute is included in the Beacon frame. + // The P2P Device Info attribute is included in the probe response frame. + + if ( rtw_get_p2p_attr_content( p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen) ) + { + // Handle the P2P Device ID attribute of Beacon first + if ( _rtw_memcmp( attr_content, pinvite_req_info->peer_macaddr, ETH_ALEN ) ) + { + uintPeerChannel = pnetwork->network.Configuration.DSConfig; + break; + } + } + else if ( rtw_get_p2p_attr_content( p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen) ) + { + // Handle the P2P Device Info attribute of probe response + if ( _rtw_memcmp( attr_content, pinvite_req_info->peer_macaddr, ETH_ALEN ) ) + { + uintPeerChannel = pnetwork->network.Configuration.DSConfig; + break; + } + } + + } + + plist = get_next(plist); + + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + +#ifdef CONFIG_WFD + if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST) && uintPeerChannel) { + struct wifi_display_info *pwfd_info = pwdinfo->wfd_info; + u8 *wfd_ie; + uint wfd_ielen = 0; + + wfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen); + if (wfd_ie) { + u8 *wfd_devinfo; + uint wfd_devlen; + + DBG_871X( "[%s] Found WFD IE!\n", __FUNCTION__ ); + wfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen); + if (wfd_devinfo) { + u16 wfd_devinfo_field = 0; + + // Commented by Albert 20120319 + // The first two bytes are the WFD device information field of WFD device information subelement. + // In big endian format. + wfd_devinfo_field = RTW_GET_BE16(wfd_devinfo); + if ( wfd_devinfo_field & WFD_DEVINFO_SESSION_AVAIL ) + { + pwfd_info->peer_session_avail = _TRUE; + } + else + { + pwfd_info->peer_session_avail = _FALSE; + } + } + } + + if ( _FALSE == pwfd_info->peer_session_avail ) + { + DBG_871X( "[%s] WFD Session not avaiable!\n", __FUNCTION__ ); + goto exit; + } + } +#endif /* CONFIG_WFD */ + + if ( uintPeerChannel ) + { +#ifdef CONFIG_CONCURRENT_MODE + if ( check_fwstate( pbuddy_mlmepriv, _FW_LINKED ) ) + { + _cancel_timer_ex( &pwdinfo->ap_p2p_switch_timer ); + } +#endif // CONFIG_CONCURRENT_MODE + + // Store the GO's bssid + for( jj = 0, kk = 18; jj < ETH_ALEN; jj++, kk += 3 ) + { + pinvite_req_info->go_bssid[ jj ] = key_2char2num( extra[kk], extra[kk+ 1] ); + } + + // Store the GO's ssid + pinvite_req_info->ssidlen = wrqu->data.length - 36; + _rtw_memcpy( pinvite_req_info->go_ssid, &extra[ 36 ], (u32) pinvite_req_info->ssidlen ); + pinvite_req_info->benable = _TRUE; + pinvite_req_info->peer_ch = uintPeerChannel; + + rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); + rtw_p2p_set_state(pwdinfo, P2P_STATE_TX_INVITE_REQ); + +#ifdef CONFIG_CONCURRENT_MODE + if ( check_fwstate( pbuddy_mlmepriv, _FW_LINKED ) ) + { + // Have to enter the power saving with the AP + set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode); + + issue_nulldata(pbuddy_adapter, NULL, 1, 3, 500); + } + else + { + set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + } +#else + set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); +#endif + + _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); + +#ifdef CONFIG_CONCURRENT_MODE + if ( check_fwstate( pbuddy_mlmepriv, _FW_LINKED ) ) + { + _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_CONCURRENT_INVITE_TIMEOUT ); + } + else + { + _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_INVITE_TIMEOUT ); + } +#else + _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_INVITE_TIMEOUT ); +#endif // CONFIG_CONCURRENT_MODE + + + } + else + { + DBG_871X( "[%s] NOT Found in the Scanning Queue!\n", __FUNCTION__ ); + } +exit: + + return ret; + +} + +static int rtw_p2p_set_persistent(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); + int jj,kk; + u8 peerMACStr[ ETH_ALEN * 2 ] = { 0x00 }; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + _list *plist, *phead; + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + uint uintPeerChannel = 0; + u8 attr_content[50] = { 0x00 }, _status = 0; + u8 *p2pie; + uint p2pielen = 0, attr_contentlen = 0; + _irqL irqL; + struct tx_invite_req_info* pinvite_req_info = &pwdinfo->invitereq_info; +#ifdef CONFIG_CONCURRENT_MODE + _adapter *pbuddy_adapter = padapter->pbuddy_adapter; + struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv; + struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; +#endif // CONFIG_CONCURRENT_MODE + + // Commented by Albert 20120328 + // The input data is 0 or 1 + // 0: disable persistent group functionality + // 1: enable persistent group founctionality + + DBG_871X( "[%s] data = %s\n", __FUNCTION__, extra ); + + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + { + DBG_871X( "[%s] WiFi Direct is disable!\n", __FUNCTION__ ); + return ret; + } + else + { + if ( extra[ 0 ] == '0' ) // Disable the persistent group function. + { + pwdinfo->persistent_supported = _FALSE; + } + else if ( extra[ 0 ] == '1' ) // Enable the persistent group function. + { + pwdinfo->persistent_supported = _TRUE; + } + else + { + pwdinfo->persistent_supported = _FALSE; + } + } + printk( "[%s] persistent_supported = %d\n", __FUNCTION__, pwdinfo->persistent_supported ); + +exit: + + return ret; + +} + +static int hexstr2bin(const char *hex, u8 *buf, size_t len) +{ + size_t i; + int a; + const char *ipos = hex; + u8 *opos = buf; + + for (i = 0; i < len; i++) { + a = hex2byte_i(ipos); + if (a < 0) + return -1; + *opos++ = a; + ipos += 2; + } + return 0; +} + +static int uuid_str2bin(const char *str, u8 *bin) +{ + const char *pos; + u8 *opos; + + pos = str; + opos = bin; + + if (hexstr2bin(pos, opos, 4)) + return -1; + pos += 8; + opos += 4; + + if (*pos++ != '-' || hexstr2bin(pos, opos, 2)) + return -1; + pos += 4; + opos += 2; + + if (*pos++ != '-' || hexstr2bin(pos, opos, 2)) + return -1; + pos += 4; + opos += 2; + + if (*pos++ != '-' || hexstr2bin(pos, opos, 2)) + return -1; + pos += 4; + opos += 2; + + if (*pos++ != '-' || hexstr2bin(pos, opos, 6)) + return -1; + + return 0; +} + +static int rtw_p2p_set_wps_uuid(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct wifidirect_info *pwdinfo = &(padapter->wdinfo); + + DBG_871X("[%s] data = %s\n", __FUNCTION__, extra); + + if ((36 == strlen(extra)) && (uuid_str2bin(extra, pwdinfo->uuid) == 0)) + { + pwdinfo->external_uuid = 1; + } else { + pwdinfo->external_uuid = 0; + ret = -EINVAL; + } + + return ret; + +} +#ifdef CONFIG_WFD +static int rtw_p2p_set_pc(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); + u8 peerMAC[ ETH_ALEN ] = { 0x00 }; + int jj,kk; + u8 peerMACStr[ ETH_ALEN * 2 ] = { 0x00 }; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + _list *plist, *phead; + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + u8 attr_content[50] = { 0x00 }, _status = 0; + u8 *p2pie; + uint p2pielen = 0, attr_contentlen = 0; + _irqL irqL; + uint uintPeerChannel = 0; +#ifdef CONFIG_CONCURRENT_MODE + _adapter *pbuddy_adapter = padapter->pbuddy_adapter; + struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; +#endif // CONFIG_CONCURRENT_MODE + + struct wifi_display_info* pwfd_info = pwdinfo->wfd_info; + + // Commented by Albert 20120512 + // 1. Input information is the MAC address which wants to know the Preferred Connection bit (PC bit) + // Format: 00:E0:4C:00:00:05 + + DBG_871X( "[%s] data = %s\n", __FUNCTION__, extra ); + + if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + { + DBG_871X( "[%s] WiFi Direct is disable!\n", __FUNCTION__ ); + return ret; + } + + for( jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3 ) + { + peerMAC[ jj ] = key_2char2num( extra[kk], extra[kk+ 1] ); + } + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + while(1) + { + if (rtw_end_of_queue_search(phead,plist)== _TRUE) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + + // Commented by Albert 2011/05/18 + // Match the device address located in the P2P IE + // This is for the case that the P2P device address is not the same as the P2P interface address. + + p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen); + if (p2pie) { + // The P2P Device ID attribute is included in the Beacon frame. + // The P2P Device Info attribute is included in the probe response frame. + printk( "[%s] Got P2P IE\n", __FUNCTION__ ); + if ( rtw_get_p2p_attr_content( p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen) ) + { + // Handle the P2P Device ID attribute of Beacon first + printk( "[%s] P2P_ATTR_DEVICE_ID \n", __FUNCTION__ ); + if ( _rtw_memcmp( attr_content, peerMAC, ETH_ALEN ) ) + { + uintPeerChannel = pnetwork->network.Configuration.DSConfig; + break; + } + } + else if ( rtw_get_p2p_attr_content( p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen) ) + { + // Handle the P2P Device Info attribute of probe response + printk( "[%s] P2P_ATTR_DEVICE_INFO \n", __FUNCTION__ ); + if ( _rtw_memcmp( attr_content, peerMAC, ETH_ALEN ) ) + { + uintPeerChannel = pnetwork->network.Configuration.DSConfig; + break; + } + } + + } + + plist = get_next(plist); + + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + printk( "[%s] channel = %d\n", __FUNCTION__, uintPeerChannel ); + + if ( uintPeerChannel ) + { + u8 *wfd_ie; + uint wfd_ielen = 0; + + wfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen); + if (wfd_ie) { + u8 *wfd_devinfo; + uint wfd_devlen; + + DBG_871X( "[%s] Found WFD IE!\n", __FUNCTION__ ); + wfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen); + if (wfd_devinfo) { + u16 wfd_devinfo_field = 0; + + // Commented by Albert 20120319 + // The first two bytes are the WFD device information field of WFD device information subelement. + // In big endian format. + wfd_devinfo_field = RTW_GET_BE16(wfd_devinfo); + if ( wfd_devinfo_field & WFD_DEVINFO_PC_TDLS ) + { + pwfd_info->wfd_pc = _TRUE; + } + else + { + pwfd_info->wfd_pc = _FALSE; + } + } + } + } + else + { + DBG_871X( "[%s] NOT Found in the Scanning Queue!\n", __FUNCTION__ ); + } + +exit: + + return ret; + +} + +static int rtw_p2p_set_wfd_device_type(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); + struct wifi_display_info *pwfd_info = pwdinfo->wfd_info; + + // Commented by Albert 20120328 + // The input data is 0 or 1 + // 0: specify to Miracast source device + // 1 or others: specify to Miracast sink device (display device) + + DBG_871X( "[%s] data = %s\n", __FUNCTION__, extra ); + + if ( extra[ 0 ] == '0' ) // Set to Miracast source device. + { + pwfd_info->wfd_device_type = WFD_DEVINFO_SOURCE; + } + else // Set to Miracast sink device. + { + pwfd_info->wfd_device_type = WFD_DEVINFO_PSINK; + } + +exit: + + return ret; + +} + +static int rtw_p2p_set_wfd_enable(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ +// Commented by Kurt 20121206 +// This function is used to set wfd enabled + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); + + if (*extra == '0') + rtw_wfd_enable(padapter, 0); + else if (*extra == '1') + rtw_wfd_enable(padapter, 1); + + DBG_871X( "[%s] wfd_enable = %d\n", __FUNCTION__, pwdinfo->wfd_info->wfd_enable ); + + return ret; + +} + +static int rtw_p2p_set_driver_iface(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ +// Commented by Kurt 20121206 +// This function is used to set driver iface is WEXT or CFG80211 + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); + + if(*extra == '1' ) + { + pwdinfo->driver_interface = DRIVER_WEXT; + DBG_871X( "[%s] driver_interface = WEXT\n", __FUNCTION__); + } + else if(*extra == '2') + { + pwdinfo->driver_interface = DRIVER_CFG80211; + DBG_871X( "[%s] driver_interface = CFG80211\n", __FUNCTION__); + } + + return ret; + +} + +// To set the WFD session available to enable or disable +static int rtw_p2p_set_sa(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); + struct wifi_display_info *pwfd_info = pwdinfo->wfd_info; + + DBG_871X( "[%s] data = %s\n", __FUNCTION__, extra ); + + if( 0 ) + { + DBG_871X( "[%s] WiFi Direct is disable!\n", __FUNCTION__ ); + return ret; + } + else + { + if ( extra[ 0 ] == '0' ) // Disable the session available. + { + pwdinfo->session_available = _FALSE; + } + else if ( extra[ 0 ] == '1' ) // Enable the session available. + { + pwdinfo->session_available = _TRUE; + } + else + { + pwdinfo->session_available = _FALSE; + } + } + printk( "[%s] session available = %d\n", __FUNCTION__, pwdinfo->session_available ); + +exit: + + return ret; + +} +#endif /* CONFIG_WFD */ + +static int rtw_p2p_prov_disc(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); + u8 peerMAC[ ETH_ALEN ] = { 0x00 }; + int jj,kk; + u8 peerMACStr[ ETH_ALEN * 2 ] = { 0x00 }; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + _list *plist, *phead; + _queue *queue = &(pmlmepriv->scanned_queue); + struct wlan_network *pnetwork = NULL; + uint uintPeerChannel = 0; + u8 attr_content[100] = { 0x00 }, _status = 0; + u8 *p2pie; + uint p2pielen = 0, attr_contentlen = 0; + _irqL irqL; +#ifdef CONFIG_CONCURRENT_MODE + _adapter *pbuddy_adapter = padapter->pbuddy_adapter; + struct mlme_priv *pbuddy_mlmepriv = &pbuddy_adapter->mlmepriv; + struct mlme_ext_priv *pbuddy_mlmeext = &pbuddy_adapter->mlmeextpriv; +#endif // CONFIG_CONCURRENT_MODE + + // Commented by Albert 20110301 + // The input data contains two informations. + // 1. First information is the MAC address which wants to issue the provisioning discovery request frame. + // 2. Second information is the WPS configuration method which wants to discovery + // Format: 00:E0:4C:00:00:05_display + // Format: 00:E0:4C:00:00:05_keypad + // Format: 00:E0:4C:00:00:05_pbc + // Format: 00:E0:4C:00:00:05_label + + DBG_871X( "[%s] data = %s\n", __FUNCTION__, extra ); + + if ( pwdinfo->p2p_state == P2P_STATE_NONE ) + { + DBG_871X( "[%s] WiFi Direct is disable!\n", __FUNCTION__ ); + return ret; + } + else + { +#ifdef CONFIG_INTEL_WIDI + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) { + DBG_871X( "[%s] WiFi is under survey!\n", __FUNCTION__ ); + return ret; + } +#endif //CONFIG_INTEL_WIDI + + // Reset the content of struct tx_provdisc_req_info excluded the wps_config_method_request. + _rtw_memset( pwdinfo->tx_prov_disc_info.peerDevAddr, 0x00, ETH_ALEN ); + _rtw_memset( pwdinfo->tx_prov_disc_info.peerIFAddr, 0x00, ETH_ALEN ); + _rtw_memset( &pwdinfo->tx_prov_disc_info.ssid, 0x00, sizeof( NDIS_802_11_SSID ) ); + pwdinfo->tx_prov_disc_info.peer_channel_num[ 0 ] = 0; + pwdinfo->tx_prov_disc_info.peer_channel_num[ 1 ] = 0; + pwdinfo->tx_prov_disc_info.benable = _FALSE; + } + + for( jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3 ) + { + peerMAC[ jj ] = key_2char2num( extra[kk], extra[kk+ 1] ); + } + + if ( _rtw_memcmp( &extra[ 18 ], "display", 7 ) ) + { + pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_DISPLYA; + } + else if ( _rtw_memcmp( &extra[ 18 ], "keypad", 7 ) ) + { + pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_KEYPAD; + } + else if ( _rtw_memcmp( &extra[ 18 ], "pbc", 3 ) ) + { + pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON; + } + else if ( _rtw_memcmp( &extra[ 18 ], "label", 5 ) ) + { + pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_LABEL; + } + else + { + DBG_871X( "[%s] Unknown WPS config methodn", __FUNCTION__ ); + return( ret ); + } + + _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + phead = get_list_head(queue); + plist = get_next(phead); + + while(1) + { + if (rtw_end_of_queue_search(phead,plist)== _TRUE) + break; + + if( uintPeerChannel != 0 ) + break; + + pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); + + // Commented by Albert 2011/05/18 + // Match the device address located in the P2P IE + // This is for the case that the P2P device address is not the same as the P2P interface address. + + p2pie = rtw_bss_ex_get_p2p_ie(&pnetwork->network, NULL, &p2pielen); + if (p2pie) { + while ( p2pie ) + { + // The P2P Device ID attribute is included in the Beacon frame. + // The P2P Device Info attribute is included in the probe response frame. + + if ( rtw_get_p2p_attr_content( p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen) ) + { + // Handle the P2P Device ID attribute of Beacon first + if ( _rtw_memcmp( attr_content, peerMAC, ETH_ALEN ) ) + { + uintPeerChannel = pnetwork->network.Configuration.DSConfig; + break; + } + } + else if ( rtw_get_p2p_attr_content( p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen) ) + { + // Handle the P2P Device Info attribute of probe response + if ( _rtw_memcmp( attr_content, peerMAC, ETH_ALEN ) ) + { + uintPeerChannel = pnetwork->network.Configuration.DSConfig; + break; + } + } + + //Get the next P2P IE + p2pie = rtw_get_p2p_ie(p2pie + p2pielen, BSS_EX_TLV_IES_LEN(&pnetwork->network) - (p2pie + p2pielen - BSS_EX_TLV_IES(&pnetwork->network)), NULL, &p2pielen); + } + + } + +#ifdef CONFIG_INTEL_WIDI + // Some Intel WiDi source may not provide P2P IE, + // so we could only compare mac addr by 802.11 Source Address + if( pmlmepriv->widi_state == INTEL_WIDI_STATE_WFD_CONNECTION + && uintPeerChannel == 0 ) + { + if ( _rtw_memcmp( pnetwork->network.MacAddress, peerMAC, ETH_ALEN ) ) + { + uintPeerChannel = pnetwork->network.Configuration.DSConfig; + break; + } + } +#endif //CONFIG_INTEL_WIDI + + plist = get_next(plist); + + } + + _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); + + if ( uintPeerChannel ) + { + #ifdef CONFIG_WFD + if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) { + struct wifi_display_info *pwfd_info = pwdinfo->wfd_info; + u8 *wfd_ie; + uint wfd_ielen = 0; + + wfd_ie = rtw_bss_ex_get_wfd_ie(&pnetwork->network, NULL, &wfd_ielen); + if (wfd_ie) { + u8 *wfd_devinfo; + uint wfd_devlen; + + DBG_871X( "[%s] Found WFD IE!\n", __FUNCTION__ ); + wfd_devinfo = rtw_get_wfd_attr_content(wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, NULL, &wfd_devlen); + if (wfd_devinfo) { + u16 wfd_devinfo_field = 0; + + // Commented by Albert 20120319 + // The first two bytes are the WFD device information field of WFD device information subelement. + // In big endian format. + wfd_devinfo_field = RTW_GET_BE16(wfd_devinfo); + if ( wfd_devinfo_field & WFD_DEVINFO_SESSION_AVAIL ) + { + pwfd_info->peer_session_avail = _TRUE; + } + else + { + pwfd_info->peer_session_avail = _FALSE; + } + } + } + + if ( _FALSE == pwfd_info->peer_session_avail ) + { + DBG_871X( "[%s] WFD Session not avaiable!\n", __FUNCTION__ ); + goto exit; + } + } + #endif /* CONFIG_WFD */ + + DBG_871X( "[%s] peer channel: %d!\n", __FUNCTION__, uintPeerChannel ); +#ifdef CONFIG_CONCURRENT_MODE + if ( check_fwstate( pbuddy_mlmepriv, _FW_LINKED ) ) + { + _cancel_timer_ex( &pwdinfo->ap_p2p_switch_timer ); + } +#endif // CONFIG_CONCURRENT_MODE + _rtw_memcpy( pwdinfo->tx_prov_disc_info.peerIFAddr, pnetwork->network.MacAddress, ETH_ALEN ); + _rtw_memcpy( pwdinfo->tx_prov_disc_info.peerDevAddr, peerMAC, ETH_ALEN ); + pwdinfo->tx_prov_disc_info.peer_channel_num[0] = ( u16 ) uintPeerChannel; + pwdinfo->tx_prov_disc_info.benable = _TRUE; + rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); + rtw_p2p_set_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ); + + if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) + { + _rtw_memcpy( &pwdinfo->tx_prov_disc_info.ssid, &pnetwork->network.Ssid, sizeof( NDIS_802_11_SSID ) ); + } + else if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) + { + _rtw_memcpy( pwdinfo->tx_prov_disc_info.ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN ); + pwdinfo->tx_prov_disc_info.ssid.SsidLength= P2P_WILDCARD_SSID_LEN; + } + +#ifdef CONFIG_CONCURRENT_MODE + if ( check_fwstate( pbuddy_mlmepriv, _FW_LINKED ) ) + { + // Have to enter the power saving with the AP + set_channel_bwmode(padapter, pbuddy_mlmeext->cur_channel, pbuddy_mlmeext->cur_ch_offset, pbuddy_mlmeext->cur_bwmode); + + issue_nulldata(pbuddy_adapter, NULL, 1, 3, 500); + } + else + { + set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); + } +#else + set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, CHANNEL_WIDTH_20); +#endif + + _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); + +#ifdef CONFIG_CONCURRENT_MODE + if ( check_fwstate( pbuddy_mlmepriv, _FW_LINKED ) ) + { + _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_CONCURRENT_PROVISION_TIMEOUT ); + } + else + { + _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT ); + } +#else + _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT ); +#endif // CONFIG_CONCURRENT_MODE + + } + else + { + DBG_871X( "[%s] NOT Found in the Scanning Queue!\n", __FUNCTION__ ); +#ifdef CONFIG_INTEL_WIDI + _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer ); + rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH); + rtw_p2p_findphase_ex_set(pwdinfo, P2P_FINDPHASE_EX_NONE); + rtw_free_network_queue(padapter, _TRUE); + _enter_critical_bh(&pmlmepriv->lock, &irqL); + rtw_sitesurvey_cmd(padapter, NULL, 0, NULL, 0); + _exit_critical_bh(&pmlmepriv->lock, &irqL); +#endif //CONFIG_INTEL_WIDI + } +exit: + + return ret; + +} + +// Added by Albert 20110328 +// This function is used to inform the driver the user had specified the pin code value or pbc +// to application. + +static int rtw_p2p_got_wpsinfo(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); + + + DBG_871X( "[%s] data = %s\n", __FUNCTION__, extra ); + // Added by Albert 20110328 + // if the input data is P2P_NO_WPSINFO -> reset the wpsinfo + // if the input data is P2P_GOT_WPSINFO_PEER_DISPLAY_PIN -> the utility just input the PIN code got from the peer P2P device. + // if the input data is P2P_GOT_WPSINFO_SELF_DISPLAY_PIN -> the utility just got the PIN code from itself. + // if the input data is P2P_GOT_WPSINFO_PBC -> the utility just determine to use the PBC + + if ( *extra == '0' ) + { + pwdinfo->ui_got_wps_info = P2P_NO_WPSINFO; + } + else if ( *extra == '1' ) + { + pwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_PEER_DISPLAY_PIN; + } + else if ( *extra == '2' ) + { + pwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_SELF_DISPLAY_PIN; + } + else if ( *extra == '3' ) + { + pwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_PBC; + } + else + { + pwdinfo->ui_got_wps_info = P2P_NO_WPSINFO; + } + + return ret; + +} + +#endif //CONFIG_P2P + +static int rtw_p2p_set(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; +#ifdef CONFIG_P2P + + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + DBG_871X( "[%s] extra = %s\n", __FUNCTION__, extra ); + + if ( _rtw_memcmp( extra, "enable=", 7 ) ) + { + rtw_wext_p2p_enable( dev, info, wrqu, &extra[7] ); + } + else if ( _rtw_memcmp( extra, "setDN=", 6 ) ) + { + wrqu->data.length -= 6; + rtw_p2p_setDN( dev, info, wrqu, &extra[6] ); + } + else if ( _rtw_memcmp( extra, "profilefound=", 13 ) ) + { + wrqu->data.length -= 13; + rtw_p2p_profilefound( dev, info, wrqu, &extra[13] ); + } + else if ( _rtw_memcmp( extra, "prov_disc=", 10 ) ) + { + wrqu->data.length -= 10; + rtw_p2p_prov_disc( dev, info, wrqu, &extra[10] ); + } + else if ( _rtw_memcmp( extra, "nego=", 5 ) ) + { + wrqu->data.length -= 5; + rtw_p2p_connect( dev, info, wrqu, &extra[5] ); + } + else if ( _rtw_memcmp( extra, "intent=", 7 ) ) + { + // Commented by Albert 2011/03/23 + // The wrqu->data.length will include the null character + // So, we will decrease 7 + 1 + wrqu->data.length -= 8; + rtw_p2p_set_intent( dev, info, wrqu, &extra[7] ); + } + else if ( _rtw_memcmp( extra, "ssid=", 5 ) ) + { + wrqu->data.length -= 5; + rtw_p2p_set_go_nego_ssid( dev, info, wrqu, &extra[5] ); + } + else if ( _rtw_memcmp( extra, "got_wpsinfo=", 12 ) ) + { + wrqu->data.length -= 12; + rtw_p2p_got_wpsinfo( dev, info, wrqu, &extra[12] ); + } + else if ( _rtw_memcmp( extra, "listen_ch=", 10 ) ) + { + // Commented by Albert 2011/05/24 + // The wrqu->data.length will include the null character + // So, we will decrease (10 + 1) + wrqu->data.length -= 11; + rtw_p2p_set_listen_ch( dev, info, wrqu, &extra[10] ); + } + else if ( _rtw_memcmp( extra, "op_ch=", 6 ) ) + { + // Commented by Albert 2011/05/24 + // The wrqu->data.length will include the null character + // So, we will decrease (6 + 1) + wrqu->data.length -= 7; + rtw_p2p_set_op_ch( dev, info, wrqu, &extra[6] ); + } + else if ( _rtw_memcmp( extra, "invite=", 7 ) ) + { + wrqu->data.length -= 8; + rtw_p2p_invite_req( dev, info, wrqu, &extra[7] ); + } + else if ( _rtw_memcmp( extra, "persistent=", 11 ) ) + { + wrqu->data.length -= 11; + rtw_p2p_set_persistent( dev, info, wrqu, &extra[11] ); + } + else if ( _rtw_memcmp ( extra, "uuid=", 5) ) + { + wrqu->data.length -= 5; + ret = rtw_p2p_set_wps_uuid( dev, info, wrqu, &extra[5] ); + } + +#ifdef CONFIG_WFD + if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) { + if (_rtw_memcmp(extra, "sa=", 3)) { + /* sa: WFD Session Available information */ + wrqu->data.length -= 3; + rtw_p2p_set_sa(dev, info, wrqu, &extra[3]); + } else if (_rtw_memcmp(extra, "pc=", 3)) { + /* pc: WFD Preferred Connection */ + wrqu->data.length -= 3; + rtw_p2p_set_pc(dev, info, wrqu, &extra[3]); + } else if (_rtw_memcmp(extra, "wfd_type=", 9)) { + wrqu->data.length -= 9; + rtw_p2p_set_wfd_device_type(dev, info, wrqu, &extra[9]); + } else if (_rtw_memcmp(extra, "wfd_enable=", 11)) { + wrqu->data.length -= 11; + rtw_p2p_set_wfd_enable(dev, info, wrqu, &extra[11]); + } else if (_rtw_memcmp(extra, "driver_iface=", 13)) { + wrqu->data.length -= 13; + rtw_p2p_set_driver_iface(dev, info, wrqu, &extra[13]); + } + } +#endif /* CONFIG_WFD */ + +#endif //CONFIG_P2P + + return ret; + +} + +static int rtw_p2p_get(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + +#ifdef CONFIG_P2P + + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct iw_point *pdata = &wrqu->data; + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + if ( padapter->bShowGetP2PState ) + { + DBG_871X( "[%s] extra = %s\n", __FUNCTION__, (char*) wrqu->data.pointer ); + } + + if ( _rtw_memcmp( wrqu->data.pointer, "status", 6 ) ) + { + rtw_p2p_get_status( dev, info, wrqu, extra ); + } + else if ( _rtw_memcmp( wrqu->data.pointer, "role", 4 ) ) + { + rtw_p2p_get_role( dev, info, wrqu, extra); + } + else if ( _rtw_memcmp( wrqu->data.pointer, "peer_ifa", 8 ) ) + { + rtw_p2p_get_peer_ifaddr( dev, info, wrqu, extra); + } + else if ( _rtw_memcmp( wrqu->data.pointer, "req_cm", 6 ) ) + { + rtw_p2p_get_req_cm( dev, info, wrqu, extra); + } + else if ( _rtw_memcmp( wrqu->data.pointer, "peer_deva", 9 ) ) + { + // Get the P2P device address when receiving the provision discovery request frame. + rtw_p2p_get_peer_devaddr( dev, info, wrqu, extra); + } + else if ( _rtw_memcmp( wrqu->data.pointer, "group_id", 8 ) ) + { + rtw_p2p_get_groupid( dev, info, wrqu, extra); + } + else if ( _rtw_memcmp( wrqu->data.pointer, "inv_peer_deva", 13 ) ) + { + // Get the P2P device address when receiving the P2P Invitation request frame. + rtw_p2p_get_peer_devaddr_by_invitation( dev, info, wrqu, extra); + } + else if ( _rtw_memcmp( wrqu->data.pointer, "op_ch", 5 ) ) + { + rtw_p2p_get_op_ch( dev, info, wrqu, extra); + } + +#ifdef CONFIG_WFD + if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) { + if (_rtw_memcmp(wrqu->data.pointer, "peer_port", 9)) + rtw_p2p_get_peer_wfd_port(dev, info, wrqu, extra); + else if (_rtw_memcmp(wrqu->data.pointer, "wfd_sa", 6)) + rtw_p2p_get_peer_wfd_session_available(dev, info, wrqu, extra); + else if (_rtw_memcmp(wrqu->data.pointer, "wfd_pc", 6)) + rtw_p2p_get_peer_wfd_preferred_connection(dev, info, wrqu, extra); + } +#endif /* CONFIG_WFD */ + +#endif //CONFIG_P2P + + return ret; + +} + +static int rtw_p2p_get2(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + +#ifdef CONFIG_P2P + + int length = wrqu->data.length; + char *buffer = (u8 *)rtw_malloc(length); + + if (buffer == NULL) + { + ret = -ENOMEM; + goto bad; + } + + if (copy_from_user(buffer, wrqu->data.pointer, wrqu->data.length)) + { + ret = -EFAULT; + goto bad; + } + + DBG_871X("[%s] buffer = %s\n", __FUNCTION__, buffer); + + if (_rtw_memcmp(buffer, "wpsCM=", 6)) + { + ret = rtw_p2p_get_wps_configmethod(dev, info, wrqu, extra, &buffer[6]); + } else if (_rtw_memcmp(buffer, "devN=", 5)) + { + ret = rtw_p2p_get_device_name(dev, info, wrqu, extra, &buffer[5]); + } else if (_rtw_memcmp(buffer, "dev_type=", 9)) + { + ret = rtw_p2p_get_device_type(dev, info, wrqu, extra, &buffer[9]); + } else if (_rtw_memcmp(buffer, "go_devadd=", 10)) + { + ret = rtw_p2p_get_go_device_address(dev, info, wrqu, extra, &buffer[10]); + } else if (_rtw_memcmp(buffer, "InvProc=", 8)) + { + ret = rtw_p2p_get_invitation_procedure(dev, info, wrqu, extra, &buffer[8]); + } else + { + snprintf(extra, sizeof("Command not found."), "Command not found."); + wrqu->data.length = strlen(extra); + } + +bad: + if (buffer) + { + rtw_mfree(buffer, length); + } + +#endif //CONFIG_P2P + + return ret; + +} + +static int rtw_cta_test_start(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + DBG_871X("%s %s\n", __func__, extra); + if (!strcmp(extra, "1")) + padapter->in_cta_test = 1; + else + padapter->in_cta_test = 0; + + if(padapter->in_cta_test) + { + u32 v = rtw_read32(padapter, REG_RCR); + v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN );//| RCR_ADF + rtw_write32(padapter, REG_RCR, v); + DBG_871X("enable RCR_ADF\n"); + } + else + { + u32 v = rtw_read32(padapter, REG_RCR); + v |= RCR_CBSSID_DATA | RCR_CBSSID_BCN ;//| RCR_ADF + rtw_write32(padapter, REG_RCR, v); + DBG_871X("disable RCR_ADF\n"); + } + return ret; +} + + +extern int rtw_change_ifname(_adapter *padapter, const char *ifname); +static int rtw_rereg_nd_name(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + _adapter *padapter = rtw_netdev_priv(dev); + struct rereg_nd_name_data *rereg_priv = &padapter->rereg_nd_name_priv; + char new_ifname[IFNAMSIZ]; + + if(rereg_priv->old_ifname[0] == 0) { + char *reg_ifname; +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->isprimary) + reg_ifname = padapter->registrypriv.ifname; + else +#endif + reg_ifname = padapter->registrypriv.if2name; + + strncpy(rereg_priv->old_ifname, reg_ifname, IFNAMSIZ); + rereg_priv->old_ifname[IFNAMSIZ-1] = 0; + } + + //DBG_871X("%s wrqu->data.length:%d\n", __FUNCTION__, wrqu->data.length); + if(wrqu->data.length > IFNAMSIZ) + return -EFAULT; + + if ( copy_from_user(new_ifname, wrqu->data.pointer, IFNAMSIZ) ) { + return -EFAULT; + } + + if( 0 == strcmp(rereg_priv->old_ifname, new_ifname) ) { + return ret; + } + + DBG_871X("%s new_ifname:%s\n", __FUNCTION__, new_ifname); + if( 0 != (ret = rtw_change_ifname(padapter, new_ifname)) ) { + goto exit; + } + + if(_rtw_memcmp(rereg_priv->old_ifname, "disable%d", 9) == _TRUE) { + padapter->ledpriv.bRegUseLed= rereg_priv->old_bRegUseLed; + rtw_hal_sw_led_init(padapter); + //rtw_ips_mode_req(&padapter->pwrctrlpriv, rereg_priv->old_ips_mode); + } + + strncpy(rereg_priv->old_ifname, new_ifname, IFNAMSIZ); + rereg_priv->old_ifname[IFNAMSIZ-1] = 0; + + if(_rtw_memcmp(new_ifname, "disable%d", 9) == _TRUE) { + + DBG_871X("%s disable\n", __FUNCTION__); + // free network queue for Android's timming issue + rtw_free_network_queue(padapter, _TRUE); + + // close led + rtw_led_control(padapter, LED_CTL_POWER_OFF); + rereg_priv->old_bRegUseLed = padapter->ledpriv.bRegUseLed; + padapter->ledpriv.bRegUseLed= _FALSE; + rtw_hal_sw_led_deinit(padapter); + + // the interface is being "disabled", we can do deeper IPS + //rereg_priv->old_ips_mode = rtw_get_ips_mode_req(&padapter->pwrctrlpriv); + //rtw_ips_mode_req(&padapter->pwrctrlpriv, IPS_NORMAL); + } +exit: + return ret; + +} + +#ifdef CONFIG_IOL +#include +#endif + +#ifdef DBG_CMD_QUEUE +u8 dump_cmd_id=0; +#endif +static int rtw_dbg_port(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _irqL irqL; + int ret = 0; + u8 major_cmd, minor_cmd; + u16 arg; + u32 extra_arg, *pdata, val32; + struct sta_info *psta; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct security_priv *psecuritypriv = &padapter->securitypriv; + struct wlan_network *cur_network = &(pmlmepriv->cur_network); + struct sta_priv *pstapriv = &padapter->stapriv; + + + pdata = (u32*)&wrqu->data; + + val32 = *pdata; + arg = (u16)(val32&0x0000ffff); + major_cmd = (u8)(val32>>24); + minor_cmd = (u8)((val32>>16)&0x00ff); + + extra_arg = *(pdata+1); + + switch(major_cmd) + { + case 0x70://read_reg + switch(minor_cmd) + { + case 1: + DBG_871X("rtw_read8(0x%x)=0x%02x\n", arg, rtw_read8(padapter, arg)); + break; + case 2: + DBG_871X("rtw_read16(0x%x)=0x%04x\n", arg, rtw_read16(padapter, arg)); + break; + case 4: + DBG_871X("rtw_read32(0x%x)=0x%08x\n", arg, rtw_read32(padapter, arg)); + break; + } + break; + case 0x71://write_reg + switch(minor_cmd) + { + case 1: + rtw_write8(padapter, arg, extra_arg); + DBG_871X("rtw_write8(0x%x)=0x%02x\n", arg, rtw_read8(padapter, arg)); + break; + case 2: + rtw_write16(padapter, arg, extra_arg); + DBG_871X("rtw_write16(0x%x)=0x%04x\n", arg, rtw_read16(padapter, arg)); + break; + case 4: + rtw_write32(padapter, arg, extra_arg); + DBG_871X("rtw_write32(0x%x)=0x%08x\n", arg, rtw_read32(padapter, arg)); + break; + } + break; + case 0x72://read_bb + DBG_871X("read_bbreg(0x%x)=0x%x\n", arg, rtw_hal_read_bbreg(padapter, arg, 0xffffffff)); + break; + case 0x73://write_bb + rtw_hal_write_bbreg(padapter, arg, 0xffffffff, extra_arg); + DBG_871X("write_bbreg(0x%x)=0x%x\n", arg, rtw_hal_read_bbreg(padapter, arg, 0xffffffff)); + break; + case 0x74://read_rf + DBG_871X("read RF_reg path(0x%02x),offset(0x%x),value(0x%08x)\n",minor_cmd,arg,rtw_hal_read_rfreg(padapter, minor_cmd, arg, 0xffffffff)); + break; + case 0x75://write_rf + rtw_hal_write_rfreg(padapter, minor_cmd, arg, 0xffffffff, extra_arg); + DBG_871X("write RF_reg path(0x%02x),offset(0x%x),value(0x%08x)\n",minor_cmd,arg, rtw_hal_read_rfreg(padapter, minor_cmd, arg, 0xffffffff)); + break; + + case 0x76: + switch(minor_cmd) + { + case 0x00: //normal mode, + padapter->recvpriv.is_signal_dbg = 0; + break; + case 0x01: //dbg mode + padapter->recvpriv.is_signal_dbg = 1; + extra_arg = extra_arg>100?100:extra_arg; + padapter->recvpriv.signal_strength_dbg=extra_arg; + break; + } + break; + case 0x78: //IOL test + switch(minor_cmd) + { + #ifdef CONFIG_IOL + case 0x04: //LLT table initialization test + { + u8 page_boundary = 0xf9; + { + struct xmit_frame *xmit_frame; + + if((xmit_frame=rtw_IOL_accquire_xmit_frame(padapter)) == NULL) { + ret = -ENOMEM; + break; + } + + rtw_IOL_append_LLT_cmd(xmit_frame, page_boundary); + + + if(_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 500,0) ) + ret = -EPERM; + } + } + break; + case 0x05: //blink LED test + { + u16 reg = 0x4c; + u32 blink_num = 50; + u32 blink_delay_ms = 200; + int i; + + { + struct xmit_frame *xmit_frame; + + if((xmit_frame=rtw_IOL_accquire_xmit_frame(padapter)) == NULL) { + ret = -ENOMEM; + break; + } + + for(i=0;inetwork.MacAddress + , WLAN_REASON_EXPIRATION_CHK, _FALSE); + break; + case 0x7F: + switch(minor_cmd) + { + case 0x0: + DBG_871X("fwstate=0x%x\n", get_fwstate(pmlmepriv)); + break; + case 0x01: + DBG_871X("auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\n", + psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm, + psecuritypriv->ndisauthtype, psecuritypriv->ndisencryptstatus); + break; + case 0x02: + DBG_871X("pmlmeinfo->state=0x%x\n", pmlmeinfo->state); + DBG_871X("DrvBcnEarly=%d\n", pmlmeext->DrvBcnEarly); + DBG_871X("DrvBcnTimeOut=%d\n", pmlmeext->DrvBcnTimeOut); + break; + case 0x03: + DBG_871X("qos_option=%d\n", pmlmepriv->qospriv.qos_option); +#ifdef CONFIG_80211N_HT + DBG_871X("ht_option=%d\n", pmlmepriv->htpriv.ht_option); +#endif //CONFIG_80211N_HT + break; + case 0x04: + DBG_871X("cur_ch=%d\n", pmlmeext->cur_channel); + DBG_871X("cur_bw=%d\n", pmlmeext->cur_bwmode); + DBG_871X("cur_ch_off=%d\n", pmlmeext->cur_ch_offset); + + DBG_871X("oper_ch=%d\n", rtw_get_oper_ch(padapter)); + DBG_871X("oper_bw=%d\n", rtw_get_oper_bw(padapter)); + DBG_871X("oper_ch_offet=%d\n", rtw_get_oper_choffset(padapter)); + + break; + case 0x05: + psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); + if(psta) + { + DBG_871X("SSID=%s\n", cur_network->network.Ssid.Ssid); + DBG_871X("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr)); + DBG_871X("cur_channel=%d, cur_bwmode=%d, cur_ch_offset=%d\n", pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset); + DBG_871X("rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self); + DBG_871X("state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid); +#ifdef CONFIG_80211N_HT + DBG_871X("qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); + DBG_871X("bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n", psta->bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m); + DBG_871X("ampdu_enable = %d\n", psta->htpriv.ampdu_enable); + DBG_871X("agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); +#endif //CONFIG_80211N_HT + + sta_rx_reorder_ctl_dump(RTW_DBGDUMP, psta); + } + else + { + DBG_871X("can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress)); + } + break; + case 0x06: + { + } + break; + case 0x07: + DBG_871X("bSurpriseRemoved=%s, bDriverStopped=%s\n" + , rtw_is_surprise_removed(padapter)?"True":"False" + , rtw_is_drv_stopped(padapter)?"True":"False"); + break; + case 0x08: + { + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct recv_priv *precvpriv = &padapter->recvpriv; + + DBG_871X("free_xmitbuf_cnt=%d, free_xmitframe_cnt=%d" + ", free_xmit_extbuf_cnt=%d, free_xframe_ext_cnt=%d" + ", free_recvframe_cnt=%d\n", + pxmitpriv->free_xmitbuf_cnt, pxmitpriv->free_xmitframe_cnt, + pxmitpriv->free_xmit_extbuf_cnt, pxmitpriv->free_xframe_ext_cnt, + precvpriv->free_recvframe_cnt); + #ifdef CONFIG_USB_HCI + DBG_871X("rx_urb_pending_cn=%d\n", ATOMIC_READ(&(precvpriv->rx_pending_cnt))); + #endif + } + break; + case 0x09: + { + int i; + _list *plist, *phead; + +#ifdef CONFIG_AP_MODE + DBG_871X("sta_dz_bitmap=0x%x, tim_bitmap=0x%x\n", pstapriv->sta_dz_bitmap, pstapriv->tim_bitmap); +#endif + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + for(i=0; i< NUM_STA; i++) + { + phead = &(pstapriv->sta_hash[i]); + plist = get_next(phead); + + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) + { + psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); + + plist = get_next(plist); + + if(extra_arg == psta->aid) + { + DBG_871X("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr)); + DBG_871X("rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self); + DBG_871X("state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid); +#ifdef CONFIG_80211N_HT + DBG_871X("qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); + DBG_871X("bwmode=%d, ch_offset=%d, sgi_20m=%d,sgi_40m=%d\n", psta->bw_mode, psta->htpriv.ch_offset, psta->htpriv.sgi_20m, psta->htpriv.sgi_40m); + DBG_871X("ampdu_enable = %d\n", psta->htpriv.ampdu_enable); + DBG_871X("agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); +#endif //CONFIG_80211N_HT + +#ifdef CONFIG_AP_MODE + DBG_871X("capability=0x%x\n", psta->capability); + DBG_871X("flags=0x%x\n", psta->flags); + DBG_871X("wpa_psk=0x%x\n", psta->wpa_psk); + DBG_871X("wpa2_group_cipher=0x%x\n", psta->wpa2_group_cipher); + DBG_871X("wpa2_pairwise_cipher=0x%x\n", psta->wpa2_pairwise_cipher); + DBG_871X("qos_info=0x%x\n", psta->qos_info); +#endif + DBG_871X("dot118021XPrivacy=0x%x\n", psta->dot118021XPrivacy); + + sta_rx_reorder_ctl_dump(RTW_DBGDUMP, psta); + } + + } + } + + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + } + break; + + case 0x0b: //Enable=1, Disable=0 driver control vrtl_carrier_sense. + { + //u8 driver_vcs_en; //Enable=1, Disable=0 driver control vrtl_carrier_sense. + //u8 driver_vcs_type;//force 0:disable VCS, 1:RTS-CTS, 2:CTS-to-self when vcs_en=1. + + if(arg == 0){ + DBG_871X("disable driver ctrl vcs\n"); + padapter->driver_vcs_en = 0; + } + else if(arg == 1){ + DBG_871X("enable driver ctrl vcs = %d\n", extra_arg); + padapter->driver_vcs_en = 1; + + if(extra_arg>2) + padapter->driver_vcs_type = 1; + else + padapter->driver_vcs_type = extra_arg; + } + } + break; + case 0x0c://dump rx/tx packet + { + if(arg == 0){ + DBG_871X("dump rx packet (%d)\n",extra_arg); + //pHalData->bDumpRxPkt =extra_arg; + rtw_hal_set_def_var(padapter, HAL_DEF_DBG_DUMP_RXPKT, &(extra_arg)); + } + else if(arg==1){ + DBG_871X("dump tx packet (%d)\n",extra_arg); + rtw_hal_set_def_var(padapter, HAL_DEF_DBG_DUMP_TXPKT, &(extra_arg)); + } + } + break; + case 0x0e: + { + if(arg == 0){ + DBG_871X("disable driver ctrl rx_ampdu_factor\n"); + padapter->driver_rx_ampdu_factor = 0xFF; + } + else if(arg == 1){ + + DBG_871X("enable driver ctrl rx_ampdu_factor = %d\n", extra_arg); + + if(extra_arg > 0x03) + padapter->driver_rx_ampdu_factor = 0xFF; + else + padapter->driver_rx_ampdu_factor = extra_arg; + } + } + break; + #ifdef DBG_CONFIG_ERROR_DETECT + case 0x0f: + { + if(extra_arg == 0){ + DBG_871X("###### silent reset test.......#####\n"); + rtw_hal_sreset_reset(padapter); + } else { + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct sreset_priv *psrtpriv = &pHalData->srestpriv; + psrtpriv->dbg_trigger_point = extra_arg; + } + + } + break; + case 0x15: + { + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + DBG_871X("==>silent resete cnts:%d\n",pwrpriv->ips_enter_cnts); + } + break; + + #endif + + case 0x10:// driver version display + dump_drv_version(RTW_DBGDUMP); + break; + case 0x11://dump linked status + { + int pre_mode; + pre_mode=padapter->bLinkInfoDump; + // linked_info_dump(padapter,extra_arg); + if(extra_arg==1 || (extra_arg==0 && pre_mode==1) ) //not consider pwr_saving 0: + { + padapter->bLinkInfoDump = extra_arg; + + } + else if( (extra_arg==2 ) || (extra_arg==0 && pre_mode==2))//consider power_saving + { + //DBG_871X("linked_info_dump =%s \n", (padapter->bLinkInfoDump)?"enable":"disable") + linked_info_dump(padapter,extra_arg); + } + + + + } + break; +#ifdef CONFIG_80211N_HT + case 0x12: //set rx_stbc + { + struct registry_priv *pregpriv = &padapter->registrypriv; + // 0: disable, bit(0):enable 2.4g, bit(1):enable 5g, 0x3: enable both 2.4g and 5g + //default is set to enable 2.4GHZ for IOT issue with bufflao's AP at 5GHZ + if( pregpriv && (extra_arg == 0 || extra_arg == 1|| extra_arg == 2 || extra_arg == 3)) + { + pregpriv->rx_stbc= extra_arg; + DBG_871X("set rx_stbc=%d\n",pregpriv->rx_stbc); + } + else + DBG_871X("get rx_stbc=%d\n",pregpriv->rx_stbc); + + } + break; + case 0x13: //set ampdu_enable + { + struct registry_priv *pregpriv = &padapter->registrypriv; + /* 0: disable, 0x1:enable */ + if (pregpriv && extra_arg < 2) { + pregpriv->ampdu_enable= extra_arg; + DBG_871X("set ampdu_enable=%d\n",pregpriv->ampdu_enable); + } + else + DBG_871X("get ampdu_enable=%d\n",pregpriv->ampdu_enable); + + } + break; +#endif + case 0x14: //get wifi_spec + { + struct registry_priv *pregpriv = &padapter->registrypriv; + DBG_871X("get wifi_spec=%d\n",pregpriv->wifi_spec); + + } + break; + case 0x16: + { + if(arg == 0xff){ + rtw_odm_dbg_comp_msg(RTW_DBGDUMP,padapter); + } + else{ + u64 dbg_comp = (u64)extra_arg; + rtw_odm_dbg_comp_set(padapter, dbg_comp); + } + } + break; +#ifdef DBG_FIXED_CHAN + case 0x17: + { + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + printk("===> Fixed channel to %d \n",extra_arg); + pmlmeext->fixed_chan = extra_arg; + + } + break; +#endif + case 0x18: + { + printk("===> Switch USB Mode %d \n",extra_arg); + rtw_hal_set_hwreg(padapter, HW_VAR_USB_MODE, (u8 *)&extra_arg); + } + break; +#ifdef CONFIG_80211N_HT + case 0x19: + { + struct registry_priv *pregistrypriv = &padapter->registrypriv; + // extra_arg : + // BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, + // BIT4: Enable HT LDPC Rx, BIT5: Enable HT LDPC Tx + if(arg == 0){ + DBG_871X("driver disable LDPC\n"); + pregistrypriv->ldpc_cap = 0x00; + } + else if(arg == 1){ + DBG_871X("driver set LDPC cap = 0x%x\n", extra_arg); + pregistrypriv->ldpc_cap = (u8)(extra_arg&0x33); + } + } + break; + case 0x1a: + { + struct registry_priv *pregistrypriv = &padapter->registrypriv; + // extra_arg : + // BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, + // BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx + if(arg == 0){ + DBG_871X("driver disable STBC\n"); + pregistrypriv->stbc_cap = 0x00; + } + else if(arg == 1){ + DBG_871X("driver set STBC cap = 0x%x\n", extra_arg); + pregistrypriv->stbc_cap = (u8)(extra_arg&0x33); + } + } + break; +#endif //CONFIG_80211N_HT + case 0x1b: + { + struct registry_priv *pregistrypriv = &padapter->registrypriv; + + if(arg == 0){ + DBG_871X("disable driver ctrl max_rx_rate, reset to default_rate_set\n"); + init_mlme_default_rate_set(padapter); +#ifdef CONFIG_80211N_HT + pregistrypriv->ht_enable = (u8)rtw_ht_enable; +#endif //CONFIG_80211N_HT + } + else if(arg == 1){ + + int i; + u8 max_rx_rate; + + DBG_871X("enable driver ctrl max_rx_rate = 0x%x\n", extra_arg); + + max_rx_rate = (u8)extra_arg; + + if(max_rx_rate < 0xc) // max_rx_rate < MSC0 -> B or G -> disable HT + { +#ifdef CONFIG_80211N_HT + pregistrypriv->ht_enable = 0; +#endif //CONFIG_80211N_HT + for(i=0; idatarate[i] > max_rx_rate) + pmlmeext->datarate[i] = 0xff; + } + + } +#ifdef CONFIG_80211N_HT + else if(max_rx_rate < 0x1c) // mcs0~mcs15 + { + u32 mcs_bitmap=0x0; + + for(i=0; i<((max_rx_rate+1)-0xc); i++) + mcs_bitmap |= BIT(i); + + set_mcs_rate_by_mask(pmlmeext->default_supported_mcs_set, mcs_bitmap); + } +#endif //CONFIG_80211N_HT + } + } + break; + case 0x1c: //enable/disable driver control AMPDU Density for peer sta's rx + { + if(arg == 0){ + DBG_871X("disable driver ctrl ampdu density\n"); + padapter->driver_ampdu_spacing = 0xFF; + } + else if(arg == 1){ + + DBG_871X("enable driver ctrl ampdu density = %d\n", extra_arg); + + if(extra_arg > 0x07) + padapter->driver_ampdu_spacing = 0xFF; + else + padapter->driver_ampdu_spacing = extra_arg; + } + } + break; +#ifdef CONFIG_BACKGROUND_NOISE_MONITOR + case 0x1e: + { + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + PDM_ODM_T pDM_Odm = &pHalData->odmpriv; + u8 chan = rtw_get_oper_ch(padapter); + DBG_871X("===========================================\n"); + ODM_InbandNoise_Monitor(pDM_Odm,_TRUE,0x1e,100); + DBG_871X("channel(%d),noise_a = %d, noise_b = %d , noise_all:%d \n", + chan,pDM_Odm->noise_level.noise[ODM_RF_PATH_A], + pDM_Odm->noise_level.noise[ODM_RF_PATH_B], + pDM_Odm->noise_level.noise_all); + DBG_871X("===========================================\n"); + + } + break; +#endif + case 0x23: + { + DBG_871X("turn %s the bNotifyChannelChange Variable\n",(extra_arg==1)?"on":"off"); + padapter->bNotifyChannelChange = extra_arg; + break; + } + case 0x24: + { +#ifdef CONFIG_P2P + DBG_871X("turn %s the bShowGetP2PState Variable\n",(extra_arg==1)?"on":"off"); + padapter->bShowGetP2PState = extra_arg; +#endif // CONFIG_P2P + break; + } +#ifdef CONFIG_GPIO_API + case 0x25: //Get GPIO register + { + /* + * dbg 0x7f250000 [gpio_num], Get gpio value, gpio_num:0~7 + */ + + u8 value; + DBG_871X("Read GPIO Value extra_arg = %d\n",extra_arg); + value = rtw_hal_get_gpio(padapter,extra_arg); + DBG_871X("Read GPIO Value = %d\n",value); + break; + } + case 0x26: //Set GPIO direction + { + + /* dbg 0x7f26000x [y], Set gpio direction, + * x: gpio_num,4~7 y: indicate direction, 0~1 + */ + + int value; + DBG_871X("Set GPIO Direction! arg = %d ,extra_arg=%d\n",arg ,extra_arg); + value = rtw_hal_config_gpio(padapter, arg, extra_arg); + DBG_871X("Set GPIO Direction %s \n",(value==-1)?"Fail!!!":"Success"); + break; + } + case 0x27: //Set GPIO output direction value + { + /* + * dbg 0x7f27000x [y], Set gpio output direction value, + * x: gpio_num,4~7 y: indicate direction, 0~1 + */ + + int value; + DBG_871X("Set GPIO Value! arg = %d ,extra_arg=%d\n",arg ,extra_arg); + value = rtw_hal_set_gpio_output_value(padapter,arg,extra_arg); + DBG_871X("Set GPIO Value %s \n",(value==-1)?"Fail!!!":"Success"); + break; + } +#endif +#ifdef DBG_CMD_QUEUE + case 0x28: + { + dump_cmd_id = extra_arg; + DBG_871X("dump_cmd_id:%d\n",dump_cmd_id); + } + break; +#endif //DBG_CMD_QUEUE + case 0xaa: + { + if((extra_arg & 0x7F)> 0x3F) extra_arg = 0xFF; + DBG_871X("chang data rate to :0x%02x\n",extra_arg); + padapter->fix_rate = extra_arg; + } + break; + case 0xdd://registers dump , 0 for mac reg,1 for bb reg, 2 for rf reg + { + if(extra_arg==0){ + mac_reg_dump(RTW_DBGDUMP, padapter); + } + else if(extra_arg==1){ + bb_reg_dump(RTW_DBGDUMP, padapter); + } + else if(extra_arg==2){ + rf_reg_dump(RTW_DBGDUMP, padapter); + } + } + break; + + case 0xee: + { + DBG_871X(" === please control /proc to trun on/off PHYDM func === \n"); + } + break; + + case 0xfd: + rtw_write8(padapter, 0xc50, arg); + DBG_871X("wr(0xc50)=0x%x\n", rtw_read8(padapter, 0xc50)); + rtw_write8(padapter, 0xc58, arg); + DBG_871X("wr(0xc58)=0x%x\n", rtw_read8(padapter, 0xc58)); + break; + case 0xfe: + DBG_871X("rd(0xc50)=0x%x\n", rtw_read8(padapter, 0xc50)); + DBG_871X("rd(0xc58)=0x%x\n", rtw_read8(padapter, 0xc58)); + break; + case 0xff: + { + DBG_871X("dbg(0x210)=0x%x\n", rtw_read32(padapter, 0x210)); + DBG_871X("dbg(0x608)=0x%x\n", rtw_read32(padapter, 0x608)); + DBG_871X("dbg(0x280)=0x%x\n", rtw_read32(padapter, 0x280)); + DBG_871X("dbg(0x284)=0x%x\n", rtw_read32(padapter, 0x284)); + DBG_871X("dbg(0x288)=0x%x\n", rtw_read32(padapter, 0x288)); + + DBG_871X("dbg(0x664)=0x%x\n", rtw_read32(padapter, 0x664)); + + + DBG_871X("\n"); + + DBG_871X("dbg(0x430)=0x%x\n", rtw_read32(padapter, 0x430)); + DBG_871X("dbg(0x438)=0x%x\n", rtw_read32(padapter, 0x438)); + + DBG_871X("dbg(0x440)=0x%x\n", rtw_read32(padapter, 0x440)); + + DBG_871X("dbg(0x458)=0x%x\n", rtw_read32(padapter, 0x458)); + + DBG_871X("dbg(0x484)=0x%x\n", rtw_read32(padapter, 0x484)); + DBG_871X("dbg(0x488)=0x%x\n", rtw_read32(padapter, 0x488)); + + DBG_871X("dbg(0x444)=0x%x\n", rtw_read32(padapter, 0x444)); + DBG_871X("dbg(0x448)=0x%x\n", rtw_read32(padapter, 0x448)); + DBG_871X("dbg(0x44c)=0x%x\n", rtw_read32(padapter, 0x44c)); + DBG_871X("dbg(0x450)=0x%x\n", rtw_read32(padapter, 0x450)); + } + break; + } + break; + default: + DBG_871X("error dbg cmd!\n"); + break; + } + + + return ret; + +} + +static int wpa_set_param(struct net_device *dev, u8 name, u32 value) +{ + uint ret=0; + u32 flags; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + switch (name){ + case IEEE_PARAM_WPA_ENABLED: + + padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_8021X; //802.1x + + //ret = ieee80211_wpa_enable(ieee, value); + + switch((value)&0xff) + { + case 1 : //WPA + padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPAPSK; //WPA_PSK + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled; + break; + case 2: //WPA2 + padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPA2PSK; //WPA2_PSK + padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled; + break; + } + + RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_,("wpa_set_param:padapter->securitypriv.ndisauthtype=%d\n", padapter->securitypriv.ndisauthtype)); + + break; + + case IEEE_PARAM_TKIP_COUNTERMEASURES: + //ieee->tkip_countermeasures=value; + break; + + case IEEE_PARAM_DROP_UNENCRYPTED: + { + /* HACK: + * + * wpa_supplicant calls set_wpa_enabled when the driver + * is loaded and unloaded, regardless of if WPA is being + * used. No other calls are made which can be used to + * determine if encryption will be used or not prior to + * association being expected. If encryption is not being + * used, drop_unencrypted is set to false, else true -- we + * can use this to determine if the CAP_PRIVACY_ON bit should + * be set. + */ + +#if 0 + struct ieee80211_security sec = { + .flags = SEC_ENABLED, + .enabled = value, + }; + ieee->drop_unencrypted = value; + /* We only change SEC_LEVEL for open mode. Others + * are set by ipw_wpa_set_encryption. + */ + if (!value) { + sec.flags |= SEC_LEVEL; + sec.level = SEC_LEVEL_0; + } + else { + sec.flags |= SEC_LEVEL; + sec.level = SEC_LEVEL_1; + } + if (ieee->set_security) + ieee->set_security(ieee->dev, &sec); +#endif + break; + + } + case IEEE_PARAM_PRIVACY_INVOKED: + + //ieee->privacy_invoked=value; + + break; + + case IEEE_PARAM_AUTH_ALGS: + + ret = wpa_set_auth_algs(dev, value); + + break; + + case IEEE_PARAM_IEEE_802_1X: + + //ieee->ieee802_1x=value; + + break; + + case IEEE_PARAM_WPAX_SELECT: + + // added for WPA2 mixed mode + //DBG_871X(KERN_WARNING "------------------------>wpax value = %x\n", value); + /* + spin_lock_irqsave(&ieee->wpax_suitlist_lock,flags); + ieee->wpax_type_set = 1; + ieee->wpax_type_notify = value; + spin_unlock_irqrestore(&ieee->wpax_suitlist_lock,flags); + */ + + break; + + default: + + + + ret = -EOPNOTSUPP; + + + break; + + } + + return ret; + +} + +static int wpa_mlme(struct net_device *dev, u32 command, u32 reason) +{ + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + switch (command) + { + case IEEE_MLME_STA_DEAUTH: + + if(!rtw_set_802_11_disassociate(padapter)) + ret = -1; + + break; + + case IEEE_MLME_STA_DISASSOC: + + if(!rtw_set_802_11_disassociate(padapter)) + ret = -1; + + break; + + default: + ret = -EOPNOTSUPP; + break; + } + + return ret; + +} + +static int wpa_supplicant_ioctl(struct net_device *dev, struct iw_point *p) +{ + struct ieee_param *param; + uint ret=0; + + //down(&ieee->wx_sem); + + if (p->length < sizeof(struct ieee_param) || !p->pointer){ + ret = -EINVAL; + goto out; + } + + param = (struct ieee_param *)rtw_malloc(p->length); + if (param == NULL) + { + ret = -ENOMEM; + goto out; + } + + if (copy_from_user(param, p->pointer, p->length)) + { + rtw_mfree((u8*)param, p->length); + ret = -EFAULT; + goto out; + } + + switch (param->cmd) { + + case IEEE_CMD_SET_WPA_PARAM: + ret = wpa_set_param(dev, param->u.wpa_param.name, param->u.wpa_param.value); + break; + + case IEEE_CMD_SET_WPA_IE: + //ret = wpa_set_wpa_ie(dev, param, p->length); + ret = rtw_set_wpa_ie((_adapter *)rtw_netdev_priv(dev), (char*)param->u.wpa_ie.data, (u16)param->u.wpa_ie.len); + break; + + case IEEE_CMD_SET_ENCRYPTION: + ret = wpa_set_encryption(dev, param, p->length); + break; + + case IEEE_CMD_MLME: + ret = wpa_mlme(dev, param->u.mlme.command, param->u.mlme.reason_code); + break; + + default: + DBG_871X("Unknown WPA supplicant request: %d\n", param->cmd); + ret = -EOPNOTSUPP; + break; + + } + + if (ret == 0 && copy_to_user(p->pointer, param, p->length)) + ret = -EFAULT; + + rtw_mfree((u8 *)param, p->length); + +out: + + //up(&ieee->wx_sem); + + return ret; + +} + +#ifdef CONFIG_AP_MODE +static int rtw_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) +{ + int ret = 0; + u32 wep_key_idx, wep_key_len,wep_total_len; + NDIS_802_11_WEP *pwep = NULL; + struct sta_info *psta = NULL, *pbcmc_sta = NULL; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct security_priv* psecuritypriv=&(padapter->securitypriv); + struct sta_priv *pstapriv = &padapter->stapriv; + + DBG_871X("%s\n", __FUNCTION__); + + param->u.crypt.err = 0; + param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0'; + + //sizeof(struct ieee_param) = 64 bytes; + //if (param_len != (u32) ((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) + if (param_len != sizeof(struct ieee_param) + param->u.crypt.key_len) + { + ret = -EINVAL; + goto exit; + } + + if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) + { + if (param->u.crypt.idx >= WEP_KEYS +#ifdef CONFIG_IEEE80211W + && param->u.crypt.idx > BIP_MAX_KEYID +#endif /* CONFIG_IEEE80211W */ + ) + { + ret = -EINVAL; + goto exit; + } + } + else + { + psta = rtw_get_stainfo(pstapriv, param->sta_addr); + if(!psta) + { + //ret = -EINVAL; + DBG_871X("rtw_set_encryption(), sta has already been removed or never been added\n"); + goto exit; + } + } + + if (strcmp(param->u.crypt.alg, "none") == 0 && (psta==NULL)) + { + //todo:clear default encryption keys + + psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; + psecuritypriv->ndisencryptstatus = Ndis802_11EncryptionDisabled; + psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_; + psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; + + DBG_871X("clear default encryption keys, keyid=%d\n", param->u.crypt.idx); + + goto exit; + } + + + if (strcmp(param->u.crypt.alg, "WEP") == 0 && (psta==NULL)) + { + DBG_871X("r871x_set_encryption, crypt.alg = WEP\n"); + + wep_key_idx = param->u.crypt.idx; + wep_key_len = param->u.crypt.key_len; + + DBG_871X("r871x_set_encryption, wep_key_idx=%d, len=%d\n", wep_key_idx, wep_key_len); + + if((wep_key_idx >= WEP_KEYS) || (wep_key_len<=0)) + { + ret = -EINVAL; + goto exit; + } + + + if (wep_key_len > 0) + { + wep_key_len = wep_key_len <= 5 ? 5 : 13; + wep_total_len = wep_key_len + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial); + pwep =(NDIS_802_11_WEP *)rtw_malloc(wep_total_len); + if(pwep == NULL){ + DBG_871X(" r871x_set_encryption: pwep allocate fail !!!\n"); + goto exit; + } + + _rtw_memset(pwep, 0, wep_total_len); + + pwep->KeyLength = wep_key_len; + pwep->Length = wep_total_len; + + } + + pwep->KeyIndex = wep_key_idx; + + _rtw_memcpy(pwep->KeyMaterial, param->u.crypt.key, pwep->KeyLength); + + if(param->u.crypt.set_tx) + { + DBG_871X("wep, set_tx=1\n"); + + psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Auto; + psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled; + psecuritypriv->dot11PrivacyAlgrthm=_WEP40_; + psecuritypriv->dot118021XGrpPrivacy=_WEP40_; + + if(pwep->KeyLength==13) + { + psecuritypriv->dot11PrivacyAlgrthm=_WEP104_; + psecuritypriv->dot118021XGrpPrivacy=_WEP104_; + } + + + psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx; + + _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength); + + psecuritypriv->dot11DefKeylen[wep_key_idx]=pwep->KeyLength; + + rtw_ap_set_wep_key(padapter, pwep->KeyMaterial, pwep->KeyLength, wep_key_idx, 1); + } + else + { + DBG_871X("wep, set_tx=0\n"); + + //don't update "psecuritypriv->dot11PrivacyAlgrthm" and + //"psecuritypriv->dot11PrivacyKeyIndex=keyid", but can rtw_set_key to cam + + _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength); + + psecuritypriv->dot11DefKeylen[wep_key_idx] = pwep->KeyLength; + + rtw_ap_set_wep_key(padapter, pwep->KeyMaterial, pwep->KeyLength, wep_key_idx, 0); + } + + goto exit; + + } + + + if(!psta && check_fwstate(pmlmepriv, WIFI_AP_STATE)) // //group key + { + if(param->u.crypt.set_tx ==1) + { + if(strcmp(param->u.crypt.alg, "WEP") == 0) + { + DBG_871X("%s, set group_key, WEP\n", __FUNCTION__); + + _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); + + psecuritypriv->dot118021XGrpPrivacy = _WEP40_; + if(param->u.crypt.key_len==13) + { + psecuritypriv->dot118021XGrpPrivacy = _WEP104_; + } + + } + else if(strcmp(param->u.crypt.alg, "TKIP") == 0) + { + DBG_871X("%s, set group_key, TKIP\n", __FUNCTION__); + + psecuritypriv->dot118021XGrpPrivacy = _TKIP_; + + _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); + + //DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); + //set mic key + _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); + _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); + + psecuritypriv->busetkipkey = _TRUE; + + } + else if(strcmp(param->u.crypt.alg, "CCMP") == 0) + { + DBG_871X("%s, set group_key, CCMP\n", __FUNCTION__); + + psecuritypriv->dot118021XGrpPrivacy = _AES_; + + _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); + } +#ifdef CONFIG_IEEE80211W + else if (strcmp(param->u.crypt.alg, "BIP") == 0) { + int no; + + DBG_871X("BIP key_len=%d , index=%d\n", param->u.crypt.key_len, param->u.crypt.idx); + /* save the IGTK key, length 16 bytes */ + _rtw_memcpy(padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len > 16 ? 16:param->u.crypt.key_len)); + /* DBG_871X("IGTK key below:\n"); + for(no=0;no<16;no++) + printk(" %02x ", padapter->securitypriv.dot11wBIPKey[param->u.crypt.idx].skey[no]); + DBG_871X("\n"); */ + padapter->securitypriv.dot11wBIPKeyid = param->u.crypt.idx; + padapter->securitypriv.binstallBIPkey = _TRUE; + DBG_871X(" ~~~~set sta key:IGKT\n"); + goto exit; + } +#endif /* CONFIG_IEEE80211W */ + else + { + DBG_871X("%s, set group_key, none\n", __FUNCTION__); + + psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; + } + + psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx; + + psecuritypriv->binstallGrpkey = _TRUE; + + psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;//!!! + + rtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); + + pbcmc_sta=rtw_get_bcmc_stainfo(padapter); + if(pbcmc_sta) + { + pbcmc_sta->ieee8021x_blocked = _FALSE; + pbcmc_sta->dot118021XPrivacy= psecuritypriv->dot118021XGrpPrivacy;//rx will use bmc_sta's dot118021XPrivacy + } + + } + + goto exit; + + } + + if(psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X && psta) // psk/802_1x + { + if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) + { + if(param->u.crypt.set_tx ==1) + { + _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); + + if(strcmp(param->u.crypt.alg, "WEP") == 0) + { + DBG_871X("%s, set pairwise key, WEP\n", __FUNCTION__); + + psta->dot118021XPrivacy = _WEP40_; + if(param->u.crypt.key_len==13) + { + psta->dot118021XPrivacy = _WEP104_; + } + } + else if(strcmp(param->u.crypt.alg, "TKIP") == 0) + { + DBG_871X("%s, set pairwise key, TKIP\n", __FUNCTION__); + + psta->dot118021XPrivacy = _TKIP_; + + //DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); + //set mic key + _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); + _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); + + psecuritypriv->busetkipkey = _TRUE; + + } + else if(strcmp(param->u.crypt.alg, "CCMP") == 0) + { + + DBG_871X("%s, set pairwise key, CCMP\n", __FUNCTION__); + + psta->dot118021XPrivacy = _AES_; + } + else + { + DBG_871X("%s, set pairwise key, none\n", __FUNCTION__); + + psta->dot118021XPrivacy = _NO_PRIVACY_; + } + + rtw_ap_set_pairwise_key(padapter, psta); + + psta->ieee8021x_blocked = _FALSE; + + psta->bpairwise_key_installed = _TRUE; + + } + else//group key??? + { + if(strcmp(param->u.crypt.alg, "WEP") == 0) + { + _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); + + psecuritypriv->dot118021XGrpPrivacy = _WEP40_; + if(param->u.crypt.key_len==13) + { + psecuritypriv->dot118021XGrpPrivacy = _WEP104_; + } + } + else if(strcmp(param->u.crypt.alg, "TKIP") == 0) + { + psecuritypriv->dot118021XGrpPrivacy = _TKIP_; + + _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); + + //DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); + //set mic key + _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); + _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); + + psecuritypriv->busetkipkey = _TRUE; + + } + else if(strcmp(param->u.crypt.alg, "CCMP") == 0) + { + psecuritypriv->dot118021XGrpPrivacy = _AES_; + + _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); + } + else + { + psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; + } + + psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx; + + psecuritypriv->binstallGrpkey = _TRUE; + + psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;//!!! + + rtw_ap_set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); + + pbcmc_sta=rtw_get_bcmc_stainfo(padapter); + if(pbcmc_sta) + { + pbcmc_sta->ieee8021x_blocked = _FALSE; + pbcmc_sta->dot118021XPrivacy= psecuritypriv->dot118021XGrpPrivacy;//rx will use bmc_sta's dot118021XPrivacy + } + + } + + } + + } + +exit: + + if(pwep) + { + rtw_mfree((u8 *)pwep, wep_total_len); + } + + return ret; + +} + +static int rtw_set_beacon(struct net_device *dev, struct ieee_param *param, int len) +{ + int ret=0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sta_priv *pstapriv = &padapter->stapriv; + unsigned char *pbuf = param->u.bcn_ie.buf; + + + DBG_871X("%s, len=%d\n", __FUNCTION__, len); + + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + return -EINVAL; + + _rtw_memcpy(&pstapriv->max_num_sta, param->u.bcn_ie.reserved, 2); + + if((pstapriv->max_num_sta>NUM_STA) || (pstapriv->max_num_sta<=0)) + pstapriv->max_num_sta = NUM_STA; + + + if(rtw_check_beacon_data(padapter, pbuf, (len-12-2)) == _SUCCESS)// 12 = param header, 2:no packed + ret = 0; + else + ret = -EINVAL; + + + return ret; + +} + +static int rtw_hostapd_sta_flush(struct net_device *dev) +{ + //_irqL irqL; + //_list *phead, *plist; + int ret=0; + //struct sta_info *psta = NULL; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + //struct sta_priv *pstapriv = &padapter->stapriv; + + DBG_871X("%s\n", __FUNCTION__); + + flush_all_cam_entry(padapter); //clear CAM + + ret = rtw_sta_flush(padapter, _TRUE); + + return ret; + +} + +static int rtw_add_sta(struct net_device *dev, struct ieee_param *param) +{ + _irqL irqL; + int ret=0; + struct sta_info *psta = NULL; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sta_priv *pstapriv = &padapter->stapriv; + + DBG_871X("rtw_add_sta(aid=%d)=" MAC_FMT "\n", param->u.add_sta.aid, MAC_ARG(param->sta_addr)); + + if(check_fwstate(pmlmepriv, (_FW_LINKED|WIFI_AP_STATE)) != _TRUE) + { + return -EINVAL; + } + + if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) + { + return -EINVAL; + } + +/* + psta = rtw_get_stainfo(pstapriv, param->sta_addr); + if(psta) + { + DBG_871X("rtw_add_sta(), free has been added psta=%p\n", psta); + //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + rtw_free_stainfo(padapter, psta); + //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); + + psta = NULL; + } +*/ + //psta = rtw_alloc_stainfo(pstapriv, param->sta_addr); + psta = rtw_get_stainfo(pstapriv, param->sta_addr); + if(psta) + { + int flags = param->u.add_sta.flags; + + //DBG_871X("rtw_add_sta(), init sta's variables, psta=%p\n", psta); + + psta->aid = param->u.add_sta.aid;//aid=1~2007 + + _rtw_memcpy(psta->bssrateset, param->u.add_sta.tx_supp_rates, 16); + + + //check wmm cap. + if(WLAN_STA_WME&flags) + psta->qos_option = 1; + else + psta->qos_option = 0; + + if(pmlmepriv->qospriv.qos_option == 0) + psta->qos_option = 0; + + +#ifdef CONFIG_80211N_HT + //chec 802.11n ht cap. + if(WLAN_STA_HT&flags) + { + psta->htpriv.ht_option = _TRUE; + psta->qos_option = 1; + _rtw_memcpy((void*)&psta->htpriv.ht_cap, (void*)¶m->u.add_sta.ht_cap, sizeof(struct rtw_ieee80211_ht_cap)); + } + else + { + psta->htpriv.ht_option = _FALSE; + } + + if(pmlmepriv->htpriv.ht_option == _FALSE) + psta->htpriv.ht_option = _FALSE; +#endif + + + update_sta_info_apmode(padapter, psta); + + + } + else + { + ret = -ENOMEM; + } + + return ret; + +} + +static int rtw_del_sta(struct net_device *dev, struct ieee_param *param) +{ + _irqL irqL; + int ret=0; + struct sta_info *psta = NULL; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sta_priv *pstapriv = &padapter->stapriv; + + DBG_871X("rtw_del_sta=" MAC_FMT "\n", MAC_ARG(param->sta_addr)); + + if(check_fwstate(pmlmepriv, (_FW_LINKED|WIFI_AP_STATE)) != _TRUE) + { + return -EINVAL; + } + + if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) + { + return -EINVAL; + } + + psta = rtw_get_stainfo(pstapriv, param->sta_addr); + if(psta) + { + u8 updated=_FALSE; + + //DBG_871X("free psta=%p, aid=%d\n", psta, psta->aid); + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + if(rtw_is_list_empty(&psta->asoc_list)==_FALSE) + { + rtw_list_delete(&psta->asoc_list); + pstapriv->asoc_list_cnt--; + updated = ap_free_sta(padapter, psta, _TRUE, WLAN_REASON_DEAUTH_LEAVING, _TRUE); + + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + associated_clients_update(padapter, updated, STA_INFO_UPDATE_ALL); + + psta = NULL; + + } + else + { + DBG_871X("rtw_del_sta(), sta has already been removed or never been added\n"); + + //ret = -1; + } + + + return ret; + +} + +static int rtw_ioctl_get_sta_data(struct net_device *dev, struct ieee_param *param, int len) +{ + int ret=0; + struct sta_info *psta = NULL; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sta_priv *pstapriv = &padapter->stapriv; + struct ieee_param_ex *param_ex = (struct ieee_param_ex *)param; + struct sta_data *psta_data = (struct sta_data *)param_ex->data; + + DBG_871X("rtw_ioctl_get_sta_info, sta_addr: " MAC_FMT "\n", MAC_ARG(param_ex->sta_addr)); + + if(check_fwstate(pmlmepriv, (_FW_LINKED|WIFI_AP_STATE)) != _TRUE) + { + return -EINVAL; + } + + if (param_ex->sta_addr[0] == 0xff && param_ex->sta_addr[1] == 0xff && + param_ex->sta_addr[2] == 0xff && param_ex->sta_addr[3] == 0xff && + param_ex->sta_addr[4] == 0xff && param_ex->sta_addr[5] == 0xff) + { + return -EINVAL; + } + + psta = rtw_get_stainfo(pstapriv, param_ex->sta_addr); + if(psta) + { +#if 0 + struct { + u16 aid; + u16 capability; + int flags; + u32 sta_set; + u8 tx_supp_rates[16]; + u32 tx_supp_rates_len; + struct rtw_ieee80211_ht_cap ht_cap; + u64 rx_pkts; + u64 rx_bytes; + u64 rx_drops; + u64 tx_pkts; + u64 tx_bytes; + u64 tx_drops; + } get_sta; +#endif + psta_data->aid = (u16)psta->aid; + psta_data->capability = psta->capability; + psta_data->flags = psta->flags; + +/* + nonerp_set : BIT(0) + no_short_slot_time_set : BIT(1) + no_short_preamble_set : BIT(2) + no_ht_gf_set : BIT(3) + no_ht_set : BIT(4) + ht_20mhz_set : BIT(5) +*/ + + psta_data->sta_set =((psta->nonerp_set) | + (psta->no_short_slot_time_set <<1) | + (psta->no_short_preamble_set <<2) | + (psta->no_ht_gf_set <<3) | + (psta->no_ht_set <<4) | + (psta->ht_20mhz_set <<5)); + + psta_data->tx_supp_rates_len = psta->bssratelen; + _rtw_memcpy(psta_data->tx_supp_rates, psta->bssrateset, psta->bssratelen); +#ifdef CONFIG_80211N_HT + _rtw_memcpy(&psta_data->ht_cap, &psta->htpriv.ht_cap, sizeof(struct rtw_ieee80211_ht_cap)); +#endif //CONFIG_80211N_HT + psta_data->rx_pkts = psta->sta_stats.rx_data_pkts; + psta_data->rx_bytes = psta->sta_stats.rx_bytes; + psta_data->rx_drops = psta->sta_stats.rx_drops; + + psta_data->tx_pkts = psta->sta_stats.tx_pkts; + psta_data->tx_bytes = psta->sta_stats.tx_bytes; + psta_data->tx_drops = psta->sta_stats.tx_drops; + + + } + else + { + ret = -1; + } + + return ret; + +} + +static int rtw_get_sta_wpaie(struct net_device *dev, struct ieee_param *param) +{ + int ret=0; + struct sta_info *psta = NULL; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct sta_priv *pstapriv = &padapter->stapriv; + + DBG_871X("rtw_get_sta_wpaie, sta_addr: " MAC_FMT "\n", MAC_ARG(param->sta_addr)); + + if(check_fwstate(pmlmepriv, (_FW_LINKED|WIFI_AP_STATE)) != _TRUE) + { + return -EINVAL; + } + + if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) + { + return -EINVAL; + } + + psta = rtw_get_stainfo(pstapriv, param->sta_addr); + if(psta) + { + if((psta->wpa_ie[0] == WLAN_EID_RSN) || (psta->wpa_ie[0] == WLAN_EID_GENERIC)) + { + int wpa_ie_len; + int copy_len; + + wpa_ie_len = psta->wpa_ie[1]; + + copy_len = ((wpa_ie_len+2) > sizeof(psta->wpa_ie)) ? (sizeof(psta->wpa_ie)):(wpa_ie_len+2); + + param->u.wpa_ie.len = copy_len; + + _rtw_memcpy(param->u.wpa_ie.reserved, psta->wpa_ie, copy_len); + } + else + { + //ret = -1; + DBG_871X("sta's wpa_ie is NONE\n"); + } + } + else + { + ret = -1; + } + + return ret; + +} + +static int rtw_set_wps_beacon(struct net_device *dev, struct ieee_param *param, int len) +{ + int ret=0; + unsigned char wps_oui[4]={0x0,0x50,0xf2,0x04}; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + int ie_len; + + DBG_871X("%s, len=%d\n", __FUNCTION__, len); + + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + return -EINVAL; + + ie_len = len-12-2;// 12 = param header, 2:no packed + + + if(pmlmepriv->wps_beacon_ie) + { + rtw_mfree(pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len); + pmlmepriv->wps_beacon_ie = NULL; + } + + if(ie_len>0) + { + pmlmepriv->wps_beacon_ie = rtw_malloc(ie_len); + pmlmepriv->wps_beacon_ie_len = ie_len; + if ( pmlmepriv->wps_beacon_ie == NULL) { + DBG_871X("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + return -EINVAL; + } + + _rtw_memcpy(pmlmepriv->wps_beacon_ie, param->u.bcn_ie.buf, ie_len); + + update_beacon(padapter, _VENDOR_SPECIFIC_IE_, wps_oui, _TRUE); + + pmlmeext->bstart_bss = _TRUE; + + } + + + return ret; + +} + +static int rtw_set_wps_probe_resp(struct net_device *dev, struct ieee_param *param, int len) +{ + int ret=0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + int ie_len; + + DBG_871X("%s, len=%d\n", __FUNCTION__, len); + + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + return -EINVAL; + + ie_len = len-12-2;// 12 = param header, 2:no packed + + + if(pmlmepriv->wps_probe_resp_ie) + { + rtw_mfree(pmlmepriv->wps_probe_resp_ie, pmlmepriv->wps_probe_resp_ie_len); + pmlmepriv->wps_probe_resp_ie = NULL; + } + + if(ie_len>0) + { + pmlmepriv->wps_probe_resp_ie = rtw_malloc(ie_len); + pmlmepriv->wps_probe_resp_ie_len = ie_len; + if ( pmlmepriv->wps_probe_resp_ie == NULL) { + DBG_871X("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + return -EINVAL; + } + _rtw_memcpy(pmlmepriv->wps_probe_resp_ie, param->u.bcn_ie.buf, ie_len); + } + + + return ret; + +} + +static int rtw_set_wps_assoc_resp(struct net_device *dev, struct ieee_param *param, int len) +{ + int ret=0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + int ie_len; + + DBG_871X("%s, len=%d\n", __FUNCTION__, len); + + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + return -EINVAL; + + ie_len = len-12-2;// 12 = param header, 2:no packed + + + if(pmlmepriv->wps_assoc_resp_ie) + { + rtw_mfree(pmlmepriv->wps_assoc_resp_ie, pmlmepriv->wps_assoc_resp_ie_len); + pmlmepriv->wps_assoc_resp_ie = NULL; + } + + if(ie_len>0) + { + pmlmepriv->wps_assoc_resp_ie = rtw_malloc(ie_len); + pmlmepriv->wps_assoc_resp_ie_len = ie_len; + if ( pmlmepriv->wps_assoc_resp_ie == NULL) { + DBG_871X("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + return -EINVAL; + } + + _rtw_memcpy(pmlmepriv->wps_assoc_resp_ie, param->u.bcn_ie.buf, ie_len); + } + + + return ret; + +} + +static int rtw_set_hidden_ssid(struct net_device *dev, struct ieee_param *param, int len) +{ + int ret=0; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *mlmepriv = &(adapter->mlmepriv); + struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv); + struct mlme_ext_info *mlmeinfo = &(mlmeext->mlmext_info); + int ie_len; + u8 *ssid_ie; + char ssid[NDIS_802_11_LENGTH_SSID + 1]; + sint ssid_len = 0; + u8 ignore_broadcast_ssid; + + if(check_fwstate(mlmepriv, WIFI_AP_STATE) != _TRUE) + return -EPERM; + + if (param->u.bcn_ie.reserved[0] != 0xea) + return -EINVAL; + + mlmeinfo->hidden_ssid_mode = ignore_broadcast_ssid = param->u.bcn_ie.reserved[1]; + + ie_len = len-12-2;// 12 = param header, 2:no packed + ssid_ie = rtw_get_ie(param->u.bcn_ie.buf, WLAN_EID_SSID, &ssid_len, ie_len); + + if (ssid_ie && ssid_len > 0 && ssid_len <= NDIS_802_11_LENGTH_SSID) { + WLAN_BSSID_EX *pbss_network = &mlmepriv->cur_network.network; + WLAN_BSSID_EX *pbss_network_ext = &mlmeinfo->network; + + _rtw_memcpy(ssid, ssid_ie+2, ssid_len); + ssid[ssid_len] = 0x0; + + if(0) + DBG_871X(FUNC_ADPT_FMT" ssid:(%s,%d), from ie:(%s,%d), (%s,%d)\n", FUNC_ADPT_ARG(adapter), + ssid, ssid_len, + pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength, + pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength); + + _rtw_memcpy(pbss_network->Ssid.Ssid, (void *)ssid, ssid_len); + pbss_network->Ssid.SsidLength = ssid_len; + _rtw_memcpy(pbss_network_ext->Ssid.Ssid, (void *)ssid, ssid_len); + pbss_network_ext->Ssid.SsidLength = ssid_len; + + if(0) + DBG_871X(FUNC_ADPT_FMT" after ssid:(%s,%d), (%s,%d)\n", FUNC_ADPT_ARG(adapter), + pbss_network->Ssid.Ssid, pbss_network->Ssid.SsidLength, + pbss_network_ext->Ssid.Ssid, pbss_network_ext->Ssid.SsidLength); + } + + DBG_871X(FUNC_ADPT_FMT" ignore_broadcast_ssid:%d, %s,%d\n", FUNC_ADPT_ARG(adapter), + ignore_broadcast_ssid, ssid, ssid_len); + + return ret; +} + +static int rtw_ioctl_acl_remove_sta(struct net_device *dev, struct ieee_param *param, int len) +{ + int ret=0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + return -EINVAL; + + if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) + { + return -EINVAL; + } + + ret = rtw_acl_remove_sta(padapter, param->sta_addr); + + return ret; + +} + +static int rtw_ioctl_acl_add_sta(struct net_device *dev, struct ieee_param *param, int len) +{ + int ret=0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + return -EINVAL; + + if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && + param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && + param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) + { + return -EINVAL; + } + + ret = rtw_acl_add_sta(padapter, param->sta_addr); + + return ret; + +} + +static int rtw_ioctl_set_macaddr_acl(struct net_device *dev, struct ieee_param *param, int len) +{ + int ret=0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) + return -EINVAL; + + rtw_set_macaddr_acl(padapter, param->u.mlme.command); + + return ret; +} + +static int rtw_hostapd_ioctl(struct net_device *dev, struct iw_point *p) +{ + struct ieee_param *param; + int ret=0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + //DBG_871X("%s\n", __FUNCTION__); + + /* + * this function is expect to call in master mode, which allows no power saving + * so, we just check hw_init_completed + */ + + if (!rtw_is_hw_init_completed(padapter)) { + ret = -EPERM; + goto out; + } + + + //if (p->length < sizeof(struct ieee_param) || !p->pointer){ + if(!p->pointer){ + ret = -EINVAL; + goto out; + } + + param = (struct ieee_param *)rtw_malloc(p->length); + if (param == NULL) + { + ret = -ENOMEM; + goto out; + } + + if (copy_from_user(param, p->pointer, p->length)) + { + rtw_mfree((u8*)param, p->length); + ret = -EFAULT; + goto out; + } + + //DBG_871X("%s, cmd=%d\n", __FUNCTION__, param->cmd); + + switch (param->cmd) + { + case RTL871X_HOSTAPD_FLUSH: + + ret = rtw_hostapd_sta_flush(dev); + + break; + + case RTL871X_HOSTAPD_ADD_STA: + + ret = rtw_add_sta(dev, param); + + break; + + case RTL871X_HOSTAPD_REMOVE_STA: + + ret = rtw_del_sta(dev, param); + + break; + + case RTL871X_HOSTAPD_SET_BEACON: + + ret = rtw_set_beacon(dev, param, p->length); + + break; + + case RTL871X_SET_ENCRYPTION: + + ret = rtw_set_encryption(dev, param, p->length); + + break; + + case RTL871X_HOSTAPD_GET_WPAIE_STA: + + ret = rtw_get_sta_wpaie(dev, param); + + break; + + case RTL871X_HOSTAPD_SET_WPS_BEACON: + + ret = rtw_set_wps_beacon(dev, param, p->length); + + break; + + case RTL871X_HOSTAPD_SET_WPS_PROBE_RESP: + + ret = rtw_set_wps_probe_resp(dev, param, p->length); + + break; + + case RTL871X_HOSTAPD_SET_WPS_ASSOC_RESP: + + ret = rtw_set_wps_assoc_resp(dev, param, p->length); + + break; + + case RTL871X_HOSTAPD_SET_HIDDEN_SSID: + + ret = rtw_set_hidden_ssid(dev, param, p->length); + + break; + + case RTL871X_HOSTAPD_GET_INFO_STA: + + ret = rtw_ioctl_get_sta_data(dev, param, p->length); + + break; + + case RTL871X_HOSTAPD_SET_MACADDR_ACL: + + ret = rtw_ioctl_set_macaddr_acl(dev, param, p->length); + + break; + + case RTL871X_HOSTAPD_ACL_ADD_STA: + + ret = rtw_ioctl_acl_add_sta(dev, param, p->length); + + break; + + case RTL871X_HOSTAPD_ACL_REMOVE_STA: + + ret = rtw_ioctl_acl_remove_sta(dev, param, p->length); + + break; + + default: + DBG_871X("Unknown hostapd request: %d\n", param->cmd); + ret = -EOPNOTSUPP; + break; + + } + + if (ret == 0 && copy_to_user(p->pointer, param, p->length)) + ret = -EFAULT; + + + rtw_mfree((u8 *)param, p->length); + +out: + + return ret; + +} +#endif + +static int rtw_wx_set_priv(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *awrq, + char *extra) +{ + +#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV + char *ext_dbg; +#endif + + int ret = 0; + int len = 0; + char *ext; + int i; + + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_point *dwrq = (struct iw_point*)awrq; + + //RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_notice_, ("+rtw_wx_set_priv\n")); + if(dwrq->length == 0) + return -EFAULT; + + len = dwrq->length; + if (!(ext = rtw_vmalloc(len))) + return -ENOMEM; + + if (copy_from_user(ext, dwrq->pointer, len)) { + rtw_vmfree(ext, len); + return -EFAULT; + } + + + //RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_notice_, + // ("rtw_wx_set_priv: %s req=%s\n", + // dev->name, ext)); + + #ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV + if (!(ext_dbg = rtw_vmalloc(len))) + { + rtw_vmfree(ext, len); + return -ENOMEM; + } + + _rtw_memcpy(ext_dbg, ext, len); + #endif + + //added for wps2.0 @20110524 + if(dwrq->flags == 0x8766 && len > 8) + { + u32 cp_sz; + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + u8 *probereq_wpsie = ext; + int probereq_wpsie_len = len; + u8 wps_oui[4]={0x0,0x50,0xf2,0x04}; + + if((_VENDOR_SPECIFIC_IE_ == probereq_wpsie[0]) && + (_rtw_memcmp(&probereq_wpsie[2], wps_oui, 4) ==_TRUE)) + { + cp_sz = probereq_wpsie_len>MAX_WPS_IE_LEN ? MAX_WPS_IE_LEN:probereq_wpsie_len; + + if(pmlmepriv->wps_probe_req_ie) + { + u32 free_len = pmlmepriv->wps_probe_req_ie_len; + pmlmepriv->wps_probe_req_ie_len = 0; + rtw_mfree(pmlmepriv->wps_probe_req_ie, free_len); + pmlmepriv->wps_probe_req_ie = NULL; + } + + pmlmepriv->wps_probe_req_ie = rtw_malloc(cp_sz); + if ( pmlmepriv->wps_probe_req_ie == NULL) { + printk("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); + ret = -EINVAL; + goto FREE_EXT; + + } + + _rtw_memcpy(pmlmepriv->wps_probe_req_ie, probereq_wpsie, cp_sz); + pmlmepriv->wps_probe_req_ie_len = cp_sz; + + } + + goto FREE_EXT; + + } + + if( len >= WEXT_CSCAN_HEADER_SIZE + && _rtw_memcmp(ext, WEXT_CSCAN_HEADER, WEXT_CSCAN_HEADER_SIZE) == _TRUE + ){ + ret = rtw_wx_set_scan(dev, info, awrq, ext); + goto FREE_EXT; + } + +FREE_EXT: + + rtw_vmfree(ext, len); + #ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV + rtw_vmfree(ext_dbg, len); + #endif + + //DBG_871X("rtw_wx_set_priv: (SIOCSIWPRIV) %s ret=%d\n", + // dev->name, ret); + + return ret; + +} + +static int rtw_pm_set(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + unsigned mode = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + DBG_871X( "[%s] extra = %s\n", __FUNCTION__, extra ); + + if ( _rtw_memcmp( extra, "lps=", 4 ) ) + { + sscanf(extra+4, "%u", &mode); + ret = rtw_pm_set_lps(padapter,mode); + } + else if ( _rtw_memcmp( extra, "ips=", 4 ) ) + { + sscanf(extra+4, "%u", &mode); + ret = rtw_pm_set_ips(padapter,mode); + } + else{ + ret = -EINVAL; + } + + return ret; +} + +static int rtw_mp_efuse_get(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wdata, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + PEFUSE_HAL pEfuseHal; + struct iw_point *wrqu; + + u8 *PROMContent = pHalData->efuse_eeprom_data; + u8 ips_mode = IPS_NUM; // init invalid value + u8 lps_mode = PS_MODE_NUM; // init invalid value + struct pwrctrl_priv *pwrctrlpriv ; + u8 *data = NULL; + u8 *rawdata = NULL; + char *pch, *ptmp, *token, *tmp[3]={0x00,0x00,0x00}; + u16 i=0, j=0, mapLen=0, addr=0, cnts=0; + u16 max_available_len = 0, raw_cursize = 0, raw_maxsize = 0; + int err; + #ifdef CONFIG_IOL + u8 org_fw_iol = padapter->registrypriv.fw_iol;// 0:Disable, 1:enable, 2:by usb speed + #endif + + wrqu = (struct iw_point*)wdata; + pwrctrlpriv = adapter_to_pwrctl(padapter); + pEfuseHal = &pHalData->EfuseHal; + + err = 0; + data = rtw_zmalloc(EFUSE_BT_MAX_MAP_LEN); + if (data == NULL) + { + err = -ENOMEM; + goto exit; + } + rawdata = rtw_zmalloc(EFUSE_BT_MAX_MAP_LEN); + if (rawdata == NULL) + { + err = -ENOMEM; + goto exit; + } + + if (copy_from_user(extra, wrqu->pointer, wrqu->length)) + { + err = -EFAULT; + goto exit; + } + #ifdef CONFIG_LPS + lps_mode = pwrctrlpriv->power_mgnt;//keep org value + rtw_pm_set_lps(padapter,PS_MODE_ACTIVE); + #endif + + #ifdef CONFIG_IPS + ips_mode = pwrctrlpriv->ips_mode;//keep org value + rtw_pm_set_ips(padapter,IPS_NONE); + #endif + + pch = extra; + DBG_871X("%s: in=%s\n", __FUNCTION__, extra); + + i = 0; + //mac 16 "00e04c871200" rmap,00,2 + while ((token = strsep(&pch, ",")) != NULL) + { + if (i > 2) break; + tmp[i] = token; + i++; + } + #ifdef CONFIG_IOL + padapter->registrypriv.fw_iol = 0;// 0:Disable, 1:enable, 2:by usb speed + #endif + + if(strcmp(tmp[0], "status") == 0){ + sprintf(extra, "Load File efuse=%s,Load File MAC=%s" + , pHalData->efuse_file_status == EFUSE_FILE_FAILED ? "FAIL" : "OK" + , pHalData->macaddr_file_status == MACADDR_FILE_FAILED ? "FAIL" : "OK" + ); + goto exit; + } + else if (strcmp(tmp[0], "drvmap") == 0) + { + mapLen = EFUSE_MAP_SIZE; + + sprintf(extra, "\n"); + for (i = 0; i < EFUSE_MAP_SIZE; i += 16) + { +// DBG_871X("0x%02x\t", i); + sprintf(extra, "%s0x%02x\t", extra, i); + for (j=0; j<8; j++) { +// DBG_871X("%02X ", data[i+j]); + sprintf(extra, "%s%02X ", extra, PROMContent[i+j]); + } +// DBG_871X("\t"); + sprintf(extra, "%s\t", extra); + for (; j<16; j++) { +// DBG_871X("%02X ", data[i+j]); + sprintf(extra, "%s%02X ", extra, PROMContent[i+j]); + } +// DBG_871X("\n"); + sprintf(extra,"%s\n",extra); + } +// DBG_871X("\n"); + } + else if (strcmp(tmp[0], "realmap") == 0) + { + mapLen = EFUSE_MAP_SIZE; + if (rtw_efuse_mask_map_read(padapter, EFUSE_WIFI , mapLen, pEfuseHal->fakeEfuseInitMap) == _FAIL) + { + DBG_871X("%s: read realmap Fail!!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + +// DBG_871X("OFFSET\tVALUE(hex)\n"); + sprintf(extra, "\n"); + for (i = 0; i < EFUSE_MAP_SIZE; i += 16) + { +// DBG_871X("0x%02x\t", i); + sprintf(extra, "%s0x%02x\t", extra, i); + for (j=0; j<8; j++) { +// DBG_871X("%02X ", data[i+j]); + sprintf(extra, "%s%02X ", extra, pEfuseHal->fakeEfuseInitMap[i+j]); + } +// DBG_871X("\t"); + sprintf(extra, "%s\t", extra); + for (; j<16; j++) { +// DBG_871X("%02X ", data[i+j]); + sprintf(extra, "%s%02X ", extra, pEfuseHal->fakeEfuseInitMap[i+j]); + } +// DBG_871X("\n"); + sprintf(extra,"%s\n",extra); + } +// DBG_871X("\n"); + } + else if (strcmp(tmp[0], "rmap") == 0) + { + if ((tmp[1]==NULL) || (tmp[2]==NULL)) + { + DBG_871X("%s: rmap Fail!! Parameters error!\n", __FUNCTION__); + err = -EINVAL; + goto exit; + } + + // rmap addr cnts + addr = simple_strtoul(tmp[1], &ptmp, 16); + DBG_871X("%s: addr=%x\n", __FUNCTION__, addr); + + cnts = simple_strtoul(tmp[2], &ptmp, 10); + if (cnts == 0) + { + DBG_871X("%s: rmap Fail!! cnts error!\n", __FUNCTION__); + err = -EINVAL; + goto exit; + } + DBG_871X("%s: cnts=%d\n", __FUNCTION__, cnts); + + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN , (PVOID)&max_available_len, _FALSE); + if ((addr + cnts) > max_available_len) + { + DBG_871X("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); + err = -EINVAL; + goto exit; + } + + if (rtw_efuse_mask_map_read(padapter, addr, cnts, data) == _FAIL) + { + DBG_871X("%s: rtw_efuse_mask_map_read error!\n", __func__); + err = -EFAULT; + goto exit; + } + +// DBG_871X("%s: data={", __FUNCTION__); + *extra = 0; + for (i=0; i= 512) + mapLen = 512; + + _rtw_memset(extra,'\0',strlen(extra)); + + sprintf(extra, "\n0x00\t"); + + for (i = 0; i < mapLen ; i++) { + sprintf(extra, "%s%02X", extra, rawdata[i]); + if ((i & 0xF) == 0xF) { + sprintf(extra, "%s\n", extra); + sprintf(extra, "%s0x%02x\t", extra, i+1); + } else if ((i & 0x7) == 0x7) { + sprintf(extra, "%s \t", extra); + } else { + sprintf(extra, "%s ", extra); + } + } + + } else if (strcmp(tmp[0], "realrawb") == 0) { + addr = 0; + mapLen = EFUSE_MAX_SIZE; + DBG_871X("EFUSE_MAX_SIZE =%d\n", EFUSE_MAX_SIZE); + if (rtw_efuse_access(padapter, _FALSE, addr, mapLen, rawdata) == _FAIL) + { + DBG_871X("%s: rtw_efuse_access Fail!!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + _rtw_memset(extra,'\0',strlen(extra)); + // DBG_871X("%s: realraw={\n", __FUNCTION__); + sprintf(extra, "\n0x00\t"); + for (i= 512; i< mapLen; i++) + { + // DBG_871X("%02X", rawdata[i]); + sprintf(extra, "%s%02X", extra, rawdata[i]); + if ((i & 0xF) == 0xF) { + // DBG_871X("\n"); + sprintf(extra, "%s\n", extra); + sprintf(extra, "%s0x%02x\t", extra, i+1); + } + else if ((i & 0x7) == 0x7){ + // DBG_871X("\t"); + sprintf(extra, "%s \t", extra); + } else { + // DBG_871X(" "); + sprintf(extra, "%s ", extra); + } + } + // DBG_871X("}\n"); + } + else if (strcmp(tmp[0], "mac") == 0) + { + if (hal_efuse_macaddr_offset(padapter) == -1) { + err = -EFAULT; + goto exit; + } + + addr = hal_efuse_macaddr_offset(padapter); + cnts = 6; + + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&max_available_len, _FALSE); + if ((addr + cnts) > max_available_len) { + DBG_871X("%s: addr(0x%02x)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); + err = -EFAULT; + goto exit; + } + + if (rtw_efuse_mask_map_read(padapter, addr, cnts, data) == _FAIL) + { + DBG_871X("%s: rtw_efuse_mask_map_read error!\n", __func__); + err = -EFAULT; + goto exit; + } + +// DBG_871X("%s: MAC address={", __FUNCTION__); + *extra = 0; + for (i=0; i max_available_len) { + DBG_871X("%s: addr(0x%02x)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); + err = -EFAULT; + goto exit; + } + if (rtw_efuse_mask_map_read(padapter, addr, cnts, data) == _FAIL) + { + DBG_871X("%s: rtw_efuse_access error!!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + +// DBG_871X("%s: {VID,PID}={", __FUNCTION__); + *extra = 0; + for (i=0; iBTEfuseInitMap) == _FAIL) + { + DBG_871X("%s: rtw_BT_efuse_map_read Fail!!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + +// DBG_871X("OFFSET\tVALUE(hex)\n"); + sprintf(extra, "\n"); + for (i=0; i<512; i+=16) // set 512 because the iwpriv's extra size have limit 0x7FF + { +// DBG_871X("0x%03x\t", i); + sprintf(extra, "%s0x%03x\t", extra, i); + for (j=0; j<8; j++) { +// DBG_871X("%02X ", pEfuseHal->BTEfuseInitMap[i+j]); + sprintf(extra, "%s%02X ", extra, pEfuseHal->BTEfuseInitMap[i+j]); + } +// DBG_871X("\t"); + sprintf(extra,"%s\t",extra); + for (; j<16; j++) { +// DBG_871X("%02X ", pEfuseHal->BTEfuseInitMap[i+j]); + sprintf(extra, "%s%02X ", extra, pEfuseHal->BTEfuseInitMap[i+j]); + } +// DBG_871X("\n"); + sprintf(extra, "%s\n", extra); + } +// DBG_871X("\n"); + } + else if (strcmp(tmp[0],"btbmap") == 0) + { + BTEfuse_PowerSwitch(padapter,1,_TRUE); + + mapLen = EFUSE_BT_MAX_MAP_LEN; + if (rtw_BT_efuse_map_read(padapter, 0, mapLen, pEfuseHal->BTEfuseInitMap) == _FAIL) + { + DBG_871X("%s: rtw_BT_efuse_map_read Fail!!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + +// DBG_871X("OFFSET\tVALUE(hex)\n"); + sprintf(extra, "\n"); + for (i=512; i<1024 ; i+=16) + { +// DBG_871X("0x%03x\t", i); + sprintf(extra, "%s0x%03x\t", extra, i); + for (j=0; j<8; j++) + { +// DBG_871X("%02X ", data[i+j]); + sprintf(extra, "%s%02X ", extra, pEfuseHal->BTEfuseInitMap[i+j]); + } +// DBG_871X("\t"); + sprintf(extra,"%s\t",extra); + for (; j<16; j++) { +// DBG_871X("%02X ", data[i+j]); + sprintf(extra, "%s%02X ", extra, pEfuseHal->BTEfuseInitMap[i+j]); + } +// DBG_871X("\n"); + sprintf(extra, "%s\n", extra); + } +// DBG_871X("\n"); + } + else if (strcmp(tmp[0],"btrmap") == 0) + { + if ((tmp[1]==NULL) || (tmp[2]==NULL)) + { + err = -EINVAL; + goto exit; + } + + BTEfuse_PowerSwitch(padapter,1,_TRUE); + + // rmap addr cnts + addr = simple_strtoul(tmp[1], &ptmp, 16); + DBG_871X("%s: addr=0x%X\n", __FUNCTION__, addr); + + cnts = simple_strtoul(tmp[2], &ptmp, 10); + if (cnts == 0) + { + DBG_871X("%s: btrmap Fail!! cnts error!\n", __FUNCTION__); + err = -EINVAL; + goto exit; + } + DBG_871X("%s: cnts=%d\n", __FUNCTION__, cnts); + + EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_EFUSE_MAP_LEN, (PVOID)&max_available_len, _FALSE); + if ((addr + cnts) > max_available_len) { + DBG_871X("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); + err = -EFAULT; + goto exit; + } + + if (rtw_BT_efuse_map_read(padapter, addr, cnts, data) == _FAIL) + { + DBG_871X("%s: rtw_BT_efuse_map_read error!!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + + *extra = 0; +// DBG_871X("%s: bt efuse data={", __FUNCTION__); + for (i=0; ifakeBTEfuseModifiedMap[i+j]); + sprintf(extra, "%s%02X ", extra, pEfuseHal->fakeBTEfuseModifiedMap[i+j]); + } +// DBG_871X("\t"); + sprintf(extra, "%s\t", extra); + for (; j<16; j++) { +// DBG_871X("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); + sprintf(extra, "%s%02X ", extra, pEfuseHal->fakeBTEfuseModifiedMap[i+j]); + } +// DBG_871X("\n"); + sprintf(extra, "%s\n", extra); + } +// DBG_871X("\n"); + } + else if (strcmp(tmp[0],"btbfake") == 0) + { +// DBG_871X("OFFSET\tVALUE(hex)\n"); + sprintf(extra, "\n"); + for (i=512; i<1024; i+=16) + { +// DBG_871X("0x%03x\t", i); + sprintf(extra, "%s0x%03x\t", extra, i); + for (j=0; j<8; j++) { +// DBG_871X("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); + sprintf(extra, "%s%02X ", extra, pEfuseHal->fakeBTEfuseModifiedMap[i+j]); + } +// DBG_871X("\t"); + sprintf(extra, "%s\t", extra); + for (; j<16; j++) { +// DBG_871X("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); + sprintf(extra, "%s%02X ", extra, pEfuseHal->fakeBTEfuseModifiedMap[i+j]); + } +// DBG_871X("\n"); + sprintf(extra, "%s\n", extra); + } +// DBG_871X("\n"); + } + else if (strcmp(tmp[0],"wlrfkmap")== 0) + { +// DBG_871X("OFFSET\tVALUE(hex)\n"); + sprintf(extra, "\n"); + for (i=0; ifakeEfuseModifiedMap[i+j]); + sprintf(extra, "%s%02X ", extra, pEfuseHal->fakeEfuseModifiedMap[i+j]); + } +// DBG_871X("\t"); + sprintf(extra, "%s\t", extra); + for (; j<16; j++) { +// DBG_871X("%02X ", pEfuseHal->fakeEfuseModifiedMap[i+j]); + sprintf(extra, "%s %02X", extra, pEfuseHal->fakeEfuseModifiedMap[i+j]); + } +// DBG_871X("\n"); + sprintf(extra, "%s\n", extra); + } +// DBG_871X("\n"); + + } + else if (strcmp(tmp[0],"wlrfkrmap")== 0) + { + if ((tmp[1]==NULL) || (tmp[2]==NULL)) + { + DBG_871X("%s: rmap Fail!! Parameters error!\n", __FUNCTION__); + err = -EINVAL; + goto exit; + } + // rmap addr cnts + addr = simple_strtoul(tmp[1], &ptmp, 16); + DBG_871X("%s: addr=%x\n", __FUNCTION__, addr); + + cnts = simple_strtoul(tmp[2], &ptmp, 10); + if (cnts == 0) + { + DBG_871X("%s: rmap Fail!! cnts error!\n", __FUNCTION__); + err = -EINVAL; + goto exit; + } + DBG_871X("%s: cnts=%d\n", __FUNCTION__, cnts); + + // DBG_871X("%s: data={", __FUNCTION__); + *extra = 0; + for (i=0; ifakeEfuseModifiedMap[addr+i]); + sprintf(extra, "%s0x%02X ", extra, pEfuseHal->fakeEfuseModifiedMap[addr+i]); + } + } + else if (strcmp(tmp[0],"btrfkrmap")== 0) + { + if ((tmp[1]==NULL) || (tmp[2]==NULL)) + { + DBG_871X("%s: rmap Fail!! Parameters error!\n", __FUNCTION__); + err = -EINVAL; + goto exit; + } + // rmap addr cnts + addr = simple_strtoul(tmp[1], &ptmp, 16); + DBG_871X("%s: addr=%x\n", __FUNCTION__, addr); + + cnts = simple_strtoul(tmp[2], &ptmp, 10); + if (cnts == 0) + { + DBG_871X("%s: rmap Fail!! cnts error!\n", __FUNCTION__); + err = -EINVAL; + goto exit; + } + DBG_871X("%s: cnts=%d\n", __FUNCTION__, cnts); + + // DBG_871X("%s: data={", __FUNCTION__); + *extra = 0; + for (i=0; ifakeBTEfuseModifiedMap[addr+i]); + sprintf(extra, "%s0x%02X ", extra, pEfuseHal->fakeBTEfuseModifiedMap[addr+i]); + } + } + else + { + sprintf(extra, "Command not found!"); + } + +exit: + if (data) + rtw_mfree(data, EFUSE_BT_MAX_MAP_LEN); + if (rawdata) + rtw_mfree(rawdata, EFUSE_BT_MAX_MAP_LEN); + if (!err) + wrqu->length = strlen(extra); + + if (padapter->registrypriv.mp_mode == 0) + { + #ifdef CONFIG_IPS + rtw_pm_set_ips(padapter, ips_mode); +#endif // CONFIG_IPS + + #ifdef CONFIG_LPS + rtw_pm_set_lps(padapter, lps_mode); +#endif // CONFIG_LPS + } + + #ifdef CONFIG_IOL + padapter->registrypriv.fw_iol = org_fw_iol;// 0:Disable, 1:enable, 2:by usb speed + #endif + return err; +} + +static int rtw_mp_efuse_set(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wdata, char *extra) +{ + struct iw_point *wrqu; + PADAPTER padapter; + struct pwrctrl_priv *pwrctrlpriv ; + PHAL_DATA_TYPE pHalData; + PEFUSE_HAL pEfuseHal; + struct hal_ops *pHalFunc; + + u8 ips_mode = IPS_NUM; // init invalid value + u8 lps_mode = PS_MODE_NUM; // init invalid value + u32 i=0,j=0, jj, kk; + u8 *setdata = NULL; + u8 *ShadowMapBT = NULL; + u8 *ShadowMapWiFi = NULL; + u8 *setrawdata = NULL; + char *pch, *ptmp, *token, *tmp[3]={0x00,0x00,0x00}; + u16 addr = 0xFF, cnts = 0, BTStatus = 0 , max_available_len = 0; + int err; + + wrqu = (struct iw_point*)wdata; + padapter = rtw_netdev_priv(dev); + pwrctrlpriv = adapter_to_pwrctl(padapter); + pHalData = GET_HAL_DATA(padapter); + pEfuseHal = &pHalData->EfuseHal; + pHalFunc = &padapter->HalFunc; + + err = 0; + + if (copy_from_user(extra, wrqu->pointer, wrqu->length)) + return -EFAULT; + + setdata = rtw_zmalloc(1024); + if (setdata == NULL) + { + err = -ENOMEM; + goto exit; + } + ShadowMapBT = rtw_malloc(EFUSE_BT_MAX_MAP_LEN); + if (ShadowMapBT == NULL) + { + err = -ENOMEM; + goto exit; + } + ShadowMapWiFi = rtw_malloc(EFUSE_MAP_SIZE); + if (ShadowMapWiFi == NULL) + { + err = -ENOMEM; + goto exit; + } + setrawdata = rtw_malloc(EFUSE_MAX_SIZE); + if (setrawdata == NULL) + { + err = -ENOMEM; + goto exit; + } + + #ifdef CONFIG_LPS + lps_mode = pwrctrlpriv->power_mgnt;//keep org value + rtw_pm_set_lps(padapter,PS_MODE_ACTIVE); + #endif + + #ifdef CONFIG_IPS + ips_mode = pwrctrlpriv->ips_mode;//keep org value + rtw_pm_set_ips(padapter,IPS_NONE); + #endif + + pch = extra; + DBG_871X("%s: in=%s\n", __FUNCTION__, extra); + + i = 0; + while ((token = strsep(&pch, ",")) != NULL) + { + if (i > 2) break; + tmp[i] = token; + i++; + } + + // tmp[0],[1],[2] + // wmap,addr,00e04c871200 + if (strcmp(tmp[0], "wmap") == 0) + { + if ((tmp[1]==NULL) || (tmp[2]==NULL)) + { + err = -EINVAL; + goto exit; + } + +#if 1 + // unknown bug workaround, need to fix later + addr=0x1ff; + rtw_write8(padapter, EFUSE_CTRL+1, (addr & 0xff)); + rtw_msleep_os(10); + rtw_write8(padapter, EFUSE_CTRL+2, ((addr >> 8) & 0x03)); + rtw_msleep_os(10); + rtw_write8(padapter, EFUSE_CTRL+3, 0x72); + rtw_msleep_os(10); + rtw_read8(padapter, EFUSE_CTRL); +#endif + + addr = simple_strtoul(tmp[1], &ptmp, 16); + addr &= 0xFFF; + + cnts = strlen(tmp[2]); + if (cnts%2) + { + err = -EINVAL; + goto exit; + } + cnts /= 2; + if (cnts == 0) + { + err = -EINVAL; + goto exit; + } + + DBG_871X("%s: addr=0x%X\n", __FUNCTION__, addr); + DBG_871X("%s: cnts=%d\n", __FUNCTION__, cnts); + DBG_871X("%s: map data=%s\n", __FUNCTION__, tmp[2]); + + for (jj=0, kk=0; jj max_available_len) { + DBG_871X("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); + err = -EFAULT; + goto exit; + } + + if (rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) + { + DBG_871X("%s: rtw_efuse_map_write error!!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + *extra = 0; + DBG_871X("%s: after rtw_efuse_map_write to _rtw_memcmp\n", __func__); + if (rtw_efuse_mask_map_read(padapter, addr, cnts, ShadowMapWiFi) == _SUCCESS) + { + if (_rtw_memcmp((void*)ShadowMapWiFi ,(void*)setdata,cnts)) + { + DBG_871X("%s: WiFi write map afterf compare success\n", __FUNCTION__); + sprintf(extra, "WiFi write map compare OK\n"); + err = 0; + goto exit; + } + else + { + sprintf(extra, "WiFi write map compare FAIL\n"); + DBG_871X("%s: WiFi write map compare Fail\n", __FUNCTION__); + err = 0; + goto exit; + } + } + } + else if (strcmp(tmp[0], "wraw") == 0) + { + if ((tmp[1]==NULL) || (tmp[2]==NULL)) + { + err = -EINVAL; + goto exit; + } + + addr = simple_strtoul( tmp[1], &ptmp, 16 ); + addr &= 0xFFF; + + cnts = strlen(tmp[2]); + if (cnts%2) + { + err = -EINVAL; + goto exit; + } + cnts /= 2; + if (cnts == 0) + { + err = -EINVAL; + goto exit; + } + + DBG_871X("%s: addr=0x%X\n", __FUNCTION__, addr); + DBG_871X("%s: cnts=%d\n", __FUNCTION__, cnts); + DBG_871X("%s: raw data=%s\n", __FUNCTION__, tmp[2]); + + for (jj=0, kk=0; jj 6) + { + DBG_871X("%s: error data for mac addr=\"%s\"\n", __FUNCTION__, tmp[1]); + err = -EFAULT; + goto exit; + } + + DBG_871X("%s: addr=0x%X\n", __FUNCTION__, addr); + DBG_871X("%s: cnts=%d\n", __FUNCTION__, cnts); + DBG_871X("%s: MAC address=%s\n", __FUNCTION__, tmp[1]); + + for (jj=0, kk=0; jj max_available_len) { + DBG_871X("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); + err = -EFAULT; + goto exit; + } + + if (rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) + { + DBG_871X("%s: rtw_efuse_map_write error!!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + } + else if (strcmp(tmp[0], "vidpid") == 0) + { + if (tmp[1]==NULL) + { + err = -EINVAL; + goto exit; + } + + // pidvid,da0b7881 + #ifdef CONFIG_RTL8188E + #ifdef CONFIG_USB_HCI + addr = EEPROM_VID_88EU; + #endif + #ifdef CONFIG_PCI_HCI + addr = EEPROM_VID_88EE; + #endif + #endif // CONFIG_RTL8188E + + #ifdef CONFIG_RTL8192E + #ifdef CONFIG_USB_HCI + addr = EEPROM_VID_8192EU; + #endif + #ifdef CONFIG_PCI_HCI + addr = EEPROM_VID_8192EE; + #endif + #endif // CONFIG_RTL8188E + + #ifdef CONFIG_RTL8723B + addr = EEPROM_VID_8723BU; + #endif + + #ifdef CONFIG_RTL8188F + addr = EEPROM_VID_8188FU; + #endif + + #ifdef CONFIG_RTL8703B + #ifdef CONFIG_USB_HCI + addr = EEPROM_VID_8703BU; + #endif /* CONFIG_USB_HCI */ + #endif /* CONFIG_RTL8703B */ + + cnts = strlen(tmp[1]); + if (cnts%2) + { + err = -EINVAL; + goto exit; + } + cnts /= 2; + if (cnts == 0) + { + err = -EINVAL; + goto exit; + } + + DBG_871X("%s: addr=0x%X\n", __FUNCTION__, addr); + DBG_871X("%s: cnts=%d\n", __FUNCTION__, cnts); + DBG_871X("%s: VID/PID=%s\n", __FUNCTION__, tmp[1]); + + for (jj=0, kk=0; jj max_available_len) { + DBG_871X("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); + err = -EFAULT; + goto exit; + } + + if (rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) + { + DBG_871X("%s: rtw_efuse_map_write error!!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + } + else if (strcmp(tmp[0], "wldumpfake") == 0) + { + if (rtw_efuse_mask_map_read(padapter, 0, EFUSE_MAP_SIZE, pEfuseHal->fakeEfuseModifiedMap) == _SUCCESS) { + DBG_871X("%s: WiFi hw efuse dump to Fake map success\n", __func__); + } else { + DBG_871X("%s: WiFi hw efuse dump to Fake map Fail\n", __func__); + err = -EFAULT; + } + } + else if (strcmp(tmp[0], "btwmap") == 0) + { + rtw_write8(padapter, 0xa3, 0x05); //For 8723AB ,8821S ? + BTStatus=rtw_read8(padapter, 0xa0); + DBG_871X("%s: btwmap before read 0xa0 BT Status =0x%x \n", __FUNCTION__,BTStatus); + if (BTStatus != 0x04) + { + sprintf(extra, "BT Status not Active Write FAIL\n"); + goto exit; + } + + if ((tmp[1]==NULL) || (tmp[2]==NULL)) + { + err = -EINVAL; + goto exit; + } + BTEfuse_PowerSwitch(padapter,1,_TRUE); + + addr=0x1ff; + rtw_write8(padapter, EFUSE_CTRL+1, (addr & 0xff)); + rtw_msleep_os(10); + rtw_write8(padapter, EFUSE_CTRL+2, ((addr >> 8) & 0x03)); + rtw_msleep_os(10); + rtw_write8(padapter, EFUSE_CTRL+3, 0x72); + rtw_msleep_os(10); + rtw_read8(padapter, EFUSE_CTRL); + + addr = simple_strtoul(tmp[1], &ptmp, 16); + addr &= 0xFFF; + + cnts = strlen(tmp[2]); + if (cnts%2) + { + err = -EINVAL; + goto exit; + } + cnts /= 2; + if (cnts == 0) + { + err = -EINVAL; + goto exit; + } + + DBG_871X("%s: addr=0x%X\n", __FUNCTION__, addr); + DBG_871X("%s: cnts=%d\n", __FUNCTION__, cnts); + DBG_871X("%s: BT data=%s\n", __FUNCTION__, tmp[2]); + + for (jj=0, kk=0; jj max_available_len) { + DBG_871X("%s: addr(0x%X)+cnts(%d) parameter error!\n", __FUNCTION__, addr, cnts); + err = -EFAULT; + goto exit; + } + + if (rtw_BT_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) + { + DBG_871X("%s: rtw_BT_efuse_map_write error!!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + *extra = 0; + DBG_871X("%s: after rtw_BT_efuse_map_write to _rtw_memcmp \n", __FUNCTION__); + if ( (rtw_BT_efuse_map_read(padapter, addr, cnts, ShadowMapBT ) == _SUCCESS ) ) + { + if (_rtw_memcmp((void*)ShadowMapBT ,(void*)setdata,cnts)) + { + DBG_871X("%s: BT write map compare OK BTStatus=0x%x\n", __FUNCTION__,BTStatus); + sprintf(extra, "BT write map compare OK"); + err = 0; + goto exit; + } + else + { + sprintf(extra, "BT write map compare FAIL"); + DBG_871X("%s: BT write map compare FAIL BTStatus=0x%x\n", __FUNCTION__,BTStatus); + err = 0; + goto exit; + } + } + } + else if (strcmp(tmp[0], "btwfake") == 0) + { + if ((tmp[1]==NULL) || (tmp[2]==NULL)) + { + err = -EINVAL; + goto exit; + } + + addr = simple_strtoul(tmp[1], &ptmp, 16); + addr &= 0xFFF; + + cnts = strlen(tmp[2]); + if (cnts%2) + { + err = -EINVAL; + goto exit; + } + cnts /= 2; + if (cnts == 0) + { + err = -EINVAL; + goto exit; + } + + DBG_871X("%s: addr=0x%X\n", __FUNCTION__, addr); + DBG_871X("%s: cnts=%d\n", __FUNCTION__, cnts); + DBG_871X("%s: BT tmp data=%s\n", __FUNCTION__, tmp[2]); + + for (jj=0, kk=0; jjfakeBTEfuseModifiedMap[addr+jj] = key_2char2num(tmp[2][kk], tmp[2][kk+1]); + } + } + else if (strcmp(tmp[0], "btdumpfake") == 0) + { + if (rtw_BT_efuse_map_read(padapter, 0, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseModifiedMap) == _SUCCESS) { + DBG_871X("%s: BT read all map success\n", __FUNCTION__); + } else { + DBG_871X("%s: BT read all map Fail!\n", __FUNCTION__); + err = -EFAULT; + } + } + else if (strcmp(tmp[0], "btfk2map") == 0) + { + rtw_write8(padapter, 0xa3, 0x05); + BTStatus=rtw_read8(padapter, 0xa0); + DBG_871X("%s: btwmap before read 0xa0 BT Status =0x%x \n", __FUNCTION__,BTStatus); + if (BTStatus != 0x04) + { + sprintf(extra, "BT Status not Active Write FAIL\n"); + goto exit; + } + + BTEfuse_PowerSwitch(padapter,1,_TRUE); + + addr=0x1ff; + rtw_write8(padapter, EFUSE_CTRL+1, (addr & 0xff)); + rtw_msleep_os(10); + rtw_write8(padapter, EFUSE_CTRL+2, ((addr >> 8) & 0x03)); + rtw_msleep_os(10); + rtw_write8(padapter, EFUSE_CTRL+3, 0x72); + rtw_msleep_os(10); + rtw_read8(padapter, EFUSE_CTRL); + + _rtw_memcpy(pEfuseHal->BTEfuseModifiedMap, pEfuseHal->fakeBTEfuseModifiedMap, EFUSE_BT_MAX_MAP_LEN); + + if (rtw_BT_efuse_map_write(padapter, 0x00, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseModifiedMap) == _FAIL) + { + DBG_871X("%s: rtw_BT_efuse_map_write error!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + + DBG_871X("pEfuseHal->fakeBTEfuseModifiedMap OFFSET\tVALUE(hex)\n"); + for (i = 0; i < EFUSE_BT_MAX_MAP_LEN; i += 16) + { + printk("0x%02x\t", i); + for (j=0; j<8; j++) { + printk("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); + } + printk("\t"); + + for (; j<16; j++) { + printk("%02X ", pEfuseHal->fakeBTEfuseModifiedMap[i+j]); + } + printk("\n"); + } + printk("\n"); +#if 1 + err = -EFAULT; + DBG_871X("%s: rtw_BT_efuse_map_read _rtw_memcmp \n", __FUNCTION__); + if ( (rtw_BT_efuse_map_read(padapter, 0x00, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseInitMap) == _SUCCESS ) ) + { + if (_rtw_memcmp((void*)pEfuseHal->fakeBTEfuseModifiedMap,(void*)pEfuseHal->fakeBTEfuseInitMap,EFUSE_BT_MAX_MAP_LEN)) + { + sprintf(extra, "BT write map compare OK"); + DBG_871X("%s: BT write map afterf compare success BTStatus=0x%x \n", __FUNCTION__,BTStatus); + err = 0; + goto exit; + } + else + { + sprintf(extra, "BT write map compare FAIL"); + if (rtw_BT_efuse_map_write(padapter, 0x00, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseModifiedMap) == _FAIL) + { + DBG_871X("%s: rtw_BT_efuse_map_write compare error,retry = %d!\n", __FUNCTION__,i); + } + + if (rtw_BT_efuse_map_read(padapter, EFUSE_BT, EFUSE_BT_MAX_MAP_LEN, pEfuseHal->fakeBTEfuseInitMap) == _SUCCESS) + { + DBG_871X("pEfuseHal->fakeBTEfuseInitMap OFFSET\tVALUE(hex)\n"); + + for (i = 0; i < EFUSE_BT_MAX_MAP_LEN; i += 16) + { + printk("0x%02x\t", i); + for (j=0; j<8; j++) { + printk("%02X ", pEfuseHal->fakeBTEfuseInitMap[i+j]); + } + printk("\t"); + for (; j<16; j++) { + printk("%02X ", pEfuseHal->fakeBTEfuseInitMap[i+j]); + } + printk("\n"); + } + printk("\n"); + } + DBG_871X("%s: BT write map afterf compare not match to write efuse try write Map again , BTStatus=0x%x\n", __FUNCTION__,BTStatus); + goto exit; + } + } +#endif + + } + else if (strcmp(tmp[0], "wlfk2map") == 0) + { + if (rtw_efuse_map_write(padapter, 0x00, EFUSE_MAP_SIZE, pEfuseHal->fakeEfuseModifiedMap) == _FAIL) + { + DBG_871X("%s: rtw_efuse_map_write fakeEfuseModifiedMap error!\n", __FUNCTION__); + err = -EFAULT; + goto exit; + } + *extra = 0; + DBG_871X("%s: after rtw_BT_efuse_map_write to _rtw_memcmp\n", __func__); + if (rtw_efuse_mask_map_read(padapter, 0x00, EFUSE_MAP_SIZE, ShadowMapWiFi) == _SUCCESS) + { + if (_rtw_memcmp((void*)ShadowMapWiFi ,(void*)setdata,cnts)) + { + DBG_871X("%s: WiFi write map afterf compare OK\n", __FUNCTION__); + sprintf(extra, "WiFi write map compare OK\n"); + err = 0; + goto exit; + } + else + { + sprintf(extra, "WiFi write map compare FAIL\n"); + DBG_871X("%s: WiFi write map compare Fail\n", __FUNCTION__); + err = 0; + goto exit; + } + } + } + else if (strcmp(tmp[0], "wlwfake") == 0) + { + if ((tmp[1]==NULL) || (tmp[2]==NULL)) + { + err = -EINVAL; + goto exit; + } + + addr = simple_strtoul(tmp[1], &ptmp, 16); + addr &= 0xFFF; + + cnts = strlen(tmp[2]); + if (cnts%2) + { + err = -EINVAL; + goto exit; + } + cnts /= 2; + if (cnts == 0) + { + err = -EINVAL; + goto exit; + } + + DBG_871X("%s: addr=0x%X\n", __FUNCTION__, addr); + DBG_871X("%s: cnts=%d\n", __FUNCTION__, cnts); + DBG_871X("%s: map tmp data=%s\n", __FUNCTION__, tmp[2]); + + for (jj=0, kk=0; jjfakeEfuseModifiedMap[addr+jj] = key_2char2num(tmp[2][kk], tmp[2][kk+1]); + } + _rtw_memset(extra, '\0', strlen(extra)); + sprintf(extra, "wlwfake OK\n"); + } else if(strcmp(tmp[0], "update") == 0) { + DBG_871X("To Use new eFuse map\n"); + /*step read efuse/eeprom data and get mac_addr*/ + rtw_hal_read_chip_info(padapter); + /* set mac addr*/ + rtw_macaddr_cfg(adapter_mac_addr(padapter), get_hal_mac_addr(padapter)); +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 17, 0) + _rtw_memcpy(padapter->pnetdev->dev_addr, get_hal_mac_addr(padapter), ETH_ALEN); /* set mac addr to net_device */ +#else + dev_addr_set(padapter->pnetdev, get_hal_mac_addr(padapter)); /* set mac addr to net_device */ +#endif + +#ifdef CONFIG_P2P + rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter)); +#endif + rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, adapter_mac_addr(padapter)); /* set mac addr to mac register */ + /*pHalFunc->hal_deinit(padapter);*/ + if (pHalFunc->hal_init(padapter) == _FAIL) { + err = -EINVAL; + goto exit; + } + _rtw_memset(extra, '\0', strlen(extra)); + sprintf(extra, "eFuse Update OK\n"); + } + +exit: + if (setdata) + rtw_mfree(setdata, 1024); + if (ShadowMapBT) + rtw_mfree(ShadowMapBT, EFUSE_BT_MAX_MAP_LEN); + if (ShadowMapWiFi) + rtw_mfree(ShadowMapWiFi, EFUSE_MAP_SIZE); + if (setrawdata) + rtw_mfree(setrawdata, EFUSE_MAX_SIZE); + + wrqu->length = strlen(extra); + + if (padapter->registrypriv.mp_mode == 0) + { + #ifdef CONFIG_IPS + rtw_pm_set_ips(padapter, ips_mode); + #endif // CONFIG_IPS + + #ifdef CONFIG_LPS + rtw_pm_set_lps(padapter, lps_mode); + #endif // CONFIG_LPS + } + + return err; +} + + +#ifdef CONFIG_MP_INCLUDED + +#ifdef CONFIG_SDIO_INDIRECT_ACCESS +#define DBG_MP_SDIO_INDIRECT_ACCESS 1 +static int rtw_mp_sd_iread(struct net_device *dev + , struct iw_request_info *info + , struct iw_point *wrqu + , char *extra) +{ + char input[16]; + u8 width; + unsigned long addr; + u32 ret = 0; + PADAPTER padapter = rtw_netdev_priv(dev); + + if (wrqu->length > 16) { + DBG_871X(FUNC_ADPT_FMT" wrqu->length:%d\n", FUNC_ADPT_ARG(padapter), wrqu->length); + ret = -EINVAL; + goto exit; + } + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) { + DBG_871X(FUNC_ADPT_FMT" copy_from_user fail\n", FUNC_ADPT_ARG(padapter)); + ret = -EFAULT; + goto exit; + } + + _rtw_memset(extra, 0, wrqu->length); + + if (sscanf(input, "%hhu,%lx", &width, &addr) != 2) { + DBG_871X(FUNC_ADPT_FMT" sscanf fail\n", FUNC_ADPT_ARG(padapter)); + ret = -EINVAL; + goto exit; + } + + if (addr > 0x3FFF) { + DBG_871X(FUNC_ADPT_FMT" addr:0x%lx\n", FUNC_ADPT_ARG(padapter), addr); + ret = -EINVAL; + goto exit; + } + + if (DBG_MP_SDIO_INDIRECT_ACCESS) + DBG_871X(FUNC_ADPT_FMT" width:%u, addr:0x%lx\n", FUNC_ADPT_ARG(padapter), width, addr); + + switch (width) { + case 1: + sprintf(extra, "0x%02x", rtw_sd_iread8(padapter, addr)); + wrqu->length = strlen(extra); + break; + case 2: + sprintf(extra, "0x%04x", rtw_sd_iread16(padapter, addr)); + wrqu->length = strlen(extra); + break; + case 4: + sprintf(extra, "0x%08x", rtw_sd_iread32(padapter, addr)); + wrqu->length = strlen(extra); + break; + default: + wrqu->length = 0; + ret = -EINVAL; + break; + } + +exit: + return ret; +} + +static int rtw_mp_sd_iwrite(struct net_device *dev + , struct iw_request_info *info + , struct iw_point *wrqu + , char *extra) +{ + char width; + unsigned long addr, data; + int ret = 0; + PADAPTER padapter = rtw_netdev_priv(dev); + char input[32]; + + if (wrqu->length > 32) { + DBG_871X(FUNC_ADPT_FMT" wrqu->length:%d\n", FUNC_ADPT_ARG(padapter), wrqu->length); + ret = -EINVAL; + goto exit; + } + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) { + DBG_871X(FUNC_ADPT_FMT" copy_from_user fail\n", FUNC_ADPT_ARG(padapter)); + ret = -EFAULT; + goto exit; + } + + _rtw_memset(extra, 0, wrqu->length); + + if (sscanf(input, "%hhu,%lx,%lx", &width, &addr, &data) != 3) { + DBG_871X(FUNC_ADPT_FMT" sscanf fail\n", FUNC_ADPT_ARG(padapter)); + ret = -EINVAL; + goto exit; + } + + if (addr > 0x3FFF) { + DBG_871X(FUNC_ADPT_FMT" addr:0x%lx\n", FUNC_ADPT_ARG(padapter), addr); + ret = -EINVAL; + goto exit; + } + + if (DBG_MP_SDIO_INDIRECT_ACCESS) + DBG_871X(FUNC_ADPT_FMT" width:%u, addr:0x%lx, data:0x%lx\n", FUNC_ADPT_ARG(padapter), width, addr, data); + + switch (width) { + case 1: + if (data > 0xFF) { + ret = -EINVAL; + break; + } + rtw_sd_iwrite8(padapter, addr, data); + break; + case 2: + if (data > 0xFFFF) { + ret = -EINVAL; + break; + } + rtw_sd_iwrite16(padapter, addr, data); + break; + case 4: + rtw_sd_iwrite32(padapter, addr, data); + break; + default: + wrqu->length = 0; + ret = -EINVAL; + break; + } + +exit: + return ret; +} +#endif /* CONFIG_SDIO_INDIRECT_ACCESS */ + +#ifdef CONFIG_RTW_CUSTOMER_STR +static int rtw_mp_customer_str( + struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + _adapter *adapter = rtw_netdev_priv(dev); + u32 len; + u8 *pbuf = NULL, *pch; + char *ptmp; + u8 param[RTW_CUSTOMER_STR_LEN]; + u8 count = 0; + u8 tmp; + u8 i; + u32 pos; + u8 ret; + u8 read = 0; + + if (adapter->registrypriv.mp_mode != 1 + || !adapter->registrypriv.mp_customer_str) + return -EFAULT; + + len = wrqu->data.length; + + pbuf = (u8 *)rtw_zmalloc(len); + if (pbuf == NULL) { + RTW_WARN("%s: no memory!\n", __func__); + return -ENOMEM; + } + + if (copy_from_user(pbuf, wrqu->data.pointer, len)) { + rtw_mfree(pbuf, len); + RTW_WARN("%s: copy from user fail!\n", __func__); + return -EFAULT; + } + RTW_INFO("%s: string=\"%s\"\n", __func__, pbuf); + + ptmp = (char *)pbuf; + pch = strsep(&ptmp, ","); + if ((pch == NULL) || (strlen(pch) == 0)) { + rtw_mfree(pbuf, len); + RTW_INFO("%s: parameter error(no cmd)!\n", __func__); + return -EFAULT; + } + + _rtw_memset(param, 0xFF, RTW_CUSTOMER_STR_LEN); + + if (strcmp(pch, "read") == 0) { + read = 1; + ret = rtw_hal_customer_str_read(adapter, param); + + } else if (strcmp(pch, "write") == 0) { + do { + pch = strsep(&ptmp, ":"); + if ((pch == NULL) || (strlen(pch) == 0)) + break; + if (strlen(pch) != 2 + || IsHexDigit(*pch) == _FALSE + || IsHexDigit(*(pch + 1)) == _FALSE + || sscanf(pch, "%hhx", &tmp) != 1 + ) { + RTW_WARN("%s: invalid 8-bit hex!\n", __func__); + rtw_mfree(pbuf, len); + return -EFAULT; + } + + param[count++] = tmp; + + } while (count < RTW_CUSTOMER_STR_LEN); + + if (count == 0) { + rtw_mfree(pbuf, len); + RTW_WARN("%s: no input!\n", __func__); + return -EFAULT; + } + ret = rtw_hal_customer_str_write(adapter, param); + } else { + rtw_mfree(pbuf, len); + RTW_INFO("%s: parameter error(unknown cmd)!\n", __func__); + return -EFAULT; + } + + pos = sprintf(extra, "%s: ", read ? "read" : "write"); + if (read == 0 || ret == _SUCCESS) { + for (i = 0; i < RTW_CUSTOMER_STR_LEN; i++) + pos += sprintf(extra + pos, "%02x:", param[i]); + extra[pos] = 0; + pos--; + } + pos += sprintf(extra + pos, " %s", ret == _SUCCESS ? "OK" : "FAIL"); + + wrqu->data.length = strlen(extra) + 1; + +free_buf: + rtw_mfree(pbuf, len); + return 0; +} +#endif /* CONFIG_RTW_CUSTOMER_STR */ + +static int rtw_mp_set(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wdata, char *extra) +{ + struct iw_point *wrqu = (struct iw_point *)wdata; + u32 subcmd = wrqu->flags; + PADAPTER padapter = rtw_netdev_priv(dev); + + if (padapter == NULL) + { + return -ENETDOWN; + } + + if((padapter->bup == _FALSE )) + { + DBG_871X(" %s fail =>(padapter->bup == _FALSE )\n",__FUNCTION__); + return -ENETDOWN; + } + + if (RTW_CANNOT_RUN(padapter)) { + DBG_871X("%s fail =>(bSurpriseRemoved == _TRUE) || ( bDriverStopped == _TRUE)\n", __func__); + return -ENETDOWN; + } + + + //_rtw_memset(extra, 0x00, IW_PRIV_SIZE_MASK); + + if (extra == NULL) + { + wrqu->length = 0; + return -EIO; + } + + switch(subcmd) + { + case CTA_TEST: + DBG_871X("set CTA_TEST\n"); + rtw_cta_test_start (dev, info, wdata, extra); + break; + case MP_DISABLE_BT_COEXIST: + DBG_871X("set case MP_DISABLE_BT_COEXIST \n"); + rtw_mp_disable_bt_coexist(dev, info, wdata, extra); + break; + } + + + return 0; +} + + +static int rtw_mp_get(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wdata, char *extra) +{ + struct iw_point *wrqu = (struct iw_point *)wdata; + u32 subcmd = wrqu->flags; + PADAPTER padapter = rtw_netdev_priv(dev); + + //DBG_871X("in mp_get extra= %s \n",extra); + + if (padapter == NULL) + { + return -ENETDOWN; + } + if((padapter->bup == _FALSE )) + { + DBG_871X(" %s fail =>(padapter->bup == _FALSE )\n",__FUNCTION__); + return -ENETDOWN; + } + + if (RTW_CANNOT_RUN(padapter)) { + DBG_871X("%s fail =>(padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE)\n", __func__); + return -ENETDOWN; + } + + if (extra == NULL) { + wrqu->length = 0; + return -EIO; + } + + switch (subcmd) { + case MP_START: + DBG_871X("set case mp_start \n"); + rtw_mp_start (dev,info,wrqu,extra); + break; + + case MP_STOP: + DBG_871X("set case mp_stop \n"); + rtw_mp_stop (dev,info,wrqu,extra); + break; + + case MP_BANDWIDTH: + DBG_871X("set case mp_bandwidth \n"); + rtw_mp_bandwidth (dev,info,wrqu,extra); + break; + + case MP_RESET_STATS: + DBG_871X("set case MP_RESET_STATS \n"); + rtw_mp_reset_stats (dev,info,wrqu,extra); + break; + + case MP_SetRFPathSwh: + DBG_871X("set MP_SetRFPathSwitch \n"); + rtw_mp_SetRFPath (dev,info,wrqu,extra); + break; + + case WRITE_REG: + rtw_mp_write_reg(dev, info, wrqu, extra); + break; + + case WRITE_RF: + rtw_mp_write_rf(dev, info, wrqu, extra); + break; + + case MP_PHYPARA: + DBG_871X("mp_get MP_PHYPARA\n"); + rtw_mp_phypara(dev, info, wrqu, extra); + break; + + case MP_CHANNEL: + DBG_871X("set case mp_channel\n"); + rtw_mp_channel(dev , info, wrqu, extra); + break; + + case READ_REG: + DBG_871X("mp_get READ_REG\n"); + rtw_mp_read_reg(dev, info, wrqu, extra); + break; + case READ_RF: + DBG_871X("mp_get READ_RF\n"); + rtw_mp_read_rf(dev, info, wrqu, extra); + break; + + case MP_RATE: + DBG_871X("set case mp_rate\n"); + rtw_mp_rate(dev, info, wrqu, extra); + break; + + case MP_TXPOWER: + DBG_871X("set case MP_TXPOWER\n"); + rtw_mp_txpower(dev, info, wrqu, extra); + break; + + case MP_ANT_TX: + DBG_871X("set case MP_ANT_TX\n"); + rtw_mp_ant_tx(dev, info, wrqu, extra); + break; + + case MP_ANT_RX: + DBG_871X("set case MP_ANT_RX\n"); + rtw_mp_ant_rx(dev, info, wrqu, extra); + break; + + case MP_QUERY: + rtw_mp_trx_query(dev, info, wrqu, extra); + break; + + case MP_CTX: + DBG_871X("set case MP_CTX\n"); + rtw_mp_ctx(dev, info, wrqu, extra); + break; + + case MP_ARX: + DBG_871X("set case MP_ARX\n"); + rtw_mp_arx(dev, info, wrqu, extra); + break; + + case EFUSE_GET: + DBG_871X("efuse get EFUSE_GET\n"); + rtw_mp_efuse_get(dev, info, wdata, extra); + break; + + case MP_DUMP: + DBG_871X("set case MP_DUMP\n"); + rtw_mp_dump(dev, info, wrqu, extra); + break; + case MP_PSD: + DBG_871X("set case MP_PSD\n"); + rtw_mp_psd(dev, info, wrqu, extra); + break; + case MP_THER: + DBG_871X("set case MP_THER\n"); + rtw_mp_thermal(dev, info, wrqu, extra); + break; + case MP_PwrCtlDM: + DBG_871X("set MP_PwrCtlDM\n"); + rtw_mp_PwrCtlDM(dev, info, wrqu, extra); + break; + case MP_QueryDrvStats: + DBG_871X("mp_get MP_QueryDrvStats\n"); + rtw_mp_QueryDrv(dev, info, wdata, extra); + break; + case MP_PWRTRK: + DBG_871X("set case MP_PWRTRK\n"); + rtw_mp_pwrtrk(dev, info, wrqu, extra); + break; + case EFUSE_SET: + DBG_871X("set case efuse set\n"); + rtw_mp_efuse_set(dev, info, wdata, extra); + break; + case MP_GET_TXPOWER_INX: + DBG_871X("mp_get MP_GET_TXPOWER_INX\n"); + rtw_mp_txpower_index(dev, info, wrqu, extra); + break; + case MP_GETVER: + DBG_871X("mp_get MP_GETVER\n"); + rtw_mp_getver(dev, info, wdata, extra); + break; + case MP_MON: + DBG_871X("mp_get MP_MON\n"); + rtw_mp_mon(dev, info, wdata, extra); + break; + case EFUSE_MASK: + DBG_871X("mp_get EFUSE_MASK\n"); + rtw_efuse_mask_file(dev, info, wdata, extra); + break; + case EFUSE_FILE: + DBG_871X("mp_get EFUSE_FILE\n"); + rtw_efuse_file_map(dev, info, wdata, extra); + break; + case MP_TX: + DBG_871X("mp_get MP_TX\n"); + rtw_mp_tx(dev, info, wdata, extra); + break; + case MP_RX: + DBG_871X("mp_get MP_RX\n"); + rtw_mp_rx(dev, info, wdata, extra); + break; + case MP_HW_TX_MODE: + DBG_871X("mp_get MP_HW_TX_MODE\n"); + rtw_mp_hwtx(dev, info, wdata, extra); + break; +#ifdef CONFIG_RTW_CUSTOMER_STR + case MP_CUSTOMER_STR: + RTW_INFO("customer str\n"); + rtw_mp_customer_str(dev, info, wdata, extra); + break; +#endif +#if defined(CONFIG_RTL8723B) + case MP_SetBT: + DBG_871X("set MP_SetBT\n"); + rtw_mp_SetBT(dev, info, wdata, extra); + break; +#endif +#ifdef CONFIG_SDIO_INDIRECT_ACCESS + case MP_SD_IREAD: + rtw_mp_sd_iread(dev, info, wrqu, extra); + break; + case MP_SD_IWRITE: + rtw_mp_sd_iwrite(dev, info, wrqu, extra); + break; +#endif + } + + rtw_msleep_os(10); //delay 5ms for sending pkt before exit adb shell operation +return 0; +} + +#endif /*#if defined(CONFIG_MP_INCLUDED)*/ + +static int rtw_wx_tdls_wfd_enable(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + +#ifdef CONFIG_TDLS +#ifdef CONFIG_WFD + + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + DBG_871X( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); + + if ( extra[ 0 ] == '0' ) + rtw_tdls_wfd_enable(padapter, 0); + else + rtw_tdls_wfd_enable(padapter, 1); + +#endif /* CONFIG_WFD */ +#endif /* CONFIG_TDLS */ + + return ret; +} + +static int rtw_tdls_weaksec(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + +#ifdef CONFIG_TDLS + + u8 i, j; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + DBG_871X( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); + + if ( extra[ 0 ] == '0' ) + padapter->wdinfo.wfd_tdls_weaksec = 0; + else + padapter->wdinfo.wfd_tdls_weaksec = 1; + +#endif /* CONFIG_TDLS */ + + return ret; +} + + +static int rtw_tdls_enable(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + +#ifdef CONFIG_TDLS + + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + _irqL irqL; + _list *plist, *phead; + s32 index; + struct sta_info *psta = NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + u8 tdls_sta[NUM_STA][ETH_ALEN]; + u8 empty_hwaddr[ETH_ALEN] = { 0x00 }; + struct tdls_txmgmt txmgmt; + + DBG_871X( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); + + _rtw_memset(tdls_sta, 0x00, sizeof(tdls_sta)); + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); + + if (extra[ 0 ] == '0') { + ptdlsinfo->tdls_enable = 0; + + if(pstapriv->asoc_sta_count==1) + return ret; + + _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); + for (index=0; index< NUM_STA; index++) { + phead = &(pstapriv->sta_hash[index]); + plist = get_next(phead); + + while (rtw_end_of_queue_search(phead, plist) == _FALSE) { + psta = LIST_CONTAINOR(plist, struct sta_info ,hash_list); + + plist = get_next(plist); + + if (psta->tdls_sta_state != TDLS_STATE_NONE) { + _rtw_memcpy(tdls_sta[index], psta->hwaddr, ETH_ALEN); + } + } + } + _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); + + for (index=0; index< NUM_STA; index++) { + if (!_rtw_memcmp(tdls_sta[index], empty_hwaddr, ETH_ALEN)) { + DBG_871X("issue tear down to "MAC_FMT"\n", MAC_ARG(tdls_sta[index])); + txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_; + _rtw_memcpy(txmgmt.peer, tdls_sta[index], ETH_ALEN); + issue_tdls_teardown(padapter, &txmgmt, _TRUE); + } + } + rtw_tdls_cmd(padapter, NULL, TDLS_RS_RCR); + rtw_reset_tdls_info(padapter); + } else if (extra[0] == '1') { + ptdlsinfo->tdls_enable = 1; + } +#endif /* CONFIG_TDLS */ + + return ret; +} + +static int rtw_tdls_setup(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; +#ifdef CONFIG_TDLS + u8 i, j; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct tdls_txmgmt txmgmt; +#ifdef CONFIG_WFD + struct wifidirect_info *pwdinfo= &(padapter->wdinfo); +#endif /* CONFIG_WFD */ + + DBG_871X("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1); + + if (wrqu->data.length - 1 != 17) { + DBG_871X("[%s] length:%d != 17\n", __FUNCTION__, (wrqu->data.length -1)); + return ret; + } + + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); + for( i=0, j=0 ; i < ETH_ALEN; i++, j+=3 ){ + txmgmt.peer[i]=key_2char2num(*(extra+j), *(extra+j+1)); + } + +#ifdef CONFIG_WFD + if (_AES_ != padapter->securitypriv.dot11PrivacyAlgrthm) { + /* Weak Security situation with AP. */ + if (0 == pwdinfo->wfd_tdls_weaksec) { + /* Can't send the tdls setup request out!! */ + DBG_871X("[%s] Current link is not AES, " + "SKIP sending the tdls setup request!!\n", __FUNCTION__); + } else { + issue_tdls_setup_req(padapter, &txmgmt, _TRUE); + } + } else +#endif /* CONFIG_WFD */ + { + issue_tdls_setup_req(padapter, &txmgmt, _TRUE); + } +#endif /* CONFIG_TDLS */ + + return ret; +} + +static int rtw_tdls_teardown(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + +#ifdef CONFIG_TDLS + + u8 i,j; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct sta_info *ptdls_sta = NULL; + struct tdls_txmgmt txmgmt; + + DBG_871X( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); + + if (wrqu->data.length - 1 != 17 && wrqu->data.length - 1 != 19) { + DBG_871X("[%s] length:%d != 17 or 19\n", + __FUNCTION__, (wrqu->data.length -1)); + return ret; + } + + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); + for (i=0, j=0; i < ETH_ALEN; i++, j+=3) + txmgmt.peer[i]=key_2char2num(*(extra+j), *(extra+j+1)); + + ptdls_sta = rtw_get_stainfo( &(padapter->stapriv), txmgmt.peer); + + if (ptdls_sta != NULL) { + txmgmt.status_code = _RSON_TDLS_TEAR_UN_RSN_; + if (wrqu->data.length - 1 == 19) + issue_tdls_teardown(padapter, &txmgmt, _FALSE); + else + issue_tdls_teardown(padapter, &txmgmt, _TRUE); + } else { + DBG_871X( "TDLS peer not found\n"); + } +#endif /* CONFIG_TDLS */ + + return ret; +} + +static int rtw_tdls_discovery(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + +#ifdef CONFIG_TDLS + + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct tdls_txmgmt txmgmt; + int i = 0, j=0; + + DBG_871X( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); + + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); + for( i=0, j=0 ; i < ETH_ALEN; i++, j+=3 ){ + txmgmt.peer[i]=key_2char2num(*(extra+j), *(extra+j+1)); + } + + issue_tdls_dis_req(padapter, &txmgmt); + +#endif /* CONFIG_TDLS */ + + return ret; +} + +static int rtw_tdls_ch_switch(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + u8 tmp; + +#ifdef CONFIG_TDLS +#ifdef CONFIG_TDLS_CH_SW + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info; + u8 i, j; + struct sta_info *ptdls_sta = NULL; + u8 take_care_iqk; + + DBG_8192C( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); + + if (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) + { + DBG_871X("TDLS channel switch is not allowed\n"); + return ret; + } + + for( i=0, j=0 ; i < ETH_ALEN; i++, j+=3 ){ + pchsw_info->addr[i] = key_2char2num(*(extra+j), *(extra+j+1)); + } + + ptdls_sta = rtw_get_stainfo(&padapter->stapriv, pchsw_info->addr); + if( ptdls_sta == NULL ) + return ret; + + pchsw_info->ch_sw_state |= TDLS_CH_SW_INITIATOR_STATE; + + if (ptdls_sta != NULL) { + if (pchsw_info->off_ch_num == 0) + pchsw_info->off_ch_num = 11; + }else { + DBG_871X( "TDLS peer not found\n"); + } + + rtw_pm_set_lps(padapter, PS_MODE_ACTIVE); + + rtw_hal_get_hwreg(padapter, HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, &take_care_iqk); + if (take_care_iqk == _TRUE) { + u8 central_chnl; + u8 bw_mode; + + bw_mode = (pchsw_info->ch_offset) ? CHANNEL_WIDTH_40 : CHANNEL_WIDTH_20; + central_chnl = rtw_get_center_ch(pchsw_info->off_ch_num, bw_mode, pchsw_info->ch_offset); + if (rtw_hal_ch_sw_iqk_info_search(padapter, central_chnl, bw_mode) >= 0) + rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_START); + else + rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_PREPARE); + } + else + rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_START); + + //issue_tdls_ch_switch_req(padapter, ptdls_sta); + /* DBG_871X("issue tdls ch switch req\n"); */ + +#endif /* CONFIG_TDLS_CH_SW */ +#endif /* CONFIG_TDLS */ + + return ret; +} + +static int rtw_tdls_ch_switch_off(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + +#ifdef CONFIG_TDLS +#ifdef CONFIG_TDLS_CH_SW + + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct tdls_ch_switch *pchsw_info = &padapter->tdlsinfo.chsw_info; + u8 i, j, mac_addr[ETH_ALEN]; + struct sta_info *ptdls_sta = NULL; + struct tdls_txmgmt txmgmt; + + _rtw_memset(&txmgmt, 0x00, sizeof(struct tdls_txmgmt)); + + DBG_871X( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); + + if (rtw_tdls_is_chsw_allowed(padapter) == _FALSE) + { + DBG_871X("TDLS channel switch is not allowed\n"); + return ret; + } + + if (wrqu->data.length >= 17) { + for (i=0, j=0 ; i < ETH_ALEN; i++, j+=3) + mac_addr[i]=key_2char2num(*(extra+j), *(extra+j+1)); + ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr); + } + + if (ptdls_sta == NULL) + return ret; + + rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CH_SW_END_TO_BASE_CHNL); + + pchsw_info->ch_sw_state &= ~(TDLS_CH_SW_INITIATOR_STATE | + TDLS_CH_SWITCH_ON_STATE | + TDLS_PEER_AT_OFF_STATE); + _rtw_memset(pchsw_info->addr, 0x00, ETH_ALEN); + + ptdls_sta->ch_switch_time = 0; + ptdls_sta->ch_switch_timeout = 0; + _cancel_timer_ex(&ptdls_sta->ch_sw_timer); + _cancel_timer_ex(&ptdls_sta->delay_timer); + _cancel_timer_ex(&ptdls_sta->stay_on_base_chnl_timer); + _cancel_timer_ex(&ptdls_sta->ch_sw_monitor_timer); + + rtw_pm_set_lps(padapter, PS_MODE_MAX); +#endif /* CONFIG_TDLS_CH_SW */ +#endif /* CONFIG_TDLS */ + + return ret; +} + +static int rtw_tdls_dump_ch(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + +#ifdef CONFIG_TDLS +#ifdef CONFIG_TDLS_CH_SW + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + + DBG_8192C("[%s] dump_stack:%s\n", __FUNCTION__, extra); + + extra[ wrqu->data.length ] = 0x00; + ptdlsinfo->chsw_info.dump_stack = rtw_atoi( extra ); + + return ret; + +#endif +#endif /* CONFIG_TDLS */ + + return ret; +} + +static int rtw_tdls_off_ch_num(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + +#ifdef CONFIG_TDLS +#ifdef CONFIG_TDLS_CH_SW + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + + DBG_8192C("[%s] off_ch_num:%s\n", __FUNCTION__, extra); + + extra[ wrqu->data.length ] = 0x00; + ptdlsinfo->chsw_info.off_ch_num = rtw_atoi(extra); + + return ret; + +#endif +#endif /* CONFIG_TDLS */ + + return ret; +} + +static int rtw_tdls_ch_offset(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + +#ifdef CONFIG_TDLS +#ifdef CONFIG_TDLS_CH_SW + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + + DBG_8192C("[%s] ch_offset:%s\n", __FUNCTION__, extra); + + extra[ wrqu->data.length ] = 0x00; + switch (rtw_atoi(extra)) + { + case SCA: + ptdlsinfo->chsw_info.ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; + break; + + case SCB: + ptdlsinfo->chsw_info.ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; + break; + + default: + ptdlsinfo->chsw_info.ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + break; + } + + return ret; + +#endif +#endif /* CONFIG_TDLS */ + + return ret; +} + +static int rtw_tdls_pson(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + +#ifdef CONFIG_TDLS + + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u8 i, j, mac_addr[ETH_ALEN]; + struct sta_info *ptdls_sta = NULL; + + DBG_871X( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); + + for (i=0, j=0; i < ETH_ALEN; i++, j+=3) + mac_addr[i]=key_2char2num(*(extra+j), *(extra+j+1)); + + ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr); + + issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->hwaddr, 1, 3, 500); + +#endif /* CONFIG_TDLS */ + + return ret; +} + +static int rtw_tdls_psoff(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + +#ifdef CONFIG_TDLS + + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u8 i, j, mac_addr[ETH_ALEN]; + struct sta_info *ptdls_sta = NULL; + + DBG_8192C( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); + + for (i=0, j=0; i < ETH_ALEN; i++, j+=3) + mac_addr[i]=key_2char2num(*(extra+j), *(extra+j+1)); + + ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr); + + if(ptdls_sta) + issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta->hwaddr, 0, 3, 500); + +#endif /* CONFIG_TDLS */ + + return ret; +} + +static int rtw_tdls_setip(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + +#ifdef CONFIG_TDLS +#ifdef CONFIG_WFD + + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + struct wifi_display_info *pwfd_info = ptdlsinfo->wfd_info; + u8 i=0, j=0, k=0, tag=0; + + DBG_871X("[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length - 1); + + while (i < 4) { + for (j=0; j < 4; j++) { + if (*( extra + j + tag ) == '.' || *( extra + j + tag ) == '\0') { + if( j == 1 ) + pwfd_info->ip_address[i]=convert_ip_addr( '0', '0', *(extra+(j-1)+tag)); + if( j == 2 ) + pwfd_info->ip_address[i]=convert_ip_addr( '0', *(extra+(j-2)+tag), *(extra+(j-1)+tag)); + if( j == 3 ) + pwfd_info->ip_address[i]=convert_ip_addr( *(extra+(j-3)+tag), *(extra+(j-2)+tag), *(extra+(j-1)+tag)); + + tag += j + 1; + break; + } + } + i++; + } + + DBG_871X( "[%s] Set IP = %u.%u.%u.%u \n", __FUNCTION__, + ptdlsinfo->wfd_info->ip_address[0], + ptdlsinfo->wfd_info->ip_address[1], + ptdlsinfo->wfd_info->ip_address[2], + ptdlsinfo->wfd_info->ip_address[3]); + +#endif /* CONFIG_WFD */ +#endif /* CONFIG_TDLS */ + + return ret; +} + +static int rtw_tdls_getip(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + +#ifdef CONFIG_TDLS +#ifdef CONFIG_WFD + + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + struct wifi_display_info *pwfd_info = ptdlsinfo->wfd_info; + + DBG_871X( "[%s]\n", __FUNCTION__); + + sprintf( extra, "\n\n%u.%u.%u.%u\n", + pwfd_info->peer_ip_address[0], pwfd_info->peer_ip_address[1], + pwfd_info->peer_ip_address[2], pwfd_info->peer_ip_address[3]); + + DBG_871X( "[%s] IP=%u.%u.%u.%u\n", __FUNCTION__, + pwfd_info->peer_ip_address[0], pwfd_info->peer_ip_address[1], + pwfd_info->peer_ip_address[2], pwfd_info->peer_ip_address[3]); + + wrqu->data.length = strlen( extra ); + +#endif /* CONFIG_WFD */ +#endif /* CONFIG_TDLS */ + + return ret; +} + +static int rtw_tdls_getport(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + +#ifdef CONFIG_TDLS +#ifdef CONFIG_WFD + + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + struct wifi_display_info *pwfd_info = ptdlsinfo->wfd_info; + + DBG_871X( "[%s]\n", __FUNCTION__); + + sprintf( extra, "\n\n%d\n", pwfd_info->peer_rtsp_ctrlport ); + DBG_871X( "[%s] remote port = %d\n", + __FUNCTION__, pwfd_info->peer_rtsp_ctrlport ); + + wrqu->data.length = strlen( extra ); + +#endif /* CONFIG_WFD */ +#endif /* CONFIG_TDLS */ + + return ret; + +} + +/* WFDTDLS, for sigma test */ +static int rtw_tdls_dis_result(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + +#ifdef CONFIG_TDLS +#ifdef CONFIG_WFD + + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + + DBG_871X( "[%s]\n", __FUNCTION__); + + if (ptdlsinfo->dev_discovered == _TRUE) { + sprintf( extra, "\n\nDis=1\n" ); + ptdlsinfo->dev_discovered = _FALSE; + } + + wrqu->data.length = strlen( extra ); + +#endif /* CONFIG_WFD */ +#endif /* CONFIG_TDLS */ + + return ret; + +} + +/* WFDTDLS, for sigma test */ +static int rtw_wfd_tdls_status(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + + int ret = 0; + +#ifdef CONFIG_TDLS + + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; + + DBG_871X("[%s]\n", __FUNCTION__); + + sprintf( extra, "\nlink_established:%d \n" + "sta_cnt:%d \n" + "sta_maximum:%d \n" + "cur_channel:%d \n" + "tdls_enable:%d" +#ifdef CONFIG_TDLS_CH_SW + "ch_sw_state:%08x\n" + "chsw_on:%d\n" + "off_ch_num:%d\n" + "cur_time:%d\n" + "ch_offset:%d\n" + "delay_swtich_back:%d" +#endif + , + ptdlsinfo->link_established, ptdlsinfo->sta_cnt, + ptdlsinfo->sta_maximum, ptdlsinfo->cur_channel, + ptdlsinfo->tdls_enable +#ifdef CONFIG_TDLS_CH_SW +, + ptdlsinfo->chsw_info.ch_sw_state, + ATOMIC_READ(&padapter->tdlsinfo.chsw_info.chsw_on), + ptdlsinfo->chsw_info.off_ch_num, + ptdlsinfo->chsw_info.cur_time, + ptdlsinfo->chsw_info.ch_offset, + ptdlsinfo->chsw_info.delay_switch_back +#endif +); + + wrqu->data.length = strlen( extra ); + +#endif /* CONFIG_TDLS */ + + return ret; + + } + +static int rtw_tdls_getsta(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) + { + + int ret = 0; +#ifdef CONFIG_TDLS + u8 i, j; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + u8 addr[ETH_ALEN] = {0}; + char charmac[17]; + struct sta_info *ptdls_sta = NULL; + + DBG_871X("[%s] %s %d\n", __FUNCTION__, + (char *)wrqu->data.pointer, wrqu->data.length -1); + + if(copy_from_user(charmac, wrqu->data.pointer+9, 17)){ + ret = -EFAULT; + goto exit; + } + + DBG_871X("[%s] %d, charmac:%s\n", __FUNCTION__, __LINE__, charmac); + for (i=0, j=0 ; i < ETH_ALEN; i++, j+=3) + addr[i]=key_2char2num(*(charmac+j), *(charmac+j+1)); + + DBG_871X("[%s] %d, charmac:%s, addr:"MAC_FMT"\n", + __FUNCTION__, __LINE__, charmac, MAC_ARG(addr)); + ptdls_sta = rtw_get_stainfo(&padapter->stapriv, addr); + if(ptdls_sta) { + sprintf(extra, "\n\ntdls_sta_state=0x%08x\n", ptdls_sta->tdls_sta_state); + DBG_871X("\n\ntdls_sta_state=%d\n", ptdls_sta->tdls_sta_state); + } else { + sprintf(extra, "\n\nNot found this sta\n"); + DBG_871X("\n\nNot found this sta\n"); + } + wrqu->data.length = strlen( extra ); + +#endif /* CONFIG_TDLS */ +exit: + return ret; + +} + +static int rtw_tdls_get_best_ch(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ +#ifdef CONFIG_FIND_BEST_CHANNEL + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + u32 i, best_channel_24G = 1, best_channel_5G = 36, index_24G = 0, index_5G = 0; + + for (i=0; pmlmeext->channel_set[i].ChannelNum !=0; i++) { + if (pmlmeext->channel_set[i].ChannelNum == 1) + index_24G = i; + if (pmlmeext->channel_set[i].ChannelNum == 36) + index_5G = i; + } + + for (i=0; pmlmeext->channel_set[i].ChannelNum !=0; i++) { + /* 2.4G */ + if (pmlmeext->channel_set[i].ChannelNum == 6 || pmlmeext->channel_set[i].ChannelNum == 11) { + if (pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_24G].rx_count) { + index_24G = i; + best_channel_24G = pmlmeext->channel_set[i].ChannelNum; + } + } + + /* 5G */ + if (pmlmeext->channel_set[i].ChannelNum >= 36 + && pmlmeext->channel_set[i].ChannelNum < 140) { + /* Find primary channel */ + if (((pmlmeext->channel_set[i].ChannelNum - 36) % 8 == 0) + && (pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_5G].rx_count)) { + index_5G = i; + best_channel_5G = pmlmeext->channel_set[i].ChannelNum; + } + } + + if (pmlmeext->channel_set[i].ChannelNum >= 149 + && pmlmeext->channel_set[i].ChannelNum < 165) { + /* Find primary channel */ + if (((pmlmeext->channel_set[i].ChannelNum - 149) % 8 == 0) + && (pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_5G].rx_count)) { + index_5G = i; + best_channel_5G = pmlmeext->channel_set[i].ChannelNum; + } + } +#if 1 /* debug */ + DBG_871X("The rx cnt of channel %3d = %d\n", + pmlmeext->channel_set[i].ChannelNum, + pmlmeext->channel_set[i].rx_count); +#endif + } + + sprintf( extra, "\nbest_channel_24G = %d\n", best_channel_24G ); + DBG_871X("best_channel_24G = %d\n", best_channel_24G); + + if (index_5G != 0) { + sprintf(extra, "best_channel_5G = %d\n", best_channel_5G); + DBG_871X("best_channel_5G = %d\n", best_channel_5G); + } + + wrqu->data.length = strlen( extra ); + +#endif + + return 0; + +} + +static int rtw_tdls(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + +#ifdef CONFIG_TDLS + + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + DBG_871X( "[%s] extra = %s\n", __FUNCTION__, extra ); + + if (hal_chk_wl_func(padapter, WL_FUNC_TDLS) == _FALSE) { + DBG_871X("Discard tdls oper since hal doesn't support tdls\n"); + return 0; + } + + if (padapter->tdlsinfo.tdls_enable == 0) { + DBG_871X("tdls haven't enabled\n"); + return 0; + } + + /* WFD Sigma will use the tdls enable command to let the driver know we want to test the tdls now! */ + + if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) { + if (_rtw_memcmp(extra, "wfdenable=", 10)) { + wrqu->data.length -= 10; + rtw_wx_tdls_wfd_enable(dev, info, wrqu, &extra[10]); + return ret; + } + } + + if (_rtw_memcmp(extra, "weaksec=", 8)) { + wrqu->data.length -=8; + rtw_tdls_weaksec( dev, info, wrqu, &extra[8] ); + return ret; + } else if (_rtw_memcmp( extra, "tdlsenable=", 11)) { + wrqu->data.length -=11; + rtw_tdls_enable( dev, info, wrqu, &extra[11] ); + return ret; + } + + if (_rtw_memcmp(extra, "setup=", 6)) { + wrqu->data.length -=6; + rtw_tdls_setup( dev, info, wrqu, &extra[6] ); + } else if (_rtw_memcmp(extra, "tear=", 5)) { + wrqu->data.length -= 5; + rtw_tdls_teardown( dev, info, wrqu, &extra[5] ); + } else if (_rtw_memcmp(extra, "dis=", 4)) { + wrqu->data.length -= 4; + rtw_tdls_discovery( dev, info, wrqu, &extra[4] ); + } else if (_rtw_memcmp(extra, "swoff=", 6)) { + wrqu->data.length -= 6; + rtw_tdls_ch_switch_off(dev, info, wrqu, &extra[6]); + } else if (_rtw_memcmp(extra, "sw=", 3)) { + wrqu->data.length -= 3; + rtw_tdls_ch_switch( dev, info, wrqu, &extra[3] ); + } else if (_rtw_memcmp(extra, "dumpstack=", 10)) { + wrqu->data.length -= 10; + rtw_tdls_dump_ch(dev, info, wrqu, &extra[10]); + } else if (_rtw_memcmp(extra, "offchnum=", 9)) { + wrqu->data.length -= 9; + rtw_tdls_off_ch_num(dev, info, wrqu, &extra[9]); + } else if (_rtw_memcmp(extra, "choffset=", 9)) { + wrqu->data.length -= 9; + rtw_tdls_ch_offset(dev, info, wrqu, &extra[9]); + } else if (_rtw_memcmp(extra, "pson=", 5)) { + wrqu->data.length -= 5; + rtw_tdls_pson( dev, info, wrqu, &extra[5] ); + } else if (_rtw_memcmp(extra, "psoff=", 6)) { + wrqu->data.length -= 6; + rtw_tdls_psoff( dev, info, wrqu, &extra[6] ); + } + +#ifdef CONFIG_WFD + if (hal_chk_wl_func(padapter, WL_FUNC_MIRACAST)) { + if (_rtw_memcmp(extra, "setip=", 6)) { + wrqu->data.length -= 6; + rtw_tdls_setip(dev, info, wrqu, &extra[6]); + } else if (_rtw_memcmp(extra, "tprobe=", 6)) { + issue_tunneled_probe_req((_adapter *)rtw_netdev_priv(dev)); + } + } +#endif /* CONFIG_WFD */ + +#endif /* CONFIG_TDLS */ + + return ret; +} + + +static int rtw_tdls_get(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + +#ifdef CONFIG_TDLS + + DBG_871X( "[%s] extra = %s\n", __FUNCTION__, (char*) wrqu->data.pointer ); + + if ( _rtw_memcmp( wrqu->data.pointer, "ip", 2 ) ) + rtw_tdls_getip( dev, info, wrqu, extra ); + else if (_rtw_memcmp(wrqu->data.pointer, "port", 4)) + rtw_tdls_getport( dev, info, wrqu, extra ); + /* WFDTDLS, for sigma test */ + else if ( _rtw_memcmp(wrqu->data.pointer, "dis", 3)) + rtw_tdls_dis_result( dev, info, wrqu, extra ); + else if ( _rtw_memcmp(wrqu->data.pointer, "status", 6)) + rtw_wfd_tdls_status( dev, info, wrqu, extra ); + else if ( _rtw_memcmp(wrqu->data.pointer, "tdls_sta=", 9)) + rtw_tdls_getsta( dev, info, wrqu, extra ); + else if (_rtw_memcmp(wrqu->data.pointer, "best_ch", 7)) + rtw_tdls_get_best_ch(dev, info, wrqu, extra); +#endif /* CONFIG_TDLS */ + + return ret; +} + + + + + +#ifdef CONFIG_INTEL_WIDI +static int rtw_widi_set(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + process_intel_widi_cmd(padapter, extra); + + return ret; +} + +static int rtw_widi_set_probe_request(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + int ret = 0; + u8 *pbuf = NULL; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + pbuf = rtw_malloc(sizeof(l2_msg_t)); + if(pbuf) + { + if ( copy_from_user(pbuf, wrqu->data.pointer, wrqu->data.length) ) + ret = -EFAULT; + //_rtw_memcpy(pbuf, wrqu->data.pointer, wrqu->data.length); + + if( wrqu->data.flags == 0 ) + intel_widi_wk_cmd(padapter, INTEL_WIDI_ISSUE_PROB_WK, pbuf, sizeof(l2_msg_t)); + else if( wrqu->data.flags == 1 ) + rtw_set_wfd_rds_sink_info( padapter, (l2_msg_t *)pbuf ); + } + return ret; +} +#endif // CONFIG_INTEL_WIDI + +#ifdef CONFIG_MAC_LOOPBACK_DRIVER + +#if defined(CONFIG_RTL8188E) +#include +extern void rtl8188e_cal_txdesc_chksum(struct tx_desc *ptxdesc); +#define cal_txdesc_chksum rtl8188e_cal_txdesc_chksum +#ifdef CONFIG_SDIO_HCI || defined(CONFIG_GSPI_HCI) +extern void rtl8188es_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf); +#define fill_default_txdesc rtl8188es_fill_default_txdesc +#endif // CONFIG_SDIO_HCI +#endif // CONFIG_RTL8188E +#if defined(CONFIG_RTL8723B) +extern void rtl8723b_cal_txdesc_chksum(struct tx_desc *ptxdesc); +#define cal_txdesc_chksum rtl8723b_cal_txdesc_chksum +extern void rtl8723b_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf); +#define fill_default_txdesc rtl8723b_fill_default_txdesc +#endif // CONFIG_RTL8723B + +#if defined(CONFIG_RTL8703B) +/* extern void rtl8703b_cal_txdesc_chksum(struct tx_desc *ptxdesc); */ +#define cal_txdesc_chksum rtl8703b_cal_txdesc_chksum +/* extern void rtl8703b_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf); */ +#define fill_default_txdesc rtl8703b_fill_default_txdesc +#endif /* CONFIG_RTL8703B */ + +#if defined(CONFIG_RTL8192E) +extern void rtl8192e_cal_txdesc_chksum(struct tx_desc *ptxdesc); +#define cal_txdesc_chksum rtl8192e_cal_txdesc_chksum +#ifdef CONFIG_SDIO_HCI || defined(CONFIG_GSPI_HCI) +extern void rtl8192es_fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf); +#define fill_default_txdesc rtl8192es_fill_default_txdesc +#endif // CONFIG_SDIO_HCI +#endif //CONFIG_RTL8192E + +static s32 initLoopback(PADAPTER padapter) +{ + PLOOPBACKDATA ploopback; + + + if (padapter->ploopback == NULL) { + ploopback = (PLOOPBACKDATA)rtw_zmalloc(sizeof(LOOPBACKDATA)); + if (ploopback == NULL) return -ENOMEM; + + _rtw_init_sema(&ploopback->sema, 0); + ploopback->bstop = _TRUE; + ploopback->cnt = 0; + ploopback->size = 300; + _rtw_memset(ploopback->msg, 0, sizeof(ploopback->msg)); + + padapter->ploopback = ploopback; + } + + return 0; +} + +static void freeLoopback(PADAPTER padapter) +{ + PLOOPBACKDATA ploopback; + + + ploopback = padapter->ploopback; + if (ploopback) { + rtw_mfree((u8*)ploopback, sizeof(LOOPBACKDATA)); + padapter->ploopback = NULL; + } +} + +static s32 initpseudoadhoc(PADAPTER padapter) +{ + NDIS_802_11_NETWORK_INFRASTRUCTURE networkType; + s32 err; + + networkType = Ndis802_11IBSS; + err = rtw_set_802_11_infrastructure_mode(padapter, networkType); + if (err == _FALSE) return _FAIL; + + err = rtw_setopmode_cmd(padapter, networkType,_TRUE); + if (err == _FAIL) return _FAIL; + + return _SUCCESS; +} + +static s32 createpseudoadhoc(PADAPTER padapter) +{ + NDIS_802_11_AUTHENTICATION_MODE authmode; + struct mlme_priv *pmlmepriv; + NDIS_802_11_SSID *passoc_ssid; + WLAN_BSSID_EX *pdev_network; + u8 *pibss; + u8 ssid[] = "pseduo_ad-hoc"; + s32 err; + _irqL irqL; + + + pmlmepriv = &padapter->mlmepriv; + + authmode = Ndis802_11AuthModeOpen; + err = rtw_set_802_11_authentication_mode(padapter, authmode); + if (err == _FALSE) return _FAIL; + + passoc_ssid = &pmlmepriv->assoc_ssid; + _rtw_memset(passoc_ssid, 0, sizeof(NDIS_802_11_SSID)); + passoc_ssid->SsidLength = sizeof(ssid) - 1; + _rtw_memcpy(passoc_ssid->Ssid, ssid, passoc_ssid->SsidLength); + + pdev_network = &padapter->registrypriv.dev_network; + pibss = padapter->registrypriv.dev_network.MacAddress; + _rtw_memcpy(&pdev_network->Ssid, passoc_ssid, sizeof(NDIS_802_11_SSID)); + + rtw_update_registrypriv_dev_network(padapter); + rtw_generate_random_ibss(pibss); + + _enter_critical_bh(&pmlmepriv->lock, &irqL); + pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE; + _exit_critical_bh(&pmlmepriv->lock, &irqL); + +#if 0 + err = rtw_create_ibss_cmd(padapter, 0); + if (err == _FAIL) return _FAIL; +#else +{ + struct wlan_network *pcur_network; + struct sta_info *psta; + + //3 create a new psta + pcur_network = &pmlmepriv->cur_network; + + //clear psta in the cur_network, if any + psta = rtw_get_stainfo(&padapter->stapriv, pcur_network->network.MacAddress); + if (psta) rtw_free_stainfo(padapter, psta); + + psta = rtw_alloc_stainfo(&padapter->stapriv, pibss); + if (psta == NULL) return _FAIL; + + //3 join psudo AdHoc + pcur_network->join_res = 1; + pcur_network->aid = psta->aid = 1; + _rtw_memcpy(&pcur_network->network, pdev_network, get_WLAN_BSSID_EX_sz(pdev_network)); + + // set msr to WIFI_FW_ADHOC_STATE +#if 0 + Set_NETYPE0_MSR(padapter, WIFI_FW_ADHOC_STATE); +#else + { + u8 val8; + + val8 = rtw_read8(padapter, MSR); + val8 &= 0xFC; // clear NETYPE0 + val8 |= WIFI_FW_ADHOC_STATE & 0x3; + rtw_write8(padapter, MSR, val8); + } +#endif +} +#endif + + return _SUCCESS; +} + +static struct xmit_frame* createloopbackpkt(PADAPTER padapter, u32 size) +{ + struct xmit_priv *pxmitpriv; + struct xmit_frame *pframe; + struct xmit_buf *pxmitbuf; + struct pkt_attrib *pattrib; + struct tx_desc *desc; + u8 *pkt_start, *pkt_end, *ptr; + struct rtw_ieee80211_hdr *hdr; + s32 bmcast; + _irqL irqL; + + + if ((TXDESC_SIZE + WLANHDR_OFFSET + size) > MAX_XMITBUF_SZ) return NULL; + + pxmitpriv = &padapter->xmitpriv; + pframe = NULL; + + //2 1. allocate xmit frame + pframe = rtw_alloc_xmitframe(pxmitpriv); + if (pframe == NULL) return NULL; + pframe->padapter = padapter; + + //2 2. allocate xmit buffer + _enter_critical_bh(&pxmitpriv->lock, &irqL); + pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv); + _exit_critical_bh(&pxmitpriv->lock, &irqL); + if (pxmitbuf == NULL) { + rtw_free_xmitframe(pxmitpriv, pframe); + return NULL; + } + + pframe->pxmitbuf = pxmitbuf; + pframe->buf_addr = pxmitbuf->pbuf; + pxmitbuf->priv_data = pframe; + + //2 3. update_attrib() + pattrib = &pframe->attrib; + + // init xmitframe attribute + _rtw_memset(pattrib, 0, sizeof(struct pkt_attrib)); + + pattrib->ether_type = 0x8723; + _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN); + _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); + _rtw_memset(pattrib->dst, 0xFF, ETH_ALEN); + _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); + +// pattrib->dhcp_pkt = 0; +// pattrib->pktlen = 0; + pattrib->ack_policy = 0; +// pattrib->pkt_hdrlen = ETH_HLEN; + pattrib->hdrlen = WLAN_HDR_A3_LEN; + pattrib->subtype = WIFI_DATA; + pattrib->priority = 0; + pattrib->qsel = pattrib->priority; +// do_queue_select(padapter, pattrib); + pattrib->nr_frags = 1; + pattrib->encrypt = 0; + pattrib->bswenc = _FALSE; + pattrib->qos_en = _FALSE; + + bmcast = IS_MCAST(pattrib->ra); + if (bmcast) { + pattrib->mac_id = 1; + pattrib->psta = rtw_get_bcmc_stainfo(padapter); + } else { + pattrib->mac_id = 0; + pattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv)); + } + + pattrib->pktlen = size; + pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen; + + //2 4. fill TX descriptor + desc = (struct tx_desc*)pframe->buf_addr; + _rtw_memset(desc, 0, TXDESC_SIZE); + + fill_default_txdesc(pframe, (u8*)desc); + + // Hw set sequence number + ((PTXDESC)desc)->hwseq_en = 0; // HWSEQ_EN, 0:disable, 1:enable +// ((PTXDESC)desc)->hwseq_sel = 0; // HWSEQ_SEL + + ((PTXDESC)desc)->disdatafb = 1; + + // convert to little endian + desc->txdw0 = cpu_to_le32(desc->txdw0); + desc->txdw1 = cpu_to_le32(desc->txdw1); + desc->txdw2 = cpu_to_le32(desc->txdw2); + desc->txdw3 = cpu_to_le32(desc->txdw3); + desc->txdw4 = cpu_to_le32(desc->txdw4); + desc->txdw5 = cpu_to_le32(desc->txdw5); + desc->txdw6 = cpu_to_le32(desc->txdw6); + desc->txdw7 = cpu_to_le32(desc->txdw7); +#ifdef CONFIG_PCI_HCI + desc->txdw8 = cpu_to_le32(desc->txdw8); + desc->txdw9 = cpu_to_le32(desc->txdw9); + desc->txdw10 = cpu_to_le32(desc->txdw10); + desc->txdw11 = cpu_to_le32(desc->txdw11); + desc->txdw12 = cpu_to_le32(desc->txdw12); + desc->txdw13 = cpu_to_le32(desc->txdw13); + desc->txdw14 = cpu_to_le32(desc->txdw14); + desc->txdw15 = cpu_to_le32(desc->txdw15); +#endif + + cal_txdesc_chksum(desc); + + //2 5. coalesce + pkt_start = pframe->buf_addr + TXDESC_SIZE; + pkt_end = pkt_start + pattrib->last_txcmdsz; + + //3 5.1. make wlan header, make_wlanhdr() + hdr = (struct rtw_ieee80211_hdr *)pkt_start; + SetFrameSubType(&hdr->frame_ctl, pattrib->subtype); + _rtw_memcpy(hdr->addr1, pattrib->dst, ETH_ALEN); // DA + _rtw_memcpy(hdr->addr2, pattrib->src, ETH_ALEN); // SA + _rtw_memcpy(hdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN); // RA, BSSID + + //3 5.2. make payload + ptr = pkt_start + pattrib->hdrlen; + get_random_bytes(ptr, pkt_end - ptr); + + pxmitbuf->len = TXDESC_SIZE + pattrib->last_txcmdsz; + pxmitbuf->ptail += pxmitbuf->len; + + return pframe; +} + +static void freeloopbackpkt(PADAPTER padapter, struct xmit_frame *pframe) +{ + struct xmit_priv *pxmitpriv; + struct xmit_buf *pxmitbuf; + + + pxmitpriv = &padapter->xmitpriv; + pxmitbuf = pframe->pxmitbuf; + + rtw_free_xmitframe(pxmitpriv, pframe); + rtw_free_xmitbuf(pxmitpriv, pxmitbuf); +} + +static void printdata(u8 *pbuf, u32 len) +{ + u32 i, val; + + + for (i = 0; (i+4) <= len; i+=4) { + printk("%08X", *(u32*)(pbuf + i)); + if ((i+4) & 0x1F) printk(" "); + else printk("\n"); + } + + if (i < len) + { +#ifdef CONFIG_BIG_ENDIAN + for (; i < len, i++) + printk("%02X", pbuf+i); +#else // CONFIG_LITTLE_ENDIAN +#if 0 + val = 0; + _rtw_memcpy(&val, pbuf + i, len - i); + printk("%8X", val); +#else + u8 str[9]; + u8 n; + val = 0; + n = len - i; + _rtw_memcpy(&val, pbuf+i, n); + sprintf(str, "%08X", val); + n = (4 - n) * 2; + printk("%8s", str+n); +#endif +#endif // CONFIG_LITTLE_ENDIAN + } + printk("\n"); +} + +static u8 pktcmp(PADAPTER padapter, u8 *txbuf, u32 txsz, u8 *rxbuf, u32 rxsz) +{ + PHAL_DATA_TYPE phal; + struct recv_stat *prxstat; + struct recv_stat report; + PRXREPORT prxreport; + u32 drvinfosize; + u32 rxpktsize; + u8 fcssize; + u8 ret = _FALSE; + + prxstat = (struct recv_stat*)rxbuf; + report.rxdw0 = le32_to_cpu(prxstat->rxdw0); + report.rxdw1 = le32_to_cpu(prxstat->rxdw1); + report.rxdw2 = le32_to_cpu(prxstat->rxdw2); + report.rxdw3 = le32_to_cpu(prxstat->rxdw3); + report.rxdw4 = le32_to_cpu(prxstat->rxdw4); + report.rxdw5 = le32_to_cpu(prxstat->rxdw5); + + prxreport = (PRXREPORT)&report; + drvinfosize = prxreport->drvinfosize << 3; + rxpktsize = prxreport->pktlen; + + phal = GET_HAL_DATA(padapter); + if (phal->ReceiveConfig & RCR_APPFCS) fcssize = IEEE80211_FCS_LEN; + else fcssize = 0; + + if ((txsz - TXDESC_SIZE) != (rxpktsize - fcssize)) { + DBG_8192C("%s: ERROR! size not match tx/rx=%d/%d !\n", + __func__, txsz - TXDESC_SIZE, rxpktsize - fcssize); + ret = _FALSE; + } else { + ret = _rtw_memcmp(txbuf + TXDESC_SIZE,\ + rxbuf + RXDESC_SIZE + drvinfosize,\ + txsz - TXDESC_SIZE); + if (ret == _FALSE) { + DBG_8192C("%s: ERROR! pkt content mismatch!\n", __func__); + } + } + + if (ret == _FALSE) + { + DBG_8192C("\n%s: TX PKT total=%d, desc=%d, content=%d\n", + __func__, txsz, TXDESC_SIZE, txsz - TXDESC_SIZE); + DBG_8192C("%s: TX DESC size=%d\n", __func__, TXDESC_SIZE); + printdata(txbuf, TXDESC_SIZE); + DBG_8192C("%s: TX content size=%d\n", __func__, txsz - TXDESC_SIZE); + printdata(txbuf + TXDESC_SIZE, txsz - TXDESC_SIZE); + + DBG_8192C("\n%s: RX PKT read=%d offset=%d(%d,%d) content=%d\n", + __func__, rxsz, RXDESC_SIZE + drvinfosize, RXDESC_SIZE, drvinfosize, rxpktsize); + if (rxpktsize != 0) + { + DBG_8192C("%s: RX DESC size=%d\n", __func__, RXDESC_SIZE); + printdata(rxbuf, RXDESC_SIZE); + DBG_8192C("%s: RX drvinfo size=%d\n", __func__, drvinfosize); + printdata(rxbuf + RXDESC_SIZE, drvinfosize); + DBG_8192C("%s: RX content size=%d\n", __func__, rxpktsize); + printdata(rxbuf + RXDESC_SIZE + drvinfosize, rxpktsize); + } else { + DBG_8192C("%s: RX data size=%d\n", __func__, rxsz); + printdata(rxbuf, rxsz); + } + } + + return ret; +} + +thread_return lbk_thread(thread_context context) +{ + s32 err; + PADAPTER padapter; + PLOOPBACKDATA ploopback; + struct xmit_frame *pxmitframe; + u32 cnt, ok, fail, headerlen; + u32 pktsize; + u32 ff_hwaddr; + + + padapter = (PADAPTER)context; + ploopback = padapter->ploopback; + if (ploopback == NULL) return -1; + cnt = 0; + ok = 0; + fail = 0; + + daemonize("%s", "RTW_LBK_THREAD"); + allow_signal(SIGTERM); + + do { + if (ploopback->size == 0) { + get_random_bytes(&pktsize, 4); + pktsize = (pktsize % 1535) + 1; // 1~1535 + } else + pktsize = ploopback->size; + + pxmitframe = createloopbackpkt(padapter, pktsize); + if (pxmitframe == NULL) { + sprintf(ploopback->msg, "loopback FAIL! 3. create Packet FAIL!"); + break; + } + + ploopback->txsize = TXDESC_SIZE + pxmitframe->attrib.last_txcmdsz; + _rtw_memcpy(ploopback->txbuf, pxmitframe->buf_addr, ploopback->txsize); + ff_hwaddr = rtw_get_ff_hwaddr(pxmitframe); + cnt++; + DBG_8192C("%s: wirte port cnt=%d size=%d\n", __func__, cnt, ploopback->txsize); + pxmitframe->pxmitbuf->pdata = ploopback->txbuf; + rtw_write_port(padapter, ff_hwaddr, ploopback->txsize, (u8 *)pxmitframe->pxmitbuf); + + // wait for rx pkt + _rtw_down_sema(&ploopback->sema); + + err = pktcmp(padapter, ploopback->txbuf, ploopback->txsize, ploopback->rxbuf, ploopback->rxsize); + if (err == _TRUE) + ok++; + else + fail++; + + ploopback->txsize = 0; + _rtw_memset(ploopback->txbuf, 0, 0x8000); + ploopback->rxsize = 0; + _rtw_memset(ploopback->rxbuf, 0, 0x8000); + + freeloopbackpkt(padapter, pxmitframe); + pxmitframe = NULL; + + if (signal_pending(current)) { + flush_signals(current); + } + + if ((ploopback->bstop == _TRUE) || + ((ploopback->cnt != 0) && (ploopback->cnt == cnt))) + { + u32 ok_rate, fail_rate, all; + all = cnt; + ok_rate = (ok*100)/all; + fail_rate = (fail*100)/all; + sprintf(ploopback->msg,\ + "loopback result: ok=%d%%(%d/%d),error=%d%%(%d/%d)",\ + ok_rate, ok, all, fail_rate, fail, all); + break; + } + } while (1); + + ploopback->bstop = _TRUE; + + thread_exit(); +} + +static void loopbackTest(PADAPTER padapter, u32 cnt, u32 size, u8* pmsg) +{ + PLOOPBACKDATA ploopback; + u32 len; + s32 err; + + + ploopback = padapter->ploopback; + + if (ploopback) + { + if (ploopback->bstop == _FALSE) { + ploopback->bstop = _TRUE; + _rtw_up_sema(&ploopback->sema); + } + len = 0; + do { + len = strlen(ploopback->msg); + if (len) break; + rtw_msleep_os(1); + } while (1); + _rtw_memcpy(pmsg, ploopback->msg, len+1); + freeLoopback(padapter); + + return; + } + + // disable dynamic algorithm + rtw_phydm_ability_backup(padapter); + rtw_phydm_func_disable_all(padapter); + + // create pseudo ad-hoc connection + err = initpseudoadhoc(padapter); + if (err == _FAIL) { + sprintf(pmsg, "loopback FAIL! 1.1 init ad-hoc FAIL!"); + return; + } + + err = createpseudoadhoc(padapter); + if (err == _FAIL) { + sprintf(pmsg, "loopback FAIL! 1.2 create ad-hoc master FAIL!"); + return; + } + + err = initLoopback(padapter); + if (err) { + sprintf(pmsg, "loopback FAIL! 2. init FAIL! error code=%d", err); + return; + } + + ploopback = padapter->ploopback; + + ploopback->bstop = _FALSE; + ploopback->cnt = cnt; + ploopback->size = size; + ploopback->lbkthread = kthread_run(lbk_thread, padapter, "RTW_LBK_THREAD"); + if (IS_ERR(padapter->lbkthread)) + { + freeLoopback(padapter); + sprintf(pmsg, "loopback start FAIL! cnt=%d", cnt); + return; + } + + sprintf(pmsg, "loopback start! cnt=%d", cnt); +} +#endif // CONFIG_MAC_LOOPBACK_DRIVER + +static int rtw_test( + struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + u32 len; + u8 *pbuf, *pch; + char *ptmp; + u8 *delim = ","; + PADAPTER padapter = rtw_netdev_priv(dev); + + + DBG_871X("+%s\n", __func__); + len = wrqu->data.length; + + pbuf = (u8*)rtw_zmalloc(len); + if (pbuf == NULL) { + DBG_871X("%s: no memory!\n", __func__); + return -ENOMEM; + } + + if (copy_from_user(pbuf, wrqu->data.pointer, len)) { + rtw_mfree(pbuf, len); + DBG_871X("%s: copy from user fail!\n", __func__); + return -EFAULT; + } + DBG_871X("%s: string=\"%s\"\n", __func__, pbuf); + + ptmp = (char*)pbuf; + pch = strsep(&ptmp, delim); + if ((pch == NULL) || (strlen(pch) == 0)) { + rtw_mfree(pbuf, len); + DBG_871X("%s: parameter error(level 1)!\n", __func__); + return -EFAULT; + } + +#ifdef CONFIG_MAC_LOOPBACK_DRIVER + if (strcmp(pch, "loopback") == 0) + { + s32 cnt = 0; + u32 size = 64; + + pch = strsep(&ptmp, delim); + if ((pch == NULL) || (strlen(pch) == 0)) { + rtw_mfree(pbuf, len); + DBG_871X("%s: parameter error(level 2)!\n", __func__); + return -EFAULT; + } + + sscanf(pch, "%d", &cnt); + DBG_871X("%s: loopback cnt=%d\n", __func__, cnt); + + pch = strsep(&ptmp, delim); + if ((pch == NULL) || (strlen(pch) == 0)) { + rtw_mfree(pbuf, len); + DBG_871X("%s: parameter error(level 2)!\n", __func__); + return -EFAULT; + } + + sscanf(pch, "%d", &size); + DBG_871X("%s: loopback size=%d\n", __func__, size); + + loopbackTest(padapter, cnt, size, extra); + wrqu->data.length = strlen(extra) + 1; + + goto free_buf; + } +#endif + + +#ifdef CONFIG_BT_COEXIST + if (strcmp(pch, "bton") == 0) { + rtw_btcoex_SetManualControl(padapter, _FALSE); + goto free_buf; + } else if (strcmp(pch, "btoff") == 0) { + rtw_btcoex_SetManualControl(padapter, _TRUE); + goto free_buf; + } +#endif + + if (strcmp(pch, "h2c") == 0) { + u8 param[8]; + u8 count = 0; + u32 tmp; + u8 i; + u32 pos; + s32 ret; + + do { + pch = strsep(&ptmp, delim); + if ((pch == NULL) || (strlen(pch) == 0)) + break; + + sscanf(pch, "%x", &tmp); + param[count++] = (u8)tmp; + } while (count < 8); + + if (count == 0) { + rtw_mfree(pbuf, len); + DBG_871X("%s: parameter error(level 2)!\n", __func__); + return -EFAULT; + } + + ret = rtw_hal_fill_h2c_cmd(padapter, param[0], count-1, ¶m[1]); + + pos = sprintf(extra, "H2C ID=0x%02x content=", param[0]); + for (i=1; idata.length = strlen(extra) + 1; + + goto free_buf; + } + +free_buf: + rtw_mfree(pbuf, len); + return 0; +} + +static iw_handler rtw_handlers[] = +{ + NULL, /* SIOCSIWCOMMIT */ + rtw_wx_get_name, /* SIOCGIWNAME */ + dummy, /* SIOCSIWNWID */ + dummy, /* SIOCGIWNWID */ + rtw_wx_set_freq, /* SIOCSIWFREQ */ + rtw_wx_get_freq, /* SIOCGIWFREQ */ + rtw_wx_set_mode, /* SIOCSIWMODE */ + rtw_wx_get_mode, /* SIOCGIWMODE */ + dummy, /* SIOCSIWSENS */ + rtw_wx_get_sens, /* SIOCGIWSENS */ + NULL, /* SIOCSIWRANGE */ + rtw_wx_get_range, /* SIOCGIWRANGE */ + rtw_wx_set_priv, /* SIOCSIWPRIV */ + NULL, /* SIOCGIWPRIV */ + NULL, /* SIOCSIWSTATS */ + NULL, /* SIOCGIWSTATS */ + dummy, /* SIOCSIWSPY */ + dummy, /* SIOCGIWSPY */ + NULL, /* SIOCGIWTHRSPY */ + NULL, /* SIOCWIWTHRSPY */ + rtw_wx_set_wap, /* SIOCSIWAP */ + rtw_wx_get_wap, /* SIOCGIWAP */ + rtw_wx_set_mlme, /* request MLME operation; uses struct iw_mlme */ + dummy, /* SIOCGIWAPLIST -- depricated */ + rtw_wx_set_scan, /* SIOCSIWSCAN */ + rtw_wx_get_scan, /* SIOCGIWSCAN */ + rtw_wx_set_essid, /* SIOCSIWESSID */ + rtw_wx_get_essid, /* SIOCGIWESSID */ + dummy, /* SIOCSIWNICKN */ + rtw_wx_get_nick, /* SIOCGIWNICKN */ + NULL, /* -- hole -- */ + NULL, /* -- hole -- */ + rtw_wx_set_rate, /* SIOCSIWRATE */ + rtw_wx_get_rate, /* SIOCGIWRATE */ + rtw_wx_set_rts, /* SIOCSIWRTS */ + rtw_wx_get_rts, /* SIOCGIWRTS */ + rtw_wx_set_frag, /* SIOCSIWFRAG */ + rtw_wx_get_frag, /* SIOCGIWFRAG */ + dummy, /* SIOCSIWTXPOW */ + dummy, /* SIOCGIWTXPOW */ + dummy, /* SIOCSIWRETRY */ + rtw_wx_get_retry, /* SIOCGIWRETRY */ + rtw_wx_set_enc, /* SIOCSIWENCODE */ + rtw_wx_get_enc, /* SIOCGIWENCODE */ + dummy, /* SIOCSIWPOWER */ + rtw_wx_get_power, /* SIOCGIWPOWER */ + NULL, /*---hole---*/ + NULL, /*---hole---*/ + rtw_wx_set_gen_ie, /* SIOCSIWGENIE */ + NULL, /* SIOCGWGENIE */ + rtw_wx_set_auth, /* SIOCSIWAUTH */ + NULL, /* SIOCGIWAUTH */ + rtw_wx_set_enc_ext, /* SIOCSIWENCODEEXT */ + NULL, /* SIOCGIWENCODEEXT */ + rtw_wx_set_pmkid, /* SIOCSIWPMKSA */ + NULL, /*---hole---*/ +}; + + +static const struct iw_priv_args rtw_private_args[] = { + { + SIOCIWFIRSTPRIV + 0x0, + IW_PRIV_TYPE_CHAR | 0x7FF, 0, "write" + }, + { + SIOCIWFIRSTPRIV + 0x1, + IW_PRIV_TYPE_CHAR | 0x7FF, + IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_FIXED | IFNAMSIZ, "read" + }, + { + SIOCIWFIRSTPRIV + 0x2, 0, 0, "driver_ext" + }, + { + SIOCIWFIRSTPRIV + 0x3, 0, 0, "mp_ioctl" + }, + { + SIOCIWFIRSTPRIV + 0x4, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "apinfo" + }, + { + SIOCIWFIRSTPRIV + 0x5, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, 0, "setpid" + }, + { + SIOCIWFIRSTPRIV + 0x6, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "wps_start" + }, +//for PLATFORM_MT53XX + { + SIOCIWFIRSTPRIV + 0x7, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "get_sensitivity" + }, + { + SIOCIWFIRSTPRIV + 0x8, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "wps_prob_req_ie" + }, + { + SIOCIWFIRSTPRIV + 0x9, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "wps_assoc_req_ie" + }, + +//for RTK_DMP_PLATFORM + { + SIOCIWFIRSTPRIV + 0xA, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "channel_plan" + }, + + { + SIOCIWFIRSTPRIV + 0xB, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, 0, "dbg" + }, + { + SIOCIWFIRSTPRIV + 0xC, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 3, 0, "rfw" + }, + { + SIOCIWFIRSTPRIV + 0xD, + IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_FIXED | IFNAMSIZ, "rfr" + }, +#if 0 + { + SIOCIWFIRSTPRIV + 0xE,0,0, "wowlan_ctrl" + }, +#endif + { + SIOCIWFIRSTPRIV + 0x10, + IW_PRIV_TYPE_CHAR | 1024, 0, "p2p_set" + }, + { + SIOCIWFIRSTPRIV + 0x11, + IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , "p2p_get" + }, + { + SIOCIWFIRSTPRIV + 0x12, 0, 0, "NULL" + }, + { + SIOCIWFIRSTPRIV + 0x13, + IW_PRIV_TYPE_CHAR | 64, IW_PRIV_TYPE_CHAR | 64 , "p2p_get2" + }, + { + SIOCIWFIRSTPRIV + 0x14, + IW_PRIV_TYPE_CHAR | 64, 0, "tdls" + }, + { + SIOCIWFIRSTPRIV + 0x15, + IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | 1024 , "tdls_get" + }, + { + SIOCIWFIRSTPRIV + 0x16, + IW_PRIV_TYPE_CHAR | 64, 0, "pm_set" + }, + + {SIOCIWFIRSTPRIV + 0x18, IW_PRIV_TYPE_CHAR | IFNAMSIZ , 0 , "rereg_nd_name"}, +#ifdef CONFIG_MP_INCLUDED + {SIOCIWFIRSTPRIV + 0x1A, IW_PRIV_TYPE_CHAR | 1024, 0, "NULL"}, + {SIOCIWFIRSTPRIV + 0x1B, IW_PRIV_TYPE_CHAR | 128, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "NULL"}, +#else + {SIOCIWFIRSTPRIV + 0x1A, IW_PRIV_TYPE_CHAR | 1024, 0, "efuse_set"}, + {SIOCIWFIRSTPRIV + 0x1B, IW_PRIV_TYPE_CHAR | 128, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_get"}, +#endif + { + SIOCIWFIRSTPRIV + 0x1D, + IW_PRIV_TYPE_CHAR | 40, IW_PRIV_TYPE_CHAR | 0x7FF, "test" + }, + +#ifdef CONFIG_INTEL_WIDI + { + SIOCIWFIRSTPRIV + 0x1E, + IW_PRIV_TYPE_CHAR | 1024, 0, "widi_set" + }, + { + SIOCIWFIRSTPRIV + 0x1F, + IW_PRIV_TYPE_CHAR | 128, 0, "widi_prob_req" + }, +#endif // CONFIG_INTEL_WIDI + +#ifdef CONFIG_MP_INCLUDED + { SIOCIWFIRSTPRIV + 0x0E, IW_PRIV_TYPE_CHAR | 1024, 0 , ""}, //set + { SIOCIWFIRSTPRIV + 0x0F, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , ""},//get +/* --- sub-ioctls definitions --- */ + { MP_START , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_start" }, //set + { MP_PHYPARA, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_phypara" },//get + { MP_STOP , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_stop" }, //set + { MP_CHANNEL , IW_PRIV_TYPE_CHAR | 1024 , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_channel" },//get + { MP_BANDWIDTH , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_bandwidth"}, //set + { MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" },//get + { MP_RESET_STATS , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_reset_stats"}, + { MP_QUERY , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , "mp_query"}, //get + { READ_REG , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "read_reg" }, + { MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" }, + { READ_RF , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "read_rf" }, + { MP_PSD , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_psd"}, + { MP_DUMP, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_dump" }, + { MP_TXPOWER , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_txpower"}, + { MP_ANT_TX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ant_tx"}, + { MP_ANT_RX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ant_rx"}, + { WRITE_REG , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "write_reg" }, + { WRITE_RF , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "write_rf" }, + { MP_CTX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ctx"}, + { MP_ARX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_arx"}, + { MP_THER , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ther"}, + { EFUSE_SET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_set" }, + { EFUSE_GET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_get" }, + { MP_PWRTRK , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrtrk"}, + { MP_QueryDrvStats, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_drvquery" }, + { MP_IOCTL, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_ioctl"}, // mp_ioctl + { MP_SetRFPathSwh, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_setrfpath" }, + { MP_PwrCtlDM, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_pwrctldm" }, + { MP_GET_TXPOWER_INX, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_get_txpower" }, + { MP_GETVER, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_priv_ver" }, + { MP_MON, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_mon" }, + { EFUSE_MASK, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_mask" }, + { EFUSE_FILE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_file" }, + { MP_TX, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_tx" }, + { MP_RX, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rx" }, + { MP_HW_TX_MODE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_hxtx" }, +#ifdef CONFIG_RTW_CUSTOMER_STR + { MP_CUSTOMER_STR, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "customer_str" }, +#endif +#if defined(CONFIG_RTL8723B) + { MP_SetBT, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_setbt" }, + { MP_DISABLE_BT_COEXIST, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_disa_btcoex"}, +#endif + { CTA_TEST, IW_PRIV_TYPE_CHAR | 1024, 0, "cta_test"}, +#endif +#ifdef CONFIG_SDIO_INDIRECT_ACCESS + { MP_SD_IREAD, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "sd_iread" }, + { MP_SD_IWRITE, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "sd_iwrite" }, +#endif +}; + +static iw_handler rtw_private_handler[] = +{ + rtw_wx_write32, //0x00 + rtw_wx_read32, //0x01 + rtw_drvext_hdl, //0x02 + rtw_mp_ioctl_hdl, //0x03 + +// for MM DTV platform + rtw_get_ap_info, //0x04 + + rtw_set_pid, //0x05 + rtw_wps_start, //0x06 + +// for PLATFORM_MT53XX + rtw_wx_get_sensitivity, //0x07 + rtw_wx_set_mtk_wps_probe_ie, //0x08 + rtw_wx_set_mtk_wps_ie, //0x09 + +// for RTK_DMP_PLATFORM +// Set Channel depend on the country code + rtw_wx_set_channel_plan, //0x0A + + rtw_dbg_port, //0x0B + rtw_wx_write_rf, //0x0C + rtw_wx_read_rf, //0x0D +#ifdef CONFIG_MP_INCLUDED + rtw_mp_set, //0x0E + rtw_mp_get, //0x0F +#else + rtw_wx_priv_null, //0x0E + rtw_wx_priv_null, //0x0F +#endif + rtw_p2p_set, //0x10 + rtw_p2p_get, //0x11 + NULL, //0x12 + rtw_p2p_get2, //0x13 + + rtw_tdls, //0x14 + rtw_tdls_get, //0x15 + + rtw_pm_set, //0x16 + rtw_wx_priv_null, //0x17 + rtw_rereg_nd_name, //0x18 + rtw_wx_priv_null, //0x19 +#ifdef CONFIG_MP_INCLUDED + rtw_wx_priv_null, //0x1A + rtw_wx_priv_null, //0x1B +#else + rtw_mp_efuse_set, //0x1A + rtw_mp_efuse_get, //0x1B +#endif + NULL, // 0x1C is reserved for hostapd + rtw_test, // 0x1D +#ifdef CONFIG_INTEL_WIDI + rtw_widi_set, //0x1E + rtw_widi_set_probe_request, //0x1F +#endif // CONFIG_INTEL_WIDI +}; + + +#if WIRELESS_EXT >= 17 +static struct iw_statistics *rtw_get_wireless_stats(struct net_device *dev) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct iw_statistics *piwstats=&padapter->iwstats; + int tmp_level = 0; + int tmp_qual = 0; + int tmp_noise = 0; + + if (check_fwstate(&padapter->mlmepriv, _FW_LINKED) != _TRUE) + { + piwstats->qual.qual = 0; + piwstats->qual.level = 0; + piwstats->qual.noise = 0; + //DBG_871X("No link level:%d, qual:%d, noise:%d\n", tmp_level, tmp_qual, tmp_noise); + } + else{ + #ifdef CONFIG_SIGNAL_DISPLAY_DBM + tmp_level = translate_percentage_to_dbm(padapter->recvpriv.signal_strength); + #else + #ifdef CONFIG_SIGNAL_SCALE_MAPPING + tmp_level = padapter->recvpriv.signal_strength; + #else + { + /* Do signal scale mapping when using percentage as the unit of signal strength, since the scale mapping is skipped in odm */ + + HAL_DATA_TYPE *pHal = GET_HAL_DATA(padapter); + + tmp_level = (u8)odm_SignalScaleMapping(&pHal->odmpriv, padapter->recvpriv.signal_strength); + } + #endif + #endif + + tmp_qual = padapter->recvpriv.signal_qual; + rtw_get_noise(padapter); + tmp_noise = padapter->recvpriv.noise; + //DBG_871X("level:%d, qual:%d, noise:%d, rssi (%d)\n", tmp_level, tmp_qual, tmp_noise,padapter->recvpriv.rssi); + + piwstats->qual.level = tmp_level; + piwstats->qual.qual = tmp_qual; + piwstats->qual.noise = tmp_noise; + } +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,14)) + piwstats->qual.updated = IW_QUAL_ALL_UPDATED ;//|IW_QUAL_DBM; +#else +#ifdef RTK_DMP_PLATFORM + //IW_QUAL_DBM= 0x8, if driver use this flag, wireless extension will show value of dbm. + //remove this flag for show percentage 0~100 + piwstats->qual.updated = 0x07; +#else + piwstats->qual.updated = 0x0f; +#endif +#endif + + #ifdef CONFIG_SIGNAL_DISPLAY_DBM + piwstats->qual.updated = piwstats->qual.updated | IW_QUAL_DBM; + #endif + + return &padapter->iwstats; +} +#endif + +#ifdef CONFIG_WIRELESS_EXT +struct iw_handler_def rtw_handlers_def = +{ + .standard = rtw_handlers, + .num_standard = sizeof(rtw_handlers) / sizeof(iw_handler), +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33)) || defined(CONFIG_WEXT_PRIV) + .private = rtw_private_handler, + .private_args = (struct iw_priv_args *)rtw_private_args, + .num_private = sizeof(rtw_private_handler) / sizeof(iw_handler), + .num_private_args = sizeof(rtw_private_args) / sizeof(struct iw_priv_args), +#endif +#if WIRELESS_EXT >= 17 + .get_wireless_stats = rtw_get_wireless_stats, +#endif +}; +#endif + +// copy from net/wireless/wext.c start +/* ---------------------------------------------------------------- */ +/* + * Calculate size of private arguments + */ +static const char iw_priv_type_size[] = { + 0, /* IW_PRIV_TYPE_NONE */ + 1, /* IW_PRIV_TYPE_BYTE */ + 1, /* IW_PRIV_TYPE_CHAR */ + 0, /* Not defined */ + sizeof(__u32), /* IW_PRIV_TYPE_INT */ + sizeof(struct iw_freq), /* IW_PRIV_TYPE_FLOAT */ + sizeof(struct sockaddr), /* IW_PRIV_TYPE_ADDR */ + 0, /* Not defined */ +}; + +static int get_priv_size(__u16 args) +{ + int num = args & IW_PRIV_SIZE_MASK; + int type = (args & IW_PRIV_TYPE_MASK) >> 12; + + return num * iw_priv_type_size[type]; +} +// copy from net/wireless/wext.c end + + +static int _rtw_ioctl_wext_private(struct net_device *dev, union iwreq_data *wrq_data) +{ + int err = 0; + u8 *input = NULL; + u32 input_len = 0; + const char delim[] = " "; + u8 *output = NULL; + u32 output_len = 0; + u32 count = 0; + u8 *buffer= NULL; + u32 buffer_len = 0; + char *ptr = NULL; + u8 cmdname[17] = {0}; // IFNAMSIZ+1 + u32 cmdlen; + s32 len; + u8 *extra = NULL; + u32 extra_size = 0; + + s32 k; + const iw_handler *priv; /* Private ioctl */ + const struct iw_priv_args *priv_args; /* Private ioctl description */ + u32 num_priv; /* Number of ioctl */ + u32 num_priv_args; /* Number of descriptions */ + iw_handler handler; + int temp; + int subcmd = 0; /* sub-ioctl index */ + int offset = 0; /* Space for sub-ioctl index */ + + union iwreq_data wdata; + + _rtw_memcpy(&wdata, wrq_data, sizeof(wdata)); + + input_len = wdata.data.length; + input = rtw_zmalloc(input_len); + if (NULL == input || input_len == 0) + return -ENOMEM; + if (copy_from_user(input, wdata.data.pointer, input_len)) { + err = -EFAULT; + goto exit; + } + input[input_len - 1] = '\0'; + ptr = input; + len = input_len; + + if (ptr == NULL) { + err = -EOPNOTSUPP; + goto exit; + } + + sscanf(ptr, "%16s", cmdname); + cmdlen = strlen(cmdname); + DBG_871X("%s: cmd=%s\n", __func__, cmdname); + + // skip command string + if (cmdlen > 0) + cmdlen += 1; // skip one space + ptr += cmdlen; + len -= cmdlen; + DBG_871X("%s: parameters=%s\n", __func__, ptr); + + priv = rtw_private_handler; + priv_args = rtw_private_args; + num_priv = sizeof(rtw_private_handler) / sizeof(iw_handler); + num_priv_args = sizeof(rtw_private_args) / sizeof(struct iw_priv_args); + + if (num_priv_args == 0) { + err = -EOPNOTSUPP; + goto exit; + } + + /* Search the correct ioctl */ + k = -1; + while((++k < num_priv_args) && strcmp(priv_args[k].name, cmdname)); + + /* If not found... */ + if (k == num_priv_args) { + err = -EOPNOTSUPP; + goto exit; + } + + /* Watch out for sub-ioctls ! */ + if (priv_args[k].cmd < SIOCDEVPRIVATE) + { + int j = -1; + + /* Find the matching *real* ioctl */ + while ((++j < num_priv_args) && ((priv_args[j].name[0] != '\0') || + (priv_args[j].set_args != priv_args[k].set_args) || + (priv_args[j].get_args != priv_args[k].get_args))); + + /* If not found... */ + if (j == num_priv_args) { + err = -EINVAL; + goto exit; + } + + /* Save sub-ioctl number */ + subcmd = priv_args[k].cmd; + /* Reserve one int (simplify alignment issues) */ + offset = sizeof(__u32); + /* Use real ioctl definition from now on */ + k = j; + } + + buffer = rtw_zmalloc(4096); + if (NULL == buffer) { + err = -ENOMEM; + goto exit; + } + + /* If we have to set some data */ + if ((priv_args[k].set_args & IW_PRIV_TYPE_MASK) && + (priv_args[k].set_args & IW_PRIV_SIZE_MASK)) + { + u8 *str; + + switch (priv_args[k].set_args & IW_PRIV_TYPE_MASK) + { + case IW_PRIV_TYPE_BYTE: + /* Fetch args */ + count = 0; + do { + str = strsep(&ptr, delim); + if (NULL == str) break; + sscanf(str, "%i", &temp); + buffer[count++] = (u8)temp; + } while (1); + buffer_len = count; + + /* Number of args to fetch */ + wdata.data.length = count; + if (wdata.data.length > (priv_args[k].set_args & IW_PRIV_SIZE_MASK)) + wdata.data.length = priv_args[k].set_args & IW_PRIV_SIZE_MASK; + + break; + + case IW_PRIV_TYPE_INT: + /* Fetch args */ + count = 0; + do { + str = strsep(&ptr, delim); + if (NULL == str) break; + sscanf(str, "%i", &temp); + ((s32*)buffer)[count++] = (s32)temp; + } while (1); + buffer_len = count * sizeof(s32); + + /* Number of args to fetch */ + wdata.data.length = count; + if (wdata.data.length > (priv_args[k].set_args & IW_PRIV_SIZE_MASK)) + wdata.data.length = priv_args[k].set_args & IW_PRIV_SIZE_MASK; + + break; + + case IW_PRIV_TYPE_CHAR: + if (len > 0) + { + /* Size of the string to fetch */ + wdata.data.length = len; + if (wdata.data.length > (priv_args[k].set_args & IW_PRIV_SIZE_MASK)) + wdata.data.length = priv_args[k].set_args & IW_PRIV_SIZE_MASK; + + /* Fetch string */ + _rtw_memcpy(buffer, ptr, wdata.data.length); + } + else + { + wdata.data.length = 1; + buffer[0] = '\0'; + } + buffer_len = wdata.data.length; + break; + + default: + DBG_8192C("%s: Not yet implemented...\n", __func__); + err = -1; + goto exit; + } + + if ((priv_args[k].set_args & IW_PRIV_SIZE_FIXED) && + (wdata.data.length != (priv_args[k].set_args & IW_PRIV_SIZE_MASK))) + { + DBG_8192C("%s: The command %s needs exactly %d argument(s)...\n", + __func__, cmdname, priv_args[k].set_args & IW_PRIV_SIZE_MASK); + err = -EINVAL; + goto exit; + } + } /* if args to set */ + else + { + wdata.data.length = 0L; + } + + /* Those two tests are important. They define how the driver + * will have to handle the data */ + if ((priv_args[k].set_args & IW_PRIV_SIZE_FIXED) && + ((get_priv_size(priv_args[k].set_args) + offset) <= IFNAMSIZ)) + { + /* First case : all SET args fit within wrq */ + if (offset) + wdata.mode = subcmd; + _rtw_memcpy(wdata.name + offset, buffer, IFNAMSIZ - offset); + } + else + { + if ((priv_args[k].set_args == 0) && + (priv_args[k].get_args & IW_PRIV_SIZE_FIXED) && + (get_priv_size(priv_args[k].get_args) <= IFNAMSIZ)) + { + /* Second case : no SET args, GET args fit within wrq */ + if (offset) + wdata.mode = subcmd; + } + else + { + /* Third case : args won't fit in wrq, or variable number of args */ + if (copy_to_user(wdata.data.pointer, buffer, buffer_len)) { + err = -EFAULT; + goto exit; + } + wdata.data.flags = subcmd; + } + } + + rtw_mfree(input, input_len); + input = NULL; + + extra_size = 0; + if (IW_IS_SET(priv_args[k].cmd)) + { + /* Size of set arguments */ + extra_size = get_priv_size(priv_args[k].set_args); + + /* Does it fits in iwr ? */ + if ((priv_args[k].set_args & IW_PRIV_SIZE_FIXED) && + ((extra_size + offset) <= IFNAMSIZ)) + extra_size = 0; + } else { + /* Size of get arguments */ + extra_size = get_priv_size(priv_args[k].get_args); + + /* Does it fits in iwr ? */ + if ((priv_args[k].get_args & IW_PRIV_SIZE_FIXED) && + (extra_size <= IFNAMSIZ)) + extra_size = 0; + } + + if (extra_size == 0) { + extra = (u8*)&wdata; + rtw_mfree(buffer, 4096); + buffer = NULL; + } else + extra = buffer; + + handler = priv[priv_args[k].cmd - SIOCIWFIRSTPRIV]; + err = handler(dev, NULL, &wdata, extra); + + /* If we have to get some data */ + if ((priv_args[k].get_args & IW_PRIV_TYPE_MASK) && + (priv_args[k].get_args & IW_PRIV_SIZE_MASK)) + { + int j; + int n = 0; /* number of args */ + u8 str[20] = {0}; + + /* Check where is the returned data */ + if ((priv_args[k].get_args & IW_PRIV_SIZE_FIXED) && + (get_priv_size(priv_args[k].get_args) <= IFNAMSIZ)) + n = priv_args[k].get_args & IW_PRIV_SIZE_MASK; + else + n = wdata.data.length; + + output = rtw_zmalloc(4096); + if (NULL == output) { + err = -ENOMEM; + goto exit; + } + + switch (priv_args[k].get_args & IW_PRIV_TYPE_MASK) + { + case IW_PRIV_TYPE_BYTE: + /* Display args */ + for (j = 0; j < n; j++) + { + sprintf(str, "%d ", extra[j]); + len = strlen(str); + output_len = strlen(output); + if ((output_len + len + 1) > 4096) { + err = -E2BIG; + goto exit; + } + _rtw_memcpy(output+output_len, str, len); + } + break; + + case IW_PRIV_TYPE_INT: + /* Display args */ + for (j = 0; j < n; j++) + { + sprintf(str, "%d ", ((__s32*)extra)[j]); + len = strlen(str); + output_len = strlen(output); + if ((output_len + len + 1) > 4096) { + err = -E2BIG; + goto exit; + } + _rtw_memcpy(output+output_len, str, len); + } + break; + + case IW_PRIV_TYPE_CHAR: + /* Display args */ + _rtw_memcpy(output, extra, n); + break; + + default: + DBG_8192C("%s: Not yet implemented...\n", __func__); + err = -1; + goto exit; + } + + output_len = strlen(output) + 1; + wrq_data->data.length = output_len; + if (copy_to_user(wrq_data->data.pointer, output, output_len)) { + err = -EFAULT; + goto exit; + } + } /* if args to set */ + else + { + wrq_data->data.length = 0; + } + +exit: + if (input) + rtw_mfree(input, input_len); + if (buffer) + rtw_mfree(buffer, 4096); + if (output) + rtw_mfree(output, 4096); + + return err; +} + +#ifdef CONFIG_COMPAT +static int rtw_ioctl_compat_wext_private(struct net_device *dev, struct ifreq *rq) +{ + struct compat_iw_point iwp_compat; + union iwreq_data wrq_data; + int err = 0; + DBG_871X("%s:...\n", __func__); + if (copy_from_user(&iwp_compat, rq->ifr_ifru.ifru_data, sizeof(struct compat_iw_point))) + return -EFAULT; + + wrq_data.data.pointer = compat_ptr(iwp_compat.pointer); + wrq_data.data.length = iwp_compat.length; + wrq_data.data.flags = iwp_compat.flags; + + err = _rtw_ioctl_wext_private(dev, &wrq_data); + + iwp_compat.pointer = ptr_to_compat(wrq_data.data.pointer); + iwp_compat.length = wrq_data.data.length; + iwp_compat.flags = wrq_data.data.flags; + if (copy_to_user(rq->ifr_ifru.ifru_data, &iwp_compat, sizeof(struct compat_iw_point))) + return -EFAULT; + + return err; +} +#endif // CONFIG_COMPAT + +static int rtw_ioctl_standard_wext_private(struct net_device *dev, struct ifreq *rq) +{ + struct iw_point *iwp; + struct ifreq ifrq; + union iwreq_data wrq_data; + int err = 0; + iwp = &wrq_data.data; + DBG_871X("%s:...\n", __func__); + if (copy_from_user(iwp, rq->ifr_ifru.ifru_data, sizeof(struct iw_point))) + return -EFAULT; + + err = _rtw_ioctl_wext_private(dev, &wrq_data); + + if (copy_to_user(rq->ifr_ifru.ifru_data, iwp, sizeof(struct iw_point))) + return -EFAULT; + + return err; +} + +int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) +{ + struct iwreq *wrq = (struct iwreq *)rq; + int ret=0; + + switch (cmd) + { + case RTL_IOCTL_WPA_SUPPLICANT: + ret = wpa_supplicant_ioctl(dev, &wrq->u.data); + break; +#ifdef CONFIG_AP_MODE + case RTL_IOCTL_HOSTAPD: + ret = rtw_hostapd_ioctl(dev, &wrq->u.data); + break; +#ifdef CONFIG_WIRELESS_EXT + case SIOCSIWMODE: + ret = rtw_wx_set_mode(dev, NULL, &wrq->u, NULL); + break; +#endif +#endif // CONFIG_AP_MODE + default: + ret = -EOPNOTSUPP; + break; + } + + return ret; +} + + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/ioctl_mp.c b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/ioctl_mp.c new file mode 100644 index 000000000..661d472d5 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/ioctl_mp.c @@ -0,0 +1,2355 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#if defined(CONFIG_MP_INCLUDED) + +#include +#include +#include +#include "../../hal/phydm/phydm_precomp.h" + + +#if defined(CONFIG_RTL8723B) +#include +#endif + +/* + * Input Format: %s,%d,%d + * %s is width, could be + * "b" for 1 byte + * "w" for WORD (2 bytes) + * "dw" for DWORD (4 bytes) + * 1st %d is address(offset) + * 2st %d is data to write + */ +int rtw_mp_write_reg(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + char *pch, *pnext, *ptmp; + char *width_str; + char width, buf[5]; + u32 addr, data; + int ret; + PADAPTER padapter = rtw_netdev_priv(dev); + char* input = kmalloc(wrqu->length, GFP_KERNEL); + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) + return -EFAULT; + + _rtw_memset(extra, 0, wrqu->length); + + pch = input; + + pnext = strpbrk(pch, " ,.-"); + if (pnext == NULL) + return -EINVAL; + *pnext = 0; + width_str = pch; + + pch = pnext + 1; + pnext = strpbrk(pch, " ,.-"); + if (pnext == NULL) + return -EINVAL; + *pnext = 0; + /*addr = simple_strtoul(pch, &ptmp, 16); + _rtw_memset(buf, '\0', sizeof(buf)); + _rtw_memcpy(buf, pch, pnext-pch); + ret = kstrtoul(buf, 16, &addr);*/ + ret = sscanf(pch, "%x", &addr); + if (addr > 0x3FFF) + return -EINVAL; + + pch = pnext + 1; + pnext = strpbrk(pch, " ,.-"); + if ((pch - input) >= wrqu->length) + return -EINVAL; + /*data = simple_strtoul(pch, &ptmp, 16);*/ + ret = sscanf(pch, "%x", &data); + DBG_871X("data=%x,addr=%x\n", (u32)data, (u32)addr); + ret = 0; + width = width_str[0]; + switch (width) { + case 'b': + /* 1 byte*/ + if (data > 0xFF) { + ret = -EINVAL; + break; + } + rtw_write8(padapter, addr, data); + break; + case 'w': + /* 2 bytes*/ + if (data > 0xFFFF) { + ret = -EINVAL; + break; + } + rtw_write16(padapter, addr, data); + break; + case 'd': + /* 4 bytes*/ + rtw_write32(padapter, addr, data); + break; + default: + ret = -EINVAL; + break; + } + + kfree(input); + return ret; +} + + +/* + * Input Format: %s,%d + * %s is width, could be + * "b" for 1 byte + * "w" for WORD (2 bytes) + * "dw" for DWORD (4 bytes) + * %d is address(offset) + * + * Return: + * %d for data readed + */ +int rtw_mp_read_reg(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + char* input = kmalloc(wrqu->length, GFP_KERNEL); + char *pch, *pnext, *ptmp; + char *width_str; + char width; + char data[20], tmp[20], buf[3]; + u32 addr = 0, strtout = 0; + u32 i = 0, j = 0, ret = 0, data32 = 0; + PADAPTER padapter = rtw_netdev_priv(dev); + + + if (wrqu->length > 128) + return -EFAULT; + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) + return -EFAULT; + + _rtw_memset(extra, 0, wrqu->length); + _rtw_memset(data, '\0', sizeof(data)); + _rtw_memset(tmp, '\0', sizeof(tmp)); + pch = input; + pnext = strpbrk(pch, " ,.-"); + if (pnext == NULL) + return -EINVAL; + *pnext = 0; + width_str = pch; + + pch = pnext + 1; + + ret = sscanf(pch, "%x", &addr); + if (addr > 0x3FFF) + return -EINVAL; + + ret = 0; + width = width_str[0]; + + switch (width) { + case 'b': + data32 = rtw_read8(padapter, addr); + DBG_871X("%x\n", data32); + sprintf(extra, "%d", data32); + wrqu->length = strlen(extra); + break; + case 'w': + /* 2 bytes*/ + sprintf(data, "%04x\n", rtw_read16(padapter, addr)); + + for (i = 0 ; i <= strlen(data) ; i++) { + if (i % 2 == 0) { + tmp[j] = ' '; + j++; + } + if (data[i] != '\0') + tmp[j] = data[i]; + + j++; + } + pch = tmp; + DBG_871X("pch=%s", pch); + + while (*pch != '\0') { + pnext = strpbrk(pch, " "); + if (!pnext || ((pnext - tmp) > 4)) + break; + + pnext++; + if (*pnext != '\0') { + /*strtout = simple_strtoul(pnext , &ptmp, 16);*/ + ret = sscanf(pnext, "%x", &strtout); + sprintf(extra, "%s %d" , extra , strtout); + } else + break; + pch = pnext; + } + wrqu->length = strlen(extra); + break; + case 'd': + /* 4 bytes */ + sprintf(data, "%08x", rtw_read32(padapter, addr)); + /*add read data format blank*/ + for (i = 0 ; i <= strlen(data) ; i++) { + if (i % 2 == 0) { + tmp[j] = ' '; + j++; + } + if (data[i] != '\0') + tmp[j] = data[i]; + + j++; + } + pch = tmp; + DBG_871X("pch=%s", pch); + + while (*pch != '\0') { + pnext = strpbrk(pch, " "); + if (!pnext) + break; + + pnext++; + if (*pnext != '\0') { + ret = sscanf(pnext, "%x", &strtout); + sprintf(extra, "%s %d" , extra , strtout); + } else + break; + pch = pnext; + } + wrqu->length = strlen(extra); + break; + + default: + wrqu->length = 0; + ret = -EINVAL; + break; + } + + kfree(input); + return ret; +} + + +/* + * Input Format: %d,%x,%x + * %d is RF path, should be smaller than MAX_RF_PATH_NUMS + * 1st %x is address(offset) + * 2st %x is data to write + */ +int rtw_mp_write_rf(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + + u32 path, addr, data; + int ret; + PADAPTER padapter = rtw_netdev_priv(dev); + char* input = kmalloc(wrqu->length, GFP_KERNEL); + + + _rtw_memset(input, 0, wrqu->length); + if (copy_from_user(input, wrqu->pointer, wrqu->length)) + return -EFAULT; + + + ret = sscanf(input, "%d,%x,%x", &path, &addr, &data); + if (ret < 3) + return -EINVAL; + + if (path >= GET_HAL_RFPATH_NUM(padapter)) + return -EINVAL; + if (addr > 0xFF) + return -EINVAL; + if (data > 0xFFFFF) + return -EINVAL; + + _rtw_memset(extra, 0, wrqu->length); + + write_rfreg(padapter, path, addr, data); + + sprintf(extra, "write_rf completed\n"); + wrqu->length = strlen(extra); + + kfree(input); + return 0; +} + + +/* + * Input Format: %d,%x + * %d is RF path, should be smaller than MAX_RF_PATH_NUMS + * %x is address(offset) + * + * Return: + * %d for data readed + */ +int rtw_mp_read_rf(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + char* input = kmalloc(wrqu->length, GFP_KERNEL); + char *pch, *pnext, *ptmp; + char data[20], tmp[20], buf[3]; + u32 path, addr, strtou; + u32 ret, i = 0 , j = 0; + PADAPTER padapter = rtw_netdev_priv(dev); + + if (wrqu->length > 128) + return -EFAULT; + _rtw_memset(input, 0, wrqu->length); + if (copy_from_user(input, wrqu->pointer, wrqu->length)) + return -EFAULT; + + ret = sscanf(input, "%d,%x", &path, &addr); + if (ret < 2) + return -EINVAL; + + if (path >= GET_HAL_RFPATH_NUM(padapter)) + return -EINVAL; + if (addr > 0xFF) + return -EINVAL; + + _rtw_memset(extra, 0, wrqu->length); + + sprintf(data, "%08x", read_rfreg(padapter, path, addr)); + /*add read data format blank*/ + for (i = 0 ; i <= strlen(data) ; i++) { + if (i % 2 == 0) { + tmp[j] = ' '; + j++; + } + tmp[j] = data[i]; + j++; + } + pch = tmp; + DBG_871X("pch=%s", pch); + + while (*pch != '\0') { + pnext = strpbrk(pch, " "); + if (!pnext) + break; + pnext++; + if (*pnext != '\0') { + /*strtou =simple_strtoul(pnext , &ptmp, 16);*/ + ret = sscanf(pnext, "%x", &strtou); + sprintf(extra, "%s %d" , extra , strtou); + } else + break; + pch = pnext; + } + wrqu->length = strlen(extra); + + kfree(input); + return 0; +} + + +int rtw_mp_start(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + int ret = 0; + u8 val8; + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct hal_ops *pHalFunc = &padapter->HalFunc; + + rtw_pm_set_ips(padapter, IPS_NONE); + LeaveAllPowerSaveMode(padapter); + + if (rtw_mp_cmd(padapter, MP_START, RTW_CMDF_WAIT_ACK) != _SUCCESS) + ret = -EPERM; + + + _rtw_memset(extra, 0, wrqu->length); + sprintf(extra, "mp_start %s\n", ret == 0 ? "ok" : "fail"); + wrqu->length = strlen(extra); + + return ret; +} + + + +int rtw_mp_stop(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + int ret = 0; + PADAPTER padapter = rtw_netdev_priv(dev); + struct hal_ops *pHalFunc = &padapter->HalFunc; + + if (rtw_mp_cmd(padapter, MP_STOP, RTW_CMDF_WAIT_ACK) != _SUCCESS) + ret = -EPERM; + + _rtw_memset(extra, 0, wrqu->length); + sprintf(extra, "mp_stop %s\n", ret == 0 ? "ok" : "fail"); + wrqu->length = strlen(extra); + + return ret; +} + + +int rtw_mp_rate(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + u32 rate = MPT_RATE_1M; + u8* input = kmalloc(wrqu->length, GFP_KERNEL); + PADAPTER padapter = rtw_netdev_priv(dev); + PMPT_CONTEXT pMptCtx = &(padapter->mppriv.MptCtx); + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) + return -EFAULT; + + rate = rtw_mpRateParseFunc(padapter, input); + padapter->mppriv.rateidx = rate; + + if (rate == 0 && strcmp(input, "1M") != 0) { + rate = rtw_atoi(input); + padapter->mppriv.rateidx = MRateToHwRate(rate); + /*if (rate <= 0x7f) + rate = wifirate2_ratetbl_inx((u8)rate); + else if (rate < 0xC8) + rate = (rate - 0x79 + MPT_RATE_MCS0); + HT rate 0x80(MCS0) ~ 0x8F(MCS15) ~ 0x9F(MCS31) 128~159 + VHT1SS~2SS rate 0xA0 (VHT1SS_MCS0 44) ~ 0xB3 (VHT2SS_MCS9 #63) 160~179 + VHT rate 0xB4 (VHT3SS_MCS0 64) ~ 0xC7 (VHT2SS_MCS9 #83) 180~199 + else + VHT rate 0x90(VHT1SS_MCS0) ~ 0x99(VHT1SS_MCS9) 144~153 + rate =(rate - MPT_RATE_VHT1SS_MCS0); + */ + } + _rtw_memset(extra, 0, wrqu->length); + + sprintf(extra, "Set data rate to %s index %d" , input, padapter->mppriv.rateidx); + DBG_871X("%s: %s rate index=%d\n", __func__, input, padapter->mppriv.rateidx); + + if (padapter->mppriv.rateidx >= DESC_RATEVHTSS4MCS9) + return -EINVAL; + + pMptCtx->MptRateIndex = HwRateToMPTRate(padapter->mppriv.rateidx); + SetDataRate(padapter); + + wrqu->length = strlen(extra); + kfree(input); + return 0; +} + + +int rtw_mp_channel(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8* input = kmalloc(wrqu->length, GFP_KERNEL); + u32 channel = 1; + int cur_ch_offset; + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) + return -EFAULT; + + channel = rtw_atoi(input); + /*DBG_871X("%s: channel=%d\n", __func__, channel);*/ + _rtw_memset(extra, 0, wrqu->length); + sprintf(extra, "Change channel %d to channel %d", padapter->mppriv.channel , channel); + padapter->mppriv.channel = channel; + SetChannel(padapter); + pHalData->CurrentChannel = channel; + + wrqu->length = strlen(extra); + kfree(input); + return 0; +} + + +int rtw_mp_bandwidth(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + u32 bandwidth = 0, sg = 0; + int cur_ch_offset; + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8* input = kmalloc(wrqu->length, GFP_KERNEL); + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) + return -EFAULT; + + if (sscanf(input, "40M=%d,shortGI=%d", &bandwidth, &sg) > 0) + DBG_871X("%s: bw=%d sg=%d\n", __func__, bandwidth , sg); + + if (bandwidth == 1) + bandwidth = CHANNEL_WIDTH_40; + else if (bandwidth == 2) + bandwidth = CHANNEL_WIDTH_80; + + padapter->mppriv.bandwidth = (u8)bandwidth; + padapter->mppriv.preamble = sg; + _rtw_memset(extra, 0, wrqu->length); + sprintf(extra, "Change BW %d to BW %d\n", pHalData->CurrentChannelBW , bandwidth); + + SetBandwidth(padapter); + pHalData->CurrentChannelBW = bandwidth; + /*cur_ch_offset = rtw_get_offset_by_ch(padapter->mppriv.channel);*/ + /*set_channel_bwmode(padapter, padapter->mppriv.channel, cur_ch_offset, bandwidth);*/ + wrqu->length = strlen(extra); + + kfree(input); + return 0; +} + + +int rtw_mp_txpower_index(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + char* input = kmalloc(wrqu->length, GFP_KERNEL); + u32 rfpath; + u32 txpower_inx; + + if (wrqu->length > 128) + return -EFAULT; + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) + return -EFAULT; + + rfpath = rtw_atoi(input); + txpower_inx = mpt_ProQueryCalTxPower(padapter, rfpath); + sprintf(extra, " %d", txpower_inx); + wrqu->length = strlen(extra); + + kfree(input); + return 0; +} + + +int rtw_mp_txpower(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + u32 idx_a = 0, idx_b = 0, idx_c = 0, idx_d = 0, status = 0; + int MsetPower = 1; + u8* input = kmalloc(wrqu->length, GFP_KERNEL); + + PADAPTER padapter = rtw_netdev_priv(dev); + PMPT_CONTEXT pMptCtx = &(padapter->mppriv.MptCtx); + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) + return -EFAULT; + + MsetPower = strncmp(input, "off", 3); + if (MsetPower == 0) { + padapter->mppriv.bSetTxPower = 0; + sprintf(extra, "MP Set power off"); + } else { + if (sscanf(input, "patha=%d,pathb=%d,pathc=%d,pathd=%d", &idx_a, &idx_b, &idx_c, &idx_d) < 3) + DBG_871X("Invalid format on line %s ,patha=%d,pathb=%d,pathc=%d,pathd=%d\n", input , idx_a , idx_b , idx_c , idx_d); + + sprintf(extra, "Set power level path_A:%d path_B:%d path_C:%d path_D:%d", idx_a , idx_b , idx_c , idx_d); + padapter->mppriv.txpoweridx = (u8)idx_a; + + pMptCtx->TxPwrLevel[ODM_RF_PATH_A] = (u8)idx_a; + pMptCtx->TxPwrLevel[ODM_RF_PATH_B] = (u8)idx_b; + pMptCtx->TxPwrLevel[ODM_RF_PATH_C] = (u8)idx_c; + pMptCtx->TxPwrLevel[ODM_RF_PATH_D] = (u8)idx_d; + padapter->mppriv.bSetTxPower = 1; + + SetTxPower(padapter); + } + + wrqu->length = strlen(extra); + kfree(input); + return 0; +} + + +int rtw_mp_ant_tx(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + u8 i; + u8* input = kmalloc(wrqu->length, GFP_KERNEL); + u16 antenna = 0; + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) + return -EFAULT; + + sprintf(extra, "switch Tx antenna to %s", input); + + for (i = 0; i < strlen(input); i++) { + switch (input[i]) { + case 'a': + antenna |= ANTENNA_A; + break; + case 'b': + antenna |= ANTENNA_B; + break; + case 'c': + antenna |= ANTENNA_C; + break; + case 'd': + antenna |= ANTENNA_D; + break; + } + } + /*antenna |= BIT(extra[i]-'a');*/ + DBG_871X("%s: antenna=0x%x\n", __func__, antenna); + padapter->mppriv.antenna_tx = antenna; + padapter->mppriv.antenna_rx = antenna; + /*DBG_871X("%s:mppriv.antenna_rx=%d\n", __func__, padapter->mppriv.antenna_tx);*/ + pHalData->AntennaTxPath = antenna; + + SetAntenna(padapter); + + wrqu->length = strlen(extra); + kfree(input); + return 0; +} + + +int rtw_mp_ant_rx(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + u8 i; + u16 antenna = 0; + u8* input = kmalloc(wrqu->length, GFP_KERNEL); + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) + return -EFAULT; + /*DBG_871X("%s: input=%s\n", __func__, input);*/ + _rtw_memset(extra, 0, wrqu->length); + + sprintf(extra, "switch Rx antenna to %s", input); + + for (i = 0; i < strlen(input); i++) { + switch (input[i]) { + case 'a': + antenna |= ANTENNA_A; + break; + case 'b': + antenna |= ANTENNA_B; + break; + case 'c': + antenna |= ANTENNA_C; + break; + case 'd': + antenna |= ANTENNA_D; + break; + } + } + + DBG_871X("%s: antenna=0x%x\n", __func__, antenna); + padapter->mppriv.antenna_tx = antenna; + padapter->mppriv.antenna_rx = antenna; + pHalData->AntennaRxPath = antenna; + /*DBG_871X("%s:mppriv.antenna_rx=%d\n", __func__, padapter->mppriv.antenna_rx);*/ + SetAntenna(padapter); + wrqu->length = strlen(extra); + + kfree(input); + return 0; +} + + +int rtw_set_ctx_destAddr(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + int jj, kk = 0; + + struct pkt_attrib *pattrib; + struct mp_priv *pmp_priv; + PADAPTER padapter = rtw_netdev_priv(dev); + + pmp_priv = &padapter->mppriv; + pattrib = &pmp_priv->tx.attrib; + + if (strlen(extra) < 5) + return _FAIL; + + DBG_871X("%s: in=%s\n", __func__, extra); + for (jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3) + pattrib->dst[jj] = key_2char2num(extra[kk], extra[kk + 1]); + + DBG_871X("pattrib->dst:%x %x %x %x %x %x\n", pattrib->dst[0], pattrib->dst[1], pattrib->dst[2], pattrib->dst[3], pattrib->dst[4], pattrib->dst[5]); + return 0; +} + + + +int rtw_mp_ctx(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + u32 pkTx = 1; + int countPkTx = 1, cotuTx = 1, CarrSprTx = 1, scTx = 1, sgleTx = 1, stop = 1; + u32 bStartTest = 1; + u32 count = 0, pktinterval = 0, pktlen = 0; + u8 status; + struct mp_priv *pmp_priv; + struct pkt_attrib *pattrib; + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + pmp_priv = &padapter->mppriv; + pattrib = &pmp_priv->tx.attrib; + + if (copy_from_user(extra, wrqu->pointer, wrqu->length)) + return -EFAULT; + + DBG_871X("%s: in=%s\n", __func__, extra); +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->adapter_type == SECONDARY_ADAPTER) { + sprintf(extra, "Error: MP mode can't support Virtual Adapter, Please to use main Adapter.\n"); + wrqu->length = strlen(extra); + return 0; + } +#endif + countPkTx = strncmp(extra, "count=", 5); /* strncmp TRUE is 0*/ + cotuTx = strncmp(extra, "background", 20); + CarrSprTx = strncmp(extra, "background,cs", 20); + scTx = strncmp(extra, "background,sc", 20); + sgleTx = strncmp(extra, "background,stone", 20); + pkTx = strncmp(extra, "background,pkt", 20); + stop = strncmp(extra, "stop", 4); + if (sscanf(extra, "count=%d,pkt", &count) > 0) + DBG_871X("count= %d\n", count); + if (sscanf(extra, "pktinterval=%d", &pktinterval) > 0) + DBG_871X("pktinterval= %d\n", pktinterval); + + if (sscanf(extra, "pktlen=%d", &pktlen) > 0) + DBG_871X("pktlen= %d\n", pktlen); + + if (_rtw_memcmp(extra, "destmac=", 8)) { + wrqu->length -= 8; + rtw_set_ctx_destAddr(dev, info, wrqu, &extra[8]); + sprintf(extra, "Set dest mac OK !\n"); + return 0; + } + + /*DBG_871X("%s: count=%d countPkTx=%d cotuTx=%d CarrSprTx=%d scTx=%d sgleTx=%d pkTx=%d stop=%d\n", __func__, count, countPkTx, cotuTx, CarrSprTx, pkTx, sgleTx, scTx, stop);*/ + _rtw_memset(extra, '\0', strlen(extra)); + + if (pktinterval != 0) { + sprintf(extra, "Pkt Interval = %d", pktinterval); + padapter->mppriv.pktInterval = pktinterval; + wrqu->length = strlen(extra); + return 0; + } + if (pktlen != 0) { + sprintf(extra, "Pkt len = %d", pktlen); + pattrib->pktlen = pktlen; + wrqu->length = strlen(extra); + return 0; + } + if (stop == 0) { + bStartTest = 0; /* To set Stop*/ + pmp_priv->tx.stop = 1; + sprintf(extra, "Stop continuous Tx"); + ODM_Write_DIG(&pHalData->odmpriv, 0x20); + } else { + bStartTest = 1; + ODM_Write_DIG(&pHalData->odmpriv, 0x7f); + if (pmp_priv->mode != MP_ON) { + if (pmp_priv->tx.stop != 1) { + DBG_871X("%s: MP_MODE != ON %d\n", __func__, pmp_priv->mode); + return -EFAULT; + } + } + } + + pmp_priv->tx.count = count; + + if (pkTx == 0 || countPkTx == 0) + pmp_priv->mode = MP_PACKET_TX; + if (sgleTx == 0) + pmp_priv->mode = MP_SINGLE_TONE_TX; + if (cotuTx == 0) + pmp_priv->mode = MP_CONTINUOUS_TX; + if (CarrSprTx == 0) + pmp_priv->mode = MP_CARRIER_SUPPRISSION_TX; + if (scTx == 0) + pmp_priv->mode = MP_SINGLE_CARRIER_TX; + + status = rtw_mp_pretx_proc(padapter, bStartTest, extra); + + wrqu->length = strlen(extra); + return status; +} + + + +int rtw_mp_disable_bt_coexist(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + PADAPTER padapter = (PADAPTER)rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct hal_ops *pHalFunc = &padapter->HalFunc; + + u8* input = kmalloc(wrqu->data.length, GFP_KERNEL); + u32 bt_coexist; + + if (copy_from_user(input, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; + + bt_coexist = rtw_atoi(input); + + if (bt_coexist == 0) { + RT_TRACE(_module_mp_, _drv_info_, + ("Set OID_RT_SET_DISABLE_BT_COEXIST: disable BT_COEXIST\n")); + DBG_871X("Set OID_RT_SET_DISABLE_BT_COEXIST: disable BT_COEXIST\n"); +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_HaltNotify(padapter); + rtw_btcoex_SetManualControl(padapter, _TRUE); + /* Force to switch Antenna to WiFi*/ + rtw_write16(padapter, 0x870, 0x300); + rtw_write16(padapter, 0x860, 0x110); +#endif + /* CONFIG_BT_COEXIST */ + } else { + RT_TRACE(_module_mp_, _drv_info_, + ("Set OID_RT_SET_DISABLE_BT_COEXIST: enable BT_COEXIST\n")); +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_SetManualControl(padapter, _FALSE); +#endif + } + + kfree(input); + return 0; +} + + +int rtw_mp_arx(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + int bStartRx = 0, bStopRx = 0, bQueryPhy = 0, bQueryMac = 0, bSetBssid = 0; + int bmac_filter = 0, bfilter_init = 0, bmon = 0, bSmpCfg = 0, bloopbk = 0; + u8* input = kmalloc(wrqu->length, GFP_KERNEL); + char *pch, *ptmp, *token, *tmp[2] = {0x00, 0x00}; + u32 i = 0, ii = 0, jj = 0, kk = 0, cnts = 0, ret; + PADAPTER padapter = rtw_netdev_priv(dev); + struct mp_priv *pmppriv = &padapter->mppriv; + struct dbg_rx_counter rx_counter; + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) + return -EFAULT; + + DBG_871X("%s: %s\n", __func__, input); +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->adapter_type == SECONDARY_ADAPTER) { + sprintf(extra, "Error: MP mode can't support Virtual Adapter, Please to use main Adapter.\n"); + wrqu->length = strlen(extra); + return 0; + } +#endif + bStartRx = (strncmp(input, "start", 5) == 0) ? 1 : 0; /* strncmp TRUE is 0*/ + bStopRx = (strncmp(input, "stop", 5) == 0) ? 1 : 0; /* strncmp TRUE is 0*/ + bQueryPhy = (strncmp(input, "phy", 3) == 0) ? 1 : 0; /* strncmp TRUE is 0*/ + bQueryMac = (strncmp(input, "mac", 3) == 0) ? 1 : 0; /* strncmp TRUE is 0*/ + bSetBssid = (strncmp(input, "setbssid=", 8) == 0) ? 1 : 0; /* strncmp TRUE is 0*/ + /*bfilter_init = (strncmp(input, "filter_init",11)==0)?1:0;*/ + bmac_filter = (strncmp(input, "accept_mac", 10) == 0) ? 1 : 0; + bmon = (strncmp(input, "mon=", 4) == 0) ? 1 : 0; + bSmpCfg = (strncmp(input , "smpcfg=" , 7) == 0) ? 1 : 0; + pmppriv->bloopback = (strncmp(input, "loopbk", 6) == 0) ? 1 : 0; /* strncmp TRUE is 0*/ + + if (bSetBssid == 1) { + pch = input; + while ((token = strsep(&pch, "=")) != NULL) { + if (i > 1) + break; + tmp[i] = token; + i++; + } + if ((tmp[0] != NULL) && (tmp[1] != NULL)) { + cnts = strlen(tmp[1]) / 2; + if (cnts < 1) + return -EFAULT; + DBG_871X("%s: cnts=%d\n", __func__, cnts); + DBG_871X("%s: data=%s\n", __func__, tmp[1]); + for (jj = 0, kk = 0; jj < cnts ; jj++, kk += 2) { + pmppriv->network_macaddr[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]); + DBG_871X("network_macaddr[%d]=%x\n", jj, pmppriv->network_macaddr[jj]); + } + } else + return -EFAULT; + + pmppriv->bSetRxBssid = _TRUE; + } + + if (bmac_filter) { + pmppriv->bmac_filter = bmac_filter; + pch = input; + while ((token = strsep(&pch, "=")) != NULL) { + if (i > 1) + break; + tmp[i] = token; + i++; + } + if ((tmp[0] != NULL) && (tmp[1] != NULL)) { + cnts = strlen(tmp[1]) / 2; + if (cnts < 1) + return -EFAULT; + DBG_871X("%s: cnts=%d\n", __func__, cnts); + DBG_871X("%s: data=%s\n", __func__, tmp[1]); + for (jj = 0, kk = 0; jj < cnts ; jj++, kk += 2) { + pmppriv->mac_filter[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]); + DBG_871X("%s mac_filter[%d]=%x\n", __func__, jj, pmppriv->mac_filter[jj]); + } + } else + return -EFAULT; + + } + + if (bStartRx) { + sprintf(extra, "start"); + SetPacketRx(padapter, bStartRx, _FALSE); + } else if (bStopRx) { + SetPacketRx(padapter, bStartRx, _FALSE); + pmppriv->bmac_filter = _FALSE; + sprintf(extra, "Received packet OK:%d CRC error:%d ,Filter out:%d", padapter->mppriv.rx_pktcount, padapter->mppriv.rx_crcerrpktcount, padapter->mppriv.rx_pktcount_filter_out); + } else if (bQueryPhy) { + _rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter)); + rtw_dump_phy_rx_counters(padapter, &rx_counter); + + DBG_871X("%s: OFDM_FA =%d\n", __func__, rx_counter.rx_ofdm_fa); + DBG_871X("%s: CCK_FA =%d\n", __func__, rx_counter.rx_cck_fa); + sprintf(extra, "Phy Received packet OK:%d CRC error:%d FA Counter: %d", rx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error, rx_counter.rx_cck_fa + rx_counter.rx_ofdm_fa); + + + } else if (bQueryMac) { + _rtw_memset(&rx_counter, 0, sizeof(struct dbg_rx_counter)); + rtw_dump_mac_rx_counters(padapter, &rx_counter); + sprintf(extra, "Mac Received packet OK: %d , CRC error: %d , Drop Packets: %d\n", + rx_counter.rx_pkt_ok, rx_counter.rx_pkt_crc_error, rx_counter.rx_pkt_drop); + + } + + if (bmon == 1) { + ret = sscanf(input, "mon=%d", &bmon); + + if (bmon == 1) { + pmppriv->rx_bindicatePkt = _TRUE; + sprintf(extra, "Indicating Receive Packet to network start\n"); + } else { + pmppriv->rx_bindicatePkt = _FALSE; + sprintf(extra, "Indicating Receive Packet to network Stop\n"); + } + } + if (bSmpCfg == 1) { + ret = sscanf(input, "smpcfg=%d", &bSmpCfg); + + if (bSmpCfg == 1) { + pmppriv->bRTWSmbCfg = _TRUE; + sprintf(extra , "Indicate By Simple Config Format\n"); + SetPacketRx(padapter, _TRUE, _TRUE); + } else { + pmppriv->bRTWSmbCfg = _FALSE; + sprintf(extra , "Indicate By Normal Format\n"); + SetPacketRx(padapter, _TRUE, _FALSE); + } + } + + if (pmppriv->bloopback == _TRUE) { + sprintf(extra , "Enter MAC LoopBack mode\n"); + _rtw_write32(padapter, 0x100, 0xB0106FF); + DBG_871X("0x100 :0x%x" , _rtw_read32(padapter, 0x100)); + _rtw_write16(padapter, 0x608, 0x30c); + DBG_871X("0x100 :0x%x" , _rtw_read32(padapter, 0x608)); + } + + wrqu->length = strlen(extra) + 1; + + kfree(input); + return 0; +} + + +int rtw_mp_trx_query(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + u32 txok, txfail, rxok, rxfail, rxfilterout; + PADAPTER padapter = rtw_netdev_priv(dev); + PMPT_CONTEXT pMptCtx = &(padapter->mppriv.MptCtx); + RT_PMAC_TX_INFO PMacTxInfo = pMptCtx->PMacTxInfo; + + if (PMacTxInfo.bEnPMacTx == TRUE) + txok = hal_mpt_query_phytxok(padapter); + else + txok = padapter->mppriv.tx.sended; + + txfail = 0; + rxok = padapter->mppriv.rx_pktcount; + rxfail = padapter->mppriv.rx_crcerrpktcount; + rxfilterout = padapter->mppriv.rx_pktcount_filter_out; + + _rtw_memset(extra, '\0', 128); + + sprintf(extra, "Tx OK:%d, Tx Fail:%d, Rx OK:%d, CRC error:%d ,Rx Filter out:%d\n", txok, txfail, rxok, rxfail, rxfilterout); + + wrqu->length = strlen(extra) + 1; + + return 0; +} + + +int rtw_mp_pwrtrk(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + u8 enable; + u32 thermal; + s32 ret; + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + u8* input = kmalloc(wrqu->length, GFP_KERNEL); + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) + return -EFAULT; + + _rtw_memset(extra, 0, wrqu->length); + + enable = 1; + if (wrqu->length > 1) { + /* not empty string*/ + if (strncmp(input, "stop", 4) == 0) { + enable = 0; + sprintf(extra, "mp tx power tracking stop"); + } else if (sscanf(input, "ther=%d", &thermal) == 1) { + ret = SetThermalMeter(padapter, (u8)thermal); + if (ret == _FAIL) + return -EPERM; + sprintf(extra, "mp tx power tracking start,target value=%d ok", thermal); + } else + return -EINVAL; + } + + ret = SetPowerTracking(padapter, enable); + if (ret == _FAIL) + return -EPERM; + + wrqu->length = strlen(extra); + + kfree(input); + return 0; +} + + + +int rtw_mp_psd(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + u8* input = kmalloc(wrqu->length, GFP_KERNEL); + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) + return -EFAULT; + + strcpy(extra, input); + + wrqu->length = mp_query_psd(padapter, extra); + + kfree(input); + return 0; +} + + +int rtw_mp_thermal(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + u8 val; + int bwrite = 1; + +#ifdef CONFIG_RTL8188E + u16 addr = EEPROM_THERMAL_METER_88E; +#endif +#if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) + u16 addr = EEPROM_THERMAL_METER_8812; +#endif +#ifdef CONFIG_RTL8192E + u16 addr = EEPROM_THERMAL_METER_8192E; +#endif +#ifdef CONFIG_RTL8723B + u16 addr = EEPROM_THERMAL_METER_8723B; +#endif +#ifdef CONFIG_RTL8703B + u16 addr = EEPROM_THERMAL_METER_8703B; +#endif +#ifdef CONFIG_RTL8188F + u16 addr = EEPROM_THERMAL_METER_8188F; +#endif + u16 cnt = 1; + u16 max_available_size = 0; + PADAPTER padapter = rtw_netdev_priv(dev); + + if (copy_from_user(extra, wrqu->pointer, wrqu->length)) + return -EFAULT; + + bwrite = strncmp(extra, "write", 6);/* strncmp TRUE is 0*/ + + GetThermalMeter(padapter, &val); + + if (bwrite == 0) { + /*DBG_871X("to write val:%d",val);*/ + EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE); + if (2 > max_available_size) { + DBG_871X("no available efuse!\n"); + return -EFAULT; + } + if (rtw_efuse_map_write(padapter, addr, cnt, &val) == _FAIL) { + DBG_871X("rtw_efuse_map_write error\n"); + return -EFAULT; + } + sprintf(extra, " efuse write ok :%d", val); + } else + sprintf(extra, "%d", val); + wrqu->length = strlen(extra); + + return 0; +} + + + +int rtw_mp_reset_stats(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + struct mp_priv *pmp_priv; + struct pkt_attrib *pattrib; + PADAPTER padapter = rtw_netdev_priv(dev); + + pmp_priv = &padapter->mppriv; + + pmp_priv->tx.sended = 0; + pmp_priv->tx_pktcount = 0; + pmp_priv->rx_pktcount = 0; + pmp_priv->rx_pktcount_filter_out = 0; + pmp_priv->rx_crcerrpktcount = 0; + + rtw_reset_phy_rx_counters(padapter); + rtw_reset_mac_rx_counters(padapter); + + _rtw_memset(extra, 0, wrqu->length); + sprintf(extra, "mp_reset_stats ok\n"); + wrqu->length = strlen(extra); + + return 0; +} + + +int rtw_mp_dump(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + struct mp_priv *pmp_priv; + struct pkt_attrib *pattrib; + u32 value; + u8* input = kmalloc(wrqu->length, GFP_KERNEL); + u8 rf_type, path_nums = 0; + u32 i, j = 1, path; + PADAPTER padapter = rtw_netdev_priv(dev); + + pmp_priv = &padapter->mppriv; + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) + return -EFAULT; + + if (strncmp(input, "all", 4) == 0) { + mac_reg_dump(RTW_DBGDUMP, padapter); + bb_reg_dump(RTW_DBGDUMP, padapter); + rf_reg_dump(RTW_DBGDUMP, padapter); + } + kfree(input); + return 0; +} + + +int rtw_mp_phypara(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + char* input = kmalloc(wrqu->length, GFP_KERNEL); + u32 valxcap, ret; + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) + return -EFAULT; + + DBG_871X("%s:iwpriv in=%s\n", __func__, input); + + ret = sscanf(input, "xcap=%d", &valxcap); + + pHalData->CrystalCap = (u8)valxcap; + hal_set_crystal_cap(padapter , valxcap); + + sprintf(extra, "Set xcap=%d", valxcap); + wrqu->length = strlen(extra) + 1; + + kfree(input); + return 0; + +} + + +int rtw_mp_SetRFPath(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + char* input = kmalloc(wrqu->length, GFP_KERNEL); + int bMain = 1, bTurnoff = 1; + + DBG_871X("%s:iwpriv in=%s\n", __func__, input); + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) + return -EFAULT; + + bMain = strncmp(input, "1", 2); /* strncmp TRUE is 0*/ + bTurnoff = strncmp(input, "0", 3); /* strncmp TRUE is 0*/ + + _rtw_memset(extra, 0, wrqu->length); + + if (bMain == 0) { + MP_PHY_SetRFPathSwitch(padapter, _TRUE); + DBG_871X("%s:PHY_SetRFPathSwitch=TRUE\n", __func__); + sprintf(extra, "mp_setrfpath Main\n"); + } else if (bTurnoff == 0) { + MP_PHY_SetRFPathSwitch(padapter, _FALSE); + DBG_871X("%s:PHY_SetRFPathSwitch=FALSE\n", __func__); + sprintf(extra, "mp_setrfpath Aux\n"); + } + + wrqu->length = strlen(extra); + + kfree(input); + return 0; +} + + +int rtw_mp_QueryDrv(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + char* input = kmalloc(wrqu->data.length, GFP_KERNEL); + int qAutoLoad = 1; + + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + + if (copy_from_user(input, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; + DBG_871X("%s:iwpriv in=%s\n", __func__, input); + + qAutoLoad = strncmp(input, "autoload", 8); /* strncmp TRUE is 0*/ + + if (qAutoLoad == 0) { + DBG_871X("%s:qAutoLoad\n", __func__); + + if (pHalData->bautoload_fail_flag) + sprintf(extra, "fail"); + else + sprintf(extra, "ok"); + } + wrqu->data.length = strlen(extra) + 1; + kfree(input); + return 0; +} + + +int rtw_mp_PwrCtlDM(struct net_device *dev, + struct iw_request_info *info, + struct iw_point *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + u8* input = kmalloc(wrqu->length, GFP_KERNEL); + int bstart = 1; + + if (copy_from_user(input, wrqu->pointer, wrqu->length)) + return -EFAULT; + + bstart = strncmp(input, "start", 5); /* strncmp TRUE is 0*/ + if (bstart == 0) { + sprintf(extra, "PwrCtlDM start\n"); + MPT_PwrCtlDM(padapter, 1); + } else { + sprintf(extra, "PwrCtlDM stop\n"); + MPT_PwrCtlDM(padapter, 0); + } + wrqu->length = strlen(extra); + + kfree(input); + return 0; +} + + +int rtw_mp_getver(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + struct mp_priv *pmp_priv; + + pmp_priv = &padapter->mppriv; + + if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; + + sprintf(extra, "rtwpriv=%d\n", RTWPRIV_VER_INFO); + wrqu->data.length = strlen(extra); + return 0; +} + + +int rtw_mp_mon(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + struct mp_priv *pmp_priv = &padapter->mppriv; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct hal_ops *pHalFunc = &padapter->HalFunc; + NDIS_802_11_NETWORK_INFRASTRUCTURE networkType; + int bstart = 1, bstop = 1; + + networkType = Ndis802_11Infrastructure; + if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; + + rtw_pm_set_ips(padapter, IPS_NONE); + LeaveAllPowerSaveMode(padapter); + +#ifdef CONFIG_MP_INCLUDED + if (init_mp_priv(padapter) == _FAIL) + DBG_871X("%s: initialize MP private data Fail!\n", __func__); + padapter->mppriv.channel = 6; + + bstart = strncmp(extra, "start", 5); /* strncmp TRUE is 0*/ + bstop = strncmp(extra, "stop", 4); /* strncmp TRUE is 0*/ + if (bstart == 0) { + mp_join(padapter, WIFI_FW_ADHOC_STATE); + SetPacketRx(padapter, _TRUE, _FALSE); + SetChannel(padapter); + pmp_priv->rx_bindicatePkt = _TRUE; + pmp_priv->bRTWSmbCfg = _TRUE; + sprintf(extra, "monitor mode start\n"); + } else if (bstop == 0) { + SetPacketRx(padapter, _FALSE, _FALSE); + pmp_priv->rx_bindicatePkt = _FALSE; + pmp_priv->bRTWSmbCfg = _FALSE; + padapter->registrypriv.mp_mode = 1; + pHalFunc->hal_deinit(padapter); + padapter->registrypriv.mp_mode = 0; + pHalFunc->hal_init(padapter); + /*rtw_disassoc_cmd(padapter, 0, _TRUE);*/ + if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { + rtw_disassoc_cmd(padapter, 500, _TRUE); + rtw_indicate_disconnect(padapter, 0, _FALSE); + /*rtw_free_assoc_resources(padapter, 1);*/ + } + rtw_pm_set_ips(padapter, IPS_NORMAL); + sprintf(extra, "monitor mode Stop\n"); + } +#endif + wrqu->data.length = strlen(extra); + return 0; +} + +int rtw_mp_pretx_proc(PADAPTER padapter, u8 bStartTest, char *extra) +{ + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct mp_priv *pmp_priv = &padapter->mppriv; + PMPT_CONTEXT pMptCtx = &(padapter->mppriv.MptCtx); + + switch (pmp_priv->mode) { + + case MP_PACKET_TX: + if (bStartTest == 0) { + pmp_priv->tx.stop = 1; + pmp_priv->mode = MP_ON; + sprintf(extra, "Stop continuous Tx"); + } else if (pmp_priv->tx.stop == 1) { + sprintf(extra, "%s\nStart continuous DA=ffffffffffff len=1500 count=%u\n", extra, pmp_priv->tx.count); + pmp_priv->tx.stop = 0; + SetPacketTx(padapter); + } else { + return -EFAULT; + } + return 0; + case MP_SINGLE_TONE_TX: + if (bStartTest != 0) + sprintf(extra, "%s\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.", extra); + SetSingleToneTx(padapter, (u8)bStartTest); + break; + case MP_CONTINUOUS_TX: + if (bStartTest != 0) + sprintf(extra, "%s\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.", extra); + SetContinuousTx(padapter, (u8)bStartTest); + break; + case MP_CARRIER_SUPPRISSION_TX: + if (bStartTest != 0) { + if (HwRateToMPTRate(pmp_priv->rateidx) <= MPT_RATE_11M) + sprintf(extra, "%s\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.", extra); + else + sprintf(extra, "%s\nSpecify carrier suppression but not CCK rate", extra); + } + SetCarrierSuppressionTx(padapter, (u8)bStartTest); + break; + case MP_SINGLE_CARRIER_TX: + if (bStartTest != 0) + sprintf(extra, "%s\nStart continuous DA=ffffffffffff len=1500\n infinite=yes.", extra); + SetSingleCarrierTx(padapter, (u8)bStartTest); + break; + + default: + sprintf(extra, "Error! Continuous-Tx is not on-going."); + return -EFAULT; + } + + if (bStartTest == 1 && pmp_priv->mode != MP_ON) { + struct mp_priv *pmp_priv = &padapter->mppriv; + + if (pmp_priv->tx.stop == 0) { + pmp_priv->tx.stop = 1; + rtw_msleep_os(5); + } +#ifdef CONFIG_80211N_HT + pmp_priv->tx.attrib.ht_en = 1; +#endif + pmp_priv->tx.stop = 0; + pmp_priv->tx.count = 1; + SetPacketTx(padapter); + } else + pmp_priv->mode = MP_ON; + +#if defined(CONFIG_RTL8812A) + if (IS_HARDWARE_TYPE_8812AU(padapter)) { + /* <20130425, Kordan> Turn off OFDM Rx to prevent from CCA causing Tx hang.*/ + if (pmp_priv->mode == MP_PACKET_TX) + PHY_SetBBReg(padapter, rCCAonSec_Jaguar, BIT3, 1); + else + PHY_SetBBReg(padapter, rCCAonSec_Jaguar, BIT3, 0); + } +#endif + + return 0; +} + + +int rtw_mp_tx(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct mp_priv *pmp_priv = &padapter->mppriv; + PMPT_CONTEXT pMptCtx = &(padapter->mppriv.MptCtx); + struct registry_priv *pregistrypriv = &padapter->registrypriv; + + u32 bandwidth = 0, sg = 0, channel = 6, txpower = 40, rate = 108, ant = 0, txmode = 1, count = 0; + u8 i = 0, j = 0, bStartTest = 1, status = 0, Idx = 0, tmpU1B = 0; + u16 antenna = 0; + + if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; + DBG_871X("extra = %s\n", extra); +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->adapter_type == SECONDARY_ADAPTER) { + sprintf(extra, "Error: MP mode can't support Virtual Adapter, Please to use main Adapter.\n"); + wrqu->data.length = strlen(extra); + return 0; + } +#endif + + if (strncmp(extra, "stop", 3) == 0) { + bStartTest = 0; /* To set Stop*/ + pmp_priv->tx.stop = 1; + sprintf(extra, "Stop continuous Tx"); + status = rtw_mp_pretx_proc(padapter, bStartTest, extra); + wrqu->data.length = strlen(extra); + return status; + } else if (strncmp(extra, "count", 5) == 0) { + if (sscanf(extra, "count=%d", &count) < 1) + DBG_871X("Got Count=%d]\n", count); + pmp_priv->tx.count = count; + return 0; + } else if (strncmp(extra, "setting", 7) == 0) { + _rtw_memset(extra, 0, wrqu->data.length); + sprintf(extra, "Current Setting :\n Channel:%d", pmp_priv->channel); + sprintf(extra, "%s\n Bandwidth:%d", extra, pmp_priv->bandwidth); + sprintf(extra, "%s\n Rate index:%d", extra, pmp_priv->rateidx); + sprintf(extra, "%s\n TxPower index:%d", extra, pmp_priv->txpoweridx); + sprintf(extra, "%s\n Antenna TxPath:%d", extra, pmp_priv->antenna_tx); + sprintf(extra, "%s\n Antenna RxPath:%d", extra, pmp_priv->antenna_rx); + sprintf(extra, "%s\n MP Mode:%d", extra, pmp_priv->mode); + wrqu->data.length = strlen(extra); + return 0; +#ifdef CONFIG_MP_VHT_HW_TX_MODE + } else if (strncmp(extra, "pmact", 5) == 0) { + if (strncmp(extra, "pmact=", 6) == 0) { + _rtw_memset(&pMptCtx->PMacTxInfo, 0, sizeof(pMptCtx->PMacTxInfo)); + if (strncmp(extra, "pmact=start", 11) == 0) { + pMptCtx->PMacTxInfo.bEnPMacTx = _TRUE; + sprintf(extra, "Set PMac Tx Mode start\n"); + } else { + pMptCtx->PMacTxInfo.bEnPMacTx = _FALSE; + sprintf(extra, "Set PMac Tx Mode Stop\n"); + } + if (pMptCtx->bldpc == TRUE) + pMptCtx->PMacTxInfo.bLDPC = _TRUE; + + if (pMptCtx->bstbc == TRUE) + pMptCtx->PMacTxInfo.bSTBC = _TRUE; + + pMptCtx->PMacTxInfo.bSPreamble = pmp_priv->preamble; + pMptCtx->PMacTxInfo.bSGI = pmp_priv->preamble; + pMptCtx->PMacTxInfo.BandWidth = pmp_priv->bandwidth; + pMptCtx->PMacTxInfo.TX_RATE = HwRateToMPTRate(pmp_priv->rateidx); + + pMptCtx->PMacTxInfo.Mode = pMptCtx->HWTxmode; + + pMptCtx->PMacTxInfo.NDP_sound = FALSE;/*(Adapter.PacketType == NDP_PKT)?TRUE:FALSE;*/ + + if (padapter->mppriv.pktInterval == 0) + pMptCtx->PMacTxInfo.PacketPeriod = 100; + else + pMptCtx->PMacTxInfo.PacketPeriod = padapter->mppriv.pktInterval; + + if (padapter->mppriv.pktLength < 1000) + pMptCtx->PMacTxInfo.PacketLength = 1000; + else + pMptCtx->PMacTxInfo.PacketLength = padapter->mppriv.pktLength; + + pMptCtx->PMacTxInfo.PacketPattern = rtw_random32() % 0xFF; + + if (padapter->mppriv.tx_pktcount != 0) + pMptCtx->PMacTxInfo.PacketCount = padapter->mppriv.tx_pktcount; + + pMptCtx->PMacTxInfo.Ntx = 0; + for (Idx = 16; Idx < 20; Idx++) { + tmpU1B = (padapter->mppriv.antenna_tx >> Idx) & 1; + if (tmpU1B) + pMptCtx->PMacTxInfo.Ntx++; + } + + _rtw_memset(pMptCtx->PMacTxInfo.MacAddress, 0xFF, ETH_ALEN); + + PMAC_Get_Pkt_Param(&pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo); + + if (MPT_IS_CCK_RATE(pMptCtx->PMacTxInfo.TX_RATE)) { + + CCK_generator(&pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo); + } else { + PMAC_Nsym_generator(&pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo); + /* 24 BIT*/ + L_SIG_generator(pMptCtx->PMacPktInfo.N_sym, &pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo); + } + /* 48BIT*/ + if (MPT_IS_HT_RATE(pMptCtx->PMacTxInfo.TX_RATE)) + HT_SIG_generator(&pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo); + else if (MPT_IS_VHT_RATE(pMptCtx->PMacTxInfo.TX_RATE)) { + /* 48BIT*/ + VHT_SIG_A_generator(&pMptCtx->PMacTxInfo, &pMptCtx->PMacPktInfo); + + /* 26/27/29 BIT & CRC 8 BIT*/ + VHT_SIG_B_generator(&pMptCtx->PMacTxInfo); + + /* 32 BIT*/ + VHT_Delimiter_generator(&pMptCtx->PMacTxInfo); + } + + mpt_ProSetPMacTx(padapter); + + } else if (strncmp(extra, "pmact,mode=", 11) == 0) { + int txmode = 0; + + if (sscanf(extra, "pmact,mode=%d", &txmode) > 0) { + if (txmode == 1) { + pMptCtx->HWTxmode = CONTINUOUS_TX; + sprintf(extra, "\t Config HW Tx mode = CONTINUOUS_TX\n"); + } else if (txmode == 2) { + pMptCtx->HWTxmode = OFDM_Single_Tone_TX; + sprintf(extra, "\t Config HW Tx mode = OFDM_Single_Tone_TX\n"); + } else { + pMptCtx->HWTxmode = PACKETS_TX; + sprintf(extra, "\t Config HW Tx mode = PACKETS_TX\n"); + } + } else { + pMptCtx->HWTxmode = PACKETS_TX; + sprintf(extra, "\t Config HW Tx mode=\n 0 = PACKETS_TX\n 1 = CONTINUOUS_TX\n 2 = OFDM_Single_Tone_TX"); + } + } else if (strncmp(extra, "pmact,", 6) == 0) { + int PacketPeriod = 0, PacketLength = 0, PacketCout = 0; + int bldpc = 0, bstbc = 0; + + if (sscanf(extra, "pmact,period=%d", &PacketPeriod) > 0) { + padapter->mppriv.pktInterval = PacketPeriod; + DBG_871X("PacketPeriod=%d\n", padapter->mppriv.pktInterval); + sprintf(extra, "PacketPeriod [1~255]= %d\n", padapter->mppriv.pktInterval); + + } else if (sscanf(extra, "pmact,length=%d", &PacketLength) > 0) { + padapter->mppriv.pktLength = PacketLength; + DBG_871X("PacketPeriod=%d\n", padapter->mppriv.pktLength); + sprintf(extra, "PacketLength[~65535]=%d\n", padapter->mppriv.pktLength); + + } else if (sscanf(extra, "pmact,count=%d", &PacketCout) > 0) { + padapter->mppriv.tx_pktcount = PacketCout; + DBG_871X("Packet Cout =%d\n", padapter->mppriv.tx_pktcount); + sprintf(extra, "Packet Cout =%d\n", padapter->mppriv.tx_pktcount); + + } else if (sscanf(extra, "pmact,ldpc=%d", &bldpc) > 0) { + pMptCtx->bldpc = bldpc; + DBG_871X("Set LDPC =%d\n", pMptCtx->bldpc); + sprintf(extra, "Set LDPC =%d\n", pMptCtx->bldpc); + + } else if (sscanf(extra, "pmact,stbc=%d", &bstbc) > 0) { + pMptCtx->bstbc = bstbc; + DBG_871X("Set STBC =%d\n", pMptCtx->bstbc); + sprintf(extra, "Set STBC =%d\n", pMptCtx->bstbc); + } else + sprintf(extra, "\n period={1~255}\n length={1000~65535}\n count={0~}\n ldpc={0/1}\n stbc={0/1}"); + + } + + wrqu->data.length = strlen(extra); + return 0; +#endif + } else { + + if (sscanf(extra, "ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d", &channel, &bandwidth, &rate, &txpower, &ant, &txmode) < 6) { + DBG_871X("Invalid format [ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d]\n", channel, bandwidth, rate, txpower, ant, txmode); + _rtw_memset(extra, 0, wrqu->data.length); + sprintf(extra, "\n Please input correct format as bleow:\n"); + sprintf(extra, "%s\t ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d\n", extra, channel, bandwidth, rate, txpower, ant, txmode); + sprintf(extra, "%s\n [ ch : BGN = <1~14> , A or AC = <36~165> ]", extra); + sprintf(extra, "%s\n [ bw : Bandwidth: 0 = 20M, 1 = 40M, 2 = 80M ]", extra); + sprintf(extra, "%s\n [ rate : CCK: 1 2 5.5 11M X 2 = < 2 4 11 22 >]", extra); + sprintf(extra, "%s\n [ OFDM: 6 9 12 18 24 36 48 54M X 2 = < 12 18 24 36 48 72 96 108>", extra); + sprintf(extra, "%s\n [ HT 1S2SS MCS0 ~ MCS15 : < [MCS0]=128 ~ [MCS7]=135 ~ [MCS15]=143 >", extra); + sprintf(extra, "%s\n [ HT 3SS MCS16 ~ MCS32 : < [MCS16]=144 ~ [MCS23]=151 ~ [MCS32]=159 >", extra); + sprintf(extra, "%s\n [ VHT 1SS MCS0 ~ MCS9 : < [MCS0]=160 ~ [MCS9]=169 >", extra); + sprintf(extra, "%s\n [ txpower : 1~63 power index", extra); + sprintf(extra, "%s\n [ ant : ,2T ex: AB=3 BC=6 CD=12", extra); + sprintf(extra, "%s\n [ txmode : < 0 = CONTINUOUS_TX, 1 = PACKET_TX, 2 = SINGLE_TONE_TX, 3 = CARRIER_SUPPRISSION_TX, 4 = SINGLE_CARRIER_TX>\n", extra); + wrqu->data.length = strlen(extra); + return status; + + } else { + DBG_871X("Got format [ch=%d,bw=%d,rate=%d,pwr=%d,ant=%d,tx=%d]\n", channel, bandwidth, rate, txpower, ant, txmode); + _rtw_memset(extra, 0, wrqu->data.length); + sprintf(extra, "Change Current channel %d to channel %d", padapter->mppriv.channel , channel); + padapter->mppriv.channel = channel; + SetChannel(padapter); + pHalData->CurrentChannel = channel; + + if (bandwidth == 1) + bandwidth = CHANNEL_WIDTH_40; + else if (bandwidth == 2) + bandwidth = CHANNEL_WIDTH_80; + sprintf(extra, "%s\nChange Current Bandwidth %d to Bandwidth %d", extra, padapter->mppriv.bandwidth , bandwidth); + padapter->mppriv.bandwidth = (u8)bandwidth; + padapter->mppriv.preamble = sg; + SetBandwidth(padapter); + pHalData->CurrentChannelBW = bandwidth; + + sprintf(extra, "%s\nSet power level :%d", extra, txpower); + padapter->mppriv.txpoweridx = (u8)txpower; + pMptCtx->TxPwrLevel[ODM_RF_PATH_A] = (u8)txpower; + pMptCtx->TxPwrLevel[ODM_RF_PATH_B] = (u8)txpower; + pMptCtx->TxPwrLevel[ODM_RF_PATH_C] = (u8)txpower; + pMptCtx->TxPwrLevel[ODM_RF_PATH_D] = (u8)txpower; + + DBG_871X("%s: bw=%d sg=%d\n", __func__, bandwidth, sg); + + if (rate <= 0x7f) + rate = wifirate2_ratetbl_inx((u8)rate); + else if (rate < 0xC8) + rate = (rate - 0x80 + MPT_RATE_MCS0); + /*HT rate 0x80(MCS0) ~ 0x8F(MCS15) ~ 0x9F(MCS31) 128~159 + VHT1SS~2SS rate 0xA0 (VHT1SS_MCS0 44) ~ 0xB3 (VHT2SS_MCS9 #63) 160~179 + VHT rate 0xB4 (VHT3SS_MCS0 64) ~ 0xC7 (VHT2SS_MCS9 #83) 180~199 + else + VHT rate 0x90(VHT1SS_MCS0) ~ 0x99(VHT1SS_MCS9) 144~153 + rate =(rate - MPT_RATE_VHT1SS_MCS0); + */ + DBG_871X("%s: rate index=%d\n", __func__, rate); + if (rate >= MPT_RATE_LAST) + return -EINVAL; + sprintf(extra, "%s\nSet data rate to %d index %d", extra, padapter->mppriv.rateidx, rate); + + padapter->mppriv.rateidx = rate; + pMptCtx->MptRateIndex = rate; + SetDataRate(padapter); + + sprintf(extra, "%s\nSet Antenna Path :%d", extra, ant); + switch (ant) { + case 1: + antenna = ANTENNA_A; + break; + case 2: + antenna = ANTENNA_B; + break; + case 4: + antenna = ANTENNA_C; + break; + case 8: + antenna = ANTENNA_D; + break; + case 3: + antenna = ANTENNA_AB; + break; + case 5: + antenna = ANTENNA_AC; + break; + case 9: + antenna = ANTENNA_AD; + break; + case 6: + antenna = ANTENNA_BC; + break; + case 10: + antenna = ANTENNA_BD; + break; + case 12: + antenna = ANTENNA_CD; + break; + case 7: + antenna = ANTENNA_ABC; + break; + case 14: + antenna = ANTENNA_BCD; + break; + case 11: + antenna = ANTENNA_ABD; + break; + case 15: + antenna = ANTENNA_ABCD; + break; + } + DBG_871X("%s: antenna=0x%x\n", __func__, antenna); + padapter->mppriv.antenna_tx = antenna; + padapter->mppriv.antenna_rx = antenna; + pHalData->AntennaTxPath = antenna; + SetAntenna(padapter); + + if (txmode == 0) { + pmp_priv->mode = MP_CONTINUOUS_TX; + } else if (txmode == 1) { + pmp_priv->mode = MP_PACKET_TX; + pmp_priv->tx.count = count; + } else if (txmode == 2) { + pmp_priv->mode = MP_SINGLE_TONE_TX; + } else if (txmode == 3) { + pmp_priv->mode = MP_CARRIER_SUPPRISSION_TX; + } else if (txmode == 4) { + pmp_priv->mode = MP_SINGLE_CARRIER_TX; + } + + status = rtw_mp_pretx_proc(padapter, bStartTest, extra); + } + + } + + wrqu->data.length = strlen(extra); + return status; +} + + +int rtw_mp_rx(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct mp_priv *pmp_priv = &padapter->mppriv; + PMPT_CONTEXT pMptCtx = &(padapter->mppriv.MptCtx); + + u32 bandwidth = 0, sg = 0, channel = 6, ant = 0; + u16 antenna = 0; + u8 bStartRx = 0; + + if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; + +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->adapter_type == SECONDARY_ADAPTER) { + sprintf(extra, "Error: MP mode can't support Virtual Adapter, Please to use main Adapter.\n"); + wrqu->data.length = strlen(extra); + return 0; + } +#endif + + if (strncmp(extra, "stop", 4) == 0) { + _rtw_memset(extra, 0, wrqu->data.length); + SetPacketRx(padapter, bStartRx, _FALSE); + pmp_priv->bmac_filter = _FALSE; + sprintf(extra, "Received packet OK:%d CRC error:%d ,Filter out:%d", padapter->mppriv.rx_pktcount, padapter->mppriv.rx_crcerrpktcount, padapter->mppriv.rx_pktcount_filter_out); + wrqu->data.length = strlen(extra); + return 0; + + } else if (sscanf(extra, "ch=%d,bw=%d,ant=%d", &channel, &bandwidth, &ant) < 3) { + DBG_871X("Invalid format [ch=%d,bw=%d,ant=%d]\n", channel, bandwidth, ant); + _rtw_memset(extra, 0, wrqu->data.length); + sprintf(extra, "\n Please input correct format as bleow:\n"); + sprintf(extra, "%s\t ch=%d,bw=%d,ant=%d\n", extra, channel, bandwidth, ant); + sprintf(extra, "%s\n [ ch : BGN = <1~14> , A or AC = <36~165> ]", extra); + sprintf(extra, "%s\n [ bw : Bandwidth: 0 = 20M, 1 = 40M, 2 = 80M ]", extra); + sprintf(extra, "%s\n [ ant : ,2T ex: AB=3 BC=6 CD=12", extra); + wrqu->data.length = strlen(extra); + return 0; + + } else { + bStartRx = 1; + DBG_871X("Got format [ch=%d,bw=%d,ant=%d]\n", channel, bandwidth, ant); + _rtw_memset(extra, 0, wrqu->data.length); + sprintf(extra, "Change Current channel %d to channel %d", padapter->mppriv.channel , channel); + padapter->mppriv.channel = channel; + SetChannel(padapter); + pHalData->CurrentChannel = channel; + + if (bandwidth == 1) + bandwidth = CHANNEL_WIDTH_40; + else if (bandwidth == 2) + bandwidth = CHANNEL_WIDTH_80; + sprintf(extra, "%s\nChange Current Bandwidth %d to Bandwidth %d", extra, padapter->mppriv.bandwidth , bandwidth); + padapter->mppriv.bandwidth = (u8)bandwidth; + padapter->mppriv.preamble = sg; + SetBandwidth(padapter); + pHalData->CurrentChannelBW = bandwidth; + + sprintf(extra, "%s\nSet Antenna Path :%d", extra, ant); + switch (ant) { + case 1: + antenna = ANTENNA_A; + break; + case 2: + antenna = ANTENNA_B; + break; + case 4: + antenna = ANTENNA_C; + break; + case 8: + antenna = ANTENNA_D; + break; + case 3: + antenna = ANTENNA_AB; + break; + case 5: + antenna = ANTENNA_AC; + break; + case 9: + antenna = ANTENNA_AD; + break; + case 6: + antenna = ANTENNA_BC; + break; + case 10: + antenna = ANTENNA_BD; + break; + case 12: + antenna = ANTENNA_CD; + break; + case 7: + antenna = ANTENNA_ABC; + break; + case 14: + antenna = ANTENNA_BCD; + break; + case 11: + antenna = ANTENNA_ABD; + break; + case 15: + antenna = ANTENNA_ABCD; + break; + } + DBG_871X("%s: antenna=0x%x\n", __func__, antenna); + padapter->mppriv.antenna_tx = antenna; + padapter->mppriv.antenna_rx = antenna; + pHalData->AntennaTxPath = antenna; + SetAntenna(padapter); + + sprintf(extra, "%s\nstart Rx", extra); + SetPacketRx(padapter, bStartRx, _FALSE); + } + wrqu->data.length = strlen(extra); + return 0; +} + + +int rtw_mp_hwtx(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct mp_priv *pmp_priv = &padapter->mppriv; + PMPT_CONTEXT pMptCtx = &(padapter->mppriv.MptCtx); + +#if defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8821B) || defined(CONFIG_RTL8822B) + u8* input = malloc(wrqu->data.length, GFP_KERNEL); + + if (copy_from_user(input, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; + + _rtw_memset(&pMptCtx->PMacTxInfo, 0, sizeof(RT_PMAC_TX_INFO)); + _rtw_memcpy((void *)&pMptCtx->PMacTxInfo, (void *)input, sizeof(RT_PMAC_TX_INFO)); + + mpt_ProSetPMacTx(padapter); + sprintf(extra, "Set PMac Tx Mode start\n"); + + wrqu->data.length = strlen(extra); + kfree(input); +#endif + return 0; + +} + +int rtw_efuse_mask_file(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + char *rtw_efuse_mask_file_path; + u8 Status; + PADAPTER padapter = rtw_netdev_priv(dev); + + _rtw_memset(maskfileBuffer, 0x00, sizeof(maskfileBuffer)); + + if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; + + if (strncmp(extra, "off", 3) == 0 && strlen(extra) < 4) { + padapter->registrypriv.boffefusemask = 1; + sprintf(extra, "Turn off Efuse Mask\n"); + wrqu->data.length = strlen(extra); + return 0; + } + if (strncmp(extra, "on", 2) == 0 && strlen(extra) < 3) { + padapter->registrypriv.boffefusemask = 0; + sprintf(extra, "Turn on Efuse Mask\n"); + wrqu->data.length = strlen(extra); + return 0; + } + rtw_efuse_mask_file_path = extra; + + if (rtw_is_file_readable(rtw_efuse_mask_file_path) == _TRUE) { + DBG_871X("%s do rtw_efuse_mask_file_read = %s! ,sizeof maskfileBuffer %zu\n", __func__, rtw_efuse_mask_file_path, sizeof(maskfileBuffer)); + Status = rtw_efuse_file_read(padapter, rtw_efuse_mask_file_path, maskfileBuffer, sizeof(maskfileBuffer)); + if (Status == _TRUE) + padapter->registrypriv.bFileMaskEfuse = _TRUE; + sprintf(extra, "efuse mask file read OK\n"); + } else { + padapter->registrypriv.bFileMaskEfuse = _FALSE; + sprintf(extra, "efuse mask file readable FAIL\n"); + DBG_871X("%s rtw_is_file_readable fail!\n", __func__); + } + wrqu->data.length = strlen(extra); + return 0; +} + + +int rtw_efuse_file_map(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + char *rtw_efuse_file_map_path; + u8 Status; + PEFUSE_HAL pEfuseHal; + PADAPTER padapter = rtw_netdev_priv(dev); + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + pEfuseHal = &pHalData->EfuseHal; + if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; + + rtw_efuse_file_map_path = extra; + + if (rtw_is_file_readable(rtw_efuse_file_map_path) == _TRUE) { + DBG_871X("%s do rtw_efuse_mask_file_read = %s!\n", __func__, rtw_efuse_file_map_path); + Status = rtw_efuse_file_read(padapter, rtw_efuse_file_map_path, pEfuseHal->fakeEfuseModifiedMap, sizeof(pEfuseHal->fakeEfuseModifiedMap)); + if (Status == _TRUE) + sprintf(extra, "efuse file file_read OK\n"); + else + sprintf(extra, "efuse file file_read FAIL\n"); + } else { + sprintf(extra, "efuse file readable FAIL\n"); + DBG_871X("%s rtw_is_file_readable fail!\n", __func__); + } + wrqu->data.length = strlen(extra); + return 0; +} + +#if defined(CONFIG_RTL8723B) +int rtw_mp_SetBT(struct net_device *dev, + struct iw_request_info *info, + union iwreq_data *wrqu, char *extra) +{ + PADAPTER padapter = rtw_netdev_priv(dev); + struct hal_ops *pHalFunc = &padapter->HalFunc; + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + + BT_REQ_CMD BtReq; + PMPT_CONTEXT pMptCtx = &(padapter->mppriv.MptCtx); + PBT_RSP_CMD pBtRsp = (PBT_RSP_CMD)&pMptCtx->mptOutBuf[0]; + char input[128]; + char *pch, *ptmp, *token, *tmp[2] = {0x00, 0x00}; + u8 setdata[100]; + u8 resetbt = 0x00; + u8 tempval, BTStatus; + u8 H2cSetbtmac[6]; + u8 u1H2CBtMpOperParm[4] = {0x01}; + int testmode = 1, ready = 1, trxparam = 1, setgen = 1, getgen = 1, testctrl = 1, testbt = 1, readtherm = 1, setbtmac = 1; + u32 i = 0, ii = 0, jj = 0, kk = 0, cnts = 0, status = 0; + PRT_MP_FIRMWARE pBTFirmware = NULL; + + if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) + return -EFAULT; + if (strlen(extra) < 1) + return -EFAULT; + + DBG_871X("%s:iwpriv in=%s\n", __func__, extra); + ready = strncmp(extra, "ready", 5); + testmode = strncmp(extra, "testmode", 8); /* strncmp TRUE is 0*/ + trxparam = strncmp(extra, "trxparam", 8); + setgen = strncmp(extra, "setgen", 6); + getgen = strncmp(extra, "getgen", 6); + testctrl = strncmp(extra, "testctrl", 8); + testbt = strncmp(extra, "testbt", 6); + readtherm = strncmp(extra, "readtherm", 9); + setbtmac = strncmp(extra, "setbtmac", 8); + + if (strncmp(extra, "dlbt", 4) == 0) { + pHalData->LastHMEBoxNum = 0; + padapter->bBTFWReady = _FALSE; + rtw_write8(padapter, 0xa3, 0x05); + BTStatus = rtw_read8(padapter, 0xa0); + DBG_871X("%s: btwmap before read 0xa0 BT Status =0x%x\n", __func__, BTStatus); + if (BTStatus != 0x04) { + sprintf(extra, "BT Status not Active DLFW FAIL\n"); + goto exit; + } + + tempval = rtw_read8(padapter, 0x6B); + tempval |= BIT7; + rtw_write8(padapter, 0x6B, tempval); + + /* Attention!! Between 0x6A[14] and 0x6A[15] setting need 100us delay*/ + /* So don't write 0x6A[14]=1 and 0x6A[15]=0 together!*/ + rtw_usleep_os(100); + /* disable BT power cut*/ + /* 0x6A[14] = 0*/ + tempval = rtw_read8(padapter, 0x6B); + tempval &= ~BIT6; + rtw_write8(padapter, 0x6B, tempval); + rtw_usleep_os(100); + MPT_PwrCtlDM(padapter, 0); + rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) | 0x00000004)); + rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) & 0xFFFFFFEF)); + rtw_msleep_os(600); + rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) | 0x00000010)); + rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) & 0xFFFFFFFB)); + rtw_msleep_os(1200); + pBTFirmware = (PRT_MP_FIRMWARE)rtw_zmalloc(sizeof(RT_MP_FIRMWARE)); + if (pBTFirmware == NULL) + goto exit; + padapter->bBTFWReady = _FALSE; + FirmwareDownloadBT(padapter, pBTFirmware); + if (pBTFirmware) + rtw_mfree((u8 *)pBTFirmware, sizeof(RT_MP_FIRMWARE)); + + DBG_871X("Wait for FirmwareDownloadBT fw boot!\n"); + rtw_msleep_os(2000); + _rtw_memset(extra, '\0', wrqu->data.length); + BtReq.opCodeVer = 1; + BtReq.OpCode = 0; + BtReq.paraLength = 0; + mptbt_BtControlProcess(padapter, &BtReq); + rtw_msleep_os(100); + + DBG_8192C("FirmwareDownloadBT ready = 0x%x 0x%x", pMptCtx->mptOutBuf[4], pMptCtx->mptOutBuf[5]); + if ((pMptCtx->mptOutBuf[4] == 0x00) && (pMptCtx->mptOutBuf[5] == 0x00)) { + + if (padapter->mppriv.bTxBufCkFail == _TRUE) + sprintf(extra, "check TxBuf Fail.\n"); + else + sprintf(extra, "download FW Fail.\n"); + } else { + sprintf(extra, "download FW OK.\n"); + goto exit; + } + goto exit; + } + if (strncmp(extra, "dlfw", 4) == 0) { + pHalData->LastHMEBoxNum = 0; + padapter->bBTFWReady = _FALSE; + rtw_write8(padapter, 0xa3, 0x05); + BTStatus = rtw_read8(padapter, 0xa0); + DBG_871X("%s: btwmap before read 0xa0 BT Status =0x%x\n", __func__, BTStatus); + if (BTStatus != 0x04) { + sprintf(extra, "BT Status not Active DLFW FAIL\n"); + goto exit; + } + + tempval = rtw_read8(padapter, 0x6B); + tempval |= BIT7; + rtw_write8(padapter, 0x6B, tempval); + + /* Attention!! Between 0x6A[14] and 0x6A[15] setting need 100us delay*/ + /* So don't write 0x6A[14]=1 and 0x6A[15]=0 together!*/ + rtw_usleep_os(100); + /* disable BT power cut*/ + /* 0x6A[14] = 0*/ + tempval = rtw_read8(padapter, 0x6B); + tempval &= ~BIT6; + rtw_write8(padapter, 0x6B, tempval); + rtw_usleep_os(100); + + MPT_PwrCtlDM(padapter, 0); + rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) | 0x00000004)); + rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) & 0xFFFFFFEF)); + rtw_msleep_os(600); + rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) | 0x00000010)); + rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) & 0xFFFFFFFB)); + rtw_msleep_os(1200); + +#if defined(CONFIG_PLATFORM_SPRD) && (MP_DRIVER == 1) + /* Pull up BT reset pin.*/ + DBG_871X("%s: pull up BT reset pin when bt start mp test\n", __func__); + rtw_wifi_gpio_wlan_ctrl(WLAN_BT_PWDN_ON); +#endif + DBG_871X(" FirmwareDownload!\n"); + +#if defined(CONFIG_RTL8723B) + status = rtl8723b_FirmwareDownload(padapter, _FALSE); +#endif + DBG_871X("Wait for FirmwareDownloadBT fw boot!\n"); + rtw_msleep_os(1000); +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_HaltNotify(padapter); + DBG_871X("SetBT btcoex HaltNotify !\n"); + /*hal_btcoex1ant_SetAntPath(padapter);*/ + rtw_btcoex_SetManualControl(padapter, _TRUE); +#endif + _rtw_memset(extra, '\0', wrqu->data.length); + BtReq.opCodeVer = 1; + BtReq.OpCode = 0; + BtReq.paraLength = 0; + mptbt_BtControlProcess(padapter, &BtReq); + rtw_msleep_os(200); + + DBG_8192C("FirmwareDownloadBT ready = 0x%x 0x%x", pMptCtx->mptOutBuf[4], pMptCtx->mptOutBuf[5]); + if ((pMptCtx->mptOutBuf[4] == 0x00) && (pMptCtx->mptOutBuf[5] == 0x00)) { + if (padapter->mppriv.bTxBufCkFail == _TRUE) + sprintf(extra, "check TxBuf Fail.\n"); + else + sprintf(extra, "download FW Fail.\n"); + } else { +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_SwitchBtTRxMask(padapter); +#endif + rtw_msleep_os(200); + sprintf(extra, "download FW OK.\n"); + goto exit; + } + goto exit; + } + + if (strncmp(extra, "down", 4) == 0) { + DBG_871X("SetBT down for to hal_init !\n"); +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_SetManualControl(padapter, _FALSE); + rtw_btcoex_Initialize(padapter); +#endif + pHalFunc->read_adapter_info(padapter); + pHalFunc->hal_deinit(padapter); + pHalFunc->hal_init(padapter); + rtw_pm_set_ips(padapter, IPS_NONE); + LeaveAllPowerSaveMode(padapter); + MPT_PwrCtlDM(padapter, 0); + rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) | 0x00000004)); + rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) & 0xFFFFFFEF)); + rtw_msleep_os(600); + /*rtw_write32(padapter, 0x6a, (rtw_read32(padapter, 0x6a)& 0xFFFFFFFE));*/ + rtw_write32(padapter, 0x6b, (rtw_read32(padapter, 0x6b) | 0x00000010)); + rtw_write32(padapter, 0xcc, (rtw_read32(padapter, 0xcc) & 0xFFFFFFFB)); + rtw_msleep_os(1200); + goto exit; + } + if (strncmp(extra, "disable", 7) == 0) { + DBG_871X("SetBT disable !\n"); + rtw_write32(padapter, 0x6a, (rtw_read32(padapter, 0x6a) & 0xFFFFFFFB)); + rtw_msleep_os(500); + goto exit; + } + if (strncmp(extra, "enable", 6) == 0) { + DBG_871X("SetBT enable !\n"); + rtw_write32(padapter, 0x6a, (rtw_read32(padapter, 0x6a) | 0x00000004)); + rtw_msleep_os(500); + goto exit; + } + if (strncmp(extra, "h2c", 3) == 0) { + DBG_871X("SetBT h2c !\n"); + padapter->bBTFWReady = _TRUE; + rtw_hal_fill_h2c_cmd(padapter, 0x63, 1, u1H2CBtMpOperParm); + goto exit; + } + if (strncmp(extra, "2ant", 4) == 0) { + DBG_871X("Set BT 2ant use!\n"); + PHY_SetMacReg(padapter, 0x67, BIT5, 0x1); + rtw_write32(padapter, 0x948, 0000); + + goto exit; + } + + if (ready != 0 && testmode != 0 && trxparam != 0 && setgen != 0 && getgen != 0 && testctrl != 0 && testbt != 0 && readtherm != 0 && setbtmac != 0) + return -EFAULT; + + if (testbt == 0) { + BtReq.opCodeVer = 1; + BtReq.OpCode = 6; + BtReq.paraLength = cnts / 2; + goto todo; + } + if (ready == 0) { + BtReq.opCodeVer = 1; + BtReq.OpCode = 0; + BtReq.paraLength = 0; + goto todo; + } + + pch = extra; + i = 0; + while ((token = strsep(&pch, ",")) != NULL) { + if (i > 1) + break; + tmp[i] = token; + i++; + } + + if ((tmp[0] != NULL) && (tmp[1] != NULL)) { + cnts = strlen(tmp[1]); + if (cnts < 1) + return -EFAULT; + + DBG_871X("%s: cnts=%d\n", __func__, cnts); + DBG_871X("%s: data=%s\n", __func__, tmp[1]); + + for (jj = 0, kk = 0; jj < cnts; jj++, kk += 2) { + BtReq.pParamStart[jj] = key_2char2num(tmp[1][kk], tmp[1][kk + 1]); + /* DBG_871X("BtReq.pParamStart[%d]=0x%02x\n", jj, BtReq.pParamStart[jj]);*/ + } + } else + return -EFAULT; + + if (testmode == 0) { + BtReq.opCodeVer = 1; + BtReq.OpCode = 1; + BtReq.paraLength = 1; + } + if (trxparam == 0) { + BtReq.opCodeVer = 1; + BtReq.OpCode = 2; + BtReq.paraLength = cnts / 2; + } + if (setgen == 0) { + DBG_871X("%s: BT_SET_GENERAL\n", __func__); + BtReq.opCodeVer = 1; + BtReq.OpCode = 3;/*BT_SET_GENERAL 3*/ + BtReq.paraLength = cnts / 2; + } + if (getgen == 0) { + DBG_871X("%s: BT_GET_GENERAL\n", __func__); + BtReq.opCodeVer = 1; + BtReq.OpCode = 4;/*BT_GET_GENERAL 4*/ + BtReq.paraLength = cnts / 2; + } + if (readtherm == 0) { + DBG_871X("%s: BT_GET_GENERAL\n", __func__); + BtReq.opCodeVer = 1; + BtReq.OpCode = 4;/*BT_GET_GENERAL 4*/ + BtReq.paraLength = cnts / 2; + } + + if (testctrl == 0) { + DBG_871X("%s: BT_TEST_CTRL\n", __func__); + BtReq.opCodeVer = 1; + BtReq.OpCode = 5;/*BT_TEST_CTRL 5*/ + BtReq.paraLength = cnts / 2; + } + + DBG_871X("%s: Req opCodeVer=%d OpCode=%d paraLength=%d\n", + __func__, BtReq.opCodeVer, BtReq.OpCode, BtReq.paraLength); + + if (BtReq.paraLength < 1) + goto todo; + for (i = 0; i < BtReq.paraLength; i++) { + DBG_871X("%s: BtReq.pParamStart[%d] = 0x%02x\n", + __func__, i, BtReq.pParamStart[i]); + } + +todo: + _rtw_memset(extra, '\0', wrqu->data.length); + + if (padapter->bBTFWReady == _FALSE) { + sprintf(extra, "BTFWReady = FALSE.\n"); + goto exit; + } + + mptbt_BtControlProcess(padapter, &BtReq); + + if (readtherm == 0) { + sprintf(extra, "BT thermal="); + for (i = 4; i < pMptCtx->mptOutLen; i++) { + if ((pMptCtx->mptOutBuf[i] == 0x00) && (pMptCtx->mptOutBuf[i + 1] == 0x00)) + goto exit; + + sprintf(extra, "%s %d ", extra, (pMptCtx->mptOutBuf[i] & 0x1f)); + } + } else { + for (i = 4; i < pMptCtx->mptOutLen; i++) + sprintf(extra, "%s 0x%x ", extra, pMptCtx->mptOutBuf[i]); + } + +exit: + wrqu->data.length = strlen(extra) + 1; + DBG_871X("-%s: output len=%d data=%s\n", __func__, wrqu->data.length, extra); + + return status; +} + +#endif /*#ifdef CONFIG_RTL8723B*/ + +#endif diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/mlme_linux.c b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/mlme_linux.c new file mode 100644 index 000000000..c3edb3a07 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/mlme_linux.c @@ -0,0 +1,618 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#define _MLME_OSDEP_C_ + +#include + + +#ifdef RTK_DMP_PLATFORM +void Linkup_workitem_callback(struct work_struct *work) +{ + struct mlme_priv *pmlmepriv = container_of(work, struct mlme_priv, Linkup_workitem); + _adapter *padapter = container_of(pmlmepriv, _adapter, mlmepriv); + +_func_enter_; + + RT_TRACE(_module_mlme_osdep_c_,_drv_info_,("+ Linkup_workitem_callback\n")); + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,12)) + kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_LINKUP); +#else + kobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_LINKUP); +#endif + +_func_exit_; +} + +void Linkdown_workitem_callback(struct work_struct *work) +{ + struct mlme_priv *pmlmepriv = container_of(work, struct mlme_priv, Linkdown_workitem); + _adapter *padapter = container_of(pmlmepriv, _adapter, mlmepriv); + +_func_enter_; + + RT_TRACE(_module_mlme_osdep_c_,_drv_info_,("+ Linkdown_workitem_callback\n")); + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,12)) + kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_LINKDOWN); +#else + kobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_LINKDOWN); +#endif + +_func_exit_; +} +#endif + + +/* +void sitesurvey_ctrl_handler(void *FunctionContext) +{ + _adapter *adapter = (_adapter *)FunctionContext; + + _sitesurvey_ctrl_handler(adapter); + + _set_timer(&adapter->mlmepriv.sitesurveyctrl.sitesurvey_ctrl_timer, 3000); +} +*/ + +void rtw_join_timeout_handler (void *FunctionContext) +{ + _adapter *adapter = (_adapter *)FunctionContext; + _rtw_join_timeout_handler(adapter); +} + + +void _rtw_scan_timeout_handler (void *FunctionContext) +{ + _adapter *adapter = (_adapter *)FunctionContext; + rtw_scan_timeout_handler(adapter); +} + + +void _dynamic_check_timer_handlder (void *FunctionContext) +{ + _adapter *adapter = (_adapter *)FunctionContext; + +#if (MP_DRIVER == 1) + if (adapter->registrypriv.mp_mode == 1 && adapter->mppriv.mp_dm ==0) //for MP ODM dynamic Tx power tracking + { + //DBG_871X("_dynamic_check_timer_handlder mp_dm =0 return \n"); + _set_timer(&adapter->mlmepriv.dynamic_chk_timer, 2000); + return; + } +#endif + +#ifdef CONFIG_CONCURRENT_MODE + if(adapter->pbuddy_adapter) + rtw_dynamic_check_timer_handlder(adapter->pbuddy_adapter); +#endif //CONFIG_CONCURRENT_MODE + + rtw_dynamic_check_timer_handlder(adapter); + + _set_timer(&adapter->mlmepriv.dynamic_chk_timer, 2000); +} + +#ifdef CONFIG_SET_SCAN_DENY_TIMER +void _rtw_set_scan_deny_timer_hdl(void *FunctionContext) +{ + _adapter *adapter = (_adapter *)FunctionContext; + rtw_set_scan_deny_timer_hdl(adapter); +} +#endif + + +void rtw_init_mlme_timer(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + _init_timer(&(pmlmepriv->assoc_timer), padapter->pnetdev, rtw_join_timeout_handler, padapter); + //_init_timer(&(pmlmepriv->sitesurveyctrl.sitesurvey_ctrl_timer), padapter->pnetdev, sitesurvey_ctrl_handler, padapter); + _init_timer(&(pmlmepriv->scan_to_timer), padapter->pnetdev, _rtw_scan_timeout_handler, padapter); + + #ifdef CONFIG_DFS_MASTER + _init_timer(&(pmlmepriv->dfs_master_timer), padapter->pnetdev, rtw_dfs_master_timer_hdl, padapter); + #endif + + _init_timer(&(pmlmepriv->dynamic_chk_timer), padapter->pnetdev, _dynamic_check_timer_handlder, padapter); + + #ifdef CONFIG_SET_SCAN_DENY_TIMER + _init_timer(&(pmlmepriv->set_scan_deny_timer), padapter->pnetdev, _rtw_set_scan_deny_timer_hdl, padapter); + #endif + +#ifdef RTK_DMP_PLATFORM + _init_workitem(&(pmlmepriv->Linkup_workitem), Linkup_workitem_callback, padapter); + _init_workitem(&(pmlmepriv->Linkdown_workitem), Linkdown_workitem_callback, padapter); +#endif + +} + +extern void rtw_indicate_wx_assoc_event(_adapter *padapter); +extern void rtw_indicate_wx_disassoc_event(_adapter *padapter); + +void rtw_os_indicate_connect(_adapter *adapter) +{ + struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); +_func_enter_; + +#ifdef CONFIG_IOCTL_CFG80211 + if ( (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)==_TRUE ) || + (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)==_TRUE ) ) + { + rtw_cfg80211_ibss_indicate_connect(adapter); + } + else + rtw_cfg80211_indicate_connect(adapter); +#endif //CONFIG_IOCTL_CFG80211 + + rtw_indicate_wx_assoc_event(adapter); + netif_carrier_on(adapter->pnetdev); + + if(adapter->pid[2] !=0) + rtw_signal_process(adapter->pid[2], SIGALRM); + +#ifdef RTK_DMP_PLATFORM + _set_workitem(&adapter->mlmepriv.Linkup_workitem); +#endif + +_func_exit_; + +} + +extern void indicate_wx_scan_complete_event(_adapter *padapter); +void rtw_os_indicate_scan_done( _adapter *padapter, bool aborted) +{ +#ifdef CONFIG_IOCTL_CFG80211 + rtw_cfg80211_indicate_scan_done(padapter, aborted); +#endif + indicate_wx_scan_complete_event(padapter); +} + +static RT_PMKID_LIST backupPMKIDList[ NUM_PMKID_CACHE ]; +void rtw_reset_securitypriv( _adapter *adapter ) +{ + u8 backupPMKIDIndex = 0; + u8 backupTKIPCountermeasure = 0x00; + u32 backupTKIPcountermeasure_time = 0; + // add for CONFIG_IEEE80211W, none 11w also can use + _irqL irqL; + struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; + + _enter_critical_bh(&adapter->security_key_mutex, &irqL); + + if(adapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)//802.1x + { + // Added by Albert 2009/02/18 + // We have to backup the PMK information for WiFi PMK Caching test item. + // + // Backup the btkip_countermeasure information. + // When the countermeasure is trigger, the driver have to disconnect with AP for 60 seconds. + + _rtw_memset( &backupPMKIDList[ 0 ], 0x00, sizeof( RT_PMKID_LIST ) * NUM_PMKID_CACHE ); + + _rtw_memcpy( &backupPMKIDList[ 0 ], &adapter->securitypriv.PMKIDList[ 0 ], sizeof( RT_PMKID_LIST ) * NUM_PMKID_CACHE ); + backupPMKIDIndex = adapter->securitypriv.PMKIDIndex; + backupTKIPCountermeasure = adapter->securitypriv.btkip_countermeasure; + backupTKIPcountermeasure_time = adapter->securitypriv.btkip_countermeasure_time; +#ifdef CONFIG_IEEE80211W + //reset RX BIP packet number + pmlmeext->mgnt_80211w_IPN_rx = 0; +#endif //CONFIG_IEEE80211W + _rtw_memset((unsigned char *)&adapter->securitypriv, 0, sizeof (struct security_priv)); + //_init_timer(&(adapter->securitypriv.tkip_timer),adapter->pnetdev, rtw_use_tkipkey_handler, adapter); + + // Added by Albert 2009/02/18 + // Restore the PMK information to securitypriv structure for the following connection. + _rtw_memcpy( &adapter->securitypriv.PMKIDList[ 0 ], &backupPMKIDList[ 0 ], sizeof( RT_PMKID_LIST ) * NUM_PMKID_CACHE ); + adapter->securitypriv.PMKIDIndex = backupPMKIDIndex; + adapter->securitypriv.btkip_countermeasure = backupTKIPCountermeasure; + adapter->securitypriv.btkip_countermeasure_time = backupTKIPcountermeasure_time; + + adapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen; + adapter->securitypriv.ndisencryptstatus = Ndis802_11WEPDisabled; + + } + else //reset values in securitypriv + { + //if(adapter->mlmepriv.fw_state & WIFI_STATION_STATE) + //{ + struct security_priv *psec_priv=&adapter->securitypriv; + + psec_priv->dot11AuthAlgrthm =dot11AuthAlgrthm_Open; //open system + psec_priv->dot11PrivacyAlgrthm = _NO_PRIVACY_; + psec_priv->dot11PrivacyKeyIndex = 0; + + psec_priv->dot118021XGrpPrivacy = _NO_PRIVACY_; + psec_priv->dot118021XGrpKeyid = 1; + + psec_priv->ndisauthtype = Ndis802_11AuthModeOpen; + psec_priv->ndisencryptstatus = Ndis802_11WEPDisabled; + //} + } + // add for CONFIG_IEEE80211W, none 11w also can use + _exit_critical_bh(&adapter->security_key_mutex, &irqL); + + DBG_871X(FUNC_ADPT_FMT" - End to Disconnect\n", FUNC_ADPT_ARG(adapter)); +} + +void rtw_os_indicate_disconnect(_adapter *adapter, u16 reason, u8 locally_generated) +{ + //RT_PMKID_LIST backupPMKIDList[ NUM_PMKID_CACHE ]; + +_func_enter_; + + netif_carrier_off(adapter->pnetdev); // Do it first for tx broadcast pkt after disconnection issue! + +#ifdef CONFIG_IOCTL_CFG80211 + rtw_cfg80211_indicate_disconnect(adapter, reason, locally_generated); +#endif //CONFIG_IOCTL_CFG80211 + + rtw_indicate_wx_disassoc_event(adapter); + +#ifdef RTK_DMP_PLATFORM + _set_workitem(&adapter->mlmepriv.Linkdown_workitem); +#endif + //modify for CONFIG_IEEE80211W, none 11w also can use the same command + rtw_reset_securitypriv_cmd(adapter); + +_func_exit_; + +} + +void rtw_report_sec_ie(_adapter *adapter,u8 authmode,u8 *sec_ie) +{ + uint len; + u8 *buff,*p,i; + union iwreq_data wrqu; + +_func_enter_; + + RT_TRACE(_module_mlme_osdep_c_,_drv_info_,("+rtw_report_sec_ie, authmode=%d\n", authmode)); + + buff = NULL; + if(authmode==_WPA_IE_ID_) + { + RT_TRACE(_module_mlme_osdep_c_,_drv_info_,("rtw_report_sec_ie, authmode=%d\n", authmode)); + + buff = rtw_zmalloc(IW_CUSTOM_MAX); + if (NULL == buff) { + DBG_871X(FUNC_ADPT_FMT ": alloc memory FAIL!!\n", + FUNC_ADPT_ARG(adapter)); + return; + } + p = buff; + + p+=sprintf(p,"ASSOCINFO(ReqIEs="); + + len = sec_ie[1]+2; + len = (len < IW_CUSTOM_MAX) ? len:IW_CUSTOM_MAX; + + for(i=0;ipnetdev,IWEVCUSTOM,&wrqu,buff); +#endif + + rtw_mfree(buff, IW_CUSTOM_MAX); + } + +exit: + +_func_exit_; + +} + +void _survey_timer_hdl (void *FunctionContext) +{ + _adapter *padapter = (_adapter *)FunctionContext; + + survey_timer_hdl(padapter); +} + +void _link_timer_hdl (void *FunctionContext) +{ + _adapter *padapter = (_adapter *)FunctionContext; + link_timer_hdl(padapter); +} + +void _addba_timer_hdl(void *FunctionContext) +{ + struct sta_info *psta = (struct sta_info *)FunctionContext; + addba_timer_hdl(psta); +} + +#ifdef CONFIG_IEEE80211W + +void _sa_query_timer_hdl (void *FunctionContext) +{ + struct sta_info *psta = (struct sta_info *)FunctionContext; + + sa_query_timer_hdl(psta); +} + +void init_dot11w_expire_timer(_adapter *padapter, struct sta_info *psta) +{ + _init_timer(&psta->dot11w_expire_timer, padapter->pnetdev, _sa_query_timer_hdl, psta); +} + +#endif //CONFIG_IEEE80211W + +void init_addba_retry_timer(_adapter *padapter, struct sta_info *psta) +{ + + _init_timer(&psta->addba_retry_timer, padapter->pnetdev, _addba_timer_hdl, psta); +} + +/* +void _reauth_timer_hdl(void *FunctionContext) +{ + _adapter *padapter = (_adapter *)FunctionContext; + reauth_timer_hdl(padapter); +} + +void _reassoc_timer_hdl(void *FunctionContext) +{ + _adapter *padapter = (_adapter *)FunctionContext; + reassoc_timer_hdl(padapter); +} +*/ + +void init_mlme_ext_timer(_adapter *padapter) +{ + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + + _init_timer(&pmlmeext->survey_timer, padapter->pnetdev, _survey_timer_hdl, padapter); + _init_timer(&pmlmeext->link_timer, padapter->pnetdev, _link_timer_hdl, padapter); + + //_init_timer(&pmlmeext->ADDBA_timer, padapter->pnetdev, _addba_timer_hdl, padapter); + + //_init_timer(&pmlmeext->reauth_timer, padapter->pnetdev, _reauth_timer_hdl, padapter); + //_init_timer(&pmlmeext->reassoc_timer, padapter->pnetdev, _reassoc_timer_hdl, padapter); +} + +#ifdef CONFIG_AP_MODE + +void rtw_indicate_sta_assoc_event(_adapter *padapter, struct sta_info *psta) +{ + union iwreq_data wrqu; + struct sta_priv *pstapriv = &padapter->stapriv; + + if(psta==NULL) + return; + + if(psta->aid > NUM_STA) + return; + + if(pstapriv->sta_aid[psta->aid - 1] != psta) + return; + + + wrqu.addr.sa_family = ARPHRD_ETHER; + + _rtw_memcpy(wrqu.addr.sa_data, psta->hwaddr, ETH_ALEN); + + DBG_871X("+rtw_indicate_sta_assoc_event\n"); + +#ifndef CONFIG_IOCTL_CFG80211 + wireless_send_event(padapter->pnetdev, IWEVREGISTERED, &wrqu, NULL); +#endif + +} + +void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info *psta) +{ + union iwreq_data wrqu; + struct sta_priv *pstapriv = &padapter->stapriv; + + if(psta==NULL) + return; + + if(psta->aid > NUM_STA) + return; + + if(pstapriv->sta_aid[psta->aid - 1] != psta) + return; + + + wrqu.addr.sa_family = ARPHRD_ETHER; + + _rtw_memcpy(wrqu.addr.sa_data, psta->hwaddr, ETH_ALEN); + + DBG_871X("+rtw_indicate_sta_disassoc_event\n"); + +#ifndef CONFIG_IOCTL_CFG80211 + wireless_send_event(padapter->pnetdev, IWEVEXPIRED, &wrqu, NULL); +#endif + +} + + +#ifdef CONFIG_HOSTAPD_MLME + +static int mgnt_xmit_entry(struct sk_buff *skb, struct net_device *pnetdev) +{ + struct hostapd_priv *phostapdpriv = rtw_netdev_priv(pnetdev); + _adapter *padapter = (_adapter *)phostapdpriv->padapter; + + //DBG_871X("%s\n", __FUNCTION__); + + return rtw_hal_hostap_mgnt_xmit_entry(padapter, skb); +} + +static int mgnt_netdev_open(struct net_device *pnetdev) +{ + struct hostapd_priv *phostapdpriv = rtw_netdev_priv(pnetdev); + + DBG_871X("mgnt_netdev_open: MAC Address:" MAC_FMT "\n", MAC_ARG(pnetdev->dev_addr)); + + + init_usb_anchor(&phostapdpriv->anchored); + + rtw_netif_wake_queue(pnetdev); + + netif_carrier_on(pnetdev); + + //rtw_write16(phostapdpriv->padapter, 0x0116, 0x0100);//only excluding beacon + + return 0; +} +static int mgnt_netdev_close(struct net_device *pnetdev) +{ + struct hostapd_priv *phostapdpriv = rtw_netdev_priv(pnetdev); + + DBG_871X("%s\n", __FUNCTION__); + + usb_kill_anchored_urbs(&phostapdpriv->anchored); + + netif_carrier_off(pnetdev); + + rtw_netif_stop_queue(pnetdev); + + //rtw_write16(phostapdpriv->padapter, 0x0116, 0x3f3f); + + return 0; +} + +#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29)) +static const struct net_device_ops rtl871x_mgnt_netdev_ops = { + .ndo_open = mgnt_netdev_open, + .ndo_stop = mgnt_netdev_close, + .ndo_start_xmit = mgnt_xmit_entry, + //.ndo_set_mac_address = r871x_net_set_mac_address, + //.ndo_get_stats = r871x_net_get_stats, + //.ndo_do_ioctl = r871x_mp_ioctl, +}; +#endif + +int hostapd_mode_init(_adapter *padapter) +{ + unsigned char mac[ETH_ALEN]; + struct hostapd_priv *phostapdpriv; + struct net_device *pnetdev; + + pnetdev = rtw_alloc_etherdev(sizeof(struct hostapd_priv)); + if (!pnetdev) + return -ENOMEM; + + //SET_MODULE_OWNER(pnetdev); + ether_setup(pnetdev); + + //pnetdev->type = ARPHRD_IEEE80211; + + phostapdpriv = rtw_netdev_priv(pnetdev); + phostapdpriv->pmgnt_netdev = pnetdev; + phostapdpriv->padapter= padapter; + padapter->phostapdpriv = phostapdpriv; + + //pnetdev->init = NULL; + +#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29)) + + DBG_871X("register rtl871x_mgnt_netdev_ops to netdev_ops\n"); + + pnetdev->netdev_ops = &rtl871x_mgnt_netdev_ops; + +#else + + pnetdev->open = mgnt_netdev_open; + + pnetdev->stop = mgnt_netdev_close; + + pnetdev->hard_start_xmit = mgnt_xmit_entry; + + //pnetdev->set_mac_address = r871x_net_set_mac_address; + + //pnetdev->get_stats = r871x_net_get_stats; + + //pnetdev->do_ioctl = r871x_mp_ioctl; + +#endif + + pnetdev->watchdog_timeo = HZ; /* 1 second timeout */ + + //pnetdev->wireless_handlers = NULL; + +#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX + pnetdev->features |= NETIF_F_IP_CSUM; +#endif + + + + if(dev_alloc_name(pnetdev,"mgnt.wlan%d") < 0) + { + DBG_871X("hostapd_mode_init(): dev_alloc_name, fail! \n"); + } + + + //SET_NETDEV_DEV(pnetdev, pintfpriv->udev); + + + mac[0]=0x00; + mac[1]=0xe0; + mac[2]=0x4c; + mac[3]=0x87; + mac[4]=0x11; + mac[5]=0x12; + + _rtw_memcpy(pnetdev->dev_addr, mac, ETH_ALEN); + + + netif_carrier_off(pnetdev); + + + /* Tell the network stack we exist */ + if (register_netdev(pnetdev) != 0) + { + DBG_871X("hostapd_mode_init(): register_netdev fail!\n"); + + if(pnetdev) + { + rtw_free_netdev(pnetdev); + } + } + + return 0; + +} + +void hostapd_mode_unload(_adapter *padapter) +{ + struct hostapd_priv *phostapdpriv = padapter->phostapdpriv; + struct net_device *pnetdev = phostapdpriv->pmgnt_netdev; + + unregister_netdev(pnetdev); + rtw_free_netdev(pnetdev); + +} + +#endif +#endif + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/os_intfs.c b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/os_intfs.c new file mode 100644 index 000000000..7347a7fae --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/os_intfs.c @@ -0,0 +1,3935 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _OS_INTFS_C_ + +#include +#include + +#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) + +#error "Shall be Linux or Windows, but not both!\n" + +#endif + + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Realtek Wireless Lan Driver"); +MODULE_AUTHOR("Realtek Semiconductor Corp."); +MODULE_VERSION(DRIVERVERSION); + +/* module param defaults */ +int rtw_chip_version = 0x00; +int rtw_rfintfs = HWPI; +int rtw_lbkmode = 0;//RTL8712_AIR_TRX; + + +int rtw_network_mode = Ndis802_11IBSS;//Ndis802_11Infrastructure;//infra, ad-hoc, auto +//NDIS_802_11_SSID ssid; +int rtw_channel = 1;//ad-hoc support requirement +int rtw_wireless_mode = WIRELESS_MODE_MAX; +int rtw_vrtl_carrier_sense = AUTO_VCS; +int rtw_vcs_type = RTS_CTS;//* +int rtw_rts_thresh = 2347;//* +int rtw_frag_thresh = 2346;//* +int rtw_preamble = PREAMBLE_LONG;//long, short, auto +int rtw_scan_mode = 1;//active, passive +int rtw_adhoc_tx_pwr = 1; +int rtw_soft_ap = 0; +//int smart_ps = 1; +#ifdef CONFIG_POWER_SAVING +int rtw_power_mgnt = PS_MODE_MAX; +#ifdef CONFIG_IPS_LEVEL_2 +int rtw_ips_mode = IPS_LEVEL_2; +#else +int rtw_ips_mode = IPS_NORMAL; +#endif +#else +int rtw_power_mgnt = PS_MODE_ACTIVE; +int rtw_ips_mode = IPS_NONE; +#endif +module_param(rtw_ips_mode, int, 0644); +MODULE_PARM_DESC(rtw_ips_mode,"The default IPS mode"); + +int rtw_smart_ps = 2; + +int rtw_check_fw_ps = 1; + +#ifdef CONFIG_TX_EARLY_MODE +int rtw_early_mode=1; +#endif + +int rtw_usb_rxagg_mode = 2;//USB_RX_AGG_DMA =1,USB_RX_AGG_USB=2 +module_param(rtw_usb_rxagg_mode, int, 0644); + +int rtw_radio_enable = 1; +int rtw_long_retry_lmt = 7; +int rtw_short_retry_lmt = 7; +int rtw_busy_thresh = 40; +//int qos_enable = 0; //* +int rtw_ack_policy = NORMAL_ACK; + +int rtw_mp_mode = 0; + +#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR) +uint rtw_mp_customer_str = 0; +module_param(rtw_mp_customer_str, uint, 0644); +MODULE_PARM_DESC(rtw_mp_customer_str, "Whether or not to enable customer str support on MP mode"); +#endif + +int rtw_software_encrypt = 0; +int rtw_software_decrypt = 0; + +int rtw_acm_method = 0;// 0:By SW 1:By HW. + +int rtw_wmm_enable = 1;// default is set to enable the wmm. +int rtw_uapsd_enable = 0; +int rtw_uapsd_max_sp = NO_LIMIT; +int rtw_uapsd_acbk_en = 0; +int rtw_uapsd_acbe_en = 0; +int rtw_uapsd_acvi_en = 0; +int rtw_uapsd_acvo_en = 0; +#ifdef CONFIG_RTL8814A +int rtw_pwrtrim_enable = 2; /* disable kfree , rename to power trim disable */ +#else +int rtw_pwrtrim_enable = 0; /* Default Enalbe power trim by efuse config */ +#endif +#ifdef CONFIG_80211N_HT +int rtw_ht_enable = 1; +// 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160MHz, 4: 80+80MHz +// 2.4G use bit 0 ~ 3, 5G use bit 4 ~ 7 +// 0x21 means enable 2.4G 40MHz & 5G 80MHz +int rtw_bw_mode = 0x21; +int rtw_ampdu_enable = 1;//for enable tx_ampdu ,// 0: disable, 0x1:enable +int rtw_rx_stbc = 1;// 0: disable, bit(0):enable 2.4g, bit(1):enable 5g, default is set to enable 2.4GHZ for IOT issue with bufflao's AP at 5GHZ +int rtw_ampdu_amsdu = 0;// 0: disabled, 1:enabled, 2:auto . There is an IOT issu with DLINK DIR-629 when the flag turn on +// Short GI support Bit Map +// BIT0 - 20MHz, 0: non-support, 1: support +// BIT1 - 40MHz, 0: non-support, 1: support +// BIT2 - 80MHz, 0: non-support, 1: support +// BIT3 - 160MHz, 0: non-support, 1: support +int rtw_short_gi = 0xf; +// BIT0: Enable VHT LDPC Rx, BIT1: Enable VHT LDPC Tx, BIT4: Enable HT LDPC Rx, BIT5: Enable HT LDPC Tx +int rtw_ldpc_cap = 0x00; +// BIT0: Enable VHT STBC Rx, BIT1: Enable VHT STBC Tx, BIT4: Enable HT STBC Rx, BIT5: Enable HT STBC Tx +int rtw_stbc_cap = 0x13; +// BIT0: Enable VHT Beamformer, BIT1: Enable VHT Beamformee, BIT4: Enable HT Beamformer, BIT5: Enable HT Beamformee +int rtw_beamform_cap = 0x2; +int rtw_bfer_rf_number = 0; /*BeamformerCapRfNum Rf path number, 0 for auto, others for manual*/ +int rtw_bfee_rf_number = 0; /*BeamformeeCapRfNum Rf path number, 0 for auto, others for manual*/ + +#endif //CONFIG_80211N_HT + +#ifdef CONFIG_80211AC_VHT +int rtw_vht_enable = 1; //0:disable, 1:enable, 2:force auto enable +int rtw_ampdu_factor = 7; +int rtw_vht_rate_sel = 0; +#endif //CONFIG_80211AC_VHT + +int rtw_lowrate_two_xmit = 1;//Use 2 path Tx to transmit MCS0~7 and legacy mode + +//int rf_config = RF_1T2R; // 1T2R +int rtw_rf_config = RF_MAX_TYPE; //auto + +int rtw_low_power = 0; +#ifdef CONFIG_WIFI_TEST +int rtw_wifi_spec = 1;//for wifi test +#else +int rtw_wifi_spec = 0; +#endif + +int rtw_special_rf_path = 0; //0: 2T2R ,1: only turn on path A 1T1R + +char rtw_country_unspecified[] = {0xFF, 0xFF, 0x00}; +char *rtw_country_code = rtw_country_unspecified; +module_param(rtw_country_code, charp, 0644); +MODULE_PARM_DESC(rtw_country_code, "The default country code (in alpha2)"); + +int rtw_channel_plan = RTW_CHPLAN_MAX; +module_param(rtw_channel_plan, int, 0644); +MODULE_PARM_DESC(rtw_channel_plan, "The default chplan ID when rtw_alpha2 is not specified or valid"); + +/*if concurrent softap + p2p(GO) is needed, this param lets p2p response full channel list. +But Softap must be SHUT DOWN once P2P decide to set up connection and become a GO.*/ +#ifdef CONFIG_FULL_CH_IN_P2P_HANDSHAKE +int rtw_full_ch_in_p2p_handshake = 1; /* reply full channel list*/ +#else +int rtw_full_ch_in_p2p_handshake = 0; /* reply only softap channel*/ +#endif + +#ifdef CONFIG_BT_COEXIST +int rtw_btcoex_enable = 1; +module_param(rtw_btcoex_enable, int, 0644); +MODULE_PARM_DESC(rtw_btcoex_enable, "Enable BT co-existence mechanism"); +int rtw_bt_iso = 2;// 0:Low, 1:High, 2:From Efuse +int rtw_bt_sco = 3;// 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter, 4.Busy, 5.OtherBusy +int rtw_bt_ampdu =1 ;// 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. +int rtw_ant_num = -1; // <0: undefined, >0: Antenna number +module_param(rtw_ant_num, int, 0644); +MODULE_PARM_DESC(rtw_ant_num, "Antenna number setting"); +#endif + +int rtw_AcceptAddbaReq = _TRUE;// 0:Reject AP's Add BA req, 1:Accept AP's Add BA req. + +int rtw_antdiv_cfg = 2; // 0:OFF , 1:ON, 2:decide by Efuse config +int rtw_antdiv_type = 0 ; //0:decide by efuse 1: for 88EE, 1Tx and 1RxCG are diversity.(2 Ant with SPDT), 2: for 88EE, 1Tx and 2Rx are diversity.( 2 Ant, Tx and RxCG are both on aux port, RxCS is on main port ), 3: for 88EE, 1Tx and 1RxCG are fixed.(1Ant, Tx and RxCG are both on aux port) + +int rtw_switch_usb3 = _FALSE; /* _FALSE: doesn't switch, _TRUE: switch from usb2.0 to usb 3.0 */ + +#ifdef CONFIG_USB_AUTOSUSPEND +int rtw_enusbss = 1;//0:disable,1:enable +#else +int rtw_enusbss = 0;//0:disable,1:enable +#endif + +int rtw_hwpdn_mode=2;//0:disable,1:enable,2: by EFUSE config + +#ifdef CONFIG_HW_PWRP_DETECTION +int rtw_hwpwrp_detect = 1; +#else +int rtw_hwpwrp_detect = 0; //HW power ping detect 0:disable , 1:enable +#endif + +#ifdef CONFIG_USB_HCI +int rtw_hw_wps_pbc = 1; +#else +int rtw_hw_wps_pbc = 0; +#endif + +#ifdef CONFIG_TX_MCAST2UNI +int rtw_mc2u_disable = 0; +#endif // CONFIG_TX_MCAST2UNI + +#ifdef CONFIG_80211D +int rtw_80211d = 0; +#endif + +#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV +int rtw_force_ant = 2;//0 :normal, 1:Main ant, 2:Aux ant +int rtw_force_igi =0;//0 :normal +module_param(rtw_force_ant, int, 0644); +module_param(rtw_force_igi, int, 0644); +#endif + +#ifdef CONFIG_QOS_OPTIMIZATION +int rtw_qos_opt_enable=1;//0: disable,1:enable +#else +int rtw_qos_opt_enable=0;//0: disable,1:enable +#endif +module_param(rtw_qos_opt_enable,int,0644); + +#ifdef CONFIG_AUTO_CHNL_SEL_NHM +int rtw_acs_mode = 1; /*0:disable, 1:enable*/ +module_param(rtw_acs_mode, int, 0644); + +int rtw_acs_auto_scan = 0; /*0:disable, 1:enable*/ +module_param(rtw_acs_auto_scan, int, 0644); + +#endif + +char* ifname = "wlan%d"; +module_param(ifname, charp, 0644); +MODULE_PARM_DESC(ifname, "The default name to allocate for first interface"); + +#ifdef CONFIG_PLATFORM_ANDROID +char* if2name = "p2p%d"; +#else //CONFIG_PLATFORM_ANDROID +char* if2name = "wlan%d"; +#endif //CONFIG_PLATFORM_ANDROID +module_param(if2name, charp, 0644); +MODULE_PARM_DESC(if2name, "The default name to allocate for second interface"); + +char* rtw_initmac = 0; // temp mac address if users want to use instead of the mac address in Efuse + +#ifdef CONFIG_MULTI_VIR_IFACES +int rtw_ext_iface_num = 1;//primary/secondary iface is excluded +module_param(rtw_ext_iface_num, int, 0644); +#endif //CONFIG_MULTI_VIR_IFACES + +module_param(rtw_pwrtrim_enable, int, 0644); +module_param(rtw_initmac, charp, 0644); +module_param(rtw_special_rf_path, int, 0644); +module_param(rtw_chip_version, int, 0644); +module_param(rtw_rfintfs, int, 0644); +module_param(rtw_lbkmode, int, 0644); +module_param(rtw_network_mode, int, 0644); +module_param(rtw_channel, int, 0644); +module_param(rtw_mp_mode, int, 0644); +module_param(rtw_wmm_enable, int, 0644); +module_param(rtw_vrtl_carrier_sense, int, 0644); +module_param(rtw_vcs_type, int, 0644); +module_param(rtw_busy_thresh, int, 0644); + +#ifdef CONFIG_80211N_HT +module_param(rtw_ht_enable, int, 0644); +module_param(rtw_bw_mode, int, 0644); +module_param(rtw_ampdu_enable, int, 0644); +module_param(rtw_rx_stbc, int, 0644); +module_param(rtw_ampdu_amsdu, int, 0644); +#endif //CONFIG_80211N_HT +#ifdef CONFIG_80211AC_VHT +module_param(rtw_vht_enable, int, 0644); +#endif //CONFIG_80211AC_VHT +#ifdef CONFIG_BEAMFORMING +module_param(rtw_beamform_cap, int, 0644); +#endif +module_param(rtw_lowrate_two_xmit, int, 0644); + +module_param(rtw_rf_config, int, 0644); +module_param(rtw_power_mgnt, int, 0644); +module_param(rtw_smart_ps, int, 0644); +module_param(rtw_low_power, int, 0644); +module_param(rtw_wifi_spec, int, 0644); + +module_param(rtw_full_ch_in_p2p_handshake, int, 0644); +module_param(rtw_antdiv_cfg, int, 0644); +module_param(rtw_antdiv_type, int, 0644); + +module_param(rtw_switch_usb3, int, 0644); + +module_param(rtw_enusbss, int, 0644); +module_param(rtw_hwpdn_mode, int, 0644); +module_param(rtw_hwpwrp_detect, int, 0644); + +module_param(rtw_hw_wps_pbc, int, 0644); + +#ifdef CONFIG_TX_EARLY_MODE +module_param(rtw_early_mode, int, 0644); +#endif +#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE +char *rtw_adaptor_info_caching_file_path= "/data/misc/wifi/rtw_cache"; +module_param(rtw_adaptor_info_caching_file_path, charp, 0644); +MODULE_PARM_DESC(rtw_adaptor_info_caching_file_path, "The path of adapter info cache file"); +#endif //CONFIG_ADAPTOR_INFO_CACHING_FILE + +#ifdef CONFIG_LAYER2_ROAMING +uint rtw_max_roaming_times=2; +module_param(rtw_max_roaming_times, uint, 0644); +MODULE_PARM_DESC(rtw_max_roaming_times,"The max roaming times to try"); +#endif //CONFIG_LAYER2_ROAMING + +#ifdef CONFIG_IOL +int rtw_fw_iol=1; +module_param(rtw_fw_iol, int, 0644); +MODULE_PARM_DESC(rtw_fw_iol, "FW IOL. 0:Disable, 1:enable, 2:by usb speed"); +#endif //CONFIG_IOL + +#ifdef CONFIG_FILE_FWIMG +char *rtw_fw_file_path = "/system/etc/firmware/rtlwifi/FW_NIC.BIN"; +module_param(rtw_fw_file_path, charp, 0644); +MODULE_PARM_DESC(rtw_fw_file_path, "The path of fw image"); + +char *rtw_fw_wow_file_path = "/system/etc/firmware/rtlwifi/FW_WoWLAN.BIN"; +module_param(rtw_fw_wow_file_path, charp, 0644); +MODULE_PARM_DESC(rtw_fw_wow_file_path, "The path of fw for Wake on Wireless image"); + +#ifdef CONFIG_MP_INCLUDED +char *rtw_fw_mp_bt_file_path = ""; +module_param(rtw_fw_mp_bt_file_path, charp, 0644); +MODULE_PARM_DESC(rtw_fw_mp_bt_file_path, "The path of fw for MP-BT image"); +#endif // CONFIG_MP_INCLUDED +#endif // CONFIG_FILE_FWIMG + +#ifdef CONFIG_TX_MCAST2UNI +module_param(rtw_mc2u_disable, int, 0644); +#endif // CONFIG_TX_MCAST2UNI + +#ifdef CONFIG_80211D +module_param(rtw_80211d, int, 0644); +MODULE_PARM_DESC(rtw_80211d, "Enable 802.11d mechanism"); +#endif + +uint rtw_notch_filter = RTW_NOTCH_FILTER; +module_param(rtw_notch_filter, uint, 0644); +MODULE_PARM_DESC(rtw_notch_filter, "0:Disable, 1:Enable, 2:Enable only for P2P"); + +uint rtw_hiq_filter = CONFIG_RTW_HIQ_FILTER; +module_param(rtw_hiq_filter, uint, 0644); +MODULE_PARM_DESC(rtw_hiq_filter, "0:allow all, 1:allow special, 2:deny all"); + +uint rtw_adaptivity_en = CONFIG_RTW_ADAPTIVITY_EN; +module_param(rtw_adaptivity_en, uint, 0644); +MODULE_PARM_DESC(rtw_adaptivity_en, "0:disable, 1:enable"); + +uint rtw_adaptivity_mode = CONFIG_RTW_ADAPTIVITY_MODE; +module_param(rtw_adaptivity_mode, uint, 0644); +MODULE_PARM_DESC(rtw_adaptivity_mode, "0:normal, 1:carrier sense"); + +uint rtw_adaptivity_dml = CONFIG_RTW_ADAPTIVITY_DML; +module_param(rtw_adaptivity_dml, uint, 0644); +MODULE_PARM_DESC(rtw_adaptivity_dml, "0:disable, 1:enable"); + +uint rtw_adaptivity_dc_backoff = CONFIG_RTW_ADAPTIVITY_DC_BACKOFF; +module_param(rtw_adaptivity_dc_backoff, uint, 0644); +MODULE_PARM_DESC(rtw_adaptivity_dc_backoff, "DC backoff for Adaptivity"); + +int rtw_adaptivity_th_l2h_ini = CONFIG_RTW_ADAPTIVITY_TH_L2H_INI; +module_param(rtw_adaptivity_th_l2h_ini, int, 0644); +MODULE_PARM_DESC(rtw_adaptivity_th_l2h_ini, "TH_L2H_ini for Adaptivity"); + +int rtw_adaptivity_th_edcca_hl_diff = CONFIG_RTW_ADAPTIVITY_TH_EDCCA_HL_DIFF; +module_param(rtw_adaptivity_th_edcca_hl_diff, int, 0644); +MODULE_PARM_DESC(rtw_adaptivity_th_edcca_hl_diff, "TH_EDCCA_HL_diff for Adaptivity"); + +uint rtw_amplifier_type_2g = CONFIG_RTW_AMPLIFIER_TYPE_2G; +module_param(rtw_amplifier_type_2g, uint, 0644); +MODULE_PARM_DESC(rtw_amplifier_type_2g, "BIT3:2G ext-PA, BIT4:2G ext-LNA"); + +uint rtw_amplifier_type_5g = CONFIG_RTW_AMPLIFIER_TYPE_5G; +module_param(rtw_amplifier_type_5g, uint, 0644); +MODULE_PARM_DESC(rtw_amplifier_type_5g, "BIT6:5G ext-PA, BIT7:5G ext-LNA"); + +uint rtw_RFE_type = CONFIG_RTW_RFE_TYPE; +module_param(rtw_RFE_type, uint, 0644); +MODULE_PARM_DESC(rtw_RFE_type, "default init value:64"); + +uint rtw_GLNA_type = CONFIG_RTW_GLNA_TYPE; +module_param(rtw_GLNA_type, uint, 0644); +MODULE_PARM_DESC(rtw_GLNA_type, "default init value:0"); + +uint rtw_TxBBSwing_2G = 0xFF; +module_param(rtw_TxBBSwing_2G, uint, 0644); +MODULE_PARM_DESC(rtw_TxBBSwing_2G, "default init value:0xFF"); + +uint rtw_TxBBSwing_5G = 0xFF; +module_param(rtw_TxBBSwing_5G, uint, 0644); +MODULE_PARM_DESC(rtw_TxBBSwing_5G, "default init value:0xFF"); + +uint rtw_OffEfuseMask = 0; +module_param(rtw_OffEfuseMask, uint, 0644); +MODULE_PARM_DESC(rtw_OffEfuseMask, "default open Efuse Mask value:0"); + +uint rtw_FileMaskEfuse = 0; +module_param(rtw_FileMaskEfuse, uint, 0644); +MODULE_PARM_DESC(rtw_FileMaskEfuse, "default drv Mask Efuse value:0"); + +uint rtw_pll_ref_clk_sel = CONFIG_RTW_PLL_REF_CLK_SEL; +module_param(rtw_pll_ref_clk_sel, uint, 0644); +MODULE_PARM_DESC(rtw_pll_ref_clk_sel, "force pll_ref_clk_sel, 0xF:use autoload value"); + +#if defined(CONFIG_CALIBRATE_TX_POWER_BY_REGULATORY) //eFuse: Regulatory selection=1 +int rtw_tx_pwr_lmt_enable = 1; +int rtw_tx_pwr_by_rate = 1; +#elif defined(CONFIG_CALIBRATE_TX_POWER_TO_MAX)//eFuse: Regulatory selection=0 +int rtw_tx_pwr_lmt_enable = 0; +int rtw_tx_pwr_by_rate = 1; +#else //eFuse: Regulatory selection=2 +#ifdef CONFIG_PCI_HCI +int rtw_tx_pwr_lmt_enable = 2; // 2- Depend on efuse +int rtw_tx_pwr_by_rate = 2;// 2- Depend on efuse +#else // USB & SDIO +int rtw_tx_pwr_lmt_enable = 0; +int rtw_tx_pwr_by_rate = 0; +#endif +#endif + +module_param(rtw_tx_pwr_lmt_enable, int, 0644); +MODULE_PARM_DESC(rtw_tx_pwr_lmt_enable,"0:Disable, 1:Enable, 2: Depend on efuse"); + +module_param(rtw_tx_pwr_by_rate, int, 0644); +MODULE_PARM_DESC(rtw_tx_pwr_by_rate,"0:Disable, 1:Enable, 2: Depend on efuse"); + +static int rtw_target_tx_pwr_2g_a[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_A; +static int rtw_target_tx_pwr_2g_a_num = 0; +module_param_array(rtw_target_tx_pwr_2g_a, int, &rtw_target_tx_pwr_2g_a_num, 0644); +MODULE_PARM_DESC(rtw_target_tx_pwr_2g_a, "2.4G target tx power (unit:dBm) of RF path A for each rate section, should match the real calibrate power, -1: undefined"); + +static int rtw_target_tx_pwr_2g_b[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_B; +static int rtw_target_tx_pwr_2g_b_num = 0; +module_param_array(rtw_target_tx_pwr_2g_b, int, &rtw_target_tx_pwr_2g_b_num, 0644); +MODULE_PARM_DESC(rtw_target_tx_pwr_2g_b, "2.4G target tx power (unit:dBm) of RF path B for each rate section, should match the real calibrate power, -1: undefined"); + +static int rtw_target_tx_pwr_2g_c[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_C; +static int rtw_target_tx_pwr_2g_c_num = 0; +module_param_array(rtw_target_tx_pwr_2g_c, int, &rtw_target_tx_pwr_2g_c_num, 0644); +MODULE_PARM_DESC(rtw_target_tx_pwr_2g_c, "2.4G target tx power (unit:dBm) of RF path C for each rate section, should match the real calibrate power, -1: undefined"); + +static int rtw_target_tx_pwr_2g_d[RATE_SECTION_NUM] = CONFIG_RTW_TARGET_TX_PWR_2G_D; +static int rtw_target_tx_pwr_2g_d_num = 0; +module_param_array(rtw_target_tx_pwr_2g_d, int, &rtw_target_tx_pwr_2g_d_num, 0644); +MODULE_PARM_DESC(rtw_target_tx_pwr_2g_d, "2.4G target tx power (unit:dBm) of RF path D for each rate section, should match the real calibrate power, -1: undefined"); + +#ifdef CONFIG_IEEE80211_BAND_5GHZ +static int rtw_target_tx_pwr_5g_a[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_A; +static int rtw_target_tx_pwr_5g_a_num = 0; +module_param_array(rtw_target_tx_pwr_5g_a, int, &rtw_target_tx_pwr_5g_a_num, 0644); +MODULE_PARM_DESC(rtw_target_tx_pwr_5g_a, "5G target tx power (unit:dBm) of RF path A for each rate section, should match the real calibrate power, -1: undefined"); + +static int rtw_target_tx_pwr_5g_b[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_B; +static int rtw_target_tx_pwr_5g_b_num = 0; +module_param_array(rtw_target_tx_pwr_5g_b, int, &rtw_target_tx_pwr_5g_b_num, 0644); +MODULE_PARM_DESC(rtw_target_tx_pwr_5g_b, "5G target tx power (unit:dBm) of RF path B for each rate section, should match the real calibrate power, -1: undefined"); + +static int rtw_target_tx_pwr_5g_c[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_C; +static int rtw_target_tx_pwr_5g_c_num = 0; +module_param_array(rtw_target_tx_pwr_5g_c, int, &rtw_target_tx_pwr_5g_c_num, 0644); +MODULE_PARM_DESC(rtw_target_tx_pwr_5g_c, "5G target tx power (unit:dBm) of RF path C for each rate section, should match the real calibrate power, -1: undefined"); + +static int rtw_target_tx_pwr_5g_d[RATE_SECTION_NUM - 1] = CONFIG_RTW_TARGET_TX_PWR_5G_D; +static int rtw_target_tx_pwr_5g_d_num = 0; +module_param_array(rtw_target_tx_pwr_5g_d, int, &rtw_target_tx_pwr_5g_d_num, 0644); +MODULE_PARM_DESC(rtw_target_tx_pwr_5g_d, "5G target tx power (unit:dBm) of RF path D for each rate section, should match the real calibrate power, -1: undefined"); +#endif /* CONFIG_IEEE80211_BAND_5GHZ */ + +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE +char *rtw_phy_file_path = REALTEK_CONFIG_PATH; +module_param(rtw_phy_file_path, charp, 0644); +MODULE_PARM_DESC(rtw_phy_file_path, "The path of phy parameter"); +// PHY FILE Bit Map +// BIT0 - MAC, 0: non-support, 1: support +// BIT1 - BB, 0: non-support, 1: support +// BIT2 - BB_PG, 0: non-support, 1: support +// BIT3 - BB_MP, 0: non-support, 1: support +// BIT4 - RF, 0: non-support, 1: support +// BIT5 - RF_TXPWR_TRACK, 0: non-support, 1: support +// BIT6 - RF_TXPWR_LMT, 0: non-support, 1: support +int rtw_load_phy_file = (BIT2|BIT6); +module_param(rtw_load_phy_file, int, 0644); +MODULE_PARM_DESC(rtw_load_phy_file,"PHY File Bit Map"); +int rtw_decrypt_phy_file = 0; +module_param(rtw_decrypt_phy_file, int, 0644); +MODULE_PARM_DESC(rtw_decrypt_phy_file,"Enable Decrypt PHY File"); +#endif + +int _netdev_open(struct net_device *pnetdev); +int netdev_open (struct net_device *pnetdev); +static int netdev_close (struct net_device *pnetdev); +#ifdef CONFIG_PLATFORM_INTEL_BYT +extern int rtw_sdio_set_power(int on); +#endif //CONFIG_PLATFORM_INTEL_BYT + +void rtw_regsty_load_target_tx_power(struct registry_priv *regsty) +{ + int path, rs; + int *target_tx_pwr; + + for (path = RF_PATH_A; path < RF_PATH_MAX; path++) { + if (path == RF_PATH_A) + target_tx_pwr = rtw_target_tx_pwr_2g_a; + else if (path == RF_PATH_B) + target_tx_pwr = rtw_target_tx_pwr_2g_b; + else if (path == RF_PATH_C) + target_tx_pwr = rtw_target_tx_pwr_2g_c; + else if (path == RF_PATH_D) + target_tx_pwr = rtw_target_tx_pwr_2g_d; + + for (rs = CCK; rs < RATE_SECTION_NUM; rs++) + regsty->target_tx_pwr_2g[path][rs] = target_tx_pwr[rs]; + } + +#ifdef CONFIG_IEEE80211_BAND_5GHZ + for (path = RF_PATH_A; path < RF_PATH_MAX; path++) { + if (path == RF_PATH_A) + target_tx_pwr = rtw_target_tx_pwr_5g_a; + else if (path == RF_PATH_B) + target_tx_pwr = rtw_target_tx_pwr_5g_b; + else if (path == RF_PATH_C) + target_tx_pwr = rtw_target_tx_pwr_5g_c; + else if (path == RF_PATH_D) + target_tx_pwr = rtw_target_tx_pwr_5g_d; + + for (rs = OFDM; rs < RATE_SECTION_NUM; rs++) + regsty->target_tx_pwr_5g[path][rs - 1] = target_tx_pwr[rs - 1]; + } +#endif /* CONFIG_IEEE80211_BAND_5GHZ */ +} + +uint loadparam(_adapter *padapter) +{ + uint status = _SUCCESS; + struct registry_priv *registry_par = &padapter->registrypriv; + +_func_enter_; + + registry_par->chip_version = (u8)rtw_chip_version; + registry_par->rfintfs = (u8)rtw_rfintfs; + registry_par->lbkmode = (u8)rtw_lbkmode; + //registry_par->hci = (u8)hci; + registry_par->network_mode = (u8)rtw_network_mode; + + _rtw_memcpy(registry_par->ssid.Ssid, "ANY", 3); + registry_par->ssid.SsidLength = 3; + + registry_par->channel = (u8)rtw_channel; + registry_par->wireless_mode = (u8)rtw_wireless_mode; + + if (IsSupported24G(registry_par->wireless_mode) && (!IsSupported5G(registry_par->wireless_mode)) + && (registry_par->channel > 14)) { + registry_par->channel = 1; + } + else if (IsSupported5G(registry_par->wireless_mode) && (!IsSupported24G(registry_par->wireless_mode)) + && (registry_par->channel <= 14)) { + registry_par->channel = 36; + } + + registry_par->vrtl_carrier_sense = (u8)rtw_vrtl_carrier_sense ; + registry_par->vcs_type = (u8)rtw_vcs_type; + registry_par->rts_thresh=(u16)rtw_rts_thresh; + registry_par->frag_thresh=(u16)rtw_frag_thresh; + registry_par->preamble = (u8)rtw_preamble; + registry_par->scan_mode = (u8)rtw_scan_mode; + registry_par->adhoc_tx_pwr = (u8)rtw_adhoc_tx_pwr; + registry_par->soft_ap= (u8)rtw_soft_ap; + registry_par->smart_ps = (u8)rtw_smart_ps; + registry_par->check_fw_ps = (u8)rtw_check_fw_ps; + registry_par->power_mgnt = (u8)rtw_power_mgnt; + registry_par->ips_mode = (u8)rtw_ips_mode; + registry_par->radio_enable = (u8)rtw_radio_enable; + registry_par->long_retry_lmt = (u8)rtw_long_retry_lmt; + registry_par->short_retry_lmt = (u8)rtw_short_retry_lmt; + registry_par->busy_thresh = (u16)rtw_busy_thresh; + //registry_par->qos_enable = (u8)rtw_qos_enable; + registry_par->ack_policy = (u8)rtw_ack_policy; + registry_par->mp_mode = (u8)rtw_mp_mode; +#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_RTW_CUSTOMER_STR) + registry_par->mp_customer_str = (u8)rtw_mp_customer_str; +#endif + registry_par->software_encrypt = (u8)rtw_software_encrypt; + registry_par->software_decrypt = (u8)rtw_software_decrypt; + + registry_par->acm_method = (u8)rtw_acm_method; + registry_par->usb_rxagg_mode = (u8)rtw_usb_rxagg_mode; + + //UAPSD + registry_par->wmm_enable = (u8)rtw_wmm_enable; + registry_par->uapsd_enable = (u8)rtw_uapsd_enable; + registry_par->uapsd_max_sp = (u8)rtw_uapsd_max_sp; + registry_par->uapsd_acbk_en = (u8)rtw_uapsd_acbk_en; + registry_par->uapsd_acbe_en = (u8)rtw_uapsd_acbe_en; + registry_par->uapsd_acvi_en = (u8)rtw_uapsd_acvi_en; + registry_par->uapsd_acvo_en = (u8)rtw_uapsd_acvo_en; + + registry_par->RegPwrTrimEnable = (u8)rtw_pwrtrim_enable; + +#ifdef CONFIG_80211N_HT + registry_par->ht_enable = (u8)rtw_ht_enable; + registry_par->bw_mode = (u8)rtw_bw_mode; + registry_par->ampdu_enable = (u8)rtw_ampdu_enable; + registry_par->rx_stbc = (u8)rtw_rx_stbc; + registry_par->ampdu_amsdu = (u8)rtw_ampdu_amsdu; + registry_par->short_gi = (u8)rtw_short_gi; + registry_par->ldpc_cap = (u8)rtw_ldpc_cap; + registry_par->stbc_cap = (u8)rtw_stbc_cap; + registry_par->beamform_cap = (u8)rtw_beamform_cap; + registry_par->beamformer_rf_num = (u8)rtw_bfer_rf_number; + registry_par->beamformee_rf_num = (u8)rtw_bfee_rf_number; +#endif + +#ifdef CONFIG_80211AC_VHT + registry_par->vht_enable = (u8)rtw_vht_enable; + registry_par->ampdu_factor = (u8)rtw_ampdu_factor; + registry_par->vht_rate_sel = (u8)rtw_vht_rate_sel; +#endif + +#ifdef CONFIG_TX_EARLY_MODE + registry_par->early_mode = (u8)rtw_early_mode; +#endif + registry_par->lowrate_two_xmit = (u8)rtw_lowrate_two_xmit; + registry_par->rf_config = (u8)rtw_rf_config; + registry_par->low_power = (u8)rtw_low_power; + + + registry_par->wifi_spec = (u8)rtw_wifi_spec; + + if (strlen(rtw_country_code) != 2 + || is_alpha(rtw_country_code[0]) == _FALSE + || is_alpha(rtw_country_code[1]) == _FALSE + ) { + if (rtw_country_code != rtw_country_unspecified) + DBG_871X_LEVEL(_drv_err_, "%s discard rtw_country_code not in alpha2\n", __func__); + _rtw_memset(registry_par->alpha2, 0xFF, 2); + } else + _rtw_memcpy(registry_par->alpha2, rtw_country_code, 2); + + registry_par->channel_plan = (u8)rtw_channel_plan; + registry_par->special_rf_path = (u8)rtw_special_rf_path; + + registry_par->full_ch_in_p2p_handshake = (u8)rtw_full_ch_in_p2p_handshake; +#ifdef CONFIG_BT_COEXIST + registry_par->btcoex = (u8)rtw_btcoex_enable; + registry_par->bt_iso = (u8)rtw_bt_iso; + registry_par->bt_sco = (u8)rtw_bt_sco; + registry_par->bt_ampdu = (u8)rtw_bt_ampdu; + registry_par->ant_num = (s8)rtw_ant_num; +#endif + + registry_par->bAcceptAddbaReq = (u8)rtw_AcceptAddbaReq; + + registry_par->antdiv_cfg = (u8)rtw_antdiv_cfg; + registry_par->antdiv_type = (u8)rtw_antdiv_type; + + registry_par->switch_usb3 = (u8)rtw_switch_usb3; + +#ifdef CONFIG_AUTOSUSPEND + registry_par->usbss_enable = (u8)rtw_enusbss;//0:disable,1:enable +#endif +#ifdef SUPPORT_HW_RFOFF_DETECTED + registry_par->hwpdn_mode = (u8)rtw_hwpdn_mode;//0:disable,1:enable,2:by EFUSE config + registry_par->hwpwrp_detect = (u8)rtw_hwpwrp_detect;//0:disable,1:enable +#endif + + registry_par->hw_wps_pbc = (u8)rtw_hw_wps_pbc; + +#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE + snprintf(registry_par->adaptor_info_caching_file_path, PATH_LENGTH_MAX, "%s", rtw_adaptor_info_caching_file_path); + registry_par->adaptor_info_caching_file_path[PATH_LENGTH_MAX-1]=0; +#endif + +#ifdef CONFIG_LAYER2_ROAMING + registry_par->max_roaming_times = (u8)rtw_max_roaming_times; +#ifdef CONFIG_INTEL_WIDI + registry_par->max_roaming_times = (u8)rtw_max_roaming_times + 2; +#endif // CONFIG_INTEL_WIDI +#endif + +#ifdef CONFIG_IOL + registry_par->fw_iol = rtw_fw_iol; +#endif + +#ifdef CONFIG_80211D + registry_par->enable80211d = (u8)rtw_80211d; +#endif + + snprintf(registry_par->ifname, 16, "%s", ifname); + snprintf(registry_par->if2name, 16, "%s", if2name); + + registry_par->notch_filter = (u8)rtw_notch_filter; + +#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV + registry_par->force_ant = (u8)rtw_force_ant; + registry_par->force_igi = (u8)rtw_force_igi; +#endif + +#ifdef CONFIG_MULTI_VIR_IFACES + registry_par->ext_iface_num = (u8)rtw_ext_iface_num; +#endif //CONFIG_MULTI_VIR_IFACES + + registry_par->pll_ref_clk_sel = (u8)rtw_pll_ref_clk_sel; + + registry_par->RegEnableTxPowerLimit = (u8)rtw_tx_pwr_lmt_enable; + registry_par->RegEnableTxPowerByRate = (u8)rtw_tx_pwr_by_rate; + + rtw_regsty_load_target_tx_power(registry_par); + + registry_par->RegPowerBase = 14; + registry_par->TxBBSwing_2G = (s8)rtw_TxBBSwing_2G; + registry_par->TxBBSwing_5G = (s8)rtw_TxBBSwing_5G; + registry_par->bEn_RFE = 1; + registry_par->RFE_Type = (u8)rtw_RFE_type; + registry_par->AmplifierType_2G = (u8)rtw_amplifier_type_2g; + registry_par->AmplifierType_5G = (u8)rtw_amplifier_type_5g; + registry_par->GLNA_Type = (u8)rtw_GLNA_type; +#ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + registry_par->load_phy_file = (u8)rtw_load_phy_file; + registry_par->RegDecryptCustomFile = (u8)rtw_decrypt_phy_file; +#endif + registry_par->qos_opt_enable = (u8)rtw_qos_opt_enable; + + registry_par->hiq_filter = (u8)rtw_hiq_filter; + + registry_par->adaptivity_en = (u8)rtw_adaptivity_en; + registry_par->adaptivity_mode = (u8)rtw_adaptivity_mode; + registry_par->adaptivity_dml = (u8)rtw_adaptivity_dml; + registry_par->adaptivity_dc_backoff = (u8)rtw_adaptivity_dc_backoff; + registry_par->adaptivity_th_l2h_ini = (s8)rtw_adaptivity_th_l2h_ini; + registry_par->adaptivity_th_edcca_hl_diff = (s8)rtw_adaptivity_th_edcca_hl_diff; + + registry_par->boffefusemask = (u8)rtw_OffEfuseMask; + registry_par->bFileMaskEfuse = (u8)rtw_FileMaskEfuse; +#ifdef CONFIG_AUTO_CHNL_SEL_NHM + registry_par->acs_mode = (u8)rtw_acs_mode; + registry_par->acs_auto_scan = (u8)rtw_acs_auto_scan; +#endif +_func_exit_; + + return status; +} + +/** + * rtw_net_set_mac_address + * This callback function is used for the Media Access Control address + * of each net_device needs to be changed. + * + * Arguments: + * @pnetdev: net_device pointer. + * @addr: new MAC address. + * + * Return: + * ret = 0: Permit to change net_device's MAC address. + * ret = -1 (Default): Operation not permitted. + * + * Auther: Arvin Liu + * Date: 2015/05/29 + */ +static int rtw_net_set_mac_address(struct net_device *pnetdev, void *addr) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct sockaddr *sa = (struct sockaddr *)addr; + int ret = -1; + + /* only the net_device is in down state to permit modifying mac addr */ + if ((pnetdev->flags & IFF_UP) == _TRUE) { + DBG_871X(FUNC_ADPT_FMT": The net_device's is not in down state\n" + , FUNC_ADPT_ARG(padapter)); + + return ret; + } + + /* if the net_device is linked, it's not permit to modify mac addr */ + if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) || + check_fwstate(pmlmepriv, _FW_LINKED) || + check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) { + DBG_871X(FUNC_ADPT_FMT": The net_device's is not idle currently\n" + , FUNC_ADPT_ARG(padapter)); + + return ret; + } + + /* check whether the input mac address is valid to permit modifying mac addr */ + if (rtw_check_invalid_mac_address(sa->sa_data, _FALSE) == _TRUE) { + DBG_871X(FUNC_ADPT_FMT": Invalid Mac Addr for "MAC_FMT"\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(sa->sa_data)); + + return ret; + } + + _rtw_memcpy(adapter_mac_addr(padapter), sa->sa_data, ETH_ALEN); /* set mac addr to adapter */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0)) + eth_hw_addr_set(pnetdev, sa->sa_data); +#else + _rtw_memcpy(pnetdev->dev_addr, sa->sa_data, ETH_ALEN); /* set mac addr to net_device */ +#endif + + rtw_ps_deny(padapter, PS_DENY_IOCTL); + LeaveAllPowerSaveModeDirect(padapter); /* leave PS mode for guaranteeing to access hw register successfully */ + rtw_hal_set_hwreg(padapter, HW_VAR_MAC_ADDR, sa->sa_data); /* set mac addr to mac register */ + rtw_ps_deny_cancel(padapter, PS_DENY_IOCTL); + + DBG_871X(FUNC_ADPT_FMT": Set Mac Addr to "MAC_FMT" Successfully\n" + , FUNC_ADPT_ARG(padapter), MAC_ARG(sa->sa_data)); + + ret = 0; + + return ret; +} + +static struct net_device_stats *rtw_net_get_stats(struct net_device *pnetdev) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + struct recv_priv *precvpriv = &(padapter->recvpriv); + + padapter->stats.tx_packets = pxmitpriv->tx_pkts;//pxmitpriv->tx_pkts++; + padapter->stats.rx_packets = precvpriv->rx_pkts;//precvpriv->rx_pkts++; + padapter->stats.tx_dropped = pxmitpriv->tx_drop; + padapter->stats.rx_dropped = precvpriv->rx_drop; + padapter->stats.tx_bytes = pxmitpriv->tx_bytes; + padapter->stats.rx_bytes = precvpriv->rx_bytes; + + return &padapter->stats; +} + +#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) +/* + * AC to queue mapping + * + * AC_VO -> queue 0 + * AC_VI -> queue 1 + * AC_BE -> queue 2 + * AC_BK -> queue 3 + */ +static const u16 rtw_1d_to_queue[8] = { 2, 3, 3, 2, 1, 1, 0, 0 }; + +/* Given a data frame determine the 802.1p/1d tag to use. */ +unsigned int rtw_classify8021d(struct sk_buff *skb) +{ + unsigned int dscp; + + /* skb->priority values from 256->263 are magic values to + * directly indicate a specific 802.1d priority. This is used + * to allow 802.1d priority to be passed directly in from VLAN + * tags, etc. + */ + if (skb->priority >= 256 && skb->priority <= 263) + return skb->priority - 256; + + switch (skb->protocol) { + case htons(ETH_P_IP): + dscp = ip_hdr(skb)->tos & 0xfc; + break; + default: + return 0; + } + + return dscp >> 5; +} + + +static u16 rtw_select_queue(struct net_device *dev, struct sk_buff *skb +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 13, 0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0) + , struct net_device *sb_dev +#else + , void *accel_priv +#endif +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0) && LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0) + , select_queue_fallback_t fallback +#endif + +#endif +) +{ + _adapter *padapter = rtw_netdev_priv(dev); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + skb->priority = rtw_classify8021d(skb); + + if(pmlmepriv->acm_mask != 0) + { + skb->priority = qos_acm(pmlmepriv->acm_mask, skb->priority); + } + + return rtw_1d_to_queue[skb->priority]; +} + +u16 rtw_recv_select_queue(struct sk_buff *skb) +{ + struct iphdr *piphdr; + unsigned int dscp; + u16 eth_type; + u32 priority; + u8 *pdata = skb->data; + + _rtw_memcpy(ð_type, pdata+(ETH_ALEN<<1), 2); + + switch (eth_type) { + case htons(ETH_P_IP): + + piphdr = (struct iphdr *)(pdata+ETH_HLEN); + + dscp = piphdr->tos & 0xfc; + + priority = dscp >> 5; + + break; + default: + priority = 0; + } + + return rtw_1d_to_queue[priority]; + +} + +#endif +static int rtw_ndev_notifier_call(struct notifier_block * nb, unsigned long state, void *ptr) +{ +#if (LINUX_VERSION_CODE>=KERNEL_VERSION(3,11,0)) + struct net_device *dev = netdev_notifier_info_to_dev(ptr); +#else + struct net_device *dev = ptr; +#endif + + if (dev == NULL) + return NOTIFY_DONE; + +#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29)) + if (dev->netdev_ops == NULL) + return NOTIFY_DONE; + + if (dev->netdev_ops->ndo_do_ioctl == NULL) + return NOTIFY_DONE; + + if (dev->netdev_ops->ndo_do_ioctl != rtw_ioctl) +#else + if (dev->do_ioctl == NULL) + return NOTIFY_DONE; + + if (dev->do_ioctl != rtw_ioctl) +#endif + return NOTIFY_DONE; + + DBG_871X_LEVEL(_drv_info_, FUNC_NDEV_FMT" state:%lu\n", FUNC_NDEV_ARG(dev), state); + + switch (state) { + case NETDEV_CHANGENAME: + rtw_adapter_proc_replace(dev); + break; + } + + return NOTIFY_DONE; +} + +static struct notifier_block rtw_ndev_notifier = { + .notifier_call = rtw_ndev_notifier_call, +}; + +int rtw_ndev_notifier_register(void) +{ + return register_netdevice_notifier(&rtw_ndev_notifier); +} + +void rtw_ndev_notifier_unregister(void) +{ + unregister_netdevice_notifier(&rtw_ndev_notifier); +} + + +int rtw_ndev_init(struct net_device *dev) +{ + _adapter *adapter = rtw_netdev_priv(dev); + + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" if%d mac_addr="MAC_FMT"\n" + , FUNC_ADPT_ARG(adapter), (adapter->iface_id+1), MAC_ARG(dev->dev_addr)); + strncpy(adapter->old_ifname, dev->name, IFNAMSIZ); + adapter->old_ifname[IFNAMSIZ-1] = '\0'; + rtw_adapter_proc_init(dev); + + return 0; +} + +void rtw_ndev_uninit(struct net_device *dev) +{ + _adapter *adapter = rtw_netdev_priv(dev); + + DBG_871X_LEVEL(_drv_always_, FUNC_ADPT_FMT" if%d\n" + , FUNC_ADPT_ARG(adapter), (adapter->iface_id+1)); + rtw_adapter_proc_deinit(dev); +} + +#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29)) +static const struct net_device_ops rtw_netdev_ops = { + .ndo_init = rtw_ndev_init, + .ndo_uninit = rtw_ndev_uninit, + .ndo_open = netdev_open, + .ndo_stop = netdev_close, + .ndo_start_xmit = rtw_xmit_entry, +#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) + .ndo_select_queue = rtw_select_queue, +#endif + .ndo_set_mac_address = rtw_net_set_mac_address, + .ndo_get_stats = rtw_net_get_stats, + .ndo_do_ioctl = rtw_ioctl, +}; +#endif + +int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname) +{ + _adapter *padapter = rtw_netdev_priv(pnetdev); + +#ifdef CONFIG_EASY_REPLACEMENT + struct net_device *TargetNetdev = NULL; + _adapter *TargetAdapter = NULL; + struct net *devnet = NULL; + + if(padapter->bDongle == 1) + { +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) + TargetNetdev = dev_get_by_name("wlan0"); +#else + #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) + devnet = pnetdev->nd_net; + #else + devnet = dev_net(pnetdev); + #endif + TargetNetdev = dev_get_by_name(devnet, "wlan0"); +#endif + if(TargetNetdev) { + DBG_871X("Force onboard module driver disappear !!!\n"); + TargetAdapter = rtw_netdev_priv(TargetNetdev); + TargetAdapter->DriverState = DRIVER_DISAPPEAR; + + padapter->pid[0] = TargetAdapter->pid[0]; + padapter->pid[1] = TargetAdapter->pid[1]; + padapter->pid[2] = TargetAdapter->pid[2]; + + dev_put(TargetNetdev); + unregister_netdev(TargetNetdev); + + padapter->DriverState = DRIVER_REPLACE_DONGLE; + } + } +#endif //CONFIG_EASY_REPLACEMENT + + if(dev_alloc_name(pnetdev, ifname) < 0) + { + RT_TRACE(_module_os_intfs_c_,_drv_err_,("dev_alloc_name, fail! \n")); + } + + netif_carrier_off(pnetdev); + //rtw_netif_stop_queue(pnetdev); + + return 0; +} + +void rtw_hook_if_ops(struct net_device *ndev) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) + ndev->netdev_ops = &rtw_netdev_ops; +#else + ndev->init = rtw_ndev_init; + ndev->uninit = rtw_ndev_uninit; + ndev->open = netdev_open; + ndev->stop = netdev_close; + ndev->hard_start_xmit = rtw_xmit_entry; + ndev->set_mac_address = rtw_net_set_mac_address; + ndev->get_stats = rtw_net_get_stats; + ndev->do_ioctl = rtw_ioctl; +#endif +} + +struct net_device *rtw_init_netdev(_adapter *old_padapter) +{ + _adapter *padapter; + struct net_device *pnetdev; + + RT_TRACE(_module_os_intfs_c_,_drv_info_,("+init_net_dev\n")); + + if(old_padapter != NULL) + pnetdev = rtw_alloc_etherdev_with_old_priv(sizeof(_adapter), (void *)old_padapter); + else + pnetdev = rtw_alloc_etherdev(sizeof(_adapter)); + + if (!pnetdev) + return NULL; + + padapter = rtw_netdev_priv(pnetdev); + padapter->pnetdev = pnetdev; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) + SET_MODULE_OWNER(pnetdev); +#endif + + rtw_hook_if_ops(pnetdev); + +#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX + pnetdev->features |= NETIF_F_IP_CSUM; +#endif + + //pnetdev->tx_timeout = NULL; + pnetdev->watchdog_timeo = HZ*3; /* 3 second timeout */ + +#ifdef CONFIG_WIRELESS_EXT + pnetdev->wireless_handlers = (struct iw_handler_def *)&rtw_handlers_def; +#endif + +#ifdef WIRELESS_SPY + //priv->wireless_data.spy_data = &priv->spy_data; + //pnetdev->wireless_data = &priv->wireless_data; +#endif + + return pnetdev; +} + +int rtw_os_ndev_alloc(_adapter *adapter) +{ + int ret = _FAIL; + struct net_device *ndev = NULL; + + ndev = rtw_init_netdev(adapter); + if (ndev == NULL) { + rtw_warn_on(1); + goto exit; + } + #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 0) + SET_NETDEV_DEV(ndev, dvobj_to_dev(adapter_to_dvobj(adapter))); + #endif + + #ifdef CONFIG_PCI_HCI + if (adapter_to_dvobj(adapter)->bdma64) + ndev->features |= NETIF_F_HIGHDMA; + ndev->irq = adapter_to_dvobj(adapter)->irq; + #endif + +#if defined(CONFIG_IOCTL_CFG80211) + if (rtw_cfg80211_ndev_res_alloc(adapter) != _SUCCESS) { + rtw_warn_on(1); + goto free_ndev; + } +#endif + + ret = _SUCCESS; + +free_ndev: + if (ret != _SUCCESS && ndev) + rtw_free_netdev(ndev); +exit: + return ret; +} + +void rtw_os_ndev_free(_adapter *adapter) +{ +#if defined(CONFIG_IOCTL_CFG80211) + rtw_cfg80211_ndev_res_free(adapter); +#endif + + if (adapter->pnetdev) { + rtw_free_netdev(adapter->pnetdev); + adapter->pnetdev = NULL; + } +} + +int rtw_os_ndev_register(_adapter *adapter, char *name) +{ + int ret = _SUCCESS; + struct net_device *ndev = adapter->pnetdev; + +#if defined(CONFIG_IOCTL_CFG80211) + if (rtw_cfg80211_ndev_res_register(adapter) != _SUCCESS) { + rtw_warn_on(1); + ret = _FAIL; + goto exit; + } +#endif + + /* alloc netdev name */ + rtw_init_netdev_name(ndev, name); + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0)) + eth_hw_addr_set(ndev, adapter_mac_addr(adapter)); +#else + _rtw_memcpy(ndev->dev_addr, adapter_mac_addr(adapter), ETH_ALEN); +#endif + + /* Tell the network stack we exist */ + if (register_netdev(ndev) != 0) { + DBG_871X(FUNC_NDEV_FMT" if%d Failed!\n", FUNC_NDEV_ARG(ndev), (adapter->iface_id+1)); + ret = _FAIL; + } + +#if defined(CONFIG_IOCTL_CFG80211) + if (ret != _SUCCESS) { + rtw_cfg80211_ndev_res_unregister(adapter); + #if !defined(RTW_SINGLE_WIPHY) + rtw_wiphy_unregister(adapter_to_wiphy(adapter)); + #endif + } +#endif + +exit: + return ret; +} + +void rtw_os_ndev_unregister(_adapter *adapter) +{ + struct net_device *netdev = NULL; + + if (adapter == NULL) + return; + + adapter->ndev_unregistering = 1; + + netdev = adapter->pnetdev; + +#if defined(CONFIG_IOCTL_CFG80211) + rtw_cfg80211_ndev_res_unregister(adapter); +#endif + + if ((adapter->DriverState != DRIVER_DISAPPEAR) && netdev) + unregister_netdev(netdev); /* will call netdev_close() */ + +#if defined(CONFIG_IOCTL_CFG80211) && !defined(RTW_SINGLE_WIPHY) + rtw_wiphy_unregister(adapter_to_wiphy(adapter)); +#endif + + adapter->ndev_unregistering = 0; +} + +/** + * rtw_os_ndev_init - Allocate and register OS layer net device and relating structures for @adapter + * @adapter: the adapter on which this function applies + * @name: the requesting net device name + * + * Returns: + * _SUCCESS or _FAIL + */ +int rtw_os_ndev_init(_adapter *adapter, char *name) +{ + int ret = _FAIL; + + if (rtw_os_ndev_alloc(adapter) != _SUCCESS) + goto exit; + + if (rtw_os_ndev_register(adapter, name) != _SUCCESS) + goto os_ndev_free; + + ret = _SUCCESS; + +os_ndev_free: + if (ret != _SUCCESS) + rtw_os_ndev_free(adapter); +exit: + return ret; +} + +/** + * rtw_os_ndev_deinit - Unregister and free OS layer net device and relating structures for @adapter + * @adapter: the adapter on which this function applies + */ +void rtw_os_ndev_deinit(_adapter *adapter) +{ + rtw_os_ndev_unregister(adapter); + rtw_os_ndev_free(adapter); +} + +int rtw_os_ndevs_alloc(struct dvobj_priv *dvobj) +{ + int i, status = _SUCCESS; + _adapter *adapter; + +#if defined(CONFIG_IOCTL_CFG80211) + if (rtw_cfg80211_dev_res_alloc(dvobj) != _SUCCESS) { + rtw_warn_on(1); + status = _FAIL; + goto exit; + } +#endif + + for (i = 0; i < dvobj->iface_nums; i++) { + + if (i >= IFACE_ID_MAX) { + DBG_871X_LEVEL(_drv_err_, "%s %d >= IFACE_ID_MAX\n", __func__, i); + rtw_warn_on(1); + continue; + } + + adapter = dvobj->padapters[i]; + if (adapter && !adapter->pnetdev) { + status = rtw_os_ndev_alloc(adapter); + if (status != _SUCCESS) { + rtw_warn_on(1); + break; + } + } + } + + if (status != _SUCCESS) { + for (; i >= 0; i--) { + adapter = dvobj->padapters[i]; + if (adapter && adapter->pnetdev) + rtw_os_ndev_free(adapter); + } + } + +#if defined(CONFIG_IOCTL_CFG80211) + if (status != _SUCCESS) + rtw_cfg80211_dev_res_free(dvobj); +#endif +exit: + return status; +} + +void rtw_os_ndevs_free(struct dvobj_priv *dvobj) +{ + int i; + _adapter *adapter = NULL; + + for (i = 0; i < dvobj->iface_nums; i++) { + + if (i >= IFACE_ID_MAX) { + DBG_871X_LEVEL(_drv_err_, "%s %d >= IFACE_ID_MAX\n", __func__, i); + rtw_warn_on(1); + continue; + } + + adapter = dvobj->padapters[i]; + + if (adapter == NULL) + continue; + + rtw_os_ndev_free(adapter); + } + +#if defined(CONFIG_IOCTL_CFG80211) + rtw_cfg80211_dev_res_free(dvobj); +#endif +} + +u32 rtw_start_drv_threads(_adapter *padapter) +{ + u32 _status = _SUCCESS; + + RT_TRACE(_module_os_intfs_c_,_drv_info_,("+rtw_start_drv_threads\n")); + +#ifdef CONFIG_XMIT_THREAD_MODE +#if defined(CONFIG_SDIO_HCI) + if (is_primary_adapter(padapter)) +#endif + { + padapter->xmitThread = kthread_run(rtw_xmit_thread, padapter, "RTW_XMIT_THREAD"); + if(IS_ERR(padapter->xmitThread)) + _status = _FAIL; + } +#endif //#ifdef CONFIG_XMIT_THREAD_MODE + +#ifdef CONFIG_RECV_THREAD_MODE + padapter->recvThread = kthread_run(rtw_recv_thread, padapter, "RTW_RECV_THREAD"); + if(IS_ERR(padapter->recvThread)) + _status = _FAIL; +#endif + + if (is_primary_adapter(padapter)) { + padapter->cmdThread = kthread_run(rtw_cmd_thread, padapter, "RTW_CMD_THREAD"); + if(IS_ERR(padapter->cmdThread)) + _status = _FAIL; + else + _rtw_down_sema(&padapter->cmdpriv.terminate_cmdthread_sema); //wait for cmd_thread to run + } + + +#ifdef CONFIG_EVENT_THREAD_MODE + padapter->evtThread = kthread_run(event_thread, padapter, "RTW_EVENT_THREAD"); + if(IS_ERR(padapter->evtThread)) + _status = _FAIL; +#endif + + rtw_hal_start_thread(padapter); + return _status; + +} + +void rtw_stop_drv_threads (_adapter *padapter) +{ + RT_TRACE(_module_os_intfs_c_,_drv_info_,("+rtw_stop_drv_threads\n")); + + if (is_primary_adapter(padapter)) + rtw_stop_cmd_thread(padapter); + +#ifdef CONFIG_EVENT_THREAD_MODE + _rtw_up_sema(&padapter->evtpriv.evt_notify); + if(padapter->evtThread){ + _rtw_down_sema(&padapter->evtpriv.terminate_evtthread_sema); + } +#endif + +#ifdef CONFIG_XMIT_THREAD_MODE + // Below is to termindate tx_thread... +#if defined(CONFIG_SDIO_HCI) + // Only wake-up primary adapter + if (is_primary_adapter(padapter)) +#endif /*SDIO_HCI */ + { + _rtw_up_sema(&padapter->xmitpriv.xmit_sema); + _rtw_down_sema(&padapter->xmitpriv.terminate_xmitthread_sema); + } + RT_TRACE(_module_os_intfs_c_, _drv_info_, ("\n drv_halt: rtw_xmit_thread can be terminated !\n")); +#endif + +#ifdef CONFIG_RECV_THREAD_MODE + // Below is to termindate rx_thread... + _rtw_up_sema(&padapter->recvpriv.recv_sema); + _rtw_down_sema(&padapter->recvpriv.terminate_recvthread_sema); + RT_TRACE(_module_os_intfs_c_,_drv_info_,("\n drv_halt:recv_thread can be terminated! \n")); +#endif + + rtw_hal_stop_thread(padapter); +} + +u8 rtw_init_default_value(_adapter *padapter); +u8 rtw_init_default_value(_adapter *padapter) +{ + u8 ret = _SUCCESS; + struct registry_priv* pregistrypriv = &padapter->registrypriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct mlme_priv *pmlmepriv= &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + + //xmit_priv + pxmitpriv->vcs_setting = pregistrypriv->vrtl_carrier_sense; + pxmitpriv->vcs = pregistrypriv->vcs_type; + pxmitpriv->vcs_type = pregistrypriv->vcs_type; + //pxmitpriv->rts_thresh = pregistrypriv->rts_thresh; + pxmitpriv->frag_len = pregistrypriv->frag_thresh; + + //recv_priv + + //mlme_priv + pmlmepriv->scan_mode = SCAN_ACTIVE; + + //qos_priv + //pmlmepriv->qospriv.qos_option = pregistrypriv->wmm_enable; + + //ht_priv +#ifdef CONFIG_80211N_HT + pmlmepriv->htpriv.ampdu_enable = _FALSE;//set to disabled +#endif + + //security_priv + //rtw_get_encrypt_decrypt_from_registrypriv(padapter); + psecuritypriv->binstallGrpkey = _FAIL; +#ifdef CONFIG_GTK_OL + psecuritypriv->binstallKCK_KEK = _FAIL; +#endif //CONFIG_GTK_OL + psecuritypriv->sw_encrypt=pregistrypriv->software_encrypt; + psecuritypriv->sw_decrypt=pregistrypriv->software_decrypt; + + psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; //open system + psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_; + + psecuritypriv->dot11PrivacyKeyIndex = 0; + + psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; + psecuritypriv->dot118021XGrpKeyid = 1; + + psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen; + psecuritypriv->ndisencryptstatus = Ndis802_11WEPDisabled; + + + //pwrctrl_priv + + + //registry_priv + rtw_init_registrypriv_dev_network(padapter); + rtw_update_registrypriv_dev_network(padapter); + + + //hal_priv + rtw_hal_def_value_init(padapter); + + //misc. + RTW_ENABLE_FUNC(padapter, DF_RX_BIT); + RTW_ENABLE_FUNC(padapter, DF_TX_BIT); + padapter->bLinkInfoDump = 0; + padapter->bNotifyChannelChange = _FALSE; +#ifdef CONFIG_P2P + padapter->bShowGetP2PState = 1; +#endif + + //for debug purpose + padapter->fix_rate = 0xFF; + padapter->data_fb = 0; + padapter->driver_ampdu_spacing = 0xFF; + padapter->driver_rx_ampdu_factor = 0xFF; + padapter->driver_rx_ampdu_spacing = 0xFF; + padapter->fix_rx_ampdu_accept = RX_AMPDU_ACCEPT_INVALID; + padapter->fix_rx_ampdu_size = RX_AMPDU_SIZE_INVALID; +#ifdef DBG_RX_COUNTER_DUMP + padapter->dump_rx_cnt_mode = 0; + padapter->drv_rx_cnt_ok = 0; + padapter->drv_rx_cnt_crcerror = 0; + padapter->drv_rx_cnt_drop = 0; +#endif + return ret; +} + +struct dvobj_priv *devobj_init(void) +{ + struct dvobj_priv *pdvobj = NULL; + + if ((pdvobj = (struct dvobj_priv*)rtw_zmalloc(sizeof(*pdvobj))) == NULL) + { + return NULL; + } + + _rtw_mutex_init(&pdvobj->hw_init_mutex); + _rtw_mutex_init(&pdvobj->h2c_fwcmd_mutex); + _rtw_mutex_init(&pdvobj->setch_mutex); + _rtw_mutex_init(&pdvobj->setbw_mutex); + _rtw_mutex_init(&pdvobj->rf_read_reg_mutex); +#ifdef CONFIG_SDIO_INDIRECT_ACCESS + _rtw_mutex_init(&pdvobj->sd_indirect_access_mutex); +#endif + +#ifdef CONFIG_RTW_CUSTOMER_STR + _rtw_mutex_init(&pdvobj->customer_str_mutex); + _rtw_memset(pdvobj->customer_str, 0xFF, RTW_CUSTOMER_STR_LEN); +#endif + + pdvobj->processing_dev_remove = _FALSE; + + ATOMIC_SET(&pdvobj->disable_func, 0); + + rtw_macid_ctl_init(&pdvobj->macid_ctl); + _rtw_spinlock_init(&pdvobj->cam_ctl.lock); + _rtw_mutex_init(&pdvobj->cam_ctl.sec_cam_access_mutex); + + return pdvobj; + +} + +void devobj_deinit(struct dvobj_priv *pdvobj) +{ + if(!pdvobj) + return; + + /* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */ +#if defined(CONFIG_IOCTL_CFG80211) + rtw_cfg80211_dev_res_free(pdvobj); +#endif + + _rtw_mutex_free(&pdvobj->hw_init_mutex); + _rtw_mutex_free(&pdvobj->h2c_fwcmd_mutex); + +#ifdef CONFIG_RTW_CUSTOMER_STR + _rtw_mutex_free(&pdvobj->customer_str_mutex); +#endif + + _rtw_mutex_free(&pdvobj->setch_mutex); + _rtw_mutex_free(&pdvobj->setbw_mutex); + _rtw_mutex_free(&pdvobj->rf_read_reg_mutex); +#ifdef CONFIG_SDIO_INDIRECT_ACCESS + _rtw_mutex_free(&pdvobj->sd_indirect_access_mutex); +#endif + + rtw_macid_ctl_deinit(&pdvobj->macid_ctl); + _rtw_spinlock_free(&pdvobj->cam_ctl.lock); + _rtw_mutex_free(&pdvobj->cam_ctl.sec_cam_access_mutex); + + rtw_mfree((u8*)pdvobj, sizeof(*pdvobj)); +} + +u8 rtw_reset_drv_sw(_adapter *padapter) +{ + u8 ret8=_SUCCESS; + struct mlme_priv *pmlmepriv= &padapter->mlmepriv; + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + + //hal_priv + if( is_primary_adapter(padapter)) + rtw_hal_def_value_init(padapter); + + RTW_ENABLE_FUNC(padapter, DF_RX_BIT); + RTW_ENABLE_FUNC(padapter, DF_TX_BIT); + padapter->bLinkInfoDump = 0; + + padapter->xmitpriv.tx_pkts = 0; + padapter->recvpriv.rx_pkts = 0; + + pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE; + + //pmlmepriv->LinkDetectInfo.TrafficBusyState = _FALSE; + pmlmepriv->LinkDetectInfo.TrafficTransitionCount = 0; + pmlmepriv->LinkDetectInfo.LowPowerTransitionCount = 0; + + _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY |_FW_UNDER_LINKING); + +#ifdef CONFIG_AUTOSUSPEND + #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,22) && LINUX_VERSION_CODE<=KERNEL_VERSION(2,6,34)) + adapter_to_dvobj(padapter)->pusbdev->autosuspend_disabled = 1;//autosuspend disabled by the user + #endif +#endif + +#ifdef DBG_CONFIG_ERROR_DETECT + if (is_primary_adapter(padapter)) + rtw_hal_sreset_reset_value(padapter); +#endif + pwrctrlpriv->pwr_state_check_cnts = 0; + + //mlmeextpriv + mlmeext_set_scan_state(&padapter->mlmeextpriv, SCAN_DISABLE); + +#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS + rtw_set_signal_stat_timer(&padapter->recvpriv); +#endif + + return ret8; +} + + +u8 rtw_init_drv_sw(_adapter *padapter) +{ + + u8 ret8=_SUCCESS; + +_func_enter_; + + RT_TRACE(_module_os_intfs_c_,_drv_info_,("+rtw_init_drv_sw\n")); + + ret8 = rtw_init_default_value(padapter); + + if ((rtw_init_cmd_priv(&padapter->cmdpriv)) == _FAIL) + { + RT_TRACE(_module_os_intfs_c_,_drv_err_,("\n Can't init cmd_priv\n")); + ret8=_FAIL; + goto exit; + } + + padapter->cmdpriv.padapter=padapter; + + if ((rtw_init_evt_priv(&padapter->evtpriv)) == _FAIL) + { + RT_TRACE(_module_os_intfs_c_,_drv_err_,("\n Can't init evt_priv\n")); + ret8=_FAIL; + goto exit; + } + + + if (rtw_init_mlme_priv(padapter) == _FAIL) + { + RT_TRACE(_module_os_intfs_c_,_drv_err_,("\n Can't init mlme_priv\n")); + ret8=_FAIL; + goto exit; + } + +#ifdef CONFIG_P2P + rtw_init_wifidirect_timers(padapter); + init_wifidirect_info(padapter, P2P_ROLE_DISABLE); + reset_global_wifidirect_info(padapter); + #ifdef CONFIG_IOCTL_CFG80211 + rtw_init_cfg80211_wifidirect_info(padapter); + #endif +#ifdef CONFIG_WFD + if(rtw_init_wifi_display_info(padapter) == _FAIL) + RT_TRACE(_module_os_intfs_c_,_drv_err_,("\n Can't init init_wifi_display_info\n")); +#endif +#endif /* CONFIG_P2P */ + + if(init_mlme_ext_priv(padapter) == _FAIL) + { + RT_TRACE(_module_os_intfs_c_,_drv_err_,("\n Can't init mlme_ext_priv\n")); + ret8=_FAIL; + goto exit; + } + +#ifdef CONFIG_TDLS + if(rtw_init_tdls_info(padapter) == _FAIL) + { + DBG_871X("Can't rtw_init_tdls_info\n"); + ret8=_FAIL; + goto exit; + } +#endif //CONFIG_TDLS + + if(_rtw_init_xmit_priv(&padapter->xmitpriv, padapter) == _FAIL) + { + DBG_871X("Can't _rtw_init_xmit_priv\n"); + ret8=_FAIL; + goto exit; + } + + if(_rtw_init_recv_priv(&padapter->recvpriv, padapter) == _FAIL) + { + DBG_871X("Can't _rtw_init_recv_priv\n"); + ret8=_FAIL; + goto exit; + } + // add for CONFIG_IEEE80211W, none 11w also can use + _rtw_spinlock_init(&padapter->security_key_mutex); + + // We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). + //_rtw_memset((unsigned char *)&padapter->securitypriv, 0, sizeof (struct security_priv)); + + //_init_timer(&(padapter->securitypriv.tkip_timer), padapter->pifp, rtw_use_tkipkey_handler, padapter); + + if(_rtw_init_sta_priv(&padapter->stapriv) == _FAIL) + { + DBG_871X("Can't _rtw_init_sta_priv\n"); + ret8=_FAIL; + goto exit; + } + + padapter->stapriv.padapter = padapter; + padapter->setband = WIFI_FREQUENCY_BAND_AUTO; + padapter->fix_rate = 0xFF; + padapter->data_fb = 0; + padapter->fix_rx_ampdu_accept = RX_AMPDU_ACCEPT_INVALID; + padapter->fix_rx_ampdu_size = RX_AMPDU_SIZE_INVALID; +#ifdef DBG_RX_COUNTER_DUMP + padapter->dump_rx_cnt_mode = 0; + padapter->drv_rx_cnt_ok = 0; + padapter->drv_rx_cnt_crcerror = 0; + padapter->drv_rx_cnt_drop = 0; +#endif + rtw_init_bcmc_stainfo(padapter); + + rtw_init_pwrctrl_priv(padapter); + + //_rtw_memset((u8 *)&padapter->qospriv, 0, sizeof (struct qos_priv));//move to mlme_priv + +#ifdef CONFIG_MP_INCLUDED + if (init_mp_priv(padapter) == _FAIL) { + DBG_871X("%s: initialize MP private data Fail!\n", __func__); + } +#endif + + rtw_hal_dm_init(padapter); +#ifdef CONFIG_SW_LED + rtw_hal_sw_led_init(padapter); +#endif +#ifdef DBG_CONFIG_ERROR_DETECT + rtw_hal_sreset_init(padapter); +#endif + +#ifdef CONFIG_INTEL_WIDI + if(rtw_init_intel_widi(padapter) == _FAIL) + { + DBG_871X("Can't rtw_init_intel_widi\n"); + ret8=_FAIL; + goto exit; + } +#endif //CONFIG_INTEL_WIDI + +#ifdef CONFIG_WAPI_SUPPORT + padapter->WapiSupport = true; //set true temp, will revise according to Efuse or Registry value later. + rtw_wapi_init(padapter); +#endif + +#ifdef CONFIG_BR_EXT + _rtw_spinlock_init(&padapter->br_ext_lock); +#endif // CONFIG_BR_EXT + +exit: + + RT_TRACE(_module_os_intfs_c_,_drv_info_,("-rtw_init_drv_sw\n")); + + _func_exit_; + + return ret8; + +} + +void rtw_cancel_all_timer(_adapter *padapter) +{ + RT_TRACE(_module_os_intfs_c_,_drv_info_,("+rtw_cancel_all_timer\n")); + + _cancel_timer_ex(&padapter->mlmepriv.assoc_timer); + RT_TRACE(_module_os_intfs_c_, _drv_info_, ("rtw_cancel_all_timer:cancel association timer complete!\n")); + + #if 0 + _cancel_timer_ex(&padapter->securitypriv.tkip_timer); + RT_TRACE(_module_os_intfs_c_, _drv_info_, ("rtw_cancel_all_timer:cancel tkip_timer!\n")); + #endif + + _cancel_timer_ex(&padapter->mlmepriv.scan_to_timer); + RT_TRACE(_module_os_intfs_c_, _drv_info_, ("rtw_cancel_all_timer:cancel scan_to_timer!\n")); + + #ifdef CONFIG_DFS_MASTER + _cancel_timer_ex(&padapter->mlmepriv.dfs_master_timer); + #endif + + _cancel_timer_ex(&padapter->mlmepriv.dynamic_chk_timer); + RT_TRACE(_module_os_intfs_c_, _drv_info_, ("rtw_cancel_all_timer:cancel dynamic_chk_timer!\n")); + + // cancel sw led timer + rtw_hal_sw_led_deinit(padapter); + RT_TRACE(_module_os_intfs_c_,_drv_info_,("rtw_cancel_all_timer:cancel DeInitSwLeds! \n")); + + _cancel_timer_ex(&(adapter_to_pwrctl(padapter)->pwr_state_check_timer)); + +#ifdef CONFIG_IOCTL_CFG80211 +#ifdef CONFIG_P2P + _cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer); +#endif //CONFIG_P2P +#endif //CONFIG_IOCTL_CFG80211 + +#ifdef CONFIG_SET_SCAN_DENY_TIMER + _cancel_timer_ex(&padapter->mlmepriv.set_scan_deny_timer); + rtw_clear_scan_deny(padapter); + RT_TRACE(_module_os_intfs_c_,_drv_info_,("rtw_cancel_all_timer:cancel set_scan_deny_timer! \n")); +#endif + +#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS + _cancel_timer_ex(&padapter->recvpriv.signal_stat_timer); +#endif + //cancel dm timer + rtw_hal_dm_deinit(padapter); + +#ifdef CONFIG_PLATFORM_FS_MX61 + msleep(50); +#endif +} + +u8 rtw_free_drv_sw(_adapter *padapter) +{ + RT_TRACE(_module_os_intfs_c_,_drv_info_,("==>rtw_free_drv_sw")); + +#ifdef CONFIG_WAPI_SUPPORT + rtw_wapi_free(padapter); +#endif + + //we can call rtw_p2p_enable here, but: + // 1. rtw_p2p_enable may have IO operation + // 2. rtw_p2p_enable is bundled with wext interface + #ifdef CONFIG_P2P + { + struct wifidirect_info *pwdinfo = &padapter->wdinfo; + if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) + { + _cancel_timer_ex( &pwdinfo->find_phase_timer ); + _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer ); + _cancel_timer_ex( &pwdinfo->pre_tx_scan_timer); +#ifdef CONFIG_CONCURRENT_MODE + _cancel_timer_ex( &pwdinfo->ap_p2p_switch_timer ); +#endif // CONFIG_CONCURRENT_MODE + rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE); + } + } + #endif + // add for CONFIG_IEEE80211W, none 11w also can use + _rtw_spinlock_free(&padapter->security_key_mutex); + +#ifdef CONFIG_BR_EXT + _rtw_spinlock_free(&padapter->br_ext_lock); +#endif // CONFIG_BR_EXT + +#ifdef CONFIG_INTEL_WIDI + rtw_free_intel_widi(padapter); +#endif //CONFIG_INTEL_WIDI + + free_mlme_ext_priv(&padapter->mlmeextpriv); + +#ifdef CONFIG_TDLS + //rtw_free_tdls_info(&padapter->tdlsinfo); +#endif //CONFIG_TDLS + + rtw_free_cmd_priv(&padapter->cmdpriv); + + rtw_free_evt_priv(&padapter->evtpriv); + + rtw_free_mlme_priv(&padapter->mlmepriv); + + //free_io_queue(padapter); + + _rtw_free_xmit_priv(&padapter->xmitpriv); + + _rtw_free_sta_priv(&padapter->stapriv); //will free bcmc_stainfo here + + _rtw_free_recv_priv(&padapter->recvpriv); + + rtw_free_pwrctrl_priv(padapter); + + //rtw_mfree((void *)padapter, sizeof (padapter)); + +#ifdef CONFIG_DRVEXT_MODULE + free_drvext(&padapter->drvextpriv); +#endif + + rtw_hal_free_data(padapter); + + RT_TRACE(_module_os_intfs_c_,_drv_info_,("<==rtw_free_drv_sw\n")); + + //free the old_pnetdev + if(padapter->rereg_nd_name_priv.old_pnetdev) { + free_netdev(padapter->rereg_nd_name_priv.old_pnetdev); + padapter->rereg_nd_name_priv.old_pnetdev = NULL; + } + + // clear pbuddy_adapter to avoid access wrong pointer. + if(padapter->pbuddy_adapter != NULL) { + padapter->pbuddy_adapter->pbuddy_adapter = NULL; + } + + RT_TRACE(_module_os_intfs_c_,_drv_info_,("-rtw_free_drv_sw\n")); + + return _SUCCESS; + +} + +#ifdef CONFIG_CONCURRENT_MODE +#ifdef CONFIG_MULTI_VIR_IFACES +int _netdev_vir_if_open(struct net_device *pnetdev) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); + _adapter *primary_padapter = GET_PRIMARY_ADAPTER(padapter); + + DBG_871X(FUNC_NDEV_FMT" enter\n", FUNC_NDEV_ARG(pnetdev)); + + if(!primary_padapter) + goto _netdev_virtual_iface_open_error; + + if (primary_padapter->bup == _FALSE || !rtw_is_hw_init_completed(primary_padapter)) + _netdev_open(primary_padapter->pnetdev); + + if(padapter->bup == _FALSE && primary_padapter->bup == _TRUE && + rtw_is_hw_init_completed(primary_padapter)) + { + padapter->bFWReady = primary_padapter->bFWReady; + + if(rtw_start_drv_threads(padapter) == _FAIL) + { + goto _netdev_virtual_iface_open_error; + } + +#ifdef CONFIG_IOCTL_CFG80211 + rtw_cfg80211_init_wiphy(padapter); +#endif + + padapter->bup = _TRUE; + + } + + padapter->net_closed = _FALSE; + + _set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000); + + rtw_netif_wake_queue(pnetdev); + + DBG_871X(FUNC_NDEV_FMT" exit\n", FUNC_NDEV_ARG(pnetdev)); + return 0; + +_netdev_virtual_iface_open_error: + + padapter->bup = _FALSE; + + netif_carrier_off(pnetdev); + rtw_netif_stop_queue(pnetdev); + + return (-1); + +} + +int netdev_vir_if_open(struct net_device *pnetdev) +{ + int ret; + _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); + + _enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL); + ret = _netdev_vir_if_open(pnetdev); + _exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL); + +#ifdef CONFIG_AUTO_AP_MODE + //if(padapter->iface_id == 2) + // rtw_start_auto_ap(padapter); +#endif + + return ret; +} + +static int netdev_vir_if_close(struct net_device *pnetdev) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); + + padapter->net_closed = _TRUE; + + if(pnetdev) + { + rtw_netif_stop_queue(pnetdev); + } + +#ifdef CONFIG_IOCTL_CFG80211 + rtw_scan_abort(padapter); + rtw_cfg80211_wait_scan_req_empty(padapter, 200); + adapter_wdev_data(padapter)->bandroid_scan = _FALSE; +#endif + + return 0; +} + +#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29)) +static const struct net_device_ops rtw_netdev_vir_if_ops = { + .ndo_open = netdev_vir_if_open, + .ndo_stop = netdev_vir_if_close, + .ndo_start_xmit = rtw_xmit_entry, + .ndo_set_mac_address = rtw_net_set_mac_address, + .ndo_get_stats = rtw_net_get_stats, + .ndo_do_ioctl = rtw_ioctl, +#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) + .ndo_select_queue = rtw_select_queue, +#endif +}; +#endif + +void rtw_hook_vir_if_ops(struct net_device *ndev) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) + ndev->netdev_ops = &rtw_netdev_vir_if_ops; +#else + ndev->open = netdev_vir_if_open; + ndev->stop = netdev_vir_if_close; + ndev->set_mac_address = rtw_net_set_mac_address; +#endif +} + +_adapter *rtw_drv_add_vir_if(_adapter *primary_padapter, + void (*set_intf_ops)(_adapter *primary_padapter,struct _io_ops *pops)) +{ + int res = _FAIL; + _adapter *padapter = NULL; + struct dvobj_priv *pdvobjpriv; + u8 mac[ETH_ALEN]; + +/* + if((primary_padapter->bup == _FALSE) || + (rtw_buddy_adapter_up(primary_padapter) == _FALSE)) + goto exit; +*/ + + /****** init adapter ******/ + padapter = (_adapter *)rtw_zvmalloc(sizeof(*padapter)); + if (padapter == NULL) + goto exit; + + if (loadparam(padapter) != _SUCCESS) + goto free_adapter; + + _rtw_memcpy(padapter, primary_padapter, sizeof(_adapter)); + + // + padapter->bup = _FALSE; + padapter->net_closed = _TRUE; + padapter->dir_dev = NULL; + padapter->dir_odm = NULL; + + + //set adapter_type/iface type + padapter->isprimary = _FALSE; + padapter->adapter_type = MAX_ADAPTER; + padapter->pbuddy_adapter = primary_padapter; +#if 0 +#ifndef CONFIG_HWPORT_SWAP //Port0 -> Pri , Port1 -> Sec + padapter->iface_type = IFACE_PORT1; +#else + padapter->iface_type = IFACE_PORT0; +#endif //CONFIG_HWPORT_SWAP +#else + //extended virtual interfaces always are set to port0 + padapter->iface_type = IFACE_PORT0; +#endif + + /****** hook vir if into dvobj ******/ + pdvobjpriv = adapter_to_dvobj(padapter); + padapter->iface_id = pdvobjpriv->iface_nums; + pdvobjpriv->padapters[pdvobjpriv->iface_nums++] = padapter; + + padapter->intf_start = NULL; + padapter->intf_stop = NULL; + + //step init_io_priv + if ((rtw_init_io_priv(padapter, set_intf_ops)) == _FAIL) { + RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("\n Can't init io_reqs\n")); + goto free_adapter; + } + + //init drv data + if(rtw_init_drv_sw(padapter)!= _SUCCESS) + goto free_drv_sw; + + + //get mac address from primary_padapter + _rtw_memcpy(mac, adapter_mac_addr(primary_padapter), ETH_ALEN); + + /* + * If the BIT1 is 0, the address is universally administered. + * If it is 1, the address is locally administered + */ +#if 1 /* needs enable MBSSID CAM */ + mac[0] |= BIT(1); + mac[0] |= (padapter->iface_id-1)<<4; +#endif + + _rtw_memcpy(adapter_mac_addr(padapter), mac, ETH_ALEN); + + res = _SUCCESS; + +free_drv_sw: + if (res != _SUCCESS && padapter) + rtw_free_drv_sw(padapter); +free_adapter: + if (res != _SUCCESS && padapter) { + rtw_vmfree((u8 *)padapter, sizeof(*padapter)); + padapter = NULL; + } +exit: + return padapter; +} + +void rtw_drv_stop_vir_if(_adapter *padapter) +{ + struct net_device *pnetdev=NULL; + + if (padapter == NULL) + return; + + pnetdev = padapter->pnetdev; + + + if (padapter->bup == _TRUE) + { + #ifdef CONFIG_XMIT_ACK + if (padapter->xmitpriv.ack_tx) + rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_DRV_STOP); + #endif + + if (padapter->intf_stop) + { + padapter->intf_stop(padapter); + } + + rtw_stop_drv_threads(padapter); + + padapter->bup = _FALSE; + } + + /* cancel timer after thread stop */ + rtw_cancel_all_timer(padapter); +} + +void rtw_drv_free_vir_if(_adapter *padapter) +{ + if (padapter == NULL) + return; + + padapter->pbuddy_adapter = NULL; + + rtw_free_drv_sw(padapter); + + /* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */ + rtw_os_ndev_free(padapter); + + rtw_vmfree((u8 *)padapter, sizeof(_adapter)); +} + +void rtw_drv_stop_vir_ifaces(struct dvobj_priv *dvobj) +{ + int i; + //struct dvobj_priv *dvobj = primary_padapter->dvobj; + + for(i=2;iiface_nums;i++) + { + rtw_drv_stop_vir_if(dvobj->padapters[i]); + } +} + +void rtw_drv_free_vir_ifaces(struct dvobj_priv *dvobj) +{ + int i; + //struct dvobj_priv *dvobj = primary_padapter->dvobj; + + for(i=2;iiface_nums;i++) + { + rtw_drv_free_vir_if(dvobj->padapters[i]); + } +} + +void rtw_drv_del_vir_if(_adapter *padapter) +{ + rtw_drv_stop_vir_if(padapter); + rtw_drv_free_vir_if(padapter); +} + +void rtw_drv_del_vir_ifaces(_adapter *primary_padapter) +{ + int i; + struct dvobj_priv *dvobj = primary_padapter->dvobj; + + for(i=2;iiface_nums;i++) + { + rtw_drv_del_vir_if(dvobj->padapters[i]); + } +} +#endif //CONFIG_MULTI_VIR_IFACES + +int _netdev_if2_open(struct net_device *pnetdev) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); + _adapter *primary_padapter = padapter->pbuddy_adapter; + + DBG_871X("+871x_drv - if2_open, bup=%d\n", padapter->bup); + +#ifdef CONFIG_PLATFORM_INTEL_BYT + if (padapter->bup == _FALSE) + { + u8 mac[ETH_ALEN]; + + /* get mac address from primary_padapter */ + if (primary_padapter->bup == _FALSE) + rtw_macaddr_cfg(adapter_mac_addr(primary_padapter), get_hal_mac_addr(primary_padapter)); + + _rtw_memcpy(mac, adapter_mac_addr(primary_padapter), ETH_ALEN); + + /* + * If the BIT1 is 0, the address is universally administered. + * If it is 1, the address is locally administered + */ + mac[0] |= BIT(1); + + _rtw_memcpy(adapter_mac_addr(padapter), mac, ETH_ALEN); + rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter)); + _rtw_memcpy(pnetdev->dev_addr, adapter_mac_addr(padapter), ETH_ALEN); + } +#endif //CONFIG_PLATFORM_INTEL_BYT + + if (primary_padapter->bup == _FALSE || !rtw_is_hw_init_completed(primary_padapter)) + _netdev_open(primary_padapter->pnetdev); + + if(padapter->bup == _FALSE && primary_padapter->bup == _TRUE && + rtw_is_hw_init_completed(primary_padapter)) + { + padapter->bFWReady = primary_padapter->bFWReady; + + //if (init_mlme_ext_priv(padapter) == _FAIL) + // goto netdev_if2_open_error; + + + if (rtw_start_drv_threads(padapter) == _FAIL) + { + goto netdev_if2_open_error; + } + + + if (padapter->intf_start) + { + padapter->intf_start(padapter); + } + +#ifdef CONFIG_IOCTL_CFG80211 + rtw_cfg80211_init_wiphy(padapter); +#endif + + padapter->bup = _TRUE; + + } + + padapter->net_closed = _FALSE; + + //execute dynamic_chk_timer only on primary interface + // secondary interface shares the timer with primary interface. + //_set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000); + + rtw_netif_wake_queue(pnetdev); + + DBG_871X("-871x_drv - if2_open, bup=%d\n", padapter->bup); + return 0; + +netdev_if2_open_error: + + padapter->bup = _FALSE; + + netif_carrier_off(pnetdev); + rtw_netif_stop_queue(pnetdev); + + return (-1); + +} + +int netdev_if2_open(struct net_device *pnetdev) +{ + int ret; + _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + + if (pwrctrlpriv->bInSuspend == _TRUE) + { + DBG_871X("+871x_drv - netdev_if2_open, bInSuspend=%d\n", pwrctrlpriv->bInSuspend); + return 0; + } + + _enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL); + ret = _netdev_if2_open(pnetdev); + _exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL); + +#ifdef CONFIG_AUTO_AP_MODE + //if(padapter->iface_id == 2) + rtw_start_auto_ap(padapter); +#endif + + return ret; +} + +static int netdev_if2_close(struct net_device *pnetdev) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + padapter->net_closed = _TRUE; + pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE; + + if(pnetdev) + { + rtw_netif_stop_queue(pnetdev); + } + +#ifdef CONFIG_P2P + if (!rtw_p2p_chk_role(&padapter->wdinfo, P2P_ROLE_DISABLE)) + rtw_p2p_enable(padapter, P2P_ROLE_DISABLE); +#endif + +#ifdef CONFIG_IOCTL_CFG80211 + rtw_scan_abort(padapter); + rtw_cfg80211_wait_scan_req_empty(padapter, 200); + adapter_wdev_data(padapter)->bandroid_scan = _FALSE; +#endif + + return 0; +} + +#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29)) +static const struct net_device_ops rtw_netdev_if2_ops = { + .ndo_init = rtw_ndev_init, + .ndo_uninit = rtw_ndev_uninit, + .ndo_open = netdev_if2_open, + .ndo_stop = netdev_if2_close, + .ndo_start_xmit = rtw_xmit_entry, + .ndo_set_mac_address = rtw_net_set_mac_address, + .ndo_get_stats = rtw_net_get_stats, + .ndo_do_ioctl = rtw_ioctl, +#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) + .ndo_select_queue = rtw_select_queue, +#endif +}; +#endif + +void rtw_hook_if2_ops(struct net_device *ndev) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)) + ndev->netdev_ops = &rtw_netdev_if2_ops; +#else + ndev->init = rtw_ndev_init; + ndev->uninit = rtw_ndev_uninit; + ndev->open = netdev_if2_open; + ndev->stop = netdev_if2_close; + ndev->set_mac_address = rtw_net_set_mac_address; +#endif +} + +_adapter *rtw_drv_if2_init(_adapter *primary_padapter, + void (*set_intf_ops)(_adapter *primary_padapter,struct _io_ops *pops)) +{ + int res = _FAIL; + _adapter *padapter = NULL; + struct dvobj_priv *pdvobjpriv; + u8 mac[ETH_ALEN]; + + /****** init adapter ******/ + padapter = (_adapter *)rtw_zvmalloc(sizeof(*padapter)); + if (padapter == NULL) + goto exit; + + if (loadparam(padapter) != _SUCCESS) + goto free_adapter; + + _rtw_memcpy(padapter, primary_padapter, sizeof(*padapter)); + + // + padapter->bup = _FALSE; + padapter->net_closed = _TRUE; + padapter->dir_dev = NULL; + padapter->dir_odm = NULL; + + //set adapter_type/iface type + padapter->isprimary = _FALSE; + padapter->adapter_type = SECONDARY_ADAPTER; + padapter->pbuddy_adapter = primary_padapter; + padapter->iface_id = IFACE_ID1; +#ifndef CONFIG_HWPORT_SWAP //Port0 -> Pri , Port1 -> Sec + padapter->iface_type = IFACE_PORT1; +#else + padapter->iface_type = IFACE_PORT0; +#endif //CONFIG_HWPORT_SWAP + + /****** hook if2 into dvobj ******/ + pdvobjpriv = adapter_to_dvobj(padapter); + pdvobjpriv->padapters[pdvobjpriv->iface_nums++] = padapter; + + // + padapter->intf_start = primary_padapter->intf_start; + padapter->intf_stop = primary_padapter->intf_stop; + + //step init_io_priv + if ((rtw_init_io_priv(padapter, set_intf_ops)) == _FAIL) { + RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("\n Can't init io_reqs\n")); + goto free_adapter; + } + + //init drv data + if(rtw_init_drv_sw(padapter)!= _SUCCESS) + goto free_drv_sw; + + + /* get mac address from primary_padapter */ + _rtw_memcpy(mac, adapter_mac_addr(primary_padapter), ETH_ALEN); + + /* + * If the BIT1 is 0, the address is universally administered. + * If it is 1, the address is locally administered + */ + mac[0] |= BIT(1); + + _rtw_memcpy(adapter_mac_addr(padapter), mac, ETH_ALEN); + rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter)); + + primary_padapter->pbuddy_adapter = padapter; + + res = _SUCCESS; + +free_drv_sw: + if (res != _SUCCESS && padapter) + rtw_free_drv_sw(padapter); +free_adapter: + if (res != _SUCCESS && padapter) { + rtw_vmfree((u8 *)padapter, sizeof(*padapter)); + padapter = NULL; + } +exit: + return padapter; +} + +void rtw_drv_if2_free(_adapter *if2) +{ + _adapter *padapter = if2; + + if (padapter == NULL) + return; + + rtw_free_drv_sw(padapter); + + /* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */ + rtw_os_ndev_free(padapter); + + rtw_vmfree((u8 *)padapter, sizeof(_adapter)); +} + +void rtw_drv_if2_stop(_adapter *if2) +{ + _adapter *padapter = if2; + struct net_device *pnetdev = NULL; + + if (padapter == NULL) + return; + + + if (padapter->bup == _TRUE) { + #ifdef CONFIG_XMIT_ACK + if (padapter->xmitpriv.ack_tx) + rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_DRV_STOP); + #endif + + if (padapter->intf_stop) + { + padapter->intf_stop(padapter); + } + + rtw_stop_drv_threads(padapter); + + padapter->bup = _FALSE; + } + + /* cancel timer after thread stop */ + rtw_cancel_all_timer(padapter); +} +#endif //end of CONFIG_CONCURRENT_MODE + +int rtw_os_ndevs_register(struct dvobj_priv *dvobj) +{ + int i, status = _SUCCESS; + struct registry_priv *regsty = dvobj_to_regsty(dvobj); + _adapter *adapter; + +#if defined(CONFIG_IOCTL_CFG80211) + if (rtw_cfg80211_dev_res_register(dvobj) != _SUCCESS) { + rtw_warn_on(1); + status = _FAIL; + goto exit; + } +#endif + + for (i = 0; i < dvobj->iface_nums; i++) { + + if (i >= IFACE_ID_MAX) { + DBG_871X_LEVEL(_drv_err_, "%s %d >= IFACE_ID_MAX\n", __func__, i); + rtw_warn_on(1); + continue; + } + + adapter = dvobj->padapters[i]; + if (adapter) { + char *name; + + if (adapter->iface_id == IFACE_ID0) + name = regsty->ifname; + else if (adapter->iface_id == IFACE_ID1) + name = regsty->if2name; + else + name = "wlan%d"; + + #ifdef CONFIG_CONCURRENT_MODE + switch (adapter->adapter_type) { + case SECONDARY_ADAPTER: + rtw_hook_if2_ops(adapter->pnetdev); + break; + #ifdef CONFIG_MULTI_VIR_IFACES + case MAX_ADAPTER: + rtw_hook_vir_if_ops(adapter->pnetdev); + break; + #endif + } + #endif /* CONFIG_CONCURRENT_MODE */ + + status = rtw_os_ndev_register(adapter, name); + + if (status != _SUCCESS) { + rtw_warn_on(1); + break; + } + } + } + + if (status != _SUCCESS) { + for (; i >= 0; i--) { + adapter = dvobj->padapters[i]; + if (adapter) + rtw_os_ndev_unregister(adapter); + } + } + +#if defined(CONFIG_IOCTL_CFG80211) + if (status != _SUCCESS) + rtw_cfg80211_dev_res_unregister(dvobj); +#endif +exit: + return status; +} + +void rtw_os_ndevs_unregister(struct dvobj_priv *dvobj) +{ + int i; + _adapter *adapter = NULL; + + for (i = 0; i < dvobj->iface_nums; i++) { + adapter = dvobj->padapters[i]; + + if (adapter == NULL) + continue; + + rtw_os_ndev_unregister(adapter); + } + +#if defined(CONFIG_IOCTL_CFG80211) + rtw_cfg80211_dev_res_unregister(dvobj); +#endif +} + +/** + * rtw_os_ndevs_init - Allocate and register OS layer net devices and relating structures for @dvobj + * @dvobj: the dvobj on which this function applies + * + * Returns: + * _SUCCESS or _FAIL + */ +int rtw_os_ndevs_init(struct dvobj_priv *dvobj) +{ + int ret = _FAIL; + + if (rtw_os_ndevs_alloc(dvobj) != _SUCCESS) + goto exit; + + if (rtw_os_ndevs_register(dvobj) != _SUCCESS) + goto os_ndevs_free; + + ret = _SUCCESS; + +os_ndevs_free: + if (ret != _SUCCESS) + rtw_os_ndevs_free(dvobj); +exit: + return ret; +} + +/** + * rtw_os_ndevs_deinit - Unregister and free OS layer net devices and relating structures for @dvobj + * @dvobj: the dvobj on which this function applies + */ +void rtw_os_ndevs_deinit(struct dvobj_priv *dvobj) +{ + rtw_os_ndevs_unregister(dvobj); + rtw_os_ndevs_free(dvobj); +} + +#ifdef CONFIG_BR_EXT +void netdev_br_init(struct net_device *netdev) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(netdev); + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) + rcu_read_lock(); +#endif // (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) + + //if(check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) + { + //struct net_bridge *br = netdev->br_port->br;//->dev->dev_addr; +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) + if (netdev->br_port) +#else // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) + if (rcu_dereference(adapter->pnetdev->rx_handler_data)) +#endif // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) + { + struct net_device *br_netdev; +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) + br_netdev = dev_get_by_name(CONFIG_BR_EXT_BRNAME); +#else // (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) + struct net *devnet = NULL; + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) + devnet = netdev->nd_net; +#else // (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) + devnet = dev_net(netdev); +#endif // (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) + + br_netdev = dev_get_by_name(devnet, CONFIG_BR_EXT_BRNAME); +#endif // (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) + + if (br_netdev) { + memcpy(adapter->br_mac, br_netdev->dev_addr, ETH_ALEN); + dev_put(br_netdev); + } else + printk("%s()-%d: dev_get_by_name(%s) failed!", __FUNCTION__, __LINE__, CONFIG_BR_EXT_BRNAME); + } + + adapter->ethBrExtInfo.addPPPoETag = 1; + } + +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) + rcu_read_unlock(); +#endif // (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) +} +#endif //CONFIG_BR_EXT + +int _netdev_open(struct net_device *pnetdev) +{ + uint status; + _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); +#ifdef CONFIG_BT_COEXIST_SOCKET_TRX + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); +#endif //CONFIG_BT_COEXIST_SOCKET_TRX + + RT_TRACE(_module_os_intfs_c_,_drv_info_,("+871x_drv - dev_open\n")); + DBG_871X("+871x_drv - drv_open, bup=%d\n", padapter->bup); + + padapter->netif_up = _TRUE; + +#ifdef CONFIG_PLATFORM_INTEL_BYT + rtw_sdio_set_power(1); +#endif //CONFIG_PLATFORM_INTEL_BYT + + if(pwrctrlpriv->ps_flag == _TRUE){ + padapter->net_closed = _FALSE; + goto netdev_open_normal_process; + } + + if(padapter->bup == _FALSE) + { +#ifdef CONFIG_PLATFORM_INTEL_BYT + rtw_macaddr_cfg(adapter_mac_addr(padapter), get_hal_mac_addr(padapter)); + rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter)); + _rtw_memcpy(pnetdev->dev_addr, adapter_mac_addr(padapter), ETH_ALEN); +#endif //CONFIG_PLATFORM_INTEL_BYT + + rtw_clr_surprise_removed(padapter); + rtw_clr_drv_stopped(padapter); + + status = rtw_hal_init(padapter); + if (status ==_FAIL) + { + RT_TRACE(_module_os_intfs_c_,_drv_err_,("rtl871x_hal_init(): Can't init h/w!\n")); + goto netdev_open_error; + } + + DBG_871X("MAC Address = "MAC_FMT"\n", MAC_ARG(pnetdev->dev_addr)); + + status=rtw_start_drv_threads(padapter); + if(status ==_FAIL) + { + DBG_871X("Initialize driver software resource Failed!\n"); + goto netdev_open_error; + } + +#ifdef CONFIG_DRVEXT_MODULE + init_drvext(padapter); +#endif + + if (padapter->intf_start) + { + padapter->intf_start(padapter); + } + +#ifdef CONFIG_IOCTL_CFG80211 + rtw_cfg80211_init_wiphy(padapter); +#endif + + rtw_led_control(padapter, LED_CTL_NO_LINK); + + padapter->bup = _TRUE; + pwrctrlpriv->bips_processing = _FALSE; + +#ifdef CONFIG_PLATFORM_INTEL_BYT +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_IpsNotify(padapter, IPS_NONE); +#endif // CONFIG_BT_COEXIST +#endif //CONFIG_PLATFORM_INTEL_BYT + } + padapter->net_closed = _FALSE; + + _set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000); + +#ifndef CONFIG_IPS_CHECK_IN_WD + rtw_set_pwr_state_check_timer(pwrctrlpriv); +#endif + + //netif_carrier_on(pnetdev);//call this func when rtw_joinbss_event_callback return success + rtw_netif_wake_queue(pnetdev); + +#ifdef CONFIG_BR_EXT + netdev_br_init(pnetdev); +#endif // CONFIG_BR_EXT + +#ifdef CONFIG_BT_COEXIST_SOCKET_TRX + if(is_primary_adapter(padapter) && _TRUE == pHalData->EEPROMBluetoothCoexist) + { + rtw_btcoex_init_socket(padapter); + padapter->coex_info.BtMgnt.ExtConfig.HCIExtensionVer = 0x04; + rtw_btcoex_SetHciVersion(padapter,0x04); + } + else + DBG_871X("CONFIG_BT_COEXIST: SECONDARY_ADAPTER\n"); +#endif //CONFIG_BT_COEXIST_SOCKET_TRX + + +netdev_open_normal_process: + + #ifdef CONFIG_CONCURRENT_MODE + { + _adapter *sec_adapter = padapter->pbuddy_adapter; + if(sec_adapter && (sec_adapter->bup == _FALSE)) + _netdev_if2_open(sec_adapter->pnetdev); + } + #endif + + RT_TRACE(_module_os_intfs_c_,_drv_info_,("-871x_drv - dev_open\n")); + DBG_871X("-871x_drv - drv_open, bup=%d\n", padapter->bup); + + return 0; + +netdev_open_error: + + padapter->bup = _FALSE; + + netif_carrier_off(pnetdev); + rtw_netif_stop_queue(pnetdev); + + RT_TRACE(_module_os_intfs_c_,_drv_err_,("-871x_drv - dev_open, fail!\n")); + DBG_871X("-871x_drv - drv_open fail, bup=%d\n", padapter->bup); + + return (-1); + +} + +int netdev_open(struct net_device *pnetdev) +{ + int ret; + _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter); + + if (pwrctrlpriv->bInSuspend == _TRUE) + { + DBG_871X("+871x_drv - drv_open, bInSuspend=%d\n", pwrctrlpriv->bInSuspend); + return 0; + } + + _enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL); + ret = _netdev_open(pnetdev); + _exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL); + + return ret; +} + +#ifdef CONFIG_IPS +int ips_netdrv_open(_adapter *padapter) +{ + int status = _SUCCESS; + //struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + + padapter->net_closed = _FALSE; + + DBG_871X("===> %s.........\n",__FUNCTION__); + + + rtw_clr_drv_stopped(padapter); + //padapter->bup = _TRUE; + + status = rtw_hal_init(padapter); + if (status ==_FAIL) + { + RT_TRACE(_module_os_intfs_c_,_drv_err_,("ips_netdrv_open(): Can't init h/w!\n")); + goto netdev_open_error; + } + + if (padapter->intf_start) + { + padapter->intf_start(padapter); + } + +#ifndef CONFIG_IPS_CHECK_IN_WD + rtw_set_pwr_state_check_timer(adapter_to_pwrctl(padapter)); +#endif + _set_timer(&padapter->mlmepriv.dynamic_chk_timer,2000); + + return _SUCCESS; + +netdev_open_error: + //padapter->bup = _FALSE; + DBG_871X("-ips_netdrv_open - drv_open failure, bup=%d\n", padapter->bup); + + return _FAIL; +} + + +int rtw_ips_pwr_up(_adapter *padapter) +{ + int result; + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); +#ifdef DBG_CONFIG_ERROR_DETECT + struct sreset_priv *psrtpriv = &pHalData->srestpriv; +#endif//#ifdef DBG_CONFIG_ERROR_DETECT + u32 start_time = rtw_get_current_time(); + DBG_871X("===> rtw_ips_pwr_up..............\n"); + +#if defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) +#ifdef DBG_CONFIG_ERROR_DETECT + if (psrtpriv->silent_reset_inprogress == _TRUE) +#endif//#ifdef DBG_CONFIG_ERROR_DETECT +#endif //defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) + rtw_reset_drv_sw(padapter); + + result = ips_netdrv_open(padapter); + + rtw_led_control(padapter, LED_CTL_NO_LINK); + + DBG_871X("<=== rtw_ips_pwr_up.............. in %dms\n", rtw_get_passing_time_ms(start_time)); + return result; + +} + +void rtw_ips_pwr_down(_adapter *padapter) +{ + u32 start_time = rtw_get_current_time(); + DBG_871X("===> rtw_ips_pwr_down...................\n"); + + padapter->net_closed = _TRUE; + + rtw_ips_dev_unload(padapter); + DBG_871X("<=== rtw_ips_pwr_down..................... in %dms\n", rtw_get_passing_time_ms(start_time)); +} +#endif +void rtw_ips_dev_unload(_adapter *padapter) +{ + struct net_device *pnetdev= (struct net_device*)padapter->pnetdev; + struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); +#ifdef DBG_CONFIG_ERROR_DETECT + struct sreset_priv *psrtpriv = &pHalData->srestpriv; +#endif//#ifdef DBG_CONFIG_ERROR_DETECT + DBG_871X("====> %s...\n",__FUNCTION__); + + +#if defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) +#ifdef DBG_CONFIG_ERROR_DETECT + if (psrtpriv->silent_reset_inprogress == _TRUE) +#endif //#ifdef DBG_CONFIG_ERROR_DETECT +#endif //defined(CONFIG_SWLPS_IN_IPS) || defined(CONFIG_FWLPS_IN_IPS) + { + rtw_hal_set_hwreg(padapter, HW_VAR_FIFO_CLEARN_UP, 0); + + if (padapter->intf_stop) + { + padapter->intf_stop(padapter); + } + } + + if (!rtw_is_surprise_removed(padapter)) + rtw_hal_deinit(padapter); + +} + + +int pm_netdev_open(struct net_device *pnetdev,u8 bnormal) +{ + int status = 0; + + _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); + + if (_TRUE == bnormal) + { + _enter_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL); + status = _netdev_open(pnetdev); + _exit_critical_mutex(&(adapter_to_dvobj(padapter)->hw_init_mutex), NULL); + } +#ifdef CONFIG_IPS + else + status = (_SUCCESS == ips_netdrv_open(padapter))?(0):(-1); +#endif + + return status; +} + +static int netdev_close(struct net_device *pnetdev) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; +#ifdef CONFIG_BT_COEXIST_SOCKET_TRX + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); +#endif //CONFIG_BT_COEXIST_SOCKET_TRX + + RT_TRACE(_module_os_intfs_c_,_drv_info_,("+871x_drv - drv_close\n")); + +#ifndef CONFIG_PLATFORM_INTEL_BYT + if(pwrctl->bInternalAutoSuspend == _TRUE) + { + //rtw_pwr_wakeup(padapter); + if(pwrctl->rf_pwrstate == rf_off) + pwrctl->ps_flag = _TRUE; + } + padapter->net_closed = _TRUE; + padapter->netif_up = _FALSE; + pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE; + +/* if (!rtw_is_hw_init_completed(padapter)) { + DBG_871X("(1)871x_drv - drv_close, bup=%d, hw_init_completed=%s\n", padapter->bup, rtw_is_hw_init_completed(padapter)?"_TRUE":"_FALSE"); + + rtw_set_drv_stopped(padapter); + + rtw_dev_unload(padapter); + } + else*/ + if(pwrctl->rf_pwrstate == rf_on){ + DBG_871X("(2)871x_drv - drv_close, bup=%d, hw_init_completed=%s\n", padapter->bup, rtw_is_hw_init_completed(padapter)?"_TRUE":"_FALSE"); + + //s1. + if(pnetdev) + { + rtw_netif_stop_queue(pnetdev); + } + +#ifndef CONFIG_ANDROID + //s2. + LeaveAllPowerSaveMode(padapter); + rtw_disassoc_cmd(padapter, 500, _FALSE); + //s2-2. indicate disconnect to os + rtw_indicate_disconnect(padapter, 0, _FALSE); + //s2-3. + rtw_free_assoc_resources(padapter, 1); + //s2-4. + rtw_free_network_queue(padapter,_TRUE); +#endif + // Close LED + rtw_led_control(padapter, LED_CTL_POWER_OFF); + } + +#ifdef CONFIG_BR_EXT + //if (OPMODE & (WIFI_STATION_STATE | WIFI_ADHOC_STATE)) + { + //void nat25_db_cleanup(_adapter *priv); + nat25_db_cleanup(padapter); + } +#endif // CONFIG_BR_EXT + +#ifdef CONFIG_P2P + if (!rtw_p2p_chk_role(&padapter->wdinfo, P2P_ROLE_DISABLE)) + rtw_p2p_enable(padapter, P2P_ROLE_DISABLE); +#endif //CONFIG_P2P + +#ifdef CONFIG_IOCTL_CFG80211 + rtw_scan_abort(padapter); + rtw_cfg80211_wait_scan_req_empty(padapter, 200); + adapter_wdev_data(padapter)->bandroid_scan = _FALSE; + //padapter->rtw_wdev->iftype = NL80211_IFTYPE_MONITOR; //set this at the end +#endif //CONFIG_IOCTL_CFG80211 + +#ifdef CONFIG_WAPI_SUPPORT + rtw_wapi_disable_tx(padapter); +#endif +#ifdef CONFIG_BT_COEXIST_SOCKET_TRX + if(is_primary_adapter(padapter) && _TRUE == pHalData->EEPROMBluetoothCoexist) + rtw_btcoex_close_socket(padapter); + else + DBG_871X("CONFIG_BT_COEXIST: SECONDARY_ADAPTER\n"); +#endif //CONFIG_BT_COEXIST_SOCKET_TRX +#else //!CONFIG_PLATFORM_INTEL_BYT + + if (pwrctl->bInSuspend == _TRUE) + { + DBG_871X("+871x_drv - drv_close, bInSuspend=%d\n", pwrctl->bInSuspend); + return 0; + } + + rtw_scan_abort(padapter); // stop scanning process before wifi is going to down + #ifdef CONFIG_IOCTL_CFG80211 + rtw_cfg80211_wait_scan_req_empty(padapter, 200); + #endif + + DBG_871X("netdev_close, bips_processing=%d\n", pwrctl->bips_processing); + while (pwrctl->bips_processing == _TRUE) // waiting for ips_processing done before call rtw_dev_unload() + rtw_msleep_os(1); + + rtw_dev_unload(padapter); + rtw_sdio_set_power(0); + +#endif //!CONFIG_PLATFORM_INTEL_BYT + + RT_TRACE(_module_os_intfs_c_,_drv_info_,("-871x_drv - drv_close\n")); + DBG_871X("-871x_drv - drv_close, bup=%d\n", padapter->bup); + + return 0; + +} + +int pm_netdev_close(struct net_device *pnetdev,u8 bnormal) +{ + int status = 0; + + status = netdev_close(pnetdev); + + return status; +} + +void rtw_ndev_destructor(struct net_device *ndev) +{ + DBG_871X(FUNC_NDEV_FMT"\n", FUNC_NDEV_ARG(ndev)); + +#ifdef CONFIG_IOCTL_CFG80211 + if (ndev->ieee80211_ptr) + rtw_mfree((u8 *)ndev->ieee80211_ptr, sizeof(struct wireless_dev)); +#endif + free_netdev(ndev); +} + +#ifdef CONFIG_ARP_KEEP_ALIVE +struct route_info { + struct in_addr dst_addr; + struct in_addr src_addr; + struct in_addr gateway; + unsigned int dev_index; +}; + +static void parse_routes(struct nlmsghdr *nl_hdr, struct route_info *rt_info) +{ + struct rtmsg *rt_msg; + struct rtattr *rt_attr; + int rt_len; + + rt_msg = (struct rtmsg *) NLMSG_DATA(nl_hdr); + if ((rt_msg->rtm_family != AF_INET) || (rt_msg->rtm_table != RT_TABLE_MAIN)) + return; + + rt_attr = (struct rtattr *) RTM_RTA(rt_msg); + rt_len = RTM_PAYLOAD(nl_hdr); + + for (; RTA_OK(rt_attr, rt_len); rt_attr = RTA_NEXT(rt_attr, rt_len)) + { + switch (rt_attr->rta_type) { + case RTA_OIF: + rt_info->dev_index = *(int *) RTA_DATA(rt_attr); + break; + case RTA_GATEWAY: + rt_info->gateway.s_addr = *(u_int *) RTA_DATA(rt_attr); + break; + case RTA_PREFSRC: + rt_info->src_addr.s_addr = *(u_int *) RTA_DATA(rt_attr); + break; + case RTA_DST: + rt_info->dst_addr.s_addr = *(u_int *) RTA_DATA(rt_attr); + break; + } + } +} + +static int route_dump(u32 *gw_addr ,int* gw_index) +{ + int err = 0; + struct socket *sock; + struct { + struct nlmsghdr nlh; + struct rtgenmsg g; + } req; + struct msghdr msg; + struct iovec iov; + struct sockaddr_nl nladdr; +#ifdef set_fs + mm_segment_t oldfs; +#endif + char *pg; + int size = 0; + + err = sock_create(AF_NETLINK, SOCK_DGRAM, NETLINK_ROUTE, &sock); + if (err) + { + printk( ": Could not create a datagram socket, error = %d\n", -ENXIO); + return err; + } + + memset(&nladdr, 0, sizeof(nladdr)); + nladdr.nl_family = AF_NETLINK; + + req.nlh.nlmsg_len = sizeof(req); + req.nlh.nlmsg_type = RTM_GETROUTE; + req.nlh.nlmsg_flags = NLM_F_ROOT | NLM_F_MATCH | NLM_F_REQUEST; + req.nlh.nlmsg_pid = 0; + req.g.rtgen_family = AF_INET; + + iov.iov_base = &req; + iov.iov_len = sizeof(req); + + msg.msg_name = &nladdr; + msg.msg_namelen = sizeof(nladdr); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) + /* referece:sock_xmit in kernel code + * WRITE for sock_sendmsg, READ for sock_recvmsg + * third parameter for msg_iovlen + * last parameter for iov_len + */ + iov_iter_init(&msg.msg_iter, WRITE, &iov, 1, sizeof(req)); +#else + msg.msg_iov = &iov; + msg.msg_iovlen = 1; +#endif + msg.msg_control = NULL; + msg.msg_controllen = 0; + msg.msg_flags = MSG_DONTWAIT; + +#ifdef set_fs + oldfs = get_fs(); + set_fs(KERNEL_DS); +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) + err = sock_sendmsg(sock, &msg); +#else + err = sock_sendmsg(sock, &msg, sizeof(req)); +#endif +#ifdef set_fs + set_fs(oldfs); +#endif + + if (err < 0) + goto out_sock; + + pg = (char *) __get_free_page(GFP_KERNEL); + if (pg == NULL) { + err = -ENOMEM; + goto out_sock; + } + +#if defined(CONFIG_IPV6) || defined (CONFIG_IPV6_MODULE) +restart: +#endif + + for (;;) + { + struct nlmsghdr *h; + + iov.iov_base = pg; + iov.iov_len = PAGE_SIZE; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) + iov_iter_init(&msg.msg_iter, READ, &iov, 1, PAGE_SIZE); +#endif + +#ifdef set_fs + oldfs = get_fs(); + set_fs(KERNEL_DS); +#endif + err = sock_recvmsg(sock, &msg, PAGE_SIZE, MSG_DONTWAIT); +#ifdef set_fs + set_fs(oldfs); +#endif + + if (err < 0) + goto out_sock_pg; + + if (msg.msg_flags & MSG_TRUNC) { + err = -ENOBUFS; + goto out_sock_pg; + } + + h = (struct nlmsghdr*) pg; + + while (NLMSG_OK(h, err)) + { + struct route_info rt_info; + if (h->nlmsg_type == NLMSG_DONE) { + err = 0; + goto done; + } + + if (h->nlmsg_type == NLMSG_ERROR) { + struct nlmsgerr *errm = (struct nlmsgerr*) NLMSG_DATA(h); + err = errm->error; + printk( "NLMSG error: %d\n", errm->error); + goto done; + } + + if (h->nlmsg_type == RTM_GETROUTE) + { + printk( "RTM_GETROUTE: NLMSG: %d\n", h->nlmsg_type); + } + if (h->nlmsg_type != RTM_NEWROUTE) { + printk( "NLMSG: %d\n", h->nlmsg_type); + err = -EINVAL; + goto done; + } + + memset(&rt_info, 0, sizeof(struct route_info)); + parse_routes(h, &rt_info); + if(!rt_info.dst_addr.s_addr && rt_info.gateway.s_addr && rt_info.dev_index) + { + *gw_addr = rt_info.gateway.s_addr; + *gw_index = rt_info.dev_index; + + } + h = NLMSG_NEXT(h, err); + } + + if (err) + { + printk( "!!!Remnant of size %d %d %d\n", err, h->nlmsg_len, h->nlmsg_type); + err = -EINVAL; + break; + } + } + +done: +#if defined(CONFIG_IPV6) || defined (CONFIG_IPV6_MODULE) + if (!err && req.g.rtgen_family == AF_INET) { + req.g.rtgen_family = AF_INET6; + + iov.iov_base = &req; + iov.iov_len = sizeof(req); + + msg.msg_name = &nladdr; + msg.msg_namelen = sizeof(nladdr); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 19, 0)) + iov_iter_init(&msg.msg_iter, WRITE, &iov, 1, sizeof(req)); +#else + msg.msg_iov = &iov; + msg.msg_iovlen = 1; +#endif + msg.msg_control = NULL; + msg.msg_controllen = 0; + msg.msg_flags=MSG_DONTWAIT; + +#ifdef set_fs + oldfs = get_fs(); + set_fs(KERNEL_DS); +#endif +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) + err = sock_sendmsg(sock, &msg); +#else + err = sock_sendmsg(sock, &msg, sizeof(req)); +#endif +#ifdef set_fs + set_fs(oldfs); +#endif + + if (err > 0) + goto restart; + } +#endif + +out_sock_pg: + free_page((unsigned long) pg); + +out_sock: + sock_release(sock); + return err; +} + +static int arp_query(unsigned char *haddr, u32 paddr, + struct net_device *dev) +{ + struct neighbour *neighbor_entry; + int ret = 0; + + neighbor_entry = neigh_lookup(&arp_tbl, &paddr, dev); + + if (neighbor_entry != NULL) { + neighbor_entry->used = jiffies; + if (neighbor_entry->nud_state & NUD_VALID) { + _rtw_memcpy(haddr, neighbor_entry->ha, dev->addr_len); + ret = 1; + } + neigh_release(neighbor_entry); + } + return ret; +} + +static int get_defaultgw(u32 *ip_addr ,char mac[]) +{ + int gw_index = 0; // oif device index + struct net_device *gw_dev = NULL; //oif device + + route_dump(ip_addr, &gw_index); + + if( !(*ip_addr) || !gw_index ) + { + //DBG_871X("No default GW \n"); + return -1; + } + + gw_dev = dev_get_by_index(&init_net, gw_index); + + if(gw_dev == NULL) + { + //DBG_871X("get Oif Device Fail \n"); + return -1; + } + + if(!arp_query(mac, *ip_addr, gw_dev)) + { + //DBG_871X( "arp query failed\n"); + dev_put(gw_dev); + return -1; + + } + dev_put(gw_dev); + + return 0; +} + +int rtw_gw_addr_query(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); + u32 gw_addr = 0; // default gw address + unsigned char gw_mac[32] = {0}; // default gw mac + int i; + int res; + + res = get_defaultgw(&gw_addr, gw_mac); + if(!res) + { + pmlmepriv->gw_ip[0] = gw_addr&0xff; + pmlmepriv->gw_ip[1] = (gw_addr&0xff00)>>8; + pmlmepriv->gw_ip[2] = (gw_addr&0xff0000)>>16; + pmlmepriv->gw_ip[3] = (gw_addr&0xff000000)>>24; + _rtw_memcpy(pmlmepriv->gw_mac_addr, gw_mac, 6); + DBG_871X("%s Gateway Mac:\t" MAC_FMT "\n", __FUNCTION__, MAC_ARG(pmlmepriv->gw_mac_addr)); + DBG_871X("%s Gateway IP:\t" IP_FMT "\n", __FUNCTION__, IP_ARG(pmlmepriv->gw_ip)); + } + else + { + DBG_871X("Get Gateway IP/MAC fail!\n"); + } + + return res; +} +#endif + +void rtw_dev_unload(PADAPTER padapter) +{ + struct net_device *pnetdev = (struct net_device*)padapter->pnetdev; + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); + struct dvobj_priv *pobjpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &pobjpriv->drv_dbg; + struct cmd_priv *pcmdpriv = &padapter->cmdpriv; + u8 cnt = 0; + + RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("+%s\n",__FUNCTION__)); + + if (padapter->bup == _TRUE) + { + DBG_871X("===> %s\n",__FUNCTION__); + + rtw_set_drv_stopped(padapter); + #ifdef CONFIG_XMIT_ACK + if (padapter->xmitpriv.ack_tx) + rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_DRV_STOP); + #endif + + if (padapter->intf_stop) + padapter->intf_stop(padapter); + + RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("@ rtw_dev_unload: stop intf complete!\n")); + + if (!pwrctl->bInternalAutoSuspend) + rtw_stop_drv_threads(padapter); + + while(ATOMIC_READ(&(pcmdpriv->cmdthd_running)) == _TRUE){ + if (cnt > 5) { + DBG_871X("stop cmdthd timeout\n"); + break; + } else { + cnt ++; + DBG_871X("cmdthd is running(%d)\n", cnt); + rtw_msleep_os(10); + } + } + + RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("@ %s: stop thread complete!\n",__FUNCTION__)); + + //check the status of IPS + if(rtw_hal_check_ips_status(padapter) == _TRUE || pwrctl->rf_pwrstate == rf_off) { //check HW status and SW state + DBG_871X_LEVEL(_drv_always_, "%s: driver in IPS-FWLPS\n", __func__); + pdbgpriv->dbg_dev_unload_inIPS_cnt++; + } else { + DBG_871X_LEVEL(_drv_always_, "%s: driver not in IPS\n", __func__); + } + + if (!rtw_is_surprise_removed(padapter)) { +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_IpsNotify(padapter, pwrctl->ips_mode_req); +#endif + { + //amy modify 20120221 for power seq is different between driver open and ips + rtw_hal_deinit(padapter); + } + rtw_set_surprise_removed(padapter); + } + RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("@ %s: deinit hal complelt!\n",__FUNCTION__)); + + padapter->bup = _FALSE; + + DBG_871X("<=== %s\n",__FUNCTION__); + } + else { + RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("%s: bup==_FALSE\n",__FUNCTION__)); + DBG_871X("%s: bup==_FALSE\n",__FUNCTION__); + } + + /* cancel timer after thread stop */ + rtw_cancel_all_timer(padapter); + RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("-%s\n",__FUNCTION__)); +} + +int rtw_suspend_free_assoc_resource(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct net_device *pnetdev = padapter->pnetdev; +#ifdef CONFIG_P2P + struct wifidirect_info* pwdinfo = &padapter->wdinfo; +#endif // CONFIG_P2P + + DBG_871X("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter)); + + if (rtw_chk_roam_flags(padapter, RTW_ROAM_ON_RESUME)) { + if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) + && check_fwstate(pmlmepriv, _FW_LINKED) +#ifdef CONFIG_P2P + && rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) +#endif // CONFIG_P2P + ) + { + DBG_871X("%s %s(" MAC_FMT "), length:%d assoc_ssid.length:%d\n",__FUNCTION__, + pmlmepriv->cur_network.network.Ssid.Ssid, + MAC_ARG(pmlmepriv->cur_network.network.MacAddress), + pmlmepriv->cur_network.network.Ssid.SsidLength, + pmlmepriv->assoc_ssid.SsidLength); + rtw_set_to_roam(padapter, 1); + } + } + + if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, _FW_LINKED)) + { + rtw_disassoc_cmd(padapter, 0, _FALSE); + //s2-2. indicate disconnect to os + rtw_indicate_disconnect(padapter, 0, _FALSE); + } + #ifdef CONFIG_AP_MODE + else if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) + { + rtw_sta_flush(padapter, _TRUE); + } + #endif + + //s2-3. + rtw_free_assoc_resources(padapter, 1); + + //s2-4. +#ifdef CONFIG_AUTOSUSPEND + if(is_primary_adapter(padapter) && (!adapter_to_pwrctl(padapter)->bInternalAutoSuspend )) +#endif + rtw_free_network_queue(padapter, _TRUE); + + if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) { + DBG_871X_LEVEL(_drv_always_, "%s: fw_under_survey\n", __func__); + rtw_indicate_scan_done(padapter, 1); + clr_fwstate(pmlmepriv, _FW_UNDER_SURVEY); + } + + if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) + { + DBG_871X_LEVEL(_drv_always_, "%s: fw_under_linking\n", __FUNCTION__); + rtw_indicate_disconnect(padapter, 0, _FALSE); + } + + DBG_871X("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter)); + return _SUCCESS; +} + +int rtw_suspend_normal(_adapter *padapter) +{ + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct net_device *pnetdev = padapter->pnetdev; + #ifdef CONFIG_CONCURRENT_MODE + struct net_device *pbuddy_netdev = padapter->pbuddy_adapter->pnetdev; + #endif + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + int ret = _SUCCESS; + + DBG_871X("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter)); + if(pnetdev){ + netif_carrier_off(pnetdev); + rtw_netif_stop_queue(pnetdev); + } +#ifdef CONFIG_CONCURRENT_MODE + if(rtw_buddy_adapter_up(padapter)){ + pbuddy_netdev = padapter->pbuddy_adapter->pnetdev; + netif_carrier_off(pbuddy_netdev); + rtw_netif_stop_queue(pbuddy_netdev); + } +#endif + + rtw_suspend_free_assoc_resource(padapter); + +#ifdef CONFIG_CONCURRENT_MODE + if(rtw_buddy_adapter_up(padapter)){ + rtw_suspend_free_assoc_resource(padapter->pbuddy_adapter); + } +#endif + rtw_led_control(padapter, LED_CTL_POWER_OFF); + + if ((rtw_hal_check_ips_status(padapter) == _TRUE) + || (adapter_to_pwrctl(padapter)->rf_pwrstate == rf_off)) + { + DBG_871X_LEVEL(_drv_always_, "%s: ### ERROR #### driver in IPS ####ERROR###!!!\n", __FUNCTION__); + + } + +#ifdef CONFIG_CONCURRENT_MODE + if(rtw_buddy_adapter_up(padapter)){ + rtw_dev_unload(padapter->pbuddy_adapter); + } +#endif + rtw_dev_unload(padapter); + + //sdio_deinit(adapter_to_dvobj(padapter)); + if(padapter->intf_deinit) + padapter->intf_deinit(adapter_to_dvobj(padapter)); + + DBG_871X("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter)); + return ret; +} + +int rtw_suspend_common(_adapter *padapter) +{ + struct dvobj_priv *psdpriv = padapter->dvobj; + struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; + struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(psdpriv); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + int ret = 0; + u32 start_time = rtw_get_current_time(); + + DBG_871X_LEVEL(_drv_always_, " suspend start\n"); + DBG_871X("==> %s (%s:%d)\n",__FUNCTION__, current->comm, current->pid); + + pdbgpriv->dbg_suspend_cnt++; + + pwrpriv->bInSuspend = _TRUE; + + while (pwrpriv->bips_processing == _TRUE) + rtw_msleep_os(1); + +#ifdef CONFIG_IOL_READ_EFUSE_MAP + if(!padapter->bup){ + u8 bMacPwrCtrlOn = _FALSE; + rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); + if(bMacPwrCtrlOn) + rtw_hal_power_off(padapter); + } +#endif + + if ((!padapter->bup) || RTW_CANNOT_RUN(padapter)) { + DBG_871X("%s bup=%d bDriverStopped=%s bSurpriseRemoved = %s\n", __func__ + , padapter->bup + , rtw_is_drv_stopped(padapter)?"True":"False" + , rtw_is_surprise_removed(padapter)?"True":"False"); + pdbgpriv->dbg_suspend_error_cnt++; + goto exit; + } + rtw_ps_deny(padapter, PS_DENY_SUSPEND); + + rtw_cancel_all_timer(padapter); +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->pbuddy_adapter){ + rtw_cancel_all_timer(padapter->pbuddy_adapter); + } +#endif // CONFIG_CONCURRENT_MODE + + LeaveAllPowerSaveModeDirect(padapter); + + rtw_stop_cmd_thread(padapter); + +#ifdef CONFIG_BT_COEXIST + // wait for the latest FW to remove this condition. + if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) { + rtw_btcoex_SuspendNotify(padapter, 0); + DBG_871X("WIFI_AP_STATE\n"); +#ifdef CONFIG_CONCURRENT_MODE + } else if (check_buddy_fwstate(padapter, WIFI_AP_STATE)) { + rtw_btcoex_SuspendNotify(padapter, 0); + DBG_871X("P2P_ROLE_GO\n"); +#endif //CONFIG_CONCURRENT_MODE + } else if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) { + rtw_btcoex_SuspendNotify(padapter, 1); + DBG_871X("STATION\n"); + } +#endif // CONFIG_BT_COEXIST + + rtw_ps_deny_cancel(padapter, PS_DENY_SUSPEND); + + if (check_fwstate(pmlmepriv,WIFI_STATION_STATE) == _TRUE +#ifdef CONFIG_CONCURRENT_MODE + && check_buddy_fwstate(padapter, WIFI_AP_STATE) == _FALSE +#endif + ) { + rtw_suspend_normal(padapter); + } else if (check_fwstate(pmlmepriv,WIFI_AP_STATE) == _TRUE +#ifdef CONFIG_CONCURRENT_MODE + && check_buddy_fwstate(padapter, WIFI_AP_STATE) == _FALSE +#endif + ) { + rtw_suspend_normal(padapter); +#ifdef CONFIG_CONCURRENT_MODE + } else if (check_fwstate(pmlmepriv,WIFI_STATION_STATE) == _TRUE + && check_buddy_fwstate(padapter, WIFI_AP_STATE) == _TRUE) { + rtw_suspend_normal(padapter); +#endif + } else { + rtw_suspend_normal(padapter); + } + + + DBG_871X_LEVEL(_drv_always_, "rtw suspend success in %d ms\n", + rtw_get_passing_time_ms(start_time)); + +exit: + DBG_871X("<=== %s return %d.............. in %dms\n", __FUNCTION__ + , ret, rtw_get_passing_time_ms(start_time)); + + return ret; +} + + +int rtw_resume_process_normal(_adapter *padapter) +{ + struct net_device *pnetdev; + #ifdef CONFIG_CONCURRENT_MODE + struct net_device *pbuddy_netdev; + #endif + struct pwrctrl_priv *pwrpriv; + struct mlme_priv *pmlmepriv; + struct dvobj_priv *psdpriv; + struct debug_priv *pdbgpriv; + + int ret = _SUCCESS; +_func_enter_; + + if (!padapter) { + ret = -1; + goto exit; + } + + pnetdev = padapter->pnetdev; + pwrpriv = adapter_to_pwrctl(padapter); + pmlmepriv = &padapter->mlmepriv; + psdpriv = padapter->dvobj; + pdbgpriv = &psdpriv->drv_dbg; + + DBG_871X("==> "FUNC_ADPT_FMT" entry....\n", FUNC_ADPT_ARG(padapter)); + // interface init + //if (sdio_init(adapter_to_dvobj(padapter)) != _SUCCESS) + if((padapter->intf_init)&& (padapter->intf_init(adapter_to_dvobj(padapter)) != _SUCCESS)) + { + ret = -1; + RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s: initialize SDIO Failed!!\n", __FUNCTION__)); + goto exit; + } + rtw_hal_disable_interrupt(padapter); + //if (sdio_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS) + if ((padapter->intf_alloc_irq)&&(padapter->intf_alloc_irq(adapter_to_dvobj(padapter)) != _SUCCESS)) + { + ret = -1; + RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s: sdio_alloc_irq Failed!!\n", __FUNCTION__)); + goto exit; + } + + rtw_reset_drv_sw(padapter); + #ifdef CONFIG_CONCURRENT_MODE + rtw_reset_drv_sw(padapter->pbuddy_adapter); + #endif + + pwrpriv->bkeepfwalive = _FALSE; + + DBG_871X("bkeepfwalive(%x)\n",pwrpriv->bkeepfwalive); + if(pm_netdev_open(pnetdev,_TRUE) != 0) { + ret = -1; + pdbgpriv->dbg_resume_error_cnt++; + goto exit; + } + + netif_device_attach(pnetdev); + netif_carrier_on(pnetdev); + + #ifdef CONFIG_CONCURRENT_MODE + if(rtw_buddy_adapter_up(padapter)){ + pbuddy_netdev = padapter->pbuddy_adapter->pnetdev; + + netif_device_attach(pbuddy_netdev); + netif_carrier_on(pbuddy_netdev); + } + #endif + + + if( padapter->pid[1]!=0) { + DBG_871X("pid[1]:%d\n",padapter->pid[1]); + rtw_signal_process(padapter->pid[1], SIGUSR2); + } + + + if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { + DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(pmlmepriv)); + + if (rtw_chk_roam_flags(padapter, RTW_ROAM_ON_RESUME)) + rtw_roaming(padapter, NULL); + + } else if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { + DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_AP_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(pmlmepriv)); + rtw_ap_restore_network(padapter); + } else if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) { + DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(padapter), get_fwstate(pmlmepriv)); + } else { + DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - ???\n", FUNC_ADPT_ARG(padapter), get_fwstate(pmlmepriv)); + } + + #ifdef CONFIG_CONCURRENT_MODE + if(rtw_buddy_adapter_up(padapter)) + { + _adapter *buddy = padapter->pbuddy_adapter; + struct mlme_priv *buddy_mlme = &padapter->pbuddy_adapter->mlmepriv; + if (check_fwstate(buddy_mlme, WIFI_STATION_STATE)) { + DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_STATION_STATE\n", FUNC_ADPT_ARG(buddy), get_fwstate(buddy_mlme)); + + if (rtw_chk_roam_flags(buddy, RTW_ROAM_ON_RESUME)) + rtw_roaming(buddy, NULL); + + } else if (check_fwstate(buddy_mlme, WIFI_AP_STATE)) { + DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_AP_STATE\n", FUNC_ADPT_ARG(buddy), get_fwstate(buddy_mlme)); + rtw_ap_restore_network(buddy); + } else if (check_fwstate(buddy_mlme, WIFI_ADHOC_STATE)) { + DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - WIFI_ADHOC_STATE\n", FUNC_ADPT_ARG(buddy), get_fwstate(buddy_mlme)); + } else { + DBG_871X(FUNC_ADPT_FMT" fwstate:0x%08x - ???\n", FUNC_ADPT_ARG(buddy), get_fwstate(buddy_mlme)); + } + } + #endif + +#ifdef CONFIG_RESUME_IN_WORKQUEUE + //rtw_unlock_suspend(); +#endif //CONFIG_RESUME_IN_WORKQUEUE + DBG_871X("<== "FUNC_ADPT_FMT" exit....\n", FUNC_ADPT_ARG(padapter)); + +exit: +_func_exit_; + return ret; +} + +int rtw_resume_common(_adapter *padapter) +{ + int ret = 0; + u32 start_time = rtw_get_current_time(); + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + + _func_enter_; + + if (pwrpriv->bInSuspend == _FALSE) + return 0; + + DBG_871X_LEVEL(_drv_always_, "resume start\n"); + DBG_871X("==> %s (%s:%d)\n",__FUNCTION__, current->comm, current->pid); + + if (check_fwstate(pmlmepriv,WIFI_STATION_STATE) == _TRUE +#ifdef CONFIG_CONCURRENT_MODE + && check_buddy_fwstate(padapter, WIFI_AP_STATE) == _FALSE +#endif + ) { + rtw_resume_process_normal(padapter); + + } else if (check_fwstate(pmlmepriv,WIFI_AP_STATE) == _TRUE +#ifdef CONFIG_CONCURRENT_MODE + && check_buddy_fwstate(padapter, WIFI_AP_STATE) == _FALSE +#endif + ) { + rtw_resume_process_normal(padapter); +#ifdef CONFIG_CONCURRENT_MODE + } else if (check_fwstate(pmlmepriv,WIFI_STATION_STATE) == _TRUE + && check_buddy_fwstate(padapter, WIFI_AP_STATE) == _TRUE) { + rtw_resume_process_normal(padapter); +#endif + } else { + rtw_resume_process_normal(padapter); + } + + #ifdef CONFIG_BT_COEXIST + rtw_btcoex_SuspendNotify(padapter, 0); + #endif // CONFIG_BT_COEXIST + + if (pwrpriv) { + pwrpriv->bInSuspend = _FALSE; + #ifdef CONFIG_PNO_SUPPORT + pwrpriv->pno_in_resume = _FALSE; + #endif + } + DBG_871X_LEVEL(_drv_always_, "%s:%d in %d ms\n", __FUNCTION__ ,ret, + rtw_get_passing_time_ms(start_time)); + + _func_exit_; + + return ret; +} + +#ifdef CONFIG_GPIO_API +u8 rtw_get_gpio(struct net_device *netdev, u8 gpio_num) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(netdev); + return rtw_hal_get_gpio(adapter, gpio_num); +} +EXPORT_SYMBOL(rtw_get_gpio); + +int rtw_set_gpio_output_value(struct net_device *netdev, u8 gpio_num, bool isHigh) +{ + u8 direction = 0; + u8 res = -1; + _adapter *adapter = (_adapter *)rtw_netdev_priv(netdev); + return rtw_hal_set_gpio_output_value(adapter, gpio_num,isHigh); +} +EXPORT_SYMBOL(rtw_set_gpio_output_value); + +int rtw_config_gpio(struct net_device *netdev, u8 gpio_num, bool isOutput) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(netdev); + return rtw_hal_config_gpio(adapter,gpio_num,isOutput); +} +EXPORT_SYMBOL(rtw_config_gpio); +int rtw_register_gpio_interrupt(struct net_device *netdev, int gpio_num, void(*callback)(u8 level)) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(netdev); + return rtw_hal_register_gpio_interrupt(adapter,gpio_num,callback); +} +EXPORT_SYMBOL(rtw_register_gpio_interrupt); + +int rtw_disable_gpio_interrupt(struct net_device *netdev, int gpio_num) +{ + _adapter *adapter = (_adapter *)rtw_netdev_priv(netdev); + return rtw_hal_disable_gpio_interrupt(adapter,gpio_num); +} +EXPORT_SYMBOL(rtw_disable_gpio_interrupt); + +#endif //#ifdef CONFIG_GPIO_API + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/recv_linux.c b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/recv_linux.c new file mode 100644 index 000000000..e37f01483 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/recv_linux.c @@ -0,0 +1,815 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _RECV_OSDEP_C_ + +#include + +int rtw_os_alloc_recvframe(_adapter *padapter, union recv_frame *precvframe, u8 *pdata, _pkt *pskb) +{ + int res = _SUCCESS; + u8 shift_sz = 0; + u32 skb_len, alloc_sz; + _pkt *pkt_copy = NULL; + struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib; + + + if(pdata == NULL) + { + precvframe->u.hdr.pkt = NULL; + res = _FAIL; + return res; + } + + + // Modified by Albert 20101213 + // For 8 bytes IP header alignment. + shift_sz = pattrib->qos ? 6:0;// Qos data, wireless lan header length is 26 + + skb_len = pattrib->pkt_len; + + // for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet. + // modify alloc_sz for recvive crc error packet by thomas 2011-06-02 + if((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)) + { + //alloc_sz = 1664; //1664 is 128 alignment. + alloc_sz = (skb_len <= 1650) ? 1664:(skb_len + 14); + } + else + { + alloc_sz = skb_len; + // 6 is for IP header 8 bytes alignment in QoS packet case. + // 8 is for skb->data 4 bytes alignment. + alloc_sz += 14; + } + + pkt_copy = rtw_skb_alloc(alloc_sz); + + if(pkt_copy) + { + pkt_copy->dev = padapter->pnetdev; + precvframe->u.hdr.pkt = pkt_copy; + precvframe->u.hdr.rx_head = pkt_copy->data; + precvframe->u.hdr.rx_end = pkt_copy->data + alloc_sz; + skb_reserve(pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data) & 7 ));//force pkt_copy->data at 8-byte alignment address + skb_reserve(pkt_copy, shift_sz);//force ip_hdr at 8-byte alignment address according to shift_sz. + _rtw_memcpy(pkt_copy->data, pdata, skb_len); + precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pkt_copy->data; + } + else + { +#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX + DBG_871X("%s:can not allocate memory for skb copy\n", __FUNCTION__); + + precvframe->u.hdr.pkt = NULL; + + //rtw_free_recvframe(precvframe, pfree_recv_queue); + //goto _exit_recvbuf2recvframe; + + res = _FAIL; +#else + if((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)) + { + DBG_871X("%s: alloc_skb fail , drop frag frame \n", __FUNCTION__); + //rtw_free_recvframe(precvframe, pfree_recv_queue); + res = _FAIL; + goto exit_rtw_os_recv_resource_alloc; + } + + if(pskb == NULL) + { + res = _FAIL; + goto exit_rtw_os_recv_resource_alloc; + } + + precvframe->u.hdr.pkt = rtw_skb_clone(pskb); + if(precvframe->u.hdr.pkt) + { + precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pdata; + precvframe->u.hdr.rx_end = pdata + alloc_sz; + } + else + { + DBG_871X("%s: rtw_skb_clone fail\n", __FUNCTION__); + //rtw_free_recvframe(precvframe, pfree_recv_queue); + //goto _exit_recvbuf2recvframe; + res = _FAIL; + } +#endif + } + +exit_rtw_os_recv_resource_alloc: + + return res; + +} + +void rtw_os_free_recvframe(union recv_frame *precvframe) +{ + if(precvframe->u.hdr.pkt) + { + rtw_skb_free(precvframe->u.hdr.pkt);//free skb by driver + + precvframe->u.hdr.pkt = NULL; + } +} + +//init os related resource in struct recv_priv +int rtw_os_recv_resource_init(struct recv_priv *precvpriv, _adapter *padapter) +{ + int res=_SUCCESS; + + return res; +} + +//alloc os related resource in union recv_frame +int rtw_os_recv_resource_alloc(_adapter *padapter, union recv_frame *precvframe) +{ + int res=_SUCCESS; + + precvframe->u.hdr.pkt_newalloc = precvframe->u.hdr.pkt = NULL; + + return res; +} + +//free os related resource in union recv_frame +void rtw_os_recv_resource_free(struct recv_priv *precvpriv) +{ + sint i; + union recv_frame *precvframe; + precvframe = (union recv_frame*) precvpriv->precv_frame_buf; + + for(i=0; i < NR_RECVFRAME; i++) + { + if(precvframe->u.hdr.pkt) + { + rtw_skb_free(precvframe->u.hdr.pkt);//free skb by driver + precvframe->u.hdr.pkt = NULL; + } + precvframe++; + } +} + +//alloc os related resource in struct recv_buf +int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf) +{ + int res=_SUCCESS; + +#ifdef CONFIG_USB_HCI + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct usb_device *pusbd = pdvobjpriv->pusbdev; + + precvbuf->irp_pending = _FALSE; + precvbuf->purb = usb_alloc_urb(0, GFP_KERNEL); + if(precvbuf->purb == NULL){ + res = _FAIL; + } + + precvbuf->pskb = NULL; + + precvbuf->pallocated_buf = precvbuf->pbuf = NULL; + + precvbuf->pdata = precvbuf->phead = precvbuf->ptail = precvbuf->pend = NULL; + + precvbuf->transfer_len = 0; + + precvbuf->len = 0; + + #ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX + precvbuf->pallocated_buf = rtw_usb_buffer_alloc(pusbd, (size_t)precvbuf->alloc_sz, &precvbuf->dma_transfer_addr); + precvbuf->pbuf = precvbuf->pallocated_buf; + if(precvbuf->pallocated_buf == NULL) + return _FAIL; + #endif //CONFIG_USE_USB_BUFFER_ALLOC_RX + +#endif //CONFIG_USB_HCI + + return res; +} + +//free os related resource in struct recv_buf +int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf) +{ + int ret = _SUCCESS; + +#ifdef CONFIG_USB_HCI + +#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX + + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct usb_device *pusbd = pdvobjpriv->pusbdev; + + rtw_usb_buffer_free(pusbd, (size_t)precvbuf->alloc_sz, precvbuf->pallocated_buf, precvbuf->dma_transfer_addr); + precvbuf->pallocated_buf = NULL; + precvbuf->dma_transfer_addr = 0; + +#endif //CONFIG_USE_USB_BUFFER_ALLOC_RX + + if(precvbuf->purb) + { + //usb_kill_urb(precvbuf->purb); + usb_free_urb(precvbuf->purb); + } + +#endif //CONFIG_USB_HCI + + + if(precvbuf->pskb) + { +#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER + if(rtw_free_skb_premem(precvbuf->pskb)!=0) +#endif + rtw_skb_free(precvbuf->pskb); + } + return ret; + +} + +_pkt *rtw_os_alloc_msdu_pkt(union recv_frame *prframe, u16 nSubframe_Length, u8 *pdata) +{ + u16 eth_type; + u8 *data_ptr; + _pkt *sub_skb; + struct rx_pkt_attrib *pattrib; + + pattrib = &prframe->u.hdr.attrib; + +#ifdef CONFIG_SKB_COPY + sub_skb = rtw_skb_alloc(nSubframe_Length + 12); + if(sub_skb) + { + skb_reserve(sub_skb, 12); + data_ptr = (u8 *)skb_put(sub_skb, nSubframe_Length); + _rtw_memcpy(data_ptr, (pdata + ETH_HLEN), nSubframe_Length); + } + else +#endif // CONFIG_SKB_COPY + { + sub_skb = rtw_skb_clone(prframe->u.hdr.pkt); + if(sub_skb) + { + sub_skb->data = pdata + ETH_HLEN; + sub_skb->len = nSubframe_Length; + skb_set_tail_pointer(sub_skb, nSubframe_Length); + } + else + { + DBG_871X("%s(): rtw_skb_clone() Fail!!!\n",__FUNCTION__); + return NULL; + } + } + + eth_type = RTW_GET_BE16(&sub_skb->data[6]); + + if (sub_skb->len >= 8 && + ((_rtw_memcmp(sub_skb->data, rtw_rfc1042_header, SNAP_SIZE) && + eth_type != ETH_P_AARP && eth_type != ETH_P_IPX) || + _rtw_memcmp(sub_skb->data, rtw_bridge_tunnel_header, SNAP_SIZE) )) { + /* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */ + skb_pull(sub_skb, SNAP_SIZE); + _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->src, ETH_ALEN); + _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->dst, ETH_ALEN); + } else { + u16 len; + /* Leave Ethernet header part of hdr and full payload */ + len = htons(sub_skb->len); + _rtw_memcpy(skb_push(sub_skb, 2), &len, 2); + _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->src, ETH_ALEN); + _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->dst, ETH_ALEN); + } + + return sub_skb; +} + +#ifdef DBG_UDP_PKT_LOSE_11AC +#define PAYLOAD_LEN_LOC_OF_IP_HDR 0x10 /*ethernet payload length location of ip header (DA+SA+eth_type+(version&hdr_len)) */ +#endif + +void rtw_os_recv_indicate_pkt(_adapter *padapter, _pkt *pkt, struct rx_pkt_attrib *pattrib) +{ + struct mlme_priv*pmlmepriv = &padapter->mlmepriv; + struct recv_priv *precvpriv = &(padapter->recvpriv); +#ifdef CONFIG_BR_EXT + void *br_port = NULL; +#endif + int ret; + + /* Indicat the packets to upper layer */ + if (pkt) { + if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) + { + _pkt *pskb2=NULL; + struct sta_info *psta = NULL; + struct sta_priv *pstapriv = &padapter->stapriv; + int bmcast = IS_MCAST(pattrib->dst); + + //DBG_871X("bmcast=%d\n", bmcast); + + if (_rtw_memcmp(pattrib->dst, adapter_mac_addr(padapter), ETH_ALEN) == _FALSE) + { + //DBG_871X("not ap psta=%p, addr=%pM\n", psta, pattrib->dst); + + if(bmcast) + { + psta = rtw_get_bcmc_stainfo(padapter); + pskb2 = rtw_skb_clone(pkt); + } else { + psta = rtw_get_stainfo(pstapriv, pattrib->dst); + } + + if(psta) + { + struct net_device *pnetdev= (struct net_device*)padapter->pnetdev; + + //DBG_871X("directly forwarding to the rtw_xmit_entry\n"); + + //skb->ip_summed = CHECKSUM_NONE; + pkt->dev = pnetdev; +#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) + skb_set_queue_mapping(pkt, rtw_recv_select_queue(pkt)); +#endif //LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35) + + _rtw_xmit_entry(pkt, pnetdev); + + if(bmcast && (pskb2 != NULL) ) { + pkt = pskb2; + DBG_COUNTER(padapter->rx_logs.os_indicate_ap_mcast); + } else { + DBG_COUNTER(padapter->rx_logs.os_indicate_ap_forward); + return; + } + } + } + else// to APself + { + //DBG_871X("to APSelf\n"); + DBG_COUNTER(padapter->rx_logs.os_indicate_ap_self); + } + } + +#ifdef CONFIG_BR_EXT + // Insert NAT2.5 RX here! +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) + br_port = padapter->pnetdev->br_port; +#else // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) + rcu_read_lock(); + br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); + rcu_read_unlock(); +#endif // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) + + + if( br_port && (check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) ) + { + int nat25_handle_frame(_adapter *priv, struct sk_buff *skb); + if (nat25_handle_frame(padapter, pkt) == -1) { + //priv->ext_stats.rx_data_drops++; + //DEBUG_ERR("RX DROP: nat25_handle_frame fail!\n"); + //return FAIL; + +#if 1 + // bypass this frame to upper layer!! +#else + rtw_skb_free(sub_skb); + continue; +#endif + } + } +#endif // CONFIG_BR_EXT + if( precvpriv->sink_udpport > 0) + rtw_sink_rtp_seq_dbg(padapter,pkt); +#ifdef DBG_UDP_PKT_LOSE_11AC + /* After eth_type_trans process , pkt->data pointer will move from ethrnet header to ip header , + * we have to check ethernet type , so this debug must be print before eth_type_trans + */ + if (*((unsigned short *)(pkt->data+ETH_ALEN*2)) == htons(ETH_P_ARP)) { + /* ARP Payload length will be 42bytes or 42+18(tailer)=60bytes*/ + if (pkt->len != 42 && pkt->len != 60) + DBG_871X("Error !!%s,ARP Payload length %u not correct\n" , __func__ , pkt->len); + } else if (*((unsigned short *)(pkt->data+ETH_ALEN*2)) == htons(ETH_P_IP)) { + if (be16_to_cpu(*((u16 *)(pkt->data+PAYLOAD_LEN_LOC_OF_IP_HDR))) != (pkt->len)-ETH_HLEN) { + DBG_871X("Error !!%s,Payload length not correct\n" , __func__); + DBG_871X("%s, IP header describe Total length=%u\n" , __func__ , be16_to_cpu(*((u16 *)(pkt->data+PAYLOAD_LEN_LOC_OF_IP_HDR)))); + DBG_871X("%s, Pkt real length=%u\n" , __func__ , (pkt->len)-ETH_HLEN); + } + } +#endif + /* After eth_type_trans process , pkt->data pointer will move from ethrnet header to ip header */ + pkt->protocol = eth_type_trans(pkt, padapter->pnetdev); + pkt->dev = padapter->pnetdev; + +#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX + if ( (pattrib->tcpchk_valid == 1) && (pattrib->tcp_chkrpt == 1) ) { + pkt->ip_summed = CHECKSUM_UNNECESSARY; + } else { + pkt->ip_summed = CHECKSUM_NONE; + } +#else /* !CONFIG_TCP_CSUM_OFFLOAD_RX */ + pkt->ip_summed = CHECKSUM_NONE; +#endif //CONFIG_TCP_CSUM_OFFLOAD_RX + + ret = rtw_netif_rx(padapter->pnetdev, pkt); + if (ret == NET_RX_SUCCESS) + DBG_COUNTER(padapter->rx_logs.os_netif_ok); + else + DBG_COUNTER(padapter->rx_logs.os_netif_err); + } +} + +void rtw_handle_tkip_mic_err(_adapter *padapter, struct sta_info *sta, u8 bgroup) +{ +#ifdef CONFIG_IOCTL_CFG80211 + enum nl80211_key_type key_type = 0; +#endif + union iwreq_data wrqu; + struct iw_michaelmicfailure ev; + struct mlme_priv* pmlmepriv = &padapter->mlmepriv; + struct security_priv *psecuritypriv = &padapter->securitypriv; + u32 cur_time = 0; + + if( psecuritypriv->last_mic_err_time == 0 ) + { + psecuritypriv->last_mic_err_time = rtw_get_current_time(); + } + else + { + cur_time = rtw_get_current_time(); + + if( cur_time - psecuritypriv->last_mic_err_time < 60*HZ ) + { + psecuritypriv->btkip_countermeasure = _TRUE; + psecuritypriv->last_mic_err_time = 0; + psecuritypriv->btkip_countermeasure_time = cur_time; + } + else + { + psecuritypriv->last_mic_err_time = rtw_get_current_time(); + } + } + +#ifdef CONFIG_IOCTL_CFG80211 + if ( bgroup ) + { + key_type |= NL80211_KEYTYPE_GROUP; + } + else + { + key_type |= NL80211_KEYTYPE_PAIRWISE; + } + + cfg80211_michael_mic_failure(padapter->pnetdev, sta->hwaddr, key_type, -1, NULL, GFP_ATOMIC); +#endif + + _rtw_memset( &ev, 0x00, sizeof( ev ) ); + if ( bgroup ) + { + ev.flags |= IW_MICFAILURE_GROUP; + } + else + { + ev.flags |= IW_MICFAILURE_PAIRWISE; + } + + ev.src_addr.sa_family = ARPHRD_ETHER; + _rtw_memcpy(ev.src_addr.sa_data, sta->hwaddr, ETH_ALEN); + + _rtw_memset( &wrqu, 0x00, sizeof( wrqu ) ); + wrqu.data.length = sizeof( ev ); + +#ifndef CONFIG_IOCTL_CFG80211 + wireless_send_event( padapter->pnetdev, IWEVMICHAELMICFAILURE, &wrqu, (char*) &ev ); +#endif +} + +void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame) +{ +#ifdef CONFIG_HOSTAPD_MLME + _pkt *skb; + struct hostapd_priv *phostapdpriv = padapter->phostapdpriv; + struct net_device *pmgnt_netdev = phostapdpriv->pmgnt_netdev; + + RT_TRACE(_module_recv_osdep_c_, _drv_info_, ("+rtw_hostapd_mlme_rx\n")); + + skb = precv_frame->u.hdr.pkt; + + if (skb == NULL) + return; + + skb->data = precv_frame->u.hdr.rx_data; + skb->tail = precv_frame->u.hdr.rx_tail; + skb->len = precv_frame->u.hdr.len; + + //pskb_copy = rtw_skb_copy(skb); +// if(skb == NULL) goto _exit; + + skb->dev = pmgnt_netdev; + skb->ip_summed = CHECKSUM_NONE; + skb->pkt_type = PACKET_OTHERHOST; + //skb->protocol = __constant_htons(0x0019); /*ETH_P_80211_RAW*/ + skb->protocol = __constant_htons(0x0003); /*ETH_P_80211_RAW*/ + + //DBG_871X("(1)data=0x%x, head=0x%x, tail=0x%x, mac_header=0x%x, len=%d\n", skb->data, skb->head, skb->tail, skb->mac_header, skb->len); + + //skb->mac.raw = skb->data; + skb_reset_mac_header(skb); + + //skb_pull(skb, 24); + _rtw_memset(skb->cb, 0, sizeof(skb->cb)); + + rtw_netif_rx(pmgnt_netdev, skb); + + precv_frame->u.hdr.pkt = NULL; // set pointer to NULL before rtw_free_recvframe() if call rtw_netif_rx() +#endif +} + +#ifdef CONFIG_AUTO_AP_MODE +static void rtw_os_ksocket_send(_adapter *padapter, union recv_frame *precv_frame) +{ + _pkt *skb = precv_frame->u.hdr.pkt; + struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; + struct sta_info *psta = precv_frame->u.hdr.psta; + + DBG_871X("eth rx: got eth_type=0x%x\n", pattrib->eth_type); + + if (psta && psta->isrc && psta->pid>0) + { + u16 rx_pid; + + rx_pid = *(u16*)(skb->data+ETH_HLEN); + + DBG_871X("eth rx(pid=0x%x): sta("MAC_FMT") pid=0x%x\n", + rx_pid, MAC_ARG(psta->hwaddr), psta->pid); + + if(rx_pid == psta->pid) + { + int i; + u16 len = *(u16*)(skb->data+ETH_HLEN+2); + //u16 ctrl_type = *(u16*)(skb->data+ETH_HLEN+4); + + //DBG_871X("eth, RC: len=0x%x, ctrl_type=0x%x\n", len, ctrl_type); + DBG_871X("eth, RC: len=0x%x\n", len); + + for(i=0;idata+ETH_HLEN+4+i)); + //DBG_871X("0x%x\n", *(skb->data+ETH_HLEN+6+i)); + + DBG_871X("eth, RC-end\n"); + +#if 0 + //send_sz = ksocket_send(padapter->ksock_send, &padapter->kaddr_send, (skb->data+ETH_HLEN+2), len); + rtw_recv_ksocket_send_cmd(padapter, (skb->data+ETH_HLEN+2), len); + + //DBG_871X("ksocket_send size=%d\n", send_sz); +#endif + } + + } + +} +#endif //CONFIG_AUTO_AP_MODE + +int rtw_recv_monitor(_adapter *padapter, union recv_frame *precv_frame) +{ + int ret = _FAIL; + struct recv_priv *precvpriv; + _queue *pfree_recv_queue; + _pkt *skb; + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + struct rx_pkt_attrib *pattrib; + + if (NULL == precv_frame) + goto _recv_drop; + + pattrib = &precv_frame->u.hdr.attrib; + precvpriv = &(padapter->recvpriv); + pfree_recv_queue = &(precvpriv->free_recv_queue); + + skb = precv_frame->u.hdr.pkt; + if (skb == NULL) { + DBG_871X("%s :skb==NULL something wrong!!!!\n", __func__); + goto _recv_drop; + } + + skb->data = precv_frame->u.hdr.rx_data; + skb_set_tail_pointer(skb, precv_frame->u.hdr.len); + skb->len = precv_frame->u.hdr.len; + skb->ip_summed = CHECKSUM_NONE; + skb->pkt_type = PACKET_OTHERHOST; + skb->protocol = htons(0x0019); /* ETH_P_80211_RAW */ + + rtw_netif_rx(padapter->pnetdev, skb); + + /* pointers to NULL before rtw_free_recvframe() */ + precv_frame->u.hdr.pkt = NULL; + + ret = _SUCCESS; + +_recv_drop: + + /* enqueue back to free_recv_queue */ + if (precv_frame) + rtw_free_recvframe(precv_frame, pfree_recv_queue); + + return ret; + +} + +int rtw_recv_indicatepkt(_adapter *padapter, union recv_frame *precv_frame) +{ + struct recv_priv *precvpriv; + _queue *pfree_recv_queue; + _pkt *skb; + struct mlme_priv*pmlmepriv = &padapter->mlmepriv; + struct rx_pkt_attrib *pattrib; + + if(NULL == precv_frame) + goto _recv_indicatepkt_drop; + + DBG_COUNTER(padapter->rx_logs.os_indicate); + pattrib = &precv_frame->u.hdr.attrib; + precvpriv = &(padapter->recvpriv); + pfree_recv_queue = &(precvpriv->free_recv_queue); + +#ifdef CONFIG_DRVEXT_MODULE + if (drvext_rx_handler(padapter, precv_frame->u.hdr.rx_data, precv_frame->u.hdr.len) == _SUCCESS) + { + goto _recv_indicatepkt_drop; + } +#endif + +#ifdef CONFIG_WAPI_SUPPORT + if (rtw_wapi_check_for_drop(padapter,precv_frame)) + { + WAPI_TRACE(WAPI_ERR, "%s(): Rx Reorder Drop case!!\n", __FUNCTION__); + goto _recv_indicatepkt_drop; + } +#endif + + skb = precv_frame->u.hdr.pkt; + if(skb == NULL) + { + RT_TRACE(_module_recv_osdep_c_,_drv_err_,("rtw_recv_indicatepkt():skb==NULL something wrong!!!!\n")); + goto _recv_indicatepkt_drop; + } + + RT_TRACE(_module_recv_osdep_c_,_drv_info_,("rtw_recv_indicatepkt():skb != NULL !!!\n")); + RT_TRACE(_module_recv_osdep_c_,_drv_info_,("rtw_recv_indicatepkt():precv_frame->u.hdr.rx_head=%p precv_frame->hdr.rx_data=%p\n", precv_frame->u.hdr.rx_head, precv_frame->u.hdr.rx_data)); + RT_TRACE(_module_recv_osdep_c_,_drv_info_,("precv_frame->hdr.rx_tail=%p precv_frame->u.hdr.rx_end=%p precv_frame->hdr.len=%d \n", precv_frame->u.hdr.rx_tail, precv_frame->u.hdr.rx_end, precv_frame->u.hdr.len)); + + skb->data = precv_frame->u.hdr.rx_data; + + skb_set_tail_pointer(skb, precv_frame->u.hdr.len); + + skb->len = precv_frame->u.hdr.len; + + RT_TRACE(_module_recv_osdep_c_,_drv_info_,("\n skb->head=%p skb->data=%p skb->tail=%p skb->end=%p skb->len=%d\n", skb->head, skb->data, skb_tail_pointer(skb), skb_end_pointer(skb), skb->len)); + + if (pattrib->eth_type == 0x888e) + DBG_871X_LEVEL(_drv_always_, "recv eapol packet\n"); + +#ifdef CONFIG_AUTO_AP_MODE +#if 1 //for testing +#if 1 + if (0x8899 == pattrib->eth_type) + { + rtw_os_ksocket_send(padapter, precv_frame); + + //goto _recv_indicatepkt_drop; + } +#else + if (0x8899 == pattrib->eth_type) + { + rtw_auto_ap_mode_rx(padapter, precv_frame); + + goto _recv_indicatepkt_end; + } +#endif +#endif +#endif //CONFIG_AUTO_AP_MODE + + /* TODO: move to core */ + { + _pkt *pkt = skb; + struct ethhdr *etherhdr = (struct ethhdr *)pkt->data; + struct sta_info *sta = precv_frame->u.hdr.psta; + + if (!sta) + goto bypass_session_tracker; + + if (ntohs(etherhdr->h_proto) == ETH_P_IP) { + u8 *ip = pkt->data + 14; + + if (GET_IPV4_PROTOCOL(ip) == 0x06 /* TCP */ + && rtw_st_ctl_chk_reg_s_proto(&sta->st_ctl, 0x06) == _TRUE + ) { + u8 *tcp = ip + GET_IPV4_IHL(ip) * 4; + + if (rtw_st_ctl_chk_reg_rule(&sta->st_ctl, padapter, IPV4_DST(ip), TCP_DST(tcp), IPV4_SRC(ip), TCP_SRC(tcp)) == _TRUE) { + if (GET_TCP_SYN(tcp) && GET_TCP_ACK(tcp)) { + session_tracker_add_cmd(padapter, sta + , IPV4_DST(ip), TCP_DST(tcp) + , IPV4_SRC(ip), TCP_SRC(tcp)); + if (DBG_SESSION_TRACKER) + DBG_871X(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" SYN-ACK\n" + , FUNC_ADPT_ARG(padapter) + , IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp)) + , IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp))); + } + if (GET_TCP_FIN(tcp)) { + session_tracker_del_cmd(padapter, sta + , IPV4_DST(ip), TCP_DST(tcp) + , IPV4_SRC(ip), TCP_SRC(tcp)); + if (DBG_SESSION_TRACKER) + DBG_871X(FUNC_ADPT_FMT" local:"IP_FMT":"PORT_FMT", remote:"IP_FMT":"PORT_FMT" FIN\n" + , FUNC_ADPT_ARG(padapter) + , IP_ARG(IPV4_DST(ip)), PORT_ARG(TCP_DST(tcp)) + , IP_ARG(IPV4_SRC(ip)), PORT_ARG(TCP_SRC(tcp))); + } + } + + } + } +bypass_session_tracker: + ; + } + + rtw_os_recv_indicate_pkt(padapter, skb, pattrib); + +_recv_indicatepkt_end: + + precv_frame->u.hdr.pkt = NULL; // pointers to NULL before rtw_free_recvframe() + + rtw_free_recvframe(precv_frame, pfree_recv_queue); + + RT_TRACE(_module_recv_osdep_c_,_drv_info_,("\n rtw_recv_indicatepkt :after rtw_os_recv_indicate_pkt!!!!\n")); + + + return _SUCCESS; + +_recv_indicatepkt_drop: + + //enqueue back to free_recv_queue + if(precv_frame) + rtw_free_recvframe(precv_frame, pfree_recv_queue); + + DBG_COUNTER(padapter->rx_logs.os_indicate_err); + + return _FAIL; + +} + +void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf) +{ + struct recv_priv *precvpriv = &padapter->recvpriv; + +#ifdef CONFIG_USB_HCI + + precvbuf->ref_cnt--; + + //free skb in recv_buf + rtw_skb_free(precvbuf->pskb); + + precvbuf->pskb = NULL; + + if(precvbuf->irp_pending == _FALSE) + { + rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); + } + + +#endif +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + precvbuf->pskb = NULL; +#endif + +} +void _rtw_reordering_ctrl_timeout_handler (void *FunctionContext); +void _rtw_reordering_ctrl_timeout_handler (void *FunctionContext) +{ + struct recv_reorder_ctrl *preorder_ctrl = (struct recv_reorder_ctrl *)FunctionContext; + rtw_reordering_ctrl_timeout_handler(preorder_ctrl); +} + +void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl) +{ + _adapter *padapter = preorder_ctrl->padapter; + + _init_timer(&(preorder_ctrl->reordering_ctrl_timer), padapter->pnetdev, _rtw_reordering_ctrl_timeout_handler, preorder_ctrl); + +} + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/rtw_proc.c b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/rtw_proc.c new file mode 100644 index 000000000..4038a9684 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/rtw_proc.c @@ -0,0 +1,2196 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + +#include /* tolower() */ +#include +#include +#include "rtw_proc.h" +#ifdef CONFIG_BT_COEXIST +#include +#endif + +#ifdef CONFIG_PROC_DEBUG + +static struct proc_dir_entry *rtw_proc = NULL; + +inline struct proc_dir_entry *get_rtw_drv_proc(void) +{ + return rtw_proc; +} + +#define RTW_PROC_NAME DRV_NAME + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,9,0)) +#define file_inode(file) ((file)->f_dentry->d_inode) +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0)) +#define PDE_DATA(inode) PDE((inode))->data +#define proc_get_parent_data(inode) PDE((inode))->parent->data +#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0)) +#define PDE_DATA(inode) pde_data(inode) +#endif + +#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) +#define get_proc_net proc_net +#else +#define get_proc_net init_net.proc_net +#endif + +inline struct proc_dir_entry *rtw_proc_create_dir(const char *name, struct proc_dir_entry *parent, void *data) +{ + struct proc_dir_entry *entry; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0)) + entry = proc_mkdir_data(name, S_IRUGO|S_IXUGO, parent, data); +#else + //entry = proc_mkdir_mode(name, S_IRUGO|S_IXUGO, parent); + entry = proc_mkdir(name, parent); + if (entry) + entry->data = data; +#endif + + return entry; +} + +inline struct proc_dir_entry *rtw_proc_create_entry(const char *name, struct proc_dir_entry *parent, +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0)) + const struct file_operations *fops, +#else + const struct proc_ops *fops, +#endif + void * data) +{ + struct proc_dir_entry *entry; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)) + entry = proc_create_data(name, S_IFREG|S_IRUGO|S_IWUGO, parent, fops, data); +#else + entry = create_proc_entry(name, S_IFREG|S_IRUGO|S_IWUGO, parent); + if (entry) { + entry->data = data; + entry->proc_fops = fops; + } +#endif + + return entry; +} + +static int proc_get_dummy(struct seq_file *m, void *v) +{ + return 0; +} + +static int proc_get_drv_version(struct seq_file *m, void *v) +{ + dump_drv_version(m); + return 0; +} + +static int proc_get_log_level(struct seq_file *m, void *v) +{ + dump_log_level(m); + return 0; +} + +static int proc_get_drv_cfg(struct seq_file *m, void *v) +{ + dump_drv_cfg(m); + return 0; +} + +static ssize_t proc_set_log_level(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + char tmp[32]; + int log_level; + + if (count < 1) + return -EINVAL; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%d ", &log_level); + + if( log_level >= _drv_always_ && log_level <= _drv_debug_ ) + { + GlobalDebugLevel= log_level; + printk("%d\n", GlobalDebugLevel); + } + } else { + return -EFAULT; + } + + return count; +} + +#ifdef DBG_MEM_ALLOC +static int proc_get_mstat(struct seq_file *m, void *v) +{ + rtw_mstat_dump(m); + return 0; +} +#endif /* DBG_MEM_ALLOC */ + +static int proc_get_country_chplan_map(struct seq_file *m, void *v) +{ + dump_country_chplan_map(m); + return 0; +} + +static int proc_get_chplan_id_list(struct seq_file *m, void *v) +{ + dump_chplan_id_list(m); + return 0; +} + +static int proc_get_chplan_test(struct seq_file *m, void *v) +{ + dump_chplan_test(m); + return 0; +} + +/* +* rtw_drv_proc: +* init/deinit when register/unregister driver +*/ +const struct rtw_proc_hdl drv_proc_hdls [] = { + {"ver_info", proc_get_drv_version, NULL}, + {"log_level", proc_get_log_level, proc_set_log_level}, + {"drv_cfg", proc_get_drv_cfg, NULL}, +#ifdef DBG_MEM_ALLOC + {"mstat", proc_get_mstat, NULL}, +#endif /* DBG_MEM_ALLOC */ + {"country_chplan_map", proc_get_country_chplan_map, NULL}, + {"chplan_id_list", proc_get_chplan_id_list, NULL}, + {"chplan_test", proc_get_chplan_test, NULL}, +}; + +const int drv_proc_hdls_num = sizeof(drv_proc_hdls) / sizeof(struct rtw_proc_hdl); + +static int rtw_drv_proc_open(struct inode *inode, struct file *file) +{ + //struct net_device *dev = proc_get_parent_data(inode); + ssize_t index = (ssize_t)PDE_DATA(inode); + const struct rtw_proc_hdl *hdl = drv_proc_hdls+index; + return single_open(file, hdl->show, NULL); +} + +static ssize_t rtw_drv_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos) +{ + ssize_t index = (ssize_t)PDE_DATA(file_inode(file)); + const struct rtw_proc_hdl *hdl = drv_proc_hdls+index; + ssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write; + + if (write) + return write(file, buffer, count, pos, NULL); + + return -EROFS; +} + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0)) +static const struct file_operations rtw_drv_proc_fops = { + .owner = THIS_MODULE, + .open = rtw_drv_proc_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .write = rtw_drv_proc_write, +}; +#else +static const struct proc_ops rtw_drv_proc_fops = { + .proc_open = rtw_drv_proc_open, + .proc_read = seq_read, + .proc_lseek = seq_lseek, + .proc_release = seq_release, + .proc_write = rtw_drv_proc_write, +}; +#endif + +int rtw_drv_proc_init(void) +{ + int ret = _FAIL; + ssize_t i; + struct proc_dir_entry *entry = NULL; + + if (rtw_proc != NULL) { + rtw_warn_on(1); + goto exit; + } + + rtw_proc = rtw_proc_create_dir(RTW_PROC_NAME, get_proc_net, NULL); + + if (rtw_proc == NULL) { + rtw_warn_on(1); + goto exit; + } + + for (i=0;iprivate; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + sd_f0_reg_dump(m, adapter); + + return 0; +} + +static int proc_get_sdio_local_reg_dump(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + sdio_local_reg_dump(m, adapter); + + return 0; +} +#endif /* CONFIG_SDIO_HCI */ + +static int proc_get_mac_reg_dump(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + mac_reg_dump(m, adapter); + + return 0; +} + +static int proc_get_bb_reg_dump(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + bb_reg_dump(m, adapter); + + return 0; +} + +static int proc_get_rf_reg_dump(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + rf_reg_dump(m, adapter); + + return 0; +} + +static int proc_get_dump_adapters_status(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + dump_adapters_status(m, adapter_to_dvobj(adapter)); + + return 0; +} + +#ifdef CONFIG_RTW_CUSTOMER_STR +static int proc_get_customer_str(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + u8 cstr[RTW_CUSTOMER_STR_LEN]; + + rtw_ps_deny(adapter, PS_DENY_IOCTL); + if (rtw_pwr_wakeup(adapter) == _FAIL) + goto exit; + + if (rtw_hal_customer_str_read(adapter, cstr) != _SUCCESS) + goto exit; + + RTW_PRINT_SEL(m, RTW_CUSTOMER_STR_FMT"\n", RTW_CUSTOMER_STR_ARG(cstr)); + +exit: + rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL); + return 0; +} +#endif /* CONFIG_RTW_CUSTOMER_STR */ + +//gpio setting +#ifdef CONFIG_GPIO_API +static ssize_t proc_set_config_gpio(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]={0}; + int num=0,gpio_pin=0,gpio_mode=0;//gpio_mode:0 input 1:output; + + if (count < 2) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + num =sscanf(tmp, "%d %d",&gpio_pin,&gpio_mode); + DBG_871X("num=%d gpio_pin=%d mode=%d\n",num,gpio_pin,gpio_mode); + padapter->pre_gpio_pin=gpio_pin; + + if(gpio_mode==0 || gpio_mode==1 ) + rtw_hal_config_gpio(padapter, gpio_pin,gpio_mode); + } + return count; + +} +static ssize_t proc_set_gpio_output_value(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]={0}; + int num=0,gpio_pin=0,pin_mode=0;//pin_mode: 1 high 0:low + + if (count < 2) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + num =sscanf(tmp, "%d %d",&gpio_pin,&pin_mode); + DBG_871X("num=%d gpio_pin=%d pin_high=%d\n",num,gpio_pin,pin_mode); + padapter->pre_gpio_pin=gpio_pin; + + if(pin_mode==0 || pin_mode==1 ) + rtw_hal_set_gpio_output_value(padapter, gpio_pin,pin_mode); + } + return count; +} +static int proc_get_gpio(struct seq_file *m, void *v) +{ + u8 gpioreturnvalue=0; + struct net_device *dev = m->private; + + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + if(!padapter) + return -EFAULT; + gpioreturnvalue = rtw_hal_get_gpio(padapter, padapter->pre_gpio_pin); + DBG_871X_SEL_NL(m, "get_gpio %d:%d \n",padapter->pre_gpio_pin ,gpioreturnvalue); + + return 0; + +} +static ssize_t proc_set_gpio(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]={0}; + int num=0,gpio_pin=0; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + num =sscanf(tmp, "%d",&gpio_pin); + DBG_871X("num=%d gpio_pin=%d\n",num,gpio_pin); + padapter->pre_gpio_pin=gpio_pin; + + } + return count; +} +#endif +static int proc_get_current_tx_rate(struct seq_file *m, void *v) +{ + + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + u8 i; + u8 null_addr[ETH_ALEN] = {0}; + u8 *macaddr; + u8 current_rate_id = 0; + + DBG_871X_SEL_NL(m, "%-5s %-4s %-17s %-7s\n" + , "macid", "if_g", "macaddr", "tx_rate"); + + for (i = 0; i < macid_ctl->num; i++) { + if (rtw_macid_is_used(macid_ctl, i) || macid_ctl->h2c_msr[i]) { + if (macid_ctl->sta[i]) + macaddr = macid_ctl->sta[i]->hwaddr; + else + macaddr = null_addr; + current_rate_id = rtw_get_current_tx_rate(adapter, i); + if (!rtw_macid_is_bmc(macid_ctl, i)) { + DBG_871X_SEL_NL(m, "%5u %4u "MAC_FMT" %s\n" + , i + , rtw_macid_get_if_g(macid_ctl, i) + , MAC_ARG(macaddr) + , HDATA_RATE(current_rate_id) + ); + } + + + } + } + + +return 0; + +} + + +static int proc_get_linked_info_dump(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + if(padapter) + DBG_871X_SEL_NL(m, "linked_info_dump :%s \n", (padapter->bLinkInfoDump)?"enable":"disable"); + + return 0; +} + + +static ssize_t proc_set_linked_info_dump(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + char tmp[32]={0}; + int mode=0,pre_mode=0; + int num=0; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + pre_mode=padapter->bLinkInfoDump; + DBG_871X("pre_mode=%d\n", pre_mode); + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + num =sscanf(tmp, "%d ", &mode); + DBG_871X("num=%d mode=%d\n",num,mode); + + if(num!=1) + { + DBG_871X("argument number is wrong\n"); + return -EFAULT; + } + + if(mode==1 || (mode==0 && pre_mode==1) ) //not consider pwr_saving 0: + { + padapter->bLinkInfoDump = mode; + + } + else if( (mode==2 ) || (mode==0 && pre_mode==2))//consider power_saving + { + //DBG_871X("linked_info_dump =%s \n", (padapter->bLinkInfoDump)?"enable":"disable") + linked_info_dump(padapter,mode); + } + } + return count; +} + +static int proc_get_mac_qinfo(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + rtw_hal_get_hwreg(adapter, HW_VAR_DUMP_MAC_QUEUE_INFO, (u8 *)m); + + return 0; +} + +int proc_get_wifi_spec(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct registry_priv *pregpriv = &padapter->registrypriv; + + DBG_871X_SEL_NL(m,"wifi_spec=%d\n",pregpriv->wifi_spec); + return 0; +} + +static int proc_get_chan_plan(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + dump_cur_chset(m, adapter); + + return 0; +} + +static ssize_t proc_set_chan_plan(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u8 chan_plan = RTW_CHPLAN_MAX; + + if (!padapter) + return -EFAULT; + + if (count < 1) + { + DBG_871X("argument size is less than 1\n"); + return -EFAULT; + } + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + int num = sscanf(tmp, "%hhx", &chan_plan); + if (num != 1) + return count; + } + + rtw_set_channel_plan(padapter, chan_plan); + + return count; +} + +static int proc_get_country_code(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + if (adapter->mlmepriv.country_ent) + dump_country_chplan(m, adapter->mlmepriv.country_ent); + else + DBG_871X_SEL_NL(m, "unspecified\n"); + + return 0; +} + +static ssize_t proc_set_country_code(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + char alpha2[2]; + int num; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (!buffer || copy_from_user(tmp, buffer, count)) + goto exit; + + num = sscanf(tmp, "%c%c", &alpha2[0], &alpha2[1]); + if (num != 2) + return count; + + rtw_set_country(padapter, alpha2); + +exit: + return count; +} + +#ifdef CONFIG_DFS_MASTER +ssize_t proc_set_update_non_ocp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *mlme = &adapter->mlmepriv; + struct mlme_ext_priv *mlmeext = &adapter->mlmeextpriv; + char tmp[32]; + u8 ch, bw = CHANNEL_WIDTH_20, offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + int ms = -1; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhu %hhu %hhu %d", &ch, &bw, &offset, &ms); + + if (num < 1 || (bw != CHANNEL_WIDTH_20 && num < 3)) + goto exit; + + if (bw == CHANNEL_WIDTH_20) + rtw_chset_update_non_ocp_ms(mlmeext->channel_set + , ch, bw, HAL_PRIME_CHNL_OFFSET_DONT_CARE, ms); + else + rtw_chset_update_non_ocp_ms(mlmeext->channel_set + , ch, bw, offset, ms); + } + +exit: + return count; +} + +ssize_t proc_set_radar_detect(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct rf_ctl_t *rfctl = adapter_to_rfctl(adapter); + char tmp[32]; + u8 fake_radar_detect_cnt = 0; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhu", &fake_radar_detect_cnt); + + if (num < 1) + goto exit; + + rfctl->dbg_dfs_master_fake_radar_detect_cnt = fake_radar_detect_cnt; + } + +exit: + return count; +} +#endif /* CONFIG_DFS_MASTER */ + +static int proc_get_udpport(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct recv_priv *precvpriv = &(padapter->recvpriv); + + DBG_871X_SEL_NL(m,"%d\n",precvpriv->sink_udpport); + return 0; +} +static ssize_t proc_set_udpport(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + struct recv_priv *precvpriv = &(padapter->recvpriv); + int sink_udpport = 0; + char tmp[32]; + + + if (!padapter) + return -EFAULT; + + if (count < 1) + { + DBG_871X("argument size is less than 1\n"); + return -EFAULT; + } + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%d", &sink_udpport); + + if (num != 1) { + DBG_871X("invalid input parameter number!\n"); + return count; + } + + } + precvpriv->sink_udpport = sink_udpport; + + return count; + +} + +static int proc_get_macid_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj); + u8 i; + u8 null_addr[ETH_ALEN] = {0}; + u8 *macaddr; + + DBG_871X_SEL_NL(m, "max_num:%u\n", macid_ctl->num); + DBG_871X_SEL_NL(m, "\n"); + + DBG_871X_SEL_NL(m, "used:\n"); + dump_macid_map(m, &macid_ctl->used, macid_ctl->num); + DBG_871X_SEL_NL(m, "\n"); + + DBG_871X_SEL_NL(m, "%-3s %-3s %-4s %-4s %-17s %s" + "\n" + , "id", "bmc", "if_g", "ch_g", "macaddr", "status" + ); + + for (i=0;inum;i++) { + if (rtw_macid_is_used(macid_ctl, i) + || macid_ctl->h2c_msr[i] + ) { + if (macid_ctl->sta[i]) + macaddr = macid_ctl->sta[i]->hwaddr; + else + macaddr = null_addr; + + DBG_871X_SEL_NL(m, "%3u %3u %4d %4d "MAC_FMT" "H2C_MSR_FMT" %s" + "\n" + , i + , rtw_macid_is_bmc(macid_ctl, i) + , rtw_macid_get_if_g(macid_ctl, i) + , rtw_macid_get_ch_g(macid_ctl, i) + , MAC_ARG(macaddr) + , H2C_MSR_ARG(&macid_ctl->h2c_msr[i]) + , rtw_macid_is_used(macid_ctl, i) ? "" : "[unused]" + ); + } + } + + return 0; +} + +static int proc_get_sec_cam(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + + DBG_871X_SEL_NL(m, "sec_cap:0x%02x\n", cam_ctl->sec_cap); + DBG_871X_SEL_NL(m, "flags:0x%08x\n", cam_ctl->flags); + DBG_871X_SEL_NL(m, "\n"); + + DBG_871X_SEL_NL(m, "max_num:%u\n", cam_ctl->num); + DBG_871X_SEL_NL(m, "used:\n"); + dump_sec_cam_map(m, &cam_ctl->used, cam_ctl->num); + DBG_871X_SEL_NL(m, "\n"); + + DBG_871X_SEL_NL(m, "reg_scr:0x%04x\n", rtw_read16(adapter, 0x680)); + DBG_871X_SEL_NL(m, "\n"); + + dump_sec_cam(m, adapter); + + return 0; +} + +static ssize_t proc_set_sec_cam(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + char tmp[32] = {0}; + char cmd[4]; + u8 id; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + /* c : clear specific cam entry */ + /* wfc : write specific cam entry from cam cache */ + + int num = sscanf(tmp, "%s %hhu", cmd, &id); + + if (num < 2) + return count; + + if (id >= cam_ctl->num) { + DBG_871X_LEVEL(_drv_err_, FUNC_ADPT_FMT" invalid id:%u\n", FUNC_ADPT_ARG(adapter), id); + return count; + } + + if (strcmp("c", cmd) == 0) { + _clear_cam_entry(adapter, id); + adapter->securitypriv.hw_decrypted = _FALSE; /* temporarily set this for TX path to use SW enc */ + } else if (strcmp("wfc", cmd) == 0) { + write_cam_from_cache(adapter, id); + } + } + + return count; +} + +static int proc_get_sec_cam_cache(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct dvobj_priv *dvobj = adapter_to_dvobj(adapter); + struct cam_ctl_t *cam_ctl = &dvobj->cam_ctl; + u8 i; + + DBG_871X_SEL_NL(m, "SW sec cam cache:\n"); + dump_sec_cam_ent_title(m, 1); + for (i = 0; i < cam_ctl->num; i++) { + if (dvobj->cam_cache[i].ctrl != 0) + dump_sec_cam_ent(m, &dvobj->cam_cache[i], i); + } + + return 0; +} + +static ssize_t proc_set_change_bss_chbw(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct mlme_priv *mlme = &(adapter->mlmepriv); + struct mlme_ext_priv *mlmeext = &(adapter->mlmeextpriv); + char tmp[32]; + u8 ch, bw = CHANNEL_WIDTH_20, offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhu %hhu %hhu", &ch, &bw, &offset); + + if (num < 1 || (bw != CHANNEL_WIDTH_20 && num < 3)) + goto exit; + + if (check_fwstate(mlme, WIFI_AP_STATE) && check_fwstate(mlme, WIFI_ASOC_STATE)) + rtw_change_bss_chbw_cmd(adapter, RTW_CMDF_WAIT_ACK, ch, bw, offset); + } + +exit: + return count; +} + +static int proc_get_target_tx_power(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + dump_target_tx_power(m, adapter); + + return 0; +} + +static int proc_get_tx_power_by_rate(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + dump_tx_power_by_rate(m, adapter); + + return 0; +} + +static int proc_get_tx_power_limit(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + dump_tx_power_limit(m, adapter); + + return 0; +} + +static int proc_get_tx_power_ext_info(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + dump_tx_power_ext_info(m, adapter); + + return 0; +} + +static ssize_t proc_set_tx_power_ext_info(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + char tmp[32] = {0}; + char cmd[16] = {0}; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%s", cmd); + + if (num < 1) + return count; + + #ifdef CONFIG_LOAD_PHY_PARA_FROM_FILE + phy_free_filebuf_mask(adapter, LOAD_BB_PG_PARA_FILE | LOAD_RF_TXPWR_LMT_PARA_FILE); + #endif + + rtw_ps_deny(adapter, PS_DENY_IOCTL); + LeaveAllPowerSaveModeDirect(adapter); + + if (strcmp("default", cmd) == 0) + rtw_run_in_thread_cmd(adapter, ((void *)(phy_reload_default_tx_power_ext_info)), adapter); + else + rtw_run_in_thread_cmd(adapter, ((void *)(phy_reload_tx_power_ext_info)), adapter); + + rtw_ps_deny_cancel(adapter, PS_DENY_IOCTL); + } + + return count; +} + +#ifdef CONFIG_RF_POWER_TRIM +static int proc_get_kfree_flag(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter); + + DBG_871X_SEL_NL(m, "0x%02x\n", kfree_data->flag); + + return 0; +} + +static ssize_t proc_set_kfree_flag(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter); + char tmp[32] = {0}; + u8 flag; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhx", &flag); + + if (num < 1) + return count; + + kfree_data->flag = flag; + } + + return count; +} + +static int proc_get_kfree_bb_gain(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter); + u8 i, j; + + for (i = 0; i < BB_GAIN_NUM; i++) { + if (i == 0) + DBG_871X_SEL(m, "2G: "); + else if (i == 1) + DBG_871X_SEL(m, "5GLB1: "); + else if (i == 2) + DBG_871X_SEL(m, "5GLB2: "); + else if (i == 3) + DBG_871X_SEL(m, "5GMB1: "); + else if (i == 4) + DBG_871X_SEL(m, "5GMB2: "); + else if (i == 5) + DBG_871X_SEL(m, "5GHB: "); + + for (j = 0; j < hal_data->NumTotalRFPath; j++) + DBG_871X_SEL(m, "%d ", kfree_data->bb_gain[i][j]); + DBG_871X_SEL(m, "\n"); + } + + return 0; +} + +static ssize_t proc_set_kfree_bb_gain(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter); + struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter); + char tmp[BB_GAIN_NUM * RF_PATH_MAX] = {0}; + u8 path, chidx; + s8 bb_gain[BB_GAIN_NUM]; + char ch_band_Group[6]; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + char *c, *next; + int i = 0; + + next = tmp; + c = strsep(&next, " \t"); + + if (sscanf(c, "%s", ch_band_Group) != 1) { + DBG_871X("Error Head Format, channel Group select\n,Please input:\t 2G , 5GLB1 , 5GLB2 , 5GMB1 , 5GMB2 , 5GHB\n"); + return count; + } + if (strcmp("2G", ch_band_Group) == 0) + chidx = BB_GAIN_2G; +#ifdef CONFIG_IEEE80211_BAND_5GHZ + else if (strcmp("5GLB1", ch_band_Group) == 0) + chidx = BB_GAIN_5GLB1; + else if (strcmp("5GLB2", ch_band_Group) == 0) + chidx = BB_GAIN_5GLB2; + else if (strcmp("5GMB1", ch_band_Group) == 0) + chidx = BB_GAIN_5GMB1; + else if (strcmp("5GMB2", ch_band_Group) == 0) + chidx = BB_GAIN_5GMB2; + else if (strcmp("5GHB", ch_band_Group) == 0) + chidx = BB_GAIN_5GHB; +#endif /*CONFIG_IEEE80211_BAND_5GHZ*/ + else { + DBG_871X("Error Head Format, channel Group select\n,Please input:\t 2G , 5GLB1 , 5GLB2 , 5GMB1 , 5GMB2 , 5GHB\n"); + return count; + } + c = strsep(&next, " \t"); + + while (c != NULL) { + if (sscanf(c, "%hhx", &bb_gain[i]) != 1) + break; + + kfree_data->bb_gain[chidx][i] = bb_gain[i]; + DBG_871X("%s,kfree_data->bb_gain[%d][%d]=%x\n", __func__, chidx, i, kfree_data->bb_gain[chidx][i]); + + c = strsep(&next, " \t"); + i++; + } + + } + + return count; + +} + +static int proc_get_kfree_thermal(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter); + + DBG_871X_SEL(m, "%d\n", kfree_data->thermal); + + return 0; +} + +static ssize_t proc_set_kfree_thermal(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + struct kfree_data_t *kfree_data = GET_KFREE_DATA(adapter); + char tmp[32] = {0}; + s8 thermal; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhd", &thermal); + + if (num < 1) + return count; + + kfree_data->thermal = thermal; + } + + return count; +} + +static ssize_t proc_set_tx_gain_offset(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter; + char tmp[32] = {0}; + u8 rf_path; + s8 offset; + + adapter = (_adapter *)rtw_netdev_priv(dev); + if (!adapter) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + u8 write_value; + int num = sscanf(tmp, "%hhu %hhd", &rf_path, &offset); + + if (num < 2) + return count; + + DBG_871X("write rf_path:%u tx gain offset:%d\n", rf_path, offset); + rtw_rf_set_tx_gain_offset(adapter, rf_path, offset); + } + + return count; +} +#endif /* CONFIG_RF_POWER_TRIM */ + +#ifdef CONFIG_BT_COEXIST +ssize_t proc_set_btinfo_evt(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u8 btinfo[8]; + + if (count < 6) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + int num = 0; + + _rtw_memset(btinfo, 0, 8); + + num = sscanf(tmp, "%hhx %hhx %hhx %hhx %hhx %hhx %hhx %hhx" + , &btinfo[0], &btinfo[1], &btinfo[2], &btinfo[3] + , &btinfo[4], &btinfo[5], &btinfo[6], &btinfo[7]); + + if (num < 6) + return -EINVAL; + + btinfo[1] = num-2; + + rtw_btinfo_cmd(padapter, btinfo, btinfo[1]+2); + } + + return count; +} + +static u8 btreg_read_type = 0; +static u16 btreg_read_addr = 0; +static int btreg_read_error = 0; +static u8 btreg_write_type = 0; +static u16 btreg_write_addr = 0; +static int btreg_write_error = 0; + +static u8 *btreg_type[] = { + "rf", + "modem", + "bluewize", + "vendor", + "le" +}; + +static int btreg_parse_str(char const *input, u8 *type, u16 *addr, u16 *val) +{ + u32 num; + u8 str[80] = {0}; + u8 t = 0; + u32 a, v; + u8 i, n; + u8 *p; + + + num = sscanf(input, "%s %x %x", str, &a, &v); + if (num < 2) { + DBG_871X("%s: INVALID input!(%s)\n", __FUNCTION__, input); + return -EINVAL; + } + if ((num < 3) && val) { + DBG_871X("%s: INVALID input!(%s)\n", __FUNCTION__, input); + return -EINVAL; + } + + /* convert to lower case for following type compare */ + p = str; + for ( ; *p; ++p) + *p = tolower(*p); + n = sizeof(btreg_type)/sizeof(btreg_type[0]); + for (i = 0; i < n; i++) { + if (!strcmp(str, btreg_type[i])) { + t = i; + break; + } + } + if (i == n) { + DBG_871X("%s: unknown type(%s)!\n", __FUNCTION__, str); + return -EINVAL; + } + + switch (t) { + case 0: + /* RF */ + if (a & 0xFFFFFF80) { + DBG_871X("%s: INVALID address(0x%X) for type %s(%d)!\n", + __FUNCTION__, a, btreg_type[t], t); + return -EINVAL; + } + break; + case 1: + /* Modem */ + if (a & 0xFFFFFE00) { + DBG_871X("%s: INVALID address(0x%X) for type %s(%d)!\n", + __FUNCTION__, a, btreg_type[t], t); + return -EINVAL; + } + break; + default: + /* Others(Bluewize, Vendor, LE) */ + if (a & 0xFFFFF000) { + DBG_871X("%s: INVALID address(0x%X) for type %s(%d)!\n", + __FUNCTION__, a, btreg_type[t], t); + return -EINVAL; + } + break; + } + + if (val) { + if (v & 0xFFFF0000) { + DBG_871X("%s: INVALID value(0x%x)!\n", __FUNCTION__, v); + return -EINVAL; + } + *val = (u16)v; + } + + *type = (u8)t; + *addr = (u16)a; + + return 0; +} + +int proc_get_btreg_read(struct seq_file *m, void *v) +{ + struct net_device *dev; + PADAPTER padapter; + u16 ret; + u32 data; + + + if (btreg_read_error) + return btreg_read_error; + + dev = m->private; + padapter = (PADAPTER)rtw_netdev_priv(dev); + + ret = rtw_btcoex_btreg_read(padapter, btreg_read_type, btreg_read_addr, &data); + if (CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(ret, BT_STATUS_BT_OP_SUCCESS)) + DBG_871X_SEL_NL(m, "BTREG read: (%s)0x%04X = 0x%08x\n", btreg_type[btreg_read_type], btreg_read_addr, data); + else + DBG_871X_SEL_NL(m, "BTREG read: (%s)0x%04X read fail. error code = 0x%04x.\n", btreg_type[btreg_read_type], btreg_read_addr, ret); + + return 0; +} + +ssize_t proc_set_btreg_read(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + PADAPTER padapter; + u8 tmp[80] = {0}; + u32 num; + int err; + + + padapter = (PADAPTER)rtw_netdev_priv(dev); + + if (NULL == buffer) { + DBG_871X(FUNC_ADPT_FMT ": input buffer is NULL!\n", + FUNC_ADPT_ARG(padapter)); + err = -EFAULT; + goto exit; + } + + if (count < 1) { + DBG_871X(FUNC_ADPT_FMT ": input length is 0!\n", + FUNC_ADPT_ARG(padapter)); + err = -EFAULT; + goto exit; + } + + num = count; + if (num > (sizeof(tmp) - 1)) + num = (sizeof(tmp) - 1); + + if (copy_from_user(tmp, buffer, num)) { + DBG_871X(FUNC_ADPT_FMT ": copy buffer from user space FAIL!\n", + FUNC_ADPT_ARG(padapter)); + err = -EFAULT; + goto exit; + } + /* [Coverity] sure tmp end with '\0'(string terminal) */ + tmp[sizeof(tmp) - 1] = 0; + + err = btreg_parse_str(tmp, &btreg_read_type, &btreg_read_addr, NULL); + if (err) + goto exit; + + DBG_871X(FUNC_ADPT_FMT ": addr=(%s)0x%X\n", + FUNC_ADPT_ARG(padapter), btreg_type[btreg_read_type], btreg_read_addr); + +exit: + btreg_read_error = err; + + return count; +} + +int proc_get_btreg_write(struct seq_file *m, void *v) +{ + struct net_device *dev; + PADAPTER padapter; + u16 ret; + u32 data; + + + if (btreg_write_error < 0) + return btreg_write_error; + else if (btreg_write_error > 0) { + DBG_871X_SEL_NL(m, "BTREG write: (%s)0x%04X write fail. error code = 0x%04x.\n", btreg_type[btreg_write_type], btreg_write_addr, btreg_write_error); + return 0; + } + + dev = m->private; + padapter = (PADAPTER)rtw_netdev_priv(dev); + + ret = rtw_btcoex_btreg_read(padapter, btreg_write_type, btreg_write_addr, &data); + if (CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(ret, BT_STATUS_BT_OP_SUCCESS)) + DBG_871X_SEL_NL(m, "BTREG read: (%s)0x%04X = 0x%08x\n", btreg_type[btreg_write_type], btreg_write_addr, data); + else + DBG_871X_SEL_NL(m, "BTREG read: (%s)0x%04X read fail. error code = 0x%04x.\n", btreg_type[btreg_write_type], btreg_write_addr, ret); + + return 0; +} + +ssize_t proc_set_btreg_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + PADAPTER padapter; + u8 tmp[80] = {0}; + u32 num; + u16 val; + u16 ret; + int err; + + + padapter = (PADAPTER)rtw_netdev_priv(dev); + + if (NULL == buffer) { + DBG_871X(FUNC_ADPT_FMT ": input buffer is NULL!\n", + FUNC_ADPT_ARG(padapter)); + err = -EFAULT; + goto exit; + } + + if (count < 1) { + DBG_871X(FUNC_ADPT_FMT ": input length is 0!\n", + FUNC_ADPT_ARG(padapter)); + err = -EFAULT; + goto exit; + } + + num = count; + if (num > (sizeof(tmp) - 1)) + num = (sizeof(tmp) - 1); + + if (copy_from_user(tmp, buffer, num)) { + DBG_871X(FUNC_ADPT_FMT ": copy buffer from user space FAIL!\n", + FUNC_ADPT_ARG(padapter)); + err = -EFAULT; + goto exit; + } + + err = btreg_parse_str(tmp, &btreg_write_type, &btreg_write_addr, &val); + if (err) + goto exit; + + DBG_871X(FUNC_ADPT_FMT ": Set (%s)0x%X = 0x%x\n", + FUNC_ADPT_ARG(padapter), btreg_type[btreg_write_type], btreg_write_addr, val); + + ret = rtw_btcoex_btreg_write(padapter, btreg_write_type, btreg_write_addr, val); + if (!CHECK_STATUS_CODE_FROM_BT_MP_OPER_RET(ret, BT_STATUS_BT_OP_SUCCESS)) + err = ret; + +exit: + btreg_write_error = err; + + return count; +} +#endif /* CONFIG_BT_COEXIST */ + +#ifdef CONFIG_AUTO_CHNL_SEL_NHM +static int proc_get_best_chan(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + u8 best_24g_ch = 0, best_5g_ch = 0; + + rtw_hal_get_odm_var(adapter, HAL_ODM_AUTO_CHNL_SEL, &(best_24g_ch), &(best_5g_ch)); + + DBG_871X_SEL_NL(m, "Best 2.4G CH:%u\n", best_24g_ch); + DBG_871X_SEL_NL(m, "Best 5G CH:%u\n", best_5g_ch); + return 0; +} + +static ssize_t proc_set_acs(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u8 acs_satae = 0; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%hhu", &acs_satae); + + if (num < 1) + return -EINVAL; + + if (1 == acs_satae) + rtw_acs_start(padapter, _TRUE); + else + rtw_acs_start(padapter, _FALSE); + + } + return count; +} +#endif + +static int proc_get_hal_spec(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + dump_hal_spec(m, adapter); + return 0; +} + +/* +* rtw_adapter_proc: +* init/deinit when register/unregister net_device +*/ +const struct rtw_proc_hdl adapter_proc_hdls [] = { + {"write_reg", proc_get_dummy, proc_set_write_reg}, + {"read_reg", proc_get_read_reg, proc_set_read_reg}, + {"adapters_status", proc_get_dump_adapters_status, NULL}, +#ifdef CONFIG_RTW_CUSTOMER_STR + {"customer_str", proc_get_customer_str, NULL}, +#endif + {"fwstate", proc_get_fwstate, NULL}, + {"sec_info", proc_get_sec_info, NULL}, + {"mlmext_state", proc_get_mlmext_state, NULL}, + {"qos_option", proc_get_qos_option, NULL}, + {"ht_option", proc_get_ht_option, NULL}, + {"rf_info", proc_get_rf_info, NULL}, + {"scan_param", proc_get_scan_param, proc_set_scan_param}, + {"scan_abort", proc_get_scan_abort, NULL}, +#ifdef CONFIG_SCAN_BACKOP + {"backop_flags_sta", proc_get_backop_flags_sta, proc_set_backop_flags_sta}, + {"backop_flags_ap", proc_get_backop_flags_ap, proc_set_backop_flags_ap}, +#endif + {"survey_info", proc_get_survey_info, proc_set_survey_info}, + {"ap_info", proc_get_ap_info, NULL}, + {"trx_info", proc_get_trx_info, proc_reset_trx_info}, + {"rate_ctl", proc_get_rate_ctl, proc_set_rate_ctl}, + {"dis_pwt_ctl", proc_get_dis_pwt, proc_set_dis_pwt}, + {"mac_qinfo", proc_get_mac_qinfo, NULL}, + {"macid_info", proc_get_macid_info, NULL}, + {"sec_cam", proc_get_sec_cam, proc_set_sec_cam}, + {"sec_cam_cache", proc_get_sec_cam_cache, NULL}, + {"suspend_info", proc_get_suspend_resume_info, NULL}, + {"wifi_spec",proc_get_wifi_spec,NULL}, +#ifdef CONFIG_LAYER2_ROAMING + {"roam_flags", proc_get_roam_flags, proc_set_roam_flags}, + {"roam_param", proc_get_roam_param, proc_set_roam_param}, + {"roam_tgt_addr", proc_get_dummy, proc_set_roam_tgt_addr}, +#endif /* CONFIG_LAYER2_ROAMING */ + +#ifdef CONFIG_SDIO_HCI + {"sd_f0_reg_dump", proc_get_sd_f0_reg_dump, NULL}, + {"sdio_local_reg_dump", proc_get_sdio_local_reg_dump, NULL}, +#endif /* CONFIG_SDIO_HCI */ + + {"fwdl_test_case", proc_get_dummy, proc_set_fwdl_test_case}, + {"del_rx_ampdu_test_case", proc_get_dummy, proc_set_del_rx_ampdu_test_case}, + {"wait_hiq_empty", proc_get_dummy, proc_set_wait_hiq_empty}, + + {"mac_reg_dump", proc_get_mac_reg_dump, NULL}, + {"bb_reg_dump", proc_get_bb_reg_dump, NULL}, + {"rf_reg_dump", proc_get_rf_reg_dump, NULL}, + +#ifdef CONFIG_AP_MODE + {"all_sta_info", proc_get_all_sta_info, NULL}, +#endif /* CONFIG_AP_MODE */ + +#ifdef DBG_MEMORY_LEAK + {"_malloc_cnt", proc_get_malloc_cnt, NULL}, +#endif /* DBG_MEMORY_LEAK */ + +#ifdef CONFIG_FIND_BEST_CHANNEL + {"best_channel", proc_get_best_channel, proc_set_best_channel}, +#endif + + {"rx_signal", proc_get_rx_signal, proc_set_rx_signal}, + {"hw_info", proc_get_hw_status, NULL}, + +#ifdef CONFIG_80211N_HT + {"ht_enable", proc_get_ht_enable, proc_set_ht_enable}, + {"bw_mode", proc_get_bw_mode, proc_set_bw_mode}, + {"ampdu_enable", proc_get_ampdu_enable, proc_set_ampdu_enable}, + {"rx_stbc", proc_get_rx_stbc, proc_set_rx_stbc}, + {"rx_ampdu", proc_get_rx_ampdu, proc_set_rx_ampdu}, + {"rx_ampdu_factor",proc_get_rx_ampdu_factor,proc_set_rx_ampdu_factor}, + {"rx_ampdu_density",proc_get_rx_ampdu_density,proc_set_rx_ampdu_density}, + {"tx_ampdu_density",proc_get_tx_ampdu_density,proc_set_tx_ampdu_density}, +#endif /* CONFIG_80211N_HT */ + + {"en_fwps", proc_get_en_fwps, proc_set_en_fwps}, + {"mac_rptbuf", proc_get_mac_rptbuf, NULL}, + + //{"path_rssi", proc_get_two_path_rssi, NULL}, +// {"rssi_disp",proc_get_rssi_disp, proc_set_rssi_disp}, + +#ifdef CONFIG_BT_COEXIST + {"btcoex_dbg", proc_get_btcoex_dbg, proc_set_btcoex_dbg}, + {"btcoex", proc_get_btcoex_info, NULL}, + {"btinfo_evt", proc_get_dummy, proc_set_btinfo_evt}, + {"btreg_read", proc_get_btreg_read, proc_set_btreg_read}, + {"btreg_write", proc_get_btreg_write, proc_set_btreg_write}, +#endif /* CONFIG_BT_COEXIST */ + +#if defined(DBG_CONFIG_ERROR_DETECT) + {"sreset", proc_get_sreset, proc_set_sreset}, +#endif /* DBG_CONFIG_ERROR_DETECT */ + {"trx_info_debug", proc_get_trx_info_debug, NULL}, + {"linked_info_dump",proc_get_linked_info_dump,proc_set_linked_info_dump}, + {"current_tx_rate", proc_get_current_tx_rate, NULL}, +#ifdef CONFIG_GPIO_API + {"gpio_info",proc_get_gpio,proc_set_gpio}, + {"gpio_set_output_value",proc_get_dummy,proc_set_gpio_output_value}, + {"gpio_set_direction",proc_get_dummy,proc_set_config_gpio}, +#endif + +#ifdef CONFIG_DBG_COUNTER + {"rx_logs", proc_get_rx_logs, NULL}, + {"tx_logs", proc_get_tx_logs, NULL}, + {"int_logs", proc_get_int_logs, NULL}, +#endif + +#ifdef CONFIG_PCI_HCI + {"rx_ring", proc_get_rx_ring, NULL}, + {"tx_ring", proc_get_tx_ring, NULL}, +#endif +#ifdef CONFIG_GPIO_WAKEUP + {"wowlan_gpio_info", proc_get_wowlan_gpio_info, + proc_set_wowlan_gpio_info}, +#endif +#ifdef CONFIG_P2P_WOWLAN + {"p2p_wowlan_info", proc_get_p2p_wowlan_info, NULL}, +#endif + {"country_code", proc_get_country_code, proc_set_country_code}, + {"chan_plan", proc_get_chan_plan, proc_set_chan_plan}, +#ifdef CONFIG_DFS_MASTER + {"dfs_master_test_case", proc_get_dfs_master_test_case, proc_set_dfs_master_test_case}, + {"update_non_ocp", proc_get_dummy, proc_set_update_non_ocp}, + {"radar_detect", proc_get_dummy, proc_set_radar_detect}, +#endif + {"new_bcn_max", proc_get_new_bcn_max, proc_set_new_bcn_max}, + {"sink_udpport",proc_get_udpport,proc_set_udpport}, +#ifdef DBG_RX_COUNTER_DUMP + {"dump_rx_cnt_mode",proc_get_rx_cnt_dump,proc_set_rx_cnt_dump}, +#endif + {"change_bss_chbw", NULL, proc_set_change_bss_chbw}, + {"target_tx_power", proc_get_target_tx_power, NULL}, + {"tx_power_by_rate", proc_get_tx_power_by_rate, NULL}, + {"tx_power_limit", proc_get_tx_power_limit, NULL}, + {"tx_power_ext_info", proc_get_tx_power_ext_info, proc_set_tx_power_ext_info}, +#ifdef CONFIG_RF_POWER_TRIM + {"tx_gain_offset", proc_get_dummy, proc_set_tx_gain_offset}, + {"kfree_flag", proc_get_kfree_flag, proc_set_kfree_flag}, + {"kfree_bb_gain", proc_get_kfree_bb_gain, proc_set_kfree_bb_gain}, + {"kfree_thermal", proc_get_kfree_thermal, proc_set_kfree_thermal}, +#endif +#ifdef CONFIG_POWER_SAVING + {"ps_info",proc_get_ps_info, NULL}, +#endif +#ifdef CONFIG_TDLS + {"tdls_info", proc_get_tdls_info, NULL}, +#endif + {"monitor", proc_get_monitor, proc_set_monitor}, + +#ifdef CONFIG_AUTO_CHNL_SEL_NHM + {"acs", proc_get_best_chan, proc_set_acs}, +#endif +#ifdef CONFIG_PREALLOC_RX_SKB_BUFFER + {"rtkm_info", proc_get_rtkm_info, NULL}, +#endif + {"efuse_map", proc_get_efuse_map, NULL}, +#ifdef CONFIG_IEEE80211W + {"11w_tx_sa_query", proc_get_tx_sa_query, proc_set_tx_sa_query}, + {"11w_tx_deauth", proc_get_tx_deauth, proc_set_tx_deauth}, + {"11w_tx_auth", proc_get_tx_auth, proc_set_tx_auth}, +#endif /* CONFIG_IEEE80211W */ + {"hal_spec", proc_get_hal_spec, NULL}, +}; + +const int adapter_proc_hdls_num = sizeof(adapter_proc_hdls) / sizeof(struct rtw_proc_hdl); + +static int rtw_adapter_proc_open(struct inode *inode, struct file *file) +{ + ssize_t index = (ssize_t)PDE_DATA(inode); + const struct rtw_proc_hdl *hdl = adapter_proc_hdls+index; + + return single_open(file, hdl->show, proc_get_parent_data(inode)); +} + +static ssize_t rtw_adapter_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos) +{ + ssize_t index = (ssize_t)PDE_DATA(file_inode(file)); + const struct rtw_proc_hdl *hdl = adapter_proc_hdls+index; + ssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write; + + if (write) + return write(file, buffer, count, pos, ((struct seq_file *)file->private_data)->private); + + return -EROFS; +} + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0)) +static const struct file_operations rtw_adapter_proc_fops = { + .owner = THIS_MODULE, + .open = rtw_adapter_proc_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .write = rtw_adapter_proc_write, +}; +#else +static const struct proc_ops rtw_adapter_proc_fops = { + .proc_open = rtw_adapter_proc_open, + .proc_read = seq_read, + .proc_lseek = seq_lseek, + .proc_release = seq_release, + .proc_write = rtw_adapter_proc_write, +}; +#endif + +int proc_get_odm_dbg_comp(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + rtw_odm_dbg_comp_msg(m, adapter); + + return 0; +} + +ssize_t proc_set_odm_dbg_comp(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + + u64 dbg_comp; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%llx", &dbg_comp); + + if (num != 1) + return count; + + rtw_odm_dbg_comp_set(adapter, dbg_comp); + } + + return count; +} + +int proc_get_odm_dbg_level(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + rtw_odm_dbg_level_msg(m, adapter); + + return 0; +} + +ssize_t proc_set_odm_dbg_level(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + + u32 dbg_level; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%u", &dbg_level); + + if (num != 1) + return count; + + rtw_odm_dbg_level_set(adapter, dbg_level); + } + + return count; +} + +int proc_get_odm_ability(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + + rtw_odm_ability_msg(m, adapter); + + return 0; +} + +ssize_t proc_set_odm_ability(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *adapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + + u32 ability; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%x", &ability); + + if (num != 1) + return count; + + rtw_odm_ability_set(adapter, ability); + } + + return count; +} + +int proc_get_odm_adaptivity(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + + rtw_odm_adaptivity_parm_msg(m, padapter); + + return 0; +} + +ssize_t proc_set_odm_adaptivity(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *dev = data; + _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); + char tmp[32]; + u32 TH_L2H_ini; + u32 TH_L2H_ini_mode2; + s8 TH_EDCCA_HL_diff; + s8 TH_EDCCA_HL_diff_mode2; + u8 EDCCA_enable; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) { + rtw_warn_on(1); + return -EFAULT; + } + + if (buffer && !copy_from_user(tmp, buffer, count)) { + + int num = sscanf(tmp, "%x %hhd %x %hhd %hhu", &TH_L2H_ini, &TH_EDCCA_HL_diff, &TH_L2H_ini_mode2, &TH_EDCCA_HL_diff_mode2, &EDCCA_enable); + + if (num != 5) + return count; + + rtw_odm_adaptivity_parm_set(padapter, (s8)TH_L2H_ini, TH_EDCCA_HL_diff, (s8)TH_L2H_ini_mode2, TH_EDCCA_HL_diff_mode2, EDCCA_enable); + } + + return count; +} + +static char *phydm_msg = NULL; +#define PHYDM_MSG_LEN 80*24 + +int proc_get_phydm_cmd(struct seq_file *m, void *v) +{ + struct net_device *netdev; + PADAPTER padapter; + PHAL_DATA_TYPE pHalData; + PDM_ODM_T phydm; + + + netdev = m->private; + padapter = (PADAPTER)rtw_netdev_priv(netdev); + pHalData = GET_HAL_DATA(padapter); + phydm = &pHalData->odmpriv; + + if (NULL == phydm_msg) { + phydm_msg = rtw_zmalloc(PHYDM_MSG_LEN); + if (NULL == phydm_msg) + return -ENOMEM; + + phydm_cmd(phydm, NULL, 0, 0, phydm_msg, PHYDM_MSG_LEN); + } + + DBG_871X_SEL(m, "%s\n", phydm_msg); + + rtw_mfree(phydm_msg, PHYDM_MSG_LEN); + phydm_msg = NULL; + + return 0; +} + +ssize_t proc_set_phydm_cmd(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data) +{ + struct net_device *netdev; + PADAPTER padapter; + PHAL_DATA_TYPE pHalData; + PDM_ODM_T phydm; + char tmp[64] = {0}; + + + netdev = (struct net_device*)data; + padapter = (PADAPTER)rtw_netdev_priv(netdev); + pHalData = GET_HAL_DATA(padapter); + phydm = &pHalData->odmpriv; + + if (count < 1) + return -EFAULT; + + if (count > sizeof(tmp)) + return -EFAULT; + + if (buffer && !copy_from_user(tmp, buffer, count)) { + if (NULL == phydm_msg) { + phydm_msg = rtw_zmalloc(PHYDM_MSG_LEN); + if (NULL == phydm_msg) + return -ENOMEM; + } else { + _rtw_memset(phydm_msg, 0, PHYDM_MSG_LEN); + } + + phydm_cmd(phydm, tmp, count, 1, phydm_msg, PHYDM_MSG_LEN); + + if (strlen(phydm_msg) == 0) { + rtw_mfree(phydm_msg, PHYDM_MSG_LEN); + phydm_msg = NULL; + } + } + + return count; +} + +/* +* rtw_odm_proc: +* init/deinit when register/unregister net_device, along with rtw_adapter_proc +*/ +const struct rtw_proc_hdl odm_proc_hdls [] = { + {"dbg_comp", proc_get_odm_dbg_comp, proc_set_odm_dbg_comp}, + {"dbg_level", proc_get_odm_dbg_level, proc_set_odm_dbg_level}, + {"ability", proc_get_odm_ability, proc_set_odm_ability}, + {"adaptivity", proc_get_odm_adaptivity, proc_set_odm_adaptivity}, + {"cmd", proc_get_phydm_cmd, proc_set_phydm_cmd}, +}; + +const int odm_proc_hdls_num = sizeof(odm_proc_hdls) / sizeof(struct rtw_proc_hdl); + +static int rtw_odm_proc_open(struct inode *inode, struct file *file) +{ + ssize_t index = (ssize_t)PDE_DATA(inode); + const struct rtw_proc_hdl *hdl = odm_proc_hdls+index; + + return single_open(file, hdl->show, proc_get_parent_data(inode)); +} + +static ssize_t rtw_odm_proc_write(struct file *file, const char __user *buffer, size_t count, loff_t *pos) +{ + ssize_t index = (ssize_t)PDE_DATA(file_inode(file)); + const struct rtw_proc_hdl *hdl = odm_proc_hdls+index; + ssize_t (*write)(struct file *, const char __user *, size_t, loff_t *, void *) = hdl->write; + + if (write) + return write(file, buffer, count, pos, ((struct seq_file *)file->private_data)->private); + + return -EROFS; +} + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 6, 0)) +static const struct file_operations rtw_odm_proc_fops = { + .owner = THIS_MODULE, + .open = rtw_odm_proc_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, + .write = rtw_odm_proc_write, +}; +#else +static const struct proc_ops rtw_odm_proc_fops = { + .proc_open = rtw_odm_proc_open, + .proc_read = seq_read, + .proc_lseek = seq_lseek, + .proc_release = seq_release, + .proc_write = rtw_odm_proc_write, +}; +#endif +struct proc_dir_entry *rtw_odm_proc_init(struct net_device *dev) +{ + struct proc_dir_entry *dir_odm = NULL; + struct proc_dir_entry *entry = NULL; + _adapter *adapter = rtw_netdev_priv(dev); + ssize_t i; + + if (adapter->dir_dev == NULL) { + rtw_warn_on(1); + goto exit; + } + + if (adapter->dir_odm != NULL) { + rtw_warn_on(1); + goto exit; + } + + dir_odm = rtw_proc_create_dir("odm", adapter->dir_dev, dev); + if (dir_odm == NULL) { + rtw_warn_on(1); + goto exit; + } + + adapter->dir_odm = dir_odm; + + for (i=0;idir_odm; + + if (dir_odm == NULL) { + rtw_warn_on(1); + return; + } + + for (i=0;idir_dev); + + adapter->dir_odm = NULL; + + if (phydm_msg) { + rtw_mfree(phydm_msg, PHYDM_MSG_LEN); + phydm_msg = NULL; + } +} + +struct proc_dir_entry *rtw_adapter_proc_init(struct net_device *dev) +{ + struct proc_dir_entry *drv_proc = get_rtw_drv_proc(); + struct proc_dir_entry *dir_dev = NULL; + struct proc_dir_entry *entry = NULL; + _adapter *adapter = rtw_netdev_priv(dev); + u8 rf_type; + ssize_t i; + + if (drv_proc == NULL) { + rtw_warn_on(1); + goto exit; + } + + if (adapter->dir_dev != NULL) { + rtw_warn_on(1); + goto exit; + } + + dir_dev = rtw_proc_create_dir(dev->name, drv_proc, dev); + if (dir_dev == NULL) { + rtw_warn_on(1); + goto exit; + } + + adapter->dir_dev = dir_dev; + + for (i=0;idir_dev; + + if (dir_dev == NULL) { + rtw_warn_on(1); + return; + } + + for (i=0;iname, drv_proc); + + adapter->dir_dev = NULL; +} + +void rtw_adapter_proc_replace(struct net_device *dev) +{ + struct proc_dir_entry *drv_proc = get_rtw_drv_proc(); + struct proc_dir_entry *dir_dev = NULL; + _adapter *adapter = rtw_netdev_priv(dev); + int i; + + dir_dev = adapter->dir_dev; + + if (dir_dev == NULL) { + rtw_warn_on(1); + return; + } + + for (i=0;iold_ifname, drv_proc); + + adapter->dir_dev = NULL; + + rtw_adapter_proc_init(dev); + +} + +#endif /* CONFIG_PROC_DEBUG */ diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/rtw_proc.h b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/rtw_proc.h new file mode 100644 index 000000000..9aee7bf56 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/rtw_proc.h @@ -0,0 +1,52 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#ifndef __RTW_PROC_H__ +#define __RTW_PROC_H__ + +#include +#include + +struct rtw_proc_hdl { + char *name; + int (*show)(struct seq_file *, void *); + ssize_t (*write)(struct file *file, const char __user *buffer, size_t count, loff_t *pos, void *data); +}; + +#ifdef CONFIG_PROC_DEBUG + +struct proc_dir_entry *get_rtw_drv_proc(void); +int rtw_drv_proc_init(void); +void rtw_drv_proc_deinit(void); +struct proc_dir_entry *rtw_adapter_proc_init(struct net_device *dev); +void rtw_adapter_proc_deinit(struct net_device *dev); +void rtw_adapter_proc_replace(struct net_device *dev); + +#else //!CONFIG_PROC_DEBUG + +#define get_rtw_drv_proc() NULL +#define rtw_drv_proc_init() 0 +#define rtw_drv_proc_deinit() do {} while (0) +#define rtw_adapter_proc_init(dev) NULL +#define rtw_adapter_proc_deinit(dev) do {} while (0) +#define rtw_adapter_proc_replace(dev) do {} while (0) + +#endif //!CONFIG_PROC_DEBUG + +#endif //__RTW_PROC_H__ diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/usb_intf.c b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/usb_intf.c new file mode 100644 index 000000000..72d9e16cd --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/usb_intf.c @@ -0,0 +1,1598 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _HCI_INTF_C_ + +#include +#include + +#ifndef CONFIG_USB_HCI +#error "CONFIG_USB_HCI shall be on!\n" +#endif + +#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) +#error "Shall be Linux or Windows, but not both!\n" +#endif + +#ifdef CONFIG_80211N_HT +extern int rtw_ht_enable; +extern int rtw_bw_mode; +extern int rtw_ampdu_enable;//for enable tx_ampdu +#endif + +#ifdef CONFIG_GLOBAL_UI_PID +int ui_pid[3] = {0, 0, 0}; +#endif + + +extern int pm_netdev_open(struct net_device *pnetdev,u8 bnormal); +static int rtw_suspend(struct usb_interface *intf, pm_message_t message); +static int rtw_resume(struct usb_interface *intf); + + +static int rtw_drv_init(struct usb_interface *pusb_intf,const struct usb_device_id *pdid); +static void rtw_dev_remove(struct usb_interface *pusb_intf); + +static void rtw_dev_shutdown(struct device *dev) +{ + struct usb_interface *usb_intf = container_of(dev, struct usb_interface, dev); + struct dvobj_priv *dvobj = NULL; + _adapter *adapter = NULL; + int i; + + DBG_871X("%s\n", __func__); + + if(usb_intf) + { + dvobj = usb_get_intfdata(usb_intf); + if (dvobj) + { + rtw_set_surprise_removed(dvobj->padapters[IFACE_ID0]); + ATOMIC_SET(&dvobj->continual_io_error, MAX_CONTINUAL_IO_ERR+1); + } + } +} + +#if (LINUX_VERSION_CODE<=KERNEL_VERSION(2,6,23)) +/* Some useful macros to use to create struct usb_device_id */ + #define USB_DEVICE_ID_MATCH_VENDOR 0x0001 + #define USB_DEVICE_ID_MATCH_PRODUCT 0x0002 + #define USB_DEVICE_ID_MATCH_DEV_LO 0x0004 + #define USB_DEVICE_ID_MATCH_DEV_HI 0x0008 + #define USB_DEVICE_ID_MATCH_DEV_CLASS 0x0010 + #define USB_DEVICE_ID_MATCH_DEV_SUBCLASS 0x0020 + #define USB_DEVICE_ID_MATCH_DEV_PROTOCOL 0x0040 + #define USB_DEVICE_ID_MATCH_INT_CLASS 0x0080 + #define USB_DEVICE_ID_MATCH_INT_SUBCLASS 0x0100 + #define USB_DEVICE_ID_MATCH_INT_PROTOCOL 0x0200 + #define USB_DEVICE_ID_MATCH_INT_NUMBER 0x0400 + + +#define USB_DEVICE_ID_MATCH_INT_INFO \ + (USB_DEVICE_ID_MATCH_INT_CLASS | \ + USB_DEVICE_ID_MATCH_INT_SUBCLASS | \ + USB_DEVICE_ID_MATCH_INT_PROTOCOL) + + +#define USB_DEVICE_AND_INTERFACE_INFO(vend, prod, cl, sc, pr) \ + .match_flags = USB_DEVICE_ID_MATCH_INT_INFO \ + | USB_DEVICE_ID_MATCH_DEVICE, \ + .idVendor = (vend), \ + .idProduct = (prod), \ + .bInterfaceClass = (cl), \ + .bInterfaceSubClass = (sc), \ + .bInterfaceProtocol = (pr) + + /** + * USB_VENDOR_AND_INTERFACE_INFO - describe a specific usb vendor with a class of usb interfaces + * @vend: the 16 bit USB Vendor ID + * @cl: bInterfaceClass value + * @sc: bInterfaceSubClass value + * @pr: bInterfaceProtocol value + * + * This macro is used to create a struct usb_device_id that matches a + * specific vendor with a specific class of interfaces. + * + * This is especially useful when explicitly matching devices that have + * vendor specific bDeviceClass values, but standards-compliant interfaces. + */ +#define USB_VENDOR_AND_INTERFACE_INFO(vend, cl, sc, pr) \ + .match_flags = USB_DEVICE_ID_MATCH_INT_INFO \ + | USB_DEVICE_ID_MATCH_VENDOR, \ + .idVendor = (vend), \ + .bInterfaceClass = (cl), \ + .bInterfaceSubClass = (sc), \ + .bInterfaceProtocol = (pr) + +/* ----------------------------------------------------------------------- */ +#endif + + +#define USB_VENDER_ID_REALTEK 0x0BDA + + +/* DID_USB_v916_20130116 */ +static struct usb_device_id rtw_usb_id_tbl[] ={ +#ifdef CONFIG_RTL8188F + /*=== Realtek demoboard ===*/ + {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDER_ID_REALTEK, 0xF179, 0xff, 0xff, 0xff), .driver_info = RTL8188F}, /* 8188FU 1*1 */ +#endif + + {} /* Terminating entry */ +}; + +MODULE_DEVICE_TABLE(usb, rtw_usb_id_tbl); + +int const rtw_usb_id_len = sizeof(rtw_usb_id_tbl) / sizeof(struct usb_device_id); + +struct rtw_usb_drv { + struct usb_driver usbdrv; + int drv_registered; + u8 hw_type; +}; + +struct rtw_usb_drv usb_drv = { + .usbdrv.name =(char*)DRV_NAME, + .usbdrv.probe = rtw_drv_init, + .usbdrv.disconnect = rtw_dev_remove, + .usbdrv.id_table = rtw_usb_id_tbl, + .usbdrv.suspend = rtw_suspend, + .usbdrv.resume = rtw_resume, + #if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22)) + .usbdrv.reset_resume = rtw_resume, + #endif + #ifdef CONFIG_AUTOSUSPEND + .usbdrv.supports_autosuspend = 1, + #endif + + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)) && (LINUX_VERSION_CODE < KERNEL_VERSION(6, 8, 0)) + .usbdrv.drvwrap.driver.shutdown = rtw_dev_shutdown, + #else + .usbdrv.driver.shutdown = rtw_dev_shutdown, + #endif +}; + +static inline int RT_usb_endpoint_dir_in(const struct usb_endpoint_descriptor *epd) +{ + return ((epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN); +} + +static inline int RT_usb_endpoint_dir_out(const struct usb_endpoint_descriptor *epd) +{ + return ((epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT); +} + +static inline int RT_usb_endpoint_xfer_int(const struct usb_endpoint_descriptor *epd) +{ + return ((epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT); +} + +static inline int RT_usb_endpoint_xfer_bulk(const struct usb_endpoint_descriptor *epd) +{ + return ((epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK); +} + +static inline int RT_usb_endpoint_is_bulk_in(const struct usb_endpoint_descriptor *epd) +{ + return (RT_usb_endpoint_xfer_bulk(epd) && RT_usb_endpoint_dir_in(epd)); +} + +static inline int RT_usb_endpoint_is_bulk_out(const struct usb_endpoint_descriptor *epd) +{ + return (RT_usb_endpoint_xfer_bulk(epd) && RT_usb_endpoint_dir_out(epd)); +} + +static inline int RT_usb_endpoint_is_int_in(const struct usb_endpoint_descriptor *epd) +{ + return (RT_usb_endpoint_xfer_int(epd) && RT_usb_endpoint_dir_in(epd)); +} + +static inline int RT_usb_endpoint_num(const struct usb_endpoint_descriptor *epd) +{ + return epd->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; +} + +static u8 rtw_init_intf_priv(struct dvobj_priv *dvobj) +{ + u8 rst = _SUCCESS; + + #ifdef CONFIG_USB_VENDOR_REQ_MUTEX + _rtw_mutex_init(&dvobj->usb_vendor_req_mutex); + #endif + + + #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC + dvobj->usb_alloc_vendor_req_buf = rtw_zmalloc(MAX_USB_IO_CTL_SIZE); + if (dvobj->usb_alloc_vendor_req_buf == NULL) { + DBG_871X("alloc usb_vendor_req_buf failed... /n"); + rst = _FAIL; + goto exit; + } + dvobj->usb_vendor_req_buf = + (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(dvobj->usb_alloc_vendor_req_buf ), ALIGNMENT_UNIT); +exit: + #endif + + return rst; + +} + +static u8 rtw_deinit_intf_priv(struct dvobj_priv *dvobj) +{ + u8 rst = _SUCCESS; + + #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC + if(dvobj->usb_vendor_req_buf) + rtw_mfree(dvobj->usb_alloc_vendor_req_buf, MAX_USB_IO_CTL_SIZE); + #endif + + #ifdef CONFIG_USB_VENDOR_REQ_MUTEX + _rtw_mutex_free(&dvobj->usb_vendor_req_mutex); + #endif + + return rst; +} +static void rtw_decide_chip_type_by_usb_info(struct dvobj_priv *pdvobjpriv, const struct usb_device_id *pdid) +{ + pdvobjpriv->chip_type = pdid->driver_info; + + #ifdef CONFIG_RTL8188E + if (pdvobjpriv->chip_type == RTL8188E) + rtl8188eu_set_hw_type(pdvobjpriv); + #endif + + #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) + if (pdvobjpriv->chip_type == RTL8812 || pdvobjpriv->chip_type == RTL8821) + rtl8812au_set_hw_type(pdvobjpriv); + #endif + + #ifdef CONFIG_RTL8192E + if (pdvobjpriv->chip_type == RTL8192E) + rtl8192eu_set_hw_type(pdvobjpriv); + #endif + + #ifdef CONFIG_RTL8723B + if (pdvobjpriv->chip_type == RTL8723B) + rtl8723bu_set_hw_type(pdvobjpriv); + #endif + + #ifdef CONFIG_RTL8814A + if (pdvobjpriv->chip_type == RTL8814A) + rtl8814au_set_hw_type(pdvobjpriv); + #endif /* CONFIG_RTL8814A */ + + #ifdef CONFIG_RTL8188F + if (pdvobjpriv->chip_type == RTL8188F) + rtl8188fu_set_hw_type(pdvobjpriv); + #endif + + #ifdef CONFIG_RTL8703B + if (pdvobjpriv->chip_type == RTL8703B) + rtl8703bu_set_hw_type(pdvobjpriv); + #endif /* CONFIG_RTL8703B */ + +} + +static struct dvobj_priv *usb_dvobj_init(struct usb_interface *usb_intf, const struct usb_device_id *pdid) +{ + int i; + u8 val8; + int status = _FAIL; + struct dvobj_priv *pdvobjpriv; + struct usb_device_descriptor *pdev_desc; + struct usb_host_config *phost_conf; + struct usb_config_descriptor *pconf_desc; + struct usb_host_interface *phost_iface; + struct usb_interface_descriptor *piface_desc; + struct usb_host_endpoint *phost_endp; + struct usb_endpoint_descriptor *pendp_desc; + struct usb_device *pusbd; + +_func_enter_; + + + if((pdvobjpriv = devobj_init()) == NULL) { + goto exit; + } + + + pdvobjpriv->pusbintf = usb_intf ; + pusbd = pdvobjpriv->pusbdev = interface_to_usbdev(usb_intf); + usb_set_intfdata(usb_intf, pdvobjpriv); + + pdvobjpriv->RtNumInPipes = 0; + pdvobjpriv->RtNumOutPipes = 0; + + //padapter->EepromAddressSize = 6; + //pdvobjpriv->nr_endpoint = 6; + + pdev_desc = &pusbd->descriptor; + +#if 0 + DBG_871X("\n8712_usb_device_descriptor:\n"); + DBG_871X("bLength=%x\n", pdev_desc->bLength); + DBG_871X("bDescriptorType=%x\n", pdev_desc->bDescriptorType); + DBG_871X("bcdUSB=%x\n", pdev_desc->bcdUSB); + DBG_871X("bDeviceClass=%x\n", pdev_desc->bDeviceClass); + DBG_871X("bDeviceSubClass=%x\n", pdev_desc->bDeviceSubClass); + DBG_871X("bDeviceProtocol=%x\n", pdev_desc->bDeviceProtocol); + DBG_871X("bMaxPacketSize0=%x\n", pdev_desc->bMaxPacketSize0); + DBG_871X("idVendor=%x\n", pdev_desc->idVendor); + DBG_871X("idProduct=%x\n", pdev_desc->idProduct); + DBG_871X("bcdDevice=%x\n", pdev_desc->bcdDevice); + DBG_871X("iManufacturer=%x\n", pdev_desc->iManufacturer); + DBG_871X("iProduct=%x\n", pdev_desc->iProduct); + DBG_871X("iSerialNumber=%x\n", pdev_desc->iSerialNumber); + DBG_871X("bNumConfigurations=%x\n", pdev_desc->bNumConfigurations); +#endif + + phost_conf = pusbd->actconfig; + pconf_desc = &phost_conf->desc; + +#if 0 + DBG_871X("\n8712_usb_configuration_descriptor:\n"); + DBG_871X("bLength=%x\n", pconf_desc->bLength); + DBG_871X("bDescriptorType=%x\n", pconf_desc->bDescriptorType); + DBG_871X("wTotalLength=%x\n", pconf_desc->wTotalLength); + DBG_871X("bNumInterfaces=%x\n", pconf_desc->bNumInterfaces); + DBG_871X("bConfigurationValue=%x\n", pconf_desc->bConfigurationValue); + DBG_871X("iConfiguration=%x\n", pconf_desc->iConfiguration); + DBG_871X("bmAttributes=%x\n", pconf_desc->bmAttributes); + DBG_871X("bMaxPower=%x\n", pconf_desc->bMaxPower); +#endif + + //DBG_871X("\n/****** num of altsetting = (%d) ******/\n", pusb_interface->num_altsetting); + + phost_iface = &usb_intf->altsetting[0]; + piface_desc = &phost_iface->desc; + +#if 0 + DBG_871X("\n8712_usb_interface_descriptor:\n"); + DBG_871X("bLength=%x\n", piface_desc->bLength); + DBG_871X("bDescriptorType=%x\n", piface_desc->bDescriptorType); + DBG_871X("bInterfaceNumber=%x\n", piface_desc->bInterfaceNumber); + DBG_871X("bAlternateSetting=%x\n", piface_desc->bAlternateSetting); + DBG_871X("bNumEndpoints=%x\n", piface_desc->bNumEndpoints); + DBG_871X("bInterfaceClass=%x\n", piface_desc->bInterfaceClass); + DBG_871X("bInterfaceSubClass=%x\n", piface_desc->bInterfaceSubClass); + DBG_871X("bInterfaceProtocol=%x\n", piface_desc->bInterfaceProtocol); + DBG_871X("iInterface=%x\n", piface_desc->iInterface); +#endif + + pdvobjpriv->NumInterfaces = pconf_desc->bNumInterfaces; + pdvobjpriv->InterfaceNumber = piface_desc->bInterfaceNumber; + pdvobjpriv->nr_endpoint = piface_desc->bNumEndpoints; + + //DBG_871X("\ndump usb_endpoint_descriptor:\n"); + + for (i = 0; i < pdvobjpriv->nr_endpoint; i++) + { + phost_endp = phost_iface->endpoint + i; + if (phost_endp) + { + pendp_desc = &phost_endp->desc; + + DBG_871X("\nusb_endpoint_descriptor(%d):\n", i); + DBG_871X("bLength=%x\n",pendp_desc->bLength); + DBG_871X("bDescriptorType=%x\n",pendp_desc->bDescriptorType); + DBG_871X("bEndpointAddress=%x\n",pendp_desc->bEndpointAddress); + //DBG_871X("bmAttributes=%x\n",pendp_desc->bmAttributes); + DBG_871X("wMaxPacketSize=%d\n",le16_to_cpu(pendp_desc->wMaxPacketSize)); + DBG_871X("bInterval=%x\n",pendp_desc->bInterval); + //DBG_871X("bRefresh=%x\n",pendp_desc->bRefresh); + //DBG_871X("bSynchAddress=%x\n",pendp_desc->bSynchAddress); + + if (RT_usb_endpoint_is_bulk_in(pendp_desc)) + { + DBG_871X("RT_usb_endpoint_is_bulk_in = %x\n", RT_usb_endpoint_num(pendp_desc)); + pdvobjpriv->RtInPipe[pdvobjpriv->RtNumInPipes] = RT_usb_endpoint_num(pendp_desc); + pdvobjpriv->RtNumInPipes++; + } + else if (RT_usb_endpoint_is_int_in(pendp_desc)) + { + DBG_871X("RT_usb_endpoint_is_int_in = %x, Interval = %x\n", RT_usb_endpoint_num(pendp_desc),pendp_desc->bInterval); + pdvobjpriv->RtInPipe[pdvobjpriv->RtNumInPipes] = RT_usb_endpoint_num(pendp_desc); + pdvobjpriv->RtNumInPipes++; + } + else if (RT_usb_endpoint_is_bulk_out(pendp_desc)) + { + DBG_871X("RT_usb_endpoint_is_bulk_out = %x\n", RT_usb_endpoint_num(pendp_desc)); + pdvobjpriv->RtOutPipe[pdvobjpriv->RtNumOutPipes] = RT_usb_endpoint_num(pendp_desc); + pdvobjpriv->RtNumOutPipes++; + } + pdvobjpriv->ep_num[i] = RT_usb_endpoint_num(pendp_desc); + } + } + + DBG_871X("nr_endpoint=%d, in_num=%d, out_num=%d\n\n", pdvobjpriv->nr_endpoint, pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes); + + switch(pusbd->speed) { + case USB_SPEED_LOW: + DBG_871X("USB_SPEED_LOW\n"); + pdvobjpriv->usb_speed = RTW_USB_SPEED_1_1; + break; + case USB_SPEED_FULL: + DBG_871X("USB_SPEED_FULL\n"); + pdvobjpriv->usb_speed = RTW_USB_SPEED_1_1; + break; + case USB_SPEED_HIGH: + DBG_871X("USB_SPEED_HIGH\n"); + pdvobjpriv->usb_speed = RTW_USB_SPEED_2; + break; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,31)) + case USB_SPEED_SUPER: + DBG_871X("USB_SPEED_SUPER\n"); + pdvobjpriv->usb_speed = RTW_USB_SPEED_3; + break; +#endif + default: + DBG_871X("USB_SPEED_UNKNOWN(%x)\n",pusbd->speed); + pdvobjpriv->usb_speed = RTW_USB_SPEED_UNKNOWN; + break; + } + + if (pdvobjpriv->usb_speed == RTW_USB_SPEED_UNKNOWN) { + DBG_871X("UNKNOWN USB SPEED MODE, ERROR !!!\n"); + goto free_dvobj; + } + + if (rtw_init_intf_priv(pdvobjpriv) == _FAIL) { + RT_TRACE(_module_os_intfs_c_,_drv_err_,("\n Can't INIT rtw_init_intf_priv\n")); + goto free_dvobj; + } + + /*step 1-1., decide the chip_type via driver_info*/ + pdvobjpriv->interface_type = RTW_USB; + rtw_decide_chip_type_by_usb_info(pdvobjpriv, pdid); + + //.3 misc + _rtw_init_sema(&(pdvobjpriv->usb_suspend_sema), 0); + rtw_reset_continual_io_error(pdvobjpriv); + + usb_get_dev(pusbd); + + status = _SUCCESS; + +free_dvobj: + if (status != _SUCCESS && pdvobjpriv) { + usb_set_intfdata(usb_intf, NULL); + + devobj_deinit(pdvobjpriv); + + pdvobjpriv = NULL; + } +exit: +_func_exit_; + return pdvobjpriv; +} + +static void usb_dvobj_deinit(struct usb_interface *usb_intf) +{ + struct dvobj_priv *dvobj = usb_get_intfdata(usb_intf); + +_func_enter_; + + usb_set_intfdata(usb_intf, NULL); + if (dvobj) { + //Modify condition for 92DU DMDP 2010.11.18, by Thomas + if ((dvobj->NumInterfaces != 2 && dvobj->NumInterfaces != 3) + || (dvobj->InterfaceNumber == 1)) { + if (interface_to_usbdev(usb_intf)->state != USB_STATE_NOTATTACHED) { + //If we didn't unplug usb dongle and remove/insert modlue, driver fails on sitesurvey for the first time when device is up . + //Reset usb port for sitesurvey fail issue. 2009.8.13, by Thomas + DBG_871X("usb attached..., try to reset usb device\n"); + usb_reset_device(interface_to_usbdev(usb_intf)); + } + } + + rtw_deinit_intf_priv(dvobj); + + devobj_deinit(dvobj); + } + + //DBG_871X("%s %d\n", __func__, ATOMIC_READ(&usb_intf->dev.kobj.kref.refcount)); + usb_put_dev(interface_to_usbdev(usb_intf)); + +_func_exit_; +} + +static int usb_reprobe_to_usb3(PADAPTER Adapter) +{ + struct registry_priv *registry_par = &Adapter->registrypriv; + int ret = _FALSE; + + if (registry_par->switch_usb3 == _TRUE) { + if (IS_HIGH_SPEED_USB(Adapter)) { + if ((rtw_read8(Adapter, 0x74) & (BIT(2)|BIT(3))) != BIT(3)) { + rtw_write8(Adapter, 0x74, 0x8); + rtw_write8(Adapter, 0x70, 0x2); + rtw_write8(Adapter, 0x3e, 0x1); + rtw_write8(Adapter, 0x3d, 0x3); + /* usb disconnect */ + rtw_write8(Adapter, 0x5, 0x80); + ret = _TRUE; + } + + } else if (IS_SUPER_SPEED_USB(Adapter)) { + rtw_write8(Adapter, 0x70, rtw_read8(Adapter, 0x70) & (~BIT(1))); + rtw_write8(Adapter, 0x3e, rtw_read8(Adapter, 0x3e) & (~BIT(0))); + } + } + + return ret; +} + +u8 rtw_set_hal_ops(_adapter *padapter) +{ + //alloc memory for HAL DATA + if (rtw_hal_data_init(padapter) == _FAIL) + return _FAIL; + + #ifdef CONFIG_RTL8188E + if (rtw_get_chip_type(padapter) == RTL8188E) + rtl8188eu_set_hal_ops(padapter); + #endif + + #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) + if (rtw_get_chip_type(padapter) == RTL8812 || rtw_get_chip_type(padapter) == RTL8821) + rtl8812au_set_hal_ops(padapter); + #endif + + #ifdef CONFIG_RTL8192E + if (rtw_get_chip_type(padapter) == RTL8192E) + rtl8192eu_set_hal_ops(padapter); + #endif + #ifdef CONFIG_RTL8723B + if (rtw_get_chip_type(padapter) == RTL8723B) + rtl8723bu_set_hal_ops(padapter); + #endif + #ifdef CONFIG_RTL8814A + if (rtw_get_chip_type(padapter) == RTL8814A) + rtl8814au_set_hal_ops(padapter); + #endif /* CONFIG_RTL8814A */ + + #ifdef CONFIG_RTL8188F + if (rtw_get_chip_type(padapter) == RTL8188F) + rtl8188fu_set_hal_ops(padapter); + #endif + + #ifdef CONFIG_RTL8703B + if (rtw_get_chip_type(padapter) == RTL8703B) + rtl8703bu_set_hal_ops(padapter); + #endif /* CONFIG_RTL8703B */ + + if (_FAIL == rtw_hal_ops_check(padapter) ) + return _FAIL; + + if (hal_spec_init(padapter) == _FAIL) + return _FAIL; + + return _SUCCESS; +} + +void usb_set_intf_ops(_adapter *padapter,struct _io_ops *pops) +{ + #ifdef CONFIG_RTL8188E + if (rtw_get_chip_type(padapter) == RTL8188E) + rtl8188eu_set_intf_ops(pops); + #endif + + #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) + if (rtw_get_chip_type(padapter) == RTL8812 || rtw_get_chip_type(padapter) == RTL8821) + rtl8812au_set_intf_ops(pops); + #endif + + #ifdef CONFIG_RTL8192E + if (rtw_get_chip_type(padapter) == RTL8192E) + rtl8192eu_set_intf_ops(pops); + #endif + + #ifdef CONFIG_RTL8723B + if (rtw_get_chip_type(padapter) == RTL8723B) + rtl8723bu_set_intf_ops(pops); + #endif + + #ifdef CONFIG_RTL8814A + if (rtw_get_chip_type(padapter) == RTL8814A) + rtl8814au_set_intf_ops(pops); + #endif /* CONFIG_RTL8814A */ + + #ifdef CONFIG_RTL8188F + if (rtw_get_chip_type(padapter) == RTL8188F) + rtl8188fu_set_intf_ops(pops); + #endif + + #ifdef CONFIG_RTL8703B + if (rtw_get_chip_type(padapter) == RTL8703B) + rtl8703bu_set_intf_ops(pops); + #endif /* CONFIG_RTL8703B */ +} + + +static void usb_intf_start(_adapter *padapter) +{ + + RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+usb_intf_start\n")); + + rtw_hal_inirp_init(padapter); + + RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-usb_intf_start\n")); + +} + +static void usb_intf_stop(_adapter *padapter) +{ + + RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+usb_intf_stop\n")); + + //disabel_hw_interrupt + if (!rtw_is_surprise_removed(padapter)) { + //device still exists, so driver can do i/o operation + //TODO: + RT_TRACE(_module_hci_intfs_c_,_drv_err_,("SurpriseRemoved==_FALSE\n")); + } + + //cancel in irp + rtw_hal_inirp_deinit(padapter); + + //cancel out irp + rtw_write_port_cancel(padapter); + + //todo:cancel other irps + + RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-usb_intf_stop\n")); + +} + +#ifdef SUPPORT_HW_RFOFF_DETECTED +int rtw_hw_suspend(_adapter *padapter ) +{ + struct pwrctrl_priv *pwrpriv; + struct usb_interface *pusb_intf; + struct net_device *pnetdev; + + _func_enter_; + if(NULL==padapter) + goto error_exit; + + if ((_FALSE == padapter->bup) || RTW_CANNOT_RUN(padapter)) { + DBG_871X("padapter->bup=%d bDriverStopped=%s bSurpriseRemoved = %s\n" + , padapter->bup + , rtw_is_drv_stopped(padapter)?"True":"False" + , rtw_is_surprise_removed(padapter)?"True":"False"); + goto error_exit; + } + + pwrpriv = adapter_to_pwrctl(padapter); + pusb_intf = adapter_to_dvobj(padapter)->pusbintf; + pnetdev = padapter->pnetdev; + + LeaveAllPowerSaveMode(padapter); + + DBG_871X("==> rtw_hw_suspend\n"); + _enter_pwrlock(&pwrpriv->lock); + pwrpriv->bips_processing = _TRUE; + //padapter->net_closed = _TRUE; + //s1. + if(pnetdev) + { + netif_carrier_off(pnetdev); + rtw_netif_stop_queue(pnetdev); + } + + //s2. + rtw_disassoc_cmd(padapter, 500, _FALSE); + + //s2-2. indicate disconnect to os + //rtw_indicate_disconnect(padapter); + { + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + if(check_fwstate(pmlmepriv, _FW_LINKED)) + { + _clr_fwstate_(pmlmepriv, _FW_LINKED); + rtw_led_control(padapter, LED_CTL_NO_LINK); + + rtw_os_indicate_disconnect(padapter, 0, _FALSE); + + #ifdef CONFIG_LPS + //donnot enqueue cmd + rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_DISCONNECT, 0); + #endif + } + } + //s2-3. + rtw_free_assoc_resources(padapter, 1); + + //s2-4. + rtw_free_network_queue(padapter,_TRUE); + #ifdef CONFIG_IPS + rtw_ips_dev_unload(padapter); + #endif + pwrpriv->rf_pwrstate = rf_off; + pwrpriv->bips_processing = _FALSE; + _exit_pwrlock(&pwrpriv->lock); + + _func_exit_; + return 0; + +error_exit: + DBG_871X("%s, failed \n",__FUNCTION__); + return (-1); + +} + +int rtw_hw_resume(_adapter *padapter) +{ + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct usb_interface *pusb_intf = adapter_to_dvobj(padapter)->pusbintf; + struct net_device *pnetdev = padapter->pnetdev; + + _func_enter_; + DBG_871X("==> rtw_hw_resume\n"); + _enter_pwrlock(&pwrpriv->lock); + pwrpriv->bips_processing = _TRUE; + rtw_reset_drv_sw(padapter); + + if(pm_netdev_open(pnetdev,_FALSE) != 0) + { + _exit_pwrlock(&pwrpriv->lock); + goto error_exit; + } + + netif_device_attach(pnetdev); + netif_carrier_on(pnetdev); + + rtw_netif_wake_queue(pnetdev); + + pwrpriv->bkeepfwalive = _FALSE; + pwrpriv->brfoffbyhw = _FALSE; + + pwrpriv->rf_pwrstate = rf_on; + pwrpriv->bips_processing = _FALSE; + _exit_pwrlock(&pwrpriv->lock); + + _func_exit_; + + return 0; +error_exit: + DBG_871X("%s, Open net dev failed \n",__FUNCTION__); + return (-1); +} +#endif + +static int rtw_suspend(struct usb_interface *pusb_intf, pm_message_t message) +{ + struct dvobj_priv *dvobj; + struct pwrctrl_priv *pwrpriv; + struct debug_priv *pdbgpriv; + PADAPTER padapter; + int ret = 0; + + + dvobj = usb_get_intfdata(pusb_intf); + pwrpriv = dvobj_to_pwrctl(dvobj); + pdbgpriv = &dvobj->drv_dbg; + padapter = dvobj->padapters[IFACE_ID0]; + + if (pwrpriv->bInSuspend == _TRUE) { + DBG_871X("%s bInSuspend = %d\n", __FUNCTION__, pwrpriv->bInSuspend); + pdbgpriv->dbg_suspend_error_cnt++; + goto exit; + } + + if ((padapter->bup) || !rtw_is_drv_stopped(padapter) || !rtw_is_surprise_removed(padapter)) { +#ifdef CONFIG_AUTOSUSPEND + if(pwrpriv->bInternalAutoSuspend ){ + + #ifdef SUPPORT_HW_RFOFF_DETECTED + // The FW command register update must after MAC and FW init ready. + if((padapter->bFWReady) && (pwrpriv->bHWPwrPindetect ) && (padapter->registrypriv.usbss_enable )) + { + u8 bOpen = _TRUE; + rtw_interface_ps_func(padapter,HAL_USB_SELECT_SUSPEND,&bOpen); + } + #endif//SUPPORT_HW_RFOFF_DETECTED + } +#endif//CONFIG_AUTOSUSPEND + } + + ret = rtw_suspend_common(padapter); + +exit: + return ret; +} + +int rtw_resume_process(_adapter *padapter) +{ + int ret,pm_cnt = 0; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); + struct dvobj_priv *pdvobj = padapter->dvobj; + struct debug_priv *pdbgpriv = &pdvobj->drv_dbg; + + + if (pwrpriv->bInSuspend == _FALSE) + { + pdbgpriv->dbg_resume_error_cnt++; + DBG_871X("%s bInSuspend = %d\n", __FUNCTION__, pwrpriv->bInSuspend); + return -1; + } + +#if defined(CONFIG_BT_COEXIST) && defined(CONFIG_AUTOSUSPEND) //add by amy for 8723as-vau +#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,32)) + DBG_871X("%s...pm_usage_cnt(%d) pwrpriv->bAutoResume=%x. ....\n",__func__,atomic_read(&(adapter_to_dvobj(padapter)->pusbintf->pm_usage_cnt)),pwrpriv->bAutoResume); + pm_cnt=atomic_read(&(adapter_to_dvobj(padapter)->pusbintf->pm_usage_cnt)); +#else // kernel < 2.6.32 + DBG_871X("...pm_usage_cnt(%d).....\n", adapter_to_dvobj(padapter)->pusbintf->pm_usage_cnt); + pm_cnt = adapter_to_dvobj(padapter)->pusbintf->pm_usage_cnt; +#endif // kernel < 2.6.32 + + DBG_871X("pwrpriv->bAutoResume (%x)\n",pwrpriv->bAutoResume ); + if( _TRUE == pwrpriv->bAutoResume ){ + pwrpriv->bInternalAutoSuspend = _FALSE; + pwrpriv->bAutoResume=_FALSE; + DBG_871X("pwrpriv->bAutoResume (%x) pwrpriv->bInternalAutoSuspend(%x)\n",pwrpriv->bAutoResume,pwrpriv->bInternalAutoSuspend ); + + } +#endif //#ifdef CONFIG_BT_COEXIST &CONFIG_AUTOSUSPEND& + + + ret = rtw_resume_common(padapter); + + #ifdef CONFIG_AUTOSUSPEND + if(pwrpriv->bInternalAutoSuspend ) + { + #ifdef SUPPORT_HW_RFOFF_DETECTED + // The FW command register update must after MAC and FW init ready. + if((padapter->bFWReady) && (pwrpriv->bHWPwrPindetect) && (padapter->registrypriv.usbss_enable )) + { + u8 bOpen = _FALSE; + rtw_interface_ps_func(padapter,HAL_USB_SELECT_SUSPEND,&bOpen); + } + #endif + #ifdef CONFIG_BT_COEXIST // for 8723as-vau + DBG_871X("pwrpriv->bAutoResume (%x)\n",pwrpriv->bAutoResume ); + if( _TRUE == pwrpriv->bAutoResume ){ + pwrpriv->bInternalAutoSuspend = _FALSE; + pwrpriv->bAutoResume=_FALSE; + DBG_871X("pwrpriv->bAutoResume (%x) pwrpriv->bInternalAutoSuspend(%x)\n",pwrpriv->bAutoResume,pwrpriv->bInternalAutoSuspend ); + } + + #else //#ifdef CONFIG_BT_COEXIST + pwrpriv->bInternalAutoSuspend = _FALSE; + #endif //#ifdef CONFIG_BT_COEXIST + pwrpriv->brfoffbyhw = _FALSE; + } + #endif//CONFIG_AUTOSUSPEND + + + return ret; +} + +static int rtw_resume(struct usb_interface *pusb_intf) +{ + struct dvobj_priv *dvobj; + struct pwrctrl_priv *pwrpriv; + struct debug_priv *pdbgpriv; + PADAPTER padapter; + struct mlme_ext_priv *pmlmeext; + int ret = 0; + + + dvobj = usb_get_intfdata(pusb_intf); + pwrpriv = dvobj_to_pwrctl(dvobj); + pdbgpriv = &dvobj->drv_dbg; + padapter = dvobj->padapters[IFACE_ID0]; + pmlmeext = &padapter->mlmeextpriv; + + DBG_871X("==> %s (%s:%d)\n", __FUNCTION__, current->comm, current->pid); + pdbgpriv->dbg_resume_cnt++; + + if(pwrpriv->bInternalAutoSuspend) + { + ret = rtw_resume_process(padapter); + } + else + { + if(pwrpriv->wowlan_mode || pwrpriv->wowlan_ap_mode) + { + rtw_resume_lock_suspend(); + ret = rtw_resume_process(padapter); + rtw_resume_unlock_suspend(); + } + else + { +#ifdef CONFIG_RESUME_IN_WORKQUEUE + rtw_resume_in_workqueue(pwrpriv); +#else + if (rtw_is_earlysuspend_registered(pwrpriv)) + { + /* jeff: bypass resume here, do in late_resume */ + rtw_set_do_late_resume(pwrpriv, _TRUE); + } + else + { + rtw_resume_lock_suspend(); + ret = rtw_resume_process(padapter); + rtw_resume_unlock_suspend(); + } +#endif + } + } + + pmlmeext->last_scan_time = rtw_get_current_time(); + DBG_871X("<======== %s return %d\n", __FUNCTION__, ret); + + return ret; +} + + + +#ifdef CONFIG_AUTOSUSPEND +void autosuspend_enter(_adapter* padapter) +{ + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); + + DBG_871X("==>autosuspend_enter...........\n"); + + pwrpriv->bInternalAutoSuspend = _TRUE; + pwrpriv->bips_processing = _TRUE; + + if(rf_off == pwrpriv->change_rfpwrstate ) + { +#ifndef CONFIG_BT_COEXIST + #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) + usb_enable_autosuspend(dvobj->pusbdev); + #else + dvobj->pusbdev->autosuspend_disabled = 0;//autosuspend disabled by the user + #endif + + #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,33)) + usb_autopm_put_interface(dvobj->pusbintf); + #elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,20)) + usb_autopm_enable(dvobj->pusbintf); + #else + usb_autosuspend_device(dvobj->pusbdev, 1); + #endif +#else //#ifndef CONFIG_BT_COEXIST + if(1==pwrpriv->autopm_cnt){ + #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) + usb_enable_autosuspend(dvobj->pusbdev); + #else + dvobj->pusbdev->autosuspend_disabled = 0;//autosuspend disabled by the user + #endif + + #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,33)) + usb_autopm_put_interface(dvobj->pusbintf); + #elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,20)) + usb_autopm_enable(dvobj->pusbintf); + #else + usb_autosuspend_device(dvobj->pusbdev, 1); + #endif + pwrpriv->autopm_cnt --; + } + else + DBG_871X("0!=pwrpriv->autopm_cnt[%d] didn't usb_autopm_put_interface\n", pwrpriv->autopm_cnt); + +#endif //#ifndef CONFIG_BT_COEXIST + } + #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,32)) + DBG_871X("...pm_usage_cnt(%d).....\n", atomic_read(&(dvobj->pusbintf->pm_usage_cnt))); + #else + DBG_871X("...pm_usage_cnt(%d).....\n", dvobj->pusbintf->pm_usage_cnt); + #endif + +} + +int autoresume_enter(_adapter* padapter) +{ + int result = _SUCCESS; + struct security_priv* psecuritypriv=&(padapter->securitypriv); + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); + struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct pwrctrl_priv *pwrpriv = dvobj_to_pwrctl(dvobj); + + DBG_871X("====> autoresume_enter \n"); + + if(rf_off == pwrpriv->rf_pwrstate ) + { + pwrpriv->ps_flag = _FALSE; +#ifndef CONFIG_BT_COEXIST + #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,33)) + if (usb_autopm_get_interface(dvobj->pusbintf) < 0) + { + DBG_871X( "can't get autopm: %d\n", result); + result = _FAIL; + goto error_exit; + } + #elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,20)) + usb_autopm_disable(dvobj->pusbintf); + #else + usb_autoresume_device(dvobj->pusbdev, 1); + #endif + + #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,32)) + DBG_871X("...pm_usage_cnt(%d).....\n", atomic_read(&(dvobj->pusbintf->pm_usage_cnt))); + #else + DBG_871X("...pm_usage_cnt(%d).....\n", dvobj->pusbintf->pm_usage_cnt); + #endif +#else //#ifndef CONFIG_BT_COEXIST + pwrpriv->bAutoResume=_TRUE; + if(0==pwrpriv->autopm_cnt){ + #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,33)) + if (usb_autopm_get_interface(dvobj->pusbintf) < 0) + { + DBG_871X( "can't get autopm: %d\n", result); + result = _FAIL; + goto error_exit; + } + #elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,20)) + usb_autopm_disable(dvobj->pusbintf); + #else + usb_autoresume_device(dvobj->pusbdev, 1); + #endif + #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,32)) + DBG_871X("...pm_usage_cnt(%d).....\n", atomic_read(&(dvobj->pusbintf->pm_usage_cnt))); + #else + DBG_871X("...pm_usage_cnt(%d).....\n", dvobj->pusbintf->pm_usage_cnt); + #endif + pwrpriv->autopm_cnt++; + } + else + DBG_871X("0!=pwrpriv->autopm_cnt[%d] didn't usb_autopm_get_interface\n",pwrpriv->autopm_cnt); +#endif //#ifndef CONFIG_BT_COEXIST + } + DBG_871X("<==== autoresume_enter \n"); +error_exit: + + return result; +} +#endif + +#ifdef CONFIG_PLATFORM_RTD2880B +extern void rtd2885_wlan_netlink_sendMsg(char *action_string, char *name); +#endif + +/* + * drv_init() - a device potentially for us + * + * notes: drv_init() is called when the bus driver has located a card for us to support. + * We accept the new device by returning 0. +*/ + +_adapter *rtw_sw_export = NULL; + +_adapter *rtw_usb_if1_init(struct dvobj_priv *dvobj, + struct usb_interface *pusb_intf) +{ + _adapter *padapter = NULL; + int status = _FAIL; + + padapter = (_adapter *)rtw_zvmalloc(sizeof(*padapter)); + if (padapter == NULL) + goto exit; + + if (loadparam(padapter) != _SUCCESS) + goto free_adapter; + + padapter->dvobj = dvobj; + + + rtw_set_drv_stopped(padapter);/*init*/ + + dvobj->padapters[dvobj->iface_nums++] = padapter; + padapter->iface_id = IFACE_ID0; + +#if defined(CONFIG_CONCURRENT_MODE) + //set adapter_type/iface type for primary padapter + padapter->isprimary = _TRUE; + padapter->adapter_type = PRIMARY_ADAPTER; + #ifndef CONFIG_HWPORT_SWAP + padapter->iface_type = IFACE_PORT0; + #else + padapter->iface_type = IFACE_PORT1; + #endif +#endif + + //step 2. hook HalFunc, allocate HalData + //hal_set_hal_ops(padapter); + if(rtw_set_hal_ops(padapter) ==_FAIL) + goto free_hal_data; + + + padapter->intf_start=&usb_intf_start; + padapter->intf_stop=&usb_intf_stop; + + //step init_io_priv + if( rtw_init_io_priv(padapter,usb_set_intf_ops) ==_FAIL) + goto free_hal_data; + + //step read_chip_version + rtw_hal_read_chip_version(padapter); + + //step usb endpoint mapping + rtw_hal_chip_configure(padapter); + +#ifdef CONFIG_BT_COEXIST + rtw_btcoex_Initialize(padapter); +#endif // CONFIG_BT_COEXIST + + //step read efuse/eeprom data and get mac_addr + rtw_hal_read_chip_info(padapter); + + //step 5. + if(rtw_init_drv_sw(padapter) ==_FAIL) { + RT_TRACE(_module_hci_intfs_c_,_drv_err_,("Initialize driver software resource Failed!\n")); + goto free_hal_data; + } + +#ifdef CONFIG_PM +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18)) + if(dvobj_to_pwrctl(dvobj)->bSupportRemoteWakeup) + { + dvobj->pusbdev->do_remote_wakeup=1; + pusb_intf->needs_remote_wakeup = 1; + device_init_wakeup(&pusb_intf->dev, 1); + DBG_871X("pwrctrlpriv.bSupportRemoteWakeup~~~~~~\n"); + DBG_871X("pwrctrlpriv.bSupportRemoteWakeup~~~[%d]~~~\n",device_may_wakeup(&pusb_intf->dev)); + } +#endif +#endif + +#ifdef CONFIG_AUTOSUSPEND + if( padapter->registrypriv.power_mgnt != PS_MODE_ACTIVE ) + { + if(padapter->registrypriv.usbss_enable ){ /* autosuspend (2s delay) */ + #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,38)) + dvobj->pusbdev->dev.power.autosuspend_delay = 0 * HZ;//15 * HZ; idle-delay time + #else + dvobj->pusbdev->autosuspend_delay = 0 * HZ;//15 * HZ; idle-delay time + #endif + + #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) + usb_enable_autosuspend(dvobj->pusbdev); + #elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,22) && LINUX_VERSION_CODE<=KERNEL_VERSION(2,6,34)) + padapter->bDisableAutosuspend = dvobj->pusbdev->autosuspend_disabled ; + dvobj->pusbdev->autosuspend_disabled = 0;//autosuspend disabled by the user + #endif + + //usb_autopm_get_interface(adapter_to_dvobj(padapter)->pusbintf );//init pm_usage_cnt ,let it start from 1 + + #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,32)) + DBG_871X("%s...pm_usage_cnt(%d).....\n",__FUNCTION__,atomic_read(&(dvobj->pusbintf ->pm_usage_cnt))); + #else + DBG_871X("%s...pm_usage_cnt(%d).....\n",__FUNCTION__,dvobj->pusbintf ->pm_usage_cnt); + #endif + } + } +#endif + //2012-07-11 Move here to prevent the 8723AS-VAU BT auto suspend influence + #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,33)) + if (usb_autopm_get_interface(pusb_intf) < 0) + { + DBG_871X( "can't get autopm: \n"); + } + #endif +#ifdef CONFIG_BT_COEXIST + dvobj_to_pwrctl(dvobj)->autopm_cnt=1; +#endif + + // set mac addr + rtw_macaddr_cfg(adapter_mac_addr(padapter), get_hal_mac_addr(padapter)); +#ifdef CONFIG_P2P + rtw_init_wifidirect_addrs(padapter, adapter_mac_addr(padapter), adapter_mac_addr(padapter)); +#endif // CONFIG_P2P + DBG_871X("bDriverStopped:%s, bSurpriseRemoved:%s, bup:%d, hw_init_completed:%d\n" + , rtw_is_drv_stopped(padapter)?"True":"False" + , rtw_is_surprise_removed(padapter)?"True":"False" + , padapter->bup + , rtw_get_hw_init_completed(padapter) + ); + + status = _SUCCESS; + +free_hal_data: + if (status != _SUCCESS && padapter->HalData) + rtw_hal_free_data(padapter); +free_adapter: + if (status != _SUCCESS && padapter) { + rtw_vmfree((u8 *)padapter, sizeof(*padapter)); + padapter = NULL; + } +exit: + return padapter; +} + +static void rtw_usb_if1_deinit(_adapter *if1) +{ + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(if1); + struct mlme_priv *pmlmepriv= &if1->mlmepriv; + + if(check_fwstate(pmlmepriv, _FW_LINKED)) + rtw_disassoc_cmd(if1, 0, _FALSE); + + +#ifdef CONFIG_AP_MODE + free_mlme_ap_info(if1); + #ifdef CONFIG_HOSTAPD_MLME + hostapd_mode_unload(if1); + #endif +#endif + + rtw_dev_unload(if1); + + DBG_871X("+r871xu_dev_remove, hw_init_completed=%d\n", rtw_get_hw_init_completed(if1)); + +#ifdef CONFIG_BT_COEXIST + if(1 == pwrctl->autopm_cnt){ + #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,33)) + usb_autopm_put_interface(adapter_to_dvobj(if1)->pusbintf); + #elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,20)) + usb_autopm_enable(adapter_to_dvobj(if1)->pusbintf); + #else + usb_autosuspend_device(adapter_to_dvobj(if1)->pusbdev, 1); + #endif + pwrctl->autopm_cnt --; + } +#endif + + rtw_free_drv_sw(if1); + + /* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */ + rtw_os_ndev_free(if1); + + rtw_vmfree((u8 *)if1, sizeof(_adapter)); + +#ifdef CONFIG_PLATFORM_RTD2880B + DBG_871X("wlan link down\n"); + rtd2885_wlan_netlink_sendMsg("linkdown", "8712"); +#endif + +} + +static int rtw_drv_init(struct usb_interface *pusb_intf, const struct usb_device_id *pdid) +{ + _adapter *if1 = NULL, *if2 = NULL; + int status = _FAIL; + struct dvobj_priv *dvobj; +#ifdef CONFIG_MULTI_VIR_IFACES + int i; +#endif //CONFIG_MULTI_VIR_IFACES + + RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("+rtw_drv_init\n")); + //DBG_871X("+rtw_drv_init\n"); + + /* Initialize dvobj_priv */ + if ((dvobj = usb_dvobj_init(pusb_intf, pdid)) == NULL) { + RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("initialize device object priv Failed!\n")); + goto exit; + } + + if ((if1 = rtw_usb_if1_init(dvobj, pusb_intf)) == NULL) { + DBG_871X("rtw_usb_if1_init Failed!\n"); + goto free_dvobj; + } + + if (usb_reprobe_to_usb3(if1) == _TRUE) + goto free_if1; + +#ifdef CONFIG_CONCURRENT_MODE + if((if2 = rtw_drv_if2_init(if1, usb_set_intf_ops)) == NULL) { + goto free_if1; + } +#ifdef CONFIG_MULTI_VIR_IFACES + for(i=0; iregistrypriv.ext_iface_num;i++) + { + if(rtw_drv_add_vir_if(if1, usb_set_intf_ops) == NULL) + { + DBG_871X("rtw_drv_add_iface failed! (%d)\n", i); + goto free_if2; + } + } +#endif //CONFIG_MULTI_VIR_IFACES +#endif + +#ifdef CONFIG_INTEL_PROXIM + rtw_sw_export=if1; +#endif + +#ifdef CONFIG_GLOBAL_UI_PID + if(ui_pid[1]!=0) { + DBG_871X("ui_pid[1]:%d\n",ui_pid[1]); + rtw_signal_process(ui_pid[1], SIGUSR2); + } +#endif + + //dev_alloc_name && register_netdev + if (rtw_os_ndevs_init(dvobj) != _SUCCESS) + goto free_if2; + +#ifdef CONFIG_HOSTAPD_MLME + hostapd_mode_init(if1); +#endif + +#ifdef CONFIG_PLATFORM_RTD2880B + DBG_871X("wlan link up\n"); + rtd2885_wlan_netlink_sendMsg("linkup", "8712"); +#endif + + RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-871x_drv - drv_init, success!\n")); + + status = _SUCCESS; + +#if 0 /* not used now */ +os_ndevs_deinit: + if (status != _SUCCESS) + rtw_os_ndevs_deinit(dvobj); +#endif +free_if2: + if(status != _SUCCESS && if2) { + #ifdef CONFIG_CONCURRENT_MODE + rtw_drv_if2_stop(if2); + rtw_drv_if2_free(if2); + #endif + } +free_if1: + if (status != _SUCCESS && if1) { + rtw_usb_if1_deinit(if1); + } +free_dvobj: + if (status != _SUCCESS) + usb_dvobj_deinit(pusb_intf); +exit: + return status == _SUCCESS?0:-ENODEV; +} + +/* + * dev_remove() - our device is being removed +*/ +//rmmod module & unplug(SurpriseRemoved) will call r871xu_dev_remove() => how to recognize both +static void rtw_dev_remove(struct usb_interface *pusb_intf) +{ + struct dvobj_priv *dvobj = usb_get_intfdata(pusb_intf); + struct pwrctrl_priv *pwrctl = dvobj_to_pwrctl(dvobj); + _adapter *padapter = dvobj->padapters[IFACE_ID0]; + struct net_device *pnetdev = padapter->pnetdev; + struct mlme_priv *pmlmepriv= &padapter->mlmepriv; + +_func_enter_; + + DBG_871X("+rtw_dev_remove\n"); + RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+dev_remove()\n")); + + dvobj->processing_dev_remove = _TRUE; + + /* TODO: use rtw_os_ndevs_deinit instead at the first stage of driver's dev deinit function */ + rtw_os_ndevs_unregister(dvobj); + + if(usb_drv.drv_registered == _TRUE) + { + //DBG_871X("r871xu_dev_remove():padapter->bSurpriseRemoved == _TRUE\n"); + rtw_set_surprise_removed(padapter); + } + /*else + { + //DBG_871X("r871xu_dev_remove():module removed\n"); + padapter->HalData->hw_init_completed = _FALSE; + }*/ + + +#if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER) + rtw_unregister_early_suspend(pwrctl); +#endif + + if (padapter->bFWReady == _TRUE) { + rtw_pm_set_ips(padapter, IPS_NONE); + rtw_pm_set_lps(padapter, PS_MODE_ACTIVE); + + LeaveAllPowerSaveMode(padapter); + } + rtw_set_drv_stopped(padapter); /*for stop thread*/ + + /* stop cmd thread */ + rtw_stop_cmd_thread(padapter); +#ifdef CONFIG_CONCURRENT_MODE +#ifdef CONFIG_MULTI_VIR_IFACES + rtw_drv_stop_vir_ifaces(dvobj); +#endif //CONFIG_MULTI_VIR_IFACES + rtw_drv_if2_stop(dvobj->padapters[IFACE_ID1]); +#endif //CONFIG_CONCURRENT_MODE + + #ifdef CONFIG_BT_COEXIST + rtw_btcoex_HaltNotify(padapter); + #endif + + rtw_usb_if1_deinit(padapter); + +#ifdef CONFIG_CONCURRENT_MODE +#ifdef CONFIG_MULTI_VIR_IFACES + rtw_drv_free_vir_ifaces(dvobj); +#endif //CONFIG_MULTI_VIR_IFACES + rtw_drv_if2_free(dvobj->padapters[IFACE_ID1]); +#endif //CONFIG_CONCURRENT_MODE + + usb_dvobj_deinit(pusb_intf); + + RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-dev_remove()\n")); + DBG_871X("-r871xu_dev_remove, done\n"); + + +#ifdef CONFIG_INTEL_PROXIM + rtw_sw_export=NULL; +#endif + +_func_exit_; + + return; + +} +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) +extern int console_suspend_enabled; +#endif + +static int /*__init*/ rtw_drv_entry(void) +{ + int ret = 0; + + DBG_871X_LEVEL(_drv_always_, "module init start\n"); + dump_drv_version(RTW_DBGDUMP); +#ifdef BTCOEXVERSION + DBG_871X_LEVEL(_drv_always_, DRV_NAME" BT-Coex version = %s\n", BTCOEXVERSION); +#endif // BTCOEXVERSION + + if(ret != 0) + { + DBG_871X("%s: power on failed!!(%d)\n", __FUNCTION__, ret); + ret = -1; + goto exit; + } +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) + //console_suspend_enabled=0; +#endif + + usb_drv.drv_registered = _TRUE; + rtw_suspend_lock_init(); + rtw_drv_proc_init(); + rtw_ndev_notifier_register(); + + ret = usb_register(&usb_drv.usbdrv); + + if (ret != 0) { + usb_drv.drv_registered = _FALSE; + rtw_suspend_lock_uninit(); + rtw_drv_proc_deinit(); + rtw_ndev_notifier_unregister(); + goto exit; + } + +exit: + DBG_871X_LEVEL(_drv_always_, "module init ret=%d\n", ret); + return ret; +} + +static void /*__exit*/ rtw_drv_halt(void) +{ + DBG_871X_LEVEL(_drv_always_, "module exit start\n"); + + usb_drv.drv_registered = _FALSE; + + usb_deregister(&usb_drv.usbdrv); + + rtw_suspend_lock_uninit(); + rtw_drv_proc_deinit(); + rtw_ndev_notifier_unregister(); + + DBG_871X_LEVEL(_drv_always_, "module exit success\n"); + + rtw_mstat_dump(RTW_DBGDUMP); +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0)) +#include +extern int get_wifi_chip_type(void); +#else +extern int rk29sdk_wifi_power(int on); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0)) +int rockchip_wifi_init_module_rtkwifi(void) +#else +int rockchip_wifi_init_module(void) +#endif +{ +#ifdef CONFIG_WIFI_LOAD_DRIVER_WHEN_KERNEL_BOOTUP + int type = get_wifi_chip_type(); + if (type < WIFI_AP6XXX_SERIES || type == WIFI_ESP8089) return 0; +#endif + printk("\n"); + printk("=======================================================\n"); + printk("==== Launching Wi-Fi driver! (Powered by Rockchip) ====\n"); + printk("=======================================================\n"); + printk("Realtek 8188FU USB WiFi driver (Powered by Rockchip) init.\n"); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0)) +#if 0 + rockchip_wifi_power(1); + //rockchip_wifi_set_carddetect(1); +#endif +#else + rk29sdk_wifi_power(1); +#endif + + return rtw_drv_entry(); +} + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0)) +void rockchip_wifi_exit_module_rtkwifi(void) +#else +void rockchip_wifi_exit_module(void) +#endif +{ +#ifdef CONFIG_WIFI_LOAD_DRIVER_WHEN_KERNEL_BOOTUP + int type = get_wifi_chip_type(); + if (type < WIFI_AP6XXX_SERIES || type == WIFI_ESP8089) return; +#endif + printk("\n"); + printk("=======================================================\n"); + printk("==== Dislaunching Wi-Fi driver! (Powered by Rockchip) ====\n"); + printk("=======================================================\n"); + printk("Realtek 8188FU USB WiFi driver (Powered by Rockchip) init.\n"); + rtw_drv_halt(); +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0)) + //rockchip_wifi_set_carddetect(0); +#if 0 + rockchip_wifi_power(0); +#endif +#else + rk29sdk_wifi_power(0); +#endif +} +#ifdef CONFIG_WIFI_BUILD_MODULE +module_init(rockchip_wifi_init_module_rtkwifi); +module_exit(rockchip_wifi_exit_module_rtkwifi); +#else +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0)) +#ifdef CONFIG_WIFI_LOAD_DRIVER_WHEN_KERNEL_BOOTUP +late_initcall(rockchip_wifi_init_module_rtkwifi); +module_exit(rockchip_wifi_exit_module_rtkwifi); +#else +module_init(rockchip_wifi_init_module_rtkwifi); +module_exit(rockchip_wifi_exit_module_rtkwifi); +#endif +#else +#ifdef CONFIG_ANDROID_4_2 +module_init(rockchip_wifi_init_module); +module_exit(rockchip_wifi_exit_module); +#else +EXPORT_SYMBOL(rockchip_wifi_init_module); +EXPORT_SYMBOL(rockchip_wifi_exit_module); +#endif +#endif +#endif +//module_init(rtw_drv_entry); +//module_exit(rtw_drv_halt); + +#ifdef CONFIG_INTEL_PROXIM +_adapter *rtw_usb_get_sw_pointer(void) +{ + return rtw_sw_export; +} +EXPORT_SYMBOL(rtw_usb_get_sw_pointer); +#endif //CONFIG_INTEL_PROXIM + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/usb_ops_linux.c b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/usb_ops_linux.c new file mode 100644 index 000000000..1c1f56334 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/usb_ops_linux.c @@ -0,0 +1,1200 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + *******************************************************************************/ +#define _USB_OPS_LINUX_C_ + +#include +#include +#include + +struct rtw_async_write_data { + u8 data[VENDOR_CMD_MAX_DATA_LEN]; + struct usb_ctrlrequest dr; +}; + +int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u16 index, void *pdata, u16 len, u8 requesttype) +{ + _adapter *padapter = pintfhdl->padapter; + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct pwrctrl_priv *pwrctl = dvobj_to_pwrctl(pdvobjpriv); + struct usb_device *udev=pdvobjpriv->pusbdev; + + unsigned int pipe; + int status = 0; + u32 tmp_buflen=0; + u8 reqtype; + u8 *pIo_buf; + int vendorreq_times = 0; + + #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE + u8 *tmp_buf; + #else // use stack memory + u8 tmp_buf[MAX_USB_IO_CTL_SIZE]; + #endif + +#ifdef CONFIG_CONCURRENT_MODE + if(padapter->adapter_type > PRIMARY_ADAPTER) + { + padapter = padapter->pbuddy_adapter; + pdvobjpriv = adapter_to_dvobj(padapter); + udev = pdvobjpriv->pusbdev; + } +#endif + + //DBG_871X("%s %s:%d\n",__FUNCTION__, current->comm, current->pid); + + if (RTW_CANNOT_IO(padapter)){ + RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usbctrl_vendorreq:(RTW_CANNOT_IO)!!!\n")); + status = -EPERM; + goto exit; + } + + if(len>MAX_VENDOR_REQ_CMD_SIZE){ + DBG_8192C( "[%s] Buffer len error ,vendor request failed\n", __FUNCTION__ ); + status = -EINVAL; + goto exit; + } + + #ifdef CONFIG_USB_VENDOR_REQ_MUTEX + _enter_critical_mutex(&pdvobjpriv->usb_vendor_req_mutex, NULL); + #endif + + + // Acquire IO memory for vendorreq +#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC + pIo_buf = pdvobjpriv->usb_vendor_req_buf; +#else + #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE + tmp_buf = rtw_malloc( (u32) len + ALIGNMENT_UNIT); + tmp_buflen = (u32)len + ALIGNMENT_UNIT; + #else // use stack memory + tmp_buflen = MAX_USB_IO_CTL_SIZE; + #endif + + // Added by Albert 2010/02/09 + // For mstar platform, mstar suggests the address for USB IO should be 16 bytes alignment. + // Trying to fix it here. + pIo_buf = (tmp_buf==NULL)?NULL:tmp_buf + ALIGNMENT_UNIT -((SIZE_PTR)(tmp_buf) & 0x0f ); +#endif + + if ( pIo_buf== NULL) { + DBG_8192C( "[%s] pIo_buf == NULL \n", __FUNCTION__ ); + status = -ENOMEM; + goto release_mutex; + } + + while(++vendorreq_times<= MAX_USBCTRL_VENDORREQ_TIMES) + { + _rtw_memset(pIo_buf, 0, len); + + if (requesttype == 0x01) + { + pipe = usb_rcvctrlpipe(udev, 0);//read_in + reqtype = REALTEK_USB_VENQT_READ; + } + else + { + pipe = usb_sndctrlpipe(udev, 0);//write_out + reqtype = REALTEK_USB_VENQT_WRITE; + _rtw_memcpy( pIo_buf, pdata, len); + } + + status = rtw_usb_control_msg(udev, pipe, request, reqtype, value, index, pIo_buf, len, RTW_USB_CONTROL_MSG_TIMEOUT); + + if ( status == len) // Success this control transfer. + { + rtw_reset_continual_io_error(pdvobjpriv); + if ( requesttype == 0x01 ) + { // For Control read transfer, we have to copy the read data from pIo_buf to pdata. + _rtw_memcpy( pdata, pIo_buf, len ); + } + } + else { // error cases + DBG_8192C("reg 0x%x, usb %s %u fail, status:%d value=0x%x, vendorreq_times:%d\n" + , value,(requesttype == 0x01)?"read":"write" , len, status, *(u32*)pdata, vendorreq_times); + + if (status < 0) { + if(status == (-ESHUTDOWN) || status == -ENODEV ) + { + rtw_set_surprise_removed(padapter); + } else { + #ifdef DBG_CONFIG_ERROR_DETECT + { + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + pHalData->srestpriv.Wifi_Error_Status = USB_VEN_REQ_CMD_FAIL; + } + #endif + } + } + else // status != len && status >= 0 + { + if(status > 0) { + if ( requesttype == 0x01 ) + { // For Control read transfer, we have to copy the read data from pIo_buf to pdata. + _rtw_memcpy( pdata, pIo_buf, len ); + } + } + } + + if(rtw_inc_and_chk_continual_io_error(pdvobjpriv) == _TRUE ){ + rtw_set_surprise_removed(padapter); + break; + } + + } + + // firmware download is checksumed, don't retry + if( (value >= FW_START_ADDRESS ) || status == len ) + break; + + } + + // release IO memory used by vendorreq + #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE + rtw_mfree(tmp_buf, tmp_buflen); + #endif + +release_mutex: + #ifdef CONFIG_USB_VENDOR_REQ_MUTEX + _exit_critical_mutex(&pdvobjpriv->usb_vendor_req_mutex, NULL); + #endif +exit: + return status; + +} + +#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ +static void _usbctrl_vendorreq_async_callback(struct urb *urb, struct pt_regs *regs) +{ + if (urb) { + if (urb->context) { + rtw_mfree(urb->context, sizeof(struct rtw_async_write_data)); + } + usb_free_urb(urb); + } +} + +int _usbctrl_vendorreq_async_write(struct usb_device *udev, u8 request, + u16 value, u16 index, void *pdata, u16 len, u8 requesttype) +{ + int rc; + unsigned int pipe; + u8 reqtype; + struct usb_ctrlrequest *dr; + struct urb *urb; + struct rtw_async_write_data *buf; + + + if (requesttype == VENDOR_READ) { + pipe = usb_rcvctrlpipe(udev, 0);//read_in + reqtype = REALTEK_USB_VENQT_READ; + } + else { + pipe = usb_sndctrlpipe(udev, 0);//write_out + reqtype = REALTEK_USB_VENQT_WRITE; + } + + buf = (struct rtl819x_async_write_data *)rtw_zmalloc(sizeof(*buf)); + if (!buf) { + rc = -ENOMEM; + goto exit; + } + + urb = usb_alloc_urb(0, GFP_ATOMIC); + if (!urb) { + rtw_mfree((u8*)buf, sizeof(*buf)); + rc = -ENOMEM; + goto exit; + } + + dr = &buf->dr; + + dr->bRequestType = reqtype; + dr->bRequest = request; + dr->wValue = cpu_to_le16(value); + dr->wIndex = cpu_to_le16(index); + dr->wLength = cpu_to_le16(len); + + _rtw_memcpy(buf, pdata, len); + + usb_fill_control_urb(urb, udev, pipe, (unsigned char *)dr, buf, len, + _usbctrl_vendorreq_async_callback, buf); + + rc = usb_submit_urb(urb, GFP_ATOMIC); + if (rc < 0) { + rtw_mfree((u8*)buf, sizeof(*buf)); + usb_free_urb(urb); + } + +exit: + return rc; +} + + +#endif /* CONFIG_USB_SUPPORT_ASYNC_VDN_REQ */ + +unsigned int ffaddr2pipehdl(struct dvobj_priv *pdvobj, u32 addr) +{ + unsigned int pipe=0, ep_num=0; + struct usb_device *pusbd = pdvobj->pusbdev; + + if (addr == RECV_BULK_IN_ADDR) { + pipe=usb_rcvbulkpipe(pusbd, pdvobj->RtInPipe[0]); + + } else if (addr == RECV_INT_IN_ADDR) { + pipe=usb_rcvintpipe(pusbd, pdvobj->RtInPipe[1]); + + } else if (addr < HW_QUEUE_ENTRY) { + ep_num = pdvobj->Queue2Pipe[addr]; + pipe = usb_sndbulkpipe(pusbd, ep_num); + } + + return pipe; +} + +struct zero_bulkout_context{ + void *pbuf; + void *purb; + void *pirp; + void *padapter; +}; + +static void usb_bulkout_zero_complete(struct urb *purb, struct pt_regs *regs) +{ + struct zero_bulkout_context *pcontext = (struct zero_bulkout_context *)purb->context; + + //DBG_8192C("+usb_bulkout_zero_complete\n"); + + if(pcontext) + { + if(pcontext->pbuf) + { + rtw_mfree(pcontext->pbuf, sizeof(int)); + } + + if(pcontext->purb && (pcontext->purb==purb)) + { + usb_free_urb(pcontext->purb); + } + + + rtw_mfree((u8*)pcontext, sizeof(struct zero_bulkout_context)); + } + + +} + +static u32 usb_bulkout_zero(struct intf_hdl *pintfhdl, u32 addr) +{ + int pipe, status, len; + u32 ret; + unsigned char *pbuf; + struct zero_bulkout_context *pcontext; + PURB purb = NULL; + _adapter *padapter = (_adapter *)pintfhdl->padapter; + struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter); + struct pwrctrl_priv *pwrctl = dvobj_to_pwrctl(pdvobj); + struct usb_device *pusbd = pdvobj->pusbdev; + + //DBG_871X("%s\n", __func__); + + + if (RTW_CANNOT_TX(padapter)) + { + return _FAIL; + } + + + pcontext = (struct zero_bulkout_context *)rtw_zmalloc(sizeof(struct zero_bulkout_context)); + if (pcontext == NULL) { + return _FAIL; + } + + pbuf = (unsigned char *)rtw_zmalloc(sizeof(int)); + purb = usb_alloc_urb(0, GFP_ATOMIC); + + //translate DMA FIFO addr to pipehandle + pipe = ffaddr2pipehdl(pdvobj, addr); + + len = 0; + pcontext->pbuf = pbuf; + pcontext->purb = purb; + pcontext->pirp = NULL; + pcontext->padapter = padapter; + + + //translate DMA FIFO addr to pipehandle + //pipe = ffaddr2pipehdl(pdvobj, addr); + + usb_fill_bulk_urb(purb, pusbd, pipe, + pbuf, + len, + usb_bulkout_zero_complete, + pcontext);//context is pcontext + + status = usb_submit_urb(purb, GFP_ATOMIC); + + if (!status) + { + ret= _SUCCESS; + } + else + { + ret= _FAIL; + } + + + return _SUCCESS; + +} + +void usb_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) +{ + +} + +void usb_write_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem) +{ + +} + + +void usb_read_port_cancel(struct intf_hdl *pintfhdl) +{ + int i; + struct recv_buf *precvbuf; + _adapter *padapter = pintfhdl->padapter; + precvbuf = (struct recv_buf *)padapter->recvpriv.precv_buf; + + DBG_871X("%s\n", __func__); + + for (i=0; i < NR_RECVBUFF ; i++) { + + if (precvbuf->purb) { + //DBG_8192C("usb_read_port_cancel : usb_kill_urb \n"); + usb_kill_urb(precvbuf->purb); + } + precvbuf++; + } + +#ifdef CONFIG_USB_INTERRUPT_IN_PIPE + usb_kill_urb(padapter->recvpriv.int_in_urb); +#endif +} + +static void usb_write_port_complete(struct urb *purb, struct pt_regs *regs) +{ + _irqL irqL; + int i; + struct xmit_buf *pxmitbuf = (struct xmit_buf *)purb->context; + //struct xmit_frame *pxmitframe = (struct xmit_frame *)pxmitbuf->priv_data; + //_adapter *padapter = pxmitframe->padapter; + _adapter *padapter = pxmitbuf->padapter; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + //struct pkt_attrib *pattrib = &pxmitframe->attrib; + +_func_enter_; + + switch(pxmitbuf->flags) + { + case VO_QUEUE_INX: + pxmitpriv->voq_cnt--; + break; + case VI_QUEUE_INX: + pxmitpriv->viq_cnt--; + break; + case BE_QUEUE_INX: + pxmitpriv->beq_cnt--; + break; + case BK_QUEUE_INX: + pxmitpriv->bkq_cnt--; + break; + default: + break; + } + + +/* + _enter_critical(&pxmitpriv->lock, &irqL); + + pxmitpriv->txirp_cnt--; + + switch(pattrib->priority) + { + case 1: + case 2: + pxmitpriv->bkq_cnt--; + //DBG_8192C("pxmitpriv->bkq_cnt=%d\n", pxmitpriv->bkq_cnt); + break; + case 4: + case 5: + pxmitpriv->viq_cnt--; + //DBG_8192C("pxmitpriv->viq_cnt=%d\n", pxmitpriv->viq_cnt); + break; + case 6: + case 7: + pxmitpriv->voq_cnt--; + //DBG_8192C("pxmitpriv->voq_cnt=%d\n", pxmitpriv->voq_cnt); + break; + case 0: + case 3: + default: + pxmitpriv->beq_cnt--; + //DBG_8192C("pxmitpriv->beq_cnt=%d\n", pxmitpriv->beq_cnt); + break; + + } + + _exit_critical(&pxmitpriv->lock, &irqL); + + + if(pxmitpriv->txirp_cnt==0) + { + RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete: txirp_cnt== 0, set allrxreturnevt!\n")); + _rtw_up_sema(&(pxmitpriv->tx_retevt)); + } +*/ + //rtw_free_xmitframe(pxmitpriv, pxmitframe); + + if (RTW_CANNOT_TX(padapter)) + { + DBG_8192C("%s(): TX Warning! bDriverStopped(%s) OR bSurpriseRemoved(%s) pxmitbuf->buf_tag(%x)\n" + , __func__ + , rtw_is_drv_stopped(padapter)?"True":"False" + , rtw_is_surprise_removed(padapter)?"True":"False" + , pxmitbuf->buf_tag); + + goto check_completion; + } + + + if (purb->status==0) { + + } else { + RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete : purb->status(%d) != 0 \n", purb->status)); + DBG_871X("###=> urb_write_port_complete status(%d)\n",purb->status); + if((purb->status==-EPIPE)||(purb->status==-EPROTO)) + { + //usb_clear_halt(pusbdev, purb->pipe); + //msleep(10); + sreset_set_wifi_error_status(padapter, USB_WRITE_PORT_FAIL); + } else if (purb->status == -EINPROGRESS) { + RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete: EINPROGESS\n")); + goto check_completion; + + } else if (purb->status == -ENOENT) { + DBG_871X("%s: -ENOENT\n", __func__); + goto check_completion; + + } else if (purb->status == -ECONNRESET) { + DBG_871X("%s: -ECONNRESET\n", __func__); + goto check_completion; + + } else if (purb->status == -ESHUTDOWN) { + RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete: ESHUTDOWN\n")); + rtw_set_drv_stopped(padapter); + RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete:bDriverStopped=TRUE\n")); + + goto check_completion; + } + else + { + rtw_set_surprise_removed(padapter); + DBG_8192C("bSurpriseRemoved=TRUE\n"); + RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete:bSurpriseRemoved=TRUE\n")); + + goto check_completion; + } + } + + #ifdef DBG_CONFIG_ERROR_DETECT + { + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + pHalData->srestpriv.last_tx_complete_time = rtw_get_current_time(); + } + #endif + +check_completion: + _enter_critical(&pxmitpriv->lock_sctx, &irqL); + rtw_sctx_done_err(&pxmitbuf->sctx, + purb->status ? RTW_SCTX_DONE_WRITE_PORT_ERR : RTW_SCTX_DONE_SUCCESS); + _exit_critical(&pxmitpriv->lock_sctx, &irqL); + + rtw_free_xmitbuf(pxmitpriv, pxmitbuf); + + //if(rtw_txframes_pending(padapter)) + { + tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); + } + +_func_exit_; + +} + +u32 usb_write_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem) +{ + _irqL irqL; + unsigned int pipe; + int status; + u32 ret = _FAIL, bwritezero = _FALSE; + PURB purb = NULL; + _adapter *padapter = (_adapter *)pintfhdl->padapter; + struct dvobj_priv *pdvobj = adapter_to_dvobj(padapter); + struct pwrctrl_priv *pwrctl = dvobj_to_pwrctl(pdvobj); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + struct xmit_buf *pxmitbuf = (struct xmit_buf *)wmem; + struct xmit_frame *pxmitframe = (struct xmit_frame *)pxmitbuf->priv_data; + struct usb_device *pusbd = pdvobj->pusbdev; + struct pkt_attrib *pattrib = &pxmitframe->attrib; + +_func_enter_; + + RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("+usb_write_port\n")); + + if (RTW_CANNOT_TX(padapter)) { + #ifdef DBG_TX + DBG_871X(" DBG_TX %s:%d bDriverStopped%s, bSurpriseRemoved:%s\n", __func__, __LINE__ + , rtw_is_drv_stopped(padapter)?"True":"False" + , rtw_is_surprise_removed(padapter)?"True":"False"); + #endif + RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port:( padapter->bDriverStopped ||padapter->bSurpriseRemoved )!!!\n")); + rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_TX_DENY); + goto exit; + } + + _enter_critical(&pxmitpriv->lock, &irqL); + + switch(addr) + { + case VO_QUEUE_INX: + pxmitpriv->voq_cnt++; + pxmitbuf->flags = VO_QUEUE_INX; + break; + case VI_QUEUE_INX: + pxmitpriv->viq_cnt++; + pxmitbuf->flags = VI_QUEUE_INX; + break; + case BE_QUEUE_INX: + pxmitpriv->beq_cnt++; + pxmitbuf->flags = BE_QUEUE_INX; + break; + case BK_QUEUE_INX: + pxmitpriv->bkq_cnt++; + pxmitbuf->flags = BK_QUEUE_INX; + break; + case HIGH_QUEUE_INX: + pxmitbuf->flags = HIGH_QUEUE_INX; + break; + default: + pxmitbuf->flags = MGT_QUEUE_INX; + break; + } + + _exit_critical(&pxmitpriv->lock, &irqL); + + purb = pxmitbuf->pxmit_urb[0]; + + //translate DMA FIFO addr to pipehandle + pipe = ffaddr2pipehdl(pdvobj, addr); + +#ifdef CONFIG_REDUCE_USB_TX_INT + if ( (pxmitpriv->free_xmitbuf_cnt%NR_XMITBUFF == 0) + || (pxmitbuf->buf_tag > XMITBUF_DATA) ) + { + purb->transfer_flags &= (~URB_NO_INTERRUPT); + } else { + purb->transfer_flags |= URB_NO_INTERRUPT; + //DBG_8192C("URB_NO_INTERRUPT "); + } +#endif + + + usb_fill_bulk_urb(purb, pusbd, pipe, + pxmitframe->buf_addr, //= pxmitbuf->pbuf + cnt, + usb_write_port_complete, + pxmitbuf);//context is pxmitbuf + +#ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX + purb->transfer_dma = pxmitbuf->dma_transfer_addr; + purb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; + purb->transfer_flags |= URB_ZERO_PACKET; +#endif // CONFIG_USE_USB_BUFFER_ALLOC_TX + +#ifdef USB_PACKET_OFFSET_SZ +#if (USB_PACKET_OFFSET_SZ == 0) + purb->transfer_flags |= URB_ZERO_PACKET; +#endif +#endif + +#if 0 + if (bwritezero) + { + purb->transfer_flags |= URB_ZERO_PACKET; + } +#endif + + status = usb_submit_urb(purb, GFP_ATOMIC); + if (!status) { + #ifdef DBG_CONFIG_ERROR_DETECT + { + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + pHalData->srestpriv.last_tx_time = rtw_get_current_time(); + } + #endif + } else { + rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_WRITE_PORT_ERR); + DBG_871X("usb_write_port, status=%d\n", status); + RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port(): usb_submit_urb, status=%x\n", status)); + + switch (status) { + case -ENODEV: + rtw_set_drv_stopped(padapter); + break; + default: + break; + } + goto exit; + } + + ret= _SUCCESS; + +// Commented by Albert 2009/10/13 +// We add the URB_ZERO_PACKET flag to urb so that the host will send the zero packet automatically. +/* + if(bwritezero == _TRUE) + { + usb_bulkout_zero(pintfhdl, addr); + } +*/ + + RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("-usb_write_port\n")); + +exit: + if (ret != _SUCCESS) + rtw_free_xmitbuf(pxmitpriv, pxmitbuf); +_func_exit_; + return ret; + +} + +void usb_write_port_cancel(struct intf_hdl *pintfhdl) +{ + int i, j; + _adapter *padapter = pintfhdl->padapter; + struct xmit_buf *pxmitbuf = (struct xmit_buf *)padapter->xmitpriv.pxmitbuf; + + DBG_871X("%s \n", __func__); + + for (i=0; ipxmit_urb[j]) { + usb_kill_urb(pxmitbuf->pxmit_urb[j]); + } + } + pxmitbuf++; + } + + pxmitbuf = (struct xmit_buf*)padapter->xmitpriv.pxmit_extbuf; + for (i = 0; i < NR_XMIT_EXTBUFF ; i++) { + for (j=0; j<8; j++) { + if(pxmitbuf->pxmit_urb[j]) { + usb_kill_urb(pxmitbuf->pxmit_urb[j]); + } + } + pxmitbuf++; + } +} + +void usb_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf) +{ + + precvbuf->transfer_len = 0; + + precvbuf->len = 0; + + precvbuf->ref_cnt = 0; + + if(precvbuf->pbuf) + { + precvbuf->pdata = precvbuf->phead = precvbuf->ptail = precvbuf->pbuf; + precvbuf->pend = precvbuf->pdata + MAX_RECVBUF_SZ; + } + +} + +int recvbuf2recvframe(PADAPTER padapter, void *ptr); + +#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX +void usb_recv_tasklet(unsigned long priv) +{ + struct recv_buf *precvbuf = NULL; + _adapter *padapter = (_adapter*)priv; + struct recv_priv *precvpriv = &padapter->recvpriv; + + while (NULL != (precvbuf = rtw_dequeue_recvbuf(&precvpriv->recv_buf_pending_queue))) + { + if (RTW_CANNOT_RUN(padapter)) { + DBG_8192C("recv_tasklet => bDriverStopped or bSurpriseRemoved\n"); + break; + } + + + recvbuf2recvframe(padapter, precvbuf); + + rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); + } + +} + +void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) +{ + struct recv_buf *precvbuf = (struct recv_buf *)purb->context; + _adapter *padapter =(_adapter *)precvbuf->adapter; + struct recv_priv *precvpriv = &padapter->recvpriv; + + RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete!!!\n")); + + ATOMIC_DEC(&(precvpriv->rx_pending_cnt)); + + if (RTW_CANNOT_RX(padapter)) + { + DBG_8192C("%s() RX Warning! bDriverStopped(%s) OR bSurpriseRemoved(%s)\n" + , __func__ + , rtw_is_drv_stopped(padapter)?"True":"False" + , rtw_is_surprise_removed(padapter)?"True":"False"); + goto exit; + } + + if(purb->status==0)//SUCCESS + { + if ((purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)) + { + RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete: (purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)\n")); + + rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); + } + else + { + rtw_reset_continual_io_error(adapter_to_dvobj(padapter)); + + precvbuf->transfer_len = purb->actual_length; + + //rtw_enqueue_rx_transfer_buffer(precvpriv, rx_transfer_buf); + rtw_enqueue_recvbuf(precvbuf, &precvpriv->recv_buf_pending_queue); + + tasklet_schedule(&precvpriv->recv_tasklet); + } + } + else + { + RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete : purb->status(%d) != 0 \n", purb->status)); + + DBG_8192C("###=> usb_read_port_complete => urb status(%d)\n", purb->status); + + if (rtw_inc_and_chk_continual_io_error(adapter_to_dvobj(padapter)) == _TRUE) + rtw_set_surprise_removed(padapter); + + switch(purb->status) { + case -EINVAL: + case -EPIPE: + case -ENODEV: + case -ESHUTDOWN: + /*rtw_set_surprise_removed(padapter);*/ + //RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bSurpriseRemoved=TRUE\n")); + case -ENOENT: + rtw_set_drv_stopped(padapter); + RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped=TRUE\n")); + break; + case -EPROTO: + case -EILSEQ: + case -ETIME: + case -ECOMM: + case -EOVERFLOW: + #ifdef DBG_CONFIG_ERROR_DETECT + { + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + pHalData->srestpriv.Wifi_Error_Status = USB_READ_PORT_FAIL; + } + #endif + rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); + break; + case -EINPROGRESS: + DBG_8192C("ERROR: URB IS IN PROGRESS!/n"); + break; + default: + break; + } + + } + +exit: + +_func_exit_; +} + +u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) +{ + int err; + unsigned int pipe; + u32 ret = _SUCCESS; + PURB purb = NULL; + struct recv_buf *precvbuf = (struct recv_buf *)rmem; + _adapter *adapter = pintfhdl->padapter; + struct dvobj_priv *pdvobj = adapter_to_dvobj(adapter); + struct pwrctrl_priv *pwrctl = dvobj_to_pwrctl(pdvobj); + struct recv_priv *precvpriv = &adapter->recvpriv; + struct usb_device *pusbd = pdvobj->pusbdev; + +_func_enter_; + + if (RTW_CANNOT_RX(adapter) || (precvbuf == NULL)) + { + RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:( RTW_CANNOT_RX ) || precvbuf == NULL!!!\n")); + return _FAIL; + } + + usb_init_recvbuf(adapter, precvbuf); + + if(precvbuf->pbuf) + { + ATOMIC_INC(&(precvpriv->rx_pending_cnt)); + purb = precvbuf->purb; + + //translate DMA FIFO addr to pipehandle + pipe = ffaddr2pipehdl(pdvobj, addr); + + usb_fill_bulk_urb(purb, pusbd, pipe, + precvbuf->pbuf, + MAX_RECVBUF_SZ, + usb_read_port_complete, + precvbuf);//context is precvbuf + + purb->transfer_dma = precvbuf->dma_transfer_addr; + purb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; + + err = usb_submit_urb(purb, GFP_ATOMIC); + if((err) && (err != (-EPERM))) + { + RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("cannot submit rx in-token(err=0x%.8x), URB_STATUS =0x%.8x", err, purb->status)); + DBG_8192C("cannot submit rx in-token(err = 0x%08x),urb_status = %d\n",err,purb->status); + ret = _FAIL; + } + + } + +_func_exit_; + + return ret; +} +#else // CONFIG_USE_USB_BUFFER_ALLOC_RX + +void usb_recv_tasklet(unsigned long priv) +{ + _pkt *pskb; + _adapter *padapter = (_adapter*)priv; + struct recv_priv *precvpriv = &padapter->recvpriv; + struct recv_buf *precvbuf = NULL; + + while (NULL != (pskb = skb_dequeue(&precvpriv->rx_skb_queue))) { + + if (RTW_CANNOT_RUN(padapter)) { + DBG_8192C("recv_tasklet => bDriverStopped or bSurpriseRemoved\n"); + #ifdef CONFIG_PREALLOC_RX_SKB_BUFFER + if (rtw_free_skb_premem(pskb) != 0) + #endif //CONFIG_PREALLOC_RX_SKB_BUFFER + rtw_skb_free(pskb); + break; + } + + recvbuf2recvframe(padapter, pskb); + + skb_reset_tail_pointer(pskb); + pskb->len = 0; + + skb_queue_tail(&precvpriv->free_recv_skb_queue, pskb); + + if (NULL != (precvbuf = rtw_dequeue_recvbuf(&precvpriv->recv_buf_pending_queue))) { + precvbuf->pskb = NULL; + rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); + } + } +} + +void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) +{ + struct recv_buf *precvbuf = (struct recv_buf *)purb->context; + _adapter *padapter =(_adapter *)precvbuf->adapter; + struct recv_priv *precvpriv = &padapter->recvpriv; + + RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete!!!\n")); + + ATOMIC_DEC(&(precvpriv->rx_pending_cnt)); + + if(RTW_CANNOT_RX(padapter)) + { + DBG_8192C("%s() RX Warning! bDriverStopped(%s) OR bSurpriseRemoved(%s)\n" + , __func__ + , rtw_is_drv_stopped(padapter)?"True":"False" + , rtw_is_surprise_removed(padapter)?"True":"False"); + goto exit; + } + + if(purb->status==0)//SUCCESS + { + if ((purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)) + { + RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete: (purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)\n")); + rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); + DBG_8192C("%s()-%d: RX Warning!\n", __FUNCTION__, __LINE__); + } + else + { + rtw_reset_continual_io_error(adapter_to_dvobj(padapter)); + + precvbuf->transfer_len = purb->actual_length; + skb_put(precvbuf->pskb, purb->actual_length); + skb_queue_tail(&precvpriv->rx_skb_queue, precvbuf->pskb); + + #ifndef CONFIG_FIX_NR_BULKIN_BUFFER + if (skb_queue_len(&precvpriv->rx_skb_queue)<=1) + #endif + tasklet_schedule(&precvpriv->recv_tasklet); + + precvbuf->pskb = NULL; + rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); + } + } + else + { + RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete : purb->status(%d) != 0 \n", purb->status)); + + DBG_8192C("###=> usb_read_port_complete => urb status(%d)\n", purb->status); + + if (rtw_inc_and_chk_continual_io_error(adapter_to_dvobj(padapter)) == _TRUE) + rtw_set_surprise_removed(padapter); + + + switch(purb->status) { + case -EINVAL: + case -EPIPE: + case -ENODEV: + case -ESHUTDOWN: + /*rtw_set_surprise_removed(padapter);*/ + //RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bSurpriseRemoved=TRUE\n")); + case -ENOENT: + rtw_set_drv_stopped(padapter); + RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped=TRUE\n")); + break; + case -EPROTO: + case -EILSEQ: + case -ETIME: + case -ECOMM: + case -EOVERFLOW: + #ifdef DBG_CONFIG_ERROR_DETECT + { + HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + pHalData->srestpriv.Wifi_Error_Status = USB_READ_PORT_FAIL; + } + #endif + rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); + break; + case -EINPROGRESS: + DBG_8192C("ERROR: URB IS IN PROGRESS!/n"); + break; + default: + break; + } + + } + +exit: + +_func_exit_; + +} + +u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) +{ + int err; + unsigned int pipe; + u32 ret = _FAIL; + PURB purb = NULL; + struct recv_buf *precvbuf = (struct recv_buf *)rmem; + _adapter *adapter = pintfhdl->padapter; + struct dvobj_priv *pdvobj = adapter_to_dvobj(adapter); + struct pwrctrl_priv *pwrctl = dvobj_to_pwrctl(pdvobj); + struct recv_priv *precvpriv = &adapter->recvpriv; + struct usb_device *pusbd = pdvobj->pusbdev; + +_func_enter_; + + if (RTW_CANNOT_RX(adapter) || (precvbuf == NULL)) { + RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:( RTW_CANNOT_RX ) || precvbuf == NULL!!!\n")); + goto exit; + } + + usb_init_recvbuf(adapter, precvbuf); + + if (precvbuf->pskb == NULL) { + SIZE_PTR tmpaddr = 0; + SIZE_PTR alignment = 0; + + if (NULL != (precvbuf->pskb = skb_dequeue(&precvpriv->free_recv_skb_queue))) + goto recv_buf_hook; + + #ifndef CONFIG_FIX_NR_BULKIN_BUFFER + precvbuf->pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ); + #endif + + if (precvbuf->pskb == NULL) { + if (0) + DBG_871X("usb_read_port() enqueue precvbuf=%p \n", precvbuf); + /* enqueue precvbuf and wait for free skb */ + rtw_enqueue_recvbuf(precvbuf, &precvpriv->recv_buf_pending_queue); + goto exit; + } + + tmpaddr = (SIZE_PTR)precvbuf->pskb->data; + alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1); + skb_reserve(precvbuf->pskb, (RECVBUFF_ALIGN_SZ - alignment)); + } + +recv_buf_hook: + precvbuf->phead = precvbuf->pskb->head; + precvbuf->pdata = precvbuf->pskb->data; + precvbuf->ptail = skb_tail_pointer(precvbuf->pskb); + precvbuf->pend = skb_end_pointer(precvbuf->pskb); + precvbuf->pbuf = precvbuf->pskb->data; + + purb = precvbuf->purb; + + /* translate DMA FIFO addr to pipehandle */ + pipe = ffaddr2pipehdl(pdvobj, addr); + + usb_fill_bulk_urb(purb, pusbd, pipe, + precvbuf->pbuf, + MAX_RECVBUF_SZ, + usb_read_port_complete, + precvbuf); + + err = usb_submit_urb(purb, GFP_ATOMIC); + if (err && err != (-EPERM)) { + DBG_871X("cannot submit rx in-token(err = 0x%08x),urb_status = %d\n" + , err, purb->status); + goto exit; + } + + ATOMIC_INC(&(precvpriv->rx_pending_cnt)); + ret = _SUCCESS; + +exit: + +_func_exit_; + + return ret; +} +#endif // CONFIG_USE_USB_BUFFER_ALLOC_RX + +#ifdef CONFIG_USB_INTERRUPT_IN_PIPE +void usb_read_interrupt_complete(struct urb *purb, struct pt_regs *regs) +{ + int err; + _adapter *padapter = (_adapter *)purb->context; + + if (RTW_CANNOT_RX(padapter)) { + DBG_8192C("%s() RX Warning! bDriverStopped(%s) OR bSurpriseRemoved(%s)\n" + , __func__ + , rtw_is_drv_stopped(padapter)?"True":"False" + , rtw_is_surprise_removed(padapter)?"True":"False"); + + return; + } + + if (purb->status == 0) {/*SUCCESS*/ + if (purb->actual_length > INTERRUPT_MSG_FORMAT_LEN) + DBG_8192C("usb_read_interrupt_complete: purb->actual_length > INTERRUPT_MSG_FORMAT_LEN(%d)\n", INTERRUPT_MSG_FORMAT_LEN); + + rtw_hal_interrupt_handler(padapter, purb->actual_length, purb->transfer_buffer); + + err = usb_submit_urb(purb, GFP_ATOMIC); + if ((err) && (err != (-EPERM))) + DBG_8192C("cannot submit interrupt in-token(err = 0x%08x),urb_status = %d\n", err, purb->status); + } else { + DBG_8192C("###=> usb_read_interrupt_complete => urb status(%d)\n", purb->status); + + switch (purb->status) { + case -EINVAL: + case -EPIPE: + case -ENODEV: + case -ESHUTDOWN: + /*rtw_set_surprise_removed(padapter);*/ + /*RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("usb_read_port_complete:bSurpriseRemoved=TRUE\n"));*/ + case -ENOENT: + rtw_set_drv_stopped(padapter); + RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("usb_read_port_complete:bDriverStopped=TRUE\n")); + break; + case -EPROTO: + break; + case -EINPROGRESS: + DBG_8192C("ERROR: URB IS IN PROGRESS!/n"); + break; + default: + break; + } + } +} + +u32 usb_read_interrupt(struct intf_hdl *pintfhdl, u32 addr) +{ + int err; + unsigned int pipe; + u32 ret = _SUCCESS; + _adapter *adapter = pintfhdl->padapter; + struct dvobj_priv *pdvobj = adapter_to_dvobj(adapter); + struct recv_priv *precvpriv = &adapter->recvpriv; + struct usb_device *pusbd = pdvobj->pusbdev; + +_func_enter_; + + if (RTW_CANNOT_RX(adapter)) { + RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("usb_read_interrupt:( RTW_CANNOT_RX )!!!\n")); + return _FAIL; + } + + /*translate DMA FIFO addr to pipehandle*/ + pipe = ffaddr2pipehdl(pdvobj, addr); + + usb_fill_int_urb(precvpriv->int_in_urb, pusbd, pipe, + precvpriv->int_in_buf, + INTERRUPT_MSG_FORMAT_LEN, + usb_read_interrupt_complete, + adapter, + 1); + + err = usb_submit_urb(precvpriv->int_in_urb, GFP_ATOMIC); + if ((err) && (err != (-EPERM))) { + DBG_8192C("cannot submit interrupt in-token(err = 0x%08x), urb_status = %d\n", err, precvpriv->int_in_urb->status); + ret = _FAIL; + } + +_func_exit_; + return ret; +} +#endif /* CONFIG_USB_INTERRUPT_IN_PIPE */ + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/wifi_regd.c b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/wifi_regd.c new file mode 100644 index 000000000..f4c179c7d --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/wifi_regd.c @@ -0,0 +1,537 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/****************************************************************************** + * + * Copyright(c) 2009-2010 Realtek Corporation. + * + *****************************************************************************/ + +#include + +#ifdef CONFIG_IOCTL_CFG80211 + +#include + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0)) +#define ieee80211_band nl80211_band +#define IEEE80211_BAND_2GHZ NL80211_BAND_2GHZ +#define IEEE80211_BAND_5GHZ NL80211_BAND_5GHZ +#define IEEE80211_NUM_BANDS NUM_NL80211_BANDS +#endif + +static struct country_code_to_enum_rd allCountries[] = { + {COUNTRY_CODE_USER, "RD"}, +}; + +/* + * REG_RULE(freq start, freq end, bandwidth, max gain, eirp, reg_flags) + */ + +/* + *Only these channels all allow active + *scan on all world regulatory domains + */ + +/* 2G chan 01 - chan 11 */ +#define RTW_2GHZ_CH01_11 \ + REG_RULE(2412-10, 2462+10, 40, 0, 20, 0) + +/* + *We enable active scan on these a case + *by case basis by regulatory domain + */ + +/* 2G chan 12 - chan 13, PASSIV SCAN */ +#define RTW_2GHZ_CH12_13 \ + REG_RULE(2467-10, 2472+10, 40, 0, 20, \ + NL80211_RRF_PASSIVE_SCAN) + +/* 2G chan 14, PASSIVS SCAN, NO OFDM (B only) */ +#define RTW_2GHZ_CH14 \ + REG_RULE(2484-10, 2484+10, 40, 0, 20, \ + NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_OFDM) + +/* 5G chan 36 - chan 64 */ +#define RTW_5GHZ_5150_5350 \ + REG_RULE(5150-10, 5350+10, 40, 0, 30, \ + NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS) + +/* 5G chan 100 - chan 165 */ +#define RTW_5GHZ_5470_5850 \ + REG_RULE(5470-10, 5850+10, 40, 0, 30, \ + NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS) + +/* 5G chan 149 - chan 165 */ +#define RTW_5GHZ_5725_5850 \ + REG_RULE(5725-10, 5850+10, 40, 0, 30, \ + NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS) + +/* 5G chan 36 - chan 165 */ +#define RTW_5GHZ_5150_5850 \ + REG_RULE(5150-10, 5850+10, 40, 0, 30, \ + NL80211_RRF_PASSIVE_SCAN | NL80211_RRF_NO_IBSS) + +static const struct ieee80211_regdomain rtw_regdom_rd = { + .n_reg_rules = 3, + .alpha2 = "99", + .reg_rules = { + RTW_2GHZ_CH01_11, + RTW_2GHZ_CH12_13, + RTW_5GHZ_5150_5850, + } +}; + +static const struct ieee80211_regdomain rtw_regdom_11 = { + .n_reg_rules = 1, + .alpha2 = "99", + .reg_rules = { + RTW_2GHZ_CH01_11, + } +}; + +static const struct ieee80211_regdomain rtw_regdom_12_13 = { + .n_reg_rules = 2, + .alpha2 = "99", + .reg_rules = { + RTW_2GHZ_CH01_11, + RTW_2GHZ_CH12_13, + } +}; + +static const struct ieee80211_regdomain rtw_regdom_no_midband = { + .n_reg_rules = 3, + .alpha2 = "99", + .reg_rules = { + RTW_2GHZ_CH01_11, + RTW_5GHZ_5150_5350, + RTW_5GHZ_5725_5850, + } +}; + +static const struct ieee80211_regdomain rtw_regdom_60_64 = { + .n_reg_rules = 3, + .alpha2 = "99", + .reg_rules = { + RTW_2GHZ_CH01_11, + RTW_2GHZ_CH12_13, + RTW_5GHZ_5725_5850, + } +}; + +static const struct ieee80211_regdomain rtw_regdom_14_60_64 = { + .n_reg_rules = 4, + .alpha2 = "99", + .reg_rules = { + RTW_2GHZ_CH01_11, + RTW_2GHZ_CH12_13, + RTW_2GHZ_CH14, + RTW_5GHZ_5725_5850, + } +}; + +static const struct ieee80211_regdomain rtw_regdom_14 = { + .n_reg_rules = 3, + .alpha2 = "99", + .reg_rules = { + RTW_2GHZ_CH01_11, + RTW_2GHZ_CH12_13, + RTW_2GHZ_CH14, + } +}; + +#if 0 +static struct rtw_regulatory *rtw_regd; +#endif + +static bool _rtw_is_radar_freq(u16 center_freq) +{ + return (center_freq >= 5260 && center_freq <= 5700); +} + +#if 0 // not_yet +static void _rtw_reg_apply_beaconing_flags(struct wiphy *wiphy, + enum nl80211_reg_initiator initiator) +{ + enum ieee80211_band band; + struct ieee80211_supported_band *sband; + const struct ieee80211_reg_rule *reg_rule; + struct ieee80211_channel *ch; + unsigned int i; + u32 bandwidth = 0; + int r; + + for (band = 0; band < IEEE80211_NUM_BANDS; band++) { + + if (!wiphy->bands[band]) + continue; + + sband = wiphy->bands[band]; + + for (i = 0; i < sband->n_channels; i++) { + ch = &sband->channels[i]; + if (_rtw_is_radar_freq(ch->center_freq) || + (ch->flags & IEEE80211_CHAN_RADAR)) + continue; + if (initiator == NL80211_REGDOM_SET_BY_COUNTRY_IE) { + r = freq_reg_info(wiphy, ch->center_freq, + bandwidth, ®_rule); + if (r) + continue; + + /* + *If 11d had a rule for this channel ensure + *we enable adhoc/beaconing if it allows us to + *use it. Note that we would have disabled it + *by applying our static world regdomain by + *default during init, prior to calling our + *regulatory_hint(). + */ + + if (!(reg_rule->flags & NL80211_RRF_NO_IBSS)) + ch->flags &= ~IEEE80211_CHAN_NO_IBSS; + if (! + (reg_rule->flags & + NL80211_RRF_PASSIVE_SCAN)) + ch->flags &= + ~IEEE80211_CHAN_PASSIVE_SCAN; + } else { + if (ch->beacon_found) + ch->flags &= ~(IEEE80211_CHAN_NO_IBSS | + IEEE80211_CHAN_PASSIVE_SCAN); + } + } + } +} + +/* Allows active scan scan on Ch 12 and 13 */ +static void _rtw_reg_apply_active_scan_flags(struct wiphy *wiphy, + enum nl80211_reg_initiator + initiator) +{ + struct ieee80211_supported_band *sband; + struct ieee80211_channel *ch; + const struct ieee80211_reg_rule *reg_rule; + u32 bandwidth = 0; + int r; + + if (!wiphy->bands[IEEE80211_BAND_2GHZ]) + return; + sband = wiphy->bands[IEEE80211_BAND_2GHZ]; + + /* + * If no country IE has been received always enable active scan + * on these channels. This is only done for specific regulatory SKUs + */ + if (initiator != NL80211_REGDOM_SET_BY_COUNTRY_IE) { + ch = &sband->channels[11]; /* CH 12 */ + if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN) + ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN; + ch = &sband->channels[12]; /* CH 13 */ + if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN) + ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN; + return; + } + + /* + * If a country IE has been received check its rule for this + * channel first before enabling active scan. The passive scan + * would have been enforced by the initial processing of our + * custom regulatory domain. + */ + + ch = &sband->channels[11]; /* CH 12 */ + r = freq_reg_info(wiphy, ch->center_freq, bandwidth, ®_rule); + if (!r) { + if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN)) + if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN) + ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN; + } + + ch = &sband->channels[12]; /* CH 13 */ + r = freq_reg_info(wiphy, ch->center_freq, bandwidth, ®_rule); + if (!r) { + if (!(reg_rule->flags & NL80211_RRF_PASSIVE_SCAN)) + if (ch->flags & IEEE80211_CHAN_PASSIVE_SCAN) + ch->flags &= ~IEEE80211_CHAN_PASSIVE_SCAN; + } +} +#endif + +/* + * Always apply Radar/DFS rules on + * freq range 5260 MHz - 5700 MHz + */ +static void _rtw_reg_apply_radar_flags(struct wiphy *wiphy) +{ + struct ieee80211_supported_band *sband; + struct ieee80211_channel *ch; + unsigned int i; + + if (!wiphy->bands[IEEE80211_BAND_5GHZ]) + return; + + sband = wiphy->bands[IEEE80211_BAND_5GHZ]; + + for (i = 0; i < sband->n_channels; i++) { + ch = &sband->channels[i]; + if (!_rtw_is_radar_freq(ch->center_freq)) + continue; +#ifdef CONFIG_DFS + #if defined(CONFIG_DFS_MASTER) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 14, 0)) + if (!(ch->flags & IEEE80211_CHAN_DISABLED)) { + ch->flags |= IEEE80211_CHAN_RADAR; + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0)) + ch->flags |= (IEEE80211_CHAN_NO_IBSS|IEEE80211_CHAN_PASSIVE_SCAN); + #else + ch->flags |= IEEE80211_CHAN_NO_IR; + #endif + } + #endif +#endif //CONFIG_DFS + +#if 0 + /* + * We always enable radar detection/DFS on this + * frequency range. Additionally we also apply on + * this frequency range: + * - If STA mode does not yet have DFS supports disable + * active scanning + * - If adhoc mode does not support DFS yet then disable + * adhoc in the frequency. + * - If AP mode does not yet support radar detection/DFS + * do not allow AP mode + */ + if (!(ch->flags & IEEE80211_CHAN_DISABLED)) + ch->flags |= IEEE80211_CHAN_RADAR | + IEEE80211_CHAN_NO_IBSS | + IEEE80211_CHAN_PASSIVE_SCAN; +#endif + } +} + +static void _rtw_reg_apply_flags(struct wiphy *wiphy) +{ +#if 1 // by channel plan + _adapter *padapter = wiphy_to_adapter(wiphy); + u8 channel_plan = padapter->mlmepriv.ChannelPlan; + struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; + RT_CHANNEL_INFO *channel_set = pmlmeext->channel_set; + u8 max_chan_nums = pmlmeext->max_chan_nums; + + struct ieee80211_supported_band *sband; + struct ieee80211_channel *ch; + unsigned int i, j; + u16 channel; + u32 freq; + + // all channels disable + for (i = 0; i < IEEE80211_NUM_BANDS; i++) { + sband = wiphy->bands[i]; + + if (sband) { + for (j = 0; j < sband->n_channels; j++) { + ch = &sband->channels[j]; + + if (ch) + ch->flags = IEEE80211_CHAN_DISABLED; + } + } + } + + // channels apply by channel plans. + for (i = 0; i < max_chan_nums; i++) { + channel = channel_set[i].ChannelNum; + freq = rtw_ch2freq(channel); + + ch = ieee80211_get_channel(wiphy, freq); + if (ch) { + if (channel_set[i].ScanType == SCAN_PASSIVE) { + #if defined(CONFIG_DFS_MASTER) && (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) + ch->flags = 0; + #elif (LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)) + ch->flags = (IEEE80211_CHAN_NO_IBSS|IEEE80211_CHAN_PASSIVE_SCAN); + #else + ch->flags = IEEE80211_CHAN_NO_IR; + #endif + } + else { + ch->flags = 0; + } + } + } + +#else + struct ieee80211_supported_band *sband; + struct ieee80211_channel *ch; + unsigned int i, j; + u16 channels[37] = + { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 36, 40, 44, 48, 52, 56, + 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, + 149, 153, + 157, 161, 165 + }; + u16 channel; + u32 freq; + + for (i = 0; i < IEEE80211_NUM_BANDS; i++) { + sband = wiphy->bands[i]; + + if (sband) + for (j = 0; j < sband->n_channels; j++) { + ch = &sband->channels[j]; + + if (ch) + ch->flags = IEEE80211_CHAN_DISABLED; + } + } + + for (i = 0; i < 37; i++) { + channel = channels[i]; + freq = rtw_ch2freq(channel); + + ch = ieee80211_get_channel(wiphy, freq); + if (ch) { + if (channel <= 11) + ch->flags = 0; + else + ch->flags = 0; //IEEE80211_CHAN_PASSIVE_SCAN; + } + //printk("%s: freq %d(%d) flag 0x%02X \n", __func__, freq, channel, ch->flags); + } +#endif +} + +static void _rtw_reg_apply_world_flags(struct wiphy *wiphy, + enum nl80211_reg_initiator initiator, + struct rtw_regulatory *reg) +{ + //_rtw_reg_apply_beaconing_flags(wiphy, initiator); + //_rtw_reg_apply_active_scan_flags(wiphy, initiator); + return; +} + +static int _rtw_reg_notifier_apply(struct wiphy *wiphy, + struct regulatory_request *request, + struct rtw_regulatory *reg) +{ + + /* Hard code flags */ + _rtw_reg_apply_flags(wiphy); + + /* We always apply this */ + _rtw_reg_apply_radar_flags(wiphy); + + switch (request->initiator) { + case NL80211_REGDOM_SET_BY_DRIVER: + DBG_8192C("%s: %s\n", __func__, "NL80211_REGDOM_SET_BY_DRIVER"); + _rtw_reg_apply_world_flags(wiphy, NL80211_REGDOM_SET_BY_DRIVER, + reg); + break; + case NL80211_REGDOM_SET_BY_CORE: + DBG_8192C("%s: %s\n", __func__, + "NL80211_REGDOM_SET_BY_CORE to DRV"); + _rtw_reg_apply_world_flags(wiphy, NL80211_REGDOM_SET_BY_DRIVER, + reg); + break; + case NL80211_REGDOM_SET_BY_USER: + DBG_8192C("%s: %s\n", __func__, + "NL80211_REGDOM_SET_BY_USER to DRV"); + _rtw_reg_apply_world_flags(wiphy, NL80211_REGDOM_SET_BY_DRIVER, + reg); + break; + case NL80211_REGDOM_SET_BY_COUNTRY_IE: + DBG_8192C("%s: %s\n", __func__, + "NL80211_REGDOM_SET_BY_COUNTRY_IE"); + _rtw_reg_apply_world_flags(wiphy, request->initiator, reg); + break; + } + + return 0; +} + +static const struct ieee80211_regdomain *_rtw_regdomain_select(struct + rtw_regulatory + *reg) +{ +#if 0 + switch (reg->country_code) { + case COUNTRY_CODE_USER: + default: + return &rtw_regdom_rd; + } +#else + return &rtw_regdom_rd; +#endif +} + +void _rtw_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) +{ + struct rtw_regulatory *reg = NULL; + + DBG_8192C("%s\n", __func__); + + _rtw_reg_notifier_apply(wiphy, request, reg); +} + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,9,0)) +int rtw_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) +#else +void rtw_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) +#endif +{ + _rtw_reg_notifier(wiphy, request); + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,9,0)) + return 0; + #endif +} + +void rtw_reg_notify_by_driver(struct wiphy *wiphy) +{ + if (wiphy) { + struct regulatory_request request; + request.initiator = NL80211_REGDOM_SET_BY_DRIVER; + rtw_reg_notifier(wiphy, &request); + } +} + +static void _rtw_regd_init_wiphy(struct rtw_regulatory *reg, struct wiphy *wiphy) +{ + const struct ieee80211_regdomain *regd; + + wiphy->reg_notifier = rtw_reg_notifier; + + #if (LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0)) + wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY; + wiphy->flags &= ~WIPHY_FLAG_STRICT_REGULATORY; + wiphy->flags &= ~WIPHY_FLAG_DISABLE_BEACON_HINTS; + #else + wiphy->regulatory_flags |= REGULATORY_CUSTOM_REG; + wiphy->regulatory_flags &= ~REGULATORY_STRICT_REG; + wiphy->regulatory_flags &= ~REGULATORY_DISABLE_BEACON_HINTS; + #endif + + regd = _rtw_regdomain_select(reg); + wiphy_apply_custom_regulatory(wiphy, regd); + + /* Hard code flags */ + _rtw_reg_apply_flags(wiphy); + _rtw_reg_apply_radar_flags(wiphy); + _rtw_reg_apply_world_flags(wiphy, NL80211_REGDOM_SET_BY_DRIVER, reg); +} + +static struct country_code_to_enum_rd *_rtw_regd_find_country(u16 countrycode) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(allCountries); i++) { + if (allCountries[i].countrycode == countrycode) + return &allCountries[i]; + } + return NULL; +} + +void rtw_regd_init(struct wiphy *wiphy) +{ + _rtw_regd_init_wiphy(NULL, wiphy); +} +#endif //CONFIG_IOCTL_CFG80211 + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/xmit_linux.c b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/xmit_linux.c new file mode 100644 index 000000000..129269948 --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/linux/xmit_linux.c @@ -0,0 +1,546 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ +#define _XMIT_OSDEP_C_ + +#include + +#define DBG_DUMP_OS_QUEUE_CTL 0 + +uint rtw_remainder_len(struct pkt_file *pfile) +{ + return (pfile->buf_len - ((SIZE_PTR)(pfile->cur_addr) - (SIZE_PTR)(pfile->buf_start))); +} + +void _rtw_open_pktfile (_pkt *pktptr, struct pkt_file *pfile) +{ +_func_enter_; + + pfile->pkt = pktptr; + pfile->cur_addr = pfile->buf_start = pktptr->data; + pfile->pkt_len = pfile->buf_len = pktptr->len; + + pfile->cur_buffer = pfile->buf_start ; + +_func_exit_; +} + +uint _rtw_pktfile_read (struct pkt_file *pfile, u8 *rmem, uint rlen) +{ + uint len = 0; + +_func_enter_; + + len = rtw_remainder_len(pfile); + len = (rlen > len)? len: rlen; + + if(rmem) + skb_copy_bits(pfile->pkt, pfile->buf_len-pfile->pkt_len, rmem, len); + + pfile->cur_addr += len; + pfile->pkt_len -= len; + +_func_exit_; + + return len; +} + +sint rtw_endofpktfile(struct pkt_file *pfile) +{ +_func_enter_; + + if (pfile->pkt_len == 0) { +_func_exit_; + return _TRUE; + } + +_func_exit_; + + return _FALSE; +} + +void rtw_set_tx_chksum_offload(_pkt *pkt, struct pkt_attrib *pattrib) +{ + +#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX + struct sk_buff *skb = (struct sk_buff *)pkt; + pattrib->hw_tcp_csum = 0; + + if (skb->ip_summed == CHECKSUM_PARTIAL) { + if (skb_shinfo(skb)->nr_frags == 0) + { + const struct iphdr *ip = ip_hdr(skb); + if (ip->protocol == IPPROTO_TCP) { + // TCP checksum offload by HW + DBG_871X("CHECKSUM_PARTIAL TCP\n"); + pattrib->hw_tcp_csum = 1; + //skb_checksum_help(skb); + } else if (ip->protocol == IPPROTO_UDP) { + //DBG_871X("CHECKSUM_PARTIAL UDP\n"); +#if 1 + skb_checksum_help(skb); +#else + // Set UDP checksum = 0 to skip checksum check + struct udphdr *udp = skb_transport_header(skb); + udp->check = 0; +#endif + } else { + DBG_871X("%s-%d TCP CSUM offload Error!!\n", __FUNCTION__, __LINE__); + WARN_ON(1); /* we need a WARN() */ + } + } + else { // IP fragmentation case + DBG_871X("%s-%d nr_frags != 0, using skb_checksum_help(skb);!!\n", __FUNCTION__, __LINE__); + skb_checksum_help(skb); + } + } +#endif + +} + +int rtw_os_xmit_resource_alloc(_adapter *padapter, struct xmit_buf *pxmitbuf, u32 alloc_sz, u8 flag) +{ + if (alloc_sz > 0) { +#ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct usb_device *pusbd = pdvobjpriv->pusbdev; + + pxmitbuf->pallocated_buf = rtw_usb_buffer_alloc(pusbd, (size_t)alloc_sz, &pxmitbuf->dma_transfer_addr); + pxmitbuf->pbuf = pxmitbuf->pallocated_buf; + if(pxmitbuf->pallocated_buf == NULL) + return _FAIL; +#else // CONFIG_USE_USB_BUFFER_ALLOC_TX + + pxmitbuf->pallocated_buf = rtw_zmalloc(alloc_sz); + if (pxmitbuf->pallocated_buf == NULL) + { + return _FAIL; + } + + pxmitbuf->pbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitbuf->pallocated_buf), XMITBUF_ALIGN_SZ); + +#endif // CONFIG_USE_USB_BUFFER_ALLOC_TX + } + + if (flag) { +#ifdef CONFIG_USB_HCI + int i; + for(i=0; i<8; i++) + { + pxmitbuf->pxmit_urb[i] = usb_alloc_urb(0, GFP_KERNEL); + if(pxmitbuf->pxmit_urb[i] == NULL) + { + DBG_871X("pxmitbuf->pxmit_urb[i]==NULL"); + return _FAIL; + } + } +#endif + } + + return _SUCCESS; +} + +void rtw_os_xmit_resource_free(_adapter *padapter, struct xmit_buf *pxmitbuf,u32 free_sz, u8 flag) +{ + if (flag) { +#ifdef CONFIG_USB_HCI + int i; + + for(i=0; i<8; i++) + { + if(pxmitbuf->pxmit_urb[i]) + { + //usb_kill_urb(pxmitbuf->pxmit_urb[i]); + usb_free_urb(pxmitbuf->pxmit_urb[i]); + } + } +#endif + } + + if (free_sz > 0 ) { +#ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX + struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); + struct usb_device *pusbd = pdvobjpriv->pusbdev; + + rtw_usb_buffer_free(pusbd, (size_t)free_sz, pxmitbuf->pallocated_buf, pxmitbuf->dma_transfer_addr); + pxmitbuf->pallocated_buf = NULL; + pxmitbuf->dma_transfer_addr = 0; +#else // CONFIG_USE_USB_BUFFER_ALLOC_TX + if(pxmitbuf->pallocated_buf) + rtw_mfree(pxmitbuf->pallocated_buf, free_sz); +#endif // CONFIG_USE_USB_BUFFER_ALLOC_TX + } +} + +void dump_os_queue(void *sel, _adapter *padapter) +{ + struct net_device *ndev = padapter->pnetdev; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) + int i; + + for (i=0;i<4;i++) { + DBG_871X_SEL_NL(sel, "os_queue[%d]:%s\n" + , i, __netif_subqueue_stopped(ndev, i)?"stopped":"waked"); + } +#else + DBG_871X_SEL_NL(sel, "os_queue:%s\n" + , netif_queue_stopped(ndev)?"stopped":"waked"); +#endif +} + +#define WMM_XMIT_THRESHOLD (NR_XMITFRAME*2/5) + +inline static bool rtw_os_need_wake_queue(_adapter *padapter, u16 qidx) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + + if (padapter->registrypriv.wifi_spec) { + if (pxmitpriv->hwxmits[qidx].accnt < WMM_XMIT_THRESHOLD) + return _TRUE; + } else { + return _TRUE; + } + return _FALSE; +#else + return _TRUE; +#endif +} + +inline static bool rtw_os_need_stop_queue(_adapter *padapter, u16 qidx) +{ + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) + if (padapter->registrypriv.wifi_spec) { + /* No free space for Tx, tx_worker is too slow */ + if (pxmitpriv->hwxmits[qidx].accnt > WMM_XMIT_THRESHOLD) + return _TRUE; + } else { + if(pxmitpriv->free_xmitframe_cnt<=4) + return _TRUE; + } +#else + if(pxmitpriv->free_xmitframe_cnt<=4) + return _TRUE; +#endif + return _FALSE; +} + +void rtw_os_pkt_complete(_adapter *padapter, _pkt *pkt) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) + u16 qidx; + + qidx = skb_get_queue_mapping(pkt); + if (rtw_os_need_wake_queue(padapter, qidx)) { + if (DBG_DUMP_OS_QUEUE_CTL) + DBG_871X(FUNC_ADPT_FMT": netif_wake_subqueue[%d]\n", FUNC_ADPT_ARG(padapter), qidx); + netif_wake_subqueue(padapter->pnetdev, qidx); + } +#else + if (rtw_os_need_wake_queue(padapter, 0)) { + if (DBG_DUMP_OS_QUEUE_CTL) + DBG_871X(FUNC_ADPT_FMT": netif_wake_queue\n", FUNC_ADPT_ARG(padapter)); + netif_wake_queue(padapter->pnetdev); + } +#endif + + rtw_skb_free(pkt); +} + +void rtw_os_xmit_complete(_adapter *padapter, struct xmit_frame *pxframe) +{ + if(pxframe->pkt) + rtw_os_pkt_complete(padapter, pxframe->pkt); + + pxframe->pkt = NULL; +} + +void rtw_os_xmit_schedule(_adapter *padapter) +{ + _adapter *pri_adapter = padapter; + +#if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI) + if(!padapter) + return; + +#ifdef CONFIG_CONCURRENT_MODE + if(padapter->adapter_type > PRIMARY_ADAPTER) + pri_adapter = padapter->pbuddy_adapter; +#endif + + if (_rtw_queue_empty(&padapter->xmitpriv.pending_xmitbuf_queue) == _FALSE) + _rtw_up_sema(&pri_adapter->xmitpriv.xmit_sema); + + +#else + _irqL irqL; + struct xmit_priv *pxmitpriv; + + if(!padapter) + return; + + pxmitpriv = &padapter->xmitpriv; + + _enter_critical_bh(&pxmitpriv->lock, &irqL); + + if(rtw_txframes_pending(padapter)) + { + tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); + } + + _exit_critical_bh(&pxmitpriv->lock, &irqL); +#endif +} + +static bool rtw_check_xmit_resource(_adapter *padapter, _pkt *pkt) +{ + bool busy = _FALSE; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; +#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) + u16 qidx; + + qidx = skb_get_queue_mapping(pkt); + if (rtw_os_need_stop_queue(padapter, qidx)) { + if (DBG_DUMP_OS_QUEUE_CTL) + DBG_871X(FUNC_ADPT_FMT": netif_stop_subqueue[%d]\n", FUNC_ADPT_ARG(padapter), qidx); + netif_stop_subqueue(padapter->pnetdev, qidx); + busy = _TRUE; + } +#else + if (rtw_os_need_stop_queue(padapter, 0)) { + if (DBG_DUMP_OS_QUEUE_CTL) + DBG_871X(FUNC_ADPT_FMT": netif_stop_queue\n", FUNC_ADPT_ARG(padapter)); + rtw_netif_stop_queue(padapter->pnetdev); + busy = _TRUE; + } +#endif + return busy; +} + +void rtw_os_wake_queue_at_free_stainfo(_adapter *padapter, int *qcnt_freed) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) + int i; + + for (i=0;i<4;i++) { + if (qcnt_freed[i] == 0) + continue; + + if(rtw_os_need_wake_queue(padapter, i)) { + if (DBG_DUMP_OS_QUEUE_CTL) + DBG_871X(FUNC_ADPT_FMT": netif_wake_subqueue[%d]\n", FUNC_ADPT_ARG(padapter), i); + netif_wake_subqueue(padapter->pnetdev, i); + } + } +#else + if (qcnt_freed[0] || qcnt_freed[1] || qcnt_freed[2] || qcnt_freed[3]) { + if(rtw_os_need_wake_queue(padapter, 0)) { + if (DBG_DUMP_OS_QUEUE_CTL) + DBG_871X(FUNC_ADPT_FMT": netif_wake_queue\n", FUNC_ADPT_ARG(padapter)); + netif_wake_queue(padapter->pnetdev); + } + } +#endif +} + +#ifdef CONFIG_TX_MCAST2UNI +int rtw_mlcst2unicst(_adapter *padapter, struct sk_buff *skb) +{ + struct sta_priv *pstapriv = &padapter->stapriv; + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; + _irqL irqL; + _list *phead, *plist; + struct sk_buff *newskb; + struct sta_info *psta = NULL; + u8 chk_alive_num = 0; + char chk_alive_list[NUM_STA]; + u8 bc_addr[6]={0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + u8 null_addr[6]={0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + + int i; + s32 res; + + DBG_COUNTER(padapter->tx_logs.os_tx_m2u); + + _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); + phead = &pstapriv->asoc_list; + plist = get_next(phead); + + //free sta asoc_queue + while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) { + int stainfo_offset; + psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); + plist = get_next(plist); + + stainfo_offset = rtw_stainfo_offset(pstapriv, psta); + if (stainfo_offset_valid(stainfo_offset)) { + chk_alive_list[chk_alive_num++] = stainfo_offset; + } + } + _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); + + for (i = 0; i < chk_alive_num; i++) { + psta = rtw_get_stainfo_by_offset(pstapriv, chk_alive_list[i]); + if(!(psta->state &_FW_LINKED)) + { + DBG_COUNTER(padapter->tx_logs.os_tx_m2u_ignore_fw_linked); + continue; + } + + /* avoid come from STA1 and send back STA1 */ + if (_rtw_memcmp(psta->hwaddr, &skb->data[6], 6) == _TRUE + || _rtw_memcmp(psta->hwaddr, null_addr, 6) == _TRUE + || _rtw_memcmp(psta->hwaddr, bc_addr, 6) == _TRUE + ) + { + DBG_COUNTER(padapter->tx_logs.os_tx_m2u_ignore_self); + continue; + } + + DBG_COUNTER(padapter->tx_logs.os_tx_m2u_entry); + + newskb = rtw_skb_copy(skb); + + if (newskb) { + _rtw_memcpy(newskb->data, psta->hwaddr, 6); + res = rtw_xmit(padapter, &newskb); + if (res < 0) { + DBG_COUNTER(padapter->tx_logs.os_tx_m2u_entry_err_xmit); + DBG_871X("%s()-%d: rtw_xmit() return error! res=%d\n", __FUNCTION__, __LINE__, res); + pxmitpriv->tx_drop++; + rtw_skb_free(newskb); + } + } else { + DBG_COUNTER(padapter->tx_logs.os_tx_m2u_entry_err_skb); + DBG_871X("%s-%d: rtw_skb_copy() failed!\n", __FUNCTION__, __LINE__); + pxmitpriv->tx_drop++; + //rtw_skb_free(skb); + return _FALSE; // Caller shall tx this multicast frame via normal way. + } + } + + rtw_skb_free(skb); + return _TRUE; +} +#endif // CONFIG_TX_MCAST2UNI + + +int _rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); + struct xmit_priv *pxmitpriv = &padapter->xmitpriv; +#ifdef CONFIG_TX_MCAST2UNI + struct mlme_priv *pmlmepriv = &padapter->mlmepriv; + extern int rtw_mc2u_disable; +#endif // CONFIG_TX_MCAST2UNI + s32 res = 0; +#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) + u16 queue; +#endif + +_func_enter_; + + if(padapter->registrypriv.mp_mode) + { + DBG_871X("MP_TX_DROP_OS_FRAME\n"); + goto drop_packet; + } + DBG_COUNTER(padapter->tx_logs.os_tx); + RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("+xmit_enry\n")); + + if (rtw_if_up(padapter) == _FALSE) { + DBG_COUNTER(padapter->tx_logs.os_tx_err_up); + RT_TRACE(_module_xmit_osdep_c_, _drv_err_, ("rtw_xmit_entry: rtw_if_up fail\n")); + #ifdef DBG_TX_DROP_FRAME + DBG_871X("DBG_TX_DROP_FRAME %s if_up fail\n", __FUNCTION__); + #endif + goto drop_packet; + } + + rtw_check_xmit_resource(padapter, pkt); + +#ifdef CONFIG_TX_MCAST2UNI + if ( !rtw_mc2u_disable + && check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE + && ( IP_MCAST_MAC(pkt->data) + || ICMPV6_MCAST_MAC(pkt->data) + #ifdef CONFIG_TX_BCAST2UNI + || is_broadcast_mac_addr(pkt->data) + #endif + ) + && (padapter->registrypriv.wifi_spec == 0) + ) + { + if ( pxmitpriv->free_xmitframe_cnt > (NR_XMITFRAME/4) ) { + res = rtw_mlcst2unicst(padapter, pkt); + if (res == _TRUE) { + goto exit; + } + } else { + //DBG_871X("Stop M2U(%d, %d)! ", pxmitpriv->free_xmitframe_cnt, pxmitpriv->free_xmitbuf_cnt); + //DBG_871X("!m2u ); + DBG_COUNTER(padapter->tx_logs.os_tx_m2u_stop); + } + } +#endif // CONFIG_TX_MCAST2UNI + + res = rtw_xmit(padapter, &pkt); + if (res < 0) { + #ifdef DBG_TX_DROP_FRAME + DBG_871X("DBG_TX_DROP_FRAME %s rtw_xmit fail\n", __FUNCTION__); + #endif + goto drop_packet; + } + + RT_TRACE(_module_xmit_osdep_c_, _drv_info_, ("rtw_xmit_entry: tx_pkts=%d\n", (u32)pxmitpriv->tx_pkts)); + goto exit; + +drop_packet: + pxmitpriv->tx_drop++; + rtw_os_pkt_complete(padapter, pkt); + RT_TRACE(_module_xmit_osdep_c_, _drv_notice_, ("rtw_xmit_entry: drop, tx_drop=%d\n", (u32)pxmitpriv->tx_drop)); + +exit: + +_func_exit_; + + return 0; +} + +int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev) +{ + _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); + struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); + int ret = 0; + + if (pkt) { + if (check_fwstate(pmlmepriv, WIFI_MONITOR_STATE) == _TRUE) { + rtw_monitor_xmit_entry((struct sk_buff *)pkt, pnetdev); + } else { + rtw_mstat_update(MSTAT_TYPE_SKB, MSTAT_ALLOC_SUCCESS, pkt->truesize); + ret = _rtw_xmit_entry(pkt, pnetdev); + } + + } + + return ret; +} + diff --git a/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/osdep_service.c b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/osdep_service.c new file mode 100644 index 000000000..70360520a --- /dev/null +++ b/src/little/linux/drivers/net/wireless/rtl8188fu/os_dep/osdep_service.c @@ -0,0 +1,2549 @@ +/****************************************************************************** + * + * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of version 2 of the GNU General Public License as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA + * + * + ******************************************************************************/ + + +#define _OSDEP_SERVICE_C_ + +#include + +#define RT_TAG '1178' + +#ifdef DBG_MEMORY_LEAK +#ifdef PLATFORM_LINUX +atomic_t _malloc_cnt = ATOMIC_INIT(0); +atomic_t _malloc_size = ATOMIC_INIT(0); +#endif +#endif /* DBG_MEMORY_LEAK */ + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0) +#define __vfs_read vfs_read +#endif + + +#if defined(PLATFORM_LINUX) +/* +* Translate the OS dependent @param error_code to OS independent RTW_STATUS_CODE +* @return: one of RTW_STATUS_CODE +*/ +inline int RTW_STATUS_CODE(int error_code){ + if(error_code >=0) + return _SUCCESS; + + switch(error_code) { + //case -ETIMEDOUT: + // return RTW_STATUS_TIMEDOUT; + default: + return _FAIL; + } +} +#else +inline int RTW_STATUS_CODE(int error_code){ + return error_code; +} +#endif + +u32 rtw_atoi(u8* s) +{ + + int num=0,flag=0; + int i; + for(i=0;i<=strlen(s);i++) + { + if(s[i] >= '0' && s[i] <= '9') + num = num * 10 + s[i] -'0'; + else if(s[0] == '-' && i==0) + flag =1; + else + break; + } + + if(flag == 1) + num = num * -1; + + return(num); + +} + +inline u8* _rtw_vmalloc(u32 sz) +{ + u8 *pbuf; +#ifdef PLATFORM_LINUX + pbuf = vmalloc(sz); +#endif +#ifdef PLATFORM_FREEBSD + pbuf = malloc(sz,M_DEVBUF,M_NOWAIT); +#endif + +#ifdef PLATFORM_WINDOWS + NdisAllocateMemoryWithTag(&pbuf,sz, RT_TAG); +#endif + +#ifdef DBG_MEMORY_LEAK +#ifdef PLATFORM_LINUX + if ( pbuf != NULL) { + atomic_inc(&_malloc_cnt); + atomic_add(sz, &_malloc_size); + } +#endif +#endif /* DBG_MEMORY_LEAK */ + + return pbuf; +} + +inline u8* _rtw_zvmalloc(u32 sz) +{ + u8 *pbuf; +#ifdef PLATFORM_LINUX + pbuf = _rtw_vmalloc(sz); + if (pbuf != NULL) + memset(pbuf, 0, sz); +#endif +#ifdef PLATFORM_FREEBSD + pbuf = malloc(sz,M_DEVBUF,M_ZERO|M_NOWAIT); +#endif +#ifdef PLATFORM_WINDOWS + NdisAllocateMemoryWithTag(&pbuf,sz, RT_TAG); + if (pbuf != NULL) + NdisFillMemory(pbuf, sz, 0); +#endif + + return pbuf; +} + +inline void _rtw_vmfree(u8 *pbuf, u32 sz) +{ +#ifdef PLATFORM_LINUX + vfree(pbuf); +#endif +#ifdef PLATFORM_FREEBSD + free(pbuf,M_DEVBUF); +#endif +#ifdef PLATFORM_WINDOWS + NdisFreeMemory(pbuf,sz, 0); +#endif + +#ifdef DBG_MEMORY_LEAK +#ifdef PLATFORM_LINUX + atomic_dec(&_malloc_cnt); + atomic_sub(sz, &_malloc_size); +#endif +#endif /* DBG_MEMORY_LEAK */ +} + +u8* _rtw_malloc(u32 sz) +{ + + u8 *pbuf=NULL; + +#ifdef PLATFORM_LINUX +#ifdef RTK_DMP_PLATFORM + if(sz > 0x4000) + pbuf = (u8 *)dvr_malloc(sz); + else +#endif + pbuf = kmalloc(sz,in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); + +#endif +#ifdef PLATFORM_FREEBSD + pbuf = malloc(sz,M_DEVBUF,M_NOWAIT); +#endif +#ifdef PLATFORM_WINDOWS + + NdisAllocateMemoryWithTag(&pbuf,sz, RT_TAG); + +#endif + +#ifdef DBG_MEMORY_LEAK +#ifdef PLATFORM_LINUX + if ( pbuf != NULL) { + atomic_inc(&_malloc_cnt); + atomic_add(sz, &_malloc_size); + } +#endif +#endif /* DBG_MEMORY_LEAK */ + + return pbuf; + +} + + +u8* _rtw_zmalloc(u32 sz) +{ +#ifdef PLATFORM_FREEBSD + return malloc(sz,M_DEVBUF,M_ZERO|M_NOWAIT); +#else // PLATFORM_FREEBSD + u8 *pbuf = _rtw_malloc(sz); + + if (pbuf != NULL) { + +#ifdef PLATFORM_LINUX + memset(pbuf, 0, sz); +#endif + +#ifdef PLATFORM_WINDOWS + NdisFillMemory(pbuf, sz, 0); +#endif + + } + + return pbuf; +#endif // PLATFORM_FREEBSD +} + +void _rtw_mfree(u8 *pbuf, u32 sz) +{ + +#ifdef PLATFORM_LINUX +#ifdef RTK_DMP_PLATFORM + if(sz > 0x4000) + dvr_free(pbuf); + else +#endif + kfree(pbuf); + +#endif +#ifdef PLATFORM_FREEBSD + free(pbuf,M_DEVBUF); +#endif +#ifdef PLATFORM_WINDOWS + + NdisFreeMemory(pbuf,sz, 0); + +#endif + +#ifdef DBG_MEMORY_LEAK +#ifdef PLATFORM_LINUX + atomic_dec(&_malloc_cnt); + atomic_sub(sz, &_malloc_size); +#endif +#endif /* DBG_MEMORY_LEAK */ + +} + +#ifdef PLATFORM_FREEBSD +//review again +struct sk_buff * dev_alloc_skb(unsigned int size) +{ + struct sk_buff *skb=NULL; + u8 *data=NULL; + + //skb = (struct sk_buff *)_rtw_zmalloc(sizeof(struct sk_buff)); // for skb->len, etc. + skb = (struct sk_buff *)_rtw_malloc(sizeof(struct sk_buff)); + if(!skb) + goto out; + data = _rtw_malloc(size); + if(!data) + goto nodata; + + skb->head = (unsigned char*)data; + skb->data = (unsigned char*)data; + skb->tail = (unsigned char*)data; + skb->end = (unsigned char*)data + size; + skb->len = 0; + //printf("%s()-%d: skb=%p, skb->head = %p\n", __FUNCTION__, __LINE__, skb, skb->head); + +out: + return skb; +nodata: + _rtw_mfree((u8 *)skb, sizeof(struct sk_buff)); + skb = NULL; +goto out; + +} + +void dev_kfree_skb_any(struct sk_buff *skb) +{ + //printf("%s()-%d: skb->head = %p\n", __FUNCTION__, __LINE__, skb->head); + if(skb->head) + _rtw_mfree(skb->head, 0); + //printf("%s()-%d: skb = %p\n", __FUNCTION__, __LINE__, skb); + if(skb) + _rtw_mfree((u8 *)skb, 0); +} +struct sk_buff *skb_clone(const struct sk_buff *skb) +{ + return NULL; +} + +#endif /* PLATFORM_FREEBSD */ + +inline struct sk_buff *_rtw_skb_alloc(u32 sz) +{ +#ifdef PLATFORM_LINUX + return __dev_alloc_skb(sz, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); +#endif /* PLATFORM_LINUX */ + +#ifdef PLATFORM_FREEBSD + return dev_alloc_skb(sz); +#endif /* PLATFORM_FREEBSD */ +} + +inline void _rtw_skb_free(struct sk_buff *skb) +{ + dev_kfree_skb_any(skb); +} + +inline struct sk_buff *_rtw_skb_copy(const struct sk_buff *skb) +{ +#ifdef PLATFORM_LINUX + return skb_copy(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); +#endif /* PLATFORM_LINUX */ + +#ifdef PLATFORM_FREEBSD + return NULL; +#endif /* PLATFORM_FREEBSD */ +} + +inline struct sk_buff *_rtw_skb_clone(struct sk_buff *skb) +{ +#ifdef PLATFORM_LINUX + return skb_clone(skb, in_interrupt() ? GFP_ATOMIC : GFP_KERNEL); +#endif /* PLATFORM_LINUX */ + +#ifdef PLATFORM_FREEBSD + return skb_clone(skb); +#endif /* PLATFORM_FREEBSD */ +} + +inline int _rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb) +{ +#ifdef PLATFORM_LINUX + skb->dev = ndev; + return netif_rx(skb); +#endif /* PLATFORM_LINUX */ + +#ifdef PLATFORM_FREEBSD + return (*ndev->if_input)(ndev, skb); +#endif /* PLATFORM_FREEBSD */ +} + +void _rtw_skb_queue_purge(struct sk_buff_head *list) +{ + struct sk_buff *skb; + + while ((skb = skb_dequeue(list)) != NULL) + _rtw_skb_free(skb); +} + +#ifdef CONFIG_USB_HCI +inline void *_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma) +{ +#ifdef PLATFORM_LINUX +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) + return usb_alloc_coherent(dev, size, (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), dma); +#else + return usb_buffer_alloc(dev, size, (in_interrupt() ? GFP_ATOMIC : GFP_KERNEL), dma); +#endif +#endif /* PLATFORM_LINUX */ + +#ifdef PLATFORM_FREEBSD + return (malloc(size, M_USBDEV, M_NOWAIT | M_ZERO)); +#endif /* PLATFORM_FREEBSD */ +} +inline void _rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma) +{ +#ifdef PLATFORM_LINUX +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) + usb_free_coherent(dev, size, addr, dma); +#else + usb_buffer_free(dev, size, addr, dma); +#endif +#endif /* PLATFORM_LINUX */ + +#ifdef PLATFORM_FREEBSD + free(addr, M_USBDEV); +#endif /* PLATFORM_FREEBSD */ +} +#endif /* CONFIG_USB_HCI */ + +#if defined(DBG_MEM_ALLOC) + +struct rtw_mem_stat { + ATOMIC_T alloc; // the memory bytes we allocate currently + ATOMIC_T peak; // the peak memory bytes we allocate + ATOMIC_T alloc_cnt; // the alloc count for alloc currently + ATOMIC_T alloc_err_cnt; // the error times we fail to allocate memory +}; + +struct rtw_mem_stat rtw_mem_type_stat[mstat_tf_idx(MSTAT_TYPE_MAX)]; +#ifdef RTW_MEM_FUNC_STAT +struct rtw_mem_stat rtw_mem_func_stat[mstat_ff_idx(MSTAT_FUNC_MAX)]; +#endif + +char *MSTAT_TYPE_str[] = { + "VIR", + "PHY", + "SKB", + "USB", +}; + +#ifdef RTW_MEM_FUNC_STAT +char *MSTAT_FUNC_str[] = { + "UNSP", + "IO", + "TXIO", + "RXIO", + "TX", + "RX", +}; +#endif + +void rtw_mstat_dump(void *sel) +{ + int i; + int value_t[4][mstat_tf_idx(MSTAT_TYPE_MAX)]; +#ifdef RTW_MEM_FUNC_STAT + int value_f[4][mstat_ff_idx(MSTAT_FUNC_MAX)]; +#endif + + int vir_alloc, vir_peak, vir_alloc_err, phy_alloc, phy_peak, phy_alloc_err; + int tx_alloc, tx_peak, tx_alloc_err, rx_alloc, rx_peak, rx_alloc_err; + + for(i=0;i 5000) { + // rtw_mstat_dump(RTW_DBGDUMP); + update_time=rtw_get_current_time(); + //} +} + +#ifndef SIZE_MAX + #define SIZE_MAX (~(size_t)0) +#endif + +struct mstat_sniff_rule { + enum mstat_f flags; + size_t lb; + size_t hb; +}; + +struct mstat_sniff_rule mstat_sniff_rules[] = { + {MSTAT_TYPE_PHY, 4097, SIZE_MAX}, +}; + +int mstat_sniff_rule_num = sizeof(mstat_sniff_rules)/sizeof(struct mstat_sniff_rule); + +bool match_mstat_sniff_rules(const enum mstat_f flags, const size_t size) +{ + int i; + for (i = 0; i= size) + return _TRUE; + } + + return _FALSE; +} + +inline u8* dbg_rtw_vmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line) +{ + u8 *p; + + if (match_mstat_sniff_rules(flags, sz)) + DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz)); + + p=_rtw_vmalloc((sz)); + + rtw_mstat_update( + flags + , p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL + , sz + ); + + return p; +} + +inline u8* dbg_rtw_zvmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line) +{ + u8 *p; + + if (match_mstat_sniff_rules(flags, sz)) + DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz)); + + p=_rtw_zvmalloc((sz)); + + rtw_mstat_update( + flags + , p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL + , sz + ); + + return p; +} + +inline void dbg_rtw_vmfree(u8 *pbuf, u32 sz, const enum mstat_f flags, const char *func, const int line) +{ + + if (match_mstat_sniff_rules(flags, sz)) + DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz)); + + _rtw_vmfree((pbuf), (sz)); + + rtw_mstat_update( + flags + , MSTAT_FREE + , sz + ); +} + +inline u8* dbg_rtw_malloc(u32 sz, const enum mstat_f flags, const char *func, const int line) +{ + u8 *p; + + if (match_mstat_sniff_rules(flags, sz)) + DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz)); + + p=_rtw_malloc((sz)); + + rtw_mstat_update( + flags + , p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL + , sz + ); + + return p; +} + +inline u8* dbg_rtw_zmalloc(u32 sz, const enum mstat_f flags, const char *func, const int line) +{ + u8 *p; + + if (match_mstat_sniff_rules(flags, sz)) + DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz)); + + p = _rtw_zmalloc((sz)); + + rtw_mstat_update( + flags + , p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL + , sz + ); + + return p; +} + +inline void dbg_rtw_mfree(u8 *pbuf, u32 sz, const enum mstat_f flags, const char *func, const int line) +{ + if (match_mstat_sniff_rules(flags, sz)) + DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz)); + + _rtw_mfree((pbuf), (sz)); + + rtw_mstat_update( + flags + , MSTAT_FREE + , sz + ); +} + +inline struct sk_buff * dbg_rtw_skb_alloc(unsigned int size, const enum mstat_f flags, const char *func, int line) +{ + struct sk_buff *skb; + unsigned int truesize = 0; + + skb = _rtw_skb_alloc(size); + + if(skb) + truesize = skb->truesize; + + if(!skb || truesize < size || match_mstat_sniff_rules(flags, truesize)) + DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d), skb:%p, truesize=%u\n", func, line, __FUNCTION__, size, skb, truesize); + + rtw_mstat_update( + flags + , skb ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL + , truesize + ); + + return skb; +} + +inline void dbg_rtw_skb_free(struct sk_buff *skb, const enum mstat_f flags, const char *func, int line) +{ + unsigned int truesize = skb->truesize; + + if(match_mstat_sniff_rules(flags, truesize)) + DBG_871X("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize); + + _rtw_skb_free(skb); + + rtw_mstat_update( + flags + , MSTAT_FREE + , truesize + ); +} + +inline struct sk_buff *dbg_rtw_skb_copy(const struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line) +{ + struct sk_buff *skb_cp; + unsigned int truesize = skb->truesize; + unsigned int cp_truesize = 0; + + skb_cp = _rtw_skb_copy(skb); + if(skb_cp) + cp_truesize = skb_cp->truesize; + + if(!skb_cp || cp_truesize < truesize || match_mstat_sniff_rules(flags, cp_truesize)) + DBG_871X("DBG_MEM_ALLOC %s:%d %s(%u), skb_cp:%p, cp_truesize=%u\n", func, line, __FUNCTION__, truesize, skb_cp, cp_truesize); + + rtw_mstat_update( + flags + , skb_cp ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL + , truesize + ); + + return skb_cp; +} + +inline struct sk_buff *dbg_rtw_skb_clone(struct sk_buff *skb, const enum mstat_f flags, const char *func, const int line) +{ + struct sk_buff *skb_cl; + unsigned int truesize = skb->truesize; + unsigned int cl_truesize = 0; + + skb_cl = _rtw_skb_clone(skb); + if(skb_cl) + cl_truesize = skb_cl->truesize; + + if(!skb_cl || cl_truesize < truesize || match_mstat_sniff_rules(flags, cl_truesize)) + DBG_871X("DBG_MEM_ALLOC %s:%d %s(%u), skb_cl:%p, cl_truesize=%u\n", func, line, __FUNCTION__, truesize, skb_cl, cl_truesize); + + rtw_mstat_update( + flags + , skb_cl ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL + , truesize + ); + + return skb_cl; +} + +inline int dbg_rtw_netif_rx(_nic_hdl ndev, struct sk_buff *skb, const enum mstat_f flags, const char *func, int line) +{ + int ret; + unsigned int truesize = skb->truesize; + + if(match_mstat_sniff_rules(flags, truesize)) + DBG_871X("DBG_MEM_ALLOC %s:%d %s, truesize=%u\n", func, line, __FUNCTION__, truesize); + + ret = _rtw_netif_rx(ndev, skb); + + rtw_mstat_update( + flags + , MSTAT_FREE + , truesize + ); + + return ret; +} + +inline void dbg_rtw_skb_queue_purge(struct sk_buff_head *list, enum mstat_f flags, const char *func, int line) +{ + struct sk_buff *skb; + + while ((skb = skb_dequeue(list)) != NULL) + dbg_rtw_skb_free(skb, flags, func, line); +} + +#ifdef CONFIG_USB_HCI +inline void *dbg_rtw_usb_buffer_alloc(struct usb_device *dev, size_t size, dma_addr_t *dma, const enum mstat_f flags, const char *func, int line) +{ + void *p; + + if(match_mstat_sniff_rules(flags, size)) + DBG_871X("DBG_MEM_ALLOC %s:%d %s(%zu)\n", func, line, __FUNCTION__, size); + + p = _rtw_usb_buffer_alloc(dev, size, dma); + + rtw_mstat_update( + flags + , p ? MSTAT_ALLOC_SUCCESS : MSTAT_ALLOC_FAIL + , size + ); + + return p; +} + +inline void dbg_rtw_usb_buffer_free(struct usb_device *dev, size_t size, void *addr, dma_addr_t dma, const enum mstat_f flags, const char *func, int line) +{ + + if(match_mstat_sniff_rules(flags, size)) + DBG_871X("DBG_MEM_ALLOC %s:%d %s(%zu)\n", func, line, __FUNCTION__, size); + + _rtw_usb_buffer_free(dev, size, addr, dma); + + rtw_mstat_update( + flags + , MSTAT_FREE + , size + ); +} +#endif /* CONFIG_USB_HCI */ + +#endif /* defined(DBG_MEM_ALLOC) */ + +void* rtw_malloc2d(int h, int w, size_t size) +{ + int j; + + void **a = (void **) rtw_zmalloc( h*sizeof(void *) + h*w*size ); + if(a == NULL) + { + DBG_871X("%s: alloc memory fail!\n", __FUNCTION__); + return NULL; + } + + for( j=0; jprev = pnew; + pnew->next = pnext; + pnew->prev = pprev; + pprev->next = pnew; +} +#endif /* PLATFORM_FREEBSD */ + + +void _rtw_init_listhead(_list *list) +{ + +#ifdef PLATFORM_LINUX + + INIT_LIST_HEAD(list); + +#endif + +#ifdef PLATFORM_FREEBSD + list->next = list; + list->prev = list; +#endif +#ifdef PLATFORM_WINDOWS + + NdisInitializeListHead(list); + +#endif + +} + + +/* +For the following list_xxx operations, +caller must guarantee the atomic context. +Otherwise, there will be racing condition. +*/ +u32 rtw_is_list_empty(_list *phead) +{ + +#ifdef PLATFORM_LINUX + + if (list_empty(phead)) + return _TRUE; + else + return _FALSE; + +#endif +#ifdef PLATFORM_FREEBSD + + if (phead->next == phead) + return _TRUE; + else + return _FALSE; + +#endif + + +#ifdef PLATFORM_WINDOWS + + if (IsListEmpty(phead)) + return _TRUE; + else + return _FALSE; + +#endif + + +} + +void rtw_list_insert_head(_list *plist, _list *phead) +{ + +#ifdef PLATFORM_LINUX + list_add(plist, phead); +#endif + +#ifdef PLATFORM_FREEBSD + __list_add(plist, phead, phead->next); +#endif + +#ifdef PLATFORM_WINDOWS + InsertHeadList(phead, plist); +#endif +} + +void rtw_list_insert_tail(_list *plist, _list *phead) +{ + +#ifdef PLATFORM_LINUX + + list_add_tail(plist, phead); + +#endif +#ifdef PLATFORM_FREEBSD + + __list_add(plist, phead->prev, phead); + +#endif +#ifdef PLATFORM_WINDOWS + + InsertTailList(phead, plist); + +#endif + +} + +void rtw_init_timer(_timer *ptimer, void *padapter, void *pfunc) +{ + _adapter *adapter = (_adapter *)padapter; + +#ifdef PLATFORM_LINUX + _init_timer(ptimer, adapter->pnetdev, pfunc, adapter); +#endif +#ifdef PLATFORM_FREEBSD + _init_timer(ptimer, adapter->pifp, pfunc, adapter->mlmepriv.nic_hdl); +#endif +#ifdef PLATFORM_WINDOWS + _init_timer(ptimer, adapter->hndis_adapter, pfunc, adapter->mlmepriv.nic_hdl); +#endif +} + +/* + +Caller must check if the list is empty before calling rtw_list_delete + +*/ + + +void _rtw_init_sema(_sema *sema, int init_val) +{ + +#ifdef PLATFORM_LINUX + + sema_init(sema, init_val); + +#endif +#ifdef PLATFORM_FREEBSD + sema_init(sema, init_val, "rtw_drv"); +#endif +#ifdef PLATFORM_OS_XP + + KeInitializeSemaphore(sema, init_val, SEMA_UPBND); // count=0; + +#endif + +#ifdef PLATFORM_OS_CE + if(*sema == NULL) + *sema = CreateSemaphore(NULL, init_val, SEMA_UPBND, NULL); +#endif + +} + +void _rtw_free_sema(_sema *sema) +{ +#ifdef PLATFORM_FREEBSD + sema_destroy(sema); +#endif +#ifdef PLATFORM_OS_CE + CloseHandle(*sema); +#endif + +} + +void _rtw_up_sema(_sema *sema) +{ + +#ifdef PLATFORM_LINUX + + up(sema); + +#endif +#ifdef PLATFORM_FREEBSD + sema_post(sema); +#endif +#ifdef PLATFORM_OS_XP + + KeReleaseSemaphore(sema, IO_NETWORK_INCREMENT, 1, FALSE ); + +#endif + +#ifdef PLATFORM_OS_CE + ReleaseSemaphore(*sema, 1, NULL ); +#endif +} + +u32 _rtw_down_sema(_sema *sema) +{ + +#ifdef PLATFORM_LINUX + + if (down_interruptible(sema)) + return _FAIL; + else + return _SUCCESS; + +#endif +#ifdef PLATFORM_FREEBSD + sema_wait(sema); + return _SUCCESS; +#endif +#ifdef PLATFORM_OS_XP + + if(STATUS_SUCCESS == KeWaitForSingleObject(sema, Executive, KernelMode, TRUE, NULL)) + return _SUCCESS; + else + return _FAIL; +#endif + +#ifdef PLATFORM_OS_CE + if(WAIT_OBJECT_0 == WaitForSingleObject(*sema, INFINITE )) + return _SUCCESS; + else + return _FAIL; +#endif +} + + + +void _rtw_mutex_init(_mutex *pmutex) +{ +#ifdef PLATFORM_LINUX + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) + mutex_init(pmutex); +#else + init_MUTEX(pmutex); +#endif + +#endif +#ifdef PLATFORM_FREEBSD + mtx_init(pmutex, "", NULL, MTX_DEF|MTX_RECURSE); +#endif +#ifdef PLATFORM_OS_XP + + KeInitializeMutex(pmutex, 0); + +#endif + +#ifdef PLATFORM_OS_CE + *pmutex = CreateMutex( NULL, _FALSE, NULL); +#endif +} + +void _rtw_mutex_free(_mutex *pmutex); +void _rtw_mutex_free(_mutex *pmutex) +{ +#ifdef PLATFORM_LINUX + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) + mutex_destroy(pmutex); +#else +#endif + +#ifdef PLATFORM_FREEBSD + sema_destroy(pmutex); +#endif + +#endif + +#ifdef PLATFORM_OS_XP + +#endif + +#ifdef PLATFORM_OS_CE + +#endif +} + +void _rtw_spinlock_init(_lock *plock) +{ + +#ifdef PLATFORM_LINUX + + spin_lock_init(plock); + +#endif +#ifdef PLATFORM_FREEBSD + mtx_init(plock, "", NULL, MTX_DEF|MTX_RECURSE); +#endif +#ifdef PLATFORM_WINDOWS + + NdisAllocateSpinLock(plock); + +#endif + +} + +void _rtw_spinlock_free(_lock *plock) +{ +#ifdef PLATFORM_FREEBSD + mtx_destroy(plock); +#endif + +#ifdef PLATFORM_WINDOWS + + NdisFreeSpinLock(plock); + +#endif + +} +#ifdef PLATFORM_FREEBSD +extern PADAPTER prtw_lock; + +void rtw_mtx_lock(_lock *plock){ + if(prtw_lock){ + mtx_lock(&prtw_lock->glock); + } + else{ + printf("%s prtw_lock==NULL",__FUNCTION__); + } +} +void rtw_mtx_unlock(_lock *plock){ + if(prtw_lock){ + mtx_unlock(&prtw_lock->glock); + } + else{ + printf("%s prtw_lock==NULL",__FUNCTION__); + } + +} +#endif //PLATFORM_FREEBSD + + +void _rtw_spinlock(_lock *plock) +{ + +#ifdef PLATFORM_LINUX + + spin_lock(plock); + +#endif +#ifdef PLATFORM_FREEBSD + mtx_lock(plock); +#endif +#ifdef PLATFORM_WINDOWS + + NdisAcquireSpinLock(plock); + +#endif + +} + +void _rtw_spinunlock(_lock *plock) +{ + +#ifdef PLATFORM_LINUX + + spin_unlock(plock); + +#endif +#ifdef PLATFORM_FREEBSD + mtx_unlock(plock); +#endif +#ifdef PLATFORM_WINDOWS + + NdisReleaseSpinLock(plock); + +#endif +} + + +void _rtw_spinlock_ex(_lock *plock) +{ + +#ifdef PLATFORM_LINUX + + spin_lock(plock); + +#endif +#ifdef PLATFORM_FREEBSD + mtx_lock(plock); +#endif +#ifdef PLATFORM_WINDOWS + + NdisDprAcquireSpinLock(plock); + +#endif + +} + +void _rtw_spinunlock_ex(_lock *plock) +{ + +#ifdef PLATFORM_LINUX + + spin_unlock(plock); + +#endif +#ifdef PLATFORM_FREEBSD + mtx_unlock(plock); +#endif +#ifdef PLATFORM_WINDOWS + + NdisDprReleaseSpinLock(plock); + +#endif +} + + + +void _rtw_init_queue(_queue *pqueue) +{ + _rtw_init_listhead(&(pqueue->queue)); + _rtw_spinlock_init(&(pqueue->lock)); +} + +void _rtw_deinit_queue(_queue *pqueue) +{ + _rtw_spinlock_free(&(pqueue->lock)); +} + +u32 _rtw_queue_empty(_queue *pqueue) +{ + return (rtw_is_list_empty(&(pqueue->queue))); +} + + +u32 rtw_end_of_queue_search(_list *head, _list *plist) +{ + if (head == plist) + return _TRUE; + else + return _FALSE; +} + + +u32 rtw_get_current_time(void) +{ + +#ifdef PLATFORM_LINUX + return jiffies; +#endif +#ifdef PLATFORM_FREEBSD + struct timeval tvp; + getmicrotime(&tvp); + return tvp.tv_sec; +#endif +#ifdef PLATFORM_WINDOWS + LARGE_INTEGER SystemTime; + NdisGetCurrentSystemTime(&SystemTime); + return (u32)(SystemTime.LowPart);// count of 100-nanosecond intervals +#endif +} + +inline u32 rtw_systime_to_ms(u32 systime) +{ +#ifdef PLATFORM_LINUX + return systime * 1000 / HZ; +#endif +#ifdef PLATFORM_FREEBSD + return systime * 1000; +#endif +#ifdef PLATFORM_WINDOWS + return systime / 10000 ; +#endif +} + +inline u32 rtw_ms_to_systime(u32 ms) +{ +#ifdef PLATFORM_LINUX + return ms * HZ / 1000; +#endif +#ifdef PLATFORM_FREEBSD + return ms /1000; +#endif +#ifdef PLATFORM_WINDOWS + return ms * 10000 ; +#endif +} + +// the input parameter start use the same unit as returned by rtw_get_current_time +inline s32 rtw_get_passing_time_ms(u32 start) +{ +#ifdef PLATFORM_LINUX + return rtw_systime_to_ms(jiffies-start); +#endif +#ifdef PLATFORM_FREEBSD + return rtw_systime_to_ms(rtw_get_current_time()); +#endif +#ifdef PLATFORM_WINDOWS + LARGE_INTEGER SystemTime; + NdisGetCurrentSystemTime(&SystemTime); + return rtw_systime_to_ms((u32)(SystemTime.LowPart) - start) ; +#endif +} + +inline s32 rtw_get_time_interval_ms(u32 start, u32 end) +{ +#ifdef PLATFORM_LINUX + return rtw_systime_to_ms(end-start); +#endif +#ifdef PLATFORM_FREEBSD + return rtw_systime_to_ms(rtw_get_current_time()); +#endif +#ifdef PLATFORM_WINDOWS + return rtw_systime_to_ms(end-start); +#endif +} + + +void rtw_sleep_schedulable(int ms) +{ + +#ifdef PLATFORM_LINUX + + u32 delta; + + delta = (ms * HZ)/1000;//(ms) + if (delta == 0) { + delta = 1;// 1 ms + } + set_current_state(TASK_INTERRUPTIBLE); + if (schedule_timeout(delta) != 0) { + return ; + } + return; + +#endif +#ifdef PLATFORM_FREEBSD + DELAY(ms*1000); + return ; +#endif + +#ifdef PLATFORM_WINDOWS + + NdisMSleep(ms*1000); //(us)*1000=(ms) + +#endif + +} + + +void rtw_msleep_os(int ms) +{ + +#ifdef PLATFORM_LINUX + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) + if (ms < 20) { + unsigned long us = ms * 1000UL; + usleep_range(us, us + 1000UL); + } else + #endif + msleep((unsigned int)ms); + +#endif +#ifdef PLATFORM_FREEBSD + //Delay for delay microseconds + DELAY(ms*1000); + return ; +#endif +#ifdef PLATFORM_WINDOWS + + NdisMSleep(ms*1000); //(us)*1000=(ms) + +#endif + + +} +void rtw_usleep_os(int us) +{ +#ifdef PLATFORM_LINUX + + // msleep((unsigned int)us); + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)) + usleep_range(us, us + 1); + #else + if ( 1 < (us/1000) ) + msleep(1); + else + msleep( (us/1000) + 1); + #endif +#endif + +#ifdef PLATFORM_FREEBSD + //Delay for delay microseconds + DELAY(us); + + return ; +#endif +#ifdef PLATFORM_WINDOWS + + NdisMSleep(us); //(us) + +#endif + + +} + + +#ifdef DBG_DELAY_OS +void _rtw_mdelay_os(int ms, const char *func, const int line) +{ + #if 0 + if(ms>10) + DBG_871X("%s:%d %s(%d)\n", func, line, __FUNCTION__, ms); + rtw_msleep_os(ms); + return; + #endif + + + DBG_871X("%s:%d %s(%d)\n", func, line, __FUNCTION__, ms); + +#if defined(PLATFORM_LINUX) + + mdelay((unsigned long)ms); + +#elif defined(PLATFORM_WINDOWS) + + NdisStallExecution(ms*1000); //(us)*1000=(ms) + +#endif + + +} +void _rtw_udelay_os(int us, const char *func, const int line) +{ + + #if 0 + if(us > 1000) { + DBG_871X("%s:%d %s(%d)\n", func, line, __FUNCTION__, us); + rtw_usleep_os(us); + return; + } + #endif + + + DBG_871X("%s:%d %s(%d)\n", func, line, __FUNCTION__, us); + + +#if defined(PLATFORM_LINUX) + + udelay((unsigned long)us); + +#elif defined(PLATFORM_WINDOWS) + + NdisStallExecution(us); //(us) + +#endif + +} +#else +void rtw_mdelay_os(int ms) +{ + +#ifdef PLATFORM_LINUX + + mdelay((unsigned long)ms); + +#endif +#ifdef PLATFORM_FREEBSD + DELAY(ms*1000); + return ; +#endif +#ifdef PLATFORM_WINDOWS + + NdisStallExecution(ms*1000); //(us)*1000=(ms) + +#endif + + +} +void rtw_udelay_os(int us) +{ + +#ifdef PLATFORM_LINUX + + udelay((unsigned long)us); + +#endif +#ifdef PLATFORM_FREEBSD + //Delay for delay microseconds + DELAY(us); + return ; +#endif +#ifdef PLATFORM_WINDOWS + + NdisStallExecution(us); //(us) + +#endif + +} +#endif + +void rtw_yield_os(void) +{ +#ifdef PLATFORM_LINUX + yield(); +#endif +#ifdef PLATFORM_FREEBSD + yield(); +#endif +#ifdef PLATFORM_WINDOWS + SwitchToThread(); +#endif +} + +#define RTW_SUSPEND_LOCK_NAME "rtw_wifi" +#define RTW_SUSPEND_EXT_LOCK_NAME "rtw_wifi_ext" +#define RTW_SUSPEND_RX_LOCK_NAME "rtw_wifi_rx" +#define RTW_SUSPEND_TRAFFIC_LOCK_NAME "rtw_wifi_traffic" +#define RTW_SUSPEND_RESUME_LOCK_NAME "rtw_wifi_resume" +#define RTW_RESUME_SCAN_LOCK_NAME "rtw_wifi_scan" +#ifdef CONFIG_WAKELOCK +static struct wake_lock rtw_suspend_lock; +static struct wake_lock rtw_suspend_ext_lock; +static struct wake_lock rtw_suspend_rx_lock; +static struct wake_lock rtw_suspend_traffic_lock; +static struct wake_lock rtw_suspend_resume_lock; +static struct wake_lock rtw_resume_scan_lock; +#elif defined(CONFIG_ANDROID_POWER) +static android_suspend_lock_t rtw_suspend_lock ={ + .name = RTW_SUSPEND_LOCK_NAME +}; +static android_suspend_lock_t rtw_suspend_ext_lock ={ + .name = RTW_SUSPEND_EXT_LOCK_NAME +}; +static android_suspend_lock_t rtw_suspend_rx_lock ={ + .name = RTW_SUSPEND_RX_LOCK_NAME +}; +static android_suspend_lock_t rtw_suspend_traffic_lock ={ + .name = RTW_SUSPEND_TRAFFIC_LOCK_NAME +}; +static android_suspend_lock_t rtw_suspend_resume_lock ={ + .name = RTW_SUSPEND_RESUME_LOCK_NAME +}; +static android_suspend_lock_t rtw_resume_scan_lock ={ + .name = RTW_RESUME_SCAN_LOCK_NAME +}; +#endif + +inline void rtw_suspend_lock_init(void) +{ + #ifdef CONFIG_WAKELOCK + wake_lock_init(&rtw_suspend_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_LOCK_NAME); + wake_lock_init(&rtw_suspend_ext_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_EXT_LOCK_NAME); + wake_lock_init(&rtw_suspend_rx_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_RX_LOCK_NAME); + wake_lock_init(&rtw_suspend_traffic_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_TRAFFIC_LOCK_NAME); + wake_lock_init(&rtw_suspend_resume_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_RESUME_LOCK_NAME); + wake_lock_init(&rtw_resume_scan_lock, WAKE_LOCK_SUSPEND, RTW_RESUME_SCAN_LOCK_NAME); + #elif defined(CONFIG_ANDROID_POWER) + android_init_suspend_lock(&rtw_suspend_lock); + android_init_suspend_lock(&rtw_suspend_ext_lock); + android_init_suspend_lock(&rtw_suspend_rx_lock); + android_init_suspend_lock(&rtw_suspend_traffic_lock); + android_init_suspend_lock(&rtw_suspend_resume_lock); + android_init_suspend_lock(&rtw_resume_scan_lock); + #endif +} + +inline void rtw_suspend_lock_uninit(void) +{ + #ifdef CONFIG_WAKELOCK + wake_lock_destroy(&rtw_suspend_lock); + wake_lock_destroy(&rtw_suspend_ext_lock); + wake_lock_destroy(&rtw_suspend_rx_lock); + wake_lock_destroy(&rtw_suspend_traffic_lock); + wake_lock_destroy(&rtw_suspend_resume_lock); + wake_lock_destroy(&rtw_resume_scan_lock); + #elif defined(CONFIG_ANDROID_POWER) + android_uninit_suspend_lock(&rtw_suspend_lock); + android_uninit_suspend_lock(&rtw_suspend_ext_lock); + android_uninit_suspend_lock(&rtw_suspend_rx_lock); + android_uninit_suspend_lock(&rtw_suspend_traffic_lock); + android_uninit_suspend_lock(&rtw_suspend_resume_lock); + android_uninit_suspend_lock(&rtw_resume_scan_lock); + #endif +} + +inline void rtw_lock_suspend(void) +{ + #ifdef CONFIG_WAKELOCK + wake_lock(&rtw_suspend_lock); + #elif defined(CONFIG_ANDROID_POWER) + android_lock_suspend(&rtw_suspend_lock); + #endif + + #if defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER) + //DBG_871X("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); + #endif +} + +inline void rtw_unlock_suspend(void) +{ + #ifdef CONFIG_WAKELOCK + wake_unlock(&rtw_suspend_lock); + #elif defined(CONFIG_ANDROID_POWER) + android_unlock_suspend(&rtw_suspend_lock); + #endif + + #if defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER) + //DBG_871X("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); + #endif +} + +inline void rtw_resume_lock_suspend(void) +{ + #ifdef CONFIG_WAKELOCK + wake_lock(&rtw_suspend_resume_lock); + #elif defined(CONFIG_ANDROID_POWER) + android_lock_suspend(&rtw_suspend_resume_lock); + #endif + + #if defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER) + //DBG_871X("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); + #endif +} + +inline void rtw_resume_unlock_suspend(void) +{ + #ifdef CONFIG_WAKELOCK + wake_unlock(&rtw_suspend_resume_lock); + #elif defined(CONFIG_ANDROID_POWER) + android_unlock_suspend(&rtw_suspend_resume_lock); + #endif + + #if defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER) + //DBG_871X("####%s: suspend_lock_count:%d####\n", __FUNCTION__, rtw_suspend_lock.stat.count); + #endif +} + +inline void rtw_lock_suspend_timeout(u32 timeout_ms) +{ + #ifdef CONFIG_WAKELOCK + wake_lock_timeout(&rtw_suspend_lock, rtw_ms_to_systime(timeout_ms)); + #elif defined(CONFIG_ANDROID_POWER) + android_lock_suspend_auto_expire(&rtw_suspend_lock, rtw_ms_to_systime(timeout_ms)); + #endif +} + +inline void rtw_lock_ext_suspend_timeout(u32 timeout_ms) +{ + #ifdef CONFIG_WAKELOCK + wake_lock_timeout(&rtw_suspend_ext_lock, rtw_ms_to_systime(timeout_ms)); + #elif defined(CONFIG_ANDROID_POWER) + android_lock_suspend_auto_expire(&rtw_suspend_ext_lock, rtw_ms_to_systime(timeout_ms)); + #endif + //DBG_871X("EXT lock timeout:%d\n", timeout_ms); +} + +inline void rtw_lock_rx_suspend_timeout(u32 timeout_ms) +{ + #ifdef CONFIG_WAKELOCK + wake_lock_timeout(&rtw_suspend_rx_lock, rtw_ms_to_systime(timeout_ms)); + #elif defined(CONFIG_ANDROID_POWER) + android_lock_suspend_auto_expire(&rtw_suspend_rx_lock, rtw_ms_to_systime(timeout_ms)); + #endif + //DBG_871X("RX lock timeout:%d\n", timeout_ms); +} + + +inline void rtw_lock_traffic_suspend_timeout(u32 timeout_ms) +{ + #ifdef CONFIG_WAKELOCK + wake_lock_timeout(&rtw_suspend_traffic_lock, rtw_ms_to_systime(timeout_ms)); + #elif defined(CONFIG_ANDROID_POWER) + android_lock_suspend_auto_expire(&rtw_suspend_traffic_lock, rtw_ms_to_systime(timeout_ms)); + #endif + //DBG_871X("traffic lock timeout:%d\n", timeout_ms); +} + +inline void rtw_lock_resume_scan_timeout(u32 timeout_ms) +{ + #ifdef CONFIG_WAKELOCK + wake_lock_timeout(&rtw_resume_scan_lock, rtw_ms_to_systime(timeout_ms)); + #elif defined(CONFIG_ANDROID_POWER) + android_lock_suspend_auto_expire(&rtw_resume_scan_lock, rtw_ms_to_systime(timeout_ms)); + #endif + //DBG_871X("resume scan lock:%d\n", timeout_ms); +} + +inline void ATOMIC_SET(ATOMIC_T *v, int i) +{ + #ifdef PLATFORM_LINUX + atomic_set(v,i); + #elif defined(PLATFORM_WINDOWS) + *v=i;// other choice???? + #elif defined(PLATFORM_FREEBSD) + atomic_set_int(v,i); + #endif +} + +inline int ATOMIC_READ(ATOMIC_T *v) +{ + #ifdef PLATFORM_LINUX + return atomic_read(v); + #elif defined(PLATFORM_WINDOWS) + return *v; // other choice???? + #elif defined(PLATFORM_FREEBSD) + return atomic_load_acq_32(v); + #endif +} + +inline void ATOMIC_ADD(ATOMIC_T *v, int i) +{ + #ifdef PLATFORM_LINUX + atomic_add(i,v); + #elif defined(PLATFORM_WINDOWS) + InterlockedAdd(v,i); + #elif defined(PLATFORM_FREEBSD) + atomic_add_int(v,i); + #endif +} +inline void ATOMIC_SUB(ATOMIC_T *v, int i) +{ + #ifdef PLATFORM_LINUX + atomic_sub(i,v); + #elif defined(PLATFORM_WINDOWS) + InterlockedAdd(v,-i); + #elif defined(PLATFORM_FREEBSD) + atomic_subtract_int(v,i); + #endif +} + +inline void ATOMIC_INC(ATOMIC_T *v) +{ + #ifdef PLATFORM_LINUX + atomic_inc(v); + #elif defined(PLATFORM_WINDOWS) + InterlockedIncrement(v); + #elif defined(PLATFORM_FREEBSD) + atomic_add_int(v,1); + #endif +} + +inline void ATOMIC_DEC(ATOMIC_T *v) +{ + #ifdef PLATFORM_LINUX + atomic_dec(v); + #elif defined(PLATFORM_WINDOWS) + InterlockedDecrement(v); + #elif defined(PLATFORM_FREEBSD) + atomic_subtract_int(v,1); + #endif +} + +inline int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i) +{ + #ifdef PLATFORM_LINUX + return atomic_add_return(i,v); + #elif defined(PLATFORM_WINDOWS) + return InterlockedAdd(v,i); + #elif defined(PLATFORM_FREEBSD) + atomic_add_int(v,i); + return atomic_load_acq_32(v); + #endif +} + +inline int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i) +{ + #ifdef PLATFORM_LINUX + return atomic_sub_return(i,v); + #elif defined(PLATFORM_WINDOWS) + return InterlockedAdd(v,-i); + #elif defined(PLATFORM_FREEBSD) + atomic_subtract_int(v,i); + return atomic_load_acq_32(v); + #endif +} + +inline int ATOMIC_INC_RETURN(ATOMIC_T *v) +{ + #ifdef PLATFORM_LINUX + return atomic_inc_return(v); + #elif defined(PLATFORM_WINDOWS) + return InterlockedIncrement(v); + #elif defined(PLATFORM_FREEBSD) + atomic_add_int(v,1); + return atomic_load_acq_32(v); + #endif +} + +inline int ATOMIC_DEC_RETURN(ATOMIC_T *v) +{ + #ifdef PLATFORM_LINUX + return atomic_dec_return(v); + #elif defined(PLATFORM_WINDOWS) + return InterlockedDecrement(v); + #elif defined(PLATFORM_FREEBSD) + atomic_subtract_int(v,1); + return atomic_load_acq_32(v); + #endif +} + + +#ifdef PLATFORM_LINUX +/* +* Open a file with the specific @param path, @param flag, @param mode +* @param fpp the pointer of struct file pointer to get struct file pointer while file opening is success +* @param path the path of the file to open +* @param flag file operation flags, please refer to linux document +* @param mode please refer to linux document +* @return Linux specific error code +*/ +static int openFile(struct file **fpp, char *path, int flag, int mode) +{ + struct file *fp; + + fp=filp_open(path, flag, mode); + if(IS_ERR(fp)) { + *fpp=NULL; + return PTR_ERR(fp); + } + else { + *fpp=fp; + return 0; + } +} + +/* +* Close the file with the specific @param fp +* @param fp the pointer of struct file to close +* @return always 0 +*/ +static int closeFile(struct file *fp) +{ + filp_close(fp,NULL); + return 0; +} + +static int readFile(struct file *fp,char *buf,int len) +{ + int rlen=0, sum=0; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 0)) + if (!(fp->f_mode & FMODE_CAN_READ)) +#else + if (!fp->f_op || !fp->f_op->read) +#endif + return -EPERM; + + while(sum= KERNEL_VERSION(4, 1, 0)) + rlen = __vfs_read(fp, buf+sum, len-sum, &fp->f_pos); +#else + rlen = fp->f_op->read(fp, buf+sum, len-sum, &fp->f_pos); +#endif + if(rlen>0) + sum+=rlen; + else if(0 != rlen) + return rlen; + else + break; + } + + return sum; + +} + +static int writeFile(struct file *fp,char *buf,int len) +{ + int wlen=0, sum=0; + + if (!fp->f_op || !fp->f_op->write) + return -EPERM; + + while(sumf_op->write(fp,buf+sum,len-sum, &fp->f_pos); + if(wlen>0) + sum+=wlen; + else if(0 != wlen) + return wlen; + else + break; + } + + return sum; + +} + +/* +* Test if the specifi @param path is a file and readable +* @param path the path of the file to test +* @return Linux specific error code +*/ +static int isFileReadable(char *path) +{ + struct file *fp; + int ret = 0; +#ifdef set_fs + mm_segment_t oldfs; +#endif + char buf; + + fp=filp_open(path, O_RDONLY, 0); + if(IS_ERR(fp)) { + ret = PTR_ERR(fp); + } + else { +#ifdef set_fs + oldfs = get_fs(); + set_fs(KERNEL_DS); +#endif + + if(1!=readFile(fp, &buf, 1)) + ret = PTR_ERR(fp); + +#ifdef set_fs + set_fs(oldfs); +#endif + filp_close(fp,NULL); + } + return ret; +} + +/* +* Open the file with @param path and retrive the file content into memory starting from @param buf for @param sz at most +* @param path the path of the file to open and read +* @param buf the starting address of the buffer to store file content +* @param sz how many bytes to read at most +* @return the byte we've read, or Linux specific error code +*/ +static int retriveFromFile(char *path, u8* buf, u32 sz) +{ + int ret =-1; +#ifdef set_fs + mm_segment_t oldfs; +#endif + struct file *fp; + + if(path && buf) { + if( 0 == (ret=openFile(&fp,path, O_RDONLY, 0)) ){ + DBG_871X("%s openFile path:%s fp=%p\n",__FUNCTION__, path ,fp); + +#ifdef set_fs + oldfs = get_fs(); + set_fs(KERNEL_DS); + ret=readFile(fp, buf, sz); + set_fs(oldfs); +#else + ret=readFile(fp, buf, sz); +#endif + closeFile(fp); + + DBG_871X("%s readFile, ret:%d\n",__FUNCTION__, ret); + + } else { + DBG_871X("%s openFile path:%s Fail, ret:%d\n",__FUNCTION__, path, ret); + } + } else { + DBG_871X("%s NULL pointer\n",__FUNCTION__); + ret = -EINVAL; + } + return ret; +} + +/* +* Open the file with @param path and wirte @param sz byte of data starting from @param buf into the file +* @param path the path of the file to open and write +* @param buf the starting address of the data to write into file +* @param sz how many bytes to write at most +* @return the byte we've written, or Linux specific error code +*/ +static int storeToFile(char *path, u8* buf, u32 sz) +{ + int ret =0; +#ifdef set_fs + mm_segment_t oldfs; +#endif + struct file *fp; + + if(path && buf) { + if( 0 == (ret=openFile(&fp, path, O_CREAT|O_WRONLY, 0666)) ) { + DBG_871X("%s openFile path:%s fp=%p\n",__FUNCTION__, path ,fp); + +#ifdef set_fs + oldfs = get_fs(); + set_fs(KERNEL_DS); + ret=writeFile(fp, buf, sz); + set_fs(oldfs); +#else + ret=writeFile(fp, buf, sz); +#endif + closeFile(fp); + + DBG_871X("%s writeFile, ret:%d\n",__FUNCTION__, ret); + + } else { + DBG_871X("%s openFile path:%s Fail, ret:%d\n",__FUNCTION__, path, ret); + } + } else { + DBG_871X("%s NULL pointer\n",__FUNCTION__); + ret = -EINVAL; + } + return ret; +} +#endif //PLATFORM_LINUX + +/* +* Test if the specifi @param path is a file and readable +* @param path the path of the file to test +* @return _TRUE or _FALSE +*/ +int rtw_is_file_readable(char *path) +{ + //Todo... + return _FALSE; +} + +/* +* Open the file with @param path and retrive the file content into memory starting from @param buf for @param sz at most +* @param path the path of the file to open and read +* @param buf the starting address of the buffer to store file content +* @param sz how many bytes to read at most +* @return the byte we've read +*/ +int rtw_retrieve_from_file(char *path, u8 *buf, u32 sz) +{ + //Todo... + return 0; +} + +/* +* Open the file with @param path and wirte @param sz byte of data starting from @param buf into the file +* @param path the path of the file to open and write +* @param buf the starting address of the data to write into file +* @param sz how many bytes to write at most +* @return the byte we've written +*/ +int rtw_store_to_file(char *path, u8* buf, u32 sz) +{ + //Todo... + return 0; +} + +#ifdef PLATFORM_LINUX +struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, void *old_priv) +{ + struct net_device *pnetdev; + struct rtw_netdev_priv_indicator *pnpi; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) + pnetdev = alloc_etherdev_mq(sizeof(struct rtw_netdev_priv_indicator), 4); +#else + pnetdev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator)); +#endif + if (!pnetdev) + goto RETURN; + + pnpi = netdev_priv(pnetdev); + pnpi->priv=old_priv; + pnpi->sizeof_priv=sizeof_priv; + +RETURN: + return pnetdev; +} + +struct net_device *rtw_alloc_etherdev(int sizeof_priv) +{ + struct net_device *pnetdev; + struct rtw_netdev_priv_indicator *pnpi; + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) + pnetdev = alloc_etherdev_mq(sizeof(struct rtw_netdev_priv_indicator), 4); +#else + pnetdev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator)); +#endif + if (!pnetdev) + goto RETURN; + + pnpi = netdev_priv(pnetdev); + + pnpi->priv = rtw_zvmalloc(sizeof_priv); + if (!pnpi->priv) { + free_netdev(pnetdev); + pnetdev = NULL; + goto RETURN; + } + + pnpi->sizeof_priv=sizeof_priv; +RETURN: + return pnetdev; +} + +void rtw_free_netdev(struct net_device * netdev) +{ + struct rtw_netdev_priv_indicator *pnpi; + + if(!netdev) + goto RETURN; + + pnpi = netdev_priv(netdev); + + if(!pnpi->priv) + goto RETURN; + + free_netdev(netdev); + +RETURN: + return; +} + +/* +* Jeff: this function should be called under ioctl (rtnl_lock is accquired) while +* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26) +*/ +int rtw_change_ifname(_adapter *padapter, const char *ifname) +{ + struct net_device *pnetdev; + struct net_device *cur_pnetdev; + struct rereg_nd_name_data *rereg_priv; + int ret; + + if(!padapter) + goto error; + + cur_pnetdev = padapter->pnetdev; + rereg_priv = &padapter->rereg_nd_name_priv; + + //free the old_pnetdev + if(rereg_priv->old_pnetdev) { + free_netdev(rereg_priv->old_pnetdev); + rereg_priv->old_pnetdev = NULL; + } + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)) + if(!rtnl_is_locked()) + unregister_netdev(cur_pnetdev); + else +#endif + unregister_netdevice(cur_pnetdev); + + rereg_priv->old_pnetdev=cur_pnetdev; + + pnetdev = rtw_init_netdev(padapter); + if (!pnetdev) { + ret = -1; + goto error; + } + + SET_NETDEV_DEV(pnetdev, dvobj_to_dev(adapter_to_dvobj(padapter))); + + rtw_init_netdev_name(pnetdev, ifname); + +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 17, 0) + _rtw_memcpy(pnetdev->dev_addr, adapter_mac_addr(padapter), ETH_ALEN); +#else + dev_addr_set(pnetdev, adapter_mac_addr(padapter)); +#endif + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)) + if(!rtnl_is_locked()) + ret = register_netdev(pnetdev); + else +#endif + ret = register_netdevice(pnetdev); + + if ( ret != 0) { + RT_TRACE(_module_hci_intfs_c_,_drv_err_,("register_netdev() failed\n")); + goto error; + } + + return 0; + +error: + + return -1; + +} +#endif + +#ifdef PLATFORM_FREEBSD +/* + * Copy a buffer from userspace and write into kernel address + * space. + * + * This emulation just calls the FreeBSD copyin function (to + * copy data from user space buffer into a kernel space buffer) + * and is designed to be used with the above io_write_wrapper. + * + * This function should return the number of bytes not copied. + * I.e. success results in a zero value. + * Negative error values are not returned. + */ +unsigned long +copy_from_user(void *to, const void *from, unsigned long n) +{ + if ( copyin(from, to, n) != 0 ) { + /* Any errors will be treated as a failure + to copy any of the requested bytes */ + return n; + } + + return 0; +} + +unsigned long +copy_to_user(void *to, const void *from, unsigned long n) +{ + if ( copyout(from, to, n) != 0 ) { + /* Any errors will be treated as a failure + to copy any of the requested bytes */ + return n; + } + + return 0; +} + + +/* + * The usb_register and usb_deregister functions are used to register + * usb drivers with the usb subsystem. In this compatibility layer + * emulation a list of drivers (struct usb_driver) is maintained + * and is used for probing/attaching etc. + * + * usb_register and usb_deregister simply call these functions. + */ +int +usb_register(struct usb_driver *driver) +{ + rtw_usb_linux_register(driver); + return 0; +} + + +int +usb_deregister(struct usb_driver *driver) +{ + rtw_usb_linux_deregister(driver); + return 0; +} + +void module_init_exit_wrapper(void *arg) +{ + int (*func)(void) = arg; + func(); + return; +} + +#endif //PLATFORM_FREEBSD + +#ifdef CONFIG_PLATFORM_SPRD +#ifdef do_div +#undef do_div +#endif +#include +#endif + +u64 rtw_modular64(u64 x, u64 y) +{ +#ifdef PLATFORM_LINUX + return do_div(x, y); +#elif defined(PLATFORM_WINDOWS) + return (x % y); +#elif defined(PLATFORM_FREEBSD) + return (x %y); +#endif +} + +u64 rtw_division64(u64 x, u64 y) +{ +#ifdef PLATFORM_LINUX + do_div(x, y); + return x; +#elif defined(PLATFORM_WINDOWS) + return (x / y); +#elif defined(PLATFORM_FREEBSD) + return (x / y); +#endif +} + +inline u32 rtw_random32(void) +{ +#ifdef PLATFORM_LINUX + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,8,0)) + #if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0) + return get_random_u32(); + #else + return prandom_u32(); + #endif + #elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)) + u32 random_int; + get_random_bytes( &random_int , 4 ); + return random_int; + #else + return random32(); + #endif +#elif defined(PLATFORM_WINDOWS) + #error "to be implemented\n" +#elif defined(PLATFORM_FREEBSD) + #error "to be implemented\n" +#endif +} + +void rtw_buf_free(u8 **buf, u32 *buf_len) +{ + u32 ori_len; + + if (!buf || !buf_len) + return; + + ori_len = *buf_len; + + if (*buf) { + u32 tmp_buf_len = *buf_len; + *buf_len = 0; + rtw_mfree(*buf, tmp_buf_len); + *buf = NULL; + } +} + +void rtw_buf_update(u8 **buf, u32 *buf_len, u8 *src, u32 src_len) +{ + u32 ori_len = 0, dup_len = 0; + u8 *ori = NULL; + u8 *dup = NULL; + + if (!buf || !buf_len) + return; + + if (!src || !src_len) + goto keep_ori; + + /* duplicate src */ + dup = rtw_malloc(src_len); + if (dup) { + dup_len = src_len; + _rtw_memcpy(dup, src, dup_len); + } + +keep_ori: + ori = *buf; + ori_len = *buf_len; + + /* replace buf with dup */ + *buf_len = 0; + *buf = dup; + *buf_len = dup_len; + + /* free ori */ + if (ori && ori_len > 0) + rtw_mfree(ori, ori_len); +} + + +/** + * rtw_cbuf_full - test if cbuf is full + * @cbuf: pointer of struct rtw_cbuf + * + * Returns: _TRUE if cbuf is full + */ +inline bool rtw_cbuf_full(struct rtw_cbuf *cbuf) +{ + return (cbuf->write == cbuf->read-1)? _TRUE : _FALSE; +} + +/** + * rtw_cbuf_empty - test if cbuf is empty + * @cbuf: pointer of struct rtw_cbuf + * + * Returns: _TRUE if cbuf is empty + */ +inline bool rtw_cbuf_empty(struct rtw_cbuf *cbuf) +{ + return (cbuf->write == cbuf->read)? _TRUE : _FALSE; +} + +/** + * rtw_cbuf_push - push a pointer into cbuf + * @cbuf: pointer of struct rtw_cbuf + * @buf: pointer to push in + * + * Lock free operation, be careful of the use scheme + * Returns: _TRUE push success + */ +bool rtw_cbuf_push(struct rtw_cbuf *cbuf, void *buf) +{ + if (rtw_cbuf_full(cbuf)) + return _FAIL; + + if (0) + DBG_871X("%s on %u\n", __func__, cbuf->write); + cbuf->bufs[cbuf->write] = buf; + cbuf->write = (cbuf->write+1)%cbuf->size; + + return _SUCCESS; +} + +/** + * rtw_cbuf_pop - pop a pointer from cbuf + * @cbuf: pointer of struct rtw_cbuf + * + * Lock free operation, be careful of the use scheme + * Returns: pointer popped out + */ +void *rtw_cbuf_pop(struct rtw_cbuf *cbuf) +{ + void *buf; + if (rtw_cbuf_empty(cbuf)) + return NULL; + + if (0) + DBG_871X("%s on %u\n", __func__, cbuf->read); + buf = cbuf->bufs[cbuf->read]; + cbuf->read = (cbuf->read+1)%cbuf->size; + + return buf; +} + +/** + * rtw_cbuf_alloc - allocte a rtw_cbuf with given size and do initialization + * @size: size of pointer + * + * Returns: pointer of srtuct rtw_cbuf, NULL for allocation failure + */ +struct rtw_cbuf *rtw_cbuf_alloc(u32 size) +{ + struct rtw_cbuf *cbuf; + + cbuf = (struct rtw_cbuf *)rtw_malloc(sizeof(*cbuf) + sizeof(void*)*size); + + if (cbuf) { + cbuf->write = cbuf->read = 0; + cbuf->size = size; + } + + return cbuf; +} + +/** + * rtw_cbuf_free - free the given rtw_cbuf + * @cbuf: pointer of struct rtw_cbuf to free + */ +void rtw_cbuf_free(struct rtw_cbuf *cbuf) +{ + rtw_mfree((u8*)cbuf, sizeof(*cbuf) + sizeof(void*)*cbuf->size); +} + +/** +* IsHexDigit - +* +* Return TRUE if chTmp is represent for hex digit +* FALSE otherwise. +*/ +inline BOOLEAN IsHexDigit(char chTmp) +{ + if ((chTmp >= '0' && chTmp <= '9') || + (chTmp >= 'a' && chTmp <= 'f') || + (chTmp >= 'A' && chTmp <= 'F')) + return _TRUE; + else + return _FALSE; +} + +/** +* is_alpha - +* +* Return TRUE if chTmp is represent for alphabet +* FALSE otherwise. +*/ +inline BOOLEAN is_alpha(char chTmp) +{ + if ((chTmp >= 'a' && chTmp <= 'z') || + (chTmp >= 'A' && chTmp <= 'Z')) + return _TRUE; + else + return _FALSE; +} + +inline char alpha_to_upper(char c) +{ + if ((c >= 'a' && c <= 'z')) + c = 'A' + (c - 'a'); + return c; +} diff --git a/src/little/linux/sound/core/pcm_lib.c b/src/little/linux/sound/core/pcm_lib.c index bda3514c7..31d6f48e9 100644 --- a/src/little/linux/sound/core/pcm_lib.c +++ b/src/little/linux/sound/core/pcm_lib.c @@ -483,7 +483,7 @@ void snd_pcm_set_ops(struct snd_pcm *pcm, int direction, { struct snd_pcm_str *stream = &pcm->streams[direction]; struct snd_pcm_substream *substream; - + for (substream = stream->substream; substream != NULL; substream = substream->next) substream->ops = ops; } @@ -498,7 +498,7 @@ EXPORT_SYMBOL(snd_pcm_set_ops); void snd_pcm_set_sync(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; - + runtime->sync.id32[0] = substream->pcm->card->number; runtime->sync.id32[1] = -1; runtime->sync.id32[2] = -1; @@ -510,7 +510,7 @@ EXPORT_SYMBOL(snd_pcm_set_sync); * Standard ioctl routine */ -static inline unsigned int div32(unsigned int a, unsigned int b, +static inline unsigned int div32(unsigned int a, unsigned int b, unsigned int *r) { if (b == 0) { @@ -774,7 +774,7 @@ void snd_interval_mulkdiv(const struct snd_interval *a, unsigned int k, /** * snd_interval_ratnum - refine the interval value * @i: interval to refine - * @rats_count: number of ratnum_t + * @rats_count: number of ratnum_t * @rats: ratnum_t array * @nump: pointer to store the resultant numerator * @denp: pointer to store the resultant denominator @@ -829,7 +829,7 @@ int snd_interval_ratnum(struct snd_interval *i, } t.min = div_down(best_num, best_den); t.openmin = !!(best_num % best_den); - + result_num = best_num; result_diff = best_diff; result_den = best_den; @@ -941,7 +941,7 @@ static int snd_interval_ratden(struct snd_interval *i, } t.min = div_down(best_num, best_den); t.openmin = !!(best_num % best_den); - + best_num = best_den = best_diff = 0; for (k = 0; k < rats_count; ++k) { unsigned int num; @@ -1229,7 +1229,7 @@ EXPORT_SYMBOL(snd_pcm_hw_constraint_integer); * @var: hw_params variable to apply the range * @min: the minimal value * @max: the maximal value - * + * * Apply the min/max range constraint to an interval parameter. * * Return: Positive if the value is changed, zero if it's not changed, or a @@ -1253,7 +1253,7 @@ static int snd_pcm_hw_rule_list(struct snd_pcm_hw_params *params, { struct snd_pcm_hw_constraint_list *list = rule->private; return snd_interval_list(hw_param_interval(params, rule->var), list->count, list->list, list->mask); -} +} /** @@ -1262,7 +1262,7 @@ static int snd_pcm_hw_rule_list(struct snd_pcm_hw_params *params, * @cond: condition bits * @var: hw_params variable to apply the list constraint * @l: list - * + * * Apply the list of constraints to an interval parameter. * * Return: Zero if successful, or a negative error code on failure. @@ -1333,7 +1333,7 @@ static int snd_pcm_hw_rule_ratnums(struct snd_pcm_hw_params *params, * * Return: Zero if successful, or a negative error code on failure. */ -int snd_pcm_hw_constraint_ratnums(struct snd_pcm_runtime *runtime, +int snd_pcm_hw_constraint_ratnums(struct snd_pcm_runtime *runtime, unsigned int cond, snd_pcm_hw_param_t var, const struct snd_pcm_hw_constraint_ratnums *r) @@ -1367,7 +1367,7 @@ static int snd_pcm_hw_rule_ratdens(struct snd_pcm_hw_params *params, * * Return: Zero if successful, or a negative error code on failure. */ -int snd_pcm_hw_constraint_ratdens(struct snd_pcm_runtime *runtime, +int snd_pcm_hw_constraint_ratdens(struct snd_pcm_runtime *runtime, unsigned int cond, snd_pcm_hw_param_t var, const struct snd_pcm_hw_constraint_ratdens *r) @@ -1411,7 +1411,7 @@ static int snd_pcm_hw_rule_msbits(struct snd_pcm_hw_params *params, * * Return: Zero if successful, or a negative error code on failure. */ -int snd_pcm_hw_constraint_msbits(struct snd_pcm_runtime *runtime, +int snd_pcm_hw_constraint_msbits(struct snd_pcm_runtime *runtime, unsigned int cond, unsigned int width, unsigned int msbits) @@ -1445,7 +1445,7 @@ int snd_pcm_hw_constraint_step(struct snd_pcm_runtime *runtime, snd_pcm_hw_param_t var, unsigned long step) { - return snd_pcm_hw_rule_add(runtime, cond, var, + return snd_pcm_hw_rule_add(runtime, cond, var, snd_pcm_hw_rule_step, (void *) step, var, -1); } @@ -1461,7 +1461,7 @@ static int snd_pcm_hw_rule_pow2(struct snd_pcm_hw_params *params, struct snd_pcm }; return snd_interval_list(hw_param_interval(params, rule->var), ARRAY_SIZE(pow2_sizes), pow2_sizes, 0); -} +} /** * snd_pcm_hw_constraint_pow2 - add a hw constraint power-of-2 rule @@ -1475,7 +1475,7 @@ int snd_pcm_hw_constraint_pow2(struct snd_pcm_runtime *runtime, unsigned int cond, snd_pcm_hw_param_t var) { - return snd_pcm_hw_rule_add(runtime, cond, var, + return snd_pcm_hw_rule_add(runtime, cond, var, snd_pcm_hw_rule_pow2, NULL, var, -1); } @@ -1618,8 +1618,8 @@ static int _snd_pcm_hw_param_first(struct snd_pcm_hw_params *params, * * Return: The minimum, or a negative error code on failure. */ -int snd_pcm_hw_param_first(struct snd_pcm_substream *pcm, - struct snd_pcm_hw_params *params, +int snd_pcm_hw_param_first(struct snd_pcm_substream *pcm, + struct snd_pcm_hw_params *params, snd_pcm_hw_param_t var, int *dir) { int changed = _snd_pcm_hw_param_first(params, var); @@ -1664,7 +1664,7 @@ static int _snd_pcm_hw_param_last(struct snd_pcm_hw_params *params, * * Return: The maximum, or a negative error code on failure. */ -int snd_pcm_hw_param_last(struct snd_pcm_substream *pcm, +int snd_pcm_hw_param_last(struct snd_pcm_substream *pcm, struct snd_pcm_hw_params *params, snd_pcm_hw_param_t var, int *dir) { @@ -1886,7 +1886,7 @@ static int wait_for_avail(struct snd_pcm_substream *substream, case SNDRV_PCM_STATE_DRAINING: if (is_playback) err = -EPIPE; - else + else avail = 0; /* indicate draining */ goto _endloop; case SNDRV_PCM_STATE_OPEN: @@ -1911,7 +1911,7 @@ static int wait_for_avail(struct snd_pcm_substream *substream, *availp = avail; return err; } - + typedef int (*pcm_transfer_f)(struct snd_pcm_substream *substream, int channel, unsigned long hwoff, void *buf, unsigned long bytes); @@ -1968,6 +1968,7 @@ static int fill_silence(struct snd_pcm_substream *substream, int channel, return 0; } +#if 0 /* default copy_user ops for read; used for both interleaved and non- modes */ static int default_read_copy(struct snd_pcm_substream *substream, int channel, unsigned long hwoff, @@ -1979,6 +1980,92 @@ static int default_read_copy(struct snd_pcm_substream *substream, return -EFAULT; return 0; } +#else +/* default copy_user ops for read; used for both interleaved and non- modes */ +#include +static int default_read_copy(struct snd_pcm_substream *substream, + int channel, unsigned long hwoff, + void *buf, unsigned long bytes) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + int i =0; + void* pDmaPtr = NULL; + int*p32Data = NULL; + int mix32Data = 0; + + short*p16Data = NULL; + short mix16Data = 0; + static const int AUDIO_DATA16_MAX = 32767; // 2^15（short） + static const int AUDIO_DATA16_MIN = -32768; + static const int AUDIO_DATA32_MAX = 2147483647; // 2^31（int） + static const int AUDIO_DATA32_MIN = -2147483648; + + //mix left and right channel + //only process audio codec is inno and pcm capture + if (SNDRV_PCM_STREAM_CAPTURE == substream->stream && 1 == rtd->num_codecs && (0 == strcmp(rtd->dai_link->codecs->dai_name,"k230-inno-codec-dai"))) + { + // only process stereo channel and 16/32 bit + if (2 == substream->runtime->channels) + { + + pDmaPtr = get_dma_ptr(substream->runtime, channel, hwoff); + if (substream->runtime->format >= SNDRV_PCM_FORMAT_S16_LE && substream->runtime->format <= SNDRV_PCM_FORMAT_U16_BE) + { + p16Data = (short*)pDmaPtr; + for (i =0;i< bytes/4;i++) + { + mix16Data = *p16Data + *(p16Data+1); + if (mix16Data > AUDIO_DATA16_MAX) + { + mix16Data = AUDIO_DATA16_MAX; + } + else if (mix16Data < AUDIO_DATA16_MIN) + { + mix16Data = AUDIO_DATA16_MIN; + } + *p16Data = mix16Data; + *(p16Data+1) = mix16Data; + p16Data += 2; + } + } + else if (substream->runtime->format >= SNDRV_PCM_FORMAT_S32_LE && substream->runtime->format <= SNDRV_PCM_FORMAT_U32_BE) + { + p32Data = (int*)pDmaPtr; + for (i =0;i< bytes/8;i++) + { + mix32Data = *p32Data + *(p32Data+1); + if (mix32Data > AUDIO_DATA32_MAX) + { + mix32Data = AUDIO_DATA32_MAX; + } + else if (mix32Data < AUDIO_DATA32_MIN) + { + mix32Data = AUDIO_DATA32_MIN; + } + *p32Data = mix32Data; + *(p32Data+1) = mix32Data; + p32Data += 2; + } + } + + + if (copy_to_user((void __user *)buf, + pDmaPtr, + bytes)) + return -EFAULT; + + return 0; + } + } + + if (copy_to_user((void __user *)buf, + get_dma_ptr(substream->runtime, channel, hwoff), + bytes)) + return -EFAULT; + + return 0; +} +#endif /* default copy_kernel ops for read */ static int default_read_copy_kernel(struct snd_pcm_substream *substream, diff --git a/src/little/linux/sound/soc/Kconfig b/src/little/linux/sound/soc/Kconfig index 71a6fe87d..417f527ff 100644 --- a/src/little/linux/sound/soc/Kconfig +++ b/src/little/linux/sound/soc/Kconfig @@ -14,7 +14,7 @@ menuconfig SND_SOC If you want ASoC support, you should say Y here and also to the specific driver for your SoC platform below. - + ASoC provides power efficient ALSA support for embedded battery powered SoC based systems like PDA's, Phones and Personal Media Players. @@ -84,5 +84,8 @@ source "sound/soc/codecs/Kconfig" # generic frame-work source "sound/soc/generic/Kconfig" +# canaan k230 audio +source "sound/soc/canaan/Kconfig" + endif # SND_SOC diff --git a/src/little/linux/sound/soc/Makefile b/src/little/linux/sound/soc/Makefile index ddbac3a21..689ed9768 100644 --- a/src/little/linux/sound/soc/Makefile +++ b/src/little/linux/sound/soc/Makefile @@ -60,3 +60,4 @@ obj-$(CONFIG_SND_SOC) += ux500/ obj-$(CONFIG_SND_SOC) += xilinx/ obj-$(CONFIG_SND_SOC) += xtensa/ obj-$(CONFIG_SND_SOC) += zte/ +obj-$(CONFIG_SND_SOC) += canaan/ diff --git a/src/little/linux/sound/soc/canaan/Kconfig b/src/little/linux/sound/soc/canaan/Kconfig new file mode 100644 index 000000000..38b193fdc --- /dev/null +++ b/src/little/linux/sound/soc/canaan/Kconfig @@ -0,0 +1,11 @@ +config SND_SOC_CANAAN_K230_INNO + tristate "ASoC support for CANAAN boards using a inno codec" + help + Say Y or M here if you want to add support for SoC audio on CANAAN K230 + boards using the INNO codec. + +config SND_SOC_CANAAN_K230_AUDIO + tristate "CANAAN K230 AUDIO interface support" + help + Say Y or M here if you want to enable audio for canaan soc. + diff --git a/src/little/linux/sound/soc/canaan/Makefile b/src/little/linux/sound/soc/canaan/Makefile new file mode 100644 index 000000000..02894b745 --- /dev/null +++ b/src/little/linux/sound/soc/canaan/Makefile @@ -0,0 +1,8 @@ +snd-soc-canaan-k230-audio-objs := canaan_k230_audio.o +obj-$(CONFIG_SND_SOC_CANAAN_K230_AUDIO) += snd-soc-canaan-k230-audio.o + +snd-soc-canaan-k230-inno-objs := canaan_k230_inno.o audio_muxpin_ctrl.o muxpin_reg_ctl.o + +obj-$(CONFIG_SND_SOC_CANAAN_K230_INNO) += snd-soc-canaan-k230-inno.o + + diff --git a/src/little/linux/sound/soc/canaan/audio_muxpin_ctrl.c b/src/little/linux/sound/soc/canaan/audio_muxpin_ctrl.c new file mode 100644 index 000000000..b704c16e1 --- /dev/null +++ b/src/little/linux/sound/soc/canaan/audio_muxpin_ctrl.c @@ -0,0 +1,113 @@ +/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "audio_muxpin_ctrl.h" +#include "muxpin_reg_ctl.h" + + +void ai_i2s_muxpin_config(void) +{ + muxpin_reg_init(); + +#define AUDIO_I2S_ENABLE_CHANNEL_OUT0_IN1 0 +#define AUDIO_I2S_CLK 32 +#define AUDIO_I2S_WS 33 +#define AUDIO_I2S_I2SIN1 36 + +#define AUDIO_I2S_I2SIN0 34 + + muxpin_config_t config1 = + { + 0x0, //st + 0x4, //ds + 0x0, //pd + 0x0, //pu + 0x1, //oe + 0x0, //ie + 0x1, //msc + 0x0, //sl + 0x2 //io_sel + }; + + muxpin_config_t config2 = + { + 0x0, //st + 0x4, //ds + 0x0, //pd + 0x0, //pu + 0x0, //oe + 0x1, //ie + 0x1, //msc + 0x0, //sl + 0x2 //io_sel + }; + + + //受限于硬件，I2S_0支持声音播放，I2S_1支持话音输入； + //func3 out + muxpin_set_config(AUDIO_I2S_CLK, config1); + muxpin_set_config(AUDIO_I2S_WS, config1); + +#if AUDIO_I2S_ENABLE_CHANNEL_OUT0_IN1 + //func3 in + muxpin_set_config(AUDIO_I2S_I2SIN1, config2); + +#else + //func3 in + muxpin_set_config(AUDIO_I2S_I2SIN0, config2); +#endif +} + +void ao_i2s_muxpin_config(void) +{ + muxpin_reg_init(); +#define AUDIO_I2S_CLK 32 +#define AUDIO_I2S_WS 33 +#define AUDIO_I2S_I2SOUT0 35 +#define AUDIO_I2S_I2SOUT1 37 + + muxpin_config_t config1 = + { + 0x0, //st + 0x4, //ds + 0x0, //pd + 0x0, //pu + 0x1, //oe + 0x0, //ie + 0x1, //msc + 0x0, //sl + 0x2 //io_sel + }; + + + //受限于硬件，I2S_0支持声音播放，I2S_1支持话音输入； + //func3 out + muxpin_set_config(AUDIO_I2S_CLK, config1); + muxpin_set_config(AUDIO_I2S_WS, config1); + + muxpin_set_config(AUDIO_I2S_I2SOUT0, config1); + muxpin_set_config(AUDIO_I2S_I2SOUT1, config1); +} + diff --git a/src/little/linux/sound/soc/canaan/audio_muxpin_ctrl.h b/src/little/linux/sound/soc/canaan/audio_muxpin_ctrl.h new file mode 100644 index 000000000..ce610d7ff --- /dev/null +++ b/src/little/linux/sound/soc/canaan/audio_muxpin_ctrl.h @@ -0,0 +1,34 @@ +/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __AUDIO_MUXPIN_CTL_H__ +#define __AUDIO_MUXPIN_CTL_H__ +#include + +void ai_i2s_muxpin_config(void); +void ao_i2s_muxpin_config(void); + +#endif + + diff --git a/src/little/linux/sound/soc/canaan/canaan_k230_audio.c b/src/little/linux/sound/soc/canaan/canaan_k230_audio.c new file mode 100644 index 000000000..e7dbdce9e --- /dev/null +++ b/src/little/linux/sound/soc/canaan/canaan_k230_audio.c @@ -0,0 +1,102 @@ +#include +#include +#include "canaan_k230_audio.h" +#include +#include + +struct canaan_audio_data { + struct platform_device *pdev; + void __iomem *base; +}; + +static struct canaan_audio_data sai = {0}; + +void audio_i2s_in_init(void) +{ + if(sai.base) + { + volatile audio_in_reg_s *audio_in_reg = sai.base; + audio_in_reg->audio_in_pdm_conf_0.audio_in_mode = AUDIO_IO_OUT_MODE_I2S;//默认使用i2s + audio_in_reg->audio_in_agc_para_4.agc_bypass = AUDIO_ENABLE; + } +} + +EXPORT_SYMBOL_GPL(audio_i2s_in_init); + +void audio_i2s_out_init(bool enable, uint32_t word_len) +{ + audio_out_data_width_e out_word_len = AUDIO_OUT_TYPE_32BIT; + if (32 == word_len) + { + out_word_len = AUDIO_OUT_TYPE_32BIT; + } + else if (24 == word_len) + { + out_word_len = AUDIO_OUT_TYPE_24BIT; + } + else if (16 == word_len) + { + out_word_len = AUDIO_OUT_TYPE_16BIT; + } + if(sai.base) + { + volatile audio_out_reg_s *audio_out_reg = sai.base + 0x800; + audio_out_reg->audio_out_ctl.data_type = out_word_len; + audio_out_reg->audio_out_ctl.mode = AUDIO_OUT_MODE_I2S; /* i2s/pdm/tdm mode */ + audio_out_reg->audio_out_ctl.enable = enable ? AUDIO_ENABLE : AUDIO_DISABLE; /* enable audio out */ + } +} + +EXPORT_SYMBOL_GPL(audio_i2s_out_init); + +void audio_i2s_enable_audio_codec(bool use_audio_codec) +{ + if(sai.base){ + volatile audio_in_reg_s *audio_in_reg = sai.base; + audio_in_reg->audio_in_pdm_conf_0.audio_codec_bypass = !use_audio_codec;//是否启用内置codec + } +} + +EXPORT_SYMBOL_GPL(audio_i2s_enable_audio_codec); + +static int canaan_audio_probe(struct platform_device *pdev) +{ + struct resource *res; + int ret = 0; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + sai.base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(sai.base)) + return PTR_ERR(sai.base); + + platform_set_drvdata(pdev, &sai); + + return ret; +} + +static int canaan_audio_remove(struct platform_device *pdev) +{ + struct canaan_audio_data *priv = platform_get_drvdata(pdev); + + return 0; +} + +static const struct of_device_id canaan_audio_ids[] = { + { .compatible = "canaan,k230-audio" }, + { /* sentinel */ }, +}; + +static struct platform_driver canaan_audio_driver = { + .driver = { + .name = "k230-audio", + .of_match_table = canaan_audio_ids, + }, + .probe = canaan_audio_probe, + .remove = canaan_audio_remove, +}; + +module_platform_driver(canaan_audio_driver); + +MODULE_DESCRIPTION("CANAAN AUDIO Interface"); +MODULE_LICENSE("GPL"); diff --git a/src/little/linux/sound/soc/canaan/canaan_k230_audio.h b/src/little/linux/sound/soc/canaan/canaan_k230_audio.h new file mode 100644 index 000000000..c819c4d22 --- /dev/null +++ b/src/little/linux/sound/soc/canaan/canaan_k230_audio.h @@ -0,0 +1,507 @@ +/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _CANAAN_AUDIO_H +#define _CANAAN_AUDIO_H +#include + +typedef enum +{ + AUDIO_DISABLE = 0, + AUDIO_ENABLE = 1, +} audio_enable_e; + +typedef enum +{ + AUDIO_OUT_TYPE_32BIT = 0, + AUDIO_OUT_TYPE_24BIT = 1, + AUDIO_OUT_TYPE_16BIT = 2, +} audio_out_data_width_e; + +typedef enum +{ + AUDIO_OUT_24BIT_ALIGN_RIGTH = 0, + AUDIO_OUT_24BIT_ALIGN_LEFT = 1, +} audio_out_align_e; + +typedef enum +{ + AUDIO_OUT_MODE_TDM = 0, + AUDIO_OUT_MODE_PDM = 1, + AUDIO_OUT_MODE_I2S = 2, +} audio_out_mode_e; + +typedef enum +{ + AUDIO_OUT_PDM_RISING = 0, + AUDIO_OUT_PDM_BOTH = 1, +} audio_out_pdm_edge_e; + +typedef enum +{ + AUDIO_PDM_OUT_CIC16 = 0, + AUDIO_PDM_OUT_CIC32 = 1, +} audio_out_pdm_cic_e; + +typedef enum +{ + AUDIO_PDM_OVERSAMPLE_32 = 0, + AUDIO_PDM_OVERSAMPLE_64, + AUDIO_PDM_OVERSAMPLE_128, +} audio_pdm_oversample_e; +typedef struct _audio_out_ctl +{ + uint32_t enable : 1; /* bit0: 0: disable 1:enable */ + uint32_t data_type : 2; /* bit1-2: 0: channel 32bit; 1:channel 24bit 2:channel 16bit */ + uint32_t align : 1; /* bit3: 0: 24bit right align; 1: 24bit left align */ + uint32_t loop_en : 1; /* bit4: 0: disable 1:enable */ + uint32_t mode : 2; /* bit5-6: 0: pcm 1:pdm 2:i2s */ + uint32_t fir2_out_bypass : 1; /* bit7: 0: enable 1:bypass ENABLE for bypass*/ + uint32_t dma_enable : 1; /* bit8: 0: disable 1:enable */ + uint32_t channel_num : 4; /* bit9-12: channel number */ + uint32_t dma_threshold : 5; /* bit13-17: dma threshold 16bit should be >= 2; 24/32bit should be >= 1 */ + uint32_t reserved : 14; /* bit18-31 */ +} __attribute__((packed, aligned(4))) audio_out_ctl_s; + +typedef struct _audio_out_rcv_fifo +{ + uint32_t audio_fifo_clear : 1; + uint32_t ref_fifo_th : 5; + uint32_t reserved : 26; +} __attribute__((packed, aligned(4))) audio_out_rcv_fifo_s; + +typedef struct _audio_out_tdm_conf +{ + uint32_t frame_sclk_delay : 1; /* bit0: delay or not. 1: frame sync delay 1 cycle */ + uint32_t frame_sync_total : 10; /* bit1-10: how many sclks frame sync 32*channels */ + uint32_t frame_sync_high : 10; /* bit1-10: how many sclks frame sync high, 1~channel bit width */ + uint32_t reserved : 11; /* reserved */ +} __attribute__((packed, aligned(4))) audio_out_tdm_conf_s; + +typedef struct _audio_out_pmd_conf +{ + uint32_t reserved0 : 4; /* bit0 */ + uint32_t pcm_sync_en : 1; /* bit4:*/ + uint32_t pdm_spike_th : 4; /* bit5-8:*/ + uint32_t pdm_ord_sel : 1; /* bit9: 0 for 24bit * 44.1K cic16 = 2.8224MHz, 1for 24bit * 16K cic32 += 2.048MHz */ + uint32_t pdm_pn_sel : 1; /* bit10: 0 for rising edge , 1 for rising&failing edge*/ + uint32_t reserved1 : 21; /* bit11-bit31: reserved*/ +} __attribute__((packed, aligned(4))) audio_out_pmd_conf_s; + +typedef struct _audio_out_condition +{ + uint32_t ref_out_fifo_rdy : 1; /* bit0: */ + uint32_t out_buf_full : 1; /* bit1: */ + uint32_t out_buf_empty : 1; /* bit2: */ + uint32_t out_rdy : 1; /* bit3: */ + uint32_t reserved : 28; /* bit4-bit32:*/ +} __attribute__((packed, aligned(4))) audio_out_condition_s; + +typedef struct _audio_filter_conf +{ + uint32_t loop_fir_bypass : 1; /* bit0 */ + uint32_t pdm_cic_filter_bypass : 1; /* bit1 bypass cic */ + uint32_t pdm_cic_mp_filter_bypass : 1; /* bit2 bypass cic补偿 */ + uint32_t pdm_hbf_filter_bypass : 1; /* bit3 bypass hbf */ + uint32_t reserved : 28; +} __attribute__((packed, aligned(4))) audio_filter_conf_s; + + +typedef struct _audio_iir_fir_conf +{ + uint32_t T_DST : 16; + uint32_t resample_sel_bypass : 3; + uint32_t iir_scnt : 4; + uint32_t iir_clr : 1; + uint32_t reserved : 8; +} __attribute__((packed, aligned(4))) audio_iir_fir_conf_s; + +typedef struct _audio_out_reg +{ + audio_out_ctl_s audio_out_ctl; /* address:0x00 */ + audio_out_rcv_fifo_s audio_out_fifo; /* address:0x04 */ + uint32_t audio_out_reserved0[1]; /* address:0x08 */ + audio_out_tdm_conf_s audio_out_tdm_conf; /* address:0x0c */ + + int audio_out_data; /* address:0x10 audio output register */ + uint32_t audio_out_reserved1[5]; /* address:0x14 */ + uint32_t audio_out_interrupt; /* address:0x28 reserved for future use */ + uint32_t audio_out_reserved2[1]; + audio_out_pmd_conf_s audio_out_pdm_conf; /* address:0x30 */ + uint32_t audio_out_iir_matrix_a[4][4]; /* address:0x34 */ + uint32_t audio_out_iir_matrix_b[4][2]; /* address:0x74 */ + uint32_t audio_out_iir_matrix_c[4]; /* address:0x94 */ + uint32_t audio_out_iir_matrix_d; /* address:0xa4 */ + uint32_t audio_out_ref2apb_data; /* address:0xa8 loopback? echo & mix ?*/ + + audio_out_condition_s audio_out_condition; /* address:0xac read only*/ + uint32_t audio_out_reserved3[16]; /* address:0xb0 read only*/ + uint32_t fir2_tap_coef[11]; /* address:0xf0 read only*/ + uint32_t reserved1[2]; /* address:0x11c-0x120*/ + uint32_t fir2_tap_coef_11[9]; /* address:0x124-0x144*/ + uint32_t reserved2; /* address:0x148*/ + uint32_t fir2_tap_coef_20[12]; /* address:0x14c-0x178*/ + audio_filter_conf_s audio_out_filter; /* address:0x17c*/ + uint32_t fir0_tap_coef[32]; /* address:0x180*/ + uint32_t fir1_tap_coef[32]; /* address:0x260*/ + audio_iir_fir_conf_s iir_fir_conf; /* address:0x340*/ + uint32_t iir_x_parameter[3]; /* address:0x344*/ + uint32_t pn_delay; /* address:0x350*/ +} __attribute__((packed, aligned(4))) audio_out_reg_s; + + +/* --------------------------------------------------audio input +-----------------------------------------------------*/ +/* pdm */ +typedef enum +{ + AUDIO_IO_IN_MODE_PDM = 0,//IO35、IO37:PDM in0和i2s out1复用的IO功能选择为i2s out1，PDM in1和i2s out0复用的IO功能选择为i2s out0； + AUDIO_IO_OUT_MODE_I2S = 2,//IO35、IO37:PDM in0和i2s out1复用的IO功能选择为PDM in0，PDM in1和i2s out0复用的IO功能选择为PDM in1。 +} audio_io_select_mode_e; + +typedef enum +{ + AUDIO_IN_LEFT_ALIGN = 0, + AUDIO_IN_RIGHT_ALIGN = 1, +} audio_in_align_e; + +typedef enum +{ + AUDIO_IN_PDM_BOTH = 0, + AUDIO_IN_PDM_RISING = 2, + AUDIO_IN_PDM_FAILING = 3, +} audio_in_pdm_edge_e; + +typedef enum +{ + AUDIO_IN_PDM_CIC16 = 0, + AUDIO_IN_PDM_CIC32 = 1, +} audio_in_pdm_cic_e; + +typedef struct _audio_in_pdm_conf_0 +{ + uint32_t pdm_enable : 1; /* bit0: 1 enable, 0 disable */ + uint32_t mpf_enable : 1; /* bit2: cic 补偿滤波器 1 enable, 0 disable */ + uint32_t hbf_enable : 1; /* bit1: 1 enable, 0 disable */ + uint32_t pdm_in_endian : 1; /* bit3: pdm +input时读入的pdm转换后的pcm数据位于32bit数据的位置：0:高28bit(4bit通道号+24bit pcm数据) ,1: +低28bit(4bit通道号+24bit pcm数据) */ + uint32_t pdm_fifo_clear : 1; /* bit4: fifo clear */ + uint32_t audio_codec_bypass : 1; /* bit5: bypass audio codec, use I2S directly to IO for digital I2S +microphone */ + uint32_t audio_in_mode : 2; /* bit76: 10: PDM in0和i2s out1复用的IO功能选择为i2s out1，PDM +in1和i2s out0复用的IO功能选择为i2s out0； + 其它：PDM in0和i2s out1复用的IO功能选择为PDM in0，PDM +in1和i2s out0复用的IO功能选择为PDM in1。*/ + uint32_t pdm_dma_fifo_th : 5; /* bit8-12: should as same as dma controller */ + uint32_t audio_dev_clk_sel : 1; /* bit13:audio_clk invert control signal */ + uint32_t pdm_clk_sel : 1; /* bit14:pdm_clk invert control signal*/ + uint32_t reserved2 : 1; /* bit15: */ + uint32_t pdm_buf_rdy : 1; /* bit16: software check this bit and receive data */ + uint32_t reserved : 15; /* bit17 ~ bit31:reserved */ +} __attribute__((packed, aligned(4))) audio_in_pdm_conf_0_s; + +typedef struct _audio_in_pdm_conf_1 +{ + uint32_t ord_select : 1; /* bit0: 0 for 16, 1 for 32 */ + uint32_t reserved : 31; /* bit1-31: */ +} __attribute__((packed, aligned(4))) audio_in_pdm_conf_1_s; + +typedef struct _audio_in_pdm_ch_conf +{ + uint32_t pdm_chl_num : 4; /* bit0-3: pdm input channel num*/ + uint32_t pdm_pn_sel : 2; /* bit4-5: 2'b10: posedge 2'b11: negedge others: double edge*/ + uint32_t reserved : 26; +} __attribute__((packed, aligned(4))) audio_in_pdm_ch_conf_s; + +/* TDM */ +typedef struct _audio_in_tdm_conf_0 +{ + uint32_t tdm_channel_mode : 4; /* bit0-3 : select tdm input channel number; 4'h0: 24 channel; 4'h1: 12; 4'h2: +8; 4'h3: 6; 4'h4: 4; 4'h5:3; 4'h6:2; 4'h7:1 */ + uint32_t tdm_width_mode : 3; /* 0: 32; 1:24；2:20; 3:16; 4:12 */ + uint32_t reserved1 : 4; /* reserved1*/ + uint32_t tdm_clk_dly : 1; /* bit11, data delay one clock or not, frame_sync , 1表示在frame +sync后一拍出数据，0表示在frame sync当前拍出数据*/ + uint32_t tdm_in_endian : 1; /* bit12 0: 24/12 bit left align 1: 24/12 bit right align */ + uint32_t tdm_dma_fifo_th : 5; /* bit13-17:tdm fifo thershold set for making tdm dma request*/ + uint32_t reserved2 : 14; +} __attribute__((packed, aligned(4))) audio_in_tdm_conf_0_s; + +typedef struct _audio_in_tdm_channel_cfg0 +{ + uint32_t io0_channel_num : 4; /* 2-24 channel */ + uint32_t io1_channel_num : 4; /* 2-24 channel */ + uint32_t io2_channel_num : 4; /* 2-24 channel */ + uint32_t io3_channel_num : 4; /* 2-24 channel */ + uint32_t io4_channel_num : 4; /* 2-24 channel */ + uint32_t io5_channel_num : 4; /* 2-24 channel */ + uint32_t io6_channel_num : 4; /* 2-24 channel */ + uint32_t io7_channel_num : 4; /* 2-24 channel */ +} __attribute__((packed, aligned(4))) audio_in_tdm_channel_cfg0_s; + +typedef struct _audio_in_tdm_channel_cfg1 +{ + uint32_t io8_channel_num : 4; /* 2-24 channel */ + uint32_t io9_channel_num : 4; /* 2-24 channel */ + uint32_t io10_channel_num : 4; /* 2-24 channel */ + uint32_t io11_channel_num : 4; /* 2-24 channel */ + uint32_t io12_channel_num : 4; /* 2-24 channel */ + uint32_t io13_channel_num : 4; /* 2-24 channel */ + uint32_t io14_channel_num : 4; /* 2-24 channel */ + uint32_t io15_channel_num : 4; /* 2-24 channel */ +} __attribute__((packed, aligned(4))) audio_in_tdm_channel_cfg1_s; + +typedef struct _audio_in_tdm_fsync_config +{ + uint32_t tdm_fsync_div_high : 10; + uint32_t tdm_fsync_div_low : 10; + uint32_t reserved : 12; +} __attribute__((packed, aligned(4))) audio_in_tdm_fsync_config_s; + +typedef struct _audio_in_tdm_ctl +{ + uint32_t tdm_intr : 1; /* write 1 to clear */ + uint32_t audi_buf_full_n2 : 1; /* tdm fifo full */ + uint32_t audi_buf_rdy_n2 : 1; /* tdm fifo not empty, data could be read from fifo */ + uint32_t tdm_enable : 1; /* enable tdm */ + uint32_t reserved : 28; +} __attribute__((packed, aligned(4))) audio_in_tdm_ctl_s; + +/* audio in agc */ +typedef struct _audio_in_agc_para_0 +{ + uint32_t agc_gatt : 16; + uint32_t agc_headroom : 16; +} __attribute__((packed, aligned(4))) auido_in_agc_para0_s; + +typedef struct _audio_in_agc_para_1 +{ + uint32_t agc_np_margin : 16; + uint32_t agc_gdth : 16; +} __attribute__((packed, aligned(4))) auido_in_agc_para1_s; + +typedef struct _audio_in_agc_para_2 +{ + uint32_t agc_gainstep_slow : 16; + uint32_t agc_gainstep_fast : 16; +} __attribute__((packed, aligned(4))) auido_in_agc_para2_s; + +typedef struct _audio_in_agc_para_3 +{ + uint32_t agc_frame_num : 16; + uint32_t agc_max_gainstep : 16; +} __attribute__((packed, aligned(4))) auido_in_agc_para3_s; + +typedef struct _audio_in_agc_para_4 +{ + uint32_t agc_bypass : 1; + uint32_t agc_model2_en : 1; + uint32_t agc_model1_en : 1; + uint32_t agc_sd_sel : 1; + uint32_t agc_xpkth : 16; + uint32_t agc_nvak_num : 6; + uint32_t agc_npkobs : 6; +} __attribute__((packed, aligned(4))) auido_in_agc_para4_s; + +typedef struct _audio_in_agc_para_5 +{ + uint32_t agc_us_num : 16; + uint32_t agc_dpk : 16; +} __attribute__((packed, aligned(4))) auido_in_agc_para5_s; + +typedef struct _audio_in_agc_para_6 +{ + uint32_t agc_ds_num : 16; + uint32_t agc_ub_num : 16; +} __attribute__((packed, aligned(4))) auido_in_agc_para6_s; + +typedef struct _audio_in_agc_para_7 +{ + uint32_t agc_ku : 16; + uint32_t agc_db_num : 16; +} __attribute__((packed, aligned(4))) auido_in_agc_para7_s; + +typedef struct _audio_in_agc_para_8 +{ + uint32_t agc_d : 16; + uint32_t agc_kd : 16; +} __attribute__((packed, aligned(4))) auido_in_agc_para8_s; + +typedef struct _audio_in_agc_para_9 +{ + uint32_t agc_theta_1 : 16; + uint32_t agc_theta_0 : 16; +} __attribute__((packed, aligned(4))) auido_in_agc_para9_s; + +typedef struct _audio_in_agc_para_10 +{ + uint32_t agc_d2b_num : 16; + uint32_t agc_d2s_num : 16; +} __attribute__((packed, aligned(4))) auido_in_agc_para10_s; + +typedef struct _audio_in_agc_para_11 +{ + uint32_t agc_d2b_num; +} __attribute__((packed, aligned(4))) auido_in_agc_para11_s; + +typedef struct _audio_in_iir_fir_ctl +{ + uint32_t chl_num : 3; /* 只能设置8个通道? */ + uint32_t T_DST : 16; /* I don't known */ + uint32_t re_bypass : 3; /* disable resample, fir, iir */ + uint32_t iir_scnt : 4; /* status move bit */ + uint32_t iir_clear : 1; /* iir clear */ + uint32_t reserved : 5; +} __attribute__((packed, aligned(4))) audio_in_iir_fir_ctl_s; + +typedef struct _audio_in_pdm_clk_spike +{ + /* debounce */ + uint32_t pdmin_clk_spike_cnt : 2; /* 0: 1 pclk cycle, 1: 2 pclk cycles, 2: 3 pclk cycles, 3: 4 pclk cycles*/ + uint32_t pdmin_clk_spike_th : 2; /* 0: 2 pclk cycle, 1: 3 pclk cycles, 2: 4 pclk cycles, 3: 5 pclk cycles */ + uint32_t reserved : 28; +} __attribute__((packed, aligned(4))) audio_in_pdm_clk_spike_s; + +typedef struct _audio_in_pdm_ch_spike +{ + /* debounce */ + uint32_t pdmin_ch0_spike_cnt : 2; /* 0: 1 pclk cycle, 1: 2 pclk cycles, 2: 3 pclk cycles, 3: 4 pclk cycles*/ + uint32_t pdmin_ch0_spike_th : 2; /* 0: 2 pclk cycle, 1: 3 pclk cycles, 2: 4 pclk cycles, 3: 5 pclk cycles */ + uint32_t pdmin_ch1_spike_cnt : 2; /* 0: 1 pclk cycle, 1: 2 pclk cycles, 2: 3 pclk cycles, 3: 4 pclk cycles*/ + uint32_t pdmin_ch1_spike_th : 2; /* 0: 2 pclk cycle, 1: 3 pclk cycles, 2: 4 pclk cycles, 3: 5 pclk cycles */ + uint32_t pdmin_ch2_spike_cnt : 2; /* 0: 1 pclk cycle, 1: 2 pclk cycles, 2: 3 pclk cycles, 3: 4 pclk cycles*/ + uint32_t pdmin_ch2_spike_th : 2; /* 0: 2 pclk cycle, 1: 3 pclk cycles, 2: 4 pclk cycles, 3: 5 pclk cycles */ + uint32_t pdmin_ch3_spike_cnt : 2; /* 0: 1 pclk cycle, 1: 2 pclk cycles, 2: 3 pclk cycles, 3: 4 pclk cycles*/ + uint32_t pdmin_ch3_spike_th : 2; /* 0: 2 pclk cycle, 1: 3 pclk cycles, 2: 4 pclk cycles, 3: 5 pclk cycles */ + uint32_t pdmin_ch4_spike_cnt : 2; /* 0: 1 pclk cycle, 1: 2 pclk cycles, 2: 3 pclk cycles, 3: 4 pclk cycles*/ + uint32_t pdmin_ch4_spike_th : 2; /* 0: 2 pclk cycle, 1: 3 pclk cycles, 2: 4 pclk cycles, 3: 5 pclk cycles */ + uint32_t pdmin_ch5_spike_cnt : 2; /* 0: 1 pclk cycle, 1: 2 pclk cycles, 2: 3 pclk cycles, 3: 4 pclk cycles*/ + uint32_t pdmin_ch5_spike_th : 2; /* 0: 2 pclk cycle, 1: 3 pclk cycles, 2: 4 pclk cycles, 3: 5 pclk cycles */ + uint32_t pdmin_ch6_spike_cnt : 2; /* 0: 1 pclk cycle, 1: 2 pclk cycles, 2: 3 pclk cycles, 3: 4 pclk cycles*/ + uint32_t pdmin_ch6_spike_th : 2; /* 0: 2 pclk cycle, 1: 3 pclk cycles, 2: 4 pclk cycles, 3: 5 pclk cycles */ + uint32_t pdmin_ch7_spike_cnt : 2; /* 0: 1 pclk cycle, 1: 2 pclk cycles, 2: 3 pclk cycles, 3: 4 pclk cycles*/ + uint32_t pdmin_ch7_spike_th : 2; /* 0: 2 pclk cycle, 1: 3 pclk cycles, 2: 4 pclk cycles, 3: 5 pclk cycles */ +} __attribute__((packed, aligned(4))) audio_in_pdm_ch_spike_s; + +typedef struct _audio_in_pdm_bypass +{ + uint32_t hbf_dsmpl_fir_bypass : 1; + uint32_t cic_mp_dsmpl_fir_bypass: 1; + uint32_t cic_dsmple_fir_bypass : 1; + uint32_t reserved : 29; +} __attribute__((packed, aligned(4))) audio_in_pdm_bypass_s; + +typedef struct _audio_in_reg +{ + /* PDM reg */ + audio_in_pdm_conf_0_s audio_in_pdm_conf_0; /* address:0x00 */ + audio_in_pdm_conf_1_s audio_in_pdm_conf_1; /* address:0x04 0 for 24bit * 44.1K cic16= 2. +8224MHz, 1 for 24bit * 16K cic32= 2.048MHz */ + uint32_t audio_in_pdm_mp_para_tap_coef[16]; /* address:0x08 cic 补偿滤波系数 */ + uint32_t audio_in_pdm_hbf_para_tap_coef[29]; /* address:0x48 hbf 滤波器*/ + audio_in_pdm_ch_conf_s audio_in_pdm_ch_conf; /* address:0xbc */ + uint32_t audio_in_pdm2pcm_data; /* address:0xc0 , read 24bit data +数据有效位28bit，其中[27:24]为数据对应的通道编号，[23:0]为实际pcm数据*/ + uint32_t audio_in_pdm_interrupt; /* address:0xc4 , only bit0 valid,write 0 clear */ + + /* TDM reg */ + audio_in_tdm_conf_0_s audio_in_tdm_config; /* address:0xc8 */ + audio_in_tdm_channel_cfg0_s audio_in_tdm_channel_cfg0; /* address:0xcc */ + audio_in_tdm_channel_cfg1_s audio_in_tdm_channel_cfg1; /* address:0xd0 */ + uint32_t reserved0; + audio_in_tdm_fsync_config_s audio_in_tdm_fsync_config; /* address:0xd8 */ + audio_in_tdm_ctl_s audio_in_tdm_ctl; /* address:0xdc */ + uint32_t reserved1; /* address:0xe0 */ + uint32_t audio_in_tdm2apb_data; /* address:0xe4 data read reg */ + uint32_t reserved2[2]; /* address:0xe8 */ + + /* For TDM/I2S/PDM */ + /* fir0 */ + uint32_t audio_in_fir0_tap_coef[11]; /* address:0xf0 fir before resample */ + uint32_t reserved3[2]; /* address:0x11c-0x120 */ + uint32_t audio_in_fir0_tap_coef_11[9]; /* address:0x124 */ + uint32_t reserved4; /* address:0x148 */ + uint32_t audio_in_fir0_tap_coef_20[12]; /* address:0x14c */ + + /* fir1 */ + uint32_t audio_in_fir1_tap_coef[3]; /* address:0x17c fir after resample */ + uint32_t reserved5; /* address:0x188 */ + uint32_t audio_in_fir1_tap_coef_3[29]; /* address:0x18c fir after resample */ + + /* iir x parameter */ + uint32_t audio_in_iir_x_0_0_1; /* address:0x200 , bit0-15 for 0, bit16-31 for 1 */ + uint32_t audio_in_iir_x_0_2; /* address:0x204 , bit0-15 valid */ + uint32_t audio_in_iir_y_0_0_1; /* address:0x208 , bit0-15 for 0, bit16-31 for 1 */ + + /* agc */ + auido_in_agc_para0_s audio_in_agc_para_0; /* address:0x20c*/ + auido_in_agc_para1_s audio_in_agc_para_1; /* address:0x210*/ + auido_in_agc_para2_s audio_in_agc_para_2; /* address:0x214*/ + auido_in_agc_para3_s audio_in_agc_para_3; /* address:0x218*/ + auido_in_agc_para4_s audio_in_agc_para_4; /* address:0x21c*/ + auido_in_agc_para5_s audio_in_agc_para_5; /* address:0x220*/ + auido_in_agc_para6_s audio_in_agc_para_6; /* address:0x224*/ + auido_in_agc_para7_s audio_in_agc_para_7; /* address:0x228*/ + auido_in_agc_para8_s audio_in_agc_para_8; /* address:0x22c*/ + auido_in_agc_para9_s audio_in_agc_para_9; /* address:0x230*/ + auido_in_agc_para10_s audio_in_agc_para_10; /* address:0x234*/ + auido_in_agc_para11_s audio_in_agc_para_11; /* address:0x238*/ + + /* iir fir config */ + audio_in_iir_fir_ctl_s audio_in_iir_fir_ctl; /* address:0x23c*/ + + /* Only for PDM */ + audio_in_pdm_clk_spike_s audio_in_pdm_clk_spike; /* address:0x240*/ + audio_in_pdm_ch_spike_s audio_in_pdm_ch_spike; /* address:0x244*/ + audio_in_pdm_bypass_s audio_in_pdm_bypass; /* address:0x248*/ +} __attribute__((packed, aligned(4))) audio_in_reg_s; + +typedef enum +{ + AUDIO_SAMPLE_8K = 0, + AUDIO_SAMPLE_16K = 1, /*PDM 16K(24bit) --> HBF(高通+2上采样) --32K----> CIC 补偿(2上采样) -- +64K-----> 4级CIC(32上采样)-->2.048MHz (24bit)(饱和处理)--->环路滤波-->2.048MHz (1bit) */ + AUDIO_SAMPLE_32K = 2, + AUDIO_SAMPLE_44D1K = 3, /*PDM 44.1K(24bit) --> HBF(高通+2上采样) --88.2K--> CIC 补偿(2上采样) -- +176.4K--> 4级CIC(16上采样)-->2.8224MHz(24bit)(饱和处理)--->环路滤波-->2.8224MHz(1bit) */ + AUDIO_SAMPLE_48K = 4, +} audio_sample_e; + +//void audio_io3537_select_mode(audio_io_select_mode_e mode);//IO35,37引脚模式选择 +void audio_i2s_in_init(void); +void audio_i2s_enable_audio_codec(bool use_audio_codec);//i2s选择使用内置audio codec + +//pdm in操作寄存器 +//void audio_pdm_in_init(audio_pdm_oversample_e pdm_oversample, uint32_t pdm_rx_num, audio_in_pdm_edge_e pdm_rx_edge, audio_in_align_e pdm_rx_align); +//volatile uint32_t *audio_pdm_rx_dma_fifo(); +//void audio_pdm_fifo_overrun_clear(); + + + +void audio_i2s_out_init(bool enable, uint32_t word_len); + +#endif + diff --git a/src/little/linux/sound/soc/canaan/canaan_k230_inno.c b/src/little/linux/sound/soc/canaan/canaan_k230_inno.c new file mode 100755 index 000000000..5de3434ea --- /dev/null +++ b/src/little/linux/sound/soc/canaan/canaan_k230_inno.c @@ -0,0 +1,171 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "canaan_k230_audio.h" +#include "audio_muxpin_ctrl.h" + +#define DRV_NAME "canaan-k230-snd-inno" + +struct k230_inno_info { + struct clk *xtal; + struct clk *pclk; + struct mutex clk_lock; + int clk_users; +}; + +static int k230_inno_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + return 0; +} + +static void k230_inno_shutdown(struct snd_pcm_substream *substream) +{ + +} + +static int k230_inno_startup(struct snd_pcm_substream *substream) +{ + return 0; +} + +static const struct snd_soc_ops canaan_k230_inno_ops = { + .startup = k230_inno_startup, + .shutdown = k230_inno_shutdown, + .hw_params = k230_inno_hw_params, +}; + +SND_SOC_DAILINK_DEFS(k230_inno, + DAILINK_COMP_ARRAY(COMP_EMPTY()), + DAILINK_COMP_ARRAY(COMP_CODEC(NULL, "k230-inno-codec-dai")), + DAILINK_COMP_ARRAY(COMP_EMPTY())); + +static struct snd_soc_dai_link canaan_k230_dailink = { + .name = "k230-inno-codec", + .stream_name = "Audio", + .ops = &canaan_k230_inno_ops, + .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBS_CFS, + SND_SOC_DAILINK_REG(k230_inno), +}; + +static struct snd_soc_card snd_soc_card_k230 = { + .name = "CANAAN-K230-I2S", + .owner = THIS_MODULE, + .dai_link = &canaan_k230_dailink, + .num_links = 1, +}; + +static int canaan_k230_inno_probe(struct platform_device *pdev) +{ + struct snd_soc_card *card = &snd_soc_card_k230; + struct device_node *codec_np, *cpu_np; + struct snd_soc_dai_link *dailink = &canaan_k230_dailink; + struct device_node *np = pdev->dev.of_node; + struct k230_inno_info *priv; + int ret; + + if (!np) { + dev_err(&pdev->dev, "only device tree supported\n"); + return -EINVAL; + } + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + mutex_init(&priv->clk_lock); + + card->dev = &pdev->dev; + snd_soc_card_set_drvdata(card, priv); + + codec_np = of_parse_phandle(np, + "canaan,k230-audio-codec", 0); + if (!codec_np) { + dev_err(&pdev->dev, + "Property 'canaan,k230-audio-codec' missing or invalid\n"); + return -EINVAL; + } + dailink->codecs->of_node = codec_np; + of_node_put(codec_np); + + cpu_np = of_parse_phandle(np, + "canaan,k230-i2s-controller", 0); + if (!cpu_np) { + dev_err(&pdev->dev, + "Property 'canaan,k230-i2s-controller' missing or invalid\n"); + return -EINVAL; + } + + dailink->cpus->of_node = cpu_np; + dailink->platforms->of_node = cpu_np; + of_node_put(cpu_np); + + ret = snd_soc_of_parse_card_name(card, "canaan,model"); + if (ret) { + dev_err(&pdev->dev, + "Soc parse card name failed %d\n", ret); + return ret; + } + + + ret = devm_snd_soc_register_card(&pdev->dev, card); + if (ret){ + dev_err(&pdev->dev, "failed to register card: %d\n", ret); + return ret; + } + + // printk("====audio muxpin \n"); + // ai_i2s_muxpin_config(); + // ao_i2s_muxpin_config(); + + audio_i2s_in_init(); + audio_i2s_enable_audio_codec(true); + audio_i2s_out_init(true,32); + + return ret; +} + +static const struct of_device_id canaan_k230_inno_of_match[] = { + { .compatible = "canaan,k230-audio-inno", }, + {}, +}; + +MODULE_DEVICE_TABLE(of, canaan_k230_inno_of_match); + +static struct platform_driver canaan_k230_inno_driver = { + .probe = canaan_k230_inno_probe, + .driver = { + .name = DRV_NAME, + .of_match_table = canaan_k230_inno_of_match, + }, +}; + +module_platform_driver(canaan_k230_inno_driver); + +MODULE_DESCRIPTION("CANAAN k230 inno machine ASoC driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRV_NAME); diff --git a/src/little/linux/sound/soc/canaan/muxpin_reg_ctl.c b/src/little/linux/sound/soc/canaan/muxpin_reg_ctl.c new file mode 100644 index 000000000..4cd619f2a --- /dev/null +++ b/src/little/linux/sound/soc/canaan/muxpin_reg_ctl.c @@ -0,0 +1,222 @@ +/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "muxpin_reg_ctl.h" +#include + + +/* IOMUX */ +#define IOMUX_BASE_ADDR (0x91105000U) + +static volatile muxpin_t *muxpin = NULL; + +int muxpin_reg_init(void) +{ + if (muxpin == NULL) + { + void __iomem *base; + base = ioremap(IOMUX_BASE_ADDR, sizeof(muxpin_t)); + if (IS_ERR(base)) + return -1; + + muxpin = base; + } + + return 0; +} + + + +/** + * @brief set io configuretion + * + * @param io_num 0 ~ 63 + * @param config be careful + * @return int + */ +int muxpin_set_config(int io_num, muxpin_config_t config) +{ + if (io_num > IO_MAX_NUM || io_num < 0) + { + // kendryte_logi("io num error.\n"); + return -1; + } + +#if 1 + muxpin->io[io_num].st = config.st; + muxpin->io[io_num].ds = config.ds; + muxpin->io[io_num].pd = config.pd; + muxpin->io[io_num].pu = config.pu; + muxpin->io[io_num].oe_en = config.oe_en; + muxpin->io[io_num].ie_en = config.ie_en; + muxpin->io[io_num].msc = config.msc; + muxpin->io[io_num].sl = config.sl; + muxpin->io[io_num].io_sel = config.io_sel; + muxpin->io[io_num].pad_di = config.pad_di; +#else + muxpin->io[io_num] = config; +#endif + return 0; +} + +/** + * @brief get io configuretion + * + * @param io_num 0 ~ 63 + * @param config return value + */ +void muxpin_get_config(int io_num, muxpin_config_t *config) +{ + if (io_num > IO_MAX_NUM || io_num < 0) + { +// kendryte_logi("io num error.\n"); + return; + } + + *config = muxpin->io[io_num]; +} + + +/** + * @brief set io pull up/down or none + * + * @param io_num 0 ~ 63 + * @param pull enum value + * @return int + */ +int muxpin_set_io_pull(int io_num, muxpin_pull_t pull) +{ + muxpin_config_t cfg; + if (io_num < 0 || io_num >= MUXPIN_NUM_IO || pull >= MUXPIN_PULL_MAX) + return -1; + + cfg = muxpin->io[io_num]; + switch (pull) + { + case MUXPIN_PULL_NONE: + cfg.pu = 0; + cfg.pd = 0; + break; + case MUXPIN_PULL_DOWN: + cfg.pu = 0; + cfg.pd = 1; + break; + case MUXPIN_PULL_UP: + cfg.pu = 1; + cfg.pd = 0; + break; + default: + break; + } + + muxpin->io[io_num] = cfg; + return 0; +} + + +/** + * @brief set io drive current + * + * @param io_num 0 ~ 63 + * @param driving enum value + * @return int + */ +int muxpin_set_io_driving(int io_num, muxpin_driving_t driving) +{ + muxpin_config_t cfg; + if (io_num > 1 && driving >= MUXPIN_DRIVING_7) + { + // kendryte_logi("io %d can't configured driving 0x%x.\n",io_num,driving); + return -1; + } + + cfg = muxpin->io[io_num]; + cfg.ds = driving; + + muxpin->io[io_num] = cfg; + return 0; +} + + +/** + * @brief set io function + * + * @param io_num 0 ~ 63 + * @param function check table for this number + * @return int + */ +int muxpin_set_function(int io_num, int function) +{ + muxpin_config_t cfg; + if (io_num > IO_MAX_NUM) + { + // kendryte_logi("io num error.\n"); + return -1; + } + + if (function > 5) + { +// kendryte_logi("please check your function num.\n"); + return -1; + } + + cfg = muxpin->io[io_num]; + cfg.io_sel = function; + + muxpin->io[io_num] = cfg; + return 0; +} + + +/** + * @brief set io voltage + * + * @param io_num 0 ~ 63 + * @param voltage 1:1.8v 0:3.3v + * @return int + */ +int muxpin_set_io_voltage(int io_num, muxpin_io_voltage_t voltage) +{ + if (io_num > IO_MAX_NUM) + { + // kendryte_logi("error: please check your io num and voltage.\n"); + return -1; + } + + if (io_num < 2 && voltage == 0) + { +// kendryte_logi("error: io %d not suport 3.3v.\n",io_num); + return -1; + } + + muxpin->io[io_num].msc = (MUXPIN_IO_VOLTAGE_1V8 == voltage) ? 1 : 0; + return 0; +} + + + + + + diff --git a/src/little/linux/sound/soc/canaan/muxpin_reg_ctl.h b/src/little/linux/sound/soc/canaan/muxpin_reg_ctl.h new file mode 100644 index 000000000..63e72f733 --- /dev/null +++ b/src/little/linux/sound/soc/canaan/muxpin_reg_ctl.h @@ -0,0 +1,121 @@ +/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef _MUXPIN_REG_CTL_H +#define _MUXPIN_REG_CTL_H + +#include + +#define IO_MAX_NUM 64 + +typedef enum muxpin_pull_e +{ + MUXPIN_PULL_NONE, /*!< No Pull */ + MUXPIN_PULL_DOWN, /*!< Pull Down */ + MUXPIN_PULL_UP, /*!< Pull Up */ + MUXPIN_PULL_MAX /*!< Count of pull settings */ +} muxpin_pull_t; + +typedef enum muxpin_driving_e +{ + MUXPIN_DRIVING_0, /*!< 000 */ + MUXPIN_DRIVING_1, /*!< 001 */ + MUXPIN_DRIVING_2, /*!< 010 */ + MUXPIN_DRIVING_3, /*!< 011 */ + MUXPIN_DRIVING_4, /*!< 100 */ + MUXPIN_DRIVING_5, /*!< 101 */ + MUXPIN_DRIVING_6, /*!< 110 */ + MUXPIN_DRIVING_7, /*!< 111 */ + MUXPIN_DRIVING_8, /*!< 1000 */ + MUXPIN_DRIVING_9, /*!< 1001 */ + MUXPIN_DRIVING_10, /*!< 1010 */ + MUXPIN_DRIVING_11, /*!< 1100 */ + MUXPIN_DRIVING_12, /*!< 1101 */ + MUXPIN_DRIVING_13, /*!< 1110 */ + MUXPIN_DRIVING_14, /*!< 1111 */ +} muxpin_driving_t; + +typedef enum muxpin_io_voltage_e +{ + MUXPIN_IO_VOLTAGE_1V8 = 1, + MUXPIN_IO_VOLTAGE_3V3 = 0, +} muxpin_io_voltage_t; + + +typedef struct mux_config +{ + uint32_t st : 1; + /*!< Schmitt trigger. */ + uint32_t ds : 4; + /*!< Driving selector. */ + uint32_t pd : 1; + /*!< Pull down enable. 0 for nothing, 1 for pull down. */ + uint32_t pu : 1; + /*!< Pull up enable. 0 for nothing, 1 for pull up. */ + uint32_t oe_en : 1; + /*!< Static output enable. */ + uint32_t ie_en : 1; + /*!< Static output enable. */ + uint32_t msc : 1; + /*!< msc control bit. */ + uint32_t sl : 1; + /*!< Slew rate control enable. */ + /*!< IO config setting. */ + uint32_t io_sel : 3; + /*!< set io function mode. */ + uint32_t resv0 : 17; + /*!< Reserved bits. */ + uint32_t pad_di : 1; + /*!< Read current IO's data input. */ +} __attribute__((aligned(4))) muxpin_config_t; + +typedef enum muxpin_io_function +{ + MUXPIN_FUNCTION1 = 0x0, + MUXPIN_FUNCTION2 = 0x1, + MUXPIN_FUNCTION3 = 0x2, + MUXPIN_FUNCTION4 = 0x3, + MUXPIN_FUNCTION5 = 0x4, +} muxpin_io_function_t; + +#define MUXPIN_NUM_IO (64) +typedef struct _muxpin_t +{ + muxpin_config_t io[MUXPIN_NUM_IO]; + /*!< FPIOA GPIO multiplexer io array */ +} __attribute__((aligned(4))) muxpin_t ; + + + +int muxpin_reg_init(void); +int muxpin_set_config(int io_num, muxpin_config_t config); +void muxpin_get_config(int io_num, muxpin_config_t *config); +int muxpin_set_io_pull(int io_num, muxpin_pull_t pull); +int muxpin_set_io_driving(int io_num, muxpin_driving_t driving); +int muxpin_set_function(int io_num, int function); +int muxpin_set_io_voltage(int io_num, muxpin_io_voltage_t voltage); + +#endif + + diff --git a/src/little/linux/sound/soc/codecs/Kconfig b/src/little/linux/sound/soc/codecs/Kconfig index 34c6dd04b..d12323e73 100644 --- a/src/little/linux/sound/soc/codecs/Kconfig +++ b/src/little/linux/sound/soc/codecs/Kconfig @@ -1784,4 +1784,7 @@ config SND_SOC_TPA6130A2 tristate "Texas Instruments TPA6130A2 headphone amplifier" depends on I2C +config SND_SOC_K230_INNO + tristate "K230 INNO Codec" + endmenu diff --git a/src/little/linux/sound/soc/codecs/Makefile b/src/little/linux/sound/soc/codecs/Makefile index 11ce98c25..03ff03d8e 100644 --- a/src/little/linux/sound/soc/codecs/Makefile +++ b/src/little/linux/sound/soc/codecs/Makefile @@ -306,6 +306,8 @@ snd-soc-tas2552-objs := tas2552.o snd-soc-tas2562-objs := tas2562.o snd-soc-tas2764-objs := tas2764.o +snd-soc-inno-k230_codec-objs := inno_k230_reg.o inno_k230.o + obj-$(CONFIG_SND_SOC_88PM860X) += snd-soc-88pm860x.o obj-$(CONFIG_SND_SOC_AB8500_CODEC) += snd-soc-ab8500-codec.o obj-$(CONFIG_SND_SOC_AC97_CODEC) += snd-soc-ac97.o @@ -613,3 +615,9 @@ obj-$(CONFIG_SND_SOC_MAX9877) += snd-soc-max9877.o obj-$(CONFIG_SND_SOC_MAX98504) += snd-soc-max98504.o obj-$(CONFIG_SND_SOC_SIMPLE_AMPLIFIER) += snd-soc-simple-amplifier.o obj-$(CONFIG_SND_SOC_TPA6130A2) += snd-soc-tpa6130a2.o + + +# inno_k230_codec-y := inno_k230_reg.o +# inno_k230_codec-y += inno_k230.o +obj-$(CONFIG_SND_SOC_K230_INNO) += snd-soc-inno-k230_codec.o + diff --git a/src/little/linux/sound/soc/codecs/inno_k230.c b/src/little/linux/sound/soc/codecs/inno_k230.c new file mode 100644 index 000000000..ae189db80 --- /dev/null +++ b/src/little/linux/sound/soc/codecs/inno_k230.c @@ -0,0 +1,477 @@ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include "inno_k230_reg.h" + +#define INNO_VOLUME_INVERT_VALUE 39 + +struct k230_inno_codec_priv { + void __iomem *base; + struct clk *pclk_adc; + struct clk *pclk_dac; + struct regmap *regmap; + struct device *dev; +}; + +enum snd_inno_k230_ctrl { + INNO_PCM_PLAYBACK_VOLUME, + INNO_PCM_PLAYBACK_MUTE, + INNO_PCM_CAPTURE_VOLUME, + INNO_PCM_CAPTURE_MUTE, +}; + +static int inno_capture_info_vol(struct snd_kcontrol *kcontrol,struct snd_ctl_elem_info *uinfo) +{ + //printk("====================inno_info_vol\n"); + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 2; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = 4; + return 0; +} + +static int inno_capture_get_vol(struct snd_kcontrol *kcontrol,struct snd_ctl_elem_value *ucontrol) +{ + + return 0; +} + +static int inno_capture_put_vol(struct snd_kcontrol *kcontrol,struct snd_ctl_elem_value *ucontrol) +{ + + return 0; +} + +static const struct snd_kcontrol_new inno_snd_capture_volume_control = +{ + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, //表示snd_kcontrol结构体用于哪一类设备（表示进行参数设置） + .name = "Capture Volume", //音量控制，每个声卡驱动程序的snd_kcontrol各不相同，为什么应用程序都可以调整它的音量，对于某些常用的属性，它们都有固定的名字。应用程序根据名字找到它的snd_kcontrol项，调用里面的put函数。 + .info = inno_capture_info_vol, //获得一些信息，如音量范围是多少 + .get = inno_capture_get_vol,//获得当前的音量值 + .put = inno_capture_put_vol, //设置音量 +}; + +static int inno_playback_info_vol(struct snd_kcontrol *kcontrol,struct snd_ctl_elem_info *uinfo) +{ + //printk("====================inno_info_vol\n"); + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 2; + uinfo->value.integer.min = -39+INNO_VOLUME_INVERT_VALUE; + uinfo->value.integer.max = 6+INNO_VOLUME_INVERT_VALUE; + return 0; +} + +static int inno_playback_get_vol(struct snd_kcontrol *kcontrol,struct snd_ctl_elem_value *ucontrol) +{ + int value; + + audio_codec_dac_get_hpoutl_gain(&value); + //printk("=========inno_get_vol:%d\n",value+INNO_VOLUME_INVERT_VALUE); + ucontrol->value.integer.value[1] = ucontrol->value.integer.value[0] = value+INNO_VOLUME_INVERT_VALUE; + return 0; +} + +static int inno_playback_put_vol(struct snd_kcontrol *kcontrol,struct snd_ctl_elem_value *ucontrol) +{ + //printk("=========inno_put_vol:%d\n",ucontrol->value.integer.value[0]); + + audio_codec_dac_set_hpoutl_gain(ucontrol->value.integer.value[0]-INNO_VOLUME_INVERT_VALUE); + audio_codec_dac_set_hpoutr_gain(ucontrol->value.integer.value[0]-INNO_VOLUME_INVERT_VALUE); + return 0; +} + +static const struct snd_kcontrol_new inno_snd_playback_volume_control = +{ + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, //表示snd_kcontrol结构体用于哪一类设备（表示进行参数设置） + .name = "Master Playback Volume", //音量控制，每个声卡驱动程序的snd_kcontrol各不相同，为什么应用程序都可以调整它的音量，对于某些常用的属性，它们都有固定的名字。应用程序根据名字找到它的snd_kcontrol项，调用里面的put函数。 + .info = inno_playback_info_vol, //获得一些信息，如音量范围是多少 + .get = inno_playback_get_vol,//获得当前的音量值 + .put = inno_playback_put_vol, //设置音量 +}; + +static int snd_inno_ctl_vol(struct snd_kcontrol *kcontrol,struct snd_ctl_elem_info *uinfo) +{ + if (kcontrol->private_value == INNO_PCM_PLAYBACK_VOLUME) + { + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 1; + uinfo->value.integer.min = -39+INNO_VOLUME_INVERT_VALUE; + uinfo->value.integer.max = 6+INNO_VOLUME_INVERT_VALUE; + uinfo->value.integer.step = 3; + } + else if (kcontrol->private_value == INNO_PCM_PLAYBACK_MUTE) + { + uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; + uinfo->count = 1; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = 1; + } + else if (kcontrol->private_value == INNO_PCM_CAPTURE_VOLUME) + { + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 1; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = 30; + uinfo->value.integer.step = 10; + } + else if (kcontrol->private_value == INNO_PCM_CAPTURE_MUTE) + { + uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; + uinfo->count = 1; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = 1; + } + return 0; +} + +static int snd_inno_ctl_get(struct snd_kcontrol *kcontrol,struct snd_ctl_elem_value *ucontrol) +{ + int value; + bool mute; + + if (kcontrol->private_value == INNO_PCM_PLAYBACK_VOLUME) + { + audio_codec_dac_get_hpoutl_gain(&value); + ucontrol->value.integer.value[0] = value+INNO_VOLUME_INVERT_VALUE; + } + else if (kcontrol->private_value == INNO_PCM_PLAYBACK_MUTE) + { + audio_codec_dac_get_hpoutl_mute(&mute); + ucontrol->value.integer.value[0] = !mute; + } + else if (kcontrol->private_value == INNO_PCM_CAPTURE_VOLUME) + { + audio_codec_adc_get_micl_gain(&value); + if (value == 6) + { + value = 10; + } + ucontrol->value.integer.value[0] = value; + } + else if (kcontrol->private_value == INNO_PCM_CAPTURE_MUTE) + { + audio_codec_adc_get_micl_mute(&mute); + ucontrol->value.integer.value[0] = !mute; + } + return 0; +} + +static int snd_inno_ctl_put(struct snd_kcontrol *kcontrol,struct snd_ctl_elem_value *ucontrol) +{ + if (kcontrol->private_value == INNO_PCM_PLAYBACK_VOLUME) + { + audio_codec_dac_set_hpoutl_gain(ucontrol->value.integer.value[0]-INNO_VOLUME_INVERT_VALUE); + audio_codec_dac_set_hpoutr_gain(ucontrol->value.integer.value[0]-INNO_VOLUME_INVERT_VALUE); + } + else if (kcontrol->private_value == INNO_PCM_PLAYBACK_MUTE) + { + audio_codec_dac_hpoutl_mute(!ucontrol->value.integer.value[0]); + audio_codec_dac_hpoutr_mute(!ucontrol->value.integer.value[0]); + } + else if (kcontrol->private_value == INNO_PCM_CAPTURE_VOLUME) + { + audio_codec_adc_set_micl_gain(ucontrol->value.integer.value[0]); + audio_codec_adc_set_micl_gain(ucontrol->value.integer.value[0]); + + } + else if (kcontrol->private_value == INNO_PCM_CAPTURE_MUTE) + { + audio_codec_adc_micl_mute(!ucontrol->value.integer.value[0]); + audio_codec_adc_micr_mute(!ucontrol->value.integer.value[0]); + } + return 0; +} + +static const struct snd_kcontrol_new inno_snd_control[] = +{ + { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "PCM Playback Volume", + .info = snd_inno_ctl_vol, + .get = snd_inno_ctl_get, + .put = snd_inno_ctl_put, + .private_value = INNO_PCM_PLAYBACK_VOLUME, + }, + { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "PCM Playback Switch", + .info = snd_inno_ctl_vol, + .get = snd_inno_ctl_get, + .put = snd_inno_ctl_put, + .private_value = INNO_PCM_PLAYBACK_MUTE, + }, + { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Mic Capture Volume", + .info = snd_inno_ctl_vol, + .get = snd_inno_ctl_get, + .put = snd_inno_ctl_put, + .private_value = INNO_PCM_CAPTURE_VOLUME, + }, + { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Mic Capture Switch", + .info = snd_inno_ctl_vol, + .get = snd_inno_ctl_get, + .put = snd_inno_ctl_put, + .private_value = INNO_PCM_CAPTURE_MUTE, + }, + +}; + + +static int k230_inno_codec_probe(struct snd_soc_component *component) +{ + snd_soc_add_component_controls(component, inno_snd_control,ARRAY_SIZE(inno_snd_control)); + return 0; +} + +static void k230_inno_codec_remove(struct snd_soc_component *component) +{ + +} + +static int k230_inno_codec_set_bias_level(struct snd_soc_component *component, + enum snd_soc_bias_level level) +{ + return 0; +} + +static const struct snd_soc_dapm_route k230_inno_codec_dapm_routes[] = { + // {"DACL VREF", NULL, "DAC PWR"}, + // {"DACR VREF", NULL, "DAC PWR"}, + // {"DACL HiLo VREF", NULL, "DAC PWR"}, + // {"DACR HiLo VREF", NULL, "DAC PWR"}, + // {"DACL CLK", NULL, "DAC PWR"}, + // {"DACR CLK", NULL, "DAC PWR"}, +}; + +static const struct snd_soc_dapm_widget k230_inno_codec_dapm_widgets[] = { +}; + +static int k230_inno_codec_open(struct snd_soc_component *component, + struct snd_pcm_substream *substream) +{ + //printk("=========k230_inno_codec_open\n"); + return 0; +} + +static const struct snd_soc_component_driver k230_inno_codec_driver = { + .open = k230_inno_codec_open, + .probe = k230_inno_codec_probe, + .remove = k230_inno_codec_remove, + .set_bias_level = k230_inno_codec_set_bias_level, + .dapm_routes = k230_inno_codec_dapm_routes, + .num_dapm_routes = ARRAY_SIZE(k230_inno_codec_dapm_routes), + .dapm_widgets = k230_inno_codec_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(k230_inno_codec_dapm_widgets), + .idle_bias_on = 1, + .use_pmdown_time = 1, + .endianness = 1, + .non_legacy_dai_naming = 1, +}; + +static int k230_inno_codec_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) +{ + return 0; +} + +static int k230_inno_codec_dai_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *hw_params, + struct snd_soc_dai *dai) +{ + struct k230_inno_codec_priv *priv = snd_soc_dai_get_drvdata(dai); + uint32_t i2s_ws = 16; + uint32_t sample_rate = 0; + uint32_t chn_cnt = 0; + int ret = 0; + struct snd_soc_component *component = dai->component; + + //clock init + sample_rate = params_rate(hw_params); + //adc or dac init + switch (params_format(hw_params)) + { + case SNDRV_PCM_FORMAT_S16_LE: + i2s_ws = 16; + break; + case SNDRV_PCM_FORMAT_S24_LE: + i2s_ws = 24; + break; + case SNDRV_PCM_FORMAT_S32_LE: + i2s_ws = 32; + break; + default: + dev_err(component->dev, "k230_inno_codec: unsupported PCM fmt"); + return -EINVAL; + } + + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) + { + //adc clock init + ret = clk_set_rate(priv->pclk_adc, sample_rate*256); + //printk("=====inno codec adc clock(%d) init,ret:%d\n",sample_rate*256,ret); + if (ret) { + dev_err(priv->dev, "Can't set inno codec clock rate: %d\n",ret); + return ret; + } + + audio_codec_adc_init(K_STANDARD_MODE,i2s_ws); + } + else + { + //dac clock init + ret = clk_set_rate(priv->pclk_dac, sample_rate*256); + //printk("=====inno codec dac clock(%d) init,ret:%d,i2s_ws:%d\n",sample_rate*256,ret,i2s_ws); + if (ret) { + dev_err(priv->dev, "Can't set inno codec clock rate: %d\n",ret); + return ret; + } + + audio_codec_dac_init(K_STANDARD_MODE,i2s_ws); + } + + //channel count + chn_cnt = params_channels(hw_params); + + //printk("=====k230_inno_codec_dai_hw_params capture:%d,i2s_ws:%d,samplerate:%d,chn_cnt:%d",\ + substream->stream == SNDRV_PCM_STREAM_CAPTURE,i2s_ws,sample_rate,chn_cnt); + return 0; +} + +static int k230_inno_codec_dai_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *cpu_dai) +{ + return 0; +} + +#define K230_INNO_CODEC_RATES (SNDRV_PCM_RATE_8000 | \ + SNDRV_PCM_RATE_16000 | \ + SNDRV_PCM_RATE_32000 | \ + SNDRV_PCM_RATE_44100 | \ + SNDRV_PCM_RATE_48000 ) + + +#define K230_INNO_CODEC_FMTS (SNDRV_PCM_FMTBIT_S16_LE|SNDRV_PCM_FMTBIT_S32_LE) + +static const struct snd_soc_dai_ops k230_inno_codec_dai_ops = { + .startup = k230_inno_codec_dai_startup, + .set_fmt = k230_inno_codec_dai_set_fmt, + .hw_params = k230_inno_codec_dai_hw_params, +}; + +static struct snd_soc_dai_driver k230_inno_codec_dai_driver[] = { + { + .name = "k230-inno-codec-dai", + .playback = { + .stream_name = "Playback", + .channels_min = 1, + .channels_max = 2, + .rates = K230_INNO_CODEC_RATES, + .formats = K230_INNO_CODEC_FMTS, + }, + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, + .rates = K230_INNO_CODEC_RATES, + .formats = K230_INNO_CODEC_FMTS, + }, + .ops = &k230_inno_codec_dai_ops, + .symmetric_rates = 1, + }, +}; + +static int inno_k230_codec_platform_probe(struct platform_device *pdev) +{ + struct k230_inno_codec_priv *priv; + //struct device_node *of_node = pdev->dev.of_node; + void __iomem *base; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + priv->base = base; + + priv->pclk_adc = devm_clk_get(&pdev->dev, "adc"); + if (IS_ERR(priv->pclk_adc)) + return PTR_ERR(priv->pclk_adc); + + ret = clk_prepare_enable(priv->pclk_adc); + if (ret < 0) { + dev_err(&pdev->dev, "failed to enable clk_adc\n"); + return ret; + } + + priv->pclk_dac = devm_clk_get(&pdev->dev, "dac"); + if (IS_ERR(priv->pclk_dac)) + return PTR_ERR(priv->pclk_dac); + + ret = clk_prepare_enable(priv->pclk_dac); + if (ret < 0) { + dev_err(&pdev->dev, "failed to enable clk_dac\n"); + return ret; + } + + priv->dev = &pdev->dev; + dev_set_drvdata(&pdev->dev, priv); + + ret = devm_snd_soc_register_component(&pdev->dev, &k230_inno_codec_driver, + k230_inno_codec_dai_driver, + ARRAY_SIZE(k230_inno_codec_dai_driver)); + + if (ret) { + clk_disable_unprepare(priv->pclk_adc); + clk_disable_unprepare(priv->pclk_dac); + dev_set_drvdata(&pdev->dev, NULL); + } + + audio_codec_reg_init(priv->base); + audio_codec_powerup_init(); + + return 0; +} + +static int inno_k230_codec_platform_remove(struct platform_device *pdev) +{ + return 0; +} + + +static const struct of_device_id inno_k230_codec_of_match[] = { + { .compatible = "k230,inno-codec", }, + {} +}; +MODULE_DEVICE_TABLE(of, inno_k230_codec_of_match); + +static struct platform_driver inno_k230_platform_driver = { + .driver = { + .name = "k230,inno-codec", + .of_match_table = of_match_ptr(inno_k230_codec_of_match), + }, + .probe = inno_k230_codec_platform_probe, + .remove = inno_k230_codec_platform_remove, +}; + +module_platform_driver(inno_k230_platform_driver); + +MODULE_DESCRIPTION("ASoC inno codec driver"); +MODULE_LICENSE("GPL v2"); diff --git a/src/little/linux/sound/soc/codecs/inno_k230_reg.c b/src/little/linux/sound/soc/codecs/inno_k230_reg.c new file mode 100644 index 000000000..87d57639c --- /dev/null +++ b/src/little/linux/sound/soc/codecs/inno_k230_reg.c @@ -0,0 +1,1465 @@ +#include "inno_k230_reg.h" +#include +#include +#include +#include +#include + + +typedef struct +{ + unsigned int gain_micl; + unsigned int gain_micr; + unsigned int adc_volumel; + unsigned int adc_volumer; + + unsigned int gain_alcl; + unsigned int gain_alcr; + + unsigned int gain_hpoutl; + unsigned int gain_hpoutr; + unsigned int dac_volumel; + unsigned int dac_volumer; +}acodec_sound_values; + +static acodec_sound_values g_snd_default_values; +static acodec_sound_values g_snd_current_values; + +#define AUDIO_CODEC_BASE_ADDR (0x9140E000U) +#define AUDIO_ADC_MIX 0 +#define AUDIO_ENABLE_BIST 0 +#define AUDIO_MODIFY_ADC_MIC_DB 1 // 是否修改MIC db值(默认0db) +#define AUDIO_MODIFY_ADC_ALC_DB 1 // 是否修改ALC db值(默认0db) + +#define AUDIO_MODIFY_DAC_DB 1 + +#define AUDIO_REG_CONFIG_NORMAL_DELAY 1 // 1ms +#define AUDIO_REG_CONFIG_LONG_DELAY 20 // 20ms +#define AUDIO_REG_CONFIG_LONG2_DELAY 10 // 10ms +//powerup 配置中sel_vref每次配置都要延迟20ms,adc的step1/step2，dac的step1延迟10ms，其他延迟1ms + +static volatile audio_codec_reg_s *audio_codec_reg = NULL; +//tatic rt_thread_t g_check_hp_thread = 0; +static bool g_adc_left_mute = false; +static bool g_adc_right_mute = false; +static bool g_dac_left_mute = false; +static bool g_dac_right_mute = false; + +static int _reset_snd_values(acodec_sound_values* snd_values ) +{ + snd_values->gain_micl = 0x03; + snd_values->gain_micr = 0x03; + snd_values->adc_volumel = 0xc3; + snd_values->adc_volumer = 0xc3; + +#if 0 + snd_values->gain_alcl = 0x1f; + snd_values->gain_alcr = 0x1f; +#else + snd_values->gain_alcl = 0x12; + snd_values->gain_alcr = 0x12; +#endif + + snd_values->gain_hpoutl = 0x10; + snd_values->gain_hpoutr = 0x10; + snd_values->dac_volumel = 0xf1; + snd_values->dac_volumer = 0xf1; + + return 0; +} + +static int _reset_adc_sound(void) +{ + reg_24_t reg24; + reg_27_t reg27; + reg_8_t reg8; + reg_9_t reg9; + + reg24.reg_data = readl(&audio_codec_reg->reg_24); + reg24.reg_24.gain_micl = g_snd_default_values.gain_micl; + writel(reg24.reg_data, &audio_codec_reg->reg_24); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + reg27.reg_data = readl(&audio_codec_reg->reg_27); + reg27.reg_27.gain_micr = g_snd_default_values.gain_micr; + writel(reg27.reg_data, &audio_codec_reg->reg_27); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + reg24.reg_data = readl(&audio_codec_reg->reg_24); + reg24.reg_24.gain_alcl = g_snd_default_values.gain_alcl; + writel(reg24.reg_data, &audio_codec_reg->reg_24); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + reg27.reg_data = readl(&audio_codec_reg->reg_27); + reg27.reg_27.gain_alcr = g_snd_default_values.gain_alcr; + writel(reg27.reg_data, &audio_codec_reg->reg_27); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + reg8.reg_data = readl(&audio_codec_reg->reg_08); + reg8.reg_8.adcl_vol = g_snd_default_values.adc_volumel; + writel(reg8.reg_data, &audio_codec_reg->reg_08); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + reg9.reg_data = readl(&audio_codec_reg->reg_09); + reg9.reg_9.adcr_vol = g_snd_default_values.adc_volumer; + writel(reg9.reg_data, &audio_codec_reg->reg_09); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + + return 0; +} + +static int _reset_dac_sound(void) +{ + reg_2b_t reg2b; + reg_2e_t reg2e; + reg_6_t reg6; + + reg2b.reg_data = readl(&audio_codec_reg->reg_2b); + reg2b.reg_2b.gain_hpoutl = g_snd_default_values.gain_hpoutl; + writel(reg2b.reg_data, &audio_codec_reg->reg_2b); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + reg2e.reg_data = readl(&audio_codec_reg->reg_2e); + reg2e.reg_2e.gain_hpoutr = g_snd_default_values.gain_hpoutr; + writel(reg2e.reg_data, &audio_codec_reg->reg_2e); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + reg6.reg_data = readl(&audio_codec_reg->reg_06); + reg6.reg_6.dac_vol = g_snd_default_values.dac_volumel; + reg6.reg_6.dac_vol = g_snd_default_values.dac_volumer; + writel(reg6.reg_data, &audio_codec_reg->reg_06); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + return 0; +} + +int audio_codec_reg_init(void* reg_base) +{ + if (audio_codec_reg == NULL) + { + audio_codec_reg = reg_base; + } + _reset_snd_values(&g_snd_default_values); + _reset_snd_values(&g_snd_current_values); + return 0; +} + +static volatile bool g_powerup_init = false; +void audio_codec_powerup_init(void) +{ + reg_29_t reg29; + reg_2c_t reg2c; + reg_21_t reg21; + reg_20_t reg20; + reg_0_t reg0; + int i = 0; + + if (g_powerup_init) + { + return; + } + g_powerup_init = true; + + // 0.reset the audio codec + reg0.reg_data = readl(&audio_codec_reg->reg_00); + reg0.reg_0.sys_bstn = 0; + reg0.reg_0.digcore_bstn = 0; +#if AUDIO_ENABLE_BIST + reg0.reg_0.bist_bstn = 0; +#endif + writel(reg0.reg_data, &audio_codec_reg->reg_00); + // printf("===========reset audio codec\n"); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + reg0.reg_data = readl(&audio_codec_reg->reg_00); + reg0.reg_0.sys_bstn = 1; +// reg0.reg_0.digcore_bstn = 1; +#if AUDIO_ENABLE_BIST + reg0.reg_0.bist_bstn = 1; +#endif + writel(reg0.reg_data, &audio_codec_reg->reg_00); + // printf("===========work audio codec\n"); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 1.Configure the register POP_CTRL_DACL[1:0] 0x29[5:4] to 2’b01, , to setup the output dc voltage of DAC left channel. + reg29.reg_data = readl(&audio_codec_reg->reg_29); + reg29.reg_29.pop_ctrl_dacl = 1; + writel(reg29.reg_data, &audio_codec_reg->reg_29); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 1.Configure the register POP_CTRL_DACR[1:0] 0x2c[5:4] to 2’b01, , to setup the output dc voltage of DAC right channel. + reg2c.reg_data = readl(&audio_codec_reg->reg_2c); + reg2c.reg_2c.pop_ctrl_dacr = 1; + writel(reg2c.reg_data, &audio_codec_reg->reg_2c); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 2.Configure the register SEL_VREF[7:0] reg0x21[7:0] to 8’b000_0001. + reg21.reg_data = readl(&audio_codec_reg->reg_21); + reg21.reg_21.sel_vref = 1; + writel(reg21.reg_data, &audio_codec_reg->reg_21); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 3.Supply the power of the analog part . + + // 4.Configure the register EN_VREF reg0x20[6] to 1 to setup reference voltage + reg20.reg_data = readl(&audio_codec_reg->reg_20); + reg20.reg_20.en_vref = 1; + writel(reg20.reg_data, &audio_codec_reg->reg_20); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 5.Change the register SEL_VREF[7:0] reg0x21[7:0] :configure the reg0x21[7:0] to 7’b1111_1111 directly. +#if 0 + reg21.reg_data = readl(&audio_codec_reg->reg_21); + reg21.reg_21.sel_vref = 0xff; + writel(reg21.reg_data,&audio_codec_reg->reg_21); + msleep(20); +#else + for (i = 0; i < 8; i++) + { + reg21.reg_data = readl(&audio_codec_reg->reg_21); + if (0 == i) + { + reg21.reg_21.sel_vref = 0x1; + } + else if (1 == i) + { + + reg21.reg_21.sel_vref = 0x3; + } + else if (2 == i) + { + + reg21.reg_21.sel_vref = 0x7; + } + else if (3 == i) + { + + reg21.reg_21.sel_vref = 0xf; + } + else if (4 == i) + { + + reg21.reg_21.sel_vref = 0x1f; + } + else if (5 == i) + { + + reg21.reg_21.sel_vref = 0x3f; + } + else if (6 == i) + { + + reg21.reg_21.sel_vref = 0x7f; + } + else if (7 == i) + { + + reg21.reg_21.sel_vref = 0xff; + } + writel(reg21.reg_data, &audio_codec_reg->reg_21); + msleep(AUDIO_REG_CONFIG_LONG_DELAY); + } + +#endif + + // 6.Wait until the voltage of VCM keeps stable at the AVDD/2. + + // 7.Configure the register SEL_VREF[7:0] reg0x21[7:0] to the appropriate value(except 7’b0000_00000) for reducing power + reg21.reg_data = readl(&audio_codec_reg->reg_21); + reg21.reg_21.sel_vref = 0x02; + writel(reg21.reg_data, &audio_codec_reg->reg_21); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + msleep(2000); //delay to prevent ADC from generating noise +} + + +static int audio_reset_micbias(void) +{ + int delay_milli_sec = 100; + //acodec_err_trace("=========audio_reset_micbias:%d ms\n",delay_milli_sec); + reg_20_t reg20; + reg20.reg_data = readl(&audio_codec_reg->reg_20); + reg20.reg_20.en_micbias = 0; + writel(reg20.reg_data, &audio_codec_reg->reg_20); + msleep(delay_milli_sec); + + reg20.reg_data = readl(&audio_codec_reg->reg_20); + reg20.reg_20.en_micbias = 1; + writel(reg20.reg_data, &audio_codec_reg->reg_20); + + return 0; +} + +// #define ACODEC_ADC_CHANNEL 5 +// static bool g_hp_insert_det = false; +// static void _check_adc_hp_thread(void *parameter) +// { +// rt_adc_device_t adc_dev; +// rt_uint32_t reg_value = 0; + +// while(1) +// { +// adc_dev = (rt_adc_device_t)rt_device_find("adc"); +// if (adc_dev == RT_NULL) +// { +// acodec_err_trace("rt_device_find adc failed\n"); +// msleep(500); +// continue; +// } +// rt_adc_enable(adc_dev, ACODEC_ADC_CHANNEL); +// break; +// } + +// bool first_check = true; +// while(1) +// { +// reg_value = rt_adc_read(adc_dev, ACODEC_ADC_CHANNEL); +// if (reg_value > 100) +// { +// if (first_check) +// { +// g_hp_insert_det = true; +// audio_codec_adc_hp_work(g_hp_insert_det); +// first_check = false; +// } +// else +// { +// if (!g_hp_insert_det) +// { +// g_hp_insert_det = true; +// audio_codec_adc_hp_work(g_hp_insert_det); +// } +// } +// } +// else +// { +// if (first_check) +// { +// g_hp_insert_det = false; +// audio_codec_adc_hp_work(g_hp_insert_det); +// first_check = false; +// } +// else +// { +// if (g_hp_insert_det) +// { +// g_hp_insert_det = false; +// audio_codec_adc_hp_work(g_hp_insert_det); +// } +// } +// } +// msleep(500); +// } +// } + +static volatile bool g_adc_sound_init = false; +void audio_codec_adc_init(k_i2s_work_mode mode, unsigned int i2s_ws) +{ + reg_24_t reg24; + reg_27_t reg27; + reg_20_t reg20; + reg_23_t reg23; + reg_26_t reg26; + reg_25_t reg25; + reg_28_t reg28; + reg_4_t reg4; + //reg_8_t reg8; + //reg_9_t reg9; + //reg_2_t reg2; + reg_0_t reg0; + + // 1.Configure the register MUTE_MICL 0x24[7] to 1, to end the mute station of the left ADC channel. + reg24.reg_data = readl(&audio_codec_reg->reg_24); + reg24.reg_24.mute_micl = 1; + writel(reg24.reg_data, &audio_codec_reg->reg_24); + msleep(AUDIO_REG_CONFIG_LONG2_DELAY); + + // 1.Configure the register MUTE_MICR 0x27[7] to 1, to end the mute station of the left ADC channel + reg27.reg_data = readl(&audio_codec_reg->reg_27); + reg27.reg_27.mute_micr = 1; + writel(reg27.reg_data, &audio_codec_reg->reg_27); + msleep(AUDIO_REG_CONFIG_LONG2_DELAY); + + // 2.Configure the register EN_IBIAS_ADC 0x20[5] to 1, to enable the current source of ADC. + reg20.reg_data = readl(&audio_codec_reg->reg_20); + reg20.reg_20.en_ibias_adc = 1; + reg20.reg_20.en_micbias = 1; + writel(reg20.reg_data, &audio_codec_reg->reg_20); + msleep(AUDIO_REG_CONFIG_LONG2_DELAY); + + // 3.Configure the register EN_BUF_ADCL 0x23[7] to 1, to enable the reference voltage buffer in ADC left channel. + reg23.reg_data = readl(&audio_codec_reg->reg_23); + reg23.reg_23.en_buf_adcl = 1; + writel(reg23.reg_data, &audio_codec_reg->reg_23); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 3.Configure the register EN_BUF_ADCR 0x26[7] to 1, to enable the reference voltage buffer in ADC right channel. + reg26.reg_data = readl(&audio_codec_reg->reg_26); + reg26.reg_26.en_buf_adcr = 1; + writel(reg26.reg_data, &audio_codec_reg->reg_26); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 4.Configure the register EN_MICL 0x23[6] to 1, to enable the MIC module in ADC left channel. + reg23.reg_data = readl(&audio_codec_reg->reg_23); + reg23.reg_23.en_micl = 1; + writel(reg23.reg_data, &audio_codec_reg->reg_23); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 4.Configure the register EN_MICR 0x26[6] to 1, to enable the MIC module in ADC right channel. + reg26.reg_data = readl(&audio_codec_reg->reg_26); + reg26.reg_26.en_micr = 1; + writel(reg26.reg_data, &audio_codec_reg->reg_26); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 5.Configure the register EN_ALCL 0x23[5] to 1, to enable the ALC module in ADC left channel + reg23.reg_data = readl(&audio_codec_reg->reg_23); + reg23.reg_23.en_alcl = 1; + writel(reg23.reg_data, &audio_codec_reg->reg_23); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 5.Configure the register EN_ALCR 0x26[5] to 1, to enable the ALC module in ADC right channel. + reg26.reg_data = readl(&audio_codec_reg->reg_26); + reg26.reg_26.en_alcr = 1; + writel(reg26.reg_data, &audio_codec_reg->reg_26); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 6.Configure the register EN_CLK_ADCL 0x23[4] to 1, to enable the clock module in ADC left channel. + reg23.reg_data = readl(&audio_codec_reg->reg_23); + reg23.reg_23.en_clk_adcl = 1; + writel(reg23.reg_data, &audio_codec_reg->reg_23); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 6.Configure the register EN_CLK_ADCR 0x26[4] to 1, to enable the clock module in ADC right channel. + reg26.reg_data = readl(&audio_codec_reg->reg_26); + reg26.reg_26.en_clk_adcr = 1; + writel(reg26.reg_data, &audio_codec_reg->reg_26); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 7.Configure the register EN_ADCL 0x23[3] to 1, to enable the ADC module in ADC left channel. + reg23.reg_data = readl(&audio_codec_reg->reg_23); + reg23.reg_23.en_adcl = 1; + writel(reg23.reg_data, &audio_codec_reg->reg_23); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 7.Configure the register EN_ADCR 0x26[3] to 1, to enable the ADC module in ADC right channel. + reg26.reg_data = readl(&audio_codec_reg->reg_26); + reg26.reg_26.en_adcr = 1; + writel(reg26.reg_data, &audio_codec_reg->reg_26); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + ////////////////////////////////////////////////////////////////////////////////////////////// + // i2s rx word length + + reg4.reg_data = readl(&audio_codec_reg->reg_04); + if (i2s_ws == 24) + { + // reg4.reg_4.i2s_rx_wl = 3;//32 + reg4.reg_4.i2s_rx_wl = 2; // 24 + } + else if (i2s_ws == 16) + { + reg4.reg_4.i2s_rx_wl = 0; // 16 + } + else if (i2s_ws == 32) + { + reg4.reg_4.i2s_rx_wl = 3;//32 + } + + writel(reg4.reg_data, &audio_codec_reg->reg_04); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // i2s rx fmt + reg4.reg_data = readl(&audio_codec_reg->reg_04); + if (K_STANDARD_MODE == mode) + { + reg4.reg_4.i2s_rx_fmt = 2; + } + else if (K_RIGHT_JUSTIFYING_MODE == mode) + { + reg4.reg_4.i2s_rx_fmt = 0; + } + else if (K_LEFT_JUSTIFYING_MODE == mode) + { + reg4.reg_4.i2s_rx_fmt = 1; + } + + writel(reg4.reg_data, &audio_codec_reg->reg_04); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + +#if AUDIO_ADC_MIX + reg2.reg_data = readl(&audio_codec_reg->reg_02); + + // reg2.reg_2.i2s_tx_datsel = 2;//mix right data + reg2.reg_2.i2s_tx_datsel = 1; // mix left data + writel(reg2.reg_data, &audio_codec_reg->reg_02); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + +#endif + + ///////////////////////////////////////////////////////////////////////////////////////////////// + + // 8.Configure the register INITIAL_ADCL 0x23[2] to 1, to end the initialization of the ADCL module. + reg23.reg_data = readl(&audio_codec_reg->reg_23); + reg23.reg_23.initial_adcl = 1; + writel(reg23.reg_data, &audio_codec_reg->reg_23); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 8.Configure the register INITIAL_ADCR 0x26[2] to 1, to end the initialization of the ADCR module. + reg26.reg_data = readl(&audio_codec_reg->reg_26); + reg26.reg_26.initial_adcr = 1; + writel(reg26.reg_data, &audio_codec_reg->reg_26); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 9.Configure the register INITIAL_ALCL 0x23[1] to 1, to end the initialization of the left ALC module. + reg23.reg_data = readl(&audio_codec_reg->reg_23); + reg23.reg_23.initial_alcl = 1; + writel(reg23.reg_data, &audio_codec_reg->reg_23); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 9.Configure the register INITIAL_ALCR 0x26[1] to 1, to end the initialization of the right ALC module. + reg26.reg_data = readl(&audio_codec_reg->reg_26); + reg26.reg_26.initial_alcr = 1; + writel(reg26.reg_data, &audio_codec_reg->reg_26); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 10.Configure the register INITIAL_MICL 0x23[0] to 1, to end the initialization of theleft MIC module. + reg23.reg_data = readl(&audio_codec_reg->reg_23); + reg23.reg_23.initial_micl = 1; + writel(reg23.reg_data, &audio_codec_reg->reg_23); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 10.Configure the register INITIAL_MICR 0x26[0] to 1, to end the initialization of the right MIC module. + reg26.reg_data = readl(&audio_codec_reg->reg_26); + reg26.reg_26.initial_micr = 1; + writel(reg26.reg_data, &audio_codec_reg->reg_26); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + +#if 0 + //11.Configure the register MUTE_MICL 0x24[7] to 1, to end the mute station of the ADC left channel. + reg24.reg_data = readl(&audio_codec_reg->reg_24); + reg24.reg_24.mute_micl = 1; + writel(reg24.reg_data,&audio_codec_reg->reg_24); + + //11.Configure the register MUTE_MICR 0x27[7] to 1, to end the mute station of the ADC right channel. + reg27.reg_data = readl(&audio_codec_reg->reg_27); + reg27.reg_27.mute_micr = 1; + writel(reg27.reg_data,&audio_codec_reg->reg_27); +#endif + + if (!g_adc_sound_init) + { + _reset_adc_sound(); + g_adc_sound_init = true; + } + + // 14.Configure the register EN_ZeroDET_ADCL 0x25[1] to 1, to enable the zerocrossing detection function in ADC left channel. + reg25.reg_data = readl(&audio_codec_reg->reg_25); + reg25.reg_25.en_zerodet_adcl = 1; + writel(reg25.reg_data, &audio_codec_reg->reg_25); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 14.Configure the register EN_ZeroDET_ADCR 0x28[1] to 1, to enable the zerocrossing detection function in ADC right channel + reg28.reg_data = readl(&audio_codec_reg->reg_28); + reg28.reg_28.en_zerodet_adcr = 1; + writel(reg28.reg_data, &audio_codec_reg->reg_28); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + reg0.reg_data = readl(&audio_codec_reg->reg_00); + reg0.reg_0.digcore_bstn = 1; + writel(reg0.reg_data, &audio_codec_reg->reg_00); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // if (0 == g_check_hp_thread) + // { + // g_check_hp_thread = rt_thread_create("acodec_hp", _check_adc_hp_thread, RT_NULL, 1024*10, 10,10); + // rt_thread_startup(g_check_hp_thread); + // } + + audio_reset_micbias(); +} + +static volatile bool g_dac_sound_init = false; +void audio_codec_dac_init(k_i2s_work_mode mode, unsigned int i2s_ws) +{ + reg_20_t reg20; + reg_29_t reg29; + reg_2c_t reg2c; + reg_2a_t reg2a; + reg_2d_t reg2d; + //reg_2b_t reg2b; + //reg_2e_t reg2e; + reg_2_t reg2; + reg_3_t reg3; + //reg_1_t reg1; + //reg_6_t reg6; + //reg_7_t reg7; + reg_0_t reg0; + + // 1.Configure the register EN_IBIAS_DAC 0x20[4] to 1, to enable the current source of DAC. + reg20.reg_data = readl(&audio_codec_reg->reg_20); + reg20.reg_20.en_ibias_dac = 1; + writel(reg20.reg_data, &audio_codec_reg->reg_20); + msleep(AUDIO_REG_CONFIG_LONG2_DELAY); + + // 2.Configure the register EN_BUF_DACL 0x29[6] to 1, to enable the reference voltage buffer of the DAC left channel + reg29.reg_data = readl(&audio_codec_reg->reg_29); + reg29.reg_29.en_buf_dacl = 1; + writel(reg29.reg_data, &audio_codec_reg->reg_29); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 2.Configure the register EN_BUF_DACR 0x2c[6] to 1, to enable the reference voltage buffer of the DAC right channel. + reg2c.reg_data = readl(&audio_codec_reg->reg_2c); + reg2c.reg_2c.en_buf_dacr = 1; + writel(reg2c.reg_data, &audio_codec_reg->reg_2c); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 3.Configure the register POP_CTRL_DACL<1:0> 0x29[5:4] to 2’b10, to enable POP sound in the DAC left channel. + reg29.reg_data = readl(&audio_codec_reg->reg_29); + reg29.reg_29.pop_ctrl_dacl = 2; + writel(reg29.reg_data, &audio_codec_reg->reg_29); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 3.Configure the register POP_CTRL_DACR<1:0> 0x2c[5:4] to 2’b10, to enable POP sound in the DAC right channel + reg2c.reg_data = readl(&audio_codec_reg->reg_2c); + reg2c.reg_2c.pop_ctrl_dacr = 2; + writel(reg2c.reg_data, &audio_codec_reg->reg_2c); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 4.Configure the register EN_HPOUTL 0x2a[5] to 1, to enable the HPDRV module in the DAC left channel + reg2a.reg_data = readl(&audio_codec_reg->reg_2a); + reg2a.reg_2a.en_hpoutl = 1; + writel(reg2a.reg_data, &audio_codec_reg->reg_2a); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 4.Configure the register EN_HPOUTR 0x2d[5] to 1, to enable the HPDRV module in the DAC right channel + reg2d.reg_data = readl(&audio_codec_reg->reg_2d); + reg2d.reg_2d.en_hpoutr = 1; + writel(reg2d.reg_data, &audio_codec_reg->reg_2d); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + +#if AUDIO_ENABLE_BIST + reg7.reg_data = readl(&audio_codec_reg->reg_07); + reg7.reg_7.dacl_bist_sel = 1; + reg7.reg_7.dacr_bist_sel = 1; + writel(reg7.reg_data, &audio_codec_reg->reg_07); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); +#endif + + // 5.Configure the register INITIAL_HPOUTL 0x2a[4] to 1, to end the initialization of the HPDRV module in the DAC left channel. + reg2a.reg_data = readl(&audio_codec_reg->reg_2a); + reg2a.reg_2a.initial_hpoutl = 1; + writel(reg2a.reg_data, &audio_codec_reg->reg_2a); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 5.Configure the register INITIAL_HPOUTR 0x2d[4] to 1, to end the initialization of the HPDRV module in the DAC right channel. + reg2d.reg_data = readl(&audio_codec_reg->reg_2d); + reg2d.reg_2d.initial_hpoutr = 1; + writel(reg2d.reg_data, &audio_codec_reg->reg_2d); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 6.Configure the register EN_VREF_DACL 0x29[3] to 1, to enable the reference voltage of DACL module + reg29.reg_data = readl(&audio_codec_reg->reg_29); + reg29.reg_29.en_vref_dacl = 1; + writel(reg29.reg_data, &audio_codec_reg->reg_29); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 6.Configure the register EN_VREF_DACR 0x2c[3] to 1, to enable the reference voltage of DACR module. + reg2c.reg_data = readl(&audio_codec_reg->reg_2c); + reg2c.reg_2c.en_vref_dacr = 1; + writel(reg2c.reg_data, &audio_codec_reg->reg_2c); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 7.Configure the register EN_CLK_DACL 0x29[2] to 1, to enable the clock module of DACL module. + reg29.reg_data = readl(&audio_codec_reg->reg_29); + reg29.reg_29.en_clk_dacl = 1; + writel(reg29.reg_data, &audio_codec_reg->reg_29); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 7.Configure the register EN_CLK_DACR 0x2c[2] to 1, to enable the clock module of DACR module. + reg2c.reg_data = readl(&audio_codec_reg->reg_2c); + reg2c.reg_2c.en_clk_dacr = 1; + writel(reg2c.reg_data, &audio_codec_reg->reg_2c); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 8.Configure the register EN_DACL 0x29[1] to 1, to enable the DACL module. + reg29.reg_data = readl(&audio_codec_reg->reg_29); + reg29.reg_29.en_dacl = 1; + writel(reg29.reg_data, &audio_codec_reg->reg_29); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 8.Configure the register EN_DACR 0x2c[1] to 1, to enable the DACR module. + reg2c.reg_data = readl(&audio_codec_reg->reg_2c); + reg2c.reg_2c.en_dacr = 1; + writel(reg2c.reg_data, &audio_codec_reg->reg_2c); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + ////////////////////////////////////////////////////////////////////////////////////////////// + // i2s tx word length + reg2.reg_data = readl(&audio_codec_reg->reg_02); + + if (i2s_ws == 24) + { + // reg2.reg_2.i2s_tx_wl = 3;//valid 32 bit + reg2.reg_2.i2s_tx_wl = 2; // valid 24 bit + } + else if (i2s_ws == 16) + { + reg2.reg_2.i2s_tx_wl = 0; // valid 16 bit + } + else if (i2s_ws == 32) + { + reg2.reg_2.i2s_tx_wl = 3;//valid 32 bit + } + + //reg2.reg_2.i2s_tx_datsel = 2; + writel(reg2.reg_data, &audio_codec_reg->reg_02); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // i2s tx fmt + reg2.reg_data = readl(&audio_codec_reg->reg_02); + if (K_STANDARD_MODE == mode) + { + reg2.reg_2.i2s_tx_fmt = 2; + } + else if (K_RIGHT_JUSTIFYING_MODE == mode) + { + reg2.reg_2.i2s_tx_fmt = 0; + } + else if (K_LEFT_JUSTIFYING_MODE == mode) + { + reg2.reg_2.i2s_tx_fmt = 1; + } + + writel(reg2.reg_data, &audio_codec_reg->reg_02); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + reg3.reg_data = readl(&audio_codec_reg->reg_03); + reg3.reg_3.i2s_tx_len = 3; // 32 bit + writel(reg3.reg_data, &audio_codec_reg->reg_03); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + ///////////////////////////////////////////////////////////////////////////////////////////////// + + // 9.Configure the register INITIAL_DACL 0x29[0] to 1, to end the initialization of the DACL module. + reg29.reg_data = readl(&audio_codec_reg->reg_29); + reg29.reg_29.initial_dacl = 1; + writel(reg29.reg_data, &audio_codec_reg->reg_29); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 9.Configure the register INITIAL_DACR 0x2c[0] to 1, to end the initialization of the DACR module. + reg2c.reg_data = readl(&audio_codec_reg->reg_2c); + reg2c.reg_2c.initial_dacr = 1; + writel(reg2c.reg_data, &audio_codec_reg->reg_2c); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 10.Configure the register MUTE_HPOUTL 0x29[7] to 1, to end the mute station of the HPDRV module in the DAC left channel + reg29.reg_data = readl(&audio_codec_reg->reg_29); + reg29.reg_29.mute_hpoutl = 1; + writel(reg29.reg_data, &audio_codec_reg->reg_29); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // 10.Configure the register MUTE_HPOUTR 0x2c[7] to 1, to end the mute station of the HPDRV module in the DAC right channel. + reg2c.reg_data = readl(&audio_codec_reg->reg_2c); + reg2c.reg_2c.mute_hpoutr = 1; + writel(reg2c.reg_data, &audio_codec_reg->reg_2c); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + if (!g_dac_sound_init) + { + _reset_dac_sound(); + g_dac_sound_init = true; + } + + reg0.reg_data = readl(&audio_codec_reg->reg_00); + reg0.reg_0.digcore_bstn = 1; + writel(reg0.reg_data, &audio_codec_reg->reg_00); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + +} + +static int convert_adc_gain(unsigned int gain, unsigned int *reg_val) +{ + unsigned int reg_value = 0; + if (gain > 30 || gain < 0) + { + return -1; + } + + if (0 == gain) + { + reg_value = 0; + } + else if (gain >0 && gain <= 10) + { + reg_value = 1; + } + else if (gain > 10 && gain <= 20) + { + reg_value = 2; + } + else if (gain > 20 && gain <= 30) + { + reg_value = 3; + } + + *reg_val = reg_value; + + return 0; +} + +static int convert_adc_gain_2(unsigned int reg_val, unsigned int *gain) +{ + unsigned int gain_value = 0; + + if (reg_val > 3 || reg_val < 0) + { + return -1; + } + + if (0 == reg_val) + { + gain_value = 0; + } + else if (1 == reg_val) + { + gain_value = 6; + } + else if (2 == reg_val) + { + gain_value = 20; + } + else if (3 == reg_val) + { + gain_value = 30; + } + + *gain = gain_value; + + return 0; +} + +int audio_codec_adc_set_micl_gain(int gain) +{ + reg_24_t reg24; + unsigned int reg_val = 0; + + printk("audio_codec_adc_set_micl_gain gain:%d\n", gain); + if (0 != convert_adc_gain(gain, ®_val)) + { + return -1; + } + + reg24.reg_data = readl(&audio_codec_reg->reg_24); + reg24.reg_24.gain_micl = reg_val; + writel(reg24.reg_data, &audio_codec_reg->reg_24); + g_snd_current_values.gain_micl = reg_val; + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + return 0; +} + +int audio_codec_adc_set_micr_gain(int gain) +{ + unsigned int reg_val = 0; + reg_27_t reg27; + + printk("audio_codec_adc_set_micr_gain gain:%d\n", gain); + if (0 != convert_adc_gain(gain, ®_val)) + { + return -1; + } + + reg27.reg_data = readl(&audio_codec_reg->reg_27); + reg27.reg_27.gain_micr = reg_val; + writel(reg27.reg_data, &audio_codec_reg->reg_27); + g_snd_current_values.gain_micr = reg_val; + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + return 0; +} + +int audio_codec_adc_get_micl_gain(int* gain) +{ + return convert_adc_gain_2(g_snd_current_values.gain_micl,gain); +} + + +int audio_codec_adc_get_micr_gain( int* gain) +{ + return convert_adc_gain_2(g_snd_current_values.gain_micr,gain); +} + + +// static int convert_adc_volume(float volume, unsigned int *reg_val) +// { +// unsigned int reg_value = 0; +// float start_gain = -97; +// bool bfind = false; +// int i = 0; + +// if (volume < -97 || volume > 30) +// { +// return -1; +// } + +// for (i = 0x1; i <= 0xff; i++) +// { +// if (volume == start_gain) +// { +// reg_value = i; +// bfind = true; +// break; +// } +// else +// { +// start_gain += 0.5; +// } +// } +// if (!bfind) +// { +// return -1; +// } + +// *reg_val = reg_value; + +// return 0; +// } + +// static int convert_adc_volume2(unsigned int reg_val,float* volume) +// { +// float start_gain = -97; +// bool bfind = false; +// int i =0; + +// if (reg_val < 1 || reg_val > 0xff) +// { +// return -1; +// } + +// for (i = 0x1; i <= 0xff; i++) +// { +// if (reg_val == i) +// { +// bfind = true; +// break; +// } +// else +// { +// start_gain += 0.5; +// } +// } +// if (!bfind) +// { +// return -1; +// } + +// *volume = start_gain; + +// return 0; +// } + +// int audio_codec_adcl_set_volume(float volume) +// { +// unsigned int reg_val = 0; +// reg_8_t reg8; + +// if (0 != convert_adc_volume(volume, ®_val)) +// { +// return -1; +// } + +// reg8.reg_data = readl(&audio_codec_reg->reg_08); +// reg8.reg_8.adcl_vol = reg_val; +// writel(reg8.reg_data, &audio_codec_reg->reg_08); +// g_snd_current_values.adc_volumel = reg_val; +// msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); +// return 0; +// } +// int audio_codec_adcr_set_volume(float volume) +// { +// unsigned int reg_val = 0; +// reg_9_t reg9; + +// if (0 != convert_adc_volume(volume, ®_val)) +// { +// return -1; +// } + +// reg9.reg_data = readl(&audio_codec_reg->reg_09); +// reg9.reg_9.adcr_vol = reg_val; +// writel(reg9.reg_data, &audio_codec_reg->reg_09); +// g_snd_current_values.adc_volumer = reg_val; +// msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); +// return 0; +// } + +// int audio_codec_adcl_get_volume(float* volume) +// { +// return convert_adc_volume2(g_snd_current_values.adc_volumel, volume); +// } +// int audio_codec_adcr_get_volume(float* volume) +// { +// return convert_adc_volume2(g_snd_current_values.adc_volumer, volume); +// } + +int audio_codec_adc_micl_mute(bool mute) +{ + reg_24_t reg24; + + printk("audio_codec_adc_micl_mute mute:%d\n", mute); + reg24.reg_data = readl(&audio_codec_reg->reg_24); + reg24.reg_24.mute_micl = mute ? 0 : 1; + writel(reg24.reg_data, &audio_codec_reg->reg_24); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + g_adc_left_mute = mute; + return 0; +} + +int audio_codec_adc_micr_mute(bool mute) +{ + reg_27_t reg27; + printk("audio_codec_adc_micr_mute mute:%d\n", mute); + reg27.reg_data = readl(&audio_codec_reg->reg_27); + reg27.reg_27.mute_micr = mute ? 0 : 1; + writel(reg27.reg_data, &audio_codec_reg->reg_27); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + g_adc_right_mute = mute; + return 0; +} + +int audio_codec_adc_get_micl_mute(bool* mute) +{ + *mute = g_adc_left_mute; + return 0; +} + +int audio_codec_adc_get_micr_mute(bool* mute) +{ + *mute = g_adc_right_mute; + return 0; +} + +// static int convert_alc_gain(float gain, unsigned int *reg_val) +// { +// unsigned int reg_value = 0; +// float start_gain = -18; +// bool bfind = false; +// int i = 0; + +// if (gain < -18 || gain > 28.5) +// { +// return -1; +// } + +// for (i = 0; i <= 0x1f; i++) +// { +// if (gain == start_gain) +// { +// reg_value = i; +// bfind = true; +// break; +// } +// else +// { +// start_gain += 1.5; +// } +// } +// if (!bfind) +// { +// return -1; +// } + +// *reg_val = reg_value; + +// return 0; +// } + +// static int convert_alc_gain2(unsigned int reg_val,float* gain) +// { +// float start_gain = -18; +// bool bfind = false; +// int i =0; + +// if (reg_val < 0 || reg_val > 0x1f) +// { +// return -1; +// } + +// for (i = 0; i <= 0x1f; i++) +// { +// if (reg_val == i) +// { +// bfind = true; +// break; +// } +// else +// { +// start_gain += 1.5; +// } +// } +// if (!bfind) +// { +// return -1; +// } + +// *gain = start_gain; + +// return 0; +// } + +// int audio_codec_alc_set_micl_gain(float gain) +// { +// unsigned int reg_val = 0; +// reg_24_t reg24; +// //acodec_err_trace("audio_codec_alc_set_micl_gain gain:%.2f\n", gain); + +// if (0 != convert_alc_gain(gain, ®_val)) +// { +// return -1; +// } + +// reg24.reg_data = readl(&audio_codec_reg->reg_24); +// reg24.reg_24.gain_alcl = reg_val; +// writel(reg24.reg_data, &audio_codec_reg->reg_24); +// g_snd_current_values.gain_alcl = reg_val; +// msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + +// return 0; +// } + +// int audio_codec_alc_set_micr_gain(float gain) +// { +// reg_27_t reg27; +// int reg_val = 0; +// //acodec_err_trace("audio_codec_alc_set_micr_gain gain:%.2f\n", gain); + +// if (0 != convert_alc_gain(gain, ®_val)) +// { +// return -1; +// } + +// reg27.reg_data = readl(&audio_codec_reg->reg_27); +// reg27.reg_27.gain_alcr = reg_val; +// writel(reg27.reg_data, &audio_codec_reg->reg_27); +// g_snd_current_values.gain_alcr = reg_val; +// msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + +// return 0; +// } + +// int audio_codec_alc_get_micl_gain(float* gain) +// { +// return convert_alc_gain2(g_snd_current_values.gain_alcl, gain); +// } + +// int audio_codec_alc_get_micr_gain(float* gain) +// { +// return convert_alc_gain2(g_snd_current_values.gain_alcr, gain); +// } + +static int convert_dac_gain(int gain, unsigned int *reg_val) +{ + unsigned int reg_value = 0; + int start_gain = -39; + bool bfind = false; + int i = 0; + + if (gain < -39 || gain > 6) + { + return -1; + } + + for (i = 0; i <= 0x1e; i+=2) // 11111/11110 both 6db + { + if (gain <= start_gain) + { + reg_value = i; + bfind = true; + break; + } + else + { + start_gain += 3; + } + } + if (!bfind) + { + return -1; + } + + *reg_val = reg_value; + + return 0; +} + +static int convert_dac_gain2(unsigned int reg_val,int* gain) +{ + int start_gain = -39; + bool bfind = false; + int i = 0; + + if (reg_val < 0 || reg_val > 0x1e) + { + return -1; + } + + for (i = 0; i <= 0x1e; i+=2) // 11111/11110 both 6db + { + if (reg_val == i) + { + bfind = true; + break; + } + else + { + start_gain += 3; + } + } + if (!bfind) + { + return -1; + } + + *gain = start_gain; + + return 0; +} + +int audio_codec_dac_set_hpoutl_gain(int gain) +{ + unsigned int reg_val = 0; + reg_2b_t reg2b; + + if (0 != convert_dac_gain(gain, ®_val)) + { + return -1; + } + + reg2b.reg_data = readl(&audio_codec_reg->reg_2b); + + reg2b.reg_2b.gain_hpoutl = reg_val; + writel(reg2b.reg_data, &audio_codec_reg->reg_2b); + g_snd_current_values.gain_hpoutl = reg_val; + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + return 0; +} + +int audio_codec_dac_set_hpoutr_gain(int gain) +{ + unsigned int reg_val = 0; + reg_2e_t reg2e; + + if (0 != convert_dac_gain(gain, ®_val)) + { + return -1; + } + + reg2e.reg_data = readl(&audio_codec_reg->reg_2e); + reg2e.reg_2e.gain_hpoutr = reg_val; // 最大db值 + writel(reg2e.reg_data, &audio_codec_reg->reg_2e); + g_snd_current_values.gain_hpoutr = reg_val; + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + return 0; +} + +int audio_codec_dac_get_hpoutl_gain(int* gain) +{ + return convert_dac_gain2( g_snd_current_values.gain_hpoutl,gain); +} + +int audio_codec_dac_get_hpoutr_gain(int* gain) +{ + return convert_dac_gain2( g_snd_current_values.gain_hpoutr,gain); +} + +int audio_codec_dac_hpoutl_mute(bool mute) +{ + reg_29_t reg29; + reg_2a_t reg2a; + + reg29.reg_data = readl(&audio_codec_reg->reg_29); + reg29.reg_29.mute_hpoutl = mute ? 0 : 1; + writel(reg29.reg_data, &audio_codec_reg->reg_29); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // MUTE的同时将INITIAL_HPOUTL也置0即可（gain 无需修改） + reg2a.reg_data = readl(&audio_codec_reg->reg_2a); + reg2a.reg_2a.initial_hpoutl = mute ? 0 : 1; + writel(reg2a.reg_data, &audio_codec_reg->reg_2a); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + g_dac_left_mute = mute; + return 0; +} +int audio_codec_dac_hpoutr_mute(bool mute) +{ + reg_2c_t reg2c; + reg_2d_t reg2d; + + reg2c.reg_data = readl(&audio_codec_reg->reg_2c); + reg2c.reg_2c.mute_hpoutr = mute ? 0 : 1; + writel(reg2c.reg_data, &audio_codec_reg->reg_2c); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + // MUTE的同时将INITIAL_HPOUTR也置0即可（gain 无需修改） + reg2d.reg_data = readl(&audio_codec_reg->reg_2d); + reg2d.reg_2d.initial_hpoutr = mute ? 0 : 1; + writel(reg2d.reg_data, &audio_codec_reg->reg_2d); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + g_dac_right_mute = mute; + return 0; +} + +int audio_codec_dac_get_hpoutl_mute(bool* mute) +{ + *mute = g_dac_left_mute; + return 0; +} + +int audio_codec_dac_get_hpoutr_mute(bool* mute) +{ + *mute = g_dac_left_mute; + return 0; +} + +// static int convert_dac_volume(float gain, unsigned int *reg_val) +// { +// unsigned int reg_value = 0; +// float start_gain = -120; +// bool bfind = false; +// int i = 0 ; + +// if (gain < -120 || gain > 7) +// { +// return -1; +// } + +// for (i = 1; i <= 0xff; i++) +// { +// if (gain == start_gain) +// { +// reg_value = i; +// bfind = true; +// break; +// } +// else +// { +// start_gain += 0.5; +// } +// } +// if (!bfind) +// { +// return -1; +// } + +// *reg_val = reg_value; + +// return 0; +// } + +// static int convert_dac_volume2(unsigned int reg_val,float* gain) +// { +// float start_gain = -120; +// bool bfind = false; +// int i = 0; + +// if (reg_val < 1 || reg_val > 0xff) +// { +// return -1; +// } + +// for (i = 1; i <= 0xff; i++) +// { +// if (i == reg_val) +// { +// bfind = true; +// break; +// } +// else +// { +// start_gain += 0.5; +// } +// } +// if (!bfind) +// { +// return -1; +// } + +// *gain = start_gain; + +// return 0; +// } + +// int audio_codec_dacl_set_volume(float volume) +// { +// unsigned int reg_val = 0; +// reg_6_t reg6; + +// if (0 != convert_dac_volume(volume, ®_val)) +// { +// return -1; +// } + +// reg6.reg_data = readl(&audio_codec_reg->reg_06); +// reg6.reg_6.dac_vol = reg_val; +// writel(reg6.reg_data, &audio_codec_reg->reg_06); +// g_snd_current_values.dac_volumel = reg_val; +// g_snd_current_values.dac_volumer = reg_val; +// msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + +// return 0; +// } +// int audio_codec_dacr_set_volume(float volume) +// { +// unsigned int reg_val = 0; +// reg_6_t reg6; +// if (0 != convert_dac_volume(volume, ®_val)) +// { +// return -1; +// } + +// reg6.reg_data = readl(&audio_codec_reg->reg_06); +// reg6.reg_6.dac_vol = reg_val; +// writel(reg6.reg_data, &audio_codec_reg->reg_06); +// g_snd_current_values.dac_volumel = reg_val; +// g_snd_current_values.dac_volumer = reg_val; +// msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + +// return 0; +// } + +// int audio_codec_dacl_get_volume(float* volume) +// { +// return convert_dac_volume2(g_snd_current_values.dac_volumel, volume); +// } + +// int audio_codec_dacr_get_volume(float* volume) +// { +// return convert_dac_volume2(g_snd_current_values.dac_volumer, volume); +// } + +int audio_codec_reset(void) +{ + _reset_adc_sound(); + _reset_dac_sound(); + g_snd_current_values = g_snd_default_values; + return 0; +} + +int audio_codec_adc_hp_work(bool work) +{ + reg_23_t reg23; + + printk("audio_codec_adc_hp_work work:%d\n",work); + reg23.reg_data = readl(&audio_codec_reg->reg_23); + reg23.reg_23.initial_micl = work?1:0; + writel(reg23.reg_data, &audio_codec_reg->reg_23); + msleep(AUDIO_REG_CONFIG_NORMAL_DELAY); + + return 0; +} + diff --git a/src/little/linux/sound/soc/codecs/inno_k230_reg.h b/src/little/linux/sound/soc/codecs/inno_k230_reg.h new file mode 100644 index 000000000..a5f2d2870 --- /dev/null +++ b/src/little/linux/sound/soc/codecs/inno_k230_reg.h @@ -0,0 +1,553 @@ +/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _INNO_K230_REG_H_ +#define _INNO_K230_REG_H_ +#include + +typedef enum +{ + K_STANDARD_MODE = 1, + K_RIGHT_JUSTIFYING_MODE = 2, + K_LEFT_JUSTIFYING_MODE = 4 +} k_i2s_work_mode; + +typedef struct _codec_reg_0 +{ + uint32_t sys_bstn : 1; + uint32_t digcore_bstn : 1; + uint32_t reserved : 5; + uint32_t bist_bstn : 1; + + + /* Bits [31:8] is reseved */ + uint32_t resv : 24; +}__attribute__((packed, aligned(4))) codec_reg_0_t; + +typedef union _reg_0u { + codec_reg_0_t reg_0; + uint32_t reg_data; +} reg_0_t; + + + +typedef struct _codec_reg_1 +{ + uint32_t reserved : 4; + uint32_t dac_mute_sr : 3; + uint32_t dac_mute_en : 1; + + + /* Bits [31:8] is reseved */ + uint32_t resv : 24; +}__attribute__((packed, aligned(4))) codec_reg_1_t; + +typedef union _reg_1u { + codec_reg_1_t reg_1; + uint32_t reg_data; +} reg_1_t; + + + + +typedef struct _codec_reg_2 +{ + uint32_t i2s_tx_datsel : 2; + uint32_t reserved : 1; + uint32_t i2s_tx_fmt : 2; + uint32_t i2s_tx_wl : 2; + uint32_t i2s_tx_lrp : 1; + + /* Bits [31:8] is reseved */ + uint32_t resv : 24; +}__attribute__((packed, aligned(4))) codec_reg_2_t; + +typedef union _reg_2u { + codec_reg_2_t reg_2; + uint32_t reg_data; +} reg_2_t; + + +typedef struct _codec_reg_3 +{ + uint32_t i2s_tx_bclkinv : 1; + uint32_t i2s_tx_rstn : 1; + uint32_t i2s_tx_len : 2; + uint32_t i2s_tx_func_mst : 1; + uint32_t i2s_tx_pin_mst : 1; + uint32_t i2s_rx_func_mst : 1; + uint32_t i2s_rx_pin_mst : 1; + + /* Bits [31:8] is reseved */ + uint32_t resv : 24; +}__attribute__((packed, aligned(4))) codec_reg_3_t; + +typedef union _reg_3u { + codec_reg_3_t reg_3; + uint32_t reg_data; +} reg_3_t; + + +typedef struct _codec_reg_4 +{ + uint32_t reserved : 2; + uint32_t i2s_lr_swap : 1; + uint32_t i2s_rx_fmt : 2; + uint32_t i2s_rx_wl : 2; + uint32_t i2s_rx_lrp : 1; + /* Bits [31:8] is reseved */ + uint32_t resv : 24; +}__attribute__((packed, aligned(4))) codec_reg_4_t; + +typedef union _reg_4u { + codec_reg_4_t reg_4; + uint32_t reg_data; +} reg_4_t; + + + +typedef struct _codec_reg_6 +{ + uint32_t dac_vol : 8; + /* Bits [31:8] is reseved */ + uint32_t resv : 24; +}__attribute__((packed, aligned(4))) codec_reg_6_t; + +typedef union _reg_6u { + codec_reg_6_t reg_6; + uint32_t reg_data; +} reg_6_t; + +typedef struct _codec_reg_7 +{ + + uint32_t reserved : 4; + uint32_t dacl_bist_sel : 2; + uint32_t dacr_bist_sel : 2; + /* Bits [31:8] is reseved */ + uint32_t resv : 24; +}__attribute__((packed, aligned(4))) codec_reg_7_t; + +typedef union _reg_7u { + codec_reg_7_t reg_7; + uint32_t reg_data; +} reg_7_t; + + + +typedef struct _codec_reg_8 +{ + uint32_t adcl_vol : 8; + /* Bits [31:8] is reseved */ + uint32_t resv : 24; +}__attribute__((packed, aligned(4))) codec_reg_8_t; + +typedef union _reg_8u { + codec_reg_8_t reg_8; + uint32_t reg_data; +} reg_8_t; + +typedef struct _codec_reg_9 +{ + uint32_t adcr_vol : 8; + /* Bits [31:8] is reseved */ + uint32_t resv : 24; +}__attribute__((packed, aligned(4))) codec_reg_9_t; + +typedef union _reg_9u { + codec_reg_9_t reg_9; + uint32_t reg_data; +} reg_9_t; + + + + + +typedef struct _codec_reg_20 +{ + uint32_t gain_micbias : 3; + uint32_t en_micbias : 1; + uint32_t en_ibias_dac : 1; + uint32_t en_ibias_adc : 1; + uint32_t en_vref : 1; + uint32_t reserved : 1; + + /* Bits [31:8] is reseved */ + uint32_t resv : 24; +}__attribute__((packed, aligned(4))) codec_reg_20_t; + +typedef union _reg_20u { + codec_reg_20_t reg_20; + uint32_t reg_data; +} reg_20_t; + + + +typedef struct _codec_reg_21 +{ + uint32_t sel_vref : 8; + + /* Bits [31:8] is reseved */ + uint32_t resv : 24; +}__attribute__((packed, aligned(4))) codec_reg_21_t; + +typedef union _reg_21u { + codec_reg_21_t reg_21; + uint32_t reg_data; +} reg_21_t; + + +typedef struct _codec_reg_23 +{ + uint32_t initial_micl : 1; + uint32_t initial_alcl : 1; + uint32_t initial_adcl : 1; + uint32_t en_adcl : 1; + uint32_t en_clk_adcl : 1; + uint32_t en_alcl : 1; + uint32_t en_micl : 1; + uint32_t en_buf_adcl : 1; + /* Bits [31:8] is reseved */ + uint32_t resv : 24; +}__attribute__((packed, aligned(4))) codec_reg_23_t; + +typedef union _reg_23u { + codec_reg_23_t reg_23; + uint32_t reg_data; +} reg_23_t; + + + +typedef struct _codec_reg_24 +{ + uint32_t gain_alcl : 5; + uint32_t gain_micl : 2; + uint32_t mute_micl : 1; + + /* Bits [31:8] is reseved */ + uint32_t resv : 24; +}__attribute__((packed, aligned(4))) codec_reg_24_t; + +typedef union _reg_24u { + codec_reg_24_t reg_24; + uint32_t reg_data; +} reg_24_t; + + +typedef struct _codec_reg_25 +{ + uint32_t gain_alcl_det0_bp : 1; + uint32_t en_zerodet_adcl : 1; + uint32_t reserved : 6; + + /* Bits [31:8] is reseved */ + uint32_t resv : 24; +}__attribute__((packed, aligned(4))) codec_reg_25_t; + +typedef union _reg_25u { + codec_reg_25_t reg_25; + uint32_t reg_data; +} reg_25_t; + + +typedef struct _codec_reg_26 +{ + uint32_t initial_micr : 1; + uint32_t initial_alcr : 1; + uint32_t initial_adcr : 1; + uint32_t en_adcr : 1; + uint32_t en_clk_adcr : 1; + uint32_t en_alcr : 1; + uint32_t en_micr : 1; + uint32_t en_buf_adcr : 1; + + + /* Bits [31:8] is reseved */ + uint32_t resv : 24; +}__attribute__((packed, aligned(4))) codec_reg_26_t; + +typedef union _reg_26u { + codec_reg_26_t reg_26; + uint32_t reg_data; +} reg_26_t; + + +typedef struct _codec_reg_27 +{ + uint32_t gain_alcr : 5; + uint32_t gain_micr : 2; + uint32_t mute_micr : 1; + + /* Bits [31:8] is reseved */ + uint32_t resv : 24; +}__attribute__((packed, aligned(4))) codec_reg_27_t; + +typedef union _reg_27u { + codec_reg_27_t reg_27; + uint32_t reg_data; +} reg_27_t; + + +typedef struct _codec_reg_28 +{ + uint32_t gain_alcr_det0_bp : 1; + uint32_t en_zerodet_adcr : 1; + uint32_t reserved : 6; + + /* Bits [31:8] is reseved */ + uint32_t resv : 24; +}__attribute__((packed, aligned(4))) codec_reg_28_t; + +typedef union _reg_28u { + codec_reg_28_t reg_28; + uint32_t reg_data; +} reg_28_t; + + +typedef struct _codec_reg_29 +{ + uint32_t initial_dacl : 1; + uint32_t en_dacl : 1; + uint32_t en_clk_dacl : 1; + uint32_t en_vref_dacl : 1; + uint32_t pop_ctrl_dacl : 2; + uint32_t en_buf_dacl : 1; + uint32_t mute_hpoutl : 1; + + + /* Bits [31:8] is reseved */ + uint32_t resv : 24; +}__attribute__((packed, aligned(4))) codec_reg_29_t; + +typedef union _reg_29u { + codec_reg_29_t reg_29; + uint32_t reg_data; +} reg_29_t; + +typedef struct _codec_reg_2a +{ + uint32_t sel_hpoutl : 4; + uint32_t initial_hpoutl : 1; + uint32_t en_hpoutl : 1; + uint32_t reserved : 2; + + /* Bits [31:8] is reseved */ + uint32_t resv : 24; +}__attribute__((packed, aligned(4))) codec_reg_2a_t; + +typedef union _reg_2au { + codec_reg_2a_t reg_2a; + uint32_t reg_data; +} reg_2a_t; + + +typedef struct _codec_reg_2b +{ + uint32_t gain_hpoutl : 5; + uint32_t reserverd : 3; + + /* Bits [31:8] is reseved */ + uint32_t resv : 24; +}__attribute__((packed, aligned(4))) codec_reg_2b_t; + +typedef union _reg_2bu { + codec_reg_2b_t reg_2b; + uint32_t reg_data; +} reg_2b_t; + + + + +typedef struct _codec_reg_2d +{ + uint32_t sel_hpoutr : 4; + uint32_t initial_hpoutr : 1; + uint32_t en_hpoutr : 1; + uint32_t reserved : 2; + + /* Bits [31:8] is reseved */ + uint32_t resv : 24; +}__attribute__((packed, aligned(4))) codec_reg_2d_t; + +typedef union _reg_2du { + codec_reg_2d_t reg_2d; + uint32_t reg_data; +} reg_2d_t; + + + +typedef struct _codec_reg_2c +{ + uint32_t initial_dacr : 1; + uint32_t en_dacr : 1; + uint32_t en_clk_dacr : 1; + uint32_t en_vref_dacr : 1; + uint32_t pop_ctrl_dacr : 2; + uint32_t en_buf_dacr : 1; + uint32_t mute_hpoutr : 1; + + + /* Bits [31:8] is reseved */ + uint32_t resv : 24; +}__attribute__((packed, aligned(4))) codec_reg_2c_t; + +typedef union _reg_2cu { + codec_reg_2c_t reg_2c; + uint32_t reg_data; +} reg_2c_t; + + +typedef struct _codec_reg_2e +{ + uint32_t gain_hpoutr : 5; + uint32_t reserverd : 3; + + /* Bits [31:8] is reseved */ + uint32_t resv : 24; +}__attribute__((packed, aligned(4))) codec_reg_2e_t; + +typedef union _reg_2eu { + codec_reg_2e_t reg_2e; + uint32_t reg_data; +} reg_2e_t; + +typedef struct _audio_codec_reg +{ + volatile uint32_t reg_00;/* address:0x00 */ + volatile uint32_t reg_01;/* address:0x04 */ + volatile uint32_t reg_02;/* address:0x08 */ + volatile uint32_t reg_03;/* address:0x0c */ + volatile uint32_t reg_04;/* address:0x10 */ + volatile uint32_t reg_05;/* address:0x14 */ + volatile uint32_t reg_06;/* address:0x18 */ + volatile uint32_t reg_07;/* address:0x1c */ + volatile uint32_t reg_08;/* address:0x20 */ + volatile uint32_t reg_09;/* address:0x24 */ + volatile uint32_t reg_0a;/* address:0x28 */ + + volatile uint32_t reg_reserved_0b_1f[21];/* address:0x04 */ + + volatile uint32_t reg_20;/* address:0x80 */ + volatile uint32_t reg_21;/* address:0x84 */ + volatile uint32_t reg_22;/* address:0x88 */ + volatile uint32_t reg_23;/* address:0x8c */ + volatile uint32_t reg_24;/* address:0x90 */ + volatile uint32_t reg_25;/* address:0x04 */ + volatile uint32_t reg_26;/* address:0x98 */ + volatile uint32_t reg_27;/* address:0x9c */ + volatile uint32_t reg_28;/* address:0xa0 */ + volatile uint32_t reg_29;/* address:0xa4 */ + volatile uint32_t reg_2a;/* address:0xa8 */ + volatile uint32_t reg_2b;/* address:0xac */ + volatile uint32_t reg_2c;/* address:0xb0 */ + volatile uint32_t reg_2d;/* address:0xb4 */ + volatile uint32_t reg_2e;/* address:0xb8 */ + + volatile uint32_t reg_reserved_2f_3f[17];/* address:0x04 */ + + //The register's address which related to the ALCL function arrange from 0x40~0x4c. + volatile uint32_t reg_40;/* address:0x100 */ + volatile uint32_t reg_41;/* address:0x104 */ + volatile uint32_t reg_42;/* address:0x108 */ + volatile uint32_t reg_43;/* address:0x10c */ + volatile uint32_t reg_44;/* address:0x110*/ + volatile uint32_t reg_45;/* address:0x114 */ + volatile uint32_t reg_46;/* address:0x118 */ + volatile uint32_t reg_47;/* address:0x11c */ + volatile uint32_t reg_48;/* address:0x120 */ + volatile uint32_t reg_49;/* address:0x124 */ + volatile uint32_t reg_4a;/* address:0x128 */ + volatile uint32_t reg_4b;/* address:0x12c */ + volatile uint32_t reg_4c;/* address:0x130 */ + volatile uint32_t reg_4d;/* address:0x134 */ + volatile uint32_t reg_4e;/* address:0x138 */ + volatile uint32_t reg_4f;/* address:0x13c */ + + //The register's address which related to the ALCR function arrange from 0x50~0x5c. + volatile uint32_t reg_50;/* address:0x140 */ + volatile uint32_t reg_51;/* address:0x144 */ + volatile uint32_t reg_52;/* address:0x148 */ + volatile uint32_t reg_53;/* address:0x14c */ + volatile uint32_t reg_54;/* address:0x150 */ + volatile uint32_t reg_55;/* address:0x154 */ + volatile uint32_t reg_56;/* address:0x158 */ + volatile uint32_t reg_57;/* address:0x15c */ + volatile uint32_t reg_58;/* address:0x160 */ + volatile uint32_t reg_59;/* address:0x164 */ + volatile uint32_t reg_5a;/* address:0x168 */ + volatile uint32_t reg_5b;/* address:0x16c */ + volatile uint32_t reg_5c;/* address:0x170 */ + +}__attribute__((packed, aligned(4))) audio_codec_reg_s; + +int audio_codec_reg_init(void* reg_base); +void audio_codec_powerup_init(void); +void audio_codec_adc_init(k_i2s_work_mode mode,uint32_t i2s_ws);//i2s_ws最大24，设置32bit仍以24bit工作 +void audio_codec_dac_init(k_i2s_work_mode mode,uint32_t i2s_ws);//i2s_ws最大24，设置32bit仍以24bit工作 + +int audio_codec_adc_set_micl_gain(int gain); +int audio_codec_adc_set_micr_gain(int gain); +int audio_codec_adc_get_micl_gain(int* gain); +int audio_codec_adc_get_micr_gain(int* gain); + +// int audio_codec_adcl_set_volume(float volume); +// int audio_codec_adcr_set_volume(float volume); +// int audio_codec_adcl_get_volume(float* volume); +// int audio_codec_adcr_get_volume(float* volume); + +int audio_codec_adc_micl_mute(bool mute); +int audio_codec_adc_micr_mute(bool mute); + +int audio_codec_adc_get_micl_mute(bool* mute); +int audio_codec_adc_get_micr_mute(bool* mute); + +// int audio_codec_alc_set_micl_gain(float gain); +// int audio_codec_alc_set_micr_gain(float gain); +// int audio_codec_alc_get_micl_gain(float* gain); +// int audio_codec_alc_get_micr_gain(float* gain); + +int audio_codec_dac_set_hpoutl_gain(int gain); +int audio_codec_dac_set_hpoutr_gain(int gain); +int audio_codec_dac_get_hpoutl_gain(int* gain); +int audio_codec_dac_get_hpoutr_gain(int* gain); + +int audio_codec_dac_hpoutl_mute(bool mute); +int audio_codec_dac_hpoutr_mute(bool mute); + +int audio_codec_dac_get_hpoutl_mute(bool* mute); +int audio_codec_dac_get_hpoutr_mute(bool* mute); + +// int audio_codec_dacl_set_volume(float volume); +// int audio_codec_dacr_set_volume(float volume); +// int audio_codec_dacl_get_volume(float* volume); +// int audio_codec_dacr_get_volume(float* volume); + +int audio_codec_reset(void); + +int audio_codec_adc_hp_work(bool work);//Reset headphone input + +#endif + + diff --git a/src/little/linux/sound/soc/dwc/dwc-i2s.c b/src/little/linux/sound/soc/dwc/dwc-i2s.c index fd4160289..723979fe1 100644 --- a/src/little/linux/sound/soc/dwc/dwc-i2s.c +++ b/src/little/linux/sound/soc/dwc/dwc-i2s.c @@ -242,21 +242,26 @@ static int dw_i2s_hw_params(struct snd_pcm_substream *substream, switch (params_format(params)) { case SNDRV_PCM_FORMAT_S16_LE: - config->data_width = 16; - dev->ccr = 0x00; + config->data_width = 32; + dev->ccr = 0x10; + //dev->ccr |= 1<<10;//dma_divide_16 dev->xfer_resolution = 0x02; + dev->capture_dma_data.dt.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; + dev->play_dma_data.dt.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; break; case SNDRV_PCM_FORMAT_S24_LE: - config->data_width = 24; - dev->ccr = 0x08; + config->data_width = 32; + dev->ccr = 0x10; dev->xfer_resolution = 0x04; + dev->capture_dma_data.dt.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; break; case SNDRV_PCM_FORMAT_S32_LE: config->data_width = 32; dev->ccr = 0x10; dev->xfer_resolution = 0x05; + dev->capture_dma_data.dt.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; break; default: @@ -264,6 +269,8 @@ static int dw_i2s_hw_params(struct snd_pcm_substream *substream, return -EINVAL; } + dev->ccr |= (1<<5) | (3<<8);//standard i2s format and dma_tx_en||dma_rx_en + config->chan_nr = params_channels(params); switch (config->chan_nr) { @@ -293,8 +300,9 @@ static int dw_i2s_hw_params(struct snd_pcm_substream *substream, } else { u32 bitclk = config->sample_rate * config->data_width * 2; - + //printk("============clk_set_rate before:%d(sample_rate:%d,width:%d)\n",bitclk,config->sample_rate ,config->data_width); ret = clk_set_rate(dev->clk, bitclk); + //printk("============clk_set_rate end:%d\n",ret); if (ret) { dev_err(dev->dev, "Can't set I2S clock rate: %d\n", ret); @@ -383,7 +391,7 @@ static int dw_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) static const struct snd_soc_dai_ops dw_i2s_dai_ops = { .startup = dw_i2s_startup, - .shutdown = dw_i2s_shutdown, + //.shutdown = dw_i2s_shutdown,//Prevent collapse，dmaengine_pcm_set_runtime_hwparams use dma_data .hw_params = dw_i2s_hw_params, .prepare = dw_i2s_prepare, .trigger = dw_i2s_trigger, @@ -445,6 +453,7 @@ static const struct snd_soc_component_driver dw_i2s_component = { .name = "dw-i2s", .suspend = dw_i2s_suspend, .resume = dw_i2s_resume, + }; /* @@ -474,7 +483,7 @@ static const u32 formats[COMP_MAX_WORDSIZE] = { SNDRV_PCM_FMTBIT_S16_LE, SNDRV_PCM_FMTBIT_S24_LE, SNDRV_PCM_FMTBIT_S24_LE, - SNDRV_PCM_FMTBIT_S32_LE, + SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE, 0, 0, 0 @@ -513,6 +522,8 @@ static int dw_configure_dai(struct dw_i2s_dev *dev, 1 << (COMP1_TX_CHANNELS(comp1) + 1); dw_i2s_dai->playback.formats = formats[idx]; dw_i2s_dai->playback.rates = rates; + + //printk("==========dw_i2s_dai->playback.formats:%d,rate:%d\n",idx,rates); } if (COMP1_RX_ENABLED(comp1)) { @@ -527,6 +538,7 @@ static int dw_configure_dai(struct dw_i2s_dev *dev, 1 << (COMP1_RX_CHANNELS(comp1) + 1); dw_i2s_dai->capture.formats = formats[idx]; dw_i2s_dai->capture.rates = rates; + } if (COMP1_MODE_EN(comp1)) { @@ -600,7 +612,9 @@ static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev, dev->play_dma_data.dt.addr_width = bus_widths[idx]; dev->play_dma_data.dt.fifo_size = fifo_depth * (fifo_width[idx2]) >> 8; - dev->play_dma_data.dt.maxburst = 16; + dev->play_dma_data.dt.maxburst = 4; + + //printk("dev->play_dma_data.dt.addr:0x%llx,bus_widths idx:%d\n",dev->play_dma_data.dt.addr,idx); } if (COMP1_RX_ENABLED(comp1)) { idx2 = COMP2_RX_WORDSIZE_0(comp2); @@ -610,13 +624,21 @@ static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev, dev->capture_dma_data.dt.addr_width = bus_widths[idx]; dev->capture_dma_data.dt.fifo_size = fifo_depth * (fifo_width[idx2] >> 8); - dev->capture_dma_data.dt.maxburst = 16; + dev->capture_dma_data.dt.maxburst = 4; + //printk("dev->capture_dma_data.dt.addr:0x%llx,bus_widths idx:%d\n",dev->capture_dma_data.dt.addr,idx); } return 0; } +static int dw_i2s_audio_cpu_dai_probe(struct snd_soc_dai *dai) +{ + struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai); + snd_soc_dai_init_dma_data(dai, &dev->play_dma_data,&dev->capture_dma_data); + return 0; +} + static int dw_i2s_probe(struct platform_device *pdev) { const struct i2s_platform_data *pdata = pdev->dev.platform_data; @@ -635,6 +657,7 @@ static int dw_i2s_probe(struct platform_device *pdev) return -ENOMEM; dw_i2s_dai->ops = &dw_i2s_dai_ops; + dw_i2s_dai->probe = dw_i2s_audio_cpu_dai_probe; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); dev->i2s_base = devm_ioremap_resource(&pdev->dev, res); @@ -644,6 +667,7 @@ static int dw_i2s_probe(struct platform_device *pdev) dev->dev = &pdev->dev; irq = platform_get_irq(pdev, 0); + if (irq >= 0) { ret = devm_request_irq(&pdev->dev, irq, i2s_irq_handler, 0, pdev->name, dev); @@ -668,6 +692,7 @@ static int dw_i2s_probe(struct platform_device *pdev) clk_id = "i2sclk"; ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res); } + if (ret < 0) return ret; @@ -685,6 +710,7 @@ static int dw_i2s_probe(struct platform_device *pdev) return PTR_ERR(dev->clk); ret = clk_prepare_enable(dev->clk); + if (ret < 0) return ret; } diff --git a/src/little/uboot/arch/riscv/Kconfig b/src/little/uboot/arch/riscv/Kconfig index d2873961a..14f9c1acc 100755 --- a/src/little/uboot/arch/riscv/Kconfig +++ b/src/little/uboot/arch/riscv/Kconfig @@ -47,6 +47,10 @@ config TARGET_K230_CANMV_01STUDIO bool "Support k230_CANMV(01STUDIO)" select SYS_CACHE_SHIFT_6 +config TARGET_K230_CANMV_DONGSHANPI + bool "Support k230_CANMV(DONGSHANPI)" + select SYS_CACHE_SHIFT_6 + config TARGET_K230D_CANMV bool "Support k230D_CANMV(K230PI zero)" select SYS_CACHE_SHIFT_6 @@ -97,6 +101,7 @@ source "board/canaan/k230_fpga/Kconfig" source "board/canaan/k230_evb/Kconfig" source "board/canaan/k230_canmv/Kconfig" source "board/canaan/k230_canmv_01studio/Kconfig" +source "board/canaan/k230_canmv_dongshanpi/Kconfig" source "board/canaan/k230d_canmv/Kconfig" source "board/canaan/k230_unsiplp4/Kconfig" source "board/canaan/k230_siplp4/Kconfig" diff --git a/src/little/uboot/arch/riscv/cpu/k230/Kconfig b/src/little/uboot/arch/riscv/cpu/k230/Kconfig index f99a245f6..b187e2041 100755 --- a/src/little/uboot/arch/riscv/cpu/k230/Kconfig +++ b/src/little/uboot/arch/riscv/cpu/k230/Kconfig @@ -26,6 +26,8 @@ config DDR_SIZE default 0x08000000 if SIPLP4_3200_WALLODT default 0x08000000 if SIPLP4_2667 default 0x08000000 if SIPLP4_1600 - default 0x20000000 + default 0x40000000 if CANMV_01STUDIO_LPDDR4_2667 + default 0x40000000 if CANMV_01STUDIO_LPDDR4_3200 + default 0x20000000 help Size of the DDR \ No newline at end of file diff --git a/src/little/uboot/arch/riscv/cpu/k230/cache.c b/src/little/uboot/arch/riscv/cpu/k230/cache.c index 06289bc76..ebd5ee3c1 100644 --- a/src/little/uboot/arch/riscv/cpu/k230/cache.c +++ b/src/little/uboot/arch/riscv/cpu/k230/cache.c @@ -294,7 +294,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long end) register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1); for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE) - asm volatile(".long 0x02b5000b"); /* dcache.cipa a0 */ + asm volatile(".long 0x02a5000b"); /* dcache.ipa a0 */ sync_is(); } diff --git a/src/little/uboot/arch/riscv/dts/k230.dtsi b/src/little/uboot/arch/riscv/dts/k230.dtsi index 8f3b80ee6..b469de1a5 100755 --- a/src/little/uboot/arch/riscv/dts/k230.dtsi +++ b/src/little/uboot/arch/riscv/dts/k230.dtsi @@ -151,7 +151,7 @@ reg = <0x0 0x91580000 0x0 0x400>; bus-width = <8>; clocks = <&def_200mhz>; - max-frequency = <50000000>; + max-frequency = <200000000>; fifo-mode; have-emmc-phy; status = "disabled"; diff --git a/src/little/uboot/arch/riscv/dts/k230_canmv.dts b/src/little/uboot/arch/riscv/dts/k230_canmv.dts index 89c3ae8a0..71e10c7a3 100755 --- a/src/little/uboot/arch/riscv/dts/k230_canmv.dts +++ b/src/little/uboot/arch/riscv/dts/k230_canmv.dts @@ -41,9 +41,7 @@ memory@0 { device_type = "memory"; reg = < - 0x0 0x8000000 0x0 0x7fff000 /*MEM_LINUX_SYS*/ - 0x0 0x200000 0x0 0x7dff000 /*MEM_RTT_SYS*/ - 0x0 0x10000000 0x0 0x10000000 + 0x0 0 0x0 0x20000000 >; }; }; diff --git a/src/little/uboot/arch/riscv/dts/k230_canmv_01studio.dts b/src/little/uboot/arch/riscv/dts/k230_canmv_01studio.dts index 530d5bfeb..7a934a0f2 100755 --- a/src/little/uboot/arch/riscv/dts/k230_canmv_01studio.dts +++ b/src/little/uboot/arch/riscv/dts/k230_canmv_01studio.dts @@ -41,8 +41,7 @@ memory@0 { device_type = "memory"; reg = < - 0x0 0x8000000 0x0 0x7fff000 /*MEM_LINUX_SYS*/ - 0x0 0x200000 0x0 0x7dff000 /*MEM_RTT_SYS*/ + 0x0 0 0x0 0x40000000 >; }; }; diff --git a/src/little/uboot/arch/riscv/dts/k230_canmv_dongshanpi.dts b/src/little/uboot/arch/riscv/dts/k230_canmv_dongshanpi.dts new file mode 100755 index 000000000..09e26ffe4 --- /dev/null +++ b/src/little/uboot/arch/riscv/dts/k230_canmv_dongshanpi.dts @@ -0,0 +1,182 @@ +/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +/dts-v1/; +#include + +#define BANK_VOLTAGE_IO0_IO1 K230_MSC_1V8 // FIXED +#define BANK_VOLTAGE_IO2_IO13 K230_MSC_3V3 +#define BANK_VOLTAGE_IO14_IO25 K230_MSC_3V3 +#define BANK_VOLTAGE_IO26_IO37 K230_MSC_3V3 +#define BANK_VOLTAGE_IO38_IO49 K230_MSC_3V3 +#define BANK_VOLTAGE_IO50_IO61 K230_MSC_3V3 +#define BANK_VOLTAGE_IO62_IO63 K230_MSC_3V3 +#include "k230.dtsi" + +/ { + model = "kendryte k230 canmv dongshanpi"; + compatible = "kendryte,k230_canmv_dongshanpi"; + + memory@0 { + device_type = "memory"; + reg = < + 0x0 0 0x0 0x20000000 + >; + }; +}; + +&mmc0 { + 1-8-v; + status = "okay"; +}; + +&mmc1 { + status = "okay"; +}; + +&usbotg1 { + status = "okay"; +}; + +&iomux { + pinctrl-names = "default"; + pinctrl-0 = <&pins>; + +// Please pay attention to the bank voltage! will damage the chip. + pins: iomux_pins { + u-boot,dm-pre-reloc; + pinctrl-single,pins = < + + // JTAG -> J5 + (IO2 ) ( 1< CSI2 + (IO7) ( 2< CSI0 + (IO9 ) ( 0< CSI1 + (IO11) ( 0< CSI2 + (IO13) ( 1< J10 + (IO14) ( 0< CSI2 + (IO21) ( 0< DSI + (IO22) ( 0< DSI + (IO23) ( 0< DSI + (IO24) ( 0< DSI + (IO25) ( 0< J10 + (IO26) ( 0< DSI + (IO36) ( 1< DSI + (IO37) ( 1< CH342F + (IO38) ( 1< CSI1 + (IO40) ( 2< CSI1 + (IO41) ( 2< J10 + (IO42) ( 0< KEY1 + (IO46) ( 0< KEY2 + (IO47) ( 0< CSI0 + (IO48) ( 3< CH342F + (IO50) ( 1< J10 + (IO52) ( 0< TFCARD + (IO54) ( 2< CSI1 + (IO60) ( 0< CSI0 + (IO61) ( 0< J10 + (IO62) ( 0<; + }; +}; diff --git a/src/little/uboot/arch/riscv/dts/k230_canmv_v2.dts b/src/little/uboot/arch/riscv/dts/k230_canmv_v2.dts index 51e47ad4f..585c6ce90 100755 --- a/src/little/uboot/arch/riscv/dts/k230_canmv_v2.dts +++ b/src/little/uboot/arch/riscv/dts/k230_canmv_v2.dts @@ -41,8 +41,7 @@ memory@0 { device_type = "memory"; reg = < - 0x0 0x8000000 0x0 0x7fff000 /*MEM_LINUX_SYS*/ - 0x0 0x200000 0x0 0x7dff000 /*MEM_RTT_SYS*/ + 0x0 0 0x0 0x20000000 >; }; }; diff --git a/src/little/uboot/arch/riscv/dts/k230_evb.dts b/src/little/uboot/arch/riscv/dts/k230_evb.dts index 1ba821042..fc795da8d 100755 --- a/src/little/uboot/arch/riscv/dts/k230_evb.dts +++ b/src/little/uboot/arch/riscv/dts/k230_evb.dts @@ -32,8 +32,7 @@ memory@0 { device_type = "memory"; reg = < - 0x0 0x8000000 0x0 0x7fff000 /*MEM_LINUX_SYS*/ - 0x0 0x200000 0x0 0x7dff000 /*MEM_RTT_SYS*/ + 0x0 0 0x0 0x20000000 >; }; }; diff --git a/src/little/uboot/arch/riscv/dts/k230_evb.dtsi b/src/little/uboot/arch/riscv/dts/k230_evb.dtsi index d4b67da44..5802c906f 100755 --- a/src/little/uboot/arch/riscv/dts/k230_evb.dtsi +++ b/src/little/uboot/arch/riscv/dts/k230_evb.dtsi @@ -41,8 +41,7 @@ memory@0 { device_type = "memory"; reg = < - 0x0 0x8000000 0x0 0x7fff000 /*MEM_LINUX_SYS*/ - 0x0 0x200000 0x0 0x7dff000 /*MEM_RTT_SYS*/ + 0x0 0 0x0 0x20000000 >; }; }; diff --git a/src/little/uboot/arch/riscv/dts/k230_evb_doorlock_ov9286.dts b/src/little/uboot/arch/riscv/dts/k230_evb_doorlock_ov9286.dts index 318b6f7c0..eccc9a6c3 100755 --- a/src/little/uboot/arch/riscv/dts/k230_evb_doorlock_ov9286.dts +++ b/src/little/uboot/arch/riscv/dts/k230_evb_doorlock_ov9286.dts @@ -32,8 +32,7 @@ memory@0 { device_type = "memory"; reg = < - 0x0 0x8000000 0x0 0x7fff000 /*MEM_LINUX_SYS*/ - 0x0 0x200000 0x0 0x7dff000 /*MEM_RTT_SYS*/ + 0x0 0 0x0 0x20000000 >; }; }; diff --git a/src/little/uboot/arch/riscv/dts/k230_evb_nand.dts b/src/little/uboot/arch/riscv/dts/k230_evb_nand.dts index 75f3fabb5..2cff56c70 100755 --- a/src/little/uboot/arch/riscv/dts/k230_evb_nand.dts +++ b/src/little/uboot/arch/riscv/dts/k230_evb_nand.dts @@ -32,8 +32,7 @@ memory@0 { device_type = "memory"; reg = < - 0x0 0x8000000 0x0 0x7fff000 /*MEM_LINUX_SYS*/ - 0x0 0x200000 0x0 0x7dff000 /*MEM_RTT_SYS*/ + 0x0 0 0x0 0x20000000 >; }; }; diff --git a/src/little/uboot/arch/riscv/dts/k230_evb_sip.dts b/src/little/uboot/arch/riscv/dts/k230_evb_sip.dts index eeb875d9b..3dc90ae14 100755 --- a/src/little/uboot/arch/riscv/dts/k230_evb_sip.dts +++ b/src/little/uboot/arch/riscv/dts/k230_evb_sip.dts @@ -32,8 +32,7 @@ memory@0 { device_type = "memory"; reg = < - 0x0 0x1600000 0x0 0x47ff000 /*MEM_LINUX_SYS*/ - 0x0 0x200000 0x0 0x13ff000 /*MEM_RTT_SYS*/ + 0x0 0 0x0 0x8000000 >; }; }; diff --git a/src/little/uboot/arch/riscv/dts/k230d_canmv.dts b/src/little/uboot/arch/riscv/dts/k230d_canmv.dts index 14bd19bf7..b604134a0 100755 --- a/src/little/uboot/arch/riscv/dts/k230d_canmv.dts +++ b/src/little/uboot/arch/riscv/dts/k230d_canmv.dts @@ -40,8 +40,7 @@ memory@0 { device_type = "memory"; reg = < - 0x0 0x1600000 0x0 0x47ff000 /*MEM_LINUX_SYS*/ - 0x0 0x200000 0x0 0x13ff000 /*MEM_RTT_SYS*/ + 0x0 0 0x0 0x8000000 >; }; }; diff --git a/src/little/uboot/arch/riscv/dts/k230d_doorlock_ov9286.dts b/src/little/uboot/arch/riscv/dts/k230d_doorlock_ov9286.dts index eadc12cc9..b1083e158 100755 --- a/src/little/uboot/arch/riscv/dts/k230d_doorlock_ov9286.dts +++ b/src/little/uboot/arch/riscv/dts/k230d_doorlock_ov9286.dts @@ -32,8 +32,7 @@ memory@0 { device_type = "memory"; reg = < - 0x0 0x2600000 0x0 0x28df000 /*MEM_LINUX_SYS*/ - 0x0 0x200000 0x0 0x23ff000 /*MEM_RTT_SYS*/ + 0x0 0 0x0 0x8000000 >; }; }; diff --git a/src/little/uboot/arch/riscv/dts/k230d_evb.dtsi b/src/little/uboot/arch/riscv/dts/k230d_evb.dtsi index 9f0321c7d..819aa262c 100755 --- a/src/little/uboot/arch/riscv/dts/k230d_evb.dtsi +++ b/src/little/uboot/arch/riscv/dts/k230d_evb.dtsi @@ -40,8 +40,7 @@ memory@0 { device_type = "memory"; reg = < - 0x0 0x1600000 0x0 0x47ff000 /*MEM_LINUX_SYS*/ - 0x0 0x200000 0x0 0x13ff000 /*MEM_RTT_SYS*/ + 0x0 0 0x0 0x8000000 >; }; }; diff --git a/src/little/uboot/board/canaan/k230_canmv_01studio/Kconfig b/src/little/uboot/board/canaan/k230_canmv_01studio/Kconfig index 731275e78..c30b9e270 100755 --- a/src/little/uboot/board/canaan/k230_canmv_01studio/Kconfig +++ b/src/little/uboot/board/canaan/k230_canmv_01studio/Kconfig @@ -18,7 +18,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select RISCV_THEAD choice prompt "ddr typy freq" - default CANMV_01STUDIO_LPDDR3_2133 + default CANMV_01STUDIO_LPDDR4_2667 config CANMV_01STUDIO_LPDDR3_2133 bool 2133 @@ -26,5 +26,9 @@ config CANMV_01STUDIO_LPDDR3_1600 bool 1600 config CANMV_01STUDIO_LPDDR3_800 bool 800 +config CANMV_01STUDIO_LPDDR4_2667 + bool LP4_2667 +config CANMV_01STUDIO_LPDDR4_3200 + bool LP4_3200 endchoice endif diff --git a/src/little/uboot/board/canaan/k230_canmv_01studio/Makefile b/src/little/uboot/board/canaan/k230_canmv_01studio/Makefile index ebafb87b7..8dc414fea 100755 --- a/src/little/uboot/board/canaan/k230_canmv_01studio/Makefile +++ b/src/little/uboot/board/canaan/k230_canmv_01studio/Makefile @@ -29,6 +29,9 @@ obj-$(CONFIG_CANMV_01STUDIO_LPDDR3_2133) += gen_canmv_01studio_lpddr3_2133.o obj-$(CONFIG_CANMV_01STUDIO_LPDDR3_1600) += gen_canmv_01studio_lpddr3_1600.o obj-$(CONFIG_CANMV_01STUDIO_LPDDR3_800) += gen_canmv_01studio_lpddr3_800.o +obj-$(CONFIG_CANMV_01STUDIO_LPDDR4_2667) += gen_canmv_01studio_lpddr4_2667.o +obj-$(CONFIG_CANMV_01STUDIO_LPDDR4_3200) += gen_canmv_01studio_lpddr4_3200.o + $(obj)/gen_canmv_01studio_lpddr3_2133.c: $(src)/canmv_01studio_ddr_init_2133.c $(srctree)/arch/riscv/cpu/k230/ddr.sh ($(srctree)/arch/riscv/cpu/k230/ddr.sh $< $@ 0x50000 0x53fff 0x54000 0x54359 || exit 1) $(obj)/gen_canmv_01studio_lpddr3_1600.c: $(src)/canmv_01studio_ddr_init_1600.c $(srctree)/arch/riscv/cpu/k230/ddr.sh @@ -36,6 +39,11 @@ $(obj)/gen_canmv_01studio_lpddr3_1600.c: $(src)/canmv_01studio_ddr_init_1600.c $(obj)/gen_canmv_01studio_lpddr3_800.c: $(src)/canmv_01studio_ddr_init_800.c $(srctree)/arch/riscv/cpu/k230/ddr.sh ($(srctree)/arch/riscv/cpu/k230/ddr.sh $< $@ 0x50000 0x53fff 0x54000 0x54359 || exit 1) +$(obj)/gen_canmv_01studio_lpddr4_2667.c: $(src)/lpddr4_init_32_swap_2667.c $(srctree)/arch/riscv/cpu/k230/ddr.sh + ($(srctree)/arch/riscv/cpu/k230/ddr.sh $< $@ 0x50000 0x53fff 0x54000 0x5433d || exit 1) +$(obj)/gen_canmv_01studio_lpddr4_3200.c: $(src)/lpddr4_init_32_swap_3200.c + ($(srctree)/arch/riscv/cpu/k230/ddr_2d.sh $< $@ 0x50000 0x53fff 0x54000 0x5433d 0x542bd || exit 1) + EXTRA_CFLAGS += -I$(srctree)/arch/$(ARCH)/cpu/k230/ EXTRA_CFLAGS += -I$(srctree)/arch/$(ARCH)/cpu/k230/puf_fw/pufs_common EXTRA_CFLAGS += -I$(srctree)/arch/$(ARCH)/cpu/k230/puf_fw/pufs_crypto diff --git a/src/little/uboot/board/canaan/k230_canmv_01studio/board.c b/src/little/uboot/board/canaan/k230_canmv_01studio/board.c index 3a953e5ef..5b3007f70 100755 --- a/src/little/uboot/board/canaan/k230_canmv_01studio/board.c +++ b/src/little/uboot/board/canaan/k230_canmv_01studio/board.c @@ -38,8 +38,12 @@ int ddr_init_training(void) canmv_01studio_ddr_init_2133(); #elif defined(CONFIG_CANMV_01STUDIO_LPDDR3_1600) canmv_01studio_ddr_init_1600(); - #elif defined(CONFIG_CANMV_01STUDIO_LPDDR3_800) + #elif defined(CONFIG_CANMV_01STUDIO_LPDDR3_800) canmv_01studio_ddr_init_800(); + #elif defined(CONFIG_CANMV_01STUDIO_LPDDR4_2667) + ddr_init_2667(); + #elif defined(CONFIG_CANMV_01STUDIO_LPDDR4_3200) + ddr4_init_3200(); #endif return 0; } diff --git a/src/little/uboot/board/canaan/k230_canmv_01studio/lpddr4_init_32_swap_1066.c b/src/little/uboot/board/canaan/k230_canmv_01studio/lpddr4_init_32_swap_1066.c new file mode 100755 index 000000000..914caf79c --- /dev/null +++ b/src/little/uboot/board/canaan/k230_canmv_01studio/lpddr4_init_32_swap_1066.c @@ -0,0 +1,18508 @@ +/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +//#include +//#include +#define DDR_REG_BASE 0x98000000 + +#define reg_write( addr,v) \ + { \ + (*(volatile uint32_t *)((size_t)(addr))) = (v); \ + } + + +#define reg_read( addr,v) \ + { \ + v =readl ((const volatile void __iomem *) addr ); \ + } + +void ddr_init_1066() +{ +int data; +int train_data=0; +printf("ddr4 ddr_init_1066\n"); + + reg_read (0x91100060,data); + data =data | 0x400; + data =data | 0x80000000; + reg_write(0x91100060,data); + + reg_read (0x911030a0,data); + data =data | 0x10; + reg_write(0x911030a0,data); + +//reg_read (0x91100060,data); +// data =data & 0xfffffffc; +// data =data | 0xc00; +// data =data | 0x80000000; +// reg_write(0x91100060,data); + + +reg_write( DDR_REG_BASE + 0x00000304 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000001 ); +reg_read ( DDR_REG_BASE + 0x00000004 , data ); +reg_write( DDR_REG_BASE + 0x00000000 , 0x01080020 ); +reg_write( DDR_REG_BASE + 0x00000010 , 0x0000b030 ); +reg_write( DDR_REG_BASE + 0x00000014 , 0x0002ec4d ); +reg_write( DDR_REG_BASE + 0x00000020 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000024 , 0xf491fa51 ); +reg_write( DDR_REG_BASE + 0x00000028 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x0000002c , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000020 ); +reg_write( DDR_REG_BASE + 0x00000034 , 0x00408a04 ); +reg_write( DDR_REG_BASE + 0x00000038 , 0x0e0e0002 ); +reg_write( DDR_REG_BASE + 0x0000003c , 0x00000060 ); +reg_write( DDR_REG_BASE + 0x00000050 , 0x98210000 ); +reg_write( DDR_REG_BASE + 0x00000054 , 0x001d001a ); +reg_write( DDR_REG_BASE + 0x00000060 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000064 , 0x00200023 ); +reg_write( DDR_REG_BASE + 0x00000068 , 0x00100000 ); +reg_write( DDR_REG_BASE + 0x000000c0 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000000d0 , 0xc0020002 ); +reg_write( DDR_REG_BASE + 0x000000d4 , 0x00010002 ); +reg_write( DDR_REG_BASE + 0x000000d8 , 0x00000a00 ); +reg_write( DDR_REG_BASE + 0x000000dc , 0x00140009 ); +reg_write( DDR_REG_BASE + 0x000000e0 , 0x00310008 ); +reg_write( DDR_REG_BASE + 0x000000e4 , 0x00020004 ); +reg_write( DDR_REG_BASE + 0x000000e8 , 0x0000004d ); +reg_write( DDR_REG_BASE + 0x000000ec , 0x0000004d ); +reg_write( DDR_REG_BASE + 0x000000f0 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000000f4 , 0x0000032f ); +reg_write( DDR_REG_BASE + 0x000000f8 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00000100 , 0x0d0b080c ); +reg_write( DDR_REG_BASE + 0x00000104 , 0x00030410 ); +reg_write( DDR_REG_BASE + 0x00000108 , 0x0305080c ); +reg_write( DDR_REG_BASE + 0x0000010c , 0x00505006 ); +reg_write( DDR_REG_BASE + 0x00000110 , 0x05040305 ); +reg_write( DDR_REG_BASE + 0x00000114 , 0x02030404 ); +reg_write( DDR_REG_BASE + 0x00000118 , 0x01010004 ); +reg_write( DDR_REG_BASE + 0x0000011c , 0x00000302 ); +reg_write( DDR_REG_BASE + 0x00000120 , 0x00000101 ); +reg_write( DDR_REG_BASE + 0x00000130 , 0x00020000 ); +reg_write( DDR_REG_BASE + 0x00000134 , 0x0a100002 ); +reg_write( DDR_REG_BASE + 0x00000138 , 0x00000025 ); +reg_write( DDR_REG_BASE + 0x0000013c , 0x80000000 ); +reg_write( DDR_REG_BASE + 0x00000144 , 0x0036001b ); +reg_write( DDR_REG_BASE + 0x00000180 , 0xc10b0008 ); +reg_write( DDR_REG_BASE + 0x00000184 , 0x00e7c42a ); +reg_write( DDR_REG_BASE + 0x00000188 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000190 , 0x03858202 ); +reg_write( DDR_REG_BASE + 0x00000194 , 0x00090202 ); +reg_write( DDR_REG_BASE + 0x00000198 , 0x0710a120 ); +reg_write( DDR_REG_BASE + 0x000001a0 , 0xe0400018 ); +reg_write( DDR_REG_BASE + 0x000001a4 , 0x00020035 ); +reg_write( DDR_REG_BASE + 0x000001a8 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000001b0 , 0x00000015 ); +reg_write( DDR_REG_BASE + 0x000001b4 , 0x00000502 ); +reg_write( DDR_REG_BASE + 0x000001c0 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000001c4 , 0xd1000000 ); +reg_write( DDR_REG_BASE + 0x00000200 , 0x0000001f ); +reg_write( DDR_REG_BASE + 0x00000204 , 0x00080808 ); +reg_write( DDR_REG_BASE + 0x00000208 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0000020c , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000210 , 0x00001f1f ); +reg_write( DDR_REG_BASE + 0x00000214 , 0x070f0707 ); +reg_write( DDR_REG_BASE + 0x00000218 , 0x0f0f0f07 ); //2gb +//reg_write( DDR_REG_BASE + 0x00000218 , 0x0f0f0707 ); //4gb +reg_write( DDR_REG_BASE + 0x0000021c , 0x00000f0f ); +reg_write( DDR_REG_BASE + 0x00000224 , 0x07070707 ); +reg_write( DDR_REG_BASE + 0x00000228 , 0x07070707 ); +reg_write( DDR_REG_BASE + 0x0000022c , 0x00000007 ); +reg_write( DDR_REG_BASE + 0x00000240 , 0x06040620 ); +reg_write( DDR_REG_BASE + 0x00000244 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000250 , 0x804b1f18 ); +reg_write( DDR_REG_BASE + 0x00000254 , 0x00002000 ); +reg_write( DDR_REG_BASE + 0x0000025c , 0x0f000001 ); +reg_write( DDR_REG_BASE + 0x00000264 , 0x0f00007f ); +reg_write( DDR_REG_BASE + 0x0000026c , 0x0f00007f ); +reg_write( DDR_REG_BASE + 0x00000270 , 0x04040208 ); +reg_write( DDR_REG_BASE + 0x00000274 , 0x08400810 ); +reg_write( DDR_REG_BASE + 0x00000300 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000304 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0000030c , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000320 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000328 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0000036c , 0x00000011 ); +reg_write( DDR_REG_BASE + 0x00000490 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000540 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000005f0 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000006a0 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000750 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00002020 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00002024 , 0xf491fa51 ); +reg_write( DDR_REG_BASE + 0x00002034 , 0x00408a04 ); +reg_write( DDR_REG_BASE + 0x00002050 , 0xf0210000 ); +reg_write( DDR_REG_BASE + 0x00002064 , 0x00208023 ); +reg_write( DDR_REG_BASE + 0x00002068 , 0x00100000 ); +reg_write( DDR_REG_BASE + 0x000020dc , 0x00140009 ); +reg_write( DDR_REG_BASE + 0x000020e0 , 0x00310008 ); +reg_write( DDR_REG_BASE + 0x000020e8 , 0x0000004d ); +reg_write( DDR_REG_BASE + 0x000020ec , 0x0000004d ); +reg_write( DDR_REG_BASE + 0x000020f4 , 0x0000032f ); +reg_write( DDR_REG_BASE + 0x000020f8 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00002100 , 0x0d0b080c ); +reg_write( DDR_REG_BASE + 0x00002104 , 0x00030410 ); +reg_write( DDR_REG_BASE + 0x00002108 , 0x0305080c ); +reg_write( DDR_REG_BASE + 0x0000210c , 0x00505006 ); +reg_write( DDR_REG_BASE + 0x00002110 , 0x05040305 ); +reg_write( DDR_REG_BASE + 0x00002114 , 0x02030404 ); +reg_write( DDR_REG_BASE + 0x00002118 , 0x01010004 ); +reg_write( DDR_REG_BASE + 0x0000211c , 0x00000302 ); +reg_write( DDR_REG_BASE + 0x00002120 , 0x00000101 ); +reg_write( DDR_REG_BASE + 0x00002130 , 0x00020000 ); +reg_write( DDR_REG_BASE + 0x00002134 , 0x0a100002 ); +reg_write( DDR_REG_BASE + 0x00002138 , 0x00000025 ); +reg_write( DDR_REG_BASE + 0x0000213c , 0x80000000 ); +reg_write( DDR_REG_BASE + 0x00002144 , 0x0036001b ); +reg_write( DDR_REG_BASE + 0x00002180 , 0xc10b0008 ); +reg_write( DDR_REG_BASE + 0x00002190 , 0x03858202 ); +reg_write( DDR_REG_BASE + 0x00002194 , 0x00090202 ); +reg_write( DDR_REG_BASE + 0x000021b4 , 0x00000502 ); +reg_write( DDR_REG_BASE + 0x00002240 , 0x06040620 ); +reg_write( DDR_REG_BASE + 0x00003020 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00003024 , 0xf491fa51 ); +reg_write( DDR_REG_BASE + 0x00003034 , 0x00408a04 ); +reg_write( DDR_REG_BASE + 0x00003050 , 0x48210000 ); +reg_write( DDR_REG_BASE + 0x00003064 , 0x00208023 ); +reg_write( DDR_REG_BASE + 0x00003068 , 0x00100000 ); +reg_write( DDR_REG_BASE + 0x000030dc , 0x00140009 ); +reg_write( DDR_REG_BASE + 0x000030e0 , 0x00310008 ); +reg_write( DDR_REG_BASE + 0x000030e8 , 0x0000004d ); +reg_write( DDR_REG_BASE + 0x000030ec , 0x0000004d ); +reg_write( DDR_REG_BASE + 0x000030f4 , 0x0000032f ); +reg_write( DDR_REG_BASE + 0x000030f8 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00003100 , 0x0d0b080c ); +reg_write( DDR_REG_BASE + 0x00003104 , 0x00030410 ); +reg_write( DDR_REG_BASE + 0x00003108 , 0x0305080c ); +reg_write( DDR_REG_BASE + 0x0000310c , 0x00505006 ); +reg_write( DDR_REG_BASE + 0x00003110 , 0x05040305 ); +reg_write( DDR_REG_BASE + 0x00003114 , 0x02030404 ); +reg_write( DDR_REG_BASE + 0x00003118 , 0x01010004 ); +reg_write( DDR_REG_BASE + 0x0000311c , 0x00000302 ); +reg_write( DDR_REG_BASE + 0x00003120 , 0x00000101 ); +reg_write( DDR_REG_BASE + 0x00003130 , 0x00020000 ); +reg_write( DDR_REG_BASE + 0x00003134 , 0x0a100002 ); +reg_write( DDR_REG_BASE + 0x00003138 , 0x00000025 ); +reg_write( DDR_REG_BASE + 0x0000313c , 0x80000000 ); +reg_write( DDR_REG_BASE + 0x00003144 , 0x0036001b ); +reg_write( DDR_REG_BASE + 0x00003180 , 0xc10b0008 ); +reg_write( DDR_REG_BASE + 0x00003190 , 0x03858202 ); +reg_write( DDR_REG_BASE + 0x00003194 , 0x00090202 ); +reg_write( DDR_REG_BASE + 0x000031b4 , 0x00000502 ); +reg_write( DDR_REG_BASE + 0x00003240 , 0x06040620 ); +reg_write( DDR_REG_BASE + 0x00004020 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00004024 , 0xf491fa51 ); +reg_write( DDR_REG_BASE + 0x00004034 , 0x00408a04 ); +reg_write( DDR_REG_BASE + 0x00004050 , 0x70210000 ); +reg_write( DDR_REG_BASE + 0x00004064 , 0x00200023 ); +reg_write( DDR_REG_BASE + 0x00004068 , 0x00100000 ); +reg_write( DDR_REG_BASE + 0x000040dc , 0x00140009 ); +reg_write( DDR_REG_BASE + 0x000040e0 , 0x00310008 ); +reg_write( DDR_REG_BASE + 0x000040e8 , 0x0000004d ); +reg_write( DDR_REG_BASE + 0x000040ec , 0x0000004d ); +reg_write( DDR_REG_BASE + 0x000040f4 , 0x0000032f ); +reg_write( DDR_REG_BASE + 0x000040f8 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00004100 , 0x0d0b080c ); +reg_write( DDR_REG_BASE + 0x00004104 , 0x00030410 ); +reg_write( DDR_REG_BASE + 0x00004108 , 0x0305080c ); +reg_write( DDR_REG_BASE + 0x0000410c , 0x00505006 ); +reg_write( DDR_REG_BASE + 0x00004110 , 0x05040305 ); +reg_write( DDR_REG_BASE + 0x00004114 , 0x02030404 ); +reg_write( DDR_REG_BASE + 0x00004118 , 0x01010004 ); +reg_write( DDR_REG_BASE + 0x0000411c , 0x00000302 ); +reg_write( DDR_REG_BASE + 0x00004120 , 0x00000101 ); +reg_write( DDR_REG_BASE + 0x00004130 , 0x00020000 ); +reg_write( DDR_REG_BASE + 0x00004134 , 0x0a100002 ); +reg_write( DDR_REG_BASE + 0x00004138 , 0x00000025 ); +reg_write( DDR_REG_BASE + 0x0000413c , 0x80000000 ); +reg_write( DDR_REG_BASE + 0x00004144 , 0x0036001b ); +reg_write( DDR_REG_BASE + 0x00004180 , 0xc10b0008 ); +reg_write( DDR_REG_BASE + 0x00004190 , 0x03858202 ); +reg_write( DDR_REG_BASE + 0x00004194 , 0x00090202 ); +reg_write( DDR_REG_BASE + 0x000041b4 , 0x00000502 ); +reg_write( DDR_REG_BASE + 0x00004240 , 0x06040620 ); +reg_read ( DDR_REG_BASE + 0x00000060 , data ); +reg_write( DDR_REG_BASE + 0x00000400 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000404 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x000004b4 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x00000564 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x00000614 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x000006c4 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x00000404 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000004b4 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000564 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000614 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000006c4 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000404 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000004b4 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000564 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000614 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000006c4 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000404 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x000004b4 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x00000564 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x00000614 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x000006c4 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x00000408 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x000004b8 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x00000568 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x00000618 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x000006c8 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x00000408 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000004b8 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000568 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000618 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000006c8 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000408 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000004b8 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000568 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000618 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000006c8 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000408 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x000004b8 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x00000568 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x00000618 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x000006c8 , 0x0000100f ); +reg_read ( DDR_REG_BASE + 0x00000030 , data ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000020 ); + + + reg_read ( 0x9110309c, data ); + data=data|0x00020000; + reg_write ( 0x9110309c, data ); + + + + +reg_write( DDR_REG_BASE + 0x00000304 , 0x00000000 ); +reg_read ( DDR_REG_BASE + 0x00000030 , data ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000020 ); +reg_read ( DDR_REG_BASE + 0x00000030 , data ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000020 ); +reg_read ( DDR_REG_BASE + 0x000001c4 , data ); +reg_write( DDR_REG_BASE + 0x000001c4 , 0xd1000000 ); +reg_write( DDR_REG_BASE + 0x00000320 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000001b0 , 0x00000014 ); +reg_write( DDR_REG_BASE + 0x000001b0 , 0x00000014 ); +reg_write( DDR_REG_BASE + 0x00000304 , 0x00000002 ); +reg_read ( DDR_REG_BASE + 0x000000d0 , data ); +reg_read ( DDR_REG_BASE + 0x000001c0 , data ); +reg_read ( DDR_REG_BASE + 0x00000000 , data ); +reg_read ( DDR_REG_BASE + 0x000000dc , data ); +reg_read ( DDR_REG_BASE + 0x000000dc , data ); +reg_read ( DDR_REG_BASE + 0x000000e0 , data ); +reg_read ( DDR_REG_BASE + 0x000000e8 , data ); +reg_read ( DDR_REG_BASE + 0x000000e8 , data ); +reg_read ( DDR_REG_BASE + 0x000000e0 , data ); +reg_read ( DDR_REG_BASE + 0x000000ec , data ); +reg_read ( DDR_REG_BASE + 0x000000ec , data ); +reg_read ( DDR_REG_BASE + 0x000000d0 , data ); +reg_read ( DDR_REG_BASE + 0x000001c0 , data ); +reg_read ( DDR_REG_BASE + 0x00000000 , data ); +reg_read ( DDR_REG_BASE + 0x000000dc , data ); +reg_read ( DDR_REG_BASE + 0x000000dc , data ); +reg_read ( DDR_REG_BASE + 0x000000e0 , data ); +reg_read ( DDR_REG_BASE + 0x000000e8 , data ); +reg_read ( DDR_REG_BASE + 0x000000e8 , data ); +reg_read ( DDR_REG_BASE + 0x000000e0 , data ); +reg_read ( DDR_REG_BASE + 0x000000ec , data ); +reg_read ( DDR_REG_BASE + 0x000000ec , data ); +reg_read ( DDR_REG_BASE + 0x000000d0 , data ); + + +reg_write( DDR_REG_BASE + 0x0001005f*4 +0x02000000 , 0x000001ff ); +reg_write( DDR_REG_BASE + 0x0001015f*4 +0x02000000 , 0x000001ff ); +reg_write( DDR_REG_BASE + 0x0001105f*4 +0x02000000 , 0x000001ff ); +reg_write( DDR_REG_BASE + 0x0001115f*4 +0x02000000 , 0x000001ff ); +reg_write( DDR_REG_BASE + 0x0001205f*4 +0x02000000 , 0x000001ff ); +reg_write( DDR_REG_BASE + 0x0001215f*4 +0x02000000 , 0x000001ff ); +reg_write( DDR_REG_BASE + 0x0001305f*4 +0x02000000 , 0x000001ff ); +reg_write( DDR_REG_BASE + 0x0001315f*4 +0x02000000 , 0x000001ff ); +reg_write( DDR_REG_BASE + 0x00000055*4 +0x02000000 , 0x000001ff ); +reg_write( DDR_REG_BASE + 0x00001055*4 +0x02000000 , 0x000001ff ); +reg_write( DDR_REG_BASE + 0x00002055*4 +0x02000000 , 0x000001ff ); +reg_write( DDR_REG_BASE + 0x00003055*4 +0x02000000 , 0x000001ff ); +reg_write( DDR_REG_BASE + 0x00004055*4 +0x02000000 , 0x000001ff ); +reg_write( DDR_REG_BASE + 0x00005055*4 +0x02000000 , 0x000001ff ); +reg_write( DDR_REG_BASE + 0x00006055*4 +0x02000000 , 0x000001ff ); +reg_write( DDR_REG_BASE + 0x00007055*4 +0x02000000 , 0x000001ff ); +reg_write( DDR_REG_BASE + 0x00008055*4 +0x02000000 , 0x000001ff ); +reg_write( DDR_REG_BASE + 0x00009055*4 +0x02000000 , 0x000001ff ); +reg_write( DDR_REG_BASE + 0x000200c5*4 +0x02000000 , 0x00000006 ); +reg_write( DDR_REG_BASE + 0x0002002e*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00090204*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00020024*4 +0x02000000 , 0x000000a3 ); +reg_write( DDR_REG_BASE + 0x0002003a*4 +0x02000000 , 0x00000002 ); +reg_write( DDR_REG_BASE + 0x0002007d*4 +0x02000000 , 0x00000212 ); +reg_write( DDR_REG_BASE + 0x0002007c*4 +0x02000000 , 0x00000061 ); +reg_write( DDR_REG_BASE + 0x00020056*4 +0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x0001004d*4 +0x02000000 , 0x00000600 ); +reg_write( DDR_REG_BASE + 0x0001014d*4 +0x02000000 , 0x00000600 ); +reg_write( DDR_REG_BASE + 0x0001104d*4 +0x02000000 , 0x00000600 ); +reg_write( DDR_REG_BASE + 0x0001114d*4 +0x02000000 , 0x00000600 ); +reg_write( DDR_REG_BASE + 0x0001204d*4 +0x02000000 , 0x00000600 ); +reg_write( DDR_REG_BASE + 0x0001214d*4 +0x02000000 , 0x00000600 ); +reg_write( DDR_REG_BASE + 0x0001304d*4 +0x02000000 , 0x00000600 ); +reg_write( DDR_REG_BASE + 0x0001314d*4 +0x02000000 , 0x00000600 ); + +reg_write( DDR_REG_BASE + 0x00010049*4 +0x02000000 , 0x00000618 ); +reg_write( DDR_REG_BASE + 0x00010149*4 +0x02000000 , 0x00000618 ); +reg_write( DDR_REG_BASE + 0x00011049*4 +0x02000000 , 0x00000618 ); +reg_write( DDR_REG_BASE + 0x00011149*4 +0x02000000 , 0x00000618 ); +reg_write( DDR_REG_BASE + 0x00012049*4 +0x02000000 , 0x00000618 ); +reg_write( DDR_REG_BASE + 0x00012149*4 +0x02000000 , 0x00000618 ); +reg_write( DDR_REG_BASE + 0x00013049*4 +0x02000000 , 0x00000618 ); +reg_write( DDR_REG_BASE + 0x00013149*4 +0x02000000 , 0x00000618 ); + +//iteration +// PHY AC/CLK output impedence +//00000_00000 0x0 120 +//00001_00001 0x21 60 +//00011_00011 0x63 40 +//00111_00111 0xe7 30 +//01111_01111 0x1ef 24 +//11111_11111 0x3ff 20 + +// // [phyinit_C_initPhyConfig] Programming ATxImpedance::ADrvStrenP to 0x1 +// // [phyinit_C_initPhyConfig] Programming ATxImpedance::ADrvStrenN to 0x1 +reg_write( DDR_REG_BASE + 0x00000043*4 +0x02000000 , 0x000021 ); +reg_write( DDR_REG_BASE + 0x00001043*4 +0x02000000 , 0x000021 ); +reg_write( DDR_REG_BASE + 0x00002043*4 +0x02000000 , 0x000021 ); +reg_write( DDR_REG_BASE + 0x00003043*4 +0x02000000 , 0x000021 ); +reg_write( DDR_REG_BASE + 0x00004043*4 +0x02000000 , 0x000021 ); +reg_write( DDR_REG_BASE + 0x00005043*4 +0x02000000 , 0x000021 ); +reg_write( DDR_REG_BASE + 0x00006043*4 +0x02000000 , 0x000021 ); +reg_write( DDR_REG_BASE + 0x00007043*4 +0x02000000 , 0x000021 ); +reg_write( DDR_REG_BASE + 0x00008043*4 +0x02000000 , 0x000021 ); +reg_write( DDR_REG_BASE + 0x00009043*4 +0x02000000 , 0x000021 ); + +reg_write( DDR_REG_BASE + 0x00020018*4 +0x02000000 , 0x00000003 ); +reg_write( DDR_REG_BASE + 0x00020075*4 +0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00020050*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00020008*4 +0x02000000 , 0x0000010b ); +reg_write( DDR_REG_BASE + 0x00020088*4 +0x02000000 , 0x00000009 ); + +//iteration place +//PHY VERF +// 0x104 15% (0x14) +// 0x14c 20% (0x1a) +// 0x19c 25% (0x20) +// 0x1e4 30% (0x26) +// 0x284 40% (0x33) + +// // [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal::GlobalVrefInDAC to 0x51 +// // [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal to 0x288 +reg_write( DDR_REG_BASE + 0x000200b2*4 +0x02000000 , 0x0000019C ); + +reg_write( DDR_REG_BASE + 0x00010043*4 +0x02000000 , 0x000005a1 ); +reg_write( DDR_REG_BASE + 0x00010143*4 +0x02000000 , 0x000005a1 ); +reg_write( DDR_REG_BASE + 0x00011043*4 +0x02000000 , 0x000005a1 ); +reg_write( DDR_REG_BASE + 0x00011143*4 +0x02000000 , 0x000005a1 ); +reg_write( DDR_REG_BASE + 0x00012043*4 +0x02000000 , 0x000005a1 ); +reg_write( DDR_REG_BASE + 0x00012143*4 +0x02000000 , 0x000005a1 ); +reg_write( DDR_REG_BASE + 0x00013043*4 +0x02000000 , 0x000005a1 ); +reg_write( DDR_REG_BASE + 0x00013143*4 +0x02000000 , 0x000005a1 ); + +reg_write( DDR_REG_BASE + 0x000200fa*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00020019*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000200f0*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000200f1*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000200f2*4 +0x02000000 , 0x00004444 ); +reg_write( DDR_REG_BASE + 0x000200f3*4 +0x02000000 , 0x00008888 ); +reg_write( DDR_REG_BASE + 0x000200f4*4 +0x02000000 , 0x00005555 ); +reg_write( DDR_REG_BASE + 0x000200f5*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000200f6*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000200f7*4 +0x02000000 , 0x0000f000 ); +reg_write( DDR_REG_BASE + 0x0001004a*4 +0x02000000 , 0x00000500 ); +reg_write( DDR_REG_BASE + 0x0001104a*4 +0x02000000 , 0x00000500 ); +reg_write( DDR_REG_BASE + 0x0001204a*4 +0x02000000 , 0x00000500 ); +reg_write( DDR_REG_BASE + 0x0001304a*4 +0x02000000 , 0x00000500 ); +reg_write( DDR_REG_BASE + 0x00020025*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0002002d*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0002002c*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00010020*4 +0x02000000 , 0x00000005 ); +reg_write( DDR_REG_BASE + 0x00011020*4 +0x02000000 , 0x00000005 ); +reg_write( DDR_REG_BASE + 0x00012020*4 +0x02000000 , 0x00000005 ); +reg_write( DDR_REG_BASE + 0x00013020*4 +0x02000000 , 0x00000005 ); +reg_write( DDR_REG_BASE + 0x00020020*4 +0x02000000 , 0x00000005 ); +reg_write( DDR_REG_BASE + 0x000100d0*4 +0x02000000 , 0x00000100 ); +reg_write( DDR_REG_BASE + 0x000101d0*4 +0x02000000 , 0x00000100 ); +reg_write( DDR_REG_BASE + 0x000110d0*4 +0x02000000 , 0x00000100 ); +reg_write( DDR_REG_BASE + 0x000111d0*4 +0x02000000 , 0x00000100 ); +reg_write( DDR_REG_BASE + 0x000120d0*4 +0x02000000 , 0x00000100 ); +reg_write( DDR_REG_BASE + 0x000121d0*4 +0x02000000 , 0x00000100 ); +reg_write( DDR_REG_BASE + 0x000130d0*4 +0x02000000 , 0x00000100 ); +reg_write( DDR_REG_BASE + 0x000131d0*4 +0x02000000 , 0x00000100 ); +reg_write( DDR_REG_BASE + 0x000100c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000101c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000102c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000103c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000104c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000105c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000106c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000107c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000108c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000110c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000111c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000112c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000113c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000114c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000115c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000116c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000117c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000118c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000120c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000121c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000122c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000123c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000124c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000125c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000126c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000127c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000128c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000130c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000131c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000132c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000133c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000134c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000135c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000136c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000137c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000138c0*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x00010080*4 +0x02000000 , 0x000001de ); +reg_write( DDR_REG_BASE + 0x00010180*4 +0x02000000 , 0x000001de ); +reg_write( DDR_REG_BASE + 0x00011080*4 +0x02000000 , 0x000001de ); +reg_write( DDR_REG_BASE + 0x00011180*4 +0x02000000 , 0x000001de ); +reg_write( DDR_REG_BASE + 0x00012080*4 +0x02000000 , 0x000001de ); +reg_write( DDR_REG_BASE + 0x00012180*4 +0x02000000 , 0x000001de ); +reg_write( DDR_REG_BASE + 0x00013080*4 +0x02000000 , 0x000001de ); +reg_write( DDR_REG_BASE + 0x00013180*4 +0x02000000 , 0x000001de ); +reg_write( DDR_REG_BASE + 0x00090201*4 +0x02000000 , 0x00000800 ); +reg_write( DDR_REG_BASE + 0x00090202*4 +0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00090203*4 +0x02000000 , 0x00001400 ); +reg_write( DDR_REG_BASE + 0x00020072*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00020073*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000100ae*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000110ae*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000120ae*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000130ae*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000100af*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000110af*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000120af*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000130af*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000100aa*4 +0x02000000 , 0x00000501 ); +reg_write( DDR_REG_BASE + 0x000110aa*4 +0x02000000 , 0x0000050d ); +reg_write( DDR_REG_BASE + 0x000120aa*4 +0x02000000 , 0x00000501 ); +reg_write( DDR_REG_BASE + 0x000130aa*4 +0x02000000 , 0x0000050d ); +reg_write( DDR_REG_BASE + 0x00020077*4 +0x02000000 , 0x00000034 ); +reg_write( DDR_REG_BASE + 0x0002007c*4 +0x02000000 , 0x00000042 ); +reg_write( DDR_REG_BASE + 0x0002007d*4 +0x02000000 , 0x00000bd2 ); +reg_write( DDR_REG_BASE + 0x000400c0*4 +0x02000000 , 0x0000010f ); +reg_write( DDR_REG_BASE + 0x000200cb*4 +0x02000000 , 0x000061f0 ); +reg_write( DDR_REG_BASE + 0x00020060*4 +0x02000000 , 0x00000002 ); +//swap +reg_write( DDR_REG_BASE + 0x20100*4+0x02000000,0x5); //CA0 +reg_write( DDR_REG_BASE + 0x20101*4+0x02000000,0x4); //CA1 +reg_write( DDR_REG_BASE + 0x20102*4+0x02000000,0x3); //CA2 +reg_write( DDR_REG_BASE + 0x20103*4+0x02000000,0x2); //CA3 +reg_write( DDR_REG_BASE + 0x20104*4+0x02000000,0x1); //CA4 +reg_write( DDR_REG_BASE + 0x20105*4+0x02000000,0x0); //CA5 + +reg_write( DDR_REG_BASE + 0x100a0*4+0x02000000,0x7); //lndq =1 +reg_write( DDR_REG_BASE + 0x100a1*4+0x02000000,0x6); //CA1 =0 +reg_write( DDR_REG_BASE + 0x100a2*4+0x02000000,0x5); //CA1 =0 +reg_write( DDR_REG_BASE + 0x100a3*4+0x02000000,0x4); //CA1 =0 +reg_write( DDR_REG_BASE + 0x100a4*4+0x02000000,0x3); //CA1 =0 +reg_write( DDR_REG_BASE + 0x100a5*4+0x02000000,0x2); //CA1 =0 +reg_write( DDR_REG_BASE + 0x100a6*4+0x02000000,0x1); //CA1 =0 +reg_write( DDR_REG_BASE + 0x100a7*4+0x02000000,0x0); //CA1 =0 + +//reg_write( DDR_REG_BASE + 0x110a0*4+0x02000000,0x4); //lndq =1 +//reg_write( DDR_REG_BASE + 0x110a1*4+0x02000000,0x1); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x110a2*4+0x02000000,0x7); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x110a3*4+0x02000000,0x0); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x110a4*4+0x02000000,0x2); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x110a5*4+0x02000000,0x3); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x110a6*4+0x02000000,0x6); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x110a7*4+0x02000000,0x5); //CA1 =0 + +reg_write( DDR_REG_BASE + 0x130a0*4+0x02000000,0x1); //lndq =1 +reg_write( DDR_REG_BASE + 0x130a1*4+0x02000000,0x3); //CA1 =0 +reg_write( DDR_REG_BASE + 0x130a2*4+0x02000000,0x2); //CA1 =0 +reg_write( DDR_REG_BASE + 0x130a3*4+0x02000000,0x0); //CA1 =0 +reg_write( DDR_REG_BASE + 0x130a4*4+0x02000000,0x7); //CA1 =0 +reg_write( DDR_REG_BASE + 0x130a5*4+0x02000000,0x6); //CA1 =0 +reg_write( DDR_REG_BASE + 0x130a6*4+0x02000000,0x4); //CA1 =0 +reg_write( DDR_REG_BASE + 0x130a7*4+0x02000000,0x5); //CA1 =0 + +//reg_write( DDR_REG_BASE + 0x130a0*4+0x02000000,0x3); //lndq =1 +//reg_write( DDR_REG_BASE + 0x130a1*4+0x02000000,0x0); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x130a2*4+0x02000000,0x2); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x130a3*4+0x02000000,0x1); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x130a4*4+0x02000000,0x6); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x130a5*4+0x02000000,0x7); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x130a6*4+0x02000000,0x5); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x130a7*4+0x02000000,0x4); //CA1 =0 + +reg_write( DDR_REG_BASE + 0x120a0*4+0x02000000,0x2); //lndq =1 +reg_write( DDR_REG_BASE + 0x120a1*4+0x02000000,0x1); //CA1 =0 +reg_write( DDR_REG_BASE + 0x120a2*4+0x02000000,0x4); //CA1 =0 +reg_write( DDR_REG_BASE + 0x120a3*4+0x02000000,0x5); //CA1 =0 +reg_write( DDR_REG_BASE + 0x120a4*4+0x02000000,0x0); //CA1 =0 +reg_write( DDR_REG_BASE + 0x120a5*4+0x02000000,0x3); //CA1 =0 +reg_write( DDR_REG_BASE + 0x120a6*4+0x02000000,0x7); //CA1 =0 +reg_write( DDR_REG_BASE + 0x120a7*4+0x02000000,0x6); //CA1 =0 + +//reg_write( DDR_REG_BASE + 0x120a0*4+0x02000000,0x4); //lndq =1 +//reg_write( DDR_REG_BASE + 0x120a1*4+0x02000000,0x1); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x120a2*4+0x02000000,0x0); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x120a3*4+0x02000000,0x5); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x120a4*4+0x02000000,0x2); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x120a5*4+0x02000000,0x3); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x120a6*4+0x02000000,0x7); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x120a7*4+0x02000000,0x6); //CA1 =0 + +reg_write( DDR_REG_BASE + 0xd0000*4+0x02000000,0x0); + +reg_write( DDR_REG_BASE +0x50000*4+0x02000000,0x114); +reg_write( DDR_REG_BASE +0x50001*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50002*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50003*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50004*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50005*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50006*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50007*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50008*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50009*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5000a*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5000b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5000c*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5000d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5000e*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5000f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50010*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50011*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50012*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50013*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50014*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50015*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50016*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50017*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50018*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50019*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5001a*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5001b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5001c*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5001d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5001e*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5001f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50020*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50021*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50022*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50023*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50024*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50025*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50026*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50027*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50028*4+0x02000000,0x2069); +reg_write( DDR_REG_BASE +0x50029*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x5002a*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x5002b*4+0x02000000,0x7000); +reg_write( DDR_REG_BASE +0x5002c*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x5002d*4+0x02000000,0x7000); +reg_write( DDR_REG_BASE +0x5002e*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x5002f*4+0x02000000,0x7000); +reg_write( DDR_REG_BASE +0x50030*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50031*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50032*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50033*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50034*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50035*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50036*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50037*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50038*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50039*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50040*4+0x02000000,0x7054); +reg_write( DDR_REG_BASE +0x50041*4+0x02000000,0x7ce0); +reg_write( DDR_REG_BASE +0x50042*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x50043*4+0x02000000,0x1101); +reg_write( DDR_REG_BASE +0x50044*4+0x02000000,0x48c); +reg_write( DDR_REG_BASE +0x50045*4+0x02000000,0x2242); +reg_write( DDR_REG_BASE +0x50046*4+0x02000000,0x8042); +reg_write( DDR_REG_BASE +0x50047*4+0x02000000,0x1b01); +reg_write( DDR_REG_BASE +0x50048*4+0x02000000,0x312); +reg_write( DDR_REG_BASE +0x50049*4+0x02000000,0xf5fb); +reg_write( DDR_REG_BASE +0x5004a*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5004b*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5004c*4+0x02000000,0xc4e1); +reg_write( DDR_REG_BASE +0x5004d*4+0x02000000,0x240a); +reg_write( DDR_REG_BASE +0x5004e*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x5004f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50050*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x50051*4+0x02000000,0xc19); +reg_write( DDR_REG_BASE +0x50052*4+0x02000000,0x1703); +reg_write( DDR_REG_BASE +0x50053*4+0x02000000,0x240a); +reg_write( DDR_REG_BASE +0x50054*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x50055*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50056*4+0x02000000,0x4000); +reg_write( DDR_REG_BASE +0x50057*4+0x02000000,0xc0d); +reg_write( DDR_REG_BASE +0x50058*4+0x02000000,0x1702); +reg_write( DDR_REG_BASE +0x50059*4+0x02000000,0xc4c1); +reg_write( DDR_REG_BASE +0x5005a*4+0x02000000,0x2020); +reg_write( DDR_REG_BASE +0x5005b*4+0x02000000,0x7c0); +reg_write( DDR_REG_BASE +0x5005c*4+0x02000000,0x7fff); +reg_write( DDR_REG_BASE +0x5005d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5005e*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5005f*4+0x02000000,0xb3c8); +reg_write( DDR_REG_BASE +0x50060*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50061*4+0x02000000,0xb388); +reg_write( DDR_REG_BASE +0x50062*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50063*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50064*4+0x02000000,0xb348); +reg_write( DDR_REG_BASE +0x50065*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50066*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50067*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50068*4+0x02000000,0x748d); +reg_write( DDR_REG_BASE +0x50069*4+0x02000000,0xdd0c); +reg_write( DDR_REG_BASE +0x5006a*4+0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x5006b*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5006c*4+0x02000000,0x748d); +reg_write( DDR_REG_BASE +0x5006d*4+0x02000000,0xdd08); +reg_write( DDR_REG_BASE +0x5006e*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x5006f*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50070*4+0x02000000,0x748d); +reg_write( DDR_REG_BASE +0x50071*4+0x02000000,0x74ad); +reg_write( DDR_REG_BASE +0x50072*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x50073*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50074*4+0x02000000,0x748d); +reg_write( DDR_REG_BASE +0x50075*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x50076*4+0x02000000,0xc702); +reg_write( DDR_REG_BASE +0x50077*4+0x02000000,0xc601); +reg_write( DDR_REG_BASE +0x50078*4+0x02000000,0x24b0); +reg_write( DDR_REG_BASE +0x50079*4+0x02000000,0x334d); +reg_write( DDR_REG_BASE +0x5007a*4+0x02000000,0x24b0); +reg_write( DDR_REG_BASE +0x5007b*4+0x02000000,0x331f); +reg_write( DDR_REG_BASE +0x5007c*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5007d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5007e*4+0x02000000,0x2244); +reg_write( DDR_REG_BASE +0x5007f*4+0x02000000,0x8ffc); +reg_write( DDR_REG_BASE +0x50080*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x50081*4+0x02000000,0x7000); +reg_write( DDR_REG_BASE +0x50082*4+0x02000000,0x20e8); +reg_write( DDR_REG_BASE +0x50083*4+0x02000000,0x1a2); +reg_write( DDR_REG_BASE +0x50084*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x50085*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50086*4+0x02000000,0x212f); +reg_write( DDR_REG_BASE +0x50087*4+0x02000000,0x4b); +reg_write( DDR_REG_BASE +0x50088*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50089*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5008a*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5008b*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5008c*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x5008d*4+0x02000000,0x704d); +reg_write( DDR_REG_BASE +0x5008e*4+0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x5008f*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x50090*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50091*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x50092*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x50093*4+0x02000000,0x206a); +reg_write( DDR_REG_BASE +0x50094*4+0x02000000,0x280); +reg_write( DDR_REG_BASE +0x50095*4+0x02000000,0xb88d); +reg_write( DDR_REG_BASE +0x50096*4+0x02000000,0x2029); +reg_write( DDR_REG_BASE +0x50097*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50098*4+0x02000000,0x44db); +reg_write( DDR_REG_BASE +0x50099*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5009a*4+0x02000000,0x4000); +reg_write( DDR_REG_BASE +0x5009b*4+0x02000000,0x42db); +reg_write( DDR_REG_BASE +0x5009c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5009d*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x5009e*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x5009f*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x500a0*4+0x02000000,0x2022); +reg_write( DDR_REG_BASE +0x500a1*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x500a2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x500a3*4+0x02000000,0x3294); +reg_write( DDR_REG_BASE +0x500a4*4+0x02000000,0x2069); +reg_write( DDR_REG_BASE +0x500a5*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x500a6*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x500a7*4+0x02000000,0xf1fe); +reg_write( DDR_REG_BASE +0x500a8*4+0x02000000,0xc3e1); +reg_write( DDR_REG_BASE +0x500a9*4+0x02000000,0xc2e1); +reg_write( DDR_REG_BASE +0x500aa*4+0x02000000,0xc1e1); +reg_write( DDR_REG_BASE +0x500ab*4+0x02000000,0xc0e1); +reg_write( DDR_REG_BASE +0x500ac*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x500ad*4+0x02000000,0xc5e1); +reg_write( DDR_REG_BASE +0x500ae*4+0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x500af*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x500b0*4+0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x500b1*4+0x02000000,0xdc14); +reg_write( DDR_REG_BASE +0x500b2*4+0x02000000,0x77f); +reg_write( DDR_REG_BASE +0x500b3*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x500b4*4+0x02000000,0xda25); +reg_write( DDR_REG_BASE +0x500b5*4+0x02000000,0xba9f); +reg_write( DDR_REG_BASE +0x500b6*4+0x02000000,0x8a60); +reg_write( DDR_REG_BASE +0x500b7*4+0x02000000,0x1233); +reg_write( DDR_REG_BASE +0x500b8*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x500b9*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x500ba*4+0x02000000,0x1aea); +reg_write( DDR_REG_BASE +0x500bb*4+0x02000000,0x8002); +reg_write( DDR_REG_BASE +0x500bc*4+0x02000000,0x12ed); +reg_write( DDR_REG_BASE +0x500bd*4+0x02000000,0x8080); +reg_write( DDR_REG_BASE +0x500be*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x500bf*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x500c0*4+0x02000000,0xf20d); +reg_write( DDR_REG_BASE +0x500c1*4+0x02000000,0xc085); +reg_write( DDR_REG_BASE +0x500c2*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x500c3*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x500c4*4+0x02000000,0x872); +reg_write( DDR_REG_BASE +0x500c5*4+0x02000000,0x360); +reg_write( DDR_REG_BASE +0x500c6*4+0x02000000,0xc185); +reg_write( DDR_REG_BASE +0x500c7*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x500c8*4+0x02000000,0x402); +reg_write( DDR_REG_BASE +0x500c9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x500ca*4+0x02000000,0xd2a); +reg_write( DDR_REG_BASE +0x500cb*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x500cc*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x500cd*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x500ce*4+0x02000000,0xc86); +reg_write( DDR_REG_BASE +0x500cf*4+0x02000000,0x2e0); +reg_write( DDR_REG_BASE +0x500d0*4+0x02000000,0x1a09); +reg_write( DDR_REG_BASE +0x500d1*4+0x02000000,0x3003); +reg_write( DDR_REG_BASE +0x500d2*4+0x02000000,0xfb6); +reg_write( DDR_REG_BASE +0x500d3*4+0x02000000,0x320); +reg_write( DDR_REG_BASE +0x500d4*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x500d5*4+0x02000000,0x25ab); +reg_write( DDR_REG_BASE +0x500d6*4+0x02000000,0x10c4); +reg_write( DDR_REG_BASE +0x500d7*4+0x02000000,0x7fff); +reg_write( DDR_REG_BASE +0x500d8*4+0x02000000,0xf1ff); +reg_write( DDR_REG_BASE +0x500d9*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x500da*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x500db*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x500dc*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x500dd*4+0x02000000,0xc1a6); +reg_write( DDR_REG_BASE +0x500de*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x500df*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x500e0*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x500e1*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x500e2*4+0x02000000,0xc243); +reg_write( DDR_REG_BASE +0x500e3*4+0x02000000,0xa0c0); +reg_write( DDR_REG_BASE +0x500e4*4+0x02000000,0xd83f); +reg_write( DDR_REG_BASE +0x500e5*4+0x02000000,0xc064); +reg_write( DDR_REG_BASE +0x500e6*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x500e7*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x500e8*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x500e9*4+0x02000000,0x88a0); +reg_write( DDR_REG_BASE +0x500ea*4+0x02000000,0x1c11); +reg_write( DDR_REG_BASE +0x500eb*4+0x02000000,0x3382); +reg_write( DDR_REG_BASE +0x500ec*4+0x02000000,0xf054); +reg_write( DDR_REG_BASE +0x500ed*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x500ee*4+0x02000000,0x89d); +reg_write( DDR_REG_BASE +0x500ef*4+0x02000000,0x6ee); +reg_write( DDR_REG_BASE +0x500f0*4+0x02000000,0xc084); +reg_write( DDR_REG_BASE +0x500f1*4+0x02000000,0x60c8); +reg_write( DDR_REG_BASE +0x500f2*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x500f3*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x500f4*4+0x02000000,0xd83f); +reg_write( DDR_REG_BASE +0x500f5*4+0x02000000,0xb19); +reg_write( DDR_REG_BASE +0x500f6*4+0x02000000,0x30b0); +reg_write( DDR_REG_BASE +0x500f7*4+0x02000000,0x7826); +reg_write( DDR_REG_BASE +0x500f8*4+0x02000000,0xb19); +reg_write( DDR_REG_BASE +0x500f9*4+0x02000000,0x3070); +reg_write( DDR_REG_BASE +0x500fa*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x500fb*4+0x02000000,0xb1d); +reg_write( DDR_REG_BASE +0x500fc*4+0x02000000,0x3031); +reg_write( DDR_REG_BASE +0x500fd*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x500fe*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x500ff*4+0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x50100*4+0x02000000,0xc300); +reg_write( DDR_REG_BASE +0x50101*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x50102*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x50103*4+0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x50104*4+0x02000000,0xc200); +reg_write( DDR_REG_BASE +0x50105*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x50106*4+0x02000000,0xb42); +reg_write( DDR_REG_BASE +0x50107*4+0x02000000,0x380); +reg_write( DDR_REG_BASE +0x50108*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50109*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5010a*4+0x02000000,0x4e20); +reg_write( DDR_REG_BASE +0x5010b*4+0x02000000,0xeca); +reg_write( DDR_REG_BASE +0x5010c*4+0x02000000,0x1a0); +reg_write( DDR_REG_BASE +0x5010d*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5010e*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x5010f*4+0x02000000,0xf026); +reg_write( DDR_REG_BASE +0x50110*4+0x02000000,0x255f); +reg_write( DDR_REG_BASE +0x50111*4+0x02000000,0x1402); +reg_write( DDR_REG_BASE +0x50112*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50113*4+0x02000000,0x7a16); +reg_write( DDR_REG_BASE +0x50114*4+0x02000000,0x62f8); +reg_write( DDR_REG_BASE +0x50115*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x50116*4+0x02000000,0x8824); +reg_write( DDR_REG_BASE +0x50117*4+0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x50118*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50119*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5011a*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x5011b*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5011c*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5011d*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x5011e*4+0x02000000,0x54); +reg_write( DDR_REG_BASE +0x5011f*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x50120*4+0x02000000,0xcc2); +reg_write( DDR_REG_BASE +0x50121*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50122*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x50123*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x50124*4+0x02000000,0xb8c5); +reg_write( DDR_REG_BASE +0x50125*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x50126*4+0x02000000,0x7907); +reg_write( DDR_REG_BASE +0x50127*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x50128*4+0x02000000,0x3200); +reg_write( DDR_REG_BASE +0x50129*4+0x02000000,0x4220); +reg_write( DDR_REG_BASE +0x5012a*4+0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x5012b*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x5012c*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x5012d*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x5012e*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x5012f*4+0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x50130*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x50131*4+0x02000000,0x8020); +reg_write( DDR_REG_BASE +0x50132*4+0x02000000,0x7945); +reg_write( DDR_REG_BASE +0x50133*4+0x02000000,0xa020); +reg_write( DDR_REG_BASE +0x50134*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50135*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50136*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50137*4+0x02000000,0x784); +reg_write( DDR_REG_BASE +0x50138*4+0x02000000,0x78b4); +reg_write( DDR_REG_BASE +0x50139*4+0x02000000,0x6028); +reg_write( DDR_REG_BASE +0x5013a*4+0x02000000,0xfad); +reg_write( DDR_REG_BASE +0x5013b*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5013c*4+0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x5013d*4+0x02000000,0xb63); +reg_write( DDR_REG_BASE +0x5013e*4+0x02000000,0xb0d4); +reg_write( DDR_REG_BASE +0x5013f*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x50140*4+0x02000000,0xefb); +reg_write( DDR_REG_BASE +0x50141*4+0x02000000,0x90b4); +reg_write( DDR_REG_BASE +0x50142*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x50143*4+0x02000000,0xc0a6); +reg_write( DDR_REG_BASE +0x50144*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50145*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50146*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50147*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50148*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50149*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5014a*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5014b*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x5014c*4+0x02000000,0x320d); +reg_write( DDR_REG_BASE +0x5014d*4+0x02000000,0x216f); +reg_write( DDR_REG_BASE +0x5014e*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x5014f*4+0x02000000,0x1154); +reg_write( DDR_REG_BASE +0x50150*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x50151*4+0x02000000,0x89a0); +reg_write( DDR_REG_BASE +0x50152*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x50153*4+0x02000000,0x1121); +reg_write( DDR_REG_BASE +0x50154*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x50155*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x50156*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x50157*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50158*4+0x02000000,0x334); +reg_write( DDR_REG_BASE +0x50159*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x5015a*4+0x02000000,0xe5a); +reg_write( DDR_REG_BASE +0x5015b*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x5015c*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5015d*4+0x02000000,0xc09c); +reg_write( DDR_REG_BASE +0x5015e*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5015f*4+0x02000000,0xc089); +reg_write( DDR_REG_BASE +0x50160*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x50161*4+0x02000000,0x3d41); +reg_write( DDR_REG_BASE +0x50162*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x50163*4+0x02000000,0x3f82); +reg_write( DDR_REG_BASE +0x50164*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50165*4+0x02000000,0x19c); +reg_write( DDR_REG_BASE +0x50166*4+0x02000000,0xece); +reg_write( DDR_REG_BASE +0x50167*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50168*4+0x02000000,0x2440); +reg_write( DDR_REG_BASE +0x50169*4+0x02000000,0x3fc3); +reg_write( DDR_REG_BASE +0x5016a*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x5016b*4+0x02000000,0xc341); +reg_write( DDR_REG_BASE +0x5016c*4+0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x5016d*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x5016e*4+0x02000000,0x601); +reg_write( DDR_REG_BASE +0x5016f*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x50170*4+0x02000000,0x6059); +reg_write( DDR_REG_BASE +0x50171*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50172*4+0x02000000,0xa900); +reg_write( DDR_REG_BASE +0x50173*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x50174*4+0x02000000,0xaf3); +reg_write( DDR_REG_BASE +0x50175*4+0x02000000,0x8634); +reg_write( DDR_REG_BASE +0x50176*4+0x02000000,0xc09f); +reg_write( DDR_REG_BASE +0x50177*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x50178*4+0x02000000,0xbf9); +reg_write( DDR_REG_BASE +0x50179*4+0x02000000,0x8334); +reg_write( DDR_REG_BASE +0x5017a*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5017b*4+0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x5017c*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x5017d*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5017e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5017f*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50180*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x50181*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50182*4+0x02000000,0x9001); +reg_write( DDR_REG_BASE +0x50183*4+0x02000000,0xe100); +reg_write( DDR_REG_BASE +0x50184*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x50185*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x50186*4+0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x50187*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x50188*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x50189*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5018a*4+0x02000000,0xb887); +reg_write( DDR_REG_BASE +0x5018b*4+0x02000000,0xdd6); +reg_write( DDR_REG_BASE +0x5018c*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5018d*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x5018e*4+0x02000000,0xe12); +reg_write( DDR_REG_BASE +0x5018f*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50190*4+0x02000000,0xc029); +reg_write( DDR_REG_BASE +0x50191*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x50192*4+0x02000000,0xe0a); +reg_write( DDR_REG_BASE +0x50193*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50194*4+0x02000000,0xc02b); +reg_write( DDR_REG_BASE +0x50195*4+0x02000000,0x33f); +reg_write( DDR_REG_BASE +0x50196*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50197*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x50198*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x50199*4+0x02000000,0x84d); +reg_write( DDR_REG_BASE +0x5019a*4+0x02000000,0xb5); +reg_write( DDR_REG_BASE +0x5019b*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x5019c*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5019d*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5019e*4+0x02000000,0x7003); +reg_write( DDR_REG_BASE +0x5019f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x501a0*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x501a1*4+0x02000000,0xc208); +reg_write( DDR_REG_BASE +0x501a2*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x501a3*4+0x02000000,0xe); +reg_write( DDR_REG_BASE +0x501a4*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x501a5*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x501a6*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x501a7*4+0x02000000,0x4a); +reg_write( DDR_REG_BASE +0x501a8*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x501a9*4+0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x501aa*4+0x02000000,0x7e07); +reg_write( DDR_REG_BASE +0x501ab*4+0x02000000,0xc8e); +reg_write( DDR_REG_BASE +0x501ac*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x501ad*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x501ae*4+0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x501af*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x501b0*4+0x02000000,0x47a9); +reg_write( DDR_REG_BASE +0x501b1*4+0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x501b2*4+0x02000000,0x17de); +reg_write( DDR_REG_BASE +0x501b3*4+0x02000000,0xe11); +reg_write( DDR_REG_BASE +0x501b4*4+0x02000000,0x3010); +reg_write( DDR_REG_BASE +0x501b5*4+0x02000000,0x2642); +reg_write( DDR_REG_BASE +0x501b6*4+0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x501b7*4+0x02000000,0xeff); +reg_write( DDR_REG_BASE +0x501b8*4+0x02000000,0xb031); +reg_write( DDR_REG_BASE +0x501b9*4+0x02000000,0x7ffb); +reg_write( DDR_REG_BASE +0x501ba*4+0x02000000,0x84b); +reg_write( DDR_REG_BASE +0x501bb*4+0x02000000,0x38f); +reg_write( DDR_REG_BASE +0x501bc*4+0x02000000,0x2e9); +reg_write( DDR_REG_BASE +0x501bd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x501be*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x501bf*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x501c0*4+0x02000000,0x7342); +reg_write( DDR_REG_BASE +0x501c1*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x501c2*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x501c3*4+0x02000000,0xc204); +reg_write( DDR_REG_BASE +0x501c4*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x501c5*4+0x02000000,0x8e); +reg_write( DDR_REG_BASE +0x501c6*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x501c7*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x501c8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x501c9*4+0x02000000,0x7d); +reg_write( DDR_REG_BASE +0x501ca*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x501cb*4+0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x501cc*4+0x02000000,0x7e07); +reg_write( DDR_REG_BASE +0x501cd*4+0x02000000,0xc4a); +reg_write( DDR_REG_BASE +0x501ce*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x501cf*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x501d0*4+0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x501d1*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x501d2*4+0x02000000,0x47a9); +reg_write( DDR_REG_BASE +0x501d3*4+0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x501d4*4+0x02000000,0x17cd); +reg_write( DDR_REG_BASE +0x501d5*4+0x02000000,0xed06); +reg_write( DDR_REG_BASE +0x501d6*4+0x02000000,0xbd61); +reg_write( DDR_REG_BASE +0x501d7*4+0x02000000,0xd01); +reg_write( DDR_REG_BASE +0x501d8*4+0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x501d9*4+0x02000000,0x7ffb); +reg_write( DDR_REG_BASE +0x501da*4+0x02000000,0x2011); +reg_write( DDR_REG_BASE +0x501db*4+0x02000000,0x8380); +reg_write( DDR_REG_BASE +0x501dc*4+0x02000000,0x2a8); +reg_write( DDR_REG_BASE +0x501dd*4+0x02000000,0x21); +reg_write( DDR_REG_BASE +0x501de*4+0x02000000,0x72ad); +reg_write( DDR_REG_BASE +0x501df*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x501e0*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x501e1*4+0x02000000,0xf00b); +reg_write( DDR_REG_BASE +0x501e2*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x501e3*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x501e4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x501e5*4+0x02000000,0x1b4); +reg_write( DDR_REG_BASE +0x501e6*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x501e7*4+0x02000000,0x19c0); +reg_write( DDR_REG_BASE +0x501e8*4+0x02000000,0x82); +reg_write( DDR_REG_BASE +0x501e9*4+0x02000000,0xa940); +reg_write( DDR_REG_BASE +0x501ea*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x501eb*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x501ec*4+0x02000000,0x8003); +reg_write( DDR_REG_BASE +0x501ed*4+0x02000000,0xf7b6); +reg_write( DDR_REG_BASE +0x501ee*4+0x02000000,0xf3a); +reg_write( DDR_REG_BASE +0x501ef*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x501f0*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x501f1*4+0x02000000,0xf36); +reg_write( DDR_REG_BASE +0x501f2*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x501f3*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x501f4*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x501f5*4+0x02000000,0x7043); +reg_write( DDR_REG_BASE +0x501f6*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x501f7*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x501f8*4+0x02000000,0xf26); +reg_write( DDR_REG_BASE +0x501f9*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x501fa*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x501fb*4+0x02000000,0x78ef); +reg_write( DDR_REG_BASE +0x501fc*4+0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x501fd*4+0x02000000,0xfee); +reg_write( DDR_REG_BASE +0x501fe*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x501ff*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x50200*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50201*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x50202*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50203*4+0x02000000,0x73c2); +reg_write( DDR_REG_BASE +0x50204*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50205*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x50206*4+0x02000000,0xd86); +reg_write( DDR_REG_BASE +0x50207*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50208*4+0x02000000,0xf06); +reg_write( DDR_REG_BASE +0x50209*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5020a*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x5020b*4+0x02000000,0x43f9); +reg_write( DDR_REG_BASE +0x5020c*4+0x02000000,0xf04e); +reg_write( DDR_REG_BASE +0x5020d*4+0x02000000,0x143f); +reg_write( DDR_REG_BASE +0x5020e*4+0x02000000,0x3082); +reg_write( DDR_REG_BASE +0x5020f*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x50210*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50211*4+0x02000000,0x2353); +reg_write( DDR_REG_BASE +0x50212*4+0x02000000,0x3101); +reg_write( DDR_REG_BASE +0x50213*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x50214*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50215*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x50216*4+0x02000000,0x6068); +reg_write( DDR_REG_BASE +0x50217*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x50218*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50219*4+0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x5021a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5021b*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x5021c*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5021d*4+0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x5021e*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5021f*4+0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x50220*4+0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x50221*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x50222*4+0x02000000,0xbe9); +reg_write( DDR_REG_BASE +0x50223*4+0x02000000,0x80a4); +reg_write( DDR_REG_BASE +0x50224*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x50225*4+0x02000000,0x3d40); +reg_write( DDR_REG_BASE +0x50226*4+0x02000000,0xc9e); +reg_write( DDR_REG_BASE +0x50227*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x50228*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x50229*4+0x02000000,0xc190); +reg_write( DDR_REG_BASE +0x5022a*4+0x02000000,0xd62); +reg_write( DDR_REG_BASE +0x5022b*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5022c*4+0x02000000,0xda07); +reg_write( DDR_REG_BASE +0x5022d*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5022e*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5022f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50230*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x50231*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x50232*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x50233*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50234*4+0x02000000,0x1b4); +reg_write( DDR_REG_BASE +0x50235*4+0x02000000,0xc210); +reg_write( DDR_REG_BASE +0x50236*4+0x02000000,0x209f); +reg_write( DDR_REG_BASE +0x50237*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x50238*4+0x02000000,0x224a); +reg_write( DDR_REG_BASE +0x50239*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x5023a*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x5023b*4+0x02000000,0x7163); +reg_write( DDR_REG_BASE +0x5023c*4+0x02000000,0x8960); +reg_write( DDR_REG_BASE +0x5023d*4+0x02000000,0x2253); +reg_write( DDR_REG_BASE +0x5023e*4+0x02000000,0x140); +reg_write( DDR_REG_BASE +0x5023f*4+0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x50240*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x50241*4+0x02000000,0xa900); +reg_write( DDR_REG_BASE +0x50242*4+0x02000000,0x1140); +reg_write( DDR_REG_BASE +0x50243*4+0x02000000,0x83); +reg_write( DDR_REG_BASE +0x50244*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x50245*4+0x02000000,0x2242); +reg_write( DDR_REG_BASE +0x50246*4+0x02000000,0x104a); +reg_write( DDR_REG_BASE +0x50247*4+0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x50248*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x50249*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5024a*4+0x02000000,0xb8c5); +reg_write( DDR_REG_BASE +0x5024b*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x5024c*4+0x02000000,0x1940); +reg_write( DDR_REG_BASE +0x5024d*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x5024e*4+0x02000000,0x1180); +reg_write( DDR_REG_BASE +0x5024f*4+0x02000000,0x83); +reg_write( DDR_REG_BASE +0x50250*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x50251*4+0x02000000,0xda10); +reg_write( DDR_REG_BASE +0x50252*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x50253*4+0x02000000,0xa01); +reg_write( DDR_REG_BASE +0x50254*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x50255*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50256*4+0x02000000,0xb8c5); +reg_write( DDR_REG_BASE +0x50257*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x50258*4+0x02000000,0x1980); +reg_write( DDR_REG_BASE +0x50259*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x5025a*4+0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x5025b*4+0x02000000,0xb001); +reg_write( DDR_REG_BASE +0x5025c*4+0x02000000,0x762); +reg_write( DDR_REG_BASE +0x5025d*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x5025e*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x5025f*4+0x02000000,0x6c0); +reg_write( DDR_REG_BASE +0x50260*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x50261*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50262*4+0x02000000,0x7043); +reg_write( DDR_REG_BASE +0x50263*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50264*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x50265*4+0x02000000,0xc22); +reg_write( DDR_REG_BASE +0x50266*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50267*4+0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x50268*4+0x02000000,0xa5a); +reg_write( DDR_REG_BASE +0x50269*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5026a*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x5026b*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x5026c*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5026d*4+0x02000000,0x94); +reg_write( DDR_REG_BASE +0x5026e*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5026f*4+0x02000000,0x9e2); +reg_write( DDR_REG_BASE +0x50270*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50271*4+0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x50272*4+0x02000000,0xf0ba); +reg_write( DDR_REG_BASE +0x50273*4+0x02000000,0x66e8); +reg_write( DDR_REG_BASE +0x50274*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x50275*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x50276*4+0x02000000,0xf2b5); +reg_write( DDR_REG_BASE +0x50277*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x50278*4+0x02000000,0x7912); +reg_write( DDR_REG_BASE +0x50279*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5027a*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5027b*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5027c*4+0x02000000,0x1b); +reg_write( DDR_REG_BASE +0x5027d*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5027e*4+0x02000000,0x7812); +reg_write( DDR_REG_BASE +0x5027f*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50280*4+0x02000000,0xdab); +reg_write( DDR_REG_BASE +0x50281*4+0x02000000,0x103e); +reg_write( DDR_REG_BASE +0x50282*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x50283*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x50284*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50285*4+0x02000000,0x95); +reg_write( DDR_REG_BASE +0x50286*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50287*4+0x02000000,0x9b2); +reg_write( DDR_REG_BASE +0x50288*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50289*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x5028a*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x5028b*4+0x02000000,0xf040); +reg_write( DDR_REG_BASE +0x5028c*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5028d*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x5028e*4+0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x5028f*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x50290*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x50291*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50292*4+0x02000000,0x1b4); +reg_write( DDR_REG_BASE +0x50293*4+0x02000000,0x6048); +reg_write( DDR_REG_BASE +0x50294*4+0x02000000,0x792f); +reg_write( DDR_REG_BASE +0x50295*4+0x02000000,0xec06); +reg_write( DDR_REG_BASE +0x50296*4+0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x50297*4+0x02000000,0xc01); +reg_write( DDR_REG_BASE +0x50298*4+0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x50299*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5029a*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x5029b*4+0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x5029c*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x5029d*4+0x02000000,0x7cc); +reg_write( DDR_REG_BASE +0x5029e*4+0x02000000,0xec05); +reg_write( DDR_REG_BASE +0x5029f*4+0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x502a0*4+0x02000000,0xcff); +reg_write( DDR_REG_BASE +0x502a1*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x502a2*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x502a3*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x502a4*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x502a5*4+0x02000000,0xbd7); +reg_write( DDR_REG_BASE +0x502a6*4+0x02000000,0x8234); +reg_write( DDR_REG_BASE +0x502a7*4+0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x502a8*4+0x02000000,0x17cc); +reg_write( DDR_REG_BASE +0x502a9*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x502aa*4+0x02000000,0x829); +reg_write( DDR_REG_BASE +0x502ab*4+0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x502ac*4+0x02000000,0x66ea); +reg_write( DDR_REG_BASE +0x502ad*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x502ae*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x502af*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x502b0*4+0x02000000,0x19c); +reg_write( DDR_REG_BASE +0x502b1*4+0x02000000,0x6048); +reg_write( DDR_REG_BASE +0x502b2*4+0x02000000,0xc29f); +reg_write( DDR_REG_BASE +0x502b3*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x502b4*4+0x02000000,0x600); +reg_write( DDR_REG_BASE +0x502b5*4+0x02000000,0x621a); +reg_write( DDR_REG_BASE +0x502b6*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x502b7*4+0x02000000,0x6c2); +reg_write( DDR_REG_BASE +0x502b8*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x502b9*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x502ba*4+0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x502bb*4+0x02000000,0x8840); +reg_write( DDR_REG_BASE +0x502bc*4+0x02000000,0x7a25); +reg_write( DDR_REG_BASE +0x502bd*4+0x02000000,0xa840); +reg_write( DDR_REG_BASE +0x502be*4+0x02000000,0xcaa); +reg_write( DDR_REG_BASE +0x502bf*4+0x02000000,0x2a0); +reg_write( DDR_REG_BASE +0x502c0*4+0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x502c1*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x502c2*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x502c3*4+0x02000000,0x96); +reg_write( DDR_REG_BASE +0x502c4*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x502c5*4+0x02000000,0x936); +reg_write( DDR_REG_BASE +0x502c6*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x502c7*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x502c8*4+0x02000000,0x2340); +reg_write( DDR_REG_BASE +0x502c9*4+0x02000000,0x321b); +reg_write( DDR_REG_BASE +0x502ca*4+0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x502cb*4+0x02000000,0xb003); +reg_write( DDR_REG_BASE +0x502cc*4+0x02000000,0x780); +reg_write( DDR_REG_BASE +0x502cd*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x502ce*4+0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x502cf*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x502d0*4+0x02000000,0x97); +reg_write( DDR_REG_BASE +0x502d1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x502d2*4+0x02000000,0x91a); +reg_write( DDR_REG_BASE +0x502d3*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x502d4*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x502d5*4+0x02000000,0xdaf); +reg_write( DDR_REG_BASE +0x502d6*4+0x02000000,0x107e); +reg_write( DDR_REG_BASE +0x502d7*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x502d8*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x502d9*4+0x02000000,0x98); +reg_write( DDR_REG_BASE +0x502da*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x502db*4+0x02000000,0x90a); +reg_write( DDR_REG_BASE +0x502dc*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x502dd*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x502de*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x502df*4+0x02000000,0xf042); +reg_write( DDR_REG_BASE +0x502e0*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x502e1*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x502e2*4+0x02000000,0xf019); +reg_write( DDR_REG_BASE +0x502e3*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x502e4*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x502e5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x502e6*4+0x02000000,0x1b4); +reg_write( DDR_REG_BASE +0x502e7*4+0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x502e8*4+0x02000000,0x10c0); +reg_write( DDR_REG_BASE +0x502e9*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x502ea*4+0x02000000,0x792f); +reg_write( DDR_REG_BASE +0x502eb*4+0x02000000,0xec06); +reg_write( DDR_REG_BASE +0x502ec*4+0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x502ed*4+0x02000000,0xc01); +reg_write( DDR_REG_BASE +0x502ee*4+0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x502ef*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x502f0*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x502f1*4+0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x502f2*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x502f3*4+0x02000000,0x7cc); +reg_write( DDR_REG_BASE +0x502f4*4+0x02000000,0xec05); +reg_write( DDR_REG_BASE +0x502f5*4+0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x502f6*4+0x02000000,0xcff); +reg_write( DDR_REG_BASE +0x502f7*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x502f8*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x502f9*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x502fa*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x502fb*4+0x02000000,0xbd3); +reg_write( DDR_REG_BASE +0x502fc*4+0x02000000,0x8234); +reg_write( DDR_REG_BASE +0x502fd*4+0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x502fe*4+0x02000000,0x17cc); +reg_write( DDR_REG_BASE +0x502ff*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50300*4+0x02000000,0x82b); +reg_write( DDR_REG_BASE +0x50301*4+0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x50302*4+0x02000000,0xc089); +reg_write( DDR_REG_BASE +0x50303*4+0x02000000,0x60f8); +reg_write( DDR_REG_BASE +0x50304*4+0x02000000,0x8848); +reg_write( DDR_REG_BASE +0x50305*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x50306*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x50307*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50308*4+0x02000000,0x19c); +reg_write( DDR_REG_BASE +0x50309*4+0x02000000,0x6048); +reg_write( DDR_REG_BASE +0x5030a*4+0x02000000,0xc29f); +reg_write( DDR_REG_BASE +0x5030b*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x5030c*4+0x02000000,0x600); +reg_write( DDR_REG_BASE +0x5030d*4+0x02000000,0x621a); +reg_write( DDR_REG_BASE +0x5030e*4+0x02000000,0x78dd); +reg_write( DDR_REG_BASE +0x5030f*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50310*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50311*4+0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x50312*4+0x02000000,0x8840); +reg_write( DDR_REG_BASE +0x50313*4+0x02000000,0x7a25); +reg_write( DDR_REG_BASE +0x50314*4+0x02000000,0xa840); +reg_write( DDR_REG_BASE +0x50315*4+0x02000000,0xbfe); +reg_write( DDR_REG_BASE +0x50316*4+0x02000000,0x2a0); +reg_write( DDR_REG_BASE +0x50317*4+0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x50318*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x50319*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5031a*4+0x02000000,0x99); +reg_write( DDR_REG_BASE +0x5031b*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5031c*4+0x02000000,0x886); +reg_write( DDR_REG_BASE +0x5031d*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5031e*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x5031f*4+0x02000000,0xe608); +reg_write( DDR_REG_BASE +0x50320*4+0x02000000,0x268c); +reg_write( DDR_REG_BASE +0x50321*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x50322*4+0x02000000,0x77c); +reg_write( DDR_REG_BASE +0x50323*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x50324*4+0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x50325*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50326*4+0x02000000,0x9a); +reg_write( DDR_REG_BASE +0x50327*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50328*4+0x02000000,0x86e); +reg_write( DDR_REG_BASE +0x50329*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5032a*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x5032b*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x5032c*4+0x02000000,0x75f5); +reg_write( DDR_REG_BASE +0x5032d*4+0x02000000,0x68e); +reg_write( DDR_REG_BASE +0x5032e*4+0x02000000,0xffee); +reg_write( DDR_REG_BASE +0x5032f*4+0x02000000,0xc689); +reg_write( DDR_REG_BASE +0x50330*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x50331*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x50332*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x50333*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x50334*4+0x02000000,0x7414); +reg_write( DDR_REG_BASE +0x50335*4+0x02000000,0x4c8); +reg_write( DDR_REG_BASE +0x50336*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x50337*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50338*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x50339*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x5033a*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5033b*4+0x02000000,0xa76); +reg_write( DDR_REG_BASE +0x5033c*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5033d*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x5033e*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x5033f*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x50340*4+0x02000000,0xf0e4); +reg_write( DDR_REG_BASE +0x50341*4+0x02000000,0x143f); +reg_write( DDR_REG_BASE +0x50342*4+0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x50343*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x50344*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50345*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50346*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x50347*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x50348*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x50349*4+0x02000000,0xf096); +reg_write( DDR_REG_BASE +0x5034a*4+0x02000000,0x60e8); +reg_write( DDR_REG_BASE +0x5034b*4+0x02000000,0x260c); +reg_write( DDR_REG_BASE +0x5034c*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x5034d*4+0x02000000,0xf491); +reg_write( DDR_REG_BASE +0x5034e*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5034f*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x50350*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x50351*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50352*4+0x02000000,0x4758); +reg_write( DDR_REG_BASE +0x50353*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50354*4+0x02000000,0xf033); +reg_write( DDR_REG_BASE +0x50355*4+0x02000000,0xf20c); +reg_write( DDR_REG_BASE +0x50356*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x50357*4+0x02000000,0x7cc); +reg_write( DDR_REG_BASE +0x50358*4+0x02000000,0x43e3); +reg_write( DDR_REG_BASE +0x50359*4+0x02000000,0xec06); +reg_write( DDR_REG_BASE +0x5035a*4+0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x5035b*4+0x02000000,0xc01); +reg_write( DDR_REG_BASE +0x5035c*4+0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x5035d*4+0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x5035e*4+0x02000000,0xbbc0); +reg_write( DDR_REG_BASE +0x5035f*4+0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x50360*4+0x02000000,0x275a); +reg_write( DDR_REG_BASE +0x50361*4+0x02000000,0x1603); +reg_write( DDR_REG_BASE +0x50362*4+0x02000000,0xc49f); +reg_write( DDR_REG_BASE +0x50363*4+0x02000000,0x647c); +reg_write( DDR_REG_BASE +0x50364*4+0x02000000,0x7b1d); +reg_write( DDR_REG_BASE +0x50365*4+0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x50366*4+0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x50367*4+0x02000000,0x2432); +reg_write( DDR_REG_BASE +0x50368*4+0x02000000,0x10df); +reg_write( DDR_REG_BASE +0x50369*4+0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x5036a*4+0x02000000,0x3043); +reg_write( DDR_REG_BASE +0x5036b*4+0x02000000,0x7c30); +reg_write( DDR_REG_BASE +0x5036c*4+0x02000000,0x248c); +reg_write( DDR_REG_BASE +0x5036d*4+0x02000000,0x9fc3); +reg_write( DDR_REG_BASE +0x5036e*4+0x02000000,0xf408); +reg_write( DDR_REG_BASE +0x5036f*4+0x02000000,0xe0df); +reg_write( DDR_REG_BASE +0x50370*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x50371*4+0x02000000,0xf716); +reg_write( DDR_REG_BASE +0x50372*4+0x02000000,0xeb94); +reg_write( DDR_REG_BASE +0x50373*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50374*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x50375*4+0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x50376*4+0x02000000,0x7074); +reg_write( DDR_REG_BASE +0x50377*4+0x02000000,0x22c0); +reg_write( DDR_REG_BASE +0x50378*4+0x02000000,0x61); +reg_write( DDR_REG_BASE +0x50379*4+0x02000000,0xf20e); +reg_write( DDR_REG_BASE +0x5037a*4+0x02000000,0xdb3f); +reg_write( DDR_REG_BASE +0x5037b*4+0x02000000,0x233c); +reg_write( DDR_REG_BASE +0x5037c*4+0x02000000,0xb); +reg_write( DDR_REG_BASE +0x5037d*4+0x02000000,0x7c50); +reg_write( DDR_REG_BASE +0x5037e*4+0x02000000,0x7bb0); +reg_write( DDR_REG_BASE +0x5037f*4+0x02000000,0x233c); +reg_write( DDR_REG_BASE +0x50380*4+0x02000000,0x303); +reg_write( DDR_REG_BASE +0x50381*4+0x02000000,0x230b); +reg_write( DDR_REG_BASE +0x50382*4+0x02000000,0x82c0); +reg_write( DDR_REG_BASE +0x50383*4+0x02000000,0x755c); +reg_write( DDR_REG_BASE +0x50384*4+0x02000000,0x763c); +reg_write( DDR_REG_BASE +0x50385*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x50386*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x50387*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x50388*4+0x02000000,0x8003); +reg_write( DDR_REG_BASE +0x50389*4+0x02000000,0x79a); +reg_write( DDR_REG_BASE +0x5038a*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x5038b*4+0x02000000,0x2053); +reg_write( DDR_REG_BASE +0x5038c*4+0x02000000,0x8083); +reg_write( DDR_REG_BASE +0x5038d*4+0x02000000,0x78b0); +reg_write( DDR_REG_BASE +0x5038e*4+0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x5038f*4+0x02000000,0xf088); +reg_write( DDR_REG_BASE +0x50390*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x50391*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50392*4+0x02000000,0x20c5); +reg_write( DDR_REG_BASE +0x50393*4+0x02000000,0x61); +reg_write( DDR_REG_BASE +0x50394*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x50395*4+0x02000000,0x72bd); +reg_write( DDR_REG_BASE +0x50396*4+0x02000000,0x71dd); +reg_write( DDR_REG_BASE +0x50397*4+0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x50398*4+0x02000000,0xf088); +reg_write( DDR_REG_BASE +0x50399*4+0x02000000,0xf211); +reg_write( DDR_REG_BASE +0x5039a*4+0x02000000,0x2204); +reg_write( DDR_REG_BASE +0x5039b*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5039c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5039d*4+0x02000000,0xfffe); +reg_write( DDR_REG_BASE +0x5039e*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5039f*4+0x02000000,0x7e30); +reg_write( DDR_REG_BASE +0x503a0*4+0x02000000,0x661e); +reg_write( DDR_REG_BASE +0x503a1*4+0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x503a2*4+0x02000000,0xe0c0); +reg_write( DDR_REG_BASE +0x503a3*4+0x02000000,0xf74a); +reg_write( DDR_REG_BASE +0x503a4*4+0x02000000,0x81b); +reg_write( DDR_REG_BASE +0x503a5*4+0x02000000,0x835); +reg_write( DDR_REG_BASE +0x503a6*4+0x02000000,0xdd40); +reg_write( DDR_REG_BASE +0x503a7*4+0x02000000,0xde20); +reg_write( DDR_REG_BASE +0x503a8*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x503a9*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x503aa*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x503ab*4+0x02000000,0xf033); +reg_write( DDR_REG_BASE +0x503ac*4+0x02000000,0xe0df); +reg_write( DDR_REG_BASE +0x503ad*4+0x02000000,0x45c9); +reg_write( DDR_REG_BASE +0x503ae*4+0x02000000,0xf7c3); +reg_write( DDR_REG_BASE +0x503af*4+0x02000000,0xdd5f); +reg_write( DDR_REG_BASE +0x503b0*4+0x02000000,0xde5f); +reg_write( DDR_REG_BASE +0x503b1*4+0x02000000,0x78af); +reg_write( DDR_REG_BASE +0x503b2*4+0x02000000,0x792f); +reg_write( DDR_REG_BASE +0x503b3*4+0x02000000,0xb16); +reg_write( DDR_REG_BASE +0x503b4*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x503b5*4+0x02000000,0x7a4f); +reg_write( DDR_REG_BASE +0x503b6*4+0x02000000,0x4308); +reg_write( DDR_REG_BASE +0x503b7*4+0x02000000,0xb0e); +reg_write( DDR_REG_BASE +0x503b8*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x503b9*4+0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x503ba*4+0x02000000,0x2580); +reg_write( DDR_REG_BASE +0x503bb*4+0x02000000,0x103f); +reg_write( DDR_REG_BASE +0x503bc*4+0x02000000,0x79bb); +reg_write( DDR_REG_BASE +0x503bd*4+0x02000000,0x2184); +reg_write( DDR_REG_BASE +0x503be*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x503bf*4+0x02000000,0xbdc4); +reg_write( DDR_REG_BASE +0x503c0*4+0x02000000,0x7d25); +reg_write( DDR_REG_BASE +0x503c1*4+0x02000000,0xc190); +reg_write( DDR_REG_BASE +0x503c2*4+0x02000000,0x79f4); +reg_write( DDR_REG_BASE +0x503c3*4+0x02000000,0xb1a0); +reg_write( DDR_REG_BASE +0x503c4*4+0x02000000,0x2642); +reg_write( DDR_REG_BASE +0x503c5*4+0x02000000,0x1801); +reg_write( DDR_REG_BASE +0x503c6*4+0x02000000,0x7a3b); +reg_write( DDR_REG_BASE +0x503c7*4+0x02000000,0x2284); +reg_write( DDR_REG_BASE +0x503c8*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x503c9*4+0x02000000,0xb9c4); +reg_write( DDR_REG_BASE +0x503ca*4+0x02000000,0x7a25); +reg_write( DDR_REG_BASE +0x503cb*4+0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x503cc*4+0x02000000,0xc396); +reg_write( DDR_REG_BASE +0x503cd*4+0x02000000,0x7bf4); +reg_write( DDR_REG_BASE +0x503ce*4+0x02000000,0x7930); +reg_write( DDR_REG_BASE +0x503cf*4+0x02000000,0x230c); +reg_write( DDR_REG_BASE +0x503d0*4+0x02000000,0x9040); +reg_write( DDR_REG_BASE +0x503d1*4+0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x503d2*4+0x02000000,0xb340); +reg_write( DDR_REG_BASE +0x503d3*4+0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x503d4*4+0x02000000,0x2c5); +reg_write( DDR_REG_BASE +0x503d5*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x503d6*4+0x02000000,0xc103); +reg_write( DDR_REG_BASE +0x503d7*4+0x02000000,0x7930); +reg_write( DDR_REG_BASE +0x503d8*4+0x02000000,0x7030); +reg_write( DDR_REG_BASE +0x503d9*4+0x02000000,0xc103); +reg_write( DDR_REG_BASE +0x503da*4+0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x503db*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x503dc*4+0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x503dd*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x503de*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x503df*4+0x02000000,0x7710); +reg_write( DDR_REG_BASE +0x503e0*4+0x02000000,0x6d4); +reg_write( DDR_REG_BASE +0x503e1*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x503e2*4+0x02000000,0xc09c); +reg_write( DDR_REG_BASE +0x503e3*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x503e4*4+0x02000000,0x7910); +reg_write( DDR_REG_BASE +0x503e5*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x503e6*4+0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x503e7*4+0x02000000,0x843); +reg_write( DDR_REG_BASE +0x503e8*4+0x02000000,0x65); +reg_write( DDR_REG_BASE +0x503e9*4+0x02000000,0xc289); +reg_write( DDR_REG_BASE +0x503ea*4+0x02000000,0x2216); +reg_write( DDR_REG_BASE +0x503eb*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x503ec*4+0x02000000,0x8a06); +reg_write( DDR_REG_BASE +0x503ed*4+0x02000000,0xdb40); +reg_write( DDR_REG_BASE +0x503ee*4+0x02000000,0x2454); +reg_write( DDR_REG_BASE +0x503ef*4+0x02000000,0x3b0b); +reg_write( DDR_REG_BASE +0x503f0*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x503f1*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x503f2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x503f3*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x503f4*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x503f5*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x503f6*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x503f7*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x503f8*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x503f9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x503fa*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x503fb*4+0x02000000,0xb060); +reg_write( DDR_REG_BASE +0x503fc*4+0x02000000,0x8a07); +reg_write( DDR_REG_BASE +0x503fd*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x503fe*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x503ff*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50400*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x50401*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x50402*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x50403*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x50404*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50405*4+0x02000000,0xb060); +reg_write( DDR_REG_BASE +0x50406*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x50407*4+0x02000000,0x2454); +reg_write( DDR_REG_BASE +0x50408*4+0x02000000,0x380b); +reg_write( DDR_REG_BASE +0x50409*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5040a*4+0x02000000,0xf015); +reg_write( DDR_REG_BASE +0x5040b*4+0x02000000,0xc09c); +reg_write( DDR_REG_BASE +0x5040c*4+0x02000000,0x6028); +reg_write( DDR_REG_BASE +0x5040d*4+0x02000000,0xe25); +reg_write( DDR_REG_BASE +0x5040e*4+0x02000000,0x3021); +reg_write( DDR_REG_BASE +0x5040f*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x50410*4+0x02000000,0x3d40); +reg_write( DDR_REG_BASE +0x50411*4+0x02000000,0x6028); +reg_write( DDR_REG_BASE +0x50412*4+0x02000000,0x23f4); +reg_write( DDR_REG_BASE +0x50413*4+0x02000000,0x1042); +reg_write( DDR_REG_BASE +0x50414*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50415*4+0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x50416*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50417*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x50418*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x50419*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x5041a*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5041b*4+0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x5041c*4+0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x5041d*4+0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x5041e*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x5041f*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50420*4+0x02000000,0x9d7); +reg_write( DDR_REG_BASE +0x50421*4+0x02000000,0x8004); +reg_write( DDR_REG_BASE +0x50422*4+0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x50423*4+0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x50424*4+0x02000000,0x264c); +reg_write( DDR_REG_BASE +0x50425*4+0x02000000,0xb080); +reg_write( DDR_REG_BASE +0x50426*4+0x02000000,0x636); +reg_write( DDR_REG_BASE +0x50427*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x50428*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x50429*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5042a*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5042b*4+0x02000000,0xa9); +reg_write( DDR_REG_BASE +0x5042c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5042d*4+0x02000000,0x8fa); +reg_write( DDR_REG_BASE +0x5042e*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5042f*4+0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x50430*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50431*4+0x02000000,0x88a); +reg_write( DDR_REG_BASE +0x50432*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x50433*4+0x02000000,0x9f6); +reg_write( DDR_REG_BASE +0x50434*4+0x02000000,0x280); +reg_write( DDR_REG_BASE +0x50435*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50436*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50437*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50438*4+0x02000000,0x1b); +reg_write( DDR_REG_BASE +0x50439*4+0x02000000,0xb8e0); +reg_write( DDR_REG_BASE +0x5043a*4+0x02000000,0xf9c); +reg_write( DDR_REG_BASE +0x5043b*4+0x02000000,0xc2); +reg_write( DDR_REG_BASE +0x5043c*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x5043d*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x5043e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5043f*4+0x02000000,0x334); +reg_write( DDR_REG_BASE +0x50440*4+0x02000000,0x88e); +reg_write( DDR_REG_BASE +0x50441*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x50442*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50443*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x50444*4+0x02000000,0x320d); +reg_write( DDR_REG_BASE +0x50445*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50446*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50447*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50448*4+0x02000000,0xb8e6); +reg_write( DDR_REG_BASE +0x50449*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5044a*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5044b*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5044c*4+0x02000000,0xb8c2); +reg_write( DDR_REG_BASE +0x5044d*4+0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x5044e*4+0x02000000,0xf403); +reg_write( DDR_REG_BASE +0x5044f*4+0x02000000,0x7914); +reg_write( DDR_REG_BASE +0x50450*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x50451*4+0x02000000,0x7915); +reg_write( DDR_REG_BASE +0x50452*4+0x02000000,0x909); +reg_write( DDR_REG_BASE +0x50453*4+0x02000000,0x354); +reg_write( DDR_REG_BASE +0x50454*4+0x02000000,0x762c); +reg_write( DDR_REG_BASE +0x50455*4+0x02000000,0x7915); +reg_write( DDR_REG_BASE +0x50456*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50457*4+0x02000000,0x6901); +reg_write( DDR_REG_BASE +0x50458*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x50459*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5045a*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x5045b*4+0x02000000,0x8a20); +reg_write( DDR_REG_BASE +0x5045c*4+0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x5045d*4+0x02000000,0xc81); +reg_write( DDR_REG_BASE +0x5045e*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x5045f*4+0x02000000,0x8a21); +reg_write( DDR_REG_BASE +0x50460*4+0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x50461*4+0x02000000,0x641); +reg_write( DDR_REG_BASE +0x50462*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50463*4+0x02000000,0x8903); +reg_write( DDR_REG_BASE +0x50464*4+0x02000000,0xb8e6); +reg_write( DDR_REG_BASE +0x50465*4+0x02000000,0x8902); +reg_write( DDR_REG_BASE +0x50466*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50467*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x50468*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50469*4+0x02000000,0x1c); +reg_write( DDR_REG_BASE +0x5046a*4+0x02000000,0xb8c2); +reg_write( DDR_REG_BASE +0x5046b*4+0x02000000,0xf409); +reg_write( DDR_REG_BASE +0x5046c*4+0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x5046d*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5046e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5046f*4+0x02000000,0x640); +reg_write( DDR_REG_BASE +0x50470*4+0x02000000,0xf209); +reg_write( DDR_REG_BASE +0x50471*4+0x02000000,0xe108); +reg_write( DDR_REG_BASE +0x50472*4+0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x50473*4+0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x50474*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50475*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50476*4+0x02000000,0x630); +reg_write( DDR_REG_BASE +0x50477*4+0x02000000,0xf203); +reg_write( DDR_REG_BASE +0x50478*4+0x02000000,0xe108); +reg_write( DDR_REG_BASE +0x50479*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x5047a*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x5047b*4+0x02000000,0x8900); +reg_write( DDR_REG_BASE +0x5047c*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5047d*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5047e*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5047f*4+0x02000000,0xc1b5); +reg_write( DDR_REG_BASE +0x50480*4+0x02000000,0xc254); +reg_write( DDR_REG_BASE +0x50481*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x50482*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x50483*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50484*4+0x02000000,0xee); +reg_write( DDR_REG_BASE +0x50485*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50486*4+0x02000000,0xdb2); +reg_write( DDR_REG_BASE +0x50487*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50488*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x50489*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x5048a*4+0x02000000,0xf035); +reg_write( DDR_REG_BASE +0x5048b*4+0x02000000,0x4261); +reg_write( DDR_REG_BASE +0x5048c*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x5048d*4+0x02000000,0xc014); +reg_write( DDR_REG_BASE +0x5048e*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x5048f*4+0x02000000,0x83); +reg_write( DDR_REG_BASE +0x50490*4+0x02000000,0xc08e); +reg_write( DDR_REG_BASE +0x50491*4+0x02000000,0x7834); +reg_write( DDR_REG_BASE +0x50492*4+0x02000000,0xb060); +reg_write( DDR_REG_BASE +0x50493*4+0x02000000,0x62ba); +reg_write( DDR_REG_BASE +0x50494*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x50495*4+0x02000000,0x9f3); +reg_write( DDR_REG_BASE +0x50496*4+0x02000000,0x8294); +reg_write( DDR_REG_BASE +0x50497*4+0x02000000,0x4183); +reg_write( DDR_REG_BASE +0x50498*4+0x02000000,0x911c); +reg_write( DDR_REG_BASE +0x50499*4+0x02000000,0x1446); +reg_write( DDR_REG_BASE +0x5049a*4+0x02000000,0x3103); +reg_write( DDR_REG_BASE +0x5049b*4+0x02000000,0x915f); +reg_write( DDR_REG_BASE +0x5049c*4+0x02000000,0xc053); +reg_write( DDR_REG_BASE +0x5049d*4+0x02000000,0x1448); +reg_write( DDR_REG_BASE +0x5049e*4+0x02000000,0x3101); +reg_write( DDR_REG_BASE +0x5049f*4+0x02000000,0x144a); +reg_write( DDR_REG_BASE +0x504a0*4+0x02000000,0x3100); +reg_write( DDR_REG_BASE +0x504a1*4+0x02000000,0x143a); +reg_write( DDR_REG_BASE +0x504a2*4+0x02000000,0x311f); +reg_write( DDR_REG_BASE +0x504a3*4+0x02000000,0x143c); +reg_write( DDR_REG_BASE +0x504a4*4+0x02000000,0x311e); +reg_write( DDR_REG_BASE +0x504a5*4+0x02000000,0x1440); +reg_write( DDR_REG_BASE +0x504a6*4+0x02000000,0x310f); +reg_write( DDR_REG_BASE +0x504a7*4+0x02000000,0x1442); +reg_write( DDR_REG_BASE +0x504a8*4+0x02000000,0x310e); +reg_write( DDR_REG_BASE +0x504a9*4+0x02000000,0x1444); +reg_write( DDR_REG_BASE +0x504aa*4+0x02000000,0x310c); +reg_write( DDR_REG_BASE +0x504ab*4+0x02000000,0xc346); +reg_write( DDR_REG_BASE +0x504ac*4+0x02000000,0xc313); +reg_write( DDR_REG_BASE +0x504ad*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x504ae*4+0x02000000,0xc147); +reg_write( DDR_REG_BASE +0x504af*4+0x02000000,0xc242); +reg_write( DDR_REG_BASE +0x504b0*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x504b1*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x504b2*4+0x02000000,0xef); +reg_write( DDR_REG_BASE +0x504b3*4+0x02000000,0xb); +reg_write( DDR_REG_BASE +0x504b4*4+0x02000000,0xc445); +reg_write( DDR_REG_BASE +0x504b5*4+0x02000000,0xc644); +reg_write( DDR_REG_BASE +0x504b6*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x504b7*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x504b8*4+0x02000000,0x3780); +reg_write( DDR_REG_BASE +0x504b9*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x504ba*4+0x02000000,0x37c0); +reg_write( DDR_REG_BASE +0x504bb*4+0x02000000,0xd4a); +reg_write( DDR_REG_BASE +0x504bc*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x504bd*4+0x02000000,0x4261); +reg_write( DDR_REG_BASE +0x504be*4+0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x504bf*4+0x02000000,0x232f); +reg_write( DDR_REG_BASE +0x504c0*4+0x02000000,0x16c8); +reg_write( DDR_REG_BASE +0x504c1*4+0x02000000,0xb97); +reg_write( DDR_REG_BASE +0x504c2*4+0x02000000,0x9364); +reg_write( DDR_REG_BASE +0x504c3*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x504c4*4+0x02000000,0xc0b5); +reg_write( DDR_REG_BASE +0x504c5*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x504c6*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x504c7*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x504c8*4+0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x504c9*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x504ca*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x504cb*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x504cc*4+0x02000000,0x866); +reg_write( DDR_REG_BASE +0x504cd*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x504ce*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x504cf*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x504d0*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x504d1*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x504d2*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x504d3*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x504d4*4+0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x504d5*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x504d6*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x504d7*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x504d8*4+0x02000000,0x926); +reg_write( DDR_REG_BASE +0x504d9*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x504da*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x504db*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x504dc*4+0x02000000,0x1100); +reg_write( DDR_REG_BASE +0x504dd*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x504de*4+0x02000000,0xb98d); +reg_write( DDR_REG_BASE +0x504df*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x504e0*4+0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x504e1*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x504e2*4+0x02000000,0xf03); +reg_write( DDR_REG_BASE +0x504e3*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x504e4*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x504e5*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x504e6*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x504e7*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x504e8*4+0x02000000,0x906); +reg_write( DDR_REG_BASE +0x504e9*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x504ea*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x504eb*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x504ec*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x504ed*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x504ee*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x504ef*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x504f0*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x504f1*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x504f2*4+0x02000000,0x8f2); +reg_write( DDR_REG_BASE +0x504f3*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x504f4*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x504f5*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x504f6*4+0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x504f7*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x504f8*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x504f9*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x504fa*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x504fb*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x504fc*4+0x02000000,0x102); +reg_write( DDR_REG_BASE +0x504fd*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x504fe*4+0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x504ff*4+0x02000000,0x4308); +reg_write( DDR_REG_BASE +0x50500*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50501*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50502*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x50503*4+0x02000000,0x1e4); +reg_write( DDR_REG_BASE +0x50504*4+0x02000000,0x218c); +reg_write( DDR_REG_BASE +0x50505*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x50506*4+0x02000000,0xb6a0); +reg_write( DDR_REG_BASE +0x50507*4+0x02000000,0xb6a1); +reg_write( DDR_REG_BASE +0x50508*4+0x02000000,0xb6a2); +reg_write( DDR_REG_BASE +0x50509*4+0x02000000,0xf224); +reg_write( DDR_REG_BASE +0x5050a*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5050b*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5050c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5050d*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5050e*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x5050f*4+0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x50510*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50511*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50512*4+0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x50513*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50514*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50515*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x50516*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x50517*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50518*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50519*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x5051a*4+0x02000000,0x8881); +reg_write( DDR_REG_BASE +0x5051b*4+0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x5051c*4+0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x5051d*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x5051e*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x5051f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50520*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x50521*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x50522*4+0x02000000,0x7a65); +reg_write( DDR_REG_BASE +0x50523*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x50524*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x50525*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50526*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x50527*4+0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x50528*4+0x02000000,0xceb); +reg_write( DDR_REG_BASE +0x50529*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x5052a*4+0x02000000,0x806); +reg_write( DDR_REG_BASE +0x5052b*4+0x02000000,0x280); +reg_write( DDR_REG_BASE +0x5052c*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x5052d*4+0x02000000,0x21a); +reg_write( DDR_REG_BASE +0x5052e*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5052f*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x50530*4+0x02000000,0x2a); +reg_write( DDR_REG_BASE +0x50531*4+0x02000000,0x1efc); +reg_write( DDR_REG_BASE +0x50532*4+0x02000000,0x92c4); +reg_write( DDR_REG_BASE +0x50533*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x50534*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50535*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50536*4+0x02000000,0x446); +reg_write( DDR_REG_BASE +0x50537*4+0x02000000,0xa8a0); +reg_write( DDR_REG_BASE +0x50538*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50539*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5053a*4+0x02000000,0xfac); +reg_write( DDR_REG_BASE +0x5053b*4+0x02000000,0xb101); +reg_write( DDR_REG_BASE +0x5053c*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5053d*4+0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x5053e*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5053f*4+0x02000000,0x7210); +reg_write( DDR_REG_BASE +0x50540*4+0x02000000,0x20e0); +reg_write( DDR_REG_BASE +0x50541*4+0x02000000,0x7ca); +reg_write( DDR_REG_BASE +0x50542*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50543*4+0x02000000,0x7101); +reg_write( DDR_REG_BASE +0x50544*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x50545*4+0x02000000,0x1d6); +reg_write( DDR_REG_BASE +0x50546*4+0x02000000,0x9f3); +reg_write( DDR_REG_BASE +0x50547*4+0x02000000,0x803e); +reg_write( DDR_REG_BASE +0x50548*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x50549*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5054a*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x5054b*4+0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x5054c*4+0x02000000,0xe52); +reg_write( DDR_REG_BASE +0x5054d*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5054e*4+0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x5054f*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x50550*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x50551*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50552*4+0x02000000,0xf2); +reg_write( DDR_REG_BASE +0x50553*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50554*4+0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x50555*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50556*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x50557*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50558*4+0x02000000,0x7784); +reg_write( DDR_REG_BASE +0x50559*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x5055a*4+0x02000000,0x1e2); +reg_write( DDR_REG_BASE +0x5055b*4+0x02000000,0xdd2); +reg_write( DDR_REG_BASE +0x5055c*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x5055d*4+0x02000000,0x760c); +reg_write( DDR_REG_BASE +0x5055e*4+0x02000000,0xb17); +reg_write( DDR_REG_BASE +0x5055f*4+0x02000000,0x1030); +reg_write( DDR_REG_BASE +0x50560*4+0x02000000,0x1d10); +reg_write( DDR_REG_BASE +0x50561*4+0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x50562*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50563*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50564*4+0x02000000,0x61a8); +reg_write( DDR_REG_BASE +0x50565*4+0x02000000,0xfb6); +reg_write( DDR_REG_BASE +0x50566*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x50567*4+0x02000000,0x1d10); +reg_write( DDR_REG_BASE +0x50568*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x50569*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x5056a*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5056b*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5056c*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5056d*4+0x02000000,0xc1a6); +reg_write( DDR_REG_BASE +0x5056e*4+0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x5056f*4+0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x50570*4+0x02000000,0xc20b); +reg_write( DDR_REG_BASE +0x50571*4+0x02000000,0xc345); +reg_write( DDR_REG_BASE +0x50572*4+0x02000000,0xdb7f); +reg_write( DDR_REG_BASE +0x50573*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50574*4+0x02000000,0x7b44); +reg_write( DDR_REG_BASE +0x50575*4+0x02000000,0xd84b); +reg_write( DDR_REG_BASE +0x50576*4+0x02000000,0x2338); +reg_write( DDR_REG_BASE +0x50577*4+0x02000000,0xf); +reg_write( DDR_REG_BASE +0x50578*4+0x02000000,0x279a); +reg_write( DDR_REG_BASE +0x50579*4+0x02000000,0x1002); +reg_write( DDR_REG_BASE +0x5057a*4+0x02000000,0xbae6); +reg_write( DDR_REG_BASE +0x5057b*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x5057c*4+0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x5057d*4+0x02000000,0x234f); +reg_write( DDR_REG_BASE +0x5057e*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x5057f*4+0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x50580*4+0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x50581*4+0x02000000,0xe4cf); +reg_write( DDR_REG_BASE +0x50582*4+0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x50583*4+0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x50584*4+0x02000000,0xe3d1); +reg_write( DDR_REG_BASE +0x50585*4+0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x50586*4+0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x50587*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50588*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50589*4+0x02000000,0x7083); +reg_write( DDR_REG_BASE +0x5058a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5058b*4+0x02000000,0x446); +reg_write( DDR_REG_BASE +0x5058c*4+0x02000000,0x1400); +reg_write( DDR_REG_BASE +0x5058d*4+0x02000000,0x301f); +reg_write( DDR_REG_BASE +0x5058e*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x5058f*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x50590*4+0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x50591*4+0x02000000,0x2642); +reg_write( DDR_REG_BASE +0x50592*4+0x02000000,0x304b); +reg_write( DDR_REG_BASE +0x50593*4+0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x50594*4+0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x50595*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x50596*4+0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x50597*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x50598*4+0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x50599*4+0x02000000,0xb51); +reg_write( DDR_REG_BASE +0x5059a*4+0x02000000,0x16b5); +reg_write( DDR_REG_BASE +0x5059b*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5059c*4+0x02000000,0xdb50); +reg_write( DDR_REG_BASE +0x5059d*4+0x02000000,0xc341); +reg_write( DDR_REG_BASE +0x5059e*4+0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x5059f*4+0x02000000,0xd810); +reg_write( DDR_REG_BASE +0x505a0*4+0x02000000,0xde30); +reg_write( DDR_REG_BASE +0x505a1*4+0x02000000,0xdd60); +reg_write( DDR_REG_BASE +0x505a2*4+0x02000000,0x4378); +reg_write( DDR_REG_BASE +0x505a3*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x505a4*4+0x02000000,0x2025); +reg_write( DDR_REG_BASE +0x505a5*4+0x02000000,0x2c0); +reg_write( DDR_REG_BASE +0x505a6*4+0x02000000,0xf01a); +reg_write( DDR_REG_BASE +0x505a7*4+0x02000000,0xf01a); +reg_write( DDR_REG_BASE +0x505a8*4+0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x505a9*4+0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x505aa*4+0x02000000,0xf05c); +reg_write( DDR_REG_BASE +0x505ab*4+0x02000000,0xf019); +reg_write( DDR_REG_BASE +0x505ac*4+0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x505ad*4+0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x505ae*4+0x02000000,0xf045); +reg_write( DDR_REG_BASE +0x505af*4+0x02000000,0xf048); +reg_write( DDR_REG_BASE +0x505b0*4+0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x505b1*4+0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x505b2*4+0x02000000,0xf047); +reg_write( DDR_REG_BASE +0x505b3*4+0x02000000,0xf03b); +reg_write( DDR_REG_BASE +0x505b4*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x505b5*4+0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x505b6*4+0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x505b7*4+0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x505b8*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x505b9*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x505ba*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x505bb*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x505bc*4+0x02000000,0xf03f); +reg_write( DDR_REG_BASE +0x505bd*4+0x02000000,0xf034); +reg_write( DDR_REG_BASE +0x505be*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x505bf*4+0x02000000,0xf0a8); +reg_write( DDR_REG_BASE +0x505c0*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x505c1*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x505c2*4+0x02000000,0xdb10); +reg_write( DDR_REG_BASE +0x505c3*4+0x02000000,0x264c); +reg_write( DDR_REG_BASE +0x505c4*4+0x02000000,0xb640); +reg_write( DDR_REG_BASE +0x505c5*4+0x02000000,0x14a); +reg_write( DDR_REG_BASE +0x505c6*4+0x02000000,0x2d); +reg_write( DDR_REG_BASE +0x505c7*4+0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x505c8*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x505c9*4+0x02000000,0x748d); +reg_write( DDR_REG_BASE +0x505ca*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x505cb*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x505cc*4+0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x505cd*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x505ce*4+0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x505cf*4+0x02000000,0x2025); +reg_write( DDR_REG_BASE +0x505d0*4+0x02000000,0x780); +reg_write( DDR_REG_BASE +0x505d1*4+0x02000000,0xf036); +reg_write( DDR_REG_BASE +0x505d2*4+0x02000000,0xf02c); +reg_write( DDR_REG_BASE +0x505d3*4+0x02000000,0xf02b); +reg_write( DDR_REG_BASE +0x505d4*4+0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x505d5*4+0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x505d6*4+0x02000000,0xf093); +reg_write( DDR_REG_BASE +0x505d7*4+0x02000000,0xf099); +reg_write( DDR_REG_BASE +0x505d8*4+0x02000000,0xf093); +reg_write( DDR_REG_BASE +0x505d9*4+0x02000000,0xf015); +reg_write( DDR_REG_BASE +0x505da*4+0x02000000,0xf019); +reg_write( DDR_REG_BASE +0x505db*4+0x02000000,0xf01c); +reg_write( DDR_REG_BASE +0x505dc*4+0x02000000,0xf091); +reg_write( DDR_REG_BASE +0x505dd*4+0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x505de*4+0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x505df*4+0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x505e0*4+0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x505e1*4+0x02000000,0xf089); +reg_write( DDR_REG_BASE +0x505e2*4+0x02000000,0xf087); +reg_write( DDR_REG_BASE +0x505e3*4+0x02000000,0xf087); +reg_write( DDR_REG_BASE +0x505e4*4+0x02000000,0xf085); +reg_write( DDR_REG_BASE +0x505e5*4+0x02000000,0xf085); +reg_write( DDR_REG_BASE +0x505e6*4+0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x505e7*4+0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x505e8*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x505e9*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x505ea*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x505eb*4+0x02000000,0xdb07); +reg_write( DDR_REG_BASE +0x505ec*4+0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x505ed*4+0x02000000,0xc701); +reg_write( DDR_REG_BASE +0x505ee*4+0x02000000,0x758d); +reg_write( DDR_REG_BASE +0x505ef*4+0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x505f0*4+0x02000000,0x758d); +reg_write( DDR_REG_BASE +0x505f1*4+0x02000000,0x47a9); +reg_write( DDR_REG_BASE +0x505f2*4+0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x505f3*4+0x02000000,0x758d); +reg_write( DDR_REG_BASE +0x505f4*4+0x02000000,0x47c9); +reg_write( DDR_REG_BASE +0x505f5*4+0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x505f6*4+0x02000000,0x718d); +reg_write( DDR_REG_BASE +0x505f7*4+0x02000000,0x476b); +reg_write( DDR_REG_BASE +0x505f8*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x505f9*4+0x02000000,0x768d); +reg_write( DDR_REG_BASE +0x505fa*4+0x02000000,0xf00b); +reg_write( DDR_REG_BASE +0x505fb*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x505fc*4+0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x505fd*4+0x02000000,0x736c); +reg_write( DDR_REG_BASE +0x505fe*4+0x02000000,0xe0d); +reg_write( DDR_REG_BASE +0x505ff*4+0x02000000,0x30d1); +reg_write( DDR_REG_BASE +0x50600*4+0x02000000,0xc402); +reg_write( DDR_REG_BASE +0x50601*4+0x02000000,0x249a); +reg_write( DDR_REG_BASE +0x50602*4+0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x50603*4+0x02000000,0x7a85); +reg_write( DDR_REG_BASE +0x50604*4+0x02000000,0x4468); +reg_write( DDR_REG_BASE +0x50605*4+0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x50606*4+0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x50607*4+0x02000000,0xffd); +reg_write( DDR_REG_BASE +0x50608*4+0x02000000,0x7b24); +reg_write( DDR_REG_BASE +0x50609*4+0x02000000,0x783d); +reg_write( DDR_REG_BASE +0x5060a*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x5060b*4+0x02000000,0xc0b); +reg_write( DDR_REG_BASE +0x5060c*4+0x02000000,0xe3b0); +reg_write( DDR_REG_BASE +0x5060d*4+0x02000000,0xdb58); +reg_write( DDR_REG_BASE +0x5060e*4+0x02000000,0x23cf); +reg_write( DDR_REG_BASE +0x5060f*4+0x02000000,0x11e1); +reg_write( DDR_REG_BASE +0x50610*4+0x02000000,0x7b24); +reg_write( DDR_REG_BASE +0x50611*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x50612*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50613*4+0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x50614*4+0x02000000,0x2c3); +reg_write( DDR_REG_BASE +0x50615*4+0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x50616*4+0x02000000,0x7b05); +reg_write( DDR_REG_BASE +0x50617*4+0x02000000,0x783d); +reg_write( DDR_REG_BASE +0x50618*4+0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x50619*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5061a*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5061b*4+0x02000000,0xc405); +reg_write( DDR_REG_BASE +0x5061c*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5061d*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x5061e*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5061f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50620*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x50621*4+0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x50622*4+0x02000000,0x7c65); +reg_write( DDR_REG_BASE +0x50623*4+0x02000000,0x232f); +reg_write( DDR_REG_BASE +0x50624*4+0x02000000,0x17c0); +reg_write( DDR_REG_BASE +0x50625*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x50626*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x50627*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50628*4+0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x50629*4+0x02000000,0x10c0); +reg_write( DDR_REG_BASE +0x5062a*4+0x02000000,0xb080); +reg_write( DDR_REG_BASE +0x5062b*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x5062c*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x5062d*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5062e*4+0x02000000,0x7154); +reg_write( DDR_REG_BASE +0x5062f*4+0x02000000,0x2104); +reg_write( DDR_REG_BASE +0x50630*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x50631*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50632*4+0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x50633*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x50634*4+0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x50635*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50636*4+0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x50637*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50638*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50639*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5063a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5063b*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x5063c*4+0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x5063d*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x5063e*4+0x02000000,0x20cf); +reg_write( DDR_REG_BASE +0x5063f*4+0x02000000,0x1a1); +reg_write( DDR_REG_BASE +0x50640*4+0x02000000,0x264c); +reg_write( DDR_REG_BASE +0x50641*4+0x02000000,0xb180); +reg_write( DDR_REG_BASE +0x50642*4+0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x50643*4+0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x50644*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x50645*4+0x02000000,0xb8c3); +reg_write( DDR_REG_BASE +0x50646*4+0x02000000,0x7f05); +reg_write( DDR_REG_BASE +0x50647*4+0x02000000,0x78ef); +reg_write( DDR_REG_BASE +0x50648*4+0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x50649*4+0x02000000,0x2354); +reg_write( DDR_REG_BASE +0x5064a*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x5064b*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x5064c*4+0x02000000,0xb080); +reg_write( DDR_REG_BASE +0x5064d*4+0x02000000,0x2355); +reg_write( DDR_REG_BASE +0x5064e*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x5064f*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x50650*4+0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x50651*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x50652*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x50653*4+0x02000000,0x2355); +reg_write( DDR_REG_BASE +0x50654*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x50655*4+0x02000000,0x7b05); +reg_write( DDR_REG_BASE +0x50656*4+0x02000000,0xb320); +reg_write( DDR_REG_BASE +0x50657*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50658*4+0x02000000,0x2740); +reg_write( DDR_REG_BASE +0x50659*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x5065a*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x5065b*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x5065c*4+0x02000000,0xf405); +reg_write( DDR_REG_BASE +0x5065d*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5065e*4+0x02000000,0x7042); +reg_write( DDR_REG_BASE +0x5065f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50660*4+0x02000000,0x446); +reg_write( DDR_REG_BASE +0x50661*4+0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x50662*4+0x02000000,0xc0a6); +reg_write( DDR_REG_BASE +0x50663*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50664*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50665*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50666*4+0x02000000,0x738d); +reg_write( DDR_REG_BASE +0x50667*4+0x02000000,0xdf10); +reg_write( DDR_REG_BASE +0x50668*4+0x02000000,0xf19e); +reg_write( DDR_REG_BASE +0x50669*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x5066a*4+0x02000000,0xf19b); +reg_write( DDR_REG_BASE +0x5066b*4+0x02000000,0x718d); +reg_write( DDR_REG_BASE +0x5066c*4+0x02000000,0xf199); +reg_write( DDR_REG_BASE +0x5066d*4+0x02000000,0xdc20); +reg_write( DDR_REG_BASE +0x5066e*4+0x02000000,0xf197); +reg_write( DDR_REG_BASE +0x5066f*4+0x02000000,0x758d); +reg_write( DDR_REG_BASE +0x50670*4+0x02000000,0xf195); +reg_write( DDR_REG_BASE +0x50671*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50672*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x50673*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x50674*4+0x02000000,0xc408); +reg_write( DDR_REG_BASE +0x50675*4+0x02000000,0xc443); +reg_write( DDR_REG_BASE +0x50676*4+0x02000000,0xc407); +reg_write( DDR_REG_BASE +0x50677*4+0x02000000,0xc442); +reg_write( DDR_REG_BASE +0x50678*4+0x02000000,0xc406); +reg_write( DDR_REG_BASE +0x50679*4+0x02000000,0xc441); +reg_write( DDR_REG_BASE +0x5067a*4+0x02000000,0xc405); +reg_write( DDR_REG_BASE +0x5067b*4+0x02000000,0xde2); +reg_write( DDR_REG_BASE +0x5067c*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5067d*4+0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x5067e*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x5067f*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x50680*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50681*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50682*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50683*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50684*4+0x02000000,0x446); +reg_write( DDR_REG_BASE +0x50685*4+0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x50686*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x50687*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x50688*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x50689*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x5068a*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5068b*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x5068c*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x5068d*4+0x02000000,0x1e8); +reg_write( DDR_REG_BASE +0x5068e*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5068f*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50690*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50691*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50692*4+0x02000000,0x446); +reg_write( DDR_REG_BASE +0x50693*4+0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x50694*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x50695*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x50696*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x50697*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x50698*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50699*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x5069a*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x5069b*4+0x02000000,0x1e6); +reg_write( DDR_REG_BASE +0x5069c*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5069d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5069e*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5069f*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x506a0*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x506a1*4+0x02000000,0x9160); +reg_write( DDR_REG_BASE +0x506a2*4+0x02000000,0x9141); +reg_write( DDR_REG_BASE +0x506a3*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x506a4*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x506a5*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x506a6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x506a7*4+0x02000000,0x7965); +reg_write( DDR_REG_BASE +0x506a8*4+0x02000000,0xe807); +reg_write( DDR_REG_BASE +0x506a9*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x506aa*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x506ab*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x506ac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x506ad*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x506ae*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x506af*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x506b0*4+0x02000000,0xda0f); +reg_write( DDR_REG_BASE +0x506b1*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x506b2*4+0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x506b3*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x506b4*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x506b5*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x506b6*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x506b7*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x506b8*4+0x02000000,0x900f); +reg_write( DDR_REG_BASE +0x506b9*4+0x02000000,0xfe4c); +reg_write( DDR_REG_BASE +0x506ba*4+0x02000000,0xda10); +reg_write( DDR_REG_BASE +0x506bb*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x506bc*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x506bd*4+0x02000000,0xa01); +reg_write( DDR_REG_BASE +0x506be*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x506bf*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x506c0*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x506c1*4+0x02000000,0xb101); +reg_write( DDR_REG_BASE +0x506c2*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x506c3*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x506c4*4+0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x506c5*4+0x02000000,0x265a); +reg_write( DDR_REG_BASE +0x506c6*4+0x02000000,0x3c83); +reg_write( DDR_REG_BASE +0x506c7*4+0x02000000,0x607c); +reg_write( DDR_REG_BASE +0x506c8*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x506c9*4+0x02000000,0x1643); +reg_write( DDR_REG_BASE +0x506ca*4+0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x506cb*4+0x02000000,0x639b); +reg_write( DDR_REG_BASE +0x506cc*4+0x02000000,0x633b); +reg_write( DDR_REG_BASE +0x506cd*4+0x02000000,0x8b80); +reg_write( DDR_REG_BASE +0x506ce*4+0x02000000,0x7c44); +reg_write( DDR_REG_BASE +0x506cf*4+0x02000000,0xab80); +reg_write( DDR_REG_BASE +0x506d0*4+0x02000000,0xbeb); +reg_write( DDR_REG_BASE +0x506d1*4+0x02000000,0x9094); +reg_write( DDR_REG_BASE +0x506d2*4+0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x506d3*4+0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x506d4*4+0x02000000,0xef9); +reg_write( DDR_REG_BASE +0x506d5*4+0x02000000,0xb0b4); +reg_write( DDR_REG_BASE +0x506d6*4+0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x506d7*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x506d8*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x506d9*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x506da*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x506db*4+0x02000000,0xc4a); +reg_write( DDR_REG_BASE +0x506dc*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x506dd*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x506de*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x506df*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x506e0*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x506e1*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x506e2*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x506e3*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x506e4*4+0x02000000,0xd988); +reg_write( DDR_REG_BASE +0x506e5*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x506e6*4+0x02000000,0xd0a); +reg_write( DDR_REG_BASE +0x506e7*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x506e8*4+0x02000000,0xdb40); +reg_write( DDR_REG_BASE +0x506e9*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x506ea*4+0x02000000,0xcc2); +reg_write( DDR_REG_BASE +0x506eb*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x506ec*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x506ed*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x506ee*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x506ef*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x506f0*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x506f1*4+0x02000000,0x20c0); +reg_write( DDR_REG_BASE +0x506f2*4+0x02000000,0xfe9); +reg_write( DDR_REG_BASE +0x506f3*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x506f4*4+0x02000000,0x2884); +reg_write( DDR_REG_BASE +0x506f5*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x506f6*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x506f7*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x506f8*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x506f9*4+0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x506fa*4+0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x506fb*4+0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x506fc*4+0x02000000,0x641); +reg_write( DDR_REG_BASE +0x506fd*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x506fe*4+0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x506ff*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x50700*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x50701*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50702*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50703*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x50704*4+0x02000000,0x8803); +reg_write( DDR_REG_BASE +0x50705*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50706*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50707*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50708*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50709*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5070a*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5070b*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x5070c*4+0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x5070d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5070e*4+0x02000000,0x917); +reg_write( DDR_REG_BASE +0x5070f*4+0x02000000,0x3f0); +reg_write( DDR_REG_BASE +0x50710*4+0x02000000,0x228a); +reg_write( DDR_REG_BASE +0x50711*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x50712*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x50713*4+0x02000000,0xb9c4); +reg_write( DDR_REG_BASE +0x50714*4+0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x50715*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x50716*4+0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x50717*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x50718*4+0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x50719*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x5071a*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5071b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5071c*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x5071d*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5071e*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x5071f*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50720*4+0x02000000,0x16a); +reg_write( DDR_REG_BASE +0x50721*4+0x02000000,0x224f); +reg_write( DDR_REG_BASE +0x50722*4+0x02000000,0x240); +reg_write( DDR_REG_BASE +0x50723*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50724*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x50725*4+0x02000000,0xb140); +reg_write( DDR_REG_BASE +0x50726*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x50727*4+0x02000000,0xb140); +reg_write( DDR_REG_BASE +0x50728*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50729*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x5072a*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x5072b*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5072c*4+0x02000000,0x80d); +reg_write( DDR_REG_BASE +0x5072d*4+0x02000000,0x72); +reg_write( DDR_REG_BASE +0x5072e*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5072f*4+0x02000000,0x48ff); +reg_write( DDR_REG_BASE +0x50730*4+0x02000000,0x2984); +reg_write( DDR_REG_BASE +0x50731*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50732*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50733*4+0x02000000,0x782e); +reg_write( DDR_REG_BASE +0x50734*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x50735*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x50736*4+0x02000000,0xe9a); +reg_write( DDR_REG_BASE +0x50737*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50738*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x50739*4+0x02000000,0x795b); +reg_write( DDR_REG_BASE +0x5073a*4+0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x5073b*4+0x02000000,0x181); +reg_write( DDR_REG_BASE +0x5073c*4+0x02000000,0xb9c4); +reg_write( DDR_REG_BASE +0x5073d*4+0x02000000,0xe906); +reg_write( DDR_REG_BASE +0x5073e*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x5073f*4+0x02000000,0x901); +reg_write( DDR_REG_BASE +0x50740*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x50741*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50742*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x50743*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50744*4+0x02000000,0xb8c1); +reg_write( DDR_REG_BASE +0x50745*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50746*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x50747*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x50748*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50749*4+0x02000000,0xb6e); +reg_write( DDR_REG_BASE +0x5074a*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5074b*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x5074c*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5074d*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5074e*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5074f*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x50750*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50751*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50752*4+0x02000000,0xd990); +reg_write( DDR_REG_BASE +0x50753*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x50754*4+0x02000000,0xc2e); +reg_write( DDR_REG_BASE +0x50755*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50756*4+0x02000000,0xdb40); +reg_write( DDR_REG_BASE +0x50757*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50758*4+0x02000000,0xbe6); +reg_write( DDR_REG_BASE +0x50759*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5075a*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5075b*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x5075c*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x5075d*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5075e*4+0x02000000,0xc3e1); +reg_write( DDR_REG_BASE +0x5075f*4+0x02000000,0xc2e1); +reg_write( DDR_REG_BASE +0x50760*4+0x02000000,0xc1e1); +reg_write( DDR_REG_BASE +0x50761*4+0x02000000,0xc0e1); +reg_write( DDR_REG_BASE +0x50762*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x50763*4+0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x50764*4+0x02000000,0x4220); +reg_write( DDR_REG_BASE +0x50765*4+0x02000000,0xc184); +reg_write( DDR_REG_BASE +0x50766*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x50767*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50768*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x50769*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5076a*4+0x02000000,0x12); +reg_write( DDR_REG_BASE +0x5076b*4+0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x5076c*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x5076d*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x5076e*4+0x02000000,0xb1e); +reg_write( DDR_REG_BASE +0x5076f*4+0x02000000,0x2e0); +reg_write( DDR_REG_BASE +0x50770*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x50771*4+0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x50772*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x50773*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50774*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x50775*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50776*4+0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x50777*4+0x02000000,0x216c); +reg_write( DDR_REG_BASE +0x50778*4+0x02000000,0x102); +reg_write( DDR_REG_BASE +0x50779*4+0x02000000,0x206c); +reg_write( DDR_REG_BASE +0x5077a*4+0x02000000,0x141); +reg_write( DDR_REG_BASE +0x5077b*4+0x02000000,0x7822); +reg_write( DDR_REG_BASE +0x5077c*4+0x02000000,0x621a); +reg_write( DDR_REG_BASE +0x5077d*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x5077e*4+0x02000000,0x784e); +reg_write( DDR_REG_BASE +0x5077f*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50780*4+0x02000000,0xc0e6); +reg_write( DDR_REG_BASE +0x50781*4+0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x50782*4+0x02000000,0x483); +reg_write( DDR_REG_BASE +0x50783*4+0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x50784*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50785*4+0x02000000,0x6e2); +reg_write( DDR_REG_BASE +0x50786*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x50787*4+0x02000000,0x638d); +reg_write( DDR_REG_BASE +0x50788*4+0x02000000,0x6479); +reg_write( DDR_REG_BASE +0x50789*4+0x02000000,0x8941); +reg_write( DDR_REG_BASE +0x5078a*4+0x02000000,0x7d04); +reg_write( DDR_REG_BASE +0x5078b*4+0x02000000,0xf00b); +reg_write( DDR_REG_BASE +0x5078c*4+0x02000000,0x6199); +reg_write( DDR_REG_BASE +0x5078d*4+0x02000000,0x89e2); +reg_write( DDR_REG_BASE +0x5078e*4+0x02000000,0x7f0b); +reg_write( DDR_REG_BASE +0x5078f*4+0x02000000,0xf206); +reg_write( DDR_REG_BASE +0x50790*4+0x02000000,0x89e3); +reg_write( DDR_REG_BASE +0x50791*4+0x02000000,0x79af); +reg_write( DDR_REG_BASE +0x50792*4+0x02000000,0x210f); +reg_write( DDR_REG_BASE +0x50793*4+0x02000000,0x3cd); +reg_write( DDR_REG_BASE +0x50794*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x50795*4+0x02000000,0xef1); +reg_write( DDR_REG_BASE +0x50796*4+0x02000000,0x90a4); +reg_write( DDR_REG_BASE +0x50797*4+0x02000000,0x2314); +reg_write( DDR_REG_BASE +0x50798*4+0x02000000,0x381); +reg_write( DDR_REG_BASE +0x50799*4+0x02000000,0x78af); +reg_write( DDR_REG_BASE +0x5079a*4+0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x5079b*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5079c*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5079d*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5079e*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5079f*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x507a0*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x507a1*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x507a2*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x507a3*4+0x02000000,0xb0e); +reg_write( DDR_REG_BASE +0x507a4*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x507a5*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x507a6*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x507a7*4+0x02000000,0x43a9); +reg_write( DDR_REG_BASE +0x507a8*4+0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x507a9*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x507aa*4+0x02000000,0x641); +reg_write( DDR_REG_BASE +0x507ab*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x507ac*4+0x02000000,0x1c80); +reg_write( DDR_REG_BASE +0x507ad*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x507ae*4+0x02000000,0xdda); +reg_write( DDR_REG_BASE +0x507af*4+0x02000000,0x260); +reg_write( DDR_REG_BASE +0x507b0*4+0x02000000,0x60f8); +reg_write( DDR_REG_BASE +0x507b1*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x507b2*4+0x02000000,0xbef); +reg_write( DDR_REG_BASE +0x507b3*4+0x02000000,0x8094); +reg_write( DDR_REG_BASE +0x507b4*4+0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x507b5*4+0x02000000,0xbfd); +reg_write( DDR_REG_BASE +0x507b6*4+0x02000000,0x90b4); +reg_write( DDR_REG_BASE +0x507b7*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x507b8*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x507b9*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x507ba*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x507bb*4+0x02000000,0xa8ae); +reg_write( DDR_REG_BASE +0x507bc*4+0x02000000,0xa8a1); +reg_write( DDR_REG_BASE +0x507bd*4+0x02000000,0xa8a0); +reg_write( DDR_REG_BASE +0x507be*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x507bf*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x507c0*4+0x02000000,0x7d8); +reg_write( DDR_REG_BASE +0x507c1*4+0x02000000,0x972); +reg_write( DDR_REG_BASE +0x507c2*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x507c3*4+0x02000000,0xa0e0); +reg_write( DDR_REG_BASE +0x507c4*4+0x02000000,0x976); +reg_write( DDR_REG_BASE +0x507c5*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x507c6*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x507c7*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x507c8*4+0x02000000,0xec2); +reg_write( DDR_REG_BASE +0x507c9*4+0x02000000,0x260); +reg_write( DDR_REG_BASE +0x507ca*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x507cb*4+0x02000000,0x236f); +reg_write( DDR_REG_BASE +0x507cc*4+0x02000000,0x30c3); +reg_write( DDR_REG_BASE +0x507cd*4+0x02000000,0x1318); +reg_write( DDR_REG_BASE +0x507ce*4+0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x507cf*4+0x02000000,0xe809); +reg_write( DDR_REG_BASE +0x507d0*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x507d1*4+0x02000000,0xad); +reg_write( DDR_REG_BASE +0x507d2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x507d3*4+0x02000000,0xf1a); +reg_write( DDR_REG_BASE +0x507d4*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x507d5*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x507d6*4+0x02000000,0xf01f); +reg_write( DDR_REG_BASE +0x507d7*4+0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x507d8*4+0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x507d9*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x507da*4+0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x507db*4+0x02000000,0x8480); +reg_write( DDR_REG_BASE +0x507dc*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x507dd*4+0x02000000,0x5f5); +reg_write( DDR_REG_BASE +0x507de*4+0x02000000,0xe100); +reg_write( DDR_REG_BASE +0x507df*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x507e0*4+0x02000000,0x808d); +reg_write( DDR_REG_BASE +0x507e1*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x507e2*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x507e3*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x507e4*4+0x02000000,0x916); +reg_write( DDR_REG_BASE +0x507e5*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x507e6*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x507e7*4+0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x507e8*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x507e9*4+0x02000000,0x3b9a); +reg_write( DDR_REG_BASE +0x507ea*4+0x02000000,0xca00); +reg_write( DDR_REG_BASE +0x507eb*4+0x02000000,0x26ca); +reg_write( DDR_REG_BASE +0x507ec*4+0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x507ed*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x507ee*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x507ef*4+0x02000000,0x70c5); +reg_write( DDR_REG_BASE +0x507f0*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x507f1*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x507f2*4+0x02000000,0x8fa); +reg_write( DDR_REG_BASE +0x507f3*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x507f4*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x507f5*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x507f6*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x507f7*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x507f8*4+0x02000000,0xd); +reg_write( DDR_REG_BASE +0x507f9*4+0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x507fa*4+0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x507fb*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x507fc*4+0x02000000,0x7045); +reg_write( DDR_REG_BASE +0x507fd*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x507fe*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x507ff*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50800*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50801*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x50802*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x50803*4+0x02000000,0x8b7); +reg_write( DDR_REG_BASE +0x50804*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x50805*4+0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x50806*4+0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x50807*4+0x02000000,0x8af); +reg_write( DDR_REG_BASE +0x50808*4+0x02000000,0xdf); +reg_write( DDR_REG_BASE +0x50809*4+0x02000000,0xdde); +reg_write( DDR_REG_BASE +0x5080a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5080b*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5080c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5080d*4+0x02000000,0xa00); +reg_write( DDR_REG_BASE +0x5080e*4+0x02000000,0x9e2); +reg_write( DDR_REG_BASE +0x5080f*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50810*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x50811*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50812*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50813*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50814*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x50815*4+0x02000000,0x736c); +reg_write( DDR_REG_BASE +0x50816*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x50817*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50818*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x50819*4+0x02000000,0xaa6); +reg_write( DDR_REG_BASE +0x5081a*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5081b*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5081c*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x5081d*4+0x02000000,0x825); +reg_write( DDR_REG_BASE +0x5081e*4+0x02000000,0xb4); +reg_write( DDR_REG_BASE +0x5081f*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50820*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x50821*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50822*4+0x02000000,0xb862); +reg_write( DDR_REG_BASE +0x50823*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x50824*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x50825*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50826*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x50827*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x50828*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50829*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5082a*4+0x02000000,0xa82); +reg_write( DDR_REG_BASE +0x5082b*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5082c*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5082d*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x5082e*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5082f*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50830*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50831*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x50832*4+0x02000000,0xdb0c); +reg_write( DDR_REG_BASE +0x50833*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50834*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x50835*4+0x02000000,0xa6e); +reg_write( DDR_REG_BASE +0x50836*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50837*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x50838*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x50839*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x5083a*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5083b*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5083c*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5083d*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5083e*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5083f*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x50840*4+0x02000000,0xa56); +reg_write( DDR_REG_BASE +0x50841*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50842*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x50843*4+0x02000000,0xc9e); +reg_write( DDR_REG_BASE +0x50844*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50845*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50846*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x50847*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50848*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x50849*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5084a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5084b*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5084c*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5084d*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5084e*4+0x02000000,0xa3a); +reg_write( DDR_REG_BASE +0x5084f*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50850*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x50851*4+0x02000000,0xc66); +reg_write( DDR_REG_BASE +0x50852*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50853*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50854*4+0x02000000,0x922); +reg_write( DDR_REG_BASE +0x50855*4+0x02000000,0x280); +reg_write( DDR_REG_BASE +0x50856*4+0x02000000,0xd896); +reg_write( DDR_REG_BASE +0x50857*4+0x02000000,0x9ea); +reg_write( DDR_REG_BASE +0x50858*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50859*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5085a*4+0x02000000,0xf3e); +reg_write( DDR_REG_BASE +0x5085b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5085c*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x5085d*4+0x02000000,0xcfa); +reg_write( DDR_REG_BASE +0x5085e*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x5085f*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50860*4+0x02000000,0xf); +reg_write( DDR_REG_BASE +0x50861*4+0x02000000,0x4240); +reg_write( DDR_REG_BASE +0x50862*4+0x02000000,0x81a); +reg_write( DDR_REG_BASE +0x50863*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x50864*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50865*4+0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x50866*4+0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x50867*4+0x02000000,0x83f); +reg_write( DDR_REG_BASE +0x50868*4+0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x50869*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x5086a*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5086b*4+0x02000000,0x14); +reg_write( DDR_REG_BASE +0x5086c*4+0x02000000,0x9320); +reg_write( DDR_REG_BASE +0x5086d*4+0x02000000,0xca01); +reg_write( DDR_REG_BASE +0x5086e*4+0x02000000,0x80d); +reg_write( DDR_REG_BASE +0x5086f*4+0x02000000,0x1b0); +reg_write( DDR_REG_BASE +0x50870*4+0x02000000,0x214f); +reg_write( DDR_REG_BASE +0x50871*4+0x02000000,0x82); +reg_write( DDR_REG_BASE +0x50872*4+0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x50873*4+0x02000000,0xd1); +reg_write( DDR_REG_BASE +0x50874*4+0x02000000,0x2185); +reg_write( DDR_REG_BASE +0x50875*4+0x02000000,0x108); +reg_write( DDR_REG_BASE +0x50876*4+0x02000000,0x4220); +reg_write( DDR_REG_BASE +0x50877*4+0x02000000,0xb340); +reg_write( DDR_REG_BASE +0x50878*4+0x02000000,0xd823); +reg_write( DDR_REG_BASE +0x50879*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x5087a*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x5087b*4+0x02000000,0xe034); +reg_write( DDR_REG_BASE +0x5087c*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x5087d*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5087e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5087f*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x50880*4+0x02000000,0xe034); +reg_write( DDR_REG_BASE +0x50881*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x50882*4+0x02000000,0xb8b1); +reg_write( DDR_REG_BASE +0x50883*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x50884*4+0x02000000,0xb221); +reg_write( DDR_REG_BASE +0x50885*4+0x02000000,0xddff); +reg_write( DDR_REG_BASE +0x50886*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x50887*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50888*4+0x02000000,0x228a); +reg_write( DDR_REG_BASE +0x50889*4+0x02000000,0xdff); +reg_write( DDR_REG_BASE +0x5088a*4+0x02000000,0x776c); +reg_write( DDR_REG_BASE +0x5088b*4+0x02000000,0xb06); +reg_write( DDR_REG_BASE +0x5088c*4+0x02000000,0x320); +reg_write( DDR_REG_BASE +0x5088d*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5088e*4+0x02000000,0x774c); +reg_write( DDR_REG_BASE +0x5088f*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x50890*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x50891*4+0x02000000,0x4340); +reg_write( DDR_REG_BASE +0x50892*4+0x02000000,0xaf6); +reg_write( DDR_REG_BASE +0x50893*4+0x02000000,0x320); +reg_write( DDR_REG_BASE +0x50894*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x50895*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x50896*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50897*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50898*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50899*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5089a*4+0x02000000,0xca04); +reg_write( DDR_REG_BASE +0x5089b*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5089c*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x5089d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5089e*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x5089f*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x508a0*4+0x02000000,0x8b20); +reg_write( DDR_REG_BASE +0x508a1*4+0x02000000,0xa0d); +reg_write( DDR_REG_BASE +0x508a2*4+0x02000000,0x44); +reg_write( DDR_REG_BASE +0x508a3*4+0x02000000,0x8b21); +reg_write( DDR_REG_BASE +0x508a4*4+0x02000000,0x919); +reg_write( DDR_REG_BASE +0x508a5*4+0x02000000,0x85); +reg_write( DDR_REG_BASE +0x508a6*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x508a7*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x508a8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x508a9*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x508aa*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x508ab*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x508ac*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x508ad*4+0x02000000,0x1f64); +reg_write( DDR_REG_BASE +0x508ae*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x508af*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x508b0*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x508b1*4+0x02000000,0xae1); +reg_write( DDR_REG_BASE +0x508b2*4+0x02000000,0x8004); +reg_write( DDR_REG_BASE +0x508b3*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x508b4*4+0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x508b5*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x508b6*4+0x02000000,0xbd9a); +reg_write( DDR_REG_BASE +0x508b7*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x508b8*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x508b9*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x508ba*4+0x02000000,0xd4a); +reg_write( DDR_REG_BASE +0x508bb*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x508bc*4+0x02000000,0x1a09); +reg_write( DDR_REG_BASE +0x508bd*4+0x02000000,0x3003); +reg_write( DDR_REG_BASE +0x508be*4+0x02000000,0xca6); +reg_write( DDR_REG_BASE +0x508bf*4+0x02000000,0x240); +reg_write( DDR_REG_BASE +0x508c0*4+0x02000000,0x254f); +reg_write( DDR_REG_BASE +0x508c1*4+0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x508c2*4+0x02000000,0xd3a); +reg_write( DDR_REG_BASE +0x508c3*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x508c4*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x508c5*4+0x02000000,0xfd2); +reg_write( DDR_REG_BASE +0x508c6*4+0x02000000,0x2a0); +reg_write( DDR_REG_BASE +0x508c7*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x508c8*4+0x02000000,0x26ab); +reg_write( DDR_REG_BASE +0x508c9*4+0x02000000,0x10c4); +reg_write( DDR_REG_BASE +0x508ca*4+0x02000000,0x7fff); +reg_write( DDR_REG_BASE +0x508cb*4+0x02000000,0xf000); +reg_write( DDR_REG_BASE +0x508cc*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x508cd*4+0x02000000,0xc1a5); +reg_write( DDR_REG_BASE +0x508ce*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x508cf*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x508d0*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x508d1*4+0x02000000,0xa3a); +reg_write( DDR_REG_BASE +0x508d2*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x508d3*4+0x02000000,0xda14); +reg_write( DDR_REG_BASE +0x508d4*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x508d5*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x508d6*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x508d7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x508d8*4+0x02000000,0xc180); +reg_write( DDR_REG_BASE +0x508d9*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x508da*4+0x02000000,0xe3a); +reg_write( DDR_REG_BASE +0x508db*4+0x02000000,0x220); +reg_write( DDR_REG_BASE +0x508dc*4+0x02000000,0xb885); +reg_write( DDR_REG_BASE +0x508dd*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x508de*4+0x02000000,0xf6); +reg_write( DDR_REG_BASE +0x508df*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x508e0*4+0x02000000,0xcfe); +reg_write( DDR_REG_BASE +0x508e1*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x508e2*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x508e3*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x508e4*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x508e5*4+0x02000000,0xf32); +reg_write( DDR_REG_BASE +0x508e6*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x508e7*4+0x02000000,0xc280); +reg_write( DDR_REG_BASE +0x508e8*4+0x02000000,0xc0a5); +reg_write( DDR_REG_BASE +0x508e9*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x508ea*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x508eb*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x508ec*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x508ed*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x508ee*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x508ef*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x508f0*4+0x02000000,0x3d02); +reg_write( DDR_REG_BASE +0x508f1*4+0x02000000,0x4748); +reg_write( DDR_REG_BASE +0x508f2*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x508f3*4+0x02000000,0x4308); +reg_write( DDR_REG_BASE +0x508f4*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x508f5*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x508f6*4+0x02000000,0x9ee); +reg_write( DDR_REG_BASE +0x508f7*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x508f8*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x508f9*4+0x02000000,0xb25); +reg_write( DDR_REG_BASE +0x508fa*4+0x02000000,0x10b1); +reg_write( DDR_REG_BASE +0x508fb*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x508fc*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x508fd*4+0x02000000,0xf2); +reg_write( DDR_REG_BASE +0x508fe*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x508ff*4+0x02000000,0xcc2); +reg_write( DDR_REG_BASE +0x50900*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50901*4+0x02000000,0x4260); +reg_write( DDR_REG_BASE +0x50902*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x50903*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50904*4+0x02000000,0xf3a); +reg_write( DDR_REG_BASE +0x50905*4+0x02000000,0x220); +reg_write( DDR_REG_BASE +0x50906*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x50907*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50908*4+0x02000000,0xd909); +reg_write( DDR_REG_BASE +0x50909*4+0x02000000,0xf036); +reg_write( DDR_REG_BASE +0x5090a*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x5090b*4+0x02000000,0x3f9b); +reg_write( DDR_REG_BASE +0x5090c*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5090d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5090e*4+0x02000000,0xb1b); +reg_write( DDR_REG_BASE +0x5090f*4+0x02000000,0x1030); +reg_write( DDR_REG_BASE +0x50910*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x50911*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50912*4+0x02000000,0xf4); +reg_write( DDR_REG_BASE +0x50913*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50914*4+0x02000000,0xc96); +reg_write( DDR_REG_BASE +0x50915*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50916*4+0x02000000,0x4260); +reg_write( DDR_REG_BASE +0x50917*4+0x02000000,0xdd09); +reg_write( DDR_REG_BASE +0x50918*4+0x02000000,0xdec0); +reg_write( DDR_REG_BASE +0x50919*4+0x02000000,0xd8d0); +reg_write( DDR_REG_BASE +0x5091a*4+0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x5091b*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5091c*4+0x02000000,0xf3); +reg_write( DDR_REG_BASE +0x5091d*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5091e*4+0x02000000,0xc82); +reg_write( DDR_REG_BASE +0x5091f*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50920*4+0x02000000,0x4260); +reg_write( DDR_REG_BASE +0x50921*4+0x02000000,0x72ad); +reg_write( DDR_REG_BASE +0x50922*4+0x02000000,0xde8c); +reg_write( DDR_REG_BASE +0x50923*4+0x02000000,0xd880); +reg_write( DDR_REG_BASE +0x50924*4+0x02000000,0x60f8); +reg_write( DDR_REG_BASE +0x50925*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x50926*4+0x02000000,0x6c0); +reg_write( DDR_REG_BASE +0x50927*4+0x02000000,0xc180); +reg_write( DDR_REG_BASE +0x50928*4+0x02000000,0xd9e); +reg_write( DDR_REG_BASE +0x50929*4+0x02000000,0x220); +reg_write( DDR_REG_BASE +0x5092a*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x5092b*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5092c*4+0x02000000,0x722c); +reg_write( DDR_REG_BASE +0x5092d*4+0x02000000,0xea2); +reg_write( DDR_REG_BASE +0x5092e*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x5092f*4+0x02000000,0xc280); +reg_write( DDR_REG_BASE +0x50930*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x50931*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50932*4+0x02000000,0x976); +reg_write( DDR_REG_BASE +0x50933*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x50934*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x50935*4+0x02000000,0x66fe); +reg_write( DDR_REG_BASE +0x50936*4+0x02000000,0x2605); +reg_write( DDR_REG_BASE +0x50937*4+0x02000000,0x16c0); +reg_write( DDR_REG_BASE +0x50938*4+0x02000000,0xc180); +reg_write( DDR_REG_BASE +0x50939*4+0x02000000,0xd7e); +reg_write( DDR_REG_BASE +0x5093a*4+0x02000000,0x220); +reg_write( DDR_REG_BASE +0x5093b*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x5093c*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5093d*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x5093e*4+0x02000000,0xe7e); +reg_write( DDR_REG_BASE +0x5093f*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50940*4+0x02000000,0xc280); +reg_write( DDR_REG_BASE +0x50941*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x50942*4+0x02000000,0x3d02); +reg_write( DDR_REG_BASE +0x50943*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50944*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50945*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50946*4+0x02000000,0xc3e2); +reg_write( DDR_REG_BASE +0x50947*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x50948*4+0x02000000,0x3d02); +reg_write( DDR_REG_BASE +0x50949*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x5094a*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x5094b*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x5094c*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5094d*4+0x02000000,0x942); +reg_write( DDR_REG_BASE +0x5094e*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x5094f*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x50950*4+0x02000000,0x2354); +reg_write( DDR_REG_BASE +0x50951*4+0x02000000,0xd00); +reg_write( DDR_REG_BASE +0x50952*4+0x02000000,0xc180); +reg_write( DDR_REG_BASE +0x50953*4+0x02000000,0xd4a); +reg_write( DDR_REG_BASE +0x50954*4+0x02000000,0x220); +reg_write( DDR_REG_BASE +0x50955*4+0x02000000,0xda09); +reg_write( DDR_REG_BASE +0x50956*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x50957*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50958*4+0x02000000,0xf5); +reg_write( DDR_REG_BASE +0x50959*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5095a*4+0x02000000,0xc0a); +reg_write( DDR_REG_BASE +0x5095b*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5095c*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x5095d*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5095e*4+0x02000000,0xd909); +reg_write( DDR_REG_BASE +0x5095f*4+0x02000000,0xe3e); +reg_write( DDR_REG_BASE +0x50960*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50961*4+0x02000000,0xc280); +reg_write( DDR_REG_BASE +0x50962*4+0x02000000,0xc7c2); +reg_write( DDR_REG_BASE +0x50963*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50964*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x50965*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x50966*4+0x02000000,0x3d02); +reg_write( DDR_REG_BASE +0x50967*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x50968*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50969*4+0x02000000,0x90a); +reg_write( DDR_REG_BASE +0x5096a*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x5096b*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x5096c*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5096d*4+0x02000000,0xf7); +reg_write( DDR_REG_BASE +0x5096e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5096f*4+0x02000000,0xbe2); +reg_write( DDR_REG_BASE +0x50970*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50971*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x50972*4+0x02000000,0xd840); +reg_write( DDR_REG_BASE +0x50973*4+0x02000000,0xc180); +reg_write( DDR_REG_BASE +0x50974*4+0x02000000,0xd06); +reg_write( DDR_REG_BASE +0x50975*4+0x02000000,0x220); +reg_write( DDR_REG_BASE +0x50976*4+0x02000000,0xda09); +reg_write( DDR_REG_BASE +0x50977*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50978*4+0x02000000,0xd909); +reg_write( DDR_REG_BASE +0x50979*4+0x02000000,0xe0a); +reg_write( DDR_REG_BASE +0x5097a*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x5097b*4+0x02000000,0xc280); +reg_write( DDR_REG_BASE +0x5097c*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x5097d*4+0x02000000,0x3d02); +reg_write( DDR_REG_BASE +0x5097e*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x5097f*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50980*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50981*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x50982*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50983*4+0x02000000,0x12); +reg_write( DDR_REG_BASE +0x50984*4+0x02000000,0x7534); +reg_write( DDR_REG_BASE +0x50985*4+0x02000000,0x20e0); +reg_write( DDR_REG_BASE +0x50986*4+0x02000000,0x7c5); +reg_write( DDR_REG_BASE +0x50987*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50988*4+0x02000000,0x1a09); +reg_write( DDR_REG_BASE +0x50989*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x5098a*4+0x02000000,0xc0e6); +reg_write( DDR_REG_BASE +0x5098b*4+0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x5098c*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5098d*4+0x02000000,0xe4); +reg_write( DDR_REG_BASE +0x5098e*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x5098f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50990*4+0x02000000,0x7cb); +reg_write( DDR_REG_BASE +0x50991*4+0x02000000,0x835); +reg_write( DDR_REG_BASE +0x50992*4+0x02000000,0xb0); +reg_write( DDR_REG_BASE +0x50993*4+0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x50994*4+0x02000000,0x7114); +reg_write( DDR_REG_BASE +0x50995*4+0x02000000,0xd825); +reg_write( DDR_REG_BASE +0x50996*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50997*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50998*4+0x02000000,0x30); +reg_write( DDR_REG_BASE +0x50999*4+0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x5099a*4+0x02000000,0xf42a); +reg_write( DDR_REG_BASE +0x5099b*4+0x02000000,0x8a25); +reg_write( DDR_REG_BASE +0x5099c*4+0x02000000,0xaa23); +reg_write( DDR_REG_BASE +0x5099d*4+0x02000000,0x8aa4); +reg_write( DDR_REG_BASE +0x5099e*4+0x02000000,0x7b34); +reg_write( DDR_REG_BASE +0x5099f*4+0x02000000,0xaaa2); +reg_write( DDR_REG_BASE +0x509a0*4+0x02000000,0x96c0); +reg_write( DDR_REG_BASE +0x509a1*4+0x02000000,0x88e0); +reg_write( DDR_REG_BASE +0x509a2*4+0x02000000,0x78bb); +reg_write( DDR_REG_BASE +0x509a3*4+0x02000000,0xb4e0); +reg_write( DDR_REG_BASE +0x509a4*4+0x02000000,0xaa00); +reg_write( DDR_REG_BASE +0x509a5*4+0x02000000,0xe5f); +reg_write( DDR_REG_BASE +0x509a6*4+0x02000000,0x1171); +reg_write( DDR_REG_BASE +0x509a7*4+0x02000000,0xaa61); +reg_write( DDR_REG_BASE +0x509a8*4+0x02000000,0xb4e1); +reg_write( DDR_REG_BASE +0x509a9*4+0x02000000,0xf02d); +reg_write( DDR_REG_BASE +0x509aa*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x509ab*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x509ac*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x509ad*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x509ae*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x509af*4+0x02000000,0x58); +reg_write( DDR_REG_BASE +0x509b0*4+0x02000000,0xb421); +reg_write( DDR_REG_BASE +0x509b1*4+0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x509b2*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x509b3*4+0x02000000,0xf6); +reg_write( DDR_REG_BASE +0x509b4*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x509b5*4+0x02000000,0xb404); +reg_write( DDR_REG_BASE +0x509b6*4+0x02000000,0x1c06); +reg_write( DDR_REG_BASE +0x509b7*4+0x02000000,0x13c5); +reg_write( DDR_REG_BASE +0x509b8*4+0x02000000,0x8a27); +reg_write( DDR_REG_BASE +0x509b9*4+0x02000000,0xaa23); +reg_write( DDR_REG_BASE +0x509ba*4+0x02000000,0x8a06); +reg_write( DDR_REG_BASE +0x509bb*4+0x02000000,0x7b34); +reg_write( DDR_REG_BASE +0x509bc*4+0x02000000,0xaa02); +reg_write( DDR_REG_BASE +0x509bd*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x509be*4+0x02000000,0xaa00); +reg_write( DDR_REG_BASE +0x509bf*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x509c0*4+0x02000000,0xaa61); +reg_write( DDR_REG_BASE +0x509c1*4+0x02000000,0x1cfe); +reg_write( DDR_REG_BASE +0x509c2*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x509c3*4+0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x509c4*4+0x02000000,0x88a0); +reg_write( DDR_REG_BASE +0x509c5*4+0x02000000,0xb4a0); +reg_write( DDR_REG_BASE +0x509c6*4+0x02000000,0x8a27); +reg_write( DDR_REG_BASE +0x509c7*4+0x02000000,0xaa23); +reg_write( DDR_REG_BASE +0x509c8*4+0x02000000,0x8a04); +reg_write( DDR_REG_BASE +0x509c9*4+0x02000000,0x7b34); +reg_write( DDR_REG_BASE +0x509ca*4+0x02000000,0xaa02); +reg_write( DDR_REG_BASE +0x509cb*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x509cc*4+0x02000000,0xaa00); +reg_write( DDR_REG_BASE +0x509cd*4+0x02000000,0xaa61); +reg_write( DDR_REG_BASE +0x509ce*4+0x02000000,0x9600); +reg_write( DDR_REG_BASE +0x509cf*4+0x02000000,0x829); +reg_write( DDR_REG_BASE +0x509d0*4+0x02000000,0x151); +reg_write( DDR_REG_BASE +0x509d1*4+0x02000000,0xb4a1); +reg_write( DDR_REG_BASE +0x509d2*4+0x02000000,0xf015); +reg_write( DDR_REG_BASE +0x509d3*4+0x02000000,0x1c02); +reg_write( DDR_REG_BASE +0x509d4*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x509d5*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x509d6*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x509d7*4+0x02000000,0xfe); +reg_write( DDR_REG_BASE +0x509d8*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x509d9*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x509da*4+0x02000000,0x3c5); +reg_write( DDR_REG_BASE +0x509db*4+0x02000000,0x19f8); +reg_write( DDR_REG_BASE +0x509dc*4+0x02000000,0x8004); +reg_write( DDR_REG_BASE +0x509dd*4+0x02000000,0x19f6); +reg_write( DDR_REG_BASE +0x509de*4+0x02000000,0x8005); +reg_write( DDR_REG_BASE +0x509df*4+0x02000000,0x19fe); +reg_write( DDR_REG_BASE +0x509e0*4+0x02000000,0x8005); +reg_write( DDR_REG_BASE +0x509e1*4+0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x509e2*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x509e3*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x509e4*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x509e5*4+0x02000000,0x58); +reg_write( DDR_REG_BASE +0x509e6*4+0x02000000,0xb401); +reg_write( DDR_REG_BASE +0x509e7*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x509e8*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x509e9*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x509ea*4+0x02000000,0xf6); +reg_write( DDR_REG_BASE +0x509eb*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x509ec*4+0x02000000,0xb024); +reg_write( DDR_REG_BASE +0x509ed*4+0x02000000,0x18fe); +reg_write( DDR_REG_BASE +0x509ee*4+0x02000000,0x8044); +reg_write( DDR_REG_BASE +0x509ef*4+0x02000000,0xb023); +reg_write( DDR_REG_BASE +0x509f0*4+0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x509f1*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x509f2*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x509f3*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x509f4*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x509f5*4+0x02000000,0xc1a5); +reg_write( DDR_REG_BASE +0x509f6*4+0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x509f7*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x509f8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x509f9*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x509fa*4+0x02000000,0x88c0); +reg_write( DDR_REG_BASE +0x509fb*4+0x02000000,0x2753); +reg_write( DDR_REG_BASE +0x509fc*4+0x02000000,0x1040); +reg_write( DDR_REG_BASE +0x509fd*4+0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x509fe*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x509ff*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x50a00*4+0x02000000,0xc144); +reg_write( DDR_REG_BASE +0x50a01*4+0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x50a02*4+0x02000000,0xcde); +reg_write( DDR_REG_BASE +0x50a03*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50a04*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x50a05*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x50a06*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50a07*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x50a08*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x50a09*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50a0a*4+0x02000000,0x9d6); +reg_write( DDR_REG_BASE +0x50a0b*4+0x02000000,0x260); +reg_write( DDR_REG_BASE +0x50a0c*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50a0d*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50a0e*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50a0f*4+0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x50a10*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50a11*4+0x02000000,0xda40); +reg_write( DDR_REG_BASE +0x50a12*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50a13*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50a14*4+0x02000000,0x95e); +reg_write( DDR_REG_BASE +0x50a15*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50a16*4+0x02000000,0xda7f); +reg_write( DDR_REG_BASE +0x50a17*4+0x02000000,0x275f); +reg_write( DDR_REG_BASE +0x50a18*4+0x02000000,0x1100); +reg_write( DDR_REG_BASE +0x50a19*4+0x02000000,0x43db); +reg_write( DDR_REG_BASE +0x50a1a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50a1b*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x50a1c*4+0x02000000,0x7f05); +reg_write( DDR_REG_BASE +0x50a1d*4+0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x50a1e*4+0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x50a1f*4+0x02000000,0xe814); +reg_write( DDR_REG_BASE +0x50a20*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50a21*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50a22*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50a23*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50a24*4+0x02000000,0x81d); +reg_write( DDR_REG_BASE +0x50a25*4+0x02000000,0xdf); +reg_write( DDR_REG_BASE +0x50a26*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50a27*4+0x02000000,0xf863); +reg_write( DDR_REG_BASE +0x50a28*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x50a29*4+0x02000000,0x3001); +reg_write( DDR_REG_BASE +0x50a2a*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x50a2b*4+0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x50a2c*4+0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x50a2d*4+0x02000000,0x61b9); +reg_write( DDR_REG_BASE +0x50a2e*4+0x02000000,0xd2a); +reg_write( DDR_REG_BASE +0x50a2f*4+0x02000000,0x2e0); +reg_write( DDR_REG_BASE +0x50a30*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50a31*4+0x02000000,0xf00b); +reg_write( DDR_REG_BASE +0x50a32*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50a33*4+0x02000000,0xf85d); +reg_write( DDR_REG_BASE +0x50a34*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x50a35*4+0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x50a36*4+0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x50a37*4+0x02000000,0x61b9); +reg_write( DDR_REG_BASE +0x50a38*4+0x02000000,0xbce); +reg_write( DDR_REG_BASE +0x50a39*4+0x02000000,0x2e0); +reg_write( DDR_REG_BASE +0x50a3a*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50a3b*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50a3c*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x50a3d*4+0x02000000,0xe04c); +reg_write( DDR_REG_BASE +0x50a3e*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x50a3f*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x50a40*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x50a41*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x50a42*4+0x02000000,0x18fc); +reg_write( DDR_REG_BASE +0x50a43*4+0x02000000,0x8044); +reg_write( DDR_REG_BASE +0x50a44*4+0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x50a45*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x50a46*4+0x02000000,0xe8aa); +reg_write( DDR_REG_BASE +0x50a47*4+0x02000000,0xf022); +reg_write( DDR_REG_BASE +0x50a48*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x50a49*4+0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x50a4a*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50a4b*4+0x02000000,0x2116); +reg_write( DDR_REG_BASE +0x50a4c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50a4d*4+0x02000000,0x7061); +reg_write( DDR_REG_BASE +0x50a4e*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x50a4f*4+0x02000000,0xf9e); +reg_write( DDR_REG_BASE +0x50a50*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50a51*4+0x02000000,0x7a8); +reg_write( DDR_REG_BASE +0x50a52*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x50a53*4+0x02000000,0xe06); +reg_write( DDR_REG_BASE +0x50a54*4+0x02000000,0x260); +reg_write( DDR_REG_BASE +0x50a55*4+0x02000000,0x210a); +reg_write( DDR_REG_BASE +0x50a56*4+0x02000000,0x780); +reg_write( DDR_REG_BASE +0x50a57*4+0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x50a58*4+0x02000000,0x3f82); +reg_write( DDR_REG_BASE +0x50a59*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50a5a*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x50a5b*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50a5c*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50a5d*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50a5e*4+0x02000000,0xb88a); +reg_write( DDR_REG_BASE +0x50a5f*4+0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x50a60*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x50a61*4+0x02000000,0x43); +reg_write( DDR_REG_BASE +0x50a62*4+0x02000000,0xb964); +reg_write( DDR_REG_BASE +0x50a63*4+0x02000000,0x7945); +reg_write( DDR_REG_BASE +0x50a64*4+0x02000000,0xb300); +reg_write( DDR_REG_BASE +0x50a65*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50a66*4+0x02000000,0xfc5); +reg_write( DDR_REG_BASE +0x50a67*4+0x02000000,0xb300); +reg_write( DDR_REG_BASE +0x50a68*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50a69*4+0x02000000,0x78d4); +reg_write( DDR_REG_BASE +0x50a6a*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x50a6b*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50a6c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50a6d*4+0x02000000,0x784); +reg_write( DDR_REG_BASE +0x50a6e*4+0x02000000,0xbb5); +reg_write( DDR_REG_BASE +0x50a6f*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50a70*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50a71*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50a72*4+0x02000000,0x8a2); +reg_write( DDR_REG_BASE +0x50a73*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50a74*4+0x02000000,0xda7f); +reg_write( DDR_REG_BASE +0x50a75*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50a76*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50a77*4+0x02000000,0xebe); +reg_write( DDR_REG_BASE +0x50a78*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50a79*4+0x02000000,0xda49); +reg_write( DDR_REG_BASE +0x50a7a*4+0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x50a7b*4+0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x50a7c*4+0x02000000,0xe813); +reg_write( DDR_REG_BASE +0x50a7d*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50a7e*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50a7f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50a80*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50a81*4+0x02000000,0x81f); +reg_write( DDR_REG_BASE +0x50a82*4+0x02000000,0xdf); +reg_write( DDR_REG_BASE +0x50a83*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50a84*4+0x02000000,0xf82f); +reg_write( DDR_REG_BASE +0x50a85*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x50a86*4+0x02000000,0x3001); +reg_write( DDR_REG_BASE +0x50a87*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x50a88*4+0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x50a89*4+0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x50a8a*4+0x02000000,0x61b9); +reg_write( DDR_REG_BASE +0x50a8b*4+0x02000000,0xc72); +reg_write( DDR_REG_BASE +0x50a8c*4+0x02000000,0x2e0); +reg_write( DDR_REG_BASE +0x50a8d*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50a8e*4+0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x50a8f*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50a90*4+0x02000000,0xf829); +reg_write( DDR_REG_BASE +0x50a91*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x50a92*4+0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x50a93*4+0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x50a94*4+0x02000000,0x61b9); +reg_write( DDR_REG_BASE +0x50a95*4+0x02000000,0xb16); +reg_write( DDR_REG_BASE +0x50a96*4+0x02000000,0x2e0); +reg_write( DDR_REG_BASE +0x50a97*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50a98*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50a99*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50a9a*4+0x02000000,0x2710); +reg_write( DDR_REG_BASE +0x50a9b*4+0x02000000,0xbaa); +reg_write( DDR_REG_BASE +0x50a9c*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50a9d*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50a9e*4+0x02000000,0x952); +reg_write( DDR_REG_BASE +0x50a9f*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x50aa0*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50aa1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50aa2*4+0x02000000,0x1d4c); +reg_write( DDR_REG_BASE +0x50aa3*4+0x02000000,0xb9a); +reg_write( DDR_REG_BASE +0x50aa4*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50aa5*4+0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x50aa6*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50aa7*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x50aa8*4+0x02000000,0xf7a0); +reg_write( DDR_REG_BASE +0x50aa9*4+0x02000000,0xb8e); +reg_write( DDR_REG_BASE +0x50aaa*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50aab*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50aac*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50aad*4+0x02000000,0xc92); +reg_write( DDR_REG_BASE +0x50aae*4+0x02000000,0x220); +reg_write( DDR_REG_BASE +0x50aaf*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50ab0*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x50ab1*4+0x02000000,0xe8ad); +reg_write( DDR_REG_BASE +0x50ab2*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50ab3*4+0x02000000,0xf023); +reg_write( DDR_REG_BASE +0x50ab4*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x50ab5*4+0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x50ab6*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50ab7*4+0x02000000,0x7916); +reg_write( DDR_REG_BASE +0x50ab8*4+0x02000000,0x61b8); +reg_write( DDR_REG_BASE +0x50ab9*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x50aba*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x50abb*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50abc*4+0x02000000,0x7a8); +reg_write( DDR_REG_BASE +0x50abd*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x50abe*4+0x02000000,0xd2e); +reg_write( DDR_REG_BASE +0x50abf*4+0x02000000,0x260); +reg_write( DDR_REG_BASE +0x50ac0*4+0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x50ac1*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50ac2*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x50ac3*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x50ac4*4+0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x50ac5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50ac6*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x50ac7*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x50ac8*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x50ac9*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x50aca*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50acb*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50acc*4+0x02000000,0xb260); +reg_write( DDR_REG_BASE +0x50acd*4+0x02000000,0x204f); +reg_write( DDR_REG_BASE +0x50ace*4+0x02000000,0x283); +reg_write( DDR_REG_BASE +0x50acf*4+0x02000000,0xb260); +reg_write( DDR_REG_BASE +0x50ad0*4+0x02000000,0x9e7); +reg_write( DDR_REG_BASE +0x50ad1*4+0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x50ad2*4+0x02000000,0x204f); +reg_write( DDR_REG_BASE +0x50ad3*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x50ad4*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x50ad5*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50ad6*4+0x02000000,0x78d4); +reg_write( DDR_REG_BASE +0x50ad7*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x50ad8*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50ad9*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50ada*4+0x02000000,0x784); +reg_write( DDR_REG_BASE +0x50adb*4+0x02000000,0xdb5); +reg_write( DDR_REG_BASE +0x50adc*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50add*4+0x02000000,0xc0a5); +reg_write( DDR_REG_BASE +0x50ade*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50adf*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50ae0*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50ae1*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50ae2*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x50ae3*4+0x02000000,0x1c82); +reg_write( DDR_REG_BASE +0x50ae4*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x50ae5*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x50ae6*4+0x02000000,0xdfff); +reg_write( DDR_REG_BASE +0x50ae7*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x50ae8*4+0x02000000,0x641); +reg_write( DDR_REG_BASE +0x50ae9*4+0x02000000,0x78ef); +reg_write( DDR_REG_BASE +0x50aea*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50aeb*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50aec*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x50aed*4+0x02000000,0x1c82); +reg_write( DDR_REG_BASE +0x50aee*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x50aef*4+0x02000000,0xffbf); +reg_write( DDR_REG_BASE +0x50af0*4+0x02000000,0x87f7); +reg_write( DDR_REG_BASE +0x50af1*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x50af2*4+0x02000000,0x641); +reg_write( DDR_REG_BASE +0x50af3*4+0x02000000,0x78ef); +reg_write( DDR_REG_BASE +0x50af4*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50af5*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50af6*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50af7*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50af8*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50af9*4+0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x50afa*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50afb*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50afc*4+0x02000000,0xf4); +reg_write( DDR_REG_BASE +0x50afd*4+0x02000000,0x9600); +reg_write( DDR_REG_BASE +0x50afe*4+0x02000000,0x6ea2); +reg_write( DDR_REG_BASE +0x50aff*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50b00*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50b01*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50b02*4+0x02000000,0x1500); +reg_write( DDR_REG_BASE +0x50b03*4+0x02000000,0x111b); +reg_write( DDR_REG_BASE +0x50b04*4+0x02000000,0x95e3); +reg_write( DDR_REG_BASE +0x50b05*4+0x02000000,0x1508); +reg_write( DDR_REG_BASE +0x50b06*4+0x02000000,0x110b); +reg_write( DDR_REG_BASE +0x50b07*4+0x02000000,0x1d08); +reg_write( DDR_REG_BASE +0x50b08*4+0x02000000,0x13c5); +reg_write( DDR_REG_BASE +0x50b09*4+0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x50b0a*4+0x02000000,0x1d06); +reg_write( DDR_REG_BASE +0x50b0b*4+0x02000000,0x13c5); +reg_write( DDR_REG_BASE +0x50b0c*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x50b0d*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50b0e*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50b0f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50b10*4+0x02000000,0x7c8); +reg_write( DDR_REG_BASE +0x50b11*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50b12*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x50b13*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x50b14*4+0x02000000,0x190); +reg_write( DDR_REG_BASE +0x50b15*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50b16*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50b17*4+0x02000000,0x2af8); +reg_write( DDR_REG_BASE +0x50b18*4+0x02000000,0xaae); +reg_write( DDR_REG_BASE +0x50b19*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50b1a*4+0x02000000,0x1efa); +reg_write( DDR_REG_BASE +0x50b1b*4+0x02000000,0x9485); +reg_write( DDR_REG_BASE +0x50b1c*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50b1d*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x50b1e*4+0x02000000,0xb5e3); +reg_write( DDR_REG_BASE +0x50b1f*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50b20*4+0x02000000,0x16c4); +reg_write( DDR_REG_BASE +0x50b21*4+0x02000000,0x1d08); +reg_write( DDR_REG_BASE +0x50b22*4+0x02000000,0x12c4); +reg_write( DDR_REG_BASE +0x50b23*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50b24*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50b25*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50b26*4+0x02000000,0x7c8); +reg_write( DDR_REG_BASE +0x50b27*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50b28*4+0x02000000,0xb8a0); +reg_write( DDR_REG_BASE +0x50b29*4+0x02000000,0x6829); +reg_write( DDR_REG_BASE +0x50b2a*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50b2b*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50b2c*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x50b2d*4+0x02000000,0xa821); +reg_write( DDR_REG_BASE +0x50b2e*4+0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x50b2f*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50b30*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50b31*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50b32*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50b33*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50b34*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50b35*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x50b36*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50b37*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x50b38*4+0x02000000,0x9720); +reg_write( DDR_REG_BASE +0x50b39*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50b3a*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50b3b*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50b3c*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50b3d*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50b3e*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x50b3f*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x50b40*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x50b41*4+0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x50b42*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x50b43*4+0x02000000,0xea06); +reg_write( DDR_REG_BASE +0x50b44*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x50b45*4+0x02000000,0xa01); +reg_write( DDR_REG_BASE +0x50b46*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x50b47*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50b48*4+0x02000000,0xb8c3); +reg_write( DDR_REG_BASE +0x50b49*4+0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x50b4a*4+0x02000000,0x70); +reg_write( DDR_REG_BASE +0x50b4b*4+0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x50b4c*4+0x02000000,0x807); +reg_write( DDR_REG_BASE +0x50b4d*4+0x02000000,0x190); +reg_write( DDR_REG_BASE +0x50b4e*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x50b4f*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50b50*4+0x02000000,0xa3e); +reg_write( DDR_REG_BASE +0x50b51*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50b52*4+0x02000000,0xd940); +reg_write( DDR_REG_BASE +0x50b53*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50b54*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x50b55*4+0x02000000,0xe112); +reg_write( DDR_REG_BASE +0x50b56*4+0x02000000,0x1ede); +reg_write( DDR_REG_BASE +0x50b57*4+0x02000000,0x1055); +reg_write( DDR_REG_BASE +0x50b58*4+0x02000000,0x1ea6); +reg_write( DDR_REG_BASE +0x50b59*4+0x02000000,0x9055); +reg_write( DDR_REG_BASE +0x50b5a*4+0x02000000,0x17b6); +reg_write( DDR_REG_BASE +0x50b5b*4+0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x50b5c*4+0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x50b5d*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50b5e*4+0x02000000,0xed29); +reg_write( DDR_REG_BASE +0x50b5f*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50b60*4+0x02000000,0x84f); +reg_write( DDR_REG_BASE +0x50b61*4+0x02000000,0x3bf); +reg_write( DDR_REG_BASE +0x50b62*4+0x02000000,0xd91c); +reg_write( DDR_REG_BASE +0x50b63*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50b64*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x50b65*4+0x02000000,0xc07); +reg_write( DDR_REG_BASE +0x50b66*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50b67*4+0x02000000,0xb88f); +reg_write( DDR_REG_BASE +0x50b68*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x50b69*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50b6a*4+0x02000000,0xa0a); +reg_write( DDR_REG_BASE +0x50b6b*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50b6c*4+0x02000000,0x1ef6); +reg_write( DDR_REG_BASE +0x50b6d*4+0x02000000,0x9205); +reg_write( DDR_REG_BASE +0x50b6e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50b6f*4+0x02000000,0xf); +reg_write( DDR_REG_BASE +0x50b70*4+0x02000000,0x4240); +reg_write( DDR_REG_BASE +0x50b71*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50b72*4+0x02000000,0x9fa); +reg_write( DDR_REG_BASE +0x50b73*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50b74*4+0x02000000,0x1ef6); +reg_write( DDR_REG_BASE +0x50b75*4+0x02000000,0x9245); +reg_write( DDR_REG_BASE +0x50b76*4+0x02000000,0x17be); +reg_write( DDR_REG_BASE +0x50b77*4+0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x50b78*4+0x02000000,0x1ef0); +reg_write( DDR_REG_BASE +0x50b79*4+0x02000000,0x9045); +reg_write( DDR_REG_BASE +0x50b7a*4+0x02000000,0x1ef6); +reg_write( DDR_REG_BASE +0x50b7b*4+0x02000000,0x9205); +reg_write( DDR_REG_BASE +0x50b7c*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x50b7d*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x50b7e*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x50b7f*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x50b80*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50b81*4+0x02000000,0x3e00); +reg_write( DDR_REG_BASE +0x50b82*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50b83*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50b84*4+0x02000000,0xb88e); +reg_write( DDR_REG_BASE +0x50b85*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x50b86*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x50b87*4+0x02000000,0x1ef6); +reg_write( DDR_REG_BASE +0x50b88*4+0x02000000,0x9205); +reg_write( DDR_REG_BASE +0x50b89*4+0x02000000,0x1ef0); +reg_write( DDR_REG_BASE +0x50b8a*4+0x02000000,0x9045); +reg_write( DDR_REG_BASE +0x50b8b*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50b8c*4+0x02000000,0x76c4); +reg_write( DDR_REG_BASE +0x50b8d*4+0x02000000,0x9013); +reg_write( DDR_REG_BASE +0x50b8e*4+0x02000000,0xe050); +reg_write( DDR_REG_BASE +0x50b8f*4+0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x50b90*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50b91*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50b92*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50b93*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50b94*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50b95*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50b96*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50b97*4+0x02000000,0xc1a2); +reg_write( DDR_REG_BASE +0x50b98*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x50b99*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50b9a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50b9b*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x50b9c*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x50b9d*4+0x02000000,0x9b); +reg_write( DDR_REG_BASE +0x50b9e*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x50b9f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50ba0*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x50ba1*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50ba2*4+0x02000000,0xea6); +reg_write( DDR_REG_BASE +0x50ba3*4+0x02000000,0x220); +reg_write( DDR_REG_BASE +0x50ba4*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50ba5*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50ba6*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50ba7*4+0x02000000,0xe3a); +reg_write( DDR_REG_BASE +0x50ba8*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50ba9*4+0x02000000,0xda7f); +reg_write( DDR_REG_BASE +0x50baa*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50bab*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50bac*4+0x02000000,0xe2e); +reg_write( DDR_REG_BASE +0x50bad*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50bae*4+0x02000000,0xdafe); +reg_write( DDR_REG_BASE +0x50baf*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50bb0*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50bb1*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x50bb2*4+0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x50bb3*4+0x02000000,0x2653); +reg_write( DDR_REG_BASE +0x50bb4*4+0x02000000,0x104f); +reg_write( DDR_REG_BASE +0x50bb5*4+0x02000000,0xe81c); +reg_write( DDR_REG_BASE +0x50bb6*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50bb7*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50bb8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50bb9*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50bba*4+0x02000000,0x82d); +reg_write( DDR_REG_BASE +0x50bbb*4+0x02000000,0xff); +reg_write( DDR_REG_BASE +0x50bbc*4+0x02000000,0x2778); +reg_write( DDR_REG_BASE +0x50bbd*4+0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x50bbe*4+0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x50bbf*4+0x02000000,0x3c82); +reg_write( DDR_REG_BASE +0x50bc0*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x50bc1*4+0x02000000,0x641); +reg_write( DDR_REG_BASE +0x50bc2*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x50bc3*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x50bc4*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x50bc5*4+0x02000000,0xdfff); +reg_write( DDR_REG_BASE +0x50bc6*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x50bc7*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x50bc8*4+0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x50bc9*4+0x02000000,0x61b9); +reg_write( DDR_REG_BASE +0x50bca*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50bcb*4+0x02000000,0x9f2); +reg_write( DDR_REG_BASE +0x50bcc*4+0x02000000,0x2e0); +reg_write( DDR_REG_BASE +0x50bcd*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x50bce*4+0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x50bcf*4+0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x50bd0*4+0x02000000,0xe12); +reg_write( DDR_REG_BASE +0x50bd1*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x50bd2*4+0x02000000,0x2778); +reg_write( DDR_REG_BASE +0x50bd3*4+0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x50bd4*4+0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x50bd5*4+0x02000000,0x3c82); +reg_write( DDR_REG_BASE +0x50bd6*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x50bd7*4+0x02000000,0x641); +reg_write( DDR_REG_BASE +0x50bd8*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x50bd9*4+0x02000000,0x1100); +reg_write( DDR_REG_BASE +0x50bda*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x50bdb*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x50bdc*4+0x02000000,0xdfff); +reg_write( DDR_REG_BASE +0x50bdd*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x50bde*4+0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x50bdf*4+0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x50be0*4+0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x50be1*4+0x02000000,0x61b9); +reg_write( DDR_REG_BASE +0x50be2*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x50be3*4+0x02000000,0x87a); +reg_write( DDR_REG_BASE +0x50be4*4+0x02000000,0x2e0); +reg_write( DDR_REG_BASE +0x50be5*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50be6*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50be7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50be8*4+0x02000000,0x36b0); +reg_write( DDR_REG_BASE +0x50be9*4+0x02000000,0x90e); +reg_write( DDR_REG_BASE +0x50bea*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50beb*4+0x02000000,0xd90a); +reg_write( DDR_REG_BASE +0x50bec*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50bed*4+0x02000000,0xa12); +reg_write( DDR_REG_BASE +0x50bee*4+0x02000000,0x220); +reg_write( DDR_REG_BASE +0x50bef*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50bf0*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50bf1*4+0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x50bf2*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x50bf3*4+0x02000000,0xe048); +reg_write( DDR_REG_BASE +0x50bf4*4+0x02000000,0xc0a2); +reg_write( DDR_REG_BASE +0x50bf5*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50bf6*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50bf7*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50bf8*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50bf9*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50bfa*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50bfb*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50bfc*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50bfd*4+0x02000000,0xf4); +reg_write( DDR_REG_BASE +0x50bfe*4+0x02000000,0x6ea2); +reg_write( DDR_REG_BASE +0x50bff*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50c00*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50c01*4+0x02000000,0x111b); +reg_write( DDR_REG_BASE +0x50c02*4+0x02000000,0x1500); +reg_write( DDR_REG_BASE +0x50c03*4+0x02000000,0x111e); +reg_write( DDR_REG_BASE +0x50c04*4+0x02000000,0x1506); +reg_write( DDR_REG_BASE +0x50c05*4+0x02000000,0x110b); +reg_write( DDR_REG_BASE +0x50c06*4+0x02000000,0x95e4); +reg_write( DDR_REG_BASE +0x50c07*4+0x02000000,0x1d08); +reg_write( DDR_REG_BASE +0x50c08*4+0x02000000,0x13c5); +reg_write( DDR_REG_BASE +0x50c09*4+0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x50c0a*4+0x02000000,0x1d06); +reg_write( DDR_REG_BASE +0x50c0b*4+0x02000000,0x13c5); +reg_write( DDR_REG_BASE +0x50c0c*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x50c0d*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50c0e*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50c0f*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x50c10*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x50c11*4+0x02000000,0x190); +reg_write( DDR_REG_BASE +0x50c12*4+0x02000000,0xd834); +reg_write( DDR_REG_BASE +0x50c13*4+0x02000000,0x1efa); +reg_write( DDR_REG_BASE +0x50c14*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50c15*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50c16*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50c17*4+0x02000000,0x2af8); +reg_write( DDR_REG_BASE +0x50c18*4+0x02000000,0x8ae); +reg_write( DDR_REG_BASE +0x50c19*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50c1a*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50c1b*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50c1c*4+0x02000000,0x16c4); +reg_write( DDR_REG_BASE +0x50c1d*4+0x02000000,0x1d06); +reg_write( DDR_REG_BASE +0x50c1e*4+0x02000000,0x12c4); +reg_write( DDR_REG_BASE +0x50c1f*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50c20*4+0x02000000,0x1784); +reg_write( DDR_REG_BASE +0x50c21*4+0x02000000,0xb5e4); +reg_write( DDR_REG_BASE +0x50c22*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50c23*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50c24*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50c25*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50c26*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50c27*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50c28*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50c29*4+0x02000000,0x236f); +reg_write( DDR_REG_BASE +0x50c2a*4+0x02000000,0x343); +reg_write( DDR_REG_BASE +0x50c2b*4+0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x50c2c*4+0x02000000,0x3040); +reg_write( DDR_REG_BASE +0x50c2d*4+0x02000000,0x9320); +reg_write( DDR_REG_BASE +0x50c2e*4+0x02000000,0x4348); +reg_write( DDR_REG_BASE +0x50c2f*4+0x02000000,0x218c); +reg_write( DDR_REG_BASE +0x50c30*4+0x02000000,0x864a); +reg_write( DDR_REG_BASE +0x50c31*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x50c32*4+0x02000000,0x2d); +reg_write( DDR_REG_BASE +0x50c33*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x50c34*4+0x02000000,0xe02); +reg_write( DDR_REG_BASE +0x50c35*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x50c36*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x50c37*4+0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x50c38*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x50c39*4+0x02000000,0x2042); +reg_write( DDR_REG_BASE +0x50c3a*4+0x02000000,0x11b); +reg_write( DDR_REG_BASE +0x50c3b*4+0x02000000,0x13fe); +reg_write( DDR_REG_BASE +0x50c3c*4+0x02000000,0x8080); +reg_write( DDR_REG_BASE +0x50c3d*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50c3e*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50c3f*4+0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x50c40*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x50c41*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50c42*4+0x02000000,0xf02a); +reg_write( DDR_REG_BASE +0x50c43*4+0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x50c44*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x50c45*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50c46*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x50c47*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50c48*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x50c49*4+0x02000000,0x381); +reg_write( DDR_REG_BASE +0x50c4a*4+0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x50c4b*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x50c4c*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50c4d*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50c4e*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x50c4f*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x50c50*4+0x02000000,0xf8f); +reg_write( DDR_REG_BASE +0x50c51*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50c52*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50c53*4+0x02000000,0xe4a); +reg_write( DDR_REG_BASE +0x50c54*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50c55*4+0x02000000,0x9700); +reg_write( DDR_REG_BASE +0x50c56*4+0x02000000,0x7063); +reg_write( DDR_REG_BASE +0x50c57*4+0x02000000,0x7a0e); +reg_write( DDR_REG_BASE +0x50c58*4+0x02000000,0x785c); +reg_write( DDR_REG_BASE +0x50c59*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x50c5a*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x50c5b*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x50c5c*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x50c5d*4+0x02000000,0xd81b); +reg_write( DDR_REG_BASE +0x50c5e*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x50c5f*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x50c60*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x50c61*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50c62*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x50c63*4+0x02000000,0x6238); +reg_write( DDR_REG_BASE +0x50c64*4+0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x50c65*4+0x02000000,0x4831); +reg_write( DDR_REG_BASE +0x50c66*4+0x02000000,0x2a44); +reg_write( DDR_REG_BASE +0x50c67*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x50c68*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x50c69*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50c6a*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50c6b*4+0x02000000,0xb700); +reg_write( DDR_REG_BASE +0x50c6c*4+0x02000000,0xbaf); +reg_write( DDR_REG_BASE +0x50c6d*4+0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x50c6e*4+0x02000000,0x2555); +reg_write( DDR_REG_BASE +0x50c6f*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x50c70*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50c71*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50c72*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50c73*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50c74*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x50c75*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x50c76*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50c77*4+0x02000000,0x6); +reg_write( DDR_REG_BASE +0x50c78*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x50c79*4+0x02000000,0xf96); +reg_write( DDR_REG_BASE +0x50c7a*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50c7b*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50c7c*4+0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x50c7d*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50c7e*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x50c7f*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x50c80*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50c81*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x50c82*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50c83*4+0x02000000,0x1c6); +reg_write( DDR_REG_BASE +0x50c84*4+0x02000000,0x95c0); +reg_write( DDR_REG_BASE +0x50c85*4+0x02000000,0xbecb); +reg_write( DDR_REG_BASE +0x50c86*4+0x02000000,0x264f); +reg_write( DDR_REG_BASE +0x50c87*4+0x02000000,0x12cf); +reg_write( DDR_REG_BASE +0x50c88*4+0x02000000,0x2605); +reg_write( DDR_REG_BASE +0x50c89*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x50c8a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50c8b*4+0x02000000,0xc00); +reg_write( DDR_REG_BASE +0x50c8c*4+0x02000000,0xb5e0); +reg_write( DDR_REG_BASE +0x50c8d*4+0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x50c8e*4+0x02000000,0xf6a); +reg_write( DDR_REG_BASE +0x50c8f*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50c90*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x50c91*4+0x02000000,0xb5e0); +reg_write( DDR_REG_BASE +0x50c92*4+0x02000000,0x9501); +reg_write( DDR_REG_BASE +0x50c93*4+0x02000000,0xb5c0); +reg_write( DDR_REG_BASE +0x50c94*4+0x02000000,0xb8c9); +reg_write( DDR_REG_BASE +0x50c95*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50c96*4+0x02000000,0xc1e2); +reg_write( DDR_REG_BASE +0x50c97*4+0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x50c98*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x50c99*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x50c9a*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50c9b*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x50c9c*4+0x02000000,0x86); +reg_write( DDR_REG_BASE +0x50c9d*4+0x02000000,0x9020); +reg_write( DDR_REG_BASE +0x50c9e*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50c9f*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50ca0*4+0x02000000,0x2153); +reg_write( DDR_REG_BASE +0x50ca1*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x50ca2*4+0x02000000,0x1c02); +reg_write( DDR_REG_BASE +0x50ca3*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x50ca4*4+0x02000000,0x783d); +reg_write( DDR_REG_BASE +0x50ca5*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50ca6*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50ca7*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50ca8*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50ca9*4+0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x50caa*4+0x02000000,0x1c03); +reg_write( DDR_REG_BASE +0x50cab*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x50cac*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x50cad*4+0x02000000,0x606c); +reg_write( DDR_REG_BASE +0x50cae*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x50caf*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50cb0*4+0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x50cb1*4+0x02000000,0x61b9); +reg_write( DDR_REG_BASE +0x50cb2*4+0x02000000,0x7c9d); +reg_write( DDR_REG_BASE +0x50cb3*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x50cb4*4+0x02000000,0x8fb); +reg_write( DDR_REG_BASE +0x50cb5*4+0x02000000,0x8174); +reg_write( DDR_REG_BASE +0x50cb6*4+0x02000000,0x2444); +reg_write( DDR_REG_BASE +0x50cb7*4+0x02000000,0x104d); +reg_write( DDR_REG_BASE +0x50cb8*4+0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x50cb9*4+0x02000000,0xd978); +reg_write( DDR_REG_BASE +0x50cba*4+0x02000000,0x2905); +reg_write( DDR_REG_BASE +0x50cbb*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50cbc*4+0x02000000,0x784f); +reg_write( DDR_REG_BASE +0x50cbd*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x50cbe*4+0x02000000,0x611a); +reg_write( DDR_REG_BASE +0x50cbf*4+0x02000000,0xbdf); +reg_write( DDR_REG_BASE +0x50cc0*4+0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x50cc1*4+0x02000000,0x2440); +reg_write( DDR_REG_BASE +0x50cc2*4+0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x50cc3*4+0x02000000,0x2284); +reg_write( DDR_REG_BASE +0x50cc4*4+0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x50cc5*4+0x02000000,0x785d); +reg_write( DDR_REG_BASE +0x50cc6*4+0x02000000,0xc5c2); +reg_write( DDR_REG_BASE +0x50cc7*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50cc8*4+0x02000000,0x701); +reg_write( DDR_REG_BASE +0x50cc9*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50cca*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x50ccb*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50ccc*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50ccd*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50cce*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50ccf*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x50cd0*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50cd1*4+0x02000000,0x711e); +reg_write( DDR_REG_BASE +0x50cd2*4+0x02000000,0x9018); +reg_write( DDR_REG_BASE +0x50cd3*4+0x02000000,0x1dc); +reg_write( DDR_REG_BASE +0x50cd4*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50cd5*4+0x02000000,0x308c); +reg_write( DDR_REG_BASE +0x50cd6*4+0x02000000,0xc609); +reg_write( DDR_REG_BASE +0x50cd7*4+0x02000000,0x4378); +reg_write( DDR_REG_BASE +0x50cd8*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50cd9*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x50cda*4+0x02000000,0x43cb); +reg_write( DDR_REG_BASE +0x50cdb*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50cdc*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x50cdd*4+0x02000000,0x2705); +reg_write( DDR_REG_BASE +0x50cde*4+0x02000000,0x32cd); +reg_write( DDR_REG_BASE +0x50cdf*4+0x02000000,0x95a0); +reg_write( DDR_REG_BASE +0x50ce0*4+0x02000000,0xc780); +reg_write( DDR_REG_BASE +0x50ce1*4+0x02000000,0x677f); +reg_write( DDR_REG_BASE +0x50ce2*4+0x02000000,0x2340); +reg_write( DDR_REG_BASE +0x50ce3*4+0x02000000,0x180b); +reg_write( DDR_REG_BASE +0x50ce4*4+0x02000000,0xafa0); +reg_write( DDR_REG_BASE +0x50ce5*4+0x02000000,0x2705); +reg_write( DDR_REG_BASE +0x50ce6*4+0x02000000,0x32cd); +reg_write( DDR_REG_BASE +0x50ce7*4+0x02000000,0x95a0); +reg_write( DDR_REG_BASE +0x50ce8*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x50ce9*4+0x02000000,0xe508); +reg_write( DDR_REG_BASE +0x50cea*4+0x02000000,0xafa8); +reg_write( DDR_REG_BASE +0x50ceb*4+0x02000000,0xbe1); +reg_write( DDR_REG_BASE +0x50cec*4+0x02000000,0x81b4); +reg_write( DDR_REG_BASE +0x50ced*4+0x02000000,0x272f); +reg_write( DDR_REG_BASE +0x50cee*4+0x02000000,0x30c0); +reg_write( DDR_REG_BASE +0x50cef*4+0x02000000,0xe48c); +reg_write( DDR_REG_BASE +0x50cf0*4+0x02000000,0x304); +reg_write( DDR_REG_BASE +0x50cf1*4+0x02000000,0x2d); +reg_write( DDR_REG_BASE +0x50cf2*4+0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x50cf3*4+0x02000000,0x205); +reg_write( DDR_REG_BASE +0x50cf4*4+0x02000000,0xb9d); +reg_write( DDR_REG_BASE +0x50cf5*4+0x02000000,0x32e); +reg_write( DDR_REG_BASE +0x50cf6*4+0x02000000,0x746d); +reg_write( DDR_REG_BASE +0x50cf7*4+0x02000000,0xc0f); +reg_write( DDR_REG_BASE +0x50cf8*4+0x02000000,0x1230); +reg_write( DDR_REG_BASE +0x50cf9*4+0x02000000,0x1b00); +reg_write( DDR_REG_BASE +0x50cfa*4+0x02000000,0x32c2); +reg_write( DDR_REG_BASE +0x50cfb*4+0x02000000,0x7695); +reg_write( DDR_REG_BASE +0x50cfc*4+0x02000000,0xf4af); +reg_write( DDR_REG_BASE +0x50cfd*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x50cfe*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50cff*4+0x02000000,0xaea3); +reg_write( DDR_REG_BASE +0x50d00*4+0x02000000,0xaea2); +reg_write( DDR_REG_BASE +0x50d01*4+0x02000000,0xae61); +reg_write( DDR_REG_BASE +0x50d02*4+0x02000000,0xae60); +reg_write( DDR_REG_BASE +0x50d03*4+0x02000000,0x75ed); +reg_write( DDR_REG_BASE +0x50d04*4+0x02000000,0x73cd); +reg_write( DDR_REG_BASE +0x50d05*4+0x02000000,0x728d); +reg_write( DDR_REG_BASE +0x50d06*4+0x02000000,0xa9e3); +reg_write( DDR_REG_BASE +0x50d07*4+0x02000000,0xa9c2); +reg_write( DDR_REG_BASE +0x50d08*4+0x02000000,0xa981); +reg_write( DDR_REG_BASE +0x50d09*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50d0a*4+0x02000000,0xaac5); +reg_write( DDR_REG_BASE +0x50d0b*4+0x02000000,0xaa83); +reg_write( DDR_REG_BASE +0x50d0c*4+0x02000000,0xaaa2); +reg_write( DDR_REG_BASE +0x50d0d*4+0x02000000,0xaa60); +reg_write( DDR_REG_BASE +0x50d0e*4+0x02000000,0xc120); +reg_write( DDR_REG_BASE +0x50d0f*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d10*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50d11*4+0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x50d12*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d13*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d14*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50d15*4+0x02000000,0x1402); +reg_write( DDR_REG_BASE +0x50d16*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d17*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d18*4+0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50d19*4+0x02000000,0x1403); +reg_write( DDR_REG_BASE +0x50d1a*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d1b*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d1c*4+0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50d1d*4+0x02000000,0xc121); +reg_write( DDR_REG_BASE +0x50d1e*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d1f*4+0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50d20*4+0x02000000,0x1405); +reg_write( DDR_REG_BASE +0x50d21*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d22*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d23*4+0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50d24*4+0x02000000,0xa8a7); +reg_write( DDR_REG_BASE +0x50d25*4+0x02000000,0xa8a6); +reg_write( DDR_REG_BASE +0x50d26*4+0x02000000,0xc122); +reg_write( DDR_REG_BASE +0x50d27*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d28*4+0x02000000,0xa9c0); +reg_write( DDR_REG_BASE +0x50d29*4+0x02000000,0x1409); +reg_write( DDR_REG_BASE +0x50d2a*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d2b*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d2c*4+0x02000000,0xa9c0); +reg_write( DDR_REG_BASE +0x50d2d*4+0x02000000,0x140a); +reg_write( DDR_REG_BASE +0x50d2e*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d2f*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d30*4+0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50d31*4+0x02000000,0x140b); +reg_write( DDR_REG_BASE +0x50d32*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d33*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d34*4+0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50d35*4+0x02000000,0xc123); +reg_write( DDR_REG_BASE +0x50d36*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d37*4+0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50d38*4+0x02000000,0x140d); +reg_write( DDR_REG_BASE +0x50d39*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d3a*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d3b*4+0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50d3c*4+0x02000000,0x180f); +reg_write( DDR_REG_BASE +0x50d3d*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50d3e*4+0x02000000,0x269); +reg_write( DDR_REG_BASE +0x50d3f*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50d40*4+0x02000000,0x180e); +reg_write( DDR_REG_BASE +0x50d41*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50d42*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x50d43*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50d44*4+0x02000000,0x1400); +reg_write( DDR_REG_BASE +0x50d45*4+0x02000000,0x2311); +reg_write( DDR_REG_BASE +0x50d46*4+0x02000000,0x8300); +reg_write( DDR_REG_BASE +0x50d47*4+0x02000000,0x258); +reg_write( DDR_REG_BASE +0x50d48*4+0x02000000,0x21); +reg_write( DDR_REG_BASE +0x50d49*4+0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x50d4a*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50d4b*4+0x02000000,0xaee5); +reg_write( DDR_REG_BASE +0x50d4c*4+0x02000000,0xaee4); +reg_write( DDR_REG_BASE +0x50d4d*4+0x02000000,0xaee3); +reg_write( DDR_REG_BASE +0x50d4e*4+0x02000000,0xae62); +reg_write( DDR_REG_BASE +0x50d4f*4+0x02000000,0xae61); +reg_write( DDR_REG_BASE +0x50d50*4+0x02000000,0xae60); +reg_write( DDR_REG_BASE +0x50d51*4+0x02000000,0x260c); +reg_write( DDR_REG_BASE +0x50d52*4+0x02000000,0xbf80); +reg_write( DDR_REG_BASE +0x50d53*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50d54*4+0x02000000,0x2208); +reg_write( DDR_REG_BASE +0x50d55*4+0x02000000,0x73ad); +reg_write( DDR_REG_BASE +0x50d56*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x50d57*4+0x02000000,0xf47c); +reg_write( DDR_REG_BASE +0x50d58*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x50d59*4+0x02000000,0x1b00); +reg_write( DDR_REG_BASE +0x50d5a*4+0x02000000,0x3143); +reg_write( DDR_REG_BASE +0x50d5b*4+0x02000000,0xaee4); +reg_write( DDR_REG_BASE +0x50d5c*4+0x02000000,0xaee3); +reg_write( DDR_REG_BASE +0x50d5d*4+0x02000000,0xaee2); +reg_write( DDR_REG_BASE +0x50d5e*4+0x02000000,0xae81); +reg_write( DDR_REG_BASE +0x50d5f*4+0x02000000,0xae80); +reg_write( DDR_REG_BASE +0x50d60*4+0x02000000,0xde0b); +reg_write( DDR_REG_BASE +0x50d61*4+0x02000000,0x234a); +reg_write( DDR_REG_BASE +0x50d62*4+0x02000000,0x1280); +reg_write( DDR_REG_BASE +0x50d63*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x50d64*4+0x02000000,0x3180); +reg_write( DDR_REG_BASE +0x50d65*4+0x02000000,0xa9c4); +reg_write( DDR_REG_BASE +0x50d66*4+0x02000000,0x1903); +reg_write( DDR_REG_BASE +0x50d67*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50d68*4+0x02000000,0x1902); +reg_write( DDR_REG_BASE +0x50d69*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50d6a*4+0x02000000,0xa9a1); +reg_write( DDR_REG_BASE +0x50d6b*4+0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50d6c*4+0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x50d6d*4+0x02000000,0xaa2b); +reg_write( DDR_REG_BASE +0x50d6e*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50d6f*4+0x02000000,0xaaaa); +reg_write( DDR_REG_BASE +0x50d70*4+0x02000000,0xaa66); +reg_write( DDR_REG_BASE +0x50d71*4+0x02000000,0xaae3); +reg_write( DDR_REG_BASE +0x50d72*4+0x02000000,0xaa20); +reg_write( DDR_REG_BASE +0x50d73*4+0x02000000,0xc120); +reg_write( DDR_REG_BASE +0x50d74*4+0x02000000,0x603a); +reg_write( DDR_REG_BASE +0x50d75*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50d76*4+0x02000000,0xaa20); +reg_write( DDR_REG_BASE +0x50d77*4+0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x50d78*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d79*4+0x02000000,0x603a); +reg_write( DDR_REG_BASE +0x50d7a*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50d7b*4+0x02000000,0xaa20); +reg_write( DDR_REG_BASE +0x50d7c*4+0x02000000,0x1402); +reg_write( DDR_REG_BASE +0x50d7d*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d7e*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d7f*4+0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50d80*4+0x02000000,0x1403); +reg_write( DDR_REG_BASE +0x50d81*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d82*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d83*4+0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50d84*4+0x02000000,0xc121); +reg_write( DDR_REG_BASE +0x50d85*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d86*4+0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50d87*4+0x02000000,0x1405); +reg_write( DDR_REG_BASE +0x50d88*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d89*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d8a*4+0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50d8b*4+0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x50d8c*4+0x02000000,0xa8e7); +reg_write( DDR_REG_BASE +0x50d8d*4+0x02000000,0xa826); +reg_write( DDR_REG_BASE +0x50d8e*4+0x02000000,0xc122); +reg_write( DDR_REG_BASE +0x50d8f*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d90*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50d91*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50d92*4+0x02000000,0x1409); +reg_write( DDR_REG_BASE +0x50d93*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d94*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d95*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50d96*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50d97*4+0x02000000,0x140a); +reg_write( DDR_REG_BASE +0x50d98*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d99*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d9a*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50d9b*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50d9c*4+0x02000000,0x140b); +reg_write( DDR_REG_BASE +0x50d9d*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d9e*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d9f*4+0x02000000,0xa9c0); +reg_write( DDR_REG_BASE +0x50da0*4+0x02000000,0xc123); +reg_write( DDR_REG_BASE +0x50da1*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50da2*4+0x02000000,0xa9c0); +reg_write( DDR_REG_BASE +0x50da3*4+0x02000000,0x140d); +reg_write( DDR_REG_BASE +0x50da4*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50da5*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50da6*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50da7*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50da8*4+0x02000000,0x180f); +reg_write( DDR_REG_BASE +0x50da9*4+0x02000000,0x1c3); +reg_write( DDR_REG_BASE +0x50daa*4+0x02000000,0xf079); +reg_write( DDR_REG_BASE +0x50dab*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x50dac*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x50dad*4+0x02000000,0x1b00); +reg_write( DDR_REG_BASE +0x50dae*4+0x02000000,0x30c2); +reg_write( DDR_REG_BASE +0x50daf*4+0x02000000,0xae81); +reg_write( DDR_REG_BASE +0x50db0*4+0x02000000,0xae80); +reg_write( DDR_REG_BASE +0x50db1*4+0x02000000,0xa961); +reg_write( DDR_REG_BASE +0x50db2*4+0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50db3*4+0x02000000,0x718d); +reg_write( DDR_REG_BASE +0x50db4*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50db5*4+0x02000000,0xaa82); +reg_write( DDR_REG_BASE +0x50db6*4+0x02000000,0xaa20); +reg_write( DDR_REG_BASE +0x50db7*4+0x02000000,0xc120); +reg_write( DDR_REG_BASE +0x50db8*4+0x02000000,0x603a); +reg_write( DDR_REG_BASE +0x50db9*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50dba*4+0x02000000,0xaa20); +reg_write( DDR_REG_BASE +0x50dbb*4+0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x50dbc*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50dbd*4+0x02000000,0x603a); +reg_write( DDR_REG_BASE +0x50dbe*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50dbf*4+0x02000000,0xaa20); +reg_write( DDR_REG_BASE +0x50dc0*4+0x02000000,0x1402); +reg_write( DDR_REG_BASE +0x50dc1*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50dc2*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50dc3*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50dc4*4+0x02000000,0x1403); +reg_write( DDR_REG_BASE +0x50dc5*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50dc6*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50dc7*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50dc8*4+0x02000000,0xc121); +reg_write( DDR_REG_BASE +0x50dc9*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50dca*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50dcb*4+0x02000000,0x1405); +reg_write( DDR_REG_BASE +0x50dcc*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50dcd*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50dce*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50dcf*4+0x02000000,0xa887); +reg_write( DDR_REG_BASE +0x50dd0*4+0x02000000,0xa886); +reg_write( DDR_REG_BASE +0x50dd1*4+0x02000000,0xf0a2); +reg_write( DDR_REG_BASE +0x50dd2*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x50dd3*4+0x02000000,0x3200); +reg_write( DDR_REG_BASE +0x50dd4*4+0x02000000,0xca5); +reg_write( DDR_REG_BASE +0x50dd5*4+0x02000000,0x1331); +reg_write( DDR_REG_BASE +0x50dd6*4+0x02000000,0x234a); +reg_write( DDR_REG_BASE +0x50dd7*4+0x02000000,0x11c0); +reg_write( DDR_REG_BASE +0x50dd8*4+0x02000000,0x768d); +reg_write( DDR_REG_BASE +0x50dd9*4+0x02000000,0x1b00); +reg_write( DDR_REG_BASE +0x50dda*4+0x02000000,0x3302); +reg_write( DDR_REG_BASE +0x50ddb*4+0x02000000,0x1905); +reg_write( DDR_REG_BASE +0x50ddc*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50ddd*4+0x02000000,0x1904); +reg_write( DDR_REG_BASE +0x50dde*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50ddf*4+0x02000000,0xa983); +reg_write( DDR_REG_BASE +0x50de0*4+0x02000000,0xa9a2); +reg_write( DDR_REG_BASE +0x50de1*4+0x02000000,0xa961); +reg_write( DDR_REG_BASE +0x50de2*4+0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50de3*4+0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x50de4*4+0x02000000,0x1a08); +reg_write( DDR_REG_BASE +0x50de5*4+0x02000000,0x143); +reg_write( DDR_REG_BASE +0x50de6*4+0x02000000,0xaa27); +reg_write( DDR_REG_BASE +0x50de7*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50de8*4+0x02000000,0xaaa6); +reg_write( DDR_REG_BASE +0x50de9*4+0x02000000,0xaa63); +reg_write( DDR_REG_BASE +0x50dea*4+0x02000000,0xaae2); +reg_write( DDR_REG_BASE +0x50deb*4+0x02000000,0xaa21); +reg_write( DDR_REG_BASE +0x50dec*4+0x02000000,0xc120); +reg_write( DDR_REG_BASE +0x50ded*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50dee*4+0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50def*4+0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x50df0*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50df1*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50df2*4+0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50df3*4+0x02000000,0x1402); +reg_write( DDR_REG_BASE +0x50df4*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50df5*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50df6*4+0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50df7*4+0x02000000,0x1403); +reg_write( DDR_REG_BASE +0x50df8*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50df9*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50dfa*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50dfb*4+0x02000000,0xc121); +reg_write( DDR_REG_BASE +0x50dfc*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50dfd*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50dfe*4+0x02000000,0x1405); +reg_write( DDR_REG_BASE +0x50dff*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e00*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e01*4+0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50e02*4+0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x50e03*4+0x02000000,0x1807); +reg_write( DDR_REG_BASE +0x50e04*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x50e05*4+0x02000000,0xa826); +reg_write( DDR_REG_BASE +0x50e06*4+0x02000000,0xc122); +reg_write( DDR_REG_BASE +0x50e07*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e08*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e09*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50e0a*4+0x02000000,0x1409); +reg_write( DDR_REG_BASE +0x50e0b*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e0c*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e0d*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e0e*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50e0f*4+0x02000000,0x140a); +reg_write( DDR_REG_BASE +0x50e10*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e11*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e12*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e13*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50e14*4+0x02000000,0x140b); +reg_write( DDR_REG_BASE +0x50e15*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e16*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e17*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e18*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50e19*4+0x02000000,0xc123); +reg_write( DDR_REG_BASE +0x50e1a*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e1b*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e1c*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50e1d*4+0x02000000,0x140d); +reg_write( DDR_REG_BASE +0x50e1e*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e1f*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e20*4+0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50e21*4+0x02000000,0x180f); +reg_write( DDR_REG_BASE +0x50e22*4+0x02000000,0x283); +reg_write( DDR_REG_BASE +0x50e23*4+0x02000000,0x180e); +reg_write( DDR_REG_BASE +0x50e24*4+0x02000000,0x143); +reg_write( DDR_REG_BASE +0x50e25*4+0x02000000,0xf04e); +reg_write( DDR_REG_BASE +0x50e26*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x50e27*4+0x02000000,0xaee3); +reg_write( DDR_REG_BASE +0x50e28*4+0x02000000,0xaee2); +reg_write( DDR_REG_BASE +0x50e29*4+0x02000000,0xae81); +reg_write( DDR_REG_BASE +0x50e2a*4+0x02000000,0xae80); +reg_write( DDR_REG_BASE +0x50e2b*4+0x02000000,0x748d); +reg_write( DDR_REG_BASE +0x50e2c*4+0x02000000,0x1b00); +reg_write( DDR_REG_BASE +0x50e2d*4+0x02000000,0x3302); +reg_write( DDR_REG_BASE +0x50e2e*4+0x02000000,0x1903); +reg_write( DDR_REG_BASE +0x50e2f*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50e30*4+0x02000000,0x1902); +reg_write( DDR_REG_BASE +0x50e31*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50e32*4+0x02000000,0xa9a1); +reg_write( DDR_REG_BASE +0x50e33*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50e34*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50e35*4+0x02000000,0xaaa8); +reg_write( DDR_REG_BASE +0x50e36*4+0x02000000,0xaa67); +reg_write( DDR_REG_BASE +0x50e37*4+0x02000000,0xaae3); +reg_write( DDR_REG_BASE +0x50e38*4+0x02000000,0xaa22); +reg_write( DDR_REG_BASE +0x50e39*4+0x02000000,0xc120); +reg_write( DDR_REG_BASE +0x50e3a*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e3b*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50e3c*4+0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x50e3d*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e3e*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e3f*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50e40*4+0x02000000,0x1402); +reg_write( DDR_REG_BASE +0x50e41*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e42*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e43*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50e44*4+0x02000000,0x1403); +reg_write( DDR_REG_BASE +0x50e45*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e46*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e47*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50e48*4+0x02000000,0xc121); +reg_write( DDR_REG_BASE +0x50e49*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e4a*4+0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50e4b*4+0x02000000,0x1405); +reg_write( DDR_REG_BASE +0x50e4c*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e4d*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e4e*4+0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50e4f*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50e50*4+0x02000000,0xa827); +reg_write( DDR_REG_BASE +0x50e51*4+0x02000000,0xa8e6); +reg_write( DDR_REG_BASE +0x50e52*4+0x02000000,0xc122); +reg_write( DDR_REG_BASE +0x50e53*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e54*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e55*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50e56*4+0x02000000,0x1409); +reg_write( DDR_REG_BASE +0x50e57*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e58*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e59*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e5a*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50e5b*4+0x02000000,0x140a); +reg_write( DDR_REG_BASE +0x50e5c*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e5d*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e5e*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e5f*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50e60*4+0x02000000,0x140b); +reg_write( DDR_REG_BASE +0x50e61*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e62*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e63*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e64*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50e65*4+0x02000000,0xc123); +reg_write( DDR_REG_BASE +0x50e66*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e67*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e68*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50e69*4+0x02000000,0x140d); +reg_write( DDR_REG_BASE +0x50e6a*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e6b*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e6c*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e6d*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50e6e*4+0x02000000,0x180f); +reg_write( DDR_REG_BASE +0x50e6f*4+0x02000000,0x143); +reg_write( DDR_REG_BASE +0x50e70*4+0x02000000,0x180e); +reg_write( DDR_REG_BASE +0x50e71*4+0x02000000,0x183); +reg_write( DDR_REG_BASE +0x50e72*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x50e73*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50e74*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50e75*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50e76*4+0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x50e77*4+0x02000000,0x641); +reg_write( DDR_REG_BASE +0x50e78*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x50e79*4+0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x50e7a*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e7b*4+0x02000000,0x2132); +reg_write( DDR_REG_BASE +0x50e7c*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50e7d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50e7e*4+0x02000000,0x688); +reg_write( DDR_REG_BASE +0x50e7f*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50e80*4+0x02000000,0xb8c6); +reg_write( DDR_REG_BASE +0x50e81*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50e82*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x50e83*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50e84*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50e85*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50e86*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50e87*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50e88*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50e89*4+0x02000000,0x168); +reg_write( DDR_REG_BASE +0x50e8a*4+0x02000000,0x21c2); +reg_write( DDR_REG_BASE +0x50e8b*4+0x02000000,0x222); +reg_write( DDR_REG_BASE +0x50e8c*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50e8d*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50e8e*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50e8f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50e90*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x50e91*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50e92*4+0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x50e93*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50e94*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50e95*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50e96*4+0x02000000,0x710d); +reg_write( DDR_REG_BASE +0x50e97*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50e98*4+0x02000000,0x1c6); +reg_write( DDR_REG_BASE +0x50e99*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x50e9a*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x50e9b*4+0x02000000,0xe1c6); +reg_write( DDR_REG_BASE +0x50e9c*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x50e9d*4+0x02000000,0xbdc9); +reg_write( DDR_REG_BASE +0x50e9e*4+0x02000000,0x254f); +reg_write( DDR_REG_BASE +0x50e9f*4+0x02000000,0x12ce); +reg_write( DDR_REG_BASE +0x50ea0*4+0x02000000,0xb46); +reg_write( DDR_REG_BASE +0x50ea1*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50ea2*4+0x02000000,0xb7c0); +reg_write( DDR_REG_BASE +0x50ea3*4+0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x50ea4*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x50ea5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50ea6*4+0x02000000,0xc00); +reg_write( DDR_REG_BASE +0x50ea7*4+0x02000000,0xb700); +reg_write( DDR_REG_BASE +0x50ea8*4+0x02000000,0xb36); +reg_write( DDR_REG_BASE +0x50ea9*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50eaa*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x50eab*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x50eac*4+0x02000000,0xb2e); +reg_write( DDR_REG_BASE +0x50ead*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50eae*4+0x02000000,0xb7c0); +reg_write( DDR_REG_BASE +0x50eaf*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50eb0*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x50eb1*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50eb2*4+0x02000000,0x1c8); +reg_write( DDR_REG_BASE +0x50eb3*4+0x02000000,0xb7a0); +reg_write( DDR_REG_BASE +0x50eb4*4+0x02000000,0xb8c9); +reg_write( DDR_REG_BASE +0x50eb5*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50eb6*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50eb7*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50eb8*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50eb9*4+0x02000000,0xc1a7); +reg_write( DDR_REG_BASE +0x50eba*4+0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x50ebb*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50ebc*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50ebd*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50ebe*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50ebf*4+0x02000000,0xc144); +reg_write( DDR_REG_BASE +0x50ec0*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50ec1*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x50ec2*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50ec3*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50ec4*4+0x02000000,0x7d8); +reg_write( DDR_REG_BASE +0x50ec5*4+0x02000000,0x8020); +reg_write( DDR_REG_BASE +0x50ec6*4+0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x50ec7*4+0x02000000,0xa92); +reg_write( DDR_REG_BASE +0x50ec8*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50ec9*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50eca*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50ecb*4+0x02000000,0xc6a); +reg_write( DDR_REG_BASE +0x50ecc*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50ecd*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x50ece*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x50ecf*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x50ed0*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x50ed1*4+0x02000000,0x37c0); +reg_write( DDR_REG_BASE +0x50ed2*4+0x02000000,0xe805); +reg_write( DDR_REG_BASE +0x50ed3*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x50ed4*4+0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x50ed5*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x50ed6*4+0x02000000,0x7dbb); +reg_write( DDR_REG_BASE +0x50ed7*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x50ed8*4+0x02000000,0x2553); +reg_write( DDR_REG_BASE +0x50ed9*4+0x02000000,0x1040); +reg_write( DDR_REG_BASE +0x50eda*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x50edb*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x50edc*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50edd*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50ede*4+0x02000000,0xda09); +reg_write( DDR_REG_BASE +0x50edf*4+0x02000000,0xdbff); +reg_write( DDR_REG_BASE +0x50ee0*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x50ee1*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x50ee2*4+0x02000000,0xd12); +reg_write( DDR_REG_BASE +0x50ee3*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50ee4*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x50ee5*4+0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x50ee6*4+0x02000000,0x110d); +reg_write( DDR_REG_BASE +0x50ee7*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50ee8*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x50ee9*4+0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x50eea*4+0x02000000,0x250f); +reg_write( DDR_REG_BASE +0x50eeb*4+0x02000000,0x16c0); +reg_write( DDR_REG_BASE +0x50eec*4+0x02000000,0x7d0f); +reg_write( DDR_REG_BASE +0x50eed*4+0x02000000,0xd840); +reg_write( DDR_REG_BASE +0x50eee*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50eef*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50ef0*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x50ef1*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50ef2*4+0x02000000,0xcf2); +reg_write( DDR_REG_BASE +0x50ef3*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50ef4*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x50ef5*4+0x02000000,0x35c1); +reg_write( DDR_REG_BASE +0x50ef6*4+0x02000000,0xd84b); +reg_write( DDR_REG_BASE +0x50ef7*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50ef8*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50ef9*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x50efa*4+0x02000000,0xda17); +reg_write( DDR_REG_BASE +0x50efb*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x50efc*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x50efd*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50efe*4+0x02000000,0xcda); +reg_write( DDR_REG_BASE +0x50eff*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50f00*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x50f01*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50f02*4+0x02000000,0xc92); +reg_write( DDR_REG_BASE +0x50f03*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50f04*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x50f05*4+0x02000000,0xc52); +reg_write( DDR_REG_BASE +0x50f06*4+0x02000000,0x1c0); +reg_write( DDR_REG_BASE +0x50f07*4+0x02000000,0xa7a); +reg_write( DDR_REG_BASE +0x50f08*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50f09*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x50f0a*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x50f0b*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50f0c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50f0d*4+0x02000000,0x9c40); +reg_write( DDR_REG_BASE +0x50f0e*4+0x02000000,0xac2); +reg_write( DDR_REG_BASE +0x50f0f*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50f10*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x50f11*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50f12*4+0x02000000,0xbda); +reg_write( DDR_REG_BASE +0x50f13*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50f14*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x50f15*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x50f16*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50f17*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x50f18*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50f19*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x50f1a*4+0x02000000,0xda0d); +reg_write( DDR_REG_BASE +0x50f1b*4+0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x50f1c*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x50f1d*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50f1e*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x50f1f*4+0x02000000,0xc9a); +reg_write( DDR_REG_BASE +0x50f20*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50f21*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x50f22*4+0x02000000,0x2756); +reg_write( DDR_REG_BASE +0x50f23*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x50f24*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50f25*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50f26*4+0x02000000,0xd988); +reg_write( DDR_REG_BASE +0x50f27*4+0x02000000,0xda0d); +reg_write( DDR_REG_BASE +0x50f28*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x50f29*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x50f2a*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50f2b*4+0x02000000,0xc82); +reg_write( DDR_REG_BASE +0x50f2c*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50f2d*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x50f2e*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50f2f*4+0x02000000,0xc3a); +reg_write( DDR_REG_BASE +0x50f30*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50f31*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x50f32*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50f33*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50f34*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x50f35*4+0x02000000,0x8ea0); +reg_write( DDR_REG_BASE +0x50f36*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x50f37*4+0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x50f38*4+0x02000000,0xb62); +reg_write( DDR_REG_BASE +0x50f39*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50f3a*4+0x02000000,0x41e1); +reg_write( DDR_REG_BASE +0x50f3b*4+0x02000000,0xe809); +reg_write( DDR_REG_BASE +0x50f3c*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x50f3d*4+0x02000000,0x9c6); +reg_write( DDR_REG_BASE +0x50f3e*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x50f3f*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50f40*4+0x02000000,0xc104); +reg_write( DDR_REG_BASE +0x50f41*4+0x02000000,0x79b4); +reg_write( DDR_REG_BASE +0x50f42*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x50f43*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x50f44*4+0x02000000,0x8e41); +reg_write( DDR_REG_BASE +0x50f45*4+0x02000000,0xae7); +reg_write( DDR_REG_BASE +0x50f46*4+0x02000000,0x8365); +reg_write( DDR_REG_BASE +0x50f47*4+0x02000000,0x7faf); +reg_write( DDR_REG_BASE +0x50f48*4+0x02000000,0x8ee0); +reg_write( DDR_REG_BASE +0x50f49*4+0x02000000,0xf03c); +reg_write( DDR_REG_BASE +0x50f4a*4+0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x50f4b*4+0x02000000,0xb3e); +reg_write( DDR_REG_BASE +0x50f4c*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50f4d*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x50f4e*4+0x02000000,0xe834); +reg_write( DDR_REG_BASE +0x50f4f*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50f50*4+0x02000000,0x99e); +reg_write( DDR_REG_BASE +0x50f51*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x50f52*4+0x02000000,0xd910); +reg_write( DDR_REG_BASE +0x50f53*4+0x02000000,0xc504); +reg_write( DDR_REG_BASE +0x50f54*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x50f55*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50f56*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x50f57*4+0x02000000,0x7df4); +reg_write( DDR_REG_BASE +0x50f58*4+0x02000000,0x9520); +reg_write( DDR_REG_BASE +0x50f59*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50f5a*4+0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x50f5b*4+0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x50f5c*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50f5d*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50f5e*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50f5f*4+0x02000000,0xa96); +reg_write( DDR_REG_BASE +0x50f60*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x50f61*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x50f62*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50f63*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50f64*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x50f65*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50f66*4+0x02000000,0x6); +reg_write( DDR_REG_BASE +0x50f67*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x50f68*4+0x02000000,0x81c3); +reg_write( DDR_REG_BASE +0x50f69*4+0x02000000,0xf706); +reg_write( DDR_REG_BASE +0x50f6a*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x50f6b*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50f6c*4+0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x50f6d*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x50f6e*4+0x02000000,0x9500); +reg_write( DDR_REG_BASE +0x50f6f*4+0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x50f70*4+0x02000000,0x95); +reg_write( DDR_REG_BASE +0x50f71*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50f72*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50f73*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x50f74*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x50f75*4+0x02000000,0x2e05); +reg_write( DDR_REG_BASE +0x50f76*4+0x02000000,0x7000); +reg_write( DDR_REG_BASE +0x50f77*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50f78*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50f79*4+0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x50f7a*4+0x02000000,0x7b10); +reg_write( DDR_REG_BASE +0x50f7b*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x50f7c*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50f7d*4+0x02000000,0xe1); +reg_write( DDR_REG_BASE +0x50f7e*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x50f7f*4+0x02000000,0xfc2); +reg_write( DDR_REG_BASE +0x50f80*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50f81*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x50f82*4+0x02000000,0x8e41); +reg_write( DDR_REG_BASE +0x50f83*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x50f84*4+0x02000000,0xa8d); +reg_write( DDR_REG_BASE +0x50f85*4+0x02000000,0x83e5); +reg_write( DDR_REG_BASE +0x50f86*4+0x02000000,0x7def); +reg_write( DDR_REG_BASE +0x50f87*4+0x02000000,0x8ea0); +reg_write( DDR_REG_BASE +0x50f88*4+0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x50f89*4+0x02000000,0xac2); +reg_write( DDR_REG_BASE +0x50f8a*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50f8b*4+0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x50f8c*4+0x02000000,0xe88a); +reg_write( DDR_REG_BASE +0x50f8d*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x50f8e*4+0x02000000,0xd0b); +reg_write( DDR_REG_BASE +0x50f8f*4+0x02000000,0x103f); +reg_write( DDR_REG_BASE +0x50f90*4+0x02000000,0x78b4); +reg_write( DDR_REG_BASE +0x50f91*4+0x02000000,0x9021); +reg_write( DDR_REG_BASE +0x50f92*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x50f93*4+0x02000000,0x10fe); +reg_write( DDR_REG_BASE +0x50f94*4+0x02000000,0x8101); +reg_write( DDR_REG_BASE +0x50f95*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x50f96*4+0x02000000,0x8e41); +reg_write( DDR_REG_BASE +0x50f97*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x50f98*4+0x02000000,0xae3); +reg_write( DDR_REG_BASE +0x50f99*4+0x02000000,0x8365); +reg_write( DDR_REG_BASE +0x50f9a*4+0x02000000,0x79af); +reg_write( DDR_REG_BASE +0x50f9b*4+0x02000000,0x8e60); +reg_write( DDR_REG_BASE +0x50f9c*4+0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x50f9d*4+0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x50f9e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50f9f*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50fa0*4+0x02000000,0x15c); +reg_write( DDR_REG_BASE +0x50fa1*4+0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x50fa2*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x50fa3*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50fa4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50fa5*4+0x02000000,0x20c0); +reg_write( DDR_REG_BASE +0x50fa6*4+0x02000000,0xa2); +reg_write( DDR_REG_BASE +0x50fa7*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x50fa8*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x50fa9*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50faa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50fab*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x50fac*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x50fad*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x50fae*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x50faf*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x50fb0*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x50fb1*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x50fb2*4+0x02000000,0xad7); +reg_write( DDR_REG_BASE +0x50fb3*4+0x02000000,0x80e5); +reg_write( DDR_REG_BASE +0x50fb4*4+0x02000000,0x7077); +reg_write( DDR_REG_BASE +0x50fb5*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50fb6*4+0x02000000,0xa92); +reg_write( DDR_REG_BASE +0x50fb7*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50fb8*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x50fb9*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x50fba*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50fbb*4+0x02000000,0xda0a); +reg_write( DDR_REG_BASE +0x50fbc*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x50fbd*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50fbe*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x50fbf*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x50fc0*4+0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x50fc1*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x50fc2*4+0x02000000,0xb52); +reg_write( DDR_REG_BASE +0x50fc3*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50fc4*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x50fc5*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50fc6*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50fc7*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x50fc8*4+0x02000000,0x766c); +reg_write( DDR_REG_BASE +0x50fc9*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x50fca*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x50fcb*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50fcc*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x50fcd*4+0x02000000,0xb3e); +reg_write( DDR_REG_BASE +0x50fce*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50fcf*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x50fd0*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x50fd1*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50fd2*4+0x02000000,0xda0e); +reg_write( DDR_REG_BASE +0x50fd3*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x50fd4*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50fd5*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x50fd6*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x50fd7*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x50fd8*4+0x02000000,0xb26); +reg_write( DDR_REG_BASE +0x50fd9*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50fda*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x50fdb*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50fdc*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x50fdd*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x50fde*4+0x02000000,0x766c); +reg_write( DDR_REG_BASE +0x50fdf*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x50fe0*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50fe1*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x50fe2*4+0x02000000,0xb12); +reg_write( DDR_REG_BASE +0x50fe3*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50fe4*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x50fe5*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50fe6*4+0x02000000,0xaca); +reg_write( DDR_REG_BASE +0x50fe7*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50fe8*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x50fe9*4+0x02000000,0xa8a); +reg_write( DDR_REG_BASE +0x50fea*4+0x02000000,0x1c0); +reg_write( DDR_REG_BASE +0x50feb*4+0x02000000,0xc0a7); +reg_write( DDR_REG_BASE +0x50fec*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50fed*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50fee*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50fef*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50ff0*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x50ff1*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x50ff2*4+0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x50ff3*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x50ff4*4+0x02000000,0xd06); +reg_write( DDR_REG_BASE +0x50ff5*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50ff6*4+0x02000000,0x4160); +reg_write( DDR_REG_BASE +0x50ff7*4+0x02000000,0xe8b8); +reg_write( DDR_REG_BASE +0x50ff8*4+0x02000000,0x246f); +reg_write( DDR_REG_BASE +0x50ff9*4+0x02000000,0x1dc3); +reg_write( DDR_REG_BASE +0x50ffa*4+0x02000000,0x8c20); +reg_write( DDR_REG_BASE +0x50ffb*4+0x02000000,0x969); +reg_write( DDR_REG_BASE +0x50ffc*4+0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x50ffd*4+0x02000000,0x142f); +reg_write( DDR_REG_BASE +0x50ffe*4+0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x50fff*4+0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x51000*4+0x02000000,0x1c81); +reg_write( DDR_REG_BASE +0x51001*4+0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x51002*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x51003*4+0x02000000,0x640); +reg_write( DDR_REG_BASE +0x51004*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51005*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x51006*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51007*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51008*4+0x02000000,0x687); +reg_write( DDR_REG_BASE +0x51009*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5100a*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5100b*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5100c*4+0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x5100d*4+0x02000000,0xb9c2); +reg_write( DDR_REG_BASE +0x5100e*4+0x02000000,0xd8f0); +reg_write( DDR_REG_BASE +0x5100f*4+0x02000000,0x2805); +reg_write( DDR_REG_BASE +0x51010*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x51011*4+0x02000000,0xeb05); +reg_write( DDR_REG_BASE +0x51012*4+0x02000000,0x143c); +reg_write( DDR_REG_BASE +0x51013*4+0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x51014*4+0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x51015*4+0x02000000,0x8c09); +reg_write( DDR_REG_BASE +0x51016*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51017*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51018*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51019*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5101a*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x5101b*4+0x02000000,0x7b2f); +reg_write( DDR_REG_BASE +0x5101c*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x5101d*4+0x02000000,0x61); +reg_write( DDR_REG_BASE +0x5101e*4+0x02000000,0xb1b); +reg_write( DDR_REG_BASE +0x5101f*4+0x02000000,0x24); +reg_write( DDR_REG_BASE +0x51020*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51021*4+0x02000000,0x404); +reg_write( DDR_REG_BASE +0x51022*4+0x02000000,0x2b05); +reg_write( DDR_REG_BASE +0x51023*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51024*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x51025*4+0x02000000,0xa0f); +reg_write( DDR_REG_BASE +0x51026*4+0x02000000,0x782c); +reg_write( DDR_REG_BASE +0x51027*4+0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x51028*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x51029*4+0x02000000,0x2805); +reg_write( DDR_REG_BASE +0x5102a*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x5102b*4+0x02000000,0xf96); +reg_write( DDR_REG_BASE +0x5102c*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5102d*4+0x02000000,0x7830); +reg_write( DDR_REG_BASE +0x5102e*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x5102f*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51030*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51031*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x51032*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51033*4+0x02000000,0x22); +reg_write( DDR_REG_BASE +0x51034*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51035*4+0x02000000,0x7de0); +reg_write( DDR_REG_BASE +0x51036*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51037*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x51038*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51039*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x5103a*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5103b*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5103c*4+0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x5103d*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x5103e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5103f*4+0x02000000,0x7ca); +reg_write( DDR_REG_BASE +0x51040*4+0x02000000,0x8b00); +reg_write( DDR_REG_BASE +0x51041*4+0x02000000,0xdea); +reg_write( DDR_REG_BASE +0x51042*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51043*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51044*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51045*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51046*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51047*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51048*4+0x02000000,0x8b82); +reg_write( DDR_REG_BASE +0x51049*4+0x02000000,0x8b41); +reg_write( DDR_REG_BASE +0x5104a*4+0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x5104b*4+0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x5104c*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5104d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5104e*4+0x02000000,0x776c); +reg_write( DDR_REG_BASE +0x5104f*4+0x02000000,0xf01c); +reg_write( DDR_REG_BASE +0x51050*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x51051*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51052*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51053*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x51054*4+0x02000000,0x2104); +reg_write( DDR_REG_BASE +0x51055*4+0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x51056*4+0x02000000,0x37fe); +reg_write( DDR_REG_BASE +0x51057*4+0x02000000,0xf000); +reg_write( DDR_REG_BASE +0x51058*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x51059*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x5105a*4+0x02000000,0x79a5); +reg_write( DDR_REG_BASE +0x5105b*4+0x02000000,0x79c5); +reg_write( DDR_REG_BASE +0x5105c*4+0x02000000,0x6ac1); +reg_write( DDR_REG_BASE +0x5105d*4+0x02000000,0x229a); +reg_write( DDR_REG_BASE +0x5105e*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5105f*4+0x02000000,0x2284); +reg_write( DDR_REG_BASE +0x51060*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51061*4+0x02000000,0x7a25); +reg_write( DDR_REG_BASE +0x51062*4+0x02000000,0x795b); +reg_write( DDR_REG_BASE +0x51063*4+0x02000000,0xb991); +reg_write( DDR_REG_BASE +0x51064*4+0x02000000,0xb99c); +reg_write( DDR_REG_BASE +0x51065*4+0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x51066*4+0x02000000,0x9120); +reg_write( DDR_REG_BASE +0x51067*4+0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x51068*4+0x02000000,0x2108); +reg_write( DDR_REG_BASE +0x51069*4+0x02000000,0xc3); +reg_write( DDR_REG_BASE +0x5106a*4+0x02000000,0xccd); +reg_write( DDR_REG_BASE +0x5106b*4+0x02000000,0x9085); +reg_write( DDR_REG_BASE +0x5106c*4+0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x5106d*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x5106e*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x5106f*4+0x02000000,0x901); +reg_write( DDR_REG_BASE +0x51070*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x51071*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x51072*4+0x02000000,0x796f); +reg_write( DDR_REG_BASE +0x51073*4+0x02000000,0x2179); +reg_write( DDR_REG_BASE +0x51074*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51075*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51076*4+0x02000000,0x7204); +reg_write( DDR_REG_BASE +0x51077*4+0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x51078*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51079*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5107a*4+0x02000000,0x7d8); +reg_write( DDR_REG_BASE +0x5107b*4+0x02000000,0x7bd); +reg_write( DDR_REG_BASE +0x5107c*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5107d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5107e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5107f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51080*4+0x02000000,0x7d8); +reg_write( DDR_REG_BASE +0x51081*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x51082*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51083*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51084*4+0x02000000,0x8020); +reg_write( DDR_REG_BASE +0x51085*4+0x02000000,0x8a00); +reg_write( DDR_REG_BASE +0x51086*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x51087*4+0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x51088*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51089*4+0x02000000,0x8a21); +reg_write( DDR_REG_BASE +0x5108a*4+0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x5108b*4+0x02000000,0x641); +reg_write( DDR_REG_BASE +0x5108c*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x5108d*4+0x02000000,0x8842); +reg_write( DDR_REG_BASE +0x5108e*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5108f*4+0x02000000,0x75); +reg_write( DDR_REG_BASE +0x51090*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51091*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51092*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51093*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51094*4+0x02000000,0x7cb); +reg_write( DDR_REG_BASE +0x51095*4+0x02000000,0x8881); +reg_write( DDR_REG_BASE +0x51096*4+0x02000000,0x8860); +reg_write( DDR_REG_BASE +0x51097*4+0x02000000,0xf022); +reg_write( DDR_REG_BASE +0x51098*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x51099*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5109a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5109b*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x5109c*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x5109d*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x5109e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5109f*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x510a0*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x510a1*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x510a2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x510a3*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x510a4*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x510a5*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x510a6*4+0x02000000,0x6ffd); +reg_write( DDR_REG_BASE +0x510a7*4+0x02000000,0xe000); +reg_write( DDR_REG_BASE +0x510a8*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x510a9*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x510aa*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x510ab*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x510ac*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x510ad*4+0x02000000,0x9220); +reg_write( DDR_REG_BASE +0x510ae*4+0x02000000,0x4928); +reg_write( DDR_REG_BASE +0x510af*4+0x02000000,0x208b); +reg_write( DDR_REG_BASE +0x510b0*4+0x02000000,0x880f); +reg_write( DDR_REG_BASE +0x510b1*4+0x02000000,0xf206); +reg_write( DDR_REG_BASE +0x510b2*4+0x02000000,0x2142); +reg_write( DDR_REG_BASE +0x510b3*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x510b4*4+0x02000000,0x2080); +reg_write( DDR_REG_BASE +0x510b5*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x510b6*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x510b7*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x510b8*4+0x02000000,0xcc1); +reg_write( DDR_REG_BASE +0x510b9*4+0x02000000,0x90c5); +reg_write( DDR_REG_BASE +0x510ba*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x510bb*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x510bc*4+0x02000000,0xc0e4); +reg_write( DDR_REG_BASE +0x510bd*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x510be*4+0x02000000,0x259a); +reg_write( DDR_REG_BASE +0x510bf*4+0x02000000,0x1008); +reg_write( DDR_REG_BASE +0x510c0*4+0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x510c1*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x510c2*4+0x02000000,0x48); +reg_write( DDR_REG_BASE +0x510c3*4+0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x510c4*4+0x02000000,0x130e); +reg_write( DDR_REG_BASE +0x510c5*4+0x02000000,0xb620); +reg_write( DDR_REG_BASE +0x510c6*4+0x02000000,0x6c22); +reg_write( DDR_REG_BASE +0x510c7*4+0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x510c8*4+0x02000000,0x104c); +reg_write( DDR_REG_BASE +0x510c9*4+0x02000000,0x7224); +reg_write( DDR_REG_BASE +0x510ca*4+0x02000000,0xb440); +reg_write( DDR_REG_BASE +0x510cb*4+0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x510cc*4+0x02000000,0x1042); +reg_write( DDR_REG_BASE +0x510cd*4+0x02000000,0xb260); +reg_write( DDR_REG_BASE +0x510ce*4+0x02000000,0x6962); +reg_write( DDR_REG_BASE +0x510cf*4+0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x510d0*4+0x02000000,0x7d65); +reg_write( DDR_REG_BASE +0x510d1*4+0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x510d2*4+0x02000000,0x3f1); +reg_write( DDR_REG_BASE +0x510d3*4+0x02000000,0xb520); +reg_write( DDR_REG_BASE +0x510d4*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x510d5*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x510d6*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x510d7*4+0x02000000,0x137c); +reg_write( DDR_REG_BASE +0x510d8*4+0x02000000,0x101); +reg_write( DDR_REG_BASE +0x510d9*4+0x02000000,0x210f); +reg_write( DDR_REG_BASE +0x510da*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x510db*4+0x02000000,0x1b7c); +reg_write( DDR_REG_BASE +0x510dc*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x510dd*4+0x02000000,0xc4c4); +reg_write( DDR_REG_BASE +0x510de*4+0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x510df*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x510e0*4+0x02000000,0xc2); +reg_write( DDR_REG_BASE +0x510e1*4+0x02000000,0x1c02); +reg_write( DDR_REG_BASE +0x510e2*4+0x02000000,0x1014); +reg_write( DDR_REG_BASE +0x510e3*4+0x02000000,0xb420); +reg_write( DDR_REG_BASE +0x510e4*4+0x02000000,0xb441); +reg_write( DDR_REG_BASE +0x510e5*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x510e6*4+0x02000000,0xb462); +reg_write( DDR_REG_BASE +0x510e7*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x510e8*4+0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x510e9*4+0x02000000,0x4320); +reg_write( DDR_REG_BASE +0x510ea*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x510eb*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x510ec*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x510ed*4+0x02000000,0x7d0); +reg_write( DDR_REG_BASE +0x510ee*4+0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x510ef*4+0x02000000,0xf06); +reg_write( DDR_REG_BASE +0x510f0*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x510f1*4+0x02000000,0x203c); +reg_write( DDR_REG_BASE +0x510f2*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x510f3*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x510f4*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x510f5*4+0x02000000,0xf427); +reg_write( DDR_REG_BASE +0x510f6*4+0x02000000,0xde25); +reg_write( DDR_REG_BASE +0x510f7*4+0x02000000,0xbe9f); +reg_write( DDR_REG_BASE +0x510f8*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x510f9*4+0x02000000,0xf01f); +reg_write( DDR_REG_BASE +0x510fa*4+0x02000000,0xec04); +reg_write( DDR_REG_BASE +0x510fb*4+0x02000000,0x1633); +reg_write( DDR_REG_BASE +0x510fc*4+0x02000000,0x1082); +reg_write( DDR_REG_BASE +0x510fd*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x510fe*4+0x02000000,0x8e40); +reg_write( DDR_REG_BASE +0x510ff*4+0x02000000,0xa31); +reg_write( DDR_REG_BASE +0x51100*4+0x02000000,0x6e); +reg_write( DDR_REG_BASE +0x51101*4+0x02000000,0x2114); +reg_write( DDR_REG_BASE +0x51102*4+0x02000000,0x302); +reg_write( DDR_REG_BASE +0x51103*4+0x02000000,0x2232); +reg_write( DDR_REG_BASE +0x51104*4+0x02000000,0xf8b); +reg_write( DDR_REG_BASE +0x51105*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51106*4+0x02000000,0x784); +reg_write( DDR_REG_BASE +0x51107*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51108*4+0x02000000,0xa1d); +reg_write( DDR_REG_BASE +0x51109*4+0x02000000,0x2c5); +reg_write( DDR_REG_BASE +0x5110a*4+0x02000000,0x245a); +reg_write( DDR_REG_BASE +0x5110b*4+0x02000000,0x140d); +reg_write( DDR_REG_BASE +0x5110c*4+0x02000000,0x7d36); +reg_write( DDR_REG_BASE +0x5110d*4+0x02000000,0x655d); +reg_write( DDR_REG_BASE +0x5110e*4+0x02000000,0x2532); +reg_write( DDR_REG_BASE +0x5110f*4+0x02000000,0x1f8d); +reg_write( DDR_REG_BASE +0x51110*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51111*4+0x02000000,0x7a8); +reg_write( DDR_REG_BASE +0x51112*4+0x02000000,0xded); +reg_write( DDR_REG_BASE +0x51113*4+0x02000000,0x90e1); +reg_write( DDR_REG_BASE +0x51114*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x51115*4+0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x51116*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x51117*4+0x02000000,0xcc9); +reg_write( DDR_REG_BASE +0x51118*4+0x02000000,0x9094); +reg_write( DDR_REG_BASE +0x51119*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5111a*4+0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x5111b*4+0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x5111c*4+0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x5111d*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5111e*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5111f*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51120*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51121*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51122*4+0x02000000,0xe064); +reg_write( DDR_REG_BASE +0x51123*4+0x02000000,0x2145); +reg_write( DDR_REG_BASE +0x51124*4+0x02000000,0x7c1); +reg_write( DDR_REG_BASE +0x51125*4+0x02000000,0x779); +reg_write( DDR_REG_BASE +0x51126*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x51127*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51128*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51129*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5112a*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5112b*4+0x02000000,0xc1a3); +reg_write( DDR_REG_BASE +0x5112c*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5112d*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x5112e*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x5112f*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51130*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x51131*4+0x02000000,0xafd); +reg_write( DDR_REG_BASE +0x51132*4+0x02000000,0x8674); +reg_write( DDR_REG_BASE +0x51133*4+0x02000000,0x2014); +reg_write( DDR_REG_BASE +0x51134*4+0x02000000,0x81); +reg_write( DDR_REG_BASE +0x51135*4+0x02000000,0xdb32); +reg_write( DDR_REG_BASE +0x51136*4+0x02000000,0xbb9f); +reg_write( DDR_REG_BASE +0x51137*4+0x02000000,0x8b20); +reg_write( DDR_REG_BASE +0x51138*4+0x02000000,0xa821); +reg_write( DDR_REG_BASE +0x51139*4+0x02000000,0x6b21); +reg_write( DDR_REG_BASE +0x5113a*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x5113b*4+0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x5113c*4+0x02000000,0xa822); +reg_write( DDR_REG_BASE +0x5113d*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x5113e*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x5113f*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51140*4+0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x51141*4+0x02000000,0xa823); +reg_write( DDR_REG_BASE +0x51142*4+0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x51143*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x51144*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x51145*4+0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x51146*4+0x02000000,0xa824); +reg_write( DDR_REG_BASE +0x51147*4+0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x51148*4+0x02000000,0x6941); +reg_write( DDR_REG_BASE +0x51149*4+0x02000000,0x8a20); +reg_write( DDR_REG_BASE +0x5114a*4+0x02000000,0x2240); +reg_write( DDR_REG_BASE +0x5114b*4+0x02000000,0x5f); +reg_write( DDR_REG_BASE +0x5114c*4+0x02000000,0x2740); +reg_write( DDR_REG_BASE +0x5114d*4+0x02000000,0x304c); +reg_write( DDR_REG_BASE +0x5114e*4+0x02000000,0xa82b); +reg_write( DDR_REG_BASE +0x5114f*4+0x02000000,0x1700); +reg_write( DDR_REG_BASE +0x51150*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x51151*4+0x02000000,0x6ca1); +reg_write( DDR_REG_BASE +0x51152*4+0x02000000,0x6dc1); +reg_write( DDR_REG_BASE +0x51153*4+0x02000000,0xa82c); +reg_write( DDR_REG_BASE +0x51154*4+0x02000000,0x8c20); +reg_write( DDR_REG_BASE +0x51155*4+0x02000000,0x6ee1); +reg_write( DDR_REG_BASE +0x51156*4+0x02000000,0x4358); +reg_write( DDR_REG_BASE +0x51157*4+0x02000000,0xa82d); +reg_write( DDR_REG_BASE +0x51158*4+0x02000000,0x8d20); +reg_write( DDR_REG_BASE +0x51159*4+0x02000000,0xa82e); +reg_write( DDR_REG_BASE +0x5115a*4+0x02000000,0x8e20); +reg_write( DDR_REG_BASE +0x5115b*4+0x02000000,0xa830); +reg_write( DDR_REG_BASE +0x5115c*4+0x02000000,0x8f20); +reg_write( DDR_REG_BASE +0x5115d*4+0x02000000,0xa831); +reg_write( DDR_REG_BASE +0x5115e*4+0x02000000,0x8f21); +reg_write( DDR_REG_BASE +0x5115f*4+0x02000000,0xa836); +reg_write( DDR_REG_BASE +0x51160*4+0x02000000,0x8f22); +reg_write( DDR_REG_BASE +0x51161*4+0x02000000,0xa838); +reg_write( DDR_REG_BASE +0x51162*4+0x02000000,0x13e6); +reg_write( DDR_REG_BASE +0x51163*4+0x02000000,0x8081); +reg_write( DDR_REG_BASE +0x51164*4+0x02000000,0xe930); +reg_write( DDR_REG_BASE +0x51165*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x51166*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x51167*4+0x02000000,0xf02a); +reg_write( DDR_REG_BASE +0x51168*4+0x02000000,0x265a); +reg_write( DDR_REG_BASE +0x51169*4+0x02000000,0x3c82); +reg_write( DDR_REG_BASE +0x5116a*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x5116b*4+0x02000000,0x1641); +reg_write( DDR_REG_BASE +0x5116c*4+0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x5116d*4+0x02000000,0x621a); +reg_write( DDR_REG_BASE +0x5116e*4+0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x5116f*4+0x02000000,0x8b40); +reg_write( DDR_REG_BASE +0x51170*4+0x02000000,0xa941); +reg_write( DDR_REG_BASE +0x51171*4+0x02000000,0xc200); +reg_write( DDR_REG_BASE +0x51172*4+0x02000000,0x8a40); +reg_write( DDR_REG_BASE +0x51173*4+0x02000000,0xa942); +reg_write( DDR_REG_BASE +0x51174*4+0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x51175*4+0x02000000,0x8a40); +reg_write( DDR_REG_BASE +0x51176*4+0x02000000,0xa943); +reg_write( DDR_REG_BASE +0x51177*4+0x02000000,0xc202); +reg_write( DDR_REG_BASE +0x51178*4+0x02000000,0x8a40); +reg_write( DDR_REG_BASE +0x51179*4+0x02000000,0xa944); +reg_write( DDR_REG_BASE +0x5117a*4+0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x5117b*4+0x02000000,0x3082); +reg_write( DDR_REG_BASE +0x5117c*4+0x02000000,0xa94b); +reg_write( DDR_REG_BASE +0x5117d*4+0x02000000,0x1700); +reg_write( DDR_REG_BASE +0x5117e*4+0x02000000,0x3082); +reg_write( DDR_REG_BASE +0x5117f*4+0x02000000,0xa94c); +reg_write( DDR_REG_BASE +0x51180*4+0x02000000,0x8c40); +reg_write( DDR_REG_BASE +0x51181*4+0x02000000,0xa94d); +reg_write( DDR_REG_BASE +0x51182*4+0x02000000,0x8d40); +reg_write( DDR_REG_BASE +0x51183*4+0x02000000,0xa94e); +reg_write( DDR_REG_BASE +0x51184*4+0x02000000,0x8e40); +reg_write( DDR_REG_BASE +0x51185*4+0x02000000,0xa950); +reg_write( DDR_REG_BASE +0x51186*4+0x02000000,0x8f40); +reg_write( DDR_REG_BASE +0x51187*4+0x02000000,0xa951); +reg_write( DDR_REG_BASE +0x51188*4+0x02000000,0x8f41); +reg_write( DDR_REG_BASE +0x51189*4+0x02000000,0xa956); +reg_write( DDR_REG_BASE +0x5118a*4+0x02000000,0x8f42); +reg_write( DDR_REG_BASE +0x5118b*4+0x02000000,0xa958); +reg_write( DDR_REG_BASE +0x5118c*4+0x02000000,0xbb9); +reg_write( DDR_REG_BASE +0x5118d*4+0x02000000,0x9094); +reg_write( DDR_REG_BASE +0x5118e*4+0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x5118f*4+0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x51190*4+0x02000000,0xef9); +reg_write( DDR_REG_BASE +0x51191*4+0x02000000,0xb0b4); +reg_write( DDR_REG_BASE +0x51192*4+0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x51193*4+0x02000000,0xf08d); +reg_write( DDR_REG_BASE +0x51194*4+0x02000000,0xda3e); +reg_write( DDR_REG_BASE +0x51195*4+0x02000000,0xba9f); +reg_write( DDR_REG_BASE +0x51196*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x51197*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x51198*4+0x02000000,0xa83a); +reg_write( DDR_REG_BASE +0x51199*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x5119a*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x5119b*4+0x02000000,0xa83b); +reg_write( DDR_REG_BASE +0x5119c*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x5119d*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x5119e*4+0x02000000,0xa83c); +reg_write( DDR_REG_BASE +0x5119f*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511a0*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511a1*4+0x02000000,0xa83d); +reg_write( DDR_REG_BASE +0x511a2*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511a3*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511a4*4+0x02000000,0x1824); +reg_write( DDR_REG_BASE +0x511a5*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511a6*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511a7*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511a8*4+0x02000000,0x1825); +reg_write( DDR_REG_BASE +0x511a9*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511aa*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511ab*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511ac*4+0x02000000,0x1826); +reg_write( DDR_REG_BASE +0x511ad*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511ae*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511af*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511b0*4+0x02000000,0x1827); +reg_write( DDR_REG_BASE +0x511b1*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511b2*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511b3*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511b4*4+0x02000000,0x1829); +reg_write( DDR_REG_BASE +0x511b5*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511b6*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511b7*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511b8*4+0x02000000,0x182a); +reg_write( DDR_REG_BASE +0x511b9*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511ba*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511bb*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511bc*4+0x02000000,0x182f); +reg_write( DDR_REG_BASE +0x511bd*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511be*4+0x02000000,0x121c); +reg_write( DDR_REG_BASE +0x511bf*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511c0*4+0x02000000,0x1831); +reg_write( DDR_REG_BASE +0x511c1*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511c2*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511c3*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511c4*4+0x02000000,0x1833); +reg_write( DDR_REG_BASE +0x511c5*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511c6*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511c7*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511c8*4+0x02000000,0x1834); +reg_write( DDR_REG_BASE +0x511c9*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511ca*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511cb*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511cc*4+0x02000000,0x1835); +reg_write( DDR_REG_BASE +0x511cd*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511ce*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511cf*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511d0*4+0x02000000,0x1836); +reg_write( DDR_REG_BASE +0x511d1*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511d2*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511d3*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511d4*4+0x02000000,0x183d); +reg_write( DDR_REG_BASE +0x511d5*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511d6*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511d7*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511d8*4+0x02000000,0x183e); +reg_write( DDR_REG_BASE +0x511d9*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511da*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511db*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511dc*4+0x02000000,0x183f); +reg_write( DDR_REG_BASE +0x511dd*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511de*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511df*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511e0*4+0x02000000,0x1840); +reg_write( DDR_REG_BASE +0x511e1*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511e2*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511e3*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511e4*4+0x02000000,0x1842); +reg_write( DDR_REG_BASE +0x511e5*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511e6*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511e7*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511e8*4+0x02000000,0x1843); +reg_write( DDR_REG_BASE +0x511e9*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511ea*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511eb*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511ec*4+0x02000000,0x1848); +reg_write( DDR_REG_BASE +0x511ed*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511ee*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511ef*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511f0*4+0x02000000,0x184a); +reg_write( DDR_REG_BASE +0x511f1*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511f2*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511f3*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511f4*4+0x02000000,0x184c); +reg_write( DDR_REG_BASE +0x511f5*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511f6*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511f7*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511f8*4+0x02000000,0x184d); +reg_write( DDR_REG_BASE +0x511f9*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511fa*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511fb*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511fc*4+0x02000000,0x184e); +reg_write( DDR_REG_BASE +0x511fd*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511fe*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511ff*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x51200*4+0x02000000,0x184f); +reg_write( DDR_REG_BASE +0x51201*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x51202*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x51203*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x51204*4+0x02000000,0x1856); +reg_write( DDR_REG_BASE +0x51205*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x51206*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x51207*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x51208*4+0x02000000,0x1857); +reg_write( DDR_REG_BASE +0x51209*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x5120a*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x5120b*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x5120c*4+0x02000000,0x1858); +reg_write( DDR_REG_BASE +0x5120d*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x5120e*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x5120f*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x51210*4+0x02000000,0x1859); +reg_write( DDR_REG_BASE +0x51211*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x51212*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x51213*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x51214*4+0x02000000,0x185b); +reg_write( DDR_REG_BASE +0x51215*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x51216*4+0x02000000,0x8a20); +reg_write( DDR_REG_BASE +0x51217*4+0x02000000,0x185c); +reg_write( DDR_REG_BASE +0x51218*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x51219*4+0x02000000,0x8a21); +reg_write( DDR_REG_BASE +0x5121a*4+0x02000000,0x1861); +reg_write( DDR_REG_BASE +0x5121b*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x5121c*4+0x02000000,0x8a22); +reg_write( DDR_REG_BASE +0x5121d*4+0x02000000,0x1863); +reg_write( DDR_REG_BASE +0x5121e*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x5121f*4+0x02000000,0xc0a3); +reg_write( DDR_REG_BASE +0x51220*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x51221*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x51222*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51223*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51224*4+0x02000000,0xc3e4); +reg_write( DDR_REG_BASE +0x51225*4+0x02000000,0xc1ab); +reg_write( DDR_REG_BASE +0x51226*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x51227*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51228*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51229*4+0x02000000,0x650); +reg_write( DDR_REG_BASE +0x5122a*4+0x02000000,0xc2e); +reg_write( DDR_REG_BASE +0x5122b*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5122c*4+0x02000000,0xda2a); +reg_write( DDR_REG_BASE +0x5122d*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x5122e*4+0x02000000,0x92e); +reg_write( DDR_REG_BASE +0x5122f*4+0x02000000,0x2a0); +reg_write( DDR_REG_BASE +0x51230*4+0x02000000,0xd92a); +reg_write( DDR_REG_BASE +0x51231*4+0x02000000,0xdd25); +reg_write( DDR_REG_BASE +0x51232*4+0x02000000,0xbd9f); +reg_write( DDR_REG_BASE +0x51233*4+0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x51234*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51235*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51236*4+0x02000000,0xe4); +reg_write( DDR_REG_BASE +0x51237*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x51238*4+0x02000000,0x1533); +reg_write( DDR_REG_BASE +0x51239*4+0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x5123a*4+0x02000000,0xb601); +reg_write( DDR_REG_BASE +0x5123b*4+0x02000000,0x15f4); +reg_write( DDR_REG_BASE +0x5123c*4+0x02000000,0x9080); +reg_write( DDR_REG_BASE +0x5123d*4+0x02000000,0xe888); +reg_write( DDR_REG_BASE +0x5123e*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5123f*4+0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x51240*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51241*4+0x02000000,0xe154); +reg_write( DDR_REG_BASE +0x51242*4+0x02000000,0x1e42); +reg_write( DDR_REG_BASE +0x51243*4+0x02000000,0x905d); +reg_write( DDR_REG_BASE +0x51244*4+0x02000000,0xbda); +reg_write( DDR_REG_BASE +0x51245*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x51246*4+0x02000000,0x2053); +reg_write( DDR_REG_BASE +0x51247*4+0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x51248*4+0x02000000,0x1a01); +reg_write( DDR_REG_BASE +0x51249*4+0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x5124a*4+0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x5124b*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x5124c*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x5124d*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x5124e*4+0x02000000,0xb9c3); +reg_write( DDR_REG_BASE +0x5124f*4+0x02000000,0x1a02); +reg_write( DDR_REG_BASE +0x51250*4+0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x51251*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x51252*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x51253*4+0x02000000,0x901); +reg_write( DDR_REG_BASE +0x51254*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x51255*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51256*4+0x02000000,0xb8c1); +reg_write( DDR_REG_BASE +0x51257*4+0x02000000,0xdea); +reg_write( DDR_REG_BASE +0x51258*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x51259*4+0x02000000,0x1a06); +reg_write( DDR_REG_BASE +0x5125a*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x5125b*4+0x02000000,0x9ce); +reg_write( DDR_REG_BASE +0x5125c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5125d*4+0x02000000,0x8b2); +reg_write( DDR_REG_BASE +0x5125e*4+0x02000000,0x1c0); +reg_write( DDR_REG_BASE +0x5125f*4+0x02000000,0x164c); +reg_write( DDR_REG_BASE +0x51260*4+0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x51261*4+0x02000000,0x80d); +reg_write( DDR_REG_BASE +0x51262*4+0x02000000,0x151); +reg_write( DDR_REG_BASE +0x51263*4+0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x51264*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x51265*4+0x02000000,0xb601); +reg_write( DDR_REG_BASE +0x51266*4+0x02000000,0xc7c4); +reg_write( DDR_REG_BASE +0x51267*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51268*4+0x02000000,0xc3e2); +reg_write( DDR_REG_BASE +0x51269*4+0x02000000,0xc1bd); +reg_write( DDR_REG_BASE +0x5126a*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x5126b*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x5126c*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5126d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5126e*4+0x02000000,0x4ad); +reg_write( DDR_REG_BASE +0x5126f*4+0x02000000,0xba6); +reg_write( DDR_REG_BASE +0x51270*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51271*4+0x02000000,0xda72); +reg_write( DDR_REG_BASE +0x51272*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x51273*4+0x02000000,0x8a6); +reg_write( DDR_REG_BASE +0x51274*4+0x02000000,0x2a0); +reg_write( DDR_REG_BASE +0x51275*4+0x02000000,0xd972); +reg_write( DDR_REG_BASE +0x51276*4+0x02000000,0xed07); +reg_write( DDR_REG_BASE +0x51277*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x51278*4+0x02000000,0xc07); +reg_write( DDR_REG_BASE +0x51279*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5127a*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x5127b*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5127c*4+0x02000000,0xe8c4); +reg_write( DDR_REG_BASE +0x5127d*4+0x02000000,0xc7c2); +reg_write( DDR_REG_BASE +0x5127e*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5127f*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51280*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51281*4+0x02000000,0xc1a7); +reg_write( DDR_REG_BASE +0x51282*4+0x02000000,0xbfa); +reg_write( DDR_REG_BASE +0x51283*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51284*4+0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x51285*4+0x02000000,0xb72); +reg_write( DDR_REG_BASE +0x51286*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51287*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x51288*4+0x02000000,0xbe2); +reg_write( DDR_REG_BASE +0x51289*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5128a*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5128b*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x5128c*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5128d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5128e*4+0x02000000,0x2710); +reg_write( DDR_REG_BASE +0x5128f*4+0x02000000,0xbe2); +reg_write( DDR_REG_BASE +0x51290*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x51291*4+0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x51292*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x51293*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51294*4+0x02000000,0xcd6); +reg_write( DDR_REG_BASE +0x51295*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51296*4+0x02000000,0xd91f); +reg_write( DDR_REG_BASE +0x51297*4+0x02000000,0xca00); +reg_write( DDR_REG_BASE +0x51298*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51299*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x5129a*4+0x02000000,0x7604); +reg_write( DDR_REG_BASE +0x5129b*4+0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x5129c*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5129d*4+0x02000000,0xb98e); +reg_write( DDR_REG_BASE +0x5129e*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5129f*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x512a0*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x512a1*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x512a2*4+0x02000000,0xd92); +reg_write( DDR_REG_BASE +0x512a3*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512a4*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x512a5*4+0x02000000,0x7bcf); +reg_write( DDR_REG_BASE +0x512a6*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x512a7*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x512a8*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x512a9*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x512aa*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x512ab*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x512ac*4+0x02000000,0xd7e); +reg_write( DDR_REG_BASE +0x512ad*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512ae*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x512af*4+0x02000000,0x71cd); +reg_write( DDR_REG_BASE +0x512b0*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x512b1*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x512b2*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x512b3*4+0x02000000,0xdb7c); +reg_write( DDR_REG_BASE +0x512b4*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x512b5*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x512b6*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x512b7*4+0x02000000,0xd6a); +reg_write( DDR_REG_BASE +0x512b8*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512b9*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x512ba*4+0x02000000,0xfae); +reg_write( DDR_REG_BASE +0x512bb*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512bc*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x512bd*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x512be*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x512bf*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x512c0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x512c1*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x512c2*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x512c3*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x512c4*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x512c5*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x512c6*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x512c7*4+0x02000000,0xd4a); +reg_write( DDR_REG_BASE +0x512c8*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512c9*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x512ca*4+0x02000000,0xf838); +reg_write( DDR_REG_BASE +0x512cb*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x512cc*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x512cd*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x512ce*4+0x02000000,0xd3a); +reg_write( DDR_REG_BASE +0x512cf*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512d0*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x512d1*4+0x02000000,0xf835); +reg_write( DDR_REG_BASE +0x512d2*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x512d3*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x512d4*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x512d5*4+0x02000000,0xd2e); +reg_write( DDR_REG_BASE +0x512d6*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512d7*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x512d8*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x512d9*4+0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x512da*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x512db*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x512dc*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x512dd*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x512de*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x512df*4+0x02000000,0xd1a); +reg_write( DDR_REG_BASE +0x512e0*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512e1*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x512e2*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x512e3*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x512e4*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x512e5*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x512e6*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x512e7*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x512e8*4+0x02000000,0xe020); +reg_write( DDR_REG_BASE +0x512e9*4+0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x512ea*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x512eb*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x512ec*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x512ed*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x512ee*4+0x02000000,0xcfa); +reg_write( DDR_REG_BASE +0x512ef*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512f0*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x512f1*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x512f2*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x512f3*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x512f4*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x512f5*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x512f6*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x512f7*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x512f8*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x512f9*4+0x02000000,0xce6); +reg_write( DDR_REG_BASE +0x512fa*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512fb*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x512fc*4+0x02000000,0xc105); +reg_write( DDR_REG_BASE +0x512fd*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x512fe*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x512ff*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51300*4+0x02000000,0x7914); +reg_write( DDR_REG_BASE +0x51301*4+0x02000000,0x2154); +reg_write( DDR_REG_BASE +0x51302*4+0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x51303*4+0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x51304*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51305*4+0x02000000,0x2054); +reg_write( DDR_REG_BASE +0x51306*4+0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x51307*4+0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x51308*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51309*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x5130a*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5130b*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5130c*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x5130d*4+0x02000000,0xcbe); +reg_write( DDR_REG_BASE +0x5130e*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5130f*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51310*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51311*4+0x02000000,0xb88e); +reg_write( DDR_REG_BASE +0x51312*4+0x02000000,0x791b); +reg_write( DDR_REG_BASE +0x51313*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51314*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x51315*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x51316*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x51317*4+0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x51318*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51319*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5131a*4+0x02000000,0xca2); +reg_write( DDR_REG_BASE +0x5131b*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5131c*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5131d*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5131e*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5131f*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x51320*4+0x02000000,0xdb40); +reg_write( DDR_REG_BASE +0x51321*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51322*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51323*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51324*4+0x02000000,0xc8e); +reg_write( DDR_REG_BASE +0x51325*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51326*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51327*4+0x02000000,0xeba); +reg_write( DDR_REG_BASE +0x51328*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51329*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5132a*4+0x02000000,0xbfc1); +reg_write( DDR_REG_BASE +0x5132b*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5132c*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x5132d*4+0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x5132e*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x5132f*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51330*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51331*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51332*4+0x02000000,0xc72); +reg_write( DDR_REG_BASE +0x51333*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51334*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x51335*4+0x02000000,0xc0a7); +reg_write( DDR_REG_BASE +0x51336*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x51337*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x51338*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51339*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5133a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5133b*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x5133c*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5133d*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x5133e*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x5133f*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51340*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51341*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51342*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51343*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51344*4+0x02000000,0x7101); +reg_write( DDR_REG_BASE +0x51345*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51346*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x51347*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51348*4+0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x51349*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5134a*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5134b*4+0x02000000,0x225f); +reg_write( DDR_REG_BASE +0x5134c*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5134d*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x5134e*4+0x02000000,0x7c3); +reg_write( DDR_REG_BASE +0x5134f*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x51350*4+0x02000000,0xeb05); +reg_write( DDR_REG_BASE +0x51351*4+0x02000000,0xbb61); +reg_write( DDR_REG_BASE +0x51352*4+0x02000000,0xbff); +reg_write( DDR_REG_BASE +0x51353*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x51354*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51355*4+0x02000000,0xb8c3); +reg_write( DDR_REG_BASE +0x51356*4+0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x51357*4+0x02000000,0x190); +reg_write( DDR_REG_BASE +0x51358*4+0x02000000,0x877); +reg_write( DDR_REG_BASE +0x51359*4+0x02000000,0x71); +reg_write( DDR_REG_BASE +0x5135a*4+0x02000000,0xdf18); +reg_write( DDR_REG_BASE +0x5135b*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x5135c*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5135d*4+0x02000000,0x116); +reg_write( DDR_REG_BASE +0x5135e*4+0x02000000,0x1e08); +reg_write( DDR_REG_BASE +0x5135f*4+0x02000000,0x1094); +reg_write( DDR_REG_BASE +0x51360*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x51361*4+0x02000000,0x1e02); +reg_write( DDR_REG_BASE +0x51362*4+0x02000000,0x1055); +reg_write( DDR_REG_BASE +0x51363*4+0x02000000,0xd829); +reg_write( DDR_REG_BASE +0x51364*4+0x02000000,0xb6a0); +reg_write( DDR_REG_BASE +0x51365*4+0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x51366*4+0x02000000,0x1205); +reg_write( DDR_REG_BASE +0x51367*4+0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x51368*4+0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x51369*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5136a*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5136b*4+0x02000000,0x98); +reg_write( DDR_REG_BASE +0x5136c*4+0x02000000,0x9680); +reg_write( DDR_REG_BASE +0x5136d*4+0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x5136e*4+0x02000000,0x1ef2); +reg_write( DDR_REG_BASE +0x5136f*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x51370*4+0x02000000,0x9fe); +reg_write( DDR_REG_BASE +0x51371*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x51372*4+0x02000000,0x1e66); +reg_write( DDR_REG_BASE +0x51373*4+0x02000000,0x1044); +reg_write( DDR_REG_BASE +0x51374*4+0x02000000,0xd8a9); +reg_write( DDR_REG_BASE +0x51375*4+0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x51376*4+0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x51377*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x51378*4+0x02000000,0xa46); +reg_write( DDR_REG_BASE +0x51379*4+0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x5137a*4+0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x5137b*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x5137c*4+0x02000000,0xa44); +reg_write( DDR_REG_BASE +0x5137d*4+0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x5137e*4+0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x5137f*4+0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x51380*4+0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x51381*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51382*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51383*4+0x02000000,0x6000); +reg_write( DDR_REG_BASE +0x51384*4+0x02000000,0x1e72); +reg_write( DDR_REG_BASE +0x51385*4+0x02000000,0x935c); +reg_write( DDR_REG_BASE +0x51386*4+0x02000000,0x1ed0); +reg_write( DDR_REG_BASE +0x51387*4+0x02000000,0x9344); +reg_write( DDR_REG_BASE +0x51388*4+0x02000000,0x1e72); +reg_write( DDR_REG_BASE +0x51389*4+0x02000000,0x90dd); +reg_write( DDR_REG_BASE +0x5138a*4+0x02000000,0x972); +reg_write( DDR_REG_BASE +0x5138b*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5138c*4+0x02000000,0x1ed0); +reg_write( DDR_REG_BASE +0x5138d*4+0x02000000,0x92c4); +reg_write( DDR_REG_BASE +0x5138e*4+0x02000000,0x1e72); +reg_write( DDR_REG_BASE +0x5138f*4+0x02000000,0x935c); +reg_write( DDR_REG_BASE +0x51390*4+0x02000000,0x1e72); +reg_write( DDR_REG_BASE +0x51391*4+0x02000000,0x92dc); +reg_write( DDR_REG_BASE +0x51392*4+0x02000000,0xf046); +reg_write( DDR_REG_BASE +0x51393*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x51394*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51395*4+0x02000000,0x116); +reg_write( DDR_REG_BASE +0x51396*4+0x02000000,0x1d08); +reg_write( DDR_REG_BASE +0x51397*4+0x02000000,0x1094); +reg_write( DDR_REG_BASE +0x51398*4+0x02000000,0x71cd); +reg_write( DDR_REG_BASE +0x51399*4+0x02000000,0x1d02); +reg_write( DDR_REG_BASE +0x5139a*4+0x02000000,0x1055); +reg_write( DDR_REG_BASE +0x5139b*4+0x02000000,0x234a); +reg_write( DDR_REG_BASE +0x5139c*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x5139d*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5139e*4+0x02000000,0xbf8b); +reg_write( DDR_REG_BASE +0x5139f*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x513a0*4+0x02000000,0xf); +reg_write( DDR_REG_BASE +0x513a1*4+0x02000000,0x4240); +reg_write( DDR_REG_BASE +0x513a2*4+0x02000000,0xb5c0); +reg_write( DDR_REG_BASE +0x513a3*4+0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x513a4*4+0x02000000,0x12c4); +reg_write( DDR_REG_BASE +0x513a5*4+0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x513a6*4+0x02000000,0x3040); +reg_write( DDR_REG_BASE +0x513a7*4+0x02000000,0x1df2); +reg_write( DDR_REG_BASE +0x513a8*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x513a9*4+0x02000000,0x1d66); +reg_write( DDR_REG_BASE +0x513aa*4+0x02000000,0x1044); +reg_write( DDR_REG_BASE +0x513ab*4+0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x513ac*4+0x02000000,0x13c4); +reg_write( DDR_REG_BASE +0x513ad*4+0x02000000,0x986); +reg_write( DDR_REG_BASE +0x513ae*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x513af*4+0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x513b0*4+0x02000000,0xbf70); +reg_write( DDR_REG_BASE +0x513b1*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x513b2*4+0x02000000,0x6c2); +reg_write( DDR_REG_BASE +0x513b3*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x513b4*4+0x02000000,0x976); +reg_write( DDR_REG_BASE +0x513b5*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x513b6*4+0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x513b7*4+0x02000000,0x13c4); +reg_write( DDR_REG_BASE +0x513b8*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x513b9*4+0x02000000,0x98); +reg_write( DDR_REG_BASE +0x513ba*4+0x02000000,0x9680); +reg_write( DDR_REG_BASE +0x513bb*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x513bc*4+0x02000000,0x966); +reg_write( DDR_REG_BASE +0x513bd*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x513be*4+0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x513bf*4+0x02000000,0x12c4); +reg_write( DDR_REG_BASE +0x513c0*4+0x02000000,0xd888); +reg_write( DDR_REG_BASE +0x513c1*4+0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x513c2*4+0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x513c3*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x513c4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x513c5*4+0x02000000,0x6000); +reg_write( DDR_REG_BASE +0x513c6*4+0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x513c7*4+0x02000000,0x12c4); +reg_write( DDR_REG_BASE +0x513c8*4+0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x513c9*4+0x02000000,0x1784); +reg_write( DDR_REG_BASE +0x513ca*4+0x02000000,0x1d72); +reg_write( DDR_REG_BASE +0x513cb*4+0x02000000,0x939c); +reg_write( DDR_REG_BASE +0x513cc*4+0x02000000,0x1dd0); +reg_write( DDR_REG_BASE +0x513cd*4+0x02000000,0x9384); +reg_write( DDR_REG_BASE +0x513ce*4+0x02000000,0x1d72); +reg_write( DDR_REG_BASE +0x513cf*4+0x02000000,0x90dd); +reg_write( DDR_REG_BASE +0x513d0*4+0x02000000,0x8e6); +reg_write( DDR_REG_BASE +0x513d1*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x513d2*4+0x02000000,0x1dd0); +reg_write( DDR_REG_BASE +0x513d3*4+0x02000000,0x9784); +reg_write( DDR_REG_BASE +0x513d4*4+0x02000000,0x1d72); +reg_write( DDR_REG_BASE +0x513d5*4+0x02000000,0x939c); +reg_write( DDR_REG_BASE +0x513d6*4+0x02000000,0x1d72); +reg_write( DDR_REG_BASE +0x513d7*4+0x02000000,0x979c); +reg_write( DDR_REG_BASE +0x513d8*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x513d9*4+0x02000000,0x92e); +reg_write( DDR_REG_BASE +0x513da*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x513db*4+0x02000000,0xd920); +reg_write( DDR_REG_BASE +0x513dc*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x513dd*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x513de*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x513df*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x513e0*4+0x02000000,0x8c6); +reg_write( DDR_REG_BASE +0x513e1*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x513e2*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x513e3*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x513e4*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x513e5*4+0x02000000,0x8be); +reg_write( DDR_REG_BASE +0x513e6*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x513e7*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x513e8*4+0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x513e9*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x513ea*4+0x02000000,0x8b2); +reg_write( DDR_REG_BASE +0x513eb*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x513ec*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x513ed*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x513ee*4+0x02000000,0x1d0a); +reg_write( DDR_REG_BASE +0x513ef*4+0x02000000,0x909d); +reg_write( DDR_REG_BASE +0x513f0*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x513f1*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x513f2*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x513f3*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x513f4*4+0x02000000,0x2088); +reg_write( DDR_REG_BASE +0x513f5*4+0x02000000,0x901); +reg_write( DDR_REG_BASE +0x513f6*4+0x02000000,0x2089); +reg_write( DDR_REG_BASE +0x513f7*4+0x02000000,0x906); +reg_write( DDR_REG_BASE +0x513f8*4+0x02000000,0x2080); +reg_write( DDR_REG_BASE +0x513f9*4+0x02000000,0x78e); +reg_write( DDR_REG_BASE +0x513fa*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x513fb*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x513fc*4+0x02000000,0x9); +reg_write( DDR_REG_BASE +0x513fd*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x513fe*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x513ff*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51400*4+0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x51401*4+0x02000000,0x8f4); +reg_write( DDR_REG_BASE +0x51402*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x51403*4+0x02000000,0xb97e); +reg_write( DDR_REG_BASE +0x51404*4+0x02000000,0xb986); +reg_write( DDR_REG_BASE +0x51405*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x51406*4+0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x51407*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51408*4+0x02000000,0xc3e6); +reg_write( DDR_REG_BASE +0x51409*4+0x02000000,0xc1aa); +reg_write( DDR_REG_BASE +0x5140a*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x5140b*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5140c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5140d*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x5140e*4+0x02000000,0xa8cd); +reg_write( DDR_REG_BASE +0x5140f*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51410*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51411*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51412*4+0x02000000,0xa8cc); +reg_write( DDR_REG_BASE +0x51413*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51414*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51415*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51416*4+0x02000000,0xa8cb); +reg_write( DDR_REG_BASE +0x51417*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51418*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51419*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x5141a*4+0x02000000,0xa8ca); +reg_write( DDR_REG_BASE +0x5141b*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5141c*4+0x02000000,0x89); +reg_write( DDR_REG_BASE +0x5141d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5141e*4+0x02000000,0xe82); +reg_write( DDR_REG_BASE +0x5141f*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51420*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51421*4+0x02000000,0x23b); +reg_write( DDR_REG_BASE +0x51422*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51423*4+0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x51424*4+0x02000000,0x17c1); +reg_write( DDR_REG_BASE +0x51425*4+0x02000000,0xe906); +reg_write( DDR_REG_BASE +0x51426*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x51427*4+0x02000000,0x901); +reg_write( DDR_REG_BASE +0x51428*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x51429*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5142a*4+0x02000000,0x1be4); +reg_write( DDR_REG_BASE +0x5142b*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x5142c*4+0x02000000,0x211); +reg_write( DDR_REG_BASE +0x5142d*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5142e*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5142f*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51430*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51431*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51432*4+0x02000000,0x1b); +reg_write( DDR_REG_BASE +0x51433*4+0x02000000,0x81f); +reg_write( DDR_REG_BASE +0x51434*4+0x02000000,0x5e); +reg_write( DDR_REG_BASE +0x51435*4+0x02000000,0xea07); +reg_write( DDR_REG_BASE +0x51436*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51437*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51438*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51439*4+0x02000000,0x7d); +reg_write( DDR_REG_BASE +0x5143a*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x5143b*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5143c*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5143d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5143e*4+0x02000000,0x4a); +reg_write( DDR_REG_BASE +0x5143f*4+0x02000000,0x7610); +reg_write( DDR_REG_BASE +0x51440*4+0x02000000,0xf4f3); +reg_write( DDR_REG_BASE +0x51441*4+0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x51442*4+0x02000000,0x1bf0); +reg_write( DDR_REG_BASE +0x51443*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x51444*4+0x02000000,0x13f0); +reg_write( DDR_REG_BASE +0x51445*4+0x02000000,0xb001); +reg_write( DDR_REG_BASE +0x51446*4+0x02000000,0xc62); +reg_write( DDR_REG_BASE +0x51447*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x51448*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x51449*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x5144a*4+0x02000000,0xea0b); +reg_write( DDR_REG_BASE +0x5144b*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5144c*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x5144d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5144e*4+0x02000000,0x58); +reg_write( DDR_REG_BASE +0x5144f*4+0x02000000,0x13e4); +reg_write( DDR_REG_BASE +0x51450*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x51451*4+0x02000000,0x782b); +reg_write( DDR_REG_BASE +0x51452*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51453*4+0x02000000,0xf40c); +reg_write( DDR_REG_BASE +0x51454*4+0x02000000,0xf0df); +reg_write( DDR_REG_BASE +0x51455*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51456*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51457*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51458*4+0x02000000,0x25); +reg_write( DDR_REG_BASE +0x51459*4+0x02000000,0x13e4); +reg_write( DDR_REG_BASE +0x5145a*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x5145b*4+0x02000000,0x782b); +reg_write( DDR_REG_BASE +0x5145c*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5145d*4+0x02000000,0xf2d7); +reg_write( DDR_REG_BASE +0x5145e*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5145f*4+0x02000000,0xbac4); +reg_write( DDR_REG_BASE +0x51460*4+0x02000000,0xea05); +reg_write( DDR_REG_BASE +0x51461*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x51462*4+0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x51463*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x51464*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51465*4+0x02000000,0xa4e); +reg_write( DDR_REG_BASE +0x51466*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51467*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51468*4+0x02000000,0x13e4); +reg_write( DDR_REG_BASE +0x51469*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x5146a*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x5146b*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5146c*4+0x02000000,0x7043); +reg_write( DDR_REG_BASE +0x5146d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5146e*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x5146f*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51470*4+0x02000000,0xb06); +reg_write( DDR_REG_BASE +0x51471*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51472*4+0x02000000,0x1be8); +reg_write( DDR_REG_BASE +0x51473*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x51474*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51475*4+0x02000000,0xd854); +reg_write( DDR_REG_BASE +0x51476*4+0x02000000,0x1be0); +reg_write( DDR_REG_BASE +0x51477*4+0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x51478*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51479*4+0x02000000,0x7042); +reg_write( DDR_REG_BASE +0x5147a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5147b*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x5147c*4+0x02000000,0x1bfc); +reg_write( DDR_REG_BASE +0x5147d*4+0x02000000,0xb700); +reg_write( DDR_REG_BASE +0x5147e*4+0x02000000,0x2402); +reg_write( DDR_REG_BASE +0x5147f*4+0x02000000,0x301c); +reg_write( DDR_REG_BASE +0x51480*4+0x02000000,0xc082); +reg_write( DDR_REG_BASE +0x51481*4+0x02000000,0xf9a); +reg_write( DDR_REG_BASE +0x51482*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51483*4+0x02000000,0x1bec); +reg_write( DDR_REG_BASE +0x51484*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x51485*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x51486*4+0x02000000,0x1801); +reg_write( DDR_REG_BASE +0x51487*4+0x02000000,0x13); +reg_write( DDR_REG_BASE +0x51488*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x51489*4+0x02000000,0xe1d0); +reg_write( DDR_REG_BASE +0x5148a*4+0x02000000,0xf7fc); +reg_write( DDR_REG_BASE +0x5148b*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x5148c*4+0x02000000,0xf041); +reg_write( DDR_REG_BASE +0x5148d*4+0x02000000,0xeea); +reg_write( DDR_REG_BASE +0x5148e*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5148f*4+0x02000000,0x78af); +reg_write( DDR_REG_BASE +0x51490*4+0x02000000,0x1bf4); +reg_write( DDR_REG_BASE +0x51491*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x51492*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51493*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51494*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51495*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51496*4+0x02000000,0x13e8); +reg_write( DDR_REG_BASE +0x51497*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x51498*4+0x02000000,0x13f4); +reg_write( DDR_REG_BASE +0x51499*4+0x02000000,0xb002); +reg_write( DDR_REG_BASE +0x5149a*4+0x02000000,0xe56); +reg_write( DDR_REG_BASE +0x5149b*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5149c*4+0x02000000,0x1bf8); +reg_write( DDR_REG_BASE +0x5149d*4+0x02000000,0xb001); +reg_write( DDR_REG_BASE +0x5149e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5149f*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x514a0*4+0x02000000,0xd090); +reg_write( DDR_REG_BASE +0x514a1*4+0x02000000,0xf9e); +reg_write( DDR_REG_BASE +0x514a2*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x514a3*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x514a4*4+0x02000000,0x84a); +reg_write( DDR_REG_BASE +0x514a5*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x514a6*4+0x02000000,0x13e8); +reg_write( DDR_REG_BASE +0x514a7*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514a8*4+0x02000000,0x13f0); +reg_write( DDR_REG_BASE +0x514a9*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514aa*4+0x02000000,0x2342); +reg_write( DDR_REG_BASE +0x514ab*4+0x02000000,0x3201); +reg_write( DDR_REG_BASE +0x514ac*4+0x02000000,0x85e); +reg_write( DDR_REG_BASE +0x514ad*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x514ae*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x514af*4+0x02000000,0x13f8); +reg_write( DDR_REG_BASE +0x514b0*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514b1*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x514b2*4+0x02000000,0x8a); +reg_write( DDR_REG_BASE +0x514b3*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x514b4*4+0x02000000,0x43c1); +reg_write( DDR_REG_BASE +0x514b5*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x514b6*4+0x02000000,0xf8f); +reg_write( DDR_REG_BASE +0x514b7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x514b8*4+0x02000000,0x3f00); +reg_write( DDR_REG_BASE +0x514b9*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x514ba*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x514bb*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x514bc*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x514bd*4+0x02000000,0x1bf8); +reg_write( DDR_REG_BASE +0x514be*4+0x02000000,0xb3c0); +reg_write( DDR_REG_BASE +0x514bf*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x514c0*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x514c1*4+0x02000000,0x13f4); +reg_write( DDR_REG_BASE +0x514c2*4+0x02000000,0xb002); +reg_write( DDR_REG_BASE +0x514c3*4+0x02000000,0xd3a); +reg_write( DDR_REG_BASE +0x514c4*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x514c5*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x514c6*4+0x02000000,0xef06); +reg_write( DDR_REG_BASE +0x514c7*4+0x02000000,0x13ec); +reg_write( DDR_REG_BASE +0x514c8*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514c9*4+0x02000000,0x60b8); +reg_write( DDR_REG_BASE +0x514ca*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x514cb*4+0x02000000,0x43); +reg_write( DDR_REG_BASE +0x514cc*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x514cd*4+0x02000000,0xe5d0); +reg_write( DDR_REG_BASE +0x514ce*4+0x02000000,0x77e); +reg_write( DDR_REG_BASE +0x514cf*4+0x02000000,0xffee); +reg_write( DDR_REG_BASE +0x514d0*4+0x02000000,0x774c); +reg_write( DDR_REG_BASE +0x514d1*4+0x02000000,0x4548); +reg_write( DDR_REG_BASE +0x514d2*4+0x02000000,0x4748); +reg_write( DDR_REG_BASE +0x514d3*4+0x02000000,0x4140); +reg_write( DDR_REG_BASE +0x514d4*4+0x02000000,0xf022); +reg_write( DDR_REG_BASE +0x514d5*4+0x02000000,0x13ec); +reg_write( DDR_REG_BASE +0x514d6*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514d7*4+0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x514d8*4+0x02000000,0x483); +reg_write( DDR_REG_BASE +0x514d9*4+0x02000000,0x1bec); +reg_write( DDR_REG_BASE +0x514da*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514db*4+0x02000000,0xf212); +reg_write( DDR_REG_BASE +0x514dc*4+0x02000000,0x13e0); +reg_write( DDR_REG_BASE +0x514dd*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514de*4+0x02000000,0xe0d0); +reg_write( DDR_REG_BASE +0x514df*4+0x02000000,0xf203); +reg_write( DDR_REG_BASE +0x514e0*4+0x02000000,0xeb11); +reg_write( DDR_REG_BASE +0x514e1*4+0x02000000,0x13e0); +reg_write( DDR_REG_BASE +0x514e2*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514e3*4+0x02000000,0x4fb4); +reg_write( DDR_REG_BASE +0x514e4*4+0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x514e5*4+0x02000000,0x4833); +reg_write( DDR_REG_BASE +0x514e6*4+0x02000000,0x7391); +reg_write( DDR_REG_BASE +0x514e7*4+0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x514e8*4+0x02000000,0x1009); +reg_write( DDR_REG_BASE +0x514e9*4+0x02000000,0x25ca); +reg_write( DDR_REG_BASE +0x514ea*4+0x02000000,0x1049); +reg_write( DDR_REG_BASE +0x514eb*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x514ec*4+0x02000000,0xeb03); +reg_write( DDR_REG_BASE +0x514ed*4+0x02000000,0x772c); +reg_write( DDR_REG_BASE +0x514ee*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x514ef*4+0x02000000,0x13e0); +reg_write( DDR_REG_BASE +0x514f0*4+0x02000000,0xb001); +reg_write( DDR_REG_BASE +0x514f1*4+0x02000000,0x13e0); +reg_write( DDR_REG_BASE +0x514f2*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514f3*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x514f4*4+0x02000000,0x1be0); +reg_write( DDR_REG_BASE +0x514f5*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514f6*4+0x02000000,0x13e0); +reg_write( DDR_REG_BASE +0x514f7*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514f8*4+0x02000000,0xe0d1); +reg_write( DDR_REG_BASE +0x514f9*4+0x02000000,0x7ba); +reg_write( DDR_REG_BASE +0x514fa*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x514fb*4+0x02000000,0x7734); +reg_write( DDR_REG_BASE +0x514fc*4+0x02000000,0x2139); +reg_write( DDR_REG_BASE +0x514fd*4+0x02000000,0x83); +reg_write( DDR_REG_BASE +0x514fe*4+0x02000000,0x2538); +reg_write( DDR_REG_BASE +0x514ff*4+0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x51500*4+0x02000000,0x786b); +reg_write( DDR_REG_BASE +0x51501*4+0x02000000,0xd850); +reg_write( DDR_REG_BASE +0x51502*4+0x02000000,0x753c); +reg_write( DDR_REG_BASE +0x51503*4+0x02000000,0x771c); +reg_write( DDR_REG_BASE +0x51504*4+0x02000000,0x77b5); +reg_write( DDR_REG_BASE +0x51505*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51506*4+0x02000000,0xf204); +reg_write( DDR_REG_BASE +0x51507*4+0x02000000,0x4fb0); +reg_write( DDR_REG_BASE +0x51508*4+0x02000000,0x207f); +reg_write( DDR_REG_BASE +0x51509*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5150a*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5150b*4+0x02000000,0x7083); +reg_write( DDR_REG_BASE +0x5150c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5150d*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x5150e*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5150f*4+0x02000000,0x8c); +reg_write( DDR_REG_BASE +0x51510*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x51511*4+0x02000000,0xf32); +reg_write( DDR_REG_BASE +0x51512*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51513*4+0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x51514*4+0x02000000,0x67b8); +reg_write( DDR_REG_BASE +0x51515*4+0x02000000,0x2844); +reg_write( DDR_REG_BASE +0x51516*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x51517*4+0x02000000,0xdd6); +reg_write( DDR_REG_BASE +0x51518*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51519*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x5151a*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5151b*4+0x02000000,0x7043); +reg_write( DDR_REG_BASE +0x5151c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5151d*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x5151e*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5151f*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51520*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51521*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51522*4+0x02000000,0x2614); +reg_write( DDR_REG_BASE +0x51523*4+0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x51524*4+0x02000000,0x2100); +reg_write( DDR_REG_BASE +0x51525*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51526*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51527*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51528*4+0x02000000,0xa90a); +reg_write( DDR_REG_BASE +0x51529*4+0x02000000,0xcda); +reg_write( DDR_REG_BASE +0x5152a*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x5152b*4+0x02000000,0x13e8); +reg_write( DDR_REG_BASE +0x5152c*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x5152d*4+0x02000000,0x13fc); +reg_write( DDR_REG_BASE +0x5152e*4+0x02000000,0xb01c); +reg_write( DDR_REG_BASE +0x5152f*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51530*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51531*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51532*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51533*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x51534*4+0x02000000,0x7a2f); +reg_write( DDR_REG_BASE +0x51535*4+0x02000000,0x7154); +reg_write( DDR_REG_BASE +0x51536*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51537*4+0x02000000,0x7042); +reg_write( DDR_REG_BASE +0x51538*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51539*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x5153a*4+0x02000000,0x5ea); +reg_write( DDR_REG_BASE +0x5153b*4+0x02000000,0xffce); +reg_write( DDR_REG_BASE +0x5153c*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x5153d*4+0x02000000,0x72d5); +reg_write( DDR_REG_BASE +0x5153e*4+0x02000000,0x5ca); +reg_write( DDR_REG_BASE +0x5153f*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x51540*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51541*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51542*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51543*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51544*4+0x02000000,0x180e); +reg_write( DDR_REG_BASE +0x51545*4+0x02000000,0x43); +reg_write( DDR_REG_BASE +0x51546*4+0x02000000,0xc7c6); +reg_write( DDR_REG_BASE +0x51547*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51548*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51549*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5154a*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5154b*4+0x02000000,0xc1bd); +reg_write( DDR_REG_BASE +0x5154c*4+0x02000000,0xd925); +reg_write( DDR_REG_BASE +0x5154d*4+0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x5154e*4+0x02000000,0x8900); +reg_write( DDR_REG_BASE +0x5154f*4+0x02000000,0x1c3a); +reg_write( DDR_REG_BASE +0x51550*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x51551*4+0x02000000,0x1133); +reg_write( DDR_REG_BASE +0x51552*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x51553*4+0x02000000,0x1c3b); +reg_write( DDR_REG_BASE +0x51554*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x51555*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51556*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51557*4+0x02000000,0x7c8); +reg_write( DDR_REG_BASE +0x51558*4+0x02000000,0x8827); +reg_write( DDR_REG_BASE +0x51559*4+0x02000000,0x88a0); +reg_write( DDR_REG_BASE +0x5155a*4+0x02000000,0xc16e); +reg_write( DDR_REG_BASE +0x5155b*4+0x02000000,0x8829); +reg_write( DDR_REG_BASE +0x5155c*4+0x02000000,0x1c39); +reg_write( DDR_REG_BASE +0x5155d*4+0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x5155e*4+0x02000000,0x8828); +reg_write( DDR_REG_BASE +0x5155f*4+0x02000000,0x1c36); +reg_write( DDR_REG_BASE +0x51560*4+0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x51561*4+0x02000000,0x882a); +reg_write( DDR_REG_BASE +0x51562*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51563*4+0x02000000,0x1c37); +reg_write( DDR_REG_BASE +0x51564*4+0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x51565*4+0x02000000,0xe46); +reg_write( DDR_REG_BASE +0x51566*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51567*4+0x02000000,0xc193); +reg_write( DDR_REG_BASE +0x51568*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51569*4+0x02000000,0xc146); +reg_write( DDR_REG_BASE +0x5156a*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x5156b*4+0x02000000,0x7a34); +reg_write( DDR_REG_BASE +0x5156c*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5156d*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x5156e*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x5156f*4+0x02000000,0x9fb); +reg_write( DDR_REG_BASE +0x51570*4+0x02000000,0x82b4); +reg_write( DDR_REG_BASE +0x51571*4+0x02000000,0xc298); +reg_write( DDR_REG_BASE +0x51572*4+0x02000000,0xd90c); +reg_write( DDR_REG_BASE +0x51573*4+0x02000000,0x2905); +reg_write( DDR_REG_BASE +0x51574*4+0x02000000,0x341); +reg_write( DDR_REG_BASE +0x51575*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x51576*4+0x02000000,0x7835); +reg_write( DDR_REG_BASE +0x51577*4+0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x51578*4+0x02000000,0x40d); +reg_write( DDR_REG_BASE +0x51579*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5157a*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5157b*4+0x02000000,0x3ff); +reg_write( DDR_REG_BASE +0x5157c*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5157d*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x5157e*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5157f*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51580*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x51581*4+0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x51582*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x51583*4+0x02000000,0xc105); +reg_write( DDR_REG_BASE +0x51584*4+0x02000000,0xea05); +reg_write( DDR_REG_BASE +0x51585*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x51586*4+0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x51587*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x51588*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51589*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x5158a*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x5158b*4+0x02000000,0x6c7); +reg_write( DDR_REG_BASE +0x5158c*4+0x02000000,0xdca); +reg_write( DDR_REG_BASE +0x5158d*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5158e*4+0x02000000,0x792f); +reg_write( DDR_REG_BASE +0x5158f*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51590*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51591*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x51592*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x51593*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x51594*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51595*4+0x02000000,0xf2f6); +reg_write( DDR_REG_BASE +0x51596*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51597*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51598*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51599*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5159a*4+0x02000000,0xb8e3); +reg_write( DDR_REG_BASE +0x5159b*4+0x02000000,0xf4f0); +reg_write( DDR_REG_BASE +0x5159c*4+0x02000000,0xab6); +reg_write( DDR_REG_BASE +0x5159d*4+0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x5159e*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x5159f*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x515a0*4+0x02000000,0xf07e); +reg_write( DDR_REG_BASE +0x515a1*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x515a2*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x515a3*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x515a4*4+0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x515a5*4+0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x515a6*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x515a7*4+0x02000000,0xb882); +reg_write( DDR_REG_BASE +0x515a8*4+0x02000000,0x815); +reg_write( DDR_REG_BASE +0x515a9*4+0x02000000,0x131); +reg_write( DDR_REG_BASE +0x515aa*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x515ab*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x515ac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x515ad*4+0x02000000,0xa00); +reg_write( DDR_REG_BASE +0x515ae*4+0x02000000,0xea2); +reg_write( DDR_REG_BASE +0x515af*4+0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x515b0*4+0x02000000,0xec2); +reg_write( DDR_REG_BASE +0x515b1*4+0x02000000,0x180); +reg_write( DDR_REG_BASE +0x515b2*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x515b3*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x515b4*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x515b5*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x515b6*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x515b7*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x515b8*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x515b9*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x515ba*4+0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x515bb*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x515bc*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x515bd*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x515be*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x515bf*4+0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x515c0*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x515c1*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x515c2*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x515c3*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x515c4*4+0x02000000,0x2045); +reg_write( DDR_REG_BASE +0x515c5*4+0x02000000,0x180); +reg_write( DDR_REG_BASE +0x515c6*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x515c7*4+0x02000000,0xf4a); +reg_write( DDR_REG_BASE +0x515c8*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x515c9*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x515ca*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x515cb*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x515cc*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x515cd*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x515ce*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x515cf*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x515d0*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x515d1*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x515d2*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x515d3*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x515d4*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x515d5*4+0x02000000,0x448); +reg_write( DDR_REG_BASE +0x515d6*4+0x02000000,0xb8c5); +reg_write( DDR_REG_BASE +0x515d7*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x515d8*4+0x02000000,0xf26); +reg_write( DDR_REG_BASE +0x515d9*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x515da*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x515db*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x515dc*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x515dd*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x515de*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x515df*4+0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x515e0*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x515e1*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x515e2*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x515e3*4+0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x515e4*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x515e5*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x515e6*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x515e7*4+0x02000000,0x2045); +reg_write( DDR_REG_BASE +0x515e8*4+0x02000000,0x580); +reg_write( DDR_REG_BASE +0x515e9*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x515ea*4+0x02000000,0xf02); +reg_write( DDR_REG_BASE +0x515eb*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x515ec*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x515ed*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x515ee*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x515ef*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x515f0*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x515f1*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x515f2*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x515f3*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x515f4*4+0x02000000,0xb8c5); +reg_write( DDR_REG_BASE +0x515f5*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x515f6*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x515f7*4+0x02000000,0xeea); +reg_write( DDR_REG_BASE +0x515f8*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x515f9*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x515fa*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x515fb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x515fc*4+0x02000000,0x2710); +reg_write( DDR_REG_BASE +0x515fd*4+0x02000000,0xd06); +reg_write( DDR_REG_BASE +0x515fe*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x515ff*4+0x02000000,0xd90a); +reg_write( DDR_REG_BASE +0x51600*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51601*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51602*4+0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x51603*4+0x02000000,0x7d0f); +reg_write( DDR_REG_BASE +0x51604*4+0x02000000,0xf8dd); +reg_write( DDR_REG_BASE +0x51605*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51606*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x51607*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x51608*4+0x02000000,0xec6); +reg_write( DDR_REG_BASE +0x51609*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5160a*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5160b*4+0x02000000,0xf8da); +reg_write( DDR_REG_BASE +0x5160c*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5160d*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5160e*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x5160f*4+0x02000000,0xeba); +reg_write( DDR_REG_BASE +0x51610*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51611*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x51612*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51613*4+0x02000000,0xb863); +reg_write( DDR_REG_BASE +0x51614*4+0x02000000,0x811); +reg_write( DDR_REG_BASE +0x51615*4+0x02000000,0x95); +reg_write( DDR_REG_BASE +0x51616*4+0x02000000,0xd9e); +reg_write( DDR_REG_BASE +0x51617*4+0x02000000,0x180); +reg_write( DDR_REG_BASE +0x51618*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51619*4+0x02000000,0xe66); +reg_write( DDR_REG_BASE +0x5161a*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5161b*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5161c*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5161d*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5161e*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5161f*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51620*4+0x02000000,0x7514); +reg_write( DDR_REG_BASE +0x51621*4+0x02000000,0x702); +reg_write( DDR_REG_BASE +0x51622*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x51623*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x51624*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51625*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51626*4+0x02000000,0xa00); +reg_write( DDR_REG_BASE +0x51627*4+0x02000000,0xdb2); +reg_write( DDR_REG_BASE +0x51628*4+0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x51629*4+0x02000000,0xdd2); +reg_write( DDR_REG_BASE +0x5162a*4+0x02000000,0x180); +reg_write( DDR_REG_BASE +0x5162b*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x5162c*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5162d*4+0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x5162e*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5162f*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51630*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51631*4+0x02000000,0xdb18); +reg_write( DDR_REG_BASE +0x51632*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x51633*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x51634*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x51635*4+0x02000000,0xe6e); +reg_write( DDR_REG_BASE +0x51636*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51637*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x51638*4+0x02000000,0x8b2); +reg_write( DDR_REG_BASE +0x51639*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5163a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5163b*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x5163c*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5163d*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5163e*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5163f*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x51640*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x51641*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x51642*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51643*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x51644*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51645*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x51646*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x51647*4+0x02000000,0xe4a); +reg_write( DDR_REG_BASE +0x51648*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51649*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5164a*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x5164b*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5164c*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5164d*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5164e*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5164f*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x51650*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51651*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x51652*4+0x02000000,0xe32); +reg_write( DDR_REG_BASE +0x51653*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51654*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x51655*4+0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x51656*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x51657*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51658*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51659*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5165a*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5165b*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5165c*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x5165d*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5165e*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5165f*4+0x02000000,0xe1a); +reg_write( DDR_REG_BASE +0x51660*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51661*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x51662*4+0x02000000,0x3481); +reg_write( DDR_REG_BASE +0x51663*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x51664*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51665*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51666*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x51667*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51668*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x51669*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5166a*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x5166b*4+0x02000000,0xe02); +reg_write( DDR_REG_BASE +0x5166c*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5166d*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5166e*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x5166f*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51670*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51671*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x51672*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51673*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x51674*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51675*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x51676*4+0x02000000,0xdea); +reg_write( DDR_REG_BASE +0x51677*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51678*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51679*4+0x02000000,0x816); +reg_write( DDR_REG_BASE +0x5167a*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5167b*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5167c*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x5167d*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5167e*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5167f*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x51680*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51681*4+0x02000000,0xdb18); +reg_write( DDR_REG_BASE +0x51682*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51683*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x51684*4+0x02000000,0xdce); +reg_write( DDR_REG_BASE +0x51685*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51686*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51687*4+0x02000000,0xcbe); +reg_write( DDR_REG_BASE +0x51688*4+0x02000000,0x180); +reg_write( DDR_REG_BASE +0x51689*4+0x02000000,0xf07f); +reg_write( DDR_REG_BASE +0x5168a*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5168b*4+0x02000000,0xcea); +reg_write( DDR_REG_BASE +0x5168c*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5168d*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x5168e*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x5168f*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x51690*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x51691*4+0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x51692*4+0x02000000,0x101); +reg_write( DDR_REG_BASE +0x51693*4+0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x51694*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51695*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51696*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x51697*4+0x02000000,0x7e0f); +reg_write( DDR_REG_BASE +0x51698*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x51699*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5169a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5169b*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5169c*4+0x02000000,0xfae); +reg_write( DDR_REG_BASE +0x5169d*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5169e*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x5169f*4+0x02000000,0xd828); +reg_write( DDR_REG_BASE +0x516a0*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x516a1*4+0x02000000,0xf88c); +reg_write( DDR_REG_BASE +0x516a2*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x516a3*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x516a4*4+0x02000000,0xf9e); +reg_write( DDR_REG_BASE +0x516a5*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516a6*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x516a7*4+0x02000000,0xf889); +reg_write( DDR_REG_BASE +0x516a8*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x516a9*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x516aa*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x516ab*4+0x02000000,0x33c1); +reg_write( DDR_REG_BASE +0x516ac*4+0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x516ad*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516ae*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x516af*4+0x02000000,0xf885); +reg_write( DDR_REG_BASE +0x516b0*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x516b1*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x516b2*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x516b3*4+0x02000000,0x3501); +reg_write( DDR_REG_BASE +0x516b4*4+0x02000000,0xf7e); +reg_write( DDR_REG_BASE +0x516b5*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516b6*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x516b7*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x516b8*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x516b9*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x516ba*4+0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x516bb*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x516bc*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x516bd*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x516be*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x516bf*4+0x02000000,0xf6a); +reg_write( DDR_REG_BASE +0x516c0*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516c1*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x516c2*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x516c3*4+0x02000000,0xd12); +reg_write( DDR_REG_BASE +0x516c4*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516c5*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x516c6*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x516c7*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x516c8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x516c9*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x516ca*4+0x02000000,0xdae0); +reg_write( DDR_REG_BASE +0x516cb*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x516cc*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x516cd*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x516ce*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x516cf*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x516d0*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x516d1*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x516d2*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x516d3*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x516d4*4+0x02000000,0x7204); +reg_write( DDR_REG_BASE +0x516d5*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x516d6*4+0x02000000,0xb340); +reg_write( DDR_REG_BASE +0x516d7*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x516d8*4+0x02000000,0x485); +reg_write( DDR_REG_BASE +0x516d9*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x516da*4+0x02000000,0xc4a); +reg_write( DDR_REG_BASE +0x516db*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516dc*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x516dd*4+0x02000000,0xf6a); +reg_write( DDR_REG_BASE +0x516de*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516df*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x516e0*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x516e1*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x516e2*4+0x02000000,0xb990); +reg_write( DDR_REG_BASE +0x516e3*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x516e4*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x516e5*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x516e6*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x516e7*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x516e8*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x516e9*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x516ea*4+0x02000000,0xd02); +reg_write( DDR_REG_BASE +0x516eb*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516ec*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x516ed*4+0x02000000,0xd90c); +reg_write( DDR_REG_BASE +0x516ee*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x516ef*4+0x02000000,0xb98d); +reg_write( DDR_REG_BASE +0x516f0*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x516f1*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x516f2*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x516f3*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x516f4*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x516f5*4+0x02000000,0xcee); +reg_write( DDR_REG_BASE +0x516f6*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516f7*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x516f8*4+0x02000000,0xf16); +reg_write( DDR_REG_BASE +0x516f9*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516fa*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x516fb*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x516fc*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x516fd*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x516fe*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x516ff*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51700*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51701*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51702*4+0x02000000,0xcd2); +reg_write( DDR_REG_BASE +0x51703*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51704*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51705*4+0x02000000,0xd850); +reg_write( DDR_REG_BASE +0x51706*4+0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x51707*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51708*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x51709*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5170a*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5170b*4+0x02000000,0xe048); +reg_write( DDR_REG_BASE +0x5170c*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x5170d*4+0x02000000,0x1804); +reg_write( DDR_REG_BASE +0x5170e*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x5170f*4+0x02000000,0x2440); +reg_write( DDR_REG_BASE +0x51710*4+0x02000000,0x3e80); +reg_write( DDR_REG_BASE +0x51711*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x51712*4+0x02000000,0x6c1); +reg_write( DDR_REG_BASE +0x51713*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x51714*4+0x02000000,0x782b); +reg_write( DDR_REG_BASE +0x51715*4+0x02000000,0xf264); +reg_write( DDR_REG_BASE +0x51716*4+0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x51717*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51718*4+0x02000000,0xc66); +reg_write( DDR_REG_BASE +0x51719*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5171a*4+0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x5171b*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5171c*4+0x02000000,0xaa6); +reg_write( DDR_REG_BASE +0x5171d*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5171e*4+0x02000000,0xd91e); +reg_write( DDR_REG_BASE +0x5171f*4+0x02000000,0x2440); +reg_write( DDR_REG_BASE +0x51720*4+0x02000000,0x3d80); +reg_write( DDR_REG_BASE +0x51721*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x51722*4+0x02000000,0x6cb); +reg_write( DDR_REG_BASE +0x51723*4+0x02000000,0xc08e); +reg_write( DDR_REG_BASE +0x51724*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x51725*4+0x02000000,0x6cd); +reg_write( DDR_REG_BASE +0x51726*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x51727*4+0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x51728*4+0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x51729*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5172a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5172b*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x5172c*4+0x02000000,0x7a34); +reg_write( DDR_REG_BASE +0x5172d*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x5172e*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5172f*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51730*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51731*4+0x02000000,0x54); +reg_write( DDR_REG_BASE +0x51732*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51733*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51734*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x51735*4+0x02000000,0xbe9); +reg_write( DDR_REG_BASE +0x51736*4+0x02000000,0x9065); +reg_write( DDR_REG_BASE +0x51737*4+0x02000000,0xc28f); +reg_write( DDR_REG_BASE +0x51738*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51739*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5173a*4+0x02000000,0xf034); +reg_write( DDR_REG_BASE +0x5173b*4+0x02000000,0x23f4); +reg_write( DDR_REG_BASE +0x5173c*4+0x02000000,0x34c); +reg_write( DDR_REG_BASE +0x5173d*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x5173e*4+0x02000000,0x7bb4); +reg_write( DDR_REG_BASE +0x5173f*4+0x02000000,0xbc80); +reg_write( DDR_REG_BASE +0x51740*4+0x02000000,0xb380); +reg_write( DDR_REG_BASE +0x51741*4+0x02000000,0xe886); +reg_write( DDR_REG_BASE +0x51742*4+0x02000000,0xc08f); +reg_write( DDR_REG_BASE +0x51743*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x51744*4+0x02000000,0x340); +reg_write( DDR_REG_BASE +0x51745*4+0x02000000,0xe80f); +reg_write( DDR_REG_BASE +0x51746*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x51747*4+0x02000000,0x340e); +reg_write( DDR_REG_BASE +0x51748*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51749*4+0x02000000,0x7e16); +reg_write( DDR_REG_BASE +0x5174a*4+0x02000000,0x6638); +reg_write( DDR_REG_BASE +0x5174b*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x5174c*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5174d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5174e*4+0x02000000,0x7a8); +reg_write( DDR_REG_BASE +0x5174f*4+0x02000000,0xa8a0); +reg_write( DDR_REG_BASE +0x51750*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x51751*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x51752*4+0x02000000,0xe817); +reg_write( DDR_REG_BASE +0x51753*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x51754*4+0x02000000,0x340e); +reg_write( DDR_REG_BASE +0x51755*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51756*4+0x02000000,0x7e16); +reg_write( DDR_REG_BASE +0x51757*4+0x02000000,0x6658); +reg_write( DDR_REG_BASE +0x51758*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x51759*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5175a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5175b*4+0x02000000,0x788); +reg_write( DDR_REG_BASE +0x5175c*4+0x02000000,0xa8a0); +reg_write( DDR_REG_BASE +0x5175d*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x5175e*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x5175f*4+0x02000000,0xe88f); +reg_write( DDR_REG_BASE +0x51760*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51761*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x51762*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51763*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51764*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51765*4+0x02000000,0x7404); +reg_write( DDR_REG_BASE +0x51766*4+0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x51767*4+0x02000000,0xb380); +reg_write( DDR_REG_BASE +0x51768*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x51769*4+0x02000000,0xc08f); +reg_write( DDR_REG_BASE +0x5176a*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x5176b*4+0x02000000,0x340); +reg_write( DDR_REG_BASE +0x5176c*4+0x02000000,0xe867); +reg_write( DDR_REG_BASE +0x5176d*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x5176e*4+0x02000000,0xb9b); +reg_write( DDR_REG_BASE +0x5176f*4+0x02000000,0x9365); +reg_write( DDR_REG_BASE +0x51770*4+0x02000000,0xc398); +reg_write( DDR_REG_BASE +0x51771*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51772*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51773*4+0x02000000,0x9c4); +reg_write( DDR_REG_BASE +0x51774*4+0x02000000,0xb96); +reg_write( DDR_REG_BASE +0x51775*4+0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x51776*4+0x02000000,0xb06); +reg_write( DDR_REG_BASE +0x51777*4+0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x51778*4+0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x51779*4+0x02000000,0x7277); +reg_write( DDR_REG_BASE +0x5177a*4+0x02000000,0x408); +reg_write( DDR_REG_BASE +0x5177b*4+0x02000000,0xffc5); +reg_write( DDR_REG_BASE +0x5177c*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5177d*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5177e*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x5177f*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51780*4+0x02000000,0x7114); +reg_write( DDR_REG_BASE +0x51781*4+0x02000000,0x3f6); +reg_write( DDR_REG_BASE +0x51782*4+0x02000000,0xffce); +reg_write( DDR_REG_BASE +0x51783*4+0x02000000,0xf01a); +reg_write( DDR_REG_BASE +0x51784*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x51785*4+0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x51786*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51787*4+0x02000000,0xe913); +reg_write( DDR_REG_BASE +0x51788*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51789*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5178a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5178b*4+0x02000000,0x19); +reg_write( DDR_REG_BASE +0x5178c*4+0x02000000,0xe88d); +reg_write( DDR_REG_BASE +0x5178d*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x5178e*4+0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x5178f*4+0x02000000,0x301); +reg_write( DDR_REG_BASE +0x51790*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x51791*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51792*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51793*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x51794*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51795*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51796*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51797*4+0x02000000,0x154); +reg_write( DDR_REG_BASE +0x51798*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51799*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x5179a*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5179b*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x5179c*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x5179d*4+0x02000000,0x8d1); +reg_write( DDR_REG_BASE +0x5179e*4+0x02000000,0x82b4); +reg_write( DDR_REG_BASE +0x5179f*4+0x02000000,0xc198); +reg_write( DDR_REG_BASE +0x517a0*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x517a1*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x517a2*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x517a3*4+0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x517a4*4+0x02000000,0xe808); +reg_write( DDR_REG_BASE +0x517a5*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x517a6*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x517a7*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x517a8*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x517a9*4+0x02000000,0xb8e3); +reg_write( DDR_REG_BASE +0x517aa*4+0x02000000,0x89c); +reg_write( DDR_REG_BASE +0x517ab*4+0x02000000,0xff41); +reg_write( DDR_REG_BASE +0x517ac*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x517ad*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x517ae*4+0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x517af*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x517b0*4+0x02000000,0xe048); +reg_write( DDR_REG_BASE +0x517b1*4+0x02000000,0x9ae); +reg_write( DDR_REG_BASE +0x517b2*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x517b3*4+0x02000000,0xc193); +reg_write( DDR_REG_BASE +0x517b4*4+0x02000000,0xc0bd); +reg_write( DDR_REG_BASE +0x517b5*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x517b6*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x517b7*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x517b8*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x517b9*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x517ba*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x517bb*4+0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x517bc*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x517bd*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x517be*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x517bf*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x517c0*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x517c1*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x517c2*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x517c3*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x517c4*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x517c5*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x517c6*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x517c7*4+0x02000000,0xc1a3); +reg_write( DDR_REG_BASE +0x517c8*4+0x02000000,0x4648); +reg_write( DDR_REG_BASE +0x517c9*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x517ca*4+0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x517cb*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x517cc*4+0x02000000,0xf031); +reg_write( DDR_REG_BASE +0x517cd*4+0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x517ce*4+0x02000000,0x3401); +reg_write( DDR_REG_BASE +0x517cf*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x517d0*4+0x02000000,0x7956); +reg_write( DDR_REG_BASE +0x517d1*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x517d2*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x517d3*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x517d4*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x517d5*4+0x02000000,0x7a8); +reg_write( DDR_REG_BASE +0x517d6*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x517d7*4+0x02000000,0xafe); +reg_write( DDR_REG_BASE +0x517d8*4+0x02000000,0x1a0); +reg_write( DDR_REG_BASE +0x517d9*4+0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x517da*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x517db*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x517dc*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x517dd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x517de*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x517df*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x517e0*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x517e1*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x517e2*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x517e3*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x517e4*4+0x02000000,0x254f); +reg_write( DDR_REG_BASE +0x517e5*4+0x02000000,0x1280); +reg_write( DDR_REG_BASE +0x517e6*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x517e7*4+0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x517e8*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x517e9*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x517ea*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x517eb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x517ec*4+0x02000000,0xbb8); +reg_write( DDR_REG_BASE +0x517ed*4+0x02000000,0x906); +reg_write( DDR_REG_BASE +0x517ee*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x517ef*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x517f0*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x517f1*4+0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x517f2*4+0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x517f3*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x517f4*4+0x02000000,0xb140); +reg_write( DDR_REG_BASE +0x517f5*4+0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x517f6*4+0x02000000,0xb140); +reg_write( DDR_REG_BASE +0x517f7*4+0x02000000,0x8f9); +reg_write( DDR_REG_BASE +0x517f8*4+0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x517f9*4+0x02000000,0x254f); +reg_write( DDR_REG_BASE +0x517fa*4+0x02000000,0x1242); +reg_write( DDR_REG_BASE +0x517fb*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x517fc*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x517fd*4+0x02000000,0x2779); +reg_write( DDR_REG_BASE +0x517fe*4+0x02000000,0x1042); +reg_write( DDR_REG_BASE +0x517ff*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x51800*4+0x02000000,0x2214); +reg_write( DDR_REG_BASE +0x51801*4+0x02000000,0x6c0); +reg_write( DDR_REG_BASE +0x51802*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x51803*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51804*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51805*4+0x02000000,0x784); +reg_write( DDR_REG_BASE +0x51806*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51807*4+0x02000000,0x88f); +reg_write( DDR_REG_BASE +0x51808*4+0x02000000,0x8044); +reg_write( DDR_REG_BASE +0x51809*4+0x02000000,0xc0a3); +reg_write( DDR_REG_BASE +0x5180a*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x5180b*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x5180c*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5180d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5180e*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5180f*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51810*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51811*4+0x02000000,0xc1a2); +reg_write( DDR_REG_BASE +0x51812*4+0x02000000,0x4728); +reg_write( DDR_REG_BASE +0x51813*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x51814*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x51815*4+0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x51816*4+0x02000000,0xc341); +reg_write( DDR_REG_BASE +0x51817*4+0x02000000,0xdbe); +reg_write( DDR_REG_BASE +0x51818*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x51819*4+0x02000000,0x4358); +reg_write( DDR_REG_BASE +0x5181a*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5181b*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x5181c*4+0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x5181d*4+0x02000000,0x17c0); +reg_write( DDR_REG_BASE +0x5181e*4+0x02000000,0xe805); +reg_write( DDR_REG_BASE +0x5181f*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x51820*4+0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x51821*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x51822*4+0x02000000,0x7dbb); +reg_write( DDR_REG_BASE +0x51823*4+0x02000000,0xb15); +reg_write( DDR_REG_BASE +0x51824*4+0x02000000,0x3031); +reg_write( DDR_REG_BASE +0x51825*4+0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x51826*4+0x02000000,0x110d); +reg_write( DDR_REG_BASE +0x51827*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x51828*4+0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x51829*4+0x02000000,0xd36); +reg_write( DDR_REG_BASE +0x5182a*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5182b*4+0x02000000,0xdabf); +reg_write( DDR_REG_BASE +0x5182c*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5182d*4+0x02000000,0x250f); +reg_write( DDR_REG_BASE +0x5182e*4+0x02000000,0x139b); +reg_write( DDR_REG_BASE +0x5182f*4+0x02000000,0xe887); +reg_write( DDR_REG_BASE +0x51830*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x51831*4+0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x51832*4+0x02000000,0xd22); +reg_write( DDR_REG_BASE +0x51833*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51834*4+0x02000000,0xda7f); +reg_write( DDR_REG_BASE +0x51835*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51836*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51837*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51838*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51839*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x5183a*4+0x02000000,0x164d); +reg_write( DDR_REG_BASE +0x5183b*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5183c*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x5183d*4+0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x5183e*4+0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x5183f*4+0x02000000,0xdff); +reg_write( DDR_REG_BASE +0x51840*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x51841*4+0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x51842*4+0x02000000,0x60f8); +reg_write( DDR_REG_BASE +0x51843*4+0x02000000,0x60b9); +reg_write( DDR_REG_BASE +0x51844*4+0x02000000,0xfb6); +reg_write( DDR_REG_BASE +0x51845*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x51846*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x51847*4+0x02000000,0x6c7); +reg_write( DDR_REG_BASE +0x51848*4+0x02000000,0x862); +reg_write( DDR_REG_BASE +0x51849*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x5184a*4+0x02000000,0x86a); +reg_write( DDR_REG_BASE +0x5184b*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x5184c*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x5184d*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x5184e*4+0x02000000,0xdb6); +reg_write( DDR_REG_BASE +0x5184f*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x51850*4+0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x51851*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51852*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51853*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51854*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51855*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x51856*4+0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x51857*4+0x02000000,0x60f8); +reg_write( DDR_REG_BASE +0x51858*4+0x02000000,0x60b8); +reg_write( DDR_REG_BASE +0x51859*4+0x02000000,0x1003); +reg_write( DDR_REG_BASE +0x5185a*4+0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x5185b*4+0x02000000,0x783d); +reg_write( DDR_REG_BASE +0x5185c*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5185d*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5185e*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5185f*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x51860*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x51861*4+0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x51862*4+0x02000000,0x20c5); +reg_write( DDR_REG_BASE +0x51863*4+0x02000000,0x4ab); +reg_write( DDR_REG_BASE +0x51864*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51865*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x51866*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x51867*4+0x02000000,0x22); +reg_write( DDR_REG_BASE +0x51868*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x51869*4+0x02000000,0x91a); +reg_write( DDR_REG_BASE +0x5186a*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x5186b*4+0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x5186c*4+0x02000000,0xc0a2); +reg_write( DDR_REG_BASE +0x5186d*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x5186e*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x5186f*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51870*4+0x02000000,0x7a1b); +reg_write( DDR_REG_BASE +0x51871*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51872*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51873*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51874*4+0x02000000,0x1c); +reg_write( DDR_REG_BASE +0x51875*4+0x02000000,0xbac4); +reg_write( DDR_REG_BASE +0x51876*4+0x02000000,0xea05); +reg_write( DDR_REG_BASE +0x51877*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x51878*4+0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x51879*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x5187a*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5187b*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x5187c*4+0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x5187d*4+0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x5187e*4+0x02000000,0xea05); +reg_write( DDR_REG_BASE +0x5187f*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x51880*4+0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x51881*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x51882*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51883*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x51884*4+0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x51885*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51886*4+0x02000000,0xc0e2); +reg_write( DDR_REG_BASE +0x51887*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51888*4+0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x51889*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5188a*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5188b*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x5188c*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x5188d*4+0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x5188e*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5188f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51890*4+0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x51891*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x51892*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51893*4+0x02000000,0x86); +reg_write( DDR_REG_BASE +0x51894*4+0x02000000,0x9240); +reg_write( DDR_REG_BASE +0x51895*4+0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x51896*4+0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x51897*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51898*4+0x02000000,0xfe86); +reg_write( DDR_REG_BASE +0x51899*4+0x02000000,0x22c4); +reg_write( DDR_REG_BASE +0x5189a*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x5189b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5189c*4+0x02000000,0xbfff); +reg_write( DDR_REG_BASE +0x5189d*4+0x02000000,0xf203); +reg_write( DDR_REG_BASE +0x5189e*4+0x02000000,0xba8e); +reg_write( DDR_REG_BASE +0x5189f*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x518a0*4+0x02000000,0xb340); +reg_write( DDR_REG_BASE +0x518a1*4+0x02000000,0xf01d); +reg_write( DDR_REG_BASE +0x518a2*4+0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x518a3*4+0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x518a4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x518a5*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x518a6*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x518a7*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x518a8*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x518a9*4+0x02000000,0x4a); +reg_write( DDR_REG_BASE +0x518aa*4+0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x518ab*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x518ac*4+0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x518ad*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x518ae*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x518af*4+0x02000000,0xe80b); +reg_write( DDR_REG_BASE +0x518b0*4+0x02000000,0x9340); +reg_write( DDR_REG_BASE +0x518b1*4+0x02000000,0x2114); +reg_write( DDR_REG_BASE +0x518b2*4+0x02000000,0x34c); +reg_write( DDR_REG_BASE +0x518b3*4+0x02000000,0xb440); +reg_write( DDR_REG_BASE +0x518b4*4+0x02000000,0x2204); +reg_write( DDR_REG_BASE +0x518b5*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x518b6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x518b7*4+0x02000000,0xfbff); +reg_write( DDR_REG_BASE +0x518b8*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x518b9*4+0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x518ba*4+0x02000000,0x342); +reg_write( DDR_REG_BASE +0x518bb*4+0x02000000,0xb340); +reg_write( DDR_REG_BASE +0x518bc*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x518bd*4+0x02000000,0xdcd); +reg_write( DDR_REG_BASE +0x518be*4+0x02000000,0x9294); +reg_write( DDR_REG_BASE +0x518bf*4+0x02000000,0xc4c2); +reg_write( DDR_REG_BASE +0x518c0*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x518c1*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x518c2*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x518c3*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x518c4*4+0x02000000,0x7cf); +reg_write( DDR_REG_BASE +0x518c5*4+0x02000000,0xdd24); +reg_write( DDR_REG_BASE +0x518c6*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x518c7*4+0x02000000,0xbd9f); +reg_write( DDR_REG_BASE +0x518c8*4+0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x518c9*4+0x02000000,0xe007); +reg_write( DDR_REG_BASE +0x518ca*4+0x02000000,0x7a1d); +reg_write( DDR_REG_BASE +0x518cb*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x518cc*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x518cd*4+0x02000000,0x6a09); +reg_write( DDR_REG_BASE +0x518ce*4+0x02000000,0xa901); +reg_write( DDR_REG_BASE +0x518cf*4+0x02000000,0x1534); +reg_write( DDR_REG_BASE +0x518d0*4+0x02000000,0x108c); +reg_write( DDR_REG_BASE +0x518d1*4+0x02000000,0xec0e); +reg_write( DDR_REG_BASE +0x518d2*4+0x02000000,0xca02); +reg_write( DDR_REG_BASE +0x518d3*4+0x02000000,0x7a1d); +reg_write( DDR_REG_BASE +0x518d4*4+0x02000000,0xa942); +reg_write( DDR_REG_BASE +0x518d5*4+0x02000000,0x1533); +reg_write( DDR_REG_BASE +0x518d6*4+0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x518d7*4+0x02000000,0xe007); +reg_write( DDR_REG_BASE +0x518d8*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x518d9*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x518da*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x518db*4+0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x518dc*4+0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x518dd*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x518de*4+0x02000000,0xa942); +reg_write( DDR_REG_BASE +0x518df*4+0x02000000,0xa903); +reg_write( DDR_REG_BASE +0x518e0*4+0x02000000,0xf01e); +reg_write( DDR_REG_BASE +0x518e1*4+0x02000000,0xee05); +reg_write( DDR_REG_BASE +0x518e2*4+0x02000000,0x1533); +reg_write( DDR_REG_BASE +0x518e3*4+0x02000000,0x108f); +reg_write( DDR_REG_BASE +0x518e4*4+0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x518e5*4+0x02000000,0x8de0); +reg_write( DDR_REG_BASE +0x518e6*4+0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x518e7*4+0x02000000,0xf16); +reg_write( DDR_REG_BASE +0x518e8*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x518e9*4+0x02000000,0x796f); +reg_write( DDR_REG_BASE +0x518ea*4+0x02000000,0xe804); +reg_write( DDR_REG_BASE +0x518eb*4+0x02000000,0x6f07); +reg_write( DDR_REG_BASE +0x518ec*4+0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x518ed*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x518ee*4+0x02000000,0x4f1f); +reg_write( DDR_REG_BASE +0x518ef*4+0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x518f0*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x518f1*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x518f2*4+0x02000000,0x2314); +reg_write( DDR_REG_BASE +0x518f3*4+0x02000000,0x380); +reg_write( DDR_REG_BASE +0x518f4*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x518f5*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x518f6*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x518f7*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x518f8*4+0x02000000,0x784); +reg_write( DDR_REG_BASE +0x518f9*4+0x02000000,0xa820); +reg_write( DDR_REG_BASE +0x518fa*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x518fb*4+0x02000000,0xecf); +reg_write( DDR_REG_BASE +0x518fc*4+0x02000000,0x9094); +reg_write( DDR_REG_BASE +0x518fd*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x518fe*4+0x02000000,0xbfb); +reg_write( DDR_REG_BASE +0x518ff*4+0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x51900*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x51901*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51902*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51903*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51904*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51905*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x51906*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51907*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x51908*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x51909*4+0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x5190a*4+0x02000000,0x17c0); +reg_write( DDR_REG_BASE +0x5190b*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x5190c*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x5190d*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x5190e*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x5190f*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x51910*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51911*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51912*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51913*4+0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x51914*4+0x02000000,0x817); +reg_write( DDR_REG_BASE +0x51915*4+0x02000000,0x70); +reg_write( DDR_REG_BASE +0x51916*4+0x02000000,0x4748); +reg_write( DDR_REG_BASE +0x51917*4+0x02000000,0x73ad); +reg_write( DDR_REG_BASE +0x51918*4+0x02000000,0xe88f); +reg_write( DDR_REG_BASE +0x51919*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5191a*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5191b*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5191c*4+0x02000000,0x25); +reg_write( DDR_REG_BASE +0x5191d*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x5191e*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x5191f*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51920*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51921*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51922*4+0x02000000,0x58); +reg_write( DDR_REG_BASE +0x51923*4+0x02000000,0x72ad); +reg_write( DDR_REG_BASE +0x51924*4+0x02000000,0x790b); +reg_write( DDR_REG_BASE +0x51925*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51926*4+0x02000000,0xf212); +reg_write( DDR_REG_BASE +0x51927*4+0x02000000,0xc42); +reg_write( DDR_REG_BASE +0x51928*4+0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x51929*4+0x02000000,0x8c6); +reg_write( DDR_REG_BASE +0x5192a*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5192b*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x5192c*4+0x02000000,0xb5a); +reg_write( DDR_REG_BASE +0x5192d*4+0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x5192e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5192f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51930*4+0x02000000,0x7d8); +reg_write( DDR_REG_BASE +0x51931*4+0x02000000,0x8020); +reg_write( DDR_REG_BASE +0x51932*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x51933*4+0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x51934*4+0x02000000,0xdb6); +reg_write( DDR_REG_BASE +0x51935*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51936*4+0x02000000,0x43e1); +reg_write( DDR_REG_BASE +0x51937*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51938*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x51939*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x5193a*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5193b*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5193c*4+0x02000000,0x4833); +reg_write( DDR_REG_BASE +0x5193d*4+0x02000000,0x4910); +reg_write( DDR_REG_BASE +0x5193e*4+0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x5193f*4+0x02000000,0x2348); +reg_write( DDR_REG_BASE +0x51940*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x51941*4+0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x51942*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51943*4+0x02000000,0x7b6e); +reg_write( DDR_REG_BASE +0x51944*4+0x02000000,0x780e); +reg_write( DDR_REG_BASE +0x51945*4+0x02000000,0x2309); +reg_write( DDR_REG_BASE +0x51946*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51947*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x51948*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51949*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5194a*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x5194b*4+0x02000000,0x956); +reg_write( DDR_REG_BASE +0x5194c*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x5194d*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x5194e*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x5194f*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51950*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51951*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51952*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51953*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51954*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x51955*4+0x02000000,0x1e8); +reg_write( DDR_REG_BASE +0x51956*4+0x02000000,0x9020); +reg_write( DDR_REG_BASE +0x51957*4+0x02000000,0x2059); +reg_write( DDR_REG_BASE +0x51958*4+0x02000000,0xf40); +reg_write( DDR_REG_BASE +0x51959*4+0x02000000,0x7724); +reg_write( DDR_REG_BASE +0x5195a*4+0x02000000,0x7930); +reg_write( DDR_REG_BASE +0x5195b*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x5195c*4+0x02000000,0x2155); +reg_write( DDR_REG_BASE +0x5195d*4+0x02000000,0xc0d); +reg_write( DDR_REG_BASE +0x5195e*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x5195f*4+0x02000000,0xe); +reg_write( DDR_REG_BASE +0x51960*4+0x02000000,0x7d05); +reg_write( DDR_REG_BASE +0x51961*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51962*4+0x02000000,0x111b); +reg_write( DDR_REG_BASE +0x51963*4+0x02000000,0x95e0); +reg_write( DDR_REG_BASE +0x51964*4+0x02000000,0x83a); +reg_write( DDR_REG_BASE +0x51965*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51966*4+0x02000000,0xd896); +reg_write( DDR_REG_BASE +0x51967*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51968*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51969*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5196a*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5196b*4+0x02000000,0x6822); +reg_write( DDR_REG_BASE +0x5196c*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5196d*4+0x02000000,0xb8e0); +reg_write( DDR_REG_BASE +0x5196e*4+0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x5196f*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51970*4+0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x51971*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51972*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51973*4+0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x51974*4+0x02000000,0x2304); +reg_write( DDR_REG_BASE +0x51975*4+0x02000000,0x305b); +reg_write( DDR_REG_BASE +0x51976*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51977*4+0x02000000,0x6c0); +reg_write( DDR_REG_BASE +0x51978*4+0x02000000,0x79e4); +reg_write( DDR_REG_BASE +0x51979*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x5197a*4+0x02000000,0x2145); +reg_write( DDR_REG_BASE +0x5197b*4+0x02000000,0x3c0); +reg_write( DDR_REG_BASE +0x5197c*4+0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x5197d*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x5197e*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x5197f*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51980*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51981*4+0x02000000,0x7101); +reg_write( DDR_REG_BASE +0x51982*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51983*4+0x02000000,0x6); +reg_write( DDR_REG_BASE +0x51984*4+0x02000000,0x790c); +reg_write( DDR_REG_BASE +0x51985*4+0x02000000,0x2985); +reg_write( DDR_REG_BASE +0x51986*4+0x02000000,0x41f); +reg_write( DDR_REG_BASE +0x51987*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x51988*4+0x02000000,0x6901); +reg_write( DDR_REG_BASE +0x51989*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5198a*4+0x02000000,0x2042); +reg_write( DDR_REG_BASE +0x5198b*4+0x02000000,0x701); +reg_write( DDR_REG_BASE +0x5198c*4+0x02000000,0x939); +reg_write( DDR_REG_BASE +0x5198d*4+0x02000000,0x454); +reg_write( DDR_REG_BASE +0x5198e*4+0x02000000,0x889); +reg_write( DDR_REG_BASE +0x5198f*4+0x02000000,0xc30); +reg_write( DDR_REG_BASE +0x51990*4+0x02000000,0xd91a); +reg_write( DDR_REG_BASE +0x51991*4+0x02000000,0x885); +reg_write( DDR_REG_BASE +0x51992*4+0x02000000,0xd70); +reg_write( DDR_REG_BASE +0x51993*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x51994*4+0x02000000,0x87d); +reg_write( DDR_REG_BASE +0x51995*4+0x02000000,0xf30); +reg_write( DDR_REG_BASE +0x51996*4+0x02000000,0xd918); +reg_write( DDR_REG_BASE +0x51997*4+0x02000000,0xe0c5); +reg_write( DDR_REG_BASE +0x51998*4+0x02000000,0xf227); +reg_write( DDR_REG_BASE +0x51999*4+0x02000000,0xe0d0); +reg_write( DDR_REG_BASE +0x5199a*4+0x02000000,0xf227); +reg_write( DDR_REG_BASE +0x5199b*4+0x02000000,0xe0e0); +reg_write( DDR_REG_BASE +0x5199c*4+0x02000000,0xf227); +reg_write( DDR_REG_BASE +0x5199d*4+0x02000000,0xe0f8); +reg_write( DDR_REG_BASE +0x5199e*4+0x02000000,0xf227); +reg_write( DDR_REG_BASE +0x5199f*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x519a0*4+0x02000000,0x8c03); +reg_write( DDR_REG_BASE +0x519a1*4+0x02000000,0x722c); +reg_write( DDR_REG_BASE +0x519a2*4+0x02000000,0xf230); +reg_write( DDR_REG_BASE +0x519a3*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x519a4*4+0x02000000,0x8802); +reg_write( DDR_REG_BASE +0x519a5*4+0x02000000,0xf419); +reg_write( DDR_REG_BASE +0x519a6*4+0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x519a7*4+0x02000000,0xf02c); +reg_write( DDR_REG_BASE +0x519a8*4+0x02000000,0x2025); +reg_write( DDR_REG_BASE +0x519a9*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x519aa*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x519ab*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x519ac*4+0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x519ad*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x519ae*4+0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x519af*4+0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x519b0*4+0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x519b1*4+0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x519b2*4+0x02000000,0xf00b); +reg_write( DDR_REG_BASE +0x519b3*4+0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x519b4*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x519b5*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x519b6*4+0x02000000,0xf019); +reg_write( DDR_REG_BASE +0x519b7*4+0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x519b8*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x519b9*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x519ba*4+0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x519bb*4+0x02000000,0xd93f); +reg_write( DDR_REG_BASE +0x519bc*4+0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x519bd*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x519be*4+0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x519bf*4+0x02000000,0xd90b); +reg_write( DDR_REG_BASE +0x519c0*4+0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x519c1*4+0x02000000,0xd90a); +reg_write( DDR_REG_BASE +0x519c2*4+0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x519c3*4+0x02000000,0xd907); +reg_write( DDR_REG_BASE +0x519c4*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x519c5*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x519c6*4+0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x519c7*4+0x02000000,0xd93e); +reg_write( DDR_REG_BASE +0x519c8*4+0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x519c9*4+0x02000000,0xd93b); +reg_write( DDR_REG_BASE +0x519ca*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x519cb*4+0x02000000,0xd93a); +reg_write( DDR_REG_BASE +0x519cc*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x519cd*4+0x02000000,0xd91f); +reg_write( DDR_REG_BASE +0x519ce*4+0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x519cf*4+0x02000000,0xd938); +reg_write( DDR_REG_BASE +0x519d0*4+0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x519d1*4+0x02000000,0xd91b); +reg_write( DDR_REG_BASE +0x519d2*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x519d3*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x519d4*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x519d5*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x519d6*4+0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x519d7*4+0x02000000,0x265a); +reg_write( DDR_REG_BASE +0x519d8*4+0x02000000,0x3c83); +reg_write( DDR_REG_BASE +0x519d9*4+0x02000000,0x607c); +reg_write( DDR_REG_BASE +0x519da*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x519db*4+0x02000000,0x1643); +reg_write( DDR_REG_BASE +0x519dc*4+0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x519dd*4+0x02000000,0x639b); +reg_write( DDR_REG_BASE +0x519de*4+0x02000000,0x633b); +reg_write( DDR_REG_BASE +0x519df*4+0x02000000,0x8b80); +reg_write( DDR_REG_BASE +0x519e0*4+0x02000000,0x7c45); +reg_write( DDR_REG_BASE +0x519e1*4+0x02000000,0xab80); +reg_write( DDR_REG_BASE +0x519e2*4+0x02000000,0xbeb); +reg_write( DDR_REG_BASE +0x519e3*4+0x02000000,0x9094); +reg_write( DDR_REG_BASE +0x519e4*4+0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x519e5*4+0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x519e6*4+0x02000000,0xef9); +reg_write( DDR_REG_BASE +0x519e7*4+0x02000000,0xb0b4); +reg_write( DDR_REG_BASE +0x519e8*4+0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x519e9*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x519ea*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x519eb*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x519ec*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x519ed*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x519ee*4+0x02000000,0x3a0d); +reg_write( DDR_REG_BASE +0x519ef*4+0x02000000,0xe76); +reg_write( DDR_REG_BASE +0x519f0*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x519f1*4+0x02000000,0xc083); +reg_write( DDR_REG_BASE +0x519f2*4+0x02000000,0xc083); +reg_write( DDR_REG_BASE +0x519f3*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x519f4*4+0x02000000,0xfc2); +reg_write( DDR_REG_BASE +0x519f5*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x519f6*4+0x02000000,0xdac8); +reg_write( DDR_REG_BASE +0x519f7*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x519f8*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x519f9*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x519fa*4+0x02000000,0x1b); +reg_write( DDR_REG_BASE +0x519fb*4+0x02000000,0x899); +reg_write( DDR_REG_BASE +0x519fc*4+0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x519fd*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x519fe*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x519ff*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51a00*4+0x02000000,0x880e); +reg_write( DDR_REG_BASE +0x51a01*4+0x02000000,0x88d); +reg_write( DDR_REG_BASE +0x51a02*4+0x02000000,0x30); +reg_write( DDR_REG_BASE +0x51a03*4+0x02000000,0xdb4b); +reg_write( DDR_REG_BASE +0x51a04*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51a05*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a06*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51a07*4+0x02000000,0x888d); +reg_write( DDR_REG_BASE +0x51a08*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51a09*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a0a*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51a0b*4+0x02000000,0x88ac); +reg_write( DDR_REG_BASE +0x51a0c*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51a0d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a0e*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51a0f*4+0x02000000,0x88cb); +reg_write( DDR_REG_BASE +0x51a10*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51a11*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a12*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51a13*4+0x02000000,0x882a); +reg_write( DDR_REG_BASE +0x51a14*4+0x02000000,0xbb9f); +reg_write( DDR_REG_BASE +0x51a15*4+0x02000000,0x1b01); +reg_write( DDR_REG_BASE +0x51a16*4+0x02000000,0x52); +reg_write( DDR_REG_BASE +0x51a17*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51a18*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a19*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51a1a*4+0x02000000,0x88eb); +reg_write( DDR_REG_BASE +0x51a1b*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51a1c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a1d*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51a1e*4+0x02000000,0xabe0); +reg_write( DDR_REG_BASE +0x51a1f*4+0x02000000,0x884c); +reg_write( DDR_REG_BASE +0x51a20*4+0x02000000,0x279a); +reg_write( DDR_REG_BASE +0x51a21*4+0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x51a22*4+0x02000000,0x1b32); +reg_write( DDR_REG_BASE +0x51a23*4+0x02000000,0x82); +reg_write( DDR_REG_BASE +0x51a24*4+0x02000000,0xc166); +reg_write( DDR_REG_BASE +0x51a25*4+0x02000000,0x1c31); +reg_write( DDR_REG_BASE +0x51a26*4+0x02000000,0x3382); +reg_write( DDR_REG_BASE +0x51a27*4+0x02000000,0x1c4a); +reg_write( DDR_REG_BASE +0x51a28*4+0x02000000,0x3342); +reg_write( DDR_REG_BASE +0x51a29*4+0x02000000,0x1c63); +reg_write( DDR_REG_BASE +0x51a2a*4+0x02000000,0x3302); +reg_write( DDR_REG_BASE +0x51a2b*4+0x02000000,0x13b8); +reg_write( DDR_REG_BASE +0x51a2c*4+0x02000000,0x8080); +reg_write( DDR_REG_BASE +0x51a2d*4+0x02000000,0x7f25); +reg_write( DDR_REG_BASE +0x51a2e*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51a2f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a30*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51a31*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x51a32*4+0x02000000,0x18d); +reg_write( DDR_REG_BASE +0x51a33*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51a34*4+0x02000000,0x12); +reg_write( DDR_REG_BASE +0x51a35*4+0x02000000,0x310); +reg_write( DDR_REG_BASE +0x51a36*4+0x02000000,0x892d); +reg_write( DDR_REG_BASE +0x51a37*4+0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x51a38*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51a39*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a3a*4+0x02000000,0x65d8); +reg_write( DDR_REG_BASE +0x51a3b*4+0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x51a3c*4+0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x51a3d*4+0x02000000,0x1b33); +reg_write( DDR_REG_BASE +0x51a3e*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x51a3f*4+0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x51a40*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51a41*4+0x02000000,0x6e02); +reg_write( DDR_REG_BASE +0x51a42*4+0x02000000,0x60b8); +reg_write( DDR_REG_BASE +0x51a43*4+0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x51a44*4+0x02000000,0x7945); +reg_write( DDR_REG_BASE +0x51a45*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51a46*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51a47*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x51a48*4+0x02000000,0xc083); +reg_write( DDR_REG_BASE +0x51a49*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51a4a*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x51a4b*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x51a4c*4+0x02000000,0x5800); +reg_write( DDR_REG_BASE +0x51a4d*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x51a4e*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x51a4f*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x51a50*4+0x02000000,0xc4e); +reg_write( DDR_REG_BASE +0x51a51*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a52*4+0x02000000,0x9ea); +reg_write( DDR_REG_BASE +0x51a53*4+0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x51a54*4+0x02000000,0xc96); +reg_write( DDR_REG_BASE +0x51a55*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x51a56*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51a57*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51a58*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x51a59*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51a5a*4+0x02000000,0xdc); +reg_write( DDR_REG_BASE +0x51a5b*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51a5c*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51a5d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a5e*4+0x02000000,0x19); +reg_write( DDR_REG_BASE +0x51a5f*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51a60*4+0x02000000,0x2f6); +reg_write( DDR_REG_BASE +0x51a61*4+0x02000000,0x22); +reg_write( DDR_REG_BASE +0x51a62*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51a63*4+0x02000000,0x2e3); +reg_write( DDR_REG_BASE +0x51a64*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a65*4+0x02000000,0xe90b); +reg_write( DDR_REG_BASE +0x51a66*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51a67*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51a68*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a69*4+0x02000000,0x58); +reg_write( DDR_REG_BASE +0x51a6a*4+0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x51a6b*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51a6c*4+0x02000000,0xf40b); +reg_write( DDR_REG_BASE +0x51a6d*4+0x02000000,0x2cd); +reg_write( DDR_REG_BASE +0x51a6e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a6f*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51a70*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51a71*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a72*4+0x02000000,0x25); +reg_write( DDR_REG_BASE +0x51a73*4+0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x51a74*4+0x02000000,0x2bc); +reg_write( DDR_REG_BASE +0x51a75*4+0x02000000,0x21); +reg_write( DDR_REG_BASE +0x51a76*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51a77*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x51a78*4+0x02000000,0xe26); +reg_write( DDR_REG_BASE +0x51a79*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51a7a*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51a7b*4+0x02000000,0x216f); +reg_write( DDR_REG_BASE +0x51a7c*4+0x02000000,0xc3); +reg_write( DDR_REG_BASE +0x51a7d*4+0x02000000,0x1100); +reg_write( DDR_REG_BASE +0x51a7e*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x51a7f*4+0x02000000,0x89c3); +reg_write( DDR_REG_BASE +0x51a80*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51a81*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51a82*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51a83*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x51a84*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a85*4+0x02000000,0x2c8); +reg_write( DDR_REG_BASE +0x51a86*4+0x02000000,0xece); +reg_write( DDR_REG_BASE +0x51a87*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51a88*4+0x02000000,0xdaa0); +reg_write( DDR_REG_BASE +0x51a89*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51a8a*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x51a8b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a8c*4+0x02000000,0x228); +reg_write( DDR_REG_BASE +0x51a8d*4+0x02000000,0xec2); +reg_write( DDR_REG_BASE +0x51a8e*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51a8f*4+0x02000000,0xdaa0); +reg_write( DDR_REG_BASE +0x51a90*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x51a91*4+0x02000000,0x3c40); +reg_write( DDR_REG_BASE +0x51a92*4+0x02000000,0xeb6); +reg_write( DDR_REG_BASE +0x51a93*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51a94*4+0x02000000,0xdaa0); +reg_write( DDR_REG_BASE +0x51a95*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51a96*4+0x02000000,0x3e80); +reg_write( DDR_REG_BASE +0x51a97*4+0x02000000,0xeae); +reg_write( DDR_REG_BASE +0x51a98*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51a99*4+0x02000000,0xdaa0); +reg_write( DDR_REG_BASE +0x51a9a*4+0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x51a9b*4+0x02000000,0x1f8e); +reg_write( DDR_REG_BASE +0x51a9c*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x51a9d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a9e*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x51a9f*4+0x02000000,0xf064); +reg_write( DDR_REG_BASE +0x51aa0*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51aa1*4+0x02000000,0xe9a); +reg_write( DDR_REG_BASE +0x51aa2*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51aa3*4+0x02000000,0xda28); +reg_write( DDR_REG_BASE +0x51aa4*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51aa5*4+0x02000000,0x3980); +reg_write( DDR_REG_BASE +0x51aa6*4+0x02000000,0xe8e); +reg_write( DDR_REG_BASE +0x51aa7*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51aa8*4+0x02000000,0xda28); +reg_write( DDR_REG_BASE +0x51aa9*4+0x02000000,0xc09c); +reg_write( DDR_REG_BASE +0x51aaa*4+0x02000000,0xe86); +reg_write( DDR_REG_BASE +0x51aab*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51aac*4+0x02000000,0xda28); +reg_write( DDR_REG_BASE +0x51aad*4+0x02000000,0x2355); +reg_write( DDR_REG_BASE +0x51aae*4+0x02000000,0x3800); +reg_write( DDR_REG_BASE +0x51aaf*4+0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x51ab0*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51ab1*4+0x02000000,0x3c01); +reg_write( DDR_REG_BASE +0x51ab2*4+0x02000000,0xa8a); +reg_write( DDR_REG_BASE +0x51ab3*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51ab4*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x51ab5*4+0x02000000,0x2355); +reg_write( DDR_REG_BASE +0x51ab6*4+0x02000000,0x38c0); +reg_write( DDR_REG_BASE +0x51ab7*4+0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x51ab8*4+0x02000000,0xa7e); +reg_write( DDR_REG_BASE +0x51ab9*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51aba*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51abb*4+0x02000000,0x3981); +reg_write( DDR_REG_BASE +0x51abc*4+0x02000000,0x2355); +reg_write( DDR_REG_BASE +0x51abd*4+0x02000000,0x3d00); +reg_write( DDR_REG_BASE +0x51abe*4+0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x51abf*4+0x02000000,0xa72); +reg_write( DDR_REG_BASE +0x51ac0*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51ac1*4+0x02000000,0xc19c); +reg_write( DDR_REG_BASE +0x51ac2*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51ac3*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51ac4*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51ac5*4+0x02000000,0x1003); +reg_write( DDR_REG_BASE +0x51ac6*4+0x02000000,0x8b); +reg_write( DDR_REG_BASE +0x51ac7*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51ac8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51ac9*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51aca*4+0x02000000,0x8862); +reg_write( DDR_REG_BASE +0x51acb*4+0x02000000,0xf035); +reg_write( DDR_REG_BASE +0x51acc*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51acd*4+0x02000000,0x3c00); +reg_write( DDR_REG_BASE +0x51ace*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x51acf*4+0x02000000,0xde); +reg_write( DDR_REG_BASE +0x51ad0*4+0x02000000,0x94e); +reg_write( DDR_REG_BASE +0x51ad1*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51ad2*4+0x02000000,0x200a); +reg_write( DDR_REG_BASE +0x51ad3*4+0x02000000,0x780); +reg_write( DDR_REG_BASE +0x51ad4*4+0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x51ad5*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51ad6*4+0x02000000,0x3980); +reg_write( DDR_REG_BASE +0x51ad7*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x51ad8*4+0x02000000,0xcd); +reg_write( DDR_REG_BASE +0x51ad9*4+0x02000000,0xc09c); +reg_write( DDR_REG_BASE +0x51ada*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x51adb*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x51adc*4+0x02000000,0xbdc5); +reg_write( DDR_REG_BASE +0x51add*4+0x02000000,0x936); +reg_write( DDR_REG_BASE +0x51ade*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51adf*4+0x02000000,0x65fd); +reg_write( DDR_REG_BASE +0x51ae0*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x51ae1*4+0x02000000,0x3a02); +reg_write( DDR_REG_BASE +0x51ae2*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51ae3*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x51ae4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51ae5*4+0x02000000,0x2c8); +reg_write( DDR_REG_BASE +0x51ae6*4+0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x51ae7*4+0x02000000,0x7974); +reg_write( DDR_REG_BASE +0x51ae8*4+0x02000000,0xb1a0); +reg_write( DDR_REG_BASE +0x51ae9*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51aea*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x51aeb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51aec*4+0x02000000,0x228); +reg_write( DDR_REG_BASE +0x51aed*4+0x02000000,0x615c); +reg_write( DDR_REG_BASE +0x51aee*4+0x02000000,0x212f); +reg_write( DDR_REG_BASE +0x51aef*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x51af0*4+0x02000000,0x7c74); +reg_write( DDR_REG_BASE +0x51af1*4+0x02000000,0x216c); +reg_write( DDR_REG_BASE +0x51af2*4+0x02000000,0x101); +reg_write( DDR_REG_BASE +0x51af3*4+0x02000000,0xb420); +reg_write( DDR_REG_BASE +0x51af4*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x51af5*4+0x02000000,0x3c41); +reg_write( DDR_REG_BASE +0x51af6*4+0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x51af7*4+0x02000000,0x7974); +reg_write( DDR_REG_BASE +0x51af8*4+0x02000000,0xb1e0); +reg_write( DDR_REG_BASE +0x51af9*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51afa*4+0x02000000,0x3e81); +reg_write( DDR_REG_BASE +0x51afb*4+0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x51afc*4+0x02000000,0x7974); +reg_write( DDR_REG_BASE +0x51afd*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x51afe*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x51aff*4+0x02000000,0xb9d); +reg_write( DDR_REG_BASE +0x51b00*4+0x02000000,0x90c5); +reg_write( DDR_REG_BASE +0x51b01*4+0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x51b02*4+0x02000000,0xb3d); +reg_write( DDR_REG_BASE +0x51b03*4+0x02000000,0xb134); +reg_write( DDR_REG_BASE +0x51b04*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51b05*4+0x02000000,0x3c00); +reg_write( DDR_REG_BASE +0x51b06*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51b07*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51b08*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51b09*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51b0a*4+0x02000000,0xd930); +reg_write( DDR_REG_BASE +0x51b0b*4+0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x51b0c*4+0x02000000,0x2140); +reg_write( DDR_REG_BASE +0x51b0d*4+0x02000000,0xcce); +reg_write( DDR_REG_BASE +0x51b0e*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51b0f*4+0x02000000,0x2642); +reg_write( DDR_REG_BASE +0x51b10*4+0x02000000,0x1283); +reg_write( DDR_REG_BASE +0x51b11*4+0x02000000,0x2142); +reg_write( DDR_REG_BASE +0x51b12*4+0x02000000,0x280); +reg_write( DDR_REG_BASE +0x51b13*4+0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x51b14*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51b15*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51b16*4+0x02000000,0x26ca); +reg_write( DDR_REG_BASE +0x51b17*4+0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x51b18*4+0x02000000,0x4308); +reg_write( DDR_REG_BASE +0x51b19*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51b1a*4+0x02000000,0xf059); +reg_write( DDR_REG_BASE +0x51b1b*4+0x02000000,0xdab); +reg_write( DDR_REG_BASE +0x51b1c*4+0x02000000,0x12e0); +reg_write( DDR_REG_BASE +0x51b1d*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51b1e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51b1f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51b20*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51b21*4+0x02000000,0x1003); +reg_write( DDR_REG_BASE +0x51b22*4+0x02000000,0x9f); +reg_write( DDR_REG_BASE +0x51b23*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51b24*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51b25*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51b26*4+0x02000000,0x8882); +reg_write( DDR_REG_BASE +0x51b27*4+0x02000000,0xba8f); +reg_write( DDR_REG_BASE +0x51b28*4+0x02000000,0x4358); +reg_write( DDR_REG_BASE +0x51b29*4+0x02000000,0xf02e); +reg_write( DDR_REG_BASE +0x51b2a*4+0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x51b2b*4+0x02000000,0x1a0f); +reg_write( DDR_REG_BASE +0x51b2c*4+0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x51b2d*4+0x02000000,0x923); +reg_write( DDR_REG_BASE +0x51b2e*4+0x02000000,0x32); +reg_write( DDR_REG_BASE +0x51b2f*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x51b30*4+0x02000000,0x1a00); +reg_write( DDR_REG_BASE +0x51b31*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51b32*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x51b33*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51b34*4+0x02000000,0x228); +reg_write( DDR_REG_BASE +0x51b35*4+0x02000000,0x61f9); +reg_write( DDR_REG_BASE +0x51b36*4+0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x51b37*4+0x02000000,0x302); +reg_write( DDR_REG_BASE +0x51b38*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51b39*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x51b3a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51b3b*4+0x02000000,0x2c8); +reg_write( DDR_REG_BASE +0x51b3c*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x51b3d*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x51b3e*4+0x02000000,0x3c41); +reg_write( DDR_REG_BASE +0x51b3f*4+0x02000000,0x61fa); +reg_write( DDR_REG_BASE +0x51b40*4+0x02000000,0x22f4); +reg_write( DDR_REG_BASE +0x51b41*4+0x02000000,0x302); +reg_write( DDR_REG_BASE +0x51b42*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x51b43*4+0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x51b44*4+0x02000000,0x301); +reg_write( DDR_REG_BASE +0x51b45*4+0x02000000,0x7942); +reg_write( DDR_REG_BASE +0x51b46*4+0x02000000,0x2608); +reg_write( DDR_REG_BASE +0x51b47*4+0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x51b48*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51b49*4+0x02000000,0x3e81); +reg_write( DDR_REG_BASE +0x51b4a*4+0x02000000,0x673f); +reg_write( DDR_REG_BASE +0x51b4b*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51b4c*4+0x02000000,0x27f4); +reg_write( DDR_REG_BASE +0x51b4d*4+0x02000000,0x130f); +reg_write( DDR_REG_BASE +0x51b4e*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x51b4f*4+0x02000000,0x300); +reg_write( DDR_REG_BASE +0x51b50*4+0x02000000,0x212f); +reg_write( DDR_REG_BASE +0x51b51*4+0x02000000,0x6c6); +reg_write( DDR_REG_BASE +0x51b52*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x51b53*4+0x02000000,0x78e2); +reg_write( DDR_REG_BASE +0x51b54*4+0x02000000,0x2108); +reg_write( DDR_REG_BASE +0x51b55*4+0x02000000,0x1b); +reg_write( DDR_REG_BASE +0x51b56*4+0x02000000,0xfa9); +reg_write( DDR_REG_BASE +0x51b57*4+0x02000000,0xb325); +reg_write( DDR_REG_BASE +0x51b58*4+0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x51b59*4+0x02000000,0x3086); +reg_write( DDR_REG_BASE +0x51b5a*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51b5b*4+0x02000000,0x811); +reg_write( DDR_REG_BASE +0x51b5c*4+0x02000000,0x32); +reg_write( DDR_REG_BASE +0x51b5d*4+0x02000000,0x200a); +reg_write( DDR_REG_BASE +0x51b5e*4+0x02000000,0x780); +reg_write( DDR_REG_BASE +0x51b5f*4+0x02000000,0xf9e); +reg_write( DDR_REG_BASE +0x51b60*4+0x02000000,0xfe8f); +reg_write( DDR_REG_BASE +0x51b61*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x51b62*4+0x02000000,0xf1e); +reg_write( DDR_REG_BASE +0x51b63*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51b64*4+0x02000000,0x200a); +reg_write( DDR_REG_BASE +0x51b65*4+0x02000000,0x780); +reg_write( DDR_REG_BASE +0x51b66*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x51b67*4+0x02000000,0xf16); +reg_write( DDR_REG_BASE +0x51b68*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51b69*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x51b6a*4+0x02000000,0x6c6); +reg_write( DDR_REG_BASE +0x51b6b*4+0x02000000,0x1b01); +reg_write( DDR_REG_BASE +0x51b6c*4+0x02000000,0x52); +reg_write( DDR_REG_BASE +0x51b6d*4+0x02000000,0x1e01); +reg_write( DDR_REG_BASE +0x51b6e*4+0x02000000,0x1012); +reg_write( DDR_REG_BASE +0x51b6f*4+0x02000000,0x77a5); +reg_write( DDR_REG_BASE +0x51b70*4+0x02000000,0xd57); +reg_write( DDR_REG_BASE +0x51b71*4+0x02000000,0x9013); +reg_write( DDR_REG_BASE +0x51b72*4+0x02000000,0x7765); +reg_write( DDR_REG_BASE +0x51b73*4+0x02000000,0xbfd); +reg_write( DDR_REG_BASE +0x51b74*4+0x02000000,0x9033); +reg_write( DDR_REG_BASE +0x51b75*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x51b76*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51b77*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51b78*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51b79*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51b7a*4+0x02000000,0xd92c); +reg_write( DDR_REG_BASE +0x51b7b*4+0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x51b7c*4+0x02000000,0x2140); +reg_write( DDR_REG_BASE +0x51b7d*4+0x02000000,0xccb); +reg_write( DDR_REG_BASE +0x51b7e*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51b7f*4+0x02000000,0x2342); +reg_write( DDR_REG_BASE +0x51b80*4+0x02000000,0x1100); +reg_write( DDR_REG_BASE +0x51b81*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51b82*4+0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x51b83*4+0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x51b84*4+0x02000000,0x690c); +reg_write( DDR_REG_BASE +0x51b85*4+0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x51b86*4+0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x51b87*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51b88*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51b89*4+0x02000000,0xf042); +reg_write( DDR_REG_BASE +0x51b8a*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51b8b*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51b8c*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51b8d*4+0x02000000,0x1003); +reg_write( DDR_REG_BASE +0x51b8e*4+0x02000000,0x9e); +reg_write( DDR_REG_BASE +0x51b8f*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51b90*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51b91*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51b92*4+0x02000000,0x8842); +reg_write( DDR_REG_BASE +0x51b93*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51b94*4+0x02000000,0xb88f); +reg_write( DDR_REG_BASE +0x51b95*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x51b96*4+0x02000000,0xf01e); +reg_write( DDR_REG_BASE +0x51b97*4+0x02000000,0xc602); +reg_write( DDR_REG_BASE +0x51b98*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x51b99*4+0x02000000,0x3a0c); +reg_write( DDR_REG_BASE +0x51b9a*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x51b9b*4+0x02000000,0x3c4d); +reg_write( DDR_REG_BASE +0x51b9c*4+0x02000000,0x265a); +reg_write( DDR_REG_BASE +0x51b9d*4+0x02000000,0x1a0e); +reg_write( DDR_REG_BASE +0x51b9e*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51b9f*4+0x02000000,0x3e8f); +reg_write( DDR_REG_BASE +0x51ba0*4+0x02000000,0x6599); +reg_write( DDR_REG_BASE +0x51ba1*4+0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x51ba2*4+0x02000000,0x9f); +reg_write( DDR_REG_BASE +0x51ba3*4+0x02000000,0x67d9); +reg_write( DDR_REG_BASE +0x51ba4*4+0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x51ba5*4+0x02000000,0x81); +reg_write( DDR_REG_BASE +0x51ba6*4+0x02000000,0x64fc); +reg_write( DDR_REG_BASE +0x51ba7*4+0x02000000,0x65dd); +reg_write( DDR_REG_BASE +0x51ba8*4+0x02000000,0x2102); +reg_write( DDR_REG_BASE +0x51ba9*4+0x02000000,0x7c1); +reg_write( DDR_REG_BASE +0x51baa*4+0x02000000,0x2308); +reg_write( DDR_REG_BASE +0x51bab*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x51bac*4+0x02000000,0x24f4); +reg_write( DDR_REG_BASE +0x51bad*4+0x02000000,0x108c); +reg_write( DDR_REG_BASE +0x51bae*4+0x02000000,0x25f4); +reg_write( DDR_REG_BASE +0x51baf*4+0x02000000,0x1083); +reg_write( DDR_REG_BASE +0x51bb0*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x51bb1*4+0x02000000,0x7b82); +reg_write( DDR_REG_BASE +0x51bb2*4+0x02000000,0x2008); +reg_write( DDR_REG_BASE +0x51bb3*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x51bb4*4+0x02000000,0x780e); +reg_write( DDR_REG_BASE +0x51bb5*4+0x02000000,0xec7); +reg_write( DDR_REG_BASE +0x51bb6*4+0x02000000,0xb0a5); +reg_write( DDR_REG_BASE +0x51bb7*4+0x02000000,0x7b2e); +reg_write( DDR_REG_BASE +0x51bb8*4+0x02000000,0xe72); +reg_write( DDR_REG_BASE +0x51bb9*4+0x02000000,0xfe8f); +reg_write( DDR_REG_BASE +0x51bba*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x51bbb*4+0x02000000,0xe6e); +reg_write( DDR_REG_BASE +0x51bbc*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51bbd*4+0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x51bbe*4+0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x51bbf*4+0x02000000,0x7767); +reg_write( DDR_REG_BASE +0x51bc0*4+0x02000000,0x1901); +reg_write( DDR_REG_BASE +0x51bc1*4+0x02000000,0x92); +reg_write( DDR_REG_BASE +0x51bc2*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51bc3*4+0x02000000,0x1b01); +reg_write( DDR_REG_BASE +0x51bc4*4+0x02000000,0x1012); +reg_write( DDR_REG_BASE +0x51bc5*4+0x02000000,0xb8d); +reg_write( DDR_REG_BASE +0x51bc6*4+0x02000000,0xb013); +reg_write( DDR_REG_BASE +0x51bc7*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x51bc8*4+0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x51bc9*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51bca*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x51bcb*4+0x02000000,0x8f7); +reg_write( DDR_REG_BASE +0x51bcc*4+0x02000000,0x8033); +reg_write( DDR_REG_BASE +0x51bcd*4+0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x51bce*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51bcf*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51bd0*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51bd1*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51bd2*4+0x02000000,0x6901); +reg_write( DDR_REG_BASE +0x51bd3*4+0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x51bd4*4+0x02000000,0x7134); +reg_write( DDR_REG_BASE +0x51bd5*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51bd6*4+0x02000000,0x7002); +reg_write( DDR_REG_BASE +0x51bd7*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51bd8*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51bd9*4+0x02000000,0x51a); +reg_write( DDR_REG_BASE +0x51bda*4+0x02000000,0xffce); +reg_write( DDR_REG_BASE +0x51bdb*4+0x02000000,0xb62); +reg_write( DDR_REG_BASE +0x51bdc*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51bdd*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x51bde*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51bdf*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51be0*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51be1*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51be2*4+0x02000000,0xa901); +reg_write( DDR_REG_BASE +0x51be3*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51be4*4+0x02000000,0x7002); +reg_write( DDR_REG_BASE +0x51be5*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51be6*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51be7*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51be8*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51be9*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51bea*4+0x02000000,0x19); +reg_write( DDR_REG_BASE +0x51beb*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51bec*4+0x02000000,0x85c); +reg_write( DDR_REG_BASE +0x51bed*4+0x02000000,0x141); +reg_write( DDR_REG_BASE +0x51bee*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51bef*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51bf0*4+0x02000000,0xe174); +reg_write( DDR_REG_BASE +0x51bf1*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51bf2*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51bf3*4+0x02000000,0xe82); +reg_write( DDR_REG_BASE +0x51bf4*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51bf5*4+0x02000000,0xb021); +reg_write( DDR_REG_BASE +0x51bf6*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x51bf7*4+0x02000000,0x3a0d); +reg_write( DDR_REG_BASE +0x51bf8*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x51bf9*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x51bfa*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51bfb*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51bfc*4+0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x51bfd*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x51bfe*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x51bff*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51c00*4+0x02000000,0x9fe); +reg_write( DDR_REG_BASE +0x51c01*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51c02*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x51c03*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x51c04*4+0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x51c05*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51c06*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51c07*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x51c08*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x51c09*4+0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x51c0a*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x51c0b*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51c0c*4+0x02000000,0xabe); +reg_write( DDR_REG_BASE +0x51c0d*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51c0e*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x51c0f*4+0x02000000,0xbec1); +reg_write( DDR_REG_BASE +0x51c10*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51c11*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x51c12*4+0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x51c13*4+0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x51c14*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51c15*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x51c16*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51c17*4+0x02000000,0xaaa); +reg_write( DDR_REG_BASE +0x51c18*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51c19*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x51c1a*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x51c1b*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51c1c*4+0x02000000,0xa5e); +reg_write( DDR_REG_BASE +0x51c1d*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51c1e*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51c1f*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x51c20*4+0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x51c21*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51c22*4+0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x51c23*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x51c24*4+0x02000000,0xd858); +reg_write( DDR_REG_BASE +0x51c25*4+0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x51c26*4+0x02000000,0x88c0); +reg_write( DDR_REG_BASE +0x51c27*4+0x02000000,0x10cd); +reg_write( DDR_REG_BASE +0x51c28*4+0x02000000,0x808d); +reg_write( DDR_REG_BASE +0x51c29*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51c2a*4+0x02000000,0x9aa); +reg_write( DDR_REG_BASE +0x51c2b*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51c2c*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x51c2d*4+0x02000000,0x2605); +reg_write( DDR_REG_BASE +0x51c2e*4+0x02000000,0x1341); +reg_write( DDR_REG_BASE +0x51c2f*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51c30*4+0x02000000,0xb9c1); +reg_write( DDR_REG_BASE +0x51c31*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x51c32*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x51c33*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51c34*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x51c35*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51c36*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x51c37*4+0x02000000,0xda09); +reg_write( DDR_REG_BASE +0x51c38*4+0x02000000,0xa66); +reg_write( DDR_REG_BASE +0x51c39*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51c3a*4+0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x51c3b*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51c3c*4+0x02000000,0xa1e); +reg_write( DDR_REG_BASE +0x51c3d*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51c3e*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51c3f*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x51c40*4+0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x51c41*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51c42*4+0x02000000,0x21aa); +reg_write( DDR_REG_BASE +0x51c43*4+0x02000000,0xc4); +reg_write( DDR_REG_BASE +0x51c44*4+0x02000000,0x911); +reg_write( DDR_REG_BASE +0x51c45*4+0x02000000,0x3f); +reg_write( DDR_REG_BASE +0x51c46*4+0x02000000,0x722c); +reg_write( DDR_REG_BASE +0x51c47*4+0x02000000,0x21ab); +reg_write( DDR_REG_BASE +0x51c48*4+0x02000000,0xc4); +reg_write( DDR_REG_BASE +0x51c49*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51c4a*4+0x02000000,0x21ab); +reg_write( DDR_REG_BASE +0x51c4b*4+0x02000000,0xc4); +reg_write( DDR_REG_BASE +0x51c4c*4+0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x51c4d*4+0x02000000,0x415); +reg_write( DDR_REG_BASE +0x51c4e*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51c4f*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x51c50*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x51c51*4+0x02000000,0x1d6); +reg_write( DDR_REG_BASE +0x51c52*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51c53*4+0x02000000,0x21aa); +reg_write( DDR_REG_BASE +0x51c54*4+0x02000000,0x104); +reg_write( DDR_REG_BASE +0x51c55*4+0x02000000,0x7b32); +reg_write( DDR_REG_BASE +0x51c56*4+0x02000000,0xb19); +reg_write( DDR_REG_BASE +0x51c57*4+0x02000000,0x25); +reg_write( DDR_REG_BASE +0x51c58*4+0x02000000,0x24aa); +reg_write( DDR_REG_BASE +0x51c59*4+0x02000000,0x1144); +reg_write( DDR_REG_BASE +0x51c5a*4+0x02000000,0x22aa); +reg_write( DDR_REG_BASE +0x51c5b*4+0x02000000,0x104); +reg_write( DDR_REG_BASE +0x51c5c*4+0x02000000,0x9fd); +reg_write( DDR_REG_BASE +0x51c5d*4+0x02000000,0x8084); +reg_write( DDR_REG_BASE +0x51c5e*4+0x02000000,0x7862); +reg_write( DDR_REG_BASE +0x51c5f*4+0x02000000,0x24aa); +reg_write( DDR_REG_BASE +0x51c60*4+0x02000000,0x1144); +reg_write( DDR_REG_BASE +0x51c61*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x51c62*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51c63*4+0x02000000,0x21aa); +reg_write( DDR_REG_BASE +0x51c64*4+0x02000000,0x104); +reg_write( DDR_REG_BASE +0x51c65*4+0x02000000,0x7110); +reg_write( DDR_REG_BASE +0x51c66*4+0x02000000,0x20e1); +reg_write( DDR_REG_BASE +0x51c67*4+0x02000000,0x7c6); +reg_write( DDR_REG_BASE +0x51c68*4+0x02000000,0x22aa); +reg_write( DDR_REG_BASE +0x51c69*4+0x02000000,0x144); +reg_write( DDR_REG_BASE +0x51c6a*4+0x02000000,0xcf3); +reg_write( DDR_REG_BASE +0x51c6b*4+0x02000000,0x9080); +reg_write( DDR_REG_BASE +0x51c6c*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51c6d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51c6e*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x51c6f*4+0x02000000,0x866); +reg_write( DDR_REG_BASE +0x51c70*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51c71*4+0x02000000,0xfa6); +reg_write( DDR_REG_BASE +0x51c72*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x51c73*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x51c74*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51c75*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51c76*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x51c77*4+0x02000000,0xf5a); +reg_write( DDR_REG_BASE +0x51c78*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x51c79*4+0x02000000,0xf96); +reg_write( DDR_REG_BASE +0x51c7a*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51c7b*4+0x02000000,0xd814); +reg_write( DDR_REG_BASE +0x51c7c*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x51c7d*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51c7e*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x51c7f*4+0x02000000,0x846); +reg_write( DDR_REG_BASE +0x51c80*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51c81*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51c82*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51c83*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x51c84*4+0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x51c85*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51c86*4+0x02000000,0xe915); +reg_write( DDR_REG_BASE +0x51c87*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51c88*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51c89*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51c8a*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51c8b*4+0x02000000,0x923); +reg_write( DDR_REG_BASE +0x51c8c*4+0x02000000,0xdf); +reg_write( DDR_REG_BASE +0x51c8d*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51c8e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51c8f*4+0x02000000,0x7c8); +reg_write( DDR_REG_BASE +0x51c90*4+0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x51c91*4+0x02000000,0x917); +reg_write( DDR_REG_BASE +0x51c92*4+0x02000000,0x134); +reg_write( DDR_REG_BASE +0x51c93*4+0x02000000,0x216c); +reg_write( DDR_REG_BASE +0x51c94*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x51c95*4+0x02000000,0x2809); +reg_write( DDR_REG_BASE +0x51c96*4+0x02000000,0x8042); +reg_write( DDR_REG_BASE +0x51c97*4+0x02000000,0xf208); +reg_write( DDR_REG_BASE +0x51c98*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51c99*4+0x02000000,0x7842); +reg_write( DDR_REG_BASE +0x51c9a*4+0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x51c9b*4+0x02000000,0x809); +reg_write( DDR_REG_BASE +0x51c9c*4+0x02000000,0x115); +reg_write( DDR_REG_BASE +0x51c9d*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x51c9e*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x51c9f*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51ca0*4+0x02000000,0x246f); +reg_write( DDR_REG_BASE +0x51ca1*4+0x02000000,0x1343); +reg_write( DDR_REG_BASE +0x51ca2*4+0x02000000,0x9460); +reg_write( DDR_REG_BASE +0x51ca3*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x51ca4*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x51ca5*4+0x02000000,0x2a05); +reg_write( DDR_REG_BASE +0x51ca6*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x51ca7*4+0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x51ca8*4+0x02000000,0x8480); +reg_write( DDR_REG_BASE +0x51ca9*4+0x02000000,0x817); +reg_write( DDR_REG_BASE +0x51caa*4+0x02000000,0xf84); +reg_write( DDR_REG_BASE +0x51cab*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x51cac*4+0x02000000,0xd41); +reg_write( DDR_REG_BASE +0x51cad*4+0x02000000,0x2885); +reg_write( DDR_REG_BASE +0x51cae*4+0x02000000,0xa0f); +reg_write( DDR_REG_BASE +0x51caf*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x51cb0*4+0x02000000,0xc2); +reg_write( DDR_REG_BASE +0x51cb1*4+0x02000000,0x2a85); +reg_write( DDR_REG_BASE +0x51cb2*4+0x02000000,0x41f); +reg_write( DDR_REG_BASE +0x51cb3*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x51cb4*4+0x02000000,0x6a01); +reg_write( DDR_REG_BASE +0x51cb5*4+0x02000000,0x6941); +reg_write( DDR_REG_BASE +0x51cb6*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51cb7*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51cb8*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x51cb9*4+0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x51cba*4+0x02000000,0xe90c); +reg_write( DDR_REG_BASE +0x51cbb*4+0x02000000,0x14fb); +reg_write( DDR_REG_BASE +0x51cbc*4+0x02000000,0x9081); +reg_write( DDR_REG_BASE +0x51cbd*4+0x02000000,0x915); +reg_write( DDR_REG_BASE +0x51cbe*4+0x02000000,0xdf); +reg_write( DDR_REG_BASE +0x51cbf*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51cc0*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51cc1*4+0x02000000,0x7c8); +reg_write( DDR_REG_BASE +0x51cc2*4+0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x51cc3*4+0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x51cc4*4+0x02000000,0x22da); +reg_write( DDR_REG_BASE +0x51cc5*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x51cc6*4+0x02000000,0x7210); +reg_write( DDR_REG_BASE +0x51cc7*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x51cc8*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x51cc9*4+0x02000000,0x8d); +reg_write( DDR_REG_BASE +0x51cca*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51ccb*4+0x02000000,0xece); +reg_write( DDR_REG_BASE +0x51ccc*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51ccd*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x51cce*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51ccf*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51cd0*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51cd1*4+0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x51cd2*4+0x02000000,0xb9c3); +reg_write( DDR_REG_BASE +0x51cd3*4+0x02000000,0xdd58); +reg_write( DDR_REG_BASE +0x51cd4*4+0x02000000,0x1a02); +reg_write( DDR_REG_BASE +0x51cd5*4+0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x51cd6*4+0x02000000,0xbd9f); +reg_write( DDR_REG_BASE +0x51cd7*4+0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x51cd8*4+0x02000000,0xe80b); +reg_write( DDR_REG_BASE +0x51cd9*4+0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x51cda*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x51cdb*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51cdc*4+0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x51cdd*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51cde*4+0x02000000,0x57); +reg_write( DDR_REG_BASE +0x51cdf*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x51ce0*4+0x02000000,0xe00); +reg_write( DDR_REG_BASE +0x51ce1*4+0x02000000,0x621e); +reg_write( DDR_REG_BASE +0x51ce2*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x51ce3*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51ce4*4+0x02000000,0x708e); +reg_write( DDR_REG_BASE +0x51ce5*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51ce6*4+0x02000000,0x24); +reg_write( DDR_REG_BASE +0x51ce7*4+0x02000000,0xe96); +reg_write( DDR_REG_BASE +0x51ce8*4+0x02000000,0xff0f); +reg_write( DDR_REG_BASE +0x51ce9*4+0x02000000,0x79cf); +reg_write( DDR_REG_BASE +0x51cea*4+0x02000000,0x7b3d); +reg_write( DDR_REG_BASE +0x51ceb*4+0x02000000,0x7a3d); +reg_write( DDR_REG_BASE +0x51cec*4+0x02000000,0x2653); +reg_write( DDR_REG_BASE +0x51ced*4+0x02000000,0x907e); +reg_write( DDR_REG_BASE +0x51cee*4+0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x51cef*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51cf0*4+0x02000000,0x23c0); +reg_write( DDR_REG_BASE +0x51cf1*4+0x02000000,0x62); +reg_write( DDR_REG_BASE +0x51cf2*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51cf3*4+0x02000000,0x2653); +reg_write( DDR_REG_BASE +0x51cf4*4+0x02000000,0x9081); +reg_write( DDR_REG_BASE +0x51cf5*4+0x02000000,0xb8c3); +reg_write( DDR_REG_BASE +0x51cf6*4+0x02000000,0x22c0); +reg_write( DDR_REG_BASE +0x51cf7*4+0x02000000,0x62); +reg_write( DDR_REG_BASE +0x51cf8*4+0x02000000,0x1a03); +reg_write( DDR_REG_BASE +0x51cf9*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x51cfa*4+0x02000000,0x1a05); +reg_write( DDR_REG_BASE +0x51cfb*4+0x02000000,0x30c2); +reg_write( DDR_REG_BASE +0x51cfc*4+0x02000000,0x1a07); +reg_write( DDR_REG_BASE +0x51cfd*4+0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x51cfe*4+0x02000000,0x1a04); +reg_write( DDR_REG_BASE +0x51cff*4+0x02000000,0x3082); +reg_write( DDR_REG_BASE +0x51d00*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x51d01*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d02*4+0x02000000,0x53); +reg_write( DDR_REG_BASE +0x51d03*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x51d04*4+0x02000000,0xcb6); +reg_write( DDR_REG_BASE +0x51d05*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d06*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d07*4+0x02000000,0x276f); +reg_write( DDR_REG_BASE +0x51d08*4+0x02000000,0x10c3); +reg_write( DDR_REG_BASE +0x51d09*4+0x02000000,0x8f00); +reg_write( DDR_REG_BASE +0x51d0a*4+0x02000000,0xb8e2); +reg_write( DDR_REG_BASE +0x51d0b*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51d0c*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x51d0d*4+0x02000000,0xe1); +reg_write( DDR_REG_BASE +0x51d0e*4+0x02000000,0x1a08); +reg_write( DDR_REG_BASE +0x51d0f*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x51d10*4+0x02000000,0x1724); +reg_write( DDR_REG_BASE +0x51d11*4+0x02000000,0x1082); +reg_write( DDR_REG_BASE +0x51d12*4+0x02000000,0x170f); +reg_write( DDR_REG_BASE +0x51d13*4+0x02000000,0x1481); +reg_write( DDR_REG_BASE +0x51d14*4+0x02000000,0x2742); +reg_write( DDR_REG_BASE +0x51d15*4+0x02000000,0x1280); +reg_write( DDR_REG_BASE +0x51d16*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51d17*4+0x02000000,0x8d60); +reg_write( DDR_REG_BASE +0x51d18*4+0x02000000,0x97c0); +reg_write( DDR_REG_BASE +0x51d19*4+0x02000000,0x8f82); +reg_write( DDR_REG_BASE +0x51d1a*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x51d1b*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x51d1c*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d1d*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d1e*4+0x02000000,0x55); +reg_write( DDR_REG_BASE +0x51d1f*4+0x02000000,0x6); +reg_write( DDR_REG_BASE +0x51d20*4+0x02000000,0xc441); +reg_write( DDR_REG_BASE +0x51d21*4+0x02000000,0xc7e); +reg_write( DDR_REG_BASE +0x51d22*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d23*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x51d24*4+0x02000000,0x8f08); +reg_write( DDR_REG_BASE +0x51d25*4+0x02000000,0xe808); +reg_write( DDR_REG_BASE +0x51d26*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d27*4+0x02000000,0x5a); +reg_write( DDR_REG_BASE +0x51d28*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51d29*4+0x02000000,0xc6e); +reg_write( DDR_REG_BASE +0x51d2a*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d2b*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d2c*4+0x02000000,0xde32); +reg_write( DDR_REG_BASE +0x51d2d*4+0x02000000,0xbe9f); +reg_write( DDR_REG_BASE +0x51d2e*4+0x02000000,0x1601); +reg_write( DDR_REG_BASE +0x51d2f*4+0x02000000,0x1483); +reg_write( DDR_REG_BASE +0x51d30*4+0x02000000,0x16d1); +reg_write( DDR_REG_BASE +0x51d31*4+0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x51d32*4+0x02000000,0x1601); +reg_write( DDR_REG_BASE +0x51d33*4+0x02000000,0x148c); +reg_write( DDR_REG_BASE +0x51d34*4+0x02000000,0x1602); +reg_write( DDR_REG_BASE +0x51d35*4+0x02000000,0x1481); +reg_write( DDR_REG_BASE +0x51d36*4+0x02000000,0x1601); +reg_write( DDR_REG_BASE +0x51d37*4+0x02000000,0x1480); +reg_write( DDR_REG_BASE +0x51d38*4+0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51d39*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51d3a*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51d3b*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d3c*4+0x02000000,0x5b); +reg_write( DDR_REG_BASE +0x51d3d*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51d3e*4+0x02000000,0xc42); +reg_write( DDR_REG_BASE +0x51d3f*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d40*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d41*4+0x02000000,0x1601); +reg_write( DDR_REG_BASE +0x51d42*4+0x02000000,0x1483); +reg_write( DDR_REG_BASE +0x51d43*4+0x02000000,0x8e21); +reg_write( DDR_REG_BASE +0x51d44*4+0x02000000,0x8e04); +reg_write( DDR_REG_BASE +0x51d45*4+0x02000000,0x16cc); +reg_write( DDR_REG_BASE +0x51d46*4+0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x51d47*4+0x02000000,0x8e80); +reg_write( DDR_REG_BASE +0x51d48*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51d49*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51d4a*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d4b*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d4c*4+0x02000000,0x5c); +reg_write( DDR_REG_BASE +0x51d4d*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51d4e*4+0x02000000,0xc22); +reg_write( DDR_REG_BASE +0x51d4f*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d50*4+0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51d51*4+0x02000000,0x8f08); +reg_write( DDR_REG_BASE +0x51d52*4+0x02000000,0x8b5); +reg_write( DDR_REG_BASE +0x51d53*4+0x02000000,0x11); +reg_write( DDR_REG_BASE +0x51d54*4+0x02000000,0x8f15); +reg_write( DDR_REG_BASE +0x51d55*4+0x02000000,0x831); +reg_write( DDR_REG_BASE +0x51d56*4+0x02000000,0x7e); +reg_write( DDR_REG_BASE +0x51d57*4+0x02000000,0xdf3e); +reg_write( DDR_REG_BASE +0x51d58*4+0x02000000,0xf840); +reg_write( DDR_REG_BASE +0x51d59*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51d5a*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51d5b*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d5c*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d5d*4+0x02000000,0x5d); +reg_write( DDR_REG_BASE +0x51d5e*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51d5f*4+0x02000000,0xc02); +reg_write( DDR_REG_BASE +0x51d60*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d61*4+0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51d62*4+0x02000000,0xf841); +reg_write( DDR_REG_BASE +0x51d63*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51d64*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51d65*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d66*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d67*4+0x02000000,0x5e); +reg_write( DDR_REG_BASE +0x51d68*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51d69*4+0x02000000,0xbee); +reg_write( DDR_REG_BASE +0x51d6a*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d6b*4+0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51d6c*4+0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x51d6d*4+0x02000000,0x833); +reg_write( DDR_REG_BASE +0x51d6e*4+0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x51d6f*4+0x02000000,0xdf65); +reg_write( DDR_REG_BASE +0x51d70*4+0x02000000,0xf834); +reg_write( DDR_REG_BASE +0x51d71*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51d72*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51d73*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d74*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d75*4+0x02000000,0x5f); +reg_write( DDR_REG_BASE +0x51d76*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51d77*4+0x02000000,0xbd2); +reg_write( DDR_REG_BASE +0x51d78*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d79*4+0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51d7a*4+0x02000000,0xf835); +reg_write( DDR_REG_BASE +0x51d7b*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51d7c*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51d7d*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d7e*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d7f*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x51d80*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51d81*4+0x02000000,0xbbe); +reg_write( DDR_REG_BASE +0x51d82*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d83*4+0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51d84*4+0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x51d85*4+0x02000000,0x851); +reg_write( DDR_REG_BASE +0x51d86*4+0x02000000,0x7e); +reg_write( DDR_REG_BASE +0x51d87*4+0x02000000,0xdd71); +reg_write( DDR_REG_BASE +0x51d88*4+0x02000000,0xbd9f); +reg_write( DDR_REG_BASE +0x51d89*4+0x02000000,0x1501); +reg_write( DDR_REG_BASE +0x51d8a*4+0x02000000,0x1483); +reg_write( DDR_REG_BASE +0x51d8b*4+0x02000000,0x1501); +reg_write( DDR_REG_BASE +0x51d8c*4+0x02000000,0x148c); +reg_write( DDR_REG_BASE +0x51d8d*4+0x02000000,0x1502); +reg_write( DDR_REG_BASE +0x51d8e*4+0x02000000,0x1481); +reg_write( DDR_REG_BASE +0x51d8f*4+0x02000000,0x1501); +reg_write( DDR_REG_BASE +0x51d90*4+0x02000000,0x1480); +reg_write( DDR_REG_BASE +0x51d91*4+0x02000000,0x16cc); +reg_write( DDR_REG_BASE +0x51d92*4+0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x51d93*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51d94*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51d95*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d96*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d97*4+0x02000000,0x61); +reg_write( DDR_REG_BASE +0x51d98*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51d99*4+0x02000000,0xb8e); +reg_write( DDR_REG_BASE +0x51d9a*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d9b*4+0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51d9c*4+0x02000000,0x1501); +reg_write( DDR_REG_BASE +0x51d9d*4+0x02000000,0x1483); +reg_write( DDR_REG_BASE +0x51d9e*4+0x02000000,0x8d21); +reg_write( DDR_REG_BASE +0x51d9f*4+0x02000000,0x8d04); +reg_write( DDR_REG_BASE +0x51da0*4+0x02000000,0x16cc); +reg_write( DDR_REG_BASE +0x51da1*4+0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x51da2*4+0x02000000,0x8d80); +reg_write( DDR_REG_BASE +0x51da3*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51da4*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51da5*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51da6*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51da7*4+0x02000000,0x62); +reg_write( DDR_REG_BASE +0x51da8*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51da9*4+0x02000000,0xb6e); +reg_write( DDR_REG_BASE +0x51daa*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51dab*4+0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51dac*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51dad*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x51dae*4+0x02000000,0x1a0); +reg_write( DDR_REG_BASE +0x51daf*4+0x02000000,0x1802); +reg_write( DDR_REG_BASE +0x51db0*4+0x02000000,0x15); +reg_write( DDR_REG_BASE +0x51db1*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51db2*4+0x02000000,0x44); +reg_write( DDR_REG_BASE +0x51db3*4+0x02000000,0x1802); +reg_write( DDR_REG_BASE +0x51db4*4+0x02000000,0x54); +reg_write( DDR_REG_BASE +0x51db5*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51db6*4+0x02000000,0x144); +reg_write( DDR_REG_BASE +0x51db7*4+0x02000000,0x1802); +reg_write( DDR_REG_BASE +0x51db8*4+0x02000000,0x54); +reg_write( DDR_REG_BASE +0x51db9*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51dba*4+0x02000000,0x1c4); +reg_write( DDR_REG_BASE +0x51dbb*4+0x02000000,0x1804); +reg_write( DDR_REG_BASE +0x51dbc*4+0x02000000,0x54); +reg_write( DDR_REG_BASE +0x51dbd*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51dbe*4+0x02000000,0x88); +reg_write( DDR_REG_BASE +0x51dbf*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51dc0*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51dc1*4+0x02000000,0x288); +reg_write( DDR_REG_BASE +0x51dc2*4+0x02000000,0xb021); +reg_write( DDR_REG_BASE +0x51dc3*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51dc4*4+0x02000000,0x2c8); +reg_write( DDR_REG_BASE +0x51dc5*4+0x02000000,0xb022); +reg_write( DDR_REG_BASE +0x51dc6*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x51dc7*4+0x02000000,0x3cc); +reg_write( DDR_REG_BASE +0x51dc8*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51dc9*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x51dca*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x51dcb*4+0x02000000,0xe180); +reg_write( DDR_REG_BASE +0x51dcc*4+0x02000000,0xd934); +reg_write( DDR_REG_BASE +0x51dcd*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51dce*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x51dcf*4+0x02000000,0xe0ee); +reg_write( DDR_REG_BASE +0x51dd0*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51dd1*4+0x02000000,0xd4e); +reg_write( DDR_REG_BASE +0x51dd2*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51dd3*4+0x02000000,0x18fc); +reg_write( DDR_REG_BASE +0x51dd4*4+0x02000000,0x8105); +reg_write( DDR_REG_BASE +0x51dd5*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x51dd6*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51dd7*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51dd8*4+0x02000000,0xbf9f); +reg_write( DDR_REG_BASE +0x51dd9*4+0x02000000,0x1701); +reg_write( DDR_REG_BASE +0x51dda*4+0x02000000,0x1483); +reg_write( DDR_REG_BASE +0x51ddb*4+0x02000000,0x1701); +reg_write( DDR_REG_BASE +0x51ddc*4+0x02000000,0x148c); +reg_write( DDR_REG_BASE +0x51ddd*4+0x02000000,0x1702); +reg_write( DDR_REG_BASE +0x51dde*4+0x02000000,0x1481); +reg_write( DDR_REG_BASE +0x51ddf*4+0x02000000,0x1701); +reg_write( DDR_REG_BASE +0x51de0*4+0x02000000,0x1480); +reg_write( DDR_REG_BASE +0x51de1*4+0x02000000,0x16cc); +reg_write( DDR_REG_BASE +0x51de2*4+0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x51de3*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51de4*4+0x02000000,0x1701); +reg_write( DDR_REG_BASE +0x51de5*4+0x02000000,0x1483); +reg_write( DDR_REG_BASE +0x51de6*4+0x02000000,0x8f21); +reg_write( DDR_REG_BASE +0x51de7*4+0x02000000,0x8f04); +reg_write( DDR_REG_BASE +0x51de8*4+0x02000000,0x16cc); +reg_write( DDR_REG_BASE +0x51de9*4+0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x51dea*4+0x02000000,0x8f80); +reg_write( DDR_REG_BASE +0x51deb*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51dec*4+0x02000000,0x621a); +reg_write( DDR_REG_BASE +0x51ded*4+0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x51dee*4+0x02000000,0x1801); +reg_write( DDR_REG_BASE +0x51def*4+0x02000000,0x52); +reg_write( DDR_REG_BASE +0x51df0*4+0x02000000,0x8fd); +reg_write( DDR_REG_BASE +0x51df1*4+0x02000000,0x8084); +reg_write( DDR_REG_BASE +0x51df2*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51df3*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51df4*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51df5*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51df6*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51df7*4+0x02000000,0xc1a7); +reg_write( DDR_REG_BASE +0x51df8*4+0x02000000,0xda07); +reg_write( DDR_REG_BASE +0x51df9*4+0x02000000,0xba8c); +reg_write( DDR_REG_BASE +0x51dfa*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51dfb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51dfc*4+0x02000000,0x9f38); +reg_write( DDR_REG_BASE +0x51dfd*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x51dfe*4+0x02000000,0x9012); +reg_write( DDR_REG_BASE +0x51dff*4+0x02000000,0x328); +reg_write( DDR_REG_BASE +0x51e00*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51e01*4+0x02000000,0x7084); +reg_write( DDR_REG_BASE +0x51e02*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e03*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x51e04*4+0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x51e05*4+0x02000000,0xd858); +reg_write( DDR_REG_BASE +0x51e06*4+0x02000000,0xb501); +reg_write( DDR_REG_BASE +0x51e07*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51e08*4+0x02000000,0xb8); +reg_write( DDR_REG_BASE +0x51e09*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51e0a*4+0x02000000,0xaaa); +reg_write( DDR_REG_BASE +0x51e0b*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51e0c*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51e0d*4+0x02000000,0xcc20); +reg_write( DDR_REG_BASE +0x51e0e*4+0x02000000,0x9520); +reg_write( DDR_REG_BASE +0x51e0f*4+0x02000000,0x7030); +reg_write( DDR_REG_BASE +0x51e10*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51e11*4+0x02000000,0xf406); +reg_write( DDR_REG_BASE +0x51e12*4+0x02000000,0xcc21); +reg_write( DDR_REG_BASE +0x51e13*4+0x02000000,0x9521); +reg_write( DDR_REG_BASE +0x51e14*4+0x02000000,0x2038); +reg_write( DDR_REG_BASE +0x51e15*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x51e16*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51e17*4+0x02000000,0xb9); +reg_write( DDR_REG_BASE +0x51e18*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51e19*4+0x02000000,0xd22); +reg_write( DDR_REG_BASE +0x51e1a*4+0x02000000,0xfe0f); +reg_write( DDR_REG_BASE +0x51e1b*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51e1c*4+0x02000000,0x7043); +reg_write( DDR_REG_BASE +0x51e1d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e1e*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x51e1f*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51e20*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51e21*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e22*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51e23*4+0x02000000,0x1a00); +reg_write( DDR_REG_BASE +0x51e24*4+0x02000000,0x3103); +reg_write( DDR_REG_BASE +0x51e25*4+0x02000000,0x216f); +reg_write( DDR_REG_BASE +0x51e26*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x51e27*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51e28*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x51e29*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51e2a*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51e2b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51e2c*4+0x02000000,0x9126); +reg_write( DDR_REG_BASE +0x51e2d*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51e2e*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51e2f*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51e30*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51e31*4+0x02000000,0x32); +reg_write( DDR_REG_BASE +0x51e32*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x51e33*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51e34*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x51e35*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51e36*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51e37*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51e38*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51e39*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x51e3a*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51e3b*4+0x02000000,0xa46); +reg_write( DDR_REG_BASE +0x51e3c*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51e3d*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x51e3e*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51e3f*4+0x02000000,0xb8e0); +reg_write( DDR_REG_BASE +0x51e40*4+0x02000000,0x264); +reg_write( DDR_REG_BASE +0x51e41*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51e42*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51e43*4+0x02000000,0xc103); +reg_write( DDR_REG_BASE +0x51e44*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51e45*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51e46*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x51e47*4+0x02000000,0xe032); +reg_write( DDR_REG_BASE +0x51e48*4+0x02000000,0xb980); +reg_write( DDR_REG_BASE +0x51e49*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51e4a*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51e4b*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51e4c*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51e4d*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51e4e*4+0x02000000,0xe090); +reg_write( DDR_REG_BASE +0x51e4f*4+0x02000000,0xca2); +reg_write( DDR_REG_BASE +0x51e50*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51e51*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x51e52*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51e53*4+0x02000000,0x256f); +reg_write( DDR_REG_BASE +0x51e54*4+0x02000000,0x1cc3); +reg_write( DDR_REG_BASE +0x51e55*4+0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x51e56*4+0x02000000,0xe885); +reg_write( DDR_REG_BASE +0x51e57*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51e58*4+0x02000000,0x7085); +reg_write( DDR_REG_BASE +0x51e59*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51e5a*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x51e5b*4+0x02000000,0xce2); +reg_write( DDR_REG_BASE +0x51e5c*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x51e5d*4+0x02000000,0xf92); +reg_write( DDR_REG_BASE +0x51e5e*4+0x02000000,0xff0f); +reg_write( DDR_REG_BASE +0x51e5f*4+0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x51e60*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51e61*4+0x02000000,0xf4bb); +reg_write( DDR_REG_BASE +0x51e62*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51e63*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x51e64*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e65*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51e66*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51e67*4+0x02000000,0x708b); +reg_write( DDR_REG_BASE +0x51e68*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e69*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51e6a*4+0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x51e6b*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x51e6c*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51e6d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51e6e*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x51e6f*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51e70*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51e71*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51e72*4+0x02000000,0x86); +reg_write( DDR_REG_BASE +0x51e73*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51e74*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x51e75*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51e76*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51e77*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51e78*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51e79*4+0x02000000,0xb8c2); +reg_write( DDR_REG_BASE +0x51e7a*4+0x02000000,0x825); +reg_write( DDR_REG_BASE +0x51e7b*4+0x02000000,0x90); +reg_write( DDR_REG_BASE +0x51e7c*4+0x02000000,0x833); +reg_write( DDR_REG_BASE +0x51e7d*4+0x02000000,0xf1); +reg_write( DDR_REG_BASE +0x51e7e*4+0x02000000,0x238b); +reg_write( DDR_REG_BASE +0x51e7f*4+0x02000000,0x903e); +reg_write( DDR_REG_BASE +0x51e80*4+0x02000000,0xce08); +reg_write( DDR_REG_BASE +0x51e81*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51e82*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e83*4+0x02000000,0x41c); +reg_write( DDR_REG_BASE +0x51e84*4+0x02000000,0x761c); +reg_write( DDR_REG_BASE +0x51e85*4+0x02000000,0x1a03); +reg_write( DDR_REG_BASE +0x51e86*4+0x02000000,0x3398); +reg_write( DDR_REG_BASE +0x51e87*4+0x02000000,0xce0e); +reg_write( DDR_REG_BASE +0x51e88*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x51e89*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e8a*4+0x02000000,0x434); +reg_write( DDR_REG_BASE +0x51e8b*4+0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x51e8c*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51e8d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e8e*4+0x02000000,0x418); +reg_write( DDR_REG_BASE +0x51e8f*4+0x02000000,0x1a03); +reg_write( DDR_REG_BASE +0x51e90*4+0x02000000,0x3398); +reg_write( DDR_REG_BASE +0x51e91*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x51e92*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e93*4+0x02000000,0x430); +reg_write( DDR_REG_BASE +0x51e94*4+0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x51e95*4+0x02000000,0x238b); +reg_write( DDR_REG_BASE +0x51e96*4+0x02000000,0x903e); +reg_write( DDR_REG_BASE +0x51e97*4+0x02000000,0xce05); +reg_write( DDR_REG_BASE +0x51e98*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51e99*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e9a*4+0x02000000,0x410); +reg_write( DDR_REG_BASE +0x51e9b*4+0x02000000,0x761c); +reg_write( DDR_REG_BASE +0x51e9c*4+0x02000000,0xce0b); +reg_write( DDR_REG_BASE +0x51e9d*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x51e9e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e9f*4+0x02000000,0x428); +reg_write( DDR_REG_BASE +0x51ea0*4+0x02000000,0x1a03); +reg_write( DDR_REG_BASE +0x51ea1*4+0x02000000,0x3398); +reg_write( DDR_REG_BASE +0x51ea2*4+0x02000000,0x771c); +reg_write( DDR_REG_BASE +0x51ea3*4+0x02000000,0x1a09); +reg_write( DDR_REG_BASE +0x51ea4*4+0x02000000,0x33d8); +reg_write( DDR_REG_BASE +0x51ea5*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51ea6*4+0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x51ea7*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51ea8*4+0x02000000,0xc); +reg_write( DDR_REG_BASE +0x51ea9*4+0x02000000,0x238b); +reg_write( DDR_REG_BASE +0x51eaa*4+0x02000000,0x903e); +reg_write( DDR_REG_BASE +0x51eab*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x51eac*4+0x02000000,0xf9b); +reg_write( DDR_REG_BASE +0x51ead*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51eae*4+0x02000000,0x86a0); +reg_write( DDR_REG_BASE +0x51eaf*4+0x02000000,0xf20b); +reg_write( DDR_REG_BASE +0x51eb0*4+0x02000000,0x233c); +reg_write( DDR_REG_BASE +0x51eb1*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x51eb2*4+0x02000000,0xa6); +reg_write( DDR_REG_BASE +0x51eb3*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x51eb4*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51eb5*4+0x02000000,0x141); +reg_write( DDR_REG_BASE +0x51eb6*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51eb7*4+0x02000000,0xbe6); +reg_write( DDR_REG_BASE +0x51eb8*4+0x02000000,0xfe0f); +reg_write( DDR_REG_BASE +0x51eb9*4+0x02000000,0x222f); +reg_write( DDR_REG_BASE +0x51eba*4+0x02000000,0x6c2); +reg_write( DDR_REG_BASE +0x51ebb*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51ebc*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51ebd*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51ebe*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51ebf*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51ec0*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51ec1*4+0x02000000,0xed95); +reg_write( DDR_REG_BASE +0x51ec2*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51ec3*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x51ec4*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x51ec5*4+0x02000000,0x6611); +reg_write( DDR_REG_BASE +0x51ec6*4+0x02000000,0x6710); +reg_write( DDR_REG_BASE +0x51ec7*4+0x02000000,0x4a10); +reg_write( DDR_REG_BASE +0x51ec8*4+0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x51ec9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51eca*4+0x02000000,0x2805); +reg_write( DDR_REG_BASE +0x51ecb*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x51ecc*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51ecd*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51ece*4+0x02000000,0xfe80); +reg_write( DDR_REG_BASE +0x51ecf*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51ed0*4+0x02000000,0x2089); +reg_write( DDR_REG_BASE +0x51ed1*4+0x02000000,0xfc1); +reg_write( DDR_REG_BASE +0x51ed2*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x51ed3*4+0x02000000,0x19e0); +reg_write( DDR_REG_BASE +0x51ed4*4+0x02000000,0x8004); +reg_write( DDR_REG_BASE +0x51ed5*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x51ed6*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x51ed7*4+0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x51ed8*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x51ed9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51eda*4+0x02000000,0x2b05); +reg_write( DDR_REG_BASE +0x51edb*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x51edc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51edd*4+0x02000000,0xfa00); +reg_write( DDR_REG_BASE +0x51ede*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x51edf*4+0x02000000,0x821); +reg_write( DDR_REG_BASE +0x51ee0*4+0x02000000,0x1fe); +reg_write( DDR_REG_BASE +0x51ee1*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x51ee2*4+0x02000000,0x2200); +reg_write( DDR_REG_BASE +0x51ee3*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51ee4*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x51ee5*4+0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x51ee6*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x51ee7*4+0x02000000,0x8d47); +reg_write( DDR_REG_BASE +0x51ee8*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x51ee9*4+0x02000000,0xf685); +reg_write( DDR_REG_BASE +0x51eea*4+0x02000000,0x2885); +reg_write( DDR_REG_BASE +0x51eeb*4+0x02000000,0xd07); +reg_write( DDR_REG_BASE +0x51eec*4+0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x51eed*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51eee*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51eef*4+0x02000000,0x2089); +reg_write( DDR_REG_BASE +0x51ef0*4+0x02000000,0xfc1); +reg_write( DDR_REG_BASE +0x51ef1*4+0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x51ef2*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x51ef3*4+0x02000000,0xc105); +reg_write( DDR_REG_BASE +0x51ef4*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x51ef5*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x51ef6*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x51ef7*4+0x02000000,0xe164); +reg_write( DDR_REG_BASE +0x51ef8*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51ef9*4+0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x51efa*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51efb*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x51efc*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51efd*4+0x02000000,0x164); +reg_write( DDR_REG_BASE +0x51efe*4+0x02000000,0xb8c1); +reg_write( DDR_REG_BASE +0x51eff*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x51f00*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x51f01*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51f02*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51f03*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51f04*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51f05*4+0x02000000,0x86); +reg_write( DDR_REG_BASE +0x51f06*4+0x02000000,0x952); +reg_write( DDR_REG_BASE +0x51f07*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51f08*4+0x02000000,0x90c0); +reg_write( DDR_REG_BASE +0x51f09*4+0x02000000,0x8e2); +reg_write( DDR_REG_BASE +0x51f0a*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51f0b*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x51f0c*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51f0d*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51f0e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51f0f*4+0x02000000,0x1f); +reg_write( DDR_REG_BASE +0x51f10*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x51f11*4+0x02000000,0x2111); +reg_write( DDR_REG_BASE +0x51f12*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51f13*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51f14*4+0x02000000,0x26cf); +reg_write( DDR_REG_BASE +0x51f15*4+0x02000000,0x1021); +reg_write( DDR_REG_BASE +0x51f16*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51f17*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51f18*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51f19*4+0x02000000,0xfe86); +reg_write( DDR_REG_BASE +0x51f1a*4+0x02000000,0xb0c0); +reg_write( DDR_REG_BASE +0x51f1b*4+0x02000000,0xb2a); +reg_write( DDR_REG_BASE +0x51f1c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51f1d*4+0x02000000,0xb4a); +reg_write( DDR_REG_BASE +0x51f1e*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x51f1f*4+0x02000000,0x8fe); +reg_write( DDR_REG_BASE +0x51f20*4+0x02000000,0xfe8f); +reg_write( DDR_REG_BASE +0x51f21*4+0x02000000,0xc52); +reg_write( DDR_REG_BASE +0x51f22*4+0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x51f23*4+0x02000000,0xca04); +reg_write( DDR_REG_BASE +0x51f24*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51f25*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x51f26*4+0x02000000,0xf033); +reg_write( DDR_REG_BASE +0x51f27*4+0x02000000,0x245a); +reg_write( DDR_REG_BASE +0x51f28*4+0x02000000,0x149e); +reg_write( DDR_REG_BASE +0x51f29*4+0x02000000,0x2600); +reg_write( DDR_REG_BASE +0x51f2a*4+0x02000000,0x3f83); +reg_write( DDR_REG_BASE +0x51f2b*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51f2c*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x51f2d*4+0x02000000,0xb341); +reg_write( DDR_REG_BASE +0x51f2e*4+0x02000000,0xf028); +reg_write( DDR_REG_BASE +0x51f2f*4+0x02000000,0x241a); +reg_write( DDR_REG_BASE +0x51f30*4+0x02000000,0x1f81); +reg_write( DDR_REG_BASE +0x51f31*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51f32*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x51f33*4+0x02000000,0x79a5); +reg_write( DDR_REG_BASE +0x51f34*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x51f35*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x51f36*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51f37*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51f38*4+0x02000000,0x140); +reg_write( DDR_REG_BASE +0x51f39*4+0x02000000,0x9120); +reg_write( DDR_REG_BASE +0x51f3a*4+0x02000000,0x7e2f); +reg_write( DDR_REG_BASE +0x51f3b*4+0x02000000,0xd13); +reg_write( DDR_REG_BASE +0x51f3c*4+0x02000000,0x13a1); +reg_write( DDR_REG_BASE +0x51f3d*4+0x02000000,0xbec4); +reg_write( DDR_REG_BASE +0x51f3e*4+0x02000000,0x8b22); +reg_write( DDR_REG_BASE +0x51f3f*4+0x02000000,0x210f); +reg_write( DDR_REG_BASE +0x51f40*4+0x02000000,0x341); +reg_write( DDR_REG_BASE +0x51f41*4+0x02000000,0xab22); +reg_write( DDR_REG_BASE +0x51f42*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x51f43*4+0x02000000,0x8b23); +reg_write( DDR_REG_BASE +0x51f44*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x51f45*4+0x02000000,0xab23); +reg_write( DDR_REG_BASE +0x51f46*4+0x02000000,0x792f); +reg_write( DDR_REG_BASE +0x51f47*4+0x02000000,0x2614); +reg_write( DDR_REG_BASE +0x51f48*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x51f49*4+0x02000000,0x2100); +reg_write( DDR_REG_BASE +0x51f4a*4+0x02000000,0xf8f); +reg_write( DDR_REG_BASE +0x51f4b*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51f4c*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x51f4d*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51f4e*4+0x02000000,0xafa3); +reg_write( DDR_REG_BASE +0x51f4f*4+0x02000000,0xee06); +reg_write( DDR_REG_BASE +0x51f50*4+0x02000000,0xbe61); +reg_write( DDR_REG_BASE +0x51f51*4+0x02000000,0xe01); +reg_write( DDR_REG_BASE +0x51f52*4+0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x51f53*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x51f54*4+0x02000000,0xaf22); +reg_write( DDR_REG_BASE +0x51f55*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x51f56*4+0x02000000,0xdb3); +reg_write( DDR_REG_BASE +0x51f57*4+0x02000000,0x9214); +reg_write( DDR_REG_BASE +0x51f58*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x51f59*4+0x02000000,0xc9f); +reg_write( DDR_REG_BASE +0x51f5a*4+0x02000000,0x9024); +reg_write( DDR_REG_BASE +0x51f5b*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x51f5c*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51f5d*4+0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x51f5e*4+0x02000000,0x33f); +reg_write( DDR_REG_BASE +0x51f5f*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51f60*4+0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x51f61*4+0x02000000,0xbd2); +reg_write( DDR_REG_BASE +0x51f62*4+0x02000000,0xfe0f); +reg_write( DDR_REG_BASE +0x51f63*4+0x02000000,0xabe); +reg_write( DDR_REG_BASE +0x51f64*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51f65*4+0x02000000,0xd80d); +reg_write( DDR_REG_BASE +0x51f66*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51f67*4+0x02000000,0xfc6); +reg_write( DDR_REG_BASE +0x51f68*4+0x02000000,0x180); +reg_write( DDR_REG_BASE +0x51f69*4+0x02000000,0xee2); +reg_write( DDR_REG_BASE +0x51f6a*4+0x02000000,0xfe4f); +reg_write( DDR_REG_BASE +0x51f6b*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51f6c*4+0x02000000,0x7003); +reg_write( DDR_REG_BASE +0x51f6d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51f6e*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x51f6f*4+0x02000000,0xaa6); +reg_write( DDR_REG_BASE +0x51f70*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51f71*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51f72*4+0x02000000,0xca04); +reg_write( DDR_REG_BASE +0x51f73*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x51f74*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x51f75*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x51f76*4+0x02000000,0xf019); +reg_write( DDR_REG_BASE +0x51f77*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51f78*4+0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x51f79*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x51f7a*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51f7b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51f7c*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x51f7d*4+0x02000000,0x2300); +reg_write( DDR_REG_BASE +0x51f7e*4+0x02000000,0x1f8d); +reg_write( DDR_REG_BASE +0x51f7f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51f80*4+0x02000000,0x7f0); +reg_write( DDR_REG_BASE +0x51f81*4+0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x51f82*4+0x02000000,0x7945); +reg_write( DDR_REG_BASE +0x51f83*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x51f84*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x51f85*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51f86*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51f87*4+0x02000000,0x140); +reg_write( DDR_REG_BASE +0x51f88*4+0x02000000,0x9180); +reg_write( DDR_REG_BASE +0x51f89*4+0x02000000,0xad80); +reg_write( DDR_REG_BASE +0x51f8a*4+0x02000000,0xb140); +reg_write( DDR_REG_BASE +0x51f8b*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x51f8c*4+0x02000000,0xadb); +reg_write( DDR_REG_BASE +0x51f8d*4+0x02000000,0x8214); +reg_write( DDR_REG_BASE +0x51f8e*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x51f8f*4+0x02000000,0xbd3); +reg_write( DDR_REG_BASE +0x51f90*4+0x02000000,0x8024); +reg_write( DDR_REG_BASE +0x51f91*4+0x02000000,0x2616); +reg_write( DDR_REG_BASE +0x51f92*4+0x02000000,0x30cb); +reg_write( DDR_REG_BASE +0x51f93*4+0x02000000,0xbde); +reg_write( DDR_REG_BASE +0x51f94*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51f95*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51f96*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51f97*4+0x02000000,0x813); +reg_write( DDR_REG_BASE +0x51f98*4+0x02000000,0xbe); +reg_write( DDR_REG_BASE +0x51f99*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51f9a*4+0x02000000,0xbaa); +reg_write( DDR_REG_BASE +0x51f9b*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x51f9c*4+0x02000000,0xa4a); +reg_write( DDR_REG_BASE +0x51f9d*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51f9e*4+0x02000000,0x720c); +reg_write( DDR_REG_BASE +0x51f9f*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51fa0*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x51fa1*4+0x02000000,0x808e); +reg_write( DDR_REG_BASE +0x51fa2*4+0x02000000,0xf207); +reg_write( DDR_REG_BASE +0x51fa3*4+0x02000000,0xb9a); +reg_write( DDR_REG_BASE +0x51fa4*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51fa5*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51fa6*4+0x02000000,0xa36); +reg_write( DDR_REG_BASE +0x51fa7*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51fa8*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51fa9*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51faa*4+0x02000000,0x81b); +reg_write( DDR_REG_BASE +0x51fab*4+0x02000000,0x21e); +reg_write( DDR_REG_BASE +0x51fac*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51fad*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51fae*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51faf*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51fb0*4+0x02000000,0xe887); +reg_write( DDR_REG_BASE +0x51fb1*4+0x02000000,0xb7e); +reg_write( DDR_REG_BASE +0x51fb2*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51fb3*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x51fb4*4+0x02000000,0xa1a); +reg_write( DDR_REG_BASE +0x51fb5*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51fb6*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51fb7*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51fb8*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x51fb9*4+0x02000000,0x820d); +reg_write( DDR_REG_BASE +0x51fba*4+0x02000000,0xf207); +reg_write( DDR_REG_BASE +0x51fbb*4+0x02000000,0xb6a); +reg_write( DDR_REG_BASE +0x51fbc*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51fbd*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x51fbe*4+0x02000000,0xa06); +reg_write( DDR_REG_BASE +0x51fbf*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51fc0*4+0x02000000,0xd8fd); +reg_write( DDR_REG_BASE +0x51fc1*4+0x02000000,0xee08); +reg_write( DDR_REG_BASE +0x51fc2*4+0x02000000,0xb5a); +reg_write( DDR_REG_BASE +0x51fc3*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51fc4*4+0x02000000,0x720c); +reg_write( DDR_REG_BASE +0x51fc5*4+0x02000000,0x9fa); +reg_write( DDR_REG_BASE +0x51fc6*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51fc7*4+0x02000000,0xd8fe); +reg_write( DDR_REG_BASE +0x51fc8*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51fc9*4+0x02000000,0x813); +reg_write( DDR_REG_BASE +0x51fca*4+0x02000000,0x13e); +reg_write( DDR_REG_BASE +0x51fcb*4+0x02000000,0x760c); +reg_write( DDR_REG_BASE +0x51fcc*4+0x02000000,0xb46); +reg_write( DDR_REG_BASE +0x51fcd*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x51fce*4+0x02000000,0x9e6); +reg_write( DDR_REG_BASE +0x51fcf*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51fd0*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x51fd1*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51fd2*4+0x02000000,0x815); +reg_write( DDR_REG_BASE +0x51fd3*4+0x02000000,0x51); +reg_write( DDR_REG_BASE +0x51fd4*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51fd5*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51fd6*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51fd7*4+0x02000000,0x19); +reg_write( DDR_REG_BASE +0x51fd8*4+0x02000000,0xe884); +reg_write( DDR_REG_BASE +0x51fd9*4+0x02000000,0xb2e); +reg_write( DDR_REG_BASE +0x51fda*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51fdb*4+0x02000000,0xd80d); +reg_write( DDR_REG_BASE +0x51fdc*4+0x02000000,0xed07); +reg_write( DDR_REG_BASE +0x51fdd*4+0x02000000,0xb26); +reg_write( DDR_REG_BASE +0x51fde*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51fdf*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x51fe0*4+0x02000000,0x9c2); +reg_write( DDR_REG_BASE +0x51fe1*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51fe2*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x51fe3*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51fe4*4+0x02000000,0x825); +reg_write( DDR_REG_BASE +0x51fe5*4+0x02000000,0x27f); +reg_write( DDR_REG_BASE +0x51fe6*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x51fe7*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51fe8*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51fe9*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51fea*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51feb*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x51fec*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51fed*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51fee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51fef*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51ff0*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51ff1*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51ff2*4+0x02000000,0xe040); +reg_write( DDR_REG_BASE +0x51ff3*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x51ff4*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x51ff5*4+0x02000000,0xf040); +reg_write( DDR_REG_BASE +0x51ff6*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51ff7*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51ff8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51ff9*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51ffa*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51ffb*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51ffc*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51ffd*4+0x02000000,0xb8e2); +reg_write( DDR_REG_BASE +0x51ffe*4+0x02000000,0x25ca); +reg_write( DDR_REG_BASE +0x51fff*4+0x02000000,0x13e1); +reg_write( DDR_REG_BASE +0x52000*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52001*4+0x02000000,0xae00); +reg_write( DDR_REG_BASE +0x52002*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52003*4+0x02000000,0x84f); +reg_write( DDR_REG_BASE +0x52004*4+0x02000000,0x95); +reg_write( DDR_REG_BASE +0x52005*4+0x02000000,0xe81d); +reg_write( DDR_REG_BASE +0x52006*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52007*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x52008*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52009*4+0x02000000,0x58); +reg_write( DDR_REG_BASE +0x5200a*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x5200b*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5200c*4+0x02000000,0xf213); +reg_write( DDR_REG_BASE +0x5200d*4+0x02000000,0xe76); +reg_write( DDR_REG_BASE +0x5200e*4+0x02000000,0xfe4f); +reg_write( DDR_REG_BASE +0x5200f*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x52010*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52011*4+0x02000000,0xaf6); +reg_write( DDR_REG_BASE +0x52012*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52013*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52014*4+0x02000000,0xd8a); +reg_write( DDR_REG_BASE +0x52015*4+0x02000000,0xfe4f); +reg_write( DDR_REG_BASE +0x52016*4+0x02000000,0xdc2); +reg_write( DDR_REG_BASE +0x52017*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x52018*4+0x02000000,0x1e01); +reg_write( DDR_REG_BASE +0x52019*4+0x02000000,0x1003); +reg_write( DDR_REG_BASE +0x5201a*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x5201b*4+0x02000000,0xdf6); +reg_write( DDR_REG_BASE +0x5201c*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x5201d*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x5201e*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x5201f*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52020*4+0x02000000,0xf1e1); +reg_write( DDR_REG_BASE +0x52021*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52022*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x52023*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52024*4+0x02000000,0x25); +reg_write( DDR_REG_BASE +0x52025*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52026*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52027*4+0x02000000,0xf5e7); +reg_write( DDR_REG_BASE +0x52028*4+0x02000000,0xf1f7); +reg_write( DDR_REG_BASE +0x52029*4+0x02000000,0xac6); +reg_write( DDR_REG_BASE +0x5202a*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x5202b*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x5202c*4+0x02000000,0xca09); +reg_write( DDR_REG_BASE +0x5202d*4+0x02000000,0xe885); +reg_write( DDR_REG_BASE +0x5202e*4+0x02000000,0x93e); +reg_write( DDR_REG_BASE +0x5202f*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52030*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52031*4+0x02000000,0x922); +reg_write( DDR_REG_BASE +0x52032*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52033*4+0x02000000,0xd809); +reg_write( DDR_REG_BASE +0x52034*4+0x02000000,0xca09); +reg_write( DDR_REG_BASE +0x52035*4+0x02000000,0xe837); +reg_write( DDR_REG_BASE +0x52036*4+0x02000000,0xd925); +reg_write( DDR_REG_BASE +0x52037*4+0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x52038*4+0x02000000,0x8900); +reg_write( DDR_REG_BASE +0x52039*4+0x02000000,0x1133); +reg_write( DDR_REG_BASE +0x5203a*4+0x02000000,0x8f); +reg_write( DDR_REG_BASE +0x5203b*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x5203c*4+0x02000000,0x7f05); +reg_write( DDR_REG_BASE +0x5203d*4+0x02000000,0xf022); +reg_write( DDR_REG_BASE +0x5203e*4+0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x5203f*4+0x02000000,0x17c1); +reg_write( DDR_REG_BASE +0x52040*4+0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x52041*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x52042*4+0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x52043*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x52044*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52045*4+0x02000000,0x78eb); +reg_write( DDR_REG_BASE +0x52046*4+0x02000000,0xf217); +reg_write( DDR_REG_BASE +0x52047*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52048*4+0x02000000,0xdda); +reg_write( DDR_REG_BASE +0x52049*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x5204a*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5204b*4+0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x5204c*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x5204d*4+0x02000000,0x7bcf); +reg_write( DDR_REG_BASE +0x5204e*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5204f*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x52050*4+0x02000000,0x93a); +reg_write( DDR_REG_BASE +0x52051*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52052*4+0x02000000,0x4378); +reg_write( DDR_REG_BASE +0x52053*4+0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x52054*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52055*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x52056*4+0x02000000,0x92e); +reg_write( DDR_REG_BASE +0x52057*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52058*4+0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x52059*4+0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x5205a*4+0x02000000,0x9da); +reg_write( DDR_REG_BASE +0x5205b*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x5205c*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x5205d*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x5205e*4+0x02000000,0xec1); +reg_write( DDR_REG_BASE +0x5205f*4+0x02000000,0x90b4); +reg_write( DDR_REG_BASE +0x52060*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52061*4+0x02000000,0x8da); +reg_write( DDR_REG_BASE +0x52062*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52063*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52064*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52065*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x52066*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52067*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52068*4+0x02000000,0xb8e5); +reg_write( DDR_REG_BASE +0x52069*4+0x02000000,0x9f8); +reg_write( DDR_REG_BASE +0x5206a*4+0x02000000,0xfe82); +reg_write( DDR_REG_BASE +0x5206b*4+0x02000000,0xb02); +reg_write( DDR_REG_BASE +0x5206c*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x5206d*4+0x02000000,0xca04); +reg_write( DDR_REG_BASE +0x5206e*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x5206f*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52070*4+0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x52071*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x52072*4+0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x52073*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x52074*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52075*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52076*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52077*4+0x02000000,0x7965); +reg_write( DDR_REG_BASE +0x52078*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x52079*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x5207a*4+0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x5207b*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x5207c*4+0x02000000,0x140); +reg_write( DDR_REG_BASE +0x5207d*4+0x02000000,0x2332); +reg_write( DDR_REG_BASE +0x5207e*4+0x02000000,0x1f81); +reg_write( DDR_REG_BASE +0x5207f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52080*4+0x02000000,0x7f0); +reg_write( DDR_REG_BASE +0x52081*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x52082*4+0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x52083*4+0x02000000,0xb420); +reg_write( DDR_REG_BASE +0x52084*4+0x02000000,0xbdf); +reg_write( DDR_REG_BASE +0x52085*4+0x02000000,0x8214); +reg_write( DDR_REG_BASE +0x52086*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x52087*4+0x02000000,0xad7); +reg_write( DDR_REG_BASE +0x52088*4+0x02000000,0x8024); +reg_write( DDR_REG_BASE +0x52089*4+0x02000000,0x2316); +reg_write( DDR_REG_BASE +0x5208a*4+0x02000000,0x308b); +reg_write( DDR_REG_BASE +0x5208b*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5208c*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5208d*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x5208e*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x5208f*4+0x02000000,0xe032); +reg_write( DDR_REG_BASE +0x52090*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52091*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x52092*4+0x02000000,0x9de); +reg_write( DDR_REG_BASE +0x52093*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52094*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52095*4+0x02000000,0xcfa); +reg_write( DDR_REG_BASE +0x52096*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x52097*4+0x02000000,0x82e); +reg_write( DDR_REG_BASE +0x52098*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x52099*4+0x02000000,0xd807); +reg_write( DDR_REG_BASE +0x5209a*4+0x02000000,0x23ab); +reg_write( DDR_REG_BASE +0x5209b*4+0x02000000,0x30c4); +reg_write( DDR_REG_BASE +0x5209c*4+0x02000000,0x7fff); +reg_write( DDR_REG_BASE +0x5209d*4+0x02000000,0xf000); +reg_write( DDR_REG_BASE +0x5209e*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x5209f*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x520a0*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x520a1*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x520a2*4+0x02000000,0x9500); +reg_write( DDR_REG_BASE +0x520a3*4+0x02000000,0xb8a1); +reg_write( DDR_REG_BASE +0x520a4*4+0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x520a5*4+0x02000000,0xf3e); +reg_write( DDR_REG_BASE +0x520a6*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x520a7*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x520a8*4+0x02000000,0xd81f); +reg_write( DDR_REG_BASE +0x520a9*4+0x02000000,0xf36); +reg_write( DDR_REG_BASE +0x520aa*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x520ab*4+0x02000000,0x1df6); +reg_write( DDR_REG_BASE +0x520ac*4+0x02000000,0x105d); +reg_write( DDR_REG_BASE +0x520ad*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x520ae*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x520af*4+0x02000000,0xf2a); +reg_write( DDR_REG_BASE +0x520b0*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x520b1*4+0x02000000,0xd81f); +reg_write( DDR_REG_BASE +0x520b2*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x520b3*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x520b4*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x520b5*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x520b6*4+0x02000000,0xf1a); +reg_write( DDR_REG_BASE +0x520b7*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x520b8*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x520b9*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x520ba*4+0x02000000,0x150a); +reg_write( DDR_REG_BASE +0x520bb*4+0x02000000,0x9700); +reg_write( DDR_REG_BASE +0x520bc*4+0x02000000,0xb881); +reg_write( DDR_REG_BASE +0x520bd*4+0x02000000,0x1d0a); +reg_write( DDR_REG_BASE +0x520be*4+0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x520bf*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x520c0*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x520c1*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x520c2*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x520c3*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x520c4*4+0x02000000,0x12); +reg_write( DDR_REG_BASE +0x520c5*4+0x02000000,0x218c); +reg_write( DDR_REG_BASE +0x520c6*4+0x02000000,0x8203); +reg_write( DDR_REG_BASE +0x520c7*4+0x02000000,0xfcc); +reg_write( DDR_REG_BASE +0x520c8*4+0x02000000,0x10e); +reg_write( DDR_REG_BASE +0x520c9*4+0x02000000,0x80e); +reg_write( DDR_REG_BASE +0x520ca*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x520cb*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x520cc*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x520cd*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x520ce*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x520cf*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x520d0*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x520d1*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x520d2*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x520d3*4+0x02000000,0x81b); +reg_write( DDR_REG_BASE +0x520d4*4+0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x520d5*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x520d6*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x520d7*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x520d8*4+0x02000000,0xe036); +reg_write( DDR_REG_BASE +0x520d9*4+0x02000000,0xed6); +reg_write( DDR_REG_BASE +0x520da*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x520db*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x520dc*4+0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x520dd*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x520de*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x520df*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x520e0*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x520e1*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x520e2*4+0x02000000,0xf2); +reg_write( DDR_REG_BASE +0x520e3*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x520e4*4+0x02000000,0x45); +reg_write( DDR_REG_BASE +0x520e5*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x520e6*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x520e7*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x520e8*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x520e9*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x520ea*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x520eb*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x520ec*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x520ed*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x520ee*4+0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x520ef*4+0x02000000,0xdc08); +reg_write( DDR_REG_BASE +0x520f0*4+0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x520f1*4+0x02000000,0xc01); +reg_write( DDR_REG_BASE +0x520f2*4+0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x520f3*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x520f4*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x520f5*4+0x02000000,0x4d); +reg_write( DDR_REG_BASE +0x520f6*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x520f7*4+0x02000000,0x4378); +reg_write( DDR_REG_BASE +0x520f8*4+0x02000000,0xc24e); +reg_write( DDR_REG_BASE +0x520f9*4+0x02000000,0xae2); +reg_write( DDR_REG_BASE +0x520fa*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x520fb*4+0x02000000,0x4728); +reg_write( DDR_REG_BASE +0x520fc*4+0x02000000,0x2353); +reg_write( DDR_REG_BASE +0x520fd*4+0x02000000,0x30c0); +reg_write( DDR_REG_BASE +0x520fe*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x520ff*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52100*4+0x02000000,0xe0c4); +reg_write( DDR_REG_BASE +0x52101*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x52102*4+0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x52103*4+0x02000000,0xd9f0); +reg_write( DDR_REG_BASE +0x52104*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x52105*4+0x02000000,0xc07); +reg_write( DDR_REG_BASE +0x52106*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x52107*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x52108*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52109*4+0x02000000,0x6c1); +reg_write( DDR_REG_BASE +0x5210a*4+0x02000000,0xba8b); +reg_write( DDR_REG_BASE +0x5210b*4+0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x5210c*4+0x02000000,0xc096); +reg_write( DDR_REG_BASE +0x5210d*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5210e*4+0x02000000,0xda28); +reg_write( DDR_REG_BASE +0x5210f*4+0x02000000,0x9be); +reg_write( DDR_REG_BASE +0x52110*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x52111*4+0x02000000,0xc396); +reg_write( DDR_REG_BASE +0x52112*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x52113*4+0x02000000,0x6c7); +reg_write( DDR_REG_BASE +0x52114*4+0x02000000,0x20b8); +reg_write( DDR_REG_BASE +0x52115*4+0x02000000,0xfc3); +reg_write( DDR_REG_BASE +0x52116*4+0x02000000,0xc06d); +reg_write( DDR_REG_BASE +0x52117*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52118*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52119*4+0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x5211a*4+0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x5211b*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x5211c*4+0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x5211d*4+0x02000000,0x14a0); +reg_write( DDR_REG_BASE +0x5211e*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x5211f*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52120*4+0x02000000,0xc346); +reg_write( DDR_REG_BASE +0x52121*4+0x02000000,0xc04f); +reg_write( DDR_REG_BASE +0x52122*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52123*4+0x02000000,0x149c); +reg_write( DDR_REG_BASE +0x52124*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x52125*4+0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x52126*4+0x02000000,0x17c3); +reg_write( DDR_REG_BASE +0x52127*4+0x02000000,0x1c30); +reg_write( DDR_REG_BASE +0x52128*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52129*4+0x02000000,0xc050); +reg_write( DDR_REG_BASE +0x5212a*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5212b*4+0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x5212c*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x5212d*4+0x02000000,0xc10e); +reg_write( DDR_REG_BASE +0x5212e*4+0x02000000,0x1c25); +reg_write( DDR_REG_BASE +0x5212f*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x52130*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x52131*4+0x02000000,0xeb06); +reg_write( DDR_REG_BASE +0x52132*4+0x02000000,0xbb61); +reg_write( DDR_REG_BASE +0x52133*4+0x02000000,0xb01); +reg_write( DDR_REG_BASE +0x52134*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x52135*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52136*4+0x02000000,0x1c24); +reg_write( DDR_REG_BASE +0x52137*4+0x02000000,0x3003); +reg_write( DDR_REG_BASE +0x52138*4+0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x52139*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5213a*4+0x02000000,0xc748); +reg_write( DDR_REG_BASE +0x5213b*4+0x02000000,0x1c1c); +reg_write( DDR_REG_BASE +0x5213c*4+0x02000000,0x3103); +reg_write( DDR_REG_BASE +0x5213d*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x5213e*4+0x02000000,0x200f); +reg_write( DDR_REG_BASE +0x5213f*4+0x02000000,0x380); +reg_write( DDR_REG_BASE +0x52140*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52141*4+0x02000000,0x9da); +reg_write( DDR_REG_BASE +0x52142*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52143*4+0x02000000,0xc054); +reg_write( DDR_REG_BASE +0x52144*4+0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x52145*4+0x02000000,0xb863); +reg_write( DDR_REG_BASE +0x52146*4+0x02000000,0xc052); +reg_write( DDR_REG_BASE +0x52147*4+0x02000000,0x7314); +reg_write( DDR_REG_BASE +0x52148*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52149*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5214a*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x5214b*4+0x02000000,0x48); +reg_write( DDR_REG_BASE +0x5214c*4+0x02000000,0x2d); +reg_write( DDR_REG_BASE +0x5214d*4+0x02000000,0xc051); +reg_write( DDR_REG_BASE +0x5214e*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5214f*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52150*4+0x02000000,0x1ea); +reg_write( DDR_REG_BASE +0x52151*4+0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x52152*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52153*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x52154*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52155*4+0x02000000,0xc0ff); +reg_write( DDR_REG_BASE +0x52156*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52157*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52158*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52159*4+0x02000000,0x3f00); +reg_write( DDR_REG_BASE +0x5215a*4+0x02000000,0x2080); +reg_write( DDR_REG_BASE +0x5215b*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5215c*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x5215d*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x5215e*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5215f*4+0x02000000,0x76c4); +reg_write( DDR_REG_BASE +0x52160*4+0x02000000,0x900f); +reg_write( DDR_REG_BASE +0x52161*4+0x02000000,0xe022); +reg_write( DDR_REG_BASE +0x52162*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52163*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x52164*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52165*4+0x02000000,0xee); +reg_write( DDR_REG_BASE +0x52166*4+0x02000000,0x2050); +reg_write( DDR_REG_BASE +0x52167*4+0x02000000,0x141); +reg_write( DDR_REG_BASE +0x52168*4+0x02000000,0xb885); +reg_write( DDR_REG_BASE +0x52169*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5216a*4+0x02000000,0x7044); +reg_write( DDR_REG_BASE +0x5216b*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x5216c*4+0x02000000,0xe0ee); +reg_write( DDR_REG_BASE +0x5216d*4+0x02000000,0xc051); +reg_write( DDR_REG_BASE +0x5216e*4+0x02000000,0x1498); +reg_write( DDR_REG_BASE +0x5216f*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x52170*4+0x02000000,0xc055); +reg_write( DDR_REG_BASE +0x52171*4+0x02000000,0x1494); +reg_write( DDR_REG_BASE +0x52172*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x52173*4+0x02000000,0xc053); +reg_write( DDR_REG_BASE +0x52174*4+0x02000000,0x996); +reg_write( DDR_REG_BASE +0x52175*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52176*4+0x02000000,0xc083); +reg_write( DDR_REG_BASE +0x52177*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x52178*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52179*4+0x02000000,0x7cb); +reg_write( DDR_REG_BASE +0x5217a*4+0x02000000,0x8e61); +reg_write( DDR_REG_BASE +0x5217b*4+0x02000000,0x8e20); +reg_write( DDR_REG_BASE +0x5217c*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x5217d*4+0x02000000,0xc210); +reg_write( DDR_REG_BASE +0x5217e*4+0x02000000,0x7a34); +reg_write( DDR_REG_BASE +0x5217f*4+0x02000000,0x9200); +reg_write( DDR_REG_BASE +0x52180*4+0x02000000,0xe889); +reg_write( DDR_REG_BASE +0x52181*4+0x02000000,0xc096); +reg_write( DDR_REG_BASE +0x52182*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x52183*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x52184*4+0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x52185*4+0x02000000,0x833); +reg_write( DDR_REG_BASE +0x52186*4+0x02000000,0x2042); +reg_write( DDR_REG_BASE +0x52187*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x52188*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x52189*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x5218a*4+0x02000000,0xbe7); +reg_write( DDR_REG_BASE +0x5218b*4+0x02000000,0x8045); +reg_write( DDR_REG_BASE +0x5218c*4+0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x5218d*4+0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x5218e*4+0x02000000,0x839); +reg_write( DDR_REG_BASE +0x5218f*4+0x02000000,0xb5); +reg_write( DDR_REG_BASE +0x52190*4+0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x52191*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x52192*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52193*4+0x02000000,0xf0f0); +reg_write( DDR_REG_BASE +0x52194*4+0x02000000,0x43db); +reg_write( DDR_REG_BASE +0x52195*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52196*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x52197*4+0x02000000,0x43e1); +reg_write( DDR_REG_BASE +0x52198*4+0x02000000,0x737f); +reg_write( DDR_REG_BASE +0x52199*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x5219a*4+0x02000000,0x41e1); +reg_write( DDR_REG_BASE +0x5219b*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x5219c*4+0x02000000,0xe42); +reg_write( DDR_REG_BASE +0x5219d*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5219e*4+0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x5219f*4+0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x521a0*4+0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x521a1*4+0x02000000,0x33c2); +reg_write( DDR_REG_BASE +0x521a2*4+0x02000000,0xd808); +reg_write( DDR_REG_BASE +0x521a3*4+0x02000000,0x41e1); +reg_write( DDR_REG_BASE +0x521a4*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x521a5*4+0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x521a6*4+0x02000000,0xe2e); +reg_write( DDR_REG_BASE +0x521a7*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x521a8*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x521a9*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x521aa*4+0x02000000,0xb3a); +reg_write( DDR_REG_BASE +0x521ab*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x521ac*4+0x02000000,0xc083); +reg_write( DDR_REG_BASE +0x521ad*4+0x02000000,0x8e61); +reg_write( DDR_REG_BASE +0x521ae*4+0x02000000,0x8e20); +reg_write( DDR_REG_BASE +0x521af*4+0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x521b0*4+0x02000000,0xc20f); +reg_write( DDR_REG_BASE +0x521b1*4+0x02000000,0x7a34); +reg_write( DDR_REG_BASE +0x521b2*4+0x02000000,0x9200); +reg_write( DDR_REG_BASE +0x521b3*4+0x02000000,0x815); +reg_write( DDR_REG_BASE +0x521b4*4+0x02000000,0x7f1); +reg_write( DDR_REG_BASE +0x521b5*4+0x02000000,0xc096); +reg_write( DDR_REG_BASE +0x521b6*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x521b7*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x521b8*4+0x02000000,0x809); +reg_write( DDR_REG_BASE +0x521b9*4+0x02000000,0x833); +reg_write( DDR_REG_BASE +0x521ba*4+0x02000000,0xe020); +reg_write( DDR_REG_BASE +0x521bb*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x521bc*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x521bd*4+0x02000000,0xbe9); +reg_write( DDR_REG_BASE +0x521be*4+0x02000000,0x8045); +reg_write( DDR_REG_BASE +0x521bf*4+0x02000000,0xc012); +reg_write( DDR_REG_BASE +0x521c0*4+0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x521c1*4+0x02000000,0x114); +reg_write( DDR_REG_BASE +0x521c2*4+0x02000000,0xc76); +reg_write( DDR_REG_BASE +0x521c3*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x521c4*4+0x02000000,0xc014); +reg_write( DDR_REG_BASE +0x521c5*4+0x02000000,0xc013); +reg_write( DDR_REG_BASE +0x521c6*4+0x02000000,0xe807); +reg_write( DDR_REG_BASE +0x521c7*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x521c8*4+0x02000000,0x36); +reg_write( DDR_REG_BASE +0x521c9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x521ca*4+0x02000000,0xb2a); +reg_write( DDR_REG_BASE +0x521cb*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x521cc*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x521cd*4+0x02000000,0x8ee0); +reg_write( DDR_REG_BASE +0x521ce*4+0x02000000,0xf035); +reg_write( DDR_REG_BASE +0x521cf*4+0x02000000,0xc010); +reg_write( DDR_REG_BASE +0x521d0*4+0x02000000,0x7dfd); +reg_write( DDR_REG_BASE +0x521d1*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x521d2*4+0x02000000,0x3c2); +reg_write( DDR_REG_BASE +0x521d3*4+0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x521d4*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x521d5*4+0x02000000,0x3c3); +reg_write( DDR_REG_BASE +0x521d6*4+0x02000000,0x6358); +reg_write( DDR_REG_BASE +0x521d7*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x521d8*4+0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x521d9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x521da*4+0x02000000,0x2049); +reg_write( DDR_REG_BASE +0x521db*4+0x02000000,0x7c1); +reg_write( DDR_REG_BASE +0x521dc*4+0x02000000,0xc015); +reg_write( DDR_REG_BASE +0x521dd*4+0x02000000,0x78f4); +reg_write( DDR_REG_BASE +0x521de*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x521df*4+0x02000000,0x4b50); +reg_write( DDR_REG_BASE +0x521e0*4+0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x521e1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x521e2*4+0x02000000,0xc04e); +reg_write( DDR_REG_BASE +0x521e3*4+0x02000000,0xc013); +reg_write( DDR_REG_BASE +0x521e4*4+0x02000000,0xe812); +reg_write( DDR_REG_BASE +0x521e5*4+0x02000000,0xc010); +reg_write( DDR_REG_BASE +0x521e6*4+0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x521e7*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x521e8*4+0x02000000,0x3c2); +reg_write( DDR_REG_BASE +0x521e9*4+0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x521ea*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x521eb*4+0x02000000,0x3c0); +reg_write( DDR_REG_BASE +0x521ec*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x521ed*4+0x02000000,0xc240); +reg_write( DDR_REG_BASE +0x521ee*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x521ef*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x521f0*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x521f1*4+0x02000000,0x38); +reg_write( DDR_REG_BASE +0x521f2*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x521f3*4+0x02000000,0xada); +reg_write( DDR_REG_BASE +0x521f4*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x521f5*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x521f6*4+0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x521f7*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x521f8*4+0x02000000,0x39); +reg_write( DDR_REG_BASE +0x521f9*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x521fa*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x521fb*4+0x02000000,0x780e); +reg_write( DDR_REG_BASE +0x521fc*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x521fd*4+0x02000000,0x207f); +reg_write( DDR_REG_BASE +0x521fe*4+0x02000000,0x140); +reg_write( DDR_REG_BASE +0x521ff*4+0x02000000,0xd56); +reg_write( DDR_REG_BASE +0x52200*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52201*4+0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x52202*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x52203*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x52204*4+0x02000000,0x897); +reg_write( DDR_REG_BASE +0x52205*4+0x02000000,0x83e5); +reg_write( DDR_REG_BASE +0x52206*4+0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x52207*4+0x02000000,0x105b); +reg_write( DDR_REG_BASE +0x52208*4+0x02000000,0xc012); +reg_write( DDR_REG_BASE +0x52209*4+0x02000000,0x835); +reg_write( DDR_REG_BASE +0x5220a*4+0x02000000,0x115); +reg_write( DDR_REG_BASE +0x5220b*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x5220c*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x5220d*4+0x02000000,0x1ea); +reg_write( DDR_REG_BASE +0x5220e*4+0x02000000,0x9200); +reg_write( DDR_REG_BASE +0x5220f*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52210*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52211*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52212*4+0x02000000,0xc0ff); +reg_write( DDR_REG_BASE +0x52213*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52214*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52215*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52216*4+0x02000000,0x3f00); +reg_write( DDR_REG_BASE +0x52217*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52218*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52219*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5221a*4+0x02000000,0xfc00); +reg_write( DDR_REG_BASE +0x5221b*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x5221c*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x5221d*4+0x02000000,0xc011); +reg_write( DDR_REG_BASE +0x5221e*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5221f*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52220*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52221*4+0x02000000,0xe0ee); +reg_write( DDR_REG_BASE +0x52222*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52223*4+0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x52224*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52225*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x52226*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x52227*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x52228*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52229*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x5222a*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5222b*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5222c*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5222d*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5222e*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5222f*4+0x02000000,0xc1ad); +reg_write( DDR_REG_BASE +0x52230*4+0x02000000,0xc248); +reg_write( DDR_REG_BASE +0x52231*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x52232*4+0x02000000,0xc16); +reg_write( DDR_REG_BASE +0x52233*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x52234*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x52235*4+0x02000000,0x2342); +reg_write( DDR_REG_BASE +0x52236*4+0x02000000,0x30cd); +reg_write( DDR_REG_BASE +0x52237*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x52238*4+0x02000000,0x97e); +reg_write( DDR_REG_BASE +0x52239*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x5223a*4+0x02000000,0x7eaf); +reg_write( DDR_REG_BASE +0x5223b*4+0x02000000,0xd33); +reg_write( DDR_REG_BASE +0x5223c*4+0x02000000,0x1134); +reg_write( DDR_REG_BASE +0x5223d*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5223e*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5223f*4+0x02000000,0xd82); +reg_write( DDR_REG_BASE +0x52240*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52241*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52242*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x52243*4+0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x52244*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52245*4+0x02000000,0xd981); +reg_write( DDR_REG_BASE +0x52246*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52247*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52248*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52249*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5224a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5224b*4+0x02000000,0xb98e); +reg_write( DDR_REG_BASE +0x5224c*4+0x02000000,0xe3e); +reg_write( DDR_REG_BASE +0x5224d*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5224e*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5224f*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52250*4+0x02000000,0xdf6); +reg_write( DDR_REG_BASE +0x52251*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52252*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52253*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x52254*4+0x02000000,0x203c); +reg_write( DDR_REG_BASE +0x52255*4+0x02000000,0x381); +reg_write( DDR_REG_BASE +0x52256*4+0x02000000,0x2342); +reg_write( DDR_REG_BASE +0x52257*4+0x02000000,0x304e); +reg_write( DDR_REG_BASE +0x52258*4+0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x52259*4+0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x5225a*4+0x02000000,0x273c); +reg_write( DDR_REG_BASE +0x5225b*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x5225c*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x5225d*4+0x02000000,0x8040); +reg_write( DDR_REG_BASE +0x5225e*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x5225f*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52260*4+0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x52261*4+0x02000000,0x1222); +reg_write( DDR_REG_BASE +0x52262*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52263*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x52264*4+0x02000000,0x20cf); +reg_write( DDR_REG_BASE +0x52265*4+0x02000000,0xa2); +reg_write( DDR_REG_BASE +0x52266*4+0x02000000,0x74b5); +reg_write( DDR_REG_BASE +0x52267*4+0x02000000,0xc26); +reg_write( DDR_REG_BASE +0x52268*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x52269*4+0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x5226a*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x5226b*4+0x02000000,0xc2a); +reg_write( DDR_REG_BASE +0x5226c*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5226d*4+0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x5226e*4+0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x5226f*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52270*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52271*4+0x02000000,0x2710); +reg_write( DDR_REG_BASE +0x52272*4+0x02000000,0xc1a); +reg_write( DDR_REG_BASE +0x52273*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x52274*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x52275*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52276*4+0x02000000,0x900f); +reg_write( DDR_REG_BASE +0x52277*4+0x02000000,0xe0c0); +reg_write( DDR_REG_BASE +0x52278*4+0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x52279*4+0x02000000,0xb1e0); +reg_write( DDR_REG_BASE +0x5227a*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5227b*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x5227c*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x5227d*4+0x02000000,0xf0f0); +reg_write( DDR_REG_BASE +0x5227e*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x5227f*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x52280*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x52281*4+0x02000000,0x78c0); +reg_write( DDR_REG_BASE +0x52282*4+0x02000000,0xb105); +reg_write( DDR_REG_BASE +0x52283*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52284*4+0x02000000,0x772c); +reg_write( DDR_REG_BASE +0x52285*4+0x02000000,0xc145); +reg_write( DDR_REG_BASE +0x52286*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52287*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x52288*4+0x02000000,0x70fd); +reg_write( DDR_REG_BASE +0x52289*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x5228a*4+0x02000000,0x773c); +reg_write( DDR_REG_BASE +0x5228b*4+0x02000000,0xc10a); +reg_write( DDR_REG_BASE +0x5228c*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x5228d*4+0x02000000,0x2114); +reg_write( DDR_REG_BASE +0x5228e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5228f*4+0x02000000,0x48e8); +reg_write( DDR_REG_BASE +0x52290*4+0x02000000,0xb9c0); +reg_write( DDR_REG_BASE +0x52291*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x52292*4+0x02000000,0xe2b); +reg_write( DDR_REG_BASE +0x52293*4+0x02000000,0x10b5); +reg_write( DDR_REG_BASE +0x52294*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52295*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x52296*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52297*4+0x02000000,0xf0f0); +reg_write( DDR_REG_BASE +0x52298*4+0x02000000,0x7bf0); +reg_write( DDR_REG_BASE +0x52299*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x5229a*4+0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x5229b*4+0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x5229c*4+0x02000000,0xc42); +reg_write( DDR_REG_BASE +0x5229d*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5229e*4+0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x5229f*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x522a0*4+0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x522a1*4+0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x522a2*4+0x02000000,0x7b10); +reg_write( DDR_REG_BASE +0x522a3*4+0x02000000,0xd808); +reg_write( DDR_REG_BASE +0x522a4*4+0x02000000,0xc32); +reg_write( DDR_REG_BASE +0x522a5*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x522a6*4+0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x522a7*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x522a8*4+0x02000000,0xe030); +reg_write( DDR_REG_BASE +0x522a9*4+0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x522aa*4+0x02000000,0x234f); +reg_write( DDR_REG_BASE +0x522ab*4+0x02000000,0x3040); +reg_write( DDR_REG_BASE +0x522ac*4+0x02000000,0x899); +reg_write( DDR_REG_BASE +0x522ad*4+0x02000000,0xb1); +reg_write( DDR_REG_BASE +0x522ae*4+0x02000000,0x73b5); +reg_write( DDR_REG_BASE +0x522af*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x522b0*4+0x02000000,0xb8c1); +reg_write( DDR_REG_BASE +0x522b1*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x522b2*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x522b3*4+0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x522b4*4+0x02000000,0xc96); +reg_write( DDR_REG_BASE +0x522b5*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x522b6*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x522b7*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x522b8*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x522b9*4+0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x522ba*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x522bb*4+0x02000000,0xb98e); +reg_write( DDR_REG_BASE +0x522bc*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x522bd*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x522be*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x522bf*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x522c0*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x522c1*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x522c2*4+0x02000000,0xd52); +reg_write( DDR_REG_BASE +0x522c3*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x522c4*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x522c5*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x522c6*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x522c7*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x522c8*4+0x02000000,0x7f0f); +reg_write( DDR_REG_BASE +0x522c9*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x522ca*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x522cb*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x522cc*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x522cd*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x522ce*4+0x02000000,0xd3a); +reg_write( DDR_REG_BASE +0x522cf*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x522d0*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x522d1*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x522d2*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x522d3*4+0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x522d4*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x522d5*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x522d6*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x522d7*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x522d8*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x522d9*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x522da*4+0x02000000,0xd22); +reg_write( DDR_REG_BASE +0x522db*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x522dc*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x522dd*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x522de*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x522df*4+0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x522e0*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x522e1*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x522e2*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x522e3*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x522e4*4+0x02000000,0xdb28); +reg_write( DDR_REG_BASE +0x522e5*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x522e6*4+0x02000000,0xd0a); +reg_write( DDR_REG_BASE +0x522e7*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x522e8*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x522e9*4+0x02000000,0xf52); +reg_write( DDR_REG_BASE +0x522ea*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x522eb*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x522ec*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x522ed*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x522ee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x522ef*4+0x02000000,0x3100); +reg_write( DDR_REG_BASE +0x522f0*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x522f1*4+0x02000000,0x22a); +reg_write( DDR_REG_BASE +0x522f2*4+0x02000000,0x21); +reg_write( DDR_REG_BASE +0x522f3*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x522f4*4+0x02000000,0x2f3); +reg_write( DDR_REG_BASE +0x522f5*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x522f6*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x522f7*4+0x02000000,0x3441); +reg_write( DDR_REG_BASE +0x522f8*4+0x02000000,0x44c); +reg_write( DDR_REG_BASE +0x522f9*4+0x02000000,0x2d); +reg_write( DDR_REG_BASE +0x522fa*4+0x02000000,0x7177); +reg_write( DDR_REG_BASE +0x522fb*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x522fc*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x522fd*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x522fe*4+0x02000000,0x13); +reg_write( DDR_REG_BASE +0x522ff*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52300*4+0x02000000,0x5d4); +reg_write( DDR_REG_BASE +0x52301*4+0x02000000,0x21); +reg_write( DDR_REG_BASE +0x52302*4+0x02000000,0x7377); +reg_write( DDR_REG_BASE +0x52303*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x52304*4+0x02000000,0x269a); +reg_write( DDR_REG_BASE +0x52305*4+0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x52306*4+0x02000000,0x7e05); +reg_write( DDR_REG_BASE +0x52307*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52308*4+0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x52309*4+0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x5230a*4+0x02000000,0x43c1); +reg_write( DDR_REG_BASE +0x5230b*4+0x02000000,0xb66); +reg_write( DDR_REG_BASE +0x5230c*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5230d*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x5230e*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x5230f*4+0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x52310*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52311*4+0x02000000,0xbde); +reg_write( DDR_REG_BASE +0x52312*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52313*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x52314*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52315*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52316*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x52317*4+0x02000000,0x7f0f); +reg_write( DDR_REG_BASE +0x52318*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x52319*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5231a*4+0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x5231b*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5231c*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5231d*4+0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x5231e*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x5231f*4+0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x52320*4+0x02000000,0xc96); +reg_write( DDR_REG_BASE +0x52321*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52322*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52323*4+0x02000000,0xd828); +reg_write( DDR_REG_BASE +0x52324*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52325*4+0x02000000,0xd808); +reg_write( DDR_REG_BASE +0x52326*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x52327*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x52328*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x52329*4+0x02000000,0x7edd); +reg_write( DDR_REG_BASE +0x5232a*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5232b*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5232c*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x5232d*4+0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x5232e*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5232f*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52330*4+0x02000000,0xc76); +reg_write( DDR_REG_BASE +0x52331*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52332*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x52333*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52334*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52335*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x52336*4+0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x52337*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52338*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52339*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x5233a*4+0x02000000,0x33c1); +reg_write( DDR_REG_BASE +0x5233b*4+0x02000000,0xc62); +reg_write( DDR_REG_BASE +0x5233c*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5233d*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5233e*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5233f*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x52340*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x52341*4+0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x52342*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52343*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52344*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x52345*4+0x02000000,0x3501); +reg_write( DDR_REG_BASE +0x52346*4+0x02000000,0xc4a); +reg_write( DDR_REG_BASE +0x52347*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52348*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52349*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5234a*4+0x02000000,0xc02); +reg_write( DDR_REG_BASE +0x5234b*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5234c*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5234d*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5234e*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5234f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52350*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52351*4+0x02000000,0xdae0); +reg_write( DDR_REG_BASE +0x52352*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x52353*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52354*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52355*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52356*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52357*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52358*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x52359*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x5235a*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x5235b*4+0x02000000,0x7204); +reg_write( DDR_REG_BASE +0x5235c*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x5235d*4+0x02000000,0xb340); +reg_write( DDR_REG_BASE +0x5235e*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x5235f*4+0x02000000,0x485); +reg_write( DDR_REG_BASE +0x52360*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52361*4+0x02000000,0xb3e); +reg_write( DDR_REG_BASE +0x52362*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52363*4+0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x52364*4+0x02000000,0xe5a); +reg_write( DDR_REG_BASE +0x52365*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52366*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52367*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x52368*4+0x02000000,0xbe90); +reg_write( DDR_REG_BASE +0x52369*4+0x02000000,0xf968); +reg_write( DDR_REG_BASE +0x5236a*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5236b*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5236c*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5236d*4+0x02000000,0xbfe); +reg_write( DDR_REG_BASE +0x5236e*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5236f*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52370*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52371*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52372*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52373*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52374*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x52375*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52376*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52377*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52378*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52379*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5237a*4+0x02000000,0xbe2); +reg_write( DDR_REG_BASE +0x5237b*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5237c*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x5237d*4+0x02000000,0xf95e); +reg_write( DDR_REG_BASE +0x5237e*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5237f*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52380*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52381*4+0x02000000,0xbd6); +reg_write( DDR_REG_BASE +0x52382*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52383*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52384*4+0x02000000,0xf957); +reg_write( DDR_REG_BASE +0x52385*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52386*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52387*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52388*4+0x02000000,0xbc6); +reg_write( DDR_REG_BASE +0x52389*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5238a*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5238b*4+0x02000000,0xf957); +reg_write( DDR_REG_BASE +0x5238c*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5238d*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5238e*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5238f*4+0x02000000,0xbba); +reg_write( DDR_REG_BASE +0x52390*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52391*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52392*4+0x02000000,0xf950); +reg_write( DDR_REG_BASE +0x52393*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52394*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52395*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52396*4+0x02000000,0xbaa); +reg_write( DDR_REG_BASE +0x52397*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52398*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52399*4+0x02000000,0xf950); +reg_write( DDR_REG_BASE +0x5239a*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5239b*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5239c*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5239d*4+0x02000000,0xb9e); +reg_write( DDR_REG_BASE +0x5239e*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5239f*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523a0*4+0x02000000,0xf949); +reg_write( DDR_REG_BASE +0x523a1*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523a2*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x523a3*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523a4*4+0x02000000,0xb8e); +reg_write( DDR_REG_BASE +0x523a5*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523a6*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523a7*4+0x02000000,0xf949); +reg_write( DDR_REG_BASE +0x523a8*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523a9*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x523aa*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523ab*4+0x02000000,0xb82); +reg_write( DDR_REG_BASE +0x523ac*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523ad*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523ae*4+0x02000000,0xf942); +reg_write( DDR_REG_BASE +0x523af*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523b0*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x523b1*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523b2*4+0x02000000,0xb72); +reg_write( DDR_REG_BASE +0x523b3*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523b4*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523b5*4+0x02000000,0xf942); +reg_write( DDR_REG_BASE +0x523b6*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523b7*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x523b8*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523b9*4+0x02000000,0xb66); +reg_write( DDR_REG_BASE +0x523ba*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523bb*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523bc*4+0x02000000,0xf93b); +reg_write( DDR_REG_BASE +0x523bd*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523be*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x523bf*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523c0*4+0x02000000,0xb56); +reg_write( DDR_REG_BASE +0x523c1*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523c2*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523c3*4+0x02000000,0xf93b); +reg_write( DDR_REG_BASE +0x523c4*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523c5*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x523c6*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523c7*4+0x02000000,0xb4a); +reg_write( DDR_REG_BASE +0x523c8*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523c9*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523ca*4+0x02000000,0xf934); +reg_write( DDR_REG_BASE +0x523cb*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523cc*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x523cd*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523ce*4+0x02000000,0xb3a); +reg_write( DDR_REG_BASE +0x523cf*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523d0*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523d1*4+0x02000000,0xf934); +reg_write( DDR_REG_BASE +0x523d2*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523d3*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x523d4*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523d5*4+0x02000000,0xb2e); +reg_write( DDR_REG_BASE +0x523d6*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523d7*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523d8*4+0x02000000,0xf92d); +reg_write( DDR_REG_BASE +0x523d9*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523da*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x523db*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523dc*4+0x02000000,0xb1e); +reg_write( DDR_REG_BASE +0x523dd*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523de*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523df*4+0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x523e0*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x523e1*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x523e2*4+0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x523e3*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x523e4*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523e5*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x523e6*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523e7*4+0x02000000,0xb0a); +reg_write( DDR_REG_BASE +0x523e8*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523e9*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523ea*4+0x02000000,0x79dd); +reg_write( DDR_REG_BASE +0x523eb*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x523ec*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x523ed*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x523ee*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x523ef*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x523f0*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x523f1*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523f2*4+0x02000000,0xaf2); +reg_write( DDR_REG_BASE +0x523f3*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523f4*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523f5*4+0x02000000,0xf91c); +reg_write( DDR_REG_BASE +0x523f6*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523f7*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x523f8*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523f9*4+0x02000000,0xae6); +reg_write( DDR_REG_BASE +0x523fa*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523fb*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523fc*4+0x02000000,0xd0e); +reg_write( DDR_REG_BASE +0x523fd*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523fe*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x523ff*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52400*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52401*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52402*4+0x02000000,0x3bd); +reg_write( DDR_REG_BASE +0x52403*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52404*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52405*4+0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x52406*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x52407*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52408*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52409*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5240a*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5240b*4+0x02000000,0xac2); +reg_write( DDR_REG_BASE +0x5240c*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5240d*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5240e*4+0x02000000,0xf90c); +reg_write( DDR_REG_BASE +0x5240f*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52410*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52411*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x52412*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52413*4+0x02000000,0xab2); +reg_write( DDR_REG_BASE +0x52414*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52415*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52416*4+0x02000000,0xf905); +reg_write( DDR_REG_BASE +0x52417*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x52418*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52419*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5241a*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5241b*4+0x02000000,0xaa2); +reg_write( DDR_REG_BASE +0x5241c*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5241d*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5241e*4+0x02000000,0xf8fe); +reg_write( DDR_REG_BASE +0x5241f*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52420*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52421*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52422*4+0x02000000,0xa92); +reg_write( DDR_REG_BASE +0x52423*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52424*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52425*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x52426*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52427*4+0x02000000,0xf900); +reg_write( DDR_REG_BASE +0x52428*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52429*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5242a*4+0x02000000,0xa82); +reg_write( DDR_REG_BASE +0x5242b*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5242c*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5242d*4+0x02000000,0xf8fa); +reg_write( DDR_REG_BASE +0x5242e*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x5242f*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52430*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52431*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52432*4+0x02000000,0xa72); +reg_write( DDR_REG_BASE +0x52433*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52434*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52435*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x52436*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52437*4+0x02000000,0xf8f5); +reg_write( DDR_REG_BASE +0x52438*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52439*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5243a*4+0x02000000,0xa62); +reg_write( DDR_REG_BASE +0x5243b*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5243c*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5243d*4+0x02000000,0xf8ef); +reg_write( DDR_REG_BASE +0x5243e*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5243f*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52440*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52441*4+0x02000000,0xa56); +reg_write( DDR_REG_BASE +0x52442*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52443*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52444*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52445*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52446*4+0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x52447*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52448*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52449*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x5244a*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5244b*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x5244c*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x5244d*4+0x02000000,0xa3e); +reg_write( DDR_REG_BASE +0x5244e*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5244f*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52450*4+0x02000000,0xf8e8); +reg_write( DDR_REG_BASE +0x52451*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x52452*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52453*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52454*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52455*4+0x02000000,0xa2e); +reg_write( DDR_REG_BASE +0x52456*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52457*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52458*4+0x02000000,0xf8e1); +reg_write( DDR_REG_BASE +0x52459*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5245a*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5245b*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5245c*4+0x02000000,0xa1e); +reg_write( DDR_REG_BASE +0x5245d*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5245e*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5245f*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52460*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52461*4+0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x52462*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52463*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x52464*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52465*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52466*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52467*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52468*4+0x02000000,0xa06); +reg_write( DDR_REG_BASE +0x52469*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5246a*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5246b*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x5246c*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x5246d*4+0x02000000,0xf8da); +reg_write( DDR_REG_BASE +0x5246e*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5246f*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52470*4+0x02000000,0x9f6); +reg_write( DDR_REG_BASE +0x52471*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52472*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52473*4+0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x52474*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52475*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52476*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52477*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52478*4+0x02000000,0xc305); +reg_write( DDR_REG_BASE +0x52479*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5247a*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5247b*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5247c*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5247d*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5247e*4+0x02000000,0x9da); +reg_write( DDR_REG_BASE +0x5247f*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52480*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52481*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x52482*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x52483*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52484*4+0x02000000,0x2100); +reg_write( DDR_REG_BASE +0x52485*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52486*4+0x02000000,0xf26c); +reg_write( DDR_REG_BASE +0x52487*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52488*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52489*4+0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x5248a*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x5248b*4+0x02000000,0x4358); +reg_write( DDR_REG_BASE +0x5248c*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5248d*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5248e*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5248f*4+0x02000000,0x9ba); +reg_write( DDR_REG_BASE +0x52490*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52491*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52492*4+0x02000000,0xf8ca); +reg_write( DDR_REG_BASE +0x52493*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52494*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52495*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x52496*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52497*4+0x02000000,0x9aa); +reg_write( DDR_REG_BASE +0x52498*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52499*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5249a*4+0x02000000,0xf8bd); +reg_write( DDR_REG_BASE +0x5249b*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x5249c*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x5249d*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5249e*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5249f*4+0x02000000,0x99a); +reg_write( DDR_REG_BASE +0x524a0*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524a1*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524a2*4+0x02000000,0xf8cb); +reg_write( DDR_REG_BASE +0x524a3*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x524a4*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x524a5*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x524a6*4+0x02000000,0x98a); +reg_write( DDR_REG_BASE +0x524a7*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524a8*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524a9*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x524aa*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x524ab*4+0x02000000,0xf8be); +reg_write( DDR_REG_BASE +0x524ac*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x524ad*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x524ae*4+0x02000000,0x97a); +reg_write( DDR_REG_BASE +0x524af*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524b0*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524b1*4+0x02000000,0xf8b2); +reg_write( DDR_REG_BASE +0x524b2*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x524b3*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x524b4*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x524b5*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x524b6*4+0x02000000,0x96a); +reg_write( DDR_REG_BASE +0x524b7*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524b8*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524b9*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x524ba*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x524bb*4+0x02000000,0xf8ad); +reg_write( DDR_REG_BASE +0x524bc*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x524bd*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x524be*4+0x02000000,0x95a); +reg_write( DDR_REG_BASE +0x524bf*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524c0*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524c1*4+0x02000000,0xf8bc); +reg_write( DDR_REG_BASE +0x524c2*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x524c3*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x524c4*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x524c5*4+0x02000000,0x94e); +reg_write( DDR_REG_BASE +0x524c6*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524c7*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524c8*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x524c9*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x524ca*4+0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x524cb*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x524cc*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x524cd*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x524ce*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x524cf*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x524d0*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x524d1*4+0x02000000,0x936); +reg_write( DDR_REG_BASE +0x524d2*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524d3*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524d4*4+0x02000000,0xf8a0); +reg_write( DDR_REG_BASE +0x524d5*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x524d6*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x524d7*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x524d8*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x524d9*4+0x02000000,0x926); +reg_write( DDR_REG_BASE +0x524da*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524db*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524dc*4+0x02000000,0xf8ae); +reg_write( DDR_REG_BASE +0x524dd*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x524de*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x524df*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x524e0*4+0x02000000,0x916); +reg_write( DDR_REG_BASE +0x524e1*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524e2*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524e3*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x524e4*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x524e5*4+0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x524e6*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x524e7*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x524e8*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x524e9*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x524ea*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x524eb*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x524ec*4+0x02000000,0x8fe); +reg_write( DDR_REG_BASE +0x524ed*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524ee*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524ef*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x524f0*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x524f1*4+0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x524f2*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x524f3*4+0x02000000,0x3441); +reg_write( DDR_REG_BASE +0x524f4*4+0x02000000,0xf890); +reg_write( DDR_REG_BASE +0x524f5*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x524f6*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x524f7*4+0x02000000,0x8ea); +reg_write( DDR_REG_BASE +0x524f8*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524f9*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524fa*4+0x02000000,0xc305); +reg_write( DDR_REG_BASE +0x524fb*4+0x02000000,0xf88a); +reg_write( DDR_REG_BASE +0x524fc*4+0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x524fd*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x524fe*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x524ff*4+0x02000000,0x8da); +reg_write( DDR_REG_BASE +0x52500*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52501*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x52502*4+0x02000000,0xf880); +reg_write( DDR_REG_BASE +0x52503*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x52504*4+0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x52505*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52506*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52507*4+0x02000000,0x8ca); +reg_write( DDR_REG_BASE +0x52508*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52509*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5250a*4+0x02000000,0xf891); +reg_write( DDR_REG_BASE +0x5250b*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5250c*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5250d*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5250e*4+0x02000000,0x8ba); +reg_write( DDR_REG_BASE +0x5250f*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52510*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52511*4+0x02000000,0xae6); +reg_write( DDR_REG_BASE +0x52512*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52513*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52514*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52515*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52516*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52517*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52518*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x52519*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x5251a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5251b*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x5251c*4+0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x5251d*4+0x02000000,0xf0c7); +reg_write( DDR_REG_BASE +0x5251e*4+0x02000000,0xf4c8); +reg_write( DDR_REG_BASE +0x5251f*4+0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x52520*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x52521*4+0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x52522*4+0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x52523*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x52524*4+0x02000000,0x4918); +reg_write( DDR_REG_BASE +0x52525*4+0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x52526*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x52527*4+0x02000000,0x4918); +reg_write( DDR_REG_BASE +0x52528*4+0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x52529*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5252a*4+0x02000000,0xf062); +reg_write( DDR_REG_BASE +0x5252b*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5252c*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x5252d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5252e*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x5252f*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52530*4+0x02000000,0x7dc0); +reg_write( DDR_REG_BASE +0x52531*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52532*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x52533*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x52534*4+0x02000000,0xf12); +reg_write( DDR_REG_BASE +0x52535*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52536*4+0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x52537*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52538*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x52539*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x5253a*4+0x02000000,0x7b10); +reg_write( DDR_REG_BASE +0x5253b*4+0x02000000,0xd808); +reg_write( DDR_REG_BASE +0x5253c*4+0x02000000,0xf02); +reg_write( DDR_REG_BASE +0x5253d*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x5253e*4+0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x5253f*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52540*4+0x02000000,0xf7e); +reg_write( DDR_REG_BASE +0x52541*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52542*4+0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x52543*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x52544*4+0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x52545*4+0x02000000,0xf865); +reg_write( DDR_REG_BASE +0x52546*4+0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x52547*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x52548*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x52549*4+0x02000000,0x846); +reg_write( DDR_REG_BASE +0x5254a*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5254b*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x5254c*4+0x02000000,0xf85e); +reg_write( DDR_REG_BASE +0x5254d*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5254e*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5254f*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52550*4+0x02000000,0x836); +reg_write( DDR_REG_BASE +0x52551*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52552*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52553*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52554*4+0x02000000,0x736f); +reg_write( DDR_REG_BASE +0x52555*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52556*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52557*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x52558*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52559*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5255a*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x5255b*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x5255c*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x5255d*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x5255e*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5255f*4+0x02000000,0x81a); +reg_write( DDR_REG_BASE +0x52560*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52561*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x52562*4+0x02000000,0x3281); +reg_write( DDR_REG_BASE +0x52563*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x52564*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52565*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x52566*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52567*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52568*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x52569*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x5256a*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x5256b*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5256c*4+0x02000000,0xffe); +reg_write( DDR_REG_BASE +0x5256d*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5256e*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5256f*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52570*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52571*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x52572*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x52573*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x52574*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52575*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52576*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52577*4+0x02000000,0xfea); +reg_write( DDR_REG_BASE +0x52578*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52579*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x5257a*4+0x02000000,0x3281); +reg_write( DDR_REG_BASE +0x5257b*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x5257c*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x5257d*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5257e*4+0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x5257f*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52580*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52581*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52582*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52583*4+0x02000000,0xfd2); +reg_write( DDR_REG_BASE +0x52584*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52585*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52586*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52587*4+0x02000000,0xf8a); +reg_write( DDR_REG_BASE +0x52588*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52589*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5258a*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5258b*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5258c*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5258d*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x5258e*4+0x02000000,0x232f); +reg_write( DDR_REG_BASE +0x5258f*4+0x02000000,0x3007); +reg_write( DDR_REG_BASE +0x52590*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52591*4+0x02000000,0x837); +reg_write( DDR_REG_BASE +0x52592*4+0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x52593*4+0x02000000,0x7bf0); +reg_write( DDR_REG_BASE +0x52594*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52595*4+0x02000000,0xed6); +reg_write( DDR_REG_BASE +0x52596*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52597*4+0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x52598*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x52599*4+0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x5259a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5259b*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5259c*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5259d*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x5259e*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x5259f*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x525a0*4+0x02000000,0xf96); +reg_write( DDR_REG_BASE +0x525a1*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x525a2*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x525a3*4+0x02000000,0x9de); +reg_write( DDR_REG_BASE +0x525a4*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x525a5*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x525a6*4+0x02000000,0xf831); +reg_write( DDR_REG_BASE +0x525a7*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x525a8*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x525a9*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x525aa*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x525ab*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x525ac*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x525ad*4+0x02000000,0xca08); +reg_write( DDR_REG_BASE +0x525ae*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x525af*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x525b0*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x525b1*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x525b2*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x525b3*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x525b4*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x525b5*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x525b6*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x525b7*4+0x02000000,0xf6a); +reg_write( DDR_REG_BASE +0x525b8*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x525b9*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x525ba*4+0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x525bb*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x525bc*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x525bd*4+0x02000000,0x2054); +reg_write( DDR_REG_BASE +0x525be*4+0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x525bf*4+0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x525c0*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x525c1*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x525c2*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x525c3*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x525c4*4+0x02000000,0xf4e); +reg_write( DDR_REG_BASE +0x525c5*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x525c6*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x525c7*4+0x02000000,0xf81e); +reg_write( DDR_REG_BASE +0x525c8*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x525c9*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x525ca*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x525cb*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x525cc*4+0x02000000,0xf3e); +reg_write( DDR_REG_BASE +0x525cd*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x525ce*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x525cf*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x525d0*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x525d1*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x525d2*4+0x02000000,0xdb50); +reg_write( DDR_REG_BASE +0x525d3*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x525d4*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x525d5*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x525d6*4+0x02000000,0xf2a); +reg_write( DDR_REG_BASE +0x525d7*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x525d8*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x525d9*4+0x02000000,0x956); +reg_write( DDR_REG_BASE +0x525da*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x525db*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x525dc*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x525dd*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x525de*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x525df*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x525e0*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x525e1*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x525e2*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x525e3*4+0x02000000,0xf12); +reg_write( DDR_REG_BASE +0x525e4*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x525e5*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x525e6*4+0x02000000,0xc0ad); +reg_write( DDR_REG_BASE +0x525e7*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x525e8*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x525e9*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x525ea*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x525eb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x525ec*4+0x02000000,0xaaaa); +reg_write( DDR_REG_BASE +0x525ed*4+0x02000000,0xf214); +reg_write( DDR_REG_BASE +0x525ee*4+0x02000000,0xb17); +reg_write( DDR_REG_BASE +0x525ef*4+0x02000000,0x3190); +reg_write( DDR_REG_BASE +0x525f0*4+0x02000000,0xb1b); +reg_write( DDR_REG_BASE +0x525f1*4+0x02000000,0x3150); +reg_write( DDR_REG_BASE +0x525f2*4+0x02000000,0xb1d); +reg_write( DDR_REG_BASE +0x525f3*4+0x02000000,0x3131); +reg_write( DDR_REG_BASE +0x525f4*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x525f5*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x525f6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x525f7*4+0x02000000,0xcccc); +reg_write( DDR_REG_BASE +0x525f8*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x525f9*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x525fa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x525fb*4+0x02000000,0x8282); +reg_write( DDR_REG_BASE +0x525fc*4+0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x525fd*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x525fe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x525ff*4+0x02000000,0xb2b2); +reg_write( DDR_REG_BASE +0x52600*4+0x02000000,0x20f); +reg_write( DDR_REG_BASE +0x52601*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x52602*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52603*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52604*4+0x02000000,0xb98f); +reg_write( DDR_REG_BASE +0x52605*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52606*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52607*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52608*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52609*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5260a*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5260b*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5260c*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5260d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5260e*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5260f*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52610*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52611*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x52612*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52613*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52614*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52615*4+0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x52616*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52617*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x52618*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52619*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5261a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5261b*4+0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x5261c*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x5261d*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x5261e*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5261f*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52620*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52621*4+0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x52622*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x52623*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x52624*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52625*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52626*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52627*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52628*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52629*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x5262a*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5262b*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5262c*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5262d*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5262e*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5262f*4+0x02000000,0xdb30); +reg_write( DDR_REG_BASE +0x52630*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52631*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52632*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52633*4+0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x52634*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x52635*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52636*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52637*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52638*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52639*4+0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x5263a*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x5263b*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x5263c*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5263d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5263e*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5263f*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52640*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52641*4+0x02000000,0xc1a6); +reg_write( DDR_REG_BASE +0x52642*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x52643*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52644*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x52645*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52646*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x52647*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x52648*4+0x02000000,0xffd); +reg_write( DDR_REG_BASE +0x52649*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x5264a*4+0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x5264b*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5264c*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5264d*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x5264e*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x5264f*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x52650*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52651*4+0x02000000,0x8e19); +reg_write( DDR_REG_BASE +0x52652*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52653*4+0x02000000,0x8e10); +reg_write( DDR_REG_BASE +0x52654*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52655*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52656*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x52657*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x52658*4+0x02000000,0x9001); +reg_write( DDR_REG_BASE +0x52659*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5265a*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5265b*4+0x02000000,0xe88a); +reg_write( DDR_REG_BASE +0x5265c*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5265d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5265e*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x5265f*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x52660*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x52661*4+0x02000000,0xcfe); +reg_write( DDR_REG_BASE +0x52662*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52663*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x52664*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52665*4+0x02000000,0x956); +reg_write( DDR_REG_BASE +0x52666*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52667*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52668*4+0x02000000,0x8608); +reg_write( DDR_REG_BASE +0x52669*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x5266a*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5266b*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5266c*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5266d*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5266e*4+0x02000000,0xe064); +reg_write( DDR_REG_BASE +0x5266f*4+0x02000000,0xce6); +reg_write( DDR_REG_BASE +0x52670*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x52671*4+0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x52672*4+0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x52673*4+0x02000000,0xaba); +reg_write( DDR_REG_BASE +0x52674*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x52675*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52676*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52677*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52678*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52679*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x5267a*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x5267b*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x5267c*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5267d*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5267e*4+0x02000000,0xe064); +reg_write( DDR_REG_BASE +0x5267f*4+0x02000000,0x2042); +reg_write( DDR_REG_BASE +0x52680*4+0x02000000,0x98f); +reg_write( DDR_REG_BASE +0x52681*4+0x02000000,0xb7a0); +reg_write( DDR_REG_BASE +0x52682*4+0x02000000,0xb7a0); +reg_write( DDR_REG_BASE +0x52683*4+0x02000000,0x1f9c); +reg_write( DDR_REG_BASE +0x52684*4+0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x52685*4+0x02000000,0x1f9b); +reg_write( DDR_REG_BASE +0x52686*4+0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x52687*4+0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x52688*4+0x02000000,0x9f84); +reg_write( DDR_REG_BASE +0x52689*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5268a*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x5268b*4+0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x5268c*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x5268d*4+0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x5268e*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x5268f*4+0x02000000,0xd7a); +reg_write( DDR_REG_BASE +0x52690*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52691*4+0x02000000,0x960e); +reg_write( DDR_REG_BASE +0x52692*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x52693*4+0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x52694*4+0x02000000,0xcaa); +reg_write( DDR_REG_BASE +0x52695*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52696*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52697*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52698*4+0x02000000,0x8ee); +reg_write( DDR_REG_BASE +0x52699*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5269a*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x5269b*4+0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x5269c*4+0x02000000,0xa66); +reg_write( DDR_REG_BASE +0x5269d*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5269e*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5269f*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x526a0*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x526a1*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x526a2*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x526a3*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x526a4*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x526a5*4+0x02000000,0xb7a0); +reg_write( DDR_REG_BASE +0x526a6*4+0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x526a7*4+0x02000000,0x9f84); +reg_write( DDR_REG_BASE +0x526a8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x526a9*4+0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x526aa*4+0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x526ab*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x526ac*4+0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x526ad*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x526ae*4+0x02000000,0xd3a); +reg_write( DDR_REG_BASE +0x526af*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x526b0*4+0x02000000,0x960a); +reg_write( DDR_REG_BASE +0x526b1*4+0x02000000,0x8e58); +reg_write( DDR_REG_BASE +0x526b2*4+0x02000000,0x8601); +reg_write( DDR_REG_BASE +0x526b3*4+0x02000000,0xbde); +reg_write( DDR_REG_BASE +0x526b4*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x526b5*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x526b6*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x526b7*4+0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x526b8*4+0x02000000,0xc62); +reg_write( DDR_REG_BASE +0x526b9*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x526ba*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x526bb*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x526bc*4+0x02000000,0x8a6); +reg_write( DDR_REG_BASE +0x526bd*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x526be*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x526bf*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x526c0*4+0x02000000,0xe807); +reg_write( DDR_REG_BASE +0x526c1*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x526c2*4+0x02000000,0xfba); +reg_write( DDR_REG_BASE +0x526c3*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x526c4*4+0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x526c5*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x526c6*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x526c7*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x526c8*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x526c9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x526ca*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x526cb*4+0x02000000,0x4220); +reg_write( DDR_REG_BASE +0x526cc*4+0x02000000,0x7414); +reg_write( DDR_REG_BASE +0x526cd*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x526ce*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x526cf*4+0x02000000,0xfffe); +reg_write( DDR_REG_BASE +0x526d0*4+0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x526d1*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x526d2*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x526d3*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x526d4*4+0x02000000,0xc16); +reg_write( DDR_REG_BASE +0x526d5*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x526d6*4+0x02000000,0x4320); +reg_write( DDR_REG_BASE +0x526d7*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x526d8*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x526d9*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x526da*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x526db*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x526dc*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x526dd*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x526de*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x526df*4+0x02000000,0x9001); +reg_write( DDR_REG_BASE +0x526e0*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x526e1*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x526e2*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x526e3*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x526e4*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x526e5*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x526e6*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x526e7*4+0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x526e8*4+0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x526e9*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x526ea*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x526eb*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x526ec*4+0x02000000,0x7504); +reg_write( DDR_REG_BASE +0x526ed*4+0x02000000,0x9c6); +reg_write( DDR_REG_BASE +0x526ee*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x526ef*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x526f0*4+0x02000000,0x8608); +reg_write( DDR_REG_BASE +0x526f1*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x526f2*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x526f3*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x526f4*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x526f5*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x526f6*4+0x02000000,0xe064); +reg_write( DDR_REG_BASE +0x526f7*4+0x02000000,0xbd6); +reg_write( DDR_REG_BASE +0x526f8*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x526f9*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x526fa*4+0x02000000,0x6c4); +reg_write( DDR_REG_BASE +0x526fb*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x526fc*4+0x02000000,0x1f00); +reg_write( DDR_REG_BASE +0x526fd*4+0x02000000,0x16c4); +reg_write( DDR_REG_BASE +0x526fe*4+0x02000000,0x1f9c); +reg_write( DDR_REG_BASE +0x526ff*4+0x02000000,0x16dc); +reg_write( DDR_REG_BASE +0x52700*4+0x02000000,0x1f9b); +reg_write( DDR_REG_BASE +0x52701*4+0x02000000,0x16dc); +reg_write( DDR_REG_BASE +0x52702*4+0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x52703*4+0x02000000,0x9f84); +reg_write( DDR_REG_BASE +0x52704*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52705*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x52706*4+0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x52707*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x52708*4+0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x52709*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x5270a*4+0x02000000,0x960e); +reg_write( DDR_REG_BASE +0x5270b*4+0x02000000,0xc82); +reg_write( DDR_REG_BASE +0x5270c*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5270d*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x5270e*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x5270f*4+0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x52710*4+0x02000000,0xbb2); +reg_write( DDR_REG_BASE +0x52711*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52712*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52713*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52714*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52715*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52716*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52717*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x52718*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x52719*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x5271a*4+0x02000000,0xfea); +reg_write( DDR_REG_BASE +0x5271b*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5271c*4+0x02000000,0x1f00); +reg_write( DDR_REG_BASE +0x5271d*4+0x02000000,0x16c4); +reg_write( DDR_REG_BASE +0x5271e*4+0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x5271f*4+0x02000000,0x962); +reg_write( DDR_REG_BASE +0x52720*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x52721*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52722*4+0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x52723*4+0x02000000,0x9f84); +reg_write( DDR_REG_BASE +0x52724*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52725*4+0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x52726*4+0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x52727*4+0x02000000,0x9344); +reg_write( DDR_REG_BASE +0x52728*4+0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x52729*4+0x02000000,0x9344); +reg_write( DDR_REG_BASE +0x5272a*4+0x02000000,0x8605); +reg_write( DDR_REG_BASE +0x5272b*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5272c*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5272d*4+0x02000000,0xc3e); +reg_write( DDR_REG_BASE +0x5272e*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5272f*4+0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x52730*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x52731*4+0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x52732*4+0x02000000,0xb6e); +reg_write( DDR_REG_BASE +0x52733*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52734*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52735*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52736*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x52737*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52738*4+0x02000000,0xece); +reg_write( DDR_REG_BASE +0x52739*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5273a*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x5273b*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5273c*4+0x02000000,0x8e58); +reg_write( DDR_REG_BASE +0x5273d*4+0x02000000,0x8603); +reg_write( DDR_REG_BASE +0x5273e*4+0x02000000,0xac6); +reg_write( DDR_REG_BASE +0x5273f*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52740*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52741*4+0x02000000,0xc0a6); +reg_write( DDR_REG_BASE +0x52742*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52743*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52744*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52745*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52746*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52747*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52748*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52749*4+0x02000000,0xc1a8); +reg_write( DDR_REG_BASE +0x5274a*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x5274b*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5274c*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x5274d*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x5274e*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x5274f*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x52750*4+0x02000000,0xffd); +reg_write( DDR_REG_BASE +0x52751*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x52752*4+0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x52753*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52754*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52755*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x52756*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x52757*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x52758*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52759*4+0x02000000,0x8e19); +reg_write( DDR_REG_BASE +0x5275a*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5275b*4+0x02000000,0x8e10); +reg_write( DDR_REG_BASE +0x5275c*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5275d*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5275e*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x5275f*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x52760*4+0x02000000,0x9001); +reg_write( DDR_REG_BASE +0x52761*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52762*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52763*4+0x02000000,0xe88a); +reg_write( DDR_REG_BASE +0x52764*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52765*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52766*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x52767*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x52768*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x52769*4+0x02000000,0xaee); +reg_write( DDR_REG_BASE +0x5276a*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x5276b*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x5276c*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x5276d*4+0x02000000,0xf46); +reg_write( DDR_REG_BASE +0x5276e*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5276f*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52770*4+0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x52771*4+0x02000000,0x8608); +reg_write( DDR_REG_BASE +0x52772*4+0x02000000,0x2179); +reg_write( DDR_REG_BASE +0x52773*4+0x02000000,0x101); +reg_write( DDR_REG_BASE +0x52774*4+0x02000000,0xb52); +reg_write( DDR_REG_BASE +0x52775*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52776*4+0x02000000,0xc144); +reg_write( DDR_REG_BASE +0x52777*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52778*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52779*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x5277a*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x5277b*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x5277c*4+0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x5277d*4+0x02000000,0x8a6); +reg_write( DDR_REG_BASE +0x5277e*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5277f*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x52780*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52781*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x52782*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52783*4+0x02000000,0xe03e); +reg_write( DDR_REG_BASE +0x52784*4+0x02000000,0xb7a0); +reg_write( DDR_REG_BASE +0x52785*4+0x02000000,0x1f9b); +reg_write( DDR_REG_BASE +0x52786*4+0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x52787*4+0x02000000,0x1f9c); +reg_write( DDR_REG_BASE +0x52788*4+0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x52789*4+0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x5278a*4+0x02000000,0x9f84); +reg_write( DDR_REG_BASE +0x5278b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5278c*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x5278d*4+0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x5278e*4+0x02000000,0x9045); +reg_write( DDR_REG_BASE +0x5278f*4+0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x52790*4+0x02000000,0x9045); +reg_write( DDR_REG_BASE +0x52791*4+0x02000000,0x960e); +reg_write( DDR_REG_BASE +0x52792*4+0x02000000,0xb72); +reg_write( DDR_REG_BASE +0x52793*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52794*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52795*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x52796*4+0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x52797*4+0x02000000,0xaa6); +reg_write( DDR_REG_BASE +0x52798*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52799*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x5279a*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x5279b*4+0x02000000,0xeea); +reg_write( DDR_REG_BASE +0x5279c*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5279d*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x5279e*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x5279f*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x527a0*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x527a1*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x527a2*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x527a3*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x527a4*4+0x02000000,0xb7a0); +reg_write( DDR_REG_BASE +0x527a5*4+0x02000000,0xb4e); +reg_write( DDR_REG_BASE +0x527a6*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x527a7*4+0x02000000,0x960a); +reg_write( DDR_REG_BASE +0x527a8*4+0x02000000,0x8e58); +reg_write( DDR_REG_BASE +0x527a9*4+0x02000000,0x8602); +reg_write( DDR_REG_BASE +0x527aa*4+0x02000000,0x9ee); +reg_write( DDR_REG_BASE +0x527ab*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x527ac*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x527ad*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x527ae*4+0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x527af*4+0x02000000,0xa76); +reg_write( DDR_REG_BASE +0x527b0*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x527b1*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x527b2*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x527b3*4+0x02000000,0xeba); +reg_write( DDR_REG_BASE +0x527b4*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x527b5*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x527b6*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x527b7*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x527b8*4+0x02000000,0xdce); +reg_write( DDR_REG_BASE +0x527b9*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x527ba*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x527bb*4+0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x527bc*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x527bd*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x527be*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x527bf*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x527c0*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x527c1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x527c2*4+0x02000000,0xfffe); +reg_write( DDR_REG_BASE +0x527c3*4+0x02000000,0x7414); +reg_write( DDR_REG_BASE +0x527c4*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x527c5*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x527c6*4+0x02000000,0x81); +reg_write( DDR_REG_BASE +0x527c7*4+0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x527c8*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x527c9*4+0x02000000,0xa2e); +reg_write( DDR_REG_BASE +0x527ca*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x527cb*4+0x02000000,0x4320); +reg_write( DDR_REG_BASE +0x527cc*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x527cd*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x527ce*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x527cf*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x527d0*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x527d1*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x527d2*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x527d3*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x527d4*4+0x02000000,0x9001); +reg_write( DDR_REG_BASE +0x527d5*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x527d6*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x527d7*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x527d8*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x527d9*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x527da*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x527db*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x527dc*4+0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x527dd*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x527de*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x527df*4+0x02000000,0xe007); +reg_write( DDR_REG_BASE +0x527e0*4+0x02000000,0xfde); +reg_write( DDR_REG_BASE +0x527e1*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x527e2*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x527e3*4+0x02000000,0x8608); +reg_write( DDR_REG_BASE +0x527e4*4+0x02000000,0xa72); +reg_write( DDR_REG_BASE +0x527e5*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x527e6*4+0x02000000,0xc104); +reg_write( DDR_REG_BASE +0x527e7*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x527e8*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x527e9*4+0x02000000,0x1f00); +reg_write( DDR_REG_BASE +0x527ea*4+0x02000000,0x16c4); +reg_write( DDR_REG_BASE +0x527eb*4+0x02000000,0x1f9b); +reg_write( DDR_REG_BASE +0x527ec*4+0x02000000,0x16dc); +reg_write( DDR_REG_BASE +0x527ed*4+0x02000000,0x1f9c); +reg_write( DDR_REG_BASE +0x527ee*4+0x02000000,0x16dc); +reg_write( DDR_REG_BASE +0x527ef*4+0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x527f0*4+0x02000000,0x9f84); +reg_write( DDR_REG_BASE +0x527f1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x527f2*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x527f3*4+0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x527f4*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x527f5*4+0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x527f6*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x527f7*4+0x02000000,0x960e); +reg_write( DDR_REG_BASE +0x527f8*4+0x02000000,0xaa6); +reg_write( DDR_REG_BASE +0x527f9*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x527fa*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x527fb*4+0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x527fc*4+0x02000000,0xc200); +reg_write( DDR_REG_BASE +0x527fd*4+0x02000000,0x9da); +reg_write( DDR_REG_BASE +0x527fe*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x527ff*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52800*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x52801*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52802*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52803*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52804*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x52805*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x52806*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52807*4+0x02000000,0xe12); +reg_write( DDR_REG_BASE +0x52808*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52809*4+0x02000000,0x1f00); +reg_write( DDR_REG_BASE +0x5280a*4+0x02000000,0x16c4); +reg_write( DDR_REG_BASE +0x5280b*4+0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x5280c*4+0x02000000,0xf86); +reg_write( DDR_REG_BASE +0x5280d*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5280e*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5280f*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52810*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52811*4+0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x52812*4+0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x52813*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52814*4+0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x52815*4+0x02000000,0x9344); +reg_write( DDR_REG_BASE +0x52816*4+0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x52817*4+0x02000000,0x9344); +reg_write( DDR_REG_BASE +0x52818*4+0x02000000,0x8605); +reg_write( DDR_REG_BASE +0x52819*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5281a*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5281b*4+0x02000000,0xa62); +reg_write( DDR_REG_BASE +0x5281c*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5281d*4+0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x5281e*4+0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x5281f*4+0x02000000,0xc200); +reg_write( DDR_REG_BASE +0x52820*4+0x02000000,0x992); +reg_write( DDR_REG_BASE +0x52821*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52822*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52823*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52824*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x52825*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52826*4+0x02000000,0xcf2); +reg_write( DDR_REG_BASE +0x52827*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52828*4+0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x52829*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5282a*4+0x02000000,0x8e58); +reg_write( DDR_REG_BASE +0x5282b*4+0x02000000,0x8603); +reg_write( DDR_REG_BASE +0x5282c*4+0x02000000,0x8ea); +reg_write( DDR_REG_BASE +0x5282d*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5282e*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5282f*4+0x02000000,0xc0a8); +reg_write( DDR_REG_BASE +0x52830*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52831*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52832*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52833*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52834*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52835*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52836*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52837*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x52838*4+0x02000000,0x3503); +reg_write( DDR_REG_BASE +0x52839*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x5283a*4+0x02000000,0xdf6); +reg_write( DDR_REG_BASE +0x5283b*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5283c*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5283d*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5283e*4+0x02000000,0x7083); +reg_write( DDR_REG_BASE +0x5283f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52840*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52841*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52842*4+0x02000000,0xc088); +reg_write( DDR_REG_BASE +0x52843*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x52844*4+0x02000000,0xb52); +reg_write( DDR_REG_BASE +0x52845*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x52846*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x52847*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52848*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52849*4+0x02000000,0x2100); +reg_write( DDR_REG_BASE +0x5284a*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5284b*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x5284c*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5284d*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x5284e*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5284f*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52850*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52851*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52852*4+0x02000000,0xfec4); +reg_write( DDR_REG_BASE +0x52853*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x52854*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x52855*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x52856*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52857*4+0x02000000,0x4898); +reg_write( DDR_REG_BASE +0x52858*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52859*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x5285a*4+0x02000000,0xc145); +reg_write( DDR_REG_BASE +0x5285b*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5285c*4+0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x5285d*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x5285e*4+0x02000000,0x6941); +reg_write( DDR_REG_BASE +0x5285f*4+0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x52860*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x52861*4+0x02000000,0x44a9); +reg_write( DDR_REG_BASE +0x52862*4+0x02000000,0xe805); +reg_write( DDR_REG_BASE +0x52863*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x52864*4+0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x52865*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x52866*4+0x02000000,0x7c9b); +reg_write( DDR_REG_BASE +0x52867*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x52868*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52869*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5286a*4+0x02000000,0xe0c4); +reg_write( DDR_REG_BASE +0x5286b*4+0x02000000,0xb080); +reg_write( DDR_REG_BASE +0x5286c*4+0x02000000,0x4140); +reg_write( DDR_REG_BASE +0x5286d*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5286e*4+0x02000000,0x9e1); +reg_write( DDR_REG_BASE +0x5286f*4+0x02000000,0x8024); +reg_write( DDR_REG_BASE +0x52870*4+0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x52871*4+0x02000000,0x7c0); +reg_write( DDR_REG_BASE +0x52872*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x52873*4+0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x52874*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52875*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52876*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52877*4+0x02000000,0x709b); +reg_write( DDR_REG_BASE +0x52878*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52879*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x5287a*4+0x02000000,0xc346); +reg_write( DDR_REG_BASE +0x5287b*4+0x02000000,0xe598); +reg_write( DDR_REG_BASE +0x5287c*4+0x02000000,0x1d8); +reg_write( DDR_REG_BASE +0x5287d*4+0x02000000,0xd); +reg_write( DDR_REG_BASE +0x5287e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5287f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52880*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x52881*4+0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x52882*4+0x02000000,0xf015); +reg_write( DDR_REG_BASE +0x52883*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52884*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x52885*4+0x02000000,0x8c2); +reg_write( DDR_REG_BASE +0x52886*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52887*4+0x02000000,0x7a05); +reg_write( DDR_REG_BASE +0x52888*4+0x02000000,0xd8ef); +reg_write( DDR_REG_BASE +0x52889*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x5288a*4+0x02000000,0x6c0); +reg_write( DDR_REG_BASE +0x5288b*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x5288c*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5288d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5288e*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x5288f*4+0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x52890*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x52891*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52892*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52893*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52894*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52895*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52896*4+0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x52897*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x52898*4+0x02000000,0x6c7); +reg_write( DDR_REG_BASE +0x52899*4+0x02000000,0x9d7); +reg_write( DDR_REG_BASE +0x5289a*4+0x02000000,0x8005); +reg_write( DDR_REG_BASE +0x5289b*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5289c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5289d*4+0x02000000,0x2100); +reg_write( DDR_REG_BASE +0x5289e*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5289f*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x528a0*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x528a1*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x528a2*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x528a3*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x528a4*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x528a5*4+0x02000000,0xfe64); +reg_write( DDR_REG_BASE +0x528a6*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x528a7*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x528a8*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x528a9*4+0x02000000,0xf064); +reg_write( DDR_REG_BASE +0x528aa*4+0x02000000,0x711c); +reg_write( DDR_REG_BASE +0x528ab*4+0x02000000,0x86e); +reg_write( DDR_REG_BASE +0x528ac*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x528ad*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x528ae*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x528af*4+0x02000000,0x866); +reg_write( DDR_REG_BASE +0x528b0*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x528b1*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x528b2*4+0x02000000,0xcba); +reg_write( DDR_REG_BASE +0x528b3*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x528b4*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x528b5*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x528b6*4+0x02000000,0xe32); +reg_write( DDR_REG_BASE +0x528b7*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x528b8*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x528b9*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x528ba*4+0x02000000,0xdf7f); +reg_write( DDR_REG_BASE +0x528bb*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x528bc*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x528bd*4+0x02000000,0xe024); +reg_write( DDR_REG_BASE +0x528be*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x528bf*4+0x02000000,0xb6e0); +reg_write( DDR_REG_BASE +0x528c0*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x528c1*4+0x02000000,0xb606); +reg_write( DDR_REG_BASE +0x528c2*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x528c3*4+0x02000000,0x3c4); +reg_write( DDR_REG_BASE +0x528c4*4+0x02000000,0x1efe); +reg_write( DDR_REG_BASE +0x528c5*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x528c6*4+0x02000000,0xd818); +reg_write( DDR_REG_BASE +0x528c7*4+0x02000000,0x90a); +reg_write( DDR_REG_BASE +0x528c8*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x528c9*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x528ca*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x528cb*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x528cc*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x528cd*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x528ce*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x528cf*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x528d0*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x528d1*4+0x02000000,0xc7e); +reg_write( DDR_REG_BASE +0x528d2*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x528d3*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x528d4*4+0x02000000,0xd807); +reg_write( DDR_REG_BASE +0x528d5*4+0x02000000,0x8ee); +reg_write( DDR_REG_BASE +0x528d6*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x528d7*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x528d8*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x528d9*4+0x02000000,0xb6e0); +reg_write( DDR_REG_BASE +0x528da*4+0x02000000,0xb606); +reg_write( DDR_REG_BASE +0x528db*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x528dc*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x528dd*4+0x02000000,0xc66); +reg_write( DDR_REG_BASE +0x528de*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x528df*4+0x02000000,0x1efe); +reg_write( DDR_REG_BASE +0x528e0*4+0x02000000,0x93c5); +reg_write( DDR_REG_BASE +0x528e1*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x528e2*4+0x02000000,0x8d2); +reg_write( DDR_REG_BASE +0x528e3*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x528e4*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x528e5*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x528e6*4+0x02000000,0xc52); +reg_write( DDR_REG_BASE +0x528e7*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x528e8*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x528e9*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x528ea*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x528eb*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x528ec*4+0x02000000,0x1fc5); +reg_write( DDR_REG_BASE +0x528ed*4+0x02000000,0x1e0c); +reg_write( DDR_REG_BASE +0x528ee*4+0x02000000,0x1fc5); +reg_write( DDR_REG_BASE +0x528ef*4+0x02000000,0x8ba); +reg_write( DDR_REG_BASE +0x528f0*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x528f1*4+0x02000000,0x1efe); +reg_write( DDR_REG_BASE +0x528f2*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x528f3*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x528f4*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x528f5*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x528f6*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x528f7*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x528f8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x528f9*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x528fa*4+0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x528fb*4+0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x528fc*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x528fd*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x528fe*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x528ff*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x52900*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x52901*4+0x02000000,0xf05f); +reg_write( DDR_REG_BASE +0x52902*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x52903*4+0x02000000,0xf9f); +reg_write( DDR_REG_BASE +0x52904*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52905*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52906*4+0x02000000,0xc602); +reg_write( DDR_REG_BASE +0x52907*4+0x02000000,0xc400); +reg_write( DDR_REG_BASE +0x52908*4+0x02000000,0xf053); +reg_write( DDR_REG_BASE +0x52909*4+0x02000000,0x225f); +reg_write( DDR_REG_BASE +0x5290a*4+0x02000000,0x480); +reg_write( DDR_REG_BASE +0x5290b*4+0x02000000,0x74d5); +reg_write( DDR_REG_BASE +0x5290c*4+0x02000000,0x24c0); +reg_write( DDR_REG_BASE +0x5290d*4+0x02000000,0x1061); +reg_write( DDR_REG_BASE +0x5290e*4+0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x5290f*4+0x02000000,0x1061); +reg_write( DDR_REG_BASE +0x52910*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52911*4+0x02000000,0xc301); +reg_write( DDR_REG_BASE +0x52912*4+0x02000000,0xc088); +reg_write( DDR_REG_BASE +0x52913*4+0x02000000,0x631b); +reg_write( DDR_REG_BASE +0x52914*4+0x02000000,0x7bd4); +reg_write( DDR_REG_BASE +0x52915*4+0x02000000,0x9300); +reg_write( DDR_REG_BASE +0x52916*4+0x02000000,0xe0c0); +reg_write( DDR_REG_BASE +0x52917*4+0x02000000,0x88); +reg_write( DDR_REG_BASE +0x52918*4+0x02000000,0x25); +reg_write( DDR_REG_BASE +0x52919*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x5291a*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x5291b*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5291c*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5291d*4+0x02000000,0x7c0); +reg_write( DDR_REG_BASE +0x5291e*4+0x02000000,0x7f1b); +reg_write( DDR_REG_BASE +0x5291f*4+0x02000000,0x2705); +reg_write( DDR_REG_BASE +0x52920*4+0x02000000,0x178f); +reg_write( DDR_REG_BASE +0x52921*4+0x02000000,0x9700); +reg_write( DDR_REG_BASE +0x52922*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52923*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52924*4+0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x52925*4+0x02000000,0x1021); +reg_write( DDR_REG_BASE +0x52926*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x52927*4+0x02000000,0x21); +reg_write( DDR_REG_BASE +0x52928*4+0x02000000,0xb53); +reg_write( DDR_REG_BASE +0x52929*4+0x02000000,0x1030); +reg_write( DDR_REG_BASE +0x5292a*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5292b*4+0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x5292c*4+0x02000000,0x80d); +reg_write( DDR_REG_BASE +0x5292d*4+0x02000000,0xd0); +reg_write( DDR_REG_BASE +0x5292e*4+0x02000000,0x84b); +reg_write( DDR_REG_BASE +0x5292f*4+0x02000000,0x210); +reg_write( DDR_REG_BASE +0x52930*4+0x02000000,0x855); +reg_write( DDR_REG_BASE +0x52931*4+0x02000000,0x1d1); +reg_write( DDR_REG_BASE +0x52932*4+0x02000000,0x788f); +reg_write( DDR_REG_BASE +0x52933*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x52934*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52935*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52936*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x52937*4+0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x52938*4+0x02000000,0xc301); +reg_write( DDR_REG_BASE +0x52939*4+0x02000000,0x677f); +reg_write( DDR_REG_BASE +0x5293a*4+0x02000000,0x7f14); +reg_write( DDR_REG_BASE +0x5293b*4+0x02000000,0x6861); +reg_write( DDR_REG_BASE +0x5293c*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x5293d*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5293e*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5293f*4+0x02000000,0x7c0); +reg_write( DDR_REG_BASE +0x52940*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52941*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52942*4+0x02000000,0x780); +reg_write( DDR_REG_BASE +0x52943*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x52944*4+0x02000000,0xb700); +reg_write( DDR_REG_BASE +0x52945*4+0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x52946*4+0x02000000,0xee5); +reg_write( DDR_REG_BASE +0x52947*4+0x02000000,0x9025); +reg_write( DDR_REG_BASE +0x52948*4+0x02000000,0xc788); +reg_write( DDR_REG_BASE +0x52949*4+0x02000000,0xe25); +reg_write( DDR_REG_BASE +0x5294a*4+0x02000000,0x11d1); +reg_write( DDR_REG_BASE +0x5294b*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5294c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5294d*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x5294e*4+0x02000000,0x7854); +reg_write( DDR_REG_BASE +0x5294f*4+0x02000000,0xa8af); +reg_write( DDR_REG_BASE +0x52950*4+0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x52951*4+0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x52952*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x52953*4+0x02000000,0x9700); +reg_write( DDR_REG_BASE +0x52954*4+0x02000000,0xb300); +reg_write( DDR_REG_BASE +0x52955*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52956*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52957*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x52958*4+0x02000000,0x7854); +reg_write( DDR_REG_BASE +0x52959*4+0x02000000,0xa8b0); +reg_write( DDR_REG_BASE +0x5295a*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x5295b*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5295c*4+0x02000000,0xe5b); +reg_write( DDR_REG_BASE +0x5295d*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5295e*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x5295f*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x52960*4+0x02000000,0x7a2f); +reg_write( DDR_REG_BASE +0x52961*4+0x02000000,0x845); +reg_write( DDR_REG_BASE +0x52962*4+0x02000000,0x80a5); +reg_write( DDR_REG_BASE +0x52963*4+0x02000000,0x716d); +reg_write( DDR_REG_BASE +0x52964*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52965*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x52966*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52967*4+0x02000000,0xf315); +reg_write( DDR_REG_BASE +0x52968*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52969*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5296a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5296b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5296c*4+0x02000000,0xb8c3); +reg_write( DDR_REG_BASE +0x5296d*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5296e*4+0x02000000,0xf02f); +reg_write( DDR_REG_BASE +0x5296f*4+0x02000000,0xc502); +reg_write( DDR_REG_BASE +0x52970*4+0x02000000,0xf028); +reg_write( DDR_REG_BASE +0x52971*4+0x02000000,0x275f); +reg_write( DDR_REG_BASE +0x52972*4+0x02000000,0x1480); +reg_write( DDR_REG_BASE +0x52973*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52974*4+0x02000000,0x47); +reg_write( DDR_REG_BASE +0x52975*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x52976*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x52977*4+0x02000000,0x661e); +reg_write( DDR_REG_BASE +0x52978*4+0x02000000,0x26f4); +reg_write( DDR_REG_BASE +0x52979*4+0x02000000,0x1340); +reg_write( DDR_REG_BASE +0x5297a*4+0x02000000,0x43a1); +reg_write( DDR_REG_BASE +0x5297b*4+0x02000000,0xe5e); +reg_write( DDR_REG_BASE +0x5297c*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x5297d*4+0x02000000,0x20bc); +reg_write( DDR_REG_BASE +0x5297e*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5297f*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52980*4+0x02000000,0x271a); +reg_write( DDR_REG_BASE +0x52981*4+0x02000000,0x1f81); +reg_write( DDR_REG_BASE +0x52982*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52983*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52984*4+0x02000000,0x26f4); +reg_write( DDR_REG_BASE +0x52985*4+0x02000000,0x1342); +reg_write( DDR_REG_BASE +0x52986*4+0x02000000,0x2054); +reg_write( DDR_REG_BASE +0x52987*4+0x02000000,0xd00); +reg_write( DDR_REG_BASE +0x52988*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x52989*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x5298a*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x5298b*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5298c*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x5298d*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x5298e*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5298f*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52990*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52991*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52992*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52993*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x52994*4+0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x52995*4+0x02000000,0x2049); +reg_write( DDR_REG_BASE +0x52996*4+0x02000000,0xfc0); +reg_write( DDR_REG_BASE +0x52997*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x52998*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52999*4+0x02000000,0xdb3); +reg_write( DDR_REG_BASE +0x5299a*4+0x02000000,0x9024); +reg_write( DDR_REG_BASE +0x5299b*4+0x02000000,0xc688); +reg_write( DDR_REG_BASE +0x5299c*4+0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x5299d*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5299e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5299f*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x529a0*4+0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x529a1*4+0x02000000,0x272f); +reg_write( DDR_REG_BASE +0x529a2*4+0x02000000,0x16c7); +reg_write( DDR_REG_BASE +0x529a3*4+0x02000000,0x89b); +reg_write( DDR_REG_BASE +0x529a4*4+0x02000000,0x83c5); +reg_write( DDR_REG_BASE +0x529a5*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x529a6*4+0x02000000,0x889); +reg_write( DDR_REG_BASE +0x529a7*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x529a8*4+0x02000000,0x9da); +reg_write( DDR_REG_BASE +0x529a9*4+0x02000000,0xfe4f); +reg_write( DDR_REG_BASE +0x529aa*4+0x02000000,0x4308); +reg_write( DDR_REG_BASE +0x529ab*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x529ac*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x529ad*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x529ae*4+0x02000000,0x8881); +reg_write( DDR_REG_BASE +0x529af*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x529b0*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x529b1*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x529b2*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x529b3*4+0x02000000,0xf034); +reg_write( DDR_REG_BASE +0x529b4*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x529b5*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x529b6*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x529b7*4+0x02000000,0x79b4); +reg_write( DDR_REG_BASE +0x529b8*4+0x02000000,0x896f); +reg_write( DDR_REG_BASE +0x529b9*4+0x02000000,0x8950); +reg_write( DDR_REG_BASE +0x529ba*4+0x02000000,0x4a76); +reg_write( DDR_REG_BASE +0x529bb*4+0x02000000,0x4b51); +reg_write( DDR_REG_BASE +0x529bc*4+0x02000000,0x7270); +reg_write( DDR_REG_BASE +0x529bd*4+0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x529be*4+0x02000000,0x38d); +reg_write( DDR_REG_BASE +0x529bf*4+0x02000000,0x7e2f); +reg_write( DDR_REG_BASE +0x529c0*4+0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x529c1*4+0x02000000,0x12ce); +reg_write( DDR_REG_BASE +0x529c2*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x529c3*4+0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x529c4*4+0x02000000,0x122d); +reg_write( DDR_REG_BASE +0x529c5*4+0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x529c6*4+0x02000000,0x12d); +reg_write( DDR_REG_BASE +0x529c7*4+0x02000000,0x2e44); +reg_write( DDR_REG_BASE +0x529c8*4+0x02000000,0x180e); +reg_write( DDR_REG_BASE +0x529c9*4+0x02000000,0xf019); +reg_write( DDR_REG_BASE +0x529ca*4+0x02000000,0xc203); +reg_write( DDR_REG_BASE +0x529cb*4+0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x529cc*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x529cd*4+0x02000000,0x2254); +reg_write( DDR_REG_BASE +0x529ce*4+0x02000000,0xd03); +reg_write( DDR_REG_BASE +0x529cf*4+0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x529d0*4+0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x529d1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x529d2*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x529d3*4+0x02000000,0x7a65); +reg_write( DDR_REG_BASE +0x529d4*4+0x02000000,0x7945); +reg_write( DDR_REG_BASE +0x529d5*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x529d6*4+0x02000000,0xb991); +reg_write( DDR_REG_BASE +0x529d7*4+0x02000000,0xb99c); +reg_write( DDR_REG_BASE +0x529d8*4+0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x529d9*4+0x02000000,0x9160); +reg_write( DDR_REG_BASE +0x529da*4+0x02000000,0x7ad0); +reg_write( DDR_REG_BASE +0x529db*4+0x02000000,0x627a); +reg_write( DDR_REG_BASE +0x529dc*4+0x02000000,0x2249); +reg_write( DDR_REG_BASE +0x529dd*4+0x02000000,0xfc2); +reg_write( DDR_REG_BASE +0x529de*4+0x02000000,0xb140); +reg_write( DDR_REG_BASE +0x529df*4+0x02000000,0x210a); +reg_write( DDR_REG_BASE +0x529e0*4+0x02000000,0x780); +reg_write( DDR_REG_BASE +0x529e1*4+0x02000000,0x9d5); +reg_write( DDR_REG_BASE +0x529e2*4+0x02000000,0x83e4); +reg_write( DDR_REG_BASE +0x529e3*4+0x02000000,0x2140); +reg_write( DDR_REG_BASE +0x529e4*4+0x02000000,0x5e); +reg_write( DDR_REG_BASE +0x529e5*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x529e6*4+0x02000000,0x7d0f); +reg_write( DDR_REG_BASE +0x529e7*4+0x02000000,0xc9d); +reg_write( DDR_REG_BASE +0x529e8*4+0x02000000,0x9365); +reg_write( DDR_REG_BASE +0x529e9*4+0x02000000,0xdf09); +reg_write( DDR_REG_BASE +0x529ea*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x529eb*4+0x02000000,0x3503); +reg_write( DDR_REG_BASE +0x529ec*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x529ed*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x529ee*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x529ef*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x529f0*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x529f1*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x529f2*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x529f3*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x529f4*4+0x02000000,0x3d0a); +reg_write( DDR_REG_BASE +0x529f5*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x529f6*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x529f7*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x529f8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x529f9*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x529fa*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x529fb*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x529fc*4+0x02000000,0x4a); +reg_write( DDR_REG_BASE +0x529fd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x529fe*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x529ff*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52a00*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52a01*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a02*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52a03*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52a04*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52a05*4+0x02000000,0x86); +reg_write( DDR_REG_BASE +0x52a06*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x52a07*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x52a08*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52a09*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52a0a*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52a0b*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52a0c*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52a0d*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52a0e*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52a0f*4+0x02000000,0xd36); +reg_write( DDR_REG_BASE +0x52a10*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52a11*4+0x02000000,0x2052); +reg_write( DDR_REG_BASE +0x52a12*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a13*4+0x02000000,0x8ae); +reg_write( DDR_REG_BASE +0x52a14*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52a15*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52a16*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x52a17*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52a18*4+0x02000000,0xff68); +reg_write( DDR_REG_BASE +0x52a19*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52a1a*4+0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x52a1b*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52a1c*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x52a1d*4+0x02000000,0x1a00); +reg_write( DDR_REG_BASE +0x52a1e*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x52a1f*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x52a20*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52a21*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x52a22*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52a23*4+0x02000000,0x7ca); +reg_write( DDR_REG_BASE +0x52a24*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x52a25*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x52a26*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x52a27*4+0x02000000,0xed06); +reg_write( DDR_REG_BASE +0x52a28*4+0x02000000,0xbd61); +reg_write( DDR_REG_BASE +0x52a29*4+0x02000000,0xd01); +reg_write( DDR_REG_BASE +0x52a2a*4+0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x52a2b*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52a2c*4+0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x52a2d*4+0x02000000,0x103); +reg_write( DDR_REG_BASE +0x52a2e*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52a2f*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x52a30*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52a31*4+0x02000000,0x1ea); +reg_write( DDR_REG_BASE +0x52a32*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52a33*4+0x02000000,0x12c3); +reg_write( DDR_REG_BASE +0x52a34*4+0x02000000,0x700); +reg_write( DDR_REG_BASE +0x52a35*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52a36*4+0x02000000,0xca0a); +reg_write( DDR_REG_BASE +0x52a37*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x52a38*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x52a39*4+0x02000000,0xf40c); +reg_write( DDR_REG_BASE +0x52a3a*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52a3b*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x52a3c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52a3d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a3e*4+0x02000000,0xb8e5); +reg_write( DDR_REG_BASE +0x52a3f*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52a40*4+0x02000000,0xf204); +reg_write( DDR_REG_BASE +0x52a41*4+0x02000000,0x8f00); +reg_write( DDR_REG_BASE +0x52a42*4+0x02000000,0x1a0a); +reg_write( DDR_REG_BASE +0x52a43*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x52a44*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x52a45*4+0x02000000,0x230f); +reg_write( DDR_REG_BASE +0x52a46*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x52a47*4+0x02000000,0xc149); +reg_write( DDR_REG_BASE +0x52a48*4+0x02000000,0x2379); +reg_write( DDR_REG_BASE +0x52a49*4+0x02000000,0x3001); +reg_write( DDR_REG_BASE +0x52a4a*4+0x02000000,0x7224); +reg_write( DDR_REG_BASE +0x52a4b*4+0x02000000,0xc14a); +reg_write( DDR_REG_BASE +0x52a4c*4+0x02000000,0x8f20); +reg_write( DDR_REG_BASE +0x52a4d*4+0x02000000,0x33b); +reg_write( DDR_REG_BASE +0x52a4e*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52a4f*4+0x02000000,0x2139); +reg_write( DDR_REG_BASE +0x52a50*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a51*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52a52*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52a53*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52a54*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52a55*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a56*4+0x02000000,0xc0ff); +reg_write( DDR_REG_BASE +0x52a57*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52a58*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52a59*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a5a*4+0x02000000,0x3f00); +reg_write( DDR_REG_BASE +0x52a5b*4+0x02000000,0x2080); +reg_write( DDR_REG_BASE +0x52a5c*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52a5d*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52a5e*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52a5f*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52a60*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52a61*4+0x02000000,0x1ea); +reg_write( DDR_REG_BASE +0x52a62*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52a63*4+0x02000000,0x7384); +reg_write( DDR_REG_BASE +0x52a64*4+0x02000000,0x900f); +reg_write( DDR_REG_BASE +0x52a65*4+0x02000000,0xe022); +reg_write( DDR_REG_BASE +0x52a66*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52a67*4+0x02000000,0x762c); +reg_write( DDR_REG_BASE +0x52a68*4+0x02000000,0xb8a5); +reg_write( DDR_REG_BASE +0x52a69*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52a6a*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52a6b*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52a6c*4+0x02000000,0xe0ee); +reg_write( DDR_REG_BASE +0x52a6d*4+0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x52a6e*4+0x02000000,0xf7e); +reg_write( DDR_REG_BASE +0x52a6f*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x52a70*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52a71*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x52a72*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52a73*4+0x02000000,0xed08); +reg_write( DDR_REG_BASE +0x52a74*4+0x02000000,0xb82); +reg_write( DDR_REG_BASE +0x52a75*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x52a76*4+0x02000000,0x2578); +reg_write( DDR_REG_BASE +0x52a77*4+0x02000000,0x1081); +reg_write( DDR_REG_BASE +0x52a78*4+0x02000000,0x2c9); +reg_write( DDR_REG_BASE +0x52a79*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a7a*4+0x02000000,0x976); +reg_write( DDR_REG_BASE +0x52a7b*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52a7c*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52a7d*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52a7e*4+0x02000000,0x709b); +reg_write( DDR_REG_BASE +0x52a7f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52a80*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52a81*4+0x02000000,0x8ee); +reg_write( DDR_REG_BASE +0x52a82*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52a83*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x52a84*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x52a85*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52a86*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52a87*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a88*4+0x02000000,0x258); +reg_write( DDR_REG_BASE +0x52a89*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52a8a*4+0x02000000,0xec6); +reg_write( DDR_REG_BASE +0x52a8b*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x52a8c*4+0x02000000,0xda5a); +reg_write( DDR_REG_BASE +0x52a8d*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52a8e*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52a8f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a90*4+0x02000000,0x1a4); +reg_write( DDR_REG_BASE +0x52a91*4+0x02000000,0xeba); +reg_write( DDR_REG_BASE +0x52a92*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x52a93*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x52a94*4+0x02000000,0xdda); +reg_write( DDR_REG_BASE +0x52a95*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x52a96*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x52a97*4+0x02000000,0xb04); +reg_write( DDR_REG_BASE +0x52a98*4+0x02000000,0xd72); +reg_write( DDR_REG_BASE +0x52a99*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x52a9a*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52a9b*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52a9c*4+0x02000000,0x7384); +reg_write( DDR_REG_BASE +0x52a9d*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52a9e*4+0x02000000,0xfec4); +reg_write( DDR_REG_BASE +0x52a9f*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52aa0*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x52aa1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52aa2*4+0x02000000,0xe008); +reg_write( DDR_REG_BASE +0x52aa3*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52aa4*4+0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x52aa5*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x52aa6*4+0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x52aa7*4+0x02000000,0x17c0); +reg_write( DDR_REG_BASE +0x52aa8*4+0x02000000,0x6e21); +reg_write( DDR_REG_BASE +0x52aa9*4+0x02000000,0x269a); +reg_write( DDR_REG_BASE +0x52aaa*4+0x02000000,0x1008); +reg_write( DDR_REG_BASE +0x52aab*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x52aac*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x52aad*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x52aae*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x52aaf*4+0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x52ab0*4+0x02000000,0x2605); +reg_write( DDR_REG_BASE +0x52ab1*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x52ab2*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52ab3*4+0x02000000,0xe0c4); +reg_write( DDR_REG_BASE +0x52ab4*4+0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x52ab5*4+0x02000000,0x4628); +reg_write( DDR_REG_BASE +0x52ab6*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52ab7*4+0x02000000,0xedf); +reg_write( DDR_REG_BASE +0x52ab8*4+0x02000000,0x9024); +reg_write( DDR_REG_BASE +0x52ab9*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52aba*4+0x02000000,0xd880); +reg_write( DDR_REG_BASE +0x52abb*4+0x02000000,0xb88e); +reg_write( DDR_REG_BASE +0x52abc*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52abd*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52abe*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52abf*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x52ac0*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x52ac1*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52ac2*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52ac3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52ac4*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52ac5*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52ac6*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52ac7*4+0x02000000,0xfe86); +reg_write( DDR_REG_BASE +0x52ac8*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52ac9*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52aca*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52acb*4+0x02000000,0x86); +reg_write( DDR_REG_BASE +0x52acc*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x52acd*4+0x02000000,0xb8a0); +reg_write( DDR_REG_BASE +0x52ace*4+0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x52acf*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52ad0*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x52ad1*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x52ad2*4+0x02000000,0x8f03); +reg_write( DDR_REG_BASE +0x52ad3*4+0x02000000,0xda3f); +reg_write( DDR_REG_BASE +0x52ad4*4+0x02000000,0xf643); +reg_write( DDR_REG_BASE +0x52ad5*4+0x02000000,0x2844); +reg_write( DDR_REG_BASE +0x52ad6*4+0x02000000,0x102); +reg_write( DDR_REG_BASE +0x52ad7*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x52ad8*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52ad9*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52ada*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52adb*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x52adc*4+0x02000000,0x8f24); +reg_write( DDR_REG_BASE +0x52add*4+0x02000000,0x43c1); +reg_write( DDR_REG_BASE +0x52ade*4+0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x52adf*4+0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x52ae0*4+0x02000000,0x7864); +reg_write( DDR_REG_BASE +0x52ae1*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x52ae2*4+0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x52ae3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52ae4*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52ae5*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x52ae6*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x52ae7*4+0x02000000,0x2054); +reg_write( DDR_REG_BASE +0x52ae8*4+0x02000000,0xd00); +reg_write( DDR_REG_BASE +0x52ae9*4+0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x52aea*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52aeb*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52aec*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52aed*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52aee*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52aef*4+0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x52af0*4+0x02000000,0x786f); +reg_write( DDR_REG_BASE +0x52af1*4+0x02000000,0x9e1); +reg_write( DDR_REG_BASE +0x52af2*4+0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x52af3*4+0x02000000,0xd8ef); +reg_write( DDR_REG_BASE +0x52af4*4+0x02000000,0x228a); +reg_write( DDR_REG_BASE +0x52af5*4+0x02000000,0x7c4); +reg_write( DDR_REG_BASE +0x52af6*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52af7*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52af8*4+0x02000000,0xe024); +reg_write( DDR_REG_BASE +0x52af9*4+0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x52afa*4+0x02000000,0x228a); +reg_write( DDR_REG_BASE +0x52afb*4+0x02000000,0x3c4); +reg_write( DDR_REG_BASE +0x52afc*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x52afd*4+0x02000000,0x180c); +reg_write( DDR_REG_BASE +0x52afe*4+0x02000000,0x45); +reg_write( DDR_REG_BASE +0x52aff*4+0x02000000,0x18fe); +reg_write( DDR_REG_BASE +0x52b00*4+0x02000000,0x8084); +reg_write( DDR_REG_BASE +0x52b01*4+0x02000000,0xf09f); +reg_write( DDR_REG_BASE +0x52b02*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x52b03*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x52b04*4+0x02000000,0x8c2); +reg_write( DDR_REG_BASE +0x52b05*4+0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x52b06*4+0x02000000,0x7a05); +reg_write( DDR_REG_BASE +0x52b07*4+0x02000000,0xd8ef); +reg_write( DDR_REG_BASE +0x52b08*4+0x02000000,0x78c4); +reg_write( DDR_REG_BASE +0x52b09*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x52b0a*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52b0b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52b0c*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52b0d*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x52b0e*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x52b0f*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52b10*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52b11*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52b12*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52b13*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52b14*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x52b15*4+0x02000000,0x6c4); +reg_write( DDR_REG_BASE +0x52b16*4+0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x52b17*4+0x02000000,0x9d9); +reg_write( DDR_REG_BASE +0x52b18*4+0x02000000,0x8005); +reg_write( DDR_REG_BASE +0x52b19*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52b1a*4+0x02000000,0xfea); +reg_write( DDR_REG_BASE +0x52b1b*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52b1c*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52b1d*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x52b1e*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52b1f*4+0x02000000,0xfe64); +reg_write( DDR_REG_BASE +0x52b20*4+0x02000000,0xb82); +reg_write( DDR_REG_BASE +0x52b21*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x52b22*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x52b23*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x52b24*4+0x02000000,0xb7a); +reg_write( DDR_REG_BASE +0x52b25*4+0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x52b26*4+0x02000000,0xa3a); +reg_write( DDR_REG_BASE +0x52b27*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x52b28*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52b29*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52b2a*4+0x02000000,0x94a); +reg_write( DDR_REG_BASE +0x52b2b*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52b2c*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x52b2d*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x52b2e*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x52b2f*4+0x02000000,0xc3a); +reg_write( DDR_REG_BASE +0x52b30*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52b31*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52b32*4+0x02000000,0xc08f); +reg_write( DDR_REG_BASE +0x52b33*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52b34*4+0x02000000,0xada); +reg_write( DDR_REG_BASE +0x52b35*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52b36*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52b37*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52b38*4+0x02000000,0xfae); +reg_write( DDR_REG_BASE +0x52b39*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52b3a*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52b3b*4+0x02000000,0xd87f); +reg_write( DDR_REG_BASE +0x52b3c*4+0x02000000,0xb4a); +reg_write( DDR_REG_BASE +0x52b3d*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x52b3e*4+0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x52b3f*4+0x02000000,0xb46); +reg_write( DDR_REG_BASE +0x52b40*4+0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x52b41*4+0x02000000,0xa06); +reg_write( DDR_REG_BASE +0x52b42*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x52b43*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52b44*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x52b45*4+0x02000000,0x916); +reg_write( DDR_REG_BASE +0x52b46*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52b47*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x52b48*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x52b49*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x52b4a*4+0x02000000,0xc02); +reg_write( DDR_REG_BASE +0x52b4b*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52b4c*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52b4d*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x52b4e*4+0x02000000,0x3f00); +reg_write( DDR_REG_BASE +0x52b4f*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52b50*4+0x02000000,0xaa2); +reg_write( DDR_REG_BASE +0x52b51*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52b52*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52b53*4+0x02000000,0x8f03); +reg_write( DDR_REG_BASE +0x52b54*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52b55*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x52b56*4+0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x52b57*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x52b58*4+0x02000000,0xf03f); +reg_write( DDR_REG_BASE +0x52b59*4+0x02000000,0xc08c); +reg_write( DDR_REG_BASE +0x52b5a*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52b5b*4+0x02000000,0xd26); +reg_write( DDR_REG_BASE +0x52b5c*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x52b5d*4+0x02000000,0xda09); +reg_write( DDR_REG_BASE +0x52b5e*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52b5f*4+0x02000000,0xf030); +reg_write( DDR_REG_BASE +0x52b60*4+0x02000000,0x787b); +reg_write( DDR_REG_BASE +0x52b61*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x52b62*4+0x02000000,0xf87); +reg_write( DDR_REG_BASE +0x52b63*4+0x02000000,0xc18f); +reg_write( DDR_REG_BASE +0x52b64*4+0x02000000,0x2135); +reg_write( DDR_REG_BASE +0x52b65*4+0x02000000,0xb); +reg_write( DDR_REG_BASE +0x52b66*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x52b67*4+0x02000000,0x3f01); +reg_write( DDR_REG_BASE +0x52b68*4+0x02000000,0x2135); +reg_write( DDR_REG_BASE +0x52b69*4+0x02000000,0xe); +reg_write( DDR_REG_BASE +0x52b6a*4+0x02000000,0x2602); +reg_write( DDR_REG_BASE +0x52b6b*4+0x02000000,0x12c0); +reg_write( DDR_REG_BASE +0x52b6c*4+0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x52b6d*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x52b6e*4+0x02000000,0xc08c); +reg_write( DDR_REG_BASE +0x52b6f*4+0x02000000,0x60b8); +reg_write( DDR_REG_BASE +0x52b70*4+0x02000000,0xa840); +reg_write( DDR_REG_BASE +0x52b71*4+0x02000000,0x7c4f); +reg_write( DDR_REG_BASE +0x52b72*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x52b73*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52b74*4+0x02000000,0x241); +reg_write( DDR_REG_BASE +0x52b75*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52b76*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52b77*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52b78*4+0x02000000,0x258); +reg_write( DDR_REG_BASE +0x52b79*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x52b7a*4+0x02000000,0x60b8); +reg_write( DDR_REG_BASE +0x52b7b*4+0x02000000,0x8820); +reg_write( DDR_REG_BASE +0x52b7c*4+0x02000000,0x921); +reg_write( DDR_REG_BASE +0x52b7d*4+0x02000000,0x305); +reg_write( DDR_REG_BASE +0x52b7e*4+0x02000000,0xa840); +reg_write( DDR_REG_BASE +0x52b7f*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x52b80*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52b81*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x52b82*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52b83*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52b84*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52b85*4+0x02000000,0x1a4); +reg_write( DDR_REG_BASE +0x52b86*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x52b87*4+0x02000000,0x2300); +reg_write( DDR_REG_BASE +0x52b88*4+0x02000000,0x1381); +reg_write( DDR_REG_BASE +0x52b89*4+0x02000000,0x78b4); +reg_write( DDR_REG_BASE +0x52b8a*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x52b8b*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x52b8c*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x52b8d*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x52b8e*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52b8f*4+0x02000000,0xda5); +reg_write( DDR_REG_BASE +0x52b90*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52b91*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52b92*4+0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x52b93*4+0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x52b94*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52b95*4+0x02000000,0x23c0); +reg_write( DDR_REG_BASE +0x52b96*4+0x02000000,0x61); +reg_write( DDR_REG_BASE +0x52b97*4+0x02000000,0x8f24); +reg_write( DDR_REG_BASE +0x52b98*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x52b99*4+0x02000000,0x787); +reg_write( DDR_REG_BASE +0x52b9a*4+0x02000000,0x97f); +reg_write( DDR_REG_BASE +0x52b9b*4+0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x52b9c*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x52b9d*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x52b9e*4+0x02000000,0x7467); +reg_write( DDR_REG_BASE +0x52b9f*4+0x02000000,0x234c); +reg_write( DDR_REG_BASE +0x52ba0*4+0x02000000,0xb780); +reg_write( DDR_REG_BASE +0x52ba1*4+0x02000000,0x6ec); +reg_write( DDR_REG_BASE +0x52ba2*4+0x02000000,0xffce); +reg_write( DDR_REG_BASE +0x52ba3*4+0x02000000,0xf036); +reg_write( DDR_REG_BASE +0x52ba4*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52ba5*4+0x02000000,0xf02e); +reg_write( DDR_REG_BASE +0x52ba6*4+0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x52ba7*4+0x02000000,0x3241); +reg_write( DDR_REG_BASE +0x52ba8*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52ba9*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52baa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52bab*4+0x02000000,0x258); +reg_write( DDR_REG_BASE +0x52bac*4+0x02000000,0x43a1); +reg_write( DDR_REG_BASE +0x52bad*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x52bae*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52baf*4+0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x52bb0*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x52bb1*4+0x02000000,0x9f2); +reg_write( DDR_REG_BASE +0x52bb2*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52bb3*4+0x02000000,0x60a8); +reg_write( DDR_REG_BASE +0x52bb4*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x52bb5*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x52bb6*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52bb7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52bb8*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52bb9*4+0x02000000,0x229a); +reg_write( DDR_REG_BASE +0x52bba*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x52bbb*4+0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x52bbc*4+0x02000000,0x3481); +reg_write( DDR_REG_BASE +0x52bbd*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x52bbe*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52bbf*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x52bc0*4+0x02000000,0x7a05); +reg_write( DDR_REG_BASE +0x52bc1*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52bc2*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52bc3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52bc4*4+0x02000000,0x1a4); +reg_write( DDR_REG_BASE +0x52bc5*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x52bc6*4+0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x52bc7*4+0x02000000,0x340); +reg_write( DDR_REG_BASE +0x52bc8*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x52bc9*4+0x02000000,0xcc); +reg_write( DDR_REG_BASE +0x52bca*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x52bcb*4+0x02000000,0x2342); +reg_write( DDR_REG_BASE +0x52bcc*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x52bcd*4+0x02000000,0x7a05); +reg_write( DDR_REG_BASE +0x52bce*4+0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x52bcf*4+0x02000000,0x340); +reg_write( DDR_REG_BASE +0x52bd0*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x52bd1*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x52bd2*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52bd3*4+0x02000000,0xda9); +reg_write( DDR_REG_BASE +0x52bd4*4+0x02000000,0x9024); +reg_write( DDR_REG_BASE +0x52bd5*4+0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x52bd6*4+0x02000000,0x8f24); +reg_write( DDR_REG_BASE +0x52bd7*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x52bd8*4+0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x52bd9*4+0x02000000,0x999); +reg_write( DDR_REG_BASE +0x52bda*4+0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x52bdb*4+0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x52bdc*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52bdd*4+0x02000000,0xb885); +reg_write( DDR_REG_BASE +0x52bde*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52bdf*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52be0*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52be1*4+0x02000000,0xe0ee); +reg_write( DDR_REG_BASE +0x52be2*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52be3*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52be4*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52be5*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52be6*4+0x02000000,0x1ea); +reg_write( DDR_REG_BASE +0x52be7*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x52be8*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52be9*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52bea*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x52beb*4+0x02000000,0x7d0f); +reg_write( DDR_REG_BASE +0x52bec*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x52bed*4+0x02000000,0x70b1); +reg_write( DDR_REG_BASE +0x52bee*4+0x02000000,0x4c6); +reg_write( DDR_REG_BASE +0x52bef*4+0x02000000,0xffed); +reg_write( DDR_REG_BASE +0x52bf0*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x52bf1*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x52bf2*4+0x02000000,0x3d0a); +reg_write( DDR_REG_BASE +0x52bf3*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52bf4*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52bf5*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52bf6*4+0x02000000,0xc0e6); +reg_write( DDR_REG_BASE +0x52bf7*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x52bf8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52bf9*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x52bfa*4+0x02000000,0x8ba0); +reg_write( DDR_REG_BASE +0x52bfb*4+0x02000000,0x8b81); +reg_write( DDR_REG_BASE +0x52bfc*4+0x02000000,0x251f); +reg_write( DDR_REG_BASE +0x52bfd*4+0x02000000,0x108f); +reg_write( DDR_REG_BASE +0x52bfe*4+0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x52bff*4+0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x52c00*4+0x02000000,0x1f9e); +reg_write( DDR_REG_BASE +0x52c01*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52c02*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52c03*4+0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x52c04*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52c05*4+0x02000000,0x2114); +reg_write( DDR_REG_BASE +0x52c06*4+0x02000000,0x38e); +reg_write( DDR_REG_BASE +0x52c07*4+0x02000000,0x2605); +reg_write( DDR_REG_BASE +0x52c08*4+0x02000000,0x301e); +reg_write( DDR_REG_BASE +0x52c09*4+0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x52c0a*4+0x02000000,0x783); +reg_write( DDR_REG_BASE +0x52c0b*4+0x02000000,0x7b7b); +reg_write( DDR_REG_BASE +0x52c0c*4+0x02000000,0xbb91); +reg_write( DDR_REG_BASE +0x52c0d*4+0x02000000,0xbb9c); +reg_write( DDR_REG_BASE +0x52c0e*4+0x02000000,0xbb9f); +reg_write( DDR_REG_BASE +0x52c0f*4+0x02000000,0x9360); +reg_write( DDR_REG_BASE +0x52c10*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x52c11*4+0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x52c12*4+0x02000000,0xb660); +reg_write( DDR_REG_BASE +0x52c13*4+0x02000000,0x232f); +reg_write( DDR_REG_BASE +0x52c14*4+0x02000000,0x2c7); +reg_write( DDR_REG_BASE +0x52c15*4+0x02000000,0xbd7); +reg_write( DDR_REG_BASE +0x52c16*4+0x02000000,0x80a4); +reg_write( DDR_REG_BASE +0x52c17*4+0x02000000,0x7ef0); +reg_write( DDR_REG_BASE +0x52c18*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x52c19*4+0x02000000,0xcf7); +reg_write( DDR_REG_BASE +0x52c1a*4+0x02000000,0x9365); +reg_write( DDR_REG_BASE +0x52c1b*4+0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x52c1c*4+0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x52c1d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52c1e*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52c1f*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52c20*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52c21*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x52c22*4+0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x52c23*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52c24*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52c25*4+0x02000000,0x4728); +reg_write( DDR_REG_BASE +0x52c26*4+0x02000000,0x7afd); +reg_write( DDR_REG_BASE +0x52c27*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x52c28*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52c29*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52c2a*4+0x02000000,0xb2); +reg_write( DDR_REG_BASE +0x52c2b*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52c2c*4+0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x52c2d*4+0x02000000,0x100c); +reg_write( DDR_REG_BASE +0x52c2e*4+0x02000000,0x2245); +reg_write( DDR_REG_BASE +0x52c2f*4+0x02000000,0x602); +reg_write( DDR_REG_BASE +0x52c30*4+0x02000000,0x7204); +reg_write( DDR_REG_BASE +0x52c31*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x52c32*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x52c33*4+0x02000000,0xb440); +reg_write( DDR_REG_BASE +0x52c34*4+0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x52c35*4+0x02000000,0x1002); +reg_write( DDR_REG_BASE +0x52c36*4+0x02000000,0x92c0); +reg_write( DDR_REG_BASE +0x52c37*4+0x02000000,0x7204); +reg_write( DDR_REG_BASE +0x52c38*4+0x02000000,0xbfc1); +reg_write( DDR_REG_BASE +0x52c39*4+0x02000000,0x78a5); +reg_write( DDR_REG_BASE +0x52c3a*4+0x02000000,0x6f43); +reg_write( DDR_REG_BASE +0x52c3b*4+0x02000000,0x90a0); +reg_write( DDR_REG_BASE +0x52c3c*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52c3d*4+0x02000000,0x2244); +reg_write( DDR_REG_BASE +0x52c3e*4+0x02000000,0x7c3); +reg_write( DDR_REG_BASE +0x52c3f*4+0x02000000,0xeb06); +reg_write( DDR_REG_BASE +0x52c40*4+0x02000000,0xbb61); +reg_write( DDR_REG_BASE +0x52c41*4+0x02000000,0xb01); +reg_write( DDR_REG_BASE +0x52c42*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x52c43*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52c44*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x52c45*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x52c46*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x52c47*4+0x02000000,0x83); +reg_write( DDR_REG_BASE +0x52c48*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52c49*4+0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x52c4a*4+0x02000000,0x17cc); +reg_write( DDR_REG_BASE +0x52c4b*4+0x02000000,0xec06); +reg_write( DDR_REG_BASE +0x52c4c*4+0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x52c4d*4+0x02000000,0xc01); +reg_write( DDR_REG_BASE +0x52c4e*4+0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x52c4f*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52c50*4+0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x52c51*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52c52*4+0x02000000,0xcc); +reg_write( DDR_REG_BASE +0x52c53*4+0x02000000,0x6f66); +reg_write( DDR_REG_BASE +0x52c54*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52c55*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x52c56*4+0x02000000,0x7db); +reg_write( DDR_REG_BASE +0x52c57*4+0x02000000,0xb11); +reg_write( DDR_REG_BASE +0x52c58*4+0x02000000,0x3010); +reg_write( DDR_REG_BASE +0x52c59*4+0x02000000,0x2342); +reg_write( DDR_REG_BASE +0x52c5a*4+0x02000000,0x305b); +reg_write( DDR_REG_BASE +0x52c5b*4+0x02000000,0xbff); +reg_write( DDR_REG_BASE +0x52c5c*4+0x02000000,0xb031); +reg_write( DDR_REG_BASE +0x52c5d*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52c5e*4+0x02000000,0xbbc4); +reg_write( DDR_REG_BASE +0x52c5f*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x52c60*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x52c61*4+0x02000000,0x2405); +reg_write( DDR_REG_BASE +0x52c62*4+0x02000000,0x101e); +reg_write( DDR_REG_BASE +0x52c63*4+0x02000000,0x2740); +reg_write( DDR_REG_BASE +0x52c64*4+0x02000000,0x124c); +reg_write( DDR_REG_BASE +0x52c65*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52c66*4+0x02000000,0x2444); +reg_write( DDR_REG_BASE +0x52c67*4+0x02000000,0x17ce); +reg_write( DDR_REG_BASE +0x52c68*4+0x02000000,0xee05); +reg_write( DDR_REG_BASE +0x52c69*4+0x02000000,0xbe61); +reg_write( DDR_REG_BASE +0x52c6a*4+0x02000000,0xeff); +reg_write( DDR_REG_BASE +0x52c6b*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x52c6c*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52c6d*4+0x02000000,0xbfc4); +reg_write( DDR_REG_BASE +0x52c6e*4+0x02000000,0x2244); +reg_write( DDR_REG_BASE +0x52c6f*4+0x02000000,0x7ce); +reg_write( DDR_REG_BASE +0x52c70*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x52c71*4+0x02000000,0xee06); +reg_write( DDR_REG_BASE +0x52c72*4+0x02000000,0xbe61); +reg_write( DDR_REG_BASE +0x52c73*4+0x02000000,0xe01); +reg_write( DDR_REG_BASE +0x52c74*4+0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x52c75*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52c76*4+0x02000000,0xbcc4); +reg_write( DDR_REG_BASE +0x52c77*4+0x02000000,0x2244); +reg_write( DDR_REG_BASE +0x52c78*4+0x02000000,0x8e); +reg_write( DDR_REG_BASE +0x52c79*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x52c7a*4+0x02000000,0xef05); +reg_write( DDR_REG_BASE +0x52c7b*4+0x02000000,0xbf61); +reg_write( DDR_REG_BASE +0x52c7c*4+0x02000000,0xfff); +reg_write( DDR_REG_BASE +0x52c7d*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x52c7e*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52c7f*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x52c80*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x52c81*4+0x02000000,0xbac0); +reg_write( DDR_REG_BASE +0x52c82*4+0x02000000,0x7e45); +reg_write( DDR_REG_BASE +0x52c83*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x52c84*4+0x02000000,0xeb05); +reg_write( DDR_REG_BASE +0x52c85*4+0x02000000,0xbb61); +reg_write( DDR_REG_BASE +0x52c86*4+0x02000000,0xbff); +reg_write( DDR_REG_BASE +0x52c87*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x52c88*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52c89*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52c8a*4+0x02000000,0x780); +reg_write( DDR_REG_BASE +0x52c8b*4+0x02000000,0x2244); +reg_write( DDR_REG_BASE +0x52c8c*4+0x02000000,0x103); +reg_write( DDR_REG_BASE +0x52c8d*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x52c8e*4+0x02000000,0xec05); +reg_write( DDR_REG_BASE +0x52c8f*4+0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x52c90*4+0x02000000,0xcff); +reg_write( DDR_REG_BASE +0x52c91*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x52c92*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52c93*4+0x02000000,0x7bc5); +reg_write( DDR_REG_BASE +0x52c94*4+0x02000000,0x2244); +reg_write( DDR_REG_BASE +0x52c95*4+0x02000000,0x202); +reg_write( DDR_REG_BASE +0x52c96*4+0x02000000,0x7a65); +reg_write( DDR_REG_BASE +0x52c97*4+0x02000000,0x225f); +reg_write( DDR_REG_BASE +0x52c98*4+0x02000000,0x402); +reg_write( DDR_REG_BASE +0x52c99*4+0x02000000,0xdd2); +reg_write( DDR_REG_BASE +0x52c9a*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52c9b*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x52c9c*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52c9d*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52c9e*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52c9f*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52ca0*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52ca1*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52ca2*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52ca3*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x52ca4*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52ca5*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x52ca6*4+0x02000000,0x8d80); +reg_write( DDR_REG_BASE +0x52ca7*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x52ca8*4+0x02000000,0x4718); +reg_write( DDR_REG_BASE +0x52ca9*4+0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x52caa*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52cab*4+0x02000000,0xea0d); +reg_write( DDR_REG_BASE +0x52cac*4+0x02000000,0x245f); +reg_write( DDR_REG_BASE +0x52cad*4+0x02000000,0x1243); +reg_write( DDR_REG_BASE +0x52cae*4+0x02000000,0xa1b); +reg_write( DDR_REG_BASE +0x52caf*4+0x02000000,0xb1); +reg_write( DDR_REG_BASE +0x52cb0*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x52cb1*4+0x02000000,0xe308); +reg_write( DDR_REG_BASE +0x52cb2*4+0x02000000,0xd809); +reg_write( DDR_REG_BASE +0x52cb3*4+0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x52cb4*4+0x02000000,0x234a); +reg_write( DDR_REG_BASE +0x52cb5*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x52cb6*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x52cb7*4+0x02000000,0x7b9b); +reg_write( DDR_REG_BASE +0x52cb8*4+0x02000000,0x74ed); +reg_write( DDR_REG_BASE +0x52cb9*4+0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x52cba*4+0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x52cbb*4+0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x52cbc*4+0x02000000,0x1501); +reg_write( DDR_REG_BASE +0x52cbd*4+0x02000000,0x109e); +reg_write( DDR_REG_BASE +0x52cbe*4+0x02000000,0xf023); +reg_write( DDR_REG_BASE +0x52cbf*4+0x02000000,0x45c9); +reg_write( DDR_REG_BASE +0x52cc0*4+0x02000000,0x259a); +reg_write( DDR_REG_BASE +0x52cc1*4+0x02000000,0x1008); +reg_write( DDR_REG_BASE +0x52cc2*4+0x02000000,0x241a); +reg_write( DDR_REG_BASE +0x52cc3*4+0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x52cc4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52cc5*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52cc6*4+0x02000000,0x7aa5); +reg_write( DDR_REG_BASE +0x52cc7*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x52cc8*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x52cc9*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52cca*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x52ccb*4+0x02000000,0xb1f); +reg_write( DDR_REG_BASE +0x52ccc*4+0x02000000,0x3030); +reg_write( DDR_REG_BASE +0x52ccd*4+0x02000000,0x9a40); +reg_write( DDR_REG_BASE +0x52cce*4+0x02000000,0x258a); +reg_write( DDR_REG_BASE +0x52ccf*4+0x02000000,0x1fcf); +reg_write( DDR_REG_BASE +0x52cd0*4+0x02000000,0x7d44); +reg_write( DDR_REG_BASE +0x52cd1*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52cd2*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52cd3*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52cd4*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52cd5*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52cd6*4+0x02000000,0x2284); +reg_write( DDR_REG_BASE +0x52cd7*4+0x02000000,0x81f); +reg_write( DDR_REG_BASE +0x52cd8*4+0x02000000,0x62ba); +reg_write( DDR_REG_BASE +0x52cd9*4+0x02000000,0x2714); +reg_write( DDR_REG_BASE +0x52cda*4+0x02000000,0x30cd); +reg_write( DDR_REG_BASE +0x52cdb*4+0x02000000,0xb540); +reg_write( DDR_REG_BASE +0x52cdc*4+0x02000000,0x66fe); +reg_write( DDR_REG_BASE +0x52cdd*4+0x02000000,0x631b); +reg_write( DDR_REG_BASE +0x52cde*4+0x02000000,0x9c3); +reg_write( DDR_REG_BASE +0x52cdf*4+0x02000000,0x8385); +reg_write( DDR_REG_BASE +0x52ce0*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x52ce1*4+0x02000000,0xefd); +reg_write( DDR_REG_BASE +0x52ce2*4+0x02000000,0xb325); +reg_write( DDR_REG_BASE +0x52ce3*4+0x02000000,0x4669); +reg_write( DDR_REG_BASE +0x52ce4*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52ce5*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52ce6*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52ce7*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52ce8*4+0x02000000,0x8819); +reg_write( DDR_REG_BASE +0x52ce9*4+0x02000000,0xb863); +reg_write( DDR_REG_BASE +0x52cea*4+0x02000000,0x7314); +reg_write( DDR_REG_BASE +0x52ceb*4+0x02000000,0x20e0); +reg_write( DDR_REG_BASE +0x52cec*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x52ced*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52cee*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x52cef*4+0x02000000,0x1e4c); +reg_write( DDR_REG_BASE +0x52cf0*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x52cf1*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x52cf2*4+0x02000000,0xb041); +reg_write( DDR_REG_BASE +0x52cf3*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52cf4*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x52cf5*4+0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x52cf6*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x52cf7*4+0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x52cf8*4+0x02000000,0x70ef); +reg_write( DDR_REG_BASE +0x52cf9*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x52cfa*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x52cfb*4+0x02000000,0xc82); +reg_write( DDR_REG_BASE +0x52cfc*4+0x02000000,0x605c); +reg_write( DDR_REG_BASE +0x52cfd*4+0x02000000,0x275a); +reg_write( DDR_REG_BASE +0x52cfe*4+0x02000000,0x3642); +reg_write( DDR_REG_BASE +0x52cff*4+0x02000000,0x71e7); +reg_write( DDR_REG_BASE +0x52d00*4+0x02000000,0x629a); +reg_write( DDR_REG_BASE +0x52d01*4+0x02000000,0x623c); +reg_write( DDR_REG_BASE +0x52d02*4+0x02000000,0x2600); +reg_write( DDR_REG_BASE +0x52d03*4+0x02000000,0x3682); +reg_write( DDR_REG_BASE +0x52d04*4+0x02000000,0x123c); +reg_write( DDR_REG_BASE +0x52d05*4+0x02000000,0x82); +reg_write( DDR_REG_BASE +0x52d06*4+0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x52d07*4+0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x52d08*4+0x02000000,0xac40); +reg_write( DDR_REG_BASE +0x52d09*4+0x02000000,0xfe5); +reg_write( DDR_REG_BASE +0x52d0a*4+0x02000000,0xb094); +reg_write( DDR_REG_BASE +0x52d0b*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x52d0c*4+0x02000000,0xbd9); +reg_write( DDR_REG_BASE +0x52d0d*4+0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x52d0e*4+0x02000000,0x2314); +reg_write( DDR_REG_BASE +0x52d0f*4+0x02000000,0x10de); +reg_write( DDR_REG_BASE +0x52d10*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x52d11*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52d12*4+0x02000000,0x791b); +reg_write( DDR_REG_BASE +0x52d13*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52d14*4+0x02000000,0x2184); +reg_write( DDR_REG_BASE +0x52d15*4+0x02000000,0xa82); +reg_write( DDR_REG_BASE +0x52d16*4+0x02000000,0x2046); +reg_write( DDR_REG_BASE +0x52d17*4+0x02000000,0xa80); +reg_write( DDR_REG_BASE +0x52d18*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x52d19*4+0x02000000,0x215a); +reg_write( DDR_REG_BASE +0x52d1a*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x52d1b*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x52d1c*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x52d1d*4+0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x52d1e*4+0x02000000,0xcc1); +reg_write( DDR_REG_BASE +0x52d1f*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x52d20*4+0x02000000,0x303); +reg_write( DDR_REG_BASE +0x52d21*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x52d22*4+0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x52d23*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x52d24*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x52d25*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x52d26*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x52d27*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x52d28*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52d29*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x52d2a*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52d2b*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52d2c*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x52d2d*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x52d2e*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52d2f*4+0x02000000,0xe000); +reg_write( DDR_REG_BASE +0x52d30*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x52d31*4+0x02000000,0xe26); +reg_write( DDR_REG_BASE +0x52d32*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x52d33*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x52d34*4+0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x52d35*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x52d36*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x52d37*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x52d38*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52d39*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52d3a*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52d3b*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x52d3c*4+0x02000000,0x3b02); +reg_write( DDR_REG_BASE +0x52d3d*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52d3e*4+0x02000000,0x709b); +reg_write( DDR_REG_BASE +0x52d3f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52d40*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52d41*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x52d42*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52d43*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52d44*4+0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x52d45*4+0x02000000,0xf8a5); +reg_write( DDR_REG_BASE +0x52d46*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52d47*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52d48*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52d49*4+0x02000000,0xfbff); +reg_write( DDR_REG_BASE +0x52d4a*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x52d4b*4+0x02000000,0x9f7); +reg_write( DDR_REG_BASE +0x52d4c*4+0x02000000,0x8294); +reg_write( DDR_REG_BASE +0x52d4d*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52d4e*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x52d4f*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52d50*4+0x02000000,0xaa); +reg_write( DDR_REG_BASE +0x52d51*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52d52*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52d53*4+0x02000000,0x51f); +reg_write( DDR_REG_BASE +0x52d54*4+0x02000000,0xda78); +reg_write( DDR_REG_BASE +0x52d55*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52d56*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52d57*4+0x02000000,0x7085); +reg_write( DDR_REG_BASE +0x52d58*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52d59*4+0x02000000,0xe0aa); +reg_write( DDR_REG_BASE +0x52d5a*4+0x02000000,0xdce); +reg_write( DDR_REG_BASE +0x52d5b*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x52d5c*4+0x02000000,0xc08d); +reg_write( DDR_REG_BASE +0x52d5d*4+0x02000000,0xc08d); +reg_write( DDR_REG_BASE +0x52d5e*4+0x02000000,0xace); +reg_write( DDR_REG_BASE +0x52d5f*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x52d60*4+0x02000000,0xd978); +reg_write( DDR_REG_BASE +0x52d61*4+0x02000000,0xe76); +reg_write( DDR_REG_BASE +0x52d62*4+0x02000000,0xfd8f); +reg_write( DDR_REG_BASE +0x52d63*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52d64*4+0x02000000,0xb56); +reg_write( DDR_REG_BASE +0x52d65*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52d66*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52d67*4+0x02000000,0xef6); +reg_write( DDR_REG_BASE +0x52d68*4+0x02000000,0xff0f); +reg_write( DDR_REG_BASE +0x52d69*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52d6a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52d6b*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x52d6c*4+0x02000000,0xb12); +reg_write( DDR_REG_BASE +0x52d6d*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52d6e*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52d6f*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52d70*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52d71*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x52d72*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52d73*4+0x02000000,0xaa2); +reg_write( DDR_REG_BASE +0x52d74*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52d75*4+0x02000000,0xdaf7); +reg_write( DDR_REG_BASE +0x52d76*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x52d77*4+0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x52d78*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x52d79*4+0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x52d7a*4+0x02000000,0xe805); +reg_write( DDR_REG_BASE +0x52d7b*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x52d7c*4+0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x52d7d*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x52d7e*4+0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x52d7f*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x52d80*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52d81*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x52d82*4+0x02000000,0x225a); +reg_write( DDR_REG_BASE +0x52d83*4+0x02000000,0x102); +reg_write( DDR_REG_BASE +0x52d84*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x52d85*4+0x02000000,0x8d20); +reg_write( DDR_REG_BASE +0x52d86*4+0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x52d87*4+0x02000000,0xf7f); +reg_write( DDR_REG_BASE +0x52d88*4+0x02000000,0x220f); +reg_write( DDR_REG_BASE +0x52d89*4+0x02000000,0xe); +reg_write( DDR_REG_BASE +0x52d8a*4+0x02000000,0x265a); +reg_write( DDR_REG_BASE +0x52d8b*4+0x02000000,0x1100); +reg_write( DDR_REG_BASE +0x52d8c*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52d8d*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x52d8e*4+0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x52d8f*4+0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x52d90*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52d91*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52d92*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x52d93*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52d94*4+0x02000000,0x640); +reg_write( DDR_REG_BASE +0x52d95*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52d96*4+0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x52d97*4+0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x52d98*4+0x02000000,0xc103); +reg_write( DDR_REG_BASE +0x52d99*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x52d9a*4+0x02000000,0x2100); +reg_write( DDR_REG_BASE +0x52d9b*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52d9c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52d9d*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x52d9e*4+0x02000000,0xd02); +reg_write( DDR_REG_BASE +0x52d9f*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x52da0*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52da1*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52da2*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52da3*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x52da4*4+0x02000000,0xea2); +reg_write( DDR_REG_BASE +0x52da5*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x52da6*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52da7*4+0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x52da8*4+0x02000000,0x7ecf); +reg_write( DDR_REG_BASE +0x52da9*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52daa*4+0x02000000,0xc81); +reg_write( DDR_REG_BASE +0x52dab*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52dac*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x52dad*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52dae*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52daf*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52db0*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x52db1*4+0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x52db2*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x52db3*4+0x02000000,0x44); +reg_write( DDR_REG_BASE +0x52db4*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x52db5*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52db6*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52db7*4+0x02000000,0xe024); +reg_write( DDR_REG_BASE +0x52db8*4+0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x52db9*4+0x02000000,0xb0e6); +reg_write( DDR_REG_BASE +0x52dba*4+0x02000000,0x18fe); +reg_write( DDR_REG_BASE +0x52dbb*4+0x02000000,0x8044); +reg_write( DDR_REG_BASE +0x52dbc*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52dbd*4+0x02000000,0xba2); +reg_write( DDR_REG_BASE +0x52dbe*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x52dbf*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52dc0*4+0x02000000,0xd830); +reg_write( DDR_REG_BASE +0x52dc1*4+0x02000000,0xf16); +reg_write( DDR_REG_BASE +0x52dc2*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52dc3*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52dc4*4+0x02000000,0xd9e); +reg_write( DDR_REG_BASE +0x52dc5*4+0x02000000,0xfe0f); +reg_write( DDR_REG_BASE +0x52dc6*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x52dc7*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52dc8*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52dc9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52dca*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x52dcb*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52dcc*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x52dcd*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x52dce*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x52dcf*4+0x02000000,0xfc3); +reg_write( DDR_REG_BASE +0x52dd0*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52dd1*4+0x02000000,0x8fb); +reg_write( DDR_REG_BASE +0x52dd2*4+0x02000000,0x8534); +reg_write( DDR_REG_BASE +0x52dd3*4+0x02000000,0xc188); +reg_write( DDR_REG_BASE +0x52dd4*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52dd5*4+0x02000000,0xeee); +reg_write( DDR_REG_BASE +0x52dd6*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52dd7*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52dd8*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52dd9*4+0x02000000,0xa6e); +reg_write( DDR_REG_BASE +0x52dda*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52ddb*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52ddc*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52ddd*4+0x02000000,0xb62); +reg_write( DDR_REG_BASE +0x52dde*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x52ddf*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52de0*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x52de1*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x52de2*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x52de3*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52de4*4+0x02000000,0xe174); +reg_write( DDR_REG_BASE +0x52de5*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x52de6*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x52de7*4+0x02000000,0xb601); +reg_write( DDR_REG_BASE +0x52de8*4+0x02000000,0x1e59); +reg_write( DDR_REG_BASE +0x52de9*4+0x02000000,0x901d); +reg_write( DDR_REG_BASE +0x52dea*4+0x02000000,0xf7d); +reg_write( DDR_REG_BASE +0x52deb*4+0x02000000,0x1a35); +reg_write( DDR_REG_BASE +0x52dec*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52ded*4+0x02000000,0xebe); +reg_write( DDR_REG_BASE +0x52dee*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52def*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52df0*4+0x02000000,0x1503); +reg_write( DDR_REG_BASE +0x52df1*4+0x02000000,0x108b); +reg_write( DDR_REG_BASE +0x52df2*4+0x02000000,0x8d82); +reg_write( DDR_REG_BASE +0x52df3*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x52df4*4+0x02000000,0xf02a); +reg_write( DDR_REG_BASE +0x52df5*4+0x02000000,0x241a); +reg_write( DDR_REG_BASE +0x52df6*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x52df7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52df8*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52df9*4+0x02000000,0x206c); +reg_write( DDR_REG_BASE +0x52dfa*4+0x02000000,0x302); +reg_write( DDR_REG_BASE +0x52dfb*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x52dfc*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52dfd*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52dfe*4+0x02000000,0x166); +reg_write( DDR_REG_BASE +0x52dff*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x52e00*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x52e01*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x52e02*4+0x02000000,0xc088); +reg_write( DDR_REG_BASE +0x52e03*4+0x02000000,0x6098); +reg_write( DDR_REG_BASE +0x52e04*4+0x02000000,0x8820); +reg_write( DDR_REG_BASE +0x52e05*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x52e06*4+0x02000000,0x7965); +reg_write( DDR_REG_BASE +0x52e07*4+0x02000000,0xa820); +reg_write( DDR_REG_BASE +0x52e08*4+0x02000000,0x241a); +reg_write( DDR_REG_BASE +0x52e09*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x52e0a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52e0b*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x52e0c*4+0x02000000,0x2153); +reg_write( DDR_REG_BASE +0x52e0d*4+0x02000000,0x80be); +reg_write( DDR_REG_BASE +0x52e0e*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52e0f*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52e10*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52e11*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x52e12*4+0x02000000,0x7a05); +reg_write( DDR_REG_BASE +0x52e13*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x52e14*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x52e15*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52e16*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x52e17*4+0x02000000,0x9200); +reg_write( DDR_REG_BASE +0x52e18*4+0x02000000,0xf205); +reg_write( DDR_REG_BASE +0x52e19*4+0x02000000,0x2080); +reg_write( DDR_REG_BASE +0x52e1a*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52e1b*4+0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x52e1c*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x52e1d*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x52e1e*4+0x02000000,0xbaf); +reg_write( DDR_REG_BASE +0x52e1f*4+0x02000000,0x9325); +reg_write( DDR_REG_BASE +0x52e20*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52e21*4+0x02000000,0x9de); +reg_write( DDR_REG_BASE +0x52e22*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52e23*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52e24*4+0x02000000,0xb8d); +reg_write( DDR_REG_BASE +0x52e25*4+0x02000000,0xb031); +reg_write( DDR_REG_BASE +0x52e26*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x52e27*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x52e28*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52e29*4+0x02000000,0x6e); +reg_write( DDR_REG_BASE +0x52e2a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52e2b*4+0x02000000,0xcfe); +reg_write( DDR_REG_BASE +0x52e2c*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x52e2d*4+0x02000000,0x2378); +reg_write( DDR_REG_BASE +0x52e2e*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x52e2f*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52e30*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x52e31*4+0x02000000,0xcc6); +reg_write( DDR_REG_BASE +0x52e32*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52e33*4+0x02000000,0x1e02); +reg_write( DDR_REG_BASE +0x52e34*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x52e35*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52e36*4+0x02000000,0xa16); +reg_write( DDR_REG_BASE +0x52e37*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52e38*4+0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x52e39*4+0x02000000,0xd840); +reg_write( DDR_REG_BASE +0x52e3a*4+0x02000000,0xe22); +reg_write( DDR_REG_BASE +0x52e3b*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52e3c*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52e3d*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52e3e*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52e3f*4+0x02000000,0xcc6); +reg_write( DDR_REG_BASE +0x52e40*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x52e41*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52e42*4+0x02000000,0x8d43); +reg_write( DDR_REG_BASE +0x52e43*4+0x02000000,0x8d62); +reg_write( DDR_REG_BASE +0x52e44*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x52e45*4+0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x52e46*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x52e47*4+0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x52e48*4+0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x52e49*4+0x02000000,0xb8e3); +reg_write( DDR_REG_BASE +0x52e4a*4+0x02000000,0xd840); +reg_write( DDR_REG_BASE +0x52e4b*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x52e4c*4+0x02000000,0x822); +reg_write( DDR_REG_BASE +0x52e4d*4+0x02000000,0x7902); +reg_write( DDR_REG_BASE +0x52e4e*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52e4f*4+0x02000000,0x7874); +reg_write( DDR_REG_BASE +0x52e50*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x52e51*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x52e52*4+0x02000000,0xae7); +reg_write( DDR_REG_BASE +0x52e53*4+0x02000000,0x80c5); +reg_write( DDR_REG_BASE +0x52e54*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x52e55*4+0x02000000,0x9c2); +reg_write( DDR_REG_BASE +0x52e56*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52e57*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52e58*4+0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x52e59*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x52e5a*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x52e5b*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52e5c*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52e5d*4+0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x52e5e*4+0x02000000,0x92a); +reg_write( DDR_REG_BASE +0x52e5f*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x52e60*4+0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x52e61*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52e62*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52e63*4+0x02000000,0x7044); +reg_write( DDR_REG_BASE +0x52e64*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52e65*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x52e66*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52e67*4+0x02000000,0x7044); +reg_write( DDR_REG_BASE +0x52e68*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52e69*4+0x02000000,0xe076); +reg_write( DDR_REG_BASE +0x52e6a*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52e6b*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52e6c*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52e6d*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52e6e*4+0x02000000,0xe0aa); +reg_write( DDR_REG_BASE +0x52e6f*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x52e70*4+0x02000000,0xf80f); +reg_write( DDR_REG_BASE +0x52e71*4+0x02000000,0xb88a); +reg_write( DDR_REG_BASE +0x52e72*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x52e73*4+0x02000000,0x9fd); +reg_write( DDR_REG_BASE +0x52e74*4+0x02000000,0x8294); +reg_write( DDR_REG_BASE +0x52e75*4+0x02000000,0xd72); +reg_write( DDR_REG_BASE +0x52e76*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x52e77*4+0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x52e78*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52e79*4+0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x52e7a*4+0x02000000,0xf7f); +reg_write( DDR_REG_BASE +0x52e7b*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52e7c*4+0x02000000,0xc81); +reg_write( DDR_REG_BASE +0x52e7d*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52e7e*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x52e7f*4+0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x52e80*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x52e81*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52e82*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52e83*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52e84*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x52e85*4+0x02000000,0xb36); +reg_write( DDR_REG_BASE +0x52e86*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x52e87*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52e88*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x52e89*4+0x02000000,0x3b02); +reg_write( DDR_REG_BASE +0x52e8a*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52e8b*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52e8c*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52e8d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52e8e*4+0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x52e8f*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52e90*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52e91*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52e92*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x52e93*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52e94*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x52e95*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52e96*4+0x02000000,0x94); +reg_write( DDR_REG_BASE +0x52e97*4+0x02000000,0x9200); +reg_write( DDR_REG_BASE +0x52e98*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52e99*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52e9a*4+0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x52e9b*4+0x02000000,0x216c); +reg_write( DDR_REG_BASE +0x52e9c*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x52e9d*4+0x02000000,0xa821); +reg_write( DDR_REG_BASE +0x52e9e*4+0x02000000,0x8822); +reg_write( DDR_REG_BASE +0x52e9f*4+0x02000000,0xb9c6); +reg_write( DDR_REG_BASE +0x52ea0*4+0x02000000,0xa822); +reg_write( DDR_REG_BASE +0x52ea1*4+0x02000000,0x882d); +reg_write( DDR_REG_BASE +0x52ea2*4+0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x52ea3*4+0x02000000,0xc02); +reg_write( DDR_REG_BASE +0x52ea4*4+0x02000000,0x2285); +reg_write( DDR_REG_BASE +0x52ea5*4+0x02000000,0x23f); +reg_write( DDR_REG_BASE +0x52ea6*4+0x02000000,0x913); +reg_write( DDR_REG_BASE +0x52ea7*4+0x02000000,0x17f); +reg_write( DDR_REG_BASE +0x52ea8*4+0x02000000,0xa84d); +reg_write( DDR_REG_BASE +0x52ea9*4+0x02000000,0x794f); +reg_write( DDR_REG_BASE +0x52eaa*4+0x02000000,0xb985); +reg_write( DDR_REG_BASE +0x52eab*4+0x02000000,0xa82d); +reg_write( DDR_REG_BASE +0x52eac*4+0x02000000,0x8823); +reg_write( DDR_REG_BASE +0x52ead*4+0x02000000,0xb987); +reg_write( DDR_REG_BASE +0x52eae*4+0x02000000,0xa823); +reg_write( DDR_REG_BASE +0x52eaf*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52eb0*4+0x02000000,0xa838); +reg_write( DDR_REG_BASE +0x52eb1*4+0x02000000,0xa831); +reg_write( DDR_REG_BASE +0x52eb2*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x52eb3*4+0x02000000,0xa830); +reg_write( DDR_REG_BASE +0x52eb4*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x52eb5*4+0x02000000,0xb9a); +reg_write( DDR_REG_BASE +0x52eb6*4+0x02000000,0xfdcf); +reg_write( DDR_REG_BASE +0x52eb7*4+0x02000000,0x256f); +reg_write( DDR_REG_BASE +0x52eb8*4+0x02000000,0x1343); +reg_write( DDR_REG_BASE +0x52eb9*4+0x02000000,0x9560); +reg_write( DDR_REG_BASE +0x52eba*4+0x02000000,0xda20); +reg_write( DDR_REG_BASE +0x52ebb*4+0x02000000,0xd940); +reg_write( DDR_REG_BASE +0x52ebc*4+0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x52ebd*4+0x02000000,0x85ca); +reg_write( DDR_REG_BASE +0x52ebe*4+0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x52ebf*4+0x02000000,0xc2d); +reg_write( DDR_REG_BASE +0x52ec0*4+0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x52ec1*4+0x02000000,0x89d0); +reg_write( DDR_REG_BASE +0x52ec2*4+0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x52ec3*4+0x02000000,0x4d); +reg_write( DDR_REG_BASE +0x52ec4*4+0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x52ec5*4+0x02000000,0x8fd8); +reg_write( DDR_REG_BASE +0x52ec6*4+0x02000000,0xd950); +reg_write( DDR_REG_BASE +0x52ec7*4+0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x52ec8*4+0x02000000,0x4d); +reg_write( DDR_REG_BASE +0x52ec9*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x52eca*4+0x02000000,0x5ca); +reg_write( DDR_REG_BASE +0x52ecb*4+0x02000000,0x213c); +reg_write( DDR_REG_BASE +0x52ecc*4+0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x52ecd*4+0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x52ece*4+0x02000000,0x89d0); +reg_write( DDR_REG_BASE +0x52ecf*4+0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x52ed0*4+0x02000000,0xad); +reg_write( DDR_REG_BASE +0x52ed1*4+0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x52ed2*4+0x02000000,0x8fd8); +reg_write( DDR_REG_BASE +0x52ed3*4+0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x52ed4*4+0x02000000,0xed); +reg_write( DDR_REG_BASE +0x52ed5*4+0x02000000,0x73d3); +reg_write( DDR_REG_BASE +0x52ed6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52ed7*4+0x02000000,0x95f); +reg_write( DDR_REG_BASE +0x52ed8*4+0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x52ed9*4+0x02000000,0x12d); +reg_write( DDR_REG_BASE +0x52eda*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x52edb*4+0x02000000,0x8c); +reg_write( DDR_REG_BASE +0x52edc*4+0x02000000,0x15fe); +reg_write( DDR_REG_BASE +0x52edd*4+0x02000000,0x9081); +reg_write( DDR_REG_BASE +0x52ede*4+0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x52edf*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x52ee0*4+0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x52ee1*4+0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x52ee2*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52ee3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52ee4*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52ee5*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52ee6*4+0x02000000,0xf8); +reg_write( DDR_REG_BASE +0x52ee7*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52ee8*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52ee9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52eea*4+0x02000000,0x1ff0); +reg_write( DDR_REG_BASE +0x52eeb*4+0x02000000,0xb881); +reg_write( DDR_REG_BASE +0x52eec*4+0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x52eed*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x52eee*4+0x02000000,0x7224); +reg_write( DDR_REG_BASE +0x52eef*4+0x02000000,0x7965); +reg_write( DDR_REG_BASE +0x52ef0*4+0x02000000,0xb280); +reg_write( DDR_REG_BASE +0x52ef1*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x52ef2*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x52ef3*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52ef4*4+0x02000000,0xc0e4); +reg_write( DDR_REG_BASE +0x52ef5*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x52ef6*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x52ef7*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52ef8*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x52ef9*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x52efa*4+0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x52efb*4+0x02000000,0x225a); +reg_write( DDR_REG_BASE +0x52efc*4+0x02000000,0xc8c); +reg_write( DDR_REG_BASE +0x52efd*4+0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x52efe*4+0x02000000,0x609d); +reg_write( DDR_REG_BASE +0x52eff*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x52f00*4+0x02000000,0x64c); +reg_write( DDR_REG_BASE +0x52f01*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x52f02*4+0x02000000,0x64bc); +reg_write( DDR_REG_BASE +0x52f03*4+0x02000000,0x642c); +reg_write( DDR_REG_BASE +0x52f04*4+0x02000000,0x1e3c); +reg_write( DDR_REG_BASE +0x52f05*4+0x02000000,0x1302); +reg_write( DDR_REG_BASE +0x52f06*4+0x02000000,0xbeb); +reg_write( DDR_REG_BASE +0x52f07*4+0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x52f08*4+0x02000000,0x2300); +reg_write( DDR_REG_BASE +0x52f09*4+0x02000000,0x168e); +reg_write( DDR_REG_BASE +0x52f0a*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x52f0b*4+0x02000000,0xadf); +reg_write( DDR_REG_BASE +0x52f0c*4+0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x52f0d*4+0x02000000,0x2614); +reg_write( DDR_REG_BASE +0x52f0e*4+0x02000000,0x308b); +reg_write( DDR_REG_BASE +0x52f0f*4+0x02000000,0xc4c4); +reg_write( DDR_REG_BASE +0x52f10*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52f11*4+0x02000000,0x1209); +reg_write( DDR_REG_BASE +0x52f12*4+0x02000000,0x308d); +reg_write( DDR_REG_BASE +0x52f13*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x52f14*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x52f15*4+0x02000000,0x1a09); +reg_write( DDR_REG_BASE +0x52f16*4+0x02000000,0x3382); +reg_write( DDR_REG_BASE +0x52f17*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x52f18*4+0x02000000,0x26f0); +reg_write( DDR_REG_BASE +0x52f19*4+0x02000000,0x73c0); +reg_write( DDR_REG_BASE +0x52f1a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52f1b*4+0x02000000,0x8e8); +reg_write( DDR_REG_BASE +0x52f1c*4+0x02000000,0xb62); +reg_write( DDR_REG_BASE +0x52f1d*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x52f1e*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x52f1f*4+0x02000000,0xcc22); +reg_write( DDR_REG_BASE +0x52f20*4+0x02000000,0xff1); +reg_write( DDR_REG_BASE +0x52f21*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52f22*4+0x02000000,0x1a09); +reg_write( DDR_REG_BASE +0x52f23*4+0x02000000,0x3342); +reg_write( DDR_REG_BASE +0x52f24*4+0x02000000,0x1a22); +reg_write( DDR_REG_BASE +0x52f25*4+0x02000000,0x339c); +reg_write( DDR_REG_BASE +0x52f26*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52f27*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52f28*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x52f29*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52f2a*4+0x02000000,0x1ea); +reg_write( DDR_REG_BASE +0x52f2b*4+0x02000000,0x9340); +reg_write( DDR_REG_BASE +0x52f2c*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52f2d*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52f2e*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52f2f*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52f30*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52f31*4+0x02000000,0xfe00); +reg_write( DDR_REG_BASE +0x52f32*4+0x02000000,0x2204); +reg_write( DDR_REG_BASE +0x52f33*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x52f34*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52f35*4+0x02000000,0xc0ff); +reg_write( DDR_REG_BASE +0x52f36*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x52f37*4+0x02000000,0x9341); +reg_write( DDR_REG_BASE +0x52f38*4+0x02000000,0xb300); +reg_write( DDR_REG_BASE +0x52f39*4+0x02000000,0xb962); +reg_write( DDR_REG_BASE +0x52f3a*4+0x02000000,0x226c); +reg_write( DDR_REG_BASE +0x52f3b*4+0x02000000,0x140); +reg_write( DDR_REG_BASE +0x52f3c*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52f3d*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x52f3e*4+0x02000000,0xb301); +reg_write( DDR_REG_BASE +0x52f3f*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52f40*4+0x02000000,0x7a1b); +reg_write( DDR_REG_BASE +0x52f41*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x52f42*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x52f43*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52f44*4+0x02000000,0xe164); +reg_write( DDR_REG_BASE +0x52f45*4+0x02000000,0x1a00); +reg_write( DDR_REG_BASE +0x52f46*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x52f47*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x52f48*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52f49*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x52f4a*4+0x02000000,0x8a61); +reg_write( DDR_REG_BASE +0x52f4b*4+0x02000000,0x8a80); +reg_write( DDR_REG_BASE +0x52f4c*4+0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x52f4d*4+0x02000000,0x241a); +reg_write( DDR_REG_BASE +0x52f4e*4+0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x52f4f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52f50*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52f51*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x52f52*4+0x02000000,0x7a05); +reg_write( DDR_REG_BASE +0x52f53*4+0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x52f54*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x52f55*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x52f56*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52f57*4+0x02000000,0x164); +reg_write( DDR_REG_BASE +0x52f58*4+0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x52f59*4+0x02000000,0xbeb); +reg_write( DDR_REG_BASE +0x52f5a*4+0x02000000,0x8305); +reg_write( DDR_REG_BASE +0x52f5b*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52f5c*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x52f5d*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52f5e*4+0x02000000,0x710d); +reg_write( DDR_REG_BASE +0x52f5f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52f60*4+0x02000000,0x6); +reg_write( DDR_REG_BASE +0x52f61*4+0x02000000,0xe56d); +reg_write( DDR_REG_BASE +0x52f62*4+0x02000000,0x2d85); +reg_write( DDR_REG_BASE +0x52f63*4+0x02000000,0x1b81); +reg_write( DDR_REG_BASE +0x52f64*4+0x02000000,0x2553); +reg_write( DDR_REG_BASE +0x52f65*4+0x02000000,0x9041); +reg_write( DDR_REG_BASE +0x52f66*4+0x02000000,0xf205); +reg_write( DDR_REG_BASE +0x52f67*4+0x02000000,0x78af); +reg_write( DDR_REG_BASE +0x52f68*4+0x02000000,0x214e); +reg_write( DDR_REG_BASE +0x52f69*4+0x02000000,0x10d); +reg_write( DDR_REG_BASE +0x52f6a*4+0x02000000,0x651d); +reg_write( DDR_REG_BASE +0x52f6b*4+0x02000000,0x7aaf); +reg_write( DDR_REG_BASE +0x52f6c*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52f6d*4+0x02000000,0xaf); +reg_write( DDR_REG_BASE +0x52f6e*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52f6f*4+0x02000000,0xfe2); +reg_write( DDR_REG_BASE +0x52f70*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52f71*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x52f72*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52f73*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52f74*4+0x02000000,0x7c8); +reg_write( DDR_REG_BASE +0x52f75*4+0x02000000,0xa8a0); +reg_write( DDR_REG_BASE +0x52f76*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x52f77*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52f78*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52f79*4+0x02000000,0x266f); +reg_write( DDR_REG_BASE +0x52f7a*4+0x02000000,0x15c3); +reg_write( DDR_REG_BASE +0x52f7b*4+0x02000000,0x8e40); +reg_write( DDR_REG_BASE +0x52f7c*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x52f7d*4+0x02000000,0xea17); +reg_write( DDR_REG_BASE +0x52f7e*4+0x02000000,0xc1a); +reg_write( DDR_REG_BASE +0x52f7f*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52f80*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x52f81*4+0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x52f82*4+0x02000000,0xe887); +reg_write( DDR_REG_BASE +0x52f83*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52f84*4+0x02000000,0xd6); +reg_write( DDR_REG_BASE +0x52f85*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52f86*4+0x02000000,0xa46); +reg_write( DDR_REG_BASE +0x52f87*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x52f88*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52f89*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x52f8a*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52f8b*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52f8c*4+0x02000000,0x7f05); +reg_write( DDR_REG_BASE +0x52f8d*4+0x02000000,0x78bb); +reg_write( DDR_REG_BASE +0x52f8e*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52f8f*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52f90*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52f91*4+0x02000000,0xfe92); +reg_write( DDR_REG_BASE +0x52f92*4+0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x52f93*4+0x02000000,0x16ff); +reg_write( DDR_REG_BASE +0x52f94*4+0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x52f95*4+0x02000000,0xea18); +reg_write( DDR_REG_BASE +0x52f96*4+0x02000000,0xbea); +reg_write( DDR_REG_BASE +0x52f97*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52f98*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x52f99*4+0x02000000,0x228c); +reg_write( DDR_REG_BASE +0x52f9a*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x52f9b*4+0x02000000,0xf209); +reg_write( DDR_REG_BASE +0x52f9c*4+0x02000000,0xe888); +reg_write( DDR_REG_BASE +0x52f9d*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52f9e*4+0x02000000,0xd7); +reg_write( DDR_REG_BASE +0x52f9f*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52fa0*4+0x02000000,0xa12); +reg_write( DDR_REG_BASE +0x52fa1*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x52fa2*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52fa3*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52fa4*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52fa5*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52fa6*4+0x02000000,0x79bb); +reg_write( DDR_REG_BASE +0x52fa7*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x52fa8*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52fa9*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52faa*4+0x02000000,0xfe9a); +reg_write( DDR_REG_BASE +0x52fab*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x52fac*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52fad*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52fae*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x52faf*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52fb0*4+0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x52fb1*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52fb2*4+0x02000000,0x9); +reg_write( DDR_REG_BASE +0x52fb3*4+0x02000000,0xea1a); +reg_write( DDR_REG_BASE +0x52fb4*4+0x02000000,0xa23); +reg_write( DDR_REG_BASE +0x52fb5*4+0x02000000,0xa30); +reg_write( DDR_REG_BASE +0x52fb6*4+0x02000000,0x720c); +reg_write( DDR_REG_BASE +0x52fb7*4+0x02000000,0x228c); +reg_write( DDR_REG_BASE +0x52fb8*4+0x02000000,0x8c03); +reg_write( DDR_REG_BASE +0x52fb9*4+0x02000000,0xf20c); +reg_write( DDR_REG_BASE +0x52fba*4+0x02000000,0xe2f8); +reg_write( DDR_REG_BASE +0x52fbb*4+0x02000000,0xf404); +reg_write( DDR_REG_BASE +0x52fbc*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52fbd*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x52fbe*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52fbf*4+0x02000000,0xd8); +reg_write( DDR_REG_BASE +0x52fc0*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52fc1*4+0x02000000,0x9d2); +reg_write( DDR_REG_BASE +0x52fc2*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x52fc3*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52fc4*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52fc5*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52fc6*4+0x02000000,0x401); +reg_write( DDR_REG_BASE +0x52fc7*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52fc8*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52fc9*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52fca*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52fcb*4+0x02000000,0xe0a0); +reg_write( DDR_REG_BASE +0x52fcc*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x52fcd*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52fce*4+0x02000000,0xc0e6); +reg_write( DDR_REG_BASE +0x52fcf*4+0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x52fd0*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x52fd1*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52fd2*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52fd3*4+0x02000000,0xff64); +reg_write( DDR_REG_BASE +0x52fd4*4+0x02000000,0xb1e0); +reg_write( DDR_REG_BASE +0x52fd5*4+0x02000000,0x1904); +reg_write( DDR_REG_BASE +0x52fd6*4+0x02000000,0x45); +reg_write( DDR_REG_BASE +0x52fd7*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x52fd8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52fd9*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x52fda*4+0x02000000,0x8a21); +reg_write( DDR_REG_BASE +0x52fdb*4+0x02000000,0x8ac0); +reg_write( DDR_REG_BASE +0x52fdc*4+0x02000000,0xf039); +reg_write( DDR_REG_BASE +0x52fdd*4+0x02000000,0x228c); +reg_write( DDR_REG_BASE +0x52fde*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x52fdf*4+0x02000000,0xf418); +reg_write( DDR_REG_BASE +0x52fe0*4+0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x52fe1*4+0x02000000,0x1f83); +reg_write( DDR_REG_BASE +0x52fe2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52fe3*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52fe4*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x52fe5*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52fe6*4+0x02000000,0x1f64); +reg_write( DDR_REG_BASE +0x52fe7*4+0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x52fe8*4+0x02000000,0x8c); +reg_write( DDR_REG_BASE +0x52fe9*4+0x02000000,0x7444); +reg_write( DDR_REG_BASE +0x52fea*4+0x02000000,0x7a65); +reg_write( DDR_REG_BASE +0x52feb*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x52fec*4+0x02000000,0xb51); +reg_write( DDR_REG_BASE +0x52fed*4+0x02000000,0x123f); +reg_write( DDR_REG_BASE +0x52fee*4+0x02000000,0xb2e0); +reg_write( DDR_REG_BASE +0x52fef*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x52ff0*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52ff1*4+0x02000000,0xf164); +reg_write( DDR_REG_BASE +0x52ff2*4+0x02000000,0xb2e0); +reg_write( DDR_REG_BASE +0x52ff3*4+0x02000000,0x1a04); +reg_write( DDR_REG_BASE +0x52ff4*4+0x02000000,0x45); +reg_write( DDR_REG_BASE +0x52ff5*4+0x02000000,0xf020); +reg_write( DDR_REG_BASE +0x52ff6*4+0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x52ff7*4+0x02000000,0x32c0); +reg_write( DDR_REG_BASE +0x52ff8*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x52ff9*4+0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x52ffa*4+0x02000000,0xf753); +reg_write( DDR_REG_BASE +0x52ffb*4+0x02000000,0x4381); +reg_write( DDR_REG_BASE +0x52ffc*4+0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x52ffd*4+0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x52ffe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52fff*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x53000*4+0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x53001*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x53002*4+0x02000000,0x7b45); +reg_write( DDR_REG_BASE +0x53003*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x53004*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x53005*4+0x02000000,0x164); +reg_write( DDR_REG_BASE +0x53006*4+0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x53007*4+0x02000000,0x8d); +reg_write( DDR_REG_BASE +0x53008*4+0x02000000,0x7444); +reg_write( DDR_REG_BASE +0x53009*4+0x02000000,0x7b45); +reg_write( DDR_REG_BASE +0x5300a*4+0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x5300b*4+0x02000000,0x1b00); +reg_write( DDR_REG_BASE +0x5300c*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x5300d*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x5300e*4+0x02000000,0xe0d); +reg_write( DDR_REG_BASE +0x5300f*4+0x02000000,0x3010); +reg_write( DDR_REG_BASE +0x53010*4+0x02000000,0xcd5); +reg_write( DDR_REG_BASE +0x53011*4+0x02000000,0x9274); +reg_write( DDR_REG_BASE +0x53012*4+0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x53013*4+0x02000000,0xb782); +reg_write( DDR_REG_BASE +0x53014*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x53015*4+0x02000000,0x993); +reg_write( DDR_REG_BASE +0x53016*4+0x02000000,0x83a5); +reg_write( DDR_REG_BASE +0x53017*4+0x02000000,0x222f); +reg_write( DDR_REG_BASE +0x53018*4+0x02000000,0x2c7); +reg_write( DDR_REG_BASE +0x53019*4+0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x5301a*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5301b*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5301c*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5301d*4+0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x5301e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5301f*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x53020*4+0x02000000,0x30); +reg_write( DDR_REG_BASE +0x53021*4+0x02000000,0x10b4); +reg_write( DDR_REG_BASE +0x53022*4+0x02000000,0x501); +reg_write( DDR_REG_BASE +0x53023*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53024*4+0x02000000,0x708f); +reg_write( DDR_REG_BASE +0x53025*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53026*4+0x02000000,0x25); +reg_write( DDR_REG_BASE +0x53027*4+0x02000000,0x90d); +reg_write( DDR_REG_BASE +0x53028*4+0x02000000,0x171); +reg_write( DDR_REG_BASE +0x53029*4+0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x5302a*4+0x02000000,0xb0e1); +reg_write( DDR_REG_BASE +0x5302b*4+0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x5302c*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5302d*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x5302e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5302f*4+0x02000000,0x58); +reg_write( DDR_REG_BASE +0x53030*4+0x02000000,0xb021); +reg_write( DDR_REG_BASE +0x53031*4+0x02000000,0xf6f); +reg_write( DDR_REG_BASE +0x53032*4+0x02000000,0x1030); +reg_write( DDR_REG_BASE +0x53033*4+0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x53034*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53035*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53036*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53037*4+0x02000000,0x32); +reg_write( DDR_REG_BASE +0x53038*4+0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x53039*4+0x02000000,0x108d); +reg_write( DDR_REG_BASE +0x5303a*4+0x02000000,0xb8e3); +reg_write( DDR_REG_BASE +0x5303b*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5303c*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5303d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5303e*4+0x02000000,0x7cf); +reg_write( DDR_REG_BASE +0x5303f*4+0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x53040*4+0x02000000,0x30a1); +reg_write( DDR_REG_BASE +0x53041*4+0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x53042*4+0x02000000,0x104e); +reg_write( DDR_REG_BASE +0x53043*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x53044*4+0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x53045*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x53046*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53047*4+0x02000000,0x2753); +reg_write( DDR_REG_BASE +0x53048*4+0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x53049*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x5304a*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x5304b*4+0x02000000,0xf848); +reg_write( DDR_REG_BASE +0x5304c*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x5304d*4+0x02000000,0xf841); +reg_write( DDR_REG_BASE +0x5304e*4+0x02000000,0xee07); +reg_write( DDR_REG_BASE +0x5304f*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x53050*4+0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x53051*4+0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x53052*4+0x02000000,0xfaa); +reg_write( DDR_REG_BASE +0x53053*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x53054*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53055*4+0x02000000,0xed08); +reg_write( DDR_REG_BASE +0x53056*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x53057*4+0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x53058*4+0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x53059*4+0x02000000,0xf9e); +reg_write( DDR_REG_BASE +0x5305a*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x5305b*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5305c*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x5305d*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5305e*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5305f*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53060*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53061*4+0x02000000,0x7cf); +reg_write( DDR_REG_BASE +0x53062*4+0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x53063*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x53064*4+0x02000000,0x9c3); +reg_write( DDR_REG_BASE +0x53065*4+0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x53066*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53067*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53068*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x53069*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5306a*4+0x02000000,0x58); +reg_write( DDR_REG_BASE +0x5306b*4+0x02000000,0xd6f); +reg_write( DDR_REG_BASE +0x5306c*4+0x02000000,0x1030); +reg_write( DDR_REG_BASE +0x5306d*4+0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x5306e*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5306f*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53070*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53071*4+0x02000000,0x65); +reg_write( DDR_REG_BASE +0x53072*4+0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x53073*4+0x02000000,0x108e); +reg_write( DDR_REG_BASE +0x53074*4+0x02000000,0xb8e3); +reg_write( DDR_REG_BASE +0x53075*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53076*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53077*4+0x02000000,0x7cf); +reg_write( DDR_REG_BASE +0x53078*4+0x02000000,0x8802); +reg_write( DDR_REG_BASE +0x53079*4+0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x5307a*4+0x02000000,0x30a1); +reg_write( DDR_REG_BASE +0x5307b*4+0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x5307c*4+0x02000000,0x104f); +reg_write( DDR_REG_BASE +0x5307d*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5307e*4+0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x5307f*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x53080*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53081*4+0x02000000,0x2553); +reg_write( DDR_REG_BASE +0x53082*4+0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x53083*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x53084*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53085*4+0x02000000,0xf82b); +reg_write( DDR_REG_BASE +0x53086*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x53087*4+0x02000000,0xf824); +reg_write( DDR_REG_BASE +0x53088*4+0x02000000,0xef07); +reg_write( DDR_REG_BASE +0x53089*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x5308a*4+0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x5308b*4+0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x5308c*4+0x02000000,0xf36); +reg_write( DDR_REG_BASE +0x5308d*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x5308e*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5308f*4+0x02000000,0xee08); +reg_write( DDR_REG_BASE +0x53090*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x53091*4+0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x53092*4+0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x53093*4+0x02000000,0xf2a); +reg_write( DDR_REG_BASE +0x53094*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x53095*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x53096*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x53097*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x53098*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x53099*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5309a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5309b*4+0x02000000,0x7cf); +reg_write( DDR_REG_BASE +0x5309c*4+0x02000000,0x8823); +reg_write( DDR_REG_BASE +0x5309d*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x5309e*4+0x02000000,0x9c3); +reg_write( DDR_REG_BASE +0x5309f*4+0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x530a0*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x530a1*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x530a2*4+0x02000000,0x708e); +reg_write( DDR_REG_BASE +0x530a3*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x530a4*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x530a5*4+0x02000000,0xfaa); +reg_write( DDR_REG_BASE +0x530a6*4+0x02000000,0xfdcf); +reg_write( DDR_REG_BASE +0x530a7*4+0x02000000,0xfb2); +reg_write( DDR_REG_BASE +0x530a8*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x530a9*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x530aa*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x530ab*4+0x02000000,0xcfe); +reg_write( DDR_REG_BASE +0x530ac*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x530ad*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x530ae*4+0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x530af*4+0x02000000,0x1f8c); +reg_write( DDR_REG_BASE +0x530b0*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x530b1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530b2*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x530b3*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x530b4*4+0x02000000,0x1ea); +reg_write( DDR_REG_BASE +0x530b5*4+0x02000000,0x9300); +reg_write( DDR_REG_BASE +0x530b6*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x530b7*4+0x02000000,0x9012); +reg_write( DDR_REG_BASE +0x530b8*4+0x02000000,0x402); +reg_write( DDR_REG_BASE +0x530b9*4+0x02000000,0x2405); +reg_write( DDR_REG_BASE +0x530ba*4+0x02000000,0x1342); +reg_write( DDR_REG_BASE +0x530bb*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x530bc*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x530bd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530be*4+0x02000000,0x3f00); +reg_write( DDR_REG_BASE +0x530bf*4+0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x530c0*4+0x02000000,0x6d44); +reg_write( DDR_REG_BASE +0x530c1*4+0x02000000,0x7a85); +reg_write( DDR_REG_BASE +0x530c2*4+0x02000000,0x2196); +reg_write( DDR_REG_BASE +0x530c3*4+0x02000000,0x6); +reg_write( DDR_REG_BASE +0x530c4*4+0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x530c5*4+0x02000000,0x9321); +reg_write( DDR_REG_BASE +0x530c6*4+0x02000000,0x6d02); +reg_write( DDR_REG_BASE +0x530c7*4+0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x530c8*4+0x02000000,0xb9c5); +reg_write( DDR_REG_BASE +0x530c9*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x530ca*4+0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x530cb*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x530cc*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x530cd*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x530ce*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x530cf*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x530d0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530d1*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x530d2*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x530d3*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x530d4*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x530d5*4+0x02000000,0x154); +reg_write( DDR_REG_BASE +0x530d6*4+0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x530d7*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x530d8*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x530d9*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x530da*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x530db*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x530dc*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x530dd*4+0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x530de*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x530df*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x530e0*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x530e1*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x530e2*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x530e3*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x530e4*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x530e5*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x530e6*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x530e7*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x530e8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x530e9*4+0x02000000,0x6e1); +reg_write( DDR_REG_BASE +0x530ea*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x530eb*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x530ec*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x530ed*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x530ee*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x530ef*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x530f0*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x530f1*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x530f2*4+0x02000000,0x8f2); +reg_write( DDR_REG_BASE +0x530f3*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x530f4*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x530f5*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x530f6*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x530f7*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x530f8*4+0x02000000,0x6e1); +reg_write( DDR_REG_BASE +0x530f9*4+0x02000000,0xd910); +reg_write( DDR_REG_BASE +0x530fa*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x530fb*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x530fc*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x530fd*4+0x02000000,0xdb0c); +reg_write( DDR_REG_BASE +0x530fe*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x530ff*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53100*4+0x02000000,0x8d6); +reg_write( DDR_REG_BASE +0x53101*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53102*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53103*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53104*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x53105*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53106*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x53107*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x53108*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x53109*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5310a*4+0x02000000,0x8c2); +reg_write( DDR_REG_BASE +0x5310b*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x5310c*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5310d*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x5310e*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x5310f*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x53110*4+0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x53111*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x53112*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x53113*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53114*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53115*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53116*4+0x02000000,0x736c); +reg_write( DDR_REG_BASE +0x53117*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x53118*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x53119*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5311a*4+0x02000000,0x8a2); +reg_write( DDR_REG_BASE +0x5311b*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x5311c*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5311d*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x5311e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5311f*4+0x02000000,0x6e1); +reg_write( DDR_REG_BASE +0x53120*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x53121*4+0x02000000,0x825); +reg_write( DDR_REG_BASE +0x53122*4+0x02000000,0xb4); +reg_write( DDR_REG_BASE +0x53123*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53124*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x53125*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x53126*4+0x02000000,0xb862); +reg_write( DDR_REG_BASE +0x53127*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x53128*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x53129*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5312a*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5312b*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5312c*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5312d*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5312e*4+0x02000000,0x87a); +reg_write( DDR_REG_BASE +0x5312f*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53130*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53131*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x53132*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x53133*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53134*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53135*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53136*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x53137*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x53138*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53139*4+0x02000000,0x866); +reg_write( DDR_REG_BASE +0x5313a*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x5313b*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5313c*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x5313d*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x5313e*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5313f*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x53140*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53141*4+0x02000000,0xdb0c); +reg_write( DDR_REG_BASE +0x53142*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x53143*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53144*4+0x02000000,0x84e); +reg_write( DDR_REG_BASE +0x53145*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53146*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53147*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x53148*4+0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x53149*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5314a*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x5314b*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5314c*4+0x02000000,0x110); +reg_write( DDR_REG_BASE +0x5314d*4+0x02000000,0x9200); +reg_write( DDR_REG_BASE +0x5314e*4+0x02000000,0x204f); +reg_write( DDR_REG_BASE +0x5314f*4+0x02000000,0x101); +reg_write( DDR_REG_BASE +0x53150*4+0x02000000,0xb8a4); +reg_write( DDR_REG_BASE +0x53151*4+0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x53152*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x53153*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x53154*4+0x02000000,0xc0e6); +reg_write( DDR_REG_BASE +0x53155*4+0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x53156*4+0x02000000,0x483); +reg_write( DDR_REG_BASE +0x53157*4+0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x53158*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53159*4+0x02000000,0x6e2); +reg_write( DDR_REG_BASE +0x5315a*4+0x02000000,0x638d); +reg_write( DDR_REG_BASE +0x5315b*4+0x02000000,0x6479); +reg_write( DDR_REG_BASE +0x5315c*4+0x02000000,0x89c1); +reg_write( DDR_REG_BASE +0x5315d*4+0x02000000,0x7d04); +reg_write( DDR_REG_BASE +0x5315e*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5315f*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x53160*4+0x02000000,0x629a); +reg_write( DDR_REG_BASE +0x53161*4+0x02000000,0x8ae3); +reg_write( DDR_REG_BASE +0x53162*4+0x02000000,0x809); +reg_write( DDR_REG_BASE +0x53163*4+0x02000000,0x3ce); +reg_write( DDR_REG_BASE +0x53164*4+0x02000000,0x8a42); +reg_write( DDR_REG_BASE +0x53165*4+0x02000000,0x7d45); +reg_write( DDR_REG_BASE +0x53166*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x53167*4+0x02000000,0x9f5); +reg_write( DDR_REG_BASE +0x53168*4+0x02000000,0x83a4); +reg_write( DDR_REG_BASE +0x53169*4+0x02000000,0x2314); +reg_write( DDR_REG_BASE +0x5316a*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x5316b*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x5316c*4+0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x5316d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5316e*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5316f*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53170*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53171*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x53172*4+0x02000000,0x3d09); +reg_write( DDR_REG_BASE +0x53173*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53174*4+0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x53175*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x53176*4+0x02000000,0x8820); +reg_write( DDR_REG_BASE +0x53177*4+0x02000000,0x1054); +reg_write( DDR_REG_BASE +0x53178*4+0x02000000,0x83); +reg_write( DDR_REG_BASE +0x53179*4+0x02000000,0x1021); +reg_write( DDR_REG_BASE +0x5317a*4+0x02000000,0x8d); +reg_write( DDR_REG_BASE +0x5317b*4+0x02000000,0x10fd); +reg_write( DDR_REG_BASE +0x5317c*4+0x02000000,0x808e); +reg_write( DDR_REG_BASE +0x5317d*4+0x02000000,0x1209); +reg_write( DDR_REG_BASE +0x5317e*4+0x02000000,0x308b); +reg_write( DDR_REG_BASE +0x5317f*4+0x02000000,0x1208); +reg_write( DDR_REG_BASE +0x53180*4+0x02000000,0x308f); +reg_write( DDR_REG_BASE +0x53181*4+0x02000000,0xc149); +reg_write( DDR_REG_BASE +0x53182*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x53183*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x53184*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53185*4+0x02000000,0x10c); +reg_write( DDR_REG_BASE +0x53186*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53187*4+0x02000000,0x8ce); +reg_write( DDR_REG_BASE +0x53188*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x53189*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x5318a*4+0x02000000,0xc096); +reg_write( DDR_REG_BASE +0x5318b*4+0x02000000,0x8c6); +reg_write( DDR_REG_BASE +0x5318c*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5318d*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x5318e*4+0x02000000,0xbee2); +reg_write( DDR_REG_BASE +0x5318f*4+0x02000000,0x6f01); +reg_write( DDR_REG_BASE +0x53190*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x53191*4+0x02000000,0x20df); +reg_write( DDR_REG_BASE +0x53192*4+0x02000000,0x3e1); +reg_write( DDR_REG_BASE +0x53193*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x53194*4+0x02000000,0x7ba5); +reg_write( DDR_REG_BASE +0x53195*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x53196*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53197*4+0x02000000,0x43d9); +reg_write( DDR_REG_BASE +0x53198*4+0x02000000,0xc34d); +reg_write( DDR_REG_BASE +0x53199*4+0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x5319a*4+0x02000000,0x141); +reg_write( DDR_REG_BASE +0x5319b*4+0x02000000,0xb882); +reg_write( DDR_REG_BASE +0x5319c*4+0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x5319d*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5319e*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x5319f*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x531a0*4+0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x531a1*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x531a2*4+0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x531a3*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x531a4*4+0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x531a5*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x531a6*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x531a7*4+0x02000000,0x180); +reg_write( DDR_REG_BASE +0x531a8*4+0x02000000,0xc04e); +reg_write( DDR_REG_BASE +0x531a9*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x531aa*4+0x02000000,0xb869); +reg_write( DDR_REG_BASE +0x531ab*4+0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x531ac*4+0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x531ad*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x531ae*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x531af*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x531b0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531b1*4+0x02000000,0xc04f); +reg_write( DDR_REG_BASE +0x531b2*4+0x02000000,0x2378); +reg_write( DDR_REG_BASE +0x531b3*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x531b4*4+0x02000000,0x28d); +reg_write( DDR_REG_BASE +0x531b5*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x531b6*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x531b7*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x531b8*4+0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x531b9*4+0x02000000,0x17c0); +reg_write( DDR_REG_BASE +0x531ba*4+0x02000000,0xc10a); +reg_write( DDR_REG_BASE +0x531bb*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x531bc*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x531bd*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x531be*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x531bf*4+0x02000000,0x7b7b); +reg_write( DDR_REG_BASE +0x531c0*4+0x02000000,0xaea); +reg_write( DDR_REG_BASE +0x531c1*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x531c2*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x531c3*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x531c4*4+0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x531c5*4+0x02000000,0x7b0b); +reg_write( DDR_REG_BASE +0x531c6*4+0x02000000,0x266); +reg_write( DDR_REG_BASE +0x531c7*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x531c8*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x531c9*4+0x02000000,0xb880); +reg_write( DDR_REG_BASE +0x531ca*4+0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x531cb*4+0x02000000,0x141); +reg_write( DDR_REG_BASE +0x531cc*4+0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x531cd*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x531ce*4+0x02000000,0xc050); +reg_write( DDR_REG_BASE +0x531cf*4+0x02000000,0x215); +reg_write( DDR_REG_BASE +0x531d0*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x531d1*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x531d2*4+0x02000000,0xc110); +reg_write( DDR_REG_BASE +0x531d3*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x531d4*4+0x02000000,0xe5e); +reg_write( DDR_REG_BASE +0x531d5*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x531d6*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x531d7*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x531d8*4+0x02000000,0x1f6); +reg_write( DDR_REG_BASE +0x531d9*4+0x02000000,0x21); +reg_write( DDR_REG_BASE +0x531da*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x531db*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x531dc*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x531dd*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x531de*4+0x02000000,0xa8c1); +reg_write( DDR_REG_BASE +0x531df*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x531e0*4+0x02000000,0xb863); +reg_write( DDR_REG_BASE +0x531e1*4+0x02000000,0x7214); +reg_write( DDR_REG_BASE +0x531e2*4+0x02000000,0xa28); +reg_write( DDR_REG_BASE +0x531e3*4+0x02000000,0xfd45); +reg_write( DDR_REG_BASE +0x531e4*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x531e5*4+0x02000000,0xf79a); +reg_write( DDR_REG_BASE +0x531e6*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x531e7*4+0x02000000,0x831); +reg_write( DDR_REG_BASE +0x531e8*4+0x02000000,0x1b1); +reg_write( DDR_REG_BASE +0x531e9*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x531ea*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x531eb*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x531ec*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x531ed*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x531ee*4+0x02000000,0x265a); +reg_write( DDR_REG_BASE +0x531ef*4+0x02000000,0x1641); +reg_write( DDR_REG_BASE +0x531f0*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x531f1*4+0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x531f2*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x531f3*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x531f4*4+0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x531f5*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x531f6*4+0x02000000,0x67f); +reg_write( DDR_REG_BASE +0x531f7*4+0x02000000,0x7dbd); +reg_write( DDR_REG_BASE +0x531f8*4+0x02000000,0x7dbd); +reg_write( DDR_REG_BASE +0x531f9*4+0x02000000,0x7dbd); +reg_write( DDR_REG_BASE +0x531fa*4+0x02000000,0x7dbd); +reg_write( DDR_REG_BASE +0x531fb*4+0x02000000,0x7dbd); +reg_write( DDR_REG_BASE +0x531fc*4+0x02000000,0x7dbd); +reg_write( DDR_REG_BASE +0x531fd*4+0x02000000,0x7dbd); +reg_write( DDR_REG_BASE +0x531fe*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x531ff*4+0x02000000,0x3e00); +reg_write( DDR_REG_BASE +0x53200*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53201*4+0x02000000,0xfda); +reg_write( DDR_REG_BASE +0x53202*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x53203*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x53204*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53205*4+0x02000000,0x7614); +reg_write( DDR_REG_BASE +0x53206*4+0x02000000,0x164); +reg_write( DDR_REG_BASE +0x53207*4+0x02000000,0xd); +reg_write( DDR_REG_BASE +0x53208*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53209*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x5320a*4+0x02000000,0x2025); +reg_write( DDR_REG_BASE +0x5320b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5320c*4+0x02000000,0xf025); +reg_write( DDR_REG_BASE +0x5320d*4+0x02000000,0xf02b); +reg_write( DDR_REG_BASE +0x5320e*4+0x02000000,0xf02f); +reg_write( DDR_REG_BASE +0x5320f*4+0x02000000,0xf033); +reg_write( DDR_REG_BASE +0x53210*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x53211*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x53212*4+0x02000000,0xf034); +reg_write( DDR_REG_BASE +0x53213*4+0x02000000,0xc096); +reg_write( DDR_REG_BASE +0x53214*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x53215*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x53216*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x53217*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53218*4+0x02000000,0x10c); +reg_write( DDR_REG_BASE +0x53219*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5321a*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x5321b*4+0x02000000,0x3e00); +reg_write( DDR_REG_BASE +0x5321c*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5321d*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x5321e*4+0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x5321f*4+0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x53220*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x53221*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x53222*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53223*4+0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x53224*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53225*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53226*4+0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x53227*4+0x02000000,0x7514); +reg_write( DDR_REG_BASE +0x53228*4+0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x53229*4+0x02000000,0x31a1); +reg_write( DDR_REG_BASE +0x5322a*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x5322b*4+0x02000000,0xd7e); +reg_write( DDR_REG_BASE +0x5322c*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5322d*4+0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x5322e*4+0x02000000,0xdf8c); +reg_write( DDR_REG_BASE +0x5322f*4+0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x53230*4+0x02000000,0xf088); +reg_write( DDR_REG_BASE +0x53231*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53232*4+0x02000000,0xe0e); +reg_write( DDR_REG_BASE +0x53233*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x53234*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x53235*4+0x02000000,0x3e01); +reg_write( DDR_REG_BASE +0x53236*4+0x02000000,0xf09d); +reg_write( DDR_REG_BASE +0x53237*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53238*4+0x02000000,0xf36); +reg_write( DDR_REG_BASE +0x53239*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5323a*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x5323b*4+0x02000000,0x3e01); +reg_write( DDR_REG_BASE +0x5323c*4+0x02000000,0xf097); +reg_write( DDR_REG_BASE +0x5323d*4+0x02000000,0xac6); +reg_write( DDR_REG_BASE +0x5323e*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5323f*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53240*4+0x02000000,0xf093); +reg_write( DDR_REG_BASE +0x53241*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53242*4+0x02000000,0xf5e); +reg_write( DDR_REG_BASE +0x53243*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x53244*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x53245*4+0x02000000,0xf08f); +reg_write( DDR_REG_BASE +0x53246*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53247*4+0x02000000,0x76c4); +reg_write( DDR_REG_BASE +0x53248*4+0x02000000,0x900f); +reg_write( DDR_REG_BASE +0x53249*4+0x02000000,0xe022); +reg_write( DDR_REG_BASE +0x5324a*4+0x02000000,0xc096); +reg_write( DDR_REG_BASE +0x5324b*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5324c*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x5324d*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x5324e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5324f*4+0x02000000,0x10c); +reg_write( DDR_REG_BASE +0x53250*4+0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x53251*4+0x02000000,0xc308); +reg_write( DDR_REG_BASE +0x53252*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x53253*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x53254*4+0x02000000,0x3e00); +reg_write( DDR_REG_BASE +0x53255*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x53256*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53257*4+0x02000000,0xd96); +reg_write( DDR_REG_BASE +0x53258*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x53259*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5325a*4+0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x5325b*4+0x02000000,0xdcf); +reg_write( DDR_REG_BASE +0x5325c*4+0x02000000,0x1030); +reg_write( DDR_REG_BASE +0x5325d*4+0x02000000,0xdfc0); +reg_write( DDR_REG_BASE +0x5325e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5325f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53260*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x53261*4+0x02000000,0x8825); +reg_write( DDR_REG_BASE +0x53262*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53263*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53264*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x53265*4+0x02000000,0x8844); +reg_write( DDR_REG_BASE +0x53266*4+0x02000000,0x225f); +reg_write( DDR_REG_BASE +0x53267*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x53268*4+0x02000000,0xf02d); +reg_write( DDR_REG_BASE +0x53269*4+0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x5326a*4+0x02000000,0x30c0); +reg_write( DDR_REG_BASE +0x5326b*4+0x02000000,0xf025); +reg_write( DDR_REG_BASE +0x5326c*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x5326d*4+0x02000000,0x78d); +reg_write( DDR_REG_BASE +0x5326e*4+0x02000000,0xdf1b); +reg_write( DDR_REG_BASE +0x5326f*4+0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x53270*4+0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x53271*4+0x02000000,0x78bc); +reg_write( DDR_REG_BASE +0x53272*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x53273*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x53274*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x53275*4+0x02000000,0xbf61); +reg_write( DDR_REG_BASE +0x53276*4+0x02000000,0xfff); +reg_write( DDR_REG_BASE +0x53277*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x53278*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x53279*4+0x02000000,0x651f); +reg_write( DDR_REG_BASE +0x5327a*4+0x02000000,0xbfc4); +reg_write( DDR_REG_BASE +0x5327b*4+0x02000000,0x7f02); +reg_write( DDR_REG_BASE +0x5327c*4+0x02000000,0x2d44); +reg_write( DDR_REG_BASE +0x5327d*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x5327e*4+0x02000000,0x6ca1); +reg_write( DDR_REG_BASE +0x5327f*4+0x02000000,0x249a); +reg_write( DDR_REG_BASE +0x53280*4+0x02000000,0x1008); +reg_write( DDR_REG_BASE +0x53281*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x53282*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x53283*4+0x02000000,0x7f05); +reg_write( DDR_REG_BASE +0x53284*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x53285*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53286*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53287*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x53288*4+0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x53289*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5328a*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5328b*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x5328c*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x5328d*4+0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x5328e*4+0x02000000,0x44a9); +reg_write( DDR_REG_BASE +0x5328f*4+0x02000000,0xcbd); +reg_write( DDR_REG_BASE +0x53290*4+0x02000000,0x9234); +reg_write( DDR_REG_BASE +0x53291*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x53292*4+0x02000000,0x3e00); +reg_write( DDR_REG_BASE +0x53293*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x53294*4+0x02000000,0xe309); +reg_write( DDR_REG_BASE +0x53295*4+0x02000000,0x9ab); +reg_write( DDR_REG_BASE +0x53296*4+0x02000000,0x80a5); +reg_write( DDR_REG_BASE +0x53297*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x53298*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53299*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x5329a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5329b*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x5329c*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x5329d*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5329e*4+0x02000000,0xae2); +reg_write( DDR_REG_BASE +0x5329f*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x532a0*4+0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x532a1*4+0x02000000,0xc096); +reg_write( DDR_REG_BASE +0x532a2*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x532a3*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x532a4*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x532a5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532a6*4+0x02000000,0x10c); +reg_write( DDR_REG_BASE +0x532a7*4+0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x532a8*4+0x02000000,0xc308); +reg_write( DDR_REG_BASE +0x532a9*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x532aa*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x532ab*4+0x02000000,0x3e00); +reg_write( DDR_REG_BASE +0x532ac*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x532ad*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x532ae*4+0x02000000,0xce6); +reg_write( DDR_REG_BASE +0x532af*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x532b0*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x532b1*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x532b2*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x532b3*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x532b4*4+0x02000000,0xab6); +reg_write( DDR_REG_BASE +0x532b5*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x532b6*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x532b7*4+0x02000000,0xdfc0); +reg_write( DDR_REG_BASE +0x532b8*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x532b9*4+0x02000000,0x815); +reg_write( DDR_REG_BASE +0x532ba*4+0x02000000,0x370); +reg_write( DDR_REG_BASE +0x532bb*4+0x02000000,0x456b); +reg_write( DDR_REG_BASE +0x532bc*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x532bd*4+0x02000000,0x80d); +reg_write( DDR_REG_BASE +0x532be*4+0x02000000,0x1b0); +reg_write( DDR_REG_BASE +0x532bf*4+0x02000000,0x456b); +reg_write( DDR_REG_BASE +0x532c0*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x532c1*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x532c2*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x532c3*4+0x02000000,0xfea); +reg_write( DDR_REG_BASE +0x532c4*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x532c5*4+0x02000000,0xc191); +reg_write( DDR_REG_BASE +0x532c6*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x532c7*4+0x02000000,0xed0d); +reg_write( DDR_REG_BASE +0x532c8*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x532c9*4+0x02000000,0xc20e); +reg_write( DDR_REG_BASE +0x532ca*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x532cb*4+0x02000000,0x3e01); +reg_write( DDR_REG_BASE +0x532cc*4+0x02000000,0x671f); +reg_write( DDR_REG_BASE +0x532cd*4+0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x532ce*4+0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x532cf*4+0x02000000,0x84a); +reg_write( DDR_REG_BASE +0x532d0*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x532d1*4+0x02000000,0x78e5); +reg_write( DDR_REG_BASE +0x532d2*4+0x02000000,0x43b9); +reg_write( DDR_REG_BASE +0x532d3*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x532d4*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x532d5*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x532d6*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x532d7*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x532d8*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x532d9*4+0x02000000,0x7002); +reg_write( DDR_REG_BASE +0x532da*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x532db*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x532dc*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x532dd*4+0x02000000,0x7114); +reg_write( DDR_REG_BASE +0x532de*4+0x02000000,0x5e8); +reg_write( DDR_REG_BASE +0x532df*4+0x02000000,0xffee); +reg_write( DDR_REG_BASE +0x532e0*4+0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x532e1*4+0x02000000,0xd56); +reg_write( DDR_REG_BASE +0x532e2*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x532e3*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x532e4*4+0x02000000,0xca09); +reg_write( DDR_REG_BASE +0x532e5*4+0x02000000,0xe895); +reg_write( DDR_REG_BASE +0x532e6*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x532e7*4+0x02000000,0x811); +reg_write( DDR_REG_BASE +0x532e8*4+0x02000000,0xf1); +reg_write( DDR_REG_BASE +0x532e9*4+0x02000000,0x79cf); +reg_write( DDR_REG_BASE +0x532ea*4+0x02000000,0xcba); +reg_write( DDR_REG_BASE +0x532eb*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x532ec*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x532ed*4+0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x532ee*4+0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x532ef*4+0x02000000,0x817); +reg_write( DDR_REG_BASE +0x532f0*4+0x02000000,0x134); +reg_write( DDR_REG_BASE +0x532f1*4+0x02000000,0x7bcf); +reg_write( DDR_REG_BASE +0x532f2*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x532f3*4+0x02000000,0xc109); +reg_write( DDR_REG_BASE +0x532f4*4+0x02000000,0xc207); +reg_write( DDR_REG_BASE +0x532f5*4+0x02000000,0xbf2); +reg_write( DDR_REG_BASE +0x532f6*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x532f7*4+0x02000000,0x2052); +reg_write( DDR_REG_BASE +0x532f8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532f9*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x532fa*4+0x02000000,0x72d5); +reg_write( DDR_REG_BASE +0x532fb*4+0x02000000,0x57a); +reg_write( DDR_REG_BASE +0x532fc*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x532fd*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x532fe*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x532ff*4+0x02000000,0x819); +reg_write( DDR_REG_BASE +0x53300*4+0x02000000,0xd1); +reg_write( DDR_REG_BASE +0x53301*4+0x02000000,0xca09); +reg_write( DDR_REG_BASE +0x53302*4+0x02000000,0xe888); +reg_write( DDR_REG_BASE +0x53303*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53304*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53305*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53306*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53307*4+0x02000000,0xb8e5); +reg_write( DDR_REG_BASE +0x53308*4+0x02000000,0xcb8); +reg_write( DDR_REG_BASE +0x53309*4+0x02000000,0xfd42); +reg_write( DDR_REG_BASE +0x5330a*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5330b*4+0x02000000,0x7003); +reg_write( DDR_REG_BASE +0x5330c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5330d*4+0x02000000,0xf); +reg_write( DDR_REG_BASE +0x5330e*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x5330f*4+0x02000000,0x3d09); +reg_write( DDR_REG_BASE +0x53310*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x53311*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x53312*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53313*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x53314*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x53315*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53316*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53317*4+0x02000000,0xc1b1); +reg_write( DDR_REG_BASE +0x53318*4+0x02000000,0xc050); +reg_write( DDR_REG_BASE +0x53319*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5331a*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5331b*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5331c*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5331d*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x5331e*4+0x02000000,0xe96); +reg_write( DDR_REG_BASE +0x5331f*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x53320*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x53321*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53322*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53323*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x53324*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x53325*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x53326*4+0x02000000,0xb72); +reg_write( DDR_REG_BASE +0x53327*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x53328*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x53329*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x5332a*4+0x02000000,0xfca); +reg_write( DDR_REG_BASE +0x5332b*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x5332c*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x5332d*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x5332e*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5332f*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x53330*4+0x02000000,0x1f22); +reg_write( DDR_REG_BASE +0x53331*4+0x02000000,0x1015); +reg_write( DDR_REG_BASE +0x53332*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53333*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x53334*4+0x02000000,0x1fa7); +reg_write( DDR_REG_BASE +0x53335*4+0x02000000,0x101c); +reg_write( DDR_REG_BASE +0x53336*4+0x02000000,0x1fa8); +reg_write( DDR_REG_BASE +0x53337*4+0x02000000,0x101c); +reg_write( DDR_REG_BASE +0x53338*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x53339*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x5333a*4+0x02000000,0xb700); +reg_write( DDR_REG_BASE +0x5333b*4+0x02000000,0x1ffe); +reg_write( DDR_REG_BASE +0x5333c*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5333d*4+0x02000000,0xb705); +reg_write( DDR_REG_BASE +0x5333e*4+0x02000000,0x922); +reg_write( DDR_REG_BASE +0x5333f*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x53340*4+0x02000000,0x1ffc); +reg_write( DDR_REG_BASE +0x53341*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x53342*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x53343*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53344*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x53345*4+0x02000000,0x8e04); +reg_write( DDR_REG_BASE +0x53346*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x53347*4+0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x53348*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x53349*4+0x02000000,0x10fd); +reg_write( DDR_REG_BASE +0x5334a*4+0x02000000,0x809e); +reg_write( DDR_REG_BASE +0x5334b*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x5334c*4+0x02000000,0x3100); +reg_write( DDR_REG_BASE +0x5334d*4+0x02000000,0x780d); +reg_write( DDR_REG_BASE +0x5334e*4+0x02000000,0x791c); +reg_write( DDR_REG_BASE +0x5334f*4+0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x53350*4+0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x53351*4+0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x53352*4+0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x53353*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x53354*4+0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x53355*4+0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x53356*4+0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x53357*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x53358*4+0x02000000,0x8e05); +reg_write( DDR_REG_BASE +0x53359*4+0x02000000,0xc04d); +reg_write( DDR_REG_BASE +0x5335a*4+0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x5335b*4+0x02000000,0xc04e); +reg_write( DDR_REG_BASE +0x5335c*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x5335d*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x5335e*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5335f*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x53360*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53361*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53362*4+0x02000000,0x8e03); +reg_write( DDR_REG_BASE +0x53363*4+0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x53364*4+0x02000000,0x8e02); +reg_write( DDR_REG_BASE +0x53365*4+0x02000000,0x25f); +reg_write( DDR_REG_BASE +0x53366*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x53367*4+0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x53368*4+0x02000000,0xe13); +reg_write( DDR_REG_BASE +0x53369*4+0x02000000,0x315e); +reg_write( DDR_REG_BASE +0x5336a*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5336b*4+0x02000000,0xae05); +reg_write( DDR_REG_BASE +0x5336c*4+0x02000000,0xae04); +reg_write( DDR_REG_BASE +0x5336d*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5336e*4+0x02000000,0xae02); +reg_write( DDR_REG_BASE +0x5336f*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x53370*4+0x02000000,0xae03); +reg_write( DDR_REG_BASE +0x53371*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x53372*4+0x02000000,0x770c); +reg_write( DDR_REG_BASE +0x53373*4+0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x53374*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53375*4+0x02000000,0xf0d0); +reg_write( DDR_REG_BASE +0x53376*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x53377*4+0x02000000,0x37c1); +reg_write( DDR_REG_BASE +0x53378*4+0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x53379*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x5337a*4+0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x5337b*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x5337c*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5337d*4+0x02000000,0x1e01); +reg_write( DDR_REG_BASE +0x5337e*4+0x02000000,0x16c2); +reg_write( DDR_REG_BASE +0x5337f*4+0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x53380*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x53381*4+0x02000000,0x200f); +reg_write( DDR_REG_BASE +0x53382*4+0x02000000,0x6c2); +reg_write( DDR_REG_BASE +0x53383*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x53384*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x53385*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53386*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x53387*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53388*4+0x02000000,0x58); +reg_write( DDR_REG_BASE +0x53389*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x5338a*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5338b*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x5338c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5338d*4+0x02000000,0x25); +reg_write( DDR_REG_BASE +0x5338e*4+0x02000000,0x784f); +reg_write( DDR_REG_BASE +0x5338f*4+0x02000000,0x790b); +reg_write( DDR_REG_BASE +0x53390*4+0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x53391*4+0x02000000,0xf2b3); +reg_write( DDR_REG_BASE +0x53392*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x53393*4+0x02000000,0x6c7); +reg_write( DDR_REG_BASE +0x53394*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53395*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53396*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x53397*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x53398*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x53399*4+0x02000000,0x8ee); +reg_write( DDR_REG_BASE +0x5339a*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x5339b*4+0x02000000,0xc04f); +reg_write( DDR_REG_BASE +0x5339c*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x5339d*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5339e*4+0x02000000,0xd1e); +reg_write( DDR_REG_BASE +0x5339f*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x533a0*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x533a1*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x533a2*4+0x02000000,0xb52); +reg_write( DDR_REG_BASE +0x533a3*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x533a4*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x533a5*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x533a6*4+0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x533a7*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x533a8*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x533a9*4+0x02000000,0xe59f); +reg_write( DDR_REG_BASE +0x533aa*4+0x02000000,0x10c); +reg_write( DDR_REG_BASE +0x533ab*4+0x02000000,0x9); +reg_write( DDR_REG_BASE +0x533ac*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x533ad*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x533ae*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x533af*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x533b0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533b1*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x533b2*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x533b3*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x533b4*4+0x02000000,0xe040); +reg_write( DDR_REG_BASE +0x533b5*4+0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x533b6*4+0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x533b7*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x533b8*4+0x02000000,0x10fd); +reg_write( DDR_REG_BASE +0x533b9*4+0x02000000,0x8080); +reg_write( DDR_REG_BASE +0x533ba*4+0x02000000,0x82b); +reg_write( DDR_REG_BASE +0x533bb*4+0x02000000,0x15f); +reg_write( DDR_REG_BASE +0x533bc*4+0x02000000,0x8e25); +reg_write( DDR_REG_BASE +0x533bd*4+0x02000000,0x8e44); +reg_write( DDR_REG_BASE +0x533be*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x533bf*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x533c0*4+0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x533c1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533c2*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x533c3*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x533c4*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x533c5*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x533c6*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x533c7*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x533c8*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x533c9*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x533ca*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x533cb*4+0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x533cc*4+0x02000000,0x9e7); +reg_write( DDR_REG_BASE +0x533cd*4+0x02000000,0x8085); +reg_write( DDR_REG_BASE +0x533ce*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x533cf*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x533d0*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x533d1*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x533d2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533d3*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x533d4*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x533d5*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x533d6*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x533d7*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x533d8*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x533d9*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x533da*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x533db*4+0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x533dc*4+0x02000000,0x8ce); +reg_write( DDR_REG_BASE +0x533dd*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x533de*4+0x02000000,0xd814); +reg_write( DDR_REG_BASE +0x533df*4+0x02000000,0xa9e); +reg_write( DDR_REG_BASE +0x533e0*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x533e1*4+0x02000000,0xc010); +reg_write( DDR_REG_BASE +0x533e2*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x533e3*4+0x02000000,0xad2); +reg_write( DDR_REG_BASE +0x533e4*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x533e5*4+0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x533e6*4+0x02000000,0x8e04); +reg_write( DDR_REG_BASE +0x533e7*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x533e8*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x533e9*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x533ea*4+0x02000000,0xf034); +reg_write( DDR_REG_BASE +0x533eb*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x533ec*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x533ed*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x533ee*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x533ef*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533f0*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x533f1*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x533f2*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x533f3*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x533f4*4+0x02000000,0x170); +reg_write( DDR_REG_BASE +0x533f5*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x533f6*4+0x02000000,0xc245); +reg_write( DDR_REG_BASE +0x533f7*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x533f8*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x533f9*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x533fa*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x533fb*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x533fc*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x533fd*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x533fe*4+0x02000000,0x166); +reg_write( DDR_REG_BASE +0x533ff*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x53400*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x53401*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53402*4+0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x53403*4+0x02000000,0x200f); +reg_write( DDR_REG_BASE +0x53404*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x53405*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x53406*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x53407*4+0x02000000,0xae5); +reg_write( DDR_REG_BASE +0x53408*4+0x02000000,0x8234); +reg_write( DDR_REG_BASE +0x53409*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x5340a*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5340b*4+0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x5340c*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x5340d*4+0x02000000,0xf40b); +reg_write( DDR_REG_BASE +0x5340e*4+0x02000000,0xc303); +reg_write( DDR_REG_BASE +0x5340f*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x53410*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53411*4+0x02000000,0xe); +reg_write( DDR_REG_BASE +0x53412*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x53413*4+0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x53414*4+0x02000000,0xe96); +reg_write( DDR_REG_BASE +0x53415*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53416*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53417*4+0x02000000,0xc105); +reg_write( DDR_REG_BASE +0x53418*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x53419*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x5341a*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x5341b*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x5341c*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5341d*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5341e*4+0x02000000,0x8e25); +reg_write( DDR_REG_BASE +0x5341f*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x53420*4+0x02000000,0x997); +reg_write( DDR_REG_BASE +0x53421*4+0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x53422*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53423*4+0x02000000,0xdda); +reg_write( DDR_REG_BASE +0x53424*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53425*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x53426*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x53427*4+0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x53428*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x53429*4+0x02000000,0xf580); +reg_write( DDR_REG_BASE +0x5342a*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x5342b*4+0x02000000,0x2008); +reg_write( DDR_REG_BASE +0x5342c*4+0x02000000,0x340); +reg_write( DDR_REG_BASE +0x5342d*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5342e*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5342f*4+0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x53430*4+0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x53431*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53432*4+0x02000000,0x11); +reg_write( DDR_REG_BASE +0x53433*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53434*4+0x02000000,0x8ea); +reg_write( DDR_REG_BASE +0x53435*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53436*4+0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x53437*4+0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x53438*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x53439*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x5343a*4+0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x5343b*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5343c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5343d*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x5343e*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5343f*4+0x02000000,0xfa2); +reg_write( DDR_REG_BASE +0x53440*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x53441*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x53442*4+0x02000000,0xc502); +reg_write( DDR_REG_BASE +0x53443*4+0x02000000,0x7767); +reg_write( DDR_REG_BASE +0x53444*4+0x02000000,0x7077); +reg_write( DDR_REG_BASE +0x53445*4+0x02000000,0x664); +reg_write( DDR_REG_BASE +0x53446*4+0x02000000,0xffea); +reg_write( DDR_REG_BASE +0x53447*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x53448*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x53449*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5344a*4+0x02000000,0x13); +reg_write( DDR_REG_BASE +0x5344b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5344c*4+0x02000000,0x7812); +reg_write( DDR_REG_BASE +0x5344d*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x5344e*4+0x02000000,0xd); +reg_write( DDR_REG_BASE +0x5344f*4+0x02000000,0x8b6); +reg_write( DDR_REG_BASE +0x53450*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53451*4+0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x53452*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53453*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53454*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x53455*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53456*4+0x02000000,0x16); +reg_write( DDR_REG_BASE +0x53457*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x53458*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53459*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5345a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5345b*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5345c*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x5345d*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x5345e*4+0x02000000,0xe040); +reg_write( DDR_REG_BASE +0x5345f*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x53460*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x53461*4+0x02000000,0x2049); +reg_write( DDR_REG_BASE +0x53462*4+0x02000000,0x7c1); +reg_write( DDR_REG_BASE +0x53463*4+0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x53464*4+0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x53465*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x53466*4+0x02000000,0x10fd); +reg_write( DDR_REG_BASE +0x53467*4+0x02000000,0x809e); +reg_write( DDR_REG_BASE +0x53468*4+0x02000000,0xe37); +reg_write( DDR_REG_BASE +0x53469*4+0x02000000,0x315f); +reg_write( DDR_REG_BASE +0x5346a*4+0x02000000,0x8e65); +reg_write( DDR_REG_BASE +0x5346b*4+0x02000000,0x8e44); +reg_write( DDR_REG_BASE +0x5346c*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x5346d*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x5346e*4+0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x5346f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53470*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x53471*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53472*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x53473*4+0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x53474*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53475*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53476*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53477*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x53478*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x53479*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x5347a*4+0x02000000,0xbe7); +reg_write( DDR_REG_BASE +0x5347b*4+0x02000000,0x8085); +reg_write( DDR_REG_BASE +0x5347c*4+0x02000000,0x962); +reg_write( DDR_REG_BASE +0x5347d*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x5347e*4+0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x5347f*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x53480*4+0x02000000,0x10fd); +reg_write( DDR_REG_BASE +0x53481*4+0x02000000,0x809e); +reg_write( DDR_REG_BASE +0x53482*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x53483*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x53484*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x53485*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x53486*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53487*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x53488*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53489*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x5348a*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5348b*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5348c*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5348d*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x5348e*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x5348f*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x53490*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x53491*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x53492*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x53493*4+0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x53494*4+0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x53495*4+0x02000000,0x7110); +reg_write( DDR_REG_BASE +0x53496*4+0x02000000,0x5a4); +reg_write( DDR_REG_BASE +0x53497*4+0x02000000,0xffce); +reg_write( DDR_REG_BASE +0x53498*4+0x02000000,0xe15); +reg_write( DDR_REG_BASE +0x53499*4+0x02000000,0x315e); +reg_write( DDR_REG_BASE +0x5349a*4+0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x5349b*4+0x02000000,0xae05); +reg_write( DDR_REG_BASE +0x5349c*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x5349d*4+0x02000000,0xae04); +reg_write( DDR_REG_BASE +0x5349e*4+0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x5349f*4+0x02000000,0xae03); +reg_write( DDR_REG_BASE +0x534a0*4+0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x534a1*4+0x02000000,0xae02); +reg_write( DDR_REG_BASE +0x534a2*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x534a3*4+0x02000000,0x1fa7); +reg_write( DDR_REG_BASE +0x534a4*4+0x02000000,0x101c); +reg_write( DDR_REG_BASE +0x534a5*4+0x02000000,0x1fa8); +reg_write( DDR_REG_BASE +0x534a6*4+0x02000000,0x101c); +reg_write( DDR_REG_BASE +0x534a7*4+0x02000000,0xb700); +reg_write( DDR_REG_BASE +0x534a8*4+0x02000000,0xc0b1); +reg_write( DDR_REG_BASE +0x534a9*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x534aa*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x534ab*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x534ac*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x534ad*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x534ae*4+0x02000000,0xf209); +reg_write( DDR_REG_BASE +0x534af*4+0x02000000,0x821); +reg_write( DDR_REG_BASE +0x534b0*4+0x02000000,0x1d1); +reg_write( DDR_REG_BASE +0x534b1*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x534b2*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x534b3*4+0x02000000,0x238); +reg_write( DDR_REG_BASE +0x534b4*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x534b5*4+0x02000000,0x45); +reg_write( DDR_REG_BASE +0x534b6*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x534b7*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x534b8*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x534b9*4+0x02000000,0x238); +reg_write( DDR_REG_BASE +0x534ba*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x534bb*4+0x02000000,0x105); +reg_write( DDR_REG_BASE +0x534bc*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x534bd*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x534be*4+0x02000000,0x1209); +reg_write( DDR_REG_BASE +0x534bf*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x534c0*4+0x02000000,0xe903); +reg_write( DDR_REG_BASE +0x534c1*4+0x02000000,0x19); +reg_write( DDR_REG_BASE +0x534c2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534c3*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x534c4*4+0x02000000,0x9018); +reg_write( DDR_REG_BASE +0x534c5*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x534c6*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x534c7*4+0x02000000,0x55); +reg_write( DDR_REG_BASE +0x534c8*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x534c9*4+0x02000000,0x1902); +reg_write( DDR_REG_BASE +0x534ca*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x534cb*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x534cc*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x534cd*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x534ce*4+0x02000000,0xca09); +reg_write( DDR_REG_BASE +0x534cf*4+0x02000000,0xe812); +reg_write( DDR_REG_BASE +0x534d0*4+0x02000000,0xcc22); +reg_write( DDR_REG_BASE +0x534d1*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x534d2*4+0x02000000,0x8010); +reg_write( DDR_REG_BASE +0x534d3*4+0x02000000,0xf785); +reg_write( DDR_REG_BASE +0x534d4*4+0x02000000,0xfc2); +reg_write( DDR_REG_BASE +0x534d5*4+0x02000000,0xfd0f); +reg_write( DDR_REG_BASE +0x534d6*4+0x02000000,0xcc22); +reg_write( DDR_REG_BASE +0x534d7*4+0x02000000,0x2615); +reg_write( DDR_REG_BASE +0x534d8*4+0x02000000,0x7001); +reg_write( DDR_REG_BASE +0x534d9*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x534da*4+0x02000000,0x8e8); +reg_write( DDR_REG_BASE +0x534db*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x534dc*4+0x02000000,0xa1a0); +reg_write( DDR_REG_BASE +0x534dd*4+0x02000000,0x1a22); +reg_write( DDR_REG_BASE +0x534de*4+0x02000000,0x301c); +reg_write( DDR_REG_BASE +0x534df*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x534e0*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x534e1*4+0x02000000,0x9018); +reg_write( DDR_REG_BASE +0x534e2*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x534e3*4+0x02000000,0xb1a0); +reg_write( DDR_REG_BASE +0x534e4*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x534e5*4+0x02000000,0xdd10); +reg_write( DDR_REG_BASE +0x534e6*4+0x02000000,0xbd61); +reg_write( DDR_REG_BASE +0x534e7*4+0x02000000,0xd01); +reg_write( DDR_REG_BASE +0x534e8*4+0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x534e9*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x534ea*4+0x02000000,0xb102); +reg_write( DDR_REG_BASE +0x534eb*4+0x02000000,0x80e); +reg_write( DDR_REG_BASE +0x534ec*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x534ed*4+0x02000000,0x1902); +reg_write( DDR_REG_BASE +0x534ee*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x534ef*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x534f0*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x534f1*4+0x02000000,0x9018); +reg_write( DDR_REG_BASE +0x534f2*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x534f3*4+0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x534f4*4+0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x534f5*4+0x02000000,0x801f); +reg_write( DDR_REG_BASE +0x534f6*4+0x02000000,0x195e); +reg_write( DDR_REG_BASE +0x534f7*4+0x02000000,0x45); +reg_write( DDR_REG_BASE +0x534f8*4+0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x534f9*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x534fa*4+0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x534fb*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x534fc*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x534fd*4+0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x534fe*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x534ff*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53500*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53501*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53502*4+0x02000000,0x83b); +reg_write( DDR_REG_BASE +0x53503*4+0x02000000,0x13f); +reg_write( DDR_REG_BASE +0x53504*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x53505*4+0x02000000,0xca09); +reg_write( DDR_REG_BASE +0x53506*4+0x02000000,0x7ef0); +reg_write( DDR_REG_BASE +0x53507*4+0x02000000,0xe80a); +reg_write( DDR_REG_BASE +0x53508*4+0x02000000,0xcc22); +reg_write( DDR_REG_BASE +0x53509*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x5350a*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5350b*4+0x02000000,0x7902); +reg_write( DDR_REG_BASE +0x5350c*4+0x02000000,0x6e02); +reg_write( DDR_REG_BASE +0x5350d*4+0x02000000,0x7030); +reg_write( DDR_REG_BASE +0x5350e*4+0x02000000,0xf4c); +reg_write( DDR_REG_BASE +0x5350f*4+0x02000000,0xfd0a); +reg_write( DDR_REG_BASE +0x53510*4+0x02000000,0xf3a); +reg_write( DDR_REG_BASE +0x53511*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x53512*4+0x02000000,0xd808); +reg_write( DDR_REG_BASE +0x53513*4+0x02000000,0xf76); +reg_write( DDR_REG_BASE +0x53514*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x53515*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x53516*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x53517*4+0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x53518*4+0x02000000,0xf6a); +reg_write( DDR_REG_BASE +0x53519*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5351a*4+0x02000000,0x1504); +reg_write( DDR_REG_BASE +0x5351b*4+0x02000000,0x1400); +reg_write( DDR_REG_BASE +0x5351c*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x5351d*4+0x02000000,0xff9); +reg_write( DDR_REG_BASE +0x5351e*4+0x02000000,0x9384); +reg_write( DDR_REG_BASE +0x5351f*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53520*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x53521*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53522*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53523*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x53524*4+0x02000000,0x3109); +reg_write( DDR_REG_BASE +0x53525*4+0x02000000,0xc352); +reg_write( DDR_REG_BASE +0x53526*4+0x02000000,0xc245); +reg_write( DDR_REG_BASE +0x53527*4+0x02000000,0xc154); +reg_write( DDR_REG_BASE +0x53528*4+0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x53529*4+0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x5352a*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x5352b*4+0x02000000,0x88a0); +reg_write( DDR_REG_BASE +0x5352c*4+0x02000000,0x10fc); +reg_write( DDR_REG_BASE +0x5352d*4+0x02000000,0x808e); +reg_write( DDR_REG_BASE +0x5352e*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5352f*4+0x02000000,0x710f); +reg_write( DDR_REG_BASE +0x53530*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x53531*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x53532*4+0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x53533*4+0x02000000,0xc06); +reg_write( DDR_REG_BASE +0x53534*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53535*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53536*4+0x02000000,0xc050); +reg_write( DDR_REG_BASE +0x53537*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53538*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53539*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x5353a*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x5353b*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x5353c*4+0x02000000,0xf46); +reg_write( DDR_REG_BASE +0x5353d*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x5353e*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x5353f*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53540*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53541*4+0x02000000,0xff7f); +reg_write( DDR_REG_BASE +0x53542*4+0x02000000,0x78e4); +reg_write( DDR_REG_BASE +0x53543*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53544*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x53545*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x53546*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x53547*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x53548*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x53549*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5354a*4+0x02000000,0x1e4); +reg_write( DDR_REG_BASE +0x5354b*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5354c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5354d*4+0x02000000,0x44d); +reg_write( DDR_REG_BASE +0x5354e*4+0x02000000,0xde6); +reg_write( DDR_REG_BASE +0x5354f*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53550*4+0x02000000,0xda60); +reg_write( DDR_REG_BASE +0x53551*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x53552*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x53553*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53554*4+0x02000000,0x1e4); +reg_write( DDR_REG_BASE +0x53555*4+0x02000000,0xae2); +reg_write( DDR_REG_BASE +0x53556*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x53557*4+0x02000000,0xd960); +reg_write( DDR_REG_BASE +0x53558*4+0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x53559*4+0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x5355a*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x5355b*4+0x02000000,0x37cf); +reg_write( DDR_REG_BASE +0x5355c*4+0x02000000,0xef05); +reg_write( DDR_REG_BASE +0x5355d*4+0x02000000,0xbf61); +reg_write( DDR_REG_BASE +0x5355e*4+0x02000000,0xfff); +reg_write( DDR_REG_BASE +0x5355f*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x53560*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53561*4+0x02000000,0x7edd); +reg_write( DDR_REG_BASE +0x53562*4+0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x53563*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x53564*4+0x02000000,0x7edd); +reg_write( DDR_REG_BASE +0x53565*4+0x02000000,0x7edd); +reg_write( DDR_REG_BASE +0x53566*4+0x02000000,0x7edd); +reg_write( DDR_REG_BASE +0x53567*4+0x02000000,0x200f); +reg_write( DDR_REG_BASE +0x53568*4+0x02000000,0x6c2); +reg_write( DDR_REG_BASE +0x53569*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5356a*4+0x02000000,0x7edd); +reg_write( DDR_REG_BASE +0x5356b*4+0x02000000,0x7edd); +reg_write( DDR_REG_BASE +0x5356c*4+0x02000000,0xe807); +reg_write( DDR_REG_BASE +0x5356d*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5356e*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5356f*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x53570*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53571*4+0x02000000,0xf0c4); +reg_write( DDR_REG_BASE +0x53572*4+0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x53573*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53574*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x53575*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x53576*4+0x02000000,0x7c1); +reg_write( DDR_REG_BASE +0x53577*4+0x02000000,0xe906); +reg_write( DDR_REG_BASE +0x53578*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x53579*4+0x02000000,0x901); +reg_write( DDR_REG_BASE +0x5357a*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x5357b*4+0x02000000,0x7c9b); +reg_write( DDR_REG_BASE +0x5357c*4+0x02000000,0x6821); +reg_write( DDR_REG_BASE +0x5357d*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x5357e*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x5357f*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53580*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53581*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53582*4+0x02000000,0xe0c4); +reg_write( DDR_REG_BASE +0x53583*4+0x02000000,0xb080); +reg_write( DDR_REG_BASE +0x53584*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x53585*4+0x02000000,0x8e3); +reg_write( DDR_REG_BASE +0x53586*4+0x02000000,0x8234); +reg_write( DDR_REG_BASE +0x53587*4+0x02000000,0x4468); +reg_write( DDR_REG_BASE +0x53588*4+0x02000000,0x1498); +reg_write( DDR_REG_BASE +0x53589*4+0x02000000,0x3600); +reg_write( DDR_REG_BASE +0x5358a*4+0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x5358b*4+0x02000000,0x1f8d); +reg_write( DDR_REG_BASE +0x5358c*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5358d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5358e*4+0x02000000,0x7bc6); +reg_write( DDR_REG_BASE +0x5358f*4+0x02000000,0xc04d); +reg_write( DDR_REG_BASE +0x53590*4+0x02000000,0x1497); +reg_write( DDR_REG_BASE +0x53591*4+0x02000000,0x3600); +reg_write( DDR_REG_BASE +0x53592*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53593*4+0x02000000,0xc34c); +reg_write( DDR_REG_BASE +0x53594*4+0x02000000,0xc04e); +reg_write( DDR_REG_BASE +0x53595*4+0x02000000,0x1496); +reg_write( DDR_REG_BASE +0x53596*4+0x02000000,0x3600); +reg_write( DDR_REG_BASE +0x53597*4+0x02000000,0xc551); +reg_write( DDR_REG_BASE +0x53598*4+0x02000000,0xc04f); +reg_write( DDR_REG_BASE +0x53599*4+0x02000000,0x784f); +reg_write( DDR_REG_BASE +0x5359a*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5359b*4+0x02000000,0x926); +reg_write( DDR_REG_BASE +0x5359c*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5359d*4+0x02000000,0xc053); +reg_write( DDR_REG_BASE +0x5359e*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5359f*4+0x02000000,0xc14a); +reg_write( DDR_REG_BASE +0x535a0*4+0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x535a1*4+0x02000000,0x7a3b); +reg_write( DDR_REG_BASE +0x535a2*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x535a3*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x535a4*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x535a5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535a6*4+0x02000000,0x1c4); +reg_write( DDR_REG_BASE +0x535a7*4+0x02000000,0x22ce); +reg_write( DDR_REG_BASE +0x535a8*4+0x02000000,0x21); +reg_write( DDR_REG_BASE +0x535a9*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x535aa*4+0x02000000,0xa840); +reg_write( DDR_REG_BASE +0x535ab*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x535ac*4+0x02000000,0x9eb); +reg_write( DDR_REG_BASE +0x535ad*4+0x02000000,0x8434); +reg_write( DDR_REG_BASE +0x535ae*4+0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x535af*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x535b0*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x535b1*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x535b2*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x535b3*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x535b4*4+0x02000000,0x709e); +reg_write( DDR_REG_BASE +0x535b5*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x535b6*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x535b7*4+0x02000000,0x8881); +reg_write( DDR_REG_BASE +0x535b8*4+0x02000000,0x250a); +reg_write( DDR_REG_BASE +0x535b9*4+0x02000000,0x1780); +reg_write( DDR_REG_BASE +0x535ba*4+0x02000000,0xf047); +reg_write( DDR_REG_BASE +0x535bb*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x535bc*4+0x02000000,0xf042); +reg_write( DDR_REG_BASE +0x535bd*4+0x02000000,0xc010); +reg_write( DDR_REG_BASE +0x535be*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x535bf*4+0x02000000,0xc01); +reg_write( DDR_REG_BASE +0x535c0*4+0x02000000,0xc011); +reg_write( DDR_REG_BASE +0x535c1*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x535c2*4+0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x535c3*4+0x02000000,0x1f81); +reg_write( DDR_REG_BASE +0x535c4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535c5*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x535c6*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x535c7*4+0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x535c8*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x535c9*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x535ca*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x535cb*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x535cc*4+0x02000000,0xb891); +reg_write( DDR_REG_BASE +0x535cd*4+0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x535ce*4+0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x535cf*4+0x02000000,0x90e0); +reg_write( DDR_REG_BASE +0x535d0*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x535d1*4+0x02000000,0x2378); +reg_write( DDR_REG_BASE +0x535d2*4+0x02000000,0x201); +reg_write( DDR_REG_BASE +0x535d3*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x535d4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535d5*4+0x02000000,0x2007); +reg_write( DDR_REG_BASE +0x535d6*4+0x02000000,0x807e); +reg_write( DDR_REG_BASE +0x535d7*4+0x02000000,0xf427); +reg_write( DDR_REG_BASE +0x535d8*4+0x02000000,0x78fd); +reg_write( DDR_REG_BASE +0x535d9*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x535da*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x535db*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x535dc*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x535dd*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x535de*4+0x02000000,0xbfc4); +reg_write( DDR_REG_BASE +0x535df*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x535e0*4+0x02000000,0xe807); +reg_write( DDR_REG_BASE +0x535e1*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x535e2*4+0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x535e3*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x535e4*4+0x02000000,0x2180); +reg_write( DDR_REG_BASE +0x535e5*4+0x02000000,0x30); +reg_write( DDR_REG_BASE +0x535e6*4+0x02000000,0x79e5); +reg_write( DDR_REG_BASE +0x535e7*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x535e8*4+0x02000000,0x148b); +reg_write( DDR_REG_BASE +0x535e9*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x535ea*4+0x02000000,0x3882); +reg_write( DDR_REG_BASE +0x535eb*4+0x02000000,0x7261); +reg_write( DDR_REG_BASE +0x535ec*4+0x02000000,0x7a74); +reg_write( DDR_REG_BASE +0x535ed*4+0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x535ee*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x535ef*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535f0*4+0x02000000,0x141f); +reg_write( DDR_REG_BASE +0x535f1*4+0x02000000,0x813); +reg_write( DDR_REG_BASE +0x535f2*4+0x02000000,0x150); +reg_write( DDR_REG_BASE +0x535f3*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x535f4*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x535f5*4+0x02000000,0x2080); +reg_write( DDR_REG_BASE +0x535f6*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x535f7*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x535f8*4+0x02000000,0x3c1); +reg_write( DDR_REG_BASE +0x535f9*4+0x02000000,0xc097); +reg_write( DDR_REG_BASE +0x535fa*4+0x02000000,0x7061); +reg_write( DDR_REG_BASE +0x535fb*4+0x02000000,0x7874); +reg_write( DDR_REG_BASE +0x535fc*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x535fd*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x535fe*4+0x02000000,0xb7f); +reg_write( DDR_REG_BASE +0x535ff*4+0x02000000,0x8254); +reg_write( DDR_REG_BASE +0x53600*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x53601*4+0x02000000,0x7eaf); +reg_write( DDR_REG_BASE +0x53602*4+0x02000000,0xc73); +reg_write( DDR_REG_BASE +0x53603*4+0x02000000,0x93a5); +reg_write( DDR_REG_BASE +0x53604*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x53605*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53606*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53607*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x53608*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x53609*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5360a*4+0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x5360b*4+0x02000000,0x703c); +reg_write( DDR_REG_BASE +0x5360c*4+0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x5360d*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x5360e*4+0x02000000,0x3240); +reg_write( DDR_REG_BASE +0x5360f*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53610*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53611*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x53612*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53613*4+0x02000000,0xc055); +reg_write( DDR_REG_BASE +0x53614*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x53615*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x53616*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x53617*4+0x02000000,0xf0df); +reg_write( DDR_REG_BASE +0x53618*4+0x02000000,0xc109); +reg_write( DDR_REG_BASE +0x53619*4+0x02000000,0x8d2); +reg_write( DDR_REG_BASE +0x5361a*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5361b*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x5361c*4+0x02000000,0x3880); +reg_write( DDR_REG_BASE +0x5361d*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x5361e*4+0x02000000,0x9e2); +reg_write( DDR_REG_BASE +0x5361f*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53620*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x53621*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x53622*4+0x02000000,0xb5a); +reg_write( DDR_REG_BASE +0x53623*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x53624*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x53625*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x53626*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53627*4+0x02000000,0xe024); +reg_write( DDR_REG_BASE +0x53628*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x53629*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5362a*4+0x02000000,0x1f84); +reg_write( DDR_REG_BASE +0x5362b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5362c*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x5362d*4+0x02000000,0xb606); +reg_write( DDR_REG_BASE +0x5362e*4+0x02000000,0x1efe); +reg_write( DDR_REG_BASE +0x5362f*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x53630*4+0x02000000,0x1ea8); +reg_write( DDR_REG_BASE +0x53631*4+0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x53632*4+0x02000000,0x1ea9); +reg_write( DDR_REG_BASE +0x53633*4+0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x53634*4+0x02000000,0xc014); +reg_write( DDR_REG_BASE +0x53635*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53636*4+0x02000000,0xe020); +reg_write( DDR_REG_BASE +0x53637*4+0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x53638*4+0x02000000,0xe26); +reg_write( DDR_REG_BASE +0x53639*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x5363a*4+0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x5363b*4+0x02000000,0xc015); +reg_write( DDR_REG_BASE +0x5363c*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5363d*4+0x02000000,0x68e1); +reg_write( DDR_REG_BASE +0x5363e*4+0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x5363f*4+0x02000000,0xcc6); +reg_write( DDR_REG_BASE +0x53640*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x53641*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x53642*4+0x02000000,0xc109); +reg_write( DDR_REG_BASE +0x53643*4+0x02000000,0x87e); +reg_write( DDR_REG_BASE +0x53644*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x53645*4+0x02000000,0xc097); +reg_write( DDR_REG_BASE +0x53646*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53647*4+0x02000000,0x992); +reg_write( DDR_REG_BASE +0x53648*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53649*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x5364a*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x5364b*4+0x02000000,0xb0a); +reg_write( DDR_REG_BASE +0x5364c*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x5364d*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x5364e*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5364f*4+0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x53650*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53651*4+0x02000000,0x1f84); +reg_write( DDR_REG_BASE +0x53652*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53653*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x53654*4+0x02000000,0xb626); +reg_write( DDR_REG_BASE +0x53655*4+0x02000000,0x1efe); +reg_write( DDR_REG_BASE +0x53656*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x53657*4+0x02000000,0x1ea8); +reg_write( DDR_REG_BASE +0x53658*4+0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x53659*4+0x02000000,0xde6); +reg_write( DDR_REG_BASE +0x5365a*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x5365b*4+0x02000000,0x1ea9); +reg_write( DDR_REG_BASE +0x5365c*4+0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x5365d*4+0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x5365e*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5365f*4+0x02000000,0xc86); +reg_write( DDR_REG_BASE +0x53660*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x53661*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x53662*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x53663*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x53664*4+0x02000000,0xc056); +reg_write( DDR_REG_BASE +0x53665*4+0x02000000,0xe08f); +reg_write( DDR_REG_BASE +0x53666*4+0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x53667*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x53668*4+0x02000000,0x61); +reg_write( DDR_REG_BASE +0x53669*4+0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x5366a*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5366b*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5366c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5366d*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x5366e*4+0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x5366f*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53670*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x53671*4+0x02000000,0xf075); +reg_write( DDR_REG_BASE +0x53672*4+0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x53673*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x53674*4+0x02000000,0xc607); +reg_write( DDR_REG_BASE +0x53675*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x53676*4+0x02000000,0xc146); +reg_write( DDR_REG_BASE +0x53677*4+0x02000000,0x722c); +reg_write( DDR_REG_BASE +0x53678*4+0x02000000,0xf068); +reg_write( DDR_REG_BASE +0x53679*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x5367a*4+0x02000000,0xe17); +reg_write( DDR_REG_BASE +0x5367b*4+0x02000000,0x1231); +reg_write( DDR_REG_BASE +0x5367c*4+0x02000000,0x7a10); +reg_write( DDR_REG_BASE +0x5367d*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5367e*4+0x02000000,0xe887); +reg_write( DDR_REG_BASE +0x5367f*4+0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x53680*4+0x02000000,0x7854); +reg_write( DDR_REG_BASE +0x53681*4+0x02000000,0x10f0); +reg_write( DDR_REG_BASE +0x53682*4+0x02000000,0x8102); +reg_write( DDR_REG_BASE +0x53683*4+0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x53684*4+0x02000000,0xf058); +reg_write( DDR_REG_BASE +0x53685*4+0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x53686*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x53687*4+0x02000000,0x83); +reg_write( DDR_REG_BASE +0x53688*4+0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x53689*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x5368a*4+0x02000000,0x8c); +reg_write( DDR_REG_BASE +0x5368b*4+0x02000000,0x4c70); +reg_write( DDR_REG_BASE +0x5368c*4+0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x5368d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5368e*4+0x02000000,0x7f0e); +reg_write( DDR_REG_BASE +0x5368f*4+0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x53690*4+0x02000000,0x11b3); +reg_write( DDR_REG_BASE +0x53691*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x53692*4+0x02000000,0x203c); +reg_write( DDR_REG_BASE +0x53693*4+0x02000000,0x39b); +reg_write( DDR_REG_BASE +0x53694*4+0x02000000,0x991); +reg_write( DDR_REG_BASE +0x53695*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x53696*4+0x02000000,0x43c1); +reg_write( DDR_REG_BASE +0x53697*4+0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x53698*4+0x02000000,0xc208); +reg_write( DDR_REG_BASE +0x53699*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5369a*4+0x02000000,0x14); +reg_write( DDR_REG_BASE +0x5369b*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x5369c*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x5369d*4+0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x5369e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5369f*4+0x02000000,0xc16); +reg_write( DDR_REG_BASE +0x536a0*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x536a1*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x536a2*4+0x02000000,0xc010); +reg_write( DDR_REG_BASE +0x536a3*4+0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x536a4*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x536a5*4+0x02000000,0x8c1); +reg_write( DDR_REG_BASE +0x536a6*4+0x02000000,0xc011); +reg_write( DDR_REG_BASE +0x536a7*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x536a8*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x536a9*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x536aa*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x536ab*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ac*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x536ad*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x536ae*4+0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x536af*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x536b0*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x536b1*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x536b2*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x536b3*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x536b4*4+0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x536b5*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x536b6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536b7*4+0x02000000,0x9540); +reg_write( DDR_REG_BASE +0x536b8*4+0x02000000,0xc016); +reg_write( DDR_REG_BASE +0x536b9*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x536ba*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x536bb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536bc*4+0x02000000,0x1c4); +reg_write( DDR_REG_BASE +0x536bd*4+0x02000000,0x2133); +reg_write( DDR_REG_BASE +0x536be*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x536bf*4+0x02000000,0xc240); +reg_write( DDR_REG_BASE +0x536c0*4+0x02000000,0x6158); +reg_write( DDR_REG_BASE +0x536c1*4+0x02000000,0x780e); +reg_write( DDR_REG_BASE +0x536c2*4+0x02000000,0xc208); +reg_write( DDR_REG_BASE +0x536c3*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x536c4*4+0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x536c5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536c6*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x536c7*4+0x02000000,0x2049); +reg_write( DDR_REG_BASE +0x536c8*4+0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x536c9*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x536ca*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x536cb*4+0x02000000,0x15); +reg_write( DDR_REG_BASE +0x536cc*4+0x02000000,0x6); +reg_write( DDR_REG_BASE +0x536cd*4+0x02000000,0x926); +reg_write( DDR_REG_BASE +0x536ce*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x536cf*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x536d0*4+0x02000000,0xb5e0); +reg_write( DDR_REG_BASE +0x536d1*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x536d2*4+0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x536d3*4+0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x536d4*4+0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x536d5*4+0x02000000,0x2014); +reg_write( DDR_REG_BASE +0x536d6*4+0x02000000,0x82); +reg_write( DDR_REG_BASE +0x536d7*4+0x02000000,0x6478); +reg_write( DDR_REG_BASE +0x536d8*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x536d9*4+0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x536da*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536db*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x536dc*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x536dd*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x536de*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x536df*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x536e0*4+0x02000000,0xe33); +reg_write( DDR_REG_BASE +0x536e1*4+0x02000000,0x9254); +reg_write( DDR_REG_BASE +0x536e2*4+0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x536e3*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x536e4*4+0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x536e5*4+0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x536e6*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x536e7*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x536e8*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x536e9*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x536ea*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x536eb*4+0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x536ec*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x536ed*4+0x02000000,0x90d); +reg_write( DDR_REG_BASE +0x536ee*4+0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x536ef*4+0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x536f0*4+0x02000000,0xbe0); +reg_write( DDR_REG_BASE +0x536f1*4+0x02000000,0xfe82); +reg_write( DDR_REG_BASE +0x536f2*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x536f3*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x536f4*4+0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x536f5*4+0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x536f6*4+0x02000000,0xf522); +reg_write( DDR_REG_BASE +0x536f7*4+0x02000000,0xc012); +reg_write( DDR_REG_BASE +0x536f8*4+0x02000000,0x881); +reg_write( DDR_REG_BASE +0x536f9*4+0x02000000,0x30); +reg_write( DDR_REG_BASE +0x536fa*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x536fb*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x536fc*4+0x02000000,0x16); +reg_write( DDR_REG_BASE +0x536fd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536fe*4+0x02000000,0x8c2); +reg_write( DDR_REG_BASE +0x536ff*4+0x02000000,0xfd0f); +reg_write( DDR_REG_BASE +0x53700*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53701*4+0x02000000,0x708e); +reg_write( DDR_REG_BASE +0x53702*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53703*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53704*4+0x02000000,0xf02d); +reg_write( DDR_REG_BASE +0x53705*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53706*4+0x02000000,0xc707); +reg_write( DDR_REG_BASE +0x53707*4+0x02000000,0x7910); +reg_write( DDR_REG_BASE +0x53708*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x53709*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x5370a*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5370b*4+0x02000000,0xf024); +reg_write( DDR_REG_BASE +0x5370c*4+0x02000000,0xf09); +reg_write( DDR_REG_BASE +0x5370d*4+0x02000000,0x1211); +reg_write( DDR_REG_BASE +0x5370e*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5370f*4+0x02000000,0xe81c); +reg_write( DDR_REG_BASE +0x53710*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53711*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53712*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x53713*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x53714*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53715*4+0x02000000,0xfffe); +reg_write( DDR_REG_BASE +0x53716*4+0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x53717*4+0x02000000,0x2035); +reg_write( DDR_REG_BASE +0x53718*4+0x02000000,0x43); +reg_write( DDR_REG_BASE +0x53719*4+0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x5371a*4+0x02000000,0x2035); +reg_write( DDR_REG_BASE +0x5371b*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x5371c*4+0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x5371d*4+0x02000000,0x2035); +reg_write( DDR_REG_BASE +0x5371e*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x5371f*4+0x02000000,0xc241); +reg_write( DDR_REG_BASE +0x53720*4+0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x53721*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53722*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x53723*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53724*4+0x02000000,0x17); +reg_write( DDR_REG_BASE +0x53725*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x53726*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x53727*4+0x02000000,0x872); +reg_write( DDR_REG_BASE +0x53728*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53729*4+0x02000000,0x43e1); +reg_write( DDR_REG_BASE +0x5372a*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5372b*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x5372c*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5372d*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5372e*4+0x02000000,0xfbd); +reg_write( DDR_REG_BASE +0x5372f*4+0x02000000,0x9254); +reg_write( DDR_REG_BASE +0x53730*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x53731*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53732*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53733*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53734*4+0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x53735*4+0x02000000,0x7dcf); +reg_write( DDR_REG_BASE +0x53736*4+0x02000000,0x89f); +reg_write( DDR_REG_BASE +0x53737*4+0x02000000,0x8345); +reg_write( DDR_REG_BASE +0x53738*4+0x02000000,0x98a); +reg_write( DDR_REG_BASE +0x53739*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x5373a*4+0x02000000,0xc013); +reg_write( DDR_REG_BASE +0x5373b*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5373c*4+0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x5373d*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5373e*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x5373f*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x53740*4+0x02000000,0x3109); +reg_write( DDR_REG_BASE +0x53741*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x53742*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x53743*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53744*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x53745*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53746*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53747*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x53748*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x53749*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x5374a*4+0x02000000,0x641); +reg_write( DDR_REG_BASE +0x5374b*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5374c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5374d*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x5374e*4+0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x5374f*4+0x02000000,0x4358); +reg_write( DDR_REG_BASE +0x53750*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x53751*4+0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x53752*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x53753*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x53754*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53755*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53756*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x53757*4+0x02000000,0x88e2); +reg_write( DDR_REG_BASE +0x53758*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53759*4+0x02000000,0xb4e); +reg_write( DDR_REG_BASE +0x5375a*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x5375b*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5375c*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5375d*4+0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x5375e*4+0x02000000,0x17ca); +reg_write( DDR_REG_BASE +0x5375f*4+0x02000000,0xa11); +reg_write( DDR_REG_BASE +0x53760*4+0x02000000,0x1010); +reg_write( DDR_REG_BASE +0x53761*4+0x02000000,0x2242); +reg_write( DDR_REG_BASE +0x53762*4+0x02000000,0x104a); +reg_write( DDR_REG_BASE +0x53763*4+0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x53764*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x53765*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53766*4+0x02000000,0x7077); +reg_write( DDR_REG_BASE +0x53767*4+0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x53768*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x53769*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5376a*4+0x02000000,0x27cf); +reg_write( DDR_REG_BASE +0x5376b*4+0x02000000,0x11e2); +reg_write( DDR_REG_BASE +0x5376c*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x5376d*4+0x02000000,0x200f); +reg_write( DDR_REG_BASE +0x5376e*4+0x02000000,0x340); +reg_write( DDR_REG_BASE +0x5376f*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x53770*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53771*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53772*4+0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x53773*4+0x02000000,0x4628); +reg_write( DDR_REG_BASE +0x53774*4+0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x53775*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x53776*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x53777*4+0x02000000,0xdfa); +reg_write( DDR_REG_BASE +0x53778*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53779*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x5377a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5377b*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x5377c*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5377d*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5377e*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x5377f*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x53780*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x53781*4+0x02000000,0xbd6); +reg_write( DDR_REG_BASE +0x53782*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53783*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x53784*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53785*4+0x02000000,0xb8e); +reg_write( DDR_REG_BASE +0x53786*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53787*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53788*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x53789*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x5378a*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x5378b*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5378c*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5378d*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5378e*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5378f*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x53790*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x53791*4+0x02000000,0x9d2); +reg_write( DDR_REG_BASE +0x53792*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x53793*4+0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x53794*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x53795*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53796*4+0x02000000,0xad2); +reg_write( DDR_REG_BASE +0x53797*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53798*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x53799*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x5379a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5379b*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5379c*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5379d*4+0x02000000,0xdb28); +reg_write( DDR_REG_BASE +0x5379e*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x5379f*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537a0*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x537a1*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x537a2*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537a3*4+0x02000000,0xb92); +reg_write( DDR_REG_BASE +0x537a4*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x537a5*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x537a6*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537a7*4+0x02000000,0xdd6); +reg_write( DDR_REG_BASE +0x537a8*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x537a9*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x537aa*4+0x02000000,0xe62e); +reg_write( DDR_REG_BASE +0x537ab*4+0x02000000,0xed18); +reg_write( DDR_REG_BASE +0x537ac*4+0x02000000,0xf836); +reg_write( DDR_REG_BASE +0x537ad*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x537ae*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537af*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x537b0*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x537b1*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537b2*4+0x02000000,0xb72); +reg_write( DDR_REG_BASE +0x537b3*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x537b4*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x537b5*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537b6*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x537b7*4+0x02000000,0xd90c); +reg_write( DDR_REG_BASE +0x537b8*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x537b9*4+0x02000000,0xdb0a); +reg_write( DDR_REG_BASE +0x537ba*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x537bb*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537bc*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x537bd*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x537be*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537bf*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x537c0*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537c1*4+0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x537c2*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x537c3*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x537c4*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x537c5*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x537c6*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537c7*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x537c8*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537c9*4+0x02000000,0xf828); +reg_write( DDR_REG_BASE +0x537ca*4+0x02000000,0xb42); +reg_write( DDR_REG_BASE +0x537cb*4+0x02000000,0xfccf); +reg_write( DDR_REG_BASE +0x537cc*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x537cd*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x537ce*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x537cf*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x537d0*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x537d1*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537d2*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x537d3*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x537d4*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537d5*4+0x02000000,0xb2e); +reg_write( DDR_REG_BASE +0x537d6*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x537d7*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x537d8*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537d9*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x537da*4+0x02000000,0x7bcf); +reg_write( DDR_REG_BASE +0x537db*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x537dc*4+0x02000000,0xd90c); +reg_write( DDR_REG_BASE +0x537dd*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x537de*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x537df*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x537e0*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x537e1*4+0x02000000,0xb16); +reg_write( DDR_REG_BASE +0x537e2*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x537e3*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x537e4*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x537e5*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x537e6*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x537e7*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x537e8*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x537e9*4+0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x537ea*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x537eb*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x537ec*4+0x02000000,0xafe); +reg_write( DDR_REG_BASE +0x537ed*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x537ee*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x537ef*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x537f0*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x537f1*4+0x02000000,0xb98f); +reg_write( DDR_REG_BASE +0x537f2*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x537f3*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x537f4*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x537f5*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x537f6*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x537f7*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x537f8*4+0x02000000,0xae6); +reg_write( DDR_REG_BASE +0x537f9*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x537fa*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x537fb*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x537fc*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x537fd*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x537fe*4+0x02000000,0xdb10); +reg_write( DDR_REG_BASE +0x537ff*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x53800*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x53801*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53802*4+0x02000000,0xad2); +reg_write( DDR_REG_BASE +0x53803*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53804*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53805*4+0x02000000,0xcfe); +reg_write( DDR_REG_BASE +0x53806*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53807*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53808*4+0x02000000,0xbfc1); +reg_write( DDR_REG_BASE +0x53809*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5380a*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x5380b*4+0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x5380c*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x5380d*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5380e*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5380f*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53810*4+0x02000000,0xab6); +reg_write( DDR_REG_BASE +0x53811*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53812*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x53813*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x53814*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x53815*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x53816*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x53817*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53818*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53819*4+0x02000000,0xd90c); +reg_write( DDR_REG_BASE +0x5381a*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x5381b*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x5381c*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5381d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5381e*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5381f*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53820*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53821*4+0x02000000,0xc1a8); +reg_write( DDR_REG_BASE +0x53822*4+0x02000000,0xc145); +reg_write( DDR_REG_BASE +0x53823*4+0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x53824*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53825*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x53826*4+0x02000000,0xc346); +reg_write( DDR_REG_BASE +0x53827*4+0x02000000,0x9b2); +reg_write( DDR_REG_BASE +0x53828*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53829*4+0x02000000,0xc244); +reg_write( DDR_REG_BASE +0x5382a*4+0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x5382b*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x5382c*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x5382d*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x5382e*4+0x02000000,0xf03a); +reg_write( DDR_REG_BASE +0x5382f*4+0x02000000,0x2532); +reg_write( DDR_REG_BASE +0x53830*4+0x02000000,0x1f8f); +reg_write( DDR_REG_BASE +0x53831*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53832*4+0x02000000,0x624); +reg_write( DDR_REG_BASE +0x53833*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53834*4+0x02000000,0x896); +reg_write( DDR_REG_BASE +0x53835*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53836*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x53837*4+0x02000000,0xc207); +reg_write( DDR_REG_BASE +0x53838*4+0x02000000,0x7944); +reg_write( DDR_REG_BASE +0x53839*4+0x02000000,0xc206); +reg_write( DDR_REG_BASE +0x5383a*4+0x02000000,0x7844); +reg_write( DDR_REG_BASE +0x5383b*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5383c*4+0x02000000,0x807e); +reg_write( DDR_REG_BASE +0x5383d*4+0x02000000,0xf42b); +reg_write( DDR_REG_BASE +0x5383e*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5383f*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53840*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x53841*4+0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x53842*4+0x02000000,0x60e8); +reg_write( DDR_REG_BASE +0x53843*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x53844*4+0x02000000,0x3001); +reg_write( DDR_REG_BASE +0x53845*4+0x02000000,0x1c08); +reg_write( DDR_REG_BASE +0x53846*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x53847*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x53848*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53849*4+0x02000000,0xc56); +reg_write( DDR_REG_BASE +0x5384a*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x5384b*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x5384c*4+0x02000000,0xd07); +reg_write( DDR_REG_BASE +0x5384d*4+0x02000000,0x1190); +reg_write( DDR_REG_BASE +0x5384e*4+0x02000000,0xed99); +reg_write( DDR_REG_BASE +0x5384f*4+0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x53850*4+0x02000000,0xd9c8); +reg_write( DDR_REG_BASE +0x53851*4+0x02000000,0xd8fa); +reg_write( DDR_REG_BASE +0x53852*4+0x02000000,0xa5e); +reg_write( DDR_REG_BASE +0x53853*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x53854*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x53855*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x53856*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x53857*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x53858*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x53859*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5385a*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5385b*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x5385c*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5385d*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5385e*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5385f*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x53860*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x53861*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53862*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53863*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53864*4+0x02000000,0xc1e); +reg_write( DDR_REG_BASE +0x53865*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53866*4+0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x53867*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x53868*4+0x02000000,0xd8f); +reg_write( DDR_REG_BASE +0x53869*4+0x02000000,0x9334); +reg_write( DDR_REG_BASE +0x5386a*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5386b*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5386c*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5386d*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5386e*4+0x02000000,0xdb41); +reg_write( DDR_REG_BASE +0x5386f*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x53870*4+0x02000000,0x3401); +reg_write( DDR_REG_BASE +0x53871*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x53872*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x53873*4+0x02000000,0x9f2); +reg_write( DDR_REG_BASE +0x53874*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53875*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x53876*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53877*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x53878*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53879*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x5387a*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x5387b*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x5387c*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x5387d*4+0x02000000,0x9de); +reg_write( DDR_REG_BASE +0x5387e*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x5387f*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x53880*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53881*4+0x02000000,0x996); +reg_write( DDR_REG_BASE +0x53882*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53883*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53884*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53885*4+0x02000000,0xe833); +reg_write( DDR_REG_BASE +0x53886*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53887*4+0x02000000,0x8f2); +reg_write( DDR_REG_BASE +0x53888*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53889*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x5388a*4+0x02000000,0xd84f); +reg_write( DDR_REG_BASE +0x5388b*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x5388c*4+0x02000000,0x2353); +reg_write( DDR_REG_BASE +0x5388d*4+0x02000000,0x305b); +reg_write( DDR_REG_BASE +0x5388e*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5388f*4+0x02000000,0xf817); +reg_write( DDR_REG_BASE +0x53890*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x53891*4+0x02000000,0x1c08); +reg_write( DDR_REG_BASE +0x53892*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x53893*4+0x02000000,0x9b2); +reg_write( DDR_REG_BASE +0x53894*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53895*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53896*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53897*4+0x02000000,0x96a); +reg_write( DDR_REG_BASE +0x53898*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53899*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5389a*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5389b*4+0x02000000,0xf); +reg_write( DDR_REG_BASE +0x5389c*4+0x02000000,0x4240); +reg_write( DDR_REG_BASE +0x5389d*4+0x02000000,0xfa6); +reg_write( DDR_REG_BASE +0x5389e*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5389f*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x538a0*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x538a1*4+0x02000000,0x8be); +reg_write( DDR_REG_BASE +0x538a2*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x538a3*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x538a4*4+0x02000000,0xd851); +reg_write( DDR_REG_BASE +0x538a5*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x538a6*4+0x02000000,0xf80b); +reg_write( DDR_REG_BASE +0x538a7*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x538a8*4+0x02000000,0x1c08); +reg_write( DDR_REG_BASE +0x538a9*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x538aa*4+0x02000000,0x982); +reg_write( DDR_REG_BASE +0x538ab*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x538ac*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x538ad*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x538ae*4+0x02000000,0x93a); +reg_write( DDR_REG_BASE +0x538af*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x538b0*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x538b1*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x538b2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538b3*4+0x02000000,0x1f40); +reg_write( DDR_REG_BASE +0x538b4*4+0x02000000,0xf76); +reg_write( DDR_REG_BASE +0x538b5*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x538b6*4+0x02000000,0xd91e); +reg_write( DDR_REG_BASE +0x538b7*4+0x02000000,0xc0a8); +reg_write( DDR_REG_BASE +0x538b8*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x538b9*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x538ba*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x538bb*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x538bc*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x538bd*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x538be*4+0x02000000,0xda17); +reg_write( DDR_REG_BASE +0x538bf*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x538c0*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x538c1*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x538c2*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x538c3*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x538c4*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x538c5*4+0x02000000,0xc1ac); +reg_write( DDR_REG_BASE +0x538c6*4+0x02000000,0xc349); +reg_write( DDR_REG_BASE +0x538c7*4+0x02000000,0xc247); +reg_write( DDR_REG_BASE +0x538c8*4+0x02000000,0xc14a); +reg_write( DDR_REG_BASE +0x538c9*4+0x02000000,0xc5e); +reg_write( DDR_REG_BASE +0x538ca*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x538cb*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x538cc*4+0x02000000,0xc011); +reg_write( DDR_REG_BASE +0x538cd*4+0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x538ce*4+0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x538cf*4+0x02000000,0xc012); +reg_write( DDR_REG_BASE +0x538d0*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x538d1*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x538d2*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x538d3*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x538d4*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x538d5*4+0x02000000,0xf0b8); +reg_write( DDR_REG_BASE +0x538d6*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x538d7*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x538d8*4+0x02000000,0xf9b); +reg_write( DDR_REG_BASE +0x538d9*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x538da*4+0x02000000,0x624); +reg_write( DDR_REG_BASE +0x538db*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x538dc*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x538dd*4+0x02000000,0x6ce); +reg_write( DDR_REG_BASE +0x538de*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x538df*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x538e0*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x538e1*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x538e2*4+0x02000000,0xf40b); +reg_write( DDR_REG_BASE +0x538e3*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x538e4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538e5*4+0x02000000,0xa00); +reg_write( DDR_REG_BASE +0x538e6*4+0x02000000,0x832); +reg_write( DDR_REG_BASE +0x538e7*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x538e8*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x538e9*4+0x02000000,0x852); +reg_write( DDR_REG_BASE +0x538ea*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x538eb*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x538ec*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x538ed*4+0x02000000,0x41e1); +reg_write( DDR_REG_BASE +0x538ee*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x538ef*4+0x02000000,0x37c0); +reg_write( DDR_REG_BASE +0x538f0*4+0x02000000,0xc209); +reg_write( DDR_REG_BASE +0x538f1*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x538f2*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x538f3*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x538f4*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x538f5*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x538f6*4+0x02000000,0xd81f); +reg_write( DDR_REG_BASE +0x538f7*4+0x02000000,0x7a24); +reg_write( DDR_REG_BASE +0x538f8*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x538f9*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x538fa*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x538fb*4+0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x538fc*4+0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x538fd*4+0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x538fe*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x538ff*4+0x02000000,0x803e); +reg_write( DDR_REG_BASE +0x53900*4+0x02000000,0xf479); +reg_write( DDR_REG_BASE +0x53901*4+0x02000000,0x78dd); +reg_write( DDR_REG_BASE +0x53902*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x53903*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x53904*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x53905*4+0x02000000,0x2045); +reg_write( DDR_REG_BASE +0x53906*4+0x02000000,0x18d); +reg_write( DDR_REG_BASE +0x53907*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x53908*4+0x02000000,0xe80b); +reg_write( DDR_REG_BASE +0x53909*4+0x02000000,0xf87e); +reg_write( DDR_REG_BASE +0x5390a*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5390b*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5390c*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5390d*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5390e*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5390f*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53910*4+0x02000000,0x8b6); +reg_write( DDR_REG_BASE +0x53911*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53912*4+0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x53913*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53914*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53915*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53916*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x53917*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53918*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53919*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5391a*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x5391b*4+0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x5391c*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5391d*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x5391e*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5391f*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53920*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53921*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53922*4+0x02000000,0x892); +reg_write( DDR_REG_BASE +0x53923*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53924*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53925*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53926*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53927*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x53928*4+0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x53929*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x5392a*4+0x02000000,0x2353); +reg_write( DDR_REG_BASE +0x5392b*4+0x02000000,0x315b); +reg_write( DDR_REG_BASE +0x5392c*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5392d*4+0x02000000,0xf869); +reg_write( DDR_REG_BASE +0x5392e*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5392f*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53930*4+0x02000000,0x876); +reg_write( DDR_REG_BASE +0x53931*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53932*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x53933*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x53934*4+0x02000000,0xf868); +reg_write( DDR_REG_BASE +0x53935*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x53936*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53937*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x53938*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53939*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5393a*4+0x02000000,0x78dd); +reg_write( DDR_REG_BASE +0x5393b*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x5393c*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x5393d*4+0x02000000,0x2045); +reg_write( DDR_REG_BASE +0x5393e*4+0x02000000,0x580); +reg_write( DDR_REG_BASE +0x5393f*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x53940*4+0x02000000,0x856); +reg_write( DDR_REG_BASE +0x53941*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53942*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53943*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53944*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53945*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x53946*4+0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x53947*4+0x02000000,0xbec5); +reg_write( DDR_REG_BASE +0x53948*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53949*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5394a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5394b*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5394c*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5394d*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5394e*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x5394f*4+0x02000000,0x83a); +reg_write( DDR_REG_BASE +0x53950*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53951*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x53952*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53953*4+0x02000000,0xe819); +reg_write( DDR_REG_BASE +0x53954*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53955*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53956*4+0x02000000,0x2710); +reg_write( DDR_REG_BASE +0x53957*4+0x02000000,0xe52); +reg_write( DDR_REG_BASE +0x53958*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x53959*4+0x02000000,0xd90a); +reg_write( DDR_REG_BASE +0x5395a*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5395b*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5395c*4+0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x5395d*4+0x02000000,0x7e0f); +reg_write( DDR_REG_BASE +0x5395e*4+0x02000000,0xf850); +reg_write( DDR_REG_BASE +0x5395f*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x53960*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53961*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53962*4+0x02000000,0x812); +reg_write( DDR_REG_BASE +0x53963*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53964*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x53965*4+0x02000000,0xf84d); +reg_write( DDR_REG_BASE +0x53966*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x53967*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x53968*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53969*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5396a*4+0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x5396b*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5396c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5396d*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x5396e*4+0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x5396f*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x53970*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53971*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x53972*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53973*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53974*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53975*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53976*4+0x02000000,0xdb18); +reg_write( DDR_REG_BASE +0x53977*4+0x02000000,0xfea); +reg_write( DDR_REG_BASE +0x53978*4+0x02000000,0xfc8f); +reg_write( DDR_REG_BASE +0x53979*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5397a*4+0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x5397b*4+0x02000000,0x90f); +reg_write( DDR_REG_BASE +0x5397c*4+0x02000000,0x110); +reg_write( DDR_REG_BASE +0x5397d*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5397e*4+0x02000000,0x817); +reg_write( DDR_REG_BASE +0x5397f*4+0x02000000,0x2d1); +reg_write( DDR_REG_BASE +0x53980*4+0x02000000,0xe909); +reg_write( DDR_REG_BASE +0x53981*4+0x02000000,0xeca); +reg_write( DDR_REG_BASE +0x53982*4+0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x53983*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53984*4+0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x53985*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53986*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53987*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53988*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53989*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5398a*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5398b*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x5398c*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5398d*4+0x02000000,0xe08c); +reg_write( DDR_REG_BASE +0x5398e*4+0x02000000,0x690); +reg_write( DDR_REG_BASE +0x5398f*4+0x02000000,0xffc5); +reg_write( DDR_REG_BASE +0x53990*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x53991*4+0x02000000,0x8cf); +reg_write( DDR_REG_BASE +0x53992*4+0x02000000,0x30); +reg_write( DDR_REG_BASE +0x53993*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x53994*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x53995*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53996*4+0x02000000,0xa00); +reg_write( DDR_REG_BASE +0x53997*4+0x02000000,0xed2); +reg_write( DDR_REG_BASE +0x53998*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53999*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x5399a*4+0x02000000,0xeee); +reg_write( DDR_REG_BASE +0x5399b*4+0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x5399c*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x5399d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5399e*4+0x02000000,0x6e1); +reg_write( DDR_REG_BASE +0x5399f*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x539a0*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x539a1*4+0x02000000,0x234a); +reg_write( DDR_REG_BASE +0x539a2*4+0x02000000,0x3800); +reg_write( DDR_REG_BASE +0x539a3*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x539a4*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x539a5*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x539a6*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x539a7*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x539a8*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x539a9*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x539aa*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x539ab*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x539ac*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x539ad*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x539ae*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x539af*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x539b0*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x539b1*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x539b2*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x539b3*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x539b4*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x539b5*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x539b6*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x539b7*4+0x02000000,0xf6a); +reg_write( DDR_REG_BASE +0x539b8*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x539b9*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x539ba*4+0x02000000,0x33c1); +reg_write( DDR_REG_BASE +0x539bb*4+0x02000000,0xe56); +reg_write( DDR_REG_BASE +0x539bc*4+0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x539bd*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x539be*4+0x02000000,0xf1a); +reg_write( DDR_REG_BASE +0x539bf*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x539c0*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x539c1*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x539c2*4+0x02000000,0xf); +reg_write( DDR_REG_BASE +0x539c3*4+0x02000000,0x4240); +reg_write( DDR_REG_BASE +0x539c4*4+0x02000000,0xd56); +reg_write( DDR_REG_BASE +0x539c5*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x539c6*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x539c7*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x539c8*4+0x02000000,0xe6e); +reg_write( DDR_REG_BASE +0x539c9*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x539ca*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x539cb*4+0x02000000,0xe8e); +reg_write( DDR_REG_BASE +0x539cc*4+0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x539cd*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x539ce*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x539cf*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x539d0*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x539d1*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x539d2*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x539d3*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x539d4*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x539d5*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x539d6*4+0x02000000,0xf2a); +reg_write( DDR_REG_BASE +0x539d7*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x539d8*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x539d9*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x539da*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x539db*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x539dc*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x539dd*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x539de*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x539df*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x539e0*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x539e1*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x539e2*4+0x02000000,0xf12); +reg_write( DDR_REG_BASE +0x539e3*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x539e4*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x539e5*4+0x02000000,0x3441); +reg_write( DDR_REG_BASE +0x539e6*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x539e7*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x539e8*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x539e9*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x539ea*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x539eb*4+0x02000000,0xdb10); +reg_write( DDR_REG_BASE +0x539ec*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x539ed*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x539ee*4+0x02000000,0xefa); +reg_write( DDR_REG_BASE +0x539ef*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x539f0*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x539f1*4+0x02000000,0xdea); +reg_write( DDR_REG_BASE +0x539f2*4+0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x539f3*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x539f4*4+0x02000000,0xeae); +reg_write( DDR_REG_BASE +0x539f5*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x539f6*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x539f7*4+0x02000000,0xc06); +reg_write( DDR_REG_BASE +0x539f8*4+0x02000000,0xfd0f); +reg_write( DDR_REG_BASE +0x539f9*4+0x02000000,0xc0ac); +reg_write( DDR_REG_BASE +0x539fa*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x539fb*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x539fc*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x539fd*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x539fe*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x539ff*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53a00*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53a01*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x53a02*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x53a03*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x53a04*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53a05*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53a06*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x53a07*4+0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x53a08*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53a09*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53a0a*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x53a0b*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x53a0c*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x53a0d*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53a0e*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53a0f*4+0x02000000,0xc1a9); +reg_write( DDR_REG_BASE +0x53a10*4+0x02000000,0xc145); +reg_write( DDR_REG_BASE +0x53a11*4+0x02000000,0xd958); +reg_write( DDR_REG_BASE +0x53a12*4+0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x53a13*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x53a14*4+0x02000000,0x8900); +reg_write( DDR_REG_BASE +0x53a15*4+0x02000000,0x11cd); +reg_write( DDR_REG_BASE +0x53a16*4+0x02000000,0x808f); +reg_write( DDR_REG_BASE +0x53a17*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x53a18*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x53a19*4+0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x53a1a*4+0x02000000,0x71cd); +reg_write( DDR_REG_BASE +0x53a1b*4+0x02000000,0xc343); +reg_write( DDR_REG_BASE +0x53a1c*4+0x02000000,0xc244); +reg_write( DDR_REG_BASE +0x53a1d*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x53a1e*4+0x02000000,0xf058); +reg_write( DDR_REG_BASE +0x53a1f*4+0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x53a20*4+0x02000000,0x17c1); +reg_write( DDR_REG_BASE +0x53a21*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x53a22*4+0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x53a23*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x53a24*4+0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x53a25*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x53a26*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53a27*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53a28*4+0x02000000,0xf04b); +reg_write( DDR_REG_BASE +0x53a29*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x53a2a*4+0x02000000,0xc202); +reg_write( DDR_REG_BASE +0x53a2b*4+0x02000000,0xc108); +reg_write( DDR_REG_BASE +0x53a2c*4+0x02000000,0x7077); +reg_write( DDR_REG_BASE +0x53a2d*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x53a2e*4+0x02000000,0x3c1); +reg_write( DDR_REG_BASE +0x53a2f*4+0x02000000,0x7944); +reg_write( DDR_REG_BASE +0x53a30*4+0x02000000,0x790b); +reg_write( DDR_REG_BASE +0x53a31*4+0x02000000,0xf242); +reg_write( DDR_REG_BASE +0x53a32*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x53a33*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x53a34*4+0x02000000,0x37c1); +reg_write( DDR_REG_BASE +0x53a35*4+0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x53a36*4+0x02000000,0x3007); +reg_write( DDR_REG_BASE +0x53a37*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53a38*4+0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x53a39*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x53a3a*4+0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x53a3b*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x53a3c*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53a3d*4+0x02000000,0xe9e); +reg_write( DDR_REG_BASE +0x53a3e*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53a3f*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x53a40*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53a41*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53a42*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x53a43*4+0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x53a44*4+0x02000000,0xe81c); +reg_write( DDR_REG_BASE +0x53a45*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53a46*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53a47*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53a48*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53a49*4+0x02000000,0x831); +reg_write( DDR_REG_BASE +0x53a4a*4+0x02000000,0xdf); +reg_write( DDR_REG_BASE +0x53a4b*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x53a4c*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x53a4d*4+0x02000000,0x3c81); +reg_write( DDR_REG_BASE +0x53a4e*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x53a4f*4+0x02000000,0x3102); +reg_write( DDR_REG_BASE +0x53a50*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x53a51*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53a52*4+0x02000000,0xc304); +reg_write( DDR_REG_BASE +0x53a53*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x53a54*4+0x02000000,0x3001); +reg_write( DDR_REG_BASE +0x53a55*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x53a56*4+0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x53a57*4+0x02000000,0x1640); +reg_write( DDR_REG_BASE +0x53a58*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x53a59*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x53a5a*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x53a5b*4+0x02000000,0xc205); +reg_write( DDR_REG_BASE +0x53a5c*4+0x02000000,0xcce); +reg_write( DDR_REG_BASE +0x53a5d*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x53a5e*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x53a5f*4+0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x53a60*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x53a61*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x53a62*4+0x02000000,0x3c81); +reg_write( DDR_REG_BASE +0x53a63*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x53a64*4+0x02000000,0x3102); +reg_write( DDR_REG_BASE +0x53a65*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x53a66*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53a67*4+0x02000000,0xc304); +reg_write( DDR_REG_BASE +0x53a68*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x53a69*4+0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x53a6a*4+0x02000000,0x1640); +reg_write( DDR_REG_BASE +0x53a6b*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x53a6c*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x53a6d*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x53a6e*4+0x02000000,0xc205); +reg_write( DDR_REG_BASE +0x53a6f*4+0x02000000,0xb62); +reg_write( DDR_REG_BASE +0x53a70*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x53a71*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x53a72*4+0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x53a73*4+0x02000000,0xb6f); +reg_write( DDR_REG_BASE +0x53a74*4+0x02000000,0xb094); +reg_write( DDR_REG_BASE +0x53a75*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x53a76*4+0x02000000,0xd53); +reg_write( DDR_REG_BASE +0x53a77*4+0x02000000,0x90b4); +reg_write( DDR_REG_BASE +0x53a78*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53a79*4+0x02000000,0xe26); +reg_write( DDR_REG_BASE +0x53a7a*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53a7b*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x53a7c*4+0x02000000,0xc0a9); +reg_write( DDR_REG_BASE +0x53a7d*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x53a7e*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x53a7f*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53a80*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x53a81*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x53a82*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53a83*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53a84*4+0x02000000,0x8b80); +reg_write( DDR_REG_BASE +0x53a85*4+0x02000000,0x8ba1); +reg_write( DDR_REG_BASE +0x53a86*4+0x02000000,0x245f); +reg_write( DDR_REG_BASE +0x53a87*4+0x02000000,0x1482); +reg_write( DDR_REG_BASE +0x53a88*4+0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x53a89*4+0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x53a8a*4+0x02000000,0x921); +reg_write( DDR_REG_BASE +0x53a8b*4+0x02000000,0xee); +reg_write( DDR_REG_BASE +0x53a8c*4+0x02000000,0x4260); +reg_write( DDR_REG_BASE +0x53a8d*4+0x02000000,0x229a); +reg_write( DDR_REG_BASE +0x53a8e*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x53a8f*4+0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x53a90*4+0x02000000,0x1f8f); +reg_write( DDR_REG_BASE +0x53a91*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a92*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x53a93*4+0x02000000,0x7ae5); +reg_write( DDR_REG_BASE +0x53a94*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x53a95*4+0x02000000,0xf8f); +reg_write( DDR_REG_BASE +0x53a96*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x53a97*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x53a98*4+0x02000000,0x9040); +reg_write( DDR_REG_BASE +0x53a99*4+0x02000000,0xb740); +reg_write( DDR_REG_BASE +0x53a9a*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x53a9b*4+0x02000000,0x7204); +reg_write( DDR_REG_BASE +0x53a9c*4+0x02000000,0xbdd); +reg_write( DDR_REG_BASE +0x53a9d*4+0x02000000,0x8254); +reg_write( DDR_REG_BASE +0x53a9e*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x53a9f*4+0x02000000,0x7e8f); +reg_write( DDR_REG_BASE +0x53aa0*4+0x02000000,0xdf9); +reg_write( DDR_REG_BASE +0x53aa1*4+0x02000000,0x93a5); +reg_write( DDR_REG_BASE +0x53aa2*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x53aa3*4+0x02000000,0xc7e); +reg_write( DDR_REG_BASE +0x53aa4*4+0x02000000,0xfe4f); +reg_write( DDR_REG_BASE +0x53aa5*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53aa6*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x53aa7*4+0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x53aa8*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53aa9*4+0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x53aaa*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53aab*4+0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x53aac*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x53aad*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x53aae*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x53aaf*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53ab0*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x53ab1*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53ab2*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53ab3*4+0x02000000,0x7b45); +reg_write( DDR_REG_BASE +0x53ab4*4+0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x53ab5*4+0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x53ab6*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x53ab7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ab8*4+0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x53ab9*4+0x02000000,0x1301); +reg_write( DDR_REG_BASE +0x53aba*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x53abb*4+0x02000000,0x6c02); +reg_write( DDR_REG_BASE +0x53abc*4+0x02000000,0x78a5); +reg_write( DDR_REG_BASE +0x53abd*4+0x02000000,0xb060); +reg_write( DDR_REG_BASE +0x53abe*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53abf*4+0x02000000,0xd1a); +reg_write( DDR_REG_BASE +0x53ac0*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53ac1*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53ac2*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x53ac3*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x53ac4*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x53ac5*4+0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x53ac6*4+0x02000000,0x3040); +reg_write( DDR_REG_BASE +0x53ac7*4+0x02000000,0x4308); +reg_write( DDR_REG_BASE +0x53ac8*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x53ac9*4+0x02000000,0xf024); +reg_write( DDR_REG_BASE +0x53aca*4+0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x53acb*4+0x02000000,0x1182); +reg_write( DDR_REG_BASE +0x53acc*4+0x02000000,0x7261); +reg_write( DDR_REG_BASE +0x53acd*4+0x02000000,0x8a01); +reg_write( DDR_REG_BASE +0x53ace*4+0x02000000,0x8a60); +reg_write( DDR_REG_BASE +0x53acf*4+0x02000000,0x8a22); +reg_write( DDR_REG_BASE +0x53ad0*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x53ad1*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53ad2*4+0x02000000,0x7b05); +reg_write( DDR_REG_BASE +0x53ad3*4+0x02000000,0x8a03); +reg_write( DDR_REG_BASE +0x53ad4*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x53ad5*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53ad6*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x53ad7*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x53ad8*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53ad9*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53ada*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53adb*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53adc*4+0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x53add*4+0x02000000,0x8a05); +reg_write( DDR_REG_BASE +0x53ade*4+0x02000000,0x8a64); +reg_write( DDR_REG_BASE +0x53adf*4+0x02000000,0x7734); +reg_write( DDR_REG_BASE +0x53ae0*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x53ae1*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53ae2*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x53ae3*4+0x02000000,0xf207); +reg_write( DDR_REG_BASE +0x53ae4*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x53ae5*4+0x02000000,0xb99c); +reg_write( DDR_REG_BASE +0x53ae6*4+0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x53ae7*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x53ae8*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x53ae9*4+0x02000000,0xab6); +reg_write( DDR_REG_BASE +0x53aea*4+0x02000000,0xfe0f); +reg_write( DDR_REG_BASE +0x53aeb*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x53aec*4+0x02000000,0x2e45); +reg_write( DDR_REG_BASE +0x53aed*4+0x02000000,0x3180); +reg_write( DDR_REG_BASE +0x53aee*4+0x02000000,0xdb9); +reg_write( DDR_REG_BASE +0x53aef*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x53af0*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x53af1*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x53af2*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x53af3*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53af4*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53af5*4+0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x53af6*4+0x02000000,0x4718); +reg_write( DDR_REG_BASE +0x53af7*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53af8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53af9*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53afa*4+0x02000000,0x88c0); +reg_write( DDR_REG_BASE +0x53afb*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x53afc*4+0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x53afd*4+0x02000000,0xea04); +reg_write( DDR_REG_BASE +0x53afe*4+0x02000000,0x79db); +reg_write( DDR_REG_BASE +0x53aff*4+0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x53b00*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x53b01*4+0x02000000,0x1241); +reg_write( DDR_REG_BASE +0x53b02*4+0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x53b03*4+0x02000000,0x9e); +reg_write( DDR_REG_BASE +0x53b04*4+0x02000000,0x7054); +reg_write( DDR_REG_BASE +0x53b05*4+0x02000000,0xdd08); +reg_write( DDR_REG_BASE +0x53b06*4+0x02000000,0x25ca); +reg_write( DDR_REG_BASE +0x53b07*4+0x02000000,0x1062); +reg_write( DDR_REG_BASE +0x53b08*4+0x02000000,0xf039); +reg_write( DDR_REG_BASE +0x53b09*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x53b0a*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x53b0b*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53b0c*4+0x02000000,0xc300); +reg_write( DDR_REG_BASE +0x53b0d*4+0x02000000,0x23f5); +reg_write( DDR_REG_BASE +0x53b0e*4+0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x53b0f*4+0x02000000,0xeb13); +reg_write( DDR_REG_BASE +0x53b10*4+0x02000000,0x7c5c); +reg_write( DDR_REG_BASE +0x53b11*4+0x02000000,0x7c9c); +reg_write( DDR_REG_BASE +0x53b12*4+0x02000000,0x7c9c); +reg_write( DDR_REG_BASE +0x53b13*4+0x02000000,0x7c9c); +reg_write( DDR_REG_BASE +0x53b14*4+0x02000000,0x224a); +reg_write( DDR_REG_BASE +0x53b15*4+0x02000000,0x16c0); +reg_write( DDR_REG_BASE +0x53b16*4+0x02000000,0x2a44); +reg_write( DDR_REG_BASE +0x53b17*4+0x02000000,0x803); +reg_write( DDR_REG_BASE +0x53b18*4+0x02000000,0x2242); +reg_write( DDR_REG_BASE +0x53b19*4+0x02000000,0x104a); +reg_write( DDR_REG_BASE +0x53b1a*4+0x02000000,0xafd); +reg_write( DDR_REG_BASE +0x53b1b*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x53b1c*4+0x02000000,0x7c9d); +reg_write( DDR_REG_BASE +0x53b1d*4+0x02000000,0x629a); +reg_write( DDR_REG_BASE +0x53b1e*4+0x02000000,0xbac4); +reg_write( DDR_REG_BASE +0x53b1f*4+0x02000000,0x4a94); +reg_write( DDR_REG_BASE +0x53b20*4+0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x53b21*4+0x02000000,0x248a); +reg_write( DDR_REG_BASE +0x53b22*4+0x02000000,0x1fcf); +reg_write( DDR_REG_BASE +0x53b23*4+0x02000000,0x7c44); +reg_write( DDR_REG_BASE +0x53b24*4+0x02000000,0x2204); +reg_write( DDR_REG_BASE +0x53b25*4+0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x53b26*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b27*4+0x02000000,0xfc00); +reg_write( DDR_REG_BASE +0x53b28*4+0x02000000,0xda0a); +reg_write( DDR_REG_BASE +0x53b29*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x53b2a*4+0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x53b2b*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x53b2c*4+0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x53b2d*4+0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x53b2e*4+0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x53b2f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b30*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x53b31*4+0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x53b32*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53b33*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x53b34*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x53b35*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x53b36*4+0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x53b37*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x53b38*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53b39*4+0x02000000,0xb891); +reg_write( DDR_REG_BASE +0x53b3a*4+0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x53b3b*4+0x02000000,0x7b85); +reg_write( DDR_REG_BASE +0x53b3c*4+0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x53b3d*4+0x02000000,0xb060); +reg_write( DDR_REG_BASE +0x53b3e*4+0x02000000,0xd97); +reg_write( DDR_REG_BASE +0x53b3f*4+0x02000000,0x93c5); +reg_write( DDR_REG_BASE +0x53b40*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x53b41*4+0x02000000,0xefd); +reg_write( DDR_REG_BASE +0x53b42*4+0x02000000,0xb3a5); +reg_write( DDR_REG_BASE +0x53b43*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x53b44*4+0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x53b45*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x53b46*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x53b47*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53b48*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x53b49*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53b4a*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53b4b*4+0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x53b4c*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x53b4d*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53b4e*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53b4f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53b50*4+0x02000000,0x1b); +reg_write( DDR_REG_BASE +0x53b51*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x53b52*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x53b53*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x53b54*4+0x02000000,0x4568); +reg_write( DDR_REG_BASE +0x53b55*4+0x02000000,0x7dc0); +reg_write( DDR_REG_BASE +0x53b56*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x53b57*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53b58*4+0x02000000,0x688); +reg_write( DDR_REG_BASE +0x53b59*4+0x02000000,0x82f); +reg_write( DDR_REG_BASE +0x53b5a*4+0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x53b5b*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x53b5c*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53b5d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53b5e*4+0x02000000,0x7d3); +reg_write( DDR_REG_BASE +0x53b5f*4+0x02000000,0x8904); +reg_write( DDR_REG_BASE +0x53b60*4+0x02000000,0xe80f); +reg_write( DDR_REG_BASE +0x53b61*4+0x02000000,0x8900); +reg_write( DDR_REG_BASE +0x53b62*4+0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x53b63*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53b64*4+0x02000000,0x6ba); +reg_write( DDR_REG_BASE +0x53b65*4+0x02000000,0xaa00); +reg_write( DDR_REG_BASE +0x53b66*4+0x02000000,0x8901); +reg_write( DDR_REG_BASE +0x53b67*4+0x02000000,0xaa19); +reg_write( DDR_REG_BASE +0x53b68*4+0x02000000,0x8902); +reg_write( DDR_REG_BASE +0x53b69*4+0x02000000,0xac00); +reg_write( DDR_REG_BASE +0x53b6a*4+0x02000000,0x8903); +reg_write( DDR_REG_BASE +0x53b6b*4+0x02000000,0xac19); +reg_write( DDR_REG_BASE +0x53b6c*4+0x02000000,0x2350); +reg_write( DDR_REG_BASE +0x53b6d*4+0x02000000,0x300); +reg_write( DDR_REG_BASE +0x53b6e*4+0x02000000,0x7d04); +reg_write( DDR_REG_BASE +0x53b6f*4+0x02000000,0x2242); +reg_write( DDR_REG_BASE +0x53b70*4+0x02000000,0x30e); +reg_write( DDR_REG_BASE +0x53b71*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53b72*4+0x02000000,0xf06); +reg_write( DDR_REG_BASE +0x53b73*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x53b74*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x53b75*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53b76*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x53b77*4+0x02000000,0xcbe); +reg_write( DDR_REG_BASE +0x53b78*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x53b79*4+0x02000000,0xda40); +reg_write( DDR_REG_BASE +0x53b7a*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53b7b*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x53b7c*4+0x02000000,0xe8e); +reg_write( DDR_REG_BASE +0x53b7d*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53b7e*4+0x02000000,0xda7f); +reg_write( DDR_REG_BASE +0x53b7f*4+0x02000000,0xdfff); +reg_write( DDR_REG_BASE +0x53b80*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53b81*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53b82*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x53b83*4+0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x53b84*4+0x02000000,0xd12); +reg_write( DDR_REG_BASE +0x53b85*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x53b86*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53b87*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53b88*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x53b89*4+0x02000000,0xc9a); +reg_write( DDR_REG_BASE +0x53b8a*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x53b8b*4+0x02000000,0xda80); +reg_write( DDR_REG_BASE +0x53b8c*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53b8d*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53b8e*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x53b8f*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x53b90*4+0x02000000,0xdfff); +reg_write( DDR_REG_BASE +0x53b91*4+0x02000000,0x776c); +reg_write( DDR_REG_BASE +0x53b92*4+0x02000000,0xcf6); +reg_write( DDR_REG_BASE +0x53b93*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x53b94*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53b95*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53b96*4+0x02000000,0xabe); +reg_write( DDR_REG_BASE +0x53b97*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x53b98*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x53b99*4+0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x53b9a*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x53b9b*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x53b9c*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53b9d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x53b9e*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x53b9f*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53ba0*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53ba1*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x53ba2*4+0x02000000,0x3403); +reg_write( DDR_REG_BASE +0x53ba3*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53ba4*4+0x02000000,0xf22); +reg_write( DDR_REG_BASE +0x53ba5*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53ba6*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x53ba7*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53ba8*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53ba9*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53baa*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53bab*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53bac*4+0x02000000,0xc22); +reg_write( DDR_REG_BASE +0x53bad*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x53bae*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x53baf*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x53bb0*4+0x02000000,0xe0e); +reg_write( DDR_REG_BASE +0x53bb1*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53bb2*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x53bb3*4+0x02000000,0x3bc1); +reg_write( DDR_REG_BASE +0x53bb4*4+0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x53bb5*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x53bb6*4+0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x53bb7*4+0x02000000,0x17ce); +reg_write( DDR_REG_BASE +0x53bb8*4+0x02000000,0xee05); +reg_write( DDR_REG_BASE +0x53bb9*4+0x02000000,0xbe61); +reg_write( DDR_REG_BASE +0x53bba*4+0x02000000,0xeff); +reg_write( DDR_REG_BASE +0x53bbb*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x53bbc*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53bbd*4+0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x53bbe*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x53bbf*4+0x02000000,0x200f); +reg_write( DDR_REG_BASE +0x53bc0*4+0x02000000,0x340); +reg_write( DDR_REG_BASE +0x53bc1*4+0x02000000,0xd7e); +reg_write( DDR_REG_BASE +0x53bc2*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53bc3*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x53bc4*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53bc5*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53bc6*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53bc7*4+0x02000000,0xfe64); +reg_write( DDR_REG_BASE +0x53bc8*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53bc9*4+0x02000000,0x7044); +reg_write( DDR_REG_BASE +0x53bca*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53bcb*4+0x02000000,0xfe64); +reg_write( DDR_REG_BASE +0x53bcc*4+0x02000000,0x1882); +reg_write( DDR_REG_BASE +0x53bcd*4+0x02000000,0x5c); +reg_write( DDR_REG_BASE +0x53bce*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53bcf*4+0x02000000,0x808); +reg_write( DDR_REG_BASE +0x53bd0*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53bd1*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x53bd2*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53bd3*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x53bd4*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53bd5*4+0x02000000,0x73c4); +reg_write( DDR_REG_BASE +0x53bd6*4+0x02000000,0x900f); +reg_write( DDR_REG_BASE +0x53bd7*4+0x02000000,0xe0c0); +reg_write( DDR_REG_BASE +0x53bd8*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53bd9*4+0x02000000,0x7044); +reg_write( DDR_REG_BASE +0x53bda*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53bdb*4+0x02000000,0xfe64); +reg_write( DDR_REG_BASE +0x53bdc*4+0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x53bdd*4+0x02000000,0x6941); +reg_write( DDR_REG_BASE +0x53bde*4+0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x53bdf*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x53be0*4+0x02000000,0x43e1); +reg_write( DDR_REG_BASE +0x53be1*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x53be2*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x53be3*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x53be4*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x53be5*4+0x02000000,0x7b7b); +reg_write( DDR_REG_BASE +0x53be6*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x53be7*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53be8*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53be9*4+0x02000000,0xe0c4); +reg_write( DDR_REG_BASE +0x53bea*4+0x02000000,0xb060); +reg_write( DDR_REG_BASE +0x53beb*4+0x02000000,0x4140); +reg_write( DDR_REG_BASE +0x53bec*4+0x02000000,0x9e3); +reg_write( DDR_REG_BASE +0x53bed*4+0x02000000,0x8234); +reg_write( DDR_REG_BASE +0x53bee*4+0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x53bef*4+0x02000000,0x7c0); +reg_write( DDR_REG_BASE +0x53bf0*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x53bf1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bf2*4+0x02000000,0xaaaa); +reg_write( DDR_REG_BASE +0x53bf3*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53bf4*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x53bf5*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x53bf6*4+0x02000000,0x43a1); +reg_write( DDR_REG_BASE +0x53bf7*4+0x02000000,0x98e); +reg_write( DDR_REG_BASE +0x53bf8*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53bf9*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53bfa*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53bfb*4+0x02000000,0xe2a); +reg_write( DDR_REG_BASE +0x53bfc*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53bfd*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x53bfe*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53bff*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c00*4+0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x53c01*4+0x02000000,0xe82); +reg_write( DDR_REG_BASE +0x53c02*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x53c03*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53c04*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x53c05*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53c06*4+0x02000000,0xe174); +reg_write( DDR_REG_BASE +0x53c07*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53c08*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x53c09*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53c0a*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x53c0b*4+0x02000000,0xb601); +reg_write( DDR_REG_BASE +0x53c0c*4+0x02000000,0x43db); +reg_write( DDR_REG_BASE +0x53c0d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c0e*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x53c0f*4+0x02000000,0xd830); +reg_write( DDR_REG_BASE +0x53c10*4+0x02000000,0x1e58); +reg_write( DDR_REG_BASE +0x53c11*4+0x02000000,0x96dc); +reg_write( DDR_REG_BASE +0x53c12*4+0x02000000,0x1e5e); +reg_write( DDR_REG_BASE +0x53c13*4+0x02000000,0x93dc); +reg_write( DDR_REG_BASE +0x53c14*4+0x02000000,0xa6e); +reg_write( DDR_REG_BASE +0x53c15*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53c16*4+0x02000000,0x1e57); +reg_write( DDR_REG_BASE +0x53c17*4+0x02000000,0x93dc); +reg_write( DDR_REG_BASE +0x53c18*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53c19*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53c1a*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53c1b*4+0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x53c1c*4+0x02000000,0x942); +reg_write( DDR_REG_BASE +0x53c1d*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53c1e*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x53c1f*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x53c20*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x53c21*4+0x02000000,0xa56); +reg_write( DDR_REG_BASE +0x53c22*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53c23*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53c24*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53c25*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x53c26*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x53c27*4+0x02000000,0x43a1); +reg_write( DDR_REG_BASE +0x53c28*4+0x02000000,0x92a); +reg_write( DDR_REG_BASE +0x53c29*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53c2a*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53c2b*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53c2c*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x53c2d*4+0x02000000,0xb601); +reg_write( DDR_REG_BASE +0x53c2e*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x53c2f*4+0x02000000,0x1e58); +reg_write( DDR_REG_BASE +0x53c30*4+0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x53c31*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53c32*4+0x02000000,0x844); +reg_write( DDR_REG_BASE +0x53c33*4+0x02000000,0x1e5e); +reg_write( DDR_REG_BASE +0x53c34*4+0x02000000,0x93dc); +reg_write( DDR_REG_BASE +0x53c35*4+0x02000000,0x1e57); +reg_write( DDR_REG_BASE +0x53c36*4+0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x53c37*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53c38*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c39*4+0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x53c3a*4+0x02000000,0xe0e); +reg_write( DDR_REG_BASE +0x53c3b*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x53c3c*4+0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x53c3d*4+0x02000000,0xd830); +reg_write( DDR_REG_BASE +0x53c3e*4+0x02000000,0xa1a); +reg_write( DDR_REG_BASE +0x53c3f*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53c40*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53c41*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x53c42*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53c43*4+0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x53c44*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53c45*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53c46*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x53c47*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53c48*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x53c49*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c4a*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x53c4b*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53c4c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53c4d*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53c4e*4+0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x53c4f*4+0x02000000,0xf022); +reg_write( DDR_REG_BASE +0x53c50*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53c51*4+0x02000000,0x2016); +reg_write( DDR_REG_BASE +0x53c52*4+0x02000000,0x83); +reg_write( DDR_REG_BASE +0x53c53*4+0x02000000,0xf01a); +reg_write( DDR_REG_BASE +0x53c54*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x53c55*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x53c56*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x53c57*4+0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x53c58*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c59*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x53c5a*4+0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x53c5b*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53c5c*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53c5d*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x53c5e*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x53c5f*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x53c60*4+0x02000000,0x7c1d); +reg_write( DDR_REG_BASE +0x53c61*4+0x02000000,0x7c9d); +reg_write( DDR_REG_BASE +0x53c62*4+0x02000000,0x7c9d); +reg_write( DDR_REG_BASE +0x53c63*4+0x02000000,0x7c9d); +reg_write( DDR_REG_BASE +0x53c64*4+0x02000000,0x7c9d); +reg_write( DDR_REG_BASE +0x53c65*4+0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x53c66*4+0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x53c67*4+0x02000000,0xc087); +reg_write( DDR_REG_BASE +0x53c68*4+0x02000000,0x7874); +reg_write( DDR_REG_BASE +0x53c69*4+0x02000000,0xb080); +reg_write( DDR_REG_BASE +0x53c6a*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x53c6b*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x53c6c*4+0x02000000,0x8d1); +reg_write( DDR_REG_BASE +0x53c6d*4+0x02000000,0x8234); +reg_write( DDR_REG_BASE +0x53c6e*4+0x02000000,0x68e1); +reg_write( DDR_REG_BASE +0x53c6f*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x53c70*4+0x02000000,0x9c1); +reg_write( DDR_REG_BASE +0x53c71*4+0x02000000,0x80a5); +reg_write( DDR_REG_BASE +0x53c72*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53c73*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x53c74*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x53c75*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x53c76*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x53c77*4+0x02000000,0xb6e1); +reg_write( DDR_REG_BASE +0x53c78*4+0x02000000,0x1e58); +reg_write( DDR_REG_BASE +0x53c79*4+0x02000000,0x96dc); +reg_write( DDR_REG_BASE +0x53c7a*4+0x02000000,0x1e5e); +reg_write( DDR_REG_BASE +0x53c7b*4+0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x53c7c*4+0x02000000,0x1e57); +reg_write( DDR_REG_BASE +0x53c7d*4+0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x53c7e*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53c7f*4+0x02000000,0x7d0); +reg_write( DDR_REG_BASE +0x53c80*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53c81*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x53c82*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53c83*4+0x02000000,0xfe64); +reg_write( DDR_REG_BASE +0x53c84*4+0x02000000,0xd830); +reg_write( DDR_REG_BASE +0x53c85*4+0x02000000,0x98e); +reg_write( DDR_REG_BASE +0x53c86*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53c87*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53c88*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53c89*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53c8a*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53c8b*4+0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x53c8c*4+0x02000000,0x862); +reg_write( DDR_REG_BASE +0x53c8d*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53c8e*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x53c8f*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x53c90*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x53c91*4+0x02000000,0x976); +reg_write( DDR_REG_BASE +0x53c92*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53c93*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53c94*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53c95*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x53c96*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x53c97*4+0x02000000,0x43a1); +reg_write( DDR_REG_BASE +0x53c98*4+0x02000000,0x84a); +reg_write( DDR_REG_BASE +0x53c99*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53c9a*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53c9b*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53c9c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c9d*4+0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x53c9e*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53c9f*4+0x02000000,0xb6e0); +reg_write( DDR_REG_BASE +0x53ca0*4+0x02000000,0xd42); +reg_write( DDR_REG_BASE +0x53ca1*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x53ca2*4+0x02000000,0xb6e1); +reg_write( DDR_REG_BASE +0x53ca3*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x53ca4*4+0x02000000,0x1e58); +reg_write( DDR_REG_BASE +0x53ca5*4+0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x53ca6*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x53ca7*4+0x02000000,0x1e5e); +reg_write( DDR_REG_BASE +0x53ca8*4+0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x53ca9*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53caa*4+0x02000000,0x844); +reg_write( DDR_REG_BASE +0x53cab*4+0x02000000,0x1e57); +reg_write( DDR_REG_BASE +0x53cac*4+0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x53cad*4+0x02000000,0x93e); +reg_write( DDR_REG_BASE +0x53cae*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53caf*4+0x02000000,0xd830); +reg_write( DDR_REG_BASE +0x53cb0*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53cb1*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53cb2*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53cb3*4+0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x53cb4*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53cb5*4+0x02000000,0x708b); +reg_write( DDR_REG_BASE +0x53cb6*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53cb7*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53cb8*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x53cb9*4+0x02000000,0xf084); +reg_write( DDR_REG_BASE +0x53cba*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x53cbb*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x53cbc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cbd*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x53cbe*4+0x02000000,0x2716); +reg_write( DDR_REG_BASE +0x53cbf*4+0x02000000,0x12de); +reg_write( DDR_REG_BASE +0x53cc0*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53cc1*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53cc2*4+0x02000000,0xc104); +reg_write( DDR_REG_BASE +0x53cc3*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x53cc4*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x53cc5*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x53cc6*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x53cc7*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x53cc8*4+0x02000000,0xd01); +reg_write( DDR_REG_BASE +0x53cc9*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53cca*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x53ccb*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53ccc*4+0x02000000,0xb891); +reg_write( DDR_REG_BASE +0x53ccd*4+0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x53cce*4+0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x53ccf*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x53cd0*4+0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x53cd1*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x53cd2*4+0x02000000,0xf05d); +reg_write( DDR_REG_BASE +0x53cd3*4+0x02000000,0x4340); +reg_write( DDR_REG_BASE +0x53cd4*4+0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x53cd5*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53cd6*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53cd7*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x53cd8*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53cd9*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53cda*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53cdb*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x53cdc*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x53cdd*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x53cde*4+0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x53cdf*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x53ce0*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x53ce1*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x53ce2*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x53ce3*4+0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x53ce4*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x53ce5*4+0x02000000,0xc087); +reg_write( DDR_REG_BASE +0x53ce6*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x53ce7*4+0x02000000,0x79f); +reg_write( DDR_REG_BASE +0x53ce8*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x53ce9*4+0x02000000,0x3bc0); +reg_write( DDR_REG_BASE +0x53cea*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x53ceb*4+0x02000000,0x2cc); +reg_write( DDR_REG_BASE +0x53cec*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x53ced*4+0x02000000,0x71f3); +reg_write( DDR_REG_BASE +0x53cee*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x53cef*4+0x02000000,0x101b); +reg_write( DDR_REG_BASE +0x53cf0*4+0x02000000,0x27d4); +reg_write( DDR_REG_BASE +0x53cf1*4+0x02000000,0x3829); +reg_write( DDR_REG_BASE +0x53cf2*4+0x02000000,0x71e3); +reg_write( DDR_REG_BASE +0x53cf3*4+0x02000000,0x2340); +reg_write( DDR_REG_BASE +0x53cf4*4+0x02000000,0x340c); +reg_write( DDR_REG_BASE +0x53cf5*4+0x02000000,0x782e); +reg_write( DDR_REG_BASE +0x53cf6*4+0x02000000,0x791c); +reg_write( DDR_REG_BASE +0x53cf7*4+0x02000000,0x7c8e); +reg_write( DDR_REG_BASE +0x53cf8*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x53cf9*4+0x02000000,0x792e); +reg_write( DDR_REG_BASE +0x53cfa*4+0x02000000,0x4990); +reg_write( DDR_REG_BASE +0x53cfb*4+0x02000000,0x2154); +reg_write( DDR_REG_BASE +0x53cfc*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x53cfd*4+0x02000000,0x272f); +reg_write( DDR_REG_BASE +0x53cfe*4+0x02000000,0x3009); +reg_write( DDR_REG_BASE +0x53cff*4+0x02000000,0x4990); +reg_write( DDR_REG_BASE +0x53d00*4+0x02000000,0x7811); +reg_write( DDR_REG_BASE +0x53d01*4+0x02000000,0x8f1); +reg_write( DDR_REG_BASE +0x53d02*4+0x02000000,0x87c2); +reg_write( DDR_REG_BASE +0x53d03*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53d04*4+0x02000000,0x3f); +reg_write( DDR_REG_BASE +0x53d05*4+0x02000000,0x4891); +reg_write( DDR_REG_BASE +0x53d06*4+0x02000000,0x78ae); +reg_write( DDR_REG_BASE +0x53d07*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x53d08*4+0x02000000,0x272f); +reg_write( DDR_REG_BASE +0x53d09*4+0x02000000,0x3049); +reg_write( DDR_REG_BASE +0x53d0a*4+0x02000000,0x4891); +reg_write( DDR_REG_BASE +0x53d0b*4+0x02000000,0x7931); +reg_write( DDR_REG_BASE +0x53d0c*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x53d0d*4+0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x53d0e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d0f*4+0x02000000,0xffc0); +reg_write( DDR_REG_BASE +0x53d10*4+0x02000000,0xfe7); +reg_write( DDR_REG_BASE +0x53d11*4+0x02000000,0xb042); +reg_write( DDR_REG_BASE +0x53d12*4+0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x53d13*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53d14*4+0x02000000,0x783b); +reg_write( DDR_REG_BASE +0x53d15*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x53d16*4+0x02000000,0x7); +reg_write( DDR_REG_BASE +0x53d17*4+0x02000000,0xb9c4); +reg_write( DDR_REG_BASE +0x53d18*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x53d19*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x53d1a*4+0x02000000,0xc405); +reg_write( DDR_REG_BASE +0x53d1b*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x53d1c*4+0x02000000,0xc00); +reg_write( DDR_REG_BASE +0x53d1d*4+0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x53d1e*4+0x02000000,0x7b85); +reg_write( DDR_REG_BASE +0x53d1f*4+0x02000000,0x787b); +reg_write( DDR_REG_BASE +0x53d20*4+0x02000000,0xb891); +reg_write( DDR_REG_BASE +0x53d21*4+0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x53d22*4+0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x53d23*4+0x02000000,0xa15); +reg_write( DDR_REG_BASE +0x53d24*4+0x02000000,0x1f1); +reg_write( DDR_REG_BASE +0x53d25*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x53d26*4+0x02000000,0x789b); +reg_write( DDR_REG_BASE +0x53d27*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53d28*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53d29*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x53d2a*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x53d2b*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x53d2c*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x53d2d*4+0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x53d2e*4+0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x53d2f*4+0x02000000,0xa4b); +reg_write( DDR_REG_BASE +0x53d30*4+0x02000000,0x8214); +reg_write( DDR_REG_BASE +0x53d31*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x53d32*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x53d33*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d34*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x53d35*4+0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x53d36*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53d37*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x53d38*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x53d39*4+0x02000000,0x1e64); +reg_write( DDR_REG_BASE +0x53d3a*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x53d3b*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x53d3c*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53d3d*4+0x02000000,0x230c); +reg_write( DDR_REG_BASE +0x53d3e*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x53d3f*4+0x02000000,0x6f8); +reg_write( DDR_REG_BASE +0x53d40*4+0x02000000,0xffee); +reg_write( DDR_REG_BASE +0x53d41*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53d42*4+0x02000000,0x1e58); +reg_write( DDR_REG_BASE +0x53d43*4+0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x53d44*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53d45*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53d46*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d47*4+0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x53d48*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x53d49*4+0x02000000,0x1e5e); +reg_write( DDR_REG_BASE +0x53d4a*4+0x02000000,0x905c); +reg_write( DDR_REG_BASE +0x53d4b*4+0x02000000,0xbee); +reg_write( DDR_REG_BASE +0x53d4c*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x53d4d*4+0x02000000,0x1e57); +reg_write( DDR_REG_BASE +0x53d4e*4+0x02000000,0x905c); +reg_write( DDR_REG_BASE +0x53d4f*4+0x02000000,0xf26); +reg_write( DDR_REG_BASE +0x53d50*4+0x02000000,0xfe0f); +reg_write( DDR_REG_BASE +0x53d51*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53d52*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53d53*4+0x02000000,0xfe64); +reg_write( DDR_REG_BASE +0x53d54*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53d55*4+0x02000000,0x73c4); +reg_write( DDR_REG_BASE +0x53d56*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53d57*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x53d58*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53d59*4+0x02000000,0x7344); +reg_write( DDR_REG_BASE +0x53d5a*4+0x02000000,0x900f); +reg_write( DDR_REG_BASE +0x53d5b*4+0x02000000,0xe0c0); +reg_write( DDR_REG_BASE +0x53d5c*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53d5d*4+0x02000000,0x73c4); +reg_write( DDR_REG_BASE +0x53d5e*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53d5f*4+0x02000000,0xfec4); +reg_write( DDR_REG_BASE +0x53d60*4+0x02000000,0x1882); +reg_write( DDR_REG_BASE +0x53d61*4+0x02000000,0x3dc); +reg_write( DDR_REG_BASE +0x53d62*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53d63*4+0x02000000,0xb5a); +reg_write( DDR_REG_BASE +0x53d64*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53d65*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x53d66*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53d67*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d68*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x53d69*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53d6a*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53d6b*4+0x02000000,0x4320); +reg_write( DDR_REG_BASE +0x53d6c*4+0x02000000,0xea2); +reg_write( DDR_REG_BASE +0x53d6d*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53d6e*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53d6f*4+0x02000000,0xf03b); +reg_write( DDR_REG_BASE +0x53d70*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53d71*4+0x02000000,0xfb6); +reg_write( DDR_REG_BASE +0x53d72*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53d73*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53d74*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53d75*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53d76*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53d77*4+0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x53d78*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53d79*4+0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x53d7a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53d7b*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53d7c*4+0x02000000,0xf023); +reg_write( DDR_REG_BASE +0x53d7d*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x53d7e*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53d7f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d80*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x53d81*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53d82*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53d83*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x53d84*4+0x02000000,0x166); +reg_write( DDR_REG_BASE +0x53d85*4+0x02000000,0x9060); +reg_write( DDR_REG_BASE +0x53d86*4+0x02000000,0xeb17); +reg_write( DDR_REG_BASE +0x53d87*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x53d88*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x53d89*4+0x02000000,0xd0c); +reg_write( DDR_REG_BASE +0x53d8a*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x53d8b*4+0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x53d8c*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x53d8d*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53d8e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d8f*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x53d90*4+0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x53d91*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53d92*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53d93*4+0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x53d94*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x53d95*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53d96*4+0x02000000,0xb891); +reg_write( DDR_REG_BASE +0x53d97*4+0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x53d98*4+0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x53d99*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x53d9a*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x53d9b*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x53d9c*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x53d9d*4+0x02000000,0x657d); +reg_write( DDR_REG_BASE +0x53d9e*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x53d9f*4+0x02000000,0x9bf); +reg_write( DDR_REG_BASE +0x53da0*4+0x02000000,0x80a5); +reg_write( DDR_REG_BASE +0x53da1*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53da2*4+0x02000000,0xada); +reg_write( DDR_REG_BASE +0x53da3*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53da4*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x53da5*4+0x02000000,0xe7a); +reg_write( DDR_REG_BASE +0x53da6*4+0x02000000,0xfe0f); +reg_write( DDR_REG_BASE +0x53da7*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x53da8*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x53da9*4+0x02000000,0xf91); +reg_write( DDR_REG_BASE +0x53daa*4+0x02000000,0x9234); +reg_write( DDR_REG_BASE +0x53dab*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x53dac*4+0x02000000,0x2178); +reg_write( DDR_REG_BASE +0x53dad*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dae*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53daf*4+0x02000000,0x156); +reg_write( DDR_REG_BASE +0x53db0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53db1*4+0x02000000,0xdf2); +reg_write( DDR_REG_BASE +0x53db2*4+0x02000000,0xfc0f); +reg_write( DDR_REG_BASE +0x53db3*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53db4*4+0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x53db5*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53db6*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x53db7*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x53db8*4+0x02000000,0x3403); +reg_write( DDR_REG_BASE +0x53db9*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x53dba*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x53dbb*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53dbc*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x53dbd*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x53dbe*4+0x02000000,0x3302); +reg_write( DDR_REG_BASE +0x53dbf*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x53dc0*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53dc1*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53dc2*4+0x02000000,0x597); +reg_write( DDR_REG_BASE +0x53dc3*4+0x02000000,0xcfe); +reg_write( DDR_REG_BASE +0x53dc4*4+0x02000000,0xfc2f); +reg_write( DDR_REG_BASE +0x53dc5*4+0x02000000,0xda8a); +reg_write( DDR_REG_BASE +0x53dc6*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x53dc7*4+0x02000000,0x9fe); +reg_write( DDR_REG_BASE +0x53dc8*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x53dc9*4+0x02000000,0xd98a); +reg_write( DDR_REG_BASE +0x53dca*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53dcb*4+0x02000000,0xa8a); +reg_write( DDR_REG_BASE +0x53dcc*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53dcd*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x53dce*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x53dcf*4+0x02000000,0x3302); +reg_write( DDR_REG_BASE +0x53dd0*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x53dd1*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x53dd2*4+0x02000000,0xc3e6); +reg_write( DDR_REG_BASE +0x53dd3*4+0x02000000,0xc1b2); +reg_write( DDR_REG_BASE +0x53dd4*4+0x02000000,0xc14a); +reg_write( DDR_REG_BASE +0x53dd5*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x53dd6*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53dd7*4+0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x53dd8*4+0x02000000,0xe805); +reg_write( DDR_REG_BASE +0x53dd9*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x53dda*4+0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x53ddb*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x53ddc*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x53ddd*4+0x02000000,0x215a); +reg_write( DDR_REG_BASE +0x53dde*4+0x02000000,0x101); +reg_write( DDR_REG_BASE +0x53ddf*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53de0*4+0x02000000,0x210f); +reg_write( DDR_REG_BASE +0x53de1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53de2*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x53de3*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53de4*4+0x02000000,0xaa2); +reg_write( DDR_REG_BASE +0x53de5*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53de6*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53de7*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53de8*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x53de9*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53dea*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53deb*4+0x02000000,0xd2a); +reg_write( DDR_REG_BASE +0x53dec*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53ded*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x53dee*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x53def*4+0x02000000,0x8e82); +reg_write( DDR_REG_BASE +0x53df0*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x53df1*4+0x02000000,0xd8fe); +reg_write( DDR_REG_BASE +0x53df2*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53df3*4+0x02000000,0xf707); +reg_write( DDR_REG_BASE +0x53df4*4+0x02000000,0xd16); +reg_write( DDR_REG_BASE +0x53df5*4+0x02000000,0xfd0f); +reg_write( DDR_REG_BASE +0x53df6*4+0x02000000,0x2054); +reg_write( DDR_REG_BASE +0x53df7*4+0x02000000,0x880); +reg_write( DDR_REG_BASE +0x53df8*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53df9*4+0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x53dfa*4+0x02000000,0x1f8d); +reg_write( DDR_REG_BASE +0x53dfb*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x53dfc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dfd*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x53dfe*4+0x02000000,0xc18d); +reg_write( DDR_REG_BASE +0x53dff*4+0x02000000,0xd12); +reg_write( DDR_REG_BASE +0x53e00*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x53e01*4+0x02000000,0xc54b); +reg_write( DDR_REG_BASE +0x53e02*4+0x02000000,0xf76); +reg_write( DDR_REG_BASE +0x53e03*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x53e04*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x53e05*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53e06*4+0x02000000,0xe002); +reg_write( DDR_REG_BASE +0x53e07*4+0x02000000,0xd840); +reg_write( DDR_REG_BASE +0x53e08*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x53e09*4+0x02000000,0x1f84); +reg_write( DDR_REG_BASE +0x53e0a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e0b*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53e0c*4+0x02000000,0xd1e); +reg_write( DDR_REG_BASE +0x53e0d*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53e0e*4+0x02000000,0xb512); +reg_write( DDR_REG_BASE +0x53e0f*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53e10*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x53e11*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x53e12*4+0x02000000,0x4a); +reg_write( DDR_REG_BASE +0x53e13*4+0x02000000,0xd998); +reg_write( DDR_REG_BASE +0x53e14*4+0x02000000,0x2011); +reg_write( DDR_REG_BASE +0x53e15*4+0x02000000,0x8380); +reg_write( DDR_REG_BASE +0x53e16*4+0x02000000,0xd8aa); +reg_write( DDR_REG_BASE +0x53e17*4+0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x53e18*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53e19*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53e1a*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x53e1b*4+0x02000000,0xe04c); +reg_write( DDR_REG_BASE +0x53e1c*4+0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x53e1d*4+0x02000000,0x189c); +reg_write( DDR_REG_BASE +0x53e1e*4+0x02000000,0x54); +reg_write( DDR_REG_BASE +0x53e1f*4+0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x53e20*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53e21*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x53e22*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x53e23*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e24*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53e25*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53e26*4+0x02000000,0x2056); +reg_write( DDR_REG_BASE +0x53e27*4+0x02000000,0xe00); +reg_write( DDR_REG_BASE +0x53e28*4+0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x53e29*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x53e2a*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x53e2b*4+0x02000000,0x16e9); +reg_write( DDR_REG_BASE +0x53e2c*4+0x02000000,0x1700); +reg_write( DDR_REG_BASE +0x53e2d*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x53e2e*4+0x02000000,0xda2); +reg_write( DDR_REG_BASE +0x53e2f*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53e30*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53e31*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53e32*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x53e33*4+0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x53e34*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53e35*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53e36*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53e37*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53e38*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x53e39*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53e3a*4+0x02000000,0xe62); +reg_write( DDR_REG_BASE +0x53e3b*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53e3c*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53e3d*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53e3e*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x53e3f*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53e40*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x53e41*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x53e42*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53e43*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53e44*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53e45*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53e46*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x53e47*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x53e48*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x53e49*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x53e4a*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53e4b*4+0x02000000,0xc304); +reg_write( DDR_REG_BASE +0x53e4c*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x53e4d*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53e4e*4+0x02000000,0xe3a); +reg_write( DDR_REG_BASE +0x53e4f*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53e50*4+0x02000000,0xb990); +reg_write( DDR_REG_BASE +0x53e51*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53e52*4+0x02000000,0xdf2); +reg_write( DDR_REG_BASE +0x53e53*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53e54*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53e55*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53e56*4+0x02000000,0x9de); +reg_write( DDR_REG_BASE +0x53e57*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x53e58*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x53e59*4+0x02000000,0x16f0); +reg_write( DDR_REG_BASE +0x53e5a*4+0x02000000,0x1700); +reg_write( DDR_REG_BASE +0x53e5b*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x53e5c*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x53e5d*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x53e5e*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53e5f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e60*4+0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x53e61*4+0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x53e62*4+0x02000000,0xb888); +reg_write( DDR_REG_BASE +0x53e63*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x53e64*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x53e65*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x53e66*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53e67*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x53e68*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x53e69*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x53e6a*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x53e6b*4+0x02000000,0x7932); +reg_write( DDR_REG_BASE +0x53e6c*4+0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x53e6d*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x53e6e*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x53e6f*4+0x02000000,0xb887); +reg_write( DDR_REG_BASE +0x53e70*4+0x02000000,0x1ef2); +reg_write( DDR_REG_BASE +0x53e71*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x53e72*4+0x02000000,0xc109); +reg_write( DDR_REG_BASE +0x53e73*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x53e74*4+0x02000000,0xc0a); +reg_write( DDR_REG_BASE +0x53e75*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53e76*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x53e77*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x53e78*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53e79*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53e7a*4+0x02000000,0xd0a); +reg_write( DDR_REG_BASE +0x53e7b*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53e7c*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53e7d*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x53e7e*4+0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x53e7f*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53e80*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53e81*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53e82*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53e83*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x53e84*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53e85*4+0x02000000,0xdce); +reg_write( DDR_REG_BASE +0x53e86*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53e87*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53e88*4+0x02000000,0x812); +reg_write( DDR_REG_BASE +0x53e89*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53e8a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53e8b*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53e8c*4+0x02000000,0xc304); +reg_write( DDR_REG_BASE +0x53e8d*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x53e8e*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53e8f*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53e90*4+0x02000000,0xb88f); +reg_write( DDR_REG_BASE +0x53e91*4+0x02000000,0x791b); +reg_write( DDR_REG_BASE +0x53e92*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53e93*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53e94*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53e95*4+0x02000000,0xdae); +reg_write( DDR_REG_BASE +0x53e96*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53e97*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53e98*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x53e99*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x53e9a*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53e9b*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x53e9c*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x53e9d*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x53e9e*4+0x02000000,0xe01e); +reg_write( DDR_REG_BASE +0x53e9f*4+0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x53ea0*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53ea1*4+0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x53ea2*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x53ea3*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53ea4*4+0x02000000,0xd8e); +reg_write( DDR_REG_BASE +0x53ea5*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53ea6*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53ea7*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x53ea8*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53ea9*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x53eaa*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53eab*4+0x02000000,0xb98f); +reg_write( DDR_REG_BASE +0x53eac*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53ead*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x53eae*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x53eaf*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53eb0*4+0x02000000,0xd76); +reg_write( DDR_REG_BASE +0x53eb1*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53eb2*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53eb3*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53eb4*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53eb5*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53eb6*4+0x02000000,0xdb10); +reg_write( DDR_REG_BASE +0x53eb7*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53eb8*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x53eb9*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53eba*4+0x02000000,0xd62); +reg_write( DDR_REG_BASE +0x53ebb*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53ebc*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53ebd*4+0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x53ebe*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53ebf*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53ec0*4+0x02000000,0xf838); +reg_write( DDR_REG_BASE +0x53ec1*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53ec2*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x53ec3*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53ec4*4+0x02000000,0xd4e); +reg_write( DDR_REG_BASE +0x53ec5*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53ec6*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53ec7*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53ec8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ec9*4+0x02000000,0x6210); +reg_write( DDR_REG_BASE +0x53eca*4+0x02000000,0xb501); +reg_write( DDR_REG_BASE +0x53ecb*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x53ecc*4+0x02000000,0xcfe); +reg_write( DDR_REG_BASE +0x53ecd*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53ece*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53ecf*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53ed0*4+0x02000000,0x408); +reg_write( DDR_REG_BASE +0x53ed1*4+0x02000000,0xb501); +reg_write( DDR_REG_BASE +0x53ed2*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53ed3*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53ed4*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53ed5*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53ed6*4+0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x53ed7*4+0x02000000,0xbf); +reg_write( DDR_REG_BASE +0x53ed8*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53ed9*4+0x02000000,0x606); +reg_write( DDR_REG_BASE +0x53eda*4+0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x53edb*4+0x02000000,0xd833); +reg_write( DDR_REG_BASE +0x53edc*4+0x02000000,0xcde); +reg_write( DDR_REG_BASE +0x53edd*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53ede*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53edf*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x53ee0*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53ee1*4+0x02000000,0x1ef2); +reg_write( DDR_REG_BASE +0x53ee2*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x53ee3*4+0x02000000,0x8c6); +reg_write( DDR_REG_BASE +0x53ee4*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x53ee5*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53ee6*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53ee7*4+0x02000000,0xb42); +reg_write( DDR_REG_BASE +0x53ee8*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x53ee9*4+0x02000000,0xc18d); +reg_write( DDR_REG_BASE +0x53eea*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x53eeb*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53eec*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53eed*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53eee*4+0x02000000,0xb5e0); +reg_write( DDR_REG_BASE +0x53eef*4+0x02000000,0xc22); +reg_write( DDR_REG_BASE +0x53ef0*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53ef1*4+0x02000000,0xb5f2); +reg_write( DDR_REG_BASE +0x53ef2*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x53ef3*4+0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x53ef4*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53ef5*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53ef6*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53ef7*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53ef8*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x53ef9*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53efa*4+0x02000000,0xce2); +reg_write( DDR_REG_BASE +0x53efb*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53efc*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53efd*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53efe*4+0x02000000,0xc304); +reg_write( DDR_REG_BASE +0x53eff*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53f00*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53f01*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53f02*4+0x02000000,0xb990); +reg_write( DDR_REG_BASE +0x53f03*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x53f04*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53f05*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53f06*4+0x02000000,0xcca); +reg_write( DDR_REG_BASE +0x53f07*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53f08*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53f09*4+0x02000000,0xf814); +reg_write( DDR_REG_BASE +0x53f0a*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53f0b*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x53f0c*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53f0d*4+0x02000000,0xcbe); +reg_write( DDR_REG_BASE +0x53f0e*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53f0f*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53f10*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53f11*4+0x02000000,0xc76); +reg_write( DDR_REG_BASE +0x53f12*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53f13*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53f14*4+0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x53f15*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53f16*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53f17*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x53f18*4+0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x53f19*4+0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x53f1a*4+0x02000000,0xb5e1); +reg_write( DDR_REG_BASE +0x53f1b*4+0x02000000,0xb0e); +reg_write( DDR_REG_BASE +0x53f1c*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x53f1d*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x53f1e*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53f1f*4+0x02000000,0x82e); +reg_write( DDR_REG_BASE +0x53f20*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53f21*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53f22*4+0x02000000,0xc10b); +reg_write( DDR_REG_BASE +0x53f23*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x53f24*4+0x02000000,0xd00); +reg_write( DDR_REG_BASE +0x53f25*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x53f26*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x53f27*4+0x02000000,0xc10a); +reg_write( DDR_REG_BASE +0x53f28*4+0x02000000,0xf96); +reg_write( DDR_REG_BASE +0x53f29*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x53f2a*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x53f2b*4+0x02000000,0xb6e); +reg_write( DDR_REG_BASE +0x53f2c*4+0x02000000,0xfe0f); +reg_write( DDR_REG_BASE +0x53f2d*4+0x02000000,0xc02); +reg_write( DDR_REG_BASE +0x53f2e*4+0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x53f2f*4+0x02000000,0xc7c6); +reg_write( DDR_REG_BASE +0x53f30*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53f31*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x53f32*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53f33*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x53f34*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x53f35*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f36*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f37*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f38*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f39*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f40*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f41*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f42*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f43*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f44*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f45*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f46*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f47*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f48*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f49*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f50*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f51*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f52*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f53*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f54*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f55*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f56*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f57*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f58*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f59*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f60*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f61*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f62*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f63*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f64*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f65*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f66*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f67*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f68*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f69*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f70*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f71*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f72*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f73*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f74*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f75*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f76*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f77*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f78*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f79*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f80*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f81*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f82*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f83*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f84*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f85*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f86*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f87*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f88*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f89*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f90*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f91*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f92*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f93*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f94*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f95*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f96*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f97*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f98*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f99*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53faa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fab*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fad*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fae*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53faf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fba*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fbb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fbc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fbd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fbe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fbf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fca*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fcb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fcc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fcd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fce*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fcf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fda*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fdb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fdc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fdd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fde*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fdf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fea*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53feb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fec*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fed*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fef*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ffa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ffb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ffc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ffd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ffe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fff*4+0x02000000,0x0); + +reg_write( DDR_REG_BASE + 0xd0000*4+0x02000000,0x1); +reg_write( DDR_REG_BASE + 0xd0000*4+0x02000000,0x0); + +reg_write( DDR_REG_BASE +0x54000*4+0x02000000,0x000); +reg_write( DDR_REG_BASE +0x54001*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54002*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54003*4+0x02000000,0x42a); +reg_write( DDR_REG_BASE +0x54004*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x54005*4+0x02000000,0x0); + +//iteration Vref +// 0x14 15% +// 0x1a 20% +// 0x20 25% +// 0x26 30% +// 0x33 40% +reg_write( DDR_REG_BASE +0x54006*4+0x02000000,0x20); + +reg_write( DDR_REG_BASE +0x54007*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54008*4+0x02000000,0x131f); +reg_write( DDR_REG_BASE +0x54009*4+0x02000000,0xc8); +reg_write( DDR_REG_BASE +0x5400a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5400b*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x5400c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5400d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5400e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5400f*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x54010*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54011*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54012*4+0x02000000,0x110); +reg_write( DDR_REG_BASE +0x54013*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54014*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54015*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54016*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54017*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54018*4+0x02000000,0x0); + +reg_write( DDR_REG_BASE +0x54019*4+0x02000000,0x914); +reg_write( DDR_REG_BASE +0x5401a*4+0x02000000,0x33); +reg_write( DDR_REG_BASE +0x5401b*4+0x02000000,0x4d64); +reg_write( DDR_REG_BASE +0x5401c*4+0x02000000,0x4f08); +reg_write( DDR_REG_BASE +0x5401d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5401e*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5401f*4+0x02000000,0x914); +reg_write( DDR_REG_BASE +0x54020*4+0x02000000,0x33); +reg_write( DDR_REG_BASE +0x54021*4+0x02000000,0x4d64); +reg_write( DDR_REG_BASE +0x54022*4+0x02000000,0x4f08); +reg_write( DDR_REG_BASE +0x54023*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54024*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x54025*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54026*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54027*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54028*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54029*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5402a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5402b*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x5402c*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5402d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5402e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5402f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54030*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54031*4+0x02000000,0x0); + +reg_write( DDR_REG_BASE +0x54032*4+0x02000000,0x1400); +reg_write( DDR_REG_BASE +0x54033*4+0x02000000,0x3309); +reg_write( DDR_REG_BASE +0x54034*4+0x02000000,0x6400); +reg_write( DDR_REG_BASE +0x54035*4+0x02000000,0x084d); +reg_write( DDR_REG_BASE +0x54036*4+0x02000000,0x4f); +reg_write( DDR_REG_BASE +0x54037*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x54038*4+0x02000000,0x1400); +reg_write( DDR_REG_BASE +0x54039*4+0x02000000,0x3309); +reg_write( DDR_REG_BASE +0x5403a*4+0x02000000,0x6400); +reg_write( DDR_REG_BASE +0x5403b*4+0x02000000,0x84d); +reg_write( DDR_REG_BASE +0x5403c*4+0x02000000,0x4f); +reg_write( DDR_REG_BASE +0x5403d*4+0x02000000,0x400); + +reg_write( DDR_REG_BASE +0x5403e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5403f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54040*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54041*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54042*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54043*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54044*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54045*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54046*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54047*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54048*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54049*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54050*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54051*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54052*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54053*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54054*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54055*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54056*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54057*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54058*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54059*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54060*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54061*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54062*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54063*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54064*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54065*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54066*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54067*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54068*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54069*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54070*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54071*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54072*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54073*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54074*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54075*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54076*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54077*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54078*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54079*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54080*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54081*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54082*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54083*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54084*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54085*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54086*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54087*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54088*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54089*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54090*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54091*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54092*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54093*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54094*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54095*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54096*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54097*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54098*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54099*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540aa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ab*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ad*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ae*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540af*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ba*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540bb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540bc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540bd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540be*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540bf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ca*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540cb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540cc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540cd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ce*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540cf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540da*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540db*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540dc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540dd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540de*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540df*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ea*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540eb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ec*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ed*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ef*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540fa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540fb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540fc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540fd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540fe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ff*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54100*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54101*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54102*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54103*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54104*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54105*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54106*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54107*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54108*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54109*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54110*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54111*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54112*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54113*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54114*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54115*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54116*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54117*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54118*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54119*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54120*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54121*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54122*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54123*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54124*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54125*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54126*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54127*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54128*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54129*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54130*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54131*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54132*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54133*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54134*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54135*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54136*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54137*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54138*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54139*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54140*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54141*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54142*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54143*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54144*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54145*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54146*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54147*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54148*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54149*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54150*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54151*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54152*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54153*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54154*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54155*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54156*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54157*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54158*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54159*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54160*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54161*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54162*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54163*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54164*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54165*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54166*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54167*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54168*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54169*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54170*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54171*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54172*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54173*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54174*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54175*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54176*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54177*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54178*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54179*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54180*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54181*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54182*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54183*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54184*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54185*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54186*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54187*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54188*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54189*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54190*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54191*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54192*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54193*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54194*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54195*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54196*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54197*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54198*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54199*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541aa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ab*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ad*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ae*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541af*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ba*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541bb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541bc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541bd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541be*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541bf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ca*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541cb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541cc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541cd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ce*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541cf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541da*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541db*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541dc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541dd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541de*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541df*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ea*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541eb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ec*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ed*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ef*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541fa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541fb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541fc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541fd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541fe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ff*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54200*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54201*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54202*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54203*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54204*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54205*4+0x02000000,0xff); +reg_write( DDR_REG_BASE +0x54206*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54207*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54208*4+0x02000000,0x14a); +reg_write( DDR_REG_BASE +0x54209*4+0x02000000,0x181); +reg_write( DDR_REG_BASE +0x5420a*4+0x02000000,0x118); +reg_write( DDR_REG_BASE +0x5420b*4+0x02000000,0x118); +reg_write( DDR_REG_BASE +0x5420c*4+0x02000000,0x16f); +reg_write( DDR_REG_BASE +0x5420d*4+0x02000000,0x16f); +reg_write( DDR_REG_BASE +0x5420e*4+0x02000000,0x159); +reg_write( DDR_REG_BASE +0x5420f*4+0x02000000,0x181); +reg_write( DDR_REG_BASE +0x54210*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x54211*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x54212*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54213*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54214*4+0x02000000,0x701c); +reg_write( DDR_REG_BASE +0x54215*4+0x02000000,0x61a8); +reg_write( DDR_REG_BASE +0x54216*4+0x02000000,0x35ac); +reg_write( DDR_REG_BASE +0x54217*4+0x02000000,0x35ac); +reg_write( DDR_REG_BASE +0x54218*4+0x02000000,0x125c); +reg_write( DDR_REG_BASE +0x54219*4+0x02000000,0x125c); +reg_write( DDR_REG_BASE +0x5421a*4+0x02000000,0xc738); +reg_write( DDR_REG_BASE +0x5421b*4+0x02000000,0xb0f4); +reg_write( DDR_REG_BASE +0x5421c*4+0x02000000,0x6590); +reg_write( DDR_REG_BASE +0x5421d*4+0x02000000,0x6590); +reg_write( DDR_REG_BASE +0x5421e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5421f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54220*4+0x02000000,0x9f38); +reg_write( DDR_REG_BASE +0x54221*4+0x02000000,0x58); +reg_write( DDR_REG_BASE +0x54222*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54223*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54224*4+0x02000000,0x2820); +reg_write( DDR_REG_BASE +0x54225*4+0x02000000,0x140f); +reg_write( DDR_REG_BASE +0x54226*4+0x02000000,0x1f02); +reg_write( DDR_REG_BASE +0x54227*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54228*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54229*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x5422a*4+0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x5422b*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5422c*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x5422d*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5422e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5422f*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x54230*4+0x02000000,0x1f4); +reg_write( DDR_REG_BASE +0x54231*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54232*4+0x02000000,0xb900); +reg_write( DDR_REG_BASE +0x54233*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54234*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54235*4+0x02000000,0xba00); +reg_write( DDR_REG_BASE +0x54236*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54237*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54238*4+0x02000000,0xbb00); +reg_write( DDR_REG_BASE +0x54239*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5423a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5423b*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5423c*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5423d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5423e*4+0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x5423f*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54240*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54241*4+0x02000000,0xf900); +reg_write( DDR_REG_BASE +0x54242*4+0x02000000,0x4f0); +reg_write( DDR_REG_BASE +0x54243*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54244*4+0x02000000,0xfa02); +reg_write( DDR_REG_BASE +0x54245*4+0x02000000,0x4f0); +reg_write( DDR_REG_BASE +0x54246*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54247*4+0x02000000,0xfb00); +reg_write( DDR_REG_BASE +0x54248*4+0x02000000,0x4f0); +reg_write( DDR_REG_BASE +0x54249*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5424a*4+0x02000000,0x6004); +reg_write( DDR_REG_BASE +0x5424b*4+0x02000000,0x7f0); +reg_write( DDR_REG_BASE +0x5424c*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x5424d*4+0x02000000,0x6500); +reg_write( DDR_REG_BASE +0x5424e*4+0x02000000,0x7f0); +reg_write( DDR_REG_BASE +0x5424f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54250*4+0x02000000,0x6200); +reg_write( DDR_REG_BASE +0x54251*4+0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x54252*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54253*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x54254*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54255*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x54256*4+0x02000000,0x1f02); +reg_write( DDR_REG_BASE +0x54257*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54258*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54259*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x5425a*4+0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x5425b*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5425c*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x5425d*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5425e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5425f*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x54260*4+0x02000000,0x1f4); +reg_write( DDR_REG_BASE +0x54261*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54262*4+0x02000000,0xb900); +reg_write( DDR_REG_BASE +0x54263*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54264*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54265*4+0x02000000,0xba00); +reg_write( DDR_REG_BASE +0x54266*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54267*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54268*4+0x02000000,0xbb00); +reg_write( DDR_REG_BASE +0x54269*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5426a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5426b*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5426c*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5426d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5426e*4+0x02000000,0x1100); +reg_write( DDR_REG_BASE +0x5426f*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54270*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x54271*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x54272*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54273*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54274*4+0x02000000,0x18f0); +reg_write( DDR_REG_BASE +0x54275*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54276*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x54277*4+0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x54278*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54279*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5427a*4+0x02000000,0xf900); +reg_write( DDR_REG_BASE +0x5427b*4+0x02000000,0x4f0); +reg_write( DDR_REG_BASE +0x5427c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5427d*4+0x02000000,0xfa02); +reg_write( DDR_REG_BASE +0x5427e*4+0x02000000,0x4f0); +reg_write( DDR_REG_BASE +0x5427f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54280*4+0x02000000,0xfb00); +reg_write( DDR_REG_BASE +0x54281*4+0x02000000,0x4f0); +reg_write( DDR_REG_BASE +0x54282*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54283*4+0x02000000,0x6204); +reg_write( DDR_REG_BASE +0x54284*4+0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x54285*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54286*4+0x02000000,0x6200); +reg_write( DDR_REG_BASE +0x54287*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54288*4+0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x54289*4+0x02000000,0x6200); +reg_write( DDR_REG_BASE +0x5428a*4+0x02000000,0x1f4); +reg_write( DDR_REG_BASE +0x5428b*4+0x02000000,0xf000); +reg_write( DDR_REG_BASE +0x5428c*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x5428d*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5428e*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x5428f*4+0x02000000,0x1f02); +reg_write( DDR_REG_BASE +0x54290*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54291*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54292*4+0x02000000,0x3b00); +reg_write( DDR_REG_BASE +0x54293*4+0x02000000,0x2f0); +reg_write( DDR_REG_BASE +0x54294*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x54295*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x54296*4+0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x54297*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54298*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x54299*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5429a*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5429b*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x5429c*4+0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x5429d*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5429e*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x5429f*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542a0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542a1*4+0x02000000,0xb900); +reg_write( DDR_REG_BASE +0x542a2*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542a3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542a4*4+0x02000000,0xba00); +reg_write( DDR_REG_BASE +0x542a5*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542a6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542a7*4+0x02000000,0xbb00); +reg_write( DDR_REG_BASE +0x542a8*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542a9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542aa*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542ab*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542ac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542ad*4+0x02000000,0x6000); +reg_write( DDR_REG_BASE +0x542ae*4+0x02000000,0x7f0); +reg_write( DDR_REG_BASE +0x542af*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542b0*4+0x02000000,0x6500); +reg_write( DDR_REG_BASE +0x542b1*4+0x02000000,0x7f0); +reg_write( DDR_REG_BASE +0x542b2*4+0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x542b3*4+0x02000000,0x2601); +reg_write( DDR_REG_BASE +0x542b4*4+0x02000000,0x7ff); +reg_write( DDR_REG_BASE +0x542b5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542b6*4+0x02000000,0x2700); +reg_write( DDR_REG_BASE +0x542b7*4+0x02000000,0x7ff); +reg_write( DDR_REG_BASE +0x542b8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542b9*4+0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x542ba*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542bb*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x542bc*4+0x02000000,0x3200); +reg_write( DDR_REG_BASE +0x542bd*4+0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x542be*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542bf*4+0x02000000,0x6208); +reg_write( DDR_REG_BASE +0x542c0*4+0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x542c1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542c2*4+0x02000000,0x6200); +reg_write( DDR_REG_BASE +0x542c3*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542c4*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542c5*4+0x02000000,0x6200); +reg_write( DDR_REG_BASE +0x542c6*4+0x02000000,0x1f4); +reg_write( DDR_REG_BASE +0x542c7*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542c8*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x542c9*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542ca*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x542cb*4+0x02000000,0x1f02); +reg_write( DDR_REG_BASE +0x542cc*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542cd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542ce*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x542cf*4+0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x542d0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542d1*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x542d2*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542d3*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542d4*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x542d5*4+0x02000000,0x1f4); +reg_write( DDR_REG_BASE +0x542d6*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542d7*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x542d8*4+0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x542d9*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542da*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x542db*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542dc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542dd*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x542de*4+0x02000000,0x1f4); +reg_write( DDR_REG_BASE +0x542df*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542e0*4+0x02000000,0xb900); +reg_write( DDR_REG_BASE +0x542e1*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542e2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542e3*4+0x02000000,0xba00); +reg_write( DDR_REG_BASE +0x542e4*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542e5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542e6*4+0x02000000,0xbb00); +reg_write( DDR_REG_BASE +0x542e7*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542e8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542e9*4+0x02000000,0x1100); +reg_write( DDR_REG_BASE +0x542ea*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542eb*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542ec*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x542ed*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542ee*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542ef*4+0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x542f0*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542f1*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x542f2*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x542f3*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542f4*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542f5*4+0x02000000,0x6000); +reg_write( DDR_REG_BASE +0x542f6*4+0x02000000,0x7f0); +reg_write( DDR_REG_BASE +0x542f7*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542f8*4+0x02000000,0x6500); +reg_write( DDR_REG_BASE +0x542f9*4+0x02000000,0x7f0); +reg_write( DDR_REG_BASE +0x542fa*4+0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x542fb*4+0x02000000,0x2601); +reg_write( DDR_REG_BASE +0x542fc*4+0x02000000,0x7ff); +reg_write( DDR_REG_BASE +0x542fd*4+0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x542fe*4+0x02000000,0x27ff); +reg_write( DDR_REG_BASE +0x542ff*4+0x02000000,0x7ff); +reg_write( DDR_REG_BASE +0x54300*4+0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x54301*4+0x02000000,0x62ff); +reg_write( DDR_REG_BASE +0x54302*4+0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x54303*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54304*4+0x02000000,0x6200); +reg_write( DDR_REG_BASE +0x54305*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54306*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x54307*4+0x02000000,0x6200); +reg_write( DDR_REG_BASE +0x54308*4+0x02000000,0x1f4); +reg_write( DDR_REG_BASE +0x54309*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x5430a*4+0x02000000,0x3200); +reg_write( DDR_REG_BASE +0x5430b*4+0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x5430c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5430d*4+0x02000000,0x208); +reg_write( DDR_REG_BASE +0x5430e*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5430f*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x54310*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x54311*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54312*4+0x02000000,0x20d); +reg_write( DDR_REG_BASE +0x54313*4+0x02000000,0x301); +reg_write( DDR_REG_BASE +0x54314*4+0x02000000,0xc0b); +reg_write( DDR_REG_BASE +0x54315*4+0x02000000,0x160e); +reg_write( DDR_REG_BASE +0x54316*4+0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x54317*4+0x02000000,0x1811); +reg_write( DDR_REG_BASE +0x54318*4+0x02000000,0xc06); +reg_write( DDR_REG_BASE +0x54319*4+0x02000000,0x1610); +reg_write( DDR_REG_BASE +0x5431a*4+0x02000000,0x201c); +reg_write( DDR_REG_BASE +0x5431b*4+0x02000000,0x2824); +reg_write( DDR_REG_BASE +0x5431c*4+0x02000000,0xc06); +reg_write( DDR_REG_BASE +0x5431d*4+0x02000000,0x1812); +reg_write( DDR_REG_BASE +0x5431e*4+0x02000000,0x241e); +reg_write( DDR_REG_BASE +0x5431f*4+0x02000000,0x2c28); +reg_write( DDR_REG_BASE +0x54320*4+0x02000000,0xa06); +reg_write( DDR_REG_BASE +0x54321*4+0x02000000,0x140e); +reg_write( DDR_REG_BASE +0x54322*4+0x02000000,0x1c18); +reg_write( DDR_REG_BASE +0x54323*4+0x02000000,0x2420); +reg_write( DDR_REG_BASE +0x54324*4+0x02000000,0xa06); +reg_write( DDR_REG_BASE +0x54325*4+0x02000000,0x1610); +reg_write( DDR_REG_BASE +0x54326*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x54327*4+0x02000000,0x2824); +reg_write( DDR_REG_BASE +0x54328*4+0x02000000,0x6e); +reg_write( DDR_REG_BASE +0x54329*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x5432a*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5432b*4+0x02000000,0xfd); +reg_write( DDR_REG_BASE +0x5432c*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5432d*4+0x02000000,0xf); +reg_write( DDR_REG_BASE +0x5432e*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5432f*4+0x02000000,0x7); +reg_write( DDR_REG_BASE +0x54330*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54331*4+0x02000000,0xe8); +reg_write( DDR_REG_BASE +0x54332*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x54333*4+0x02000000,0xff); +reg_write( DDR_REG_BASE +0x54334*4+0x02000000,0xfc); +reg_write( DDR_REG_BASE +0x54335*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x54336*4+0x02000000,0x404); +reg_write( DDR_REG_BASE +0x54337*4+0x02000000,0x3a); +reg_write( DDR_REG_BASE +0x54338*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x54339*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x5433a*4+0x02000000,0x11); +reg_write( DDR_REG_BASE +0x5433b*4+0x02000000,0x7); +reg_write( DDR_REG_BASE +0x5433c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5433d*4+0x02000000,0x0); + + + + +reg_write( DDR_REG_BASE + 0xd0000*4+0x02000000,0x1); + + +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000d0099*4 +0x02000000 , 0x00000009 ); +reg_write( DDR_REG_BASE + 0x000d0099*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000d0099*4 +0x02000000 , 0x00000000 ); + +while((train_data&0x7) !=0x07) { + + reg_read ( DDR_REG_BASE + 0x000d0004*4 +0x02000000 , data ); + while((data&0x1) !=0x0) { + reg_read ( DDR_REG_BASE + 0x000d0004*4 +0x02000000 , data ); + } + + + + reg_read ( DDR_REG_BASE + 0x000d0032*4 +0x02000000 , train_data ); + + switch(train_data) + { + case 0x00000000: printf("%08X: PMU Major Msg: End of initialization \n",train_data);break; + case 0x00000001: printf("%08X: PMU Major Msg: End of fine write leveling \n",train_data);break; + case 0x00000002: printf("%08X: PMU Major Msg: End of read enable training \n",train_data);break; + case 0x00000003: printf("%08X: PMU Major Msg: End of read delay center optimization \n",train_data);break; + case 0x00000004: printf("%08X: PMU Major Msg: End of write delay center optimization \n",train_data);break; + case 0x00000005: printf("%08X: PMU Major Msg: End of 2D read delay/voltage center optimization \n",train_data);break; + case 0x00000006: printf("%08X: PMU Major Msg: End of 2D write delay /voltage center optimization \n",train_data);break; + case 0x00000007: printf("%08X: PMU Major Msg: Firmware run has completed \n",train_data);break; + case 0x00000008: printf("%08X: PMU Major Msg: Enter streaming message mode \n",train_data);break; + case 0x00000009: printf("%08X: PMU Major Msg: End of max read latency training \n",train_data);break; + case 0x0000000a: printf("%08X: PMU Major Msg: End of read dq deskew training \n",train_data);break; + case 0x0000000b: printf("%08X: PMU Major Msg: End of LCDL offset calibration \n",train_data);break; + case 0x0000000c: printf("%08X: PMU Major Msg: End of LRDIMM Specific training (DWL, MREP, MRD and MWD) \n",train_data);break; + case 0x0000000d: printf("%08X: PMU Major Msg: End of CA training \n",train_data);break; + case 0x000000fd: printf("%08X: PMU Major Msg: End of MPR read delay center optimization \n",train_data);break; + case 0x000000fe: printf("%08X: PMU Major Msg: End of Write leveling coarse delay \n",train_data);break; + case 0x000000ff: printf("%08X: PMU Major Msg: FATAL ERROR. \n",train_data);break; + default: printf("%08X: PMU Major Msg: Un-recognized message... ! \n",train_data);break; + } + + reg_write( DDR_REG_BASE + 0x000d0031*4 +0x02000000 , 0x00000000 ); + reg_read ( DDR_REG_BASE + 0x000d0004*4 +0x02000000 , data ); + while((data&0x1) ==0x0) { + reg_read ( DDR_REG_BASE + 0x000d0004*4 +0x02000000 , data ); + } + reg_write( DDR_REG_BASE + 0x000d0031*4 +0x02000000 , 0x00000001 ); + +} + +train_data=0; + + + +reg_write( DDR_REG_BASE + 0x000d0099*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000000 ); + + +reg_write( DDR_REG_BASE + 0x00090000*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x00090001*4 +0x02000000 , 0x00000400 ); +reg_write( DDR_REG_BASE + 0x00090002*4 +0x02000000 , 0x0000010e ); +reg_write( DDR_REG_BASE + 0x00090003*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090004*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090005*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090029*4 +0x02000000 , 0x0000000b ); +reg_write( DDR_REG_BASE + 0x0009002a*4 +0x02000000 , 0x00000480 ); +reg_write( DDR_REG_BASE + 0x0009002b*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009002c*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x0009002d*4 +0x02000000 , 0x00000448 ); +reg_write( DDR_REG_BASE + 0x0009002e*4 +0x02000000 , 0x00000139 ); +reg_write( DDR_REG_BASE + 0x0009002f*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090030*4 +0x02000000 , 0x00000478 ); +reg_write( DDR_REG_BASE + 0x00090031*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090032*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090033*4 +0x02000000 , 0x000000e8 ); +reg_write( DDR_REG_BASE + 0x00090034*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090035*4 +0x02000000 , 0x00000002 ); +reg_write( DDR_REG_BASE + 0x00090036*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x00090037*4 +0x02000000 , 0x00000139 ); +reg_write( DDR_REG_BASE + 0x00090038*4 +0x02000000 , 0x0000000b ); +reg_write( DDR_REG_BASE + 0x00090039*4 +0x02000000 , 0x000007c0 ); +reg_write( DDR_REG_BASE + 0x0009003a*4 +0x02000000 , 0x00000139 ); +reg_write( DDR_REG_BASE + 0x0009003b*4 +0x02000000 , 0x00000044 ); +reg_write( DDR_REG_BASE + 0x0009003c*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x0009003d*4 +0x02000000 , 0x00000159 ); +reg_write( DDR_REG_BASE + 0x0009003e*4 +0x02000000 , 0x0000014f ); +reg_write( DDR_REG_BASE + 0x0009003f*4 +0x02000000 , 0x00000630 ); +reg_write( DDR_REG_BASE + 0x00090040*4 +0x02000000 , 0x00000159 ); +reg_write( DDR_REG_BASE + 0x00090041*4 +0x02000000 , 0x00000047 ); +reg_write( DDR_REG_BASE + 0x00090042*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090043*4 +0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x00090044*4 +0x02000000 , 0x0000004f ); +reg_write( DDR_REG_BASE + 0x00090045*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090046*4 +0x02000000 , 0x00000179 ); +reg_write( DDR_REG_BASE + 0x00090047*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090048*4 +0x02000000 , 0x000000e0 ); +reg_write( DDR_REG_BASE + 0x00090049*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009004a*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009004b*4 +0x02000000 , 0x000007c8 ); +reg_write( DDR_REG_BASE + 0x0009004c*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009004d*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009004e*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x0009004f*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090050*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090051*4 +0x02000000 , 0x0000045a ); +reg_write( DDR_REG_BASE + 0x00090052*4 +0x02000000 , 0x00000009 ); +reg_write( DDR_REG_BASE + 0x00090053*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090054*4 +0x02000000 , 0x00000448 ); +reg_write( DDR_REG_BASE + 0x00090055*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090056*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x00090057*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090058*4 +0x02000000 , 0x00000179 ); +reg_write( DDR_REG_BASE + 0x00090059*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x0009005a*4 +0x02000000 , 0x00000618 ); +reg_write( DDR_REG_BASE + 0x0009005b*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009005c*4 +0x02000000 , 0x000040c0 ); +reg_write( DDR_REG_BASE + 0x0009005d*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x0009005e*4 +0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x0009005f*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090060*4 +0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00090061*4 +0x02000000 , 0x00000048 ); +reg_write( DDR_REG_BASE + 0x00090062*4 +0x02000000 , 0x00004040 ); +reg_write( DDR_REG_BASE + 0x00090063*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090064*4 +0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x00090065*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090066*4 +0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00090067*4 +0x02000000 , 0x00000048 ); +reg_write( DDR_REG_BASE + 0x00090068*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x00090069*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x0009006a*4 +0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x0009006b*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x0009006c*4 +0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x0009006d*4 +0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x0009006e*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009006f*4 +0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00090070*4 +0x02000000 , 0x00000078 ); +reg_write( DDR_REG_BASE + 0x00090071*4 +0x02000000 , 0x00000549 ); +reg_write( DDR_REG_BASE + 0x00090072*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090073*4 +0x02000000 , 0x00000159 ); +reg_write( DDR_REG_BASE + 0x00090074*4 +0x02000000 , 0x00000d49 ); +reg_write( DDR_REG_BASE + 0x00090075*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090076*4 +0x02000000 , 0x00000159 ); +reg_write( DDR_REG_BASE + 0x00090077*4 +0x02000000 , 0x0000094a ); +reg_write( DDR_REG_BASE + 0x00090078*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090079*4 +0x02000000 , 0x00000159 ); +reg_write( DDR_REG_BASE + 0x0009007a*4 +0x02000000 , 0x00000441 ); +reg_write( DDR_REG_BASE + 0x0009007b*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x0009007c*4 +0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x0009007d*4 +0x02000000 , 0x00000042 ); +reg_write( DDR_REG_BASE + 0x0009007e*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x0009007f*4 +0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x00090080*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00090081*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090082*4 +0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x00090083*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090084*4 +0x02000000 , 0x000000e0 ); +reg_write( DDR_REG_BASE + 0x00090085*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090086*4 +0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x00090087*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x00090088*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090089*4 +0x02000000 , 0x00000009 ); +reg_write( DDR_REG_BASE + 0x0009008a*4 +0x02000000 , 0x000003c0 ); +reg_write( DDR_REG_BASE + 0x0009008b*4 +0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x0009008c*4 +0x02000000 , 0x00000009 ); +reg_write( DDR_REG_BASE + 0x0009008d*4 +0x02000000 , 0x000003c0 ); +reg_write( DDR_REG_BASE + 0x0009008e*4 +0x02000000 , 0x00000159 ); +reg_write( DDR_REG_BASE + 0x0009008f*4 +0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x00090090*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x00090091*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090092*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090093*4 +0x02000000 , 0x000003c0 ); +reg_write( DDR_REG_BASE + 0x00090094*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090095*4 +0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x00090096*4 +0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00090097*4 +0x02000000 , 0x00000048 ); +reg_write( DDR_REG_BASE + 0x00090098*4 +0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x00090099*4 +0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x0009009a*4 +0x02000000 , 0x00000058 ); +reg_write( DDR_REG_BASE + 0x0009009b*4 +0x02000000 , 0x0000000b ); +reg_write( DDR_REG_BASE + 0x0009009c*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x0009009d*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009009e*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x0009009f*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000900a0*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x000900a1*4 +0x02000000 , 0x00000005 ); +reg_write( DDR_REG_BASE + 0x000900a2*4 +0x02000000 , 0x000007c0 ); +reg_write( DDR_REG_BASE + 0x000900a3*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00040000*4 +0x02000000 , 0x00000811 ); +reg_write( DDR_REG_BASE + 0x00040020*4 +0x02000000 , 0x00000880 ); +reg_write( DDR_REG_BASE + 0x00040040*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040060*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040001*4 +0x02000000 , 0x00004008 ); +reg_write( DDR_REG_BASE + 0x00040021*4 +0x02000000 , 0x00000083 ); +reg_write( DDR_REG_BASE + 0x00040041*4 +0x02000000 , 0x0000004f ); +reg_write( DDR_REG_BASE + 0x00040061*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040002*4 +0x02000000 , 0x00004040 ); +reg_write( DDR_REG_BASE + 0x00040022*4 +0x02000000 , 0x00000083 ); +reg_write( DDR_REG_BASE + 0x00040042*4 +0x02000000 , 0x00000051 ); +reg_write( DDR_REG_BASE + 0x00040062*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040003*4 +0x02000000 , 0x00000811 ); +reg_write( DDR_REG_BASE + 0x00040023*4 +0x02000000 , 0x00000880 ); +reg_write( DDR_REG_BASE + 0x00040043*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040063*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040004*4 +0x02000000 , 0x00000720 ); +reg_write( DDR_REG_BASE + 0x00040024*4 +0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00040044*4 +0x02000000 , 0x00001740 ); +reg_write( DDR_REG_BASE + 0x00040064*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040005*4 +0x02000000 , 0x00000016 ); +reg_write( DDR_REG_BASE + 0x00040025*4 +0x02000000 , 0x00000083 ); +reg_write( DDR_REG_BASE + 0x00040045*4 +0x02000000 , 0x0000004b ); +reg_write( DDR_REG_BASE + 0x00040065*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040006*4 +0x02000000 , 0x00000716 ); +reg_write( DDR_REG_BASE + 0x00040026*4 +0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00040046*4 +0x02000000 , 0x00002001 ); +reg_write( DDR_REG_BASE + 0x00040066*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040007*4 +0x02000000 , 0x00000716 ); +reg_write( DDR_REG_BASE + 0x00040027*4 +0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00040047*4 +0x02000000 , 0x00002800 ); +reg_write( DDR_REG_BASE + 0x00040067*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040008*4 +0x02000000 , 0x00000716 ); +reg_write( DDR_REG_BASE + 0x00040028*4 +0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00040048*4 +0x02000000 , 0x00000f00 ); +reg_write( DDR_REG_BASE + 0x00040068*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040009*4 +0x02000000 , 0x00000720 ); +reg_write( DDR_REG_BASE + 0x00040029*4 +0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00040049*4 +0x02000000 , 0x00001400 ); +reg_write( DDR_REG_BASE + 0x00040069*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004000a*4 +0x02000000 , 0x00000e08 ); +reg_write( DDR_REG_BASE + 0x0004002a*4 +0x02000000 , 0x00000c15 ); +reg_write( DDR_REG_BASE + 0x0004004a*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004006a*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004000b*4 +0x02000000 , 0x00000625 ); +reg_write( DDR_REG_BASE + 0x0004002b*4 +0x02000000 , 0x00000015 ); +reg_write( DDR_REG_BASE + 0x0004004b*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004006b*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004000c*4 +0x02000000 , 0x00004028 ); +reg_write( DDR_REG_BASE + 0x0004002c*4 +0x02000000 , 0x00000080 ); +reg_write( DDR_REG_BASE + 0x0004004c*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004006c*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004000d*4 +0x02000000 , 0x00000e08 ); +reg_write( DDR_REG_BASE + 0x0004002d*4 +0x02000000 , 0x00000c1a ); +reg_write( DDR_REG_BASE + 0x0004004d*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004006d*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004000e*4 +0x02000000 , 0x00000625 ); +reg_write( DDR_REG_BASE + 0x0004002e*4 +0x02000000 , 0x0000001a ); +reg_write( DDR_REG_BASE + 0x0004004e*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004006e*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004000f*4 +0x02000000 , 0x00004040 ); +reg_write( DDR_REG_BASE + 0x0004002f*4 +0x02000000 , 0x00000080 ); +reg_write( DDR_REG_BASE + 0x0004004f*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004006f*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040010*4 +0x02000000 , 0x00002604 ); +reg_write( DDR_REG_BASE + 0x00040030*4 +0x02000000 , 0x00000015 ); +reg_write( DDR_REG_BASE + 0x00040050*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040070*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040011*4 +0x02000000 , 0x00000708 ); +reg_write( DDR_REG_BASE + 0x00040031*4 +0x02000000 , 0x00000005 ); +reg_write( DDR_REG_BASE + 0x00040051*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040071*4 +0x02000000 , 0x00002002 ); +reg_write( DDR_REG_BASE + 0x00040012*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00040032*4 +0x02000000 , 0x00000080 ); +reg_write( DDR_REG_BASE + 0x00040052*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040072*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040013*4 +0x02000000 , 0x00002604 ); +reg_write( DDR_REG_BASE + 0x00040033*4 +0x02000000 , 0x0000001a ); +reg_write( DDR_REG_BASE + 0x00040053*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040073*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040014*4 +0x02000000 , 0x00000708 ); +reg_write( DDR_REG_BASE + 0x00040034*4 +0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x00040054*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040074*4 +0x02000000 , 0x00002002 ); +reg_write( DDR_REG_BASE + 0x00040015*4 +0x02000000 , 0x00004040 ); +reg_write( DDR_REG_BASE + 0x00040035*4 +0x02000000 , 0x00000080 ); +reg_write( DDR_REG_BASE + 0x00040055*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040075*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040016*4 +0x02000000 , 0x0000060a ); +reg_write( DDR_REG_BASE + 0x00040036*4 +0x02000000 , 0x00000015 ); +reg_write( DDR_REG_BASE + 0x00040056*4 +0x02000000 , 0x00001200 ); +reg_write( DDR_REG_BASE + 0x00040076*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040017*4 +0x02000000 , 0x0000061a ); +reg_write( DDR_REG_BASE + 0x00040037*4 +0x02000000 , 0x00000015 ); +reg_write( DDR_REG_BASE + 0x00040057*4 +0x02000000 , 0x00001300 ); +reg_write( DDR_REG_BASE + 0x00040077*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040018*4 +0x02000000 , 0x0000060a ); +reg_write( DDR_REG_BASE + 0x00040038*4 +0x02000000 , 0x0000001a ); +reg_write( DDR_REG_BASE + 0x00040058*4 +0x02000000 , 0x00001200 ); +reg_write( DDR_REG_BASE + 0x00040078*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040019*4 +0x02000000 , 0x00000642 ); +reg_write( DDR_REG_BASE + 0x00040039*4 +0x02000000 , 0x0000001a ); +reg_write( DDR_REG_BASE + 0x00040059*4 +0x02000000 , 0x00001300 ); +reg_write( DDR_REG_BASE + 0x00040079*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004001a*4 +0x02000000 , 0x00004808 ); +reg_write( DDR_REG_BASE + 0x0004003a*4 +0x02000000 , 0x00000880 ); +reg_write( DDR_REG_BASE + 0x0004005a*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004007a*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900a4*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900a5*4 +0x02000000 , 0x00000790 ); +reg_write( DDR_REG_BASE + 0x000900a6*4 +0x02000000 , 0x0000011a ); +reg_write( DDR_REG_BASE + 0x000900a7*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900a8*4 +0x02000000 , 0x000007aa ); +reg_write( DDR_REG_BASE + 0x000900a9*4 +0x02000000 , 0x0000002a ); +reg_write( DDR_REG_BASE + 0x000900aa*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000900ab*4 +0x02000000 , 0x000007b2 ); +reg_write( DDR_REG_BASE + 0x000900ac*4 +0x02000000 , 0x0000002a ); +reg_write( DDR_REG_BASE + 0x000900ad*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900ae*4 +0x02000000 , 0x000007c8 ); +reg_write( DDR_REG_BASE + 0x000900af*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x000900b0*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000900b1*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000900b2*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x000900b3*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000900b4*4 +0x02000000 , 0x000002a8 ); +reg_write( DDR_REG_BASE + 0x000900b5*4 +0x02000000 , 0x00000129 ); +reg_write( DDR_REG_BASE + 0x000900b6*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900b7*4 +0x02000000 , 0x00000370 ); +reg_write( DDR_REG_BASE + 0x000900b8*4 +0x02000000 , 0x00000129 ); +reg_write( DDR_REG_BASE + 0x000900b9*4 +0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x000900ba*4 +0x02000000 , 0x000003c8 ); +reg_write( DDR_REG_BASE + 0x000900bb*4 +0x02000000 , 0x000001a9 ); +reg_write( DDR_REG_BASE + 0x000900bc*4 +0x02000000 , 0x0000000c ); +reg_write( DDR_REG_BASE + 0x000900bd*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x000900be*4 +0x02000000 , 0x00000199 ); +reg_write( DDR_REG_BASE + 0x000900bf*4 +0x02000000 , 0x00000014 ); +reg_write( DDR_REG_BASE + 0x000900c0*4 +0x02000000 , 0x00000790 ); +reg_write( DDR_REG_BASE + 0x000900c1*4 +0x02000000 , 0x0000011a ); +reg_write( DDR_REG_BASE + 0x000900c2*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900c3*4 +0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x000900c4*4 +0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x000900c5*4 +0x02000000 , 0x0000000e ); +reg_write( DDR_REG_BASE + 0x000900c6*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x000900c7*4 +0x02000000 , 0x00000199 ); +reg_write( DDR_REG_BASE + 0x000900c8*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900c9*4 +0x02000000 , 0x00008568 ); +reg_write( DDR_REG_BASE + 0x000900ca*4 +0x02000000 , 0x00000108 ); +reg_write( DDR_REG_BASE + 0x000900cb*4 +0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x000900cc*4 +0x02000000 , 0x00000790 ); +reg_write( DDR_REG_BASE + 0x000900cd*4 +0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x000900ce*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900cf*4 +0x02000000 , 0x000001d8 ); +reg_write( DDR_REG_BASE + 0x000900d0*4 +0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x000900d1*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000900d2*4 +0x02000000 , 0x00008558 ); +reg_write( DDR_REG_BASE + 0x000900d3*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x000900d4*4 +0x02000000 , 0x00000070 ); +reg_write( DDR_REG_BASE + 0x000900d5*4 +0x02000000 , 0x00000788 ); +reg_write( DDR_REG_BASE + 0x000900d6*4 +0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x000900d7*4 +0x02000000 , 0x00001ff8 ); +reg_write( DDR_REG_BASE + 0x000900d8*4 +0x02000000 , 0x000085a8 ); +reg_write( DDR_REG_BASE + 0x000900d9*4 +0x02000000 , 0x000001e8 ); +reg_write( DDR_REG_BASE + 0x000900da*4 +0x02000000 , 0x00000050 ); +reg_write( DDR_REG_BASE + 0x000900db*4 +0x02000000 , 0x00000798 ); +reg_write( DDR_REG_BASE + 0x000900dc*4 +0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x000900dd*4 +0x02000000 , 0x00000060 ); +reg_write( DDR_REG_BASE + 0x000900de*4 +0x02000000 , 0x000007a0 ); +reg_write( DDR_REG_BASE + 0x000900df*4 +0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x000900e0*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900e1*4 +0x02000000 , 0x00008310 ); +reg_write( DDR_REG_BASE + 0x000900e2*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x000900e3*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900e4*4 +0x02000000 , 0x0000a310 ); +reg_write( DDR_REG_BASE + 0x000900e5*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x000900e6*4 +0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x000900e7*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x000900e8*4 +0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x000900e9*4 +0x02000000 , 0x0000006e ); +reg_write( DDR_REG_BASE + 0x000900ea*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900eb*4 +0x02000000 , 0x00000068 ); +reg_write( DDR_REG_BASE + 0x000900ec*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900ed*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x000900ee*4 +0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x000900ef*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900f0*4 +0x02000000 , 0x00008310 ); +reg_write( DDR_REG_BASE + 0x000900f1*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x000900f2*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900f3*4 +0x02000000 , 0x0000a310 ); +reg_write( DDR_REG_BASE + 0x000900f4*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x000900f5*4 +0x02000000 , 0x00001ff8 ); +reg_write( DDR_REG_BASE + 0x000900f6*4 +0x02000000 , 0x000085a8 ); +reg_write( DDR_REG_BASE + 0x000900f7*4 +0x02000000 , 0x000001e8 ); +reg_write( DDR_REG_BASE + 0x000900f8*4 +0x02000000 , 0x00000068 ); +reg_write( DDR_REG_BASE + 0x000900f9*4 +0x02000000 , 0x00000798 ); +reg_write( DDR_REG_BASE + 0x000900fa*4 +0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x000900fb*4 +0x02000000 , 0x00000078 ); +reg_write( DDR_REG_BASE + 0x000900fc*4 +0x02000000 , 0x000007a0 ); +reg_write( DDR_REG_BASE + 0x000900fd*4 +0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x000900fe*4 +0x02000000 , 0x00000068 ); +reg_write( DDR_REG_BASE + 0x000900ff*4 +0x02000000 , 0x00000790 ); +reg_write( DDR_REG_BASE + 0x00090100*4 +0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x00090101*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090102*4 +0x02000000 , 0x00008b10 ); +reg_write( DDR_REG_BASE + 0x00090103*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x00090104*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090105*4 +0x02000000 , 0x0000ab10 ); +reg_write( DDR_REG_BASE + 0x00090106*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x00090107*4 +0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x00090108*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x00090109*4 +0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x0009010a*4 +0x02000000 , 0x00000058 ); +reg_write( DDR_REG_BASE + 0x0009010b*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009010c*4 +0x02000000 , 0x00000068 ); +reg_write( DDR_REG_BASE + 0x0009010d*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009010e*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x0009010f*4 +0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x00090110*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090111*4 +0x02000000 , 0x00008b10 ); +reg_write( DDR_REG_BASE + 0x00090112*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x00090113*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00090114*4 +0x02000000 , 0x0000ab10 ); +reg_write( DDR_REG_BASE + 0x00090115*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x00090116*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090117*4 +0x02000000 , 0x000001d8 ); +reg_write( DDR_REG_BASE + 0x00090118*4 +0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x00090119*4 +0x02000000 , 0x00000080 ); +reg_write( DDR_REG_BASE + 0x0009011a*4 +0x02000000 , 0x00000790 ); +reg_write( DDR_REG_BASE + 0x0009011b*4 +0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x0009011c*4 +0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x0009011d*4 +0x02000000 , 0x000007aa ); +reg_write( DDR_REG_BASE + 0x0009011e*4 +0x02000000 , 0x0000006a ); +reg_write( DDR_REG_BASE + 0x0009011f*4 +0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x00090120*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090121*4 +0x02000000 , 0x000001e9 ); +reg_write( DDR_REG_BASE + 0x00090122*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090123*4 +0x02000000 , 0x00008080 ); +reg_write( DDR_REG_BASE + 0x00090124*4 +0x02000000 , 0x00000108 ); +reg_write( DDR_REG_BASE + 0x00090125*4 +0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00090126*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x00090127*4 +0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x00090128*4 +0x02000000 , 0x0000000c ); +reg_write( DDR_REG_BASE + 0x00090129*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009012a*4 +0x02000000 , 0x00000068 ); +reg_write( DDR_REG_BASE + 0x0009012b*4 +0x02000000 , 0x00000009 ); +reg_write( DDR_REG_BASE + 0x0009012c*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009012d*4 +0x02000000 , 0x000001a9 ); +reg_write( DDR_REG_BASE + 0x0009012e*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009012f*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x00090130*4 +0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x00090131*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090132*4 +0x02000000 , 0x00008080 ); +reg_write( DDR_REG_BASE + 0x00090133*4 +0x02000000 , 0x00000108 ); +reg_write( DDR_REG_BASE + 0x00090134*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090135*4 +0x02000000 , 0x000007aa ); +reg_write( DDR_REG_BASE + 0x00090136*4 +0x02000000 , 0x0000006a ); +reg_write( DDR_REG_BASE + 0x00090137*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090138*4 +0x02000000 , 0x00008568 ); +reg_write( DDR_REG_BASE + 0x00090139*4 +0x02000000 , 0x00000108 ); +reg_write( DDR_REG_BASE + 0x0009013a*4 +0x02000000 , 0x000000b7 ); +reg_write( DDR_REG_BASE + 0x0009013b*4 +0x02000000 , 0x00000790 ); +reg_write( DDR_REG_BASE + 0x0009013c*4 +0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x0009013d*4 +0x02000000 , 0x0000001f ); +reg_write( DDR_REG_BASE + 0x0009013e*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009013f*4 +0x02000000 , 0x00000068 ); +reg_write( DDR_REG_BASE + 0x00090140*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090141*4 +0x02000000 , 0x00008558 ); +reg_write( DDR_REG_BASE + 0x00090142*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x00090143*4 +0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00090144*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x00090145*4 +0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x00090146*4 +0x02000000 , 0x0000000d ); +reg_write( DDR_REG_BASE + 0x00090147*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090148*4 +0x02000000 , 0x00000068 ); +reg_write( DDR_REG_BASE + 0x00090149*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009014a*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x0009014b*4 +0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x0009014c*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009014d*4 +0x02000000 , 0x00008558 ); +reg_write( DDR_REG_BASE + 0x0009014e*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x0009014f*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090150*4 +0x02000000 , 0x000003c8 ); +reg_write( DDR_REG_BASE + 0x00090151*4 +0x02000000 , 0x000001a9 ); +reg_write( DDR_REG_BASE + 0x00090152*4 +0x02000000 , 0x00000003 ); +reg_write( DDR_REG_BASE + 0x00090153*4 +0x02000000 , 0x00000370 ); +reg_write( DDR_REG_BASE + 0x00090154*4 +0x02000000 , 0x00000129 ); +reg_write( DDR_REG_BASE + 0x00090155*4 +0x02000000 , 0x00000020 ); +reg_write( DDR_REG_BASE + 0x00090156*4 +0x02000000 , 0x000002aa ); +reg_write( DDR_REG_BASE + 0x00090157*4 +0x02000000 , 0x00000009 ); +reg_write( DDR_REG_BASE + 0x00090158*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090159*4 +0x02000000 , 0x000000e8 ); +reg_write( DDR_REG_BASE + 0x0009015a*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009015b*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009015c*4 +0x02000000 , 0x00008140 ); +reg_write( DDR_REG_BASE + 0x0009015d*4 +0x02000000 , 0x0000010c ); +reg_write( DDR_REG_BASE + 0x0009015e*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x0009015f*4 +0x02000000 , 0x00008138 ); +reg_write( DDR_REG_BASE + 0x00090160*4 +0x02000000 , 0x00000104 ); +reg_write( DDR_REG_BASE + 0x00090161*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090162*4 +0x02000000 , 0x00000448 ); +reg_write( DDR_REG_BASE + 0x00090163*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090164*4 +0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00090165*4 +0x02000000 , 0x000007c0 ); +reg_write( DDR_REG_BASE + 0x00090166*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090167*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090168*4 +0x02000000 , 0x000000e8 ); +reg_write( DDR_REG_BASE + 0x00090169*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009016a*4 +0x02000000 , 0x00000047 ); +reg_write( DDR_REG_BASE + 0x0009016b*4 +0x02000000 , 0x00000630 ); +reg_write( DDR_REG_BASE + 0x0009016c*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009016d*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x0009016e*4 +0x02000000 , 0x00000618 ); +reg_write( DDR_REG_BASE + 0x0009016f*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090170*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090171*4 +0x02000000 , 0x000000e0 ); +reg_write( DDR_REG_BASE + 0x00090172*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090173*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090174*4 +0x02000000 , 0x000007c8 ); +reg_write( DDR_REG_BASE + 0x00090175*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090176*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090177*4 +0x02000000 , 0x00008140 ); +reg_write( DDR_REG_BASE + 0x00090178*4 +0x02000000 , 0x0000010c ); +reg_write( DDR_REG_BASE + 0x00090179*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009017a*4 +0x02000000 , 0x00000478 ); +reg_write( DDR_REG_BASE + 0x0009017b*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009017c*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009017d*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x0009017e*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x0009017f*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090180*4 +0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00090181*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090006*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090007*4 +0x02000000 , 0x000007c8 ); +reg_write( DDR_REG_BASE + 0x00090008*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090009*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009000a*4 +0x02000000 , 0x00000400 ); +reg_write( DDR_REG_BASE + 0x0009000b*4 +0x02000000 , 0x00000106 ); +reg_write( DDR_REG_BASE + 0x000d00e7*4 +0x02000000 , 0x00000400 ); +reg_write( DDR_REG_BASE + 0x00090017*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009001f*4 +0x02000000 , 0x00000029 ); +reg_write( DDR_REG_BASE + 0x00090026*4 +0x02000000 , 0x00000068 ); +reg_write( DDR_REG_BASE + 0x000400d0*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000400d1*4 +0x02000000 , 0x00000101 ); +reg_write( DDR_REG_BASE + 0x000400d2*4 +0x02000000 , 0x00000105 ); +reg_write( DDR_REG_BASE + 0x000400d3*4 +0x02000000 , 0x00000107 ); +reg_write( DDR_REG_BASE + 0x000400d4*4 +0x02000000 , 0x0000010f ); +reg_write( DDR_REG_BASE + 0x000400d5*4 +0x02000000 , 0x00000202 ); +reg_write( DDR_REG_BASE + 0x000400d6*4 +0x02000000 , 0x0000020a ); +reg_write( DDR_REG_BASE + 0x000400d7*4 +0x02000000 , 0x0000020b ); +reg_write( DDR_REG_BASE + 0x0002003a*4 +0x02000000 , 0x00000002 ); +reg_write( DDR_REG_BASE + 0x000200be*4 +0x02000000 , 0x00000003 ); +reg_write( DDR_REG_BASE + 0x0002000b*4 +0x02000000 , 0x00000021 ); +reg_write( DDR_REG_BASE + 0x0002000c*4 +0x02000000 , 0x00000042 ); +reg_write( DDR_REG_BASE + 0x0002000d*4 +0x02000000 , 0x0000029b ); +reg_write( DDR_REG_BASE + 0x0002000e*4 +0x02000000 , 0x0000002c ); +reg_write( DDR_REG_BASE + 0x0009000c*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009000d*4 +0x02000000 , 0x00000173 ); +reg_write( DDR_REG_BASE + 0x0009000e*4 +0x02000000 , 0x00000060 ); +reg_write( DDR_REG_BASE + 0x0009000f*4 +0x02000000 , 0x00006110 ); +reg_write( DDR_REG_BASE + 0x00090010*4 +0x02000000 , 0x00002152 ); +reg_write( DDR_REG_BASE + 0x00090011*4 +0x02000000 , 0x0000dfbd ); +reg_write( DDR_REG_BASE + 0x00090012*4 +0x02000000 , 0x00002060 ); +reg_write( DDR_REG_BASE + 0x00090013*4 +0x02000000 , 0x00006152 ); +reg_write( DDR_REG_BASE + 0x00040080*4 +0x02000000 , 0x000000e0 ); +reg_write( DDR_REG_BASE + 0x00040081*4 +0x02000000 , 0x00000012 ); +reg_write( DDR_REG_BASE + 0x00040082*4 +0x02000000 , 0x000000e0 ); +reg_write( DDR_REG_BASE + 0x00040083*4 +0x02000000 , 0x00000012 ); +reg_write( DDR_REG_BASE + 0x00040084*4 +0x02000000 , 0x000000e0 ); +reg_write( DDR_REG_BASE + 0x00040085*4 +0x02000000 , 0x00000012 ); +reg_write( DDR_REG_BASE + 0x000400fd*4 +0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00010011*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00010012*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00010013*4 +0x02000000 , 0x00000180 ); +reg_write( DDR_REG_BASE + 0x00010018*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00010002*4 +0x02000000 , 0x00006209 ); +reg_write( DDR_REG_BASE + 0x000100b2*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000101b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000102b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000103b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000104b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000105b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000106b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000107b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000108b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00011011*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00011012*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00011013*4 +0x02000000 , 0x00000180 ); +reg_write( DDR_REG_BASE + 0x00011018*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00011002*4 +0x02000000 , 0x00006209 ); +reg_write( DDR_REG_BASE + 0x000110b2*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000111b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000112b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000113b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000114b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000115b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000116b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000117b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000118b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00012011*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00012012*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00012013*4 +0x02000000 , 0x00000180 ); +reg_write( DDR_REG_BASE + 0x00012018*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00012002*4 +0x02000000 , 0x00006209 ); +reg_write( DDR_REG_BASE + 0x000120b2*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000121b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000122b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000123b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000124b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000125b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000126b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000127b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000128b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00013011*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00013012*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00013013*4 +0x02000000 , 0x00000180 ); +reg_write( DDR_REG_BASE + 0x00013018*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00013002*4 +0x02000000 , 0x00006209 ); +reg_write( DDR_REG_BASE + 0x000130b2*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000131b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000132b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000133b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000134b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000135b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000136b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000137b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000138b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00020089*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00020088*4 +0x02000000 , 0x00000019 ); +reg_write( DDR_REG_BASE + 0x000c0080*4 +0x02000000 , 0x00000002 ); +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000000 ); +reg_read ( DDR_REG_BASE + 0x00020010*4 +0x02000000 , data ); +reg_write( DDR_REG_BASE + 0x00020010*4 +0x02000000 , 0x0000006a ); +reg_write( DDR_REG_BASE + 0x00020010*4 +0x02000000 , 0x0000006a ); +reg_read ( DDR_REG_BASE + 0x0002001d*4 +0x02000000 , data ); +reg_write( DDR_REG_BASE + 0x0002001d*4 +0x02000000 , 0x00000001 ); +reg_read ( DDR_REG_BASE + 0x00020097*4 +0x02000000 , data ); + + + + +reg_write( DDR_REG_BASE + 0x000001b0 , 0x00000034 ); + +reg_read (DDR_REG_BASE + 0x000001bc , data ); +while((data&0x1) !=0x1) { + reg_read (DDR_REG_BASE + 0x000001bc , data ); +} + + +reg_write( DDR_REG_BASE + 0x000001b0 , 0x00000014 ); +reg_write( DDR_REG_BASE + 0x000001b0 , 0x00000015 ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000320 , 0x00000001 ); + + + +reg_read (DDR_REG_BASE + 0x00000324 , data ); + while((data&0x1) !=0x1) { + reg_read (DDR_REG_BASE + 0x00000324 , data ); + } + +reg_read (DDR_REG_BASE + 0x00000004 , data ); + while((data&0x1) !=0x1) { + reg_read (DDR_REG_BASE + 0x00000004 , data ); + } + + + + +reg_write( DDR_REG_BASE + 0x000001c4 , 0xd1000000 ); +reg_write( DDR_REG_BASE + 0x00000320 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000000d0 , 0x00020002 ); +reg_write( DDR_REG_BASE + 0x00000320 , 0x00000001 ); + + + +reg_read (DDR_REG_BASE + 0x00000324 , data ); + while((data&0x1) !=0x1) { + reg_read (DDR_REG_BASE + 0x00000324 , data ); + } + + + + +reg_write( DDR_REG_BASE + 0x00000304 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000490 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000540 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000005f0 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000006a0 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000750 , 0x00000001 ); + +reg_write( DDR_REG_BASE + 0x0000060 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0000050 , 0x98210000 ); + +} diff --git a/src/little/uboot/board/canaan/k230_canmv_01studio/lpddr4_init_32_swap_2667.c b/src/little/uboot/board/canaan/k230_canmv_01studio/lpddr4_init_32_swap_2667.c new file mode 100755 index 000000000..df514cbe9 --- /dev/null +++ b/src/little/uboot/board/canaan/k230_canmv_01studio/lpddr4_init_32_swap_2667.c @@ -0,0 +1,18668 @@ +/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +//#include +//#include +#define DDR_REG_BASE 0x98000000 + +#define reg_write( addr,v) \ + { \ + (*(volatile uint32_t *)((size_t)(addr))) = (v); \ + } + + +#define reg_read( addr,v) \ + { \ + v =readl ( (const volatile void __iomem *) addr ); \ + } +#define BOOT_REG_BASE (0x91102000) +#define PLL0_CFG0 (BOOT_REG_BASE + 0x0 ) +#define PLL0_CFG1 (BOOT_REG_BASE + 0x4 ) +#define PLL0_CTL (BOOT_REG_BASE + 0x8 ) +#define PLL0_STAT (BOOT_REG_BASE + 0xC ) +#define PLL1_CFG0 (BOOT_REG_BASE + 0x10 ) +#define PLL1_CFG1 (BOOT_REG_BASE + 0x14 ) +#define PLL1_CTL (BOOT_REG_BASE + 0x18 ) +#define PLL1_STAT (BOOT_REG_BASE + 0x1C ) +#define PLL2_CFG0 (BOOT_REG_BASE + 0x20 ) +#define PLL2_CFG1 (BOOT_REG_BASE + 0x24 ) +#define PLL2_CTL (BOOT_REG_BASE + 0x28 ) +#define PLL2_STAT (BOOT_REG_BASE + 0x2C ) +#define PLL3_CFG0 (BOOT_REG_BASE + 0x30 ) +#define PLL3_CFG1 (BOOT_REG_BASE + 0x34 ) +#define PLL3_CTL (BOOT_REG_BASE + 0x38 ) +#define PLL3_STAT (BOOT_REG_BASE + 0x3C ) + +void pd_pll(uint32_t pll_ctl,uint32_t pll_stat) +{ +int rdata; + writel(0x10001,pll_ctl); + rdata=readl(pll_stat); + while( (rdata&0x30) != 0x0){ + rdata=readl(pll_stat); + } +} +void init_pll(uint32_t pll_ctl,uint32_t pll_stat) +{ + int rdata; + writel(0x20002,pll_ctl); + rdata=readl(pll_stat); + while( (rdata & 0x30) != 0x20){ + rdata=readl(pll_stat); + } +} + +uint32_t cfg_pll(int fb_div,int ref_div,int out_div,int pllx_cfg0,int pllx_cfg1,int pllx_ctl,int pllx_stat) +{ + int pll_sta; + int wdata,rdata; + pd_pll(pllx_ctl,pllx_stat); + //writel(( (fb_div/2) | 0x20000),pllx_cfg1 ); + writel(( (fb_div/4) | 0x20000),pllx_cfg1 ); //for minimum long term jitter + writel(( (fb_div & 0x1fff) | ( (ref_div & 0x3f) << 16 ) | ( (out_div & 0xf) << 24) ),pllx_cfg0 ); + init_pll(pllx_ctl,pllx_stat); + +} + +int change_pll_2660(void) +{ + /* enable cache */ + //Note: The recommended value for BWADJ is FBK_DIV/2.Valid values range from 0 to 0xFFF. + //To minimize long-term jitter, using NB=NF/4 is better. NB = BWADJ[11:0] + 1, + //So, BWADJ=(NB-1)=[NF/2 -1] or (NF/4 -1)--minimize long term jitter + + // csi_dcache_enable(); + // csi_icache_enable(); + // printf("Core %d Hello World!\n",1); + // printf("C908 core1 boot success!\n"); + + // cfg_pll( // 760M + // 379, //fb_div=NF-1 + // 2, //ref_div=NR-1 + // 3, //out_div=OD-1 + // PLL2_CFG0, + // PLL2_CFG1, + // PLL2_CTL, + // PLL2_STAT + // ); + + cfg_pll( // 1860Mhz + 110, //fb_div=NF-1 + 0, //ref_div=NR-1 + 0, //out_div=OD-1 + PLL2_CFG0, + PLL2_CFG1, + PLL2_CTL, + PLL2_STAT + ); + + + *(uint32_t*)(0x91100060) = 0x800043fe;//switch ddrc_core_clk source to pll2div4 + //__ASM volatile("wfi"); + udelay(50); + + //sys_exit(0); +} +void ddr_init_2667() +{ +int data; +int train_data=0; + change_pll_2660(); + + //reg_read (0x91100060,data); + // data =data & 0xfffffffd; + // data =data | 0x80000003; + //// data = ( (data>>2)<<2)|0x2; + //// data = data | 0x80000000; + // reg_write(0x91100060,data); + + //reg_read (0x91100060,data); + // data =((data>>2)<<2)|0x2; + // data =data | 0x80000000; + // reg_write(0x91100060,data); + + + reg_read (0x911030a0,data); + data =data | 0x10; + reg_write(0x911030a0,data); + + + + + +reg_write( DDR_REG_BASE + 0x00000304 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000001 ); +reg_read ( DDR_REG_BASE + 0x00000004 , data); +reg_write( DDR_REG_BASE + 0x00000000 , 0x01080020 ); +reg_write( DDR_REG_BASE + 0x00000010 , 0x0000b030 ); +reg_write( DDR_REG_BASE + 0x00000014 , 0x0002ec4d ); +reg_write( DDR_REG_BASE + 0x00000020 , 0x00000202 ); +reg_write( DDR_REG_BASE + 0x00000024 , 0xf491fa51 ); +reg_write( DDR_REG_BASE + 0x00000028 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x0000002c , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000020 ); +reg_write( DDR_REG_BASE + 0x00000034 , 0x00408a04 ); +reg_write( DDR_REG_BASE + 0x00000038 , 0x0e0e0002 ); +reg_write( DDR_REG_BASE + 0x0000003c , 0x00000060 ); +reg_write( DDR_REG_BASE + 0x00000050 , 0x98210000 ); +reg_write( DDR_REG_BASE + 0x00000054 , 0x004b0043 ); +reg_write( DDR_REG_BASE + 0x00000060 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000064 , 0x00510057 ); +reg_write( DDR_REG_BASE + 0x00000068 , 0x00280000 ); +reg_write( DDR_REG_BASE + 0x000000c0 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000000d0 , 0xc0020002 ); +reg_write( DDR_REG_BASE + 0x000000d4 , 0x00010002 ); +reg_write( DDR_REG_BASE + 0x000000d8 , 0x00001600 ); +reg_write( DDR_REG_BASE + 0x000000dc , 0x00440024 ); +reg_write( DDR_REG_BASE + 0x000000e0 , 0x00310008 ); +reg_write( DDR_REG_BASE + 0x000000e4 , 0x00040008 ); +reg_write( DDR_REG_BASE + 0x000000e8 , 0x0000004d ); +reg_write( DDR_REG_BASE + 0x000000ec , 0x0000004d ); +reg_write( DDR_REG_BASE + 0x000000f0 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000000f4 , 0x0000032f ); +reg_write( DDR_REG_BASE + 0x000000f8 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00000100 , 0x171b161c ); +reg_write( DDR_REG_BASE + 0x00000104 , 0x00050528 ); +reg_write( DDR_REG_BASE + 0x00000108 , 0x060c0e12 ); +reg_write( DDR_REG_BASE + 0x0000010c , 0x00a0a006 ); +reg_write( DDR_REG_BASE + 0x00000110 , 0x0c04070c ); +reg_write( DDR_REG_BASE + 0x00000114 , 0x02040a0a ); +reg_write( DDR_REG_BASE + 0x00000118 , 0x01010006 ); +reg_write( DDR_REG_BASE + 0x0000011c , 0x00000402 ); +reg_write( DDR_REG_BASE + 0x00000120 , 0x00000101 ); +reg_write( DDR_REG_BASE + 0x00000130 , 0x00020000 ); +reg_write( DDR_REG_BASE + 0x00000134 , 0x0b100002 ); +reg_write( DDR_REG_BASE + 0x00000138 , 0x0000005c ); +reg_write( DDR_REG_BASE + 0x0000013c , 0x80000000 ); +reg_write( DDR_REG_BASE + 0x00000144 , 0x00860043 ); +reg_write( DDR_REG_BASE + 0x00000180 , 0xc29b0014 ); +reg_write( DDR_REG_BASE + 0x00000184 , 0x0227c42a ); +reg_write( DDR_REG_BASE + 0x00000188 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000190 , 0x03938208 ); +reg_write( DDR_REG_BASE + 0x00000194 , 0x00090202 ); +reg_write( DDR_REG_BASE + 0x00000198 , 0x0710a120 ); +reg_write( DDR_REG_BASE + 0x000001a0 , 0xe0400018 ); +reg_write( DDR_REG_BASE + 0x000001a4 , 0x00020035 ); +reg_write( DDR_REG_BASE + 0x000001a8 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000001b0 , 0x00000015 ); +reg_write( DDR_REG_BASE + 0x000001b4 , 0x00001308 ); +reg_write( DDR_REG_BASE + 0x000001c0 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000001c4 , 0xd1000000 ); +reg_write( DDR_REG_BASE + 0x00000200 , 0x0000001f ); +reg_write( DDR_REG_BASE + 0x00000204 , 0x00080808 ); +reg_write( DDR_REG_BASE + 0x00000208 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0000020c , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000210 , 0x00001f1f ); +reg_write( DDR_REG_BASE + 0x00000214 , 0x070f0707 ); + +//reg_write( DDR_REG_BASE + 0x00000218 , 0x0f0f0f07 ); //2gb, 256MB +//reg_write( DDR_REG_BASE + 0x00000218 , 0x0f0f0707 ); // 4gb,512MB +reg_write( DDR_REG_BASE + 0x00000218 , 0x07070707 ); //16gb,2GB +reg_write( DDR_REG_BASE + 0x0000021c , 0x00000f0f ); +reg_write( DDR_REG_BASE + 0x00000224 , 0x07070707 ); +reg_write( DDR_REG_BASE + 0x00000228 , 0x07070707 ); +reg_write( DDR_REG_BASE + 0x0000022c , 0x00000007 ); +reg_write( DDR_REG_BASE + 0x00000240 , 0x06070944 ); +reg_write( DDR_REG_BASE + 0x00000244 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000250 , 0x804b1f18 ); +reg_write( DDR_REG_BASE + 0x00000254 , 0x00002000 ); +reg_write( DDR_REG_BASE + 0x0000025c , 0x0f000001 ); +reg_write( DDR_REG_BASE + 0x00000264 , 0x0f00007f ); +reg_write( DDR_REG_BASE + 0x0000026c , 0x0f00007f ); +reg_write( DDR_REG_BASE + 0x00000270 , 0x04040208 ); +reg_write( DDR_REG_BASE + 0x00000274 , 0x08400810 ); +reg_write( DDR_REG_BASE + 0x00000300 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000304 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0000030c , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000320 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000328 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0000036c , 0x00000011 ); +reg_write( DDR_REG_BASE + 0x00000490 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000540 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000005f0 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000006a0 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000750 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00002020 , 0x00000202 ); +reg_write( DDR_REG_BASE + 0x00002024 , 0xf491fa51 ); +reg_write( DDR_REG_BASE + 0x00002034 , 0x00408a04 ); +reg_write( DDR_REG_BASE + 0x00002050 , 0xf0210000 ); +reg_write( DDR_REG_BASE + 0x00002064 , 0x00518057 ); +reg_write( DDR_REG_BASE + 0x00002068 , 0x00280000 ); +reg_write( DDR_REG_BASE + 0x000020dc , 0x00440024 ); +reg_write( DDR_REG_BASE + 0x000020e0 , 0x00310008 ); +reg_write( DDR_REG_BASE + 0x000020e8 , 0x0000004d ); +reg_write( DDR_REG_BASE + 0x000020ec , 0x0000004d ); +reg_write( DDR_REG_BASE + 0x000020f4 , 0x0000032f ); +reg_write( DDR_REG_BASE + 0x000020f8 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00002100 , 0x171b161c ); +reg_write( DDR_REG_BASE + 0x00002104 , 0x00050528 ); +reg_write( DDR_REG_BASE + 0x00002108 , 0x060c0e12 ); +reg_write( DDR_REG_BASE + 0x0000210c , 0x00a0a006 ); +reg_write( DDR_REG_BASE + 0x00002110 , 0x0c04070c ); +reg_write( DDR_REG_BASE + 0x00002114 , 0x02040a0a ); +reg_write( DDR_REG_BASE + 0x00002118 , 0x01010006 ); +reg_write( DDR_REG_BASE + 0x0000211c , 0x00000402 ); +reg_write( DDR_REG_BASE + 0x00002120 , 0x00000101 ); +reg_write( DDR_REG_BASE + 0x00002130 , 0x00020000 ); +reg_write( DDR_REG_BASE + 0x00002134 , 0x0b100002 ); +reg_write( DDR_REG_BASE + 0x00002138 , 0x0000005c ); +reg_write( DDR_REG_BASE + 0x0000213c , 0x80000000 ); +reg_write( DDR_REG_BASE + 0x00002144 , 0x00860043 ); +reg_write( DDR_REG_BASE + 0x00002180 , 0xc29b0014 ); +reg_write( DDR_REG_BASE + 0x00002190 , 0x03938208 ); +reg_write( DDR_REG_BASE + 0x00002194 , 0x00090202 ); +reg_write( DDR_REG_BASE + 0x000021b4 , 0x00001308 ); +reg_write( DDR_REG_BASE + 0x00002240 , 0x06070944 ); +reg_write( DDR_REG_BASE + 0x00003020 , 0x00000202 ); +reg_write( DDR_REG_BASE + 0x00003024 , 0xf491fa51 ); +reg_write( DDR_REG_BASE + 0x00003034 , 0x00408a04 ); +reg_write( DDR_REG_BASE + 0x00003050 , 0x48210000 ); +reg_write( DDR_REG_BASE + 0x00003064 , 0x00518057 ); +reg_write( DDR_REG_BASE + 0x00003068 , 0x00280000 ); +reg_write( DDR_REG_BASE + 0x000030dc , 0x00440024 ); +reg_write( DDR_REG_BASE + 0x000030e0 , 0x00310008 ); +reg_write( DDR_REG_BASE + 0x000030e8 , 0x0000004d ); +reg_write( DDR_REG_BASE + 0x000030ec , 0x0000004d ); +reg_write( DDR_REG_BASE + 0x000030f4 , 0x0000032f ); +reg_write( DDR_REG_BASE + 0x000030f8 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00003100 , 0x171b161c ); +reg_write( DDR_REG_BASE + 0x00003104 , 0x00050528 ); +reg_write( DDR_REG_BASE + 0x00003108 , 0x060c0e12 ); +reg_write( DDR_REG_BASE + 0x0000310c , 0x00a0a006 ); +reg_write( DDR_REG_BASE + 0x00003110 , 0x0c04070c ); +reg_write( DDR_REG_BASE + 0x00003114 , 0x02040a0a ); +reg_write( DDR_REG_BASE + 0x00003118 , 0x01010006 ); +reg_write( DDR_REG_BASE + 0x0000311c , 0x00000402 ); +reg_write( DDR_REG_BASE + 0x00003120 , 0x00000101 ); +reg_write( DDR_REG_BASE + 0x00003130 , 0x00020000 ); +reg_write( DDR_REG_BASE + 0x00003134 , 0x0b100002 ); +reg_write( DDR_REG_BASE + 0x00003138 , 0x0000005c ); +reg_write( DDR_REG_BASE + 0x0000313c , 0x80000000 ); +reg_write( DDR_REG_BASE + 0x00003144 , 0x00860043 ); +reg_write( DDR_REG_BASE + 0x00003180 , 0xc29b0014 ); +reg_write( DDR_REG_BASE + 0x00003190 , 0x03938208 ); +reg_write( DDR_REG_BASE + 0x00003194 , 0x00090202 ); +reg_write( DDR_REG_BASE + 0x000031b4 , 0x00001308 ); +reg_write( DDR_REG_BASE + 0x00003240 , 0x06070944 ); +reg_write( DDR_REG_BASE + 0x00004020 , 0x00000202 ); +reg_write( DDR_REG_BASE + 0x00004024 , 0xf491fa51 ); +reg_write( DDR_REG_BASE + 0x00004034 , 0x00408a04 ); +reg_write( DDR_REG_BASE + 0x00004050 , 0x70210000 ); +reg_write( DDR_REG_BASE + 0x00004064 , 0x00510057 ); +reg_write( DDR_REG_BASE + 0x00004068 , 0x00280000 ); +reg_write( DDR_REG_BASE + 0x000040dc , 0x00440024 ); +reg_write( DDR_REG_BASE + 0x000040e0 , 0x00310008 ); +reg_write( DDR_REG_BASE + 0x000040e8 , 0x0000004d ); +reg_write( DDR_REG_BASE + 0x000040ec , 0x0000004d ); +reg_write( DDR_REG_BASE + 0x000040f4 , 0x0000032f ); +reg_write( DDR_REG_BASE + 0x000040f8 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00004100 , 0x171b161c ); +reg_write( DDR_REG_BASE + 0x00004104 , 0x00050528 ); +reg_write( DDR_REG_BASE + 0x00004108 , 0x060c0e12 ); +reg_write( DDR_REG_BASE + 0x0000410c , 0x00a0a006 ); +reg_write( DDR_REG_BASE + 0x00004110 , 0x0c04070c ); +reg_write( DDR_REG_BASE + 0x00004114 , 0x02040a0a ); +reg_write( DDR_REG_BASE + 0x00004118 , 0x01010006 ); +reg_write( DDR_REG_BASE + 0x0000411c , 0x00000402 ); +reg_write( DDR_REG_BASE + 0x00004120 , 0x00000101 ); +reg_write( DDR_REG_BASE + 0x00004130 , 0x00020000 ); +reg_write( DDR_REG_BASE + 0x00004134 , 0x0b100002 ); +reg_write( DDR_REG_BASE + 0x00004138 , 0x0000005c ); +reg_write( DDR_REG_BASE + 0x0000413c , 0x80000000 ); +reg_write( DDR_REG_BASE + 0x00004144 , 0x00860043 ); +reg_write( DDR_REG_BASE + 0x00004180 , 0xc29b0014 ); +reg_write( DDR_REG_BASE + 0x00004190 , 0x03938208 ); +reg_write( DDR_REG_BASE + 0x00004194 , 0x00090202 ); +reg_write( DDR_REG_BASE + 0x000041b4 , 0x00001308 ); +reg_write( DDR_REG_BASE + 0x00004240 , 0x06070944 ); +reg_read ( DDR_REG_BASE + 0x00000060 , data ); +reg_write( DDR_REG_BASE + 0x00000400 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000404 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x000004b4 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x00000564 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x00000614 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x000006c4 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x00000404 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000004b4 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000564 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000614 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000006c4 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000404 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000004b4 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000564 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000614 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000006c4 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000404 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x000004b4 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x00000564 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x00000614 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x000006c4 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x00000408 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x000004b8 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x00000568 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x00000618 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x000006c8 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x00000408 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000004b8 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000568 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000618 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000006c8 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000408 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000004b8 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000568 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000618 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000006c8 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000408 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x000004b8 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x00000568 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x00000618 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x000006c8 , 0x0000100f ); +reg_read ( DDR_REG_BASE + 0x00000030 , data ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000020 ); + + + +reg_read ( 0x9110309c, data ); + data=data|0x00020000; +reg_write ( 0x9110309c, data ); + + +reg_write( DDR_REG_BASE + 0x00000304 , 0x00000000 ); +reg_read ( DDR_REG_BASE + 0x00000030 , data ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000020 ); +reg_read ( DDR_REG_BASE + 0x00000030 , data ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000020 ); +reg_read ( DDR_REG_BASE + 0x000001c4 , data ); +reg_write( DDR_REG_BASE + 0x000001c4 , 0xd1000000 ); +reg_write( DDR_REG_BASE + 0x00000320 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000001b0 , 0x00000014 ); +reg_write( DDR_REG_BASE + 0x000001b0 , 0x00000014 ); +reg_write( DDR_REG_BASE + 0x00000304 , 0x00000002 ); +reg_read ( DDR_REG_BASE + 0x000000d0 , data ); +reg_read ( DDR_REG_BASE + 0x000001c0 , data ); +reg_read ( DDR_REG_BASE + 0x00000000 , data ); +reg_read ( DDR_REG_BASE + 0x000000dc , data ); +reg_read ( DDR_REG_BASE + 0x000000dc , data ); +reg_read ( DDR_REG_BASE + 0x000000e0 , data ); +reg_read ( DDR_REG_BASE + 0x000000e8 , data ); +reg_read ( DDR_REG_BASE + 0x000000e8 , data ); +reg_read ( DDR_REG_BASE + 0x000000e0 , data ); +reg_read ( DDR_REG_BASE + 0x000000ec , data ); +reg_read ( DDR_REG_BASE + 0x000000ec , data ); +reg_read ( DDR_REG_BASE + 0x000000d0 , data ); +reg_read ( DDR_REG_BASE + 0x000001c0 , data ); +reg_read ( DDR_REG_BASE + 0x00000000 , data ); +reg_read ( DDR_REG_BASE + 0x000000dc , data ); +reg_read ( DDR_REG_BASE + 0x000000dc , data ); +reg_read ( DDR_REG_BASE + 0x000000e0 , data ); +reg_read ( DDR_REG_BASE + 0x000000e8 , data ); +reg_read ( DDR_REG_BASE + 0x000000e8 , data ); +reg_read ( DDR_REG_BASE + 0x000000e0 , data ); +reg_read ( DDR_REG_BASE + 0x000000ec , data ); +reg_read ( DDR_REG_BASE + 0x000000ec , data ); +reg_read ( DDR_REG_BASE + 0x000000d0 , data ); + + +//reg_write( DDR_REG_BASE +0x1005f*4+0x02000000,0x1ff); +//reg_write( DDR_REG_BASE +0x1015f*4+0x02000000,0x1ff); +//reg_write( DDR_REG_BASE +0x1105f*4+0x02000000,0x1ff); +//reg_write( DDR_REG_BASE +0x1115f*4+0x02000000,0x1ff); +//reg_write( DDR_REG_BASE +0x1205f*4+0x02000000,0x1ff); +//reg_write( DDR_REG_BASE +0x1215f*4+0x02000000,0x1ff); +//reg_write( DDR_REG_BASE +0x1305f*4+0x02000000,0x1ff); +//reg_write( DDR_REG_BASE +0x1315f*4+0x02000000,0x1ff); +//reg_write( DDR_REG_BASE +0x55*4+0x02000000,0x1ff); +//reg_write( DDR_REG_BASE +0x1055*4+0x02000000,0x1ff); +//reg_write( DDR_REG_BASE +0x2055*4+0x02000000,0x1ff); +//reg_write( DDR_REG_BASE +0x3055*4+0x02000000,0x1ff); +//reg_write( DDR_REG_BASE +0x4055*4+0x02000000,0x1ff); +//reg_write( DDR_REG_BASE +0x5055*4+0x02000000,0x1ff); +//reg_write( DDR_REG_BASE +0x6055*4+0x02000000,0x1ff); +//reg_write( DDR_REG_BASE +0x7055*4+0x02000000,0x1ff); +//reg_write( DDR_REG_BASE +0x8055*4+0x02000000,0x1ff); +//reg_write( DDR_REG_BASE +0x9055*4+0x02000000,0x1ff); +//reg_write( DDR_REG_BASE +0x200c5*4+0x02000000,0x19); +reg_write( DDR_REG_BASE + 0x0002002e*4+0x02000000 , 0x00000002 ); +reg_write( DDR_REG_BASE + 0x00090204*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00020024*4+0x02000000 , 0x000000a3 ); +reg_write( DDR_REG_BASE + 0x0002003a*4+0x02000000 , 0x00000002 ); +reg_write( DDR_REG_BASE + 0x0002007d*4+0x02000000 , 0x00000212 ); +reg_write( DDR_REG_BASE + 0x0002007c*4+0x02000000 , 0x00000061 ); +reg_write( DDR_REG_BASE + 0x00020056*4+0x02000000 , 0x00000003 ); + +//iteration place +//PHY RX ODT +//0010_00 00_0000 0x208 0x200 Down:120 +//0010_10 00_0000 0x28a 0x280 Down:80 +//0110_00 00_0000 0x618 0x600 Down:60 +//0110_10 00_0000 0x69a 0x680 Down:48 +//1110_00 00_0000 0xe38 0xe00 Down:40 +//1110_10 00_0000 0xeba 0xe80 Down:34.3 + +reg_write( DDR_REG_BASE + 0x0001004d*4+0x02000000 , 0x00000600 ); +reg_write( DDR_REG_BASE + 0x0001014d*4+0x02000000 , 0x00000600 ); +reg_write( DDR_REG_BASE + 0x0001104d*4+0x02000000 , 0x00000600 ); +reg_write( DDR_REG_BASE + 0x0001114d*4+0x02000000 , 0x00000600 ); +reg_write( DDR_REG_BASE + 0x0001204d*4+0x02000000 , 0x00000600 ); +reg_write( DDR_REG_BASE + 0x0001214d*4+0x02000000 , 0x00000600 ); +reg_write( DDR_REG_BASE + 0x0001304d*4+0x02000000 , 0x00000600 ); +reg_write( DDR_REG_BASE + 0x0001314d*4+0x02000000 , 0x00000600 ); + +//iteration place +//PHY TX output impedence +//0010_00 00_1000 0x208 Pullup/Down:120 +//0010_10 00_1010 0x28a Pullup/Down:80 +//0110_00 01_1000 0x618 Pullup/Down:60 +//0110_10 01_1010 0x69a Pullup/Down:48 +//1110_00 11_1000 0xe38 Pullup/Down:40 +//1110_10 11_1010 0xeba Pullup/Down:34.3 +reg_write( DDR_REG_BASE + 0x00010049*4 +0x02000000 , 0x00000e38 ); +reg_write( DDR_REG_BASE + 0x00010149*4 +0x02000000 , 0x00000e38 ); +reg_write( DDR_REG_BASE + 0x00011049*4 +0x02000000 , 0x00000e38 ); +reg_write( DDR_REG_BASE + 0x00011149*4 +0x02000000 , 0x00000e38 ); +reg_write( DDR_REG_BASE + 0x00012049*4 +0x02000000 , 0x00000e38 ); +reg_write( DDR_REG_BASE + 0x00012149*4 +0x02000000 , 0x00000e38 ); +reg_write( DDR_REG_BASE + 0x00013049*4 +0x02000000 , 0x00000e38 ); +reg_write( DDR_REG_BASE + 0x00013149*4 +0x02000000 , 0x00000e38 ); + + +//iteration +// PHY AC/CLK output impedence +//00000_00000 0x0 120 +//00001_00001 0x21 60 +//00011_00011 0x63 40 +//00111_00111 0xe7 30 +//01111_01111 0x1ef 24 +//11111_11111 0x3ff 20 + +// // [phyinit_C_initPhyConfig] Programming ATxImpedance::ADrvStrenP to 0x1 +// // [phyinit_C_initPhyConfig] Programming ATxImpedance::ADrvStrenN to 0x1 +reg_write( DDR_REG_BASE + 0x00000043*4 +0x02000000 , 0x0003ff ); +reg_write( DDR_REG_BASE + 0x00001043*4 +0x02000000 , 0x0003ff ); +reg_write( DDR_REG_BASE + 0x00002043*4 +0x02000000 , 0x0003ff ); +reg_write( DDR_REG_BASE + 0x00003043*4 +0x02000000 , 0x0003ff ); +reg_write( DDR_REG_BASE + 0x00004043*4 +0x02000000 , 0x0003ff ); +reg_write( DDR_REG_BASE + 0x00005043*4 +0x02000000 , 0x0003ff ); +reg_write( DDR_REG_BASE + 0x00006043*4 +0x02000000 , 0x0003ff ); +reg_write( DDR_REG_BASE + 0x00007043*4 +0x02000000 , 0x0003ff ); +reg_write( DDR_REG_BASE + 0x00008043*4 +0x02000000 , 0x0003ff ); +reg_write( DDR_REG_BASE + 0x00009043*4 +0x02000000 , 0x0003ff ); + +reg_write( DDR_REG_BASE + 0x00020018*4+0x02000000 , 0x00000003 ); +reg_write( DDR_REG_BASE + 0x00020075*4+0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00020050*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE +0x20008*4+0x02000000,0x29b); +reg_write( DDR_REG_BASE + 0x00020088*4+0x02000000 , 0x00000009 ); + +//iteration place +//PHY VERF +// 0x104 15% (0x14) +// 0x14c 20% (0x1a) +// 0x19c 25% (0x20) +// 0x1e4 30% (0x26) +// 0x284 40% (0x33) + +// // [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal::GlobalVrefInDAC to 0x51 +// // [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal to 0x288 +reg_write( DDR_REG_BASE + 0x000200b2*4 +0x02000000 , 0x0000014c ); + + + +reg_write( DDR_REG_BASE + 0x00010043*4+0x02000000 , 0x000005a1 ); +reg_write( DDR_REG_BASE + 0x00010143*4+0x02000000 , 0x000005a1 ); +reg_write( DDR_REG_BASE + 0x00011043*4+0x02000000 , 0x000005a1 ); +reg_write( DDR_REG_BASE + 0x00011143*4+0x02000000 , 0x000005a1 ); +reg_write( DDR_REG_BASE + 0x00012043*4+0x02000000 , 0x000005a1 ); +reg_write( DDR_REG_BASE + 0x00012143*4+0x02000000 , 0x000005a1 ); +reg_write( DDR_REG_BASE + 0x00013043*4+0x02000000 , 0x000005a1 ); +reg_write( DDR_REG_BASE + 0x00013143*4+0x02000000 , 0x000005a1 ); +reg_write( DDR_REG_BASE + 0x000200fa*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00020019*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000200f0*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000200f1*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000200f2*4+0x02000000 , 0x00004444 ); +reg_write( DDR_REG_BASE + 0x000200f3*4+0x02000000 , 0x00008888 ); +reg_write( DDR_REG_BASE + 0x000200f4*4+0x02000000 , 0x00005555 ); +reg_write( DDR_REG_BASE + 0x000200f5*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000200f6*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000200f7*4+0x02000000 , 0x0000f000 ); +reg_write( DDR_REG_BASE + 0x0001004a*4+0x02000000 , 0x00000500 ); +reg_write( DDR_REG_BASE + 0x0001104a*4+0x02000000 , 0x00000500 ); +reg_write( DDR_REG_BASE + 0x0001204a*4+0x02000000 , 0x00000500 ); +reg_write( DDR_REG_BASE + 0x0001304a*4+0x02000000 , 0x00000500 ); +reg_write( DDR_REG_BASE + 0x00020025*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0002002d*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0002002c*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00010020*4+0x02000000 , 0x00000006 ); +reg_write( DDR_REG_BASE + 0x00011020*4+0x02000000 , 0x00000006 ); +reg_write( DDR_REG_BASE + 0x00012020*4+0x02000000 , 0x00000006 ); +reg_write( DDR_REG_BASE + 0x00013020*4+0x02000000 , 0x00000006 ); +reg_write( DDR_REG_BASE + 0x00020020*4+0x02000000 , 0x00000006 ); +reg_write( DDR_REG_BASE + 0x000100d0*4+0x02000000 , 0x00000100 ); +reg_write( DDR_REG_BASE + 0x000101d0*4+0x02000000 , 0x00000100 ); +reg_write( DDR_REG_BASE + 0x000110d0*4+0x02000000 , 0x00000100 ); +reg_write( DDR_REG_BASE + 0x000111d0*4+0x02000000 , 0x00000100 ); +reg_write( DDR_REG_BASE + 0x000120d0*4+0x02000000 , 0x00000100 ); +reg_write( DDR_REG_BASE + 0x000121d0*4+0x02000000 , 0x00000100 ); +reg_write( DDR_REG_BASE + 0x000130d0*4+0x02000000 , 0x00000100 ); +reg_write( DDR_REG_BASE + 0x000131d0*4+0x02000000 , 0x00000100 ); +reg_write( DDR_REG_BASE + 0x000100c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000101c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000102c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000103c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000104c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000105c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000106c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000107c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000108c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000110c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000111c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000112c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000113c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000114c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000115c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000116c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000117c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000118c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000120c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000121c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000122c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000123c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000124c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000125c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000126c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000127c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000128c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000130c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000131c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000132c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000133c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000134c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000135c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000136c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000137c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x000138c0*4+0x02000000 , 0x00000057 ); +reg_write( DDR_REG_BASE + 0x00010080*4+0x02000000 , 0x00000318 ); +reg_write( DDR_REG_BASE + 0x00010180*4+0x02000000 , 0x00000318 ); +reg_write( DDR_REG_BASE + 0x00011080*4+0x02000000 , 0x00000318 ); +reg_write( DDR_REG_BASE + 0x00011180*4+0x02000000 , 0x00000318 ); +reg_write( DDR_REG_BASE + 0x00012080*4+0x02000000 , 0x00000318 ); +reg_write( DDR_REG_BASE + 0x00012180*4+0x02000000 , 0x00000318 ); +reg_write( DDR_REG_BASE + 0x00013080*4+0x02000000 , 0x00000318 ); +reg_write( DDR_REG_BASE + 0x00013180*4+0x02000000 , 0x00000318 ); +reg_write( DDR_REG_BASE + 0x00090201*4+0x02000000 , 0x00001600 ); +reg_write( DDR_REG_BASE + 0x00090202*4+0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x00090203*4+0x02000000 , 0x00002200 ); +reg_write( DDR_REG_BASE + 0x00020072*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00020073*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000100ae*4+0x02000000 , 0x00000027 ); +reg_write( DDR_REG_BASE + 0x000110ae*4+0x02000000 , 0x00000027 ); +reg_write( DDR_REG_BASE + 0x000120ae*4+0x02000000 , 0x00000027 ); +reg_write( DDR_REG_BASE + 0x000130ae*4+0x02000000 , 0x00000027 ); +reg_write( DDR_REG_BASE + 0x000100af*4+0x02000000 , 0x00000027 ); +reg_write( DDR_REG_BASE + 0x000110af*4+0x02000000 , 0x00000027 ); +reg_write( DDR_REG_BASE + 0x000120af*4+0x02000000 , 0x00000027 ); +reg_write( DDR_REG_BASE + 0x000130af*4+0x02000000 , 0x00000027 ); +reg_write( DDR_REG_BASE + 0x000100aa*4+0x02000000 , 0x00000501 ); +reg_write( DDR_REG_BASE + 0x000110aa*4+0x02000000 , 0x0000050d ); +reg_write( DDR_REG_BASE + 0x000120aa*4+0x02000000 , 0x00000501 ); +reg_write( DDR_REG_BASE + 0x000130aa*4+0x02000000 , 0x0000050d ); +reg_write( DDR_REG_BASE + 0x00020077*4+0x02000000 , 0x00000034 ); +reg_write( DDR_REG_BASE + 0x0002007c*4+0x02000000 , 0x00000054 ); +reg_write( DDR_REG_BASE + 0x0002007d*4+0x02000000 , 0x000004b2 ); +reg_write( DDR_REG_BASE + 0x000400c0*4+0x02000000 , 0x0000010f ); +reg_write( DDR_REG_BASE + 0x000200cb*4+0x02000000 , 0x000061f0 ); +reg_write( DDR_REG_BASE + 0x00020060*4+0x02000000 , 0x00000002 ); + +//swap +reg_write( DDR_REG_BASE + 0x20100*4+0x02000000,0x5); //CA0 +reg_write( DDR_REG_BASE + 0x20101*4+0x02000000,0x4); //CA1 +reg_write( DDR_REG_BASE + 0x20102*4+0x02000000,0x3); //CA2 +reg_write( DDR_REG_BASE + 0x20103*4+0x02000000,0x2); //CA3 +reg_write( DDR_REG_BASE + 0x20104*4+0x02000000,0x1); //CA4 +reg_write( DDR_REG_BASE + 0x20105*4+0x02000000,0x0); //CA5 + +reg_write( DDR_REG_BASE + 0x110a0*4+0x02000000,0x4); // +reg_write( DDR_REG_BASE + 0x110a1*4+0x02000000,0x7); // +reg_write( DDR_REG_BASE + 0x110a2*4+0x02000000,0x6); // +reg_write( DDR_REG_BASE + 0x110a3*4+0x02000000,0x0); // +reg_write( DDR_REG_BASE + 0x110a4*4+0x02000000,0x2); // +reg_write( DDR_REG_BASE + 0x110a5*4+0x02000000,0x1); // +reg_write( DDR_REG_BASE + 0x110a6*4+0x02000000,0x5); // +reg_write( DDR_REG_BASE + 0x110a7*4+0x02000000,0x3); // + +//reg_write( DDR_REG_BASE + 0x110a0*4+0x02000000,0x4); //lndq =1 +//reg_write( DDR_REG_BASE + 0x110a1*4+0x02000000,0x1); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x110a2*4+0x02000000,0x7); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x110a3*4+0x02000000,0x0); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x110a4*4+0x02000000,0x2); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x110a5*4+0x02000000,0x3); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x110a6*4+0x02000000,0x6); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x110a7*4+0x02000000,0x5); //CA1 =0 + +reg_write( DDR_REG_BASE + 0x130a0*4+0x02000000,0x3); // +reg_write( DDR_REG_BASE + 0x130a1*4+0x02000000,0x4); // +reg_write( DDR_REG_BASE + 0x130a2*4+0x02000000,0x0); // +reg_write( DDR_REG_BASE + 0x130a3*4+0x02000000,0x2); // +reg_write( DDR_REG_BASE + 0x130a4*4+0x02000000,0x1); // +reg_write( DDR_REG_BASE + 0x130a5*4+0x02000000,0x5); // +reg_write( DDR_REG_BASE + 0x130a6*4+0x02000000,0x6); // +reg_write( DDR_REG_BASE + 0x130a7*4+0x02000000,0x7); // + +//reg_write( DDR_REG_BASE + 0x130a0*4+0x02000000,0x3); //lndq =1 +//reg_write( DDR_REG_BASE + 0x130a1*4+0x02000000,0x0); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x130a2*4+0x02000000,0x2); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x130a3*4+0x02000000,0x1); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x130a4*4+0x02000000,0x6); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x130a5*4+0x02000000,0x7); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x130a6*4+0x02000000,0x5); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x130a7*4+0x02000000,0x4); //CA1 =0 + +reg_write( DDR_REG_BASE + 0x120a0*4+0x02000000,0x3); // +reg_write( DDR_REG_BASE + 0x120a1*4+0x02000000,0x0); // +reg_write( DDR_REG_BASE + 0x120a2*4+0x02000000,0x2); // +reg_write( DDR_REG_BASE + 0x120a3*4+0x02000000,0x5); // +reg_write( DDR_REG_BASE + 0x120a4*4+0x02000000,0x4); // +reg_write( DDR_REG_BASE + 0x120a5*4+0x02000000,0x1); // +reg_write( DDR_REG_BASE + 0x120a6*4+0x02000000,0x7); // +reg_write( DDR_REG_BASE + 0x120a7*4+0x02000000,0x6); // + + + + +reg_write( DDR_REG_BASE + 0xd0000*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50000*4+0x02000000,0x114); +reg_write( DDR_REG_BASE +0x50001*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50002*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50003*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50004*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50005*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50006*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50007*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50008*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50009*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5000a*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5000b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5000c*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5000d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5000e*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5000f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50010*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50011*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50012*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50013*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50014*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50015*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50016*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50017*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50018*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50019*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5001a*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5001b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5001c*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5001d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5001e*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5001f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50020*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50021*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50022*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50023*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50024*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50025*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50026*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50027*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50028*4+0x02000000,0x2069); +reg_write( DDR_REG_BASE +0x50029*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x5002a*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x5002b*4+0x02000000,0x7000); +reg_write( DDR_REG_BASE +0x5002c*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x5002d*4+0x02000000,0x7000); +reg_write( DDR_REG_BASE +0x5002e*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x5002f*4+0x02000000,0x7000); +reg_write( DDR_REG_BASE +0x50030*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50031*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50032*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50033*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50034*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50035*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50036*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50037*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50038*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50039*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50040*4+0x02000000,0x7054); +reg_write( DDR_REG_BASE +0x50041*4+0x02000000,0x7ce0); +reg_write( DDR_REG_BASE +0x50042*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x50043*4+0x02000000,0x1101); +reg_write( DDR_REG_BASE +0x50044*4+0x02000000,0x48c); +reg_write( DDR_REG_BASE +0x50045*4+0x02000000,0x2242); +reg_write( DDR_REG_BASE +0x50046*4+0x02000000,0x8042); +reg_write( DDR_REG_BASE +0x50047*4+0x02000000,0x1b01); +reg_write( DDR_REG_BASE +0x50048*4+0x02000000,0x312); +reg_write( DDR_REG_BASE +0x50049*4+0x02000000,0xf5fb); +reg_write( DDR_REG_BASE +0x5004a*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5004b*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5004c*4+0x02000000,0xc4e1); +reg_write( DDR_REG_BASE +0x5004d*4+0x02000000,0x240a); +reg_write( DDR_REG_BASE +0x5004e*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x5004f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50050*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x50051*4+0x02000000,0xc19); +reg_write( DDR_REG_BASE +0x50052*4+0x02000000,0x1703); +reg_write( DDR_REG_BASE +0x50053*4+0x02000000,0x240a); +reg_write( DDR_REG_BASE +0x50054*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x50055*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50056*4+0x02000000,0x4000); +reg_write( DDR_REG_BASE +0x50057*4+0x02000000,0xc0d); +reg_write( DDR_REG_BASE +0x50058*4+0x02000000,0x1702); +reg_write( DDR_REG_BASE +0x50059*4+0x02000000,0xc4c1); +reg_write( DDR_REG_BASE +0x5005a*4+0x02000000,0x2020); +reg_write( DDR_REG_BASE +0x5005b*4+0x02000000,0x7c0); +reg_write( DDR_REG_BASE +0x5005c*4+0x02000000,0x7fff); +reg_write( DDR_REG_BASE +0x5005d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5005e*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5005f*4+0x02000000,0xb3c8); +reg_write( DDR_REG_BASE +0x50060*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50061*4+0x02000000,0xb388); +reg_write( DDR_REG_BASE +0x50062*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50063*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50064*4+0x02000000,0xb348); +reg_write( DDR_REG_BASE +0x50065*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50066*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50067*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50068*4+0x02000000,0x748d); +reg_write( DDR_REG_BASE +0x50069*4+0x02000000,0xdd0c); +reg_write( DDR_REG_BASE +0x5006a*4+0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x5006b*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5006c*4+0x02000000,0x748d); +reg_write( DDR_REG_BASE +0x5006d*4+0x02000000,0xdd08); +reg_write( DDR_REG_BASE +0x5006e*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x5006f*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50070*4+0x02000000,0x748d); +reg_write( DDR_REG_BASE +0x50071*4+0x02000000,0x74ad); +reg_write( DDR_REG_BASE +0x50072*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x50073*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50074*4+0x02000000,0x748d); +reg_write( DDR_REG_BASE +0x50075*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x50076*4+0x02000000,0xc702); +reg_write( DDR_REG_BASE +0x50077*4+0x02000000,0xc601); +reg_write( DDR_REG_BASE +0x50078*4+0x02000000,0x24b0); +reg_write( DDR_REG_BASE +0x50079*4+0x02000000,0x334d); +reg_write( DDR_REG_BASE +0x5007a*4+0x02000000,0x24b0); +reg_write( DDR_REG_BASE +0x5007b*4+0x02000000,0x331f); +reg_write( DDR_REG_BASE +0x5007c*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5007d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5007e*4+0x02000000,0x2244); +reg_write( DDR_REG_BASE +0x5007f*4+0x02000000,0x8ffc); +reg_write( DDR_REG_BASE +0x50080*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x50081*4+0x02000000,0x7000); +reg_write( DDR_REG_BASE +0x50082*4+0x02000000,0x20e8); +reg_write( DDR_REG_BASE +0x50083*4+0x02000000,0x1a2); +reg_write( DDR_REG_BASE +0x50084*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x50085*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50086*4+0x02000000,0x212f); +reg_write( DDR_REG_BASE +0x50087*4+0x02000000,0x4b); +reg_write( DDR_REG_BASE +0x50088*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50089*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5008a*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5008b*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5008c*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x5008d*4+0x02000000,0x704d); +reg_write( DDR_REG_BASE +0x5008e*4+0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x5008f*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x50090*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50091*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x50092*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x50093*4+0x02000000,0x206a); +reg_write( DDR_REG_BASE +0x50094*4+0x02000000,0x280); +reg_write( DDR_REG_BASE +0x50095*4+0x02000000,0xb88d); +reg_write( DDR_REG_BASE +0x50096*4+0x02000000,0x2029); +reg_write( DDR_REG_BASE +0x50097*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50098*4+0x02000000,0x44db); +reg_write( DDR_REG_BASE +0x50099*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5009a*4+0x02000000,0x4000); +reg_write( DDR_REG_BASE +0x5009b*4+0x02000000,0x42db); +reg_write( DDR_REG_BASE +0x5009c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5009d*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x5009e*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x5009f*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x500a0*4+0x02000000,0x2022); +reg_write( DDR_REG_BASE +0x500a1*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x500a2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x500a3*4+0x02000000,0x3294); +reg_write( DDR_REG_BASE +0x500a4*4+0x02000000,0x2069); +reg_write( DDR_REG_BASE +0x500a5*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x500a6*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x500a7*4+0x02000000,0xf1fe); +reg_write( DDR_REG_BASE +0x500a8*4+0x02000000,0xc3e1); +reg_write( DDR_REG_BASE +0x500a9*4+0x02000000,0xc2e1); +reg_write( DDR_REG_BASE +0x500aa*4+0x02000000,0xc1e1); +reg_write( DDR_REG_BASE +0x500ab*4+0x02000000,0xc0e1); +reg_write( DDR_REG_BASE +0x500ac*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x500ad*4+0x02000000,0xc5e1); +reg_write( DDR_REG_BASE +0x500ae*4+0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x500af*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x500b0*4+0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x500b1*4+0x02000000,0xdc14); +reg_write( DDR_REG_BASE +0x500b2*4+0x02000000,0x77f); +reg_write( DDR_REG_BASE +0x500b3*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x500b4*4+0x02000000,0xda25); +reg_write( DDR_REG_BASE +0x500b5*4+0x02000000,0xba9f); +reg_write( DDR_REG_BASE +0x500b6*4+0x02000000,0x8a60); +reg_write( DDR_REG_BASE +0x500b7*4+0x02000000,0x1233); +reg_write( DDR_REG_BASE +0x500b8*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x500b9*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x500ba*4+0x02000000,0x1aea); +reg_write( DDR_REG_BASE +0x500bb*4+0x02000000,0x8002); +reg_write( DDR_REG_BASE +0x500bc*4+0x02000000,0x12ed); +reg_write( DDR_REG_BASE +0x500bd*4+0x02000000,0x8080); +reg_write( DDR_REG_BASE +0x500be*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x500bf*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x500c0*4+0x02000000,0xf20d); +reg_write( DDR_REG_BASE +0x500c1*4+0x02000000,0xc085); +reg_write( DDR_REG_BASE +0x500c2*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x500c3*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x500c4*4+0x02000000,0x872); +reg_write( DDR_REG_BASE +0x500c5*4+0x02000000,0x360); +reg_write( DDR_REG_BASE +0x500c6*4+0x02000000,0xc185); +reg_write( DDR_REG_BASE +0x500c7*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x500c8*4+0x02000000,0x402); +reg_write( DDR_REG_BASE +0x500c9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x500ca*4+0x02000000,0xd2a); +reg_write( DDR_REG_BASE +0x500cb*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x500cc*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x500cd*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x500ce*4+0x02000000,0xc86); +reg_write( DDR_REG_BASE +0x500cf*4+0x02000000,0x2e0); +reg_write( DDR_REG_BASE +0x500d0*4+0x02000000,0x1a09); +reg_write( DDR_REG_BASE +0x500d1*4+0x02000000,0x3003); +reg_write( DDR_REG_BASE +0x500d2*4+0x02000000,0xfb6); +reg_write( DDR_REG_BASE +0x500d3*4+0x02000000,0x320); +reg_write( DDR_REG_BASE +0x500d4*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x500d5*4+0x02000000,0x25ab); +reg_write( DDR_REG_BASE +0x500d6*4+0x02000000,0x10c4); +reg_write( DDR_REG_BASE +0x500d7*4+0x02000000,0x7fff); +reg_write( DDR_REG_BASE +0x500d8*4+0x02000000,0xf1ff); +reg_write( DDR_REG_BASE +0x500d9*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x500da*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x500db*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x500dc*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x500dd*4+0x02000000,0xc1a6); +reg_write( DDR_REG_BASE +0x500de*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x500df*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x500e0*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x500e1*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x500e2*4+0x02000000,0xc243); +reg_write( DDR_REG_BASE +0x500e3*4+0x02000000,0xa0c0); +reg_write( DDR_REG_BASE +0x500e4*4+0x02000000,0xd83f); +reg_write( DDR_REG_BASE +0x500e5*4+0x02000000,0xc064); +reg_write( DDR_REG_BASE +0x500e6*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x500e7*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x500e8*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x500e9*4+0x02000000,0x88a0); +reg_write( DDR_REG_BASE +0x500ea*4+0x02000000,0x1c11); +reg_write( DDR_REG_BASE +0x500eb*4+0x02000000,0x3382); +reg_write( DDR_REG_BASE +0x500ec*4+0x02000000,0xf054); +reg_write( DDR_REG_BASE +0x500ed*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x500ee*4+0x02000000,0x89d); +reg_write( DDR_REG_BASE +0x500ef*4+0x02000000,0x6ee); +reg_write( DDR_REG_BASE +0x500f0*4+0x02000000,0xc084); +reg_write( DDR_REG_BASE +0x500f1*4+0x02000000,0x60c8); +reg_write( DDR_REG_BASE +0x500f2*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x500f3*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x500f4*4+0x02000000,0xd83f); +reg_write( DDR_REG_BASE +0x500f5*4+0x02000000,0xb19); +reg_write( DDR_REG_BASE +0x500f6*4+0x02000000,0x30b0); +reg_write( DDR_REG_BASE +0x500f7*4+0x02000000,0x7826); +reg_write( DDR_REG_BASE +0x500f8*4+0x02000000,0xb19); +reg_write( DDR_REG_BASE +0x500f9*4+0x02000000,0x3070); +reg_write( DDR_REG_BASE +0x500fa*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x500fb*4+0x02000000,0xb1d); +reg_write( DDR_REG_BASE +0x500fc*4+0x02000000,0x3031); +reg_write( DDR_REG_BASE +0x500fd*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x500fe*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x500ff*4+0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x50100*4+0x02000000,0xc300); +reg_write( DDR_REG_BASE +0x50101*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x50102*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x50103*4+0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x50104*4+0x02000000,0xc200); +reg_write( DDR_REG_BASE +0x50105*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x50106*4+0x02000000,0xb42); +reg_write( DDR_REG_BASE +0x50107*4+0x02000000,0x380); +reg_write( DDR_REG_BASE +0x50108*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50109*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5010a*4+0x02000000,0x4e20); +reg_write( DDR_REG_BASE +0x5010b*4+0x02000000,0xeca); +reg_write( DDR_REG_BASE +0x5010c*4+0x02000000,0x1a0); +reg_write( DDR_REG_BASE +0x5010d*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5010e*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x5010f*4+0x02000000,0xf026); +reg_write( DDR_REG_BASE +0x50110*4+0x02000000,0x255f); +reg_write( DDR_REG_BASE +0x50111*4+0x02000000,0x1402); +reg_write( DDR_REG_BASE +0x50112*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50113*4+0x02000000,0x7a16); +reg_write( DDR_REG_BASE +0x50114*4+0x02000000,0x62f8); +reg_write( DDR_REG_BASE +0x50115*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x50116*4+0x02000000,0x8824); +reg_write( DDR_REG_BASE +0x50117*4+0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x50118*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50119*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5011a*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x5011b*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5011c*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5011d*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x5011e*4+0x02000000,0x54); +reg_write( DDR_REG_BASE +0x5011f*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x50120*4+0x02000000,0xcc2); +reg_write( DDR_REG_BASE +0x50121*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50122*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x50123*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x50124*4+0x02000000,0xb8c5); +reg_write( DDR_REG_BASE +0x50125*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x50126*4+0x02000000,0x7907); +reg_write( DDR_REG_BASE +0x50127*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x50128*4+0x02000000,0x3200); +reg_write( DDR_REG_BASE +0x50129*4+0x02000000,0x4220); +reg_write( DDR_REG_BASE +0x5012a*4+0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x5012b*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x5012c*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x5012d*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x5012e*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x5012f*4+0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x50130*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x50131*4+0x02000000,0x8020); +reg_write( DDR_REG_BASE +0x50132*4+0x02000000,0x7945); +reg_write( DDR_REG_BASE +0x50133*4+0x02000000,0xa020); +reg_write( DDR_REG_BASE +0x50134*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50135*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50136*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50137*4+0x02000000,0x784); +reg_write( DDR_REG_BASE +0x50138*4+0x02000000,0x78b4); +reg_write( DDR_REG_BASE +0x50139*4+0x02000000,0x6028); +reg_write( DDR_REG_BASE +0x5013a*4+0x02000000,0xfad); +reg_write( DDR_REG_BASE +0x5013b*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5013c*4+0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x5013d*4+0x02000000,0xb63); +reg_write( DDR_REG_BASE +0x5013e*4+0x02000000,0xb0d4); +reg_write( DDR_REG_BASE +0x5013f*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x50140*4+0x02000000,0xefb); +reg_write( DDR_REG_BASE +0x50141*4+0x02000000,0x90b4); +reg_write( DDR_REG_BASE +0x50142*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x50143*4+0x02000000,0xc0a6); +reg_write( DDR_REG_BASE +0x50144*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50145*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50146*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50147*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50148*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50149*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5014a*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5014b*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x5014c*4+0x02000000,0x320d); +reg_write( DDR_REG_BASE +0x5014d*4+0x02000000,0x216f); +reg_write( DDR_REG_BASE +0x5014e*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x5014f*4+0x02000000,0x1154); +reg_write( DDR_REG_BASE +0x50150*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x50151*4+0x02000000,0x89a0); +reg_write( DDR_REG_BASE +0x50152*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x50153*4+0x02000000,0x1121); +reg_write( DDR_REG_BASE +0x50154*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x50155*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x50156*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x50157*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50158*4+0x02000000,0x334); +reg_write( DDR_REG_BASE +0x50159*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x5015a*4+0x02000000,0xe5a); +reg_write( DDR_REG_BASE +0x5015b*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x5015c*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5015d*4+0x02000000,0xc09c); +reg_write( DDR_REG_BASE +0x5015e*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5015f*4+0x02000000,0xc089); +reg_write( DDR_REG_BASE +0x50160*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x50161*4+0x02000000,0x3d41); +reg_write( DDR_REG_BASE +0x50162*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x50163*4+0x02000000,0x3f82); +reg_write( DDR_REG_BASE +0x50164*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50165*4+0x02000000,0x19c); +reg_write( DDR_REG_BASE +0x50166*4+0x02000000,0xece); +reg_write( DDR_REG_BASE +0x50167*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50168*4+0x02000000,0x2440); +reg_write( DDR_REG_BASE +0x50169*4+0x02000000,0x3fc3); +reg_write( DDR_REG_BASE +0x5016a*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x5016b*4+0x02000000,0xc341); +reg_write( DDR_REG_BASE +0x5016c*4+0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x5016d*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x5016e*4+0x02000000,0x601); +reg_write( DDR_REG_BASE +0x5016f*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x50170*4+0x02000000,0x6059); +reg_write( DDR_REG_BASE +0x50171*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50172*4+0x02000000,0xa900); +reg_write( DDR_REG_BASE +0x50173*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x50174*4+0x02000000,0xaf3); +reg_write( DDR_REG_BASE +0x50175*4+0x02000000,0x8634); +reg_write( DDR_REG_BASE +0x50176*4+0x02000000,0xc09f); +reg_write( DDR_REG_BASE +0x50177*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x50178*4+0x02000000,0xbf9); +reg_write( DDR_REG_BASE +0x50179*4+0x02000000,0x8334); +reg_write( DDR_REG_BASE +0x5017a*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5017b*4+0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x5017c*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x5017d*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5017e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5017f*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50180*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x50181*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50182*4+0x02000000,0x9001); +reg_write( DDR_REG_BASE +0x50183*4+0x02000000,0xe100); +reg_write( DDR_REG_BASE +0x50184*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x50185*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x50186*4+0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x50187*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x50188*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x50189*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5018a*4+0x02000000,0xb887); +reg_write( DDR_REG_BASE +0x5018b*4+0x02000000,0xdd6); +reg_write( DDR_REG_BASE +0x5018c*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5018d*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x5018e*4+0x02000000,0xe12); +reg_write( DDR_REG_BASE +0x5018f*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50190*4+0x02000000,0xc029); +reg_write( DDR_REG_BASE +0x50191*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x50192*4+0x02000000,0xe0a); +reg_write( DDR_REG_BASE +0x50193*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50194*4+0x02000000,0xc02b); +reg_write( DDR_REG_BASE +0x50195*4+0x02000000,0x33f); +reg_write( DDR_REG_BASE +0x50196*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50197*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x50198*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x50199*4+0x02000000,0x84d); +reg_write( DDR_REG_BASE +0x5019a*4+0x02000000,0xb5); +reg_write( DDR_REG_BASE +0x5019b*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x5019c*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5019d*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5019e*4+0x02000000,0x7003); +reg_write( DDR_REG_BASE +0x5019f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x501a0*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x501a1*4+0x02000000,0xc208); +reg_write( DDR_REG_BASE +0x501a2*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x501a3*4+0x02000000,0xe); +reg_write( DDR_REG_BASE +0x501a4*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x501a5*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x501a6*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x501a7*4+0x02000000,0x4a); +reg_write( DDR_REG_BASE +0x501a8*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x501a9*4+0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x501aa*4+0x02000000,0x7e07); +reg_write( DDR_REG_BASE +0x501ab*4+0x02000000,0xc8e); +reg_write( DDR_REG_BASE +0x501ac*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x501ad*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x501ae*4+0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x501af*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x501b0*4+0x02000000,0x47a9); +reg_write( DDR_REG_BASE +0x501b1*4+0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x501b2*4+0x02000000,0x17de); +reg_write( DDR_REG_BASE +0x501b3*4+0x02000000,0xe11); +reg_write( DDR_REG_BASE +0x501b4*4+0x02000000,0x3010); +reg_write( DDR_REG_BASE +0x501b5*4+0x02000000,0x2642); +reg_write( DDR_REG_BASE +0x501b6*4+0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x501b7*4+0x02000000,0xeff); +reg_write( DDR_REG_BASE +0x501b8*4+0x02000000,0xb031); +reg_write( DDR_REG_BASE +0x501b9*4+0x02000000,0x7ffb); +reg_write( DDR_REG_BASE +0x501ba*4+0x02000000,0x84b); +reg_write( DDR_REG_BASE +0x501bb*4+0x02000000,0x38f); +reg_write( DDR_REG_BASE +0x501bc*4+0x02000000,0x2e9); +reg_write( DDR_REG_BASE +0x501bd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x501be*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x501bf*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x501c0*4+0x02000000,0x7342); +reg_write( DDR_REG_BASE +0x501c1*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x501c2*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x501c3*4+0x02000000,0xc204); +reg_write( DDR_REG_BASE +0x501c4*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x501c5*4+0x02000000,0x8e); +reg_write( DDR_REG_BASE +0x501c6*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x501c7*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x501c8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x501c9*4+0x02000000,0x7d); +reg_write( DDR_REG_BASE +0x501ca*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x501cb*4+0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x501cc*4+0x02000000,0x7e07); +reg_write( DDR_REG_BASE +0x501cd*4+0x02000000,0xc4a); +reg_write( DDR_REG_BASE +0x501ce*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x501cf*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x501d0*4+0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x501d1*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x501d2*4+0x02000000,0x47a9); +reg_write( DDR_REG_BASE +0x501d3*4+0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x501d4*4+0x02000000,0x17cd); +reg_write( DDR_REG_BASE +0x501d5*4+0x02000000,0xed06); +reg_write( DDR_REG_BASE +0x501d6*4+0x02000000,0xbd61); +reg_write( DDR_REG_BASE +0x501d7*4+0x02000000,0xd01); +reg_write( DDR_REG_BASE +0x501d8*4+0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x501d9*4+0x02000000,0x7ffb); +reg_write( DDR_REG_BASE +0x501da*4+0x02000000,0x2011); +reg_write( DDR_REG_BASE +0x501db*4+0x02000000,0x8380); +reg_write( DDR_REG_BASE +0x501dc*4+0x02000000,0x2a8); +reg_write( DDR_REG_BASE +0x501dd*4+0x02000000,0x21); +reg_write( DDR_REG_BASE +0x501de*4+0x02000000,0x72ad); +reg_write( DDR_REG_BASE +0x501df*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x501e0*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x501e1*4+0x02000000,0xf00b); +reg_write( DDR_REG_BASE +0x501e2*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x501e3*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x501e4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x501e5*4+0x02000000,0x1b4); +reg_write( DDR_REG_BASE +0x501e6*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x501e7*4+0x02000000,0x19c0); +reg_write( DDR_REG_BASE +0x501e8*4+0x02000000,0x82); +reg_write( DDR_REG_BASE +0x501e9*4+0x02000000,0xa940); +reg_write( DDR_REG_BASE +0x501ea*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x501eb*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x501ec*4+0x02000000,0x8003); +reg_write( DDR_REG_BASE +0x501ed*4+0x02000000,0xf7b6); +reg_write( DDR_REG_BASE +0x501ee*4+0x02000000,0xf3a); +reg_write( DDR_REG_BASE +0x501ef*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x501f0*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x501f1*4+0x02000000,0xf36); +reg_write( DDR_REG_BASE +0x501f2*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x501f3*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x501f4*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x501f5*4+0x02000000,0x7043); +reg_write( DDR_REG_BASE +0x501f6*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x501f7*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x501f8*4+0x02000000,0xf26); +reg_write( DDR_REG_BASE +0x501f9*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x501fa*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x501fb*4+0x02000000,0x78ef); +reg_write( DDR_REG_BASE +0x501fc*4+0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x501fd*4+0x02000000,0xfee); +reg_write( DDR_REG_BASE +0x501fe*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x501ff*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x50200*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50201*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x50202*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50203*4+0x02000000,0x73c2); +reg_write( DDR_REG_BASE +0x50204*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50205*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x50206*4+0x02000000,0xd86); +reg_write( DDR_REG_BASE +0x50207*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50208*4+0x02000000,0xf06); +reg_write( DDR_REG_BASE +0x50209*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5020a*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x5020b*4+0x02000000,0x43f9); +reg_write( DDR_REG_BASE +0x5020c*4+0x02000000,0xf04e); +reg_write( DDR_REG_BASE +0x5020d*4+0x02000000,0x143f); +reg_write( DDR_REG_BASE +0x5020e*4+0x02000000,0x3082); +reg_write( DDR_REG_BASE +0x5020f*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x50210*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50211*4+0x02000000,0x2353); +reg_write( DDR_REG_BASE +0x50212*4+0x02000000,0x3101); +reg_write( DDR_REG_BASE +0x50213*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x50214*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50215*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x50216*4+0x02000000,0x6068); +reg_write( DDR_REG_BASE +0x50217*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x50218*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50219*4+0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x5021a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5021b*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x5021c*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5021d*4+0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x5021e*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5021f*4+0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x50220*4+0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x50221*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x50222*4+0x02000000,0xbe9); +reg_write( DDR_REG_BASE +0x50223*4+0x02000000,0x80a4); +reg_write( DDR_REG_BASE +0x50224*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x50225*4+0x02000000,0x3d40); +reg_write( DDR_REG_BASE +0x50226*4+0x02000000,0xc9e); +reg_write( DDR_REG_BASE +0x50227*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x50228*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x50229*4+0x02000000,0xc190); +reg_write( DDR_REG_BASE +0x5022a*4+0x02000000,0xd62); +reg_write( DDR_REG_BASE +0x5022b*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5022c*4+0x02000000,0xda07); +reg_write( DDR_REG_BASE +0x5022d*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5022e*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5022f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50230*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x50231*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x50232*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x50233*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50234*4+0x02000000,0x1b4); +reg_write( DDR_REG_BASE +0x50235*4+0x02000000,0xc210); +reg_write( DDR_REG_BASE +0x50236*4+0x02000000,0x209f); +reg_write( DDR_REG_BASE +0x50237*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x50238*4+0x02000000,0x224a); +reg_write( DDR_REG_BASE +0x50239*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x5023a*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x5023b*4+0x02000000,0x7163); +reg_write( DDR_REG_BASE +0x5023c*4+0x02000000,0x8960); +reg_write( DDR_REG_BASE +0x5023d*4+0x02000000,0x2253); +reg_write( DDR_REG_BASE +0x5023e*4+0x02000000,0x140); +reg_write( DDR_REG_BASE +0x5023f*4+0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x50240*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x50241*4+0x02000000,0xa900); +reg_write( DDR_REG_BASE +0x50242*4+0x02000000,0x1140); +reg_write( DDR_REG_BASE +0x50243*4+0x02000000,0x83); +reg_write( DDR_REG_BASE +0x50244*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x50245*4+0x02000000,0x2242); +reg_write( DDR_REG_BASE +0x50246*4+0x02000000,0x104a); +reg_write( DDR_REG_BASE +0x50247*4+0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x50248*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x50249*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5024a*4+0x02000000,0xb8c5); +reg_write( DDR_REG_BASE +0x5024b*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x5024c*4+0x02000000,0x1940); +reg_write( DDR_REG_BASE +0x5024d*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x5024e*4+0x02000000,0x1180); +reg_write( DDR_REG_BASE +0x5024f*4+0x02000000,0x83); +reg_write( DDR_REG_BASE +0x50250*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x50251*4+0x02000000,0xda10); +reg_write( DDR_REG_BASE +0x50252*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x50253*4+0x02000000,0xa01); +reg_write( DDR_REG_BASE +0x50254*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x50255*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50256*4+0x02000000,0xb8c5); +reg_write( DDR_REG_BASE +0x50257*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x50258*4+0x02000000,0x1980); +reg_write( DDR_REG_BASE +0x50259*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x5025a*4+0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x5025b*4+0x02000000,0xb001); +reg_write( DDR_REG_BASE +0x5025c*4+0x02000000,0x762); +reg_write( DDR_REG_BASE +0x5025d*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x5025e*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x5025f*4+0x02000000,0x6c0); +reg_write( DDR_REG_BASE +0x50260*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x50261*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50262*4+0x02000000,0x7043); +reg_write( DDR_REG_BASE +0x50263*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50264*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x50265*4+0x02000000,0xc22); +reg_write( DDR_REG_BASE +0x50266*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50267*4+0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x50268*4+0x02000000,0xa5a); +reg_write( DDR_REG_BASE +0x50269*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5026a*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x5026b*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x5026c*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5026d*4+0x02000000,0x94); +reg_write( DDR_REG_BASE +0x5026e*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5026f*4+0x02000000,0x9e2); +reg_write( DDR_REG_BASE +0x50270*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50271*4+0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x50272*4+0x02000000,0xf0ba); +reg_write( DDR_REG_BASE +0x50273*4+0x02000000,0x66e8); +reg_write( DDR_REG_BASE +0x50274*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x50275*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x50276*4+0x02000000,0xf2b5); +reg_write( DDR_REG_BASE +0x50277*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x50278*4+0x02000000,0x7912); +reg_write( DDR_REG_BASE +0x50279*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5027a*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5027b*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5027c*4+0x02000000,0x1b); +reg_write( DDR_REG_BASE +0x5027d*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5027e*4+0x02000000,0x7812); +reg_write( DDR_REG_BASE +0x5027f*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50280*4+0x02000000,0xdab); +reg_write( DDR_REG_BASE +0x50281*4+0x02000000,0x103e); +reg_write( DDR_REG_BASE +0x50282*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x50283*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x50284*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50285*4+0x02000000,0x95); +reg_write( DDR_REG_BASE +0x50286*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50287*4+0x02000000,0x9b2); +reg_write( DDR_REG_BASE +0x50288*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50289*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x5028a*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x5028b*4+0x02000000,0xf040); +reg_write( DDR_REG_BASE +0x5028c*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5028d*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x5028e*4+0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x5028f*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x50290*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x50291*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50292*4+0x02000000,0x1b4); +reg_write( DDR_REG_BASE +0x50293*4+0x02000000,0x6048); +reg_write( DDR_REG_BASE +0x50294*4+0x02000000,0x792f); +reg_write( DDR_REG_BASE +0x50295*4+0x02000000,0xec06); +reg_write( DDR_REG_BASE +0x50296*4+0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x50297*4+0x02000000,0xc01); +reg_write( DDR_REG_BASE +0x50298*4+0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x50299*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5029a*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x5029b*4+0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x5029c*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x5029d*4+0x02000000,0x7cc); +reg_write( DDR_REG_BASE +0x5029e*4+0x02000000,0xec05); +reg_write( DDR_REG_BASE +0x5029f*4+0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x502a0*4+0x02000000,0xcff); +reg_write( DDR_REG_BASE +0x502a1*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x502a2*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x502a3*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x502a4*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x502a5*4+0x02000000,0xbd7); +reg_write( DDR_REG_BASE +0x502a6*4+0x02000000,0x8234); +reg_write( DDR_REG_BASE +0x502a7*4+0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x502a8*4+0x02000000,0x17cc); +reg_write( DDR_REG_BASE +0x502a9*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x502aa*4+0x02000000,0x829); +reg_write( DDR_REG_BASE +0x502ab*4+0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x502ac*4+0x02000000,0x66ea); +reg_write( DDR_REG_BASE +0x502ad*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x502ae*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x502af*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x502b0*4+0x02000000,0x19c); +reg_write( DDR_REG_BASE +0x502b1*4+0x02000000,0x6048); +reg_write( DDR_REG_BASE +0x502b2*4+0x02000000,0xc29f); +reg_write( DDR_REG_BASE +0x502b3*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x502b4*4+0x02000000,0x600); +reg_write( DDR_REG_BASE +0x502b5*4+0x02000000,0x621a); +reg_write( DDR_REG_BASE +0x502b6*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x502b7*4+0x02000000,0x6c2); +reg_write( DDR_REG_BASE +0x502b8*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x502b9*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x502ba*4+0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x502bb*4+0x02000000,0x8840); +reg_write( DDR_REG_BASE +0x502bc*4+0x02000000,0x7a25); +reg_write( DDR_REG_BASE +0x502bd*4+0x02000000,0xa840); +reg_write( DDR_REG_BASE +0x502be*4+0x02000000,0xcaa); +reg_write( DDR_REG_BASE +0x502bf*4+0x02000000,0x2a0); +reg_write( DDR_REG_BASE +0x502c0*4+0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x502c1*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x502c2*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x502c3*4+0x02000000,0x96); +reg_write( DDR_REG_BASE +0x502c4*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x502c5*4+0x02000000,0x936); +reg_write( DDR_REG_BASE +0x502c6*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x502c7*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x502c8*4+0x02000000,0x2340); +reg_write( DDR_REG_BASE +0x502c9*4+0x02000000,0x321b); +reg_write( DDR_REG_BASE +0x502ca*4+0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x502cb*4+0x02000000,0xb003); +reg_write( DDR_REG_BASE +0x502cc*4+0x02000000,0x780); +reg_write( DDR_REG_BASE +0x502cd*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x502ce*4+0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x502cf*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x502d0*4+0x02000000,0x97); +reg_write( DDR_REG_BASE +0x502d1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x502d2*4+0x02000000,0x91a); +reg_write( DDR_REG_BASE +0x502d3*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x502d4*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x502d5*4+0x02000000,0xdaf); +reg_write( DDR_REG_BASE +0x502d6*4+0x02000000,0x107e); +reg_write( DDR_REG_BASE +0x502d7*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x502d8*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x502d9*4+0x02000000,0x98); +reg_write( DDR_REG_BASE +0x502da*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x502db*4+0x02000000,0x90a); +reg_write( DDR_REG_BASE +0x502dc*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x502dd*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x502de*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x502df*4+0x02000000,0xf042); +reg_write( DDR_REG_BASE +0x502e0*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x502e1*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x502e2*4+0x02000000,0xf019); +reg_write( DDR_REG_BASE +0x502e3*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x502e4*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x502e5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x502e6*4+0x02000000,0x1b4); +reg_write( DDR_REG_BASE +0x502e7*4+0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x502e8*4+0x02000000,0x10c0); +reg_write( DDR_REG_BASE +0x502e9*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x502ea*4+0x02000000,0x792f); +reg_write( DDR_REG_BASE +0x502eb*4+0x02000000,0xec06); +reg_write( DDR_REG_BASE +0x502ec*4+0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x502ed*4+0x02000000,0xc01); +reg_write( DDR_REG_BASE +0x502ee*4+0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x502ef*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x502f0*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x502f1*4+0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x502f2*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x502f3*4+0x02000000,0x7cc); +reg_write( DDR_REG_BASE +0x502f4*4+0x02000000,0xec05); +reg_write( DDR_REG_BASE +0x502f5*4+0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x502f6*4+0x02000000,0xcff); +reg_write( DDR_REG_BASE +0x502f7*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x502f8*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x502f9*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x502fa*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x502fb*4+0x02000000,0xbd3); +reg_write( DDR_REG_BASE +0x502fc*4+0x02000000,0x8234); +reg_write( DDR_REG_BASE +0x502fd*4+0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x502fe*4+0x02000000,0x17cc); +reg_write( DDR_REG_BASE +0x502ff*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50300*4+0x02000000,0x82b); +reg_write( DDR_REG_BASE +0x50301*4+0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x50302*4+0x02000000,0xc089); +reg_write( DDR_REG_BASE +0x50303*4+0x02000000,0x60f8); +reg_write( DDR_REG_BASE +0x50304*4+0x02000000,0x8848); +reg_write( DDR_REG_BASE +0x50305*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x50306*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x50307*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50308*4+0x02000000,0x19c); +reg_write( DDR_REG_BASE +0x50309*4+0x02000000,0x6048); +reg_write( DDR_REG_BASE +0x5030a*4+0x02000000,0xc29f); +reg_write( DDR_REG_BASE +0x5030b*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x5030c*4+0x02000000,0x600); +reg_write( DDR_REG_BASE +0x5030d*4+0x02000000,0x621a); +reg_write( DDR_REG_BASE +0x5030e*4+0x02000000,0x78dd); +reg_write( DDR_REG_BASE +0x5030f*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50310*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50311*4+0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x50312*4+0x02000000,0x8840); +reg_write( DDR_REG_BASE +0x50313*4+0x02000000,0x7a25); +reg_write( DDR_REG_BASE +0x50314*4+0x02000000,0xa840); +reg_write( DDR_REG_BASE +0x50315*4+0x02000000,0xbfe); +reg_write( DDR_REG_BASE +0x50316*4+0x02000000,0x2a0); +reg_write( DDR_REG_BASE +0x50317*4+0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x50318*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x50319*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5031a*4+0x02000000,0x99); +reg_write( DDR_REG_BASE +0x5031b*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5031c*4+0x02000000,0x886); +reg_write( DDR_REG_BASE +0x5031d*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5031e*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x5031f*4+0x02000000,0xe608); +reg_write( DDR_REG_BASE +0x50320*4+0x02000000,0x268c); +reg_write( DDR_REG_BASE +0x50321*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x50322*4+0x02000000,0x77c); +reg_write( DDR_REG_BASE +0x50323*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x50324*4+0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x50325*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50326*4+0x02000000,0x9a); +reg_write( DDR_REG_BASE +0x50327*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50328*4+0x02000000,0x86e); +reg_write( DDR_REG_BASE +0x50329*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5032a*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x5032b*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x5032c*4+0x02000000,0x75f5); +reg_write( DDR_REG_BASE +0x5032d*4+0x02000000,0x68e); +reg_write( DDR_REG_BASE +0x5032e*4+0x02000000,0xffee); +reg_write( DDR_REG_BASE +0x5032f*4+0x02000000,0xc689); +reg_write( DDR_REG_BASE +0x50330*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x50331*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x50332*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x50333*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x50334*4+0x02000000,0x7414); +reg_write( DDR_REG_BASE +0x50335*4+0x02000000,0x4c8); +reg_write( DDR_REG_BASE +0x50336*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x50337*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50338*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x50339*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x5033a*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5033b*4+0x02000000,0xa76); +reg_write( DDR_REG_BASE +0x5033c*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5033d*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x5033e*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x5033f*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x50340*4+0x02000000,0xf0e4); +reg_write( DDR_REG_BASE +0x50341*4+0x02000000,0x143f); +reg_write( DDR_REG_BASE +0x50342*4+0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x50343*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x50344*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50345*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50346*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x50347*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x50348*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x50349*4+0x02000000,0xf096); +reg_write( DDR_REG_BASE +0x5034a*4+0x02000000,0x60e8); +reg_write( DDR_REG_BASE +0x5034b*4+0x02000000,0x260c); +reg_write( DDR_REG_BASE +0x5034c*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x5034d*4+0x02000000,0xf491); +reg_write( DDR_REG_BASE +0x5034e*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5034f*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x50350*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x50351*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50352*4+0x02000000,0x4758); +reg_write( DDR_REG_BASE +0x50353*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50354*4+0x02000000,0xf033); +reg_write( DDR_REG_BASE +0x50355*4+0x02000000,0xf20c); +reg_write( DDR_REG_BASE +0x50356*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x50357*4+0x02000000,0x7cc); +reg_write( DDR_REG_BASE +0x50358*4+0x02000000,0x43e3); +reg_write( DDR_REG_BASE +0x50359*4+0x02000000,0xec06); +reg_write( DDR_REG_BASE +0x5035a*4+0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x5035b*4+0x02000000,0xc01); +reg_write( DDR_REG_BASE +0x5035c*4+0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x5035d*4+0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x5035e*4+0x02000000,0xbbc0); +reg_write( DDR_REG_BASE +0x5035f*4+0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x50360*4+0x02000000,0x275a); +reg_write( DDR_REG_BASE +0x50361*4+0x02000000,0x1603); +reg_write( DDR_REG_BASE +0x50362*4+0x02000000,0xc49f); +reg_write( DDR_REG_BASE +0x50363*4+0x02000000,0x647c); +reg_write( DDR_REG_BASE +0x50364*4+0x02000000,0x7b1d); +reg_write( DDR_REG_BASE +0x50365*4+0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x50366*4+0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x50367*4+0x02000000,0x2432); +reg_write( DDR_REG_BASE +0x50368*4+0x02000000,0x10df); +reg_write( DDR_REG_BASE +0x50369*4+0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x5036a*4+0x02000000,0x3043); +reg_write( DDR_REG_BASE +0x5036b*4+0x02000000,0x7c30); +reg_write( DDR_REG_BASE +0x5036c*4+0x02000000,0x248c); +reg_write( DDR_REG_BASE +0x5036d*4+0x02000000,0x9fc3); +reg_write( DDR_REG_BASE +0x5036e*4+0x02000000,0xf408); +reg_write( DDR_REG_BASE +0x5036f*4+0x02000000,0xe0df); +reg_write( DDR_REG_BASE +0x50370*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x50371*4+0x02000000,0xf716); +reg_write( DDR_REG_BASE +0x50372*4+0x02000000,0xeb94); +reg_write( DDR_REG_BASE +0x50373*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50374*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x50375*4+0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x50376*4+0x02000000,0x7074); +reg_write( DDR_REG_BASE +0x50377*4+0x02000000,0x22c0); +reg_write( DDR_REG_BASE +0x50378*4+0x02000000,0x61); +reg_write( DDR_REG_BASE +0x50379*4+0x02000000,0xf20e); +reg_write( DDR_REG_BASE +0x5037a*4+0x02000000,0xdb3f); +reg_write( DDR_REG_BASE +0x5037b*4+0x02000000,0x233c); +reg_write( DDR_REG_BASE +0x5037c*4+0x02000000,0xb); +reg_write( DDR_REG_BASE +0x5037d*4+0x02000000,0x7c50); +reg_write( DDR_REG_BASE +0x5037e*4+0x02000000,0x7bb0); +reg_write( DDR_REG_BASE +0x5037f*4+0x02000000,0x233c); +reg_write( DDR_REG_BASE +0x50380*4+0x02000000,0x303); +reg_write( DDR_REG_BASE +0x50381*4+0x02000000,0x230b); +reg_write( DDR_REG_BASE +0x50382*4+0x02000000,0x82c0); +reg_write( DDR_REG_BASE +0x50383*4+0x02000000,0x755c); +reg_write( DDR_REG_BASE +0x50384*4+0x02000000,0x763c); +reg_write( DDR_REG_BASE +0x50385*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x50386*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x50387*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x50388*4+0x02000000,0x8003); +reg_write( DDR_REG_BASE +0x50389*4+0x02000000,0x79a); +reg_write( DDR_REG_BASE +0x5038a*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x5038b*4+0x02000000,0x2053); +reg_write( DDR_REG_BASE +0x5038c*4+0x02000000,0x8083); +reg_write( DDR_REG_BASE +0x5038d*4+0x02000000,0x78b0); +reg_write( DDR_REG_BASE +0x5038e*4+0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x5038f*4+0x02000000,0xf088); +reg_write( DDR_REG_BASE +0x50390*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x50391*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50392*4+0x02000000,0x20c5); +reg_write( DDR_REG_BASE +0x50393*4+0x02000000,0x61); +reg_write( DDR_REG_BASE +0x50394*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x50395*4+0x02000000,0x72bd); +reg_write( DDR_REG_BASE +0x50396*4+0x02000000,0x71dd); +reg_write( DDR_REG_BASE +0x50397*4+0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x50398*4+0x02000000,0xf088); +reg_write( DDR_REG_BASE +0x50399*4+0x02000000,0xf211); +reg_write( DDR_REG_BASE +0x5039a*4+0x02000000,0x2204); +reg_write( DDR_REG_BASE +0x5039b*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5039c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5039d*4+0x02000000,0xfffe); +reg_write( DDR_REG_BASE +0x5039e*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5039f*4+0x02000000,0x7e30); +reg_write( DDR_REG_BASE +0x503a0*4+0x02000000,0x661e); +reg_write( DDR_REG_BASE +0x503a1*4+0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x503a2*4+0x02000000,0xe0c0); +reg_write( DDR_REG_BASE +0x503a3*4+0x02000000,0xf74a); +reg_write( DDR_REG_BASE +0x503a4*4+0x02000000,0x81b); +reg_write( DDR_REG_BASE +0x503a5*4+0x02000000,0x835); +reg_write( DDR_REG_BASE +0x503a6*4+0x02000000,0xdd40); +reg_write( DDR_REG_BASE +0x503a7*4+0x02000000,0xde20); +reg_write( DDR_REG_BASE +0x503a8*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x503a9*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x503aa*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x503ab*4+0x02000000,0xf033); +reg_write( DDR_REG_BASE +0x503ac*4+0x02000000,0xe0df); +reg_write( DDR_REG_BASE +0x503ad*4+0x02000000,0x45c9); +reg_write( DDR_REG_BASE +0x503ae*4+0x02000000,0xf7c3); +reg_write( DDR_REG_BASE +0x503af*4+0x02000000,0xdd5f); +reg_write( DDR_REG_BASE +0x503b0*4+0x02000000,0xde5f); +reg_write( DDR_REG_BASE +0x503b1*4+0x02000000,0x78af); +reg_write( DDR_REG_BASE +0x503b2*4+0x02000000,0x792f); +reg_write( DDR_REG_BASE +0x503b3*4+0x02000000,0xb16); +reg_write( DDR_REG_BASE +0x503b4*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x503b5*4+0x02000000,0x7a4f); +reg_write( DDR_REG_BASE +0x503b6*4+0x02000000,0x4308); +reg_write( DDR_REG_BASE +0x503b7*4+0x02000000,0xb0e); +reg_write( DDR_REG_BASE +0x503b8*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x503b9*4+0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x503ba*4+0x02000000,0x2580); +reg_write( DDR_REG_BASE +0x503bb*4+0x02000000,0x103f); +reg_write( DDR_REG_BASE +0x503bc*4+0x02000000,0x79bb); +reg_write( DDR_REG_BASE +0x503bd*4+0x02000000,0x2184); +reg_write( DDR_REG_BASE +0x503be*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x503bf*4+0x02000000,0xbdc4); +reg_write( DDR_REG_BASE +0x503c0*4+0x02000000,0x7d25); +reg_write( DDR_REG_BASE +0x503c1*4+0x02000000,0xc190); +reg_write( DDR_REG_BASE +0x503c2*4+0x02000000,0x79f4); +reg_write( DDR_REG_BASE +0x503c3*4+0x02000000,0xb1a0); +reg_write( DDR_REG_BASE +0x503c4*4+0x02000000,0x2642); +reg_write( DDR_REG_BASE +0x503c5*4+0x02000000,0x1801); +reg_write( DDR_REG_BASE +0x503c6*4+0x02000000,0x7a3b); +reg_write( DDR_REG_BASE +0x503c7*4+0x02000000,0x2284); +reg_write( DDR_REG_BASE +0x503c8*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x503c9*4+0x02000000,0xb9c4); +reg_write( DDR_REG_BASE +0x503ca*4+0x02000000,0x7a25); +reg_write( DDR_REG_BASE +0x503cb*4+0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x503cc*4+0x02000000,0xc396); +reg_write( DDR_REG_BASE +0x503cd*4+0x02000000,0x7bf4); +reg_write( DDR_REG_BASE +0x503ce*4+0x02000000,0x7930); +reg_write( DDR_REG_BASE +0x503cf*4+0x02000000,0x230c); +reg_write( DDR_REG_BASE +0x503d0*4+0x02000000,0x9040); +reg_write( DDR_REG_BASE +0x503d1*4+0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x503d2*4+0x02000000,0xb340); +reg_write( DDR_REG_BASE +0x503d3*4+0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x503d4*4+0x02000000,0x2c5); +reg_write( DDR_REG_BASE +0x503d5*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x503d6*4+0x02000000,0xc103); +reg_write( DDR_REG_BASE +0x503d7*4+0x02000000,0x7930); +reg_write( DDR_REG_BASE +0x503d8*4+0x02000000,0x7030); +reg_write( DDR_REG_BASE +0x503d9*4+0x02000000,0xc103); +reg_write( DDR_REG_BASE +0x503da*4+0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x503db*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x503dc*4+0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x503dd*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x503de*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x503df*4+0x02000000,0x7710); +reg_write( DDR_REG_BASE +0x503e0*4+0x02000000,0x6d4); +reg_write( DDR_REG_BASE +0x503e1*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x503e2*4+0x02000000,0xc09c); +reg_write( DDR_REG_BASE +0x503e3*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x503e4*4+0x02000000,0x7910); +reg_write( DDR_REG_BASE +0x503e5*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x503e6*4+0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x503e7*4+0x02000000,0x843); +reg_write( DDR_REG_BASE +0x503e8*4+0x02000000,0x65); +reg_write( DDR_REG_BASE +0x503e9*4+0x02000000,0xc289); +reg_write( DDR_REG_BASE +0x503ea*4+0x02000000,0x2216); +reg_write( DDR_REG_BASE +0x503eb*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x503ec*4+0x02000000,0x8a06); +reg_write( DDR_REG_BASE +0x503ed*4+0x02000000,0xdb40); +reg_write( DDR_REG_BASE +0x503ee*4+0x02000000,0x2454); +reg_write( DDR_REG_BASE +0x503ef*4+0x02000000,0x3b0b); +reg_write( DDR_REG_BASE +0x503f0*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x503f1*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x503f2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x503f3*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x503f4*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x503f5*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x503f6*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x503f7*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x503f8*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x503f9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x503fa*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x503fb*4+0x02000000,0xb060); +reg_write( DDR_REG_BASE +0x503fc*4+0x02000000,0x8a07); +reg_write( DDR_REG_BASE +0x503fd*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x503fe*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x503ff*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50400*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x50401*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x50402*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x50403*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x50404*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50405*4+0x02000000,0xb060); +reg_write( DDR_REG_BASE +0x50406*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x50407*4+0x02000000,0x2454); +reg_write( DDR_REG_BASE +0x50408*4+0x02000000,0x380b); +reg_write( DDR_REG_BASE +0x50409*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5040a*4+0x02000000,0xf015); +reg_write( DDR_REG_BASE +0x5040b*4+0x02000000,0xc09c); +reg_write( DDR_REG_BASE +0x5040c*4+0x02000000,0x6028); +reg_write( DDR_REG_BASE +0x5040d*4+0x02000000,0xe25); +reg_write( DDR_REG_BASE +0x5040e*4+0x02000000,0x3021); +reg_write( DDR_REG_BASE +0x5040f*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x50410*4+0x02000000,0x3d40); +reg_write( DDR_REG_BASE +0x50411*4+0x02000000,0x6028); +reg_write( DDR_REG_BASE +0x50412*4+0x02000000,0x23f4); +reg_write( DDR_REG_BASE +0x50413*4+0x02000000,0x1042); +reg_write( DDR_REG_BASE +0x50414*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50415*4+0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x50416*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50417*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x50418*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x50419*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x5041a*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5041b*4+0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x5041c*4+0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x5041d*4+0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x5041e*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x5041f*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50420*4+0x02000000,0x9d7); +reg_write( DDR_REG_BASE +0x50421*4+0x02000000,0x8004); +reg_write( DDR_REG_BASE +0x50422*4+0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x50423*4+0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x50424*4+0x02000000,0x264c); +reg_write( DDR_REG_BASE +0x50425*4+0x02000000,0xb080); +reg_write( DDR_REG_BASE +0x50426*4+0x02000000,0x636); +reg_write( DDR_REG_BASE +0x50427*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x50428*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x50429*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5042a*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5042b*4+0x02000000,0xa9); +reg_write( DDR_REG_BASE +0x5042c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5042d*4+0x02000000,0x8fa); +reg_write( DDR_REG_BASE +0x5042e*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5042f*4+0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x50430*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50431*4+0x02000000,0x88a); +reg_write( DDR_REG_BASE +0x50432*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x50433*4+0x02000000,0x9f6); +reg_write( DDR_REG_BASE +0x50434*4+0x02000000,0x280); +reg_write( DDR_REG_BASE +0x50435*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50436*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50437*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50438*4+0x02000000,0x1b); +reg_write( DDR_REG_BASE +0x50439*4+0x02000000,0xb8e0); +reg_write( DDR_REG_BASE +0x5043a*4+0x02000000,0xf9c); +reg_write( DDR_REG_BASE +0x5043b*4+0x02000000,0xc2); +reg_write( DDR_REG_BASE +0x5043c*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x5043d*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x5043e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5043f*4+0x02000000,0x334); +reg_write( DDR_REG_BASE +0x50440*4+0x02000000,0x88e); +reg_write( DDR_REG_BASE +0x50441*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x50442*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50443*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x50444*4+0x02000000,0x320d); +reg_write( DDR_REG_BASE +0x50445*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50446*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50447*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50448*4+0x02000000,0xb8e6); +reg_write( DDR_REG_BASE +0x50449*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5044a*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5044b*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5044c*4+0x02000000,0xb8c2); +reg_write( DDR_REG_BASE +0x5044d*4+0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x5044e*4+0x02000000,0xf403); +reg_write( DDR_REG_BASE +0x5044f*4+0x02000000,0x7914); +reg_write( DDR_REG_BASE +0x50450*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x50451*4+0x02000000,0x7915); +reg_write( DDR_REG_BASE +0x50452*4+0x02000000,0x909); +reg_write( DDR_REG_BASE +0x50453*4+0x02000000,0x354); +reg_write( DDR_REG_BASE +0x50454*4+0x02000000,0x762c); +reg_write( DDR_REG_BASE +0x50455*4+0x02000000,0x7915); +reg_write( DDR_REG_BASE +0x50456*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50457*4+0x02000000,0x6901); +reg_write( DDR_REG_BASE +0x50458*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x50459*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5045a*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x5045b*4+0x02000000,0x8a20); +reg_write( DDR_REG_BASE +0x5045c*4+0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x5045d*4+0x02000000,0xc81); +reg_write( DDR_REG_BASE +0x5045e*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x5045f*4+0x02000000,0x8a21); +reg_write( DDR_REG_BASE +0x50460*4+0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x50461*4+0x02000000,0x641); +reg_write( DDR_REG_BASE +0x50462*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50463*4+0x02000000,0x8903); +reg_write( DDR_REG_BASE +0x50464*4+0x02000000,0xb8e6); +reg_write( DDR_REG_BASE +0x50465*4+0x02000000,0x8902); +reg_write( DDR_REG_BASE +0x50466*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50467*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x50468*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50469*4+0x02000000,0x1c); +reg_write( DDR_REG_BASE +0x5046a*4+0x02000000,0xb8c2); +reg_write( DDR_REG_BASE +0x5046b*4+0x02000000,0xf409); +reg_write( DDR_REG_BASE +0x5046c*4+0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x5046d*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5046e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5046f*4+0x02000000,0x640); +reg_write( DDR_REG_BASE +0x50470*4+0x02000000,0xf209); +reg_write( DDR_REG_BASE +0x50471*4+0x02000000,0xe108); +reg_write( DDR_REG_BASE +0x50472*4+0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x50473*4+0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x50474*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50475*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50476*4+0x02000000,0x630); +reg_write( DDR_REG_BASE +0x50477*4+0x02000000,0xf203); +reg_write( DDR_REG_BASE +0x50478*4+0x02000000,0xe108); +reg_write( DDR_REG_BASE +0x50479*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x5047a*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x5047b*4+0x02000000,0x8900); +reg_write( DDR_REG_BASE +0x5047c*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5047d*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5047e*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5047f*4+0x02000000,0xc1b5); +reg_write( DDR_REG_BASE +0x50480*4+0x02000000,0xc254); +reg_write( DDR_REG_BASE +0x50481*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x50482*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x50483*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50484*4+0x02000000,0xee); +reg_write( DDR_REG_BASE +0x50485*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50486*4+0x02000000,0xdb2); +reg_write( DDR_REG_BASE +0x50487*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50488*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x50489*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x5048a*4+0x02000000,0xf035); +reg_write( DDR_REG_BASE +0x5048b*4+0x02000000,0x4261); +reg_write( DDR_REG_BASE +0x5048c*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x5048d*4+0x02000000,0xc014); +reg_write( DDR_REG_BASE +0x5048e*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x5048f*4+0x02000000,0x83); +reg_write( DDR_REG_BASE +0x50490*4+0x02000000,0xc08e); +reg_write( DDR_REG_BASE +0x50491*4+0x02000000,0x7834); +reg_write( DDR_REG_BASE +0x50492*4+0x02000000,0xb060); +reg_write( DDR_REG_BASE +0x50493*4+0x02000000,0x62ba); +reg_write( DDR_REG_BASE +0x50494*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x50495*4+0x02000000,0x9f3); +reg_write( DDR_REG_BASE +0x50496*4+0x02000000,0x8294); +reg_write( DDR_REG_BASE +0x50497*4+0x02000000,0x4183); +reg_write( DDR_REG_BASE +0x50498*4+0x02000000,0x911c); +reg_write( DDR_REG_BASE +0x50499*4+0x02000000,0x1446); +reg_write( DDR_REG_BASE +0x5049a*4+0x02000000,0x3103); +reg_write( DDR_REG_BASE +0x5049b*4+0x02000000,0x915f); +reg_write( DDR_REG_BASE +0x5049c*4+0x02000000,0xc053); +reg_write( DDR_REG_BASE +0x5049d*4+0x02000000,0x1448); +reg_write( DDR_REG_BASE +0x5049e*4+0x02000000,0x3101); +reg_write( DDR_REG_BASE +0x5049f*4+0x02000000,0x144a); +reg_write( DDR_REG_BASE +0x504a0*4+0x02000000,0x3100); +reg_write( DDR_REG_BASE +0x504a1*4+0x02000000,0x143a); +reg_write( DDR_REG_BASE +0x504a2*4+0x02000000,0x311f); +reg_write( DDR_REG_BASE +0x504a3*4+0x02000000,0x143c); +reg_write( DDR_REG_BASE +0x504a4*4+0x02000000,0x311e); +reg_write( DDR_REG_BASE +0x504a5*4+0x02000000,0x1440); +reg_write( DDR_REG_BASE +0x504a6*4+0x02000000,0x310f); +reg_write( DDR_REG_BASE +0x504a7*4+0x02000000,0x1442); +reg_write( DDR_REG_BASE +0x504a8*4+0x02000000,0x310e); +reg_write( DDR_REG_BASE +0x504a9*4+0x02000000,0x1444); +reg_write( DDR_REG_BASE +0x504aa*4+0x02000000,0x310c); +reg_write( DDR_REG_BASE +0x504ab*4+0x02000000,0xc346); +reg_write( DDR_REG_BASE +0x504ac*4+0x02000000,0xc313); +reg_write( DDR_REG_BASE +0x504ad*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x504ae*4+0x02000000,0xc147); +reg_write( DDR_REG_BASE +0x504af*4+0x02000000,0xc242); +reg_write( DDR_REG_BASE +0x504b0*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x504b1*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x504b2*4+0x02000000,0xef); +reg_write( DDR_REG_BASE +0x504b3*4+0x02000000,0xb); +reg_write( DDR_REG_BASE +0x504b4*4+0x02000000,0xc445); +reg_write( DDR_REG_BASE +0x504b5*4+0x02000000,0xc644); +reg_write( DDR_REG_BASE +0x504b6*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x504b7*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x504b8*4+0x02000000,0x3780); +reg_write( DDR_REG_BASE +0x504b9*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x504ba*4+0x02000000,0x37c0); +reg_write( DDR_REG_BASE +0x504bb*4+0x02000000,0xd4a); +reg_write( DDR_REG_BASE +0x504bc*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x504bd*4+0x02000000,0x4261); +reg_write( DDR_REG_BASE +0x504be*4+0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x504bf*4+0x02000000,0x232f); +reg_write( DDR_REG_BASE +0x504c0*4+0x02000000,0x16c8); +reg_write( DDR_REG_BASE +0x504c1*4+0x02000000,0xb97); +reg_write( DDR_REG_BASE +0x504c2*4+0x02000000,0x9364); +reg_write( DDR_REG_BASE +0x504c3*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x504c4*4+0x02000000,0xc0b5); +reg_write( DDR_REG_BASE +0x504c5*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x504c6*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x504c7*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x504c8*4+0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x504c9*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x504ca*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x504cb*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x504cc*4+0x02000000,0x866); +reg_write( DDR_REG_BASE +0x504cd*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x504ce*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x504cf*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x504d0*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x504d1*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x504d2*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x504d3*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x504d4*4+0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x504d5*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x504d6*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x504d7*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x504d8*4+0x02000000,0x926); +reg_write( DDR_REG_BASE +0x504d9*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x504da*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x504db*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x504dc*4+0x02000000,0x1100); +reg_write( DDR_REG_BASE +0x504dd*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x504de*4+0x02000000,0xb98d); +reg_write( DDR_REG_BASE +0x504df*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x504e0*4+0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x504e1*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x504e2*4+0x02000000,0xf03); +reg_write( DDR_REG_BASE +0x504e3*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x504e4*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x504e5*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x504e6*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x504e7*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x504e8*4+0x02000000,0x906); +reg_write( DDR_REG_BASE +0x504e9*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x504ea*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x504eb*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x504ec*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x504ed*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x504ee*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x504ef*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x504f0*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x504f1*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x504f2*4+0x02000000,0x8f2); +reg_write( DDR_REG_BASE +0x504f3*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x504f4*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x504f5*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x504f6*4+0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x504f7*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x504f8*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x504f9*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x504fa*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x504fb*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x504fc*4+0x02000000,0x102); +reg_write( DDR_REG_BASE +0x504fd*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x504fe*4+0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x504ff*4+0x02000000,0x4308); +reg_write( DDR_REG_BASE +0x50500*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50501*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50502*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x50503*4+0x02000000,0x1e4); +reg_write( DDR_REG_BASE +0x50504*4+0x02000000,0x218c); +reg_write( DDR_REG_BASE +0x50505*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x50506*4+0x02000000,0xb6a0); +reg_write( DDR_REG_BASE +0x50507*4+0x02000000,0xb6a1); +reg_write( DDR_REG_BASE +0x50508*4+0x02000000,0xb6a2); +reg_write( DDR_REG_BASE +0x50509*4+0x02000000,0xf224); +reg_write( DDR_REG_BASE +0x5050a*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5050b*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5050c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5050d*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5050e*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x5050f*4+0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x50510*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50511*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50512*4+0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x50513*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50514*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50515*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x50516*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x50517*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50518*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50519*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x5051a*4+0x02000000,0x8881); +reg_write( DDR_REG_BASE +0x5051b*4+0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x5051c*4+0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x5051d*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x5051e*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x5051f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50520*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x50521*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x50522*4+0x02000000,0x7a65); +reg_write( DDR_REG_BASE +0x50523*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x50524*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x50525*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50526*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x50527*4+0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x50528*4+0x02000000,0xceb); +reg_write( DDR_REG_BASE +0x50529*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x5052a*4+0x02000000,0x806); +reg_write( DDR_REG_BASE +0x5052b*4+0x02000000,0x280); +reg_write( DDR_REG_BASE +0x5052c*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x5052d*4+0x02000000,0x21a); +reg_write( DDR_REG_BASE +0x5052e*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5052f*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x50530*4+0x02000000,0x2a); +reg_write( DDR_REG_BASE +0x50531*4+0x02000000,0x1efc); +reg_write( DDR_REG_BASE +0x50532*4+0x02000000,0x92c4); +reg_write( DDR_REG_BASE +0x50533*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x50534*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50535*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50536*4+0x02000000,0x446); +reg_write( DDR_REG_BASE +0x50537*4+0x02000000,0xa8a0); +reg_write( DDR_REG_BASE +0x50538*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50539*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5053a*4+0x02000000,0xfac); +reg_write( DDR_REG_BASE +0x5053b*4+0x02000000,0xb101); +reg_write( DDR_REG_BASE +0x5053c*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5053d*4+0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x5053e*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5053f*4+0x02000000,0x7210); +reg_write( DDR_REG_BASE +0x50540*4+0x02000000,0x20e0); +reg_write( DDR_REG_BASE +0x50541*4+0x02000000,0x7ca); +reg_write( DDR_REG_BASE +0x50542*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50543*4+0x02000000,0x7101); +reg_write( DDR_REG_BASE +0x50544*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x50545*4+0x02000000,0x1d6); +reg_write( DDR_REG_BASE +0x50546*4+0x02000000,0x9f3); +reg_write( DDR_REG_BASE +0x50547*4+0x02000000,0x803e); +reg_write( DDR_REG_BASE +0x50548*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x50549*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5054a*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x5054b*4+0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x5054c*4+0x02000000,0xe52); +reg_write( DDR_REG_BASE +0x5054d*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5054e*4+0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x5054f*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x50550*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x50551*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50552*4+0x02000000,0xf2); +reg_write( DDR_REG_BASE +0x50553*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50554*4+0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x50555*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50556*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x50557*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50558*4+0x02000000,0x7784); +reg_write( DDR_REG_BASE +0x50559*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x5055a*4+0x02000000,0x1e2); +reg_write( DDR_REG_BASE +0x5055b*4+0x02000000,0xdd2); +reg_write( DDR_REG_BASE +0x5055c*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x5055d*4+0x02000000,0x760c); +reg_write( DDR_REG_BASE +0x5055e*4+0x02000000,0xb17); +reg_write( DDR_REG_BASE +0x5055f*4+0x02000000,0x1030); +reg_write( DDR_REG_BASE +0x50560*4+0x02000000,0x1d10); +reg_write( DDR_REG_BASE +0x50561*4+0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x50562*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50563*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50564*4+0x02000000,0x61a8); +reg_write( DDR_REG_BASE +0x50565*4+0x02000000,0xfb6); +reg_write( DDR_REG_BASE +0x50566*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x50567*4+0x02000000,0x1d10); +reg_write( DDR_REG_BASE +0x50568*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x50569*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x5056a*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5056b*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5056c*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5056d*4+0x02000000,0xc1a6); +reg_write( DDR_REG_BASE +0x5056e*4+0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x5056f*4+0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x50570*4+0x02000000,0xc20b); +reg_write( DDR_REG_BASE +0x50571*4+0x02000000,0xc345); +reg_write( DDR_REG_BASE +0x50572*4+0x02000000,0xdb7f); +reg_write( DDR_REG_BASE +0x50573*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50574*4+0x02000000,0x7b44); +reg_write( DDR_REG_BASE +0x50575*4+0x02000000,0xd84b); +reg_write( DDR_REG_BASE +0x50576*4+0x02000000,0x2338); +reg_write( DDR_REG_BASE +0x50577*4+0x02000000,0xf); +reg_write( DDR_REG_BASE +0x50578*4+0x02000000,0x279a); +reg_write( DDR_REG_BASE +0x50579*4+0x02000000,0x1002); +reg_write( DDR_REG_BASE +0x5057a*4+0x02000000,0xbae6); +reg_write( DDR_REG_BASE +0x5057b*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x5057c*4+0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x5057d*4+0x02000000,0x234f); +reg_write( DDR_REG_BASE +0x5057e*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x5057f*4+0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x50580*4+0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x50581*4+0x02000000,0xe4cf); +reg_write( DDR_REG_BASE +0x50582*4+0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x50583*4+0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x50584*4+0x02000000,0xe3d1); +reg_write( DDR_REG_BASE +0x50585*4+0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x50586*4+0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x50587*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50588*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50589*4+0x02000000,0x7083); +reg_write( DDR_REG_BASE +0x5058a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5058b*4+0x02000000,0x446); +reg_write( DDR_REG_BASE +0x5058c*4+0x02000000,0x1400); +reg_write( DDR_REG_BASE +0x5058d*4+0x02000000,0x301f); +reg_write( DDR_REG_BASE +0x5058e*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x5058f*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x50590*4+0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x50591*4+0x02000000,0x2642); +reg_write( DDR_REG_BASE +0x50592*4+0x02000000,0x304b); +reg_write( DDR_REG_BASE +0x50593*4+0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x50594*4+0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x50595*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x50596*4+0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x50597*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x50598*4+0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x50599*4+0x02000000,0xb51); +reg_write( DDR_REG_BASE +0x5059a*4+0x02000000,0x16b5); +reg_write( DDR_REG_BASE +0x5059b*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5059c*4+0x02000000,0xdb50); +reg_write( DDR_REG_BASE +0x5059d*4+0x02000000,0xc341); +reg_write( DDR_REG_BASE +0x5059e*4+0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x5059f*4+0x02000000,0xd810); +reg_write( DDR_REG_BASE +0x505a0*4+0x02000000,0xde30); +reg_write( DDR_REG_BASE +0x505a1*4+0x02000000,0xdd60); +reg_write( DDR_REG_BASE +0x505a2*4+0x02000000,0x4378); +reg_write( DDR_REG_BASE +0x505a3*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x505a4*4+0x02000000,0x2025); +reg_write( DDR_REG_BASE +0x505a5*4+0x02000000,0x2c0); +reg_write( DDR_REG_BASE +0x505a6*4+0x02000000,0xf01a); +reg_write( DDR_REG_BASE +0x505a7*4+0x02000000,0xf01a); +reg_write( DDR_REG_BASE +0x505a8*4+0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x505a9*4+0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x505aa*4+0x02000000,0xf05c); +reg_write( DDR_REG_BASE +0x505ab*4+0x02000000,0xf019); +reg_write( DDR_REG_BASE +0x505ac*4+0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x505ad*4+0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x505ae*4+0x02000000,0xf045); +reg_write( DDR_REG_BASE +0x505af*4+0x02000000,0xf048); +reg_write( DDR_REG_BASE +0x505b0*4+0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x505b1*4+0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x505b2*4+0x02000000,0xf047); +reg_write( DDR_REG_BASE +0x505b3*4+0x02000000,0xf03b); +reg_write( DDR_REG_BASE +0x505b4*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x505b5*4+0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x505b6*4+0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x505b7*4+0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x505b8*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x505b9*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x505ba*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x505bb*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x505bc*4+0x02000000,0xf03f); +reg_write( DDR_REG_BASE +0x505bd*4+0x02000000,0xf034); +reg_write( DDR_REG_BASE +0x505be*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x505bf*4+0x02000000,0xf0a8); +reg_write( DDR_REG_BASE +0x505c0*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x505c1*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x505c2*4+0x02000000,0xdb10); +reg_write( DDR_REG_BASE +0x505c3*4+0x02000000,0x264c); +reg_write( DDR_REG_BASE +0x505c4*4+0x02000000,0xb640); +reg_write( DDR_REG_BASE +0x505c5*4+0x02000000,0x14a); +reg_write( DDR_REG_BASE +0x505c6*4+0x02000000,0x2d); +reg_write( DDR_REG_BASE +0x505c7*4+0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x505c8*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x505c9*4+0x02000000,0x748d); +reg_write( DDR_REG_BASE +0x505ca*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x505cb*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x505cc*4+0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x505cd*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x505ce*4+0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x505cf*4+0x02000000,0x2025); +reg_write( DDR_REG_BASE +0x505d0*4+0x02000000,0x780); +reg_write( DDR_REG_BASE +0x505d1*4+0x02000000,0xf036); +reg_write( DDR_REG_BASE +0x505d2*4+0x02000000,0xf02c); +reg_write( DDR_REG_BASE +0x505d3*4+0x02000000,0xf02b); +reg_write( DDR_REG_BASE +0x505d4*4+0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x505d5*4+0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x505d6*4+0x02000000,0xf093); +reg_write( DDR_REG_BASE +0x505d7*4+0x02000000,0xf099); +reg_write( DDR_REG_BASE +0x505d8*4+0x02000000,0xf093); +reg_write( DDR_REG_BASE +0x505d9*4+0x02000000,0xf015); +reg_write( DDR_REG_BASE +0x505da*4+0x02000000,0xf019); +reg_write( DDR_REG_BASE +0x505db*4+0x02000000,0xf01c); +reg_write( DDR_REG_BASE +0x505dc*4+0x02000000,0xf091); +reg_write( DDR_REG_BASE +0x505dd*4+0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x505de*4+0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x505df*4+0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x505e0*4+0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x505e1*4+0x02000000,0xf089); +reg_write( DDR_REG_BASE +0x505e2*4+0x02000000,0xf087); +reg_write( DDR_REG_BASE +0x505e3*4+0x02000000,0xf087); +reg_write( DDR_REG_BASE +0x505e4*4+0x02000000,0xf085); +reg_write( DDR_REG_BASE +0x505e5*4+0x02000000,0xf085); +reg_write( DDR_REG_BASE +0x505e6*4+0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x505e7*4+0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x505e8*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x505e9*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x505ea*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x505eb*4+0x02000000,0xdb07); +reg_write( DDR_REG_BASE +0x505ec*4+0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x505ed*4+0x02000000,0xc701); +reg_write( DDR_REG_BASE +0x505ee*4+0x02000000,0x758d); +reg_write( DDR_REG_BASE +0x505ef*4+0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x505f0*4+0x02000000,0x758d); +reg_write( DDR_REG_BASE +0x505f1*4+0x02000000,0x47a9); +reg_write( DDR_REG_BASE +0x505f2*4+0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x505f3*4+0x02000000,0x758d); +reg_write( DDR_REG_BASE +0x505f4*4+0x02000000,0x47c9); +reg_write( DDR_REG_BASE +0x505f5*4+0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x505f6*4+0x02000000,0x718d); +reg_write( DDR_REG_BASE +0x505f7*4+0x02000000,0x476b); +reg_write( DDR_REG_BASE +0x505f8*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x505f9*4+0x02000000,0x768d); +reg_write( DDR_REG_BASE +0x505fa*4+0x02000000,0xf00b); +reg_write( DDR_REG_BASE +0x505fb*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x505fc*4+0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x505fd*4+0x02000000,0x736c); +reg_write( DDR_REG_BASE +0x505fe*4+0x02000000,0xe0d); +reg_write( DDR_REG_BASE +0x505ff*4+0x02000000,0x30d1); +reg_write( DDR_REG_BASE +0x50600*4+0x02000000,0xc402); +reg_write( DDR_REG_BASE +0x50601*4+0x02000000,0x249a); +reg_write( DDR_REG_BASE +0x50602*4+0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x50603*4+0x02000000,0x7a85); +reg_write( DDR_REG_BASE +0x50604*4+0x02000000,0x4468); +reg_write( DDR_REG_BASE +0x50605*4+0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x50606*4+0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x50607*4+0x02000000,0xffd); +reg_write( DDR_REG_BASE +0x50608*4+0x02000000,0x7b24); +reg_write( DDR_REG_BASE +0x50609*4+0x02000000,0x783d); +reg_write( DDR_REG_BASE +0x5060a*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x5060b*4+0x02000000,0xc0b); +reg_write( DDR_REG_BASE +0x5060c*4+0x02000000,0xe3b0); +reg_write( DDR_REG_BASE +0x5060d*4+0x02000000,0xdb58); +reg_write( DDR_REG_BASE +0x5060e*4+0x02000000,0x23cf); +reg_write( DDR_REG_BASE +0x5060f*4+0x02000000,0x11e1); +reg_write( DDR_REG_BASE +0x50610*4+0x02000000,0x7b24); +reg_write( DDR_REG_BASE +0x50611*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x50612*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50613*4+0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x50614*4+0x02000000,0x2c3); +reg_write( DDR_REG_BASE +0x50615*4+0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x50616*4+0x02000000,0x7b05); +reg_write( DDR_REG_BASE +0x50617*4+0x02000000,0x783d); +reg_write( DDR_REG_BASE +0x50618*4+0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x50619*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5061a*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5061b*4+0x02000000,0xc405); +reg_write( DDR_REG_BASE +0x5061c*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5061d*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x5061e*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5061f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50620*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x50621*4+0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x50622*4+0x02000000,0x7c65); +reg_write( DDR_REG_BASE +0x50623*4+0x02000000,0x232f); +reg_write( DDR_REG_BASE +0x50624*4+0x02000000,0x17c0); +reg_write( DDR_REG_BASE +0x50625*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x50626*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x50627*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50628*4+0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x50629*4+0x02000000,0x10c0); +reg_write( DDR_REG_BASE +0x5062a*4+0x02000000,0xb080); +reg_write( DDR_REG_BASE +0x5062b*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x5062c*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x5062d*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5062e*4+0x02000000,0x7154); +reg_write( DDR_REG_BASE +0x5062f*4+0x02000000,0x2104); +reg_write( DDR_REG_BASE +0x50630*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x50631*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50632*4+0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x50633*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x50634*4+0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x50635*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50636*4+0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x50637*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50638*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50639*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5063a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5063b*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x5063c*4+0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x5063d*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x5063e*4+0x02000000,0x20cf); +reg_write( DDR_REG_BASE +0x5063f*4+0x02000000,0x1a1); +reg_write( DDR_REG_BASE +0x50640*4+0x02000000,0x264c); +reg_write( DDR_REG_BASE +0x50641*4+0x02000000,0xb180); +reg_write( DDR_REG_BASE +0x50642*4+0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x50643*4+0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x50644*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x50645*4+0x02000000,0xb8c3); +reg_write( DDR_REG_BASE +0x50646*4+0x02000000,0x7f05); +reg_write( DDR_REG_BASE +0x50647*4+0x02000000,0x78ef); +reg_write( DDR_REG_BASE +0x50648*4+0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x50649*4+0x02000000,0x2354); +reg_write( DDR_REG_BASE +0x5064a*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x5064b*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x5064c*4+0x02000000,0xb080); +reg_write( DDR_REG_BASE +0x5064d*4+0x02000000,0x2355); +reg_write( DDR_REG_BASE +0x5064e*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x5064f*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x50650*4+0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x50651*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x50652*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x50653*4+0x02000000,0x2355); +reg_write( DDR_REG_BASE +0x50654*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x50655*4+0x02000000,0x7b05); +reg_write( DDR_REG_BASE +0x50656*4+0x02000000,0xb320); +reg_write( DDR_REG_BASE +0x50657*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50658*4+0x02000000,0x2740); +reg_write( DDR_REG_BASE +0x50659*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x5065a*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x5065b*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x5065c*4+0x02000000,0xf405); +reg_write( DDR_REG_BASE +0x5065d*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5065e*4+0x02000000,0x7042); +reg_write( DDR_REG_BASE +0x5065f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50660*4+0x02000000,0x446); +reg_write( DDR_REG_BASE +0x50661*4+0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x50662*4+0x02000000,0xc0a6); +reg_write( DDR_REG_BASE +0x50663*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50664*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50665*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50666*4+0x02000000,0x738d); +reg_write( DDR_REG_BASE +0x50667*4+0x02000000,0xdf10); +reg_write( DDR_REG_BASE +0x50668*4+0x02000000,0xf19e); +reg_write( DDR_REG_BASE +0x50669*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x5066a*4+0x02000000,0xf19b); +reg_write( DDR_REG_BASE +0x5066b*4+0x02000000,0x718d); +reg_write( DDR_REG_BASE +0x5066c*4+0x02000000,0xf199); +reg_write( DDR_REG_BASE +0x5066d*4+0x02000000,0xdc20); +reg_write( DDR_REG_BASE +0x5066e*4+0x02000000,0xf197); +reg_write( DDR_REG_BASE +0x5066f*4+0x02000000,0x758d); +reg_write( DDR_REG_BASE +0x50670*4+0x02000000,0xf195); +reg_write( DDR_REG_BASE +0x50671*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50672*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x50673*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x50674*4+0x02000000,0xc408); +reg_write( DDR_REG_BASE +0x50675*4+0x02000000,0xc443); +reg_write( DDR_REG_BASE +0x50676*4+0x02000000,0xc407); +reg_write( DDR_REG_BASE +0x50677*4+0x02000000,0xc442); +reg_write( DDR_REG_BASE +0x50678*4+0x02000000,0xc406); +reg_write( DDR_REG_BASE +0x50679*4+0x02000000,0xc441); +reg_write( DDR_REG_BASE +0x5067a*4+0x02000000,0xc405); +reg_write( DDR_REG_BASE +0x5067b*4+0x02000000,0xde2); +reg_write( DDR_REG_BASE +0x5067c*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5067d*4+0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x5067e*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x5067f*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x50680*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50681*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50682*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50683*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50684*4+0x02000000,0x446); +reg_write( DDR_REG_BASE +0x50685*4+0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x50686*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x50687*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x50688*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x50689*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x5068a*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5068b*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x5068c*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x5068d*4+0x02000000,0x1e8); +reg_write( DDR_REG_BASE +0x5068e*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5068f*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50690*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50691*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50692*4+0x02000000,0x446); +reg_write( DDR_REG_BASE +0x50693*4+0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x50694*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x50695*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x50696*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x50697*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x50698*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50699*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x5069a*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x5069b*4+0x02000000,0x1e6); +reg_write( DDR_REG_BASE +0x5069c*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5069d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5069e*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5069f*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x506a0*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x506a1*4+0x02000000,0x9160); +reg_write( DDR_REG_BASE +0x506a2*4+0x02000000,0x9141); +reg_write( DDR_REG_BASE +0x506a3*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x506a4*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x506a5*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x506a6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x506a7*4+0x02000000,0x7965); +reg_write( DDR_REG_BASE +0x506a8*4+0x02000000,0xe807); +reg_write( DDR_REG_BASE +0x506a9*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x506aa*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x506ab*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x506ac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x506ad*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x506ae*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x506af*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x506b0*4+0x02000000,0xda0f); +reg_write( DDR_REG_BASE +0x506b1*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x506b2*4+0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x506b3*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x506b4*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x506b5*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x506b6*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x506b7*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x506b8*4+0x02000000,0x900f); +reg_write( DDR_REG_BASE +0x506b9*4+0x02000000,0xfe4c); +reg_write( DDR_REG_BASE +0x506ba*4+0x02000000,0xda10); +reg_write( DDR_REG_BASE +0x506bb*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x506bc*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x506bd*4+0x02000000,0xa01); +reg_write( DDR_REG_BASE +0x506be*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x506bf*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x506c0*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x506c1*4+0x02000000,0xb101); +reg_write( DDR_REG_BASE +0x506c2*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x506c3*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x506c4*4+0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x506c5*4+0x02000000,0x265a); +reg_write( DDR_REG_BASE +0x506c6*4+0x02000000,0x3c83); +reg_write( DDR_REG_BASE +0x506c7*4+0x02000000,0x607c); +reg_write( DDR_REG_BASE +0x506c8*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x506c9*4+0x02000000,0x1643); +reg_write( DDR_REG_BASE +0x506ca*4+0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x506cb*4+0x02000000,0x639b); +reg_write( DDR_REG_BASE +0x506cc*4+0x02000000,0x633b); +reg_write( DDR_REG_BASE +0x506cd*4+0x02000000,0x8b80); +reg_write( DDR_REG_BASE +0x506ce*4+0x02000000,0x7c44); +reg_write( DDR_REG_BASE +0x506cf*4+0x02000000,0xab80); +reg_write( DDR_REG_BASE +0x506d0*4+0x02000000,0xbeb); +reg_write( DDR_REG_BASE +0x506d1*4+0x02000000,0x9094); +reg_write( DDR_REG_BASE +0x506d2*4+0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x506d3*4+0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x506d4*4+0x02000000,0xef9); +reg_write( DDR_REG_BASE +0x506d5*4+0x02000000,0xb0b4); +reg_write( DDR_REG_BASE +0x506d6*4+0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x506d7*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x506d8*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x506d9*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x506da*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x506db*4+0x02000000,0xc4a); +reg_write( DDR_REG_BASE +0x506dc*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x506dd*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x506de*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x506df*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x506e0*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x506e1*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x506e2*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x506e3*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x506e4*4+0x02000000,0xd988); +reg_write( DDR_REG_BASE +0x506e5*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x506e6*4+0x02000000,0xd0a); +reg_write( DDR_REG_BASE +0x506e7*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x506e8*4+0x02000000,0xdb40); +reg_write( DDR_REG_BASE +0x506e9*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x506ea*4+0x02000000,0xcc2); +reg_write( DDR_REG_BASE +0x506eb*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x506ec*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x506ed*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x506ee*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x506ef*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x506f0*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x506f1*4+0x02000000,0x20c0); +reg_write( DDR_REG_BASE +0x506f2*4+0x02000000,0xfe9); +reg_write( DDR_REG_BASE +0x506f3*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x506f4*4+0x02000000,0x2884); +reg_write( DDR_REG_BASE +0x506f5*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x506f6*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x506f7*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x506f8*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x506f9*4+0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x506fa*4+0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x506fb*4+0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x506fc*4+0x02000000,0x641); +reg_write( DDR_REG_BASE +0x506fd*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x506fe*4+0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x506ff*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x50700*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x50701*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50702*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50703*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x50704*4+0x02000000,0x8803); +reg_write( DDR_REG_BASE +0x50705*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50706*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50707*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50708*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50709*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5070a*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5070b*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x5070c*4+0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x5070d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5070e*4+0x02000000,0x917); +reg_write( DDR_REG_BASE +0x5070f*4+0x02000000,0x3f0); +reg_write( DDR_REG_BASE +0x50710*4+0x02000000,0x228a); +reg_write( DDR_REG_BASE +0x50711*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x50712*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x50713*4+0x02000000,0xb9c4); +reg_write( DDR_REG_BASE +0x50714*4+0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x50715*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x50716*4+0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x50717*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x50718*4+0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x50719*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x5071a*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5071b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5071c*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x5071d*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5071e*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x5071f*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50720*4+0x02000000,0x16a); +reg_write( DDR_REG_BASE +0x50721*4+0x02000000,0x224f); +reg_write( DDR_REG_BASE +0x50722*4+0x02000000,0x240); +reg_write( DDR_REG_BASE +0x50723*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50724*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x50725*4+0x02000000,0xb140); +reg_write( DDR_REG_BASE +0x50726*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x50727*4+0x02000000,0xb140); +reg_write( DDR_REG_BASE +0x50728*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50729*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x5072a*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x5072b*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5072c*4+0x02000000,0x80d); +reg_write( DDR_REG_BASE +0x5072d*4+0x02000000,0x72); +reg_write( DDR_REG_BASE +0x5072e*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5072f*4+0x02000000,0x48ff); +reg_write( DDR_REG_BASE +0x50730*4+0x02000000,0x2984); +reg_write( DDR_REG_BASE +0x50731*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50732*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50733*4+0x02000000,0x782e); +reg_write( DDR_REG_BASE +0x50734*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x50735*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x50736*4+0x02000000,0xe9a); +reg_write( DDR_REG_BASE +0x50737*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50738*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x50739*4+0x02000000,0x795b); +reg_write( DDR_REG_BASE +0x5073a*4+0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x5073b*4+0x02000000,0x181); +reg_write( DDR_REG_BASE +0x5073c*4+0x02000000,0xb9c4); +reg_write( DDR_REG_BASE +0x5073d*4+0x02000000,0xe906); +reg_write( DDR_REG_BASE +0x5073e*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x5073f*4+0x02000000,0x901); +reg_write( DDR_REG_BASE +0x50740*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x50741*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50742*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x50743*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50744*4+0x02000000,0xb8c1); +reg_write( DDR_REG_BASE +0x50745*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50746*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x50747*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x50748*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50749*4+0x02000000,0xb6e); +reg_write( DDR_REG_BASE +0x5074a*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5074b*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x5074c*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5074d*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5074e*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5074f*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x50750*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50751*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50752*4+0x02000000,0xd990); +reg_write( DDR_REG_BASE +0x50753*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x50754*4+0x02000000,0xc2e); +reg_write( DDR_REG_BASE +0x50755*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50756*4+0x02000000,0xdb40); +reg_write( DDR_REG_BASE +0x50757*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50758*4+0x02000000,0xbe6); +reg_write( DDR_REG_BASE +0x50759*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5075a*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5075b*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x5075c*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x5075d*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5075e*4+0x02000000,0xc3e1); +reg_write( DDR_REG_BASE +0x5075f*4+0x02000000,0xc2e1); +reg_write( DDR_REG_BASE +0x50760*4+0x02000000,0xc1e1); +reg_write( DDR_REG_BASE +0x50761*4+0x02000000,0xc0e1); +reg_write( DDR_REG_BASE +0x50762*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x50763*4+0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x50764*4+0x02000000,0x4220); +reg_write( DDR_REG_BASE +0x50765*4+0x02000000,0xc184); +reg_write( DDR_REG_BASE +0x50766*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x50767*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50768*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x50769*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5076a*4+0x02000000,0x12); +reg_write( DDR_REG_BASE +0x5076b*4+0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x5076c*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x5076d*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x5076e*4+0x02000000,0xb1e); +reg_write( DDR_REG_BASE +0x5076f*4+0x02000000,0x2e0); +reg_write( DDR_REG_BASE +0x50770*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x50771*4+0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x50772*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x50773*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50774*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x50775*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50776*4+0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x50777*4+0x02000000,0x216c); +reg_write( DDR_REG_BASE +0x50778*4+0x02000000,0x102); +reg_write( DDR_REG_BASE +0x50779*4+0x02000000,0x206c); +reg_write( DDR_REG_BASE +0x5077a*4+0x02000000,0x141); +reg_write( DDR_REG_BASE +0x5077b*4+0x02000000,0x7822); +reg_write( DDR_REG_BASE +0x5077c*4+0x02000000,0x621a); +reg_write( DDR_REG_BASE +0x5077d*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x5077e*4+0x02000000,0x784e); +reg_write( DDR_REG_BASE +0x5077f*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50780*4+0x02000000,0xc0e6); +reg_write( DDR_REG_BASE +0x50781*4+0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x50782*4+0x02000000,0x483); +reg_write( DDR_REG_BASE +0x50783*4+0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x50784*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50785*4+0x02000000,0x6e2); +reg_write( DDR_REG_BASE +0x50786*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x50787*4+0x02000000,0x638d); +reg_write( DDR_REG_BASE +0x50788*4+0x02000000,0x6479); +reg_write( DDR_REG_BASE +0x50789*4+0x02000000,0x8941); +reg_write( DDR_REG_BASE +0x5078a*4+0x02000000,0x7d04); +reg_write( DDR_REG_BASE +0x5078b*4+0x02000000,0xf00b); +reg_write( DDR_REG_BASE +0x5078c*4+0x02000000,0x6199); +reg_write( DDR_REG_BASE +0x5078d*4+0x02000000,0x89e2); +reg_write( DDR_REG_BASE +0x5078e*4+0x02000000,0x7f0b); +reg_write( DDR_REG_BASE +0x5078f*4+0x02000000,0xf206); +reg_write( DDR_REG_BASE +0x50790*4+0x02000000,0x89e3); +reg_write( DDR_REG_BASE +0x50791*4+0x02000000,0x79af); +reg_write( DDR_REG_BASE +0x50792*4+0x02000000,0x210f); +reg_write( DDR_REG_BASE +0x50793*4+0x02000000,0x3cd); +reg_write( DDR_REG_BASE +0x50794*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x50795*4+0x02000000,0xef1); +reg_write( DDR_REG_BASE +0x50796*4+0x02000000,0x90a4); +reg_write( DDR_REG_BASE +0x50797*4+0x02000000,0x2314); +reg_write( DDR_REG_BASE +0x50798*4+0x02000000,0x381); +reg_write( DDR_REG_BASE +0x50799*4+0x02000000,0x78af); +reg_write( DDR_REG_BASE +0x5079a*4+0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x5079b*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5079c*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5079d*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5079e*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5079f*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x507a0*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x507a1*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x507a2*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x507a3*4+0x02000000,0xb0e); +reg_write( DDR_REG_BASE +0x507a4*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x507a5*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x507a6*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x507a7*4+0x02000000,0x43a9); +reg_write( DDR_REG_BASE +0x507a8*4+0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x507a9*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x507aa*4+0x02000000,0x641); +reg_write( DDR_REG_BASE +0x507ab*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x507ac*4+0x02000000,0x1c80); +reg_write( DDR_REG_BASE +0x507ad*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x507ae*4+0x02000000,0xdda); +reg_write( DDR_REG_BASE +0x507af*4+0x02000000,0x260); +reg_write( DDR_REG_BASE +0x507b0*4+0x02000000,0x60f8); +reg_write( DDR_REG_BASE +0x507b1*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x507b2*4+0x02000000,0xbef); +reg_write( DDR_REG_BASE +0x507b3*4+0x02000000,0x8094); +reg_write( DDR_REG_BASE +0x507b4*4+0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x507b5*4+0x02000000,0xbfd); +reg_write( DDR_REG_BASE +0x507b6*4+0x02000000,0x90b4); +reg_write( DDR_REG_BASE +0x507b7*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x507b8*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x507b9*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x507ba*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x507bb*4+0x02000000,0xa8ae); +reg_write( DDR_REG_BASE +0x507bc*4+0x02000000,0xa8a1); +reg_write( DDR_REG_BASE +0x507bd*4+0x02000000,0xa8a0); +reg_write( DDR_REG_BASE +0x507be*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x507bf*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x507c0*4+0x02000000,0x7d8); +reg_write( DDR_REG_BASE +0x507c1*4+0x02000000,0x972); +reg_write( DDR_REG_BASE +0x507c2*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x507c3*4+0x02000000,0xa0e0); +reg_write( DDR_REG_BASE +0x507c4*4+0x02000000,0x976); +reg_write( DDR_REG_BASE +0x507c5*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x507c6*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x507c7*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x507c8*4+0x02000000,0xec2); +reg_write( DDR_REG_BASE +0x507c9*4+0x02000000,0x260); +reg_write( DDR_REG_BASE +0x507ca*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x507cb*4+0x02000000,0x236f); +reg_write( DDR_REG_BASE +0x507cc*4+0x02000000,0x30c3); +reg_write( DDR_REG_BASE +0x507cd*4+0x02000000,0x1318); +reg_write( DDR_REG_BASE +0x507ce*4+0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x507cf*4+0x02000000,0xe809); +reg_write( DDR_REG_BASE +0x507d0*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x507d1*4+0x02000000,0xad); +reg_write( DDR_REG_BASE +0x507d2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x507d3*4+0x02000000,0xf1a); +reg_write( DDR_REG_BASE +0x507d4*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x507d5*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x507d6*4+0x02000000,0xf01f); +reg_write( DDR_REG_BASE +0x507d7*4+0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x507d8*4+0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x507d9*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x507da*4+0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x507db*4+0x02000000,0x8480); +reg_write( DDR_REG_BASE +0x507dc*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x507dd*4+0x02000000,0x5f5); +reg_write( DDR_REG_BASE +0x507de*4+0x02000000,0xe100); +reg_write( DDR_REG_BASE +0x507df*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x507e0*4+0x02000000,0x808d); +reg_write( DDR_REG_BASE +0x507e1*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x507e2*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x507e3*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x507e4*4+0x02000000,0x916); +reg_write( DDR_REG_BASE +0x507e5*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x507e6*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x507e7*4+0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x507e8*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x507e9*4+0x02000000,0x3b9a); +reg_write( DDR_REG_BASE +0x507ea*4+0x02000000,0xca00); +reg_write( DDR_REG_BASE +0x507eb*4+0x02000000,0x26ca); +reg_write( DDR_REG_BASE +0x507ec*4+0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x507ed*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x507ee*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x507ef*4+0x02000000,0x70c5); +reg_write( DDR_REG_BASE +0x507f0*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x507f1*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x507f2*4+0x02000000,0x8fa); +reg_write( DDR_REG_BASE +0x507f3*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x507f4*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x507f5*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x507f6*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x507f7*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x507f8*4+0x02000000,0xd); +reg_write( DDR_REG_BASE +0x507f9*4+0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x507fa*4+0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x507fb*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x507fc*4+0x02000000,0x7045); +reg_write( DDR_REG_BASE +0x507fd*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x507fe*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x507ff*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50800*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50801*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x50802*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x50803*4+0x02000000,0x8b7); +reg_write( DDR_REG_BASE +0x50804*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x50805*4+0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x50806*4+0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x50807*4+0x02000000,0x8af); +reg_write( DDR_REG_BASE +0x50808*4+0x02000000,0xdf); +reg_write( DDR_REG_BASE +0x50809*4+0x02000000,0xdde); +reg_write( DDR_REG_BASE +0x5080a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5080b*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5080c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5080d*4+0x02000000,0xa00); +reg_write( DDR_REG_BASE +0x5080e*4+0x02000000,0x9e2); +reg_write( DDR_REG_BASE +0x5080f*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50810*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x50811*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50812*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50813*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50814*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x50815*4+0x02000000,0x736c); +reg_write( DDR_REG_BASE +0x50816*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x50817*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50818*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x50819*4+0x02000000,0xaa6); +reg_write( DDR_REG_BASE +0x5081a*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5081b*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5081c*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x5081d*4+0x02000000,0x825); +reg_write( DDR_REG_BASE +0x5081e*4+0x02000000,0xb4); +reg_write( DDR_REG_BASE +0x5081f*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50820*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x50821*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50822*4+0x02000000,0xb862); +reg_write( DDR_REG_BASE +0x50823*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x50824*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x50825*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50826*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x50827*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x50828*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50829*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5082a*4+0x02000000,0xa82); +reg_write( DDR_REG_BASE +0x5082b*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5082c*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5082d*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x5082e*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5082f*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50830*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50831*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x50832*4+0x02000000,0xdb0c); +reg_write( DDR_REG_BASE +0x50833*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50834*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x50835*4+0x02000000,0xa6e); +reg_write( DDR_REG_BASE +0x50836*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50837*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x50838*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x50839*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x5083a*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5083b*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5083c*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5083d*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5083e*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5083f*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x50840*4+0x02000000,0xa56); +reg_write( DDR_REG_BASE +0x50841*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50842*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x50843*4+0x02000000,0xc9e); +reg_write( DDR_REG_BASE +0x50844*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50845*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50846*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x50847*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50848*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x50849*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5084a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5084b*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5084c*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5084d*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5084e*4+0x02000000,0xa3a); +reg_write( DDR_REG_BASE +0x5084f*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50850*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x50851*4+0x02000000,0xc66); +reg_write( DDR_REG_BASE +0x50852*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50853*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50854*4+0x02000000,0x922); +reg_write( DDR_REG_BASE +0x50855*4+0x02000000,0x280); +reg_write( DDR_REG_BASE +0x50856*4+0x02000000,0xd896); +reg_write( DDR_REG_BASE +0x50857*4+0x02000000,0x9ea); +reg_write( DDR_REG_BASE +0x50858*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50859*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5085a*4+0x02000000,0xf3e); +reg_write( DDR_REG_BASE +0x5085b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5085c*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x5085d*4+0x02000000,0xcfa); +reg_write( DDR_REG_BASE +0x5085e*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x5085f*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50860*4+0x02000000,0xf); +reg_write( DDR_REG_BASE +0x50861*4+0x02000000,0x4240); +reg_write( DDR_REG_BASE +0x50862*4+0x02000000,0x81a); +reg_write( DDR_REG_BASE +0x50863*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x50864*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50865*4+0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x50866*4+0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x50867*4+0x02000000,0x83f); +reg_write( DDR_REG_BASE +0x50868*4+0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x50869*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x5086a*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5086b*4+0x02000000,0x14); +reg_write( DDR_REG_BASE +0x5086c*4+0x02000000,0x9320); +reg_write( DDR_REG_BASE +0x5086d*4+0x02000000,0xca01); +reg_write( DDR_REG_BASE +0x5086e*4+0x02000000,0x80d); +reg_write( DDR_REG_BASE +0x5086f*4+0x02000000,0x1b0); +reg_write( DDR_REG_BASE +0x50870*4+0x02000000,0x214f); +reg_write( DDR_REG_BASE +0x50871*4+0x02000000,0x82); +reg_write( DDR_REG_BASE +0x50872*4+0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x50873*4+0x02000000,0xd1); +reg_write( DDR_REG_BASE +0x50874*4+0x02000000,0x2185); +reg_write( DDR_REG_BASE +0x50875*4+0x02000000,0x108); +reg_write( DDR_REG_BASE +0x50876*4+0x02000000,0x4220); +reg_write( DDR_REG_BASE +0x50877*4+0x02000000,0xb340); +reg_write( DDR_REG_BASE +0x50878*4+0x02000000,0xd823); +reg_write( DDR_REG_BASE +0x50879*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x5087a*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x5087b*4+0x02000000,0xe034); +reg_write( DDR_REG_BASE +0x5087c*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x5087d*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5087e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5087f*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x50880*4+0x02000000,0xe034); +reg_write( DDR_REG_BASE +0x50881*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x50882*4+0x02000000,0xb8b1); +reg_write( DDR_REG_BASE +0x50883*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x50884*4+0x02000000,0xb221); +reg_write( DDR_REG_BASE +0x50885*4+0x02000000,0xddff); +reg_write( DDR_REG_BASE +0x50886*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x50887*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50888*4+0x02000000,0x228a); +reg_write( DDR_REG_BASE +0x50889*4+0x02000000,0xdff); +reg_write( DDR_REG_BASE +0x5088a*4+0x02000000,0x776c); +reg_write( DDR_REG_BASE +0x5088b*4+0x02000000,0xb06); +reg_write( DDR_REG_BASE +0x5088c*4+0x02000000,0x320); +reg_write( DDR_REG_BASE +0x5088d*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5088e*4+0x02000000,0x774c); +reg_write( DDR_REG_BASE +0x5088f*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x50890*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x50891*4+0x02000000,0x4340); +reg_write( DDR_REG_BASE +0x50892*4+0x02000000,0xaf6); +reg_write( DDR_REG_BASE +0x50893*4+0x02000000,0x320); +reg_write( DDR_REG_BASE +0x50894*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x50895*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x50896*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50897*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50898*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50899*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5089a*4+0x02000000,0xca04); +reg_write( DDR_REG_BASE +0x5089b*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5089c*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x5089d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5089e*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x5089f*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x508a0*4+0x02000000,0x8b20); +reg_write( DDR_REG_BASE +0x508a1*4+0x02000000,0xa0d); +reg_write( DDR_REG_BASE +0x508a2*4+0x02000000,0x44); +reg_write( DDR_REG_BASE +0x508a3*4+0x02000000,0x8b21); +reg_write( DDR_REG_BASE +0x508a4*4+0x02000000,0x919); +reg_write( DDR_REG_BASE +0x508a5*4+0x02000000,0x85); +reg_write( DDR_REG_BASE +0x508a6*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x508a7*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x508a8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x508a9*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x508aa*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x508ab*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x508ac*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x508ad*4+0x02000000,0x1f64); +reg_write( DDR_REG_BASE +0x508ae*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x508af*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x508b0*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x508b1*4+0x02000000,0xae1); +reg_write( DDR_REG_BASE +0x508b2*4+0x02000000,0x8004); +reg_write( DDR_REG_BASE +0x508b3*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x508b4*4+0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x508b5*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x508b6*4+0x02000000,0xbd9a); +reg_write( DDR_REG_BASE +0x508b7*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x508b8*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x508b9*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x508ba*4+0x02000000,0xd4a); +reg_write( DDR_REG_BASE +0x508bb*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x508bc*4+0x02000000,0x1a09); +reg_write( DDR_REG_BASE +0x508bd*4+0x02000000,0x3003); +reg_write( DDR_REG_BASE +0x508be*4+0x02000000,0xca6); +reg_write( DDR_REG_BASE +0x508bf*4+0x02000000,0x240); +reg_write( DDR_REG_BASE +0x508c0*4+0x02000000,0x254f); +reg_write( DDR_REG_BASE +0x508c1*4+0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x508c2*4+0x02000000,0xd3a); +reg_write( DDR_REG_BASE +0x508c3*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x508c4*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x508c5*4+0x02000000,0xfd2); +reg_write( DDR_REG_BASE +0x508c6*4+0x02000000,0x2a0); +reg_write( DDR_REG_BASE +0x508c7*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x508c8*4+0x02000000,0x26ab); +reg_write( DDR_REG_BASE +0x508c9*4+0x02000000,0x10c4); +reg_write( DDR_REG_BASE +0x508ca*4+0x02000000,0x7fff); +reg_write( DDR_REG_BASE +0x508cb*4+0x02000000,0xf000); +reg_write( DDR_REG_BASE +0x508cc*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x508cd*4+0x02000000,0xc1a5); +reg_write( DDR_REG_BASE +0x508ce*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x508cf*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x508d0*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x508d1*4+0x02000000,0xa3a); +reg_write( DDR_REG_BASE +0x508d2*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x508d3*4+0x02000000,0xda14); +reg_write( DDR_REG_BASE +0x508d4*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x508d5*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x508d6*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x508d7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x508d8*4+0x02000000,0xc180); +reg_write( DDR_REG_BASE +0x508d9*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x508da*4+0x02000000,0xe3a); +reg_write( DDR_REG_BASE +0x508db*4+0x02000000,0x220); +reg_write( DDR_REG_BASE +0x508dc*4+0x02000000,0xb885); +reg_write( DDR_REG_BASE +0x508dd*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x508de*4+0x02000000,0xf6); +reg_write( DDR_REG_BASE +0x508df*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x508e0*4+0x02000000,0xcfe); +reg_write( DDR_REG_BASE +0x508e1*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x508e2*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x508e3*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x508e4*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x508e5*4+0x02000000,0xf32); +reg_write( DDR_REG_BASE +0x508e6*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x508e7*4+0x02000000,0xc280); +reg_write( DDR_REG_BASE +0x508e8*4+0x02000000,0xc0a5); +reg_write( DDR_REG_BASE +0x508e9*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x508ea*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x508eb*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x508ec*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x508ed*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x508ee*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x508ef*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x508f0*4+0x02000000,0x3d02); +reg_write( DDR_REG_BASE +0x508f1*4+0x02000000,0x4748); +reg_write( DDR_REG_BASE +0x508f2*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x508f3*4+0x02000000,0x4308); +reg_write( DDR_REG_BASE +0x508f4*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x508f5*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x508f6*4+0x02000000,0x9ee); +reg_write( DDR_REG_BASE +0x508f7*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x508f8*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x508f9*4+0x02000000,0xb25); +reg_write( DDR_REG_BASE +0x508fa*4+0x02000000,0x10b1); +reg_write( DDR_REG_BASE +0x508fb*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x508fc*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x508fd*4+0x02000000,0xf2); +reg_write( DDR_REG_BASE +0x508fe*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x508ff*4+0x02000000,0xcc2); +reg_write( DDR_REG_BASE +0x50900*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50901*4+0x02000000,0x4260); +reg_write( DDR_REG_BASE +0x50902*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x50903*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50904*4+0x02000000,0xf3a); +reg_write( DDR_REG_BASE +0x50905*4+0x02000000,0x220); +reg_write( DDR_REG_BASE +0x50906*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x50907*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50908*4+0x02000000,0xd909); +reg_write( DDR_REG_BASE +0x50909*4+0x02000000,0xf036); +reg_write( DDR_REG_BASE +0x5090a*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x5090b*4+0x02000000,0x3f9b); +reg_write( DDR_REG_BASE +0x5090c*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5090d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5090e*4+0x02000000,0xb1b); +reg_write( DDR_REG_BASE +0x5090f*4+0x02000000,0x1030); +reg_write( DDR_REG_BASE +0x50910*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x50911*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50912*4+0x02000000,0xf4); +reg_write( DDR_REG_BASE +0x50913*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50914*4+0x02000000,0xc96); +reg_write( DDR_REG_BASE +0x50915*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50916*4+0x02000000,0x4260); +reg_write( DDR_REG_BASE +0x50917*4+0x02000000,0xdd09); +reg_write( DDR_REG_BASE +0x50918*4+0x02000000,0xdec0); +reg_write( DDR_REG_BASE +0x50919*4+0x02000000,0xd8d0); +reg_write( DDR_REG_BASE +0x5091a*4+0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x5091b*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5091c*4+0x02000000,0xf3); +reg_write( DDR_REG_BASE +0x5091d*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5091e*4+0x02000000,0xc82); +reg_write( DDR_REG_BASE +0x5091f*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50920*4+0x02000000,0x4260); +reg_write( DDR_REG_BASE +0x50921*4+0x02000000,0x72ad); +reg_write( DDR_REG_BASE +0x50922*4+0x02000000,0xde8c); +reg_write( DDR_REG_BASE +0x50923*4+0x02000000,0xd880); +reg_write( DDR_REG_BASE +0x50924*4+0x02000000,0x60f8); +reg_write( DDR_REG_BASE +0x50925*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x50926*4+0x02000000,0x6c0); +reg_write( DDR_REG_BASE +0x50927*4+0x02000000,0xc180); +reg_write( DDR_REG_BASE +0x50928*4+0x02000000,0xd9e); +reg_write( DDR_REG_BASE +0x50929*4+0x02000000,0x220); +reg_write( DDR_REG_BASE +0x5092a*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x5092b*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5092c*4+0x02000000,0x722c); +reg_write( DDR_REG_BASE +0x5092d*4+0x02000000,0xea2); +reg_write( DDR_REG_BASE +0x5092e*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x5092f*4+0x02000000,0xc280); +reg_write( DDR_REG_BASE +0x50930*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x50931*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50932*4+0x02000000,0x976); +reg_write( DDR_REG_BASE +0x50933*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x50934*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x50935*4+0x02000000,0x66fe); +reg_write( DDR_REG_BASE +0x50936*4+0x02000000,0x2605); +reg_write( DDR_REG_BASE +0x50937*4+0x02000000,0x16c0); +reg_write( DDR_REG_BASE +0x50938*4+0x02000000,0xc180); +reg_write( DDR_REG_BASE +0x50939*4+0x02000000,0xd7e); +reg_write( DDR_REG_BASE +0x5093a*4+0x02000000,0x220); +reg_write( DDR_REG_BASE +0x5093b*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x5093c*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5093d*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x5093e*4+0x02000000,0xe7e); +reg_write( DDR_REG_BASE +0x5093f*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50940*4+0x02000000,0xc280); +reg_write( DDR_REG_BASE +0x50941*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x50942*4+0x02000000,0x3d02); +reg_write( DDR_REG_BASE +0x50943*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50944*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50945*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50946*4+0x02000000,0xc3e2); +reg_write( DDR_REG_BASE +0x50947*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x50948*4+0x02000000,0x3d02); +reg_write( DDR_REG_BASE +0x50949*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x5094a*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x5094b*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x5094c*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5094d*4+0x02000000,0x942); +reg_write( DDR_REG_BASE +0x5094e*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x5094f*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x50950*4+0x02000000,0x2354); +reg_write( DDR_REG_BASE +0x50951*4+0x02000000,0xd00); +reg_write( DDR_REG_BASE +0x50952*4+0x02000000,0xc180); +reg_write( DDR_REG_BASE +0x50953*4+0x02000000,0xd4a); +reg_write( DDR_REG_BASE +0x50954*4+0x02000000,0x220); +reg_write( DDR_REG_BASE +0x50955*4+0x02000000,0xda09); +reg_write( DDR_REG_BASE +0x50956*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x50957*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50958*4+0x02000000,0xf5); +reg_write( DDR_REG_BASE +0x50959*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5095a*4+0x02000000,0xc0a); +reg_write( DDR_REG_BASE +0x5095b*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5095c*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x5095d*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5095e*4+0x02000000,0xd909); +reg_write( DDR_REG_BASE +0x5095f*4+0x02000000,0xe3e); +reg_write( DDR_REG_BASE +0x50960*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50961*4+0x02000000,0xc280); +reg_write( DDR_REG_BASE +0x50962*4+0x02000000,0xc7c2); +reg_write( DDR_REG_BASE +0x50963*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50964*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x50965*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x50966*4+0x02000000,0x3d02); +reg_write( DDR_REG_BASE +0x50967*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x50968*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50969*4+0x02000000,0x90a); +reg_write( DDR_REG_BASE +0x5096a*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x5096b*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x5096c*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5096d*4+0x02000000,0xf7); +reg_write( DDR_REG_BASE +0x5096e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5096f*4+0x02000000,0xbe2); +reg_write( DDR_REG_BASE +0x50970*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50971*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x50972*4+0x02000000,0xd840); +reg_write( DDR_REG_BASE +0x50973*4+0x02000000,0xc180); +reg_write( DDR_REG_BASE +0x50974*4+0x02000000,0xd06); +reg_write( DDR_REG_BASE +0x50975*4+0x02000000,0x220); +reg_write( DDR_REG_BASE +0x50976*4+0x02000000,0xda09); +reg_write( DDR_REG_BASE +0x50977*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50978*4+0x02000000,0xd909); +reg_write( DDR_REG_BASE +0x50979*4+0x02000000,0xe0a); +reg_write( DDR_REG_BASE +0x5097a*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x5097b*4+0x02000000,0xc280); +reg_write( DDR_REG_BASE +0x5097c*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x5097d*4+0x02000000,0x3d02); +reg_write( DDR_REG_BASE +0x5097e*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x5097f*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50980*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50981*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x50982*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50983*4+0x02000000,0x12); +reg_write( DDR_REG_BASE +0x50984*4+0x02000000,0x7534); +reg_write( DDR_REG_BASE +0x50985*4+0x02000000,0x20e0); +reg_write( DDR_REG_BASE +0x50986*4+0x02000000,0x7c5); +reg_write( DDR_REG_BASE +0x50987*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50988*4+0x02000000,0x1a09); +reg_write( DDR_REG_BASE +0x50989*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x5098a*4+0x02000000,0xc0e6); +reg_write( DDR_REG_BASE +0x5098b*4+0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x5098c*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5098d*4+0x02000000,0xe4); +reg_write( DDR_REG_BASE +0x5098e*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x5098f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50990*4+0x02000000,0x7cb); +reg_write( DDR_REG_BASE +0x50991*4+0x02000000,0x835); +reg_write( DDR_REG_BASE +0x50992*4+0x02000000,0xb0); +reg_write( DDR_REG_BASE +0x50993*4+0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x50994*4+0x02000000,0x7114); +reg_write( DDR_REG_BASE +0x50995*4+0x02000000,0xd825); +reg_write( DDR_REG_BASE +0x50996*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50997*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50998*4+0x02000000,0x30); +reg_write( DDR_REG_BASE +0x50999*4+0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x5099a*4+0x02000000,0xf42a); +reg_write( DDR_REG_BASE +0x5099b*4+0x02000000,0x8a25); +reg_write( DDR_REG_BASE +0x5099c*4+0x02000000,0xaa23); +reg_write( DDR_REG_BASE +0x5099d*4+0x02000000,0x8aa4); +reg_write( DDR_REG_BASE +0x5099e*4+0x02000000,0x7b34); +reg_write( DDR_REG_BASE +0x5099f*4+0x02000000,0xaaa2); +reg_write( DDR_REG_BASE +0x509a0*4+0x02000000,0x96c0); +reg_write( DDR_REG_BASE +0x509a1*4+0x02000000,0x88e0); +reg_write( DDR_REG_BASE +0x509a2*4+0x02000000,0x78bb); +reg_write( DDR_REG_BASE +0x509a3*4+0x02000000,0xb4e0); +reg_write( DDR_REG_BASE +0x509a4*4+0x02000000,0xaa00); +reg_write( DDR_REG_BASE +0x509a5*4+0x02000000,0xe5f); +reg_write( DDR_REG_BASE +0x509a6*4+0x02000000,0x1171); +reg_write( DDR_REG_BASE +0x509a7*4+0x02000000,0xaa61); +reg_write( DDR_REG_BASE +0x509a8*4+0x02000000,0xb4e1); +reg_write( DDR_REG_BASE +0x509a9*4+0x02000000,0xf02d); +reg_write( DDR_REG_BASE +0x509aa*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x509ab*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x509ac*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x509ad*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x509ae*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x509af*4+0x02000000,0x58); +reg_write( DDR_REG_BASE +0x509b0*4+0x02000000,0xb421); +reg_write( DDR_REG_BASE +0x509b1*4+0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x509b2*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x509b3*4+0x02000000,0xf6); +reg_write( DDR_REG_BASE +0x509b4*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x509b5*4+0x02000000,0xb404); +reg_write( DDR_REG_BASE +0x509b6*4+0x02000000,0x1c06); +reg_write( DDR_REG_BASE +0x509b7*4+0x02000000,0x13c5); +reg_write( DDR_REG_BASE +0x509b8*4+0x02000000,0x8a27); +reg_write( DDR_REG_BASE +0x509b9*4+0x02000000,0xaa23); +reg_write( DDR_REG_BASE +0x509ba*4+0x02000000,0x8a06); +reg_write( DDR_REG_BASE +0x509bb*4+0x02000000,0x7b34); +reg_write( DDR_REG_BASE +0x509bc*4+0x02000000,0xaa02); +reg_write( DDR_REG_BASE +0x509bd*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x509be*4+0x02000000,0xaa00); +reg_write( DDR_REG_BASE +0x509bf*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x509c0*4+0x02000000,0xaa61); +reg_write( DDR_REG_BASE +0x509c1*4+0x02000000,0x1cfe); +reg_write( DDR_REG_BASE +0x509c2*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x509c3*4+0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x509c4*4+0x02000000,0x88a0); +reg_write( DDR_REG_BASE +0x509c5*4+0x02000000,0xb4a0); +reg_write( DDR_REG_BASE +0x509c6*4+0x02000000,0x8a27); +reg_write( DDR_REG_BASE +0x509c7*4+0x02000000,0xaa23); +reg_write( DDR_REG_BASE +0x509c8*4+0x02000000,0x8a04); +reg_write( DDR_REG_BASE +0x509c9*4+0x02000000,0x7b34); +reg_write( DDR_REG_BASE +0x509ca*4+0x02000000,0xaa02); +reg_write( DDR_REG_BASE +0x509cb*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x509cc*4+0x02000000,0xaa00); +reg_write( DDR_REG_BASE +0x509cd*4+0x02000000,0xaa61); +reg_write( DDR_REG_BASE +0x509ce*4+0x02000000,0x9600); +reg_write( DDR_REG_BASE +0x509cf*4+0x02000000,0x829); +reg_write( DDR_REG_BASE +0x509d0*4+0x02000000,0x151); +reg_write( DDR_REG_BASE +0x509d1*4+0x02000000,0xb4a1); +reg_write( DDR_REG_BASE +0x509d2*4+0x02000000,0xf015); +reg_write( DDR_REG_BASE +0x509d3*4+0x02000000,0x1c02); +reg_write( DDR_REG_BASE +0x509d4*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x509d5*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x509d6*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x509d7*4+0x02000000,0xfe); +reg_write( DDR_REG_BASE +0x509d8*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x509d9*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x509da*4+0x02000000,0x3c5); +reg_write( DDR_REG_BASE +0x509db*4+0x02000000,0x19f8); +reg_write( DDR_REG_BASE +0x509dc*4+0x02000000,0x8004); +reg_write( DDR_REG_BASE +0x509dd*4+0x02000000,0x19f6); +reg_write( DDR_REG_BASE +0x509de*4+0x02000000,0x8005); +reg_write( DDR_REG_BASE +0x509df*4+0x02000000,0x19fe); +reg_write( DDR_REG_BASE +0x509e0*4+0x02000000,0x8005); +reg_write( DDR_REG_BASE +0x509e1*4+0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x509e2*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x509e3*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x509e4*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x509e5*4+0x02000000,0x58); +reg_write( DDR_REG_BASE +0x509e6*4+0x02000000,0xb401); +reg_write( DDR_REG_BASE +0x509e7*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x509e8*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x509e9*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x509ea*4+0x02000000,0xf6); +reg_write( DDR_REG_BASE +0x509eb*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x509ec*4+0x02000000,0xb024); +reg_write( DDR_REG_BASE +0x509ed*4+0x02000000,0x18fe); +reg_write( DDR_REG_BASE +0x509ee*4+0x02000000,0x8044); +reg_write( DDR_REG_BASE +0x509ef*4+0x02000000,0xb023); +reg_write( DDR_REG_BASE +0x509f0*4+0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x509f1*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x509f2*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x509f3*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x509f4*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x509f5*4+0x02000000,0xc1a5); +reg_write( DDR_REG_BASE +0x509f6*4+0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x509f7*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x509f8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x509f9*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x509fa*4+0x02000000,0x88c0); +reg_write( DDR_REG_BASE +0x509fb*4+0x02000000,0x2753); +reg_write( DDR_REG_BASE +0x509fc*4+0x02000000,0x1040); +reg_write( DDR_REG_BASE +0x509fd*4+0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x509fe*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x509ff*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x50a00*4+0x02000000,0xc144); +reg_write( DDR_REG_BASE +0x50a01*4+0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x50a02*4+0x02000000,0xcde); +reg_write( DDR_REG_BASE +0x50a03*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50a04*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x50a05*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x50a06*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50a07*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x50a08*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x50a09*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50a0a*4+0x02000000,0x9d6); +reg_write( DDR_REG_BASE +0x50a0b*4+0x02000000,0x260); +reg_write( DDR_REG_BASE +0x50a0c*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50a0d*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50a0e*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50a0f*4+0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x50a10*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50a11*4+0x02000000,0xda40); +reg_write( DDR_REG_BASE +0x50a12*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50a13*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50a14*4+0x02000000,0x95e); +reg_write( DDR_REG_BASE +0x50a15*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50a16*4+0x02000000,0xda7f); +reg_write( DDR_REG_BASE +0x50a17*4+0x02000000,0x275f); +reg_write( DDR_REG_BASE +0x50a18*4+0x02000000,0x1100); +reg_write( DDR_REG_BASE +0x50a19*4+0x02000000,0x43db); +reg_write( DDR_REG_BASE +0x50a1a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50a1b*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x50a1c*4+0x02000000,0x7f05); +reg_write( DDR_REG_BASE +0x50a1d*4+0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x50a1e*4+0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x50a1f*4+0x02000000,0xe814); +reg_write( DDR_REG_BASE +0x50a20*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50a21*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50a22*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50a23*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50a24*4+0x02000000,0x81d); +reg_write( DDR_REG_BASE +0x50a25*4+0x02000000,0xdf); +reg_write( DDR_REG_BASE +0x50a26*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50a27*4+0x02000000,0xf863); +reg_write( DDR_REG_BASE +0x50a28*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x50a29*4+0x02000000,0x3001); +reg_write( DDR_REG_BASE +0x50a2a*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x50a2b*4+0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x50a2c*4+0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x50a2d*4+0x02000000,0x61b9); +reg_write( DDR_REG_BASE +0x50a2e*4+0x02000000,0xd2a); +reg_write( DDR_REG_BASE +0x50a2f*4+0x02000000,0x2e0); +reg_write( DDR_REG_BASE +0x50a30*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50a31*4+0x02000000,0xf00b); +reg_write( DDR_REG_BASE +0x50a32*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50a33*4+0x02000000,0xf85d); +reg_write( DDR_REG_BASE +0x50a34*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x50a35*4+0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x50a36*4+0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x50a37*4+0x02000000,0x61b9); +reg_write( DDR_REG_BASE +0x50a38*4+0x02000000,0xbce); +reg_write( DDR_REG_BASE +0x50a39*4+0x02000000,0x2e0); +reg_write( DDR_REG_BASE +0x50a3a*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50a3b*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50a3c*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x50a3d*4+0x02000000,0xe04c); +reg_write( DDR_REG_BASE +0x50a3e*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x50a3f*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x50a40*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x50a41*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x50a42*4+0x02000000,0x18fc); +reg_write( DDR_REG_BASE +0x50a43*4+0x02000000,0x8044); +reg_write( DDR_REG_BASE +0x50a44*4+0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x50a45*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x50a46*4+0x02000000,0xe8aa); +reg_write( DDR_REG_BASE +0x50a47*4+0x02000000,0xf022); +reg_write( DDR_REG_BASE +0x50a48*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x50a49*4+0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x50a4a*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50a4b*4+0x02000000,0x2116); +reg_write( DDR_REG_BASE +0x50a4c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50a4d*4+0x02000000,0x7061); +reg_write( DDR_REG_BASE +0x50a4e*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x50a4f*4+0x02000000,0xf9e); +reg_write( DDR_REG_BASE +0x50a50*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50a51*4+0x02000000,0x7a8); +reg_write( DDR_REG_BASE +0x50a52*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x50a53*4+0x02000000,0xe06); +reg_write( DDR_REG_BASE +0x50a54*4+0x02000000,0x260); +reg_write( DDR_REG_BASE +0x50a55*4+0x02000000,0x210a); +reg_write( DDR_REG_BASE +0x50a56*4+0x02000000,0x780); +reg_write( DDR_REG_BASE +0x50a57*4+0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x50a58*4+0x02000000,0x3f82); +reg_write( DDR_REG_BASE +0x50a59*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50a5a*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x50a5b*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50a5c*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50a5d*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50a5e*4+0x02000000,0xb88a); +reg_write( DDR_REG_BASE +0x50a5f*4+0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x50a60*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x50a61*4+0x02000000,0x43); +reg_write( DDR_REG_BASE +0x50a62*4+0x02000000,0xb964); +reg_write( DDR_REG_BASE +0x50a63*4+0x02000000,0x7945); +reg_write( DDR_REG_BASE +0x50a64*4+0x02000000,0xb300); +reg_write( DDR_REG_BASE +0x50a65*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50a66*4+0x02000000,0xfc5); +reg_write( DDR_REG_BASE +0x50a67*4+0x02000000,0xb300); +reg_write( DDR_REG_BASE +0x50a68*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50a69*4+0x02000000,0x78d4); +reg_write( DDR_REG_BASE +0x50a6a*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x50a6b*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50a6c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50a6d*4+0x02000000,0x784); +reg_write( DDR_REG_BASE +0x50a6e*4+0x02000000,0xbb5); +reg_write( DDR_REG_BASE +0x50a6f*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50a70*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50a71*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50a72*4+0x02000000,0x8a2); +reg_write( DDR_REG_BASE +0x50a73*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50a74*4+0x02000000,0xda7f); +reg_write( DDR_REG_BASE +0x50a75*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50a76*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50a77*4+0x02000000,0xebe); +reg_write( DDR_REG_BASE +0x50a78*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50a79*4+0x02000000,0xda49); +reg_write( DDR_REG_BASE +0x50a7a*4+0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x50a7b*4+0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x50a7c*4+0x02000000,0xe813); +reg_write( DDR_REG_BASE +0x50a7d*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50a7e*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50a7f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50a80*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50a81*4+0x02000000,0x81f); +reg_write( DDR_REG_BASE +0x50a82*4+0x02000000,0xdf); +reg_write( DDR_REG_BASE +0x50a83*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50a84*4+0x02000000,0xf82f); +reg_write( DDR_REG_BASE +0x50a85*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x50a86*4+0x02000000,0x3001); +reg_write( DDR_REG_BASE +0x50a87*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x50a88*4+0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x50a89*4+0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x50a8a*4+0x02000000,0x61b9); +reg_write( DDR_REG_BASE +0x50a8b*4+0x02000000,0xc72); +reg_write( DDR_REG_BASE +0x50a8c*4+0x02000000,0x2e0); +reg_write( DDR_REG_BASE +0x50a8d*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50a8e*4+0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x50a8f*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50a90*4+0x02000000,0xf829); +reg_write( DDR_REG_BASE +0x50a91*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x50a92*4+0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x50a93*4+0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x50a94*4+0x02000000,0x61b9); +reg_write( DDR_REG_BASE +0x50a95*4+0x02000000,0xb16); +reg_write( DDR_REG_BASE +0x50a96*4+0x02000000,0x2e0); +reg_write( DDR_REG_BASE +0x50a97*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50a98*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50a99*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50a9a*4+0x02000000,0x2710); +reg_write( DDR_REG_BASE +0x50a9b*4+0x02000000,0xbaa); +reg_write( DDR_REG_BASE +0x50a9c*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50a9d*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50a9e*4+0x02000000,0x952); +reg_write( DDR_REG_BASE +0x50a9f*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x50aa0*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50aa1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50aa2*4+0x02000000,0x1d4c); +reg_write( DDR_REG_BASE +0x50aa3*4+0x02000000,0xb9a); +reg_write( DDR_REG_BASE +0x50aa4*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50aa5*4+0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x50aa6*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50aa7*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x50aa8*4+0x02000000,0xf7a0); +reg_write( DDR_REG_BASE +0x50aa9*4+0x02000000,0xb8e); +reg_write( DDR_REG_BASE +0x50aaa*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50aab*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50aac*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50aad*4+0x02000000,0xc92); +reg_write( DDR_REG_BASE +0x50aae*4+0x02000000,0x220); +reg_write( DDR_REG_BASE +0x50aaf*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50ab0*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x50ab1*4+0x02000000,0xe8ad); +reg_write( DDR_REG_BASE +0x50ab2*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50ab3*4+0x02000000,0xf023); +reg_write( DDR_REG_BASE +0x50ab4*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x50ab5*4+0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x50ab6*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50ab7*4+0x02000000,0x7916); +reg_write( DDR_REG_BASE +0x50ab8*4+0x02000000,0x61b8); +reg_write( DDR_REG_BASE +0x50ab9*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x50aba*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x50abb*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50abc*4+0x02000000,0x7a8); +reg_write( DDR_REG_BASE +0x50abd*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x50abe*4+0x02000000,0xd2e); +reg_write( DDR_REG_BASE +0x50abf*4+0x02000000,0x260); +reg_write( DDR_REG_BASE +0x50ac0*4+0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x50ac1*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50ac2*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x50ac3*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x50ac4*4+0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x50ac5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50ac6*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x50ac7*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x50ac8*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x50ac9*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x50aca*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50acb*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50acc*4+0x02000000,0xb260); +reg_write( DDR_REG_BASE +0x50acd*4+0x02000000,0x204f); +reg_write( DDR_REG_BASE +0x50ace*4+0x02000000,0x283); +reg_write( DDR_REG_BASE +0x50acf*4+0x02000000,0xb260); +reg_write( DDR_REG_BASE +0x50ad0*4+0x02000000,0x9e7); +reg_write( DDR_REG_BASE +0x50ad1*4+0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x50ad2*4+0x02000000,0x204f); +reg_write( DDR_REG_BASE +0x50ad3*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x50ad4*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x50ad5*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50ad6*4+0x02000000,0x78d4); +reg_write( DDR_REG_BASE +0x50ad7*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x50ad8*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50ad9*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50ada*4+0x02000000,0x784); +reg_write( DDR_REG_BASE +0x50adb*4+0x02000000,0xdb5); +reg_write( DDR_REG_BASE +0x50adc*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50add*4+0x02000000,0xc0a5); +reg_write( DDR_REG_BASE +0x50ade*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50adf*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50ae0*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50ae1*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50ae2*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x50ae3*4+0x02000000,0x1c82); +reg_write( DDR_REG_BASE +0x50ae4*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x50ae5*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x50ae6*4+0x02000000,0xdfff); +reg_write( DDR_REG_BASE +0x50ae7*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x50ae8*4+0x02000000,0x641); +reg_write( DDR_REG_BASE +0x50ae9*4+0x02000000,0x78ef); +reg_write( DDR_REG_BASE +0x50aea*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50aeb*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50aec*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x50aed*4+0x02000000,0x1c82); +reg_write( DDR_REG_BASE +0x50aee*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x50aef*4+0x02000000,0xffbf); +reg_write( DDR_REG_BASE +0x50af0*4+0x02000000,0x87f7); +reg_write( DDR_REG_BASE +0x50af1*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x50af2*4+0x02000000,0x641); +reg_write( DDR_REG_BASE +0x50af3*4+0x02000000,0x78ef); +reg_write( DDR_REG_BASE +0x50af4*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50af5*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50af6*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50af7*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50af8*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50af9*4+0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x50afa*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50afb*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50afc*4+0x02000000,0xf4); +reg_write( DDR_REG_BASE +0x50afd*4+0x02000000,0x9600); +reg_write( DDR_REG_BASE +0x50afe*4+0x02000000,0x6ea2); +reg_write( DDR_REG_BASE +0x50aff*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50b00*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50b01*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50b02*4+0x02000000,0x1500); +reg_write( DDR_REG_BASE +0x50b03*4+0x02000000,0x111b); +reg_write( DDR_REG_BASE +0x50b04*4+0x02000000,0x95e3); +reg_write( DDR_REG_BASE +0x50b05*4+0x02000000,0x1508); +reg_write( DDR_REG_BASE +0x50b06*4+0x02000000,0x110b); +reg_write( DDR_REG_BASE +0x50b07*4+0x02000000,0x1d08); +reg_write( DDR_REG_BASE +0x50b08*4+0x02000000,0x13c5); +reg_write( DDR_REG_BASE +0x50b09*4+0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x50b0a*4+0x02000000,0x1d06); +reg_write( DDR_REG_BASE +0x50b0b*4+0x02000000,0x13c5); +reg_write( DDR_REG_BASE +0x50b0c*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x50b0d*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50b0e*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50b0f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50b10*4+0x02000000,0x7c8); +reg_write( DDR_REG_BASE +0x50b11*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50b12*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x50b13*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x50b14*4+0x02000000,0x190); +reg_write( DDR_REG_BASE +0x50b15*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50b16*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50b17*4+0x02000000,0x2af8); +reg_write( DDR_REG_BASE +0x50b18*4+0x02000000,0xaae); +reg_write( DDR_REG_BASE +0x50b19*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50b1a*4+0x02000000,0x1efa); +reg_write( DDR_REG_BASE +0x50b1b*4+0x02000000,0x9485); +reg_write( DDR_REG_BASE +0x50b1c*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50b1d*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x50b1e*4+0x02000000,0xb5e3); +reg_write( DDR_REG_BASE +0x50b1f*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50b20*4+0x02000000,0x16c4); +reg_write( DDR_REG_BASE +0x50b21*4+0x02000000,0x1d08); +reg_write( DDR_REG_BASE +0x50b22*4+0x02000000,0x12c4); +reg_write( DDR_REG_BASE +0x50b23*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50b24*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50b25*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50b26*4+0x02000000,0x7c8); +reg_write( DDR_REG_BASE +0x50b27*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50b28*4+0x02000000,0xb8a0); +reg_write( DDR_REG_BASE +0x50b29*4+0x02000000,0x6829); +reg_write( DDR_REG_BASE +0x50b2a*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50b2b*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50b2c*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x50b2d*4+0x02000000,0xa821); +reg_write( DDR_REG_BASE +0x50b2e*4+0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x50b2f*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50b30*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50b31*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50b32*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50b33*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50b34*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50b35*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x50b36*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50b37*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x50b38*4+0x02000000,0x9720); +reg_write( DDR_REG_BASE +0x50b39*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50b3a*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50b3b*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50b3c*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50b3d*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50b3e*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x50b3f*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x50b40*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x50b41*4+0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x50b42*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x50b43*4+0x02000000,0xea06); +reg_write( DDR_REG_BASE +0x50b44*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x50b45*4+0x02000000,0xa01); +reg_write( DDR_REG_BASE +0x50b46*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x50b47*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50b48*4+0x02000000,0xb8c3); +reg_write( DDR_REG_BASE +0x50b49*4+0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x50b4a*4+0x02000000,0x70); +reg_write( DDR_REG_BASE +0x50b4b*4+0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x50b4c*4+0x02000000,0x807); +reg_write( DDR_REG_BASE +0x50b4d*4+0x02000000,0x190); +reg_write( DDR_REG_BASE +0x50b4e*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x50b4f*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50b50*4+0x02000000,0xa3e); +reg_write( DDR_REG_BASE +0x50b51*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50b52*4+0x02000000,0xd940); +reg_write( DDR_REG_BASE +0x50b53*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50b54*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x50b55*4+0x02000000,0xe112); +reg_write( DDR_REG_BASE +0x50b56*4+0x02000000,0x1ede); +reg_write( DDR_REG_BASE +0x50b57*4+0x02000000,0x1055); +reg_write( DDR_REG_BASE +0x50b58*4+0x02000000,0x1ea6); +reg_write( DDR_REG_BASE +0x50b59*4+0x02000000,0x9055); +reg_write( DDR_REG_BASE +0x50b5a*4+0x02000000,0x17b6); +reg_write( DDR_REG_BASE +0x50b5b*4+0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x50b5c*4+0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x50b5d*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50b5e*4+0x02000000,0xed29); +reg_write( DDR_REG_BASE +0x50b5f*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50b60*4+0x02000000,0x84f); +reg_write( DDR_REG_BASE +0x50b61*4+0x02000000,0x3bf); +reg_write( DDR_REG_BASE +0x50b62*4+0x02000000,0xd91c); +reg_write( DDR_REG_BASE +0x50b63*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50b64*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x50b65*4+0x02000000,0xc07); +reg_write( DDR_REG_BASE +0x50b66*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50b67*4+0x02000000,0xb88f); +reg_write( DDR_REG_BASE +0x50b68*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x50b69*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50b6a*4+0x02000000,0xa0a); +reg_write( DDR_REG_BASE +0x50b6b*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50b6c*4+0x02000000,0x1ef6); +reg_write( DDR_REG_BASE +0x50b6d*4+0x02000000,0x9205); +reg_write( DDR_REG_BASE +0x50b6e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50b6f*4+0x02000000,0xf); +reg_write( DDR_REG_BASE +0x50b70*4+0x02000000,0x4240); +reg_write( DDR_REG_BASE +0x50b71*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50b72*4+0x02000000,0x9fa); +reg_write( DDR_REG_BASE +0x50b73*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50b74*4+0x02000000,0x1ef6); +reg_write( DDR_REG_BASE +0x50b75*4+0x02000000,0x9245); +reg_write( DDR_REG_BASE +0x50b76*4+0x02000000,0x17be); +reg_write( DDR_REG_BASE +0x50b77*4+0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x50b78*4+0x02000000,0x1ef0); +reg_write( DDR_REG_BASE +0x50b79*4+0x02000000,0x9045); +reg_write( DDR_REG_BASE +0x50b7a*4+0x02000000,0x1ef6); +reg_write( DDR_REG_BASE +0x50b7b*4+0x02000000,0x9205); +reg_write( DDR_REG_BASE +0x50b7c*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x50b7d*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x50b7e*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x50b7f*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x50b80*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50b81*4+0x02000000,0x3e00); +reg_write( DDR_REG_BASE +0x50b82*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50b83*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50b84*4+0x02000000,0xb88e); +reg_write( DDR_REG_BASE +0x50b85*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x50b86*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x50b87*4+0x02000000,0x1ef6); +reg_write( DDR_REG_BASE +0x50b88*4+0x02000000,0x9205); +reg_write( DDR_REG_BASE +0x50b89*4+0x02000000,0x1ef0); +reg_write( DDR_REG_BASE +0x50b8a*4+0x02000000,0x9045); +reg_write( DDR_REG_BASE +0x50b8b*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50b8c*4+0x02000000,0x76c4); +reg_write( DDR_REG_BASE +0x50b8d*4+0x02000000,0x9013); +reg_write( DDR_REG_BASE +0x50b8e*4+0x02000000,0xe050); +reg_write( DDR_REG_BASE +0x50b8f*4+0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x50b90*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50b91*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50b92*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50b93*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50b94*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50b95*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50b96*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50b97*4+0x02000000,0xc1a2); +reg_write( DDR_REG_BASE +0x50b98*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x50b99*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50b9a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50b9b*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x50b9c*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x50b9d*4+0x02000000,0x9b); +reg_write( DDR_REG_BASE +0x50b9e*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x50b9f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50ba0*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x50ba1*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50ba2*4+0x02000000,0xea6); +reg_write( DDR_REG_BASE +0x50ba3*4+0x02000000,0x220); +reg_write( DDR_REG_BASE +0x50ba4*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50ba5*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50ba6*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50ba7*4+0x02000000,0xe3a); +reg_write( DDR_REG_BASE +0x50ba8*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50ba9*4+0x02000000,0xda7f); +reg_write( DDR_REG_BASE +0x50baa*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50bab*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50bac*4+0x02000000,0xe2e); +reg_write( DDR_REG_BASE +0x50bad*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50bae*4+0x02000000,0xdafe); +reg_write( DDR_REG_BASE +0x50baf*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50bb0*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50bb1*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x50bb2*4+0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x50bb3*4+0x02000000,0x2653); +reg_write( DDR_REG_BASE +0x50bb4*4+0x02000000,0x104f); +reg_write( DDR_REG_BASE +0x50bb5*4+0x02000000,0xe81c); +reg_write( DDR_REG_BASE +0x50bb6*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50bb7*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50bb8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50bb9*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50bba*4+0x02000000,0x82d); +reg_write( DDR_REG_BASE +0x50bbb*4+0x02000000,0xff); +reg_write( DDR_REG_BASE +0x50bbc*4+0x02000000,0x2778); +reg_write( DDR_REG_BASE +0x50bbd*4+0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x50bbe*4+0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x50bbf*4+0x02000000,0x3c82); +reg_write( DDR_REG_BASE +0x50bc0*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x50bc1*4+0x02000000,0x641); +reg_write( DDR_REG_BASE +0x50bc2*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x50bc3*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x50bc4*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x50bc5*4+0x02000000,0xdfff); +reg_write( DDR_REG_BASE +0x50bc6*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x50bc7*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x50bc8*4+0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x50bc9*4+0x02000000,0x61b9); +reg_write( DDR_REG_BASE +0x50bca*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50bcb*4+0x02000000,0x9f2); +reg_write( DDR_REG_BASE +0x50bcc*4+0x02000000,0x2e0); +reg_write( DDR_REG_BASE +0x50bcd*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x50bce*4+0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x50bcf*4+0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x50bd0*4+0x02000000,0xe12); +reg_write( DDR_REG_BASE +0x50bd1*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x50bd2*4+0x02000000,0x2778); +reg_write( DDR_REG_BASE +0x50bd3*4+0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x50bd4*4+0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x50bd5*4+0x02000000,0x3c82); +reg_write( DDR_REG_BASE +0x50bd6*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x50bd7*4+0x02000000,0x641); +reg_write( DDR_REG_BASE +0x50bd8*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x50bd9*4+0x02000000,0x1100); +reg_write( DDR_REG_BASE +0x50bda*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x50bdb*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x50bdc*4+0x02000000,0xdfff); +reg_write( DDR_REG_BASE +0x50bdd*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x50bde*4+0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x50bdf*4+0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x50be0*4+0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x50be1*4+0x02000000,0x61b9); +reg_write( DDR_REG_BASE +0x50be2*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x50be3*4+0x02000000,0x87a); +reg_write( DDR_REG_BASE +0x50be4*4+0x02000000,0x2e0); +reg_write( DDR_REG_BASE +0x50be5*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50be6*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50be7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50be8*4+0x02000000,0x36b0); +reg_write( DDR_REG_BASE +0x50be9*4+0x02000000,0x90e); +reg_write( DDR_REG_BASE +0x50bea*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50beb*4+0x02000000,0xd90a); +reg_write( DDR_REG_BASE +0x50bec*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50bed*4+0x02000000,0xa12); +reg_write( DDR_REG_BASE +0x50bee*4+0x02000000,0x220); +reg_write( DDR_REG_BASE +0x50bef*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50bf0*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50bf1*4+0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x50bf2*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x50bf3*4+0x02000000,0xe048); +reg_write( DDR_REG_BASE +0x50bf4*4+0x02000000,0xc0a2); +reg_write( DDR_REG_BASE +0x50bf5*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50bf6*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50bf7*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50bf8*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50bf9*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50bfa*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50bfb*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50bfc*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50bfd*4+0x02000000,0xf4); +reg_write( DDR_REG_BASE +0x50bfe*4+0x02000000,0x6ea2); +reg_write( DDR_REG_BASE +0x50bff*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50c00*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50c01*4+0x02000000,0x111b); +reg_write( DDR_REG_BASE +0x50c02*4+0x02000000,0x1500); +reg_write( DDR_REG_BASE +0x50c03*4+0x02000000,0x111e); +reg_write( DDR_REG_BASE +0x50c04*4+0x02000000,0x1506); +reg_write( DDR_REG_BASE +0x50c05*4+0x02000000,0x110b); +reg_write( DDR_REG_BASE +0x50c06*4+0x02000000,0x95e4); +reg_write( DDR_REG_BASE +0x50c07*4+0x02000000,0x1d08); +reg_write( DDR_REG_BASE +0x50c08*4+0x02000000,0x13c5); +reg_write( DDR_REG_BASE +0x50c09*4+0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x50c0a*4+0x02000000,0x1d06); +reg_write( DDR_REG_BASE +0x50c0b*4+0x02000000,0x13c5); +reg_write( DDR_REG_BASE +0x50c0c*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x50c0d*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50c0e*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50c0f*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x50c10*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x50c11*4+0x02000000,0x190); +reg_write( DDR_REG_BASE +0x50c12*4+0x02000000,0xd834); +reg_write( DDR_REG_BASE +0x50c13*4+0x02000000,0x1efa); +reg_write( DDR_REG_BASE +0x50c14*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50c15*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50c16*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50c17*4+0x02000000,0x2af8); +reg_write( DDR_REG_BASE +0x50c18*4+0x02000000,0x8ae); +reg_write( DDR_REG_BASE +0x50c19*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50c1a*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50c1b*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50c1c*4+0x02000000,0x16c4); +reg_write( DDR_REG_BASE +0x50c1d*4+0x02000000,0x1d06); +reg_write( DDR_REG_BASE +0x50c1e*4+0x02000000,0x12c4); +reg_write( DDR_REG_BASE +0x50c1f*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50c20*4+0x02000000,0x1784); +reg_write( DDR_REG_BASE +0x50c21*4+0x02000000,0xb5e4); +reg_write( DDR_REG_BASE +0x50c22*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50c23*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50c24*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50c25*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50c26*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50c27*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50c28*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50c29*4+0x02000000,0x236f); +reg_write( DDR_REG_BASE +0x50c2a*4+0x02000000,0x343); +reg_write( DDR_REG_BASE +0x50c2b*4+0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x50c2c*4+0x02000000,0x3040); +reg_write( DDR_REG_BASE +0x50c2d*4+0x02000000,0x9320); +reg_write( DDR_REG_BASE +0x50c2e*4+0x02000000,0x4348); +reg_write( DDR_REG_BASE +0x50c2f*4+0x02000000,0x218c); +reg_write( DDR_REG_BASE +0x50c30*4+0x02000000,0x864a); +reg_write( DDR_REG_BASE +0x50c31*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x50c32*4+0x02000000,0x2d); +reg_write( DDR_REG_BASE +0x50c33*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x50c34*4+0x02000000,0xe02); +reg_write( DDR_REG_BASE +0x50c35*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x50c36*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x50c37*4+0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x50c38*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x50c39*4+0x02000000,0x2042); +reg_write( DDR_REG_BASE +0x50c3a*4+0x02000000,0x11b); +reg_write( DDR_REG_BASE +0x50c3b*4+0x02000000,0x13fe); +reg_write( DDR_REG_BASE +0x50c3c*4+0x02000000,0x8080); +reg_write( DDR_REG_BASE +0x50c3d*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50c3e*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50c3f*4+0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x50c40*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x50c41*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50c42*4+0x02000000,0xf02a); +reg_write( DDR_REG_BASE +0x50c43*4+0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x50c44*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x50c45*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50c46*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x50c47*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50c48*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x50c49*4+0x02000000,0x381); +reg_write( DDR_REG_BASE +0x50c4a*4+0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x50c4b*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x50c4c*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50c4d*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50c4e*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x50c4f*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x50c50*4+0x02000000,0xf8f); +reg_write( DDR_REG_BASE +0x50c51*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50c52*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50c53*4+0x02000000,0xe4a); +reg_write( DDR_REG_BASE +0x50c54*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50c55*4+0x02000000,0x9700); +reg_write( DDR_REG_BASE +0x50c56*4+0x02000000,0x7063); +reg_write( DDR_REG_BASE +0x50c57*4+0x02000000,0x7a0e); +reg_write( DDR_REG_BASE +0x50c58*4+0x02000000,0x785c); +reg_write( DDR_REG_BASE +0x50c59*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x50c5a*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x50c5b*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x50c5c*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x50c5d*4+0x02000000,0xd81b); +reg_write( DDR_REG_BASE +0x50c5e*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x50c5f*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x50c60*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x50c61*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50c62*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x50c63*4+0x02000000,0x6238); +reg_write( DDR_REG_BASE +0x50c64*4+0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x50c65*4+0x02000000,0x4831); +reg_write( DDR_REG_BASE +0x50c66*4+0x02000000,0x2a44); +reg_write( DDR_REG_BASE +0x50c67*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x50c68*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x50c69*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50c6a*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50c6b*4+0x02000000,0xb700); +reg_write( DDR_REG_BASE +0x50c6c*4+0x02000000,0xbaf); +reg_write( DDR_REG_BASE +0x50c6d*4+0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x50c6e*4+0x02000000,0x2555); +reg_write( DDR_REG_BASE +0x50c6f*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x50c70*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50c71*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50c72*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50c73*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50c74*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x50c75*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x50c76*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50c77*4+0x02000000,0x6); +reg_write( DDR_REG_BASE +0x50c78*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x50c79*4+0x02000000,0xf96); +reg_write( DDR_REG_BASE +0x50c7a*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50c7b*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50c7c*4+0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x50c7d*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50c7e*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x50c7f*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x50c80*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50c81*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x50c82*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50c83*4+0x02000000,0x1c6); +reg_write( DDR_REG_BASE +0x50c84*4+0x02000000,0x95c0); +reg_write( DDR_REG_BASE +0x50c85*4+0x02000000,0xbecb); +reg_write( DDR_REG_BASE +0x50c86*4+0x02000000,0x264f); +reg_write( DDR_REG_BASE +0x50c87*4+0x02000000,0x12cf); +reg_write( DDR_REG_BASE +0x50c88*4+0x02000000,0x2605); +reg_write( DDR_REG_BASE +0x50c89*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x50c8a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50c8b*4+0x02000000,0xc00); +reg_write( DDR_REG_BASE +0x50c8c*4+0x02000000,0xb5e0); +reg_write( DDR_REG_BASE +0x50c8d*4+0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x50c8e*4+0x02000000,0xf6a); +reg_write( DDR_REG_BASE +0x50c8f*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50c90*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x50c91*4+0x02000000,0xb5e0); +reg_write( DDR_REG_BASE +0x50c92*4+0x02000000,0x9501); +reg_write( DDR_REG_BASE +0x50c93*4+0x02000000,0xb5c0); +reg_write( DDR_REG_BASE +0x50c94*4+0x02000000,0xb8c9); +reg_write( DDR_REG_BASE +0x50c95*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50c96*4+0x02000000,0xc1e2); +reg_write( DDR_REG_BASE +0x50c97*4+0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x50c98*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x50c99*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x50c9a*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50c9b*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x50c9c*4+0x02000000,0x86); +reg_write( DDR_REG_BASE +0x50c9d*4+0x02000000,0x9020); +reg_write( DDR_REG_BASE +0x50c9e*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50c9f*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50ca0*4+0x02000000,0x2153); +reg_write( DDR_REG_BASE +0x50ca1*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x50ca2*4+0x02000000,0x1c02); +reg_write( DDR_REG_BASE +0x50ca3*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x50ca4*4+0x02000000,0x783d); +reg_write( DDR_REG_BASE +0x50ca5*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50ca6*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50ca7*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50ca8*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50ca9*4+0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x50caa*4+0x02000000,0x1c03); +reg_write( DDR_REG_BASE +0x50cab*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x50cac*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x50cad*4+0x02000000,0x606c); +reg_write( DDR_REG_BASE +0x50cae*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x50caf*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50cb0*4+0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x50cb1*4+0x02000000,0x61b9); +reg_write( DDR_REG_BASE +0x50cb2*4+0x02000000,0x7c9d); +reg_write( DDR_REG_BASE +0x50cb3*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x50cb4*4+0x02000000,0x8fb); +reg_write( DDR_REG_BASE +0x50cb5*4+0x02000000,0x8174); +reg_write( DDR_REG_BASE +0x50cb6*4+0x02000000,0x2444); +reg_write( DDR_REG_BASE +0x50cb7*4+0x02000000,0x104d); +reg_write( DDR_REG_BASE +0x50cb8*4+0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x50cb9*4+0x02000000,0xd978); +reg_write( DDR_REG_BASE +0x50cba*4+0x02000000,0x2905); +reg_write( DDR_REG_BASE +0x50cbb*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50cbc*4+0x02000000,0x784f); +reg_write( DDR_REG_BASE +0x50cbd*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x50cbe*4+0x02000000,0x611a); +reg_write( DDR_REG_BASE +0x50cbf*4+0x02000000,0xbdf); +reg_write( DDR_REG_BASE +0x50cc0*4+0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x50cc1*4+0x02000000,0x2440); +reg_write( DDR_REG_BASE +0x50cc2*4+0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x50cc3*4+0x02000000,0x2284); +reg_write( DDR_REG_BASE +0x50cc4*4+0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x50cc5*4+0x02000000,0x785d); +reg_write( DDR_REG_BASE +0x50cc6*4+0x02000000,0xc5c2); +reg_write( DDR_REG_BASE +0x50cc7*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50cc8*4+0x02000000,0x701); +reg_write( DDR_REG_BASE +0x50cc9*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50cca*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x50ccb*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50ccc*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50ccd*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50cce*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50ccf*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x50cd0*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50cd1*4+0x02000000,0x711e); +reg_write( DDR_REG_BASE +0x50cd2*4+0x02000000,0x9018); +reg_write( DDR_REG_BASE +0x50cd3*4+0x02000000,0x1dc); +reg_write( DDR_REG_BASE +0x50cd4*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50cd5*4+0x02000000,0x308c); +reg_write( DDR_REG_BASE +0x50cd6*4+0x02000000,0xc609); +reg_write( DDR_REG_BASE +0x50cd7*4+0x02000000,0x4378); +reg_write( DDR_REG_BASE +0x50cd8*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50cd9*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x50cda*4+0x02000000,0x43cb); +reg_write( DDR_REG_BASE +0x50cdb*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50cdc*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x50cdd*4+0x02000000,0x2705); +reg_write( DDR_REG_BASE +0x50cde*4+0x02000000,0x32cd); +reg_write( DDR_REG_BASE +0x50cdf*4+0x02000000,0x95a0); +reg_write( DDR_REG_BASE +0x50ce0*4+0x02000000,0xc780); +reg_write( DDR_REG_BASE +0x50ce1*4+0x02000000,0x677f); +reg_write( DDR_REG_BASE +0x50ce2*4+0x02000000,0x2340); +reg_write( DDR_REG_BASE +0x50ce3*4+0x02000000,0x180b); +reg_write( DDR_REG_BASE +0x50ce4*4+0x02000000,0xafa0); +reg_write( DDR_REG_BASE +0x50ce5*4+0x02000000,0x2705); +reg_write( DDR_REG_BASE +0x50ce6*4+0x02000000,0x32cd); +reg_write( DDR_REG_BASE +0x50ce7*4+0x02000000,0x95a0); +reg_write( DDR_REG_BASE +0x50ce8*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x50ce9*4+0x02000000,0xe508); +reg_write( DDR_REG_BASE +0x50cea*4+0x02000000,0xafa8); +reg_write( DDR_REG_BASE +0x50ceb*4+0x02000000,0xbe1); +reg_write( DDR_REG_BASE +0x50cec*4+0x02000000,0x81b4); +reg_write( DDR_REG_BASE +0x50ced*4+0x02000000,0x272f); +reg_write( DDR_REG_BASE +0x50cee*4+0x02000000,0x30c0); +reg_write( DDR_REG_BASE +0x50cef*4+0x02000000,0xe48c); +reg_write( DDR_REG_BASE +0x50cf0*4+0x02000000,0x304); +reg_write( DDR_REG_BASE +0x50cf1*4+0x02000000,0x2d); +reg_write( DDR_REG_BASE +0x50cf2*4+0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x50cf3*4+0x02000000,0x205); +reg_write( DDR_REG_BASE +0x50cf4*4+0x02000000,0xb9d); +reg_write( DDR_REG_BASE +0x50cf5*4+0x02000000,0x32e); +reg_write( DDR_REG_BASE +0x50cf6*4+0x02000000,0x746d); +reg_write( DDR_REG_BASE +0x50cf7*4+0x02000000,0xc0f); +reg_write( DDR_REG_BASE +0x50cf8*4+0x02000000,0x1230); +reg_write( DDR_REG_BASE +0x50cf9*4+0x02000000,0x1b00); +reg_write( DDR_REG_BASE +0x50cfa*4+0x02000000,0x32c2); +reg_write( DDR_REG_BASE +0x50cfb*4+0x02000000,0x7695); +reg_write( DDR_REG_BASE +0x50cfc*4+0x02000000,0xf4af); +reg_write( DDR_REG_BASE +0x50cfd*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x50cfe*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50cff*4+0x02000000,0xaea3); +reg_write( DDR_REG_BASE +0x50d00*4+0x02000000,0xaea2); +reg_write( DDR_REG_BASE +0x50d01*4+0x02000000,0xae61); +reg_write( DDR_REG_BASE +0x50d02*4+0x02000000,0xae60); +reg_write( DDR_REG_BASE +0x50d03*4+0x02000000,0x75ed); +reg_write( DDR_REG_BASE +0x50d04*4+0x02000000,0x73cd); +reg_write( DDR_REG_BASE +0x50d05*4+0x02000000,0x728d); +reg_write( DDR_REG_BASE +0x50d06*4+0x02000000,0xa9e3); +reg_write( DDR_REG_BASE +0x50d07*4+0x02000000,0xa9c2); +reg_write( DDR_REG_BASE +0x50d08*4+0x02000000,0xa981); +reg_write( DDR_REG_BASE +0x50d09*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50d0a*4+0x02000000,0xaac5); +reg_write( DDR_REG_BASE +0x50d0b*4+0x02000000,0xaa83); +reg_write( DDR_REG_BASE +0x50d0c*4+0x02000000,0xaaa2); +reg_write( DDR_REG_BASE +0x50d0d*4+0x02000000,0xaa60); +reg_write( DDR_REG_BASE +0x50d0e*4+0x02000000,0xc120); +reg_write( DDR_REG_BASE +0x50d0f*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d10*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50d11*4+0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x50d12*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d13*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d14*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50d15*4+0x02000000,0x1402); +reg_write( DDR_REG_BASE +0x50d16*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d17*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d18*4+0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50d19*4+0x02000000,0x1403); +reg_write( DDR_REG_BASE +0x50d1a*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d1b*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d1c*4+0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50d1d*4+0x02000000,0xc121); +reg_write( DDR_REG_BASE +0x50d1e*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d1f*4+0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50d20*4+0x02000000,0x1405); +reg_write( DDR_REG_BASE +0x50d21*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d22*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d23*4+0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50d24*4+0x02000000,0xa8a7); +reg_write( DDR_REG_BASE +0x50d25*4+0x02000000,0xa8a6); +reg_write( DDR_REG_BASE +0x50d26*4+0x02000000,0xc122); +reg_write( DDR_REG_BASE +0x50d27*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d28*4+0x02000000,0xa9c0); +reg_write( DDR_REG_BASE +0x50d29*4+0x02000000,0x1409); +reg_write( DDR_REG_BASE +0x50d2a*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d2b*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d2c*4+0x02000000,0xa9c0); +reg_write( DDR_REG_BASE +0x50d2d*4+0x02000000,0x140a); +reg_write( DDR_REG_BASE +0x50d2e*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d2f*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d30*4+0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50d31*4+0x02000000,0x140b); +reg_write( DDR_REG_BASE +0x50d32*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d33*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d34*4+0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50d35*4+0x02000000,0xc123); +reg_write( DDR_REG_BASE +0x50d36*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d37*4+0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50d38*4+0x02000000,0x140d); +reg_write( DDR_REG_BASE +0x50d39*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d3a*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d3b*4+0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50d3c*4+0x02000000,0x180f); +reg_write( DDR_REG_BASE +0x50d3d*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50d3e*4+0x02000000,0x269); +reg_write( DDR_REG_BASE +0x50d3f*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50d40*4+0x02000000,0x180e); +reg_write( DDR_REG_BASE +0x50d41*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50d42*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x50d43*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50d44*4+0x02000000,0x1400); +reg_write( DDR_REG_BASE +0x50d45*4+0x02000000,0x2311); +reg_write( DDR_REG_BASE +0x50d46*4+0x02000000,0x8300); +reg_write( DDR_REG_BASE +0x50d47*4+0x02000000,0x258); +reg_write( DDR_REG_BASE +0x50d48*4+0x02000000,0x21); +reg_write( DDR_REG_BASE +0x50d49*4+0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x50d4a*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50d4b*4+0x02000000,0xaee5); +reg_write( DDR_REG_BASE +0x50d4c*4+0x02000000,0xaee4); +reg_write( DDR_REG_BASE +0x50d4d*4+0x02000000,0xaee3); +reg_write( DDR_REG_BASE +0x50d4e*4+0x02000000,0xae62); +reg_write( DDR_REG_BASE +0x50d4f*4+0x02000000,0xae61); +reg_write( DDR_REG_BASE +0x50d50*4+0x02000000,0xae60); +reg_write( DDR_REG_BASE +0x50d51*4+0x02000000,0x260c); +reg_write( DDR_REG_BASE +0x50d52*4+0x02000000,0xbf80); +reg_write( DDR_REG_BASE +0x50d53*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50d54*4+0x02000000,0x2208); +reg_write( DDR_REG_BASE +0x50d55*4+0x02000000,0x73ad); +reg_write( DDR_REG_BASE +0x50d56*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x50d57*4+0x02000000,0xf47c); +reg_write( DDR_REG_BASE +0x50d58*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x50d59*4+0x02000000,0x1b00); +reg_write( DDR_REG_BASE +0x50d5a*4+0x02000000,0x3143); +reg_write( DDR_REG_BASE +0x50d5b*4+0x02000000,0xaee4); +reg_write( DDR_REG_BASE +0x50d5c*4+0x02000000,0xaee3); +reg_write( DDR_REG_BASE +0x50d5d*4+0x02000000,0xaee2); +reg_write( DDR_REG_BASE +0x50d5e*4+0x02000000,0xae81); +reg_write( DDR_REG_BASE +0x50d5f*4+0x02000000,0xae80); +reg_write( DDR_REG_BASE +0x50d60*4+0x02000000,0xde0b); +reg_write( DDR_REG_BASE +0x50d61*4+0x02000000,0x234a); +reg_write( DDR_REG_BASE +0x50d62*4+0x02000000,0x1280); +reg_write( DDR_REG_BASE +0x50d63*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x50d64*4+0x02000000,0x3180); +reg_write( DDR_REG_BASE +0x50d65*4+0x02000000,0xa9c4); +reg_write( DDR_REG_BASE +0x50d66*4+0x02000000,0x1903); +reg_write( DDR_REG_BASE +0x50d67*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50d68*4+0x02000000,0x1902); +reg_write( DDR_REG_BASE +0x50d69*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50d6a*4+0x02000000,0xa9a1); +reg_write( DDR_REG_BASE +0x50d6b*4+0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50d6c*4+0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x50d6d*4+0x02000000,0xaa2b); +reg_write( DDR_REG_BASE +0x50d6e*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50d6f*4+0x02000000,0xaaaa); +reg_write( DDR_REG_BASE +0x50d70*4+0x02000000,0xaa66); +reg_write( DDR_REG_BASE +0x50d71*4+0x02000000,0xaae3); +reg_write( DDR_REG_BASE +0x50d72*4+0x02000000,0xaa20); +reg_write( DDR_REG_BASE +0x50d73*4+0x02000000,0xc120); +reg_write( DDR_REG_BASE +0x50d74*4+0x02000000,0x603a); +reg_write( DDR_REG_BASE +0x50d75*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50d76*4+0x02000000,0xaa20); +reg_write( DDR_REG_BASE +0x50d77*4+0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x50d78*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d79*4+0x02000000,0x603a); +reg_write( DDR_REG_BASE +0x50d7a*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50d7b*4+0x02000000,0xaa20); +reg_write( DDR_REG_BASE +0x50d7c*4+0x02000000,0x1402); +reg_write( DDR_REG_BASE +0x50d7d*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d7e*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d7f*4+0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50d80*4+0x02000000,0x1403); +reg_write( DDR_REG_BASE +0x50d81*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d82*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d83*4+0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50d84*4+0x02000000,0xc121); +reg_write( DDR_REG_BASE +0x50d85*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d86*4+0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50d87*4+0x02000000,0x1405); +reg_write( DDR_REG_BASE +0x50d88*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d89*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d8a*4+0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50d8b*4+0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x50d8c*4+0x02000000,0xa8e7); +reg_write( DDR_REG_BASE +0x50d8d*4+0x02000000,0xa826); +reg_write( DDR_REG_BASE +0x50d8e*4+0x02000000,0xc122); +reg_write( DDR_REG_BASE +0x50d8f*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d90*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50d91*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50d92*4+0x02000000,0x1409); +reg_write( DDR_REG_BASE +0x50d93*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d94*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d95*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50d96*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50d97*4+0x02000000,0x140a); +reg_write( DDR_REG_BASE +0x50d98*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d99*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d9a*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50d9b*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50d9c*4+0x02000000,0x140b); +reg_write( DDR_REG_BASE +0x50d9d*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d9e*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d9f*4+0x02000000,0xa9c0); +reg_write( DDR_REG_BASE +0x50da0*4+0x02000000,0xc123); +reg_write( DDR_REG_BASE +0x50da1*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50da2*4+0x02000000,0xa9c0); +reg_write( DDR_REG_BASE +0x50da3*4+0x02000000,0x140d); +reg_write( DDR_REG_BASE +0x50da4*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50da5*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50da6*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50da7*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50da8*4+0x02000000,0x180f); +reg_write( DDR_REG_BASE +0x50da9*4+0x02000000,0x1c3); +reg_write( DDR_REG_BASE +0x50daa*4+0x02000000,0xf079); +reg_write( DDR_REG_BASE +0x50dab*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x50dac*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x50dad*4+0x02000000,0x1b00); +reg_write( DDR_REG_BASE +0x50dae*4+0x02000000,0x30c2); +reg_write( DDR_REG_BASE +0x50daf*4+0x02000000,0xae81); +reg_write( DDR_REG_BASE +0x50db0*4+0x02000000,0xae80); +reg_write( DDR_REG_BASE +0x50db1*4+0x02000000,0xa961); +reg_write( DDR_REG_BASE +0x50db2*4+0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50db3*4+0x02000000,0x718d); +reg_write( DDR_REG_BASE +0x50db4*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50db5*4+0x02000000,0xaa82); +reg_write( DDR_REG_BASE +0x50db6*4+0x02000000,0xaa20); +reg_write( DDR_REG_BASE +0x50db7*4+0x02000000,0xc120); +reg_write( DDR_REG_BASE +0x50db8*4+0x02000000,0x603a); +reg_write( DDR_REG_BASE +0x50db9*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50dba*4+0x02000000,0xaa20); +reg_write( DDR_REG_BASE +0x50dbb*4+0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x50dbc*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50dbd*4+0x02000000,0x603a); +reg_write( DDR_REG_BASE +0x50dbe*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50dbf*4+0x02000000,0xaa20); +reg_write( DDR_REG_BASE +0x50dc0*4+0x02000000,0x1402); +reg_write( DDR_REG_BASE +0x50dc1*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50dc2*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50dc3*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50dc4*4+0x02000000,0x1403); +reg_write( DDR_REG_BASE +0x50dc5*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50dc6*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50dc7*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50dc8*4+0x02000000,0xc121); +reg_write( DDR_REG_BASE +0x50dc9*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50dca*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50dcb*4+0x02000000,0x1405); +reg_write( DDR_REG_BASE +0x50dcc*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50dcd*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50dce*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50dcf*4+0x02000000,0xa887); +reg_write( DDR_REG_BASE +0x50dd0*4+0x02000000,0xa886); +reg_write( DDR_REG_BASE +0x50dd1*4+0x02000000,0xf0a2); +reg_write( DDR_REG_BASE +0x50dd2*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x50dd3*4+0x02000000,0x3200); +reg_write( DDR_REG_BASE +0x50dd4*4+0x02000000,0xca5); +reg_write( DDR_REG_BASE +0x50dd5*4+0x02000000,0x1331); +reg_write( DDR_REG_BASE +0x50dd6*4+0x02000000,0x234a); +reg_write( DDR_REG_BASE +0x50dd7*4+0x02000000,0x11c0); +reg_write( DDR_REG_BASE +0x50dd8*4+0x02000000,0x768d); +reg_write( DDR_REG_BASE +0x50dd9*4+0x02000000,0x1b00); +reg_write( DDR_REG_BASE +0x50dda*4+0x02000000,0x3302); +reg_write( DDR_REG_BASE +0x50ddb*4+0x02000000,0x1905); +reg_write( DDR_REG_BASE +0x50ddc*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50ddd*4+0x02000000,0x1904); +reg_write( DDR_REG_BASE +0x50dde*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50ddf*4+0x02000000,0xa983); +reg_write( DDR_REG_BASE +0x50de0*4+0x02000000,0xa9a2); +reg_write( DDR_REG_BASE +0x50de1*4+0x02000000,0xa961); +reg_write( DDR_REG_BASE +0x50de2*4+0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50de3*4+0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x50de4*4+0x02000000,0x1a08); +reg_write( DDR_REG_BASE +0x50de5*4+0x02000000,0x143); +reg_write( DDR_REG_BASE +0x50de6*4+0x02000000,0xaa27); +reg_write( DDR_REG_BASE +0x50de7*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50de8*4+0x02000000,0xaaa6); +reg_write( DDR_REG_BASE +0x50de9*4+0x02000000,0xaa63); +reg_write( DDR_REG_BASE +0x50dea*4+0x02000000,0xaae2); +reg_write( DDR_REG_BASE +0x50deb*4+0x02000000,0xaa21); +reg_write( DDR_REG_BASE +0x50dec*4+0x02000000,0xc120); +reg_write( DDR_REG_BASE +0x50ded*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50dee*4+0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50def*4+0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x50df0*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50df1*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50df2*4+0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50df3*4+0x02000000,0x1402); +reg_write( DDR_REG_BASE +0x50df4*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50df5*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50df6*4+0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50df7*4+0x02000000,0x1403); +reg_write( DDR_REG_BASE +0x50df8*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50df9*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50dfa*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50dfb*4+0x02000000,0xc121); +reg_write( DDR_REG_BASE +0x50dfc*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50dfd*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50dfe*4+0x02000000,0x1405); +reg_write( DDR_REG_BASE +0x50dff*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e00*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e01*4+0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50e02*4+0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x50e03*4+0x02000000,0x1807); +reg_write( DDR_REG_BASE +0x50e04*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x50e05*4+0x02000000,0xa826); +reg_write( DDR_REG_BASE +0x50e06*4+0x02000000,0xc122); +reg_write( DDR_REG_BASE +0x50e07*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e08*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e09*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50e0a*4+0x02000000,0x1409); +reg_write( DDR_REG_BASE +0x50e0b*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e0c*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e0d*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e0e*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50e0f*4+0x02000000,0x140a); +reg_write( DDR_REG_BASE +0x50e10*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e11*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e12*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e13*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50e14*4+0x02000000,0x140b); +reg_write( DDR_REG_BASE +0x50e15*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e16*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e17*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e18*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50e19*4+0x02000000,0xc123); +reg_write( DDR_REG_BASE +0x50e1a*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e1b*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e1c*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50e1d*4+0x02000000,0x140d); +reg_write( DDR_REG_BASE +0x50e1e*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e1f*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e20*4+0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50e21*4+0x02000000,0x180f); +reg_write( DDR_REG_BASE +0x50e22*4+0x02000000,0x283); +reg_write( DDR_REG_BASE +0x50e23*4+0x02000000,0x180e); +reg_write( DDR_REG_BASE +0x50e24*4+0x02000000,0x143); +reg_write( DDR_REG_BASE +0x50e25*4+0x02000000,0xf04e); +reg_write( DDR_REG_BASE +0x50e26*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x50e27*4+0x02000000,0xaee3); +reg_write( DDR_REG_BASE +0x50e28*4+0x02000000,0xaee2); +reg_write( DDR_REG_BASE +0x50e29*4+0x02000000,0xae81); +reg_write( DDR_REG_BASE +0x50e2a*4+0x02000000,0xae80); +reg_write( DDR_REG_BASE +0x50e2b*4+0x02000000,0x748d); +reg_write( DDR_REG_BASE +0x50e2c*4+0x02000000,0x1b00); +reg_write( DDR_REG_BASE +0x50e2d*4+0x02000000,0x3302); +reg_write( DDR_REG_BASE +0x50e2e*4+0x02000000,0x1903); +reg_write( DDR_REG_BASE +0x50e2f*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50e30*4+0x02000000,0x1902); +reg_write( DDR_REG_BASE +0x50e31*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50e32*4+0x02000000,0xa9a1); +reg_write( DDR_REG_BASE +0x50e33*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50e34*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50e35*4+0x02000000,0xaaa8); +reg_write( DDR_REG_BASE +0x50e36*4+0x02000000,0xaa67); +reg_write( DDR_REG_BASE +0x50e37*4+0x02000000,0xaae3); +reg_write( DDR_REG_BASE +0x50e38*4+0x02000000,0xaa22); +reg_write( DDR_REG_BASE +0x50e39*4+0x02000000,0xc120); +reg_write( DDR_REG_BASE +0x50e3a*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e3b*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50e3c*4+0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x50e3d*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e3e*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e3f*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50e40*4+0x02000000,0x1402); +reg_write( DDR_REG_BASE +0x50e41*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e42*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e43*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50e44*4+0x02000000,0x1403); +reg_write( DDR_REG_BASE +0x50e45*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e46*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e47*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50e48*4+0x02000000,0xc121); +reg_write( DDR_REG_BASE +0x50e49*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e4a*4+0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50e4b*4+0x02000000,0x1405); +reg_write( DDR_REG_BASE +0x50e4c*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e4d*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e4e*4+0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50e4f*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50e50*4+0x02000000,0xa827); +reg_write( DDR_REG_BASE +0x50e51*4+0x02000000,0xa8e6); +reg_write( DDR_REG_BASE +0x50e52*4+0x02000000,0xc122); +reg_write( DDR_REG_BASE +0x50e53*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e54*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e55*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50e56*4+0x02000000,0x1409); +reg_write( DDR_REG_BASE +0x50e57*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e58*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e59*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e5a*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50e5b*4+0x02000000,0x140a); +reg_write( DDR_REG_BASE +0x50e5c*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e5d*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e5e*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e5f*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50e60*4+0x02000000,0x140b); +reg_write( DDR_REG_BASE +0x50e61*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e62*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e63*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e64*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50e65*4+0x02000000,0xc123); +reg_write( DDR_REG_BASE +0x50e66*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e67*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e68*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50e69*4+0x02000000,0x140d); +reg_write( DDR_REG_BASE +0x50e6a*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e6b*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e6c*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e6d*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50e6e*4+0x02000000,0x180f); +reg_write( DDR_REG_BASE +0x50e6f*4+0x02000000,0x143); +reg_write( DDR_REG_BASE +0x50e70*4+0x02000000,0x180e); +reg_write( DDR_REG_BASE +0x50e71*4+0x02000000,0x183); +reg_write( DDR_REG_BASE +0x50e72*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x50e73*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50e74*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50e75*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50e76*4+0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x50e77*4+0x02000000,0x641); +reg_write( DDR_REG_BASE +0x50e78*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x50e79*4+0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x50e7a*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e7b*4+0x02000000,0x2132); +reg_write( DDR_REG_BASE +0x50e7c*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50e7d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50e7e*4+0x02000000,0x688); +reg_write( DDR_REG_BASE +0x50e7f*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50e80*4+0x02000000,0xb8c6); +reg_write( DDR_REG_BASE +0x50e81*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50e82*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x50e83*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50e84*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50e85*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50e86*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50e87*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50e88*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50e89*4+0x02000000,0x168); +reg_write( DDR_REG_BASE +0x50e8a*4+0x02000000,0x21c2); +reg_write( DDR_REG_BASE +0x50e8b*4+0x02000000,0x222); +reg_write( DDR_REG_BASE +0x50e8c*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50e8d*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50e8e*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50e8f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50e90*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x50e91*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50e92*4+0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x50e93*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50e94*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50e95*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50e96*4+0x02000000,0x710d); +reg_write( DDR_REG_BASE +0x50e97*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50e98*4+0x02000000,0x1c6); +reg_write( DDR_REG_BASE +0x50e99*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x50e9a*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x50e9b*4+0x02000000,0xe1c6); +reg_write( DDR_REG_BASE +0x50e9c*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x50e9d*4+0x02000000,0xbdc9); +reg_write( DDR_REG_BASE +0x50e9e*4+0x02000000,0x254f); +reg_write( DDR_REG_BASE +0x50e9f*4+0x02000000,0x12ce); +reg_write( DDR_REG_BASE +0x50ea0*4+0x02000000,0xb46); +reg_write( DDR_REG_BASE +0x50ea1*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50ea2*4+0x02000000,0xb7c0); +reg_write( DDR_REG_BASE +0x50ea3*4+0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x50ea4*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x50ea5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50ea6*4+0x02000000,0xc00); +reg_write( DDR_REG_BASE +0x50ea7*4+0x02000000,0xb700); +reg_write( DDR_REG_BASE +0x50ea8*4+0x02000000,0xb36); +reg_write( DDR_REG_BASE +0x50ea9*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50eaa*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x50eab*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x50eac*4+0x02000000,0xb2e); +reg_write( DDR_REG_BASE +0x50ead*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50eae*4+0x02000000,0xb7c0); +reg_write( DDR_REG_BASE +0x50eaf*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50eb0*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x50eb1*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50eb2*4+0x02000000,0x1c8); +reg_write( DDR_REG_BASE +0x50eb3*4+0x02000000,0xb7a0); +reg_write( DDR_REG_BASE +0x50eb4*4+0x02000000,0xb8c9); +reg_write( DDR_REG_BASE +0x50eb5*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50eb6*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50eb7*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50eb8*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50eb9*4+0x02000000,0xc1a7); +reg_write( DDR_REG_BASE +0x50eba*4+0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x50ebb*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50ebc*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50ebd*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50ebe*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50ebf*4+0x02000000,0xc144); +reg_write( DDR_REG_BASE +0x50ec0*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50ec1*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x50ec2*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50ec3*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50ec4*4+0x02000000,0x7d8); +reg_write( DDR_REG_BASE +0x50ec5*4+0x02000000,0x8020); +reg_write( DDR_REG_BASE +0x50ec6*4+0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x50ec7*4+0x02000000,0xa92); +reg_write( DDR_REG_BASE +0x50ec8*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50ec9*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50eca*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50ecb*4+0x02000000,0xc6a); +reg_write( DDR_REG_BASE +0x50ecc*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50ecd*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x50ece*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x50ecf*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x50ed0*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x50ed1*4+0x02000000,0x37c0); +reg_write( DDR_REG_BASE +0x50ed2*4+0x02000000,0xe805); +reg_write( DDR_REG_BASE +0x50ed3*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x50ed4*4+0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x50ed5*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x50ed6*4+0x02000000,0x7dbb); +reg_write( DDR_REG_BASE +0x50ed7*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x50ed8*4+0x02000000,0x2553); +reg_write( DDR_REG_BASE +0x50ed9*4+0x02000000,0x1040); +reg_write( DDR_REG_BASE +0x50eda*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x50edb*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x50edc*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50edd*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50ede*4+0x02000000,0xda09); +reg_write( DDR_REG_BASE +0x50edf*4+0x02000000,0xdbff); +reg_write( DDR_REG_BASE +0x50ee0*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x50ee1*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x50ee2*4+0x02000000,0xd12); +reg_write( DDR_REG_BASE +0x50ee3*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50ee4*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x50ee5*4+0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x50ee6*4+0x02000000,0x110d); +reg_write( DDR_REG_BASE +0x50ee7*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50ee8*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x50ee9*4+0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x50eea*4+0x02000000,0x250f); +reg_write( DDR_REG_BASE +0x50eeb*4+0x02000000,0x16c0); +reg_write( DDR_REG_BASE +0x50eec*4+0x02000000,0x7d0f); +reg_write( DDR_REG_BASE +0x50eed*4+0x02000000,0xd840); +reg_write( DDR_REG_BASE +0x50eee*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50eef*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50ef0*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x50ef1*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50ef2*4+0x02000000,0xcf2); +reg_write( DDR_REG_BASE +0x50ef3*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50ef4*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x50ef5*4+0x02000000,0x35c1); +reg_write( DDR_REG_BASE +0x50ef6*4+0x02000000,0xd84b); +reg_write( DDR_REG_BASE +0x50ef7*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50ef8*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50ef9*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x50efa*4+0x02000000,0xda17); +reg_write( DDR_REG_BASE +0x50efb*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x50efc*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x50efd*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50efe*4+0x02000000,0xcda); +reg_write( DDR_REG_BASE +0x50eff*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50f00*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x50f01*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50f02*4+0x02000000,0xc92); +reg_write( DDR_REG_BASE +0x50f03*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50f04*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x50f05*4+0x02000000,0xc52); +reg_write( DDR_REG_BASE +0x50f06*4+0x02000000,0x1c0); +reg_write( DDR_REG_BASE +0x50f07*4+0x02000000,0xa7a); +reg_write( DDR_REG_BASE +0x50f08*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50f09*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x50f0a*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x50f0b*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50f0c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50f0d*4+0x02000000,0x9c40); +reg_write( DDR_REG_BASE +0x50f0e*4+0x02000000,0xac2); +reg_write( DDR_REG_BASE +0x50f0f*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50f10*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x50f11*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50f12*4+0x02000000,0xbda); +reg_write( DDR_REG_BASE +0x50f13*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50f14*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x50f15*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x50f16*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50f17*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x50f18*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50f19*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x50f1a*4+0x02000000,0xda0d); +reg_write( DDR_REG_BASE +0x50f1b*4+0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x50f1c*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x50f1d*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50f1e*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x50f1f*4+0x02000000,0xc9a); +reg_write( DDR_REG_BASE +0x50f20*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50f21*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x50f22*4+0x02000000,0x2756); +reg_write( DDR_REG_BASE +0x50f23*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x50f24*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50f25*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50f26*4+0x02000000,0xd988); +reg_write( DDR_REG_BASE +0x50f27*4+0x02000000,0xda0d); +reg_write( DDR_REG_BASE +0x50f28*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x50f29*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x50f2a*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50f2b*4+0x02000000,0xc82); +reg_write( DDR_REG_BASE +0x50f2c*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50f2d*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x50f2e*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50f2f*4+0x02000000,0xc3a); +reg_write( DDR_REG_BASE +0x50f30*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50f31*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x50f32*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50f33*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50f34*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x50f35*4+0x02000000,0x8ea0); +reg_write( DDR_REG_BASE +0x50f36*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x50f37*4+0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x50f38*4+0x02000000,0xb62); +reg_write( DDR_REG_BASE +0x50f39*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50f3a*4+0x02000000,0x41e1); +reg_write( DDR_REG_BASE +0x50f3b*4+0x02000000,0xe809); +reg_write( DDR_REG_BASE +0x50f3c*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x50f3d*4+0x02000000,0x9c6); +reg_write( DDR_REG_BASE +0x50f3e*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x50f3f*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50f40*4+0x02000000,0xc104); +reg_write( DDR_REG_BASE +0x50f41*4+0x02000000,0x79b4); +reg_write( DDR_REG_BASE +0x50f42*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x50f43*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x50f44*4+0x02000000,0x8e41); +reg_write( DDR_REG_BASE +0x50f45*4+0x02000000,0xae7); +reg_write( DDR_REG_BASE +0x50f46*4+0x02000000,0x8365); +reg_write( DDR_REG_BASE +0x50f47*4+0x02000000,0x7faf); +reg_write( DDR_REG_BASE +0x50f48*4+0x02000000,0x8ee0); +reg_write( DDR_REG_BASE +0x50f49*4+0x02000000,0xf03c); +reg_write( DDR_REG_BASE +0x50f4a*4+0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x50f4b*4+0x02000000,0xb3e); +reg_write( DDR_REG_BASE +0x50f4c*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50f4d*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x50f4e*4+0x02000000,0xe834); +reg_write( DDR_REG_BASE +0x50f4f*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50f50*4+0x02000000,0x99e); +reg_write( DDR_REG_BASE +0x50f51*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x50f52*4+0x02000000,0xd910); +reg_write( DDR_REG_BASE +0x50f53*4+0x02000000,0xc504); +reg_write( DDR_REG_BASE +0x50f54*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x50f55*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50f56*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x50f57*4+0x02000000,0x7df4); +reg_write( DDR_REG_BASE +0x50f58*4+0x02000000,0x9520); +reg_write( DDR_REG_BASE +0x50f59*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50f5a*4+0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x50f5b*4+0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x50f5c*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50f5d*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50f5e*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50f5f*4+0x02000000,0xa96); +reg_write( DDR_REG_BASE +0x50f60*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x50f61*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x50f62*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50f63*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50f64*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x50f65*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50f66*4+0x02000000,0x6); +reg_write( DDR_REG_BASE +0x50f67*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x50f68*4+0x02000000,0x81c3); +reg_write( DDR_REG_BASE +0x50f69*4+0x02000000,0xf706); +reg_write( DDR_REG_BASE +0x50f6a*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x50f6b*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50f6c*4+0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x50f6d*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x50f6e*4+0x02000000,0x9500); +reg_write( DDR_REG_BASE +0x50f6f*4+0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x50f70*4+0x02000000,0x95); +reg_write( DDR_REG_BASE +0x50f71*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50f72*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50f73*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x50f74*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x50f75*4+0x02000000,0x2e05); +reg_write( DDR_REG_BASE +0x50f76*4+0x02000000,0x7000); +reg_write( DDR_REG_BASE +0x50f77*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50f78*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50f79*4+0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x50f7a*4+0x02000000,0x7b10); +reg_write( DDR_REG_BASE +0x50f7b*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x50f7c*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50f7d*4+0x02000000,0xe1); +reg_write( DDR_REG_BASE +0x50f7e*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x50f7f*4+0x02000000,0xfc2); +reg_write( DDR_REG_BASE +0x50f80*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50f81*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x50f82*4+0x02000000,0x8e41); +reg_write( DDR_REG_BASE +0x50f83*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x50f84*4+0x02000000,0xa8d); +reg_write( DDR_REG_BASE +0x50f85*4+0x02000000,0x83e5); +reg_write( DDR_REG_BASE +0x50f86*4+0x02000000,0x7def); +reg_write( DDR_REG_BASE +0x50f87*4+0x02000000,0x8ea0); +reg_write( DDR_REG_BASE +0x50f88*4+0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x50f89*4+0x02000000,0xac2); +reg_write( DDR_REG_BASE +0x50f8a*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50f8b*4+0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x50f8c*4+0x02000000,0xe88a); +reg_write( DDR_REG_BASE +0x50f8d*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x50f8e*4+0x02000000,0xd0b); +reg_write( DDR_REG_BASE +0x50f8f*4+0x02000000,0x103f); +reg_write( DDR_REG_BASE +0x50f90*4+0x02000000,0x78b4); +reg_write( DDR_REG_BASE +0x50f91*4+0x02000000,0x9021); +reg_write( DDR_REG_BASE +0x50f92*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x50f93*4+0x02000000,0x10fe); +reg_write( DDR_REG_BASE +0x50f94*4+0x02000000,0x8101); +reg_write( DDR_REG_BASE +0x50f95*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x50f96*4+0x02000000,0x8e41); +reg_write( DDR_REG_BASE +0x50f97*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x50f98*4+0x02000000,0xae3); +reg_write( DDR_REG_BASE +0x50f99*4+0x02000000,0x8365); +reg_write( DDR_REG_BASE +0x50f9a*4+0x02000000,0x79af); +reg_write( DDR_REG_BASE +0x50f9b*4+0x02000000,0x8e60); +reg_write( DDR_REG_BASE +0x50f9c*4+0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x50f9d*4+0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x50f9e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50f9f*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50fa0*4+0x02000000,0x15c); +reg_write( DDR_REG_BASE +0x50fa1*4+0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x50fa2*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x50fa3*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50fa4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50fa5*4+0x02000000,0x20c0); +reg_write( DDR_REG_BASE +0x50fa6*4+0x02000000,0xa2); +reg_write( DDR_REG_BASE +0x50fa7*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x50fa8*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x50fa9*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50faa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50fab*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x50fac*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x50fad*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x50fae*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x50faf*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x50fb0*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x50fb1*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x50fb2*4+0x02000000,0xad7); +reg_write( DDR_REG_BASE +0x50fb3*4+0x02000000,0x80e5); +reg_write( DDR_REG_BASE +0x50fb4*4+0x02000000,0x7077); +reg_write( DDR_REG_BASE +0x50fb5*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50fb6*4+0x02000000,0xa92); +reg_write( DDR_REG_BASE +0x50fb7*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50fb8*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x50fb9*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x50fba*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50fbb*4+0x02000000,0xda0a); +reg_write( DDR_REG_BASE +0x50fbc*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x50fbd*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50fbe*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x50fbf*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x50fc0*4+0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x50fc1*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x50fc2*4+0x02000000,0xb52); +reg_write( DDR_REG_BASE +0x50fc3*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50fc4*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x50fc5*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50fc6*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50fc7*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x50fc8*4+0x02000000,0x766c); +reg_write( DDR_REG_BASE +0x50fc9*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x50fca*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x50fcb*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50fcc*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x50fcd*4+0x02000000,0xb3e); +reg_write( DDR_REG_BASE +0x50fce*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50fcf*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x50fd0*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x50fd1*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50fd2*4+0x02000000,0xda0e); +reg_write( DDR_REG_BASE +0x50fd3*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x50fd4*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50fd5*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x50fd6*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x50fd7*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x50fd8*4+0x02000000,0xb26); +reg_write( DDR_REG_BASE +0x50fd9*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50fda*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x50fdb*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50fdc*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x50fdd*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x50fde*4+0x02000000,0x766c); +reg_write( DDR_REG_BASE +0x50fdf*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x50fe0*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50fe1*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x50fe2*4+0x02000000,0xb12); +reg_write( DDR_REG_BASE +0x50fe3*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50fe4*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x50fe5*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50fe6*4+0x02000000,0xaca); +reg_write( DDR_REG_BASE +0x50fe7*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50fe8*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x50fe9*4+0x02000000,0xa8a); +reg_write( DDR_REG_BASE +0x50fea*4+0x02000000,0x1c0); +reg_write( DDR_REG_BASE +0x50feb*4+0x02000000,0xc0a7); +reg_write( DDR_REG_BASE +0x50fec*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50fed*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50fee*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50fef*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50ff0*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x50ff1*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x50ff2*4+0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x50ff3*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x50ff4*4+0x02000000,0xd06); +reg_write( DDR_REG_BASE +0x50ff5*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50ff6*4+0x02000000,0x4160); +reg_write( DDR_REG_BASE +0x50ff7*4+0x02000000,0xe8b8); +reg_write( DDR_REG_BASE +0x50ff8*4+0x02000000,0x246f); +reg_write( DDR_REG_BASE +0x50ff9*4+0x02000000,0x1dc3); +reg_write( DDR_REG_BASE +0x50ffa*4+0x02000000,0x8c20); +reg_write( DDR_REG_BASE +0x50ffb*4+0x02000000,0x969); +reg_write( DDR_REG_BASE +0x50ffc*4+0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x50ffd*4+0x02000000,0x142f); +reg_write( DDR_REG_BASE +0x50ffe*4+0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x50fff*4+0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x51000*4+0x02000000,0x1c81); +reg_write( DDR_REG_BASE +0x51001*4+0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x51002*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x51003*4+0x02000000,0x640); +reg_write( DDR_REG_BASE +0x51004*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51005*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x51006*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51007*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51008*4+0x02000000,0x687); +reg_write( DDR_REG_BASE +0x51009*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5100a*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5100b*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5100c*4+0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x5100d*4+0x02000000,0xb9c2); +reg_write( DDR_REG_BASE +0x5100e*4+0x02000000,0xd8f0); +reg_write( DDR_REG_BASE +0x5100f*4+0x02000000,0x2805); +reg_write( DDR_REG_BASE +0x51010*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x51011*4+0x02000000,0xeb05); +reg_write( DDR_REG_BASE +0x51012*4+0x02000000,0x143c); +reg_write( DDR_REG_BASE +0x51013*4+0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x51014*4+0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x51015*4+0x02000000,0x8c09); +reg_write( DDR_REG_BASE +0x51016*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51017*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51018*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51019*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5101a*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x5101b*4+0x02000000,0x7b2f); +reg_write( DDR_REG_BASE +0x5101c*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x5101d*4+0x02000000,0x61); +reg_write( DDR_REG_BASE +0x5101e*4+0x02000000,0xb1b); +reg_write( DDR_REG_BASE +0x5101f*4+0x02000000,0x24); +reg_write( DDR_REG_BASE +0x51020*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51021*4+0x02000000,0x404); +reg_write( DDR_REG_BASE +0x51022*4+0x02000000,0x2b05); +reg_write( DDR_REG_BASE +0x51023*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51024*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x51025*4+0x02000000,0xa0f); +reg_write( DDR_REG_BASE +0x51026*4+0x02000000,0x782c); +reg_write( DDR_REG_BASE +0x51027*4+0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x51028*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x51029*4+0x02000000,0x2805); +reg_write( DDR_REG_BASE +0x5102a*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x5102b*4+0x02000000,0xf96); +reg_write( DDR_REG_BASE +0x5102c*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5102d*4+0x02000000,0x7830); +reg_write( DDR_REG_BASE +0x5102e*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x5102f*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51030*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51031*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x51032*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51033*4+0x02000000,0x22); +reg_write( DDR_REG_BASE +0x51034*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51035*4+0x02000000,0x7de0); +reg_write( DDR_REG_BASE +0x51036*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51037*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x51038*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51039*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x5103a*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5103b*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5103c*4+0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x5103d*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x5103e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5103f*4+0x02000000,0x7ca); +reg_write( DDR_REG_BASE +0x51040*4+0x02000000,0x8b00); +reg_write( DDR_REG_BASE +0x51041*4+0x02000000,0xdea); +reg_write( DDR_REG_BASE +0x51042*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51043*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51044*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51045*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51046*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51047*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51048*4+0x02000000,0x8b82); +reg_write( DDR_REG_BASE +0x51049*4+0x02000000,0x8b41); +reg_write( DDR_REG_BASE +0x5104a*4+0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x5104b*4+0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x5104c*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5104d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5104e*4+0x02000000,0x776c); +reg_write( DDR_REG_BASE +0x5104f*4+0x02000000,0xf01c); +reg_write( DDR_REG_BASE +0x51050*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x51051*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51052*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51053*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x51054*4+0x02000000,0x2104); +reg_write( DDR_REG_BASE +0x51055*4+0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x51056*4+0x02000000,0x37fe); +reg_write( DDR_REG_BASE +0x51057*4+0x02000000,0xf000); +reg_write( DDR_REG_BASE +0x51058*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x51059*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x5105a*4+0x02000000,0x79a5); +reg_write( DDR_REG_BASE +0x5105b*4+0x02000000,0x79c5); +reg_write( DDR_REG_BASE +0x5105c*4+0x02000000,0x6ac1); +reg_write( DDR_REG_BASE +0x5105d*4+0x02000000,0x229a); +reg_write( DDR_REG_BASE +0x5105e*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5105f*4+0x02000000,0x2284); +reg_write( DDR_REG_BASE +0x51060*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51061*4+0x02000000,0x7a25); +reg_write( DDR_REG_BASE +0x51062*4+0x02000000,0x795b); +reg_write( DDR_REG_BASE +0x51063*4+0x02000000,0xb991); +reg_write( DDR_REG_BASE +0x51064*4+0x02000000,0xb99c); +reg_write( DDR_REG_BASE +0x51065*4+0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x51066*4+0x02000000,0x9120); +reg_write( DDR_REG_BASE +0x51067*4+0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x51068*4+0x02000000,0x2108); +reg_write( DDR_REG_BASE +0x51069*4+0x02000000,0xc3); +reg_write( DDR_REG_BASE +0x5106a*4+0x02000000,0xccd); +reg_write( DDR_REG_BASE +0x5106b*4+0x02000000,0x9085); +reg_write( DDR_REG_BASE +0x5106c*4+0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x5106d*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x5106e*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x5106f*4+0x02000000,0x901); +reg_write( DDR_REG_BASE +0x51070*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x51071*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x51072*4+0x02000000,0x796f); +reg_write( DDR_REG_BASE +0x51073*4+0x02000000,0x2179); +reg_write( DDR_REG_BASE +0x51074*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51075*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51076*4+0x02000000,0x7204); +reg_write( DDR_REG_BASE +0x51077*4+0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x51078*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51079*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5107a*4+0x02000000,0x7d8); +reg_write( DDR_REG_BASE +0x5107b*4+0x02000000,0x7bd); +reg_write( DDR_REG_BASE +0x5107c*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5107d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5107e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5107f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51080*4+0x02000000,0x7d8); +reg_write( DDR_REG_BASE +0x51081*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x51082*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51083*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51084*4+0x02000000,0x8020); +reg_write( DDR_REG_BASE +0x51085*4+0x02000000,0x8a00); +reg_write( DDR_REG_BASE +0x51086*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x51087*4+0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x51088*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51089*4+0x02000000,0x8a21); +reg_write( DDR_REG_BASE +0x5108a*4+0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x5108b*4+0x02000000,0x641); +reg_write( DDR_REG_BASE +0x5108c*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x5108d*4+0x02000000,0x8842); +reg_write( DDR_REG_BASE +0x5108e*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5108f*4+0x02000000,0x75); +reg_write( DDR_REG_BASE +0x51090*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51091*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51092*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51093*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51094*4+0x02000000,0x7cb); +reg_write( DDR_REG_BASE +0x51095*4+0x02000000,0x8881); +reg_write( DDR_REG_BASE +0x51096*4+0x02000000,0x8860); +reg_write( DDR_REG_BASE +0x51097*4+0x02000000,0xf022); +reg_write( DDR_REG_BASE +0x51098*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x51099*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5109a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5109b*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x5109c*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x5109d*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x5109e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5109f*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x510a0*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x510a1*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x510a2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x510a3*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x510a4*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x510a5*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x510a6*4+0x02000000,0x6ffd); +reg_write( DDR_REG_BASE +0x510a7*4+0x02000000,0xe000); +reg_write( DDR_REG_BASE +0x510a8*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x510a9*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x510aa*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x510ab*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x510ac*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x510ad*4+0x02000000,0x9220); +reg_write( DDR_REG_BASE +0x510ae*4+0x02000000,0x4928); +reg_write( DDR_REG_BASE +0x510af*4+0x02000000,0x208b); +reg_write( DDR_REG_BASE +0x510b0*4+0x02000000,0x880f); +reg_write( DDR_REG_BASE +0x510b1*4+0x02000000,0xf206); +reg_write( DDR_REG_BASE +0x510b2*4+0x02000000,0x2142); +reg_write( DDR_REG_BASE +0x510b3*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x510b4*4+0x02000000,0x2080); +reg_write( DDR_REG_BASE +0x510b5*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x510b6*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x510b7*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x510b8*4+0x02000000,0xcc1); +reg_write( DDR_REG_BASE +0x510b9*4+0x02000000,0x90c5); +reg_write( DDR_REG_BASE +0x510ba*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x510bb*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x510bc*4+0x02000000,0xc0e4); +reg_write( DDR_REG_BASE +0x510bd*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x510be*4+0x02000000,0x259a); +reg_write( DDR_REG_BASE +0x510bf*4+0x02000000,0x1008); +reg_write( DDR_REG_BASE +0x510c0*4+0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x510c1*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x510c2*4+0x02000000,0x48); +reg_write( DDR_REG_BASE +0x510c3*4+0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x510c4*4+0x02000000,0x130e); +reg_write( DDR_REG_BASE +0x510c5*4+0x02000000,0xb620); +reg_write( DDR_REG_BASE +0x510c6*4+0x02000000,0x6c22); +reg_write( DDR_REG_BASE +0x510c7*4+0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x510c8*4+0x02000000,0x104c); +reg_write( DDR_REG_BASE +0x510c9*4+0x02000000,0x7224); +reg_write( DDR_REG_BASE +0x510ca*4+0x02000000,0xb440); +reg_write( DDR_REG_BASE +0x510cb*4+0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x510cc*4+0x02000000,0x1042); +reg_write( DDR_REG_BASE +0x510cd*4+0x02000000,0xb260); +reg_write( DDR_REG_BASE +0x510ce*4+0x02000000,0x6962); +reg_write( DDR_REG_BASE +0x510cf*4+0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x510d0*4+0x02000000,0x7d65); +reg_write( DDR_REG_BASE +0x510d1*4+0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x510d2*4+0x02000000,0x3f1); +reg_write( DDR_REG_BASE +0x510d3*4+0x02000000,0xb520); +reg_write( DDR_REG_BASE +0x510d4*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x510d5*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x510d6*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x510d7*4+0x02000000,0x137c); +reg_write( DDR_REG_BASE +0x510d8*4+0x02000000,0x101); +reg_write( DDR_REG_BASE +0x510d9*4+0x02000000,0x210f); +reg_write( DDR_REG_BASE +0x510da*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x510db*4+0x02000000,0x1b7c); +reg_write( DDR_REG_BASE +0x510dc*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x510dd*4+0x02000000,0xc4c4); +reg_write( DDR_REG_BASE +0x510de*4+0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x510df*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x510e0*4+0x02000000,0xc2); +reg_write( DDR_REG_BASE +0x510e1*4+0x02000000,0x1c02); +reg_write( DDR_REG_BASE +0x510e2*4+0x02000000,0x1014); +reg_write( DDR_REG_BASE +0x510e3*4+0x02000000,0xb420); +reg_write( DDR_REG_BASE +0x510e4*4+0x02000000,0xb441); +reg_write( DDR_REG_BASE +0x510e5*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x510e6*4+0x02000000,0xb462); +reg_write( DDR_REG_BASE +0x510e7*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x510e8*4+0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x510e9*4+0x02000000,0x4320); +reg_write( DDR_REG_BASE +0x510ea*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x510eb*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x510ec*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x510ed*4+0x02000000,0x7d0); +reg_write( DDR_REG_BASE +0x510ee*4+0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x510ef*4+0x02000000,0xf06); +reg_write( DDR_REG_BASE +0x510f0*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x510f1*4+0x02000000,0x203c); +reg_write( DDR_REG_BASE +0x510f2*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x510f3*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x510f4*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x510f5*4+0x02000000,0xf427); +reg_write( DDR_REG_BASE +0x510f6*4+0x02000000,0xde25); +reg_write( DDR_REG_BASE +0x510f7*4+0x02000000,0xbe9f); +reg_write( DDR_REG_BASE +0x510f8*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x510f9*4+0x02000000,0xf01f); +reg_write( DDR_REG_BASE +0x510fa*4+0x02000000,0xec04); +reg_write( DDR_REG_BASE +0x510fb*4+0x02000000,0x1633); +reg_write( DDR_REG_BASE +0x510fc*4+0x02000000,0x1082); +reg_write( DDR_REG_BASE +0x510fd*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x510fe*4+0x02000000,0x8e40); +reg_write( DDR_REG_BASE +0x510ff*4+0x02000000,0xa31); +reg_write( DDR_REG_BASE +0x51100*4+0x02000000,0x6e); +reg_write( DDR_REG_BASE +0x51101*4+0x02000000,0x2114); +reg_write( DDR_REG_BASE +0x51102*4+0x02000000,0x302); +reg_write( DDR_REG_BASE +0x51103*4+0x02000000,0x2232); +reg_write( DDR_REG_BASE +0x51104*4+0x02000000,0xf8b); +reg_write( DDR_REG_BASE +0x51105*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51106*4+0x02000000,0x784); +reg_write( DDR_REG_BASE +0x51107*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51108*4+0x02000000,0xa1d); +reg_write( DDR_REG_BASE +0x51109*4+0x02000000,0x2c5); +reg_write( DDR_REG_BASE +0x5110a*4+0x02000000,0x245a); +reg_write( DDR_REG_BASE +0x5110b*4+0x02000000,0x140d); +reg_write( DDR_REG_BASE +0x5110c*4+0x02000000,0x7d36); +reg_write( DDR_REG_BASE +0x5110d*4+0x02000000,0x655d); +reg_write( DDR_REG_BASE +0x5110e*4+0x02000000,0x2532); +reg_write( DDR_REG_BASE +0x5110f*4+0x02000000,0x1f8d); +reg_write( DDR_REG_BASE +0x51110*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51111*4+0x02000000,0x7a8); +reg_write( DDR_REG_BASE +0x51112*4+0x02000000,0xded); +reg_write( DDR_REG_BASE +0x51113*4+0x02000000,0x90e1); +reg_write( DDR_REG_BASE +0x51114*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x51115*4+0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x51116*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x51117*4+0x02000000,0xcc9); +reg_write( DDR_REG_BASE +0x51118*4+0x02000000,0x9094); +reg_write( DDR_REG_BASE +0x51119*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5111a*4+0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x5111b*4+0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x5111c*4+0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x5111d*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5111e*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5111f*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51120*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51121*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51122*4+0x02000000,0xe064); +reg_write( DDR_REG_BASE +0x51123*4+0x02000000,0x2145); +reg_write( DDR_REG_BASE +0x51124*4+0x02000000,0x7c1); +reg_write( DDR_REG_BASE +0x51125*4+0x02000000,0x779); +reg_write( DDR_REG_BASE +0x51126*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x51127*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51128*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51129*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5112a*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5112b*4+0x02000000,0xc1a3); +reg_write( DDR_REG_BASE +0x5112c*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5112d*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x5112e*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x5112f*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51130*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x51131*4+0x02000000,0xafd); +reg_write( DDR_REG_BASE +0x51132*4+0x02000000,0x8674); +reg_write( DDR_REG_BASE +0x51133*4+0x02000000,0x2014); +reg_write( DDR_REG_BASE +0x51134*4+0x02000000,0x81); +reg_write( DDR_REG_BASE +0x51135*4+0x02000000,0xdb32); +reg_write( DDR_REG_BASE +0x51136*4+0x02000000,0xbb9f); +reg_write( DDR_REG_BASE +0x51137*4+0x02000000,0x8b20); +reg_write( DDR_REG_BASE +0x51138*4+0x02000000,0xa821); +reg_write( DDR_REG_BASE +0x51139*4+0x02000000,0x6b21); +reg_write( DDR_REG_BASE +0x5113a*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x5113b*4+0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x5113c*4+0x02000000,0xa822); +reg_write( DDR_REG_BASE +0x5113d*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x5113e*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x5113f*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51140*4+0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x51141*4+0x02000000,0xa823); +reg_write( DDR_REG_BASE +0x51142*4+0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x51143*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x51144*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x51145*4+0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x51146*4+0x02000000,0xa824); +reg_write( DDR_REG_BASE +0x51147*4+0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x51148*4+0x02000000,0x6941); +reg_write( DDR_REG_BASE +0x51149*4+0x02000000,0x8a20); +reg_write( DDR_REG_BASE +0x5114a*4+0x02000000,0x2240); +reg_write( DDR_REG_BASE +0x5114b*4+0x02000000,0x5f); +reg_write( DDR_REG_BASE +0x5114c*4+0x02000000,0x2740); +reg_write( DDR_REG_BASE +0x5114d*4+0x02000000,0x304c); +reg_write( DDR_REG_BASE +0x5114e*4+0x02000000,0xa82b); +reg_write( DDR_REG_BASE +0x5114f*4+0x02000000,0x1700); +reg_write( DDR_REG_BASE +0x51150*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x51151*4+0x02000000,0x6ca1); +reg_write( DDR_REG_BASE +0x51152*4+0x02000000,0x6dc1); +reg_write( DDR_REG_BASE +0x51153*4+0x02000000,0xa82c); +reg_write( DDR_REG_BASE +0x51154*4+0x02000000,0x8c20); +reg_write( DDR_REG_BASE +0x51155*4+0x02000000,0x6ee1); +reg_write( DDR_REG_BASE +0x51156*4+0x02000000,0x4358); +reg_write( DDR_REG_BASE +0x51157*4+0x02000000,0xa82d); +reg_write( DDR_REG_BASE +0x51158*4+0x02000000,0x8d20); +reg_write( DDR_REG_BASE +0x51159*4+0x02000000,0xa82e); +reg_write( DDR_REG_BASE +0x5115a*4+0x02000000,0x8e20); +reg_write( DDR_REG_BASE +0x5115b*4+0x02000000,0xa830); +reg_write( DDR_REG_BASE +0x5115c*4+0x02000000,0x8f20); +reg_write( DDR_REG_BASE +0x5115d*4+0x02000000,0xa831); +reg_write( DDR_REG_BASE +0x5115e*4+0x02000000,0x8f21); +reg_write( DDR_REG_BASE +0x5115f*4+0x02000000,0xa836); +reg_write( DDR_REG_BASE +0x51160*4+0x02000000,0x8f22); +reg_write( DDR_REG_BASE +0x51161*4+0x02000000,0xa838); +reg_write( DDR_REG_BASE +0x51162*4+0x02000000,0x13e6); +reg_write( DDR_REG_BASE +0x51163*4+0x02000000,0x8081); +reg_write( DDR_REG_BASE +0x51164*4+0x02000000,0xe930); +reg_write( DDR_REG_BASE +0x51165*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x51166*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x51167*4+0x02000000,0xf02a); +reg_write( DDR_REG_BASE +0x51168*4+0x02000000,0x265a); +reg_write( DDR_REG_BASE +0x51169*4+0x02000000,0x3c82); +reg_write( DDR_REG_BASE +0x5116a*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x5116b*4+0x02000000,0x1641); +reg_write( DDR_REG_BASE +0x5116c*4+0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x5116d*4+0x02000000,0x621a); +reg_write( DDR_REG_BASE +0x5116e*4+0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x5116f*4+0x02000000,0x8b40); +reg_write( DDR_REG_BASE +0x51170*4+0x02000000,0xa941); +reg_write( DDR_REG_BASE +0x51171*4+0x02000000,0xc200); +reg_write( DDR_REG_BASE +0x51172*4+0x02000000,0x8a40); +reg_write( DDR_REG_BASE +0x51173*4+0x02000000,0xa942); +reg_write( DDR_REG_BASE +0x51174*4+0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x51175*4+0x02000000,0x8a40); +reg_write( DDR_REG_BASE +0x51176*4+0x02000000,0xa943); +reg_write( DDR_REG_BASE +0x51177*4+0x02000000,0xc202); +reg_write( DDR_REG_BASE +0x51178*4+0x02000000,0x8a40); +reg_write( DDR_REG_BASE +0x51179*4+0x02000000,0xa944); +reg_write( DDR_REG_BASE +0x5117a*4+0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x5117b*4+0x02000000,0x3082); +reg_write( DDR_REG_BASE +0x5117c*4+0x02000000,0xa94b); +reg_write( DDR_REG_BASE +0x5117d*4+0x02000000,0x1700); +reg_write( DDR_REG_BASE +0x5117e*4+0x02000000,0x3082); +reg_write( DDR_REG_BASE +0x5117f*4+0x02000000,0xa94c); +reg_write( DDR_REG_BASE +0x51180*4+0x02000000,0x8c40); +reg_write( DDR_REG_BASE +0x51181*4+0x02000000,0xa94d); +reg_write( DDR_REG_BASE +0x51182*4+0x02000000,0x8d40); +reg_write( DDR_REG_BASE +0x51183*4+0x02000000,0xa94e); +reg_write( DDR_REG_BASE +0x51184*4+0x02000000,0x8e40); +reg_write( DDR_REG_BASE +0x51185*4+0x02000000,0xa950); +reg_write( DDR_REG_BASE +0x51186*4+0x02000000,0x8f40); +reg_write( DDR_REG_BASE +0x51187*4+0x02000000,0xa951); +reg_write( DDR_REG_BASE +0x51188*4+0x02000000,0x8f41); +reg_write( DDR_REG_BASE +0x51189*4+0x02000000,0xa956); +reg_write( DDR_REG_BASE +0x5118a*4+0x02000000,0x8f42); +reg_write( DDR_REG_BASE +0x5118b*4+0x02000000,0xa958); +reg_write( DDR_REG_BASE +0x5118c*4+0x02000000,0xbb9); +reg_write( DDR_REG_BASE +0x5118d*4+0x02000000,0x9094); +reg_write( DDR_REG_BASE +0x5118e*4+0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x5118f*4+0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x51190*4+0x02000000,0xef9); +reg_write( DDR_REG_BASE +0x51191*4+0x02000000,0xb0b4); +reg_write( DDR_REG_BASE +0x51192*4+0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x51193*4+0x02000000,0xf08d); +reg_write( DDR_REG_BASE +0x51194*4+0x02000000,0xda3e); +reg_write( DDR_REG_BASE +0x51195*4+0x02000000,0xba9f); +reg_write( DDR_REG_BASE +0x51196*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x51197*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x51198*4+0x02000000,0xa83a); +reg_write( DDR_REG_BASE +0x51199*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x5119a*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x5119b*4+0x02000000,0xa83b); +reg_write( DDR_REG_BASE +0x5119c*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x5119d*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x5119e*4+0x02000000,0xa83c); +reg_write( DDR_REG_BASE +0x5119f*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511a0*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511a1*4+0x02000000,0xa83d); +reg_write( DDR_REG_BASE +0x511a2*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511a3*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511a4*4+0x02000000,0x1824); +reg_write( DDR_REG_BASE +0x511a5*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511a6*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511a7*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511a8*4+0x02000000,0x1825); +reg_write( DDR_REG_BASE +0x511a9*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511aa*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511ab*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511ac*4+0x02000000,0x1826); +reg_write( DDR_REG_BASE +0x511ad*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511ae*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511af*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511b0*4+0x02000000,0x1827); +reg_write( DDR_REG_BASE +0x511b1*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511b2*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511b3*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511b4*4+0x02000000,0x1829); +reg_write( DDR_REG_BASE +0x511b5*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511b6*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511b7*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511b8*4+0x02000000,0x182a); +reg_write( DDR_REG_BASE +0x511b9*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511ba*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511bb*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511bc*4+0x02000000,0x182f); +reg_write( DDR_REG_BASE +0x511bd*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511be*4+0x02000000,0x121c); +reg_write( DDR_REG_BASE +0x511bf*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511c0*4+0x02000000,0x1831); +reg_write( DDR_REG_BASE +0x511c1*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511c2*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511c3*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511c4*4+0x02000000,0x1833); +reg_write( DDR_REG_BASE +0x511c5*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511c6*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511c7*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511c8*4+0x02000000,0x1834); +reg_write( DDR_REG_BASE +0x511c9*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511ca*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511cb*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511cc*4+0x02000000,0x1835); +reg_write( DDR_REG_BASE +0x511cd*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511ce*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511cf*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511d0*4+0x02000000,0x1836); +reg_write( DDR_REG_BASE +0x511d1*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511d2*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511d3*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511d4*4+0x02000000,0x183d); +reg_write( DDR_REG_BASE +0x511d5*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511d6*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511d7*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511d8*4+0x02000000,0x183e); +reg_write( DDR_REG_BASE +0x511d9*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511da*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511db*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511dc*4+0x02000000,0x183f); +reg_write( DDR_REG_BASE +0x511dd*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511de*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511df*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511e0*4+0x02000000,0x1840); +reg_write( DDR_REG_BASE +0x511e1*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511e2*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511e3*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511e4*4+0x02000000,0x1842); +reg_write( DDR_REG_BASE +0x511e5*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511e6*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511e7*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511e8*4+0x02000000,0x1843); +reg_write( DDR_REG_BASE +0x511e9*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511ea*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511eb*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511ec*4+0x02000000,0x1848); +reg_write( DDR_REG_BASE +0x511ed*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511ee*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511ef*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511f0*4+0x02000000,0x184a); +reg_write( DDR_REG_BASE +0x511f1*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511f2*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511f3*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511f4*4+0x02000000,0x184c); +reg_write( DDR_REG_BASE +0x511f5*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511f6*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511f7*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511f8*4+0x02000000,0x184d); +reg_write( DDR_REG_BASE +0x511f9*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511fa*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511fb*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511fc*4+0x02000000,0x184e); +reg_write( DDR_REG_BASE +0x511fd*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511fe*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511ff*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x51200*4+0x02000000,0x184f); +reg_write( DDR_REG_BASE +0x51201*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x51202*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x51203*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x51204*4+0x02000000,0x1856); +reg_write( DDR_REG_BASE +0x51205*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x51206*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x51207*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x51208*4+0x02000000,0x1857); +reg_write( DDR_REG_BASE +0x51209*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x5120a*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x5120b*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x5120c*4+0x02000000,0x1858); +reg_write( DDR_REG_BASE +0x5120d*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x5120e*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x5120f*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x51210*4+0x02000000,0x1859); +reg_write( DDR_REG_BASE +0x51211*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x51212*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x51213*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x51214*4+0x02000000,0x185b); +reg_write( DDR_REG_BASE +0x51215*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x51216*4+0x02000000,0x8a20); +reg_write( DDR_REG_BASE +0x51217*4+0x02000000,0x185c); +reg_write( DDR_REG_BASE +0x51218*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x51219*4+0x02000000,0x8a21); +reg_write( DDR_REG_BASE +0x5121a*4+0x02000000,0x1861); +reg_write( DDR_REG_BASE +0x5121b*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x5121c*4+0x02000000,0x8a22); +reg_write( DDR_REG_BASE +0x5121d*4+0x02000000,0x1863); +reg_write( DDR_REG_BASE +0x5121e*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x5121f*4+0x02000000,0xc0a3); +reg_write( DDR_REG_BASE +0x51220*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x51221*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x51222*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51223*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51224*4+0x02000000,0xc3e4); +reg_write( DDR_REG_BASE +0x51225*4+0x02000000,0xc1ab); +reg_write( DDR_REG_BASE +0x51226*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x51227*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51228*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51229*4+0x02000000,0x650); +reg_write( DDR_REG_BASE +0x5122a*4+0x02000000,0xc2e); +reg_write( DDR_REG_BASE +0x5122b*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5122c*4+0x02000000,0xda2a); +reg_write( DDR_REG_BASE +0x5122d*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x5122e*4+0x02000000,0x92e); +reg_write( DDR_REG_BASE +0x5122f*4+0x02000000,0x2a0); +reg_write( DDR_REG_BASE +0x51230*4+0x02000000,0xd92a); +reg_write( DDR_REG_BASE +0x51231*4+0x02000000,0xdd25); +reg_write( DDR_REG_BASE +0x51232*4+0x02000000,0xbd9f); +reg_write( DDR_REG_BASE +0x51233*4+0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x51234*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51235*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51236*4+0x02000000,0xe4); +reg_write( DDR_REG_BASE +0x51237*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x51238*4+0x02000000,0x1533); +reg_write( DDR_REG_BASE +0x51239*4+0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x5123a*4+0x02000000,0xb601); +reg_write( DDR_REG_BASE +0x5123b*4+0x02000000,0x15f4); +reg_write( DDR_REG_BASE +0x5123c*4+0x02000000,0x9080); +reg_write( DDR_REG_BASE +0x5123d*4+0x02000000,0xe888); +reg_write( DDR_REG_BASE +0x5123e*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5123f*4+0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x51240*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51241*4+0x02000000,0xe154); +reg_write( DDR_REG_BASE +0x51242*4+0x02000000,0x1e42); +reg_write( DDR_REG_BASE +0x51243*4+0x02000000,0x905d); +reg_write( DDR_REG_BASE +0x51244*4+0x02000000,0xbda); +reg_write( DDR_REG_BASE +0x51245*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x51246*4+0x02000000,0x2053); +reg_write( DDR_REG_BASE +0x51247*4+0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x51248*4+0x02000000,0x1a01); +reg_write( DDR_REG_BASE +0x51249*4+0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x5124a*4+0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x5124b*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x5124c*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x5124d*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x5124e*4+0x02000000,0xb9c3); +reg_write( DDR_REG_BASE +0x5124f*4+0x02000000,0x1a02); +reg_write( DDR_REG_BASE +0x51250*4+0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x51251*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x51252*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x51253*4+0x02000000,0x901); +reg_write( DDR_REG_BASE +0x51254*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x51255*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51256*4+0x02000000,0xb8c1); +reg_write( DDR_REG_BASE +0x51257*4+0x02000000,0xdea); +reg_write( DDR_REG_BASE +0x51258*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x51259*4+0x02000000,0x1a06); +reg_write( DDR_REG_BASE +0x5125a*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x5125b*4+0x02000000,0x9ce); +reg_write( DDR_REG_BASE +0x5125c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5125d*4+0x02000000,0x8b2); +reg_write( DDR_REG_BASE +0x5125e*4+0x02000000,0x1c0); +reg_write( DDR_REG_BASE +0x5125f*4+0x02000000,0x164c); +reg_write( DDR_REG_BASE +0x51260*4+0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x51261*4+0x02000000,0x80d); +reg_write( DDR_REG_BASE +0x51262*4+0x02000000,0x151); +reg_write( DDR_REG_BASE +0x51263*4+0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x51264*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x51265*4+0x02000000,0xb601); +reg_write( DDR_REG_BASE +0x51266*4+0x02000000,0xc7c4); +reg_write( DDR_REG_BASE +0x51267*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51268*4+0x02000000,0xc3e2); +reg_write( DDR_REG_BASE +0x51269*4+0x02000000,0xc1bd); +reg_write( DDR_REG_BASE +0x5126a*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x5126b*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x5126c*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5126d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5126e*4+0x02000000,0x4ad); +reg_write( DDR_REG_BASE +0x5126f*4+0x02000000,0xba6); +reg_write( DDR_REG_BASE +0x51270*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51271*4+0x02000000,0xda72); +reg_write( DDR_REG_BASE +0x51272*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x51273*4+0x02000000,0x8a6); +reg_write( DDR_REG_BASE +0x51274*4+0x02000000,0x2a0); +reg_write( DDR_REG_BASE +0x51275*4+0x02000000,0xd972); +reg_write( DDR_REG_BASE +0x51276*4+0x02000000,0xed07); +reg_write( DDR_REG_BASE +0x51277*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x51278*4+0x02000000,0xc07); +reg_write( DDR_REG_BASE +0x51279*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5127a*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x5127b*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5127c*4+0x02000000,0xe8c4); +reg_write( DDR_REG_BASE +0x5127d*4+0x02000000,0xc7c2); +reg_write( DDR_REG_BASE +0x5127e*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5127f*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51280*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51281*4+0x02000000,0xc1a7); +reg_write( DDR_REG_BASE +0x51282*4+0x02000000,0xbfa); +reg_write( DDR_REG_BASE +0x51283*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51284*4+0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x51285*4+0x02000000,0xb72); +reg_write( DDR_REG_BASE +0x51286*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51287*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x51288*4+0x02000000,0xbe2); +reg_write( DDR_REG_BASE +0x51289*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5128a*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5128b*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x5128c*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5128d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5128e*4+0x02000000,0x2710); +reg_write( DDR_REG_BASE +0x5128f*4+0x02000000,0xbe2); +reg_write( DDR_REG_BASE +0x51290*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x51291*4+0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x51292*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x51293*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51294*4+0x02000000,0xcd6); +reg_write( DDR_REG_BASE +0x51295*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51296*4+0x02000000,0xd91f); +reg_write( DDR_REG_BASE +0x51297*4+0x02000000,0xca00); +reg_write( DDR_REG_BASE +0x51298*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51299*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x5129a*4+0x02000000,0x7604); +reg_write( DDR_REG_BASE +0x5129b*4+0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x5129c*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5129d*4+0x02000000,0xb98e); +reg_write( DDR_REG_BASE +0x5129e*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5129f*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x512a0*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x512a1*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x512a2*4+0x02000000,0xd92); +reg_write( DDR_REG_BASE +0x512a3*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512a4*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x512a5*4+0x02000000,0x7bcf); +reg_write( DDR_REG_BASE +0x512a6*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x512a7*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x512a8*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x512a9*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x512aa*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x512ab*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x512ac*4+0x02000000,0xd7e); +reg_write( DDR_REG_BASE +0x512ad*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512ae*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x512af*4+0x02000000,0x71cd); +reg_write( DDR_REG_BASE +0x512b0*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x512b1*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x512b2*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x512b3*4+0x02000000,0xdb7c); +reg_write( DDR_REG_BASE +0x512b4*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x512b5*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x512b6*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x512b7*4+0x02000000,0xd6a); +reg_write( DDR_REG_BASE +0x512b8*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512b9*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x512ba*4+0x02000000,0xfae); +reg_write( DDR_REG_BASE +0x512bb*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512bc*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x512bd*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x512be*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x512bf*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x512c0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x512c1*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x512c2*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x512c3*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x512c4*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x512c5*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x512c6*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x512c7*4+0x02000000,0xd4a); +reg_write( DDR_REG_BASE +0x512c8*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512c9*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x512ca*4+0x02000000,0xf838); +reg_write( DDR_REG_BASE +0x512cb*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x512cc*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x512cd*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x512ce*4+0x02000000,0xd3a); +reg_write( DDR_REG_BASE +0x512cf*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512d0*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x512d1*4+0x02000000,0xf835); +reg_write( DDR_REG_BASE +0x512d2*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x512d3*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x512d4*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x512d5*4+0x02000000,0xd2e); +reg_write( DDR_REG_BASE +0x512d6*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512d7*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x512d8*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x512d9*4+0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x512da*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x512db*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x512dc*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x512dd*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x512de*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x512df*4+0x02000000,0xd1a); +reg_write( DDR_REG_BASE +0x512e0*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512e1*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x512e2*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x512e3*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x512e4*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x512e5*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x512e6*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x512e7*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x512e8*4+0x02000000,0xe020); +reg_write( DDR_REG_BASE +0x512e9*4+0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x512ea*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x512eb*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x512ec*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x512ed*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x512ee*4+0x02000000,0xcfa); +reg_write( DDR_REG_BASE +0x512ef*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512f0*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x512f1*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x512f2*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x512f3*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x512f4*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x512f5*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x512f6*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x512f7*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x512f8*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x512f9*4+0x02000000,0xce6); +reg_write( DDR_REG_BASE +0x512fa*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512fb*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x512fc*4+0x02000000,0xc105); +reg_write( DDR_REG_BASE +0x512fd*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x512fe*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x512ff*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51300*4+0x02000000,0x7914); +reg_write( DDR_REG_BASE +0x51301*4+0x02000000,0x2154); +reg_write( DDR_REG_BASE +0x51302*4+0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x51303*4+0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x51304*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51305*4+0x02000000,0x2054); +reg_write( DDR_REG_BASE +0x51306*4+0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x51307*4+0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x51308*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51309*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x5130a*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5130b*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5130c*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x5130d*4+0x02000000,0xcbe); +reg_write( DDR_REG_BASE +0x5130e*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5130f*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51310*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51311*4+0x02000000,0xb88e); +reg_write( DDR_REG_BASE +0x51312*4+0x02000000,0x791b); +reg_write( DDR_REG_BASE +0x51313*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51314*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x51315*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x51316*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x51317*4+0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x51318*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51319*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5131a*4+0x02000000,0xca2); +reg_write( DDR_REG_BASE +0x5131b*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5131c*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5131d*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5131e*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5131f*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x51320*4+0x02000000,0xdb40); +reg_write( DDR_REG_BASE +0x51321*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51322*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51323*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51324*4+0x02000000,0xc8e); +reg_write( DDR_REG_BASE +0x51325*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51326*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51327*4+0x02000000,0xeba); +reg_write( DDR_REG_BASE +0x51328*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51329*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5132a*4+0x02000000,0xbfc1); +reg_write( DDR_REG_BASE +0x5132b*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5132c*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x5132d*4+0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x5132e*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x5132f*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51330*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51331*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51332*4+0x02000000,0xc72); +reg_write( DDR_REG_BASE +0x51333*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51334*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x51335*4+0x02000000,0xc0a7); +reg_write( DDR_REG_BASE +0x51336*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x51337*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x51338*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51339*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5133a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5133b*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x5133c*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5133d*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x5133e*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x5133f*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51340*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51341*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51342*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51343*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51344*4+0x02000000,0x7101); +reg_write( DDR_REG_BASE +0x51345*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51346*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x51347*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51348*4+0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x51349*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5134a*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5134b*4+0x02000000,0x225f); +reg_write( DDR_REG_BASE +0x5134c*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5134d*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x5134e*4+0x02000000,0x7c3); +reg_write( DDR_REG_BASE +0x5134f*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x51350*4+0x02000000,0xeb05); +reg_write( DDR_REG_BASE +0x51351*4+0x02000000,0xbb61); +reg_write( DDR_REG_BASE +0x51352*4+0x02000000,0xbff); +reg_write( DDR_REG_BASE +0x51353*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x51354*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51355*4+0x02000000,0xb8c3); +reg_write( DDR_REG_BASE +0x51356*4+0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x51357*4+0x02000000,0x190); +reg_write( DDR_REG_BASE +0x51358*4+0x02000000,0x877); +reg_write( DDR_REG_BASE +0x51359*4+0x02000000,0x71); +reg_write( DDR_REG_BASE +0x5135a*4+0x02000000,0xdf18); +reg_write( DDR_REG_BASE +0x5135b*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x5135c*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5135d*4+0x02000000,0x116); +reg_write( DDR_REG_BASE +0x5135e*4+0x02000000,0x1e08); +reg_write( DDR_REG_BASE +0x5135f*4+0x02000000,0x1094); +reg_write( DDR_REG_BASE +0x51360*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x51361*4+0x02000000,0x1e02); +reg_write( DDR_REG_BASE +0x51362*4+0x02000000,0x1055); +reg_write( DDR_REG_BASE +0x51363*4+0x02000000,0xd829); +reg_write( DDR_REG_BASE +0x51364*4+0x02000000,0xb6a0); +reg_write( DDR_REG_BASE +0x51365*4+0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x51366*4+0x02000000,0x1205); +reg_write( DDR_REG_BASE +0x51367*4+0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x51368*4+0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x51369*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5136a*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5136b*4+0x02000000,0x98); +reg_write( DDR_REG_BASE +0x5136c*4+0x02000000,0x9680); +reg_write( DDR_REG_BASE +0x5136d*4+0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x5136e*4+0x02000000,0x1ef2); +reg_write( DDR_REG_BASE +0x5136f*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x51370*4+0x02000000,0x9fe); +reg_write( DDR_REG_BASE +0x51371*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x51372*4+0x02000000,0x1e66); +reg_write( DDR_REG_BASE +0x51373*4+0x02000000,0x1044); +reg_write( DDR_REG_BASE +0x51374*4+0x02000000,0xd8a9); +reg_write( DDR_REG_BASE +0x51375*4+0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x51376*4+0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x51377*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x51378*4+0x02000000,0xa46); +reg_write( DDR_REG_BASE +0x51379*4+0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x5137a*4+0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x5137b*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x5137c*4+0x02000000,0xa44); +reg_write( DDR_REG_BASE +0x5137d*4+0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x5137e*4+0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x5137f*4+0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x51380*4+0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x51381*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51382*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51383*4+0x02000000,0x6000); +reg_write( DDR_REG_BASE +0x51384*4+0x02000000,0x1e72); +reg_write( DDR_REG_BASE +0x51385*4+0x02000000,0x935c); +reg_write( DDR_REG_BASE +0x51386*4+0x02000000,0x1ed0); +reg_write( DDR_REG_BASE +0x51387*4+0x02000000,0x9344); +reg_write( DDR_REG_BASE +0x51388*4+0x02000000,0x1e72); +reg_write( DDR_REG_BASE +0x51389*4+0x02000000,0x90dd); +reg_write( DDR_REG_BASE +0x5138a*4+0x02000000,0x972); +reg_write( DDR_REG_BASE +0x5138b*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5138c*4+0x02000000,0x1ed0); +reg_write( DDR_REG_BASE +0x5138d*4+0x02000000,0x92c4); +reg_write( DDR_REG_BASE +0x5138e*4+0x02000000,0x1e72); +reg_write( DDR_REG_BASE +0x5138f*4+0x02000000,0x935c); +reg_write( DDR_REG_BASE +0x51390*4+0x02000000,0x1e72); +reg_write( DDR_REG_BASE +0x51391*4+0x02000000,0x92dc); +reg_write( DDR_REG_BASE +0x51392*4+0x02000000,0xf046); +reg_write( DDR_REG_BASE +0x51393*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x51394*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51395*4+0x02000000,0x116); +reg_write( DDR_REG_BASE +0x51396*4+0x02000000,0x1d08); +reg_write( DDR_REG_BASE +0x51397*4+0x02000000,0x1094); +reg_write( DDR_REG_BASE +0x51398*4+0x02000000,0x71cd); +reg_write( DDR_REG_BASE +0x51399*4+0x02000000,0x1d02); +reg_write( DDR_REG_BASE +0x5139a*4+0x02000000,0x1055); +reg_write( DDR_REG_BASE +0x5139b*4+0x02000000,0x234a); +reg_write( DDR_REG_BASE +0x5139c*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x5139d*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5139e*4+0x02000000,0xbf8b); +reg_write( DDR_REG_BASE +0x5139f*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x513a0*4+0x02000000,0xf); +reg_write( DDR_REG_BASE +0x513a1*4+0x02000000,0x4240); +reg_write( DDR_REG_BASE +0x513a2*4+0x02000000,0xb5c0); +reg_write( DDR_REG_BASE +0x513a3*4+0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x513a4*4+0x02000000,0x12c4); +reg_write( DDR_REG_BASE +0x513a5*4+0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x513a6*4+0x02000000,0x3040); +reg_write( DDR_REG_BASE +0x513a7*4+0x02000000,0x1df2); +reg_write( DDR_REG_BASE +0x513a8*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x513a9*4+0x02000000,0x1d66); +reg_write( DDR_REG_BASE +0x513aa*4+0x02000000,0x1044); +reg_write( DDR_REG_BASE +0x513ab*4+0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x513ac*4+0x02000000,0x13c4); +reg_write( DDR_REG_BASE +0x513ad*4+0x02000000,0x986); +reg_write( DDR_REG_BASE +0x513ae*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x513af*4+0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x513b0*4+0x02000000,0xbf70); +reg_write( DDR_REG_BASE +0x513b1*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x513b2*4+0x02000000,0x6c2); +reg_write( DDR_REG_BASE +0x513b3*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x513b4*4+0x02000000,0x976); +reg_write( DDR_REG_BASE +0x513b5*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x513b6*4+0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x513b7*4+0x02000000,0x13c4); +reg_write( DDR_REG_BASE +0x513b8*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x513b9*4+0x02000000,0x98); +reg_write( DDR_REG_BASE +0x513ba*4+0x02000000,0x9680); +reg_write( DDR_REG_BASE +0x513bb*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x513bc*4+0x02000000,0x966); +reg_write( DDR_REG_BASE +0x513bd*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x513be*4+0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x513bf*4+0x02000000,0x12c4); +reg_write( DDR_REG_BASE +0x513c0*4+0x02000000,0xd888); +reg_write( DDR_REG_BASE +0x513c1*4+0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x513c2*4+0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x513c3*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x513c4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x513c5*4+0x02000000,0x6000); +reg_write( DDR_REG_BASE +0x513c6*4+0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x513c7*4+0x02000000,0x12c4); +reg_write( DDR_REG_BASE +0x513c8*4+0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x513c9*4+0x02000000,0x1784); +reg_write( DDR_REG_BASE +0x513ca*4+0x02000000,0x1d72); +reg_write( DDR_REG_BASE +0x513cb*4+0x02000000,0x939c); +reg_write( DDR_REG_BASE +0x513cc*4+0x02000000,0x1dd0); +reg_write( DDR_REG_BASE +0x513cd*4+0x02000000,0x9384); +reg_write( DDR_REG_BASE +0x513ce*4+0x02000000,0x1d72); +reg_write( DDR_REG_BASE +0x513cf*4+0x02000000,0x90dd); +reg_write( DDR_REG_BASE +0x513d0*4+0x02000000,0x8e6); +reg_write( DDR_REG_BASE +0x513d1*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x513d2*4+0x02000000,0x1dd0); +reg_write( DDR_REG_BASE +0x513d3*4+0x02000000,0x9784); +reg_write( DDR_REG_BASE +0x513d4*4+0x02000000,0x1d72); +reg_write( DDR_REG_BASE +0x513d5*4+0x02000000,0x939c); +reg_write( DDR_REG_BASE +0x513d6*4+0x02000000,0x1d72); +reg_write( DDR_REG_BASE +0x513d7*4+0x02000000,0x979c); +reg_write( DDR_REG_BASE +0x513d8*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x513d9*4+0x02000000,0x92e); +reg_write( DDR_REG_BASE +0x513da*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x513db*4+0x02000000,0xd920); +reg_write( DDR_REG_BASE +0x513dc*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x513dd*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x513de*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x513df*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x513e0*4+0x02000000,0x8c6); +reg_write( DDR_REG_BASE +0x513e1*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x513e2*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x513e3*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x513e4*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x513e5*4+0x02000000,0x8be); +reg_write( DDR_REG_BASE +0x513e6*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x513e7*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x513e8*4+0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x513e9*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x513ea*4+0x02000000,0x8b2); +reg_write( DDR_REG_BASE +0x513eb*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x513ec*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x513ed*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x513ee*4+0x02000000,0x1d0a); +reg_write( DDR_REG_BASE +0x513ef*4+0x02000000,0x909d); +reg_write( DDR_REG_BASE +0x513f0*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x513f1*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x513f2*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x513f3*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x513f4*4+0x02000000,0x2088); +reg_write( DDR_REG_BASE +0x513f5*4+0x02000000,0x901); +reg_write( DDR_REG_BASE +0x513f6*4+0x02000000,0x2089); +reg_write( DDR_REG_BASE +0x513f7*4+0x02000000,0x906); +reg_write( DDR_REG_BASE +0x513f8*4+0x02000000,0x2080); +reg_write( DDR_REG_BASE +0x513f9*4+0x02000000,0x78e); +reg_write( DDR_REG_BASE +0x513fa*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x513fb*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x513fc*4+0x02000000,0x9); +reg_write( DDR_REG_BASE +0x513fd*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x513fe*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x513ff*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51400*4+0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x51401*4+0x02000000,0x8f4); +reg_write( DDR_REG_BASE +0x51402*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x51403*4+0x02000000,0xb97e); +reg_write( DDR_REG_BASE +0x51404*4+0x02000000,0xb986); +reg_write( DDR_REG_BASE +0x51405*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x51406*4+0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x51407*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51408*4+0x02000000,0xc3e6); +reg_write( DDR_REG_BASE +0x51409*4+0x02000000,0xc1aa); +reg_write( DDR_REG_BASE +0x5140a*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x5140b*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5140c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5140d*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x5140e*4+0x02000000,0xa8cd); +reg_write( DDR_REG_BASE +0x5140f*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51410*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51411*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51412*4+0x02000000,0xa8cc); +reg_write( DDR_REG_BASE +0x51413*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51414*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51415*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51416*4+0x02000000,0xa8cb); +reg_write( DDR_REG_BASE +0x51417*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51418*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51419*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x5141a*4+0x02000000,0xa8ca); +reg_write( DDR_REG_BASE +0x5141b*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5141c*4+0x02000000,0x89); +reg_write( DDR_REG_BASE +0x5141d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5141e*4+0x02000000,0xe82); +reg_write( DDR_REG_BASE +0x5141f*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51420*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51421*4+0x02000000,0x23b); +reg_write( DDR_REG_BASE +0x51422*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51423*4+0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x51424*4+0x02000000,0x17c1); +reg_write( DDR_REG_BASE +0x51425*4+0x02000000,0xe906); +reg_write( DDR_REG_BASE +0x51426*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x51427*4+0x02000000,0x901); +reg_write( DDR_REG_BASE +0x51428*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x51429*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5142a*4+0x02000000,0x1be4); +reg_write( DDR_REG_BASE +0x5142b*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x5142c*4+0x02000000,0x211); +reg_write( DDR_REG_BASE +0x5142d*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5142e*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5142f*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51430*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51431*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51432*4+0x02000000,0x1b); +reg_write( DDR_REG_BASE +0x51433*4+0x02000000,0x81f); +reg_write( DDR_REG_BASE +0x51434*4+0x02000000,0x5e); +reg_write( DDR_REG_BASE +0x51435*4+0x02000000,0xea07); +reg_write( DDR_REG_BASE +0x51436*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51437*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51438*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51439*4+0x02000000,0x7d); +reg_write( DDR_REG_BASE +0x5143a*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x5143b*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5143c*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5143d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5143e*4+0x02000000,0x4a); +reg_write( DDR_REG_BASE +0x5143f*4+0x02000000,0x7610); +reg_write( DDR_REG_BASE +0x51440*4+0x02000000,0xf4f3); +reg_write( DDR_REG_BASE +0x51441*4+0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x51442*4+0x02000000,0x1bf0); +reg_write( DDR_REG_BASE +0x51443*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x51444*4+0x02000000,0x13f0); +reg_write( DDR_REG_BASE +0x51445*4+0x02000000,0xb001); +reg_write( DDR_REG_BASE +0x51446*4+0x02000000,0xc62); +reg_write( DDR_REG_BASE +0x51447*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x51448*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x51449*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x5144a*4+0x02000000,0xea0b); +reg_write( DDR_REG_BASE +0x5144b*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5144c*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x5144d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5144e*4+0x02000000,0x58); +reg_write( DDR_REG_BASE +0x5144f*4+0x02000000,0x13e4); +reg_write( DDR_REG_BASE +0x51450*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x51451*4+0x02000000,0x782b); +reg_write( DDR_REG_BASE +0x51452*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51453*4+0x02000000,0xf40c); +reg_write( DDR_REG_BASE +0x51454*4+0x02000000,0xf0df); +reg_write( DDR_REG_BASE +0x51455*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51456*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51457*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51458*4+0x02000000,0x25); +reg_write( DDR_REG_BASE +0x51459*4+0x02000000,0x13e4); +reg_write( DDR_REG_BASE +0x5145a*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x5145b*4+0x02000000,0x782b); +reg_write( DDR_REG_BASE +0x5145c*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5145d*4+0x02000000,0xf2d7); +reg_write( DDR_REG_BASE +0x5145e*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5145f*4+0x02000000,0xbac4); +reg_write( DDR_REG_BASE +0x51460*4+0x02000000,0xea05); +reg_write( DDR_REG_BASE +0x51461*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x51462*4+0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x51463*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x51464*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51465*4+0x02000000,0xa4e); +reg_write( DDR_REG_BASE +0x51466*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51467*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51468*4+0x02000000,0x13e4); +reg_write( DDR_REG_BASE +0x51469*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x5146a*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x5146b*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5146c*4+0x02000000,0x7043); +reg_write( DDR_REG_BASE +0x5146d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5146e*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x5146f*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51470*4+0x02000000,0xb06); +reg_write( DDR_REG_BASE +0x51471*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51472*4+0x02000000,0x1be8); +reg_write( DDR_REG_BASE +0x51473*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x51474*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51475*4+0x02000000,0xd854); +reg_write( DDR_REG_BASE +0x51476*4+0x02000000,0x1be0); +reg_write( DDR_REG_BASE +0x51477*4+0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x51478*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51479*4+0x02000000,0x7042); +reg_write( DDR_REG_BASE +0x5147a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5147b*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x5147c*4+0x02000000,0x1bfc); +reg_write( DDR_REG_BASE +0x5147d*4+0x02000000,0xb700); +reg_write( DDR_REG_BASE +0x5147e*4+0x02000000,0x2402); +reg_write( DDR_REG_BASE +0x5147f*4+0x02000000,0x301c); +reg_write( DDR_REG_BASE +0x51480*4+0x02000000,0xc082); +reg_write( DDR_REG_BASE +0x51481*4+0x02000000,0xf9a); +reg_write( DDR_REG_BASE +0x51482*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51483*4+0x02000000,0x1bec); +reg_write( DDR_REG_BASE +0x51484*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x51485*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x51486*4+0x02000000,0x1801); +reg_write( DDR_REG_BASE +0x51487*4+0x02000000,0x13); +reg_write( DDR_REG_BASE +0x51488*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x51489*4+0x02000000,0xe1d0); +reg_write( DDR_REG_BASE +0x5148a*4+0x02000000,0xf7fc); +reg_write( DDR_REG_BASE +0x5148b*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x5148c*4+0x02000000,0xf041); +reg_write( DDR_REG_BASE +0x5148d*4+0x02000000,0xeea); +reg_write( DDR_REG_BASE +0x5148e*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5148f*4+0x02000000,0x78af); +reg_write( DDR_REG_BASE +0x51490*4+0x02000000,0x1bf4); +reg_write( DDR_REG_BASE +0x51491*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x51492*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51493*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51494*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51495*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51496*4+0x02000000,0x13e8); +reg_write( DDR_REG_BASE +0x51497*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x51498*4+0x02000000,0x13f4); +reg_write( DDR_REG_BASE +0x51499*4+0x02000000,0xb002); +reg_write( DDR_REG_BASE +0x5149a*4+0x02000000,0xe56); +reg_write( DDR_REG_BASE +0x5149b*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5149c*4+0x02000000,0x1bf8); +reg_write( DDR_REG_BASE +0x5149d*4+0x02000000,0xb001); +reg_write( DDR_REG_BASE +0x5149e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5149f*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x514a0*4+0x02000000,0xd090); +reg_write( DDR_REG_BASE +0x514a1*4+0x02000000,0xf9e); +reg_write( DDR_REG_BASE +0x514a2*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x514a3*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x514a4*4+0x02000000,0x84a); +reg_write( DDR_REG_BASE +0x514a5*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x514a6*4+0x02000000,0x13e8); +reg_write( DDR_REG_BASE +0x514a7*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514a8*4+0x02000000,0x13f0); +reg_write( DDR_REG_BASE +0x514a9*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514aa*4+0x02000000,0x2342); +reg_write( DDR_REG_BASE +0x514ab*4+0x02000000,0x3201); +reg_write( DDR_REG_BASE +0x514ac*4+0x02000000,0x85e); +reg_write( DDR_REG_BASE +0x514ad*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x514ae*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x514af*4+0x02000000,0x13f8); +reg_write( DDR_REG_BASE +0x514b0*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514b1*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x514b2*4+0x02000000,0x8a); +reg_write( DDR_REG_BASE +0x514b3*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x514b4*4+0x02000000,0x43c1); +reg_write( DDR_REG_BASE +0x514b5*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x514b6*4+0x02000000,0xf8f); +reg_write( DDR_REG_BASE +0x514b7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x514b8*4+0x02000000,0x3f00); +reg_write( DDR_REG_BASE +0x514b9*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x514ba*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x514bb*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x514bc*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x514bd*4+0x02000000,0x1bf8); +reg_write( DDR_REG_BASE +0x514be*4+0x02000000,0xb3c0); +reg_write( DDR_REG_BASE +0x514bf*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x514c0*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x514c1*4+0x02000000,0x13f4); +reg_write( DDR_REG_BASE +0x514c2*4+0x02000000,0xb002); +reg_write( DDR_REG_BASE +0x514c3*4+0x02000000,0xd3a); +reg_write( DDR_REG_BASE +0x514c4*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x514c5*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x514c6*4+0x02000000,0xef06); +reg_write( DDR_REG_BASE +0x514c7*4+0x02000000,0x13ec); +reg_write( DDR_REG_BASE +0x514c8*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514c9*4+0x02000000,0x60b8); +reg_write( DDR_REG_BASE +0x514ca*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x514cb*4+0x02000000,0x43); +reg_write( DDR_REG_BASE +0x514cc*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x514cd*4+0x02000000,0xe5d0); +reg_write( DDR_REG_BASE +0x514ce*4+0x02000000,0x77e); +reg_write( DDR_REG_BASE +0x514cf*4+0x02000000,0xffee); +reg_write( DDR_REG_BASE +0x514d0*4+0x02000000,0x774c); +reg_write( DDR_REG_BASE +0x514d1*4+0x02000000,0x4548); +reg_write( DDR_REG_BASE +0x514d2*4+0x02000000,0x4748); +reg_write( DDR_REG_BASE +0x514d3*4+0x02000000,0x4140); +reg_write( DDR_REG_BASE +0x514d4*4+0x02000000,0xf022); +reg_write( DDR_REG_BASE +0x514d5*4+0x02000000,0x13ec); +reg_write( DDR_REG_BASE +0x514d6*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514d7*4+0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x514d8*4+0x02000000,0x483); +reg_write( DDR_REG_BASE +0x514d9*4+0x02000000,0x1bec); +reg_write( DDR_REG_BASE +0x514da*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514db*4+0x02000000,0xf212); +reg_write( DDR_REG_BASE +0x514dc*4+0x02000000,0x13e0); +reg_write( DDR_REG_BASE +0x514dd*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514de*4+0x02000000,0xe0d0); +reg_write( DDR_REG_BASE +0x514df*4+0x02000000,0xf203); +reg_write( DDR_REG_BASE +0x514e0*4+0x02000000,0xeb11); +reg_write( DDR_REG_BASE +0x514e1*4+0x02000000,0x13e0); +reg_write( DDR_REG_BASE +0x514e2*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514e3*4+0x02000000,0x4fb4); +reg_write( DDR_REG_BASE +0x514e4*4+0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x514e5*4+0x02000000,0x4833); +reg_write( DDR_REG_BASE +0x514e6*4+0x02000000,0x7391); +reg_write( DDR_REG_BASE +0x514e7*4+0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x514e8*4+0x02000000,0x1009); +reg_write( DDR_REG_BASE +0x514e9*4+0x02000000,0x25ca); +reg_write( DDR_REG_BASE +0x514ea*4+0x02000000,0x1049); +reg_write( DDR_REG_BASE +0x514eb*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x514ec*4+0x02000000,0xeb03); +reg_write( DDR_REG_BASE +0x514ed*4+0x02000000,0x772c); +reg_write( DDR_REG_BASE +0x514ee*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x514ef*4+0x02000000,0x13e0); +reg_write( DDR_REG_BASE +0x514f0*4+0x02000000,0xb001); +reg_write( DDR_REG_BASE +0x514f1*4+0x02000000,0x13e0); +reg_write( DDR_REG_BASE +0x514f2*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514f3*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x514f4*4+0x02000000,0x1be0); +reg_write( DDR_REG_BASE +0x514f5*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514f6*4+0x02000000,0x13e0); +reg_write( DDR_REG_BASE +0x514f7*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514f8*4+0x02000000,0xe0d1); +reg_write( DDR_REG_BASE +0x514f9*4+0x02000000,0x7ba); +reg_write( DDR_REG_BASE +0x514fa*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x514fb*4+0x02000000,0x7734); +reg_write( DDR_REG_BASE +0x514fc*4+0x02000000,0x2139); +reg_write( DDR_REG_BASE +0x514fd*4+0x02000000,0x83); +reg_write( DDR_REG_BASE +0x514fe*4+0x02000000,0x2538); +reg_write( DDR_REG_BASE +0x514ff*4+0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x51500*4+0x02000000,0x786b); +reg_write( DDR_REG_BASE +0x51501*4+0x02000000,0xd850); +reg_write( DDR_REG_BASE +0x51502*4+0x02000000,0x753c); +reg_write( DDR_REG_BASE +0x51503*4+0x02000000,0x771c); +reg_write( DDR_REG_BASE +0x51504*4+0x02000000,0x77b5); +reg_write( DDR_REG_BASE +0x51505*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51506*4+0x02000000,0xf204); +reg_write( DDR_REG_BASE +0x51507*4+0x02000000,0x4fb0); +reg_write( DDR_REG_BASE +0x51508*4+0x02000000,0x207f); +reg_write( DDR_REG_BASE +0x51509*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5150a*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5150b*4+0x02000000,0x7083); +reg_write( DDR_REG_BASE +0x5150c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5150d*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x5150e*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5150f*4+0x02000000,0x8c); +reg_write( DDR_REG_BASE +0x51510*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x51511*4+0x02000000,0xf32); +reg_write( DDR_REG_BASE +0x51512*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51513*4+0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x51514*4+0x02000000,0x67b8); +reg_write( DDR_REG_BASE +0x51515*4+0x02000000,0x2844); +reg_write( DDR_REG_BASE +0x51516*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x51517*4+0x02000000,0xdd6); +reg_write( DDR_REG_BASE +0x51518*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51519*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x5151a*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5151b*4+0x02000000,0x7043); +reg_write( DDR_REG_BASE +0x5151c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5151d*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x5151e*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5151f*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51520*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51521*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51522*4+0x02000000,0x2614); +reg_write( DDR_REG_BASE +0x51523*4+0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x51524*4+0x02000000,0x2100); +reg_write( DDR_REG_BASE +0x51525*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51526*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51527*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51528*4+0x02000000,0xa90a); +reg_write( DDR_REG_BASE +0x51529*4+0x02000000,0xcda); +reg_write( DDR_REG_BASE +0x5152a*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x5152b*4+0x02000000,0x13e8); +reg_write( DDR_REG_BASE +0x5152c*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x5152d*4+0x02000000,0x13fc); +reg_write( DDR_REG_BASE +0x5152e*4+0x02000000,0xb01c); +reg_write( DDR_REG_BASE +0x5152f*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51530*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51531*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51532*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51533*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x51534*4+0x02000000,0x7a2f); +reg_write( DDR_REG_BASE +0x51535*4+0x02000000,0x7154); +reg_write( DDR_REG_BASE +0x51536*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51537*4+0x02000000,0x7042); +reg_write( DDR_REG_BASE +0x51538*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51539*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x5153a*4+0x02000000,0x5ea); +reg_write( DDR_REG_BASE +0x5153b*4+0x02000000,0xffce); +reg_write( DDR_REG_BASE +0x5153c*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x5153d*4+0x02000000,0x72d5); +reg_write( DDR_REG_BASE +0x5153e*4+0x02000000,0x5ca); +reg_write( DDR_REG_BASE +0x5153f*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x51540*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51541*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51542*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51543*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51544*4+0x02000000,0x180e); +reg_write( DDR_REG_BASE +0x51545*4+0x02000000,0x43); +reg_write( DDR_REG_BASE +0x51546*4+0x02000000,0xc7c6); +reg_write( DDR_REG_BASE +0x51547*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51548*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51549*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5154a*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5154b*4+0x02000000,0xc1bd); +reg_write( DDR_REG_BASE +0x5154c*4+0x02000000,0xd925); +reg_write( DDR_REG_BASE +0x5154d*4+0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x5154e*4+0x02000000,0x8900); +reg_write( DDR_REG_BASE +0x5154f*4+0x02000000,0x1c3a); +reg_write( DDR_REG_BASE +0x51550*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x51551*4+0x02000000,0x1133); +reg_write( DDR_REG_BASE +0x51552*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x51553*4+0x02000000,0x1c3b); +reg_write( DDR_REG_BASE +0x51554*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x51555*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51556*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51557*4+0x02000000,0x7c8); +reg_write( DDR_REG_BASE +0x51558*4+0x02000000,0x8827); +reg_write( DDR_REG_BASE +0x51559*4+0x02000000,0x88a0); +reg_write( DDR_REG_BASE +0x5155a*4+0x02000000,0xc16e); +reg_write( DDR_REG_BASE +0x5155b*4+0x02000000,0x8829); +reg_write( DDR_REG_BASE +0x5155c*4+0x02000000,0x1c39); +reg_write( DDR_REG_BASE +0x5155d*4+0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x5155e*4+0x02000000,0x8828); +reg_write( DDR_REG_BASE +0x5155f*4+0x02000000,0x1c36); +reg_write( DDR_REG_BASE +0x51560*4+0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x51561*4+0x02000000,0x882a); +reg_write( DDR_REG_BASE +0x51562*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51563*4+0x02000000,0x1c37); +reg_write( DDR_REG_BASE +0x51564*4+0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x51565*4+0x02000000,0xe46); +reg_write( DDR_REG_BASE +0x51566*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51567*4+0x02000000,0xc193); +reg_write( DDR_REG_BASE +0x51568*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51569*4+0x02000000,0xc146); +reg_write( DDR_REG_BASE +0x5156a*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x5156b*4+0x02000000,0x7a34); +reg_write( DDR_REG_BASE +0x5156c*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5156d*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x5156e*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x5156f*4+0x02000000,0x9fb); +reg_write( DDR_REG_BASE +0x51570*4+0x02000000,0x82b4); +reg_write( DDR_REG_BASE +0x51571*4+0x02000000,0xc298); +reg_write( DDR_REG_BASE +0x51572*4+0x02000000,0xd90c); +reg_write( DDR_REG_BASE +0x51573*4+0x02000000,0x2905); +reg_write( DDR_REG_BASE +0x51574*4+0x02000000,0x341); +reg_write( DDR_REG_BASE +0x51575*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x51576*4+0x02000000,0x7835); +reg_write( DDR_REG_BASE +0x51577*4+0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x51578*4+0x02000000,0x40d); +reg_write( DDR_REG_BASE +0x51579*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5157a*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5157b*4+0x02000000,0x3ff); +reg_write( DDR_REG_BASE +0x5157c*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5157d*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x5157e*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5157f*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51580*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x51581*4+0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x51582*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x51583*4+0x02000000,0xc105); +reg_write( DDR_REG_BASE +0x51584*4+0x02000000,0xea05); +reg_write( DDR_REG_BASE +0x51585*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x51586*4+0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x51587*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x51588*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51589*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x5158a*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x5158b*4+0x02000000,0x6c7); +reg_write( DDR_REG_BASE +0x5158c*4+0x02000000,0xdca); +reg_write( DDR_REG_BASE +0x5158d*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5158e*4+0x02000000,0x792f); +reg_write( DDR_REG_BASE +0x5158f*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51590*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51591*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x51592*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x51593*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x51594*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51595*4+0x02000000,0xf2f6); +reg_write( DDR_REG_BASE +0x51596*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51597*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51598*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51599*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5159a*4+0x02000000,0xb8e3); +reg_write( DDR_REG_BASE +0x5159b*4+0x02000000,0xf4f0); +reg_write( DDR_REG_BASE +0x5159c*4+0x02000000,0xab6); +reg_write( DDR_REG_BASE +0x5159d*4+0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x5159e*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x5159f*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x515a0*4+0x02000000,0xf07e); +reg_write( DDR_REG_BASE +0x515a1*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x515a2*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x515a3*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x515a4*4+0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x515a5*4+0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x515a6*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x515a7*4+0x02000000,0xb882); +reg_write( DDR_REG_BASE +0x515a8*4+0x02000000,0x815); +reg_write( DDR_REG_BASE +0x515a9*4+0x02000000,0x131); +reg_write( DDR_REG_BASE +0x515aa*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x515ab*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x515ac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x515ad*4+0x02000000,0xa00); +reg_write( DDR_REG_BASE +0x515ae*4+0x02000000,0xea2); +reg_write( DDR_REG_BASE +0x515af*4+0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x515b0*4+0x02000000,0xec2); +reg_write( DDR_REG_BASE +0x515b1*4+0x02000000,0x180); +reg_write( DDR_REG_BASE +0x515b2*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x515b3*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x515b4*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x515b5*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x515b6*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x515b7*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x515b8*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x515b9*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x515ba*4+0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x515bb*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x515bc*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x515bd*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x515be*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x515bf*4+0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x515c0*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x515c1*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x515c2*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x515c3*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x515c4*4+0x02000000,0x2045); +reg_write( DDR_REG_BASE +0x515c5*4+0x02000000,0x180); +reg_write( DDR_REG_BASE +0x515c6*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x515c7*4+0x02000000,0xf4a); +reg_write( DDR_REG_BASE +0x515c8*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x515c9*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x515ca*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x515cb*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x515cc*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x515cd*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x515ce*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x515cf*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x515d0*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x515d1*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x515d2*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x515d3*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x515d4*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x515d5*4+0x02000000,0x448); +reg_write( DDR_REG_BASE +0x515d6*4+0x02000000,0xb8c5); +reg_write( DDR_REG_BASE +0x515d7*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x515d8*4+0x02000000,0xf26); +reg_write( DDR_REG_BASE +0x515d9*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x515da*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x515db*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x515dc*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x515dd*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x515de*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x515df*4+0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x515e0*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x515e1*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x515e2*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x515e3*4+0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x515e4*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x515e5*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x515e6*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x515e7*4+0x02000000,0x2045); +reg_write( DDR_REG_BASE +0x515e8*4+0x02000000,0x580); +reg_write( DDR_REG_BASE +0x515e9*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x515ea*4+0x02000000,0xf02); +reg_write( DDR_REG_BASE +0x515eb*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x515ec*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x515ed*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x515ee*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x515ef*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x515f0*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x515f1*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x515f2*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x515f3*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x515f4*4+0x02000000,0xb8c5); +reg_write( DDR_REG_BASE +0x515f5*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x515f6*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x515f7*4+0x02000000,0xeea); +reg_write( DDR_REG_BASE +0x515f8*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x515f9*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x515fa*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x515fb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x515fc*4+0x02000000,0x2710); +reg_write( DDR_REG_BASE +0x515fd*4+0x02000000,0xd06); +reg_write( DDR_REG_BASE +0x515fe*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x515ff*4+0x02000000,0xd90a); +reg_write( DDR_REG_BASE +0x51600*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51601*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51602*4+0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x51603*4+0x02000000,0x7d0f); +reg_write( DDR_REG_BASE +0x51604*4+0x02000000,0xf8dd); +reg_write( DDR_REG_BASE +0x51605*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51606*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x51607*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x51608*4+0x02000000,0xec6); +reg_write( DDR_REG_BASE +0x51609*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5160a*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5160b*4+0x02000000,0xf8da); +reg_write( DDR_REG_BASE +0x5160c*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5160d*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5160e*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x5160f*4+0x02000000,0xeba); +reg_write( DDR_REG_BASE +0x51610*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51611*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x51612*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51613*4+0x02000000,0xb863); +reg_write( DDR_REG_BASE +0x51614*4+0x02000000,0x811); +reg_write( DDR_REG_BASE +0x51615*4+0x02000000,0x95); +reg_write( DDR_REG_BASE +0x51616*4+0x02000000,0xd9e); +reg_write( DDR_REG_BASE +0x51617*4+0x02000000,0x180); +reg_write( DDR_REG_BASE +0x51618*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51619*4+0x02000000,0xe66); +reg_write( DDR_REG_BASE +0x5161a*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5161b*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5161c*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5161d*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5161e*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5161f*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51620*4+0x02000000,0x7514); +reg_write( DDR_REG_BASE +0x51621*4+0x02000000,0x702); +reg_write( DDR_REG_BASE +0x51622*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x51623*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x51624*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51625*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51626*4+0x02000000,0xa00); +reg_write( DDR_REG_BASE +0x51627*4+0x02000000,0xdb2); +reg_write( DDR_REG_BASE +0x51628*4+0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x51629*4+0x02000000,0xdd2); +reg_write( DDR_REG_BASE +0x5162a*4+0x02000000,0x180); +reg_write( DDR_REG_BASE +0x5162b*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x5162c*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5162d*4+0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x5162e*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5162f*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51630*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51631*4+0x02000000,0xdb18); +reg_write( DDR_REG_BASE +0x51632*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x51633*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x51634*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x51635*4+0x02000000,0xe6e); +reg_write( DDR_REG_BASE +0x51636*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51637*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x51638*4+0x02000000,0x8b2); +reg_write( DDR_REG_BASE +0x51639*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5163a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5163b*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x5163c*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5163d*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5163e*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5163f*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x51640*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x51641*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x51642*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51643*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x51644*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51645*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x51646*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x51647*4+0x02000000,0xe4a); +reg_write( DDR_REG_BASE +0x51648*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51649*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5164a*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x5164b*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5164c*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5164d*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5164e*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5164f*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x51650*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51651*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x51652*4+0x02000000,0xe32); +reg_write( DDR_REG_BASE +0x51653*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51654*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x51655*4+0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x51656*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x51657*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51658*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51659*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5165a*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5165b*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5165c*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x5165d*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5165e*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5165f*4+0x02000000,0xe1a); +reg_write( DDR_REG_BASE +0x51660*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51661*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x51662*4+0x02000000,0x3481); +reg_write( DDR_REG_BASE +0x51663*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x51664*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51665*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51666*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x51667*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51668*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x51669*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5166a*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x5166b*4+0x02000000,0xe02); +reg_write( DDR_REG_BASE +0x5166c*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5166d*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5166e*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x5166f*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51670*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51671*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x51672*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51673*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x51674*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51675*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x51676*4+0x02000000,0xdea); +reg_write( DDR_REG_BASE +0x51677*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51678*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51679*4+0x02000000,0x816); +reg_write( DDR_REG_BASE +0x5167a*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5167b*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5167c*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x5167d*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5167e*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5167f*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x51680*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51681*4+0x02000000,0xdb18); +reg_write( DDR_REG_BASE +0x51682*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51683*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x51684*4+0x02000000,0xdce); +reg_write( DDR_REG_BASE +0x51685*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51686*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51687*4+0x02000000,0xcbe); +reg_write( DDR_REG_BASE +0x51688*4+0x02000000,0x180); +reg_write( DDR_REG_BASE +0x51689*4+0x02000000,0xf07f); +reg_write( DDR_REG_BASE +0x5168a*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5168b*4+0x02000000,0xcea); +reg_write( DDR_REG_BASE +0x5168c*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5168d*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x5168e*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x5168f*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x51690*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x51691*4+0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x51692*4+0x02000000,0x101); +reg_write( DDR_REG_BASE +0x51693*4+0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x51694*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51695*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51696*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x51697*4+0x02000000,0x7e0f); +reg_write( DDR_REG_BASE +0x51698*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x51699*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5169a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5169b*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5169c*4+0x02000000,0xfae); +reg_write( DDR_REG_BASE +0x5169d*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5169e*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x5169f*4+0x02000000,0xd828); +reg_write( DDR_REG_BASE +0x516a0*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x516a1*4+0x02000000,0xf88c); +reg_write( DDR_REG_BASE +0x516a2*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x516a3*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x516a4*4+0x02000000,0xf9e); +reg_write( DDR_REG_BASE +0x516a5*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516a6*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x516a7*4+0x02000000,0xf889); +reg_write( DDR_REG_BASE +0x516a8*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x516a9*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x516aa*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x516ab*4+0x02000000,0x33c1); +reg_write( DDR_REG_BASE +0x516ac*4+0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x516ad*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516ae*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x516af*4+0x02000000,0xf885); +reg_write( DDR_REG_BASE +0x516b0*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x516b1*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x516b2*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x516b3*4+0x02000000,0x3501); +reg_write( DDR_REG_BASE +0x516b4*4+0x02000000,0xf7e); +reg_write( DDR_REG_BASE +0x516b5*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516b6*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x516b7*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x516b8*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x516b9*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x516ba*4+0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x516bb*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x516bc*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x516bd*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x516be*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x516bf*4+0x02000000,0xf6a); +reg_write( DDR_REG_BASE +0x516c0*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516c1*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x516c2*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x516c3*4+0x02000000,0xd12); +reg_write( DDR_REG_BASE +0x516c4*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516c5*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x516c6*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x516c7*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x516c8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x516c9*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x516ca*4+0x02000000,0xdae0); +reg_write( DDR_REG_BASE +0x516cb*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x516cc*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x516cd*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x516ce*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x516cf*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x516d0*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x516d1*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x516d2*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x516d3*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x516d4*4+0x02000000,0x7204); +reg_write( DDR_REG_BASE +0x516d5*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x516d6*4+0x02000000,0xb340); +reg_write( DDR_REG_BASE +0x516d7*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x516d8*4+0x02000000,0x485); +reg_write( DDR_REG_BASE +0x516d9*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x516da*4+0x02000000,0xc4a); +reg_write( DDR_REG_BASE +0x516db*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516dc*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x516dd*4+0x02000000,0xf6a); +reg_write( DDR_REG_BASE +0x516de*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516df*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x516e0*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x516e1*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x516e2*4+0x02000000,0xb990); +reg_write( DDR_REG_BASE +0x516e3*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x516e4*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x516e5*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x516e6*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x516e7*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x516e8*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x516e9*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x516ea*4+0x02000000,0xd02); +reg_write( DDR_REG_BASE +0x516eb*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516ec*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x516ed*4+0x02000000,0xd90c); +reg_write( DDR_REG_BASE +0x516ee*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x516ef*4+0x02000000,0xb98d); +reg_write( DDR_REG_BASE +0x516f0*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x516f1*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x516f2*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x516f3*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x516f4*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x516f5*4+0x02000000,0xcee); +reg_write( DDR_REG_BASE +0x516f6*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516f7*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x516f8*4+0x02000000,0xf16); +reg_write( DDR_REG_BASE +0x516f9*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516fa*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x516fb*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x516fc*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x516fd*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x516fe*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x516ff*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51700*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51701*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51702*4+0x02000000,0xcd2); +reg_write( DDR_REG_BASE +0x51703*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51704*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51705*4+0x02000000,0xd850); +reg_write( DDR_REG_BASE +0x51706*4+0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x51707*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51708*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x51709*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5170a*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5170b*4+0x02000000,0xe048); +reg_write( DDR_REG_BASE +0x5170c*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x5170d*4+0x02000000,0x1804); +reg_write( DDR_REG_BASE +0x5170e*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x5170f*4+0x02000000,0x2440); +reg_write( DDR_REG_BASE +0x51710*4+0x02000000,0x3e80); +reg_write( DDR_REG_BASE +0x51711*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x51712*4+0x02000000,0x6c1); +reg_write( DDR_REG_BASE +0x51713*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x51714*4+0x02000000,0x782b); +reg_write( DDR_REG_BASE +0x51715*4+0x02000000,0xf264); +reg_write( DDR_REG_BASE +0x51716*4+0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x51717*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51718*4+0x02000000,0xc66); +reg_write( DDR_REG_BASE +0x51719*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5171a*4+0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x5171b*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5171c*4+0x02000000,0xaa6); +reg_write( DDR_REG_BASE +0x5171d*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5171e*4+0x02000000,0xd91e); +reg_write( DDR_REG_BASE +0x5171f*4+0x02000000,0x2440); +reg_write( DDR_REG_BASE +0x51720*4+0x02000000,0x3d80); +reg_write( DDR_REG_BASE +0x51721*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x51722*4+0x02000000,0x6cb); +reg_write( DDR_REG_BASE +0x51723*4+0x02000000,0xc08e); +reg_write( DDR_REG_BASE +0x51724*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x51725*4+0x02000000,0x6cd); +reg_write( DDR_REG_BASE +0x51726*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x51727*4+0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x51728*4+0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x51729*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5172a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5172b*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x5172c*4+0x02000000,0x7a34); +reg_write( DDR_REG_BASE +0x5172d*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x5172e*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5172f*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51730*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51731*4+0x02000000,0x54); +reg_write( DDR_REG_BASE +0x51732*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51733*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51734*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x51735*4+0x02000000,0xbe9); +reg_write( DDR_REG_BASE +0x51736*4+0x02000000,0x9065); +reg_write( DDR_REG_BASE +0x51737*4+0x02000000,0xc28f); +reg_write( DDR_REG_BASE +0x51738*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51739*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5173a*4+0x02000000,0xf034); +reg_write( DDR_REG_BASE +0x5173b*4+0x02000000,0x23f4); +reg_write( DDR_REG_BASE +0x5173c*4+0x02000000,0x34c); +reg_write( DDR_REG_BASE +0x5173d*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x5173e*4+0x02000000,0x7bb4); +reg_write( DDR_REG_BASE +0x5173f*4+0x02000000,0xbc80); +reg_write( DDR_REG_BASE +0x51740*4+0x02000000,0xb380); +reg_write( DDR_REG_BASE +0x51741*4+0x02000000,0xe886); +reg_write( DDR_REG_BASE +0x51742*4+0x02000000,0xc08f); +reg_write( DDR_REG_BASE +0x51743*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x51744*4+0x02000000,0x340); +reg_write( DDR_REG_BASE +0x51745*4+0x02000000,0xe80f); +reg_write( DDR_REG_BASE +0x51746*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x51747*4+0x02000000,0x340e); +reg_write( DDR_REG_BASE +0x51748*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51749*4+0x02000000,0x7e16); +reg_write( DDR_REG_BASE +0x5174a*4+0x02000000,0x6638); +reg_write( DDR_REG_BASE +0x5174b*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x5174c*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5174d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5174e*4+0x02000000,0x7a8); +reg_write( DDR_REG_BASE +0x5174f*4+0x02000000,0xa8a0); +reg_write( DDR_REG_BASE +0x51750*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x51751*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x51752*4+0x02000000,0xe817); +reg_write( DDR_REG_BASE +0x51753*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x51754*4+0x02000000,0x340e); +reg_write( DDR_REG_BASE +0x51755*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51756*4+0x02000000,0x7e16); +reg_write( DDR_REG_BASE +0x51757*4+0x02000000,0x6658); +reg_write( DDR_REG_BASE +0x51758*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x51759*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5175a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5175b*4+0x02000000,0x788); +reg_write( DDR_REG_BASE +0x5175c*4+0x02000000,0xa8a0); +reg_write( DDR_REG_BASE +0x5175d*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x5175e*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x5175f*4+0x02000000,0xe88f); +reg_write( DDR_REG_BASE +0x51760*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51761*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x51762*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51763*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51764*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51765*4+0x02000000,0x7404); +reg_write( DDR_REG_BASE +0x51766*4+0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x51767*4+0x02000000,0xb380); +reg_write( DDR_REG_BASE +0x51768*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x51769*4+0x02000000,0xc08f); +reg_write( DDR_REG_BASE +0x5176a*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x5176b*4+0x02000000,0x340); +reg_write( DDR_REG_BASE +0x5176c*4+0x02000000,0xe867); +reg_write( DDR_REG_BASE +0x5176d*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x5176e*4+0x02000000,0xb9b); +reg_write( DDR_REG_BASE +0x5176f*4+0x02000000,0x9365); +reg_write( DDR_REG_BASE +0x51770*4+0x02000000,0xc398); +reg_write( DDR_REG_BASE +0x51771*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51772*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51773*4+0x02000000,0x9c4); +reg_write( DDR_REG_BASE +0x51774*4+0x02000000,0xb96); +reg_write( DDR_REG_BASE +0x51775*4+0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x51776*4+0x02000000,0xb06); +reg_write( DDR_REG_BASE +0x51777*4+0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x51778*4+0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x51779*4+0x02000000,0x7277); +reg_write( DDR_REG_BASE +0x5177a*4+0x02000000,0x408); +reg_write( DDR_REG_BASE +0x5177b*4+0x02000000,0xffc5); +reg_write( DDR_REG_BASE +0x5177c*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5177d*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5177e*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x5177f*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51780*4+0x02000000,0x7114); +reg_write( DDR_REG_BASE +0x51781*4+0x02000000,0x3f6); +reg_write( DDR_REG_BASE +0x51782*4+0x02000000,0xffce); +reg_write( DDR_REG_BASE +0x51783*4+0x02000000,0xf01a); +reg_write( DDR_REG_BASE +0x51784*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x51785*4+0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x51786*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51787*4+0x02000000,0xe913); +reg_write( DDR_REG_BASE +0x51788*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51789*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5178a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5178b*4+0x02000000,0x19); +reg_write( DDR_REG_BASE +0x5178c*4+0x02000000,0xe88d); +reg_write( DDR_REG_BASE +0x5178d*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x5178e*4+0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x5178f*4+0x02000000,0x301); +reg_write( DDR_REG_BASE +0x51790*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x51791*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51792*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51793*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x51794*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51795*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51796*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51797*4+0x02000000,0x154); +reg_write( DDR_REG_BASE +0x51798*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51799*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x5179a*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5179b*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x5179c*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x5179d*4+0x02000000,0x8d1); +reg_write( DDR_REG_BASE +0x5179e*4+0x02000000,0x82b4); +reg_write( DDR_REG_BASE +0x5179f*4+0x02000000,0xc198); +reg_write( DDR_REG_BASE +0x517a0*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x517a1*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x517a2*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x517a3*4+0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x517a4*4+0x02000000,0xe808); +reg_write( DDR_REG_BASE +0x517a5*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x517a6*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x517a7*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x517a8*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x517a9*4+0x02000000,0xb8e3); +reg_write( DDR_REG_BASE +0x517aa*4+0x02000000,0x89c); +reg_write( DDR_REG_BASE +0x517ab*4+0x02000000,0xff41); +reg_write( DDR_REG_BASE +0x517ac*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x517ad*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x517ae*4+0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x517af*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x517b0*4+0x02000000,0xe048); +reg_write( DDR_REG_BASE +0x517b1*4+0x02000000,0x9ae); +reg_write( DDR_REG_BASE +0x517b2*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x517b3*4+0x02000000,0xc193); +reg_write( DDR_REG_BASE +0x517b4*4+0x02000000,0xc0bd); +reg_write( DDR_REG_BASE +0x517b5*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x517b6*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x517b7*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x517b8*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x517b9*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x517ba*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x517bb*4+0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x517bc*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x517bd*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x517be*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x517bf*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x517c0*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x517c1*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x517c2*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x517c3*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x517c4*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x517c5*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x517c6*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x517c7*4+0x02000000,0xc1a3); +reg_write( DDR_REG_BASE +0x517c8*4+0x02000000,0x4648); +reg_write( DDR_REG_BASE +0x517c9*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x517ca*4+0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x517cb*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x517cc*4+0x02000000,0xf031); +reg_write( DDR_REG_BASE +0x517cd*4+0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x517ce*4+0x02000000,0x3401); +reg_write( DDR_REG_BASE +0x517cf*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x517d0*4+0x02000000,0x7956); +reg_write( DDR_REG_BASE +0x517d1*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x517d2*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x517d3*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x517d4*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x517d5*4+0x02000000,0x7a8); +reg_write( DDR_REG_BASE +0x517d6*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x517d7*4+0x02000000,0xafe); +reg_write( DDR_REG_BASE +0x517d8*4+0x02000000,0x1a0); +reg_write( DDR_REG_BASE +0x517d9*4+0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x517da*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x517db*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x517dc*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x517dd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x517de*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x517df*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x517e0*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x517e1*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x517e2*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x517e3*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x517e4*4+0x02000000,0x254f); +reg_write( DDR_REG_BASE +0x517e5*4+0x02000000,0x1280); +reg_write( DDR_REG_BASE +0x517e6*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x517e7*4+0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x517e8*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x517e9*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x517ea*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x517eb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x517ec*4+0x02000000,0xbb8); +reg_write( DDR_REG_BASE +0x517ed*4+0x02000000,0x906); +reg_write( DDR_REG_BASE +0x517ee*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x517ef*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x517f0*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x517f1*4+0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x517f2*4+0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x517f3*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x517f4*4+0x02000000,0xb140); +reg_write( DDR_REG_BASE +0x517f5*4+0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x517f6*4+0x02000000,0xb140); +reg_write( DDR_REG_BASE +0x517f7*4+0x02000000,0x8f9); +reg_write( DDR_REG_BASE +0x517f8*4+0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x517f9*4+0x02000000,0x254f); +reg_write( DDR_REG_BASE +0x517fa*4+0x02000000,0x1242); +reg_write( DDR_REG_BASE +0x517fb*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x517fc*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x517fd*4+0x02000000,0x2779); +reg_write( DDR_REG_BASE +0x517fe*4+0x02000000,0x1042); +reg_write( DDR_REG_BASE +0x517ff*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x51800*4+0x02000000,0x2214); +reg_write( DDR_REG_BASE +0x51801*4+0x02000000,0x6c0); +reg_write( DDR_REG_BASE +0x51802*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x51803*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51804*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51805*4+0x02000000,0x784); +reg_write( DDR_REG_BASE +0x51806*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51807*4+0x02000000,0x88f); +reg_write( DDR_REG_BASE +0x51808*4+0x02000000,0x8044); +reg_write( DDR_REG_BASE +0x51809*4+0x02000000,0xc0a3); +reg_write( DDR_REG_BASE +0x5180a*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x5180b*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x5180c*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5180d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5180e*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5180f*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51810*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51811*4+0x02000000,0xc1a2); +reg_write( DDR_REG_BASE +0x51812*4+0x02000000,0x4728); +reg_write( DDR_REG_BASE +0x51813*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x51814*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x51815*4+0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x51816*4+0x02000000,0xc341); +reg_write( DDR_REG_BASE +0x51817*4+0x02000000,0xdbe); +reg_write( DDR_REG_BASE +0x51818*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x51819*4+0x02000000,0x4358); +reg_write( DDR_REG_BASE +0x5181a*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5181b*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x5181c*4+0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x5181d*4+0x02000000,0x17c0); +reg_write( DDR_REG_BASE +0x5181e*4+0x02000000,0xe805); +reg_write( DDR_REG_BASE +0x5181f*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x51820*4+0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x51821*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x51822*4+0x02000000,0x7dbb); +reg_write( DDR_REG_BASE +0x51823*4+0x02000000,0xb15); +reg_write( DDR_REG_BASE +0x51824*4+0x02000000,0x3031); +reg_write( DDR_REG_BASE +0x51825*4+0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x51826*4+0x02000000,0x110d); +reg_write( DDR_REG_BASE +0x51827*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x51828*4+0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x51829*4+0x02000000,0xd36); +reg_write( DDR_REG_BASE +0x5182a*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5182b*4+0x02000000,0xdabf); +reg_write( DDR_REG_BASE +0x5182c*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5182d*4+0x02000000,0x250f); +reg_write( DDR_REG_BASE +0x5182e*4+0x02000000,0x139b); +reg_write( DDR_REG_BASE +0x5182f*4+0x02000000,0xe887); +reg_write( DDR_REG_BASE +0x51830*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x51831*4+0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x51832*4+0x02000000,0xd22); +reg_write( DDR_REG_BASE +0x51833*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51834*4+0x02000000,0xda7f); +reg_write( DDR_REG_BASE +0x51835*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51836*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51837*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51838*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51839*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x5183a*4+0x02000000,0x164d); +reg_write( DDR_REG_BASE +0x5183b*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5183c*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x5183d*4+0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x5183e*4+0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x5183f*4+0x02000000,0xdff); +reg_write( DDR_REG_BASE +0x51840*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x51841*4+0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x51842*4+0x02000000,0x60f8); +reg_write( DDR_REG_BASE +0x51843*4+0x02000000,0x60b9); +reg_write( DDR_REG_BASE +0x51844*4+0x02000000,0xfb6); +reg_write( DDR_REG_BASE +0x51845*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x51846*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x51847*4+0x02000000,0x6c7); +reg_write( DDR_REG_BASE +0x51848*4+0x02000000,0x862); +reg_write( DDR_REG_BASE +0x51849*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x5184a*4+0x02000000,0x86a); +reg_write( DDR_REG_BASE +0x5184b*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x5184c*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x5184d*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x5184e*4+0x02000000,0xdb6); +reg_write( DDR_REG_BASE +0x5184f*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x51850*4+0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x51851*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51852*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51853*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51854*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51855*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x51856*4+0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x51857*4+0x02000000,0x60f8); +reg_write( DDR_REG_BASE +0x51858*4+0x02000000,0x60b8); +reg_write( DDR_REG_BASE +0x51859*4+0x02000000,0x1003); +reg_write( DDR_REG_BASE +0x5185a*4+0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x5185b*4+0x02000000,0x783d); +reg_write( DDR_REG_BASE +0x5185c*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5185d*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5185e*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5185f*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x51860*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x51861*4+0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x51862*4+0x02000000,0x20c5); +reg_write( DDR_REG_BASE +0x51863*4+0x02000000,0x4ab); +reg_write( DDR_REG_BASE +0x51864*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51865*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x51866*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x51867*4+0x02000000,0x22); +reg_write( DDR_REG_BASE +0x51868*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x51869*4+0x02000000,0x91a); +reg_write( DDR_REG_BASE +0x5186a*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x5186b*4+0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x5186c*4+0x02000000,0xc0a2); +reg_write( DDR_REG_BASE +0x5186d*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x5186e*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x5186f*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51870*4+0x02000000,0x7a1b); +reg_write( DDR_REG_BASE +0x51871*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51872*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51873*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51874*4+0x02000000,0x1c); +reg_write( DDR_REG_BASE +0x51875*4+0x02000000,0xbac4); +reg_write( DDR_REG_BASE +0x51876*4+0x02000000,0xea05); +reg_write( DDR_REG_BASE +0x51877*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x51878*4+0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x51879*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x5187a*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5187b*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x5187c*4+0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x5187d*4+0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x5187e*4+0x02000000,0xea05); +reg_write( DDR_REG_BASE +0x5187f*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x51880*4+0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x51881*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x51882*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51883*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x51884*4+0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x51885*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51886*4+0x02000000,0xc0e2); +reg_write( DDR_REG_BASE +0x51887*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51888*4+0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x51889*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5188a*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5188b*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x5188c*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x5188d*4+0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x5188e*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5188f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51890*4+0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x51891*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x51892*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51893*4+0x02000000,0x86); +reg_write( DDR_REG_BASE +0x51894*4+0x02000000,0x9240); +reg_write( DDR_REG_BASE +0x51895*4+0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x51896*4+0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x51897*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51898*4+0x02000000,0xfe86); +reg_write( DDR_REG_BASE +0x51899*4+0x02000000,0x22c4); +reg_write( DDR_REG_BASE +0x5189a*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x5189b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5189c*4+0x02000000,0xbfff); +reg_write( DDR_REG_BASE +0x5189d*4+0x02000000,0xf203); +reg_write( DDR_REG_BASE +0x5189e*4+0x02000000,0xba8e); +reg_write( DDR_REG_BASE +0x5189f*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x518a0*4+0x02000000,0xb340); +reg_write( DDR_REG_BASE +0x518a1*4+0x02000000,0xf01d); +reg_write( DDR_REG_BASE +0x518a2*4+0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x518a3*4+0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x518a4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x518a5*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x518a6*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x518a7*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x518a8*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x518a9*4+0x02000000,0x4a); +reg_write( DDR_REG_BASE +0x518aa*4+0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x518ab*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x518ac*4+0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x518ad*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x518ae*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x518af*4+0x02000000,0xe80b); +reg_write( DDR_REG_BASE +0x518b0*4+0x02000000,0x9340); +reg_write( DDR_REG_BASE +0x518b1*4+0x02000000,0x2114); +reg_write( DDR_REG_BASE +0x518b2*4+0x02000000,0x34c); +reg_write( DDR_REG_BASE +0x518b3*4+0x02000000,0xb440); +reg_write( DDR_REG_BASE +0x518b4*4+0x02000000,0x2204); +reg_write( DDR_REG_BASE +0x518b5*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x518b6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x518b7*4+0x02000000,0xfbff); +reg_write( DDR_REG_BASE +0x518b8*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x518b9*4+0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x518ba*4+0x02000000,0x342); +reg_write( DDR_REG_BASE +0x518bb*4+0x02000000,0xb340); +reg_write( DDR_REG_BASE +0x518bc*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x518bd*4+0x02000000,0xdcd); +reg_write( DDR_REG_BASE +0x518be*4+0x02000000,0x9294); +reg_write( DDR_REG_BASE +0x518bf*4+0x02000000,0xc4c2); +reg_write( DDR_REG_BASE +0x518c0*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x518c1*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x518c2*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x518c3*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x518c4*4+0x02000000,0x7cf); +reg_write( DDR_REG_BASE +0x518c5*4+0x02000000,0xdd24); +reg_write( DDR_REG_BASE +0x518c6*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x518c7*4+0x02000000,0xbd9f); +reg_write( DDR_REG_BASE +0x518c8*4+0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x518c9*4+0x02000000,0xe007); +reg_write( DDR_REG_BASE +0x518ca*4+0x02000000,0x7a1d); +reg_write( DDR_REG_BASE +0x518cb*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x518cc*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x518cd*4+0x02000000,0x6a09); +reg_write( DDR_REG_BASE +0x518ce*4+0x02000000,0xa901); +reg_write( DDR_REG_BASE +0x518cf*4+0x02000000,0x1534); +reg_write( DDR_REG_BASE +0x518d0*4+0x02000000,0x108c); +reg_write( DDR_REG_BASE +0x518d1*4+0x02000000,0xec0e); +reg_write( DDR_REG_BASE +0x518d2*4+0x02000000,0xca02); +reg_write( DDR_REG_BASE +0x518d3*4+0x02000000,0x7a1d); +reg_write( DDR_REG_BASE +0x518d4*4+0x02000000,0xa942); +reg_write( DDR_REG_BASE +0x518d5*4+0x02000000,0x1533); +reg_write( DDR_REG_BASE +0x518d6*4+0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x518d7*4+0x02000000,0xe007); +reg_write( DDR_REG_BASE +0x518d8*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x518d9*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x518da*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x518db*4+0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x518dc*4+0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x518dd*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x518de*4+0x02000000,0xa942); +reg_write( DDR_REG_BASE +0x518df*4+0x02000000,0xa903); +reg_write( DDR_REG_BASE +0x518e0*4+0x02000000,0xf01e); +reg_write( DDR_REG_BASE +0x518e1*4+0x02000000,0xee05); +reg_write( DDR_REG_BASE +0x518e2*4+0x02000000,0x1533); +reg_write( DDR_REG_BASE +0x518e3*4+0x02000000,0x108f); +reg_write( DDR_REG_BASE +0x518e4*4+0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x518e5*4+0x02000000,0x8de0); +reg_write( DDR_REG_BASE +0x518e6*4+0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x518e7*4+0x02000000,0xf16); +reg_write( DDR_REG_BASE +0x518e8*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x518e9*4+0x02000000,0x796f); +reg_write( DDR_REG_BASE +0x518ea*4+0x02000000,0xe804); +reg_write( DDR_REG_BASE +0x518eb*4+0x02000000,0x6f07); +reg_write( DDR_REG_BASE +0x518ec*4+0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x518ed*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x518ee*4+0x02000000,0x4f1f); +reg_write( DDR_REG_BASE +0x518ef*4+0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x518f0*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x518f1*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x518f2*4+0x02000000,0x2314); +reg_write( DDR_REG_BASE +0x518f3*4+0x02000000,0x380); +reg_write( DDR_REG_BASE +0x518f4*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x518f5*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x518f6*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x518f7*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x518f8*4+0x02000000,0x784); +reg_write( DDR_REG_BASE +0x518f9*4+0x02000000,0xa820); +reg_write( DDR_REG_BASE +0x518fa*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x518fb*4+0x02000000,0xecf); +reg_write( DDR_REG_BASE +0x518fc*4+0x02000000,0x9094); +reg_write( DDR_REG_BASE +0x518fd*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x518fe*4+0x02000000,0xbfb); +reg_write( DDR_REG_BASE +0x518ff*4+0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x51900*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x51901*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51902*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51903*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51904*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51905*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x51906*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51907*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x51908*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x51909*4+0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x5190a*4+0x02000000,0x17c0); +reg_write( DDR_REG_BASE +0x5190b*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x5190c*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x5190d*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x5190e*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x5190f*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x51910*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51911*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51912*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51913*4+0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x51914*4+0x02000000,0x817); +reg_write( DDR_REG_BASE +0x51915*4+0x02000000,0x70); +reg_write( DDR_REG_BASE +0x51916*4+0x02000000,0x4748); +reg_write( DDR_REG_BASE +0x51917*4+0x02000000,0x73ad); +reg_write( DDR_REG_BASE +0x51918*4+0x02000000,0xe88f); +reg_write( DDR_REG_BASE +0x51919*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5191a*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5191b*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5191c*4+0x02000000,0x25); +reg_write( DDR_REG_BASE +0x5191d*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x5191e*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x5191f*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51920*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51921*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51922*4+0x02000000,0x58); +reg_write( DDR_REG_BASE +0x51923*4+0x02000000,0x72ad); +reg_write( DDR_REG_BASE +0x51924*4+0x02000000,0x790b); +reg_write( DDR_REG_BASE +0x51925*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51926*4+0x02000000,0xf212); +reg_write( DDR_REG_BASE +0x51927*4+0x02000000,0xc42); +reg_write( DDR_REG_BASE +0x51928*4+0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x51929*4+0x02000000,0x8c6); +reg_write( DDR_REG_BASE +0x5192a*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5192b*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x5192c*4+0x02000000,0xb5a); +reg_write( DDR_REG_BASE +0x5192d*4+0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x5192e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5192f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51930*4+0x02000000,0x7d8); +reg_write( DDR_REG_BASE +0x51931*4+0x02000000,0x8020); +reg_write( DDR_REG_BASE +0x51932*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x51933*4+0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x51934*4+0x02000000,0xdb6); +reg_write( DDR_REG_BASE +0x51935*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51936*4+0x02000000,0x43e1); +reg_write( DDR_REG_BASE +0x51937*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51938*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x51939*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x5193a*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5193b*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5193c*4+0x02000000,0x4833); +reg_write( DDR_REG_BASE +0x5193d*4+0x02000000,0x4910); +reg_write( DDR_REG_BASE +0x5193e*4+0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x5193f*4+0x02000000,0x2348); +reg_write( DDR_REG_BASE +0x51940*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x51941*4+0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x51942*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51943*4+0x02000000,0x7b6e); +reg_write( DDR_REG_BASE +0x51944*4+0x02000000,0x780e); +reg_write( DDR_REG_BASE +0x51945*4+0x02000000,0x2309); +reg_write( DDR_REG_BASE +0x51946*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51947*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x51948*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51949*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5194a*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x5194b*4+0x02000000,0x956); +reg_write( DDR_REG_BASE +0x5194c*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x5194d*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x5194e*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x5194f*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51950*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51951*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51952*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51953*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51954*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x51955*4+0x02000000,0x1e8); +reg_write( DDR_REG_BASE +0x51956*4+0x02000000,0x9020); +reg_write( DDR_REG_BASE +0x51957*4+0x02000000,0x2059); +reg_write( DDR_REG_BASE +0x51958*4+0x02000000,0xf40); +reg_write( DDR_REG_BASE +0x51959*4+0x02000000,0x7724); +reg_write( DDR_REG_BASE +0x5195a*4+0x02000000,0x7930); +reg_write( DDR_REG_BASE +0x5195b*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x5195c*4+0x02000000,0x2155); +reg_write( DDR_REG_BASE +0x5195d*4+0x02000000,0xc0d); +reg_write( DDR_REG_BASE +0x5195e*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x5195f*4+0x02000000,0xe); +reg_write( DDR_REG_BASE +0x51960*4+0x02000000,0x7d05); +reg_write( DDR_REG_BASE +0x51961*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51962*4+0x02000000,0x111b); +reg_write( DDR_REG_BASE +0x51963*4+0x02000000,0x95e0); +reg_write( DDR_REG_BASE +0x51964*4+0x02000000,0x83a); +reg_write( DDR_REG_BASE +0x51965*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51966*4+0x02000000,0xd896); +reg_write( DDR_REG_BASE +0x51967*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51968*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51969*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5196a*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5196b*4+0x02000000,0x6822); +reg_write( DDR_REG_BASE +0x5196c*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5196d*4+0x02000000,0xb8e0); +reg_write( DDR_REG_BASE +0x5196e*4+0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x5196f*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51970*4+0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x51971*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51972*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51973*4+0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x51974*4+0x02000000,0x2304); +reg_write( DDR_REG_BASE +0x51975*4+0x02000000,0x305b); +reg_write( DDR_REG_BASE +0x51976*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51977*4+0x02000000,0x6c0); +reg_write( DDR_REG_BASE +0x51978*4+0x02000000,0x79e4); +reg_write( DDR_REG_BASE +0x51979*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x5197a*4+0x02000000,0x2145); +reg_write( DDR_REG_BASE +0x5197b*4+0x02000000,0x3c0); +reg_write( DDR_REG_BASE +0x5197c*4+0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x5197d*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x5197e*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x5197f*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51980*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51981*4+0x02000000,0x7101); +reg_write( DDR_REG_BASE +0x51982*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51983*4+0x02000000,0x6); +reg_write( DDR_REG_BASE +0x51984*4+0x02000000,0x790c); +reg_write( DDR_REG_BASE +0x51985*4+0x02000000,0x2985); +reg_write( DDR_REG_BASE +0x51986*4+0x02000000,0x41f); +reg_write( DDR_REG_BASE +0x51987*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x51988*4+0x02000000,0x6901); +reg_write( DDR_REG_BASE +0x51989*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5198a*4+0x02000000,0x2042); +reg_write( DDR_REG_BASE +0x5198b*4+0x02000000,0x701); +reg_write( DDR_REG_BASE +0x5198c*4+0x02000000,0x939); +reg_write( DDR_REG_BASE +0x5198d*4+0x02000000,0x454); +reg_write( DDR_REG_BASE +0x5198e*4+0x02000000,0x889); +reg_write( DDR_REG_BASE +0x5198f*4+0x02000000,0xc30); +reg_write( DDR_REG_BASE +0x51990*4+0x02000000,0xd91a); +reg_write( DDR_REG_BASE +0x51991*4+0x02000000,0x885); +reg_write( DDR_REG_BASE +0x51992*4+0x02000000,0xd70); +reg_write( DDR_REG_BASE +0x51993*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x51994*4+0x02000000,0x87d); +reg_write( DDR_REG_BASE +0x51995*4+0x02000000,0xf30); +reg_write( DDR_REG_BASE +0x51996*4+0x02000000,0xd918); +reg_write( DDR_REG_BASE +0x51997*4+0x02000000,0xe0c5); +reg_write( DDR_REG_BASE +0x51998*4+0x02000000,0xf227); +reg_write( DDR_REG_BASE +0x51999*4+0x02000000,0xe0d0); +reg_write( DDR_REG_BASE +0x5199a*4+0x02000000,0xf227); +reg_write( DDR_REG_BASE +0x5199b*4+0x02000000,0xe0e0); +reg_write( DDR_REG_BASE +0x5199c*4+0x02000000,0xf227); +reg_write( DDR_REG_BASE +0x5199d*4+0x02000000,0xe0f8); +reg_write( DDR_REG_BASE +0x5199e*4+0x02000000,0xf227); +reg_write( DDR_REG_BASE +0x5199f*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x519a0*4+0x02000000,0x8c03); +reg_write( DDR_REG_BASE +0x519a1*4+0x02000000,0x722c); +reg_write( DDR_REG_BASE +0x519a2*4+0x02000000,0xf230); +reg_write( DDR_REG_BASE +0x519a3*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x519a4*4+0x02000000,0x8802); +reg_write( DDR_REG_BASE +0x519a5*4+0x02000000,0xf419); +reg_write( DDR_REG_BASE +0x519a6*4+0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x519a7*4+0x02000000,0xf02c); +reg_write( DDR_REG_BASE +0x519a8*4+0x02000000,0x2025); +reg_write( DDR_REG_BASE +0x519a9*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x519aa*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x519ab*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x519ac*4+0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x519ad*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x519ae*4+0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x519af*4+0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x519b0*4+0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x519b1*4+0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x519b2*4+0x02000000,0xf00b); +reg_write( DDR_REG_BASE +0x519b3*4+0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x519b4*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x519b5*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x519b6*4+0x02000000,0xf019); +reg_write( DDR_REG_BASE +0x519b7*4+0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x519b8*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x519b9*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x519ba*4+0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x519bb*4+0x02000000,0xd93f); +reg_write( DDR_REG_BASE +0x519bc*4+0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x519bd*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x519be*4+0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x519bf*4+0x02000000,0xd90b); +reg_write( DDR_REG_BASE +0x519c0*4+0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x519c1*4+0x02000000,0xd90a); +reg_write( DDR_REG_BASE +0x519c2*4+0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x519c3*4+0x02000000,0xd907); +reg_write( DDR_REG_BASE +0x519c4*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x519c5*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x519c6*4+0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x519c7*4+0x02000000,0xd93e); +reg_write( DDR_REG_BASE +0x519c8*4+0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x519c9*4+0x02000000,0xd93b); +reg_write( DDR_REG_BASE +0x519ca*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x519cb*4+0x02000000,0xd93a); +reg_write( DDR_REG_BASE +0x519cc*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x519cd*4+0x02000000,0xd91f); +reg_write( DDR_REG_BASE +0x519ce*4+0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x519cf*4+0x02000000,0xd938); +reg_write( DDR_REG_BASE +0x519d0*4+0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x519d1*4+0x02000000,0xd91b); +reg_write( DDR_REG_BASE +0x519d2*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x519d3*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x519d4*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x519d5*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x519d6*4+0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x519d7*4+0x02000000,0x265a); +reg_write( DDR_REG_BASE +0x519d8*4+0x02000000,0x3c83); +reg_write( DDR_REG_BASE +0x519d9*4+0x02000000,0x607c); +reg_write( DDR_REG_BASE +0x519da*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x519db*4+0x02000000,0x1643); +reg_write( DDR_REG_BASE +0x519dc*4+0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x519dd*4+0x02000000,0x639b); +reg_write( DDR_REG_BASE +0x519de*4+0x02000000,0x633b); +reg_write( DDR_REG_BASE +0x519df*4+0x02000000,0x8b80); +reg_write( DDR_REG_BASE +0x519e0*4+0x02000000,0x7c45); +reg_write( DDR_REG_BASE +0x519e1*4+0x02000000,0xab80); +reg_write( DDR_REG_BASE +0x519e2*4+0x02000000,0xbeb); +reg_write( DDR_REG_BASE +0x519e3*4+0x02000000,0x9094); +reg_write( DDR_REG_BASE +0x519e4*4+0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x519e5*4+0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x519e6*4+0x02000000,0xef9); +reg_write( DDR_REG_BASE +0x519e7*4+0x02000000,0xb0b4); +reg_write( DDR_REG_BASE +0x519e8*4+0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x519e9*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x519ea*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x519eb*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x519ec*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x519ed*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x519ee*4+0x02000000,0x3a0d); +reg_write( DDR_REG_BASE +0x519ef*4+0x02000000,0xe76); +reg_write( DDR_REG_BASE +0x519f0*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x519f1*4+0x02000000,0xc083); +reg_write( DDR_REG_BASE +0x519f2*4+0x02000000,0xc083); +reg_write( DDR_REG_BASE +0x519f3*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x519f4*4+0x02000000,0xfc2); +reg_write( DDR_REG_BASE +0x519f5*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x519f6*4+0x02000000,0xdac8); +reg_write( DDR_REG_BASE +0x519f7*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x519f8*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x519f9*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x519fa*4+0x02000000,0x1b); +reg_write( DDR_REG_BASE +0x519fb*4+0x02000000,0x899); +reg_write( DDR_REG_BASE +0x519fc*4+0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x519fd*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x519fe*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x519ff*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51a00*4+0x02000000,0x880e); +reg_write( DDR_REG_BASE +0x51a01*4+0x02000000,0x88d); +reg_write( DDR_REG_BASE +0x51a02*4+0x02000000,0x30); +reg_write( DDR_REG_BASE +0x51a03*4+0x02000000,0xdb4b); +reg_write( DDR_REG_BASE +0x51a04*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51a05*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a06*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51a07*4+0x02000000,0x888d); +reg_write( DDR_REG_BASE +0x51a08*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51a09*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a0a*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51a0b*4+0x02000000,0x88ac); +reg_write( DDR_REG_BASE +0x51a0c*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51a0d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a0e*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51a0f*4+0x02000000,0x88cb); +reg_write( DDR_REG_BASE +0x51a10*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51a11*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a12*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51a13*4+0x02000000,0x882a); +reg_write( DDR_REG_BASE +0x51a14*4+0x02000000,0xbb9f); +reg_write( DDR_REG_BASE +0x51a15*4+0x02000000,0x1b01); +reg_write( DDR_REG_BASE +0x51a16*4+0x02000000,0x52); +reg_write( DDR_REG_BASE +0x51a17*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51a18*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a19*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51a1a*4+0x02000000,0x88eb); +reg_write( DDR_REG_BASE +0x51a1b*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51a1c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a1d*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51a1e*4+0x02000000,0xabe0); +reg_write( DDR_REG_BASE +0x51a1f*4+0x02000000,0x884c); +reg_write( DDR_REG_BASE +0x51a20*4+0x02000000,0x279a); +reg_write( DDR_REG_BASE +0x51a21*4+0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x51a22*4+0x02000000,0x1b32); +reg_write( DDR_REG_BASE +0x51a23*4+0x02000000,0x82); +reg_write( DDR_REG_BASE +0x51a24*4+0x02000000,0xc166); +reg_write( DDR_REG_BASE +0x51a25*4+0x02000000,0x1c31); +reg_write( DDR_REG_BASE +0x51a26*4+0x02000000,0x3382); +reg_write( DDR_REG_BASE +0x51a27*4+0x02000000,0x1c4a); +reg_write( DDR_REG_BASE +0x51a28*4+0x02000000,0x3342); +reg_write( DDR_REG_BASE +0x51a29*4+0x02000000,0x1c63); +reg_write( DDR_REG_BASE +0x51a2a*4+0x02000000,0x3302); +reg_write( DDR_REG_BASE +0x51a2b*4+0x02000000,0x13b8); +reg_write( DDR_REG_BASE +0x51a2c*4+0x02000000,0x8080); +reg_write( DDR_REG_BASE +0x51a2d*4+0x02000000,0x7f25); +reg_write( DDR_REG_BASE +0x51a2e*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51a2f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a30*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51a31*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x51a32*4+0x02000000,0x18d); +reg_write( DDR_REG_BASE +0x51a33*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51a34*4+0x02000000,0x12); +reg_write( DDR_REG_BASE +0x51a35*4+0x02000000,0x310); +reg_write( DDR_REG_BASE +0x51a36*4+0x02000000,0x892d); +reg_write( DDR_REG_BASE +0x51a37*4+0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x51a38*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51a39*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a3a*4+0x02000000,0x65d8); +reg_write( DDR_REG_BASE +0x51a3b*4+0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x51a3c*4+0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x51a3d*4+0x02000000,0x1b33); +reg_write( DDR_REG_BASE +0x51a3e*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x51a3f*4+0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x51a40*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51a41*4+0x02000000,0x6e02); +reg_write( DDR_REG_BASE +0x51a42*4+0x02000000,0x60b8); +reg_write( DDR_REG_BASE +0x51a43*4+0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x51a44*4+0x02000000,0x7945); +reg_write( DDR_REG_BASE +0x51a45*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51a46*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51a47*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x51a48*4+0x02000000,0xc083); +reg_write( DDR_REG_BASE +0x51a49*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51a4a*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x51a4b*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x51a4c*4+0x02000000,0x5800); +reg_write( DDR_REG_BASE +0x51a4d*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x51a4e*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x51a4f*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x51a50*4+0x02000000,0xc4e); +reg_write( DDR_REG_BASE +0x51a51*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a52*4+0x02000000,0x9ea); +reg_write( DDR_REG_BASE +0x51a53*4+0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x51a54*4+0x02000000,0xc96); +reg_write( DDR_REG_BASE +0x51a55*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x51a56*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51a57*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51a58*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x51a59*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51a5a*4+0x02000000,0xdc); +reg_write( DDR_REG_BASE +0x51a5b*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51a5c*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51a5d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a5e*4+0x02000000,0x19); +reg_write( DDR_REG_BASE +0x51a5f*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51a60*4+0x02000000,0x2f6); +reg_write( DDR_REG_BASE +0x51a61*4+0x02000000,0x22); +reg_write( DDR_REG_BASE +0x51a62*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51a63*4+0x02000000,0x2e3); +reg_write( DDR_REG_BASE +0x51a64*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a65*4+0x02000000,0xe90b); +reg_write( DDR_REG_BASE +0x51a66*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51a67*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51a68*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a69*4+0x02000000,0x58); +reg_write( DDR_REG_BASE +0x51a6a*4+0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x51a6b*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51a6c*4+0x02000000,0xf40b); +reg_write( DDR_REG_BASE +0x51a6d*4+0x02000000,0x2cd); +reg_write( DDR_REG_BASE +0x51a6e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a6f*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51a70*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51a71*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a72*4+0x02000000,0x25); +reg_write( DDR_REG_BASE +0x51a73*4+0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x51a74*4+0x02000000,0x2bc); +reg_write( DDR_REG_BASE +0x51a75*4+0x02000000,0x21); +reg_write( DDR_REG_BASE +0x51a76*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51a77*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x51a78*4+0x02000000,0xe26); +reg_write( DDR_REG_BASE +0x51a79*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51a7a*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51a7b*4+0x02000000,0x216f); +reg_write( DDR_REG_BASE +0x51a7c*4+0x02000000,0xc3); +reg_write( DDR_REG_BASE +0x51a7d*4+0x02000000,0x1100); +reg_write( DDR_REG_BASE +0x51a7e*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x51a7f*4+0x02000000,0x89c3); +reg_write( DDR_REG_BASE +0x51a80*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51a81*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51a82*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51a83*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x51a84*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a85*4+0x02000000,0x2c8); +reg_write( DDR_REG_BASE +0x51a86*4+0x02000000,0xece); +reg_write( DDR_REG_BASE +0x51a87*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51a88*4+0x02000000,0xdaa0); +reg_write( DDR_REG_BASE +0x51a89*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51a8a*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x51a8b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a8c*4+0x02000000,0x228); +reg_write( DDR_REG_BASE +0x51a8d*4+0x02000000,0xec2); +reg_write( DDR_REG_BASE +0x51a8e*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51a8f*4+0x02000000,0xdaa0); +reg_write( DDR_REG_BASE +0x51a90*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x51a91*4+0x02000000,0x3c40); +reg_write( DDR_REG_BASE +0x51a92*4+0x02000000,0xeb6); +reg_write( DDR_REG_BASE +0x51a93*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51a94*4+0x02000000,0xdaa0); +reg_write( DDR_REG_BASE +0x51a95*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51a96*4+0x02000000,0x3e80); +reg_write( DDR_REG_BASE +0x51a97*4+0x02000000,0xeae); +reg_write( DDR_REG_BASE +0x51a98*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51a99*4+0x02000000,0xdaa0); +reg_write( DDR_REG_BASE +0x51a9a*4+0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x51a9b*4+0x02000000,0x1f8e); +reg_write( DDR_REG_BASE +0x51a9c*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x51a9d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a9e*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x51a9f*4+0x02000000,0xf064); +reg_write( DDR_REG_BASE +0x51aa0*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51aa1*4+0x02000000,0xe9a); +reg_write( DDR_REG_BASE +0x51aa2*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51aa3*4+0x02000000,0xda28); +reg_write( DDR_REG_BASE +0x51aa4*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51aa5*4+0x02000000,0x3980); +reg_write( DDR_REG_BASE +0x51aa6*4+0x02000000,0xe8e); +reg_write( DDR_REG_BASE +0x51aa7*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51aa8*4+0x02000000,0xda28); +reg_write( DDR_REG_BASE +0x51aa9*4+0x02000000,0xc09c); +reg_write( DDR_REG_BASE +0x51aaa*4+0x02000000,0xe86); +reg_write( DDR_REG_BASE +0x51aab*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51aac*4+0x02000000,0xda28); +reg_write( DDR_REG_BASE +0x51aad*4+0x02000000,0x2355); +reg_write( DDR_REG_BASE +0x51aae*4+0x02000000,0x3800); +reg_write( DDR_REG_BASE +0x51aaf*4+0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x51ab0*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51ab1*4+0x02000000,0x3c01); +reg_write( DDR_REG_BASE +0x51ab2*4+0x02000000,0xa8a); +reg_write( DDR_REG_BASE +0x51ab3*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51ab4*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x51ab5*4+0x02000000,0x2355); +reg_write( DDR_REG_BASE +0x51ab6*4+0x02000000,0x38c0); +reg_write( DDR_REG_BASE +0x51ab7*4+0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x51ab8*4+0x02000000,0xa7e); +reg_write( DDR_REG_BASE +0x51ab9*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51aba*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51abb*4+0x02000000,0x3981); +reg_write( DDR_REG_BASE +0x51abc*4+0x02000000,0x2355); +reg_write( DDR_REG_BASE +0x51abd*4+0x02000000,0x3d00); +reg_write( DDR_REG_BASE +0x51abe*4+0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x51abf*4+0x02000000,0xa72); +reg_write( DDR_REG_BASE +0x51ac0*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51ac1*4+0x02000000,0xc19c); +reg_write( DDR_REG_BASE +0x51ac2*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51ac3*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51ac4*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51ac5*4+0x02000000,0x1003); +reg_write( DDR_REG_BASE +0x51ac6*4+0x02000000,0x8b); +reg_write( DDR_REG_BASE +0x51ac7*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51ac8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51ac9*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51aca*4+0x02000000,0x8862); +reg_write( DDR_REG_BASE +0x51acb*4+0x02000000,0xf035); +reg_write( DDR_REG_BASE +0x51acc*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51acd*4+0x02000000,0x3c00); +reg_write( DDR_REG_BASE +0x51ace*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x51acf*4+0x02000000,0xde); +reg_write( DDR_REG_BASE +0x51ad0*4+0x02000000,0x94e); +reg_write( DDR_REG_BASE +0x51ad1*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51ad2*4+0x02000000,0x200a); +reg_write( DDR_REG_BASE +0x51ad3*4+0x02000000,0x780); +reg_write( DDR_REG_BASE +0x51ad4*4+0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x51ad5*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51ad6*4+0x02000000,0x3980); +reg_write( DDR_REG_BASE +0x51ad7*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x51ad8*4+0x02000000,0xcd); +reg_write( DDR_REG_BASE +0x51ad9*4+0x02000000,0xc09c); +reg_write( DDR_REG_BASE +0x51ada*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x51adb*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x51adc*4+0x02000000,0xbdc5); +reg_write( DDR_REG_BASE +0x51add*4+0x02000000,0x936); +reg_write( DDR_REG_BASE +0x51ade*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51adf*4+0x02000000,0x65fd); +reg_write( DDR_REG_BASE +0x51ae0*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x51ae1*4+0x02000000,0x3a02); +reg_write( DDR_REG_BASE +0x51ae2*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51ae3*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x51ae4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51ae5*4+0x02000000,0x2c8); +reg_write( DDR_REG_BASE +0x51ae6*4+0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x51ae7*4+0x02000000,0x7974); +reg_write( DDR_REG_BASE +0x51ae8*4+0x02000000,0xb1a0); +reg_write( DDR_REG_BASE +0x51ae9*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51aea*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x51aeb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51aec*4+0x02000000,0x228); +reg_write( DDR_REG_BASE +0x51aed*4+0x02000000,0x615c); +reg_write( DDR_REG_BASE +0x51aee*4+0x02000000,0x212f); +reg_write( DDR_REG_BASE +0x51aef*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x51af0*4+0x02000000,0x7c74); +reg_write( DDR_REG_BASE +0x51af1*4+0x02000000,0x216c); +reg_write( DDR_REG_BASE +0x51af2*4+0x02000000,0x101); +reg_write( DDR_REG_BASE +0x51af3*4+0x02000000,0xb420); +reg_write( DDR_REG_BASE +0x51af4*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x51af5*4+0x02000000,0x3c41); +reg_write( DDR_REG_BASE +0x51af6*4+0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x51af7*4+0x02000000,0x7974); +reg_write( DDR_REG_BASE +0x51af8*4+0x02000000,0xb1e0); +reg_write( DDR_REG_BASE +0x51af9*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51afa*4+0x02000000,0x3e81); +reg_write( DDR_REG_BASE +0x51afb*4+0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x51afc*4+0x02000000,0x7974); +reg_write( DDR_REG_BASE +0x51afd*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x51afe*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x51aff*4+0x02000000,0xb9d); +reg_write( DDR_REG_BASE +0x51b00*4+0x02000000,0x90c5); +reg_write( DDR_REG_BASE +0x51b01*4+0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x51b02*4+0x02000000,0xb3d); +reg_write( DDR_REG_BASE +0x51b03*4+0x02000000,0xb134); +reg_write( DDR_REG_BASE +0x51b04*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51b05*4+0x02000000,0x3c00); +reg_write( DDR_REG_BASE +0x51b06*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51b07*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51b08*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51b09*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51b0a*4+0x02000000,0xd930); +reg_write( DDR_REG_BASE +0x51b0b*4+0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x51b0c*4+0x02000000,0x2140); +reg_write( DDR_REG_BASE +0x51b0d*4+0x02000000,0xcce); +reg_write( DDR_REG_BASE +0x51b0e*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51b0f*4+0x02000000,0x2642); +reg_write( DDR_REG_BASE +0x51b10*4+0x02000000,0x1283); +reg_write( DDR_REG_BASE +0x51b11*4+0x02000000,0x2142); +reg_write( DDR_REG_BASE +0x51b12*4+0x02000000,0x280); +reg_write( DDR_REG_BASE +0x51b13*4+0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x51b14*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51b15*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51b16*4+0x02000000,0x26ca); +reg_write( DDR_REG_BASE +0x51b17*4+0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x51b18*4+0x02000000,0x4308); +reg_write( DDR_REG_BASE +0x51b19*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51b1a*4+0x02000000,0xf059); +reg_write( DDR_REG_BASE +0x51b1b*4+0x02000000,0xdab); +reg_write( DDR_REG_BASE +0x51b1c*4+0x02000000,0x12e0); +reg_write( DDR_REG_BASE +0x51b1d*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51b1e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51b1f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51b20*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51b21*4+0x02000000,0x1003); +reg_write( DDR_REG_BASE +0x51b22*4+0x02000000,0x9f); +reg_write( DDR_REG_BASE +0x51b23*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51b24*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51b25*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51b26*4+0x02000000,0x8882); +reg_write( DDR_REG_BASE +0x51b27*4+0x02000000,0xba8f); +reg_write( DDR_REG_BASE +0x51b28*4+0x02000000,0x4358); +reg_write( DDR_REG_BASE +0x51b29*4+0x02000000,0xf02e); +reg_write( DDR_REG_BASE +0x51b2a*4+0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x51b2b*4+0x02000000,0x1a0f); +reg_write( DDR_REG_BASE +0x51b2c*4+0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x51b2d*4+0x02000000,0x923); +reg_write( DDR_REG_BASE +0x51b2e*4+0x02000000,0x32); +reg_write( DDR_REG_BASE +0x51b2f*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x51b30*4+0x02000000,0x1a00); +reg_write( DDR_REG_BASE +0x51b31*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51b32*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x51b33*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51b34*4+0x02000000,0x228); +reg_write( DDR_REG_BASE +0x51b35*4+0x02000000,0x61f9); +reg_write( DDR_REG_BASE +0x51b36*4+0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x51b37*4+0x02000000,0x302); +reg_write( DDR_REG_BASE +0x51b38*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51b39*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x51b3a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51b3b*4+0x02000000,0x2c8); +reg_write( DDR_REG_BASE +0x51b3c*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x51b3d*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x51b3e*4+0x02000000,0x3c41); +reg_write( DDR_REG_BASE +0x51b3f*4+0x02000000,0x61fa); +reg_write( DDR_REG_BASE +0x51b40*4+0x02000000,0x22f4); +reg_write( DDR_REG_BASE +0x51b41*4+0x02000000,0x302); +reg_write( DDR_REG_BASE +0x51b42*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x51b43*4+0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x51b44*4+0x02000000,0x301); +reg_write( DDR_REG_BASE +0x51b45*4+0x02000000,0x7942); +reg_write( DDR_REG_BASE +0x51b46*4+0x02000000,0x2608); +reg_write( DDR_REG_BASE +0x51b47*4+0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x51b48*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51b49*4+0x02000000,0x3e81); +reg_write( DDR_REG_BASE +0x51b4a*4+0x02000000,0x673f); +reg_write( DDR_REG_BASE +0x51b4b*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51b4c*4+0x02000000,0x27f4); +reg_write( DDR_REG_BASE +0x51b4d*4+0x02000000,0x130f); +reg_write( DDR_REG_BASE +0x51b4e*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x51b4f*4+0x02000000,0x300); +reg_write( DDR_REG_BASE +0x51b50*4+0x02000000,0x212f); +reg_write( DDR_REG_BASE +0x51b51*4+0x02000000,0x6c6); +reg_write( DDR_REG_BASE +0x51b52*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x51b53*4+0x02000000,0x78e2); +reg_write( DDR_REG_BASE +0x51b54*4+0x02000000,0x2108); +reg_write( DDR_REG_BASE +0x51b55*4+0x02000000,0x1b); +reg_write( DDR_REG_BASE +0x51b56*4+0x02000000,0xfa9); +reg_write( DDR_REG_BASE +0x51b57*4+0x02000000,0xb325); +reg_write( DDR_REG_BASE +0x51b58*4+0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x51b59*4+0x02000000,0x3086); +reg_write( DDR_REG_BASE +0x51b5a*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51b5b*4+0x02000000,0x811); +reg_write( DDR_REG_BASE +0x51b5c*4+0x02000000,0x32); +reg_write( DDR_REG_BASE +0x51b5d*4+0x02000000,0x200a); +reg_write( DDR_REG_BASE +0x51b5e*4+0x02000000,0x780); +reg_write( DDR_REG_BASE +0x51b5f*4+0x02000000,0xf9e); +reg_write( DDR_REG_BASE +0x51b60*4+0x02000000,0xfe8f); +reg_write( DDR_REG_BASE +0x51b61*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x51b62*4+0x02000000,0xf1e); +reg_write( DDR_REG_BASE +0x51b63*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51b64*4+0x02000000,0x200a); +reg_write( DDR_REG_BASE +0x51b65*4+0x02000000,0x780); +reg_write( DDR_REG_BASE +0x51b66*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x51b67*4+0x02000000,0xf16); +reg_write( DDR_REG_BASE +0x51b68*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51b69*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x51b6a*4+0x02000000,0x6c6); +reg_write( DDR_REG_BASE +0x51b6b*4+0x02000000,0x1b01); +reg_write( DDR_REG_BASE +0x51b6c*4+0x02000000,0x52); +reg_write( DDR_REG_BASE +0x51b6d*4+0x02000000,0x1e01); +reg_write( DDR_REG_BASE +0x51b6e*4+0x02000000,0x1012); +reg_write( DDR_REG_BASE +0x51b6f*4+0x02000000,0x77a5); +reg_write( DDR_REG_BASE +0x51b70*4+0x02000000,0xd57); +reg_write( DDR_REG_BASE +0x51b71*4+0x02000000,0x9013); +reg_write( DDR_REG_BASE +0x51b72*4+0x02000000,0x7765); +reg_write( DDR_REG_BASE +0x51b73*4+0x02000000,0xbfd); +reg_write( DDR_REG_BASE +0x51b74*4+0x02000000,0x9033); +reg_write( DDR_REG_BASE +0x51b75*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x51b76*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51b77*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51b78*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51b79*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51b7a*4+0x02000000,0xd92c); +reg_write( DDR_REG_BASE +0x51b7b*4+0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x51b7c*4+0x02000000,0x2140); +reg_write( DDR_REG_BASE +0x51b7d*4+0x02000000,0xccb); +reg_write( DDR_REG_BASE +0x51b7e*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51b7f*4+0x02000000,0x2342); +reg_write( DDR_REG_BASE +0x51b80*4+0x02000000,0x1100); +reg_write( DDR_REG_BASE +0x51b81*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51b82*4+0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x51b83*4+0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x51b84*4+0x02000000,0x690c); +reg_write( DDR_REG_BASE +0x51b85*4+0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x51b86*4+0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x51b87*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51b88*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51b89*4+0x02000000,0xf042); +reg_write( DDR_REG_BASE +0x51b8a*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51b8b*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51b8c*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51b8d*4+0x02000000,0x1003); +reg_write( DDR_REG_BASE +0x51b8e*4+0x02000000,0x9e); +reg_write( DDR_REG_BASE +0x51b8f*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51b90*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51b91*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51b92*4+0x02000000,0x8842); +reg_write( DDR_REG_BASE +0x51b93*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51b94*4+0x02000000,0xb88f); +reg_write( DDR_REG_BASE +0x51b95*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x51b96*4+0x02000000,0xf01e); +reg_write( DDR_REG_BASE +0x51b97*4+0x02000000,0xc602); +reg_write( DDR_REG_BASE +0x51b98*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x51b99*4+0x02000000,0x3a0c); +reg_write( DDR_REG_BASE +0x51b9a*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x51b9b*4+0x02000000,0x3c4d); +reg_write( DDR_REG_BASE +0x51b9c*4+0x02000000,0x265a); +reg_write( DDR_REG_BASE +0x51b9d*4+0x02000000,0x1a0e); +reg_write( DDR_REG_BASE +0x51b9e*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51b9f*4+0x02000000,0x3e8f); +reg_write( DDR_REG_BASE +0x51ba0*4+0x02000000,0x6599); +reg_write( DDR_REG_BASE +0x51ba1*4+0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x51ba2*4+0x02000000,0x9f); +reg_write( DDR_REG_BASE +0x51ba3*4+0x02000000,0x67d9); +reg_write( DDR_REG_BASE +0x51ba4*4+0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x51ba5*4+0x02000000,0x81); +reg_write( DDR_REG_BASE +0x51ba6*4+0x02000000,0x64fc); +reg_write( DDR_REG_BASE +0x51ba7*4+0x02000000,0x65dd); +reg_write( DDR_REG_BASE +0x51ba8*4+0x02000000,0x2102); +reg_write( DDR_REG_BASE +0x51ba9*4+0x02000000,0x7c1); +reg_write( DDR_REG_BASE +0x51baa*4+0x02000000,0x2308); +reg_write( DDR_REG_BASE +0x51bab*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x51bac*4+0x02000000,0x24f4); +reg_write( DDR_REG_BASE +0x51bad*4+0x02000000,0x108c); +reg_write( DDR_REG_BASE +0x51bae*4+0x02000000,0x25f4); +reg_write( DDR_REG_BASE +0x51baf*4+0x02000000,0x1083); +reg_write( DDR_REG_BASE +0x51bb0*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x51bb1*4+0x02000000,0x7b82); +reg_write( DDR_REG_BASE +0x51bb2*4+0x02000000,0x2008); +reg_write( DDR_REG_BASE +0x51bb3*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x51bb4*4+0x02000000,0x780e); +reg_write( DDR_REG_BASE +0x51bb5*4+0x02000000,0xec7); +reg_write( DDR_REG_BASE +0x51bb6*4+0x02000000,0xb0a5); +reg_write( DDR_REG_BASE +0x51bb7*4+0x02000000,0x7b2e); +reg_write( DDR_REG_BASE +0x51bb8*4+0x02000000,0xe72); +reg_write( DDR_REG_BASE +0x51bb9*4+0x02000000,0xfe8f); +reg_write( DDR_REG_BASE +0x51bba*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x51bbb*4+0x02000000,0xe6e); +reg_write( DDR_REG_BASE +0x51bbc*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51bbd*4+0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x51bbe*4+0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x51bbf*4+0x02000000,0x7767); +reg_write( DDR_REG_BASE +0x51bc0*4+0x02000000,0x1901); +reg_write( DDR_REG_BASE +0x51bc1*4+0x02000000,0x92); +reg_write( DDR_REG_BASE +0x51bc2*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51bc3*4+0x02000000,0x1b01); +reg_write( DDR_REG_BASE +0x51bc4*4+0x02000000,0x1012); +reg_write( DDR_REG_BASE +0x51bc5*4+0x02000000,0xb8d); +reg_write( DDR_REG_BASE +0x51bc6*4+0x02000000,0xb013); +reg_write( DDR_REG_BASE +0x51bc7*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x51bc8*4+0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x51bc9*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51bca*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x51bcb*4+0x02000000,0x8f7); +reg_write( DDR_REG_BASE +0x51bcc*4+0x02000000,0x8033); +reg_write( DDR_REG_BASE +0x51bcd*4+0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x51bce*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51bcf*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51bd0*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51bd1*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51bd2*4+0x02000000,0x6901); +reg_write( DDR_REG_BASE +0x51bd3*4+0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x51bd4*4+0x02000000,0x7134); +reg_write( DDR_REG_BASE +0x51bd5*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51bd6*4+0x02000000,0x7002); +reg_write( DDR_REG_BASE +0x51bd7*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51bd8*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51bd9*4+0x02000000,0x51a); +reg_write( DDR_REG_BASE +0x51bda*4+0x02000000,0xffce); +reg_write( DDR_REG_BASE +0x51bdb*4+0x02000000,0xb62); +reg_write( DDR_REG_BASE +0x51bdc*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51bdd*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x51bde*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51bdf*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51be0*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51be1*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51be2*4+0x02000000,0xa901); +reg_write( DDR_REG_BASE +0x51be3*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51be4*4+0x02000000,0x7002); +reg_write( DDR_REG_BASE +0x51be5*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51be6*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51be7*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51be8*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51be9*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51bea*4+0x02000000,0x19); +reg_write( DDR_REG_BASE +0x51beb*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51bec*4+0x02000000,0x85c); +reg_write( DDR_REG_BASE +0x51bed*4+0x02000000,0x141); +reg_write( DDR_REG_BASE +0x51bee*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51bef*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51bf0*4+0x02000000,0xe174); +reg_write( DDR_REG_BASE +0x51bf1*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51bf2*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51bf3*4+0x02000000,0xe82); +reg_write( DDR_REG_BASE +0x51bf4*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51bf5*4+0x02000000,0xb021); +reg_write( DDR_REG_BASE +0x51bf6*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x51bf7*4+0x02000000,0x3a0d); +reg_write( DDR_REG_BASE +0x51bf8*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x51bf9*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x51bfa*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51bfb*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51bfc*4+0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x51bfd*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x51bfe*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x51bff*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51c00*4+0x02000000,0x9fe); +reg_write( DDR_REG_BASE +0x51c01*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51c02*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x51c03*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x51c04*4+0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x51c05*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51c06*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51c07*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x51c08*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x51c09*4+0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x51c0a*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x51c0b*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51c0c*4+0x02000000,0xabe); +reg_write( DDR_REG_BASE +0x51c0d*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51c0e*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x51c0f*4+0x02000000,0xbec1); +reg_write( DDR_REG_BASE +0x51c10*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51c11*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x51c12*4+0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x51c13*4+0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x51c14*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51c15*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x51c16*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51c17*4+0x02000000,0xaaa); +reg_write( DDR_REG_BASE +0x51c18*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51c19*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x51c1a*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x51c1b*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51c1c*4+0x02000000,0xa5e); +reg_write( DDR_REG_BASE +0x51c1d*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51c1e*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51c1f*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x51c20*4+0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x51c21*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51c22*4+0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x51c23*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x51c24*4+0x02000000,0xd858); +reg_write( DDR_REG_BASE +0x51c25*4+0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x51c26*4+0x02000000,0x88c0); +reg_write( DDR_REG_BASE +0x51c27*4+0x02000000,0x10cd); +reg_write( DDR_REG_BASE +0x51c28*4+0x02000000,0x808d); +reg_write( DDR_REG_BASE +0x51c29*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51c2a*4+0x02000000,0x9aa); +reg_write( DDR_REG_BASE +0x51c2b*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51c2c*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x51c2d*4+0x02000000,0x2605); +reg_write( DDR_REG_BASE +0x51c2e*4+0x02000000,0x1341); +reg_write( DDR_REG_BASE +0x51c2f*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51c30*4+0x02000000,0xb9c1); +reg_write( DDR_REG_BASE +0x51c31*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x51c32*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x51c33*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51c34*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x51c35*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51c36*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x51c37*4+0x02000000,0xda09); +reg_write( DDR_REG_BASE +0x51c38*4+0x02000000,0xa66); +reg_write( DDR_REG_BASE +0x51c39*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51c3a*4+0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x51c3b*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51c3c*4+0x02000000,0xa1e); +reg_write( DDR_REG_BASE +0x51c3d*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51c3e*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51c3f*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x51c40*4+0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x51c41*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51c42*4+0x02000000,0x21aa); +reg_write( DDR_REG_BASE +0x51c43*4+0x02000000,0xc4); +reg_write( DDR_REG_BASE +0x51c44*4+0x02000000,0x911); +reg_write( DDR_REG_BASE +0x51c45*4+0x02000000,0x3f); +reg_write( DDR_REG_BASE +0x51c46*4+0x02000000,0x722c); +reg_write( DDR_REG_BASE +0x51c47*4+0x02000000,0x21ab); +reg_write( DDR_REG_BASE +0x51c48*4+0x02000000,0xc4); +reg_write( DDR_REG_BASE +0x51c49*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51c4a*4+0x02000000,0x21ab); +reg_write( DDR_REG_BASE +0x51c4b*4+0x02000000,0xc4); +reg_write( DDR_REG_BASE +0x51c4c*4+0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x51c4d*4+0x02000000,0x415); +reg_write( DDR_REG_BASE +0x51c4e*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51c4f*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x51c50*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x51c51*4+0x02000000,0x1d6); +reg_write( DDR_REG_BASE +0x51c52*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51c53*4+0x02000000,0x21aa); +reg_write( DDR_REG_BASE +0x51c54*4+0x02000000,0x104); +reg_write( DDR_REG_BASE +0x51c55*4+0x02000000,0x7b32); +reg_write( DDR_REG_BASE +0x51c56*4+0x02000000,0xb19); +reg_write( DDR_REG_BASE +0x51c57*4+0x02000000,0x25); +reg_write( DDR_REG_BASE +0x51c58*4+0x02000000,0x24aa); +reg_write( DDR_REG_BASE +0x51c59*4+0x02000000,0x1144); +reg_write( DDR_REG_BASE +0x51c5a*4+0x02000000,0x22aa); +reg_write( DDR_REG_BASE +0x51c5b*4+0x02000000,0x104); +reg_write( DDR_REG_BASE +0x51c5c*4+0x02000000,0x9fd); +reg_write( DDR_REG_BASE +0x51c5d*4+0x02000000,0x8084); +reg_write( DDR_REG_BASE +0x51c5e*4+0x02000000,0x7862); +reg_write( DDR_REG_BASE +0x51c5f*4+0x02000000,0x24aa); +reg_write( DDR_REG_BASE +0x51c60*4+0x02000000,0x1144); +reg_write( DDR_REG_BASE +0x51c61*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x51c62*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51c63*4+0x02000000,0x21aa); +reg_write( DDR_REG_BASE +0x51c64*4+0x02000000,0x104); +reg_write( DDR_REG_BASE +0x51c65*4+0x02000000,0x7110); +reg_write( DDR_REG_BASE +0x51c66*4+0x02000000,0x20e1); +reg_write( DDR_REG_BASE +0x51c67*4+0x02000000,0x7c6); +reg_write( DDR_REG_BASE +0x51c68*4+0x02000000,0x22aa); +reg_write( DDR_REG_BASE +0x51c69*4+0x02000000,0x144); +reg_write( DDR_REG_BASE +0x51c6a*4+0x02000000,0xcf3); +reg_write( DDR_REG_BASE +0x51c6b*4+0x02000000,0x9080); +reg_write( DDR_REG_BASE +0x51c6c*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51c6d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51c6e*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x51c6f*4+0x02000000,0x866); +reg_write( DDR_REG_BASE +0x51c70*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51c71*4+0x02000000,0xfa6); +reg_write( DDR_REG_BASE +0x51c72*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x51c73*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x51c74*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51c75*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51c76*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x51c77*4+0x02000000,0xf5a); +reg_write( DDR_REG_BASE +0x51c78*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x51c79*4+0x02000000,0xf96); +reg_write( DDR_REG_BASE +0x51c7a*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51c7b*4+0x02000000,0xd814); +reg_write( DDR_REG_BASE +0x51c7c*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x51c7d*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51c7e*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x51c7f*4+0x02000000,0x846); +reg_write( DDR_REG_BASE +0x51c80*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51c81*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51c82*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51c83*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x51c84*4+0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x51c85*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51c86*4+0x02000000,0xe915); +reg_write( DDR_REG_BASE +0x51c87*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51c88*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51c89*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51c8a*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51c8b*4+0x02000000,0x923); +reg_write( DDR_REG_BASE +0x51c8c*4+0x02000000,0xdf); +reg_write( DDR_REG_BASE +0x51c8d*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51c8e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51c8f*4+0x02000000,0x7c8); +reg_write( DDR_REG_BASE +0x51c90*4+0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x51c91*4+0x02000000,0x917); +reg_write( DDR_REG_BASE +0x51c92*4+0x02000000,0x134); +reg_write( DDR_REG_BASE +0x51c93*4+0x02000000,0x216c); +reg_write( DDR_REG_BASE +0x51c94*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x51c95*4+0x02000000,0x2809); +reg_write( DDR_REG_BASE +0x51c96*4+0x02000000,0x8042); +reg_write( DDR_REG_BASE +0x51c97*4+0x02000000,0xf208); +reg_write( DDR_REG_BASE +0x51c98*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51c99*4+0x02000000,0x7842); +reg_write( DDR_REG_BASE +0x51c9a*4+0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x51c9b*4+0x02000000,0x809); +reg_write( DDR_REG_BASE +0x51c9c*4+0x02000000,0x115); +reg_write( DDR_REG_BASE +0x51c9d*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x51c9e*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x51c9f*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51ca0*4+0x02000000,0x246f); +reg_write( DDR_REG_BASE +0x51ca1*4+0x02000000,0x1343); +reg_write( DDR_REG_BASE +0x51ca2*4+0x02000000,0x9460); +reg_write( DDR_REG_BASE +0x51ca3*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x51ca4*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x51ca5*4+0x02000000,0x2a05); +reg_write( DDR_REG_BASE +0x51ca6*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x51ca7*4+0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x51ca8*4+0x02000000,0x8480); +reg_write( DDR_REG_BASE +0x51ca9*4+0x02000000,0x817); +reg_write( DDR_REG_BASE +0x51caa*4+0x02000000,0xf84); +reg_write( DDR_REG_BASE +0x51cab*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x51cac*4+0x02000000,0xd41); +reg_write( DDR_REG_BASE +0x51cad*4+0x02000000,0x2885); +reg_write( DDR_REG_BASE +0x51cae*4+0x02000000,0xa0f); +reg_write( DDR_REG_BASE +0x51caf*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x51cb0*4+0x02000000,0xc2); +reg_write( DDR_REG_BASE +0x51cb1*4+0x02000000,0x2a85); +reg_write( DDR_REG_BASE +0x51cb2*4+0x02000000,0x41f); +reg_write( DDR_REG_BASE +0x51cb3*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x51cb4*4+0x02000000,0x6a01); +reg_write( DDR_REG_BASE +0x51cb5*4+0x02000000,0x6941); +reg_write( DDR_REG_BASE +0x51cb6*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51cb7*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51cb8*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x51cb9*4+0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x51cba*4+0x02000000,0xe90c); +reg_write( DDR_REG_BASE +0x51cbb*4+0x02000000,0x14fb); +reg_write( DDR_REG_BASE +0x51cbc*4+0x02000000,0x9081); +reg_write( DDR_REG_BASE +0x51cbd*4+0x02000000,0x915); +reg_write( DDR_REG_BASE +0x51cbe*4+0x02000000,0xdf); +reg_write( DDR_REG_BASE +0x51cbf*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51cc0*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51cc1*4+0x02000000,0x7c8); +reg_write( DDR_REG_BASE +0x51cc2*4+0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x51cc3*4+0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x51cc4*4+0x02000000,0x22da); +reg_write( DDR_REG_BASE +0x51cc5*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x51cc6*4+0x02000000,0x7210); +reg_write( DDR_REG_BASE +0x51cc7*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x51cc8*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x51cc9*4+0x02000000,0x8d); +reg_write( DDR_REG_BASE +0x51cca*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51ccb*4+0x02000000,0xece); +reg_write( DDR_REG_BASE +0x51ccc*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51ccd*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x51cce*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51ccf*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51cd0*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51cd1*4+0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x51cd2*4+0x02000000,0xb9c3); +reg_write( DDR_REG_BASE +0x51cd3*4+0x02000000,0xdd58); +reg_write( DDR_REG_BASE +0x51cd4*4+0x02000000,0x1a02); +reg_write( DDR_REG_BASE +0x51cd5*4+0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x51cd6*4+0x02000000,0xbd9f); +reg_write( DDR_REG_BASE +0x51cd7*4+0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x51cd8*4+0x02000000,0xe80b); +reg_write( DDR_REG_BASE +0x51cd9*4+0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x51cda*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x51cdb*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51cdc*4+0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x51cdd*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51cde*4+0x02000000,0x57); +reg_write( DDR_REG_BASE +0x51cdf*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x51ce0*4+0x02000000,0xe00); +reg_write( DDR_REG_BASE +0x51ce1*4+0x02000000,0x621e); +reg_write( DDR_REG_BASE +0x51ce2*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x51ce3*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51ce4*4+0x02000000,0x708e); +reg_write( DDR_REG_BASE +0x51ce5*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51ce6*4+0x02000000,0x24); +reg_write( DDR_REG_BASE +0x51ce7*4+0x02000000,0xe96); +reg_write( DDR_REG_BASE +0x51ce8*4+0x02000000,0xff0f); +reg_write( DDR_REG_BASE +0x51ce9*4+0x02000000,0x79cf); +reg_write( DDR_REG_BASE +0x51cea*4+0x02000000,0x7b3d); +reg_write( DDR_REG_BASE +0x51ceb*4+0x02000000,0x7a3d); +reg_write( DDR_REG_BASE +0x51cec*4+0x02000000,0x2653); +reg_write( DDR_REG_BASE +0x51ced*4+0x02000000,0x907e); +reg_write( DDR_REG_BASE +0x51cee*4+0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x51cef*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51cf0*4+0x02000000,0x23c0); +reg_write( DDR_REG_BASE +0x51cf1*4+0x02000000,0x62); +reg_write( DDR_REG_BASE +0x51cf2*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51cf3*4+0x02000000,0x2653); +reg_write( DDR_REG_BASE +0x51cf4*4+0x02000000,0x9081); +reg_write( DDR_REG_BASE +0x51cf5*4+0x02000000,0xb8c3); +reg_write( DDR_REG_BASE +0x51cf6*4+0x02000000,0x22c0); +reg_write( DDR_REG_BASE +0x51cf7*4+0x02000000,0x62); +reg_write( DDR_REG_BASE +0x51cf8*4+0x02000000,0x1a03); +reg_write( DDR_REG_BASE +0x51cf9*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x51cfa*4+0x02000000,0x1a05); +reg_write( DDR_REG_BASE +0x51cfb*4+0x02000000,0x30c2); +reg_write( DDR_REG_BASE +0x51cfc*4+0x02000000,0x1a07); +reg_write( DDR_REG_BASE +0x51cfd*4+0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x51cfe*4+0x02000000,0x1a04); +reg_write( DDR_REG_BASE +0x51cff*4+0x02000000,0x3082); +reg_write( DDR_REG_BASE +0x51d00*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x51d01*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d02*4+0x02000000,0x53); +reg_write( DDR_REG_BASE +0x51d03*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x51d04*4+0x02000000,0xcb6); +reg_write( DDR_REG_BASE +0x51d05*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d06*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d07*4+0x02000000,0x276f); +reg_write( DDR_REG_BASE +0x51d08*4+0x02000000,0x10c3); +reg_write( DDR_REG_BASE +0x51d09*4+0x02000000,0x8f00); +reg_write( DDR_REG_BASE +0x51d0a*4+0x02000000,0xb8e2); +reg_write( DDR_REG_BASE +0x51d0b*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51d0c*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x51d0d*4+0x02000000,0xe1); +reg_write( DDR_REG_BASE +0x51d0e*4+0x02000000,0x1a08); +reg_write( DDR_REG_BASE +0x51d0f*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x51d10*4+0x02000000,0x1724); +reg_write( DDR_REG_BASE +0x51d11*4+0x02000000,0x1082); +reg_write( DDR_REG_BASE +0x51d12*4+0x02000000,0x170f); +reg_write( DDR_REG_BASE +0x51d13*4+0x02000000,0x1481); +reg_write( DDR_REG_BASE +0x51d14*4+0x02000000,0x2742); +reg_write( DDR_REG_BASE +0x51d15*4+0x02000000,0x1280); +reg_write( DDR_REG_BASE +0x51d16*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51d17*4+0x02000000,0x8d60); +reg_write( DDR_REG_BASE +0x51d18*4+0x02000000,0x97c0); +reg_write( DDR_REG_BASE +0x51d19*4+0x02000000,0x8f82); +reg_write( DDR_REG_BASE +0x51d1a*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x51d1b*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x51d1c*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d1d*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d1e*4+0x02000000,0x55); +reg_write( DDR_REG_BASE +0x51d1f*4+0x02000000,0x6); +reg_write( DDR_REG_BASE +0x51d20*4+0x02000000,0xc441); +reg_write( DDR_REG_BASE +0x51d21*4+0x02000000,0xc7e); +reg_write( DDR_REG_BASE +0x51d22*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d23*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x51d24*4+0x02000000,0x8f08); +reg_write( DDR_REG_BASE +0x51d25*4+0x02000000,0xe808); +reg_write( DDR_REG_BASE +0x51d26*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d27*4+0x02000000,0x5a); +reg_write( DDR_REG_BASE +0x51d28*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51d29*4+0x02000000,0xc6e); +reg_write( DDR_REG_BASE +0x51d2a*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d2b*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d2c*4+0x02000000,0xde32); +reg_write( DDR_REG_BASE +0x51d2d*4+0x02000000,0xbe9f); +reg_write( DDR_REG_BASE +0x51d2e*4+0x02000000,0x1601); +reg_write( DDR_REG_BASE +0x51d2f*4+0x02000000,0x1483); +reg_write( DDR_REG_BASE +0x51d30*4+0x02000000,0x16d1); +reg_write( DDR_REG_BASE +0x51d31*4+0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x51d32*4+0x02000000,0x1601); +reg_write( DDR_REG_BASE +0x51d33*4+0x02000000,0x148c); +reg_write( DDR_REG_BASE +0x51d34*4+0x02000000,0x1602); +reg_write( DDR_REG_BASE +0x51d35*4+0x02000000,0x1481); +reg_write( DDR_REG_BASE +0x51d36*4+0x02000000,0x1601); +reg_write( DDR_REG_BASE +0x51d37*4+0x02000000,0x1480); +reg_write( DDR_REG_BASE +0x51d38*4+0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51d39*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51d3a*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51d3b*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d3c*4+0x02000000,0x5b); +reg_write( DDR_REG_BASE +0x51d3d*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51d3e*4+0x02000000,0xc42); +reg_write( DDR_REG_BASE +0x51d3f*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d40*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d41*4+0x02000000,0x1601); +reg_write( DDR_REG_BASE +0x51d42*4+0x02000000,0x1483); +reg_write( DDR_REG_BASE +0x51d43*4+0x02000000,0x8e21); +reg_write( DDR_REG_BASE +0x51d44*4+0x02000000,0x8e04); +reg_write( DDR_REG_BASE +0x51d45*4+0x02000000,0x16cc); +reg_write( DDR_REG_BASE +0x51d46*4+0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x51d47*4+0x02000000,0x8e80); +reg_write( DDR_REG_BASE +0x51d48*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51d49*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51d4a*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d4b*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d4c*4+0x02000000,0x5c); +reg_write( DDR_REG_BASE +0x51d4d*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51d4e*4+0x02000000,0xc22); +reg_write( DDR_REG_BASE +0x51d4f*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d50*4+0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51d51*4+0x02000000,0x8f08); +reg_write( DDR_REG_BASE +0x51d52*4+0x02000000,0x8b5); +reg_write( DDR_REG_BASE +0x51d53*4+0x02000000,0x11); +reg_write( DDR_REG_BASE +0x51d54*4+0x02000000,0x8f15); +reg_write( DDR_REG_BASE +0x51d55*4+0x02000000,0x831); +reg_write( DDR_REG_BASE +0x51d56*4+0x02000000,0x7e); +reg_write( DDR_REG_BASE +0x51d57*4+0x02000000,0xdf3e); +reg_write( DDR_REG_BASE +0x51d58*4+0x02000000,0xf840); +reg_write( DDR_REG_BASE +0x51d59*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51d5a*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51d5b*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d5c*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d5d*4+0x02000000,0x5d); +reg_write( DDR_REG_BASE +0x51d5e*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51d5f*4+0x02000000,0xc02); +reg_write( DDR_REG_BASE +0x51d60*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d61*4+0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51d62*4+0x02000000,0xf841); +reg_write( DDR_REG_BASE +0x51d63*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51d64*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51d65*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d66*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d67*4+0x02000000,0x5e); +reg_write( DDR_REG_BASE +0x51d68*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51d69*4+0x02000000,0xbee); +reg_write( DDR_REG_BASE +0x51d6a*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d6b*4+0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51d6c*4+0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x51d6d*4+0x02000000,0x833); +reg_write( DDR_REG_BASE +0x51d6e*4+0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x51d6f*4+0x02000000,0xdf65); +reg_write( DDR_REG_BASE +0x51d70*4+0x02000000,0xf834); +reg_write( DDR_REG_BASE +0x51d71*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51d72*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51d73*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d74*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d75*4+0x02000000,0x5f); +reg_write( DDR_REG_BASE +0x51d76*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51d77*4+0x02000000,0xbd2); +reg_write( DDR_REG_BASE +0x51d78*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d79*4+0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51d7a*4+0x02000000,0xf835); +reg_write( DDR_REG_BASE +0x51d7b*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51d7c*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51d7d*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d7e*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d7f*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x51d80*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51d81*4+0x02000000,0xbbe); +reg_write( DDR_REG_BASE +0x51d82*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d83*4+0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51d84*4+0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x51d85*4+0x02000000,0x851); +reg_write( DDR_REG_BASE +0x51d86*4+0x02000000,0x7e); +reg_write( DDR_REG_BASE +0x51d87*4+0x02000000,0xdd71); +reg_write( DDR_REG_BASE +0x51d88*4+0x02000000,0xbd9f); +reg_write( DDR_REG_BASE +0x51d89*4+0x02000000,0x1501); +reg_write( DDR_REG_BASE +0x51d8a*4+0x02000000,0x1483); +reg_write( DDR_REG_BASE +0x51d8b*4+0x02000000,0x1501); +reg_write( DDR_REG_BASE +0x51d8c*4+0x02000000,0x148c); +reg_write( DDR_REG_BASE +0x51d8d*4+0x02000000,0x1502); +reg_write( DDR_REG_BASE +0x51d8e*4+0x02000000,0x1481); +reg_write( DDR_REG_BASE +0x51d8f*4+0x02000000,0x1501); +reg_write( DDR_REG_BASE +0x51d90*4+0x02000000,0x1480); +reg_write( DDR_REG_BASE +0x51d91*4+0x02000000,0x16cc); +reg_write( DDR_REG_BASE +0x51d92*4+0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x51d93*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51d94*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51d95*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d96*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d97*4+0x02000000,0x61); +reg_write( DDR_REG_BASE +0x51d98*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51d99*4+0x02000000,0xb8e); +reg_write( DDR_REG_BASE +0x51d9a*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d9b*4+0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51d9c*4+0x02000000,0x1501); +reg_write( DDR_REG_BASE +0x51d9d*4+0x02000000,0x1483); +reg_write( DDR_REG_BASE +0x51d9e*4+0x02000000,0x8d21); +reg_write( DDR_REG_BASE +0x51d9f*4+0x02000000,0x8d04); +reg_write( DDR_REG_BASE +0x51da0*4+0x02000000,0x16cc); +reg_write( DDR_REG_BASE +0x51da1*4+0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x51da2*4+0x02000000,0x8d80); +reg_write( DDR_REG_BASE +0x51da3*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51da4*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51da5*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51da6*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51da7*4+0x02000000,0x62); +reg_write( DDR_REG_BASE +0x51da8*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51da9*4+0x02000000,0xb6e); +reg_write( DDR_REG_BASE +0x51daa*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51dab*4+0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51dac*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51dad*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x51dae*4+0x02000000,0x1a0); +reg_write( DDR_REG_BASE +0x51daf*4+0x02000000,0x1802); +reg_write( DDR_REG_BASE +0x51db0*4+0x02000000,0x15); +reg_write( DDR_REG_BASE +0x51db1*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51db2*4+0x02000000,0x44); +reg_write( DDR_REG_BASE +0x51db3*4+0x02000000,0x1802); +reg_write( DDR_REG_BASE +0x51db4*4+0x02000000,0x54); +reg_write( DDR_REG_BASE +0x51db5*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51db6*4+0x02000000,0x144); +reg_write( DDR_REG_BASE +0x51db7*4+0x02000000,0x1802); +reg_write( DDR_REG_BASE +0x51db8*4+0x02000000,0x54); +reg_write( DDR_REG_BASE +0x51db9*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51dba*4+0x02000000,0x1c4); +reg_write( DDR_REG_BASE +0x51dbb*4+0x02000000,0x1804); +reg_write( DDR_REG_BASE +0x51dbc*4+0x02000000,0x54); +reg_write( DDR_REG_BASE +0x51dbd*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51dbe*4+0x02000000,0x88); +reg_write( DDR_REG_BASE +0x51dbf*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51dc0*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51dc1*4+0x02000000,0x288); +reg_write( DDR_REG_BASE +0x51dc2*4+0x02000000,0xb021); +reg_write( DDR_REG_BASE +0x51dc3*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51dc4*4+0x02000000,0x2c8); +reg_write( DDR_REG_BASE +0x51dc5*4+0x02000000,0xb022); +reg_write( DDR_REG_BASE +0x51dc6*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x51dc7*4+0x02000000,0x3cc); +reg_write( DDR_REG_BASE +0x51dc8*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51dc9*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x51dca*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x51dcb*4+0x02000000,0xe180); +reg_write( DDR_REG_BASE +0x51dcc*4+0x02000000,0xd934); +reg_write( DDR_REG_BASE +0x51dcd*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51dce*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x51dcf*4+0x02000000,0xe0ee); +reg_write( DDR_REG_BASE +0x51dd0*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51dd1*4+0x02000000,0xd4e); +reg_write( DDR_REG_BASE +0x51dd2*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51dd3*4+0x02000000,0x18fc); +reg_write( DDR_REG_BASE +0x51dd4*4+0x02000000,0x8105); +reg_write( DDR_REG_BASE +0x51dd5*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x51dd6*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51dd7*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51dd8*4+0x02000000,0xbf9f); +reg_write( DDR_REG_BASE +0x51dd9*4+0x02000000,0x1701); +reg_write( DDR_REG_BASE +0x51dda*4+0x02000000,0x1483); +reg_write( DDR_REG_BASE +0x51ddb*4+0x02000000,0x1701); +reg_write( DDR_REG_BASE +0x51ddc*4+0x02000000,0x148c); +reg_write( DDR_REG_BASE +0x51ddd*4+0x02000000,0x1702); +reg_write( DDR_REG_BASE +0x51dde*4+0x02000000,0x1481); +reg_write( DDR_REG_BASE +0x51ddf*4+0x02000000,0x1701); +reg_write( DDR_REG_BASE +0x51de0*4+0x02000000,0x1480); +reg_write( DDR_REG_BASE +0x51de1*4+0x02000000,0x16cc); +reg_write( DDR_REG_BASE +0x51de2*4+0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x51de3*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51de4*4+0x02000000,0x1701); +reg_write( DDR_REG_BASE +0x51de5*4+0x02000000,0x1483); +reg_write( DDR_REG_BASE +0x51de6*4+0x02000000,0x8f21); +reg_write( DDR_REG_BASE +0x51de7*4+0x02000000,0x8f04); +reg_write( DDR_REG_BASE +0x51de8*4+0x02000000,0x16cc); +reg_write( DDR_REG_BASE +0x51de9*4+0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x51dea*4+0x02000000,0x8f80); +reg_write( DDR_REG_BASE +0x51deb*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51dec*4+0x02000000,0x621a); +reg_write( DDR_REG_BASE +0x51ded*4+0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x51dee*4+0x02000000,0x1801); +reg_write( DDR_REG_BASE +0x51def*4+0x02000000,0x52); +reg_write( DDR_REG_BASE +0x51df0*4+0x02000000,0x8fd); +reg_write( DDR_REG_BASE +0x51df1*4+0x02000000,0x8084); +reg_write( DDR_REG_BASE +0x51df2*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51df3*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51df4*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51df5*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51df6*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51df7*4+0x02000000,0xc1a7); +reg_write( DDR_REG_BASE +0x51df8*4+0x02000000,0xda07); +reg_write( DDR_REG_BASE +0x51df9*4+0x02000000,0xba8c); +reg_write( DDR_REG_BASE +0x51dfa*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51dfb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51dfc*4+0x02000000,0x9f38); +reg_write( DDR_REG_BASE +0x51dfd*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x51dfe*4+0x02000000,0x9012); +reg_write( DDR_REG_BASE +0x51dff*4+0x02000000,0x328); +reg_write( DDR_REG_BASE +0x51e00*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51e01*4+0x02000000,0x7084); +reg_write( DDR_REG_BASE +0x51e02*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e03*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x51e04*4+0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x51e05*4+0x02000000,0xd858); +reg_write( DDR_REG_BASE +0x51e06*4+0x02000000,0xb501); +reg_write( DDR_REG_BASE +0x51e07*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51e08*4+0x02000000,0xb8); +reg_write( DDR_REG_BASE +0x51e09*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51e0a*4+0x02000000,0xaaa); +reg_write( DDR_REG_BASE +0x51e0b*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51e0c*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51e0d*4+0x02000000,0xcc20); +reg_write( DDR_REG_BASE +0x51e0e*4+0x02000000,0x9520); +reg_write( DDR_REG_BASE +0x51e0f*4+0x02000000,0x7030); +reg_write( DDR_REG_BASE +0x51e10*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51e11*4+0x02000000,0xf406); +reg_write( DDR_REG_BASE +0x51e12*4+0x02000000,0xcc21); +reg_write( DDR_REG_BASE +0x51e13*4+0x02000000,0x9521); +reg_write( DDR_REG_BASE +0x51e14*4+0x02000000,0x2038); +reg_write( DDR_REG_BASE +0x51e15*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x51e16*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51e17*4+0x02000000,0xb9); +reg_write( DDR_REG_BASE +0x51e18*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51e19*4+0x02000000,0xd22); +reg_write( DDR_REG_BASE +0x51e1a*4+0x02000000,0xfe0f); +reg_write( DDR_REG_BASE +0x51e1b*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51e1c*4+0x02000000,0x7043); +reg_write( DDR_REG_BASE +0x51e1d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e1e*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x51e1f*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51e20*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51e21*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e22*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51e23*4+0x02000000,0x1a00); +reg_write( DDR_REG_BASE +0x51e24*4+0x02000000,0x3103); +reg_write( DDR_REG_BASE +0x51e25*4+0x02000000,0x216f); +reg_write( DDR_REG_BASE +0x51e26*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x51e27*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51e28*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x51e29*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51e2a*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51e2b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51e2c*4+0x02000000,0x9126); +reg_write( DDR_REG_BASE +0x51e2d*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51e2e*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51e2f*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51e30*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51e31*4+0x02000000,0x32); +reg_write( DDR_REG_BASE +0x51e32*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x51e33*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51e34*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x51e35*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51e36*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51e37*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51e38*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51e39*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x51e3a*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51e3b*4+0x02000000,0xa46); +reg_write( DDR_REG_BASE +0x51e3c*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51e3d*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x51e3e*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51e3f*4+0x02000000,0xb8e0); +reg_write( DDR_REG_BASE +0x51e40*4+0x02000000,0x264); +reg_write( DDR_REG_BASE +0x51e41*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51e42*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51e43*4+0x02000000,0xc103); +reg_write( DDR_REG_BASE +0x51e44*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51e45*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51e46*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x51e47*4+0x02000000,0xe032); +reg_write( DDR_REG_BASE +0x51e48*4+0x02000000,0xb980); +reg_write( DDR_REG_BASE +0x51e49*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51e4a*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51e4b*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51e4c*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51e4d*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51e4e*4+0x02000000,0xe090); +reg_write( DDR_REG_BASE +0x51e4f*4+0x02000000,0xca2); +reg_write( DDR_REG_BASE +0x51e50*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51e51*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x51e52*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51e53*4+0x02000000,0x256f); +reg_write( DDR_REG_BASE +0x51e54*4+0x02000000,0x1cc3); +reg_write( DDR_REG_BASE +0x51e55*4+0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x51e56*4+0x02000000,0xe885); +reg_write( DDR_REG_BASE +0x51e57*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51e58*4+0x02000000,0x7085); +reg_write( DDR_REG_BASE +0x51e59*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51e5a*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x51e5b*4+0x02000000,0xce2); +reg_write( DDR_REG_BASE +0x51e5c*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x51e5d*4+0x02000000,0xf92); +reg_write( DDR_REG_BASE +0x51e5e*4+0x02000000,0xff0f); +reg_write( DDR_REG_BASE +0x51e5f*4+0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x51e60*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51e61*4+0x02000000,0xf4bb); +reg_write( DDR_REG_BASE +0x51e62*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51e63*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x51e64*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e65*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51e66*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51e67*4+0x02000000,0x708b); +reg_write( DDR_REG_BASE +0x51e68*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e69*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51e6a*4+0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x51e6b*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x51e6c*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51e6d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51e6e*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x51e6f*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51e70*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51e71*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51e72*4+0x02000000,0x86); +reg_write( DDR_REG_BASE +0x51e73*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51e74*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x51e75*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51e76*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51e77*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51e78*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51e79*4+0x02000000,0xb8c2); +reg_write( DDR_REG_BASE +0x51e7a*4+0x02000000,0x825); +reg_write( DDR_REG_BASE +0x51e7b*4+0x02000000,0x90); +reg_write( DDR_REG_BASE +0x51e7c*4+0x02000000,0x833); +reg_write( DDR_REG_BASE +0x51e7d*4+0x02000000,0xf1); +reg_write( DDR_REG_BASE +0x51e7e*4+0x02000000,0x238b); +reg_write( DDR_REG_BASE +0x51e7f*4+0x02000000,0x903e); +reg_write( DDR_REG_BASE +0x51e80*4+0x02000000,0xce08); +reg_write( DDR_REG_BASE +0x51e81*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51e82*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e83*4+0x02000000,0x41c); +reg_write( DDR_REG_BASE +0x51e84*4+0x02000000,0x761c); +reg_write( DDR_REG_BASE +0x51e85*4+0x02000000,0x1a03); +reg_write( DDR_REG_BASE +0x51e86*4+0x02000000,0x3398); +reg_write( DDR_REG_BASE +0x51e87*4+0x02000000,0xce0e); +reg_write( DDR_REG_BASE +0x51e88*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x51e89*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e8a*4+0x02000000,0x434); +reg_write( DDR_REG_BASE +0x51e8b*4+0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x51e8c*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51e8d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e8e*4+0x02000000,0x418); +reg_write( DDR_REG_BASE +0x51e8f*4+0x02000000,0x1a03); +reg_write( DDR_REG_BASE +0x51e90*4+0x02000000,0x3398); +reg_write( DDR_REG_BASE +0x51e91*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x51e92*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e93*4+0x02000000,0x430); +reg_write( DDR_REG_BASE +0x51e94*4+0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x51e95*4+0x02000000,0x238b); +reg_write( DDR_REG_BASE +0x51e96*4+0x02000000,0x903e); +reg_write( DDR_REG_BASE +0x51e97*4+0x02000000,0xce05); +reg_write( DDR_REG_BASE +0x51e98*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51e99*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e9a*4+0x02000000,0x410); +reg_write( DDR_REG_BASE +0x51e9b*4+0x02000000,0x761c); +reg_write( DDR_REG_BASE +0x51e9c*4+0x02000000,0xce0b); +reg_write( DDR_REG_BASE +0x51e9d*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x51e9e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e9f*4+0x02000000,0x428); +reg_write( DDR_REG_BASE +0x51ea0*4+0x02000000,0x1a03); +reg_write( DDR_REG_BASE +0x51ea1*4+0x02000000,0x3398); +reg_write( DDR_REG_BASE +0x51ea2*4+0x02000000,0x771c); +reg_write( DDR_REG_BASE +0x51ea3*4+0x02000000,0x1a09); +reg_write( DDR_REG_BASE +0x51ea4*4+0x02000000,0x33d8); +reg_write( DDR_REG_BASE +0x51ea5*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51ea6*4+0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x51ea7*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51ea8*4+0x02000000,0xc); +reg_write( DDR_REG_BASE +0x51ea9*4+0x02000000,0x238b); +reg_write( DDR_REG_BASE +0x51eaa*4+0x02000000,0x903e); +reg_write( DDR_REG_BASE +0x51eab*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x51eac*4+0x02000000,0xf9b); +reg_write( DDR_REG_BASE +0x51ead*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51eae*4+0x02000000,0x86a0); +reg_write( DDR_REG_BASE +0x51eaf*4+0x02000000,0xf20b); +reg_write( DDR_REG_BASE +0x51eb0*4+0x02000000,0x233c); +reg_write( DDR_REG_BASE +0x51eb1*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x51eb2*4+0x02000000,0xa6); +reg_write( DDR_REG_BASE +0x51eb3*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x51eb4*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51eb5*4+0x02000000,0x141); +reg_write( DDR_REG_BASE +0x51eb6*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51eb7*4+0x02000000,0xbe6); +reg_write( DDR_REG_BASE +0x51eb8*4+0x02000000,0xfe0f); +reg_write( DDR_REG_BASE +0x51eb9*4+0x02000000,0x222f); +reg_write( DDR_REG_BASE +0x51eba*4+0x02000000,0x6c2); +reg_write( DDR_REG_BASE +0x51ebb*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51ebc*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51ebd*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51ebe*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51ebf*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51ec0*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51ec1*4+0x02000000,0xed95); +reg_write( DDR_REG_BASE +0x51ec2*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51ec3*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x51ec4*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x51ec5*4+0x02000000,0x6611); +reg_write( DDR_REG_BASE +0x51ec6*4+0x02000000,0x6710); +reg_write( DDR_REG_BASE +0x51ec7*4+0x02000000,0x4a10); +reg_write( DDR_REG_BASE +0x51ec8*4+0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x51ec9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51eca*4+0x02000000,0x2805); +reg_write( DDR_REG_BASE +0x51ecb*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x51ecc*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51ecd*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51ece*4+0x02000000,0xfe80); +reg_write( DDR_REG_BASE +0x51ecf*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51ed0*4+0x02000000,0x2089); +reg_write( DDR_REG_BASE +0x51ed1*4+0x02000000,0xfc1); +reg_write( DDR_REG_BASE +0x51ed2*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x51ed3*4+0x02000000,0x19e0); +reg_write( DDR_REG_BASE +0x51ed4*4+0x02000000,0x8004); +reg_write( DDR_REG_BASE +0x51ed5*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x51ed6*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x51ed7*4+0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x51ed8*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x51ed9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51eda*4+0x02000000,0x2b05); +reg_write( DDR_REG_BASE +0x51edb*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x51edc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51edd*4+0x02000000,0xfa00); +reg_write( DDR_REG_BASE +0x51ede*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x51edf*4+0x02000000,0x821); +reg_write( DDR_REG_BASE +0x51ee0*4+0x02000000,0x1fe); +reg_write( DDR_REG_BASE +0x51ee1*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x51ee2*4+0x02000000,0x2200); +reg_write( DDR_REG_BASE +0x51ee3*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51ee4*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x51ee5*4+0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x51ee6*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x51ee7*4+0x02000000,0x8d47); +reg_write( DDR_REG_BASE +0x51ee8*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x51ee9*4+0x02000000,0xf685); +reg_write( DDR_REG_BASE +0x51eea*4+0x02000000,0x2885); +reg_write( DDR_REG_BASE +0x51eeb*4+0x02000000,0xd07); +reg_write( DDR_REG_BASE +0x51eec*4+0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x51eed*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51eee*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51eef*4+0x02000000,0x2089); +reg_write( DDR_REG_BASE +0x51ef0*4+0x02000000,0xfc1); +reg_write( DDR_REG_BASE +0x51ef1*4+0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x51ef2*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x51ef3*4+0x02000000,0xc105); +reg_write( DDR_REG_BASE +0x51ef4*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x51ef5*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x51ef6*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x51ef7*4+0x02000000,0xe164); +reg_write( DDR_REG_BASE +0x51ef8*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51ef9*4+0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x51efa*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51efb*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x51efc*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51efd*4+0x02000000,0x164); +reg_write( DDR_REG_BASE +0x51efe*4+0x02000000,0xb8c1); +reg_write( DDR_REG_BASE +0x51eff*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x51f00*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x51f01*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51f02*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51f03*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51f04*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51f05*4+0x02000000,0x86); +reg_write( DDR_REG_BASE +0x51f06*4+0x02000000,0x952); +reg_write( DDR_REG_BASE +0x51f07*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51f08*4+0x02000000,0x90c0); +reg_write( DDR_REG_BASE +0x51f09*4+0x02000000,0x8e2); +reg_write( DDR_REG_BASE +0x51f0a*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51f0b*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x51f0c*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51f0d*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51f0e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51f0f*4+0x02000000,0x1f); +reg_write( DDR_REG_BASE +0x51f10*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x51f11*4+0x02000000,0x2111); +reg_write( DDR_REG_BASE +0x51f12*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51f13*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51f14*4+0x02000000,0x26cf); +reg_write( DDR_REG_BASE +0x51f15*4+0x02000000,0x1021); +reg_write( DDR_REG_BASE +0x51f16*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51f17*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51f18*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51f19*4+0x02000000,0xfe86); +reg_write( DDR_REG_BASE +0x51f1a*4+0x02000000,0xb0c0); +reg_write( DDR_REG_BASE +0x51f1b*4+0x02000000,0xb2a); +reg_write( DDR_REG_BASE +0x51f1c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51f1d*4+0x02000000,0xb4a); +reg_write( DDR_REG_BASE +0x51f1e*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x51f1f*4+0x02000000,0x8fe); +reg_write( DDR_REG_BASE +0x51f20*4+0x02000000,0xfe8f); +reg_write( DDR_REG_BASE +0x51f21*4+0x02000000,0xc52); +reg_write( DDR_REG_BASE +0x51f22*4+0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x51f23*4+0x02000000,0xca04); +reg_write( DDR_REG_BASE +0x51f24*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51f25*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x51f26*4+0x02000000,0xf033); +reg_write( DDR_REG_BASE +0x51f27*4+0x02000000,0x245a); +reg_write( DDR_REG_BASE +0x51f28*4+0x02000000,0x149e); +reg_write( DDR_REG_BASE +0x51f29*4+0x02000000,0x2600); +reg_write( DDR_REG_BASE +0x51f2a*4+0x02000000,0x3f83); +reg_write( DDR_REG_BASE +0x51f2b*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51f2c*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x51f2d*4+0x02000000,0xb341); +reg_write( DDR_REG_BASE +0x51f2e*4+0x02000000,0xf028); +reg_write( DDR_REG_BASE +0x51f2f*4+0x02000000,0x241a); +reg_write( DDR_REG_BASE +0x51f30*4+0x02000000,0x1f81); +reg_write( DDR_REG_BASE +0x51f31*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51f32*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x51f33*4+0x02000000,0x79a5); +reg_write( DDR_REG_BASE +0x51f34*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x51f35*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x51f36*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51f37*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51f38*4+0x02000000,0x140); +reg_write( DDR_REG_BASE +0x51f39*4+0x02000000,0x9120); +reg_write( DDR_REG_BASE +0x51f3a*4+0x02000000,0x7e2f); +reg_write( DDR_REG_BASE +0x51f3b*4+0x02000000,0xd13); +reg_write( DDR_REG_BASE +0x51f3c*4+0x02000000,0x13a1); +reg_write( DDR_REG_BASE +0x51f3d*4+0x02000000,0xbec4); +reg_write( DDR_REG_BASE +0x51f3e*4+0x02000000,0x8b22); +reg_write( DDR_REG_BASE +0x51f3f*4+0x02000000,0x210f); +reg_write( DDR_REG_BASE +0x51f40*4+0x02000000,0x341); +reg_write( DDR_REG_BASE +0x51f41*4+0x02000000,0xab22); +reg_write( DDR_REG_BASE +0x51f42*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x51f43*4+0x02000000,0x8b23); +reg_write( DDR_REG_BASE +0x51f44*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x51f45*4+0x02000000,0xab23); +reg_write( DDR_REG_BASE +0x51f46*4+0x02000000,0x792f); +reg_write( DDR_REG_BASE +0x51f47*4+0x02000000,0x2614); +reg_write( DDR_REG_BASE +0x51f48*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x51f49*4+0x02000000,0x2100); +reg_write( DDR_REG_BASE +0x51f4a*4+0x02000000,0xf8f); +reg_write( DDR_REG_BASE +0x51f4b*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51f4c*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x51f4d*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51f4e*4+0x02000000,0xafa3); +reg_write( DDR_REG_BASE +0x51f4f*4+0x02000000,0xee06); +reg_write( DDR_REG_BASE +0x51f50*4+0x02000000,0xbe61); +reg_write( DDR_REG_BASE +0x51f51*4+0x02000000,0xe01); +reg_write( DDR_REG_BASE +0x51f52*4+0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x51f53*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x51f54*4+0x02000000,0xaf22); +reg_write( DDR_REG_BASE +0x51f55*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x51f56*4+0x02000000,0xdb3); +reg_write( DDR_REG_BASE +0x51f57*4+0x02000000,0x9214); +reg_write( DDR_REG_BASE +0x51f58*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x51f59*4+0x02000000,0xc9f); +reg_write( DDR_REG_BASE +0x51f5a*4+0x02000000,0x9024); +reg_write( DDR_REG_BASE +0x51f5b*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x51f5c*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51f5d*4+0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x51f5e*4+0x02000000,0x33f); +reg_write( DDR_REG_BASE +0x51f5f*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51f60*4+0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x51f61*4+0x02000000,0xbd2); +reg_write( DDR_REG_BASE +0x51f62*4+0x02000000,0xfe0f); +reg_write( DDR_REG_BASE +0x51f63*4+0x02000000,0xabe); +reg_write( DDR_REG_BASE +0x51f64*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51f65*4+0x02000000,0xd80d); +reg_write( DDR_REG_BASE +0x51f66*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51f67*4+0x02000000,0xfc6); +reg_write( DDR_REG_BASE +0x51f68*4+0x02000000,0x180); +reg_write( DDR_REG_BASE +0x51f69*4+0x02000000,0xee2); +reg_write( DDR_REG_BASE +0x51f6a*4+0x02000000,0xfe4f); +reg_write( DDR_REG_BASE +0x51f6b*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51f6c*4+0x02000000,0x7003); +reg_write( DDR_REG_BASE +0x51f6d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51f6e*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x51f6f*4+0x02000000,0xaa6); +reg_write( DDR_REG_BASE +0x51f70*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51f71*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51f72*4+0x02000000,0xca04); +reg_write( DDR_REG_BASE +0x51f73*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x51f74*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x51f75*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x51f76*4+0x02000000,0xf019); +reg_write( DDR_REG_BASE +0x51f77*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51f78*4+0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x51f79*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x51f7a*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51f7b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51f7c*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x51f7d*4+0x02000000,0x2300); +reg_write( DDR_REG_BASE +0x51f7e*4+0x02000000,0x1f8d); +reg_write( DDR_REG_BASE +0x51f7f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51f80*4+0x02000000,0x7f0); +reg_write( DDR_REG_BASE +0x51f81*4+0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x51f82*4+0x02000000,0x7945); +reg_write( DDR_REG_BASE +0x51f83*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x51f84*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x51f85*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51f86*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51f87*4+0x02000000,0x140); +reg_write( DDR_REG_BASE +0x51f88*4+0x02000000,0x9180); +reg_write( DDR_REG_BASE +0x51f89*4+0x02000000,0xad80); +reg_write( DDR_REG_BASE +0x51f8a*4+0x02000000,0xb140); +reg_write( DDR_REG_BASE +0x51f8b*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x51f8c*4+0x02000000,0xadb); +reg_write( DDR_REG_BASE +0x51f8d*4+0x02000000,0x8214); +reg_write( DDR_REG_BASE +0x51f8e*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x51f8f*4+0x02000000,0xbd3); +reg_write( DDR_REG_BASE +0x51f90*4+0x02000000,0x8024); +reg_write( DDR_REG_BASE +0x51f91*4+0x02000000,0x2616); +reg_write( DDR_REG_BASE +0x51f92*4+0x02000000,0x30cb); +reg_write( DDR_REG_BASE +0x51f93*4+0x02000000,0xbde); +reg_write( DDR_REG_BASE +0x51f94*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51f95*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51f96*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51f97*4+0x02000000,0x813); +reg_write( DDR_REG_BASE +0x51f98*4+0x02000000,0xbe); +reg_write( DDR_REG_BASE +0x51f99*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51f9a*4+0x02000000,0xbaa); +reg_write( DDR_REG_BASE +0x51f9b*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x51f9c*4+0x02000000,0xa4a); +reg_write( DDR_REG_BASE +0x51f9d*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51f9e*4+0x02000000,0x720c); +reg_write( DDR_REG_BASE +0x51f9f*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51fa0*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x51fa1*4+0x02000000,0x808e); +reg_write( DDR_REG_BASE +0x51fa2*4+0x02000000,0xf207); +reg_write( DDR_REG_BASE +0x51fa3*4+0x02000000,0xb9a); +reg_write( DDR_REG_BASE +0x51fa4*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51fa5*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51fa6*4+0x02000000,0xa36); +reg_write( DDR_REG_BASE +0x51fa7*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51fa8*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51fa9*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51faa*4+0x02000000,0x81b); +reg_write( DDR_REG_BASE +0x51fab*4+0x02000000,0x21e); +reg_write( DDR_REG_BASE +0x51fac*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51fad*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51fae*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51faf*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51fb0*4+0x02000000,0xe887); +reg_write( DDR_REG_BASE +0x51fb1*4+0x02000000,0xb7e); +reg_write( DDR_REG_BASE +0x51fb2*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51fb3*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x51fb4*4+0x02000000,0xa1a); +reg_write( DDR_REG_BASE +0x51fb5*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51fb6*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51fb7*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51fb8*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x51fb9*4+0x02000000,0x820d); +reg_write( DDR_REG_BASE +0x51fba*4+0x02000000,0xf207); +reg_write( DDR_REG_BASE +0x51fbb*4+0x02000000,0xb6a); +reg_write( DDR_REG_BASE +0x51fbc*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51fbd*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x51fbe*4+0x02000000,0xa06); +reg_write( DDR_REG_BASE +0x51fbf*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51fc0*4+0x02000000,0xd8fd); +reg_write( DDR_REG_BASE +0x51fc1*4+0x02000000,0xee08); +reg_write( DDR_REG_BASE +0x51fc2*4+0x02000000,0xb5a); +reg_write( DDR_REG_BASE +0x51fc3*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51fc4*4+0x02000000,0x720c); +reg_write( DDR_REG_BASE +0x51fc5*4+0x02000000,0x9fa); +reg_write( DDR_REG_BASE +0x51fc6*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51fc7*4+0x02000000,0xd8fe); +reg_write( DDR_REG_BASE +0x51fc8*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51fc9*4+0x02000000,0x813); +reg_write( DDR_REG_BASE +0x51fca*4+0x02000000,0x13e); +reg_write( DDR_REG_BASE +0x51fcb*4+0x02000000,0x760c); +reg_write( DDR_REG_BASE +0x51fcc*4+0x02000000,0xb46); +reg_write( DDR_REG_BASE +0x51fcd*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x51fce*4+0x02000000,0x9e6); +reg_write( DDR_REG_BASE +0x51fcf*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51fd0*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x51fd1*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51fd2*4+0x02000000,0x815); +reg_write( DDR_REG_BASE +0x51fd3*4+0x02000000,0x51); +reg_write( DDR_REG_BASE +0x51fd4*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51fd5*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51fd6*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51fd7*4+0x02000000,0x19); +reg_write( DDR_REG_BASE +0x51fd8*4+0x02000000,0xe884); +reg_write( DDR_REG_BASE +0x51fd9*4+0x02000000,0xb2e); +reg_write( DDR_REG_BASE +0x51fda*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51fdb*4+0x02000000,0xd80d); +reg_write( DDR_REG_BASE +0x51fdc*4+0x02000000,0xed07); +reg_write( DDR_REG_BASE +0x51fdd*4+0x02000000,0xb26); +reg_write( DDR_REG_BASE +0x51fde*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51fdf*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x51fe0*4+0x02000000,0x9c2); +reg_write( DDR_REG_BASE +0x51fe1*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51fe2*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x51fe3*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51fe4*4+0x02000000,0x825); +reg_write( DDR_REG_BASE +0x51fe5*4+0x02000000,0x27f); +reg_write( DDR_REG_BASE +0x51fe6*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x51fe7*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51fe8*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51fe9*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51fea*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51feb*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x51fec*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51fed*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51fee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51fef*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51ff0*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51ff1*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51ff2*4+0x02000000,0xe040); +reg_write( DDR_REG_BASE +0x51ff3*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x51ff4*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x51ff5*4+0x02000000,0xf040); +reg_write( DDR_REG_BASE +0x51ff6*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51ff7*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51ff8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51ff9*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51ffa*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51ffb*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51ffc*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51ffd*4+0x02000000,0xb8e2); +reg_write( DDR_REG_BASE +0x51ffe*4+0x02000000,0x25ca); +reg_write( DDR_REG_BASE +0x51fff*4+0x02000000,0x13e1); +reg_write( DDR_REG_BASE +0x52000*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52001*4+0x02000000,0xae00); +reg_write( DDR_REG_BASE +0x52002*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52003*4+0x02000000,0x84f); +reg_write( DDR_REG_BASE +0x52004*4+0x02000000,0x95); +reg_write( DDR_REG_BASE +0x52005*4+0x02000000,0xe81d); +reg_write( DDR_REG_BASE +0x52006*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52007*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x52008*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52009*4+0x02000000,0x58); +reg_write( DDR_REG_BASE +0x5200a*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x5200b*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5200c*4+0x02000000,0xf213); +reg_write( DDR_REG_BASE +0x5200d*4+0x02000000,0xe76); +reg_write( DDR_REG_BASE +0x5200e*4+0x02000000,0xfe4f); +reg_write( DDR_REG_BASE +0x5200f*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x52010*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52011*4+0x02000000,0xaf6); +reg_write( DDR_REG_BASE +0x52012*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52013*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52014*4+0x02000000,0xd8a); +reg_write( DDR_REG_BASE +0x52015*4+0x02000000,0xfe4f); +reg_write( DDR_REG_BASE +0x52016*4+0x02000000,0xdc2); +reg_write( DDR_REG_BASE +0x52017*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x52018*4+0x02000000,0x1e01); +reg_write( DDR_REG_BASE +0x52019*4+0x02000000,0x1003); +reg_write( DDR_REG_BASE +0x5201a*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x5201b*4+0x02000000,0xdf6); +reg_write( DDR_REG_BASE +0x5201c*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x5201d*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x5201e*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x5201f*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52020*4+0x02000000,0xf1e1); +reg_write( DDR_REG_BASE +0x52021*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52022*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x52023*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52024*4+0x02000000,0x25); +reg_write( DDR_REG_BASE +0x52025*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52026*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52027*4+0x02000000,0xf5e7); +reg_write( DDR_REG_BASE +0x52028*4+0x02000000,0xf1f7); +reg_write( DDR_REG_BASE +0x52029*4+0x02000000,0xac6); +reg_write( DDR_REG_BASE +0x5202a*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x5202b*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x5202c*4+0x02000000,0xca09); +reg_write( DDR_REG_BASE +0x5202d*4+0x02000000,0xe885); +reg_write( DDR_REG_BASE +0x5202e*4+0x02000000,0x93e); +reg_write( DDR_REG_BASE +0x5202f*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52030*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52031*4+0x02000000,0x922); +reg_write( DDR_REG_BASE +0x52032*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52033*4+0x02000000,0xd809); +reg_write( DDR_REG_BASE +0x52034*4+0x02000000,0xca09); +reg_write( DDR_REG_BASE +0x52035*4+0x02000000,0xe837); +reg_write( DDR_REG_BASE +0x52036*4+0x02000000,0xd925); +reg_write( DDR_REG_BASE +0x52037*4+0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x52038*4+0x02000000,0x8900); +reg_write( DDR_REG_BASE +0x52039*4+0x02000000,0x1133); +reg_write( DDR_REG_BASE +0x5203a*4+0x02000000,0x8f); +reg_write( DDR_REG_BASE +0x5203b*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x5203c*4+0x02000000,0x7f05); +reg_write( DDR_REG_BASE +0x5203d*4+0x02000000,0xf022); +reg_write( DDR_REG_BASE +0x5203e*4+0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x5203f*4+0x02000000,0x17c1); +reg_write( DDR_REG_BASE +0x52040*4+0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x52041*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x52042*4+0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x52043*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x52044*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52045*4+0x02000000,0x78eb); +reg_write( DDR_REG_BASE +0x52046*4+0x02000000,0xf217); +reg_write( DDR_REG_BASE +0x52047*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52048*4+0x02000000,0xdda); +reg_write( DDR_REG_BASE +0x52049*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x5204a*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5204b*4+0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x5204c*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x5204d*4+0x02000000,0x7bcf); +reg_write( DDR_REG_BASE +0x5204e*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5204f*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x52050*4+0x02000000,0x93a); +reg_write( DDR_REG_BASE +0x52051*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52052*4+0x02000000,0x4378); +reg_write( DDR_REG_BASE +0x52053*4+0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x52054*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52055*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x52056*4+0x02000000,0x92e); +reg_write( DDR_REG_BASE +0x52057*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52058*4+0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x52059*4+0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x5205a*4+0x02000000,0x9da); +reg_write( DDR_REG_BASE +0x5205b*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x5205c*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x5205d*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x5205e*4+0x02000000,0xec1); +reg_write( DDR_REG_BASE +0x5205f*4+0x02000000,0x90b4); +reg_write( DDR_REG_BASE +0x52060*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52061*4+0x02000000,0x8da); +reg_write( DDR_REG_BASE +0x52062*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52063*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52064*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52065*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x52066*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52067*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52068*4+0x02000000,0xb8e5); +reg_write( DDR_REG_BASE +0x52069*4+0x02000000,0x9f8); +reg_write( DDR_REG_BASE +0x5206a*4+0x02000000,0xfe82); +reg_write( DDR_REG_BASE +0x5206b*4+0x02000000,0xb02); +reg_write( DDR_REG_BASE +0x5206c*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x5206d*4+0x02000000,0xca04); +reg_write( DDR_REG_BASE +0x5206e*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x5206f*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52070*4+0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x52071*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x52072*4+0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x52073*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x52074*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52075*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52076*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52077*4+0x02000000,0x7965); +reg_write( DDR_REG_BASE +0x52078*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x52079*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x5207a*4+0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x5207b*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x5207c*4+0x02000000,0x140); +reg_write( DDR_REG_BASE +0x5207d*4+0x02000000,0x2332); +reg_write( DDR_REG_BASE +0x5207e*4+0x02000000,0x1f81); +reg_write( DDR_REG_BASE +0x5207f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52080*4+0x02000000,0x7f0); +reg_write( DDR_REG_BASE +0x52081*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x52082*4+0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x52083*4+0x02000000,0xb420); +reg_write( DDR_REG_BASE +0x52084*4+0x02000000,0xbdf); +reg_write( DDR_REG_BASE +0x52085*4+0x02000000,0x8214); +reg_write( DDR_REG_BASE +0x52086*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x52087*4+0x02000000,0xad7); +reg_write( DDR_REG_BASE +0x52088*4+0x02000000,0x8024); +reg_write( DDR_REG_BASE +0x52089*4+0x02000000,0x2316); +reg_write( DDR_REG_BASE +0x5208a*4+0x02000000,0x308b); +reg_write( DDR_REG_BASE +0x5208b*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5208c*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5208d*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x5208e*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x5208f*4+0x02000000,0xe032); +reg_write( DDR_REG_BASE +0x52090*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52091*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x52092*4+0x02000000,0x9de); +reg_write( DDR_REG_BASE +0x52093*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52094*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52095*4+0x02000000,0xcfa); +reg_write( DDR_REG_BASE +0x52096*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x52097*4+0x02000000,0x82e); +reg_write( DDR_REG_BASE +0x52098*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x52099*4+0x02000000,0xd807); +reg_write( DDR_REG_BASE +0x5209a*4+0x02000000,0x23ab); +reg_write( DDR_REG_BASE +0x5209b*4+0x02000000,0x30c4); +reg_write( DDR_REG_BASE +0x5209c*4+0x02000000,0x7fff); +reg_write( DDR_REG_BASE +0x5209d*4+0x02000000,0xf000); +reg_write( DDR_REG_BASE +0x5209e*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x5209f*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x520a0*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x520a1*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x520a2*4+0x02000000,0x9500); +reg_write( DDR_REG_BASE +0x520a3*4+0x02000000,0xb8a1); +reg_write( DDR_REG_BASE +0x520a4*4+0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x520a5*4+0x02000000,0xf3e); +reg_write( DDR_REG_BASE +0x520a6*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x520a7*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x520a8*4+0x02000000,0xd81f); +reg_write( DDR_REG_BASE +0x520a9*4+0x02000000,0xf36); +reg_write( DDR_REG_BASE +0x520aa*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x520ab*4+0x02000000,0x1df6); +reg_write( DDR_REG_BASE +0x520ac*4+0x02000000,0x105d); +reg_write( DDR_REG_BASE +0x520ad*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x520ae*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x520af*4+0x02000000,0xf2a); +reg_write( DDR_REG_BASE +0x520b0*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x520b1*4+0x02000000,0xd81f); +reg_write( DDR_REG_BASE +0x520b2*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x520b3*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x520b4*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x520b5*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x520b6*4+0x02000000,0xf1a); +reg_write( DDR_REG_BASE +0x520b7*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x520b8*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x520b9*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x520ba*4+0x02000000,0x150a); +reg_write( DDR_REG_BASE +0x520bb*4+0x02000000,0x9700); +reg_write( DDR_REG_BASE +0x520bc*4+0x02000000,0xb881); +reg_write( DDR_REG_BASE +0x520bd*4+0x02000000,0x1d0a); +reg_write( DDR_REG_BASE +0x520be*4+0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x520bf*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x520c0*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x520c1*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x520c2*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x520c3*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x520c4*4+0x02000000,0x12); +reg_write( DDR_REG_BASE +0x520c5*4+0x02000000,0x218c); +reg_write( DDR_REG_BASE +0x520c6*4+0x02000000,0x8203); +reg_write( DDR_REG_BASE +0x520c7*4+0x02000000,0xfcc); +reg_write( DDR_REG_BASE +0x520c8*4+0x02000000,0x10e); +reg_write( DDR_REG_BASE +0x520c9*4+0x02000000,0x80e); +reg_write( DDR_REG_BASE +0x520ca*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x520cb*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x520cc*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x520cd*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x520ce*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x520cf*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x520d0*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x520d1*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x520d2*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x520d3*4+0x02000000,0x81b); +reg_write( DDR_REG_BASE +0x520d4*4+0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x520d5*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x520d6*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x520d7*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x520d8*4+0x02000000,0xe036); +reg_write( DDR_REG_BASE +0x520d9*4+0x02000000,0xed6); +reg_write( DDR_REG_BASE +0x520da*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x520db*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x520dc*4+0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x520dd*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x520de*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x520df*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x520e0*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x520e1*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x520e2*4+0x02000000,0xf2); +reg_write( DDR_REG_BASE +0x520e3*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x520e4*4+0x02000000,0x45); +reg_write( DDR_REG_BASE +0x520e5*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x520e6*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x520e7*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x520e8*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x520e9*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x520ea*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x520eb*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x520ec*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x520ed*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x520ee*4+0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x520ef*4+0x02000000,0xdc08); +reg_write( DDR_REG_BASE +0x520f0*4+0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x520f1*4+0x02000000,0xc01); +reg_write( DDR_REG_BASE +0x520f2*4+0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x520f3*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x520f4*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x520f5*4+0x02000000,0x4d); +reg_write( DDR_REG_BASE +0x520f6*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x520f7*4+0x02000000,0x4378); +reg_write( DDR_REG_BASE +0x520f8*4+0x02000000,0xc24e); +reg_write( DDR_REG_BASE +0x520f9*4+0x02000000,0xae2); +reg_write( DDR_REG_BASE +0x520fa*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x520fb*4+0x02000000,0x4728); +reg_write( DDR_REG_BASE +0x520fc*4+0x02000000,0x2353); +reg_write( DDR_REG_BASE +0x520fd*4+0x02000000,0x30c0); +reg_write( DDR_REG_BASE +0x520fe*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x520ff*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52100*4+0x02000000,0xe0c4); +reg_write( DDR_REG_BASE +0x52101*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x52102*4+0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x52103*4+0x02000000,0xd9f0); +reg_write( DDR_REG_BASE +0x52104*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x52105*4+0x02000000,0xc07); +reg_write( DDR_REG_BASE +0x52106*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x52107*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x52108*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52109*4+0x02000000,0x6c1); +reg_write( DDR_REG_BASE +0x5210a*4+0x02000000,0xba8b); +reg_write( DDR_REG_BASE +0x5210b*4+0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x5210c*4+0x02000000,0xc096); +reg_write( DDR_REG_BASE +0x5210d*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5210e*4+0x02000000,0xda28); +reg_write( DDR_REG_BASE +0x5210f*4+0x02000000,0x9be); +reg_write( DDR_REG_BASE +0x52110*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x52111*4+0x02000000,0xc396); +reg_write( DDR_REG_BASE +0x52112*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x52113*4+0x02000000,0x6c7); +reg_write( DDR_REG_BASE +0x52114*4+0x02000000,0x20b8); +reg_write( DDR_REG_BASE +0x52115*4+0x02000000,0xfc3); +reg_write( DDR_REG_BASE +0x52116*4+0x02000000,0xc06d); +reg_write( DDR_REG_BASE +0x52117*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52118*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52119*4+0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x5211a*4+0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x5211b*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x5211c*4+0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x5211d*4+0x02000000,0x14a0); +reg_write( DDR_REG_BASE +0x5211e*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x5211f*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52120*4+0x02000000,0xc346); +reg_write( DDR_REG_BASE +0x52121*4+0x02000000,0xc04f); +reg_write( DDR_REG_BASE +0x52122*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52123*4+0x02000000,0x149c); +reg_write( DDR_REG_BASE +0x52124*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x52125*4+0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x52126*4+0x02000000,0x17c3); +reg_write( DDR_REG_BASE +0x52127*4+0x02000000,0x1c30); +reg_write( DDR_REG_BASE +0x52128*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52129*4+0x02000000,0xc050); +reg_write( DDR_REG_BASE +0x5212a*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5212b*4+0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x5212c*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x5212d*4+0x02000000,0xc10e); +reg_write( DDR_REG_BASE +0x5212e*4+0x02000000,0x1c25); +reg_write( DDR_REG_BASE +0x5212f*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x52130*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x52131*4+0x02000000,0xeb06); +reg_write( DDR_REG_BASE +0x52132*4+0x02000000,0xbb61); +reg_write( DDR_REG_BASE +0x52133*4+0x02000000,0xb01); +reg_write( DDR_REG_BASE +0x52134*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x52135*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52136*4+0x02000000,0x1c24); +reg_write( DDR_REG_BASE +0x52137*4+0x02000000,0x3003); +reg_write( DDR_REG_BASE +0x52138*4+0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x52139*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5213a*4+0x02000000,0xc748); +reg_write( DDR_REG_BASE +0x5213b*4+0x02000000,0x1c1c); +reg_write( DDR_REG_BASE +0x5213c*4+0x02000000,0x3103); +reg_write( DDR_REG_BASE +0x5213d*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x5213e*4+0x02000000,0x200f); +reg_write( DDR_REG_BASE +0x5213f*4+0x02000000,0x380); +reg_write( DDR_REG_BASE +0x52140*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52141*4+0x02000000,0x9da); +reg_write( DDR_REG_BASE +0x52142*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52143*4+0x02000000,0xc054); +reg_write( DDR_REG_BASE +0x52144*4+0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x52145*4+0x02000000,0xb863); +reg_write( DDR_REG_BASE +0x52146*4+0x02000000,0xc052); +reg_write( DDR_REG_BASE +0x52147*4+0x02000000,0x7314); +reg_write( DDR_REG_BASE +0x52148*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52149*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5214a*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x5214b*4+0x02000000,0x48); +reg_write( DDR_REG_BASE +0x5214c*4+0x02000000,0x2d); +reg_write( DDR_REG_BASE +0x5214d*4+0x02000000,0xc051); +reg_write( DDR_REG_BASE +0x5214e*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5214f*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52150*4+0x02000000,0x1ea); +reg_write( DDR_REG_BASE +0x52151*4+0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x52152*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52153*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x52154*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52155*4+0x02000000,0xc0ff); +reg_write( DDR_REG_BASE +0x52156*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52157*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52158*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52159*4+0x02000000,0x3f00); +reg_write( DDR_REG_BASE +0x5215a*4+0x02000000,0x2080); +reg_write( DDR_REG_BASE +0x5215b*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5215c*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x5215d*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x5215e*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5215f*4+0x02000000,0x76c4); +reg_write( DDR_REG_BASE +0x52160*4+0x02000000,0x900f); +reg_write( DDR_REG_BASE +0x52161*4+0x02000000,0xe022); +reg_write( DDR_REG_BASE +0x52162*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52163*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x52164*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52165*4+0x02000000,0xee); +reg_write( DDR_REG_BASE +0x52166*4+0x02000000,0x2050); +reg_write( DDR_REG_BASE +0x52167*4+0x02000000,0x141); +reg_write( DDR_REG_BASE +0x52168*4+0x02000000,0xb885); +reg_write( DDR_REG_BASE +0x52169*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5216a*4+0x02000000,0x7044); +reg_write( DDR_REG_BASE +0x5216b*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x5216c*4+0x02000000,0xe0ee); +reg_write( DDR_REG_BASE +0x5216d*4+0x02000000,0xc051); +reg_write( DDR_REG_BASE +0x5216e*4+0x02000000,0x1498); +reg_write( DDR_REG_BASE +0x5216f*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x52170*4+0x02000000,0xc055); +reg_write( DDR_REG_BASE +0x52171*4+0x02000000,0x1494); +reg_write( DDR_REG_BASE +0x52172*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x52173*4+0x02000000,0xc053); +reg_write( DDR_REG_BASE +0x52174*4+0x02000000,0x996); +reg_write( DDR_REG_BASE +0x52175*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52176*4+0x02000000,0xc083); +reg_write( DDR_REG_BASE +0x52177*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x52178*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52179*4+0x02000000,0x7cb); +reg_write( DDR_REG_BASE +0x5217a*4+0x02000000,0x8e61); +reg_write( DDR_REG_BASE +0x5217b*4+0x02000000,0x8e20); +reg_write( DDR_REG_BASE +0x5217c*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x5217d*4+0x02000000,0xc210); +reg_write( DDR_REG_BASE +0x5217e*4+0x02000000,0x7a34); +reg_write( DDR_REG_BASE +0x5217f*4+0x02000000,0x9200); +reg_write( DDR_REG_BASE +0x52180*4+0x02000000,0xe889); +reg_write( DDR_REG_BASE +0x52181*4+0x02000000,0xc096); +reg_write( DDR_REG_BASE +0x52182*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x52183*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x52184*4+0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x52185*4+0x02000000,0x833); +reg_write( DDR_REG_BASE +0x52186*4+0x02000000,0x2042); +reg_write( DDR_REG_BASE +0x52187*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x52188*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x52189*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x5218a*4+0x02000000,0xbe7); +reg_write( DDR_REG_BASE +0x5218b*4+0x02000000,0x8045); +reg_write( DDR_REG_BASE +0x5218c*4+0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x5218d*4+0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x5218e*4+0x02000000,0x839); +reg_write( DDR_REG_BASE +0x5218f*4+0x02000000,0xb5); +reg_write( DDR_REG_BASE +0x52190*4+0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x52191*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x52192*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52193*4+0x02000000,0xf0f0); +reg_write( DDR_REG_BASE +0x52194*4+0x02000000,0x43db); +reg_write( DDR_REG_BASE +0x52195*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52196*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x52197*4+0x02000000,0x43e1); +reg_write( DDR_REG_BASE +0x52198*4+0x02000000,0x737f); +reg_write( DDR_REG_BASE +0x52199*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x5219a*4+0x02000000,0x41e1); +reg_write( DDR_REG_BASE +0x5219b*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x5219c*4+0x02000000,0xe42); +reg_write( DDR_REG_BASE +0x5219d*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5219e*4+0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x5219f*4+0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x521a0*4+0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x521a1*4+0x02000000,0x33c2); +reg_write( DDR_REG_BASE +0x521a2*4+0x02000000,0xd808); +reg_write( DDR_REG_BASE +0x521a3*4+0x02000000,0x41e1); +reg_write( DDR_REG_BASE +0x521a4*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x521a5*4+0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x521a6*4+0x02000000,0xe2e); +reg_write( DDR_REG_BASE +0x521a7*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x521a8*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x521a9*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x521aa*4+0x02000000,0xb3a); +reg_write( DDR_REG_BASE +0x521ab*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x521ac*4+0x02000000,0xc083); +reg_write( DDR_REG_BASE +0x521ad*4+0x02000000,0x8e61); +reg_write( DDR_REG_BASE +0x521ae*4+0x02000000,0x8e20); +reg_write( DDR_REG_BASE +0x521af*4+0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x521b0*4+0x02000000,0xc20f); +reg_write( DDR_REG_BASE +0x521b1*4+0x02000000,0x7a34); +reg_write( DDR_REG_BASE +0x521b2*4+0x02000000,0x9200); +reg_write( DDR_REG_BASE +0x521b3*4+0x02000000,0x815); +reg_write( DDR_REG_BASE +0x521b4*4+0x02000000,0x7f1); +reg_write( DDR_REG_BASE +0x521b5*4+0x02000000,0xc096); +reg_write( DDR_REG_BASE +0x521b6*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x521b7*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x521b8*4+0x02000000,0x809); +reg_write( DDR_REG_BASE +0x521b9*4+0x02000000,0x833); +reg_write( DDR_REG_BASE +0x521ba*4+0x02000000,0xe020); +reg_write( DDR_REG_BASE +0x521bb*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x521bc*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x521bd*4+0x02000000,0xbe9); +reg_write( DDR_REG_BASE +0x521be*4+0x02000000,0x8045); +reg_write( DDR_REG_BASE +0x521bf*4+0x02000000,0xc012); +reg_write( DDR_REG_BASE +0x521c0*4+0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x521c1*4+0x02000000,0x114); +reg_write( DDR_REG_BASE +0x521c2*4+0x02000000,0xc76); +reg_write( DDR_REG_BASE +0x521c3*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x521c4*4+0x02000000,0xc014); +reg_write( DDR_REG_BASE +0x521c5*4+0x02000000,0xc013); +reg_write( DDR_REG_BASE +0x521c6*4+0x02000000,0xe807); +reg_write( DDR_REG_BASE +0x521c7*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x521c8*4+0x02000000,0x36); +reg_write( DDR_REG_BASE +0x521c9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x521ca*4+0x02000000,0xb2a); +reg_write( DDR_REG_BASE +0x521cb*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x521cc*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x521cd*4+0x02000000,0x8ee0); +reg_write( DDR_REG_BASE +0x521ce*4+0x02000000,0xf035); +reg_write( DDR_REG_BASE +0x521cf*4+0x02000000,0xc010); +reg_write( DDR_REG_BASE +0x521d0*4+0x02000000,0x7dfd); +reg_write( DDR_REG_BASE +0x521d1*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x521d2*4+0x02000000,0x3c2); +reg_write( DDR_REG_BASE +0x521d3*4+0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x521d4*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x521d5*4+0x02000000,0x3c3); +reg_write( DDR_REG_BASE +0x521d6*4+0x02000000,0x6358); +reg_write( DDR_REG_BASE +0x521d7*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x521d8*4+0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x521d9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x521da*4+0x02000000,0x2049); +reg_write( DDR_REG_BASE +0x521db*4+0x02000000,0x7c1); +reg_write( DDR_REG_BASE +0x521dc*4+0x02000000,0xc015); +reg_write( DDR_REG_BASE +0x521dd*4+0x02000000,0x78f4); +reg_write( DDR_REG_BASE +0x521de*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x521df*4+0x02000000,0x4b50); +reg_write( DDR_REG_BASE +0x521e0*4+0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x521e1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x521e2*4+0x02000000,0xc04e); +reg_write( DDR_REG_BASE +0x521e3*4+0x02000000,0xc013); +reg_write( DDR_REG_BASE +0x521e4*4+0x02000000,0xe812); +reg_write( DDR_REG_BASE +0x521e5*4+0x02000000,0xc010); +reg_write( DDR_REG_BASE +0x521e6*4+0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x521e7*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x521e8*4+0x02000000,0x3c2); +reg_write( DDR_REG_BASE +0x521e9*4+0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x521ea*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x521eb*4+0x02000000,0x3c0); +reg_write( DDR_REG_BASE +0x521ec*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x521ed*4+0x02000000,0xc240); +reg_write( DDR_REG_BASE +0x521ee*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x521ef*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x521f0*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x521f1*4+0x02000000,0x38); +reg_write( DDR_REG_BASE +0x521f2*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x521f3*4+0x02000000,0xada); +reg_write( DDR_REG_BASE +0x521f4*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x521f5*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x521f6*4+0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x521f7*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x521f8*4+0x02000000,0x39); +reg_write( DDR_REG_BASE +0x521f9*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x521fa*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x521fb*4+0x02000000,0x780e); +reg_write( DDR_REG_BASE +0x521fc*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x521fd*4+0x02000000,0x207f); +reg_write( DDR_REG_BASE +0x521fe*4+0x02000000,0x140); +reg_write( DDR_REG_BASE +0x521ff*4+0x02000000,0xd56); +reg_write( DDR_REG_BASE +0x52200*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52201*4+0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x52202*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x52203*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x52204*4+0x02000000,0x897); +reg_write( DDR_REG_BASE +0x52205*4+0x02000000,0x83e5); +reg_write( DDR_REG_BASE +0x52206*4+0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x52207*4+0x02000000,0x105b); +reg_write( DDR_REG_BASE +0x52208*4+0x02000000,0xc012); +reg_write( DDR_REG_BASE +0x52209*4+0x02000000,0x835); +reg_write( DDR_REG_BASE +0x5220a*4+0x02000000,0x115); +reg_write( DDR_REG_BASE +0x5220b*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x5220c*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x5220d*4+0x02000000,0x1ea); +reg_write( DDR_REG_BASE +0x5220e*4+0x02000000,0x9200); +reg_write( DDR_REG_BASE +0x5220f*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52210*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52211*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52212*4+0x02000000,0xc0ff); +reg_write( DDR_REG_BASE +0x52213*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52214*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52215*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52216*4+0x02000000,0x3f00); +reg_write( DDR_REG_BASE +0x52217*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52218*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52219*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5221a*4+0x02000000,0xfc00); +reg_write( DDR_REG_BASE +0x5221b*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x5221c*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x5221d*4+0x02000000,0xc011); +reg_write( DDR_REG_BASE +0x5221e*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5221f*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52220*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52221*4+0x02000000,0xe0ee); +reg_write( DDR_REG_BASE +0x52222*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52223*4+0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x52224*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52225*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x52226*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x52227*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x52228*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52229*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x5222a*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5222b*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5222c*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5222d*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5222e*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5222f*4+0x02000000,0xc1ad); +reg_write( DDR_REG_BASE +0x52230*4+0x02000000,0xc248); +reg_write( DDR_REG_BASE +0x52231*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x52232*4+0x02000000,0xc16); +reg_write( DDR_REG_BASE +0x52233*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x52234*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x52235*4+0x02000000,0x2342); +reg_write( DDR_REG_BASE +0x52236*4+0x02000000,0x30cd); +reg_write( DDR_REG_BASE +0x52237*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x52238*4+0x02000000,0x97e); +reg_write( DDR_REG_BASE +0x52239*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x5223a*4+0x02000000,0x7eaf); +reg_write( DDR_REG_BASE +0x5223b*4+0x02000000,0xd33); +reg_write( DDR_REG_BASE +0x5223c*4+0x02000000,0x1134); +reg_write( DDR_REG_BASE +0x5223d*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5223e*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5223f*4+0x02000000,0xd82); +reg_write( DDR_REG_BASE +0x52240*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52241*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52242*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x52243*4+0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x52244*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52245*4+0x02000000,0xd981); +reg_write( DDR_REG_BASE +0x52246*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52247*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52248*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52249*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5224a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5224b*4+0x02000000,0xb98e); +reg_write( DDR_REG_BASE +0x5224c*4+0x02000000,0xe3e); +reg_write( DDR_REG_BASE +0x5224d*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5224e*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5224f*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52250*4+0x02000000,0xdf6); +reg_write( DDR_REG_BASE +0x52251*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52252*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52253*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x52254*4+0x02000000,0x203c); +reg_write( DDR_REG_BASE +0x52255*4+0x02000000,0x381); +reg_write( DDR_REG_BASE +0x52256*4+0x02000000,0x2342); +reg_write( DDR_REG_BASE +0x52257*4+0x02000000,0x304e); +reg_write( DDR_REG_BASE +0x52258*4+0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x52259*4+0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x5225a*4+0x02000000,0x273c); +reg_write( DDR_REG_BASE +0x5225b*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x5225c*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x5225d*4+0x02000000,0x8040); +reg_write( DDR_REG_BASE +0x5225e*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x5225f*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52260*4+0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x52261*4+0x02000000,0x1222); +reg_write( DDR_REG_BASE +0x52262*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52263*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x52264*4+0x02000000,0x20cf); +reg_write( DDR_REG_BASE +0x52265*4+0x02000000,0xa2); +reg_write( DDR_REG_BASE +0x52266*4+0x02000000,0x74b5); +reg_write( DDR_REG_BASE +0x52267*4+0x02000000,0xc26); +reg_write( DDR_REG_BASE +0x52268*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x52269*4+0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x5226a*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x5226b*4+0x02000000,0xc2a); +reg_write( DDR_REG_BASE +0x5226c*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5226d*4+0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x5226e*4+0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x5226f*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52270*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52271*4+0x02000000,0x2710); +reg_write( DDR_REG_BASE +0x52272*4+0x02000000,0xc1a); +reg_write( DDR_REG_BASE +0x52273*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x52274*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x52275*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52276*4+0x02000000,0x900f); +reg_write( DDR_REG_BASE +0x52277*4+0x02000000,0xe0c0); +reg_write( DDR_REG_BASE +0x52278*4+0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x52279*4+0x02000000,0xb1e0); +reg_write( DDR_REG_BASE +0x5227a*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5227b*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x5227c*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x5227d*4+0x02000000,0xf0f0); +reg_write( DDR_REG_BASE +0x5227e*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x5227f*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x52280*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x52281*4+0x02000000,0x78c0); +reg_write( DDR_REG_BASE +0x52282*4+0x02000000,0xb105); +reg_write( DDR_REG_BASE +0x52283*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52284*4+0x02000000,0x772c); +reg_write( DDR_REG_BASE +0x52285*4+0x02000000,0xc145); +reg_write( DDR_REG_BASE +0x52286*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52287*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x52288*4+0x02000000,0x70fd); +reg_write( DDR_REG_BASE +0x52289*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x5228a*4+0x02000000,0x773c); +reg_write( DDR_REG_BASE +0x5228b*4+0x02000000,0xc10a); +reg_write( DDR_REG_BASE +0x5228c*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x5228d*4+0x02000000,0x2114); +reg_write( DDR_REG_BASE +0x5228e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5228f*4+0x02000000,0x48e8); +reg_write( DDR_REG_BASE +0x52290*4+0x02000000,0xb9c0); +reg_write( DDR_REG_BASE +0x52291*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x52292*4+0x02000000,0xe2b); +reg_write( DDR_REG_BASE +0x52293*4+0x02000000,0x10b5); +reg_write( DDR_REG_BASE +0x52294*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52295*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x52296*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52297*4+0x02000000,0xf0f0); +reg_write( DDR_REG_BASE +0x52298*4+0x02000000,0x7bf0); +reg_write( DDR_REG_BASE +0x52299*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x5229a*4+0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x5229b*4+0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x5229c*4+0x02000000,0xc42); +reg_write( DDR_REG_BASE +0x5229d*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5229e*4+0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x5229f*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x522a0*4+0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x522a1*4+0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x522a2*4+0x02000000,0x7b10); +reg_write( DDR_REG_BASE +0x522a3*4+0x02000000,0xd808); +reg_write( DDR_REG_BASE +0x522a4*4+0x02000000,0xc32); +reg_write( DDR_REG_BASE +0x522a5*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x522a6*4+0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x522a7*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x522a8*4+0x02000000,0xe030); +reg_write( DDR_REG_BASE +0x522a9*4+0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x522aa*4+0x02000000,0x234f); +reg_write( DDR_REG_BASE +0x522ab*4+0x02000000,0x3040); +reg_write( DDR_REG_BASE +0x522ac*4+0x02000000,0x899); +reg_write( DDR_REG_BASE +0x522ad*4+0x02000000,0xb1); +reg_write( DDR_REG_BASE +0x522ae*4+0x02000000,0x73b5); +reg_write( DDR_REG_BASE +0x522af*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x522b0*4+0x02000000,0xb8c1); +reg_write( DDR_REG_BASE +0x522b1*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x522b2*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x522b3*4+0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x522b4*4+0x02000000,0xc96); +reg_write( DDR_REG_BASE +0x522b5*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x522b6*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x522b7*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x522b8*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x522b9*4+0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x522ba*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x522bb*4+0x02000000,0xb98e); +reg_write( DDR_REG_BASE +0x522bc*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x522bd*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x522be*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x522bf*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x522c0*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x522c1*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x522c2*4+0x02000000,0xd52); +reg_write( DDR_REG_BASE +0x522c3*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x522c4*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x522c5*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x522c6*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x522c7*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x522c8*4+0x02000000,0x7f0f); +reg_write( DDR_REG_BASE +0x522c9*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x522ca*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x522cb*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x522cc*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x522cd*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x522ce*4+0x02000000,0xd3a); +reg_write( DDR_REG_BASE +0x522cf*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x522d0*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x522d1*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x522d2*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x522d3*4+0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x522d4*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x522d5*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x522d6*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x522d7*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x522d8*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x522d9*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x522da*4+0x02000000,0xd22); +reg_write( DDR_REG_BASE +0x522db*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x522dc*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x522dd*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x522de*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x522df*4+0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x522e0*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x522e1*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x522e2*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x522e3*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x522e4*4+0x02000000,0xdb28); +reg_write( DDR_REG_BASE +0x522e5*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x522e6*4+0x02000000,0xd0a); +reg_write( DDR_REG_BASE +0x522e7*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x522e8*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x522e9*4+0x02000000,0xf52); +reg_write( DDR_REG_BASE +0x522ea*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x522eb*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x522ec*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x522ed*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x522ee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x522ef*4+0x02000000,0x3100); +reg_write( DDR_REG_BASE +0x522f0*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x522f1*4+0x02000000,0x22a); +reg_write( DDR_REG_BASE +0x522f2*4+0x02000000,0x21); +reg_write( DDR_REG_BASE +0x522f3*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x522f4*4+0x02000000,0x2f3); +reg_write( DDR_REG_BASE +0x522f5*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x522f6*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x522f7*4+0x02000000,0x3441); +reg_write( DDR_REG_BASE +0x522f8*4+0x02000000,0x44c); +reg_write( DDR_REG_BASE +0x522f9*4+0x02000000,0x2d); +reg_write( DDR_REG_BASE +0x522fa*4+0x02000000,0x7177); +reg_write( DDR_REG_BASE +0x522fb*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x522fc*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x522fd*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x522fe*4+0x02000000,0x13); +reg_write( DDR_REG_BASE +0x522ff*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52300*4+0x02000000,0x5d4); +reg_write( DDR_REG_BASE +0x52301*4+0x02000000,0x21); +reg_write( DDR_REG_BASE +0x52302*4+0x02000000,0x7377); +reg_write( DDR_REG_BASE +0x52303*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x52304*4+0x02000000,0x269a); +reg_write( DDR_REG_BASE +0x52305*4+0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x52306*4+0x02000000,0x7e05); +reg_write( DDR_REG_BASE +0x52307*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52308*4+0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x52309*4+0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x5230a*4+0x02000000,0x43c1); +reg_write( DDR_REG_BASE +0x5230b*4+0x02000000,0xb66); +reg_write( DDR_REG_BASE +0x5230c*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5230d*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x5230e*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x5230f*4+0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x52310*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52311*4+0x02000000,0xbde); +reg_write( DDR_REG_BASE +0x52312*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52313*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x52314*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52315*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52316*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x52317*4+0x02000000,0x7f0f); +reg_write( DDR_REG_BASE +0x52318*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x52319*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5231a*4+0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x5231b*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5231c*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5231d*4+0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x5231e*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x5231f*4+0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x52320*4+0x02000000,0xc96); +reg_write( DDR_REG_BASE +0x52321*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52322*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52323*4+0x02000000,0xd828); +reg_write( DDR_REG_BASE +0x52324*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52325*4+0x02000000,0xd808); +reg_write( DDR_REG_BASE +0x52326*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x52327*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x52328*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x52329*4+0x02000000,0x7edd); +reg_write( DDR_REG_BASE +0x5232a*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5232b*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5232c*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x5232d*4+0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x5232e*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5232f*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52330*4+0x02000000,0xc76); +reg_write( DDR_REG_BASE +0x52331*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52332*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x52333*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52334*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52335*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x52336*4+0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x52337*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52338*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52339*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x5233a*4+0x02000000,0x33c1); +reg_write( DDR_REG_BASE +0x5233b*4+0x02000000,0xc62); +reg_write( DDR_REG_BASE +0x5233c*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5233d*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5233e*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5233f*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x52340*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x52341*4+0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x52342*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52343*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52344*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x52345*4+0x02000000,0x3501); +reg_write( DDR_REG_BASE +0x52346*4+0x02000000,0xc4a); +reg_write( DDR_REG_BASE +0x52347*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52348*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52349*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5234a*4+0x02000000,0xc02); +reg_write( DDR_REG_BASE +0x5234b*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5234c*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5234d*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5234e*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5234f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52350*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52351*4+0x02000000,0xdae0); +reg_write( DDR_REG_BASE +0x52352*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x52353*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52354*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52355*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52356*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52357*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52358*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x52359*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x5235a*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x5235b*4+0x02000000,0x7204); +reg_write( DDR_REG_BASE +0x5235c*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x5235d*4+0x02000000,0xb340); +reg_write( DDR_REG_BASE +0x5235e*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x5235f*4+0x02000000,0x485); +reg_write( DDR_REG_BASE +0x52360*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52361*4+0x02000000,0xb3e); +reg_write( DDR_REG_BASE +0x52362*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52363*4+0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x52364*4+0x02000000,0xe5a); +reg_write( DDR_REG_BASE +0x52365*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52366*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52367*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x52368*4+0x02000000,0xbe90); +reg_write( DDR_REG_BASE +0x52369*4+0x02000000,0xf968); +reg_write( DDR_REG_BASE +0x5236a*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5236b*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5236c*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5236d*4+0x02000000,0xbfe); +reg_write( DDR_REG_BASE +0x5236e*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5236f*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52370*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52371*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52372*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52373*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52374*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x52375*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52376*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52377*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52378*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52379*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5237a*4+0x02000000,0xbe2); +reg_write( DDR_REG_BASE +0x5237b*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5237c*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x5237d*4+0x02000000,0xf95e); +reg_write( DDR_REG_BASE +0x5237e*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5237f*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52380*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52381*4+0x02000000,0xbd6); +reg_write( DDR_REG_BASE +0x52382*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52383*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52384*4+0x02000000,0xf957); +reg_write( DDR_REG_BASE +0x52385*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52386*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52387*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52388*4+0x02000000,0xbc6); +reg_write( DDR_REG_BASE +0x52389*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5238a*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5238b*4+0x02000000,0xf957); +reg_write( DDR_REG_BASE +0x5238c*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5238d*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5238e*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5238f*4+0x02000000,0xbba); +reg_write( DDR_REG_BASE +0x52390*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52391*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52392*4+0x02000000,0xf950); +reg_write( DDR_REG_BASE +0x52393*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52394*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52395*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52396*4+0x02000000,0xbaa); +reg_write( DDR_REG_BASE +0x52397*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52398*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52399*4+0x02000000,0xf950); +reg_write( DDR_REG_BASE +0x5239a*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5239b*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5239c*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5239d*4+0x02000000,0xb9e); +reg_write( DDR_REG_BASE +0x5239e*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5239f*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523a0*4+0x02000000,0xf949); +reg_write( DDR_REG_BASE +0x523a1*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523a2*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x523a3*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523a4*4+0x02000000,0xb8e); +reg_write( DDR_REG_BASE +0x523a5*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523a6*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523a7*4+0x02000000,0xf949); +reg_write( DDR_REG_BASE +0x523a8*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523a9*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x523aa*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523ab*4+0x02000000,0xb82); +reg_write( DDR_REG_BASE +0x523ac*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523ad*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523ae*4+0x02000000,0xf942); +reg_write( DDR_REG_BASE +0x523af*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523b0*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x523b1*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523b2*4+0x02000000,0xb72); +reg_write( DDR_REG_BASE +0x523b3*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523b4*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523b5*4+0x02000000,0xf942); +reg_write( DDR_REG_BASE +0x523b6*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523b7*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x523b8*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523b9*4+0x02000000,0xb66); +reg_write( DDR_REG_BASE +0x523ba*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523bb*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523bc*4+0x02000000,0xf93b); +reg_write( DDR_REG_BASE +0x523bd*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523be*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x523bf*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523c0*4+0x02000000,0xb56); +reg_write( DDR_REG_BASE +0x523c1*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523c2*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523c3*4+0x02000000,0xf93b); +reg_write( DDR_REG_BASE +0x523c4*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523c5*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x523c6*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523c7*4+0x02000000,0xb4a); +reg_write( DDR_REG_BASE +0x523c8*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523c9*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523ca*4+0x02000000,0xf934); +reg_write( DDR_REG_BASE +0x523cb*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523cc*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x523cd*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523ce*4+0x02000000,0xb3a); +reg_write( DDR_REG_BASE +0x523cf*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523d0*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523d1*4+0x02000000,0xf934); +reg_write( DDR_REG_BASE +0x523d2*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523d3*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x523d4*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523d5*4+0x02000000,0xb2e); +reg_write( DDR_REG_BASE +0x523d6*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523d7*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523d8*4+0x02000000,0xf92d); +reg_write( DDR_REG_BASE +0x523d9*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523da*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x523db*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523dc*4+0x02000000,0xb1e); +reg_write( DDR_REG_BASE +0x523dd*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523de*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523df*4+0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x523e0*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x523e1*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x523e2*4+0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x523e3*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x523e4*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523e5*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x523e6*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523e7*4+0x02000000,0xb0a); +reg_write( DDR_REG_BASE +0x523e8*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523e9*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523ea*4+0x02000000,0x79dd); +reg_write( DDR_REG_BASE +0x523eb*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x523ec*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x523ed*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x523ee*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x523ef*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x523f0*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x523f1*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523f2*4+0x02000000,0xaf2); +reg_write( DDR_REG_BASE +0x523f3*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523f4*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523f5*4+0x02000000,0xf91c); +reg_write( DDR_REG_BASE +0x523f6*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523f7*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x523f8*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523f9*4+0x02000000,0xae6); +reg_write( DDR_REG_BASE +0x523fa*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523fb*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523fc*4+0x02000000,0xd0e); +reg_write( DDR_REG_BASE +0x523fd*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523fe*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x523ff*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52400*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52401*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52402*4+0x02000000,0x3bd); +reg_write( DDR_REG_BASE +0x52403*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52404*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52405*4+0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x52406*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x52407*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52408*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52409*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5240a*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5240b*4+0x02000000,0xac2); +reg_write( DDR_REG_BASE +0x5240c*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5240d*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5240e*4+0x02000000,0xf90c); +reg_write( DDR_REG_BASE +0x5240f*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52410*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52411*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x52412*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52413*4+0x02000000,0xab2); +reg_write( DDR_REG_BASE +0x52414*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52415*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52416*4+0x02000000,0xf905); +reg_write( DDR_REG_BASE +0x52417*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x52418*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52419*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5241a*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5241b*4+0x02000000,0xaa2); +reg_write( DDR_REG_BASE +0x5241c*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5241d*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5241e*4+0x02000000,0xf8fe); +reg_write( DDR_REG_BASE +0x5241f*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52420*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52421*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52422*4+0x02000000,0xa92); +reg_write( DDR_REG_BASE +0x52423*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52424*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52425*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x52426*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52427*4+0x02000000,0xf900); +reg_write( DDR_REG_BASE +0x52428*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52429*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5242a*4+0x02000000,0xa82); +reg_write( DDR_REG_BASE +0x5242b*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5242c*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5242d*4+0x02000000,0xf8fa); +reg_write( DDR_REG_BASE +0x5242e*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x5242f*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52430*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52431*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52432*4+0x02000000,0xa72); +reg_write( DDR_REG_BASE +0x52433*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52434*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52435*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x52436*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52437*4+0x02000000,0xf8f5); +reg_write( DDR_REG_BASE +0x52438*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52439*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5243a*4+0x02000000,0xa62); +reg_write( DDR_REG_BASE +0x5243b*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5243c*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5243d*4+0x02000000,0xf8ef); +reg_write( DDR_REG_BASE +0x5243e*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5243f*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52440*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52441*4+0x02000000,0xa56); +reg_write( DDR_REG_BASE +0x52442*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52443*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52444*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52445*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52446*4+0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x52447*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52448*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52449*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x5244a*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5244b*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x5244c*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x5244d*4+0x02000000,0xa3e); +reg_write( DDR_REG_BASE +0x5244e*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5244f*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52450*4+0x02000000,0xf8e8); +reg_write( DDR_REG_BASE +0x52451*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x52452*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52453*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52454*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52455*4+0x02000000,0xa2e); +reg_write( DDR_REG_BASE +0x52456*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52457*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52458*4+0x02000000,0xf8e1); +reg_write( DDR_REG_BASE +0x52459*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5245a*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5245b*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5245c*4+0x02000000,0xa1e); +reg_write( DDR_REG_BASE +0x5245d*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5245e*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5245f*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52460*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52461*4+0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x52462*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52463*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x52464*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52465*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52466*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52467*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52468*4+0x02000000,0xa06); +reg_write( DDR_REG_BASE +0x52469*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5246a*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5246b*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x5246c*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x5246d*4+0x02000000,0xf8da); +reg_write( DDR_REG_BASE +0x5246e*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5246f*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52470*4+0x02000000,0x9f6); +reg_write( DDR_REG_BASE +0x52471*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52472*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52473*4+0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x52474*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52475*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52476*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52477*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52478*4+0x02000000,0xc305); +reg_write( DDR_REG_BASE +0x52479*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5247a*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5247b*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5247c*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5247d*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5247e*4+0x02000000,0x9da); +reg_write( DDR_REG_BASE +0x5247f*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52480*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52481*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x52482*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x52483*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52484*4+0x02000000,0x2100); +reg_write( DDR_REG_BASE +0x52485*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52486*4+0x02000000,0xf26c); +reg_write( DDR_REG_BASE +0x52487*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52488*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52489*4+0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x5248a*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x5248b*4+0x02000000,0x4358); +reg_write( DDR_REG_BASE +0x5248c*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5248d*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5248e*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5248f*4+0x02000000,0x9ba); +reg_write( DDR_REG_BASE +0x52490*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52491*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52492*4+0x02000000,0xf8ca); +reg_write( DDR_REG_BASE +0x52493*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52494*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52495*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x52496*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52497*4+0x02000000,0x9aa); +reg_write( DDR_REG_BASE +0x52498*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52499*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5249a*4+0x02000000,0xf8bd); +reg_write( DDR_REG_BASE +0x5249b*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x5249c*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x5249d*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5249e*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5249f*4+0x02000000,0x99a); +reg_write( DDR_REG_BASE +0x524a0*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524a1*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524a2*4+0x02000000,0xf8cb); +reg_write( DDR_REG_BASE +0x524a3*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x524a4*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x524a5*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x524a6*4+0x02000000,0x98a); +reg_write( DDR_REG_BASE +0x524a7*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524a8*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524a9*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x524aa*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x524ab*4+0x02000000,0xf8be); +reg_write( DDR_REG_BASE +0x524ac*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x524ad*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x524ae*4+0x02000000,0x97a); +reg_write( DDR_REG_BASE +0x524af*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524b0*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524b1*4+0x02000000,0xf8b2); +reg_write( DDR_REG_BASE +0x524b2*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x524b3*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x524b4*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x524b5*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x524b6*4+0x02000000,0x96a); +reg_write( DDR_REG_BASE +0x524b7*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524b8*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524b9*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x524ba*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x524bb*4+0x02000000,0xf8ad); +reg_write( DDR_REG_BASE +0x524bc*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x524bd*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x524be*4+0x02000000,0x95a); +reg_write( DDR_REG_BASE +0x524bf*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524c0*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524c1*4+0x02000000,0xf8bc); +reg_write( DDR_REG_BASE +0x524c2*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x524c3*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x524c4*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x524c5*4+0x02000000,0x94e); +reg_write( DDR_REG_BASE +0x524c6*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524c7*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524c8*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x524c9*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x524ca*4+0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x524cb*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x524cc*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x524cd*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x524ce*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x524cf*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x524d0*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x524d1*4+0x02000000,0x936); +reg_write( DDR_REG_BASE +0x524d2*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524d3*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524d4*4+0x02000000,0xf8a0); +reg_write( DDR_REG_BASE +0x524d5*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x524d6*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x524d7*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x524d8*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x524d9*4+0x02000000,0x926); +reg_write( DDR_REG_BASE +0x524da*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524db*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524dc*4+0x02000000,0xf8ae); +reg_write( DDR_REG_BASE +0x524dd*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x524de*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x524df*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x524e0*4+0x02000000,0x916); +reg_write( DDR_REG_BASE +0x524e1*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524e2*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524e3*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x524e4*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x524e5*4+0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x524e6*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x524e7*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x524e8*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x524e9*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x524ea*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x524eb*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x524ec*4+0x02000000,0x8fe); +reg_write( DDR_REG_BASE +0x524ed*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524ee*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524ef*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x524f0*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x524f1*4+0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x524f2*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x524f3*4+0x02000000,0x3441); +reg_write( DDR_REG_BASE +0x524f4*4+0x02000000,0xf890); +reg_write( DDR_REG_BASE +0x524f5*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x524f6*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x524f7*4+0x02000000,0x8ea); +reg_write( DDR_REG_BASE +0x524f8*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524f9*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524fa*4+0x02000000,0xc305); +reg_write( DDR_REG_BASE +0x524fb*4+0x02000000,0xf88a); +reg_write( DDR_REG_BASE +0x524fc*4+0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x524fd*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x524fe*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x524ff*4+0x02000000,0x8da); +reg_write( DDR_REG_BASE +0x52500*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52501*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x52502*4+0x02000000,0xf880); +reg_write( DDR_REG_BASE +0x52503*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x52504*4+0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x52505*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52506*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52507*4+0x02000000,0x8ca); +reg_write( DDR_REG_BASE +0x52508*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52509*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5250a*4+0x02000000,0xf891); +reg_write( DDR_REG_BASE +0x5250b*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5250c*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5250d*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5250e*4+0x02000000,0x8ba); +reg_write( DDR_REG_BASE +0x5250f*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52510*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52511*4+0x02000000,0xae6); +reg_write( DDR_REG_BASE +0x52512*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52513*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52514*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52515*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52516*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52517*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52518*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x52519*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x5251a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5251b*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x5251c*4+0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x5251d*4+0x02000000,0xf0c7); +reg_write( DDR_REG_BASE +0x5251e*4+0x02000000,0xf4c8); +reg_write( DDR_REG_BASE +0x5251f*4+0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x52520*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x52521*4+0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x52522*4+0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x52523*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x52524*4+0x02000000,0x4918); +reg_write( DDR_REG_BASE +0x52525*4+0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x52526*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x52527*4+0x02000000,0x4918); +reg_write( DDR_REG_BASE +0x52528*4+0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x52529*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5252a*4+0x02000000,0xf062); +reg_write( DDR_REG_BASE +0x5252b*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5252c*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x5252d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5252e*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x5252f*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52530*4+0x02000000,0x7dc0); +reg_write( DDR_REG_BASE +0x52531*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52532*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x52533*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x52534*4+0x02000000,0xf12); +reg_write( DDR_REG_BASE +0x52535*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52536*4+0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x52537*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52538*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x52539*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x5253a*4+0x02000000,0x7b10); +reg_write( DDR_REG_BASE +0x5253b*4+0x02000000,0xd808); +reg_write( DDR_REG_BASE +0x5253c*4+0x02000000,0xf02); +reg_write( DDR_REG_BASE +0x5253d*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x5253e*4+0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x5253f*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52540*4+0x02000000,0xf7e); +reg_write( DDR_REG_BASE +0x52541*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52542*4+0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x52543*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x52544*4+0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x52545*4+0x02000000,0xf865); +reg_write( DDR_REG_BASE +0x52546*4+0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x52547*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x52548*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x52549*4+0x02000000,0x846); +reg_write( DDR_REG_BASE +0x5254a*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5254b*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x5254c*4+0x02000000,0xf85e); +reg_write( DDR_REG_BASE +0x5254d*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5254e*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5254f*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52550*4+0x02000000,0x836); +reg_write( DDR_REG_BASE +0x52551*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52552*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52553*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52554*4+0x02000000,0x736f); +reg_write( DDR_REG_BASE +0x52555*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52556*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52557*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x52558*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52559*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5255a*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x5255b*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x5255c*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x5255d*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x5255e*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5255f*4+0x02000000,0x81a); +reg_write( DDR_REG_BASE +0x52560*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52561*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x52562*4+0x02000000,0x3281); +reg_write( DDR_REG_BASE +0x52563*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x52564*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52565*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x52566*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52567*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52568*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x52569*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x5256a*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x5256b*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5256c*4+0x02000000,0xffe); +reg_write( DDR_REG_BASE +0x5256d*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5256e*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5256f*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52570*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52571*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x52572*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x52573*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x52574*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52575*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52576*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52577*4+0x02000000,0xfea); +reg_write( DDR_REG_BASE +0x52578*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52579*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x5257a*4+0x02000000,0x3281); +reg_write( DDR_REG_BASE +0x5257b*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x5257c*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x5257d*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5257e*4+0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x5257f*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52580*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52581*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52582*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52583*4+0x02000000,0xfd2); +reg_write( DDR_REG_BASE +0x52584*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52585*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52586*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52587*4+0x02000000,0xf8a); +reg_write( DDR_REG_BASE +0x52588*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52589*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5258a*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5258b*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5258c*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5258d*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x5258e*4+0x02000000,0x232f); +reg_write( DDR_REG_BASE +0x5258f*4+0x02000000,0x3007); +reg_write( DDR_REG_BASE +0x52590*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52591*4+0x02000000,0x837); +reg_write( DDR_REG_BASE +0x52592*4+0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x52593*4+0x02000000,0x7bf0); +reg_write( DDR_REG_BASE +0x52594*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52595*4+0x02000000,0xed6); +reg_write( DDR_REG_BASE +0x52596*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52597*4+0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x52598*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x52599*4+0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x5259a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5259b*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5259c*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5259d*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x5259e*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x5259f*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x525a0*4+0x02000000,0xf96); +reg_write( DDR_REG_BASE +0x525a1*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x525a2*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x525a3*4+0x02000000,0x9de); +reg_write( DDR_REG_BASE +0x525a4*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x525a5*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x525a6*4+0x02000000,0xf831); +reg_write( DDR_REG_BASE +0x525a7*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x525a8*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x525a9*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x525aa*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x525ab*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x525ac*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x525ad*4+0x02000000,0xca08); +reg_write( DDR_REG_BASE +0x525ae*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x525af*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x525b0*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x525b1*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x525b2*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x525b3*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x525b4*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x525b5*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x525b6*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x525b7*4+0x02000000,0xf6a); +reg_write( DDR_REG_BASE +0x525b8*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x525b9*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x525ba*4+0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x525bb*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x525bc*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x525bd*4+0x02000000,0x2054); +reg_write( DDR_REG_BASE +0x525be*4+0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x525bf*4+0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x525c0*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x525c1*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x525c2*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x525c3*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x525c4*4+0x02000000,0xf4e); +reg_write( DDR_REG_BASE +0x525c5*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x525c6*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x525c7*4+0x02000000,0xf81e); +reg_write( DDR_REG_BASE +0x525c8*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x525c9*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x525ca*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x525cb*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x525cc*4+0x02000000,0xf3e); +reg_write( DDR_REG_BASE +0x525cd*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x525ce*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x525cf*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x525d0*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x525d1*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x525d2*4+0x02000000,0xdb50); +reg_write( DDR_REG_BASE +0x525d3*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x525d4*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x525d5*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x525d6*4+0x02000000,0xf2a); +reg_write( DDR_REG_BASE +0x525d7*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x525d8*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x525d9*4+0x02000000,0x956); +reg_write( DDR_REG_BASE +0x525da*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x525db*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x525dc*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x525dd*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x525de*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x525df*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x525e0*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x525e1*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x525e2*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x525e3*4+0x02000000,0xf12); +reg_write( DDR_REG_BASE +0x525e4*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x525e5*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x525e6*4+0x02000000,0xc0ad); +reg_write( DDR_REG_BASE +0x525e7*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x525e8*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x525e9*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x525ea*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x525eb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x525ec*4+0x02000000,0xaaaa); +reg_write( DDR_REG_BASE +0x525ed*4+0x02000000,0xf214); +reg_write( DDR_REG_BASE +0x525ee*4+0x02000000,0xb17); +reg_write( DDR_REG_BASE +0x525ef*4+0x02000000,0x3190); +reg_write( DDR_REG_BASE +0x525f0*4+0x02000000,0xb1b); +reg_write( DDR_REG_BASE +0x525f1*4+0x02000000,0x3150); +reg_write( DDR_REG_BASE +0x525f2*4+0x02000000,0xb1d); +reg_write( DDR_REG_BASE +0x525f3*4+0x02000000,0x3131); +reg_write( DDR_REG_BASE +0x525f4*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x525f5*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x525f6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x525f7*4+0x02000000,0xcccc); +reg_write( DDR_REG_BASE +0x525f8*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x525f9*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x525fa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x525fb*4+0x02000000,0x8282); +reg_write( DDR_REG_BASE +0x525fc*4+0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x525fd*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x525fe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x525ff*4+0x02000000,0xb2b2); +reg_write( DDR_REG_BASE +0x52600*4+0x02000000,0x20f); +reg_write( DDR_REG_BASE +0x52601*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x52602*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52603*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52604*4+0x02000000,0xb98f); +reg_write( DDR_REG_BASE +0x52605*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52606*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52607*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52608*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52609*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5260a*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5260b*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5260c*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5260d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5260e*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5260f*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52610*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52611*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x52612*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52613*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52614*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52615*4+0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x52616*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52617*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x52618*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52619*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5261a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5261b*4+0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x5261c*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x5261d*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x5261e*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5261f*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52620*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52621*4+0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x52622*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x52623*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x52624*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52625*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52626*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52627*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52628*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52629*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x5262a*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5262b*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5262c*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5262d*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5262e*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5262f*4+0x02000000,0xdb30); +reg_write( DDR_REG_BASE +0x52630*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52631*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52632*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52633*4+0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x52634*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x52635*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52636*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52637*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52638*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52639*4+0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x5263a*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x5263b*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x5263c*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5263d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5263e*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5263f*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52640*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52641*4+0x02000000,0xc1a6); +reg_write( DDR_REG_BASE +0x52642*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x52643*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52644*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x52645*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52646*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x52647*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x52648*4+0x02000000,0xffd); +reg_write( DDR_REG_BASE +0x52649*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x5264a*4+0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x5264b*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5264c*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5264d*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x5264e*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x5264f*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x52650*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52651*4+0x02000000,0x8e19); +reg_write( DDR_REG_BASE +0x52652*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52653*4+0x02000000,0x8e10); +reg_write( DDR_REG_BASE +0x52654*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52655*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52656*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x52657*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x52658*4+0x02000000,0x9001); +reg_write( DDR_REG_BASE +0x52659*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5265a*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5265b*4+0x02000000,0xe88a); +reg_write( DDR_REG_BASE +0x5265c*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5265d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5265e*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x5265f*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x52660*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x52661*4+0x02000000,0xcfe); +reg_write( DDR_REG_BASE +0x52662*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52663*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x52664*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52665*4+0x02000000,0x956); +reg_write( DDR_REG_BASE +0x52666*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52667*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52668*4+0x02000000,0x8608); +reg_write( DDR_REG_BASE +0x52669*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x5266a*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5266b*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5266c*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5266d*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5266e*4+0x02000000,0xe064); +reg_write( DDR_REG_BASE +0x5266f*4+0x02000000,0xce6); +reg_write( DDR_REG_BASE +0x52670*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x52671*4+0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x52672*4+0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x52673*4+0x02000000,0xaba); +reg_write( DDR_REG_BASE +0x52674*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x52675*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52676*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52677*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52678*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52679*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x5267a*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x5267b*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x5267c*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5267d*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5267e*4+0x02000000,0xe064); +reg_write( DDR_REG_BASE +0x5267f*4+0x02000000,0x2042); +reg_write( DDR_REG_BASE +0x52680*4+0x02000000,0x98f); +reg_write( DDR_REG_BASE +0x52681*4+0x02000000,0xb7a0); +reg_write( DDR_REG_BASE +0x52682*4+0x02000000,0xb7a0); +reg_write( DDR_REG_BASE +0x52683*4+0x02000000,0x1f9c); +reg_write( DDR_REG_BASE +0x52684*4+0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x52685*4+0x02000000,0x1f9b); +reg_write( DDR_REG_BASE +0x52686*4+0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x52687*4+0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x52688*4+0x02000000,0x9f84); +reg_write( DDR_REG_BASE +0x52689*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5268a*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x5268b*4+0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x5268c*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x5268d*4+0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x5268e*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x5268f*4+0x02000000,0xd7a); +reg_write( DDR_REG_BASE +0x52690*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52691*4+0x02000000,0x960e); +reg_write( DDR_REG_BASE +0x52692*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x52693*4+0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x52694*4+0x02000000,0xcaa); +reg_write( DDR_REG_BASE +0x52695*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52696*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52697*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52698*4+0x02000000,0x8ee); +reg_write( DDR_REG_BASE +0x52699*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5269a*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x5269b*4+0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x5269c*4+0x02000000,0xa66); +reg_write( DDR_REG_BASE +0x5269d*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5269e*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5269f*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x526a0*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x526a1*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x526a2*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x526a3*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x526a4*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x526a5*4+0x02000000,0xb7a0); +reg_write( DDR_REG_BASE +0x526a6*4+0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x526a7*4+0x02000000,0x9f84); +reg_write( DDR_REG_BASE +0x526a8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x526a9*4+0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x526aa*4+0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x526ab*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x526ac*4+0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x526ad*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x526ae*4+0x02000000,0xd3a); +reg_write( DDR_REG_BASE +0x526af*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x526b0*4+0x02000000,0x960a); +reg_write( DDR_REG_BASE +0x526b1*4+0x02000000,0x8e58); +reg_write( DDR_REG_BASE +0x526b2*4+0x02000000,0x8601); +reg_write( DDR_REG_BASE +0x526b3*4+0x02000000,0xbde); +reg_write( DDR_REG_BASE +0x526b4*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x526b5*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x526b6*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x526b7*4+0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x526b8*4+0x02000000,0xc62); +reg_write( DDR_REG_BASE +0x526b9*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x526ba*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x526bb*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x526bc*4+0x02000000,0x8a6); +reg_write( DDR_REG_BASE +0x526bd*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x526be*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x526bf*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x526c0*4+0x02000000,0xe807); +reg_write( DDR_REG_BASE +0x526c1*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x526c2*4+0x02000000,0xfba); +reg_write( DDR_REG_BASE +0x526c3*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x526c4*4+0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x526c5*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x526c6*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x526c7*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x526c8*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x526c9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x526ca*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x526cb*4+0x02000000,0x4220); +reg_write( DDR_REG_BASE +0x526cc*4+0x02000000,0x7414); +reg_write( DDR_REG_BASE +0x526cd*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x526ce*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x526cf*4+0x02000000,0xfffe); +reg_write( DDR_REG_BASE +0x526d0*4+0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x526d1*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x526d2*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x526d3*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x526d4*4+0x02000000,0xc16); +reg_write( DDR_REG_BASE +0x526d5*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x526d6*4+0x02000000,0x4320); +reg_write( DDR_REG_BASE +0x526d7*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x526d8*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x526d9*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x526da*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x526db*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x526dc*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x526dd*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x526de*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x526df*4+0x02000000,0x9001); +reg_write( DDR_REG_BASE +0x526e0*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x526e1*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x526e2*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x526e3*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x526e4*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x526e5*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x526e6*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x526e7*4+0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x526e8*4+0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x526e9*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x526ea*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x526eb*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x526ec*4+0x02000000,0x7504); +reg_write( DDR_REG_BASE +0x526ed*4+0x02000000,0x9c6); +reg_write( DDR_REG_BASE +0x526ee*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x526ef*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x526f0*4+0x02000000,0x8608); +reg_write( DDR_REG_BASE +0x526f1*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x526f2*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x526f3*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x526f4*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x526f5*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x526f6*4+0x02000000,0xe064); +reg_write( DDR_REG_BASE +0x526f7*4+0x02000000,0xbd6); +reg_write( DDR_REG_BASE +0x526f8*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x526f9*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x526fa*4+0x02000000,0x6c4); +reg_write( DDR_REG_BASE +0x526fb*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x526fc*4+0x02000000,0x1f00); +reg_write( DDR_REG_BASE +0x526fd*4+0x02000000,0x16c4); +reg_write( DDR_REG_BASE +0x526fe*4+0x02000000,0x1f9c); +reg_write( DDR_REG_BASE +0x526ff*4+0x02000000,0x16dc); +reg_write( DDR_REG_BASE +0x52700*4+0x02000000,0x1f9b); +reg_write( DDR_REG_BASE +0x52701*4+0x02000000,0x16dc); +reg_write( DDR_REG_BASE +0x52702*4+0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x52703*4+0x02000000,0x9f84); +reg_write( DDR_REG_BASE +0x52704*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52705*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x52706*4+0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x52707*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x52708*4+0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x52709*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x5270a*4+0x02000000,0x960e); +reg_write( DDR_REG_BASE +0x5270b*4+0x02000000,0xc82); +reg_write( DDR_REG_BASE +0x5270c*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5270d*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x5270e*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x5270f*4+0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x52710*4+0x02000000,0xbb2); +reg_write( DDR_REG_BASE +0x52711*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52712*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52713*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52714*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52715*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52716*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52717*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x52718*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x52719*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x5271a*4+0x02000000,0xfea); +reg_write( DDR_REG_BASE +0x5271b*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5271c*4+0x02000000,0x1f00); +reg_write( DDR_REG_BASE +0x5271d*4+0x02000000,0x16c4); +reg_write( DDR_REG_BASE +0x5271e*4+0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x5271f*4+0x02000000,0x962); +reg_write( DDR_REG_BASE +0x52720*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x52721*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52722*4+0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x52723*4+0x02000000,0x9f84); +reg_write( DDR_REG_BASE +0x52724*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52725*4+0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x52726*4+0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x52727*4+0x02000000,0x9344); +reg_write( DDR_REG_BASE +0x52728*4+0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x52729*4+0x02000000,0x9344); +reg_write( DDR_REG_BASE +0x5272a*4+0x02000000,0x8605); +reg_write( DDR_REG_BASE +0x5272b*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5272c*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5272d*4+0x02000000,0xc3e); +reg_write( DDR_REG_BASE +0x5272e*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5272f*4+0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x52730*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x52731*4+0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x52732*4+0x02000000,0xb6e); +reg_write( DDR_REG_BASE +0x52733*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52734*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52735*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52736*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x52737*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52738*4+0x02000000,0xece); +reg_write( DDR_REG_BASE +0x52739*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5273a*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x5273b*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5273c*4+0x02000000,0x8e58); +reg_write( DDR_REG_BASE +0x5273d*4+0x02000000,0x8603); +reg_write( DDR_REG_BASE +0x5273e*4+0x02000000,0xac6); +reg_write( DDR_REG_BASE +0x5273f*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52740*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52741*4+0x02000000,0xc0a6); +reg_write( DDR_REG_BASE +0x52742*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52743*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52744*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52745*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52746*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52747*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52748*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52749*4+0x02000000,0xc1a8); +reg_write( DDR_REG_BASE +0x5274a*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x5274b*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5274c*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x5274d*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x5274e*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x5274f*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x52750*4+0x02000000,0xffd); +reg_write( DDR_REG_BASE +0x52751*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x52752*4+0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x52753*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52754*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52755*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x52756*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x52757*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x52758*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52759*4+0x02000000,0x8e19); +reg_write( DDR_REG_BASE +0x5275a*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5275b*4+0x02000000,0x8e10); +reg_write( DDR_REG_BASE +0x5275c*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5275d*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5275e*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x5275f*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x52760*4+0x02000000,0x9001); +reg_write( DDR_REG_BASE +0x52761*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52762*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52763*4+0x02000000,0xe88a); +reg_write( DDR_REG_BASE +0x52764*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52765*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52766*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x52767*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x52768*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x52769*4+0x02000000,0xaee); +reg_write( DDR_REG_BASE +0x5276a*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x5276b*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x5276c*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x5276d*4+0x02000000,0xf46); +reg_write( DDR_REG_BASE +0x5276e*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5276f*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52770*4+0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x52771*4+0x02000000,0x8608); +reg_write( DDR_REG_BASE +0x52772*4+0x02000000,0x2179); +reg_write( DDR_REG_BASE +0x52773*4+0x02000000,0x101); +reg_write( DDR_REG_BASE +0x52774*4+0x02000000,0xb52); +reg_write( DDR_REG_BASE +0x52775*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52776*4+0x02000000,0xc144); +reg_write( DDR_REG_BASE +0x52777*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52778*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52779*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x5277a*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x5277b*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x5277c*4+0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x5277d*4+0x02000000,0x8a6); +reg_write( DDR_REG_BASE +0x5277e*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5277f*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x52780*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52781*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x52782*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52783*4+0x02000000,0xe03e); +reg_write( DDR_REG_BASE +0x52784*4+0x02000000,0xb7a0); +reg_write( DDR_REG_BASE +0x52785*4+0x02000000,0x1f9b); +reg_write( DDR_REG_BASE +0x52786*4+0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x52787*4+0x02000000,0x1f9c); +reg_write( DDR_REG_BASE +0x52788*4+0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x52789*4+0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x5278a*4+0x02000000,0x9f84); +reg_write( DDR_REG_BASE +0x5278b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5278c*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x5278d*4+0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x5278e*4+0x02000000,0x9045); +reg_write( DDR_REG_BASE +0x5278f*4+0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x52790*4+0x02000000,0x9045); +reg_write( DDR_REG_BASE +0x52791*4+0x02000000,0x960e); +reg_write( DDR_REG_BASE +0x52792*4+0x02000000,0xb72); +reg_write( DDR_REG_BASE +0x52793*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52794*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52795*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x52796*4+0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x52797*4+0x02000000,0xaa6); +reg_write( DDR_REG_BASE +0x52798*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52799*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x5279a*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x5279b*4+0x02000000,0xeea); +reg_write( DDR_REG_BASE +0x5279c*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5279d*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x5279e*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x5279f*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x527a0*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x527a1*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x527a2*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x527a3*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x527a4*4+0x02000000,0xb7a0); +reg_write( DDR_REG_BASE +0x527a5*4+0x02000000,0xb4e); +reg_write( DDR_REG_BASE +0x527a6*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x527a7*4+0x02000000,0x960a); +reg_write( DDR_REG_BASE +0x527a8*4+0x02000000,0x8e58); +reg_write( DDR_REG_BASE +0x527a9*4+0x02000000,0x8602); +reg_write( DDR_REG_BASE +0x527aa*4+0x02000000,0x9ee); +reg_write( DDR_REG_BASE +0x527ab*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x527ac*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x527ad*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x527ae*4+0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x527af*4+0x02000000,0xa76); +reg_write( DDR_REG_BASE +0x527b0*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x527b1*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x527b2*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x527b3*4+0x02000000,0xeba); +reg_write( DDR_REG_BASE +0x527b4*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x527b5*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x527b6*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x527b7*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x527b8*4+0x02000000,0xdce); +reg_write( DDR_REG_BASE +0x527b9*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x527ba*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x527bb*4+0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x527bc*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x527bd*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x527be*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x527bf*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x527c0*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x527c1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x527c2*4+0x02000000,0xfffe); +reg_write( DDR_REG_BASE +0x527c3*4+0x02000000,0x7414); +reg_write( DDR_REG_BASE +0x527c4*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x527c5*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x527c6*4+0x02000000,0x81); +reg_write( DDR_REG_BASE +0x527c7*4+0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x527c8*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x527c9*4+0x02000000,0xa2e); +reg_write( DDR_REG_BASE +0x527ca*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x527cb*4+0x02000000,0x4320); +reg_write( DDR_REG_BASE +0x527cc*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x527cd*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x527ce*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x527cf*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x527d0*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x527d1*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x527d2*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x527d3*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x527d4*4+0x02000000,0x9001); +reg_write( DDR_REG_BASE +0x527d5*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x527d6*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x527d7*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x527d8*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x527d9*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x527da*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x527db*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x527dc*4+0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x527dd*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x527de*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x527df*4+0x02000000,0xe007); +reg_write( DDR_REG_BASE +0x527e0*4+0x02000000,0xfde); +reg_write( DDR_REG_BASE +0x527e1*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x527e2*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x527e3*4+0x02000000,0x8608); +reg_write( DDR_REG_BASE +0x527e4*4+0x02000000,0xa72); +reg_write( DDR_REG_BASE +0x527e5*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x527e6*4+0x02000000,0xc104); +reg_write( DDR_REG_BASE +0x527e7*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x527e8*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x527e9*4+0x02000000,0x1f00); +reg_write( DDR_REG_BASE +0x527ea*4+0x02000000,0x16c4); +reg_write( DDR_REG_BASE +0x527eb*4+0x02000000,0x1f9b); +reg_write( DDR_REG_BASE +0x527ec*4+0x02000000,0x16dc); +reg_write( DDR_REG_BASE +0x527ed*4+0x02000000,0x1f9c); +reg_write( DDR_REG_BASE +0x527ee*4+0x02000000,0x16dc); +reg_write( DDR_REG_BASE +0x527ef*4+0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x527f0*4+0x02000000,0x9f84); +reg_write( DDR_REG_BASE +0x527f1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x527f2*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x527f3*4+0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x527f4*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x527f5*4+0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x527f6*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x527f7*4+0x02000000,0x960e); +reg_write( DDR_REG_BASE +0x527f8*4+0x02000000,0xaa6); +reg_write( DDR_REG_BASE +0x527f9*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x527fa*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x527fb*4+0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x527fc*4+0x02000000,0xc200); +reg_write( DDR_REG_BASE +0x527fd*4+0x02000000,0x9da); +reg_write( DDR_REG_BASE +0x527fe*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x527ff*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52800*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x52801*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52802*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52803*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52804*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x52805*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x52806*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52807*4+0x02000000,0xe12); +reg_write( DDR_REG_BASE +0x52808*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52809*4+0x02000000,0x1f00); +reg_write( DDR_REG_BASE +0x5280a*4+0x02000000,0x16c4); +reg_write( DDR_REG_BASE +0x5280b*4+0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x5280c*4+0x02000000,0xf86); +reg_write( DDR_REG_BASE +0x5280d*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5280e*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5280f*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52810*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52811*4+0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x52812*4+0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x52813*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52814*4+0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x52815*4+0x02000000,0x9344); +reg_write( DDR_REG_BASE +0x52816*4+0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x52817*4+0x02000000,0x9344); +reg_write( DDR_REG_BASE +0x52818*4+0x02000000,0x8605); +reg_write( DDR_REG_BASE +0x52819*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5281a*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5281b*4+0x02000000,0xa62); +reg_write( DDR_REG_BASE +0x5281c*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5281d*4+0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x5281e*4+0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x5281f*4+0x02000000,0xc200); +reg_write( DDR_REG_BASE +0x52820*4+0x02000000,0x992); +reg_write( DDR_REG_BASE +0x52821*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52822*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52823*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52824*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x52825*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52826*4+0x02000000,0xcf2); +reg_write( DDR_REG_BASE +0x52827*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52828*4+0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x52829*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5282a*4+0x02000000,0x8e58); +reg_write( DDR_REG_BASE +0x5282b*4+0x02000000,0x8603); +reg_write( DDR_REG_BASE +0x5282c*4+0x02000000,0x8ea); +reg_write( DDR_REG_BASE +0x5282d*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5282e*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5282f*4+0x02000000,0xc0a8); +reg_write( DDR_REG_BASE +0x52830*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52831*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52832*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52833*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52834*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52835*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52836*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52837*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x52838*4+0x02000000,0x3503); +reg_write( DDR_REG_BASE +0x52839*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x5283a*4+0x02000000,0xdf6); +reg_write( DDR_REG_BASE +0x5283b*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5283c*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5283d*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5283e*4+0x02000000,0x7083); +reg_write( DDR_REG_BASE +0x5283f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52840*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52841*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52842*4+0x02000000,0xc088); +reg_write( DDR_REG_BASE +0x52843*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x52844*4+0x02000000,0xb52); +reg_write( DDR_REG_BASE +0x52845*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x52846*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x52847*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52848*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52849*4+0x02000000,0x2100); +reg_write( DDR_REG_BASE +0x5284a*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5284b*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x5284c*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5284d*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x5284e*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5284f*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52850*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52851*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52852*4+0x02000000,0xfec4); +reg_write( DDR_REG_BASE +0x52853*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x52854*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x52855*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x52856*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52857*4+0x02000000,0x4898); +reg_write( DDR_REG_BASE +0x52858*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52859*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x5285a*4+0x02000000,0xc145); +reg_write( DDR_REG_BASE +0x5285b*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5285c*4+0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x5285d*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x5285e*4+0x02000000,0x6941); +reg_write( DDR_REG_BASE +0x5285f*4+0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x52860*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x52861*4+0x02000000,0x44a9); +reg_write( DDR_REG_BASE +0x52862*4+0x02000000,0xe805); +reg_write( DDR_REG_BASE +0x52863*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x52864*4+0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x52865*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x52866*4+0x02000000,0x7c9b); +reg_write( DDR_REG_BASE +0x52867*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x52868*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52869*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5286a*4+0x02000000,0xe0c4); +reg_write( DDR_REG_BASE +0x5286b*4+0x02000000,0xb080); +reg_write( DDR_REG_BASE +0x5286c*4+0x02000000,0x4140); +reg_write( DDR_REG_BASE +0x5286d*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5286e*4+0x02000000,0x9e1); +reg_write( DDR_REG_BASE +0x5286f*4+0x02000000,0x8024); +reg_write( DDR_REG_BASE +0x52870*4+0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x52871*4+0x02000000,0x7c0); +reg_write( DDR_REG_BASE +0x52872*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x52873*4+0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x52874*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52875*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52876*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52877*4+0x02000000,0x709b); +reg_write( DDR_REG_BASE +0x52878*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52879*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x5287a*4+0x02000000,0xc346); +reg_write( DDR_REG_BASE +0x5287b*4+0x02000000,0xe598); +reg_write( DDR_REG_BASE +0x5287c*4+0x02000000,0x1d8); +reg_write( DDR_REG_BASE +0x5287d*4+0x02000000,0xd); +reg_write( DDR_REG_BASE +0x5287e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5287f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52880*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x52881*4+0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x52882*4+0x02000000,0xf015); +reg_write( DDR_REG_BASE +0x52883*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52884*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x52885*4+0x02000000,0x8c2); +reg_write( DDR_REG_BASE +0x52886*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52887*4+0x02000000,0x7a05); +reg_write( DDR_REG_BASE +0x52888*4+0x02000000,0xd8ef); +reg_write( DDR_REG_BASE +0x52889*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x5288a*4+0x02000000,0x6c0); +reg_write( DDR_REG_BASE +0x5288b*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x5288c*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5288d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5288e*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x5288f*4+0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x52890*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x52891*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52892*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52893*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52894*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52895*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52896*4+0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x52897*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x52898*4+0x02000000,0x6c7); +reg_write( DDR_REG_BASE +0x52899*4+0x02000000,0x9d7); +reg_write( DDR_REG_BASE +0x5289a*4+0x02000000,0x8005); +reg_write( DDR_REG_BASE +0x5289b*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5289c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5289d*4+0x02000000,0x2100); +reg_write( DDR_REG_BASE +0x5289e*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5289f*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x528a0*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x528a1*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x528a2*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x528a3*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x528a4*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x528a5*4+0x02000000,0xfe64); +reg_write( DDR_REG_BASE +0x528a6*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x528a7*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x528a8*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x528a9*4+0x02000000,0xf064); +reg_write( DDR_REG_BASE +0x528aa*4+0x02000000,0x711c); +reg_write( DDR_REG_BASE +0x528ab*4+0x02000000,0x86e); +reg_write( DDR_REG_BASE +0x528ac*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x528ad*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x528ae*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x528af*4+0x02000000,0x866); +reg_write( DDR_REG_BASE +0x528b0*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x528b1*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x528b2*4+0x02000000,0xcba); +reg_write( DDR_REG_BASE +0x528b3*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x528b4*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x528b5*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x528b6*4+0x02000000,0xe32); +reg_write( DDR_REG_BASE +0x528b7*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x528b8*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x528b9*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x528ba*4+0x02000000,0xdf7f); +reg_write( DDR_REG_BASE +0x528bb*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x528bc*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x528bd*4+0x02000000,0xe024); +reg_write( DDR_REG_BASE +0x528be*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x528bf*4+0x02000000,0xb6e0); +reg_write( DDR_REG_BASE +0x528c0*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x528c1*4+0x02000000,0xb606); +reg_write( DDR_REG_BASE +0x528c2*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x528c3*4+0x02000000,0x3c4); +reg_write( DDR_REG_BASE +0x528c4*4+0x02000000,0x1efe); +reg_write( DDR_REG_BASE +0x528c5*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x528c6*4+0x02000000,0xd818); +reg_write( DDR_REG_BASE +0x528c7*4+0x02000000,0x90a); +reg_write( DDR_REG_BASE +0x528c8*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x528c9*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x528ca*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x528cb*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x528cc*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x528cd*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x528ce*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x528cf*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x528d0*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x528d1*4+0x02000000,0xc7e); +reg_write( DDR_REG_BASE +0x528d2*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x528d3*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x528d4*4+0x02000000,0xd807); +reg_write( DDR_REG_BASE +0x528d5*4+0x02000000,0x8ee); +reg_write( DDR_REG_BASE +0x528d6*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x528d7*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x528d8*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x528d9*4+0x02000000,0xb6e0); +reg_write( DDR_REG_BASE +0x528da*4+0x02000000,0xb606); +reg_write( DDR_REG_BASE +0x528db*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x528dc*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x528dd*4+0x02000000,0xc66); +reg_write( DDR_REG_BASE +0x528de*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x528df*4+0x02000000,0x1efe); +reg_write( DDR_REG_BASE +0x528e0*4+0x02000000,0x93c5); +reg_write( DDR_REG_BASE +0x528e1*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x528e2*4+0x02000000,0x8d2); +reg_write( DDR_REG_BASE +0x528e3*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x528e4*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x528e5*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x528e6*4+0x02000000,0xc52); +reg_write( DDR_REG_BASE +0x528e7*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x528e8*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x528e9*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x528ea*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x528eb*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x528ec*4+0x02000000,0x1fc5); +reg_write( DDR_REG_BASE +0x528ed*4+0x02000000,0x1e0c); +reg_write( DDR_REG_BASE +0x528ee*4+0x02000000,0x1fc5); +reg_write( DDR_REG_BASE +0x528ef*4+0x02000000,0x8ba); +reg_write( DDR_REG_BASE +0x528f0*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x528f1*4+0x02000000,0x1efe); +reg_write( DDR_REG_BASE +0x528f2*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x528f3*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x528f4*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x528f5*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x528f6*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x528f7*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x528f8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x528f9*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x528fa*4+0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x528fb*4+0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x528fc*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x528fd*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x528fe*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x528ff*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x52900*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x52901*4+0x02000000,0xf05f); +reg_write( DDR_REG_BASE +0x52902*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x52903*4+0x02000000,0xf9f); +reg_write( DDR_REG_BASE +0x52904*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52905*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52906*4+0x02000000,0xc602); +reg_write( DDR_REG_BASE +0x52907*4+0x02000000,0xc400); +reg_write( DDR_REG_BASE +0x52908*4+0x02000000,0xf053); +reg_write( DDR_REG_BASE +0x52909*4+0x02000000,0x225f); +reg_write( DDR_REG_BASE +0x5290a*4+0x02000000,0x480); +reg_write( DDR_REG_BASE +0x5290b*4+0x02000000,0x74d5); +reg_write( DDR_REG_BASE +0x5290c*4+0x02000000,0x24c0); +reg_write( DDR_REG_BASE +0x5290d*4+0x02000000,0x1061); +reg_write( DDR_REG_BASE +0x5290e*4+0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x5290f*4+0x02000000,0x1061); +reg_write( DDR_REG_BASE +0x52910*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52911*4+0x02000000,0xc301); +reg_write( DDR_REG_BASE +0x52912*4+0x02000000,0xc088); +reg_write( DDR_REG_BASE +0x52913*4+0x02000000,0x631b); +reg_write( DDR_REG_BASE +0x52914*4+0x02000000,0x7bd4); +reg_write( DDR_REG_BASE +0x52915*4+0x02000000,0x9300); +reg_write( DDR_REG_BASE +0x52916*4+0x02000000,0xe0c0); +reg_write( DDR_REG_BASE +0x52917*4+0x02000000,0x88); +reg_write( DDR_REG_BASE +0x52918*4+0x02000000,0x25); +reg_write( DDR_REG_BASE +0x52919*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x5291a*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x5291b*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5291c*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5291d*4+0x02000000,0x7c0); +reg_write( DDR_REG_BASE +0x5291e*4+0x02000000,0x7f1b); +reg_write( DDR_REG_BASE +0x5291f*4+0x02000000,0x2705); +reg_write( DDR_REG_BASE +0x52920*4+0x02000000,0x178f); +reg_write( DDR_REG_BASE +0x52921*4+0x02000000,0x9700); +reg_write( DDR_REG_BASE +0x52922*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52923*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52924*4+0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x52925*4+0x02000000,0x1021); +reg_write( DDR_REG_BASE +0x52926*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x52927*4+0x02000000,0x21); +reg_write( DDR_REG_BASE +0x52928*4+0x02000000,0xb53); +reg_write( DDR_REG_BASE +0x52929*4+0x02000000,0x1030); +reg_write( DDR_REG_BASE +0x5292a*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5292b*4+0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x5292c*4+0x02000000,0x80d); +reg_write( DDR_REG_BASE +0x5292d*4+0x02000000,0xd0); +reg_write( DDR_REG_BASE +0x5292e*4+0x02000000,0x84b); +reg_write( DDR_REG_BASE +0x5292f*4+0x02000000,0x210); +reg_write( DDR_REG_BASE +0x52930*4+0x02000000,0x855); +reg_write( DDR_REG_BASE +0x52931*4+0x02000000,0x1d1); +reg_write( DDR_REG_BASE +0x52932*4+0x02000000,0x788f); +reg_write( DDR_REG_BASE +0x52933*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x52934*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52935*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52936*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x52937*4+0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x52938*4+0x02000000,0xc301); +reg_write( DDR_REG_BASE +0x52939*4+0x02000000,0x677f); +reg_write( DDR_REG_BASE +0x5293a*4+0x02000000,0x7f14); +reg_write( DDR_REG_BASE +0x5293b*4+0x02000000,0x6861); +reg_write( DDR_REG_BASE +0x5293c*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x5293d*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5293e*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5293f*4+0x02000000,0x7c0); +reg_write( DDR_REG_BASE +0x52940*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52941*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52942*4+0x02000000,0x780); +reg_write( DDR_REG_BASE +0x52943*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x52944*4+0x02000000,0xb700); +reg_write( DDR_REG_BASE +0x52945*4+0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x52946*4+0x02000000,0xee5); +reg_write( DDR_REG_BASE +0x52947*4+0x02000000,0x9025); +reg_write( DDR_REG_BASE +0x52948*4+0x02000000,0xc788); +reg_write( DDR_REG_BASE +0x52949*4+0x02000000,0xe25); +reg_write( DDR_REG_BASE +0x5294a*4+0x02000000,0x11d1); +reg_write( DDR_REG_BASE +0x5294b*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5294c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5294d*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x5294e*4+0x02000000,0x7854); +reg_write( DDR_REG_BASE +0x5294f*4+0x02000000,0xa8af); +reg_write( DDR_REG_BASE +0x52950*4+0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x52951*4+0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x52952*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x52953*4+0x02000000,0x9700); +reg_write( DDR_REG_BASE +0x52954*4+0x02000000,0xb300); +reg_write( DDR_REG_BASE +0x52955*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52956*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52957*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x52958*4+0x02000000,0x7854); +reg_write( DDR_REG_BASE +0x52959*4+0x02000000,0xa8b0); +reg_write( DDR_REG_BASE +0x5295a*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x5295b*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5295c*4+0x02000000,0xe5b); +reg_write( DDR_REG_BASE +0x5295d*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5295e*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x5295f*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x52960*4+0x02000000,0x7a2f); +reg_write( DDR_REG_BASE +0x52961*4+0x02000000,0x845); +reg_write( DDR_REG_BASE +0x52962*4+0x02000000,0x80a5); +reg_write( DDR_REG_BASE +0x52963*4+0x02000000,0x716d); +reg_write( DDR_REG_BASE +0x52964*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52965*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x52966*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52967*4+0x02000000,0xf315); +reg_write( DDR_REG_BASE +0x52968*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52969*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5296a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5296b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5296c*4+0x02000000,0xb8c3); +reg_write( DDR_REG_BASE +0x5296d*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5296e*4+0x02000000,0xf02f); +reg_write( DDR_REG_BASE +0x5296f*4+0x02000000,0xc502); +reg_write( DDR_REG_BASE +0x52970*4+0x02000000,0xf028); +reg_write( DDR_REG_BASE +0x52971*4+0x02000000,0x275f); +reg_write( DDR_REG_BASE +0x52972*4+0x02000000,0x1480); +reg_write( DDR_REG_BASE +0x52973*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52974*4+0x02000000,0x47); +reg_write( DDR_REG_BASE +0x52975*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x52976*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x52977*4+0x02000000,0x661e); +reg_write( DDR_REG_BASE +0x52978*4+0x02000000,0x26f4); +reg_write( DDR_REG_BASE +0x52979*4+0x02000000,0x1340); +reg_write( DDR_REG_BASE +0x5297a*4+0x02000000,0x43a1); +reg_write( DDR_REG_BASE +0x5297b*4+0x02000000,0xe5e); +reg_write( DDR_REG_BASE +0x5297c*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x5297d*4+0x02000000,0x20bc); +reg_write( DDR_REG_BASE +0x5297e*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5297f*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52980*4+0x02000000,0x271a); +reg_write( DDR_REG_BASE +0x52981*4+0x02000000,0x1f81); +reg_write( DDR_REG_BASE +0x52982*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52983*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52984*4+0x02000000,0x26f4); +reg_write( DDR_REG_BASE +0x52985*4+0x02000000,0x1342); +reg_write( DDR_REG_BASE +0x52986*4+0x02000000,0x2054); +reg_write( DDR_REG_BASE +0x52987*4+0x02000000,0xd00); +reg_write( DDR_REG_BASE +0x52988*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x52989*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x5298a*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x5298b*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5298c*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x5298d*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x5298e*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5298f*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52990*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52991*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52992*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52993*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x52994*4+0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x52995*4+0x02000000,0x2049); +reg_write( DDR_REG_BASE +0x52996*4+0x02000000,0xfc0); +reg_write( DDR_REG_BASE +0x52997*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x52998*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52999*4+0x02000000,0xdb3); +reg_write( DDR_REG_BASE +0x5299a*4+0x02000000,0x9024); +reg_write( DDR_REG_BASE +0x5299b*4+0x02000000,0xc688); +reg_write( DDR_REG_BASE +0x5299c*4+0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x5299d*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5299e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5299f*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x529a0*4+0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x529a1*4+0x02000000,0x272f); +reg_write( DDR_REG_BASE +0x529a2*4+0x02000000,0x16c7); +reg_write( DDR_REG_BASE +0x529a3*4+0x02000000,0x89b); +reg_write( DDR_REG_BASE +0x529a4*4+0x02000000,0x83c5); +reg_write( DDR_REG_BASE +0x529a5*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x529a6*4+0x02000000,0x889); +reg_write( DDR_REG_BASE +0x529a7*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x529a8*4+0x02000000,0x9da); +reg_write( DDR_REG_BASE +0x529a9*4+0x02000000,0xfe4f); +reg_write( DDR_REG_BASE +0x529aa*4+0x02000000,0x4308); +reg_write( DDR_REG_BASE +0x529ab*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x529ac*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x529ad*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x529ae*4+0x02000000,0x8881); +reg_write( DDR_REG_BASE +0x529af*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x529b0*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x529b1*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x529b2*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x529b3*4+0x02000000,0xf034); +reg_write( DDR_REG_BASE +0x529b4*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x529b5*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x529b6*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x529b7*4+0x02000000,0x79b4); +reg_write( DDR_REG_BASE +0x529b8*4+0x02000000,0x896f); +reg_write( DDR_REG_BASE +0x529b9*4+0x02000000,0x8950); +reg_write( DDR_REG_BASE +0x529ba*4+0x02000000,0x4a76); +reg_write( DDR_REG_BASE +0x529bb*4+0x02000000,0x4b51); +reg_write( DDR_REG_BASE +0x529bc*4+0x02000000,0x7270); +reg_write( DDR_REG_BASE +0x529bd*4+0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x529be*4+0x02000000,0x38d); +reg_write( DDR_REG_BASE +0x529bf*4+0x02000000,0x7e2f); +reg_write( DDR_REG_BASE +0x529c0*4+0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x529c1*4+0x02000000,0x12ce); +reg_write( DDR_REG_BASE +0x529c2*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x529c3*4+0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x529c4*4+0x02000000,0x122d); +reg_write( DDR_REG_BASE +0x529c5*4+0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x529c6*4+0x02000000,0x12d); +reg_write( DDR_REG_BASE +0x529c7*4+0x02000000,0x2e44); +reg_write( DDR_REG_BASE +0x529c8*4+0x02000000,0x180e); +reg_write( DDR_REG_BASE +0x529c9*4+0x02000000,0xf019); +reg_write( DDR_REG_BASE +0x529ca*4+0x02000000,0xc203); +reg_write( DDR_REG_BASE +0x529cb*4+0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x529cc*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x529cd*4+0x02000000,0x2254); +reg_write( DDR_REG_BASE +0x529ce*4+0x02000000,0xd03); +reg_write( DDR_REG_BASE +0x529cf*4+0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x529d0*4+0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x529d1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x529d2*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x529d3*4+0x02000000,0x7a65); +reg_write( DDR_REG_BASE +0x529d4*4+0x02000000,0x7945); +reg_write( DDR_REG_BASE +0x529d5*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x529d6*4+0x02000000,0xb991); +reg_write( DDR_REG_BASE +0x529d7*4+0x02000000,0xb99c); +reg_write( DDR_REG_BASE +0x529d8*4+0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x529d9*4+0x02000000,0x9160); +reg_write( DDR_REG_BASE +0x529da*4+0x02000000,0x7ad0); +reg_write( DDR_REG_BASE +0x529db*4+0x02000000,0x627a); +reg_write( DDR_REG_BASE +0x529dc*4+0x02000000,0x2249); +reg_write( DDR_REG_BASE +0x529dd*4+0x02000000,0xfc2); +reg_write( DDR_REG_BASE +0x529de*4+0x02000000,0xb140); +reg_write( DDR_REG_BASE +0x529df*4+0x02000000,0x210a); +reg_write( DDR_REG_BASE +0x529e0*4+0x02000000,0x780); +reg_write( DDR_REG_BASE +0x529e1*4+0x02000000,0x9d5); +reg_write( DDR_REG_BASE +0x529e2*4+0x02000000,0x83e4); +reg_write( DDR_REG_BASE +0x529e3*4+0x02000000,0x2140); +reg_write( DDR_REG_BASE +0x529e4*4+0x02000000,0x5e); +reg_write( DDR_REG_BASE +0x529e5*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x529e6*4+0x02000000,0x7d0f); +reg_write( DDR_REG_BASE +0x529e7*4+0x02000000,0xc9d); +reg_write( DDR_REG_BASE +0x529e8*4+0x02000000,0x9365); +reg_write( DDR_REG_BASE +0x529e9*4+0x02000000,0xdf09); +reg_write( DDR_REG_BASE +0x529ea*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x529eb*4+0x02000000,0x3503); +reg_write( DDR_REG_BASE +0x529ec*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x529ed*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x529ee*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x529ef*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x529f0*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x529f1*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x529f2*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x529f3*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x529f4*4+0x02000000,0x3d0a); +reg_write( DDR_REG_BASE +0x529f5*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x529f6*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x529f7*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x529f8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x529f9*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x529fa*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x529fb*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x529fc*4+0x02000000,0x4a); +reg_write( DDR_REG_BASE +0x529fd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x529fe*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x529ff*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52a00*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52a01*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a02*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52a03*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52a04*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52a05*4+0x02000000,0x86); +reg_write( DDR_REG_BASE +0x52a06*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x52a07*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x52a08*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52a09*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52a0a*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52a0b*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52a0c*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52a0d*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52a0e*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52a0f*4+0x02000000,0xd36); +reg_write( DDR_REG_BASE +0x52a10*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52a11*4+0x02000000,0x2052); +reg_write( DDR_REG_BASE +0x52a12*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a13*4+0x02000000,0x8ae); +reg_write( DDR_REG_BASE +0x52a14*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52a15*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52a16*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x52a17*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52a18*4+0x02000000,0xff68); +reg_write( DDR_REG_BASE +0x52a19*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52a1a*4+0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x52a1b*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52a1c*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x52a1d*4+0x02000000,0x1a00); +reg_write( DDR_REG_BASE +0x52a1e*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x52a1f*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x52a20*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52a21*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x52a22*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52a23*4+0x02000000,0x7ca); +reg_write( DDR_REG_BASE +0x52a24*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x52a25*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x52a26*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x52a27*4+0x02000000,0xed06); +reg_write( DDR_REG_BASE +0x52a28*4+0x02000000,0xbd61); +reg_write( DDR_REG_BASE +0x52a29*4+0x02000000,0xd01); +reg_write( DDR_REG_BASE +0x52a2a*4+0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x52a2b*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52a2c*4+0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x52a2d*4+0x02000000,0x103); +reg_write( DDR_REG_BASE +0x52a2e*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52a2f*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x52a30*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52a31*4+0x02000000,0x1ea); +reg_write( DDR_REG_BASE +0x52a32*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52a33*4+0x02000000,0x12c3); +reg_write( DDR_REG_BASE +0x52a34*4+0x02000000,0x700); +reg_write( DDR_REG_BASE +0x52a35*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52a36*4+0x02000000,0xca0a); +reg_write( DDR_REG_BASE +0x52a37*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x52a38*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x52a39*4+0x02000000,0xf40c); +reg_write( DDR_REG_BASE +0x52a3a*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52a3b*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x52a3c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52a3d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a3e*4+0x02000000,0xb8e5); +reg_write( DDR_REG_BASE +0x52a3f*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52a40*4+0x02000000,0xf204); +reg_write( DDR_REG_BASE +0x52a41*4+0x02000000,0x8f00); +reg_write( DDR_REG_BASE +0x52a42*4+0x02000000,0x1a0a); +reg_write( DDR_REG_BASE +0x52a43*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x52a44*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x52a45*4+0x02000000,0x230f); +reg_write( DDR_REG_BASE +0x52a46*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x52a47*4+0x02000000,0xc149); +reg_write( DDR_REG_BASE +0x52a48*4+0x02000000,0x2379); +reg_write( DDR_REG_BASE +0x52a49*4+0x02000000,0x3001); +reg_write( DDR_REG_BASE +0x52a4a*4+0x02000000,0x7224); +reg_write( DDR_REG_BASE +0x52a4b*4+0x02000000,0xc14a); +reg_write( DDR_REG_BASE +0x52a4c*4+0x02000000,0x8f20); +reg_write( DDR_REG_BASE +0x52a4d*4+0x02000000,0x33b); +reg_write( DDR_REG_BASE +0x52a4e*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52a4f*4+0x02000000,0x2139); +reg_write( DDR_REG_BASE +0x52a50*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a51*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52a52*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52a53*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52a54*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52a55*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a56*4+0x02000000,0xc0ff); +reg_write( DDR_REG_BASE +0x52a57*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52a58*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52a59*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a5a*4+0x02000000,0x3f00); +reg_write( DDR_REG_BASE +0x52a5b*4+0x02000000,0x2080); +reg_write( DDR_REG_BASE +0x52a5c*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52a5d*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52a5e*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52a5f*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52a60*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52a61*4+0x02000000,0x1ea); +reg_write( DDR_REG_BASE +0x52a62*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52a63*4+0x02000000,0x7384); +reg_write( DDR_REG_BASE +0x52a64*4+0x02000000,0x900f); +reg_write( DDR_REG_BASE +0x52a65*4+0x02000000,0xe022); +reg_write( DDR_REG_BASE +0x52a66*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52a67*4+0x02000000,0x762c); +reg_write( DDR_REG_BASE +0x52a68*4+0x02000000,0xb8a5); +reg_write( DDR_REG_BASE +0x52a69*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52a6a*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52a6b*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52a6c*4+0x02000000,0xe0ee); +reg_write( DDR_REG_BASE +0x52a6d*4+0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x52a6e*4+0x02000000,0xf7e); +reg_write( DDR_REG_BASE +0x52a6f*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x52a70*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52a71*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x52a72*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52a73*4+0x02000000,0xed08); +reg_write( DDR_REG_BASE +0x52a74*4+0x02000000,0xb82); +reg_write( DDR_REG_BASE +0x52a75*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x52a76*4+0x02000000,0x2578); +reg_write( DDR_REG_BASE +0x52a77*4+0x02000000,0x1081); +reg_write( DDR_REG_BASE +0x52a78*4+0x02000000,0x2c9); +reg_write( DDR_REG_BASE +0x52a79*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a7a*4+0x02000000,0x976); +reg_write( DDR_REG_BASE +0x52a7b*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52a7c*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52a7d*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52a7e*4+0x02000000,0x709b); +reg_write( DDR_REG_BASE +0x52a7f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52a80*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52a81*4+0x02000000,0x8ee); +reg_write( DDR_REG_BASE +0x52a82*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52a83*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x52a84*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x52a85*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52a86*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52a87*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a88*4+0x02000000,0x258); +reg_write( DDR_REG_BASE +0x52a89*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52a8a*4+0x02000000,0xec6); +reg_write( DDR_REG_BASE +0x52a8b*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x52a8c*4+0x02000000,0xda5a); +reg_write( DDR_REG_BASE +0x52a8d*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52a8e*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52a8f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a90*4+0x02000000,0x1a4); +reg_write( DDR_REG_BASE +0x52a91*4+0x02000000,0xeba); +reg_write( DDR_REG_BASE +0x52a92*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x52a93*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x52a94*4+0x02000000,0xdda); +reg_write( DDR_REG_BASE +0x52a95*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x52a96*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x52a97*4+0x02000000,0xb04); +reg_write( DDR_REG_BASE +0x52a98*4+0x02000000,0xd72); +reg_write( DDR_REG_BASE +0x52a99*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x52a9a*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52a9b*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52a9c*4+0x02000000,0x7384); +reg_write( DDR_REG_BASE +0x52a9d*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52a9e*4+0x02000000,0xfec4); +reg_write( DDR_REG_BASE +0x52a9f*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52aa0*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x52aa1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52aa2*4+0x02000000,0xe008); +reg_write( DDR_REG_BASE +0x52aa3*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52aa4*4+0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x52aa5*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x52aa6*4+0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x52aa7*4+0x02000000,0x17c0); +reg_write( DDR_REG_BASE +0x52aa8*4+0x02000000,0x6e21); +reg_write( DDR_REG_BASE +0x52aa9*4+0x02000000,0x269a); +reg_write( DDR_REG_BASE +0x52aaa*4+0x02000000,0x1008); +reg_write( DDR_REG_BASE +0x52aab*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x52aac*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x52aad*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x52aae*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x52aaf*4+0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x52ab0*4+0x02000000,0x2605); +reg_write( DDR_REG_BASE +0x52ab1*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x52ab2*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52ab3*4+0x02000000,0xe0c4); +reg_write( DDR_REG_BASE +0x52ab4*4+0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x52ab5*4+0x02000000,0x4628); +reg_write( DDR_REG_BASE +0x52ab6*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52ab7*4+0x02000000,0xedf); +reg_write( DDR_REG_BASE +0x52ab8*4+0x02000000,0x9024); +reg_write( DDR_REG_BASE +0x52ab9*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52aba*4+0x02000000,0xd880); +reg_write( DDR_REG_BASE +0x52abb*4+0x02000000,0xb88e); +reg_write( DDR_REG_BASE +0x52abc*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52abd*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52abe*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52abf*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x52ac0*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x52ac1*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52ac2*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52ac3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52ac4*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52ac5*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52ac6*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52ac7*4+0x02000000,0xfe86); +reg_write( DDR_REG_BASE +0x52ac8*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52ac9*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52aca*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52acb*4+0x02000000,0x86); +reg_write( DDR_REG_BASE +0x52acc*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x52acd*4+0x02000000,0xb8a0); +reg_write( DDR_REG_BASE +0x52ace*4+0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x52acf*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52ad0*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x52ad1*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x52ad2*4+0x02000000,0x8f03); +reg_write( DDR_REG_BASE +0x52ad3*4+0x02000000,0xda3f); +reg_write( DDR_REG_BASE +0x52ad4*4+0x02000000,0xf643); +reg_write( DDR_REG_BASE +0x52ad5*4+0x02000000,0x2844); +reg_write( DDR_REG_BASE +0x52ad6*4+0x02000000,0x102); +reg_write( DDR_REG_BASE +0x52ad7*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x52ad8*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52ad9*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52ada*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52adb*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x52adc*4+0x02000000,0x8f24); +reg_write( DDR_REG_BASE +0x52add*4+0x02000000,0x43c1); +reg_write( DDR_REG_BASE +0x52ade*4+0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x52adf*4+0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x52ae0*4+0x02000000,0x7864); +reg_write( DDR_REG_BASE +0x52ae1*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x52ae2*4+0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x52ae3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52ae4*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52ae5*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x52ae6*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x52ae7*4+0x02000000,0x2054); +reg_write( DDR_REG_BASE +0x52ae8*4+0x02000000,0xd00); +reg_write( DDR_REG_BASE +0x52ae9*4+0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x52aea*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52aeb*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52aec*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52aed*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52aee*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52aef*4+0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x52af0*4+0x02000000,0x786f); +reg_write( DDR_REG_BASE +0x52af1*4+0x02000000,0x9e1); +reg_write( DDR_REG_BASE +0x52af2*4+0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x52af3*4+0x02000000,0xd8ef); +reg_write( DDR_REG_BASE +0x52af4*4+0x02000000,0x228a); +reg_write( DDR_REG_BASE +0x52af5*4+0x02000000,0x7c4); +reg_write( DDR_REG_BASE +0x52af6*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52af7*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52af8*4+0x02000000,0xe024); +reg_write( DDR_REG_BASE +0x52af9*4+0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x52afa*4+0x02000000,0x228a); +reg_write( DDR_REG_BASE +0x52afb*4+0x02000000,0x3c4); +reg_write( DDR_REG_BASE +0x52afc*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x52afd*4+0x02000000,0x180c); +reg_write( DDR_REG_BASE +0x52afe*4+0x02000000,0x45); +reg_write( DDR_REG_BASE +0x52aff*4+0x02000000,0x18fe); +reg_write( DDR_REG_BASE +0x52b00*4+0x02000000,0x8084); +reg_write( DDR_REG_BASE +0x52b01*4+0x02000000,0xf09f); +reg_write( DDR_REG_BASE +0x52b02*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x52b03*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x52b04*4+0x02000000,0x8c2); +reg_write( DDR_REG_BASE +0x52b05*4+0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x52b06*4+0x02000000,0x7a05); +reg_write( DDR_REG_BASE +0x52b07*4+0x02000000,0xd8ef); +reg_write( DDR_REG_BASE +0x52b08*4+0x02000000,0x78c4); +reg_write( DDR_REG_BASE +0x52b09*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x52b0a*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52b0b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52b0c*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52b0d*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x52b0e*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x52b0f*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52b10*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52b11*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52b12*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52b13*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52b14*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x52b15*4+0x02000000,0x6c4); +reg_write( DDR_REG_BASE +0x52b16*4+0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x52b17*4+0x02000000,0x9d9); +reg_write( DDR_REG_BASE +0x52b18*4+0x02000000,0x8005); +reg_write( DDR_REG_BASE +0x52b19*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52b1a*4+0x02000000,0xfea); +reg_write( DDR_REG_BASE +0x52b1b*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52b1c*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52b1d*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x52b1e*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52b1f*4+0x02000000,0xfe64); +reg_write( DDR_REG_BASE +0x52b20*4+0x02000000,0xb82); +reg_write( DDR_REG_BASE +0x52b21*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x52b22*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x52b23*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x52b24*4+0x02000000,0xb7a); +reg_write( DDR_REG_BASE +0x52b25*4+0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x52b26*4+0x02000000,0xa3a); +reg_write( DDR_REG_BASE +0x52b27*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x52b28*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52b29*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52b2a*4+0x02000000,0x94a); +reg_write( DDR_REG_BASE +0x52b2b*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52b2c*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x52b2d*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x52b2e*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x52b2f*4+0x02000000,0xc3a); +reg_write( DDR_REG_BASE +0x52b30*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52b31*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52b32*4+0x02000000,0xc08f); +reg_write( DDR_REG_BASE +0x52b33*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52b34*4+0x02000000,0xada); +reg_write( DDR_REG_BASE +0x52b35*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52b36*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52b37*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52b38*4+0x02000000,0xfae); +reg_write( DDR_REG_BASE +0x52b39*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52b3a*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52b3b*4+0x02000000,0xd87f); +reg_write( DDR_REG_BASE +0x52b3c*4+0x02000000,0xb4a); +reg_write( DDR_REG_BASE +0x52b3d*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x52b3e*4+0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x52b3f*4+0x02000000,0xb46); +reg_write( DDR_REG_BASE +0x52b40*4+0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x52b41*4+0x02000000,0xa06); +reg_write( DDR_REG_BASE +0x52b42*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x52b43*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52b44*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x52b45*4+0x02000000,0x916); +reg_write( DDR_REG_BASE +0x52b46*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52b47*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x52b48*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x52b49*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x52b4a*4+0x02000000,0xc02); +reg_write( DDR_REG_BASE +0x52b4b*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52b4c*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52b4d*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x52b4e*4+0x02000000,0x3f00); +reg_write( DDR_REG_BASE +0x52b4f*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52b50*4+0x02000000,0xaa2); +reg_write( DDR_REG_BASE +0x52b51*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52b52*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52b53*4+0x02000000,0x8f03); +reg_write( DDR_REG_BASE +0x52b54*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52b55*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x52b56*4+0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x52b57*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x52b58*4+0x02000000,0xf03f); +reg_write( DDR_REG_BASE +0x52b59*4+0x02000000,0xc08c); +reg_write( DDR_REG_BASE +0x52b5a*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52b5b*4+0x02000000,0xd26); +reg_write( DDR_REG_BASE +0x52b5c*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x52b5d*4+0x02000000,0xda09); +reg_write( DDR_REG_BASE +0x52b5e*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52b5f*4+0x02000000,0xf030); +reg_write( DDR_REG_BASE +0x52b60*4+0x02000000,0x787b); +reg_write( DDR_REG_BASE +0x52b61*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x52b62*4+0x02000000,0xf87); +reg_write( DDR_REG_BASE +0x52b63*4+0x02000000,0xc18f); +reg_write( DDR_REG_BASE +0x52b64*4+0x02000000,0x2135); +reg_write( DDR_REG_BASE +0x52b65*4+0x02000000,0xb); +reg_write( DDR_REG_BASE +0x52b66*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x52b67*4+0x02000000,0x3f01); +reg_write( DDR_REG_BASE +0x52b68*4+0x02000000,0x2135); +reg_write( DDR_REG_BASE +0x52b69*4+0x02000000,0xe); +reg_write( DDR_REG_BASE +0x52b6a*4+0x02000000,0x2602); +reg_write( DDR_REG_BASE +0x52b6b*4+0x02000000,0x12c0); +reg_write( DDR_REG_BASE +0x52b6c*4+0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x52b6d*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x52b6e*4+0x02000000,0xc08c); +reg_write( DDR_REG_BASE +0x52b6f*4+0x02000000,0x60b8); +reg_write( DDR_REG_BASE +0x52b70*4+0x02000000,0xa840); +reg_write( DDR_REG_BASE +0x52b71*4+0x02000000,0x7c4f); +reg_write( DDR_REG_BASE +0x52b72*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x52b73*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52b74*4+0x02000000,0x241); +reg_write( DDR_REG_BASE +0x52b75*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52b76*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52b77*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52b78*4+0x02000000,0x258); +reg_write( DDR_REG_BASE +0x52b79*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x52b7a*4+0x02000000,0x60b8); +reg_write( DDR_REG_BASE +0x52b7b*4+0x02000000,0x8820); +reg_write( DDR_REG_BASE +0x52b7c*4+0x02000000,0x921); +reg_write( DDR_REG_BASE +0x52b7d*4+0x02000000,0x305); +reg_write( DDR_REG_BASE +0x52b7e*4+0x02000000,0xa840); +reg_write( DDR_REG_BASE +0x52b7f*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x52b80*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52b81*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x52b82*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52b83*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52b84*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52b85*4+0x02000000,0x1a4); +reg_write( DDR_REG_BASE +0x52b86*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x52b87*4+0x02000000,0x2300); +reg_write( DDR_REG_BASE +0x52b88*4+0x02000000,0x1381); +reg_write( DDR_REG_BASE +0x52b89*4+0x02000000,0x78b4); +reg_write( DDR_REG_BASE +0x52b8a*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x52b8b*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x52b8c*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x52b8d*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x52b8e*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52b8f*4+0x02000000,0xda5); +reg_write( DDR_REG_BASE +0x52b90*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52b91*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52b92*4+0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x52b93*4+0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x52b94*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52b95*4+0x02000000,0x23c0); +reg_write( DDR_REG_BASE +0x52b96*4+0x02000000,0x61); +reg_write( DDR_REG_BASE +0x52b97*4+0x02000000,0x8f24); +reg_write( DDR_REG_BASE +0x52b98*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x52b99*4+0x02000000,0x787); +reg_write( DDR_REG_BASE +0x52b9a*4+0x02000000,0x97f); +reg_write( DDR_REG_BASE +0x52b9b*4+0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x52b9c*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x52b9d*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x52b9e*4+0x02000000,0x7467); +reg_write( DDR_REG_BASE +0x52b9f*4+0x02000000,0x234c); +reg_write( DDR_REG_BASE +0x52ba0*4+0x02000000,0xb780); +reg_write( DDR_REG_BASE +0x52ba1*4+0x02000000,0x6ec); +reg_write( DDR_REG_BASE +0x52ba2*4+0x02000000,0xffce); +reg_write( DDR_REG_BASE +0x52ba3*4+0x02000000,0xf036); +reg_write( DDR_REG_BASE +0x52ba4*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52ba5*4+0x02000000,0xf02e); +reg_write( DDR_REG_BASE +0x52ba6*4+0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x52ba7*4+0x02000000,0x3241); +reg_write( DDR_REG_BASE +0x52ba8*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52ba9*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52baa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52bab*4+0x02000000,0x258); +reg_write( DDR_REG_BASE +0x52bac*4+0x02000000,0x43a1); +reg_write( DDR_REG_BASE +0x52bad*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x52bae*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52baf*4+0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x52bb0*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x52bb1*4+0x02000000,0x9f2); +reg_write( DDR_REG_BASE +0x52bb2*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52bb3*4+0x02000000,0x60a8); +reg_write( DDR_REG_BASE +0x52bb4*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x52bb5*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x52bb6*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52bb7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52bb8*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52bb9*4+0x02000000,0x229a); +reg_write( DDR_REG_BASE +0x52bba*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x52bbb*4+0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x52bbc*4+0x02000000,0x3481); +reg_write( DDR_REG_BASE +0x52bbd*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x52bbe*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52bbf*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x52bc0*4+0x02000000,0x7a05); +reg_write( DDR_REG_BASE +0x52bc1*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52bc2*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52bc3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52bc4*4+0x02000000,0x1a4); +reg_write( DDR_REG_BASE +0x52bc5*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x52bc6*4+0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x52bc7*4+0x02000000,0x340); +reg_write( DDR_REG_BASE +0x52bc8*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x52bc9*4+0x02000000,0xcc); +reg_write( DDR_REG_BASE +0x52bca*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x52bcb*4+0x02000000,0x2342); +reg_write( DDR_REG_BASE +0x52bcc*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x52bcd*4+0x02000000,0x7a05); +reg_write( DDR_REG_BASE +0x52bce*4+0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x52bcf*4+0x02000000,0x340); +reg_write( DDR_REG_BASE +0x52bd0*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x52bd1*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x52bd2*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52bd3*4+0x02000000,0xda9); +reg_write( DDR_REG_BASE +0x52bd4*4+0x02000000,0x9024); +reg_write( DDR_REG_BASE +0x52bd5*4+0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x52bd6*4+0x02000000,0x8f24); +reg_write( DDR_REG_BASE +0x52bd7*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x52bd8*4+0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x52bd9*4+0x02000000,0x999); +reg_write( DDR_REG_BASE +0x52bda*4+0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x52bdb*4+0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x52bdc*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52bdd*4+0x02000000,0xb885); +reg_write( DDR_REG_BASE +0x52bde*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52bdf*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52be0*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52be1*4+0x02000000,0xe0ee); +reg_write( DDR_REG_BASE +0x52be2*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52be3*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52be4*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52be5*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52be6*4+0x02000000,0x1ea); +reg_write( DDR_REG_BASE +0x52be7*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x52be8*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52be9*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52bea*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x52beb*4+0x02000000,0x7d0f); +reg_write( DDR_REG_BASE +0x52bec*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x52bed*4+0x02000000,0x70b1); +reg_write( DDR_REG_BASE +0x52bee*4+0x02000000,0x4c6); +reg_write( DDR_REG_BASE +0x52bef*4+0x02000000,0xffed); +reg_write( DDR_REG_BASE +0x52bf0*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x52bf1*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x52bf2*4+0x02000000,0x3d0a); +reg_write( DDR_REG_BASE +0x52bf3*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52bf4*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52bf5*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52bf6*4+0x02000000,0xc0e6); +reg_write( DDR_REG_BASE +0x52bf7*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x52bf8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52bf9*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x52bfa*4+0x02000000,0x8ba0); +reg_write( DDR_REG_BASE +0x52bfb*4+0x02000000,0x8b81); +reg_write( DDR_REG_BASE +0x52bfc*4+0x02000000,0x251f); +reg_write( DDR_REG_BASE +0x52bfd*4+0x02000000,0x108f); +reg_write( DDR_REG_BASE +0x52bfe*4+0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x52bff*4+0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x52c00*4+0x02000000,0x1f9e); +reg_write( DDR_REG_BASE +0x52c01*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52c02*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52c03*4+0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x52c04*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52c05*4+0x02000000,0x2114); +reg_write( DDR_REG_BASE +0x52c06*4+0x02000000,0x38e); +reg_write( DDR_REG_BASE +0x52c07*4+0x02000000,0x2605); +reg_write( DDR_REG_BASE +0x52c08*4+0x02000000,0x301e); +reg_write( DDR_REG_BASE +0x52c09*4+0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x52c0a*4+0x02000000,0x783); +reg_write( DDR_REG_BASE +0x52c0b*4+0x02000000,0x7b7b); +reg_write( DDR_REG_BASE +0x52c0c*4+0x02000000,0xbb91); +reg_write( DDR_REG_BASE +0x52c0d*4+0x02000000,0xbb9c); +reg_write( DDR_REG_BASE +0x52c0e*4+0x02000000,0xbb9f); +reg_write( DDR_REG_BASE +0x52c0f*4+0x02000000,0x9360); +reg_write( DDR_REG_BASE +0x52c10*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x52c11*4+0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x52c12*4+0x02000000,0xb660); +reg_write( DDR_REG_BASE +0x52c13*4+0x02000000,0x232f); +reg_write( DDR_REG_BASE +0x52c14*4+0x02000000,0x2c7); +reg_write( DDR_REG_BASE +0x52c15*4+0x02000000,0xbd7); +reg_write( DDR_REG_BASE +0x52c16*4+0x02000000,0x80a4); +reg_write( DDR_REG_BASE +0x52c17*4+0x02000000,0x7ef0); +reg_write( DDR_REG_BASE +0x52c18*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x52c19*4+0x02000000,0xcf7); +reg_write( DDR_REG_BASE +0x52c1a*4+0x02000000,0x9365); +reg_write( DDR_REG_BASE +0x52c1b*4+0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x52c1c*4+0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x52c1d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52c1e*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52c1f*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52c20*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52c21*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x52c22*4+0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x52c23*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52c24*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52c25*4+0x02000000,0x4728); +reg_write( DDR_REG_BASE +0x52c26*4+0x02000000,0x7afd); +reg_write( DDR_REG_BASE +0x52c27*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x52c28*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52c29*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52c2a*4+0x02000000,0xb2); +reg_write( DDR_REG_BASE +0x52c2b*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52c2c*4+0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x52c2d*4+0x02000000,0x100c); +reg_write( DDR_REG_BASE +0x52c2e*4+0x02000000,0x2245); +reg_write( DDR_REG_BASE +0x52c2f*4+0x02000000,0x602); +reg_write( DDR_REG_BASE +0x52c30*4+0x02000000,0x7204); +reg_write( DDR_REG_BASE +0x52c31*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x52c32*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x52c33*4+0x02000000,0xb440); +reg_write( DDR_REG_BASE +0x52c34*4+0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x52c35*4+0x02000000,0x1002); +reg_write( DDR_REG_BASE +0x52c36*4+0x02000000,0x92c0); +reg_write( DDR_REG_BASE +0x52c37*4+0x02000000,0x7204); +reg_write( DDR_REG_BASE +0x52c38*4+0x02000000,0xbfc1); +reg_write( DDR_REG_BASE +0x52c39*4+0x02000000,0x78a5); +reg_write( DDR_REG_BASE +0x52c3a*4+0x02000000,0x6f43); +reg_write( DDR_REG_BASE +0x52c3b*4+0x02000000,0x90a0); +reg_write( DDR_REG_BASE +0x52c3c*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52c3d*4+0x02000000,0x2244); +reg_write( DDR_REG_BASE +0x52c3e*4+0x02000000,0x7c3); +reg_write( DDR_REG_BASE +0x52c3f*4+0x02000000,0xeb06); +reg_write( DDR_REG_BASE +0x52c40*4+0x02000000,0xbb61); +reg_write( DDR_REG_BASE +0x52c41*4+0x02000000,0xb01); +reg_write( DDR_REG_BASE +0x52c42*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x52c43*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52c44*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x52c45*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x52c46*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x52c47*4+0x02000000,0x83); +reg_write( DDR_REG_BASE +0x52c48*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52c49*4+0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x52c4a*4+0x02000000,0x17cc); +reg_write( DDR_REG_BASE +0x52c4b*4+0x02000000,0xec06); +reg_write( DDR_REG_BASE +0x52c4c*4+0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x52c4d*4+0x02000000,0xc01); +reg_write( DDR_REG_BASE +0x52c4e*4+0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x52c4f*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52c50*4+0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x52c51*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52c52*4+0x02000000,0xcc); +reg_write( DDR_REG_BASE +0x52c53*4+0x02000000,0x6f66); +reg_write( DDR_REG_BASE +0x52c54*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52c55*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x52c56*4+0x02000000,0x7db); +reg_write( DDR_REG_BASE +0x52c57*4+0x02000000,0xb11); +reg_write( DDR_REG_BASE +0x52c58*4+0x02000000,0x3010); +reg_write( DDR_REG_BASE +0x52c59*4+0x02000000,0x2342); +reg_write( DDR_REG_BASE +0x52c5a*4+0x02000000,0x305b); +reg_write( DDR_REG_BASE +0x52c5b*4+0x02000000,0xbff); +reg_write( DDR_REG_BASE +0x52c5c*4+0x02000000,0xb031); +reg_write( DDR_REG_BASE +0x52c5d*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52c5e*4+0x02000000,0xbbc4); +reg_write( DDR_REG_BASE +0x52c5f*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x52c60*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x52c61*4+0x02000000,0x2405); +reg_write( DDR_REG_BASE +0x52c62*4+0x02000000,0x101e); +reg_write( DDR_REG_BASE +0x52c63*4+0x02000000,0x2740); +reg_write( DDR_REG_BASE +0x52c64*4+0x02000000,0x124c); +reg_write( DDR_REG_BASE +0x52c65*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52c66*4+0x02000000,0x2444); +reg_write( DDR_REG_BASE +0x52c67*4+0x02000000,0x17ce); +reg_write( DDR_REG_BASE +0x52c68*4+0x02000000,0xee05); +reg_write( DDR_REG_BASE +0x52c69*4+0x02000000,0xbe61); +reg_write( DDR_REG_BASE +0x52c6a*4+0x02000000,0xeff); +reg_write( DDR_REG_BASE +0x52c6b*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x52c6c*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52c6d*4+0x02000000,0xbfc4); +reg_write( DDR_REG_BASE +0x52c6e*4+0x02000000,0x2244); +reg_write( DDR_REG_BASE +0x52c6f*4+0x02000000,0x7ce); +reg_write( DDR_REG_BASE +0x52c70*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x52c71*4+0x02000000,0xee06); +reg_write( DDR_REG_BASE +0x52c72*4+0x02000000,0xbe61); +reg_write( DDR_REG_BASE +0x52c73*4+0x02000000,0xe01); +reg_write( DDR_REG_BASE +0x52c74*4+0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x52c75*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52c76*4+0x02000000,0xbcc4); +reg_write( DDR_REG_BASE +0x52c77*4+0x02000000,0x2244); +reg_write( DDR_REG_BASE +0x52c78*4+0x02000000,0x8e); +reg_write( DDR_REG_BASE +0x52c79*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x52c7a*4+0x02000000,0xef05); +reg_write( DDR_REG_BASE +0x52c7b*4+0x02000000,0xbf61); +reg_write( DDR_REG_BASE +0x52c7c*4+0x02000000,0xfff); +reg_write( DDR_REG_BASE +0x52c7d*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x52c7e*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52c7f*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x52c80*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x52c81*4+0x02000000,0xbac0); +reg_write( DDR_REG_BASE +0x52c82*4+0x02000000,0x7e45); +reg_write( DDR_REG_BASE +0x52c83*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x52c84*4+0x02000000,0xeb05); +reg_write( DDR_REG_BASE +0x52c85*4+0x02000000,0xbb61); +reg_write( DDR_REG_BASE +0x52c86*4+0x02000000,0xbff); +reg_write( DDR_REG_BASE +0x52c87*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x52c88*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52c89*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52c8a*4+0x02000000,0x780); +reg_write( DDR_REG_BASE +0x52c8b*4+0x02000000,0x2244); +reg_write( DDR_REG_BASE +0x52c8c*4+0x02000000,0x103); +reg_write( DDR_REG_BASE +0x52c8d*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x52c8e*4+0x02000000,0xec05); +reg_write( DDR_REG_BASE +0x52c8f*4+0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x52c90*4+0x02000000,0xcff); +reg_write( DDR_REG_BASE +0x52c91*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x52c92*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52c93*4+0x02000000,0x7bc5); +reg_write( DDR_REG_BASE +0x52c94*4+0x02000000,0x2244); +reg_write( DDR_REG_BASE +0x52c95*4+0x02000000,0x202); +reg_write( DDR_REG_BASE +0x52c96*4+0x02000000,0x7a65); +reg_write( DDR_REG_BASE +0x52c97*4+0x02000000,0x225f); +reg_write( DDR_REG_BASE +0x52c98*4+0x02000000,0x402); +reg_write( DDR_REG_BASE +0x52c99*4+0x02000000,0xdd2); +reg_write( DDR_REG_BASE +0x52c9a*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52c9b*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x52c9c*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52c9d*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52c9e*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52c9f*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52ca0*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52ca1*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52ca2*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52ca3*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x52ca4*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52ca5*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x52ca6*4+0x02000000,0x8d80); +reg_write( DDR_REG_BASE +0x52ca7*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x52ca8*4+0x02000000,0x4718); +reg_write( DDR_REG_BASE +0x52ca9*4+0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x52caa*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52cab*4+0x02000000,0xea0d); +reg_write( DDR_REG_BASE +0x52cac*4+0x02000000,0x245f); +reg_write( DDR_REG_BASE +0x52cad*4+0x02000000,0x1243); +reg_write( DDR_REG_BASE +0x52cae*4+0x02000000,0xa1b); +reg_write( DDR_REG_BASE +0x52caf*4+0x02000000,0xb1); +reg_write( DDR_REG_BASE +0x52cb0*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x52cb1*4+0x02000000,0xe308); +reg_write( DDR_REG_BASE +0x52cb2*4+0x02000000,0xd809); +reg_write( DDR_REG_BASE +0x52cb3*4+0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x52cb4*4+0x02000000,0x234a); +reg_write( DDR_REG_BASE +0x52cb5*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x52cb6*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x52cb7*4+0x02000000,0x7b9b); +reg_write( DDR_REG_BASE +0x52cb8*4+0x02000000,0x74ed); +reg_write( DDR_REG_BASE +0x52cb9*4+0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x52cba*4+0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x52cbb*4+0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x52cbc*4+0x02000000,0x1501); +reg_write( DDR_REG_BASE +0x52cbd*4+0x02000000,0x109e); +reg_write( DDR_REG_BASE +0x52cbe*4+0x02000000,0xf023); +reg_write( DDR_REG_BASE +0x52cbf*4+0x02000000,0x45c9); +reg_write( DDR_REG_BASE +0x52cc0*4+0x02000000,0x259a); +reg_write( DDR_REG_BASE +0x52cc1*4+0x02000000,0x1008); +reg_write( DDR_REG_BASE +0x52cc2*4+0x02000000,0x241a); +reg_write( DDR_REG_BASE +0x52cc3*4+0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x52cc4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52cc5*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52cc6*4+0x02000000,0x7aa5); +reg_write( DDR_REG_BASE +0x52cc7*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x52cc8*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x52cc9*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52cca*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x52ccb*4+0x02000000,0xb1f); +reg_write( DDR_REG_BASE +0x52ccc*4+0x02000000,0x3030); +reg_write( DDR_REG_BASE +0x52ccd*4+0x02000000,0x9a40); +reg_write( DDR_REG_BASE +0x52cce*4+0x02000000,0x258a); +reg_write( DDR_REG_BASE +0x52ccf*4+0x02000000,0x1fcf); +reg_write( DDR_REG_BASE +0x52cd0*4+0x02000000,0x7d44); +reg_write( DDR_REG_BASE +0x52cd1*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52cd2*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52cd3*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52cd4*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52cd5*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52cd6*4+0x02000000,0x2284); +reg_write( DDR_REG_BASE +0x52cd7*4+0x02000000,0x81f); +reg_write( DDR_REG_BASE +0x52cd8*4+0x02000000,0x62ba); +reg_write( DDR_REG_BASE +0x52cd9*4+0x02000000,0x2714); +reg_write( DDR_REG_BASE +0x52cda*4+0x02000000,0x30cd); +reg_write( DDR_REG_BASE +0x52cdb*4+0x02000000,0xb540); +reg_write( DDR_REG_BASE +0x52cdc*4+0x02000000,0x66fe); +reg_write( DDR_REG_BASE +0x52cdd*4+0x02000000,0x631b); +reg_write( DDR_REG_BASE +0x52cde*4+0x02000000,0x9c3); +reg_write( DDR_REG_BASE +0x52cdf*4+0x02000000,0x8385); +reg_write( DDR_REG_BASE +0x52ce0*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x52ce1*4+0x02000000,0xefd); +reg_write( DDR_REG_BASE +0x52ce2*4+0x02000000,0xb325); +reg_write( DDR_REG_BASE +0x52ce3*4+0x02000000,0x4669); +reg_write( DDR_REG_BASE +0x52ce4*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52ce5*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52ce6*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52ce7*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52ce8*4+0x02000000,0x8819); +reg_write( DDR_REG_BASE +0x52ce9*4+0x02000000,0xb863); +reg_write( DDR_REG_BASE +0x52cea*4+0x02000000,0x7314); +reg_write( DDR_REG_BASE +0x52ceb*4+0x02000000,0x20e0); +reg_write( DDR_REG_BASE +0x52cec*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x52ced*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52cee*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x52cef*4+0x02000000,0x1e4c); +reg_write( DDR_REG_BASE +0x52cf0*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x52cf1*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x52cf2*4+0x02000000,0xb041); +reg_write( DDR_REG_BASE +0x52cf3*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52cf4*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x52cf5*4+0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x52cf6*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x52cf7*4+0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x52cf8*4+0x02000000,0x70ef); +reg_write( DDR_REG_BASE +0x52cf9*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x52cfa*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x52cfb*4+0x02000000,0xc82); +reg_write( DDR_REG_BASE +0x52cfc*4+0x02000000,0x605c); +reg_write( DDR_REG_BASE +0x52cfd*4+0x02000000,0x275a); +reg_write( DDR_REG_BASE +0x52cfe*4+0x02000000,0x3642); +reg_write( DDR_REG_BASE +0x52cff*4+0x02000000,0x71e7); +reg_write( DDR_REG_BASE +0x52d00*4+0x02000000,0x629a); +reg_write( DDR_REG_BASE +0x52d01*4+0x02000000,0x623c); +reg_write( DDR_REG_BASE +0x52d02*4+0x02000000,0x2600); +reg_write( DDR_REG_BASE +0x52d03*4+0x02000000,0x3682); +reg_write( DDR_REG_BASE +0x52d04*4+0x02000000,0x123c); +reg_write( DDR_REG_BASE +0x52d05*4+0x02000000,0x82); +reg_write( DDR_REG_BASE +0x52d06*4+0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x52d07*4+0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x52d08*4+0x02000000,0xac40); +reg_write( DDR_REG_BASE +0x52d09*4+0x02000000,0xfe5); +reg_write( DDR_REG_BASE +0x52d0a*4+0x02000000,0xb094); +reg_write( DDR_REG_BASE +0x52d0b*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x52d0c*4+0x02000000,0xbd9); +reg_write( DDR_REG_BASE +0x52d0d*4+0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x52d0e*4+0x02000000,0x2314); +reg_write( DDR_REG_BASE +0x52d0f*4+0x02000000,0x10de); +reg_write( DDR_REG_BASE +0x52d10*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x52d11*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52d12*4+0x02000000,0x791b); +reg_write( DDR_REG_BASE +0x52d13*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52d14*4+0x02000000,0x2184); +reg_write( DDR_REG_BASE +0x52d15*4+0x02000000,0xa82); +reg_write( DDR_REG_BASE +0x52d16*4+0x02000000,0x2046); +reg_write( DDR_REG_BASE +0x52d17*4+0x02000000,0xa80); +reg_write( DDR_REG_BASE +0x52d18*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x52d19*4+0x02000000,0x215a); +reg_write( DDR_REG_BASE +0x52d1a*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x52d1b*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x52d1c*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x52d1d*4+0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x52d1e*4+0x02000000,0xcc1); +reg_write( DDR_REG_BASE +0x52d1f*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x52d20*4+0x02000000,0x303); +reg_write( DDR_REG_BASE +0x52d21*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x52d22*4+0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x52d23*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x52d24*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x52d25*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x52d26*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x52d27*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x52d28*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52d29*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x52d2a*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52d2b*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52d2c*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x52d2d*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x52d2e*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52d2f*4+0x02000000,0xe000); +reg_write( DDR_REG_BASE +0x52d30*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x52d31*4+0x02000000,0xe26); +reg_write( DDR_REG_BASE +0x52d32*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x52d33*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x52d34*4+0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x52d35*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x52d36*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x52d37*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x52d38*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52d39*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52d3a*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52d3b*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x52d3c*4+0x02000000,0x3b02); +reg_write( DDR_REG_BASE +0x52d3d*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52d3e*4+0x02000000,0x709b); +reg_write( DDR_REG_BASE +0x52d3f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52d40*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52d41*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x52d42*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52d43*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52d44*4+0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x52d45*4+0x02000000,0xf8a5); +reg_write( DDR_REG_BASE +0x52d46*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52d47*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52d48*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52d49*4+0x02000000,0xfbff); +reg_write( DDR_REG_BASE +0x52d4a*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x52d4b*4+0x02000000,0x9f7); +reg_write( DDR_REG_BASE +0x52d4c*4+0x02000000,0x8294); +reg_write( DDR_REG_BASE +0x52d4d*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52d4e*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x52d4f*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52d50*4+0x02000000,0xaa); +reg_write( DDR_REG_BASE +0x52d51*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52d52*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52d53*4+0x02000000,0x51f); +reg_write( DDR_REG_BASE +0x52d54*4+0x02000000,0xda78); +reg_write( DDR_REG_BASE +0x52d55*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52d56*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52d57*4+0x02000000,0x7085); +reg_write( DDR_REG_BASE +0x52d58*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52d59*4+0x02000000,0xe0aa); +reg_write( DDR_REG_BASE +0x52d5a*4+0x02000000,0xdce); +reg_write( DDR_REG_BASE +0x52d5b*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x52d5c*4+0x02000000,0xc08d); +reg_write( DDR_REG_BASE +0x52d5d*4+0x02000000,0xc08d); +reg_write( DDR_REG_BASE +0x52d5e*4+0x02000000,0xace); +reg_write( DDR_REG_BASE +0x52d5f*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x52d60*4+0x02000000,0xd978); +reg_write( DDR_REG_BASE +0x52d61*4+0x02000000,0xe76); +reg_write( DDR_REG_BASE +0x52d62*4+0x02000000,0xfd8f); +reg_write( DDR_REG_BASE +0x52d63*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52d64*4+0x02000000,0xb56); +reg_write( DDR_REG_BASE +0x52d65*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52d66*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52d67*4+0x02000000,0xef6); +reg_write( DDR_REG_BASE +0x52d68*4+0x02000000,0xff0f); +reg_write( DDR_REG_BASE +0x52d69*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52d6a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52d6b*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x52d6c*4+0x02000000,0xb12); +reg_write( DDR_REG_BASE +0x52d6d*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52d6e*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52d6f*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52d70*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52d71*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x52d72*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52d73*4+0x02000000,0xaa2); +reg_write( DDR_REG_BASE +0x52d74*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52d75*4+0x02000000,0xdaf7); +reg_write( DDR_REG_BASE +0x52d76*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x52d77*4+0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x52d78*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x52d79*4+0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x52d7a*4+0x02000000,0xe805); +reg_write( DDR_REG_BASE +0x52d7b*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x52d7c*4+0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x52d7d*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x52d7e*4+0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x52d7f*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x52d80*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52d81*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x52d82*4+0x02000000,0x225a); +reg_write( DDR_REG_BASE +0x52d83*4+0x02000000,0x102); +reg_write( DDR_REG_BASE +0x52d84*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x52d85*4+0x02000000,0x8d20); +reg_write( DDR_REG_BASE +0x52d86*4+0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x52d87*4+0x02000000,0xf7f); +reg_write( DDR_REG_BASE +0x52d88*4+0x02000000,0x220f); +reg_write( DDR_REG_BASE +0x52d89*4+0x02000000,0xe); +reg_write( DDR_REG_BASE +0x52d8a*4+0x02000000,0x265a); +reg_write( DDR_REG_BASE +0x52d8b*4+0x02000000,0x1100); +reg_write( DDR_REG_BASE +0x52d8c*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52d8d*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x52d8e*4+0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x52d8f*4+0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x52d90*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52d91*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52d92*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x52d93*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52d94*4+0x02000000,0x640); +reg_write( DDR_REG_BASE +0x52d95*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52d96*4+0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x52d97*4+0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x52d98*4+0x02000000,0xc103); +reg_write( DDR_REG_BASE +0x52d99*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x52d9a*4+0x02000000,0x2100); +reg_write( DDR_REG_BASE +0x52d9b*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52d9c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52d9d*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x52d9e*4+0x02000000,0xd02); +reg_write( DDR_REG_BASE +0x52d9f*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x52da0*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52da1*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52da2*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52da3*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x52da4*4+0x02000000,0xea2); +reg_write( DDR_REG_BASE +0x52da5*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x52da6*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52da7*4+0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x52da8*4+0x02000000,0x7ecf); +reg_write( DDR_REG_BASE +0x52da9*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52daa*4+0x02000000,0xc81); +reg_write( DDR_REG_BASE +0x52dab*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52dac*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x52dad*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52dae*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52daf*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52db0*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x52db1*4+0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x52db2*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x52db3*4+0x02000000,0x44); +reg_write( DDR_REG_BASE +0x52db4*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x52db5*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52db6*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52db7*4+0x02000000,0xe024); +reg_write( DDR_REG_BASE +0x52db8*4+0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x52db9*4+0x02000000,0xb0e6); +reg_write( DDR_REG_BASE +0x52dba*4+0x02000000,0x18fe); +reg_write( DDR_REG_BASE +0x52dbb*4+0x02000000,0x8044); +reg_write( DDR_REG_BASE +0x52dbc*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52dbd*4+0x02000000,0xba2); +reg_write( DDR_REG_BASE +0x52dbe*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x52dbf*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52dc0*4+0x02000000,0xd830); +reg_write( DDR_REG_BASE +0x52dc1*4+0x02000000,0xf16); +reg_write( DDR_REG_BASE +0x52dc2*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52dc3*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52dc4*4+0x02000000,0xd9e); +reg_write( DDR_REG_BASE +0x52dc5*4+0x02000000,0xfe0f); +reg_write( DDR_REG_BASE +0x52dc6*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x52dc7*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52dc8*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52dc9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52dca*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x52dcb*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52dcc*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x52dcd*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x52dce*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x52dcf*4+0x02000000,0xfc3); +reg_write( DDR_REG_BASE +0x52dd0*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52dd1*4+0x02000000,0x8fb); +reg_write( DDR_REG_BASE +0x52dd2*4+0x02000000,0x8534); +reg_write( DDR_REG_BASE +0x52dd3*4+0x02000000,0xc188); +reg_write( DDR_REG_BASE +0x52dd4*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52dd5*4+0x02000000,0xeee); +reg_write( DDR_REG_BASE +0x52dd6*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52dd7*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52dd8*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52dd9*4+0x02000000,0xa6e); +reg_write( DDR_REG_BASE +0x52dda*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52ddb*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52ddc*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52ddd*4+0x02000000,0xb62); +reg_write( DDR_REG_BASE +0x52dde*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x52ddf*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52de0*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x52de1*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x52de2*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x52de3*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52de4*4+0x02000000,0xe174); +reg_write( DDR_REG_BASE +0x52de5*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x52de6*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x52de7*4+0x02000000,0xb601); +reg_write( DDR_REG_BASE +0x52de8*4+0x02000000,0x1e59); +reg_write( DDR_REG_BASE +0x52de9*4+0x02000000,0x901d); +reg_write( DDR_REG_BASE +0x52dea*4+0x02000000,0xf7d); +reg_write( DDR_REG_BASE +0x52deb*4+0x02000000,0x1a35); +reg_write( DDR_REG_BASE +0x52dec*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52ded*4+0x02000000,0xebe); +reg_write( DDR_REG_BASE +0x52dee*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52def*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52df0*4+0x02000000,0x1503); +reg_write( DDR_REG_BASE +0x52df1*4+0x02000000,0x108b); +reg_write( DDR_REG_BASE +0x52df2*4+0x02000000,0x8d82); +reg_write( DDR_REG_BASE +0x52df3*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x52df4*4+0x02000000,0xf02a); +reg_write( DDR_REG_BASE +0x52df5*4+0x02000000,0x241a); +reg_write( DDR_REG_BASE +0x52df6*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x52df7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52df8*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52df9*4+0x02000000,0x206c); +reg_write( DDR_REG_BASE +0x52dfa*4+0x02000000,0x302); +reg_write( DDR_REG_BASE +0x52dfb*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x52dfc*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52dfd*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52dfe*4+0x02000000,0x166); +reg_write( DDR_REG_BASE +0x52dff*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x52e00*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x52e01*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x52e02*4+0x02000000,0xc088); +reg_write( DDR_REG_BASE +0x52e03*4+0x02000000,0x6098); +reg_write( DDR_REG_BASE +0x52e04*4+0x02000000,0x8820); +reg_write( DDR_REG_BASE +0x52e05*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x52e06*4+0x02000000,0x7965); +reg_write( DDR_REG_BASE +0x52e07*4+0x02000000,0xa820); +reg_write( DDR_REG_BASE +0x52e08*4+0x02000000,0x241a); +reg_write( DDR_REG_BASE +0x52e09*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x52e0a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52e0b*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x52e0c*4+0x02000000,0x2153); +reg_write( DDR_REG_BASE +0x52e0d*4+0x02000000,0x80be); +reg_write( DDR_REG_BASE +0x52e0e*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52e0f*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52e10*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52e11*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x52e12*4+0x02000000,0x7a05); +reg_write( DDR_REG_BASE +0x52e13*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x52e14*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x52e15*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52e16*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x52e17*4+0x02000000,0x9200); +reg_write( DDR_REG_BASE +0x52e18*4+0x02000000,0xf205); +reg_write( DDR_REG_BASE +0x52e19*4+0x02000000,0x2080); +reg_write( DDR_REG_BASE +0x52e1a*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52e1b*4+0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x52e1c*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x52e1d*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x52e1e*4+0x02000000,0xbaf); +reg_write( DDR_REG_BASE +0x52e1f*4+0x02000000,0x9325); +reg_write( DDR_REG_BASE +0x52e20*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52e21*4+0x02000000,0x9de); +reg_write( DDR_REG_BASE +0x52e22*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52e23*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52e24*4+0x02000000,0xb8d); +reg_write( DDR_REG_BASE +0x52e25*4+0x02000000,0xb031); +reg_write( DDR_REG_BASE +0x52e26*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x52e27*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x52e28*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52e29*4+0x02000000,0x6e); +reg_write( DDR_REG_BASE +0x52e2a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52e2b*4+0x02000000,0xcfe); +reg_write( DDR_REG_BASE +0x52e2c*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x52e2d*4+0x02000000,0x2378); +reg_write( DDR_REG_BASE +0x52e2e*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x52e2f*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52e30*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x52e31*4+0x02000000,0xcc6); +reg_write( DDR_REG_BASE +0x52e32*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52e33*4+0x02000000,0x1e02); +reg_write( DDR_REG_BASE +0x52e34*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x52e35*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52e36*4+0x02000000,0xa16); +reg_write( DDR_REG_BASE +0x52e37*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52e38*4+0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x52e39*4+0x02000000,0xd840); +reg_write( DDR_REG_BASE +0x52e3a*4+0x02000000,0xe22); +reg_write( DDR_REG_BASE +0x52e3b*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52e3c*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52e3d*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52e3e*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52e3f*4+0x02000000,0xcc6); +reg_write( DDR_REG_BASE +0x52e40*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x52e41*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52e42*4+0x02000000,0x8d43); +reg_write( DDR_REG_BASE +0x52e43*4+0x02000000,0x8d62); +reg_write( DDR_REG_BASE +0x52e44*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x52e45*4+0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x52e46*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x52e47*4+0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x52e48*4+0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x52e49*4+0x02000000,0xb8e3); +reg_write( DDR_REG_BASE +0x52e4a*4+0x02000000,0xd840); +reg_write( DDR_REG_BASE +0x52e4b*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x52e4c*4+0x02000000,0x822); +reg_write( DDR_REG_BASE +0x52e4d*4+0x02000000,0x7902); +reg_write( DDR_REG_BASE +0x52e4e*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52e4f*4+0x02000000,0x7874); +reg_write( DDR_REG_BASE +0x52e50*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x52e51*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x52e52*4+0x02000000,0xae7); +reg_write( DDR_REG_BASE +0x52e53*4+0x02000000,0x80c5); +reg_write( DDR_REG_BASE +0x52e54*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x52e55*4+0x02000000,0x9c2); +reg_write( DDR_REG_BASE +0x52e56*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52e57*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52e58*4+0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x52e59*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x52e5a*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x52e5b*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52e5c*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52e5d*4+0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x52e5e*4+0x02000000,0x92a); +reg_write( DDR_REG_BASE +0x52e5f*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x52e60*4+0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x52e61*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52e62*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52e63*4+0x02000000,0x7044); +reg_write( DDR_REG_BASE +0x52e64*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52e65*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x52e66*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52e67*4+0x02000000,0x7044); +reg_write( DDR_REG_BASE +0x52e68*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52e69*4+0x02000000,0xe076); +reg_write( DDR_REG_BASE +0x52e6a*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52e6b*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52e6c*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52e6d*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52e6e*4+0x02000000,0xe0aa); +reg_write( DDR_REG_BASE +0x52e6f*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x52e70*4+0x02000000,0xf80f); +reg_write( DDR_REG_BASE +0x52e71*4+0x02000000,0xb88a); +reg_write( DDR_REG_BASE +0x52e72*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x52e73*4+0x02000000,0x9fd); +reg_write( DDR_REG_BASE +0x52e74*4+0x02000000,0x8294); +reg_write( DDR_REG_BASE +0x52e75*4+0x02000000,0xd72); +reg_write( DDR_REG_BASE +0x52e76*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x52e77*4+0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x52e78*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52e79*4+0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x52e7a*4+0x02000000,0xf7f); +reg_write( DDR_REG_BASE +0x52e7b*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52e7c*4+0x02000000,0xc81); +reg_write( DDR_REG_BASE +0x52e7d*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52e7e*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x52e7f*4+0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x52e80*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x52e81*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52e82*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52e83*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52e84*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x52e85*4+0x02000000,0xb36); +reg_write( DDR_REG_BASE +0x52e86*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x52e87*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52e88*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x52e89*4+0x02000000,0x3b02); +reg_write( DDR_REG_BASE +0x52e8a*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52e8b*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52e8c*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52e8d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52e8e*4+0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x52e8f*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52e90*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52e91*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52e92*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x52e93*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52e94*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x52e95*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52e96*4+0x02000000,0x94); +reg_write( DDR_REG_BASE +0x52e97*4+0x02000000,0x9200); +reg_write( DDR_REG_BASE +0x52e98*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52e99*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52e9a*4+0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x52e9b*4+0x02000000,0x216c); +reg_write( DDR_REG_BASE +0x52e9c*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x52e9d*4+0x02000000,0xa821); +reg_write( DDR_REG_BASE +0x52e9e*4+0x02000000,0x8822); +reg_write( DDR_REG_BASE +0x52e9f*4+0x02000000,0xb9c6); +reg_write( DDR_REG_BASE +0x52ea0*4+0x02000000,0xa822); +reg_write( DDR_REG_BASE +0x52ea1*4+0x02000000,0x882d); +reg_write( DDR_REG_BASE +0x52ea2*4+0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x52ea3*4+0x02000000,0xc02); +reg_write( DDR_REG_BASE +0x52ea4*4+0x02000000,0x2285); +reg_write( DDR_REG_BASE +0x52ea5*4+0x02000000,0x23f); +reg_write( DDR_REG_BASE +0x52ea6*4+0x02000000,0x913); +reg_write( DDR_REG_BASE +0x52ea7*4+0x02000000,0x17f); +reg_write( DDR_REG_BASE +0x52ea8*4+0x02000000,0xa84d); +reg_write( DDR_REG_BASE +0x52ea9*4+0x02000000,0x794f); +reg_write( DDR_REG_BASE +0x52eaa*4+0x02000000,0xb985); +reg_write( DDR_REG_BASE +0x52eab*4+0x02000000,0xa82d); +reg_write( DDR_REG_BASE +0x52eac*4+0x02000000,0x8823); +reg_write( DDR_REG_BASE +0x52ead*4+0x02000000,0xb987); +reg_write( DDR_REG_BASE +0x52eae*4+0x02000000,0xa823); +reg_write( DDR_REG_BASE +0x52eaf*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52eb0*4+0x02000000,0xa838); +reg_write( DDR_REG_BASE +0x52eb1*4+0x02000000,0xa831); +reg_write( DDR_REG_BASE +0x52eb2*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x52eb3*4+0x02000000,0xa830); +reg_write( DDR_REG_BASE +0x52eb4*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x52eb5*4+0x02000000,0xb9a); +reg_write( DDR_REG_BASE +0x52eb6*4+0x02000000,0xfdcf); +reg_write( DDR_REG_BASE +0x52eb7*4+0x02000000,0x256f); +reg_write( DDR_REG_BASE +0x52eb8*4+0x02000000,0x1343); +reg_write( DDR_REG_BASE +0x52eb9*4+0x02000000,0x9560); +reg_write( DDR_REG_BASE +0x52eba*4+0x02000000,0xda20); +reg_write( DDR_REG_BASE +0x52ebb*4+0x02000000,0xd940); +reg_write( DDR_REG_BASE +0x52ebc*4+0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x52ebd*4+0x02000000,0x85ca); +reg_write( DDR_REG_BASE +0x52ebe*4+0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x52ebf*4+0x02000000,0xc2d); +reg_write( DDR_REG_BASE +0x52ec0*4+0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x52ec1*4+0x02000000,0x89d0); +reg_write( DDR_REG_BASE +0x52ec2*4+0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x52ec3*4+0x02000000,0x4d); +reg_write( DDR_REG_BASE +0x52ec4*4+0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x52ec5*4+0x02000000,0x8fd8); +reg_write( DDR_REG_BASE +0x52ec6*4+0x02000000,0xd950); +reg_write( DDR_REG_BASE +0x52ec7*4+0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x52ec8*4+0x02000000,0x4d); +reg_write( DDR_REG_BASE +0x52ec9*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x52eca*4+0x02000000,0x5ca); +reg_write( DDR_REG_BASE +0x52ecb*4+0x02000000,0x213c); +reg_write( DDR_REG_BASE +0x52ecc*4+0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x52ecd*4+0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x52ece*4+0x02000000,0x89d0); +reg_write( DDR_REG_BASE +0x52ecf*4+0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x52ed0*4+0x02000000,0xad); +reg_write( DDR_REG_BASE +0x52ed1*4+0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x52ed2*4+0x02000000,0x8fd8); +reg_write( DDR_REG_BASE +0x52ed3*4+0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x52ed4*4+0x02000000,0xed); +reg_write( DDR_REG_BASE +0x52ed5*4+0x02000000,0x73d3); +reg_write( DDR_REG_BASE +0x52ed6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52ed7*4+0x02000000,0x95f); +reg_write( DDR_REG_BASE +0x52ed8*4+0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x52ed9*4+0x02000000,0x12d); +reg_write( DDR_REG_BASE +0x52eda*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x52edb*4+0x02000000,0x8c); +reg_write( DDR_REG_BASE +0x52edc*4+0x02000000,0x15fe); +reg_write( DDR_REG_BASE +0x52edd*4+0x02000000,0x9081); +reg_write( DDR_REG_BASE +0x52ede*4+0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x52edf*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x52ee0*4+0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x52ee1*4+0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x52ee2*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52ee3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52ee4*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52ee5*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52ee6*4+0x02000000,0xf8); +reg_write( DDR_REG_BASE +0x52ee7*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52ee8*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52ee9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52eea*4+0x02000000,0x1ff0); +reg_write( DDR_REG_BASE +0x52eeb*4+0x02000000,0xb881); +reg_write( DDR_REG_BASE +0x52eec*4+0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x52eed*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x52eee*4+0x02000000,0x7224); +reg_write( DDR_REG_BASE +0x52eef*4+0x02000000,0x7965); +reg_write( DDR_REG_BASE +0x52ef0*4+0x02000000,0xb280); +reg_write( DDR_REG_BASE +0x52ef1*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x52ef2*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x52ef3*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52ef4*4+0x02000000,0xc0e4); +reg_write( DDR_REG_BASE +0x52ef5*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x52ef6*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x52ef7*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52ef8*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x52ef9*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x52efa*4+0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x52efb*4+0x02000000,0x225a); +reg_write( DDR_REG_BASE +0x52efc*4+0x02000000,0xc8c); +reg_write( DDR_REG_BASE +0x52efd*4+0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x52efe*4+0x02000000,0x609d); +reg_write( DDR_REG_BASE +0x52eff*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x52f00*4+0x02000000,0x64c); +reg_write( DDR_REG_BASE +0x52f01*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x52f02*4+0x02000000,0x64bc); +reg_write( DDR_REG_BASE +0x52f03*4+0x02000000,0x642c); +reg_write( DDR_REG_BASE +0x52f04*4+0x02000000,0x1e3c); +reg_write( DDR_REG_BASE +0x52f05*4+0x02000000,0x1302); +reg_write( DDR_REG_BASE +0x52f06*4+0x02000000,0xbeb); +reg_write( DDR_REG_BASE +0x52f07*4+0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x52f08*4+0x02000000,0x2300); +reg_write( DDR_REG_BASE +0x52f09*4+0x02000000,0x168e); +reg_write( DDR_REG_BASE +0x52f0a*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x52f0b*4+0x02000000,0xadf); +reg_write( DDR_REG_BASE +0x52f0c*4+0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x52f0d*4+0x02000000,0x2614); +reg_write( DDR_REG_BASE +0x52f0e*4+0x02000000,0x308b); +reg_write( DDR_REG_BASE +0x52f0f*4+0x02000000,0xc4c4); +reg_write( DDR_REG_BASE +0x52f10*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52f11*4+0x02000000,0x1209); +reg_write( DDR_REG_BASE +0x52f12*4+0x02000000,0x308d); +reg_write( DDR_REG_BASE +0x52f13*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x52f14*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x52f15*4+0x02000000,0x1a09); +reg_write( DDR_REG_BASE +0x52f16*4+0x02000000,0x3382); +reg_write( DDR_REG_BASE +0x52f17*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x52f18*4+0x02000000,0x26f0); +reg_write( DDR_REG_BASE +0x52f19*4+0x02000000,0x73c0); +reg_write( DDR_REG_BASE +0x52f1a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52f1b*4+0x02000000,0x8e8); +reg_write( DDR_REG_BASE +0x52f1c*4+0x02000000,0xb62); +reg_write( DDR_REG_BASE +0x52f1d*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x52f1e*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x52f1f*4+0x02000000,0xcc22); +reg_write( DDR_REG_BASE +0x52f20*4+0x02000000,0xff1); +reg_write( DDR_REG_BASE +0x52f21*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52f22*4+0x02000000,0x1a09); +reg_write( DDR_REG_BASE +0x52f23*4+0x02000000,0x3342); +reg_write( DDR_REG_BASE +0x52f24*4+0x02000000,0x1a22); +reg_write( DDR_REG_BASE +0x52f25*4+0x02000000,0x339c); +reg_write( DDR_REG_BASE +0x52f26*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52f27*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52f28*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x52f29*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52f2a*4+0x02000000,0x1ea); +reg_write( DDR_REG_BASE +0x52f2b*4+0x02000000,0x9340); +reg_write( DDR_REG_BASE +0x52f2c*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52f2d*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52f2e*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52f2f*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52f30*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52f31*4+0x02000000,0xfe00); +reg_write( DDR_REG_BASE +0x52f32*4+0x02000000,0x2204); +reg_write( DDR_REG_BASE +0x52f33*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x52f34*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52f35*4+0x02000000,0xc0ff); +reg_write( DDR_REG_BASE +0x52f36*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x52f37*4+0x02000000,0x9341); +reg_write( DDR_REG_BASE +0x52f38*4+0x02000000,0xb300); +reg_write( DDR_REG_BASE +0x52f39*4+0x02000000,0xb962); +reg_write( DDR_REG_BASE +0x52f3a*4+0x02000000,0x226c); +reg_write( DDR_REG_BASE +0x52f3b*4+0x02000000,0x140); +reg_write( DDR_REG_BASE +0x52f3c*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52f3d*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x52f3e*4+0x02000000,0xb301); +reg_write( DDR_REG_BASE +0x52f3f*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52f40*4+0x02000000,0x7a1b); +reg_write( DDR_REG_BASE +0x52f41*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x52f42*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x52f43*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52f44*4+0x02000000,0xe164); +reg_write( DDR_REG_BASE +0x52f45*4+0x02000000,0x1a00); +reg_write( DDR_REG_BASE +0x52f46*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x52f47*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x52f48*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52f49*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x52f4a*4+0x02000000,0x8a61); +reg_write( DDR_REG_BASE +0x52f4b*4+0x02000000,0x8a80); +reg_write( DDR_REG_BASE +0x52f4c*4+0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x52f4d*4+0x02000000,0x241a); +reg_write( DDR_REG_BASE +0x52f4e*4+0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x52f4f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52f50*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52f51*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x52f52*4+0x02000000,0x7a05); +reg_write( DDR_REG_BASE +0x52f53*4+0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x52f54*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x52f55*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x52f56*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52f57*4+0x02000000,0x164); +reg_write( DDR_REG_BASE +0x52f58*4+0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x52f59*4+0x02000000,0xbeb); +reg_write( DDR_REG_BASE +0x52f5a*4+0x02000000,0x8305); +reg_write( DDR_REG_BASE +0x52f5b*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52f5c*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x52f5d*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52f5e*4+0x02000000,0x710d); +reg_write( DDR_REG_BASE +0x52f5f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52f60*4+0x02000000,0x6); +reg_write( DDR_REG_BASE +0x52f61*4+0x02000000,0xe56d); +reg_write( DDR_REG_BASE +0x52f62*4+0x02000000,0x2d85); +reg_write( DDR_REG_BASE +0x52f63*4+0x02000000,0x1b81); +reg_write( DDR_REG_BASE +0x52f64*4+0x02000000,0x2553); +reg_write( DDR_REG_BASE +0x52f65*4+0x02000000,0x9041); +reg_write( DDR_REG_BASE +0x52f66*4+0x02000000,0xf205); +reg_write( DDR_REG_BASE +0x52f67*4+0x02000000,0x78af); +reg_write( DDR_REG_BASE +0x52f68*4+0x02000000,0x214e); +reg_write( DDR_REG_BASE +0x52f69*4+0x02000000,0x10d); +reg_write( DDR_REG_BASE +0x52f6a*4+0x02000000,0x651d); +reg_write( DDR_REG_BASE +0x52f6b*4+0x02000000,0x7aaf); +reg_write( DDR_REG_BASE +0x52f6c*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52f6d*4+0x02000000,0xaf); +reg_write( DDR_REG_BASE +0x52f6e*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52f6f*4+0x02000000,0xfe2); +reg_write( DDR_REG_BASE +0x52f70*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52f71*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x52f72*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52f73*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52f74*4+0x02000000,0x7c8); +reg_write( DDR_REG_BASE +0x52f75*4+0x02000000,0xa8a0); +reg_write( DDR_REG_BASE +0x52f76*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x52f77*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52f78*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52f79*4+0x02000000,0x266f); +reg_write( DDR_REG_BASE +0x52f7a*4+0x02000000,0x15c3); +reg_write( DDR_REG_BASE +0x52f7b*4+0x02000000,0x8e40); +reg_write( DDR_REG_BASE +0x52f7c*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x52f7d*4+0x02000000,0xea17); +reg_write( DDR_REG_BASE +0x52f7e*4+0x02000000,0xc1a); +reg_write( DDR_REG_BASE +0x52f7f*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52f80*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x52f81*4+0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x52f82*4+0x02000000,0xe887); +reg_write( DDR_REG_BASE +0x52f83*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52f84*4+0x02000000,0xd6); +reg_write( DDR_REG_BASE +0x52f85*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52f86*4+0x02000000,0xa46); +reg_write( DDR_REG_BASE +0x52f87*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x52f88*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52f89*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x52f8a*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52f8b*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52f8c*4+0x02000000,0x7f05); +reg_write( DDR_REG_BASE +0x52f8d*4+0x02000000,0x78bb); +reg_write( DDR_REG_BASE +0x52f8e*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52f8f*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52f90*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52f91*4+0x02000000,0xfe92); +reg_write( DDR_REG_BASE +0x52f92*4+0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x52f93*4+0x02000000,0x16ff); +reg_write( DDR_REG_BASE +0x52f94*4+0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x52f95*4+0x02000000,0xea18); +reg_write( DDR_REG_BASE +0x52f96*4+0x02000000,0xbea); +reg_write( DDR_REG_BASE +0x52f97*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52f98*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x52f99*4+0x02000000,0x228c); +reg_write( DDR_REG_BASE +0x52f9a*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x52f9b*4+0x02000000,0xf209); +reg_write( DDR_REG_BASE +0x52f9c*4+0x02000000,0xe888); +reg_write( DDR_REG_BASE +0x52f9d*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52f9e*4+0x02000000,0xd7); +reg_write( DDR_REG_BASE +0x52f9f*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52fa0*4+0x02000000,0xa12); +reg_write( DDR_REG_BASE +0x52fa1*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x52fa2*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52fa3*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52fa4*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52fa5*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52fa6*4+0x02000000,0x79bb); +reg_write( DDR_REG_BASE +0x52fa7*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x52fa8*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52fa9*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52faa*4+0x02000000,0xfe9a); +reg_write( DDR_REG_BASE +0x52fab*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x52fac*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52fad*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52fae*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x52faf*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52fb0*4+0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x52fb1*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52fb2*4+0x02000000,0x9); +reg_write( DDR_REG_BASE +0x52fb3*4+0x02000000,0xea1a); +reg_write( DDR_REG_BASE +0x52fb4*4+0x02000000,0xa23); +reg_write( DDR_REG_BASE +0x52fb5*4+0x02000000,0xa30); +reg_write( DDR_REG_BASE +0x52fb6*4+0x02000000,0x720c); +reg_write( DDR_REG_BASE +0x52fb7*4+0x02000000,0x228c); +reg_write( DDR_REG_BASE +0x52fb8*4+0x02000000,0x8c03); +reg_write( DDR_REG_BASE +0x52fb9*4+0x02000000,0xf20c); +reg_write( DDR_REG_BASE +0x52fba*4+0x02000000,0xe2f8); +reg_write( DDR_REG_BASE +0x52fbb*4+0x02000000,0xf404); +reg_write( DDR_REG_BASE +0x52fbc*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52fbd*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x52fbe*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52fbf*4+0x02000000,0xd8); +reg_write( DDR_REG_BASE +0x52fc0*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52fc1*4+0x02000000,0x9d2); +reg_write( DDR_REG_BASE +0x52fc2*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x52fc3*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52fc4*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52fc5*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52fc6*4+0x02000000,0x401); +reg_write( DDR_REG_BASE +0x52fc7*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52fc8*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52fc9*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52fca*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52fcb*4+0x02000000,0xe0a0); +reg_write( DDR_REG_BASE +0x52fcc*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x52fcd*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52fce*4+0x02000000,0xc0e6); +reg_write( DDR_REG_BASE +0x52fcf*4+0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x52fd0*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x52fd1*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52fd2*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52fd3*4+0x02000000,0xff64); +reg_write( DDR_REG_BASE +0x52fd4*4+0x02000000,0xb1e0); +reg_write( DDR_REG_BASE +0x52fd5*4+0x02000000,0x1904); +reg_write( DDR_REG_BASE +0x52fd6*4+0x02000000,0x45); +reg_write( DDR_REG_BASE +0x52fd7*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x52fd8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52fd9*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x52fda*4+0x02000000,0x8a21); +reg_write( DDR_REG_BASE +0x52fdb*4+0x02000000,0x8ac0); +reg_write( DDR_REG_BASE +0x52fdc*4+0x02000000,0xf039); +reg_write( DDR_REG_BASE +0x52fdd*4+0x02000000,0x228c); +reg_write( DDR_REG_BASE +0x52fde*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x52fdf*4+0x02000000,0xf418); +reg_write( DDR_REG_BASE +0x52fe0*4+0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x52fe1*4+0x02000000,0x1f83); +reg_write( DDR_REG_BASE +0x52fe2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52fe3*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52fe4*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x52fe5*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52fe6*4+0x02000000,0x1f64); +reg_write( DDR_REG_BASE +0x52fe7*4+0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x52fe8*4+0x02000000,0x8c); +reg_write( DDR_REG_BASE +0x52fe9*4+0x02000000,0x7444); +reg_write( DDR_REG_BASE +0x52fea*4+0x02000000,0x7a65); +reg_write( DDR_REG_BASE +0x52feb*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x52fec*4+0x02000000,0xb51); +reg_write( DDR_REG_BASE +0x52fed*4+0x02000000,0x123f); +reg_write( DDR_REG_BASE +0x52fee*4+0x02000000,0xb2e0); +reg_write( DDR_REG_BASE +0x52fef*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x52ff0*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52ff1*4+0x02000000,0xf164); +reg_write( DDR_REG_BASE +0x52ff2*4+0x02000000,0xb2e0); +reg_write( DDR_REG_BASE +0x52ff3*4+0x02000000,0x1a04); +reg_write( DDR_REG_BASE +0x52ff4*4+0x02000000,0x45); +reg_write( DDR_REG_BASE +0x52ff5*4+0x02000000,0xf020); +reg_write( DDR_REG_BASE +0x52ff6*4+0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x52ff7*4+0x02000000,0x32c0); +reg_write( DDR_REG_BASE +0x52ff8*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x52ff9*4+0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x52ffa*4+0x02000000,0xf753); +reg_write( DDR_REG_BASE +0x52ffb*4+0x02000000,0x4381); +reg_write( DDR_REG_BASE +0x52ffc*4+0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x52ffd*4+0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x52ffe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52fff*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x53000*4+0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x53001*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x53002*4+0x02000000,0x7b45); +reg_write( DDR_REG_BASE +0x53003*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x53004*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x53005*4+0x02000000,0x164); +reg_write( DDR_REG_BASE +0x53006*4+0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x53007*4+0x02000000,0x8d); +reg_write( DDR_REG_BASE +0x53008*4+0x02000000,0x7444); +reg_write( DDR_REG_BASE +0x53009*4+0x02000000,0x7b45); +reg_write( DDR_REG_BASE +0x5300a*4+0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x5300b*4+0x02000000,0x1b00); +reg_write( DDR_REG_BASE +0x5300c*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x5300d*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x5300e*4+0x02000000,0xe0d); +reg_write( DDR_REG_BASE +0x5300f*4+0x02000000,0x3010); +reg_write( DDR_REG_BASE +0x53010*4+0x02000000,0xcd5); +reg_write( DDR_REG_BASE +0x53011*4+0x02000000,0x9274); +reg_write( DDR_REG_BASE +0x53012*4+0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x53013*4+0x02000000,0xb782); +reg_write( DDR_REG_BASE +0x53014*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x53015*4+0x02000000,0x993); +reg_write( DDR_REG_BASE +0x53016*4+0x02000000,0x83a5); +reg_write( DDR_REG_BASE +0x53017*4+0x02000000,0x222f); +reg_write( DDR_REG_BASE +0x53018*4+0x02000000,0x2c7); +reg_write( DDR_REG_BASE +0x53019*4+0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x5301a*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5301b*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5301c*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5301d*4+0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x5301e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5301f*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x53020*4+0x02000000,0x30); +reg_write( DDR_REG_BASE +0x53021*4+0x02000000,0x10b4); +reg_write( DDR_REG_BASE +0x53022*4+0x02000000,0x501); +reg_write( DDR_REG_BASE +0x53023*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53024*4+0x02000000,0x708f); +reg_write( DDR_REG_BASE +0x53025*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53026*4+0x02000000,0x25); +reg_write( DDR_REG_BASE +0x53027*4+0x02000000,0x90d); +reg_write( DDR_REG_BASE +0x53028*4+0x02000000,0x171); +reg_write( DDR_REG_BASE +0x53029*4+0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x5302a*4+0x02000000,0xb0e1); +reg_write( DDR_REG_BASE +0x5302b*4+0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x5302c*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5302d*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x5302e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5302f*4+0x02000000,0x58); +reg_write( DDR_REG_BASE +0x53030*4+0x02000000,0xb021); +reg_write( DDR_REG_BASE +0x53031*4+0x02000000,0xf6f); +reg_write( DDR_REG_BASE +0x53032*4+0x02000000,0x1030); +reg_write( DDR_REG_BASE +0x53033*4+0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x53034*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53035*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53036*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53037*4+0x02000000,0x32); +reg_write( DDR_REG_BASE +0x53038*4+0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x53039*4+0x02000000,0x108d); +reg_write( DDR_REG_BASE +0x5303a*4+0x02000000,0xb8e3); +reg_write( DDR_REG_BASE +0x5303b*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5303c*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5303d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5303e*4+0x02000000,0x7cf); +reg_write( DDR_REG_BASE +0x5303f*4+0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x53040*4+0x02000000,0x30a1); +reg_write( DDR_REG_BASE +0x53041*4+0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x53042*4+0x02000000,0x104e); +reg_write( DDR_REG_BASE +0x53043*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x53044*4+0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x53045*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x53046*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53047*4+0x02000000,0x2753); +reg_write( DDR_REG_BASE +0x53048*4+0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x53049*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x5304a*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x5304b*4+0x02000000,0xf848); +reg_write( DDR_REG_BASE +0x5304c*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x5304d*4+0x02000000,0xf841); +reg_write( DDR_REG_BASE +0x5304e*4+0x02000000,0xee07); +reg_write( DDR_REG_BASE +0x5304f*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x53050*4+0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x53051*4+0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x53052*4+0x02000000,0xfaa); +reg_write( DDR_REG_BASE +0x53053*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x53054*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53055*4+0x02000000,0xed08); +reg_write( DDR_REG_BASE +0x53056*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x53057*4+0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x53058*4+0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x53059*4+0x02000000,0xf9e); +reg_write( DDR_REG_BASE +0x5305a*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x5305b*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5305c*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x5305d*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5305e*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5305f*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53060*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53061*4+0x02000000,0x7cf); +reg_write( DDR_REG_BASE +0x53062*4+0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x53063*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x53064*4+0x02000000,0x9c3); +reg_write( DDR_REG_BASE +0x53065*4+0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x53066*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53067*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53068*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x53069*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5306a*4+0x02000000,0x58); +reg_write( DDR_REG_BASE +0x5306b*4+0x02000000,0xd6f); +reg_write( DDR_REG_BASE +0x5306c*4+0x02000000,0x1030); +reg_write( DDR_REG_BASE +0x5306d*4+0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x5306e*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5306f*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53070*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53071*4+0x02000000,0x65); +reg_write( DDR_REG_BASE +0x53072*4+0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x53073*4+0x02000000,0x108e); +reg_write( DDR_REG_BASE +0x53074*4+0x02000000,0xb8e3); +reg_write( DDR_REG_BASE +0x53075*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53076*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53077*4+0x02000000,0x7cf); +reg_write( DDR_REG_BASE +0x53078*4+0x02000000,0x8802); +reg_write( DDR_REG_BASE +0x53079*4+0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x5307a*4+0x02000000,0x30a1); +reg_write( DDR_REG_BASE +0x5307b*4+0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x5307c*4+0x02000000,0x104f); +reg_write( DDR_REG_BASE +0x5307d*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5307e*4+0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x5307f*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x53080*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53081*4+0x02000000,0x2553); +reg_write( DDR_REG_BASE +0x53082*4+0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x53083*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x53084*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53085*4+0x02000000,0xf82b); +reg_write( DDR_REG_BASE +0x53086*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x53087*4+0x02000000,0xf824); +reg_write( DDR_REG_BASE +0x53088*4+0x02000000,0xef07); +reg_write( DDR_REG_BASE +0x53089*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x5308a*4+0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x5308b*4+0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x5308c*4+0x02000000,0xf36); +reg_write( DDR_REG_BASE +0x5308d*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x5308e*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5308f*4+0x02000000,0xee08); +reg_write( DDR_REG_BASE +0x53090*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x53091*4+0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x53092*4+0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x53093*4+0x02000000,0xf2a); +reg_write( DDR_REG_BASE +0x53094*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x53095*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x53096*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x53097*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x53098*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x53099*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5309a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5309b*4+0x02000000,0x7cf); +reg_write( DDR_REG_BASE +0x5309c*4+0x02000000,0x8823); +reg_write( DDR_REG_BASE +0x5309d*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x5309e*4+0x02000000,0x9c3); +reg_write( DDR_REG_BASE +0x5309f*4+0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x530a0*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x530a1*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x530a2*4+0x02000000,0x708e); +reg_write( DDR_REG_BASE +0x530a3*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x530a4*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x530a5*4+0x02000000,0xfaa); +reg_write( DDR_REG_BASE +0x530a6*4+0x02000000,0xfdcf); +reg_write( DDR_REG_BASE +0x530a7*4+0x02000000,0xfb2); +reg_write( DDR_REG_BASE +0x530a8*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x530a9*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x530aa*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x530ab*4+0x02000000,0xcfe); +reg_write( DDR_REG_BASE +0x530ac*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x530ad*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x530ae*4+0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x530af*4+0x02000000,0x1f8c); +reg_write( DDR_REG_BASE +0x530b0*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x530b1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530b2*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x530b3*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x530b4*4+0x02000000,0x1ea); +reg_write( DDR_REG_BASE +0x530b5*4+0x02000000,0x9300); +reg_write( DDR_REG_BASE +0x530b6*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x530b7*4+0x02000000,0x9012); +reg_write( DDR_REG_BASE +0x530b8*4+0x02000000,0x402); +reg_write( DDR_REG_BASE +0x530b9*4+0x02000000,0x2405); +reg_write( DDR_REG_BASE +0x530ba*4+0x02000000,0x1342); +reg_write( DDR_REG_BASE +0x530bb*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x530bc*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x530bd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530be*4+0x02000000,0x3f00); +reg_write( DDR_REG_BASE +0x530bf*4+0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x530c0*4+0x02000000,0x6d44); +reg_write( DDR_REG_BASE +0x530c1*4+0x02000000,0x7a85); +reg_write( DDR_REG_BASE +0x530c2*4+0x02000000,0x2196); +reg_write( DDR_REG_BASE +0x530c3*4+0x02000000,0x6); +reg_write( DDR_REG_BASE +0x530c4*4+0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x530c5*4+0x02000000,0x9321); +reg_write( DDR_REG_BASE +0x530c6*4+0x02000000,0x6d02); +reg_write( DDR_REG_BASE +0x530c7*4+0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x530c8*4+0x02000000,0xb9c5); +reg_write( DDR_REG_BASE +0x530c9*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x530ca*4+0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x530cb*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x530cc*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x530cd*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x530ce*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x530cf*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x530d0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530d1*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x530d2*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x530d3*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x530d4*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x530d5*4+0x02000000,0x154); +reg_write( DDR_REG_BASE +0x530d6*4+0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x530d7*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x530d8*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x530d9*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x530da*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x530db*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x530dc*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x530dd*4+0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x530de*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x530df*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x530e0*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x530e1*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x530e2*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x530e3*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x530e4*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x530e5*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x530e6*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x530e7*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x530e8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x530e9*4+0x02000000,0x6e1); +reg_write( DDR_REG_BASE +0x530ea*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x530eb*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x530ec*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x530ed*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x530ee*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x530ef*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x530f0*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x530f1*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x530f2*4+0x02000000,0x8f2); +reg_write( DDR_REG_BASE +0x530f3*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x530f4*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x530f5*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x530f6*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x530f7*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x530f8*4+0x02000000,0x6e1); +reg_write( DDR_REG_BASE +0x530f9*4+0x02000000,0xd910); +reg_write( DDR_REG_BASE +0x530fa*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x530fb*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x530fc*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x530fd*4+0x02000000,0xdb0c); +reg_write( DDR_REG_BASE +0x530fe*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x530ff*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53100*4+0x02000000,0x8d6); +reg_write( DDR_REG_BASE +0x53101*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53102*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53103*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53104*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x53105*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53106*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x53107*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x53108*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x53109*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5310a*4+0x02000000,0x8c2); +reg_write( DDR_REG_BASE +0x5310b*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x5310c*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5310d*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x5310e*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x5310f*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x53110*4+0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x53111*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x53112*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x53113*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53114*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53115*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53116*4+0x02000000,0x736c); +reg_write( DDR_REG_BASE +0x53117*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x53118*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x53119*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5311a*4+0x02000000,0x8a2); +reg_write( DDR_REG_BASE +0x5311b*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x5311c*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5311d*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x5311e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5311f*4+0x02000000,0x6e1); +reg_write( DDR_REG_BASE +0x53120*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x53121*4+0x02000000,0x825); +reg_write( DDR_REG_BASE +0x53122*4+0x02000000,0xb4); +reg_write( DDR_REG_BASE +0x53123*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53124*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x53125*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x53126*4+0x02000000,0xb862); +reg_write( DDR_REG_BASE +0x53127*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x53128*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x53129*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5312a*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5312b*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5312c*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5312d*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5312e*4+0x02000000,0x87a); +reg_write( DDR_REG_BASE +0x5312f*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53130*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53131*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x53132*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x53133*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53134*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53135*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53136*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x53137*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x53138*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53139*4+0x02000000,0x866); +reg_write( DDR_REG_BASE +0x5313a*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x5313b*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5313c*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x5313d*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x5313e*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5313f*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x53140*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53141*4+0x02000000,0xdb0c); +reg_write( DDR_REG_BASE +0x53142*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x53143*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53144*4+0x02000000,0x84e); +reg_write( DDR_REG_BASE +0x53145*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53146*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53147*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x53148*4+0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x53149*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5314a*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x5314b*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5314c*4+0x02000000,0x110); +reg_write( DDR_REG_BASE +0x5314d*4+0x02000000,0x9200); +reg_write( DDR_REG_BASE +0x5314e*4+0x02000000,0x204f); +reg_write( DDR_REG_BASE +0x5314f*4+0x02000000,0x101); +reg_write( DDR_REG_BASE +0x53150*4+0x02000000,0xb8a4); +reg_write( DDR_REG_BASE +0x53151*4+0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x53152*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x53153*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x53154*4+0x02000000,0xc0e6); +reg_write( DDR_REG_BASE +0x53155*4+0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x53156*4+0x02000000,0x483); +reg_write( DDR_REG_BASE +0x53157*4+0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x53158*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53159*4+0x02000000,0x6e2); +reg_write( DDR_REG_BASE +0x5315a*4+0x02000000,0x638d); +reg_write( DDR_REG_BASE +0x5315b*4+0x02000000,0x6479); +reg_write( DDR_REG_BASE +0x5315c*4+0x02000000,0x89c1); +reg_write( DDR_REG_BASE +0x5315d*4+0x02000000,0x7d04); +reg_write( DDR_REG_BASE +0x5315e*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5315f*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x53160*4+0x02000000,0x629a); +reg_write( DDR_REG_BASE +0x53161*4+0x02000000,0x8ae3); +reg_write( DDR_REG_BASE +0x53162*4+0x02000000,0x809); +reg_write( DDR_REG_BASE +0x53163*4+0x02000000,0x3ce); +reg_write( DDR_REG_BASE +0x53164*4+0x02000000,0x8a42); +reg_write( DDR_REG_BASE +0x53165*4+0x02000000,0x7d45); +reg_write( DDR_REG_BASE +0x53166*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x53167*4+0x02000000,0x9f5); +reg_write( DDR_REG_BASE +0x53168*4+0x02000000,0x83a4); +reg_write( DDR_REG_BASE +0x53169*4+0x02000000,0x2314); +reg_write( DDR_REG_BASE +0x5316a*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x5316b*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x5316c*4+0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x5316d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5316e*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5316f*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53170*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53171*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x53172*4+0x02000000,0x3d09); +reg_write( DDR_REG_BASE +0x53173*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53174*4+0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x53175*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x53176*4+0x02000000,0x8820); +reg_write( DDR_REG_BASE +0x53177*4+0x02000000,0x1054); +reg_write( DDR_REG_BASE +0x53178*4+0x02000000,0x83); +reg_write( DDR_REG_BASE +0x53179*4+0x02000000,0x1021); +reg_write( DDR_REG_BASE +0x5317a*4+0x02000000,0x8d); +reg_write( DDR_REG_BASE +0x5317b*4+0x02000000,0x10fd); +reg_write( DDR_REG_BASE +0x5317c*4+0x02000000,0x808e); +reg_write( DDR_REG_BASE +0x5317d*4+0x02000000,0x1209); +reg_write( DDR_REG_BASE +0x5317e*4+0x02000000,0x308b); +reg_write( DDR_REG_BASE +0x5317f*4+0x02000000,0x1208); +reg_write( DDR_REG_BASE +0x53180*4+0x02000000,0x308f); +reg_write( DDR_REG_BASE +0x53181*4+0x02000000,0xc149); +reg_write( DDR_REG_BASE +0x53182*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x53183*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x53184*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53185*4+0x02000000,0x10c); +reg_write( DDR_REG_BASE +0x53186*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53187*4+0x02000000,0x8ce); +reg_write( DDR_REG_BASE +0x53188*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x53189*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x5318a*4+0x02000000,0xc096); +reg_write( DDR_REG_BASE +0x5318b*4+0x02000000,0x8c6); +reg_write( DDR_REG_BASE +0x5318c*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5318d*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x5318e*4+0x02000000,0xbee2); +reg_write( DDR_REG_BASE +0x5318f*4+0x02000000,0x6f01); +reg_write( DDR_REG_BASE +0x53190*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x53191*4+0x02000000,0x20df); +reg_write( DDR_REG_BASE +0x53192*4+0x02000000,0x3e1); +reg_write( DDR_REG_BASE +0x53193*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x53194*4+0x02000000,0x7ba5); +reg_write( DDR_REG_BASE +0x53195*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x53196*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53197*4+0x02000000,0x43d9); +reg_write( DDR_REG_BASE +0x53198*4+0x02000000,0xc34d); +reg_write( DDR_REG_BASE +0x53199*4+0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x5319a*4+0x02000000,0x141); +reg_write( DDR_REG_BASE +0x5319b*4+0x02000000,0xb882); +reg_write( DDR_REG_BASE +0x5319c*4+0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x5319d*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5319e*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x5319f*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x531a0*4+0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x531a1*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x531a2*4+0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x531a3*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x531a4*4+0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x531a5*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x531a6*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x531a7*4+0x02000000,0x180); +reg_write( DDR_REG_BASE +0x531a8*4+0x02000000,0xc04e); +reg_write( DDR_REG_BASE +0x531a9*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x531aa*4+0x02000000,0xb869); +reg_write( DDR_REG_BASE +0x531ab*4+0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x531ac*4+0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x531ad*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x531ae*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x531af*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x531b0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531b1*4+0x02000000,0xc04f); +reg_write( DDR_REG_BASE +0x531b2*4+0x02000000,0x2378); +reg_write( DDR_REG_BASE +0x531b3*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x531b4*4+0x02000000,0x28d); +reg_write( DDR_REG_BASE +0x531b5*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x531b6*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x531b7*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x531b8*4+0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x531b9*4+0x02000000,0x17c0); +reg_write( DDR_REG_BASE +0x531ba*4+0x02000000,0xc10a); +reg_write( DDR_REG_BASE +0x531bb*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x531bc*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x531bd*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x531be*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x531bf*4+0x02000000,0x7b7b); +reg_write( DDR_REG_BASE +0x531c0*4+0x02000000,0xaea); +reg_write( DDR_REG_BASE +0x531c1*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x531c2*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x531c3*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x531c4*4+0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x531c5*4+0x02000000,0x7b0b); +reg_write( DDR_REG_BASE +0x531c6*4+0x02000000,0x266); +reg_write( DDR_REG_BASE +0x531c7*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x531c8*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x531c9*4+0x02000000,0xb880); +reg_write( DDR_REG_BASE +0x531ca*4+0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x531cb*4+0x02000000,0x141); +reg_write( DDR_REG_BASE +0x531cc*4+0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x531cd*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x531ce*4+0x02000000,0xc050); +reg_write( DDR_REG_BASE +0x531cf*4+0x02000000,0x215); +reg_write( DDR_REG_BASE +0x531d0*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x531d1*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x531d2*4+0x02000000,0xc110); +reg_write( DDR_REG_BASE +0x531d3*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x531d4*4+0x02000000,0xe5e); +reg_write( DDR_REG_BASE +0x531d5*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x531d6*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x531d7*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x531d8*4+0x02000000,0x1f6); +reg_write( DDR_REG_BASE +0x531d9*4+0x02000000,0x21); +reg_write( DDR_REG_BASE +0x531da*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x531db*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x531dc*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x531dd*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x531de*4+0x02000000,0xa8c1); +reg_write( DDR_REG_BASE +0x531df*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x531e0*4+0x02000000,0xb863); +reg_write( DDR_REG_BASE +0x531e1*4+0x02000000,0x7214); +reg_write( DDR_REG_BASE +0x531e2*4+0x02000000,0xa28); +reg_write( DDR_REG_BASE +0x531e3*4+0x02000000,0xfd45); +reg_write( DDR_REG_BASE +0x531e4*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x531e5*4+0x02000000,0xf79a); +reg_write( DDR_REG_BASE +0x531e6*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x531e7*4+0x02000000,0x831); +reg_write( DDR_REG_BASE +0x531e8*4+0x02000000,0x1b1); +reg_write( DDR_REG_BASE +0x531e9*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x531ea*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x531eb*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x531ec*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x531ed*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x531ee*4+0x02000000,0x265a); +reg_write( DDR_REG_BASE +0x531ef*4+0x02000000,0x1641); +reg_write( DDR_REG_BASE +0x531f0*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x531f1*4+0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x531f2*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x531f3*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x531f4*4+0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x531f5*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x531f6*4+0x02000000,0x67f); +reg_write( DDR_REG_BASE +0x531f7*4+0x02000000,0x7dbd); +reg_write( DDR_REG_BASE +0x531f8*4+0x02000000,0x7dbd); +reg_write( DDR_REG_BASE +0x531f9*4+0x02000000,0x7dbd); +reg_write( DDR_REG_BASE +0x531fa*4+0x02000000,0x7dbd); +reg_write( DDR_REG_BASE +0x531fb*4+0x02000000,0x7dbd); +reg_write( DDR_REG_BASE +0x531fc*4+0x02000000,0x7dbd); +reg_write( DDR_REG_BASE +0x531fd*4+0x02000000,0x7dbd); +reg_write( DDR_REG_BASE +0x531fe*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x531ff*4+0x02000000,0x3e00); +reg_write( DDR_REG_BASE +0x53200*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53201*4+0x02000000,0xfda); +reg_write( DDR_REG_BASE +0x53202*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x53203*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x53204*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53205*4+0x02000000,0x7614); +reg_write( DDR_REG_BASE +0x53206*4+0x02000000,0x164); +reg_write( DDR_REG_BASE +0x53207*4+0x02000000,0xd); +reg_write( DDR_REG_BASE +0x53208*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53209*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x5320a*4+0x02000000,0x2025); +reg_write( DDR_REG_BASE +0x5320b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5320c*4+0x02000000,0xf025); +reg_write( DDR_REG_BASE +0x5320d*4+0x02000000,0xf02b); +reg_write( DDR_REG_BASE +0x5320e*4+0x02000000,0xf02f); +reg_write( DDR_REG_BASE +0x5320f*4+0x02000000,0xf033); +reg_write( DDR_REG_BASE +0x53210*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x53211*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x53212*4+0x02000000,0xf034); +reg_write( DDR_REG_BASE +0x53213*4+0x02000000,0xc096); +reg_write( DDR_REG_BASE +0x53214*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x53215*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x53216*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x53217*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53218*4+0x02000000,0x10c); +reg_write( DDR_REG_BASE +0x53219*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5321a*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x5321b*4+0x02000000,0x3e00); +reg_write( DDR_REG_BASE +0x5321c*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5321d*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x5321e*4+0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x5321f*4+0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x53220*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x53221*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x53222*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53223*4+0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x53224*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53225*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53226*4+0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x53227*4+0x02000000,0x7514); +reg_write( DDR_REG_BASE +0x53228*4+0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x53229*4+0x02000000,0x31a1); +reg_write( DDR_REG_BASE +0x5322a*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x5322b*4+0x02000000,0xd7e); +reg_write( DDR_REG_BASE +0x5322c*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5322d*4+0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x5322e*4+0x02000000,0xdf8c); +reg_write( DDR_REG_BASE +0x5322f*4+0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x53230*4+0x02000000,0xf088); +reg_write( DDR_REG_BASE +0x53231*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53232*4+0x02000000,0xe0e); +reg_write( DDR_REG_BASE +0x53233*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x53234*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x53235*4+0x02000000,0x3e01); +reg_write( DDR_REG_BASE +0x53236*4+0x02000000,0xf09d); +reg_write( DDR_REG_BASE +0x53237*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53238*4+0x02000000,0xf36); +reg_write( DDR_REG_BASE +0x53239*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5323a*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x5323b*4+0x02000000,0x3e01); +reg_write( DDR_REG_BASE +0x5323c*4+0x02000000,0xf097); +reg_write( DDR_REG_BASE +0x5323d*4+0x02000000,0xac6); +reg_write( DDR_REG_BASE +0x5323e*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5323f*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53240*4+0x02000000,0xf093); +reg_write( DDR_REG_BASE +0x53241*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53242*4+0x02000000,0xf5e); +reg_write( DDR_REG_BASE +0x53243*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x53244*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x53245*4+0x02000000,0xf08f); +reg_write( DDR_REG_BASE +0x53246*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53247*4+0x02000000,0x76c4); +reg_write( DDR_REG_BASE +0x53248*4+0x02000000,0x900f); +reg_write( DDR_REG_BASE +0x53249*4+0x02000000,0xe022); +reg_write( DDR_REG_BASE +0x5324a*4+0x02000000,0xc096); +reg_write( DDR_REG_BASE +0x5324b*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5324c*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x5324d*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x5324e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5324f*4+0x02000000,0x10c); +reg_write( DDR_REG_BASE +0x53250*4+0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x53251*4+0x02000000,0xc308); +reg_write( DDR_REG_BASE +0x53252*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x53253*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x53254*4+0x02000000,0x3e00); +reg_write( DDR_REG_BASE +0x53255*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x53256*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53257*4+0x02000000,0xd96); +reg_write( DDR_REG_BASE +0x53258*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x53259*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5325a*4+0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x5325b*4+0x02000000,0xdcf); +reg_write( DDR_REG_BASE +0x5325c*4+0x02000000,0x1030); +reg_write( DDR_REG_BASE +0x5325d*4+0x02000000,0xdfc0); +reg_write( DDR_REG_BASE +0x5325e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5325f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53260*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x53261*4+0x02000000,0x8825); +reg_write( DDR_REG_BASE +0x53262*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53263*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53264*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x53265*4+0x02000000,0x8844); +reg_write( DDR_REG_BASE +0x53266*4+0x02000000,0x225f); +reg_write( DDR_REG_BASE +0x53267*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x53268*4+0x02000000,0xf02d); +reg_write( DDR_REG_BASE +0x53269*4+0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x5326a*4+0x02000000,0x30c0); +reg_write( DDR_REG_BASE +0x5326b*4+0x02000000,0xf025); +reg_write( DDR_REG_BASE +0x5326c*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x5326d*4+0x02000000,0x78d); +reg_write( DDR_REG_BASE +0x5326e*4+0x02000000,0xdf1b); +reg_write( DDR_REG_BASE +0x5326f*4+0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x53270*4+0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x53271*4+0x02000000,0x78bc); +reg_write( DDR_REG_BASE +0x53272*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x53273*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x53274*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x53275*4+0x02000000,0xbf61); +reg_write( DDR_REG_BASE +0x53276*4+0x02000000,0xfff); +reg_write( DDR_REG_BASE +0x53277*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x53278*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x53279*4+0x02000000,0x651f); +reg_write( DDR_REG_BASE +0x5327a*4+0x02000000,0xbfc4); +reg_write( DDR_REG_BASE +0x5327b*4+0x02000000,0x7f02); +reg_write( DDR_REG_BASE +0x5327c*4+0x02000000,0x2d44); +reg_write( DDR_REG_BASE +0x5327d*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x5327e*4+0x02000000,0x6ca1); +reg_write( DDR_REG_BASE +0x5327f*4+0x02000000,0x249a); +reg_write( DDR_REG_BASE +0x53280*4+0x02000000,0x1008); +reg_write( DDR_REG_BASE +0x53281*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x53282*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x53283*4+0x02000000,0x7f05); +reg_write( DDR_REG_BASE +0x53284*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x53285*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53286*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53287*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x53288*4+0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x53289*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5328a*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5328b*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x5328c*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x5328d*4+0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x5328e*4+0x02000000,0x44a9); +reg_write( DDR_REG_BASE +0x5328f*4+0x02000000,0xcbd); +reg_write( DDR_REG_BASE +0x53290*4+0x02000000,0x9234); +reg_write( DDR_REG_BASE +0x53291*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x53292*4+0x02000000,0x3e00); +reg_write( DDR_REG_BASE +0x53293*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x53294*4+0x02000000,0xe309); +reg_write( DDR_REG_BASE +0x53295*4+0x02000000,0x9ab); +reg_write( DDR_REG_BASE +0x53296*4+0x02000000,0x80a5); +reg_write( DDR_REG_BASE +0x53297*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x53298*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53299*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x5329a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5329b*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x5329c*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x5329d*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5329e*4+0x02000000,0xae2); +reg_write( DDR_REG_BASE +0x5329f*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x532a0*4+0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x532a1*4+0x02000000,0xc096); +reg_write( DDR_REG_BASE +0x532a2*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x532a3*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x532a4*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x532a5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532a6*4+0x02000000,0x10c); +reg_write( DDR_REG_BASE +0x532a7*4+0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x532a8*4+0x02000000,0xc308); +reg_write( DDR_REG_BASE +0x532a9*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x532aa*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x532ab*4+0x02000000,0x3e00); +reg_write( DDR_REG_BASE +0x532ac*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x532ad*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x532ae*4+0x02000000,0xce6); +reg_write( DDR_REG_BASE +0x532af*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x532b0*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x532b1*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x532b2*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x532b3*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x532b4*4+0x02000000,0xab6); +reg_write( DDR_REG_BASE +0x532b5*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x532b6*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x532b7*4+0x02000000,0xdfc0); +reg_write( DDR_REG_BASE +0x532b8*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x532b9*4+0x02000000,0x815); +reg_write( DDR_REG_BASE +0x532ba*4+0x02000000,0x370); +reg_write( DDR_REG_BASE +0x532bb*4+0x02000000,0x456b); +reg_write( DDR_REG_BASE +0x532bc*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x532bd*4+0x02000000,0x80d); +reg_write( DDR_REG_BASE +0x532be*4+0x02000000,0x1b0); +reg_write( DDR_REG_BASE +0x532bf*4+0x02000000,0x456b); +reg_write( DDR_REG_BASE +0x532c0*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x532c1*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x532c2*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x532c3*4+0x02000000,0xfea); +reg_write( DDR_REG_BASE +0x532c4*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x532c5*4+0x02000000,0xc191); +reg_write( DDR_REG_BASE +0x532c6*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x532c7*4+0x02000000,0xed0d); +reg_write( DDR_REG_BASE +0x532c8*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x532c9*4+0x02000000,0xc20e); +reg_write( DDR_REG_BASE +0x532ca*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x532cb*4+0x02000000,0x3e01); +reg_write( DDR_REG_BASE +0x532cc*4+0x02000000,0x671f); +reg_write( DDR_REG_BASE +0x532cd*4+0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x532ce*4+0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x532cf*4+0x02000000,0x84a); +reg_write( DDR_REG_BASE +0x532d0*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x532d1*4+0x02000000,0x78e5); +reg_write( DDR_REG_BASE +0x532d2*4+0x02000000,0x43b9); +reg_write( DDR_REG_BASE +0x532d3*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x532d4*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x532d5*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x532d6*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x532d7*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x532d8*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x532d9*4+0x02000000,0x7002); +reg_write( DDR_REG_BASE +0x532da*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x532db*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x532dc*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x532dd*4+0x02000000,0x7114); +reg_write( DDR_REG_BASE +0x532de*4+0x02000000,0x5e8); +reg_write( DDR_REG_BASE +0x532df*4+0x02000000,0xffee); +reg_write( DDR_REG_BASE +0x532e0*4+0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x532e1*4+0x02000000,0xd56); +reg_write( DDR_REG_BASE +0x532e2*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x532e3*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x532e4*4+0x02000000,0xca09); +reg_write( DDR_REG_BASE +0x532e5*4+0x02000000,0xe895); +reg_write( DDR_REG_BASE +0x532e6*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x532e7*4+0x02000000,0x811); +reg_write( DDR_REG_BASE +0x532e8*4+0x02000000,0xf1); +reg_write( DDR_REG_BASE +0x532e9*4+0x02000000,0x79cf); +reg_write( DDR_REG_BASE +0x532ea*4+0x02000000,0xcba); +reg_write( DDR_REG_BASE +0x532eb*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x532ec*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x532ed*4+0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x532ee*4+0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x532ef*4+0x02000000,0x817); +reg_write( DDR_REG_BASE +0x532f0*4+0x02000000,0x134); +reg_write( DDR_REG_BASE +0x532f1*4+0x02000000,0x7bcf); +reg_write( DDR_REG_BASE +0x532f2*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x532f3*4+0x02000000,0xc109); +reg_write( DDR_REG_BASE +0x532f4*4+0x02000000,0xc207); +reg_write( DDR_REG_BASE +0x532f5*4+0x02000000,0xbf2); +reg_write( DDR_REG_BASE +0x532f6*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x532f7*4+0x02000000,0x2052); +reg_write( DDR_REG_BASE +0x532f8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532f9*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x532fa*4+0x02000000,0x72d5); +reg_write( DDR_REG_BASE +0x532fb*4+0x02000000,0x57a); +reg_write( DDR_REG_BASE +0x532fc*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x532fd*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x532fe*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x532ff*4+0x02000000,0x819); +reg_write( DDR_REG_BASE +0x53300*4+0x02000000,0xd1); +reg_write( DDR_REG_BASE +0x53301*4+0x02000000,0xca09); +reg_write( DDR_REG_BASE +0x53302*4+0x02000000,0xe888); +reg_write( DDR_REG_BASE +0x53303*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53304*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53305*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53306*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53307*4+0x02000000,0xb8e5); +reg_write( DDR_REG_BASE +0x53308*4+0x02000000,0xcb8); +reg_write( DDR_REG_BASE +0x53309*4+0x02000000,0xfd42); +reg_write( DDR_REG_BASE +0x5330a*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5330b*4+0x02000000,0x7003); +reg_write( DDR_REG_BASE +0x5330c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5330d*4+0x02000000,0xf); +reg_write( DDR_REG_BASE +0x5330e*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x5330f*4+0x02000000,0x3d09); +reg_write( DDR_REG_BASE +0x53310*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x53311*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x53312*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53313*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x53314*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x53315*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53316*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53317*4+0x02000000,0xc1b1); +reg_write( DDR_REG_BASE +0x53318*4+0x02000000,0xc050); +reg_write( DDR_REG_BASE +0x53319*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5331a*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5331b*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5331c*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5331d*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x5331e*4+0x02000000,0xe96); +reg_write( DDR_REG_BASE +0x5331f*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x53320*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x53321*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53322*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53323*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x53324*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x53325*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x53326*4+0x02000000,0xb72); +reg_write( DDR_REG_BASE +0x53327*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x53328*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x53329*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x5332a*4+0x02000000,0xfca); +reg_write( DDR_REG_BASE +0x5332b*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x5332c*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x5332d*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x5332e*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5332f*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x53330*4+0x02000000,0x1f22); +reg_write( DDR_REG_BASE +0x53331*4+0x02000000,0x1015); +reg_write( DDR_REG_BASE +0x53332*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53333*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x53334*4+0x02000000,0x1fa7); +reg_write( DDR_REG_BASE +0x53335*4+0x02000000,0x101c); +reg_write( DDR_REG_BASE +0x53336*4+0x02000000,0x1fa8); +reg_write( DDR_REG_BASE +0x53337*4+0x02000000,0x101c); +reg_write( DDR_REG_BASE +0x53338*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x53339*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x5333a*4+0x02000000,0xb700); +reg_write( DDR_REG_BASE +0x5333b*4+0x02000000,0x1ffe); +reg_write( DDR_REG_BASE +0x5333c*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5333d*4+0x02000000,0xb705); +reg_write( DDR_REG_BASE +0x5333e*4+0x02000000,0x922); +reg_write( DDR_REG_BASE +0x5333f*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x53340*4+0x02000000,0x1ffc); +reg_write( DDR_REG_BASE +0x53341*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x53342*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x53343*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53344*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x53345*4+0x02000000,0x8e04); +reg_write( DDR_REG_BASE +0x53346*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x53347*4+0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x53348*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x53349*4+0x02000000,0x10fd); +reg_write( DDR_REG_BASE +0x5334a*4+0x02000000,0x809e); +reg_write( DDR_REG_BASE +0x5334b*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x5334c*4+0x02000000,0x3100); +reg_write( DDR_REG_BASE +0x5334d*4+0x02000000,0x780d); +reg_write( DDR_REG_BASE +0x5334e*4+0x02000000,0x791c); +reg_write( DDR_REG_BASE +0x5334f*4+0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x53350*4+0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x53351*4+0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x53352*4+0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x53353*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x53354*4+0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x53355*4+0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x53356*4+0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x53357*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x53358*4+0x02000000,0x8e05); +reg_write( DDR_REG_BASE +0x53359*4+0x02000000,0xc04d); +reg_write( DDR_REG_BASE +0x5335a*4+0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x5335b*4+0x02000000,0xc04e); +reg_write( DDR_REG_BASE +0x5335c*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x5335d*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x5335e*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5335f*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x53360*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53361*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53362*4+0x02000000,0x8e03); +reg_write( DDR_REG_BASE +0x53363*4+0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x53364*4+0x02000000,0x8e02); +reg_write( DDR_REG_BASE +0x53365*4+0x02000000,0x25f); +reg_write( DDR_REG_BASE +0x53366*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x53367*4+0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x53368*4+0x02000000,0xe13); +reg_write( DDR_REG_BASE +0x53369*4+0x02000000,0x315e); +reg_write( DDR_REG_BASE +0x5336a*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5336b*4+0x02000000,0xae05); +reg_write( DDR_REG_BASE +0x5336c*4+0x02000000,0xae04); +reg_write( DDR_REG_BASE +0x5336d*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5336e*4+0x02000000,0xae02); +reg_write( DDR_REG_BASE +0x5336f*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x53370*4+0x02000000,0xae03); +reg_write( DDR_REG_BASE +0x53371*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x53372*4+0x02000000,0x770c); +reg_write( DDR_REG_BASE +0x53373*4+0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x53374*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53375*4+0x02000000,0xf0d0); +reg_write( DDR_REG_BASE +0x53376*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x53377*4+0x02000000,0x37c1); +reg_write( DDR_REG_BASE +0x53378*4+0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x53379*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x5337a*4+0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x5337b*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x5337c*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5337d*4+0x02000000,0x1e01); +reg_write( DDR_REG_BASE +0x5337e*4+0x02000000,0x16c2); +reg_write( DDR_REG_BASE +0x5337f*4+0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x53380*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x53381*4+0x02000000,0x200f); +reg_write( DDR_REG_BASE +0x53382*4+0x02000000,0x6c2); +reg_write( DDR_REG_BASE +0x53383*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x53384*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x53385*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53386*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x53387*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53388*4+0x02000000,0x58); +reg_write( DDR_REG_BASE +0x53389*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x5338a*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5338b*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x5338c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5338d*4+0x02000000,0x25); +reg_write( DDR_REG_BASE +0x5338e*4+0x02000000,0x784f); +reg_write( DDR_REG_BASE +0x5338f*4+0x02000000,0x790b); +reg_write( DDR_REG_BASE +0x53390*4+0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x53391*4+0x02000000,0xf2b3); +reg_write( DDR_REG_BASE +0x53392*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x53393*4+0x02000000,0x6c7); +reg_write( DDR_REG_BASE +0x53394*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53395*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53396*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x53397*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x53398*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x53399*4+0x02000000,0x8ee); +reg_write( DDR_REG_BASE +0x5339a*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x5339b*4+0x02000000,0xc04f); +reg_write( DDR_REG_BASE +0x5339c*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x5339d*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5339e*4+0x02000000,0xd1e); +reg_write( DDR_REG_BASE +0x5339f*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x533a0*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x533a1*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x533a2*4+0x02000000,0xb52); +reg_write( DDR_REG_BASE +0x533a3*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x533a4*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x533a5*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x533a6*4+0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x533a7*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x533a8*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x533a9*4+0x02000000,0xe59f); +reg_write( DDR_REG_BASE +0x533aa*4+0x02000000,0x10c); +reg_write( DDR_REG_BASE +0x533ab*4+0x02000000,0x9); +reg_write( DDR_REG_BASE +0x533ac*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x533ad*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x533ae*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x533af*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x533b0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533b1*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x533b2*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x533b3*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x533b4*4+0x02000000,0xe040); +reg_write( DDR_REG_BASE +0x533b5*4+0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x533b6*4+0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x533b7*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x533b8*4+0x02000000,0x10fd); +reg_write( DDR_REG_BASE +0x533b9*4+0x02000000,0x8080); +reg_write( DDR_REG_BASE +0x533ba*4+0x02000000,0x82b); +reg_write( DDR_REG_BASE +0x533bb*4+0x02000000,0x15f); +reg_write( DDR_REG_BASE +0x533bc*4+0x02000000,0x8e25); +reg_write( DDR_REG_BASE +0x533bd*4+0x02000000,0x8e44); +reg_write( DDR_REG_BASE +0x533be*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x533bf*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x533c0*4+0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x533c1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533c2*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x533c3*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x533c4*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x533c5*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x533c6*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x533c7*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x533c8*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x533c9*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x533ca*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x533cb*4+0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x533cc*4+0x02000000,0x9e7); +reg_write( DDR_REG_BASE +0x533cd*4+0x02000000,0x8085); +reg_write( DDR_REG_BASE +0x533ce*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x533cf*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x533d0*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x533d1*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x533d2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533d3*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x533d4*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x533d5*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x533d6*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x533d7*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x533d8*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x533d9*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x533da*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x533db*4+0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x533dc*4+0x02000000,0x8ce); +reg_write( DDR_REG_BASE +0x533dd*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x533de*4+0x02000000,0xd814); +reg_write( DDR_REG_BASE +0x533df*4+0x02000000,0xa9e); +reg_write( DDR_REG_BASE +0x533e0*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x533e1*4+0x02000000,0xc010); +reg_write( DDR_REG_BASE +0x533e2*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x533e3*4+0x02000000,0xad2); +reg_write( DDR_REG_BASE +0x533e4*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x533e5*4+0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x533e6*4+0x02000000,0x8e04); +reg_write( DDR_REG_BASE +0x533e7*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x533e8*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x533e9*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x533ea*4+0x02000000,0xf034); +reg_write( DDR_REG_BASE +0x533eb*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x533ec*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x533ed*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x533ee*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x533ef*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533f0*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x533f1*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x533f2*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x533f3*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x533f4*4+0x02000000,0x170); +reg_write( DDR_REG_BASE +0x533f5*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x533f6*4+0x02000000,0xc245); +reg_write( DDR_REG_BASE +0x533f7*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x533f8*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x533f9*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x533fa*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x533fb*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x533fc*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x533fd*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x533fe*4+0x02000000,0x166); +reg_write( DDR_REG_BASE +0x533ff*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x53400*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x53401*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53402*4+0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x53403*4+0x02000000,0x200f); +reg_write( DDR_REG_BASE +0x53404*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x53405*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x53406*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x53407*4+0x02000000,0xae5); +reg_write( DDR_REG_BASE +0x53408*4+0x02000000,0x8234); +reg_write( DDR_REG_BASE +0x53409*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x5340a*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5340b*4+0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x5340c*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x5340d*4+0x02000000,0xf40b); +reg_write( DDR_REG_BASE +0x5340e*4+0x02000000,0xc303); +reg_write( DDR_REG_BASE +0x5340f*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x53410*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53411*4+0x02000000,0xe); +reg_write( DDR_REG_BASE +0x53412*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x53413*4+0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x53414*4+0x02000000,0xe96); +reg_write( DDR_REG_BASE +0x53415*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53416*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53417*4+0x02000000,0xc105); +reg_write( DDR_REG_BASE +0x53418*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x53419*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x5341a*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x5341b*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x5341c*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5341d*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5341e*4+0x02000000,0x8e25); +reg_write( DDR_REG_BASE +0x5341f*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x53420*4+0x02000000,0x997); +reg_write( DDR_REG_BASE +0x53421*4+0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x53422*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53423*4+0x02000000,0xdda); +reg_write( DDR_REG_BASE +0x53424*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53425*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x53426*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x53427*4+0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x53428*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x53429*4+0x02000000,0xf580); +reg_write( DDR_REG_BASE +0x5342a*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x5342b*4+0x02000000,0x2008); +reg_write( DDR_REG_BASE +0x5342c*4+0x02000000,0x340); +reg_write( DDR_REG_BASE +0x5342d*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5342e*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5342f*4+0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x53430*4+0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x53431*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53432*4+0x02000000,0x11); +reg_write( DDR_REG_BASE +0x53433*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53434*4+0x02000000,0x8ea); +reg_write( DDR_REG_BASE +0x53435*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53436*4+0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x53437*4+0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x53438*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x53439*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x5343a*4+0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x5343b*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5343c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5343d*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x5343e*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5343f*4+0x02000000,0xfa2); +reg_write( DDR_REG_BASE +0x53440*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x53441*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x53442*4+0x02000000,0xc502); +reg_write( DDR_REG_BASE +0x53443*4+0x02000000,0x7767); +reg_write( DDR_REG_BASE +0x53444*4+0x02000000,0x7077); +reg_write( DDR_REG_BASE +0x53445*4+0x02000000,0x664); +reg_write( DDR_REG_BASE +0x53446*4+0x02000000,0xffea); +reg_write( DDR_REG_BASE +0x53447*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x53448*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x53449*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5344a*4+0x02000000,0x13); +reg_write( DDR_REG_BASE +0x5344b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5344c*4+0x02000000,0x7812); +reg_write( DDR_REG_BASE +0x5344d*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x5344e*4+0x02000000,0xd); +reg_write( DDR_REG_BASE +0x5344f*4+0x02000000,0x8b6); +reg_write( DDR_REG_BASE +0x53450*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53451*4+0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x53452*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53453*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53454*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x53455*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53456*4+0x02000000,0x16); +reg_write( DDR_REG_BASE +0x53457*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x53458*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53459*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5345a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5345b*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5345c*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x5345d*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x5345e*4+0x02000000,0xe040); +reg_write( DDR_REG_BASE +0x5345f*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x53460*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x53461*4+0x02000000,0x2049); +reg_write( DDR_REG_BASE +0x53462*4+0x02000000,0x7c1); +reg_write( DDR_REG_BASE +0x53463*4+0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x53464*4+0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x53465*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x53466*4+0x02000000,0x10fd); +reg_write( DDR_REG_BASE +0x53467*4+0x02000000,0x809e); +reg_write( DDR_REG_BASE +0x53468*4+0x02000000,0xe37); +reg_write( DDR_REG_BASE +0x53469*4+0x02000000,0x315f); +reg_write( DDR_REG_BASE +0x5346a*4+0x02000000,0x8e65); +reg_write( DDR_REG_BASE +0x5346b*4+0x02000000,0x8e44); +reg_write( DDR_REG_BASE +0x5346c*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x5346d*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x5346e*4+0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x5346f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53470*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x53471*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53472*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x53473*4+0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x53474*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53475*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53476*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53477*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x53478*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x53479*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x5347a*4+0x02000000,0xbe7); +reg_write( DDR_REG_BASE +0x5347b*4+0x02000000,0x8085); +reg_write( DDR_REG_BASE +0x5347c*4+0x02000000,0x962); +reg_write( DDR_REG_BASE +0x5347d*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x5347e*4+0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x5347f*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x53480*4+0x02000000,0x10fd); +reg_write( DDR_REG_BASE +0x53481*4+0x02000000,0x809e); +reg_write( DDR_REG_BASE +0x53482*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x53483*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x53484*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x53485*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x53486*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53487*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x53488*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53489*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x5348a*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5348b*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5348c*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5348d*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x5348e*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x5348f*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x53490*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x53491*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x53492*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x53493*4+0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x53494*4+0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x53495*4+0x02000000,0x7110); +reg_write( DDR_REG_BASE +0x53496*4+0x02000000,0x5a4); +reg_write( DDR_REG_BASE +0x53497*4+0x02000000,0xffce); +reg_write( DDR_REG_BASE +0x53498*4+0x02000000,0xe15); +reg_write( DDR_REG_BASE +0x53499*4+0x02000000,0x315e); +reg_write( DDR_REG_BASE +0x5349a*4+0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x5349b*4+0x02000000,0xae05); +reg_write( DDR_REG_BASE +0x5349c*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x5349d*4+0x02000000,0xae04); +reg_write( DDR_REG_BASE +0x5349e*4+0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x5349f*4+0x02000000,0xae03); +reg_write( DDR_REG_BASE +0x534a0*4+0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x534a1*4+0x02000000,0xae02); +reg_write( DDR_REG_BASE +0x534a2*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x534a3*4+0x02000000,0x1fa7); +reg_write( DDR_REG_BASE +0x534a4*4+0x02000000,0x101c); +reg_write( DDR_REG_BASE +0x534a5*4+0x02000000,0x1fa8); +reg_write( DDR_REG_BASE +0x534a6*4+0x02000000,0x101c); +reg_write( DDR_REG_BASE +0x534a7*4+0x02000000,0xb700); +reg_write( DDR_REG_BASE +0x534a8*4+0x02000000,0xc0b1); +reg_write( DDR_REG_BASE +0x534a9*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x534aa*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x534ab*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x534ac*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x534ad*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x534ae*4+0x02000000,0xf209); +reg_write( DDR_REG_BASE +0x534af*4+0x02000000,0x821); +reg_write( DDR_REG_BASE +0x534b0*4+0x02000000,0x1d1); +reg_write( DDR_REG_BASE +0x534b1*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x534b2*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x534b3*4+0x02000000,0x238); +reg_write( DDR_REG_BASE +0x534b4*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x534b5*4+0x02000000,0x45); +reg_write( DDR_REG_BASE +0x534b6*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x534b7*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x534b8*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x534b9*4+0x02000000,0x238); +reg_write( DDR_REG_BASE +0x534ba*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x534bb*4+0x02000000,0x105); +reg_write( DDR_REG_BASE +0x534bc*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x534bd*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x534be*4+0x02000000,0x1209); +reg_write( DDR_REG_BASE +0x534bf*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x534c0*4+0x02000000,0xe903); +reg_write( DDR_REG_BASE +0x534c1*4+0x02000000,0x19); +reg_write( DDR_REG_BASE +0x534c2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534c3*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x534c4*4+0x02000000,0x9018); +reg_write( DDR_REG_BASE +0x534c5*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x534c6*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x534c7*4+0x02000000,0x55); +reg_write( DDR_REG_BASE +0x534c8*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x534c9*4+0x02000000,0x1902); +reg_write( DDR_REG_BASE +0x534ca*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x534cb*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x534cc*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x534cd*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x534ce*4+0x02000000,0xca09); +reg_write( DDR_REG_BASE +0x534cf*4+0x02000000,0xe812); +reg_write( DDR_REG_BASE +0x534d0*4+0x02000000,0xcc22); +reg_write( DDR_REG_BASE +0x534d1*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x534d2*4+0x02000000,0x8010); +reg_write( DDR_REG_BASE +0x534d3*4+0x02000000,0xf785); +reg_write( DDR_REG_BASE +0x534d4*4+0x02000000,0xfc2); +reg_write( DDR_REG_BASE +0x534d5*4+0x02000000,0xfd0f); +reg_write( DDR_REG_BASE +0x534d6*4+0x02000000,0xcc22); +reg_write( DDR_REG_BASE +0x534d7*4+0x02000000,0x2615); +reg_write( DDR_REG_BASE +0x534d8*4+0x02000000,0x7001); +reg_write( DDR_REG_BASE +0x534d9*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x534da*4+0x02000000,0x8e8); +reg_write( DDR_REG_BASE +0x534db*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x534dc*4+0x02000000,0xa1a0); +reg_write( DDR_REG_BASE +0x534dd*4+0x02000000,0x1a22); +reg_write( DDR_REG_BASE +0x534de*4+0x02000000,0x301c); +reg_write( DDR_REG_BASE +0x534df*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x534e0*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x534e1*4+0x02000000,0x9018); +reg_write( DDR_REG_BASE +0x534e2*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x534e3*4+0x02000000,0xb1a0); +reg_write( DDR_REG_BASE +0x534e4*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x534e5*4+0x02000000,0xdd10); +reg_write( DDR_REG_BASE +0x534e6*4+0x02000000,0xbd61); +reg_write( DDR_REG_BASE +0x534e7*4+0x02000000,0xd01); +reg_write( DDR_REG_BASE +0x534e8*4+0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x534e9*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x534ea*4+0x02000000,0xb102); +reg_write( DDR_REG_BASE +0x534eb*4+0x02000000,0x80e); +reg_write( DDR_REG_BASE +0x534ec*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x534ed*4+0x02000000,0x1902); +reg_write( DDR_REG_BASE +0x534ee*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x534ef*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x534f0*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x534f1*4+0x02000000,0x9018); +reg_write( DDR_REG_BASE +0x534f2*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x534f3*4+0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x534f4*4+0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x534f5*4+0x02000000,0x801f); +reg_write( DDR_REG_BASE +0x534f6*4+0x02000000,0x195e); +reg_write( DDR_REG_BASE +0x534f7*4+0x02000000,0x45); +reg_write( DDR_REG_BASE +0x534f8*4+0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x534f9*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x534fa*4+0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x534fb*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x534fc*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x534fd*4+0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x534fe*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x534ff*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53500*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53501*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53502*4+0x02000000,0x83b); +reg_write( DDR_REG_BASE +0x53503*4+0x02000000,0x13f); +reg_write( DDR_REG_BASE +0x53504*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x53505*4+0x02000000,0xca09); +reg_write( DDR_REG_BASE +0x53506*4+0x02000000,0x7ef0); +reg_write( DDR_REG_BASE +0x53507*4+0x02000000,0xe80a); +reg_write( DDR_REG_BASE +0x53508*4+0x02000000,0xcc22); +reg_write( DDR_REG_BASE +0x53509*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x5350a*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5350b*4+0x02000000,0x7902); +reg_write( DDR_REG_BASE +0x5350c*4+0x02000000,0x6e02); +reg_write( DDR_REG_BASE +0x5350d*4+0x02000000,0x7030); +reg_write( DDR_REG_BASE +0x5350e*4+0x02000000,0xf4c); +reg_write( DDR_REG_BASE +0x5350f*4+0x02000000,0xfd0a); +reg_write( DDR_REG_BASE +0x53510*4+0x02000000,0xf3a); +reg_write( DDR_REG_BASE +0x53511*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x53512*4+0x02000000,0xd808); +reg_write( DDR_REG_BASE +0x53513*4+0x02000000,0xf76); +reg_write( DDR_REG_BASE +0x53514*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x53515*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x53516*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x53517*4+0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x53518*4+0x02000000,0xf6a); +reg_write( DDR_REG_BASE +0x53519*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5351a*4+0x02000000,0x1504); +reg_write( DDR_REG_BASE +0x5351b*4+0x02000000,0x1400); +reg_write( DDR_REG_BASE +0x5351c*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x5351d*4+0x02000000,0xff9); +reg_write( DDR_REG_BASE +0x5351e*4+0x02000000,0x9384); +reg_write( DDR_REG_BASE +0x5351f*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53520*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x53521*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53522*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53523*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x53524*4+0x02000000,0x3109); +reg_write( DDR_REG_BASE +0x53525*4+0x02000000,0xc352); +reg_write( DDR_REG_BASE +0x53526*4+0x02000000,0xc245); +reg_write( DDR_REG_BASE +0x53527*4+0x02000000,0xc154); +reg_write( DDR_REG_BASE +0x53528*4+0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x53529*4+0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x5352a*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x5352b*4+0x02000000,0x88a0); +reg_write( DDR_REG_BASE +0x5352c*4+0x02000000,0x10fc); +reg_write( DDR_REG_BASE +0x5352d*4+0x02000000,0x808e); +reg_write( DDR_REG_BASE +0x5352e*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5352f*4+0x02000000,0x710f); +reg_write( DDR_REG_BASE +0x53530*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x53531*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x53532*4+0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x53533*4+0x02000000,0xc06); +reg_write( DDR_REG_BASE +0x53534*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53535*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53536*4+0x02000000,0xc050); +reg_write( DDR_REG_BASE +0x53537*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53538*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53539*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x5353a*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x5353b*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x5353c*4+0x02000000,0xf46); +reg_write( DDR_REG_BASE +0x5353d*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x5353e*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x5353f*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53540*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53541*4+0x02000000,0xff7f); +reg_write( DDR_REG_BASE +0x53542*4+0x02000000,0x78e4); +reg_write( DDR_REG_BASE +0x53543*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53544*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x53545*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x53546*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x53547*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x53548*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x53549*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5354a*4+0x02000000,0x1e4); +reg_write( DDR_REG_BASE +0x5354b*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5354c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5354d*4+0x02000000,0x44d); +reg_write( DDR_REG_BASE +0x5354e*4+0x02000000,0xde6); +reg_write( DDR_REG_BASE +0x5354f*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53550*4+0x02000000,0xda60); +reg_write( DDR_REG_BASE +0x53551*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x53552*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x53553*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53554*4+0x02000000,0x1e4); +reg_write( DDR_REG_BASE +0x53555*4+0x02000000,0xae2); +reg_write( DDR_REG_BASE +0x53556*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x53557*4+0x02000000,0xd960); +reg_write( DDR_REG_BASE +0x53558*4+0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x53559*4+0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x5355a*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x5355b*4+0x02000000,0x37cf); +reg_write( DDR_REG_BASE +0x5355c*4+0x02000000,0xef05); +reg_write( DDR_REG_BASE +0x5355d*4+0x02000000,0xbf61); +reg_write( DDR_REG_BASE +0x5355e*4+0x02000000,0xfff); +reg_write( DDR_REG_BASE +0x5355f*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x53560*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53561*4+0x02000000,0x7edd); +reg_write( DDR_REG_BASE +0x53562*4+0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x53563*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x53564*4+0x02000000,0x7edd); +reg_write( DDR_REG_BASE +0x53565*4+0x02000000,0x7edd); +reg_write( DDR_REG_BASE +0x53566*4+0x02000000,0x7edd); +reg_write( DDR_REG_BASE +0x53567*4+0x02000000,0x200f); +reg_write( DDR_REG_BASE +0x53568*4+0x02000000,0x6c2); +reg_write( DDR_REG_BASE +0x53569*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5356a*4+0x02000000,0x7edd); +reg_write( DDR_REG_BASE +0x5356b*4+0x02000000,0x7edd); +reg_write( DDR_REG_BASE +0x5356c*4+0x02000000,0xe807); +reg_write( DDR_REG_BASE +0x5356d*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5356e*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5356f*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x53570*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53571*4+0x02000000,0xf0c4); +reg_write( DDR_REG_BASE +0x53572*4+0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x53573*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53574*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x53575*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x53576*4+0x02000000,0x7c1); +reg_write( DDR_REG_BASE +0x53577*4+0x02000000,0xe906); +reg_write( DDR_REG_BASE +0x53578*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x53579*4+0x02000000,0x901); +reg_write( DDR_REG_BASE +0x5357a*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x5357b*4+0x02000000,0x7c9b); +reg_write( DDR_REG_BASE +0x5357c*4+0x02000000,0x6821); +reg_write( DDR_REG_BASE +0x5357d*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x5357e*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x5357f*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53580*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53581*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53582*4+0x02000000,0xe0c4); +reg_write( DDR_REG_BASE +0x53583*4+0x02000000,0xb080); +reg_write( DDR_REG_BASE +0x53584*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x53585*4+0x02000000,0x8e3); +reg_write( DDR_REG_BASE +0x53586*4+0x02000000,0x8234); +reg_write( DDR_REG_BASE +0x53587*4+0x02000000,0x4468); +reg_write( DDR_REG_BASE +0x53588*4+0x02000000,0x1498); +reg_write( DDR_REG_BASE +0x53589*4+0x02000000,0x3600); +reg_write( DDR_REG_BASE +0x5358a*4+0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x5358b*4+0x02000000,0x1f8d); +reg_write( DDR_REG_BASE +0x5358c*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5358d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5358e*4+0x02000000,0x7bc6); +reg_write( DDR_REG_BASE +0x5358f*4+0x02000000,0xc04d); +reg_write( DDR_REG_BASE +0x53590*4+0x02000000,0x1497); +reg_write( DDR_REG_BASE +0x53591*4+0x02000000,0x3600); +reg_write( DDR_REG_BASE +0x53592*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53593*4+0x02000000,0xc34c); +reg_write( DDR_REG_BASE +0x53594*4+0x02000000,0xc04e); +reg_write( DDR_REG_BASE +0x53595*4+0x02000000,0x1496); +reg_write( DDR_REG_BASE +0x53596*4+0x02000000,0x3600); +reg_write( DDR_REG_BASE +0x53597*4+0x02000000,0xc551); +reg_write( DDR_REG_BASE +0x53598*4+0x02000000,0xc04f); +reg_write( DDR_REG_BASE +0x53599*4+0x02000000,0x784f); +reg_write( DDR_REG_BASE +0x5359a*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5359b*4+0x02000000,0x926); +reg_write( DDR_REG_BASE +0x5359c*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5359d*4+0x02000000,0xc053); +reg_write( DDR_REG_BASE +0x5359e*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5359f*4+0x02000000,0xc14a); +reg_write( DDR_REG_BASE +0x535a0*4+0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x535a1*4+0x02000000,0x7a3b); +reg_write( DDR_REG_BASE +0x535a2*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x535a3*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x535a4*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x535a5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535a6*4+0x02000000,0x1c4); +reg_write( DDR_REG_BASE +0x535a7*4+0x02000000,0x22ce); +reg_write( DDR_REG_BASE +0x535a8*4+0x02000000,0x21); +reg_write( DDR_REG_BASE +0x535a9*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x535aa*4+0x02000000,0xa840); +reg_write( DDR_REG_BASE +0x535ab*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x535ac*4+0x02000000,0x9eb); +reg_write( DDR_REG_BASE +0x535ad*4+0x02000000,0x8434); +reg_write( DDR_REG_BASE +0x535ae*4+0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x535af*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x535b0*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x535b1*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x535b2*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x535b3*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x535b4*4+0x02000000,0x709e); +reg_write( DDR_REG_BASE +0x535b5*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x535b6*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x535b7*4+0x02000000,0x8881); +reg_write( DDR_REG_BASE +0x535b8*4+0x02000000,0x250a); +reg_write( DDR_REG_BASE +0x535b9*4+0x02000000,0x1780); +reg_write( DDR_REG_BASE +0x535ba*4+0x02000000,0xf047); +reg_write( DDR_REG_BASE +0x535bb*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x535bc*4+0x02000000,0xf042); +reg_write( DDR_REG_BASE +0x535bd*4+0x02000000,0xc010); +reg_write( DDR_REG_BASE +0x535be*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x535bf*4+0x02000000,0xc01); +reg_write( DDR_REG_BASE +0x535c0*4+0x02000000,0xc011); +reg_write( DDR_REG_BASE +0x535c1*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x535c2*4+0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x535c3*4+0x02000000,0x1f81); +reg_write( DDR_REG_BASE +0x535c4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535c5*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x535c6*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x535c7*4+0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x535c8*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x535c9*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x535ca*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x535cb*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x535cc*4+0x02000000,0xb891); +reg_write( DDR_REG_BASE +0x535cd*4+0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x535ce*4+0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x535cf*4+0x02000000,0x90e0); +reg_write( DDR_REG_BASE +0x535d0*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x535d1*4+0x02000000,0x2378); +reg_write( DDR_REG_BASE +0x535d2*4+0x02000000,0x201); +reg_write( DDR_REG_BASE +0x535d3*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x535d4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535d5*4+0x02000000,0x2007); +reg_write( DDR_REG_BASE +0x535d6*4+0x02000000,0x807e); +reg_write( DDR_REG_BASE +0x535d7*4+0x02000000,0xf427); +reg_write( DDR_REG_BASE +0x535d8*4+0x02000000,0x78fd); +reg_write( DDR_REG_BASE +0x535d9*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x535da*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x535db*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x535dc*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x535dd*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x535de*4+0x02000000,0xbfc4); +reg_write( DDR_REG_BASE +0x535df*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x535e0*4+0x02000000,0xe807); +reg_write( DDR_REG_BASE +0x535e1*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x535e2*4+0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x535e3*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x535e4*4+0x02000000,0x2180); +reg_write( DDR_REG_BASE +0x535e5*4+0x02000000,0x30); +reg_write( DDR_REG_BASE +0x535e6*4+0x02000000,0x79e5); +reg_write( DDR_REG_BASE +0x535e7*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x535e8*4+0x02000000,0x148b); +reg_write( DDR_REG_BASE +0x535e9*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x535ea*4+0x02000000,0x3882); +reg_write( DDR_REG_BASE +0x535eb*4+0x02000000,0x7261); +reg_write( DDR_REG_BASE +0x535ec*4+0x02000000,0x7a74); +reg_write( DDR_REG_BASE +0x535ed*4+0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x535ee*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x535ef*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535f0*4+0x02000000,0x141f); +reg_write( DDR_REG_BASE +0x535f1*4+0x02000000,0x813); +reg_write( DDR_REG_BASE +0x535f2*4+0x02000000,0x150); +reg_write( DDR_REG_BASE +0x535f3*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x535f4*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x535f5*4+0x02000000,0x2080); +reg_write( DDR_REG_BASE +0x535f6*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x535f7*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x535f8*4+0x02000000,0x3c1); +reg_write( DDR_REG_BASE +0x535f9*4+0x02000000,0xc097); +reg_write( DDR_REG_BASE +0x535fa*4+0x02000000,0x7061); +reg_write( DDR_REG_BASE +0x535fb*4+0x02000000,0x7874); +reg_write( DDR_REG_BASE +0x535fc*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x535fd*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x535fe*4+0x02000000,0xb7f); +reg_write( DDR_REG_BASE +0x535ff*4+0x02000000,0x8254); +reg_write( DDR_REG_BASE +0x53600*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x53601*4+0x02000000,0x7eaf); +reg_write( DDR_REG_BASE +0x53602*4+0x02000000,0xc73); +reg_write( DDR_REG_BASE +0x53603*4+0x02000000,0x93a5); +reg_write( DDR_REG_BASE +0x53604*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x53605*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53606*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53607*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x53608*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x53609*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5360a*4+0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x5360b*4+0x02000000,0x703c); +reg_write( DDR_REG_BASE +0x5360c*4+0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x5360d*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x5360e*4+0x02000000,0x3240); +reg_write( DDR_REG_BASE +0x5360f*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53610*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53611*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x53612*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53613*4+0x02000000,0xc055); +reg_write( DDR_REG_BASE +0x53614*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x53615*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x53616*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x53617*4+0x02000000,0xf0df); +reg_write( DDR_REG_BASE +0x53618*4+0x02000000,0xc109); +reg_write( DDR_REG_BASE +0x53619*4+0x02000000,0x8d2); +reg_write( DDR_REG_BASE +0x5361a*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5361b*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x5361c*4+0x02000000,0x3880); +reg_write( DDR_REG_BASE +0x5361d*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x5361e*4+0x02000000,0x9e2); +reg_write( DDR_REG_BASE +0x5361f*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53620*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x53621*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x53622*4+0x02000000,0xb5a); +reg_write( DDR_REG_BASE +0x53623*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x53624*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x53625*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x53626*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53627*4+0x02000000,0xe024); +reg_write( DDR_REG_BASE +0x53628*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x53629*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5362a*4+0x02000000,0x1f84); +reg_write( DDR_REG_BASE +0x5362b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5362c*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x5362d*4+0x02000000,0xb606); +reg_write( DDR_REG_BASE +0x5362e*4+0x02000000,0x1efe); +reg_write( DDR_REG_BASE +0x5362f*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x53630*4+0x02000000,0x1ea8); +reg_write( DDR_REG_BASE +0x53631*4+0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x53632*4+0x02000000,0x1ea9); +reg_write( DDR_REG_BASE +0x53633*4+0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x53634*4+0x02000000,0xc014); +reg_write( DDR_REG_BASE +0x53635*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53636*4+0x02000000,0xe020); +reg_write( DDR_REG_BASE +0x53637*4+0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x53638*4+0x02000000,0xe26); +reg_write( DDR_REG_BASE +0x53639*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x5363a*4+0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x5363b*4+0x02000000,0xc015); +reg_write( DDR_REG_BASE +0x5363c*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5363d*4+0x02000000,0x68e1); +reg_write( DDR_REG_BASE +0x5363e*4+0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x5363f*4+0x02000000,0xcc6); +reg_write( DDR_REG_BASE +0x53640*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x53641*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x53642*4+0x02000000,0xc109); +reg_write( DDR_REG_BASE +0x53643*4+0x02000000,0x87e); +reg_write( DDR_REG_BASE +0x53644*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x53645*4+0x02000000,0xc097); +reg_write( DDR_REG_BASE +0x53646*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53647*4+0x02000000,0x992); +reg_write( DDR_REG_BASE +0x53648*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53649*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x5364a*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x5364b*4+0x02000000,0xb0a); +reg_write( DDR_REG_BASE +0x5364c*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x5364d*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x5364e*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5364f*4+0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x53650*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53651*4+0x02000000,0x1f84); +reg_write( DDR_REG_BASE +0x53652*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53653*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x53654*4+0x02000000,0xb626); +reg_write( DDR_REG_BASE +0x53655*4+0x02000000,0x1efe); +reg_write( DDR_REG_BASE +0x53656*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x53657*4+0x02000000,0x1ea8); +reg_write( DDR_REG_BASE +0x53658*4+0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x53659*4+0x02000000,0xde6); +reg_write( DDR_REG_BASE +0x5365a*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x5365b*4+0x02000000,0x1ea9); +reg_write( DDR_REG_BASE +0x5365c*4+0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x5365d*4+0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x5365e*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5365f*4+0x02000000,0xc86); +reg_write( DDR_REG_BASE +0x53660*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x53661*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x53662*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x53663*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x53664*4+0x02000000,0xc056); +reg_write( DDR_REG_BASE +0x53665*4+0x02000000,0xe08f); +reg_write( DDR_REG_BASE +0x53666*4+0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x53667*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x53668*4+0x02000000,0x61); +reg_write( DDR_REG_BASE +0x53669*4+0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x5366a*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5366b*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5366c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5366d*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x5366e*4+0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x5366f*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53670*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x53671*4+0x02000000,0xf075); +reg_write( DDR_REG_BASE +0x53672*4+0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x53673*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x53674*4+0x02000000,0xc607); +reg_write( DDR_REG_BASE +0x53675*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x53676*4+0x02000000,0xc146); +reg_write( DDR_REG_BASE +0x53677*4+0x02000000,0x722c); +reg_write( DDR_REG_BASE +0x53678*4+0x02000000,0xf068); +reg_write( DDR_REG_BASE +0x53679*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x5367a*4+0x02000000,0xe17); +reg_write( DDR_REG_BASE +0x5367b*4+0x02000000,0x1231); +reg_write( DDR_REG_BASE +0x5367c*4+0x02000000,0x7a10); +reg_write( DDR_REG_BASE +0x5367d*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5367e*4+0x02000000,0xe887); +reg_write( DDR_REG_BASE +0x5367f*4+0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x53680*4+0x02000000,0x7854); +reg_write( DDR_REG_BASE +0x53681*4+0x02000000,0x10f0); +reg_write( DDR_REG_BASE +0x53682*4+0x02000000,0x8102); +reg_write( DDR_REG_BASE +0x53683*4+0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x53684*4+0x02000000,0xf058); +reg_write( DDR_REG_BASE +0x53685*4+0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x53686*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x53687*4+0x02000000,0x83); +reg_write( DDR_REG_BASE +0x53688*4+0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x53689*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x5368a*4+0x02000000,0x8c); +reg_write( DDR_REG_BASE +0x5368b*4+0x02000000,0x4c70); +reg_write( DDR_REG_BASE +0x5368c*4+0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x5368d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5368e*4+0x02000000,0x7f0e); +reg_write( DDR_REG_BASE +0x5368f*4+0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x53690*4+0x02000000,0x11b3); +reg_write( DDR_REG_BASE +0x53691*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x53692*4+0x02000000,0x203c); +reg_write( DDR_REG_BASE +0x53693*4+0x02000000,0x39b); +reg_write( DDR_REG_BASE +0x53694*4+0x02000000,0x991); +reg_write( DDR_REG_BASE +0x53695*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x53696*4+0x02000000,0x43c1); +reg_write( DDR_REG_BASE +0x53697*4+0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x53698*4+0x02000000,0xc208); +reg_write( DDR_REG_BASE +0x53699*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5369a*4+0x02000000,0x14); +reg_write( DDR_REG_BASE +0x5369b*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x5369c*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x5369d*4+0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x5369e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5369f*4+0x02000000,0xc16); +reg_write( DDR_REG_BASE +0x536a0*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x536a1*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x536a2*4+0x02000000,0xc010); +reg_write( DDR_REG_BASE +0x536a3*4+0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x536a4*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x536a5*4+0x02000000,0x8c1); +reg_write( DDR_REG_BASE +0x536a6*4+0x02000000,0xc011); +reg_write( DDR_REG_BASE +0x536a7*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x536a8*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x536a9*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x536aa*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x536ab*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ac*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x536ad*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x536ae*4+0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x536af*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x536b0*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x536b1*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x536b2*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x536b3*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x536b4*4+0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x536b5*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x536b6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536b7*4+0x02000000,0x9540); +reg_write( DDR_REG_BASE +0x536b8*4+0x02000000,0xc016); +reg_write( DDR_REG_BASE +0x536b9*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x536ba*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x536bb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536bc*4+0x02000000,0x1c4); +reg_write( DDR_REG_BASE +0x536bd*4+0x02000000,0x2133); +reg_write( DDR_REG_BASE +0x536be*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x536bf*4+0x02000000,0xc240); +reg_write( DDR_REG_BASE +0x536c0*4+0x02000000,0x6158); +reg_write( DDR_REG_BASE +0x536c1*4+0x02000000,0x780e); +reg_write( DDR_REG_BASE +0x536c2*4+0x02000000,0xc208); +reg_write( DDR_REG_BASE +0x536c3*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x536c4*4+0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x536c5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536c6*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x536c7*4+0x02000000,0x2049); +reg_write( DDR_REG_BASE +0x536c8*4+0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x536c9*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x536ca*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x536cb*4+0x02000000,0x15); +reg_write( DDR_REG_BASE +0x536cc*4+0x02000000,0x6); +reg_write( DDR_REG_BASE +0x536cd*4+0x02000000,0x926); +reg_write( DDR_REG_BASE +0x536ce*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x536cf*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x536d0*4+0x02000000,0xb5e0); +reg_write( DDR_REG_BASE +0x536d1*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x536d2*4+0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x536d3*4+0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x536d4*4+0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x536d5*4+0x02000000,0x2014); +reg_write( DDR_REG_BASE +0x536d6*4+0x02000000,0x82); +reg_write( DDR_REG_BASE +0x536d7*4+0x02000000,0x6478); +reg_write( DDR_REG_BASE +0x536d8*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x536d9*4+0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x536da*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536db*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x536dc*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x536dd*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x536de*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x536df*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x536e0*4+0x02000000,0xe33); +reg_write( DDR_REG_BASE +0x536e1*4+0x02000000,0x9254); +reg_write( DDR_REG_BASE +0x536e2*4+0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x536e3*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x536e4*4+0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x536e5*4+0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x536e6*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x536e7*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x536e8*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x536e9*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x536ea*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x536eb*4+0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x536ec*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x536ed*4+0x02000000,0x90d); +reg_write( DDR_REG_BASE +0x536ee*4+0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x536ef*4+0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x536f0*4+0x02000000,0xbe0); +reg_write( DDR_REG_BASE +0x536f1*4+0x02000000,0xfe82); +reg_write( DDR_REG_BASE +0x536f2*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x536f3*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x536f4*4+0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x536f5*4+0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x536f6*4+0x02000000,0xf522); +reg_write( DDR_REG_BASE +0x536f7*4+0x02000000,0xc012); +reg_write( DDR_REG_BASE +0x536f8*4+0x02000000,0x881); +reg_write( DDR_REG_BASE +0x536f9*4+0x02000000,0x30); +reg_write( DDR_REG_BASE +0x536fa*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x536fb*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x536fc*4+0x02000000,0x16); +reg_write( DDR_REG_BASE +0x536fd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536fe*4+0x02000000,0x8c2); +reg_write( DDR_REG_BASE +0x536ff*4+0x02000000,0xfd0f); +reg_write( DDR_REG_BASE +0x53700*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53701*4+0x02000000,0x708e); +reg_write( DDR_REG_BASE +0x53702*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53703*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53704*4+0x02000000,0xf02d); +reg_write( DDR_REG_BASE +0x53705*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53706*4+0x02000000,0xc707); +reg_write( DDR_REG_BASE +0x53707*4+0x02000000,0x7910); +reg_write( DDR_REG_BASE +0x53708*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x53709*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x5370a*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5370b*4+0x02000000,0xf024); +reg_write( DDR_REG_BASE +0x5370c*4+0x02000000,0xf09); +reg_write( DDR_REG_BASE +0x5370d*4+0x02000000,0x1211); +reg_write( DDR_REG_BASE +0x5370e*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5370f*4+0x02000000,0xe81c); +reg_write( DDR_REG_BASE +0x53710*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53711*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53712*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x53713*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x53714*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53715*4+0x02000000,0xfffe); +reg_write( DDR_REG_BASE +0x53716*4+0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x53717*4+0x02000000,0x2035); +reg_write( DDR_REG_BASE +0x53718*4+0x02000000,0x43); +reg_write( DDR_REG_BASE +0x53719*4+0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x5371a*4+0x02000000,0x2035); +reg_write( DDR_REG_BASE +0x5371b*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x5371c*4+0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x5371d*4+0x02000000,0x2035); +reg_write( DDR_REG_BASE +0x5371e*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x5371f*4+0x02000000,0xc241); +reg_write( DDR_REG_BASE +0x53720*4+0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x53721*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53722*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x53723*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53724*4+0x02000000,0x17); +reg_write( DDR_REG_BASE +0x53725*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x53726*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x53727*4+0x02000000,0x872); +reg_write( DDR_REG_BASE +0x53728*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53729*4+0x02000000,0x43e1); +reg_write( DDR_REG_BASE +0x5372a*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5372b*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x5372c*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5372d*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5372e*4+0x02000000,0xfbd); +reg_write( DDR_REG_BASE +0x5372f*4+0x02000000,0x9254); +reg_write( DDR_REG_BASE +0x53730*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x53731*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53732*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53733*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53734*4+0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x53735*4+0x02000000,0x7dcf); +reg_write( DDR_REG_BASE +0x53736*4+0x02000000,0x89f); +reg_write( DDR_REG_BASE +0x53737*4+0x02000000,0x8345); +reg_write( DDR_REG_BASE +0x53738*4+0x02000000,0x98a); +reg_write( DDR_REG_BASE +0x53739*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x5373a*4+0x02000000,0xc013); +reg_write( DDR_REG_BASE +0x5373b*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5373c*4+0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x5373d*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5373e*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x5373f*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x53740*4+0x02000000,0x3109); +reg_write( DDR_REG_BASE +0x53741*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x53742*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x53743*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53744*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x53745*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53746*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53747*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x53748*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x53749*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x5374a*4+0x02000000,0x641); +reg_write( DDR_REG_BASE +0x5374b*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5374c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5374d*4+0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x5374e*4+0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x5374f*4+0x02000000,0x4358); +reg_write( DDR_REG_BASE +0x53750*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x53751*4+0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x53752*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x53753*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x53754*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53755*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53756*4+0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x53757*4+0x02000000,0x88e2); +reg_write( DDR_REG_BASE +0x53758*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53759*4+0x02000000,0xb4e); +reg_write( DDR_REG_BASE +0x5375a*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x5375b*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5375c*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5375d*4+0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x5375e*4+0x02000000,0x17ca); +reg_write( DDR_REG_BASE +0x5375f*4+0x02000000,0xa11); +reg_write( DDR_REG_BASE +0x53760*4+0x02000000,0x1010); +reg_write( DDR_REG_BASE +0x53761*4+0x02000000,0x2242); +reg_write( DDR_REG_BASE +0x53762*4+0x02000000,0x104a); +reg_write( DDR_REG_BASE +0x53763*4+0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x53764*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x53765*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53766*4+0x02000000,0x7077); +reg_write( DDR_REG_BASE +0x53767*4+0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x53768*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x53769*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5376a*4+0x02000000,0x27cf); +reg_write( DDR_REG_BASE +0x5376b*4+0x02000000,0x11e2); +reg_write( DDR_REG_BASE +0x5376c*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x5376d*4+0x02000000,0x200f); +reg_write( DDR_REG_BASE +0x5376e*4+0x02000000,0x340); +reg_write( DDR_REG_BASE +0x5376f*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x53770*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53771*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53772*4+0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x53773*4+0x02000000,0x4628); +reg_write( DDR_REG_BASE +0x53774*4+0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x53775*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x53776*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x53777*4+0x02000000,0xdfa); +reg_write( DDR_REG_BASE +0x53778*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53779*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x5377a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5377b*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x5377c*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5377d*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5377e*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x5377f*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x53780*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x53781*4+0x02000000,0xbd6); +reg_write( DDR_REG_BASE +0x53782*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53783*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x53784*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53785*4+0x02000000,0xb8e); +reg_write( DDR_REG_BASE +0x53786*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53787*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53788*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x53789*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x5378a*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x5378b*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5378c*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5378d*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5378e*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5378f*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x53790*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x53791*4+0x02000000,0x9d2); +reg_write( DDR_REG_BASE +0x53792*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x53793*4+0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x53794*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x53795*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53796*4+0x02000000,0xad2); +reg_write( DDR_REG_BASE +0x53797*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53798*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x53799*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x5379a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5379b*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5379c*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5379d*4+0x02000000,0xdb28); +reg_write( DDR_REG_BASE +0x5379e*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x5379f*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537a0*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x537a1*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x537a2*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537a3*4+0x02000000,0xb92); +reg_write( DDR_REG_BASE +0x537a4*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x537a5*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x537a6*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537a7*4+0x02000000,0xdd6); +reg_write( DDR_REG_BASE +0x537a8*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x537a9*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x537aa*4+0x02000000,0xe62e); +reg_write( DDR_REG_BASE +0x537ab*4+0x02000000,0xed18); +reg_write( DDR_REG_BASE +0x537ac*4+0x02000000,0xf836); +reg_write( DDR_REG_BASE +0x537ad*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x537ae*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537af*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x537b0*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x537b1*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537b2*4+0x02000000,0xb72); +reg_write( DDR_REG_BASE +0x537b3*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x537b4*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x537b5*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537b6*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x537b7*4+0x02000000,0xd90c); +reg_write( DDR_REG_BASE +0x537b8*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x537b9*4+0x02000000,0xdb0a); +reg_write( DDR_REG_BASE +0x537ba*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x537bb*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537bc*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x537bd*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x537be*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537bf*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x537c0*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537c1*4+0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x537c2*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x537c3*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x537c4*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x537c5*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x537c6*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537c7*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x537c8*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537c9*4+0x02000000,0xf828); +reg_write( DDR_REG_BASE +0x537ca*4+0x02000000,0xb42); +reg_write( DDR_REG_BASE +0x537cb*4+0x02000000,0xfccf); +reg_write( DDR_REG_BASE +0x537cc*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x537cd*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x537ce*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x537cf*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x537d0*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x537d1*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537d2*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x537d3*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x537d4*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537d5*4+0x02000000,0xb2e); +reg_write( DDR_REG_BASE +0x537d6*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x537d7*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x537d8*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537d9*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x537da*4+0x02000000,0x7bcf); +reg_write( DDR_REG_BASE +0x537db*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x537dc*4+0x02000000,0xd90c); +reg_write( DDR_REG_BASE +0x537dd*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x537de*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x537df*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x537e0*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x537e1*4+0x02000000,0xb16); +reg_write( DDR_REG_BASE +0x537e2*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x537e3*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x537e4*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x537e5*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x537e6*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x537e7*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x537e8*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x537e9*4+0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x537ea*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x537eb*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x537ec*4+0x02000000,0xafe); +reg_write( DDR_REG_BASE +0x537ed*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x537ee*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x537ef*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x537f0*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x537f1*4+0x02000000,0xb98f); +reg_write( DDR_REG_BASE +0x537f2*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x537f3*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x537f4*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x537f5*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x537f6*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x537f7*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x537f8*4+0x02000000,0xae6); +reg_write( DDR_REG_BASE +0x537f9*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x537fa*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x537fb*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x537fc*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x537fd*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x537fe*4+0x02000000,0xdb10); +reg_write( DDR_REG_BASE +0x537ff*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x53800*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x53801*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53802*4+0x02000000,0xad2); +reg_write( DDR_REG_BASE +0x53803*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53804*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53805*4+0x02000000,0xcfe); +reg_write( DDR_REG_BASE +0x53806*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53807*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53808*4+0x02000000,0xbfc1); +reg_write( DDR_REG_BASE +0x53809*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5380a*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x5380b*4+0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x5380c*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x5380d*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5380e*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5380f*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53810*4+0x02000000,0xab6); +reg_write( DDR_REG_BASE +0x53811*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53812*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x53813*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x53814*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x53815*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x53816*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x53817*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53818*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53819*4+0x02000000,0xd90c); +reg_write( DDR_REG_BASE +0x5381a*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x5381b*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x5381c*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5381d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5381e*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5381f*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53820*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53821*4+0x02000000,0xc1a8); +reg_write( DDR_REG_BASE +0x53822*4+0x02000000,0xc145); +reg_write( DDR_REG_BASE +0x53823*4+0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x53824*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53825*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x53826*4+0x02000000,0xc346); +reg_write( DDR_REG_BASE +0x53827*4+0x02000000,0x9b2); +reg_write( DDR_REG_BASE +0x53828*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53829*4+0x02000000,0xc244); +reg_write( DDR_REG_BASE +0x5382a*4+0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x5382b*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x5382c*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x5382d*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x5382e*4+0x02000000,0xf03a); +reg_write( DDR_REG_BASE +0x5382f*4+0x02000000,0x2532); +reg_write( DDR_REG_BASE +0x53830*4+0x02000000,0x1f8f); +reg_write( DDR_REG_BASE +0x53831*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53832*4+0x02000000,0x624); +reg_write( DDR_REG_BASE +0x53833*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53834*4+0x02000000,0x896); +reg_write( DDR_REG_BASE +0x53835*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53836*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x53837*4+0x02000000,0xc207); +reg_write( DDR_REG_BASE +0x53838*4+0x02000000,0x7944); +reg_write( DDR_REG_BASE +0x53839*4+0x02000000,0xc206); +reg_write( DDR_REG_BASE +0x5383a*4+0x02000000,0x7844); +reg_write( DDR_REG_BASE +0x5383b*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5383c*4+0x02000000,0x807e); +reg_write( DDR_REG_BASE +0x5383d*4+0x02000000,0xf42b); +reg_write( DDR_REG_BASE +0x5383e*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5383f*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53840*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x53841*4+0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x53842*4+0x02000000,0x60e8); +reg_write( DDR_REG_BASE +0x53843*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x53844*4+0x02000000,0x3001); +reg_write( DDR_REG_BASE +0x53845*4+0x02000000,0x1c08); +reg_write( DDR_REG_BASE +0x53846*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x53847*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x53848*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53849*4+0x02000000,0xc56); +reg_write( DDR_REG_BASE +0x5384a*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x5384b*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x5384c*4+0x02000000,0xd07); +reg_write( DDR_REG_BASE +0x5384d*4+0x02000000,0x1190); +reg_write( DDR_REG_BASE +0x5384e*4+0x02000000,0xed99); +reg_write( DDR_REG_BASE +0x5384f*4+0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x53850*4+0x02000000,0xd9c8); +reg_write( DDR_REG_BASE +0x53851*4+0x02000000,0xd8fa); +reg_write( DDR_REG_BASE +0x53852*4+0x02000000,0xa5e); +reg_write( DDR_REG_BASE +0x53853*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x53854*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x53855*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x53856*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x53857*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x53858*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x53859*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5385a*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5385b*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x5385c*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5385d*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5385e*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5385f*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x53860*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x53861*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53862*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53863*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53864*4+0x02000000,0xc1e); +reg_write( DDR_REG_BASE +0x53865*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53866*4+0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x53867*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x53868*4+0x02000000,0xd8f); +reg_write( DDR_REG_BASE +0x53869*4+0x02000000,0x9334); +reg_write( DDR_REG_BASE +0x5386a*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5386b*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5386c*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5386d*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5386e*4+0x02000000,0xdb41); +reg_write( DDR_REG_BASE +0x5386f*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x53870*4+0x02000000,0x3401); +reg_write( DDR_REG_BASE +0x53871*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x53872*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x53873*4+0x02000000,0x9f2); +reg_write( DDR_REG_BASE +0x53874*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53875*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x53876*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53877*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x53878*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53879*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x5387a*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x5387b*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x5387c*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x5387d*4+0x02000000,0x9de); +reg_write( DDR_REG_BASE +0x5387e*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x5387f*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x53880*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53881*4+0x02000000,0x996); +reg_write( DDR_REG_BASE +0x53882*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53883*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53884*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53885*4+0x02000000,0xe833); +reg_write( DDR_REG_BASE +0x53886*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53887*4+0x02000000,0x8f2); +reg_write( DDR_REG_BASE +0x53888*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53889*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x5388a*4+0x02000000,0xd84f); +reg_write( DDR_REG_BASE +0x5388b*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x5388c*4+0x02000000,0x2353); +reg_write( DDR_REG_BASE +0x5388d*4+0x02000000,0x305b); +reg_write( DDR_REG_BASE +0x5388e*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5388f*4+0x02000000,0xf817); +reg_write( DDR_REG_BASE +0x53890*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x53891*4+0x02000000,0x1c08); +reg_write( DDR_REG_BASE +0x53892*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x53893*4+0x02000000,0x9b2); +reg_write( DDR_REG_BASE +0x53894*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53895*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53896*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53897*4+0x02000000,0x96a); +reg_write( DDR_REG_BASE +0x53898*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53899*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5389a*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5389b*4+0x02000000,0xf); +reg_write( DDR_REG_BASE +0x5389c*4+0x02000000,0x4240); +reg_write( DDR_REG_BASE +0x5389d*4+0x02000000,0xfa6); +reg_write( DDR_REG_BASE +0x5389e*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5389f*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x538a0*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x538a1*4+0x02000000,0x8be); +reg_write( DDR_REG_BASE +0x538a2*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x538a3*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x538a4*4+0x02000000,0xd851); +reg_write( DDR_REG_BASE +0x538a5*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x538a6*4+0x02000000,0xf80b); +reg_write( DDR_REG_BASE +0x538a7*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x538a8*4+0x02000000,0x1c08); +reg_write( DDR_REG_BASE +0x538a9*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x538aa*4+0x02000000,0x982); +reg_write( DDR_REG_BASE +0x538ab*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x538ac*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x538ad*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x538ae*4+0x02000000,0x93a); +reg_write( DDR_REG_BASE +0x538af*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x538b0*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x538b1*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x538b2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538b3*4+0x02000000,0x1f40); +reg_write( DDR_REG_BASE +0x538b4*4+0x02000000,0xf76); +reg_write( DDR_REG_BASE +0x538b5*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x538b6*4+0x02000000,0xd91e); +reg_write( DDR_REG_BASE +0x538b7*4+0x02000000,0xc0a8); +reg_write( DDR_REG_BASE +0x538b8*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x538b9*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x538ba*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x538bb*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x538bc*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x538bd*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x538be*4+0x02000000,0xda17); +reg_write( DDR_REG_BASE +0x538bf*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x538c0*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x538c1*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x538c2*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x538c3*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x538c4*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x538c5*4+0x02000000,0xc1ac); +reg_write( DDR_REG_BASE +0x538c6*4+0x02000000,0xc349); +reg_write( DDR_REG_BASE +0x538c7*4+0x02000000,0xc247); +reg_write( DDR_REG_BASE +0x538c8*4+0x02000000,0xc14a); +reg_write( DDR_REG_BASE +0x538c9*4+0x02000000,0xc5e); +reg_write( DDR_REG_BASE +0x538ca*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x538cb*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x538cc*4+0x02000000,0xc011); +reg_write( DDR_REG_BASE +0x538cd*4+0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x538ce*4+0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x538cf*4+0x02000000,0xc012); +reg_write( DDR_REG_BASE +0x538d0*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x538d1*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x538d2*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x538d3*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x538d4*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x538d5*4+0x02000000,0xf0b8); +reg_write( DDR_REG_BASE +0x538d6*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x538d7*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x538d8*4+0x02000000,0xf9b); +reg_write( DDR_REG_BASE +0x538d9*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x538da*4+0x02000000,0x624); +reg_write( DDR_REG_BASE +0x538db*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x538dc*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x538dd*4+0x02000000,0x6ce); +reg_write( DDR_REG_BASE +0x538de*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x538df*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x538e0*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x538e1*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x538e2*4+0x02000000,0xf40b); +reg_write( DDR_REG_BASE +0x538e3*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x538e4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538e5*4+0x02000000,0xa00); +reg_write( DDR_REG_BASE +0x538e6*4+0x02000000,0x832); +reg_write( DDR_REG_BASE +0x538e7*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x538e8*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x538e9*4+0x02000000,0x852); +reg_write( DDR_REG_BASE +0x538ea*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x538eb*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x538ec*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x538ed*4+0x02000000,0x41e1); +reg_write( DDR_REG_BASE +0x538ee*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x538ef*4+0x02000000,0x37c0); +reg_write( DDR_REG_BASE +0x538f0*4+0x02000000,0xc209); +reg_write( DDR_REG_BASE +0x538f1*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x538f2*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x538f3*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x538f4*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x538f5*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x538f6*4+0x02000000,0xd81f); +reg_write( DDR_REG_BASE +0x538f7*4+0x02000000,0x7a24); +reg_write( DDR_REG_BASE +0x538f8*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x538f9*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x538fa*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x538fb*4+0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x538fc*4+0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x538fd*4+0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x538fe*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x538ff*4+0x02000000,0x803e); +reg_write( DDR_REG_BASE +0x53900*4+0x02000000,0xf479); +reg_write( DDR_REG_BASE +0x53901*4+0x02000000,0x78dd); +reg_write( DDR_REG_BASE +0x53902*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x53903*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x53904*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x53905*4+0x02000000,0x2045); +reg_write( DDR_REG_BASE +0x53906*4+0x02000000,0x18d); +reg_write( DDR_REG_BASE +0x53907*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x53908*4+0x02000000,0xe80b); +reg_write( DDR_REG_BASE +0x53909*4+0x02000000,0xf87e); +reg_write( DDR_REG_BASE +0x5390a*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5390b*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5390c*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5390d*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5390e*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5390f*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53910*4+0x02000000,0x8b6); +reg_write( DDR_REG_BASE +0x53911*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53912*4+0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x53913*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53914*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53915*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53916*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x53917*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53918*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53919*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5391a*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x5391b*4+0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x5391c*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5391d*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x5391e*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5391f*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53920*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53921*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53922*4+0x02000000,0x892); +reg_write( DDR_REG_BASE +0x53923*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53924*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53925*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53926*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53927*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x53928*4+0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x53929*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x5392a*4+0x02000000,0x2353); +reg_write( DDR_REG_BASE +0x5392b*4+0x02000000,0x315b); +reg_write( DDR_REG_BASE +0x5392c*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5392d*4+0x02000000,0xf869); +reg_write( DDR_REG_BASE +0x5392e*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5392f*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53930*4+0x02000000,0x876); +reg_write( DDR_REG_BASE +0x53931*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53932*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x53933*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x53934*4+0x02000000,0xf868); +reg_write( DDR_REG_BASE +0x53935*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x53936*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53937*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x53938*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53939*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5393a*4+0x02000000,0x78dd); +reg_write( DDR_REG_BASE +0x5393b*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x5393c*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x5393d*4+0x02000000,0x2045); +reg_write( DDR_REG_BASE +0x5393e*4+0x02000000,0x580); +reg_write( DDR_REG_BASE +0x5393f*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x53940*4+0x02000000,0x856); +reg_write( DDR_REG_BASE +0x53941*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53942*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53943*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53944*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53945*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x53946*4+0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x53947*4+0x02000000,0xbec5); +reg_write( DDR_REG_BASE +0x53948*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53949*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5394a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5394b*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5394c*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5394d*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5394e*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x5394f*4+0x02000000,0x83a); +reg_write( DDR_REG_BASE +0x53950*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53951*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x53952*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53953*4+0x02000000,0xe819); +reg_write( DDR_REG_BASE +0x53954*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53955*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53956*4+0x02000000,0x2710); +reg_write( DDR_REG_BASE +0x53957*4+0x02000000,0xe52); +reg_write( DDR_REG_BASE +0x53958*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x53959*4+0x02000000,0xd90a); +reg_write( DDR_REG_BASE +0x5395a*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5395b*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5395c*4+0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x5395d*4+0x02000000,0x7e0f); +reg_write( DDR_REG_BASE +0x5395e*4+0x02000000,0xf850); +reg_write( DDR_REG_BASE +0x5395f*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x53960*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53961*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53962*4+0x02000000,0x812); +reg_write( DDR_REG_BASE +0x53963*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53964*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x53965*4+0x02000000,0xf84d); +reg_write( DDR_REG_BASE +0x53966*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x53967*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x53968*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53969*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5396a*4+0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x5396b*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5396c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5396d*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x5396e*4+0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x5396f*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x53970*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53971*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x53972*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53973*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53974*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53975*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53976*4+0x02000000,0xdb18); +reg_write( DDR_REG_BASE +0x53977*4+0x02000000,0xfea); +reg_write( DDR_REG_BASE +0x53978*4+0x02000000,0xfc8f); +reg_write( DDR_REG_BASE +0x53979*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5397a*4+0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x5397b*4+0x02000000,0x90f); +reg_write( DDR_REG_BASE +0x5397c*4+0x02000000,0x110); +reg_write( DDR_REG_BASE +0x5397d*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5397e*4+0x02000000,0x817); +reg_write( DDR_REG_BASE +0x5397f*4+0x02000000,0x2d1); +reg_write( DDR_REG_BASE +0x53980*4+0x02000000,0xe909); +reg_write( DDR_REG_BASE +0x53981*4+0x02000000,0xeca); +reg_write( DDR_REG_BASE +0x53982*4+0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x53983*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53984*4+0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x53985*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53986*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53987*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53988*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53989*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5398a*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5398b*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x5398c*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5398d*4+0x02000000,0xe08c); +reg_write( DDR_REG_BASE +0x5398e*4+0x02000000,0x690); +reg_write( DDR_REG_BASE +0x5398f*4+0x02000000,0xffc5); +reg_write( DDR_REG_BASE +0x53990*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x53991*4+0x02000000,0x8cf); +reg_write( DDR_REG_BASE +0x53992*4+0x02000000,0x30); +reg_write( DDR_REG_BASE +0x53993*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x53994*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x53995*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53996*4+0x02000000,0xa00); +reg_write( DDR_REG_BASE +0x53997*4+0x02000000,0xed2); +reg_write( DDR_REG_BASE +0x53998*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53999*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x5399a*4+0x02000000,0xeee); +reg_write( DDR_REG_BASE +0x5399b*4+0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x5399c*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x5399d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5399e*4+0x02000000,0x6e1); +reg_write( DDR_REG_BASE +0x5399f*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x539a0*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x539a1*4+0x02000000,0x234a); +reg_write( DDR_REG_BASE +0x539a2*4+0x02000000,0x3800); +reg_write( DDR_REG_BASE +0x539a3*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x539a4*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x539a5*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x539a6*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x539a7*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x539a8*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x539a9*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x539aa*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x539ab*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x539ac*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x539ad*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x539ae*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x539af*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x539b0*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x539b1*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x539b2*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x539b3*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x539b4*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x539b5*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x539b6*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x539b7*4+0x02000000,0xf6a); +reg_write( DDR_REG_BASE +0x539b8*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x539b9*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x539ba*4+0x02000000,0x33c1); +reg_write( DDR_REG_BASE +0x539bb*4+0x02000000,0xe56); +reg_write( DDR_REG_BASE +0x539bc*4+0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x539bd*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x539be*4+0x02000000,0xf1a); +reg_write( DDR_REG_BASE +0x539bf*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x539c0*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x539c1*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x539c2*4+0x02000000,0xf); +reg_write( DDR_REG_BASE +0x539c3*4+0x02000000,0x4240); +reg_write( DDR_REG_BASE +0x539c4*4+0x02000000,0xd56); +reg_write( DDR_REG_BASE +0x539c5*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x539c6*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x539c7*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x539c8*4+0x02000000,0xe6e); +reg_write( DDR_REG_BASE +0x539c9*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x539ca*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x539cb*4+0x02000000,0xe8e); +reg_write( DDR_REG_BASE +0x539cc*4+0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x539cd*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x539ce*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x539cf*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x539d0*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x539d1*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x539d2*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x539d3*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x539d4*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x539d5*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x539d6*4+0x02000000,0xf2a); +reg_write( DDR_REG_BASE +0x539d7*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x539d8*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x539d9*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x539da*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x539db*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x539dc*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x539dd*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x539de*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x539df*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x539e0*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x539e1*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x539e2*4+0x02000000,0xf12); +reg_write( DDR_REG_BASE +0x539e3*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x539e4*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x539e5*4+0x02000000,0x3441); +reg_write( DDR_REG_BASE +0x539e6*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x539e7*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x539e8*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x539e9*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x539ea*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x539eb*4+0x02000000,0xdb10); +reg_write( DDR_REG_BASE +0x539ec*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x539ed*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x539ee*4+0x02000000,0xefa); +reg_write( DDR_REG_BASE +0x539ef*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x539f0*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x539f1*4+0x02000000,0xdea); +reg_write( DDR_REG_BASE +0x539f2*4+0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x539f3*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x539f4*4+0x02000000,0xeae); +reg_write( DDR_REG_BASE +0x539f5*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x539f6*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x539f7*4+0x02000000,0xc06); +reg_write( DDR_REG_BASE +0x539f8*4+0x02000000,0xfd0f); +reg_write( DDR_REG_BASE +0x539f9*4+0x02000000,0xc0ac); +reg_write( DDR_REG_BASE +0x539fa*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x539fb*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x539fc*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x539fd*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x539fe*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x539ff*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53a00*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53a01*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x53a02*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x53a03*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x53a04*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53a05*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53a06*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x53a07*4+0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x53a08*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53a09*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53a0a*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x53a0b*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x53a0c*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x53a0d*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53a0e*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53a0f*4+0x02000000,0xc1a9); +reg_write( DDR_REG_BASE +0x53a10*4+0x02000000,0xc145); +reg_write( DDR_REG_BASE +0x53a11*4+0x02000000,0xd958); +reg_write( DDR_REG_BASE +0x53a12*4+0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x53a13*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x53a14*4+0x02000000,0x8900); +reg_write( DDR_REG_BASE +0x53a15*4+0x02000000,0x11cd); +reg_write( DDR_REG_BASE +0x53a16*4+0x02000000,0x808f); +reg_write( DDR_REG_BASE +0x53a17*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x53a18*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x53a19*4+0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x53a1a*4+0x02000000,0x71cd); +reg_write( DDR_REG_BASE +0x53a1b*4+0x02000000,0xc343); +reg_write( DDR_REG_BASE +0x53a1c*4+0x02000000,0xc244); +reg_write( DDR_REG_BASE +0x53a1d*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x53a1e*4+0x02000000,0xf058); +reg_write( DDR_REG_BASE +0x53a1f*4+0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x53a20*4+0x02000000,0x17c1); +reg_write( DDR_REG_BASE +0x53a21*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x53a22*4+0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x53a23*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x53a24*4+0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x53a25*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x53a26*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53a27*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53a28*4+0x02000000,0xf04b); +reg_write( DDR_REG_BASE +0x53a29*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x53a2a*4+0x02000000,0xc202); +reg_write( DDR_REG_BASE +0x53a2b*4+0x02000000,0xc108); +reg_write( DDR_REG_BASE +0x53a2c*4+0x02000000,0x7077); +reg_write( DDR_REG_BASE +0x53a2d*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x53a2e*4+0x02000000,0x3c1); +reg_write( DDR_REG_BASE +0x53a2f*4+0x02000000,0x7944); +reg_write( DDR_REG_BASE +0x53a30*4+0x02000000,0x790b); +reg_write( DDR_REG_BASE +0x53a31*4+0x02000000,0xf242); +reg_write( DDR_REG_BASE +0x53a32*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x53a33*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x53a34*4+0x02000000,0x37c1); +reg_write( DDR_REG_BASE +0x53a35*4+0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x53a36*4+0x02000000,0x3007); +reg_write( DDR_REG_BASE +0x53a37*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53a38*4+0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x53a39*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x53a3a*4+0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x53a3b*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x53a3c*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53a3d*4+0x02000000,0xe9e); +reg_write( DDR_REG_BASE +0x53a3e*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53a3f*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x53a40*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53a41*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53a42*4+0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x53a43*4+0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x53a44*4+0x02000000,0xe81c); +reg_write( DDR_REG_BASE +0x53a45*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53a46*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53a47*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53a48*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53a49*4+0x02000000,0x831); +reg_write( DDR_REG_BASE +0x53a4a*4+0x02000000,0xdf); +reg_write( DDR_REG_BASE +0x53a4b*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x53a4c*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x53a4d*4+0x02000000,0x3c81); +reg_write( DDR_REG_BASE +0x53a4e*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x53a4f*4+0x02000000,0x3102); +reg_write( DDR_REG_BASE +0x53a50*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x53a51*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53a52*4+0x02000000,0xc304); +reg_write( DDR_REG_BASE +0x53a53*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x53a54*4+0x02000000,0x3001); +reg_write( DDR_REG_BASE +0x53a55*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x53a56*4+0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x53a57*4+0x02000000,0x1640); +reg_write( DDR_REG_BASE +0x53a58*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x53a59*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x53a5a*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x53a5b*4+0x02000000,0xc205); +reg_write( DDR_REG_BASE +0x53a5c*4+0x02000000,0xcce); +reg_write( DDR_REG_BASE +0x53a5d*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x53a5e*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x53a5f*4+0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x53a60*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x53a61*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x53a62*4+0x02000000,0x3c81); +reg_write( DDR_REG_BASE +0x53a63*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x53a64*4+0x02000000,0x3102); +reg_write( DDR_REG_BASE +0x53a65*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x53a66*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53a67*4+0x02000000,0xc304); +reg_write( DDR_REG_BASE +0x53a68*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x53a69*4+0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x53a6a*4+0x02000000,0x1640); +reg_write( DDR_REG_BASE +0x53a6b*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x53a6c*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x53a6d*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x53a6e*4+0x02000000,0xc205); +reg_write( DDR_REG_BASE +0x53a6f*4+0x02000000,0xb62); +reg_write( DDR_REG_BASE +0x53a70*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x53a71*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x53a72*4+0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x53a73*4+0x02000000,0xb6f); +reg_write( DDR_REG_BASE +0x53a74*4+0x02000000,0xb094); +reg_write( DDR_REG_BASE +0x53a75*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x53a76*4+0x02000000,0xd53); +reg_write( DDR_REG_BASE +0x53a77*4+0x02000000,0x90b4); +reg_write( DDR_REG_BASE +0x53a78*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53a79*4+0x02000000,0xe26); +reg_write( DDR_REG_BASE +0x53a7a*4+0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53a7b*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x53a7c*4+0x02000000,0xc0a9); +reg_write( DDR_REG_BASE +0x53a7d*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x53a7e*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x53a7f*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53a80*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x53a81*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x53a82*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53a83*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53a84*4+0x02000000,0x8b80); +reg_write( DDR_REG_BASE +0x53a85*4+0x02000000,0x8ba1); +reg_write( DDR_REG_BASE +0x53a86*4+0x02000000,0x245f); +reg_write( DDR_REG_BASE +0x53a87*4+0x02000000,0x1482); +reg_write( DDR_REG_BASE +0x53a88*4+0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x53a89*4+0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x53a8a*4+0x02000000,0x921); +reg_write( DDR_REG_BASE +0x53a8b*4+0x02000000,0xee); +reg_write( DDR_REG_BASE +0x53a8c*4+0x02000000,0x4260); +reg_write( DDR_REG_BASE +0x53a8d*4+0x02000000,0x229a); +reg_write( DDR_REG_BASE +0x53a8e*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x53a8f*4+0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x53a90*4+0x02000000,0x1f8f); +reg_write( DDR_REG_BASE +0x53a91*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a92*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x53a93*4+0x02000000,0x7ae5); +reg_write( DDR_REG_BASE +0x53a94*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x53a95*4+0x02000000,0xf8f); +reg_write( DDR_REG_BASE +0x53a96*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x53a97*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x53a98*4+0x02000000,0x9040); +reg_write( DDR_REG_BASE +0x53a99*4+0x02000000,0xb740); +reg_write( DDR_REG_BASE +0x53a9a*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x53a9b*4+0x02000000,0x7204); +reg_write( DDR_REG_BASE +0x53a9c*4+0x02000000,0xbdd); +reg_write( DDR_REG_BASE +0x53a9d*4+0x02000000,0x8254); +reg_write( DDR_REG_BASE +0x53a9e*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x53a9f*4+0x02000000,0x7e8f); +reg_write( DDR_REG_BASE +0x53aa0*4+0x02000000,0xdf9); +reg_write( DDR_REG_BASE +0x53aa1*4+0x02000000,0x93a5); +reg_write( DDR_REG_BASE +0x53aa2*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x53aa3*4+0x02000000,0xc7e); +reg_write( DDR_REG_BASE +0x53aa4*4+0x02000000,0xfe4f); +reg_write( DDR_REG_BASE +0x53aa5*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53aa6*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x53aa7*4+0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x53aa8*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53aa9*4+0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x53aaa*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53aab*4+0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x53aac*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x53aad*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x53aae*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x53aaf*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53ab0*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x53ab1*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53ab2*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53ab3*4+0x02000000,0x7b45); +reg_write( DDR_REG_BASE +0x53ab4*4+0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x53ab5*4+0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x53ab6*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x53ab7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ab8*4+0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x53ab9*4+0x02000000,0x1301); +reg_write( DDR_REG_BASE +0x53aba*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x53abb*4+0x02000000,0x6c02); +reg_write( DDR_REG_BASE +0x53abc*4+0x02000000,0x78a5); +reg_write( DDR_REG_BASE +0x53abd*4+0x02000000,0xb060); +reg_write( DDR_REG_BASE +0x53abe*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53abf*4+0x02000000,0xd1a); +reg_write( DDR_REG_BASE +0x53ac0*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53ac1*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53ac2*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x53ac3*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x53ac4*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x53ac5*4+0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x53ac6*4+0x02000000,0x3040); +reg_write( DDR_REG_BASE +0x53ac7*4+0x02000000,0x4308); +reg_write( DDR_REG_BASE +0x53ac8*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x53ac9*4+0x02000000,0xf024); +reg_write( DDR_REG_BASE +0x53aca*4+0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x53acb*4+0x02000000,0x1182); +reg_write( DDR_REG_BASE +0x53acc*4+0x02000000,0x7261); +reg_write( DDR_REG_BASE +0x53acd*4+0x02000000,0x8a01); +reg_write( DDR_REG_BASE +0x53ace*4+0x02000000,0x8a60); +reg_write( DDR_REG_BASE +0x53acf*4+0x02000000,0x8a22); +reg_write( DDR_REG_BASE +0x53ad0*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x53ad1*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53ad2*4+0x02000000,0x7b05); +reg_write( DDR_REG_BASE +0x53ad3*4+0x02000000,0x8a03); +reg_write( DDR_REG_BASE +0x53ad4*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x53ad5*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53ad6*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x53ad7*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x53ad8*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53ad9*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53ada*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53adb*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53adc*4+0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x53add*4+0x02000000,0x8a05); +reg_write( DDR_REG_BASE +0x53ade*4+0x02000000,0x8a64); +reg_write( DDR_REG_BASE +0x53adf*4+0x02000000,0x7734); +reg_write( DDR_REG_BASE +0x53ae0*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x53ae1*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53ae2*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x53ae3*4+0x02000000,0xf207); +reg_write( DDR_REG_BASE +0x53ae4*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x53ae5*4+0x02000000,0xb99c); +reg_write( DDR_REG_BASE +0x53ae6*4+0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x53ae7*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x53ae8*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x53ae9*4+0x02000000,0xab6); +reg_write( DDR_REG_BASE +0x53aea*4+0x02000000,0xfe0f); +reg_write( DDR_REG_BASE +0x53aeb*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x53aec*4+0x02000000,0x2e45); +reg_write( DDR_REG_BASE +0x53aed*4+0x02000000,0x3180); +reg_write( DDR_REG_BASE +0x53aee*4+0x02000000,0xdb9); +reg_write( DDR_REG_BASE +0x53aef*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x53af0*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x53af1*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x53af2*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x53af3*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53af4*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53af5*4+0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x53af6*4+0x02000000,0x4718); +reg_write( DDR_REG_BASE +0x53af7*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53af8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53af9*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53afa*4+0x02000000,0x88c0); +reg_write( DDR_REG_BASE +0x53afb*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x53afc*4+0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x53afd*4+0x02000000,0xea04); +reg_write( DDR_REG_BASE +0x53afe*4+0x02000000,0x79db); +reg_write( DDR_REG_BASE +0x53aff*4+0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x53b00*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x53b01*4+0x02000000,0x1241); +reg_write( DDR_REG_BASE +0x53b02*4+0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x53b03*4+0x02000000,0x9e); +reg_write( DDR_REG_BASE +0x53b04*4+0x02000000,0x7054); +reg_write( DDR_REG_BASE +0x53b05*4+0x02000000,0xdd08); +reg_write( DDR_REG_BASE +0x53b06*4+0x02000000,0x25ca); +reg_write( DDR_REG_BASE +0x53b07*4+0x02000000,0x1062); +reg_write( DDR_REG_BASE +0x53b08*4+0x02000000,0xf039); +reg_write( DDR_REG_BASE +0x53b09*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x53b0a*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x53b0b*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53b0c*4+0x02000000,0xc300); +reg_write( DDR_REG_BASE +0x53b0d*4+0x02000000,0x23f5); +reg_write( DDR_REG_BASE +0x53b0e*4+0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x53b0f*4+0x02000000,0xeb13); +reg_write( DDR_REG_BASE +0x53b10*4+0x02000000,0x7c5c); +reg_write( DDR_REG_BASE +0x53b11*4+0x02000000,0x7c9c); +reg_write( DDR_REG_BASE +0x53b12*4+0x02000000,0x7c9c); +reg_write( DDR_REG_BASE +0x53b13*4+0x02000000,0x7c9c); +reg_write( DDR_REG_BASE +0x53b14*4+0x02000000,0x224a); +reg_write( DDR_REG_BASE +0x53b15*4+0x02000000,0x16c0); +reg_write( DDR_REG_BASE +0x53b16*4+0x02000000,0x2a44); +reg_write( DDR_REG_BASE +0x53b17*4+0x02000000,0x803); +reg_write( DDR_REG_BASE +0x53b18*4+0x02000000,0x2242); +reg_write( DDR_REG_BASE +0x53b19*4+0x02000000,0x104a); +reg_write( DDR_REG_BASE +0x53b1a*4+0x02000000,0xafd); +reg_write( DDR_REG_BASE +0x53b1b*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x53b1c*4+0x02000000,0x7c9d); +reg_write( DDR_REG_BASE +0x53b1d*4+0x02000000,0x629a); +reg_write( DDR_REG_BASE +0x53b1e*4+0x02000000,0xbac4); +reg_write( DDR_REG_BASE +0x53b1f*4+0x02000000,0x4a94); +reg_write( DDR_REG_BASE +0x53b20*4+0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x53b21*4+0x02000000,0x248a); +reg_write( DDR_REG_BASE +0x53b22*4+0x02000000,0x1fcf); +reg_write( DDR_REG_BASE +0x53b23*4+0x02000000,0x7c44); +reg_write( DDR_REG_BASE +0x53b24*4+0x02000000,0x2204); +reg_write( DDR_REG_BASE +0x53b25*4+0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x53b26*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b27*4+0x02000000,0xfc00); +reg_write( DDR_REG_BASE +0x53b28*4+0x02000000,0xda0a); +reg_write( DDR_REG_BASE +0x53b29*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x53b2a*4+0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x53b2b*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x53b2c*4+0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x53b2d*4+0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x53b2e*4+0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x53b2f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b30*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x53b31*4+0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x53b32*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53b33*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x53b34*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x53b35*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x53b36*4+0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x53b37*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x53b38*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53b39*4+0x02000000,0xb891); +reg_write( DDR_REG_BASE +0x53b3a*4+0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x53b3b*4+0x02000000,0x7b85); +reg_write( DDR_REG_BASE +0x53b3c*4+0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x53b3d*4+0x02000000,0xb060); +reg_write( DDR_REG_BASE +0x53b3e*4+0x02000000,0xd97); +reg_write( DDR_REG_BASE +0x53b3f*4+0x02000000,0x93c5); +reg_write( DDR_REG_BASE +0x53b40*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x53b41*4+0x02000000,0xefd); +reg_write( DDR_REG_BASE +0x53b42*4+0x02000000,0xb3a5); +reg_write( DDR_REG_BASE +0x53b43*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x53b44*4+0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x53b45*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x53b46*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x53b47*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53b48*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x53b49*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53b4a*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53b4b*4+0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x53b4c*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x53b4d*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53b4e*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53b4f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53b50*4+0x02000000,0x1b); +reg_write( DDR_REG_BASE +0x53b51*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x53b52*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x53b53*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x53b54*4+0x02000000,0x4568); +reg_write( DDR_REG_BASE +0x53b55*4+0x02000000,0x7dc0); +reg_write( DDR_REG_BASE +0x53b56*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x53b57*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53b58*4+0x02000000,0x688); +reg_write( DDR_REG_BASE +0x53b59*4+0x02000000,0x82f); +reg_write( DDR_REG_BASE +0x53b5a*4+0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x53b5b*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x53b5c*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53b5d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53b5e*4+0x02000000,0x7d3); +reg_write( DDR_REG_BASE +0x53b5f*4+0x02000000,0x8904); +reg_write( DDR_REG_BASE +0x53b60*4+0x02000000,0xe80f); +reg_write( DDR_REG_BASE +0x53b61*4+0x02000000,0x8900); +reg_write( DDR_REG_BASE +0x53b62*4+0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x53b63*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53b64*4+0x02000000,0x6ba); +reg_write( DDR_REG_BASE +0x53b65*4+0x02000000,0xaa00); +reg_write( DDR_REG_BASE +0x53b66*4+0x02000000,0x8901); +reg_write( DDR_REG_BASE +0x53b67*4+0x02000000,0xaa19); +reg_write( DDR_REG_BASE +0x53b68*4+0x02000000,0x8902); +reg_write( DDR_REG_BASE +0x53b69*4+0x02000000,0xac00); +reg_write( DDR_REG_BASE +0x53b6a*4+0x02000000,0x8903); +reg_write( DDR_REG_BASE +0x53b6b*4+0x02000000,0xac19); +reg_write( DDR_REG_BASE +0x53b6c*4+0x02000000,0x2350); +reg_write( DDR_REG_BASE +0x53b6d*4+0x02000000,0x300); +reg_write( DDR_REG_BASE +0x53b6e*4+0x02000000,0x7d04); +reg_write( DDR_REG_BASE +0x53b6f*4+0x02000000,0x2242); +reg_write( DDR_REG_BASE +0x53b70*4+0x02000000,0x30e); +reg_write( DDR_REG_BASE +0x53b71*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53b72*4+0x02000000,0xf06); +reg_write( DDR_REG_BASE +0x53b73*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x53b74*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x53b75*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53b76*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x53b77*4+0x02000000,0xcbe); +reg_write( DDR_REG_BASE +0x53b78*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x53b79*4+0x02000000,0xda40); +reg_write( DDR_REG_BASE +0x53b7a*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53b7b*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x53b7c*4+0x02000000,0xe8e); +reg_write( DDR_REG_BASE +0x53b7d*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53b7e*4+0x02000000,0xda7f); +reg_write( DDR_REG_BASE +0x53b7f*4+0x02000000,0xdfff); +reg_write( DDR_REG_BASE +0x53b80*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53b81*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53b82*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x53b83*4+0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x53b84*4+0x02000000,0xd12); +reg_write( DDR_REG_BASE +0x53b85*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x53b86*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53b87*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53b88*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x53b89*4+0x02000000,0xc9a); +reg_write( DDR_REG_BASE +0x53b8a*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x53b8b*4+0x02000000,0xda80); +reg_write( DDR_REG_BASE +0x53b8c*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53b8d*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53b8e*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x53b8f*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x53b90*4+0x02000000,0xdfff); +reg_write( DDR_REG_BASE +0x53b91*4+0x02000000,0x776c); +reg_write( DDR_REG_BASE +0x53b92*4+0x02000000,0xcf6); +reg_write( DDR_REG_BASE +0x53b93*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x53b94*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53b95*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53b96*4+0x02000000,0xabe); +reg_write( DDR_REG_BASE +0x53b97*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x53b98*4+0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x53b99*4+0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x53b9a*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x53b9b*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x53b9c*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53b9d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x53b9e*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x53b9f*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53ba0*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53ba1*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x53ba2*4+0x02000000,0x3403); +reg_write( DDR_REG_BASE +0x53ba3*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53ba4*4+0x02000000,0xf22); +reg_write( DDR_REG_BASE +0x53ba5*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53ba6*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x53ba7*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53ba8*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53ba9*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53baa*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53bab*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53bac*4+0x02000000,0xc22); +reg_write( DDR_REG_BASE +0x53bad*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x53bae*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x53baf*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x53bb0*4+0x02000000,0xe0e); +reg_write( DDR_REG_BASE +0x53bb1*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53bb2*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x53bb3*4+0x02000000,0x3bc1); +reg_write( DDR_REG_BASE +0x53bb4*4+0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x53bb5*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x53bb6*4+0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x53bb7*4+0x02000000,0x17ce); +reg_write( DDR_REG_BASE +0x53bb8*4+0x02000000,0xee05); +reg_write( DDR_REG_BASE +0x53bb9*4+0x02000000,0xbe61); +reg_write( DDR_REG_BASE +0x53bba*4+0x02000000,0xeff); +reg_write( DDR_REG_BASE +0x53bbb*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x53bbc*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53bbd*4+0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x53bbe*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x53bbf*4+0x02000000,0x200f); +reg_write( DDR_REG_BASE +0x53bc0*4+0x02000000,0x340); +reg_write( DDR_REG_BASE +0x53bc1*4+0x02000000,0xd7e); +reg_write( DDR_REG_BASE +0x53bc2*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53bc3*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x53bc4*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53bc5*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53bc6*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53bc7*4+0x02000000,0xfe64); +reg_write( DDR_REG_BASE +0x53bc8*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53bc9*4+0x02000000,0x7044); +reg_write( DDR_REG_BASE +0x53bca*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53bcb*4+0x02000000,0xfe64); +reg_write( DDR_REG_BASE +0x53bcc*4+0x02000000,0x1882); +reg_write( DDR_REG_BASE +0x53bcd*4+0x02000000,0x5c); +reg_write( DDR_REG_BASE +0x53bce*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53bcf*4+0x02000000,0x808); +reg_write( DDR_REG_BASE +0x53bd0*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53bd1*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x53bd2*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53bd3*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x53bd4*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53bd5*4+0x02000000,0x73c4); +reg_write( DDR_REG_BASE +0x53bd6*4+0x02000000,0x900f); +reg_write( DDR_REG_BASE +0x53bd7*4+0x02000000,0xe0c0); +reg_write( DDR_REG_BASE +0x53bd8*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53bd9*4+0x02000000,0x7044); +reg_write( DDR_REG_BASE +0x53bda*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53bdb*4+0x02000000,0xfe64); +reg_write( DDR_REG_BASE +0x53bdc*4+0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x53bdd*4+0x02000000,0x6941); +reg_write( DDR_REG_BASE +0x53bde*4+0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x53bdf*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x53be0*4+0x02000000,0x43e1); +reg_write( DDR_REG_BASE +0x53be1*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x53be2*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x53be3*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x53be4*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x53be5*4+0x02000000,0x7b7b); +reg_write( DDR_REG_BASE +0x53be6*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x53be7*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53be8*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53be9*4+0x02000000,0xe0c4); +reg_write( DDR_REG_BASE +0x53bea*4+0x02000000,0xb060); +reg_write( DDR_REG_BASE +0x53beb*4+0x02000000,0x4140); +reg_write( DDR_REG_BASE +0x53bec*4+0x02000000,0x9e3); +reg_write( DDR_REG_BASE +0x53bed*4+0x02000000,0x8234); +reg_write( DDR_REG_BASE +0x53bee*4+0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x53bef*4+0x02000000,0x7c0); +reg_write( DDR_REG_BASE +0x53bf0*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x53bf1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bf2*4+0x02000000,0xaaaa); +reg_write( DDR_REG_BASE +0x53bf3*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53bf4*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x53bf5*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x53bf6*4+0x02000000,0x43a1); +reg_write( DDR_REG_BASE +0x53bf7*4+0x02000000,0x98e); +reg_write( DDR_REG_BASE +0x53bf8*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53bf9*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53bfa*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53bfb*4+0x02000000,0xe2a); +reg_write( DDR_REG_BASE +0x53bfc*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53bfd*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x53bfe*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53bff*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c00*4+0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x53c01*4+0x02000000,0xe82); +reg_write( DDR_REG_BASE +0x53c02*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x53c03*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53c04*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x53c05*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53c06*4+0x02000000,0xe174); +reg_write( DDR_REG_BASE +0x53c07*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53c08*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x53c09*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53c0a*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x53c0b*4+0x02000000,0xb601); +reg_write( DDR_REG_BASE +0x53c0c*4+0x02000000,0x43db); +reg_write( DDR_REG_BASE +0x53c0d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c0e*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x53c0f*4+0x02000000,0xd830); +reg_write( DDR_REG_BASE +0x53c10*4+0x02000000,0x1e58); +reg_write( DDR_REG_BASE +0x53c11*4+0x02000000,0x96dc); +reg_write( DDR_REG_BASE +0x53c12*4+0x02000000,0x1e5e); +reg_write( DDR_REG_BASE +0x53c13*4+0x02000000,0x93dc); +reg_write( DDR_REG_BASE +0x53c14*4+0x02000000,0xa6e); +reg_write( DDR_REG_BASE +0x53c15*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53c16*4+0x02000000,0x1e57); +reg_write( DDR_REG_BASE +0x53c17*4+0x02000000,0x93dc); +reg_write( DDR_REG_BASE +0x53c18*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53c19*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53c1a*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53c1b*4+0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x53c1c*4+0x02000000,0x942); +reg_write( DDR_REG_BASE +0x53c1d*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53c1e*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x53c1f*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x53c20*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x53c21*4+0x02000000,0xa56); +reg_write( DDR_REG_BASE +0x53c22*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53c23*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53c24*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53c25*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x53c26*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x53c27*4+0x02000000,0x43a1); +reg_write( DDR_REG_BASE +0x53c28*4+0x02000000,0x92a); +reg_write( DDR_REG_BASE +0x53c29*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53c2a*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53c2b*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53c2c*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x53c2d*4+0x02000000,0xb601); +reg_write( DDR_REG_BASE +0x53c2e*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x53c2f*4+0x02000000,0x1e58); +reg_write( DDR_REG_BASE +0x53c30*4+0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x53c31*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53c32*4+0x02000000,0x844); +reg_write( DDR_REG_BASE +0x53c33*4+0x02000000,0x1e5e); +reg_write( DDR_REG_BASE +0x53c34*4+0x02000000,0x93dc); +reg_write( DDR_REG_BASE +0x53c35*4+0x02000000,0x1e57); +reg_write( DDR_REG_BASE +0x53c36*4+0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x53c37*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53c38*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c39*4+0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x53c3a*4+0x02000000,0xe0e); +reg_write( DDR_REG_BASE +0x53c3b*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x53c3c*4+0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x53c3d*4+0x02000000,0xd830); +reg_write( DDR_REG_BASE +0x53c3e*4+0x02000000,0xa1a); +reg_write( DDR_REG_BASE +0x53c3f*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53c40*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53c41*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x53c42*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53c43*4+0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x53c44*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53c45*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53c46*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x53c47*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53c48*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x53c49*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c4a*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x53c4b*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53c4c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53c4d*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53c4e*4+0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x53c4f*4+0x02000000,0xf022); +reg_write( DDR_REG_BASE +0x53c50*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53c51*4+0x02000000,0x2016); +reg_write( DDR_REG_BASE +0x53c52*4+0x02000000,0x83); +reg_write( DDR_REG_BASE +0x53c53*4+0x02000000,0xf01a); +reg_write( DDR_REG_BASE +0x53c54*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x53c55*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x53c56*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x53c57*4+0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x53c58*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c59*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x53c5a*4+0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x53c5b*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53c5c*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53c5d*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x53c5e*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x53c5f*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x53c60*4+0x02000000,0x7c1d); +reg_write( DDR_REG_BASE +0x53c61*4+0x02000000,0x7c9d); +reg_write( DDR_REG_BASE +0x53c62*4+0x02000000,0x7c9d); +reg_write( DDR_REG_BASE +0x53c63*4+0x02000000,0x7c9d); +reg_write( DDR_REG_BASE +0x53c64*4+0x02000000,0x7c9d); +reg_write( DDR_REG_BASE +0x53c65*4+0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x53c66*4+0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x53c67*4+0x02000000,0xc087); +reg_write( DDR_REG_BASE +0x53c68*4+0x02000000,0x7874); +reg_write( DDR_REG_BASE +0x53c69*4+0x02000000,0xb080); +reg_write( DDR_REG_BASE +0x53c6a*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x53c6b*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x53c6c*4+0x02000000,0x8d1); +reg_write( DDR_REG_BASE +0x53c6d*4+0x02000000,0x8234); +reg_write( DDR_REG_BASE +0x53c6e*4+0x02000000,0x68e1); +reg_write( DDR_REG_BASE +0x53c6f*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x53c70*4+0x02000000,0x9c1); +reg_write( DDR_REG_BASE +0x53c71*4+0x02000000,0x80a5); +reg_write( DDR_REG_BASE +0x53c72*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53c73*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x53c74*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x53c75*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x53c76*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x53c77*4+0x02000000,0xb6e1); +reg_write( DDR_REG_BASE +0x53c78*4+0x02000000,0x1e58); +reg_write( DDR_REG_BASE +0x53c79*4+0x02000000,0x96dc); +reg_write( DDR_REG_BASE +0x53c7a*4+0x02000000,0x1e5e); +reg_write( DDR_REG_BASE +0x53c7b*4+0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x53c7c*4+0x02000000,0x1e57); +reg_write( DDR_REG_BASE +0x53c7d*4+0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x53c7e*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53c7f*4+0x02000000,0x7d0); +reg_write( DDR_REG_BASE +0x53c80*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53c81*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x53c82*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53c83*4+0x02000000,0xfe64); +reg_write( DDR_REG_BASE +0x53c84*4+0x02000000,0xd830); +reg_write( DDR_REG_BASE +0x53c85*4+0x02000000,0x98e); +reg_write( DDR_REG_BASE +0x53c86*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53c87*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53c88*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53c89*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53c8a*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53c8b*4+0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x53c8c*4+0x02000000,0x862); +reg_write( DDR_REG_BASE +0x53c8d*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53c8e*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x53c8f*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x53c90*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x53c91*4+0x02000000,0x976); +reg_write( DDR_REG_BASE +0x53c92*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53c93*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53c94*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53c95*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x53c96*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x53c97*4+0x02000000,0x43a1); +reg_write( DDR_REG_BASE +0x53c98*4+0x02000000,0x84a); +reg_write( DDR_REG_BASE +0x53c99*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53c9a*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53c9b*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53c9c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c9d*4+0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x53c9e*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53c9f*4+0x02000000,0xb6e0); +reg_write( DDR_REG_BASE +0x53ca0*4+0x02000000,0xd42); +reg_write( DDR_REG_BASE +0x53ca1*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x53ca2*4+0x02000000,0xb6e1); +reg_write( DDR_REG_BASE +0x53ca3*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x53ca4*4+0x02000000,0x1e58); +reg_write( DDR_REG_BASE +0x53ca5*4+0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x53ca6*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x53ca7*4+0x02000000,0x1e5e); +reg_write( DDR_REG_BASE +0x53ca8*4+0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x53ca9*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53caa*4+0x02000000,0x844); +reg_write( DDR_REG_BASE +0x53cab*4+0x02000000,0x1e57); +reg_write( DDR_REG_BASE +0x53cac*4+0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x53cad*4+0x02000000,0x93e); +reg_write( DDR_REG_BASE +0x53cae*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53caf*4+0x02000000,0xd830); +reg_write( DDR_REG_BASE +0x53cb0*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53cb1*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53cb2*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53cb3*4+0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x53cb4*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53cb5*4+0x02000000,0x708b); +reg_write( DDR_REG_BASE +0x53cb6*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53cb7*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53cb8*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x53cb9*4+0x02000000,0xf084); +reg_write( DDR_REG_BASE +0x53cba*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x53cbb*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x53cbc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cbd*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x53cbe*4+0x02000000,0x2716); +reg_write( DDR_REG_BASE +0x53cbf*4+0x02000000,0x12de); +reg_write( DDR_REG_BASE +0x53cc0*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53cc1*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53cc2*4+0x02000000,0xc104); +reg_write( DDR_REG_BASE +0x53cc3*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x53cc4*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x53cc5*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x53cc6*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x53cc7*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x53cc8*4+0x02000000,0xd01); +reg_write( DDR_REG_BASE +0x53cc9*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53cca*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x53ccb*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53ccc*4+0x02000000,0xb891); +reg_write( DDR_REG_BASE +0x53ccd*4+0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x53cce*4+0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x53ccf*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x53cd0*4+0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x53cd1*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x53cd2*4+0x02000000,0xf05d); +reg_write( DDR_REG_BASE +0x53cd3*4+0x02000000,0x4340); +reg_write( DDR_REG_BASE +0x53cd4*4+0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x53cd5*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53cd6*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53cd7*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x53cd8*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53cd9*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53cda*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53cdb*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x53cdc*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x53cdd*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x53cde*4+0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x53cdf*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x53ce0*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x53ce1*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x53ce2*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x53ce3*4+0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x53ce4*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x53ce5*4+0x02000000,0xc087); +reg_write( DDR_REG_BASE +0x53ce6*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x53ce7*4+0x02000000,0x79f); +reg_write( DDR_REG_BASE +0x53ce8*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x53ce9*4+0x02000000,0x3bc0); +reg_write( DDR_REG_BASE +0x53cea*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x53ceb*4+0x02000000,0x2cc); +reg_write( DDR_REG_BASE +0x53cec*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x53ced*4+0x02000000,0x71f3); +reg_write( DDR_REG_BASE +0x53cee*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x53cef*4+0x02000000,0x101b); +reg_write( DDR_REG_BASE +0x53cf0*4+0x02000000,0x27d4); +reg_write( DDR_REG_BASE +0x53cf1*4+0x02000000,0x3829); +reg_write( DDR_REG_BASE +0x53cf2*4+0x02000000,0x71e3); +reg_write( DDR_REG_BASE +0x53cf3*4+0x02000000,0x2340); +reg_write( DDR_REG_BASE +0x53cf4*4+0x02000000,0x340c); +reg_write( DDR_REG_BASE +0x53cf5*4+0x02000000,0x782e); +reg_write( DDR_REG_BASE +0x53cf6*4+0x02000000,0x791c); +reg_write( DDR_REG_BASE +0x53cf7*4+0x02000000,0x7c8e); +reg_write( DDR_REG_BASE +0x53cf8*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x53cf9*4+0x02000000,0x792e); +reg_write( DDR_REG_BASE +0x53cfa*4+0x02000000,0x4990); +reg_write( DDR_REG_BASE +0x53cfb*4+0x02000000,0x2154); +reg_write( DDR_REG_BASE +0x53cfc*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x53cfd*4+0x02000000,0x272f); +reg_write( DDR_REG_BASE +0x53cfe*4+0x02000000,0x3009); +reg_write( DDR_REG_BASE +0x53cff*4+0x02000000,0x4990); +reg_write( DDR_REG_BASE +0x53d00*4+0x02000000,0x7811); +reg_write( DDR_REG_BASE +0x53d01*4+0x02000000,0x8f1); +reg_write( DDR_REG_BASE +0x53d02*4+0x02000000,0x87c2); +reg_write( DDR_REG_BASE +0x53d03*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53d04*4+0x02000000,0x3f); +reg_write( DDR_REG_BASE +0x53d05*4+0x02000000,0x4891); +reg_write( DDR_REG_BASE +0x53d06*4+0x02000000,0x78ae); +reg_write( DDR_REG_BASE +0x53d07*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x53d08*4+0x02000000,0x272f); +reg_write( DDR_REG_BASE +0x53d09*4+0x02000000,0x3049); +reg_write( DDR_REG_BASE +0x53d0a*4+0x02000000,0x4891); +reg_write( DDR_REG_BASE +0x53d0b*4+0x02000000,0x7931); +reg_write( DDR_REG_BASE +0x53d0c*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x53d0d*4+0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x53d0e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d0f*4+0x02000000,0xffc0); +reg_write( DDR_REG_BASE +0x53d10*4+0x02000000,0xfe7); +reg_write( DDR_REG_BASE +0x53d11*4+0x02000000,0xb042); +reg_write( DDR_REG_BASE +0x53d12*4+0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x53d13*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53d14*4+0x02000000,0x783b); +reg_write( DDR_REG_BASE +0x53d15*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x53d16*4+0x02000000,0x7); +reg_write( DDR_REG_BASE +0x53d17*4+0x02000000,0xb9c4); +reg_write( DDR_REG_BASE +0x53d18*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x53d19*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x53d1a*4+0x02000000,0xc405); +reg_write( DDR_REG_BASE +0x53d1b*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x53d1c*4+0x02000000,0xc00); +reg_write( DDR_REG_BASE +0x53d1d*4+0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x53d1e*4+0x02000000,0x7b85); +reg_write( DDR_REG_BASE +0x53d1f*4+0x02000000,0x787b); +reg_write( DDR_REG_BASE +0x53d20*4+0x02000000,0xb891); +reg_write( DDR_REG_BASE +0x53d21*4+0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x53d22*4+0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x53d23*4+0x02000000,0xa15); +reg_write( DDR_REG_BASE +0x53d24*4+0x02000000,0x1f1); +reg_write( DDR_REG_BASE +0x53d25*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x53d26*4+0x02000000,0x789b); +reg_write( DDR_REG_BASE +0x53d27*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53d28*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53d29*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x53d2a*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x53d2b*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x53d2c*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x53d2d*4+0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x53d2e*4+0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x53d2f*4+0x02000000,0xa4b); +reg_write( DDR_REG_BASE +0x53d30*4+0x02000000,0x8214); +reg_write( DDR_REG_BASE +0x53d31*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x53d32*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x53d33*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d34*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x53d35*4+0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x53d36*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53d37*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x53d38*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x53d39*4+0x02000000,0x1e64); +reg_write( DDR_REG_BASE +0x53d3a*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x53d3b*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x53d3c*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53d3d*4+0x02000000,0x230c); +reg_write( DDR_REG_BASE +0x53d3e*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x53d3f*4+0x02000000,0x6f8); +reg_write( DDR_REG_BASE +0x53d40*4+0x02000000,0xffee); +reg_write( DDR_REG_BASE +0x53d41*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53d42*4+0x02000000,0x1e58); +reg_write( DDR_REG_BASE +0x53d43*4+0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x53d44*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53d45*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53d46*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d47*4+0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x53d48*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x53d49*4+0x02000000,0x1e5e); +reg_write( DDR_REG_BASE +0x53d4a*4+0x02000000,0x905c); +reg_write( DDR_REG_BASE +0x53d4b*4+0x02000000,0xbee); +reg_write( DDR_REG_BASE +0x53d4c*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x53d4d*4+0x02000000,0x1e57); +reg_write( DDR_REG_BASE +0x53d4e*4+0x02000000,0x905c); +reg_write( DDR_REG_BASE +0x53d4f*4+0x02000000,0xf26); +reg_write( DDR_REG_BASE +0x53d50*4+0x02000000,0xfe0f); +reg_write( DDR_REG_BASE +0x53d51*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53d52*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53d53*4+0x02000000,0xfe64); +reg_write( DDR_REG_BASE +0x53d54*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53d55*4+0x02000000,0x73c4); +reg_write( DDR_REG_BASE +0x53d56*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53d57*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x53d58*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53d59*4+0x02000000,0x7344); +reg_write( DDR_REG_BASE +0x53d5a*4+0x02000000,0x900f); +reg_write( DDR_REG_BASE +0x53d5b*4+0x02000000,0xe0c0); +reg_write( DDR_REG_BASE +0x53d5c*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53d5d*4+0x02000000,0x73c4); +reg_write( DDR_REG_BASE +0x53d5e*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53d5f*4+0x02000000,0xfec4); +reg_write( DDR_REG_BASE +0x53d60*4+0x02000000,0x1882); +reg_write( DDR_REG_BASE +0x53d61*4+0x02000000,0x3dc); +reg_write( DDR_REG_BASE +0x53d62*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53d63*4+0x02000000,0xb5a); +reg_write( DDR_REG_BASE +0x53d64*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53d65*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x53d66*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53d67*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d68*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x53d69*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53d6a*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53d6b*4+0x02000000,0x4320); +reg_write( DDR_REG_BASE +0x53d6c*4+0x02000000,0xea2); +reg_write( DDR_REG_BASE +0x53d6d*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53d6e*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53d6f*4+0x02000000,0xf03b); +reg_write( DDR_REG_BASE +0x53d70*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53d71*4+0x02000000,0xfb6); +reg_write( DDR_REG_BASE +0x53d72*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53d73*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53d74*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53d75*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53d76*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53d77*4+0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x53d78*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53d79*4+0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x53d7a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53d7b*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53d7c*4+0x02000000,0xf023); +reg_write( DDR_REG_BASE +0x53d7d*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x53d7e*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53d7f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d80*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x53d81*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53d82*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53d83*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x53d84*4+0x02000000,0x166); +reg_write( DDR_REG_BASE +0x53d85*4+0x02000000,0x9060); +reg_write( DDR_REG_BASE +0x53d86*4+0x02000000,0xeb17); +reg_write( DDR_REG_BASE +0x53d87*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x53d88*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x53d89*4+0x02000000,0xd0c); +reg_write( DDR_REG_BASE +0x53d8a*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x53d8b*4+0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x53d8c*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x53d8d*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53d8e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d8f*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x53d90*4+0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x53d91*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53d92*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53d93*4+0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x53d94*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x53d95*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53d96*4+0x02000000,0xb891); +reg_write( DDR_REG_BASE +0x53d97*4+0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x53d98*4+0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x53d99*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x53d9a*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x53d9b*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x53d9c*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x53d9d*4+0x02000000,0x657d); +reg_write( DDR_REG_BASE +0x53d9e*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x53d9f*4+0x02000000,0x9bf); +reg_write( DDR_REG_BASE +0x53da0*4+0x02000000,0x80a5); +reg_write( DDR_REG_BASE +0x53da1*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53da2*4+0x02000000,0xada); +reg_write( DDR_REG_BASE +0x53da3*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53da4*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x53da5*4+0x02000000,0xe7a); +reg_write( DDR_REG_BASE +0x53da6*4+0x02000000,0xfe0f); +reg_write( DDR_REG_BASE +0x53da7*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x53da8*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x53da9*4+0x02000000,0xf91); +reg_write( DDR_REG_BASE +0x53daa*4+0x02000000,0x9234); +reg_write( DDR_REG_BASE +0x53dab*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x53dac*4+0x02000000,0x2178); +reg_write( DDR_REG_BASE +0x53dad*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dae*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53daf*4+0x02000000,0x156); +reg_write( DDR_REG_BASE +0x53db0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53db1*4+0x02000000,0xdf2); +reg_write( DDR_REG_BASE +0x53db2*4+0x02000000,0xfc0f); +reg_write( DDR_REG_BASE +0x53db3*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53db4*4+0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x53db5*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53db6*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x53db7*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x53db8*4+0x02000000,0x3403); +reg_write( DDR_REG_BASE +0x53db9*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x53dba*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x53dbb*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53dbc*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x53dbd*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x53dbe*4+0x02000000,0x3302); +reg_write( DDR_REG_BASE +0x53dbf*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x53dc0*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53dc1*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53dc2*4+0x02000000,0x597); +reg_write( DDR_REG_BASE +0x53dc3*4+0x02000000,0xcfe); +reg_write( DDR_REG_BASE +0x53dc4*4+0x02000000,0xfc2f); +reg_write( DDR_REG_BASE +0x53dc5*4+0x02000000,0xda8a); +reg_write( DDR_REG_BASE +0x53dc6*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x53dc7*4+0x02000000,0x9fe); +reg_write( DDR_REG_BASE +0x53dc8*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x53dc9*4+0x02000000,0xd98a); +reg_write( DDR_REG_BASE +0x53dca*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53dcb*4+0x02000000,0xa8a); +reg_write( DDR_REG_BASE +0x53dcc*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53dcd*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x53dce*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x53dcf*4+0x02000000,0x3302); +reg_write( DDR_REG_BASE +0x53dd0*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x53dd1*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x53dd2*4+0x02000000,0xc3e6); +reg_write( DDR_REG_BASE +0x53dd3*4+0x02000000,0xc1b2); +reg_write( DDR_REG_BASE +0x53dd4*4+0x02000000,0xc14a); +reg_write( DDR_REG_BASE +0x53dd5*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x53dd6*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53dd7*4+0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x53dd8*4+0x02000000,0xe805); +reg_write( DDR_REG_BASE +0x53dd9*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x53dda*4+0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x53ddb*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x53ddc*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x53ddd*4+0x02000000,0x215a); +reg_write( DDR_REG_BASE +0x53dde*4+0x02000000,0x101); +reg_write( DDR_REG_BASE +0x53ddf*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53de0*4+0x02000000,0x210f); +reg_write( DDR_REG_BASE +0x53de1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53de2*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x53de3*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53de4*4+0x02000000,0xaa2); +reg_write( DDR_REG_BASE +0x53de5*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53de6*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53de7*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53de8*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x53de9*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53dea*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53deb*4+0x02000000,0xd2a); +reg_write( DDR_REG_BASE +0x53dec*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53ded*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x53dee*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x53def*4+0x02000000,0x8e82); +reg_write( DDR_REG_BASE +0x53df0*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x53df1*4+0x02000000,0xd8fe); +reg_write( DDR_REG_BASE +0x53df2*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53df3*4+0x02000000,0xf707); +reg_write( DDR_REG_BASE +0x53df4*4+0x02000000,0xd16); +reg_write( DDR_REG_BASE +0x53df5*4+0x02000000,0xfd0f); +reg_write( DDR_REG_BASE +0x53df6*4+0x02000000,0x2054); +reg_write( DDR_REG_BASE +0x53df7*4+0x02000000,0x880); +reg_write( DDR_REG_BASE +0x53df8*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53df9*4+0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x53dfa*4+0x02000000,0x1f8d); +reg_write( DDR_REG_BASE +0x53dfb*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x53dfc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dfd*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x53dfe*4+0x02000000,0xc18d); +reg_write( DDR_REG_BASE +0x53dff*4+0x02000000,0xd12); +reg_write( DDR_REG_BASE +0x53e00*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x53e01*4+0x02000000,0xc54b); +reg_write( DDR_REG_BASE +0x53e02*4+0x02000000,0xf76); +reg_write( DDR_REG_BASE +0x53e03*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x53e04*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x53e05*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53e06*4+0x02000000,0xe002); +reg_write( DDR_REG_BASE +0x53e07*4+0x02000000,0xd840); +reg_write( DDR_REG_BASE +0x53e08*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x53e09*4+0x02000000,0x1f84); +reg_write( DDR_REG_BASE +0x53e0a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e0b*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53e0c*4+0x02000000,0xd1e); +reg_write( DDR_REG_BASE +0x53e0d*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53e0e*4+0x02000000,0xb512); +reg_write( DDR_REG_BASE +0x53e0f*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53e10*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x53e11*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x53e12*4+0x02000000,0x4a); +reg_write( DDR_REG_BASE +0x53e13*4+0x02000000,0xd998); +reg_write( DDR_REG_BASE +0x53e14*4+0x02000000,0x2011); +reg_write( DDR_REG_BASE +0x53e15*4+0x02000000,0x8380); +reg_write( DDR_REG_BASE +0x53e16*4+0x02000000,0xd8aa); +reg_write( DDR_REG_BASE +0x53e17*4+0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x53e18*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53e19*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53e1a*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x53e1b*4+0x02000000,0xe04c); +reg_write( DDR_REG_BASE +0x53e1c*4+0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x53e1d*4+0x02000000,0x189c); +reg_write( DDR_REG_BASE +0x53e1e*4+0x02000000,0x54); +reg_write( DDR_REG_BASE +0x53e1f*4+0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x53e20*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53e21*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x53e22*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x53e23*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e24*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53e25*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53e26*4+0x02000000,0x2056); +reg_write( DDR_REG_BASE +0x53e27*4+0x02000000,0xe00); +reg_write( DDR_REG_BASE +0x53e28*4+0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x53e29*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x53e2a*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x53e2b*4+0x02000000,0x16e9); +reg_write( DDR_REG_BASE +0x53e2c*4+0x02000000,0x1700); +reg_write( DDR_REG_BASE +0x53e2d*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x53e2e*4+0x02000000,0xda2); +reg_write( DDR_REG_BASE +0x53e2f*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53e30*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53e31*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53e32*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x53e33*4+0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x53e34*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53e35*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53e36*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53e37*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53e38*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x53e39*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53e3a*4+0x02000000,0xe62); +reg_write( DDR_REG_BASE +0x53e3b*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53e3c*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53e3d*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53e3e*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x53e3f*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53e40*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x53e41*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x53e42*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53e43*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53e44*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53e45*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53e46*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x53e47*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x53e48*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x53e49*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x53e4a*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53e4b*4+0x02000000,0xc304); +reg_write( DDR_REG_BASE +0x53e4c*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x53e4d*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53e4e*4+0x02000000,0xe3a); +reg_write( DDR_REG_BASE +0x53e4f*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53e50*4+0x02000000,0xb990); +reg_write( DDR_REG_BASE +0x53e51*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53e52*4+0x02000000,0xdf2); +reg_write( DDR_REG_BASE +0x53e53*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53e54*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53e55*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53e56*4+0x02000000,0x9de); +reg_write( DDR_REG_BASE +0x53e57*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x53e58*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x53e59*4+0x02000000,0x16f0); +reg_write( DDR_REG_BASE +0x53e5a*4+0x02000000,0x1700); +reg_write( DDR_REG_BASE +0x53e5b*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x53e5c*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x53e5d*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x53e5e*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53e5f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e60*4+0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x53e61*4+0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x53e62*4+0x02000000,0xb888); +reg_write( DDR_REG_BASE +0x53e63*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x53e64*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x53e65*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x53e66*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53e67*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x53e68*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x53e69*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x53e6a*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x53e6b*4+0x02000000,0x7932); +reg_write( DDR_REG_BASE +0x53e6c*4+0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x53e6d*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x53e6e*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x53e6f*4+0x02000000,0xb887); +reg_write( DDR_REG_BASE +0x53e70*4+0x02000000,0x1ef2); +reg_write( DDR_REG_BASE +0x53e71*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x53e72*4+0x02000000,0xc109); +reg_write( DDR_REG_BASE +0x53e73*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x53e74*4+0x02000000,0xc0a); +reg_write( DDR_REG_BASE +0x53e75*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53e76*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x53e77*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x53e78*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53e79*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53e7a*4+0x02000000,0xd0a); +reg_write( DDR_REG_BASE +0x53e7b*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53e7c*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53e7d*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x53e7e*4+0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x53e7f*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53e80*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53e81*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53e82*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53e83*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x53e84*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53e85*4+0x02000000,0xdce); +reg_write( DDR_REG_BASE +0x53e86*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53e87*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53e88*4+0x02000000,0x812); +reg_write( DDR_REG_BASE +0x53e89*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53e8a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53e8b*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53e8c*4+0x02000000,0xc304); +reg_write( DDR_REG_BASE +0x53e8d*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x53e8e*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53e8f*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53e90*4+0x02000000,0xb88f); +reg_write( DDR_REG_BASE +0x53e91*4+0x02000000,0x791b); +reg_write( DDR_REG_BASE +0x53e92*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53e93*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53e94*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53e95*4+0x02000000,0xdae); +reg_write( DDR_REG_BASE +0x53e96*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53e97*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53e98*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x53e99*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x53e9a*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53e9b*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x53e9c*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x53e9d*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x53e9e*4+0x02000000,0xe01e); +reg_write( DDR_REG_BASE +0x53e9f*4+0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x53ea0*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53ea1*4+0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x53ea2*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x53ea3*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53ea4*4+0x02000000,0xd8e); +reg_write( DDR_REG_BASE +0x53ea5*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53ea6*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53ea7*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x53ea8*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53ea9*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x53eaa*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53eab*4+0x02000000,0xb98f); +reg_write( DDR_REG_BASE +0x53eac*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53ead*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x53eae*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x53eaf*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53eb0*4+0x02000000,0xd76); +reg_write( DDR_REG_BASE +0x53eb1*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53eb2*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53eb3*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53eb4*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53eb5*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53eb6*4+0x02000000,0xdb10); +reg_write( DDR_REG_BASE +0x53eb7*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53eb8*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x53eb9*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53eba*4+0x02000000,0xd62); +reg_write( DDR_REG_BASE +0x53ebb*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53ebc*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53ebd*4+0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x53ebe*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53ebf*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53ec0*4+0x02000000,0xf838); +reg_write( DDR_REG_BASE +0x53ec1*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53ec2*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x53ec3*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53ec4*4+0x02000000,0xd4e); +reg_write( DDR_REG_BASE +0x53ec5*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53ec6*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53ec7*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53ec8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ec9*4+0x02000000,0x6210); +reg_write( DDR_REG_BASE +0x53eca*4+0x02000000,0xb501); +reg_write( DDR_REG_BASE +0x53ecb*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x53ecc*4+0x02000000,0xcfe); +reg_write( DDR_REG_BASE +0x53ecd*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53ece*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53ecf*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53ed0*4+0x02000000,0x408); +reg_write( DDR_REG_BASE +0x53ed1*4+0x02000000,0xb501); +reg_write( DDR_REG_BASE +0x53ed2*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53ed3*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53ed4*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53ed5*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53ed6*4+0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x53ed7*4+0x02000000,0xbf); +reg_write( DDR_REG_BASE +0x53ed8*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53ed9*4+0x02000000,0x606); +reg_write( DDR_REG_BASE +0x53eda*4+0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x53edb*4+0x02000000,0xd833); +reg_write( DDR_REG_BASE +0x53edc*4+0x02000000,0xcde); +reg_write( DDR_REG_BASE +0x53edd*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53ede*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53edf*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x53ee0*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53ee1*4+0x02000000,0x1ef2); +reg_write( DDR_REG_BASE +0x53ee2*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x53ee3*4+0x02000000,0x8c6); +reg_write( DDR_REG_BASE +0x53ee4*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x53ee5*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53ee6*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53ee7*4+0x02000000,0xb42); +reg_write( DDR_REG_BASE +0x53ee8*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x53ee9*4+0x02000000,0xc18d); +reg_write( DDR_REG_BASE +0x53eea*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x53eeb*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53eec*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53eed*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53eee*4+0x02000000,0xb5e0); +reg_write( DDR_REG_BASE +0x53eef*4+0x02000000,0xc22); +reg_write( DDR_REG_BASE +0x53ef0*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53ef1*4+0x02000000,0xb5f2); +reg_write( DDR_REG_BASE +0x53ef2*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x53ef3*4+0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x53ef4*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53ef5*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53ef6*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53ef7*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53ef8*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x53ef9*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53efa*4+0x02000000,0xce2); +reg_write( DDR_REG_BASE +0x53efb*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53efc*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53efd*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53efe*4+0x02000000,0xc304); +reg_write( DDR_REG_BASE +0x53eff*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53f00*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53f01*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53f02*4+0x02000000,0xb990); +reg_write( DDR_REG_BASE +0x53f03*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x53f04*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53f05*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53f06*4+0x02000000,0xcca); +reg_write( DDR_REG_BASE +0x53f07*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53f08*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53f09*4+0x02000000,0xf814); +reg_write( DDR_REG_BASE +0x53f0a*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53f0b*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x53f0c*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53f0d*4+0x02000000,0xcbe); +reg_write( DDR_REG_BASE +0x53f0e*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53f0f*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53f10*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53f11*4+0x02000000,0xc76); +reg_write( DDR_REG_BASE +0x53f12*4+0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53f13*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53f14*4+0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x53f15*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53f16*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53f17*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x53f18*4+0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x53f19*4+0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x53f1a*4+0x02000000,0xb5e1); +reg_write( DDR_REG_BASE +0x53f1b*4+0x02000000,0xb0e); +reg_write( DDR_REG_BASE +0x53f1c*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x53f1d*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x53f1e*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53f1f*4+0x02000000,0x82e); +reg_write( DDR_REG_BASE +0x53f20*4+0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53f21*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53f22*4+0x02000000,0xc10b); +reg_write( DDR_REG_BASE +0x53f23*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x53f24*4+0x02000000,0xd00); +reg_write( DDR_REG_BASE +0x53f25*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x53f26*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x53f27*4+0x02000000,0xc10a); +reg_write( DDR_REG_BASE +0x53f28*4+0x02000000,0xf96); +reg_write( DDR_REG_BASE +0x53f29*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x53f2a*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x53f2b*4+0x02000000,0xb6e); +reg_write( DDR_REG_BASE +0x53f2c*4+0x02000000,0xfe0f); +reg_write( DDR_REG_BASE +0x53f2d*4+0x02000000,0xc02); +reg_write( DDR_REG_BASE +0x53f2e*4+0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x53f2f*4+0x02000000,0xc7c6); +reg_write( DDR_REG_BASE +0x53f30*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53f31*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x53f32*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53f33*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x53f34*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x53f35*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f36*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f37*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f38*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f39*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f40*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f41*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f42*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f43*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f44*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f45*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f46*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f47*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f48*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f49*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f50*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f51*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f52*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f53*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f54*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f55*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f56*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f57*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f58*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f59*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f60*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f61*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f62*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f63*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f64*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f65*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f66*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f67*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f68*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f69*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f70*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f71*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f72*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f73*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f74*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f75*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f76*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f77*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f78*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f79*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f80*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f81*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f82*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f83*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f84*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f85*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f86*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f87*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f88*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f89*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f90*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f91*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f92*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f93*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f94*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f95*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f96*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f97*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f98*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f99*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53faa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fab*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fad*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fae*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53faf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fba*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fbb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fbc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fbd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fbe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fbf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fca*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fcb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fcc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fcd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fce*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fcf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fda*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fdb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fdc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fdd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fde*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fdf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fea*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53feb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fec*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fed*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fef*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ffa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ffb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ffc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ffd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ffe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fff*4+0x02000000,0x0); + +reg_write( DDR_REG_BASE + 0xd0000*4+0x02000000,0x1); +reg_write( DDR_REG_BASE + 0xd0000*4+0x02000000,0x0); + +reg_write( DDR_REG_BASE +0x54000*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x54001*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54002*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54003*4+0x02000000,0xa6a); +reg_write( DDR_REG_BASE +0x54004*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x54005*4+0x02000000,0x0); + +//iteration Vref +// 0x14 15% +// 0x1a 20% +// 0x20 25% +// 0x26 30% +// 0x33 40% +reg_write( DDR_REG_BASE +0x54006*4+0x02000000,0x1a); + +reg_write( DDR_REG_BASE +0x54007*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54008*4+0x02000000,0x131f); +reg_write( DDR_REG_BASE +0x54009*4+0x02000000,0xc8); +reg_write( DDR_REG_BASE +0x5400a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5400b*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x5400c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5400d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5400e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5400f*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x54010*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54011*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54012*4+0x02000000,0x110); +reg_write( DDR_REG_BASE +0x54013*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54014*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54015*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54016*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54017*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54018*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54019*4+0x02000000,0x2444); +reg_write( DDR_REG_BASE +0x5401a*4+0x02000000,0x33); + +//iteration +//MR11 low-DQ/high-CA ODT: 2:120 3:80 4:60 5:70 6:40 +reg_write( DDR_REG_BASE +0x5401b*4+0x02000000,0x4d64); + + + +reg_write( DDR_REG_BASE +0x5401c*4+0x02000000,0x4f08); +reg_write( DDR_REG_BASE +0x5401d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5401e*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5401f*4+0x02000000,0x2444); +reg_write( DDR_REG_BASE +0x54020*4+0x02000000,0x33); + +//iteration +//MR11 low-DQ/high-CA ODT: 2:120 3:80 4:60 5:70 6:40 +reg_write( DDR_REG_BASE +0x54021*4+0x02000000,0x4d64); + + +reg_write( DDR_REG_BASE +0x54022*4+0x02000000,0x4f08); +reg_write( DDR_REG_BASE +0x54023*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54024*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x54025*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54026*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54027*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54028*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54029*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5402a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5402b*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x5402c*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5402d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5402e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5402f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54030*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54031*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54032*4+0x02000000,0x4400); +reg_write( DDR_REG_BASE +0x54033*4+0x02000000,0x3324); + +//iteration +//MR11 low-DQ/high-CA ODT: 2:120 3:80 4:60 5:70 6:40 +reg_write( DDR_REG_BASE +0x54034*4+0x02000000,0x6400); +reg_write( DDR_REG_BASE +0x54035*4+0x02000000,0x84d); +reg_write( DDR_REG_BASE +0x54036*4+0x02000000,0x4f); +reg_write( DDR_REG_BASE +0x54037*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x54038*4+0x02000000,0x5400); +reg_write( DDR_REG_BASE +0x54039*4+0x02000000,0x332d); + +//iteration +//MR11 low-DQ/high-CA ODT: 2:120 3:80 4:60 5:70 6:40 +reg_write( DDR_REG_BASE +0x5403a*4+0x02000000,0x6400); +reg_write( DDR_REG_BASE +0x5403b*4+0x02000000,0x84d); +reg_write( DDR_REG_BASE +0x5403c*4+0x02000000,0x4f); +reg_write( DDR_REG_BASE +0x5403d*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x5403e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5403f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54040*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54041*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54042*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54043*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54044*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54045*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54046*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54047*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54048*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54049*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54050*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54051*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54052*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54053*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54054*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54055*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54056*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54057*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54058*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54059*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54060*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54061*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54062*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54063*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54064*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54065*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54066*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54067*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54068*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54069*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54070*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54071*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54072*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54073*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54074*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54075*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54076*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54077*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54078*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54079*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54080*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54081*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54082*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54083*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54084*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54085*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54086*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54087*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54088*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54089*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54090*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54091*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54092*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54093*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54094*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54095*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54096*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54097*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54098*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54099*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540aa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ab*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ad*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ae*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540af*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ba*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540bb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540bc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540bd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540be*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540bf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ca*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540cb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540cc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540cd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ce*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540cf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540da*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540db*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540dc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540dd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540de*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540df*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ea*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540eb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ec*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ed*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ef*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540fa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540fb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540fc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540fd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540fe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ff*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54100*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54101*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54102*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54103*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54104*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54105*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54106*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54107*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54108*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54109*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54110*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54111*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54112*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54113*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54114*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54115*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54116*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54117*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54118*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54119*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54120*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54121*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54122*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54123*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54124*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54125*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54126*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54127*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54128*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54129*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54130*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54131*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54132*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54133*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54134*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54135*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54136*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54137*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54138*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54139*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54140*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54141*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54142*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54143*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54144*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54145*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54146*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54147*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54148*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54149*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54150*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54151*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54152*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54153*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54154*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54155*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54156*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54157*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54158*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54159*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54160*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54161*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54162*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54163*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54164*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54165*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54166*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54167*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54168*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54169*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54170*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54171*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54172*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54173*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54174*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54175*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54176*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54177*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54178*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54179*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54180*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54181*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54182*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54183*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54184*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54185*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54186*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54187*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54188*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54189*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54190*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54191*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54192*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54193*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54194*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54195*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54196*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54197*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54198*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54199*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541aa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ab*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ad*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ae*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541af*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ba*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541bb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541bc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541bd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541be*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541bf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ca*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541cb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541cc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541cd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ce*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541cf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541da*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541db*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541dc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541dd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541de*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541df*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ea*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541eb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ec*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ed*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ef*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541fa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541fb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541fc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541fd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541fe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ff*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54200*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54201*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54202*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54203*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54204*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54205*4+0x02000000,0xff); +reg_write( DDR_REG_BASE +0x54206*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54207*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54208*4+0x02000000,0x14a); +reg_write( DDR_REG_BASE +0x54209*4+0x02000000,0x181); +reg_write( DDR_REG_BASE +0x5420a*4+0x02000000,0x118); +reg_write( DDR_REG_BASE +0x5420b*4+0x02000000,0x118); +reg_write( DDR_REG_BASE +0x5420c*4+0x02000000,0x16f); +reg_write( DDR_REG_BASE +0x5420d*4+0x02000000,0x16f); +reg_write( DDR_REG_BASE +0x5420e*4+0x02000000,0x159); +reg_write( DDR_REG_BASE +0x5420f*4+0x02000000,0x181); +reg_write( DDR_REG_BASE +0x54210*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x54211*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x54212*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54213*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54214*4+0x02000000,0x701c); +reg_write( DDR_REG_BASE +0x54215*4+0x02000000,0x61a8); +reg_write( DDR_REG_BASE +0x54216*4+0x02000000,0x35ac); +reg_write( DDR_REG_BASE +0x54217*4+0x02000000,0x35ac); +reg_write( DDR_REG_BASE +0x54218*4+0x02000000,0x125c); +reg_write( DDR_REG_BASE +0x54219*4+0x02000000,0x125c); +reg_write( DDR_REG_BASE +0x5421a*4+0x02000000,0xc738); +reg_write( DDR_REG_BASE +0x5421b*4+0x02000000,0xb0f4); +reg_write( DDR_REG_BASE +0x5421c*4+0x02000000,0x6590); +reg_write( DDR_REG_BASE +0x5421d*4+0x02000000,0x6590); +reg_write( DDR_REG_BASE +0x5421e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5421f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54220*4+0x02000000,0x9f38); +reg_write( DDR_REG_BASE +0x54221*4+0x02000000,0x58); +reg_write( DDR_REG_BASE +0x54222*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54223*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54224*4+0x02000000,0x2820); +reg_write( DDR_REG_BASE +0x54225*4+0x02000000,0x140f); +reg_write( DDR_REG_BASE +0x54226*4+0x02000000,0x1f02); +reg_write( DDR_REG_BASE +0x54227*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54228*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54229*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x5422a*4+0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x5422b*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5422c*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x5422d*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5422e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5422f*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x54230*4+0x02000000,0x1f4); +reg_write( DDR_REG_BASE +0x54231*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54232*4+0x02000000,0xb900); +reg_write( DDR_REG_BASE +0x54233*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54234*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54235*4+0x02000000,0xba00); +reg_write( DDR_REG_BASE +0x54236*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54237*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54238*4+0x02000000,0xbb00); +reg_write( DDR_REG_BASE +0x54239*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5423a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5423b*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5423c*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5423d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5423e*4+0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x5423f*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54240*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54241*4+0x02000000,0xf900); +reg_write( DDR_REG_BASE +0x54242*4+0x02000000,0x4f0); +reg_write( DDR_REG_BASE +0x54243*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54244*4+0x02000000,0xfa02); +reg_write( DDR_REG_BASE +0x54245*4+0x02000000,0x4f0); +reg_write( DDR_REG_BASE +0x54246*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54247*4+0x02000000,0xfb00); +reg_write( DDR_REG_BASE +0x54248*4+0x02000000,0x4f0); +reg_write( DDR_REG_BASE +0x54249*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5424a*4+0x02000000,0x6004); +reg_write( DDR_REG_BASE +0x5424b*4+0x02000000,0x7f0); +reg_write( DDR_REG_BASE +0x5424c*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x5424d*4+0x02000000,0x6500); +reg_write( DDR_REG_BASE +0x5424e*4+0x02000000,0x7f0); +reg_write( DDR_REG_BASE +0x5424f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54250*4+0x02000000,0x6200); +reg_write( DDR_REG_BASE +0x54251*4+0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x54252*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54253*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x54254*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54255*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x54256*4+0x02000000,0x1f02); +reg_write( DDR_REG_BASE +0x54257*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54258*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54259*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x5425a*4+0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x5425b*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5425c*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x5425d*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5425e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5425f*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x54260*4+0x02000000,0x1f4); +reg_write( DDR_REG_BASE +0x54261*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54262*4+0x02000000,0xb900); +reg_write( DDR_REG_BASE +0x54263*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54264*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54265*4+0x02000000,0xba00); +reg_write( DDR_REG_BASE +0x54266*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54267*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54268*4+0x02000000,0xbb00); +reg_write( DDR_REG_BASE +0x54269*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5426a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5426b*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5426c*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5426d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5426e*4+0x02000000,0x1100); +reg_write( DDR_REG_BASE +0x5426f*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54270*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x54271*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x54272*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54273*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54274*4+0x02000000,0x18f0); +reg_write( DDR_REG_BASE +0x54275*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54276*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x54277*4+0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x54278*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54279*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5427a*4+0x02000000,0xf900); +reg_write( DDR_REG_BASE +0x5427b*4+0x02000000,0x4f0); +reg_write( DDR_REG_BASE +0x5427c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5427d*4+0x02000000,0xfa02); +reg_write( DDR_REG_BASE +0x5427e*4+0x02000000,0x4f0); +reg_write( DDR_REG_BASE +0x5427f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54280*4+0x02000000,0xfb00); +reg_write( DDR_REG_BASE +0x54281*4+0x02000000,0x4f0); +reg_write( DDR_REG_BASE +0x54282*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54283*4+0x02000000,0x6204); +reg_write( DDR_REG_BASE +0x54284*4+0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x54285*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54286*4+0x02000000,0x6200); +reg_write( DDR_REG_BASE +0x54287*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54288*4+0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x54289*4+0x02000000,0x6200); +reg_write( DDR_REG_BASE +0x5428a*4+0x02000000,0x1f4); +reg_write( DDR_REG_BASE +0x5428b*4+0x02000000,0xf000); +reg_write( DDR_REG_BASE +0x5428c*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x5428d*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5428e*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x5428f*4+0x02000000,0x1f02); +reg_write( DDR_REG_BASE +0x54290*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54291*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54292*4+0x02000000,0x3b00); +reg_write( DDR_REG_BASE +0x54293*4+0x02000000,0x2f0); +reg_write( DDR_REG_BASE +0x54294*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x54295*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x54296*4+0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x54297*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54298*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x54299*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5429a*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5429b*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x5429c*4+0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x5429d*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5429e*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x5429f*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542a0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542a1*4+0x02000000,0xb900); +reg_write( DDR_REG_BASE +0x542a2*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542a3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542a4*4+0x02000000,0xba00); +reg_write( DDR_REG_BASE +0x542a5*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542a6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542a7*4+0x02000000,0xbb00); +reg_write( DDR_REG_BASE +0x542a8*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542a9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542aa*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542ab*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542ac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542ad*4+0x02000000,0x6000); +reg_write( DDR_REG_BASE +0x542ae*4+0x02000000,0x7f0); +reg_write( DDR_REG_BASE +0x542af*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542b0*4+0x02000000,0x6500); +reg_write( DDR_REG_BASE +0x542b1*4+0x02000000,0x7f0); +reg_write( DDR_REG_BASE +0x542b2*4+0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x542b3*4+0x02000000,0x2601); +reg_write( DDR_REG_BASE +0x542b4*4+0x02000000,0x7ff); +reg_write( DDR_REG_BASE +0x542b5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542b6*4+0x02000000,0x2700); +reg_write( DDR_REG_BASE +0x542b7*4+0x02000000,0x7ff); +reg_write( DDR_REG_BASE +0x542b8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542b9*4+0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x542ba*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542bb*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x542bc*4+0x02000000,0x3200); +reg_write( DDR_REG_BASE +0x542bd*4+0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x542be*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542bf*4+0x02000000,0x6208); +reg_write( DDR_REG_BASE +0x542c0*4+0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x542c1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542c2*4+0x02000000,0x6200); +reg_write( DDR_REG_BASE +0x542c3*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542c4*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542c5*4+0x02000000,0x6200); +reg_write( DDR_REG_BASE +0x542c6*4+0x02000000,0x1f4); +reg_write( DDR_REG_BASE +0x542c7*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542c8*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x542c9*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542ca*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x542cb*4+0x02000000,0x1f02); +reg_write( DDR_REG_BASE +0x542cc*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542cd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542ce*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x542cf*4+0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x542d0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542d1*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x542d2*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542d3*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542d4*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x542d5*4+0x02000000,0x1f4); +reg_write( DDR_REG_BASE +0x542d6*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542d7*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x542d8*4+0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x542d9*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542da*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x542db*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542dc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542dd*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x542de*4+0x02000000,0x1f4); +reg_write( DDR_REG_BASE +0x542df*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542e0*4+0x02000000,0xb900); +reg_write( DDR_REG_BASE +0x542e1*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542e2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542e3*4+0x02000000,0xba00); +reg_write( DDR_REG_BASE +0x542e4*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542e5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542e6*4+0x02000000,0xbb00); +reg_write( DDR_REG_BASE +0x542e7*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542e8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542e9*4+0x02000000,0x1100); +reg_write( DDR_REG_BASE +0x542ea*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542eb*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542ec*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x542ed*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542ee*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542ef*4+0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x542f0*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542f1*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x542f2*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x542f3*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542f4*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542f5*4+0x02000000,0x6000); +reg_write( DDR_REG_BASE +0x542f6*4+0x02000000,0x7f0); +reg_write( DDR_REG_BASE +0x542f7*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542f8*4+0x02000000,0x6500); +reg_write( DDR_REG_BASE +0x542f9*4+0x02000000,0x7f0); +reg_write( DDR_REG_BASE +0x542fa*4+0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x542fb*4+0x02000000,0x2601); +reg_write( DDR_REG_BASE +0x542fc*4+0x02000000,0x7ff); +reg_write( DDR_REG_BASE +0x542fd*4+0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x542fe*4+0x02000000,0x27ff); +reg_write( DDR_REG_BASE +0x542ff*4+0x02000000,0x7ff); +reg_write( DDR_REG_BASE +0x54300*4+0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x54301*4+0x02000000,0x62ff); +reg_write( DDR_REG_BASE +0x54302*4+0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x54303*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54304*4+0x02000000,0x6200); +reg_write( DDR_REG_BASE +0x54305*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54306*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x54307*4+0x02000000,0x6200); +reg_write( DDR_REG_BASE +0x54308*4+0x02000000,0x1f4); +reg_write( DDR_REG_BASE +0x54309*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x5430a*4+0x02000000,0x3200); +reg_write( DDR_REG_BASE +0x5430b*4+0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x5430c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5430d*4+0x02000000,0x208); +reg_write( DDR_REG_BASE +0x5430e*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5430f*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x54310*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x54311*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54312*4+0x02000000,0x20d); +reg_write( DDR_REG_BASE +0x54313*4+0x02000000,0x301); +reg_write( DDR_REG_BASE +0x54314*4+0x02000000,0xc0b); +reg_write( DDR_REG_BASE +0x54315*4+0x02000000,0x160e); +reg_write( DDR_REG_BASE +0x54316*4+0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x54317*4+0x02000000,0x1811); +reg_write( DDR_REG_BASE +0x54318*4+0x02000000,0xc06); +reg_write( DDR_REG_BASE +0x54319*4+0x02000000,0x1610); +reg_write( DDR_REG_BASE +0x5431a*4+0x02000000,0x201c); +reg_write( DDR_REG_BASE +0x5431b*4+0x02000000,0x2824); +reg_write( DDR_REG_BASE +0x5431c*4+0x02000000,0xc06); +reg_write( DDR_REG_BASE +0x5431d*4+0x02000000,0x1812); +reg_write( DDR_REG_BASE +0x5431e*4+0x02000000,0x241e); +reg_write( DDR_REG_BASE +0x5431f*4+0x02000000,0x2c28); +reg_write( DDR_REG_BASE +0x54320*4+0x02000000,0xa06); +reg_write( DDR_REG_BASE +0x54321*4+0x02000000,0x140e); +reg_write( DDR_REG_BASE +0x54322*4+0x02000000,0x1c18); +reg_write( DDR_REG_BASE +0x54323*4+0x02000000,0x2420); +reg_write( DDR_REG_BASE +0x54324*4+0x02000000,0xa06); +reg_write( DDR_REG_BASE +0x54325*4+0x02000000,0x1610); +reg_write( DDR_REG_BASE +0x54326*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x54327*4+0x02000000,0x2824); +reg_write( DDR_REG_BASE +0x54328*4+0x02000000,0x6e); +reg_write( DDR_REG_BASE +0x54329*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x5432a*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5432b*4+0x02000000,0xfd); +reg_write( DDR_REG_BASE +0x5432c*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5432d*4+0x02000000,0xf); +reg_write( DDR_REG_BASE +0x5432e*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5432f*4+0x02000000,0x7); +reg_write( DDR_REG_BASE +0x54330*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54331*4+0x02000000,0xe8); +reg_write( DDR_REG_BASE +0x54332*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x54333*4+0x02000000,0xff); +reg_write( DDR_REG_BASE +0x54334*4+0x02000000,0xfc); +reg_write( DDR_REG_BASE +0x54335*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x54336*4+0x02000000,0x404); +reg_write( DDR_REG_BASE +0x54337*4+0x02000000,0x3a); +reg_write( DDR_REG_BASE +0x54338*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x54339*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x5433a*4+0x02000000,0x11); +reg_write( DDR_REG_BASE +0x5433b*4+0x02000000,0x7); +reg_write( DDR_REG_BASE +0x5433c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5433d*4+0x02000000,0x0); + +reg_write( DDR_REG_BASE + 0xd0000*4+0x02000000,0x1); + + +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000d0099*4 +0x02000000 , 0x00000009 ); +reg_write( DDR_REG_BASE + 0x000d0099*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000d0099*4 +0x02000000 , 0x00000000 ); + + + + + +while((train_data&0x7) !=0x07) { + + reg_read ( DDR_REG_BASE + 0x000d0004*4 +0x02000000 , data ); + while((data&0x1) !=0x0) { + reg_read ( DDR_REG_BASE + 0x000d0004*4 +0x02000000 , data ); + } + + + + reg_read ( DDR_REG_BASE + 0x000d0032*4 +0x02000000 , train_data ); + switch(train_data) + { + case 0x00000000: printf("%08X: PMU Major Msg: End of initialization \n",train_data);break; + case 0x00000001: printf("%08X: PMU Major Msg: End of fine write leveling \n",train_data);break; + case 0x00000002: printf("%08X: PMU Major Msg: End of read enable training \n",train_data);break; + case 0x00000003: printf("%08X: PMU Major Msg: End of read delay center optimization \n",train_data);break; + case 0x00000004: printf("%08X: PMU Major Msg: End of write delay center optimization \n",train_data);break; + case 0x00000005: printf("%08X: PMU Major Msg: End of 2D read delay/voltage center optimization \n",train_data);break; + case 0x00000006: printf("%08X: PMU Major Msg: End of 2D write delay /voltage center optimization \n",train_data);break; + case 0x00000007: + { + unsigned long add,i=0; + printf("%08X: PMU Major Msg: Firmware run has completed \n",train_data); + // add = DDR_REG_BASE +0x5401b*4+0x02000000; printf("MR12-CA add =%lx value =%lx\n",add,readl(add)); + // add = DDR_REG_BASE +0x5401c*4+0x02000000; printf("MR14-DQ add =%lx value =%lx\n",add,readl(add)); + // for(i=0;i<8;i++) + // {add = DDR_REG_BASE + 0x00010040*4+0x02000000+i*0x100; printf("dbyte0 add =%lx value =%lx\n",add,readl(add));} + // //add = DDR_REG_BASE + 0x00010140*4+0x02000000; printf("add =%lx value =%lx\n",add,readl(add)); + // for(i=0;i<8;i++) + // {add = DDR_REG_BASE + 0x00011140*4+0x02000000+i*0x100; printf("dbyte1 add =%lx value =%lx\n",add,readl(add));} + // for(i=0;i<8;i++) + // {add = DDR_REG_BASE + 0x00012140*4+0x02000000+i*0x100; printf("dbyte2 add =%lx value =%lx\n",add,readl(add));} + // for(i=0;i<8;i++) + // {add = DDR_REG_BASE + 0x00013140*4+0x02000000+i*0x100; printf("dbyte3 add =%lx value =%lx\n",add,readl(add)); } + } + break; + case 0x00000008: printf("%08X: PMU Major Msg: Enter streaming message mode \n",train_data);break; + case 0x00000009: printf("%08X: PMU Major Msg: End of max read latency training \n",train_data);break; + case 0x0000000a: printf("%08X: PMU Major Msg: End of read dq deskew training \n",train_data);break; + case 0x0000000b: printf("%08X: PMU Major Msg: End of LCDL offset calibration \n",train_data);break; + case 0x0000000c: printf("%08X: PMU Major Msg: End of LRDIMM Specific training (DWL, MREP, MRD and MWD) \n",train_data);break; + case 0x0000000d: printf("%08X: PMU Major Msg: End of CA training \n",train_data);break; + case 0x000000fd: printf("%08X: PMU Major Msg: End of MPR read delay center optimization \n",train_data);break; + case 0x000000fe: printf("%08X: PMU Major Msg: End of Write leveling coarse delay \n",train_data);break; + case 0x000000ff: printf("%08X: PMU Major Msg: FATAL ERROR. \n",train_data);break; + default: printf("%08X: PMU Major Msg: Un-recognized message... ! \n",train_data);break; + } + + + reg_write( DDR_REG_BASE + 0x000d0031*4 +0x02000000 , 0x00000000 ); + reg_read ( DDR_REG_BASE + 0x000d0004*4 +0x02000000 , data ); + while((data&0x1) ==0x0) { + reg_read ( DDR_REG_BASE + 0x000d0004*4 +0x02000000 , data ); + } + reg_write( DDR_REG_BASE + 0x000d0031*4 +0x02000000 , 0x00000001 ); + +} + +train_data=0; + + +reg_write( DDR_REG_BASE + 0x000d0099*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000000 ); +//reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000001 ); + + + +//////////////////////////////2d training begin////////////////////// + +//lp4_ddr2667_2d(); + +///////////////////////////2d training end/////////////////////////////////////////// +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000000 ); + +reg_write( DDR_REG_BASE + 0x00090000*4+0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x00090001*4+0x02000000 , 0x00000400 ); +reg_write( DDR_REG_BASE + 0x00090002*4+0x02000000 , 0x0000010e ); +reg_write( DDR_REG_BASE + 0x00090003*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090004*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090005*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090029*4+0x02000000 , 0x0000000b ); +reg_write( DDR_REG_BASE + 0x0009002a*4+0x02000000 , 0x00000480 ); +reg_write( DDR_REG_BASE + 0x0009002b*4+0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009002c*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x0009002d*4+0x02000000 , 0x00000448 ); +reg_write( DDR_REG_BASE + 0x0009002e*4+0x02000000 , 0x00000139 ); +reg_write( DDR_REG_BASE + 0x0009002f*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090030*4+0x02000000 , 0x00000478 ); +reg_write( DDR_REG_BASE + 0x00090031*4+0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090032*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090033*4+0x02000000 , 0x000000e8 ); +reg_write( DDR_REG_BASE + 0x00090034*4+0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090035*4+0x02000000 , 0x00000002 ); +reg_write( DDR_REG_BASE + 0x00090036*4+0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x00090037*4+0x02000000 , 0x00000139 ); +reg_write( DDR_REG_BASE + 0x00090038*4+0x02000000 , 0x0000000b ); +reg_write( DDR_REG_BASE + 0x00090039*4+0x02000000 , 0x000007c0 ); +reg_write( DDR_REG_BASE + 0x0009003a*4+0x02000000 , 0x00000139 ); +reg_write( DDR_REG_BASE + 0x0009003b*4+0x02000000 , 0x00000044 ); +reg_write( DDR_REG_BASE + 0x0009003c*4+0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x0009003d*4+0x02000000 , 0x00000159 ); +reg_write( DDR_REG_BASE + 0x0009003e*4+0x02000000 , 0x0000014f ); +reg_write( DDR_REG_BASE + 0x0009003f*4+0x02000000 , 0x00000630 ); +reg_write( DDR_REG_BASE + 0x00090040*4+0x02000000 , 0x00000159 ); +reg_write( DDR_REG_BASE + 0x00090041*4+0x02000000 , 0x00000047 ); +reg_write( DDR_REG_BASE + 0x00090042*4+0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090043*4+0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x00090044*4+0x02000000 , 0x0000004f ); +reg_write( DDR_REG_BASE + 0x00090045*4+0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090046*4+0x02000000 , 0x00000179 ); +reg_write( DDR_REG_BASE + 0x00090047*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090048*4+0x02000000 , 0x000000e0 ); +reg_write( DDR_REG_BASE + 0x00090049*4+0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009004a*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009004b*4+0x02000000 , 0x000007c8 ); +reg_write( DDR_REG_BASE + 0x0009004c*4+0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009004d*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009004e*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x0009004f*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090050*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090051*4+0x02000000 , 0x0000045a ); +reg_write( DDR_REG_BASE + 0x00090052*4+0x02000000 , 0x00000009 ); +reg_write( DDR_REG_BASE + 0x00090053*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090054*4+0x02000000 , 0x00000448 ); +reg_write( DDR_REG_BASE + 0x00090055*4+0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090056*4+0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x00090057*4+0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090058*4+0x02000000 , 0x00000179 ); +reg_write( DDR_REG_BASE + 0x00090059*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x0009005a*4+0x02000000 , 0x00000618 ); +reg_write( DDR_REG_BASE + 0x0009005b*4+0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009005c*4+0x02000000 , 0x000040c0 ); +reg_write( DDR_REG_BASE + 0x0009005d*4+0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x0009005e*4+0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x0009005f*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090060*4+0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00090061*4+0x02000000 , 0x00000048 ); +reg_write( DDR_REG_BASE + 0x00090062*4+0x02000000 , 0x00004040 ); +reg_write( DDR_REG_BASE + 0x00090063*4+0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090064*4+0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x00090065*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090066*4+0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00090067*4+0x02000000 , 0x00000048 ); +reg_write( DDR_REG_BASE + 0x00090068*4+0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x00090069*4+0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x0009006a*4+0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x0009006b*4+0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x0009006c*4+0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x0009006d*4+0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x0009006e*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009006f*4+0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00090070*4+0x02000000 , 0x00000078 ); +reg_write( DDR_REG_BASE + 0x00090071*4+0x02000000 , 0x00000549 ); +reg_write( DDR_REG_BASE + 0x00090072*4+0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090073*4+0x02000000 , 0x00000159 ); +reg_write( DDR_REG_BASE + 0x00090074*4+0x02000000 , 0x00000d49 ); +reg_write( DDR_REG_BASE + 0x00090075*4+0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090076*4+0x02000000 , 0x00000159 ); +reg_write( DDR_REG_BASE + 0x00090077*4+0x02000000 , 0x0000094a ); +reg_write( DDR_REG_BASE + 0x00090078*4+0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090079*4+0x02000000 , 0x00000159 ); +reg_write( DDR_REG_BASE + 0x0009007a*4+0x02000000 , 0x00000441 ); +reg_write( DDR_REG_BASE + 0x0009007b*4+0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x0009007c*4+0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x0009007d*4+0x02000000 , 0x00000042 ); +reg_write( DDR_REG_BASE + 0x0009007e*4+0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x0009007f*4+0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x00090080*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00090081*4+0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090082*4+0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x00090083*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090084*4+0x02000000 , 0x000000e0 ); +reg_write( DDR_REG_BASE + 0x00090085*4+0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090086*4+0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x00090087*4+0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x00090088*4+0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090089*4+0x02000000 , 0x00000009 ); +reg_write( DDR_REG_BASE + 0x0009008a*4+0x02000000 , 0x000003c0 ); +reg_write( DDR_REG_BASE + 0x0009008b*4+0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x0009008c*4+0x02000000 , 0x00000009 ); +reg_write( DDR_REG_BASE + 0x0009008d*4+0x02000000 , 0x000003c0 ); +reg_write( DDR_REG_BASE + 0x0009008e*4+0x02000000 , 0x00000159 ); +reg_write( DDR_REG_BASE + 0x0009008f*4+0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x00090090*4+0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x00090091*4+0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090092*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090093*4+0x02000000 , 0x000003c0 ); +reg_write( DDR_REG_BASE + 0x00090094*4+0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090095*4+0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x00090096*4+0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00090097*4+0x02000000 , 0x00000048 ); +reg_write( DDR_REG_BASE + 0x00090098*4+0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x00090099*4+0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x0009009a*4+0x02000000 , 0x00000058 ); +reg_write( DDR_REG_BASE + 0x0009009b*4+0x02000000 , 0x0000000b ); +reg_write( DDR_REG_BASE + 0x0009009c*4+0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x0009009d*4+0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009009e*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x0009009f*4+0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000900a0*4+0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x000900a1*4+0x02000000 , 0x00000005 ); +reg_write( DDR_REG_BASE + 0x000900a2*4+0x02000000 , 0x000007c0 ); +reg_write( DDR_REG_BASE + 0x000900a3*4+0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00040000*4+0x02000000 , 0x00000811 ); +reg_write( DDR_REG_BASE + 0x00040020*4+0x02000000 , 0x00000880 ); +reg_write( DDR_REG_BASE + 0x00040040*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040060*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040001*4+0x02000000 , 0x00004008 ); +reg_write( DDR_REG_BASE + 0x00040021*4+0x02000000 , 0x00000083 ); +reg_write( DDR_REG_BASE + 0x00040041*4+0x02000000 , 0x0000004f ); +reg_write( DDR_REG_BASE + 0x00040061*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040002*4+0x02000000 , 0x00004040 ); +reg_write( DDR_REG_BASE + 0x00040022*4+0x02000000 , 0x00000083 ); +reg_write( DDR_REG_BASE + 0x00040042*4+0x02000000 , 0x00000051 ); +reg_write( DDR_REG_BASE + 0x00040062*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040003*4+0x02000000 , 0x00000811 ); +reg_write( DDR_REG_BASE + 0x00040023*4+0x02000000 , 0x00000880 ); +reg_write( DDR_REG_BASE + 0x00040043*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040063*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040004*4+0x02000000 , 0x00000720 ); +reg_write( DDR_REG_BASE + 0x00040024*4+0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00040044*4+0x02000000 , 0x00001740 ); +reg_write( DDR_REG_BASE + 0x00040064*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040005*4+0x02000000 , 0x00000016 ); +reg_write( DDR_REG_BASE + 0x00040025*4+0x02000000 , 0x00000083 ); +reg_write( DDR_REG_BASE + 0x00040045*4+0x02000000 , 0x0000004b ); +reg_write( DDR_REG_BASE + 0x00040065*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040006*4+0x02000000 , 0x00000716 ); +reg_write( DDR_REG_BASE + 0x00040026*4+0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00040046*4+0x02000000 , 0x00002001 ); +reg_write( DDR_REG_BASE + 0x00040066*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040007*4+0x02000000 , 0x00000716 ); +reg_write( DDR_REG_BASE + 0x00040027*4+0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00040047*4+0x02000000 , 0x00002800 ); +reg_write( DDR_REG_BASE + 0x00040067*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040008*4+0x02000000 , 0x00000716 ); +reg_write( DDR_REG_BASE + 0x00040028*4+0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00040048*4+0x02000000 , 0x00000f00 ); +reg_write( DDR_REG_BASE + 0x00040068*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040009*4+0x02000000 , 0x00000720 ); +reg_write( DDR_REG_BASE + 0x00040029*4+0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00040049*4+0x02000000 , 0x00001400 ); +reg_write( DDR_REG_BASE + 0x00040069*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004000a*4+0x02000000 , 0x00000e08 ); +reg_write( DDR_REG_BASE + 0x0004002a*4+0x02000000 , 0x00000c15 ); +reg_write( DDR_REG_BASE + 0x0004004a*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004006a*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004000b*4+0x02000000 , 0x00000625 ); +reg_write( DDR_REG_BASE + 0x0004002b*4+0x02000000 , 0x00000015 ); +reg_write( DDR_REG_BASE + 0x0004004b*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004006b*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004000c*4+0x02000000 , 0x00004028 ); +reg_write( DDR_REG_BASE + 0x0004002c*4+0x02000000 , 0x00000080 ); +reg_write( DDR_REG_BASE + 0x0004004c*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004006c*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004000d*4+0x02000000 , 0x00000e08 ); +reg_write( DDR_REG_BASE + 0x0004002d*4+0x02000000 , 0x00000c1a ); +reg_write( DDR_REG_BASE + 0x0004004d*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004006d*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004000e*4+0x02000000 , 0x00000625 ); +reg_write( DDR_REG_BASE + 0x0004002e*4+0x02000000 , 0x0000001a ); +reg_write( DDR_REG_BASE + 0x0004004e*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004006e*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004000f*4+0x02000000 , 0x00004040 ); +reg_write( DDR_REG_BASE + 0x0004002f*4+0x02000000 , 0x00000080 ); +reg_write( DDR_REG_BASE + 0x0004004f*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004006f*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040010*4+0x02000000 , 0x00002604 ); +reg_write( DDR_REG_BASE + 0x00040030*4+0x02000000 , 0x00000015 ); +reg_write( DDR_REG_BASE + 0x00040050*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040070*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040011*4+0x02000000 , 0x00000708 ); +reg_write( DDR_REG_BASE + 0x00040031*4+0x02000000 , 0x00000005 ); +reg_write( DDR_REG_BASE + 0x00040051*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040071*4+0x02000000 , 0x00002002 ); +reg_write( DDR_REG_BASE + 0x00040012*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00040032*4+0x02000000 , 0x00000080 ); +reg_write( DDR_REG_BASE + 0x00040052*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040072*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040013*4+0x02000000 , 0x00002604 ); +reg_write( DDR_REG_BASE + 0x00040033*4+0x02000000 , 0x0000001a ); +reg_write( DDR_REG_BASE + 0x00040053*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040073*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040014*4+0x02000000 , 0x00000708 ); +reg_write( DDR_REG_BASE + 0x00040034*4+0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x00040054*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040074*4+0x02000000 , 0x00002002 ); +reg_write( DDR_REG_BASE + 0x00040015*4+0x02000000 , 0x00004040 ); +reg_write( DDR_REG_BASE + 0x00040035*4+0x02000000 , 0x00000080 ); +reg_write( DDR_REG_BASE + 0x00040055*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040075*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040016*4+0x02000000 , 0x0000060a ); +reg_write( DDR_REG_BASE + 0x00040036*4+0x02000000 , 0x00000015 ); +reg_write( DDR_REG_BASE + 0x00040056*4+0x02000000 , 0x00001200 ); +reg_write( DDR_REG_BASE + 0x00040076*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040017*4+0x02000000 , 0x0000061a ); +reg_write( DDR_REG_BASE + 0x00040037*4+0x02000000 , 0x00000015 ); +reg_write( DDR_REG_BASE + 0x00040057*4+0x02000000 , 0x00001300 ); +reg_write( DDR_REG_BASE + 0x00040077*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040018*4+0x02000000 , 0x0000060a ); +reg_write( DDR_REG_BASE + 0x00040038*4+0x02000000 , 0x0000001a ); +reg_write( DDR_REG_BASE + 0x00040058*4+0x02000000 , 0x00001200 ); +reg_write( DDR_REG_BASE + 0x00040078*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040019*4+0x02000000 , 0x00000642 ); +reg_write( DDR_REG_BASE + 0x00040039*4+0x02000000 , 0x0000001a ); +reg_write( DDR_REG_BASE + 0x00040059*4+0x02000000 , 0x00001300 ); +reg_write( DDR_REG_BASE + 0x00040079*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004001a*4+0x02000000 , 0x00004808 ); +reg_write( DDR_REG_BASE + 0x0004003a*4+0x02000000 , 0x00000880 ); +reg_write( DDR_REG_BASE + 0x0004005a*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004007a*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900a4*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900a5*4+0x02000000 , 0x00000790 ); +reg_write( DDR_REG_BASE + 0x000900a6*4+0x02000000 , 0x0000011a ); +reg_write( DDR_REG_BASE + 0x000900a7*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900a8*4+0x02000000 , 0x000007aa ); +reg_write( DDR_REG_BASE + 0x000900a9*4+0x02000000 , 0x0000002a ); +reg_write( DDR_REG_BASE + 0x000900aa*4+0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000900ab*4+0x02000000 , 0x000007b2 ); +reg_write( DDR_REG_BASE + 0x000900ac*4+0x02000000 , 0x0000002a ); +reg_write( DDR_REG_BASE + 0x000900ad*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900ae*4+0x02000000 , 0x000007c8 ); +reg_write( DDR_REG_BASE + 0x000900af*4+0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x000900b0*4+0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000900b1*4+0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000900b2*4+0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x000900b3*4+0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000900b4*4+0x02000000 , 0x000002a8 ); +reg_write( DDR_REG_BASE + 0x000900b5*4+0x02000000 , 0x00000129 ); +reg_write( DDR_REG_BASE + 0x000900b6*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900b7*4+0x02000000 , 0x00000370 ); +reg_write( DDR_REG_BASE + 0x000900b8*4+0x02000000 , 0x00000129 ); +reg_write( DDR_REG_BASE + 0x000900b9*4+0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x000900ba*4+0x02000000 , 0x000003c8 ); +reg_write( DDR_REG_BASE + 0x000900bb*4+0x02000000 , 0x000001a9 ); +reg_write( DDR_REG_BASE + 0x000900bc*4+0x02000000 , 0x0000000c ); +reg_write( DDR_REG_BASE + 0x000900bd*4+0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x000900be*4+0x02000000 , 0x00000199 ); +reg_write( DDR_REG_BASE + 0x000900bf*4+0x02000000 , 0x00000014 ); +reg_write( DDR_REG_BASE + 0x000900c0*4+0x02000000 , 0x00000790 ); +reg_write( DDR_REG_BASE + 0x000900c1*4+0x02000000 , 0x0000011a ); +reg_write( DDR_REG_BASE + 0x000900c2*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900c3*4+0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x000900c4*4+0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x000900c5*4+0x02000000 , 0x0000000e ); +reg_write( DDR_REG_BASE + 0x000900c6*4+0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x000900c7*4+0x02000000 , 0x00000199 ); +reg_write( DDR_REG_BASE + 0x000900c8*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900c9*4+0x02000000 , 0x00008568 ); +reg_write( DDR_REG_BASE + 0x000900ca*4+0x02000000 , 0x00000108 ); +reg_write( DDR_REG_BASE + 0x000900cb*4+0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x000900cc*4+0x02000000 , 0x00000790 ); +reg_write( DDR_REG_BASE + 0x000900cd*4+0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x000900ce*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900cf*4+0x02000000 , 0x000001d8 ); +reg_write( DDR_REG_BASE + 0x000900d0*4+0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x000900d1*4+0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000900d2*4+0x02000000 , 0x00008558 ); +reg_write( DDR_REG_BASE + 0x000900d3*4+0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x000900d4*4+0x02000000 , 0x00000070 ); +reg_write( DDR_REG_BASE + 0x000900d5*4+0x02000000 , 0x00000788 ); +reg_write( DDR_REG_BASE + 0x000900d6*4+0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x000900d7*4+0x02000000 , 0x00001ff8 ); +reg_write( DDR_REG_BASE + 0x000900d8*4+0x02000000 , 0x000085a8 ); +reg_write( DDR_REG_BASE + 0x000900d9*4+0x02000000 , 0x000001e8 ); +reg_write( DDR_REG_BASE + 0x000900da*4+0x02000000 , 0x00000050 ); +reg_write( DDR_REG_BASE + 0x000900db*4+0x02000000 , 0x00000798 ); +reg_write( DDR_REG_BASE + 0x000900dc*4+0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x000900dd*4+0x02000000 , 0x00000060 ); +reg_write( DDR_REG_BASE + 0x000900de*4+0x02000000 , 0x000007a0 ); +reg_write( DDR_REG_BASE + 0x000900df*4+0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x000900e0*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900e1*4+0x02000000 , 0x00008310 ); +reg_write( DDR_REG_BASE + 0x000900e2*4+0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x000900e3*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900e4*4+0x02000000 , 0x0000a310 ); +reg_write( DDR_REG_BASE + 0x000900e5*4+0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x000900e6*4+0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x000900e7*4+0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x000900e8*4+0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x000900e9*4+0x02000000 , 0x0000006e ); +reg_write( DDR_REG_BASE + 0x000900ea*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900eb*4+0x02000000 , 0x00000068 ); +reg_write( DDR_REG_BASE + 0x000900ec*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900ed*4+0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x000900ee*4+0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x000900ef*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900f0*4+0x02000000 , 0x00008310 ); +reg_write( DDR_REG_BASE + 0x000900f1*4+0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x000900f2*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900f3*4+0x02000000 , 0x0000a310 ); +reg_write( DDR_REG_BASE + 0x000900f4*4+0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x000900f5*4+0x02000000 , 0x00001ff8 ); +reg_write( DDR_REG_BASE + 0x000900f6*4+0x02000000 , 0x000085a8 ); +reg_write( DDR_REG_BASE + 0x000900f7*4+0x02000000 , 0x000001e8 ); +reg_write( DDR_REG_BASE + 0x000900f8*4+0x02000000 , 0x00000068 ); +reg_write( DDR_REG_BASE + 0x000900f9*4+0x02000000 , 0x00000798 ); +reg_write( DDR_REG_BASE + 0x000900fa*4+0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x000900fb*4+0x02000000 , 0x00000078 ); +reg_write( DDR_REG_BASE + 0x000900fc*4+0x02000000 , 0x000007a0 ); +reg_write( DDR_REG_BASE + 0x000900fd*4+0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x000900fe*4+0x02000000 , 0x00000068 ); +reg_write( DDR_REG_BASE + 0x000900ff*4+0x02000000 , 0x00000790 ); +reg_write( DDR_REG_BASE + 0x00090100*4+0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x00090101*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090102*4+0x02000000 , 0x00008b10 ); +reg_write( DDR_REG_BASE + 0x00090103*4+0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x00090104*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090105*4+0x02000000 , 0x0000ab10 ); +reg_write( DDR_REG_BASE + 0x00090106*4+0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x00090107*4+0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x00090108*4+0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x00090109*4+0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x0009010a*4+0x02000000 , 0x00000058 ); +reg_write( DDR_REG_BASE + 0x0009010b*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009010c*4+0x02000000 , 0x00000068 ); +reg_write( DDR_REG_BASE + 0x0009010d*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009010e*4+0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x0009010f*4+0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x00090110*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090111*4+0x02000000 , 0x00008b10 ); +reg_write( DDR_REG_BASE + 0x00090112*4+0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x00090113*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00090114*4+0x02000000 , 0x0000ab10 ); +reg_write( DDR_REG_BASE + 0x00090115*4+0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x00090116*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090117*4+0x02000000 , 0x000001d8 ); +reg_write( DDR_REG_BASE + 0x00090118*4+0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x00090119*4+0x02000000 , 0x00000080 ); +reg_write( DDR_REG_BASE + 0x0009011a*4+0x02000000 , 0x00000790 ); +reg_write( DDR_REG_BASE + 0x0009011b*4+0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x0009011c*4+0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x0009011d*4+0x02000000 , 0x000007aa ); +reg_write( DDR_REG_BASE + 0x0009011e*4+0x02000000 , 0x0000006a ); +reg_write( DDR_REG_BASE + 0x0009011f*4+0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x00090120*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090121*4+0x02000000 , 0x000001e9 ); +reg_write( DDR_REG_BASE + 0x00090122*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090123*4+0x02000000 , 0x00008080 ); +reg_write( DDR_REG_BASE + 0x00090124*4+0x02000000 , 0x00000108 ); +reg_write( DDR_REG_BASE + 0x00090125*4+0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00090126*4+0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x00090127*4+0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x00090128*4+0x02000000 , 0x0000000c ); +reg_write( DDR_REG_BASE + 0x00090129*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009012a*4+0x02000000 , 0x00000068 ); +reg_write( DDR_REG_BASE + 0x0009012b*4+0x02000000 , 0x00000009 ); +reg_write( DDR_REG_BASE + 0x0009012c*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009012d*4+0x02000000 , 0x000001a9 ); +reg_write( DDR_REG_BASE + 0x0009012e*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009012f*4+0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x00090130*4+0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x00090131*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090132*4+0x02000000 , 0x00008080 ); +reg_write( DDR_REG_BASE + 0x00090133*4+0x02000000 , 0x00000108 ); +reg_write( DDR_REG_BASE + 0x00090134*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090135*4+0x02000000 , 0x000007aa ); +reg_write( DDR_REG_BASE + 0x00090136*4+0x02000000 , 0x0000006a ); +reg_write( DDR_REG_BASE + 0x00090137*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090138*4+0x02000000 , 0x00008568 ); +reg_write( DDR_REG_BASE + 0x00090139*4+0x02000000 , 0x00000108 ); +reg_write( DDR_REG_BASE + 0x0009013a*4+0x02000000 , 0x000000b7 ); +reg_write( DDR_REG_BASE + 0x0009013b*4+0x02000000 , 0x00000790 ); +reg_write( DDR_REG_BASE + 0x0009013c*4+0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x0009013d*4+0x02000000 , 0x0000001f ); +reg_write( DDR_REG_BASE + 0x0009013e*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009013f*4+0x02000000 , 0x00000068 ); +reg_write( DDR_REG_BASE + 0x00090140*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090141*4+0x02000000 , 0x00008558 ); +reg_write( DDR_REG_BASE + 0x00090142*4+0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x00090143*4+0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00090144*4+0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x00090145*4+0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x00090146*4+0x02000000 , 0x0000000d ); +reg_write( DDR_REG_BASE + 0x00090147*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090148*4+0x02000000 , 0x00000068 ); +reg_write( DDR_REG_BASE + 0x00090149*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009014a*4+0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x0009014b*4+0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x0009014c*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009014d*4+0x02000000 , 0x00008558 ); +reg_write( DDR_REG_BASE + 0x0009014e*4+0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x0009014f*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090150*4+0x02000000 , 0x000003c8 ); +reg_write( DDR_REG_BASE + 0x00090151*4+0x02000000 , 0x000001a9 ); +reg_write( DDR_REG_BASE + 0x00090152*4+0x02000000 , 0x00000003 ); +reg_write( DDR_REG_BASE + 0x00090153*4+0x02000000 , 0x00000370 ); +reg_write( DDR_REG_BASE + 0x00090154*4+0x02000000 , 0x00000129 ); +reg_write( DDR_REG_BASE + 0x00090155*4+0x02000000 , 0x00000020 ); +reg_write( DDR_REG_BASE + 0x00090156*4+0x02000000 , 0x000002aa ); +reg_write( DDR_REG_BASE + 0x00090157*4+0x02000000 , 0x00000009 ); +reg_write( DDR_REG_BASE + 0x00090158*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090159*4+0x02000000 , 0x000000e8 ); +reg_write( DDR_REG_BASE + 0x0009015a*4+0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009015b*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009015c*4+0x02000000 , 0x00008140 ); +reg_write( DDR_REG_BASE + 0x0009015d*4+0x02000000 , 0x0000010c ); +reg_write( DDR_REG_BASE + 0x0009015e*4+0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x0009015f*4+0x02000000 , 0x00008138 ); +reg_write( DDR_REG_BASE + 0x00090160*4+0x02000000 , 0x00000104 ); +reg_write( DDR_REG_BASE + 0x00090161*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090162*4+0x02000000 , 0x00000448 ); +reg_write( DDR_REG_BASE + 0x00090163*4+0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090164*4+0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00090165*4+0x02000000 , 0x000007c0 ); +reg_write( DDR_REG_BASE + 0x00090166*4+0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090167*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090168*4+0x02000000 , 0x000000e8 ); +reg_write( DDR_REG_BASE + 0x00090169*4+0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009016a*4+0x02000000 , 0x00000047 ); +reg_write( DDR_REG_BASE + 0x0009016b*4+0x02000000 , 0x00000630 ); +reg_write( DDR_REG_BASE + 0x0009016c*4+0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009016d*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x0009016e*4+0x02000000 , 0x00000618 ); +reg_write( DDR_REG_BASE + 0x0009016f*4+0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090170*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090171*4+0x02000000 , 0x000000e0 ); +reg_write( DDR_REG_BASE + 0x00090172*4+0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090173*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090174*4+0x02000000 , 0x000007c8 ); +reg_write( DDR_REG_BASE + 0x00090175*4+0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090176*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090177*4+0x02000000 , 0x00008140 ); +reg_write( DDR_REG_BASE + 0x00090178*4+0x02000000 , 0x0000010c ); +reg_write( DDR_REG_BASE + 0x00090179*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009017a*4+0x02000000 , 0x00000478 ); +reg_write( DDR_REG_BASE + 0x0009017b*4+0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009017c*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009017d*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x0009017e*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x0009017f*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090180*4+0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00090181*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090006*4+0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090007*4+0x02000000 , 0x000007c8 ); +reg_write( DDR_REG_BASE + 0x00090008*4+0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090009*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009000a*4+0x02000000 , 0x00000400 ); +reg_write( DDR_REG_BASE + 0x0009000b*4+0x02000000 , 0x00000106 ); +reg_write( DDR_REG_BASE + 0x000d00e7*4+0x02000000 , 0x00000400 ); +reg_write( DDR_REG_BASE + 0x00090017*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009001f*4+0x02000000 , 0x00000029 ); +reg_write( DDR_REG_BASE + 0x00090026*4+0x02000000 , 0x00000068 ); +reg_write( DDR_REG_BASE + 0x000400d0*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000400d1*4+0x02000000 , 0x00000101 ); +reg_write( DDR_REG_BASE + 0x000400d2*4+0x02000000 , 0x00000105 ); +reg_write( DDR_REG_BASE + 0x000400d3*4+0x02000000 , 0x00000107 ); +reg_write( DDR_REG_BASE + 0x000400d4*4+0x02000000 , 0x0000010f ); +reg_write( DDR_REG_BASE + 0x000400d5*4+0x02000000 , 0x00000202 ); +reg_write( DDR_REG_BASE + 0x000400d6*4+0x02000000 , 0x0000020a ); +reg_write( DDR_REG_BASE + 0x000400d7*4+0x02000000 , 0x0000020b ); +reg_write( DDR_REG_BASE + 0x0002003a*4+0x02000000 , 0x00000002 ); +reg_write( DDR_REG_BASE + 0x000200be*4+0x02000000 , 0x00000003 ); +reg_write( DDR_REG_BASE + 0x0002000b*4+0x02000000 , 0x00000053 ); +reg_write( DDR_REG_BASE + 0x0002000c*4+0x02000000 , 0x000000a6 ); +reg_write( DDR_REG_BASE + 0x0002000d*4+0x02000000 , 0x00000682 ); +reg_write( DDR_REG_BASE + 0x0002000e*4+0x02000000 , 0x0000002c ); +reg_write( DDR_REG_BASE + 0x0009000c*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009000d*4+0x02000000 , 0x00000173 ); +reg_write( DDR_REG_BASE + 0x0009000e*4+0x02000000 , 0x00000060 ); +reg_write( DDR_REG_BASE + 0x0009000f*4+0x02000000 , 0x00006110 ); +reg_write( DDR_REG_BASE + 0x00090010*4+0x02000000 , 0x00002152 ); +reg_write( DDR_REG_BASE + 0x00090011*4+0x02000000 , 0x0000dfbd ); +reg_write( DDR_REG_BASE + 0x00090012*4+0x02000000 , 0x00002060 ); +reg_write( DDR_REG_BASE + 0x00090013*4+0x02000000 , 0x00006152 ); +reg_write( DDR_REG_BASE + 0x00020010*4 +0x02000000 , 0x5a); +reg_write( DDR_REG_BASE + 0x00020011*4 +0x02000000 , 0x3); +reg_write( DDR_REG_BASE + 0x00040080*4+0x02000000 , 0x000000e0 ); +reg_write( DDR_REG_BASE + 0x00040081*4+0x02000000 , 0x00000012 ); +reg_write( DDR_REG_BASE + 0x00040082*4+0x02000000 , 0x000000e0 ); +reg_write( DDR_REG_BASE + 0x00040083*4+0x02000000 , 0x00000012 ); +reg_write( DDR_REG_BASE + 0x00040084*4+0x02000000 , 0x000000e0 ); +reg_write( DDR_REG_BASE + 0x00040085*4+0x02000000 , 0x00000012 ); +reg_write( DDR_REG_BASE + 0x000400fd*4+0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00010011*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00010012*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00010013*4+0x02000000 , 0x00000180 ); +reg_write( DDR_REG_BASE + 0x00010018*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00010002*4+0x02000000 , 0x00006209 ); +reg_write( DDR_REG_BASE + 0x000100b2*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000101b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000102b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000103b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000104b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000105b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000106b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000107b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000108b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00011011*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00011012*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00011013*4+0x02000000 , 0x00000180 ); +reg_write( DDR_REG_BASE + 0x00011018*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00011002*4+0x02000000 , 0x00006209 ); +reg_write( DDR_REG_BASE + 0x000110b2*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000111b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000112b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000113b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000114b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000115b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000116b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000117b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000118b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00012011*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00012012*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00012013*4+0x02000000 , 0x00000180 ); +reg_write( DDR_REG_BASE + 0x00012018*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00012002*4+0x02000000 , 0x00006209 ); +reg_write( DDR_REG_BASE + 0x000120b2*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000121b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000122b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000123b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000124b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000125b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000126b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000127b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000128b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00013011*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00013012*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00013013*4+0x02000000 , 0x00000180 ); +reg_write( DDR_REG_BASE + 0x00013018*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00013002*4+0x02000000 , 0x00006209 ); +reg_write( DDR_REG_BASE + 0x000130b2*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000131b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000132b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000133b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000134b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000135b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000136b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000137b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000138b4*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00020089*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00020088*4+0x02000000 , 0x00000019 ); +reg_write( DDR_REG_BASE + 0x000c0080*4+0x02000000 , 0x00000002 ); +reg_write( DDR_REG_BASE + 0x000d0000*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000d0000*4+0x02000000 , 0x00000000 ); +reg_read ( DDR_REG_BASE + 0x0002001d*4+0x02000000 , data ); +reg_write( DDR_REG_BASE + 0x0002001d*4+0x02000000 , 0x00000001 ); +reg_read ( DDR_REG_BASE + 0x00020097*4+0x02000000 , data ); + + +//////////////////phy init end //////////////////////////////////// + +reg_write( DDR_REG_BASE + 0x000001b0 , 0x00000034 ); + +reg_read (DDR_REG_BASE + 0x000001bc , data ); +while((data&0x1) !=0x1) { + reg_read (DDR_REG_BASE + 0x000001bc , data ); +} + + +reg_write( DDR_REG_BASE + 0x000001b0 , 0x00000014 ); +reg_write( DDR_REG_BASE + 0x000001b0 , 0x00000015 ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000320 , 0x00000001 ); + + + +reg_read (DDR_REG_BASE + 0x00000324 , data ); + while((data&0x1) !=0x1) { + reg_read (DDR_REG_BASE + 0x00000324 , data ); + } + +reg_read (DDR_REG_BASE + 0x00000004 , data ); + while((data&0x1) !=0x1) { + reg_read (DDR_REG_BASE + 0x00000004 , data ); + } + + + + +reg_write( DDR_REG_BASE + 0x000001c4 , 0xd1000000 ); +reg_write( DDR_REG_BASE + 0x00000320 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000000d0 , 0x00020002 ); +reg_write( DDR_REG_BASE + 0x00000320 , 0x00000001 ); + + + +reg_read (DDR_REG_BASE + 0x00000324 , data ); + while((data&0x1) !=0x1) { + reg_read (DDR_REG_BASE + 0x00000324 , data ); + } + + + + +reg_write( DDR_REG_BASE + 0x00000304 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000490 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000540 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000005f0 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000006a0 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000750 , 0x00000001 ); + +reg_write( DDR_REG_BASE + 0x0000060 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0000050 , 0x98210000 ); + + // { + // unsigned long add,i; + // add = DDR_REG_BASE +0x5401b*4+0x02000000; printf("MR12-CA add =%lx value =%lx\n",add,readl(add)); + // add = DDR_REG_BASE +0x5401c*4+0x02000000; printf("MR14-DQ add =%lx value =%lx\n",add,readl(add)); + + // for(i=0;i<8;i++) + // {add = DDR_REG_BASE + 0x00010040*4+0x02000000+i*0x100*4; printf("dbyte0 add =%lx value =%lx\n",add,readl(add));} + // for(i=0;i<8;i++) + // {add = DDR_REG_BASE + 0x00011040*4+0x02000000+i*0x100*4; printf("dbyte1 add =%lx value =%lx\n",add,readl(add));} + // for(i=0;i<8;i++) + // {add = DDR_REG_BASE + 0x00012040*4+0x02000000+i*0x100*4; printf("dbyte2 add =%lx value =%lx\n",add,readl(add));} + // for(i=0;i<8;i++) + // {add = DDR_REG_BASE + 0x00013040*4+0x02000000+i*0x100*4; printf("dbyte3 add =%lx value =%lx\n",add,readl(add)); } + // } + + + +} diff --git a/src/little/uboot/board/canaan/k230_canmv_01studio/lpddr4_init_32_swap_3200.c b/src/little/uboot/board/canaan/k230_canmv_01studio/lpddr4_init_32_swap_3200.c new file mode 100755 index 000000000..3fa082ffa --- /dev/null +++ b/src/little/uboot/board/canaan/k230_canmv_01studio/lpddr4_init_32_swap_3200.c @@ -0,0 +1,35725 @@ +/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +//#include +//#include +#include +#define DDR_REG_BASE 0x98000000 + +#define reg_write( addr,v) \ + { \ + (*(volatile uint32_t *)((size_t)(addr))) = (v); \ + } + + +#define reg_read( addr,v) \ + { \ + v =readl ((const volatile void __iomem *) addr ); \ + } + +int change_pll_3100(void); + +void ddr4_init_3200(void) +{ + int data; + int train_data=0; + printf("ddr4_init_3200 \n"); + + change_pll_3100(); + + // reg_read (0x91100060,data); + // data =((data>>2)<<2)|0x0; + // data =data | 0x80000000; + // reg_write(0x91100060,data); + + reg_read (0x911030a0,data); + data =data | 0x10; + reg_write(0x911030a0,data); + + + + +reg_write( DDR_REG_BASE + 0x00000304 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000001 ); +reg_read ( DDR_REG_BASE + 0x00000004 , data); +reg_write( DDR_REG_BASE + 0x00000000 , 0x01080020 ); +reg_write( DDR_REG_BASE + 0x00000010 , 0x0000b030 ); +reg_write( DDR_REG_BASE + 0x00000014 , 0x0002ec4d ); +reg_write( DDR_REG_BASE + 0x00000020 , 0x00000202 ); +reg_write( DDR_REG_BASE + 0x00000024 , 0xf491fa51 ); +reg_write( DDR_REG_BASE + 0x00000028 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x0000002c , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000020 ); +reg_write( DDR_REG_BASE + 0x00000034 , 0x00408a04 ); +reg_write( DDR_REG_BASE + 0x00000038 , 0x0e0e0002 ); +reg_write( DDR_REG_BASE + 0x0000003c , 0x00000060 ); +reg_write( DDR_REG_BASE + 0x00000050 , 0x98210000 ); +reg_write( DDR_REG_BASE + 0x00000054 , 0x005a0050 ); +reg_write( DDR_REG_BASE + 0x00000060 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000064 , 0x00610068 ); +reg_write( DDR_REG_BASE + 0x00000068 , 0x00300000 ); +reg_write( DDR_REG_BASE + 0x000000c0 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000000d0 , 0xc0020002 ); +reg_write( DDR_REG_BASE + 0x000000d4 , 0x00010002 ); +reg_write( DDR_REG_BASE + 0x000000d8 , 0x00001a00 ); +reg_write( DDR_REG_BASE + 0x000000dc , 0x0054002d ); +reg_write( DDR_REG_BASE + 0x000000e0 , 0x00310008 ); +reg_write( DDR_REG_BASE + 0x000000e4 , 0x00040009 ); +reg_write( DDR_REG_BASE + 0x000000e8 , 0x0000004d ); +reg_write( DDR_REG_BASE + 0x000000ec , 0x0000004d ); +reg_write( DDR_REG_BASE + 0x000000f0 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000000f4 , 0x0000032f ); +reg_write( DDR_REG_BASE + 0x000000f8 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00000100 , 0x1b201a22 ); +reg_write( DDR_REG_BASE + 0x00000104 , 0x00060630 ); +reg_write( DDR_REG_BASE + 0x00000108 , 0x070e0f14 ); +reg_write( DDR_REG_BASE + 0x0000010c , 0x00c0c006 ); +reg_write( DDR_REG_BASE + 0x00000110 , 0x0f04080f ); +reg_write( DDR_REG_BASE + 0x00000114 , 0x02040c0c ); +reg_write( DDR_REG_BASE + 0x00000118 , 0x01010007 ); +reg_write( DDR_REG_BASE + 0x0000011c , 0x00000402 ); +reg_write( DDR_REG_BASE + 0x00000120 , 0x00000101 ); +reg_write( DDR_REG_BASE + 0x00000130 , 0x00020000 ); +reg_write( DDR_REG_BASE + 0x00000134 , 0x0c100002 ); +reg_write( DDR_REG_BASE + 0x00000138 , 0x0000006e ); +reg_write( DDR_REG_BASE + 0x0000013c , 0x80000000 ); +reg_write( DDR_REG_BASE + 0x00000144 , 0x00a00050 ); +reg_write( DDR_REG_BASE + 0x00000180 , 0xc3200018 ); +reg_write( DDR_REG_BASE + 0x00000184 , 0x0287c42a ); +reg_write( DDR_REG_BASE + 0x00000188 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000190 , 0x0397820a ); +reg_write( DDR_REG_BASE + 0x00000194 , 0x00090202 ); +reg_write( DDR_REG_BASE + 0x00000198 , 0x0710a120 ); +reg_write( DDR_REG_BASE + 0x000001a0 , 0xe0400018 ); +reg_write( DDR_REG_BASE + 0x000001a4 , 0x00020035 ); +reg_write( DDR_REG_BASE + 0x000001a8 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000001b0 , 0x00000015 ); +reg_write( DDR_REG_BASE + 0x000001b4 , 0x0000170a ); +reg_write( DDR_REG_BASE + 0x000001c0 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000001c4 , 0xd1000000 ); +reg_write( DDR_REG_BASE + 0x00000200 , 0x0000001f ); +reg_write( DDR_REG_BASE + 0x00000204 , 0x00080808 ); +reg_write( DDR_REG_BASE + 0x00000208 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0000020c , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000210 , 0x00001f1f ); +reg_write( DDR_REG_BASE + 0x00000214 , 0x070f0707 ); +reg_write( DDR_REG_BASE + 0x00000218 , 0x0f070707 ); // 8gb,1GB +reg_write( DDR_REG_BASE + 0x0000021c , 0x00000f0f ); +reg_write( DDR_REG_BASE + 0x00000224 , 0x07070707 ); +reg_write( DDR_REG_BASE + 0x00000228 , 0x07070707 ); +reg_write( DDR_REG_BASE + 0x0000022c , 0x00000007 ); +reg_write( DDR_REG_BASE + 0x00000240 , 0x06080a48 ); +reg_write( DDR_REG_BASE + 0x00000244 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000250 , 0x804b1f18 ); +reg_write( DDR_REG_BASE + 0x00000254 , 0x00002000 ); +reg_write( DDR_REG_BASE + 0x0000025c , 0x0f000001 ); +reg_write( DDR_REG_BASE + 0x00000264 , 0x0f00007f ); +reg_write( DDR_REG_BASE + 0x0000026c , 0x0f00007f ); +reg_write( DDR_REG_BASE + 0x00000270 , 0x04040208 ); +reg_write( DDR_REG_BASE + 0x00000274 , 0x08400810 ); +reg_write( DDR_REG_BASE + 0x00000300 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000304 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0000030c , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000320 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000328 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0000036c , 0x00000011 ); +reg_write( DDR_REG_BASE + 0x00000490 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000540 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000005f0 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000006a0 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000750 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00002020 , 0x00000202 ); +reg_write( DDR_REG_BASE + 0x00002024 , 0xf491fa51 ); +reg_write( DDR_REG_BASE + 0x00002034 , 0x00408a04 ); +reg_write( DDR_REG_BASE + 0x00002050 , 0xf0210000 ); +reg_write( DDR_REG_BASE + 0x00002064 , 0x00618068 ); +reg_write( DDR_REG_BASE + 0x00002068 , 0x00300000 ); +reg_write( DDR_REG_BASE + 0x000020dc , 0x0054002d ); +reg_write( DDR_REG_BASE + 0x000020e0 , 0x00310008 ); +reg_write( DDR_REG_BASE + 0x000020e8 , 0x0000004d ); +reg_write( DDR_REG_BASE + 0x000020ec , 0x0000004d ); +reg_write( DDR_REG_BASE + 0x000020f4 , 0x0000032f ); +reg_write( DDR_REG_BASE + 0x000020f8 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00002100 , 0x1b201a22 ); +reg_write( DDR_REG_BASE + 0x00002104 , 0x00060630 ); +reg_write( DDR_REG_BASE + 0x00002108 , 0x070e0f14 ); +reg_write( DDR_REG_BASE + 0x0000210c , 0x00c0c006 ); +reg_write( DDR_REG_BASE + 0x00002110 , 0x0f04080f ); +reg_write( DDR_REG_BASE + 0x00002114 , 0x02040c0c ); +reg_write( DDR_REG_BASE + 0x00002118 , 0x01010007 ); +reg_write( DDR_REG_BASE + 0x0000211c , 0x00000402 ); +reg_write( DDR_REG_BASE + 0x00002120 , 0x00000101 ); +reg_write( DDR_REG_BASE + 0x00002130 , 0x00020000 ); +reg_write( DDR_REG_BASE + 0x00002134 , 0x0c100002 ); +reg_write( DDR_REG_BASE + 0x00002138 , 0x0000006e ); +reg_write( DDR_REG_BASE + 0x0000213c , 0x80000000 ); +reg_write( DDR_REG_BASE + 0x00002144 , 0x00a00050 ); +reg_write( DDR_REG_BASE + 0x00002180 , 0xc3200018 ); +reg_write( DDR_REG_BASE + 0x00002190 , 0x0397820a ); +reg_write( DDR_REG_BASE + 0x00002194 , 0x00090202 ); +reg_write( DDR_REG_BASE + 0x000021b4 , 0x0000170a ); +reg_write( DDR_REG_BASE + 0x00002240 , 0x06080a48 ); +reg_write( DDR_REG_BASE + 0x00003020 , 0x00000202 ); +reg_write( DDR_REG_BASE + 0x00003024 , 0xf491fa51 ); +reg_write( DDR_REG_BASE + 0x00003034 , 0x00408a04 ); +reg_write( DDR_REG_BASE + 0x00003050 , 0x48210000 ); +reg_write( DDR_REG_BASE + 0x00003064 , 0x00618068 ); +reg_write( DDR_REG_BASE + 0x00003068 , 0x00300000 ); +reg_write( DDR_REG_BASE + 0x000030dc , 0x0054002d ); +reg_write( DDR_REG_BASE + 0x000030e0 , 0x00310008 ); +reg_write( DDR_REG_BASE + 0x000030e8 , 0x0000004d ); +reg_write( DDR_REG_BASE + 0x000030ec , 0x0000004d ); +reg_write( DDR_REG_BASE + 0x000030f4 , 0x0000032f ); +reg_write( DDR_REG_BASE + 0x000030f8 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00003100 , 0x1b201a22 ); +reg_write( DDR_REG_BASE + 0x00003104 , 0x00060630 ); +reg_write( DDR_REG_BASE + 0x00003108 , 0x070e0f14 ); +reg_write( DDR_REG_BASE + 0x0000310c , 0x00c0c006 ); +reg_write( DDR_REG_BASE + 0x00003110 , 0x0f04080f ); +reg_write( DDR_REG_BASE + 0x00003114 , 0x02040c0c ); +reg_write( DDR_REG_BASE + 0x00003118 , 0x01010007 ); +reg_write( DDR_REG_BASE + 0x0000311c , 0x00000402 ); +reg_write( DDR_REG_BASE + 0x00003120 , 0x00000101 ); +reg_write( DDR_REG_BASE + 0x00003130 , 0x00020000 ); +reg_write( DDR_REG_BASE + 0x00003134 , 0x0c100002 ); +reg_write( DDR_REG_BASE + 0x00003138 , 0x0000006e ); +reg_write( DDR_REG_BASE + 0x0000313c , 0x80000000 ); +reg_write( DDR_REG_BASE + 0x00003144 , 0x00a00050 ); +reg_write( DDR_REG_BASE + 0x00003180 , 0xc3200018 ); +reg_write( DDR_REG_BASE + 0x00003190 , 0x0397820a ); +reg_write( DDR_REG_BASE + 0x00003194 , 0x00090202 ); +reg_write( DDR_REG_BASE + 0x000031b4 , 0x0000170a ); +reg_write( DDR_REG_BASE + 0x00003240 , 0x06080a48 ); +reg_write( DDR_REG_BASE + 0x00004020 , 0x00000202 ); +reg_write( DDR_REG_BASE + 0x00004024 , 0xf491fa51 ); +reg_write( DDR_REG_BASE + 0x00004034 , 0x00408a04 ); +reg_write( DDR_REG_BASE + 0x00004050 , 0x70210000 ); +reg_write( DDR_REG_BASE + 0x00004064 , 0x00610068 ); +reg_write( DDR_REG_BASE + 0x00004068 , 0x00300000 ); +reg_write( DDR_REG_BASE + 0x000040dc , 0x0054002d ); +reg_write( DDR_REG_BASE + 0x000040e0 , 0x00310008 ); +reg_write( DDR_REG_BASE + 0x000040e8 , 0x0000004d ); +reg_write( DDR_REG_BASE + 0x000040ec , 0x0000004d ); +reg_write( DDR_REG_BASE + 0x000040f4 , 0x0000032f ); +reg_write( DDR_REG_BASE + 0x000040f8 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00004100 , 0x1b201a22 ); +reg_write( DDR_REG_BASE + 0x00004104 , 0x00060630 ); +reg_write( DDR_REG_BASE + 0x00004108 , 0x070e0f14 ); +reg_write( DDR_REG_BASE + 0x0000410c , 0x00c0c006 ); +reg_write( DDR_REG_BASE + 0x00004110 , 0x0f04080f ); +reg_write( DDR_REG_BASE + 0x00004114 , 0x02040c0c ); +reg_write( DDR_REG_BASE + 0x00004118 , 0x01010007 ); +reg_write( DDR_REG_BASE + 0x0000411c , 0x00000402 ); +reg_write( DDR_REG_BASE + 0x00004120 , 0x00000101 ); +reg_write( DDR_REG_BASE + 0x00004130 , 0x00020000 ); +reg_write( DDR_REG_BASE + 0x00004134 , 0x0c100002 ); +reg_write( DDR_REG_BASE + 0x00004138 , 0x0000006e ); +reg_write( DDR_REG_BASE + 0x0000413c , 0x80000000 ); +reg_write( DDR_REG_BASE + 0x00004144 , 0x00a00050 ); +reg_write( DDR_REG_BASE + 0x00004180 , 0xc3200018 ); +reg_write( DDR_REG_BASE + 0x00004190 , 0x0397820a ); +reg_write( DDR_REG_BASE + 0x00004194 , 0x00090202 ); +reg_write( DDR_REG_BASE + 0x000041b4 , 0x0000170a ); +reg_write( DDR_REG_BASE + 0x00004240 , 0x06080a48 ); +reg_read ( DDR_REG_BASE + 0x00000060 , data); +reg_write( DDR_REG_BASE + 0x00000400 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000404 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x000004b4 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x00000564 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x00000614 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x000006c4 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x00000404 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000004b4 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000564 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000614 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000006c4 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000404 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000004b4 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000564 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000614 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000006c4 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000404 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x000004b4 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x00000564 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x00000614 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x000006c4 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x00000408 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x000004b8 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x00000568 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x00000618 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x000006c8 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x00000408 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000004b8 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000568 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000618 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000006c8 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000408 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000004b8 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000568 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000618 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000006c8 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000408 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x000004b8 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x00000568 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x00000618 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x000006c8 , 0x0000100f ); +reg_read ( DDR_REG_BASE + 0x00000030 , data ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000020 ); + +////////////////////de rst//////////////////////////////////////// + + reg_read ( 0x9110309c, data ); + data=data|0x00020000; + reg_write ( 0x9110309c, data ); + + + + +reg_write( DDR_REG_BASE + 0x00000304 , 0x00000000 ); +reg_read ( DDR_REG_BASE + 0x00000030 , data ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000020 ); +reg_read ( DDR_REG_BASE + 0x00000030 , data ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000020 ); +reg_read ( DDR_REG_BASE + 0x000001c4 , data ); +reg_write( DDR_REG_BASE + 0x000001c4 , 0xd1000000 ); +reg_write( DDR_REG_BASE + 0x00000320 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000001b0 , 0x00000014 ); +reg_write( DDR_REG_BASE + 0x000001b0 , 0x00000014 ); +reg_write( DDR_REG_BASE + 0x00000304 , 0x00000002 ); +reg_read ( DDR_REG_BASE + 0x000000d0 , data ); +reg_read ( DDR_REG_BASE + 0x000001c0 , data ); +reg_read ( DDR_REG_BASE + 0x00000000 , data ); +reg_read ( DDR_REG_BASE + 0x000000dc , data ); +reg_read ( DDR_REG_BASE + 0x000000dc , data ); +reg_read ( DDR_REG_BASE + 0x000000e0 , data ); +reg_read ( DDR_REG_BASE + 0x000000e8 , data ); +reg_read ( DDR_REG_BASE + 0x000000e8 , data ); +reg_read ( DDR_REG_BASE + 0x000000e0 , data ); +reg_read ( DDR_REG_BASE + 0x000000ec , data ); +reg_read ( DDR_REG_BASE + 0x000000ec , data ); +reg_read ( DDR_REG_BASE + 0x000000d0 , data ); +reg_read ( DDR_REG_BASE + 0x000001c0 , data ); +reg_read ( DDR_REG_BASE + 0x00000000 , data ); +reg_read ( DDR_REG_BASE + 0x000000dc , data ); +reg_read ( DDR_REG_BASE + 0x000000dc , data ); +reg_read ( DDR_REG_BASE + 0x000000e0 , data ); +reg_read ( DDR_REG_BASE + 0x000000e8 , data ); +reg_read ( DDR_REG_BASE + 0x000000e8 , data ); +reg_read ( DDR_REG_BASE + 0x000000e0 , data ); +reg_read ( DDR_REG_BASE + 0x000000ec , data ); +reg_read ( DDR_REG_BASE + 0x000000ec , data ); +reg_read ( DDR_REG_BASE + 0x000000d0 , data ); + +///////////////////////// phy init begin/////////////////////// + +reg_write( DDR_REG_BASE +0x1005f*4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x1015f*4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x1105f*4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x1115f*4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x1205f*4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x1215f*4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x1305f*4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x1315f*4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x55 *4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x1055 *4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x2055 *4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x3055 *4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x4055 *4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x5055 *4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x6055 *4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x7055 *4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x8055 *4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x9055 *4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x200c5*4 +0x02000000,0x19); +reg_write( DDR_REG_BASE +0x2002e*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x90204*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x20024*4 +0x02000000,0xe3); +reg_write( DDR_REG_BASE +0x2003a*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x2007d*4 +0x02000000,0x212); +reg_write( DDR_REG_BASE +0x2007c*4 +0x02000000,0x61); +reg_write( DDR_REG_BASE +0x20056*4 +0x02000000,0x3); + +//iteration place +//PHY RX ODT +//0010_00 00_0000 0x208 0x200 Down:120 +//0010_10 00_0000 0x28a 0x280 Down:80 +//0110_00 00_0000 0x618 0x600 Down:60 +//0110_10 00_0000 0x69a 0x680 Down:48 +//1110_00 00_0000 0xe38 0xe00 Down:40 +//1110_10 00_0000 0xeba 0xe80 Down:34.3 +reg_write( DDR_REG_BASE +0x1004d*4 +0x02000000,0x600); +reg_write( DDR_REG_BASE +0x1014d*4 +0x02000000,0x600); +reg_write( DDR_REG_BASE +0x1104d*4 +0x02000000,0x600); +reg_write( DDR_REG_BASE +0x1114d*4 +0x02000000,0x600); +reg_write( DDR_REG_BASE +0x1204d*4 +0x02000000,0x600); +reg_write( DDR_REG_BASE +0x1214d*4 +0x02000000,0x600); +reg_write( DDR_REG_BASE +0x1304d*4 +0x02000000,0x600); +reg_write( DDR_REG_BASE +0x1314d*4 +0x02000000,0x600); + +//iteration place +//PHY TX output impedence +//0010_00 00_1000 0x208 Pullup/Down:120 +//0010_10 00_1010 0x28a Pullup/Down:80 +//0110_00 01_1000 0x618 Pullup/Down:60 +//0110_10 01_1010 0x69a Pullup/Down:48 +//1110_00 11_1000 0xe38 Pullup/Down:40 +//1110_10 11_1010 0xeba Pullup/Down:34.3 +reg_write( DDR_REG_BASE +0x10049*4 +0x02000000,0xe38); +reg_write( DDR_REG_BASE +0x10149*4 +0x02000000,0xe38); +reg_write( DDR_REG_BASE +0x11049*4 +0x02000000,0xe38); +reg_write( DDR_REG_BASE +0x11149*4 +0x02000000,0xe38); +reg_write( DDR_REG_BASE +0x12049*4 +0x02000000,0xe38); +reg_write( DDR_REG_BASE +0x12149*4 +0x02000000,0xe38); +reg_write( DDR_REG_BASE +0x13049*4 +0x02000000,0xe38); +reg_write( DDR_REG_BASE +0x13149*4 +0x02000000,0xe38); + +//iteration +// PHY AC/CLK output impedence +//00000_00000 0x0 120 +//00001_00001 0x21 60 +//00011_00011 0x63 40 +//00111_00111 0xe7 30 +//01111_01111 0x1ef 24 +//11111_11111 0x3ff 20 + +// // [phyinit_C_initPhyConfig] Programming ATxImpedance::ADrvStrenP to 0x1 +// // [phyinit_C_initPhyConfig] Programming ATxImpedance::ADrvStrenN to 0x1 +reg_write( DDR_REG_BASE +0x43 *4 +0x02000000,0x63); +reg_write( DDR_REG_BASE +0x1043 *4 +0x02000000,0x63); +reg_write( DDR_REG_BASE +0x2043 *4 +0x02000000,0x63); +reg_write( DDR_REG_BASE +0x3043 *4 +0x02000000,0x63); +reg_write( DDR_REG_BASE +0x4043 *4 +0x02000000,0x63); +reg_write( DDR_REG_BASE +0x5043 *4 +0x02000000,0x63); +reg_write( DDR_REG_BASE +0x6043 *4 +0x02000000,0x63); +reg_write( DDR_REG_BASE +0x7043 *4 +0x02000000,0x63); +reg_write( DDR_REG_BASE +0x8043 *4 +0x02000000,0x63); +reg_write( DDR_REG_BASE +0x9043 *4 +0x02000000,0x63); + + +reg_write( DDR_REG_BASE +0x20018*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x20075*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x20050*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x20008*4 +0x02000000,0x320); +reg_write( DDR_REG_BASE +0x20088*4 +0x02000000,0x9); + +//iteration place +//PHY VERF +// 0x104 15% (0x14) +// 0x14c 20% (0x1a) +// 0x19c 25% (0x20) +// 0x1e4 30% (0x26) +// 0x284 40% (0x33) + +// // [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal::GlobalVrefInDAC to 0x51 +// // [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal to 0x288 +reg_write( DDR_REG_BASE +0x200b2*4 +0x02000000,0x19c); +reg_write( DDR_REG_BASE +0x10043*4 +0x02000000,0x5a1); +reg_write( DDR_REG_BASE +0x10143*4 +0x02000000,0x5a1); +reg_write( DDR_REG_BASE +0x11043*4 +0x02000000,0x5a1); +reg_write( DDR_REG_BASE +0x11143*4 +0x02000000,0x5a1); +reg_write( DDR_REG_BASE +0x12043*4 +0x02000000,0x5a1); +reg_write( DDR_REG_BASE +0x12143*4 +0x02000000,0x5a1); +reg_write( DDR_REG_BASE +0x13043*4 +0x02000000,0x5a1); +reg_write( DDR_REG_BASE +0x13143*4 +0x02000000,0x5a1); +reg_write( DDR_REG_BASE +0x200fa*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x20019*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x200f0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x200f1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x200f2*4 +0x02000000,0x4444); +reg_write( DDR_REG_BASE +0x200f3*4 +0x02000000,0x8888); +reg_write( DDR_REG_BASE +0x200f4*4 +0x02000000,0x5555); +reg_write( DDR_REG_BASE +0x200f5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x200f6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x200f7*4 +0x02000000,0xf000); +reg_write( DDR_REG_BASE +0x1004a*4 +0x02000000,0x500); +reg_write( DDR_REG_BASE +0x1104a*4 +0x02000000,0x500); +reg_write( DDR_REG_BASE +0x1204a*4 +0x02000000,0x500); +reg_write( DDR_REG_BASE +0x1304a*4 +0x02000000,0x500); +reg_write( DDR_REG_BASE +0x20025*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x2002d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x2002c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x20060*4 +0x02000000,0x2); + + +//swap +reg_write( DDR_REG_BASE + 0x20100*4+0x02000000,0x5); //CA0 +reg_write( DDR_REG_BASE + 0x20101*4+0x02000000,0x4); //CA1 +reg_write( DDR_REG_BASE + 0x20102*4+0x02000000,0x3); //CA2 +reg_write( DDR_REG_BASE + 0x20103*4+0x02000000,0x2); //CA3 +reg_write( DDR_REG_BASE + 0x20104*4+0x02000000,0x1); //CA4 +reg_write( DDR_REG_BASE + 0x20105*4+0x02000000,0x0); //CA5 + +reg_write( DDR_REG_BASE + 0x100a0*4+0x02000000,0x4); // +reg_write( DDR_REG_BASE + 0x100a1*4+0x02000000,0x5); // +reg_write( DDR_REG_BASE + 0x100a2*4+0x02000000,0x0); // +reg_write( DDR_REG_BASE + 0x100a3*4+0x02000000,0x6); // +reg_write( DDR_REG_BASE + 0x100a4*4+0x02000000,0x7); // +reg_write( DDR_REG_BASE + 0x100a5*4+0x02000000,0x2); // +reg_write( DDR_REG_BASE + 0x100a6*4+0x02000000,0x3); // +reg_write( DDR_REG_BASE + 0x100a7*4+0x02000000,0x1); // + +reg_write( DDR_REG_BASE + 0x110a0*4+0x02000000,0x4); // +reg_write( DDR_REG_BASE + 0x110a1*4+0x02000000,0x7); // +reg_write( DDR_REG_BASE + 0x110a2*4+0x02000000,0x6); // +reg_write( DDR_REG_BASE + 0x110a3*4+0x02000000,0x0); // +reg_write( DDR_REG_BASE + 0x110a4*4+0x02000000,0x2); // +reg_write( DDR_REG_BASE + 0x110a5*4+0x02000000,0x1); // +reg_write( DDR_REG_BASE + 0x110a6*4+0x02000000,0x5); // +reg_write( DDR_REG_BASE + 0x110a7*4+0x02000000,0x3); // + +reg_write( DDR_REG_BASE + 0x130a0*4+0x02000000,0x3); // +reg_write( DDR_REG_BASE + 0x130a1*4+0x02000000,0x4); // +reg_write( DDR_REG_BASE + 0x130a2*4+0x02000000,0x0); // +reg_write( DDR_REG_BASE + 0x130a3*4+0x02000000,0x2); // +reg_write( DDR_REG_BASE + 0x130a4*4+0x02000000,0x1); // +reg_write( DDR_REG_BASE + 0x130a5*4+0x02000000,0x5); // +reg_write( DDR_REG_BASE + 0x130a6*4+0x02000000,0x6); // +reg_write( DDR_REG_BASE + 0x130a7*4+0x02000000,0x7); // + +//reg_write( DDR_REG_BASE + 0x130a0*4+0x02000000,0x3); //lndq =1 +//reg_write( DDR_REG_BASE + 0x130a1*4+0x02000000,0x0); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x130a2*4+0x02000000,0x2); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x130a3*4+0x02000000,0x1); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x130a4*4+0x02000000,0x6); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x130a5*4+0x02000000,0x7); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x130a6*4+0x02000000,0x5); //CA1 =0 +//reg_write( DDR_REG_BASE + 0x130a7*4+0x02000000,0x4); //CA1 =0 + +reg_write( DDR_REG_BASE + 0x120a0*4+0x02000000,0x3); // +reg_write( DDR_REG_BASE + 0x120a1*4+0x02000000,0x0); // +reg_write( DDR_REG_BASE + 0x120a2*4+0x02000000,0x2); // +reg_write( DDR_REG_BASE + 0x120a3*4+0x02000000,0x5); // +reg_write( DDR_REG_BASE + 0x120a4*4+0x02000000,0x4); // +reg_write( DDR_REG_BASE + 0x120a5*4+0x02000000,0x1); // +reg_write( DDR_REG_BASE + 0x120a6*4+0x02000000,0x7); // +reg_write( DDR_REG_BASE + 0x120a7*4+0x02000000,0x6); // + + + +reg_write( DDR_REG_BASE + 0x000d0000*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE +0x50000*4 +0x02000000,0x114); +reg_write( DDR_REG_BASE +0x50001*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50002*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50003*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50004*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50005*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50006*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50007*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50008*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50009*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5000a*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5000b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5000c*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5000d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5000e*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5000f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50010*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50011*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50012*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50013*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50014*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50015*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50016*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50017*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50018*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50019*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5001a*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5001b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5001c*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5001d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5001e*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5001f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50020*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50021*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50022*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50023*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50024*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50025*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50026*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50027*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50028*4 +0x02000000,0x2069); +reg_write( DDR_REG_BASE +0x50029*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x5002a*4 +0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x5002b*4 +0x02000000,0x7000); +reg_write( DDR_REG_BASE +0x5002c*4 +0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x5002d*4 +0x02000000,0x7000); +reg_write( DDR_REG_BASE +0x5002e*4 +0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x5002f*4 +0x02000000,0x7000); +reg_write( DDR_REG_BASE +0x50030*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50031*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50032*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50033*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50034*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50035*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50036*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50037*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50038*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50039*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50040*4 +0x02000000,0x7054); +reg_write( DDR_REG_BASE +0x50041*4 +0x02000000,0x7ce0); +reg_write( DDR_REG_BASE +0x50042*4 +0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x50043*4 +0x02000000,0x1101); +reg_write( DDR_REG_BASE +0x50044*4 +0x02000000,0x48c); +reg_write( DDR_REG_BASE +0x50045*4 +0x02000000,0x2242); +reg_write( DDR_REG_BASE +0x50046*4 +0x02000000,0x8042); +reg_write( DDR_REG_BASE +0x50047*4 +0x02000000,0x1b01); +reg_write( DDR_REG_BASE +0x50048*4 +0x02000000,0x312); +reg_write( DDR_REG_BASE +0x50049*4 +0x02000000,0xf5fb); +reg_write( DDR_REG_BASE +0x5004a*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5004b*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5004c*4 +0x02000000,0xc4e1); +reg_write( DDR_REG_BASE +0x5004d*4 +0x02000000,0x240a); +reg_write( DDR_REG_BASE +0x5004e*4 +0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x5004f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50050*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x50051*4 +0x02000000,0xc19); +reg_write( DDR_REG_BASE +0x50052*4 +0x02000000,0x1703); +reg_write( DDR_REG_BASE +0x50053*4 +0x02000000,0x240a); +reg_write( DDR_REG_BASE +0x50054*4 +0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x50055*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50056*4 +0x02000000,0x4000); +reg_write( DDR_REG_BASE +0x50057*4 +0x02000000,0xc0d); +reg_write( DDR_REG_BASE +0x50058*4 +0x02000000,0x1702); +reg_write( DDR_REG_BASE +0x50059*4 +0x02000000,0xc4c1); +reg_write( DDR_REG_BASE +0x5005a*4 +0x02000000,0x2020); +reg_write( DDR_REG_BASE +0x5005b*4 +0x02000000,0x7c0); +reg_write( DDR_REG_BASE +0x5005c*4 +0x02000000,0x7fff); +reg_write( DDR_REG_BASE +0x5005d*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5005e*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5005f*4 +0x02000000,0xb3c8); +reg_write( DDR_REG_BASE +0x50060*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50061*4 +0x02000000,0xb388); +reg_write( DDR_REG_BASE +0x50062*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50063*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50064*4 +0x02000000,0xb348); +reg_write( DDR_REG_BASE +0x50065*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50066*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50067*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50068*4 +0x02000000,0x748d); +reg_write( DDR_REG_BASE +0x50069*4 +0x02000000,0xdd0c); +reg_write( DDR_REG_BASE +0x5006a*4 +0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x5006b*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5006c*4 +0x02000000,0x748d); +reg_write( DDR_REG_BASE +0x5006d*4 +0x02000000,0xdd08); +reg_write( DDR_REG_BASE +0x5006e*4 +0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x5006f*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50070*4 +0x02000000,0x748d); +reg_write( DDR_REG_BASE +0x50071*4 +0x02000000,0x74ad); +reg_write( DDR_REG_BASE +0x50072*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x50073*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50074*4 +0x02000000,0x748d); +reg_write( DDR_REG_BASE +0x50075*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x50076*4 +0x02000000,0xc702); +reg_write( DDR_REG_BASE +0x50077*4 +0x02000000,0xc601); +reg_write( DDR_REG_BASE +0x50078*4 +0x02000000,0x24b0); +reg_write( DDR_REG_BASE +0x50079*4 +0x02000000,0x334d); +reg_write( DDR_REG_BASE +0x5007a*4 +0x02000000,0x24b0); +reg_write( DDR_REG_BASE +0x5007b*4 +0x02000000,0x331f); +reg_write( DDR_REG_BASE +0x5007c*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5007d*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5007e*4 +0x02000000,0x2244); +reg_write( DDR_REG_BASE +0x5007f*4 +0x02000000,0x8ffc); +reg_write( DDR_REG_BASE +0x50080*4 +0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x50081*4 +0x02000000,0x7000); +reg_write( DDR_REG_BASE +0x50082*4 +0x02000000,0x20e8); +reg_write( DDR_REG_BASE +0x50083*4 +0x02000000,0x1a2); +reg_write( DDR_REG_BASE +0x50084*4 +0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x50085*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50086*4 +0x02000000,0x212f); +reg_write( DDR_REG_BASE +0x50087*4 +0x02000000,0x4b); +reg_write( DDR_REG_BASE +0x50088*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50089*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5008a*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5008b*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5008c*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x5008d*4 +0x02000000,0x704d); +reg_write( DDR_REG_BASE +0x5008e*4 +0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x5008f*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x50090*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50091*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x50092*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x50093*4 +0x02000000,0x206a); +reg_write( DDR_REG_BASE +0x50094*4 +0x02000000,0x280); +reg_write( DDR_REG_BASE +0x50095*4 +0x02000000,0xb88d); +reg_write( DDR_REG_BASE +0x50096*4 +0x02000000,0x2029); +reg_write( DDR_REG_BASE +0x50097*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50098*4 +0x02000000,0x44db); +reg_write( DDR_REG_BASE +0x50099*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5009a*4 +0x02000000,0x4000); +reg_write( DDR_REG_BASE +0x5009b*4 +0x02000000,0x42db); +reg_write( DDR_REG_BASE +0x5009c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5009d*4 +0x02000000,0x400); +reg_write( DDR_REG_BASE +0x5009e*4 +0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x5009f*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x500a0*4 +0x02000000,0x2022); +reg_write( DDR_REG_BASE +0x500a1*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x500a2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x500a3*4 +0x02000000,0x3294); +reg_write( DDR_REG_BASE +0x500a4*4 +0x02000000,0x2069); +reg_write( DDR_REG_BASE +0x500a5*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x500a6*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x500a7*4 +0x02000000,0xf1fe); +reg_write( DDR_REG_BASE +0x500a8*4 +0x02000000,0xc3e1); +reg_write( DDR_REG_BASE +0x500a9*4 +0x02000000,0xc2e1); +reg_write( DDR_REG_BASE +0x500aa*4 +0x02000000,0xc1e1); +reg_write( DDR_REG_BASE +0x500ab*4 +0x02000000,0xc0e1); +reg_write( DDR_REG_BASE +0x500ac*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x500ad*4 +0x02000000,0xc5e1); +reg_write( DDR_REG_BASE +0x500ae*4 +0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x500af*4 +0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x500b0*4 +0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x500b1*4 +0x02000000,0xdc14); +reg_write( DDR_REG_BASE +0x500b2*4 +0x02000000,0x77f); +reg_write( DDR_REG_BASE +0x500b3*4 +0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x500b4*4 +0x02000000,0xda25); +reg_write( DDR_REG_BASE +0x500b5*4 +0x02000000,0xba9f); +reg_write( DDR_REG_BASE +0x500b6*4 +0x02000000,0x8a60); +reg_write( DDR_REG_BASE +0x500b7*4 +0x02000000,0x1233); +reg_write( DDR_REG_BASE +0x500b8*4 +0x02000000,0x80); +reg_write( DDR_REG_BASE +0x500b9*4 +0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x500ba*4 +0x02000000,0x1aea); +reg_write( DDR_REG_BASE +0x500bb*4 +0x02000000,0x8002); +reg_write( DDR_REG_BASE +0x500bc*4 +0x02000000,0x12ed); +reg_write( DDR_REG_BASE +0x500bd*4 +0x02000000,0x8080); +reg_write( DDR_REG_BASE +0x500be*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x500bf*4 +0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x500c0*4 +0x02000000,0xf20d); +reg_write( DDR_REG_BASE +0x500c1*4 +0x02000000,0xc085); +reg_write( DDR_REG_BASE +0x500c2*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x500c3*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x500c4*4 +0x02000000,0x872); +reg_write( DDR_REG_BASE +0x500c5*4 +0x02000000,0x360); +reg_write( DDR_REG_BASE +0x500c6*4 +0x02000000,0xc185); +reg_write( DDR_REG_BASE +0x500c7*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x500c8*4 +0x02000000,0x402); +reg_write( DDR_REG_BASE +0x500c9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x500ca*4 +0x02000000,0xd2a); +reg_write( DDR_REG_BASE +0x500cb*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x500cc*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x500cd*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x500ce*4 +0x02000000,0xc86); +reg_write( DDR_REG_BASE +0x500cf*4 +0x02000000,0x2e0); +reg_write( DDR_REG_BASE +0x500d0*4 +0x02000000,0x1a09); +reg_write( DDR_REG_BASE +0x500d1*4 +0x02000000,0x3003); +reg_write( DDR_REG_BASE +0x500d2*4 +0x02000000,0xfb6); +reg_write( DDR_REG_BASE +0x500d3*4 +0x02000000,0x320); +reg_write( DDR_REG_BASE +0x500d4*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x500d5*4 +0x02000000,0x25ab); +reg_write( DDR_REG_BASE +0x500d6*4 +0x02000000,0x10c4); +reg_write( DDR_REG_BASE +0x500d7*4 +0x02000000,0x7fff); +reg_write( DDR_REG_BASE +0x500d8*4 +0x02000000,0xf1ff); +reg_write( DDR_REG_BASE +0x500d9*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x500da*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x500db*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x500dc*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x500dd*4 +0x02000000,0xc1a6); +reg_write( DDR_REG_BASE +0x500de*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x500df*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x500e0*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x500e1*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x500e2*4 +0x02000000,0xc243); +reg_write( DDR_REG_BASE +0x500e3*4 +0x02000000,0xa0c0); +reg_write( DDR_REG_BASE +0x500e4*4 +0x02000000,0xd83f); +reg_write( DDR_REG_BASE +0x500e5*4 +0x02000000,0xc064); +reg_write( DDR_REG_BASE +0x500e6*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x500e7*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x500e8*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x500e9*4 +0x02000000,0x88a0); +reg_write( DDR_REG_BASE +0x500ea*4 +0x02000000,0x1c11); +reg_write( DDR_REG_BASE +0x500eb*4 +0x02000000,0x3382); +reg_write( DDR_REG_BASE +0x500ec*4 +0x02000000,0xf054); +reg_write( DDR_REG_BASE +0x500ed*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x500ee*4 +0x02000000,0x89d); +reg_write( DDR_REG_BASE +0x500ef*4 +0x02000000,0x6ee); +reg_write( DDR_REG_BASE +0x500f0*4 +0x02000000,0xc084); +reg_write( DDR_REG_BASE +0x500f1*4 +0x02000000,0x60c8); +reg_write( DDR_REG_BASE +0x500f2*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x500f3*4 +0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x500f4*4 +0x02000000,0xd83f); +reg_write( DDR_REG_BASE +0x500f5*4 +0x02000000,0xb19); +reg_write( DDR_REG_BASE +0x500f6*4 +0x02000000,0x30b0); +reg_write( DDR_REG_BASE +0x500f7*4 +0x02000000,0x7826); +reg_write( DDR_REG_BASE +0x500f8*4 +0x02000000,0xb19); +reg_write( DDR_REG_BASE +0x500f9*4 +0x02000000,0x3070); +reg_write( DDR_REG_BASE +0x500fa*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x500fb*4 +0x02000000,0xb1d); +reg_write( DDR_REG_BASE +0x500fc*4 +0x02000000,0x3031); +reg_write( DDR_REG_BASE +0x500fd*4 +0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x500fe*4 +0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x500ff*4 +0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x50100*4 +0x02000000,0xc300); +reg_write( DDR_REG_BASE +0x50101*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x50102*4 +0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x50103*4 +0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x50104*4 +0x02000000,0xc200); +reg_write( DDR_REG_BASE +0x50105*4 +0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x50106*4 +0x02000000,0xb42); +reg_write( DDR_REG_BASE +0x50107*4 +0x02000000,0x380); +reg_write( DDR_REG_BASE +0x50108*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50109*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5010a*4 +0x02000000,0x4e20); +reg_write( DDR_REG_BASE +0x5010b*4 +0x02000000,0xeca); +reg_write( DDR_REG_BASE +0x5010c*4 +0x02000000,0x1a0); +reg_write( DDR_REG_BASE +0x5010d*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5010e*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x5010f*4 +0x02000000,0xf026); +reg_write( DDR_REG_BASE +0x50110*4 +0x02000000,0x255f); +reg_write( DDR_REG_BASE +0x50111*4 +0x02000000,0x1402); +reg_write( DDR_REG_BASE +0x50112*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50113*4 +0x02000000,0x7a16); +reg_write( DDR_REG_BASE +0x50114*4 +0x02000000,0x62f8); +reg_write( DDR_REG_BASE +0x50115*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x50116*4 +0x02000000,0x8824); +reg_write( DDR_REG_BASE +0x50117*4 +0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x50118*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50119*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5011a*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x5011b*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5011c*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5011d*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x5011e*4 +0x02000000,0x54); +reg_write( DDR_REG_BASE +0x5011f*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x50120*4 +0x02000000,0xcc2); +reg_write( DDR_REG_BASE +0x50121*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50122*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x50123*4 +0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x50124*4 +0x02000000,0xb8c5); +reg_write( DDR_REG_BASE +0x50125*4 +0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x50126*4 +0x02000000,0x7907); +reg_write( DDR_REG_BASE +0x50127*4 +0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x50128*4 +0x02000000,0x3200); +reg_write( DDR_REG_BASE +0x50129*4 +0x02000000,0x4220); +reg_write( DDR_REG_BASE +0x5012a*4 +0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x5012b*4 +0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x5012c*4 +0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x5012d*4 +0x02000000,0x801); +reg_write( DDR_REG_BASE +0x5012e*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x5012f*4 +0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x50130*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x50131*4 +0x02000000,0x8020); +reg_write( DDR_REG_BASE +0x50132*4 +0x02000000,0x7945); +reg_write( DDR_REG_BASE +0x50133*4 +0x02000000,0xa020); +reg_write( DDR_REG_BASE +0x50134*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50135*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50136*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50137*4 +0x02000000,0x784); +reg_write( DDR_REG_BASE +0x50138*4 +0x02000000,0x78b4); +reg_write( DDR_REG_BASE +0x50139*4 +0x02000000,0x6028); +reg_write( DDR_REG_BASE +0x5013a*4 +0x02000000,0xfad); +reg_write( DDR_REG_BASE +0x5013b*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5013c*4 +0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x5013d*4 +0x02000000,0xb63); +reg_write( DDR_REG_BASE +0x5013e*4 +0x02000000,0xb0d4); +reg_write( DDR_REG_BASE +0x5013f*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x50140*4 +0x02000000,0xefb); +reg_write( DDR_REG_BASE +0x50141*4 +0x02000000,0x90b4); +reg_write( DDR_REG_BASE +0x50142*4 +0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x50143*4 +0x02000000,0xc0a6); +reg_write( DDR_REG_BASE +0x50144*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50145*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50146*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50147*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50148*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50149*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5014a*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5014b*4 +0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x5014c*4 +0x02000000,0x320d); +reg_write( DDR_REG_BASE +0x5014d*4 +0x02000000,0x216f); +reg_write( DDR_REG_BASE +0x5014e*4 +0x02000000,0x243); +reg_write( DDR_REG_BASE +0x5014f*4 +0x02000000,0x1154); +reg_write( DDR_REG_BASE +0x50150*4 +0x02000000,0x80); +reg_write( DDR_REG_BASE +0x50151*4 +0x02000000,0x89a0); +reg_write( DDR_REG_BASE +0x50152*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x50153*4 +0x02000000,0x1121); +reg_write( DDR_REG_BASE +0x50154*4 +0x02000000,0x80); +reg_write( DDR_REG_BASE +0x50155*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x50156*4 +0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x50157*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50158*4 +0x02000000,0x334); +reg_write( DDR_REG_BASE +0x50159*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x5015a*4 +0x02000000,0xe5a); +reg_write( DDR_REG_BASE +0x5015b*4 +0x02000000,0x160); +reg_write( DDR_REG_BASE +0x5015c*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5015d*4 +0x02000000,0xc09c); +reg_write( DDR_REG_BASE +0x5015e*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5015f*4 +0x02000000,0xc089); +reg_write( DDR_REG_BASE +0x50160*4 +0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x50161*4 +0x02000000,0x3d41); +reg_write( DDR_REG_BASE +0x50162*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x50163*4 +0x02000000,0x3f82); +reg_write( DDR_REG_BASE +0x50164*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50165*4 +0x02000000,0x19c); +reg_write( DDR_REG_BASE +0x50166*4 +0x02000000,0xece); +reg_write( DDR_REG_BASE +0x50167*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50168*4 +0x02000000,0x2440); +reg_write( DDR_REG_BASE +0x50169*4 +0x02000000,0x3fc3); +reg_write( DDR_REG_BASE +0x5016a*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x5016b*4 +0x02000000,0xc341); +reg_write( DDR_REG_BASE +0x5016c*4 +0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x5016d*4 +0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x5016e*4 +0x02000000,0x601); +reg_write( DDR_REG_BASE +0x5016f*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x50170*4 +0x02000000,0x6059); +reg_write( DDR_REG_BASE +0x50171*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50172*4 +0x02000000,0xa900); +reg_write( DDR_REG_BASE +0x50173*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x50174*4 +0x02000000,0xaf3); +reg_write( DDR_REG_BASE +0x50175*4 +0x02000000,0x8634); +reg_write( DDR_REG_BASE +0x50176*4 +0x02000000,0xc09f); +reg_write( DDR_REG_BASE +0x50177*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x50178*4 +0x02000000,0xbf9); +reg_write( DDR_REG_BASE +0x50179*4 +0x02000000,0x8334); +reg_write( DDR_REG_BASE +0x5017a*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5017b*4 +0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x5017c*4 +0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x5017d*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5017e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5017f*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50180*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x50181*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50182*4 +0x02000000,0x9001); +reg_write( DDR_REG_BASE +0x50183*4 +0x02000000,0xe100); +reg_write( DDR_REG_BASE +0x50184*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x50185*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x50186*4 +0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x50187*4 +0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x50188*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x50189*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5018a*4 +0x02000000,0xb887); +reg_write( DDR_REG_BASE +0x5018b*4 +0x02000000,0xdd6); +reg_write( DDR_REG_BASE +0x5018c*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5018d*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x5018e*4 +0x02000000,0xe12); +reg_write( DDR_REG_BASE +0x5018f*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50190*4 +0x02000000,0xc029); +reg_write( DDR_REG_BASE +0x50191*4 +0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x50192*4 +0x02000000,0xe0a); +reg_write( DDR_REG_BASE +0x50193*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50194*4 +0x02000000,0xc02b); +reg_write( DDR_REG_BASE +0x50195*4 +0x02000000,0x33f); +reg_write( DDR_REG_BASE +0x50196*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50197*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x50198*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x50199*4 +0x02000000,0x84d); +reg_write( DDR_REG_BASE +0x5019a*4 +0x02000000,0xb5); +reg_write( DDR_REG_BASE +0x5019b*4 +0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x5019c*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5019d*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5019e*4 +0x02000000,0x7003); +reg_write( DDR_REG_BASE +0x5019f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x501a0*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x501a1*4 +0x02000000,0xc208); +reg_write( DDR_REG_BASE +0x501a2*4 +0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x501a3*4 +0x02000000,0xe); +reg_write( DDR_REG_BASE +0x501a4*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x501a5*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x501a6*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x501a7*4 +0x02000000,0x4a); +reg_write( DDR_REG_BASE +0x501a8*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x501a9*4 +0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x501aa*4 +0x02000000,0x7e07); +reg_write( DDR_REG_BASE +0x501ab*4 +0x02000000,0xc8e); +reg_write( DDR_REG_BASE +0x501ac*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x501ad*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x501ae*4 +0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x501af*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x501b0*4 +0x02000000,0x47a9); +reg_write( DDR_REG_BASE +0x501b1*4 +0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x501b2*4 +0x02000000,0x17de); +reg_write( DDR_REG_BASE +0x501b3*4 +0x02000000,0xe11); +reg_write( DDR_REG_BASE +0x501b4*4 +0x02000000,0x3010); +reg_write( DDR_REG_BASE +0x501b5*4 +0x02000000,0x2642); +reg_write( DDR_REG_BASE +0x501b6*4 +0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x501b7*4 +0x02000000,0xeff); +reg_write( DDR_REG_BASE +0x501b8*4 +0x02000000,0xb031); +reg_write( DDR_REG_BASE +0x501b9*4 +0x02000000,0x7ffb); +reg_write( DDR_REG_BASE +0x501ba*4 +0x02000000,0x84b); +reg_write( DDR_REG_BASE +0x501bb*4 +0x02000000,0x38f); +reg_write( DDR_REG_BASE +0x501bc*4 +0x02000000,0x2e9); +reg_write( DDR_REG_BASE +0x501bd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x501be*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x501bf*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x501c0*4 +0x02000000,0x7342); +reg_write( DDR_REG_BASE +0x501c1*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x501c2*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x501c3*4 +0x02000000,0xc204); +reg_write( DDR_REG_BASE +0x501c4*4 +0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x501c5*4 +0x02000000,0x8e); +reg_write( DDR_REG_BASE +0x501c6*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x501c7*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x501c8*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x501c9*4 +0x02000000,0x7d); +reg_write( DDR_REG_BASE +0x501ca*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x501cb*4 +0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x501cc*4 +0x02000000,0x7e07); +reg_write( DDR_REG_BASE +0x501cd*4 +0x02000000,0xc4a); +reg_write( DDR_REG_BASE +0x501ce*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x501cf*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x501d0*4 +0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x501d1*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x501d2*4 +0x02000000,0x47a9); +reg_write( DDR_REG_BASE +0x501d3*4 +0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x501d4*4 +0x02000000,0x17cd); +reg_write( DDR_REG_BASE +0x501d5*4 +0x02000000,0xed06); +reg_write( DDR_REG_BASE +0x501d6*4 +0x02000000,0xbd61); +reg_write( DDR_REG_BASE +0x501d7*4 +0x02000000,0xd01); +reg_write( DDR_REG_BASE +0x501d8*4 +0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x501d9*4 +0x02000000,0x7ffb); +reg_write( DDR_REG_BASE +0x501da*4 +0x02000000,0x2011); +reg_write( DDR_REG_BASE +0x501db*4 +0x02000000,0x8380); +reg_write( DDR_REG_BASE +0x501dc*4 +0x02000000,0x2a8); +reg_write( DDR_REG_BASE +0x501dd*4 +0x02000000,0x21); +reg_write( DDR_REG_BASE +0x501de*4 +0x02000000,0x72ad); +reg_write( DDR_REG_BASE +0x501df*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x501e0*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x501e1*4 +0x02000000,0xf00b); +reg_write( DDR_REG_BASE +0x501e2*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x501e3*4 +0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x501e4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x501e5*4 +0x02000000,0x1b4); +reg_write( DDR_REG_BASE +0x501e6*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x501e7*4 +0x02000000,0x19c0); +reg_write( DDR_REG_BASE +0x501e8*4 +0x02000000,0x82); +reg_write( DDR_REG_BASE +0x501e9*4 +0x02000000,0xa940); +reg_write( DDR_REG_BASE +0x501ea*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x501eb*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x501ec*4 +0x02000000,0x8003); +reg_write( DDR_REG_BASE +0x501ed*4 +0x02000000,0xf7b6); +reg_write( DDR_REG_BASE +0x501ee*4 +0x02000000,0xf3a); +reg_write( DDR_REG_BASE +0x501ef*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x501f0*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x501f1*4 +0x02000000,0xf36); +reg_write( DDR_REG_BASE +0x501f2*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x501f3*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x501f4*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x501f5*4 +0x02000000,0x7043); +reg_write( DDR_REG_BASE +0x501f6*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x501f7*4 +0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x501f8*4 +0x02000000,0xf26); +reg_write( DDR_REG_BASE +0x501f9*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x501fa*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x501fb*4 +0x02000000,0x78ef); +reg_write( DDR_REG_BASE +0x501fc*4 +0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x501fd*4 +0x02000000,0xfee); +reg_write( DDR_REG_BASE +0x501fe*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x501ff*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x50200*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50201*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x50202*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50203*4 +0x02000000,0x73c2); +reg_write( DDR_REG_BASE +0x50204*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50205*4 +0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x50206*4 +0x02000000,0xd86); +reg_write( DDR_REG_BASE +0x50207*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50208*4 +0x02000000,0xf06); +reg_write( DDR_REG_BASE +0x50209*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5020a*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x5020b*4 +0x02000000,0x43f9); +reg_write( DDR_REG_BASE +0x5020c*4 +0x02000000,0xf04e); +reg_write( DDR_REG_BASE +0x5020d*4 +0x02000000,0x143f); +reg_write( DDR_REG_BASE +0x5020e*4 +0x02000000,0x3082); +reg_write( DDR_REG_BASE +0x5020f*4 +0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x50210*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50211*4 +0x02000000,0x2353); +reg_write( DDR_REG_BASE +0x50212*4 +0x02000000,0x3101); +reg_write( DDR_REG_BASE +0x50213*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x50214*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50215*4 +0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x50216*4 +0x02000000,0x6068); +reg_write( DDR_REG_BASE +0x50217*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x50218*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50219*4 +0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x5021a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5021b*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x5021c*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5021d*4 +0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x5021e*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5021f*4 +0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x50220*4 +0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x50221*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x50222*4 +0x02000000,0xbe9); +reg_write( DDR_REG_BASE +0x50223*4 +0x02000000,0x80a4); +reg_write( DDR_REG_BASE +0x50224*4 +0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x50225*4 +0x02000000,0x3d40); +reg_write( DDR_REG_BASE +0x50226*4 +0x02000000,0xc9e); +reg_write( DDR_REG_BASE +0x50227*4 +0x02000000,0x80); +reg_write( DDR_REG_BASE +0x50228*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x50229*4 +0x02000000,0xc190); +reg_write( DDR_REG_BASE +0x5022a*4 +0x02000000,0xd62); +reg_write( DDR_REG_BASE +0x5022b*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5022c*4 +0x02000000,0xda07); +reg_write( DDR_REG_BASE +0x5022d*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5022e*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5022f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50230*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x50231*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x50232*4 +0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x50233*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50234*4 +0x02000000,0x1b4); +reg_write( DDR_REG_BASE +0x50235*4 +0x02000000,0xc210); +reg_write( DDR_REG_BASE +0x50236*4 +0x02000000,0x209f); +reg_write( DDR_REG_BASE +0x50237*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x50238*4 +0x02000000,0x224a); +reg_write( DDR_REG_BASE +0x50239*4 +0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x5023a*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x5023b*4 +0x02000000,0x7163); +reg_write( DDR_REG_BASE +0x5023c*4 +0x02000000,0x8960); +reg_write( DDR_REG_BASE +0x5023d*4 +0x02000000,0x2253); +reg_write( DDR_REG_BASE +0x5023e*4 +0x02000000,0x140); +reg_write( DDR_REG_BASE +0x5023f*4 +0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x50240*4 +0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x50241*4 +0x02000000,0xa900); +reg_write( DDR_REG_BASE +0x50242*4 +0x02000000,0x1140); +reg_write( DDR_REG_BASE +0x50243*4 +0x02000000,0x83); +reg_write( DDR_REG_BASE +0x50244*4 +0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x50245*4 +0x02000000,0x2242); +reg_write( DDR_REG_BASE +0x50246*4 +0x02000000,0x104a); +reg_write( DDR_REG_BASE +0x50247*4 +0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x50248*4 +0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x50249*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5024a*4 +0x02000000,0xb8c5); +reg_write( DDR_REG_BASE +0x5024b*4 +0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x5024c*4 +0x02000000,0x1940); +reg_write( DDR_REG_BASE +0x5024d*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x5024e*4 +0x02000000,0x1180); +reg_write( DDR_REG_BASE +0x5024f*4 +0x02000000,0x83); +reg_write( DDR_REG_BASE +0x50250*4 +0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x50251*4 +0x02000000,0xda10); +reg_write( DDR_REG_BASE +0x50252*4 +0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x50253*4 +0x02000000,0xa01); +reg_write( DDR_REG_BASE +0x50254*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x50255*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50256*4 +0x02000000,0xb8c5); +reg_write( DDR_REG_BASE +0x50257*4 +0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x50258*4 +0x02000000,0x1980); +reg_write( DDR_REG_BASE +0x50259*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x5025a*4 +0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x5025b*4 +0x02000000,0xb001); +reg_write( DDR_REG_BASE +0x5025c*4 +0x02000000,0x762); +reg_write( DDR_REG_BASE +0x5025d*4 +0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x5025e*4 +0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x5025f*4 +0x02000000,0x6c0); +reg_write( DDR_REG_BASE +0x50260*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x50261*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50262*4 +0x02000000,0x7043); +reg_write( DDR_REG_BASE +0x50263*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50264*4 +0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x50265*4 +0x02000000,0xc22); +reg_write( DDR_REG_BASE +0x50266*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50267*4 +0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x50268*4 +0x02000000,0xa5a); +reg_write( DDR_REG_BASE +0x50269*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5026a*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x5026b*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x5026c*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5026d*4 +0x02000000,0x94); +reg_write( DDR_REG_BASE +0x5026e*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5026f*4 +0x02000000,0x9e2); +reg_write( DDR_REG_BASE +0x50270*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50271*4 +0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x50272*4 +0x02000000,0xf0ba); +reg_write( DDR_REG_BASE +0x50273*4 +0x02000000,0x66e8); +reg_write( DDR_REG_BASE +0x50274*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x50275*4 +0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x50276*4 +0x02000000,0xf2b5); +reg_write( DDR_REG_BASE +0x50277*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x50278*4 +0x02000000,0x7912); +reg_write( DDR_REG_BASE +0x50279*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5027a*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5027b*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5027c*4 +0x02000000,0x1b); +reg_write( DDR_REG_BASE +0x5027d*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5027e*4 +0x02000000,0x7812); +reg_write( DDR_REG_BASE +0x5027f*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50280*4 +0x02000000,0xdab); +reg_write( DDR_REG_BASE +0x50281*4 +0x02000000,0x103e); +reg_write( DDR_REG_BASE +0x50282*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x50283*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x50284*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50285*4 +0x02000000,0x95); +reg_write( DDR_REG_BASE +0x50286*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50287*4 +0x02000000,0x9b2); +reg_write( DDR_REG_BASE +0x50288*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50289*4 +0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x5028a*4 +0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x5028b*4 +0x02000000,0xf040); +reg_write( DDR_REG_BASE +0x5028c*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5028d*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x5028e*4 +0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x5028f*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x50290*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x50291*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50292*4 +0x02000000,0x1b4); +reg_write( DDR_REG_BASE +0x50293*4 +0x02000000,0x6048); +reg_write( DDR_REG_BASE +0x50294*4 +0x02000000,0x792f); +reg_write( DDR_REG_BASE +0x50295*4 +0x02000000,0xec06); +reg_write( DDR_REG_BASE +0x50296*4 +0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x50297*4 +0x02000000,0xc01); +reg_write( DDR_REG_BASE +0x50298*4 +0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x50299*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5029a*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x5029b*4 +0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x5029c*4 +0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x5029d*4 +0x02000000,0x7cc); +reg_write( DDR_REG_BASE +0x5029e*4 +0x02000000,0xec05); +reg_write( DDR_REG_BASE +0x5029f*4 +0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x502a0*4 +0x02000000,0xcff); +reg_write( DDR_REG_BASE +0x502a1*4 +0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x502a2*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x502a3*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x502a4*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x502a5*4 +0x02000000,0xbd7); +reg_write( DDR_REG_BASE +0x502a6*4 +0x02000000,0x8234); +reg_write( DDR_REG_BASE +0x502a7*4 +0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x502a8*4 +0x02000000,0x17cc); +reg_write( DDR_REG_BASE +0x502a9*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x502aa*4 +0x02000000,0x829); +reg_write( DDR_REG_BASE +0x502ab*4 +0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x502ac*4 +0x02000000,0x66ea); +reg_write( DDR_REG_BASE +0x502ad*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x502ae*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x502af*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x502b0*4 +0x02000000,0x19c); +reg_write( DDR_REG_BASE +0x502b1*4 +0x02000000,0x6048); +reg_write( DDR_REG_BASE +0x502b2*4 +0x02000000,0xc29f); +reg_write( DDR_REG_BASE +0x502b3*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x502b4*4 +0x02000000,0x600); +reg_write( DDR_REG_BASE +0x502b5*4 +0x02000000,0x621a); +reg_write( DDR_REG_BASE +0x502b6*4 +0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x502b7*4 +0x02000000,0x6c2); +reg_write( DDR_REG_BASE +0x502b8*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x502b9*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x502ba*4 +0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x502bb*4 +0x02000000,0x8840); +reg_write( DDR_REG_BASE +0x502bc*4 +0x02000000,0x7a25); +reg_write( DDR_REG_BASE +0x502bd*4 +0x02000000,0xa840); +reg_write( DDR_REG_BASE +0x502be*4 +0x02000000,0xcaa); +reg_write( DDR_REG_BASE +0x502bf*4 +0x02000000,0x2a0); +reg_write( DDR_REG_BASE +0x502c0*4 +0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x502c1*4 +0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x502c2*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x502c3*4 +0x02000000,0x96); +reg_write( DDR_REG_BASE +0x502c4*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x502c5*4 +0x02000000,0x936); +reg_write( DDR_REG_BASE +0x502c6*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x502c7*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x502c8*4 +0x02000000,0x2340); +reg_write( DDR_REG_BASE +0x502c9*4 +0x02000000,0x321b); +reg_write( DDR_REG_BASE +0x502ca*4 +0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x502cb*4 +0x02000000,0xb003); +reg_write( DDR_REG_BASE +0x502cc*4 +0x02000000,0x780); +reg_write( DDR_REG_BASE +0x502cd*4 +0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x502ce*4 +0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x502cf*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x502d0*4 +0x02000000,0x97); +reg_write( DDR_REG_BASE +0x502d1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x502d2*4 +0x02000000,0x91a); +reg_write( DDR_REG_BASE +0x502d3*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x502d4*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x502d5*4 +0x02000000,0xdaf); +reg_write( DDR_REG_BASE +0x502d6*4 +0x02000000,0x107e); +reg_write( DDR_REG_BASE +0x502d7*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x502d8*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x502d9*4 +0x02000000,0x98); +reg_write( DDR_REG_BASE +0x502da*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x502db*4 +0x02000000,0x90a); +reg_write( DDR_REG_BASE +0x502dc*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x502dd*4 +0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x502de*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x502df*4 +0x02000000,0xf042); +reg_write( DDR_REG_BASE +0x502e0*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x502e1*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x502e2*4 +0x02000000,0xf019); +reg_write( DDR_REG_BASE +0x502e3*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x502e4*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x502e5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x502e6*4 +0x02000000,0x1b4); +reg_write( DDR_REG_BASE +0x502e7*4 +0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x502e8*4 +0x02000000,0x10c0); +reg_write( DDR_REG_BASE +0x502e9*4 +0x02000000,0x80); +reg_write( DDR_REG_BASE +0x502ea*4 +0x02000000,0x792f); +reg_write( DDR_REG_BASE +0x502eb*4 +0x02000000,0xec06); +reg_write( DDR_REG_BASE +0x502ec*4 +0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x502ed*4 +0x02000000,0xc01); +reg_write( DDR_REG_BASE +0x502ee*4 +0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x502ef*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x502f0*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x502f1*4 +0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x502f2*4 +0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x502f3*4 +0x02000000,0x7cc); +reg_write( DDR_REG_BASE +0x502f4*4 +0x02000000,0xec05); +reg_write( DDR_REG_BASE +0x502f5*4 +0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x502f6*4 +0x02000000,0xcff); +reg_write( DDR_REG_BASE +0x502f7*4 +0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x502f8*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x502f9*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x502fa*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x502fb*4 +0x02000000,0xbd3); +reg_write( DDR_REG_BASE +0x502fc*4 +0x02000000,0x8234); +reg_write( DDR_REG_BASE +0x502fd*4 +0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x502fe*4 +0x02000000,0x17cc); +reg_write( DDR_REG_BASE +0x502ff*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50300*4 +0x02000000,0x82b); +reg_write( DDR_REG_BASE +0x50301*4 +0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x50302*4 +0x02000000,0xc089); +reg_write( DDR_REG_BASE +0x50303*4 +0x02000000,0x60f8); +reg_write( DDR_REG_BASE +0x50304*4 +0x02000000,0x8848); +reg_write( DDR_REG_BASE +0x50305*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x50306*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x50307*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50308*4 +0x02000000,0x19c); +reg_write( DDR_REG_BASE +0x50309*4 +0x02000000,0x6048); +reg_write( DDR_REG_BASE +0x5030a*4 +0x02000000,0xc29f); +reg_write( DDR_REG_BASE +0x5030b*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x5030c*4 +0x02000000,0x600); +reg_write( DDR_REG_BASE +0x5030d*4 +0x02000000,0x621a); +reg_write( DDR_REG_BASE +0x5030e*4 +0x02000000,0x78dd); +reg_write( DDR_REG_BASE +0x5030f*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50310*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50311*4 +0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x50312*4 +0x02000000,0x8840); +reg_write( DDR_REG_BASE +0x50313*4 +0x02000000,0x7a25); +reg_write( DDR_REG_BASE +0x50314*4 +0x02000000,0xa840); +reg_write( DDR_REG_BASE +0x50315*4 +0x02000000,0xbfe); +reg_write( DDR_REG_BASE +0x50316*4 +0x02000000,0x2a0); +reg_write( DDR_REG_BASE +0x50317*4 +0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x50318*4 +0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x50319*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5031a*4 +0x02000000,0x99); +reg_write( DDR_REG_BASE +0x5031b*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5031c*4 +0x02000000,0x886); +reg_write( DDR_REG_BASE +0x5031d*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5031e*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x5031f*4 +0x02000000,0xe608); +reg_write( DDR_REG_BASE +0x50320*4 +0x02000000,0x268c); +reg_write( DDR_REG_BASE +0x50321*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x50322*4 +0x02000000,0x77c); +reg_write( DDR_REG_BASE +0x50323*4 +0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x50324*4 +0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x50325*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50326*4 +0x02000000,0x9a); +reg_write( DDR_REG_BASE +0x50327*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50328*4 +0x02000000,0x86e); +reg_write( DDR_REG_BASE +0x50329*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5032a*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x5032b*4 +0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x5032c*4 +0x02000000,0x75f5); +reg_write( DDR_REG_BASE +0x5032d*4 +0x02000000,0x68e); +reg_write( DDR_REG_BASE +0x5032e*4 +0x02000000,0xffee); +reg_write( DDR_REG_BASE +0x5032f*4 +0x02000000,0xc689); +reg_write( DDR_REG_BASE +0x50330*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x50331*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x50332*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x50333*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x50334*4 +0x02000000,0x7414); +reg_write( DDR_REG_BASE +0x50335*4 +0x02000000,0x4c8); +reg_write( DDR_REG_BASE +0x50336*4 +0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x50337*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50338*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x50339*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x5033a*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5033b*4 +0x02000000,0xa76); +reg_write( DDR_REG_BASE +0x5033c*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5033d*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x5033e*4 +0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x5033f*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x50340*4 +0x02000000,0xf0e4); +reg_write( DDR_REG_BASE +0x50341*4 +0x02000000,0x143f); +reg_write( DDR_REG_BASE +0x50342*4 +0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x50343*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x50344*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50345*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50346*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x50347*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x50348*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x50349*4 +0x02000000,0xf096); +reg_write( DDR_REG_BASE +0x5034a*4 +0x02000000,0x60e8); +reg_write( DDR_REG_BASE +0x5034b*4 +0x02000000,0x260c); +reg_write( DDR_REG_BASE +0x5034c*4 +0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x5034d*4 +0x02000000,0xf491); +reg_write( DDR_REG_BASE +0x5034e*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5034f*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x50350*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x50351*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50352*4 +0x02000000,0x4758); +reg_write( DDR_REG_BASE +0x50353*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50354*4 +0x02000000,0xf033); +reg_write( DDR_REG_BASE +0x50355*4 +0x02000000,0xf20c); +reg_write( DDR_REG_BASE +0x50356*4 +0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x50357*4 +0x02000000,0x7cc); +reg_write( DDR_REG_BASE +0x50358*4 +0x02000000,0x43e3); +reg_write( DDR_REG_BASE +0x50359*4 +0x02000000,0xec06); +reg_write( DDR_REG_BASE +0x5035a*4 +0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x5035b*4 +0x02000000,0xc01); +reg_write( DDR_REG_BASE +0x5035c*4 +0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x5035d*4 +0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x5035e*4 +0x02000000,0xbbc0); +reg_write( DDR_REG_BASE +0x5035f*4 +0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x50360*4 +0x02000000,0x275a); +reg_write( DDR_REG_BASE +0x50361*4 +0x02000000,0x1603); +reg_write( DDR_REG_BASE +0x50362*4 +0x02000000,0xc49f); +reg_write( DDR_REG_BASE +0x50363*4 +0x02000000,0x647c); +reg_write( DDR_REG_BASE +0x50364*4 +0x02000000,0x7b1d); +reg_write( DDR_REG_BASE +0x50365*4 +0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x50366*4 +0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x50367*4 +0x02000000,0x2432); +reg_write( DDR_REG_BASE +0x50368*4 +0x02000000,0x10df); +reg_write( DDR_REG_BASE +0x50369*4 +0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x5036a*4 +0x02000000,0x3043); +reg_write( DDR_REG_BASE +0x5036b*4 +0x02000000,0x7c30); +reg_write( DDR_REG_BASE +0x5036c*4 +0x02000000,0x248c); +reg_write( DDR_REG_BASE +0x5036d*4 +0x02000000,0x9fc3); +reg_write( DDR_REG_BASE +0x5036e*4 +0x02000000,0xf408); +reg_write( DDR_REG_BASE +0x5036f*4 +0x02000000,0xe0df); +reg_write( DDR_REG_BASE +0x50370*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x50371*4 +0x02000000,0xf716); +reg_write( DDR_REG_BASE +0x50372*4 +0x02000000,0xeb94); +reg_write( DDR_REG_BASE +0x50373*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50374*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x50375*4 +0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x50376*4 +0x02000000,0x7074); +reg_write( DDR_REG_BASE +0x50377*4 +0x02000000,0x22c0); +reg_write( DDR_REG_BASE +0x50378*4 +0x02000000,0x61); +reg_write( DDR_REG_BASE +0x50379*4 +0x02000000,0xf20e); +reg_write( DDR_REG_BASE +0x5037a*4 +0x02000000,0xdb3f); +reg_write( DDR_REG_BASE +0x5037b*4 +0x02000000,0x233c); +reg_write( DDR_REG_BASE +0x5037c*4 +0x02000000,0xb); +reg_write( DDR_REG_BASE +0x5037d*4 +0x02000000,0x7c50); +reg_write( DDR_REG_BASE +0x5037e*4 +0x02000000,0x7bb0); +reg_write( DDR_REG_BASE +0x5037f*4 +0x02000000,0x233c); +reg_write( DDR_REG_BASE +0x50380*4 +0x02000000,0x303); +reg_write( DDR_REG_BASE +0x50381*4 +0x02000000,0x230b); +reg_write( DDR_REG_BASE +0x50382*4 +0x02000000,0x82c0); +reg_write( DDR_REG_BASE +0x50383*4 +0x02000000,0x755c); +reg_write( DDR_REG_BASE +0x50384*4 +0x02000000,0x763c); +reg_write( DDR_REG_BASE +0x50385*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x50386*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x50387*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x50388*4 +0x02000000,0x8003); +reg_write( DDR_REG_BASE +0x50389*4 +0x02000000,0x79a); +reg_write( DDR_REG_BASE +0x5038a*4 +0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x5038b*4 +0x02000000,0x2053); +reg_write( DDR_REG_BASE +0x5038c*4 +0x02000000,0x8083); +reg_write( DDR_REG_BASE +0x5038d*4 +0x02000000,0x78b0); +reg_write( DDR_REG_BASE +0x5038e*4 +0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x5038f*4 +0x02000000,0xf088); +reg_write( DDR_REG_BASE +0x50390*4 +0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x50391*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50392*4 +0x02000000,0x20c5); +reg_write( DDR_REG_BASE +0x50393*4 +0x02000000,0x61); +reg_write( DDR_REG_BASE +0x50394*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x50395*4 +0x02000000,0x72bd); +reg_write( DDR_REG_BASE +0x50396*4 +0x02000000,0x71dd); +reg_write( DDR_REG_BASE +0x50397*4 +0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x50398*4 +0x02000000,0xf088); +reg_write( DDR_REG_BASE +0x50399*4 +0x02000000,0xf211); +reg_write( DDR_REG_BASE +0x5039a*4 +0x02000000,0x2204); +reg_write( DDR_REG_BASE +0x5039b*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5039c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5039d*4 +0x02000000,0xfffe); +reg_write( DDR_REG_BASE +0x5039e*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5039f*4 +0x02000000,0x7e30); +reg_write( DDR_REG_BASE +0x503a0*4 +0x02000000,0x661e); +reg_write( DDR_REG_BASE +0x503a1*4 +0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x503a2*4 +0x02000000,0xe0c0); +reg_write( DDR_REG_BASE +0x503a3*4 +0x02000000,0xf74a); +reg_write( DDR_REG_BASE +0x503a4*4 +0x02000000,0x81b); +reg_write( DDR_REG_BASE +0x503a5*4 +0x02000000,0x835); +reg_write( DDR_REG_BASE +0x503a6*4 +0x02000000,0xdd40); +reg_write( DDR_REG_BASE +0x503a7*4 +0x02000000,0xde20); +reg_write( DDR_REG_BASE +0x503a8*4 +0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x503a9*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x503aa*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x503ab*4 +0x02000000,0xf033); +reg_write( DDR_REG_BASE +0x503ac*4 +0x02000000,0xe0df); +reg_write( DDR_REG_BASE +0x503ad*4 +0x02000000,0x45c9); +reg_write( DDR_REG_BASE +0x503ae*4 +0x02000000,0xf7c3); +reg_write( DDR_REG_BASE +0x503af*4 +0x02000000,0xdd5f); +reg_write( DDR_REG_BASE +0x503b0*4 +0x02000000,0xde5f); +reg_write( DDR_REG_BASE +0x503b1*4 +0x02000000,0x78af); +reg_write( DDR_REG_BASE +0x503b2*4 +0x02000000,0x792f); +reg_write( DDR_REG_BASE +0x503b3*4 +0x02000000,0xb16); +reg_write( DDR_REG_BASE +0x503b4*4 +0x02000000,0x160); +reg_write( DDR_REG_BASE +0x503b5*4 +0x02000000,0x7a4f); +reg_write( DDR_REG_BASE +0x503b6*4 +0x02000000,0x4308); +reg_write( DDR_REG_BASE +0x503b7*4 +0x02000000,0xb0e); +reg_write( DDR_REG_BASE +0x503b8*4 +0x02000000,0x160); +reg_write( DDR_REG_BASE +0x503b9*4 +0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x503ba*4 +0x02000000,0x2580); +reg_write( DDR_REG_BASE +0x503bb*4 +0x02000000,0x103f); +reg_write( DDR_REG_BASE +0x503bc*4 +0x02000000,0x79bb); +reg_write( DDR_REG_BASE +0x503bd*4 +0x02000000,0x2184); +reg_write( DDR_REG_BASE +0x503be*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x503bf*4 +0x02000000,0xbdc4); +reg_write( DDR_REG_BASE +0x503c0*4 +0x02000000,0x7d25); +reg_write( DDR_REG_BASE +0x503c1*4 +0x02000000,0xc190); +reg_write( DDR_REG_BASE +0x503c2*4 +0x02000000,0x79f4); +reg_write( DDR_REG_BASE +0x503c3*4 +0x02000000,0xb1a0); +reg_write( DDR_REG_BASE +0x503c4*4 +0x02000000,0x2642); +reg_write( DDR_REG_BASE +0x503c5*4 +0x02000000,0x1801); +reg_write( DDR_REG_BASE +0x503c6*4 +0x02000000,0x7a3b); +reg_write( DDR_REG_BASE +0x503c7*4 +0x02000000,0x2284); +reg_write( DDR_REG_BASE +0x503c8*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x503c9*4 +0x02000000,0xb9c4); +reg_write( DDR_REG_BASE +0x503ca*4 +0x02000000,0x7a25); +reg_write( DDR_REG_BASE +0x503cb*4 +0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x503cc*4 +0x02000000,0xc396); +reg_write( DDR_REG_BASE +0x503cd*4 +0x02000000,0x7bf4); +reg_write( DDR_REG_BASE +0x503ce*4 +0x02000000,0x7930); +reg_write( DDR_REG_BASE +0x503cf*4 +0x02000000,0x230c); +reg_write( DDR_REG_BASE +0x503d0*4 +0x02000000,0x9040); +reg_write( DDR_REG_BASE +0x503d1*4 +0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x503d2*4 +0x02000000,0xb340); +reg_write( DDR_REG_BASE +0x503d3*4 +0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x503d4*4 +0x02000000,0x2c5); +reg_write( DDR_REG_BASE +0x503d5*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x503d6*4 +0x02000000,0xc103); +reg_write( DDR_REG_BASE +0x503d7*4 +0x02000000,0x7930); +reg_write( DDR_REG_BASE +0x503d8*4 +0x02000000,0x7030); +reg_write( DDR_REG_BASE +0x503d9*4 +0x02000000,0xc103); +reg_write( DDR_REG_BASE +0x503da*4 +0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x503db*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x503dc*4 +0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x503dd*4 +0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x503de*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x503df*4 +0x02000000,0x7710); +reg_write( DDR_REG_BASE +0x503e0*4 +0x02000000,0x6d4); +reg_write( DDR_REG_BASE +0x503e1*4 +0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x503e2*4 +0x02000000,0xc09c); +reg_write( DDR_REG_BASE +0x503e3*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x503e4*4 +0x02000000,0x7910); +reg_write( DDR_REG_BASE +0x503e5*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x503e6*4 +0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x503e7*4 +0x02000000,0x843); +reg_write( DDR_REG_BASE +0x503e8*4 +0x02000000,0x65); +reg_write( DDR_REG_BASE +0x503e9*4 +0x02000000,0xc289); +reg_write( DDR_REG_BASE +0x503ea*4 +0x02000000,0x2216); +reg_write( DDR_REG_BASE +0x503eb*4 +0x02000000,0x782); +reg_write( DDR_REG_BASE +0x503ec*4 +0x02000000,0x8a06); +reg_write( DDR_REG_BASE +0x503ed*4 +0x02000000,0xdb40); +reg_write( DDR_REG_BASE +0x503ee*4 +0x02000000,0x2454); +reg_write( DDR_REG_BASE +0x503ef*4 +0x02000000,0x3b0b); +reg_write( DDR_REG_BASE +0x503f0*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x503f1*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x503f2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x503f3*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x503f4*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x503f5*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x503f6*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x503f7*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x503f8*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x503f9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x503fa*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x503fb*4 +0x02000000,0xb060); +reg_write( DDR_REG_BASE +0x503fc*4 +0x02000000,0x8a07); +reg_write( DDR_REG_BASE +0x503fd*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x503fe*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x503ff*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50400*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x50401*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x50402*4 +0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x50403*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x50404*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50405*4 +0x02000000,0xb060); +reg_write( DDR_REG_BASE +0x50406*4 +0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x50407*4 +0x02000000,0x2454); +reg_write( DDR_REG_BASE +0x50408*4 +0x02000000,0x380b); +reg_write( DDR_REG_BASE +0x50409*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5040a*4 +0x02000000,0xf015); +reg_write( DDR_REG_BASE +0x5040b*4 +0x02000000,0xc09c); +reg_write( DDR_REG_BASE +0x5040c*4 +0x02000000,0x6028); +reg_write( DDR_REG_BASE +0x5040d*4 +0x02000000,0xe25); +reg_write( DDR_REG_BASE +0x5040e*4 +0x02000000,0x3021); +reg_write( DDR_REG_BASE +0x5040f*4 +0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x50410*4 +0x02000000,0x3d40); +reg_write( DDR_REG_BASE +0x50411*4 +0x02000000,0x6028); +reg_write( DDR_REG_BASE +0x50412*4 +0x02000000,0x23f4); +reg_write( DDR_REG_BASE +0x50413*4 +0x02000000,0x1042); +reg_write( DDR_REG_BASE +0x50414*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50415*4 +0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x50416*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50417*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x50418*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x50419*4 +0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x5041a*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5041b*4 +0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x5041c*4 +0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x5041d*4 +0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x5041e*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x5041f*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50420*4 +0x02000000,0x9d7); +reg_write( DDR_REG_BASE +0x50421*4 +0x02000000,0x8004); +reg_write( DDR_REG_BASE +0x50422*4 +0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x50423*4 +0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x50424*4 +0x02000000,0x264c); +reg_write( DDR_REG_BASE +0x50425*4 +0x02000000,0xb080); +reg_write( DDR_REG_BASE +0x50426*4 +0x02000000,0x636); +reg_write( DDR_REG_BASE +0x50427*4 +0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x50428*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x50429*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5042a*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5042b*4 +0x02000000,0xa9); +reg_write( DDR_REG_BASE +0x5042c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5042d*4 +0x02000000,0x8fa); +reg_write( DDR_REG_BASE +0x5042e*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5042f*4 +0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x50430*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50431*4 +0x02000000,0x88a); +reg_write( DDR_REG_BASE +0x50432*4 +0x02000000,0x80); +reg_write( DDR_REG_BASE +0x50433*4 +0x02000000,0x9f6); +reg_write( DDR_REG_BASE +0x50434*4 +0x02000000,0x280); +reg_write( DDR_REG_BASE +0x50435*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50436*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50437*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50438*4 +0x02000000,0x1b); +reg_write( DDR_REG_BASE +0x50439*4 +0x02000000,0xb8e0); +reg_write( DDR_REG_BASE +0x5043a*4 +0x02000000,0xf9c); +reg_write( DDR_REG_BASE +0x5043b*4 +0x02000000,0xc2); +reg_write( DDR_REG_BASE +0x5043c*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x5043d*4 +0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x5043e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5043f*4 +0x02000000,0x334); +reg_write( DDR_REG_BASE +0x50440*4 +0x02000000,0x88e); +reg_write( DDR_REG_BASE +0x50441*4 +0x02000000,0x160); +reg_write( DDR_REG_BASE +0x50442*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50443*4 +0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x50444*4 +0x02000000,0x320d); +reg_write( DDR_REG_BASE +0x50445*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50446*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50447*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50448*4 +0x02000000,0xb8e6); +reg_write( DDR_REG_BASE +0x50449*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5044a*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5044b*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5044c*4 +0x02000000,0xb8c2); +reg_write( DDR_REG_BASE +0x5044d*4 +0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x5044e*4 +0x02000000,0xf403); +reg_write( DDR_REG_BASE +0x5044f*4 +0x02000000,0x7914); +reg_write( DDR_REG_BASE +0x50450*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x50451*4 +0x02000000,0x7915); +reg_write( DDR_REG_BASE +0x50452*4 +0x02000000,0x909); +reg_write( DDR_REG_BASE +0x50453*4 +0x02000000,0x354); +reg_write( DDR_REG_BASE +0x50454*4 +0x02000000,0x762c); +reg_write( DDR_REG_BASE +0x50455*4 +0x02000000,0x7915); +reg_write( DDR_REG_BASE +0x50456*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50457*4 +0x02000000,0x6901); +reg_write( DDR_REG_BASE +0x50458*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x50459*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5045a*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x5045b*4 +0x02000000,0x8a20); +reg_write( DDR_REG_BASE +0x5045c*4 +0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x5045d*4 +0x02000000,0xc81); +reg_write( DDR_REG_BASE +0x5045e*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x5045f*4 +0x02000000,0x8a21); +reg_write( DDR_REG_BASE +0x50460*4 +0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x50461*4 +0x02000000,0x641); +reg_write( DDR_REG_BASE +0x50462*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50463*4 +0x02000000,0x8903); +reg_write( DDR_REG_BASE +0x50464*4 +0x02000000,0xb8e6); +reg_write( DDR_REG_BASE +0x50465*4 +0x02000000,0x8902); +reg_write( DDR_REG_BASE +0x50466*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50467*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x50468*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50469*4 +0x02000000,0x1c); +reg_write( DDR_REG_BASE +0x5046a*4 +0x02000000,0xb8c2); +reg_write( DDR_REG_BASE +0x5046b*4 +0x02000000,0xf409); +reg_write( DDR_REG_BASE +0x5046c*4 +0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x5046d*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5046e*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5046f*4 +0x02000000,0x640); +reg_write( DDR_REG_BASE +0x50470*4 +0x02000000,0xf209); +reg_write( DDR_REG_BASE +0x50471*4 +0x02000000,0xe108); +reg_write( DDR_REG_BASE +0x50472*4 +0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x50473*4 +0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x50474*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50475*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50476*4 +0x02000000,0x630); +reg_write( DDR_REG_BASE +0x50477*4 +0x02000000,0xf203); +reg_write( DDR_REG_BASE +0x50478*4 +0x02000000,0xe108); +reg_write( DDR_REG_BASE +0x50479*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x5047a*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x5047b*4 +0x02000000,0x8900); +reg_write( DDR_REG_BASE +0x5047c*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5047d*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5047e*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5047f*4 +0x02000000,0xc1b5); +reg_write( DDR_REG_BASE +0x50480*4 +0x02000000,0xc254); +reg_write( DDR_REG_BASE +0x50481*4 +0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x50482*4 +0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x50483*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50484*4 +0x02000000,0xee); +reg_write( DDR_REG_BASE +0x50485*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50486*4 +0x02000000,0xdb2); +reg_write( DDR_REG_BASE +0x50487*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50488*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x50489*4 +0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x5048a*4 +0x02000000,0xf035); +reg_write( DDR_REG_BASE +0x5048b*4 +0x02000000,0x4261); +reg_write( DDR_REG_BASE +0x5048c*4 +0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x5048d*4 +0x02000000,0xc014); +reg_write( DDR_REG_BASE +0x5048e*4 +0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x5048f*4 +0x02000000,0x83); +reg_write( DDR_REG_BASE +0x50490*4 +0x02000000,0xc08e); +reg_write( DDR_REG_BASE +0x50491*4 +0x02000000,0x7834); +reg_write( DDR_REG_BASE +0x50492*4 +0x02000000,0xb060); +reg_write( DDR_REG_BASE +0x50493*4 +0x02000000,0x62ba); +reg_write( DDR_REG_BASE +0x50494*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x50495*4 +0x02000000,0x9f3); +reg_write( DDR_REG_BASE +0x50496*4 +0x02000000,0x8294); +reg_write( DDR_REG_BASE +0x50497*4 +0x02000000,0x4183); +reg_write( DDR_REG_BASE +0x50498*4 +0x02000000,0x911c); +reg_write( DDR_REG_BASE +0x50499*4 +0x02000000,0x1446); +reg_write( DDR_REG_BASE +0x5049a*4 +0x02000000,0x3103); +reg_write( DDR_REG_BASE +0x5049b*4 +0x02000000,0x915f); +reg_write( DDR_REG_BASE +0x5049c*4 +0x02000000,0xc053); +reg_write( DDR_REG_BASE +0x5049d*4 +0x02000000,0x1448); +reg_write( DDR_REG_BASE +0x5049e*4 +0x02000000,0x3101); +reg_write( DDR_REG_BASE +0x5049f*4 +0x02000000,0x144a); +reg_write( DDR_REG_BASE +0x504a0*4 +0x02000000,0x3100); +reg_write( DDR_REG_BASE +0x504a1*4 +0x02000000,0x143a); +reg_write( DDR_REG_BASE +0x504a2*4 +0x02000000,0x311f); +reg_write( DDR_REG_BASE +0x504a3*4 +0x02000000,0x143c); +reg_write( DDR_REG_BASE +0x504a4*4 +0x02000000,0x311e); +reg_write( DDR_REG_BASE +0x504a5*4 +0x02000000,0x1440); +reg_write( DDR_REG_BASE +0x504a6*4 +0x02000000,0x310f); +reg_write( DDR_REG_BASE +0x504a7*4 +0x02000000,0x1442); +reg_write( DDR_REG_BASE +0x504a8*4 +0x02000000,0x310e); +reg_write( DDR_REG_BASE +0x504a9*4 +0x02000000,0x1444); +reg_write( DDR_REG_BASE +0x504aa*4 +0x02000000,0x310c); +reg_write( DDR_REG_BASE +0x504ab*4 +0x02000000,0xc346); +reg_write( DDR_REG_BASE +0x504ac*4 +0x02000000,0xc313); +reg_write( DDR_REG_BASE +0x504ad*4 +0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x504ae*4 +0x02000000,0xc147); +reg_write( DDR_REG_BASE +0x504af*4 +0x02000000,0xc242); +reg_write( DDR_REG_BASE +0x504b0*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x504b1*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x504b2*4 +0x02000000,0xef); +reg_write( DDR_REG_BASE +0x504b3*4 +0x02000000,0xb); +reg_write( DDR_REG_BASE +0x504b4*4 +0x02000000,0xc445); +reg_write( DDR_REG_BASE +0x504b5*4 +0x02000000,0xc644); +reg_write( DDR_REG_BASE +0x504b6*4 +0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x504b7*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x504b8*4 +0x02000000,0x3780); +reg_write( DDR_REG_BASE +0x504b9*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x504ba*4 +0x02000000,0x37c0); +reg_write( DDR_REG_BASE +0x504bb*4 +0x02000000,0xd4a); +reg_write( DDR_REG_BASE +0x504bc*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x504bd*4 +0x02000000,0x4261); +reg_write( DDR_REG_BASE +0x504be*4 +0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x504bf*4 +0x02000000,0x232f); +reg_write( DDR_REG_BASE +0x504c0*4 +0x02000000,0x16c8); +reg_write( DDR_REG_BASE +0x504c1*4 +0x02000000,0xb97); +reg_write( DDR_REG_BASE +0x504c2*4 +0x02000000,0x9364); +reg_write( DDR_REG_BASE +0x504c3*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x504c4*4 +0x02000000,0xc0b5); +reg_write( DDR_REG_BASE +0x504c5*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x504c6*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x504c7*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x504c8*4 +0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x504c9*4 +0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x504ca*4 +0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x504cb*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x504cc*4 +0x02000000,0x866); +reg_write( DDR_REG_BASE +0x504cd*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x504ce*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x504cf*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x504d0*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x504d1*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x504d2*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x504d3*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x504d4*4 +0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x504d5*4 +0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x504d6*4 +0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x504d7*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x504d8*4 +0x02000000,0x926); +reg_write( DDR_REG_BASE +0x504d9*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x504da*4 +0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x504db*4 +0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x504dc*4 +0x02000000,0x1100); +reg_write( DDR_REG_BASE +0x504dd*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x504de*4 +0x02000000,0xb98d); +reg_write( DDR_REG_BASE +0x504df*4 +0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x504e0*4 +0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x504e1*4 +0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x504e2*4 +0x02000000,0xf03); +reg_write( DDR_REG_BASE +0x504e3*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x504e4*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x504e5*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x504e6*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x504e7*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x504e8*4 +0x02000000,0x906); +reg_write( DDR_REG_BASE +0x504e9*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x504ea*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x504eb*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x504ec*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x504ed*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x504ee*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x504ef*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x504f0*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x504f1*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x504f2*4 +0x02000000,0x8f2); +reg_write( DDR_REG_BASE +0x504f3*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x504f4*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x504f5*4 +0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x504f6*4 +0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x504f7*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x504f8*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x504f9*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x504fa*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x504fb*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x504fc*4 +0x02000000,0x102); +reg_write( DDR_REG_BASE +0x504fd*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x504fe*4 +0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x504ff*4 +0x02000000,0x4308); +reg_write( DDR_REG_BASE +0x50500*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50501*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50502*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x50503*4 +0x02000000,0x1e4); +reg_write( DDR_REG_BASE +0x50504*4 +0x02000000,0x218c); +reg_write( DDR_REG_BASE +0x50505*4 +0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x50506*4 +0x02000000,0xb6a0); +reg_write( DDR_REG_BASE +0x50507*4 +0x02000000,0xb6a1); +reg_write( DDR_REG_BASE +0x50508*4 +0x02000000,0xb6a2); +reg_write( DDR_REG_BASE +0x50509*4 +0x02000000,0xf224); +reg_write( DDR_REG_BASE +0x5050a*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5050b*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5050c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5050d*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5050e*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x5050f*4 +0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x50510*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50511*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50512*4 +0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x50513*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50514*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50515*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x50516*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x50517*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50518*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50519*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x5051a*4 +0x02000000,0x8881); +reg_write( DDR_REG_BASE +0x5051b*4 +0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x5051c*4 +0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x5051d*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x5051e*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x5051f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50520*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x50521*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x50522*4 +0x02000000,0x7a65); +reg_write( DDR_REG_BASE +0x50523*4 +0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x50524*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x50525*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50526*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x50527*4 +0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x50528*4 +0x02000000,0xceb); +reg_write( DDR_REG_BASE +0x50529*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x5052a*4 +0x02000000,0x806); +reg_write( DDR_REG_BASE +0x5052b*4 +0x02000000,0x280); +reg_write( DDR_REG_BASE +0x5052c*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x5052d*4 +0x02000000,0x21a); +reg_write( DDR_REG_BASE +0x5052e*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5052f*4 +0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x50530*4 +0x02000000,0x2a); +reg_write( DDR_REG_BASE +0x50531*4 +0x02000000,0x1efc); +reg_write( DDR_REG_BASE +0x50532*4 +0x02000000,0x92c4); +reg_write( DDR_REG_BASE +0x50533*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x50534*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50535*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50536*4 +0x02000000,0x446); +reg_write( DDR_REG_BASE +0x50537*4 +0x02000000,0xa8a0); +reg_write( DDR_REG_BASE +0x50538*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50539*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5053a*4 +0x02000000,0xfac); +reg_write( DDR_REG_BASE +0x5053b*4 +0x02000000,0xb101); +reg_write( DDR_REG_BASE +0x5053c*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5053d*4 +0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x5053e*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5053f*4 +0x02000000,0x7210); +reg_write( DDR_REG_BASE +0x50540*4 +0x02000000,0x20e0); +reg_write( DDR_REG_BASE +0x50541*4 +0x02000000,0x7ca); +reg_write( DDR_REG_BASE +0x50542*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50543*4 +0x02000000,0x7101); +reg_write( DDR_REG_BASE +0x50544*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x50545*4 +0x02000000,0x1d6); +reg_write( DDR_REG_BASE +0x50546*4 +0x02000000,0x9f3); +reg_write( DDR_REG_BASE +0x50547*4 +0x02000000,0x803e); +reg_write( DDR_REG_BASE +0x50548*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x50549*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5054a*4 +0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x5054b*4 +0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x5054c*4 +0x02000000,0xe52); +reg_write( DDR_REG_BASE +0x5054d*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5054e*4 +0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x5054f*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x50550*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x50551*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50552*4 +0x02000000,0xf2); +reg_write( DDR_REG_BASE +0x50553*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50554*4 +0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x50555*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50556*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x50557*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50558*4 +0x02000000,0x7784); +reg_write( DDR_REG_BASE +0x50559*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x5055a*4 +0x02000000,0x1e2); +reg_write( DDR_REG_BASE +0x5055b*4 +0x02000000,0xdd2); +reg_write( DDR_REG_BASE +0x5055c*4 +0x02000000,0x160); +reg_write( DDR_REG_BASE +0x5055d*4 +0x02000000,0x760c); +reg_write( DDR_REG_BASE +0x5055e*4 +0x02000000,0xb17); +reg_write( DDR_REG_BASE +0x5055f*4 +0x02000000,0x1030); +reg_write( DDR_REG_BASE +0x50560*4 +0x02000000,0x1d10); +reg_write( DDR_REG_BASE +0x50561*4 +0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x50562*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50563*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50564*4 +0x02000000,0x61a8); +reg_write( DDR_REG_BASE +0x50565*4 +0x02000000,0xfb6); +reg_write( DDR_REG_BASE +0x50566*4 +0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x50567*4 +0x02000000,0x1d10); +reg_write( DDR_REG_BASE +0x50568*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x50569*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x5056a*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5056b*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5056c*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5056d*4 +0x02000000,0xc1a6); +reg_write( DDR_REG_BASE +0x5056e*4 +0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x5056f*4 +0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x50570*4 +0x02000000,0xc20b); +reg_write( DDR_REG_BASE +0x50571*4 +0x02000000,0xc345); +reg_write( DDR_REG_BASE +0x50572*4 +0x02000000,0xdb7f); +reg_write( DDR_REG_BASE +0x50573*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50574*4 +0x02000000,0x7b44); +reg_write( DDR_REG_BASE +0x50575*4 +0x02000000,0xd84b); +reg_write( DDR_REG_BASE +0x50576*4 +0x02000000,0x2338); +reg_write( DDR_REG_BASE +0x50577*4 +0x02000000,0xf); +reg_write( DDR_REG_BASE +0x50578*4 +0x02000000,0x279a); +reg_write( DDR_REG_BASE +0x50579*4 +0x02000000,0x1002); +reg_write( DDR_REG_BASE +0x5057a*4 +0x02000000,0xbae6); +reg_write( DDR_REG_BASE +0x5057b*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x5057c*4 +0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x5057d*4 +0x02000000,0x234f); +reg_write( DDR_REG_BASE +0x5057e*4 +0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x5057f*4 +0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x50580*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x50581*4 +0x02000000,0xe4cf); +reg_write( DDR_REG_BASE +0x50582*4 +0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x50583*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x50584*4 +0x02000000,0xe3d1); +reg_write( DDR_REG_BASE +0x50585*4 +0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x50586*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x50587*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50588*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50589*4 +0x02000000,0x7083); +reg_write( DDR_REG_BASE +0x5058a*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5058b*4 +0x02000000,0x446); +reg_write( DDR_REG_BASE +0x5058c*4 +0x02000000,0x1400); +reg_write( DDR_REG_BASE +0x5058d*4 +0x02000000,0x301f); +reg_write( DDR_REG_BASE +0x5058e*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x5058f*4 +0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x50590*4 +0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x50591*4 +0x02000000,0x2642); +reg_write( DDR_REG_BASE +0x50592*4 +0x02000000,0x304b); +reg_write( DDR_REG_BASE +0x50593*4 +0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x50594*4 +0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x50595*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x50596*4 +0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x50597*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x50598*4 +0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x50599*4 +0x02000000,0xb51); +reg_write( DDR_REG_BASE +0x5059a*4 +0x02000000,0x16b5); +reg_write( DDR_REG_BASE +0x5059b*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5059c*4 +0x02000000,0xdb50); +reg_write( DDR_REG_BASE +0x5059d*4 +0x02000000,0xc341); +reg_write( DDR_REG_BASE +0x5059e*4 +0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x5059f*4 +0x02000000,0xd810); +reg_write( DDR_REG_BASE +0x505a0*4 +0x02000000,0xde30); +reg_write( DDR_REG_BASE +0x505a1*4 +0x02000000,0xdd60); +reg_write( DDR_REG_BASE +0x505a2*4 +0x02000000,0x4378); +reg_write( DDR_REG_BASE +0x505a3*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x505a4*4 +0x02000000,0x2025); +reg_write( DDR_REG_BASE +0x505a5*4 +0x02000000,0x2c0); +reg_write( DDR_REG_BASE +0x505a6*4 +0x02000000,0xf01a); +reg_write( DDR_REG_BASE +0x505a7*4 +0x02000000,0xf01a); +reg_write( DDR_REG_BASE +0x505a8*4 +0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x505a9*4 +0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x505aa*4 +0x02000000,0xf05c); +reg_write( DDR_REG_BASE +0x505ab*4 +0x02000000,0xf019); +reg_write( DDR_REG_BASE +0x505ac*4 +0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x505ad*4 +0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x505ae*4 +0x02000000,0xf045); +reg_write( DDR_REG_BASE +0x505af*4 +0x02000000,0xf048); +reg_write( DDR_REG_BASE +0x505b0*4 +0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x505b1*4 +0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x505b2*4 +0x02000000,0xf047); +reg_write( DDR_REG_BASE +0x505b3*4 +0x02000000,0xf03b); +reg_write( DDR_REG_BASE +0x505b4*4 +0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x505b5*4 +0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x505b6*4 +0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x505b7*4 +0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x505b8*4 +0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x505b9*4 +0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x505ba*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x505bb*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x505bc*4 +0x02000000,0xf03f); +reg_write( DDR_REG_BASE +0x505bd*4 +0x02000000,0xf034); +reg_write( DDR_REG_BASE +0x505be*4 +0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x505bf*4 +0x02000000,0xf0a8); +reg_write( DDR_REG_BASE +0x505c0*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x505c1*4 +0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x505c2*4 +0x02000000,0xdb10); +reg_write( DDR_REG_BASE +0x505c3*4 +0x02000000,0x264c); +reg_write( DDR_REG_BASE +0x505c4*4 +0x02000000,0xb640); +reg_write( DDR_REG_BASE +0x505c5*4 +0x02000000,0x14a); +reg_write( DDR_REG_BASE +0x505c6*4 +0x02000000,0x2d); +reg_write( DDR_REG_BASE +0x505c7*4 +0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x505c8*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x505c9*4 +0x02000000,0x748d); +reg_write( DDR_REG_BASE +0x505ca*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x505cb*4 +0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x505cc*4 +0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x505cd*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x505ce*4 +0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x505cf*4 +0x02000000,0x2025); +reg_write( DDR_REG_BASE +0x505d0*4 +0x02000000,0x780); +reg_write( DDR_REG_BASE +0x505d1*4 +0x02000000,0xf036); +reg_write( DDR_REG_BASE +0x505d2*4 +0x02000000,0xf02c); +reg_write( DDR_REG_BASE +0x505d3*4 +0x02000000,0xf02b); +reg_write( DDR_REG_BASE +0x505d4*4 +0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x505d5*4 +0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x505d6*4 +0x02000000,0xf093); +reg_write( DDR_REG_BASE +0x505d7*4 +0x02000000,0xf099); +reg_write( DDR_REG_BASE +0x505d8*4 +0x02000000,0xf093); +reg_write( DDR_REG_BASE +0x505d9*4 +0x02000000,0xf015); +reg_write( DDR_REG_BASE +0x505da*4 +0x02000000,0xf019); +reg_write( DDR_REG_BASE +0x505db*4 +0x02000000,0xf01c); +reg_write( DDR_REG_BASE +0x505dc*4 +0x02000000,0xf091); +reg_write( DDR_REG_BASE +0x505dd*4 +0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x505de*4 +0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x505df*4 +0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x505e0*4 +0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x505e1*4 +0x02000000,0xf089); +reg_write( DDR_REG_BASE +0x505e2*4 +0x02000000,0xf087); +reg_write( DDR_REG_BASE +0x505e3*4 +0x02000000,0xf087); +reg_write( DDR_REG_BASE +0x505e4*4 +0x02000000,0xf085); +reg_write( DDR_REG_BASE +0x505e5*4 +0x02000000,0xf085); +reg_write( DDR_REG_BASE +0x505e6*4 +0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x505e7*4 +0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x505e8*4 +0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x505e9*4 +0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x505ea*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x505eb*4 +0x02000000,0xdb07); +reg_write( DDR_REG_BASE +0x505ec*4 +0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x505ed*4 +0x02000000,0xc701); +reg_write( DDR_REG_BASE +0x505ee*4 +0x02000000,0x758d); +reg_write( DDR_REG_BASE +0x505ef*4 +0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x505f0*4 +0x02000000,0x758d); +reg_write( DDR_REG_BASE +0x505f1*4 +0x02000000,0x47a9); +reg_write( DDR_REG_BASE +0x505f2*4 +0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x505f3*4 +0x02000000,0x758d); +reg_write( DDR_REG_BASE +0x505f4*4 +0x02000000,0x47c9); +reg_write( DDR_REG_BASE +0x505f5*4 +0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x505f6*4 +0x02000000,0x718d); +reg_write( DDR_REG_BASE +0x505f7*4 +0x02000000,0x476b); +reg_write( DDR_REG_BASE +0x505f8*4 +0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x505f9*4 +0x02000000,0x768d); +reg_write( DDR_REG_BASE +0x505fa*4 +0x02000000,0xf00b); +reg_write( DDR_REG_BASE +0x505fb*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x505fc*4 +0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x505fd*4 +0x02000000,0x736c); +reg_write( DDR_REG_BASE +0x505fe*4 +0x02000000,0xe0d); +reg_write( DDR_REG_BASE +0x505ff*4 +0x02000000,0x30d1); +reg_write( DDR_REG_BASE +0x50600*4 +0x02000000,0xc402); +reg_write( DDR_REG_BASE +0x50601*4 +0x02000000,0x249a); +reg_write( DDR_REG_BASE +0x50602*4 +0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x50603*4 +0x02000000,0x7a85); +reg_write( DDR_REG_BASE +0x50604*4 +0x02000000,0x4468); +reg_write( DDR_REG_BASE +0x50605*4 +0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x50606*4 +0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x50607*4 +0x02000000,0xffd); +reg_write( DDR_REG_BASE +0x50608*4 +0x02000000,0x7b24); +reg_write( DDR_REG_BASE +0x50609*4 +0x02000000,0x783d); +reg_write( DDR_REG_BASE +0x5060a*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x5060b*4 +0x02000000,0xc0b); +reg_write( DDR_REG_BASE +0x5060c*4 +0x02000000,0xe3b0); +reg_write( DDR_REG_BASE +0x5060d*4 +0x02000000,0xdb58); +reg_write( DDR_REG_BASE +0x5060e*4 +0x02000000,0x23cf); +reg_write( DDR_REG_BASE +0x5060f*4 +0x02000000,0x11e1); +reg_write( DDR_REG_BASE +0x50610*4 +0x02000000,0x7b24); +reg_write( DDR_REG_BASE +0x50611*4 +0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x50612*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50613*4 +0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x50614*4 +0x02000000,0x2c3); +reg_write( DDR_REG_BASE +0x50615*4 +0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x50616*4 +0x02000000,0x7b05); +reg_write( DDR_REG_BASE +0x50617*4 +0x02000000,0x783d); +reg_write( DDR_REG_BASE +0x50618*4 +0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x50619*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5061a*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5061b*4 +0x02000000,0xc405); +reg_write( DDR_REG_BASE +0x5061c*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5061d*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x5061e*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5061f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50620*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x50621*4 +0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x50622*4 +0x02000000,0x7c65); +reg_write( DDR_REG_BASE +0x50623*4 +0x02000000,0x232f); +reg_write( DDR_REG_BASE +0x50624*4 +0x02000000,0x17c0); +reg_write( DDR_REG_BASE +0x50625*4 +0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x50626*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x50627*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50628*4 +0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x50629*4 +0x02000000,0x10c0); +reg_write( DDR_REG_BASE +0x5062a*4 +0x02000000,0xb080); +reg_write( DDR_REG_BASE +0x5062b*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x5062c*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x5062d*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5062e*4 +0x02000000,0x7154); +reg_write( DDR_REG_BASE +0x5062f*4 +0x02000000,0x2104); +reg_write( DDR_REG_BASE +0x50630*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x50631*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50632*4 +0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x50633*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x50634*4 +0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x50635*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50636*4 +0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x50637*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50638*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50639*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5063a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5063b*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x5063c*4 +0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x5063d*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x5063e*4 +0x02000000,0x20cf); +reg_write( DDR_REG_BASE +0x5063f*4 +0x02000000,0x1a1); +reg_write( DDR_REG_BASE +0x50640*4 +0x02000000,0x264c); +reg_write( DDR_REG_BASE +0x50641*4 +0x02000000,0xb180); +reg_write( DDR_REG_BASE +0x50642*4 +0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x50643*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x50644*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x50645*4 +0x02000000,0xb8c3); +reg_write( DDR_REG_BASE +0x50646*4 +0x02000000,0x7f05); +reg_write( DDR_REG_BASE +0x50647*4 +0x02000000,0x78ef); +reg_write( DDR_REG_BASE +0x50648*4 +0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x50649*4 +0x02000000,0x2354); +reg_write( DDR_REG_BASE +0x5064a*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x5064b*4 +0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x5064c*4 +0x02000000,0xb080); +reg_write( DDR_REG_BASE +0x5064d*4 +0x02000000,0x2355); +reg_write( DDR_REG_BASE +0x5064e*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x5064f*4 +0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x50650*4 +0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x50651*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x50652*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x50653*4 +0x02000000,0x2355); +reg_write( DDR_REG_BASE +0x50654*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x50655*4 +0x02000000,0x7b05); +reg_write( DDR_REG_BASE +0x50656*4 +0x02000000,0xb320); +reg_write( DDR_REG_BASE +0x50657*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50658*4 +0x02000000,0x2740); +reg_write( DDR_REG_BASE +0x50659*4 +0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x5065a*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x5065b*4 +0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x5065c*4 +0x02000000,0xf405); +reg_write( DDR_REG_BASE +0x5065d*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5065e*4 +0x02000000,0x7042); +reg_write( DDR_REG_BASE +0x5065f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50660*4 +0x02000000,0x446); +reg_write( DDR_REG_BASE +0x50661*4 +0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x50662*4 +0x02000000,0xc0a6); +reg_write( DDR_REG_BASE +0x50663*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50664*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50665*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50666*4 +0x02000000,0x738d); +reg_write( DDR_REG_BASE +0x50667*4 +0x02000000,0xdf10); +reg_write( DDR_REG_BASE +0x50668*4 +0x02000000,0xf19e); +reg_write( DDR_REG_BASE +0x50669*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x5066a*4 +0x02000000,0xf19b); +reg_write( DDR_REG_BASE +0x5066b*4 +0x02000000,0x718d); +reg_write( DDR_REG_BASE +0x5066c*4 +0x02000000,0xf199); +reg_write( DDR_REG_BASE +0x5066d*4 +0x02000000,0xdc20); +reg_write( DDR_REG_BASE +0x5066e*4 +0x02000000,0xf197); +reg_write( DDR_REG_BASE +0x5066f*4 +0x02000000,0x758d); +reg_write( DDR_REG_BASE +0x50670*4 +0x02000000,0xf195); +reg_write( DDR_REG_BASE +0x50671*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50672*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x50673*4 +0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x50674*4 +0x02000000,0xc408); +reg_write( DDR_REG_BASE +0x50675*4 +0x02000000,0xc443); +reg_write( DDR_REG_BASE +0x50676*4 +0x02000000,0xc407); +reg_write( DDR_REG_BASE +0x50677*4 +0x02000000,0xc442); +reg_write( DDR_REG_BASE +0x50678*4 +0x02000000,0xc406); +reg_write( DDR_REG_BASE +0x50679*4 +0x02000000,0xc441); +reg_write( DDR_REG_BASE +0x5067a*4 +0x02000000,0xc405); +reg_write( DDR_REG_BASE +0x5067b*4 +0x02000000,0xde2); +reg_write( DDR_REG_BASE +0x5067c*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5067d*4 +0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x5067e*4 +0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x5067f*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x50680*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50681*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50682*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50683*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50684*4 +0x02000000,0x446); +reg_write( DDR_REG_BASE +0x50685*4 +0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x50686*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x50687*4 +0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x50688*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x50689*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x5068a*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5068b*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x5068c*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x5068d*4 +0x02000000,0x1e8); +reg_write( DDR_REG_BASE +0x5068e*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5068f*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50690*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50691*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50692*4 +0x02000000,0x446); +reg_write( DDR_REG_BASE +0x50693*4 +0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x50694*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x50695*4 +0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x50696*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x50697*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x50698*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50699*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x5069a*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x5069b*4 +0x02000000,0x1e6); +reg_write( DDR_REG_BASE +0x5069c*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5069d*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5069e*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5069f*4 +0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x506a0*4 +0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x506a1*4 +0x02000000,0x9160); +reg_write( DDR_REG_BASE +0x506a2*4 +0x02000000,0x9141); +reg_write( DDR_REG_BASE +0x506a3*4 +0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x506a4*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x506a5*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x506a6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x506a7*4 +0x02000000,0x7965); +reg_write( DDR_REG_BASE +0x506a8*4 +0x02000000,0xe807); +reg_write( DDR_REG_BASE +0x506a9*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x506aa*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x506ab*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x506ac*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x506ad*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x506ae*4 +0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x506af*4 +0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x506b0*4 +0x02000000,0xda0f); +reg_write( DDR_REG_BASE +0x506b1*4 +0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x506b2*4 +0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x506b3*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x506b4*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x506b5*4 +0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x506b6*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x506b7*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x506b8*4 +0x02000000,0x900f); +reg_write( DDR_REG_BASE +0x506b9*4 +0x02000000,0xfe4c); +reg_write( DDR_REG_BASE +0x506ba*4 +0x02000000,0xda10); +reg_write( DDR_REG_BASE +0x506bb*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x506bc*4 +0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x506bd*4 +0x02000000,0xa01); +reg_write( DDR_REG_BASE +0x506be*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x506bf*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x506c0*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x506c1*4 +0x02000000,0xb101); +reg_write( DDR_REG_BASE +0x506c2*4 +0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x506c3*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x506c4*4 +0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x506c5*4 +0x02000000,0x265a); +reg_write( DDR_REG_BASE +0x506c6*4 +0x02000000,0x3c83); +reg_write( DDR_REG_BASE +0x506c7*4 +0x02000000,0x607c); +reg_write( DDR_REG_BASE +0x506c8*4 +0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x506c9*4 +0x02000000,0x1643); +reg_write( DDR_REG_BASE +0x506ca*4 +0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x506cb*4 +0x02000000,0x639b); +reg_write( DDR_REG_BASE +0x506cc*4 +0x02000000,0x633b); +reg_write( DDR_REG_BASE +0x506cd*4 +0x02000000,0x8b80); +reg_write( DDR_REG_BASE +0x506ce*4 +0x02000000,0x7c44); +reg_write( DDR_REG_BASE +0x506cf*4 +0x02000000,0xab80); +reg_write( DDR_REG_BASE +0x506d0*4 +0x02000000,0xbeb); +reg_write( DDR_REG_BASE +0x506d1*4 +0x02000000,0x9094); +reg_write( DDR_REG_BASE +0x506d2*4 +0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x506d3*4 +0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x506d4*4 +0x02000000,0xef9); +reg_write( DDR_REG_BASE +0x506d5*4 +0x02000000,0xb0b4); +reg_write( DDR_REG_BASE +0x506d6*4 +0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x506d7*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x506d8*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x506d9*4 +0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x506da*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x506db*4 +0x02000000,0xc4a); +reg_write( DDR_REG_BASE +0x506dc*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x506dd*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x506de*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x506df*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x506e0*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x506e1*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x506e2*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x506e3*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x506e4*4 +0x02000000,0xd988); +reg_write( DDR_REG_BASE +0x506e5*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x506e6*4 +0x02000000,0xd0a); +reg_write( DDR_REG_BASE +0x506e7*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x506e8*4 +0x02000000,0xdb40); +reg_write( DDR_REG_BASE +0x506e9*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x506ea*4 +0x02000000,0xcc2); +reg_write( DDR_REG_BASE +0x506eb*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x506ec*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x506ed*4 +0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x506ee*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x506ef*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x506f0*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x506f1*4 +0x02000000,0x20c0); +reg_write( DDR_REG_BASE +0x506f2*4 +0x02000000,0xfe9); +reg_write( DDR_REG_BASE +0x506f3*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x506f4*4 +0x02000000,0x2884); +reg_write( DDR_REG_BASE +0x506f5*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x506f6*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x506f7*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x506f8*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x506f9*4 +0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x506fa*4 +0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x506fb*4 +0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x506fc*4 +0x02000000,0x641); +reg_write( DDR_REG_BASE +0x506fd*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x506fe*4 +0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x506ff*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x50700*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x50701*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50702*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50703*4 +0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x50704*4 +0x02000000,0x8803); +reg_write( DDR_REG_BASE +0x50705*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50706*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50707*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50708*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50709*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5070a*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5070b*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x5070c*4 +0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x5070d*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5070e*4 +0x02000000,0x917); +reg_write( DDR_REG_BASE +0x5070f*4 +0x02000000,0x3f0); +reg_write( DDR_REG_BASE +0x50710*4 +0x02000000,0x228a); +reg_write( DDR_REG_BASE +0x50711*4 +0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x50712*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x50713*4 +0x02000000,0xb9c4); +reg_write( DDR_REG_BASE +0x50714*4 +0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x50715*4 +0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x50716*4 +0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x50717*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x50718*4 +0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x50719*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x5071a*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5071b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5071c*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x5071d*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5071e*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x5071f*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50720*4 +0x02000000,0x16a); +reg_write( DDR_REG_BASE +0x50721*4 +0x02000000,0x224f); +reg_write( DDR_REG_BASE +0x50722*4 +0x02000000,0x240); +reg_write( DDR_REG_BASE +0x50723*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50724*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x50725*4 +0x02000000,0xb140); +reg_write( DDR_REG_BASE +0x50726*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x50727*4 +0x02000000,0xb140); +reg_write( DDR_REG_BASE +0x50728*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50729*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x5072a*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x5072b*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5072c*4 +0x02000000,0x80d); +reg_write( DDR_REG_BASE +0x5072d*4 +0x02000000,0x72); +reg_write( DDR_REG_BASE +0x5072e*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5072f*4 +0x02000000,0x48ff); +reg_write( DDR_REG_BASE +0x50730*4 +0x02000000,0x2984); +reg_write( DDR_REG_BASE +0x50731*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50732*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50733*4 +0x02000000,0x782e); +reg_write( DDR_REG_BASE +0x50734*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x50735*4 +0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x50736*4 +0x02000000,0xe9a); +reg_write( DDR_REG_BASE +0x50737*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50738*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x50739*4 +0x02000000,0x795b); +reg_write( DDR_REG_BASE +0x5073a*4 +0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x5073b*4 +0x02000000,0x181); +reg_write( DDR_REG_BASE +0x5073c*4 +0x02000000,0xb9c4); +reg_write( DDR_REG_BASE +0x5073d*4 +0x02000000,0xe906); +reg_write( DDR_REG_BASE +0x5073e*4 +0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x5073f*4 +0x02000000,0x901); +reg_write( DDR_REG_BASE +0x50740*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x50741*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50742*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x50743*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50744*4 +0x02000000,0xb8c1); +reg_write( DDR_REG_BASE +0x50745*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50746*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x50747*4 +0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x50748*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50749*4 +0x02000000,0xb6e); +reg_write( DDR_REG_BASE +0x5074a*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5074b*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x5074c*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5074d*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5074e*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5074f*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x50750*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50751*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50752*4 +0x02000000,0xd990); +reg_write( DDR_REG_BASE +0x50753*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x50754*4 +0x02000000,0xc2e); +reg_write( DDR_REG_BASE +0x50755*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50756*4 +0x02000000,0xdb40); +reg_write( DDR_REG_BASE +0x50757*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50758*4 +0x02000000,0xbe6); +reg_write( DDR_REG_BASE +0x50759*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5075a*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5075b*4 +0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x5075c*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x5075d*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5075e*4 +0x02000000,0xc3e1); +reg_write( DDR_REG_BASE +0x5075f*4 +0x02000000,0xc2e1); +reg_write( DDR_REG_BASE +0x50760*4 +0x02000000,0xc1e1); +reg_write( DDR_REG_BASE +0x50761*4 +0x02000000,0xc0e1); +reg_write( DDR_REG_BASE +0x50762*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x50763*4 +0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x50764*4 +0x02000000,0x4220); +reg_write( DDR_REG_BASE +0x50765*4 +0x02000000,0xc184); +reg_write( DDR_REG_BASE +0x50766*4 +0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x50767*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50768*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x50769*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5076a*4 +0x02000000,0x12); +reg_write( DDR_REG_BASE +0x5076b*4 +0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x5076c*4 +0x02000000,0x64); +reg_write( DDR_REG_BASE +0x5076d*4 +0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x5076e*4 +0x02000000,0xb1e); +reg_write( DDR_REG_BASE +0x5076f*4 +0x02000000,0x2e0); +reg_write( DDR_REG_BASE +0x50770*4 +0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x50771*4 +0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x50772*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x50773*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50774*4 +0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x50775*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50776*4 +0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x50777*4 +0x02000000,0x216c); +reg_write( DDR_REG_BASE +0x50778*4 +0x02000000,0x102); +reg_write( DDR_REG_BASE +0x50779*4 +0x02000000,0x206c); +reg_write( DDR_REG_BASE +0x5077a*4 +0x02000000,0x141); +reg_write( DDR_REG_BASE +0x5077b*4 +0x02000000,0x7822); +reg_write( DDR_REG_BASE +0x5077c*4 +0x02000000,0x621a); +reg_write( DDR_REG_BASE +0x5077d*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x5077e*4 +0x02000000,0x784e); +reg_write( DDR_REG_BASE +0x5077f*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50780*4 +0x02000000,0xc0e6); +reg_write( DDR_REG_BASE +0x50781*4 +0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x50782*4 +0x02000000,0x483); +reg_write( DDR_REG_BASE +0x50783*4 +0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x50784*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50785*4 +0x02000000,0x6e2); +reg_write( DDR_REG_BASE +0x50786*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x50787*4 +0x02000000,0x638d); +reg_write( DDR_REG_BASE +0x50788*4 +0x02000000,0x6479); +reg_write( DDR_REG_BASE +0x50789*4 +0x02000000,0x8941); +reg_write( DDR_REG_BASE +0x5078a*4 +0x02000000,0x7d04); +reg_write( DDR_REG_BASE +0x5078b*4 +0x02000000,0xf00b); +reg_write( DDR_REG_BASE +0x5078c*4 +0x02000000,0x6199); +reg_write( DDR_REG_BASE +0x5078d*4 +0x02000000,0x89e2); +reg_write( DDR_REG_BASE +0x5078e*4 +0x02000000,0x7f0b); +reg_write( DDR_REG_BASE +0x5078f*4 +0x02000000,0xf206); +reg_write( DDR_REG_BASE +0x50790*4 +0x02000000,0x89e3); +reg_write( DDR_REG_BASE +0x50791*4 +0x02000000,0x79af); +reg_write( DDR_REG_BASE +0x50792*4 +0x02000000,0x210f); +reg_write( DDR_REG_BASE +0x50793*4 +0x02000000,0x3cd); +reg_write( DDR_REG_BASE +0x50794*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x50795*4 +0x02000000,0xef1); +reg_write( DDR_REG_BASE +0x50796*4 +0x02000000,0x90a4); +reg_write( DDR_REG_BASE +0x50797*4 +0x02000000,0x2314); +reg_write( DDR_REG_BASE +0x50798*4 +0x02000000,0x381); +reg_write( DDR_REG_BASE +0x50799*4 +0x02000000,0x78af); +reg_write( DDR_REG_BASE +0x5079a*4 +0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x5079b*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5079c*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5079d*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5079e*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5079f*4 +0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x507a0*4 +0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x507a1*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x507a2*4 +0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x507a3*4 +0x02000000,0xb0e); +reg_write( DDR_REG_BASE +0x507a4*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x507a5*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x507a6*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x507a7*4 +0x02000000,0x43a9); +reg_write( DDR_REG_BASE +0x507a8*4 +0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x507a9*4 +0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x507aa*4 +0x02000000,0x641); +reg_write( DDR_REG_BASE +0x507ab*4 +0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x507ac*4 +0x02000000,0x1c80); +reg_write( DDR_REG_BASE +0x507ad*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x507ae*4 +0x02000000,0xdda); +reg_write( DDR_REG_BASE +0x507af*4 +0x02000000,0x260); +reg_write( DDR_REG_BASE +0x507b0*4 +0x02000000,0x60f8); +reg_write( DDR_REG_BASE +0x507b1*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x507b2*4 +0x02000000,0xbef); +reg_write( DDR_REG_BASE +0x507b3*4 +0x02000000,0x8094); +reg_write( DDR_REG_BASE +0x507b4*4 +0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x507b5*4 +0x02000000,0xbfd); +reg_write( DDR_REG_BASE +0x507b6*4 +0x02000000,0x90b4); +reg_write( DDR_REG_BASE +0x507b7*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x507b8*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x507b9*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x507ba*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x507bb*4 +0x02000000,0xa8ae); +reg_write( DDR_REG_BASE +0x507bc*4 +0x02000000,0xa8a1); +reg_write( DDR_REG_BASE +0x507bd*4 +0x02000000,0xa8a0); +reg_write( DDR_REG_BASE +0x507be*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x507bf*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x507c0*4 +0x02000000,0x7d8); +reg_write( DDR_REG_BASE +0x507c1*4 +0x02000000,0x972); +reg_write( DDR_REG_BASE +0x507c2*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x507c3*4 +0x02000000,0xa0e0); +reg_write( DDR_REG_BASE +0x507c4*4 +0x02000000,0x976); +reg_write( DDR_REG_BASE +0x507c5*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x507c6*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x507c7*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x507c8*4 +0x02000000,0xec2); +reg_write( DDR_REG_BASE +0x507c9*4 +0x02000000,0x260); +reg_write( DDR_REG_BASE +0x507ca*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x507cb*4 +0x02000000,0x236f); +reg_write( DDR_REG_BASE +0x507cc*4 +0x02000000,0x30c3); +reg_write( DDR_REG_BASE +0x507cd*4 +0x02000000,0x1318); +reg_write( DDR_REG_BASE +0x507ce*4 +0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x507cf*4 +0x02000000,0xe809); +reg_write( DDR_REG_BASE +0x507d0*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x507d1*4 +0x02000000,0xad); +reg_write( DDR_REG_BASE +0x507d2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x507d3*4 +0x02000000,0xf1a); +reg_write( DDR_REG_BASE +0x507d4*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x507d5*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x507d6*4 +0x02000000,0xf01f); +reg_write( DDR_REG_BASE +0x507d7*4 +0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x507d8*4 +0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x507d9*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x507da*4 +0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x507db*4 +0x02000000,0x8480); +reg_write( DDR_REG_BASE +0x507dc*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x507dd*4 +0x02000000,0x5f5); +reg_write( DDR_REG_BASE +0x507de*4 +0x02000000,0xe100); +reg_write( DDR_REG_BASE +0x507df*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x507e0*4 +0x02000000,0x808d); +reg_write( DDR_REG_BASE +0x507e1*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x507e2*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x507e3*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x507e4*4 +0x02000000,0x916); +reg_write( DDR_REG_BASE +0x507e5*4 +0x02000000,0x160); +reg_write( DDR_REG_BASE +0x507e6*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x507e7*4 +0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x507e8*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x507e9*4 +0x02000000,0x3b9a); +reg_write( DDR_REG_BASE +0x507ea*4 +0x02000000,0xca00); +reg_write( DDR_REG_BASE +0x507eb*4 +0x02000000,0x26ca); +reg_write( DDR_REG_BASE +0x507ec*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x507ed*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x507ee*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x507ef*4 +0x02000000,0x70c5); +reg_write( DDR_REG_BASE +0x507f0*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x507f1*4 +0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x507f2*4 +0x02000000,0x8fa); +reg_write( DDR_REG_BASE +0x507f3*4 +0x02000000,0x160); +reg_write( DDR_REG_BASE +0x507f4*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x507f5*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x507f6*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x507f7*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x507f8*4 +0x02000000,0xd); +reg_write( DDR_REG_BASE +0x507f9*4 +0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x507fa*4 +0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x507fb*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x507fc*4 +0x02000000,0x7045); +reg_write( DDR_REG_BASE +0x507fd*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x507fe*4 +0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x507ff*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50800*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50801*4 +0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x50802*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x50803*4 +0x02000000,0x8b7); +reg_write( DDR_REG_BASE +0x50804*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x50805*4 +0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x50806*4 +0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x50807*4 +0x02000000,0x8af); +reg_write( DDR_REG_BASE +0x50808*4 +0x02000000,0xdf); +reg_write( DDR_REG_BASE +0x50809*4 +0x02000000,0xdde); +reg_write( DDR_REG_BASE +0x5080a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5080b*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5080c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5080d*4 +0x02000000,0xa00); +reg_write( DDR_REG_BASE +0x5080e*4 +0x02000000,0x9e2); +reg_write( DDR_REG_BASE +0x5080f*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50810*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x50811*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50812*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50813*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50814*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x50815*4 +0x02000000,0x736c); +reg_write( DDR_REG_BASE +0x50816*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x50817*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50818*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x50819*4 +0x02000000,0xaa6); +reg_write( DDR_REG_BASE +0x5081a*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5081b*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5081c*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x5081d*4 +0x02000000,0x825); +reg_write( DDR_REG_BASE +0x5081e*4 +0x02000000,0xb4); +reg_write( DDR_REG_BASE +0x5081f*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50820*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x50821*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50822*4 +0x02000000,0xb862); +reg_write( DDR_REG_BASE +0x50823*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x50824*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x50825*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50826*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x50827*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x50828*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50829*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5082a*4 +0x02000000,0xa82); +reg_write( DDR_REG_BASE +0x5082b*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5082c*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5082d*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x5082e*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5082f*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50830*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50831*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x50832*4 +0x02000000,0xdb0c); +reg_write( DDR_REG_BASE +0x50833*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50834*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x50835*4 +0x02000000,0xa6e); +reg_write( DDR_REG_BASE +0x50836*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50837*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x50838*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x50839*4 +0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x5083a*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5083b*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5083c*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5083d*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5083e*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5083f*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x50840*4 +0x02000000,0xa56); +reg_write( DDR_REG_BASE +0x50841*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50842*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x50843*4 +0x02000000,0xc9e); +reg_write( DDR_REG_BASE +0x50844*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50845*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50846*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x50847*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50848*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x50849*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5084a*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5084b*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5084c*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5084d*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5084e*4 +0x02000000,0xa3a); +reg_write( DDR_REG_BASE +0x5084f*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50850*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x50851*4 +0x02000000,0xc66); +reg_write( DDR_REG_BASE +0x50852*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50853*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50854*4 +0x02000000,0x922); +reg_write( DDR_REG_BASE +0x50855*4 +0x02000000,0x280); +reg_write( DDR_REG_BASE +0x50856*4 +0x02000000,0xd896); +reg_write( DDR_REG_BASE +0x50857*4 +0x02000000,0x9ea); +reg_write( DDR_REG_BASE +0x50858*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50859*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5085a*4 +0x02000000,0xf3e); +reg_write( DDR_REG_BASE +0x5085b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5085c*4 +0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x5085d*4 +0x02000000,0xcfa); +reg_write( DDR_REG_BASE +0x5085e*4 +0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x5085f*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50860*4 +0x02000000,0xf); +reg_write( DDR_REG_BASE +0x50861*4 +0x02000000,0x4240); +reg_write( DDR_REG_BASE +0x50862*4 +0x02000000,0x81a); +reg_write( DDR_REG_BASE +0x50863*4 +0x02000000,0x160); +reg_write( DDR_REG_BASE +0x50864*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50865*4 +0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x50866*4 +0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x50867*4 +0x02000000,0x83f); +reg_write( DDR_REG_BASE +0x50868*4 +0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x50869*4 +0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x5086a*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5086b*4 +0x02000000,0x14); +reg_write( DDR_REG_BASE +0x5086c*4 +0x02000000,0x9320); +reg_write( DDR_REG_BASE +0x5086d*4 +0x02000000,0xca01); +reg_write( DDR_REG_BASE +0x5086e*4 +0x02000000,0x80d); +reg_write( DDR_REG_BASE +0x5086f*4 +0x02000000,0x1b0); +reg_write( DDR_REG_BASE +0x50870*4 +0x02000000,0x214f); +reg_write( DDR_REG_BASE +0x50871*4 +0x02000000,0x82); +reg_write( DDR_REG_BASE +0x50872*4 +0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x50873*4 +0x02000000,0xd1); +reg_write( DDR_REG_BASE +0x50874*4 +0x02000000,0x2185); +reg_write( DDR_REG_BASE +0x50875*4 +0x02000000,0x108); +reg_write( DDR_REG_BASE +0x50876*4 +0x02000000,0x4220); +reg_write( DDR_REG_BASE +0x50877*4 +0x02000000,0xb340); +reg_write( DDR_REG_BASE +0x50878*4 +0x02000000,0xd823); +reg_write( DDR_REG_BASE +0x50879*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x5087a*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x5087b*4 +0x02000000,0xe034); +reg_write( DDR_REG_BASE +0x5087c*4 +0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x5087d*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5087e*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5087f*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x50880*4 +0x02000000,0xe034); +reg_write( DDR_REG_BASE +0x50881*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x50882*4 +0x02000000,0xb8b1); +reg_write( DDR_REG_BASE +0x50883*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x50884*4 +0x02000000,0xb221); +reg_write( DDR_REG_BASE +0x50885*4 +0x02000000,0xddff); +reg_write( DDR_REG_BASE +0x50886*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x50887*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50888*4 +0x02000000,0x228a); +reg_write( DDR_REG_BASE +0x50889*4 +0x02000000,0xdff); +reg_write( DDR_REG_BASE +0x5088a*4 +0x02000000,0x776c); +reg_write( DDR_REG_BASE +0x5088b*4 +0x02000000,0xb06); +reg_write( DDR_REG_BASE +0x5088c*4 +0x02000000,0x320); +reg_write( DDR_REG_BASE +0x5088d*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5088e*4 +0x02000000,0x774c); +reg_write( DDR_REG_BASE +0x5088f*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x50890*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x50891*4 +0x02000000,0x4340); +reg_write( DDR_REG_BASE +0x50892*4 +0x02000000,0xaf6); +reg_write( DDR_REG_BASE +0x50893*4 +0x02000000,0x320); +reg_write( DDR_REG_BASE +0x50894*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x50895*4 +0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x50896*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50897*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50898*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50899*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5089a*4 +0x02000000,0xca04); +reg_write( DDR_REG_BASE +0x5089b*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5089c*4 +0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x5089d*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5089e*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x5089f*4 +0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x508a0*4 +0x02000000,0x8b20); +reg_write( DDR_REG_BASE +0x508a1*4 +0x02000000,0xa0d); +reg_write( DDR_REG_BASE +0x508a2*4 +0x02000000,0x44); +reg_write( DDR_REG_BASE +0x508a3*4 +0x02000000,0x8b21); +reg_write( DDR_REG_BASE +0x508a4*4 +0x02000000,0x919); +reg_write( DDR_REG_BASE +0x508a5*4 +0x02000000,0x85); +reg_write( DDR_REG_BASE +0x508a6*4 +0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x508a7*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x508a8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x508a9*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x508aa*4 +0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x508ab*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x508ac*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x508ad*4 +0x02000000,0x1f64); +reg_write( DDR_REG_BASE +0x508ae*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x508af*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x508b0*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x508b1*4 +0x02000000,0xae1); +reg_write( DDR_REG_BASE +0x508b2*4 +0x02000000,0x8004); +reg_write( DDR_REG_BASE +0x508b3*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x508b4*4 +0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x508b5*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x508b6*4 +0x02000000,0xbd9a); +reg_write( DDR_REG_BASE +0x508b7*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x508b8*4 +0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x508b9*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x508ba*4 +0x02000000,0xd4a); +reg_write( DDR_REG_BASE +0x508bb*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x508bc*4 +0x02000000,0x1a09); +reg_write( DDR_REG_BASE +0x508bd*4 +0x02000000,0x3003); +reg_write( DDR_REG_BASE +0x508be*4 +0x02000000,0xca6); +reg_write( DDR_REG_BASE +0x508bf*4 +0x02000000,0x240); +reg_write( DDR_REG_BASE +0x508c0*4 +0x02000000,0x254f); +reg_write( DDR_REG_BASE +0x508c1*4 +0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x508c2*4 +0x02000000,0xd3a); +reg_write( DDR_REG_BASE +0x508c3*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x508c4*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x508c5*4 +0x02000000,0xfd2); +reg_write( DDR_REG_BASE +0x508c6*4 +0x02000000,0x2a0); +reg_write( DDR_REG_BASE +0x508c7*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x508c8*4 +0x02000000,0x26ab); +reg_write( DDR_REG_BASE +0x508c9*4 +0x02000000,0x10c4); +reg_write( DDR_REG_BASE +0x508ca*4 +0x02000000,0x7fff); +reg_write( DDR_REG_BASE +0x508cb*4 +0x02000000,0xf000); +reg_write( DDR_REG_BASE +0x508cc*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x508cd*4 +0x02000000,0xc1a5); +reg_write( DDR_REG_BASE +0x508ce*4 +0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x508cf*4 +0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x508d0*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x508d1*4 +0x02000000,0xa3a); +reg_write( DDR_REG_BASE +0x508d2*4 +0x02000000,0x160); +reg_write( DDR_REG_BASE +0x508d3*4 +0x02000000,0xda14); +reg_write( DDR_REG_BASE +0x508d4*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x508d5*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x508d6*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x508d7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x508d8*4 +0x02000000,0xc180); +reg_write( DDR_REG_BASE +0x508d9*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x508da*4 +0x02000000,0xe3a); +reg_write( DDR_REG_BASE +0x508db*4 +0x02000000,0x220); +reg_write( DDR_REG_BASE +0x508dc*4 +0x02000000,0xb885); +reg_write( DDR_REG_BASE +0x508dd*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x508de*4 +0x02000000,0xf6); +reg_write( DDR_REG_BASE +0x508df*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x508e0*4 +0x02000000,0xcfe); +reg_write( DDR_REG_BASE +0x508e1*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x508e2*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x508e3*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x508e4*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x508e5*4 +0x02000000,0xf32); +reg_write( DDR_REG_BASE +0x508e6*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x508e7*4 +0x02000000,0xc280); +reg_write( DDR_REG_BASE +0x508e8*4 +0x02000000,0xc0a5); +reg_write( DDR_REG_BASE +0x508e9*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x508ea*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x508eb*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x508ec*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x508ed*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x508ee*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x508ef*4 +0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x508f0*4 +0x02000000,0x3d02); +reg_write( DDR_REG_BASE +0x508f1*4 +0x02000000,0x4748); +reg_write( DDR_REG_BASE +0x508f2*4 +0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x508f3*4 +0x02000000,0x4308); +reg_write( DDR_REG_BASE +0x508f4*4 +0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x508f5*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x508f6*4 +0x02000000,0x9ee); +reg_write( DDR_REG_BASE +0x508f7*4 +0x02000000,0x160); +reg_write( DDR_REG_BASE +0x508f8*4 +0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x508f9*4 +0x02000000,0xb25); +reg_write( DDR_REG_BASE +0x508fa*4 +0x02000000,0x10b1); +reg_write( DDR_REG_BASE +0x508fb*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x508fc*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x508fd*4 +0x02000000,0xf2); +reg_write( DDR_REG_BASE +0x508fe*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x508ff*4 +0x02000000,0xcc2); +reg_write( DDR_REG_BASE +0x50900*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50901*4 +0x02000000,0x4260); +reg_write( DDR_REG_BASE +0x50902*4 +0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x50903*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50904*4 +0x02000000,0xf3a); +reg_write( DDR_REG_BASE +0x50905*4 +0x02000000,0x220); +reg_write( DDR_REG_BASE +0x50906*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x50907*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50908*4 +0x02000000,0xd909); +reg_write( DDR_REG_BASE +0x50909*4 +0x02000000,0xf036); +reg_write( DDR_REG_BASE +0x5090a*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x5090b*4 +0x02000000,0x3f9b); +reg_write( DDR_REG_BASE +0x5090c*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5090d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5090e*4 +0x02000000,0xb1b); +reg_write( DDR_REG_BASE +0x5090f*4 +0x02000000,0x1030); +reg_write( DDR_REG_BASE +0x50910*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x50911*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50912*4 +0x02000000,0xf4); +reg_write( DDR_REG_BASE +0x50913*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50914*4 +0x02000000,0xc96); +reg_write( DDR_REG_BASE +0x50915*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50916*4 +0x02000000,0x4260); +reg_write( DDR_REG_BASE +0x50917*4 +0x02000000,0xdd09); +reg_write( DDR_REG_BASE +0x50918*4 +0x02000000,0xdec0); +reg_write( DDR_REG_BASE +0x50919*4 +0x02000000,0xd8d0); +reg_write( DDR_REG_BASE +0x5091a*4 +0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x5091b*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5091c*4 +0x02000000,0xf3); +reg_write( DDR_REG_BASE +0x5091d*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5091e*4 +0x02000000,0xc82); +reg_write( DDR_REG_BASE +0x5091f*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50920*4 +0x02000000,0x4260); +reg_write( DDR_REG_BASE +0x50921*4 +0x02000000,0x72ad); +reg_write( DDR_REG_BASE +0x50922*4 +0x02000000,0xde8c); +reg_write( DDR_REG_BASE +0x50923*4 +0x02000000,0xd880); +reg_write( DDR_REG_BASE +0x50924*4 +0x02000000,0x60f8); +reg_write( DDR_REG_BASE +0x50925*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x50926*4 +0x02000000,0x6c0); +reg_write( DDR_REG_BASE +0x50927*4 +0x02000000,0xc180); +reg_write( DDR_REG_BASE +0x50928*4 +0x02000000,0xd9e); +reg_write( DDR_REG_BASE +0x50929*4 +0x02000000,0x220); +reg_write( DDR_REG_BASE +0x5092a*4 +0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x5092b*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5092c*4 +0x02000000,0x722c); +reg_write( DDR_REG_BASE +0x5092d*4 +0x02000000,0xea2); +reg_write( DDR_REG_BASE +0x5092e*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x5092f*4 +0x02000000,0xc280); +reg_write( DDR_REG_BASE +0x50930*4 +0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x50931*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50932*4 +0x02000000,0x976); +reg_write( DDR_REG_BASE +0x50933*4 +0x02000000,0x160); +reg_write( DDR_REG_BASE +0x50934*4 +0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x50935*4 +0x02000000,0x66fe); +reg_write( DDR_REG_BASE +0x50936*4 +0x02000000,0x2605); +reg_write( DDR_REG_BASE +0x50937*4 +0x02000000,0x16c0); +reg_write( DDR_REG_BASE +0x50938*4 +0x02000000,0xc180); +reg_write( DDR_REG_BASE +0x50939*4 +0x02000000,0xd7e); +reg_write( DDR_REG_BASE +0x5093a*4 +0x02000000,0x220); +reg_write( DDR_REG_BASE +0x5093b*4 +0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x5093c*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5093d*4 +0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x5093e*4 +0x02000000,0xe7e); +reg_write( DDR_REG_BASE +0x5093f*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50940*4 +0x02000000,0xc280); +reg_write( DDR_REG_BASE +0x50941*4 +0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x50942*4 +0x02000000,0x3d02); +reg_write( DDR_REG_BASE +0x50943*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50944*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50945*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50946*4 +0x02000000,0xc3e2); +reg_write( DDR_REG_BASE +0x50947*4 +0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x50948*4 +0x02000000,0x3d02); +reg_write( DDR_REG_BASE +0x50949*4 +0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x5094a*4 +0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x5094b*4 +0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x5094c*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5094d*4 +0x02000000,0x942); +reg_write( DDR_REG_BASE +0x5094e*4 +0x02000000,0x160); +reg_write( DDR_REG_BASE +0x5094f*4 +0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x50950*4 +0x02000000,0x2354); +reg_write( DDR_REG_BASE +0x50951*4 +0x02000000,0xd00); +reg_write( DDR_REG_BASE +0x50952*4 +0x02000000,0xc180); +reg_write( DDR_REG_BASE +0x50953*4 +0x02000000,0xd4a); +reg_write( DDR_REG_BASE +0x50954*4 +0x02000000,0x220); +reg_write( DDR_REG_BASE +0x50955*4 +0x02000000,0xda09); +reg_write( DDR_REG_BASE +0x50956*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x50957*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50958*4 +0x02000000,0xf5); +reg_write( DDR_REG_BASE +0x50959*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5095a*4 +0x02000000,0xc0a); +reg_write( DDR_REG_BASE +0x5095b*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5095c*4 +0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x5095d*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5095e*4 +0x02000000,0xd909); +reg_write( DDR_REG_BASE +0x5095f*4 +0x02000000,0xe3e); +reg_write( DDR_REG_BASE +0x50960*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50961*4 +0x02000000,0xc280); +reg_write( DDR_REG_BASE +0x50962*4 +0x02000000,0xc7c2); +reg_write( DDR_REG_BASE +0x50963*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50964*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x50965*4 +0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x50966*4 +0x02000000,0x3d02); +reg_write( DDR_REG_BASE +0x50967*4 +0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x50968*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50969*4 +0x02000000,0x90a); +reg_write( DDR_REG_BASE +0x5096a*4 +0x02000000,0x160); +reg_write( DDR_REG_BASE +0x5096b*4 +0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x5096c*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5096d*4 +0x02000000,0xf7); +reg_write( DDR_REG_BASE +0x5096e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5096f*4 +0x02000000,0xbe2); +reg_write( DDR_REG_BASE +0x50970*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50971*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x50972*4 +0x02000000,0xd840); +reg_write( DDR_REG_BASE +0x50973*4 +0x02000000,0xc180); +reg_write( DDR_REG_BASE +0x50974*4 +0x02000000,0xd06); +reg_write( DDR_REG_BASE +0x50975*4 +0x02000000,0x220); +reg_write( DDR_REG_BASE +0x50976*4 +0x02000000,0xda09); +reg_write( DDR_REG_BASE +0x50977*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50978*4 +0x02000000,0xd909); +reg_write( DDR_REG_BASE +0x50979*4 +0x02000000,0xe0a); +reg_write( DDR_REG_BASE +0x5097a*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x5097b*4 +0x02000000,0xc280); +reg_write( DDR_REG_BASE +0x5097c*4 +0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x5097d*4 +0x02000000,0x3d02); +reg_write( DDR_REG_BASE +0x5097e*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x5097f*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50980*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50981*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x50982*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50983*4 +0x02000000,0x12); +reg_write( DDR_REG_BASE +0x50984*4 +0x02000000,0x7534); +reg_write( DDR_REG_BASE +0x50985*4 +0x02000000,0x20e0); +reg_write( DDR_REG_BASE +0x50986*4 +0x02000000,0x7c5); +reg_write( DDR_REG_BASE +0x50987*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50988*4 +0x02000000,0x1a09); +reg_write( DDR_REG_BASE +0x50989*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x5098a*4 +0x02000000,0xc0e6); +reg_write( DDR_REG_BASE +0x5098b*4 +0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x5098c*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5098d*4 +0x02000000,0xe4); +reg_write( DDR_REG_BASE +0x5098e*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x5098f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50990*4 +0x02000000,0x7cb); +reg_write( DDR_REG_BASE +0x50991*4 +0x02000000,0x835); +reg_write( DDR_REG_BASE +0x50992*4 +0x02000000,0xb0); +reg_write( DDR_REG_BASE +0x50993*4 +0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x50994*4 +0x02000000,0x7114); +reg_write( DDR_REG_BASE +0x50995*4 +0x02000000,0xd825); +reg_write( DDR_REG_BASE +0x50996*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50997*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50998*4 +0x02000000,0x30); +reg_write( DDR_REG_BASE +0x50999*4 +0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x5099a*4 +0x02000000,0xf42a); +reg_write( DDR_REG_BASE +0x5099b*4 +0x02000000,0x8a25); +reg_write( DDR_REG_BASE +0x5099c*4 +0x02000000,0xaa23); +reg_write( DDR_REG_BASE +0x5099d*4 +0x02000000,0x8aa4); +reg_write( DDR_REG_BASE +0x5099e*4 +0x02000000,0x7b34); +reg_write( DDR_REG_BASE +0x5099f*4 +0x02000000,0xaaa2); +reg_write( DDR_REG_BASE +0x509a0*4 +0x02000000,0x96c0); +reg_write( DDR_REG_BASE +0x509a1*4 +0x02000000,0x88e0); +reg_write( DDR_REG_BASE +0x509a2*4 +0x02000000,0x78bb); +reg_write( DDR_REG_BASE +0x509a3*4 +0x02000000,0xb4e0); +reg_write( DDR_REG_BASE +0x509a4*4 +0x02000000,0xaa00); +reg_write( DDR_REG_BASE +0x509a5*4 +0x02000000,0xe5f); +reg_write( DDR_REG_BASE +0x509a6*4 +0x02000000,0x1171); +reg_write( DDR_REG_BASE +0x509a7*4 +0x02000000,0xaa61); +reg_write( DDR_REG_BASE +0x509a8*4 +0x02000000,0xb4e1); +reg_write( DDR_REG_BASE +0x509a9*4 +0x02000000,0xf02d); +reg_write( DDR_REG_BASE +0x509aa*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x509ab*4 +0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x509ac*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x509ad*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x509ae*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x509af*4 +0x02000000,0x58); +reg_write( DDR_REG_BASE +0x509b0*4 +0x02000000,0xb421); +reg_write( DDR_REG_BASE +0x509b1*4 +0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x509b2*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x509b3*4 +0x02000000,0xf6); +reg_write( DDR_REG_BASE +0x509b4*4 +0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x509b5*4 +0x02000000,0xb404); +reg_write( DDR_REG_BASE +0x509b6*4 +0x02000000,0x1c06); +reg_write( DDR_REG_BASE +0x509b7*4 +0x02000000,0x13c5); +reg_write( DDR_REG_BASE +0x509b8*4 +0x02000000,0x8a27); +reg_write( DDR_REG_BASE +0x509b9*4 +0x02000000,0xaa23); +reg_write( DDR_REG_BASE +0x509ba*4 +0x02000000,0x8a06); +reg_write( DDR_REG_BASE +0x509bb*4 +0x02000000,0x7b34); +reg_write( DDR_REG_BASE +0x509bc*4 +0x02000000,0xaa02); +reg_write( DDR_REG_BASE +0x509bd*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x509be*4 +0x02000000,0xaa00); +reg_write( DDR_REG_BASE +0x509bf*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x509c0*4 +0x02000000,0xaa61); +reg_write( DDR_REG_BASE +0x509c1*4 +0x02000000,0x1cfe); +reg_write( DDR_REG_BASE +0x509c2*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x509c3*4 +0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x509c4*4 +0x02000000,0x88a0); +reg_write( DDR_REG_BASE +0x509c5*4 +0x02000000,0xb4a0); +reg_write( DDR_REG_BASE +0x509c6*4 +0x02000000,0x8a27); +reg_write( DDR_REG_BASE +0x509c7*4 +0x02000000,0xaa23); +reg_write( DDR_REG_BASE +0x509c8*4 +0x02000000,0x8a04); +reg_write( DDR_REG_BASE +0x509c9*4 +0x02000000,0x7b34); +reg_write( DDR_REG_BASE +0x509ca*4 +0x02000000,0xaa02); +reg_write( DDR_REG_BASE +0x509cb*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x509cc*4 +0x02000000,0xaa00); +reg_write( DDR_REG_BASE +0x509cd*4 +0x02000000,0xaa61); +reg_write( DDR_REG_BASE +0x509ce*4 +0x02000000,0x9600); +reg_write( DDR_REG_BASE +0x509cf*4 +0x02000000,0x829); +reg_write( DDR_REG_BASE +0x509d0*4 +0x02000000,0x151); +reg_write( DDR_REG_BASE +0x509d1*4 +0x02000000,0xb4a1); +reg_write( DDR_REG_BASE +0x509d2*4 +0x02000000,0xf015); +reg_write( DDR_REG_BASE +0x509d3*4 +0x02000000,0x1c02); +reg_write( DDR_REG_BASE +0x509d4*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x509d5*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x509d6*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x509d7*4 +0x02000000,0xfe); +reg_write( DDR_REG_BASE +0x509d8*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x509d9*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x509da*4 +0x02000000,0x3c5); +reg_write( DDR_REG_BASE +0x509db*4 +0x02000000,0x19f8); +reg_write( DDR_REG_BASE +0x509dc*4 +0x02000000,0x8004); +reg_write( DDR_REG_BASE +0x509dd*4 +0x02000000,0x19f6); +reg_write( DDR_REG_BASE +0x509de*4 +0x02000000,0x8005); +reg_write( DDR_REG_BASE +0x509df*4 +0x02000000,0x19fe); +reg_write( DDR_REG_BASE +0x509e0*4 +0x02000000,0x8005); +reg_write( DDR_REG_BASE +0x509e1*4 +0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x509e2*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x509e3*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x509e4*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x509e5*4 +0x02000000,0x58); +reg_write( DDR_REG_BASE +0x509e6*4 +0x02000000,0xb401); +reg_write( DDR_REG_BASE +0x509e7*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x509e8*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x509e9*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x509ea*4 +0x02000000,0xf6); +reg_write( DDR_REG_BASE +0x509eb*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x509ec*4 +0x02000000,0xb024); +reg_write( DDR_REG_BASE +0x509ed*4 +0x02000000,0x18fe); +reg_write( DDR_REG_BASE +0x509ee*4 +0x02000000,0x8044); +reg_write( DDR_REG_BASE +0x509ef*4 +0x02000000,0xb023); +reg_write( DDR_REG_BASE +0x509f0*4 +0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x509f1*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x509f2*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x509f3*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x509f4*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x509f5*4 +0x02000000,0xc1a5); +reg_write( DDR_REG_BASE +0x509f6*4 +0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x509f7*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x509f8*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x509f9*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x509fa*4 +0x02000000,0x88c0); +reg_write( DDR_REG_BASE +0x509fb*4 +0x02000000,0x2753); +reg_write( DDR_REG_BASE +0x509fc*4 +0x02000000,0x1040); +reg_write( DDR_REG_BASE +0x509fd*4 +0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x509fe*4 +0x02000000,0x80); +reg_write( DDR_REG_BASE +0x509ff*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x50a00*4 +0x02000000,0xc144); +reg_write( DDR_REG_BASE +0x50a01*4 +0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x50a02*4 +0x02000000,0xcde); +reg_write( DDR_REG_BASE +0x50a03*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50a04*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x50a05*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x50a06*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50a07*4 +0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x50a08*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x50a09*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50a0a*4 +0x02000000,0x9d6); +reg_write( DDR_REG_BASE +0x50a0b*4 +0x02000000,0x260); +reg_write( DDR_REG_BASE +0x50a0c*4 +0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50a0d*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50a0e*4 +0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50a0f*4 +0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x50a10*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50a11*4 +0x02000000,0xda40); +reg_write( DDR_REG_BASE +0x50a12*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50a13*4 +0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50a14*4 +0x02000000,0x95e); +reg_write( DDR_REG_BASE +0x50a15*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50a16*4 +0x02000000,0xda7f); +reg_write( DDR_REG_BASE +0x50a17*4 +0x02000000,0x275f); +reg_write( DDR_REG_BASE +0x50a18*4 +0x02000000,0x1100); +reg_write( DDR_REG_BASE +0x50a19*4 +0x02000000,0x43db); +reg_write( DDR_REG_BASE +0x50a1a*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50a1b*4 +0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x50a1c*4 +0x02000000,0x7f05); +reg_write( DDR_REG_BASE +0x50a1d*4 +0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x50a1e*4 +0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x50a1f*4 +0x02000000,0xe814); +reg_write( DDR_REG_BASE +0x50a20*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50a21*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50a22*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50a23*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50a24*4 +0x02000000,0x81d); +reg_write( DDR_REG_BASE +0x50a25*4 +0x02000000,0xdf); +reg_write( DDR_REG_BASE +0x50a26*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50a27*4 +0x02000000,0xf863); +reg_write( DDR_REG_BASE +0x50a28*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x50a29*4 +0x02000000,0x3001); +reg_write( DDR_REG_BASE +0x50a2a*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x50a2b*4 +0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x50a2c*4 +0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x50a2d*4 +0x02000000,0x61b9); +reg_write( DDR_REG_BASE +0x50a2e*4 +0x02000000,0xd2a); +reg_write( DDR_REG_BASE +0x50a2f*4 +0x02000000,0x2e0); +reg_write( DDR_REG_BASE +0x50a30*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50a31*4 +0x02000000,0xf00b); +reg_write( DDR_REG_BASE +0x50a32*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50a33*4 +0x02000000,0xf85d); +reg_write( DDR_REG_BASE +0x50a34*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x50a35*4 +0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x50a36*4 +0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x50a37*4 +0x02000000,0x61b9); +reg_write( DDR_REG_BASE +0x50a38*4 +0x02000000,0xbce); +reg_write( DDR_REG_BASE +0x50a39*4 +0x02000000,0x2e0); +reg_write( DDR_REG_BASE +0x50a3a*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50a3b*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50a3c*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x50a3d*4 +0x02000000,0xe04c); +reg_write( DDR_REG_BASE +0x50a3e*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x50a3f*4 +0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x50a40*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x50a41*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x50a42*4 +0x02000000,0x18fc); +reg_write( DDR_REG_BASE +0x50a43*4 +0x02000000,0x8044); +reg_write( DDR_REG_BASE +0x50a44*4 +0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x50a45*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x50a46*4 +0x02000000,0xe8aa); +reg_write( DDR_REG_BASE +0x50a47*4 +0x02000000,0xf022); +reg_write( DDR_REG_BASE +0x50a48*4 +0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x50a49*4 +0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x50a4a*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50a4b*4 +0x02000000,0x2116); +reg_write( DDR_REG_BASE +0x50a4c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50a4d*4 +0x02000000,0x7061); +reg_write( DDR_REG_BASE +0x50a4e*4 +0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x50a4f*4 +0x02000000,0xf9e); +reg_write( DDR_REG_BASE +0x50a50*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50a51*4 +0x02000000,0x7a8); +reg_write( DDR_REG_BASE +0x50a52*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x50a53*4 +0x02000000,0xe06); +reg_write( DDR_REG_BASE +0x50a54*4 +0x02000000,0x260); +reg_write( DDR_REG_BASE +0x50a55*4 +0x02000000,0x210a); +reg_write( DDR_REG_BASE +0x50a56*4 +0x02000000,0x780); +reg_write( DDR_REG_BASE +0x50a57*4 +0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x50a58*4 +0x02000000,0x3f82); +reg_write( DDR_REG_BASE +0x50a59*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50a5a*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x50a5b*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50a5c*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50a5d*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50a5e*4 +0x02000000,0xb88a); +reg_write( DDR_REG_BASE +0x50a5f*4 +0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x50a60*4 +0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x50a61*4 +0x02000000,0x43); +reg_write( DDR_REG_BASE +0x50a62*4 +0x02000000,0xb964); +reg_write( DDR_REG_BASE +0x50a63*4 +0x02000000,0x7945); +reg_write( DDR_REG_BASE +0x50a64*4 +0x02000000,0xb300); +reg_write( DDR_REG_BASE +0x50a65*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50a66*4 +0x02000000,0xfc5); +reg_write( DDR_REG_BASE +0x50a67*4 +0x02000000,0xb300); +reg_write( DDR_REG_BASE +0x50a68*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50a69*4 +0x02000000,0x78d4); +reg_write( DDR_REG_BASE +0x50a6a*4 +0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x50a6b*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50a6c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50a6d*4 +0x02000000,0x784); +reg_write( DDR_REG_BASE +0x50a6e*4 +0x02000000,0xbb5); +reg_write( DDR_REG_BASE +0x50a6f*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50a70*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50a71*4 +0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50a72*4 +0x02000000,0x8a2); +reg_write( DDR_REG_BASE +0x50a73*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50a74*4 +0x02000000,0xda7f); +reg_write( DDR_REG_BASE +0x50a75*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50a76*4 +0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50a77*4 +0x02000000,0xebe); +reg_write( DDR_REG_BASE +0x50a78*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50a79*4 +0x02000000,0xda49); +reg_write( DDR_REG_BASE +0x50a7a*4 +0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x50a7b*4 +0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x50a7c*4 +0x02000000,0xe813); +reg_write( DDR_REG_BASE +0x50a7d*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50a7e*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50a7f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50a80*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50a81*4 +0x02000000,0x81f); +reg_write( DDR_REG_BASE +0x50a82*4 +0x02000000,0xdf); +reg_write( DDR_REG_BASE +0x50a83*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50a84*4 +0x02000000,0xf82f); +reg_write( DDR_REG_BASE +0x50a85*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x50a86*4 +0x02000000,0x3001); +reg_write( DDR_REG_BASE +0x50a87*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x50a88*4 +0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x50a89*4 +0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x50a8a*4 +0x02000000,0x61b9); +reg_write( DDR_REG_BASE +0x50a8b*4 +0x02000000,0xc72); +reg_write( DDR_REG_BASE +0x50a8c*4 +0x02000000,0x2e0); +reg_write( DDR_REG_BASE +0x50a8d*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50a8e*4 +0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x50a8f*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50a90*4 +0x02000000,0xf829); +reg_write( DDR_REG_BASE +0x50a91*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x50a92*4 +0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x50a93*4 +0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x50a94*4 +0x02000000,0x61b9); +reg_write( DDR_REG_BASE +0x50a95*4 +0x02000000,0xb16); +reg_write( DDR_REG_BASE +0x50a96*4 +0x02000000,0x2e0); +reg_write( DDR_REG_BASE +0x50a97*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50a98*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50a99*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50a9a*4 +0x02000000,0x2710); +reg_write( DDR_REG_BASE +0x50a9b*4 +0x02000000,0xbaa); +reg_write( DDR_REG_BASE +0x50a9c*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50a9d*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50a9e*4 +0x02000000,0x952); +reg_write( DDR_REG_BASE +0x50a9f*4 +0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x50aa0*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50aa1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50aa2*4 +0x02000000,0x1d4c); +reg_write( DDR_REG_BASE +0x50aa3*4 +0x02000000,0xb9a); +reg_write( DDR_REG_BASE +0x50aa4*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50aa5*4 +0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x50aa6*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50aa7*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x50aa8*4 +0x02000000,0xf7a0); +reg_write( DDR_REG_BASE +0x50aa9*4 +0x02000000,0xb8e); +reg_write( DDR_REG_BASE +0x50aaa*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50aab*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50aac*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50aad*4 +0x02000000,0xc92); +reg_write( DDR_REG_BASE +0x50aae*4 +0x02000000,0x220); +reg_write( DDR_REG_BASE +0x50aaf*4 +0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50ab0*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x50ab1*4 +0x02000000,0xe8ad); +reg_write( DDR_REG_BASE +0x50ab2*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50ab3*4 +0x02000000,0xf023); +reg_write( DDR_REG_BASE +0x50ab4*4 +0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x50ab5*4 +0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x50ab6*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50ab7*4 +0x02000000,0x7916); +reg_write( DDR_REG_BASE +0x50ab8*4 +0x02000000,0x61b8); +reg_write( DDR_REG_BASE +0x50ab9*4 +0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x50aba*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x50abb*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50abc*4 +0x02000000,0x7a8); +reg_write( DDR_REG_BASE +0x50abd*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x50abe*4 +0x02000000,0xd2e); +reg_write( DDR_REG_BASE +0x50abf*4 +0x02000000,0x260); +reg_write( DDR_REG_BASE +0x50ac0*4 +0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x50ac1*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50ac2*4 +0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x50ac3*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x50ac4*4 +0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x50ac5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50ac6*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x50ac7*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x50ac8*4 +0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x50ac9*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x50aca*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50acb*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50acc*4 +0x02000000,0xb260); +reg_write( DDR_REG_BASE +0x50acd*4 +0x02000000,0x204f); +reg_write( DDR_REG_BASE +0x50ace*4 +0x02000000,0x283); +reg_write( DDR_REG_BASE +0x50acf*4 +0x02000000,0xb260); +reg_write( DDR_REG_BASE +0x50ad0*4 +0x02000000,0x9e7); +reg_write( DDR_REG_BASE +0x50ad1*4 +0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x50ad2*4 +0x02000000,0x204f); +reg_write( DDR_REG_BASE +0x50ad3*4 +0x02000000,0x243); +reg_write( DDR_REG_BASE +0x50ad4*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x50ad5*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50ad6*4 +0x02000000,0x78d4); +reg_write( DDR_REG_BASE +0x50ad7*4 +0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x50ad8*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50ad9*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50ada*4 +0x02000000,0x784); +reg_write( DDR_REG_BASE +0x50adb*4 +0x02000000,0xdb5); +reg_write( DDR_REG_BASE +0x50adc*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50add*4 +0x02000000,0xc0a5); +reg_write( DDR_REG_BASE +0x50ade*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50adf*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50ae0*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50ae1*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50ae2*4 +0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x50ae3*4 +0x02000000,0x1c82); +reg_write( DDR_REG_BASE +0x50ae4*4 +0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x50ae5*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x50ae6*4 +0x02000000,0xdfff); +reg_write( DDR_REG_BASE +0x50ae7*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x50ae8*4 +0x02000000,0x641); +reg_write( DDR_REG_BASE +0x50ae9*4 +0x02000000,0x78ef); +reg_write( DDR_REG_BASE +0x50aea*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50aeb*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50aec*4 +0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x50aed*4 +0x02000000,0x1c82); +reg_write( DDR_REG_BASE +0x50aee*4 +0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x50aef*4 +0x02000000,0xffbf); +reg_write( DDR_REG_BASE +0x50af0*4 +0x02000000,0x87f7); +reg_write( DDR_REG_BASE +0x50af1*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x50af2*4 +0x02000000,0x641); +reg_write( DDR_REG_BASE +0x50af3*4 +0x02000000,0x78ef); +reg_write( DDR_REG_BASE +0x50af4*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50af5*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50af6*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50af7*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50af8*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50af9*4 +0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x50afa*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50afb*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50afc*4 +0x02000000,0xf4); +reg_write( DDR_REG_BASE +0x50afd*4 +0x02000000,0x9600); +reg_write( DDR_REG_BASE +0x50afe*4 +0x02000000,0x6ea2); +reg_write( DDR_REG_BASE +0x50aff*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50b00*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50b01*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50b02*4 +0x02000000,0x1500); +reg_write( DDR_REG_BASE +0x50b03*4 +0x02000000,0x111b); +reg_write( DDR_REG_BASE +0x50b04*4 +0x02000000,0x95e3); +reg_write( DDR_REG_BASE +0x50b05*4 +0x02000000,0x1508); +reg_write( DDR_REG_BASE +0x50b06*4 +0x02000000,0x110b); +reg_write( DDR_REG_BASE +0x50b07*4 +0x02000000,0x1d08); +reg_write( DDR_REG_BASE +0x50b08*4 +0x02000000,0x13c5); +reg_write( DDR_REG_BASE +0x50b09*4 +0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x50b0a*4 +0x02000000,0x1d06); +reg_write( DDR_REG_BASE +0x50b0b*4 +0x02000000,0x13c5); +reg_write( DDR_REG_BASE +0x50b0c*4 +0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x50b0d*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50b0e*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50b0f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50b10*4 +0x02000000,0x7c8); +reg_write( DDR_REG_BASE +0x50b11*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50b12*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x50b13*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x50b14*4 +0x02000000,0x190); +reg_write( DDR_REG_BASE +0x50b15*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50b16*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50b17*4 +0x02000000,0x2af8); +reg_write( DDR_REG_BASE +0x50b18*4 +0x02000000,0xaae); +reg_write( DDR_REG_BASE +0x50b19*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50b1a*4 +0x02000000,0x1efa); +reg_write( DDR_REG_BASE +0x50b1b*4 +0x02000000,0x9485); +reg_write( DDR_REG_BASE +0x50b1c*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50b1d*4 +0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x50b1e*4 +0x02000000,0xb5e3); +reg_write( DDR_REG_BASE +0x50b1f*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50b20*4 +0x02000000,0x16c4); +reg_write( DDR_REG_BASE +0x50b21*4 +0x02000000,0x1d08); +reg_write( DDR_REG_BASE +0x50b22*4 +0x02000000,0x12c4); +reg_write( DDR_REG_BASE +0x50b23*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50b24*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50b25*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50b26*4 +0x02000000,0x7c8); +reg_write( DDR_REG_BASE +0x50b27*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50b28*4 +0x02000000,0xb8a0); +reg_write( DDR_REG_BASE +0x50b29*4 +0x02000000,0x6829); +reg_write( DDR_REG_BASE +0x50b2a*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50b2b*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50b2c*4 +0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x50b2d*4 +0x02000000,0xa821); +reg_write( DDR_REG_BASE +0x50b2e*4 +0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x50b2f*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50b30*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50b31*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50b32*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50b33*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50b34*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50b35*4 +0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x50b36*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50b37*4 +0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x50b38*4 +0x02000000,0x9720); +reg_write( DDR_REG_BASE +0x50b39*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50b3a*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50b3b*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50b3c*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50b3d*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50b3e*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x50b3f*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x50b40*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x50b41*4 +0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x50b42*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x50b43*4 +0x02000000,0xea06); +reg_write( DDR_REG_BASE +0x50b44*4 +0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x50b45*4 +0x02000000,0xa01); +reg_write( DDR_REG_BASE +0x50b46*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x50b47*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50b48*4 +0x02000000,0xb8c3); +reg_write( DDR_REG_BASE +0x50b49*4 +0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x50b4a*4 +0x02000000,0x70); +reg_write( DDR_REG_BASE +0x50b4b*4 +0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x50b4c*4 +0x02000000,0x807); +reg_write( DDR_REG_BASE +0x50b4d*4 +0x02000000,0x190); +reg_write( DDR_REG_BASE +0x50b4e*4 +0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x50b4f*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50b50*4 +0x02000000,0xa3e); +reg_write( DDR_REG_BASE +0x50b51*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50b52*4 +0x02000000,0xd940); +reg_write( DDR_REG_BASE +0x50b53*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50b54*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x50b55*4 +0x02000000,0xe112); +reg_write( DDR_REG_BASE +0x50b56*4 +0x02000000,0x1ede); +reg_write( DDR_REG_BASE +0x50b57*4 +0x02000000,0x1055); +reg_write( DDR_REG_BASE +0x50b58*4 +0x02000000,0x1ea6); +reg_write( DDR_REG_BASE +0x50b59*4 +0x02000000,0x9055); +reg_write( DDR_REG_BASE +0x50b5a*4 +0x02000000,0x17b6); +reg_write( DDR_REG_BASE +0x50b5b*4 +0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x50b5c*4 +0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x50b5d*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50b5e*4 +0x02000000,0xed29); +reg_write( DDR_REG_BASE +0x50b5f*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50b60*4 +0x02000000,0x84f); +reg_write( DDR_REG_BASE +0x50b61*4 +0x02000000,0x3bf); +reg_write( DDR_REG_BASE +0x50b62*4 +0x02000000,0xd91c); +reg_write( DDR_REG_BASE +0x50b63*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50b64*4 +0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x50b65*4 +0x02000000,0xc07); +reg_write( DDR_REG_BASE +0x50b66*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50b67*4 +0x02000000,0xb88f); +reg_write( DDR_REG_BASE +0x50b68*4 +0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x50b69*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50b6a*4 +0x02000000,0xa0a); +reg_write( DDR_REG_BASE +0x50b6b*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50b6c*4 +0x02000000,0x1ef6); +reg_write( DDR_REG_BASE +0x50b6d*4 +0x02000000,0x9205); +reg_write( DDR_REG_BASE +0x50b6e*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50b6f*4 +0x02000000,0xf); +reg_write( DDR_REG_BASE +0x50b70*4 +0x02000000,0x4240); +reg_write( DDR_REG_BASE +0x50b71*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50b72*4 +0x02000000,0x9fa); +reg_write( DDR_REG_BASE +0x50b73*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50b74*4 +0x02000000,0x1ef6); +reg_write( DDR_REG_BASE +0x50b75*4 +0x02000000,0x9245); +reg_write( DDR_REG_BASE +0x50b76*4 +0x02000000,0x17be); +reg_write( DDR_REG_BASE +0x50b77*4 +0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x50b78*4 +0x02000000,0x1ef0); +reg_write( DDR_REG_BASE +0x50b79*4 +0x02000000,0x9045); +reg_write( DDR_REG_BASE +0x50b7a*4 +0x02000000,0x1ef6); +reg_write( DDR_REG_BASE +0x50b7b*4 +0x02000000,0x9205); +reg_write( DDR_REG_BASE +0x50b7c*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x50b7d*4 +0x02000000,0x8); +reg_write( DDR_REG_BASE +0x50b7e*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x50b7f*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x50b80*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50b81*4 +0x02000000,0x3e00); +reg_write( DDR_REG_BASE +0x50b82*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50b83*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50b84*4 +0x02000000,0xb88e); +reg_write( DDR_REG_BASE +0x50b85*4 +0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x50b86*4 +0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x50b87*4 +0x02000000,0x1ef6); +reg_write( DDR_REG_BASE +0x50b88*4 +0x02000000,0x9205); +reg_write( DDR_REG_BASE +0x50b89*4 +0x02000000,0x1ef0); +reg_write( DDR_REG_BASE +0x50b8a*4 +0x02000000,0x9045); +reg_write( DDR_REG_BASE +0x50b8b*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50b8c*4 +0x02000000,0x76c4); +reg_write( DDR_REG_BASE +0x50b8d*4 +0x02000000,0x9013); +reg_write( DDR_REG_BASE +0x50b8e*4 +0x02000000,0xe050); +reg_write( DDR_REG_BASE +0x50b8f*4 +0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x50b90*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50b91*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50b92*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50b93*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50b94*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50b95*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50b96*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50b97*4 +0x02000000,0xc1a2); +reg_write( DDR_REG_BASE +0x50b98*4 +0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x50b99*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50b9a*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50b9b*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x50b9c*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x50b9d*4 +0x02000000,0x9b); +reg_write( DDR_REG_BASE +0x50b9e*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x50b9f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50ba0*4 +0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x50ba1*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50ba2*4 +0x02000000,0xea6); +reg_write( DDR_REG_BASE +0x50ba3*4 +0x02000000,0x220); +reg_write( DDR_REG_BASE +0x50ba4*4 +0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50ba5*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50ba6*4 +0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50ba7*4 +0x02000000,0xe3a); +reg_write( DDR_REG_BASE +0x50ba8*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50ba9*4 +0x02000000,0xda7f); +reg_write( DDR_REG_BASE +0x50baa*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50bab*4 +0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50bac*4 +0x02000000,0xe2e); +reg_write( DDR_REG_BASE +0x50bad*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50bae*4 +0x02000000,0xdafe); +reg_write( DDR_REG_BASE +0x50baf*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50bb0*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50bb1*4 +0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x50bb2*4 +0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x50bb3*4 +0x02000000,0x2653); +reg_write( DDR_REG_BASE +0x50bb4*4 +0x02000000,0x104f); +reg_write( DDR_REG_BASE +0x50bb5*4 +0x02000000,0xe81c); +reg_write( DDR_REG_BASE +0x50bb6*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50bb7*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50bb8*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50bb9*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50bba*4 +0x02000000,0x82d); +reg_write( DDR_REG_BASE +0x50bbb*4 +0x02000000,0xff); +reg_write( DDR_REG_BASE +0x50bbc*4 +0x02000000,0x2778); +reg_write( DDR_REG_BASE +0x50bbd*4 +0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x50bbe*4 +0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x50bbf*4 +0x02000000,0x3c82); +reg_write( DDR_REG_BASE +0x50bc0*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x50bc1*4 +0x02000000,0x641); +reg_write( DDR_REG_BASE +0x50bc2*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x50bc3*4 +0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x50bc4*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x50bc5*4 +0x02000000,0xdfff); +reg_write( DDR_REG_BASE +0x50bc6*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x50bc7*4 +0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x50bc8*4 +0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x50bc9*4 +0x02000000,0x61b9); +reg_write( DDR_REG_BASE +0x50bca*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50bcb*4 +0x02000000,0x9f2); +reg_write( DDR_REG_BASE +0x50bcc*4 +0x02000000,0x2e0); +reg_write( DDR_REG_BASE +0x50bcd*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x50bce*4 +0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x50bcf*4 +0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x50bd0*4 +0x02000000,0xe12); +reg_write( DDR_REG_BASE +0x50bd1*4 +0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x50bd2*4 +0x02000000,0x2778); +reg_write( DDR_REG_BASE +0x50bd3*4 +0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x50bd4*4 +0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x50bd5*4 +0x02000000,0x3c82); +reg_write( DDR_REG_BASE +0x50bd6*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x50bd7*4 +0x02000000,0x641); +reg_write( DDR_REG_BASE +0x50bd8*4 +0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x50bd9*4 +0x02000000,0x1100); +reg_write( DDR_REG_BASE +0x50bda*4 +0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x50bdb*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x50bdc*4 +0x02000000,0xdfff); +reg_write( DDR_REG_BASE +0x50bdd*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x50bde*4 +0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x50bdf*4 +0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x50be0*4 +0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x50be1*4 +0x02000000,0x61b9); +reg_write( DDR_REG_BASE +0x50be2*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x50be3*4 +0x02000000,0x87a); +reg_write( DDR_REG_BASE +0x50be4*4 +0x02000000,0x2e0); +reg_write( DDR_REG_BASE +0x50be5*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50be6*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50be7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50be8*4 +0x02000000,0x36b0); +reg_write( DDR_REG_BASE +0x50be9*4 +0x02000000,0x90e); +reg_write( DDR_REG_BASE +0x50bea*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50beb*4 +0x02000000,0xd90a); +reg_write( DDR_REG_BASE +0x50bec*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50bed*4 +0x02000000,0xa12); +reg_write( DDR_REG_BASE +0x50bee*4 +0x02000000,0x220); +reg_write( DDR_REG_BASE +0x50bef*4 +0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x50bf0*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50bf1*4 +0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x50bf2*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x50bf3*4 +0x02000000,0xe048); +reg_write( DDR_REG_BASE +0x50bf4*4 +0x02000000,0xc0a2); +reg_write( DDR_REG_BASE +0x50bf5*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50bf6*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50bf7*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50bf8*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50bf9*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50bfa*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50bfb*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50bfc*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50bfd*4 +0x02000000,0xf4); +reg_write( DDR_REG_BASE +0x50bfe*4 +0x02000000,0x6ea2); +reg_write( DDR_REG_BASE +0x50bff*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50c00*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50c01*4 +0x02000000,0x111b); +reg_write( DDR_REG_BASE +0x50c02*4 +0x02000000,0x1500); +reg_write( DDR_REG_BASE +0x50c03*4 +0x02000000,0x111e); +reg_write( DDR_REG_BASE +0x50c04*4 +0x02000000,0x1506); +reg_write( DDR_REG_BASE +0x50c05*4 +0x02000000,0x110b); +reg_write( DDR_REG_BASE +0x50c06*4 +0x02000000,0x95e4); +reg_write( DDR_REG_BASE +0x50c07*4 +0x02000000,0x1d08); +reg_write( DDR_REG_BASE +0x50c08*4 +0x02000000,0x13c5); +reg_write( DDR_REG_BASE +0x50c09*4 +0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x50c0a*4 +0x02000000,0x1d06); +reg_write( DDR_REG_BASE +0x50c0b*4 +0x02000000,0x13c5); +reg_write( DDR_REG_BASE +0x50c0c*4 +0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x50c0d*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50c0e*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50c0f*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x50c10*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x50c11*4 +0x02000000,0x190); +reg_write( DDR_REG_BASE +0x50c12*4 +0x02000000,0xd834); +reg_write( DDR_REG_BASE +0x50c13*4 +0x02000000,0x1efa); +reg_write( DDR_REG_BASE +0x50c14*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50c15*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50c16*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50c17*4 +0x02000000,0x2af8); +reg_write( DDR_REG_BASE +0x50c18*4 +0x02000000,0x8ae); +reg_write( DDR_REG_BASE +0x50c19*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50c1a*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50c1b*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50c1c*4 +0x02000000,0x16c4); +reg_write( DDR_REG_BASE +0x50c1d*4 +0x02000000,0x1d06); +reg_write( DDR_REG_BASE +0x50c1e*4 +0x02000000,0x12c4); +reg_write( DDR_REG_BASE +0x50c1f*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50c20*4 +0x02000000,0x1784); +reg_write( DDR_REG_BASE +0x50c21*4 +0x02000000,0xb5e4); +reg_write( DDR_REG_BASE +0x50c22*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50c23*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50c24*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50c25*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50c26*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50c27*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50c28*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50c29*4 +0x02000000,0x236f); +reg_write( DDR_REG_BASE +0x50c2a*4 +0x02000000,0x343); +reg_write( DDR_REG_BASE +0x50c2b*4 +0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x50c2c*4 +0x02000000,0x3040); +reg_write( DDR_REG_BASE +0x50c2d*4 +0x02000000,0x9320); +reg_write( DDR_REG_BASE +0x50c2e*4 +0x02000000,0x4348); +reg_write( DDR_REG_BASE +0x50c2f*4 +0x02000000,0x218c); +reg_write( DDR_REG_BASE +0x50c30*4 +0x02000000,0x864a); +reg_write( DDR_REG_BASE +0x50c31*4 +0x02000000,0x80); +reg_write( DDR_REG_BASE +0x50c32*4 +0x02000000,0x2d); +reg_write( DDR_REG_BASE +0x50c33*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x50c34*4 +0x02000000,0xe02); +reg_write( DDR_REG_BASE +0x50c35*4 +0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x50c36*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x50c37*4 +0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x50c38*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x50c39*4 +0x02000000,0x2042); +reg_write( DDR_REG_BASE +0x50c3a*4 +0x02000000,0x11b); +reg_write( DDR_REG_BASE +0x50c3b*4 +0x02000000,0x13fe); +reg_write( DDR_REG_BASE +0x50c3c*4 +0x02000000,0x8080); +reg_write( DDR_REG_BASE +0x50c3d*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50c3e*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50c3f*4 +0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x50c40*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x50c41*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50c42*4 +0x02000000,0xf02a); +reg_write( DDR_REG_BASE +0x50c43*4 +0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x50c44*4 +0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x50c45*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50c46*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x50c47*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50c48*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x50c49*4 +0x02000000,0x381); +reg_write( DDR_REG_BASE +0x50c4a*4 +0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x50c4b*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x50c4c*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50c4d*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50c4e*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x50c4f*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x50c50*4 +0x02000000,0xf8f); +reg_write( DDR_REG_BASE +0x50c51*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50c52*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50c53*4 +0x02000000,0xe4a); +reg_write( DDR_REG_BASE +0x50c54*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50c55*4 +0x02000000,0x9700); +reg_write( DDR_REG_BASE +0x50c56*4 +0x02000000,0x7063); +reg_write( DDR_REG_BASE +0x50c57*4 +0x02000000,0x7a0e); +reg_write( DDR_REG_BASE +0x50c58*4 +0x02000000,0x785c); +reg_write( DDR_REG_BASE +0x50c59*4 +0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x50c5a*4 +0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x50c5b*4 +0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x50c5c*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x50c5d*4 +0x02000000,0xd81b); +reg_write( DDR_REG_BASE +0x50c5e*4 +0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x50c5f*4 +0x02000000,0x801); +reg_write( DDR_REG_BASE +0x50c60*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x50c61*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50c62*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x50c63*4 +0x02000000,0x6238); +reg_write( DDR_REG_BASE +0x50c64*4 +0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x50c65*4 +0x02000000,0x4831); +reg_write( DDR_REG_BASE +0x50c66*4 +0x02000000,0x2a44); +reg_write( DDR_REG_BASE +0x50c67*4 +0x02000000,0x800); +reg_write( DDR_REG_BASE +0x50c68*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x50c69*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50c6a*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50c6b*4 +0x02000000,0xb700); +reg_write( DDR_REG_BASE +0x50c6c*4 +0x02000000,0xbaf); +reg_write( DDR_REG_BASE +0x50c6d*4 +0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x50c6e*4 +0x02000000,0x2555); +reg_write( DDR_REG_BASE +0x50c6f*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x50c70*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50c71*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50c72*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50c73*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50c74*4 +0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x50c75*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x50c76*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50c77*4 +0x02000000,0x6); +reg_write( DDR_REG_BASE +0x50c78*4 +0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x50c79*4 +0x02000000,0xf96); +reg_write( DDR_REG_BASE +0x50c7a*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50c7b*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50c7c*4 +0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x50c7d*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50c7e*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x50c7f*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x50c80*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50c81*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x50c82*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50c83*4 +0x02000000,0x1c6); +reg_write( DDR_REG_BASE +0x50c84*4 +0x02000000,0x95c0); +reg_write( DDR_REG_BASE +0x50c85*4 +0x02000000,0xbecb); +reg_write( DDR_REG_BASE +0x50c86*4 +0x02000000,0x264f); +reg_write( DDR_REG_BASE +0x50c87*4 +0x02000000,0x12cf); +reg_write( DDR_REG_BASE +0x50c88*4 +0x02000000,0x2605); +reg_write( DDR_REG_BASE +0x50c89*4 +0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x50c8a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50c8b*4 +0x02000000,0xc00); +reg_write( DDR_REG_BASE +0x50c8c*4 +0x02000000,0xb5e0); +reg_write( DDR_REG_BASE +0x50c8d*4 +0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x50c8e*4 +0x02000000,0xf6a); +reg_write( DDR_REG_BASE +0x50c8f*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50c90*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x50c91*4 +0x02000000,0xb5e0); +reg_write( DDR_REG_BASE +0x50c92*4 +0x02000000,0x9501); +reg_write( DDR_REG_BASE +0x50c93*4 +0x02000000,0xb5c0); +reg_write( DDR_REG_BASE +0x50c94*4 +0x02000000,0xb8c9); +reg_write( DDR_REG_BASE +0x50c95*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50c96*4 +0x02000000,0xc1e2); +reg_write( DDR_REG_BASE +0x50c97*4 +0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x50c98*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x50c99*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x50c9a*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50c9b*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x50c9c*4 +0x02000000,0x86); +reg_write( DDR_REG_BASE +0x50c9d*4 +0x02000000,0x9020); +reg_write( DDR_REG_BASE +0x50c9e*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50c9f*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50ca0*4 +0x02000000,0x2153); +reg_write( DDR_REG_BASE +0x50ca1*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x50ca2*4 +0x02000000,0x1c02); +reg_write( DDR_REG_BASE +0x50ca3*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x50ca4*4 +0x02000000,0x783d); +reg_write( DDR_REG_BASE +0x50ca5*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50ca6*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50ca7*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50ca8*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50ca9*4 +0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x50caa*4 +0x02000000,0x1c03); +reg_write( DDR_REG_BASE +0x50cab*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x50cac*4 +0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x50cad*4 +0x02000000,0x606c); +reg_write( DDR_REG_BASE +0x50cae*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x50caf*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50cb0*4 +0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x50cb1*4 +0x02000000,0x61b9); +reg_write( DDR_REG_BASE +0x50cb2*4 +0x02000000,0x7c9d); +reg_write( DDR_REG_BASE +0x50cb3*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x50cb4*4 +0x02000000,0x8fb); +reg_write( DDR_REG_BASE +0x50cb5*4 +0x02000000,0x8174); +reg_write( DDR_REG_BASE +0x50cb6*4 +0x02000000,0x2444); +reg_write( DDR_REG_BASE +0x50cb7*4 +0x02000000,0x104d); +reg_write( DDR_REG_BASE +0x50cb8*4 +0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x50cb9*4 +0x02000000,0xd978); +reg_write( DDR_REG_BASE +0x50cba*4 +0x02000000,0x2905); +reg_write( DDR_REG_BASE +0x50cbb*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50cbc*4 +0x02000000,0x784f); +reg_write( DDR_REG_BASE +0x50cbd*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x50cbe*4 +0x02000000,0x611a); +reg_write( DDR_REG_BASE +0x50cbf*4 +0x02000000,0xbdf); +reg_write( DDR_REG_BASE +0x50cc0*4 +0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x50cc1*4 +0x02000000,0x2440); +reg_write( DDR_REG_BASE +0x50cc2*4 +0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x50cc3*4 +0x02000000,0x2284); +reg_write( DDR_REG_BASE +0x50cc4*4 +0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x50cc5*4 +0x02000000,0x785d); +reg_write( DDR_REG_BASE +0x50cc6*4 +0x02000000,0xc5c2); +reg_write( DDR_REG_BASE +0x50cc7*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50cc8*4 +0x02000000,0x701); +reg_write( DDR_REG_BASE +0x50cc9*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50cca*4 +0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x50ccb*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50ccc*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50ccd*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50cce*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50ccf*4 +0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x50cd0*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50cd1*4 +0x02000000,0x711e); +reg_write( DDR_REG_BASE +0x50cd2*4 +0x02000000,0x9018); +reg_write( DDR_REG_BASE +0x50cd3*4 +0x02000000,0x1dc); +reg_write( DDR_REG_BASE +0x50cd4*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50cd5*4 +0x02000000,0x308c); +reg_write( DDR_REG_BASE +0x50cd6*4 +0x02000000,0xc609); +reg_write( DDR_REG_BASE +0x50cd7*4 +0x02000000,0x4378); +reg_write( DDR_REG_BASE +0x50cd8*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50cd9*4 +0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x50cda*4 +0x02000000,0x43cb); +reg_write( DDR_REG_BASE +0x50cdb*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50cdc*4 +0x02000000,0x200); +reg_write( DDR_REG_BASE +0x50cdd*4 +0x02000000,0x2705); +reg_write( DDR_REG_BASE +0x50cde*4 +0x02000000,0x32cd); +reg_write( DDR_REG_BASE +0x50cdf*4 +0x02000000,0x95a0); +reg_write( DDR_REG_BASE +0x50ce0*4 +0x02000000,0xc780); +reg_write( DDR_REG_BASE +0x50ce1*4 +0x02000000,0x677f); +reg_write( DDR_REG_BASE +0x50ce2*4 +0x02000000,0x2340); +reg_write( DDR_REG_BASE +0x50ce3*4 +0x02000000,0x180b); +reg_write( DDR_REG_BASE +0x50ce4*4 +0x02000000,0xafa0); +reg_write( DDR_REG_BASE +0x50ce5*4 +0x02000000,0x2705); +reg_write( DDR_REG_BASE +0x50ce6*4 +0x02000000,0x32cd); +reg_write( DDR_REG_BASE +0x50ce7*4 +0x02000000,0x95a0); +reg_write( DDR_REG_BASE +0x50ce8*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x50ce9*4 +0x02000000,0xe508); +reg_write( DDR_REG_BASE +0x50cea*4 +0x02000000,0xafa8); +reg_write( DDR_REG_BASE +0x50ceb*4 +0x02000000,0xbe1); +reg_write( DDR_REG_BASE +0x50cec*4 +0x02000000,0x81b4); +reg_write( DDR_REG_BASE +0x50ced*4 +0x02000000,0x272f); +reg_write( DDR_REG_BASE +0x50cee*4 +0x02000000,0x30c0); +reg_write( DDR_REG_BASE +0x50cef*4 +0x02000000,0xe48c); +reg_write( DDR_REG_BASE +0x50cf0*4 +0x02000000,0x304); +reg_write( DDR_REG_BASE +0x50cf1*4 +0x02000000,0x2d); +reg_write( DDR_REG_BASE +0x50cf2*4 +0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x50cf3*4 +0x02000000,0x205); +reg_write( DDR_REG_BASE +0x50cf4*4 +0x02000000,0xb9d); +reg_write( DDR_REG_BASE +0x50cf5*4 +0x02000000,0x32e); +reg_write( DDR_REG_BASE +0x50cf6*4 +0x02000000,0x746d); +reg_write( DDR_REG_BASE +0x50cf7*4 +0x02000000,0xc0f); +reg_write( DDR_REG_BASE +0x50cf8*4 +0x02000000,0x1230); +reg_write( DDR_REG_BASE +0x50cf9*4 +0x02000000,0x1b00); +reg_write( DDR_REG_BASE +0x50cfa*4 +0x02000000,0x32c2); +reg_write( DDR_REG_BASE +0x50cfb*4 +0x02000000,0x7695); +reg_write( DDR_REG_BASE +0x50cfc*4 +0x02000000,0xf4af); +reg_write( DDR_REG_BASE +0x50cfd*4 +0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x50cfe*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50cff*4 +0x02000000,0xaea3); +reg_write( DDR_REG_BASE +0x50d00*4 +0x02000000,0xaea2); +reg_write( DDR_REG_BASE +0x50d01*4 +0x02000000,0xae61); +reg_write( DDR_REG_BASE +0x50d02*4 +0x02000000,0xae60); +reg_write( DDR_REG_BASE +0x50d03*4 +0x02000000,0x75ed); +reg_write( DDR_REG_BASE +0x50d04*4 +0x02000000,0x73cd); +reg_write( DDR_REG_BASE +0x50d05*4 +0x02000000,0x728d); +reg_write( DDR_REG_BASE +0x50d06*4 +0x02000000,0xa9e3); +reg_write( DDR_REG_BASE +0x50d07*4 +0x02000000,0xa9c2); +reg_write( DDR_REG_BASE +0x50d08*4 +0x02000000,0xa981); +reg_write( DDR_REG_BASE +0x50d09*4 +0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50d0a*4 +0x02000000,0xaac5); +reg_write( DDR_REG_BASE +0x50d0b*4 +0x02000000,0xaa83); +reg_write( DDR_REG_BASE +0x50d0c*4 +0x02000000,0xaaa2); +reg_write( DDR_REG_BASE +0x50d0d*4 +0x02000000,0xaa60); +reg_write( DDR_REG_BASE +0x50d0e*4 +0x02000000,0xc120); +reg_write( DDR_REG_BASE +0x50d0f*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d10*4 +0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50d11*4 +0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x50d12*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d13*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d14*4 +0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50d15*4 +0x02000000,0x1402); +reg_write( DDR_REG_BASE +0x50d16*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d17*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d18*4 +0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50d19*4 +0x02000000,0x1403); +reg_write( DDR_REG_BASE +0x50d1a*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d1b*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d1c*4 +0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50d1d*4 +0x02000000,0xc121); +reg_write( DDR_REG_BASE +0x50d1e*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d1f*4 +0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50d20*4 +0x02000000,0x1405); +reg_write( DDR_REG_BASE +0x50d21*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d22*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d23*4 +0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50d24*4 +0x02000000,0xa8a7); +reg_write( DDR_REG_BASE +0x50d25*4 +0x02000000,0xa8a6); +reg_write( DDR_REG_BASE +0x50d26*4 +0x02000000,0xc122); +reg_write( DDR_REG_BASE +0x50d27*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d28*4 +0x02000000,0xa9c0); +reg_write( DDR_REG_BASE +0x50d29*4 +0x02000000,0x1409); +reg_write( DDR_REG_BASE +0x50d2a*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d2b*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d2c*4 +0x02000000,0xa9c0); +reg_write( DDR_REG_BASE +0x50d2d*4 +0x02000000,0x140a); +reg_write( DDR_REG_BASE +0x50d2e*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d2f*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d30*4 +0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50d31*4 +0x02000000,0x140b); +reg_write( DDR_REG_BASE +0x50d32*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d33*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d34*4 +0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50d35*4 +0x02000000,0xc123); +reg_write( DDR_REG_BASE +0x50d36*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d37*4 +0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50d38*4 +0x02000000,0x140d); +reg_write( DDR_REG_BASE +0x50d39*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d3a*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d3b*4 +0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50d3c*4 +0x02000000,0x180f); +reg_write( DDR_REG_BASE +0x50d3d*4 +0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50d3e*4 +0x02000000,0x269); +reg_write( DDR_REG_BASE +0x50d3f*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50d40*4 +0x02000000,0x180e); +reg_write( DDR_REG_BASE +0x50d41*4 +0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50d42*4 +0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x50d43*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50d44*4 +0x02000000,0x1400); +reg_write( DDR_REG_BASE +0x50d45*4 +0x02000000,0x2311); +reg_write( DDR_REG_BASE +0x50d46*4 +0x02000000,0x8300); +reg_write( DDR_REG_BASE +0x50d47*4 +0x02000000,0x258); +reg_write( DDR_REG_BASE +0x50d48*4 +0x02000000,0x21); +reg_write( DDR_REG_BASE +0x50d49*4 +0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x50d4a*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50d4b*4 +0x02000000,0xaee5); +reg_write( DDR_REG_BASE +0x50d4c*4 +0x02000000,0xaee4); +reg_write( DDR_REG_BASE +0x50d4d*4 +0x02000000,0xaee3); +reg_write( DDR_REG_BASE +0x50d4e*4 +0x02000000,0xae62); +reg_write( DDR_REG_BASE +0x50d4f*4 +0x02000000,0xae61); +reg_write( DDR_REG_BASE +0x50d50*4 +0x02000000,0xae60); +reg_write( DDR_REG_BASE +0x50d51*4 +0x02000000,0x260c); +reg_write( DDR_REG_BASE +0x50d52*4 +0x02000000,0xbf80); +reg_write( DDR_REG_BASE +0x50d53*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50d54*4 +0x02000000,0x2208); +reg_write( DDR_REG_BASE +0x50d55*4 +0x02000000,0x73ad); +reg_write( DDR_REG_BASE +0x50d56*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x50d57*4 +0x02000000,0xf47c); +reg_write( DDR_REG_BASE +0x50d58*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x50d59*4 +0x02000000,0x1b00); +reg_write( DDR_REG_BASE +0x50d5a*4 +0x02000000,0x3143); +reg_write( DDR_REG_BASE +0x50d5b*4 +0x02000000,0xaee4); +reg_write( DDR_REG_BASE +0x50d5c*4 +0x02000000,0xaee3); +reg_write( DDR_REG_BASE +0x50d5d*4 +0x02000000,0xaee2); +reg_write( DDR_REG_BASE +0x50d5e*4 +0x02000000,0xae81); +reg_write( DDR_REG_BASE +0x50d5f*4 +0x02000000,0xae80); +reg_write( DDR_REG_BASE +0x50d60*4 +0x02000000,0xde0b); +reg_write( DDR_REG_BASE +0x50d61*4 +0x02000000,0x234a); +reg_write( DDR_REG_BASE +0x50d62*4 +0x02000000,0x1280); +reg_write( DDR_REG_BASE +0x50d63*4 +0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x50d64*4 +0x02000000,0x3180); +reg_write( DDR_REG_BASE +0x50d65*4 +0x02000000,0xa9c4); +reg_write( DDR_REG_BASE +0x50d66*4 +0x02000000,0x1903); +reg_write( DDR_REG_BASE +0x50d67*4 +0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50d68*4 +0x02000000,0x1902); +reg_write( DDR_REG_BASE +0x50d69*4 +0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50d6a*4 +0x02000000,0xa9a1); +reg_write( DDR_REG_BASE +0x50d6b*4 +0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50d6c*4 +0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x50d6d*4 +0x02000000,0xaa2b); +reg_write( DDR_REG_BASE +0x50d6e*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50d6f*4 +0x02000000,0xaaaa); +reg_write( DDR_REG_BASE +0x50d70*4 +0x02000000,0xaa66); +reg_write( DDR_REG_BASE +0x50d71*4 +0x02000000,0xaae3); +reg_write( DDR_REG_BASE +0x50d72*4 +0x02000000,0xaa20); +reg_write( DDR_REG_BASE +0x50d73*4 +0x02000000,0xc120); +reg_write( DDR_REG_BASE +0x50d74*4 +0x02000000,0x603a); +reg_write( DDR_REG_BASE +0x50d75*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50d76*4 +0x02000000,0xaa20); +reg_write( DDR_REG_BASE +0x50d77*4 +0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x50d78*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d79*4 +0x02000000,0x603a); +reg_write( DDR_REG_BASE +0x50d7a*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50d7b*4 +0x02000000,0xaa20); +reg_write( DDR_REG_BASE +0x50d7c*4 +0x02000000,0x1402); +reg_write( DDR_REG_BASE +0x50d7d*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d7e*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d7f*4 +0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50d80*4 +0x02000000,0x1403); +reg_write( DDR_REG_BASE +0x50d81*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d82*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d83*4 +0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50d84*4 +0x02000000,0xc121); +reg_write( DDR_REG_BASE +0x50d85*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d86*4 +0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50d87*4 +0x02000000,0x1405); +reg_write( DDR_REG_BASE +0x50d88*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d89*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d8a*4 +0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50d8b*4 +0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x50d8c*4 +0x02000000,0xa8e7); +reg_write( DDR_REG_BASE +0x50d8d*4 +0x02000000,0xa826); +reg_write( DDR_REG_BASE +0x50d8e*4 +0x02000000,0xc122); +reg_write( DDR_REG_BASE +0x50d8f*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d90*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50d91*4 +0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50d92*4 +0x02000000,0x1409); +reg_write( DDR_REG_BASE +0x50d93*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d94*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d95*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50d96*4 +0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50d97*4 +0x02000000,0x140a); +reg_write( DDR_REG_BASE +0x50d98*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d99*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d9a*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50d9b*4 +0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50d9c*4 +0x02000000,0x140b); +reg_write( DDR_REG_BASE +0x50d9d*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d9e*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50d9f*4 +0x02000000,0xa9c0); +reg_write( DDR_REG_BASE +0x50da0*4 +0x02000000,0xc123); +reg_write( DDR_REG_BASE +0x50da1*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50da2*4 +0x02000000,0xa9c0); +reg_write( DDR_REG_BASE +0x50da3*4 +0x02000000,0x140d); +reg_write( DDR_REG_BASE +0x50da4*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50da5*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50da6*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50da7*4 +0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50da8*4 +0x02000000,0x180f); +reg_write( DDR_REG_BASE +0x50da9*4 +0x02000000,0x1c3); +reg_write( DDR_REG_BASE +0x50daa*4 +0x02000000,0xf079); +reg_write( DDR_REG_BASE +0x50dab*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x50dac*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x50dad*4 +0x02000000,0x1b00); +reg_write( DDR_REG_BASE +0x50dae*4 +0x02000000,0x30c2); +reg_write( DDR_REG_BASE +0x50daf*4 +0x02000000,0xae81); +reg_write( DDR_REG_BASE +0x50db0*4 +0x02000000,0xae80); +reg_write( DDR_REG_BASE +0x50db1*4 +0x02000000,0xa961); +reg_write( DDR_REG_BASE +0x50db2*4 +0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50db3*4 +0x02000000,0x718d); +reg_write( DDR_REG_BASE +0x50db4*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50db5*4 +0x02000000,0xaa82); +reg_write( DDR_REG_BASE +0x50db6*4 +0x02000000,0xaa20); +reg_write( DDR_REG_BASE +0x50db7*4 +0x02000000,0xc120); +reg_write( DDR_REG_BASE +0x50db8*4 +0x02000000,0x603a); +reg_write( DDR_REG_BASE +0x50db9*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50dba*4 +0x02000000,0xaa20); +reg_write( DDR_REG_BASE +0x50dbb*4 +0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x50dbc*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50dbd*4 +0x02000000,0x603a); +reg_write( DDR_REG_BASE +0x50dbe*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50dbf*4 +0x02000000,0xaa20); +reg_write( DDR_REG_BASE +0x50dc0*4 +0x02000000,0x1402); +reg_write( DDR_REG_BASE +0x50dc1*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50dc2*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50dc3*4 +0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50dc4*4 +0x02000000,0x1403); +reg_write( DDR_REG_BASE +0x50dc5*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50dc6*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50dc7*4 +0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50dc8*4 +0x02000000,0xc121); +reg_write( DDR_REG_BASE +0x50dc9*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50dca*4 +0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50dcb*4 +0x02000000,0x1405); +reg_write( DDR_REG_BASE +0x50dcc*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50dcd*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50dce*4 +0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50dcf*4 +0x02000000,0xa887); +reg_write( DDR_REG_BASE +0x50dd0*4 +0x02000000,0xa886); +reg_write( DDR_REG_BASE +0x50dd1*4 +0x02000000,0xf0a2); +reg_write( DDR_REG_BASE +0x50dd2*4 +0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x50dd3*4 +0x02000000,0x3200); +reg_write( DDR_REG_BASE +0x50dd4*4 +0x02000000,0xca5); +reg_write( DDR_REG_BASE +0x50dd5*4 +0x02000000,0x1331); +reg_write( DDR_REG_BASE +0x50dd6*4 +0x02000000,0x234a); +reg_write( DDR_REG_BASE +0x50dd7*4 +0x02000000,0x11c0); +reg_write( DDR_REG_BASE +0x50dd8*4 +0x02000000,0x768d); +reg_write( DDR_REG_BASE +0x50dd9*4 +0x02000000,0x1b00); +reg_write( DDR_REG_BASE +0x50dda*4 +0x02000000,0x3302); +reg_write( DDR_REG_BASE +0x50ddb*4 +0x02000000,0x1905); +reg_write( DDR_REG_BASE +0x50ddc*4 +0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50ddd*4 +0x02000000,0x1904); +reg_write( DDR_REG_BASE +0x50dde*4 +0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50ddf*4 +0x02000000,0xa983); +reg_write( DDR_REG_BASE +0x50de0*4 +0x02000000,0xa9a2); +reg_write( DDR_REG_BASE +0x50de1*4 +0x02000000,0xa961); +reg_write( DDR_REG_BASE +0x50de2*4 +0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50de3*4 +0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x50de4*4 +0x02000000,0x1a08); +reg_write( DDR_REG_BASE +0x50de5*4 +0x02000000,0x143); +reg_write( DDR_REG_BASE +0x50de6*4 +0x02000000,0xaa27); +reg_write( DDR_REG_BASE +0x50de7*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50de8*4 +0x02000000,0xaaa6); +reg_write( DDR_REG_BASE +0x50de9*4 +0x02000000,0xaa63); +reg_write( DDR_REG_BASE +0x50dea*4 +0x02000000,0xaae2); +reg_write( DDR_REG_BASE +0x50deb*4 +0x02000000,0xaa21); +reg_write( DDR_REG_BASE +0x50dec*4 +0x02000000,0xc120); +reg_write( DDR_REG_BASE +0x50ded*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50dee*4 +0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50def*4 +0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x50df0*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50df1*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50df2*4 +0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50df3*4 +0x02000000,0x1402); +reg_write( DDR_REG_BASE +0x50df4*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50df5*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50df6*4 +0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50df7*4 +0x02000000,0x1403); +reg_write( DDR_REG_BASE +0x50df8*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50df9*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50dfa*4 +0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50dfb*4 +0x02000000,0xc121); +reg_write( DDR_REG_BASE +0x50dfc*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50dfd*4 +0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50dfe*4 +0x02000000,0x1405); +reg_write( DDR_REG_BASE +0x50dff*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e00*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e01*4 +0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50e02*4 +0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x50e03*4 +0x02000000,0x1807); +reg_write( DDR_REG_BASE +0x50e04*4 +0x02000000,0x243); +reg_write( DDR_REG_BASE +0x50e05*4 +0x02000000,0xa826); +reg_write( DDR_REG_BASE +0x50e06*4 +0x02000000,0xc122); +reg_write( DDR_REG_BASE +0x50e07*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e08*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e09*4 +0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50e0a*4 +0x02000000,0x1409); +reg_write( DDR_REG_BASE +0x50e0b*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e0c*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e0d*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e0e*4 +0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50e0f*4 +0x02000000,0x140a); +reg_write( DDR_REG_BASE +0x50e10*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e11*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e12*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e13*4 +0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50e14*4 +0x02000000,0x140b); +reg_write( DDR_REG_BASE +0x50e15*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e16*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e17*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e18*4 +0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50e19*4 +0x02000000,0xc123); +reg_write( DDR_REG_BASE +0x50e1a*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e1b*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e1c*4 +0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50e1d*4 +0x02000000,0x140d); +reg_write( DDR_REG_BASE +0x50e1e*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e1f*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e20*4 +0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50e21*4 +0x02000000,0x180f); +reg_write( DDR_REG_BASE +0x50e22*4 +0x02000000,0x283); +reg_write( DDR_REG_BASE +0x50e23*4 +0x02000000,0x180e); +reg_write( DDR_REG_BASE +0x50e24*4 +0x02000000,0x143); +reg_write( DDR_REG_BASE +0x50e25*4 +0x02000000,0xf04e); +reg_write( DDR_REG_BASE +0x50e26*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x50e27*4 +0x02000000,0xaee3); +reg_write( DDR_REG_BASE +0x50e28*4 +0x02000000,0xaee2); +reg_write( DDR_REG_BASE +0x50e29*4 +0x02000000,0xae81); +reg_write( DDR_REG_BASE +0x50e2a*4 +0x02000000,0xae80); +reg_write( DDR_REG_BASE +0x50e2b*4 +0x02000000,0x748d); +reg_write( DDR_REG_BASE +0x50e2c*4 +0x02000000,0x1b00); +reg_write( DDR_REG_BASE +0x50e2d*4 +0x02000000,0x3302); +reg_write( DDR_REG_BASE +0x50e2e*4 +0x02000000,0x1903); +reg_write( DDR_REG_BASE +0x50e2f*4 +0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50e30*4 +0x02000000,0x1902); +reg_write( DDR_REG_BASE +0x50e31*4 +0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50e32*4 +0x02000000,0xa9a1); +reg_write( DDR_REG_BASE +0x50e33*4 +0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50e34*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50e35*4 +0x02000000,0xaaa8); +reg_write( DDR_REG_BASE +0x50e36*4 +0x02000000,0xaa67); +reg_write( DDR_REG_BASE +0x50e37*4 +0x02000000,0xaae3); +reg_write( DDR_REG_BASE +0x50e38*4 +0x02000000,0xaa22); +reg_write( DDR_REG_BASE +0x50e39*4 +0x02000000,0xc120); +reg_write( DDR_REG_BASE +0x50e3a*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e3b*4 +0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50e3c*4 +0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x50e3d*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e3e*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e3f*4 +0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50e40*4 +0x02000000,0x1402); +reg_write( DDR_REG_BASE +0x50e41*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e42*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e43*4 +0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50e44*4 +0x02000000,0x1403); +reg_write( DDR_REG_BASE +0x50e45*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e46*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e47*4 +0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50e48*4 +0x02000000,0xc121); +reg_write( DDR_REG_BASE +0x50e49*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e4a*4 +0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50e4b*4 +0x02000000,0x1405); +reg_write( DDR_REG_BASE +0x50e4c*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e4d*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e4e*4 +0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50e4f*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50e50*4 +0x02000000,0xa827); +reg_write( DDR_REG_BASE +0x50e51*4 +0x02000000,0xa8e6); +reg_write( DDR_REG_BASE +0x50e52*4 +0x02000000,0xc122); +reg_write( DDR_REG_BASE +0x50e53*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e54*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e55*4 +0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50e56*4 +0x02000000,0x1409); +reg_write( DDR_REG_BASE +0x50e57*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e58*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e59*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e5a*4 +0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50e5b*4 +0x02000000,0x140a); +reg_write( DDR_REG_BASE +0x50e5c*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e5d*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e5e*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e5f*4 +0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50e60*4 +0x02000000,0x140b); +reg_write( DDR_REG_BASE +0x50e61*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e62*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e63*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e64*4 +0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50e65*4 +0x02000000,0xc123); +reg_write( DDR_REG_BASE +0x50e66*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e67*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e68*4 +0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50e69*4 +0x02000000,0x140d); +reg_write( DDR_REG_BASE +0x50e6a*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50e6b*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e6c*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50e6d*4 +0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50e6e*4 +0x02000000,0x180f); +reg_write( DDR_REG_BASE +0x50e6f*4 +0x02000000,0x143); +reg_write( DDR_REG_BASE +0x50e70*4 +0x02000000,0x180e); +reg_write( DDR_REG_BASE +0x50e71*4 +0x02000000,0x183); +reg_write( DDR_REG_BASE +0x50e72*4 +0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x50e73*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50e74*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50e75*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50e76*4 +0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x50e77*4 +0x02000000,0x641); +reg_write( DDR_REG_BASE +0x50e78*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x50e79*4 +0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x50e7a*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50e7b*4 +0x02000000,0x2132); +reg_write( DDR_REG_BASE +0x50e7c*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50e7d*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50e7e*4 +0x02000000,0x688); +reg_write( DDR_REG_BASE +0x50e7f*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50e80*4 +0x02000000,0xb8c6); +reg_write( DDR_REG_BASE +0x50e81*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50e82*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x50e83*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50e84*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50e85*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50e86*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50e87*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50e88*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50e89*4 +0x02000000,0x168); +reg_write( DDR_REG_BASE +0x50e8a*4 +0x02000000,0x21c2); +reg_write( DDR_REG_BASE +0x50e8b*4 +0x02000000,0x222); +reg_write( DDR_REG_BASE +0x50e8c*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50e8d*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50e8e*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50e8f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50e90*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x50e91*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50e92*4 +0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x50e93*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50e94*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50e95*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50e96*4 +0x02000000,0x710d); +reg_write( DDR_REG_BASE +0x50e97*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50e98*4 +0x02000000,0x1c6); +reg_write( DDR_REG_BASE +0x50e99*4 +0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x50e9a*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x50e9b*4 +0x02000000,0xe1c6); +reg_write( DDR_REG_BASE +0x50e9c*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x50e9d*4 +0x02000000,0xbdc9); +reg_write( DDR_REG_BASE +0x50e9e*4 +0x02000000,0x254f); +reg_write( DDR_REG_BASE +0x50e9f*4 +0x02000000,0x12ce); +reg_write( DDR_REG_BASE +0x50ea0*4 +0x02000000,0xb46); +reg_write( DDR_REG_BASE +0x50ea1*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50ea2*4 +0x02000000,0xb7c0); +reg_write( DDR_REG_BASE +0x50ea3*4 +0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x50ea4*4 +0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x50ea5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50ea6*4 +0x02000000,0xc00); +reg_write( DDR_REG_BASE +0x50ea7*4 +0x02000000,0xb700); +reg_write( DDR_REG_BASE +0x50ea8*4 +0x02000000,0xb36); +reg_write( DDR_REG_BASE +0x50ea9*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50eaa*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x50eab*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x50eac*4 +0x02000000,0xb2e); +reg_write( DDR_REG_BASE +0x50ead*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50eae*4 +0x02000000,0xb7c0); +reg_write( DDR_REG_BASE +0x50eaf*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50eb0*4 +0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x50eb1*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50eb2*4 +0x02000000,0x1c8); +reg_write( DDR_REG_BASE +0x50eb3*4 +0x02000000,0xb7a0); +reg_write( DDR_REG_BASE +0x50eb4*4 +0x02000000,0xb8c9); +reg_write( DDR_REG_BASE +0x50eb5*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50eb6*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50eb7*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50eb8*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50eb9*4 +0x02000000,0xc1a7); +reg_write( DDR_REG_BASE +0x50eba*4 +0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x50ebb*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50ebc*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50ebd*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50ebe*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50ebf*4 +0x02000000,0xc144); +reg_write( DDR_REG_BASE +0x50ec0*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50ec1*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x50ec2*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50ec3*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50ec4*4 +0x02000000,0x7d8); +reg_write( DDR_REG_BASE +0x50ec5*4 +0x02000000,0x8020); +reg_write( DDR_REG_BASE +0x50ec6*4 +0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x50ec7*4 +0x02000000,0xa92); +reg_write( DDR_REG_BASE +0x50ec8*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50ec9*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50eca*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50ecb*4 +0x02000000,0xc6a); +reg_write( DDR_REG_BASE +0x50ecc*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50ecd*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x50ece*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x50ecf*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x50ed0*4 +0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x50ed1*4 +0x02000000,0x37c0); +reg_write( DDR_REG_BASE +0x50ed2*4 +0x02000000,0xe805); +reg_write( DDR_REG_BASE +0x50ed3*4 +0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x50ed4*4 +0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x50ed5*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x50ed6*4 +0x02000000,0x7dbb); +reg_write( DDR_REG_BASE +0x50ed7*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x50ed8*4 +0x02000000,0x2553); +reg_write( DDR_REG_BASE +0x50ed9*4 +0x02000000,0x1040); +reg_write( DDR_REG_BASE +0x50eda*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x50edb*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x50edc*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50edd*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50ede*4 +0x02000000,0xda09); +reg_write( DDR_REG_BASE +0x50edf*4 +0x02000000,0xdbff); +reg_write( DDR_REG_BASE +0x50ee0*4 +0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x50ee1*4 +0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x50ee2*4 +0x02000000,0xd12); +reg_write( DDR_REG_BASE +0x50ee3*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50ee4*4 +0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x50ee5*4 +0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x50ee6*4 +0x02000000,0x110d); +reg_write( DDR_REG_BASE +0x50ee7*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50ee8*4 +0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x50ee9*4 +0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x50eea*4 +0x02000000,0x250f); +reg_write( DDR_REG_BASE +0x50eeb*4 +0x02000000,0x16c0); +reg_write( DDR_REG_BASE +0x50eec*4 +0x02000000,0x7d0f); +reg_write( DDR_REG_BASE +0x50eed*4 +0x02000000,0xd840); +reg_write( DDR_REG_BASE +0x50eee*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50eef*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50ef0*4 +0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x50ef1*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50ef2*4 +0x02000000,0xcf2); +reg_write( DDR_REG_BASE +0x50ef3*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50ef4*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x50ef5*4 +0x02000000,0x35c1); +reg_write( DDR_REG_BASE +0x50ef6*4 +0x02000000,0xd84b); +reg_write( DDR_REG_BASE +0x50ef7*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50ef8*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50ef9*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x50efa*4 +0x02000000,0xda17); +reg_write( DDR_REG_BASE +0x50efb*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x50efc*4 +0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x50efd*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50efe*4 +0x02000000,0xcda); +reg_write( DDR_REG_BASE +0x50eff*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50f00*4 +0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x50f01*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50f02*4 +0x02000000,0xc92); +reg_write( DDR_REG_BASE +0x50f03*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50f04*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x50f05*4 +0x02000000,0xc52); +reg_write( DDR_REG_BASE +0x50f06*4 +0x02000000,0x1c0); +reg_write( DDR_REG_BASE +0x50f07*4 +0x02000000,0xa7a); +reg_write( DDR_REG_BASE +0x50f08*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50f09*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x50f0a*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x50f0b*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50f0c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50f0d*4 +0x02000000,0x9c40); +reg_write( DDR_REG_BASE +0x50f0e*4 +0x02000000,0xac2); +reg_write( DDR_REG_BASE +0x50f0f*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50f10*4 +0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x50f11*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50f12*4 +0x02000000,0xbda); +reg_write( DDR_REG_BASE +0x50f13*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50f14*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x50f15*4 +0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x50f16*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50f17*4 +0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x50f18*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50f19*4 +0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x50f1a*4 +0x02000000,0xda0d); +reg_write( DDR_REG_BASE +0x50f1b*4 +0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x50f1c*4 +0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x50f1d*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50f1e*4 +0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x50f1f*4 +0x02000000,0xc9a); +reg_write( DDR_REG_BASE +0x50f20*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50f21*4 +0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x50f22*4 +0x02000000,0x2756); +reg_write( DDR_REG_BASE +0x50f23*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x50f24*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50f25*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50f26*4 +0x02000000,0xd988); +reg_write( DDR_REG_BASE +0x50f27*4 +0x02000000,0xda0d); +reg_write( DDR_REG_BASE +0x50f28*4 +0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x50f29*4 +0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x50f2a*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50f2b*4 +0x02000000,0xc82); +reg_write( DDR_REG_BASE +0x50f2c*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50f2d*4 +0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x50f2e*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50f2f*4 +0x02000000,0xc3a); +reg_write( DDR_REG_BASE +0x50f30*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50f31*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x50f32*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50f33*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50f34*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x50f35*4 +0x02000000,0x8ea0); +reg_write( DDR_REG_BASE +0x50f36*4 +0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x50f37*4 +0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x50f38*4 +0x02000000,0xb62); +reg_write( DDR_REG_BASE +0x50f39*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50f3a*4 +0x02000000,0x41e1); +reg_write( DDR_REG_BASE +0x50f3b*4 +0x02000000,0xe809); +reg_write( DDR_REG_BASE +0x50f3c*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x50f3d*4 +0x02000000,0x9c6); +reg_write( DDR_REG_BASE +0x50f3e*4 +0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x50f3f*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50f40*4 +0x02000000,0xc104); +reg_write( DDR_REG_BASE +0x50f41*4 +0x02000000,0x79b4); +reg_write( DDR_REG_BASE +0x50f42*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x50f43*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x50f44*4 +0x02000000,0x8e41); +reg_write( DDR_REG_BASE +0x50f45*4 +0x02000000,0xae7); +reg_write( DDR_REG_BASE +0x50f46*4 +0x02000000,0x8365); +reg_write( DDR_REG_BASE +0x50f47*4 +0x02000000,0x7faf); +reg_write( DDR_REG_BASE +0x50f48*4 +0x02000000,0x8ee0); +reg_write( DDR_REG_BASE +0x50f49*4 +0x02000000,0xf03c); +reg_write( DDR_REG_BASE +0x50f4a*4 +0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x50f4b*4 +0x02000000,0xb3e); +reg_write( DDR_REG_BASE +0x50f4c*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50f4d*4 +0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x50f4e*4 +0x02000000,0xe834); +reg_write( DDR_REG_BASE +0x50f4f*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50f50*4 +0x02000000,0x99e); +reg_write( DDR_REG_BASE +0x50f51*4 +0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x50f52*4 +0x02000000,0xd910); +reg_write( DDR_REG_BASE +0x50f53*4 +0x02000000,0xc504); +reg_write( DDR_REG_BASE +0x50f54*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x50f55*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50f56*4 +0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x50f57*4 +0x02000000,0x7df4); +reg_write( DDR_REG_BASE +0x50f58*4 +0x02000000,0x9520); +reg_write( DDR_REG_BASE +0x50f59*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50f5a*4 +0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x50f5b*4 +0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x50f5c*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50f5d*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50f5e*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50f5f*4 +0x02000000,0xa96); +reg_write( DDR_REG_BASE +0x50f60*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x50f61*4 +0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x50f62*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50f63*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50f64*4 +0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x50f65*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50f66*4 +0x02000000,0x6); +reg_write( DDR_REG_BASE +0x50f67*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x50f68*4 +0x02000000,0x81c3); +reg_write( DDR_REG_BASE +0x50f69*4 +0x02000000,0xf706); +reg_write( DDR_REG_BASE +0x50f6a*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x50f6b*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50f6c*4 +0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x50f6d*4 +0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x50f6e*4 +0x02000000,0x9500); +reg_write( DDR_REG_BASE +0x50f6f*4 +0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x50f70*4 +0x02000000,0x95); +reg_write( DDR_REG_BASE +0x50f71*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50f72*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50f73*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x50f74*4 +0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x50f75*4 +0x02000000,0x2e05); +reg_write( DDR_REG_BASE +0x50f76*4 +0x02000000,0x7000); +reg_write( DDR_REG_BASE +0x50f77*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50f78*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50f79*4 +0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x50f7a*4 +0x02000000,0x7b10); +reg_write( DDR_REG_BASE +0x50f7b*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x50f7c*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50f7d*4 +0x02000000,0xe1); +reg_write( DDR_REG_BASE +0x50f7e*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x50f7f*4 +0x02000000,0xfc2); +reg_write( DDR_REG_BASE +0x50f80*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50f81*4 +0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x50f82*4 +0x02000000,0x8e41); +reg_write( DDR_REG_BASE +0x50f83*4 +0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x50f84*4 +0x02000000,0xa8d); +reg_write( DDR_REG_BASE +0x50f85*4 +0x02000000,0x83e5); +reg_write( DDR_REG_BASE +0x50f86*4 +0x02000000,0x7def); +reg_write( DDR_REG_BASE +0x50f87*4 +0x02000000,0x8ea0); +reg_write( DDR_REG_BASE +0x50f88*4 +0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x50f89*4 +0x02000000,0xac2); +reg_write( DDR_REG_BASE +0x50f8a*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50f8b*4 +0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x50f8c*4 +0x02000000,0xe88a); +reg_write( DDR_REG_BASE +0x50f8d*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x50f8e*4 +0x02000000,0xd0b); +reg_write( DDR_REG_BASE +0x50f8f*4 +0x02000000,0x103f); +reg_write( DDR_REG_BASE +0x50f90*4 +0x02000000,0x78b4); +reg_write( DDR_REG_BASE +0x50f91*4 +0x02000000,0x9021); +reg_write( DDR_REG_BASE +0x50f92*4 +0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x50f93*4 +0x02000000,0x10fe); +reg_write( DDR_REG_BASE +0x50f94*4 +0x02000000,0x8101); +reg_write( DDR_REG_BASE +0x50f95*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x50f96*4 +0x02000000,0x8e41); +reg_write( DDR_REG_BASE +0x50f97*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x50f98*4 +0x02000000,0xae3); +reg_write( DDR_REG_BASE +0x50f99*4 +0x02000000,0x8365); +reg_write( DDR_REG_BASE +0x50f9a*4 +0x02000000,0x79af); +reg_write( DDR_REG_BASE +0x50f9b*4 +0x02000000,0x8e60); +reg_write( DDR_REG_BASE +0x50f9c*4 +0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x50f9d*4 +0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x50f9e*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50f9f*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50fa0*4 +0x02000000,0x15c); +reg_write( DDR_REG_BASE +0x50fa1*4 +0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x50fa2*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x50fa3*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50fa4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50fa5*4 +0x02000000,0x20c0); +reg_write( DDR_REG_BASE +0x50fa6*4 +0x02000000,0xa2); +reg_write( DDR_REG_BASE +0x50fa7*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x50fa8*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x50fa9*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50faa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50fab*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x50fac*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x50fad*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x50fae*4 +0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x50faf*4 +0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x50fb0*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x50fb1*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x50fb2*4 +0x02000000,0xad7); +reg_write( DDR_REG_BASE +0x50fb3*4 +0x02000000,0x80e5); +reg_write( DDR_REG_BASE +0x50fb4*4 +0x02000000,0x7077); +reg_write( DDR_REG_BASE +0x50fb5*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50fb6*4 +0x02000000,0xa92); +reg_write( DDR_REG_BASE +0x50fb7*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50fb8*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x50fb9*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x50fba*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50fbb*4 +0x02000000,0xda0a); +reg_write( DDR_REG_BASE +0x50fbc*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x50fbd*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50fbe*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x50fbf*4 +0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x50fc0*4 +0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x50fc1*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x50fc2*4 +0x02000000,0xb52); +reg_write( DDR_REG_BASE +0x50fc3*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50fc4*4 +0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x50fc5*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50fc6*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50fc7*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x50fc8*4 +0x02000000,0x766c); +reg_write( DDR_REG_BASE +0x50fc9*4 +0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x50fca*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x50fcb*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50fcc*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x50fcd*4 +0x02000000,0xb3e); +reg_write( DDR_REG_BASE +0x50fce*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50fcf*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x50fd0*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x50fd1*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50fd2*4 +0x02000000,0xda0e); +reg_write( DDR_REG_BASE +0x50fd3*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x50fd4*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50fd5*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x50fd6*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x50fd7*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x50fd8*4 +0x02000000,0xb26); +reg_write( DDR_REG_BASE +0x50fd9*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50fda*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x50fdb*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50fdc*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x50fdd*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x50fde*4 +0x02000000,0x766c); +reg_write( DDR_REG_BASE +0x50fdf*4 +0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x50fe0*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50fe1*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x50fe2*4 +0x02000000,0xb12); +reg_write( DDR_REG_BASE +0x50fe3*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50fe4*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x50fe5*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50fe6*4 +0x02000000,0xaca); +reg_write( DDR_REG_BASE +0x50fe7*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50fe8*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x50fe9*4 +0x02000000,0xa8a); +reg_write( DDR_REG_BASE +0x50fea*4 +0x02000000,0x1c0); +reg_write( DDR_REG_BASE +0x50feb*4 +0x02000000,0xc0a7); +reg_write( DDR_REG_BASE +0x50fec*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50fed*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50fee*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50fef*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50ff0*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x50ff1*4 +0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x50ff2*4 +0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x50ff3*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x50ff4*4 +0x02000000,0xd06); +reg_write( DDR_REG_BASE +0x50ff5*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50ff6*4 +0x02000000,0x4160); +reg_write( DDR_REG_BASE +0x50ff7*4 +0x02000000,0xe8b8); +reg_write( DDR_REG_BASE +0x50ff8*4 +0x02000000,0x246f); +reg_write( DDR_REG_BASE +0x50ff9*4 +0x02000000,0x1dc3); +reg_write( DDR_REG_BASE +0x50ffa*4 +0x02000000,0x8c20); +reg_write( DDR_REG_BASE +0x50ffb*4 +0x02000000,0x969); +reg_write( DDR_REG_BASE +0x50ffc*4 +0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x50ffd*4 +0x02000000,0x142f); +reg_write( DDR_REG_BASE +0x50ffe*4 +0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x50fff*4 +0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x51000*4 +0x02000000,0x1c81); +reg_write( DDR_REG_BASE +0x51001*4 +0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x51002*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x51003*4 +0x02000000,0x640); +reg_write( DDR_REG_BASE +0x51004*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51005*4 +0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x51006*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51007*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51008*4 +0x02000000,0x687); +reg_write( DDR_REG_BASE +0x51009*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5100a*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5100b*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5100c*4 +0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x5100d*4 +0x02000000,0xb9c2); +reg_write( DDR_REG_BASE +0x5100e*4 +0x02000000,0xd8f0); +reg_write( DDR_REG_BASE +0x5100f*4 +0x02000000,0x2805); +reg_write( DDR_REG_BASE +0x51010*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x51011*4 +0x02000000,0xeb05); +reg_write( DDR_REG_BASE +0x51012*4 +0x02000000,0x143c); +reg_write( DDR_REG_BASE +0x51013*4 +0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x51014*4 +0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x51015*4 +0x02000000,0x8c09); +reg_write( DDR_REG_BASE +0x51016*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51017*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51018*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51019*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5101a*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x5101b*4 +0x02000000,0x7b2f); +reg_write( DDR_REG_BASE +0x5101c*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x5101d*4 +0x02000000,0x61); +reg_write( DDR_REG_BASE +0x5101e*4 +0x02000000,0xb1b); +reg_write( DDR_REG_BASE +0x5101f*4 +0x02000000,0x24); +reg_write( DDR_REG_BASE +0x51020*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51021*4 +0x02000000,0x404); +reg_write( DDR_REG_BASE +0x51022*4 +0x02000000,0x2b05); +reg_write( DDR_REG_BASE +0x51023*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51024*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x51025*4 +0x02000000,0xa0f); +reg_write( DDR_REG_BASE +0x51026*4 +0x02000000,0x782c); +reg_write( DDR_REG_BASE +0x51027*4 +0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x51028*4 +0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x51029*4 +0x02000000,0x2805); +reg_write( DDR_REG_BASE +0x5102a*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x5102b*4 +0x02000000,0xf96); +reg_write( DDR_REG_BASE +0x5102c*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5102d*4 +0x02000000,0x7830); +reg_write( DDR_REG_BASE +0x5102e*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x5102f*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51030*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51031*4 +0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x51032*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51033*4 +0x02000000,0x22); +reg_write( DDR_REG_BASE +0x51034*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51035*4 +0x02000000,0x7de0); +reg_write( DDR_REG_BASE +0x51036*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51037*4 +0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x51038*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51039*4 +0x02000000,0x8); +reg_write( DDR_REG_BASE +0x5103a*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5103b*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5103c*4 +0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x5103d*4 +0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x5103e*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5103f*4 +0x02000000,0x7ca); +reg_write( DDR_REG_BASE +0x51040*4 +0x02000000,0x8b00); +reg_write( DDR_REG_BASE +0x51041*4 +0x02000000,0xdea); +reg_write( DDR_REG_BASE +0x51042*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51043*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51044*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51045*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51046*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51047*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51048*4 +0x02000000,0x8b82); +reg_write( DDR_REG_BASE +0x51049*4 +0x02000000,0x8b41); +reg_write( DDR_REG_BASE +0x5104a*4 +0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x5104b*4 +0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x5104c*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5104d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5104e*4 +0x02000000,0x776c); +reg_write( DDR_REG_BASE +0x5104f*4 +0x02000000,0xf01c); +reg_write( DDR_REG_BASE +0x51050*4 +0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x51051*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51052*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51053*4 +0x02000000,0x800); +reg_write( DDR_REG_BASE +0x51054*4 +0x02000000,0x2104); +reg_write( DDR_REG_BASE +0x51055*4 +0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x51056*4 +0x02000000,0x37fe); +reg_write( DDR_REG_BASE +0x51057*4 +0x02000000,0xf000); +reg_write( DDR_REG_BASE +0x51058*4 +0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x51059*4 +0x02000000,0x801); +reg_write( DDR_REG_BASE +0x5105a*4 +0x02000000,0x79a5); +reg_write( DDR_REG_BASE +0x5105b*4 +0x02000000,0x79c5); +reg_write( DDR_REG_BASE +0x5105c*4 +0x02000000,0x6ac1); +reg_write( DDR_REG_BASE +0x5105d*4 +0x02000000,0x229a); +reg_write( DDR_REG_BASE +0x5105e*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5105f*4 +0x02000000,0x2284); +reg_write( DDR_REG_BASE +0x51060*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51061*4 +0x02000000,0x7a25); +reg_write( DDR_REG_BASE +0x51062*4 +0x02000000,0x795b); +reg_write( DDR_REG_BASE +0x51063*4 +0x02000000,0xb991); +reg_write( DDR_REG_BASE +0x51064*4 +0x02000000,0xb99c); +reg_write( DDR_REG_BASE +0x51065*4 +0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x51066*4 +0x02000000,0x9120); +reg_write( DDR_REG_BASE +0x51067*4 +0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x51068*4 +0x02000000,0x2108); +reg_write( DDR_REG_BASE +0x51069*4 +0x02000000,0xc3); +reg_write( DDR_REG_BASE +0x5106a*4 +0x02000000,0xccd); +reg_write( DDR_REG_BASE +0x5106b*4 +0x02000000,0x9085); +reg_write( DDR_REG_BASE +0x5106c*4 +0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x5106d*4 +0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x5106e*4 +0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x5106f*4 +0x02000000,0x901); +reg_write( DDR_REG_BASE +0x51070*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x51071*4 +0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x51072*4 +0x02000000,0x796f); +reg_write( DDR_REG_BASE +0x51073*4 +0x02000000,0x2179); +reg_write( DDR_REG_BASE +0x51074*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51075*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51076*4 +0x02000000,0x7204); +reg_write( DDR_REG_BASE +0x51077*4 +0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x51078*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51079*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5107a*4 +0x02000000,0x7d8); +reg_write( DDR_REG_BASE +0x5107b*4 +0x02000000,0x7bd); +reg_write( DDR_REG_BASE +0x5107c*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5107d*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5107e*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5107f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51080*4 +0x02000000,0x7d8); +reg_write( DDR_REG_BASE +0x51081*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x51082*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51083*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51084*4 +0x02000000,0x8020); +reg_write( DDR_REG_BASE +0x51085*4 +0x02000000,0x8a00); +reg_write( DDR_REG_BASE +0x51086*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x51087*4 +0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x51088*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51089*4 +0x02000000,0x8a21); +reg_write( DDR_REG_BASE +0x5108a*4 +0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x5108b*4 +0x02000000,0x641); +reg_write( DDR_REG_BASE +0x5108c*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x5108d*4 +0x02000000,0x8842); +reg_write( DDR_REG_BASE +0x5108e*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5108f*4 +0x02000000,0x75); +reg_write( DDR_REG_BASE +0x51090*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51091*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51092*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51093*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51094*4 +0x02000000,0x7cb); +reg_write( DDR_REG_BASE +0x51095*4 +0x02000000,0x8881); +reg_write( DDR_REG_BASE +0x51096*4 +0x02000000,0x8860); +reg_write( DDR_REG_BASE +0x51097*4 +0x02000000,0xf022); +reg_write( DDR_REG_BASE +0x51098*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x51099*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5109a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5109b*4 +0x02000000,0x800); +reg_write( DDR_REG_BASE +0x5109c*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x5109d*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x5109e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5109f*4 +0x02000000,0x800); +reg_write( DDR_REG_BASE +0x510a0*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x510a1*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x510a2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x510a3*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x510a4*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x510a5*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x510a6*4 +0x02000000,0x6ffd); +reg_write( DDR_REG_BASE +0x510a7*4 +0x02000000,0xe000); +reg_write( DDR_REG_BASE +0x510a8*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x510a9*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x510aa*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x510ab*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x510ac*4 +0x02000000,0x64); +reg_write( DDR_REG_BASE +0x510ad*4 +0x02000000,0x9220); +reg_write( DDR_REG_BASE +0x510ae*4 +0x02000000,0x4928); +reg_write( DDR_REG_BASE +0x510af*4 +0x02000000,0x208b); +reg_write( DDR_REG_BASE +0x510b0*4 +0x02000000,0x880f); +reg_write( DDR_REG_BASE +0x510b1*4 +0x02000000,0xf206); +reg_write( DDR_REG_BASE +0x510b2*4 +0x02000000,0x2142); +reg_write( DDR_REG_BASE +0x510b3*4 +0x02000000,0x400); +reg_write( DDR_REG_BASE +0x510b4*4 +0x02000000,0x2080); +reg_write( DDR_REG_BASE +0x510b5*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x510b6*4 +0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x510b7*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x510b8*4 +0x02000000,0xcc1); +reg_write( DDR_REG_BASE +0x510b9*4 +0x02000000,0x90c5); +reg_write( DDR_REG_BASE +0x510ba*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x510bb*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x510bc*4 +0x02000000,0xc0e4); +reg_write( DDR_REG_BASE +0x510bd*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x510be*4 +0x02000000,0x259a); +reg_write( DDR_REG_BASE +0x510bf*4 +0x02000000,0x1008); +reg_write( DDR_REG_BASE +0x510c0*4 +0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x510c1*4 +0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x510c2*4 +0x02000000,0x48); +reg_write( DDR_REG_BASE +0x510c3*4 +0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x510c4*4 +0x02000000,0x130e); +reg_write( DDR_REG_BASE +0x510c5*4 +0x02000000,0xb620); +reg_write( DDR_REG_BASE +0x510c6*4 +0x02000000,0x6c22); +reg_write( DDR_REG_BASE +0x510c7*4 +0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x510c8*4 +0x02000000,0x104c); +reg_write( DDR_REG_BASE +0x510c9*4 +0x02000000,0x7224); +reg_write( DDR_REG_BASE +0x510ca*4 +0x02000000,0xb440); +reg_write( DDR_REG_BASE +0x510cb*4 +0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x510cc*4 +0x02000000,0x1042); +reg_write( DDR_REG_BASE +0x510cd*4 +0x02000000,0xb260); +reg_write( DDR_REG_BASE +0x510ce*4 +0x02000000,0x6962); +reg_write( DDR_REG_BASE +0x510cf*4 +0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x510d0*4 +0x02000000,0x7d65); +reg_write( DDR_REG_BASE +0x510d1*4 +0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x510d2*4 +0x02000000,0x3f1); +reg_write( DDR_REG_BASE +0x510d3*4 +0x02000000,0xb520); +reg_write( DDR_REG_BASE +0x510d4*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x510d5*4 +0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x510d6*4 +0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x510d7*4 +0x02000000,0x137c); +reg_write( DDR_REG_BASE +0x510d8*4 +0x02000000,0x101); +reg_write( DDR_REG_BASE +0x510d9*4 +0x02000000,0x210f); +reg_write( DDR_REG_BASE +0x510da*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x510db*4 +0x02000000,0x1b7c); +reg_write( DDR_REG_BASE +0x510dc*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x510dd*4 +0x02000000,0xc4c4); +reg_write( DDR_REG_BASE +0x510de*4 +0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x510df*4 +0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x510e0*4 +0x02000000,0xc2); +reg_write( DDR_REG_BASE +0x510e1*4 +0x02000000,0x1c02); +reg_write( DDR_REG_BASE +0x510e2*4 +0x02000000,0x1014); +reg_write( DDR_REG_BASE +0x510e3*4 +0x02000000,0xb420); +reg_write( DDR_REG_BASE +0x510e4*4 +0x02000000,0xb441); +reg_write( DDR_REG_BASE +0x510e5*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x510e6*4 +0x02000000,0xb462); +reg_write( DDR_REG_BASE +0x510e7*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x510e8*4 +0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x510e9*4 +0x02000000,0x4320); +reg_write( DDR_REG_BASE +0x510ea*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x510eb*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x510ec*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x510ed*4 +0x02000000,0x7d0); +reg_write( DDR_REG_BASE +0x510ee*4 +0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x510ef*4 +0x02000000,0xf06); +reg_write( DDR_REG_BASE +0x510f0*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x510f1*4 +0x02000000,0x203c); +reg_write( DDR_REG_BASE +0x510f2*4 +0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x510f3*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x510f4*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x510f5*4 +0x02000000,0xf427); +reg_write( DDR_REG_BASE +0x510f6*4 +0x02000000,0xde25); +reg_write( DDR_REG_BASE +0x510f7*4 +0x02000000,0xbe9f); +reg_write( DDR_REG_BASE +0x510f8*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x510f9*4 +0x02000000,0xf01f); +reg_write( DDR_REG_BASE +0x510fa*4 +0x02000000,0xec04); +reg_write( DDR_REG_BASE +0x510fb*4 +0x02000000,0x1633); +reg_write( DDR_REG_BASE +0x510fc*4 +0x02000000,0x1082); +reg_write( DDR_REG_BASE +0x510fd*4 +0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x510fe*4 +0x02000000,0x8e40); +reg_write( DDR_REG_BASE +0x510ff*4 +0x02000000,0xa31); +reg_write( DDR_REG_BASE +0x51100*4 +0x02000000,0x6e); +reg_write( DDR_REG_BASE +0x51101*4 +0x02000000,0x2114); +reg_write( DDR_REG_BASE +0x51102*4 +0x02000000,0x302); +reg_write( DDR_REG_BASE +0x51103*4 +0x02000000,0x2232); +reg_write( DDR_REG_BASE +0x51104*4 +0x02000000,0xf8b); +reg_write( DDR_REG_BASE +0x51105*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51106*4 +0x02000000,0x784); +reg_write( DDR_REG_BASE +0x51107*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51108*4 +0x02000000,0xa1d); +reg_write( DDR_REG_BASE +0x51109*4 +0x02000000,0x2c5); +reg_write( DDR_REG_BASE +0x5110a*4 +0x02000000,0x245a); +reg_write( DDR_REG_BASE +0x5110b*4 +0x02000000,0x140d); +reg_write( DDR_REG_BASE +0x5110c*4 +0x02000000,0x7d36); +reg_write( DDR_REG_BASE +0x5110d*4 +0x02000000,0x655d); +reg_write( DDR_REG_BASE +0x5110e*4 +0x02000000,0x2532); +reg_write( DDR_REG_BASE +0x5110f*4 +0x02000000,0x1f8d); +reg_write( DDR_REG_BASE +0x51110*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51111*4 +0x02000000,0x7a8); +reg_write( DDR_REG_BASE +0x51112*4 +0x02000000,0xded); +reg_write( DDR_REG_BASE +0x51113*4 +0x02000000,0x90e1); +reg_write( DDR_REG_BASE +0x51114*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x51115*4 +0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x51116*4 +0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x51117*4 +0x02000000,0xcc9); +reg_write( DDR_REG_BASE +0x51118*4 +0x02000000,0x9094); +reg_write( DDR_REG_BASE +0x51119*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5111a*4 +0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x5111b*4 +0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x5111c*4 +0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x5111d*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5111e*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5111f*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51120*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51121*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51122*4 +0x02000000,0xe064); +reg_write( DDR_REG_BASE +0x51123*4 +0x02000000,0x2145); +reg_write( DDR_REG_BASE +0x51124*4 +0x02000000,0x7c1); +reg_write( DDR_REG_BASE +0x51125*4 +0x02000000,0x779); +reg_write( DDR_REG_BASE +0x51126*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x51127*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51128*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51129*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5112a*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5112b*4 +0x02000000,0xc1a3); +reg_write( DDR_REG_BASE +0x5112c*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5112d*4 +0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x5112e*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x5112f*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51130*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x51131*4 +0x02000000,0xafd); +reg_write( DDR_REG_BASE +0x51132*4 +0x02000000,0x8674); +reg_write( DDR_REG_BASE +0x51133*4 +0x02000000,0x2014); +reg_write( DDR_REG_BASE +0x51134*4 +0x02000000,0x81); +reg_write( DDR_REG_BASE +0x51135*4 +0x02000000,0xdb32); +reg_write( DDR_REG_BASE +0x51136*4 +0x02000000,0xbb9f); +reg_write( DDR_REG_BASE +0x51137*4 +0x02000000,0x8b20); +reg_write( DDR_REG_BASE +0x51138*4 +0x02000000,0xa821); +reg_write( DDR_REG_BASE +0x51139*4 +0x02000000,0x6b21); +reg_write( DDR_REG_BASE +0x5113a*4 +0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x5113b*4 +0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x5113c*4 +0x02000000,0xa822); +reg_write( DDR_REG_BASE +0x5113d*4 +0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x5113e*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x5113f*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51140*4 +0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x51141*4 +0x02000000,0xa823); +reg_write( DDR_REG_BASE +0x51142*4 +0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x51143*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x51144*4 +0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x51145*4 +0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x51146*4 +0x02000000,0xa824); +reg_write( DDR_REG_BASE +0x51147*4 +0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x51148*4 +0x02000000,0x6941); +reg_write( DDR_REG_BASE +0x51149*4 +0x02000000,0x8a20); +reg_write( DDR_REG_BASE +0x5114a*4 +0x02000000,0x2240); +reg_write( DDR_REG_BASE +0x5114b*4 +0x02000000,0x5f); +reg_write( DDR_REG_BASE +0x5114c*4 +0x02000000,0x2740); +reg_write( DDR_REG_BASE +0x5114d*4 +0x02000000,0x304c); +reg_write( DDR_REG_BASE +0x5114e*4 +0x02000000,0xa82b); +reg_write( DDR_REG_BASE +0x5114f*4 +0x02000000,0x1700); +reg_write( DDR_REG_BASE +0x51150*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x51151*4 +0x02000000,0x6ca1); +reg_write( DDR_REG_BASE +0x51152*4 +0x02000000,0x6dc1); +reg_write( DDR_REG_BASE +0x51153*4 +0x02000000,0xa82c); +reg_write( DDR_REG_BASE +0x51154*4 +0x02000000,0x8c20); +reg_write( DDR_REG_BASE +0x51155*4 +0x02000000,0x6ee1); +reg_write( DDR_REG_BASE +0x51156*4 +0x02000000,0x4358); +reg_write( DDR_REG_BASE +0x51157*4 +0x02000000,0xa82d); +reg_write( DDR_REG_BASE +0x51158*4 +0x02000000,0x8d20); +reg_write( DDR_REG_BASE +0x51159*4 +0x02000000,0xa82e); +reg_write( DDR_REG_BASE +0x5115a*4 +0x02000000,0x8e20); +reg_write( DDR_REG_BASE +0x5115b*4 +0x02000000,0xa830); +reg_write( DDR_REG_BASE +0x5115c*4 +0x02000000,0x8f20); +reg_write( DDR_REG_BASE +0x5115d*4 +0x02000000,0xa831); +reg_write( DDR_REG_BASE +0x5115e*4 +0x02000000,0x8f21); +reg_write( DDR_REG_BASE +0x5115f*4 +0x02000000,0xa836); +reg_write( DDR_REG_BASE +0x51160*4 +0x02000000,0x8f22); +reg_write( DDR_REG_BASE +0x51161*4 +0x02000000,0xa838); +reg_write( DDR_REG_BASE +0x51162*4 +0x02000000,0x13e6); +reg_write( DDR_REG_BASE +0x51163*4 +0x02000000,0x8081); +reg_write( DDR_REG_BASE +0x51164*4 +0x02000000,0xe930); +reg_write( DDR_REG_BASE +0x51165*4 +0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x51166*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x51167*4 +0x02000000,0xf02a); +reg_write( DDR_REG_BASE +0x51168*4 +0x02000000,0x265a); +reg_write( DDR_REG_BASE +0x51169*4 +0x02000000,0x3c82); +reg_write( DDR_REG_BASE +0x5116a*4 +0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x5116b*4 +0x02000000,0x1641); +reg_write( DDR_REG_BASE +0x5116c*4 +0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x5116d*4 +0x02000000,0x621a); +reg_write( DDR_REG_BASE +0x5116e*4 +0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x5116f*4 +0x02000000,0x8b40); +reg_write( DDR_REG_BASE +0x51170*4 +0x02000000,0xa941); +reg_write( DDR_REG_BASE +0x51171*4 +0x02000000,0xc200); +reg_write( DDR_REG_BASE +0x51172*4 +0x02000000,0x8a40); +reg_write( DDR_REG_BASE +0x51173*4 +0x02000000,0xa942); +reg_write( DDR_REG_BASE +0x51174*4 +0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x51175*4 +0x02000000,0x8a40); +reg_write( DDR_REG_BASE +0x51176*4 +0x02000000,0xa943); +reg_write( DDR_REG_BASE +0x51177*4 +0x02000000,0xc202); +reg_write( DDR_REG_BASE +0x51178*4 +0x02000000,0x8a40); +reg_write( DDR_REG_BASE +0x51179*4 +0x02000000,0xa944); +reg_write( DDR_REG_BASE +0x5117a*4 +0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x5117b*4 +0x02000000,0x3082); +reg_write( DDR_REG_BASE +0x5117c*4 +0x02000000,0xa94b); +reg_write( DDR_REG_BASE +0x5117d*4 +0x02000000,0x1700); +reg_write( DDR_REG_BASE +0x5117e*4 +0x02000000,0x3082); +reg_write( DDR_REG_BASE +0x5117f*4 +0x02000000,0xa94c); +reg_write( DDR_REG_BASE +0x51180*4 +0x02000000,0x8c40); +reg_write( DDR_REG_BASE +0x51181*4 +0x02000000,0xa94d); +reg_write( DDR_REG_BASE +0x51182*4 +0x02000000,0x8d40); +reg_write( DDR_REG_BASE +0x51183*4 +0x02000000,0xa94e); +reg_write( DDR_REG_BASE +0x51184*4 +0x02000000,0x8e40); +reg_write( DDR_REG_BASE +0x51185*4 +0x02000000,0xa950); +reg_write( DDR_REG_BASE +0x51186*4 +0x02000000,0x8f40); +reg_write( DDR_REG_BASE +0x51187*4 +0x02000000,0xa951); +reg_write( DDR_REG_BASE +0x51188*4 +0x02000000,0x8f41); +reg_write( DDR_REG_BASE +0x51189*4 +0x02000000,0xa956); +reg_write( DDR_REG_BASE +0x5118a*4 +0x02000000,0x8f42); +reg_write( DDR_REG_BASE +0x5118b*4 +0x02000000,0xa958); +reg_write( DDR_REG_BASE +0x5118c*4 +0x02000000,0xbb9); +reg_write( DDR_REG_BASE +0x5118d*4 +0x02000000,0x9094); +reg_write( DDR_REG_BASE +0x5118e*4 +0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x5118f*4 +0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x51190*4 +0x02000000,0xef9); +reg_write( DDR_REG_BASE +0x51191*4 +0x02000000,0xb0b4); +reg_write( DDR_REG_BASE +0x51192*4 +0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x51193*4 +0x02000000,0xf08d); +reg_write( DDR_REG_BASE +0x51194*4 +0x02000000,0xda3e); +reg_write( DDR_REG_BASE +0x51195*4 +0x02000000,0xba9f); +reg_write( DDR_REG_BASE +0x51196*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x51197*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x51198*4 +0x02000000,0xa83a); +reg_write( DDR_REG_BASE +0x51199*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x5119a*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x5119b*4 +0x02000000,0xa83b); +reg_write( DDR_REG_BASE +0x5119c*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x5119d*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x5119e*4 +0x02000000,0xa83c); +reg_write( DDR_REG_BASE +0x5119f*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511a0*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511a1*4 +0x02000000,0xa83d); +reg_write( DDR_REG_BASE +0x511a2*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511a3*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511a4*4 +0x02000000,0x1824); +reg_write( DDR_REG_BASE +0x511a5*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511a6*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511a7*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511a8*4 +0x02000000,0x1825); +reg_write( DDR_REG_BASE +0x511a9*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511aa*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511ab*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511ac*4 +0x02000000,0x1826); +reg_write( DDR_REG_BASE +0x511ad*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511ae*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511af*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511b0*4 +0x02000000,0x1827); +reg_write( DDR_REG_BASE +0x511b1*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511b2*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511b3*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511b4*4 +0x02000000,0x1829); +reg_write( DDR_REG_BASE +0x511b5*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511b6*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511b7*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511b8*4 +0x02000000,0x182a); +reg_write( DDR_REG_BASE +0x511b9*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511ba*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511bb*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511bc*4 +0x02000000,0x182f); +reg_write( DDR_REG_BASE +0x511bd*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511be*4 +0x02000000,0x121c); +reg_write( DDR_REG_BASE +0x511bf*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511c0*4 +0x02000000,0x1831); +reg_write( DDR_REG_BASE +0x511c1*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511c2*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511c3*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511c4*4 +0x02000000,0x1833); +reg_write( DDR_REG_BASE +0x511c5*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511c6*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511c7*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511c8*4 +0x02000000,0x1834); +reg_write( DDR_REG_BASE +0x511c9*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511ca*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511cb*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511cc*4 +0x02000000,0x1835); +reg_write( DDR_REG_BASE +0x511cd*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511ce*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511cf*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511d0*4 +0x02000000,0x1836); +reg_write( DDR_REG_BASE +0x511d1*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511d2*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511d3*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511d4*4 +0x02000000,0x183d); +reg_write( DDR_REG_BASE +0x511d5*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511d6*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511d7*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511d8*4 +0x02000000,0x183e); +reg_write( DDR_REG_BASE +0x511d9*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511da*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511db*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511dc*4 +0x02000000,0x183f); +reg_write( DDR_REG_BASE +0x511dd*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511de*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511df*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511e0*4 +0x02000000,0x1840); +reg_write( DDR_REG_BASE +0x511e1*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511e2*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511e3*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511e4*4 +0x02000000,0x1842); +reg_write( DDR_REG_BASE +0x511e5*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511e6*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511e7*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511e8*4 +0x02000000,0x1843); +reg_write( DDR_REG_BASE +0x511e9*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511ea*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511eb*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511ec*4 +0x02000000,0x1848); +reg_write( DDR_REG_BASE +0x511ed*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511ee*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511ef*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511f0*4 +0x02000000,0x184a); +reg_write( DDR_REG_BASE +0x511f1*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511f2*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511f3*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511f4*4 +0x02000000,0x184c); +reg_write( DDR_REG_BASE +0x511f5*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511f6*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511f7*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511f8*4 +0x02000000,0x184d); +reg_write( DDR_REG_BASE +0x511f9*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511fa*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511fb*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x511fc*4 +0x02000000,0x184e); +reg_write( DDR_REG_BASE +0x511fd*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x511fe*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x511ff*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x51200*4 +0x02000000,0x184f); +reg_write( DDR_REG_BASE +0x51201*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x51202*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x51203*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x51204*4 +0x02000000,0x1856); +reg_write( DDR_REG_BASE +0x51205*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x51206*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x51207*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x51208*4 +0x02000000,0x1857); +reg_write( DDR_REG_BASE +0x51209*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x5120a*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x5120b*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x5120c*4 +0x02000000,0x1858); +reg_write( DDR_REG_BASE +0x5120d*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x5120e*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x5120f*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x51210*4 +0x02000000,0x1859); +reg_write( DDR_REG_BASE +0x51211*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x51212*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x51213*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x51214*4 +0x02000000,0x185b); +reg_write( DDR_REG_BASE +0x51215*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x51216*4 +0x02000000,0x8a20); +reg_write( DDR_REG_BASE +0x51217*4 +0x02000000,0x185c); +reg_write( DDR_REG_BASE +0x51218*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x51219*4 +0x02000000,0x8a21); +reg_write( DDR_REG_BASE +0x5121a*4 +0x02000000,0x1861); +reg_write( DDR_REG_BASE +0x5121b*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x5121c*4 +0x02000000,0x8a22); +reg_write( DDR_REG_BASE +0x5121d*4 +0x02000000,0x1863); +reg_write( DDR_REG_BASE +0x5121e*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x5121f*4 +0x02000000,0xc0a3); +reg_write( DDR_REG_BASE +0x51220*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x51221*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x51222*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51223*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51224*4 +0x02000000,0xc3e4); +reg_write( DDR_REG_BASE +0x51225*4 +0x02000000,0xc1ab); +reg_write( DDR_REG_BASE +0x51226*4 +0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x51227*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51228*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51229*4 +0x02000000,0x650); +reg_write( DDR_REG_BASE +0x5122a*4 +0x02000000,0xc2e); +reg_write( DDR_REG_BASE +0x5122b*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5122c*4 +0x02000000,0xda2a); +reg_write( DDR_REG_BASE +0x5122d*4 +0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x5122e*4 +0x02000000,0x92e); +reg_write( DDR_REG_BASE +0x5122f*4 +0x02000000,0x2a0); +reg_write( DDR_REG_BASE +0x51230*4 +0x02000000,0xd92a); +reg_write( DDR_REG_BASE +0x51231*4 +0x02000000,0xdd25); +reg_write( DDR_REG_BASE +0x51232*4 +0x02000000,0xbd9f); +reg_write( DDR_REG_BASE +0x51233*4 +0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x51234*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51235*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51236*4 +0x02000000,0xe4); +reg_write( DDR_REG_BASE +0x51237*4 +0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x51238*4 +0x02000000,0x1533); +reg_write( DDR_REG_BASE +0x51239*4 +0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x5123a*4 +0x02000000,0xb601); +reg_write( DDR_REG_BASE +0x5123b*4 +0x02000000,0x15f4); +reg_write( DDR_REG_BASE +0x5123c*4 +0x02000000,0x9080); +reg_write( DDR_REG_BASE +0x5123d*4 +0x02000000,0xe888); +reg_write( DDR_REG_BASE +0x5123e*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5123f*4 +0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x51240*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51241*4 +0x02000000,0xe154); +reg_write( DDR_REG_BASE +0x51242*4 +0x02000000,0x1e42); +reg_write( DDR_REG_BASE +0x51243*4 +0x02000000,0x905d); +reg_write( DDR_REG_BASE +0x51244*4 +0x02000000,0xbda); +reg_write( DDR_REG_BASE +0x51245*4 +0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x51246*4 +0x02000000,0x2053); +reg_write( DDR_REG_BASE +0x51247*4 +0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x51248*4 +0x02000000,0x1a01); +reg_write( DDR_REG_BASE +0x51249*4 +0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x5124a*4 +0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x5124b*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x5124c*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x5124d*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x5124e*4 +0x02000000,0xb9c3); +reg_write( DDR_REG_BASE +0x5124f*4 +0x02000000,0x1a02); +reg_write( DDR_REG_BASE +0x51250*4 +0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x51251*4 +0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x51252*4 +0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x51253*4 +0x02000000,0x901); +reg_write( DDR_REG_BASE +0x51254*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x51255*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51256*4 +0x02000000,0xb8c1); +reg_write( DDR_REG_BASE +0x51257*4 +0x02000000,0xdea); +reg_write( DDR_REG_BASE +0x51258*4 +0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x51259*4 +0x02000000,0x1a06); +reg_write( DDR_REG_BASE +0x5125a*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x5125b*4 +0x02000000,0x9ce); +reg_write( DDR_REG_BASE +0x5125c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5125d*4 +0x02000000,0x8b2); +reg_write( DDR_REG_BASE +0x5125e*4 +0x02000000,0x1c0); +reg_write( DDR_REG_BASE +0x5125f*4 +0x02000000,0x164c); +reg_write( DDR_REG_BASE +0x51260*4 +0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x51261*4 +0x02000000,0x80d); +reg_write( DDR_REG_BASE +0x51262*4 +0x02000000,0x151); +reg_write( DDR_REG_BASE +0x51263*4 +0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x51264*4 +0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x51265*4 +0x02000000,0xb601); +reg_write( DDR_REG_BASE +0x51266*4 +0x02000000,0xc7c4); +reg_write( DDR_REG_BASE +0x51267*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51268*4 +0x02000000,0xc3e2); +reg_write( DDR_REG_BASE +0x51269*4 +0x02000000,0xc1bd); +reg_write( DDR_REG_BASE +0x5126a*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x5126b*4 +0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x5126c*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5126d*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5126e*4 +0x02000000,0x4ad); +reg_write( DDR_REG_BASE +0x5126f*4 +0x02000000,0xba6); +reg_write( DDR_REG_BASE +0x51270*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51271*4 +0x02000000,0xda72); +reg_write( DDR_REG_BASE +0x51272*4 +0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x51273*4 +0x02000000,0x8a6); +reg_write( DDR_REG_BASE +0x51274*4 +0x02000000,0x2a0); +reg_write( DDR_REG_BASE +0x51275*4 +0x02000000,0xd972); +reg_write( DDR_REG_BASE +0x51276*4 +0x02000000,0xed07); +reg_write( DDR_REG_BASE +0x51277*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x51278*4 +0x02000000,0xc07); +reg_write( DDR_REG_BASE +0x51279*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5127a*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x5127b*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5127c*4 +0x02000000,0xe8c4); +reg_write( DDR_REG_BASE +0x5127d*4 +0x02000000,0xc7c2); +reg_write( DDR_REG_BASE +0x5127e*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5127f*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51280*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51281*4 +0x02000000,0xc1a7); +reg_write( DDR_REG_BASE +0x51282*4 +0x02000000,0xbfa); +reg_write( DDR_REG_BASE +0x51283*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51284*4 +0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x51285*4 +0x02000000,0xb72); +reg_write( DDR_REG_BASE +0x51286*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51287*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x51288*4 +0x02000000,0xbe2); +reg_write( DDR_REG_BASE +0x51289*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5128a*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5128b*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x5128c*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5128d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5128e*4 +0x02000000,0x2710); +reg_write( DDR_REG_BASE +0x5128f*4 +0x02000000,0xbe2); +reg_write( DDR_REG_BASE +0x51290*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x51291*4 +0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x51292*4 +0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x51293*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51294*4 +0x02000000,0xcd6); +reg_write( DDR_REG_BASE +0x51295*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51296*4 +0x02000000,0xd91f); +reg_write( DDR_REG_BASE +0x51297*4 +0x02000000,0xca00); +reg_write( DDR_REG_BASE +0x51298*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51299*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x5129a*4 +0x02000000,0x7604); +reg_write( DDR_REG_BASE +0x5129b*4 +0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x5129c*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5129d*4 +0x02000000,0xb98e); +reg_write( DDR_REG_BASE +0x5129e*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5129f*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x512a0*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x512a1*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x512a2*4 +0x02000000,0xd92); +reg_write( DDR_REG_BASE +0x512a3*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512a4*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x512a5*4 +0x02000000,0x7bcf); +reg_write( DDR_REG_BASE +0x512a6*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x512a7*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x512a8*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x512a9*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x512aa*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x512ab*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x512ac*4 +0x02000000,0xd7e); +reg_write( DDR_REG_BASE +0x512ad*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512ae*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x512af*4 +0x02000000,0x71cd); +reg_write( DDR_REG_BASE +0x512b0*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x512b1*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x512b2*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x512b3*4 +0x02000000,0xdb7c); +reg_write( DDR_REG_BASE +0x512b4*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x512b5*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x512b6*4 +0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x512b7*4 +0x02000000,0xd6a); +reg_write( DDR_REG_BASE +0x512b8*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512b9*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x512ba*4 +0x02000000,0xfae); +reg_write( DDR_REG_BASE +0x512bb*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512bc*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x512bd*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x512be*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x512bf*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x512c0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x512c1*4 +0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x512c2*4 +0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x512c3*4 +0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x512c4*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x512c5*4 +0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x512c6*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x512c7*4 +0x02000000,0xd4a); +reg_write( DDR_REG_BASE +0x512c8*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512c9*4 +0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x512ca*4 +0x02000000,0xf838); +reg_write( DDR_REG_BASE +0x512cb*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x512cc*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x512cd*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x512ce*4 +0x02000000,0xd3a); +reg_write( DDR_REG_BASE +0x512cf*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512d0*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x512d1*4 +0x02000000,0xf835); +reg_write( DDR_REG_BASE +0x512d2*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x512d3*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x512d4*4 +0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x512d5*4 +0x02000000,0xd2e); +reg_write( DDR_REG_BASE +0x512d6*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512d7*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x512d8*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x512d9*4 +0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x512da*4 +0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x512db*4 +0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x512dc*4 +0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x512dd*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x512de*4 +0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x512df*4 +0x02000000,0xd1a); +reg_write( DDR_REG_BASE +0x512e0*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512e1*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x512e2*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x512e3*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x512e4*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x512e5*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x512e6*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x512e7*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x512e8*4 +0x02000000,0xe020); +reg_write( DDR_REG_BASE +0x512e9*4 +0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x512ea*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x512eb*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x512ec*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x512ed*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x512ee*4 +0x02000000,0xcfa); +reg_write( DDR_REG_BASE +0x512ef*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512f0*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x512f1*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x512f2*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x512f3*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x512f4*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x512f5*4 +0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x512f6*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x512f7*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x512f8*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x512f9*4 +0x02000000,0xce6); +reg_write( DDR_REG_BASE +0x512fa*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512fb*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x512fc*4 +0x02000000,0xc105); +reg_write( DDR_REG_BASE +0x512fd*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x512fe*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x512ff*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51300*4 +0x02000000,0x7914); +reg_write( DDR_REG_BASE +0x51301*4 +0x02000000,0x2154); +reg_write( DDR_REG_BASE +0x51302*4 +0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x51303*4 +0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x51304*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51305*4 +0x02000000,0x2054); +reg_write( DDR_REG_BASE +0x51306*4 +0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x51307*4 +0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x51308*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51309*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x5130a*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5130b*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5130c*4 +0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x5130d*4 +0x02000000,0xcbe); +reg_write( DDR_REG_BASE +0x5130e*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5130f*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51310*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51311*4 +0x02000000,0xb88e); +reg_write( DDR_REG_BASE +0x51312*4 +0x02000000,0x791b); +reg_write( DDR_REG_BASE +0x51313*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51314*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x51315*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x51316*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x51317*4 +0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x51318*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51319*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5131a*4 +0x02000000,0xca2); +reg_write( DDR_REG_BASE +0x5131b*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5131c*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5131d*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5131e*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5131f*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x51320*4 +0x02000000,0xdb40); +reg_write( DDR_REG_BASE +0x51321*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51322*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51323*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51324*4 +0x02000000,0xc8e); +reg_write( DDR_REG_BASE +0x51325*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51326*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51327*4 +0x02000000,0xeba); +reg_write( DDR_REG_BASE +0x51328*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51329*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5132a*4 +0x02000000,0xbfc1); +reg_write( DDR_REG_BASE +0x5132b*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5132c*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x5132d*4 +0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x5132e*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x5132f*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51330*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51331*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51332*4 +0x02000000,0xc72); +reg_write( DDR_REG_BASE +0x51333*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51334*4 +0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x51335*4 +0x02000000,0xc0a7); +reg_write( DDR_REG_BASE +0x51336*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x51337*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x51338*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51339*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5133a*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5133b*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x5133c*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5133d*4 +0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x5133e*4 +0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x5133f*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51340*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51341*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51342*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51343*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51344*4 +0x02000000,0x7101); +reg_write( DDR_REG_BASE +0x51345*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51346*4 +0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x51347*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51348*4 +0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x51349*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5134a*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5134b*4 +0x02000000,0x225f); +reg_write( DDR_REG_BASE +0x5134c*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5134d*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x5134e*4 +0x02000000,0x7c3); +reg_write( DDR_REG_BASE +0x5134f*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x51350*4 +0x02000000,0xeb05); +reg_write( DDR_REG_BASE +0x51351*4 +0x02000000,0xbb61); +reg_write( DDR_REG_BASE +0x51352*4 +0x02000000,0xbff); +reg_write( DDR_REG_BASE +0x51353*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x51354*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51355*4 +0x02000000,0xb8c3); +reg_write( DDR_REG_BASE +0x51356*4 +0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x51357*4 +0x02000000,0x190); +reg_write( DDR_REG_BASE +0x51358*4 +0x02000000,0x877); +reg_write( DDR_REG_BASE +0x51359*4 +0x02000000,0x71); +reg_write( DDR_REG_BASE +0x5135a*4 +0x02000000,0xdf18); +reg_write( DDR_REG_BASE +0x5135b*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x5135c*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5135d*4 +0x02000000,0x116); +reg_write( DDR_REG_BASE +0x5135e*4 +0x02000000,0x1e08); +reg_write( DDR_REG_BASE +0x5135f*4 +0x02000000,0x1094); +reg_write( DDR_REG_BASE +0x51360*4 +0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x51361*4 +0x02000000,0x1e02); +reg_write( DDR_REG_BASE +0x51362*4 +0x02000000,0x1055); +reg_write( DDR_REG_BASE +0x51363*4 +0x02000000,0xd829); +reg_write( DDR_REG_BASE +0x51364*4 +0x02000000,0xb6a0); +reg_write( DDR_REG_BASE +0x51365*4 +0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x51366*4 +0x02000000,0x1205); +reg_write( DDR_REG_BASE +0x51367*4 +0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x51368*4 +0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x51369*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5136a*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5136b*4 +0x02000000,0x98); +reg_write( DDR_REG_BASE +0x5136c*4 +0x02000000,0x9680); +reg_write( DDR_REG_BASE +0x5136d*4 +0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x5136e*4 +0x02000000,0x1ef2); +reg_write( DDR_REG_BASE +0x5136f*4 +0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x51370*4 +0x02000000,0x9fe); +reg_write( DDR_REG_BASE +0x51371*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x51372*4 +0x02000000,0x1e66); +reg_write( DDR_REG_BASE +0x51373*4 +0x02000000,0x1044); +reg_write( DDR_REG_BASE +0x51374*4 +0x02000000,0xd8a9); +reg_write( DDR_REG_BASE +0x51375*4 +0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x51376*4 +0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x51377*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x51378*4 +0x02000000,0xa46); +reg_write( DDR_REG_BASE +0x51379*4 +0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x5137a*4 +0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x5137b*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x5137c*4 +0x02000000,0xa44); +reg_write( DDR_REG_BASE +0x5137d*4 +0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x5137e*4 +0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x5137f*4 +0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x51380*4 +0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x51381*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51382*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51383*4 +0x02000000,0x6000); +reg_write( DDR_REG_BASE +0x51384*4 +0x02000000,0x1e72); +reg_write( DDR_REG_BASE +0x51385*4 +0x02000000,0x935c); +reg_write( DDR_REG_BASE +0x51386*4 +0x02000000,0x1ed0); +reg_write( DDR_REG_BASE +0x51387*4 +0x02000000,0x9344); +reg_write( DDR_REG_BASE +0x51388*4 +0x02000000,0x1e72); +reg_write( DDR_REG_BASE +0x51389*4 +0x02000000,0x90dd); +reg_write( DDR_REG_BASE +0x5138a*4 +0x02000000,0x972); +reg_write( DDR_REG_BASE +0x5138b*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5138c*4 +0x02000000,0x1ed0); +reg_write( DDR_REG_BASE +0x5138d*4 +0x02000000,0x92c4); +reg_write( DDR_REG_BASE +0x5138e*4 +0x02000000,0x1e72); +reg_write( DDR_REG_BASE +0x5138f*4 +0x02000000,0x935c); +reg_write( DDR_REG_BASE +0x51390*4 +0x02000000,0x1e72); +reg_write( DDR_REG_BASE +0x51391*4 +0x02000000,0x92dc); +reg_write( DDR_REG_BASE +0x51392*4 +0x02000000,0xf046); +reg_write( DDR_REG_BASE +0x51393*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x51394*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51395*4 +0x02000000,0x116); +reg_write( DDR_REG_BASE +0x51396*4 +0x02000000,0x1d08); +reg_write( DDR_REG_BASE +0x51397*4 +0x02000000,0x1094); +reg_write( DDR_REG_BASE +0x51398*4 +0x02000000,0x71cd); +reg_write( DDR_REG_BASE +0x51399*4 +0x02000000,0x1d02); +reg_write( DDR_REG_BASE +0x5139a*4 +0x02000000,0x1055); +reg_write( DDR_REG_BASE +0x5139b*4 +0x02000000,0x234a); +reg_write( DDR_REG_BASE +0x5139c*4 +0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x5139d*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5139e*4 +0x02000000,0xbf8b); +reg_write( DDR_REG_BASE +0x5139f*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x513a0*4 +0x02000000,0xf); +reg_write( DDR_REG_BASE +0x513a1*4 +0x02000000,0x4240); +reg_write( DDR_REG_BASE +0x513a2*4 +0x02000000,0xb5c0); +reg_write( DDR_REG_BASE +0x513a3*4 +0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x513a4*4 +0x02000000,0x12c4); +reg_write( DDR_REG_BASE +0x513a5*4 +0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x513a6*4 +0x02000000,0x3040); +reg_write( DDR_REG_BASE +0x513a7*4 +0x02000000,0x1df2); +reg_write( DDR_REG_BASE +0x513a8*4 +0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x513a9*4 +0x02000000,0x1d66); +reg_write( DDR_REG_BASE +0x513aa*4 +0x02000000,0x1044); +reg_write( DDR_REG_BASE +0x513ab*4 +0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x513ac*4 +0x02000000,0x13c4); +reg_write( DDR_REG_BASE +0x513ad*4 +0x02000000,0x986); +reg_write( DDR_REG_BASE +0x513ae*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x513af*4 +0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x513b0*4 +0x02000000,0xbf70); +reg_write( DDR_REG_BASE +0x513b1*4 +0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x513b2*4 +0x02000000,0x6c2); +reg_write( DDR_REG_BASE +0x513b3*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x513b4*4 +0x02000000,0x976); +reg_write( DDR_REG_BASE +0x513b5*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x513b6*4 +0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x513b7*4 +0x02000000,0x13c4); +reg_write( DDR_REG_BASE +0x513b8*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x513b9*4 +0x02000000,0x98); +reg_write( DDR_REG_BASE +0x513ba*4 +0x02000000,0x9680); +reg_write( DDR_REG_BASE +0x513bb*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x513bc*4 +0x02000000,0x966); +reg_write( DDR_REG_BASE +0x513bd*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x513be*4 +0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x513bf*4 +0x02000000,0x12c4); +reg_write( DDR_REG_BASE +0x513c0*4 +0x02000000,0xd888); +reg_write( DDR_REG_BASE +0x513c1*4 +0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x513c2*4 +0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x513c3*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x513c4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x513c5*4 +0x02000000,0x6000); +reg_write( DDR_REG_BASE +0x513c6*4 +0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x513c7*4 +0x02000000,0x12c4); +reg_write( DDR_REG_BASE +0x513c8*4 +0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x513c9*4 +0x02000000,0x1784); +reg_write( DDR_REG_BASE +0x513ca*4 +0x02000000,0x1d72); +reg_write( DDR_REG_BASE +0x513cb*4 +0x02000000,0x939c); +reg_write( DDR_REG_BASE +0x513cc*4 +0x02000000,0x1dd0); +reg_write( DDR_REG_BASE +0x513cd*4 +0x02000000,0x9384); +reg_write( DDR_REG_BASE +0x513ce*4 +0x02000000,0x1d72); +reg_write( DDR_REG_BASE +0x513cf*4 +0x02000000,0x90dd); +reg_write( DDR_REG_BASE +0x513d0*4 +0x02000000,0x8e6); +reg_write( DDR_REG_BASE +0x513d1*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x513d2*4 +0x02000000,0x1dd0); +reg_write( DDR_REG_BASE +0x513d3*4 +0x02000000,0x9784); +reg_write( DDR_REG_BASE +0x513d4*4 +0x02000000,0x1d72); +reg_write( DDR_REG_BASE +0x513d5*4 +0x02000000,0x939c); +reg_write( DDR_REG_BASE +0x513d6*4 +0x02000000,0x1d72); +reg_write( DDR_REG_BASE +0x513d7*4 +0x02000000,0x979c); +reg_write( DDR_REG_BASE +0x513d8*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x513d9*4 +0x02000000,0x92e); +reg_write( DDR_REG_BASE +0x513da*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x513db*4 +0x02000000,0xd920); +reg_write( DDR_REG_BASE +0x513dc*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x513dd*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x513de*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x513df*4 +0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x513e0*4 +0x02000000,0x8c6); +reg_write( DDR_REG_BASE +0x513e1*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x513e2*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x513e3*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x513e4*4 +0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x513e5*4 +0x02000000,0x8be); +reg_write( DDR_REG_BASE +0x513e6*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x513e7*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x513e8*4 +0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x513e9*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x513ea*4 +0x02000000,0x8b2); +reg_write( DDR_REG_BASE +0x513eb*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x513ec*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x513ed*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x513ee*4 +0x02000000,0x1d0a); +reg_write( DDR_REG_BASE +0x513ef*4 +0x02000000,0x909d); +reg_write( DDR_REG_BASE +0x513f0*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x513f1*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x513f2*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x513f3*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x513f4*4 +0x02000000,0x2088); +reg_write( DDR_REG_BASE +0x513f5*4 +0x02000000,0x901); +reg_write( DDR_REG_BASE +0x513f6*4 +0x02000000,0x2089); +reg_write( DDR_REG_BASE +0x513f7*4 +0x02000000,0x906); +reg_write( DDR_REG_BASE +0x513f8*4 +0x02000000,0x2080); +reg_write( DDR_REG_BASE +0x513f9*4 +0x02000000,0x78e); +reg_write( DDR_REG_BASE +0x513fa*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x513fb*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x513fc*4 +0x02000000,0x9); +reg_write( DDR_REG_BASE +0x513fd*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x513fe*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x513ff*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51400*4 +0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x51401*4 +0x02000000,0x8f4); +reg_write( DDR_REG_BASE +0x51402*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x51403*4 +0x02000000,0xb97e); +reg_write( DDR_REG_BASE +0x51404*4 +0x02000000,0xb986); +reg_write( DDR_REG_BASE +0x51405*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x51406*4 +0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x51407*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51408*4 +0x02000000,0xc3e6); +reg_write( DDR_REG_BASE +0x51409*4 +0x02000000,0xc1aa); +reg_write( DDR_REG_BASE +0x5140a*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x5140b*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5140c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5140d*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x5140e*4 +0x02000000,0xa8cd); +reg_write( DDR_REG_BASE +0x5140f*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51410*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51411*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51412*4 +0x02000000,0xa8cc); +reg_write( DDR_REG_BASE +0x51413*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51414*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51415*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51416*4 +0x02000000,0xa8cb); +reg_write( DDR_REG_BASE +0x51417*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51418*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51419*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x5141a*4 +0x02000000,0xa8ca); +reg_write( DDR_REG_BASE +0x5141b*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5141c*4 +0x02000000,0x89); +reg_write( DDR_REG_BASE +0x5141d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5141e*4 +0x02000000,0xe82); +reg_write( DDR_REG_BASE +0x5141f*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51420*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51421*4 +0x02000000,0x23b); +reg_write( DDR_REG_BASE +0x51422*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51423*4 +0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x51424*4 +0x02000000,0x17c1); +reg_write( DDR_REG_BASE +0x51425*4 +0x02000000,0xe906); +reg_write( DDR_REG_BASE +0x51426*4 +0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x51427*4 +0x02000000,0x901); +reg_write( DDR_REG_BASE +0x51428*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x51429*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5142a*4 +0x02000000,0x1be4); +reg_write( DDR_REG_BASE +0x5142b*4 +0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x5142c*4 +0x02000000,0x211); +reg_write( DDR_REG_BASE +0x5142d*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5142e*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5142f*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51430*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51431*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51432*4 +0x02000000,0x1b); +reg_write( DDR_REG_BASE +0x51433*4 +0x02000000,0x81f); +reg_write( DDR_REG_BASE +0x51434*4 +0x02000000,0x5e); +reg_write( DDR_REG_BASE +0x51435*4 +0x02000000,0xea07); +reg_write( DDR_REG_BASE +0x51436*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51437*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51438*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51439*4 +0x02000000,0x7d); +reg_write( DDR_REG_BASE +0x5143a*4 +0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x5143b*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5143c*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5143d*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5143e*4 +0x02000000,0x4a); +reg_write( DDR_REG_BASE +0x5143f*4 +0x02000000,0x7610); +reg_write( DDR_REG_BASE +0x51440*4 +0x02000000,0xf4f3); +reg_write( DDR_REG_BASE +0x51441*4 +0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x51442*4 +0x02000000,0x1bf0); +reg_write( DDR_REG_BASE +0x51443*4 +0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x51444*4 +0x02000000,0x13f0); +reg_write( DDR_REG_BASE +0x51445*4 +0x02000000,0xb001); +reg_write( DDR_REG_BASE +0x51446*4 +0x02000000,0xc62); +reg_write( DDR_REG_BASE +0x51447*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x51448*4 +0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x51449*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x5144a*4 +0x02000000,0xea0b); +reg_write( DDR_REG_BASE +0x5144b*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5144c*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x5144d*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5144e*4 +0x02000000,0x58); +reg_write( DDR_REG_BASE +0x5144f*4 +0x02000000,0x13e4); +reg_write( DDR_REG_BASE +0x51450*4 +0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x51451*4 +0x02000000,0x782b); +reg_write( DDR_REG_BASE +0x51452*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51453*4 +0x02000000,0xf40c); +reg_write( DDR_REG_BASE +0x51454*4 +0x02000000,0xf0df); +reg_write( DDR_REG_BASE +0x51455*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51456*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51457*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51458*4 +0x02000000,0x25); +reg_write( DDR_REG_BASE +0x51459*4 +0x02000000,0x13e4); +reg_write( DDR_REG_BASE +0x5145a*4 +0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x5145b*4 +0x02000000,0x782b); +reg_write( DDR_REG_BASE +0x5145c*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5145d*4 +0x02000000,0xf2d7); +reg_write( DDR_REG_BASE +0x5145e*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5145f*4 +0x02000000,0xbac4); +reg_write( DDR_REG_BASE +0x51460*4 +0x02000000,0xea05); +reg_write( DDR_REG_BASE +0x51461*4 +0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x51462*4 +0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x51463*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x51464*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51465*4 +0x02000000,0xa4e); +reg_write( DDR_REG_BASE +0x51466*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51467*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51468*4 +0x02000000,0x13e4); +reg_write( DDR_REG_BASE +0x51469*4 +0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x5146a*4 +0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x5146b*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5146c*4 +0x02000000,0x7043); +reg_write( DDR_REG_BASE +0x5146d*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5146e*4 +0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x5146f*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51470*4 +0x02000000,0xb06); +reg_write( DDR_REG_BASE +0x51471*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51472*4 +0x02000000,0x1be8); +reg_write( DDR_REG_BASE +0x51473*4 +0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x51474*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51475*4 +0x02000000,0xd854); +reg_write( DDR_REG_BASE +0x51476*4 +0x02000000,0x1be0); +reg_write( DDR_REG_BASE +0x51477*4 +0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x51478*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51479*4 +0x02000000,0x7042); +reg_write( DDR_REG_BASE +0x5147a*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5147b*4 +0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x5147c*4 +0x02000000,0x1bfc); +reg_write( DDR_REG_BASE +0x5147d*4 +0x02000000,0xb700); +reg_write( DDR_REG_BASE +0x5147e*4 +0x02000000,0x2402); +reg_write( DDR_REG_BASE +0x5147f*4 +0x02000000,0x301c); +reg_write( DDR_REG_BASE +0x51480*4 +0x02000000,0xc082); +reg_write( DDR_REG_BASE +0x51481*4 +0x02000000,0xf9a); +reg_write( DDR_REG_BASE +0x51482*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51483*4 +0x02000000,0x1bec); +reg_write( DDR_REG_BASE +0x51484*4 +0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x51485*4 +0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x51486*4 +0x02000000,0x1801); +reg_write( DDR_REG_BASE +0x51487*4 +0x02000000,0x13); +reg_write( DDR_REG_BASE +0x51488*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x51489*4 +0x02000000,0xe1d0); +reg_write( DDR_REG_BASE +0x5148a*4 +0x02000000,0xf7fc); +reg_write( DDR_REG_BASE +0x5148b*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x5148c*4 +0x02000000,0xf041); +reg_write( DDR_REG_BASE +0x5148d*4 +0x02000000,0xeea); +reg_write( DDR_REG_BASE +0x5148e*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5148f*4 +0x02000000,0x78af); +reg_write( DDR_REG_BASE +0x51490*4 +0x02000000,0x1bf4); +reg_write( DDR_REG_BASE +0x51491*4 +0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x51492*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51493*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51494*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51495*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51496*4 +0x02000000,0x13e8); +reg_write( DDR_REG_BASE +0x51497*4 +0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x51498*4 +0x02000000,0x13f4); +reg_write( DDR_REG_BASE +0x51499*4 +0x02000000,0xb002); +reg_write( DDR_REG_BASE +0x5149a*4 +0x02000000,0xe56); +reg_write( DDR_REG_BASE +0x5149b*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5149c*4 +0x02000000,0x1bf8); +reg_write( DDR_REG_BASE +0x5149d*4 +0x02000000,0xb001); +reg_write( DDR_REG_BASE +0x5149e*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5149f*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x514a0*4 +0x02000000,0xd090); +reg_write( DDR_REG_BASE +0x514a1*4 +0x02000000,0xf9e); +reg_write( DDR_REG_BASE +0x514a2*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x514a3*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x514a4*4 +0x02000000,0x84a); +reg_write( DDR_REG_BASE +0x514a5*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x514a6*4 +0x02000000,0x13e8); +reg_write( DDR_REG_BASE +0x514a7*4 +0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514a8*4 +0x02000000,0x13f0); +reg_write( DDR_REG_BASE +0x514a9*4 +0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514aa*4 +0x02000000,0x2342); +reg_write( DDR_REG_BASE +0x514ab*4 +0x02000000,0x3201); +reg_write( DDR_REG_BASE +0x514ac*4 +0x02000000,0x85e); +reg_write( DDR_REG_BASE +0x514ad*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x514ae*4 +0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x514af*4 +0x02000000,0x13f8); +reg_write( DDR_REG_BASE +0x514b0*4 +0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514b1*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x514b2*4 +0x02000000,0x8a); +reg_write( DDR_REG_BASE +0x514b3*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x514b4*4 +0x02000000,0x43c1); +reg_write( DDR_REG_BASE +0x514b5*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x514b6*4 +0x02000000,0xf8f); +reg_write( DDR_REG_BASE +0x514b7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x514b8*4 +0x02000000,0x3f00); +reg_write( DDR_REG_BASE +0x514b9*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x514ba*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x514bb*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x514bc*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x514bd*4 +0x02000000,0x1bf8); +reg_write( DDR_REG_BASE +0x514be*4 +0x02000000,0xb3c0); +reg_write( DDR_REG_BASE +0x514bf*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x514c0*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x514c1*4 +0x02000000,0x13f4); +reg_write( DDR_REG_BASE +0x514c2*4 +0x02000000,0xb002); +reg_write( DDR_REG_BASE +0x514c3*4 +0x02000000,0xd3a); +reg_write( DDR_REG_BASE +0x514c4*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x514c5*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x514c6*4 +0x02000000,0xef06); +reg_write( DDR_REG_BASE +0x514c7*4 +0x02000000,0x13ec); +reg_write( DDR_REG_BASE +0x514c8*4 +0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514c9*4 +0x02000000,0x60b8); +reg_write( DDR_REG_BASE +0x514ca*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x514cb*4 +0x02000000,0x43); +reg_write( DDR_REG_BASE +0x514cc*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x514cd*4 +0x02000000,0xe5d0); +reg_write( DDR_REG_BASE +0x514ce*4 +0x02000000,0x77e); +reg_write( DDR_REG_BASE +0x514cf*4 +0x02000000,0xffee); +reg_write( DDR_REG_BASE +0x514d0*4 +0x02000000,0x774c); +reg_write( DDR_REG_BASE +0x514d1*4 +0x02000000,0x4548); +reg_write( DDR_REG_BASE +0x514d2*4 +0x02000000,0x4748); +reg_write( DDR_REG_BASE +0x514d3*4 +0x02000000,0x4140); +reg_write( DDR_REG_BASE +0x514d4*4 +0x02000000,0xf022); +reg_write( DDR_REG_BASE +0x514d5*4 +0x02000000,0x13ec); +reg_write( DDR_REG_BASE +0x514d6*4 +0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514d7*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x514d8*4 +0x02000000,0x483); +reg_write( DDR_REG_BASE +0x514d9*4 +0x02000000,0x1bec); +reg_write( DDR_REG_BASE +0x514da*4 +0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514db*4 +0x02000000,0xf212); +reg_write( DDR_REG_BASE +0x514dc*4 +0x02000000,0x13e0); +reg_write( DDR_REG_BASE +0x514dd*4 +0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514de*4 +0x02000000,0xe0d0); +reg_write( DDR_REG_BASE +0x514df*4 +0x02000000,0xf203); +reg_write( DDR_REG_BASE +0x514e0*4 +0x02000000,0xeb11); +reg_write( DDR_REG_BASE +0x514e1*4 +0x02000000,0x13e0); +reg_write( DDR_REG_BASE +0x514e2*4 +0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514e3*4 +0x02000000,0x4fb4); +reg_write( DDR_REG_BASE +0x514e4*4 +0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x514e5*4 +0x02000000,0x4833); +reg_write( DDR_REG_BASE +0x514e6*4 +0x02000000,0x7391); +reg_write( DDR_REG_BASE +0x514e7*4 +0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x514e8*4 +0x02000000,0x1009); +reg_write( DDR_REG_BASE +0x514e9*4 +0x02000000,0x25ca); +reg_write( DDR_REG_BASE +0x514ea*4 +0x02000000,0x1049); +reg_write( DDR_REG_BASE +0x514eb*4 +0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x514ec*4 +0x02000000,0xeb03); +reg_write( DDR_REG_BASE +0x514ed*4 +0x02000000,0x772c); +reg_write( DDR_REG_BASE +0x514ee*4 +0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x514ef*4 +0x02000000,0x13e0); +reg_write( DDR_REG_BASE +0x514f0*4 +0x02000000,0xb001); +reg_write( DDR_REG_BASE +0x514f1*4 +0x02000000,0x13e0); +reg_write( DDR_REG_BASE +0x514f2*4 +0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514f3*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x514f4*4 +0x02000000,0x1be0); +reg_write( DDR_REG_BASE +0x514f5*4 +0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514f6*4 +0x02000000,0x13e0); +reg_write( DDR_REG_BASE +0x514f7*4 +0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x514f8*4 +0x02000000,0xe0d1); +reg_write( DDR_REG_BASE +0x514f9*4 +0x02000000,0x7ba); +reg_write( DDR_REG_BASE +0x514fa*4 +0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x514fb*4 +0x02000000,0x7734); +reg_write( DDR_REG_BASE +0x514fc*4 +0x02000000,0x2139); +reg_write( DDR_REG_BASE +0x514fd*4 +0x02000000,0x83); +reg_write( DDR_REG_BASE +0x514fe*4 +0x02000000,0x2538); +reg_write( DDR_REG_BASE +0x514ff*4 +0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x51500*4 +0x02000000,0x786b); +reg_write( DDR_REG_BASE +0x51501*4 +0x02000000,0xd850); +reg_write( DDR_REG_BASE +0x51502*4 +0x02000000,0x753c); +reg_write( DDR_REG_BASE +0x51503*4 +0x02000000,0x771c); +reg_write( DDR_REG_BASE +0x51504*4 +0x02000000,0x77b5); +reg_write( DDR_REG_BASE +0x51505*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51506*4 +0x02000000,0xf204); +reg_write( DDR_REG_BASE +0x51507*4 +0x02000000,0x4fb0); +reg_write( DDR_REG_BASE +0x51508*4 +0x02000000,0x207f); +reg_write( DDR_REG_BASE +0x51509*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5150a*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5150b*4 +0x02000000,0x7083); +reg_write( DDR_REG_BASE +0x5150c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5150d*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x5150e*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5150f*4 +0x02000000,0x8c); +reg_write( DDR_REG_BASE +0x51510*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x51511*4 +0x02000000,0xf32); +reg_write( DDR_REG_BASE +0x51512*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51513*4 +0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x51514*4 +0x02000000,0x67b8); +reg_write( DDR_REG_BASE +0x51515*4 +0x02000000,0x2844); +reg_write( DDR_REG_BASE +0x51516*4 +0x02000000,0x80); +reg_write( DDR_REG_BASE +0x51517*4 +0x02000000,0xdd6); +reg_write( DDR_REG_BASE +0x51518*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51519*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x5151a*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5151b*4 +0x02000000,0x7043); +reg_write( DDR_REG_BASE +0x5151c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5151d*4 +0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x5151e*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5151f*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51520*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51521*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51522*4 +0x02000000,0x2614); +reg_write( DDR_REG_BASE +0x51523*4 +0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x51524*4 +0x02000000,0x2100); +reg_write( DDR_REG_BASE +0x51525*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51526*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51527*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51528*4 +0x02000000,0xa90a); +reg_write( DDR_REG_BASE +0x51529*4 +0x02000000,0xcda); +reg_write( DDR_REG_BASE +0x5152a*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x5152b*4 +0x02000000,0x13e8); +reg_write( DDR_REG_BASE +0x5152c*4 +0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x5152d*4 +0x02000000,0x13fc); +reg_write( DDR_REG_BASE +0x5152e*4 +0x02000000,0xb01c); +reg_write( DDR_REG_BASE +0x5152f*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51530*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51531*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51532*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51533*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x51534*4 +0x02000000,0x7a2f); +reg_write( DDR_REG_BASE +0x51535*4 +0x02000000,0x7154); +reg_write( DDR_REG_BASE +0x51536*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51537*4 +0x02000000,0x7042); +reg_write( DDR_REG_BASE +0x51538*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51539*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x5153a*4 +0x02000000,0x5ea); +reg_write( DDR_REG_BASE +0x5153b*4 +0x02000000,0xffce); +reg_write( DDR_REG_BASE +0x5153c*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x5153d*4 +0x02000000,0x72d5); +reg_write( DDR_REG_BASE +0x5153e*4 +0x02000000,0x5ca); +reg_write( DDR_REG_BASE +0x5153f*4 +0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x51540*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51541*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51542*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51543*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51544*4 +0x02000000,0x180e); +reg_write( DDR_REG_BASE +0x51545*4 +0x02000000,0x43); +reg_write( DDR_REG_BASE +0x51546*4 +0x02000000,0xc7c6); +reg_write( DDR_REG_BASE +0x51547*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51548*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51549*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5154a*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5154b*4 +0x02000000,0xc1bd); +reg_write( DDR_REG_BASE +0x5154c*4 +0x02000000,0xd925); +reg_write( DDR_REG_BASE +0x5154d*4 +0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x5154e*4 +0x02000000,0x8900); +reg_write( DDR_REG_BASE +0x5154f*4 +0x02000000,0x1c3a); +reg_write( DDR_REG_BASE +0x51550*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x51551*4 +0x02000000,0x1133); +reg_write( DDR_REG_BASE +0x51552*4 +0x02000000,0x80); +reg_write( DDR_REG_BASE +0x51553*4 +0x02000000,0x1c3b); +reg_write( DDR_REG_BASE +0x51554*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x51555*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51556*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51557*4 +0x02000000,0x7c8); +reg_write( DDR_REG_BASE +0x51558*4 +0x02000000,0x8827); +reg_write( DDR_REG_BASE +0x51559*4 +0x02000000,0x88a0); +reg_write( DDR_REG_BASE +0x5155a*4 +0x02000000,0xc16e); +reg_write( DDR_REG_BASE +0x5155b*4 +0x02000000,0x8829); +reg_write( DDR_REG_BASE +0x5155c*4 +0x02000000,0x1c39); +reg_write( DDR_REG_BASE +0x5155d*4 +0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x5155e*4 +0x02000000,0x8828); +reg_write( DDR_REG_BASE +0x5155f*4 +0x02000000,0x1c36); +reg_write( DDR_REG_BASE +0x51560*4 +0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x51561*4 +0x02000000,0x882a); +reg_write( DDR_REG_BASE +0x51562*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51563*4 +0x02000000,0x1c37); +reg_write( DDR_REG_BASE +0x51564*4 +0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x51565*4 +0x02000000,0xe46); +reg_write( DDR_REG_BASE +0x51566*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51567*4 +0x02000000,0xc193); +reg_write( DDR_REG_BASE +0x51568*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51569*4 +0x02000000,0xc146); +reg_write( DDR_REG_BASE +0x5156a*4 +0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x5156b*4 +0x02000000,0x7a34); +reg_write( DDR_REG_BASE +0x5156c*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5156d*4 +0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x5156e*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x5156f*4 +0x02000000,0x9fb); +reg_write( DDR_REG_BASE +0x51570*4 +0x02000000,0x82b4); +reg_write( DDR_REG_BASE +0x51571*4 +0x02000000,0xc298); +reg_write( DDR_REG_BASE +0x51572*4 +0x02000000,0xd90c); +reg_write( DDR_REG_BASE +0x51573*4 +0x02000000,0x2905); +reg_write( DDR_REG_BASE +0x51574*4 +0x02000000,0x341); +reg_write( DDR_REG_BASE +0x51575*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x51576*4 +0x02000000,0x7835); +reg_write( DDR_REG_BASE +0x51577*4 +0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x51578*4 +0x02000000,0x40d); +reg_write( DDR_REG_BASE +0x51579*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5157a*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5157b*4 +0x02000000,0x3ff); +reg_write( DDR_REG_BASE +0x5157c*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5157d*4 +0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x5157e*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5157f*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51580*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x51581*4 +0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x51582*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x51583*4 +0x02000000,0xc105); +reg_write( DDR_REG_BASE +0x51584*4 +0x02000000,0xea05); +reg_write( DDR_REG_BASE +0x51585*4 +0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x51586*4 +0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x51587*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x51588*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51589*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x5158a*4 +0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x5158b*4 +0x02000000,0x6c7); +reg_write( DDR_REG_BASE +0x5158c*4 +0x02000000,0xdca); +reg_write( DDR_REG_BASE +0x5158d*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5158e*4 +0x02000000,0x792f); +reg_write( DDR_REG_BASE +0x5158f*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51590*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51591*4 +0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x51592*4 +0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x51593*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x51594*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51595*4 +0x02000000,0xf2f6); +reg_write( DDR_REG_BASE +0x51596*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51597*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51598*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51599*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5159a*4 +0x02000000,0xb8e3); +reg_write( DDR_REG_BASE +0x5159b*4 +0x02000000,0xf4f0); +reg_write( DDR_REG_BASE +0x5159c*4 +0x02000000,0xab6); +reg_write( DDR_REG_BASE +0x5159d*4 +0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x5159e*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x5159f*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x515a0*4 +0x02000000,0xf07e); +reg_write( DDR_REG_BASE +0x515a1*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x515a2*4 +0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x515a3*4 +0x02000000,0x80); +reg_write( DDR_REG_BASE +0x515a4*4 +0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x515a5*4 +0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x515a6*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x515a7*4 +0x02000000,0xb882); +reg_write( DDR_REG_BASE +0x515a8*4 +0x02000000,0x815); +reg_write( DDR_REG_BASE +0x515a9*4 +0x02000000,0x131); +reg_write( DDR_REG_BASE +0x515aa*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x515ab*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x515ac*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x515ad*4 +0x02000000,0xa00); +reg_write( DDR_REG_BASE +0x515ae*4 +0x02000000,0xea2); +reg_write( DDR_REG_BASE +0x515af*4 +0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x515b0*4 +0x02000000,0xec2); +reg_write( DDR_REG_BASE +0x515b1*4 +0x02000000,0x180); +reg_write( DDR_REG_BASE +0x515b2*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x515b3*4 +0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x515b4*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x515b5*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x515b6*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x515b7*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x515b8*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x515b9*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x515ba*4 +0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x515bb*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x515bc*4 +0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x515bd*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x515be*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x515bf*4 +0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x515c0*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x515c1*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x515c2*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x515c3*4 +0x02000000,0x800); +reg_write( DDR_REG_BASE +0x515c4*4 +0x02000000,0x2045); +reg_write( DDR_REG_BASE +0x515c5*4 +0x02000000,0x180); +reg_write( DDR_REG_BASE +0x515c6*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x515c7*4 +0x02000000,0xf4a); +reg_write( DDR_REG_BASE +0x515c8*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x515c9*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x515ca*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x515cb*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x515cc*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x515cd*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x515ce*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x515cf*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x515d0*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x515d1*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x515d2*4 +0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x515d3*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x515d4*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x515d5*4 +0x02000000,0x448); +reg_write( DDR_REG_BASE +0x515d6*4 +0x02000000,0xb8c5); +reg_write( DDR_REG_BASE +0x515d7*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x515d8*4 +0x02000000,0xf26); +reg_write( DDR_REG_BASE +0x515d9*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x515da*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x515db*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x515dc*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x515dd*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x515de*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x515df*4 +0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x515e0*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x515e1*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x515e2*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x515e3*4 +0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x515e4*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x515e5*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x515e6*4 +0x02000000,0x800); +reg_write( DDR_REG_BASE +0x515e7*4 +0x02000000,0x2045); +reg_write( DDR_REG_BASE +0x515e8*4 +0x02000000,0x580); +reg_write( DDR_REG_BASE +0x515e9*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x515ea*4 +0x02000000,0xf02); +reg_write( DDR_REG_BASE +0x515eb*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x515ec*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x515ed*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x515ee*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x515ef*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x515f0*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x515f1*4 +0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x515f2*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x515f3*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x515f4*4 +0x02000000,0xb8c5); +reg_write( DDR_REG_BASE +0x515f5*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x515f6*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x515f7*4 +0x02000000,0xeea); +reg_write( DDR_REG_BASE +0x515f8*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x515f9*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x515fa*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x515fb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x515fc*4 +0x02000000,0x2710); +reg_write( DDR_REG_BASE +0x515fd*4 +0x02000000,0xd06); +reg_write( DDR_REG_BASE +0x515fe*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x515ff*4 +0x02000000,0xd90a); +reg_write( DDR_REG_BASE +0x51600*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51601*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51602*4 +0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x51603*4 +0x02000000,0x7d0f); +reg_write( DDR_REG_BASE +0x51604*4 +0x02000000,0xf8dd); +reg_write( DDR_REG_BASE +0x51605*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51606*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x51607*4 +0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x51608*4 +0x02000000,0xec6); +reg_write( DDR_REG_BASE +0x51609*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5160a*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5160b*4 +0x02000000,0xf8da); +reg_write( DDR_REG_BASE +0x5160c*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5160d*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5160e*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x5160f*4 +0x02000000,0xeba); +reg_write( DDR_REG_BASE +0x51610*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51611*4 +0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x51612*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51613*4 +0x02000000,0xb863); +reg_write( DDR_REG_BASE +0x51614*4 +0x02000000,0x811); +reg_write( DDR_REG_BASE +0x51615*4 +0x02000000,0x95); +reg_write( DDR_REG_BASE +0x51616*4 +0x02000000,0xd9e); +reg_write( DDR_REG_BASE +0x51617*4 +0x02000000,0x180); +reg_write( DDR_REG_BASE +0x51618*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51619*4 +0x02000000,0xe66); +reg_write( DDR_REG_BASE +0x5161a*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5161b*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5161c*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5161d*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5161e*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5161f*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51620*4 +0x02000000,0x7514); +reg_write( DDR_REG_BASE +0x51621*4 +0x02000000,0x702); +reg_write( DDR_REG_BASE +0x51622*4 +0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x51623*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x51624*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51625*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51626*4 +0x02000000,0xa00); +reg_write( DDR_REG_BASE +0x51627*4 +0x02000000,0xdb2); +reg_write( DDR_REG_BASE +0x51628*4 +0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x51629*4 +0x02000000,0xdd2); +reg_write( DDR_REG_BASE +0x5162a*4 +0x02000000,0x180); +reg_write( DDR_REG_BASE +0x5162b*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x5162c*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5162d*4 +0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x5162e*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5162f*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51630*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51631*4 +0x02000000,0xdb18); +reg_write( DDR_REG_BASE +0x51632*4 +0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x51633*4 +0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x51634*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x51635*4 +0x02000000,0xe6e); +reg_write( DDR_REG_BASE +0x51636*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51637*4 +0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x51638*4 +0x02000000,0x8b2); +reg_write( DDR_REG_BASE +0x51639*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5163a*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5163b*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x5163c*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5163d*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5163e*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5163f*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x51640*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x51641*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x51642*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51643*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x51644*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51645*4 +0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x51646*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x51647*4 +0x02000000,0xe4a); +reg_write( DDR_REG_BASE +0x51648*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51649*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5164a*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x5164b*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5164c*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5164d*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5164e*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5164f*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x51650*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51651*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x51652*4 +0x02000000,0xe32); +reg_write( DDR_REG_BASE +0x51653*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51654*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x51655*4 +0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x51656*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x51657*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51658*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51659*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5165a*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5165b*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5165c*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x5165d*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5165e*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5165f*4 +0x02000000,0xe1a); +reg_write( DDR_REG_BASE +0x51660*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51661*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x51662*4 +0x02000000,0x3481); +reg_write( DDR_REG_BASE +0x51663*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x51664*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51665*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51666*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x51667*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51668*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x51669*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5166a*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x5166b*4 +0x02000000,0xe02); +reg_write( DDR_REG_BASE +0x5166c*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5166d*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5166e*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x5166f*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51670*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51671*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x51672*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51673*4 +0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x51674*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51675*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x51676*4 +0x02000000,0xdea); +reg_write( DDR_REG_BASE +0x51677*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51678*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51679*4 +0x02000000,0x816); +reg_write( DDR_REG_BASE +0x5167a*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5167b*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5167c*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x5167d*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5167e*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5167f*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x51680*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51681*4 +0x02000000,0xdb18); +reg_write( DDR_REG_BASE +0x51682*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51683*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x51684*4 +0x02000000,0xdce); +reg_write( DDR_REG_BASE +0x51685*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51686*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51687*4 +0x02000000,0xcbe); +reg_write( DDR_REG_BASE +0x51688*4 +0x02000000,0x180); +reg_write( DDR_REG_BASE +0x51689*4 +0x02000000,0xf07f); +reg_write( DDR_REG_BASE +0x5168a*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5168b*4 +0x02000000,0xcea); +reg_write( DDR_REG_BASE +0x5168c*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5168d*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x5168e*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x5168f*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x51690*4 +0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x51691*4 +0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x51692*4 +0x02000000,0x101); +reg_write( DDR_REG_BASE +0x51693*4 +0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x51694*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51695*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51696*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x51697*4 +0x02000000,0x7e0f); +reg_write( DDR_REG_BASE +0x51698*4 +0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x51699*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5169a*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5169b*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5169c*4 +0x02000000,0xfae); +reg_write( DDR_REG_BASE +0x5169d*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5169e*4 +0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x5169f*4 +0x02000000,0xd828); +reg_write( DDR_REG_BASE +0x516a0*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x516a1*4 +0x02000000,0xf88c); +reg_write( DDR_REG_BASE +0x516a2*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x516a3*4 +0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x516a4*4 +0x02000000,0xf9e); +reg_write( DDR_REG_BASE +0x516a5*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516a6*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x516a7*4 +0x02000000,0xf889); +reg_write( DDR_REG_BASE +0x516a8*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x516a9*4 +0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x516aa*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x516ab*4 +0x02000000,0x33c1); +reg_write( DDR_REG_BASE +0x516ac*4 +0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x516ad*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516ae*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x516af*4 +0x02000000,0xf885); +reg_write( DDR_REG_BASE +0x516b0*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x516b1*4 +0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x516b2*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x516b3*4 +0x02000000,0x3501); +reg_write( DDR_REG_BASE +0x516b4*4 +0x02000000,0xf7e); +reg_write( DDR_REG_BASE +0x516b5*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516b6*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x516b7*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x516b8*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x516b9*4 +0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x516ba*4 +0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x516bb*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x516bc*4 +0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x516bd*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x516be*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x516bf*4 +0x02000000,0xf6a); +reg_write( DDR_REG_BASE +0x516c0*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516c1*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x516c2*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x516c3*4 +0x02000000,0xd12); +reg_write( DDR_REG_BASE +0x516c4*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516c5*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x516c6*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x516c7*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x516c8*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x516c9*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x516ca*4 +0x02000000,0xdae0); +reg_write( DDR_REG_BASE +0x516cb*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x516cc*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x516cd*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x516ce*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x516cf*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x516d0*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x516d1*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x516d2*4 +0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x516d3*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x516d4*4 +0x02000000,0x7204); +reg_write( DDR_REG_BASE +0x516d5*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x516d6*4 +0x02000000,0xb340); +reg_write( DDR_REG_BASE +0x516d7*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x516d8*4 +0x02000000,0x485); +reg_write( DDR_REG_BASE +0x516d9*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x516da*4 +0x02000000,0xc4a); +reg_write( DDR_REG_BASE +0x516db*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516dc*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x516dd*4 +0x02000000,0xf6a); +reg_write( DDR_REG_BASE +0x516de*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516df*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x516e0*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x516e1*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x516e2*4 +0x02000000,0xb990); +reg_write( DDR_REG_BASE +0x516e3*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x516e4*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x516e5*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x516e6*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x516e7*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x516e8*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x516e9*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x516ea*4 +0x02000000,0xd02); +reg_write( DDR_REG_BASE +0x516eb*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516ec*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x516ed*4 +0x02000000,0xd90c); +reg_write( DDR_REG_BASE +0x516ee*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x516ef*4 +0x02000000,0xb98d); +reg_write( DDR_REG_BASE +0x516f0*4 +0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x516f1*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x516f2*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x516f3*4 +0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x516f4*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x516f5*4 +0x02000000,0xcee); +reg_write( DDR_REG_BASE +0x516f6*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516f7*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x516f8*4 +0x02000000,0xf16); +reg_write( DDR_REG_BASE +0x516f9*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516fa*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x516fb*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x516fc*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x516fd*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x516fe*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x516ff*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51700*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51701*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51702*4 +0x02000000,0xcd2); +reg_write( DDR_REG_BASE +0x51703*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51704*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51705*4 +0x02000000,0xd850); +reg_write( DDR_REG_BASE +0x51706*4 +0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x51707*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51708*4 +0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x51709*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5170a*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5170b*4 +0x02000000,0xe048); +reg_write( DDR_REG_BASE +0x5170c*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x5170d*4 +0x02000000,0x1804); +reg_write( DDR_REG_BASE +0x5170e*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x5170f*4 +0x02000000,0x2440); +reg_write( DDR_REG_BASE +0x51710*4 +0x02000000,0x3e80); +reg_write( DDR_REG_BASE +0x51711*4 +0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x51712*4 +0x02000000,0x6c1); +reg_write( DDR_REG_BASE +0x51713*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x51714*4 +0x02000000,0x782b); +reg_write( DDR_REG_BASE +0x51715*4 +0x02000000,0xf264); +reg_write( DDR_REG_BASE +0x51716*4 +0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x51717*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51718*4 +0x02000000,0xc66); +reg_write( DDR_REG_BASE +0x51719*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5171a*4 +0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x5171b*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5171c*4 +0x02000000,0xaa6); +reg_write( DDR_REG_BASE +0x5171d*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5171e*4 +0x02000000,0xd91e); +reg_write( DDR_REG_BASE +0x5171f*4 +0x02000000,0x2440); +reg_write( DDR_REG_BASE +0x51720*4 +0x02000000,0x3d80); +reg_write( DDR_REG_BASE +0x51721*4 +0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x51722*4 +0x02000000,0x6cb); +reg_write( DDR_REG_BASE +0x51723*4 +0x02000000,0xc08e); +reg_write( DDR_REG_BASE +0x51724*4 +0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x51725*4 +0x02000000,0x6cd); +reg_write( DDR_REG_BASE +0x51726*4 +0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x51727*4 +0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x51728*4 +0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x51729*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5172a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5172b*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x5172c*4 +0x02000000,0x7a34); +reg_write( DDR_REG_BASE +0x5172d*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x5172e*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5172f*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51730*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51731*4 +0x02000000,0x54); +reg_write( DDR_REG_BASE +0x51732*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51733*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51734*4 +0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x51735*4 +0x02000000,0xbe9); +reg_write( DDR_REG_BASE +0x51736*4 +0x02000000,0x9065); +reg_write( DDR_REG_BASE +0x51737*4 +0x02000000,0xc28f); +reg_write( DDR_REG_BASE +0x51738*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51739*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5173a*4 +0x02000000,0xf034); +reg_write( DDR_REG_BASE +0x5173b*4 +0x02000000,0x23f4); +reg_write( DDR_REG_BASE +0x5173c*4 +0x02000000,0x34c); +reg_write( DDR_REG_BASE +0x5173d*4 +0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x5173e*4 +0x02000000,0x7bb4); +reg_write( DDR_REG_BASE +0x5173f*4 +0x02000000,0xbc80); +reg_write( DDR_REG_BASE +0x51740*4 +0x02000000,0xb380); +reg_write( DDR_REG_BASE +0x51741*4 +0x02000000,0xe886); +reg_write( DDR_REG_BASE +0x51742*4 +0x02000000,0xc08f); +reg_write( DDR_REG_BASE +0x51743*4 +0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x51744*4 +0x02000000,0x340); +reg_write( DDR_REG_BASE +0x51745*4 +0x02000000,0xe80f); +reg_write( DDR_REG_BASE +0x51746*4 +0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x51747*4 +0x02000000,0x340e); +reg_write( DDR_REG_BASE +0x51748*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51749*4 +0x02000000,0x7e16); +reg_write( DDR_REG_BASE +0x5174a*4 +0x02000000,0x6638); +reg_write( DDR_REG_BASE +0x5174b*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x5174c*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5174d*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5174e*4 +0x02000000,0x7a8); +reg_write( DDR_REG_BASE +0x5174f*4 +0x02000000,0xa8a0); +reg_write( DDR_REG_BASE +0x51750*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x51751*4 +0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x51752*4 +0x02000000,0xe817); +reg_write( DDR_REG_BASE +0x51753*4 +0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x51754*4 +0x02000000,0x340e); +reg_write( DDR_REG_BASE +0x51755*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51756*4 +0x02000000,0x7e16); +reg_write( DDR_REG_BASE +0x51757*4 +0x02000000,0x6658); +reg_write( DDR_REG_BASE +0x51758*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x51759*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5175a*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5175b*4 +0x02000000,0x788); +reg_write( DDR_REG_BASE +0x5175c*4 +0x02000000,0xa8a0); +reg_write( DDR_REG_BASE +0x5175d*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x5175e*4 +0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x5175f*4 +0x02000000,0xe88f); +reg_write( DDR_REG_BASE +0x51760*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51761*4 +0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x51762*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51763*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51764*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51765*4 +0x02000000,0x7404); +reg_write( DDR_REG_BASE +0x51766*4 +0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x51767*4 +0x02000000,0xb380); +reg_write( DDR_REG_BASE +0x51768*4 +0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x51769*4 +0x02000000,0xc08f); +reg_write( DDR_REG_BASE +0x5176a*4 +0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x5176b*4 +0x02000000,0x340); +reg_write( DDR_REG_BASE +0x5176c*4 +0x02000000,0xe867); +reg_write( DDR_REG_BASE +0x5176d*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x5176e*4 +0x02000000,0xb9b); +reg_write( DDR_REG_BASE +0x5176f*4 +0x02000000,0x9365); +reg_write( DDR_REG_BASE +0x51770*4 +0x02000000,0xc398); +reg_write( DDR_REG_BASE +0x51771*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51772*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51773*4 +0x02000000,0x9c4); +reg_write( DDR_REG_BASE +0x51774*4 +0x02000000,0xb96); +reg_write( DDR_REG_BASE +0x51775*4 +0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x51776*4 +0x02000000,0xb06); +reg_write( DDR_REG_BASE +0x51777*4 +0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x51778*4 +0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x51779*4 +0x02000000,0x7277); +reg_write( DDR_REG_BASE +0x5177a*4 +0x02000000,0x408); +reg_write( DDR_REG_BASE +0x5177b*4 +0x02000000,0xffc5); +reg_write( DDR_REG_BASE +0x5177c*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5177d*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5177e*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x5177f*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51780*4 +0x02000000,0x7114); +reg_write( DDR_REG_BASE +0x51781*4 +0x02000000,0x3f6); +reg_write( DDR_REG_BASE +0x51782*4 +0x02000000,0xffce); +reg_write( DDR_REG_BASE +0x51783*4 +0x02000000,0xf01a); +reg_write( DDR_REG_BASE +0x51784*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x51785*4 +0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x51786*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51787*4 +0x02000000,0xe913); +reg_write( DDR_REG_BASE +0x51788*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51789*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5178a*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5178b*4 +0x02000000,0x19); +reg_write( DDR_REG_BASE +0x5178c*4 +0x02000000,0xe88d); +reg_write( DDR_REG_BASE +0x5178d*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x5178e*4 +0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x5178f*4 +0x02000000,0x301); +reg_write( DDR_REG_BASE +0x51790*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x51791*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51792*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51793*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x51794*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51795*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51796*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51797*4 +0x02000000,0x154); +reg_write( DDR_REG_BASE +0x51798*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51799*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x5179a*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5179b*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x5179c*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x5179d*4 +0x02000000,0x8d1); +reg_write( DDR_REG_BASE +0x5179e*4 +0x02000000,0x82b4); +reg_write( DDR_REG_BASE +0x5179f*4 +0x02000000,0xc198); +reg_write( DDR_REG_BASE +0x517a0*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x517a1*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x517a2*4 +0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x517a3*4 +0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x517a4*4 +0x02000000,0xe808); +reg_write( DDR_REG_BASE +0x517a5*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x517a6*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x517a7*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x517a8*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x517a9*4 +0x02000000,0xb8e3); +reg_write( DDR_REG_BASE +0x517aa*4 +0x02000000,0x89c); +reg_write( DDR_REG_BASE +0x517ab*4 +0x02000000,0xff41); +reg_write( DDR_REG_BASE +0x517ac*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x517ad*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x517ae*4 +0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x517af*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x517b0*4 +0x02000000,0xe048); +reg_write( DDR_REG_BASE +0x517b1*4 +0x02000000,0x9ae); +reg_write( DDR_REG_BASE +0x517b2*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x517b3*4 +0x02000000,0xc193); +reg_write( DDR_REG_BASE +0x517b4*4 +0x02000000,0xc0bd); +reg_write( DDR_REG_BASE +0x517b5*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x517b6*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x517b7*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x517b8*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x517b9*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x517ba*4 +0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x517bb*4 +0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x517bc*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x517bd*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x517be*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x517bf*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x517c0*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x517c1*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x517c2*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x517c3*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x517c4*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x517c5*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x517c6*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x517c7*4 +0x02000000,0xc1a3); +reg_write( DDR_REG_BASE +0x517c8*4 +0x02000000,0x4648); +reg_write( DDR_REG_BASE +0x517c9*4 +0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x517ca*4 +0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x517cb*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x517cc*4 +0x02000000,0xf031); +reg_write( DDR_REG_BASE +0x517cd*4 +0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x517ce*4 +0x02000000,0x3401); +reg_write( DDR_REG_BASE +0x517cf*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x517d0*4 +0x02000000,0x7956); +reg_write( DDR_REG_BASE +0x517d1*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x517d2*4 +0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x517d3*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x517d4*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x517d5*4 +0x02000000,0x7a8); +reg_write( DDR_REG_BASE +0x517d6*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x517d7*4 +0x02000000,0xafe); +reg_write( DDR_REG_BASE +0x517d8*4 +0x02000000,0x1a0); +reg_write( DDR_REG_BASE +0x517d9*4 +0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x517da*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x517db*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x517dc*4 +0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x517dd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x517de*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x517df*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x517e0*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x517e1*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x517e2*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x517e3*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x517e4*4 +0x02000000,0x254f); +reg_write( DDR_REG_BASE +0x517e5*4 +0x02000000,0x1280); +reg_write( DDR_REG_BASE +0x517e6*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x517e7*4 +0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x517e8*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x517e9*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x517ea*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x517eb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x517ec*4 +0x02000000,0xbb8); +reg_write( DDR_REG_BASE +0x517ed*4 +0x02000000,0x906); +reg_write( DDR_REG_BASE +0x517ee*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x517ef*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x517f0*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x517f1*4 +0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x517f2*4 +0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x517f3*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x517f4*4 +0x02000000,0xb140); +reg_write( DDR_REG_BASE +0x517f5*4 +0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x517f6*4 +0x02000000,0xb140); +reg_write( DDR_REG_BASE +0x517f7*4 +0x02000000,0x8f9); +reg_write( DDR_REG_BASE +0x517f8*4 +0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x517f9*4 +0x02000000,0x254f); +reg_write( DDR_REG_BASE +0x517fa*4 +0x02000000,0x1242); +reg_write( DDR_REG_BASE +0x517fb*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x517fc*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x517fd*4 +0x02000000,0x2779); +reg_write( DDR_REG_BASE +0x517fe*4 +0x02000000,0x1042); +reg_write( DDR_REG_BASE +0x517ff*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x51800*4 +0x02000000,0x2214); +reg_write( DDR_REG_BASE +0x51801*4 +0x02000000,0x6c0); +reg_write( DDR_REG_BASE +0x51802*4 +0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x51803*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51804*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51805*4 +0x02000000,0x784); +reg_write( DDR_REG_BASE +0x51806*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51807*4 +0x02000000,0x88f); +reg_write( DDR_REG_BASE +0x51808*4 +0x02000000,0x8044); +reg_write( DDR_REG_BASE +0x51809*4 +0x02000000,0xc0a3); +reg_write( DDR_REG_BASE +0x5180a*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x5180b*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x5180c*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5180d*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5180e*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5180f*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51810*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51811*4 +0x02000000,0xc1a2); +reg_write( DDR_REG_BASE +0x51812*4 +0x02000000,0x4728); +reg_write( DDR_REG_BASE +0x51813*4 +0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x51814*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x51815*4 +0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x51816*4 +0x02000000,0xc341); +reg_write( DDR_REG_BASE +0x51817*4 +0x02000000,0xdbe); +reg_write( DDR_REG_BASE +0x51818*4 +0x02000000,0x160); +reg_write( DDR_REG_BASE +0x51819*4 +0x02000000,0x4358); +reg_write( DDR_REG_BASE +0x5181a*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5181b*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x5181c*4 +0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x5181d*4 +0x02000000,0x17c0); +reg_write( DDR_REG_BASE +0x5181e*4 +0x02000000,0xe805); +reg_write( DDR_REG_BASE +0x5181f*4 +0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x51820*4 +0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x51821*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x51822*4 +0x02000000,0x7dbb); +reg_write( DDR_REG_BASE +0x51823*4 +0x02000000,0xb15); +reg_write( DDR_REG_BASE +0x51824*4 +0x02000000,0x3031); +reg_write( DDR_REG_BASE +0x51825*4 +0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x51826*4 +0x02000000,0x110d); +reg_write( DDR_REG_BASE +0x51827*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x51828*4 +0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x51829*4 +0x02000000,0xd36); +reg_write( DDR_REG_BASE +0x5182a*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5182b*4 +0x02000000,0xdabf); +reg_write( DDR_REG_BASE +0x5182c*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5182d*4 +0x02000000,0x250f); +reg_write( DDR_REG_BASE +0x5182e*4 +0x02000000,0x139b); +reg_write( DDR_REG_BASE +0x5182f*4 +0x02000000,0xe887); +reg_write( DDR_REG_BASE +0x51830*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x51831*4 +0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x51832*4 +0x02000000,0xd22); +reg_write( DDR_REG_BASE +0x51833*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51834*4 +0x02000000,0xda7f); +reg_write( DDR_REG_BASE +0x51835*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51836*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51837*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51838*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51839*4 +0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x5183a*4 +0x02000000,0x164d); +reg_write( DDR_REG_BASE +0x5183b*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5183c*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x5183d*4 +0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x5183e*4 +0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x5183f*4 +0x02000000,0xdff); +reg_write( DDR_REG_BASE +0x51840*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x51841*4 +0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x51842*4 +0x02000000,0x60f8); +reg_write( DDR_REG_BASE +0x51843*4 +0x02000000,0x60b9); +reg_write( DDR_REG_BASE +0x51844*4 +0x02000000,0xfb6); +reg_write( DDR_REG_BASE +0x51845*4 +0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x51846*4 +0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x51847*4 +0x02000000,0x6c7); +reg_write( DDR_REG_BASE +0x51848*4 +0x02000000,0x862); +reg_write( DDR_REG_BASE +0x51849*4 +0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x5184a*4 +0x02000000,0x86a); +reg_write( DDR_REG_BASE +0x5184b*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x5184c*4 +0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x5184d*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x5184e*4 +0x02000000,0xdb6); +reg_write( DDR_REG_BASE +0x5184f*4 +0x02000000,0x160); +reg_write( DDR_REG_BASE +0x51850*4 +0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x51851*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51852*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51853*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51854*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51855*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x51856*4 +0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x51857*4 +0x02000000,0x60f8); +reg_write( DDR_REG_BASE +0x51858*4 +0x02000000,0x60b8); +reg_write( DDR_REG_BASE +0x51859*4 +0x02000000,0x1003); +reg_write( DDR_REG_BASE +0x5185a*4 +0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x5185b*4 +0x02000000,0x783d); +reg_write( DDR_REG_BASE +0x5185c*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5185d*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5185e*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5185f*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x51860*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x51861*4 +0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x51862*4 +0x02000000,0x20c5); +reg_write( DDR_REG_BASE +0x51863*4 +0x02000000,0x4ab); +reg_write( DDR_REG_BASE +0x51864*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51865*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x51866*4 +0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x51867*4 +0x02000000,0x22); +reg_write( DDR_REG_BASE +0x51868*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x51869*4 +0x02000000,0x91a); +reg_write( DDR_REG_BASE +0x5186a*4 +0x02000000,0x160); +reg_write( DDR_REG_BASE +0x5186b*4 +0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x5186c*4 +0x02000000,0xc0a2); +reg_write( DDR_REG_BASE +0x5186d*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x5186e*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x5186f*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51870*4 +0x02000000,0x7a1b); +reg_write( DDR_REG_BASE +0x51871*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51872*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51873*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51874*4 +0x02000000,0x1c); +reg_write( DDR_REG_BASE +0x51875*4 +0x02000000,0xbac4); +reg_write( DDR_REG_BASE +0x51876*4 +0x02000000,0xea05); +reg_write( DDR_REG_BASE +0x51877*4 +0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x51878*4 +0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x51879*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x5187a*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5187b*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x5187c*4 +0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x5187d*4 +0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x5187e*4 +0x02000000,0xea05); +reg_write( DDR_REG_BASE +0x5187f*4 +0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x51880*4 +0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x51881*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x51882*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51883*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x51884*4 +0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x51885*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51886*4 +0x02000000,0xc0e2); +reg_write( DDR_REG_BASE +0x51887*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51888*4 +0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x51889*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5188a*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5188b*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x5188c*4 +0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x5188d*4 +0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x5188e*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5188f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51890*4 +0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x51891*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x51892*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51893*4 +0x02000000,0x86); +reg_write( DDR_REG_BASE +0x51894*4 +0x02000000,0x9240); +reg_write( DDR_REG_BASE +0x51895*4 +0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x51896*4 +0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x51897*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51898*4 +0x02000000,0xfe86); +reg_write( DDR_REG_BASE +0x51899*4 +0x02000000,0x22c4); +reg_write( DDR_REG_BASE +0x5189a*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x5189b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5189c*4 +0x02000000,0xbfff); +reg_write( DDR_REG_BASE +0x5189d*4 +0x02000000,0xf203); +reg_write( DDR_REG_BASE +0x5189e*4 +0x02000000,0xba8e); +reg_write( DDR_REG_BASE +0x5189f*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x518a0*4 +0x02000000,0xb340); +reg_write( DDR_REG_BASE +0x518a1*4 +0x02000000,0xf01d); +reg_write( DDR_REG_BASE +0x518a2*4 +0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x518a3*4 +0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x518a4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x518a5*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x518a6*4 +0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x518a7*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x518a8*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x518a9*4 +0x02000000,0x4a); +reg_write( DDR_REG_BASE +0x518aa*4 +0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x518ab*4 +0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x518ac*4 +0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x518ad*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x518ae*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x518af*4 +0x02000000,0xe80b); +reg_write( DDR_REG_BASE +0x518b0*4 +0x02000000,0x9340); +reg_write( DDR_REG_BASE +0x518b1*4 +0x02000000,0x2114); +reg_write( DDR_REG_BASE +0x518b2*4 +0x02000000,0x34c); +reg_write( DDR_REG_BASE +0x518b3*4 +0x02000000,0xb440); +reg_write( DDR_REG_BASE +0x518b4*4 +0x02000000,0x2204); +reg_write( DDR_REG_BASE +0x518b5*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x518b6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x518b7*4 +0x02000000,0xfbff); +reg_write( DDR_REG_BASE +0x518b8*4 +0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x518b9*4 +0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x518ba*4 +0x02000000,0x342); +reg_write( DDR_REG_BASE +0x518bb*4 +0x02000000,0xb340); +reg_write( DDR_REG_BASE +0x518bc*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x518bd*4 +0x02000000,0xdcd); +reg_write( DDR_REG_BASE +0x518be*4 +0x02000000,0x9294); +reg_write( DDR_REG_BASE +0x518bf*4 +0x02000000,0xc4c2); +reg_write( DDR_REG_BASE +0x518c0*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x518c1*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x518c2*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x518c3*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x518c4*4 +0x02000000,0x7cf); +reg_write( DDR_REG_BASE +0x518c5*4 +0x02000000,0xdd24); +reg_write( DDR_REG_BASE +0x518c6*4 +0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x518c7*4 +0x02000000,0xbd9f); +reg_write( DDR_REG_BASE +0x518c8*4 +0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x518c9*4 +0x02000000,0xe007); +reg_write( DDR_REG_BASE +0x518ca*4 +0x02000000,0x7a1d); +reg_write( DDR_REG_BASE +0x518cb*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x518cc*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x518cd*4 +0x02000000,0x6a09); +reg_write( DDR_REG_BASE +0x518ce*4 +0x02000000,0xa901); +reg_write( DDR_REG_BASE +0x518cf*4 +0x02000000,0x1534); +reg_write( DDR_REG_BASE +0x518d0*4 +0x02000000,0x108c); +reg_write( DDR_REG_BASE +0x518d1*4 +0x02000000,0xec0e); +reg_write( DDR_REG_BASE +0x518d2*4 +0x02000000,0xca02); +reg_write( DDR_REG_BASE +0x518d3*4 +0x02000000,0x7a1d); +reg_write( DDR_REG_BASE +0x518d4*4 +0x02000000,0xa942); +reg_write( DDR_REG_BASE +0x518d5*4 +0x02000000,0x1533); +reg_write( DDR_REG_BASE +0x518d6*4 +0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x518d7*4 +0x02000000,0xe007); +reg_write( DDR_REG_BASE +0x518d8*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x518d9*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x518da*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x518db*4 +0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x518dc*4 +0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x518dd*4 +0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x518de*4 +0x02000000,0xa942); +reg_write( DDR_REG_BASE +0x518df*4 +0x02000000,0xa903); +reg_write( DDR_REG_BASE +0x518e0*4 +0x02000000,0xf01e); +reg_write( DDR_REG_BASE +0x518e1*4 +0x02000000,0xee05); +reg_write( DDR_REG_BASE +0x518e2*4 +0x02000000,0x1533); +reg_write( DDR_REG_BASE +0x518e3*4 +0x02000000,0x108f); +reg_write( DDR_REG_BASE +0x518e4*4 +0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x518e5*4 +0x02000000,0x8de0); +reg_write( DDR_REG_BASE +0x518e6*4 +0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x518e7*4 +0x02000000,0xf16); +reg_write( DDR_REG_BASE +0x518e8*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x518e9*4 +0x02000000,0x796f); +reg_write( DDR_REG_BASE +0x518ea*4 +0x02000000,0xe804); +reg_write( DDR_REG_BASE +0x518eb*4 +0x02000000,0x6f07); +reg_write( DDR_REG_BASE +0x518ec*4 +0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x518ed*4 +0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x518ee*4 +0x02000000,0x4f1f); +reg_write( DDR_REG_BASE +0x518ef*4 +0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x518f0*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x518f1*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x518f2*4 +0x02000000,0x2314); +reg_write( DDR_REG_BASE +0x518f3*4 +0x02000000,0x380); +reg_write( DDR_REG_BASE +0x518f4*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x518f5*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x518f6*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x518f7*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x518f8*4 +0x02000000,0x784); +reg_write( DDR_REG_BASE +0x518f9*4 +0x02000000,0xa820); +reg_write( DDR_REG_BASE +0x518fa*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x518fb*4 +0x02000000,0xecf); +reg_write( DDR_REG_BASE +0x518fc*4 +0x02000000,0x9094); +reg_write( DDR_REG_BASE +0x518fd*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x518fe*4 +0x02000000,0xbfb); +reg_write( DDR_REG_BASE +0x518ff*4 +0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x51900*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x51901*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51902*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51903*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51904*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51905*4 +0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x51906*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51907*4 +0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x51908*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x51909*4 +0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x5190a*4 +0x02000000,0x17c0); +reg_write( DDR_REG_BASE +0x5190b*4 +0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x5190c*4 +0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x5190d*4 +0x02000000,0x801); +reg_write( DDR_REG_BASE +0x5190e*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x5190f*4 +0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x51910*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51911*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51912*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51913*4 +0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x51914*4 +0x02000000,0x817); +reg_write( DDR_REG_BASE +0x51915*4 +0x02000000,0x70); +reg_write( DDR_REG_BASE +0x51916*4 +0x02000000,0x4748); +reg_write( DDR_REG_BASE +0x51917*4 +0x02000000,0x73ad); +reg_write( DDR_REG_BASE +0x51918*4 +0x02000000,0xe88f); +reg_write( DDR_REG_BASE +0x51919*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5191a*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5191b*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5191c*4 +0x02000000,0x25); +reg_write( DDR_REG_BASE +0x5191d*4 +0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x5191e*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x5191f*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51920*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51921*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51922*4 +0x02000000,0x58); +reg_write( DDR_REG_BASE +0x51923*4 +0x02000000,0x72ad); +reg_write( DDR_REG_BASE +0x51924*4 +0x02000000,0x790b); +reg_write( DDR_REG_BASE +0x51925*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51926*4 +0x02000000,0xf212); +reg_write( DDR_REG_BASE +0x51927*4 +0x02000000,0xc42); +reg_write( DDR_REG_BASE +0x51928*4 +0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x51929*4 +0x02000000,0x8c6); +reg_write( DDR_REG_BASE +0x5192a*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5192b*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x5192c*4 +0x02000000,0xb5a); +reg_write( DDR_REG_BASE +0x5192d*4 +0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x5192e*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5192f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51930*4 +0x02000000,0x7d8); +reg_write( DDR_REG_BASE +0x51931*4 +0x02000000,0x8020); +reg_write( DDR_REG_BASE +0x51932*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x51933*4 +0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x51934*4 +0x02000000,0xdb6); +reg_write( DDR_REG_BASE +0x51935*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51936*4 +0x02000000,0x43e1); +reg_write( DDR_REG_BASE +0x51937*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51938*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x51939*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x5193a*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5193b*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5193c*4 +0x02000000,0x4833); +reg_write( DDR_REG_BASE +0x5193d*4 +0x02000000,0x4910); +reg_write( DDR_REG_BASE +0x5193e*4 +0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x5193f*4 +0x02000000,0x2348); +reg_write( DDR_REG_BASE +0x51940*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x51941*4 +0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x51942*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51943*4 +0x02000000,0x7b6e); +reg_write( DDR_REG_BASE +0x51944*4 +0x02000000,0x780e); +reg_write( DDR_REG_BASE +0x51945*4 +0x02000000,0x2309); +reg_write( DDR_REG_BASE +0x51946*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51947*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x51948*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51949*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5194a*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x5194b*4 +0x02000000,0x956); +reg_write( DDR_REG_BASE +0x5194c*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x5194d*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x5194e*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x5194f*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51950*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51951*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51952*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51953*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51954*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x51955*4 +0x02000000,0x1e8); +reg_write( DDR_REG_BASE +0x51956*4 +0x02000000,0x9020); +reg_write( DDR_REG_BASE +0x51957*4 +0x02000000,0x2059); +reg_write( DDR_REG_BASE +0x51958*4 +0x02000000,0xf40); +reg_write( DDR_REG_BASE +0x51959*4 +0x02000000,0x7724); +reg_write( DDR_REG_BASE +0x5195a*4 +0x02000000,0x7930); +reg_write( DDR_REG_BASE +0x5195b*4 +0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x5195c*4 +0x02000000,0x2155); +reg_write( DDR_REG_BASE +0x5195d*4 +0x02000000,0xc0d); +reg_write( DDR_REG_BASE +0x5195e*4 +0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x5195f*4 +0x02000000,0xe); +reg_write( DDR_REG_BASE +0x51960*4 +0x02000000,0x7d05); +reg_write( DDR_REG_BASE +0x51961*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51962*4 +0x02000000,0x111b); +reg_write( DDR_REG_BASE +0x51963*4 +0x02000000,0x95e0); +reg_write( DDR_REG_BASE +0x51964*4 +0x02000000,0x83a); +reg_write( DDR_REG_BASE +0x51965*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51966*4 +0x02000000,0xd896); +reg_write( DDR_REG_BASE +0x51967*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51968*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51969*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5196a*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5196b*4 +0x02000000,0x6822); +reg_write( DDR_REG_BASE +0x5196c*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5196d*4 +0x02000000,0xb8e0); +reg_write( DDR_REG_BASE +0x5196e*4 +0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x5196f*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51970*4 +0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x51971*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51972*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51973*4 +0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x51974*4 +0x02000000,0x2304); +reg_write( DDR_REG_BASE +0x51975*4 +0x02000000,0x305b); +reg_write( DDR_REG_BASE +0x51976*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51977*4 +0x02000000,0x6c0); +reg_write( DDR_REG_BASE +0x51978*4 +0x02000000,0x79e4); +reg_write( DDR_REG_BASE +0x51979*4 +0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x5197a*4 +0x02000000,0x2145); +reg_write( DDR_REG_BASE +0x5197b*4 +0x02000000,0x3c0); +reg_write( DDR_REG_BASE +0x5197c*4 +0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x5197d*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x5197e*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x5197f*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51980*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51981*4 +0x02000000,0x7101); +reg_write( DDR_REG_BASE +0x51982*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51983*4 +0x02000000,0x6); +reg_write( DDR_REG_BASE +0x51984*4 +0x02000000,0x790c); +reg_write( DDR_REG_BASE +0x51985*4 +0x02000000,0x2985); +reg_write( DDR_REG_BASE +0x51986*4 +0x02000000,0x41f); +reg_write( DDR_REG_BASE +0x51987*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x51988*4 +0x02000000,0x6901); +reg_write( DDR_REG_BASE +0x51989*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5198a*4 +0x02000000,0x2042); +reg_write( DDR_REG_BASE +0x5198b*4 +0x02000000,0x701); +reg_write( DDR_REG_BASE +0x5198c*4 +0x02000000,0x939); +reg_write( DDR_REG_BASE +0x5198d*4 +0x02000000,0x454); +reg_write( DDR_REG_BASE +0x5198e*4 +0x02000000,0x889); +reg_write( DDR_REG_BASE +0x5198f*4 +0x02000000,0xc30); +reg_write( DDR_REG_BASE +0x51990*4 +0x02000000,0xd91a); +reg_write( DDR_REG_BASE +0x51991*4 +0x02000000,0x885); +reg_write( DDR_REG_BASE +0x51992*4 +0x02000000,0xd70); +reg_write( DDR_REG_BASE +0x51993*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x51994*4 +0x02000000,0x87d); +reg_write( DDR_REG_BASE +0x51995*4 +0x02000000,0xf30); +reg_write( DDR_REG_BASE +0x51996*4 +0x02000000,0xd918); +reg_write( DDR_REG_BASE +0x51997*4 +0x02000000,0xe0c5); +reg_write( DDR_REG_BASE +0x51998*4 +0x02000000,0xf227); +reg_write( DDR_REG_BASE +0x51999*4 +0x02000000,0xe0d0); +reg_write( DDR_REG_BASE +0x5199a*4 +0x02000000,0xf227); +reg_write( DDR_REG_BASE +0x5199b*4 +0x02000000,0xe0e0); +reg_write( DDR_REG_BASE +0x5199c*4 +0x02000000,0xf227); +reg_write( DDR_REG_BASE +0x5199d*4 +0x02000000,0xe0f8); +reg_write( DDR_REG_BASE +0x5199e*4 +0x02000000,0xf227); +reg_write( DDR_REG_BASE +0x5199f*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x519a0*4 +0x02000000,0x8c03); +reg_write( DDR_REG_BASE +0x519a1*4 +0x02000000,0x722c); +reg_write( DDR_REG_BASE +0x519a2*4 +0x02000000,0xf230); +reg_write( DDR_REG_BASE +0x519a3*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x519a4*4 +0x02000000,0x8802); +reg_write( DDR_REG_BASE +0x519a5*4 +0x02000000,0xf419); +reg_write( DDR_REG_BASE +0x519a6*4 +0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x519a7*4 +0x02000000,0xf02c); +reg_write( DDR_REG_BASE +0x519a8*4 +0x02000000,0x2025); +reg_write( DDR_REG_BASE +0x519a9*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x519aa*4 +0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x519ab*4 +0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x519ac*4 +0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x519ad*4 +0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x519ae*4 +0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x519af*4 +0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x519b0*4 +0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x519b1*4 +0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x519b2*4 +0x02000000,0xf00b); +reg_write( DDR_REG_BASE +0x519b3*4 +0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x519b4*4 +0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x519b5*4 +0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x519b6*4 +0x02000000,0xf019); +reg_write( DDR_REG_BASE +0x519b7*4 +0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x519b8*4 +0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x519b9*4 +0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x519ba*4 +0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x519bb*4 +0x02000000,0xd93f); +reg_write( DDR_REG_BASE +0x519bc*4 +0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x519bd*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x519be*4 +0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x519bf*4 +0x02000000,0xd90b); +reg_write( DDR_REG_BASE +0x519c0*4 +0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x519c1*4 +0x02000000,0xd90a); +reg_write( DDR_REG_BASE +0x519c2*4 +0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x519c3*4 +0x02000000,0xd907); +reg_write( DDR_REG_BASE +0x519c4*4 +0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x519c5*4 +0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x519c6*4 +0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x519c7*4 +0x02000000,0xd93e); +reg_write( DDR_REG_BASE +0x519c8*4 +0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x519c9*4 +0x02000000,0xd93b); +reg_write( DDR_REG_BASE +0x519ca*4 +0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x519cb*4 +0x02000000,0xd93a); +reg_write( DDR_REG_BASE +0x519cc*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x519cd*4 +0x02000000,0xd91f); +reg_write( DDR_REG_BASE +0x519ce*4 +0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x519cf*4 +0x02000000,0xd938); +reg_write( DDR_REG_BASE +0x519d0*4 +0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x519d1*4 +0x02000000,0xd91b); +reg_write( DDR_REG_BASE +0x519d2*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x519d3*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x519d4*4 +0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x519d5*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x519d6*4 +0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x519d7*4 +0x02000000,0x265a); +reg_write( DDR_REG_BASE +0x519d8*4 +0x02000000,0x3c83); +reg_write( DDR_REG_BASE +0x519d9*4 +0x02000000,0x607c); +reg_write( DDR_REG_BASE +0x519da*4 +0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x519db*4 +0x02000000,0x1643); +reg_write( DDR_REG_BASE +0x519dc*4 +0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x519dd*4 +0x02000000,0x639b); +reg_write( DDR_REG_BASE +0x519de*4 +0x02000000,0x633b); +reg_write( DDR_REG_BASE +0x519df*4 +0x02000000,0x8b80); +reg_write( DDR_REG_BASE +0x519e0*4 +0x02000000,0x7c45); +reg_write( DDR_REG_BASE +0x519e1*4 +0x02000000,0xab80); +reg_write( DDR_REG_BASE +0x519e2*4 +0x02000000,0xbeb); +reg_write( DDR_REG_BASE +0x519e3*4 +0x02000000,0x9094); +reg_write( DDR_REG_BASE +0x519e4*4 +0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x519e5*4 +0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x519e6*4 +0x02000000,0xef9); +reg_write( DDR_REG_BASE +0x519e7*4 +0x02000000,0xb0b4); +reg_write( DDR_REG_BASE +0x519e8*4 +0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x519e9*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x519ea*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x519eb*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x519ec*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x519ed*4 +0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x519ee*4 +0x02000000,0x3a0d); +reg_write( DDR_REG_BASE +0x519ef*4 +0x02000000,0xe76); +reg_write( DDR_REG_BASE +0x519f0*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x519f1*4 +0x02000000,0xc083); +reg_write( DDR_REG_BASE +0x519f2*4 +0x02000000,0xc083); +reg_write( DDR_REG_BASE +0x519f3*4 +0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x519f4*4 +0x02000000,0xfc2); +reg_write( DDR_REG_BASE +0x519f5*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x519f6*4 +0x02000000,0xdac8); +reg_write( DDR_REG_BASE +0x519f7*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x519f8*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x519f9*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x519fa*4 +0x02000000,0x1b); +reg_write( DDR_REG_BASE +0x519fb*4 +0x02000000,0x899); +reg_write( DDR_REG_BASE +0x519fc*4 +0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x519fd*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x519fe*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x519ff*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51a00*4 +0x02000000,0x880e); +reg_write( DDR_REG_BASE +0x51a01*4 +0x02000000,0x88d); +reg_write( DDR_REG_BASE +0x51a02*4 +0x02000000,0x30); +reg_write( DDR_REG_BASE +0x51a03*4 +0x02000000,0xdb4b); +reg_write( DDR_REG_BASE +0x51a04*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51a05*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a06*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51a07*4 +0x02000000,0x888d); +reg_write( DDR_REG_BASE +0x51a08*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51a09*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a0a*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51a0b*4 +0x02000000,0x88ac); +reg_write( DDR_REG_BASE +0x51a0c*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51a0d*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a0e*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51a0f*4 +0x02000000,0x88cb); +reg_write( DDR_REG_BASE +0x51a10*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51a11*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a12*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51a13*4 +0x02000000,0x882a); +reg_write( DDR_REG_BASE +0x51a14*4 +0x02000000,0xbb9f); +reg_write( DDR_REG_BASE +0x51a15*4 +0x02000000,0x1b01); +reg_write( DDR_REG_BASE +0x51a16*4 +0x02000000,0x52); +reg_write( DDR_REG_BASE +0x51a17*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51a18*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a19*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51a1a*4 +0x02000000,0x88eb); +reg_write( DDR_REG_BASE +0x51a1b*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51a1c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a1d*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51a1e*4 +0x02000000,0xabe0); +reg_write( DDR_REG_BASE +0x51a1f*4 +0x02000000,0x884c); +reg_write( DDR_REG_BASE +0x51a20*4 +0x02000000,0x279a); +reg_write( DDR_REG_BASE +0x51a21*4 +0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x51a22*4 +0x02000000,0x1b32); +reg_write( DDR_REG_BASE +0x51a23*4 +0x02000000,0x82); +reg_write( DDR_REG_BASE +0x51a24*4 +0x02000000,0xc166); +reg_write( DDR_REG_BASE +0x51a25*4 +0x02000000,0x1c31); +reg_write( DDR_REG_BASE +0x51a26*4 +0x02000000,0x3382); +reg_write( DDR_REG_BASE +0x51a27*4 +0x02000000,0x1c4a); +reg_write( DDR_REG_BASE +0x51a28*4 +0x02000000,0x3342); +reg_write( DDR_REG_BASE +0x51a29*4 +0x02000000,0x1c63); +reg_write( DDR_REG_BASE +0x51a2a*4 +0x02000000,0x3302); +reg_write( DDR_REG_BASE +0x51a2b*4 +0x02000000,0x13b8); +reg_write( DDR_REG_BASE +0x51a2c*4 +0x02000000,0x8080); +reg_write( DDR_REG_BASE +0x51a2d*4 +0x02000000,0x7f25); +reg_write( DDR_REG_BASE +0x51a2e*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51a2f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a30*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51a31*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x51a32*4 +0x02000000,0x18d); +reg_write( DDR_REG_BASE +0x51a33*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51a34*4 +0x02000000,0x12); +reg_write( DDR_REG_BASE +0x51a35*4 +0x02000000,0x310); +reg_write( DDR_REG_BASE +0x51a36*4 +0x02000000,0x892d); +reg_write( DDR_REG_BASE +0x51a37*4 +0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x51a38*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51a39*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a3a*4 +0x02000000,0x65d8); +reg_write( DDR_REG_BASE +0x51a3b*4 +0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x51a3c*4 +0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x51a3d*4 +0x02000000,0x1b33); +reg_write( DDR_REG_BASE +0x51a3e*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x51a3f*4 +0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x51a40*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51a41*4 +0x02000000,0x6e02); +reg_write( DDR_REG_BASE +0x51a42*4 +0x02000000,0x60b8); +reg_write( DDR_REG_BASE +0x51a43*4 +0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x51a44*4 +0x02000000,0x7945); +reg_write( DDR_REG_BASE +0x51a45*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51a46*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51a47*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x51a48*4 +0x02000000,0xc083); +reg_write( DDR_REG_BASE +0x51a49*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51a4a*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x51a4b*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x51a4c*4 +0x02000000,0x5800); +reg_write( DDR_REG_BASE +0x51a4d*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x51a4e*4 +0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x51a4f*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x51a50*4 +0x02000000,0xc4e); +reg_write( DDR_REG_BASE +0x51a51*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a52*4 +0x02000000,0x9ea); +reg_write( DDR_REG_BASE +0x51a53*4 +0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x51a54*4 +0x02000000,0xc96); +reg_write( DDR_REG_BASE +0x51a55*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x51a56*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51a57*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51a58*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x51a59*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51a5a*4 +0x02000000,0xdc); +reg_write( DDR_REG_BASE +0x51a5b*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51a5c*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51a5d*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a5e*4 +0x02000000,0x19); +reg_write( DDR_REG_BASE +0x51a5f*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51a60*4 +0x02000000,0x2f6); +reg_write( DDR_REG_BASE +0x51a61*4 +0x02000000,0x22); +reg_write( DDR_REG_BASE +0x51a62*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51a63*4 +0x02000000,0x2e3); +reg_write( DDR_REG_BASE +0x51a64*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a65*4 +0x02000000,0xe90b); +reg_write( DDR_REG_BASE +0x51a66*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51a67*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51a68*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a69*4 +0x02000000,0x58); +reg_write( DDR_REG_BASE +0x51a6a*4 +0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x51a6b*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51a6c*4 +0x02000000,0xf40b); +reg_write( DDR_REG_BASE +0x51a6d*4 +0x02000000,0x2cd); +reg_write( DDR_REG_BASE +0x51a6e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a6f*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51a70*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51a71*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a72*4 +0x02000000,0x25); +reg_write( DDR_REG_BASE +0x51a73*4 +0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x51a74*4 +0x02000000,0x2bc); +reg_write( DDR_REG_BASE +0x51a75*4 +0x02000000,0x21); +reg_write( DDR_REG_BASE +0x51a76*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51a77*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x51a78*4 +0x02000000,0xe26); +reg_write( DDR_REG_BASE +0x51a79*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51a7a*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51a7b*4 +0x02000000,0x216f); +reg_write( DDR_REG_BASE +0x51a7c*4 +0x02000000,0xc3); +reg_write( DDR_REG_BASE +0x51a7d*4 +0x02000000,0x1100); +reg_write( DDR_REG_BASE +0x51a7e*4 +0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x51a7f*4 +0x02000000,0x89c3); +reg_write( DDR_REG_BASE +0x51a80*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51a81*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51a82*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51a83*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x51a84*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a85*4 +0x02000000,0x2c8); +reg_write( DDR_REG_BASE +0x51a86*4 +0x02000000,0xece); +reg_write( DDR_REG_BASE +0x51a87*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51a88*4 +0x02000000,0xdaa0); +reg_write( DDR_REG_BASE +0x51a89*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51a8a*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x51a8b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a8c*4 +0x02000000,0x228); +reg_write( DDR_REG_BASE +0x51a8d*4 +0x02000000,0xec2); +reg_write( DDR_REG_BASE +0x51a8e*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51a8f*4 +0x02000000,0xdaa0); +reg_write( DDR_REG_BASE +0x51a90*4 +0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x51a91*4 +0x02000000,0x3c40); +reg_write( DDR_REG_BASE +0x51a92*4 +0x02000000,0xeb6); +reg_write( DDR_REG_BASE +0x51a93*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51a94*4 +0x02000000,0xdaa0); +reg_write( DDR_REG_BASE +0x51a95*4 +0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51a96*4 +0x02000000,0x3e80); +reg_write( DDR_REG_BASE +0x51a97*4 +0x02000000,0xeae); +reg_write( DDR_REG_BASE +0x51a98*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51a99*4 +0x02000000,0xdaa0); +reg_write( DDR_REG_BASE +0x51a9a*4 +0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x51a9b*4 +0x02000000,0x1f8e); +reg_write( DDR_REG_BASE +0x51a9c*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x51a9d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a9e*4 +0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x51a9f*4 +0x02000000,0xf064); +reg_write( DDR_REG_BASE +0x51aa0*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51aa1*4 +0x02000000,0xe9a); +reg_write( DDR_REG_BASE +0x51aa2*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51aa3*4 +0x02000000,0xda28); +reg_write( DDR_REG_BASE +0x51aa4*4 +0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51aa5*4 +0x02000000,0x3980); +reg_write( DDR_REG_BASE +0x51aa6*4 +0x02000000,0xe8e); +reg_write( DDR_REG_BASE +0x51aa7*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51aa8*4 +0x02000000,0xda28); +reg_write( DDR_REG_BASE +0x51aa9*4 +0x02000000,0xc09c); +reg_write( DDR_REG_BASE +0x51aaa*4 +0x02000000,0xe86); +reg_write( DDR_REG_BASE +0x51aab*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51aac*4 +0x02000000,0xda28); +reg_write( DDR_REG_BASE +0x51aad*4 +0x02000000,0x2355); +reg_write( DDR_REG_BASE +0x51aae*4 +0x02000000,0x3800); +reg_write( DDR_REG_BASE +0x51aaf*4 +0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x51ab0*4 +0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51ab1*4 +0x02000000,0x3c01); +reg_write( DDR_REG_BASE +0x51ab2*4 +0x02000000,0xa8a); +reg_write( DDR_REG_BASE +0x51ab3*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51ab4*4 +0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x51ab5*4 +0x02000000,0x2355); +reg_write( DDR_REG_BASE +0x51ab6*4 +0x02000000,0x38c0); +reg_write( DDR_REG_BASE +0x51ab7*4 +0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x51ab8*4 +0x02000000,0xa7e); +reg_write( DDR_REG_BASE +0x51ab9*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51aba*4 +0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51abb*4 +0x02000000,0x3981); +reg_write( DDR_REG_BASE +0x51abc*4 +0x02000000,0x2355); +reg_write( DDR_REG_BASE +0x51abd*4 +0x02000000,0x3d00); +reg_write( DDR_REG_BASE +0x51abe*4 +0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x51abf*4 +0x02000000,0xa72); +reg_write( DDR_REG_BASE +0x51ac0*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51ac1*4 +0x02000000,0xc19c); +reg_write( DDR_REG_BASE +0x51ac2*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51ac3*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51ac4*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51ac5*4 +0x02000000,0x1003); +reg_write( DDR_REG_BASE +0x51ac6*4 +0x02000000,0x8b); +reg_write( DDR_REG_BASE +0x51ac7*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51ac8*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51ac9*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51aca*4 +0x02000000,0x8862); +reg_write( DDR_REG_BASE +0x51acb*4 +0x02000000,0xf035); +reg_write( DDR_REG_BASE +0x51acc*4 +0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51acd*4 +0x02000000,0x3c00); +reg_write( DDR_REG_BASE +0x51ace*4 +0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x51acf*4 +0x02000000,0xde); +reg_write( DDR_REG_BASE +0x51ad0*4 +0x02000000,0x94e); +reg_write( DDR_REG_BASE +0x51ad1*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51ad2*4 +0x02000000,0x200a); +reg_write( DDR_REG_BASE +0x51ad3*4 +0x02000000,0x780); +reg_write( DDR_REG_BASE +0x51ad4*4 +0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x51ad5*4 +0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51ad6*4 +0x02000000,0x3980); +reg_write( DDR_REG_BASE +0x51ad7*4 +0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x51ad8*4 +0x02000000,0xcd); +reg_write( DDR_REG_BASE +0x51ad9*4 +0x02000000,0xc09c); +reg_write( DDR_REG_BASE +0x51ada*4 +0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x51adb*4 +0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x51adc*4 +0x02000000,0xbdc5); +reg_write( DDR_REG_BASE +0x51add*4 +0x02000000,0x936); +reg_write( DDR_REG_BASE +0x51ade*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51adf*4 +0x02000000,0x65fd); +reg_write( DDR_REG_BASE +0x51ae0*4 +0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x51ae1*4 +0x02000000,0x3a02); +reg_write( DDR_REG_BASE +0x51ae2*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51ae3*4 +0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x51ae4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51ae5*4 +0x02000000,0x2c8); +reg_write( DDR_REG_BASE +0x51ae6*4 +0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x51ae7*4 +0x02000000,0x7974); +reg_write( DDR_REG_BASE +0x51ae8*4 +0x02000000,0xb1a0); +reg_write( DDR_REG_BASE +0x51ae9*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51aea*4 +0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x51aeb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51aec*4 +0x02000000,0x228); +reg_write( DDR_REG_BASE +0x51aed*4 +0x02000000,0x615c); +reg_write( DDR_REG_BASE +0x51aee*4 +0x02000000,0x212f); +reg_write( DDR_REG_BASE +0x51aef*4 +0x02000000,0x782); +reg_write( DDR_REG_BASE +0x51af0*4 +0x02000000,0x7c74); +reg_write( DDR_REG_BASE +0x51af1*4 +0x02000000,0x216c); +reg_write( DDR_REG_BASE +0x51af2*4 +0x02000000,0x101); +reg_write( DDR_REG_BASE +0x51af3*4 +0x02000000,0xb420); +reg_write( DDR_REG_BASE +0x51af4*4 +0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x51af5*4 +0x02000000,0x3c41); +reg_write( DDR_REG_BASE +0x51af6*4 +0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x51af7*4 +0x02000000,0x7974); +reg_write( DDR_REG_BASE +0x51af8*4 +0x02000000,0xb1e0); +reg_write( DDR_REG_BASE +0x51af9*4 +0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51afa*4 +0x02000000,0x3e81); +reg_write( DDR_REG_BASE +0x51afb*4 +0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x51afc*4 +0x02000000,0x7974); +reg_write( DDR_REG_BASE +0x51afd*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x51afe*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x51aff*4 +0x02000000,0xb9d); +reg_write( DDR_REG_BASE +0x51b00*4 +0x02000000,0x90c5); +reg_write( DDR_REG_BASE +0x51b01*4 +0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x51b02*4 +0x02000000,0xb3d); +reg_write( DDR_REG_BASE +0x51b03*4 +0x02000000,0xb134); +reg_write( DDR_REG_BASE +0x51b04*4 +0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51b05*4 +0x02000000,0x3c00); +reg_write( DDR_REG_BASE +0x51b06*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51b07*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51b08*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51b09*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51b0a*4 +0x02000000,0xd930); +reg_write( DDR_REG_BASE +0x51b0b*4 +0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x51b0c*4 +0x02000000,0x2140); +reg_write( DDR_REG_BASE +0x51b0d*4 +0x02000000,0xcce); +reg_write( DDR_REG_BASE +0x51b0e*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51b0f*4 +0x02000000,0x2642); +reg_write( DDR_REG_BASE +0x51b10*4 +0x02000000,0x1283); +reg_write( DDR_REG_BASE +0x51b11*4 +0x02000000,0x2142); +reg_write( DDR_REG_BASE +0x51b12*4 +0x02000000,0x280); +reg_write( DDR_REG_BASE +0x51b13*4 +0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x51b14*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51b15*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51b16*4 +0x02000000,0x26ca); +reg_write( DDR_REG_BASE +0x51b17*4 +0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x51b18*4 +0x02000000,0x4308); +reg_write( DDR_REG_BASE +0x51b19*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51b1a*4 +0x02000000,0xf059); +reg_write( DDR_REG_BASE +0x51b1b*4 +0x02000000,0xdab); +reg_write( DDR_REG_BASE +0x51b1c*4 +0x02000000,0x12e0); +reg_write( DDR_REG_BASE +0x51b1d*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51b1e*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51b1f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51b20*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51b21*4 +0x02000000,0x1003); +reg_write( DDR_REG_BASE +0x51b22*4 +0x02000000,0x9f); +reg_write( DDR_REG_BASE +0x51b23*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51b24*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51b25*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51b26*4 +0x02000000,0x8882); +reg_write( DDR_REG_BASE +0x51b27*4 +0x02000000,0xba8f); +reg_write( DDR_REG_BASE +0x51b28*4 +0x02000000,0x4358); +reg_write( DDR_REG_BASE +0x51b29*4 +0x02000000,0xf02e); +reg_write( DDR_REG_BASE +0x51b2a*4 +0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x51b2b*4 +0x02000000,0x1a0f); +reg_write( DDR_REG_BASE +0x51b2c*4 +0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x51b2d*4 +0x02000000,0x923); +reg_write( DDR_REG_BASE +0x51b2e*4 +0x02000000,0x32); +reg_write( DDR_REG_BASE +0x51b2f*4 +0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x51b30*4 +0x02000000,0x1a00); +reg_write( DDR_REG_BASE +0x51b31*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51b32*4 +0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x51b33*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51b34*4 +0x02000000,0x228); +reg_write( DDR_REG_BASE +0x51b35*4 +0x02000000,0x61f9); +reg_write( DDR_REG_BASE +0x51b36*4 +0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x51b37*4 +0x02000000,0x302); +reg_write( DDR_REG_BASE +0x51b38*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51b39*4 +0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x51b3a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51b3b*4 +0x02000000,0x2c8); +reg_write( DDR_REG_BASE +0x51b3c*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x51b3d*4 +0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x51b3e*4 +0x02000000,0x3c41); +reg_write( DDR_REG_BASE +0x51b3f*4 +0x02000000,0x61fa); +reg_write( DDR_REG_BASE +0x51b40*4 +0x02000000,0x22f4); +reg_write( DDR_REG_BASE +0x51b41*4 +0x02000000,0x302); +reg_write( DDR_REG_BASE +0x51b42*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x51b43*4 +0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x51b44*4 +0x02000000,0x301); +reg_write( DDR_REG_BASE +0x51b45*4 +0x02000000,0x7942); +reg_write( DDR_REG_BASE +0x51b46*4 +0x02000000,0x2608); +reg_write( DDR_REG_BASE +0x51b47*4 +0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x51b48*4 +0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51b49*4 +0x02000000,0x3e81); +reg_write( DDR_REG_BASE +0x51b4a*4 +0x02000000,0x673f); +reg_write( DDR_REG_BASE +0x51b4b*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51b4c*4 +0x02000000,0x27f4); +reg_write( DDR_REG_BASE +0x51b4d*4 +0x02000000,0x130f); +reg_write( DDR_REG_BASE +0x51b4e*4 +0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x51b4f*4 +0x02000000,0x300); +reg_write( DDR_REG_BASE +0x51b50*4 +0x02000000,0x212f); +reg_write( DDR_REG_BASE +0x51b51*4 +0x02000000,0x6c6); +reg_write( DDR_REG_BASE +0x51b52*4 +0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x51b53*4 +0x02000000,0x78e2); +reg_write( DDR_REG_BASE +0x51b54*4 +0x02000000,0x2108); +reg_write( DDR_REG_BASE +0x51b55*4 +0x02000000,0x1b); +reg_write( DDR_REG_BASE +0x51b56*4 +0x02000000,0xfa9); +reg_write( DDR_REG_BASE +0x51b57*4 +0x02000000,0xb325); +reg_write( DDR_REG_BASE +0x51b58*4 +0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x51b59*4 +0x02000000,0x3086); +reg_write( DDR_REG_BASE +0x51b5a*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51b5b*4 +0x02000000,0x811); +reg_write( DDR_REG_BASE +0x51b5c*4 +0x02000000,0x32); +reg_write( DDR_REG_BASE +0x51b5d*4 +0x02000000,0x200a); +reg_write( DDR_REG_BASE +0x51b5e*4 +0x02000000,0x780); +reg_write( DDR_REG_BASE +0x51b5f*4 +0x02000000,0xf9e); +reg_write( DDR_REG_BASE +0x51b60*4 +0x02000000,0xfe8f); +reg_write( DDR_REG_BASE +0x51b61*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x51b62*4 +0x02000000,0xf1e); +reg_write( DDR_REG_BASE +0x51b63*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51b64*4 +0x02000000,0x200a); +reg_write( DDR_REG_BASE +0x51b65*4 +0x02000000,0x780); +reg_write( DDR_REG_BASE +0x51b66*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x51b67*4 +0x02000000,0xf16); +reg_write( DDR_REG_BASE +0x51b68*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51b69*4 +0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x51b6a*4 +0x02000000,0x6c6); +reg_write( DDR_REG_BASE +0x51b6b*4 +0x02000000,0x1b01); +reg_write( DDR_REG_BASE +0x51b6c*4 +0x02000000,0x52); +reg_write( DDR_REG_BASE +0x51b6d*4 +0x02000000,0x1e01); +reg_write( DDR_REG_BASE +0x51b6e*4 +0x02000000,0x1012); +reg_write( DDR_REG_BASE +0x51b6f*4 +0x02000000,0x77a5); +reg_write( DDR_REG_BASE +0x51b70*4 +0x02000000,0xd57); +reg_write( DDR_REG_BASE +0x51b71*4 +0x02000000,0x9013); +reg_write( DDR_REG_BASE +0x51b72*4 +0x02000000,0x7765); +reg_write( DDR_REG_BASE +0x51b73*4 +0x02000000,0xbfd); +reg_write( DDR_REG_BASE +0x51b74*4 +0x02000000,0x9033); +reg_write( DDR_REG_BASE +0x51b75*4 +0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x51b76*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51b77*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51b78*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51b79*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51b7a*4 +0x02000000,0xd92c); +reg_write( DDR_REG_BASE +0x51b7b*4 +0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x51b7c*4 +0x02000000,0x2140); +reg_write( DDR_REG_BASE +0x51b7d*4 +0x02000000,0xccb); +reg_write( DDR_REG_BASE +0x51b7e*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51b7f*4 +0x02000000,0x2342); +reg_write( DDR_REG_BASE +0x51b80*4 +0x02000000,0x1100); +reg_write( DDR_REG_BASE +0x51b81*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51b82*4 +0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x51b83*4 +0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x51b84*4 +0x02000000,0x690c); +reg_write( DDR_REG_BASE +0x51b85*4 +0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x51b86*4 +0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x51b87*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51b88*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51b89*4 +0x02000000,0xf042); +reg_write( DDR_REG_BASE +0x51b8a*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51b8b*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51b8c*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51b8d*4 +0x02000000,0x1003); +reg_write( DDR_REG_BASE +0x51b8e*4 +0x02000000,0x9e); +reg_write( DDR_REG_BASE +0x51b8f*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51b90*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51b91*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51b92*4 +0x02000000,0x8842); +reg_write( DDR_REG_BASE +0x51b93*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51b94*4 +0x02000000,0xb88f); +reg_write( DDR_REG_BASE +0x51b95*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x51b96*4 +0x02000000,0xf01e); +reg_write( DDR_REG_BASE +0x51b97*4 +0x02000000,0xc602); +reg_write( DDR_REG_BASE +0x51b98*4 +0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x51b99*4 +0x02000000,0x3a0c); +reg_write( DDR_REG_BASE +0x51b9a*4 +0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x51b9b*4 +0x02000000,0x3c4d); +reg_write( DDR_REG_BASE +0x51b9c*4 +0x02000000,0x265a); +reg_write( DDR_REG_BASE +0x51b9d*4 +0x02000000,0x1a0e); +reg_write( DDR_REG_BASE +0x51b9e*4 +0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51b9f*4 +0x02000000,0x3e8f); +reg_write( DDR_REG_BASE +0x51ba0*4 +0x02000000,0x6599); +reg_write( DDR_REG_BASE +0x51ba1*4 +0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x51ba2*4 +0x02000000,0x9f); +reg_write( DDR_REG_BASE +0x51ba3*4 +0x02000000,0x67d9); +reg_write( DDR_REG_BASE +0x51ba4*4 +0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x51ba5*4 +0x02000000,0x81); +reg_write( DDR_REG_BASE +0x51ba6*4 +0x02000000,0x64fc); +reg_write( DDR_REG_BASE +0x51ba7*4 +0x02000000,0x65dd); +reg_write( DDR_REG_BASE +0x51ba8*4 +0x02000000,0x2102); +reg_write( DDR_REG_BASE +0x51ba9*4 +0x02000000,0x7c1); +reg_write( DDR_REG_BASE +0x51baa*4 +0x02000000,0x2308); +reg_write( DDR_REG_BASE +0x51bab*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x51bac*4 +0x02000000,0x24f4); +reg_write( DDR_REG_BASE +0x51bad*4 +0x02000000,0x108c); +reg_write( DDR_REG_BASE +0x51bae*4 +0x02000000,0x25f4); +reg_write( DDR_REG_BASE +0x51baf*4 +0x02000000,0x1083); +reg_write( DDR_REG_BASE +0x51bb0*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x51bb1*4 +0x02000000,0x7b82); +reg_write( DDR_REG_BASE +0x51bb2*4 +0x02000000,0x2008); +reg_write( DDR_REG_BASE +0x51bb3*4 +0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x51bb4*4 +0x02000000,0x780e); +reg_write( DDR_REG_BASE +0x51bb5*4 +0x02000000,0xec7); +reg_write( DDR_REG_BASE +0x51bb6*4 +0x02000000,0xb0a5); +reg_write( DDR_REG_BASE +0x51bb7*4 +0x02000000,0x7b2e); +reg_write( DDR_REG_BASE +0x51bb8*4 +0x02000000,0xe72); +reg_write( DDR_REG_BASE +0x51bb9*4 +0x02000000,0xfe8f); +reg_write( DDR_REG_BASE +0x51bba*4 +0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x51bbb*4 +0x02000000,0xe6e); +reg_write( DDR_REG_BASE +0x51bbc*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51bbd*4 +0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x51bbe*4 +0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x51bbf*4 +0x02000000,0x7767); +reg_write( DDR_REG_BASE +0x51bc0*4 +0x02000000,0x1901); +reg_write( DDR_REG_BASE +0x51bc1*4 +0x02000000,0x92); +reg_write( DDR_REG_BASE +0x51bc2*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51bc3*4 +0x02000000,0x1b01); +reg_write( DDR_REG_BASE +0x51bc4*4 +0x02000000,0x1012); +reg_write( DDR_REG_BASE +0x51bc5*4 +0x02000000,0xb8d); +reg_write( DDR_REG_BASE +0x51bc6*4 +0x02000000,0xb013); +reg_write( DDR_REG_BASE +0x51bc7*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x51bc8*4 +0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x51bc9*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51bca*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x51bcb*4 +0x02000000,0x8f7); +reg_write( DDR_REG_BASE +0x51bcc*4 +0x02000000,0x8033); +reg_write( DDR_REG_BASE +0x51bcd*4 +0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x51bce*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51bcf*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51bd0*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51bd1*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51bd2*4 +0x02000000,0x6901); +reg_write( DDR_REG_BASE +0x51bd3*4 +0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x51bd4*4 +0x02000000,0x7134); +reg_write( DDR_REG_BASE +0x51bd5*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51bd6*4 +0x02000000,0x7002); +reg_write( DDR_REG_BASE +0x51bd7*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51bd8*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51bd9*4 +0x02000000,0x51a); +reg_write( DDR_REG_BASE +0x51bda*4 +0x02000000,0xffce); +reg_write( DDR_REG_BASE +0x51bdb*4 +0x02000000,0xb62); +reg_write( DDR_REG_BASE +0x51bdc*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51bdd*4 +0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x51bde*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51bdf*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51be0*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51be1*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51be2*4 +0x02000000,0xa901); +reg_write( DDR_REG_BASE +0x51be3*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51be4*4 +0x02000000,0x7002); +reg_write( DDR_REG_BASE +0x51be5*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51be6*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51be7*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51be8*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51be9*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51bea*4 +0x02000000,0x19); +reg_write( DDR_REG_BASE +0x51beb*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51bec*4 +0x02000000,0x85c); +reg_write( DDR_REG_BASE +0x51bed*4 +0x02000000,0x141); +reg_write( DDR_REG_BASE +0x51bee*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51bef*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51bf0*4 +0x02000000,0xe174); +reg_write( DDR_REG_BASE +0x51bf1*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51bf2*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51bf3*4 +0x02000000,0xe82); +reg_write( DDR_REG_BASE +0x51bf4*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51bf5*4 +0x02000000,0xb021); +reg_write( DDR_REG_BASE +0x51bf6*4 +0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x51bf7*4 +0x02000000,0x3a0d); +reg_write( DDR_REG_BASE +0x51bf8*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x51bf9*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x51bfa*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51bfb*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51bfc*4 +0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x51bfd*4 +0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x51bfe*4 +0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x51bff*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51c00*4 +0x02000000,0x9fe); +reg_write( DDR_REG_BASE +0x51c01*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51c02*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x51c03*4 +0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x51c04*4 +0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x51c05*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51c06*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51c07*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x51c08*4 +0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x51c09*4 +0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x51c0a*4 +0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x51c0b*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51c0c*4 +0x02000000,0xabe); +reg_write( DDR_REG_BASE +0x51c0d*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51c0e*4 +0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x51c0f*4 +0x02000000,0xbec1); +reg_write( DDR_REG_BASE +0x51c10*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51c11*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x51c12*4 +0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x51c13*4 +0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x51c14*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51c15*4 +0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x51c16*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51c17*4 +0x02000000,0xaaa); +reg_write( DDR_REG_BASE +0x51c18*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51c19*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x51c1a*4 +0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x51c1b*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51c1c*4 +0x02000000,0xa5e); +reg_write( DDR_REG_BASE +0x51c1d*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51c1e*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51c1f*4 +0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x51c20*4 +0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x51c21*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51c22*4 +0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x51c23*4 +0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x51c24*4 +0x02000000,0xd858); +reg_write( DDR_REG_BASE +0x51c25*4 +0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x51c26*4 +0x02000000,0x88c0); +reg_write( DDR_REG_BASE +0x51c27*4 +0x02000000,0x10cd); +reg_write( DDR_REG_BASE +0x51c28*4 +0x02000000,0x808d); +reg_write( DDR_REG_BASE +0x51c29*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51c2a*4 +0x02000000,0x9aa); +reg_write( DDR_REG_BASE +0x51c2b*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51c2c*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x51c2d*4 +0x02000000,0x2605); +reg_write( DDR_REG_BASE +0x51c2e*4 +0x02000000,0x1341); +reg_write( DDR_REG_BASE +0x51c2f*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51c30*4 +0x02000000,0xb9c1); +reg_write( DDR_REG_BASE +0x51c31*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x51c32*4 +0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x51c33*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51c34*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x51c35*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51c36*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x51c37*4 +0x02000000,0xda09); +reg_write( DDR_REG_BASE +0x51c38*4 +0x02000000,0xa66); +reg_write( DDR_REG_BASE +0x51c39*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51c3a*4 +0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x51c3b*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51c3c*4 +0x02000000,0xa1e); +reg_write( DDR_REG_BASE +0x51c3d*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51c3e*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51c3f*4 +0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x51c40*4 +0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x51c41*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51c42*4 +0x02000000,0x21aa); +reg_write( DDR_REG_BASE +0x51c43*4 +0x02000000,0xc4); +reg_write( DDR_REG_BASE +0x51c44*4 +0x02000000,0x911); +reg_write( DDR_REG_BASE +0x51c45*4 +0x02000000,0x3f); +reg_write( DDR_REG_BASE +0x51c46*4 +0x02000000,0x722c); +reg_write( DDR_REG_BASE +0x51c47*4 +0x02000000,0x21ab); +reg_write( DDR_REG_BASE +0x51c48*4 +0x02000000,0xc4); +reg_write( DDR_REG_BASE +0x51c49*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51c4a*4 +0x02000000,0x21ab); +reg_write( DDR_REG_BASE +0x51c4b*4 +0x02000000,0xc4); +reg_write( DDR_REG_BASE +0x51c4c*4 +0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x51c4d*4 +0x02000000,0x415); +reg_write( DDR_REG_BASE +0x51c4e*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51c4f*4 +0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x51c50*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x51c51*4 +0x02000000,0x1d6); +reg_write( DDR_REG_BASE +0x51c52*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51c53*4 +0x02000000,0x21aa); +reg_write( DDR_REG_BASE +0x51c54*4 +0x02000000,0x104); +reg_write( DDR_REG_BASE +0x51c55*4 +0x02000000,0x7b32); +reg_write( DDR_REG_BASE +0x51c56*4 +0x02000000,0xb19); +reg_write( DDR_REG_BASE +0x51c57*4 +0x02000000,0x25); +reg_write( DDR_REG_BASE +0x51c58*4 +0x02000000,0x24aa); +reg_write( DDR_REG_BASE +0x51c59*4 +0x02000000,0x1144); +reg_write( DDR_REG_BASE +0x51c5a*4 +0x02000000,0x22aa); +reg_write( DDR_REG_BASE +0x51c5b*4 +0x02000000,0x104); +reg_write( DDR_REG_BASE +0x51c5c*4 +0x02000000,0x9fd); +reg_write( DDR_REG_BASE +0x51c5d*4 +0x02000000,0x8084); +reg_write( DDR_REG_BASE +0x51c5e*4 +0x02000000,0x7862); +reg_write( DDR_REG_BASE +0x51c5f*4 +0x02000000,0x24aa); +reg_write( DDR_REG_BASE +0x51c60*4 +0x02000000,0x1144); +reg_write( DDR_REG_BASE +0x51c61*4 +0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x51c62*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51c63*4 +0x02000000,0x21aa); +reg_write( DDR_REG_BASE +0x51c64*4 +0x02000000,0x104); +reg_write( DDR_REG_BASE +0x51c65*4 +0x02000000,0x7110); +reg_write( DDR_REG_BASE +0x51c66*4 +0x02000000,0x20e1); +reg_write( DDR_REG_BASE +0x51c67*4 +0x02000000,0x7c6); +reg_write( DDR_REG_BASE +0x51c68*4 +0x02000000,0x22aa); +reg_write( DDR_REG_BASE +0x51c69*4 +0x02000000,0x144); +reg_write( DDR_REG_BASE +0x51c6a*4 +0x02000000,0xcf3); +reg_write( DDR_REG_BASE +0x51c6b*4 +0x02000000,0x9080); +reg_write( DDR_REG_BASE +0x51c6c*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51c6d*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51c6e*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x51c6f*4 +0x02000000,0x866); +reg_write( DDR_REG_BASE +0x51c70*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51c71*4 +0x02000000,0xfa6); +reg_write( DDR_REG_BASE +0x51c72*4 +0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x51c73*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x51c74*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51c75*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51c76*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x51c77*4 +0x02000000,0xf5a); +reg_write( DDR_REG_BASE +0x51c78*4 +0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x51c79*4 +0x02000000,0xf96); +reg_write( DDR_REG_BASE +0x51c7a*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51c7b*4 +0x02000000,0xd814); +reg_write( DDR_REG_BASE +0x51c7c*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x51c7d*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51c7e*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x51c7f*4 +0x02000000,0x846); +reg_write( DDR_REG_BASE +0x51c80*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51c81*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51c82*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51c83*4 +0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x51c84*4 +0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x51c85*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51c86*4 +0x02000000,0xe915); +reg_write( DDR_REG_BASE +0x51c87*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51c88*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51c89*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51c8a*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51c8b*4 +0x02000000,0x923); +reg_write( DDR_REG_BASE +0x51c8c*4 +0x02000000,0xdf); +reg_write( DDR_REG_BASE +0x51c8d*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51c8e*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51c8f*4 +0x02000000,0x7c8); +reg_write( DDR_REG_BASE +0x51c90*4 +0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x51c91*4 +0x02000000,0x917); +reg_write( DDR_REG_BASE +0x51c92*4 +0x02000000,0x134); +reg_write( DDR_REG_BASE +0x51c93*4 +0x02000000,0x216c); +reg_write( DDR_REG_BASE +0x51c94*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x51c95*4 +0x02000000,0x2809); +reg_write( DDR_REG_BASE +0x51c96*4 +0x02000000,0x8042); +reg_write( DDR_REG_BASE +0x51c97*4 +0x02000000,0xf208); +reg_write( DDR_REG_BASE +0x51c98*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51c99*4 +0x02000000,0x7842); +reg_write( DDR_REG_BASE +0x51c9a*4 +0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x51c9b*4 +0x02000000,0x809); +reg_write( DDR_REG_BASE +0x51c9c*4 +0x02000000,0x115); +reg_write( DDR_REG_BASE +0x51c9d*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x51c9e*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x51c9f*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51ca0*4 +0x02000000,0x246f); +reg_write( DDR_REG_BASE +0x51ca1*4 +0x02000000,0x1343); +reg_write( DDR_REG_BASE +0x51ca2*4 +0x02000000,0x9460); +reg_write( DDR_REG_BASE +0x51ca3*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x51ca4*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x51ca5*4 +0x02000000,0x2a05); +reg_write( DDR_REG_BASE +0x51ca6*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x51ca7*4 +0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x51ca8*4 +0x02000000,0x8480); +reg_write( DDR_REG_BASE +0x51ca9*4 +0x02000000,0x817); +reg_write( DDR_REG_BASE +0x51caa*4 +0x02000000,0xf84); +reg_write( DDR_REG_BASE +0x51cab*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x51cac*4 +0x02000000,0xd41); +reg_write( DDR_REG_BASE +0x51cad*4 +0x02000000,0x2885); +reg_write( DDR_REG_BASE +0x51cae*4 +0x02000000,0xa0f); +reg_write( DDR_REG_BASE +0x51caf*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x51cb0*4 +0x02000000,0xc2); +reg_write( DDR_REG_BASE +0x51cb1*4 +0x02000000,0x2a85); +reg_write( DDR_REG_BASE +0x51cb2*4 +0x02000000,0x41f); +reg_write( DDR_REG_BASE +0x51cb3*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x51cb4*4 +0x02000000,0x6a01); +reg_write( DDR_REG_BASE +0x51cb5*4 +0x02000000,0x6941); +reg_write( DDR_REG_BASE +0x51cb6*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51cb7*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51cb8*4 +0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x51cb9*4 +0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x51cba*4 +0x02000000,0xe90c); +reg_write( DDR_REG_BASE +0x51cbb*4 +0x02000000,0x14fb); +reg_write( DDR_REG_BASE +0x51cbc*4 +0x02000000,0x9081); +reg_write( DDR_REG_BASE +0x51cbd*4 +0x02000000,0x915); +reg_write( DDR_REG_BASE +0x51cbe*4 +0x02000000,0xdf); +reg_write( DDR_REG_BASE +0x51cbf*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51cc0*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51cc1*4 +0x02000000,0x7c8); +reg_write( DDR_REG_BASE +0x51cc2*4 +0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x51cc3*4 +0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x51cc4*4 +0x02000000,0x22da); +reg_write( DDR_REG_BASE +0x51cc5*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x51cc6*4 +0x02000000,0x7210); +reg_write( DDR_REG_BASE +0x51cc7*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x51cc8*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x51cc9*4 +0x02000000,0x8d); +reg_write( DDR_REG_BASE +0x51cca*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51ccb*4 +0x02000000,0xece); +reg_write( DDR_REG_BASE +0x51ccc*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51ccd*4 +0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x51cce*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51ccf*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51cd0*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51cd1*4 +0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x51cd2*4 +0x02000000,0xb9c3); +reg_write( DDR_REG_BASE +0x51cd3*4 +0x02000000,0xdd58); +reg_write( DDR_REG_BASE +0x51cd4*4 +0x02000000,0x1a02); +reg_write( DDR_REG_BASE +0x51cd5*4 +0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x51cd6*4 +0x02000000,0xbd9f); +reg_write( DDR_REG_BASE +0x51cd7*4 +0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x51cd8*4 +0x02000000,0xe80b); +reg_write( DDR_REG_BASE +0x51cd9*4 +0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x51cda*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x51cdb*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51cdc*4 +0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x51cdd*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51cde*4 +0x02000000,0x57); +reg_write( DDR_REG_BASE +0x51cdf*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x51ce0*4 +0x02000000,0xe00); +reg_write( DDR_REG_BASE +0x51ce1*4 +0x02000000,0x621e); +reg_write( DDR_REG_BASE +0x51ce2*4 +0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x51ce3*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51ce4*4 +0x02000000,0x708e); +reg_write( DDR_REG_BASE +0x51ce5*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51ce6*4 +0x02000000,0x24); +reg_write( DDR_REG_BASE +0x51ce7*4 +0x02000000,0xe96); +reg_write( DDR_REG_BASE +0x51ce8*4 +0x02000000,0xff0f); +reg_write( DDR_REG_BASE +0x51ce9*4 +0x02000000,0x79cf); +reg_write( DDR_REG_BASE +0x51cea*4 +0x02000000,0x7b3d); +reg_write( DDR_REG_BASE +0x51ceb*4 +0x02000000,0x7a3d); +reg_write( DDR_REG_BASE +0x51cec*4 +0x02000000,0x2653); +reg_write( DDR_REG_BASE +0x51ced*4 +0x02000000,0x907e); +reg_write( DDR_REG_BASE +0x51cee*4 +0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x51cef*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51cf0*4 +0x02000000,0x23c0); +reg_write( DDR_REG_BASE +0x51cf1*4 +0x02000000,0x62); +reg_write( DDR_REG_BASE +0x51cf2*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51cf3*4 +0x02000000,0x2653); +reg_write( DDR_REG_BASE +0x51cf4*4 +0x02000000,0x9081); +reg_write( DDR_REG_BASE +0x51cf5*4 +0x02000000,0xb8c3); +reg_write( DDR_REG_BASE +0x51cf6*4 +0x02000000,0x22c0); +reg_write( DDR_REG_BASE +0x51cf7*4 +0x02000000,0x62); +reg_write( DDR_REG_BASE +0x51cf8*4 +0x02000000,0x1a03); +reg_write( DDR_REG_BASE +0x51cf9*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x51cfa*4 +0x02000000,0x1a05); +reg_write( DDR_REG_BASE +0x51cfb*4 +0x02000000,0x30c2); +reg_write( DDR_REG_BASE +0x51cfc*4 +0x02000000,0x1a07); +reg_write( DDR_REG_BASE +0x51cfd*4 +0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x51cfe*4 +0x02000000,0x1a04); +reg_write( DDR_REG_BASE +0x51cff*4 +0x02000000,0x3082); +reg_write( DDR_REG_BASE +0x51d00*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x51d01*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d02*4 +0x02000000,0x53); +reg_write( DDR_REG_BASE +0x51d03*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x51d04*4 +0x02000000,0xcb6); +reg_write( DDR_REG_BASE +0x51d05*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d06*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d07*4 +0x02000000,0x276f); +reg_write( DDR_REG_BASE +0x51d08*4 +0x02000000,0x10c3); +reg_write( DDR_REG_BASE +0x51d09*4 +0x02000000,0x8f00); +reg_write( DDR_REG_BASE +0x51d0a*4 +0x02000000,0xb8e2); +reg_write( DDR_REG_BASE +0x51d0b*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51d0c*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x51d0d*4 +0x02000000,0xe1); +reg_write( DDR_REG_BASE +0x51d0e*4 +0x02000000,0x1a08); +reg_write( DDR_REG_BASE +0x51d0f*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x51d10*4 +0x02000000,0x1724); +reg_write( DDR_REG_BASE +0x51d11*4 +0x02000000,0x1082); +reg_write( DDR_REG_BASE +0x51d12*4 +0x02000000,0x170f); +reg_write( DDR_REG_BASE +0x51d13*4 +0x02000000,0x1481); +reg_write( DDR_REG_BASE +0x51d14*4 +0x02000000,0x2742); +reg_write( DDR_REG_BASE +0x51d15*4 +0x02000000,0x1280); +reg_write( DDR_REG_BASE +0x51d16*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51d17*4 +0x02000000,0x8d60); +reg_write( DDR_REG_BASE +0x51d18*4 +0x02000000,0x97c0); +reg_write( DDR_REG_BASE +0x51d19*4 +0x02000000,0x8f82); +reg_write( DDR_REG_BASE +0x51d1a*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x51d1b*4 +0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x51d1c*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d1d*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d1e*4 +0x02000000,0x55); +reg_write( DDR_REG_BASE +0x51d1f*4 +0x02000000,0x6); +reg_write( DDR_REG_BASE +0x51d20*4 +0x02000000,0xc441); +reg_write( DDR_REG_BASE +0x51d21*4 +0x02000000,0xc7e); +reg_write( DDR_REG_BASE +0x51d22*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d23*4 +0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x51d24*4 +0x02000000,0x8f08); +reg_write( DDR_REG_BASE +0x51d25*4 +0x02000000,0xe808); +reg_write( DDR_REG_BASE +0x51d26*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d27*4 +0x02000000,0x5a); +reg_write( DDR_REG_BASE +0x51d28*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51d29*4 +0x02000000,0xc6e); +reg_write( DDR_REG_BASE +0x51d2a*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d2b*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d2c*4 +0x02000000,0xde32); +reg_write( DDR_REG_BASE +0x51d2d*4 +0x02000000,0xbe9f); +reg_write( DDR_REG_BASE +0x51d2e*4 +0x02000000,0x1601); +reg_write( DDR_REG_BASE +0x51d2f*4 +0x02000000,0x1483); +reg_write( DDR_REG_BASE +0x51d30*4 +0x02000000,0x16d1); +reg_write( DDR_REG_BASE +0x51d31*4 +0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x51d32*4 +0x02000000,0x1601); +reg_write( DDR_REG_BASE +0x51d33*4 +0x02000000,0x148c); +reg_write( DDR_REG_BASE +0x51d34*4 +0x02000000,0x1602); +reg_write( DDR_REG_BASE +0x51d35*4 +0x02000000,0x1481); +reg_write( DDR_REG_BASE +0x51d36*4 +0x02000000,0x1601); +reg_write( DDR_REG_BASE +0x51d37*4 +0x02000000,0x1480); +reg_write( DDR_REG_BASE +0x51d38*4 +0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51d39*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51d3a*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51d3b*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d3c*4 +0x02000000,0x5b); +reg_write( DDR_REG_BASE +0x51d3d*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51d3e*4 +0x02000000,0xc42); +reg_write( DDR_REG_BASE +0x51d3f*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d40*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d41*4 +0x02000000,0x1601); +reg_write( DDR_REG_BASE +0x51d42*4 +0x02000000,0x1483); +reg_write( DDR_REG_BASE +0x51d43*4 +0x02000000,0x8e21); +reg_write( DDR_REG_BASE +0x51d44*4 +0x02000000,0x8e04); +reg_write( DDR_REG_BASE +0x51d45*4 +0x02000000,0x16cc); +reg_write( DDR_REG_BASE +0x51d46*4 +0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x51d47*4 +0x02000000,0x8e80); +reg_write( DDR_REG_BASE +0x51d48*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51d49*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51d4a*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d4b*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d4c*4 +0x02000000,0x5c); +reg_write( DDR_REG_BASE +0x51d4d*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51d4e*4 +0x02000000,0xc22); +reg_write( DDR_REG_BASE +0x51d4f*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d50*4 +0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51d51*4 +0x02000000,0x8f08); +reg_write( DDR_REG_BASE +0x51d52*4 +0x02000000,0x8b5); +reg_write( DDR_REG_BASE +0x51d53*4 +0x02000000,0x11); +reg_write( DDR_REG_BASE +0x51d54*4 +0x02000000,0x8f15); +reg_write( DDR_REG_BASE +0x51d55*4 +0x02000000,0x831); +reg_write( DDR_REG_BASE +0x51d56*4 +0x02000000,0x7e); +reg_write( DDR_REG_BASE +0x51d57*4 +0x02000000,0xdf3e); +reg_write( DDR_REG_BASE +0x51d58*4 +0x02000000,0xf840); +reg_write( DDR_REG_BASE +0x51d59*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51d5a*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51d5b*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d5c*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d5d*4 +0x02000000,0x5d); +reg_write( DDR_REG_BASE +0x51d5e*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51d5f*4 +0x02000000,0xc02); +reg_write( DDR_REG_BASE +0x51d60*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d61*4 +0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51d62*4 +0x02000000,0xf841); +reg_write( DDR_REG_BASE +0x51d63*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51d64*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51d65*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d66*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d67*4 +0x02000000,0x5e); +reg_write( DDR_REG_BASE +0x51d68*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51d69*4 +0x02000000,0xbee); +reg_write( DDR_REG_BASE +0x51d6a*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d6b*4 +0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51d6c*4 +0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x51d6d*4 +0x02000000,0x833); +reg_write( DDR_REG_BASE +0x51d6e*4 +0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x51d6f*4 +0x02000000,0xdf65); +reg_write( DDR_REG_BASE +0x51d70*4 +0x02000000,0xf834); +reg_write( DDR_REG_BASE +0x51d71*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51d72*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51d73*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d74*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d75*4 +0x02000000,0x5f); +reg_write( DDR_REG_BASE +0x51d76*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51d77*4 +0x02000000,0xbd2); +reg_write( DDR_REG_BASE +0x51d78*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d79*4 +0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51d7a*4 +0x02000000,0xf835); +reg_write( DDR_REG_BASE +0x51d7b*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51d7c*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51d7d*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d7e*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d7f*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x51d80*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51d81*4 +0x02000000,0xbbe); +reg_write( DDR_REG_BASE +0x51d82*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d83*4 +0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51d84*4 +0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x51d85*4 +0x02000000,0x851); +reg_write( DDR_REG_BASE +0x51d86*4 +0x02000000,0x7e); +reg_write( DDR_REG_BASE +0x51d87*4 +0x02000000,0xdd71); +reg_write( DDR_REG_BASE +0x51d88*4 +0x02000000,0xbd9f); +reg_write( DDR_REG_BASE +0x51d89*4 +0x02000000,0x1501); +reg_write( DDR_REG_BASE +0x51d8a*4 +0x02000000,0x1483); +reg_write( DDR_REG_BASE +0x51d8b*4 +0x02000000,0x1501); +reg_write( DDR_REG_BASE +0x51d8c*4 +0x02000000,0x148c); +reg_write( DDR_REG_BASE +0x51d8d*4 +0x02000000,0x1502); +reg_write( DDR_REG_BASE +0x51d8e*4 +0x02000000,0x1481); +reg_write( DDR_REG_BASE +0x51d8f*4 +0x02000000,0x1501); +reg_write( DDR_REG_BASE +0x51d90*4 +0x02000000,0x1480); +reg_write( DDR_REG_BASE +0x51d91*4 +0x02000000,0x16cc); +reg_write( DDR_REG_BASE +0x51d92*4 +0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x51d93*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51d94*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51d95*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51d96*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d97*4 +0x02000000,0x61); +reg_write( DDR_REG_BASE +0x51d98*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51d99*4 +0x02000000,0xb8e); +reg_write( DDR_REG_BASE +0x51d9a*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51d9b*4 +0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51d9c*4 +0x02000000,0x1501); +reg_write( DDR_REG_BASE +0x51d9d*4 +0x02000000,0x1483); +reg_write( DDR_REG_BASE +0x51d9e*4 +0x02000000,0x8d21); +reg_write( DDR_REG_BASE +0x51d9f*4 +0x02000000,0x8d04); +reg_write( DDR_REG_BASE +0x51da0*4 +0x02000000,0x16cc); +reg_write( DDR_REG_BASE +0x51da1*4 +0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x51da2*4 +0x02000000,0x8d80); +reg_write( DDR_REG_BASE +0x51da3*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51da4*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51da5*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51da6*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51da7*4 +0x02000000,0x62); +reg_write( DDR_REG_BASE +0x51da8*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51da9*4 +0x02000000,0xb6e); +reg_write( DDR_REG_BASE +0x51daa*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51dab*4 +0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51dac*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51dad*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x51dae*4 +0x02000000,0x1a0); +reg_write( DDR_REG_BASE +0x51daf*4 +0x02000000,0x1802); +reg_write( DDR_REG_BASE +0x51db0*4 +0x02000000,0x15); +reg_write( DDR_REG_BASE +0x51db1*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51db2*4 +0x02000000,0x44); +reg_write( DDR_REG_BASE +0x51db3*4 +0x02000000,0x1802); +reg_write( DDR_REG_BASE +0x51db4*4 +0x02000000,0x54); +reg_write( DDR_REG_BASE +0x51db5*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51db6*4 +0x02000000,0x144); +reg_write( DDR_REG_BASE +0x51db7*4 +0x02000000,0x1802); +reg_write( DDR_REG_BASE +0x51db8*4 +0x02000000,0x54); +reg_write( DDR_REG_BASE +0x51db9*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51dba*4 +0x02000000,0x1c4); +reg_write( DDR_REG_BASE +0x51dbb*4 +0x02000000,0x1804); +reg_write( DDR_REG_BASE +0x51dbc*4 +0x02000000,0x54); +reg_write( DDR_REG_BASE +0x51dbd*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51dbe*4 +0x02000000,0x88); +reg_write( DDR_REG_BASE +0x51dbf*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51dc0*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51dc1*4 +0x02000000,0x288); +reg_write( DDR_REG_BASE +0x51dc2*4 +0x02000000,0xb021); +reg_write( DDR_REG_BASE +0x51dc3*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51dc4*4 +0x02000000,0x2c8); +reg_write( DDR_REG_BASE +0x51dc5*4 +0x02000000,0xb022); +reg_write( DDR_REG_BASE +0x51dc6*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x51dc7*4 +0x02000000,0x3cc); +reg_write( DDR_REG_BASE +0x51dc8*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51dc9*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x51dca*4 +0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x51dcb*4 +0x02000000,0xe180); +reg_write( DDR_REG_BASE +0x51dcc*4 +0x02000000,0xd934); +reg_write( DDR_REG_BASE +0x51dcd*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51dce*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x51dcf*4 +0x02000000,0xe0ee); +reg_write( DDR_REG_BASE +0x51dd0*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51dd1*4 +0x02000000,0xd4e); +reg_write( DDR_REG_BASE +0x51dd2*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51dd3*4 +0x02000000,0x18fc); +reg_write( DDR_REG_BASE +0x51dd4*4 +0x02000000,0x8105); +reg_write( DDR_REG_BASE +0x51dd5*4 +0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x51dd6*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51dd7*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51dd8*4 +0x02000000,0xbf9f); +reg_write( DDR_REG_BASE +0x51dd9*4 +0x02000000,0x1701); +reg_write( DDR_REG_BASE +0x51dda*4 +0x02000000,0x1483); +reg_write( DDR_REG_BASE +0x51ddb*4 +0x02000000,0x1701); +reg_write( DDR_REG_BASE +0x51ddc*4 +0x02000000,0x148c); +reg_write( DDR_REG_BASE +0x51ddd*4 +0x02000000,0x1702); +reg_write( DDR_REG_BASE +0x51dde*4 +0x02000000,0x1481); +reg_write( DDR_REG_BASE +0x51ddf*4 +0x02000000,0x1701); +reg_write( DDR_REG_BASE +0x51de0*4 +0x02000000,0x1480); +reg_write( DDR_REG_BASE +0x51de1*4 +0x02000000,0x16cc); +reg_write( DDR_REG_BASE +0x51de2*4 +0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x51de3*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51de4*4 +0x02000000,0x1701); +reg_write( DDR_REG_BASE +0x51de5*4 +0x02000000,0x1483); +reg_write( DDR_REG_BASE +0x51de6*4 +0x02000000,0x8f21); +reg_write( DDR_REG_BASE +0x51de7*4 +0x02000000,0x8f04); +reg_write( DDR_REG_BASE +0x51de8*4 +0x02000000,0x16cc); +reg_write( DDR_REG_BASE +0x51de9*4 +0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x51dea*4 +0x02000000,0x8f80); +reg_write( DDR_REG_BASE +0x51deb*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51dec*4 +0x02000000,0x621a); +reg_write( DDR_REG_BASE +0x51ded*4 +0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x51dee*4 +0x02000000,0x1801); +reg_write( DDR_REG_BASE +0x51def*4 +0x02000000,0x52); +reg_write( DDR_REG_BASE +0x51df0*4 +0x02000000,0x8fd); +reg_write( DDR_REG_BASE +0x51df1*4 +0x02000000,0x8084); +reg_write( DDR_REG_BASE +0x51df2*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51df3*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51df4*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51df5*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51df6*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51df7*4 +0x02000000,0xc1a7); +reg_write( DDR_REG_BASE +0x51df8*4 +0x02000000,0xda07); +reg_write( DDR_REG_BASE +0x51df9*4 +0x02000000,0xba8c); +reg_write( DDR_REG_BASE +0x51dfa*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51dfb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51dfc*4 +0x02000000,0x9f38); +reg_write( DDR_REG_BASE +0x51dfd*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x51dfe*4 +0x02000000,0x9012); +reg_write( DDR_REG_BASE +0x51dff*4 +0x02000000,0x328); +reg_write( DDR_REG_BASE +0x51e00*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51e01*4 +0x02000000,0x7084); +reg_write( DDR_REG_BASE +0x51e02*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e03*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x51e04*4 +0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x51e05*4 +0x02000000,0xd858); +reg_write( DDR_REG_BASE +0x51e06*4 +0x02000000,0xb501); +reg_write( DDR_REG_BASE +0x51e07*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51e08*4 +0x02000000,0xb8); +reg_write( DDR_REG_BASE +0x51e09*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51e0a*4 +0x02000000,0xaaa); +reg_write( DDR_REG_BASE +0x51e0b*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51e0c*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51e0d*4 +0x02000000,0xcc20); +reg_write( DDR_REG_BASE +0x51e0e*4 +0x02000000,0x9520); +reg_write( DDR_REG_BASE +0x51e0f*4 +0x02000000,0x7030); +reg_write( DDR_REG_BASE +0x51e10*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51e11*4 +0x02000000,0xf406); +reg_write( DDR_REG_BASE +0x51e12*4 +0x02000000,0xcc21); +reg_write( DDR_REG_BASE +0x51e13*4 +0x02000000,0x9521); +reg_write( DDR_REG_BASE +0x51e14*4 +0x02000000,0x2038); +reg_write( DDR_REG_BASE +0x51e15*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x51e16*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51e17*4 +0x02000000,0xb9); +reg_write( DDR_REG_BASE +0x51e18*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51e19*4 +0x02000000,0xd22); +reg_write( DDR_REG_BASE +0x51e1a*4 +0x02000000,0xfe0f); +reg_write( DDR_REG_BASE +0x51e1b*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51e1c*4 +0x02000000,0x7043); +reg_write( DDR_REG_BASE +0x51e1d*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e1e*4 +0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x51e1f*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51e20*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51e21*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e22*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51e23*4 +0x02000000,0x1a00); +reg_write( DDR_REG_BASE +0x51e24*4 +0x02000000,0x3103); +reg_write( DDR_REG_BASE +0x51e25*4 +0x02000000,0x216f); +reg_write( DDR_REG_BASE +0x51e26*4 +0x02000000,0x243); +reg_write( DDR_REG_BASE +0x51e27*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51e28*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x51e29*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51e2a*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51e2b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51e2c*4 +0x02000000,0x9126); +reg_write( DDR_REG_BASE +0x51e2d*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51e2e*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51e2f*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51e30*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51e31*4 +0x02000000,0x32); +reg_write( DDR_REG_BASE +0x51e32*4 +0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x51e33*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51e34*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x51e35*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51e36*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51e37*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51e38*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51e39*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x51e3a*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51e3b*4 +0x02000000,0xa46); +reg_write( DDR_REG_BASE +0x51e3c*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51e3d*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x51e3e*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51e3f*4 +0x02000000,0xb8e0); +reg_write( DDR_REG_BASE +0x51e40*4 +0x02000000,0x264); +reg_write( DDR_REG_BASE +0x51e41*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51e42*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51e43*4 +0x02000000,0xc103); +reg_write( DDR_REG_BASE +0x51e44*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51e45*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51e46*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x51e47*4 +0x02000000,0xe032); +reg_write( DDR_REG_BASE +0x51e48*4 +0x02000000,0xb980); +reg_write( DDR_REG_BASE +0x51e49*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51e4a*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51e4b*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51e4c*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51e4d*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51e4e*4 +0x02000000,0xe090); +reg_write( DDR_REG_BASE +0x51e4f*4 +0x02000000,0xca2); +reg_write( DDR_REG_BASE +0x51e50*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51e51*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x51e52*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51e53*4 +0x02000000,0x256f); +reg_write( DDR_REG_BASE +0x51e54*4 +0x02000000,0x1cc3); +reg_write( DDR_REG_BASE +0x51e55*4 +0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x51e56*4 +0x02000000,0xe885); +reg_write( DDR_REG_BASE +0x51e57*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51e58*4 +0x02000000,0x7085); +reg_write( DDR_REG_BASE +0x51e59*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51e5a*4 +0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x51e5b*4 +0x02000000,0xce2); +reg_write( DDR_REG_BASE +0x51e5c*4 +0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x51e5d*4 +0x02000000,0xf92); +reg_write( DDR_REG_BASE +0x51e5e*4 +0x02000000,0xff0f); +reg_write( DDR_REG_BASE +0x51e5f*4 +0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x51e60*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51e61*4 +0x02000000,0xf4bb); +reg_write( DDR_REG_BASE +0x51e62*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51e63*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x51e64*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e65*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51e66*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51e67*4 +0x02000000,0x708b); +reg_write( DDR_REG_BASE +0x51e68*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e69*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51e6a*4 +0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x51e6b*4 +0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x51e6c*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51e6d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51e6e*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x51e6f*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51e70*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51e71*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51e72*4 +0x02000000,0x86); +reg_write( DDR_REG_BASE +0x51e73*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51e74*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x51e75*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51e76*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51e77*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51e78*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51e79*4 +0x02000000,0xb8c2); +reg_write( DDR_REG_BASE +0x51e7a*4 +0x02000000,0x825); +reg_write( DDR_REG_BASE +0x51e7b*4 +0x02000000,0x90); +reg_write( DDR_REG_BASE +0x51e7c*4 +0x02000000,0x833); +reg_write( DDR_REG_BASE +0x51e7d*4 +0x02000000,0xf1); +reg_write( DDR_REG_BASE +0x51e7e*4 +0x02000000,0x238b); +reg_write( DDR_REG_BASE +0x51e7f*4 +0x02000000,0x903e); +reg_write( DDR_REG_BASE +0x51e80*4 +0x02000000,0xce08); +reg_write( DDR_REG_BASE +0x51e81*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51e82*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e83*4 +0x02000000,0x41c); +reg_write( DDR_REG_BASE +0x51e84*4 +0x02000000,0x761c); +reg_write( DDR_REG_BASE +0x51e85*4 +0x02000000,0x1a03); +reg_write( DDR_REG_BASE +0x51e86*4 +0x02000000,0x3398); +reg_write( DDR_REG_BASE +0x51e87*4 +0x02000000,0xce0e); +reg_write( DDR_REG_BASE +0x51e88*4 +0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x51e89*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e8a*4 +0x02000000,0x434); +reg_write( DDR_REG_BASE +0x51e8b*4 +0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x51e8c*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51e8d*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e8e*4 +0x02000000,0x418); +reg_write( DDR_REG_BASE +0x51e8f*4 +0x02000000,0x1a03); +reg_write( DDR_REG_BASE +0x51e90*4 +0x02000000,0x3398); +reg_write( DDR_REG_BASE +0x51e91*4 +0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x51e92*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e93*4 +0x02000000,0x430); +reg_write( DDR_REG_BASE +0x51e94*4 +0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x51e95*4 +0x02000000,0x238b); +reg_write( DDR_REG_BASE +0x51e96*4 +0x02000000,0x903e); +reg_write( DDR_REG_BASE +0x51e97*4 +0x02000000,0xce05); +reg_write( DDR_REG_BASE +0x51e98*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51e99*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e9a*4 +0x02000000,0x410); +reg_write( DDR_REG_BASE +0x51e9b*4 +0x02000000,0x761c); +reg_write( DDR_REG_BASE +0x51e9c*4 +0x02000000,0xce0b); +reg_write( DDR_REG_BASE +0x51e9d*4 +0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x51e9e*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e9f*4 +0x02000000,0x428); +reg_write( DDR_REG_BASE +0x51ea0*4 +0x02000000,0x1a03); +reg_write( DDR_REG_BASE +0x51ea1*4 +0x02000000,0x3398); +reg_write( DDR_REG_BASE +0x51ea2*4 +0x02000000,0x771c); +reg_write( DDR_REG_BASE +0x51ea3*4 +0x02000000,0x1a09); +reg_write( DDR_REG_BASE +0x51ea4*4 +0x02000000,0x33d8); +reg_write( DDR_REG_BASE +0x51ea5*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51ea6*4 +0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x51ea7*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51ea8*4 +0x02000000,0xc); +reg_write( DDR_REG_BASE +0x51ea9*4 +0x02000000,0x238b); +reg_write( DDR_REG_BASE +0x51eaa*4 +0x02000000,0x903e); +reg_write( DDR_REG_BASE +0x51eab*4 +0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x51eac*4 +0x02000000,0xf9b); +reg_write( DDR_REG_BASE +0x51ead*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51eae*4 +0x02000000,0x86a0); +reg_write( DDR_REG_BASE +0x51eaf*4 +0x02000000,0xf20b); +reg_write( DDR_REG_BASE +0x51eb0*4 +0x02000000,0x233c); +reg_write( DDR_REG_BASE +0x51eb1*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x51eb2*4 +0x02000000,0xa6); +reg_write( DDR_REG_BASE +0x51eb3*4 +0x02000000,0x400); +reg_write( DDR_REG_BASE +0x51eb4*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51eb5*4 +0x02000000,0x141); +reg_write( DDR_REG_BASE +0x51eb6*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51eb7*4 +0x02000000,0xbe6); +reg_write( DDR_REG_BASE +0x51eb8*4 +0x02000000,0xfe0f); +reg_write( DDR_REG_BASE +0x51eb9*4 +0x02000000,0x222f); +reg_write( DDR_REG_BASE +0x51eba*4 +0x02000000,0x6c2); +reg_write( DDR_REG_BASE +0x51ebb*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51ebc*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51ebd*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51ebe*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51ebf*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51ec0*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51ec1*4 +0x02000000,0xed95); +reg_write( DDR_REG_BASE +0x51ec2*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51ec3*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x51ec4*4 +0x02000000,0x80); +reg_write( DDR_REG_BASE +0x51ec5*4 +0x02000000,0x6611); +reg_write( DDR_REG_BASE +0x51ec6*4 +0x02000000,0x6710); +reg_write( DDR_REG_BASE +0x51ec7*4 +0x02000000,0x4a10); +reg_write( DDR_REG_BASE +0x51ec8*4 +0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x51ec9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51eca*4 +0x02000000,0x2805); +reg_write( DDR_REG_BASE +0x51ecb*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x51ecc*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51ecd*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51ece*4 +0x02000000,0xfe80); +reg_write( DDR_REG_BASE +0x51ecf*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51ed0*4 +0x02000000,0x2089); +reg_write( DDR_REG_BASE +0x51ed1*4 +0x02000000,0xfc1); +reg_write( DDR_REG_BASE +0x51ed2*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x51ed3*4 +0x02000000,0x19e0); +reg_write( DDR_REG_BASE +0x51ed4*4 +0x02000000,0x8004); +reg_write( DDR_REG_BASE +0x51ed5*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x51ed6*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x51ed7*4 +0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x51ed8*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x51ed9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51eda*4 +0x02000000,0x2b05); +reg_write( DDR_REG_BASE +0x51edb*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x51edc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51edd*4 +0x02000000,0xfa00); +reg_write( DDR_REG_BASE +0x51ede*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x51edf*4 +0x02000000,0x821); +reg_write( DDR_REG_BASE +0x51ee0*4 +0x02000000,0x1fe); +reg_write( DDR_REG_BASE +0x51ee1*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x51ee2*4 +0x02000000,0x2200); +reg_write( DDR_REG_BASE +0x51ee3*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51ee4*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x51ee5*4 +0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x51ee6*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x51ee7*4 +0x02000000,0x8d47); +reg_write( DDR_REG_BASE +0x51ee8*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x51ee9*4 +0x02000000,0xf685); +reg_write( DDR_REG_BASE +0x51eea*4 +0x02000000,0x2885); +reg_write( DDR_REG_BASE +0x51eeb*4 +0x02000000,0xd07); +reg_write( DDR_REG_BASE +0x51eec*4 +0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x51eed*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51eee*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51eef*4 +0x02000000,0x2089); +reg_write( DDR_REG_BASE +0x51ef0*4 +0x02000000,0xfc1); +reg_write( DDR_REG_BASE +0x51ef1*4 +0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x51ef2*4 +0x02000000,0x200); +reg_write( DDR_REG_BASE +0x51ef3*4 +0x02000000,0xc105); +reg_write( DDR_REG_BASE +0x51ef4*4 +0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x51ef5*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x51ef6*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x51ef7*4 +0x02000000,0xe164); +reg_write( DDR_REG_BASE +0x51ef8*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51ef9*4 +0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x51efa*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51efb*4 +0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x51efc*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51efd*4 +0x02000000,0x164); +reg_write( DDR_REG_BASE +0x51efe*4 +0x02000000,0xb8c1); +reg_write( DDR_REG_BASE +0x51eff*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x51f00*4 +0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x51f01*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51f02*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51f03*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51f04*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51f05*4 +0x02000000,0x86); +reg_write( DDR_REG_BASE +0x51f06*4 +0x02000000,0x952); +reg_write( DDR_REG_BASE +0x51f07*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51f08*4 +0x02000000,0x90c0); +reg_write( DDR_REG_BASE +0x51f09*4 +0x02000000,0x8e2); +reg_write( DDR_REG_BASE +0x51f0a*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51f0b*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x51f0c*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51f0d*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51f0e*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51f0f*4 +0x02000000,0x1f); +reg_write( DDR_REG_BASE +0x51f10*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x51f11*4 +0x02000000,0x2111); +reg_write( DDR_REG_BASE +0x51f12*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51f13*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51f14*4 +0x02000000,0x26cf); +reg_write( DDR_REG_BASE +0x51f15*4 +0x02000000,0x1021); +reg_write( DDR_REG_BASE +0x51f16*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51f17*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51f18*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51f19*4 +0x02000000,0xfe86); +reg_write( DDR_REG_BASE +0x51f1a*4 +0x02000000,0xb0c0); +reg_write( DDR_REG_BASE +0x51f1b*4 +0x02000000,0xb2a); +reg_write( DDR_REG_BASE +0x51f1c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51f1d*4 +0x02000000,0xb4a); +reg_write( DDR_REG_BASE +0x51f1e*4 +0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x51f1f*4 +0x02000000,0x8fe); +reg_write( DDR_REG_BASE +0x51f20*4 +0x02000000,0xfe8f); +reg_write( DDR_REG_BASE +0x51f21*4 +0x02000000,0xc52); +reg_write( DDR_REG_BASE +0x51f22*4 +0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x51f23*4 +0x02000000,0xca04); +reg_write( DDR_REG_BASE +0x51f24*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51f25*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x51f26*4 +0x02000000,0xf033); +reg_write( DDR_REG_BASE +0x51f27*4 +0x02000000,0x245a); +reg_write( DDR_REG_BASE +0x51f28*4 +0x02000000,0x149e); +reg_write( DDR_REG_BASE +0x51f29*4 +0x02000000,0x2600); +reg_write( DDR_REG_BASE +0x51f2a*4 +0x02000000,0x3f83); +reg_write( DDR_REG_BASE +0x51f2b*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51f2c*4 +0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x51f2d*4 +0x02000000,0xb341); +reg_write( DDR_REG_BASE +0x51f2e*4 +0x02000000,0xf028); +reg_write( DDR_REG_BASE +0x51f2f*4 +0x02000000,0x241a); +reg_write( DDR_REG_BASE +0x51f30*4 +0x02000000,0x1f81); +reg_write( DDR_REG_BASE +0x51f31*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51f32*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x51f33*4 +0x02000000,0x79a5); +reg_write( DDR_REG_BASE +0x51f34*4 +0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x51f35*4 +0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x51f36*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51f37*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51f38*4 +0x02000000,0x140); +reg_write( DDR_REG_BASE +0x51f39*4 +0x02000000,0x9120); +reg_write( DDR_REG_BASE +0x51f3a*4 +0x02000000,0x7e2f); +reg_write( DDR_REG_BASE +0x51f3b*4 +0x02000000,0xd13); +reg_write( DDR_REG_BASE +0x51f3c*4 +0x02000000,0x13a1); +reg_write( DDR_REG_BASE +0x51f3d*4 +0x02000000,0xbec4); +reg_write( DDR_REG_BASE +0x51f3e*4 +0x02000000,0x8b22); +reg_write( DDR_REG_BASE +0x51f3f*4 +0x02000000,0x210f); +reg_write( DDR_REG_BASE +0x51f40*4 +0x02000000,0x341); +reg_write( DDR_REG_BASE +0x51f41*4 +0x02000000,0xab22); +reg_write( DDR_REG_BASE +0x51f42*4 +0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x51f43*4 +0x02000000,0x8b23); +reg_write( DDR_REG_BASE +0x51f44*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x51f45*4 +0x02000000,0xab23); +reg_write( DDR_REG_BASE +0x51f46*4 +0x02000000,0x792f); +reg_write( DDR_REG_BASE +0x51f47*4 +0x02000000,0x2614); +reg_write( DDR_REG_BASE +0x51f48*4 +0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x51f49*4 +0x02000000,0x2100); +reg_write( DDR_REG_BASE +0x51f4a*4 +0x02000000,0xf8f); +reg_write( DDR_REG_BASE +0x51f4b*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51f4c*4 +0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x51f4d*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51f4e*4 +0x02000000,0xafa3); +reg_write( DDR_REG_BASE +0x51f4f*4 +0x02000000,0xee06); +reg_write( DDR_REG_BASE +0x51f50*4 +0x02000000,0xbe61); +reg_write( DDR_REG_BASE +0x51f51*4 +0x02000000,0xe01); +reg_write( DDR_REG_BASE +0x51f52*4 +0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x51f53*4 +0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x51f54*4 +0x02000000,0xaf22); +reg_write( DDR_REG_BASE +0x51f55*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x51f56*4 +0x02000000,0xdb3); +reg_write( DDR_REG_BASE +0x51f57*4 +0x02000000,0x9214); +reg_write( DDR_REG_BASE +0x51f58*4 +0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x51f59*4 +0x02000000,0xc9f); +reg_write( DDR_REG_BASE +0x51f5a*4 +0x02000000,0x9024); +reg_write( DDR_REG_BASE +0x51f5b*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x51f5c*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51f5d*4 +0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x51f5e*4 +0x02000000,0x33f); +reg_write( DDR_REG_BASE +0x51f5f*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51f60*4 +0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x51f61*4 +0x02000000,0xbd2); +reg_write( DDR_REG_BASE +0x51f62*4 +0x02000000,0xfe0f); +reg_write( DDR_REG_BASE +0x51f63*4 +0x02000000,0xabe); +reg_write( DDR_REG_BASE +0x51f64*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51f65*4 +0x02000000,0xd80d); +reg_write( DDR_REG_BASE +0x51f66*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51f67*4 +0x02000000,0xfc6); +reg_write( DDR_REG_BASE +0x51f68*4 +0x02000000,0x180); +reg_write( DDR_REG_BASE +0x51f69*4 +0x02000000,0xee2); +reg_write( DDR_REG_BASE +0x51f6a*4 +0x02000000,0xfe4f); +reg_write( DDR_REG_BASE +0x51f6b*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51f6c*4 +0x02000000,0x7003); +reg_write( DDR_REG_BASE +0x51f6d*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51f6e*4 +0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x51f6f*4 +0x02000000,0xaa6); +reg_write( DDR_REG_BASE +0x51f70*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51f71*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51f72*4 +0x02000000,0xca04); +reg_write( DDR_REG_BASE +0x51f73*4 +0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x51f74*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x51f75*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x51f76*4 +0x02000000,0xf019); +reg_write( DDR_REG_BASE +0x51f77*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51f78*4 +0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x51f79*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x51f7a*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51f7b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51f7c*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x51f7d*4 +0x02000000,0x2300); +reg_write( DDR_REG_BASE +0x51f7e*4 +0x02000000,0x1f8d); +reg_write( DDR_REG_BASE +0x51f7f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51f80*4 +0x02000000,0x7f0); +reg_write( DDR_REG_BASE +0x51f81*4 +0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x51f82*4 +0x02000000,0x7945); +reg_write( DDR_REG_BASE +0x51f83*4 +0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x51f84*4 +0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x51f85*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51f86*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51f87*4 +0x02000000,0x140); +reg_write( DDR_REG_BASE +0x51f88*4 +0x02000000,0x9180); +reg_write( DDR_REG_BASE +0x51f89*4 +0x02000000,0xad80); +reg_write( DDR_REG_BASE +0x51f8a*4 +0x02000000,0xb140); +reg_write( DDR_REG_BASE +0x51f8b*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x51f8c*4 +0x02000000,0xadb); +reg_write( DDR_REG_BASE +0x51f8d*4 +0x02000000,0x8214); +reg_write( DDR_REG_BASE +0x51f8e*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x51f8f*4 +0x02000000,0xbd3); +reg_write( DDR_REG_BASE +0x51f90*4 +0x02000000,0x8024); +reg_write( DDR_REG_BASE +0x51f91*4 +0x02000000,0x2616); +reg_write( DDR_REG_BASE +0x51f92*4 +0x02000000,0x30cb); +reg_write( DDR_REG_BASE +0x51f93*4 +0x02000000,0xbde); +reg_write( DDR_REG_BASE +0x51f94*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51f95*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51f96*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51f97*4 +0x02000000,0x813); +reg_write( DDR_REG_BASE +0x51f98*4 +0x02000000,0xbe); +reg_write( DDR_REG_BASE +0x51f99*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51f9a*4 +0x02000000,0xbaa); +reg_write( DDR_REG_BASE +0x51f9b*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x51f9c*4 +0x02000000,0xa4a); +reg_write( DDR_REG_BASE +0x51f9d*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51f9e*4 +0x02000000,0x720c); +reg_write( DDR_REG_BASE +0x51f9f*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51fa0*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x51fa1*4 +0x02000000,0x808e); +reg_write( DDR_REG_BASE +0x51fa2*4 +0x02000000,0xf207); +reg_write( DDR_REG_BASE +0x51fa3*4 +0x02000000,0xb9a); +reg_write( DDR_REG_BASE +0x51fa4*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51fa5*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51fa6*4 +0x02000000,0xa36); +reg_write( DDR_REG_BASE +0x51fa7*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51fa8*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51fa9*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51faa*4 +0x02000000,0x81b); +reg_write( DDR_REG_BASE +0x51fab*4 +0x02000000,0x21e); +reg_write( DDR_REG_BASE +0x51fac*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51fad*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51fae*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51faf*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51fb0*4 +0x02000000,0xe887); +reg_write( DDR_REG_BASE +0x51fb1*4 +0x02000000,0xb7e); +reg_write( DDR_REG_BASE +0x51fb2*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51fb3*4 +0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x51fb4*4 +0x02000000,0xa1a); +reg_write( DDR_REG_BASE +0x51fb5*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51fb6*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51fb7*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51fb8*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x51fb9*4 +0x02000000,0x820d); +reg_write( DDR_REG_BASE +0x51fba*4 +0x02000000,0xf207); +reg_write( DDR_REG_BASE +0x51fbb*4 +0x02000000,0xb6a); +reg_write( DDR_REG_BASE +0x51fbc*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51fbd*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x51fbe*4 +0x02000000,0xa06); +reg_write( DDR_REG_BASE +0x51fbf*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51fc0*4 +0x02000000,0xd8fd); +reg_write( DDR_REG_BASE +0x51fc1*4 +0x02000000,0xee08); +reg_write( DDR_REG_BASE +0x51fc2*4 +0x02000000,0xb5a); +reg_write( DDR_REG_BASE +0x51fc3*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51fc4*4 +0x02000000,0x720c); +reg_write( DDR_REG_BASE +0x51fc5*4 +0x02000000,0x9fa); +reg_write( DDR_REG_BASE +0x51fc6*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51fc7*4 +0x02000000,0xd8fe); +reg_write( DDR_REG_BASE +0x51fc8*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51fc9*4 +0x02000000,0x813); +reg_write( DDR_REG_BASE +0x51fca*4 +0x02000000,0x13e); +reg_write( DDR_REG_BASE +0x51fcb*4 +0x02000000,0x760c); +reg_write( DDR_REG_BASE +0x51fcc*4 +0x02000000,0xb46); +reg_write( DDR_REG_BASE +0x51fcd*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x51fce*4 +0x02000000,0x9e6); +reg_write( DDR_REG_BASE +0x51fcf*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51fd0*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x51fd1*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51fd2*4 +0x02000000,0x815); +reg_write( DDR_REG_BASE +0x51fd3*4 +0x02000000,0x51); +reg_write( DDR_REG_BASE +0x51fd4*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51fd5*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51fd6*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51fd7*4 +0x02000000,0x19); +reg_write( DDR_REG_BASE +0x51fd8*4 +0x02000000,0xe884); +reg_write( DDR_REG_BASE +0x51fd9*4 +0x02000000,0xb2e); +reg_write( DDR_REG_BASE +0x51fda*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51fdb*4 +0x02000000,0xd80d); +reg_write( DDR_REG_BASE +0x51fdc*4 +0x02000000,0xed07); +reg_write( DDR_REG_BASE +0x51fdd*4 +0x02000000,0xb26); +reg_write( DDR_REG_BASE +0x51fde*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51fdf*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x51fe0*4 +0x02000000,0x9c2); +reg_write( DDR_REG_BASE +0x51fe1*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51fe2*4 +0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x51fe3*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51fe4*4 +0x02000000,0x825); +reg_write( DDR_REG_BASE +0x51fe5*4 +0x02000000,0x27f); +reg_write( DDR_REG_BASE +0x51fe6*4 +0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x51fe7*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51fe8*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51fe9*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51fea*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51feb*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x51fec*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51fed*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51fee*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51fef*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51ff0*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51ff1*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51ff2*4 +0x02000000,0xe040); +reg_write( DDR_REG_BASE +0x51ff3*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x51ff4*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x51ff5*4 +0x02000000,0xf040); +reg_write( DDR_REG_BASE +0x51ff6*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51ff7*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51ff8*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51ff9*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51ffa*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51ffb*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51ffc*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x51ffd*4 +0x02000000,0xb8e2); +reg_write( DDR_REG_BASE +0x51ffe*4 +0x02000000,0x25ca); +reg_write( DDR_REG_BASE +0x51fff*4 +0x02000000,0x13e1); +reg_write( DDR_REG_BASE +0x52000*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52001*4 +0x02000000,0xae00); +reg_write( DDR_REG_BASE +0x52002*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52003*4 +0x02000000,0x84f); +reg_write( DDR_REG_BASE +0x52004*4 +0x02000000,0x95); +reg_write( DDR_REG_BASE +0x52005*4 +0x02000000,0xe81d); +reg_write( DDR_REG_BASE +0x52006*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52007*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x52008*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52009*4 +0x02000000,0x58); +reg_write( DDR_REG_BASE +0x5200a*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x5200b*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5200c*4 +0x02000000,0xf213); +reg_write( DDR_REG_BASE +0x5200d*4 +0x02000000,0xe76); +reg_write( DDR_REG_BASE +0x5200e*4 +0x02000000,0xfe4f); +reg_write( DDR_REG_BASE +0x5200f*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x52010*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52011*4 +0x02000000,0xaf6); +reg_write( DDR_REG_BASE +0x52012*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52013*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52014*4 +0x02000000,0xd8a); +reg_write( DDR_REG_BASE +0x52015*4 +0x02000000,0xfe4f); +reg_write( DDR_REG_BASE +0x52016*4 +0x02000000,0xdc2); +reg_write( DDR_REG_BASE +0x52017*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x52018*4 +0x02000000,0x1e01); +reg_write( DDR_REG_BASE +0x52019*4 +0x02000000,0x1003); +reg_write( DDR_REG_BASE +0x5201a*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x5201b*4 +0x02000000,0xdf6); +reg_write( DDR_REG_BASE +0x5201c*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x5201d*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x5201e*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x5201f*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52020*4 +0x02000000,0xf1e1); +reg_write( DDR_REG_BASE +0x52021*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52022*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x52023*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52024*4 +0x02000000,0x25); +reg_write( DDR_REG_BASE +0x52025*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52026*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52027*4 +0x02000000,0xf5e7); +reg_write( DDR_REG_BASE +0x52028*4 +0x02000000,0xf1f7); +reg_write( DDR_REG_BASE +0x52029*4 +0x02000000,0xac6); +reg_write( DDR_REG_BASE +0x5202a*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x5202b*4 +0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x5202c*4 +0x02000000,0xca09); +reg_write( DDR_REG_BASE +0x5202d*4 +0x02000000,0xe885); +reg_write( DDR_REG_BASE +0x5202e*4 +0x02000000,0x93e); +reg_write( DDR_REG_BASE +0x5202f*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52030*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52031*4 +0x02000000,0x922); +reg_write( DDR_REG_BASE +0x52032*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52033*4 +0x02000000,0xd809); +reg_write( DDR_REG_BASE +0x52034*4 +0x02000000,0xca09); +reg_write( DDR_REG_BASE +0x52035*4 +0x02000000,0xe837); +reg_write( DDR_REG_BASE +0x52036*4 +0x02000000,0xd925); +reg_write( DDR_REG_BASE +0x52037*4 +0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x52038*4 +0x02000000,0x8900); +reg_write( DDR_REG_BASE +0x52039*4 +0x02000000,0x1133); +reg_write( DDR_REG_BASE +0x5203a*4 +0x02000000,0x8f); +reg_write( DDR_REG_BASE +0x5203b*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x5203c*4 +0x02000000,0x7f05); +reg_write( DDR_REG_BASE +0x5203d*4 +0x02000000,0xf022); +reg_write( DDR_REG_BASE +0x5203e*4 +0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x5203f*4 +0x02000000,0x17c1); +reg_write( DDR_REG_BASE +0x52040*4 +0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x52041*4 +0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x52042*4 +0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x52043*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x52044*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52045*4 +0x02000000,0x78eb); +reg_write( DDR_REG_BASE +0x52046*4 +0x02000000,0xf217); +reg_write( DDR_REG_BASE +0x52047*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52048*4 +0x02000000,0xdda); +reg_write( DDR_REG_BASE +0x52049*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x5204a*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5204b*4 +0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x5204c*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x5204d*4 +0x02000000,0x7bcf); +reg_write( DDR_REG_BASE +0x5204e*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5204f*4 +0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x52050*4 +0x02000000,0x93a); +reg_write( DDR_REG_BASE +0x52051*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52052*4 +0x02000000,0x4378); +reg_write( DDR_REG_BASE +0x52053*4 +0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x52054*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52055*4 +0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x52056*4 +0x02000000,0x92e); +reg_write( DDR_REG_BASE +0x52057*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52058*4 +0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x52059*4 +0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x5205a*4 +0x02000000,0x9da); +reg_write( DDR_REG_BASE +0x5205b*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x5205c*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x5205d*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x5205e*4 +0x02000000,0xec1); +reg_write( DDR_REG_BASE +0x5205f*4 +0x02000000,0x90b4); +reg_write( DDR_REG_BASE +0x52060*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52061*4 +0x02000000,0x8da); +reg_write( DDR_REG_BASE +0x52062*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52063*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52064*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52065*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x52066*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52067*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52068*4 +0x02000000,0xb8e5); +reg_write( DDR_REG_BASE +0x52069*4 +0x02000000,0x9f8); +reg_write( DDR_REG_BASE +0x5206a*4 +0x02000000,0xfe82); +reg_write( DDR_REG_BASE +0x5206b*4 +0x02000000,0xb02); +reg_write( DDR_REG_BASE +0x5206c*4 +0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x5206d*4 +0x02000000,0xca04); +reg_write( DDR_REG_BASE +0x5206e*4 +0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x5206f*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52070*4 +0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x52071*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x52072*4 +0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x52073*4 +0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x52074*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52075*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52076*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52077*4 +0x02000000,0x7965); +reg_write( DDR_REG_BASE +0x52078*4 +0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x52079*4 +0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x5207a*4 +0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x5207b*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x5207c*4 +0x02000000,0x140); +reg_write( DDR_REG_BASE +0x5207d*4 +0x02000000,0x2332); +reg_write( DDR_REG_BASE +0x5207e*4 +0x02000000,0x1f81); +reg_write( DDR_REG_BASE +0x5207f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52080*4 +0x02000000,0x7f0); +reg_write( DDR_REG_BASE +0x52081*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x52082*4 +0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x52083*4 +0x02000000,0xb420); +reg_write( DDR_REG_BASE +0x52084*4 +0x02000000,0xbdf); +reg_write( DDR_REG_BASE +0x52085*4 +0x02000000,0x8214); +reg_write( DDR_REG_BASE +0x52086*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x52087*4 +0x02000000,0xad7); +reg_write( DDR_REG_BASE +0x52088*4 +0x02000000,0x8024); +reg_write( DDR_REG_BASE +0x52089*4 +0x02000000,0x2316); +reg_write( DDR_REG_BASE +0x5208a*4 +0x02000000,0x308b); +reg_write( DDR_REG_BASE +0x5208b*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5208c*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5208d*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x5208e*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x5208f*4 +0x02000000,0xe032); +reg_write( DDR_REG_BASE +0x52090*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52091*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x52092*4 +0x02000000,0x9de); +reg_write( DDR_REG_BASE +0x52093*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52094*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52095*4 +0x02000000,0xcfa); +reg_write( DDR_REG_BASE +0x52096*4 +0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x52097*4 +0x02000000,0x82e); +reg_write( DDR_REG_BASE +0x52098*4 +0x02000000,0x160); +reg_write( DDR_REG_BASE +0x52099*4 +0x02000000,0xd807); +reg_write( DDR_REG_BASE +0x5209a*4 +0x02000000,0x23ab); +reg_write( DDR_REG_BASE +0x5209b*4 +0x02000000,0x30c4); +reg_write( DDR_REG_BASE +0x5209c*4 +0x02000000,0x7fff); +reg_write( DDR_REG_BASE +0x5209d*4 +0x02000000,0xf000); +reg_write( DDR_REG_BASE +0x5209e*4 +0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x5209f*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x520a0*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x520a1*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x520a2*4 +0x02000000,0x9500); +reg_write( DDR_REG_BASE +0x520a3*4 +0x02000000,0xb8a1); +reg_write( DDR_REG_BASE +0x520a4*4 +0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x520a5*4 +0x02000000,0xf3e); +reg_write( DDR_REG_BASE +0x520a6*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x520a7*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x520a8*4 +0x02000000,0xd81f); +reg_write( DDR_REG_BASE +0x520a9*4 +0x02000000,0xf36); +reg_write( DDR_REG_BASE +0x520aa*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x520ab*4 +0x02000000,0x1df6); +reg_write( DDR_REG_BASE +0x520ac*4 +0x02000000,0x105d); +reg_write( DDR_REG_BASE +0x520ad*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x520ae*4 +0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x520af*4 +0x02000000,0xf2a); +reg_write( DDR_REG_BASE +0x520b0*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x520b1*4 +0x02000000,0xd81f); +reg_write( DDR_REG_BASE +0x520b2*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x520b3*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x520b4*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x520b5*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x520b6*4 +0x02000000,0xf1a); +reg_write( DDR_REG_BASE +0x520b7*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x520b8*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x520b9*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x520ba*4 +0x02000000,0x150a); +reg_write( DDR_REG_BASE +0x520bb*4 +0x02000000,0x9700); +reg_write( DDR_REG_BASE +0x520bc*4 +0x02000000,0xb881); +reg_write( DDR_REG_BASE +0x520bd*4 +0x02000000,0x1d0a); +reg_write( DDR_REG_BASE +0x520be*4 +0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x520bf*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x520c0*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x520c1*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x520c2*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x520c3*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x520c4*4 +0x02000000,0x12); +reg_write( DDR_REG_BASE +0x520c5*4 +0x02000000,0x218c); +reg_write( DDR_REG_BASE +0x520c6*4 +0x02000000,0x8203); +reg_write( DDR_REG_BASE +0x520c7*4 +0x02000000,0xfcc); +reg_write( DDR_REG_BASE +0x520c8*4 +0x02000000,0x10e); +reg_write( DDR_REG_BASE +0x520c9*4 +0x02000000,0x80e); +reg_write( DDR_REG_BASE +0x520ca*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x520cb*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x520cc*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x520cd*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x520ce*4 +0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x520cf*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x520d0*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x520d1*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x520d2*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x520d3*4 +0x02000000,0x81b); +reg_write( DDR_REG_BASE +0x520d4*4 +0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x520d5*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x520d6*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x520d7*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x520d8*4 +0x02000000,0xe036); +reg_write( DDR_REG_BASE +0x520d9*4 +0x02000000,0xed6); +reg_write( DDR_REG_BASE +0x520da*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x520db*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x520dc*4 +0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x520dd*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x520de*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x520df*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x520e0*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x520e1*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x520e2*4 +0x02000000,0xf2); +reg_write( DDR_REG_BASE +0x520e3*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x520e4*4 +0x02000000,0x45); +reg_write( DDR_REG_BASE +0x520e5*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x520e6*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x520e7*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x520e8*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x520e9*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x520ea*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x520eb*4 +0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x520ec*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x520ed*4 +0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x520ee*4 +0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x520ef*4 +0x02000000,0xdc08); +reg_write( DDR_REG_BASE +0x520f0*4 +0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x520f1*4 +0x02000000,0xc01); +reg_write( DDR_REG_BASE +0x520f2*4 +0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x520f3*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x520f4*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x520f5*4 +0x02000000,0x4d); +reg_write( DDR_REG_BASE +0x520f6*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x520f7*4 +0x02000000,0x4378); +reg_write( DDR_REG_BASE +0x520f8*4 +0x02000000,0xc24e); +reg_write( DDR_REG_BASE +0x520f9*4 +0x02000000,0xae2); +reg_write( DDR_REG_BASE +0x520fa*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x520fb*4 +0x02000000,0x4728); +reg_write( DDR_REG_BASE +0x520fc*4 +0x02000000,0x2353); +reg_write( DDR_REG_BASE +0x520fd*4 +0x02000000,0x30c0); +reg_write( DDR_REG_BASE +0x520fe*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x520ff*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52100*4 +0x02000000,0xe0c4); +reg_write( DDR_REG_BASE +0x52101*4 +0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x52102*4 +0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x52103*4 +0x02000000,0xd9f0); +reg_write( DDR_REG_BASE +0x52104*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x52105*4 +0x02000000,0xc07); +reg_write( DDR_REG_BASE +0x52106*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x52107*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x52108*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52109*4 +0x02000000,0x6c1); +reg_write( DDR_REG_BASE +0x5210a*4 +0x02000000,0xba8b); +reg_write( DDR_REG_BASE +0x5210b*4 +0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x5210c*4 +0x02000000,0xc096); +reg_write( DDR_REG_BASE +0x5210d*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5210e*4 +0x02000000,0xda28); +reg_write( DDR_REG_BASE +0x5210f*4 +0x02000000,0x9be); +reg_write( DDR_REG_BASE +0x52110*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x52111*4 +0x02000000,0xc396); +reg_write( DDR_REG_BASE +0x52112*4 +0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x52113*4 +0x02000000,0x6c7); +reg_write( DDR_REG_BASE +0x52114*4 +0x02000000,0x20b8); +reg_write( DDR_REG_BASE +0x52115*4 +0x02000000,0xfc3); +reg_write( DDR_REG_BASE +0x52116*4 +0x02000000,0xc06d); +reg_write( DDR_REG_BASE +0x52117*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52118*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52119*4 +0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x5211a*4 +0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x5211b*4 +0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x5211c*4 +0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x5211d*4 +0x02000000,0x14a0); +reg_write( DDR_REG_BASE +0x5211e*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x5211f*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52120*4 +0x02000000,0xc346); +reg_write( DDR_REG_BASE +0x52121*4 +0x02000000,0xc04f); +reg_write( DDR_REG_BASE +0x52122*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52123*4 +0x02000000,0x149c); +reg_write( DDR_REG_BASE +0x52124*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x52125*4 +0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x52126*4 +0x02000000,0x17c3); +reg_write( DDR_REG_BASE +0x52127*4 +0x02000000,0x1c30); +reg_write( DDR_REG_BASE +0x52128*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52129*4 +0x02000000,0xc050); +reg_write( DDR_REG_BASE +0x5212a*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5212b*4 +0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x5212c*4 +0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x5212d*4 +0x02000000,0xc10e); +reg_write( DDR_REG_BASE +0x5212e*4 +0x02000000,0x1c25); +reg_write( DDR_REG_BASE +0x5212f*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x52130*4 +0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x52131*4 +0x02000000,0xeb06); +reg_write( DDR_REG_BASE +0x52132*4 +0x02000000,0xbb61); +reg_write( DDR_REG_BASE +0x52133*4 +0x02000000,0xb01); +reg_write( DDR_REG_BASE +0x52134*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x52135*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52136*4 +0x02000000,0x1c24); +reg_write( DDR_REG_BASE +0x52137*4 +0x02000000,0x3003); +reg_write( DDR_REG_BASE +0x52138*4 +0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x52139*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5213a*4 +0x02000000,0xc748); +reg_write( DDR_REG_BASE +0x5213b*4 +0x02000000,0x1c1c); +reg_write( DDR_REG_BASE +0x5213c*4 +0x02000000,0x3103); +reg_write( DDR_REG_BASE +0x5213d*4 +0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x5213e*4 +0x02000000,0x200f); +reg_write( DDR_REG_BASE +0x5213f*4 +0x02000000,0x380); +reg_write( DDR_REG_BASE +0x52140*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52141*4 +0x02000000,0x9da); +reg_write( DDR_REG_BASE +0x52142*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52143*4 +0x02000000,0xc054); +reg_write( DDR_REG_BASE +0x52144*4 +0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x52145*4 +0x02000000,0xb863); +reg_write( DDR_REG_BASE +0x52146*4 +0x02000000,0xc052); +reg_write( DDR_REG_BASE +0x52147*4 +0x02000000,0x7314); +reg_write( DDR_REG_BASE +0x52148*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52149*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5214a*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x5214b*4 +0x02000000,0x48); +reg_write( DDR_REG_BASE +0x5214c*4 +0x02000000,0x2d); +reg_write( DDR_REG_BASE +0x5214d*4 +0x02000000,0xc051); +reg_write( DDR_REG_BASE +0x5214e*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5214f*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52150*4 +0x02000000,0x1ea); +reg_write( DDR_REG_BASE +0x52151*4 +0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x52152*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52153*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x52154*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52155*4 +0x02000000,0xc0ff); +reg_write( DDR_REG_BASE +0x52156*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52157*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52158*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52159*4 +0x02000000,0x3f00); +reg_write( DDR_REG_BASE +0x5215a*4 +0x02000000,0x2080); +reg_write( DDR_REG_BASE +0x5215b*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5215c*4 +0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x5215d*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x5215e*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5215f*4 +0x02000000,0x76c4); +reg_write( DDR_REG_BASE +0x52160*4 +0x02000000,0x900f); +reg_write( DDR_REG_BASE +0x52161*4 +0x02000000,0xe022); +reg_write( DDR_REG_BASE +0x52162*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52163*4 +0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x52164*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52165*4 +0x02000000,0xee); +reg_write( DDR_REG_BASE +0x52166*4 +0x02000000,0x2050); +reg_write( DDR_REG_BASE +0x52167*4 +0x02000000,0x141); +reg_write( DDR_REG_BASE +0x52168*4 +0x02000000,0xb885); +reg_write( DDR_REG_BASE +0x52169*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5216a*4 +0x02000000,0x7044); +reg_write( DDR_REG_BASE +0x5216b*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x5216c*4 +0x02000000,0xe0ee); +reg_write( DDR_REG_BASE +0x5216d*4 +0x02000000,0xc051); +reg_write( DDR_REG_BASE +0x5216e*4 +0x02000000,0x1498); +reg_write( DDR_REG_BASE +0x5216f*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x52170*4 +0x02000000,0xc055); +reg_write( DDR_REG_BASE +0x52171*4 +0x02000000,0x1494); +reg_write( DDR_REG_BASE +0x52172*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x52173*4 +0x02000000,0xc053); +reg_write( DDR_REG_BASE +0x52174*4 +0x02000000,0x996); +reg_write( DDR_REG_BASE +0x52175*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52176*4 +0x02000000,0xc083); +reg_write( DDR_REG_BASE +0x52177*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x52178*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52179*4 +0x02000000,0x7cb); +reg_write( DDR_REG_BASE +0x5217a*4 +0x02000000,0x8e61); +reg_write( DDR_REG_BASE +0x5217b*4 +0x02000000,0x8e20); +reg_write( DDR_REG_BASE +0x5217c*4 +0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x5217d*4 +0x02000000,0xc210); +reg_write( DDR_REG_BASE +0x5217e*4 +0x02000000,0x7a34); +reg_write( DDR_REG_BASE +0x5217f*4 +0x02000000,0x9200); +reg_write( DDR_REG_BASE +0x52180*4 +0x02000000,0xe889); +reg_write( DDR_REG_BASE +0x52181*4 +0x02000000,0xc096); +reg_write( DDR_REG_BASE +0x52182*4 +0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x52183*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x52184*4 +0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x52185*4 +0x02000000,0x833); +reg_write( DDR_REG_BASE +0x52186*4 +0x02000000,0x2042); +reg_write( DDR_REG_BASE +0x52187*4 +0x02000000,0x800); +reg_write( DDR_REG_BASE +0x52188*4 +0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x52189*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x5218a*4 +0x02000000,0xbe7); +reg_write( DDR_REG_BASE +0x5218b*4 +0x02000000,0x8045); +reg_write( DDR_REG_BASE +0x5218c*4 +0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x5218d*4 +0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x5218e*4 +0x02000000,0x839); +reg_write( DDR_REG_BASE +0x5218f*4 +0x02000000,0xb5); +reg_write( DDR_REG_BASE +0x52190*4 +0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x52191*4 +0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x52192*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52193*4 +0x02000000,0xf0f0); +reg_write( DDR_REG_BASE +0x52194*4 +0x02000000,0x43db); +reg_write( DDR_REG_BASE +0x52195*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52196*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x52197*4 +0x02000000,0x43e1); +reg_write( DDR_REG_BASE +0x52198*4 +0x02000000,0x737f); +reg_write( DDR_REG_BASE +0x52199*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x5219a*4 +0x02000000,0x41e1); +reg_write( DDR_REG_BASE +0x5219b*4 +0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x5219c*4 +0x02000000,0xe42); +reg_write( DDR_REG_BASE +0x5219d*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5219e*4 +0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x5219f*4 +0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x521a0*4 +0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x521a1*4 +0x02000000,0x33c2); +reg_write( DDR_REG_BASE +0x521a2*4 +0x02000000,0xd808); +reg_write( DDR_REG_BASE +0x521a3*4 +0x02000000,0x41e1); +reg_write( DDR_REG_BASE +0x521a4*4 +0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x521a5*4 +0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x521a6*4 +0x02000000,0xe2e); +reg_write( DDR_REG_BASE +0x521a7*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x521a8*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x521a9*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x521aa*4 +0x02000000,0xb3a); +reg_write( DDR_REG_BASE +0x521ab*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x521ac*4 +0x02000000,0xc083); +reg_write( DDR_REG_BASE +0x521ad*4 +0x02000000,0x8e61); +reg_write( DDR_REG_BASE +0x521ae*4 +0x02000000,0x8e20); +reg_write( DDR_REG_BASE +0x521af*4 +0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x521b0*4 +0x02000000,0xc20f); +reg_write( DDR_REG_BASE +0x521b1*4 +0x02000000,0x7a34); +reg_write( DDR_REG_BASE +0x521b2*4 +0x02000000,0x9200); +reg_write( DDR_REG_BASE +0x521b3*4 +0x02000000,0x815); +reg_write( DDR_REG_BASE +0x521b4*4 +0x02000000,0x7f1); +reg_write( DDR_REG_BASE +0x521b5*4 +0x02000000,0xc096); +reg_write( DDR_REG_BASE +0x521b6*4 +0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x521b7*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x521b8*4 +0x02000000,0x809); +reg_write( DDR_REG_BASE +0x521b9*4 +0x02000000,0x833); +reg_write( DDR_REG_BASE +0x521ba*4 +0x02000000,0xe020); +reg_write( DDR_REG_BASE +0x521bb*4 +0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x521bc*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x521bd*4 +0x02000000,0xbe9); +reg_write( DDR_REG_BASE +0x521be*4 +0x02000000,0x8045); +reg_write( DDR_REG_BASE +0x521bf*4 +0x02000000,0xc012); +reg_write( DDR_REG_BASE +0x521c0*4 +0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x521c1*4 +0x02000000,0x114); +reg_write( DDR_REG_BASE +0x521c2*4 +0x02000000,0xc76); +reg_write( DDR_REG_BASE +0x521c3*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x521c4*4 +0x02000000,0xc014); +reg_write( DDR_REG_BASE +0x521c5*4 +0x02000000,0xc013); +reg_write( DDR_REG_BASE +0x521c6*4 +0x02000000,0xe807); +reg_write( DDR_REG_BASE +0x521c7*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x521c8*4 +0x02000000,0x36); +reg_write( DDR_REG_BASE +0x521c9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x521ca*4 +0x02000000,0xb2a); +reg_write( DDR_REG_BASE +0x521cb*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x521cc*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x521cd*4 +0x02000000,0x8ee0); +reg_write( DDR_REG_BASE +0x521ce*4 +0x02000000,0xf035); +reg_write( DDR_REG_BASE +0x521cf*4 +0x02000000,0xc010); +reg_write( DDR_REG_BASE +0x521d0*4 +0x02000000,0x7dfd); +reg_write( DDR_REG_BASE +0x521d1*4 +0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x521d2*4 +0x02000000,0x3c2); +reg_write( DDR_REG_BASE +0x521d3*4 +0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x521d4*4 +0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x521d5*4 +0x02000000,0x3c3); +reg_write( DDR_REG_BASE +0x521d6*4 +0x02000000,0x6358); +reg_write( DDR_REG_BASE +0x521d7*4 +0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x521d8*4 +0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x521d9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x521da*4 +0x02000000,0x2049); +reg_write( DDR_REG_BASE +0x521db*4 +0x02000000,0x7c1); +reg_write( DDR_REG_BASE +0x521dc*4 +0x02000000,0xc015); +reg_write( DDR_REG_BASE +0x521dd*4 +0x02000000,0x78f4); +reg_write( DDR_REG_BASE +0x521de*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x521df*4 +0x02000000,0x4b50); +reg_write( DDR_REG_BASE +0x521e0*4 +0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x521e1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x521e2*4 +0x02000000,0xc04e); +reg_write( DDR_REG_BASE +0x521e3*4 +0x02000000,0xc013); +reg_write( DDR_REG_BASE +0x521e4*4 +0x02000000,0xe812); +reg_write( DDR_REG_BASE +0x521e5*4 +0x02000000,0xc010); +reg_write( DDR_REG_BASE +0x521e6*4 +0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x521e7*4 +0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x521e8*4 +0x02000000,0x3c2); +reg_write( DDR_REG_BASE +0x521e9*4 +0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x521ea*4 +0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x521eb*4 +0x02000000,0x3c0); +reg_write( DDR_REG_BASE +0x521ec*4 +0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x521ed*4 +0x02000000,0xc240); +reg_write( DDR_REG_BASE +0x521ee*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x521ef*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x521f0*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x521f1*4 +0x02000000,0x38); +reg_write( DDR_REG_BASE +0x521f2*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x521f3*4 +0x02000000,0xada); +reg_write( DDR_REG_BASE +0x521f4*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x521f5*4 +0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x521f6*4 +0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x521f7*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x521f8*4 +0x02000000,0x39); +reg_write( DDR_REG_BASE +0x521f9*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x521fa*4 +0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x521fb*4 +0x02000000,0x780e); +reg_write( DDR_REG_BASE +0x521fc*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x521fd*4 +0x02000000,0x207f); +reg_write( DDR_REG_BASE +0x521fe*4 +0x02000000,0x140); +reg_write( DDR_REG_BASE +0x521ff*4 +0x02000000,0xd56); +reg_write( DDR_REG_BASE +0x52200*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52201*4 +0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x52202*4 +0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x52203*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x52204*4 +0x02000000,0x897); +reg_write( DDR_REG_BASE +0x52205*4 +0x02000000,0x83e5); +reg_write( DDR_REG_BASE +0x52206*4 +0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x52207*4 +0x02000000,0x105b); +reg_write( DDR_REG_BASE +0x52208*4 +0x02000000,0xc012); +reg_write( DDR_REG_BASE +0x52209*4 +0x02000000,0x835); +reg_write( DDR_REG_BASE +0x5220a*4 +0x02000000,0x115); +reg_write( DDR_REG_BASE +0x5220b*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x5220c*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x5220d*4 +0x02000000,0x1ea); +reg_write( DDR_REG_BASE +0x5220e*4 +0x02000000,0x9200); +reg_write( DDR_REG_BASE +0x5220f*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52210*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52211*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52212*4 +0x02000000,0xc0ff); +reg_write( DDR_REG_BASE +0x52213*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52214*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52215*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52216*4 +0x02000000,0x3f00); +reg_write( DDR_REG_BASE +0x52217*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52218*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52219*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5221a*4 +0x02000000,0xfc00); +reg_write( DDR_REG_BASE +0x5221b*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x5221c*4 +0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x5221d*4 +0x02000000,0xc011); +reg_write( DDR_REG_BASE +0x5221e*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5221f*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52220*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52221*4 +0x02000000,0xe0ee); +reg_write( DDR_REG_BASE +0x52222*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52223*4 +0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x52224*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52225*4 +0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x52226*4 +0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x52227*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x52228*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52229*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x5222a*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5222b*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5222c*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5222d*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5222e*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5222f*4 +0x02000000,0xc1ad); +reg_write( DDR_REG_BASE +0x52230*4 +0x02000000,0xc248); +reg_write( DDR_REG_BASE +0x52231*4 +0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x52232*4 +0x02000000,0xc16); +reg_write( DDR_REG_BASE +0x52233*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x52234*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x52235*4 +0x02000000,0x2342); +reg_write( DDR_REG_BASE +0x52236*4 +0x02000000,0x30cd); +reg_write( DDR_REG_BASE +0x52237*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x52238*4 +0x02000000,0x97e); +reg_write( DDR_REG_BASE +0x52239*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x5223a*4 +0x02000000,0x7eaf); +reg_write( DDR_REG_BASE +0x5223b*4 +0x02000000,0xd33); +reg_write( DDR_REG_BASE +0x5223c*4 +0x02000000,0x1134); +reg_write( DDR_REG_BASE +0x5223d*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5223e*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5223f*4 +0x02000000,0xd82); +reg_write( DDR_REG_BASE +0x52240*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52241*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52242*4 +0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x52243*4 +0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x52244*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52245*4 +0x02000000,0xd981); +reg_write( DDR_REG_BASE +0x52246*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52247*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52248*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52249*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5224a*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5224b*4 +0x02000000,0xb98e); +reg_write( DDR_REG_BASE +0x5224c*4 +0x02000000,0xe3e); +reg_write( DDR_REG_BASE +0x5224d*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5224e*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5224f*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52250*4 +0x02000000,0xdf6); +reg_write( DDR_REG_BASE +0x52251*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52252*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52253*4 +0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x52254*4 +0x02000000,0x203c); +reg_write( DDR_REG_BASE +0x52255*4 +0x02000000,0x381); +reg_write( DDR_REG_BASE +0x52256*4 +0x02000000,0x2342); +reg_write( DDR_REG_BASE +0x52257*4 +0x02000000,0x304e); +reg_write( DDR_REG_BASE +0x52258*4 +0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x52259*4 +0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x5225a*4 +0x02000000,0x273c); +reg_write( DDR_REG_BASE +0x5225b*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x5225c*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x5225d*4 +0x02000000,0x8040); +reg_write( DDR_REG_BASE +0x5225e*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x5225f*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52260*4 +0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x52261*4 +0x02000000,0x1222); +reg_write( DDR_REG_BASE +0x52262*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52263*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x52264*4 +0x02000000,0x20cf); +reg_write( DDR_REG_BASE +0x52265*4 +0x02000000,0xa2); +reg_write( DDR_REG_BASE +0x52266*4 +0x02000000,0x74b5); +reg_write( DDR_REG_BASE +0x52267*4 +0x02000000,0xc26); +reg_write( DDR_REG_BASE +0x52268*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x52269*4 +0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x5226a*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x5226b*4 +0x02000000,0xc2a); +reg_write( DDR_REG_BASE +0x5226c*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5226d*4 +0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x5226e*4 +0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x5226f*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52270*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52271*4 +0x02000000,0x2710); +reg_write( DDR_REG_BASE +0x52272*4 +0x02000000,0xc1a); +reg_write( DDR_REG_BASE +0x52273*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x52274*4 +0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x52275*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52276*4 +0x02000000,0x900f); +reg_write( DDR_REG_BASE +0x52277*4 +0x02000000,0xe0c0); +reg_write( DDR_REG_BASE +0x52278*4 +0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x52279*4 +0x02000000,0xb1e0); +reg_write( DDR_REG_BASE +0x5227a*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5227b*4 +0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x5227c*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x5227d*4 +0x02000000,0xf0f0); +reg_write( DDR_REG_BASE +0x5227e*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x5227f*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x52280*4 +0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x52281*4 +0x02000000,0x78c0); +reg_write( DDR_REG_BASE +0x52282*4 +0x02000000,0xb105); +reg_write( DDR_REG_BASE +0x52283*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52284*4 +0x02000000,0x772c); +reg_write( DDR_REG_BASE +0x52285*4 +0x02000000,0xc145); +reg_write( DDR_REG_BASE +0x52286*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52287*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x52288*4 +0x02000000,0x70fd); +reg_write( DDR_REG_BASE +0x52289*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x5228a*4 +0x02000000,0x773c); +reg_write( DDR_REG_BASE +0x5228b*4 +0x02000000,0xc10a); +reg_write( DDR_REG_BASE +0x5228c*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x5228d*4 +0x02000000,0x2114); +reg_write( DDR_REG_BASE +0x5228e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5228f*4 +0x02000000,0x48e8); +reg_write( DDR_REG_BASE +0x52290*4 +0x02000000,0xb9c0); +reg_write( DDR_REG_BASE +0x52291*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x52292*4 +0x02000000,0xe2b); +reg_write( DDR_REG_BASE +0x52293*4 +0x02000000,0x10b5); +reg_write( DDR_REG_BASE +0x52294*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52295*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x52296*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52297*4 +0x02000000,0xf0f0); +reg_write( DDR_REG_BASE +0x52298*4 +0x02000000,0x7bf0); +reg_write( DDR_REG_BASE +0x52299*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x5229a*4 +0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x5229b*4 +0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x5229c*4 +0x02000000,0xc42); +reg_write( DDR_REG_BASE +0x5229d*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5229e*4 +0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x5229f*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x522a0*4 +0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x522a1*4 +0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x522a2*4 +0x02000000,0x7b10); +reg_write( DDR_REG_BASE +0x522a3*4 +0x02000000,0xd808); +reg_write( DDR_REG_BASE +0x522a4*4 +0x02000000,0xc32); +reg_write( DDR_REG_BASE +0x522a5*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x522a6*4 +0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x522a7*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x522a8*4 +0x02000000,0xe030); +reg_write( DDR_REG_BASE +0x522a9*4 +0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x522aa*4 +0x02000000,0x234f); +reg_write( DDR_REG_BASE +0x522ab*4 +0x02000000,0x3040); +reg_write( DDR_REG_BASE +0x522ac*4 +0x02000000,0x899); +reg_write( DDR_REG_BASE +0x522ad*4 +0x02000000,0xb1); +reg_write( DDR_REG_BASE +0x522ae*4 +0x02000000,0x73b5); +reg_write( DDR_REG_BASE +0x522af*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x522b0*4 +0x02000000,0xb8c1); +reg_write( DDR_REG_BASE +0x522b1*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x522b2*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x522b3*4 +0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x522b4*4 +0x02000000,0xc96); +reg_write( DDR_REG_BASE +0x522b5*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x522b6*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x522b7*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x522b8*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x522b9*4 +0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x522ba*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x522bb*4 +0x02000000,0xb98e); +reg_write( DDR_REG_BASE +0x522bc*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x522bd*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x522be*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x522bf*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x522c0*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x522c1*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x522c2*4 +0x02000000,0xd52); +reg_write( DDR_REG_BASE +0x522c3*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x522c4*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x522c5*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x522c6*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x522c7*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x522c8*4 +0x02000000,0x7f0f); +reg_write( DDR_REG_BASE +0x522c9*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x522ca*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x522cb*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x522cc*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x522cd*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x522ce*4 +0x02000000,0xd3a); +reg_write( DDR_REG_BASE +0x522cf*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x522d0*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x522d1*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x522d2*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x522d3*4 +0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x522d4*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x522d5*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x522d6*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x522d7*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x522d8*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x522d9*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x522da*4 +0x02000000,0xd22); +reg_write( DDR_REG_BASE +0x522db*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x522dc*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x522dd*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x522de*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x522df*4 +0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x522e0*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x522e1*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x522e2*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x522e3*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x522e4*4 +0x02000000,0xdb28); +reg_write( DDR_REG_BASE +0x522e5*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x522e6*4 +0x02000000,0xd0a); +reg_write( DDR_REG_BASE +0x522e7*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x522e8*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x522e9*4 +0x02000000,0xf52); +reg_write( DDR_REG_BASE +0x522ea*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x522eb*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x522ec*4 +0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x522ed*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x522ee*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x522ef*4 +0x02000000,0x3100); +reg_write( DDR_REG_BASE +0x522f0*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x522f1*4 +0x02000000,0x22a); +reg_write( DDR_REG_BASE +0x522f2*4 +0x02000000,0x21); +reg_write( DDR_REG_BASE +0x522f3*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x522f4*4 +0x02000000,0x2f3); +reg_write( DDR_REG_BASE +0x522f5*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x522f6*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x522f7*4 +0x02000000,0x3441); +reg_write( DDR_REG_BASE +0x522f8*4 +0x02000000,0x44c); +reg_write( DDR_REG_BASE +0x522f9*4 +0x02000000,0x2d); +reg_write( DDR_REG_BASE +0x522fa*4 +0x02000000,0x7177); +reg_write( DDR_REG_BASE +0x522fb*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x522fc*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x522fd*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x522fe*4 +0x02000000,0x13); +reg_write( DDR_REG_BASE +0x522ff*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52300*4 +0x02000000,0x5d4); +reg_write( DDR_REG_BASE +0x52301*4 +0x02000000,0x21); +reg_write( DDR_REG_BASE +0x52302*4 +0x02000000,0x7377); +reg_write( DDR_REG_BASE +0x52303*4 +0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x52304*4 +0x02000000,0x269a); +reg_write( DDR_REG_BASE +0x52305*4 +0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x52306*4 +0x02000000,0x7e05); +reg_write( DDR_REG_BASE +0x52307*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52308*4 +0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x52309*4 +0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x5230a*4 +0x02000000,0x43c1); +reg_write( DDR_REG_BASE +0x5230b*4 +0x02000000,0xb66); +reg_write( DDR_REG_BASE +0x5230c*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5230d*4 +0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x5230e*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x5230f*4 +0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x52310*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52311*4 +0x02000000,0xbde); +reg_write( DDR_REG_BASE +0x52312*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52313*4 +0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x52314*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52315*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52316*4 +0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x52317*4 +0x02000000,0x7f0f); +reg_write( DDR_REG_BASE +0x52318*4 +0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x52319*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5231a*4 +0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x5231b*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5231c*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5231d*4 +0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x5231e*4 +0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x5231f*4 +0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x52320*4 +0x02000000,0xc96); +reg_write( DDR_REG_BASE +0x52321*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52322*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52323*4 +0x02000000,0xd828); +reg_write( DDR_REG_BASE +0x52324*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52325*4 +0x02000000,0xd808); +reg_write( DDR_REG_BASE +0x52326*4 +0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x52327*4 +0x02000000,0x801); +reg_write( DDR_REG_BASE +0x52328*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x52329*4 +0x02000000,0x7edd); +reg_write( DDR_REG_BASE +0x5232a*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5232b*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5232c*4 +0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x5232d*4 +0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x5232e*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5232f*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52330*4 +0x02000000,0xc76); +reg_write( DDR_REG_BASE +0x52331*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52332*4 +0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x52333*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52334*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52335*4 +0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x52336*4 +0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x52337*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52338*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52339*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x5233a*4 +0x02000000,0x33c1); +reg_write( DDR_REG_BASE +0x5233b*4 +0x02000000,0xc62); +reg_write( DDR_REG_BASE +0x5233c*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5233d*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5233e*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5233f*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x52340*4 +0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x52341*4 +0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x52342*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52343*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52344*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x52345*4 +0x02000000,0x3501); +reg_write( DDR_REG_BASE +0x52346*4 +0x02000000,0xc4a); +reg_write( DDR_REG_BASE +0x52347*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52348*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52349*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5234a*4 +0x02000000,0xc02); +reg_write( DDR_REG_BASE +0x5234b*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5234c*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5234d*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5234e*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5234f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52350*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52351*4 +0x02000000,0xdae0); +reg_write( DDR_REG_BASE +0x52352*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x52353*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52354*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52355*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52356*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52357*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52358*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x52359*4 +0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x5235a*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x5235b*4 +0x02000000,0x7204); +reg_write( DDR_REG_BASE +0x5235c*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x5235d*4 +0x02000000,0xb340); +reg_write( DDR_REG_BASE +0x5235e*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x5235f*4 +0x02000000,0x485); +reg_write( DDR_REG_BASE +0x52360*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52361*4 +0x02000000,0xb3e); +reg_write( DDR_REG_BASE +0x52362*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52363*4 +0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x52364*4 +0x02000000,0xe5a); +reg_write( DDR_REG_BASE +0x52365*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52366*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52367*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x52368*4 +0x02000000,0xbe90); +reg_write( DDR_REG_BASE +0x52369*4 +0x02000000,0xf968); +reg_write( DDR_REG_BASE +0x5236a*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5236b*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5236c*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5236d*4 +0x02000000,0xbfe); +reg_write( DDR_REG_BASE +0x5236e*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5236f*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52370*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52371*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52372*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52373*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52374*4 +0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x52375*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52376*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52377*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52378*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52379*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5237a*4 +0x02000000,0xbe2); +reg_write( DDR_REG_BASE +0x5237b*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5237c*4 +0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x5237d*4 +0x02000000,0xf95e); +reg_write( DDR_REG_BASE +0x5237e*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5237f*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52380*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52381*4 +0x02000000,0xbd6); +reg_write( DDR_REG_BASE +0x52382*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52383*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52384*4 +0x02000000,0xf957); +reg_write( DDR_REG_BASE +0x52385*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52386*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52387*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52388*4 +0x02000000,0xbc6); +reg_write( DDR_REG_BASE +0x52389*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5238a*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5238b*4 +0x02000000,0xf957); +reg_write( DDR_REG_BASE +0x5238c*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5238d*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5238e*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5238f*4 +0x02000000,0xbba); +reg_write( DDR_REG_BASE +0x52390*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52391*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52392*4 +0x02000000,0xf950); +reg_write( DDR_REG_BASE +0x52393*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52394*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52395*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52396*4 +0x02000000,0xbaa); +reg_write( DDR_REG_BASE +0x52397*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52398*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52399*4 +0x02000000,0xf950); +reg_write( DDR_REG_BASE +0x5239a*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5239b*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5239c*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5239d*4 +0x02000000,0xb9e); +reg_write( DDR_REG_BASE +0x5239e*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5239f*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523a0*4 +0x02000000,0xf949); +reg_write( DDR_REG_BASE +0x523a1*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523a2*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x523a3*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523a4*4 +0x02000000,0xb8e); +reg_write( DDR_REG_BASE +0x523a5*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523a6*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523a7*4 +0x02000000,0xf949); +reg_write( DDR_REG_BASE +0x523a8*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523a9*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x523aa*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523ab*4 +0x02000000,0xb82); +reg_write( DDR_REG_BASE +0x523ac*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523ad*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523ae*4 +0x02000000,0xf942); +reg_write( DDR_REG_BASE +0x523af*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523b0*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x523b1*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523b2*4 +0x02000000,0xb72); +reg_write( DDR_REG_BASE +0x523b3*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523b4*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523b5*4 +0x02000000,0xf942); +reg_write( DDR_REG_BASE +0x523b6*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523b7*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x523b8*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523b9*4 +0x02000000,0xb66); +reg_write( DDR_REG_BASE +0x523ba*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523bb*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523bc*4 +0x02000000,0xf93b); +reg_write( DDR_REG_BASE +0x523bd*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523be*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x523bf*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523c0*4 +0x02000000,0xb56); +reg_write( DDR_REG_BASE +0x523c1*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523c2*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523c3*4 +0x02000000,0xf93b); +reg_write( DDR_REG_BASE +0x523c4*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523c5*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x523c6*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523c7*4 +0x02000000,0xb4a); +reg_write( DDR_REG_BASE +0x523c8*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523c9*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523ca*4 +0x02000000,0xf934); +reg_write( DDR_REG_BASE +0x523cb*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523cc*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x523cd*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523ce*4 +0x02000000,0xb3a); +reg_write( DDR_REG_BASE +0x523cf*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523d0*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523d1*4 +0x02000000,0xf934); +reg_write( DDR_REG_BASE +0x523d2*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523d3*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x523d4*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523d5*4 +0x02000000,0xb2e); +reg_write( DDR_REG_BASE +0x523d6*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523d7*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523d8*4 +0x02000000,0xf92d); +reg_write( DDR_REG_BASE +0x523d9*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523da*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x523db*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523dc*4 +0x02000000,0xb1e); +reg_write( DDR_REG_BASE +0x523dd*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523de*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523df*4 +0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x523e0*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x523e1*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x523e2*4 +0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x523e3*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x523e4*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523e5*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x523e6*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523e7*4 +0x02000000,0xb0a); +reg_write( DDR_REG_BASE +0x523e8*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523e9*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523ea*4 +0x02000000,0x79dd); +reg_write( DDR_REG_BASE +0x523eb*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x523ec*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x523ed*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x523ee*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x523ef*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x523f0*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x523f1*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523f2*4 +0x02000000,0xaf2); +reg_write( DDR_REG_BASE +0x523f3*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523f4*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523f5*4 +0x02000000,0xf91c); +reg_write( DDR_REG_BASE +0x523f6*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523f7*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x523f8*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523f9*4 +0x02000000,0xae6); +reg_write( DDR_REG_BASE +0x523fa*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523fb*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523fc*4 +0x02000000,0xd0e); +reg_write( DDR_REG_BASE +0x523fd*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x523fe*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x523ff*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52400*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52401*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52402*4 +0x02000000,0x3bd); +reg_write( DDR_REG_BASE +0x52403*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52404*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52405*4 +0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x52406*4 +0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x52407*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52408*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52409*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5240a*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5240b*4 +0x02000000,0xac2); +reg_write( DDR_REG_BASE +0x5240c*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5240d*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5240e*4 +0x02000000,0xf90c); +reg_write( DDR_REG_BASE +0x5240f*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52410*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52411*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x52412*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52413*4 +0x02000000,0xab2); +reg_write( DDR_REG_BASE +0x52414*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52415*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52416*4 +0x02000000,0xf905); +reg_write( DDR_REG_BASE +0x52417*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x52418*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52419*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5241a*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5241b*4 +0x02000000,0xaa2); +reg_write( DDR_REG_BASE +0x5241c*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5241d*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5241e*4 +0x02000000,0xf8fe); +reg_write( DDR_REG_BASE +0x5241f*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52420*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52421*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52422*4 +0x02000000,0xa92); +reg_write( DDR_REG_BASE +0x52423*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52424*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52425*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x52426*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52427*4 +0x02000000,0xf900); +reg_write( DDR_REG_BASE +0x52428*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52429*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5242a*4 +0x02000000,0xa82); +reg_write( DDR_REG_BASE +0x5242b*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5242c*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5242d*4 +0x02000000,0xf8fa); +reg_write( DDR_REG_BASE +0x5242e*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x5242f*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52430*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52431*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52432*4 +0x02000000,0xa72); +reg_write( DDR_REG_BASE +0x52433*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52434*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52435*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x52436*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52437*4 +0x02000000,0xf8f5); +reg_write( DDR_REG_BASE +0x52438*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52439*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5243a*4 +0x02000000,0xa62); +reg_write( DDR_REG_BASE +0x5243b*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5243c*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5243d*4 +0x02000000,0xf8ef); +reg_write( DDR_REG_BASE +0x5243e*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5243f*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52440*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52441*4 +0x02000000,0xa56); +reg_write( DDR_REG_BASE +0x52442*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52443*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52444*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52445*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52446*4 +0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x52447*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52448*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52449*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x5244a*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5244b*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x5244c*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x5244d*4 +0x02000000,0xa3e); +reg_write( DDR_REG_BASE +0x5244e*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5244f*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52450*4 +0x02000000,0xf8e8); +reg_write( DDR_REG_BASE +0x52451*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x52452*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52453*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52454*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52455*4 +0x02000000,0xa2e); +reg_write( DDR_REG_BASE +0x52456*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52457*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52458*4 +0x02000000,0xf8e1); +reg_write( DDR_REG_BASE +0x52459*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5245a*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5245b*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5245c*4 +0x02000000,0xa1e); +reg_write( DDR_REG_BASE +0x5245d*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5245e*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5245f*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52460*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52461*4 +0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x52462*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52463*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x52464*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52465*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52466*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52467*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52468*4 +0x02000000,0xa06); +reg_write( DDR_REG_BASE +0x52469*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5246a*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5246b*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x5246c*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x5246d*4 +0x02000000,0xf8da); +reg_write( DDR_REG_BASE +0x5246e*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5246f*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52470*4 +0x02000000,0x9f6); +reg_write( DDR_REG_BASE +0x52471*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52472*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52473*4 +0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x52474*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52475*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52476*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52477*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52478*4 +0x02000000,0xc305); +reg_write( DDR_REG_BASE +0x52479*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5247a*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5247b*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5247c*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5247d*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5247e*4 +0x02000000,0x9da); +reg_write( DDR_REG_BASE +0x5247f*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52480*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52481*4 +0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x52482*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x52483*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52484*4 +0x02000000,0x2100); +reg_write( DDR_REG_BASE +0x52485*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52486*4 +0x02000000,0xf26c); +reg_write( DDR_REG_BASE +0x52487*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52488*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52489*4 +0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x5248a*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x5248b*4 +0x02000000,0x4358); +reg_write( DDR_REG_BASE +0x5248c*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5248d*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5248e*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5248f*4 +0x02000000,0x9ba); +reg_write( DDR_REG_BASE +0x52490*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52491*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52492*4 +0x02000000,0xf8ca); +reg_write( DDR_REG_BASE +0x52493*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52494*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52495*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x52496*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52497*4 +0x02000000,0x9aa); +reg_write( DDR_REG_BASE +0x52498*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52499*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5249a*4 +0x02000000,0xf8bd); +reg_write( DDR_REG_BASE +0x5249b*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x5249c*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x5249d*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5249e*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5249f*4 +0x02000000,0x99a); +reg_write( DDR_REG_BASE +0x524a0*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524a1*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524a2*4 +0x02000000,0xf8cb); +reg_write( DDR_REG_BASE +0x524a3*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x524a4*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x524a5*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x524a6*4 +0x02000000,0x98a); +reg_write( DDR_REG_BASE +0x524a7*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524a8*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524a9*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x524aa*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x524ab*4 +0x02000000,0xf8be); +reg_write( DDR_REG_BASE +0x524ac*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x524ad*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x524ae*4 +0x02000000,0x97a); +reg_write( DDR_REG_BASE +0x524af*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524b0*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524b1*4 +0x02000000,0xf8b2); +reg_write( DDR_REG_BASE +0x524b2*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x524b3*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x524b4*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x524b5*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x524b6*4 +0x02000000,0x96a); +reg_write( DDR_REG_BASE +0x524b7*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524b8*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524b9*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x524ba*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x524bb*4 +0x02000000,0xf8ad); +reg_write( DDR_REG_BASE +0x524bc*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x524bd*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x524be*4 +0x02000000,0x95a); +reg_write( DDR_REG_BASE +0x524bf*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524c0*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524c1*4 +0x02000000,0xf8bc); +reg_write( DDR_REG_BASE +0x524c2*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x524c3*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x524c4*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x524c5*4 +0x02000000,0x94e); +reg_write( DDR_REG_BASE +0x524c6*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524c7*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524c8*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x524c9*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x524ca*4 +0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x524cb*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x524cc*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x524cd*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x524ce*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x524cf*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x524d0*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x524d1*4 +0x02000000,0x936); +reg_write( DDR_REG_BASE +0x524d2*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524d3*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524d4*4 +0x02000000,0xf8a0); +reg_write( DDR_REG_BASE +0x524d5*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x524d6*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x524d7*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x524d8*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x524d9*4 +0x02000000,0x926); +reg_write( DDR_REG_BASE +0x524da*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524db*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524dc*4 +0x02000000,0xf8ae); +reg_write( DDR_REG_BASE +0x524dd*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x524de*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x524df*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x524e0*4 +0x02000000,0x916); +reg_write( DDR_REG_BASE +0x524e1*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524e2*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524e3*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x524e4*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x524e5*4 +0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x524e6*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x524e7*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x524e8*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x524e9*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x524ea*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x524eb*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x524ec*4 +0x02000000,0x8fe); +reg_write( DDR_REG_BASE +0x524ed*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524ee*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524ef*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x524f0*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x524f1*4 +0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x524f2*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x524f3*4 +0x02000000,0x3441); +reg_write( DDR_REG_BASE +0x524f4*4 +0x02000000,0xf890); +reg_write( DDR_REG_BASE +0x524f5*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x524f6*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x524f7*4 +0x02000000,0x8ea); +reg_write( DDR_REG_BASE +0x524f8*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524f9*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524fa*4 +0x02000000,0xc305); +reg_write( DDR_REG_BASE +0x524fb*4 +0x02000000,0xf88a); +reg_write( DDR_REG_BASE +0x524fc*4 +0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x524fd*4 +0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x524fe*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x524ff*4 +0x02000000,0x8da); +reg_write( DDR_REG_BASE +0x52500*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52501*4 +0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x52502*4 +0x02000000,0xf880); +reg_write( DDR_REG_BASE +0x52503*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x52504*4 +0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x52505*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52506*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52507*4 +0x02000000,0x8ca); +reg_write( DDR_REG_BASE +0x52508*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52509*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5250a*4 +0x02000000,0xf891); +reg_write( DDR_REG_BASE +0x5250b*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5250c*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5250d*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5250e*4 +0x02000000,0x8ba); +reg_write( DDR_REG_BASE +0x5250f*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52510*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52511*4 +0x02000000,0xae6); +reg_write( DDR_REG_BASE +0x52512*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52513*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52514*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52515*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52516*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52517*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52518*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x52519*4 +0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x5251a*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5251b*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x5251c*4 +0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x5251d*4 +0x02000000,0xf0c7); +reg_write( DDR_REG_BASE +0x5251e*4 +0x02000000,0xf4c8); +reg_write( DDR_REG_BASE +0x5251f*4 +0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x52520*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x52521*4 +0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x52522*4 +0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x52523*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x52524*4 +0x02000000,0x4918); +reg_write( DDR_REG_BASE +0x52525*4 +0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x52526*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x52527*4 +0x02000000,0x4918); +reg_write( DDR_REG_BASE +0x52528*4 +0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x52529*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5252a*4 +0x02000000,0xf062); +reg_write( DDR_REG_BASE +0x5252b*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5252c*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x5252d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5252e*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x5252f*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52530*4 +0x02000000,0x7dc0); +reg_write( DDR_REG_BASE +0x52531*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52532*4 +0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x52533*4 +0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x52534*4 +0x02000000,0xf12); +reg_write( DDR_REG_BASE +0x52535*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52536*4 +0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x52537*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52538*4 +0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x52539*4 +0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x5253a*4 +0x02000000,0x7b10); +reg_write( DDR_REG_BASE +0x5253b*4 +0x02000000,0xd808); +reg_write( DDR_REG_BASE +0x5253c*4 +0x02000000,0xf02); +reg_write( DDR_REG_BASE +0x5253d*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x5253e*4 +0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x5253f*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52540*4 +0x02000000,0xf7e); +reg_write( DDR_REG_BASE +0x52541*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52542*4 +0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x52543*4 +0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x52544*4 +0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x52545*4 +0x02000000,0xf865); +reg_write( DDR_REG_BASE +0x52546*4 +0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x52547*4 +0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x52548*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x52549*4 +0x02000000,0x846); +reg_write( DDR_REG_BASE +0x5254a*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5254b*4 +0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x5254c*4 +0x02000000,0xf85e); +reg_write( DDR_REG_BASE +0x5254d*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5254e*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5254f*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52550*4 +0x02000000,0x836); +reg_write( DDR_REG_BASE +0x52551*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52552*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52553*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52554*4 +0x02000000,0x736f); +reg_write( DDR_REG_BASE +0x52555*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52556*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52557*4 +0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x52558*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52559*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5255a*4 +0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x5255b*4 +0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x5255c*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x5255d*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x5255e*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5255f*4 +0x02000000,0x81a); +reg_write( DDR_REG_BASE +0x52560*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52561*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x52562*4 +0x02000000,0x3281); +reg_write( DDR_REG_BASE +0x52563*4 +0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x52564*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52565*4 +0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x52566*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52567*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52568*4 +0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x52569*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x5256a*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x5256b*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5256c*4 +0x02000000,0xffe); +reg_write( DDR_REG_BASE +0x5256d*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5256e*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5256f*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52570*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52571*4 +0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x52572*4 +0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x52573*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x52574*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52575*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52576*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52577*4 +0x02000000,0xfea); +reg_write( DDR_REG_BASE +0x52578*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52579*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x5257a*4 +0x02000000,0x3281); +reg_write( DDR_REG_BASE +0x5257b*4 +0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x5257c*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x5257d*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5257e*4 +0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x5257f*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52580*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52581*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52582*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52583*4 +0x02000000,0xfd2); +reg_write( DDR_REG_BASE +0x52584*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52585*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52586*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52587*4 +0x02000000,0xf8a); +reg_write( DDR_REG_BASE +0x52588*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52589*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5258a*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5258b*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5258c*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5258d*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x5258e*4 +0x02000000,0x232f); +reg_write( DDR_REG_BASE +0x5258f*4 +0x02000000,0x3007); +reg_write( DDR_REG_BASE +0x52590*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52591*4 +0x02000000,0x837); +reg_write( DDR_REG_BASE +0x52592*4 +0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x52593*4 +0x02000000,0x7bf0); +reg_write( DDR_REG_BASE +0x52594*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52595*4 +0x02000000,0xed6); +reg_write( DDR_REG_BASE +0x52596*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52597*4 +0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x52598*4 +0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x52599*4 +0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x5259a*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5259b*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5259c*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5259d*4 +0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x5259e*4 +0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x5259f*4 +0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x525a0*4 +0x02000000,0xf96); +reg_write( DDR_REG_BASE +0x525a1*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x525a2*4 +0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x525a3*4 +0x02000000,0x9de); +reg_write( DDR_REG_BASE +0x525a4*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x525a5*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x525a6*4 +0x02000000,0xf831); +reg_write( DDR_REG_BASE +0x525a7*4 +0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x525a8*4 +0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x525a9*4 +0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x525aa*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x525ab*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x525ac*4 +0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x525ad*4 +0x02000000,0xca08); +reg_write( DDR_REG_BASE +0x525ae*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x525af*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x525b0*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x525b1*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x525b2*4 +0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x525b3*4 +0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x525b4*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x525b5*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x525b6*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x525b7*4 +0x02000000,0xf6a); +reg_write( DDR_REG_BASE +0x525b8*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x525b9*4 +0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x525ba*4 +0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x525bb*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x525bc*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x525bd*4 +0x02000000,0x2054); +reg_write( DDR_REG_BASE +0x525be*4 +0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x525bf*4 +0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x525c0*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x525c1*4 +0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x525c2*4 +0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x525c3*4 +0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x525c4*4 +0x02000000,0xf4e); +reg_write( DDR_REG_BASE +0x525c5*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x525c6*4 +0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x525c7*4 +0x02000000,0xf81e); +reg_write( DDR_REG_BASE +0x525c8*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x525c9*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x525ca*4 +0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x525cb*4 +0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x525cc*4 +0x02000000,0xf3e); +reg_write( DDR_REG_BASE +0x525cd*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x525ce*4 +0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x525cf*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x525d0*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x525d1*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x525d2*4 +0x02000000,0xdb50); +reg_write( DDR_REG_BASE +0x525d3*4 +0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x525d4*4 +0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x525d5*4 +0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x525d6*4 +0x02000000,0xf2a); +reg_write( DDR_REG_BASE +0x525d7*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x525d8*4 +0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x525d9*4 +0x02000000,0x956); +reg_write( DDR_REG_BASE +0x525da*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x525db*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x525dc*4 +0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x525dd*4 +0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x525de*4 +0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x525df*4 +0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x525e0*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x525e1*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x525e2*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x525e3*4 +0x02000000,0xf12); +reg_write( DDR_REG_BASE +0x525e4*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x525e5*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x525e6*4 +0x02000000,0xc0ad); +reg_write( DDR_REG_BASE +0x525e7*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x525e8*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x525e9*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x525ea*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x525eb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x525ec*4 +0x02000000,0xaaaa); +reg_write( DDR_REG_BASE +0x525ed*4 +0x02000000,0xf214); +reg_write( DDR_REG_BASE +0x525ee*4 +0x02000000,0xb17); +reg_write( DDR_REG_BASE +0x525ef*4 +0x02000000,0x3190); +reg_write( DDR_REG_BASE +0x525f0*4 +0x02000000,0xb1b); +reg_write( DDR_REG_BASE +0x525f1*4 +0x02000000,0x3150); +reg_write( DDR_REG_BASE +0x525f2*4 +0x02000000,0xb1d); +reg_write( DDR_REG_BASE +0x525f3*4 +0x02000000,0x3131); +reg_write( DDR_REG_BASE +0x525f4*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x525f5*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x525f6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x525f7*4 +0x02000000,0xcccc); +reg_write( DDR_REG_BASE +0x525f8*4 +0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x525f9*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x525fa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x525fb*4 +0x02000000,0x8282); +reg_write( DDR_REG_BASE +0x525fc*4 +0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x525fd*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x525fe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x525ff*4 +0x02000000,0xb2b2); +reg_write( DDR_REG_BASE +0x52600*4 +0x02000000,0x20f); +reg_write( DDR_REG_BASE +0x52601*4 +0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x52602*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52603*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52604*4 +0x02000000,0xb98f); +reg_write( DDR_REG_BASE +0x52605*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52606*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52607*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52608*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52609*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5260a*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5260b*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5260c*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5260d*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5260e*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5260f*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52610*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52611*4 +0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x52612*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52613*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52614*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52615*4 +0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x52616*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52617*4 +0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x52618*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52619*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5261a*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5261b*4 +0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x5261c*4 +0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x5261d*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x5261e*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5261f*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52620*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52621*4 +0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x52622*4 +0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x52623*4 +0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x52624*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52625*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52626*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52627*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52628*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52629*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x5262a*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5262b*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5262c*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5262d*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5262e*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5262f*4 +0x02000000,0xdb30); +reg_write( DDR_REG_BASE +0x52630*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52631*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52632*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52633*4 +0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x52634*4 +0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x52635*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52636*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52637*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52638*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52639*4 +0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x5263a*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x5263b*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x5263c*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5263d*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5263e*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5263f*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52640*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52641*4 +0x02000000,0xc1a6); +reg_write( DDR_REG_BASE +0x52642*4 +0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x52643*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52644*4 +0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x52645*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52646*4 +0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x52647*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x52648*4 +0x02000000,0xffd); +reg_write( DDR_REG_BASE +0x52649*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x5264a*4 +0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x5264b*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5264c*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5264d*4 +0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x5264e*4 +0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x5264f*4 +0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x52650*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52651*4 +0x02000000,0x8e19); +reg_write( DDR_REG_BASE +0x52652*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52653*4 +0x02000000,0x8e10); +reg_write( DDR_REG_BASE +0x52654*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52655*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52656*4 +0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x52657*4 +0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x52658*4 +0x02000000,0x9001); +reg_write( DDR_REG_BASE +0x52659*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5265a*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5265b*4 +0x02000000,0xe88a); +reg_write( DDR_REG_BASE +0x5265c*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5265d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5265e*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x5265f*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x52660*4 +0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x52661*4 +0x02000000,0xcfe); +reg_write( DDR_REG_BASE +0x52662*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52663*4 +0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x52664*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52665*4 +0x02000000,0x956); +reg_write( DDR_REG_BASE +0x52666*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52667*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52668*4 +0x02000000,0x8608); +reg_write( DDR_REG_BASE +0x52669*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x5266a*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5266b*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5266c*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5266d*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5266e*4 +0x02000000,0xe064); +reg_write( DDR_REG_BASE +0x5266f*4 +0x02000000,0xce6); +reg_write( DDR_REG_BASE +0x52670*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x52671*4 +0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x52672*4 +0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x52673*4 +0x02000000,0xaba); +reg_write( DDR_REG_BASE +0x52674*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x52675*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52676*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52677*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52678*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52679*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x5267a*4 +0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x5267b*4 +0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x5267c*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5267d*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5267e*4 +0x02000000,0xe064); +reg_write( DDR_REG_BASE +0x5267f*4 +0x02000000,0x2042); +reg_write( DDR_REG_BASE +0x52680*4 +0x02000000,0x98f); +reg_write( DDR_REG_BASE +0x52681*4 +0x02000000,0xb7a0); +reg_write( DDR_REG_BASE +0x52682*4 +0x02000000,0xb7a0); +reg_write( DDR_REG_BASE +0x52683*4 +0x02000000,0x1f9c); +reg_write( DDR_REG_BASE +0x52684*4 +0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x52685*4 +0x02000000,0x1f9b); +reg_write( DDR_REG_BASE +0x52686*4 +0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x52687*4 +0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x52688*4 +0x02000000,0x9f84); +reg_write( DDR_REG_BASE +0x52689*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5268a*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x5268b*4 +0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x5268c*4 +0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x5268d*4 +0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x5268e*4 +0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x5268f*4 +0x02000000,0xd7a); +reg_write( DDR_REG_BASE +0x52690*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52691*4 +0x02000000,0x960e); +reg_write( DDR_REG_BASE +0x52692*4 +0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x52693*4 +0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x52694*4 +0x02000000,0xcaa); +reg_write( DDR_REG_BASE +0x52695*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52696*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52697*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52698*4 +0x02000000,0x8ee); +reg_write( DDR_REG_BASE +0x52699*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5269a*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x5269b*4 +0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x5269c*4 +0x02000000,0xa66); +reg_write( DDR_REG_BASE +0x5269d*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5269e*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5269f*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x526a0*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x526a1*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x526a2*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x526a3*4 +0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x526a4*4 +0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x526a5*4 +0x02000000,0xb7a0); +reg_write( DDR_REG_BASE +0x526a6*4 +0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x526a7*4 +0x02000000,0x9f84); +reg_write( DDR_REG_BASE +0x526a8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x526a9*4 +0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x526aa*4 +0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x526ab*4 +0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x526ac*4 +0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x526ad*4 +0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x526ae*4 +0x02000000,0xd3a); +reg_write( DDR_REG_BASE +0x526af*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x526b0*4 +0x02000000,0x960a); +reg_write( DDR_REG_BASE +0x526b1*4 +0x02000000,0x8e58); +reg_write( DDR_REG_BASE +0x526b2*4 +0x02000000,0x8601); +reg_write( DDR_REG_BASE +0x526b3*4 +0x02000000,0xbde); +reg_write( DDR_REG_BASE +0x526b4*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x526b5*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x526b6*4 +0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x526b7*4 +0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x526b8*4 +0x02000000,0xc62); +reg_write( DDR_REG_BASE +0x526b9*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x526ba*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x526bb*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x526bc*4 +0x02000000,0x8a6); +reg_write( DDR_REG_BASE +0x526bd*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x526be*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x526bf*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x526c0*4 +0x02000000,0xe807); +reg_write( DDR_REG_BASE +0x526c1*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x526c2*4 +0x02000000,0xfba); +reg_write( DDR_REG_BASE +0x526c3*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x526c4*4 +0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x526c5*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x526c6*4 +0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x526c7*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x526c8*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x526c9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x526ca*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x526cb*4 +0x02000000,0x4220); +reg_write( DDR_REG_BASE +0x526cc*4 +0x02000000,0x7414); +reg_write( DDR_REG_BASE +0x526cd*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x526ce*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x526cf*4 +0x02000000,0xfffe); +reg_write( DDR_REG_BASE +0x526d0*4 +0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x526d1*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x526d2*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x526d3*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x526d4*4 +0x02000000,0xc16); +reg_write( DDR_REG_BASE +0x526d5*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x526d6*4 +0x02000000,0x4320); +reg_write( DDR_REG_BASE +0x526d7*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x526d8*4 +0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x526d9*4 +0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x526da*4 +0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x526db*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x526dc*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x526dd*4 +0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x526de*4 +0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x526df*4 +0x02000000,0x9001); +reg_write( DDR_REG_BASE +0x526e0*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x526e1*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x526e2*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x526e3*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x526e4*4 +0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x526e5*4 +0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x526e6*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x526e7*4 +0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x526e8*4 +0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x526e9*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x526ea*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x526eb*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x526ec*4 +0x02000000,0x7504); +reg_write( DDR_REG_BASE +0x526ed*4 +0x02000000,0x9c6); +reg_write( DDR_REG_BASE +0x526ee*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x526ef*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x526f0*4 +0x02000000,0x8608); +reg_write( DDR_REG_BASE +0x526f1*4 +0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x526f2*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x526f3*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x526f4*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x526f5*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x526f6*4 +0x02000000,0xe064); +reg_write( DDR_REG_BASE +0x526f7*4 +0x02000000,0xbd6); +reg_write( DDR_REG_BASE +0x526f8*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x526f9*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x526fa*4 +0x02000000,0x6c4); +reg_write( DDR_REG_BASE +0x526fb*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x526fc*4 +0x02000000,0x1f00); +reg_write( DDR_REG_BASE +0x526fd*4 +0x02000000,0x16c4); +reg_write( DDR_REG_BASE +0x526fe*4 +0x02000000,0x1f9c); +reg_write( DDR_REG_BASE +0x526ff*4 +0x02000000,0x16dc); +reg_write( DDR_REG_BASE +0x52700*4 +0x02000000,0x1f9b); +reg_write( DDR_REG_BASE +0x52701*4 +0x02000000,0x16dc); +reg_write( DDR_REG_BASE +0x52702*4 +0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x52703*4 +0x02000000,0x9f84); +reg_write( DDR_REG_BASE +0x52704*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52705*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x52706*4 +0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x52707*4 +0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x52708*4 +0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x52709*4 +0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x5270a*4 +0x02000000,0x960e); +reg_write( DDR_REG_BASE +0x5270b*4 +0x02000000,0xc82); +reg_write( DDR_REG_BASE +0x5270c*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5270d*4 +0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x5270e*4 +0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x5270f*4 +0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x52710*4 +0x02000000,0xbb2); +reg_write( DDR_REG_BASE +0x52711*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52712*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52713*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52714*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52715*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52716*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52717*4 +0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x52718*4 +0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x52719*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x5271a*4 +0x02000000,0xfea); +reg_write( DDR_REG_BASE +0x5271b*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5271c*4 +0x02000000,0x1f00); +reg_write( DDR_REG_BASE +0x5271d*4 +0x02000000,0x16c4); +reg_write( DDR_REG_BASE +0x5271e*4 +0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x5271f*4 +0x02000000,0x962); +reg_write( DDR_REG_BASE +0x52720*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x52721*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52722*4 +0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x52723*4 +0x02000000,0x9f84); +reg_write( DDR_REG_BASE +0x52724*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52725*4 +0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x52726*4 +0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x52727*4 +0x02000000,0x9344); +reg_write( DDR_REG_BASE +0x52728*4 +0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x52729*4 +0x02000000,0x9344); +reg_write( DDR_REG_BASE +0x5272a*4 +0x02000000,0x8605); +reg_write( DDR_REG_BASE +0x5272b*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5272c*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5272d*4 +0x02000000,0xc3e); +reg_write( DDR_REG_BASE +0x5272e*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5272f*4 +0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x52730*4 +0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x52731*4 +0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x52732*4 +0x02000000,0xb6e); +reg_write( DDR_REG_BASE +0x52733*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52734*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52735*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52736*4 +0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x52737*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52738*4 +0x02000000,0xece); +reg_write( DDR_REG_BASE +0x52739*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5273a*4 +0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x5273b*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5273c*4 +0x02000000,0x8e58); +reg_write( DDR_REG_BASE +0x5273d*4 +0x02000000,0x8603); +reg_write( DDR_REG_BASE +0x5273e*4 +0x02000000,0xac6); +reg_write( DDR_REG_BASE +0x5273f*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52740*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52741*4 +0x02000000,0xc0a6); +reg_write( DDR_REG_BASE +0x52742*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52743*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52744*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52745*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52746*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52747*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52748*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52749*4 +0x02000000,0xc1a8); +reg_write( DDR_REG_BASE +0x5274a*4 +0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x5274b*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5274c*4 +0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x5274d*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x5274e*4 +0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x5274f*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x52750*4 +0x02000000,0xffd); +reg_write( DDR_REG_BASE +0x52751*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x52752*4 +0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x52753*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52754*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52755*4 +0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x52756*4 +0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x52757*4 +0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x52758*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52759*4 +0x02000000,0x8e19); +reg_write( DDR_REG_BASE +0x5275a*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5275b*4 +0x02000000,0x8e10); +reg_write( DDR_REG_BASE +0x5275c*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5275d*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5275e*4 +0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x5275f*4 +0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x52760*4 +0x02000000,0x9001); +reg_write( DDR_REG_BASE +0x52761*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52762*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52763*4 +0x02000000,0xe88a); +reg_write( DDR_REG_BASE +0x52764*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52765*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52766*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x52767*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x52768*4 +0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x52769*4 +0x02000000,0xaee); +reg_write( DDR_REG_BASE +0x5276a*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x5276b*4 +0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x5276c*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x5276d*4 +0x02000000,0xf46); +reg_write( DDR_REG_BASE +0x5276e*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5276f*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52770*4 +0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x52771*4 +0x02000000,0x8608); +reg_write( DDR_REG_BASE +0x52772*4 +0x02000000,0x2179); +reg_write( DDR_REG_BASE +0x52773*4 +0x02000000,0x101); +reg_write( DDR_REG_BASE +0x52774*4 +0x02000000,0xb52); +reg_write( DDR_REG_BASE +0x52775*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52776*4 +0x02000000,0xc144); +reg_write( DDR_REG_BASE +0x52777*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52778*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52779*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x5277a*4 +0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x5277b*4 +0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x5277c*4 +0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x5277d*4 +0x02000000,0x8a6); +reg_write( DDR_REG_BASE +0x5277e*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5277f*4 +0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x52780*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52781*4 +0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x52782*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52783*4 +0x02000000,0xe03e); +reg_write( DDR_REG_BASE +0x52784*4 +0x02000000,0xb7a0); +reg_write( DDR_REG_BASE +0x52785*4 +0x02000000,0x1f9b); +reg_write( DDR_REG_BASE +0x52786*4 +0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x52787*4 +0x02000000,0x1f9c); +reg_write( DDR_REG_BASE +0x52788*4 +0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x52789*4 +0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x5278a*4 +0x02000000,0x9f84); +reg_write( DDR_REG_BASE +0x5278b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5278c*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x5278d*4 +0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x5278e*4 +0x02000000,0x9045); +reg_write( DDR_REG_BASE +0x5278f*4 +0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x52790*4 +0x02000000,0x9045); +reg_write( DDR_REG_BASE +0x52791*4 +0x02000000,0x960e); +reg_write( DDR_REG_BASE +0x52792*4 +0x02000000,0xb72); +reg_write( DDR_REG_BASE +0x52793*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52794*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52795*4 +0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x52796*4 +0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x52797*4 +0x02000000,0xaa6); +reg_write( DDR_REG_BASE +0x52798*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52799*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x5279a*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x5279b*4 +0x02000000,0xeea); +reg_write( DDR_REG_BASE +0x5279c*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5279d*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x5279e*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x5279f*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x527a0*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x527a1*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x527a2*4 +0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x527a3*4 +0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x527a4*4 +0x02000000,0xb7a0); +reg_write( DDR_REG_BASE +0x527a5*4 +0x02000000,0xb4e); +reg_write( DDR_REG_BASE +0x527a6*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x527a7*4 +0x02000000,0x960a); +reg_write( DDR_REG_BASE +0x527a8*4 +0x02000000,0x8e58); +reg_write( DDR_REG_BASE +0x527a9*4 +0x02000000,0x8602); +reg_write( DDR_REG_BASE +0x527aa*4 +0x02000000,0x9ee); +reg_write( DDR_REG_BASE +0x527ab*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x527ac*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x527ad*4 +0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x527ae*4 +0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x527af*4 +0x02000000,0xa76); +reg_write( DDR_REG_BASE +0x527b0*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x527b1*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x527b2*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x527b3*4 +0x02000000,0xeba); +reg_write( DDR_REG_BASE +0x527b4*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x527b5*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x527b6*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x527b7*4 +0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x527b8*4 +0x02000000,0xdce); +reg_write( DDR_REG_BASE +0x527b9*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x527ba*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x527bb*4 +0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x527bc*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x527bd*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x527be*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x527bf*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x527c0*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x527c1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x527c2*4 +0x02000000,0xfffe); +reg_write( DDR_REG_BASE +0x527c3*4 +0x02000000,0x7414); +reg_write( DDR_REG_BASE +0x527c4*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x527c5*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x527c6*4 +0x02000000,0x81); +reg_write( DDR_REG_BASE +0x527c7*4 +0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x527c8*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x527c9*4 +0x02000000,0xa2e); +reg_write( DDR_REG_BASE +0x527ca*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x527cb*4 +0x02000000,0x4320); +reg_write( DDR_REG_BASE +0x527cc*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x527cd*4 +0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x527ce*4 +0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x527cf*4 +0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x527d0*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x527d1*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x527d2*4 +0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x527d3*4 +0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x527d4*4 +0x02000000,0x9001); +reg_write( DDR_REG_BASE +0x527d5*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x527d6*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x527d7*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x527d8*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x527d9*4 +0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x527da*4 +0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x527db*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x527dc*4 +0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x527dd*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x527de*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x527df*4 +0x02000000,0xe007); +reg_write( DDR_REG_BASE +0x527e0*4 +0x02000000,0xfde); +reg_write( DDR_REG_BASE +0x527e1*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x527e2*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x527e3*4 +0x02000000,0x8608); +reg_write( DDR_REG_BASE +0x527e4*4 +0x02000000,0xa72); +reg_write( DDR_REG_BASE +0x527e5*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x527e6*4 +0x02000000,0xc104); +reg_write( DDR_REG_BASE +0x527e7*4 +0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x527e8*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x527e9*4 +0x02000000,0x1f00); +reg_write( DDR_REG_BASE +0x527ea*4 +0x02000000,0x16c4); +reg_write( DDR_REG_BASE +0x527eb*4 +0x02000000,0x1f9b); +reg_write( DDR_REG_BASE +0x527ec*4 +0x02000000,0x16dc); +reg_write( DDR_REG_BASE +0x527ed*4 +0x02000000,0x1f9c); +reg_write( DDR_REG_BASE +0x527ee*4 +0x02000000,0x16dc); +reg_write( DDR_REG_BASE +0x527ef*4 +0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x527f0*4 +0x02000000,0x9f84); +reg_write( DDR_REG_BASE +0x527f1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x527f2*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x527f3*4 +0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x527f4*4 +0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x527f5*4 +0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x527f6*4 +0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x527f7*4 +0x02000000,0x960e); +reg_write( DDR_REG_BASE +0x527f8*4 +0x02000000,0xaa6); +reg_write( DDR_REG_BASE +0x527f9*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x527fa*4 +0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x527fb*4 +0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x527fc*4 +0x02000000,0xc200); +reg_write( DDR_REG_BASE +0x527fd*4 +0x02000000,0x9da); +reg_write( DDR_REG_BASE +0x527fe*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x527ff*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52800*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x52801*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52802*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52803*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52804*4 +0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x52805*4 +0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x52806*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52807*4 +0x02000000,0xe12); +reg_write( DDR_REG_BASE +0x52808*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52809*4 +0x02000000,0x1f00); +reg_write( DDR_REG_BASE +0x5280a*4 +0x02000000,0x16c4); +reg_write( DDR_REG_BASE +0x5280b*4 +0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x5280c*4 +0x02000000,0xf86); +reg_write( DDR_REG_BASE +0x5280d*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5280e*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5280f*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52810*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52811*4 +0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x52812*4 +0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x52813*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52814*4 +0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x52815*4 +0x02000000,0x9344); +reg_write( DDR_REG_BASE +0x52816*4 +0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x52817*4 +0x02000000,0x9344); +reg_write( DDR_REG_BASE +0x52818*4 +0x02000000,0x8605); +reg_write( DDR_REG_BASE +0x52819*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5281a*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5281b*4 +0x02000000,0xa62); +reg_write( DDR_REG_BASE +0x5281c*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5281d*4 +0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x5281e*4 +0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x5281f*4 +0x02000000,0xc200); +reg_write( DDR_REG_BASE +0x52820*4 +0x02000000,0x992); +reg_write( DDR_REG_BASE +0x52821*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52822*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52823*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52824*4 +0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x52825*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52826*4 +0x02000000,0xcf2); +reg_write( DDR_REG_BASE +0x52827*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52828*4 +0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x52829*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5282a*4 +0x02000000,0x8e58); +reg_write( DDR_REG_BASE +0x5282b*4 +0x02000000,0x8603); +reg_write( DDR_REG_BASE +0x5282c*4 +0x02000000,0x8ea); +reg_write( DDR_REG_BASE +0x5282d*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5282e*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5282f*4 +0x02000000,0xc0a8); +reg_write( DDR_REG_BASE +0x52830*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52831*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52832*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52833*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52834*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52835*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52836*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52837*4 +0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x52838*4 +0x02000000,0x3503); +reg_write( DDR_REG_BASE +0x52839*4 +0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x5283a*4 +0x02000000,0xdf6); +reg_write( DDR_REG_BASE +0x5283b*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5283c*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5283d*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5283e*4 +0x02000000,0x7083); +reg_write( DDR_REG_BASE +0x5283f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52840*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52841*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52842*4 +0x02000000,0xc088); +reg_write( DDR_REG_BASE +0x52843*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x52844*4 +0x02000000,0xb52); +reg_write( DDR_REG_BASE +0x52845*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x52846*4 +0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x52847*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52848*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52849*4 +0x02000000,0x2100); +reg_write( DDR_REG_BASE +0x5284a*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5284b*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x5284c*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5284d*4 +0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x5284e*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5284f*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52850*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52851*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52852*4 +0x02000000,0xfec4); +reg_write( DDR_REG_BASE +0x52853*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x52854*4 +0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x52855*4 +0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x52856*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52857*4 +0x02000000,0x4898); +reg_write( DDR_REG_BASE +0x52858*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52859*4 +0x02000000,0x200); +reg_write( DDR_REG_BASE +0x5285a*4 +0x02000000,0xc145); +reg_write( DDR_REG_BASE +0x5285b*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5285c*4 +0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x5285d*4 +0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x5285e*4 +0x02000000,0x6941); +reg_write( DDR_REG_BASE +0x5285f*4 +0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x52860*4 +0x02000000,0x8); +reg_write( DDR_REG_BASE +0x52861*4 +0x02000000,0x44a9); +reg_write( DDR_REG_BASE +0x52862*4 +0x02000000,0xe805); +reg_write( DDR_REG_BASE +0x52863*4 +0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x52864*4 +0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x52865*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x52866*4 +0x02000000,0x7c9b); +reg_write( DDR_REG_BASE +0x52867*4 +0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x52868*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52869*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5286a*4 +0x02000000,0xe0c4); +reg_write( DDR_REG_BASE +0x5286b*4 +0x02000000,0xb080); +reg_write( DDR_REG_BASE +0x5286c*4 +0x02000000,0x4140); +reg_write( DDR_REG_BASE +0x5286d*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5286e*4 +0x02000000,0x9e1); +reg_write( DDR_REG_BASE +0x5286f*4 +0x02000000,0x8024); +reg_write( DDR_REG_BASE +0x52870*4 +0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x52871*4 +0x02000000,0x7c0); +reg_write( DDR_REG_BASE +0x52872*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x52873*4 +0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x52874*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52875*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52876*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52877*4 +0x02000000,0x709b); +reg_write( DDR_REG_BASE +0x52878*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52879*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x5287a*4 +0x02000000,0xc346); +reg_write( DDR_REG_BASE +0x5287b*4 +0x02000000,0xe598); +reg_write( DDR_REG_BASE +0x5287c*4 +0x02000000,0x1d8); +reg_write( DDR_REG_BASE +0x5287d*4 +0x02000000,0xd); +reg_write( DDR_REG_BASE +0x5287e*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5287f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52880*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x52881*4 +0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x52882*4 +0x02000000,0xf015); +reg_write( DDR_REG_BASE +0x52883*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52884*4 +0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x52885*4 +0x02000000,0x8c2); +reg_write( DDR_REG_BASE +0x52886*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52887*4 +0x02000000,0x7a05); +reg_write( DDR_REG_BASE +0x52888*4 +0x02000000,0xd8ef); +reg_write( DDR_REG_BASE +0x52889*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x5288a*4 +0x02000000,0x6c0); +reg_write( DDR_REG_BASE +0x5288b*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x5288c*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5288d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5288e*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x5288f*4 +0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x52890*4 +0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x52891*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52892*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52893*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52894*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52895*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52896*4 +0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x52897*4 +0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x52898*4 +0x02000000,0x6c7); +reg_write( DDR_REG_BASE +0x52899*4 +0x02000000,0x9d7); +reg_write( DDR_REG_BASE +0x5289a*4 +0x02000000,0x8005); +reg_write( DDR_REG_BASE +0x5289b*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5289c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5289d*4 +0x02000000,0x2100); +reg_write( DDR_REG_BASE +0x5289e*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5289f*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x528a0*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x528a1*4 +0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x528a2*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x528a3*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x528a4*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x528a5*4 +0x02000000,0xfe64); +reg_write( DDR_REG_BASE +0x528a6*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x528a7*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x528a8*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x528a9*4 +0x02000000,0xf064); +reg_write( DDR_REG_BASE +0x528aa*4 +0x02000000,0x711c); +reg_write( DDR_REG_BASE +0x528ab*4 +0x02000000,0x86e); +reg_write( DDR_REG_BASE +0x528ac*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x528ad*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x528ae*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x528af*4 +0x02000000,0x866); +reg_write( DDR_REG_BASE +0x528b0*4 +0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x528b1*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x528b2*4 +0x02000000,0xcba); +reg_write( DDR_REG_BASE +0x528b3*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x528b4*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x528b5*4 +0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x528b6*4 +0x02000000,0xe32); +reg_write( DDR_REG_BASE +0x528b7*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x528b8*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x528b9*4 +0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x528ba*4 +0x02000000,0xdf7f); +reg_write( DDR_REG_BASE +0x528bb*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x528bc*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x528bd*4 +0x02000000,0xe024); +reg_write( DDR_REG_BASE +0x528be*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x528bf*4 +0x02000000,0xb6e0); +reg_write( DDR_REG_BASE +0x528c0*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x528c1*4 +0x02000000,0xb606); +reg_write( DDR_REG_BASE +0x528c2*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x528c3*4 +0x02000000,0x3c4); +reg_write( DDR_REG_BASE +0x528c4*4 +0x02000000,0x1efe); +reg_write( DDR_REG_BASE +0x528c5*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x528c6*4 +0x02000000,0xd818); +reg_write( DDR_REG_BASE +0x528c7*4 +0x02000000,0x90a); +reg_write( DDR_REG_BASE +0x528c8*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x528c9*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x528ca*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x528cb*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x528cc*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x528cd*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x528ce*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x528cf*4 +0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x528d0*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x528d1*4 +0x02000000,0xc7e); +reg_write( DDR_REG_BASE +0x528d2*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x528d3*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x528d4*4 +0x02000000,0xd807); +reg_write( DDR_REG_BASE +0x528d5*4 +0x02000000,0x8ee); +reg_write( DDR_REG_BASE +0x528d6*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x528d7*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x528d8*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x528d9*4 +0x02000000,0xb6e0); +reg_write( DDR_REG_BASE +0x528da*4 +0x02000000,0xb606); +reg_write( DDR_REG_BASE +0x528db*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x528dc*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x528dd*4 +0x02000000,0xc66); +reg_write( DDR_REG_BASE +0x528de*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x528df*4 +0x02000000,0x1efe); +reg_write( DDR_REG_BASE +0x528e0*4 +0x02000000,0x93c5); +reg_write( DDR_REG_BASE +0x528e1*4 +0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x528e2*4 +0x02000000,0x8d2); +reg_write( DDR_REG_BASE +0x528e3*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x528e4*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x528e5*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x528e6*4 +0x02000000,0xc52); +reg_write( DDR_REG_BASE +0x528e7*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x528e8*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x528e9*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x528ea*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x528eb*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x528ec*4 +0x02000000,0x1fc5); +reg_write( DDR_REG_BASE +0x528ed*4 +0x02000000,0x1e0c); +reg_write( DDR_REG_BASE +0x528ee*4 +0x02000000,0x1fc5); +reg_write( DDR_REG_BASE +0x528ef*4 +0x02000000,0x8ba); +reg_write( DDR_REG_BASE +0x528f0*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x528f1*4 +0x02000000,0x1efe); +reg_write( DDR_REG_BASE +0x528f2*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x528f3*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x528f4*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x528f5*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x528f6*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x528f7*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x528f8*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x528f9*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x528fa*4 +0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x528fb*4 +0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x528fc*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x528fd*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x528fe*4 +0x02000000,0x64); +reg_write( DDR_REG_BASE +0x528ff*4 +0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x52900*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x52901*4 +0x02000000,0xf05f); +reg_write( DDR_REG_BASE +0x52902*4 +0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x52903*4 +0x02000000,0xf9f); +reg_write( DDR_REG_BASE +0x52904*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52905*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52906*4 +0x02000000,0xc602); +reg_write( DDR_REG_BASE +0x52907*4 +0x02000000,0xc400); +reg_write( DDR_REG_BASE +0x52908*4 +0x02000000,0xf053); +reg_write( DDR_REG_BASE +0x52909*4 +0x02000000,0x225f); +reg_write( DDR_REG_BASE +0x5290a*4 +0x02000000,0x480); +reg_write( DDR_REG_BASE +0x5290b*4 +0x02000000,0x74d5); +reg_write( DDR_REG_BASE +0x5290c*4 +0x02000000,0x24c0); +reg_write( DDR_REG_BASE +0x5290d*4 +0x02000000,0x1061); +reg_write( DDR_REG_BASE +0x5290e*4 +0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x5290f*4 +0x02000000,0x1061); +reg_write( DDR_REG_BASE +0x52910*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52911*4 +0x02000000,0xc301); +reg_write( DDR_REG_BASE +0x52912*4 +0x02000000,0xc088); +reg_write( DDR_REG_BASE +0x52913*4 +0x02000000,0x631b); +reg_write( DDR_REG_BASE +0x52914*4 +0x02000000,0x7bd4); +reg_write( DDR_REG_BASE +0x52915*4 +0x02000000,0x9300); +reg_write( DDR_REG_BASE +0x52916*4 +0x02000000,0xe0c0); +reg_write( DDR_REG_BASE +0x52917*4 +0x02000000,0x88); +reg_write( DDR_REG_BASE +0x52918*4 +0x02000000,0x25); +reg_write( DDR_REG_BASE +0x52919*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x5291a*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x5291b*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5291c*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5291d*4 +0x02000000,0x7c0); +reg_write( DDR_REG_BASE +0x5291e*4 +0x02000000,0x7f1b); +reg_write( DDR_REG_BASE +0x5291f*4 +0x02000000,0x2705); +reg_write( DDR_REG_BASE +0x52920*4 +0x02000000,0x178f); +reg_write( DDR_REG_BASE +0x52921*4 +0x02000000,0x9700); +reg_write( DDR_REG_BASE +0x52922*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52923*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52924*4 +0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x52925*4 +0x02000000,0x1021); +reg_write( DDR_REG_BASE +0x52926*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x52927*4 +0x02000000,0x21); +reg_write( DDR_REG_BASE +0x52928*4 +0x02000000,0xb53); +reg_write( DDR_REG_BASE +0x52929*4 +0x02000000,0x1030); +reg_write( DDR_REG_BASE +0x5292a*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5292b*4 +0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x5292c*4 +0x02000000,0x80d); +reg_write( DDR_REG_BASE +0x5292d*4 +0x02000000,0xd0); +reg_write( DDR_REG_BASE +0x5292e*4 +0x02000000,0x84b); +reg_write( DDR_REG_BASE +0x5292f*4 +0x02000000,0x210); +reg_write( DDR_REG_BASE +0x52930*4 +0x02000000,0x855); +reg_write( DDR_REG_BASE +0x52931*4 +0x02000000,0x1d1); +reg_write( DDR_REG_BASE +0x52932*4 +0x02000000,0x788f); +reg_write( DDR_REG_BASE +0x52933*4 +0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x52934*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52935*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52936*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x52937*4 +0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x52938*4 +0x02000000,0xc301); +reg_write( DDR_REG_BASE +0x52939*4 +0x02000000,0x677f); +reg_write( DDR_REG_BASE +0x5293a*4 +0x02000000,0x7f14); +reg_write( DDR_REG_BASE +0x5293b*4 +0x02000000,0x6861); +reg_write( DDR_REG_BASE +0x5293c*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x5293d*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5293e*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5293f*4 +0x02000000,0x7c0); +reg_write( DDR_REG_BASE +0x52940*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52941*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52942*4 +0x02000000,0x780); +reg_write( DDR_REG_BASE +0x52943*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x52944*4 +0x02000000,0xb700); +reg_write( DDR_REG_BASE +0x52945*4 +0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x52946*4 +0x02000000,0xee5); +reg_write( DDR_REG_BASE +0x52947*4 +0x02000000,0x9025); +reg_write( DDR_REG_BASE +0x52948*4 +0x02000000,0xc788); +reg_write( DDR_REG_BASE +0x52949*4 +0x02000000,0xe25); +reg_write( DDR_REG_BASE +0x5294a*4 +0x02000000,0x11d1); +reg_write( DDR_REG_BASE +0x5294b*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5294c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5294d*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x5294e*4 +0x02000000,0x7854); +reg_write( DDR_REG_BASE +0x5294f*4 +0x02000000,0xa8af); +reg_write( DDR_REG_BASE +0x52950*4 +0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x52951*4 +0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x52952*4 +0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x52953*4 +0x02000000,0x9700); +reg_write( DDR_REG_BASE +0x52954*4 +0x02000000,0xb300); +reg_write( DDR_REG_BASE +0x52955*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52956*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52957*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x52958*4 +0x02000000,0x7854); +reg_write( DDR_REG_BASE +0x52959*4 +0x02000000,0xa8b0); +reg_write( DDR_REG_BASE +0x5295a*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x5295b*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5295c*4 +0x02000000,0xe5b); +reg_write( DDR_REG_BASE +0x5295d*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5295e*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x5295f*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x52960*4 +0x02000000,0x7a2f); +reg_write( DDR_REG_BASE +0x52961*4 +0x02000000,0x845); +reg_write( DDR_REG_BASE +0x52962*4 +0x02000000,0x80a5); +reg_write( DDR_REG_BASE +0x52963*4 +0x02000000,0x716d); +reg_write( DDR_REG_BASE +0x52964*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52965*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x52966*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52967*4 +0x02000000,0xf315); +reg_write( DDR_REG_BASE +0x52968*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52969*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5296a*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5296b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5296c*4 +0x02000000,0xb8c3); +reg_write( DDR_REG_BASE +0x5296d*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5296e*4 +0x02000000,0xf02f); +reg_write( DDR_REG_BASE +0x5296f*4 +0x02000000,0xc502); +reg_write( DDR_REG_BASE +0x52970*4 +0x02000000,0xf028); +reg_write( DDR_REG_BASE +0x52971*4 +0x02000000,0x275f); +reg_write( DDR_REG_BASE +0x52972*4 +0x02000000,0x1480); +reg_write( DDR_REG_BASE +0x52973*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52974*4 +0x02000000,0x47); +reg_write( DDR_REG_BASE +0x52975*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x52976*4 +0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x52977*4 +0x02000000,0x661e); +reg_write( DDR_REG_BASE +0x52978*4 +0x02000000,0x26f4); +reg_write( DDR_REG_BASE +0x52979*4 +0x02000000,0x1340); +reg_write( DDR_REG_BASE +0x5297a*4 +0x02000000,0x43a1); +reg_write( DDR_REG_BASE +0x5297b*4 +0x02000000,0xe5e); +reg_write( DDR_REG_BASE +0x5297c*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x5297d*4 +0x02000000,0x20bc); +reg_write( DDR_REG_BASE +0x5297e*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5297f*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52980*4 +0x02000000,0x271a); +reg_write( DDR_REG_BASE +0x52981*4 +0x02000000,0x1f81); +reg_write( DDR_REG_BASE +0x52982*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52983*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52984*4 +0x02000000,0x26f4); +reg_write( DDR_REG_BASE +0x52985*4 +0x02000000,0x1342); +reg_write( DDR_REG_BASE +0x52986*4 +0x02000000,0x2054); +reg_write( DDR_REG_BASE +0x52987*4 +0x02000000,0xd00); +reg_write( DDR_REG_BASE +0x52988*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x52989*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x5298a*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x5298b*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5298c*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x5298d*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x5298e*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5298f*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52990*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52991*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52992*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52993*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x52994*4 +0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x52995*4 +0x02000000,0x2049); +reg_write( DDR_REG_BASE +0x52996*4 +0x02000000,0xfc0); +reg_write( DDR_REG_BASE +0x52997*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x52998*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52999*4 +0x02000000,0xdb3); +reg_write( DDR_REG_BASE +0x5299a*4 +0x02000000,0x9024); +reg_write( DDR_REG_BASE +0x5299b*4 +0x02000000,0xc688); +reg_write( DDR_REG_BASE +0x5299c*4 +0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x5299d*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5299e*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5299f*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x529a0*4 +0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x529a1*4 +0x02000000,0x272f); +reg_write( DDR_REG_BASE +0x529a2*4 +0x02000000,0x16c7); +reg_write( DDR_REG_BASE +0x529a3*4 +0x02000000,0x89b); +reg_write( DDR_REG_BASE +0x529a4*4 +0x02000000,0x83c5); +reg_write( DDR_REG_BASE +0x529a5*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x529a6*4 +0x02000000,0x889); +reg_write( DDR_REG_BASE +0x529a7*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x529a8*4 +0x02000000,0x9da); +reg_write( DDR_REG_BASE +0x529a9*4 +0x02000000,0xfe4f); +reg_write( DDR_REG_BASE +0x529aa*4 +0x02000000,0x4308); +reg_write( DDR_REG_BASE +0x529ab*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x529ac*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x529ad*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x529ae*4 +0x02000000,0x8881); +reg_write( DDR_REG_BASE +0x529af*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x529b0*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x529b1*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x529b2*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x529b3*4 +0x02000000,0xf034); +reg_write( DDR_REG_BASE +0x529b4*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x529b5*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x529b6*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x529b7*4 +0x02000000,0x79b4); +reg_write( DDR_REG_BASE +0x529b8*4 +0x02000000,0x896f); +reg_write( DDR_REG_BASE +0x529b9*4 +0x02000000,0x8950); +reg_write( DDR_REG_BASE +0x529ba*4 +0x02000000,0x4a76); +reg_write( DDR_REG_BASE +0x529bb*4 +0x02000000,0x4b51); +reg_write( DDR_REG_BASE +0x529bc*4 +0x02000000,0x7270); +reg_write( DDR_REG_BASE +0x529bd*4 +0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x529be*4 +0x02000000,0x38d); +reg_write( DDR_REG_BASE +0x529bf*4 +0x02000000,0x7e2f); +reg_write( DDR_REG_BASE +0x529c0*4 +0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x529c1*4 +0x02000000,0x12ce); +reg_write( DDR_REG_BASE +0x529c2*4 +0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x529c3*4 +0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x529c4*4 +0x02000000,0x122d); +reg_write( DDR_REG_BASE +0x529c5*4 +0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x529c6*4 +0x02000000,0x12d); +reg_write( DDR_REG_BASE +0x529c7*4 +0x02000000,0x2e44); +reg_write( DDR_REG_BASE +0x529c8*4 +0x02000000,0x180e); +reg_write( DDR_REG_BASE +0x529c9*4 +0x02000000,0xf019); +reg_write( DDR_REG_BASE +0x529ca*4 +0x02000000,0xc203); +reg_write( DDR_REG_BASE +0x529cb*4 +0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x529cc*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x529cd*4 +0x02000000,0x2254); +reg_write( DDR_REG_BASE +0x529ce*4 +0x02000000,0xd03); +reg_write( DDR_REG_BASE +0x529cf*4 +0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x529d0*4 +0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x529d1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x529d2*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x529d3*4 +0x02000000,0x7a65); +reg_write( DDR_REG_BASE +0x529d4*4 +0x02000000,0x7945); +reg_write( DDR_REG_BASE +0x529d5*4 +0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x529d6*4 +0x02000000,0xb991); +reg_write( DDR_REG_BASE +0x529d7*4 +0x02000000,0xb99c); +reg_write( DDR_REG_BASE +0x529d8*4 +0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x529d9*4 +0x02000000,0x9160); +reg_write( DDR_REG_BASE +0x529da*4 +0x02000000,0x7ad0); +reg_write( DDR_REG_BASE +0x529db*4 +0x02000000,0x627a); +reg_write( DDR_REG_BASE +0x529dc*4 +0x02000000,0x2249); +reg_write( DDR_REG_BASE +0x529dd*4 +0x02000000,0xfc2); +reg_write( DDR_REG_BASE +0x529de*4 +0x02000000,0xb140); +reg_write( DDR_REG_BASE +0x529df*4 +0x02000000,0x210a); +reg_write( DDR_REG_BASE +0x529e0*4 +0x02000000,0x780); +reg_write( DDR_REG_BASE +0x529e1*4 +0x02000000,0x9d5); +reg_write( DDR_REG_BASE +0x529e2*4 +0x02000000,0x83e4); +reg_write( DDR_REG_BASE +0x529e3*4 +0x02000000,0x2140); +reg_write( DDR_REG_BASE +0x529e4*4 +0x02000000,0x5e); +reg_write( DDR_REG_BASE +0x529e5*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x529e6*4 +0x02000000,0x7d0f); +reg_write( DDR_REG_BASE +0x529e7*4 +0x02000000,0xc9d); +reg_write( DDR_REG_BASE +0x529e8*4 +0x02000000,0x9365); +reg_write( DDR_REG_BASE +0x529e9*4 +0x02000000,0xdf09); +reg_write( DDR_REG_BASE +0x529ea*4 +0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x529eb*4 +0x02000000,0x3503); +reg_write( DDR_REG_BASE +0x529ec*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x529ed*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x529ee*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x529ef*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x529f0*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x529f1*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x529f2*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x529f3*4 +0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x529f4*4 +0x02000000,0x3d0a); +reg_write( DDR_REG_BASE +0x529f5*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x529f6*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x529f7*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x529f8*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x529f9*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x529fa*4 +0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x529fb*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x529fc*4 +0x02000000,0x4a); +reg_write( DDR_REG_BASE +0x529fd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x529fe*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x529ff*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52a00*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52a01*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a02*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52a03*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52a04*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52a05*4 +0x02000000,0x86); +reg_write( DDR_REG_BASE +0x52a06*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x52a07*4 +0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x52a08*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52a09*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52a0a*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52a0b*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52a0c*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52a0d*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52a0e*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52a0f*4 +0x02000000,0xd36); +reg_write( DDR_REG_BASE +0x52a10*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52a11*4 +0x02000000,0x2052); +reg_write( DDR_REG_BASE +0x52a12*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a13*4 +0x02000000,0x8ae); +reg_write( DDR_REG_BASE +0x52a14*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52a15*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52a16*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x52a17*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52a18*4 +0x02000000,0xff68); +reg_write( DDR_REG_BASE +0x52a19*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52a1a*4 +0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x52a1b*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52a1c*4 +0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x52a1d*4 +0x02000000,0x1a00); +reg_write( DDR_REG_BASE +0x52a1e*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x52a1f*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x52a20*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52a21*4 +0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x52a22*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52a23*4 +0x02000000,0x7ca); +reg_write( DDR_REG_BASE +0x52a24*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x52a25*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x52a26*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x52a27*4 +0x02000000,0xed06); +reg_write( DDR_REG_BASE +0x52a28*4 +0x02000000,0xbd61); +reg_write( DDR_REG_BASE +0x52a29*4 +0x02000000,0xd01); +reg_write( DDR_REG_BASE +0x52a2a*4 +0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x52a2b*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52a2c*4 +0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x52a2d*4 +0x02000000,0x103); +reg_write( DDR_REG_BASE +0x52a2e*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52a2f*4 +0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x52a30*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52a31*4 +0x02000000,0x1ea); +reg_write( DDR_REG_BASE +0x52a32*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52a33*4 +0x02000000,0x12c3); +reg_write( DDR_REG_BASE +0x52a34*4 +0x02000000,0x700); +reg_write( DDR_REG_BASE +0x52a35*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52a36*4 +0x02000000,0xca0a); +reg_write( DDR_REG_BASE +0x52a37*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x52a38*4 +0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x52a39*4 +0x02000000,0xf40c); +reg_write( DDR_REG_BASE +0x52a3a*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52a3b*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x52a3c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52a3d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a3e*4 +0x02000000,0xb8e5); +reg_write( DDR_REG_BASE +0x52a3f*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52a40*4 +0x02000000,0xf204); +reg_write( DDR_REG_BASE +0x52a41*4 +0x02000000,0x8f00); +reg_write( DDR_REG_BASE +0x52a42*4 +0x02000000,0x1a0a); +reg_write( DDR_REG_BASE +0x52a43*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x52a44*4 +0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x52a45*4 +0x02000000,0x230f); +reg_write( DDR_REG_BASE +0x52a46*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x52a47*4 +0x02000000,0xc149); +reg_write( DDR_REG_BASE +0x52a48*4 +0x02000000,0x2379); +reg_write( DDR_REG_BASE +0x52a49*4 +0x02000000,0x3001); +reg_write( DDR_REG_BASE +0x52a4a*4 +0x02000000,0x7224); +reg_write( DDR_REG_BASE +0x52a4b*4 +0x02000000,0xc14a); +reg_write( DDR_REG_BASE +0x52a4c*4 +0x02000000,0x8f20); +reg_write( DDR_REG_BASE +0x52a4d*4 +0x02000000,0x33b); +reg_write( DDR_REG_BASE +0x52a4e*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52a4f*4 +0x02000000,0x2139); +reg_write( DDR_REG_BASE +0x52a50*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a51*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52a52*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52a53*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52a54*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52a55*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a56*4 +0x02000000,0xc0ff); +reg_write( DDR_REG_BASE +0x52a57*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52a58*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52a59*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a5a*4 +0x02000000,0x3f00); +reg_write( DDR_REG_BASE +0x52a5b*4 +0x02000000,0x2080); +reg_write( DDR_REG_BASE +0x52a5c*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52a5d*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52a5e*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52a5f*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52a60*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52a61*4 +0x02000000,0x1ea); +reg_write( DDR_REG_BASE +0x52a62*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52a63*4 +0x02000000,0x7384); +reg_write( DDR_REG_BASE +0x52a64*4 +0x02000000,0x900f); +reg_write( DDR_REG_BASE +0x52a65*4 +0x02000000,0xe022); +reg_write( DDR_REG_BASE +0x52a66*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52a67*4 +0x02000000,0x762c); +reg_write( DDR_REG_BASE +0x52a68*4 +0x02000000,0xb8a5); +reg_write( DDR_REG_BASE +0x52a69*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52a6a*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52a6b*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52a6c*4 +0x02000000,0xe0ee); +reg_write( DDR_REG_BASE +0x52a6d*4 +0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x52a6e*4 +0x02000000,0xf7e); +reg_write( DDR_REG_BASE +0x52a6f*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x52a70*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52a71*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x52a72*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52a73*4 +0x02000000,0xed08); +reg_write( DDR_REG_BASE +0x52a74*4 +0x02000000,0xb82); +reg_write( DDR_REG_BASE +0x52a75*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x52a76*4 +0x02000000,0x2578); +reg_write( DDR_REG_BASE +0x52a77*4 +0x02000000,0x1081); +reg_write( DDR_REG_BASE +0x52a78*4 +0x02000000,0x2c9); +reg_write( DDR_REG_BASE +0x52a79*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a7a*4 +0x02000000,0x976); +reg_write( DDR_REG_BASE +0x52a7b*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52a7c*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52a7d*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52a7e*4 +0x02000000,0x709b); +reg_write( DDR_REG_BASE +0x52a7f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52a80*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52a81*4 +0x02000000,0x8ee); +reg_write( DDR_REG_BASE +0x52a82*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52a83*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x52a84*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x52a85*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52a86*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52a87*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a88*4 +0x02000000,0x258); +reg_write( DDR_REG_BASE +0x52a89*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52a8a*4 +0x02000000,0xec6); +reg_write( DDR_REG_BASE +0x52a8b*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x52a8c*4 +0x02000000,0xda5a); +reg_write( DDR_REG_BASE +0x52a8d*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52a8e*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52a8f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a90*4 +0x02000000,0x1a4); +reg_write( DDR_REG_BASE +0x52a91*4 +0x02000000,0xeba); +reg_write( DDR_REG_BASE +0x52a92*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x52a93*4 +0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x52a94*4 +0x02000000,0xdda); +reg_write( DDR_REG_BASE +0x52a95*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x52a96*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x52a97*4 +0x02000000,0xb04); +reg_write( DDR_REG_BASE +0x52a98*4 +0x02000000,0xd72); +reg_write( DDR_REG_BASE +0x52a99*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x52a9a*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52a9b*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52a9c*4 +0x02000000,0x7384); +reg_write( DDR_REG_BASE +0x52a9d*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52a9e*4 +0x02000000,0xfec4); +reg_write( DDR_REG_BASE +0x52a9f*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52aa0*4 +0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x52aa1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52aa2*4 +0x02000000,0xe008); +reg_write( DDR_REG_BASE +0x52aa3*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52aa4*4 +0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x52aa5*4 +0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x52aa6*4 +0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x52aa7*4 +0x02000000,0x17c0); +reg_write( DDR_REG_BASE +0x52aa8*4 +0x02000000,0x6e21); +reg_write( DDR_REG_BASE +0x52aa9*4 +0x02000000,0x269a); +reg_write( DDR_REG_BASE +0x52aaa*4 +0x02000000,0x1008); +reg_write( DDR_REG_BASE +0x52aab*4 +0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x52aac*4 +0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x52aad*4 +0x02000000,0x801); +reg_write( DDR_REG_BASE +0x52aae*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x52aaf*4 +0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x52ab0*4 +0x02000000,0x2605); +reg_write( DDR_REG_BASE +0x52ab1*4 +0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x52ab2*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52ab3*4 +0x02000000,0xe0c4); +reg_write( DDR_REG_BASE +0x52ab4*4 +0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x52ab5*4 +0x02000000,0x4628); +reg_write( DDR_REG_BASE +0x52ab6*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52ab7*4 +0x02000000,0xedf); +reg_write( DDR_REG_BASE +0x52ab8*4 +0x02000000,0x9024); +reg_write( DDR_REG_BASE +0x52ab9*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52aba*4 +0x02000000,0xd880); +reg_write( DDR_REG_BASE +0x52abb*4 +0x02000000,0xb88e); +reg_write( DDR_REG_BASE +0x52abc*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52abd*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52abe*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52abf*4 +0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x52ac0*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x52ac1*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52ac2*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52ac3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52ac4*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52ac5*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52ac6*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52ac7*4 +0x02000000,0xfe86); +reg_write( DDR_REG_BASE +0x52ac8*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52ac9*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52aca*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52acb*4 +0x02000000,0x86); +reg_write( DDR_REG_BASE +0x52acc*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x52acd*4 +0x02000000,0xb8a0); +reg_write( DDR_REG_BASE +0x52ace*4 +0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x52acf*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52ad0*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x52ad1*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x52ad2*4 +0x02000000,0x8f03); +reg_write( DDR_REG_BASE +0x52ad3*4 +0x02000000,0xda3f); +reg_write( DDR_REG_BASE +0x52ad4*4 +0x02000000,0xf643); +reg_write( DDR_REG_BASE +0x52ad5*4 +0x02000000,0x2844); +reg_write( DDR_REG_BASE +0x52ad6*4 +0x02000000,0x102); +reg_write( DDR_REG_BASE +0x52ad7*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x52ad8*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52ad9*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52ada*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52adb*4 +0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x52adc*4 +0x02000000,0x8f24); +reg_write( DDR_REG_BASE +0x52add*4 +0x02000000,0x43c1); +reg_write( DDR_REG_BASE +0x52ade*4 +0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x52adf*4 +0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x52ae0*4 +0x02000000,0x7864); +reg_write( DDR_REG_BASE +0x52ae1*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x52ae2*4 +0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x52ae3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52ae4*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52ae5*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x52ae6*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x52ae7*4 +0x02000000,0x2054); +reg_write( DDR_REG_BASE +0x52ae8*4 +0x02000000,0xd00); +reg_write( DDR_REG_BASE +0x52ae9*4 +0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x52aea*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52aeb*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52aec*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52aed*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52aee*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52aef*4 +0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x52af0*4 +0x02000000,0x786f); +reg_write( DDR_REG_BASE +0x52af1*4 +0x02000000,0x9e1); +reg_write( DDR_REG_BASE +0x52af2*4 +0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x52af3*4 +0x02000000,0xd8ef); +reg_write( DDR_REG_BASE +0x52af4*4 +0x02000000,0x228a); +reg_write( DDR_REG_BASE +0x52af5*4 +0x02000000,0x7c4); +reg_write( DDR_REG_BASE +0x52af6*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52af7*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52af8*4 +0x02000000,0xe024); +reg_write( DDR_REG_BASE +0x52af9*4 +0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x52afa*4 +0x02000000,0x228a); +reg_write( DDR_REG_BASE +0x52afb*4 +0x02000000,0x3c4); +reg_write( DDR_REG_BASE +0x52afc*4 +0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x52afd*4 +0x02000000,0x180c); +reg_write( DDR_REG_BASE +0x52afe*4 +0x02000000,0x45); +reg_write( DDR_REG_BASE +0x52aff*4 +0x02000000,0x18fe); +reg_write( DDR_REG_BASE +0x52b00*4 +0x02000000,0x8084); +reg_write( DDR_REG_BASE +0x52b01*4 +0x02000000,0xf09f); +reg_write( DDR_REG_BASE +0x52b02*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x52b03*4 +0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x52b04*4 +0x02000000,0x8c2); +reg_write( DDR_REG_BASE +0x52b05*4 +0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x52b06*4 +0x02000000,0x7a05); +reg_write( DDR_REG_BASE +0x52b07*4 +0x02000000,0xd8ef); +reg_write( DDR_REG_BASE +0x52b08*4 +0x02000000,0x78c4); +reg_write( DDR_REG_BASE +0x52b09*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x52b0a*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52b0b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52b0c*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52b0d*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x52b0e*4 +0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x52b0f*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52b10*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52b11*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52b12*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52b13*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52b14*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x52b15*4 +0x02000000,0x6c4); +reg_write( DDR_REG_BASE +0x52b16*4 +0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x52b17*4 +0x02000000,0x9d9); +reg_write( DDR_REG_BASE +0x52b18*4 +0x02000000,0x8005); +reg_write( DDR_REG_BASE +0x52b19*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52b1a*4 +0x02000000,0xfea); +reg_write( DDR_REG_BASE +0x52b1b*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52b1c*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52b1d*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x52b1e*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52b1f*4 +0x02000000,0xfe64); +reg_write( DDR_REG_BASE +0x52b20*4 +0x02000000,0xb82); +reg_write( DDR_REG_BASE +0x52b21*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x52b22*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x52b23*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x52b24*4 +0x02000000,0xb7a); +reg_write( DDR_REG_BASE +0x52b25*4 +0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x52b26*4 +0x02000000,0xa3a); +reg_write( DDR_REG_BASE +0x52b27*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x52b28*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52b29*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52b2a*4 +0x02000000,0x94a); +reg_write( DDR_REG_BASE +0x52b2b*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52b2c*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x52b2d*4 +0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x52b2e*4 +0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x52b2f*4 +0x02000000,0xc3a); +reg_write( DDR_REG_BASE +0x52b30*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52b31*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52b32*4 +0x02000000,0xc08f); +reg_write( DDR_REG_BASE +0x52b33*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52b34*4 +0x02000000,0xada); +reg_write( DDR_REG_BASE +0x52b35*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52b36*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52b37*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52b38*4 +0x02000000,0xfae); +reg_write( DDR_REG_BASE +0x52b39*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52b3a*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52b3b*4 +0x02000000,0xd87f); +reg_write( DDR_REG_BASE +0x52b3c*4 +0x02000000,0xb4a); +reg_write( DDR_REG_BASE +0x52b3d*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x52b3e*4 +0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x52b3f*4 +0x02000000,0xb46); +reg_write( DDR_REG_BASE +0x52b40*4 +0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x52b41*4 +0x02000000,0xa06); +reg_write( DDR_REG_BASE +0x52b42*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x52b43*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52b44*4 +0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x52b45*4 +0x02000000,0x916); +reg_write( DDR_REG_BASE +0x52b46*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52b47*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x52b48*4 +0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x52b49*4 +0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x52b4a*4 +0x02000000,0xc02); +reg_write( DDR_REG_BASE +0x52b4b*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52b4c*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52b4d*4 +0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x52b4e*4 +0x02000000,0x3f00); +reg_write( DDR_REG_BASE +0x52b4f*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52b50*4 +0x02000000,0xaa2); +reg_write( DDR_REG_BASE +0x52b51*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52b52*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52b53*4 +0x02000000,0x8f03); +reg_write( DDR_REG_BASE +0x52b54*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52b55*4 +0x02000000,0x243); +reg_write( DDR_REG_BASE +0x52b56*4 +0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x52b57*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x52b58*4 +0x02000000,0xf03f); +reg_write( DDR_REG_BASE +0x52b59*4 +0x02000000,0xc08c); +reg_write( DDR_REG_BASE +0x52b5a*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52b5b*4 +0x02000000,0xd26); +reg_write( DDR_REG_BASE +0x52b5c*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x52b5d*4 +0x02000000,0xda09); +reg_write( DDR_REG_BASE +0x52b5e*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52b5f*4 +0x02000000,0xf030); +reg_write( DDR_REG_BASE +0x52b60*4 +0x02000000,0x787b); +reg_write( DDR_REG_BASE +0x52b61*4 +0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x52b62*4 +0x02000000,0xf87); +reg_write( DDR_REG_BASE +0x52b63*4 +0x02000000,0xc18f); +reg_write( DDR_REG_BASE +0x52b64*4 +0x02000000,0x2135); +reg_write( DDR_REG_BASE +0x52b65*4 +0x02000000,0xb); +reg_write( DDR_REG_BASE +0x52b66*4 +0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x52b67*4 +0x02000000,0x3f01); +reg_write( DDR_REG_BASE +0x52b68*4 +0x02000000,0x2135); +reg_write( DDR_REG_BASE +0x52b69*4 +0x02000000,0xe); +reg_write( DDR_REG_BASE +0x52b6a*4 +0x02000000,0x2602); +reg_write( DDR_REG_BASE +0x52b6b*4 +0x02000000,0x12c0); +reg_write( DDR_REG_BASE +0x52b6c*4 +0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x52b6d*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x52b6e*4 +0x02000000,0xc08c); +reg_write( DDR_REG_BASE +0x52b6f*4 +0x02000000,0x60b8); +reg_write( DDR_REG_BASE +0x52b70*4 +0x02000000,0xa840); +reg_write( DDR_REG_BASE +0x52b71*4 +0x02000000,0x7c4f); +reg_write( DDR_REG_BASE +0x52b72*4 +0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x52b73*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52b74*4 +0x02000000,0x241); +reg_write( DDR_REG_BASE +0x52b75*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52b76*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52b77*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52b78*4 +0x02000000,0x258); +reg_write( DDR_REG_BASE +0x52b79*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x52b7a*4 +0x02000000,0x60b8); +reg_write( DDR_REG_BASE +0x52b7b*4 +0x02000000,0x8820); +reg_write( DDR_REG_BASE +0x52b7c*4 +0x02000000,0x921); +reg_write( DDR_REG_BASE +0x52b7d*4 +0x02000000,0x305); +reg_write( DDR_REG_BASE +0x52b7e*4 +0x02000000,0xa840); +reg_write( DDR_REG_BASE +0x52b7f*4 +0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x52b80*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52b81*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x52b82*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52b83*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52b84*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52b85*4 +0x02000000,0x1a4); +reg_write( DDR_REG_BASE +0x52b86*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x52b87*4 +0x02000000,0x2300); +reg_write( DDR_REG_BASE +0x52b88*4 +0x02000000,0x1381); +reg_write( DDR_REG_BASE +0x52b89*4 +0x02000000,0x78b4); +reg_write( DDR_REG_BASE +0x52b8a*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x52b8b*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x52b8c*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x52b8d*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x52b8e*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52b8f*4 +0x02000000,0xda5); +reg_write( DDR_REG_BASE +0x52b90*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52b91*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52b92*4 +0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x52b93*4 +0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x52b94*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52b95*4 +0x02000000,0x23c0); +reg_write( DDR_REG_BASE +0x52b96*4 +0x02000000,0x61); +reg_write( DDR_REG_BASE +0x52b97*4 +0x02000000,0x8f24); +reg_write( DDR_REG_BASE +0x52b98*4 +0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x52b99*4 +0x02000000,0x787); +reg_write( DDR_REG_BASE +0x52b9a*4 +0x02000000,0x97f); +reg_write( DDR_REG_BASE +0x52b9b*4 +0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x52b9c*4 +0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x52b9d*4 +0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x52b9e*4 +0x02000000,0x7467); +reg_write( DDR_REG_BASE +0x52b9f*4 +0x02000000,0x234c); +reg_write( DDR_REG_BASE +0x52ba0*4 +0x02000000,0xb780); +reg_write( DDR_REG_BASE +0x52ba1*4 +0x02000000,0x6ec); +reg_write( DDR_REG_BASE +0x52ba2*4 +0x02000000,0xffce); +reg_write( DDR_REG_BASE +0x52ba3*4 +0x02000000,0xf036); +reg_write( DDR_REG_BASE +0x52ba4*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52ba5*4 +0x02000000,0xf02e); +reg_write( DDR_REG_BASE +0x52ba6*4 +0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x52ba7*4 +0x02000000,0x3241); +reg_write( DDR_REG_BASE +0x52ba8*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52ba9*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52baa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52bab*4 +0x02000000,0x258); +reg_write( DDR_REG_BASE +0x52bac*4 +0x02000000,0x43a1); +reg_write( DDR_REG_BASE +0x52bad*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x52bae*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52baf*4 +0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x52bb0*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x52bb1*4 +0x02000000,0x9f2); +reg_write( DDR_REG_BASE +0x52bb2*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52bb3*4 +0x02000000,0x60a8); +reg_write( DDR_REG_BASE +0x52bb4*4 +0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x52bb5*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x52bb6*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52bb7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52bb8*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52bb9*4 +0x02000000,0x229a); +reg_write( DDR_REG_BASE +0x52bba*4 +0x02000000,0x8); +reg_write( DDR_REG_BASE +0x52bbb*4 +0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x52bbc*4 +0x02000000,0x3481); +reg_write( DDR_REG_BASE +0x52bbd*4 +0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x52bbe*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52bbf*4 +0x02000000,0x80); +reg_write( DDR_REG_BASE +0x52bc0*4 +0x02000000,0x7a05); +reg_write( DDR_REG_BASE +0x52bc1*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52bc2*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52bc3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52bc4*4 +0x02000000,0x1a4); +reg_write( DDR_REG_BASE +0x52bc5*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x52bc6*4 +0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x52bc7*4 +0x02000000,0x340); +reg_write( DDR_REG_BASE +0x52bc8*4 +0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x52bc9*4 +0x02000000,0xcc); +reg_write( DDR_REG_BASE +0x52bca*4 +0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x52bcb*4 +0x02000000,0x2342); +reg_write( DDR_REG_BASE +0x52bcc*4 +0x02000000,0x800); +reg_write( DDR_REG_BASE +0x52bcd*4 +0x02000000,0x7a05); +reg_write( DDR_REG_BASE +0x52bce*4 +0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x52bcf*4 +0x02000000,0x340); +reg_write( DDR_REG_BASE +0x52bd0*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x52bd1*4 +0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x52bd2*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52bd3*4 +0x02000000,0xda9); +reg_write( DDR_REG_BASE +0x52bd4*4 +0x02000000,0x9024); +reg_write( DDR_REG_BASE +0x52bd5*4 +0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x52bd6*4 +0x02000000,0x8f24); +reg_write( DDR_REG_BASE +0x52bd7*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x52bd8*4 +0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x52bd9*4 +0x02000000,0x999); +reg_write( DDR_REG_BASE +0x52bda*4 +0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x52bdb*4 +0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x52bdc*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52bdd*4 +0x02000000,0xb885); +reg_write( DDR_REG_BASE +0x52bde*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52bdf*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52be0*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52be1*4 +0x02000000,0xe0ee); +reg_write( DDR_REG_BASE +0x52be2*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52be3*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52be4*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52be5*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52be6*4 +0x02000000,0x1ea); +reg_write( DDR_REG_BASE +0x52be7*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x52be8*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52be9*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52bea*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x52beb*4 +0x02000000,0x7d0f); +reg_write( DDR_REG_BASE +0x52bec*4 +0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x52bed*4 +0x02000000,0x70b1); +reg_write( DDR_REG_BASE +0x52bee*4 +0x02000000,0x4c6); +reg_write( DDR_REG_BASE +0x52bef*4 +0x02000000,0xffed); +reg_write( DDR_REG_BASE +0x52bf0*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x52bf1*4 +0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x52bf2*4 +0x02000000,0x3d0a); +reg_write( DDR_REG_BASE +0x52bf3*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52bf4*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52bf5*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52bf6*4 +0x02000000,0xc0e6); +reg_write( DDR_REG_BASE +0x52bf7*4 +0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x52bf8*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52bf9*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x52bfa*4 +0x02000000,0x8ba0); +reg_write( DDR_REG_BASE +0x52bfb*4 +0x02000000,0x8b81); +reg_write( DDR_REG_BASE +0x52bfc*4 +0x02000000,0x251f); +reg_write( DDR_REG_BASE +0x52bfd*4 +0x02000000,0x108f); +reg_write( DDR_REG_BASE +0x52bfe*4 +0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x52bff*4 +0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x52c00*4 +0x02000000,0x1f9e); +reg_write( DDR_REG_BASE +0x52c01*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52c02*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52c03*4 +0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x52c04*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52c05*4 +0x02000000,0x2114); +reg_write( DDR_REG_BASE +0x52c06*4 +0x02000000,0x38e); +reg_write( DDR_REG_BASE +0x52c07*4 +0x02000000,0x2605); +reg_write( DDR_REG_BASE +0x52c08*4 +0x02000000,0x301e); +reg_write( DDR_REG_BASE +0x52c09*4 +0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x52c0a*4 +0x02000000,0x783); +reg_write( DDR_REG_BASE +0x52c0b*4 +0x02000000,0x7b7b); +reg_write( DDR_REG_BASE +0x52c0c*4 +0x02000000,0xbb91); +reg_write( DDR_REG_BASE +0x52c0d*4 +0x02000000,0xbb9c); +reg_write( DDR_REG_BASE +0x52c0e*4 +0x02000000,0xbb9f); +reg_write( DDR_REG_BASE +0x52c0f*4 +0x02000000,0x9360); +reg_write( DDR_REG_BASE +0x52c10*4 +0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x52c11*4 +0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x52c12*4 +0x02000000,0xb660); +reg_write( DDR_REG_BASE +0x52c13*4 +0x02000000,0x232f); +reg_write( DDR_REG_BASE +0x52c14*4 +0x02000000,0x2c7); +reg_write( DDR_REG_BASE +0x52c15*4 +0x02000000,0xbd7); +reg_write( DDR_REG_BASE +0x52c16*4 +0x02000000,0x80a4); +reg_write( DDR_REG_BASE +0x52c17*4 +0x02000000,0x7ef0); +reg_write( DDR_REG_BASE +0x52c18*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x52c19*4 +0x02000000,0xcf7); +reg_write( DDR_REG_BASE +0x52c1a*4 +0x02000000,0x9365); +reg_write( DDR_REG_BASE +0x52c1b*4 +0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x52c1c*4 +0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x52c1d*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52c1e*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52c1f*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52c20*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52c21*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x52c22*4 +0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x52c23*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52c24*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52c25*4 +0x02000000,0x4728); +reg_write( DDR_REG_BASE +0x52c26*4 +0x02000000,0x7afd); +reg_write( DDR_REG_BASE +0x52c27*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x52c28*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52c29*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52c2a*4 +0x02000000,0xb2); +reg_write( DDR_REG_BASE +0x52c2b*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52c2c*4 +0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x52c2d*4 +0x02000000,0x100c); +reg_write( DDR_REG_BASE +0x52c2e*4 +0x02000000,0x2245); +reg_write( DDR_REG_BASE +0x52c2f*4 +0x02000000,0x602); +reg_write( DDR_REG_BASE +0x52c30*4 +0x02000000,0x7204); +reg_write( DDR_REG_BASE +0x52c31*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x52c32*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x52c33*4 +0x02000000,0xb440); +reg_write( DDR_REG_BASE +0x52c34*4 +0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x52c35*4 +0x02000000,0x1002); +reg_write( DDR_REG_BASE +0x52c36*4 +0x02000000,0x92c0); +reg_write( DDR_REG_BASE +0x52c37*4 +0x02000000,0x7204); +reg_write( DDR_REG_BASE +0x52c38*4 +0x02000000,0xbfc1); +reg_write( DDR_REG_BASE +0x52c39*4 +0x02000000,0x78a5); +reg_write( DDR_REG_BASE +0x52c3a*4 +0x02000000,0x6f43); +reg_write( DDR_REG_BASE +0x52c3b*4 +0x02000000,0x90a0); +reg_write( DDR_REG_BASE +0x52c3c*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52c3d*4 +0x02000000,0x2244); +reg_write( DDR_REG_BASE +0x52c3e*4 +0x02000000,0x7c3); +reg_write( DDR_REG_BASE +0x52c3f*4 +0x02000000,0xeb06); +reg_write( DDR_REG_BASE +0x52c40*4 +0x02000000,0xbb61); +reg_write( DDR_REG_BASE +0x52c41*4 +0x02000000,0xb01); +reg_write( DDR_REG_BASE +0x52c42*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x52c43*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52c44*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x52c45*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x52c46*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x52c47*4 +0x02000000,0x83); +reg_write( DDR_REG_BASE +0x52c48*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52c49*4 +0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x52c4a*4 +0x02000000,0x17cc); +reg_write( DDR_REG_BASE +0x52c4b*4 +0x02000000,0xec06); +reg_write( DDR_REG_BASE +0x52c4c*4 +0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x52c4d*4 +0x02000000,0xc01); +reg_write( DDR_REG_BASE +0x52c4e*4 +0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x52c4f*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52c50*4 +0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x52c51*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52c52*4 +0x02000000,0xcc); +reg_write( DDR_REG_BASE +0x52c53*4 +0x02000000,0x6f66); +reg_write( DDR_REG_BASE +0x52c54*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52c55*4 +0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x52c56*4 +0x02000000,0x7db); +reg_write( DDR_REG_BASE +0x52c57*4 +0x02000000,0xb11); +reg_write( DDR_REG_BASE +0x52c58*4 +0x02000000,0x3010); +reg_write( DDR_REG_BASE +0x52c59*4 +0x02000000,0x2342); +reg_write( DDR_REG_BASE +0x52c5a*4 +0x02000000,0x305b); +reg_write( DDR_REG_BASE +0x52c5b*4 +0x02000000,0xbff); +reg_write( DDR_REG_BASE +0x52c5c*4 +0x02000000,0xb031); +reg_write( DDR_REG_BASE +0x52c5d*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52c5e*4 +0x02000000,0xbbc4); +reg_write( DDR_REG_BASE +0x52c5f*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x52c60*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x52c61*4 +0x02000000,0x2405); +reg_write( DDR_REG_BASE +0x52c62*4 +0x02000000,0x101e); +reg_write( DDR_REG_BASE +0x52c63*4 +0x02000000,0x2740); +reg_write( DDR_REG_BASE +0x52c64*4 +0x02000000,0x124c); +reg_write( DDR_REG_BASE +0x52c65*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52c66*4 +0x02000000,0x2444); +reg_write( DDR_REG_BASE +0x52c67*4 +0x02000000,0x17ce); +reg_write( DDR_REG_BASE +0x52c68*4 +0x02000000,0xee05); +reg_write( DDR_REG_BASE +0x52c69*4 +0x02000000,0xbe61); +reg_write( DDR_REG_BASE +0x52c6a*4 +0x02000000,0xeff); +reg_write( DDR_REG_BASE +0x52c6b*4 +0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x52c6c*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52c6d*4 +0x02000000,0xbfc4); +reg_write( DDR_REG_BASE +0x52c6e*4 +0x02000000,0x2244); +reg_write( DDR_REG_BASE +0x52c6f*4 +0x02000000,0x7ce); +reg_write( DDR_REG_BASE +0x52c70*4 +0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x52c71*4 +0x02000000,0xee06); +reg_write( DDR_REG_BASE +0x52c72*4 +0x02000000,0xbe61); +reg_write( DDR_REG_BASE +0x52c73*4 +0x02000000,0xe01); +reg_write( DDR_REG_BASE +0x52c74*4 +0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x52c75*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52c76*4 +0x02000000,0xbcc4); +reg_write( DDR_REG_BASE +0x52c77*4 +0x02000000,0x2244); +reg_write( DDR_REG_BASE +0x52c78*4 +0x02000000,0x8e); +reg_write( DDR_REG_BASE +0x52c79*4 +0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x52c7a*4 +0x02000000,0xef05); +reg_write( DDR_REG_BASE +0x52c7b*4 +0x02000000,0xbf61); +reg_write( DDR_REG_BASE +0x52c7c*4 +0x02000000,0xfff); +reg_write( DDR_REG_BASE +0x52c7d*4 +0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x52c7e*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52c7f*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x52c80*4 +0x02000000,0x200); +reg_write( DDR_REG_BASE +0x52c81*4 +0x02000000,0xbac0); +reg_write( DDR_REG_BASE +0x52c82*4 +0x02000000,0x7e45); +reg_write( DDR_REG_BASE +0x52c83*4 +0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x52c84*4 +0x02000000,0xeb05); +reg_write( DDR_REG_BASE +0x52c85*4 +0x02000000,0xbb61); +reg_write( DDR_REG_BASE +0x52c86*4 +0x02000000,0xbff); +reg_write( DDR_REG_BASE +0x52c87*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x52c88*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52c89*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52c8a*4 +0x02000000,0x780); +reg_write( DDR_REG_BASE +0x52c8b*4 +0x02000000,0x2244); +reg_write( DDR_REG_BASE +0x52c8c*4 +0x02000000,0x103); +reg_write( DDR_REG_BASE +0x52c8d*4 +0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x52c8e*4 +0x02000000,0xec05); +reg_write( DDR_REG_BASE +0x52c8f*4 +0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x52c90*4 +0x02000000,0xcff); +reg_write( DDR_REG_BASE +0x52c91*4 +0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x52c92*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52c93*4 +0x02000000,0x7bc5); +reg_write( DDR_REG_BASE +0x52c94*4 +0x02000000,0x2244); +reg_write( DDR_REG_BASE +0x52c95*4 +0x02000000,0x202); +reg_write( DDR_REG_BASE +0x52c96*4 +0x02000000,0x7a65); +reg_write( DDR_REG_BASE +0x52c97*4 +0x02000000,0x225f); +reg_write( DDR_REG_BASE +0x52c98*4 +0x02000000,0x402); +reg_write( DDR_REG_BASE +0x52c99*4 +0x02000000,0xdd2); +reg_write( DDR_REG_BASE +0x52c9a*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52c9b*4 +0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x52c9c*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52c9d*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52c9e*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52c9f*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52ca0*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52ca1*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52ca2*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52ca3*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x52ca4*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52ca5*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x52ca6*4 +0x02000000,0x8d80); +reg_write( DDR_REG_BASE +0x52ca7*4 +0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x52ca8*4 +0x02000000,0x4718); +reg_write( DDR_REG_BASE +0x52ca9*4 +0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x52caa*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52cab*4 +0x02000000,0xea0d); +reg_write( DDR_REG_BASE +0x52cac*4 +0x02000000,0x245f); +reg_write( DDR_REG_BASE +0x52cad*4 +0x02000000,0x1243); +reg_write( DDR_REG_BASE +0x52cae*4 +0x02000000,0xa1b); +reg_write( DDR_REG_BASE +0x52caf*4 +0x02000000,0xb1); +reg_write( DDR_REG_BASE +0x52cb0*4 +0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x52cb1*4 +0x02000000,0xe308); +reg_write( DDR_REG_BASE +0x52cb2*4 +0x02000000,0xd809); +reg_write( DDR_REG_BASE +0x52cb3*4 +0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x52cb4*4 +0x02000000,0x234a); +reg_write( DDR_REG_BASE +0x52cb5*4 +0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x52cb6*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x52cb7*4 +0x02000000,0x7b9b); +reg_write( DDR_REG_BASE +0x52cb8*4 +0x02000000,0x74ed); +reg_write( DDR_REG_BASE +0x52cb9*4 +0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x52cba*4 +0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x52cbb*4 +0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x52cbc*4 +0x02000000,0x1501); +reg_write( DDR_REG_BASE +0x52cbd*4 +0x02000000,0x109e); +reg_write( DDR_REG_BASE +0x52cbe*4 +0x02000000,0xf023); +reg_write( DDR_REG_BASE +0x52cbf*4 +0x02000000,0x45c9); +reg_write( DDR_REG_BASE +0x52cc0*4 +0x02000000,0x259a); +reg_write( DDR_REG_BASE +0x52cc1*4 +0x02000000,0x1008); +reg_write( DDR_REG_BASE +0x52cc2*4 +0x02000000,0x241a); +reg_write( DDR_REG_BASE +0x52cc3*4 +0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x52cc4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52cc5*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52cc6*4 +0x02000000,0x7aa5); +reg_write( DDR_REG_BASE +0x52cc7*4 +0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x52cc8*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x52cc9*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52cca*4 +0x02000000,0x64); +reg_write( DDR_REG_BASE +0x52ccb*4 +0x02000000,0xb1f); +reg_write( DDR_REG_BASE +0x52ccc*4 +0x02000000,0x3030); +reg_write( DDR_REG_BASE +0x52ccd*4 +0x02000000,0x9a40); +reg_write( DDR_REG_BASE +0x52cce*4 +0x02000000,0x258a); +reg_write( DDR_REG_BASE +0x52ccf*4 +0x02000000,0x1fcf); +reg_write( DDR_REG_BASE +0x52cd0*4 +0x02000000,0x7d44); +reg_write( DDR_REG_BASE +0x52cd1*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52cd2*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52cd3*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52cd4*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52cd5*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x52cd6*4 +0x02000000,0x2284); +reg_write( DDR_REG_BASE +0x52cd7*4 +0x02000000,0x81f); +reg_write( DDR_REG_BASE +0x52cd8*4 +0x02000000,0x62ba); +reg_write( DDR_REG_BASE +0x52cd9*4 +0x02000000,0x2714); +reg_write( DDR_REG_BASE +0x52cda*4 +0x02000000,0x30cd); +reg_write( DDR_REG_BASE +0x52cdb*4 +0x02000000,0xb540); +reg_write( DDR_REG_BASE +0x52cdc*4 +0x02000000,0x66fe); +reg_write( DDR_REG_BASE +0x52cdd*4 +0x02000000,0x631b); +reg_write( DDR_REG_BASE +0x52cde*4 +0x02000000,0x9c3); +reg_write( DDR_REG_BASE +0x52cdf*4 +0x02000000,0x8385); +reg_write( DDR_REG_BASE +0x52ce0*4 +0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x52ce1*4 +0x02000000,0xefd); +reg_write( DDR_REG_BASE +0x52ce2*4 +0x02000000,0xb325); +reg_write( DDR_REG_BASE +0x52ce3*4 +0x02000000,0x4669); +reg_write( DDR_REG_BASE +0x52ce4*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52ce5*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52ce6*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52ce7*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52ce8*4 +0x02000000,0x8819); +reg_write( DDR_REG_BASE +0x52ce9*4 +0x02000000,0xb863); +reg_write( DDR_REG_BASE +0x52cea*4 +0x02000000,0x7314); +reg_write( DDR_REG_BASE +0x52ceb*4 +0x02000000,0x20e0); +reg_write( DDR_REG_BASE +0x52cec*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x52ced*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52cee*4 +0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x52cef*4 +0x02000000,0x1e4c); +reg_write( DDR_REG_BASE +0x52cf0*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x52cf1*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x52cf2*4 +0x02000000,0xb041); +reg_write( DDR_REG_BASE +0x52cf3*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52cf4*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x52cf5*4 +0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x52cf6*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x52cf7*4 +0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x52cf8*4 +0x02000000,0x70ef); +reg_write( DDR_REG_BASE +0x52cf9*4 +0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x52cfa*4 +0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x52cfb*4 +0x02000000,0xc82); +reg_write( DDR_REG_BASE +0x52cfc*4 +0x02000000,0x605c); +reg_write( DDR_REG_BASE +0x52cfd*4 +0x02000000,0x275a); +reg_write( DDR_REG_BASE +0x52cfe*4 +0x02000000,0x3642); +reg_write( DDR_REG_BASE +0x52cff*4 +0x02000000,0x71e7); +reg_write( DDR_REG_BASE +0x52d00*4 +0x02000000,0x629a); +reg_write( DDR_REG_BASE +0x52d01*4 +0x02000000,0x623c); +reg_write( DDR_REG_BASE +0x52d02*4 +0x02000000,0x2600); +reg_write( DDR_REG_BASE +0x52d03*4 +0x02000000,0x3682); +reg_write( DDR_REG_BASE +0x52d04*4 +0x02000000,0x123c); +reg_write( DDR_REG_BASE +0x52d05*4 +0x02000000,0x82); +reg_write( DDR_REG_BASE +0x52d06*4 +0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x52d07*4 +0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x52d08*4 +0x02000000,0xac40); +reg_write( DDR_REG_BASE +0x52d09*4 +0x02000000,0xfe5); +reg_write( DDR_REG_BASE +0x52d0a*4 +0x02000000,0xb094); +reg_write( DDR_REG_BASE +0x52d0b*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x52d0c*4 +0x02000000,0xbd9); +reg_write( DDR_REG_BASE +0x52d0d*4 +0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x52d0e*4 +0x02000000,0x2314); +reg_write( DDR_REG_BASE +0x52d0f*4 +0x02000000,0x10de); +reg_write( DDR_REG_BASE +0x52d10*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x52d11*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52d12*4 +0x02000000,0x791b); +reg_write( DDR_REG_BASE +0x52d13*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52d14*4 +0x02000000,0x2184); +reg_write( DDR_REG_BASE +0x52d15*4 +0x02000000,0xa82); +reg_write( DDR_REG_BASE +0x52d16*4 +0x02000000,0x2046); +reg_write( DDR_REG_BASE +0x52d17*4 +0x02000000,0xa80); +reg_write( DDR_REG_BASE +0x52d18*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x52d19*4 +0x02000000,0x215a); +reg_write( DDR_REG_BASE +0x52d1a*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x52d1b*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x52d1c*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x52d1d*4 +0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x52d1e*4 +0x02000000,0xcc1); +reg_write( DDR_REG_BASE +0x52d1f*4 +0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x52d20*4 +0x02000000,0x303); +reg_write( DDR_REG_BASE +0x52d21*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x52d22*4 +0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x52d23*4 +0x02000000,0x400); +reg_write( DDR_REG_BASE +0x52d24*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x52d25*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x52d26*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x52d27*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x52d28*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52d29*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x52d2a*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52d2b*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52d2c*4 +0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x52d2d*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x52d2e*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52d2f*4 +0x02000000,0xe000); +reg_write( DDR_REG_BASE +0x52d30*4 +0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x52d31*4 +0x02000000,0xe26); +reg_write( DDR_REG_BASE +0x52d32*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x52d33*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x52d34*4 +0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x52d35*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x52d36*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x52d37*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x52d38*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52d39*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52d3a*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52d3b*4 +0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x52d3c*4 +0x02000000,0x3b02); +reg_write( DDR_REG_BASE +0x52d3d*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52d3e*4 +0x02000000,0x709b); +reg_write( DDR_REG_BASE +0x52d3f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52d40*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52d41*4 +0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x52d42*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52d43*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52d44*4 +0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x52d45*4 +0x02000000,0xf8a5); +reg_write( DDR_REG_BASE +0x52d46*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52d47*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52d48*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52d49*4 +0x02000000,0xfbff); +reg_write( DDR_REG_BASE +0x52d4a*4 +0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x52d4b*4 +0x02000000,0x9f7); +reg_write( DDR_REG_BASE +0x52d4c*4 +0x02000000,0x8294); +reg_write( DDR_REG_BASE +0x52d4d*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52d4e*4 +0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x52d4f*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52d50*4 +0x02000000,0xaa); +reg_write( DDR_REG_BASE +0x52d51*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52d52*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52d53*4 +0x02000000,0x51f); +reg_write( DDR_REG_BASE +0x52d54*4 +0x02000000,0xda78); +reg_write( DDR_REG_BASE +0x52d55*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52d56*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52d57*4 +0x02000000,0x7085); +reg_write( DDR_REG_BASE +0x52d58*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52d59*4 +0x02000000,0xe0aa); +reg_write( DDR_REG_BASE +0x52d5a*4 +0x02000000,0xdce); +reg_write( DDR_REG_BASE +0x52d5b*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x52d5c*4 +0x02000000,0xc08d); +reg_write( DDR_REG_BASE +0x52d5d*4 +0x02000000,0xc08d); +reg_write( DDR_REG_BASE +0x52d5e*4 +0x02000000,0xace); +reg_write( DDR_REG_BASE +0x52d5f*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x52d60*4 +0x02000000,0xd978); +reg_write( DDR_REG_BASE +0x52d61*4 +0x02000000,0xe76); +reg_write( DDR_REG_BASE +0x52d62*4 +0x02000000,0xfd8f); +reg_write( DDR_REG_BASE +0x52d63*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52d64*4 +0x02000000,0xb56); +reg_write( DDR_REG_BASE +0x52d65*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52d66*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52d67*4 +0x02000000,0xef6); +reg_write( DDR_REG_BASE +0x52d68*4 +0x02000000,0xff0f); +reg_write( DDR_REG_BASE +0x52d69*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52d6a*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52d6b*4 +0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x52d6c*4 +0x02000000,0xb12); +reg_write( DDR_REG_BASE +0x52d6d*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52d6e*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52d6f*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52d70*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52d71*4 +0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x52d72*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52d73*4 +0x02000000,0xaa2); +reg_write( DDR_REG_BASE +0x52d74*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52d75*4 +0x02000000,0xdaf7); +reg_write( DDR_REG_BASE +0x52d76*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x52d77*4 +0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x52d78*4 +0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x52d79*4 +0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x52d7a*4 +0x02000000,0xe805); +reg_write( DDR_REG_BASE +0x52d7b*4 +0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x52d7c*4 +0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x52d7d*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x52d7e*4 +0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x52d7f*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x52d80*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52d81*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x52d82*4 +0x02000000,0x225a); +reg_write( DDR_REG_BASE +0x52d83*4 +0x02000000,0x102); +reg_write( DDR_REG_BASE +0x52d84*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x52d85*4 +0x02000000,0x8d20); +reg_write( DDR_REG_BASE +0x52d86*4 +0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x52d87*4 +0x02000000,0xf7f); +reg_write( DDR_REG_BASE +0x52d88*4 +0x02000000,0x220f); +reg_write( DDR_REG_BASE +0x52d89*4 +0x02000000,0xe); +reg_write( DDR_REG_BASE +0x52d8a*4 +0x02000000,0x265a); +reg_write( DDR_REG_BASE +0x52d8b*4 +0x02000000,0x1100); +reg_write( DDR_REG_BASE +0x52d8c*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52d8d*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x52d8e*4 +0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x52d8f*4 +0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x52d90*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52d91*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52d92*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x52d93*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52d94*4 +0x02000000,0x640); +reg_write( DDR_REG_BASE +0x52d95*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52d96*4 +0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x52d97*4 +0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x52d98*4 +0x02000000,0xc103); +reg_write( DDR_REG_BASE +0x52d99*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x52d9a*4 +0x02000000,0x2100); +reg_write( DDR_REG_BASE +0x52d9b*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52d9c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52d9d*4 +0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x52d9e*4 +0x02000000,0xd02); +reg_write( DDR_REG_BASE +0x52d9f*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x52da0*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52da1*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52da2*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52da3*4 +0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x52da4*4 +0x02000000,0xea2); +reg_write( DDR_REG_BASE +0x52da5*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x52da6*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52da7*4 +0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x52da8*4 +0x02000000,0x7ecf); +reg_write( DDR_REG_BASE +0x52da9*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52daa*4 +0x02000000,0xc81); +reg_write( DDR_REG_BASE +0x52dab*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52dac*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x52dad*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52dae*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52daf*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52db0*4 +0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x52db1*4 +0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x52db2*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x52db3*4 +0x02000000,0x44); +reg_write( DDR_REG_BASE +0x52db4*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x52db5*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52db6*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52db7*4 +0x02000000,0xe024); +reg_write( DDR_REG_BASE +0x52db8*4 +0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x52db9*4 +0x02000000,0xb0e6); +reg_write( DDR_REG_BASE +0x52dba*4 +0x02000000,0x18fe); +reg_write( DDR_REG_BASE +0x52dbb*4 +0x02000000,0x8044); +reg_write( DDR_REG_BASE +0x52dbc*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52dbd*4 +0x02000000,0xba2); +reg_write( DDR_REG_BASE +0x52dbe*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x52dbf*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52dc0*4 +0x02000000,0xd830); +reg_write( DDR_REG_BASE +0x52dc1*4 +0x02000000,0xf16); +reg_write( DDR_REG_BASE +0x52dc2*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52dc3*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52dc4*4 +0x02000000,0xd9e); +reg_write( DDR_REG_BASE +0x52dc5*4 +0x02000000,0xfe0f); +reg_write( DDR_REG_BASE +0x52dc6*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x52dc7*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52dc8*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52dc9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52dca*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x52dcb*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52dcc*4 +0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x52dcd*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x52dce*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x52dcf*4 +0x02000000,0xfc3); +reg_write( DDR_REG_BASE +0x52dd0*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52dd1*4 +0x02000000,0x8fb); +reg_write( DDR_REG_BASE +0x52dd2*4 +0x02000000,0x8534); +reg_write( DDR_REG_BASE +0x52dd3*4 +0x02000000,0xc188); +reg_write( DDR_REG_BASE +0x52dd4*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52dd5*4 +0x02000000,0xeee); +reg_write( DDR_REG_BASE +0x52dd6*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52dd7*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52dd8*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52dd9*4 +0x02000000,0xa6e); +reg_write( DDR_REG_BASE +0x52dda*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52ddb*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52ddc*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52ddd*4 +0x02000000,0xb62); +reg_write( DDR_REG_BASE +0x52dde*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x52ddf*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52de0*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x52de1*4 +0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x52de2*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x52de3*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52de4*4 +0x02000000,0xe174); +reg_write( DDR_REG_BASE +0x52de5*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x52de6*4 +0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x52de7*4 +0x02000000,0xb601); +reg_write( DDR_REG_BASE +0x52de8*4 +0x02000000,0x1e59); +reg_write( DDR_REG_BASE +0x52de9*4 +0x02000000,0x901d); +reg_write( DDR_REG_BASE +0x52dea*4 +0x02000000,0xf7d); +reg_write( DDR_REG_BASE +0x52deb*4 +0x02000000,0x1a35); +reg_write( DDR_REG_BASE +0x52dec*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52ded*4 +0x02000000,0xebe); +reg_write( DDR_REG_BASE +0x52dee*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52def*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52df0*4 +0x02000000,0x1503); +reg_write( DDR_REG_BASE +0x52df1*4 +0x02000000,0x108b); +reg_write( DDR_REG_BASE +0x52df2*4 +0x02000000,0x8d82); +reg_write( DDR_REG_BASE +0x52df3*4 +0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x52df4*4 +0x02000000,0xf02a); +reg_write( DDR_REG_BASE +0x52df5*4 +0x02000000,0x241a); +reg_write( DDR_REG_BASE +0x52df6*4 +0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x52df7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52df8*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52df9*4 +0x02000000,0x206c); +reg_write( DDR_REG_BASE +0x52dfa*4 +0x02000000,0x302); +reg_write( DDR_REG_BASE +0x52dfb*4 +0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x52dfc*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52dfd*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52dfe*4 +0x02000000,0x166); +reg_write( DDR_REG_BASE +0x52dff*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x52e00*4 +0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x52e01*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x52e02*4 +0x02000000,0xc088); +reg_write( DDR_REG_BASE +0x52e03*4 +0x02000000,0x6098); +reg_write( DDR_REG_BASE +0x52e04*4 +0x02000000,0x8820); +reg_write( DDR_REG_BASE +0x52e05*4 +0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x52e06*4 +0x02000000,0x7965); +reg_write( DDR_REG_BASE +0x52e07*4 +0x02000000,0xa820); +reg_write( DDR_REG_BASE +0x52e08*4 +0x02000000,0x241a); +reg_write( DDR_REG_BASE +0x52e09*4 +0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x52e0a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52e0b*4 +0x02000000,0x800); +reg_write( DDR_REG_BASE +0x52e0c*4 +0x02000000,0x2153); +reg_write( DDR_REG_BASE +0x52e0d*4 +0x02000000,0x80be); +reg_write( DDR_REG_BASE +0x52e0e*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52e0f*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52e10*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52e11*4 +0x02000000,0x800); +reg_write( DDR_REG_BASE +0x52e12*4 +0x02000000,0x7a05); +reg_write( DDR_REG_BASE +0x52e13*4 +0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x52e14*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x52e15*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52e16*4 +0x02000000,0x64); +reg_write( DDR_REG_BASE +0x52e17*4 +0x02000000,0x9200); +reg_write( DDR_REG_BASE +0x52e18*4 +0x02000000,0xf205); +reg_write( DDR_REG_BASE +0x52e19*4 +0x02000000,0x2080); +reg_write( DDR_REG_BASE +0x52e1a*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52e1b*4 +0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x52e1c*4 +0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x52e1d*4 +0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x52e1e*4 +0x02000000,0xbaf); +reg_write( DDR_REG_BASE +0x52e1f*4 +0x02000000,0x9325); +reg_write( DDR_REG_BASE +0x52e20*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52e21*4 +0x02000000,0x9de); +reg_write( DDR_REG_BASE +0x52e22*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52e23*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52e24*4 +0x02000000,0xb8d); +reg_write( DDR_REG_BASE +0x52e25*4 +0x02000000,0xb031); +reg_write( DDR_REG_BASE +0x52e26*4 +0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x52e27*4 +0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x52e28*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52e29*4 +0x02000000,0x6e); +reg_write( DDR_REG_BASE +0x52e2a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52e2b*4 +0x02000000,0xcfe); +reg_write( DDR_REG_BASE +0x52e2c*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x52e2d*4 +0x02000000,0x2378); +reg_write( DDR_REG_BASE +0x52e2e*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x52e2f*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52e30*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x52e31*4 +0x02000000,0xcc6); +reg_write( DDR_REG_BASE +0x52e32*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52e33*4 +0x02000000,0x1e02); +reg_write( DDR_REG_BASE +0x52e34*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x52e35*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52e36*4 +0x02000000,0xa16); +reg_write( DDR_REG_BASE +0x52e37*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52e38*4 +0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x52e39*4 +0x02000000,0xd840); +reg_write( DDR_REG_BASE +0x52e3a*4 +0x02000000,0xe22); +reg_write( DDR_REG_BASE +0x52e3b*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52e3c*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52e3d*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52e3e*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52e3f*4 +0x02000000,0xcc6); +reg_write( DDR_REG_BASE +0x52e40*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x52e41*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52e42*4 +0x02000000,0x8d43); +reg_write( DDR_REG_BASE +0x52e43*4 +0x02000000,0x8d62); +reg_write( DDR_REG_BASE +0x52e44*4 +0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x52e45*4 +0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x52e46*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x52e47*4 +0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x52e48*4 +0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x52e49*4 +0x02000000,0xb8e3); +reg_write( DDR_REG_BASE +0x52e4a*4 +0x02000000,0xd840); +reg_write( DDR_REG_BASE +0x52e4b*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x52e4c*4 +0x02000000,0x822); +reg_write( DDR_REG_BASE +0x52e4d*4 +0x02000000,0x7902); +reg_write( DDR_REG_BASE +0x52e4e*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52e4f*4 +0x02000000,0x7874); +reg_write( DDR_REG_BASE +0x52e50*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x52e51*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x52e52*4 +0x02000000,0xae7); +reg_write( DDR_REG_BASE +0x52e53*4 +0x02000000,0x80c5); +reg_write( DDR_REG_BASE +0x52e54*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x52e55*4 +0x02000000,0x9c2); +reg_write( DDR_REG_BASE +0x52e56*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52e57*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52e58*4 +0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x52e59*4 +0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x52e5a*4 +0x02000000,0x800); +reg_write( DDR_REG_BASE +0x52e5b*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52e5c*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52e5d*4 +0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x52e5e*4 +0x02000000,0x92a); +reg_write( DDR_REG_BASE +0x52e5f*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x52e60*4 +0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x52e61*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52e62*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52e63*4 +0x02000000,0x7044); +reg_write( DDR_REG_BASE +0x52e64*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52e65*4 +0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x52e66*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52e67*4 +0x02000000,0x7044); +reg_write( DDR_REG_BASE +0x52e68*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52e69*4 +0x02000000,0xe076); +reg_write( DDR_REG_BASE +0x52e6a*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52e6b*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52e6c*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52e6d*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52e6e*4 +0x02000000,0xe0aa); +reg_write( DDR_REG_BASE +0x52e6f*4 +0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x52e70*4 +0x02000000,0xf80f); +reg_write( DDR_REG_BASE +0x52e71*4 +0x02000000,0xb88a); +reg_write( DDR_REG_BASE +0x52e72*4 +0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x52e73*4 +0x02000000,0x9fd); +reg_write( DDR_REG_BASE +0x52e74*4 +0x02000000,0x8294); +reg_write( DDR_REG_BASE +0x52e75*4 +0x02000000,0xd72); +reg_write( DDR_REG_BASE +0x52e76*4 +0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x52e77*4 +0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x52e78*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52e79*4 +0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x52e7a*4 +0x02000000,0xf7f); +reg_write( DDR_REG_BASE +0x52e7b*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52e7c*4 +0x02000000,0xc81); +reg_write( DDR_REG_BASE +0x52e7d*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52e7e*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x52e7f*4 +0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x52e80*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x52e81*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52e82*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52e83*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52e84*4 +0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x52e85*4 +0x02000000,0xb36); +reg_write( DDR_REG_BASE +0x52e86*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x52e87*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52e88*4 +0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x52e89*4 +0x02000000,0x3b02); +reg_write( DDR_REG_BASE +0x52e8a*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52e8b*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52e8c*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52e8d*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52e8e*4 +0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x52e8f*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52e90*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52e91*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52e92*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x52e93*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52e94*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x52e95*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52e96*4 +0x02000000,0x94); +reg_write( DDR_REG_BASE +0x52e97*4 +0x02000000,0x9200); +reg_write( DDR_REG_BASE +0x52e98*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52e99*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52e9a*4 +0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x52e9b*4 +0x02000000,0x216c); +reg_write( DDR_REG_BASE +0x52e9c*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x52e9d*4 +0x02000000,0xa821); +reg_write( DDR_REG_BASE +0x52e9e*4 +0x02000000,0x8822); +reg_write( DDR_REG_BASE +0x52e9f*4 +0x02000000,0xb9c6); +reg_write( DDR_REG_BASE +0x52ea0*4 +0x02000000,0xa822); +reg_write( DDR_REG_BASE +0x52ea1*4 +0x02000000,0x882d); +reg_write( DDR_REG_BASE +0x52ea2*4 +0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x52ea3*4 +0x02000000,0xc02); +reg_write( DDR_REG_BASE +0x52ea4*4 +0x02000000,0x2285); +reg_write( DDR_REG_BASE +0x52ea5*4 +0x02000000,0x23f); +reg_write( DDR_REG_BASE +0x52ea6*4 +0x02000000,0x913); +reg_write( DDR_REG_BASE +0x52ea7*4 +0x02000000,0x17f); +reg_write( DDR_REG_BASE +0x52ea8*4 +0x02000000,0xa84d); +reg_write( DDR_REG_BASE +0x52ea9*4 +0x02000000,0x794f); +reg_write( DDR_REG_BASE +0x52eaa*4 +0x02000000,0xb985); +reg_write( DDR_REG_BASE +0x52eab*4 +0x02000000,0xa82d); +reg_write( DDR_REG_BASE +0x52eac*4 +0x02000000,0x8823); +reg_write( DDR_REG_BASE +0x52ead*4 +0x02000000,0xb987); +reg_write( DDR_REG_BASE +0x52eae*4 +0x02000000,0xa823); +reg_write( DDR_REG_BASE +0x52eaf*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52eb0*4 +0x02000000,0xa838); +reg_write( DDR_REG_BASE +0x52eb1*4 +0x02000000,0xa831); +reg_write( DDR_REG_BASE +0x52eb2*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x52eb3*4 +0x02000000,0xa830); +reg_write( DDR_REG_BASE +0x52eb4*4 +0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x52eb5*4 +0x02000000,0xb9a); +reg_write( DDR_REG_BASE +0x52eb6*4 +0x02000000,0xfdcf); +reg_write( DDR_REG_BASE +0x52eb7*4 +0x02000000,0x256f); +reg_write( DDR_REG_BASE +0x52eb8*4 +0x02000000,0x1343); +reg_write( DDR_REG_BASE +0x52eb9*4 +0x02000000,0x9560); +reg_write( DDR_REG_BASE +0x52eba*4 +0x02000000,0xda20); +reg_write( DDR_REG_BASE +0x52ebb*4 +0x02000000,0xd940); +reg_write( DDR_REG_BASE +0x52ebc*4 +0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x52ebd*4 +0x02000000,0x85ca); +reg_write( DDR_REG_BASE +0x52ebe*4 +0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x52ebf*4 +0x02000000,0xc2d); +reg_write( DDR_REG_BASE +0x52ec0*4 +0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x52ec1*4 +0x02000000,0x89d0); +reg_write( DDR_REG_BASE +0x52ec2*4 +0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x52ec3*4 +0x02000000,0x4d); +reg_write( DDR_REG_BASE +0x52ec4*4 +0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x52ec5*4 +0x02000000,0x8fd8); +reg_write( DDR_REG_BASE +0x52ec6*4 +0x02000000,0xd950); +reg_write( DDR_REG_BASE +0x52ec7*4 +0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x52ec8*4 +0x02000000,0x4d); +reg_write( DDR_REG_BASE +0x52ec9*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x52eca*4 +0x02000000,0x5ca); +reg_write( DDR_REG_BASE +0x52ecb*4 +0x02000000,0x213c); +reg_write( DDR_REG_BASE +0x52ecc*4 +0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x52ecd*4 +0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x52ece*4 +0x02000000,0x89d0); +reg_write( DDR_REG_BASE +0x52ecf*4 +0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x52ed0*4 +0x02000000,0xad); +reg_write( DDR_REG_BASE +0x52ed1*4 +0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x52ed2*4 +0x02000000,0x8fd8); +reg_write( DDR_REG_BASE +0x52ed3*4 +0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x52ed4*4 +0x02000000,0xed); +reg_write( DDR_REG_BASE +0x52ed5*4 +0x02000000,0x73d3); +reg_write( DDR_REG_BASE +0x52ed6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52ed7*4 +0x02000000,0x95f); +reg_write( DDR_REG_BASE +0x52ed8*4 +0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x52ed9*4 +0x02000000,0x12d); +reg_write( DDR_REG_BASE +0x52eda*4 +0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x52edb*4 +0x02000000,0x8c); +reg_write( DDR_REG_BASE +0x52edc*4 +0x02000000,0x15fe); +reg_write( DDR_REG_BASE +0x52edd*4 +0x02000000,0x9081); +reg_write( DDR_REG_BASE +0x52ede*4 +0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x52edf*4 +0x02000000,0x400); +reg_write( DDR_REG_BASE +0x52ee0*4 +0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x52ee1*4 +0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x52ee2*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52ee3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52ee4*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52ee5*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52ee6*4 +0x02000000,0xf8); +reg_write( DDR_REG_BASE +0x52ee7*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52ee8*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52ee9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52eea*4 +0x02000000,0x1ff0); +reg_write( DDR_REG_BASE +0x52eeb*4 +0x02000000,0xb881); +reg_write( DDR_REG_BASE +0x52eec*4 +0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x52eed*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x52eee*4 +0x02000000,0x7224); +reg_write( DDR_REG_BASE +0x52eef*4 +0x02000000,0x7965); +reg_write( DDR_REG_BASE +0x52ef0*4 +0x02000000,0xb280); +reg_write( DDR_REG_BASE +0x52ef1*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x52ef2*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x52ef3*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52ef4*4 +0x02000000,0xc0e4); +reg_write( DDR_REG_BASE +0x52ef5*4 +0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x52ef6*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x52ef7*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52ef8*4 +0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x52ef9*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x52efa*4 +0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x52efb*4 +0x02000000,0x225a); +reg_write( DDR_REG_BASE +0x52efc*4 +0x02000000,0xc8c); +reg_write( DDR_REG_BASE +0x52efd*4 +0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x52efe*4 +0x02000000,0x609d); +reg_write( DDR_REG_BASE +0x52eff*4 +0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x52f00*4 +0x02000000,0x64c); +reg_write( DDR_REG_BASE +0x52f01*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x52f02*4 +0x02000000,0x64bc); +reg_write( DDR_REG_BASE +0x52f03*4 +0x02000000,0x642c); +reg_write( DDR_REG_BASE +0x52f04*4 +0x02000000,0x1e3c); +reg_write( DDR_REG_BASE +0x52f05*4 +0x02000000,0x1302); +reg_write( DDR_REG_BASE +0x52f06*4 +0x02000000,0xbeb); +reg_write( DDR_REG_BASE +0x52f07*4 +0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x52f08*4 +0x02000000,0x2300); +reg_write( DDR_REG_BASE +0x52f09*4 +0x02000000,0x168e); +reg_write( DDR_REG_BASE +0x52f0a*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x52f0b*4 +0x02000000,0xadf); +reg_write( DDR_REG_BASE +0x52f0c*4 +0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x52f0d*4 +0x02000000,0x2614); +reg_write( DDR_REG_BASE +0x52f0e*4 +0x02000000,0x308b); +reg_write( DDR_REG_BASE +0x52f0f*4 +0x02000000,0xc4c4); +reg_write( DDR_REG_BASE +0x52f10*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52f11*4 +0x02000000,0x1209); +reg_write( DDR_REG_BASE +0x52f12*4 +0x02000000,0x308d); +reg_write( DDR_REG_BASE +0x52f13*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x52f14*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x52f15*4 +0x02000000,0x1a09); +reg_write( DDR_REG_BASE +0x52f16*4 +0x02000000,0x3382); +reg_write( DDR_REG_BASE +0x52f17*4 +0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x52f18*4 +0x02000000,0x26f0); +reg_write( DDR_REG_BASE +0x52f19*4 +0x02000000,0x73c0); +reg_write( DDR_REG_BASE +0x52f1a*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52f1b*4 +0x02000000,0x8e8); +reg_write( DDR_REG_BASE +0x52f1c*4 +0x02000000,0xb62); +reg_write( DDR_REG_BASE +0x52f1d*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x52f1e*4 +0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x52f1f*4 +0x02000000,0xcc22); +reg_write( DDR_REG_BASE +0x52f20*4 +0x02000000,0xff1); +reg_write( DDR_REG_BASE +0x52f21*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52f22*4 +0x02000000,0x1a09); +reg_write( DDR_REG_BASE +0x52f23*4 +0x02000000,0x3342); +reg_write( DDR_REG_BASE +0x52f24*4 +0x02000000,0x1a22); +reg_write( DDR_REG_BASE +0x52f25*4 +0x02000000,0x339c); +reg_write( DDR_REG_BASE +0x52f26*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52f27*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52f28*4 +0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x52f29*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52f2a*4 +0x02000000,0x1ea); +reg_write( DDR_REG_BASE +0x52f2b*4 +0x02000000,0x9340); +reg_write( DDR_REG_BASE +0x52f2c*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52f2d*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52f2e*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52f2f*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52f30*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52f31*4 +0x02000000,0xfe00); +reg_write( DDR_REG_BASE +0x52f32*4 +0x02000000,0x2204); +reg_write( DDR_REG_BASE +0x52f33*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x52f34*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52f35*4 +0x02000000,0xc0ff); +reg_write( DDR_REG_BASE +0x52f36*4 +0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x52f37*4 +0x02000000,0x9341); +reg_write( DDR_REG_BASE +0x52f38*4 +0x02000000,0xb300); +reg_write( DDR_REG_BASE +0x52f39*4 +0x02000000,0xb962); +reg_write( DDR_REG_BASE +0x52f3a*4 +0x02000000,0x226c); +reg_write( DDR_REG_BASE +0x52f3b*4 +0x02000000,0x140); +reg_write( DDR_REG_BASE +0x52f3c*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52f3d*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x52f3e*4 +0x02000000,0xb301); +reg_write( DDR_REG_BASE +0x52f3f*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52f40*4 +0x02000000,0x7a1b); +reg_write( DDR_REG_BASE +0x52f41*4 +0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x52f42*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x52f43*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52f44*4 +0x02000000,0xe164); +reg_write( DDR_REG_BASE +0x52f45*4 +0x02000000,0x1a00); +reg_write( DDR_REG_BASE +0x52f46*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x52f47*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x52f48*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52f49*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x52f4a*4 +0x02000000,0x8a61); +reg_write( DDR_REG_BASE +0x52f4b*4 +0x02000000,0x8a80); +reg_write( DDR_REG_BASE +0x52f4c*4 +0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x52f4d*4 +0x02000000,0x241a); +reg_write( DDR_REG_BASE +0x52f4e*4 +0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x52f4f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52f50*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52f51*4 +0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x52f52*4 +0x02000000,0x7a05); +reg_write( DDR_REG_BASE +0x52f53*4 +0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x52f54*4 +0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x52f55*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x52f56*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52f57*4 +0x02000000,0x164); +reg_write( DDR_REG_BASE +0x52f58*4 +0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x52f59*4 +0x02000000,0xbeb); +reg_write( DDR_REG_BASE +0x52f5a*4 +0x02000000,0x8305); +reg_write( DDR_REG_BASE +0x52f5b*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52f5c*4 +0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x52f5d*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52f5e*4 +0x02000000,0x710d); +reg_write( DDR_REG_BASE +0x52f5f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52f60*4 +0x02000000,0x6); +reg_write( DDR_REG_BASE +0x52f61*4 +0x02000000,0xe56d); +reg_write( DDR_REG_BASE +0x52f62*4 +0x02000000,0x2d85); +reg_write( DDR_REG_BASE +0x52f63*4 +0x02000000,0x1b81); +reg_write( DDR_REG_BASE +0x52f64*4 +0x02000000,0x2553); +reg_write( DDR_REG_BASE +0x52f65*4 +0x02000000,0x9041); +reg_write( DDR_REG_BASE +0x52f66*4 +0x02000000,0xf205); +reg_write( DDR_REG_BASE +0x52f67*4 +0x02000000,0x78af); +reg_write( DDR_REG_BASE +0x52f68*4 +0x02000000,0x214e); +reg_write( DDR_REG_BASE +0x52f69*4 +0x02000000,0x10d); +reg_write( DDR_REG_BASE +0x52f6a*4 +0x02000000,0x651d); +reg_write( DDR_REG_BASE +0x52f6b*4 +0x02000000,0x7aaf); +reg_write( DDR_REG_BASE +0x52f6c*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52f6d*4 +0x02000000,0xaf); +reg_write( DDR_REG_BASE +0x52f6e*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52f6f*4 +0x02000000,0xfe2); +reg_write( DDR_REG_BASE +0x52f70*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52f71*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x52f72*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52f73*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52f74*4 +0x02000000,0x7c8); +reg_write( DDR_REG_BASE +0x52f75*4 +0x02000000,0xa8a0); +reg_write( DDR_REG_BASE +0x52f76*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x52f77*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52f78*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52f79*4 +0x02000000,0x266f); +reg_write( DDR_REG_BASE +0x52f7a*4 +0x02000000,0x15c3); +reg_write( DDR_REG_BASE +0x52f7b*4 +0x02000000,0x8e40); +reg_write( DDR_REG_BASE +0x52f7c*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x52f7d*4 +0x02000000,0xea17); +reg_write( DDR_REG_BASE +0x52f7e*4 +0x02000000,0xc1a); +reg_write( DDR_REG_BASE +0x52f7f*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52f80*4 +0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x52f81*4 +0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x52f82*4 +0x02000000,0xe887); +reg_write( DDR_REG_BASE +0x52f83*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52f84*4 +0x02000000,0xd6); +reg_write( DDR_REG_BASE +0x52f85*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52f86*4 +0x02000000,0xa46); +reg_write( DDR_REG_BASE +0x52f87*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x52f88*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52f89*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x52f8a*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52f8b*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52f8c*4 +0x02000000,0x7f05); +reg_write( DDR_REG_BASE +0x52f8d*4 +0x02000000,0x78bb); +reg_write( DDR_REG_BASE +0x52f8e*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52f8f*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52f90*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52f91*4 +0x02000000,0xfe92); +reg_write( DDR_REG_BASE +0x52f92*4 +0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x52f93*4 +0x02000000,0x16ff); +reg_write( DDR_REG_BASE +0x52f94*4 +0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x52f95*4 +0x02000000,0xea18); +reg_write( DDR_REG_BASE +0x52f96*4 +0x02000000,0xbea); +reg_write( DDR_REG_BASE +0x52f97*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52f98*4 +0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x52f99*4 +0x02000000,0x228c); +reg_write( DDR_REG_BASE +0x52f9a*4 +0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x52f9b*4 +0x02000000,0xf209); +reg_write( DDR_REG_BASE +0x52f9c*4 +0x02000000,0xe888); +reg_write( DDR_REG_BASE +0x52f9d*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52f9e*4 +0x02000000,0xd7); +reg_write( DDR_REG_BASE +0x52f9f*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52fa0*4 +0x02000000,0xa12); +reg_write( DDR_REG_BASE +0x52fa1*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x52fa2*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52fa3*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52fa4*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52fa5*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52fa6*4 +0x02000000,0x79bb); +reg_write( DDR_REG_BASE +0x52fa7*4 +0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x52fa8*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52fa9*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52faa*4 +0x02000000,0xfe9a); +reg_write( DDR_REG_BASE +0x52fab*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x52fac*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52fad*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52fae*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x52faf*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52fb0*4 +0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x52fb1*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52fb2*4 +0x02000000,0x9); +reg_write( DDR_REG_BASE +0x52fb3*4 +0x02000000,0xea1a); +reg_write( DDR_REG_BASE +0x52fb4*4 +0x02000000,0xa23); +reg_write( DDR_REG_BASE +0x52fb5*4 +0x02000000,0xa30); +reg_write( DDR_REG_BASE +0x52fb6*4 +0x02000000,0x720c); +reg_write( DDR_REG_BASE +0x52fb7*4 +0x02000000,0x228c); +reg_write( DDR_REG_BASE +0x52fb8*4 +0x02000000,0x8c03); +reg_write( DDR_REG_BASE +0x52fb9*4 +0x02000000,0xf20c); +reg_write( DDR_REG_BASE +0x52fba*4 +0x02000000,0xe2f8); +reg_write( DDR_REG_BASE +0x52fbb*4 +0x02000000,0xf404); +reg_write( DDR_REG_BASE +0x52fbc*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52fbd*4 +0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x52fbe*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52fbf*4 +0x02000000,0xd8); +reg_write( DDR_REG_BASE +0x52fc0*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52fc1*4 +0x02000000,0x9d2); +reg_write( DDR_REG_BASE +0x52fc2*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x52fc3*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52fc4*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52fc5*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52fc6*4 +0x02000000,0x401); +reg_write( DDR_REG_BASE +0x52fc7*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52fc8*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52fc9*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52fca*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52fcb*4 +0x02000000,0xe0a0); +reg_write( DDR_REG_BASE +0x52fcc*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x52fcd*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52fce*4 +0x02000000,0xc0e6); +reg_write( DDR_REG_BASE +0x52fcf*4 +0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x52fd0*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x52fd1*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52fd2*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52fd3*4 +0x02000000,0xff64); +reg_write( DDR_REG_BASE +0x52fd4*4 +0x02000000,0xb1e0); +reg_write( DDR_REG_BASE +0x52fd5*4 +0x02000000,0x1904); +reg_write( DDR_REG_BASE +0x52fd6*4 +0x02000000,0x45); +reg_write( DDR_REG_BASE +0x52fd7*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x52fd8*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52fd9*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x52fda*4 +0x02000000,0x8a21); +reg_write( DDR_REG_BASE +0x52fdb*4 +0x02000000,0x8ac0); +reg_write( DDR_REG_BASE +0x52fdc*4 +0x02000000,0xf039); +reg_write( DDR_REG_BASE +0x52fdd*4 +0x02000000,0x228c); +reg_write( DDR_REG_BASE +0x52fde*4 +0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x52fdf*4 +0x02000000,0xf418); +reg_write( DDR_REG_BASE +0x52fe0*4 +0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x52fe1*4 +0x02000000,0x1f83); +reg_write( DDR_REG_BASE +0x52fe2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52fe3*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52fe4*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x52fe5*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52fe6*4 +0x02000000,0x1f64); +reg_write( DDR_REG_BASE +0x52fe7*4 +0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x52fe8*4 +0x02000000,0x8c); +reg_write( DDR_REG_BASE +0x52fe9*4 +0x02000000,0x7444); +reg_write( DDR_REG_BASE +0x52fea*4 +0x02000000,0x7a65); +reg_write( DDR_REG_BASE +0x52feb*4 +0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x52fec*4 +0x02000000,0xb51); +reg_write( DDR_REG_BASE +0x52fed*4 +0x02000000,0x123f); +reg_write( DDR_REG_BASE +0x52fee*4 +0x02000000,0xb2e0); +reg_write( DDR_REG_BASE +0x52fef*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x52ff0*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52ff1*4 +0x02000000,0xf164); +reg_write( DDR_REG_BASE +0x52ff2*4 +0x02000000,0xb2e0); +reg_write( DDR_REG_BASE +0x52ff3*4 +0x02000000,0x1a04); +reg_write( DDR_REG_BASE +0x52ff4*4 +0x02000000,0x45); +reg_write( DDR_REG_BASE +0x52ff5*4 +0x02000000,0xf020); +reg_write( DDR_REG_BASE +0x52ff6*4 +0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x52ff7*4 +0x02000000,0x32c0); +reg_write( DDR_REG_BASE +0x52ff8*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x52ff9*4 +0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x52ffa*4 +0x02000000,0xf753); +reg_write( DDR_REG_BASE +0x52ffb*4 +0x02000000,0x4381); +reg_write( DDR_REG_BASE +0x52ffc*4 +0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x52ffd*4 +0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x52ffe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52fff*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x53000*4 +0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x53001*4 +0x02000000,0x8); +reg_write( DDR_REG_BASE +0x53002*4 +0x02000000,0x7b45); +reg_write( DDR_REG_BASE +0x53003*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x53004*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x53005*4 +0x02000000,0x164); +reg_write( DDR_REG_BASE +0x53006*4 +0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x53007*4 +0x02000000,0x8d); +reg_write( DDR_REG_BASE +0x53008*4 +0x02000000,0x7444); +reg_write( DDR_REG_BASE +0x53009*4 +0x02000000,0x7b45); +reg_write( DDR_REG_BASE +0x5300a*4 +0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x5300b*4 +0x02000000,0x1b00); +reg_write( DDR_REG_BASE +0x5300c*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x5300d*4 +0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x5300e*4 +0x02000000,0xe0d); +reg_write( DDR_REG_BASE +0x5300f*4 +0x02000000,0x3010); +reg_write( DDR_REG_BASE +0x53010*4 +0x02000000,0xcd5); +reg_write( DDR_REG_BASE +0x53011*4 +0x02000000,0x9274); +reg_write( DDR_REG_BASE +0x53012*4 +0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x53013*4 +0x02000000,0xb782); +reg_write( DDR_REG_BASE +0x53014*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x53015*4 +0x02000000,0x993); +reg_write( DDR_REG_BASE +0x53016*4 +0x02000000,0x83a5); +reg_write( DDR_REG_BASE +0x53017*4 +0x02000000,0x222f); +reg_write( DDR_REG_BASE +0x53018*4 +0x02000000,0x2c7); +reg_write( DDR_REG_BASE +0x53019*4 +0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x5301a*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5301b*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5301c*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5301d*4 +0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x5301e*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5301f*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x53020*4 +0x02000000,0x30); +reg_write( DDR_REG_BASE +0x53021*4 +0x02000000,0x10b4); +reg_write( DDR_REG_BASE +0x53022*4 +0x02000000,0x501); +reg_write( DDR_REG_BASE +0x53023*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53024*4 +0x02000000,0x708f); +reg_write( DDR_REG_BASE +0x53025*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53026*4 +0x02000000,0x25); +reg_write( DDR_REG_BASE +0x53027*4 +0x02000000,0x90d); +reg_write( DDR_REG_BASE +0x53028*4 +0x02000000,0x171); +reg_write( DDR_REG_BASE +0x53029*4 +0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x5302a*4 +0x02000000,0xb0e1); +reg_write( DDR_REG_BASE +0x5302b*4 +0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x5302c*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5302d*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x5302e*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5302f*4 +0x02000000,0x58); +reg_write( DDR_REG_BASE +0x53030*4 +0x02000000,0xb021); +reg_write( DDR_REG_BASE +0x53031*4 +0x02000000,0xf6f); +reg_write( DDR_REG_BASE +0x53032*4 +0x02000000,0x1030); +reg_write( DDR_REG_BASE +0x53033*4 +0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x53034*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53035*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53036*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53037*4 +0x02000000,0x32); +reg_write( DDR_REG_BASE +0x53038*4 +0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x53039*4 +0x02000000,0x108d); +reg_write( DDR_REG_BASE +0x5303a*4 +0x02000000,0xb8e3); +reg_write( DDR_REG_BASE +0x5303b*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5303c*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5303d*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5303e*4 +0x02000000,0x7cf); +reg_write( DDR_REG_BASE +0x5303f*4 +0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x53040*4 +0x02000000,0x30a1); +reg_write( DDR_REG_BASE +0x53041*4 +0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x53042*4 +0x02000000,0x104e); +reg_write( DDR_REG_BASE +0x53043*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x53044*4 +0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x53045*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x53046*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53047*4 +0x02000000,0x2753); +reg_write( DDR_REG_BASE +0x53048*4 +0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x53049*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x5304a*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x5304b*4 +0x02000000,0xf848); +reg_write( DDR_REG_BASE +0x5304c*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x5304d*4 +0x02000000,0xf841); +reg_write( DDR_REG_BASE +0x5304e*4 +0x02000000,0xee07); +reg_write( DDR_REG_BASE +0x5304f*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x53050*4 +0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x53051*4 +0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x53052*4 +0x02000000,0xfaa); +reg_write( DDR_REG_BASE +0x53053*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x53054*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53055*4 +0x02000000,0xed08); +reg_write( DDR_REG_BASE +0x53056*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x53057*4 +0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x53058*4 +0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x53059*4 +0x02000000,0xf9e); +reg_write( DDR_REG_BASE +0x5305a*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x5305b*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5305c*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x5305d*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5305e*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5305f*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53060*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53061*4 +0x02000000,0x7cf); +reg_write( DDR_REG_BASE +0x53062*4 +0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x53063*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x53064*4 +0x02000000,0x9c3); +reg_write( DDR_REG_BASE +0x53065*4 +0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x53066*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53067*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53068*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x53069*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5306a*4 +0x02000000,0x58); +reg_write( DDR_REG_BASE +0x5306b*4 +0x02000000,0xd6f); +reg_write( DDR_REG_BASE +0x5306c*4 +0x02000000,0x1030); +reg_write( DDR_REG_BASE +0x5306d*4 +0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x5306e*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5306f*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53070*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53071*4 +0x02000000,0x65); +reg_write( DDR_REG_BASE +0x53072*4 +0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x53073*4 +0x02000000,0x108e); +reg_write( DDR_REG_BASE +0x53074*4 +0x02000000,0xb8e3); +reg_write( DDR_REG_BASE +0x53075*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53076*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53077*4 +0x02000000,0x7cf); +reg_write( DDR_REG_BASE +0x53078*4 +0x02000000,0x8802); +reg_write( DDR_REG_BASE +0x53079*4 +0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x5307a*4 +0x02000000,0x30a1); +reg_write( DDR_REG_BASE +0x5307b*4 +0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x5307c*4 +0x02000000,0x104f); +reg_write( DDR_REG_BASE +0x5307d*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5307e*4 +0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x5307f*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x53080*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53081*4 +0x02000000,0x2553); +reg_write( DDR_REG_BASE +0x53082*4 +0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x53083*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x53084*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53085*4 +0x02000000,0xf82b); +reg_write( DDR_REG_BASE +0x53086*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x53087*4 +0x02000000,0xf824); +reg_write( DDR_REG_BASE +0x53088*4 +0x02000000,0xef07); +reg_write( DDR_REG_BASE +0x53089*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x5308a*4 +0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x5308b*4 +0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x5308c*4 +0x02000000,0xf36); +reg_write( DDR_REG_BASE +0x5308d*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x5308e*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5308f*4 +0x02000000,0xee08); +reg_write( DDR_REG_BASE +0x53090*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x53091*4 +0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x53092*4 +0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x53093*4 +0x02000000,0xf2a); +reg_write( DDR_REG_BASE +0x53094*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x53095*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x53096*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x53097*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x53098*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x53099*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5309a*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5309b*4 +0x02000000,0x7cf); +reg_write( DDR_REG_BASE +0x5309c*4 +0x02000000,0x8823); +reg_write( DDR_REG_BASE +0x5309d*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x5309e*4 +0x02000000,0x9c3); +reg_write( DDR_REG_BASE +0x5309f*4 +0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x530a0*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x530a1*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x530a2*4 +0x02000000,0x708e); +reg_write( DDR_REG_BASE +0x530a3*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x530a4*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x530a5*4 +0x02000000,0xfaa); +reg_write( DDR_REG_BASE +0x530a6*4 +0x02000000,0xfdcf); +reg_write( DDR_REG_BASE +0x530a7*4 +0x02000000,0xfb2); +reg_write( DDR_REG_BASE +0x530a8*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x530a9*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x530aa*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x530ab*4 +0x02000000,0xcfe); +reg_write( DDR_REG_BASE +0x530ac*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x530ad*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x530ae*4 +0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x530af*4 +0x02000000,0x1f8c); +reg_write( DDR_REG_BASE +0x530b0*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x530b1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530b2*4 +0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x530b3*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x530b4*4 +0x02000000,0x1ea); +reg_write( DDR_REG_BASE +0x530b5*4 +0x02000000,0x9300); +reg_write( DDR_REG_BASE +0x530b6*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x530b7*4 +0x02000000,0x9012); +reg_write( DDR_REG_BASE +0x530b8*4 +0x02000000,0x402); +reg_write( DDR_REG_BASE +0x530b9*4 +0x02000000,0x2405); +reg_write( DDR_REG_BASE +0x530ba*4 +0x02000000,0x1342); +reg_write( DDR_REG_BASE +0x530bb*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x530bc*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x530bd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530be*4 +0x02000000,0x3f00); +reg_write( DDR_REG_BASE +0x530bf*4 +0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x530c0*4 +0x02000000,0x6d44); +reg_write( DDR_REG_BASE +0x530c1*4 +0x02000000,0x7a85); +reg_write( DDR_REG_BASE +0x530c2*4 +0x02000000,0x2196); +reg_write( DDR_REG_BASE +0x530c3*4 +0x02000000,0x6); +reg_write( DDR_REG_BASE +0x530c4*4 +0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x530c5*4 +0x02000000,0x9321); +reg_write( DDR_REG_BASE +0x530c6*4 +0x02000000,0x6d02); +reg_write( DDR_REG_BASE +0x530c7*4 +0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x530c8*4 +0x02000000,0xb9c5); +reg_write( DDR_REG_BASE +0x530c9*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x530ca*4 +0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x530cb*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x530cc*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x530cd*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x530ce*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x530cf*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x530d0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530d1*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x530d2*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x530d3*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x530d4*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x530d5*4 +0x02000000,0x154); +reg_write( DDR_REG_BASE +0x530d6*4 +0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x530d7*4 +0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x530d8*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x530d9*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x530da*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x530db*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x530dc*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x530dd*4 +0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x530de*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x530df*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x530e0*4 +0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x530e1*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x530e2*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x530e3*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x530e4*4 +0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x530e5*4 +0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x530e6*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x530e7*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x530e8*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x530e9*4 +0x02000000,0x6e1); +reg_write( DDR_REG_BASE +0x530ea*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x530eb*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x530ec*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x530ed*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x530ee*4 +0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x530ef*4 +0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x530f0*4 +0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x530f1*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x530f2*4 +0x02000000,0x8f2); +reg_write( DDR_REG_BASE +0x530f3*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x530f4*4 +0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x530f5*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x530f6*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x530f7*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x530f8*4 +0x02000000,0x6e1); +reg_write( DDR_REG_BASE +0x530f9*4 +0x02000000,0xd910); +reg_write( DDR_REG_BASE +0x530fa*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x530fb*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x530fc*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x530fd*4 +0x02000000,0xdb0c); +reg_write( DDR_REG_BASE +0x530fe*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x530ff*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53100*4 +0x02000000,0x8d6); +reg_write( DDR_REG_BASE +0x53101*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53102*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53103*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53104*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x53105*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53106*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x53107*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x53108*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x53109*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5310a*4 +0x02000000,0x8c2); +reg_write( DDR_REG_BASE +0x5310b*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x5310c*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5310d*4 +0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x5310e*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x5310f*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x53110*4 +0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x53111*4 +0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x53112*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x53113*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53114*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53115*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53116*4 +0x02000000,0x736c); +reg_write( DDR_REG_BASE +0x53117*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x53118*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x53119*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5311a*4 +0x02000000,0x8a2); +reg_write( DDR_REG_BASE +0x5311b*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x5311c*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5311d*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x5311e*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5311f*4 +0x02000000,0x6e1); +reg_write( DDR_REG_BASE +0x53120*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x53121*4 +0x02000000,0x825); +reg_write( DDR_REG_BASE +0x53122*4 +0x02000000,0xb4); +reg_write( DDR_REG_BASE +0x53123*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53124*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x53125*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x53126*4 +0x02000000,0xb862); +reg_write( DDR_REG_BASE +0x53127*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x53128*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x53129*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5312a*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5312b*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5312c*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5312d*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5312e*4 +0x02000000,0x87a); +reg_write( DDR_REG_BASE +0x5312f*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53130*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53131*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x53132*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x53133*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53134*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53135*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53136*4 +0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x53137*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x53138*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53139*4 +0x02000000,0x866); +reg_write( DDR_REG_BASE +0x5313a*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x5313b*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5313c*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x5313d*4 +0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x5313e*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5313f*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x53140*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53141*4 +0x02000000,0xdb0c); +reg_write( DDR_REG_BASE +0x53142*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x53143*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53144*4 +0x02000000,0x84e); +reg_write( DDR_REG_BASE +0x53145*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53146*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53147*4 +0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x53148*4 +0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x53149*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5314a*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x5314b*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5314c*4 +0x02000000,0x110); +reg_write( DDR_REG_BASE +0x5314d*4 +0x02000000,0x9200); +reg_write( DDR_REG_BASE +0x5314e*4 +0x02000000,0x204f); +reg_write( DDR_REG_BASE +0x5314f*4 +0x02000000,0x101); +reg_write( DDR_REG_BASE +0x53150*4 +0x02000000,0xb8a4); +reg_write( DDR_REG_BASE +0x53151*4 +0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x53152*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x53153*4 +0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x53154*4 +0x02000000,0xc0e6); +reg_write( DDR_REG_BASE +0x53155*4 +0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x53156*4 +0x02000000,0x483); +reg_write( DDR_REG_BASE +0x53157*4 +0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x53158*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53159*4 +0x02000000,0x6e2); +reg_write( DDR_REG_BASE +0x5315a*4 +0x02000000,0x638d); +reg_write( DDR_REG_BASE +0x5315b*4 +0x02000000,0x6479); +reg_write( DDR_REG_BASE +0x5315c*4 +0x02000000,0x89c1); +reg_write( DDR_REG_BASE +0x5315d*4 +0x02000000,0x7d04); +reg_write( DDR_REG_BASE +0x5315e*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5315f*4 +0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x53160*4 +0x02000000,0x629a); +reg_write( DDR_REG_BASE +0x53161*4 +0x02000000,0x8ae3); +reg_write( DDR_REG_BASE +0x53162*4 +0x02000000,0x809); +reg_write( DDR_REG_BASE +0x53163*4 +0x02000000,0x3ce); +reg_write( DDR_REG_BASE +0x53164*4 +0x02000000,0x8a42); +reg_write( DDR_REG_BASE +0x53165*4 +0x02000000,0x7d45); +reg_write( DDR_REG_BASE +0x53166*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x53167*4 +0x02000000,0x9f5); +reg_write( DDR_REG_BASE +0x53168*4 +0x02000000,0x83a4); +reg_write( DDR_REG_BASE +0x53169*4 +0x02000000,0x2314); +reg_write( DDR_REG_BASE +0x5316a*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x5316b*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x5316c*4 +0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x5316d*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5316e*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5316f*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53170*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53171*4 +0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x53172*4 +0x02000000,0x3d09); +reg_write( DDR_REG_BASE +0x53173*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53174*4 +0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x53175*4 +0x02000000,0x243); +reg_write( DDR_REG_BASE +0x53176*4 +0x02000000,0x8820); +reg_write( DDR_REG_BASE +0x53177*4 +0x02000000,0x1054); +reg_write( DDR_REG_BASE +0x53178*4 +0x02000000,0x83); +reg_write( DDR_REG_BASE +0x53179*4 +0x02000000,0x1021); +reg_write( DDR_REG_BASE +0x5317a*4 +0x02000000,0x8d); +reg_write( DDR_REG_BASE +0x5317b*4 +0x02000000,0x10fd); +reg_write( DDR_REG_BASE +0x5317c*4 +0x02000000,0x808e); +reg_write( DDR_REG_BASE +0x5317d*4 +0x02000000,0x1209); +reg_write( DDR_REG_BASE +0x5317e*4 +0x02000000,0x308b); +reg_write( DDR_REG_BASE +0x5317f*4 +0x02000000,0x1208); +reg_write( DDR_REG_BASE +0x53180*4 +0x02000000,0x308f); +reg_write( DDR_REG_BASE +0x53181*4 +0x02000000,0xc149); +reg_write( DDR_REG_BASE +0x53182*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x53183*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x53184*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53185*4 +0x02000000,0x10c); +reg_write( DDR_REG_BASE +0x53186*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53187*4 +0x02000000,0x8ce); +reg_write( DDR_REG_BASE +0x53188*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x53189*4 +0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x5318a*4 +0x02000000,0xc096); +reg_write( DDR_REG_BASE +0x5318b*4 +0x02000000,0x8c6); +reg_write( DDR_REG_BASE +0x5318c*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5318d*4 +0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x5318e*4 +0x02000000,0xbee2); +reg_write( DDR_REG_BASE +0x5318f*4 +0x02000000,0x6f01); +reg_write( DDR_REG_BASE +0x53190*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x53191*4 +0x02000000,0x20df); +reg_write( DDR_REG_BASE +0x53192*4 +0x02000000,0x3e1); +reg_write( DDR_REG_BASE +0x53193*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x53194*4 +0x02000000,0x7ba5); +reg_write( DDR_REG_BASE +0x53195*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x53196*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53197*4 +0x02000000,0x43d9); +reg_write( DDR_REG_BASE +0x53198*4 +0x02000000,0xc34d); +reg_write( DDR_REG_BASE +0x53199*4 +0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x5319a*4 +0x02000000,0x141); +reg_write( DDR_REG_BASE +0x5319b*4 +0x02000000,0xb882); +reg_write( DDR_REG_BASE +0x5319c*4 +0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x5319d*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5319e*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x5319f*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x531a0*4 +0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x531a1*4 +0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x531a2*4 +0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x531a3*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x531a4*4 +0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x531a5*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x531a6*4 +0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x531a7*4 +0x02000000,0x180); +reg_write( DDR_REG_BASE +0x531a8*4 +0x02000000,0xc04e); +reg_write( DDR_REG_BASE +0x531a9*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x531aa*4 +0x02000000,0xb869); +reg_write( DDR_REG_BASE +0x531ab*4 +0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x531ac*4 +0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x531ad*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x531ae*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x531af*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x531b0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531b1*4 +0x02000000,0xc04f); +reg_write( DDR_REG_BASE +0x531b2*4 +0x02000000,0x2378); +reg_write( DDR_REG_BASE +0x531b3*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x531b4*4 +0x02000000,0x28d); +reg_write( DDR_REG_BASE +0x531b5*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x531b6*4 +0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x531b7*4 +0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x531b8*4 +0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x531b9*4 +0x02000000,0x17c0); +reg_write( DDR_REG_BASE +0x531ba*4 +0x02000000,0xc10a); +reg_write( DDR_REG_BASE +0x531bb*4 +0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x531bc*4 +0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x531bd*4 +0x02000000,0x801); +reg_write( DDR_REG_BASE +0x531be*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x531bf*4 +0x02000000,0x7b7b); +reg_write( DDR_REG_BASE +0x531c0*4 +0x02000000,0xaea); +reg_write( DDR_REG_BASE +0x531c1*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x531c2*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x531c3*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x531c4*4 +0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x531c5*4 +0x02000000,0x7b0b); +reg_write( DDR_REG_BASE +0x531c6*4 +0x02000000,0x266); +reg_write( DDR_REG_BASE +0x531c7*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x531c8*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x531c9*4 +0x02000000,0xb880); +reg_write( DDR_REG_BASE +0x531ca*4 +0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x531cb*4 +0x02000000,0x141); +reg_write( DDR_REG_BASE +0x531cc*4 +0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x531cd*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x531ce*4 +0x02000000,0xc050); +reg_write( DDR_REG_BASE +0x531cf*4 +0x02000000,0x215); +reg_write( DDR_REG_BASE +0x531d0*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x531d1*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x531d2*4 +0x02000000,0xc110); +reg_write( DDR_REG_BASE +0x531d3*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x531d4*4 +0x02000000,0xe5e); +reg_write( DDR_REG_BASE +0x531d5*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x531d6*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x531d7*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x531d8*4 +0x02000000,0x1f6); +reg_write( DDR_REG_BASE +0x531d9*4 +0x02000000,0x21); +reg_write( DDR_REG_BASE +0x531da*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x531db*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x531dc*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x531dd*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x531de*4 +0x02000000,0xa8c1); +reg_write( DDR_REG_BASE +0x531df*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x531e0*4 +0x02000000,0xb863); +reg_write( DDR_REG_BASE +0x531e1*4 +0x02000000,0x7214); +reg_write( DDR_REG_BASE +0x531e2*4 +0x02000000,0xa28); +reg_write( DDR_REG_BASE +0x531e3*4 +0x02000000,0xfd45); +reg_write( DDR_REG_BASE +0x531e4*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x531e5*4 +0x02000000,0xf79a); +reg_write( DDR_REG_BASE +0x531e6*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x531e7*4 +0x02000000,0x831); +reg_write( DDR_REG_BASE +0x531e8*4 +0x02000000,0x1b1); +reg_write( DDR_REG_BASE +0x531e9*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x531ea*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x531eb*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x531ec*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x531ed*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x531ee*4 +0x02000000,0x265a); +reg_write( DDR_REG_BASE +0x531ef*4 +0x02000000,0x1641); +reg_write( DDR_REG_BASE +0x531f0*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x531f1*4 +0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x531f2*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x531f3*4 +0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x531f4*4 +0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x531f5*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x531f6*4 +0x02000000,0x67f); +reg_write( DDR_REG_BASE +0x531f7*4 +0x02000000,0x7dbd); +reg_write( DDR_REG_BASE +0x531f8*4 +0x02000000,0x7dbd); +reg_write( DDR_REG_BASE +0x531f9*4 +0x02000000,0x7dbd); +reg_write( DDR_REG_BASE +0x531fa*4 +0x02000000,0x7dbd); +reg_write( DDR_REG_BASE +0x531fb*4 +0x02000000,0x7dbd); +reg_write( DDR_REG_BASE +0x531fc*4 +0x02000000,0x7dbd); +reg_write( DDR_REG_BASE +0x531fd*4 +0x02000000,0x7dbd); +reg_write( DDR_REG_BASE +0x531fe*4 +0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x531ff*4 +0x02000000,0x3e00); +reg_write( DDR_REG_BASE +0x53200*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53201*4 +0x02000000,0xfda); +reg_write( DDR_REG_BASE +0x53202*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x53203*4 +0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x53204*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53205*4 +0x02000000,0x7614); +reg_write( DDR_REG_BASE +0x53206*4 +0x02000000,0x164); +reg_write( DDR_REG_BASE +0x53207*4 +0x02000000,0xd); +reg_write( DDR_REG_BASE +0x53208*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53209*4 +0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x5320a*4 +0x02000000,0x2025); +reg_write( DDR_REG_BASE +0x5320b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5320c*4 +0x02000000,0xf025); +reg_write( DDR_REG_BASE +0x5320d*4 +0x02000000,0xf02b); +reg_write( DDR_REG_BASE +0x5320e*4 +0x02000000,0xf02f); +reg_write( DDR_REG_BASE +0x5320f*4 +0x02000000,0xf033); +reg_write( DDR_REG_BASE +0x53210*4 +0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x53211*4 +0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x53212*4 +0x02000000,0xf034); +reg_write( DDR_REG_BASE +0x53213*4 +0x02000000,0xc096); +reg_write( DDR_REG_BASE +0x53214*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x53215*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x53216*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x53217*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53218*4 +0x02000000,0x10c); +reg_write( DDR_REG_BASE +0x53219*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5321a*4 +0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x5321b*4 +0x02000000,0x3e00); +reg_write( DDR_REG_BASE +0x5321c*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5321d*4 +0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x5321e*4 +0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x5321f*4 +0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x53220*4 +0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x53221*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x53222*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53223*4 +0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x53224*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53225*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53226*4 +0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x53227*4 +0x02000000,0x7514); +reg_write( DDR_REG_BASE +0x53228*4 +0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x53229*4 +0x02000000,0x31a1); +reg_write( DDR_REG_BASE +0x5322a*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x5322b*4 +0x02000000,0xd7e); +reg_write( DDR_REG_BASE +0x5322c*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5322d*4 +0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x5322e*4 +0x02000000,0xdf8c); +reg_write( DDR_REG_BASE +0x5322f*4 +0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x53230*4 +0x02000000,0xf088); +reg_write( DDR_REG_BASE +0x53231*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53232*4 +0x02000000,0xe0e); +reg_write( DDR_REG_BASE +0x53233*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x53234*4 +0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x53235*4 +0x02000000,0x3e01); +reg_write( DDR_REG_BASE +0x53236*4 +0x02000000,0xf09d); +reg_write( DDR_REG_BASE +0x53237*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53238*4 +0x02000000,0xf36); +reg_write( DDR_REG_BASE +0x53239*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5323a*4 +0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x5323b*4 +0x02000000,0x3e01); +reg_write( DDR_REG_BASE +0x5323c*4 +0x02000000,0xf097); +reg_write( DDR_REG_BASE +0x5323d*4 +0x02000000,0xac6); +reg_write( DDR_REG_BASE +0x5323e*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5323f*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53240*4 +0x02000000,0xf093); +reg_write( DDR_REG_BASE +0x53241*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53242*4 +0x02000000,0xf5e); +reg_write( DDR_REG_BASE +0x53243*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x53244*4 +0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x53245*4 +0x02000000,0xf08f); +reg_write( DDR_REG_BASE +0x53246*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53247*4 +0x02000000,0x76c4); +reg_write( DDR_REG_BASE +0x53248*4 +0x02000000,0x900f); +reg_write( DDR_REG_BASE +0x53249*4 +0x02000000,0xe022); +reg_write( DDR_REG_BASE +0x5324a*4 +0x02000000,0xc096); +reg_write( DDR_REG_BASE +0x5324b*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5324c*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x5324d*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x5324e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5324f*4 +0x02000000,0x10c); +reg_write( DDR_REG_BASE +0x53250*4 +0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x53251*4 +0x02000000,0xc308); +reg_write( DDR_REG_BASE +0x53252*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x53253*4 +0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x53254*4 +0x02000000,0x3e00); +reg_write( DDR_REG_BASE +0x53255*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x53256*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53257*4 +0x02000000,0xd96); +reg_write( DDR_REG_BASE +0x53258*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x53259*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5325a*4 +0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x5325b*4 +0x02000000,0xdcf); +reg_write( DDR_REG_BASE +0x5325c*4 +0x02000000,0x1030); +reg_write( DDR_REG_BASE +0x5325d*4 +0x02000000,0xdfc0); +reg_write( DDR_REG_BASE +0x5325e*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5325f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53260*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x53261*4 +0x02000000,0x8825); +reg_write( DDR_REG_BASE +0x53262*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53263*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53264*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x53265*4 +0x02000000,0x8844); +reg_write( DDR_REG_BASE +0x53266*4 +0x02000000,0x225f); +reg_write( DDR_REG_BASE +0x53267*4 +0x02000000,0x243); +reg_write( DDR_REG_BASE +0x53268*4 +0x02000000,0xf02d); +reg_write( DDR_REG_BASE +0x53269*4 +0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x5326a*4 +0x02000000,0x30c0); +reg_write( DDR_REG_BASE +0x5326b*4 +0x02000000,0xf025); +reg_write( DDR_REG_BASE +0x5326c*4 +0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x5326d*4 +0x02000000,0x78d); +reg_write( DDR_REG_BASE +0x5326e*4 +0x02000000,0xdf1b); +reg_write( DDR_REG_BASE +0x5326f*4 +0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x53270*4 +0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x53271*4 +0x02000000,0x78bc); +reg_write( DDR_REG_BASE +0x53272*4 +0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x53273*4 +0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x53274*4 +0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x53275*4 +0x02000000,0xbf61); +reg_write( DDR_REG_BASE +0x53276*4 +0x02000000,0xfff); +reg_write( DDR_REG_BASE +0x53277*4 +0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x53278*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x53279*4 +0x02000000,0x651f); +reg_write( DDR_REG_BASE +0x5327a*4 +0x02000000,0xbfc4); +reg_write( DDR_REG_BASE +0x5327b*4 +0x02000000,0x7f02); +reg_write( DDR_REG_BASE +0x5327c*4 +0x02000000,0x2d44); +reg_write( DDR_REG_BASE +0x5327d*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x5327e*4 +0x02000000,0x6ca1); +reg_write( DDR_REG_BASE +0x5327f*4 +0x02000000,0x249a); +reg_write( DDR_REG_BASE +0x53280*4 +0x02000000,0x1008); +reg_write( DDR_REG_BASE +0x53281*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x53282*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x53283*4 +0x02000000,0x7f05); +reg_write( DDR_REG_BASE +0x53284*4 +0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x53285*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53286*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53287*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x53288*4 +0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x53289*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5328a*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5328b*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x5328c*4 +0x02000000,0x64); +reg_write( DDR_REG_BASE +0x5328d*4 +0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x5328e*4 +0x02000000,0x44a9); +reg_write( DDR_REG_BASE +0x5328f*4 +0x02000000,0xcbd); +reg_write( DDR_REG_BASE +0x53290*4 +0x02000000,0x9234); +reg_write( DDR_REG_BASE +0x53291*4 +0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x53292*4 +0x02000000,0x3e00); +reg_write( DDR_REG_BASE +0x53293*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x53294*4 +0x02000000,0xe309); +reg_write( DDR_REG_BASE +0x53295*4 +0x02000000,0x9ab); +reg_write( DDR_REG_BASE +0x53296*4 +0x02000000,0x80a5); +reg_write( DDR_REG_BASE +0x53297*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x53298*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53299*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x5329a*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5329b*4 +0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x5329c*4 +0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x5329d*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5329e*4 +0x02000000,0xae2); +reg_write( DDR_REG_BASE +0x5329f*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x532a0*4 +0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x532a1*4 +0x02000000,0xc096); +reg_write( DDR_REG_BASE +0x532a2*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x532a3*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x532a4*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x532a5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532a6*4 +0x02000000,0x10c); +reg_write( DDR_REG_BASE +0x532a7*4 +0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x532a8*4 +0x02000000,0xc308); +reg_write( DDR_REG_BASE +0x532a9*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x532aa*4 +0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x532ab*4 +0x02000000,0x3e00); +reg_write( DDR_REG_BASE +0x532ac*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x532ad*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x532ae*4 +0x02000000,0xce6); +reg_write( DDR_REG_BASE +0x532af*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x532b0*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x532b1*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x532b2*4 +0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x532b3*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x532b4*4 +0x02000000,0xab6); +reg_write( DDR_REG_BASE +0x532b5*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x532b6*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x532b7*4 +0x02000000,0xdfc0); +reg_write( DDR_REG_BASE +0x532b8*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x532b9*4 +0x02000000,0x815); +reg_write( DDR_REG_BASE +0x532ba*4 +0x02000000,0x370); +reg_write( DDR_REG_BASE +0x532bb*4 +0x02000000,0x456b); +reg_write( DDR_REG_BASE +0x532bc*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x532bd*4 +0x02000000,0x80d); +reg_write( DDR_REG_BASE +0x532be*4 +0x02000000,0x1b0); +reg_write( DDR_REG_BASE +0x532bf*4 +0x02000000,0x456b); +reg_write( DDR_REG_BASE +0x532c0*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x532c1*4 +0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x532c2*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x532c3*4 +0x02000000,0xfea); +reg_write( DDR_REG_BASE +0x532c4*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x532c5*4 +0x02000000,0xc191); +reg_write( DDR_REG_BASE +0x532c6*4 +0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x532c7*4 +0x02000000,0xed0d); +reg_write( DDR_REG_BASE +0x532c8*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x532c9*4 +0x02000000,0xc20e); +reg_write( DDR_REG_BASE +0x532ca*4 +0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x532cb*4 +0x02000000,0x3e01); +reg_write( DDR_REG_BASE +0x532cc*4 +0x02000000,0x671f); +reg_write( DDR_REG_BASE +0x532cd*4 +0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x532ce*4 +0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x532cf*4 +0x02000000,0x84a); +reg_write( DDR_REG_BASE +0x532d0*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x532d1*4 +0x02000000,0x78e5); +reg_write( DDR_REG_BASE +0x532d2*4 +0x02000000,0x43b9); +reg_write( DDR_REG_BASE +0x532d3*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x532d4*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x532d5*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x532d6*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x532d7*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x532d8*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x532d9*4 +0x02000000,0x7002); +reg_write( DDR_REG_BASE +0x532da*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x532db*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x532dc*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x532dd*4 +0x02000000,0x7114); +reg_write( DDR_REG_BASE +0x532de*4 +0x02000000,0x5e8); +reg_write( DDR_REG_BASE +0x532df*4 +0x02000000,0xffee); +reg_write( DDR_REG_BASE +0x532e0*4 +0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x532e1*4 +0x02000000,0xd56); +reg_write( DDR_REG_BASE +0x532e2*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x532e3*4 +0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x532e4*4 +0x02000000,0xca09); +reg_write( DDR_REG_BASE +0x532e5*4 +0x02000000,0xe895); +reg_write( DDR_REG_BASE +0x532e6*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x532e7*4 +0x02000000,0x811); +reg_write( DDR_REG_BASE +0x532e8*4 +0x02000000,0xf1); +reg_write( DDR_REG_BASE +0x532e9*4 +0x02000000,0x79cf); +reg_write( DDR_REG_BASE +0x532ea*4 +0x02000000,0xcba); +reg_write( DDR_REG_BASE +0x532eb*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x532ec*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x532ed*4 +0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x532ee*4 +0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x532ef*4 +0x02000000,0x817); +reg_write( DDR_REG_BASE +0x532f0*4 +0x02000000,0x134); +reg_write( DDR_REG_BASE +0x532f1*4 +0x02000000,0x7bcf); +reg_write( DDR_REG_BASE +0x532f2*4 +0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x532f3*4 +0x02000000,0xc109); +reg_write( DDR_REG_BASE +0x532f4*4 +0x02000000,0xc207); +reg_write( DDR_REG_BASE +0x532f5*4 +0x02000000,0xbf2); +reg_write( DDR_REG_BASE +0x532f6*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x532f7*4 +0x02000000,0x2052); +reg_write( DDR_REG_BASE +0x532f8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532f9*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x532fa*4 +0x02000000,0x72d5); +reg_write( DDR_REG_BASE +0x532fb*4 +0x02000000,0x57a); +reg_write( DDR_REG_BASE +0x532fc*4 +0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x532fd*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x532fe*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x532ff*4 +0x02000000,0x819); +reg_write( DDR_REG_BASE +0x53300*4 +0x02000000,0xd1); +reg_write( DDR_REG_BASE +0x53301*4 +0x02000000,0xca09); +reg_write( DDR_REG_BASE +0x53302*4 +0x02000000,0xe888); +reg_write( DDR_REG_BASE +0x53303*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53304*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53305*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53306*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53307*4 +0x02000000,0xb8e5); +reg_write( DDR_REG_BASE +0x53308*4 +0x02000000,0xcb8); +reg_write( DDR_REG_BASE +0x53309*4 +0x02000000,0xfd42); +reg_write( DDR_REG_BASE +0x5330a*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5330b*4 +0x02000000,0x7003); +reg_write( DDR_REG_BASE +0x5330c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5330d*4 +0x02000000,0xf); +reg_write( DDR_REG_BASE +0x5330e*4 +0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x5330f*4 +0x02000000,0x3d09); +reg_write( DDR_REG_BASE +0x53310*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x53311*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x53312*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53313*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x53314*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x53315*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53316*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53317*4 +0x02000000,0xc1b1); +reg_write( DDR_REG_BASE +0x53318*4 +0x02000000,0xc050); +reg_write( DDR_REG_BASE +0x53319*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5331a*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5331b*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5331c*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5331d*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x5331e*4 +0x02000000,0xe96); +reg_write( DDR_REG_BASE +0x5331f*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x53320*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x53321*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53322*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53323*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x53324*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x53325*4 +0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x53326*4 +0x02000000,0xb72); +reg_write( DDR_REG_BASE +0x53327*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x53328*4 +0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x53329*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x5332a*4 +0x02000000,0xfca); +reg_write( DDR_REG_BASE +0x5332b*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x5332c*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x5332d*4 +0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x5332e*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5332f*4 +0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x53330*4 +0x02000000,0x1f22); +reg_write( DDR_REG_BASE +0x53331*4 +0x02000000,0x1015); +reg_write( DDR_REG_BASE +0x53332*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53333*4 +0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x53334*4 +0x02000000,0x1fa7); +reg_write( DDR_REG_BASE +0x53335*4 +0x02000000,0x101c); +reg_write( DDR_REG_BASE +0x53336*4 +0x02000000,0x1fa8); +reg_write( DDR_REG_BASE +0x53337*4 +0x02000000,0x101c); +reg_write( DDR_REG_BASE +0x53338*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x53339*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x5333a*4 +0x02000000,0xb700); +reg_write( DDR_REG_BASE +0x5333b*4 +0x02000000,0x1ffe); +reg_write( DDR_REG_BASE +0x5333c*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5333d*4 +0x02000000,0xb705); +reg_write( DDR_REG_BASE +0x5333e*4 +0x02000000,0x922); +reg_write( DDR_REG_BASE +0x5333f*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x53340*4 +0x02000000,0x1ffc); +reg_write( DDR_REG_BASE +0x53341*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x53342*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x53343*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53344*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x53345*4 +0x02000000,0x8e04); +reg_write( DDR_REG_BASE +0x53346*4 +0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x53347*4 +0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x53348*4 +0x02000000,0x243); +reg_write( DDR_REG_BASE +0x53349*4 +0x02000000,0x10fd); +reg_write( DDR_REG_BASE +0x5334a*4 +0x02000000,0x809e); +reg_write( DDR_REG_BASE +0x5334b*4 +0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x5334c*4 +0x02000000,0x3100); +reg_write( DDR_REG_BASE +0x5334d*4 +0x02000000,0x780d); +reg_write( DDR_REG_BASE +0x5334e*4 +0x02000000,0x791c); +reg_write( DDR_REG_BASE +0x5334f*4 +0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x53350*4 +0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x53351*4 +0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x53352*4 +0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x53353*4 +0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x53354*4 +0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x53355*4 +0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x53356*4 +0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x53357*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x53358*4 +0x02000000,0x8e05); +reg_write( DDR_REG_BASE +0x53359*4 +0x02000000,0xc04d); +reg_write( DDR_REG_BASE +0x5335a*4 +0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x5335b*4 +0x02000000,0xc04e); +reg_write( DDR_REG_BASE +0x5335c*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x5335d*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x5335e*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5335f*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x53360*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53361*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53362*4 +0x02000000,0x8e03); +reg_write( DDR_REG_BASE +0x53363*4 +0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x53364*4 +0x02000000,0x8e02); +reg_write( DDR_REG_BASE +0x53365*4 +0x02000000,0x25f); +reg_write( DDR_REG_BASE +0x53366*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x53367*4 +0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x53368*4 +0x02000000,0xe13); +reg_write( DDR_REG_BASE +0x53369*4 +0x02000000,0x315e); +reg_write( DDR_REG_BASE +0x5336a*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5336b*4 +0x02000000,0xae05); +reg_write( DDR_REG_BASE +0x5336c*4 +0x02000000,0xae04); +reg_write( DDR_REG_BASE +0x5336d*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5336e*4 +0x02000000,0xae02); +reg_write( DDR_REG_BASE +0x5336f*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x53370*4 +0x02000000,0xae03); +reg_write( DDR_REG_BASE +0x53371*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x53372*4 +0x02000000,0x770c); +reg_write( DDR_REG_BASE +0x53373*4 +0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x53374*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53375*4 +0x02000000,0xf0d0); +reg_write( DDR_REG_BASE +0x53376*4 +0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x53377*4 +0x02000000,0x37c1); +reg_write( DDR_REG_BASE +0x53378*4 +0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x53379*4 +0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x5337a*4 +0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x5337b*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x5337c*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5337d*4 +0x02000000,0x1e01); +reg_write( DDR_REG_BASE +0x5337e*4 +0x02000000,0x16c2); +reg_write( DDR_REG_BASE +0x5337f*4 +0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x53380*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x53381*4 +0x02000000,0x200f); +reg_write( DDR_REG_BASE +0x53382*4 +0x02000000,0x6c2); +reg_write( DDR_REG_BASE +0x53383*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x53384*4 +0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x53385*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53386*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x53387*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53388*4 +0x02000000,0x58); +reg_write( DDR_REG_BASE +0x53389*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x5338a*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5338b*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x5338c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5338d*4 +0x02000000,0x25); +reg_write( DDR_REG_BASE +0x5338e*4 +0x02000000,0x784f); +reg_write( DDR_REG_BASE +0x5338f*4 +0x02000000,0x790b); +reg_write( DDR_REG_BASE +0x53390*4 +0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x53391*4 +0x02000000,0xf2b3); +reg_write( DDR_REG_BASE +0x53392*4 +0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x53393*4 +0x02000000,0x6c7); +reg_write( DDR_REG_BASE +0x53394*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53395*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53396*4 +0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x53397*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x53398*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x53399*4 +0x02000000,0x8ee); +reg_write( DDR_REG_BASE +0x5339a*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x5339b*4 +0x02000000,0xc04f); +reg_write( DDR_REG_BASE +0x5339c*4 +0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x5339d*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5339e*4 +0x02000000,0xd1e); +reg_write( DDR_REG_BASE +0x5339f*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x533a0*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x533a1*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x533a2*4 +0x02000000,0xb52); +reg_write( DDR_REG_BASE +0x533a3*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x533a4*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x533a5*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x533a6*4 +0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x533a7*4 +0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x533a8*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x533a9*4 +0x02000000,0xe59f); +reg_write( DDR_REG_BASE +0x533aa*4 +0x02000000,0x10c); +reg_write( DDR_REG_BASE +0x533ab*4 +0x02000000,0x9); +reg_write( DDR_REG_BASE +0x533ac*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x533ad*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x533ae*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x533af*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x533b0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533b1*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x533b2*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x533b3*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x533b4*4 +0x02000000,0xe040); +reg_write( DDR_REG_BASE +0x533b5*4 +0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x533b6*4 +0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x533b7*4 +0x02000000,0x243); +reg_write( DDR_REG_BASE +0x533b8*4 +0x02000000,0x10fd); +reg_write( DDR_REG_BASE +0x533b9*4 +0x02000000,0x8080); +reg_write( DDR_REG_BASE +0x533ba*4 +0x02000000,0x82b); +reg_write( DDR_REG_BASE +0x533bb*4 +0x02000000,0x15f); +reg_write( DDR_REG_BASE +0x533bc*4 +0x02000000,0x8e25); +reg_write( DDR_REG_BASE +0x533bd*4 +0x02000000,0x8e44); +reg_write( DDR_REG_BASE +0x533be*4 +0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x533bf*4 +0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x533c0*4 +0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x533c1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533c2*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x533c3*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x533c4*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x533c5*4 +0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x533c6*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x533c7*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x533c8*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x533c9*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x533ca*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x533cb*4 +0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x533cc*4 +0x02000000,0x9e7); +reg_write( DDR_REG_BASE +0x533cd*4 +0x02000000,0x8085); +reg_write( DDR_REG_BASE +0x533ce*4 +0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x533cf*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x533d0*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x533d1*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x533d2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533d3*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x533d4*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x533d5*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x533d6*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x533d7*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x533d8*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x533d9*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x533da*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x533db*4 +0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x533dc*4 +0x02000000,0x8ce); +reg_write( DDR_REG_BASE +0x533dd*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x533de*4 +0x02000000,0xd814); +reg_write( DDR_REG_BASE +0x533df*4 +0x02000000,0xa9e); +reg_write( DDR_REG_BASE +0x533e0*4 +0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x533e1*4 +0x02000000,0xc010); +reg_write( DDR_REG_BASE +0x533e2*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x533e3*4 +0x02000000,0xad2); +reg_write( DDR_REG_BASE +0x533e4*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x533e5*4 +0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x533e6*4 +0x02000000,0x8e04); +reg_write( DDR_REG_BASE +0x533e7*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x533e8*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x533e9*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x533ea*4 +0x02000000,0xf034); +reg_write( DDR_REG_BASE +0x533eb*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x533ec*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x533ed*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x533ee*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x533ef*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533f0*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x533f1*4 +0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x533f2*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x533f3*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x533f4*4 +0x02000000,0x170); +reg_write( DDR_REG_BASE +0x533f5*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x533f6*4 +0x02000000,0xc245); +reg_write( DDR_REG_BASE +0x533f7*4 +0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x533f8*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x533f9*4 +0x02000000,0x8); +reg_write( DDR_REG_BASE +0x533fa*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x533fb*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x533fc*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x533fd*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x533fe*4 +0x02000000,0x166); +reg_write( DDR_REG_BASE +0x533ff*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x53400*4 +0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x53401*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53402*4 +0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x53403*4 +0x02000000,0x200f); +reg_write( DDR_REG_BASE +0x53404*4 +0x02000000,0x80); +reg_write( DDR_REG_BASE +0x53405*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x53406*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x53407*4 +0x02000000,0xae5); +reg_write( DDR_REG_BASE +0x53408*4 +0x02000000,0x8234); +reg_write( DDR_REG_BASE +0x53409*4 +0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x5340a*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5340b*4 +0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x5340c*4 +0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x5340d*4 +0x02000000,0xf40b); +reg_write( DDR_REG_BASE +0x5340e*4 +0x02000000,0xc303); +reg_write( DDR_REG_BASE +0x5340f*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x53410*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53411*4 +0x02000000,0xe); +reg_write( DDR_REG_BASE +0x53412*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x53413*4 +0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x53414*4 +0x02000000,0xe96); +reg_write( DDR_REG_BASE +0x53415*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53416*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53417*4 +0x02000000,0xc105); +reg_write( DDR_REG_BASE +0x53418*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x53419*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x5341a*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x5341b*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x5341c*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5341d*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5341e*4 +0x02000000,0x8e25); +reg_write( DDR_REG_BASE +0x5341f*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x53420*4 +0x02000000,0x997); +reg_write( DDR_REG_BASE +0x53421*4 +0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x53422*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53423*4 +0x02000000,0xdda); +reg_write( DDR_REG_BASE +0x53424*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53425*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x53426*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x53427*4 +0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x53428*4 +0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x53429*4 +0x02000000,0xf580); +reg_write( DDR_REG_BASE +0x5342a*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x5342b*4 +0x02000000,0x2008); +reg_write( DDR_REG_BASE +0x5342c*4 +0x02000000,0x340); +reg_write( DDR_REG_BASE +0x5342d*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5342e*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5342f*4 +0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x53430*4 +0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x53431*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53432*4 +0x02000000,0x11); +reg_write( DDR_REG_BASE +0x53433*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53434*4 +0x02000000,0x8ea); +reg_write( DDR_REG_BASE +0x53435*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53436*4 +0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x53437*4 +0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x53438*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x53439*4 +0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x5343a*4 +0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x5343b*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5343c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5343d*4 +0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x5343e*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5343f*4 +0x02000000,0xfa2); +reg_write( DDR_REG_BASE +0x53440*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x53441*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x53442*4 +0x02000000,0xc502); +reg_write( DDR_REG_BASE +0x53443*4 +0x02000000,0x7767); +reg_write( DDR_REG_BASE +0x53444*4 +0x02000000,0x7077); +reg_write( DDR_REG_BASE +0x53445*4 +0x02000000,0x664); +reg_write( DDR_REG_BASE +0x53446*4 +0x02000000,0xffea); +reg_write( DDR_REG_BASE +0x53447*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x53448*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x53449*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5344a*4 +0x02000000,0x13); +reg_write( DDR_REG_BASE +0x5344b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5344c*4 +0x02000000,0x7812); +reg_write( DDR_REG_BASE +0x5344d*4 +0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x5344e*4 +0x02000000,0xd); +reg_write( DDR_REG_BASE +0x5344f*4 +0x02000000,0x8b6); +reg_write( DDR_REG_BASE +0x53450*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53451*4 +0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x53452*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53453*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53454*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x53455*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53456*4 +0x02000000,0x16); +reg_write( DDR_REG_BASE +0x53457*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x53458*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53459*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5345a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5345b*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5345c*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x5345d*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x5345e*4 +0x02000000,0xe040); +reg_write( DDR_REG_BASE +0x5345f*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x53460*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x53461*4 +0x02000000,0x2049); +reg_write( DDR_REG_BASE +0x53462*4 +0x02000000,0x7c1); +reg_write( DDR_REG_BASE +0x53463*4 +0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x53464*4 +0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x53465*4 +0x02000000,0x243); +reg_write( DDR_REG_BASE +0x53466*4 +0x02000000,0x10fd); +reg_write( DDR_REG_BASE +0x53467*4 +0x02000000,0x809e); +reg_write( DDR_REG_BASE +0x53468*4 +0x02000000,0xe37); +reg_write( DDR_REG_BASE +0x53469*4 +0x02000000,0x315f); +reg_write( DDR_REG_BASE +0x5346a*4 +0x02000000,0x8e65); +reg_write( DDR_REG_BASE +0x5346b*4 +0x02000000,0x8e44); +reg_write( DDR_REG_BASE +0x5346c*4 +0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x5346d*4 +0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x5346e*4 +0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x5346f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53470*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x53471*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53472*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x53473*4 +0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x53474*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53475*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53476*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53477*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x53478*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x53479*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x5347a*4 +0x02000000,0xbe7); +reg_write( DDR_REG_BASE +0x5347b*4 +0x02000000,0x8085); +reg_write( DDR_REG_BASE +0x5347c*4 +0x02000000,0x962); +reg_write( DDR_REG_BASE +0x5347d*4 +0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x5347e*4 +0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x5347f*4 +0x02000000,0x243); +reg_write( DDR_REG_BASE +0x53480*4 +0x02000000,0x10fd); +reg_write( DDR_REG_BASE +0x53481*4 +0x02000000,0x809e); +reg_write( DDR_REG_BASE +0x53482*4 +0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x53483*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x53484*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x53485*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x53486*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53487*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x53488*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53489*4 +0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x5348a*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5348b*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5348c*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5348d*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x5348e*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x5348f*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x53490*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x53491*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x53492*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x53493*4 +0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x53494*4 +0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x53495*4 +0x02000000,0x7110); +reg_write( DDR_REG_BASE +0x53496*4 +0x02000000,0x5a4); +reg_write( DDR_REG_BASE +0x53497*4 +0x02000000,0xffce); +reg_write( DDR_REG_BASE +0x53498*4 +0x02000000,0xe15); +reg_write( DDR_REG_BASE +0x53499*4 +0x02000000,0x315e); +reg_write( DDR_REG_BASE +0x5349a*4 +0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x5349b*4 +0x02000000,0xae05); +reg_write( DDR_REG_BASE +0x5349c*4 +0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x5349d*4 +0x02000000,0xae04); +reg_write( DDR_REG_BASE +0x5349e*4 +0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x5349f*4 +0x02000000,0xae03); +reg_write( DDR_REG_BASE +0x534a0*4 +0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x534a1*4 +0x02000000,0xae02); +reg_write( DDR_REG_BASE +0x534a2*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x534a3*4 +0x02000000,0x1fa7); +reg_write( DDR_REG_BASE +0x534a4*4 +0x02000000,0x101c); +reg_write( DDR_REG_BASE +0x534a5*4 +0x02000000,0x1fa8); +reg_write( DDR_REG_BASE +0x534a6*4 +0x02000000,0x101c); +reg_write( DDR_REG_BASE +0x534a7*4 +0x02000000,0xb700); +reg_write( DDR_REG_BASE +0x534a8*4 +0x02000000,0xc0b1); +reg_write( DDR_REG_BASE +0x534a9*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x534aa*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x534ab*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x534ac*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x534ad*4 +0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x534ae*4 +0x02000000,0xf209); +reg_write( DDR_REG_BASE +0x534af*4 +0x02000000,0x821); +reg_write( DDR_REG_BASE +0x534b0*4 +0x02000000,0x1d1); +reg_write( DDR_REG_BASE +0x534b1*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x534b2*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x534b3*4 +0x02000000,0x238); +reg_write( DDR_REG_BASE +0x534b4*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x534b5*4 +0x02000000,0x45); +reg_write( DDR_REG_BASE +0x534b6*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x534b7*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x534b8*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x534b9*4 +0x02000000,0x238); +reg_write( DDR_REG_BASE +0x534ba*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x534bb*4 +0x02000000,0x105); +reg_write( DDR_REG_BASE +0x534bc*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x534bd*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x534be*4 +0x02000000,0x1209); +reg_write( DDR_REG_BASE +0x534bf*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x534c0*4 +0x02000000,0xe903); +reg_write( DDR_REG_BASE +0x534c1*4 +0x02000000,0x19); +reg_write( DDR_REG_BASE +0x534c2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534c3*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x534c4*4 +0x02000000,0x9018); +reg_write( DDR_REG_BASE +0x534c5*4 +0x02000000,0x64); +reg_write( DDR_REG_BASE +0x534c6*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x534c7*4 +0x02000000,0x55); +reg_write( DDR_REG_BASE +0x534c8*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x534c9*4 +0x02000000,0x1902); +reg_write( DDR_REG_BASE +0x534ca*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x534cb*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x534cc*4 +0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x534cd*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x534ce*4 +0x02000000,0xca09); +reg_write( DDR_REG_BASE +0x534cf*4 +0x02000000,0xe812); +reg_write( DDR_REG_BASE +0x534d0*4 +0x02000000,0xcc22); +reg_write( DDR_REG_BASE +0x534d1*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x534d2*4 +0x02000000,0x8010); +reg_write( DDR_REG_BASE +0x534d3*4 +0x02000000,0xf785); +reg_write( DDR_REG_BASE +0x534d4*4 +0x02000000,0xfc2); +reg_write( DDR_REG_BASE +0x534d5*4 +0x02000000,0xfd0f); +reg_write( DDR_REG_BASE +0x534d6*4 +0x02000000,0xcc22); +reg_write( DDR_REG_BASE +0x534d7*4 +0x02000000,0x2615); +reg_write( DDR_REG_BASE +0x534d8*4 +0x02000000,0x7001); +reg_write( DDR_REG_BASE +0x534d9*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x534da*4 +0x02000000,0x8e8); +reg_write( DDR_REG_BASE +0x534db*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x534dc*4 +0x02000000,0xa1a0); +reg_write( DDR_REG_BASE +0x534dd*4 +0x02000000,0x1a22); +reg_write( DDR_REG_BASE +0x534de*4 +0x02000000,0x301c); +reg_write( DDR_REG_BASE +0x534df*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x534e0*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x534e1*4 +0x02000000,0x9018); +reg_write( DDR_REG_BASE +0x534e2*4 +0x02000000,0x64); +reg_write( DDR_REG_BASE +0x534e3*4 +0x02000000,0xb1a0); +reg_write( DDR_REG_BASE +0x534e4*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x534e5*4 +0x02000000,0xdd10); +reg_write( DDR_REG_BASE +0x534e6*4 +0x02000000,0xbd61); +reg_write( DDR_REG_BASE +0x534e7*4 +0x02000000,0xd01); +reg_write( DDR_REG_BASE +0x534e8*4 +0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x534e9*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x534ea*4 +0x02000000,0xb102); +reg_write( DDR_REG_BASE +0x534eb*4 +0x02000000,0x80e); +reg_write( DDR_REG_BASE +0x534ec*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x534ed*4 +0x02000000,0x1902); +reg_write( DDR_REG_BASE +0x534ee*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x534ef*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x534f0*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x534f1*4 +0x02000000,0x9018); +reg_write( DDR_REG_BASE +0x534f2*4 +0x02000000,0x8); +reg_write( DDR_REG_BASE +0x534f3*4 +0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x534f4*4 +0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x534f5*4 +0x02000000,0x801f); +reg_write( DDR_REG_BASE +0x534f6*4 +0x02000000,0x195e); +reg_write( DDR_REG_BASE +0x534f7*4 +0x02000000,0x45); +reg_write( DDR_REG_BASE +0x534f8*4 +0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x534f9*4 +0x02000000,0x801); +reg_write( DDR_REG_BASE +0x534fa*4 +0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x534fb*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x534fc*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x534fd*4 +0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x534fe*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x534ff*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53500*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53501*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53502*4 +0x02000000,0x83b); +reg_write( DDR_REG_BASE +0x53503*4 +0x02000000,0x13f); +reg_write( DDR_REG_BASE +0x53504*4 +0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x53505*4 +0x02000000,0xca09); +reg_write( DDR_REG_BASE +0x53506*4 +0x02000000,0x7ef0); +reg_write( DDR_REG_BASE +0x53507*4 +0x02000000,0xe80a); +reg_write( DDR_REG_BASE +0x53508*4 +0x02000000,0xcc22); +reg_write( DDR_REG_BASE +0x53509*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x5350a*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5350b*4 +0x02000000,0x7902); +reg_write( DDR_REG_BASE +0x5350c*4 +0x02000000,0x6e02); +reg_write( DDR_REG_BASE +0x5350d*4 +0x02000000,0x7030); +reg_write( DDR_REG_BASE +0x5350e*4 +0x02000000,0xf4c); +reg_write( DDR_REG_BASE +0x5350f*4 +0x02000000,0xfd0a); +reg_write( DDR_REG_BASE +0x53510*4 +0x02000000,0xf3a); +reg_write( DDR_REG_BASE +0x53511*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x53512*4 +0x02000000,0xd808); +reg_write( DDR_REG_BASE +0x53513*4 +0x02000000,0xf76); +reg_write( DDR_REG_BASE +0x53514*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x53515*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x53516*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x53517*4 +0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x53518*4 +0x02000000,0xf6a); +reg_write( DDR_REG_BASE +0x53519*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5351a*4 +0x02000000,0x1504); +reg_write( DDR_REG_BASE +0x5351b*4 +0x02000000,0x1400); +reg_write( DDR_REG_BASE +0x5351c*4 +0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x5351d*4 +0x02000000,0xff9); +reg_write( DDR_REG_BASE +0x5351e*4 +0x02000000,0x9384); +reg_write( DDR_REG_BASE +0x5351f*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53520*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x53521*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53522*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53523*4 +0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x53524*4 +0x02000000,0x3109); +reg_write( DDR_REG_BASE +0x53525*4 +0x02000000,0xc352); +reg_write( DDR_REG_BASE +0x53526*4 +0x02000000,0xc245); +reg_write( DDR_REG_BASE +0x53527*4 +0x02000000,0xc154); +reg_write( DDR_REG_BASE +0x53528*4 +0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x53529*4 +0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x5352a*4 +0x02000000,0x243); +reg_write( DDR_REG_BASE +0x5352b*4 +0x02000000,0x88a0); +reg_write( DDR_REG_BASE +0x5352c*4 +0x02000000,0x10fc); +reg_write( DDR_REG_BASE +0x5352d*4 +0x02000000,0x808e); +reg_write( DDR_REG_BASE +0x5352e*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5352f*4 +0x02000000,0x710f); +reg_write( DDR_REG_BASE +0x53530*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x53531*4 +0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x53532*4 +0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x53533*4 +0x02000000,0xc06); +reg_write( DDR_REG_BASE +0x53534*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53535*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53536*4 +0x02000000,0xc050); +reg_write( DDR_REG_BASE +0x53537*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53538*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53539*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x5353a*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x5353b*4 +0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x5353c*4 +0x02000000,0xf46); +reg_write( DDR_REG_BASE +0x5353d*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x5353e*4 +0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x5353f*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53540*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53541*4 +0x02000000,0xff7f); +reg_write( DDR_REG_BASE +0x53542*4 +0x02000000,0x78e4); +reg_write( DDR_REG_BASE +0x53543*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53544*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x53545*4 +0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x53546*4 +0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x53547*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x53548*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x53549*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5354a*4 +0x02000000,0x1e4); +reg_write( DDR_REG_BASE +0x5354b*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5354c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5354d*4 +0x02000000,0x44d); +reg_write( DDR_REG_BASE +0x5354e*4 +0x02000000,0xde6); +reg_write( DDR_REG_BASE +0x5354f*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53550*4 +0x02000000,0xda60); +reg_write( DDR_REG_BASE +0x53551*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x53552*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x53553*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53554*4 +0x02000000,0x1e4); +reg_write( DDR_REG_BASE +0x53555*4 +0x02000000,0xae2); +reg_write( DDR_REG_BASE +0x53556*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x53557*4 +0x02000000,0xd960); +reg_write( DDR_REG_BASE +0x53558*4 +0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x53559*4 +0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x5355a*4 +0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x5355b*4 +0x02000000,0x37cf); +reg_write( DDR_REG_BASE +0x5355c*4 +0x02000000,0xef05); +reg_write( DDR_REG_BASE +0x5355d*4 +0x02000000,0xbf61); +reg_write( DDR_REG_BASE +0x5355e*4 +0x02000000,0xfff); +reg_write( DDR_REG_BASE +0x5355f*4 +0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x53560*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53561*4 +0x02000000,0x7edd); +reg_write( DDR_REG_BASE +0x53562*4 +0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x53563*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x53564*4 +0x02000000,0x7edd); +reg_write( DDR_REG_BASE +0x53565*4 +0x02000000,0x7edd); +reg_write( DDR_REG_BASE +0x53566*4 +0x02000000,0x7edd); +reg_write( DDR_REG_BASE +0x53567*4 +0x02000000,0x200f); +reg_write( DDR_REG_BASE +0x53568*4 +0x02000000,0x6c2); +reg_write( DDR_REG_BASE +0x53569*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5356a*4 +0x02000000,0x7edd); +reg_write( DDR_REG_BASE +0x5356b*4 +0x02000000,0x7edd); +reg_write( DDR_REG_BASE +0x5356c*4 +0x02000000,0xe807); +reg_write( DDR_REG_BASE +0x5356d*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5356e*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5356f*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x53570*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53571*4 +0x02000000,0xf0c4); +reg_write( DDR_REG_BASE +0x53572*4 +0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x53573*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53574*4 +0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x53575*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x53576*4 +0x02000000,0x7c1); +reg_write( DDR_REG_BASE +0x53577*4 +0x02000000,0xe906); +reg_write( DDR_REG_BASE +0x53578*4 +0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x53579*4 +0x02000000,0x901); +reg_write( DDR_REG_BASE +0x5357a*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x5357b*4 +0x02000000,0x7c9b); +reg_write( DDR_REG_BASE +0x5357c*4 +0x02000000,0x6821); +reg_write( DDR_REG_BASE +0x5357d*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x5357e*4 +0x02000000,0x8); +reg_write( DDR_REG_BASE +0x5357f*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53580*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53581*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53582*4 +0x02000000,0xe0c4); +reg_write( DDR_REG_BASE +0x53583*4 +0x02000000,0xb080); +reg_write( DDR_REG_BASE +0x53584*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x53585*4 +0x02000000,0x8e3); +reg_write( DDR_REG_BASE +0x53586*4 +0x02000000,0x8234); +reg_write( DDR_REG_BASE +0x53587*4 +0x02000000,0x4468); +reg_write( DDR_REG_BASE +0x53588*4 +0x02000000,0x1498); +reg_write( DDR_REG_BASE +0x53589*4 +0x02000000,0x3600); +reg_write( DDR_REG_BASE +0x5358a*4 +0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x5358b*4 +0x02000000,0x1f8d); +reg_write( DDR_REG_BASE +0x5358c*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5358d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5358e*4 +0x02000000,0x7bc6); +reg_write( DDR_REG_BASE +0x5358f*4 +0x02000000,0xc04d); +reg_write( DDR_REG_BASE +0x53590*4 +0x02000000,0x1497); +reg_write( DDR_REG_BASE +0x53591*4 +0x02000000,0x3600); +reg_write( DDR_REG_BASE +0x53592*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53593*4 +0x02000000,0xc34c); +reg_write( DDR_REG_BASE +0x53594*4 +0x02000000,0xc04e); +reg_write( DDR_REG_BASE +0x53595*4 +0x02000000,0x1496); +reg_write( DDR_REG_BASE +0x53596*4 +0x02000000,0x3600); +reg_write( DDR_REG_BASE +0x53597*4 +0x02000000,0xc551); +reg_write( DDR_REG_BASE +0x53598*4 +0x02000000,0xc04f); +reg_write( DDR_REG_BASE +0x53599*4 +0x02000000,0x784f); +reg_write( DDR_REG_BASE +0x5359a*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5359b*4 +0x02000000,0x926); +reg_write( DDR_REG_BASE +0x5359c*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5359d*4 +0x02000000,0xc053); +reg_write( DDR_REG_BASE +0x5359e*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5359f*4 +0x02000000,0xc14a); +reg_write( DDR_REG_BASE +0x535a0*4 +0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x535a1*4 +0x02000000,0x7a3b); +reg_write( DDR_REG_BASE +0x535a2*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x535a3*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x535a4*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x535a5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535a6*4 +0x02000000,0x1c4); +reg_write( DDR_REG_BASE +0x535a7*4 +0x02000000,0x22ce); +reg_write( DDR_REG_BASE +0x535a8*4 +0x02000000,0x21); +reg_write( DDR_REG_BASE +0x535a9*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x535aa*4 +0x02000000,0xa840); +reg_write( DDR_REG_BASE +0x535ab*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x535ac*4 +0x02000000,0x9eb); +reg_write( DDR_REG_BASE +0x535ad*4 +0x02000000,0x8434); +reg_write( DDR_REG_BASE +0x535ae*4 +0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x535af*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x535b0*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x535b1*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x535b2*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x535b3*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x535b4*4 +0x02000000,0x709e); +reg_write( DDR_REG_BASE +0x535b5*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x535b6*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x535b7*4 +0x02000000,0x8881); +reg_write( DDR_REG_BASE +0x535b8*4 +0x02000000,0x250a); +reg_write( DDR_REG_BASE +0x535b9*4 +0x02000000,0x1780); +reg_write( DDR_REG_BASE +0x535ba*4 +0x02000000,0xf047); +reg_write( DDR_REG_BASE +0x535bb*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x535bc*4 +0x02000000,0xf042); +reg_write( DDR_REG_BASE +0x535bd*4 +0x02000000,0xc010); +reg_write( DDR_REG_BASE +0x535be*4 +0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x535bf*4 +0x02000000,0xc01); +reg_write( DDR_REG_BASE +0x535c0*4 +0x02000000,0xc011); +reg_write( DDR_REG_BASE +0x535c1*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x535c2*4 +0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x535c3*4 +0x02000000,0x1f81); +reg_write( DDR_REG_BASE +0x535c4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535c5*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x535c6*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x535c7*4 +0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x535c8*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x535c9*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x535ca*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x535cb*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x535cc*4 +0x02000000,0xb891); +reg_write( DDR_REG_BASE +0x535cd*4 +0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x535ce*4 +0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x535cf*4 +0x02000000,0x90e0); +reg_write( DDR_REG_BASE +0x535d0*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x535d1*4 +0x02000000,0x2378); +reg_write( DDR_REG_BASE +0x535d2*4 +0x02000000,0x201); +reg_write( DDR_REG_BASE +0x535d3*4 +0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x535d4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535d5*4 +0x02000000,0x2007); +reg_write( DDR_REG_BASE +0x535d6*4 +0x02000000,0x807e); +reg_write( DDR_REG_BASE +0x535d7*4 +0x02000000,0xf427); +reg_write( DDR_REG_BASE +0x535d8*4 +0x02000000,0x78fd); +reg_write( DDR_REG_BASE +0x535d9*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x535da*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x535db*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x535dc*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x535dd*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x535de*4 +0x02000000,0xbfc4); +reg_write( DDR_REG_BASE +0x535df*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x535e0*4 +0x02000000,0xe807); +reg_write( DDR_REG_BASE +0x535e1*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x535e2*4 +0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x535e3*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x535e4*4 +0x02000000,0x2180); +reg_write( DDR_REG_BASE +0x535e5*4 +0x02000000,0x30); +reg_write( DDR_REG_BASE +0x535e6*4 +0x02000000,0x79e5); +reg_write( DDR_REG_BASE +0x535e7*4 +0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x535e8*4 +0x02000000,0x148b); +reg_write( DDR_REG_BASE +0x535e9*4 +0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x535ea*4 +0x02000000,0x3882); +reg_write( DDR_REG_BASE +0x535eb*4 +0x02000000,0x7261); +reg_write( DDR_REG_BASE +0x535ec*4 +0x02000000,0x7a74); +reg_write( DDR_REG_BASE +0x535ed*4 +0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x535ee*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x535ef*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535f0*4 +0x02000000,0x141f); +reg_write( DDR_REG_BASE +0x535f1*4 +0x02000000,0x813); +reg_write( DDR_REG_BASE +0x535f2*4 +0x02000000,0x150); +reg_write( DDR_REG_BASE +0x535f3*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x535f4*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x535f5*4 +0x02000000,0x2080); +reg_write( DDR_REG_BASE +0x535f6*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x535f7*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x535f8*4 +0x02000000,0x3c1); +reg_write( DDR_REG_BASE +0x535f9*4 +0x02000000,0xc097); +reg_write( DDR_REG_BASE +0x535fa*4 +0x02000000,0x7061); +reg_write( DDR_REG_BASE +0x535fb*4 +0x02000000,0x7874); +reg_write( DDR_REG_BASE +0x535fc*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x535fd*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x535fe*4 +0x02000000,0xb7f); +reg_write( DDR_REG_BASE +0x535ff*4 +0x02000000,0x8254); +reg_write( DDR_REG_BASE +0x53600*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x53601*4 +0x02000000,0x7eaf); +reg_write( DDR_REG_BASE +0x53602*4 +0x02000000,0xc73); +reg_write( DDR_REG_BASE +0x53603*4 +0x02000000,0x93a5); +reg_write( DDR_REG_BASE +0x53604*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x53605*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53606*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53607*4 +0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x53608*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x53609*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5360a*4 +0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x5360b*4 +0x02000000,0x703c); +reg_write( DDR_REG_BASE +0x5360c*4 +0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x5360d*4 +0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x5360e*4 +0x02000000,0x3240); +reg_write( DDR_REG_BASE +0x5360f*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53610*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53611*4 +0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x53612*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53613*4 +0x02000000,0xc055); +reg_write( DDR_REG_BASE +0x53614*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x53615*4 +0x02000000,0x200); +reg_write( DDR_REG_BASE +0x53616*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x53617*4 +0x02000000,0xf0df); +reg_write( DDR_REG_BASE +0x53618*4 +0x02000000,0xc109); +reg_write( DDR_REG_BASE +0x53619*4 +0x02000000,0x8d2); +reg_write( DDR_REG_BASE +0x5361a*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5361b*4 +0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x5361c*4 +0x02000000,0x3880); +reg_write( DDR_REG_BASE +0x5361d*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x5361e*4 +0x02000000,0x9e2); +reg_write( DDR_REG_BASE +0x5361f*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53620*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x53621*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x53622*4 +0x02000000,0xb5a); +reg_write( DDR_REG_BASE +0x53623*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x53624*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x53625*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x53626*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53627*4 +0x02000000,0xe024); +reg_write( DDR_REG_BASE +0x53628*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x53629*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5362a*4 +0x02000000,0x1f84); +reg_write( DDR_REG_BASE +0x5362b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5362c*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x5362d*4 +0x02000000,0xb606); +reg_write( DDR_REG_BASE +0x5362e*4 +0x02000000,0x1efe); +reg_write( DDR_REG_BASE +0x5362f*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x53630*4 +0x02000000,0x1ea8); +reg_write( DDR_REG_BASE +0x53631*4 +0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x53632*4 +0x02000000,0x1ea9); +reg_write( DDR_REG_BASE +0x53633*4 +0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x53634*4 +0x02000000,0xc014); +reg_write( DDR_REG_BASE +0x53635*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53636*4 +0x02000000,0xe020); +reg_write( DDR_REG_BASE +0x53637*4 +0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x53638*4 +0x02000000,0xe26); +reg_write( DDR_REG_BASE +0x53639*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x5363a*4 +0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x5363b*4 +0x02000000,0xc015); +reg_write( DDR_REG_BASE +0x5363c*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5363d*4 +0x02000000,0x68e1); +reg_write( DDR_REG_BASE +0x5363e*4 +0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x5363f*4 +0x02000000,0xcc6); +reg_write( DDR_REG_BASE +0x53640*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x53641*4 +0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x53642*4 +0x02000000,0xc109); +reg_write( DDR_REG_BASE +0x53643*4 +0x02000000,0x87e); +reg_write( DDR_REG_BASE +0x53644*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x53645*4 +0x02000000,0xc097); +reg_write( DDR_REG_BASE +0x53646*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53647*4 +0x02000000,0x992); +reg_write( DDR_REG_BASE +0x53648*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53649*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x5364a*4 +0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x5364b*4 +0x02000000,0xb0a); +reg_write( DDR_REG_BASE +0x5364c*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x5364d*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x5364e*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5364f*4 +0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x53650*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53651*4 +0x02000000,0x1f84); +reg_write( DDR_REG_BASE +0x53652*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53653*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x53654*4 +0x02000000,0xb626); +reg_write( DDR_REG_BASE +0x53655*4 +0x02000000,0x1efe); +reg_write( DDR_REG_BASE +0x53656*4 +0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x53657*4 +0x02000000,0x1ea8); +reg_write( DDR_REG_BASE +0x53658*4 +0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x53659*4 +0x02000000,0xde6); +reg_write( DDR_REG_BASE +0x5365a*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x5365b*4 +0x02000000,0x1ea9); +reg_write( DDR_REG_BASE +0x5365c*4 +0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x5365d*4 +0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x5365e*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5365f*4 +0x02000000,0xc86); +reg_write( DDR_REG_BASE +0x53660*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x53661*4 +0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x53662*4 +0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x53663*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x53664*4 +0x02000000,0xc056); +reg_write( DDR_REG_BASE +0x53665*4 +0x02000000,0xe08f); +reg_write( DDR_REG_BASE +0x53666*4 +0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x53667*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x53668*4 +0x02000000,0x61); +reg_write( DDR_REG_BASE +0x53669*4 +0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x5366a*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5366b*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5366c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5366d*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x5366e*4 +0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x5366f*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53670*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x53671*4 +0x02000000,0xf075); +reg_write( DDR_REG_BASE +0x53672*4 +0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x53673*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x53674*4 +0x02000000,0xc607); +reg_write( DDR_REG_BASE +0x53675*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x53676*4 +0x02000000,0xc146); +reg_write( DDR_REG_BASE +0x53677*4 +0x02000000,0x722c); +reg_write( DDR_REG_BASE +0x53678*4 +0x02000000,0xf068); +reg_write( DDR_REG_BASE +0x53679*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x5367a*4 +0x02000000,0xe17); +reg_write( DDR_REG_BASE +0x5367b*4 +0x02000000,0x1231); +reg_write( DDR_REG_BASE +0x5367c*4 +0x02000000,0x7a10); +reg_write( DDR_REG_BASE +0x5367d*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5367e*4 +0x02000000,0xe887); +reg_write( DDR_REG_BASE +0x5367f*4 +0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x53680*4 +0x02000000,0x7854); +reg_write( DDR_REG_BASE +0x53681*4 +0x02000000,0x10f0); +reg_write( DDR_REG_BASE +0x53682*4 +0x02000000,0x8102); +reg_write( DDR_REG_BASE +0x53683*4 +0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x53684*4 +0x02000000,0xf058); +reg_write( DDR_REG_BASE +0x53685*4 +0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x53686*4 +0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x53687*4 +0x02000000,0x83); +reg_write( DDR_REG_BASE +0x53688*4 +0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x53689*4 +0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x5368a*4 +0x02000000,0x8c); +reg_write( DDR_REG_BASE +0x5368b*4 +0x02000000,0x4c70); +reg_write( DDR_REG_BASE +0x5368c*4 +0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x5368d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5368e*4 +0x02000000,0x7f0e); +reg_write( DDR_REG_BASE +0x5368f*4 +0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x53690*4 +0x02000000,0x11b3); +reg_write( DDR_REG_BASE +0x53691*4 +0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x53692*4 +0x02000000,0x203c); +reg_write( DDR_REG_BASE +0x53693*4 +0x02000000,0x39b); +reg_write( DDR_REG_BASE +0x53694*4 +0x02000000,0x991); +reg_write( DDR_REG_BASE +0x53695*4 +0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x53696*4 +0x02000000,0x43c1); +reg_write( DDR_REG_BASE +0x53697*4 +0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x53698*4 +0x02000000,0xc208); +reg_write( DDR_REG_BASE +0x53699*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5369a*4 +0x02000000,0x14); +reg_write( DDR_REG_BASE +0x5369b*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x5369c*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x5369d*4 +0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x5369e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5369f*4 +0x02000000,0xc16); +reg_write( DDR_REG_BASE +0x536a0*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x536a1*4 +0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x536a2*4 +0x02000000,0xc010); +reg_write( DDR_REG_BASE +0x536a3*4 +0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x536a4*4 +0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x536a5*4 +0x02000000,0x8c1); +reg_write( DDR_REG_BASE +0x536a6*4 +0x02000000,0xc011); +reg_write( DDR_REG_BASE +0x536a7*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x536a8*4 +0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x536a9*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x536aa*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x536ab*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ac*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x536ad*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x536ae*4 +0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x536af*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x536b0*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x536b1*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x536b2*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x536b3*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x536b4*4 +0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x536b5*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x536b6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536b7*4 +0x02000000,0x9540); +reg_write( DDR_REG_BASE +0x536b8*4 +0x02000000,0xc016); +reg_write( DDR_REG_BASE +0x536b9*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x536ba*4 +0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x536bb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536bc*4 +0x02000000,0x1c4); +reg_write( DDR_REG_BASE +0x536bd*4 +0x02000000,0x2133); +reg_write( DDR_REG_BASE +0x536be*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x536bf*4 +0x02000000,0xc240); +reg_write( DDR_REG_BASE +0x536c0*4 +0x02000000,0x6158); +reg_write( DDR_REG_BASE +0x536c1*4 +0x02000000,0x780e); +reg_write( DDR_REG_BASE +0x536c2*4 +0x02000000,0xc208); +reg_write( DDR_REG_BASE +0x536c3*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x536c4*4 +0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x536c5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536c6*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x536c7*4 +0x02000000,0x2049); +reg_write( DDR_REG_BASE +0x536c8*4 +0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x536c9*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x536ca*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x536cb*4 +0x02000000,0x15); +reg_write( DDR_REG_BASE +0x536cc*4 +0x02000000,0x6); +reg_write( DDR_REG_BASE +0x536cd*4 +0x02000000,0x926); +reg_write( DDR_REG_BASE +0x536ce*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x536cf*4 +0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x536d0*4 +0x02000000,0xb5e0); +reg_write( DDR_REG_BASE +0x536d1*4 +0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x536d2*4 +0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x536d3*4 +0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x536d4*4 +0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x536d5*4 +0x02000000,0x2014); +reg_write( DDR_REG_BASE +0x536d6*4 +0x02000000,0x82); +reg_write( DDR_REG_BASE +0x536d7*4 +0x02000000,0x6478); +reg_write( DDR_REG_BASE +0x536d8*4 +0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x536d9*4 +0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x536da*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536db*4 +0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x536dc*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x536dd*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x536de*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x536df*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x536e0*4 +0x02000000,0xe33); +reg_write( DDR_REG_BASE +0x536e1*4 +0x02000000,0x9254); +reg_write( DDR_REG_BASE +0x536e2*4 +0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x536e3*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x536e4*4 +0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x536e5*4 +0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x536e6*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x536e7*4 +0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x536e8*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x536e9*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x536ea*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x536eb*4 +0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x536ec*4 +0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x536ed*4 +0x02000000,0x90d); +reg_write( DDR_REG_BASE +0x536ee*4 +0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x536ef*4 +0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x536f0*4 +0x02000000,0xbe0); +reg_write( DDR_REG_BASE +0x536f1*4 +0x02000000,0xfe82); +reg_write( DDR_REG_BASE +0x536f2*4 +0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x536f3*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x536f4*4 +0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x536f5*4 +0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x536f6*4 +0x02000000,0xf522); +reg_write( DDR_REG_BASE +0x536f7*4 +0x02000000,0xc012); +reg_write( DDR_REG_BASE +0x536f8*4 +0x02000000,0x881); +reg_write( DDR_REG_BASE +0x536f9*4 +0x02000000,0x30); +reg_write( DDR_REG_BASE +0x536fa*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x536fb*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x536fc*4 +0x02000000,0x16); +reg_write( DDR_REG_BASE +0x536fd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536fe*4 +0x02000000,0x8c2); +reg_write( DDR_REG_BASE +0x536ff*4 +0x02000000,0xfd0f); +reg_write( DDR_REG_BASE +0x53700*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53701*4 +0x02000000,0x708e); +reg_write( DDR_REG_BASE +0x53702*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53703*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53704*4 +0x02000000,0xf02d); +reg_write( DDR_REG_BASE +0x53705*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53706*4 +0x02000000,0xc707); +reg_write( DDR_REG_BASE +0x53707*4 +0x02000000,0x7910); +reg_write( DDR_REG_BASE +0x53708*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x53709*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x5370a*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5370b*4 +0x02000000,0xf024); +reg_write( DDR_REG_BASE +0x5370c*4 +0x02000000,0xf09); +reg_write( DDR_REG_BASE +0x5370d*4 +0x02000000,0x1211); +reg_write( DDR_REG_BASE +0x5370e*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5370f*4 +0x02000000,0xe81c); +reg_write( DDR_REG_BASE +0x53710*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53711*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53712*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x53713*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x53714*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53715*4 +0x02000000,0xfffe); +reg_write( DDR_REG_BASE +0x53716*4 +0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x53717*4 +0x02000000,0x2035); +reg_write( DDR_REG_BASE +0x53718*4 +0x02000000,0x43); +reg_write( DDR_REG_BASE +0x53719*4 +0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x5371a*4 +0x02000000,0x2035); +reg_write( DDR_REG_BASE +0x5371b*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x5371c*4 +0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x5371d*4 +0x02000000,0x2035); +reg_write( DDR_REG_BASE +0x5371e*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x5371f*4 +0x02000000,0xc241); +reg_write( DDR_REG_BASE +0x53720*4 +0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x53721*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53722*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x53723*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53724*4 +0x02000000,0x17); +reg_write( DDR_REG_BASE +0x53725*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x53726*4 +0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x53727*4 +0x02000000,0x872); +reg_write( DDR_REG_BASE +0x53728*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53729*4 +0x02000000,0x43e1); +reg_write( DDR_REG_BASE +0x5372a*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5372b*4 +0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x5372c*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5372d*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5372e*4 +0x02000000,0xfbd); +reg_write( DDR_REG_BASE +0x5372f*4 +0x02000000,0x9254); +reg_write( DDR_REG_BASE +0x53730*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x53731*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53732*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53733*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53734*4 +0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x53735*4 +0x02000000,0x7dcf); +reg_write( DDR_REG_BASE +0x53736*4 +0x02000000,0x89f); +reg_write( DDR_REG_BASE +0x53737*4 +0x02000000,0x8345); +reg_write( DDR_REG_BASE +0x53738*4 +0x02000000,0x98a); +reg_write( DDR_REG_BASE +0x53739*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x5373a*4 +0x02000000,0xc013); +reg_write( DDR_REG_BASE +0x5373b*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5373c*4 +0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x5373d*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5373e*4 +0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x5373f*4 +0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x53740*4 +0x02000000,0x3109); +reg_write( DDR_REG_BASE +0x53741*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x53742*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x53743*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53744*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x53745*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53746*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53747*4 +0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x53748*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x53749*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x5374a*4 +0x02000000,0x641); +reg_write( DDR_REG_BASE +0x5374b*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5374c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5374d*4 +0x02000000,0x7c9); +reg_write( DDR_REG_BASE +0x5374e*4 +0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x5374f*4 +0x02000000,0x4358); +reg_write( DDR_REG_BASE +0x53750*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x53751*4 +0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x53752*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x53753*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x53754*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53755*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53756*4 +0x02000000,0x67c); +reg_write( DDR_REG_BASE +0x53757*4 +0x02000000,0x88e2); +reg_write( DDR_REG_BASE +0x53758*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53759*4 +0x02000000,0xb4e); +reg_write( DDR_REG_BASE +0x5375a*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x5375b*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5375c*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5375d*4 +0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x5375e*4 +0x02000000,0x17ca); +reg_write( DDR_REG_BASE +0x5375f*4 +0x02000000,0xa11); +reg_write( DDR_REG_BASE +0x53760*4 +0x02000000,0x1010); +reg_write( DDR_REG_BASE +0x53761*4 +0x02000000,0x2242); +reg_write( DDR_REG_BASE +0x53762*4 +0x02000000,0x104a); +reg_write( DDR_REG_BASE +0x53763*4 +0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x53764*4 +0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x53765*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53766*4 +0x02000000,0x7077); +reg_write( DDR_REG_BASE +0x53767*4 +0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x53768*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x53769*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5376a*4 +0x02000000,0x27cf); +reg_write( DDR_REG_BASE +0x5376b*4 +0x02000000,0x11e2); +reg_write( DDR_REG_BASE +0x5376c*4 +0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x5376d*4 +0x02000000,0x200f); +reg_write( DDR_REG_BASE +0x5376e*4 +0x02000000,0x340); +reg_write( DDR_REG_BASE +0x5376f*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x53770*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53771*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53772*4 +0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x53773*4 +0x02000000,0x4628); +reg_write( DDR_REG_BASE +0x53774*4 +0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x53775*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x53776*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x53777*4 +0x02000000,0xdfa); +reg_write( DDR_REG_BASE +0x53778*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53779*4 +0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x5377a*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5377b*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x5377c*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5377d*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5377e*4 +0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x5377f*4 +0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x53780*4 +0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x53781*4 +0x02000000,0xbd6); +reg_write( DDR_REG_BASE +0x53782*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53783*4 +0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x53784*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53785*4 +0x02000000,0xb8e); +reg_write( DDR_REG_BASE +0x53786*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53787*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53788*4 +0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x53789*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x5378a*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x5378b*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5378c*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5378d*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5378e*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5378f*4 +0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x53790*4 +0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x53791*4 +0x02000000,0x9d2); +reg_write( DDR_REG_BASE +0x53792*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x53793*4 +0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x53794*4 +0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x53795*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53796*4 +0x02000000,0xad2); +reg_write( DDR_REG_BASE +0x53797*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53798*4 +0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x53799*4 +0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x5379a*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5379b*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5379c*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5379d*4 +0x02000000,0xdb28); +reg_write( DDR_REG_BASE +0x5379e*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x5379f*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537a0*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x537a1*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x537a2*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537a3*4 +0x02000000,0xb92); +reg_write( DDR_REG_BASE +0x537a4*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x537a5*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x537a6*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537a7*4 +0x02000000,0xdd6); +reg_write( DDR_REG_BASE +0x537a8*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x537a9*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x537aa*4 +0x02000000,0xe62e); +reg_write( DDR_REG_BASE +0x537ab*4 +0x02000000,0xed18); +reg_write( DDR_REG_BASE +0x537ac*4 +0x02000000,0xf836); +reg_write( DDR_REG_BASE +0x537ad*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x537ae*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537af*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x537b0*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x537b1*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537b2*4 +0x02000000,0xb72); +reg_write( DDR_REG_BASE +0x537b3*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x537b4*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x537b5*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537b6*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x537b7*4 +0x02000000,0xd90c); +reg_write( DDR_REG_BASE +0x537b8*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x537b9*4 +0x02000000,0xdb0a); +reg_write( DDR_REG_BASE +0x537ba*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x537bb*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537bc*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x537bd*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x537be*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537bf*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x537c0*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537c1*4 +0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x537c2*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x537c3*4 +0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x537c4*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x537c5*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x537c6*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537c7*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x537c8*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537c9*4 +0x02000000,0xf828); +reg_write( DDR_REG_BASE +0x537ca*4 +0x02000000,0xb42); +reg_write( DDR_REG_BASE +0x537cb*4 +0x02000000,0xfccf); +reg_write( DDR_REG_BASE +0x537cc*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x537cd*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x537ce*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x537cf*4 +0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x537d0*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x537d1*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537d2*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x537d3*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x537d4*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537d5*4 +0x02000000,0xb2e); +reg_write( DDR_REG_BASE +0x537d6*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x537d7*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x537d8*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x537d9*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x537da*4 +0x02000000,0x7bcf); +reg_write( DDR_REG_BASE +0x537db*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x537dc*4 +0x02000000,0xd90c); +reg_write( DDR_REG_BASE +0x537dd*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x537de*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x537df*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x537e0*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x537e1*4 +0x02000000,0xb16); +reg_write( DDR_REG_BASE +0x537e2*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x537e3*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x537e4*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x537e5*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x537e6*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x537e7*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x537e8*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x537e9*4 +0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x537ea*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x537eb*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x537ec*4 +0x02000000,0xafe); +reg_write( DDR_REG_BASE +0x537ed*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x537ee*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x537ef*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x537f0*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x537f1*4 +0x02000000,0xb98f); +reg_write( DDR_REG_BASE +0x537f2*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x537f3*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x537f4*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x537f5*4 +0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x537f6*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x537f7*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x537f8*4 +0x02000000,0xae6); +reg_write( DDR_REG_BASE +0x537f9*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x537fa*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x537fb*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x537fc*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x537fd*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x537fe*4 +0x02000000,0xdb10); +reg_write( DDR_REG_BASE +0x537ff*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x53800*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x53801*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53802*4 +0x02000000,0xad2); +reg_write( DDR_REG_BASE +0x53803*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53804*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53805*4 +0x02000000,0xcfe); +reg_write( DDR_REG_BASE +0x53806*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53807*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53808*4 +0x02000000,0xbfc1); +reg_write( DDR_REG_BASE +0x53809*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5380a*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x5380b*4 +0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x5380c*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x5380d*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5380e*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5380f*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53810*4 +0x02000000,0xab6); +reg_write( DDR_REG_BASE +0x53811*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53812*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x53813*4 +0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x53814*4 +0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x53815*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x53816*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x53817*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53818*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53819*4 +0x02000000,0xd90c); +reg_write( DDR_REG_BASE +0x5381a*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x5381b*4 +0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x5381c*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5381d*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5381e*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5381f*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53820*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53821*4 +0x02000000,0xc1a8); +reg_write( DDR_REG_BASE +0x53822*4 +0x02000000,0xc145); +reg_write( DDR_REG_BASE +0x53823*4 +0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x53824*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53825*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x53826*4 +0x02000000,0xc346); +reg_write( DDR_REG_BASE +0x53827*4 +0x02000000,0x9b2); +reg_write( DDR_REG_BASE +0x53828*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53829*4 +0x02000000,0xc244); +reg_write( DDR_REG_BASE +0x5382a*4 +0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x5382b*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x5382c*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x5382d*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x5382e*4 +0x02000000,0xf03a); +reg_write( DDR_REG_BASE +0x5382f*4 +0x02000000,0x2532); +reg_write( DDR_REG_BASE +0x53830*4 +0x02000000,0x1f8f); +reg_write( DDR_REG_BASE +0x53831*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53832*4 +0x02000000,0x624); +reg_write( DDR_REG_BASE +0x53833*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53834*4 +0x02000000,0x896); +reg_write( DDR_REG_BASE +0x53835*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53836*4 +0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x53837*4 +0x02000000,0xc207); +reg_write( DDR_REG_BASE +0x53838*4 +0x02000000,0x7944); +reg_write( DDR_REG_BASE +0x53839*4 +0x02000000,0xc206); +reg_write( DDR_REG_BASE +0x5383a*4 +0x02000000,0x7844); +reg_write( DDR_REG_BASE +0x5383b*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5383c*4 +0x02000000,0x807e); +reg_write( DDR_REG_BASE +0x5383d*4 +0x02000000,0xf42b); +reg_write( DDR_REG_BASE +0x5383e*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5383f*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53840*4 +0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x53841*4 +0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x53842*4 +0x02000000,0x60e8); +reg_write( DDR_REG_BASE +0x53843*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x53844*4 +0x02000000,0x3001); +reg_write( DDR_REG_BASE +0x53845*4 +0x02000000,0x1c08); +reg_write( DDR_REG_BASE +0x53846*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x53847*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x53848*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53849*4 +0x02000000,0xc56); +reg_write( DDR_REG_BASE +0x5384a*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x5384b*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x5384c*4 +0x02000000,0xd07); +reg_write( DDR_REG_BASE +0x5384d*4 +0x02000000,0x1190); +reg_write( DDR_REG_BASE +0x5384e*4 +0x02000000,0xed99); +reg_write( DDR_REG_BASE +0x5384f*4 +0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x53850*4 +0x02000000,0xd9c8); +reg_write( DDR_REG_BASE +0x53851*4 +0x02000000,0xd8fa); +reg_write( DDR_REG_BASE +0x53852*4 +0x02000000,0xa5e); +reg_write( DDR_REG_BASE +0x53853*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x53854*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x53855*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x53856*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x53857*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x53858*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x53859*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5385a*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5385b*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x5385c*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5385d*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5385e*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5385f*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x53860*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x53861*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53862*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53863*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53864*4 +0x02000000,0xc1e); +reg_write( DDR_REG_BASE +0x53865*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53866*4 +0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x53867*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x53868*4 +0x02000000,0xd8f); +reg_write( DDR_REG_BASE +0x53869*4 +0x02000000,0x9334); +reg_write( DDR_REG_BASE +0x5386a*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5386b*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5386c*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5386d*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5386e*4 +0x02000000,0xdb41); +reg_write( DDR_REG_BASE +0x5386f*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x53870*4 +0x02000000,0x3401); +reg_write( DDR_REG_BASE +0x53871*4 +0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x53872*4 +0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x53873*4 +0x02000000,0x9f2); +reg_write( DDR_REG_BASE +0x53874*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53875*4 +0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x53876*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53877*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x53878*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53879*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x5387a*4 +0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x5387b*4 +0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x5387c*4 +0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x5387d*4 +0x02000000,0x9de); +reg_write( DDR_REG_BASE +0x5387e*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x5387f*4 +0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x53880*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53881*4 +0x02000000,0x996); +reg_write( DDR_REG_BASE +0x53882*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53883*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53884*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53885*4 +0x02000000,0xe833); +reg_write( DDR_REG_BASE +0x53886*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53887*4 +0x02000000,0x8f2); +reg_write( DDR_REG_BASE +0x53888*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53889*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x5388a*4 +0x02000000,0xd84f); +reg_write( DDR_REG_BASE +0x5388b*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x5388c*4 +0x02000000,0x2353); +reg_write( DDR_REG_BASE +0x5388d*4 +0x02000000,0x305b); +reg_write( DDR_REG_BASE +0x5388e*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5388f*4 +0x02000000,0xf817); +reg_write( DDR_REG_BASE +0x53890*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x53891*4 +0x02000000,0x1c08); +reg_write( DDR_REG_BASE +0x53892*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x53893*4 +0x02000000,0x9b2); +reg_write( DDR_REG_BASE +0x53894*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53895*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53896*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53897*4 +0x02000000,0x96a); +reg_write( DDR_REG_BASE +0x53898*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53899*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5389a*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5389b*4 +0x02000000,0xf); +reg_write( DDR_REG_BASE +0x5389c*4 +0x02000000,0x4240); +reg_write( DDR_REG_BASE +0x5389d*4 +0x02000000,0xfa6); +reg_write( DDR_REG_BASE +0x5389e*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5389f*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x538a0*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x538a1*4 +0x02000000,0x8be); +reg_write( DDR_REG_BASE +0x538a2*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x538a3*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x538a4*4 +0x02000000,0xd851); +reg_write( DDR_REG_BASE +0x538a5*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x538a6*4 +0x02000000,0xf80b); +reg_write( DDR_REG_BASE +0x538a7*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x538a8*4 +0x02000000,0x1c08); +reg_write( DDR_REG_BASE +0x538a9*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x538aa*4 +0x02000000,0x982); +reg_write( DDR_REG_BASE +0x538ab*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x538ac*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x538ad*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x538ae*4 +0x02000000,0x93a); +reg_write( DDR_REG_BASE +0x538af*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x538b0*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x538b1*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x538b2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538b3*4 +0x02000000,0x1f40); +reg_write( DDR_REG_BASE +0x538b4*4 +0x02000000,0xf76); +reg_write( DDR_REG_BASE +0x538b5*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x538b6*4 +0x02000000,0xd91e); +reg_write( DDR_REG_BASE +0x538b7*4 +0x02000000,0xc0a8); +reg_write( DDR_REG_BASE +0x538b8*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x538b9*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x538ba*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x538bb*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x538bc*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x538bd*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x538be*4 +0x02000000,0xda17); +reg_write( DDR_REG_BASE +0x538bf*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x538c0*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x538c1*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x538c2*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x538c3*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x538c4*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x538c5*4 +0x02000000,0xc1ac); +reg_write( DDR_REG_BASE +0x538c6*4 +0x02000000,0xc349); +reg_write( DDR_REG_BASE +0x538c7*4 +0x02000000,0xc247); +reg_write( DDR_REG_BASE +0x538c8*4 +0x02000000,0xc14a); +reg_write( DDR_REG_BASE +0x538c9*4 +0x02000000,0xc5e); +reg_write( DDR_REG_BASE +0x538ca*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x538cb*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x538cc*4 +0x02000000,0xc011); +reg_write( DDR_REG_BASE +0x538cd*4 +0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x538ce*4 +0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x538cf*4 +0x02000000,0xc012); +reg_write( DDR_REG_BASE +0x538d0*4 +0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x538d1*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x538d2*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x538d3*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x538d4*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x538d5*4 +0x02000000,0xf0b8); +reg_write( DDR_REG_BASE +0x538d6*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x538d7*4 +0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x538d8*4 +0x02000000,0xf9b); +reg_write( DDR_REG_BASE +0x538d9*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x538da*4 +0x02000000,0x624); +reg_write( DDR_REG_BASE +0x538db*4 +0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x538dc*4 +0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x538dd*4 +0x02000000,0x6ce); +reg_write( DDR_REG_BASE +0x538de*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x538df*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x538e0*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x538e1*4 +0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x538e2*4 +0x02000000,0xf40b); +reg_write( DDR_REG_BASE +0x538e3*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x538e4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538e5*4 +0x02000000,0xa00); +reg_write( DDR_REG_BASE +0x538e6*4 +0x02000000,0x832); +reg_write( DDR_REG_BASE +0x538e7*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x538e8*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x538e9*4 +0x02000000,0x852); +reg_write( DDR_REG_BASE +0x538ea*4 +0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x538eb*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x538ec*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x538ed*4 +0x02000000,0x41e1); +reg_write( DDR_REG_BASE +0x538ee*4 +0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x538ef*4 +0x02000000,0x37c0); +reg_write( DDR_REG_BASE +0x538f0*4 +0x02000000,0xc209); +reg_write( DDR_REG_BASE +0x538f1*4 +0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x538f2*4 +0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x538f3*4 +0x02000000,0x801); +reg_write( DDR_REG_BASE +0x538f4*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x538f5*4 +0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x538f6*4 +0x02000000,0xd81f); +reg_write( DDR_REG_BASE +0x538f7*4 +0x02000000,0x7a24); +reg_write( DDR_REG_BASE +0x538f8*4 +0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x538f9*4 +0x02000000,0x801); +reg_write( DDR_REG_BASE +0x538fa*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x538fb*4 +0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x538fc*4 +0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x538fd*4 +0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x538fe*4 +0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x538ff*4 +0x02000000,0x803e); +reg_write( DDR_REG_BASE +0x53900*4 +0x02000000,0xf479); +reg_write( DDR_REG_BASE +0x53901*4 +0x02000000,0x78dd); +reg_write( DDR_REG_BASE +0x53902*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x53903*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x53904*4 +0x02000000,0x800); +reg_write( DDR_REG_BASE +0x53905*4 +0x02000000,0x2045); +reg_write( DDR_REG_BASE +0x53906*4 +0x02000000,0x18d); +reg_write( DDR_REG_BASE +0x53907*4 +0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x53908*4 +0x02000000,0xe80b); +reg_write( DDR_REG_BASE +0x53909*4 +0x02000000,0xf87e); +reg_write( DDR_REG_BASE +0x5390a*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5390b*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5390c*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5390d*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5390e*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5390f*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53910*4 +0x02000000,0x8b6); +reg_write( DDR_REG_BASE +0x53911*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53912*4 +0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x53913*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53914*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53915*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53916*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x53917*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53918*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53919*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5391a*4 +0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x5391b*4 +0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x5391c*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5391d*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x5391e*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5391f*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53920*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53921*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53922*4 +0x02000000,0x892); +reg_write( DDR_REG_BASE +0x53923*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53924*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53925*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53926*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53927*4 +0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x53928*4 +0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x53929*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x5392a*4 +0x02000000,0x2353); +reg_write( DDR_REG_BASE +0x5392b*4 +0x02000000,0x315b); +reg_write( DDR_REG_BASE +0x5392c*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5392d*4 +0x02000000,0xf869); +reg_write( DDR_REG_BASE +0x5392e*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5392f*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53930*4 +0x02000000,0x876); +reg_write( DDR_REG_BASE +0x53931*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53932*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x53933*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x53934*4 +0x02000000,0xf868); +reg_write( DDR_REG_BASE +0x53935*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x53936*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53937*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x53938*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53939*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5393a*4 +0x02000000,0x78dd); +reg_write( DDR_REG_BASE +0x5393b*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x5393c*4 +0x02000000,0x800); +reg_write( DDR_REG_BASE +0x5393d*4 +0x02000000,0x2045); +reg_write( DDR_REG_BASE +0x5393e*4 +0x02000000,0x580); +reg_write( DDR_REG_BASE +0x5393f*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x53940*4 +0x02000000,0x856); +reg_write( DDR_REG_BASE +0x53941*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53942*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53943*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53944*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53945*4 +0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x53946*4 +0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x53947*4 +0x02000000,0xbec5); +reg_write( DDR_REG_BASE +0x53948*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53949*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5394a*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5394b*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5394c*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5394d*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5394e*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x5394f*4 +0x02000000,0x83a); +reg_write( DDR_REG_BASE +0x53950*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53951*4 +0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x53952*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53953*4 +0x02000000,0xe819); +reg_write( DDR_REG_BASE +0x53954*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53955*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53956*4 +0x02000000,0x2710); +reg_write( DDR_REG_BASE +0x53957*4 +0x02000000,0xe52); +reg_write( DDR_REG_BASE +0x53958*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x53959*4 +0x02000000,0xd90a); +reg_write( DDR_REG_BASE +0x5395a*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5395b*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5395c*4 +0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x5395d*4 +0x02000000,0x7e0f); +reg_write( DDR_REG_BASE +0x5395e*4 +0x02000000,0xf850); +reg_write( DDR_REG_BASE +0x5395f*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x53960*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53961*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53962*4 +0x02000000,0x812); +reg_write( DDR_REG_BASE +0x53963*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53964*4 +0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x53965*4 +0x02000000,0xf84d); +reg_write( DDR_REG_BASE +0x53966*4 +0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x53967*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x53968*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53969*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5396a*4 +0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x5396b*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5396c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5396d*4 +0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x5396e*4 +0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x5396f*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x53970*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53971*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x53972*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53973*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53974*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53975*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53976*4 +0x02000000,0xdb18); +reg_write( DDR_REG_BASE +0x53977*4 +0x02000000,0xfea); +reg_write( DDR_REG_BASE +0x53978*4 +0x02000000,0xfc8f); +reg_write( DDR_REG_BASE +0x53979*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5397a*4 +0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x5397b*4 +0x02000000,0x90f); +reg_write( DDR_REG_BASE +0x5397c*4 +0x02000000,0x110); +reg_write( DDR_REG_BASE +0x5397d*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5397e*4 +0x02000000,0x817); +reg_write( DDR_REG_BASE +0x5397f*4 +0x02000000,0x2d1); +reg_write( DDR_REG_BASE +0x53980*4 +0x02000000,0xe909); +reg_write( DDR_REG_BASE +0x53981*4 +0x02000000,0xeca); +reg_write( DDR_REG_BASE +0x53982*4 +0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x53983*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53984*4 +0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x53985*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53986*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53987*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53988*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53989*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5398a*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5398b*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x5398c*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5398d*4 +0x02000000,0xe08c); +reg_write( DDR_REG_BASE +0x5398e*4 +0x02000000,0x690); +reg_write( DDR_REG_BASE +0x5398f*4 +0x02000000,0xffc5); +reg_write( DDR_REG_BASE +0x53990*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x53991*4 +0x02000000,0x8cf); +reg_write( DDR_REG_BASE +0x53992*4 +0x02000000,0x30); +reg_write( DDR_REG_BASE +0x53993*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x53994*4 +0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x53995*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53996*4 +0x02000000,0xa00); +reg_write( DDR_REG_BASE +0x53997*4 +0x02000000,0xed2); +reg_write( DDR_REG_BASE +0x53998*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53999*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x5399a*4 +0x02000000,0xeee); +reg_write( DDR_REG_BASE +0x5399b*4 +0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x5399c*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x5399d*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5399e*4 +0x02000000,0x6e1); +reg_write( DDR_REG_BASE +0x5399f*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x539a0*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x539a1*4 +0x02000000,0x234a); +reg_write( DDR_REG_BASE +0x539a2*4 +0x02000000,0x3800); +reg_write( DDR_REG_BASE +0x539a3*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x539a4*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x539a5*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x539a6*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x539a7*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x539a8*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x539a9*4 +0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x539aa*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x539ab*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x539ac*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x539ad*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x539ae*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x539af*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x539b0*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x539b1*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x539b2*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x539b3*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x539b4*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x539b5*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x539b6*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x539b7*4 +0x02000000,0xf6a); +reg_write( DDR_REG_BASE +0x539b8*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x539b9*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x539ba*4 +0x02000000,0x33c1); +reg_write( DDR_REG_BASE +0x539bb*4 +0x02000000,0xe56); +reg_write( DDR_REG_BASE +0x539bc*4 +0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x539bd*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x539be*4 +0x02000000,0xf1a); +reg_write( DDR_REG_BASE +0x539bf*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x539c0*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x539c1*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x539c2*4 +0x02000000,0xf); +reg_write( DDR_REG_BASE +0x539c3*4 +0x02000000,0x4240); +reg_write( DDR_REG_BASE +0x539c4*4 +0x02000000,0xd56); +reg_write( DDR_REG_BASE +0x539c5*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x539c6*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x539c7*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x539c8*4 +0x02000000,0xe6e); +reg_write( DDR_REG_BASE +0x539c9*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x539ca*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x539cb*4 +0x02000000,0xe8e); +reg_write( DDR_REG_BASE +0x539cc*4 +0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x539cd*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x539ce*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x539cf*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x539d0*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x539d1*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x539d2*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x539d3*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x539d4*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x539d5*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x539d6*4 +0x02000000,0xf2a); +reg_write( DDR_REG_BASE +0x539d7*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x539d8*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x539d9*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x539da*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x539db*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x539dc*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x539dd*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x539de*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x539df*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x539e0*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x539e1*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x539e2*4 +0x02000000,0xf12); +reg_write( DDR_REG_BASE +0x539e3*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x539e4*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x539e5*4 +0x02000000,0x3441); +reg_write( DDR_REG_BASE +0x539e6*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x539e7*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x539e8*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x539e9*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x539ea*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x539eb*4 +0x02000000,0xdb10); +reg_write( DDR_REG_BASE +0x539ec*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x539ed*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x539ee*4 +0x02000000,0xefa); +reg_write( DDR_REG_BASE +0x539ef*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x539f0*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x539f1*4 +0x02000000,0xdea); +reg_write( DDR_REG_BASE +0x539f2*4 +0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x539f3*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x539f4*4 +0x02000000,0xeae); +reg_write( DDR_REG_BASE +0x539f5*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x539f6*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x539f7*4 +0x02000000,0xc06); +reg_write( DDR_REG_BASE +0x539f8*4 +0x02000000,0xfd0f); +reg_write( DDR_REG_BASE +0x539f9*4 +0x02000000,0xc0ac); +reg_write( DDR_REG_BASE +0x539fa*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x539fb*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x539fc*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x539fd*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x539fe*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x539ff*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53a00*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53a01*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x53a02*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x53a03*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x53a04*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53a05*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53a06*4 +0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x53a07*4 +0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x53a08*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53a09*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53a0a*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x53a0b*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x53a0c*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x53a0d*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53a0e*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53a0f*4 +0x02000000,0xc1a9); +reg_write( DDR_REG_BASE +0x53a10*4 +0x02000000,0xc145); +reg_write( DDR_REG_BASE +0x53a11*4 +0x02000000,0xd958); +reg_write( DDR_REG_BASE +0x53a12*4 +0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x53a13*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x53a14*4 +0x02000000,0x8900); +reg_write( DDR_REG_BASE +0x53a15*4 +0x02000000,0x11cd); +reg_write( DDR_REG_BASE +0x53a16*4 +0x02000000,0x808f); +reg_write( DDR_REG_BASE +0x53a17*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x53a18*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x53a19*4 +0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x53a1a*4 +0x02000000,0x71cd); +reg_write( DDR_REG_BASE +0x53a1b*4 +0x02000000,0xc343); +reg_write( DDR_REG_BASE +0x53a1c*4 +0x02000000,0xc244); +reg_write( DDR_REG_BASE +0x53a1d*4 +0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x53a1e*4 +0x02000000,0xf058); +reg_write( DDR_REG_BASE +0x53a1f*4 +0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x53a20*4 +0x02000000,0x17c1); +reg_write( DDR_REG_BASE +0x53a21*4 +0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x53a22*4 +0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x53a23*4 +0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x53a24*4 +0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x53a25*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x53a26*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53a27*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53a28*4 +0x02000000,0xf04b); +reg_write( DDR_REG_BASE +0x53a29*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x53a2a*4 +0x02000000,0xc202); +reg_write( DDR_REG_BASE +0x53a2b*4 +0x02000000,0xc108); +reg_write( DDR_REG_BASE +0x53a2c*4 +0x02000000,0x7077); +reg_write( DDR_REG_BASE +0x53a2d*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x53a2e*4 +0x02000000,0x3c1); +reg_write( DDR_REG_BASE +0x53a2f*4 +0x02000000,0x7944); +reg_write( DDR_REG_BASE +0x53a30*4 +0x02000000,0x790b); +reg_write( DDR_REG_BASE +0x53a31*4 +0x02000000,0xf242); +reg_write( DDR_REG_BASE +0x53a32*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x53a33*4 +0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x53a34*4 +0x02000000,0x37c1); +reg_write( DDR_REG_BASE +0x53a35*4 +0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x53a36*4 +0x02000000,0x3007); +reg_write( DDR_REG_BASE +0x53a37*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53a38*4 +0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x53a39*4 +0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x53a3a*4 +0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x53a3b*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x53a3c*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53a3d*4 +0x02000000,0xe9e); +reg_write( DDR_REG_BASE +0x53a3e*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53a3f*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x53a40*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53a41*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53a42*4 +0x02000000,0x6e0); +reg_write( DDR_REG_BASE +0x53a43*4 +0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x53a44*4 +0x02000000,0xe81c); +reg_write( DDR_REG_BASE +0x53a45*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53a46*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53a47*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53a48*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53a49*4 +0x02000000,0x831); +reg_write( DDR_REG_BASE +0x53a4a*4 +0x02000000,0xdf); +reg_write( DDR_REG_BASE +0x53a4b*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x53a4c*4 +0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x53a4d*4 +0x02000000,0x3c81); +reg_write( DDR_REG_BASE +0x53a4e*4 +0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x53a4f*4 +0x02000000,0x3102); +reg_write( DDR_REG_BASE +0x53a50*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x53a51*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53a52*4 +0x02000000,0xc304); +reg_write( DDR_REG_BASE +0x53a53*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x53a54*4 +0x02000000,0x3001); +reg_write( DDR_REG_BASE +0x53a55*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x53a56*4 +0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x53a57*4 +0x02000000,0x1640); +reg_write( DDR_REG_BASE +0x53a58*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x53a59*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x53a5a*4 +0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x53a5b*4 +0x02000000,0xc205); +reg_write( DDR_REG_BASE +0x53a5c*4 +0x02000000,0xcce); +reg_write( DDR_REG_BASE +0x53a5d*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x53a5e*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x53a5f*4 +0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x53a60*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x53a61*4 +0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x53a62*4 +0x02000000,0x3c81); +reg_write( DDR_REG_BASE +0x53a63*4 +0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x53a64*4 +0x02000000,0x3102); +reg_write( DDR_REG_BASE +0x53a65*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x53a66*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53a67*4 +0x02000000,0xc304); +reg_write( DDR_REG_BASE +0x53a68*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x53a69*4 +0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x53a6a*4 +0x02000000,0x1640); +reg_write( DDR_REG_BASE +0x53a6b*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x53a6c*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x53a6d*4 +0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x53a6e*4 +0x02000000,0xc205); +reg_write( DDR_REG_BASE +0x53a6f*4 +0x02000000,0xb62); +reg_write( DDR_REG_BASE +0x53a70*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x53a71*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x53a72*4 +0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x53a73*4 +0x02000000,0xb6f); +reg_write( DDR_REG_BASE +0x53a74*4 +0x02000000,0xb094); +reg_write( DDR_REG_BASE +0x53a75*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x53a76*4 +0x02000000,0xd53); +reg_write( DDR_REG_BASE +0x53a77*4 +0x02000000,0x90b4); +reg_write( DDR_REG_BASE +0x53a78*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53a79*4 +0x02000000,0xe26); +reg_write( DDR_REG_BASE +0x53a7a*4 +0x02000000,0xfcef); +reg_write( DDR_REG_BASE +0x53a7b*4 +0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x53a7c*4 +0x02000000,0xc0a9); +reg_write( DDR_REG_BASE +0x53a7d*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x53a7e*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x53a7f*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53a80*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x53a81*4 +0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x53a82*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53a83*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53a84*4 +0x02000000,0x8b80); +reg_write( DDR_REG_BASE +0x53a85*4 +0x02000000,0x8ba1); +reg_write( DDR_REG_BASE +0x53a86*4 +0x02000000,0x245f); +reg_write( DDR_REG_BASE +0x53a87*4 +0x02000000,0x1482); +reg_write( DDR_REG_BASE +0x53a88*4 +0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x53a89*4 +0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x53a8a*4 +0x02000000,0x921); +reg_write( DDR_REG_BASE +0x53a8b*4 +0x02000000,0xee); +reg_write( DDR_REG_BASE +0x53a8c*4 +0x02000000,0x4260); +reg_write( DDR_REG_BASE +0x53a8d*4 +0x02000000,0x229a); +reg_write( DDR_REG_BASE +0x53a8e*4 +0x02000000,0x8); +reg_write( DDR_REG_BASE +0x53a8f*4 +0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x53a90*4 +0x02000000,0x1f8f); +reg_write( DDR_REG_BASE +0x53a91*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a92*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x53a93*4 +0x02000000,0x7ae5); +reg_write( DDR_REG_BASE +0x53a94*4 +0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x53a95*4 +0x02000000,0xf8f); +reg_write( DDR_REG_BASE +0x53a96*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x53a97*4 +0x02000000,0x64); +reg_write( DDR_REG_BASE +0x53a98*4 +0x02000000,0x9040); +reg_write( DDR_REG_BASE +0x53a99*4 +0x02000000,0xb740); +reg_write( DDR_REG_BASE +0x53a9a*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x53a9b*4 +0x02000000,0x7204); +reg_write( DDR_REG_BASE +0x53a9c*4 +0x02000000,0xbdd); +reg_write( DDR_REG_BASE +0x53a9d*4 +0x02000000,0x8254); +reg_write( DDR_REG_BASE +0x53a9e*4 +0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x53a9f*4 +0x02000000,0x7e8f); +reg_write( DDR_REG_BASE +0x53aa0*4 +0x02000000,0xdf9); +reg_write( DDR_REG_BASE +0x53aa1*4 +0x02000000,0x93a5); +reg_write( DDR_REG_BASE +0x53aa2*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x53aa3*4 +0x02000000,0xc7e); +reg_write( DDR_REG_BASE +0x53aa4*4 +0x02000000,0xfe4f); +reg_write( DDR_REG_BASE +0x53aa5*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53aa6*4 +0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x53aa7*4 +0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x53aa8*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53aa9*4 +0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x53aaa*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53aab*4 +0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x53aac*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x53aad*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x53aae*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x53aaf*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53ab0*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x53ab1*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53ab2*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53ab3*4 +0x02000000,0x7b45); +reg_write( DDR_REG_BASE +0x53ab4*4 +0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x53ab5*4 +0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x53ab6*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x53ab7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ab8*4 +0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x53ab9*4 +0x02000000,0x1301); +reg_write( DDR_REG_BASE +0x53aba*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x53abb*4 +0x02000000,0x6c02); +reg_write( DDR_REG_BASE +0x53abc*4 +0x02000000,0x78a5); +reg_write( DDR_REG_BASE +0x53abd*4 +0x02000000,0xb060); +reg_write( DDR_REG_BASE +0x53abe*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53abf*4 +0x02000000,0xd1a); +reg_write( DDR_REG_BASE +0x53ac0*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53ac1*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53ac2*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x53ac3*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x53ac4*4 +0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x53ac5*4 +0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x53ac6*4 +0x02000000,0x3040); +reg_write( DDR_REG_BASE +0x53ac7*4 +0x02000000,0x4308); +reg_write( DDR_REG_BASE +0x53ac8*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x53ac9*4 +0x02000000,0xf024); +reg_write( DDR_REG_BASE +0x53aca*4 +0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x53acb*4 +0x02000000,0x1182); +reg_write( DDR_REG_BASE +0x53acc*4 +0x02000000,0x7261); +reg_write( DDR_REG_BASE +0x53acd*4 +0x02000000,0x8a01); +reg_write( DDR_REG_BASE +0x53ace*4 +0x02000000,0x8a60); +reg_write( DDR_REG_BASE +0x53acf*4 +0x02000000,0x8a22); +reg_write( DDR_REG_BASE +0x53ad0*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x53ad1*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53ad2*4 +0x02000000,0x7b05); +reg_write( DDR_REG_BASE +0x53ad3*4 +0x02000000,0x8a03); +reg_write( DDR_REG_BASE +0x53ad4*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x53ad5*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53ad6*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x53ad7*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x53ad8*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53ad9*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53ada*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53adb*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53adc*4 +0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x53add*4 +0x02000000,0x8a05); +reg_write( DDR_REG_BASE +0x53ade*4 +0x02000000,0x8a64); +reg_write( DDR_REG_BASE +0x53adf*4 +0x02000000,0x7734); +reg_write( DDR_REG_BASE +0x53ae0*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x53ae1*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53ae2*4 +0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x53ae3*4 +0x02000000,0xf207); +reg_write( DDR_REG_BASE +0x53ae4*4 +0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x53ae5*4 +0x02000000,0xb99c); +reg_write( DDR_REG_BASE +0x53ae6*4 +0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x53ae7*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x53ae8*4 +0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x53ae9*4 +0x02000000,0xab6); +reg_write( DDR_REG_BASE +0x53aea*4 +0x02000000,0xfe0f); +reg_write( DDR_REG_BASE +0x53aeb*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x53aec*4 +0x02000000,0x2e45); +reg_write( DDR_REG_BASE +0x53aed*4 +0x02000000,0x3180); +reg_write( DDR_REG_BASE +0x53aee*4 +0x02000000,0xdb9); +reg_write( DDR_REG_BASE +0x53aef*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x53af0*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x53af1*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x53af2*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x53af3*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53af4*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53af5*4 +0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x53af6*4 +0x02000000,0x4718); +reg_write( DDR_REG_BASE +0x53af7*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53af8*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53af9*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53afa*4 +0x02000000,0x88c0); +reg_write( DDR_REG_BASE +0x53afb*4 +0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x53afc*4 +0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x53afd*4 +0x02000000,0xea04); +reg_write( DDR_REG_BASE +0x53afe*4 +0x02000000,0x79db); +reg_write( DDR_REG_BASE +0x53aff*4 +0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x53b00*4 +0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x53b01*4 +0x02000000,0x1241); +reg_write( DDR_REG_BASE +0x53b02*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x53b03*4 +0x02000000,0x9e); +reg_write( DDR_REG_BASE +0x53b04*4 +0x02000000,0x7054); +reg_write( DDR_REG_BASE +0x53b05*4 +0x02000000,0xdd08); +reg_write( DDR_REG_BASE +0x53b06*4 +0x02000000,0x25ca); +reg_write( DDR_REG_BASE +0x53b07*4 +0x02000000,0x1062); +reg_write( DDR_REG_BASE +0x53b08*4 +0x02000000,0xf039); +reg_write( DDR_REG_BASE +0x53b09*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x53b0a*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x53b0b*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53b0c*4 +0x02000000,0xc300); +reg_write( DDR_REG_BASE +0x53b0d*4 +0x02000000,0x23f5); +reg_write( DDR_REG_BASE +0x53b0e*4 +0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x53b0f*4 +0x02000000,0xeb13); +reg_write( DDR_REG_BASE +0x53b10*4 +0x02000000,0x7c5c); +reg_write( DDR_REG_BASE +0x53b11*4 +0x02000000,0x7c9c); +reg_write( DDR_REG_BASE +0x53b12*4 +0x02000000,0x7c9c); +reg_write( DDR_REG_BASE +0x53b13*4 +0x02000000,0x7c9c); +reg_write( DDR_REG_BASE +0x53b14*4 +0x02000000,0x224a); +reg_write( DDR_REG_BASE +0x53b15*4 +0x02000000,0x16c0); +reg_write( DDR_REG_BASE +0x53b16*4 +0x02000000,0x2a44); +reg_write( DDR_REG_BASE +0x53b17*4 +0x02000000,0x803); +reg_write( DDR_REG_BASE +0x53b18*4 +0x02000000,0x2242); +reg_write( DDR_REG_BASE +0x53b19*4 +0x02000000,0x104a); +reg_write( DDR_REG_BASE +0x53b1a*4 +0x02000000,0xafd); +reg_write( DDR_REG_BASE +0x53b1b*4 +0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x53b1c*4 +0x02000000,0x7c9d); +reg_write( DDR_REG_BASE +0x53b1d*4 +0x02000000,0x629a); +reg_write( DDR_REG_BASE +0x53b1e*4 +0x02000000,0xbac4); +reg_write( DDR_REG_BASE +0x53b1f*4 +0x02000000,0x4a94); +reg_write( DDR_REG_BASE +0x53b20*4 +0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x53b21*4 +0x02000000,0x248a); +reg_write( DDR_REG_BASE +0x53b22*4 +0x02000000,0x1fcf); +reg_write( DDR_REG_BASE +0x53b23*4 +0x02000000,0x7c44); +reg_write( DDR_REG_BASE +0x53b24*4 +0x02000000,0x2204); +reg_write( DDR_REG_BASE +0x53b25*4 +0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x53b26*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b27*4 +0x02000000,0xfc00); +reg_write( DDR_REG_BASE +0x53b28*4 +0x02000000,0xda0a); +reg_write( DDR_REG_BASE +0x53b29*4 +0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x53b2a*4 +0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x53b2b*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x53b2c*4 +0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x53b2d*4 +0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x53b2e*4 +0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x53b2f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b30*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x53b31*4 +0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x53b32*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53b33*4 +0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x53b34*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x53b35*4 +0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x53b36*4 +0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x53b37*4 +0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x53b38*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53b39*4 +0x02000000,0xb891); +reg_write( DDR_REG_BASE +0x53b3a*4 +0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x53b3b*4 +0x02000000,0x7b85); +reg_write( DDR_REG_BASE +0x53b3c*4 +0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x53b3d*4 +0x02000000,0xb060); +reg_write( DDR_REG_BASE +0x53b3e*4 +0x02000000,0xd97); +reg_write( DDR_REG_BASE +0x53b3f*4 +0x02000000,0x93c5); +reg_write( DDR_REG_BASE +0x53b40*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x53b41*4 +0x02000000,0xefd); +reg_write( DDR_REG_BASE +0x53b42*4 +0x02000000,0xb3a5); +reg_write( DDR_REG_BASE +0x53b43*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x53b44*4 +0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x53b45*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x53b46*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x53b47*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53b48*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x53b49*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53b4a*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53b4b*4 +0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x53b4c*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x53b4d*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53b4e*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53b4f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53b50*4 +0x02000000,0x1b); +reg_write( DDR_REG_BASE +0x53b51*4 +0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x53b52*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x53b53*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x53b54*4 +0x02000000,0x4568); +reg_write( DDR_REG_BASE +0x53b55*4 +0x02000000,0x7dc0); +reg_write( DDR_REG_BASE +0x53b56*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x53b57*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53b58*4 +0x02000000,0x688); +reg_write( DDR_REG_BASE +0x53b59*4 +0x02000000,0x82f); +reg_write( DDR_REG_BASE +0x53b5a*4 +0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x53b5b*4 +0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x53b5c*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53b5d*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53b5e*4 +0x02000000,0x7d3); +reg_write( DDR_REG_BASE +0x53b5f*4 +0x02000000,0x8904); +reg_write( DDR_REG_BASE +0x53b60*4 +0x02000000,0xe80f); +reg_write( DDR_REG_BASE +0x53b61*4 +0x02000000,0x8900); +reg_write( DDR_REG_BASE +0x53b62*4 +0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x53b63*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53b64*4 +0x02000000,0x6ba); +reg_write( DDR_REG_BASE +0x53b65*4 +0x02000000,0xaa00); +reg_write( DDR_REG_BASE +0x53b66*4 +0x02000000,0x8901); +reg_write( DDR_REG_BASE +0x53b67*4 +0x02000000,0xaa19); +reg_write( DDR_REG_BASE +0x53b68*4 +0x02000000,0x8902); +reg_write( DDR_REG_BASE +0x53b69*4 +0x02000000,0xac00); +reg_write( DDR_REG_BASE +0x53b6a*4 +0x02000000,0x8903); +reg_write( DDR_REG_BASE +0x53b6b*4 +0x02000000,0xac19); +reg_write( DDR_REG_BASE +0x53b6c*4 +0x02000000,0x2350); +reg_write( DDR_REG_BASE +0x53b6d*4 +0x02000000,0x300); +reg_write( DDR_REG_BASE +0x53b6e*4 +0x02000000,0x7d04); +reg_write( DDR_REG_BASE +0x53b6f*4 +0x02000000,0x2242); +reg_write( DDR_REG_BASE +0x53b70*4 +0x02000000,0x30e); +reg_write( DDR_REG_BASE +0x53b71*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53b72*4 +0x02000000,0xf06); +reg_write( DDR_REG_BASE +0x53b73*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x53b74*4 +0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x53b75*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53b76*4 +0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x53b77*4 +0x02000000,0xcbe); +reg_write( DDR_REG_BASE +0x53b78*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x53b79*4 +0x02000000,0xda40); +reg_write( DDR_REG_BASE +0x53b7a*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53b7b*4 +0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x53b7c*4 +0x02000000,0xe8e); +reg_write( DDR_REG_BASE +0x53b7d*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53b7e*4 +0x02000000,0xda7f); +reg_write( DDR_REG_BASE +0x53b7f*4 +0x02000000,0xdfff); +reg_write( DDR_REG_BASE +0x53b80*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53b81*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53b82*4 +0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x53b83*4 +0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x53b84*4 +0x02000000,0xd12); +reg_write( DDR_REG_BASE +0x53b85*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x53b86*4 +0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53b87*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53b88*4 +0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x53b89*4 +0x02000000,0xc9a); +reg_write( DDR_REG_BASE +0x53b8a*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x53b8b*4 +0x02000000,0xda80); +reg_write( DDR_REG_BASE +0x53b8c*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53b8d*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53b8e*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x53b8f*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x53b90*4 +0x02000000,0xdfff); +reg_write( DDR_REG_BASE +0x53b91*4 +0x02000000,0x776c); +reg_write( DDR_REG_BASE +0x53b92*4 +0x02000000,0xcf6); +reg_write( DDR_REG_BASE +0x53b93*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x53b94*4 +0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53b95*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x53b96*4 +0x02000000,0xabe); +reg_write( DDR_REG_BASE +0x53b97*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x53b98*4 +0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x53b99*4 +0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x53b9a*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x53b9b*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x53b9c*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53b9d*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x53b9e*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x53b9f*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53ba0*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53ba1*4 +0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x53ba2*4 +0x02000000,0x3403); +reg_write( DDR_REG_BASE +0x53ba3*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53ba4*4 +0x02000000,0xf22); +reg_write( DDR_REG_BASE +0x53ba5*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53ba6*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x53ba7*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53ba8*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53ba9*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53baa*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53bab*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53bac*4 +0x02000000,0xc22); +reg_write( DDR_REG_BASE +0x53bad*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x53bae*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x53baf*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x53bb0*4 +0x02000000,0xe0e); +reg_write( DDR_REG_BASE +0x53bb1*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53bb2*4 +0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x53bb3*4 +0x02000000,0x3bc1); +reg_write( DDR_REG_BASE +0x53bb4*4 +0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x53bb5*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x53bb6*4 +0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x53bb7*4 +0x02000000,0x17ce); +reg_write( DDR_REG_BASE +0x53bb8*4 +0x02000000,0xee05); +reg_write( DDR_REG_BASE +0x53bb9*4 +0x02000000,0xbe61); +reg_write( DDR_REG_BASE +0x53bba*4 +0x02000000,0xeff); +reg_write( DDR_REG_BASE +0x53bbb*4 +0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x53bbc*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53bbd*4 +0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x53bbe*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x53bbf*4 +0x02000000,0x200f); +reg_write( DDR_REG_BASE +0x53bc0*4 +0x02000000,0x340); +reg_write( DDR_REG_BASE +0x53bc1*4 +0x02000000,0xd7e); +reg_write( DDR_REG_BASE +0x53bc2*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53bc3*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x53bc4*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53bc5*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53bc6*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53bc7*4 +0x02000000,0xfe64); +reg_write( DDR_REG_BASE +0x53bc8*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53bc9*4 +0x02000000,0x7044); +reg_write( DDR_REG_BASE +0x53bca*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53bcb*4 +0x02000000,0xfe64); +reg_write( DDR_REG_BASE +0x53bcc*4 +0x02000000,0x1882); +reg_write( DDR_REG_BASE +0x53bcd*4 +0x02000000,0x5c); +reg_write( DDR_REG_BASE +0x53bce*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53bcf*4 +0x02000000,0x808); +reg_write( DDR_REG_BASE +0x53bd0*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53bd1*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x53bd2*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53bd3*4 +0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x53bd4*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53bd5*4 +0x02000000,0x73c4); +reg_write( DDR_REG_BASE +0x53bd6*4 +0x02000000,0x900f); +reg_write( DDR_REG_BASE +0x53bd7*4 +0x02000000,0xe0c0); +reg_write( DDR_REG_BASE +0x53bd8*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53bd9*4 +0x02000000,0x7044); +reg_write( DDR_REG_BASE +0x53bda*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53bdb*4 +0x02000000,0xfe64); +reg_write( DDR_REG_BASE +0x53bdc*4 +0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x53bdd*4 +0x02000000,0x6941); +reg_write( DDR_REG_BASE +0x53bde*4 +0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x53bdf*4 +0x02000000,0x8); +reg_write( DDR_REG_BASE +0x53be0*4 +0x02000000,0x43e1); +reg_write( DDR_REG_BASE +0x53be1*4 +0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x53be2*4 +0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x53be3*4 +0x02000000,0x801); +reg_write( DDR_REG_BASE +0x53be4*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x53be5*4 +0x02000000,0x7b7b); +reg_write( DDR_REG_BASE +0x53be6*4 +0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x53be7*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53be8*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53be9*4 +0x02000000,0xe0c4); +reg_write( DDR_REG_BASE +0x53bea*4 +0x02000000,0xb060); +reg_write( DDR_REG_BASE +0x53beb*4 +0x02000000,0x4140); +reg_write( DDR_REG_BASE +0x53bec*4 +0x02000000,0x9e3); +reg_write( DDR_REG_BASE +0x53bed*4 +0x02000000,0x8234); +reg_write( DDR_REG_BASE +0x53bee*4 +0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x53bef*4 +0x02000000,0x7c0); +reg_write( DDR_REG_BASE +0x53bf0*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x53bf1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bf2*4 +0x02000000,0xaaaa); +reg_write( DDR_REG_BASE +0x53bf3*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53bf4*4 +0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x53bf5*4 +0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x53bf6*4 +0x02000000,0x43a1); +reg_write( DDR_REG_BASE +0x53bf7*4 +0x02000000,0x98e); +reg_write( DDR_REG_BASE +0x53bf8*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53bf9*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53bfa*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53bfb*4 +0x02000000,0xe2a); +reg_write( DDR_REG_BASE +0x53bfc*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53bfd*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x53bfe*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53bff*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c00*4 +0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x53c01*4 +0x02000000,0xe82); +reg_write( DDR_REG_BASE +0x53c02*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x53c03*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53c04*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x53c05*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53c06*4 +0x02000000,0xe174); +reg_write( DDR_REG_BASE +0x53c07*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53c08*4 +0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x53c09*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53c0a*4 +0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x53c0b*4 +0x02000000,0xb601); +reg_write( DDR_REG_BASE +0x53c0c*4 +0x02000000,0x43db); +reg_write( DDR_REG_BASE +0x53c0d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c0e*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x53c0f*4 +0x02000000,0xd830); +reg_write( DDR_REG_BASE +0x53c10*4 +0x02000000,0x1e58); +reg_write( DDR_REG_BASE +0x53c11*4 +0x02000000,0x96dc); +reg_write( DDR_REG_BASE +0x53c12*4 +0x02000000,0x1e5e); +reg_write( DDR_REG_BASE +0x53c13*4 +0x02000000,0x93dc); +reg_write( DDR_REG_BASE +0x53c14*4 +0x02000000,0xa6e); +reg_write( DDR_REG_BASE +0x53c15*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53c16*4 +0x02000000,0x1e57); +reg_write( DDR_REG_BASE +0x53c17*4 +0x02000000,0x93dc); +reg_write( DDR_REG_BASE +0x53c18*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53c19*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53c1a*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53c1b*4 +0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x53c1c*4 +0x02000000,0x942); +reg_write( DDR_REG_BASE +0x53c1d*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53c1e*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x53c1f*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x53c20*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x53c21*4 +0x02000000,0xa56); +reg_write( DDR_REG_BASE +0x53c22*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53c23*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53c24*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53c25*4 +0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x53c26*4 +0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x53c27*4 +0x02000000,0x43a1); +reg_write( DDR_REG_BASE +0x53c28*4 +0x02000000,0x92a); +reg_write( DDR_REG_BASE +0x53c29*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53c2a*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53c2b*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53c2c*4 +0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x53c2d*4 +0x02000000,0xb601); +reg_write( DDR_REG_BASE +0x53c2e*4 +0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x53c2f*4 +0x02000000,0x1e58); +reg_write( DDR_REG_BASE +0x53c30*4 +0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x53c31*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53c32*4 +0x02000000,0x844); +reg_write( DDR_REG_BASE +0x53c33*4 +0x02000000,0x1e5e); +reg_write( DDR_REG_BASE +0x53c34*4 +0x02000000,0x93dc); +reg_write( DDR_REG_BASE +0x53c35*4 +0x02000000,0x1e57); +reg_write( DDR_REG_BASE +0x53c36*4 +0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x53c37*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53c38*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c39*4 +0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x53c3a*4 +0x02000000,0xe0e); +reg_write( DDR_REG_BASE +0x53c3b*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x53c3c*4 +0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x53c3d*4 +0x02000000,0xd830); +reg_write( DDR_REG_BASE +0x53c3e*4 +0x02000000,0xa1a); +reg_write( DDR_REG_BASE +0x53c3f*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53c40*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53c41*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x53c42*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53c43*4 +0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x53c44*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53c45*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53c46*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x53c47*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53c48*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x53c49*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c4a*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x53c4b*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53c4c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53c4d*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53c4e*4 +0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x53c4f*4 +0x02000000,0xf022); +reg_write( DDR_REG_BASE +0x53c50*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53c51*4 +0x02000000,0x2016); +reg_write( DDR_REG_BASE +0x53c52*4 +0x02000000,0x83); +reg_write( DDR_REG_BASE +0x53c53*4 +0x02000000,0xf01a); +reg_write( DDR_REG_BASE +0x53c54*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x53c55*4 +0x02000000,0x8); +reg_write( DDR_REG_BASE +0x53c56*4 +0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x53c57*4 +0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x53c58*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c59*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x53c5a*4 +0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x53c5b*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53c5c*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53c5d*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x53c5e*4 +0x02000000,0x64); +reg_write( DDR_REG_BASE +0x53c5f*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x53c60*4 +0x02000000,0x7c1d); +reg_write( DDR_REG_BASE +0x53c61*4 +0x02000000,0x7c9d); +reg_write( DDR_REG_BASE +0x53c62*4 +0x02000000,0x7c9d); +reg_write( DDR_REG_BASE +0x53c63*4 +0x02000000,0x7c9d); +reg_write( DDR_REG_BASE +0x53c64*4 +0x02000000,0x7c9d); +reg_write( DDR_REG_BASE +0x53c65*4 +0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x53c66*4 +0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x53c67*4 +0x02000000,0xc087); +reg_write( DDR_REG_BASE +0x53c68*4 +0x02000000,0x7874); +reg_write( DDR_REG_BASE +0x53c69*4 +0x02000000,0xb080); +reg_write( DDR_REG_BASE +0x53c6a*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x53c6b*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x53c6c*4 +0x02000000,0x8d1); +reg_write( DDR_REG_BASE +0x53c6d*4 +0x02000000,0x8234); +reg_write( DDR_REG_BASE +0x53c6e*4 +0x02000000,0x68e1); +reg_write( DDR_REG_BASE +0x53c6f*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x53c70*4 +0x02000000,0x9c1); +reg_write( DDR_REG_BASE +0x53c71*4 +0x02000000,0x80a5); +reg_write( DDR_REG_BASE +0x53c72*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53c73*4 +0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x53c74*4 +0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x53c75*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x53c76*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x53c77*4 +0x02000000,0xb6e1); +reg_write( DDR_REG_BASE +0x53c78*4 +0x02000000,0x1e58); +reg_write( DDR_REG_BASE +0x53c79*4 +0x02000000,0x96dc); +reg_write( DDR_REG_BASE +0x53c7a*4 +0x02000000,0x1e5e); +reg_write( DDR_REG_BASE +0x53c7b*4 +0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x53c7c*4 +0x02000000,0x1e57); +reg_write( DDR_REG_BASE +0x53c7d*4 +0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x53c7e*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53c7f*4 +0x02000000,0x7d0); +reg_write( DDR_REG_BASE +0x53c80*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53c81*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x53c82*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53c83*4 +0x02000000,0xfe64); +reg_write( DDR_REG_BASE +0x53c84*4 +0x02000000,0xd830); +reg_write( DDR_REG_BASE +0x53c85*4 +0x02000000,0x98e); +reg_write( DDR_REG_BASE +0x53c86*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53c87*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53c88*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53c89*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53c8a*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53c8b*4 +0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x53c8c*4 +0x02000000,0x862); +reg_write( DDR_REG_BASE +0x53c8d*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53c8e*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x53c8f*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x53c90*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x53c91*4 +0x02000000,0x976); +reg_write( DDR_REG_BASE +0x53c92*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53c93*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53c94*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53c95*4 +0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x53c96*4 +0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x53c97*4 +0x02000000,0x43a1); +reg_write( DDR_REG_BASE +0x53c98*4 +0x02000000,0x84a); +reg_write( DDR_REG_BASE +0x53c99*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53c9a*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53c9b*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53c9c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c9d*4 +0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x53c9e*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53c9f*4 +0x02000000,0xb6e0); +reg_write( DDR_REG_BASE +0x53ca0*4 +0x02000000,0xd42); +reg_write( DDR_REG_BASE +0x53ca1*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x53ca2*4 +0x02000000,0xb6e1); +reg_write( DDR_REG_BASE +0x53ca3*4 +0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x53ca4*4 +0x02000000,0x1e58); +reg_write( DDR_REG_BASE +0x53ca5*4 +0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x53ca6*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x53ca7*4 +0x02000000,0x1e5e); +reg_write( DDR_REG_BASE +0x53ca8*4 +0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x53ca9*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53caa*4 +0x02000000,0x844); +reg_write( DDR_REG_BASE +0x53cab*4 +0x02000000,0x1e57); +reg_write( DDR_REG_BASE +0x53cac*4 +0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x53cad*4 +0x02000000,0x93e); +reg_write( DDR_REG_BASE +0x53cae*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53caf*4 +0x02000000,0xd830); +reg_write( DDR_REG_BASE +0x53cb0*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53cb1*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53cb2*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53cb3*4 +0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x53cb4*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53cb5*4 +0x02000000,0x708b); +reg_write( DDR_REG_BASE +0x53cb6*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53cb7*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53cb8*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x53cb9*4 +0x02000000,0xf084); +reg_write( DDR_REG_BASE +0x53cba*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x53cbb*4 +0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x53cbc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cbd*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x53cbe*4 +0x02000000,0x2716); +reg_write( DDR_REG_BASE +0x53cbf*4 +0x02000000,0x12de); +reg_write( DDR_REG_BASE +0x53cc0*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53cc1*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53cc2*4 +0x02000000,0xc104); +reg_write( DDR_REG_BASE +0x53cc3*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x53cc4*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x53cc5*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x53cc6*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x53cc7*4 +0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x53cc8*4 +0x02000000,0xd01); +reg_write( DDR_REG_BASE +0x53cc9*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53cca*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x53ccb*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53ccc*4 +0x02000000,0xb891); +reg_write( DDR_REG_BASE +0x53ccd*4 +0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x53cce*4 +0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x53ccf*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x53cd0*4 +0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x53cd1*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x53cd2*4 +0x02000000,0xf05d); +reg_write( DDR_REG_BASE +0x53cd3*4 +0x02000000,0x4340); +reg_write( DDR_REG_BASE +0x53cd4*4 +0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x53cd5*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53cd6*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53cd7*4 +0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x53cd8*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53cd9*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53cda*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53cdb*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x53cdc*4 +0x02000000,0x64); +reg_write( DDR_REG_BASE +0x53cdd*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x53cde*4 +0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x53cdf*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x53ce0*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x53ce1*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x53ce2*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x53ce3*4 +0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x53ce4*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x53ce5*4 +0x02000000,0xc087); +reg_write( DDR_REG_BASE +0x53ce6*4 +0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x53ce7*4 +0x02000000,0x79f); +reg_write( DDR_REG_BASE +0x53ce8*4 +0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x53ce9*4 +0x02000000,0x3bc0); +reg_write( DDR_REG_BASE +0x53cea*4 +0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x53ceb*4 +0x02000000,0x2cc); +reg_write( DDR_REG_BASE +0x53cec*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x53ced*4 +0x02000000,0x71f3); +reg_write( DDR_REG_BASE +0x53cee*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x53cef*4 +0x02000000,0x101b); +reg_write( DDR_REG_BASE +0x53cf0*4 +0x02000000,0x27d4); +reg_write( DDR_REG_BASE +0x53cf1*4 +0x02000000,0x3829); +reg_write( DDR_REG_BASE +0x53cf2*4 +0x02000000,0x71e3); +reg_write( DDR_REG_BASE +0x53cf3*4 +0x02000000,0x2340); +reg_write( DDR_REG_BASE +0x53cf4*4 +0x02000000,0x340c); +reg_write( DDR_REG_BASE +0x53cf5*4 +0x02000000,0x782e); +reg_write( DDR_REG_BASE +0x53cf6*4 +0x02000000,0x791c); +reg_write( DDR_REG_BASE +0x53cf7*4 +0x02000000,0x7c8e); +reg_write( DDR_REG_BASE +0x53cf8*4 +0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x53cf9*4 +0x02000000,0x792e); +reg_write( DDR_REG_BASE +0x53cfa*4 +0x02000000,0x4990); +reg_write( DDR_REG_BASE +0x53cfb*4 +0x02000000,0x2154); +reg_write( DDR_REG_BASE +0x53cfc*4 +0x02000000,0x801); +reg_write( DDR_REG_BASE +0x53cfd*4 +0x02000000,0x272f); +reg_write( DDR_REG_BASE +0x53cfe*4 +0x02000000,0x3009); +reg_write( DDR_REG_BASE +0x53cff*4 +0x02000000,0x4990); +reg_write( DDR_REG_BASE +0x53d00*4 +0x02000000,0x7811); +reg_write( DDR_REG_BASE +0x53d01*4 +0x02000000,0x8f1); +reg_write( DDR_REG_BASE +0x53d02*4 +0x02000000,0x87c2); +reg_write( DDR_REG_BASE +0x53d03*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53d04*4 +0x02000000,0x3f); +reg_write( DDR_REG_BASE +0x53d05*4 +0x02000000,0x4891); +reg_write( DDR_REG_BASE +0x53d06*4 +0x02000000,0x78ae); +reg_write( DDR_REG_BASE +0x53d07*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x53d08*4 +0x02000000,0x272f); +reg_write( DDR_REG_BASE +0x53d09*4 +0x02000000,0x3049); +reg_write( DDR_REG_BASE +0x53d0a*4 +0x02000000,0x4891); +reg_write( DDR_REG_BASE +0x53d0b*4 +0x02000000,0x7931); +reg_write( DDR_REG_BASE +0x53d0c*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x53d0d*4 +0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x53d0e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d0f*4 +0x02000000,0xffc0); +reg_write( DDR_REG_BASE +0x53d10*4 +0x02000000,0xfe7); +reg_write( DDR_REG_BASE +0x53d11*4 +0x02000000,0xb042); +reg_write( DDR_REG_BASE +0x53d12*4 +0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x53d13*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53d14*4 +0x02000000,0x783b); +reg_write( DDR_REG_BASE +0x53d15*4 +0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x53d16*4 +0x02000000,0x7); +reg_write( DDR_REG_BASE +0x53d17*4 +0x02000000,0xb9c4); +reg_write( DDR_REG_BASE +0x53d18*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x53d19*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x53d1a*4 +0x02000000,0xc405); +reg_write( DDR_REG_BASE +0x53d1b*4 +0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x53d1c*4 +0x02000000,0xc00); +reg_write( DDR_REG_BASE +0x53d1d*4 +0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x53d1e*4 +0x02000000,0x7b85); +reg_write( DDR_REG_BASE +0x53d1f*4 +0x02000000,0x787b); +reg_write( DDR_REG_BASE +0x53d20*4 +0x02000000,0xb891); +reg_write( DDR_REG_BASE +0x53d21*4 +0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x53d22*4 +0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x53d23*4 +0x02000000,0xa15); +reg_write( DDR_REG_BASE +0x53d24*4 +0x02000000,0x1f1); +reg_write( DDR_REG_BASE +0x53d25*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x53d26*4 +0x02000000,0x789b); +reg_write( DDR_REG_BASE +0x53d27*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53d28*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53d29*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x53d2a*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x53d2b*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x53d2c*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x53d2d*4 +0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x53d2e*4 +0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x53d2f*4 +0x02000000,0xa4b); +reg_write( DDR_REG_BASE +0x53d30*4 +0x02000000,0x8214); +reg_write( DDR_REG_BASE +0x53d31*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x53d32*4 +0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x53d33*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d34*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x53d35*4 +0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x53d36*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53d37*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x53d38*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x53d39*4 +0x02000000,0x1e64); +reg_write( DDR_REG_BASE +0x53d3a*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x53d3b*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x53d3c*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53d3d*4 +0x02000000,0x230c); +reg_write( DDR_REG_BASE +0x53d3e*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x53d3f*4 +0x02000000,0x6f8); +reg_write( DDR_REG_BASE +0x53d40*4 +0x02000000,0xffee); +reg_write( DDR_REG_BASE +0x53d41*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53d42*4 +0x02000000,0x1e58); +reg_write( DDR_REG_BASE +0x53d43*4 +0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x53d44*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53d45*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53d46*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d47*4 +0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x53d48*4 +0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x53d49*4 +0x02000000,0x1e5e); +reg_write( DDR_REG_BASE +0x53d4a*4 +0x02000000,0x905c); +reg_write( DDR_REG_BASE +0x53d4b*4 +0x02000000,0xbee); +reg_write( DDR_REG_BASE +0x53d4c*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x53d4d*4 +0x02000000,0x1e57); +reg_write( DDR_REG_BASE +0x53d4e*4 +0x02000000,0x905c); +reg_write( DDR_REG_BASE +0x53d4f*4 +0x02000000,0xf26); +reg_write( DDR_REG_BASE +0x53d50*4 +0x02000000,0xfe0f); +reg_write( DDR_REG_BASE +0x53d51*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53d52*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53d53*4 +0x02000000,0xfe64); +reg_write( DDR_REG_BASE +0x53d54*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53d55*4 +0x02000000,0x73c4); +reg_write( DDR_REG_BASE +0x53d56*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53d57*4 +0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x53d58*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53d59*4 +0x02000000,0x7344); +reg_write( DDR_REG_BASE +0x53d5a*4 +0x02000000,0x900f); +reg_write( DDR_REG_BASE +0x53d5b*4 +0x02000000,0xe0c0); +reg_write( DDR_REG_BASE +0x53d5c*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53d5d*4 +0x02000000,0x73c4); +reg_write( DDR_REG_BASE +0x53d5e*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53d5f*4 +0x02000000,0xfec4); +reg_write( DDR_REG_BASE +0x53d60*4 +0x02000000,0x1882); +reg_write( DDR_REG_BASE +0x53d61*4 +0x02000000,0x3dc); +reg_write( DDR_REG_BASE +0x53d62*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53d63*4 +0x02000000,0xb5a); +reg_write( DDR_REG_BASE +0x53d64*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53d65*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x53d66*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53d67*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d68*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x53d69*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53d6a*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53d6b*4 +0x02000000,0x4320); +reg_write( DDR_REG_BASE +0x53d6c*4 +0x02000000,0xea2); +reg_write( DDR_REG_BASE +0x53d6d*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53d6e*4 +0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53d6f*4 +0x02000000,0xf03b); +reg_write( DDR_REG_BASE +0x53d70*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53d71*4 +0x02000000,0xfb6); +reg_write( DDR_REG_BASE +0x53d72*4 +0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53d73*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53d74*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53d75*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53d76*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53d77*4 +0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x53d78*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53d79*4 +0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x53d7a*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53d7b*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x53d7c*4 +0x02000000,0xf023); +reg_write( DDR_REG_BASE +0x53d7d*4 +0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x53d7e*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53d7f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d80*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x53d81*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53d82*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53d83*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x53d84*4 +0x02000000,0x166); +reg_write( DDR_REG_BASE +0x53d85*4 +0x02000000,0x9060); +reg_write( DDR_REG_BASE +0x53d86*4 +0x02000000,0xeb17); +reg_write( DDR_REG_BASE +0x53d87*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x53d88*4 +0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x53d89*4 +0x02000000,0xd0c); +reg_write( DDR_REG_BASE +0x53d8a*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x53d8b*4 +0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x53d8c*4 +0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x53d8d*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53d8e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d8f*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x53d90*4 +0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x53d91*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53d92*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53d93*4 +0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x53d94*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x53d95*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53d96*4 +0x02000000,0xb891); +reg_write( DDR_REG_BASE +0x53d97*4 +0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x53d98*4 +0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x53d99*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x53d9a*4 +0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x53d9b*4 +0x02000000,0x800); +reg_write( DDR_REG_BASE +0x53d9c*4 +0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x53d9d*4 +0x02000000,0x657d); +reg_write( DDR_REG_BASE +0x53d9e*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x53d9f*4 +0x02000000,0x9bf); +reg_write( DDR_REG_BASE +0x53da0*4 +0x02000000,0x80a5); +reg_write( DDR_REG_BASE +0x53da1*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53da2*4 +0x02000000,0xada); +reg_write( DDR_REG_BASE +0x53da3*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53da4*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x53da5*4 +0x02000000,0xe7a); +reg_write( DDR_REG_BASE +0x53da6*4 +0x02000000,0xfe0f); +reg_write( DDR_REG_BASE +0x53da7*4 +0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x53da8*4 +0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x53da9*4 +0x02000000,0xf91); +reg_write( DDR_REG_BASE +0x53daa*4 +0x02000000,0x9234); +reg_write( DDR_REG_BASE +0x53dab*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x53dac*4 +0x02000000,0x2178); +reg_write( DDR_REG_BASE +0x53dad*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dae*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53daf*4 +0x02000000,0x156); +reg_write( DDR_REG_BASE +0x53db0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53db1*4 +0x02000000,0xdf2); +reg_write( DDR_REG_BASE +0x53db2*4 +0x02000000,0xfc0f); +reg_write( DDR_REG_BASE +0x53db3*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53db4*4 +0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x53db5*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53db6*4 +0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x53db7*4 +0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x53db8*4 +0x02000000,0x3403); +reg_write( DDR_REG_BASE +0x53db9*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x53dba*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x53dbb*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53dbc*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x53dbd*4 +0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x53dbe*4 +0x02000000,0x3302); +reg_write( DDR_REG_BASE +0x53dbf*4 +0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x53dc0*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53dc1*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53dc2*4 +0x02000000,0x597); +reg_write( DDR_REG_BASE +0x53dc3*4 +0x02000000,0xcfe); +reg_write( DDR_REG_BASE +0x53dc4*4 +0x02000000,0xfc2f); +reg_write( DDR_REG_BASE +0x53dc5*4 +0x02000000,0xda8a); +reg_write( DDR_REG_BASE +0x53dc6*4 +0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x53dc7*4 +0x02000000,0x9fe); +reg_write( DDR_REG_BASE +0x53dc8*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x53dc9*4 +0x02000000,0xd98a); +reg_write( DDR_REG_BASE +0x53dca*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x53dcb*4 +0x02000000,0xa8a); +reg_write( DDR_REG_BASE +0x53dcc*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53dcd*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x53dce*4 +0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x53dcf*4 +0x02000000,0x3302); +reg_write( DDR_REG_BASE +0x53dd0*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x53dd1*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x53dd2*4 +0x02000000,0xc3e6); +reg_write( DDR_REG_BASE +0x53dd3*4 +0x02000000,0xc1b2); +reg_write( DDR_REG_BASE +0x53dd4*4 +0x02000000,0xc14a); +reg_write( DDR_REG_BASE +0x53dd5*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x53dd6*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53dd7*4 +0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x53dd8*4 +0x02000000,0xe805); +reg_write( DDR_REG_BASE +0x53dd9*4 +0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x53dda*4 +0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x53ddb*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x53ddc*4 +0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x53ddd*4 +0x02000000,0x215a); +reg_write( DDR_REG_BASE +0x53dde*4 +0x02000000,0x101); +reg_write( DDR_REG_BASE +0x53ddf*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53de0*4 +0x02000000,0x210f); +reg_write( DDR_REG_BASE +0x53de1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53de2*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x53de3*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53de4*4 +0x02000000,0xaa2); +reg_write( DDR_REG_BASE +0x53de5*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53de6*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53de7*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53de8*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x53de9*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53dea*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53deb*4 +0x02000000,0xd2a); +reg_write( DDR_REG_BASE +0x53dec*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53ded*4 +0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x53dee*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x53def*4 +0x02000000,0x8e82); +reg_write( DDR_REG_BASE +0x53df0*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x53df1*4 +0x02000000,0xd8fe); +reg_write( DDR_REG_BASE +0x53df2*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53df3*4 +0x02000000,0xf707); +reg_write( DDR_REG_BASE +0x53df4*4 +0x02000000,0xd16); +reg_write( DDR_REG_BASE +0x53df5*4 +0x02000000,0xfd0f); +reg_write( DDR_REG_BASE +0x53df6*4 +0x02000000,0x2054); +reg_write( DDR_REG_BASE +0x53df7*4 +0x02000000,0x880); +reg_write( DDR_REG_BASE +0x53df8*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53df9*4 +0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x53dfa*4 +0x02000000,0x1f8d); +reg_write( DDR_REG_BASE +0x53dfb*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x53dfc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dfd*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x53dfe*4 +0x02000000,0xc18d); +reg_write( DDR_REG_BASE +0x53dff*4 +0x02000000,0xd12); +reg_write( DDR_REG_BASE +0x53e00*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x53e01*4 +0x02000000,0xc54b); +reg_write( DDR_REG_BASE +0x53e02*4 +0x02000000,0xf76); +reg_write( DDR_REG_BASE +0x53e03*4 +0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x53e04*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x53e05*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53e06*4 +0x02000000,0xe002); +reg_write( DDR_REG_BASE +0x53e07*4 +0x02000000,0xd840); +reg_write( DDR_REG_BASE +0x53e08*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x53e09*4 +0x02000000,0x1f84); +reg_write( DDR_REG_BASE +0x53e0a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e0b*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53e0c*4 +0x02000000,0xd1e); +reg_write( DDR_REG_BASE +0x53e0d*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53e0e*4 +0x02000000,0xb512); +reg_write( DDR_REG_BASE +0x53e0f*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53e10*4 +0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x53e11*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x53e12*4 +0x02000000,0x4a); +reg_write( DDR_REG_BASE +0x53e13*4 +0x02000000,0xd998); +reg_write( DDR_REG_BASE +0x53e14*4 +0x02000000,0x2011); +reg_write( DDR_REG_BASE +0x53e15*4 +0x02000000,0x8380); +reg_write( DDR_REG_BASE +0x53e16*4 +0x02000000,0xd8aa); +reg_write( DDR_REG_BASE +0x53e17*4 +0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x53e18*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53e19*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53e1a*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x53e1b*4 +0x02000000,0xe04c); +reg_write( DDR_REG_BASE +0x53e1c*4 +0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x53e1d*4 +0x02000000,0x189c); +reg_write( DDR_REG_BASE +0x53e1e*4 +0x02000000,0x54); +reg_write( DDR_REG_BASE +0x53e1f*4 +0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x53e20*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53e21*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x53e22*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x53e23*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e24*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53e25*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53e26*4 +0x02000000,0x2056); +reg_write( DDR_REG_BASE +0x53e27*4 +0x02000000,0xe00); +reg_write( DDR_REG_BASE +0x53e28*4 +0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x53e29*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x53e2a*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x53e2b*4 +0x02000000,0x16e9); +reg_write( DDR_REG_BASE +0x53e2c*4 +0x02000000,0x1700); +reg_write( DDR_REG_BASE +0x53e2d*4 +0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x53e2e*4 +0x02000000,0xda2); +reg_write( DDR_REG_BASE +0x53e2f*4 +0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53e30*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53e31*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53e32*4 +0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x53e33*4 +0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x53e34*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53e35*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53e36*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53e37*4 +0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53e38*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x53e39*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53e3a*4 +0x02000000,0xe62); +reg_write( DDR_REG_BASE +0x53e3b*4 +0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53e3c*4 +0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53e3d*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53e3e*4 +0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x53e3f*4 +0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53e40*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x53e41*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x53e42*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53e43*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53e44*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53e45*4 +0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53e46*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x53e47*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x53e48*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x53e49*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x53e4a*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53e4b*4 +0x02000000,0xc304); +reg_write( DDR_REG_BASE +0x53e4c*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x53e4d*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53e4e*4 +0x02000000,0xe3a); +reg_write( DDR_REG_BASE +0x53e4f*4 +0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53e50*4 +0x02000000,0xb990); +reg_write( DDR_REG_BASE +0x53e51*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53e52*4 +0x02000000,0xdf2); +reg_write( DDR_REG_BASE +0x53e53*4 +0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53e54*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53e55*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53e56*4 +0x02000000,0x9de); +reg_write( DDR_REG_BASE +0x53e57*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x53e58*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x53e59*4 +0x02000000,0x16f0); +reg_write( DDR_REG_BASE +0x53e5a*4 +0x02000000,0x1700); +reg_write( DDR_REG_BASE +0x53e5b*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x53e5c*4 +0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x53e5d*4 +0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x53e5e*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53e5f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e60*4 +0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x53e61*4 +0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x53e62*4 +0x02000000,0xb888); +reg_write( DDR_REG_BASE +0x53e63*4 +0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x53e64*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x53e65*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x53e66*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53e67*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x53e68*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x53e69*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x53e6a*4 +0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x53e6b*4 +0x02000000,0x7932); +reg_write( DDR_REG_BASE +0x53e6c*4 +0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x53e6d*4 +0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x53e6e*4 +0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x53e6f*4 +0x02000000,0xb887); +reg_write( DDR_REG_BASE +0x53e70*4 +0x02000000,0x1ef2); +reg_write( DDR_REG_BASE +0x53e71*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x53e72*4 +0x02000000,0xc109); +reg_write( DDR_REG_BASE +0x53e73*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x53e74*4 +0x02000000,0xc0a); +reg_write( DDR_REG_BASE +0x53e75*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53e76*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x53e77*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x53e78*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53e79*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53e7a*4 +0x02000000,0xd0a); +reg_write( DDR_REG_BASE +0x53e7b*4 +0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53e7c*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53e7d*4 +0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x53e7e*4 +0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x53e7f*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53e80*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53e81*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53e82*4 +0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53e83*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x53e84*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53e85*4 +0x02000000,0xdce); +reg_write( DDR_REG_BASE +0x53e86*4 +0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53e87*4 +0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53e88*4 +0x02000000,0x812); +reg_write( DDR_REG_BASE +0x53e89*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53e8a*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53e8b*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53e8c*4 +0x02000000,0xc304); +reg_write( DDR_REG_BASE +0x53e8d*4 +0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x53e8e*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53e8f*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53e90*4 +0x02000000,0xb88f); +reg_write( DDR_REG_BASE +0x53e91*4 +0x02000000,0x791b); +reg_write( DDR_REG_BASE +0x53e92*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53e93*4 +0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53e94*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53e95*4 +0x02000000,0xdae); +reg_write( DDR_REG_BASE +0x53e96*4 +0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53e97*4 +0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53e98*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x53e99*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x53e9a*4 +0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53e9b*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x53e9c*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x53e9d*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x53e9e*4 +0x02000000,0xe01e); +reg_write( DDR_REG_BASE +0x53e9f*4 +0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x53ea0*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53ea1*4 +0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x53ea2*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x53ea3*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53ea4*4 +0x02000000,0xd8e); +reg_write( DDR_REG_BASE +0x53ea5*4 +0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53ea6*4 +0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53ea7*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x53ea8*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53ea9*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x53eaa*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53eab*4 +0x02000000,0xb98f); +reg_write( DDR_REG_BASE +0x53eac*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53ead*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x53eae*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x53eaf*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53eb0*4 +0x02000000,0xd76); +reg_write( DDR_REG_BASE +0x53eb1*4 +0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53eb2*4 +0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53eb3*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53eb4*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53eb5*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53eb6*4 +0x02000000,0xdb10); +reg_write( DDR_REG_BASE +0x53eb7*4 +0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53eb8*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x53eb9*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53eba*4 +0x02000000,0xd62); +reg_write( DDR_REG_BASE +0x53ebb*4 +0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53ebc*4 +0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53ebd*4 +0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x53ebe*4 +0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53ebf*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53ec0*4 +0x02000000,0xf838); +reg_write( DDR_REG_BASE +0x53ec1*4 +0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53ec2*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x53ec3*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53ec4*4 +0x02000000,0xd4e); +reg_write( DDR_REG_BASE +0x53ec5*4 +0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53ec6*4 +0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53ec7*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53ec8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ec9*4 +0x02000000,0x6210); +reg_write( DDR_REG_BASE +0x53eca*4 +0x02000000,0xb501); +reg_write( DDR_REG_BASE +0x53ecb*4 +0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x53ecc*4 +0x02000000,0xcfe); +reg_write( DDR_REG_BASE +0x53ecd*4 +0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53ece*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53ecf*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53ed0*4 +0x02000000,0x408); +reg_write( DDR_REG_BASE +0x53ed1*4 +0x02000000,0xb501); +reg_write( DDR_REG_BASE +0x53ed2*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53ed3*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53ed4*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53ed5*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53ed6*4 +0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x53ed7*4 +0x02000000,0xbf); +reg_write( DDR_REG_BASE +0x53ed8*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53ed9*4 +0x02000000,0x606); +reg_write( DDR_REG_BASE +0x53eda*4 +0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x53edb*4 +0x02000000,0xd833); +reg_write( DDR_REG_BASE +0x53edc*4 +0x02000000,0xcde); +reg_write( DDR_REG_BASE +0x53edd*4 +0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53ede*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53edf*4 +0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x53ee0*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53ee1*4 +0x02000000,0x1ef2); +reg_write( DDR_REG_BASE +0x53ee2*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x53ee3*4 +0x02000000,0x8c6); +reg_write( DDR_REG_BASE +0x53ee4*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x53ee5*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53ee6*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53ee7*4 +0x02000000,0xb42); +reg_write( DDR_REG_BASE +0x53ee8*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x53ee9*4 +0x02000000,0xc18d); +reg_write( DDR_REG_BASE +0x53eea*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x53eeb*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53eec*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53eed*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53eee*4 +0x02000000,0xb5e0); +reg_write( DDR_REG_BASE +0x53eef*4 +0x02000000,0xc22); +reg_write( DDR_REG_BASE +0x53ef0*4 +0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53ef1*4 +0x02000000,0xb5f2); +reg_write( DDR_REG_BASE +0x53ef2*4 +0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x53ef3*4 +0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x53ef4*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53ef5*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53ef6*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53ef7*4 +0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53ef8*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x53ef9*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53efa*4 +0x02000000,0xce2); +reg_write( DDR_REG_BASE +0x53efb*4 +0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53efc*4 +0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53efd*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53efe*4 +0x02000000,0xc304); +reg_write( DDR_REG_BASE +0x53eff*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53f00*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53f01*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53f02*4 +0x02000000,0xb990); +reg_write( DDR_REG_BASE +0x53f03*4 +0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x53f04*4 +0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53f05*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53f06*4 +0x02000000,0xcca); +reg_write( DDR_REG_BASE +0x53f07*4 +0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53f08*4 +0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53f09*4 +0x02000000,0xf814); +reg_write( DDR_REG_BASE +0x53f0a*4 +0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x53f0b*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x53f0c*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x53f0d*4 +0x02000000,0xcbe); +reg_write( DDR_REG_BASE +0x53f0e*4 +0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53f0f*4 +0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53f10*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53f11*4 +0x02000000,0xc76); +reg_write( DDR_REG_BASE +0x53f12*4 +0x02000000,0xfc6f); +reg_write( DDR_REG_BASE +0x53f13*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53f14*4 +0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x53f15*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53f16*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53f17*4 +0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x53f18*4 +0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x53f19*4 +0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x53f1a*4 +0x02000000,0xb5e1); +reg_write( DDR_REG_BASE +0x53f1b*4 +0x02000000,0xb0e); +reg_write( DDR_REG_BASE +0x53f1c*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x53f1d*4 +0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x53f1e*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x53f1f*4 +0x02000000,0x82e); +reg_write( DDR_REG_BASE +0x53f20*4 +0x02000000,0xfcaf); +reg_write( DDR_REG_BASE +0x53f21*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53f22*4 +0x02000000,0xc10b); +reg_write( DDR_REG_BASE +0x53f23*4 +0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x53f24*4 +0x02000000,0xd00); +reg_write( DDR_REG_BASE +0x53f25*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x53f26*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x53f27*4 +0x02000000,0xc10a); +reg_write( DDR_REG_BASE +0x53f28*4 +0x02000000,0xf96); +reg_write( DDR_REG_BASE +0x53f29*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x53f2a*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x53f2b*4 +0x02000000,0xb6e); +reg_write( DDR_REG_BASE +0x53f2c*4 +0x02000000,0xfe0f); +reg_write( DDR_REG_BASE +0x53f2d*4 +0x02000000,0xc02); +reg_write( DDR_REG_BASE +0x53f2e*4 +0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x53f2f*4 +0x02000000,0xc7c6); +reg_write( DDR_REG_BASE +0x53f30*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53f31*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x53f32*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53f33*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x53f34*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x53f35*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f36*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f37*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f38*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f39*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f40*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f41*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f42*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f43*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f44*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f45*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f46*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f47*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f48*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f49*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f50*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f51*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f52*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f53*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f54*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f55*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f56*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f57*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f58*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f59*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f60*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f61*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f62*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f63*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f64*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f65*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f66*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f67*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f68*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f69*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f70*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f71*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f72*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f73*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f74*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f75*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f76*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f77*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f78*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f79*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f80*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f81*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f82*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f83*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f84*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f85*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f86*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f87*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f88*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f89*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f90*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f91*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f92*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f93*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f94*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f95*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f96*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f97*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f98*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f99*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53faa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fab*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fac*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fad*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fae*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53faf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fba*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fbb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fbc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fbd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fbe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fbf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fca*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fcb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fcc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fcd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fce*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fcf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fda*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fdb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fdc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fdd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fde*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fdf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fea*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53feb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fec*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fed*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fee*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fef*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ffa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ffb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ffc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ffd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ffe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fff*4 +0x02000000,0x0); + +reg_write( DDR_REG_BASE + 0x000d0000*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000d0000*4+0x02000000 , 0x00000000 ); + + +reg_write( DDR_REG_BASE +0x54000*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x54001*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54002*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54003*4 +0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x54004*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x54005*4 +0x02000000,0x0); +//iteration Vref +// 0x14 15% +// 0x1a 20% +// 0x20 25% +// 0x26 30% +// 0x33 40% +reg_write( DDR_REG_BASE +0x54006*4 +0x02000000,0x20); + +reg_write( DDR_REG_BASE +0x54007*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54008*4 +0x02000000,0x131f); +reg_write( DDR_REG_BASE +0x54009*4 +0x02000000,0xc8); +reg_write( DDR_REG_BASE +0x5400a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5400b*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x5400c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5400d*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5400e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5400f*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x54010*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54011*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54012*4 +0x02000000,0x110); +reg_write( DDR_REG_BASE +0x54013*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54014*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54015*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54016*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54017*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54018*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54019*4 +0x02000000,0x2d54); +reg_write( DDR_REG_BASE +0x5401a*4 +0x02000000,0x33); +//iteration +//MR11 l-DQ/h-CA ODT: 2:120 3:80 4:60 5:70 6:40 +reg_write( DDR_REG_BASE +0x5401b*4 +0x02000000,0x4d44); +reg_write( DDR_REG_BASE +0x5401c*4 +0x02000000,0x4f08); +reg_write( DDR_REG_BASE +0x5401d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5401e*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5401f*4 +0x02000000,0x2d54); +reg_write( DDR_REG_BASE +0x54020*4 +0x02000000,0x33); +//iteration +//MR11 l-DQ/h-CA ODT: 2:120 3:80 4:60 5:70 6:40 +reg_write( DDR_REG_BASE +0x54021*4 +0x02000000,0x4d44); +reg_write( DDR_REG_BASE +0x54022*4 +0x02000000,0x4f08); +reg_write( DDR_REG_BASE +0x54023*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54024*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x54025*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54026*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54027*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54028*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54029*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5402a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5402b*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x5402c*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5402d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5402e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5402f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54030*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54031*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54032*4 +0x02000000,0x5400); +reg_write( DDR_REG_BASE +0x54033*4 +0x02000000,0x332d); +//iteration +//MR11 low-DQ/high-CA ODT: 2:120 3:80 4:60 5:70 6:40 +reg_write( DDR_REG_BASE +0x54034*4 +0x02000000,0x4400); +reg_write( DDR_REG_BASE +0x54035*4 +0x02000000,0x84d); +reg_write( DDR_REG_BASE +0x54036*4 +0x02000000,0x4f); +reg_write( DDR_REG_BASE +0x54037*4 +0x02000000,0x400); +reg_write( DDR_REG_BASE +0x54038*4 +0x02000000,0x5400); +reg_write( DDR_REG_BASE +0x54039*4 +0x02000000,0x332d); +//iteration +//MR11 low-DQ/high-CA ODT: 2:120 3:80 4:60 5:70 6:40 +reg_write( DDR_REG_BASE +0x5403a*4 +0x02000000,0x4400); +reg_write( DDR_REG_BASE +0x5403b*4 +0x02000000,0x84d); +reg_write( DDR_REG_BASE +0x5403c*4 +0x02000000,0x4f); +reg_write( DDR_REG_BASE +0x5403d*4 +0x02000000,0x400); +reg_write( DDR_REG_BASE +0x5403e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5403f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54040*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54041*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54042*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54043*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54044*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54045*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54046*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54047*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54048*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54049*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54050*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54051*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54052*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54053*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54054*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54055*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54056*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54057*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54058*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54059*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54060*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54061*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54062*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54063*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54064*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54065*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54066*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54067*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54068*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54069*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54070*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54071*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54072*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54073*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54074*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54075*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54076*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54077*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54078*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54079*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54080*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54081*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54082*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54083*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54084*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54085*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54086*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54087*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54088*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54089*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54090*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54091*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54092*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54093*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54094*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54095*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54096*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54097*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54098*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54099*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540aa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ab*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ac*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ad*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ae*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540af*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ba*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540bb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540bc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540bd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540be*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540bf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ca*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540cb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540cc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540cd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ce*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540cf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540da*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540db*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540dc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540dd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540de*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540df*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ea*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540eb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ec*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ed*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ee*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ef*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540fa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540fb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540fc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540fd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540fe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ff*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54100*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54101*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54102*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54103*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54104*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54105*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54106*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54107*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54108*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54109*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54110*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54111*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54112*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54113*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54114*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54115*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54116*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54117*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54118*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54119*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54120*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54121*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54122*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54123*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54124*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54125*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54126*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54127*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54128*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54129*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54130*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54131*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54132*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54133*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54134*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54135*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54136*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54137*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54138*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54139*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54140*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54141*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54142*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54143*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54144*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54145*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54146*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54147*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54148*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54149*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54150*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54151*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54152*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54153*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54154*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54155*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54156*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54157*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54158*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54159*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54160*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54161*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54162*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54163*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54164*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54165*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54166*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54167*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54168*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54169*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54170*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54171*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54172*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54173*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54174*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54175*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54176*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54177*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54178*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54179*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54180*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54181*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54182*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54183*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54184*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54185*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54186*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54187*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54188*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54189*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54190*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54191*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54192*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54193*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54194*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54195*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54196*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54197*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54198*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54199*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541aa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ab*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ac*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ad*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ae*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541af*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ba*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541bb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541bc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541bd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541be*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541bf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ca*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541cb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541cc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541cd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ce*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541cf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541da*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541db*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541dc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541dd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541de*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541df*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ea*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541eb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ec*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ed*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ee*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ef*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541fa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541fb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541fc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541fd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541fe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ff*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54200*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54201*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54202*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54203*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54204*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54205*4 +0x02000000,0xff); +reg_write( DDR_REG_BASE +0x54206*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54207*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54208*4 +0x02000000,0x14a); +reg_write( DDR_REG_BASE +0x54209*4 +0x02000000,0x181); +reg_write( DDR_REG_BASE +0x5420a*4 +0x02000000,0x118); +reg_write( DDR_REG_BASE +0x5420b*4 +0x02000000,0x118); +reg_write( DDR_REG_BASE +0x5420c*4 +0x02000000,0x16f); +reg_write( DDR_REG_BASE +0x5420d*4 +0x02000000,0x16f); +reg_write( DDR_REG_BASE +0x5420e*4 +0x02000000,0x159); +reg_write( DDR_REG_BASE +0x5420f*4 +0x02000000,0x181); +reg_write( DDR_REG_BASE +0x54210*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x54211*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x54212*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54213*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54214*4 +0x02000000,0x701c); +reg_write( DDR_REG_BASE +0x54215*4 +0x02000000,0x61a8); +reg_write( DDR_REG_BASE +0x54216*4 +0x02000000,0x35ac); +reg_write( DDR_REG_BASE +0x54217*4 +0x02000000,0x35ac); +reg_write( DDR_REG_BASE +0x54218*4 +0x02000000,0x125c); +reg_write( DDR_REG_BASE +0x54219*4 +0x02000000,0x125c); +reg_write( DDR_REG_BASE +0x5421a*4 +0x02000000,0xc738); +reg_write( DDR_REG_BASE +0x5421b*4 +0x02000000,0xb0f4); +reg_write( DDR_REG_BASE +0x5421c*4 +0x02000000,0x6590); +reg_write( DDR_REG_BASE +0x5421d*4 +0x02000000,0x6590); +reg_write( DDR_REG_BASE +0x5421e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5421f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54220*4 +0x02000000,0x9f38); +reg_write( DDR_REG_BASE +0x54221*4 +0x02000000,0x58); +reg_write( DDR_REG_BASE +0x54222*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54223*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54224*4 +0x02000000,0x2820); +reg_write( DDR_REG_BASE +0x54225*4 +0x02000000,0x140f); +reg_write( DDR_REG_BASE +0x54226*4 +0x02000000,0x1f02); +reg_write( DDR_REG_BASE +0x54227*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54228*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54229*4 +0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x5422a*4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x5422b*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5422c*4 +0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x5422d*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5422e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5422f*4 +0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x54230*4 +0x02000000,0x1f4); +reg_write( DDR_REG_BASE +0x54231*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54232*4 +0x02000000,0xb900); +reg_write( DDR_REG_BASE +0x54233*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54234*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54235*4 +0x02000000,0xba00); +reg_write( DDR_REG_BASE +0x54236*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54237*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54238*4 +0x02000000,0xbb00); +reg_write( DDR_REG_BASE +0x54239*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5423a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5423b*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5423c*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5423d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5423e*4 +0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x5423f*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54240*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54241*4 +0x02000000,0xf900); +reg_write( DDR_REG_BASE +0x54242*4 +0x02000000,0x4f0); +reg_write( DDR_REG_BASE +0x54243*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54244*4 +0x02000000,0xfa02); +reg_write( DDR_REG_BASE +0x54245*4 +0x02000000,0x4f0); +reg_write( DDR_REG_BASE +0x54246*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54247*4 +0x02000000,0xfb00); +reg_write( DDR_REG_BASE +0x54248*4 +0x02000000,0x4f0); +reg_write( DDR_REG_BASE +0x54249*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5424a*4 +0x02000000,0x6004); +reg_write( DDR_REG_BASE +0x5424b*4 +0x02000000,0x7f0); +reg_write( DDR_REG_BASE +0x5424c*4 +0x02000000,0x800); +reg_write( DDR_REG_BASE +0x5424d*4 +0x02000000,0x6500); +reg_write( DDR_REG_BASE +0x5424e*4 +0x02000000,0x7f0); +reg_write( DDR_REG_BASE +0x5424f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54250*4 +0x02000000,0x6200); +reg_write( DDR_REG_BASE +0x54251*4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x54252*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54253*4 +0x02000000,0x200); +reg_write( DDR_REG_BASE +0x54254*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54255*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x54256*4 +0x02000000,0x1f02); +reg_write( DDR_REG_BASE +0x54257*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54258*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54259*4 +0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x5425a*4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x5425b*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5425c*4 +0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x5425d*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5425e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5425f*4 +0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x54260*4 +0x02000000,0x1f4); +reg_write( DDR_REG_BASE +0x54261*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54262*4 +0x02000000,0xb900); +reg_write( DDR_REG_BASE +0x54263*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54264*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54265*4 +0x02000000,0xba00); +reg_write( DDR_REG_BASE +0x54266*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54267*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54268*4 +0x02000000,0xbb00); +reg_write( DDR_REG_BASE +0x54269*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5426a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5426b*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5426c*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5426d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5426e*4 +0x02000000,0x1100); +reg_write( DDR_REG_BASE +0x5426f*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54270*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x54271*4 +0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x54272*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54273*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54274*4 +0x02000000,0x18f0); +reg_write( DDR_REG_BASE +0x54275*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54276*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x54277*4 +0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x54278*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54279*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5427a*4 +0x02000000,0xf900); +reg_write( DDR_REG_BASE +0x5427b*4 +0x02000000,0x4f0); +reg_write( DDR_REG_BASE +0x5427c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5427d*4 +0x02000000,0xfa02); +reg_write( DDR_REG_BASE +0x5427e*4 +0x02000000,0x4f0); +reg_write( DDR_REG_BASE +0x5427f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54280*4 +0x02000000,0xfb00); +reg_write( DDR_REG_BASE +0x54281*4 +0x02000000,0x4f0); +reg_write( DDR_REG_BASE +0x54282*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54283*4 +0x02000000,0x6204); +reg_write( DDR_REG_BASE +0x54284*4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x54285*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54286*4 +0x02000000,0x6200); +reg_write( DDR_REG_BASE +0x54287*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54288*4 +0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x54289*4 +0x02000000,0x6200); +reg_write( DDR_REG_BASE +0x5428a*4 +0x02000000,0x1f4); +reg_write( DDR_REG_BASE +0x5428b*4 +0x02000000,0xf000); +reg_write( DDR_REG_BASE +0x5428c*4 +0x02000000,0x200); +reg_write( DDR_REG_BASE +0x5428d*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5428e*4 +0x02000000,0x400); +reg_write( DDR_REG_BASE +0x5428f*4 +0x02000000,0x1f02); +reg_write( DDR_REG_BASE +0x54290*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54291*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54292*4 +0x02000000,0x3b00); +reg_write( DDR_REG_BASE +0x54293*4 +0x02000000,0x2f0); +reg_write( DDR_REG_BASE +0x54294*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x54295*4 +0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x54296*4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x54297*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54298*4 +0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x54299*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5429a*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5429b*4 +0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x5429c*4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x5429d*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5429e*4 +0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x5429f*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542a0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542a1*4 +0x02000000,0xb900); +reg_write( DDR_REG_BASE +0x542a2*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542a3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542a4*4 +0x02000000,0xba00); +reg_write( DDR_REG_BASE +0x542a5*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542a6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542a7*4 +0x02000000,0xbb00); +reg_write( DDR_REG_BASE +0x542a8*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542a9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542aa*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542ab*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542ac*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542ad*4 +0x02000000,0x6000); +reg_write( DDR_REG_BASE +0x542ae*4 +0x02000000,0x7f0); +reg_write( DDR_REG_BASE +0x542af*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542b0*4 +0x02000000,0x6500); +reg_write( DDR_REG_BASE +0x542b1*4 +0x02000000,0x7f0); +reg_write( DDR_REG_BASE +0x542b2*4 +0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x542b3*4 +0x02000000,0x2601); +reg_write( DDR_REG_BASE +0x542b4*4 +0x02000000,0x7ff); +reg_write( DDR_REG_BASE +0x542b5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542b6*4 +0x02000000,0x2700); +reg_write( DDR_REG_BASE +0x542b7*4 +0x02000000,0x7ff); +reg_write( DDR_REG_BASE +0x542b8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542b9*4 +0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x542ba*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542bb*4 +0x02000000,0x200); +reg_write( DDR_REG_BASE +0x542bc*4 +0x02000000,0x3200); +reg_write( DDR_REG_BASE +0x542bd*4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x542be*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542bf*4 +0x02000000,0x6208); +reg_write( DDR_REG_BASE +0x542c0*4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x542c1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542c2*4 +0x02000000,0x6200); +reg_write( DDR_REG_BASE +0x542c3*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542c4*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542c5*4 +0x02000000,0x6200); +reg_write( DDR_REG_BASE +0x542c6*4 +0x02000000,0x1f4); +reg_write( DDR_REG_BASE +0x542c7*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542c8*4 +0x02000000,0x200); +reg_write( DDR_REG_BASE +0x542c9*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542ca*4 +0x02000000,0x800); +reg_write( DDR_REG_BASE +0x542cb*4 +0x02000000,0x1f02); +reg_write( DDR_REG_BASE +0x542cc*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542cd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542ce*4 +0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x542cf*4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x542d0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542d1*4 +0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x542d2*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542d3*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542d4*4 +0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x542d5*4 +0x02000000,0x1f4); +reg_write( DDR_REG_BASE +0x542d6*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542d7*4 +0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x542d8*4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x542d9*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542da*4 +0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x542db*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542dc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542dd*4 +0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x542de*4 +0x02000000,0x1f4); +reg_write( DDR_REG_BASE +0x542df*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542e0*4 +0x02000000,0xb900); +reg_write( DDR_REG_BASE +0x542e1*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542e2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542e3*4 +0x02000000,0xba00); +reg_write( DDR_REG_BASE +0x542e4*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542e5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542e6*4 +0x02000000,0xbb00); +reg_write( DDR_REG_BASE +0x542e7*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542e8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542e9*4 +0x02000000,0x1100); +reg_write( DDR_REG_BASE +0x542ea*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542eb*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542ec*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x542ed*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542ee*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542ef*4 +0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x542f0*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542f1*4 +0x02000000,0x200); +reg_write( DDR_REG_BASE +0x542f2*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x542f3*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x542f4*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542f5*4 +0x02000000,0x6000); +reg_write( DDR_REG_BASE +0x542f6*4 +0x02000000,0x7f0); +reg_write( DDR_REG_BASE +0x542f7*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x542f8*4 +0x02000000,0x6500); +reg_write( DDR_REG_BASE +0x542f9*4 +0x02000000,0x7f0); +reg_write( DDR_REG_BASE +0x542fa*4 +0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x542fb*4 +0x02000000,0x2601); +reg_write( DDR_REG_BASE +0x542fc*4 +0x02000000,0x7ff); +reg_write( DDR_REG_BASE +0x542fd*4 +0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x542fe*4 +0x02000000,0x27ff); +reg_write( DDR_REG_BASE +0x542ff*4 +0x02000000,0x7ff); +reg_write( DDR_REG_BASE +0x54300*4 +0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x54301*4 +0x02000000,0x62ff); +reg_write( DDR_REG_BASE +0x54302*4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x54303*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54304*4 +0x02000000,0x6200); +reg_write( DDR_REG_BASE +0x54305*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54306*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x54307*4 +0x02000000,0x6200); +reg_write( DDR_REG_BASE +0x54308*4 +0x02000000,0x1f4); +reg_write( DDR_REG_BASE +0x54309*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x5430a*4 +0x02000000,0x3200); +reg_write( DDR_REG_BASE +0x5430b*4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x5430c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5430d*4 +0x02000000,0x208); +reg_write( DDR_REG_BASE +0x5430e*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5430f*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x54310*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x54311*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54312*4 +0x02000000,0x20d); +reg_write( DDR_REG_BASE +0x54313*4 +0x02000000,0x301); +reg_write( DDR_REG_BASE +0x54314*4 +0x02000000,0xc0b); +reg_write( DDR_REG_BASE +0x54315*4 +0x02000000,0x160e); +reg_write( DDR_REG_BASE +0x54316*4 +0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x54317*4 +0x02000000,0x1811); +reg_write( DDR_REG_BASE +0x54318*4 +0x02000000,0xc06); +reg_write( DDR_REG_BASE +0x54319*4 +0x02000000,0x1610); +reg_write( DDR_REG_BASE +0x5431a*4 +0x02000000,0x201c); +reg_write( DDR_REG_BASE +0x5431b*4 +0x02000000,0x2824); +reg_write( DDR_REG_BASE +0x5431c*4 +0x02000000,0xc06); +reg_write( DDR_REG_BASE +0x5431d*4 +0x02000000,0x1812); +reg_write( DDR_REG_BASE +0x5431e*4 +0x02000000,0x241e); +reg_write( DDR_REG_BASE +0x5431f*4 +0x02000000,0x2c28); +reg_write( DDR_REG_BASE +0x54320*4 +0x02000000,0xa06); +reg_write( DDR_REG_BASE +0x54321*4 +0x02000000,0x140e); +reg_write( DDR_REG_BASE +0x54322*4 +0x02000000,0x1c18); +reg_write( DDR_REG_BASE +0x54323*4 +0x02000000,0x2420); +reg_write( DDR_REG_BASE +0x54324*4 +0x02000000,0xa06); +reg_write( DDR_REG_BASE +0x54325*4 +0x02000000,0x1610); +reg_write( DDR_REG_BASE +0x54326*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x54327*4 +0x02000000,0x2824); +reg_write( DDR_REG_BASE +0x54328*4 +0x02000000,0x6e); +reg_write( DDR_REG_BASE +0x54329*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x5432a*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5432b*4 +0x02000000,0xfd); +reg_write( DDR_REG_BASE +0x5432c*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5432d*4 +0x02000000,0xf); +reg_write( DDR_REG_BASE +0x5432e*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5432f*4 +0x02000000,0x7); +reg_write( DDR_REG_BASE +0x54330*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54331*4 +0x02000000,0xe8); +reg_write( DDR_REG_BASE +0x54332*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x54333*4 +0x02000000,0xff); +reg_write( DDR_REG_BASE +0x54334*4 +0x02000000,0xfc); +reg_write( DDR_REG_BASE +0x54335*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x54336*4 +0x02000000,0x404); +reg_write( DDR_REG_BASE +0x54337*4 +0x02000000,0x3a); +reg_write( DDR_REG_BASE +0x54338*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x54339*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x5433a*4 +0x02000000,0x11); +reg_write( DDR_REG_BASE +0x5433b*4 +0x02000000,0x7); +reg_write( DDR_REG_BASE +0x5433c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5433d*4 +0x02000000,0x0); + +reg_write( DDR_REG_BASE + 0x000d0000*4+0x02000000 , 0x00000001 ); + +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000d0099*4 +0x02000000 , 0x00000009 ); +reg_write( DDR_REG_BASE + 0x000d0099*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000d0099*4 +0x02000000 , 0x00000000 ); + +while((train_data&0x7) !=0x07) { + + reg_read ( DDR_REG_BASE + 0x000d0004*4 +0x02000000 , data ); + while((data&0x1) !=0x0) { + reg_read ( DDR_REG_BASE + 0x000d0004*4 +0x02000000 , data ); + } + + + + reg_read ( DDR_REG_BASE + 0x000d0032*4 +0x02000000 , train_data ); + switch(train_data) + { + case 0x00000000: printf("%08X: PMU Major Msg: End of initialization \n",train_data);break; + case 0x00000001: printf("%08X: PMU Major Msg: End of fine write leveling \n",train_data);break; + case 0x00000002: printf("%08X: PMU Major Msg: End of read enable training \n",train_data);break; + case 0x00000003: printf("%08X: PMU Major Msg: End of read delay center optimization \n",train_data);break; + case 0x00000004: printf("%08X: PMU Major Msg: End of write delay center optimization \n",train_data);break; + case 0x00000005: printf("%08X: PMU Major Msg: End of 2D read delay/voltage center optimization \n",train_data);break; + case 0x00000006: printf("%08X: PMU Major Msg: End of 2D write delay /voltage center optimization \n",train_data);break; + case 0x00000007: printf("%08X: PMU Major Msg: Firmware run has completed \n",train_data);break; + case 0x00000008: printf("%08X: PMU Major Msg: Enter streaming message mode \n",train_data);break; + case 0x00000009: printf("%08X: PMU Major Msg: End of max read latency training \n",train_data);break; + case 0x0000000a: printf("%08X: PMU Major Msg: End of read dq deskew training \n",train_data);break; + case 0x0000000b: printf("%08X: PMU Major Msg: End of LCDL offset calibration \n",train_data);break; + case 0x0000000c: printf("%08X: PMU Major Msg: End of LRDIMM Specific training (DWL, MREP, MRD and MWD) \n",train_data);break; + case 0x0000000d: printf("%08X: PMU Major Msg: End of CA training \n",train_data);break; + case 0x000000fd: printf("%08X: PMU Major Msg: End of MPR read delay center optimization \n",train_data);break; + case 0x000000fe: printf("%08X: PMU Major Msg: End of Write leveling coarse delay \n",train_data);break; + case 0x000000ff: printf("%08X: PMU Major Msg: FATAL ERROR. \n",train_data);break; + default: printf("%08X: PMU Major Msg: Un-recognized message... ! \n",train_data);break; + } + + + reg_write( DDR_REG_BASE + 0x000d0031*4 +0x02000000 , 0x00000000 ); + reg_read ( DDR_REG_BASE + 0x000d0004*4 +0x02000000 , data ); + while((data&0x1) ==0x0) { + reg_read ( DDR_REG_BASE + 0x000d0004*4 +0x02000000 , data ); + } + reg_write( DDR_REG_BASE + 0x000d0031*4 +0x02000000 , 0x00000001 ); + +} + +train_data=0; + + +reg_write( DDR_REG_BASE + 0x000d0099*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000000 ); + + +//////////////////////////////2d training begin//////////////////////////////////// + +reg_write( DDR_REG_BASE + 0x000d0000*4+0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE +0x50000*4 +0x02000000,0x204); +reg_write( DDR_REG_BASE +0x50001*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50002*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50003*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50004*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50005*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50006*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50007*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50008*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50009*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5000a*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5000b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5000c*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5000d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5000e*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5000f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50010*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50011*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50012*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50013*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50014*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50015*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50016*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50017*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50018*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50019*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5001a*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5001b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5001c*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5001d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5001e*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5001f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50020*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50021*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50022*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50023*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50024*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50025*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50026*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50027*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50028*4 +0x02000000,0x2069); +reg_write( DDR_REG_BASE +0x50029*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x5002a*4 +0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x5002b*4 +0x02000000,0x7000); +reg_write( DDR_REG_BASE +0x5002c*4 +0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x5002d*4 +0x02000000,0x7000); +reg_write( DDR_REG_BASE +0x5002e*4 +0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x5002f*4 +0x02000000,0x7000); +reg_write( DDR_REG_BASE +0x50030*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50031*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50032*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50033*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50034*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50035*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50036*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50037*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50038*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50039*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50040*4 +0x02000000,0x7054); +reg_write( DDR_REG_BASE +0x50041*4 +0x02000000,0x7ce0); +reg_write( DDR_REG_BASE +0x50042*4 +0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x50043*4 +0x02000000,0x1101); +reg_write( DDR_REG_BASE +0x50044*4 +0x02000000,0x48c); +reg_write( DDR_REG_BASE +0x50045*4 +0x02000000,0x2242); +reg_write( DDR_REG_BASE +0x50046*4 +0x02000000,0x8042); +reg_write( DDR_REG_BASE +0x50047*4 +0x02000000,0x1b01); +reg_write( DDR_REG_BASE +0x50048*4 +0x02000000,0x312); +reg_write( DDR_REG_BASE +0x50049*4 +0x02000000,0xf5fb); +reg_write( DDR_REG_BASE +0x5004a*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5004b*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5004c*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5004d*4 +0x02000000,0xb3c8); +reg_write( DDR_REG_BASE +0x5004e*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5004f*4 +0x02000000,0xb388); +reg_write( DDR_REG_BASE +0x50050*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50051*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50052*4 +0x02000000,0xb348); +reg_write( DDR_REG_BASE +0x50053*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50054*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50055*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50056*4 +0x02000000,0x748d); +reg_write( DDR_REG_BASE +0x50057*4 +0x02000000,0xdd0c); +reg_write( DDR_REG_BASE +0x50058*4 +0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x50059*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5005a*4 +0x02000000,0x748d); +reg_write( DDR_REG_BASE +0x5005b*4 +0x02000000,0xdd08); +reg_write( DDR_REG_BASE +0x5005c*4 +0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x5005d*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5005e*4 +0x02000000,0x748d); +reg_write( DDR_REG_BASE +0x5005f*4 +0x02000000,0x74ad); +reg_write( DDR_REG_BASE +0x50060*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x50061*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50062*4 +0x02000000,0x748d); +reg_write( DDR_REG_BASE +0x50063*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x50064*4 +0x02000000,0xc702); +reg_write( DDR_REG_BASE +0x50065*4 +0x02000000,0xc601); +reg_write( DDR_REG_BASE +0x50066*4 +0x02000000,0x24b0); +reg_write( DDR_REG_BASE +0x50067*4 +0x02000000,0x334d); +reg_write( DDR_REG_BASE +0x50068*4 +0x02000000,0x24b0); +reg_write( DDR_REG_BASE +0x50069*4 +0x02000000,0x331f); +reg_write( DDR_REG_BASE +0x5006a*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5006b*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5006c*4 +0x02000000,0xc5e1); +reg_write( DDR_REG_BASE +0x5006d*4 +0x02000000,0xc6e1); +reg_write( DDR_REG_BASE +0x5006e*4 +0x02000000,0xc7e1); +reg_write( DDR_REG_BASE +0x5006f*4 +0x02000000,0x2107); +reg_write( DDR_REG_BASE +0x50070*4 +0x02000000,0xcb); +reg_write( DDR_REG_BASE +0x50071*4 +0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x50072*4 +0x02000000,0xf040); +reg_write( DDR_REG_BASE +0x50073*4 +0x02000000,0x704d); +reg_write( DDR_REG_BASE +0x50074*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x50075*4 +0x02000000,0x26); +reg_write( DDR_REG_BASE +0x50076*4 +0x02000000,0x232f); +reg_write( DDR_REG_BASE +0x50077*4 +0x02000000,0x12c4); +reg_write( DDR_REG_BASE +0x50078*4 +0x02000000,0x200e); +reg_write( DDR_REG_BASE +0x50079*4 +0x02000000,0x8280); +reg_write( DDR_REG_BASE +0x5007a*4 +0x02000000,0x2203); +reg_write( DDR_REG_BASE +0x5007b*4 +0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x5007c*4 +0x02000000,0xb19); +reg_write( DDR_REG_BASE +0x5007d*4 +0x02000000,0x7de); +reg_write( DDR_REG_BASE +0x5007e*4 +0x02000000,0x220e); +reg_write( DDR_REG_BASE +0x5007f*4 +0x02000000,0x8282); +reg_write( DDR_REG_BASE +0x50080*4 +0x02000000,0x2203); +reg_write( DDR_REG_BASE +0x50081*4 +0x02000000,0x10c3); +reg_write( DDR_REG_BASE +0x50082*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x50083*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50084*4 +0x02000000,0xc5e1); +reg_write( DDR_REG_BASE +0x50085*4 +0x02000000,0xc6e1); +reg_write( DDR_REG_BASE +0x50086*4 +0x02000000,0xc7e1); +reg_write( DDR_REG_BASE +0x50087*4 +0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x50088*4 +0x02000000,0x250a); +reg_write( DDR_REG_BASE +0x50089*4 +0x02000000,0x9080); +reg_write( DDR_REG_BASE +0x5008a*4 +0x02000000,0x23cc); +reg_write( DDR_REG_BASE +0x5008b*4 +0x02000000,0x8021); +reg_write( DDR_REG_BASE +0x5008c*4 +0x02000000,0xf260); +reg_write( DDR_REG_BASE +0x5008d*4 +0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x5008e*4 +0x02000000,0xf20c); +reg_write( DDR_REG_BASE +0x5008f*4 +0x02000000,0x3c); +reg_write( DDR_REG_BASE +0x50090*4 +0x02000000,0x2b); +reg_write( DDR_REG_BASE +0x50091*4 +0x02000000,0xdc40); +reg_write( DDR_REG_BASE +0x50092*4 +0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x50093*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50094*4 +0x02000000,0x212f); +reg_write( DDR_REG_BASE +0x50095*4 +0x02000000,0x804b); +reg_write( DDR_REG_BASE +0x50096*4 +0x02000000,0x7f8); +reg_write( DDR_REG_BASE +0x50097*4 +0x02000000,0xffe3); +reg_write( DDR_REG_BASE +0x50098*4 +0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x50099*4 +0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x5009a*4 +0x02000000,0xdc20); +reg_write( DDR_REG_BASE +0x5009b*4 +0x02000000,0x210a); +reg_write( DDR_REG_BASE +0x5009c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5009d*4 +0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x5009e*4 +0x02000000,0x21); +reg_write( DDR_REG_BASE +0x5009f*4 +0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x500a0*4 +0x02000000,0x21); +reg_write( DDR_REG_BASE +0x500a1*4 +0x02000000,0xf222); +reg_write( DDR_REG_BASE +0x500a2*4 +0x02000000,0x14); +reg_write( DDR_REG_BASE +0x500a3*4 +0x02000000,0x24); +reg_write( DDR_REG_BASE +0x500a4*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x500a5*4 +0x02000000,0x212f); +reg_write( DDR_REG_BASE +0x500a6*4 +0x02000000,0x8040); +reg_write( DDR_REG_BASE +0x500a7*4 +0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x500a8*4 +0x02000000,0x7fe); +reg_write( DDR_REG_BASE +0x500a9*4 +0x02000000,0xffe3); +reg_write( DDR_REG_BASE +0x500aa*4 +0x02000000,0x21c0); +reg_write( DDR_REG_BASE +0x500ab*4 +0x02000000,0x8043); +reg_write( DDR_REG_BASE +0x500ac*4 +0x02000000,0x240a); +reg_write( DDR_REG_BASE +0x500ad*4 +0x02000000,0x7300); +reg_write( DDR_REG_BASE +0x500ae*4 +0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x500af*4 +0x02000000,0x90c0); +reg_write( DDR_REG_BASE +0x500b0*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x500b1*4 +0x02000000,0x46); +reg_write( DDR_REG_BASE +0x500b2*4 +0x02000000,0x22); +reg_write( DDR_REG_BASE +0x500b3*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x500b4*4 +0x02000000,0x20a8); +reg_write( DDR_REG_BASE +0x500b5*4 +0x02000000,0x380); +reg_write( DDR_REG_BASE +0x500b6*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x500b7*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x500b8*4 +0x02000000,0x2101); +reg_write( DDR_REG_BASE +0x500b9*4 +0x02000000,0x8041); +reg_write( DDR_REG_BASE +0x500ba*4 +0x02000000,0x2201); +reg_write( DDR_REG_BASE +0x500bb*4 +0x02000000,0x8082); +reg_write( DDR_REG_BASE +0x500bc*4 +0x02000000,0x25cc); +reg_write( DDR_REG_BASE +0x500bd*4 +0x02000000,0x9086); +reg_write( DDR_REG_BASE +0x500be*4 +0x02000000,0x20c0); +reg_write( DDR_REG_BASE +0x500bf*4 +0x02000000,0x6e); +reg_write( DDR_REG_BASE +0x500c0*4 +0x02000000,0x22c2); +reg_write( DDR_REG_BASE +0x500c1*4 +0x02000000,0x34e); +reg_write( DDR_REG_BASE +0x500c2*4 +0x02000000,0x7075); +reg_write( DDR_REG_BASE +0x500c3*4 +0x02000000,0xf22f); +reg_write( DDR_REG_BASE +0x500c4*4 +0x02000000,0xf645); +reg_write( DDR_REG_BASE +0x500c5*4 +0x02000000,0x220e); +reg_write( DDR_REG_BASE +0x500c6*4 +0x02000000,0x8282); +reg_write( DDR_REG_BASE +0x500c7*4 +0x02000000,0x2203); +reg_write( DDR_REG_BASE +0x500c8*4 +0x02000000,0x10c3); +reg_write( DDR_REG_BASE +0x500c9*4 +0x02000000,0x232f); +reg_write( DDR_REG_BASE +0x500ca*4 +0x02000000,0x92c0); +reg_write( DDR_REG_BASE +0x500cb*4 +0x02000000,0x4e); +reg_write( DDR_REG_BASE +0x500cc*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x500cd*4 +0x02000000,0x200e); +reg_write( DDR_REG_BASE +0x500ce*4 +0x02000000,0x8280); +reg_write( DDR_REG_BASE +0x500cf*4 +0x02000000,0x47); +reg_write( DDR_REG_BASE +0x500d0*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x500d1*4 +0x02000000,0x2203); +reg_write( DDR_REG_BASE +0x500d2*4 +0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x500d3*4 +0x02000000,0x20a8); +reg_write( DDR_REG_BASE +0x500d4*4 +0x02000000,0x580); +reg_write( DDR_REG_BASE +0x500d5*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x500d6*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x500d7*4 +0x02000000,0x2101); +reg_write( DDR_REG_BASE +0x500d8*4 +0x02000000,0x8041); +reg_write( DDR_REG_BASE +0x500d9*4 +0x02000000,0x2201); +reg_write( DDR_REG_BASE +0x500da*4 +0x02000000,0x8082); +reg_write( DDR_REG_BASE +0x500db*4 +0x02000000,0x2301); +reg_write( DDR_REG_BASE +0x500dc*4 +0x02000000,0xc3); +reg_write( DDR_REG_BASE +0x500dd*4 +0x02000000,0x2202); +reg_write( DDR_REG_BASE +0x500de*4 +0x02000000,0x8342); +reg_write( DDR_REG_BASE +0x500df*4 +0x02000000,0x2303); +reg_write( DDR_REG_BASE +0x500e0*4 +0x02000000,0x8383); +reg_write( DDR_REG_BASE +0x500e1*4 +0x02000000,0xf746); +reg_write( DDR_REG_BASE +0x500e2*4 +0x02000000,0x2200); +reg_write( DDR_REG_BASE +0x500e3*4 +0x02000000,0x8342); +reg_write( DDR_REG_BASE +0x500e4*4 +0x02000000,0x2301); +reg_write( DDR_REG_BASE +0x500e5*4 +0x02000000,0x8383); +reg_write( DDR_REG_BASE +0x500e6*4 +0x02000000,0x20c0); +reg_write( DDR_REG_BASE +0x500e7*4 +0x02000000,0x66); +reg_write( DDR_REG_BASE +0x500e8*4 +0x02000000,0x7075); +reg_write( DDR_REG_BASE +0x500e9*4 +0x02000000,0x12); +reg_write( DDR_REG_BASE +0x500ea*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x500eb*4 +0x02000000,0xf1da); +reg_write( DDR_REG_BASE +0x500ec*4 +0x02000000,0x4241); +reg_write( DDR_REG_BASE +0x500ed*4 +0x02000000,0x4341); +reg_write( DDR_REG_BASE +0x500ee*4 +0x02000000,0x6a09); +reg_write( DDR_REG_BASE +0x500ef*4 +0x02000000,0x212f); +reg_write( DDR_REG_BASE +0x500f0*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x500f1*4 +0x02000000,0xc7c1); +reg_write( DDR_REG_BASE +0x500f2*4 +0x02000000,0xc6c1); +reg_write( DDR_REG_BASE +0x500f3*4 +0x02000000,0xc5c1); +reg_write( DDR_REG_BASE +0x500f4*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x500f5*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x500f6*4 +0x02000000,0x2244); +reg_write( DDR_REG_BASE +0x500f7*4 +0x02000000,0x8ffc); +reg_write( DDR_REG_BASE +0x500f8*4 +0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x500f9*4 +0x02000000,0x7000); +reg_write( DDR_REG_BASE +0x500fa*4 +0x02000000,0x20e8); +reg_write( DDR_REG_BASE +0x500fb*4 +0x02000000,0x1a2); +reg_write( DDR_REG_BASE +0x500fc*4 +0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x500fd*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x500fe*4 +0x02000000,0x212f); +reg_write( DDR_REG_BASE +0x500ff*4 +0x02000000,0x4b); +reg_write( DDR_REG_BASE +0x50100*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50101*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50102*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50103*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50104*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50105*4 +0x02000000,0x704d); +reg_write( DDR_REG_BASE +0x50106*4 +0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x50107*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x50108*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50109*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x5010a*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x5010b*4 +0x02000000,0x206a); +reg_write( DDR_REG_BASE +0x5010c*4 +0x02000000,0x280); +reg_write( DDR_REG_BASE +0x5010d*4 +0x02000000,0xb88d); +reg_write( DDR_REG_BASE +0x5010e*4 +0x02000000,0x2029); +reg_write( DDR_REG_BASE +0x5010f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50110*4 +0x02000000,0x44db); +reg_write( DDR_REG_BASE +0x50111*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50112*4 +0x02000000,0x4000); +reg_write( DDR_REG_BASE +0x50113*4 +0x02000000,0x42db); +reg_write( DDR_REG_BASE +0x50114*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50115*4 +0x02000000,0x400); +reg_write( DDR_REG_BASE +0x50116*4 +0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x50117*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50118*4 +0x02000000,0x2022); +reg_write( DDR_REG_BASE +0x50119*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5011a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5011b*4 +0x02000000,0x2548); +reg_write( DDR_REG_BASE +0x5011c*4 +0x02000000,0x2069); +reg_write( DDR_REG_BASE +0x5011d*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x5011e*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5011f*4 +0x02000000,0xf1fe); +reg_write( DDR_REG_BASE +0x50120*4 +0x02000000,0xc3e1); +reg_write( DDR_REG_BASE +0x50121*4 +0x02000000,0xc2e1); +reg_write( DDR_REG_BASE +0x50122*4 +0x02000000,0xc1e1); +reg_write( DDR_REG_BASE +0x50123*4 +0x02000000,0xc0e1); +reg_write( DDR_REG_BASE +0x50124*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x50125*4 +0x02000000,0xc5e1); +reg_write( DDR_REG_BASE +0x50126*4 +0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x50127*4 +0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x50128*4 +0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x50129*4 +0x02000000,0xdc14); +reg_write( DDR_REG_BASE +0x5012a*4 +0x02000000,0x66b); +reg_write( DDR_REG_BASE +0x5012b*4 +0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x5012c*4 +0x02000000,0xda25); +reg_write( DDR_REG_BASE +0x5012d*4 +0x02000000,0xba9f); +reg_write( DDR_REG_BASE +0x5012e*4 +0x02000000,0x8a60); +reg_write( DDR_REG_BASE +0x5012f*4 +0x02000000,0x1233); +reg_write( DDR_REG_BASE +0x50130*4 +0x02000000,0x80); +reg_write( DDR_REG_BASE +0x50131*4 +0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x50132*4 +0x02000000,0x1aea); +reg_write( DDR_REG_BASE +0x50133*4 +0x02000000,0x8002); +reg_write( DDR_REG_BASE +0x50134*4 +0x02000000,0x12ed); +reg_write( DDR_REG_BASE +0x50135*4 +0x02000000,0x8080); +reg_write( DDR_REG_BASE +0x50136*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x50137*4 +0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x50138*4 +0x02000000,0xf20d); +reg_write( DDR_REG_BASE +0x50139*4 +0x02000000,0xc085); +reg_write( DDR_REG_BASE +0x5013a*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5013b*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x5013c*4 +0x02000000,0xb9a); +reg_write( DDR_REG_BASE +0x5013d*4 +0x02000000,0x260); +reg_write( DDR_REG_BASE +0x5013e*4 +0x02000000,0xc185); +reg_write( DDR_REG_BASE +0x5013f*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50140*4 +0x02000000,0x402); +reg_write( DDR_REG_BASE +0x50141*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50142*4 +0x02000000,0xf6e); +reg_write( DDR_REG_BASE +0x50143*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50144*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50145*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50146*4 +0x02000000,0xa3e); +reg_write( DDR_REG_BASE +0x50147*4 +0x02000000,0x220); +reg_write( DDR_REG_BASE +0x50148*4 +0x02000000,0x1a10); +reg_write( DDR_REG_BASE +0x50149*4 +0x02000000,0x3003); +reg_write( DDR_REG_BASE +0x5014a*4 +0x02000000,0xade); +reg_write( DDR_REG_BASE +0x5014b*4 +0x02000000,0x260); +reg_write( DDR_REG_BASE +0x5014c*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5014d*4 +0x02000000,0x25ab); +reg_write( DDR_REG_BASE +0x5014e*4 +0x02000000,0x10c4); +reg_write( DDR_REG_BASE +0x5014f*4 +0x02000000,0x7fff); +reg_write( DDR_REG_BASE +0x50150*4 +0x02000000,0xf1ff); +reg_write( DDR_REG_BASE +0x50151*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50152*4 +0x02000000,0xb8e6); +reg_write( DDR_REG_BASE +0x50153*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50154*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50155*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50156*4 +0x02000000,0xb8c2); +reg_write( DDR_REG_BASE +0x50157*4 +0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x50158*4 +0x02000000,0xf403); +reg_write( DDR_REG_BASE +0x50159*4 +0x02000000,0x7914); +reg_write( DDR_REG_BASE +0x5015a*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x5015b*4 +0x02000000,0x7915); +reg_write( DDR_REG_BASE +0x5015c*4 +0x02000000,0x909); +reg_write( DDR_REG_BASE +0x5015d*4 +0x02000000,0x354); +reg_write( DDR_REG_BASE +0x5015e*4 +0x02000000,0x762c); +reg_write( DDR_REG_BASE +0x5015f*4 +0x02000000,0x7915); +reg_write( DDR_REG_BASE +0x50160*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50161*4 +0x02000000,0x6901); +reg_write( DDR_REG_BASE +0x50162*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x50163*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50164*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x50165*4 +0x02000000,0x8a20); +reg_write( DDR_REG_BASE +0x50166*4 +0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x50167*4 +0x02000000,0xc81); +reg_write( DDR_REG_BASE +0x50168*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x50169*4 +0x02000000,0x8a21); +reg_write( DDR_REG_BASE +0x5016a*4 +0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x5016b*4 +0x02000000,0x641); +reg_write( DDR_REG_BASE +0x5016c*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x5016d*4 +0x02000000,0x8903); +reg_write( DDR_REG_BASE +0x5016e*4 +0x02000000,0xb8e6); +reg_write( DDR_REG_BASE +0x5016f*4 +0x02000000,0x8902); +reg_write( DDR_REG_BASE +0x50170*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50171*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x50172*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50173*4 +0x02000000,0x1c); +reg_write( DDR_REG_BASE +0x50174*4 +0x02000000,0xb8c2); +reg_write( DDR_REG_BASE +0x50175*4 +0x02000000,0xf409); +reg_write( DDR_REG_BASE +0x50176*4 +0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x50177*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50178*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50179*4 +0x02000000,0x540); +reg_write( DDR_REG_BASE +0x5017a*4 +0x02000000,0xf209); +reg_write( DDR_REG_BASE +0x5017b*4 +0x02000000,0xe108); +reg_write( DDR_REG_BASE +0x5017c*4 +0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x5017d*4 +0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x5017e*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5017f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50180*4 +0x02000000,0x530); +reg_write( DDR_REG_BASE +0x50181*4 +0x02000000,0xf203); +reg_write( DDR_REG_BASE +0x50182*4 +0x02000000,0xe108); +reg_write( DDR_REG_BASE +0x50183*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50184*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50185*4 +0x02000000,0x8900); +reg_write( DDR_REG_BASE +0x50186*4 +0x02000000,0xc0e2); +reg_write( DDR_REG_BASE +0x50187*4 +0x02000000,0x2053); +reg_write( DDR_REG_BASE +0x50188*4 +0x02000000,0x14c); +reg_write( DDR_REG_BASE +0x50189*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5018a*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5018b*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5018c*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5018d*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5018e*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5018f*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x50190*4 +0x02000000,0x4d); +reg_write( DDR_REG_BASE +0x50191*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50192*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50193*4 +0x02000000,0xf00b); +reg_write( DDR_REG_BASE +0x50194*4 +0x02000000,0x1070); +reg_write( DDR_REG_BASE +0x50195*4 +0x02000000,0x83); +reg_write( DDR_REG_BASE +0x50196*4 +0x02000000,0xd19); +reg_write( DDR_REG_BASE +0x50197*4 +0x02000000,0x10e0); +reg_write( DDR_REG_BASE +0x50198*4 +0x02000000,0x792f); +reg_write( DDR_REG_BASE +0x50199*4 +0x02000000,0x106e); +reg_write( DDR_REG_BASE +0x5019a*4 +0x02000000,0x80); +reg_write( DDR_REG_BASE +0x5019b*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x5019c*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x5019d*4 +0x02000000,0x784f); +reg_write( DDR_REG_BASE +0x5019e*4 +0x02000000,0x8ed); +reg_write( DDR_REG_BASE +0x5019f*4 +0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x501a0*4 +0x02000000,0x7043); +reg_write( DDR_REG_BASE +0x501a1*4 +0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x501a2*4 +0x02000000,0x6199); +reg_write( DDR_REG_BASE +0x501a3*4 +0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x501a4*4 +0x02000000,0xc4c2); +reg_write( DDR_REG_BASE +0x501a5*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x501a6*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x501a7*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x501a8*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x501a9*4 +0x02000000,0xc1b6); +reg_write( DDR_REG_BASE +0x501aa*4 +0x02000000,0x4548); +reg_write( DDR_REG_BASE +0x501ab*4 +0x02000000,0xc153); +reg_write( DDR_REG_BASE +0x501ac*4 +0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x501ad*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x501ae*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x501af*4 +0x02000000,0x186); +reg_write( DDR_REG_BASE +0x501b0*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x501b1*4 +0x02000000,0xe92); +reg_write( DDR_REG_BASE +0x501b2*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x501b3*4 +0x02000000,0xc354); +reg_write( DDR_REG_BASE +0x501b4*4 +0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x501b5*4 +0x02000000,0xf041); +reg_write( DDR_REG_BASE +0x501b6*4 +0x02000000,0x4261); +reg_write( DDR_REG_BASE +0x501b7*4 +0x02000000,0xf015); +reg_write( DDR_REG_BASE +0x501b8*4 +0x02000000,0xc014); +reg_write( DDR_REG_BASE +0x501b9*4 +0x02000000,0x819); +reg_write( DDR_REG_BASE +0x501ba*4 +0x02000000,0xb0); +reg_write( DDR_REG_BASE +0x501bb*4 +0x02000000,0xc08e); +reg_write( DDR_REG_BASE +0x501bc*4 +0x02000000,0xc014); +reg_write( DDR_REG_BASE +0x501bd*4 +0x02000000,0x87f); +reg_write( DDR_REG_BASE +0x501be*4 +0x02000000,0x71); +reg_write( DDR_REG_BASE +0x501bf*4 +0x02000000,0xc38e); +reg_write( DDR_REG_BASE +0x501c0*4 +0x02000000,0x6548); +reg_write( DDR_REG_BASE +0x501c1*4 +0x02000000,0x7b34); +reg_write( DDR_REG_BASE +0x501c2*4 +0x02000000,0xb300); +reg_write( DDR_REG_BASE +0x501c3*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x501c4*4 +0x02000000,0x25f4); +reg_write( DDR_REG_BASE +0x501c5*4 +0x02000000,0x1083); +reg_write( DDR_REG_BASE +0x501c6*4 +0x02000000,0x7834); +reg_write( DDR_REG_BASE +0x501c7*4 +0x02000000,0xb060); +reg_write( DDR_REG_BASE +0x501c8*4 +0x02000000,0xc013); +reg_write( DDR_REG_BASE +0x501c9*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x501ca*4 +0x02000000,0x621a); +reg_write( DDR_REG_BASE +0x501cb*4 +0x02000000,0x9dd); +reg_write( DDR_REG_BASE +0x501cc*4 +0x02000000,0x8294); +reg_write( DDR_REG_BASE +0x501cd*4 +0x02000000,0x4183); +reg_write( DDR_REG_BASE +0x501ce*4 +0x02000000,0x911c); +reg_write( DDR_REG_BASE +0x501cf*4 +0x02000000,0x1446); +reg_write( DDR_REG_BASE +0x501d0*4 +0x02000000,0x3103); +reg_write( DDR_REG_BASE +0x501d1*4 +0x02000000,0x915f); +reg_write( DDR_REG_BASE +0x501d2*4 +0x02000000,0xc055); +reg_write( DDR_REG_BASE +0x501d3*4 +0x02000000,0x1448); +reg_write( DDR_REG_BASE +0x501d4*4 +0x02000000,0x3101); +reg_write( DDR_REG_BASE +0x501d5*4 +0x02000000,0x144a); +reg_write( DDR_REG_BASE +0x501d6*4 +0x02000000,0x3100); +reg_write( DDR_REG_BASE +0x501d7*4 +0x02000000,0x143a); +reg_write( DDR_REG_BASE +0x501d8*4 +0x02000000,0x311f); +reg_write( DDR_REG_BASE +0x501d9*4 +0x02000000,0x143c); +reg_write( DDR_REG_BASE +0x501da*4 +0x02000000,0x311e); +reg_write( DDR_REG_BASE +0x501db*4 +0x02000000,0x1440); +reg_write( DDR_REG_BASE +0x501dc*4 +0x02000000,0x310f); +reg_write( DDR_REG_BASE +0x501dd*4 +0x02000000,0x1442); +reg_write( DDR_REG_BASE +0x501de*4 +0x02000000,0x310e); +reg_write( DDR_REG_BASE +0x501df*4 +0x02000000,0x1444); +reg_write( DDR_REG_BASE +0x501e0*4 +0x02000000,0x310c); +reg_write( DDR_REG_BASE +0x501e1*4 +0x02000000,0xc346); +reg_write( DDR_REG_BASE +0x501e2*4 +0x02000000,0xc315); +reg_write( DDR_REG_BASE +0x501e3*4 +0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x501e4*4 +0x02000000,0xc147); +reg_write( DDR_REG_BASE +0x501e5*4 +0x02000000,0xc242); +reg_write( DDR_REG_BASE +0x501e6*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x501e7*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x501e8*4 +0x02000000,0x187); +reg_write( DDR_REG_BASE +0x501e9*4 +0x02000000,0xb); +reg_write( DDR_REG_BASE +0x501ea*4 +0x02000000,0xc445); +reg_write( DDR_REG_BASE +0x501eb*4 +0x02000000,0xc644); +reg_write( DDR_REG_BASE +0x501ec*4 +0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x501ed*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x501ee*4 +0x02000000,0x3780); +reg_write( DDR_REG_BASE +0x501ef*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x501f0*4 +0x02000000,0x37c0); +reg_write( DDR_REG_BASE +0x501f1*4 +0x02000000,0xe12); +reg_write( DDR_REG_BASE +0x501f2*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x501f3*4 +0x02000000,0x4261); +reg_write( DDR_REG_BASE +0x501f4*4 +0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x501f5*4 +0x02000000,0xc013); +reg_write( DDR_REG_BASE +0x501f6*4 +0x02000000,0x232f); +reg_write( DDR_REG_BASE +0x501f7*4 +0x02000000,0x16c8); +reg_write( DDR_REG_BASE +0x501f8*4 +0x02000000,0xb7d); +reg_write( DDR_REG_BASE +0x501f9*4 +0x02000000,0x9024); +reg_write( DDR_REG_BASE +0x501fa*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x501fb*4 +0x02000000,0xc0b6); +reg_write( DDR_REG_BASE +0x501fc*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x501fd*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x501fe*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x501ff*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50200*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50201*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50202*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x50203*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50204*4 +0x02000000,0x102); +reg_write( DDR_REG_BASE +0x50205*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50206*4 +0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x50207*4 +0x02000000,0x4308); +reg_write( DDR_REG_BASE +0x50208*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50209*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x5020a*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x5020b*4 +0x02000000,0x1e4); +reg_write( DDR_REG_BASE +0x5020c*4 +0x02000000,0x218c); +reg_write( DDR_REG_BASE +0x5020d*4 +0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x5020e*4 +0x02000000,0xb6a0); +reg_write( DDR_REG_BASE +0x5020f*4 +0x02000000,0xb6a1); +reg_write( DDR_REG_BASE +0x50210*4 +0x02000000,0xb6a2); +reg_write( DDR_REG_BASE +0x50211*4 +0x02000000,0xf224); +reg_write( DDR_REG_BASE +0x50212*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50213*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50214*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50215*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50216*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50217*4 +0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x50218*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50219*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5021a*4 +0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x5021b*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5021c*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5021d*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x5021e*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x5021f*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50220*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50221*4 +0x02000000,0x669); +reg_write( DDR_REG_BASE +0x50222*4 +0x02000000,0x8881); +reg_write( DDR_REG_BASE +0x50223*4 +0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x50224*4 +0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x50225*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50226*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x50227*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50228*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x50229*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5022a*4 +0x02000000,0x7a65); +reg_write( DDR_REG_BASE +0x5022b*4 +0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x5022c*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x5022d*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x5022e*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x5022f*4 +0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x50230*4 +0x02000000,0xceb); +reg_write( DDR_REG_BASE +0x50231*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x50232*4 +0x02000000,0x88e); +reg_write( DDR_REG_BASE +0x50233*4 +0x02000000,0x1c0); +reg_write( DDR_REG_BASE +0x50234*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x50235*4 +0x02000000,0x21a); +reg_write( DDR_REG_BASE +0x50236*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50237*4 +0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x50238*4 +0x02000000,0x2a); +reg_write( DDR_REG_BASE +0x50239*4 +0x02000000,0x1efc); +reg_write( DDR_REG_BASE +0x5023a*4 +0x02000000,0x92c4); +reg_write( DDR_REG_BASE +0x5023b*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x5023c*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5023d*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5023e*4 +0x02000000,0x4ba); +reg_write( DDR_REG_BASE +0x5023f*4 +0x02000000,0xa8a0); +reg_write( DDR_REG_BASE +0x50240*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50241*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50242*4 +0x02000000,0xfac); +reg_write( DDR_REG_BASE +0x50243*4 +0x02000000,0xb101); +reg_write( DDR_REG_BASE +0x50244*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50245*4 +0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x50246*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50247*4 +0x02000000,0x7210); +reg_write( DDR_REG_BASE +0x50248*4 +0x02000000,0x20e0); +reg_write( DDR_REG_BASE +0x50249*4 +0x02000000,0x7ca); +reg_write( DDR_REG_BASE +0x5024a*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5024b*4 +0x02000000,0x7101); +reg_write( DDR_REG_BASE +0x5024c*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x5024d*4 +0x02000000,0x1d6); +reg_write( DDR_REG_BASE +0x5024e*4 +0x02000000,0x9f3); +reg_write( DDR_REG_BASE +0x5024f*4 +0x02000000,0x803e); +reg_write( DDR_REG_BASE +0x50250*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x50251*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50252*4 +0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x50253*4 +0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x50254*4 +0x02000000,0xec6); +reg_write( DDR_REG_BASE +0x50255*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50256*4 +0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x50257*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x50258*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x50259*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5025a*4 +0x02000000,0xf2); +reg_write( DDR_REG_BASE +0x5025b*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x5025c*4 +0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x5025d*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x5025e*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x5025f*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50260*4 +0x02000000,0x7784); +reg_write( DDR_REG_BASE +0x50261*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x50262*4 +0x02000000,0x1e2); +reg_write( DDR_REG_BASE +0x50263*4 +0x02000000,0xf36); +reg_write( DDR_REG_BASE +0x50264*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50265*4 +0x02000000,0x760c); +reg_write( DDR_REG_BASE +0x50266*4 +0x02000000,0xb17); +reg_write( DDR_REG_BASE +0x50267*4 +0x02000000,0x1030); +reg_write( DDR_REG_BASE +0x50268*4 +0x02000000,0x1d10); +reg_write( DDR_REG_BASE +0x50269*4 +0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x5026a*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5026b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5026c*4 +0x02000000,0x61a8); +reg_write( DDR_REG_BASE +0x5026d*4 +0x02000000,0xfb6); +reg_write( DDR_REG_BASE +0x5026e*4 +0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x5026f*4 +0x02000000,0x1d10); +reg_write( DDR_REG_BASE +0x50270*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x50271*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x50272*4 +0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x50273*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50274*4 +0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x50275*4 +0x02000000,0xca11); +reg_write( DDR_REG_BASE +0x50276*4 +0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x50277*4 +0x02000000,0xfba); +reg_write( DDR_REG_BASE +0x50278*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50279*4 +0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x5027a*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x5027b*4 +0x02000000,0xc813); +reg_write( DDR_REG_BASE +0x5027c*4 +0x02000000,0xdf3); +reg_write( DDR_REG_BASE +0x5027d*4 +0x02000000,0x9024); +reg_write( DDR_REG_BASE +0x5027e*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5027f*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x50280*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50281*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50282*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50283*4 +0x02000000,0xc1a6); +reg_write( DDR_REG_BASE +0x50284*4 +0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x50285*4 +0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x50286*4 +0x02000000,0xc20b); +reg_write( DDR_REG_BASE +0x50287*4 +0x02000000,0xc345); +reg_write( DDR_REG_BASE +0x50288*4 +0x02000000,0xdb7f); +reg_write( DDR_REG_BASE +0x50289*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5028a*4 +0x02000000,0x7b44); +reg_write( DDR_REG_BASE +0x5028b*4 +0x02000000,0xd84b); +reg_write( DDR_REG_BASE +0x5028c*4 +0x02000000,0x2338); +reg_write( DDR_REG_BASE +0x5028d*4 +0x02000000,0xf); +reg_write( DDR_REG_BASE +0x5028e*4 +0x02000000,0x279a); +reg_write( DDR_REG_BASE +0x5028f*4 +0x02000000,0x1002); +reg_write( DDR_REG_BASE +0x50290*4 +0x02000000,0xbae6); +reg_write( DDR_REG_BASE +0x50291*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x50292*4 +0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x50293*4 +0x02000000,0x234f); +reg_write( DDR_REG_BASE +0x50294*4 +0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x50295*4 +0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x50296*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x50297*4 +0x02000000,0xe4cf); +reg_write( DDR_REG_BASE +0x50298*4 +0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x50299*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x5029a*4 +0x02000000,0xe3d1); +reg_write( DDR_REG_BASE +0x5029b*4 +0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x5029c*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x5029d*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x5029e*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5029f*4 +0x02000000,0x7083); +reg_write( DDR_REG_BASE +0x502a0*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x502a1*4 +0x02000000,0x4ba); +reg_write( DDR_REG_BASE +0x502a2*4 +0x02000000,0x1400); +reg_write( DDR_REG_BASE +0x502a3*4 +0x02000000,0x301f); +reg_write( DDR_REG_BASE +0x502a4*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x502a5*4 +0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x502a6*4 +0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x502a7*4 +0x02000000,0x2642); +reg_write( DDR_REG_BASE +0x502a8*4 +0x02000000,0x304b); +reg_write( DDR_REG_BASE +0x502a9*4 +0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x502aa*4 +0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x502ab*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x502ac*4 +0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x502ad*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x502ae*4 +0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x502af*4 +0x02000000,0xb51); +reg_write( DDR_REG_BASE +0x502b0*4 +0x02000000,0x16b5); +reg_write( DDR_REG_BASE +0x502b1*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x502b2*4 +0x02000000,0xdb50); +reg_write( DDR_REG_BASE +0x502b3*4 +0x02000000,0xc341); +reg_write( DDR_REG_BASE +0x502b4*4 +0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x502b5*4 +0x02000000,0xd810); +reg_write( DDR_REG_BASE +0x502b6*4 +0x02000000,0xde30); +reg_write( DDR_REG_BASE +0x502b7*4 +0x02000000,0xdd60); +reg_write( DDR_REG_BASE +0x502b8*4 +0x02000000,0x4378); +reg_write( DDR_REG_BASE +0x502b9*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x502ba*4 +0x02000000,0x2025); +reg_write( DDR_REG_BASE +0x502bb*4 +0x02000000,0x2c0); +reg_write( DDR_REG_BASE +0x502bc*4 +0x02000000,0xf01a); +reg_write( DDR_REG_BASE +0x502bd*4 +0x02000000,0xf01a); +reg_write( DDR_REG_BASE +0x502be*4 +0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x502bf*4 +0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x502c0*4 +0x02000000,0xf05c); +reg_write( DDR_REG_BASE +0x502c1*4 +0x02000000,0xf019); +reg_write( DDR_REG_BASE +0x502c2*4 +0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x502c3*4 +0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x502c4*4 +0x02000000,0xf045); +reg_write( DDR_REG_BASE +0x502c5*4 +0x02000000,0xf048); +reg_write( DDR_REG_BASE +0x502c6*4 +0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x502c7*4 +0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x502c8*4 +0x02000000,0xf047); +reg_write( DDR_REG_BASE +0x502c9*4 +0x02000000,0xf03b); +reg_write( DDR_REG_BASE +0x502ca*4 +0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x502cb*4 +0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x502cc*4 +0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x502cd*4 +0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x502ce*4 +0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x502cf*4 +0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x502d0*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x502d1*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x502d2*4 +0x02000000,0xf03f); +reg_write( DDR_REG_BASE +0x502d3*4 +0x02000000,0xf034); +reg_write( DDR_REG_BASE +0x502d4*4 +0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x502d5*4 +0x02000000,0xf0a8); +reg_write( DDR_REG_BASE +0x502d6*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x502d7*4 +0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x502d8*4 +0x02000000,0xdb10); +reg_write( DDR_REG_BASE +0x502d9*4 +0x02000000,0x264c); +reg_write( DDR_REG_BASE +0x502da*4 +0x02000000,0xb640); +reg_write( DDR_REG_BASE +0x502db*4 +0x02000000,0x14a); +reg_write( DDR_REG_BASE +0x502dc*4 +0x02000000,0x2d); +reg_write( DDR_REG_BASE +0x502dd*4 +0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x502de*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x502df*4 +0x02000000,0x748d); +reg_write( DDR_REG_BASE +0x502e0*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x502e1*4 +0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x502e2*4 +0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x502e3*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x502e4*4 +0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x502e5*4 +0x02000000,0x2025); +reg_write( DDR_REG_BASE +0x502e6*4 +0x02000000,0x780); +reg_write( DDR_REG_BASE +0x502e7*4 +0x02000000,0xf036); +reg_write( DDR_REG_BASE +0x502e8*4 +0x02000000,0xf02c); +reg_write( DDR_REG_BASE +0x502e9*4 +0x02000000,0xf02b); +reg_write( DDR_REG_BASE +0x502ea*4 +0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x502eb*4 +0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x502ec*4 +0x02000000,0xf093); +reg_write( DDR_REG_BASE +0x502ed*4 +0x02000000,0xf099); +reg_write( DDR_REG_BASE +0x502ee*4 +0x02000000,0xf093); +reg_write( DDR_REG_BASE +0x502ef*4 +0x02000000,0xf015); +reg_write( DDR_REG_BASE +0x502f0*4 +0x02000000,0xf019); +reg_write( DDR_REG_BASE +0x502f1*4 +0x02000000,0xf01c); +reg_write( DDR_REG_BASE +0x502f2*4 +0x02000000,0xf091); +reg_write( DDR_REG_BASE +0x502f3*4 +0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x502f4*4 +0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x502f5*4 +0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x502f6*4 +0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x502f7*4 +0x02000000,0xf089); +reg_write( DDR_REG_BASE +0x502f8*4 +0x02000000,0xf087); +reg_write( DDR_REG_BASE +0x502f9*4 +0x02000000,0xf087); +reg_write( DDR_REG_BASE +0x502fa*4 +0x02000000,0xf085); +reg_write( DDR_REG_BASE +0x502fb*4 +0x02000000,0xf085); +reg_write( DDR_REG_BASE +0x502fc*4 +0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x502fd*4 +0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x502fe*4 +0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x502ff*4 +0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x50300*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x50301*4 +0x02000000,0xdb07); +reg_write( DDR_REG_BASE +0x50302*4 +0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x50303*4 +0x02000000,0xc701); +reg_write( DDR_REG_BASE +0x50304*4 +0x02000000,0x758d); +reg_write( DDR_REG_BASE +0x50305*4 +0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x50306*4 +0x02000000,0x758d); +reg_write( DDR_REG_BASE +0x50307*4 +0x02000000,0x47a9); +reg_write( DDR_REG_BASE +0x50308*4 +0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x50309*4 +0x02000000,0x758d); +reg_write( DDR_REG_BASE +0x5030a*4 +0x02000000,0x47c9); +reg_write( DDR_REG_BASE +0x5030b*4 +0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x5030c*4 +0x02000000,0x718d); +reg_write( DDR_REG_BASE +0x5030d*4 +0x02000000,0x476b); +reg_write( DDR_REG_BASE +0x5030e*4 +0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x5030f*4 +0x02000000,0x768d); +reg_write( DDR_REG_BASE +0x50310*4 +0x02000000,0xf00b); +reg_write( DDR_REG_BASE +0x50311*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x50312*4 +0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x50313*4 +0x02000000,0x736c); +reg_write( DDR_REG_BASE +0x50314*4 +0x02000000,0xe0d); +reg_write( DDR_REG_BASE +0x50315*4 +0x02000000,0x30d1); +reg_write( DDR_REG_BASE +0x50316*4 +0x02000000,0xc402); +reg_write( DDR_REG_BASE +0x50317*4 +0x02000000,0x249a); +reg_write( DDR_REG_BASE +0x50318*4 +0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x50319*4 +0x02000000,0x7a85); +reg_write( DDR_REG_BASE +0x5031a*4 +0x02000000,0x4468); +reg_write( DDR_REG_BASE +0x5031b*4 +0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x5031c*4 +0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x5031d*4 +0x02000000,0xffd); +reg_write( DDR_REG_BASE +0x5031e*4 +0x02000000,0x7b24); +reg_write( DDR_REG_BASE +0x5031f*4 +0x02000000,0x783d); +reg_write( DDR_REG_BASE +0x50320*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x50321*4 +0x02000000,0xc0b); +reg_write( DDR_REG_BASE +0x50322*4 +0x02000000,0xe3b0); +reg_write( DDR_REG_BASE +0x50323*4 +0x02000000,0xdb58); +reg_write( DDR_REG_BASE +0x50324*4 +0x02000000,0x23cf); +reg_write( DDR_REG_BASE +0x50325*4 +0x02000000,0x11e1); +reg_write( DDR_REG_BASE +0x50326*4 +0x02000000,0x7b24); +reg_write( DDR_REG_BASE +0x50327*4 +0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x50328*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50329*4 +0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x5032a*4 +0x02000000,0x2c3); +reg_write( DDR_REG_BASE +0x5032b*4 +0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x5032c*4 +0x02000000,0x7b05); +reg_write( DDR_REG_BASE +0x5032d*4 +0x02000000,0x783d); +reg_write( DDR_REG_BASE +0x5032e*4 +0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x5032f*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50330*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50331*4 +0x02000000,0xc405); +reg_write( DDR_REG_BASE +0x50332*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50333*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x50334*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50335*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50336*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x50337*4 +0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x50338*4 +0x02000000,0x7c65); +reg_write( DDR_REG_BASE +0x50339*4 +0x02000000,0x232f); +reg_write( DDR_REG_BASE +0x5033a*4 +0x02000000,0x17c0); +reg_write( DDR_REG_BASE +0x5033b*4 +0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x5033c*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x5033d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5033e*4 +0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x5033f*4 +0x02000000,0x10c0); +reg_write( DDR_REG_BASE +0x50340*4 +0x02000000,0xb080); +reg_write( DDR_REG_BASE +0x50341*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x50342*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x50343*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50344*4 +0x02000000,0x7154); +reg_write( DDR_REG_BASE +0x50345*4 +0x02000000,0x2104); +reg_write( DDR_REG_BASE +0x50346*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x50347*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50348*4 +0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x50349*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x5034a*4 +0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x5034b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5034c*4 +0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x5034d*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x5034e*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x5034f*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50350*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50351*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x50352*4 +0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x50353*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x50354*4 +0x02000000,0x20cf); +reg_write( DDR_REG_BASE +0x50355*4 +0x02000000,0x1a1); +reg_write( DDR_REG_BASE +0x50356*4 +0x02000000,0x264c); +reg_write( DDR_REG_BASE +0x50357*4 +0x02000000,0xb180); +reg_write( DDR_REG_BASE +0x50358*4 +0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x50359*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x5035a*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5035b*4 +0x02000000,0xb8c3); +reg_write( DDR_REG_BASE +0x5035c*4 +0x02000000,0x7f05); +reg_write( DDR_REG_BASE +0x5035d*4 +0x02000000,0x78ef); +reg_write( DDR_REG_BASE +0x5035e*4 +0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x5035f*4 +0x02000000,0x2354); +reg_write( DDR_REG_BASE +0x50360*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x50361*4 +0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x50362*4 +0x02000000,0xb080); +reg_write( DDR_REG_BASE +0x50363*4 +0x02000000,0x2355); +reg_write( DDR_REG_BASE +0x50364*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x50365*4 +0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x50366*4 +0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x50367*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x50368*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x50369*4 +0x02000000,0x2355); +reg_write( DDR_REG_BASE +0x5036a*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x5036b*4 +0x02000000,0x7b05); +reg_write( DDR_REG_BASE +0x5036c*4 +0x02000000,0xb320); +reg_write( DDR_REG_BASE +0x5036d*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x5036e*4 +0x02000000,0x2740); +reg_write( DDR_REG_BASE +0x5036f*4 +0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x50370*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x50371*4 +0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x50372*4 +0x02000000,0xf405); +reg_write( DDR_REG_BASE +0x50373*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50374*4 +0x02000000,0x7042); +reg_write( DDR_REG_BASE +0x50375*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50376*4 +0x02000000,0x4ba); +reg_write( DDR_REG_BASE +0x50377*4 +0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x50378*4 +0x02000000,0xc0a6); +reg_write( DDR_REG_BASE +0x50379*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x5037a*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x5037b*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5037c*4 +0x02000000,0x738d); +reg_write( DDR_REG_BASE +0x5037d*4 +0x02000000,0xdf10); +reg_write( DDR_REG_BASE +0x5037e*4 +0x02000000,0xf19e); +reg_write( DDR_REG_BASE +0x5037f*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x50380*4 +0x02000000,0xf19b); +reg_write( DDR_REG_BASE +0x50381*4 +0x02000000,0x718d); +reg_write( DDR_REG_BASE +0x50382*4 +0x02000000,0xf199); +reg_write( DDR_REG_BASE +0x50383*4 +0x02000000,0xdc20); +reg_write( DDR_REG_BASE +0x50384*4 +0x02000000,0xf197); +reg_write( DDR_REG_BASE +0x50385*4 +0x02000000,0x758d); +reg_write( DDR_REG_BASE +0x50386*4 +0x02000000,0xf195); +reg_write( DDR_REG_BASE +0x50387*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50388*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x50389*4 +0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x5038a*4 +0x02000000,0xc408); +reg_write( DDR_REG_BASE +0x5038b*4 +0x02000000,0xc443); +reg_write( DDR_REG_BASE +0x5038c*4 +0x02000000,0xc407); +reg_write( DDR_REG_BASE +0x5038d*4 +0x02000000,0xc442); +reg_write( DDR_REG_BASE +0x5038e*4 +0x02000000,0xc406); +reg_write( DDR_REG_BASE +0x5038f*4 +0x02000000,0xc441); +reg_write( DDR_REG_BASE +0x50390*4 +0x02000000,0xc405); +reg_write( DDR_REG_BASE +0x50391*4 +0x02000000,0xde2); +reg_write( DDR_REG_BASE +0x50392*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50393*4 +0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x50394*4 +0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x50395*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x50396*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50397*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50398*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50399*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5039a*4 +0x02000000,0x4ba); +reg_write( DDR_REG_BASE +0x5039b*4 +0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x5039c*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x5039d*4 +0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x5039e*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x5039f*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x503a0*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x503a1*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x503a2*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x503a3*4 +0x02000000,0x1e8); +reg_write( DDR_REG_BASE +0x503a4*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x503a5*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x503a6*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x503a7*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x503a8*4 +0x02000000,0x4ba); +reg_write( DDR_REG_BASE +0x503a9*4 +0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x503aa*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x503ab*4 +0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x503ac*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x503ad*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x503ae*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x503af*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x503b0*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x503b1*4 +0x02000000,0x1e6); +reg_write( DDR_REG_BASE +0x503b2*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x503b3*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x503b4*4 +0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x503b5*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x503b6*4 +0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x503b7*4 +0x02000000,0x265a); +reg_write( DDR_REG_BASE +0x503b8*4 +0x02000000,0x3c83); +reg_write( DDR_REG_BASE +0x503b9*4 +0x02000000,0x607c); +reg_write( DDR_REG_BASE +0x503ba*4 +0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x503bb*4 +0x02000000,0x1643); +reg_write( DDR_REG_BASE +0x503bc*4 +0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x503bd*4 +0x02000000,0x639b); +reg_write( DDR_REG_BASE +0x503be*4 +0x02000000,0x633b); +reg_write( DDR_REG_BASE +0x503bf*4 +0x02000000,0x8b80); +reg_write( DDR_REG_BASE +0x503c0*4 +0x02000000,0x7c44); +reg_write( DDR_REG_BASE +0x503c1*4 +0x02000000,0xab80); +reg_write( DDR_REG_BASE +0x503c2*4 +0x02000000,0xbeb); +reg_write( DDR_REG_BASE +0x503c3*4 +0x02000000,0x9094); +reg_write( DDR_REG_BASE +0x503c4*4 +0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x503c5*4 +0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x503c6*4 +0x02000000,0xef9); +reg_write( DDR_REG_BASE +0x503c7*4 +0x02000000,0xb0b4); +reg_write( DDR_REG_BASE +0x503c8*4 +0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x503c9*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x503ca*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x503cb*4 +0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x503cc*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x503cd*4 +0x02000000,0xc76); +reg_write( DDR_REG_BASE +0x503ce*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x503cf*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x503d0*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x503d1*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x503d2*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x503d3*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x503d4*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x503d5*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x503d6*4 +0x02000000,0xd988); +reg_write( DDR_REG_BASE +0x503d7*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x503d8*4 +0x02000000,0xd52); +reg_write( DDR_REG_BASE +0x503d9*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x503da*4 +0x02000000,0xdb40); +reg_write( DDR_REG_BASE +0x503db*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x503dc*4 +0x02000000,0xcee); +reg_write( DDR_REG_BASE +0x503dd*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x503de*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x503df*4 +0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x503e0*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x503e1*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x503e2*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x503e3*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x503e4*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x503e5*4 +0x02000000,0xc1a2); +reg_write( DDR_REG_BASE +0x503e6*4 +0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x503e7*4 +0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x503e8*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x503e9*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x503ea*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x503eb*4 +0x02000000,0x8820); +reg_write( DDR_REG_BASE +0x503ec*4 +0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x503ed*4 +0x02000000,0x915); +reg_write( DDR_REG_BASE +0x503ee*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x503ef*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x503f0*4 +0x02000000,0x784f); +reg_write( DDR_REG_BASE +0x503f1*4 +0x02000000,0x8f7); +reg_write( DDR_REG_BASE +0x503f2*4 +0x02000000,0x87f4); +reg_write( DDR_REG_BASE +0x503f3*4 +0x02000000,0x2314); +reg_write( DDR_REG_BASE +0x503f4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x503f5*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x503f6*4 +0x02000000,0xd91e); +reg_write( DDR_REG_BASE +0x503f7*4 +0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x503f8*4 +0x02000000,0x2314); +reg_write( DDR_REG_BASE +0x503f9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x503fa*4 +0x02000000,0x8880); +reg_write( DDR_REG_BASE +0x503fb*4 +0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x503fc*4 +0x02000000,0xc0f); +reg_write( DDR_REG_BASE +0x503fd*4 +0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x503fe*4 +0x02000000,0x7724); +reg_write( DDR_REG_BASE +0x503ff*4 +0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x50400*4 +0x02000000,0x8047); +reg_write( DDR_REG_BASE +0x50401*4 +0x02000000,0xf5f8); +reg_write( DDR_REG_BASE +0x50402*4 +0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x50403*4 +0x02000000,0x4728); +reg_write( DDR_REG_BASE +0x50404*4 +0x02000000,0x78ef); +reg_write( DDR_REG_BASE +0x50405*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50406*4 +0x02000000,0x784f); +reg_write( DDR_REG_BASE +0x50407*4 +0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x50408*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x50409*4 +0x02000000,0xdeff); +reg_write( DDR_REG_BASE +0x5040a*4 +0x02000000,0x4718); +reg_write( DDR_REG_BASE +0x5040b*4 +0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x5040c*4 +0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x5040d*4 +0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x5040e*4 +0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x5040f*4 +0x02000000,0x8880); +reg_write( DDR_REG_BASE +0x50410*4 +0x02000000,0xca14); +reg_write( DDR_REG_BASE +0x50411*4 +0x02000000,0xe80a); +reg_write( DDR_REG_BASE +0x50412*4 +0x02000000,0xca66); +reg_write( DDR_REG_BASE +0x50413*4 +0x02000000,0x7410); +reg_write( DDR_REG_BASE +0x50414*4 +0x02000000,0xca67); +reg_write( DDR_REG_BASE +0x50415*4 +0x02000000,0x90d); +reg_write( DDR_REG_BASE +0x50416*4 +0x02000000,0x21); +reg_write( DDR_REG_BASE +0x50417*4 +0x02000000,0x23c0); +reg_write( DDR_REG_BASE +0x50418*4 +0x02000000,0x1061); +reg_write( DDR_REG_BASE +0x50419*4 +0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x5041a*4 +0x02000000,0x2108); +reg_write( DDR_REG_BASE +0x5041b*4 +0x02000000,0x79e); +reg_write( DDR_REG_BASE +0x5041c*4 +0x02000000,0x2409); +reg_write( DDR_REG_BASE +0x5041d*4 +0x02000000,0x138e); +reg_write( DDR_REG_BASE +0x5041e*4 +0x02000000,0x71e7); +reg_write( DDR_REG_BASE +0x5041f*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50420*4 +0x02000000,0x8dd); +reg_write( DDR_REG_BASE +0x50421*4 +0x02000000,0x87e5); +reg_write( DDR_REG_BASE +0x50422*4 +0x02000000,0x2314); +reg_write( DDR_REG_BASE +0x50423*4 +0x02000000,0x7c0); +reg_write( DDR_REG_BASE +0x50424*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50425*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50426*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50427*4 +0x02000000,0xe); +reg_write( DDR_REG_BASE +0x50428*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x50429*4 +0x02000000,0x133f); +reg_write( DDR_REG_BASE +0x5042a*4 +0x02000000,0x80); +reg_write( DDR_REG_BASE +0x5042b*4 +0x02000000,0xe00f); +reg_write( DDR_REG_BASE +0x5042c*4 +0x02000000,0xad00); +reg_write( DDR_REG_BASE +0x5042d*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x5042e*4 +0x02000000,0x8c6); +reg_write( DDR_REG_BASE +0x5042f*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50430*4 +0x02000000,0x2314); +reg_write( DDR_REG_BASE +0x50431*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50432*4 +0x02000000,0x2340); +reg_write( DDR_REG_BASE +0x50433*4 +0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x50434*4 +0x02000000,0xad22); +reg_write( DDR_REG_BASE +0x50435*4 +0x02000000,0xad01); +reg_write( DDR_REG_BASE +0x50436*4 +0x02000000,0x6a03); +reg_write( DDR_REG_BASE +0x50437*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x50438*4 +0x02000000,0x8b2); +reg_write( DDR_REG_BASE +0x50439*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5043a*4 +0x02000000,0x2314); +reg_write( DDR_REG_BASE +0x5043b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5043c*4 +0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x5043d*4 +0x02000000,0xb963); +reg_write( DDR_REG_BASE +0x5043e*4 +0x02000000,0xad24); +reg_write( DDR_REG_BASE +0x5043f*4 +0x02000000,0xad03); +reg_write( DDR_REG_BASE +0x50440*4 +0x02000000,0x6f0b); +reg_write( DDR_REG_BASE +0x50441*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x50442*4 +0x02000000,0x89e); +reg_write( DDR_REG_BASE +0x50443*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50444*4 +0x02000000,0x2314); +reg_write( DDR_REG_BASE +0x50445*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50446*4 +0x02000000,0xad05); +reg_write( DDR_REG_BASE +0x50447*4 +0x02000000,0x1215); +reg_write( DDR_REG_BASE +0x50448*4 +0x02000000,0x3603); +reg_write( DDR_REG_BASE +0x50449*4 +0x02000000,0xc816); +reg_write( DDR_REG_BASE +0x5044a*4 +0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x5044b*4 +0x02000000,0xf2c7); +reg_write( DDR_REG_BASE +0x5044c*4 +0x02000000,0x1a14); +reg_write( DDR_REG_BASE +0x5044d*4 +0x02000000,0x30d8); +reg_write( DDR_REG_BASE +0x5044e*4 +0x02000000,0x5070); +reg_write( DDR_REG_BASE +0x5044f*4 +0x02000000,0xf20b); +reg_write( DDR_REG_BASE +0x50450*4 +0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x50451*4 +0x02000000,0x913); +reg_write( DDR_REG_BASE +0x50452*4 +0x02000000,0x15e); +reg_write( DDR_REG_BASE +0x50453*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50454*4 +0x02000000,0xdb0f); +reg_write( DDR_REG_BASE +0x50455*4 +0x02000000,0x1a18); +reg_write( DDR_REG_BASE +0x50456*4 +0x02000000,0x3019); +reg_write( DDR_REG_BASE +0x50457*4 +0x02000000,0x1a14); +reg_write( DDR_REG_BASE +0x50458*4 +0x02000000,0x33d9); +reg_write( DDR_REG_BASE +0x50459*4 +0x02000000,0x1214); +reg_write( DDR_REG_BASE +0x5045a*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x5045b*4 +0x02000000,0xe92c); +reg_write( DDR_REG_BASE +0x5045c*4 +0x02000000,0x1215); +reg_write( DDR_REG_BASE +0x5045d*4 +0x02000000,0x3082); +reg_write( DDR_REG_BASE +0x5045e*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5045f*4 +0x02000000,0xdd64); +reg_write( DDR_REG_BASE +0x50460*4 +0x02000000,0x2244); +reg_write( DDR_REG_BASE +0x50461*4 +0x02000000,0x7cc); +reg_write( DDR_REG_BASE +0x50462*4 +0x02000000,0x4220); +reg_write( DDR_REG_BASE +0x50463*4 +0x02000000,0x2602); +reg_write( DDR_REG_BASE +0x50464*4 +0x02000000,0x3381); +reg_write( DDR_REG_BASE +0x50465*4 +0x02000000,0xec06); +reg_write( DDR_REG_BASE +0x50466*4 +0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x50467*4 +0x02000000,0xc01); +reg_write( DDR_REG_BASE +0x50468*4 +0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x50469*4 +0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x5046a*4 +0x02000000,0x2904); +reg_write( DDR_REG_BASE +0x5046b*4 +0x02000000,0x81); +reg_write( DDR_REG_BASE +0x5046c*4 +0x02000000,0x234e); +reg_write( DDR_REG_BASE +0x5046d*4 +0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x5046e*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x5046f*4 +0x02000000,0x7c2f); +reg_write( DDR_REG_BASE +0x50470*4 +0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x50471*4 +0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x50472*4 +0x02000000,0x7a2f); +reg_write( DDR_REG_BASE +0x50473*4 +0x02000000,0xa13); +reg_write( DDR_REG_BASE +0x50474*4 +0x02000000,0x325); +reg_write( DDR_REG_BASE +0x50475*4 +0x02000000,0xd964); +reg_write( DDR_REG_BASE +0x50476*4 +0x02000000,0x4181); +reg_write( DDR_REG_BASE +0x50477*4 +0x02000000,0x219f); +reg_write( DDR_REG_BASE +0x50478*4 +0x02000000,0x901); +reg_write( DDR_REG_BASE +0x50479*4 +0x02000000,0x2905); +reg_write( DDR_REG_BASE +0x5047a*4 +0x02000000,0x81); +reg_write( DDR_REG_BASE +0x5047b*4 +0x02000000,0x7b2c); +reg_write( DDR_REG_BASE +0x5047c*4 +0x02000000,0xc11); +reg_write( DDR_REG_BASE +0x5047d*4 +0x02000000,0x10a5); +reg_write( DDR_REG_BASE +0x5047e*4 +0x02000000,0x1a14); +reg_write( DDR_REG_BASE +0x5047f*4 +0x02000000,0x30d8); +reg_write( DDR_REG_BASE +0x50480*4 +0x02000000,0x229f); +reg_write( DDR_REG_BASE +0x50481*4 +0x02000000,0x901); +reg_write( DDR_REG_BASE +0x50482*4 +0x02000000,0x2a05); +reg_write( DDR_REG_BASE +0x50483*4 +0x02000000,0x30d); +reg_write( DDR_REG_BASE +0x50484*4 +0x02000000,0x78ac); +reg_write( DDR_REG_BASE +0x50485*4 +0x02000000,0x5070); +reg_write( DDR_REG_BASE +0x50486*4 +0x02000000,0xc0a2); +reg_write( DDR_REG_BASE +0x50487*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50488*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50489*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5048a*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5048b*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5048c*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5048d*4 +0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x5048e*4 +0x02000000,0xb140); +reg_write( DDR_REG_BASE +0x5048f*4 +0x02000000,0xb15d); +reg_write( DDR_REG_BASE +0x50490*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50491*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x50492*4 +0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x50493*4 +0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x50494*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50495*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x50496*4 +0x02000000,0xff64); +reg_write( DDR_REG_BASE +0x50497*4 +0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x50498*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50499*4 +0x02000000,0x1804); +reg_write( DDR_REG_BASE +0x5049a*4 +0x02000000,0x45); +reg_write( DDR_REG_BASE +0x5049b*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5049c*4 +0x02000000,0x917); +reg_write( DDR_REG_BASE +0x5049d*4 +0x02000000,0x3f0); +reg_write( DDR_REG_BASE +0x5049e*4 +0x02000000,0x228a); +reg_write( DDR_REG_BASE +0x5049f*4 +0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x504a0*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x504a1*4 +0x02000000,0xb9c4); +reg_write( DDR_REG_BASE +0x504a2*4 +0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x504a3*4 +0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x504a4*4 +0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x504a5*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x504a6*4 +0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x504a7*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x504a8*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x504a9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x504aa*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x504ab*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x504ac*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x504ad*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x504ae*4 +0x02000000,0x16a); +reg_write( DDR_REG_BASE +0x504af*4 +0x02000000,0x224f); +reg_write( DDR_REG_BASE +0x504b0*4 +0x02000000,0x240); +reg_write( DDR_REG_BASE +0x504b1*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x504b2*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x504b3*4 +0x02000000,0xb140); +reg_write( DDR_REG_BASE +0x504b4*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x504b5*4 +0x02000000,0xb140); +reg_write( DDR_REG_BASE +0x504b6*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x504b7*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x504b8*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x504b9*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x504ba*4 +0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x504bb*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x504bc*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x504bd*4 +0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x504be*4 +0x02000000,0x230a); +reg_write( DDR_REG_BASE +0x504bf*4 +0x02000000,0x780); +reg_write( DDR_REG_BASE +0x504c0*4 +0x02000000,0xbcc4); +reg_write( DDR_REG_BASE +0x504c1*4 +0x02000000,0xec06); +reg_write( DDR_REG_BASE +0x504c2*4 +0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x504c3*4 +0x02000000,0xc01); +reg_write( DDR_REG_BASE +0x504c4*4 +0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x504c5*4 +0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x504c6*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x504c7*4 +0x02000000,0xbbc0); +reg_write( DDR_REG_BASE +0x504c8*4 +0x02000000,0x631b); +reg_write( DDR_REG_BASE +0x504c9*4 +0x02000000,0x7c2f); +reg_write( DDR_REG_BASE +0x504ca*4 +0x02000000,0xae9); +reg_write( DDR_REG_BASE +0x504cb*4 +0x02000000,0x8325); +reg_write( DDR_REG_BASE +0x504cc*4 +0x02000000,0x786f); +reg_write( DDR_REG_BASE +0x504cd*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x504ce*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x504cf*4 +0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x504d0*4 +0x02000000,0xbf6); +reg_write( DDR_REG_BASE +0x504d1*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x504d2*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x504d3*4 +0x02000000,0x795b); +reg_write( DDR_REG_BASE +0x504d4*4 +0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x504d5*4 +0x02000000,0x181); +reg_write( DDR_REG_BASE +0x504d6*4 +0x02000000,0xb9c4); +reg_write( DDR_REG_BASE +0x504d7*4 +0x02000000,0xe906); +reg_write( DDR_REG_BASE +0x504d8*4 +0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x504d9*4 +0x02000000,0x901); +reg_write( DDR_REG_BASE +0x504da*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x504db*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x504dc*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x504dd*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x504de*4 +0x02000000,0xb8c1); +reg_write( DDR_REG_BASE +0x504df*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x504e0*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x504e1*4 +0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x504e2*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x504e3*4 +0x02000000,0xa4a); +reg_write( DDR_REG_BASE +0x504e4*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x504e5*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x504e6*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x504e7*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x504e8*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x504e9*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x504ea*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x504eb*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x504ec*4 +0x02000000,0xd990); +reg_write( DDR_REG_BASE +0x504ed*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x504ee*4 +0x02000000,0xb26); +reg_write( DDR_REG_BASE +0x504ef*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x504f0*4 +0x02000000,0xdb40); +reg_write( DDR_REG_BASE +0x504f1*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x504f2*4 +0x02000000,0xac2); +reg_write( DDR_REG_BASE +0x504f3*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x504f4*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x504f5*4 +0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x504f6*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x504f7*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x504f8*4 +0x02000000,0xc3e1); +reg_write( DDR_REG_BASE +0x504f9*4 +0x02000000,0xc2e1); +reg_write( DDR_REG_BASE +0x504fa*4 +0x02000000,0xc1e1); +reg_write( DDR_REG_BASE +0x504fb*4 +0x02000000,0xc0e1); +reg_write( DDR_REG_BASE +0x504fc*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x504fd*4 +0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x504fe*4 +0x02000000,0x4220); +reg_write( DDR_REG_BASE +0x504ff*4 +0x02000000,0xc184); +reg_write( DDR_REG_BASE +0x50500*4 +0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x50501*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50502*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x50503*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50504*4 +0x02000000,0x12); +reg_write( DDR_REG_BASE +0x50505*4 +0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x50506*4 +0x02000000,0x64); +reg_write( DDR_REG_BASE +0x50507*4 +0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x50508*4 +0x02000000,0xc02); +reg_write( DDR_REG_BASE +0x50509*4 +0x02000000,0x220); +reg_write( DDR_REG_BASE +0x5050a*4 +0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x5050b*4 +0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x5050c*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x5050d*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x5050e*4 +0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x5050f*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50510*4 +0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x50511*4 +0x02000000,0x216c); +reg_write( DDR_REG_BASE +0x50512*4 +0x02000000,0x102); +reg_write( DDR_REG_BASE +0x50513*4 +0x02000000,0x206c); +reg_write( DDR_REG_BASE +0x50514*4 +0x02000000,0x141); +reg_write( DDR_REG_BASE +0x50515*4 +0x02000000,0x7822); +reg_write( DDR_REG_BASE +0x50516*4 +0x02000000,0x621a); +reg_write( DDR_REG_BASE +0x50517*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50518*4 +0x02000000,0x784e); +reg_write( DDR_REG_BASE +0x50519*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5051a*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5051b*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5051c*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5051d*4 +0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x5051e*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x5051f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50520*4 +0x02000000,0x674); +reg_write( DDR_REG_BASE +0x50521*4 +0x02000000,0x6de4); +reg_write( DDR_REG_BASE +0x50522*4 +0x02000000,0x83e); +reg_write( DDR_REG_BASE +0x50523*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50524*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x50525*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x50526*4 +0x02000000,0x43c9); +reg_write( DDR_REG_BASE +0x50527*4 +0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x50528*4 +0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x50529*4 +0x02000000,0x641); +reg_write( DDR_REG_BASE +0x5052a*4 +0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x5052b*4 +0x02000000,0x1c80); +reg_write( DDR_REG_BASE +0x5052c*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x5052d*4 +0x02000000,0xab2); +reg_write( DDR_REG_BASE +0x5052e*4 +0x02000000,0x1a0); +reg_write( DDR_REG_BASE +0x5052f*4 +0x02000000,0x60f8); +reg_write( DDR_REG_BASE +0x50530*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x50531*4 +0x02000000,0xbf1); +reg_write( DDR_REG_BASE +0x50532*4 +0x02000000,0x8094); +reg_write( DDR_REG_BASE +0x50533*4 +0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x50534*4 +0x02000000,0xbfb); +reg_write( DDR_REG_BASE +0x50535*4 +0x02000000,0x90b4); +reg_write( DDR_REG_BASE +0x50536*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50537*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50538*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50539*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x5053a*4 +0x02000000,0xa8ce); +reg_write( DDR_REG_BASE +0x5053b*4 +0x02000000,0xa8c1); +reg_write( DDR_REG_BASE +0x5053c*4 +0x02000000,0xa8c0); +reg_write( DDR_REG_BASE +0x5053d*4 +0x02000000,0xbe2); +reg_write( DDR_REG_BASE +0x5053e*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5053f*4 +0x02000000,0xa5e0); +reg_write( DDR_REG_BASE +0x50540*4 +0x02000000,0xbe6); +reg_write( DDR_REG_BASE +0x50541*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50542*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x50543*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x50544*4 +0x02000000,0xa72); +reg_write( DDR_REG_BASE +0x50545*4 +0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x50546*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50547*4 +0x02000000,0x236f); +reg_write( DDR_REG_BASE +0x50548*4 +0x02000000,0x30c3); +reg_write( DDR_REG_BASE +0x50549*4 +0x02000000,0x1318); +reg_write( DDR_REG_BASE +0x5054a*4 +0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x5054b*4 +0x02000000,0xe809); +reg_write( DDR_REG_BASE +0x5054c*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5054d*4 +0x02000000,0x145); +reg_write( DDR_REG_BASE +0x5054e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5054f*4 +0x02000000,0xf56); +reg_write( DDR_REG_BASE +0x50550*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50551*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x50552*4 +0x02000000,0xf01f); +reg_write( DDR_REG_BASE +0x50553*4 +0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x50554*4 +0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x50555*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50556*4 +0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x50557*4 +0x02000000,0x8480); +reg_write( DDR_REG_BASE +0x50558*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50559*4 +0x02000000,0x5f5); +reg_write( DDR_REG_BASE +0x5055a*4 +0x02000000,0xe100); +reg_write( DDR_REG_BASE +0x5055b*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x5055c*4 +0x02000000,0x808d); +reg_write( DDR_REG_BASE +0x5055d*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x5055e*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x5055f*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x50560*4 +0x02000000,0x992); +reg_write( DDR_REG_BASE +0x50561*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50562*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50563*4 +0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x50564*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50565*4 +0x02000000,0x3b9a); +reg_write( DDR_REG_BASE +0x50566*4 +0x02000000,0xca00); +reg_write( DDR_REG_BASE +0x50567*4 +0x02000000,0x26ca); +reg_write( DDR_REG_BASE +0x50568*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x50569*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x5056a*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5056b*4 +0x02000000,0x70c5); +reg_write( DDR_REG_BASE +0x5056c*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5056d*4 +0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x5056e*4 +0x02000000,0x976); +reg_write( DDR_REG_BASE +0x5056f*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50570*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50571*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50572*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50573*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50574*4 +0x02000000,0xd); +reg_write( DDR_REG_BASE +0x50575*4 +0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x50576*4 +0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x50577*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50578*4 +0x02000000,0x7045); +reg_write( DDR_REG_BASE +0x50579*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5057a*4 +0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x5057b*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x5057c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5057d*4 +0x02000000,0x57c); +reg_write( DDR_REG_BASE +0x5057e*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x5057f*4 +0x02000000,0x8b7); +reg_write( DDR_REG_BASE +0x50580*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x50581*4 +0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x50582*4 +0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x50583*4 +0x02000000,0x8af); +reg_write( DDR_REG_BASE +0x50584*4 +0x02000000,0xdf); +reg_write( DDR_REG_BASE +0x50585*4 +0x02000000,0xc82); +reg_write( DDR_REG_BASE +0x50586*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50587*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50588*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50589*4 +0x02000000,0xa00); +reg_write( DDR_REG_BASE +0x5058a*4 +0x02000000,0x8fa); +reg_write( DDR_REG_BASE +0x5058b*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5058c*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x5058d*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x5058e*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5058f*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50590*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x50591*4 +0x02000000,0x736c); +reg_write( DDR_REG_BASE +0x50592*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x50593*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50594*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x50595*4 +0x02000000,0x9da); +reg_write( DDR_REG_BASE +0x50596*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50597*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x50598*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x50599*4 +0x02000000,0x825); +reg_write( DDR_REG_BASE +0x5059a*4 +0x02000000,0xb4); +reg_write( DDR_REG_BASE +0x5059b*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5059c*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5059d*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5059e*4 +0x02000000,0xb862); +reg_write( DDR_REG_BASE +0x5059f*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x505a0*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x505a1*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x505a2*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x505a3*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x505a4*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x505a5*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x505a6*4 +0x02000000,0x9b6); +reg_write( DDR_REG_BASE +0x505a7*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x505a8*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x505a9*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x505aa*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x505ab*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x505ac*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x505ad*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x505ae*4 +0x02000000,0xdb0c); +reg_write( DDR_REG_BASE +0x505af*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x505b0*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x505b1*4 +0x02000000,0x9a2); +reg_write( DDR_REG_BASE +0x505b2*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x505b3*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x505b4*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x505b5*4 +0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x505b6*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x505b7*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x505b8*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x505b9*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x505ba*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x505bb*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x505bc*4 +0x02000000,0x98a); +reg_write( DDR_REG_BASE +0x505bd*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x505be*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x505bf*4 +0x02000000,0xbd2); +reg_write( DDR_REG_BASE +0x505c0*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x505c1*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x505c2*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x505c3*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x505c4*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x505c5*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x505c6*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x505c7*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x505c8*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x505c9*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x505ca*4 +0x02000000,0x96e); +reg_write( DDR_REG_BASE +0x505cb*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x505cc*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x505cd*4 +0x02000000,0xb9a); +reg_write( DDR_REG_BASE +0x505ce*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x505cf*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x505d0*4 +0x02000000,0xbde); +reg_write( DDR_REG_BASE +0x505d1*4 +0x02000000,0x1c0); +reg_write( DDR_REG_BASE +0x505d2*4 +0x02000000,0xd896); +reg_write( DDR_REG_BASE +0x505d3*4 +0x02000000,0x902); +reg_write( DDR_REG_BASE +0x505d4*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x505d5*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x505d6*4 +0x02000000,0xd1a); +reg_write( DDR_REG_BASE +0x505d7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x505d8*4 +0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x505d9*4 +0x02000000,0xbe6); +reg_write( DDR_REG_BASE +0x505da*4 +0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x505db*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x505dc*4 +0x02000000,0xf); +reg_write( DDR_REG_BASE +0x505dd*4 +0x02000000,0x4240); +reg_write( DDR_REG_BASE +0x505de*4 +0x02000000,0x896); +reg_write( DDR_REG_BASE +0x505df*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x505e0*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x505e1*4 +0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x505e2*4 +0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x505e3*4 +0x02000000,0x83f); +reg_write( DDR_REG_BASE +0x505e4*4 +0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x505e5*4 +0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x505e6*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x505e7*4 +0x02000000,0x14); +reg_write( DDR_REG_BASE +0x505e8*4 +0x02000000,0x9320); +reg_write( DDR_REG_BASE +0x505e9*4 +0x02000000,0xca01); +reg_write( DDR_REG_BASE +0x505ea*4 +0x02000000,0x80d); +reg_write( DDR_REG_BASE +0x505eb*4 +0x02000000,0x1b0); +reg_write( DDR_REG_BASE +0x505ec*4 +0x02000000,0x214f); +reg_write( DDR_REG_BASE +0x505ed*4 +0x02000000,0x82); +reg_write( DDR_REG_BASE +0x505ee*4 +0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x505ef*4 +0x02000000,0xd1); +reg_write( DDR_REG_BASE +0x505f0*4 +0x02000000,0x2185); +reg_write( DDR_REG_BASE +0x505f1*4 +0x02000000,0x108); +reg_write( DDR_REG_BASE +0x505f2*4 +0x02000000,0x4220); +reg_write( DDR_REG_BASE +0x505f3*4 +0x02000000,0xb340); +reg_write( DDR_REG_BASE +0x505f4*4 +0x02000000,0xd823); +reg_write( DDR_REG_BASE +0x505f5*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x505f6*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x505f7*4 +0x02000000,0xe034); +reg_write( DDR_REG_BASE +0x505f8*4 +0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x505f9*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x505fa*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x505fb*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x505fc*4 +0x02000000,0xe034); +reg_write( DDR_REG_BASE +0x505fd*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x505fe*4 +0x02000000,0xb8b1); +reg_write( DDR_REG_BASE +0x505ff*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x50600*4 +0x02000000,0xb221); +reg_write( DDR_REG_BASE +0x50601*4 +0x02000000,0xddff); +reg_write( DDR_REG_BASE +0x50602*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x50603*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50604*4 +0x02000000,0x228a); +reg_write( DDR_REG_BASE +0x50605*4 +0x02000000,0xdff); +reg_write( DDR_REG_BASE +0x50606*4 +0x02000000,0x776c); +reg_write( DDR_REG_BASE +0x50607*4 +0x02000000,0x8c6); +reg_write( DDR_REG_BASE +0x50608*4 +0x02000000,0x2a0); +reg_write( DDR_REG_BASE +0x50609*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5060a*4 +0x02000000,0x774c); +reg_write( DDR_REG_BASE +0x5060b*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x5060c*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5060d*4 +0x02000000,0x4340); +reg_write( DDR_REG_BASE +0x5060e*4 +0x02000000,0x8b6); +reg_write( DDR_REG_BASE +0x5060f*4 +0x02000000,0x2a0); +reg_write( DDR_REG_BASE +0x50610*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x50611*4 +0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x50612*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50613*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50614*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50615*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50616*4 +0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x50617*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50618*4 +0x02000000,0xbd9a); +reg_write( DDR_REG_BASE +0x50619*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5061a*4 +0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x5061b*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x5061c*4 +0x02000000,0xdba); +reg_write( DDR_REG_BASE +0x5061d*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5061e*4 +0x02000000,0x1a10); +reg_write( DDR_REG_BASE +0x5061f*4 +0x02000000,0x3003); +reg_write( DDR_REG_BASE +0x50620*4 +0x02000000,0x88a); +reg_write( DDR_REG_BASE +0x50621*4 +0x02000000,0x1c0); +reg_write( DDR_REG_BASE +0x50622*4 +0x02000000,0x254f); +reg_write( DDR_REG_BASE +0x50623*4 +0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x50624*4 +0x02000000,0xdaa); +reg_write( DDR_REG_BASE +0x50625*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50626*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50627*4 +0x02000000,0x926); +reg_write( DDR_REG_BASE +0x50628*4 +0x02000000,0x220); +reg_write( DDR_REG_BASE +0x50629*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5062a*4 +0x02000000,0x26ab); +reg_write( DDR_REG_BASE +0x5062b*4 +0x02000000,0x10c4); +reg_write( DDR_REG_BASE +0x5062c*4 +0x02000000,0x7fff); +reg_write( DDR_REG_BASE +0x5062d*4 +0x02000000,0xf000); +reg_write( DDR_REG_BASE +0x5062e*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5062f*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50630*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50631*4 +0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x50632*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x50633*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50634*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50635*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50636*4 +0x02000000,0x12); +reg_write( DDR_REG_BASE +0x50637*4 +0x02000000,0x86b); +reg_write( DDR_REG_BASE +0x50638*4 +0x02000000,0x175); +reg_write( DDR_REG_BASE +0x50639*4 +0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x5063a*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5063b*4 +0x02000000,0x708f); +reg_write( DDR_REG_BASE +0x5063c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5063d*4 +0x02000000,0x669); +reg_write( DDR_REG_BASE +0x5063e*4 +0x02000000,0xf023); +reg_write( DDR_REG_BASE +0x5063f*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x50640*4 +0x02000000,0x83b); +reg_write( DDR_REG_BASE +0x50641*4 +0x02000000,0x3ae); +reg_write( DDR_REG_BASE +0x50642*4 +0x02000000,0x252f); +reg_write( DDR_REG_BASE +0x50643*4 +0x02000000,0x16c7); +reg_write( DDR_REG_BASE +0x50644*4 +0x02000000,0x259f); +reg_write( DDR_REG_BASE +0x50645*4 +0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x50646*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50647*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50648*4 +0x02000000,0x71a); +reg_write( DDR_REG_BASE +0x50649*4 +0x02000000,0xc202); +reg_write( DDR_REG_BASE +0x5064a*4 +0x02000000,0x43c1); +reg_write( DDR_REG_BASE +0x5064b*4 +0x02000000,0x6509); +reg_write( DDR_REG_BASE +0x5064c*4 +0x02000000,0x60b8); +reg_write( DDR_REG_BASE +0x5064d*4 +0x02000000,0x8802); +reg_write( DDR_REG_BASE +0x5064e*4 +0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x5064f*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50650*4 +0x02000000,0x16); +reg_write( DDR_REG_BASE +0x50651*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50652*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x50653*4 +0x02000000,0xd4e); +reg_write( DDR_REG_BASE +0x50654*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50655*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x50656*4 +0x02000000,0x2500); +reg_write( DDR_REG_BASE +0x50657*4 +0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x50658*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50659*4 +0x02000000,0x6dc); +reg_write( DDR_REG_BASE +0x5065a*4 +0x02000000,0x82e); +reg_write( DDR_REG_BASE +0x5065b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5065c*4 +0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x5065d*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x5065e*4 +0x02000000,0xec3); +reg_write( DDR_REG_BASE +0x5065f*4 +0x02000000,0x9254); +reg_write( DDR_REG_BASE +0x50660*4 +0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x50661*4 +0x02000000,0x78ef); +reg_write( DDR_REG_BASE +0x50662*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x50663*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50664*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50665*4 +0x02000000,0x669); +reg_write( DDR_REG_BASE +0x50666*4 +0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x50667*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50668*4 +0x02000000,0x9ed); +reg_write( DDR_REG_BASE +0x50669*4 +0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x5066a*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x5066b*4 +0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x5066c*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x5066d*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x5066e*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5066f*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50670*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50671*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50672*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50673*4 +0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x50674*4 +0x02000000,0x3b04); +reg_write( DDR_REG_BASE +0x50675*4 +0x02000000,0x68a1); +reg_write( DDR_REG_BASE +0x50676*4 +0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x50677*4 +0x02000000,0xf0ac); +reg_write( DDR_REG_BASE +0x50678*4 +0x02000000,0x8d62); +reg_write( DDR_REG_BASE +0x50679*4 +0x02000000,0x15ff); +reg_write( DDR_REG_BASE +0x5067a*4 +0x02000000,0x9480); +reg_write( DDR_REG_BASE +0x5067b*4 +0x02000000,0x152d); +reg_write( DDR_REG_BASE +0x5067c*4 +0x02000000,0x109f); +reg_write( DDR_REG_BASE +0x5067d*4 +0x02000000,0x152f); +reg_write( DDR_REG_BASE +0x5067e*4 +0x02000000,0x109e); +reg_write( DDR_REG_BASE +0x5067f*4 +0x02000000,0x1cd8); +reg_write( DDR_REG_BASE +0x50680*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x50681*4 +0x02000000,0x8d05); +reg_write( DDR_REG_BASE +0x50682*4 +0x02000000,0x1531); +reg_write( DDR_REG_BASE +0x50683*4 +0x02000000,0x108b); +reg_write( DDR_REG_BASE +0x50684*4 +0x02000000,0x1533); +reg_write( DDR_REG_BASE +0x50685*4 +0x02000000,0x108f); +reg_write( DDR_REG_BASE +0x50686*4 +0x02000000,0x1cdc); +reg_write( DDR_REG_BASE +0x50687*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x50688*4 +0x02000000,0x8d07); +reg_write( DDR_REG_BASE +0x50689*4 +0x02000000,0x1535); +reg_write( DDR_REG_BASE +0x5068a*4 +0x02000000,0x108e); +reg_write( DDR_REG_BASE +0x5068b*4 +0x02000000,0x1537); +reg_write( DDR_REG_BASE +0x5068c*4 +0x02000000,0x108c); +reg_write( DDR_REG_BASE +0x5068d*4 +0x02000000,0x1ce0); +reg_write( DDR_REG_BASE +0x5068e*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x5068f*4 +0x02000000,0x8d09); +reg_write( DDR_REG_BASE +0x50690*4 +0x02000000,0x1539); +reg_write( DDR_REG_BASE +0x50691*4 +0x02000000,0x1082); +reg_write( DDR_REG_BASE +0x50692*4 +0x02000000,0x153b); +reg_write( DDR_REG_BASE +0x50693*4 +0x02000000,0x1081); +reg_write( DDR_REG_BASE +0x50694*4 +0x02000000,0x1ce4); +reg_write( DDR_REG_BASE +0x50695*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x50696*4 +0x02000000,0x8d0b); +reg_write( DDR_REG_BASE +0x50697*4 +0x02000000,0x1ce8); +reg_write( DDR_REG_BASE +0x50698*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x50699*4 +0x02000000,0x8d0d); +reg_write( DDR_REG_BASE +0x5069a*4 +0x02000000,0x1cec); +reg_write( DDR_REG_BASE +0x5069b*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x5069c*4 +0x02000000,0x8d0f); +reg_write( DDR_REG_BASE +0x5069d*4 +0x02000000,0x1cf0); +reg_write( DDR_REG_BASE +0x5069e*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x5069f*4 +0x02000000,0x8d11); +reg_write( DDR_REG_BASE +0x506a0*4 +0x02000000,0x1cf4); +reg_write( DDR_REG_BASE +0x506a1*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x506a2*4 +0x02000000,0x8d13); +reg_write( DDR_REG_BASE +0x506a3*4 +0x02000000,0x1cf8); +reg_write( DDR_REG_BASE +0x506a4*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x506a5*4 +0x02000000,0x8d15); +reg_write( DDR_REG_BASE +0x506a6*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x506a7*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x506a8*4 +0x02000000,0x8d17); +reg_write( DDR_REG_BASE +0x506a9*4 +0x02000000,0x1c40); +reg_write( DDR_REG_BASE +0x506aa*4 +0x02000000,0x3018); +reg_write( DDR_REG_BASE +0x506ab*4 +0x02000000,0x8d19); +reg_write( DDR_REG_BASE +0x506ac*4 +0x02000000,0x1c41); +reg_write( DDR_REG_BASE +0x506ad*4 +0x02000000,0x3018); +reg_write( DDR_REG_BASE +0x506ae*4 +0x02000000,0x8d1b); +reg_write( DDR_REG_BASE +0x506af*4 +0x02000000,0x1c42); +reg_write( DDR_REG_BASE +0x506b0*4 +0x02000000,0x3018); +reg_write( DDR_REG_BASE +0x506b1*4 +0x02000000,0x8d1d); +reg_write( DDR_REG_BASE +0x506b2*4 +0x02000000,0x1c43); +reg_write( DDR_REG_BASE +0x506b3*4 +0x02000000,0x3018); +reg_write( DDR_REG_BASE +0x506b4*4 +0x02000000,0x8d1f); +reg_write( DDR_REG_BASE +0x506b5*4 +0x02000000,0x1c44); +reg_write( DDR_REG_BASE +0x506b6*4 +0x02000000,0x3018); +reg_write( DDR_REG_BASE +0x506b7*4 +0x02000000,0x1521); +reg_write( DDR_REG_BASE +0x506b8*4 +0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x506b9*4 +0x02000000,0x1c45); +reg_write( DDR_REG_BASE +0x506ba*4 +0x02000000,0x3018); +reg_write( DDR_REG_BASE +0x506bb*4 +0x02000000,0x1523); +reg_write( DDR_REG_BASE +0x506bc*4 +0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x506bd*4 +0x02000000,0x1c46); +reg_write( DDR_REG_BASE +0x506be*4 +0x02000000,0x3018); +reg_write( DDR_REG_BASE +0x506bf*4 +0x02000000,0x1525); +reg_write( DDR_REG_BASE +0x506c0*4 +0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x506c1*4 +0x02000000,0x1c47); +reg_write( DDR_REG_BASE +0x506c2*4 +0x02000000,0x3018); +reg_write( DDR_REG_BASE +0x506c3*4 +0x02000000,0x1527); +reg_write( DDR_REG_BASE +0x506c4*4 +0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x506c5*4 +0x02000000,0x1c48); +reg_write( DDR_REG_BASE +0x506c6*4 +0x02000000,0x3018); +reg_write( DDR_REG_BASE +0x506c7*4 +0x02000000,0x1529); +reg_write( DDR_REG_BASE +0x506c8*4 +0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x506c9*4 +0x02000000,0x1c49); +reg_write( DDR_REG_BASE +0x506ca*4 +0x02000000,0x3018); +reg_write( DDR_REG_BASE +0x506cb*4 +0x02000000,0x152b); +reg_write( DDR_REG_BASE +0x506cc*4 +0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x506cd*4 +0x02000000,0x1c4a); +reg_write( DDR_REG_BASE +0x506ce*4 +0x02000000,0x3018); +reg_write( DDR_REG_BASE +0x506cf*4 +0x02000000,0x153d); +reg_write( DDR_REG_BASE +0x506d0*4 +0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x506d1*4 +0x02000000,0xc25a); +reg_write( DDR_REG_BASE +0x506d2*4 +0x02000000,0x14d8); +reg_write( DDR_REG_BASE +0x506d3*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x506d4*4 +0x02000000,0xc05c); +reg_write( DDR_REG_BASE +0x506d5*4 +0x02000000,0x144a); +reg_write( DDR_REG_BASE +0x506d6*4 +0x02000000,0x3600); +reg_write( DDR_REG_BASE +0x506d7*4 +0x02000000,0xc15b); +reg_write( DDR_REG_BASE +0x506d8*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x506d9*4 +0x02000000,0x14); +reg_write( DDR_REG_BASE +0x506da*4 +0x02000000,0x1f); +reg_write( DDR_REG_BASE +0x506db*4 +0x02000000,0xc053); +reg_write( DDR_REG_BASE +0x506dc*4 +0x02000000,0x1449); +reg_write( DDR_REG_BASE +0x506dd*4 +0x02000000,0x3600); +reg_write( DDR_REG_BASE +0x506de*4 +0x02000000,0xc459); +reg_write( DDR_REG_BASE +0x506df*4 +0x02000000,0xc658); +reg_write( DDR_REG_BASE +0x506e0*4 +0x02000000,0xc052); +reg_write( DDR_REG_BASE +0x506e1*4 +0x02000000,0x1448); +reg_write( DDR_REG_BASE +0x506e2*4 +0x02000000,0x3600); +reg_write( DDR_REG_BASE +0x506e3*4 +0x02000000,0xc757); +reg_write( DDR_REG_BASE +0x506e4*4 +0x02000000,0x1c58); +reg_write( DDR_REG_BASE +0x506e5*4 +0x02000000,0x32c0); +reg_write( DDR_REG_BASE +0x506e6*4 +0x02000000,0xc051); +reg_write( DDR_REG_BASE +0x506e7*4 +0x02000000,0x1447); +reg_write( DDR_REG_BASE +0x506e8*4 +0x02000000,0x3600); +reg_write( DDR_REG_BASE +0x506e9*4 +0x02000000,0x1c54); +reg_write( DDR_REG_BASE +0x506ea*4 +0x02000000,0x3780); +reg_write( DDR_REG_BASE +0x506eb*4 +0x02000000,0x1c50); +reg_write( DDR_REG_BASE +0x506ec*4 +0x02000000,0x37c0); +reg_write( DDR_REG_BASE +0x506ed*4 +0x02000000,0xc050); +reg_write( DDR_REG_BASE +0x506ee*4 +0x02000000,0x1446); +reg_write( DDR_REG_BASE +0x506ef*4 +0x02000000,0x3600); +reg_write( DDR_REG_BASE +0x506f0*4 +0x02000000,0xc04f); +reg_write( DDR_REG_BASE +0x506f1*4 +0x02000000,0x1445); +reg_write( DDR_REG_BASE +0x506f2*4 +0x02000000,0x3600); +reg_write( DDR_REG_BASE +0x506f3*4 +0x02000000,0xc04e); +reg_write( DDR_REG_BASE +0x506f4*4 +0x02000000,0x1444); +reg_write( DDR_REG_BASE +0x506f5*4 +0x02000000,0x3600); +reg_write( DDR_REG_BASE +0x506f6*4 +0x02000000,0xc04d); +reg_write( DDR_REG_BASE +0x506f7*4 +0x02000000,0x1443); +reg_write( DDR_REG_BASE +0x506f8*4 +0x02000000,0x3600); +reg_write( DDR_REG_BASE +0x506f9*4 +0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x506fa*4 +0x02000000,0x1442); +reg_write( DDR_REG_BASE +0x506fb*4 +0x02000000,0x3600); +reg_write( DDR_REG_BASE +0x506fc*4 +0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x506fd*4 +0x02000000,0x1441); +reg_write( DDR_REG_BASE +0x506fe*4 +0x02000000,0x3600); +reg_write( DDR_REG_BASE +0x506ff*4 +0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x50700*4 +0x02000000,0x1440); +reg_write( DDR_REG_BASE +0x50701*4 +0x02000000,0x3600); +reg_write( DDR_REG_BASE +0x50702*4 +0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x50703*4 +0x02000000,0x14fc); +reg_write( DDR_REG_BASE +0x50704*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x50705*4 +0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x50706*4 +0x02000000,0x14f8); +reg_write( DDR_REG_BASE +0x50707*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x50708*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x50709*4 +0x02000000,0x14f4); +reg_write( DDR_REG_BASE +0x5070a*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x5070b*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x5070c*4 +0x02000000,0x14f0); +reg_write( DDR_REG_BASE +0x5070d*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x5070e*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x5070f*4 +0x02000000,0x14ec); +reg_write( DDR_REG_BASE +0x50710*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x50711*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x50712*4 +0x02000000,0x14e8); +reg_write( DDR_REG_BASE +0x50713*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x50714*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x50715*4 +0x02000000,0x14e4); +reg_write( DDR_REG_BASE +0x50716*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x50717*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x50718*4 +0x02000000,0x14e0); +reg_write( DDR_REG_BASE +0x50719*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x5071a*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5071b*4 +0x02000000,0x14dc); +reg_write( DDR_REG_BASE +0x5071c*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x5071d*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5071e*4 +0x02000000,0xbb6); +reg_write( DDR_REG_BASE +0x5071f*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50720*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x50721*4 +0x02000000,0x7767); +reg_write( DDR_REG_BASE +0x50722*4 +0x02000000,0x7077); +reg_write( DDR_REG_BASE +0x50723*4 +0x02000000,0x6ac); +reg_write( DDR_REG_BASE +0x50724*4 +0x02000000,0xffca); +reg_write( DDR_REG_BASE +0x50725*4 +0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x50726*4 +0x02000000,0x3b04); +reg_write( DDR_REG_BASE +0x50727*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50728*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50729*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5072a*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x5072b*4 +0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x5072c*4 +0x02000000,0x3d02); +reg_write( DDR_REG_BASE +0x5072d*4 +0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x5072e*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5072f*4 +0x02000000,0x8f2); +reg_write( DDR_REG_BASE +0x50730*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50731*4 +0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x50732*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50733*4 +0x02000000,0x18f); +reg_write( DDR_REG_BASE +0x50734*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50735*4 +0x02000000,0xb8a); +reg_write( DDR_REG_BASE +0x50736*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50737*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x50738*4 +0x02000000,0xd840); +reg_write( DDR_REG_BASE +0x50739*4 +0x02000000,0xc180); +reg_write( DDR_REG_BASE +0x5073a*4 +0x02000000,0xc22); +reg_write( DDR_REG_BASE +0x5073b*4 +0x02000000,0x160); +reg_write( DDR_REG_BASE +0x5073c*4 +0x02000000,0xda09); +reg_write( DDR_REG_BASE +0x5073d*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5073e*4 +0x02000000,0xd909); +reg_write( DDR_REG_BASE +0x5073f*4 +0x02000000,0xc280); +reg_write( DDR_REG_BASE +0x50740*4 +0x02000000,0xcce); +reg_write( DDR_REG_BASE +0x50741*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50742*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x50743*4 +0x02000000,0xd830); +reg_write( DDR_REG_BASE +0x50744*4 +0x02000000,0xc180); +reg_write( DDR_REG_BASE +0x50745*4 +0x02000000,0xc0e); +reg_write( DDR_REG_BASE +0x50746*4 +0x02000000,0x160); +reg_write( DDR_REG_BASE +0x50747*4 +0x02000000,0xda09); +reg_write( DDR_REG_BASE +0x50748*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x50749*4 +0x02000000,0xd909); +reg_write( DDR_REG_BASE +0x5074a*4 +0x02000000,0xc280); +reg_write( DDR_REG_BASE +0x5074b*4 +0x02000000,0xcba); +reg_write( DDR_REG_BASE +0x5074c*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x5074d*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5074e*4 +0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x5074f*4 +0x02000000,0x3d02); +reg_write( DDR_REG_BASE +0x50750*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x50751*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50752*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50753*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x50754*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50755*4 +0x02000000,0x12); +reg_write( DDR_REG_BASE +0x50756*4 +0x02000000,0x7534); +reg_write( DDR_REG_BASE +0x50757*4 +0x02000000,0x20e0); +reg_write( DDR_REG_BASE +0x50758*4 +0x02000000,0x7c5); +reg_write( DDR_REG_BASE +0x50759*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x5075a*4 +0x02000000,0x1a10); +reg_write( DDR_REG_BASE +0x5075b*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x5075c*4 +0x02000000,0xc0e6); +reg_write( DDR_REG_BASE +0x5075d*4 +0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x5075e*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5075f*4 +0x02000000,0xe4); +reg_write( DDR_REG_BASE +0x50760*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x50761*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50762*4 +0x02000000,0x667); +reg_write( DDR_REG_BASE +0x50763*4 +0x02000000,0x835); +reg_write( DDR_REG_BASE +0x50764*4 +0x02000000,0xb0); +reg_write( DDR_REG_BASE +0x50765*4 +0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x50766*4 +0x02000000,0x7114); +reg_write( DDR_REG_BASE +0x50767*4 +0x02000000,0xd825); +reg_write( DDR_REG_BASE +0x50768*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50769*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5076a*4 +0x02000000,0x30); +reg_write( DDR_REG_BASE +0x5076b*4 +0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x5076c*4 +0x02000000,0xf42a); +reg_write( DDR_REG_BASE +0x5076d*4 +0x02000000,0x8a25); +reg_write( DDR_REG_BASE +0x5076e*4 +0x02000000,0xaa23); +reg_write( DDR_REG_BASE +0x5076f*4 +0x02000000,0x8aa4); +reg_write( DDR_REG_BASE +0x50770*4 +0x02000000,0x7b34); +reg_write( DDR_REG_BASE +0x50771*4 +0x02000000,0xaaa2); +reg_write( DDR_REG_BASE +0x50772*4 +0x02000000,0x96c0); +reg_write( DDR_REG_BASE +0x50773*4 +0x02000000,0x88e0); +reg_write( DDR_REG_BASE +0x50774*4 +0x02000000,0x78bb); +reg_write( DDR_REG_BASE +0x50775*4 +0x02000000,0xb4e0); +reg_write( DDR_REG_BASE +0x50776*4 +0x02000000,0xaa00); +reg_write( DDR_REG_BASE +0x50777*4 +0x02000000,0xe5f); +reg_write( DDR_REG_BASE +0x50778*4 +0x02000000,0x1171); +reg_write( DDR_REG_BASE +0x50779*4 +0x02000000,0xaa61); +reg_write( DDR_REG_BASE +0x5077a*4 +0x02000000,0xb4e1); +reg_write( DDR_REG_BASE +0x5077b*4 +0x02000000,0xf02d); +reg_write( DDR_REG_BASE +0x5077c*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5077d*4 +0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x5077e*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5077f*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x50780*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50781*4 +0x02000000,0x58); +reg_write( DDR_REG_BASE +0x50782*4 +0x02000000,0xb421); +reg_write( DDR_REG_BASE +0x50783*4 +0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x50784*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50785*4 +0x02000000,0xf6); +reg_write( DDR_REG_BASE +0x50786*4 +0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x50787*4 +0x02000000,0xb404); +reg_write( DDR_REG_BASE +0x50788*4 +0x02000000,0x1c06); +reg_write( DDR_REG_BASE +0x50789*4 +0x02000000,0x13c5); +reg_write( DDR_REG_BASE +0x5078a*4 +0x02000000,0x8a27); +reg_write( DDR_REG_BASE +0x5078b*4 +0x02000000,0xaa23); +reg_write( DDR_REG_BASE +0x5078c*4 +0x02000000,0x8a06); +reg_write( DDR_REG_BASE +0x5078d*4 +0x02000000,0x7b34); +reg_write( DDR_REG_BASE +0x5078e*4 +0x02000000,0xaa02); +reg_write( DDR_REG_BASE +0x5078f*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x50790*4 +0x02000000,0xaa00); +reg_write( DDR_REG_BASE +0x50791*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50792*4 +0x02000000,0xaa61); +reg_write( DDR_REG_BASE +0x50793*4 +0x02000000,0x1cfe); +reg_write( DDR_REG_BASE +0x50794*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50795*4 +0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x50796*4 +0x02000000,0x88a0); +reg_write( DDR_REG_BASE +0x50797*4 +0x02000000,0xb4a0); +reg_write( DDR_REG_BASE +0x50798*4 +0x02000000,0x8a27); +reg_write( DDR_REG_BASE +0x50799*4 +0x02000000,0xaa23); +reg_write( DDR_REG_BASE +0x5079a*4 +0x02000000,0x8a04); +reg_write( DDR_REG_BASE +0x5079b*4 +0x02000000,0x7b34); +reg_write( DDR_REG_BASE +0x5079c*4 +0x02000000,0xaa02); +reg_write( DDR_REG_BASE +0x5079d*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5079e*4 +0x02000000,0xaa00); +reg_write( DDR_REG_BASE +0x5079f*4 +0x02000000,0xaa61); +reg_write( DDR_REG_BASE +0x507a0*4 +0x02000000,0x9600); +reg_write( DDR_REG_BASE +0x507a1*4 +0x02000000,0x829); +reg_write( DDR_REG_BASE +0x507a2*4 +0x02000000,0x151); +reg_write( DDR_REG_BASE +0x507a3*4 +0x02000000,0xb4a1); +reg_write( DDR_REG_BASE +0x507a4*4 +0x02000000,0xf015); +reg_write( DDR_REG_BASE +0x507a5*4 +0x02000000,0x1c02); +reg_write( DDR_REG_BASE +0x507a6*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x507a7*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x507a8*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x507a9*4 +0x02000000,0xfe); +reg_write( DDR_REG_BASE +0x507aa*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x507ab*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x507ac*4 +0x02000000,0x3c5); +reg_write( DDR_REG_BASE +0x507ad*4 +0x02000000,0x19f8); +reg_write( DDR_REG_BASE +0x507ae*4 +0x02000000,0x8004); +reg_write( DDR_REG_BASE +0x507af*4 +0x02000000,0x19f6); +reg_write( DDR_REG_BASE +0x507b0*4 +0x02000000,0x8005); +reg_write( DDR_REG_BASE +0x507b1*4 +0x02000000,0x19fe); +reg_write( DDR_REG_BASE +0x507b2*4 +0x02000000,0x8005); +reg_write( DDR_REG_BASE +0x507b3*4 +0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x507b4*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x507b5*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x507b6*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x507b7*4 +0x02000000,0x58); +reg_write( DDR_REG_BASE +0x507b8*4 +0x02000000,0xb401); +reg_write( DDR_REG_BASE +0x507b9*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x507ba*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x507bb*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x507bc*4 +0x02000000,0xf6); +reg_write( DDR_REG_BASE +0x507bd*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x507be*4 +0x02000000,0xb024); +reg_write( DDR_REG_BASE +0x507bf*4 +0x02000000,0x18fe); +reg_write( DDR_REG_BASE +0x507c0*4 +0x02000000,0x8044); +reg_write( DDR_REG_BASE +0x507c1*4 +0x02000000,0xb023); +reg_write( DDR_REG_BASE +0x507c2*4 +0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x507c3*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x507c4*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x507c5*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x507c6*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x507c7*4 +0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x507c8*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x507c9*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x507ca*4 +0x02000000,0xf4); +reg_write( DDR_REG_BASE +0x507cb*4 +0x02000000,0x9600); +reg_write( DDR_REG_BASE +0x507cc*4 +0x02000000,0x6ea2); +reg_write( DDR_REG_BASE +0x507cd*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x507ce*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x507cf*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x507d0*4 +0x02000000,0x1500); +reg_write( DDR_REG_BASE +0x507d1*4 +0x02000000,0x111b); +reg_write( DDR_REG_BASE +0x507d2*4 +0x02000000,0x95e3); +reg_write( DDR_REG_BASE +0x507d3*4 +0x02000000,0x1508); +reg_write( DDR_REG_BASE +0x507d4*4 +0x02000000,0x110b); +reg_write( DDR_REG_BASE +0x507d5*4 +0x02000000,0x1d08); +reg_write( DDR_REG_BASE +0x507d6*4 +0x02000000,0x13c5); +reg_write( DDR_REG_BASE +0x507d7*4 +0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x507d8*4 +0x02000000,0x1d06); +reg_write( DDR_REG_BASE +0x507d9*4 +0x02000000,0x13c5); +reg_write( DDR_REG_BASE +0x507da*4 +0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x507db*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x507dc*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x507dd*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x507de*4 +0x02000000,0x664); +reg_write( DDR_REG_BASE +0x507df*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x507e0*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x507e1*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x507e2*4 +0x02000000,0x190); +reg_write( DDR_REG_BASE +0x507e3*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x507e4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x507e5*4 +0x02000000,0x2af8); +reg_write( DDR_REG_BASE +0x507e6*4 +0x02000000,0xc86); +reg_write( DDR_REG_BASE +0x507e7*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x507e8*4 +0x02000000,0x1efa); +reg_write( DDR_REG_BASE +0x507e9*4 +0x02000000,0x9485); +reg_write( DDR_REG_BASE +0x507ea*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x507eb*4 +0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x507ec*4 +0x02000000,0xb5e3); +reg_write( DDR_REG_BASE +0x507ed*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x507ee*4 +0x02000000,0x16c4); +reg_write( DDR_REG_BASE +0x507ef*4 +0x02000000,0x1d08); +reg_write( DDR_REG_BASE +0x507f0*4 +0x02000000,0x12c4); +reg_write( DDR_REG_BASE +0x507f1*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x507f2*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x507f3*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x507f4*4 +0x02000000,0x664); +reg_write( DDR_REG_BASE +0x507f5*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x507f6*4 +0x02000000,0xb8a0); +reg_write( DDR_REG_BASE +0x507f7*4 +0x02000000,0x6829); +reg_write( DDR_REG_BASE +0x507f8*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x507f9*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x507fa*4 +0x02000000,0x57c); +reg_write( DDR_REG_BASE +0x507fb*4 +0x02000000,0xa821); +reg_write( DDR_REG_BASE +0x507fc*4 +0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x507fd*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x507fe*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x507ff*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50800*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50801*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50802*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50803*4 +0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x50804*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50805*4 +0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x50806*4 +0x02000000,0x9720); +reg_write( DDR_REG_BASE +0x50807*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50808*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50809*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5080a*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5080b*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x5080c*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x5080d*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5080e*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x5080f*4 +0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x50810*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x50811*4 +0x02000000,0xea06); +reg_write( DDR_REG_BASE +0x50812*4 +0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x50813*4 +0x02000000,0xa01); +reg_write( DDR_REG_BASE +0x50814*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x50815*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50816*4 +0x02000000,0xb8c3); +reg_write( DDR_REG_BASE +0x50817*4 +0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x50818*4 +0x02000000,0x70); +reg_write( DDR_REG_BASE +0x50819*4 +0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x5081a*4 +0x02000000,0x807); +reg_write( DDR_REG_BASE +0x5081b*4 +0x02000000,0x190); +reg_write( DDR_REG_BASE +0x5081c*4 +0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x5081d*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5081e*4 +0x02000000,0xc16); +reg_write( DDR_REG_BASE +0x5081f*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50820*4 +0x02000000,0xd940); +reg_write( DDR_REG_BASE +0x50821*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50822*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x50823*4 +0x02000000,0xe112); +reg_write( DDR_REG_BASE +0x50824*4 +0x02000000,0x1ede); +reg_write( DDR_REG_BASE +0x50825*4 +0x02000000,0x1055); +reg_write( DDR_REG_BASE +0x50826*4 +0x02000000,0x1ea6); +reg_write( DDR_REG_BASE +0x50827*4 +0x02000000,0x9055); +reg_write( DDR_REG_BASE +0x50828*4 +0x02000000,0x17b6); +reg_write( DDR_REG_BASE +0x50829*4 +0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x5082a*4 +0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x5082b*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5082c*4 +0x02000000,0xed29); +reg_write( DDR_REG_BASE +0x5082d*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x5082e*4 +0x02000000,0x84f); +reg_write( DDR_REG_BASE +0x5082f*4 +0x02000000,0x3bf); +reg_write( DDR_REG_BASE +0x50830*4 +0x02000000,0xd91c); +reg_write( DDR_REG_BASE +0x50831*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50832*4 +0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x50833*4 +0x02000000,0xc07); +reg_write( DDR_REG_BASE +0x50834*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50835*4 +0x02000000,0xb88f); +reg_write( DDR_REG_BASE +0x50836*4 +0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x50837*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50838*4 +0x02000000,0xbe2); +reg_write( DDR_REG_BASE +0x50839*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x5083a*4 +0x02000000,0x1ef6); +reg_write( DDR_REG_BASE +0x5083b*4 +0x02000000,0x9205); +reg_write( DDR_REG_BASE +0x5083c*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5083d*4 +0x02000000,0xf); +reg_write( DDR_REG_BASE +0x5083e*4 +0x02000000,0x4240); +reg_write( DDR_REG_BASE +0x5083f*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50840*4 +0x02000000,0xbd2); +reg_write( DDR_REG_BASE +0x50841*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50842*4 +0x02000000,0x1ef6); +reg_write( DDR_REG_BASE +0x50843*4 +0x02000000,0x9245); +reg_write( DDR_REG_BASE +0x50844*4 +0x02000000,0x17be); +reg_write( DDR_REG_BASE +0x50845*4 +0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x50846*4 +0x02000000,0x1ef0); +reg_write( DDR_REG_BASE +0x50847*4 +0x02000000,0x9045); +reg_write( DDR_REG_BASE +0x50848*4 +0x02000000,0x1ef6); +reg_write( DDR_REG_BASE +0x50849*4 +0x02000000,0x9205); +reg_write( DDR_REG_BASE +0x5084a*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x5084b*4 +0x02000000,0x8); +reg_write( DDR_REG_BASE +0x5084c*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x5084d*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x5084e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5084f*4 +0x02000000,0x3e00); +reg_write( DDR_REG_BASE +0x50850*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50851*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50852*4 +0x02000000,0xb88e); +reg_write( DDR_REG_BASE +0x50853*4 +0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x50854*4 +0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x50855*4 +0x02000000,0x1ef6); +reg_write( DDR_REG_BASE +0x50856*4 +0x02000000,0x9205); +reg_write( DDR_REG_BASE +0x50857*4 +0x02000000,0x1ef0); +reg_write( DDR_REG_BASE +0x50858*4 +0x02000000,0x9045); +reg_write( DDR_REG_BASE +0x50859*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5085a*4 +0x02000000,0x76c4); +reg_write( DDR_REG_BASE +0x5085b*4 +0x02000000,0x9013); +reg_write( DDR_REG_BASE +0x5085c*4 +0x02000000,0xe050); +reg_write( DDR_REG_BASE +0x5085d*4 +0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x5085e*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x5085f*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50860*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50861*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50862*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50863*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50864*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50865*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50866*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50867*4 +0x02000000,0xf4); +reg_write( DDR_REG_BASE +0x50868*4 +0x02000000,0x6ea2); +reg_write( DDR_REG_BASE +0x50869*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5086a*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5086b*4 +0x02000000,0x111b); +reg_write( DDR_REG_BASE +0x5086c*4 +0x02000000,0x1500); +reg_write( DDR_REG_BASE +0x5086d*4 +0x02000000,0x111e); +reg_write( DDR_REG_BASE +0x5086e*4 +0x02000000,0x1506); +reg_write( DDR_REG_BASE +0x5086f*4 +0x02000000,0x110b); +reg_write( DDR_REG_BASE +0x50870*4 +0x02000000,0x95e4); +reg_write( DDR_REG_BASE +0x50871*4 +0x02000000,0x1d08); +reg_write( DDR_REG_BASE +0x50872*4 +0x02000000,0x13c5); +reg_write( DDR_REG_BASE +0x50873*4 +0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x50874*4 +0x02000000,0x1d06); +reg_write( DDR_REG_BASE +0x50875*4 +0x02000000,0x13c5); +reg_write( DDR_REG_BASE +0x50876*4 +0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x50877*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50878*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50879*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x5087a*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x5087b*4 +0x02000000,0x190); +reg_write( DDR_REG_BASE +0x5087c*4 +0x02000000,0xd834); +reg_write( DDR_REG_BASE +0x5087d*4 +0x02000000,0x1efa); +reg_write( DDR_REG_BASE +0x5087e*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5087f*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50880*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50881*4 +0x02000000,0x2af8); +reg_write( DDR_REG_BASE +0x50882*4 +0x02000000,0xb4e); +reg_write( DDR_REG_BASE +0x50883*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50884*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50885*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50886*4 +0x02000000,0x16c4); +reg_write( DDR_REG_BASE +0x50887*4 +0x02000000,0x1d06); +reg_write( DDR_REG_BASE +0x50888*4 +0x02000000,0x12c4); +reg_write( DDR_REG_BASE +0x50889*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x5088a*4 +0x02000000,0x1784); +reg_write( DDR_REG_BASE +0x5088b*4 +0x02000000,0xb5e4); +reg_write( DDR_REG_BASE +0x5088c*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x5088d*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x5088e*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5088f*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50890*4 +0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x50891*4 +0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x50892*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50893*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50894*4 +0x02000000,0x783d); +reg_write( DDR_REG_BASE +0x50895*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50896*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50897*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50898*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50899*4 +0x02000000,0xc1a2); +reg_write( DDR_REG_BASE +0x5089a*4 +0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x5089b*4 +0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x5089c*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5089d*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x5089e*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5089f*4 +0x02000000,0x1a); +reg_write( DDR_REG_BASE +0x508a0*4 +0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x508a1*4 +0x02000000,0xd8f0); +reg_write( DDR_REG_BASE +0x508a2*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x508a3*4 +0x02000000,0x3e2); +reg_write( DDR_REG_BASE +0x508a4*4 +0x02000000,0x4358); +reg_write( DDR_REG_BASE +0x508a5*4 +0x02000000,0x9fa); +reg_write( DDR_REG_BASE +0x508a6*4 +0x02000000,0x160); +reg_write( DDR_REG_BASE +0x508a7*4 +0x02000000,0x782b); +reg_write( DDR_REG_BASE +0x508a8*4 +0x02000000,0xf469); +reg_write( DDR_REG_BASE +0x508a9*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x508aa*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x508ab*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x508ac*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x508ad*4 +0x02000000,0x8cb); +reg_write( DDR_REG_BASE +0x508ae*4 +0x02000000,0xbf); +reg_write( DDR_REG_BASE +0x508af*4 +0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x508b0*4 +0x02000000,0xca15); +reg_write( DDR_REG_BASE +0x508b1*4 +0x02000000,0x120c); +reg_write( DDR_REG_BASE +0x508b2*4 +0x02000000,0x308d); +reg_write( DDR_REG_BASE +0x508b3*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x508b4*4 +0x02000000,0x4061); +reg_write( DDR_REG_BASE +0x508b5*4 +0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x508b6*4 +0x02000000,0xdb40); +reg_write( DDR_REG_BASE +0x508b7*4 +0x02000000,0x1a15); +reg_write( DDR_REG_BASE +0x508b8*4 +0x02000000,0x30c3); +reg_write( DDR_REG_BASE +0x508b9*4 +0x02000000,0xf52); +reg_write( DDR_REG_BASE +0x508ba*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x508bb*4 +0x02000000,0x1a0c); +reg_write( DDR_REG_BASE +0x508bc*4 +0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x508bd*4 +0x02000000,0xb1b); +reg_write( DDR_REG_BASE +0x508be*4 +0x02000000,0x1030); +reg_write( DDR_REG_BASE +0x508bf*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x508c0*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x508c1*4 +0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x508c2*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x508c3*4 +0x02000000,0xdb80); +reg_write( DDR_REG_BASE +0x508c4*4 +0x02000000,0xcfa); +reg_write( DDR_REG_BASE +0x508c5*4 +0x02000000,0x160); +reg_write( DDR_REG_BASE +0x508c6*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x508c7*4 +0x02000000,0x3001); +reg_write( DDR_REG_BASE +0x508c8*4 +0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x508c9*4 +0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x508ca*4 +0x02000000,0xf4a); +reg_write( DDR_REG_BASE +0x508cb*4 +0x02000000,0x160); +reg_write( DDR_REG_BASE +0x508cc*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x508cd*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x508ce*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x508cf*4 +0x02000000,0x669); +reg_write( DDR_REG_BASE +0x508d0*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x508d1*4 +0x02000000,0x9f); +reg_write( DDR_REG_BASE +0x508d2*4 +0x02000000,0x88c0); +reg_write( DDR_REG_BASE +0x508d3*4 +0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x508d4*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x508d5*4 +0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x508d6*4 +0x02000000,0x1fc1); +reg_write( DDR_REG_BASE +0x508d7*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x508d8*4 +0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x508d9*4 +0x02000000,0xb2f); +reg_write( DDR_REG_BASE +0x508da*4 +0x02000000,0x306e); +reg_write( DDR_REG_BASE +0x508db*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x508dc*4 +0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x508dd*4 +0x02000000,0x239f); +reg_write( DDR_REG_BASE +0x508de*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x508df*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x508e0*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x508e1*4 +0x02000000,0x6dc); +reg_write( DDR_REG_BASE +0x508e2*4 +0x02000000,0x7b14); +reg_write( DDR_REG_BASE +0x508e3*4 +0x02000000,0x627f); +reg_write( DDR_REG_BASE +0x508e4*4 +0x02000000,0x634b); +reg_write( DDR_REG_BASE +0x508e5*4 +0x02000000,0x8f41); +reg_write( DDR_REG_BASE +0x508e6*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x508e7*4 +0x02000000,0x2309); +reg_write( DDR_REG_BASE +0x508e8*4 +0x02000000,0x10cb); +reg_write( DDR_REG_BASE +0x508e9*4 +0x02000000,0x2608); +reg_write( DDR_REG_BASE +0x508ea*4 +0x02000000,0x309e); +reg_write( DDR_REG_BASE +0x508eb*4 +0x02000000,0x8e7); +reg_write( DDR_REG_BASE +0x508ec*4 +0x02000000,0x87f4); +reg_write( DDR_REG_BASE +0x508ed*4 +0x02000000,0x7b8f); +reg_write( DDR_REG_BASE +0x508ee*4 +0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x508ef*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x508f0*4 +0x02000000,0x9d3); +reg_write( DDR_REG_BASE +0x508f1*4 +0x02000000,0x8254); +reg_write( DDR_REG_BASE +0x508f2*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x508f3*4 +0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x508f4*4 +0x02000000,0xff9); +reg_write( DDR_REG_BASE +0x508f5*4 +0x02000000,0xb025); +reg_write( DDR_REG_BASE +0x508f6*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x508f7*4 +0x02000000,0xca65); +reg_write( DDR_REG_BASE +0x508f8*4 +0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x508f9*4 +0x02000000,0x321e); +reg_write( DDR_REG_BASE +0x508fa*4 +0x02000000,0x2342); +reg_write( DDR_REG_BASE +0x508fb*4 +0x02000000,0x120b); +reg_write( DDR_REG_BASE +0x508fc*4 +0x02000000,0x2009); +reg_write( DDR_REG_BASE +0x508fd*4 +0x02000000,0x783); +reg_write( DDR_REG_BASE +0x508fe*4 +0x02000000,0xca64); +reg_write( DDR_REG_BASE +0x508ff*4 +0x02000000,0x1a67); +reg_write( DDR_REG_BASE +0x50900*4 +0x02000000,0x30c2); +reg_write( DDR_REG_BASE +0x50901*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50902*4 +0x02000000,0x32); +reg_write( DDR_REG_BASE +0x50903*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x50904*4 +0x02000000,0x2308); +reg_write( DDR_REG_BASE +0x50905*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x50906*4 +0x02000000,0x1a66); +reg_write( DDR_REG_BASE +0x50907*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x50908*4 +0x02000000,0x7a0f); +reg_write( DDR_REG_BASE +0x50909*4 +0x02000000,0xfe2); +reg_write( DDR_REG_BASE +0x5090a*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x5090b*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x5090c*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5090d*4 +0x02000000,0x1a0c); +reg_write( DDR_REG_BASE +0x5090e*4 +0x02000000,0x3342); +reg_write( DDR_REG_BASE +0x5090f*4 +0x02000000,0x1a15); +reg_write( DDR_REG_BASE +0x50910*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x50911*4 +0x02000000,0xc0a2); +reg_write( DDR_REG_BASE +0x50912*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50913*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50914*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50915*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50916*4 +0x02000000,0xc0e6); +reg_write( DDR_REG_BASE +0x50917*4 +0x02000000,0xc604); +reg_write( DDR_REG_BASE +0x50918*4 +0x02000000,0x90f); +reg_write( DDR_REG_BASE +0x50919*4 +0x02000000,0x7f4); +reg_write( DDR_REG_BASE +0x5091a*4 +0x02000000,0xc503); +reg_write( DDR_REG_BASE +0x5091b*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5091c*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5091d*4 +0x02000000,0x1003); +reg_write( DDR_REG_BASE +0x5091e*4 +0x02000000,0xf03c); +reg_write( DDR_REG_BASE +0x5091f*4 +0x02000000,0x2014); +reg_write( DDR_REG_BASE +0x50920*4 +0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x50921*4 +0x02000000,0x8ce1); +reg_write( DDR_REG_BASE +0x50922*4 +0x02000000,0xff3); +reg_write( DDR_REG_BASE +0x50923*4 +0x02000000,0x90a4); +reg_write( DDR_REG_BASE +0x50924*4 +0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x50925*4 +0x02000000,0x33c0); +reg_write( DDR_REG_BASE +0x50926*4 +0x02000000,0x8ce0); +reg_write( DDR_REG_BASE +0x50927*4 +0x02000000,0xaeb); +reg_write( DDR_REG_BASE +0x50928*4 +0x02000000,0x83e4); +reg_write( DDR_REG_BASE +0x50929*4 +0x02000000,0x43e9); +reg_write( DDR_REG_BASE +0x5092a*4 +0x02000000,0x2602); +reg_write( DDR_REG_BASE +0x5092b*4 +0x02000000,0x308f); +reg_write( DDR_REG_BASE +0x5092c*4 +0x02000000,0x2202); +reg_write( DDR_REG_BASE +0x5092d*4 +0x02000000,0x2cc); +reg_write( DDR_REG_BASE +0x5092e*4 +0x02000000,0x7074); +reg_write( DDR_REG_BASE +0x5092f*4 +0x02000000,0x74fd); +reg_write( DDR_REG_BASE +0x50930*4 +0x02000000,0xae80); +reg_write( DDR_REG_BASE +0x50931*4 +0x02000000,0x4628); +reg_write( DDR_REG_BASE +0x50932*4 +0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x50933*4 +0x02000000,0xe2b); +reg_write( DDR_REG_BASE +0x50934*4 +0x02000000,0x30a4); +reg_write( DDR_REG_BASE +0x50935*4 +0x02000000,0x7ccf); +reg_write( DDR_REG_BASE +0x50936*4 +0x02000000,0xc23); +reg_write( DDR_REG_BASE +0x50937*4 +0x02000000,0x17f5); +reg_write( DDR_REG_BASE +0x50938*4 +0x02000000,0x7074); +reg_write( DDR_REG_BASE +0x50939*4 +0x02000000,0xdcff); +reg_write( DDR_REG_BASE +0x5093a*4 +0x02000000,0x24ca); +reg_write( DDR_REG_BASE +0x5093b*4 +0x02000000,0x1062); +reg_write( DDR_REG_BASE +0x5093c*4 +0x02000000,0x64fe); +reg_write( DDR_REG_BASE +0x5093d*4 +0x02000000,0x7ccd); +reg_write( DDR_REG_BASE +0x5093e*4 +0x02000000,0x2014); +reg_write( DDR_REG_BASE +0x5093f*4 +0x02000000,0x30c); +reg_write( DDR_REG_BASE +0x50940*4 +0x02000000,0x1400); +reg_write( DDR_REG_BASE +0x50941*4 +0x02000000,0x108b); +reg_write( DDR_REG_BASE +0x50942*4 +0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x50943*4 +0x02000000,0x109e); +reg_write( DDR_REG_BASE +0x50944*4 +0x02000000,0xadf); +reg_write( DDR_REG_BASE +0x50945*4 +0x02000000,0x82e5); +reg_write( DDR_REG_BASE +0x50946*4 +0x02000000,0x7fcd); +reg_write( DDR_REG_BASE +0x50947*4 +0x02000000,0x7074); +reg_write( DDR_REG_BASE +0x50948*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50949*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x5094a*4 +0x02000000,0x61); +reg_write( DDR_REG_BASE +0x5094b*4 +0x02000000,0x60f8); +reg_write( DDR_REG_BASE +0x5094c*4 +0x02000000,0x7a0d); +reg_write( DDR_REG_BASE +0x5094d*4 +0x02000000,0xca0c); +reg_write( DDR_REG_BASE +0x5094e*4 +0x02000000,0xf203); +reg_write( DDR_REG_BASE +0x5094f*4 +0x02000000,0x4a31); +reg_write( DDR_REG_BASE +0x50950*4 +0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x50951*4 +0x02000000,0x7942); +reg_write( DDR_REG_BASE +0x50952*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x50953*4 +0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x50954*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x50955*4 +0x02000000,0xea06); +reg_write( DDR_REG_BASE +0x50956*4 +0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x50957*4 +0x02000000,0xa01); +reg_write( DDR_REG_BASE +0x50958*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x50959*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5095a*4 +0x02000000,0xad00); +reg_write( DDR_REG_BASE +0x5095b*4 +0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x5095c*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5095d*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5095e*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5095f*4 +0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x50960*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50961*4 +0x02000000,0x7101); +reg_write( DDR_REG_BASE +0x50962*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50963*4 +0x02000000,0x6); +reg_write( DDR_REG_BASE +0x50964*4 +0x02000000,0x4348); +reg_write( DDR_REG_BASE +0x50965*4 +0x02000000,0x218c); +reg_write( DDR_REG_BASE +0x50966*4 +0x02000000,0x864a); +reg_write( DDR_REG_BASE +0x50967*4 +0x02000000,0x96); +reg_write( DDR_REG_BASE +0x50968*4 +0x02000000,0x2d); +reg_write( DDR_REG_BASE +0x50969*4 +0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x5096a*4 +0x02000000,0xeca); +reg_write( DDR_REG_BASE +0x5096b*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x5096c*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5096d*4 +0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x5096e*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x5096f*4 +0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x50970*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x50971*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50972*4 +0x02000000,0x68ec); +reg_write( DDR_REG_BASE +0x50973*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50974*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50975*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50976*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50977*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50978*4 +0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x50979*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5097a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5097b*4 +0x02000000,0xf033); +reg_write( DDR_REG_BASE +0x5097c*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x5097d*4 +0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x5097e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5097f*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x50980*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50981*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x50982*4 +0x02000000,0x381); +reg_write( DDR_REG_BASE +0x50983*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x50984*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x50985*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50986*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50987*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x50988*4 +0x02000000,0xb891); +reg_write( DDR_REG_BASE +0x50989*4 +0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x5098a*4 +0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x5098b*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5098c*4 +0x02000000,0xf0a); +reg_write( DDR_REG_BASE +0x5098d*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x5098e*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x5098f*4 +0x02000000,0xeb08); +reg_write( DDR_REG_BASE +0x50990*4 +0x02000000,0x2704); +reg_write( DDR_REG_BASE +0x50991*4 +0x02000000,0x1f81); +reg_write( DDR_REG_BASE +0x50992*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50993*4 +0x02000000,0xfffc); +reg_write( DDR_REG_BASE +0x50994*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x50995*4 +0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x50996*4 +0x02000000,0x78e2); +reg_write( DDR_REG_BASE +0x50997*4 +0x02000000,0x7a0e); +reg_write( DDR_REG_BASE +0x50998*4 +0x02000000,0x785c); +reg_write( DDR_REG_BASE +0x50999*4 +0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x5099a*4 +0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x5099b*4 +0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x5099c*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x5099d*4 +0x02000000,0xd81b); +reg_write( DDR_REG_BASE +0x5099e*4 +0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x5099f*4 +0x02000000,0x801); +reg_write( DDR_REG_BASE +0x509a0*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x509a1*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x509a2*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x509a3*4 +0x02000000,0x6238); +reg_write( DDR_REG_BASE +0x509a4*4 +0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x509a5*4 +0x02000000,0x4831); +reg_write( DDR_REG_BASE +0x509a6*4 +0x02000000,0x2a44); +reg_write( DDR_REG_BASE +0x509a7*4 +0x02000000,0x800); +reg_write( DDR_REG_BASE +0x509a8*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x509a9*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x509aa*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x509ab*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x509ac*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x509ad*4 +0x02000000,0xda1); +reg_write( DDR_REG_BASE +0x509ae*4 +0x02000000,0x90b4); +reg_write( DDR_REG_BASE +0x509af*4 +0x02000000,0x2655); +reg_write( DDR_REG_BASE +0x509b0*4 +0x02000000,0x3800); +reg_write( DDR_REG_BASE +0x509b1*4 +0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x509b2*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x509b3*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x509b4*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x509b5*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x509b6*4 +0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x509b7*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x509b8*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x509b9*4 +0x02000000,0x6); +reg_write( DDR_REG_BASE +0x509ba*4 +0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x509bb*4 +0x02000000,0x886); +reg_write( DDR_REG_BASE +0x509bc*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x509bd*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x509be*4 +0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x509bf*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x509c0*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x509c1*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x509c2*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x509c3*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x509c4*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x509c5*4 +0x02000000,0x1c6); +reg_write( DDR_REG_BASE +0x509c6*4 +0x02000000,0x95c0); +reg_write( DDR_REG_BASE +0x509c7*4 +0x02000000,0xbecb); +reg_write( DDR_REG_BASE +0x509c8*4 +0x02000000,0x264f); +reg_write( DDR_REG_BASE +0x509c9*4 +0x02000000,0x12cf); +reg_write( DDR_REG_BASE +0x509ca*4 +0x02000000,0x2605); +reg_write( DDR_REG_BASE +0x509cb*4 +0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x509cc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x509cd*4 +0x02000000,0xc00); +reg_write( DDR_REG_BASE +0x509ce*4 +0x02000000,0xb5e0); +reg_write( DDR_REG_BASE +0x509cf*4 +0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x509d0*4 +0x02000000,0x85a); +reg_write( DDR_REG_BASE +0x509d1*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x509d2*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x509d3*4 +0x02000000,0xb5e0); +reg_write( DDR_REG_BASE +0x509d4*4 +0x02000000,0x9501); +reg_write( DDR_REG_BASE +0x509d5*4 +0x02000000,0xb5c0); +reg_write( DDR_REG_BASE +0x509d6*4 +0x02000000,0xb8c9); +reg_write( DDR_REG_BASE +0x509d7*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x509d8*4 +0x02000000,0x6f5); +reg_write( DDR_REG_BASE +0x509d9*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x509da*4 +0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x509db*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x509dc*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x509dd*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x509de*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x509df*4 +0x02000000,0xc1ac); +reg_write( DDR_REG_BASE +0x509e0*4 +0x02000000,0xc249); +reg_write( DDR_REG_BASE +0x509e1*4 +0x02000000,0xc144); +reg_write( DDR_REG_BASE +0x509e2*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x509e3*4 +0x02000000,0x744c); +reg_write( DDR_REG_BASE +0x509e4*4 +0x02000000,0xc34b); +reg_write( DDR_REG_BASE +0x509e5*4 +0x02000000,0xb86); +reg_write( DDR_REG_BASE +0x509e6*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x509e7*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x509e8*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x509e9*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x509ea*4 +0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x509eb*4 +0x02000000,0x851); +reg_write( DDR_REG_BASE +0x509ec*4 +0x02000000,0xb5); +reg_write( DDR_REG_BASE +0x509ed*4 +0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x509ee*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x509ef*4 +0x02000000,0xc609); +reg_write( DDR_REG_BASE +0x509f0*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x509f1*4 +0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x509f2*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x509f3*4 +0x02000000,0xf01c); +reg_write( DDR_REG_BASE +0x509f4*4 +0x02000000,0x79cc); +reg_write( DDR_REG_BASE +0x509f5*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x509f6*4 +0x02000000,0x7214); +reg_write( DDR_REG_BASE +0x509f7*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x509f8*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x509f9*4 +0x02000000,0x71a); +reg_write( DDR_REG_BASE +0x509fa*4 +0x02000000,0xf403); +reg_write( DDR_REG_BASE +0x509fb*4 +0x02000000,0x6109); +reg_write( DDR_REG_BASE +0x509fc*4 +0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x509fd*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x509fe*4 +0x02000000,0x8822); +reg_write( DDR_REG_BASE +0x509ff*4 +0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x50a00*4 +0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x50a01*4 +0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x50a02*4 +0x02000000,0x2138); +reg_write( DDR_REG_BASE +0x50a03*4 +0x02000000,0x6c0); +reg_write( DDR_REG_BASE +0x50a04*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50a05*4 +0x02000000,0x57); +reg_write( DDR_REG_BASE +0x50a06*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50a07*4 +0x02000000,0xe36); +reg_write( DDR_REG_BASE +0x50a08*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50a09*4 +0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x50a0a*4 +0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x50a0b*4 +0x02000000,0x25ca); +reg_write( DDR_REG_BASE +0x50a0c*4 +0x02000000,0x1061); +reg_write( DDR_REG_BASE +0x50a0d*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x50a0e*4 +0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x50a0f*4 +0x02000000,0xecd); +reg_write( DDR_REG_BASE +0x50a10*4 +0x02000000,0x9024); +reg_write( DDR_REG_BASE +0x50a11*4 +0x02000000,0xd941); +reg_write( DDR_REG_BASE +0x50a12*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50a13*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x50a14*4 +0x02000000,0xf08e); +reg_write( DDR_REG_BASE +0x50a15*4 +0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x50a16*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50a17*4 +0x02000000,0xc64a); +reg_write( DDR_REG_BASE +0x50a18*4 +0x02000000,0xf03b); +reg_write( DDR_REG_BASE +0x50a19*4 +0x02000000,0x943); +reg_write( DDR_REG_BASE +0x50a1a*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50a1b*4 +0x02000000,0xca02); +reg_write( DDR_REG_BASE +0x50a1c*4 +0x02000000,0x83b); +reg_write( DDR_REG_BASE +0x50a1d*4 +0x02000000,0x44); +reg_write( DDR_REG_BASE +0x50a1e*4 +0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x50a1f*4 +0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x50a20*4 +0x02000000,0x7834); +reg_write( DDR_REG_BASE +0x50a21*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50a22*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50a23*4 +0x02000000,0x6dc); +reg_write( DDR_REG_BASE +0x50a24*4 +0x02000000,0x6029); +reg_write( DDR_REG_BASE +0x50a25*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x50a26*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50a27*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50a28*4 +0x02000000,0x6dc); +reg_write( DDR_REG_BASE +0x50a29*4 +0x02000000,0x8861); +reg_write( DDR_REG_BASE +0x50a2a*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x50a2b*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x50a2c*4 +0x02000000,0x631b); +reg_write( DDR_REG_BASE +0x50a2d*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x50a2e*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x50a2f*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x50a30*4 +0x02000000,0xc342); +reg_write( DDR_REG_BASE +0x50a31*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50a32*4 +0x02000000,0x59); +reg_write( DDR_REG_BASE +0x50a33*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x50a34*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50a35*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x50a36*4 +0x02000000,0xd86); +reg_write( DDR_REG_BASE +0x50a37*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50a38*4 +0x02000000,0x43e1); +reg_write( DDR_REG_BASE +0x50a39*4 +0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x50a3a*4 +0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x50a3b*4 +0x02000000,0x7ecf); +reg_write( DDR_REG_BASE +0x50a3c*4 +0x02000000,0x7daf); +reg_write( DDR_REG_BASE +0x50a3d*4 +0x02000000,0x7834); +reg_write( DDR_REG_BASE +0x50a3e*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50a3f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50a40*4 +0x02000000,0x6dc); +reg_write( DDR_REG_BASE +0x50a41*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x50a42*4 +0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x50a43*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50a44*4 +0x02000000,0x6dc); +reg_write( DDR_REG_BASE +0x50a45*4 +0x02000000,0x602a); +reg_write( DDR_REG_BASE +0x50a46*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x50a47*4 +0x02000000,0x8b61); +reg_write( DDR_REG_BASE +0x50a48*4 +0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x50a49*4 +0x02000000,0x6338); +reg_write( DDR_REG_BASE +0x50a4a*4 +0x02000000,0x70d1); +reg_write( DDR_REG_BASE +0x50a4b*4 +0x02000000,0x26ca); +reg_write( DDR_REG_BASE +0x50a4c*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x50a4d*4 +0x02000000,0x6238); +reg_write( DDR_REG_BASE +0x50a4e*4 +0x02000000,0x70b1); +reg_write( DDR_REG_BASE +0x50a4f*4 +0x02000000,0x25ca); +reg_write( DDR_REG_BASE +0x50a50*4 +0x02000000,0x100d); +reg_write( DDR_REG_BASE +0x50a51*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x50a52*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x50a53*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x50a54*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x50a55*4 +0x02000000,0x7a0f); +reg_write( DDR_REG_BASE +0x50a56*4 +0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x50a57*4 +0x02000000,0xa57); +reg_write( DDR_REG_BASE +0x50a58*4 +0x02000000,0x25); +reg_write( DDR_REG_BASE +0x50a59*4 +0x02000000,0xd841); +reg_write( DDR_REG_BASE +0x50a5a*4 +0x02000000,0x784a); +reg_write( DDR_REG_BASE +0x50a5b*4 +0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x50a5c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50a5d*4 +0x02000000,0x71b); +reg_write( DDR_REG_BASE +0x50a5e*4 +0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x50a5f*4 +0x02000000,0x6069); +reg_write( DDR_REG_BASE +0x50a60*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x50a61*4 +0x02000000,0x815); +reg_write( DDR_REG_BASE +0x50a62*4 +0x02000000,0x70); +reg_write( DDR_REG_BASE +0x50a63*4 +0x02000000,0x61f9); +reg_write( DDR_REG_BASE +0x50a64*4 +0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x50a65*4 +0x02000000,0x6078); +reg_write( DDR_REG_BASE +0x50a66*4 +0x02000000,0x8861); +reg_write( DDR_REG_BASE +0x50a67*4 +0x02000000,0xd880); +reg_write( DDR_REG_BASE +0x50a68*4 +0x02000000,0x7862); +reg_write( DDR_REG_BASE +0x50a69*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x50a6a*4 +0x02000000,0x782d); +reg_write( DDR_REG_BASE +0x50a6b*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x50a6c*4 +0x02000000,0x7b2f); +reg_write( DDR_REG_BASE +0x50a6d*4 +0x02000000,0xca03); +reg_write( DDR_REG_BASE +0x50a6e*4 +0x02000000,0xb57); +reg_write( DDR_REG_BASE +0x50a6f*4 +0x02000000,0x87f4); +reg_write( DDR_REG_BASE +0x50a70*4 +0x02000000,0x5042); +reg_write( DDR_REG_BASE +0x50a71*4 +0x02000000,0x921); +reg_write( DDR_REG_BASE +0x50a72*4 +0x02000000,0x24); +reg_write( DDR_REG_BASE +0x50a73*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x50a74*4 +0x02000000,0xca02); +reg_write( DDR_REG_BASE +0x50a75*4 +0x02000000,0x819); +reg_write( DDR_REG_BASE +0x50a76*4 +0x02000000,0x64); +reg_write( DDR_REG_BASE +0x50a77*4 +0x02000000,0x43e1); +reg_write( DDR_REG_BASE +0x50a78*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x50a79*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50a7a*4 +0x02000000,0x5a); +reg_write( DDR_REG_BASE +0x50a7b*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x50a7c*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50a7d*4 +0x02000000,0xcfa); +reg_write( DDR_REG_BASE +0x50a7e*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50a7f*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x50a80*4 +0x02000000,0xddff); +reg_write( DDR_REG_BASE +0x50a81*4 +0x02000000,0x79cf); +reg_write( DDR_REG_BASE +0x50a82*4 +0x02000000,0x7baf); +reg_write( DDR_REG_BASE +0x50a83*4 +0x02000000,0xb13); +reg_write( DDR_REG_BASE +0x50a84*4 +0x02000000,0x65); +reg_write( DDR_REG_BASE +0x50a85*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50a86*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x50a87*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x50a88*4 +0x02000000,0x4912); +reg_write( DDR_REG_BASE +0x50a89*4 +0x02000000,0x4b10); +reg_write( DDR_REG_BASE +0x50a8a*4 +0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x50a8b*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x50a8c*4 +0x02000000,0x78f4); +reg_write( DDR_REG_BASE +0x50a8d*4 +0x02000000,0xa841); +reg_write( DDR_REG_BASE +0x50a8e*4 +0x02000000,0xc20a); +reg_write( DDR_REG_BASE +0x50a8f*4 +0x02000000,0xa840); +reg_write( DDR_REG_BASE +0x50a90*4 +0x02000000,0x1203); +reg_write( DDR_REG_BASE +0x50a91*4 +0x02000000,0x3082); +reg_write( DDR_REG_BASE +0x50a92*4 +0x02000000,0xc812); +reg_write( DDR_REG_BASE +0x50a93*4 +0x02000000,0x81f); +reg_write( DDR_REG_BASE +0x50a94*4 +0x02000000,0x84); +reg_write( DDR_REG_BASE +0x50a95*4 +0x02000000,0x1202); +reg_write( DDR_REG_BASE +0x50a96*4 +0x02000000,0x3082); +reg_write( DDR_REG_BASE +0x50a97*4 +0x02000000,0xa17); +reg_write( DDR_REG_BASE +0x50a98*4 +0x02000000,0x24); +reg_write( DDR_REG_BASE +0x50a99*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x50a9a*4 +0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x50a9b*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50a9c*4 +0x02000000,0x5b); +reg_write( DDR_REG_BASE +0x50a9d*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x50a9e*4 +0x02000000,0xcb6); +reg_write( DDR_REG_BASE +0x50a9f*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50aa0*4 +0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x50aa1*4 +0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x50aa2*4 +0x02000000,0xe79f); +reg_write( DDR_REG_BASE +0x50aa3*4 +0x02000000,0x6e6); +reg_write( DDR_REG_BASE +0x50aa4*4 +0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x50aa5*4 +0x02000000,0xdeff); +reg_write( DDR_REG_BASE +0x50aa6*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x50aa7*4 +0x02000000,0x228a); +reg_write( DDR_REG_BASE +0x50aa8*4 +0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x50aa9*4 +0x02000000,0xc103); +reg_write( DDR_REG_BASE +0x50aaa*4 +0x02000000,0x183f); +reg_write( DDR_REG_BASE +0x50aab*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x50aac*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x50aad*4 +0x02000000,0x7214); +reg_write( DDR_REG_BASE +0x50aae*4 +0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x50aaf*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x50ab0*4 +0x02000000,0x6c1); +reg_write( DDR_REG_BASE +0x50ab1*4 +0x02000000,0x193e); +reg_write( DDR_REG_BASE +0x50ab2*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x50ab3*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x50ab4*4 +0x02000000,0x7114); +reg_write( DDR_REG_BASE +0x50ab5*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x50ab6*4 +0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x50ab7*4 +0x02000000,0x6c1); +reg_write( DDR_REG_BASE +0x50ab8*4 +0x02000000,0x1840); +reg_write( DDR_REG_BASE +0x50ab9*4 +0x02000000,0x82); +reg_write( DDR_REG_BASE +0x50aba*4 +0x02000000,0x1203); +reg_write( DDR_REG_BASE +0x50abb*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50abc*4 +0x02000000,0xc812); +reg_write( DDR_REG_BASE +0x50abd*4 +0x02000000,0x815); +reg_write( DDR_REG_BASE +0x50abe*4 +0x02000000,0x44); +reg_write( DDR_REG_BASE +0x50abf*4 +0x02000000,0x1202); +reg_write( DDR_REG_BASE +0x50ac0*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50ac1*4 +0x02000000,0x90d); +reg_write( DDR_REG_BASE +0x50ac2*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50ac3*4 +0x02000000,0xf5e); +reg_write( DDR_REG_BASE +0x50ac4*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50ac5*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x50ac6*4 +0x02000000,0xc0ac); +reg_write( DDR_REG_BASE +0x50ac7*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50ac8*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50ac9*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50aca*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x50acb*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50acc*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50acd*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50ace*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50acf*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50ad0*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50ad1*4 +0x02000000,0x168); +reg_write( DDR_REG_BASE +0x50ad2*4 +0x02000000,0x21c2); +reg_write( DDR_REG_BASE +0x50ad3*4 +0x02000000,0x222); +reg_write( DDR_REG_BASE +0x50ad4*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50ad5*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50ad6*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50ad7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50ad8*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x50ad9*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50ada*4 +0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x50adb*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50adc*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50add*4 +0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x50ade*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50adf*4 +0x02000000,0x22); +reg_write( DDR_REG_BASE +0x50ae0*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x50ae1*4 +0x02000000,0x7de0); +reg_write( DDR_REG_BASE +0x50ae2*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50ae3*4 +0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x50ae4*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50ae5*4 +0x02000000,0x8); +reg_write( DDR_REG_BASE +0x50ae6*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50ae7*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50ae8*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x50ae9*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50aea*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x50aeb*4 +0x02000000,0x813); +reg_write( DDR_REG_BASE +0x50aec*4 +0x02000000,0x70); +reg_write( DDR_REG_BASE +0x50aed*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x50aee*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50aef*4 +0x02000000,0xf40b); +reg_write( DDR_REG_BASE +0x50af0*4 +0x02000000,0x8a40); +reg_write( DDR_REG_BASE +0x50af1*4 +0x02000000,0xd84f); +reg_write( DDR_REG_BASE +0x50af2*4 +0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x50af3*4 +0x02000000,0x8a40); +reg_write( DDR_REG_BASE +0x50af4*4 +0x02000000,0xd853); +reg_write( DDR_REG_BASE +0x50af5*4 +0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x50af6*4 +0x02000000,0x7054); +reg_write( DDR_REG_BASE +0x50af7*4 +0x02000000,0x20c0); +reg_write( DDR_REG_BASE +0x50af8*4 +0x02000000,0xce2); +reg_write( DDR_REG_BASE +0x50af9*4 +0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x50afa*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50afb*4 +0x02000000,0x20c0); +reg_write( DDR_REG_BASE +0x50afc*4 +0x02000000,0xa1); +reg_write( DDR_REG_BASE +0x50afd*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50afe*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x50aff*4 +0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x50b00*4 +0x02000000,0x7114); +reg_write( DDR_REG_BASE +0x50b01*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50b02*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50b03*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x50b04*4 +0x02000000,0xf205); +reg_write( DDR_REG_BASE +0x50b05*4 +0x02000000,0xea8c); +reg_write( DDR_REG_BASE +0x50b06*4 +0x02000000,0x8820); +reg_write( DDR_REG_BASE +0x50b07*4 +0x02000000,0xd84d); +reg_write( DDR_REG_BASE +0x50b08*4 +0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x50b09*4 +0x02000000,0x8820); +reg_write( DDR_REG_BASE +0x50b0a*4 +0x02000000,0xd84e); +reg_write( DDR_REG_BASE +0x50b0b*4 +0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x50b0c*4 +0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x50b0d*4 +0x02000000,0x20c0); +reg_write( DDR_REG_BASE +0x50b0e*4 +0x02000000,0xce2); +reg_write( DDR_REG_BASE +0x50b0f*4 +0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x50b10*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x50b11*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50b12*4 +0x02000000,0xc1e); +reg_write( DDR_REG_BASE +0x50b13*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50b14*4 +0x02000000,0xb993); +reg_write( DDR_REG_BASE +0x50b15*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50b16*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x50b17*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50b18*4 +0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x50b19*4 +0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x50b1a*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x50b1b*4 +0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x50b1c*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50b1d*4 +0x02000000,0xf00b); +reg_write( DDR_REG_BASE +0x50b1e*4 +0x02000000,0xf2e); +reg_write( DDR_REG_BASE +0x50b1f*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50b20*4 +0x02000000,0x210a); +reg_write( DDR_REG_BASE +0x50b21*4 +0x02000000,0x780); +reg_write( DDR_REG_BASE +0x50b22*4 +0x02000000,0xe804); +reg_write( DDR_REG_BASE +0x50b23*4 +0x02000000,0x78af); +reg_write( DDR_REG_BASE +0x50b24*4 +0x02000000,0x200f); +reg_write( DDR_REG_BASE +0x50b25*4 +0x02000000,0x2cd); +reg_write( DDR_REG_BASE +0x50b26*4 +0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x50b27*4 +0x02000000,0xbf1); +reg_write( DDR_REG_BASE +0x50b28*4 +0x02000000,0x90b4); +reg_write( DDR_REG_BASE +0x50b29*4 +0x02000000,0x4061); +reg_write( DDR_REG_BASE +0x50b2a*4 +0x02000000,0x78af); +reg_write( DDR_REG_BASE +0x50b2b*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x50b2c*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50b2d*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50b2e*4 +0x02000000,0x674); +reg_write( DDR_REG_BASE +0x50b2f*4 +0x02000000,0x469); +reg_write( DDR_REG_BASE +0x50b30*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50b31*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50b32*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50b33*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50b34*4 +0x02000000,0x674); +reg_write( DDR_REG_BASE +0x50b35*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x50b36*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50b37*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x50b38*4 +0x02000000,0x8020); +reg_write( DDR_REG_BASE +0x50b39*4 +0x02000000,0x8a00); +reg_write( DDR_REG_BASE +0x50b3a*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x50b3b*4 +0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x50b3c*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x50b3d*4 +0x02000000,0x8a21); +reg_write( DDR_REG_BASE +0x50b3e*4 +0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x50b3f*4 +0x02000000,0x641); +reg_write( DDR_REG_BASE +0x50b40*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x50b41*4 +0x02000000,0x8842); +reg_write( DDR_REG_BASE +0x50b42*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50b43*4 +0x02000000,0x52d); +reg_write( DDR_REG_BASE +0x50b44*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50b45*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50b46*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50b47*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50b48*4 +0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x50b49*4 +0x02000000,0x817); +reg_write( DDR_REG_BASE +0x50b4a*4 +0x02000000,0xae); +reg_write( DDR_REG_BASE +0x50b4b*4 +0x02000000,0x796f); +reg_write( DDR_REG_BASE +0x50b4c*4 +0x02000000,0xea03); +reg_write( DDR_REG_BASE +0x50b4d*4 +0x02000000,0x6b21); +reg_write( DDR_REG_BASE +0x50b4e*4 +0x02000000,0x792f); +reg_write( DDR_REG_BASE +0x50b4f*4 +0x02000000,0xa0b); +reg_write( DDR_REG_BASE +0x50b50*4 +0x02000000,0xf4); +reg_write( DDR_REG_BASE +0x50b51*4 +0x02000000,0x6961); +reg_write( DDR_REG_BASE +0x50b52*4 +0x02000000,0x6963); +reg_write( DDR_REG_BASE +0x50b53*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x50b54*4 +0x02000000,0xaeb); +reg_write( DDR_REG_BASE +0x50b55*4 +0x02000000,0x8194); +reg_write( DDR_REG_BASE +0x50b56*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50b57*4 +0x02000000,0x786f); +reg_write( DDR_REG_BASE +0x50b58*4 +0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x50b59*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50b5a*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50b5b*4 +0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x50b5c*4 +0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x50b5d*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50b5e*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50b5f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50b60*4 +0x02000000,0x14); +reg_write( DDR_REG_BASE +0x50b61*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x50b62*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50b63*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50b64*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50b65*4 +0x02000000,0x15); +reg_write( DDR_REG_BASE +0x50b66*4 +0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x50b67*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50b68*4 +0x02000000,0x1a12); +reg_write( DDR_REG_BASE +0x50b69*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x50b6a*4 +0x02000000,0x256f); +reg_write( DDR_REG_BASE +0x50b6b*4 +0x02000000,0x1bc3); +reg_write( DDR_REG_BASE +0x50b6c*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50b6d*4 +0x02000000,0x8dc0); +reg_write( DDR_REG_BASE +0x50b6e*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50b6f*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50b70*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50b71*4 +0x02000000,0x1a03); +reg_write( DDR_REG_BASE +0x50b72*4 +0x02000000,0x3382); +reg_write( DDR_REG_BASE +0x50b73*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50b74*4 +0x02000000,0x15f7); +reg_write( DDR_REG_BASE +0x50b75*4 +0x02000000,0x908c); +reg_write( DDR_REG_BASE +0x50b76*4 +0x02000000,0x1a0b); +reg_write( DDR_REG_BASE +0x50b77*4 +0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x50b78*4 +0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x50b79*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50b7a*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50b7b*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50b7c*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50b7d*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50b7e*4 +0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x50b7f*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50b80*4 +0x02000000,0x2053); +reg_write( DDR_REG_BASE +0x50b81*4 +0x02000000,0x8141); +reg_write( DDR_REG_BASE +0x50b82*4 +0x02000000,0x776c); +reg_write( DDR_REG_BASE +0x50b83*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x50b84*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x50b85*4 +0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x50b86*4 +0x02000000,0x2484); +reg_write( DDR_REG_BASE +0x50b87*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x50b88*4 +0x02000000,0x1a13); +reg_write( DDR_REG_BASE +0x50b89*4 +0x02000000,0x3082); +reg_write( DDR_REG_BASE +0x50b8a*4 +0x02000000,0x1a12); +reg_write( DDR_REG_BASE +0x50b8b*4 +0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x50b8c*4 +0x02000000,0x1a0f); +reg_write( DDR_REG_BASE +0x50b8d*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x50b8e*4 +0x02000000,0x1a14); +reg_write( DDR_REG_BASE +0x50b8f*4 +0x02000000,0x3302); +reg_write( DDR_REG_BASE +0x50b90*4 +0x02000000,0xe902); +reg_write( DDR_REG_BASE +0x50b91*4 +0x02000000,0xea04); +reg_write( DDR_REG_BASE +0x50b92*4 +0x02000000,0x1a12); +reg_write( DDR_REG_BASE +0x50b93*4 +0x02000000,0x3503); +reg_write( DDR_REG_BASE +0x50b94*4 +0x02000000,0xe0d); +reg_write( DDR_REG_BASE +0x50b95*4 +0x02000000,0x1435); +reg_write( DDR_REG_BASE +0x50b96*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50b97*4 +0x02000000,0x1a03); +reg_write( DDR_REG_BASE +0x50b98*4 +0x02000000,0x3fc3); +reg_write( DDR_REG_BASE +0x50b99*4 +0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x50b9a*4 +0x02000000,0x79dd); +reg_write( DDR_REG_BASE +0x50b9b*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50b9c*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50b9d*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50b9e*4 +0x02000000,0x6909); +reg_write( DDR_REG_BASE +0x50b9f*4 +0x02000000,0xbec3); +reg_write( DDR_REG_BASE +0x50ba0*4 +0x02000000,0x1a02); +reg_write( DDR_REG_BASE +0x50ba1*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x50ba2*4 +0x02000000,0x61d8); +reg_write( DDR_REG_BASE +0x50ba3*4 +0x02000000,0x1a03); +reg_write( DDR_REG_BASE +0x50ba4*4 +0x02000000,0x3382); +reg_write( DDR_REG_BASE +0x50ba5*4 +0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x50ba6*4 +0x02000000,0x1a02); +reg_write( DDR_REG_BASE +0x50ba7*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x50ba8*4 +0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x50ba9*4 +0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x50baa*4 +0x02000000,0x8840); +reg_write( DDR_REG_BASE +0x50bab*4 +0x02000000,0x1a14); +reg_write( DDR_REG_BASE +0x50bac*4 +0x02000000,0x3098); +reg_write( DDR_REG_BASE +0x50bad*4 +0x02000000,0x8861); +reg_write( DDR_REG_BASE +0x50bae*4 +0x02000000,0x1a18); +reg_write( DDR_REG_BASE +0x50baf*4 +0x02000000,0x30d8); +reg_write( DDR_REG_BASE +0x50bb0*4 +0x02000000,0xec14); +reg_write( DDR_REG_BASE +0x50bb1*4 +0x02000000,0xb1d); +reg_write( DDR_REG_BASE +0x50bb2*4 +0x02000000,0x3010); +reg_write( DDR_REG_BASE +0x50bb3*4 +0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x50bb4*4 +0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x50bb5*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x50bb6*4 +0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x50bb7*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x50bb8*4 +0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x50bb9*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x50bba*4 +0x02000000,0x1a18); +reg_write( DDR_REG_BASE +0x50bbb*4 +0x02000000,0x30d8); +reg_write( DDR_REG_BASE +0x50bbc*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x50bbd*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x50bbe*4 +0x02000000,0xbbc3); +reg_write( DDR_REG_BASE +0x50bbf*4 +0x02000000,0xbac3); +reg_write( DDR_REG_BASE +0x50bc0*4 +0x02000000,0x1a18); +reg_write( DDR_REG_BASE +0x50bc1*4 +0x02000000,0x30d8); +reg_write( DDR_REG_BASE +0x50bc2*4 +0x02000000,0x1a14); +reg_write( DDR_REG_BASE +0x50bc3*4 +0x02000000,0x3098); +reg_write( DDR_REG_BASE +0x50bc4*4 +0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x50bc5*4 +0x02000000,0xf43); +reg_write( DDR_REG_BASE +0x50bc6*4 +0x02000000,0x68c9); +reg_write( DDR_REG_BASE +0x50bc7*4 +0x02000000,0x7077); +reg_write( DDR_REG_BASE +0x50bc8*4 +0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x50bc9*4 +0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x50bca*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50bcb*4 +0x02000000,0x8900); +reg_write( DDR_REG_BASE +0x50bcc*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50bcd*4 +0x02000000,0xb8c1); +reg_write( DDR_REG_BASE +0x50bce*4 +0x02000000,0x1a15); +reg_write( DDR_REG_BASE +0x50bcf*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x50bd0*4 +0x02000000,0x8900); +reg_write( DDR_REG_BASE +0x50bd1*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50bd2*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50bd3*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50bd4*4 +0x02000000,0xb8c1); +reg_write( DDR_REG_BASE +0x50bd5*4 +0x02000000,0x1a0c); +reg_write( DDR_REG_BASE +0x50bd6*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x50bd7*4 +0x02000000,0x15f7); +reg_write( DDR_REG_BASE +0x50bd8*4 +0x02000000,0x9081); +reg_write( DDR_REG_BASE +0x50bd9*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x50bda*4 +0x02000000,0xb9c3); +reg_write( DDR_REG_BASE +0x50bdb*4 +0x02000000,0xb9c4); +reg_write( DDR_REG_BASE +0x50bdc*4 +0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x50bdd*4 +0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x50bde*4 +0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x50bdf*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x50be0*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x50be1*4 +0x02000000,0x5053); +reg_write( DDR_REG_BASE +0x50be2*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50be3*4 +0x02000000,0x2b); +reg_write( DDR_REG_BASE +0x50be4*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x50be5*4 +0x02000000,0xa2a); +reg_write( DDR_REG_BASE +0x50be6*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50be7*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x50be8*4 +0x02000000,0x7077); +reg_write( DDR_REG_BASE +0x50be9*4 +0x02000000,0xd87f); +reg_write( DDR_REG_BASE +0x50bea*4 +0x02000000,0xdd50); +reg_write( DDR_REG_BASE +0x50beb*4 +0x02000000,0x751c); +reg_write( DDR_REG_BASE +0x50bec*4 +0x02000000,0xc814); +reg_write( DDR_REG_BASE +0x50bed*4 +0x02000000,0x1a65); +reg_write( DDR_REG_BASE +0x50bee*4 +0x02000000,0x3342); +reg_write( DDR_REG_BASE +0x50bef*4 +0x02000000,0x1a64); +reg_write( DDR_REG_BASE +0x50bf0*4 +0x02000000,0x3003); +reg_write( DDR_REG_BASE +0x50bf1*4 +0x02000000,0x5055); +reg_write( DDR_REG_BASE +0x50bf2*4 +0x02000000,0xc818); +reg_write( DDR_REG_BASE +0x50bf3*4 +0x02000000,0x7077); +reg_write( DDR_REG_BASE +0x50bf4*4 +0x02000000,0x5056); +reg_write( DDR_REG_BASE +0x50bf5*4 +0x02000000,0x16fd); +reg_write( DDR_REG_BASE +0x50bf6*4 +0x02000000,0x9080); +reg_write( DDR_REG_BASE +0x50bf7*4 +0x02000000,0x791b); +reg_write( DDR_REG_BASE +0x50bf8*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50bf9*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50bfa*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50bfb*4 +0x02000000,0x703c); +reg_write( DDR_REG_BASE +0x50bfc*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x50bfd*4 +0x02000000,0x879e); +reg_write( DDR_REG_BASE +0x50bfe*4 +0x02000000,0xf253); +reg_write( DDR_REG_BASE +0x50bff*4 +0x02000000,0xb61); +reg_write( DDR_REG_BASE +0x50c00*4 +0x02000000,0x3030); +reg_write( DDR_REG_BASE +0x50c01*4 +0x02000000,0x269f); +reg_write( DDR_REG_BASE +0x50c02*4 +0x02000000,0x3a0f); +reg_write( DDR_REG_BASE +0x50c03*4 +0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x50c04*4 +0x02000000,0x243); +reg_write( DDR_REG_BASE +0x50c05*4 +0x02000000,0x8820); +reg_write( DDR_REG_BASE +0x50c06*4 +0x02000000,0x8808); +reg_write( DDR_REG_BASE +0x50c07*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50c08*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50c09*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50c0a*4 +0x02000000,0x86a0); +reg_write( DDR_REG_BASE +0x50c0b*4 +0x02000000,0x7b1d); +reg_write( DDR_REG_BASE +0x50c0c*4 +0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x50c0d*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50c0e*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50c0f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50c10*4 +0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x50c11*4 +0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x50c12*4 +0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x50c13*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x50c14*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50c15*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50c16*4 +0x02000000,0x86); +reg_write( DDR_REG_BASE +0x50c17*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x50c18*4 +0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x50c19*4 +0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x50c1a*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x50c1b*4 +0x02000000,0x82); +reg_write( DDR_REG_BASE +0x50c1c*4 +0x02000000,0xc80c); +reg_write( DDR_REG_BASE +0x50c1d*4 +0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x50c1e*4 +0x02000000,0x6050); +reg_write( DDR_REG_BASE +0x50c1f*4 +0x02000000,0x4b10); +reg_write( DDR_REG_BASE +0x50c20*4 +0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x50c21*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50c22*4 +0x02000000,0xc806); +reg_write( DDR_REG_BASE +0x50c23*4 +0x02000000,0x6052); +reg_write( DDR_REG_BASE +0x50c24*4 +0x02000000,0x2905); +reg_write( DDR_REG_BASE +0x50c25*4 +0x02000000,0x81); +reg_write( DDR_REG_BASE +0x50c26*4 +0x02000000,0x2e05); +reg_write( DDR_REG_BASE +0x50c27*4 +0x02000000,0x309e); +reg_write( DDR_REG_BASE +0x50c28*4 +0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x50c29*4 +0x02000000,0xe0ff); +reg_write( DDR_REG_BASE +0x50c2a*4 +0x02000000,0xd87f); +reg_write( DDR_REG_BASE +0x50c2b*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x50c2c*4 +0x02000000,0x45); +reg_write( DDR_REG_BASE +0x50c2d*4 +0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x50c2e*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50c2f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50c30*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x50c31*4 +0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x50c32*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x50c33*4 +0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x50c34*4 +0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x50c35*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50c36*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50c37*4 +0x02000000,0x686); +reg_write( DDR_REG_BASE +0x50c38*4 +0x02000000,0xa9e); +reg_write( DDR_REG_BASE +0x50c39*4 +0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x50c3a*4 +0x02000000,0x2e85); +reg_write( DDR_REG_BASE +0x50c3b*4 +0x02000000,0x3406); +reg_write( DDR_REG_BASE +0x50c3c*4 +0x02000000,0x7a0f); +reg_write( DDR_REG_BASE +0x50c3d*4 +0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x50c3e*4 +0x02000000,0x3040); +reg_write( DDR_REG_BASE +0x50c3f*4 +0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x50c40*4 +0x02000000,0x6158); +reg_write( DDR_REG_BASE +0x50c41*4 +0x02000000,0x2509); +reg_write( DDR_REG_BASE +0x50c42*4 +0x02000000,0x1003); +reg_write( DDR_REG_BASE +0x50c43*4 +0x02000000,0x4a30); +reg_write( DDR_REG_BASE +0x50c44*4 +0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x50c45*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50c46*4 +0x02000000,0x1a65); +reg_write( DDR_REG_BASE +0x50c47*4 +0x02000000,0x30c2); +reg_write( DDR_REG_BASE +0x50c48*4 +0x02000000,0x1a64); +reg_write( DDR_REG_BASE +0x50c49*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x50c4a*4 +0x02000000,0x7a0f); +reg_write( DDR_REG_BASE +0x50c4b*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50c4c*4 +0x02000000,0x29); +reg_write( DDR_REG_BASE +0x50c4d*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x50c4e*4 +0x02000000,0x956); +reg_write( DDR_REG_BASE +0x50c4f*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50c50*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x50c51*4 +0x02000000,0xaa2); +reg_write( DDR_REG_BASE +0x50c52*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x50c53*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50c54*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50c55*4 +0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x50c56*4 +0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x50c57*4 +0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x50c58*4 +0x02000000,0xc2); +reg_write( DDR_REG_BASE +0x50c59*4 +0x02000000,0x1c02); +reg_write( DDR_REG_BASE +0x50c5a*4 +0x02000000,0x1014); +reg_write( DDR_REG_BASE +0x50c5b*4 +0x02000000,0xb420); +reg_write( DDR_REG_BASE +0x50c5c*4 +0x02000000,0xb441); +reg_write( DDR_REG_BASE +0x50c5d*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50c5e*4 +0x02000000,0xb462); +reg_write( DDR_REG_BASE +0x50c5f*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50c60*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50c61*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50c62*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50c63*4 +0x02000000,0xc1ac); +reg_write( DDR_REG_BASE +0x50c64*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x50c65*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50c66*4 +0x02000000,0x686); +reg_write( DDR_REG_BASE +0x50c67*4 +0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x50c68*4 +0x02000000,0x3340); +reg_write( DDR_REG_BASE +0x50c69*4 +0x02000000,0xc344); +reg_write( DDR_REG_BASE +0x50c6a*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50c6b*4 +0x02000000,0x7083); +reg_write( DDR_REG_BASE +0x50c6c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50c6d*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50c6e*4 +0x02000000,0x2680); +reg_write( DDR_REG_BASE +0x50c6f*4 +0x02000000,0x3581); +reg_write( DDR_REG_BASE +0x50c70*4 +0x02000000,0xc24b); +reg_write( DDR_REG_BASE +0x50c71*4 +0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x50c72*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50c73*4 +0x02000000,0x200a); +reg_write( DDR_REG_BASE +0x50c74*4 +0x02000000,0x780); +reg_write( DDR_REG_BASE +0x50c75*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x50c76*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50c77*4 +0x02000000,0x1491); +reg_write( DDR_REG_BASE +0x50c78*4 +0x02000000,0xe5e); +reg_write( DDR_REG_BASE +0x50c79*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50c7a*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50c7b*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50c7c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50c7d*4 +0x02000000,0x474); +reg_write( DDR_REG_BASE +0x50c7e*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50c7f*4 +0x02000000,0x1f); +reg_write( DDR_REG_BASE +0x50c80*4 +0x02000000,0x1f); +reg_write( DDR_REG_BASE +0x50c81*4 +0x02000000,0xa109); +reg_write( DDR_REG_BASE +0x50c82*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50c83*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x50c84*4 +0x02000000,0x192c); +reg_write( DDR_REG_BASE +0x50c85*4 +0x02000000,0x401); +reg_write( DDR_REG_BASE +0x50c86*4 +0x02000000,0xb1f8); +reg_write( DDR_REG_BASE +0x50c87*4 +0x02000000,0x1928); +reg_write( DDR_REG_BASE +0x50c88*4 +0x02000000,0x3c5); +reg_write( DDR_REG_BASE +0x50c89*4 +0x02000000,0x1a0e); +reg_write( DDR_REG_BASE +0x50c8a*4 +0x02000000,0x33c2); +reg_write( DDR_REG_BASE +0x50c8b*4 +0x02000000,0x1a0d); +reg_write( DDR_REG_BASE +0x50c8c*4 +0x02000000,0x33c2); +reg_write( DDR_REG_BASE +0x50c8d*4 +0x02000000,0xe88b); +reg_write( DDR_REG_BASE +0x50c8e*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50c8f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50c90*4 +0x02000000,0xc00); +reg_write( DDR_REG_BASE +0x50c91*4 +0x02000000,0xb118); +reg_write( DDR_REG_BASE +0x50c92*4 +0x02000000,0x2040); +reg_write( DDR_REG_BASE +0x50c93*4 +0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x50c94*4 +0x02000000,0xe00f); +reg_write( DDR_REG_BASE +0x50c95*4 +0x02000000,0xb153); +reg_write( DDR_REG_BASE +0x50c96*4 +0x02000000,0xb114); +reg_write( DDR_REG_BASE +0x50c97*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x50c98*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50c99*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50c9a*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x50c9b*4 +0x02000000,0x8942); +reg_write( DDR_REG_BASE +0x50c9c*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x50c9d*4 +0x02000000,0x500); +reg_write( DDR_REG_BASE +0x50c9e*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x50c9f*4 +0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x50ca0*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x50ca1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50ca2*4 +0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x50ca3*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x50ca4*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50ca5*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50ca6*4 +0x02000000,0x1b70); +reg_write( DDR_REG_BASE +0x50ca7*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x50ca8*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x50ca9*4 +0x02000000,0xc34a); +reg_write( DDR_REG_BASE +0x50caa*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x50cab*4 +0x02000000,0x642); +reg_write( DDR_REG_BASE +0x50cac*4 +0x02000000,0x8900); +reg_write( DDR_REG_BASE +0x50cad*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x50cae*4 +0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x50caf*4 +0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x50cb0*4 +0x02000000,0x60a8); +reg_write( DDR_REG_BASE +0x50cb1*4 +0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x50cb2*4 +0x02000000,0x8905); +reg_write( DDR_REG_BASE +0x50cb3*4 +0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x50cb4*4 +0x02000000,0x8904); +reg_write( DDR_REG_BASE +0x50cb5*4 +0x02000000,0xf079); +reg_write( DDR_REG_BASE +0x50cb6*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50cb7*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50cb8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50cb9*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x50cba*4 +0x02000000,0xdeff); +reg_write( DDR_REG_BASE +0x50cbb*4 +0x02000000,0x43b9); +reg_write( DDR_REG_BASE +0x50cbc*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x50cbd*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50cbe*4 +0x02000000,0xc647); +reg_write( DDR_REG_BASE +0x50cbf*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x50cc0*4 +0x02000000,0xf069); +reg_write( DDR_REG_BASE +0x50cc1*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50cc2*4 +0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x50cc3*4 +0x02000000,0x254f); +reg_write( DDR_REG_BASE +0x50cc4*4 +0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x50cc5*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x50cc6*4 +0x02000000,0x849); +reg_write( DDR_REG_BASE +0x50cc7*4 +0x02000000,0x111); +reg_write( DDR_REG_BASE +0x50cc8*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50cc9*4 +0x02000000,0xd98c); +reg_write( DDR_REG_BASE +0x50cca*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x50ccb*4 +0x02000000,0xd8c0); +reg_write( DDR_REG_BASE +0x50ccc*4 +0x02000000,0x703c); +reg_write( DDR_REG_BASE +0x50ccd*4 +0x02000000,0xc103); +reg_write( DDR_REG_BASE +0x50cce*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50ccf*4 +0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x50cd0*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x50cd1*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x50cd2*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x50cd3*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x50cd4*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x50cd5*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x50cd6*4 +0x02000000,0x780d); +reg_write( DDR_REG_BASE +0x50cd7*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x50cd8*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50cd9*4 +0x02000000,0xf831); +reg_write( DDR_REG_BASE +0x50cda*4 +0x02000000,0x86e); +reg_write( DDR_REG_BASE +0x50cdb*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50cdc*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x50cdd*4 +0x02000000,0x7910); +reg_write( DDR_REG_BASE +0x50cde*4 +0x02000000,0xca0c); +reg_write( DDR_REG_BASE +0x50cdf*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x50ce0*4 +0x02000000,0x7c3); +reg_write( DDR_REG_BASE +0x50ce1*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x50ce2*4 +0x02000000,0xeb05); +reg_write( DDR_REG_BASE +0x50ce3*4 +0x02000000,0xbb61); +reg_write( DDR_REG_BASE +0x50ce4*4 +0x02000000,0xbff); +reg_write( DDR_REG_BASE +0x50ce5*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x50ce6*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50ce7*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x50ce8*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50ce9*4 +0x02000000,0xe80d); +reg_write( DDR_REG_BASE +0x50cea*4 +0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x50ceb*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x50cec*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x50ced*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x50cee*4 +0x02000000,0x78cd); +reg_write( DDR_REG_BASE +0x50cef*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x50cf0*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50cf1*4 +0x02000000,0xf825); +reg_write( DDR_REG_BASE +0x50cf2*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x50cf3*4 +0x02000000,0x11b); +reg_write( DDR_REG_BASE +0x50cf4*4 +0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x50cf5*4 +0x02000000,0x254f); +reg_write( DDR_REG_BASE +0x50cf6*4 +0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x50cf7*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x50cf8*4 +0x02000000,0x821); +reg_write( DDR_REG_BASE +0x50cf9*4 +0x02000000,0x111); +reg_write( DDR_REG_BASE +0x50cfa*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x50cfb*4 +0x02000000,0x813); +reg_write( DDR_REG_BASE +0x50cfc*4 +0x02000000,0x91); +reg_write( DDR_REG_BASE +0x50cfd*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50cfe*4 +0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x50cff*4 +0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x50d00*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x50d01*4 +0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x50d02*4 +0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x50d03*4 +0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x50d04*4 +0x02000000,0x906); +reg_write( DDR_REG_BASE +0x50d05*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x50d06*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x50d07*4 +0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x50d08*4 +0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x50d09*4 +0x02000000,0x841); +reg_write( DDR_REG_BASE +0x50d0a*4 +0x02000000,0x36e); +reg_write( DDR_REG_BASE +0x50d0b*4 +0x02000000,0x7aef); +reg_write( DDR_REG_BASE +0x50d0c*4 +0x02000000,0x229f); +reg_write( DDR_REG_BASE +0x50d0d*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x50d0e*4 +0x02000000,0xc105); +reg_write( DDR_REG_BASE +0x50d0f*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50d10*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50d11*4 +0x02000000,0x71a); +reg_write( DDR_REG_BASE +0x50d12*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50d13*4 +0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x50d14*4 +0x02000000,0x1802); +reg_write( DDR_REG_BASE +0x50d15*4 +0x02000000,0x6c2); +reg_write( DDR_REG_BASE +0x50d16*4 +0x02000000,0xa820); +reg_write( DDR_REG_BASE +0x50d17*4 +0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x50d18*4 +0x02000000,0x2100); +reg_write( DDR_REG_BASE +0x50d19*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50d1a*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50d1b*4 +0x02000000,0x6dd); +reg_write( DDR_REG_BASE +0x50d1c*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x50d1d*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x50d1e*4 +0x02000000,0x2100); +reg_write( DDR_REG_BASE +0x50d1f*4 +0x02000000,0x781); +reg_write( DDR_REG_BASE +0x50d20*4 +0x02000000,0xd87f); +reg_write( DDR_REG_BASE +0x50d21*4 +0x02000000,0xa900); +reg_write( DDR_REG_BASE +0x50d22*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x50d23*4 +0x02000000,0xbed); +reg_write( DDR_REG_BASE +0x50d24*4 +0x02000000,0x87f4); +reg_write( DDR_REG_BASE +0x50d25*4 +0x02000000,0x2214); +reg_write( DDR_REG_BASE +0x50d26*4 +0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x50d27*4 +0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x50d28*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x50d29*4 +0x02000000,0xd33); +reg_write( DDR_REG_BASE +0x50d2a*4 +0x02000000,0x9254); +reg_write( DDR_REG_BASE +0x50d2b*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x50d2c*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x50d2d*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x50d2e*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x50d2f*4 +0x02000000,0xc108); +reg_write( DDR_REG_BASE +0x50d30*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x50d31*4 +0x02000000,0x7030); +reg_write( DDR_REG_BASE +0x50d32*4 +0x02000000,0x708); +reg_write( DDR_REG_BASE +0x50d33*4 +0x02000000,0xffee); +reg_write( DDR_REG_BASE +0x50d34*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50d35*4 +0x02000000,0xc0ac); +reg_write( DDR_REG_BASE +0x50d36*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50d37*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50d38*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50d39*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50d3a*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50d3b*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x50d3c*4 +0x02000000,0xb891); +reg_write( DDR_REG_BASE +0x50d3d*4 +0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x50d3e*4 +0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x50d3f*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50d40*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50d41*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50d42*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50d43*4 +0x02000000,0xc1a3); +reg_write( DDR_REG_BASE +0x50d44*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50d45*4 +0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x50d46*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50d47*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x50d48*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x50d49*4 +0x02000000,0xafd); +reg_write( DDR_REG_BASE +0x50d4a*4 +0x02000000,0x8674); +reg_write( DDR_REG_BASE +0x50d4b*4 +0x02000000,0x2014); +reg_write( DDR_REG_BASE +0x50d4c*4 +0x02000000,0x81); +reg_write( DDR_REG_BASE +0x50d4d*4 +0x02000000,0xdb32); +reg_write( DDR_REG_BASE +0x50d4e*4 +0x02000000,0xbb9f); +reg_write( DDR_REG_BASE +0x50d4f*4 +0x02000000,0x8b20); +reg_write( DDR_REG_BASE +0x50d50*4 +0x02000000,0xa821); +reg_write( DDR_REG_BASE +0x50d51*4 +0x02000000,0x6b21); +reg_write( DDR_REG_BASE +0x50d52*4 +0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x50d53*4 +0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x50d54*4 +0x02000000,0xa822); +reg_write( DDR_REG_BASE +0x50d55*4 +0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x50d56*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x50d57*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x50d58*4 +0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x50d59*4 +0x02000000,0xa823); +reg_write( DDR_REG_BASE +0x50d5a*4 +0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x50d5b*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x50d5c*4 +0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x50d5d*4 +0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x50d5e*4 +0x02000000,0xa824); +reg_write( DDR_REG_BASE +0x50d5f*4 +0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x50d60*4 +0x02000000,0x6941); +reg_write( DDR_REG_BASE +0x50d61*4 +0x02000000,0x8a20); +reg_write( DDR_REG_BASE +0x50d62*4 +0x02000000,0x2240); +reg_write( DDR_REG_BASE +0x50d63*4 +0x02000000,0x5f); +reg_write( DDR_REG_BASE +0x50d64*4 +0x02000000,0x2740); +reg_write( DDR_REG_BASE +0x50d65*4 +0x02000000,0x304c); +reg_write( DDR_REG_BASE +0x50d66*4 +0x02000000,0xa82b); +reg_write( DDR_REG_BASE +0x50d67*4 +0x02000000,0x1700); +reg_write( DDR_REG_BASE +0x50d68*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50d69*4 +0x02000000,0x6ca1); +reg_write( DDR_REG_BASE +0x50d6a*4 +0x02000000,0x6dc1); +reg_write( DDR_REG_BASE +0x50d6b*4 +0x02000000,0xa82c); +reg_write( DDR_REG_BASE +0x50d6c*4 +0x02000000,0x8c20); +reg_write( DDR_REG_BASE +0x50d6d*4 +0x02000000,0x6ee1); +reg_write( DDR_REG_BASE +0x50d6e*4 +0x02000000,0x4358); +reg_write( DDR_REG_BASE +0x50d6f*4 +0x02000000,0xa82d); +reg_write( DDR_REG_BASE +0x50d70*4 +0x02000000,0x8d20); +reg_write( DDR_REG_BASE +0x50d71*4 +0x02000000,0xa82e); +reg_write( DDR_REG_BASE +0x50d72*4 +0x02000000,0x8e20); +reg_write( DDR_REG_BASE +0x50d73*4 +0x02000000,0xa830); +reg_write( DDR_REG_BASE +0x50d74*4 +0x02000000,0x8f20); +reg_write( DDR_REG_BASE +0x50d75*4 +0x02000000,0xa831); +reg_write( DDR_REG_BASE +0x50d76*4 +0x02000000,0x8f21); +reg_write( DDR_REG_BASE +0x50d77*4 +0x02000000,0xa836); +reg_write( DDR_REG_BASE +0x50d78*4 +0x02000000,0x8f22); +reg_write( DDR_REG_BASE +0x50d79*4 +0x02000000,0xa838); +reg_write( DDR_REG_BASE +0x50d7a*4 +0x02000000,0x13e6); +reg_write( DDR_REG_BASE +0x50d7b*4 +0x02000000,0x8081); +reg_write( DDR_REG_BASE +0x50d7c*4 +0x02000000,0xe930); +reg_write( DDR_REG_BASE +0x50d7d*4 +0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x50d7e*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x50d7f*4 +0x02000000,0xf02a); +reg_write( DDR_REG_BASE +0x50d80*4 +0x02000000,0x265a); +reg_write( DDR_REG_BASE +0x50d81*4 +0x02000000,0x3c82); +reg_write( DDR_REG_BASE +0x50d82*4 +0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x50d83*4 +0x02000000,0x1641); +reg_write( DDR_REG_BASE +0x50d84*4 +0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x50d85*4 +0x02000000,0x621a); +reg_write( DDR_REG_BASE +0x50d86*4 +0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x50d87*4 +0x02000000,0x8b40); +reg_write( DDR_REG_BASE +0x50d88*4 +0x02000000,0xa941); +reg_write( DDR_REG_BASE +0x50d89*4 +0x02000000,0xc200); +reg_write( DDR_REG_BASE +0x50d8a*4 +0x02000000,0x8a40); +reg_write( DDR_REG_BASE +0x50d8b*4 +0x02000000,0xa942); +reg_write( DDR_REG_BASE +0x50d8c*4 +0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x50d8d*4 +0x02000000,0x8a40); +reg_write( DDR_REG_BASE +0x50d8e*4 +0x02000000,0xa943); +reg_write( DDR_REG_BASE +0x50d8f*4 +0x02000000,0xc202); +reg_write( DDR_REG_BASE +0x50d90*4 +0x02000000,0x8a40); +reg_write( DDR_REG_BASE +0x50d91*4 +0x02000000,0xa944); +reg_write( DDR_REG_BASE +0x50d92*4 +0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x50d93*4 +0x02000000,0x3082); +reg_write( DDR_REG_BASE +0x50d94*4 +0x02000000,0xa94b); +reg_write( DDR_REG_BASE +0x50d95*4 +0x02000000,0x1700); +reg_write( DDR_REG_BASE +0x50d96*4 +0x02000000,0x3082); +reg_write( DDR_REG_BASE +0x50d97*4 +0x02000000,0xa94c); +reg_write( DDR_REG_BASE +0x50d98*4 +0x02000000,0x8c40); +reg_write( DDR_REG_BASE +0x50d99*4 +0x02000000,0xa94d); +reg_write( DDR_REG_BASE +0x50d9a*4 +0x02000000,0x8d40); +reg_write( DDR_REG_BASE +0x50d9b*4 +0x02000000,0xa94e); +reg_write( DDR_REG_BASE +0x50d9c*4 +0x02000000,0x8e40); +reg_write( DDR_REG_BASE +0x50d9d*4 +0x02000000,0xa950); +reg_write( DDR_REG_BASE +0x50d9e*4 +0x02000000,0x8f40); +reg_write( DDR_REG_BASE +0x50d9f*4 +0x02000000,0xa951); +reg_write( DDR_REG_BASE +0x50da0*4 +0x02000000,0x8f41); +reg_write( DDR_REG_BASE +0x50da1*4 +0x02000000,0xa956); +reg_write( DDR_REG_BASE +0x50da2*4 +0x02000000,0x8f42); +reg_write( DDR_REG_BASE +0x50da3*4 +0x02000000,0xa958); +reg_write( DDR_REG_BASE +0x50da4*4 +0x02000000,0xbb9); +reg_write( DDR_REG_BASE +0x50da5*4 +0x02000000,0x9094); +reg_write( DDR_REG_BASE +0x50da6*4 +0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x50da7*4 +0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x50da8*4 +0x02000000,0xef9); +reg_write( DDR_REG_BASE +0x50da9*4 +0x02000000,0xb0b4); +reg_write( DDR_REG_BASE +0x50daa*4 +0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x50dab*4 +0x02000000,0xf08d); +reg_write( DDR_REG_BASE +0x50dac*4 +0x02000000,0xda3e); +reg_write( DDR_REG_BASE +0x50dad*4 +0x02000000,0xba9f); +reg_write( DDR_REG_BASE +0x50dae*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50daf*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50db0*4 +0x02000000,0xa83a); +reg_write( DDR_REG_BASE +0x50db1*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50db2*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50db3*4 +0x02000000,0xa83b); +reg_write( DDR_REG_BASE +0x50db4*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50db5*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50db6*4 +0x02000000,0xa83c); +reg_write( DDR_REG_BASE +0x50db7*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50db8*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50db9*4 +0x02000000,0xa83d); +reg_write( DDR_REG_BASE +0x50dba*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50dbb*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50dbc*4 +0x02000000,0x1824); +reg_write( DDR_REG_BASE +0x50dbd*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50dbe*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50dbf*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50dc0*4 +0x02000000,0x1825); +reg_write( DDR_REG_BASE +0x50dc1*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50dc2*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50dc3*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50dc4*4 +0x02000000,0x1826); +reg_write( DDR_REG_BASE +0x50dc5*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50dc6*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50dc7*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50dc8*4 +0x02000000,0x1827); +reg_write( DDR_REG_BASE +0x50dc9*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50dca*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50dcb*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50dcc*4 +0x02000000,0x1829); +reg_write( DDR_REG_BASE +0x50dcd*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50dce*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50dcf*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50dd0*4 +0x02000000,0x182a); +reg_write( DDR_REG_BASE +0x50dd1*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50dd2*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50dd3*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50dd4*4 +0x02000000,0x182f); +reg_write( DDR_REG_BASE +0x50dd5*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50dd6*4 +0x02000000,0x121c); +reg_write( DDR_REG_BASE +0x50dd7*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50dd8*4 +0x02000000,0x1831); +reg_write( DDR_REG_BASE +0x50dd9*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50dda*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50ddb*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50ddc*4 +0x02000000,0x1833); +reg_write( DDR_REG_BASE +0x50ddd*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50dde*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50ddf*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50de0*4 +0x02000000,0x1834); +reg_write( DDR_REG_BASE +0x50de1*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50de2*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50de3*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50de4*4 +0x02000000,0x1835); +reg_write( DDR_REG_BASE +0x50de5*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50de6*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50de7*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50de8*4 +0x02000000,0x1836); +reg_write( DDR_REG_BASE +0x50de9*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50dea*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50deb*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50dec*4 +0x02000000,0x183d); +reg_write( DDR_REG_BASE +0x50ded*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50dee*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50def*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50df0*4 +0x02000000,0x183e); +reg_write( DDR_REG_BASE +0x50df1*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50df2*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50df3*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50df4*4 +0x02000000,0x183f); +reg_write( DDR_REG_BASE +0x50df5*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50df6*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50df7*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50df8*4 +0x02000000,0x1840); +reg_write( DDR_REG_BASE +0x50df9*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50dfa*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50dfb*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50dfc*4 +0x02000000,0x1842); +reg_write( DDR_REG_BASE +0x50dfd*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50dfe*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50dff*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50e00*4 +0x02000000,0x1843); +reg_write( DDR_REG_BASE +0x50e01*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50e02*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50e03*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50e04*4 +0x02000000,0x1848); +reg_write( DDR_REG_BASE +0x50e05*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50e06*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50e07*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50e08*4 +0x02000000,0x184a); +reg_write( DDR_REG_BASE +0x50e09*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50e0a*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50e0b*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50e0c*4 +0x02000000,0x184c); +reg_write( DDR_REG_BASE +0x50e0d*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50e0e*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50e0f*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50e10*4 +0x02000000,0x184d); +reg_write( DDR_REG_BASE +0x50e11*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50e12*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50e13*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50e14*4 +0x02000000,0x184e); +reg_write( DDR_REG_BASE +0x50e15*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50e16*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50e17*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50e18*4 +0x02000000,0x184f); +reg_write( DDR_REG_BASE +0x50e19*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50e1a*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50e1b*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50e1c*4 +0x02000000,0x1856); +reg_write( DDR_REG_BASE +0x50e1d*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50e1e*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50e1f*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50e20*4 +0x02000000,0x1857); +reg_write( DDR_REG_BASE +0x50e21*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50e22*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50e23*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50e24*4 +0x02000000,0x1858); +reg_write( DDR_REG_BASE +0x50e25*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50e26*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50e27*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50e28*4 +0x02000000,0x1859); +reg_write( DDR_REG_BASE +0x50e29*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50e2a*4 +0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50e2b*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50e2c*4 +0x02000000,0x185b); +reg_write( DDR_REG_BASE +0x50e2d*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50e2e*4 +0x02000000,0x8a20); +reg_write( DDR_REG_BASE +0x50e2f*4 +0x02000000,0x185c); +reg_write( DDR_REG_BASE +0x50e30*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50e31*4 +0x02000000,0x8a21); +reg_write( DDR_REG_BASE +0x50e32*4 +0x02000000,0x1861); +reg_write( DDR_REG_BASE +0x50e33*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50e34*4 +0x02000000,0x8a22); +reg_write( DDR_REG_BASE +0x50e35*4 +0x02000000,0x1863); +reg_write( DDR_REG_BASE +0x50e36*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50e37*4 +0x02000000,0xc0a3); +reg_write( DDR_REG_BASE +0x50e38*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50e39*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50e3a*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50e3b*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50e3c*4 +0x02000000,0xc3e4); +reg_write( DDR_REG_BASE +0x50e3d*4 +0x02000000,0xc1ab); +reg_write( DDR_REG_BASE +0x50e3e*4 +0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x50e3f*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50e40*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50e41*4 +0x02000000,0x550); +reg_write( DDR_REG_BASE +0x50e42*4 +0x02000000,0xbfe); +reg_write( DDR_REG_BASE +0x50e43*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x50e44*4 +0x02000000,0xda2a); +reg_write( DDR_REG_BASE +0x50e45*4 +0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x50e46*4 +0x02000000,0x972); +reg_write( DDR_REG_BASE +0x50e47*4 +0x02000000,0x220); +reg_write( DDR_REG_BASE +0x50e48*4 +0x02000000,0xd92a); +reg_write( DDR_REG_BASE +0x50e49*4 +0x02000000,0xdd25); +reg_write( DDR_REG_BASE +0x50e4a*4 +0x02000000,0xbd9f); +reg_write( DDR_REG_BASE +0x50e4b*4 +0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x50e4c*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50e4d*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50e4e*4 +0x02000000,0xe4); +reg_write( DDR_REG_BASE +0x50e4f*4 +0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x50e50*4 +0x02000000,0x1533); +reg_write( DDR_REG_BASE +0x50e51*4 +0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x50e52*4 +0x02000000,0xb601); +reg_write( DDR_REG_BASE +0x50e53*4 +0x02000000,0x15f4); +reg_write( DDR_REG_BASE +0x50e54*4 +0x02000000,0x9080); +reg_write( DDR_REG_BASE +0x50e55*4 +0x02000000,0xe888); +reg_write( DDR_REG_BASE +0x50e56*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50e57*4 +0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x50e58*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x50e59*4 +0x02000000,0xe154); +reg_write( DDR_REG_BASE +0x50e5a*4 +0x02000000,0x1e42); +reg_write( DDR_REG_BASE +0x50e5b*4 +0x02000000,0x905d); +reg_write( DDR_REG_BASE +0x50e5c*4 +0x02000000,0x902); +reg_write( DDR_REG_BASE +0x50e5d*4 +0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x50e5e*4 +0x02000000,0x2053); +reg_write( DDR_REG_BASE +0x50e5f*4 +0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x50e60*4 +0x02000000,0x1a01); +reg_write( DDR_REG_BASE +0x50e61*4 +0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x50e62*4 +0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x50e63*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50e64*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50e65*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50e66*4 +0x02000000,0xb9c3); +reg_write( DDR_REG_BASE +0x50e67*4 +0x02000000,0x1a04); +reg_write( DDR_REG_BASE +0x50e68*4 +0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x50e69*4 +0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x50e6a*4 +0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x50e6b*4 +0x02000000,0x901); +reg_write( DDR_REG_BASE +0x50e6c*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x50e6d*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50e6e*4 +0x02000000,0xb8c1); +reg_write( DDR_REG_BASE +0x50e6f*4 +0x02000000,0xb6e); +reg_write( DDR_REG_BASE +0x50e70*4 +0x02000000,0x160); +reg_write( DDR_REG_BASE +0x50e71*4 +0x02000000,0x1a08); +reg_write( DDR_REG_BASE +0x50e72*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x50e73*4 +0x02000000,0x81e); +reg_write( DDR_REG_BASE +0x50e74*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50e75*4 +0x02000000,0x856); +reg_write( DDR_REG_BASE +0x50e76*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x50e77*4 +0x02000000,0x164c); +reg_write( DDR_REG_BASE +0x50e78*4 +0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x50e79*4 +0x02000000,0x80d); +reg_write( DDR_REG_BASE +0x50e7a*4 +0x02000000,0x151); +reg_write( DDR_REG_BASE +0x50e7b*4 +0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x50e7c*4 +0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x50e7d*4 +0x02000000,0xb601); +reg_write( DDR_REG_BASE +0x50e7e*4 +0x02000000,0xc7c4); +reg_write( DDR_REG_BASE +0x50e7f*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50e80*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50e81*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50e82*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50e83*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50e84*4 +0x02000000,0x7101); +reg_write( DDR_REG_BASE +0x50e85*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50e86*4 +0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x50e87*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50e88*4 +0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x50e89*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50e8a*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50e8b*4 +0x02000000,0x225f); +reg_write( DDR_REG_BASE +0x50e8c*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x50e8d*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x50e8e*4 +0x02000000,0x7c3); +reg_write( DDR_REG_BASE +0x50e8f*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x50e90*4 +0x02000000,0xeb05); +reg_write( DDR_REG_BASE +0x50e91*4 +0x02000000,0xbb61); +reg_write( DDR_REG_BASE +0x50e92*4 +0x02000000,0xbff); +reg_write( DDR_REG_BASE +0x50e93*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x50e94*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50e95*4 +0x02000000,0xb8c3); +reg_write( DDR_REG_BASE +0x50e96*4 +0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x50e97*4 +0x02000000,0x190); +reg_write( DDR_REG_BASE +0x50e98*4 +0x02000000,0x877); +reg_write( DDR_REG_BASE +0x50e99*4 +0x02000000,0x71); +reg_write( DDR_REG_BASE +0x50e9a*4 +0x02000000,0xdf18); +reg_write( DDR_REG_BASE +0x50e9b*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50e9c*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50e9d*4 +0x02000000,0x116); +reg_write( DDR_REG_BASE +0x50e9e*4 +0x02000000,0x1e08); +reg_write( DDR_REG_BASE +0x50e9f*4 +0x02000000,0x1094); +reg_write( DDR_REG_BASE +0x50ea0*4 +0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x50ea1*4 +0x02000000,0x1e02); +reg_write( DDR_REG_BASE +0x50ea2*4 +0x02000000,0x1055); +reg_write( DDR_REG_BASE +0x50ea3*4 +0x02000000,0xd829); +reg_write( DDR_REG_BASE +0x50ea4*4 +0x02000000,0xb6a0); +reg_write( DDR_REG_BASE +0x50ea5*4 +0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x50ea6*4 +0x02000000,0x1205); +reg_write( DDR_REG_BASE +0x50ea7*4 +0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x50ea8*4 +0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x50ea9*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50eaa*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50eab*4 +0x02000000,0x98); +reg_write( DDR_REG_BASE +0x50eac*4 +0x02000000,0x9680); +reg_write( DDR_REG_BASE +0x50ead*4 +0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x50eae*4 +0x02000000,0x1ef2); +reg_write( DDR_REG_BASE +0x50eaf*4 +0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x50eb0*4 +0x02000000,0xef2); +reg_write( DDR_REG_BASE +0x50eb1*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50eb2*4 +0x02000000,0x1e66); +reg_write( DDR_REG_BASE +0x50eb3*4 +0x02000000,0x1044); +reg_write( DDR_REG_BASE +0x50eb4*4 +0x02000000,0xd8a9); +reg_write( DDR_REG_BASE +0x50eb5*4 +0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x50eb6*4 +0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x50eb7*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x50eb8*4 +0x02000000,0xa46); +reg_write( DDR_REG_BASE +0x50eb9*4 +0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x50eba*4 +0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x50ebb*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x50ebc*4 +0x02000000,0xa44); +reg_write( DDR_REG_BASE +0x50ebd*4 +0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x50ebe*4 +0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x50ebf*4 +0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x50ec0*4 +0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x50ec1*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50ec2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50ec3*4 +0x02000000,0x6000); +reg_write( DDR_REG_BASE +0x50ec4*4 +0x02000000,0x1e72); +reg_write( DDR_REG_BASE +0x50ec5*4 +0x02000000,0x935c); +reg_write( DDR_REG_BASE +0x50ec6*4 +0x02000000,0x1ed0); +reg_write( DDR_REG_BASE +0x50ec7*4 +0x02000000,0x9344); +reg_write( DDR_REG_BASE +0x50ec8*4 +0x02000000,0x1e72); +reg_write( DDR_REG_BASE +0x50ec9*4 +0x02000000,0x90dd); +reg_write( DDR_REG_BASE +0x50eca*4 +0x02000000,0xe66); +reg_write( DDR_REG_BASE +0x50ecb*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50ecc*4 +0x02000000,0x1ed0); +reg_write( DDR_REG_BASE +0x50ecd*4 +0x02000000,0x92c4); +reg_write( DDR_REG_BASE +0x50ece*4 +0x02000000,0x1e72); +reg_write( DDR_REG_BASE +0x50ecf*4 +0x02000000,0x935c); +reg_write( DDR_REG_BASE +0x50ed0*4 +0x02000000,0x1e72); +reg_write( DDR_REG_BASE +0x50ed1*4 +0x02000000,0x92dc); +reg_write( DDR_REG_BASE +0x50ed2*4 +0x02000000,0xf046); +reg_write( DDR_REG_BASE +0x50ed3*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x50ed4*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50ed5*4 +0x02000000,0x116); +reg_write( DDR_REG_BASE +0x50ed6*4 +0x02000000,0x1d08); +reg_write( DDR_REG_BASE +0x50ed7*4 +0x02000000,0x1094); +reg_write( DDR_REG_BASE +0x50ed8*4 +0x02000000,0x71cd); +reg_write( DDR_REG_BASE +0x50ed9*4 +0x02000000,0x1d02); +reg_write( DDR_REG_BASE +0x50eda*4 +0x02000000,0x1055); +reg_write( DDR_REG_BASE +0x50edb*4 +0x02000000,0x234a); +reg_write( DDR_REG_BASE +0x50edc*4 +0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x50edd*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50ede*4 +0x02000000,0xbf8b); +reg_write( DDR_REG_BASE +0x50edf*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50ee0*4 +0x02000000,0xf); +reg_write( DDR_REG_BASE +0x50ee1*4 +0x02000000,0x4240); +reg_write( DDR_REG_BASE +0x50ee2*4 +0x02000000,0xb5c0); +reg_write( DDR_REG_BASE +0x50ee3*4 +0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x50ee4*4 +0x02000000,0x12c4); +reg_write( DDR_REG_BASE +0x50ee5*4 +0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x50ee6*4 +0x02000000,0x3040); +reg_write( DDR_REG_BASE +0x50ee7*4 +0x02000000,0x1df2); +reg_write( DDR_REG_BASE +0x50ee8*4 +0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x50ee9*4 +0x02000000,0x1d66); +reg_write( DDR_REG_BASE +0x50eea*4 +0x02000000,0x1044); +reg_write( DDR_REG_BASE +0x50eeb*4 +0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x50eec*4 +0x02000000,0x13c4); +reg_write( DDR_REG_BASE +0x50eed*4 +0x02000000,0xe7a); +reg_write( DDR_REG_BASE +0x50eee*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50eef*4 +0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x50ef0*4 +0x02000000,0xbf70); +reg_write( DDR_REG_BASE +0x50ef1*4 +0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x50ef2*4 +0x02000000,0x6c2); +reg_write( DDR_REG_BASE +0x50ef3*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50ef4*4 +0x02000000,0xe6a); +reg_write( DDR_REG_BASE +0x50ef5*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50ef6*4 +0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x50ef7*4 +0x02000000,0x13c4); +reg_write( DDR_REG_BASE +0x50ef8*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50ef9*4 +0x02000000,0x98); +reg_write( DDR_REG_BASE +0x50efa*4 +0x02000000,0x9680); +reg_write( DDR_REG_BASE +0x50efb*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50efc*4 +0x02000000,0xe5a); +reg_write( DDR_REG_BASE +0x50efd*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50efe*4 +0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x50eff*4 +0x02000000,0x12c4); +reg_write( DDR_REG_BASE +0x50f00*4 +0x02000000,0xd888); +reg_write( DDR_REG_BASE +0x50f01*4 +0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x50f02*4 +0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x50f03*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50f04*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50f05*4 +0x02000000,0x6000); +reg_write( DDR_REG_BASE +0x50f06*4 +0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x50f07*4 +0x02000000,0x12c4); +reg_write( DDR_REG_BASE +0x50f08*4 +0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x50f09*4 +0x02000000,0x1784); +reg_write( DDR_REG_BASE +0x50f0a*4 +0x02000000,0x1d72); +reg_write( DDR_REG_BASE +0x50f0b*4 +0x02000000,0x939c); +reg_write( DDR_REG_BASE +0x50f0c*4 +0x02000000,0x1dd0); +reg_write( DDR_REG_BASE +0x50f0d*4 +0x02000000,0x9384); +reg_write( DDR_REG_BASE +0x50f0e*4 +0x02000000,0x1d72); +reg_write( DDR_REG_BASE +0x50f0f*4 +0x02000000,0x90dd); +reg_write( DDR_REG_BASE +0x50f10*4 +0x02000000,0xdda); +reg_write( DDR_REG_BASE +0x50f11*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50f12*4 +0x02000000,0x1dd0); +reg_write( DDR_REG_BASE +0x50f13*4 +0x02000000,0x9784); +reg_write( DDR_REG_BASE +0x50f14*4 +0x02000000,0x1d72); +reg_write( DDR_REG_BASE +0x50f15*4 +0x02000000,0x939c); +reg_write( DDR_REG_BASE +0x50f16*4 +0x02000000,0x1d72); +reg_write( DDR_REG_BASE +0x50f17*4 +0x02000000,0x979c); +reg_write( DDR_REG_BASE +0x50f18*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50f19*4 +0x02000000,0xe22); +reg_write( DDR_REG_BASE +0x50f1a*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50f1b*4 +0x02000000,0xd920); +reg_write( DDR_REG_BASE +0x50f1c*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x50f1d*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50f1e*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x50f1f*4 +0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x50f20*4 +0x02000000,0xdba); +reg_write( DDR_REG_BASE +0x50f21*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50f22*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50f23*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x50f24*4 +0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x50f25*4 +0x02000000,0xdb2); +reg_write( DDR_REG_BASE +0x50f26*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50f27*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50f28*4 +0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x50f29*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x50f2a*4 +0x02000000,0xda6); +reg_write( DDR_REG_BASE +0x50f2b*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50f2c*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50f2d*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x50f2e*4 +0x02000000,0x1d0a); +reg_write( DDR_REG_BASE +0x50f2f*4 +0x02000000,0x909d); +reg_write( DDR_REG_BASE +0x50f30*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50f31*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50f32*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50f33*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50f34*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50f35*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50f36*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50f37*4 +0x02000000,0xc1bd); +reg_write( DDR_REG_BASE +0x50f38*4 +0x02000000,0xd925); +reg_write( DDR_REG_BASE +0x50f39*4 +0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x50f3a*4 +0x02000000,0x8900); +reg_write( DDR_REG_BASE +0x50f3b*4 +0x02000000,0x1c3a); +reg_write( DDR_REG_BASE +0x50f3c*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x50f3d*4 +0x02000000,0x1133); +reg_write( DDR_REG_BASE +0x50f3e*4 +0x02000000,0x80); +reg_write( DDR_REG_BASE +0x50f3f*4 +0x02000000,0x1c3b); +reg_write( DDR_REG_BASE +0x50f40*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x50f41*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50f42*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50f43*4 +0x02000000,0x664); +reg_write( DDR_REG_BASE +0x50f44*4 +0x02000000,0x8827); +reg_write( DDR_REG_BASE +0x50f45*4 +0x02000000,0x88a0); +reg_write( DDR_REG_BASE +0x50f46*4 +0x02000000,0xc16e); +reg_write( DDR_REG_BASE +0x50f47*4 +0x02000000,0x8829); +reg_write( DDR_REG_BASE +0x50f48*4 +0x02000000,0x1c39); +reg_write( DDR_REG_BASE +0x50f49*4 +0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x50f4a*4 +0x02000000,0x8828); +reg_write( DDR_REG_BASE +0x50f4b*4 +0x02000000,0x1c36); +reg_write( DDR_REG_BASE +0x50f4c*4 +0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x50f4d*4 +0x02000000,0x882a); +reg_write( DDR_REG_BASE +0x50f4e*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x50f4f*4 +0x02000000,0x1c37); +reg_write( DDR_REG_BASE +0x50f50*4 +0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x50f51*4 +0x02000000,0xdb2); +reg_write( DDR_REG_BASE +0x50f52*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50f53*4 +0x02000000,0xc193); +reg_write( DDR_REG_BASE +0x50f54*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50f55*4 +0x02000000,0xc146); +reg_write( DDR_REG_BASE +0x50f56*4 +0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x50f57*4 +0x02000000,0x7a34); +reg_write( DDR_REG_BASE +0x50f58*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50f59*4 +0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x50f5a*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x50f5b*4 +0x02000000,0x9fb); +reg_write( DDR_REG_BASE +0x50f5c*4 +0x02000000,0x82b4); +reg_write( DDR_REG_BASE +0x50f5d*4 +0x02000000,0xc298); +reg_write( DDR_REG_BASE +0x50f5e*4 +0x02000000,0xd90c); +reg_write( DDR_REG_BASE +0x50f5f*4 +0x02000000,0x2905); +reg_write( DDR_REG_BASE +0x50f60*4 +0x02000000,0x341); +reg_write( DDR_REG_BASE +0x50f61*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x50f62*4 +0x02000000,0x7835); +reg_write( DDR_REG_BASE +0x50f63*4 +0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x50f64*4 +0x02000000,0x40d); +reg_write( DDR_REG_BASE +0x50f65*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50f66*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50f67*4 +0x02000000,0x3ff); +reg_write( DDR_REG_BASE +0x50f68*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50f69*4 +0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x50f6a*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x50f6b*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x50f6c*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x50f6d*4 +0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x50f6e*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x50f6f*4 +0x02000000,0xc105); +reg_write( DDR_REG_BASE +0x50f70*4 +0x02000000,0xea05); +reg_write( DDR_REG_BASE +0x50f71*4 +0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x50f72*4 +0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x50f73*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x50f74*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x50f75*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x50f76*4 +0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x50f77*4 +0x02000000,0x6c7); +reg_write( DDR_REG_BASE +0x50f78*4 +0x02000000,0xd36); +reg_write( DDR_REG_BASE +0x50f79*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50f7a*4 +0x02000000,0x792f); +reg_write( DDR_REG_BASE +0x50f7b*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50f7c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50f7d*4 +0x02000000,0x57c); +reg_write( DDR_REG_BASE +0x50f7e*4 +0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x50f7f*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x50f80*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x50f81*4 +0x02000000,0xf2f6); +reg_write( DDR_REG_BASE +0x50f82*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50f83*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50f84*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50f85*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50f86*4 +0x02000000,0xb8e3); +reg_write( DDR_REG_BASE +0x50f87*4 +0x02000000,0xf4f0); +reg_write( DDR_REG_BASE +0x50f88*4 +0x02000000,0x87a); +reg_write( DDR_REG_BASE +0x50f89*4 +0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x50f8a*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x50f8b*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50f8c*4 +0x02000000,0xf07e); +reg_write( DDR_REG_BASE +0x50f8d*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x50f8e*4 +0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x50f8f*4 +0x02000000,0x80); +reg_write( DDR_REG_BASE +0x50f90*4 +0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x50f91*4 +0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x50f92*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x50f93*4 +0x02000000,0xb882); +reg_write( DDR_REG_BASE +0x50f94*4 +0x02000000,0x815); +reg_write( DDR_REG_BASE +0x50f95*4 +0x02000000,0x131); +reg_write( DDR_REG_BASE +0x50f96*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x50f97*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50f98*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50f99*4 +0x02000000,0xa00); +reg_write( DDR_REG_BASE +0x50f9a*4 +0x02000000,0xcda); +reg_write( DDR_REG_BASE +0x50f9b*4 +0x02000000,0xff0f); +reg_write( DDR_REG_BASE +0x50f9c*4 +0x02000000,0x89e); +reg_write( DDR_REG_BASE +0x50f9d*4 +0x02000000,0x140); +reg_write( DDR_REG_BASE +0x50f9e*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x50f9f*4 +0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x50fa0*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50fa1*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x50fa2*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x50fa3*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50fa4*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x50fa5*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x50fa6*4 +0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x50fa7*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x50fa8*4 +0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x50fa9*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x50faa*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x50fab*4 +0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x50fac*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50fad*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50fae*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x50faf*4 +0x02000000,0x800); +reg_write( DDR_REG_BASE +0x50fb0*4 +0x02000000,0x2045); +reg_write( DDR_REG_BASE +0x50fb1*4 +0x02000000,0x180); +reg_write( DDR_REG_BASE +0x50fb2*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50fb3*4 +0x02000000,0xd9e); +reg_write( DDR_REG_BASE +0x50fb4*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x50fb5*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50fb6*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x50fb7*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x50fb8*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x50fb9*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x50fba*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x50fbb*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50fbc*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50fbd*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x50fbe*4 +0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x50fbf*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50fc0*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50fc1*4 +0x02000000,0x4bc); +reg_write( DDR_REG_BASE +0x50fc2*4 +0x02000000,0xb8c5); +reg_write( DDR_REG_BASE +0x50fc3*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50fc4*4 +0x02000000,0xd7a); +reg_write( DDR_REG_BASE +0x50fc5*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x50fc6*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50fc7*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x50fc8*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50fc9*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50fca*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x50fcb*4 +0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x50fcc*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x50fcd*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x50fce*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x50fcf*4 +0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x50fd0*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50fd1*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x50fd2*4 +0x02000000,0x800); +reg_write( DDR_REG_BASE +0x50fd3*4 +0x02000000,0x2045); +reg_write( DDR_REG_BASE +0x50fd4*4 +0x02000000,0x580); +reg_write( DDR_REG_BASE +0x50fd5*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50fd6*4 +0x02000000,0xd56); +reg_write( DDR_REG_BASE +0x50fd7*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x50fd8*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50fd9*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x50fda*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50fdb*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50fdc*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x50fdd*4 +0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x50fde*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x50fdf*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x50fe0*4 +0x02000000,0xb8c5); +reg_write( DDR_REG_BASE +0x50fe1*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50fe2*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50fe3*4 +0x02000000,0xd3e); +reg_write( DDR_REG_BASE +0x50fe4*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x50fe5*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x50fe6*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50fe7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50fe8*4 +0x02000000,0x2710); +reg_write( DDR_REG_BASE +0x50fe9*4 +0x02000000,0xca2); +reg_write( DDR_REG_BASE +0x50fea*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50feb*4 +0x02000000,0xd90a); +reg_write( DDR_REG_BASE +0x50fec*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50fed*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50fee*4 +0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x50fef*4 +0x02000000,0x7d0f); +reg_write( DDR_REG_BASE +0x50ff0*4 +0x02000000,0xf8dd); +reg_write( DDR_REG_BASE +0x50ff1*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x50ff2*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x50ff3*4 +0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x50ff4*4 +0x02000000,0xd1a); +reg_write( DDR_REG_BASE +0x50ff5*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x50ff6*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x50ff7*4 +0x02000000,0xf8da); +reg_write( DDR_REG_BASE +0x50ff8*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x50ff9*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x50ffa*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x50ffb*4 +0x02000000,0xd0e); +reg_write( DDR_REG_BASE +0x50ffc*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x50ffd*4 +0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x50ffe*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x50fff*4 +0x02000000,0xb863); +reg_write( DDR_REG_BASE +0x51000*4 +0x02000000,0x811); +reg_write( DDR_REG_BASE +0x51001*4 +0x02000000,0x95); +reg_write( DDR_REG_BASE +0x51002*4 +0x02000000,0xf7a); +reg_write( DDR_REG_BASE +0x51003*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x51004*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51005*4 +0x02000000,0xc9e); +reg_write( DDR_REG_BASE +0x51006*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51007*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51008*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51009*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5100a*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5100b*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5100c*4 +0x02000000,0x7514); +reg_write( DDR_REG_BASE +0x5100d*4 +0x02000000,0x702); +reg_write( DDR_REG_BASE +0x5100e*4 +0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x5100f*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x51010*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51011*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51012*4 +0x02000000,0xa00); +reg_write( DDR_REG_BASE +0x51013*4 +0x02000000,0xbea); +reg_write( DDR_REG_BASE +0x51014*4 +0x02000000,0xff0f); +reg_write( DDR_REG_BASE +0x51015*4 +0x02000000,0xfae); +reg_write( DDR_REG_BASE +0x51016*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x51017*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x51018*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51019*4 +0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x5101a*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5101b*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5101c*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5101d*4 +0x02000000,0xdb18); +reg_write( DDR_REG_BASE +0x5101e*4 +0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x5101f*4 +0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x51020*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x51021*4 +0x02000000,0xcc2); +reg_write( DDR_REG_BASE +0x51022*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51023*4 +0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x51024*4 +0x02000000,0xf06); +reg_write( DDR_REG_BASE +0x51025*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51026*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51027*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x51028*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51029*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5102a*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5102b*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x5102c*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5102d*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x5102e*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x5102f*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x51030*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51031*4 +0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x51032*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x51033*4 +0x02000000,0xc9e); +reg_write( DDR_REG_BASE +0x51034*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51035*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51036*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x51037*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51038*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51039*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5103a*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5103b*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5103c*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5103d*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x5103e*4 +0x02000000,0xc86); +reg_write( DDR_REG_BASE +0x5103f*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51040*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x51041*4 +0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x51042*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x51043*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51044*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51045*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x51046*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51047*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x51048*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x51049*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5104a*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5104b*4 +0x02000000,0xc6e); +reg_write( DDR_REG_BASE +0x5104c*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5104d*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x5104e*4 +0x02000000,0x3481); +reg_write( DDR_REG_BASE +0x5104f*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x51050*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51051*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51052*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x51053*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51054*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x51055*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51056*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x51057*4 +0x02000000,0xc56); +reg_write( DDR_REG_BASE +0x51058*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51059*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5105a*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x5105b*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5105c*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5105d*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5105e*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5105f*4 +0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x51060*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51061*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x51062*4 +0x02000000,0xc3e); +reg_write( DDR_REG_BASE +0x51063*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51064*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51065*4 +0x02000000,0xe6a); +reg_write( DDR_REG_BASE +0x51066*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51067*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51068*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x51069*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5106a*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5106b*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5106c*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5106d*4 +0x02000000,0xdb18); +reg_write( DDR_REG_BASE +0x5106e*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5106f*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x51070*4 +0x02000000,0xc22); +reg_write( DDR_REG_BASE +0x51071*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51072*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51073*4 +0x02000000,0xe9a); +reg_write( DDR_REG_BASE +0x51074*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x51075*4 +0x02000000,0xf07f); +reg_write( DDR_REG_BASE +0x51076*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51077*4 +0x02000000,0xb22); +reg_write( DDR_REG_BASE +0x51078*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51079*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x5107a*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x5107b*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x5107c*4 +0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x5107d*4 +0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x5107e*4 +0x02000000,0x101); +reg_write( DDR_REG_BASE +0x5107f*4 +0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x51080*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51081*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51082*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x51083*4 +0x02000000,0x7e0f); +reg_write( DDR_REG_BASE +0x51084*4 +0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x51085*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51086*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51087*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51088*4 +0x02000000,0xe02); +reg_write( DDR_REG_BASE +0x51089*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5108a*4 +0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x5108b*4 +0x02000000,0xd828); +reg_write( DDR_REG_BASE +0x5108c*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5108d*4 +0x02000000,0xf88c); +reg_write( DDR_REG_BASE +0x5108e*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5108f*4 +0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x51090*4 +0x02000000,0xdf2); +reg_write( DDR_REG_BASE +0x51091*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51092*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51093*4 +0x02000000,0xf889); +reg_write( DDR_REG_BASE +0x51094*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51095*4 +0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x51096*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x51097*4 +0x02000000,0x33c1); +reg_write( DDR_REG_BASE +0x51098*4 +0x02000000,0xde2); +reg_write( DDR_REG_BASE +0x51099*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5109a*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5109b*4 +0x02000000,0xf885); +reg_write( DDR_REG_BASE +0x5109c*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5109d*4 +0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x5109e*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x5109f*4 +0x02000000,0x3501); +reg_write( DDR_REG_BASE +0x510a0*4 +0x02000000,0xdd2); +reg_write( DDR_REG_BASE +0x510a1*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x510a2*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x510a3*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x510a4*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x510a5*4 +0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x510a6*4 +0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x510a7*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x510a8*4 +0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x510a9*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x510aa*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x510ab*4 +0x02000000,0xdbe); +reg_write( DDR_REG_BASE +0x510ac*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x510ad*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x510ae*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x510af*4 +0x02000000,0xb4a); +reg_write( DDR_REG_BASE +0x510b0*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x510b1*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x510b2*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x510b3*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x510b4*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x510b5*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x510b6*4 +0x02000000,0xdae0); +reg_write( DDR_REG_BASE +0x510b7*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x510b8*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x510b9*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x510ba*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x510bb*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x510bc*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x510bd*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x510be*4 +0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x510bf*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x510c0*4 +0x02000000,0x7204); +reg_write( DDR_REG_BASE +0x510c1*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x510c2*4 +0x02000000,0xb340); +reg_write( DDR_REG_BASE +0x510c3*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x510c4*4 +0x02000000,0x485); +reg_write( DDR_REG_BASE +0x510c5*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x510c6*4 +0x02000000,0xa82); +reg_write( DDR_REG_BASE +0x510c7*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x510c8*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x510c9*4 +0x02000000,0xdbe); +reg_write( DDR_REG_BASE +0x510ca*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x510cb*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x510cc*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x510cd*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x510ce*4 +0x02000000,0xb990); +reg_write( DDR_REG_BASE +0x510cf*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x510d0*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x510d1*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x510d2*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x510d3*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x510d4*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x510d5*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x510d6*4 +0x02000000,0xb56); +reg_write( DDR_REG_BASE +0x510d7*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x510d8*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x510d9*4 +0x02000000,0xd90c); +reg_write( DDR_REG_BASE +0x510da*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x510db*4 +0x02000000,0xb98d); +reg_write( DDR_REG_BASE +0x510dc*4 +0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x510dd*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x510de*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x510df*4 +0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x510e0*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x510e1*4 +0x02000000,0xb42); +reg_write( DDR_REG_BASE +0x510e2*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x510e3*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x510e4*4 +0x02000000,0xd6a); +reg_write( DDR_REG_BASE +0x510e5*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x510e6*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x510e7*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x510e8*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x510e9*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x510ea*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x510eb*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x510ec*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x510ed*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x510ee*4 +0x02000000,0xb26); +reg_write( DDR_REG_BASE +0x510ef*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x510f0*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x510f1*4 +0x02000000,0xd850); +reg_write( DDR_REG_BASE +0x510f2*4 +0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x510f3*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x510f4*4 +0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x510f5*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x510f6*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x510f7*4 +0x02000000,0xe048); +reg_write( DDR_REG_BASE +0x510f8*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x510f9*4 +0x02000000,0x1804); +reg_write( DDR_REG_BASE +0x510fa*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x510fb*4 +0x02000000,0x2440); +reg_write( DDR_REG_BASE +0x510fc*4 +0x02000000,0x3e80); +reg_write( DDR_REG_BASE +0x510fd*4 +0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x510fe*4 +0x02000000,0x6c1); +reg_write( DDR_REG_BASE +0x510ff*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x51100*4 +0x02000000,0x782b); +reg_write( DDR_REG_BASE +0x51101*4 +0x02000000,0xf264); +reg_write( DDR_REG_BASE +0x51102*4 +0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x51103*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51104*4 +0x02000000,0xa9e); +reg_write( DDR_REG_BASE +0x51105*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51106*4 +0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x51107*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51108*4 +0x02000000,0xa42); +reg_write( DDR_REG_BASE +0x51109*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5110a*4 +0x02000000,0xd91e); +reg_write( DDR_REG_BASE +0x5110b*4 +0x02000000,0x2440); +reg_write( DDR_REG_BASE +0x5110c*4 +0x02000000,0x3d80); +reg_write( DDR_REG_BASE +0x5110d*4 +0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x5110e*4 +0x02000000,0x6cb); +reg_write( DDR_REG_BASE +0x5110f*4 +0x02000000,0xc08e); +reg_write( DDR_REG_BASE +0x51110*4 +0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x51111*4 +0x02000000,0x6cd); +reg_write( DDR_REG_BASE +0x51112*4 +0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x51113*4 +0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x51114*4 +0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x51115*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51116*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51117*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x51118*4 +0x02000000,0x7a34); +reg_write( DDR_REG_BASE +0x51119*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x5111a*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5111b*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5111c*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x5111d*4 +0x02000000,0x54); +reg_write( DDR_REG_BASE +0x5111e*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x5111f*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51120*4 +0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x51121*4 +0x02000000,0xbe9); +reg_write( DDR_REG_BASE +0x51122*4 +0x02000000,0x9065); +reg_write( DDR_REG_BASE +0x51123*4 +0x02000000,0xc28f); +reg_write( DDR_REG_BASE +0x51124*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51125*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51126*4 +0x02000000,0xf034); +reg_write( DDR_REG_BASE +0x51127*4 +0x02000000,0x23f4); +reg_write( DDR_REG_BASE +0x51128*4 +0x02000000,0x34c); +reg_write( DDR_REG_BASE +0x51129*4 +0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x5112a*4 +0x02000000,0x7bb4); +reg_write( DDR_REG_BASE +0x5112b*4 +0x02000000,0xbc80); +reg_write( DDR_REG_BASE +0x5112c*4 +0x02000000,0xb380); +reg_write( DDR_REG_BASE +0x5112d*4 +0x02000000,0xe886); +reg_write( DDR_REG_BASE +0x5112e*4 +0x02000000,0xc08f); +reg_write( DDR_REG_BASE +0x5112f*4 +0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x51130*4 +0x02000000,0x340); +reg_write( DDR_REG_BASE +0x51131*4 +0x02000000,0xe80f); +reg_write( DDR_REG_BASE +0x51132*4 +0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x51133*4 +0x02000000,0x340e); +reg_write( DDR_REG_BASE +0x51134*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51135*4 +0x02000000,0x7e16); +reg_write( DDR_REG_BASE +0x51136*4 +0x02000000,0x6638); +reg_write( DDR_REG_BASE +0x51137*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x51138*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51139*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5113a*4 +0x02000000,0x644); +reg_write( DDR_REG_BASE +0x5113b*4 +0x02000000,0xa8a0); +reg_write( DDR_REG_BASE +0x5113c*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x5113d*4 +0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x5113e*4 +0x02000000,0xe817); +reg_write( DDR_REG_BASE +0x5113f*4 +0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x51140*4 +0x02000000,0x340e); +reg_write( DDR_REG_BASE +0x51141*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51142*4 +0x02000000,0x7e16); +reg_write( DDR_REG_BASE +0x51143*4 +0x02000000,0x6658); +reg_write( DDR_REG_BASE +0x51144*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x51145*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51146*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51147*4 +0x02000000,0x624); +reg_write( DDR_REG_BASE +0x51148*4 +0x02000000,0xa8a0); +reg_write( DDR_REG_BASE +0x51149*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x5114a*4 +0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x5114b*4 +0x02000000,0xe88f); +reg_write( DDR_REG_BASE +0x5114c*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5114d*4 +0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x5114e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5114f*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51150*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51151*4 +0x02000000,0x7404); +reg_write( DDR_REG_BASE +0x51152*4 +0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x51153*4 +0x02000000,0xb380); +reg_write( DDR_REG_BASE +0x51154*4 +0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x51155*4 +0x02000000,0xc08f); +reg_write( DDR_REG_BASE +0x51156*4 +0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x51157*4 +0x02000000,0x340); +reg_write( DDR_REG_BASE +0x51158*4 +0x02000000,0xe867); +reg_write( DDR_REG_BASE +0x51159*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x5115a*4 +0x02000000,0xb9b); +reg_write( DDR_REG_BASE +0x5115b*4 +0x02000000,0x9365); +reg_write( DDR_REG_BASE +0x5115c*4 +0x02000000,0xc398); +reg_write( DDR_REG_BASE +0x5115d*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5115e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5115f*4 +0x02000000,0x9c4); +reg_write( DDR_REG_BASE +0x51160*4 +0x02000000,0x9ce); +reg_write( DDR_REG_BASE +0x51161*4 +0x02000000,0xff0f); +reg_write( DDR_REG_BASE +0x51162*4 +0x02000000,0x93e); +reg_write( DDR_REG_BASE +0x51163*4 +0x02000000,0xff0f); +reg_write( DDR_REG_BASE +0x51164*4 +0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x51165*4 +0x02000000,0x7277); +reg_write( DDR_REG_BASE +0x51166*4 +0x02000000,0x408); +reg_write( DDR_REG_BASE +0x51167*4 +0x02000000,0xffc5); +reg_write( DDR_REG_BASE +0x51168*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51169*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5116a*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x5116b*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5116c*4 +0x02000000,0x7114); +reg_write( DDR_REG_BASE +0x5116d*4 +0x02000000,0x3f6); +reg_write( DDR_REG_BASE +0x5116e*4 +0x02000000,0xffce); +reg_write( DDR_REG_BASE +0x5116f*4 +0x02000000,0xf01a); +reg_write( DDR_REG_BASE +0x51170*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x51171*4 +0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x51172*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51173*4 +0x02000000,0xe913); +reg_write( DDR_REG_BASE +0x51174*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51175*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51176*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51177*4 +0x02000000,0x19); +reg_write( DDR_REG_BASE +0x51178*4 +0x02000000,0xe88d); +reg_write( DDR_REG_BASE +0x51179*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x5117a*4 +0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x5117b*4 +0x02000000,0x301); +reg_write( DDR_REG_BASE +0x5117c*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x5117d*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5117e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5117f*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x51180*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51181*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51182*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51183*4 +0x02000000,0x154); +reg_write( DDR_REG_BASE +0x51184*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51185*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x51186*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x51187*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x51188*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x51189*4 +0x02000000,0x8d1); +reg_write( DDR_REG_BASE +0x5118a*4 +0x02000000,0x82b4); +reg_write( DDR_REG_BASE +0x5118b*4 +0x02000000,0xc198); +reg_write( DDR_REG_BASE +0x5118c*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5118d*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5118e*4 +0x02000000,0x57c); +reg_write( DDR_REG_BASE +0x5118f*4 +0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x51190*4 +0x02000000,0xe808); +reg_write( DDR_REG_BASE +0x51191*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51192*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51193*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51194*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51195*4 +0x02000000,0xb8e3); +reg_write( DDR_REG_BASE +0x51196*4 +0x02000000,0xd98); +reg_write( DDR_REG_BASE +0x51197*4 +0x02000000,0xff41); +reg_write( DDR_REG_BASE +0x51198*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51199*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5119a*4 +0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x5119b*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5119c*4 +0x02000000,0xe048); +reg_write( DDR_REG_BASE +0x5119d*4 +0x02000000,0x91a); +reg_write( DDR_REG_BASE +0x5119e*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5119f*4 +0x02000000,0xc193); +reg_write( DDR_REG_BASE +0x511a0*4 +0x02000000,0xc0bd); +reg_write( DDR_REG_BASE +0x511a1*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x511a2*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x511a3*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x511a4*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x511a5*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x511a6*4 +0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x511a7*4 +0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x511a8*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x511a9*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x511aa*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x511ab*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x511ac*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x511ad*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x511ae*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x511af*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x511b0*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x511b1*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x511b2*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x511b3*4 +0x02000000,0xc1a2); +reg_write( DDR_REG_BASE +0x511b4*4 +0x02000000,0x4728); +reg_write( DDR_REG_BASE +0x511b5*4 +0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x511b6*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x511b7*4 +0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x511b8*4 +0x02000000,0xc341); +reg_write( DDR_REG_BASE +0x511b9*4 +0x02000000,0xada); +reg_write( DDR_REG_BASE +0x511ba*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x511bb*4 +0x02000000,0x4358); +reg_write( DDR_REG_BASE +0x511bc*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x511bd*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x511be*4 +0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x511bf*4 +0x02000000,0x17c0); +reg_write( DDR_REG_BASE +0x511c0*4 +0x02000000,0xe805); +reg_write( DDR_REG_BASE +0x511c1*4 +0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x511c2*4 +0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x511c3*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x511c4*4 +0x02000000,0x7dbb); +reg_write( DDR_REG_BASE +0x511c5*4 +0x02000000,0xb15); +reg_write( DDR_REG_BASE +0x511c6*4 +0x02000000,0x3031); +reg_write( DDR_REG_BASE +0x511c7*4 +0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x511c8*4 +0x02000000,0x110d); +reg_write( DDR_REG_BASE +0x511c9*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x511ca*4 +0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x511cb*4 +0x02000000,0xbd6); +reg_write( DDR_REG_BASE +0x511cc*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x511cd*4 +0x02000000,0xdabf); +reg_write( DDR_REG_BASE +0x511ce*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x511cf*4 +0x02000000,0x250f); +reg_write( DDR_REG_BASE +0x511d0*4 +0x02000000,0x139b); +reg_write( DDR_REG_BASE +0x511d1*4 +0x02000000,0xe887); +reg_write( DDR_REG_BASE +0x511d2*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x511d3*4 +0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x511d4*4 +0x02000000,0xbc2); +reg_write( DDR_REG_BASE +0x511d5*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x511d6*4 +0x02000000,0xda7f); +reg_write( DDR_REG_BASE +0x511d7*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x511d8*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x511d9*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x511da*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x511db*4 +0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x511dc*4 +0x02000000,0x164d); +reg_write( DDR_REG_BASE +0x511dd*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x511de*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x511df*4 +0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x511e0*4 +0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x511e1*4 +0x02000000,0xdff); +reg_write( DDR_REG_BASE +0x511e2*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x511e3*4 +0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x511e4*4 +0x02000000,0x60f8); +reg_write( DDR_REG_BASE +0x511e5*4 +0x02000000,0x60b9); +reg_write( DDR_REG_BASE +0x511e6*4 +0x02000000,0xcba); +reg_write( DDR_REG_BASE +0x511e7*4 +0x02000000,0x1a0); +reg_write( DDR_REG_BASE +0x511e8*4 +0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x511e9*4 +0x02000000,0x6c7); +reg_write( DDR_REG_BASE +0x511ea*4 +0x02000000,0xa86); +reg_write( DDR_REG_BASE +0x511eb*4 +0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x511ec*4 +0x02000000,0xa8e); +reg_write( DDR_REG_BASE +0x511ed*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x511ee*4 +0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x511ef*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x511f0*4 +0x02000000,0x91a); +reg_write( DDR_REG_BASE +0x511f1*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x511f2*4 +0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x511f3*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x511f4*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x511f5*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x511f6*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x511f7*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x511f8*4 +0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x511f9*4 +0x02000000,0x60f8); +reg_write( DDR_REG_BASE +0x511fa*4 +0x02000000,0x60b8); +reg_write( DDR_REG_BASE +0x511fb*4 +0x02000000,0x1003); +reg_write( DDR_REG_BASE +0x511fc*4 +0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x511fd*4 +0x02000000,0x783d); +reg_write( DDR_REG_BASE +0x511fe*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x511ff*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51200*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51201*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x51202*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x51203*4 +0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x51204*4 +0x02000000,0x20c5); +reg_write( DDR_REG_BASE +0x51205*4 +0x02000000,0x4ab); +reg_write( DDR_REG_BASE +0x51206*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51207*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x51208*4 +0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x51209*4 +0x02000000,0x22); +reg_write( DDR_REG_BASE +0x5120a*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x5120b*4 +0x02000000,0xf62); +reg_write( DDR_REG_BASE +0x5120c*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5120d*4 +0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x5120e*4 +0x02000000,0xc0a2); +reg_write( DDR_REG_BASE +0x5120f*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x51210*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x51211*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51212*4 +0x02000000,0x7a1b); +reg_write( DDR_REG_BASE +0x51213*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51214*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51215*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51216*4 +0x02000000,0x1c); +reg_write( DDR_REG_BASE +0x51217*4 +0x02000000,0xbac4); +reg_write( DDR_REG_BASE +0x51218*4 +0x02000000,0xea05); +reg_write( DDR_REG_BASE +0x51219*4 +0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x5121a*4 +0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x5121b*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x5121c*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5121d*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x5121e*4 +0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x5121f*4 +0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x51220*4 +0x02000000,0xea05); +reg_write( DDR_REG_BASE +0x51221*4 +0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x51222*4 +0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x51223*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x51224*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51225*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x51226*4 +0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x51227*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51228*4 +0x02000000,0xc0e2); +reg_write( DDR_REG_BASE +0x51229*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5122a*4 +0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x5122b*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5122c*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5122d*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x5122e*4 +0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x5122f*4 +0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x51230*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51231*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51232*4 +0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x51233*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x51234*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51235*4 +0x02000000,0x86); +reg_write( DDR_REG_BASE +0x51236*4 +0x02000000,0x9240); +reg_write( DDR_REG_BASE +0x51237*4 +0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x51238*4 +0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x51239*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5123a*4 +0x02000000,0xfe86); +reg_write( DDR_REG_BASE +0x5123b*4 +0x02000000,0x22c4); +reg_write( DDR_REG_BASE +0x5123c*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x5123d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5123e*4 +0x02000000,0xbfff); +reg_write( DDR_REG_BASE +0x5123f*4 +0x02000000,0xf203); +reg_write( DDR_REG_BASE +0x51240*4 +0x02000000,0xba8e); +reg_write( DDR_REG_BASE +0x51241*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x51242*4 +0x02000000,0xb340); +reg_write( DDR_REG_BASE +0x51243*4 +0x02000000,0xf01d); +reg_write( DDR_REG_BASE +0x51244*4 +0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x51245*4 +0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x51246*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51247*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x51248*4 +0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x51249*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x5124a*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5124b*4 +0x02000000,0x4a); +reg_write( DDR_REG_BASE +0x5124c*4 +0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x5124d*4 +0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x5124e*4 +0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x5124f*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51250*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51251*4 +0x02000000,0xe80b); +reg_write( DDR_REG_BASE +0x51252*4 +0x02000000,0x9340); +reg_write( DDR_REG_BASE +0x51253*4 +0x02000000,0x2114); +reg_write( DDR_REG_BASE +0x51254*4 +0x02000000,0x34c); +reg_write( DDR_REG_BASE +0x51255*4 +0x02000000,0xb440); +reg_write( DDR_REG_BASE +0x51256*4 +0x02000000,0x2204); +reg_write( DDR_REG_BASE +0x51257*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x51258*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51259*4 +0x02000000,0xfbff); +reg_write( DDR_REG_BASE +0x5125a*4 +0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x5125b*4 +0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x5125c*4 +0x02000000,0x342); +reg_write( DDR_REG_BASE +0x5125d*4 +0x02000000,0xb340); +reg_write( DDR_REG_BASE +0x5125e*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x5125f*4 +0x02000000,0xdcd); +reg_write( DDR_REG_BASE +0x51260*4 +0x02000000,0x9294); +reg_write( DDR_REG_BASE +0x51261*4 +0x02000000,0xc4c2); +reg_write( DDR_REG_BASE +0x51262*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51263*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x51264*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51265*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51266*4 +0x02000000,0x66b); +reg_write( DDR_REG_BASE +0x51267*4 +0x02000000,0xdd24); +reg_write( DDR_REG_BASE +0x51268*4 +0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x51269*4 +0x02000000,0xbd9f); +reg_write( DDR_REG_BASE +0x5126a*4 +0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x5126b*4 +0x02000000,0xe007); +reg_write( DDR_REG_BASE +0x5126c*4 +0x02000000,0x7a1d); +reg_write( DDR_REG_BASE +0x5126d*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x5126e*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x5126f*4 +0x02000000,0x6a09); +reg_write( DDR_REG_BASE +0x51270*4 +0x02000000,0xa901); +reg_write( DDR_REG_BASE +0x51271*4 +0x02000000,0x1534); +reg_write( DDR_REG_BASE +0x51272*4 +0x02000000,0x108c); +reg_write( DDR_REG_BASE +0x51273*4 +0x02000000,0xec0e); +reg_write( DDR_REG_BASE +0x51274*4 +0x02000000,0xca04); +reg_write( DDR_REG_BASE +0x51275*4 +0x02000000,0x7a1d); +reg_write( DDR_REG_BASE +0x51276*4 +0x02000000,0xa942); +reg_write( DDR_REG_BASE +0x51277*4 +0x02000000,0x1533); +reg_write( DDR_REG_BASE +0x51278*4 +0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x51279*4 +0x02000000,0xe007); +reg_write( DDR_REG_BASE +0x5127a*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5127b*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5127c*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5127d*4 +0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x5127e*4 +0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x5127f*4 +0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x51280*4 +0x02000000,0xa942); +reg_write( DDR_REG_BASE +0x51281*4 +0x02000000,0xa903); +reg_write( DDR_REG_BASE +0x51282*4 +0x02000000,0xf01e); +reg_write( DDR_REG_BASE +0x51283*4 +0x02000000,0xee05); +reg_write( DDR_REG_BASE +0x51284*4 +0x02000000,0x1533); +reg_write( DDR_REG_BASE +0x51285*4 +0x02000000,0x108f); +reg_write( DDR_REG_BASE +0x51286*4 +0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x51287*4 +0x02000000,0x8de0); +reg_write( DDR_REG_BASE +0x51288*4 +0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x51289*4 +0x02000000,0xf16); +reg_write( DDR_REG_BASE +0x5128a*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5128b*4 +0x02000000,0x796f); +reg_write( DDR_REG_BASE +0x5128c*4 +0x02000000,0xe804); +reg_write( DDR_REG_BASE +0x5128d*4 +0x02000000,0x6f07); +reg_write( DDR_REG_BASE +0x5128e*4 +0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x5128f*4 +0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x51290*4 +0x02000000,0x4f1f); +reg_write( DDR_REG_BASE +0x51291*4 +0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x51292*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x51293*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x51294*4 +0x02000000,0x2314); +reg_write( DDR_REG_BASE +0x51295*4 +0x02000000,0x380); +reg_write( DDR_REG_BASE +0x51296*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x51297*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x51298*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51299*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5129a*4 +0x02000000,0x620); +reg_write( DDR_REG_BASE +0x5129b*4 +0x02000000,0xa820); +reg_write( DDR_REG_BASE +0x5129c*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x5129d*4 +0x02000000,0xecf); +reg_write( DDR_REG_BASE +0x5129e*4 +0x02000000,0x9094); +reg_write( DDR_REG_BASE +0x5129f*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x512a0*4 +0x02000000,0xbfb); +reg_write( DDR_REG_BASE +0x512a1*4 +0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x512a2*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x512a3*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x512a4*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x512a5*4 +0x02000000,0xa26); +reg_write( DDR_REG_BASE +0x512a6*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x512a7*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x512a8*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x512a9*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x512aa*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x512ab*4 +0x02000000,0x7101); +reg_write( DDR_REG_BASE +0x512ac*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x512ad*4 +0x02000000,0x6); +reg_write( DDR_REG_BASE +0x512ae*4 +0x02000000,0x790c); +reg_write( DDR_REG_BASE +0x512af*4 +0x02000000,0x2985); +reg_write( DDR_REG_BASE +0x512b0*4 +0x02000000,0x41f); +reg_write( DDR_REG_BASE +0x512b1*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x512b2*4 +0x02000000,0x6901); +reg_write( DDR_REG_BASE +0x512b3*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x512b4*4 +0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x512b5*4 +0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x512b6*4 +0x02000000,0x82a); +reg_write( DDR_REG_BASE +0x512b7*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x512b8*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x512b9*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x512ba*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x512bb*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x512bc*4 +0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x512bd*4 +0x02000000,0xe907); +reg_write( DDR_REG_BASE +0x512be*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x512bf*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x512c0*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x512c1*4 +0x02000000,0x58); +reg_write( DDR_REG_BASE +0x512c2*4 +0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x512c3*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x512c4*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x512c5*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x512c6*4 +0x02000000,0x25); +reg_write( DDR_REG_BASE +0x512c7*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x512c8*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x512c9*4 +0x02000000,0xf024); +reg_write( DDR_REG_BASE +0x512ca*4 +0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x512cb*4 +0x02000000,0x7ce); +reg_write( DDR_REG_BASE +0x512cc*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x512cd*4 +0x02000000,0xee06); +reg_write( DDR_REG_BASE +0x512ce*4 +0x02000000,0xbe61); +reg_write( DDR_REG_BASE +0x512cf*4 +0x02000000,0xe01); +reg_write( DDR_REG_BASE +0x512d0*4 +0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x512d1*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x512d2*4 +0x02000000,0xb9c1); +reg_write( DDR_REG_BASE +0x512d3*4 +0x02000000,0x933); +reg_write( DDR_REG_BASE +0x512d4*4 +0x02000000,0xa1); +reg_write( DDR_REG_BASE +0x512d5*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x512d6*4 +0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x512d7*4 +0x02000000,0x7ce); +reg_write( DDR_REG_BASE +0x512d8*4 +0x02000000,0xee05); +reg_write( DDR_REG_BASE +0x512d9*4 +0x02000000,0xbe61); +reg_write( DDR_REG_BASE +0x512da*4 +0x02000000,0xeff); +reg_write( DDR_REG_BASE +0x512db*4 +0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x512dc*4 +0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x512dd*4 +0x02000000,0x79ab); +reg_write( DDR_REG_BASE +0x512de*4 +0x02000000,0xd910); +reg_write( DDR_REG_BASE +0x512df*4 +0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x512e0*4 +0x02000000,0x7ce); +reg_write( DDR_REG_BASE +0x512e1*4 +0x02000000,0x24c0); +reg_write( DDR_REG_BASE +0x512e2*4 +0x02000000,0x1062); +reg_write( DDR_REG_BASE +0x512e3*4 +0x02000000,0xee06); +reg_write( DDR_REG_BASE +0x512e4*4 +0x02000000,0xbe61); +reg_write( DDR_REG_BASE +0x512e5*4 +0x02000000,0xe01); +reg_write( DDR_REG_BASE +0x512e6*4 +0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x512e7*4 +0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x512e8*4 +0x02000000,0x79ab); +reg_write( DDR_REG_BASE +0x512e9*4 +0x02000000,0x24c0); +reg_write( DDR_REG_BASE +0x512ea*4 +0x02000000,0x1062); +reg_write( DDR_REG_BASE +0x512eb*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x512ec*4 +0x02000000,0xbbd); +reg_write( DDR_REG_BASE +0x512ed*4 +0x02000000,0x8134); +reg_write( DDR_REG_BASE +0x512ee*4 +0x02000000,0x797b); +reg_write( DDR_REG_BASE +0x512ef*4 +0x02000000,0x4081); +reg_write( DDR_REG_BASE +0x512f0*4 +0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x512f1*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x512f2*4 +0x02000000,0x2042); +reg_write( DDR_REG_BASE +0x512f3*4 +0x02000000,0x701); +reg_write( DDR_REG_BASE +0x512f4*4 +0x02000000,0x939); +reg_write( DDR_REG_BASE +0x512f5*4 +0x02000000,0x454); +reg_write( DDR_REG_BASE +0x512f6*4 +0x02000000,0x889); +reg_write( DDR_REG_BASE +0x512f7*4 +0x02000000,0xc30); +reg_write( DDR_REG_BASE +0x512f8*4 +0x02000000,0xd91a); +reg_write( DDR_REG_BASE +0x512f9*4 +0x02000000,0x885); +reg_write( DDR_REG_BASE +0x512fa*4 +0x02000000,0xd70); +reg_write( DDR_REG_BASE +0x512fb*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x512fc*4 +0x02000000,0x87d); +reg_write( DDR_REG_BASE +0x512fd*4 +0x02000000,0xf30); +reg_write( DDR_REG_BASE +0x512fe*4 +0x02000000,0xd918); +reg_write( DDR_REG_BASE +0x512ff*4 +0x02000000,0xe0c5); +reg_write( DDR_REG_BASE +0x51300*4 +0x02000000,0xf227); +reg_write( DDR_REG_BASE +0x51301*4 +0x02000000,0xe0d0); +reg_write( DDR_REG_BASE +0x51302*4 +0x02000000,0xf227); +reg_write( DDR_REG_BASE +0x51303*4 +0x02000000,0xe0e0); +reg_write( DDR_REG_BASE +0x51304*4 +0x02000000,0xf227); +reg_write( DDR_REG_BASE +0x51305*4 +0x02000000,0xe0f8); +reg_write( DDR_REG_BASE +0x51306*4 +0x02000000,0xf227); +reg_write( DDR_REG_BASE +0x51307*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x51308*4 +0x02000000,0x8c03); +reg_write( DDR_REG_BASE +0x51309*4 +0x02000000,0x722c); +reg_write( DDR_REG_BASE +0x5130a*4 +0x02000000,0xf230); +reg_write( DDR_REG_BASE +0x5130b*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x5130c*4 +0x02000000,0x8802); +reg_write( DDR_REG_BASE +0x5130d*4 +0x02000000,0xf419); +reg_write( DDR_REG_BASE +0x5130e*4 +0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x5130f*4 +0x02000000,0xf02c); +reg_write( DDR_REG_BASE +0x51310*4 +0x02000000,0x2025); +reg_write( DDR_REG_BASE +0x51311*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x51312*4 +0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x51313*4 +0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x51314*4 +0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x51315*4 +0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x51316*4 +0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x51317*4 +0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x51318*4 +0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x51319*4 +0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x5131a*4 +0x02000000,0xf00b); +reg_write( DDR_REG_BASE +0x5131b*4 +0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x5131c*4 +0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x5131d*4 +0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x5131e*4 +0x02000000,0xf019); +reg_write( DDR_REG_BASE +0x5131f*4 +0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x51320*4 +0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x51321*4 +0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x51322*4 +0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x51323*4 +0x02000000,0xd93f); +reg_write( DDR_REG_BASE +0x51324*4 +0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x51325*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51326*4 +0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x51327*4 +0x02000000,0xd90b); +reg_write( DDR_REG_BASE +0x51328*4 +0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x51329*4 +0x02000000,0xd90a); +reg_write( DDR_REG_BASE +0x5132a*4 +0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x5132b*4 +0x02000000,0xd907); +reg_write( DDR_REG_BASE +0x5132c*4 +0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x5132d*4 +0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x5132e*4 +0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x5132f*4 +0x02000000,0xd93e); +reg_write( DDR_REG_BASE +0x51330*4 +0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x51331*4 +0x02000000,0xd93b); +reg_write( DDR_REG_BASE +0x51332*4 +0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x51333*4 +0x02000000,0xd93a); +reg_write( DDR_REG_BASE +0x51334*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x51335*4 +0x02000000,0xd91f); +reg_write( DDR_REG_BASE +0x51336*4 +0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x51337*4 +0x02000000,0xd938); +reg_write( DDR_REG_BASE +0x51338*4 +0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x51339*4 +0x02000000,0xd91b); +reg_write( DDR_REG_BASE +0x5133a*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x5133b*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x5133c*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5133d*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5133e*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5133f*4 +0x02000000,0xc1b6); +reg_write( DDR_REG_BASE +0x51340*4 +0x02000000,0xc253); +reg_write( DDR_REG_BASE +0x51341*4 +0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x51342*4 +0x02000000,0xc052); +reg_write( DDR_REG_BASE +0x51343*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x51344*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51345*4 +0x02000000,0xaee); +reg_write( DDR_REG_BASE +0x51346*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51347*4 +0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x51348*4 +0x02000000,0xc054); +reg_write( DDR_REG_BASE +0x51349*4 +0x02000000,0x4061); +reg_write( DDR_REG_BASE +0x5134a*4 +0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x5134b*4 +0x02000000,0xae2); +reg_write( DDR_REG_BASE +0x5134c*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5134d*4 +0x02000000,0xda08); +reg_write( DDR_REG_BASE +0x5134e*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5134f*4 +0x02000000,0x708e); +reg_write( DDR_REG_BASE +0x51350*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51351*4 +0x02000000,0x667); +reg_write( DDR_REG_BASE +0x51352*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x51353*4 +0x02000000,0xc055); +reg_write( DDR_REG_BASE +0x51354*4 +0x02000000,0xf03c); +reg_write( DDR_REG_BASE +0x51355*4 +0x02000000,0xc015); +reg_write( DDR_REG_BASE +0x51356*4 +0x02000000,0xc114); +reg_write( DDR_REG_BASE +0x51357*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x51358*4 +0x02000000,0x46); +reg_write( DDR_REG_BASE +0x51359*4 +0x02000000,0xe837); +reg_write( DDR_REG_BASE +0x5135a*4 +0x02000000,0x7def); +reg_write( DDR_REG_BASE +0x5135b*4 +0x02000000,0x60bf); +reg_write( DDR_REG_BASE +0x5135c*4 +0x02000000,0x1a12); +reg_write( DDR_REG_BASE +0x5135d*4 +0x02000000,0x3098); +reg_write( DDR_REG_BASE +0x5135e*4 +0x02000000,0x7bef); +reg_write( DDR_REG_BASE +0x5135f*4 +0x02000000,0xc081); +reg_write( DDR_REG_BASE +0x51360*4 +0x02000000,0x722c); +reg_write( DDR_REG_BASE +0x51361*4 +0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x51362*4 +0x02000000,0xcf6); +reg_write( DDR_REG_BASE +0x51363*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51364*4 +0x02000000,0x4378); +reg_write( DDR_REG_BASE +0x51365*4 +0x02000000,0x1212); +reg_write( DDR_REG_BASE +0x51366*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x51367*4 +0x02000000,0xc213); +reg_write( DDR_REG_BASE +0x51368*4 +0x02000000,0x9ba); +reg_write( DDR_REG_BASE +0x51369*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x5136a*4 +0x02000000,0xc081); +reg_write( DDR_REG_BASE +0x5136b*4 +0x02000000,0xc812); +reg_write( DDR_REG_BASE +0x5136c*4 +0x02000000,0x1203); +reg_write( DDR_REG_BASE +0x5136d*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x5136e*4 +0x02000000,0x82b); +reg_write( DDR_REG_BASE +0x5136f*4 +0x02000000,0x44); +reg_write( DDR_REG_BASE +0x51370*4 +0x02000000,0x1202); +reg_write( DDR_REG_BASE +0x51371*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x51372*4 +0x02000000,0x923); +reg_write( DDR_REG_BASE +0x51373*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51374*4 +0x02000000,0xc031); +reg_write( DDR_REG_BASE +0x51375*4 +0x02000000,0x1443); +reg_write( DDR_REG_BASE +0x51376*4 +0x02000000,0x30c3); +reg_write( DDR_REG_BASE +0x51377*4 +0x02000000,0x1442); +reg_write( DDR_REG_BASE +0x51378*4 +0x02000000,0x3082); +reg_write( DDR_REG_BASE +0x51379*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5137a*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5137b*4 +0x02000000,0x69); +reg_write( DDR_REG_BASE +0x5137c*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x5137d*4 +0x02000000,0xafa); +reg_write( DDR_REG_BASE +0x5137e*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5137f*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x51380*4 +0x02000000,0xde2); +reg_write( DDR_REG_BASE +0x51381*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51382*4 +0x02000000,0xc081); +reg_write( DDR_REG_BASE +0x51383*4 +0x02000000,0x2454); +reg_write( DDR_REG_BASE +0x51384*4 +0x02000000,0x3840); +reg_write( DDR_REG_BASE +0x51385*4 +0x02000000,0x722c); +reg_write( DDR_REG_BASE +0x51386*4 +0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x51387*4 +0x02000000,0x8a6); +reg_write( DDR_REG_BASE +0x51388*4 +0x02000000,0x1a0); +reg_write( DDR_REG_BASE +0x51389*4 +0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x5138a*4 +0x02000000,0xc012); +reg_write( DDR_REG_BASE +0x5138b*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5138c*4 +0x02000000,0xdde); +reg_write( DDR_REG_BASE +0x5138d*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x5138e*4 +0x02000000,0xc281); +reg_write( DDR_REG_BASE +0x5138f*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x51390*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51391*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51392*4 +0x02000000,0x667); +reg_write( DDR_REG_BASE +0x51393*4 +0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x51394*4 +0x02000000,0x79cf); +reg_write( DDR_REG_BASE +0x51395*4 +0x02000000,0x883); +reg_write( DDR_REG_BASE +0x51396*4 +0x02000000,0x8065); +reg_write( DDR_REG_BASE +0x51397*4 +0x02000000,0x222f); +reg_write( DDR_REG_BASE +0x51398*4 +0x02000000,0x8042); +reg_write( DDR_REG_BASE +0x51399*4 +0x02000000,0xc0b6); +reg_write( DDR_REG_BASE +0x5139a*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x5139b*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x5139c*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5139d*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5139e*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5139f*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x513a0*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x513a1*4 +0x02000000,0xc1b7); +reg_write( DDR_REG_BASE +0x513a2*4 +0x02000000,0xc056); +reg_write( DDR_REG_BASE +0x513a3*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x513a4*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x513a5*4 +0x02000000,0xa2e); +reg_write( DDR_REG_BASE +0x513a6*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x513a7*4 +0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x513a8*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x513a9*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x513aa*4 +0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x513ab*4 +0x02000000,0xa22); +reg_write( DDR_REG_BASE +0x513ac*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x513ad*4 +0x02000000,0xda08); +reg_write( DDR_REG_BASE +0x513ae*4 +0x02000000,0x60ba); +reg_write( DDR_REG_BASE +0x513af*4 +0x02000000,0xca06); +reg_write( DDR_REG_BASE +0x513b0*4 +0x02000000,0x794f); +reg_write( DDR_REG_BASE +0x513b1*4 +0x02000000,0x43db); +reg_write( DDR_REG_BASE +0x513b2*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x513b3*4 +0x02000000,0x667); +reg_write( DDR_REG_BASE +0x513b4*4 +0x02000000,0x782a); +reg_write( DDR_REG_BASE +0x513b5*4 +0x02000000,0xc052); +reg_write( DDR_REG_BASE +0x513b6*4 +0x02000000,0x785b); +reg_write( DDR_REG_BASE +0x513b7*4 +0x02000000,0xc053); +reg_write( DDR_REG_BASE +0x513b8*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x513b9*4 +0x02000000,0x70c0); +reg_write( DDR_REG_BASE +0x513ba*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x513bb*4 +0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x513bc*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x513bd*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x513be*4 +0x02000000,0xc054); +reg_write( DDR_REG_BASE +0x513bf*4 +0x02000000,0xf648); +reg_write( DDR_REG_BASE +0x513c0*4 +0x02000000,0x1301); +reg_write( DDR_REG_BASE +0x513c1*4 +0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x513c2*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x513c3*4 +0x02000000,0xc054); +reg_write( DDR_REG_BASE +0x513c4*4 +0x02000000,0xc012); +reg_write( DDR_REG_BASE +0x513c5*4 +0x02000000,0xc053); +reg_write( DDR_REG_BASE +0x513c6*4 +0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x513c7*4 +0x02000000,0x308f); +reg_write( DDR_REG_BASE +0x513c8*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x513c9*4 +0x02000000,0xf056); +reg_write( DDR_REG_BASE +0x513ca*4 +0x02000000,0xc013); +reg_write( DDR_REG_BASE +0x513cb*4 +0x02000000,0xc312); +reg_write( DDR_REG_BASE +0x513cc*4 +0x02000000,0x7a0f); +reg_write( DDR_REG_BASE +0x513cd*4 +0x02000000,0x62b8); +reg_write( DDR_REG_BASE +0x513ce*4 +0x02000000,0x7e6f); +reg_write( DDR_REG_BASE +0x513cf*4 +0x02000000,0x70d1); +reg_write( DDR_REG_BASE +0x513d0*4 +0x02000000,0xa97); +reg_write( DDR_REG_BASE +0x513d1*4 +0x02000000,0x30); +reg_write( DDR_REG_BASE +0x513d2*4 +0x02000000,0x26ca); +reg_write( DDR_REG_BASE +0x513d3*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x513d4*4 +0x02000000,0x78fd); +reg_write( DDR_REG_BASE +0x513d5*4 +0x02000000,0x5052); +reg_write( DDR_REG_BASE +0x513d6*4 +0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x513d7*4 +0x02000000,0xc055); +reg_write( DDR_REG_BASE +0x513d8*4 +0x02000000,0xc315); +reg_write( DDR_REG_BASE +0x513d9*4 +0x02000000,0xc081); +reg_write( DDR_REG_BASE +0x513da*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x513db*4 +0x02000000,0xc06); +reg_write( DDR_REG_BASE +0x513dc*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x513dd*4 +0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x513de*4 +0x02000000,0x1212); +reg_write( DDR_REG_BASE +0x513df*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x513e0*4 +0x02000000,0xc081); +reg_write( DDR_REG_BASE +0x513e1*4 +0x02000000,0x8ca); +reg_write( DDR_REG_BASE +0x513e2*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x513e3*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x513e4*4 +0x02000000,0xc812); +reg_write( DDR_REG_BASE +0x513e5*4 +0x02000000,0x1203); +reg_write( DDR_REG_BASE +0x513e6*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x513e7*4 +0x02000000,0x82d); +reg_write( DDR_REG_BASE +0x513e8*4 +0x02000000,0x44); +reg_write( DDR_REG_BASE +0x513e9*4 +0x02000000,0x1202); +reg_write( DDR_REG_BASE +0x513ea*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x513eb*4 +0x02000000,0x925); +reg_write( DDR_REG_BASE +0x513ec*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x513ed*4 +0x02000000,0xc031); +reg_write( DDR_REG_BASE +0x513ee*4 +0x02000000,0x1443); +reg_write( DDR_REG_BASE +0x513ef*4 +0x02000000,0x30c3); +reg_write( DDR_REG_BASE +0x513f0*4 +0x02000000,0x1442); +reg_write( DDR_REG_BASE +0x513f1*4 +0x02000000,0x3082); +reg_write( DDR_REG_BASE +0x513f2*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x513f3*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x513f4*4 +0x02000000,0x70); +reg_write( DDR_REG_BASE +0x513f5*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x513f6*4 +0x02000000,0xa06); +reg_write( DDR_REG_BASE +0x513f7*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x513f8*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x513f9*4 +0x02000000,0xcf2); +reg_write( DDR_REG_BASE +0x513fa*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x513fb*4 +0x02000000,0xc081); +reg_write( DDR_REG_BASE +0x513fc*4 +0x02000000,0xc315); +reg_write( DDR_REG_BASE +0x513fd*4 +0x02000000,0x2454); +reg_write( DDR_REG_BASE +0x513fe*4 +0x02000000,0x3840); +reg_write( DDR_REG_BASE +0x513ff*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51400*4 +0x02000000,0xfb2); +reg_write( DDR_REG_BASE +0x51401*4 +0x02000000,0x160); +reg_write( DDR_REG_BASE +0x51402*4 +0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x51403*4 +0x02000000,0xc016); +reg_write( DDR_REG_BASE +0x51404*4 +0x02000000,0xdca); +reg_write( DDR_REG_BASE +0x51405*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51406*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51407*4 +0x02000000,0x1443); +reg_write( DDR_REG_BASE +0x51408*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x51409*4 +0x02000000,0xc481); +reg_write( DDR_REG_BASE +0x5140a*4 +0x02000000,0xc331); +reg_write( DDR_REG_BASE +0x5140b*4 +0x02000000,0xe10f); +reg_write( DDR_REG_BASE +0x5140c*4 +0x02000000,0x7a2f); +reg_write( DDR_REG_BASE +0x5140d*4 +0x02000000,0x7c54); +reg_write( DDR_REG_BASE +0x5140e*4 +0x02000000,0x8c21); +reg_write( DDR_REG_BASE +0x5140f*4 +0x02000000,0x7962); +reg_write( DDR_REG_BASE +0x51410*4 +0x02000000,0x7a2f); +reg_write( DDR_REG_BASE +0x51411*4 +0x02000000,0x8c20); +reg_write( DDR_REG_BASE +0x51412*4 +0x02000000,0x4b31); +reg_write( DDR_REG_BASE +0x51413*4 +0x02000000,0x792f); +reg_write( DDR_REG_BASE +0x51414*4 +0x02000000,0x2109); +reg_write( DDR_REG_BASE +0x51415*4 +0x02000000,0x81); +reg_write( DDR_REG_BASE +0x51416*4 +0x02000000,0x8841); +reg_write( DDR_REG_BASE +0x51417*4 +0x02000000,0x909); +reg_write( DDR_REG_BASE +0x51418*4 +0x02000000,0x85); +reg_write( DDR_REG_BASE +0x51419*4 +0x02000000,0xa821); +reg_write( DDR_REG_BASE +0x5141a*4 +0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x5141b*4 +0x02000000,0xc014); +reg_write( DDR_REG_BASE +0x5141c*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x5141d*4 +0x02000000,0x671f); +reg_write( DDR_REG_BASE +0x5141e*4 +0x02000000,0x1301); +reg_write( DDR_REG_BASE +0x5141f*4 +0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x51420*4 +0x02000000,0x7fef); +reg_write( DDR_REG_BASE +0x51421*4 +0x02000000,0x855); +reg_write( DDR_REG_BASE +0x51422*4 +0x02000000,0x83e5); +reg_write( DDR_REG_BASE +0x51423*4 +0x02000000,0x7d2f); +reg_write( DDR_REG_BASE +0x51424*4 +0x02000000,0xc0b7); +reg_write( DDR_REG_BASE +0x51425*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x51426*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x51427*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51428*4 +0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x51429*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x5142a*4 +0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x5142b*4 +0x02000000,0x265a); +reg_write( DDR_REG_BASE +0x5142c*4 +0x02000000,0x3c83); +reg_write( DDR_REG_BASE +0x5142d*4 +0x02000000,0x607c); +reg_write( DDR_REG_BASE +0x5142e*4 +0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x5142f*4 +0x02000000,0x1643); +reg_write( DDR_REG_BASE +0x51430*4 +0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x51431*4 +0x02000000,0x639b); +reg_write( DDR_REG_BASE +0x51432*4 +0x02000000,0x633b); +reg_write( DDR_REG_BASE +0x51433*4 +0x02000000,0x8b80); +reg_write( DDR_REG_BASE +0x51434*4 +0x02000000,0x7c45); +reg_write( DDR_REG_BASE +0x51435*4 +0x02000000,0xab80); +reg_write( DDR_REG_BASE +0x51436*4 +0x02000000,0xbeb); +reg_write( DDR_REG_BASE +0x51437*4 +0x02000000,0x9094); +reg_write( DDR_REG_BASE +0x51438*4 +0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x51439*4 +0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x5143a*4 +0x02000000,0xef9); +reg_write( DDR_REG_BASE +0x5143b*4 +0x02000000,0xb0b4); +reg_write( DDR_REG_BASE +0x5143c*4 +0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x5143d*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5143e*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5143f*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51440*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51441*4 +0x02000000,0xc1bb); +reg_write( DDR_REG_BASE +0x51442*4 +0x02000000,0x9fe); +reg_write( DDR_REG_BASE +0x51443*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x51444*4 +0x02000000,0xc082); +reg_write( DDR_REG_BASE +0x51445*4 +0x02000000,0xc082); +reg_write( DDR_REG_BASE +0x51446*4 +0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x51447*4 +0x02000000,0xfc6); +reg_write( DDR_REG_BASE +0x51448*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51449*4 +0x02000000,0xdac8); +reg_write( DDR_REG_BASE +0x5144a*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5144b*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5144c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5144d*4 +0x02000000,0x1b); +reg_write( DDR_REG_BASE +0x5144e*4 +0x02000000,0x897); +reg_write( DDR_REG_BASE +0x5144f*4 +0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x51450*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51451*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51452*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x51453*4 +0x02000000,0x880e); +reg_write( DDR_REG_BASE +0x51454*4 +0x02000000,0x88b); +reg_write( DDR_REG_BASE +0x51455*4 +0x02000000,0x30); +reg_write( DDR_REG_BASE +0x51456*4 +0x02000000,0xdb4b); +reg_write( DDR_REG_BASE +0x51457*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51458*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51459*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x5145a*4 +0x02000000,0x888d); +reg_write( DDR_REG_BASE +0x5145b*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5145c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5145d*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x5145e*4 +0x02000000,0x88ac); +reg_write( DDR_REG_BASE +0x5145f*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51460*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51461*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x51462*4 +0x02000000,0x88cb); +reg_write( DDR_REG_BASE +0x51463*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51464*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51465*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x51466*4 +0x02000000,0x882a); +reg_write( DDR_REG_BASE +0x51467*4 +0x02000000,0xbb9f); +reg_write( DDR_REG_BASE +0x51468*4 +0x02000000,0x1b01); +reg_write( DDR_REG_BASE +0x51469*4 +0x02000000,0x52); +reg_write( DDR_REG_BASE +0x5146a*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5146b*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5146c*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x5146d*4 +0x02000000,0x88eb); +reg_write( DDR_REG_BASE +0x5146e*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5146f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51470*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x51471*4 +0x02000000,0xabe0); +reg_write( DDR_REG_BASE +0x51472*4 +0x02000000,0x884c); +reg_write( DDR_REG_BASE +0x51473*4 +0x02000000,0x279a); +reg_write( DDR_REG_BASE +0x51474*4 +0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x51475*4 +0x02000000,0x1b32); +reg_write( DDR_REG_BASE +0x51476*4 +0x02000000,0x82); +reg_write( DDR_REG_BASE +0x51477*4 +0x02000000,0xc165); +reg_write( DDR_REG_BASE +0x51478*4 +0x02000000,0x1c2d); +reg_write( DDR_REG_BASE +0x51479*4 +0x02000000,0x3382); +reg_write( DDR_REG_BASE +0x5147a*4 +0x02000000,0x1c46); +reg_write( DDR_REG_BASE +0x5147b*4 +0x02000000,0x3342); +reg_write( DDR_REG_BASE +0x5147c*4 +0x02000000,0x1c5f); +reg_write( DDR_REG_BASE +0x5147d*4 +0x02000000,0x3302); +reg_write( DDR_REG_BASE +0x5147e*4 +0x02000000,0x13b8); +reg_write( DDR_REG_BASE +0x5147f*4 +0x02000000,0x8080); +reg_write( DDR_REG_BASE +0x51480*4 +0x02000000,0x7f25); +reg_write( DDR_REG_BASE +0x51481*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51482*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51483*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x51484*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x51485*4 +0x02000000,0x18d); +reg_write( DDR_REG_BASE +0x51486*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51487*4 +0x02000000,0x12); +reg_write( DDR_REG_BASE +0x51488*4 +0x02000000,0x310); +reg_write( DDR_REG_BASE +0x51489*4 +0x02000000,0x892d); +reg_write( DDR_REG_BASE +0x5148a*4 +0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x5148b*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x5148c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5148d*4 +0x02000000,0x65d8); +reg_write( DDR_REG_BASE +0x5148e*4 +0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x5148f*4 +0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x51490*4 +0x02000000,0x1b33); +reg_write( DDR_REG_BASE +0x51491*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x51492*4 +0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x51493*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51494*4 +0x02000000,0x6e02); +reg_write( DDR_REG_BASE +0x51495*4 +0x02000000,0x60b8); +reg_write( DDR_REG_BASE +0x51496*4 +0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x51497*4 +0x02000000,0x7945); +reg_write( DDR_REG_BASE +0x51498*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51499*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5149a*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5149b*4 +0x02000000,0xc082); +reg_write( DDR_REG_BASE +0x5149c*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5149d*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x5149e*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x5149f*4 +0x02000000,0x5800); +reg_write( DDR_REG_BASE +0x514a0*4 +0x02000000,0xb92); +reg_write( DDR_REG_BASE +0x514a1*4 +0x02000000,0x1a0); +reg_write( DDR_REG_BASE +0x514a2*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x514a3*4 +0x02000000,0xb1e); +reg_write( DDR_REG_BASE +0x514a4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x514a5*4 +0x02000000,0x87a); +reg_write( DDR_REG_BASE +0x514a6*4 +0x02000000,0xff0f); +reg_write( DDR_REG_BASE +0x514a7*4 +0x02000000,0xb52); +reg_write( DDR_REG_BASE +0x514a8*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x514a9*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x514aa*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x514ab*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x514ac*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x514ad*4 +0x02000000,0xdc); +reg_write( DDR_REG_BASE +0x514ae*4 +0x02000000,0x256f); +reg_write( DDR_REG_BASE +0x514af*4 +0x02000000,0x1cc3); +reg_write( DDR_REG_BASE +0x514b0*4 +0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x514b1*4 +0x02000000,0xe8a4); +reg_write( DDR_REG_BASE +0x514b2*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x514b3*4 +0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x514b4*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x514b5*4 +0x02000000,0x7042); +reg_write( DDR_REG_BASE +0x514b6*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x514b7*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x514b8*4 +0x02000000,0x839); +reg_write( DDR_REG_BASE +0x514b9*4 +0x02000000,0x95); +reg_write( DDR_REG_BASE +0x514ba*4 +0x02000000,0xe812); +reg_write( DDR_REG_BASE +0x514bb*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x514bc*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x514bd*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x514be*4 +0x02000000,0x58); +reg_write( DDR_REG_BASE +0x514bf*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x514c0*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x514c1*4 +0x02000000,0xf20a); +reg_write( DDR_REG_BASE +0x514c2*4 +0x02000000,0x6901); +reg_write( DDR_REG_BASE +0x514c3*4 +0x02000000,0xd36); +reg_write( DDR_REG_BASE +0x514c4*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x514c5*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x514c6*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x514c7*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x514c8*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x514c9*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x514ca*4 +0x02000000,0x6821); +reg_write( DDR_REG_BASE +0x514cb*4 +0x02000000,0xf1e9); +reg_write( DDR_REG_BASE +0x514cc*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x514cd*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x514ce*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x514cf*4 +0x02000000,0x25); +reg_write( DDR_REG_BASE +0x514d0*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x514d1*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x514d2*4 +0x02000000,0xf5f0); +reg_write( DDR_REG_BASE +0x514d3*4 +0x02000000,0xf1f8); +reg_write( DDR_REG_BASE +0x514d4*4 +0x02000000,0xd12); +reg_write( DDR_REG_BASE +0x514d5*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x514d6*4 +0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x514d7*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x514d8*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x514d9*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x514da*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x514db*4 +0x02000000,0xa901); +reg_write( DDR_REG_BASE +0x514dc*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x514dd*4 +0x02000000,0x7002); +reg_write( DDR_REG_BASE +0x514de*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x514df*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x514e0*4 +0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x514e1*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x514e2*4 +0x02000000,0xf4b5); +reg_write( DDR_REG_BASE +0x514e3*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x514e4*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x514e5*4 +0x02000000,0x30); +reg_write( DDR_REG_BASE +0x514e6*4 +0x02000000,0x11b4); +reg_write( DDR_REG_BASE +0x514e7*4 +0x02000000,0x502); +reg_write( DDR_REG_BASE +0x514e8*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x514e9*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x514ea*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x514eb*4 +0x02000000,0x25); +reg_write( DDR_REG_BASE +0x514ec*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x514ed*4 +0x02000000,0xa0d); +reg_write( DDR_REG_BASE +0x514ee*4 +0x02000000,0x171); +reg_write( DDR_REG_BASE +0x514ef*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x514f0*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x514f1*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x514f2*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x514f3*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x514f4*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x514f5*4 +0x02000000,0x58); +reg_write( DDR_REG_BASE +0x514f6*4 +0x02000000,0xb101); +reg_write( DDR_REG_BASE +0x514f7*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x514f8*4 +0x02000000,0x86d); +reg_write( DDR_REG_BASE +0x514f9*4 +0x02000000,0x30); +reg_write( DDR_REG_BASE +0x514fa*4 +0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x514fb*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x514fc*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x514fd*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x514fe*4 +0x02000000,0x32); +reg_write( DDR_REG_BASE +0x514ff*4 +0x02000000,0xb8e3); +reg_write( DDR_REG_BASE +0x51500*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51501*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51502*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x51503*4 +0x02000000,0x88e6); +reg_write( DDR_REG_BASE +0x51504*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51505*4 +0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x51506*4 +0x02000000,0x30a1); +reg_write( DDR_REG_BASE +0x51507*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x51508*4 +0x02000000,0x8e); +reg_write( DDR_REG_BASE +0x51509*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x5150a*4 +0x02000000,0x4d); +reg_write( DDR_REG_BASE +0x5150b*4 +0x02000000,0xf01d); +reg_write( DDR_REG_BASE +0x5150c*4 +0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x5150d*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x5150e*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5150f*4 +0x02000000,0xb9c1); +reg_write( DDR_REG_BASE +0x51510*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x51511*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x51512*4 +0x02000000,0xf849); +reg_write( DDR_REG_BASE +0x51513*4 +0x02000000,0x271a); +reg_write( DDR_REG_BASE +0x51514*4 +0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x51515*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51516*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x51517*4 +0x02000000,0xf84c); +reg_write( DDR_REG_BASE +0x51518*4 +0x02000000,0xed07); +reg_write( DDR_REG_BASE +0x51519*4 +0x02000000,0x79ef); +reg_write( DDR_REG_BASE +0x5151a*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5151b*4 +0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x5151c*4 +0x02000000,0x882); +reg_write( DDR_REG_BASE +0x5151d*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x5151e*4 +0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x5151f*4 +0x02000000,0xee08); +reg_write( DDR_REG_BASE +0x51520*4 +0x02000000,0x79ef); +reg_write( DDR_REG_BASE +0x51521*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51522*4 +0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x51523*4 +0x02000000,0x876); +reg_write( DDR_REG_BASE +0x51524*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51525*4 +0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x51526*4 +0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x51527*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51528*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51529*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x5152a*4 +0x02000000,0x8807); +reg_write( DDR_REG_BASE +0x5152b*4 +0x02000000,0x8c5); +reg_write( DDR_REG_BASE +0x5152c*4 +0x02000000,0x83e5); +reg_write( DDR_REG_BASE +0x5152d*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x5152e*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5152f*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x51530*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51531*4 +0x02000000,0x58); +reg_write( DDR_REG_BASE +0x51532*4 +0x02000000,0xd79); +reg_write( DDR_REG_BASE +0x51533*4 +0x02000000,0x1030); +reg_write( DDR_REG_BASE +0x51534*4 +0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x51535*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51536*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51537*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51538*4 +0x02000000,0x65); +reg_write( DDR_REG_BASE +0x51539*4 +0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x5153a*4 +0x02000000,0x108e); +reg_write( DDR_REG_BASE +0x5153b*4 +0x02000000,0xb8e3); +reg_write( DDR_REG_BASE +0x5153c*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5153d*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5153e*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x5153f*4 +0x02000000,0x8808); +reg_write( DDR_REG_BASE +0x51540*4 +0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x51541*4 +0x02000000,0x30a1); +reg_write( DDR_REG_BASE +0x51542*4 +0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x51543*4 +0x02000000,0x104f); +reg_write( DDR_REG_BASE +0x51544*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51545*4 +0x02000000,0xf022); +reg_write( DDR_REG_BASE +0x51546*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x51547*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51548*4 +0x02000000,0x2553); +reg_write( DDR_REG_BASE +0x51549*4 +0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x5154a*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x5154b*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x5154c*4 +0x02000000,0xf82c); +reg_write( DDR_REG_BASE +0x5154d*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5154e*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x5154f*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51550*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51551*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x51552*4 +0x02000000,0xf82e); +reg_write( DDR_REG_BASE +0x51553*4 +0x02000000,0xef09); +reg_write( DDR_REG_BASE +0x51554*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51555*4 +0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x51556*4 +0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x51557*4 +0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x51558*4 +0x02000000,0x80a); +reg_write( DDR_REG_BASE +0x51559*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x5155a*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5155b*4 +0x02000000,0xee09); +reg_write( DDR_REG_BASE +0x5155c*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5155d*4 +0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x5155e*4 +0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x5155f*4 +0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x51560*4 +0x02000000,0xffa); +reg_write( DDR_REG_BASE +0x51561*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51562*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51563*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51564*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x51565*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51566*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51567*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51568*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x51569*4 +0x02000000,0x8829); +reg_write( DDR_REG_BASE +0x5156a*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5156b*4 +0x02000000,0x9b9); +reg_write( DDR_REG_BASE +0x5156c*4 +0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x5156d*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x5156e*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5156f*4 +0x02000000,0x708e); +reg_write( DDR_REG_BASE +0x51570*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51571*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51572*4 +0x02000000,0xb76); +reg_write( DDR_REG_BASE +0x51573*4 +0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x51574*4 +0x02000000,0xb7e); +reg_write( DDR_REG_BASE +0x51575*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51576*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x51577*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x51578*4 +0x02000000,0xa0a); +reg_write( DDR_REG_BASE +0x51579*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x5157a*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x5157b*4 +0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x5157c*4 +0x02000000,0x1f8c); +reg_write( DDR_REG_BASE +0x5157d*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5157e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5157f*4 +0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x51580*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x51581*4 +0x02000000,0x1ea); +reg_write( DDR_REG_BASE +0x51582*4 +0x02000000,0x9300); +reg_write( DDR_REG_BASE +0x51583*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x51584*4 +0x02000000,0x9012); +reg_write( DDR_REG_BASE +0x51585*4 +0x02000000,0x402); +reg_write( DDR_REG_BASE +0x51586*4 +0x02000000,0x2405); +reg_write( DDR_REG_BASE +0x51587*4 +0x02000000,0x1342); +reg_write( DDR_REG_BASE +0x51588*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x51589*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x5158a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5158b*4 +0x02000000,0x3f00); +reg_write( DDR_REG_BASE +0x5158c*4 +0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x5158d*4 +0x02000000,0x6d44); +reg_write( DDR_REG_BASE +0x5158e*4 +0x02000000,0x7a85); +reg_write( DDR_REG_BASE +0x5158f*4 +0x02000000,0x2196); +reg_write( DDR_REG_BASE +0x51590*4 +0x02000000,0x6); +reg_write( DDR_REG_BASE +0x51591*4 +0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x51592*4 +0x02000000,0x9321); +reg_write( DDR_REG_BASE +0x51593*4 +0x02000000,0x6d02); +reg_write( DDR_REG_BASE +0x51594*4 +0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x51595*4 +0x02000000,0xb9c5); +reg_write( DDR_REG_BASE +0x51596*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51597*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51598*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51599*4 +0x02000000,0xe174); +reg_write( DDR_REG_BASE +0x5159a*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5159b*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x5159c*4 +0x02000000,0xcca); +reg_write( DDR_REG_BASE +0x5159d*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5159e*4 +0x02000000,0xb021); +reg_write( DDR_REG_BASE +0x5159f*4 +0x02000000,0xc0bb); +reg_write( DDR_REG_BASE +0x515a0*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x515a1*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x515a2*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x515a3*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x515a4*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x515a5*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x515a6*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x515a7*4 +0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x515a8*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x515a9*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x515aa*4 +0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x515ab*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x515ac*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x515ad*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x515ae*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x515af*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x515b0*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x515b1*4 +0x02000000,0x154); +reg_write( DDR_REG_BASE +0x515b2*4 +0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x515b3*4 +0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x515b4*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x515b5*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x515b6*4 +0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x515b7*4 +0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x515b8*4 +0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x515b9*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x515ba*4 +0x02000000,0x89a); +reg_write( DDR_REG_BASE +0x515bb*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x515bc*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x515bd*4 +0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x515be*4 +0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x515bf*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x515c0*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x515c1*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x515c2*4 +0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x515c3*4 +0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x515c4*4 +0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x515c5*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x515c6*4 +0x02000000,0x976); +reg_write( DDR_REG_BASE +0x515c7*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x515c8*4 +0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x515c9*4 +0x02000000,0xbec1); +reg_write( DDR_REG_BASE +0x515ca*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x515cb*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x515cc*4 +0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x515cd*4 +0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x515ce*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x515cf*4 +0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x515d0*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x515d1*4 +0x02000000,0x962); +reg_write( DDR_REG_BASE +0x515d2*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x515d3*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x515d4*4 +0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x515d5*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x515d6*4 +0x02000000,0x8fa); +reg_write( DDR_REG_BASE +0x515d7*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x515d8*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x515d9*4 +0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x515da*4 +0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x515db*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x515dc*4 +0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x515dd*4 +0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x515de*4 +0x02000000,0xd858); +reg_write( DDR_REG_BASE +0x515df*4 +0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x515e0*4 +0x02000000,0x88c0); +reg_write( DDR_REG_BASE +0x515e1*4 +0x02000000,0x10cd); +reg_write( DDR_REG_BASE +0x515e2*4 +0x02000000,0x808d); +reg_write( DDR_REG_BASE +0x515e3*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x515e4*4 +0x02000000,0x846); +reg_write( DDR_REG_BASE +0x515e5*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x515e6*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x515e7*4 +0x02000000,0x2605); +reg_write( DDR_REG_BASE +0x515e8*4 +0x02000000,0x1341); +reg_write( DDR_REG_BASE +0x515e9*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x515ea*4 +0x02000000,0xb9c1); +reg_write( DDR_REG_BASE +0x515eb*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x515ec*4 +0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x515ed*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x515ee*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x515ef*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x515f0*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x515f1*4 +0x02000000,0xda09); +reg_write( DDR_REG_BASE +0x515f2*4 +0x02000000,0x91e); +reg_write( DDR_REG_BASE +0x515f3*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x515f4*4 +0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x515f5*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x515f6*4 +0x02000000,0x8ba); +reg_write( DDR_REG_BASE +0x515f7*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x515f8*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x515f9*4 +0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x515fa*4 +0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x515fb*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x515fc*4 +0x02000000,0x21aa); +reg_write( DDR_REG_BASE +0x515fd*4 +0x02000000,0xc4); +reg_write( DDR_REG_BASE +0x515fe*4 +0x02000000,0x911); +reg_write( DDR_REG_BASE +0x515ff*4 +0x02000000,0x3f); +reg_write( DDR_REG_BASE +0x51600*4 +0x02000000,0x722c); +reg_write( DDR_REG_BASE +0x51601*4 +0x02000000,0x21ab); +reg_write( DDR_REG_BASE +0x51602*4 +0x02000000,0xc4); +reg_write( DDR_REG_BASE +0x51603*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51604*4 +0x02000000,0x21ab); +reg_write( DDR_REG_BASE +0x51605*4 +0x02000000,0xc4); +reg_write( DDR_REG_BASE +0x51606*4 +0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x51607*4 +0x02000000,0x415); +reg_write( DDR_REG_BASE +0x51608*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51609*4 +0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x5160a*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x5160b*4 +0x02000000,0x1d6); +reg_write( DDR_REG_BASE +0x5160c*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5160d*4 +0x02000000,0x21aa); +reg_write( DDR_REG_BASE +0x5160e*4 +0x02000000,0x104); +reg_write( DDR_REG_BASE +0x5160f*4 +0x02000000,0x7b32); +reg_write( DDR_REG_BASE +0x51610*4 +0x02000000,0xb19); +reg_write( DDR_REG_BASE +0x51611*4 +0x02000000,0x25); +reg_write( DDR_REG_BASE +0x51612*4 +0x02000000,0x24aa); +reg_write( DDR_REG_BASE +0x51613*4 +0x02000000,0x1144); +reg_write( DDR_REG_BASE +0x51614*4 +0x02000000,0x22aa); +reg_write( DDR_REG_BASE +0x51615*4 +0x02000000,0x104); +reg_write( DDR_REG_BASE +0x51616*4 +0x02000000,0x9fd); +reg_write( DDR_REG_BASE +0x51617*4 +0x02000000,0x8084); +reg_write( DDR_REG_BASE +0x51618*4 +0x02000000,0x7862); +reg_write( DDR_REG_BASE +0x51619*4 +0x02000000,0x24aa); +reg_write( DDR_REG_BASE +0x5161a*4 +0x02000000,0x1144); +reg_write( DDR_REG_BASE +0x5161b*4 +0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x5161c*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x5161d*4 +0x02000000,0x21aa); +reg_write( DDR_REG_BASE +0x5161e*4 +0x02000000,0x104); +reg_write( DDR_REG_BASE +0x5161f*4 +0x02000000,0x7110); +reg_write( DDR_REG_BASE +0x51620*4 +0x02000000,0x20e1); +reg_write( DDR_REG_BASE +0x51621*4 +0x02000000,0x7c6); +reg_write( DDR_REG_BASE +0x51622*4 +0x02000000,0x22aa); +reg_write( DDR_REG_BASE +0x51623*4 +0x02000000,0x144); +reg_write( DDR_REG_BASE +0x51624*4 +0x02000000,0xcf3); +reg_write( DDR_REG_BASE +0x51625*4 +0x02000000,0x9080); +reg_write( DDR_REG_BASE +0x51626*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51627*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51628*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x51629*4 +0x02000000,0x866); +reg_write( DDR_REG_BASE +0x5162a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5162b*4 +0x02000000,0xfa6); +reg_write( DDR_REG_BASE +0x5162c*4 +0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x5162d*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x5162e*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5162f*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51630*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x51631*4 +0x02000000,0xf5a); +reg_write( DDR_REG_BASE +0x51632*4 +0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x51633*4 +0x02000000,0xf96); +reg_write( DDR_REG_BASE +0x51634*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51635*4 +0x02000000,0xd814); +reg_write( DDR_REG_BASE +0x51636*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x51637*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51638*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x51639*4 +0x02000000,0x846); +reg_write( DDR_REG_BASE +0x5163a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5163b*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5163c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5163d*4 +0x02000000,0x57c); +reg_write( DDR_REG_BASE +0x5163e*4 +0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x5163f*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51640*4 +0x02000000,0xe915); +reg_write( DDR_REG_BASE +0x51641*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51642*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51643*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51644*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51645*4 +0x02000000,0x923); +reg_write( DDR_REG_BASE +0x51646*4 +0x02000000,0xdf); +reg_write( DDR_REG_BASE +0x51647*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51648*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51649*4 +0x02000000,0x664); +reg_write( DDR_REG_BASE +0x5164a*4 +0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x5164b*4 +0x02000000,0x917); +reg_write( DDR_REG_BASE +0x5164c*4 +0x02000000,0x134); +reg_write( DDR_REG_BASE +0x5164d*4 +0x02000000,0x216c); +reg_write( DDR_REG_BASE +0x5164e*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x5164f*4 +0x02000000,0x2809); +reg_write( DDR_REG_BASE +0x51650*4 +0x02000000,0x8042); +reg_write( DDR_REG_BASE +0x51651*4 +0x02000000,0xf208); +reg_write( DDR_REG_BASE +0x51652*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51653*4 +0x02000000,0x7842); +reg_write( DDR_REG_BASE +0x51654*4 +0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x51655*4 +0x02000000,0x809); +reg_write( DDR_REG_BASE +0x51656*4 +0x02000000,0x115); +reg_write( DDR_REG_BASE +0x51657*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x51658*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x51659*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5165a*4 +0x02000000,0x246f); +reg_write( DDR_REG_BASE +0x5165b*4 +0x02000000,0x1343); +reg_write( DDR_REG_BASE +0x5165c*4 +0x02000000,0x9460); +reg_write( DDR_REG_BASE +0x5165d*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x5165e*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x5165f*4 +0x02000000,0x2a05); +reg_write( DDR_REG_BASE +0x51660*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x51661*4 +0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x51662*4 +0x02000000,0x8480); +reg_write( DDR_REG_BASE +0x51663*4 +0x02000000,0x817); +reg_write( DDR_REG_BASE +0x51664*4 +0x02000000,0xf84); +reg_write( DDR_REG_BASE +0x51665*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x51666*4 +0x02000000,0xd41); +reg_write( DDR_REG_BASE +0x51667*4 +0x02000000,0x2885); +reg_write( DDR_REG_BASE +0x51668*4 +0x02000000,0xa0f); +reg_write( DDR_REG_BASE +0x51669*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x5166a*4 +0x02000000,0xc2); +reg_write( DDR_REG_BASE +0x5166b*4 +0x02000000,0x2a85); +reg_write( DDR_REG_BASE +0x5166c*4 +0x02000000,0x41f); +reg_write( DDR_REG_BASE +0x5166d*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x5166e*4 +0x02000000,0x6a01); +reg_write( DDR_REG_BASE +0x5166f*4 +0x02000000,0x6941); +reg_write( DDR_REG_BASE +0x51670*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51671*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51672*4 +0x02000000,0x57c); +reg_write( DDR_REG_BASE +0x51673*4 +0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x51674*4 +0x02000000,0xe90c); +reg_write( DDR_REG_BASE +0x51675*4 +0x02000000,0x14fb); +reg_write( DDR_REG_BASE +0x51676*4 +0x02000000,0x9081); +reg_write( DDR_REG_BASE +0x51677*4 +0x02000000,0x915); +reg_write( DDR_REG_BASE +0x51678*4 +0x02000000,0xdf); +reg_write( DDR_REG_BASE +0x51679*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5167a*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5167b*4 +0x02000000,0x664); +reg_write( DDR_REG_BASE +0x5167c*4 +0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x5167d*4 +0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x5167e*4 +0x02000000,0x22da); +reg_write( DDR_REG_BASE +0x5167f*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x51680*4 +0x02000000,0x7210); +reg_write( DDR_REG_BASE +0x51681*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x51682*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x51683*4 +0x02000000,0x8d); +reg_write( DDR_REG_BASE +0x51684*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51685*4 +0x02000000,0x8b2); +reg_write( DDR_REG_BASE +0x51686*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51687*4 +0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x51688*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51689*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5168a*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5168b*4 +0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x5168c*4 +0x02000000,0xb9c3); +reg_write( DDR_REG_BASE +0x5168d*4 +0x02000000,0xdd58); +reg_write( DDR_REG_BASE +0x5168e*4 +0x02000000,0x1a04); +reg_write( DDR_REG_BASE +0x5168f*4 +0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x51690*4 +0x02000000,0xbd9f); +reg_write( DDR_REG_BASE +0x51691*4 +0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x51692*4 +0x02000000,0xe80b); +reg_write( DDR_REG_BASE +0x51693*4 +0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x51694*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x51695*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51696*4 +0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x51697*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51698*4 +0x02000000,0x57); +reg_write( DDR_REG_BASE +0x51699*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x5169a*4 +0x02000000,0xe00); +reg_write( DDR_REG_BASE +0x5169b*4 +0x02000000,0x621e); +reg_write( DDR_REG_BASE +0x5169c*4 +0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x5169d*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5169e*4 +0x02000000,0x708e); +reg_write( DDR_REG_BASE +0x5169f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x516a0*4 +0x02000000,0x24); +reg_write( DDR_REG_BASE +0x516a1*4 +0x02000000,0x87a); +reg_write( DDR_REG_BASE +0x516a2*4 +0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x516a3*4 +0x02000000,0x79cf); +reg_write( DDR_REG_BASE +0x516a4*4 +0x02000000,0x7b3d); +reg_write( DDR_REG_BASE +0x516a5*4 +0x02000000,0x7a3d); +reg_write( DDR_REG_BASE +0x516a6*4 +0x02000000,0x2653); +reg_write( DDR_REG_BASE +0x516a7*4 +0x02000000,0x907e); +reg_write( DDR_REG_BASE +0x516a8*4 +0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x516a9*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x516aa*4 +0x02000000,0x23c0); +reg_write( DDR_REG_BASE +0x516ab*4 +0x02000000,0x62); +reg_write( DDR_REG_BASE +0x516ac*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x516ad*4 +0x02000000,0x2653); +reg_write( DDR_REG_BASE +0x516ae*4 +0x02000000,0x9081); +reg_write( DDR_REG_BASE +0x516af*4 +0x02000000,0xb8c3); +reg_write( DDR_REG_BASE +0x516b0*4 +0x02000000,0x22c0); +reg_write( DDR_REG_BASE +0x516b1*4 +0x02000000,0x62); +reg_write( DDR_REG_BASE +0x516b2*4 +0x02000000,0x1a05); +reg_write( DDR_REG_BASE +0x516b3*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x516b4*4 +0x02000000,0x1a07); +reg_write( DDR_REG_BASE +0x516b5*4 +0x02000000,0x30c2); +reg_write( DDR_REG_BASE +0x516b6*4 +0x02000000,0x1a09); +reg_write( DDR_REG_BASE +0x516b7*4 +0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x516b8*4 +0x02000000,0x1a06); +reg_write( DDR_REG_BASE +0x516b9*4 +0x02000000,0x3082); +reg_write( DDR_REG_BASE +0x516ba*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x516bb*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x516bc*4 +0x02000000,0xeb); +reg_write( DDR_REG_BASE +0x516bd*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x516be*4 +0x02000000,0xc76); +reg_write( DDR_REG_BASE +0x516bf*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516c0*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x516c1*4 +0x02000000,0x276f); +reg_write( DDR_REG_BASE +0x516c2*4 +0x02000000,0x10c3); +reg_write( DDR_REG_BASE +0x516c3*4 +0x02000000,0x8f00); +reg_write( DDR_REG_BASE +0x516c4*4 +0x02000000,0xb8e2); +reg_write( DDR_REG_BASE +0x516c5*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x516c6*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x516c7*4 +0x02000000,0xe1); +reg_write( DDR_REG_BASE +0x516c8*4 +0x02000000,0x1a0a); +reg_write( DDR_REG_BASE +0x516c9*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x516ca*4 +0x02000000,0x1724); +reg_write( DDR_REG_BASE +0x516cb*4 +0x02000000,0x1082); +reg_write( DDR_REG_BASE +0x516cc*4 +0x02000000,0x170f); +reg_write( DDR_REG_BASE +0x516cd*4 +0x02000000,0x1481); +reg_write( DDR_REG_BASE +0x516ce*4 +0x02000000,0x2742); +reg_write( DDR_REG_BASE +0x516cf*4 +0x02000000,0x1280); +reg_write( DDR_REG_BASE +0x516d0*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x516d1*4 +0x02000000,0x8d60); +reg_write( DDR_REG_BASE +0x516d2*4 +0x02000000,0x97c0); +reg_write( DDR_REG_BASE +0x516d3*4 +0x02000000,0x8f82); +reg_write( DDR_REG_BASE +0x516d4*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x516d5*4 +0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x516d6*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x516d7*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x516d8*4 +0x02000000,0xed); +reg_write( DDR_REG_BASE +0x516d9*4 +0x02000000,0x6); +reg_write( DDR_REG_BASE +0x516da*4 +0x02000000,0xc441); +reg_write( DDR_REG_BASE +0x516db*4 +0x02000000,0xc3e); +reg_write( DDR_REG_BASE +0x516dc*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516dd*4 +0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x516de*4 +0x02000000,0x8f08); +reg_write( DDR_REG_BASE +0x516df*4 +0x02000000,0xe808); +reg_write( DDR_REG_BASE +0x516e0*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x516e1*4 +0x02000000,0xf2); +reg_write( DDR_REG_BASE +0x516e2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x516e3*4 +0x02000000,0xc2e); +reg_write( DDR_REG_BASE +0x516e4*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516e5*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x516e6*4 +0x02000000,0xde32); +reg_write( DDR_REG_BASE +0x516e7*4 +0x02000000,0xbe9f); +reg_write( DDR_REG_BASE +0x516e8*4 +0x02000000,0x1601); +reg_write( DDR_REG_BASE +0x516e9*4 +0x02000000,0x1483); +reg_write( DDR_REG_BASE +0x516ea*4 +0x02000000,0x16d1); +reg_write( DDR_REG_BASE +0x516eb*4 +0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x516ec*4 +0x02000000,0x1601); +reg_write( DDR_REG_BASE +0x516ed*4 +0x02000000,0x148c); +reg_write( DDR_REG_BASE +0x516ee*4 +0x02000000,0x1602); +reg_write( DDR_REG_BASE +0x516ef*4 +0x02000000,0x1481); +reg_write( DDR_REG_BASE +0x516f0*4 +0x02000000,0x1601); +reg_write( DDR_REG_BASE +0x516f1*4 +0x02000000,0x1480); +reg_write( DDR_REG_BASE +0x516f2*4 +0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x516f3*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x516f4*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x516f5*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x516f6*4 +0x02000000,0xf3); +reg_write( DDR_REG_BASE +0x516f7*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x516f8*4 +0x02000000,0xc02); +reg_write( DDR_REG_BASE +0x516f9*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x516fa*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x516fb*4 +0x02000000,0x1601); +reg_write( DDR_REG_BASE +0x516fc*4 +0x02000000,0x1483); +reg_write( DDR_REG_BASE +0x516fd*4 +0x02000000,0x8e21); +reg_write( DDR_REG_BASE +0x516fe*4 +0x02000000,0x8e04); +reg_write( DDR_REG_BASE +0x516ff*4 +0x02000000,0x16cc); +reg_write( DDR_REG_BASE +0x51700*4 +0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x51701*4 +0x02000000,0x8e80); +reg_write( DDR_REG_BASE +0x51702*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51703*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51704*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51705*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51706*4 +0x02000000,0xf4); +reg_write( DDR_REG_BASE +0x51707*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51708*4 +0x02000000,0xbe2); +reg_write( DDR_REG_BASE +0x51709*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5170a*4 +0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x5170b*4 +0x02000000,0x8f08); +reg_write( DDR_REG_BASE +0x5170c*4 +0x02000000,0x8b5); +reg_write( DDR_REG_BASE +0x5170d*4 +0x02000000,0x11); +reg_write( DDR_REG_BASE +0x5170e*4 +0x02000000,0x8f15); +reg_write( DDR_REG_BASE +0x5170f*4 +0x02000000,0x831); +reg_write( DDR_REG_BASE +0x51710*4 +0x02000000,0x7e); +reg_write( DDR_REG_BASE +0x51711*4 +0x02000000,0xdf3e); +reg_write( DDR_REG_BASE +0x51712*4 +0x02000000,0xf840); +reg_write( DDR_REG_BASE +0x51713*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51714*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51715*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51716*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51717*4 +0x02000000,0xf5); +reg_write( DDR_REG_BASE +0x51718*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51719*4 +0x02000000,0xbc2); +reg_write( DDR_REG_BASE +0x5171a*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5171b*4 +0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x5171c*4 +0x02000000,0xf841); +reg_write( DDR_REG_BASE +0x5171d*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5171e*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x5171f*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51720*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51721*4 +0x02000000,0xf6); +reg_write( DDR_REG_BASE +0x51722*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51723*4 +0x02000000,0xbae); +reg_write( DDR_REG_BASE +0x51724*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51725*4 +0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51726*4 +0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x51727*4 +0x02000000,0x833); +reg_write( DDR_REG_BASE +0x51728*4 +0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x51729*4 +0x02000000,0xdf65); +reg_write( DDR_REG_BASE +0x5172a*4 +0x02000000,0xf834); +reg_write( DDR_REG_BASE +0x5172b*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x5172c*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5172d*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x5172e*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5172f*4 +0x02000000,0xf7); +reg_write( DDR_REG_BASE +0x51730*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51731*4 +0x02000000,0xb92); +reg_write( DDR_REG_BASE +0x51732*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51733*4 +0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51734*4 +0x02000000,0xf835); +reg_write( DDR_REG_BASE +0x51735*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51736*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51737*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51738*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51739*4 +0x02000000,0xf8); +reg_write( DDR_REG_BASE +0x5173a*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x5173b*4 +0x02000000,0xb7e); +reg_write( DDR_REG_BASE +0x5173c*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5173d*4 +0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x5173e*4 +0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x5173f*4 +0x02000000,0x851); +reg_write( DDR_REG_BASE +0x51740*4 +0x02000000,0x7e); +reg_write( DDR_REG_BASE +0x51741*4 +0x02000000,0xdd71); +reg_write( DDR_REG_BASE +0x51742*4 +0x02000000,0xbd9f); +reg_write( DDR_REG_BASE +0x51743*4 +0x02000000,0x1501); +reg_write( DDR_REG_BASE +0x51744*4 +0x02000000,0x1483); +reg_write( DDR_REG_BASE +0x51745*4 +0x02000000,0x1501); +reg_write( DDR_REG_BASE +0x51746*4 +0x02000000,0x148c); +reg_write( DDR_REG_BASE +0x51747*4 +0x02000000,0x1502); +reg_write( DDR_REG_BASE +0x51748*4 +0x02000000,0x1481); +reg_write( DDR_REG_BASE +0x51749*4 +0x02000000,0x1501); +reg_write( DDR_REG_BASE +0x5174a*4 +0x02000000,0x1480); +reg_write( DDR_REG_BASE +0x5174b*4 +0x02000000,0x16cc); +reg_write( DDR_REG_BASE +0x5174c*4 +0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x5174d*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x5174e*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5174f*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51750*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51751*4 +0x02000000,0xf9); +reg_write( DDR_REG_BASE +0x51752*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51753*4 +0x02000000,0xb4e); +reg_write( DDR_REG_BASE +0x51754*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51755*4 +0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51756*4 +0x02000000,0x1501); +reg_write( DDR_REG_BASE +0x51757*4 +0x02000000,0x1483); +reg_write( DDR_REG_BASE +0x51758*4 +0x02000000,0x8d21); +reg_write( DDR_REG_BASE +0x51759*4 +0x02000000,0x8d04); +reg_write( DDR_REG_BASE +0x5175a*4 +0x02000000,0x16cc); +reg_write( DDR_REG_BASE +0x5175b*4 +0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x5175c*4 +0x02000000,0x8d80); +reg_write( DDR_REG_BASE +0x5175d*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5175e*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x5175f*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51760*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51761*4 +0x02000000,0xfa); +reg_write( DDR_REG_BASE +0x51762*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51763*4 +0x02000000,0xb2e); +reg_write( DDR_REG_BASE +0x51764*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51765*4 +0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x51766*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51767*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x51768*4 +0x02000000,0x1a0); +reg_write( DDR_REG_BASE +0x51769*4 +0x02000000,0x1802); +reg_write( DDR_REG_BASE +0x5176a*4 +0x02000000,0x15); +reg_write( DDR_REG_BASE +0x5176b*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x5176c*4 +0x02000000,0x44); +reg_write( DDR_REG_BASE +0x5176d*4 +0x02000000,0x1802); +reg_write( DDR_REG_BASE +0x5176e*4 +0x02000000,0x54); +reg_write( DDR_REG_BASE +0x5176f*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51770*4 +0x02000000,0x144); +reg_write( DDR_REG_BASE +0x51771*4 +0x02000000,0x1802); +reg_write( DDR_REG_BASE +0x51772*4 +0x02000000,0x54); +reg_write( DDR_REG_BASE +0x51773*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51774*4 +0x02000000,0x1c4); +reg_write( DDR_REG_BASE +0x51775*4 +0x02000000,0x1804); +reg_write( DDR_REG_BASE +0x51776*4 +0x02000000,0x54); +reg_write( DDR_REG_BASE +0x51777*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51778*4 +0x02000000,0x88); +reg_write( DDR_REG_BASE +0x51779*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x5177a*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x5177b*4 +0x02000000,0x288); +reg_write( DDR_REG_BASE +0x5177c*4 +0x02000000,0xb021); +reg_write( DDR_REG_BASE +0x5177d*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x5177e*4 +0x02000000,0x2c8); +reg_write( DDR_REG_BASE +0x5177f*4 +0x02000000,0xb022); +reg_write( DDR_REG_BASE +0x51780*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x51781*4 +0x02000000,0x3cc); +reg_write( DDR_REG_BASE +0x51782*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51783*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x51784*4 +0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x51785*4 +0x02000000,0xe180); +reg_write( DDR_REG_BASE +0x51786*4 +0x02000000,0xd934); +reg_write( DDR_REG_BASE +0x51787*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51788*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x51789*4 +0x02000000,0xe0ee); +reg_write( DDR_REG_BASE +0x5178a*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x5178b*4 +0x02000000,0xd4e); +reg_write( DDR_REG_BASE +0x5178c*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5178d*4 +0x02000000,0x18fc); +reg_write( DDR_REG_BASE +0x5178e*4 +0x02000000,0x8105); +reg_write( DDR_REG_BASE +0x5178f*4 +0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x51790*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51791*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51792*4 +0x02000000,0xbf9f); +reg_write( DDR_REG_BASE +0x51793*4 +0x02000000,0x1701); +reg_write( DDR_REG_BASE +0x51794*4 +0x02000000,0x1483); +reg_write( DDR_REG_BASE +0x51795*4 +0x02000000,0x1701); +reg_write( DDR_REG_BASE +0x51796*4 +0x02000000,0x148c); +reg_write( DDR_REG_BASE +0x51797*4 +0x02000000,0x1702); +reg_write( DDR_REG_BASE +0x51798*4 +0x02000000,0x1481); +reg_write( DDR_REG_BASE +0x51799*4 +0x02000000,0x1701); +reg_write( DDR_REG_BASE +0x5179a*4 +0x02000000,0x1480); +reg_write( DDR_REG_BASE +0x5179b*4 +0x02000000,0x16cc); +reg_write( DDR_REG_BASE +0x5179c*4 +0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x5179d*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5179e*4 +0x02000000,0x1701); +reg_write( DDR_REG_BASE +0x5179f*4 +0x02000000,0x1483); +reg_write( DDR_REG_BASE +0x517a0*4 +0x02000000,0x8f21); +reg_write( DDR_REG_BASE +0x517a1*4 +0x02000000,0x8f04); +reg_write( DDR_REG_BASE +0x517a2*4 +0x02000000,0x16cc); +reg_write( DDR_REG_BASE +0x517a3*4 +0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x517a4*4 +0x02000000,0x8f80); +reg_write( DDR_REG_BASE +0x517a5*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x517a6*4 +0x02000000,0x621a); +reg_write( DDR_REG_BASE +0x517a7*4 +0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x517a8*4 +0x02000000,0x1801); +reg_write( DDR_REG_BASE +0x517a9*4 +0x02000000,0x52); +reg_write( DDR_REG_BASE +0x517aa*4 +0x02000000,0x8fd); +reg_write( DDR_REG_BASE +0x517ab*4 +0x02000000,0x8084); +reg_write( DDR_REG_BASE +0x517ac*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x517ad*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x517ae*4 +0x02000000,0x2014); +reg_write( DDR_REG_BASE +0x517af*4 +0x02000000,0x82); +reg_write( DDR_REG_BASE +0x517b0*4 +0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x517b1*4 +0x02000000,0x1802); +reg_write( DDR_REG_BASE +0x517b2*4 +0x02000000,0x54); +reg_write( DDR_REG_BASE +0x517b3*4 +0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x517b4*4 +0x02000000,0x8084); +reg_write( DDR_REG_BASE +0x517b5*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x517b6*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x517b7*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x517b8*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x517b9*4 +0x02000000,0xc1a5); +reg_write( DDR_REG_BASE +0x517ba*4 +0x02000000,0xde07); +reg_write( DDR_REG_BASE +0x517bb*4 +0x02000000,0xbe8c); +reg_write( DDR_REG_BASE +0x517bc*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x517bd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x517be*4 +0x02000000,0x9f38); +reg_write( DDR_REG_BASE +0x517bf*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x517c0*4 +0x02000000,0x9012); +reg_write( DDR_REG_BASE +0x517c1*4 +0x02000000,0x328); +reg_write( DDR_REG_BASE +0x517c2*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x517c3*4 +0x02000000,0x7384); +reg_write( DDR_REG_BASE +0x517c4*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x517c5*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x517c6*4 +0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x517c7*4 +0x02000000,0xd858); +reg_write( DDR_REG_BASE +0x517c8*4 +0x02000000,0xb501); +reg_write( DDR_REG_BASE +0x517c9*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x517ca*4 +0x02000000,0x14c); +reg_write( DDR_REG_BASE +0x517cb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x517cc*4 +0x02000000,0xa5a); +reg_write( DDR_REG_BASE +0x517cd*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x517ce*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x517cf*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x517d0*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x517d1*4 +0x02000000,0x150); +reg_write( DDR_REG_BASE +0x517d2*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x517d3*4 +0x02000000,0xa4e); +reg_write( DDR_REG_BASE +0x517d4*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x517d5*4 +0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x517d6*4 +0x02000000,0xcc34); +reg_write( DDR_REG_BASE +0x517d7*4 +0x02000000,0x9520); +reg_write( DDR_REG_BASE +0x517d8*4 +0x02000000,0x7030); +reg_write( DDR_REG_BASE +0x517d9*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x517da*4 +0x02000000,0xf405); +reg_write( DDR_REG_BASE +0x517db*4 +0x02000000,0xcc35); +reg_write( DDR_REG_BASE +0x517dc*4 +0x02000000,0x9521); +reg_write( DDR_REG_BASE +0x517dd*4 +0x02000000,0x2038); +reg_write( DDR_REG_BASE +0x517de*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x517df*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x517e0*4 +0x02000000,0x151); +reg_write( DDR_REG_BASE +0x517e1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x517e2*4 +0x02000000,0xa7e); +reg_write( DDR_REG_BASE +0x517e3*4 +0x02000000,0xfe8f); +reg_write( DDR_REG_BASE +0x517e4*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x517e5*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x517e6*4 +0x02000000,0x57c); +reg_write( DDR_REG_BASE +0x517e7*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x517e8*4 +0x02000000,0x1043); +reg_write( DDR_REG_BASE +0x517e9*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x517ea*4 +0x02000000,0x709b); +reg_write( DDR_REG_BASE +0x517eb*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x517ec*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x517ed*4 +0x02000000,0x1a00); +reg_write( DDR_REG_BASE +0x517ee*4 +0x02000000,0x3103); +reg_write( DDR_REG_BASE +0x517ef*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x517f0*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x517f1*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x517f2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x517f3*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x517f4*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x517f5*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x517f6*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x517f7*4 +0x02000000,0x32); +reg_write( DDR_REG_BASE +0x517f8*4 +0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x517f9*4 +0x02000000,0x243); +reg_write( DDR_REG_BASE +0x517fa*4 +0x02000000,0x9006); +reg_write( DDR_REG_BASE +0x517fb*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x517fc*4 +0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x517fd*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x517fe*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x517ff*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51800*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51801*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51802*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x51803*4 +0x02000000,0xd26); +reg_write( DDR_REG_BASE +0x51804*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x51805*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51806*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51807*4 +0x02000000,0xb8e0); +reg_write( DDR_REG_BASE +0x51808*4 +0x02000000,0x234); +reg_write( DDR_REG_BASE +0x51809*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5180a*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5180b*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5180c*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x5180d*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x5180e*4 +0x02000000,0xe032); +reg_write( DDR_REG_BASE +0x5180f*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x51810*4 +0x02000000,0xb880); +reg_write( DDR_REG_BASE +0x51811*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x51812*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51813*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51814*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51815*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51816*4 +0x02000000,0xe090); +reg_write( DDR_REG_BASE +0x51817*4 +0x02000000,0xc72); +reg_write( DDR_REG_BASE +0x51818*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51819*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x5181a*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x5181b*4 +0x02000000,0x266f); +reg_write( DDR_REG_BASE +0x5181c*4 +0x02000000,0x1cc3); +reg_write( DDR_REG_BASE +0x5181d*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x5181e*4 +0x02000000,0xe885); +reg_write( DDR_REG_BASE +0x5181f*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51820*4 +0x02000000,0x7085); +reg_write( DDR_REG_BASE +0x51821*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51822*4 +0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x51823*4 +0x02000000,0xcc6); +reg_write( DDR_REG_BASE +0x51824*4 +0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x51825*4 +0x02000000,0xc32); +reg_write( DDR_REG_BASE +0x51826*4 +0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x51827*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x51828*4 +0x02000000,0x89d); +reg_write( DDR_REG_BASE +0x51829*4 +0x02000000,0x11); +reg_write( DDR_REG_BASE +0x5182a*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5182b*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5182c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5182d*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5182e*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5182f*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51830*4 +0x02000000,0x86); +reg_write( DDR_REG_BASE +0x51831*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51832*4 +0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x51833*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51834*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51835*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x51836*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51837*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51838*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51839*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x5183a*4 +0x02000000,0x3f9b); +reg_write( DDR_REG_BASE +0x5183b*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5183c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5183d*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x5183e*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x5183f*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51840*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51841*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51842*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51843*4 +0x02000000,0xb8c2); +reg_write( DDR_REG_BASE +0x51844*4 +0x02000000,0x823); +reg_write( DDR_REG_BASE +0x51845*4 +0x02000000,0x90); +reg_write( DDR_REG_BASE +0x51846*4 +0x02000000,0x827); +reg_write( DDR_REG_BASE +0x51847*4 +0x02000000,0xf1); +reg_write( DDR_REG_BASE +0x51848*4 +0x02000000,0x228b); +reg_write( DDR_REG_BASE +0x51849*4 +0x02000000,0x803e); +reg_write( DDR_REG_BASE +0x5184a*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x5184b*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5184c*4 +0x02000000,0x42c); +reg_write( DDR_REG_BASE +0x5184d*4 +0x02000000,0xce0a); +reg_write( DDR_REG_BASE +0x5184e*4 +0x02000000,0x705c); +reg_write( DDR_REG_BASE +0x5184f*4 +0x02000000,0x5016); +reg_write( DDR_REG_BASE +0x51850*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x51851*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51852*4 +0x02000000,0x444); +reg_write( DDR_REG_BASE +0x51853*4 +0x02000000,0xce10); +reg_write( DDR_REG_BASE +0x51854*4 +0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x51855*4 +0x02000000,0xce09); +reg_write( DDR_REG_BASE +0x51856*4 +0x02000000,0x5016); +reg_write( DDR_REG_BASE +0x51857*4 +0x02000000,0xce0f); +reg_write( DDR_REG_BASE +0x51858*4 +0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x51859*4 +0x02000000,0x228b); +reg_write( DDR_REG_BASE +0x5185a*4 +0x02000000,0x803e); +reg_write( DDR_REG_BASE +0x5185b*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x5185c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5185d*4 +0x02000000,0x420); +reg_write( DDR_REG_BASE +0x5185e*4 +0x02000000,0xce07); +reg_write( DDR_REG_BASE +0x5185f*4 +0x02000000,0x705c); +reg_write( DDR_REG_BASE +0x51860*4 +0x02000000,0x5016); +reg_write( DDR_REG_BASE +0x51861*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x51862*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51863*4 +0x02000000,0x438); +reg_write( DDR_REG_BASE +0x51864*4 +0x02000000,0xce0d); +reg_write( DDR_REG_BASE +0x51865*4 +0x02000000,0x705c); +reg_write( DDR_REG_BASE +0x51866*4 +0x02000000,0x5034); +reg_write( DDR_REG_BASE +0x51867*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51868*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x51869*4 +0x02000000,0xcfe); +reg_write( DDR_REG_BASE +0x5186a*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5186b*4 +0x02000000,0x90c0); +reg_write( DDR_REG_BASE +0x5186c*4 +0x02000000,0xc8a); +reg_write( DDR_REG_BASE +0x5186d*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5186e*4 +0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x5186f*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51870*4 +0x02000000,0xbea0); +reg_write( DDR_REG_BASE +0x51871*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51872*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51873*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51874*4 +0x02000000,0xfe86); +reg_write( DDR_REG_BASE +0x51875*4 +0x02000000,0xb1c0); +reg_write( DDR_REG_BASE +0x51876*4 +0x02000000,0xbd2); +reg_write( DDR_REG_BASE +0x51877*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51878*4 +0x02000000,0xbd6); +reg_write( DDR_REG_BASE +0x51879*4 +0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x5187a*4 +0x02000000,0x942); +reg_write( DDR_REG_BASE +0x5187b*4 +0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x5187c*4 +0x02000000,0xd72); +reg_write( DDR_REG_BASE +0x5187d*4 +0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x5187e*4 +0x02000000,0xca06); +reg_write( DDR_REG_BASE +0x5187f*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51880*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x51881*4 +0x02000000,0xf036); +reg_write( DDR_REG_BASE +0x51882*4 +0x02000000,0x265a); +reg_write( DDR_REG_BASE +0x51883*4 +0x02000000,0x1483); +reg_write( DDR_REG_BASE +0x51884*4 +0x02000000,0x657c); +reg_write( DDR_REG_BASE +0x51885*4 +0x02000000,0xb441); +reg_write( DDR_REG_BASE +0x51886*4 +0x02000000,0xf02d); +reg_write( DDR_REG_BASE +0x51887*4 +0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x51888*4 +0x02000000,0x1f81); +reg_write( DDR_REG_BASE +0x51889*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5188a*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x5188b*4 +0x02000000,0x79e5); +reg_write( DDR_REG_BASE +0x5188c*4 +0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x5188d*4 +0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x5188e*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x5188f*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51890*4 +0x02000000,0x140); +reg_write( DDR_REG_BASE +0x51891*4 +0x02000000,0x9120); +reg_write( DDR_REG_BASE +0x51892*4 +0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x51893*4 +0x02000000,0x3047); +reg_write( DDR_REG_BASE +0x51894*4 +0x02000000,0xf11); +reg_write( DDR_REG_BASE +0x51895*4 +0x02000000,0x17a1); +reg_write( DDR_REG_BASE +0x51896*4 +0x02000000,0x716d); +reg_write( DDR_REG_BASE +0x51897*4 +0x02000000,0x8c22); +reg_write( DDR_REG_BASE +0x51898*4 +0x02000000,0x210f); +reg_write( DDR_REG_BASE +0x51899*4 +0x02000000,0x3c1); +reg_write( DDR_REG_BASE +0x5189a*4 +0x02000000,0xac22); +reg_write( DDR_REG_BASE +0x5189b*4 +0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x5189c*4 +0x02000000,0x8c23); +reg_write( DDR_REG_BASE +0x5189d*4 +0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x5189e*4 +0x02000000,0x37db); +reg_write( DDR_REG_BASE +0x5189f*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x518a0*4 +0x02000000,0xac23); +reg_write( DDR_REG_BASE +0x518a1*4 +0x02000000,0x792f); +reg_write( DDR_REG_BASE +0x518a2*4 +0x02000000,0x2314); +reg_write( DDR_REG_BASE +0x518a3*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x518a4*4 +0x02000000,0x61b9); +reg_write( DDR_REG_BASE +0x518a5*4 +0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x518a6*4 +0x02000000,0x32c0); +reg_write( DDR_REG_BASE +0x518a7*4 +0x02000000,0xa9e3); +reg_write( DDR_REG_BASE +0x518a8*4 +0x02000000,0xb11); +reg_write( DDR_REG_BASE +0x518a9*4 +0x02000000,0x3010); +reg_write( DDR_REG_BASE +0x518aa*4 +0x02000000,0x2342); +reg_write( DDR_REG_BASE +0x518ab*4 +0x02000000,0x305b); +reg_write( DDR_REG_BASE +0x518ac*4 +0x02000000,0xbfd); +reg_write( DDR_REG_BASE +0x518ad*4 +0x02000000,0xb031); +reg_write( DDR_REG_BASE +0x518ae*4 +0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x518af*4 +0x02000000,0x3780); +reg_write( DDR_REG_BASE +0x518b0*4 +0x02000000,0x1902); +reg_write( DDR_REG_BASE +0x518b1*4 +0x02000000,0x782); +reg_write( DDR_REG_BASE +0x518b2*4 +0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x518b3*4 +0x02000000,0xfab); +reg_write( DDR_REG_BASE +0x518b4*4 +0x02000000,0x9214); +reg_write( DDR_REG_BASE +0x518b5*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x518b6*4 +0x02000000,0xe99); +reg_write( DDR_REG_BASE +0x518b7*4 +0x02000000,0x9024); +reg_write( DDR_REG_BASE +0x518b8*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x518b9*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x518ba*4 +0x02000000,0x708f); +reg_write( DDR_REG_BASE +0x518bb*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x518bc*4 +0x02000000,0x25); +reg_write( DDR_REG_BASE +0x518bd*4 +0x02000000,0xef28); +reg_write( DDR_REG_BASE +0x518be*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x518bf*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x518c0*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x518c1*4 +0x02000000,0x32); +reg_write( DDR_REG_BASE +0x518c2*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x518c3*4 +0x02000000,0x709b); +reg_write( DDR_REG_BASE +0x518c4*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x518c5*4 +0x02000000,0x66b); +reg_write( DDR_REG_BASE +0x518c6*4 +0x02000000,0x71cd); +reg_write( DDR_REG_BASE +0x518c7*4 +0x02000000,0xb8e3); +reg_write( DDR_REG_BASE +0x518c8*4 +0x02000000,0x26ca); +reg_write( DDR_REG_BASE +0x518c9*4 +0x02000000,0x10a1); +reg_write( DDR_REG_BASE +0x518ca*4 +0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x518cb*4 +0x02000000,0xf15); +reg_write( DDR_REG_BASE +0x518cc*4 +0x02000000,0x103e); +reg_write( DDR_REG_BASE +0x518cd*4 +0x02000000,0x212f); +reg_write( DDR_REG_BASE +0x518ce*4 +0x02000000,0x6c7); +reg_write( DDR_REG_BASE +0x518cf*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x518d0*4 +0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x518d1*4 +0x02000000,0x91a); +reg_write( DDR_REG_BASE +0x518d2*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x518d3*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x518d4*4 +0x02000000,0xf13); +reg_write( DDR_REG_BASE +0x518d5*4 +0x02000000,0x107e); +reg_write( DDR_REG_BASE +0x518d6*4 +0x02000000,0x212f); +reg_write( DDR_REG_BASE +0x518d7*4 +0x02000000,0x6c7); +reg_write( DDR_REG_BASE +0x518d8*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x518d9*4 +0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x518da*4 +0x02000000,0x906); +reg_write( DDR_REG_BASE +0x518db*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x518dc*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x518dd*4 +0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x518de*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x518df*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x518e0*4 +0x02000000,0x66b); +reg_write( DDR_REG_BASE +0x518e1*4 +0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x518e2*4 +0x02000000,0x8d3); +reg_write( DDR_REG_BASE +0x518e3*4 +0x02000000,0x86c5); +reg_write( DDR_REG_BASE +0x518e4*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x518e5*4 +0x02000000,0x708f); +reg_write( DDR_REG_BASE +0x518e6*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x518e7*4 +0x02000000,0x58); +reg_write( DDR_REG_BASE +0x518e8*4 +0x02000000,0xef28); +reg_write( DDR_REG_BASE +0x518e9*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x518ea*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x518eb*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x518ec*4 +0x02000000,0x65); +reg_write( DDR_REG_BASE +0x518ed*4 +0x02000000,0x71cd); +reg_write( DDR_REG_BASE +0x518ee*4 +0x02000000,0xb8e3); +reg_write( DDR_REG_BASE +0x518ef*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x518f0*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x518f1*4 +0x02000000,0x66b); +reg_write( DDR_REG_BASE +0x518f2*4 +0x02000000,0x1002); +reg_write( DDR_REG_BASE +0x518f3*4 +0x02000000,0x9b); +reg_write( DDR_REG_BASE +0x518f4*4 +0x02000000,0x26ca); +reg_write( DDR_REG_BASE +0x518f5*4 +0x02000000,0x10a1); +reg_write( DDR_REG_BASE +0x518f6*4 +0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x518f7*4 +0x02000000,0xf15); +reg_write( DDR_REG_BASE +0x518f8*4 +0x02000000,0x103e); +reg_write( DDR_REG_BASE +0x518f9*4 +0x02000000,0x212f); +reg_write( DDR_REG_BASE +0x518fa*4 +0x02000000,0x6c7); +reg_write( DDR_REG_BASE +0x518fb*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x518fc*4 +0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x518fd*4 +0x02000000,0x8c2); +reg_write( DDR_REG_BASE +0x518fe*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x518ff*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x51900*4 +0x02000000,0xf13); +reg_write( DDR_REG_BASE +0x51901*4 +0x02000000,0x107e); +reg_write( DDR_REG_BASE +0x51902*4 +0x02000000,0x212f); +reg_write( DDR_REG_BASE +0x51903*4 +0x02000000,0x6c7); +reg_write( DDR_REG_BASE +0x51904*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51905*4 +0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x51906*4 +0x02000000,0x8ae); +reg_write( DDR_REG_BASE +0x51907*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51908*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x51909*4 +0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x5190a*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5190b*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5190c*4 +0x02000000,0x66b); +reg_write( DDR_REG_BASE +0x5190d*4 +0x02000000,0x8803); +reg_write( DDR_REG_BASE +0x5190e*4 +0x02000000,0x8d3); +reg_write( DDR_REG_BASE +0x5190f*4 +0x02000000,0x86c5); +reg_write( DDR_REG_BASE +0x51910*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51911*4 +0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x51912*4 +0x02000000,0x33f); +reg_write( DDR_REG_BASE +0x51913*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51914*4 +0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x51915*4 +0x02000000,0xaba); +reg_write( DDR_REG_BASE +0x51916*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51917*4 +0x02000000,0xd80d); +reg_write( DDR_REG_BASE +0x51918*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51919*4 +0x02000000,0xcd6); +reg_write( DDR_REG_BASE +0x5191a*4 +0x02000000,0x140); +reg_write( DDR_REG_BASE +0x5191b*4 +0x02000000,0xd62); +reg_write( DDR_REG_BASE +0x5191c*4 +0x02000000,0xfe8f); +reg_write( DDR_REG_BASE +0x5191d*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5191e*4 +0x02000000,0xaa6); +reg_write( DDR_REG_BASE +0x5191f*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51920*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x51921*4 +0x02000000,0x1003); +reg_write( DDR_REG_BASE +0x51922*4 +0x02000000,0xca06); +reg_write( DDR_REG_BASE +0x51923*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x51924*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x51925*4 +0x02000000,0xf01a); +reg_write( DDR_REG_BASE +0x51926*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51927*4 +0x02000000,0xf015); +reg_write( DDR_REG_BASE +0x51928*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x51929*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x5192a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5192b*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x5192c*4 +0x02000000,0x2300); +reg_write( DDR_REG_BASE +0x5192d*4 +0x02000000,0x1f8c); +reg_write( DDR_REG_BASE +0x5192e*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5192f*4 +0x02000000,0x1b98); +reg_write( DDR_REG_BASE +0x51930*4 +0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x51931*4 +0x02000000,0x7945); +reg_write( DDR_REG_BASE +0x51932*4 +0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x51933*4 +0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x51934*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51935*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51936*4 +0x02000000,0x140); +reg_write( DDR_REG_BASE +0x51937*4 +0x02000000,0x91c0); +reg_write( DDR_REG_BASE +0x51938*4 +0x02000000,0xacc0); +reg_write( DDR_REG_BASE +0x51939*4 +0x02000000,0xb140); +reg_write( DDR_REG_BASE +0x5193a*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x5193b*4 +0x02000000,0xadd); +reg_write( DDR_REG_BASE +0x5193c*4 +0x02000000,0x8214); +reg_write( DDR_REG_BASE +0x5193d*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x5193e*4 +0x02000000,0xbd1); +reg_write( DDR_REG_BASE +0x5193f*4 +0x02000000,0x8024); +reg_write( DDR_REG_BASE +0x51940*4 +0x02000000,0x2516); +reg_write( DDR_REG_BASE +0x51941*4 +0x02000000,0x10cb); +reg_write( DDR_REG_BASE +0x51942*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51943*4 +0x02000000,0x853); +reg_write( DDR_REG_BASE +0x51944*4 +0x02000000,0x1be); +reg_write( DDR_REG_BASE +0x51945*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51946*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51947*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51948*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x51949*4 +0x02000000,0xae00); +reg_write( DDR_REG_BASE +0x5194a*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x5194b*4 +0x02000000,0x83d); +reg_write( DDR_REG_BASE +0x5194c*4 +0x02000000,0x95); +reg_write( DDR_REG_BASE +0x5194d*4 +0x02000000,0xe814); +reg_write( DDR_REG_BASE +0x5194e*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5194f*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51950*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51951*4 +0x02000000,0x58); +reg_write( DDR_REG_BASE +0x51952*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51953*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51954*4 +0x02000000,0xf20a); +reg_write( DDR_REG_BASE +0x51955*4 +0x02000000,0xf877); +reg_write( DDR_REG_BASE +0x51956*4 +0x02000000,0xc9a); +reg_write( DDR_REG_BASE +0x51957*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x51958*4 +0x02000000,0x1e01); +reg_write( DDR_REG_BASE +0x51959*4 +0x02000000,0x1003); +reg_write( DDR_REG_BASE +0x5195a*4 +0x02000000,0xa2e); +reg_write( DDR_REG_BASE +0x5195b*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5195c*4 +0x02000000,0x760c); +reg_write( DDR_REG_BASE +0x5195d*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x5195e*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5195f*4 +0x02000000,0xf1eb); +reg_write( DDR_REG_BASE +0x51960*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51961*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51962*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51963*4 +0x02000000,0x25); +reg_write( DDR_REG_BASE +0x51964*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51965*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51966*4 +0x02000000,0xf5ef); +reg_write( DDR_REG_BASE +0x51967*4 +0x02000000,0xf1f8); +reg_write( DDR_REG_BASE +0x51968*4 +0x02000000,0xbea); +reg_write( DDR_REG_BASE +0x51969*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5196a*4 +0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x5196b*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x5196c*4 +0x02000000,0xb8e5); +reg_write( DDR_REG_BASE +0x5196d*4 +0x02000000,0xf299); +reg_write( DDR_REG_BASE +0x5196e*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x5196f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51970*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x51971*4 +0x02000000,0xf08d); +reg_write( DDR_REG_BASE +0x51972*4 +0x02000000,0xe809); +reg_write( DDR_REG_BASE +0x51973*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51974*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51975*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51976*4 +0x02000000,0x58); +reg_write( DDR_REG_BASE +0x51977*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51978*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51979*4 +0x02000000,0xf40a); +reg_write( DDR_REG_BASE +0x5197a*4 +0x02000000,0xf082); +reg_write( DDR_REG_BASE +0x5197b*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5197c*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5197d*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5197e*4 +0x02000000,0x25); +reg_write( DDR_REG_BASE +0x5197f*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51980*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51981*4 +0x02000000,0xf27c); +reg_write( DDR_REG_BASE +0x51982*4 +0x02000000,0xf860); +reg_write( DDR_REG_BASE +0x51983*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51984*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x51985*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51986*4 +0x02000000,0xba6); +reg_write( DDR_REG_BASE +0x51987*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51988*4 +0x02000000,0x1e01); +reg_write( DDR_REG_BASE +0x51989*4 +0x02000000,0x1003); +reg_write( DDR_REG_BASE +0x5198a*4 +0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x5198b*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5198c*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x5198d*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5198e*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5198f*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x51990*4 +0x02000000,0x641); +reg_write( DDR_REG_BASE +0x51991*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x51992*4 +0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x51993*4 +0x02000000,0x1f8d); +reg_write( DDR_REG_BASE +0x51994*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51995*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51996*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x51997*4 +0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x51998*4 +0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x51999*4 +0x02000000,0x1f8f); +reg_write( DDR_REG_BASE +0x5199a*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x5199b*4 +0x02000000,0x86); +reg_write( DDR_REG_BASE +0x5199c*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x5199d*4 +0x02000000,0x6638); +reg_write( DDR_REG_BASE +0x5199e*4 +0x02000000,0x8816); +reg_write( DDR_REG_BASE +0x5199f*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x519a0*4 +0x02000000,0xaf2); +reg_write( DDR_REG_BASE +0x519a1*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x519a2*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x519a3*4 +0x02000000,0x97e0); +reg_write( DDR_REG_BASE +0x519a4*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x519a5*4 +0x02000000,0x802); +reg_write( DDR_REG_BASE +0x519a6*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x519a7*4 +0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x519a8*4 +0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x519a9*4 +0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x519aa*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x519ab*4 +0x02000000,0xfe86); +reg_write( DDR_REG_BASE +0x519ac*4 +0x02000000,0x2746); +reg_write( DDR_REG_BASE +0x519ad*4 +0x02000000,0x134f); +reg_write( DDR_REG_BASE +0x519ae*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x519af*4 +0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x519b0*4 +0x02000000,0x258a); +reg_write( DDR_REG_BASE +0x519b1*4 +0x02000000,0x1fc7); +reg_write( DDR_REG_BASE +0x519b2*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x519b3*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x519b4*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x519b5*4 +0x02000000,0xb8e6); +reg_write( DDR_REG_BASE +0x519b6*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x519b7*4 +0x02000000,0x25ca); +reg_write( DDR_REG_BASE +0x519b8*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x519b9*4 +0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x519ba*4 +0x02000000,0xd4e); +reg_write( DDR_REG_BASE +0x519bb*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x519bc*4 +0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x519bd*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x519be*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x519bf*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x519c0*4 +0x02000000,0x1d); +reg_write( DDR_REG_BASE +0x519c1*4 +0x02000000,0x86b); +reg_write( DDR_REG_BASE +0x519c2*4 +0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x519c3*4 +0x02000000,0xbf82); +reg_write( DDR_REG_BASE +0x519c4*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x519c5*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x519c6*4 +0x02000000,0x8f); +reg_write( DDR_REG_BASE +0x519c7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x519c8*4 +0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x519c9*4 +0x02000000,0xf838); +reg_write( DDR_REG_BASE +0x519ca*4 +0x02000000,0xd2e); +reg_write( DDR_REG_BASE +0x519cb*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x519cc*4 +0x02000000,0xdb40); +reg_write( DDR_REG_BASE +0x519cd*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x519ce*4 +0x02000000,0x90); +reg_write( DDR_REG_BASE +0x519cf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x519d0*4 +0x02000000,0xf834); +reg_write( DDR_REG_BASE +0x519d1*4 +0x02000000,0xd22); +reg_write( DDR_REG_BASE +0x519d2*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x519d3*4 +0x02000000,0xdb30); +reg_write( DDR_REG_BASE +0x519d4*4 +0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x519d5*4 +0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x519d6*4 +0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x519d7*4 +0x02000000,0xd16); +reg_write( DDR_REG_BASE +0x519d8*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x519d9*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x519da*4 +0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x519db*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x519dc*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x519dd*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x519de*4 +0x02000000,0x1f); +reg_write( DDR_REG_BASE +0x519df*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x519e0*4 +0x02000000,0x925); +reg_write( DDR_REG_BASE +0x519e1*4 +0x02000000,0xe); +reg_write( DDR_REG_BASE +0x519e2*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x519e3*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x519e4*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x519e5*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x519e6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x519e7*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x519e8*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x519e9*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x519ea*4 +0x02000000,0xfe86); +reg_write( DDR_REG_BASE +0x519eb*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x519ec*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x519ed*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x519ee*4 +0x02000000,0x86); +reg_write( DDR_REG_BASE +0x519ef*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x519f0*4 +0x02000000,0xb8a0); +reg_write( DDR_REG_BASE +0x519f1*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x519f2*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x519f3*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x519f4*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x519f5*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x519f6*4 +0x02000000,0x8cb); +reg_write( DDR_REG_BASE +0x519f7*4 +0x02000000,0x8134); +reg_write( DDR_REG_BASE +0x519f8*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x519f9*4 +0x02000000,0x8f2); +reg_write( DDR_REG_BASE +0x519fa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x519fb*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x519fc*4 +0x02000000,0x68a1); +reg_write( DDR_REG_BASE +0x519fd*4 +0x02000000,0x78af); +reg_write( DDR_REG_BASE +0x519fe*4 +0x02000000,0x7114); +reg_write( DDR_REG_BASE +0x519ff*4 +0x02000000,0x6e8); +reg_write( DDR_REG_BASE +0x51a00*4 +0x02000000,0xffee); +reg_write( DDR_REG_BASE +0x51a01*4 +0x02000000,0xaea0); +reg_write( DDR_REG_BASE +0x51a02*4 +0x02000000,0xab6); +reg_write( DDR_REG_BASE +0x51a03*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51a04*4 +0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x51a05*4 +0x02000000,0xc76); +reg_write( DDR_REG_BASE +0x51a06*4 +0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x51a07*4 +0x02000000,0xca06); +reg_write( DDR_REG_BASE +0x51a08*4 +0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x51a09*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51a0a*4 +0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x51a0b*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x51a0c*4 +0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x51a0d*4 +0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x51a0e*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51a0f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a10*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x51a11*4 +0x02000000,0x7965); +reg_write( DDR_REG_BASE +0x51a12*4 +0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x51a13*4 +0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x51a14*4 +0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x51a15*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51a16*4 +0x02000000,0x140); +reg_write( DDR_REG_BASE +0x51a17*4 +0x02000000,0x2332); +reg_write( DDR_REG_BASE +0x51a18*4 +0x02000000,0x1f81); +reg_write( DDR_REG_BASE +0x51a19*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a1a*4 +0x02000000,0x1b98); +reg_write( DDR_REG_BASE +0x51a1b*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x51a1c*4 +0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x51a1d*4 +0x02000000,0xb420); +reg_write( DDR_REG_BASE +0x51a1e*4 +0x02000000,0xbdf); +reg_write( DDR_REG_BASE +0x51a1f*4 +0x02000000,0x8214); +reg_write( DDR_REG_BASE +0x51a20*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x51a21*4 +0x02000000,0xad7); +reg_write( DDR_REG_BASE +0x51a22*4 +0x02000000,0x8024); +reg_write( DDR_REG_BASE +0x51a23*4 +0x02000000,0x2316); +reg_write( DDR_REG_BASE +0x51a24*4 +0x02000000,0x308b); +reg_write( DDR_REG_BASE +0x51a25*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51a26*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51a27*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51a28*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x51a29*4 +0x02000000,0xe032); +reg_write( DDR_REG_BASE +0x51a2a*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x51a2b*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x51a2c*4 +0x02000000,0xa4e); +reg_write( DDR_REG_BASE +0x51a2d*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51a2e*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51a2f*4 +0x02000000,0x86e); +reg_write( DDR_REG_BASE +0x51a30*4 +0x02000000,0x80); +reg_write( DDR_REG_BASE +0x51a31*4 +0x02000000,0x912); +reg_write( DDR_REG_BASE +0x51a32*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x51a33*4 +0x02000000,0xd807); +reg_write( DDR_REG_BASE +0x51a34*4 +0x02000000,0x23ab); +reg_write( DDR_REG_BASE +0x51a35*4 +0x02000000,0x30c4); +reg_write( DDR_REG_BASE +0x51a36*4 +0x02000000,0x7fff); +reg_write( DDR_REG_BASE +0x51a37*4 +0x02000000,0xf000); +reg_write( DDR_REG_BASE +0x51a38*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x51a39*4 +0x02000000,0xd82); +reg_write( DDR_REG_BASE +0x51a3a*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51a3b*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x51a3c*4 +0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x51a3d*4 +0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x51a3e*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51a3f*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x51a40*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51a41*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51a42*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x51a43*4 +0x02000000,0xd3e); +reg_write( DDR_REG_BASE +0x51a44*4 +0x02000000,0xfe8f); +reg_write( DDR_REG_BASE +0x51a45*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x51a46*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x51a47*4 +0x02000000,0xa2e); +reg_write( DDR_REG_BASE +0x51a48*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51a49*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51a4a*4 +0x02000000,0xb02); +reg_write( DDR_REG_BASE +0x51a4b*4 +0x02000000,0xfe8f); +reg_write( DDR_REG_BASE +0x51a4c*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x51a4d*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51a4e*4 +0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x51a4f*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x51a50*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51a51*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51a52*4 +0x02000000,0x9500); +reg_write( DDR_REG_BASE +0x51a53*4 +0x02000000,0xb8a1); +reg_write( DDR_REG_BASE +0x51a54*4 +0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x51a55*4 +0x02000000,0xf52); +reg_write( DDR_REG_BASE +0x51a56*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x51a57*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x51a58*4 +0x02000000,0xd81f); +reg_write( DDR_REG_BASE +0x51a59*4 +0x02000000,0xf4a); +reg_write( DDR_REG_BASE +0x51a5a*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x51a5b*4 +0x02000000,0x1df6); +reg_write( DDR_REG_BASE +0x51a5c*4 +0x02000000,0x105d); +reg_write( DDR_REG_BASE +0x51a5d*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x51a5e*4 +0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x51a5f*4 +0x02000000,0xf3e); +reg_write( DDR_REG_BASE +0x51a60*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x51a61*4 +0x02000000,0xd81f); +reg_write( DDR_REG_BASE +0x51a62*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x51a63*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51a64*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x51a65*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x51a66*4 +0x02000000,0xf2e); +reg_write( DDR_REG_BASE +0x51a67*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x51a68*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x51a69*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x51a6a*4 +0x02000000,0x150a); +reg_write( DDR_REG_BASE +0x51a6b*4 +0x02000000,0x9700); +reg_write( DDR_REG_BASE +0x51a6c*4 +0x02000000,0xb881); +reg_write( DDR_REG_BASE +0x51a6d*4 +0x02000000,0x1d0a); +reg_write( DDR_REG_BASE +0x51a6e*4 +0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x51a6f*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x51a70*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x51a71*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51a72*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51a73*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a74*4 +0x02000000,0x12); +reg_write( DDR_REG_BASE +0x51a75*4 +0x02000000,0x218c); +reg_write( DDR_REG_BASE +0x51a76*4 +0x02000000,0x8203); +reg_write( DDR_REG_BASE +0x51a77*4 +0x02000000,0x884); +reg_write( DDR_REG_BASE +0x51a78*4 +0x02000000,0xce); +reg_write( DDR_REG_BASE +0x51a79*4 +0x02000000,0x80e); +reg_write( DDR_REG_BASE +0x51a7a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a7b*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x51a7c*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51a7d*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51a7e*4 +0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x51a7f*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51a80*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51a81*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a82*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51a83*4 +0x02000000,0x81b); +reg_write( DDR_REG_BASE +0x51a84*4 +0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x51a85*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51a86*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x51a87*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x51a88*4 +0x02000000,0xe036); +reg_write( DDR_REG_BASE +0x51a89*4 +0x02000000,0xeea); +reg_write( DDR_REG_BASE +0x51a8a*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x51a8b*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x51a8c*4 +0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x51a8d*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x51a8e*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x51a8f*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x51a90*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51a91*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51a92*4 +0x02000000,0xf2); +reg_write( DDR_REG_BASE +0x51a93*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x51a94*4 +0x02000000,0x45); +reg_write( DDR_REG_BASE +0x51a95*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x51a96*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x51a97*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51a98*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51a99*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51a9a*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51a9b*4 +0x02000000,0xc1a8); +reg_write( DDR_REG_BASE +0x51a9c*4 +0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x51a9d*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51a9e*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51a9f*4 +0x02000000,0x669); +reg_write( DDR_REG_BASE +0x51aa0*4 +0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x51aa1*4 +0x02000000,0xc146); +reg_write( DDR_REG_BASE +0x51aa2*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51aa3*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x51aa4*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51aa5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51aa6*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x51aa7*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51aa8*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51aa9*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51aaa*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x51aab*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51aac*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x51aad*4 +0x02000000,0xeb6); +reg_write( DDR_REG_BASE +0x51aae*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51aaf*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51ab0*4 +0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x51ab1*4 +0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x51ab2*4 +0x02000000,0xd981); +reg_write( DDR_REG_BASE +0x51ab3*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x51ab4*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51ab5*4 +0x02000000,0xb98e); +reg_write( DDR_REG_BASE +0x51ab6*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x51ab7*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51ab8*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51ab9*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51aba*4 +0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x51abb*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51abc*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51abd*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51abe*4 +0x02000000,0xf2a); +reg_write( DDR_REG_BASE +0x51abf*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51ac0*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51ac1*4 +0x02000000,0x8da); +reg_write( DDR_REG_BASE +0x51ac2*4 +0x02000000,0xff0f); +reg_write( DDR_REG_BASE +0x51ac3*4 +0x02000000,0x8e2); +reg_write( DDR_REG_BASE +0x51ac4*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51ac5*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x51ac6*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51ac7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51ac8*4 +0x02000000,0x2710); +reg_write( DDR_REG_BASE +0x51ac9*4 +0x02000000,0xee2); +reg_write( DDR_REG_BASE +0x51aca*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x51acb*4 +0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x51acc*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51acd*4 +0x02000000,0x900f); +reg_write( DDR_REG_BASE +0x51ace*4 +0x02000000,0xe0c0); +reg_write( DDR_REG_BASE +0x51acf*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x51ad0*4 +0x02000000,0x205); +reg_write( DDR_REG_BASE +0x51ad1*4 +0x02000000,0xb0a5); +reg_write( DDR_REG_BASE +0x51ad2*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51ad3*4 +0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x51ad4*4 +0x02000000,0xe66); +reg_write( DDR_REG_BASE +0x51ad5*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51ad6*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51ad7*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51ad8*4 +0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x51ad9*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51ada*4 +0x02000000,0xb98e); +reg_write( DDR_REG_BASE +0x51adb*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x51adc*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x51add*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51ade*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51adf*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x51ae0*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x51ae1*4 +0x02000000,0xf42); +reg_write( DDR_REG_BASE +0x51ae2*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51ae3*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51ae4*4 +0x02000000,0x7fcf); +reg_write( DDR_REG_BASE +0x51ae5*4 +0x02000000,0xf8b8); +reg_write( DDR_REG_BASE +0x51ae6*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51ae7*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51ae8*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51ae9*4 +0x02000000,0xf32); +reg_write( DDR_REG_BASE +0x51aea*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51aeb*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51aec*4 +0x02000000,0xbec1); +reg_write( DDR_REG_BASE +0x51aed*4 +0x02000000,0xc645); +reg_write( DDR_REG_BASE +0x51aee*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51aef*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51af0*4 +0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x51af1*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51af2*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51af3*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x51af4*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51af5*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x51af6*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x51af7*4 +0x02000000,0xf16); +reg_write( DDR_REG_BASE +0x51af8*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51af9*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51afa*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51afb*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51afc*4 +0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x51afd*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51afe*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x51aff*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51b00*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51b01*4 +0x02000000,0xdb28); +reg_write( DDR_REG_BASE +0x51b02*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51b03*4 +0x02000000,0xefe); +reg_write( DDR_REG_BASE +0x51b04*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51b05*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51b06*4 +0x02000000,0x942); +reg_write( DDR_REG_BASE +0x51b07*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51b08*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51b09*4 +0x02000000,0xc104); +reg_write( DDR_REG_BASE +0x51b0a*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x51b0b*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51b0c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51b0d*4 +0x02000000,0x3100); +reg_write( DDR_REG_BASE +0x51b0e*4 +0x02000000,0x2014); +reg_write( DDR_REG_BASE +0x51b0f*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x51b10*4 +0x02000000,0x4968); +reg_write( DDR_REG_BASE +0x51b11*4 +0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x51b12*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51b13*4 +0x02000000,0xe030); +reg_write( DDR_REG_BASE +0x51b14*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x51b15*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x51b16*4 +0x02000000,0xe804); +reg_write( DDR_REG_BASE +0x51b17*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x51b18*4 +0x02000000,0x3441); +reg_write( DDR_REG_BASE +0x51b19*4 +0x02000000,0xf068); +reg_write( DDR_REG_BASE +0x51b1a*4 +0x02000000,0xf8a0); +reg_write( DDR_REG_BASE +0x51b1b*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51b1c*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51b1d*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51b1e*4 +0x02000000,0xec6); +reg_write( DDR_REG_BASE +0x51b1f*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51b20*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51b21*4 +0x02000000,0xf89a); +reg_write( DDR_REG_BASE +0x51b22*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51b23*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51b24*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x51b25*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x51b26*4 +0x02000000,0xeb6); +reg_write( DDR_REG_BASE +0x51b27*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51b28*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51b29*4 +0x02000000,0xf893); +reg_write( DDR_REG_BASE +0x51b2a*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x51b2b*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x51b2c*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51b2d*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51b2e*4 +0x02000000,0xea6); +reg_write( DDR_REG_BASE +0x51b2f*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51b30*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51b31*4 +0x02000000,0xf895); +reg_write( DDR_REG_BASE +0x51b32*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51b33*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51b34*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51b35*4 +0x02000000,0xe9a); +reg_write( DDR_REG_BASE +0x51b36*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51b37*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51b38*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x51b39*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51b3a*4 +0x02000000,0xf88d); +reg_write( DDR_REG_BASE +0x51b3b*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51b3c*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51b3d*4 +0x02000000,0xe8a); +reg_write( DDR_REG_BASE +0x51b3e*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51b3f*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51b40*4 +0x02000000,0xf887); +reg_write( DDR_REG_BASE +0x51b41*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x51b42*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x51b43*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51b44*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51b45*4 +0x02000000,0xe7a); +reg_write( DDR_REG_BASE +0x51b46*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51b47*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51b48*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x51b49*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x51b4a*4 +0x02000000,0xf882); +reg_write( DDR_REG_BASE +0x51b4b*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51b4c*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51b4d*4 +0x02000000,0xe6a); +reg_write( DDR_REG_BASE +0x51b4e*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51b4f*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51b50*4 +0x02000000,0xf885); +reg_write( DDR_REG_BASE +0x51b51*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51b52*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51b53*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51b54*4 +0x02000000,0xe5a); +reg_write( DDR_REG_BASE +0x51b55*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51b56*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51b57*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51b58*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51b59*4 +0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x51b5a*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51b5b*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51b5c*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x51b5d*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51b5e*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x51b5f*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x51b60*4 +0x02000000,0xe42); +reg_write( DDR_REG_BASE +0x51b61*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51b62*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51b63*4 +0x02000000,0xf876); +reg_write( DDR_REG_BASE +0x51b64*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x51b65*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x51b66*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51b67*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51b68*4 +0x02000000,0xe32); +reg_write( DDR_REG_BASE +0x51b69*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51b6a*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51b6b*4 +0x02000000,0xf878); +reg_write( DDR_REG_BASE +0x51b6c*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51b6d*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51b6e*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51b6f*4 +0x02000000,0xe26); +reg_write( DDR_REG_BASE +0x51b70*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51b71*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51b72*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51b73*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51b74*4 +0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x51b75*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51b76*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x51b77*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51b78*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51b79*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x51b7a*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51b7b*4 +0x02000000,0xe0e); +reg_write( DDR_REG_BASE +0x51b7c*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51b7d*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51b7e*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x51b7f*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x51b80*4 +0x02000000,0xf867); +reg_write( DDR_REG_BASE +0x51b81*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51b82*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51b83*4 +0x02000000,0xdfe); +reg_write( DDR_REG_BASE +0x51b84*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51b85*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51b86*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51b87*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x51b88*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51b89*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51b8a*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x51b8b*4 +0x02000000,0xc304); +reg_write( DDR_REG_BASE +0x51b8c*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51b8d*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x51b8e*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51b8f*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51b90*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51b91*4 +0x02000000,0xde2); +reg_write( DDR_REG_BASE +0x51b92*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51b93*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51b94*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x51b95*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51b96*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51b97*4 +0x02000000,0x2100); +reg_write( DDR_REG_BASE +0x51b98*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51b99*4 +0x02000000,0xf26d); +reg_write( DDR_REG_BASE +0x51b9a*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x51b9b*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51b9c*4 +0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x51b9d*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x51b9e*4 +0x02000000,0x4358); +reg_write( DDR_REG_BASE +0x51b9f*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51ba0*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51ba1*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51ba2*4 +0x02000000,0xdbe); +reg_write( DDR_REG_BASE +0x51ba3*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51ba4*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51ba5*4 +0x02000000,0xf858); +reg_write( DDR_REG_BASE +0x51ba6*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51ba7*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51ba8*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x51ba9*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x51baa*4 +0x02000000,0xdae); +reg_write( DDR_REG_BASE +0x51bab*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51bac*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51bad*4 +0x02000000,0xf84e); +reg_write( DDR_REG_BASE +0x51bae*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x51baf*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x51bb0*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51bb1*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51bb2*4 +0x02000000,0xd9e); +reg_write( DDR_REG_BASE +0x51bb3*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51bb4*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51bb5*4 +0x02000000,0xf847); +reg_write( DDR_REG_BASE +0x51bb6*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51bb7*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51bb8*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51bb9*4 +0x02000000,0xd92); +reg_write( DDR_REG_BASE +0x51bba*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51bbb*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51bbc*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x51bbd*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51bbe*4 +0x02000000,0xf84b); +reg_write( DDR_REG_BASE +0x51bbf*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51bc0*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51bc1*4 +0x02000000,0xd82); +reg_write( DDR_REG_BASE +0x51bc2*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51bc3*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51bc4*4 +0x02000000,0xf842); +reg_write( DDR_REG_BASE +0x51bc5*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x51bc6*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x51bc7*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51bc8*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51bc9*4 +0x02000000,0xd72); +reg_write( DDR_REG_BASE +0x51bca*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51bcb*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51bcc*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x51bcd*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x51bce*4 +0x02000000,0xf83d); +reg_write( DDR_REG_BASE +0x51bcf*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51bd0*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51bd1*4 +0x02000000,0xd62); +reg_write( DDR_REG_BASE +0x51bd2*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51bd3*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51bd4*4 +0x02000000,0xf837); +reg_write( DDR_REG_BASE +0x51bd5*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51bd6*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51bd7*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51bd8*4 +0x02000000,0xd52); +reg_write( DDR_REG_BASE +0x51bd9*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51bda*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51bdb*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51bdc*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51bdd*4 +0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x51bde*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51bdf*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51be0*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x51be1*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51be2*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x51be3*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x51be4*4 +0x02000000,0xd3a); +reg_write( DDR_REG_BASE +0x51be5*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51be6*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51be7*4 +0x02000000,0xf831); +reg_write( DDR_REG_BASE +0x51be8*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x51be9*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x51bea*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51beb*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51bec*4 +0x02000000,0xd2a); +reg_write( DDR_REG_BASE +0x51bed*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51bee*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51bef*4 +0x02000000,0xf82a); +reg_write( DDR_REG_BASE +0x51bf0*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51bf1*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51bf2*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51bf3*4 +0x02000000,0xd1e); +reg_write( DDR_REG_BASE +0x51bf4*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51bf5*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51bf6*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51bf7*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51bf8*4 +0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x51bf9*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51bfa*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x51bfb*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51bfc*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51bfd*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x51bfe*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51bff*4 +0x02000000,0xd06); +reg_write( DDR_REG_BASE +0x51c00*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51c01*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51c02*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x51c03*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x51c04*4 +0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x51c05*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x51c06*4 +0x02000000,0x3441); +reg_write( DDR_REG_BASE +0x51c07*4 +0x02000000,0xf821); +reg_write( DDR_REG_BASE +0x51c08*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x51c09*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51c0a*4 +0x02000000,0xcee); +reg_write( DDR_REG_BASE +0x51c0b*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51c0c*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51c0d*4 +0x02000000,0xc304); +reg_write( DDR_REG_BASE +0x51c0e*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51c0f*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51c10*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x51c11*4 +0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x51c12*4 +0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x51c13*4 +0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x51c14*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51c15*4 +0x02000000,0xcda); +reg_write( DDR_REG_BASE +0x51c16*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51c17*4 +0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x51c18*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51c19*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51c1a*4 +0x02000000,0xb98f); +reg_write( DDR_REG_BASE +0x51c1b*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x51c1c*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x51c1d*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x51c1e*4 +0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x51c1f*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51c20*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51c21*4 +0x02000000,0xcc2); +reg_write( DDR_REG_BASE +0x51c22*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51c23*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51c24*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51c25*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51c26*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x51c27*4 +0x02000000,0xdb30); +reg_write( DDR_REG_BASE +0x51c28*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51c29*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51c2a*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51c2b*4 +0x02000000,0xcae); +reg_write( DDR_REG_BASE +0x51c2c*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51c2d*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51c2e*4 +0x02000000,0xed6); +reg_write( DDR_REG_BASE +0x51c2f*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51c30*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51c31*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51c32*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x51c33*4 +0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x51c34*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51c35*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51c36*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x51c37*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51c38*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51c39*4 +0x02000000,0xc92); +reg_write( DDR_REG_BASE +0x51c3a*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51c3b*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x51c3c*4 +0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x51c3d*4 +0x02000000,0xc0a8); +reg_write( DDR_REG_BASE +0x51c3e*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x51c3f*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x51c40*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51c41*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51c42*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51c43*4 +0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x51c44*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x51c45*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x51c46*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51c47*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51c48*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51c49*4 +0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x51c4a*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x51c4b*4 +0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x51c4c*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51c4d*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51c4e*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51c4f*4 +0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x51c50*4 +0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x51c51*4 +0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x51c52*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51c53*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51c54*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51c55*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51c56*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51c57*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x51c58*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51c59*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51c5a*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51c5b*4 +0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x51c5c*4 +0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x51c5d*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x51c5e*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51c5f*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51c60*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51c61*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51c62*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51c63*4 +0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x51c64*4 +0x02000000,0x3103); +reg_write( DDR_REG_BASE +0x51c65*4 +0x02000000,0xc244); +reg_write( DDR_REG_BASE +0x51c66*4 +0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x51c67*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x51c68*4 +0x02000000,0xc088); +reg_write( DDR_REG_BASE +0x51c69*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51c6a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51c6b*4 +0x02000000,0x7f00); +reg_write( DDR_REG_BASE +0x51c6c*4 +0x02000000,0xda51); +reg_write( DDR_REG_BASE +0x51c6d*4 +0x02000000,0xe86); +reg_write( DDR_REG_BASE +0x51c6e*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x51c6f*4 +0x02000000,0xc345); +reg_write( DDR_REG_BASE +0x51c70*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51c71*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51c72*4 +0x02000000,0xe024); +reg_write( DDR_REG_BASE +0x51c73*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x51c74*4 +0x02000000,0xfc5); +reg_write( DDR_REG_BASE +0x51c75*4 +0x02000000,0x180c); +reg_write( DDR_REG_BASE +0x51c76*4 +0x02000000,0xfc5); +reg_write( DDR_REG_BASE +0x51c77*4 +0x02000000,0x18fe); +reg_write( DDR_REG_BASE +0x51c78*4 +0x02000000,0x8005); +reg_write( DDR_REG_BASE +0x51c79*4 +0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x51c7a*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x51c7b*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51c7c*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x51c7d*4 +0x02000000,0xe0b0); +reg_write( DDR_REG_BASE +0x51c7e*4 +0x02000000,0xd840); +reg_write( DDR_REG_BASE +0x51c7f*4 +0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x51c80*4 +0x02000000,0x3001); +reg_write( DDR_REG_BASE +0x51c81*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51c82*4 +0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x51c83*4 +0x02000000,0xc00); +reg_write( DDR_REG_BASE +0x51c84*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51c85*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51c86*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51c87*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51c88*4 +0x02000000,0xe030); +reg_write( DDR_REG_BASE +0x51c89*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x51c8a*4 +0x02000000,0xf06a); +reg_write( DDR_REG_BASE +0x51c8b*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x51c8c*4 +0x02000000,0x8cf); +reg_write( DDR_REG_BASE +0x51c8d*4 +0x02000000,0x36e); +reg_write( DDR_REG_BASE +0x51c8e*4 +0x02000000,0x7eaf); +reg_write( DDR_REG_BASE +0x51c8f*4 +0x02000000,0xc203); +reg_write( DDR_REG_BASE +0x51c90*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x51c91*4 +0x02000000,0x80e); +reg_write( DDR_REG_BASE +0x51c92*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51c93*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51c94*4 +0x02000000,0xc203); +reg_write( DDR_REG_BASE +0x51c95*4 +0x02000000,0xc306); +reg_write( DDR_REG_BASE +0x51c96*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51c97*4 +0x02000000,0xf96); +reg_write( DDR_REG_BASE +0x51c98*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51c99*4 +0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x51c9a*4 +0x02000000,0xc103); +reg_write( DDR_REG_BASE +0x51c9b*4 +0x02000000,0xc204); +reg_write( DDR_REG_BASE +0x51c9c*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x51c9d*4 +0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x51c9e*4 +0x02000000,0xd46); +reg_write( DDR_REG_BASE +0x51c9f*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51ca0*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x51ca1*4 +0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x51ca2*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51ca3*4 +0x02000000,0xe812); +reg_write( DDR_REG_BASE +0x51ca4*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51ca5*4 +0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x51ca6*4 +0x02000000,0xb1); +reg_write( DDR_REG_BASE +0x51ca7*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x51ca8*4 +0x02000000,0xc103); +reg_write( DDR_REG_BASE +0x51ca9*4 +0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x51caa*4 +0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x51cab*4 +0x02000000,0xc103); +reg_write( DDR_REG_BASE +0x51cac*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x51cad*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51cae*4 +0x02000000,0xd1e); +reg_write( DDR_REG_BASE +0x51caf*4 +0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x51cb0*4 +0x02000000,0xc103); +reg_write( DDR_REG_BASE +0x51cb1*4 +0x02000000,0xe6a); +reg_write( DDR_REG_BASE +0x51cb2*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51cb3*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x51cb4*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51cb5*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51cb6*4 +0x02000000,0x669); +reg_write( DDR_REG_BASE +0x51cb7*4 +0x02000000,0x88e0); +reg_write( DDR_REG_BASE +0x51cb8*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x51cb9*4 +0x02000000,0x8b); +reg_write( DDR_REG_BASE +0x51cba*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x51cbb*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51cbc*4 +0x02000000,0xffe); +reg_write( DDR_REG_BASE +0x51cbd*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51cbe*4 +0x02000000,0xda08); +reg_write( DDR_REG_BASE +0x51cbf*4 +0x02000000,0x2340); +reg_write( DDR_REG_BASE +0x51cc0*4 +0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x51cc1*4 +0x02000000,0x79e2); +reg_write( DDR_REG_BASE +0x51cc2*4 +0x02000000,0x7829); +reg_write( DDR_REG_BASE +0x51cc3*4 +0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x51cc4*4 +0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x51cc5*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51cc6*4 +0x02000000,0xf01f); +reg_write( DDR_REG_BASE +0x51cc7*4 +0x02000000,0xdc41); +reg_write( DDR_REG_BASE +0x51cc8*4 +0x02000000,0x7c2a); +reg_write( DDR_REG_BASE +0x51cc9*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x51cca*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51ccb*4 +0x02000000,0x6dc); +reg_write( DDR_REG_BASE +0x51ccc*4 +0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x51ccd*4 +0x02000000,0x2432); +reg_write( DDR_REG_BASE +0x51cce*4 +0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x51ccf*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51cd0*4 +0x02000000,0x71b); +reg_write( DDR_REG_BASE +0x51cd1*4 +0x02000000,0xe00f); +reg_write( DDR_REG_BASE +0x51cd2*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51cd3*4 +0x02000000,0x7c14); +reg_write( DDR_REG_BASE +0x51cd4*4 +0x02000000,0xc088); +reg_write( DDR_REG_BASE +0x51cd5*4 +0x02000000,0x7834); +reg_write( DDR_REG_BASE +0x51cd6*4 +0x02000000,0x644f); +reg_write( DDR_REG_BASE +0x51cd7*4 +0x02000000,0x8820); +reg_write( DDR_REG_BASE +0x51cd8*4 +0x02000000,0x629a); +reg_write( DDR_REG_BASE +0x51cd9*4 +0x02000000,0x2108); +reg_write( DDR_REG_BASE +0x51cda*4 +0x02000000,0x3c1); +reg_write( DDR_REG_BASE +0x51cdb*4 +0x02000000,0xa820); +reg_write( DDR_REG_BASE +0x51cdc*4 +0x02000000,0x8a21); +reg_write( DDR_REG_BASE +0x51cdd*4 +0x02000000,0x8841); +reg_write( DDR_REG_BASE +0x51cde*4 +0x02000000,0x2209); +reg_write( DDR_REG_BASE +0x51cdf*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x51ce0*4 +0x02000000,0xa841); +reg_write( DDR_REG_BASE +0x51ce1*4 +0x02000000,0x49f0); +reg_write( DDR_REG_BASE +0x51ce2*4 +0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x51ce3*4 +0x02000000,0x2009); +reg_write( DDR_REG_BASE +0x51ce4*4 +0x02000000,0x780); +reg_write( DDR_REG_BASE +0x51ce5*4 +0x02000000,0x212f); +reg_write( DDR_REG_BASE +0x51ce6*4 +0x02000000,0x2c7); +reg_write( DDR_REG_BASE +0x51ce7*4 +0x02000000,0x9c3); +reg_write( DDR_REG_BASE +0x51ce8*4 +0x02000000,0x80e4); +reg_write( DDR_REG_BASE +0x51ce9*4 +0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x51cea*4 +0x02000000,0x3007); +reg_write( DDR_REG_BASE +0x51ceb*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x51cec*4 +0x02000000,0xbfa); +reg_write( DDR_REG_BASE +0x51ced*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51cee*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51cef*4 +0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x51cf0*4 +0x02000000,0x2609); +reg_write( DDR_REG_BASE +0x51cf1*4 +0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x51cf2*4 +0x02000000,0xa821); +reg_write( DDR_REG_BASE +0x51cf3*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x51cf4*4 +0x02000000,0xd2f); +reg_write( DDR_REG_BASE +0x51cf5*4 +0x02000000,0x9094); +reg_write( DDR_REG_BASE +0x51cf6*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51cf7*4 +0x02000000,0x89b); +reg_write( DDR_REG_BASE +0x51cf8*4 +0x02000000,0xb0); +reg_write( DDR_REG_BASE +0x51cf9*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x51cfa*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51cfb*4 +0x02000000,0x71); +reg_write( DDR_REG_BASE +0x51cfc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51cfd*4 +0x02000000,0xffa); +reg_write( DDR_REG_BASE +0x51cfe*4 +0x02000000,0xfe4f); +reg_write( DDR_REG_BASE +0x51cff*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51d00*4 +0x02000000,0x708f); +reg_write( DDR_REG_BASE +0x51d01*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51d02*4 +0x02000000,0x669); +reg_write( DDR_REG_BASE +0x51d03*4 +0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x51d04*4 +0x02000000,0xf035); +reg_write( DDR_REG_BASE +0x51d05*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x51d06*4 +0x02000000,0x85f); +reg_write( DDR_REG_BASE +0x51d07*4 +0x02000000,0x36e); +reg_write( DDR_REG_BASE +0x51d08*4 +0x02000000,0x212f); +reg_write( DDR_REG_BASE +0x51d09*4 +0x02000000,0x6c7); +reg_write( DDR_REG_BASE +0x51d0a*4 +0x02000000,0xc088); +reg_write( DDR_REG_BASE +0x51d0b*4 +0x02000000,0x7834); +reg_write( DDR_REG_BASE +0x51d0c*4 +0x02000000,0x8841); +reg_write( DDR_REG_BASE +0x51d0d*4 +0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x51d0e*4 +0x02000000,0x43a1); +reg_write( DDR_REG_BASE +0x51d0f*4 +0x02000000,0xc241); +reg_write( DDR_REG_BASE +0x51d10*4 +0x02000000,0x6059); +reg_write( DDR_REG_BASE +0x51d11*4 +0x02000000,0xc204); +reg_write( DDR_REG_BASE +0x51d12*4 +0x02000000,0x7e3d); +reg_write( DDR_REG_BASE +0x51d13*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x51d14*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x51d15*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d16*4 +0x02000000,0x73); +reg_write( DDR_REG_BASE +0x51d17*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51d18*4 +0x02000000,0xfc2); +reg_write( DDR_REG_BASE +0x51d19*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51d1a*4 +0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x51d1b*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51d1c*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x51d1d*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51d1e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51d1f*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x51d20*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x51d21*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x51d22*4 +0x02000000,0x8); +reg_write( DDR_REG_BASE +0x51d23*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x51d24*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51d25*4 +0x02000000,0x817); +reg_write( DDR_REG_BASE +0x51d26*4 +0x02000000,0xc10); +reg_write( DDR_REG_BASE +0x51d27*4 +0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x51d28*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51d29*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51d2a*4 +0x02000000,0x80); +reg_write( DDR_REG_BASE +0x51d2b*4 +0x02000000,0xb0c0); +reg_write( DDR_REG_BASE +0x51d2c*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51d2d*4 +0x02000000,0xe0c0); +reg_write( DDR_REG_BASE +0x51d2e*4 +0x02000000,0xf206); +reg_write( DDR_REG_BASE +0x51d2f*4 +0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x51d30*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51d31*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51d32*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x51d33*4 +0x02000000,0xb0c0); +reg_write( DDR_REG_BASE +0x51d34*4 +0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x51d35*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x51d36*4 +0x02000000,0xd9f); +reg_write( DDR_REG_BASE +0x51d37*4 +0x02000000,0x9254); +reg_write( DDR_REG_BASE +0x51d38*4 +0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x51d39*4 +0x02000000,0x78ef); +reg_write( DDR_REG_BASE +0x51d3a*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x51d3b*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51d3c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51d3d*4 +0x02000000,0x669); +reg_write( DDR_REG_BASE +0x51d3e*4 +0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x51d3f*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51d40*4 +0x02000000,0x9ed); +reg_write( DDR_REG_BASE +0x51d41*4 +0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x51d42*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x51d43*4 +0x02000000,0xbd2); +reg_write( DDR_REG_BASE +0x51d44*4 +0x02000000,0xfe8f); +reg_write( DDR_REG_BASE +0x51d45*4 +0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x51d46*4 +0x02000000,0x3103); +reg_write( DDR_REG_BASE +0x51d47*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x51d48*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x51d49*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51d4a*4 +0x02000000,0xc0e6); +reg_write( DDR_REG_BASE +0x51d4b*4 +0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x51d4c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51d4d*4 +0x02000000,0x669); +reg_write( DDR_REG_BASE +0x51d4e*4 +0x02000000,0x8ba0); +reg_write( DDR_REG_BASE +0x51d4f*4 +0x02000000,0x8b81); +reg_write( DDR_REG_BASE +0x51d50*4 +0x02000000,0x251f); +reg_write( DDR_REG_BASE +0x51d51*4 +0x02000000,0x108f); +reg_write( DDR_REG_BASE +0x51d52*4 +0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x51d53*4 +0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x51d54*4 +0x02000000,0x1f9e); +reg_write( DDR_REG_BASE +0x51d55*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51d56*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x51d57*4 +0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x51d58*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51d59*4 +0x02000000,0x2114); +reg_write( DDR_REG_BASE +0x51d5a*4 +0x02000000,0x38e); +reg_write( DDR_REG_BASE +0x51d5b*4 +0x02000000,0x2605); +reg_write( DDR_REG_BASE +0x51d5c*4 +0x02000000,0x301e); +reg_write( DDR_REG_BASE +0x51d5d*4 +0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x51d5e*4 +0x02000000,0x783); +reg_write( DDR_REG_BASE +0x51d5f*4 +0x02000000,0x7b7b); +reg_write( DDR_REG_BASE +0x51d60*4 +0x02000000,0xbb91); +reg_write( DDR_REG_BASE +0x51d61*4 +0x02000000,0xbb9c); +reg_write( DDR_REG_BASE +0x51d62*4 +0x02000000,0xbb9f); +reg_write( DDR_REG_BASE +0x51d63*4 +0x02000000,0x9360); +reg_write( DDR_REG_BASE +0x51d64*4 +0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x51d65*4 +0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x51d66*4 +0x02000000,0xb660); +reg_write( DDR_REG_BASE +0x51d67*4 +0x02000000,0x232f); +reg_write( DDR_REG_BASE +0x51d68*4 +0x02000000,0x2c7); +reg_write( DDR_REG_BASE +0x51d69*4 +0x02000000,0xbd7); +reg_write( DDR_REG_BASE +0x51d6a*4 +0x02000000,0x80a4); +reg_write( DDR_REG_BASE +0x51d6b*4 +0x02000000,0x7ef0); +reg_write( DDR_REG_BASE +0x51d6c*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x51d6d*4 +0x02000000,0xcf7); +reg_write( DDR_REG_BASE +0x51d6e*4 +0x02000000,0x9365); +reg_write( DDR_REG_BASE +0x51d6f*4 +0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x51d70*4 +0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x51d71*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51d72*4 +0x02000000,0xc0e6); +reg_write( DDR_REG_BASE +0x51d73*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d74*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51d75*4 +0x02000000,0x669); +reg_write( DDR_REG_BASE +0x51d76*4 +0x02000000,0x8960); +reg_write( DDR_REG_BASE +0x51d77*4 +0x02000000,0x8941); +reg_write( DDR_REG_BASE +0x51d78*4 +0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x51d79*4 +0x02000000,0x24d); +reg_write( DDR_REG_BASE +0x51d7a*4 +0x02000000,0xe508); +reg_write( DDR_REG_BASE +0x51d7b*4 +0x02000000,0xf022); +reg_write( DDR_REG_BASE +0x51d7c*4 +0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x51d7d*4 +0x02000000,0x8); +reg_write( DDR_REG_BASE +0x51d7e*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x51d7f*4 +0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x51d80*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51d81*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x51d82*4 +0x02000000,0x278a); +reg_write( DDR_REG_BASE +0x51d83*4 +0x02000000,0x1fcf); +reg_write( DDR_REG_BASE +0x51d84*4 +0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x51d85*4 +0x02000000,0x79c5); +reg_write( DDR_REG_BASE +0x51d86*4 +0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x51d87*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51d88*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51d89*4 +0x02000000,0x64); +reg_write( DDR_REG_BASE +0x51d8a*4 +0x02000000,0x9120); +reg_write( DDR_REG_BASE +0x51d8b*4 +0x02000000,0x7f24); +reg_write( DDR_REG_BASE +0x51d8c*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x51d8d*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x51d8e*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x51d8f*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x51d90*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x51d91*4 +0x02000000,0x216c); +reg_write( DDR_REG_BASE +0x51d92*4 +0x02000000,0x10e); +reg_write( DDR_REG_BASE +0x51d93*4 +0x02000000,0x66fe); +reg_write( DDR_REG_BASE +0x51d94*4 +0x02000000,0x2014); +reg_write( DDR_REG_BASE +0x51d95*4 +0x02000000,0x341); +reg_write( DDR_REG_BASE +0x51d96*4 +0x02000000,0xb1c0); +reg_write( DDR_REG_BASE +0x51d97*4 +0x02000000,0xe509); +reg_write( DDR_REG_BASE +0x51d98*4 +0x02000000,0xcc9); +reg_write( DDR_REG_BASE +0x51d99*4 +0x02000000,0x9274); +reg_write( DDR_REG_BASE +0x51d9a*4 +0x02000000,0x4181); +reg_write( DDR_REG_BASE +0x51d9b*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x51d9c*4 +0x02000000,0xaf9); +reg_write( DDR_REG_BASE +0x51d9d*4 +0x02000000,0x80e5); +reg_write( DDR_REG_BASE +0x51d9e*4 +0x02000000,0xdc08); +reg_write( DDR_REG_BASE +0x51d9f*4 +0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x51da0*4 +0x02000000,0xcc32); +reg_write( DDR_REG_BASE +0x51da1*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x51da2*4 +0x02000000,0x1a33); +reg_write( DDR_REG_BASE +0x51da3*4 +0x02000000,0x301c); +reg_write( DDR_REG_BASE +0x51da4*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x51da5*4 +0x02000000,0x4308); +reg_write( DDR_REG_BASE +0x51da6*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x51da7*4 +0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x51da8*4 +0x02000000,0xb19); +reg_write( DDR_REG_BASE +0x51da9*4 +0x02000000,0x10ee); +reg_write( DDR_REG_BASE +0x51daa*4 +0x02000000,0x786f); +reg_write( DDR_REG_BASE +0x51dab*4 +0x02000000,0xa7e); +reg_write( DDR_REG_BASE +0x51dac*4 +0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x51dad*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51dae*4 +0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x51daf*4 +0x02000000,0x1801); +reg_write( DDR_REG_BASE +0x51db0*4 +0x02000000,0xfd3); +reg_write( DDR_REG_BASE +0x51db1*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x51db2*4 +0x02000000,0xafb); +reg_write( DDR_REG_BASE +0x51db3*4 +0x02000000,0x8094); +reg_write( DDR_REG_BASE +0x51db4*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x51db5*4 +0x02000000,0xbe9); +reg_write( DDR_REG_BASE +0x51db6*4 +0x02000000,0x8094); +reg_write( DDR_REG_BASE +0x51db7*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x51db8*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51db9*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51dba*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x51dbb*4 +0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x51dbc*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x51dbd*4 +0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x51dbe*4 +0x02000000,0x70ef); +reg_write( DDR_REG_BASE +0x51dbf*4 +0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x51dc0*4 +0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x51dc1*4 +0x02000000,0xc82); +reg_write( DDR_REG_BASE +0x51dc2*4 +0x02000000,0x605c); +reg_write( DDR_REG_BASE +0x51dc3*4 +0x02000000,0x275a); +reg_write( DDR_REG_BASE +0x51dc4*4 +0x02000000,0x3642); +reg_write( DDR_REG_BASE +0x51dc5*4 +0x02000000,0x71e7); +reg_write( DDR_REG_BASE +0x51dc6*4 +0x02000000,0x629a); +reg_write( DDR_REG_BASE +0x51dc7*4 +0x02000000,0x623c); +reg_write( DDR_REG_BASE +0x51dc8*4 +0x02000000,0x2600); +reg_write( DDR_REG_BASE +0x51dc9*4 +0x02000000,0x3682); +reg_write( DDR_REG_BASE +0x51dca*4 +0x02000000,0x125c); +reg_write( DDR_REG_BASE +0x51dcb*4 +0x02000000,0x82); +reg_write( DDR_REG_BASE +0x51dcc*4 +0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x51dcd*4 +0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x51dce*4 +0x02000000,0xac40); +reg_write( DDR_REG_BASE +0x51dcf*4 +0x02000000,0xfe5); +reg_write( DDR_REG_BASE +0x51dd0*4 +0x02000000,0xb094); +reg_write( DDR_REG_BASE +0x51dd1*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x51dd2*4 +0x02000000,0xbd9); +reg_write( DDR_REG_BASE +0x51dd3*4 +0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x51dd4*4 +0x02000000,0x2314); +reg_write( DDR_REG_BASE +0x51dd5*4 +0x02000000,0x10de); +reg_write( DDR_REG_BASE +0x51dd6*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x51dd7*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51dd8*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51dd9*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51dda*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51ddb*4 +0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x51ddc*4 +0x02000000,0x3003); +reg_write( DDR_REG_BASE +0x51ddd*4 +0x02000000,0x4548); +reg_write( DDR_REG_BASE +0x51dde*4 +0x02000000,0x4628); +reg_write( DDR_REG_BASE +0x51ddf*4 +0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x51de0*4 +0x02000000,0xc099); +reg_write( DDR_REG_BASE +0x51de1*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51de2*4 +0x02000000,0xda5a); +reg_write( DDR_REG_BASE +0x51de3*4 +0x02000000,0xb8a); +reg_write( DDR_REG_BASE +0x51de4*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x51de5*4 +0x02000000,0x4378); +reg_write( DDR_REG_BASE +0x51de6*4 +0x02000000,0xc082); +reg_write( DDR_REG_BASE +0x51de7*4 +0x02000000,0xb82); +reg_write( DDR_REG_BASE +0x51de8*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x51de9*4 +0x02000000,0xda5a); +reg_write( DDR_REG_BASE +0x51dea*4 +0x02000000,0xb0f); +reg_write( DDR_REG_BASE +0x51deb*4 +0x02000000,0x71); +reg_write( DDR_REG_BASE +0x51dec*4 +0x02000000,0xc099); +reg_write( DDR_REG_BASE +0x51ded*4 +0x02000000,0xc182); +reg_write( DDR_REG_BASE +0x51dee*4 +0x02000000,0x9e2); +reg_write( DDR_REG_BASE +0x51def*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51df0*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x51df1*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x51df2*4 +0x02000000,0xd56); +reg_write( DDR_REG_BASE +0x51df3*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51df4*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x51df5*4 +0x02000000,0xca66); +reg_write( DDR_REG_BASE +0x51df6*4 +0x02000000,0xf070); +reg_write( DDR_REG_BASE +0x51df7*4 +0x02000000,0xb13); +reg_write( DDR_REG_BASE +0x51df8*4 +0x02000000,0x3071); +reg_write( DDR_REG_BASE +0x51df9*4 +0x02000000,0xc182); +reg_write( DDR_REG_BASE +0x51dfa*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51dfb*4 +0x02000000,0xc16); +reg_write( DDR_REG_BASE +0x51dfc*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x51dfd*4 +0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x51dfe*4 +0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x51dff*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51e00*4 +0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x51e01*4 +0x02000000,0xd19); +reg_write( DDR_REG_BASE +0x51e02*4 +0x02000000,0x106e); +reg_write( DDR_REG_BASE +0x51e03*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x51e04*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x51e05*4 +0x02000000,0x8); +reg_write( DDR_REG_BASE +0x51e06*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51e07*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x51e08*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51e09*4 +0x02000000,0xe064); +reg_write( DDR_REG_BASE +0x51e0a*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51e0b*4 +0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x51e0c*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x51e0d*4 +0x02000000,0x9eb); +reg_write( DDR_REG_BASE +0x51e0e*4 +0x02000000,0x8254); +reg_write( DDR_REG_BASE +0x51e0f*4 +0x02000000,0x8ca); +reg_write( DDR_REG_BASE +0x51e10*4 +0x02000000,0xfe4f); +reg_write( DDR_REG_BASE +0x51e11*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51e12*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e13*4 +0x02000000,0x667); +reg_write( DDR_REG_BASE +0x51e14*4 +0x02000000,0x8820); +reg_write( DDR_REG_BASE +0x51e15*4 +0x02000000,0x8842); +reg_write( DDR_REG_BASE +0x51e16*4 +0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x51e17*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e18*4 +0x02000000,0x6dc); +reg_write( DDR_REG_BASE +0x51e19*4 +0x02000000,0x2614); +reg_write( DDR_REG_BASE +0x51e1a*4 +0x02000000,0x104b); +reg_write( DDR_REG_BASE +0x51e1b*4 +0x02000000,0x8823); +reg_write( DDR_REG_BASE +0x51e1c*4 +0x02000000,0xf037); +reg_write( DDR_REG_BASE +0x51e1d*4 +0x02000000,0x264c); +reg_write( DDR_REG_BASE +0x51e1e*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x51e1f*4 +0x02000000,0xd5b); +reg_write( DDR_REG_BASE +0x51e20*4 +0x02000000,0x17ae); +reg_write( DDR_REG_BASE +0x51e21*4 +0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x51e22*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x51e23*4 +0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x51e24*4 +0x02000000,0x1140); +reg_write( DDR_REG_BASE +0x51e25*4 +0x02000000,0x84d); +reg_write( DDR_REG_BASE +0x51e26*4 +0x02000000,0x32); +reg_write( DDR_REG_BASE +0x51e27*4 +0x02000000,0x200a); +reg_write( DDR_REG_BASE +0x51e28*4 +0x02000000,0x780); +reg_write( DDR_REG_BASE +0x51e29*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x51e2a*4 +0x02000000,0x8); +reg_write( DDR_REG_BASE +0x51e2b*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x51e2c*4 +0x02000000,0xf9f); +reg_write( DDR_REG_BASE +0x51e2d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51e2e*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x51e2f*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51e30*4 +0x02000000,0x7c0); +reg_write( DDR_REG_BASE +0x51e31*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51e32*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51e33*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51e34*4 +0x02000000,0x166); +reg_write( DDR_REG_BASE +0x51e35*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51e36*4 +0x02000000,0xe894); +reg_write( DDR_REG_BASE +0x51e37*4 +0x02000000,0x2414); +reg_write( DDR_REG_BASE +0x51e38*4 +0x02000000,0x13c0); +reg_write( DDR_REG_BASE +0x51e39*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51e3a*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x51e3b*4 +0x02000000,0x9f); +reg_write( DDR_REG_BASE +0x51e3c*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51e3d*4 +0x02000000,0x2708); +reg_write( DDR_REG_BASE +0x51e3e*4 +0x02000000,0x301f); +reg_write( DDR_REG_BASE +0x51e3f*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51e40*4 +0x02000000,0x1801); +reg_write( DDR_REG_BASE +0x51e41*4 +0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x51e42*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x51e43*4 +0x02000000,0x9f); +reg_write( DDR_REG_BASE +0x51e44*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51e45*4 +0x02000000,0x2709); +reg_write( DDR_REG_BASE +0x51e46*4 +0x02000000,0x301f); +reg_write( DDR_REG_BASE +0x51e47*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51e48*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x51e49*4 +0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x51e4a*4 +0x02000000,0xe441); +reg_write( DDR_REG_BASE +0x51e4b*4 +0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x51e4c*4 +0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x51e4d*4 +0x02000000,0xea3); +reg_write( DDR_REG_BASE +0x51e4e*4 +0x02000000,0xb274); +reg_write( DDR_REG_BASE +0x51e4f*4 +0x02000000,0x2340); +reg_write( DDR_REG_BASE +0x51e50*4 +0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x51e51*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x51e52*4 +0x02000000,0x4308); +reg_write( DDR_REG_BASE +0x51e53*4 +0x02000000,0x7b4f); +reg_write( DDR_REG_BASE +0x51e54*4 +0x02000000,0x9f3); +reg_write( DDR_REG_BASE +0x51e55*4 +0x02000000,0x80e5); +reg_write( DDR_REG_BASE +0x51e56*4 +0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x51e57*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x51e58*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x51e59*4 +0x02000000,0xc8a); +reg_write( DDR_REG_BASE +0x51e5a*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51e5b*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x51e5c*4 +0x02000000,0xca15); +reg_write( DDR_REG_BASE +0x51e5d*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51e5e*4 +0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x51e5f*4 +0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x51e60*4 +0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x51e61*4 +0x02000000,0x801); +reg_write( DDR_REG_BASE +0x51e62*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x51e63*4 +0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x51e64*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51e65*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51e66*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51e67*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x51e68*4 +0x02000000,0xca67); +reg_write( DDR_REG_BASE +0x51e69*4 +0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x51e6a*4 +0x02000000,0x81b); +reg_write( DDR_REG_BASE +0x51e6b*4 +0x02000000,0x8045); +reg_write( DDR_REG_BASE +0x51e6c*4 +0x02000000,0xb0f); +reg_write( DDR_REG_BASE +0x51e6d*4 +0x02000000,0x3071); +reg_write( DDR_REG_BASE +0x51e6e*4 +0x02000000,0xc099); +reg_write( DDR_REG_BASE +0x51e6f*4 +0x02000000,0xc182); +reg_write( DDR_REG_BASE +0x51e70*4 +0x02000000,0x8de); +reg_write( DDR_REG_BASE +0x51e71*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51e72*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51e73*4 +0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x51e74*4 +0x02000000,0x3003); +reg_write( DDR_REG_BASE +0x51e75*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x51e76*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x51e77*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51e78*4 +0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x51e79*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x51e7a*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x51e7b*4 +0x02000000,0xe000); +reg_write( DDR_REG_BASE +0x51e7c*4 +0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x51e7d*4 +0x02000000,0xf02); +reg_write( DDR_REG_BASE +0x51e7e*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51e7f*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x51e80*4 +0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x51e81*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x51e82*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x51e83*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x51e84*4 +0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x51e85*4 +0x02000000,0x216c); +reg_write( DDR_REG_BASE +0x51e86*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x51e87*4 +0x02000000,0xa821); +reg_write( DDR_REG_BASE +0x51e88*4 +0x02000000,0x8822); +reg_write( DDR_REG_BASE +0x51e89*4 +0x02000000,0xb9c6); +reg_write( DDR_REG_BASE +0x51e8a*4 +0x02000000,0xa822); +reg_write( DDR_REG_BASE +0x51e8b*4 +0x02000000,0x882d); +reg_write( DDR_REG_BASE +0x51e8c*4 +0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x51e8d*4 +0x02000000,0xc02); +reg_write( DDR_REG_BASE +0x51e8e*4 +0x02000000,0x2285); +reg_write( DDR_REG_BASE +0x51e8f*4 +0x02000000,0x23f); +reg_write( DDR_REG_BASE +0x51e90*4 +0x02000000,0x913); +reg_write( DDR_REG_BASE +0x51e91*4 +0x02000000,0x17f); +reg_write( DDR_REG_BASE +0x51e92*4 +0x02000000,0xa84d); +reg_write( DDR_REG_BASE +0x51e93*4 +0x02000000,0x794f); +reg_write( DDR_REG_BASE +0x51e94*4 +0x02000000,0xb985); +reg_write( DDR_REG_BASE +0x51e95*4 +0x02000000,0xa82d); +reg_write( DDR_REG_BASE +0x51e96*4 +0x02000000,0x8823); +reg_write( DDR_REG_BASE +0x51e97*4 +0x02000000,0xb987); +reg_write( DDR_REG_BASE +0x51e98*4 +0x02000000,0xa823); +reg_write( DDR_REG_BASE +0x51e99*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51e9a*4 +0x02000000,0xa838); +reg_write( DDR_REG_BASE +0x51e9b*4 +0x02000000,0xa831); +reg_write( DDR_REG_BASE +0x51e9c*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x51e9d*4 +0x02000000,0xa830); +reg_write( DDR_REG_BASE +0x51e9e*4 +0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x51e9f*4 +0x02000000,0xe4a); +reg_write( DDR_REG_BASE +0x51ea0*4 +0x02000000,0xfe8f); +reg_write( DDR_REG_BASE +0x51ea1*4 +0x02000000,0x256f); +reg_write( DDR_REG_BASE +0x51ea2*4 +0x02000000,0x1343); +reg_write( DDR_REG_BASE +0x51ea3*4 +0x02000000,0x9560); +reg_write( DDR_REG_BASE +0x51ea4*4 +0x02000000,0xda20); +reg_write( DDR_REG_BASE +0x51ea5*4 +0x02000000,0xd940); +reg_write( DDR_REG_BASE +0x51ea6*4 +0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x51ea7*4 +0x02000000,0x85ca); +reg_write( DDR_REG_BASE +0x51ea8*4 +0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x51ea9*4 +0x02000000,0xc2d); +reg_write( DDR_REG_BASE +0x51eaa*4 +0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x51eab*4 +0x02000000,0x89d0); +reg_write( DDR_REG_BASE +0x51eac*4 +0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x51ead*4 +0x02000000,0x4d); +reg_write( DDR_REG_BASE +0x51eae*4 +0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x51eaf*4 +0x02000000,0x8fd8); +reg_write( DDR_REG_BASE +0x51eb0*4 +0x02000000,0xd950); +reg_write( DDR_REG_BASE +0x51eb1*4 +0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x51eb2*4 +0x02000000,0x4d); +reg_write( DDR_REG_BASE +0x51eb3*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51eb4*4 +0x02000000,0x5ca); +reg_write( DDR_REG_BASE +0x51eb5*4 +0x02000000,0x213c); +reg_write( DDR_REG_BASE +0x51eb6*4 +0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x51eb7*4 +0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x51eb8*4 +0x02000000,0x89d0); +reg_write( DDR_REG_BASE +0x51eb9*4 +0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x51eba*4 +0x02000000,0xad); +reg_write( DDR_REG_BASE +0x51ebb*4 +0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x51ebc*4 +0x02000000,0x8fd8); +reg_write( DDR_REG_BASE +0x51ebd*4 +0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x51ebe*4 +0x02000000,0xed); +reg_write( DDR_REG_BASE +0x51ebf*4 +0x02000000,0x73d3); +reg_write( DDR_REG_BASE +0x51ec0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51ec1*4 +0x02000000,0x95f); +reg_write( DDR_REG_BASE +0x51ec2*4 +0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x51ec3*4 +0x02000000,0x12d); +reg_write( DDR_REG_BASE +0x51ec4*4 +0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x51ec5*4 +0x02000000,0x8c); +reg_write( DDR_REG_BASE +0x51ec6*4 +0x02000000,0x15fe); +reg_write( DDR_REG_BASE +0x51ec7*4 +0x02000000,0x9081); +reg_write( DDR_REG_BASE +0x51ec8*4 +0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x51ec9*4 +0x02000000,0x400); +reg_write( DDR_REG_BASE +0x51eca*4 +0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x51ecb*4 +0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x51ecc*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51ecd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51ece*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51ecf*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51ed0*4 +0x02000000,0xf8); +reg_write( DDR_REG_BASE +0x51ed1*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x51ed2*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51ed3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51ed4*4 +0x02000000,0x1ff0); +reg_write( DDR_REG_BASE +0x51ed5*4 +0x02000000,0xb881); +reg_write( DDR_REG_BASE +0x51ed6*4 +0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x51ed7*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x51ed8*4 +0x02000000,0x7224); +reg_write( DDR_REG_BASE +0x51ed9*4 +0x02000000,0x7965); +reg_write( DDR_REG_BASE +0x51eda*4 +0x02000000,0xb280); +reg_write( DDR_REG_BASE +0x51edb*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x51edc*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x51edd*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51ede*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51edf*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51ee0*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51ee1*4 +0x02000000,0x4358); +reg_write( DDR_REG_BASE +0x51ee2*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x51ee3*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51ee4*4 +0x02000000,0x669); +reg_write( DDR_REG_BASE +0x51ee5*4 +0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x51ee6*4 +0x02000000,0x8b); +reg_write( DDR_REG_BASE +0x51ee7*4 +0x02000000,0x4738); +reg_write( DDR_REG_BASE +0x51ee8*4 +0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x51ee9*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x51eea*4 +0x02000000,0xf030); +reg_write( DDR_REG_BASE +0x51eeb*4 +0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x51eec*4 +0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x51eed*4 +0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x51eee*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51eef*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x51ef0*4 +0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x51ef1*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51ef2*4 +0x02000000,0xdc30); +reg_write( DDR_REG_BASE +0x51ef3*4 +0x02000000,0xbc90); +reg_write( DDR_REG_BASE +0x51ef4*4 +0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x51ef5*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51ef6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51ef7*4 +0x02000000,0x7d65); +reg_write( DDR_REG_BASE +0x51ef8*4 +0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x51ef9*4 +0x02000000,0x1303); +reg_write( DDR_REG_BASE +0x51efa*4 +0x02000000,0xe410); +reg_write( DDR_REG_BASE +0x51efb*4 +0x02000000,0x7ca5); +reg_write( DDR_REG_BASE +0x51efc*4 +0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x51efd*4 +0x02000000,0x24d); +reg_write( DDR_REG_BASE +0x51efe*4 +0x02000000,0x7e9b); +reg_write( DDR_REG_BASE +0x51eff*4 +0x02000000,0x7c7b); +reg_write( DDR_REG_BASE +0x51f00*4 +0x02000000,0x7ee5); +reg_write( DDR_REG_BASE +0x51f01*4 +0x02000000,0x2600); +reg_write( DDR_REG_BASE +0x51f02*4 +0x02000000,0x3343); +reg_write( DDR_REG_BASE +0x51f03*4 +0x02000000,0x75e3); +reg_write( DDR_REG_BASE +0x51f04*4 +0x02000000,0x7f85); +reg_write( DDR_REG_BASE +0x51f05*4 +0x02000000,0x631b); +reg_write( DDR_REG_BASE +0x51f06*4 +0x02000000,0xb13); +reg_write( DDR_REG_BASE +0x51f07*4 +0x02000000,0x3030); +reg_write( DDR_REG_BASE +0x51f08*4 +0x02000000,0x651d); +reg_write( DDR_REG_BASE +0x51f09*4 +0x02000000,0x9680); +reg_write( DDR_REG_BASE +0x51f0a*4 +0x02000000,0xab80); +reg_write( DDR_REG_BASE +0x51f0b*4 +0x02000000,0x9760); +reg_write( DDR_REG_BASE +0x51f0c*4 +0x02000000,0x7b82); +reg_write( DDR_REG_BASE +0x51f0d*4 +0x02000000,0xad60); +reg_write( DDR_REG_BASE +0x51f0e*4 +0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x51f0f*4 +0x02000000,0x8b80); +reg_write( DDR_REG_BASE +0x51f10*4 +0x02000000,0xb680); +reg_write( DDR_REG_BASE +0x51f11*4 +0x02000000,0x8b60); +reg_write( DDR_REG_BASE +0x51f12*4 +0x02000000,0x1500); +reg_write( DDR_REG_BASE +0x51f13*4 +0x02000000,0x10cc); +reg_write( DDR_REG_BASE +0x51f14*4 +0x02000000,0x639b); +reg_write( DDR_REG_BASE +0x51f15*4 +0x02000000,0xb760); +reg_write( DDR_REG_BASE +0x51f16*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x51f17*4 +0x02000000,0x8ab); +reg_write( DDR_REG_BASE +0x51f18*4 +0x02000000,0x8254); +reg_write( DDR_REG_BASE +0x51f19*4 +0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x51f1a*4 +0x02000000,0x8a01); +reg_write( DDR_REG_BASE +0x51f1b*4 +0x02000000,0x212f); +reg_write( DDR_REG_BASE +0x51f1c*4 +0x02000000,0x2c7); +reg_write( DDR_REG_BASE +0x51f1d*4 +0x02000000,0x8f7); +reg_write( DDR_REG_BASE +0x51f1e*4 +0x02000000,0x8065); +reg_write( DDR_REG_BASE +0x51f1f*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51f20*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x51f21*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x51f22*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51f23*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51f24*4 +0x02000000,0xc0e4); +reg_write( DDR_REG_BASE +0x51f25*4 +0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x51f26*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x51f27*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51f28*4 +0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x51f29*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x51f2a*4 +0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x51f2b*4 +0x02000000,0x225a); +reg_write( DDR_REG_BASE +0x51f2c*4 +0x02000000,0xc8c); +reg_write( DDR_REG_BASE +0x51f2d*4 +0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x51f2e*4 +0x02000000,0x609d); +reg_write( DDR_REG_BASE +0x51f2f*4 +0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x51f30*4 +0x02000000,0x64c); +reg_write( DDR_REG_BASE +0x51f31*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x51f32*4 +0x02000000,0x64bc); +reg_write( DDR_REG_BASE +0x51f33*4 +0x02000000,0x642c); +reg_write( DDR_REG_BASE +0x51f34*4 +0x02000000,0x1e5c); +reg_write( DDR_REG_BASE +0x51f35*4 +0x02000000,0x1302); +reg_write( DDR_REG_BASE +0x51f36*4 +0x02000000,0xbeb); +reg_write( DDR_REG_BASE +0x51f37*4 +0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x51f38*4 +0x02000000,0x2300); +reg_write( DDR_REG_BASE +0x51f39*4 +0x02000000,0x168e); +reg_write( DDR_REG_BASE +0x51f3a*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x51f3b*4 +0x02000000,0xadf); +reg_write( DDR_REG_BASE +0x51f3c*4 +0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x51f3d*4 +0x02000000,0x2614); +reg_write( DDR_REG_BASE +0x51f3e*4 +0x02000000,0x308b); +reg_write( DDR_REG_BASE +0x51f3f*4 +0x02000000,0xc4c4); +reg_write( DDR_REG_BASE +0x51f40*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51f41*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51f42*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51f43*4 +0x02000000,0xc1bc); +reg_write( DDR_REG_BASE +0x51f44*4 +0x02000000,0xc244); +reg_write( DDR_REG_BASE +0x51f45*4 +0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x51f46*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x51f47*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51f48*4 +0x02000000,0x710d); +reg_write( DDR_REG_BASE +0x51f49*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x51f4a*4 +0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x51f4b*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51f4c*4 +0x02000000,0x9c6); +reg_write( DDR_REG_BASE +0x51f4d*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x51f4e*4 +0x02000000,0x4378); +reg_write( DDR_REG_BASE +0x51f4f*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51f50*4 +0x02000000,0x7002); +reg_write( DDR_REG_BASE +0x51f51*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51f52*4 +0x02000000,0x666); +reg_write( DDR_REG_BASE +0x51f53*4 +0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x51f54*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51f55*4 +0x02000000,0x7001); +reg_write( DDR_REG_BASE +0x51f56*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51f57*4 +0x02000000,0x674); +reg_write( DDR_REG_BASE +0x51f58*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x51f59*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51f5a*4 +0x02000000,0x708f); +reg_write( DDR_REG_BASE +0x51f5b*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51f5c*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51f5d*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x51f5e*4 +0x02000000,0xca6); +reg_write( DDR_REG_BASE +0x51f5f*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51f60*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x51f61*4 +0x02000000,0xa56); +reg_write( DDR_REG_BASE +0x51f62*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51f63*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x51f64*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x51f65*4 +0x02000000,0x8); +reg_write( DDR_REG_BASE +0x51f66*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51f67*4 +0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x51f68*4 +0x02000000,0xe1f2); +reg_write( DDR_REG_BASE +0x51f69*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x51f6a*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x51f6b*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x51f6c*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x51f6d*4 +0x02000000,0xb1a1); +reg_write( DDR_REG_BASE +0x51f6e*4 +0x02000000,0xb102); +reg_write( DDR_REG_BASE +0x51f6f*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51f70*4 +0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x51f71*4 +0x02000000,0x17c1); +reg_write( DDR_REG_BASE +0x51f72*4 +0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x51f73*4 +0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x51f74*4 +0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x51f75*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x51f76*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51f77*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51f78*4 +0x02000000,0x7344); +reg_write( DDR_REG_BASE +0x51f79*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51f7a*4 +0x02000000,0xfec4); +reg_write( DDR_REG_BASE +0x51f7b*4 +0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x51f7c*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x51f7d*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51f7e*4 +0x02000000,0x200f); +reg_write( DDR_REG_BASE +0x51f7f*4 +0x02000000,0x380); +reg_write( DDR_REG_BASE +0x51f80*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51f81*4 +0x02000000,0xe32); +reg_write( DDR_REG_BASE +0x51f82*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x51f83*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x51f84*4 +0x02000000,0x271a); +reg_write( DDR_REG_BASE +0x51f85*4 +0x02000000,0x1f8f); +reg_write( DDR_REG_BASE +0x51f86*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x51f87*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51f88*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51f89*4 +0x02000000,0x7214); +reg_write( DDR_REG_BASE +0x51f8a*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51f8b*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51f8c*4 +0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x51f8d*4 +0x02000000,0xf404); +reg_write( DDR_REG_BASE +0x51f8e*4 +0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x51f8f*4 +0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x51f90*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x51f91*4 +0x02000000,0x6c4); +reg_write( DDR_REG_BASE +0x51f92*4 +0x02000000,0x1484); +reg_write( DDR_REG_BASE +0x51f93*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x51f94*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x51f95*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51f96*4 +0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x51f97*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51f98*4 +0x02000000,0x164); +reg_write( DDR_REG_BASE +0x51f99*4 +0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x51f9a*4 +0x02000000,0x206c); +reg_write( DDR_REG_BASE +0x51f9b*4 +0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x51f9c*4 +0x02000000,0xfae); +reg_write( DDR_REG_BASE +0x51f9d*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51f9e*4 +0x02000000,0xb880); +reg_write( DDR_REG_BASE +0x51f9f*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51fa0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51fa1*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x51fa2*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x51fa3*4 +0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x51fa4*4 +0x02000000,0x966); +reg_write( DDR_REG_BASE +0x51fa5*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51fa6*4 +0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x51fa7*4 +0x02000000,0xc092); +reg_write( DDR_REG_BASE +0x51fa8*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51fa9*4 +0x02000000,0xffe); +reg_write( DDR_REG_BASE +0x51faa*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51fab*4 +0x02000000,0xda28); +reg_write( DDR_REG_BASE +0x51fac*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x51fad*4 +0x02000000,0xc192); +reg_write( DDR_REG_BASE +0x51fae*4 +0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x51faf*4 +0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x51fb0*4 +0x02000000,0x8c0); +reg_write( DDR_REG_BASE +0x51fb1*4 +0x02000000,0x7f05); +reg_write( DDR_REG_BASE +0x51fb2*4 +0x02000000,0xc746); +reg_write( DDR_REG_BASE +0x51fb3*4 +0x02000000,0xb32); +reg_write( DDR_REG_BASE +0x51fb4*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51fb5*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x51fb6*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51fb7*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51fb8*4 +0x02000000,0xf283); +reg_write( DDR_REG_BASE +0x51fb9*4 +0x02000000,0xc088); +reg_write( DDR_REG_BASE +0x51fba*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51fbb*4 +0x02000000,0x38); +reg_write( DDR_REG_BASE +0x51fbc*4 +0x02000000,0xfe6); +reg_write( DDR_REG_BASE +0x51fbd*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51fbe*4 +0x02000000,0xda14); +reg_write( DDR_REG_BASE +0x51fbf*4 +0x02000000,0xca0c); +reg_write( DDR_REG_BASE +0x51fc0*4 +0x02000000,0xd910); +reg_write( DDR_REG_BASE +0x51fc1*4 +0x02000000,0x4220); +reg_write( DDR_REG_BASE +0x51fc2*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x51fc3*4 +0x02000000,0x7c1); +reg_write( DDR_REG_BASE +0x51fc4*4 +0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x51fc5*4 +0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x51fc6*4 +0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x51fc7*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x51fc8*4 +0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x51fc9*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x51fca*4 +0x02000000,0x7c3); +reg_write( DDR_REG_BASE +0x51fcb*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51fcc*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x51fcd*4 +0x02000000,0xeb06); +reg_write( DDR_REG_BASE +0x51fce*4 +0x02000000,0xbb61); +reg_write( DDR_REG_BASE +0x51fcf*4 +0x02000000,0xb01); +reg_write( DDR_REG_BASE +0x51fd0*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x51fd1*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51fd2*4 +0x02000000,0x7c0f); +reg_write( DDR_REG_BASE +0x51fd3*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51fd4*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51fd5*4 +0x02000000,0x666); +reg_write( DDR_REG_BASE +0x51fd6*4 +0x02000000,0x8862); +reg_write( DDR_REG_BASE +0x51fd7*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51fd8*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51fd9*4 +0x02000000,0x666); +reg_write( DDR_REG_BASE +0x51fda*4 +0x02000000,0x88a1); +reg_write( DDR_REG_BASE +0x51fdb*4 +0x02000000,0x7993); +reg_write( DDR_REG_BASE +0x51fdc*4 +0x02000000,0x4399); +reg_write( DDR_REG_BASE +0x51fdd*4 +0x02000000,0xf00b); +reg_write( DDR_REG_BASE +0x51fde*4 +0x02000000,0x2454); +reg_write( DDR_REG_BASE +0x51fdf*4 +0x02000000,0x390b); +reg_write( DDR_REG_BASE +0x51fe0*4 +0x02000000,0x7c14); +reg_write( DDR_REG_BASE +0x51fe1*4 +0x02000000,0x23f4); +reg_write( DDR_REG_BASE +0x51fe2*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x51fe3*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x51fe4*4 +0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x51fe5*4 +0x02000000,0x7842); +reg_write( DDR_REG_BASE +0x51fe6*4 +0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x51fe7*4 +0x02000000,0x78af); +reg_write( DDR_REG_BASE +0x51fe8*4 +0x02000000,0xbed); +reg_write( DDR_REG_BASE +0x51fe9*4 +0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x51fea*4 +0x02000000,0xc488); +reg_write( DDR_REG_BASE +0x51feb*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x51fec*4 +0x02000000,0xf044); +reg_write( DDR_REG_BASE +0x51fed*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51fee*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51fef*4 +0x02000000,0x666); +reg_write( DDR_REG_BASE +0x51ff0*4 +0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x51ff1*4 +0x02000000,0x7914); +reg_write( DDR_REG_BASE +0x51ff2*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51ff3*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51ff4*4 +0x02000000,0x666); +reg_write( DDR_REG_BASE +0x51ff5*4 +0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x51ff6*4 +0x02000000,0x8b); +reg_write( DDR_REG_BASE +0x51ff7*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51ff8*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51ff9*4 +0x02000000,0x666); +reg_write( DDR_REG_BASE +0x51ffa*4 +0x02000000,0x8843); +reg_write( DDR_REG_BASE +0x51ffb*4 +0x02000000,0xf026); +reg_write( DDR_REG_BASE +0x51ffc*4 +0x02000000,0x9180); +reg_write( DDR_REG_BASE +0x51ffd*4 +0x02000000,0x7463); +reg_write( DDR_REG_BASE +0x51ffe*4 +0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x51fff*4 +0x02000000,0x8306); +reg_write( DDR_REG_BASE +0x52000*4 +0x02000000,0x34); +reg_write( DDR_REG_BASE +0x52001*4 +0x02000000,0x24); +reg_write( DDR_REG_BASE +0x52002*4 +0x02000000,0xb180); +reg_write( DDR_REG_BASE +0x52003*4 +0x02000000,0x829); +reg_write( DDR_REG_BASE +0x52004*4 +0x02000000,0x813); +reg_write( DDR_REG_BASE +0x52005*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x52006*4 +0x02000000,0xf8f); +reg_write( DDR_REG_BASE +0x52007*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52008*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52009*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x5200a*4 +0x02000000,0x7f05); +reg_write( DDR_REG_BASE +0x5200b*4 +0x02000000,0x200a); +reg_write( DDR_REG_BASE +0x5200c*4 +0x02000000,0x780); +reg_write( DDR_REG_BASE +0x5200d*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x5200e*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5200f*4 +0x02000000,0x78e5); +reg_write( DDR_REG_BASE +0x52010*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52011*4 +0x02000000,0xb891); +reg_write( DDR_REG_BASE +0x52012*4 +0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x52013*4 +0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x52014*4 +0x02000000,0xb080); +reg_write( DDR_REG_BASE +0x52015*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x52016*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52017*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52018*4 +0x02000000,0xfe00); +reg_write( DDR_REG_BASE +0x52019*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x5201a*4 +0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x5201b*4 +0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x5201c*4 +0x02000000,0x7224); +reg_write( DDR_REG_BASE +0x5201d*4 +0x02000000,0xec1); +reg_write( DDR_REG_BASE +0x5201e*4 +0x02000000,0xb094); +reg_write( DDR_REG_BASE +0x5201f*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x52020*4 +0x02000000,0x7b4f); +reg_write( DDR_REG_BASE +0x52021*4 +0x02000000,0xbfb); +reg_write( DDR_REG_BASE +0x52022*4 +0x02000000,0x90e5); +reg_write( DDR_REG_BASE +0x52023*4 +0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x52024*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x52025*4 +0x02000000,0xcda); +reg_write( DDR_REG_BASE +0x52026*4 +0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x52027*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52028*4 +0x02000000,0xc202); +reg_write( DDR_REG_BASE +0x52029*4 +0x02000000,0xc188); +reg_write( DDR_REG_BASE +0x5202a*4 +0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x5202b*4 +0x02000000,0x43); +reg_write( DDR_REG_BASE +0x5202c*4 +0x02000000,0xb5a); +reg_write( DDR_REG_BASE +0x5202d*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5202e*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x5202f*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x52030*4 +0x02000000,0x7dcf); +reg_write( DDR_REG_BASE +0x52031*4 +0x02000000,0xd7b); +reg_write( DDR_REG_BASE +0x52032*4 +0x02000000,0x97f4); +reg_write( DDR_REG_BASE +0x52033*4 +0x02000000,0xc188); +reg_write( DDR_REG_BASE +0x52034*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52035*4 +0x02000000,0xc192); +reg_write( DDR_REG_BASE +0x52036*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52037*4 +0x02000000,0xdee); +reg_write( DDR_REG_BASE +0x52038*4 +0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x52039*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x5203a*4 +0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x5203b*4 +0x02000000,0xc202); +reg_write( DDR_REG_BASE +0x5203c*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x5203d*4 +0x02000000,0xc192); +reg_write( DDR_REG_BASE +0x5203e*4 +0x02000000,0xb36); +reg_write( DDR_REG_BASE +0x5203f*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x52040*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x52041*4 +0x02000000,0xaee); +reg_write( DDR_REG_BASE +0x52042*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x52043*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52044*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52045*4 +0x02000000,0x7001); +reg_write( DDR_REG_BASE +0x52046*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52047*4 +0x02000000,0x674); +reg_write( DDR_REG_BASE +0x52048*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52049*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5204a*4 +0x02000000,0xace); +reg_write( DDR_REG_BASE +0x5204b*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5204c*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x5204d*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x5204e*4 +0x02000000,0xe81c); +reg_write( DDR_REG_BASE +0x5204f*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52050*4 +0x02000000,0x819); +reg_write( DDR_REG_BASE +0x52051*4 +0x02000000,0xb1); +reg_write( DDR_REG_BASE +0x52052*4 +0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x52053*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52054*4 +0x02000000,0xc203); +reg_write( DDR_REG_BASE +0x52055*4 +0x02000000,0xc305); +reg_write( DDR_REG_BASE +0x52056*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52057*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x52058*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52059*4 +0x02000000,0x1f); +reg_write( DDR_REG_BASE +0x5205a*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x5205b*4 +0x02000000,0xf00b); +reg_write( DDR_REG_BASE +0x5205c*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x5205d*4 +0x02000000,0xc303); +reg_write( DDR_REG_BASE +0x5205e*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5205f*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52060*4 +0x02000000,0xb995); +reg_write( DDR_REG_BASE +0x52061*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52062*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52063*4 +0x02000000,0x6841); +reg_write( DDR_REG_BASE +0x52064*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x52065*4 +0x02000000,0x92a); +reg_write( DDR_REG_BASE +0x52066*4 +0x02000000,0xfe4f); +reg_write( DDR_REG_BASE +0x52067*4 +0x02000000,0xb92); +reg_write( DDR_REG_BASE +0x52068*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x52069*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x5206a*4 +0x02000000,0xc0bc); +reg_write( DDR_REG_BASE +0x5206b*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x5206c*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x5206d*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5206e*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5206f*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52070*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52071*4 +0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x52072*4 +0x02000000,0x3806); +reg_write( DDR_REG_BASE +0x52073*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52074*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52075*4 +0x02000000,0x640); +reg_write( DDR_REG_BASE +0x52076*4 +0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x52077*4 +0x02000000,0xc24a); +reg_write( DDR_REG_BASE +0x52078*4 +0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x52079*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5207a*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5207b*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5207c*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x5207d*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x5207e*4 +0x02000000,0xc81); +reg_write( DDR_REG_BASE +0x5207f*4 +0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x52080*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x52081*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52082*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52083*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52084*4 +0x02000000,0x674); +reg_write( DDR_REG_BASE +0x52085*4 +0x02000000,0x8812); +reg_write( DDR_REG_BASE +0x52086*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52087*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x52088*4 +0x02000000,0xf4e); +reg_write( DDR_REG_BASE +0x52089*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5208a*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x5208b*4 +0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x5208c*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x5208d*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5208e*4 +0x02000000,0x710f); +reg_write( DDR_REG_BASE +0x5208f*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52090*4 +0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x52091*4 +0x02000000,0xc302); +reg_write( DDR_REG_BASE +0x52092*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52093*4 +0x02000000,0x708e); +reg_write( DDR_REG_BASE +0x52094*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52095*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52096*4 +0x02000000,0x2338); +reg_write( DDR_REG_BASE +0x52097*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x52098*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52099*4 +0x02000000,0x1b); +reg_write( DDR_REG_BASE +0x5209a*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x5209b*4 +0x02000000,0x90e); +reg_write( DDR_REG_BASE +0x5209c*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5209d*4 +0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x5209e*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5209f*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x520a0*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x520a1*4 +0x02000000,0x1801); +reg_write( DDR_REG_BASE +0x520a2*4 +0x02000000,0x6c2); +reg_write( DDR_REG_BASE +0x520a3*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x520a4*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x520a5*4 +0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x520a6*4 +0x02000000,0x37c0); +reg_write( DDR_REG_BASE +0x520a7*4 +0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x520a8*4 +0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x520a9*4 +0x02000000,0x801); +reg_write( DDR_REG_BASE +0x520aa*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x520ab*4 +0x02000000,0x7dbb); +reg_write( DDR_REG_BASE +0x520ac*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x520ad*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x520ae*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x520af*4 +0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x520b0*4 +0x02000000,0x110d); +reg_write( DDR_REG_BASE +0x520b1*4 +0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x520b2*4 +0x02000000,0x1f8e); +reg_write( DDR_REG_BASE +0x520b3*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x520b4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x520b5*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x520b6*4 +0x02000000,0x8040); +reg_write( DDR_REG_BASE +0x520b7*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x520b8*4 +0x02000000,0x7001); +reg_write( DDR_REG_BASE +0x520b9*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x520ba*4 +0x02000000,0x674); +reg_write( DDR_REG_BASE +0x520bb*4 +0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x520bc*4 +0x02000000,0xf205); +reg_write( DDR_REG_BASE +0x520bd*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x520be*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x520bf*4 +0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x520c0*4 +0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x520c1*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x520c2*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x520c3*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x520c4*4 +0x02000000,0x9da); +reg_write( DDR_REG_BASE +0x520c5*4 +0x02000000,0xff0f); +reg_write( DDR_REG_BASE +0x520c6*4 +0x02000000,0x250f); +reg_write( DDR_REG_BASE +0x520c7*4 +0x02000000,0x16c0); +reg_write( DDR_REG_BASE +0x520c8*4 +0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x520c9*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x520ca*4 +0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x520cb*4 +0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x520cc*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x520cd*4 +0x02000000,0xf7e); +reg_write( DDR_REG_BASE +0x520ce*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x520cf*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x520d0*4 +0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x520d1*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x520d2*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x520d3*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x520d4*4 +0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x520d5*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x520d6*4 +0x02000000,0x8); +reg_write( DDR_REG_BASE +0x520d7*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x520d8*4 +0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x520d9*4 +0x02000000,0xe1f2); +reg_write( DDR_REG_BASE +0x520da*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x520db*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x520dc*4 +0x02000000,0x228a); +reg_write( DDR_REG_BASE +0x520dd*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x520de*4 +0x02000000,0xb101); +reg_write( DDR_REG_BASE +0x520df*4 +0x02000000,0xb142); +reg_write( DDR_REG_BASE +0x520e0*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x520e1*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x520e2*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x520e3*4 +0x02000000,0xfec4); +reg_write( DDR_REG_BASE +0x520e4*4 +0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x520e5*4 +0x02000000,0xd1e); +reg_write( DDR_REG_BASE +0x520e6*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x520e7*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x520e8*4 +0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x520e9*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x520ea*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x520eb*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x520ec*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x520ed*4 +0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x520ee*4 +0x02000000,0xed2); +reg_write( DDR_REG_BASE +0x520ef*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x520f0*4 +0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x520f1*4 +0x02000000,0xc08e); +reg_write( DDR_REG_BASE +0x520f2*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x520f3*4 +0x02000000,0x38); +reg_write( DDR_REG_BASE +0x520f4*4 +0x02000000,0xda5a); +reg_write( DDR_REG_BASE +0x520f5*4 +0x02000000,0xd76); +reg_write( DDR_REG_BASE +0x520f6*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x520f7*4 +0x02000000,0xc78e); +reg_write( DDR_REG_BASE +0x520f8*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x520f9*4 +0x02000000,0x120c); +reg_write( DDR_REG_BASE +0x520fa*4 +0x02000000,0x309f); +reg_write( DDR_REG_BASE +0x520fb*4 +0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x520fc*4 +0x02000000,0xc0c); +reg_write( DDR_REG_BASE +0x520fd*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x520fe*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x520ff*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x52100*4 +0x02000000,0x8864); +reg_write( DDR_REG_BASE +0x52101*4 +0x02000000,0x7cc5); +reg_write( DDR_REG_BASE +0x52102*4 +0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x52103*4 +0x02000000,0x480); +reg_write( DDR_REG_BASE +0x52104*4 +0x02000000,0x671f); +reg_write( DDR_REG_BASE +0x52105*4 +0x02000000,0x770c); +reg_write( DDR_REG_BASE +0x52106*4 +0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x52107*4 +0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x52108*4 +0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x52109*4 +0x02000000,0x37c0); +reg_write( DDR_REG_BASE +0x5210a*4 +0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x5210b*4 +0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x5210c*4 +0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x5210d*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x5210e*4 +0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x5210f*4 +0x02000000,0x3780); +reg_write( DDR_REG_BASE +0x52110*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52111*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52112*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x52113*4 +0x02000000,0x88a5); +reg_write( DDR_REG_BASE +0x52114*4 +0x02000000,0x2653); +reg_write( DDR_REG_BASE +0x52115*4 +0x02000000,0x311e); +reg_write( DDR_REG_BASE +0x52116*4 +0x02000000,0xf026); +reg_write( DDR_REG_BASE +0x52117*4 +0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x52118*4 +0x02000000,0x37c2); +reg_write( DDR_REG_BASE +0x52119*4 +0x02000000,0xea06); +reg_write( DDR_REG_BASE +0x5211a*4 +0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x5211b*4 +0x02000000,0xa01); +reg_write( DDR_REG_BASE +0x5211c*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x5211d*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5211e*4 +0x02000000,0x2140); +reg_write( DDR_REG_BASE +0x5211f*4 +0x02000000,0x4b); +reg_write( DDR_REG_BASE +0x52120*4 +0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x52121*4 +0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x52122*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52123*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52124*4 +0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x52125*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52126*4 +0x02000000,0x7a85); +reg_write( DDR_REG_BASE +0x52127*4 +0x02000000,0x7945); +reg_write( DDR_REG_BASE +0x52128*4 +0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x52129*4 +0x02000000,0xb991); +reg_write( DDR_REG_BASE +0x5212a*4 +0x02000000,0xb99c); +reg_write( DDR_REG_BASE +0x5212b*4 +0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x5212c*4 +0x02000000,0x9140); +reg_write( DDR_REG_BASE +0x5212d*4 +0x02000000,0x2604); +reg_write( DDR_REG_BASE +0x5212e*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x5212f*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x52130*4 +0x02000000,0x795d); +reg_write( DDR_REG_BASE +0x52131*4 +0x02000000,0x216c); +reg_write( DDR_REG_BASE +0x52132*4 +0x02000000,0x101); +reg_write( DDR_REG_BASE +0x52133*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x52134*4 +0x02000000,0x1f02); +reg_write( DDR_REG_BASE +0x52135*4 +0x02000000,0x1014); +reg_write( DDR_REG_BASE +0x52136*4 +0x02000000,0x4161); +reg_write( DDR_REG_BASE +0x52137*4 +0x02000000,0x9c3); +reg_write( DDR_REG_BASE +0x52138*4 +0x02000000,0x8274); +reg_write( DDR_REG_BASE +0x52139*4 +0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x5213a*4 +0x02000000,0xc7f); +reg_write( DDR_REG_BASE +0x5213b*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x5213c*4 +0x02000000,0x7e6f); +reg_write( DDR_REG_BASE +0x5213d*4 +0x02000000,0xdf7); +reg_write( DDR_REG_BASE +0x5213e*4 +0x02000000,0x93a5); +reg_write( DDR_REG_BASE +0x5213f*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52140*4 +0x02000000,0xca66); +reg_write( DDR_REG_BASE +0x52141*4 +0x02000000,0xf0e6); +reg_write( DDR_REG_BASE +0x52142*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52143*4 +0x02000000,0xbd6); +reg_write( DDR_REG_BASE +0x52144*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52145*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52146*4 +0x02000000,0xc107); +reg_write( DDR_REG_BASE +0x52147*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52148*4 +0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x52149*4 +0x02000000,0xf3e); +reg_write( DDR_REG_BASE +0x5214a*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5214b*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5214c*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5214d*4 +0x02000000,0xa9a); +reg_write( DDR_REG_BASE +0x5214e*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x5214f*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52150*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52151*4 +0x02000000,0xe9a); +reg_write( DDR_REG_BASE +0x52152*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52153*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52154*4 +0x02000000,0xca0c); +reg_write( DDR_REG_BASE +0x52155*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52156*4 +0x02000000,0xc245); +reg_write( DDR_REG_BASE +0x52157*4 +0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x52158*4 +0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x52159*4 +0x02000000,0x3ec1); +reg_write( DDR_REG_BASE +0x5215a*4 +0x02000000,0x615b); +reg_write( DDR_REG_BASE +0x5215b*4 +0x02000000,0xc18e); +reg_write( DDR_REG_BASE +0x5215c*4 +0x02000000,0x6149); +reg_write( DDR_REG_BASE +0x5215d*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x5215e*4 +0x02000000,0xab20); +reg_write( DDR_REG_BASE +0x5215f*4 +0x02000000,0x228c); +reg_write( DDR_REG_BASE +0x52160*4 +0x02000000,0x8d02); +reg_write( DDR_REG_BASE +0x52161*4 +0x02000000,0xf7b8); +reg_write( DDR_REG_BASE +0x52162*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52163*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x52164*4 +0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x52165*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x52166*4 +0x02000000,0xea05); +reg_write( DDR_REG_BASE +0x52167*4 +0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x52168*4 +0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x52169*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x5216a*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5216b*4 +0x02000000,0xc04d); +reg_write( DDR_REG_BASE +0x5216c*4 +0x02000000,0xf0a7); +reg_write( DDR_REG_BASE +0x5216d*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5216e*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5216f*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x52170*4 +0x02000000,0x8844); +reg_write( DDR_REG_BASE +0x52171*4 +0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x52172*4 +0x02000000,0x3ec0); +reg_write( DDR_REG_BASE +0x52173*4 +0x02000000,0x225f); +reg_write( DDR_REG_BASE +0x52174*4 +0x02000000,0x481); +reg_write( DDR_REG_BASE +0x52175*4 +0x02000000,0x603c); +reg_write( DDR_REG_BASE +0x52176*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52177*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52178*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x52179*4 +0x02000000,0x8825); +reg_write( DDR_REG_BASE +0x5217a*4 +0x02000000,0xf031); +reg_write( DDR_REG_BASE +0x5217b*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x5217c*4 +0x02000000,0x855); +reg_write( DDR_REG_BASE +0x5217d*4 +0x02000000,0x36e); +reg_write( DDR_REG_BASE +0x5217e*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x5217f*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52180*4 +0x02000000,0x8); +reg_write( DDR_REG_BASE +0x52181*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x52182*4 +0x02000000,0xf8f); +reg_write( DDR_REG_BASE +0x52183*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52184*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52185*4 +0x02000000,0x9cc0); +reg_write( DDR_REG_BASE +0x52186*4 +0x02000000,0x78e5); +reg_write( DDR_REG_BASE +0x52187*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52188*4 +0x02000000,0xf8f); +reg_write( DDR_REG_BASE +0x52189*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x5218a*4 +0x02000000,0x64); +reg_write( DDR_REG_BASE +0x5218b*4 +0x02000000,0xe21); +reg_write( DDR_REG_BASE +0x5218c*4 +0x02000000,0x1012); +reg_write( DDR_REG_BASE +0x5218d*4 +0x02000000,0x260b); +reg_write( DDR_REG_BASE +0x5218e*4 +0x02000000,0x9f80); +reg_write( DDR_REG_BASE +0x5218f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52190*4 +0x02000000,0x1f00); +reg_write( DDR_REG_BASE +0x52191*4 +0x02000000,0xf20d); +reg_write( DDR_REG_BASE +0x52192*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52193*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52194*4 +0x02000000,0xfe00); +reg_write( DDR_REG_BASE +0x52195*4 +0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x52196*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52197*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52198*4 +0x02000000,0x1c1f); +reg_write( DDR_REG_BASE +0x52199*4 +0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x5219a*4 +0x02000000,0x1f00); +reg_write( DDR_REG_BASE +0x5219b*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x5219c*4 +0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x5219d*4 +0x02000000,0x265e); +reg_write( DDR_REG_BASE +0x5219e*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x5219f*4 +0x02000000,0xbec4); +reg_write( DDR_REG_BASE +0x521a0*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x521a1*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x521a2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x521a3*4 +0x02000000,0xfc00); +reg_write( DDR_REG_BASE +0x521a4*4 +0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x521a5*4 +0x02000000,0xb700); +reg_write( DDR_REG_BASE +0x521a6*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x521a7*4 +0x02000000,0x7285); +reg_write( DDR_REG_BASE +0x521a8*4 +0x02000000,0xda7); +reg_write( DDR_REG_BASE +0x521a9*4 +0x02000000,0x9254); +reg_write( DDR_REG_BASE +0x521aa*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x521ab*4 +0x02000000,0x7b4f); +reg_write( DDR_REG_BASE +0x521ac*4 +0x02000000,0x9f9); +reg_write( DDR_REG_BASE +0x521ad*4 +0x02000000,0x80e5); +reg_write( DDR_REG_BASE +0x521ae*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x521af*4 +0x02000000,0x9c6); +reg_write( DDR_REG_BASE +0x521b0*4 +0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x521b1*4 +0x02000000,0x986); +reg_write( DDR_REG_BASE +0x521b2*4 +0x02000000,0xfe0f); +reg_write( DDR_REG_BASE +0x521b3*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x521b4*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x521b5*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x521b6*4 +0x02000000,0x8864); +reg_write( DDR_REG_BASE +0x521b7*4 +0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x521b8*4 +0x02000000,0x3ecf); +reg_write( DDR_REG_BASE +0x521b9*4 +0x02000000,0x43cb); +reg_write( DDR_REG_BASE +0x521ba*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x521bb*4 +0x02000000,0x6dc); +reg_write( DDR_REG_BASE +0x521bc*4 +0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x521bd*4 +0x02000000,0x480); +reg_write( DDR_REG_BASE +0x521be*4 +0x02000000,0x671f); +reg_write( DDR_REG_BASE +0x521bf*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x521c0*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x521c1*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x521c2*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x521c3*4 +0x02000000,0x9f); +reg_write( DDR_REG_BASE +0x521c4*4 +0x02000000,0xf045); +reg_write( DDR_REG_BASE +0x521c5*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x521c6*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x521c7*4 +0x02000000,0xf040); +reg_write( DDR_REG_BASE +0x521c8*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x521c9*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x521ca*4 +0x02000000,0x8); +reg_write( DDR_REG_BASE +0x521cb*4 +0x02000000,0x241a); +reg_write( DDR_REG_BASE +0x521cc*4 +0x02000000,0x1f81); +reg_write( DDR_REG_BASE +0x521cd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x521ce*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x521cf*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x521d0*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x521d1*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x521d2*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x521d3*4 +0x02000000,0x166); +reg_write( DDR_REG_BASE +0x521d4*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x521d5*4 +0x02000000,0xc103); +reg_write( DDR_REG_BASE +0x521d6*4 +0x02000000,0x218c); +reg_write( DDR_REG_BASE +0x521d7*4 +0x02000000,0x8004); +reg_write( DDR_REG_BASE +0x521d8*4 +0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x521d9*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x521da*4 +0x02000000,0xf402); +reg_write( DDR_REG_BASE +0x521db*4 +0x02000000,0x621a); +reg_write( DDR_REG_BASE +0x521dc*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x521dd*4 +0x02000000,0x849); +reg_write( DDR_REG_BASE +0x521de*4 +0x02000000,0x36e); +reg_write( DDR_REG_BASE +0x521df*4 +0x02000000,0x97c0); +reg_write( DDR_REG_BASE +0x521e0*4 +0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x521e1*4 +0x02000000,0xf386); +reg_write( DDR_REG_BASE +0x521e2*4 +0x02000000,0x38); +reg_write( DDR_REG_BASE +0x521e3*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x521e4*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x521e5*4 +0x02000000,0x1420); +reg_write( DDR_REG_BASE +0x521e6*4 +0x02000000,0x301e); +reg_write( DDR_REG_BASE +0x521e7*4 +0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x521e8*4 +0x02000000,0x80d); +reg_write( DDR_REG_BASE +0x521e9*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x521ea*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x521eb*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x521ec*4 +0x02000000,0x1340); +reg_write( DDR_REG_BASE +0x521ed*4 +0x02000000,0x109e); +reg_write( DDR_REG_BASE +0x521ee*4 +0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x521ef*4 +0x02000000,0xf088); +reg_write( DDR_REG_BASE +0x521f0*4 +0x02000000,0xf40e); +reg_write( DDR_REG_BASE +0x521f1*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x521f2*4 +0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x521f3*4 +0x02000000,0x3787); +reg_write( DDR_REG_BASE +0x521f4*4 +0x02000000,0x2314); +reg_write( DDR_REG_BASE +0x521f5*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x521f6*4 +0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x521f7*4 +0x02000000,0x2608); +reg_write( DDR_REG_BASE +0x521f8*4 +0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x521f9*4 +0x02000000,0xa821); +reg_write( DDR_REG_BASE +0x521fa*4 +0x02000000,0x8820); +reg_write( DDR_REG_BASE +0x521fb*4 +0x02000000,0x2609); +reg_write( DDR_REG_BASE +0x521fc*4 +0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x521fd*4 +0x02000000,0xa820); +reg_write( DDR_REG_BASE +0x521fe*4 +0x02000000,0x2380); +reg_write( DDR_REG_BASE +0x521ff*4 +0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x52200*4 +0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x52201*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x52202*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52203*4 +0x02000000,0x60d8); +reg_write( DDR_REG_BASE +0x52204*4 +0x02000000,0x1f02); +reg_write( DDR_REG_BASE +0x52205*4 +0x02000000,0x1014); +reg_write( DDR_REG_BASE +0x52206*4 +0x02000000,0xd85); +reg_write( DDR_REG_BASE +0x52207*4 +0x02000000,0x9254); +reg_write( DDR_REG_BASE +0x52208*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x52209*4 +0x02000000,0x7c6f); +reg_write( DDR_REG_BASE +0x5220a*4 +0x02000000,0xf77); +reg_write( DDR_REG_BASE +0x5220b*4 +0x02000000,0xb325); +reg_write( DDR_REG_BASE +0x5220c*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x5220d*4 +0x02000000,0xd22); +reg_write( DDR_REG_BASE +0x5220e*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5220f*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52210*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52211*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52212*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52213*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52214*4 +0x02000000,0xe09e); +reg_write( DDR_REG_BASE +0x52215*4 +0x02000000,0x6b2); +reg_write( DDR_REG_BASE +0x52216*4 +0x02000000,0xffce); +reg_write( DDR_REG_BASE +0x52217*4 +0x02000000,0xf42); +reg_write( DDR_REG_BASE +0x52218*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x52219*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5221a*4 +0x02000000,0xca15); +reg_write( DDR_REG_BASE +0x5221b*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5221c*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x5221d*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x5221e*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x5221f*4 +0x02000000,0xc108); +reg_write( DDR_REG_BASE +0x52220*4 +0x02000000,0xed05); +reg_write( DDR_REG_BASE +0x52221*4 +0x02000000,0xbd61); +reg_write( DDR_REG_BASE +0x52222*4 +0x02000000,0xdff); +reg_write( DDR_REG_BASE +0x52223*4 +0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x52224*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52225*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x52226*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x52227*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52228*4 +0x02000000,0xc10c); +reg_write( DDR_REG_BASE +0x52229*4 +0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x5222a*4 +0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x5222b*4 +0x02000000,0x792f); +reg_write( DDR_REG_BASE +0x5222c*4 +0x02000000,0xca67); +reg_write( DDR_REG_BASE +0x5222d*4 +0x02000000,0xc144); +reg_write( DDR_REG_BASE +0x5222e*4 +0x02000000,0xc108); +reg_write( DDR_REG_BASE +0x5222f*4 +0x02000000,0x7110); +reg_write( DDR_REG_BASE +0x52230*4 +0x02000000,0x624); +reg_write( DDR_REG_BASE +0x52231*4 +0x02000000,0xffce); +reg_write( DDR_REG_BASE +0x52232*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52233*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x52234*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52235*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x52236*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52237*4 +0x02000000,0xc81); +reg_write( DDR_REG_BASE +0x52238*4 +0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x52239*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x5223a*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x5223b*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5223c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5223d*4 +0x02000000,0x674); +reg_write( DDR_REG_BASE +0x5223e*4 +0x02000000,0x8832); +reg_write( DDR_REG_BASE +0x5223f*4 +0x02000000,0xd52); +reg_write( DDR_REG_BASE +0x52240*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x52241*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52242*4 +0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x52243*4 +0x02000000,0xe811); +reg_write( DDR_REG_BASE +0x52244*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52245*4 +0x02000000,0xc302); +reg_write( DDR_REG_BASE +0x52246*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52247*4 +0x02000000,0x1d); +reg_write( DDR_REG_BASE +0x52248*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52249*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5224a*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5224b*4 +0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x5224c*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5224d*4 +0x02000000,0xd5a); +reg_write( DDR_REG_BASE +0x5224e*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5224f*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x52250*4 +0x02000000,0xfbe); +reg_write( DDR_REG_BASE +0x52251*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52252*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52253*4 +0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x52254*4 +0x02000000,0xe80a); +reg_write( DDR_REG_BASE +0x52255*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52256*4 +0x02000000,0x7001); +reg_write( DDR_REG_BASE +0x52257*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52258*4 +0x02000000,0x674); +reg_write( DDR_REG_BASE +0x52259*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x5225a*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5225b*4 +0x02000000,0xeae); +reg_write( DDR_REG_BASE +0x5225c*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5225d*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x5225e*4 +0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x5225f*4 +0x02000000,0x3806); +reg_write( DDR_REG_BASE +0x52260*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52261*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52262*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52263*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52264*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52265*4 +0x02000000,0x1210); +reg_write( DDR_REG_BASE +0x52266*4 +0x02000000,0x308d); +reg_write( DDR_REG_BASE +0x52267*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x52268*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x52269*4 +0x02000000,0x1a10); +reg_write( DDR_REG_BASE +0x5226a*4 +0x02000000,0x3382); +reg_write( DDR_REG_BASE +0x5226b*4 +0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x5226c*4 +0x02000000,0x26f0); +reg_write( DDR_REG_BASE +0x5226d*4 +0x02000000,0x73c0); +reg_write( DDR_REG_BASE +0x5226e*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5226f*4 +0x02000000,0x1ca4); +reg_write( DDR_REG_BASE +0x52270*4 +0x02000000,0x8d2); +reg_write( DDR_REG_BASE +0x52271*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x52272*4 +0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x52273*4 +0x02000000,0xcc36); +reg_write( DDR_REG_BASE +0x52274*4 +0x02000000,0xff1); +reg_write( DDR_REG_BASE +0x52275*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52276*4 +0x02000000,0x1a10); +reg_write( DDR_REG_BASE +0x52277*4 +0x02000000,0x3342); +reg_write( DDR_REG_BASE +0x52278*4 +0x02000000,0x1a36); +reg_write( DDR_REG_BASE +0x52279*4 +0x02000000,0x339c); +reg_write( DDR_REG_BASE +0x5227a*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5227b*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5227c*4 +0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x5227d*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x5227e*4 +0x02000000,0x1ea); +reg_write( DDR_REG_BASE +0x5227f*4 +0x02000000,0x9340); +reg_write( DDR_REG_BASE +0x52280*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52281*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52282*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52283*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52284*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52285*4 +0x02000000,0xfe00); +reg_write( DDR_REG_BASE +0x52286*4 +0x02000000,0x2204); +reg_write( DDR_REG_BASE +0x52287*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x52288*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52289*4 +0x02000000,0xc0ff); +reg_write( DDR_REG_BASE +0x5228a*4 +0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x5228b*4 +0x02000000,0x9341); +reg_write( DDR_REG_BASE +0x5228c*4 +0x02000000,0xb300); +reg_write( DDR_REG_BASE +0x5228d*4 +0x02000000,0xb962); +reg_write( DDR_REG_BASE +0x5228e*4 +0x02000000,0x226c); +reg_write( DDR_REG_BASE +0x5228f*4 +0x02000000,0x140); +reg_write( DDR_REG_BASE +0x52290*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52291*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x52292*4 +0x02000000,0xb301); +reg_write( DDR_REG_BASE +0x52293*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52294*4 +0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x52295*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52296*4 +0x02000000,0x710d); +reg_write( DDR_REG_BASE +0x52297*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52298*4 +0x02000000,0x6); +reg_write( DDR_REG_BASE +0x52299*4 +0x02000000,0xe56d); +reg_write( DDR_REG_BASE +0x5229a*4 +0x02000000,0x2d85); +reg_write( DDR_REG_BASE +0x5229b*4 +0x02000000,0x1b81); +reg_write( DDR_REG_BASE +0x5229c*4 +0x02000000,0x2553); +reg_write( DDR_REG_BASE +0x5229d*4 +0x02000000,0x9041); +reg_write( DDR_REG_BASE +0x5229e*4 +0x02000000,0xf205); +reg_write( DDR_REG_BASE +0x5229f*4 +0x02000000,0x78af); +reg_write( DDR_REG_BASE +0x522a0*4 +0x02000000,0x214e); +reg_write( DDR_REG_BASE +0x522a1*4 +0x02000000,0x10d); +reg_write( DDR_REG_BASE +0x522a2*4 +0x02000000,0x651d); +reg_write( DDR_REG_BASE +0x522a3*4 +0x02000000,0x7aaf); +reg_write( DDR_REG_BASE +0x522a4*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x522a5*4 +0x02000000,0x147); +reg_write( DDR_REG_BASE +0x522a6*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x522a7*4 +0x02000000,0xca6); +reg_write( DDR_REG_BASE +0x522a8*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x522a9*4 +0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x522aa*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x522ab*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x522ac*4 +0x02000000,0x664); +reg_write( DDR_REG_BASE +0x522ad*4 +0x02000000,0xa8a0); +reg_write( DDR_REG_BASE +0x522ae*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x522af*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x522b0*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x522b1*4 +0x02000000,0x266f); +reg_write( DDR_REG_BASE +0x522b2*4 +0x02000000,0x15c3); +reg_write( DDR_REG_BASE +0x522b3*4 +0x02000000,0x8e40); +reg_write( DDR_REG_BASE +0x522b4*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x522b5*4 +0x02000000,0xea17); +reg_write( DDR_REG_BASE +0x522b6*4 +0x02000000,0x87a); +reg_write( DDR_REG_BASE +0x522b7*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x522b8*4 +0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x522b9*4 +0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x522ba*4 +0x02000000,0xe887); +reg_write( DDR_REG_BASE +0x522bb*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x522bc*4 +0x02000000,0x16e); +reg_write( DDR_REG_BASE +0x522bd*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x522be*4 +0x02000000,0xcc6); +reg_write( DDR_REG_BASE +0x522bf*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x522c0*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x522c1*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x522c2*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x522c3*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x522c4*4 +0x02000000,0x7f05); +reg_write( DDR_REG_BASE +0x522c5*4 +0x02000000,0x78bb); +reg_write( DDR_REG_BASE +0x522c6*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x522c7*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x522c8*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x522c9*4 +0x02000000,0xfe92); +reg_write( DDR_REG_BASE +0x522ca*4 +0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x522cb*4 +0x02000000,0x16ff); +reg_write( DDR_REG_BASE +0x522cc*4 +0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x522cd*4 +0x02000000,0xea18); +reg_write( DDR_REG_BASE +0x522ce*4 +0x02000000,0x84a); +reg_write( DDR_REG_BASE +0x522cf*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x522d0*4 +0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x522d1*4 +0x02000000,0x228c); +reg_write( DDR_REG_BASE +0x522d2*4 +0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x522d3*4 +0x02000000,0xf209); +reg_write( DDR_REG_BASE +0x522d4*4 +0x02000000,0xe888); +reg_write( DDR_REG_BASE +0x522d5*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x522d6*4 +0x02000000,0x16f); +reg_write( DDR_REG_BASE +0x522d7*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x522d8*4 +0x02000000,0xc92); +reg_write( DDR_REG_BASE +0x522d9*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x522da*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x522db*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x522dc*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x522dd*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x522de*4 +0x02000000,0x79bb); +reg_write( DDR_REG_BASE +0x522df*4 +0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x522e0*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x522e1*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x522e2*4 +0x02000000,0xfe9a); +reg_write( DDR_REG_BASE +0x522e3*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x522e4*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x522e5*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x522e6*4 +0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x522e7*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x522e8*4 +0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x522e9*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x522ea*4 +0x02000000,0x9); +reg_write( DDR_REG_BASE +0x522eb*4 +0x02000000,0xea1a); +reg_write( DDR_REG_BASE +0x522ec*4 +0x02000000,0xa23); +reg_write( DDR_REG_BASE +0x522ed*4 +0x02000000,0xa30); +reg_write( DDR_REG_BASE +0x522ee*4 +0x02000000,0x720c); +reg_write( DDR_REG_BASE +0x522ef*4 +0x02000000,0x228c); +reg_write( DDR_REG_BASE +0x522f0*4 +0x02000000,0x8c03); +reg_write( DDR_REG_BASE +0x522f1*4 +0x02000000,0xf20c); +reg_write( DDR_REG_BASE +0x522f2*4 +0x02000000,0xe2f8); +reg_write( DDR_REG_BASE +0x522f3*4 +0x02000000,0xf404); +reg_write( DDR_REG_BASE +0x522f4*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x522f5*4 +0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x522f6*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x522f7*4 +0x02000000,0x170); +reg_write( DDR_REG_BASE +0x522f8*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x522f9*4 +0x02000000,0xc52); +reg_write( DDR_REG_BASE +0x522fa*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x522fb*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x522fc*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x522fd*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x522fe*4 +0x02000000,0x401); +reg_write( DDR_REG_BASE +0x522ff*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52300*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52301*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52302*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52303*4 +0x02000000,0xe0a0); +reg_write( DDR_REG_BASE +0x52304*4 +0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x52305*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52306*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52307*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52308*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52309*4 +0x02000000,0xc1a2); +reg_write( DDR_REG_BASE +0x5230a*4 +0x02000000,0x4628); +reg_write( DDR_REG_BASE +0x5230b*4 +0x02000000,0x2009); +reg_write( DDR_REG_BASE +0x5230c*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x5230d*4 +0x02000000,0xab7); +reg_write( DDR_REG_BASE +0x5230e*4 +0x02000000,0x65); +reg_write( DDR_REG_BASE +0x5230f*4 +0x02000000,0x4748); +reg_write( DDR_REG_BASE +0x52310*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52311*4 +0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x52312*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52313*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52314*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x52315*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52316*4 +0x02000000,0x474); +reg_write( DDR_REG_BASE +0x52317*4 +0x02000000,0x78e2); +reg_write( DDR_REG_BASE +0x52318*4 +0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x52319*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x5231a*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5231b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5231c*4 +0x02000000,0x25f4); +reg_write( DDR_REG_BASE +0x5231d*4 +0x02000000,0x13c3); +reg_write( DDR_REG_BASE +0x5231e*4 +0x02000000,0x25f4); +reg_write( DDR_REG_BASE +0x5231f*4 +0x02000000,0x1002); +reg_write( DDR_REG_BASE +0x52320*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52321*4 +0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x52322*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x52323*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52324*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52325*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x52326*4 +0x02000000,0xba6); +reg_write( DDR_REG_BASE +0x52327*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52328*4 +0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x52329*4 +0x02000000,0x7ee2); +reg_write( DDR_REG_BASE +0x5232a*4 +0x02000000,0x25f4); +reg_write( DDR_REG_BASE +0x5232b*4 +0x02000000,0x1383); +reg_write( DDR_REG_BASE +0x5232c*4 +0x02000000,0x25f4); +reg_write( DDR_REG_BASE +0x5232d*4 +0x02000000,0x13c2); +reg_write( DDR_REG_BASE +0x5232e*4 +0x02000000,0x234f); +reg_write( DDR_REG_BASE +0x5232f*4 +0x02000000,0x3401); +reg_write( DDR_REG_BASE +0x52330*4 +0x02000000,0xb92); +reg_write( DDR_REG_BASE +0x52331*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52332*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x52333*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52334*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52335*4 +0x02000000,0x667); +reg_write( DDR_REG_BASE +0x52336*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x52337*4 +0x02000000,0x8b); +reg_write( DDR_REG_BASE +0x52338*4 +0x02000000,0x8840); +reg_write( DDR_REG_BASE +0x52339*4 +0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x5233a*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5233b*4 +0x02000000,0x4a8); +reg_write( DDR_REG_BASE +0x5233c*4 +0x02000000,0xf026); +reg_write( DDR_REG_BASE +0x5233d*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5233e*4 +0x02000000,0x666c); +reg_write( DDR_REG_BASE +0x5233f*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x52340*4 +0x02000000,0x249a); +reg_write( DDR_REG_BASE +0x52341*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x52342*4 +0x02000000,0x6068); +reg_write( DDR_REG_BASE +0x52343*4 +0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x52344*4 +0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x52345*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52346*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52347*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52348*4 +0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x52349*4 +0x02000000,0x8); +reg_write( DDR_REG_BASE +0x5234a*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x5234b*4 +0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x5234c*4 +0x02000000,0xf); +reg_write( DDR_REG_BASE +0x5234d*4 +0x02000000,0xe000); +reg_write( DDR_REG_BASE +0x5234e*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x5234f*4 +0x02000000,0x2184); +reg_write( DDR_REG_BASE +0x52350*4 +0x02000000,0x8); +reg_write( DDR_REG_BASE +0x52351*4 +0x02000000,0x78a5); +reg_write( DDR_REG_BASE +0x52352*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x52353*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52354*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52355*4 +0x02000000,0x82); +reg_write( DDR_REG_BASE +0x52356*4 +0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x52357*4 +0x02000000,0xd); +reg_write( DDR_REG_BASE +0x52358*4 +0x02000000,0xb580); +reg_write( DDR_REG_BASE +0x52359*4 +0x02000000,0xe014); +reg_write( DDR_REG_BASE +0x5235a*4 +0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x5235b*4 +0x02000000,0xc); +reg_write( DDR_REG_BASE +0x5235c*4 +0x02000000,0x6769); +reg_write( DDR_REG_BASE +0x5235d*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x5235e*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x5235f*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52360*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52361*4 +0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x52362*4 +0x02000000,0x794f); +reg_write( DDR_REG_BASE +0x52363*4 +0x02000000,0xbb7); +reg_write( DDR_REG_BASE +0x52364*4 +0x02000000,0x9065); +reg_write( DDR_REG_BASE +0x52365*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52366*4 +0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x52367*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52368*4 +0x02000000,0x5f); +reg_write( DDR_REG_BASE +0x52369*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5236a*4 +0x02000000,0xb1e); +reg_write( DDR_REG_BASE +0x5236b*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5236c*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x5236d*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5236e*4 +0x02000000,0xc0a2); +reg_write( DDR_REG_BASE +0x5236f*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52370*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52371*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52372*4 +0x02000000,0xc0e6); +reg_write( DDR_REG_BASE +0x52373*4 +0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x52374*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x52375*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52376*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52377*4 +0x02000000,0xff64); +reg_write( DDR_REG_BASE +0x52378*4 +0x02000000,0xb1e0); +reg_write( DDR_REG_BASE +0x52379*4 +0x02000000,0x1904); +reg_write( DDR_REG_BASE +0x5237a*4 +0x02000000,0x45); +reg_write( DDR_REG_BASE +0x5237b*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x5237c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5237d*4 +0x02000000,0x669); +reg_write( DDR_REG_BASE +0x5237e*4 +0x02000000,0x8a21); +reg_write( DDR_REG_BASE +0x5237f*4 +0x02000000,0x8ac0); +reg_write( DDR_REG_BASE +0x52380*4 +0x02000000,0xf039); +reg_write( DDR_REG_BASE +0x52381*4 +0x02000000,0x228c); +reg_write( DDR_REG_BASE +0x52382*4 +0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x52383*4 +0x02000000,0xf418); +reg_write( DDR_REG_BASE +0x52384*4 +0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x52385*4 +0x02000000,0x1f83); +reg_write( DDR_REG_BASE +0x52386*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52387*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52388*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x52389*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x5238a*4 +0x02000000,0x1f64); +reg_write( DDR_REG_BASE +0x5238b*4 +0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x5238c*4 +0x02000000,0x8c); +reg_write( DDR_REG_BASE +0x5238d*4 +0x02000000,0x7444); +reg_write( DDR_REG_BASE +0x5238e*4 +0x02000000,0x7a65); +reg_write( DDR_REG_BASE +0x5238f*4 +0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x52390*4 +0x02000000,0xb51); +reg_write( DDR_REG_BASE +0x52391*4 +0x02000000,0x123f); +reg_write( DDR_REG_BASE +0x52392*4 +0x02000000,0xb2e0); +reg_write( DDR_REG_BASE +0x52393*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x52394*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52395*4 +0x02000000,0xf164); +reg_write( DDR_REG_BASE +0x52396*4 +0x02000000,0xb2e0); +reg_write( DDR_REG_BASE +0x52397*4 +0x02000000,0x1a04); +reg_write( DDR_REG_BASE +0x52398*4 +0x02000000,0x45); +reg_write( DDR_REG_BASE +0x52399*4 +0x02000000,0xf020); +reg_write( DDR_REG_BASE +0x5239a*4 +0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x5239b*4 +0x02000000,0x32c0); +reg_write( DDR_REG_BASE +0x5239c*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x5239d*4 +0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x5239e*4 +0x02000000,0xf753); +reg_write( DDR_REG_BASE +0x5239f*4 +0x02000000,0x4381); +reg_write( DDR_REG_BASE +0x523a0*4 +0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x523a1*4 +0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x523a2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x523a3*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x523a4*4 +0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x523a5*4 +0x02000000,0x8); +reg_write( DDR_REG_BASE +0x523a6*4 +0x02000000,0x7b45); +reg_write( DDR_REG_BASE +0x523a7*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x523a8*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x523a9*4 +0x02000000,0x164); +reg_write( DDR_REG_BASE +0x523aa*4 +0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x523ab*4 +0x02000000,0x8d); +reg_write( DDR_REG_BASE +0x523ac*4 +0x02000000,0x7444); +reg_write( DDR_REG_BASE +0x523ad*4 +0x02000000,0x7b45); +reg_write( DDR_REG_BASE +0x523ae*4 +0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x523af*4 +0x02000000,0x1b00); +reg_write( DDR_REG_BASE +0x523b0*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x523b1*4 +0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x523b2*4 +0x02000000,0xe0d); +reg_write( DDR_REG_BASE +0x523b3*4 +0x02000000,0x3010); +reg_write( DDR_REG_BASE +0x523b4*4 +0x02000000,0xcd5); +reg_write( DDR_REG_BASE +0x523b5*4 +0x02000000,0x9274); +reg_write( DDR_REG_BASE +0x523b6*4 +0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x523b7*4 +0x02000000,0xb782); +reg_write( DDR_REG_BASE +0x523b8*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x523b9*4 +0x02000000,0x993); +reg_write( DDR_REG_BASE +0x523ba*4 +0x02000000,0x83a5); +reg_write( DDR_REG_BASE +0x523bb*4 +0x02000000,0x222f); +reg_write( DDR_REG_BASE +0x523bc*4 +0x02000000,0x2c7); +reg_write( DDR_REG_BASE +0x523bd*4 +0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x523be*4 +0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x523bf*4 +0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x523c0*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x523c1*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x523c2*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x523c3*4 +0x02000000,0x57d); +reg_write( DDR_REG_BASE +0x523c4*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x523c5*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x523c6*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x523c7*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x523c8*4 +0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x523c9*4 +0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x523ca*4 +0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x523cb*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x523cc*4 +0x02000000,0xd6a); +reg_write( DDR_REG_BASE +0x523cd*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x523ce*4 +0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x523cf*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x523d0*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x523d1*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x523d2*4 +0x02000000,0x57d); +reg_write( DDR_REG_BASE +0x523d3*4 +0x02000000,0xd910); +reg_write( DDR_REG_BASE +0x523d4*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x523d5*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x523d6*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x523d7*4 +0x02000000,0xdb0c); +reg_write( DDR_REG_BASE +0x523d8*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x523d9*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523da*4 +0x02000000,0xd4e); +reg_write( DDR_REG_BASE +0x523db*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x523dc*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523dd*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x523de*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x523df*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x523e0*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x523e1*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523e2*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x523e3*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523e4*4 +0x02000000,0xd3a); +reg_write( DDR_REG_BASE +0x523e5*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x523e6*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523e7*4 +0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x523e8*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x523e9*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x523ea*4 +0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x523eb*4 +0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x523ec*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x523ed*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x523ee*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x523ef*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x523f0*4 +0x02000000,0x736c); +reg_write( DDR_REG_BASE +0x523f1*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x523f2*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x523f3*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x523f4*4 +0x02000000,0xd1a); +reg_write( DDR_REG_BASE +0x523f5*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x523f6*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x523f7*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x523f8*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x523f9*4 +0x02000000,0x57d); +reg_write( DDR_REG_BASE +0x523fa*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x523fb*4 +0x02000000,0x825); +reg_write( DDR_REG_BASE +0x523fc*4 +0x02000000,0xb4); +reg_write( DDR_REG_BASE +0x523fd*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x523fe*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x523ff*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52400*4 +0x02000000,0xb862); +reg_write( DDR_REG_BASE +0x52401*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52402*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52403*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52404*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52405*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x52406*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52407*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52408*4 +0x02000000,0xcf2); +reg_write( DDR_REG_BASE +0x52409*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5240a*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5240b*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x5240c*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5240d*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5240e*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5240f*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52410*4 +0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x52411*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52412*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52413*4 +0x02000000,0xcde); +reg_write( DDR_REG_BASE +0x52414*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52415*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52416*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x52417*4 +0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x52418*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52419*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5241a*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5241b*4 +0x02000000,0xdb0c); +reg_write( DDR_REG_BASE +0x5241c*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5241d*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5241e*4 +0x02000000,0xcc6); +reg_write( DDR_REG_BASE +0x5241f*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52420*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52421*4 +0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x52422*4 +0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x52423*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52424*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x52425*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52426*4 +0x02000000,0x110); +reg_write( DDR_REG_BASE +0x52427*4 +0x02000000,0x9200); +reg_write( DDR_REG_BASE +0x52428*4 +0x02000000,0x204f); +reg_write( DDR_REG_BASE +0x52429*4 +0x02000000,0x101); +reg_write( DDR_REG_BASE +0x5242a*4 +0x02000000,0xb8a4); +reg_write( DDR_REG_BASE +0x5242b*4 +0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x5242c*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x5242d*4 +0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x5242e*4 +0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x5242f*4 +0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x52430*4 +0x02000000,0xd36); +reg_write( DDR_REG_BASE +0x52431*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x52432*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x52433*4 +0x02000000,0x4408); +reg_write( DDR_REG_BASE +0x52434*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x52435*4 +0x02000000,0x786f); +reg_write( DDR_REG_BASE +0x52436*4 +0x02000000,0x791b); +reg_write( DDR_REG_BASE +0x52437*4 +0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x52438*4 +0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x52439*4 +0x02000000,0x4181); +reg_write( DDR_REG_BASE +0x5243a*4 +0x02000000,0xed05); +reg_write( DDR_REG_BASE +0x5243b*4 +0x02000000,0xbd61); +reg_write( DDR_REG_BASE +0x5243c*4 +0x02000000,0xdff); +reg_write( DDR_REG_BASE +0x5243d*4 +0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x5243e*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x5243f*4 +0x02000000,0xb9c1); +reg_write( DDR_REG_BASE +0x52440*4 +0x02000000,0x9eb); +reg_write( DDR_REG_BASE +0x52441*4 +0x02000000,0x80a1); +reg_write( DDR_REG_BASE +0x52442*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x52443*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x52444*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52445*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52446*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52447*4 +0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x52448*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x52449*4 +0x02000000,0xc24f); +reg_write( DDR_REG_BASE +0x5244a*4 +0x02000000,0xc15a); +reg_write( DDR_REG_BASE +0x5244b*4 +0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x5244c*4 +0x02000000,0xc09e); +reg_write( DDR_REG_BASE +0x5244d*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5244e*4 +0x02000000,0xeb2); +reg_write( DDR_REG_BASE +0x5244f*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x52450*4 +0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x52451*4 +0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x52452*4 +0x02000000,0xf22); +reg_write( DDR_REG_BASE +0x52453*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52454*4 +0x02000000,0xc19e); +reg_write( DDR_REG_BASE +0x52455*4 +0x02000000,0xca13); +reg_write( DDR_REG_BASE +0x52456*4 +0x02000000,0xe807); +reg_write( DDR_REG_BASE +0x52457*4 +0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x52458*4 +0x02000000,0xa4e); +reg_write( DDR_REG_BASE +0x52459*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5245a*4 +0x02000000,0xc10f); +reg_write( DDR_REG_BASE +0x5245b*4 +0x02000000,0x23d); +reg_write( DDR_REG_BASE +0x5245c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5245d*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5245e*4 +0x02000000,0xc04e); +reg_write( DDR_REG_BASE +0x5245f*4 +0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x52460*4 +0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x52461*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x52462*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52463*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52464*4 +0x02000000,0x7204); +reg_write( DDR_REG_BASE +0x52465*4 +0x02000000,0xc056); +reg_write( DDR_REG_BASE +0x52466*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52467*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x52468*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52469*4 +0x02000000,0xe); +reg_write( DDR_REG_BASE +0x5246a*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5246b*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5246c*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5246d*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5246e*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x5246f*4 +0x02000000,0x8041); +reg_write( DDR_REG_BASE +0x52470*4 +0x02000000,0xc016); +reg_write( DDR_REG_BASE +0x52471*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x52472*4 +0x02000000,0xa1); +reg_write( DDR_REG_BASE +0x52473*4 +0x02000000,0xc056); +reg_write( DDR_REG_BASE +0x52474*4 +0x02000000,0xca0b); +reg_write( DDR_REG_BASE +0x52475*4 +0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x52476*4 +0x02000000,0x803e); +reg_write( DDR_REG_BASE +0x52477*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x52478*4 +0x02000000,0xc058); +reg_write( DDR_REG_BASE +0x52479*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x5247a*4 +0x02000000,0x61); +reg_write( DDR_REG_BASE +0x5247b*4 +0x02000000,0xc058); +reg_write( DDR_REG_BASE +0x5247c*4 +0x02000000,0xd810); +reg_write( DDR_REG_BASE +0x5247d*4 +0x02000000,0xc057); +reg_write( DDR_REG_BASE +0x5247e*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x5247f*4 +0x02000000,0x61); +reg_write( DDR_REG_BASE +0x52480*4 +0x02000000,0xc057); +reg_write( DDR_REG_BASE +0x52481*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52482*4 +0x02000000,0xc04d); +reg_write( DDR_REG_BASE +0x52483*4 +0x02000000,0xf0db); +reg_write( DDR_REG_BASE +0x52484*4 +0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x52485*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x52486*4 +0x02000000,0x88e1); +reg_write( DDR_REG_BASE +0x52487*4 +0x02000000,0x88a0); +reg_write( DDR_REG_BASE +0x52488*4 +0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x52489*4 +0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x5248a*4 +0x02000000,0xd76); +reg_write( DDR_REG_BASE +0x5248b*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5248c*4 +0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x5248d*4 +0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x5248e*4 +0x02000000,0x5042); +reg_write( DDR_REG_BASE +0x5248f*4 +0x02000000,0xca03); +reg_write( DDR_REG_BASE +0x52490*4 +0x02000000,0x929); +reg_write( DDR_REG_BASE +0x52491*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52492*4 +0x02000000,0xca02); +reg_write( DDR_REG_BASE +0x52493*4 +0x02000000,0x825); +reg_write( DDR_REG_BASE +0x52494*4 +0x02000000,0x64); +reg_write( DDR_REG_BASE +0x52495*4 +0x02000000,0x43a1); +reg_write( DDR_REG_BASE +0x52496*4 +0x02000000,0xc01a); +reg_write( DDR_REG_BASE +0x52497*4 +0x02000000,0xc20e); +reg_write( DDR_REG_BASE +0x52498*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52499*4 +0x02000000,0x4b); +reg_write( DDR_REG_BASE +0x5249a*4 +0x02000000,0x6); +reg_write( DDR_REG_BASE +0x5249b*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5249c*4 +0x02000000,0xc017); +reg_write( DDR_REG_BASE +0x5249d*4 +0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x5249e*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5249f*4 +0x02000000,0xc018); +reg_write( DDR_REG_BASE +0x524a0*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x524a1*4 +0x02000000,0x8b2); +reg_write( DDR_REG_BASE +0x524a2*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524a3*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x524a4*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x524a5*4 +0x02000000,0xc05d); +reg_write( DDR_REG_BASE +0x524a6*4 +0x02000000,0xc017); +reg_write( DDR_REG_BASE +0x524a7*4 +0x02000000,0x1460); +reg_write( DDR_REG_BASE +0x524a8*4 +0x02000000,0x301b); +reg_write( DDR_REG_BASE +0x524a9*4 +0x02000000,0xc050); +reg_write( DDR_REG_BASE +0x524aa*4 +0x02000000,0xc01a); +reg_write( DDR_REG_BASE +0x524ab*4 +0x02000000,0xc059); +reg_write( DDR_REG_BASE +0x524ac*4 +0x02000000,0xf094); +reg_write( DDR_REG_BASE +0x524ad*4 +0x02000000,0x78af); +reg_write( DDR_REG_BASE +0x524ae*4 +0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x524af*4 +0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x524b0*4 +0x02000000,0xc64a); +reg_write( DDR_REG_BASE +0x524b1*4 +0x02000000,0x7114); +reg_write( DDR_REG_BASE +0x524b2*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x524b3*4 +0x02000000,0xc052); +reg_write( DDR_REG_BASE +0x524b4*4 +0x02000000,0xc053); +reg_write( DDR_REG_BASE +0x524b5*4 +0x02000000,0xf226); +reg_write( DDR_REG_BASE +0x524b6*4 +0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x524b7*4 +0x02000000,0x252f); +reg_write( DDR_REG_BASE +0x524b8*4 +0x02000000,0x16c8); +reg_write( DDR_REG_BASE +0x524b9*4 +0x02000000,0x78a2); +reg_write( DDR_REG_BASE +0x524ba*4 +0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x524bb*4 +0x02000000,0x78ef); +reg_write( DDR_REG_BASE +0x524bc*4 +0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x524bd*4 +0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x524be*4 +0x02000000,0xd0e); +reg_write( DDR_REG_BASE +0x524bf*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x524c0*4 +0x02000000,0xc20a); +reg_write( DDR_REG_BASE +0x524c1*4 +0x02000000,0xc053); +reg_write( DDR_REG_BASE +0x524c2*4 +0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x524c3*4 +0x02000000,0xc20a); +reg_write( DDR_REG_BASE +0x524c4*4 +0x02000000,0x60b8); +reg_write( DDR_REG_BASE +0x524c5*4 +0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x524c6*4 +0x02000000,0xcfe); +reg_write( DDR_REG_BASE +0x524c7*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x524c8*4 +0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x524c9*4 +0x02000000,0xc052); +reg_write( DDR_REG_BASE +0x524ca*4 +0x02000000,0xc013); +reg_write( DDR_REG_BASE +0x524cb*4 +0x02000000,0xe0f); +reg_write( DDR_REG_BASE +0x524cc*4 +0x02000000,0x1025); +reg_write( DDR_REG_BASE +0x524cd*4 +0x02000000,0x78b3); +reg_write( DDR_REG_BASE +0x524ce*4 +0x02000000,0xc113); +reg_write( DDR_REG_BASE +0x524cf*4 +0x02000000,0xc14a); +reg_write( DDR_REG_BASE +0x524d0*4 +0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x524d1*4 +0x02000000,0xc012); +reg_write( DDR_REG_BASE +0x524d2*4 +0x02000000,0xe0f); +reg_write( DDR_REG_BASE +0x524d3*4 +0x02000000,0x1025); +reg_write( DDR_REG_BASE +0x524d4*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x524d5*4 +0x02000000,0xc012); +reg_write( DDR_REG_BASE +0x524d6*4 +0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x524d7*4 +0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x524d8*4 +0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x524d9*4 +0x02000000,0xc64a); +reg_write( DDR_REG_BASE +0x524da*4 +0x02000000,0x780e); +reg_write( DDR_REG_BASE +0x524db*4 +0x02000000,0xc05c); +reg_write( DDR_REG_BASE +0x524dc*4 +0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x524dd*4 +0x02000000,0xc51c); +reg_write( DDR_REG_BASE +0x524de*4 +0x02000000,0x651d); +reg_write( DDR_REG_BASE +0x524df*4 +0x02000000,0x78ef); +reg_write( DDR_REG_BASE +0x524e0*4 +0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x524e1*4 +0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x524e2*4 +0x02000000,0x80d); +reg_write( DDR_REG_BASE +0x524e3*4 +0x02000000,0xb1); +reg_write( DDR_REG_BASE +0x524e4*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x524e5*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x524e6*4 +0x02000000,0xc151); +reg_write( DDR_REG_BASE +0x524e7*4 +0x02000000,0xf023); +reg_write( DDR_REG_BASE +0x524e8*4 +0x02000000,0xc010); +reg_write( DDR_REG_BASE +0x524e9*4 +0x02000000,0x7f10); +reg_write( DDR_REG_BASE +0x524ea*4 +0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x524eb*4 +0x02000000,0x78e2); +reg_write( DDR_REG_BASE +0x524ec*4 +0x02000000,0x7a0f); +reg_write( DDR_REG_BASE +0x524ed*4 +0x02000000,0x78af); +reg_write( DDR_REG_BASE +0x524ee*4 +0x02000000,0xc05b); +reg_write( DDR_REG_BASE +0x524ef*4 +0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x524f0*4 +0x02000000,0xcaa); +reg_write( DDR_REG_BASE +0x524f1*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x524f2*4 +0x02000000,0xc11b); +reg_write( DDR_REG_BASE +0x524f3*4 +0x02000000,0xc051); +reg_write( DDR_REG_BASE +0x524f4*4 +0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x524f5*4 +0x02000000,0xc11b); +reg_write( DDR_REG_BASE +0x524f6*4 +0x02000000,0x60f8); +reg_write( DDR_REG_BASE +0x524f7*4 +0x02000000,0x7a0f); +reg_write( DDR_REG_BASE +0x524f8*4 +0x02000000,0xc9a); +reg_write( DDR_REG_BASE +0x524f9*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x524fa*4 +0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x524fb*4 +0x02000000,0xc211); +reg_write( DDR_REG_BASE +0x524fc*4 +0x02000000,0xc10a); +reg_write( DDR_REG_BASE +0x524fd*4 +0x02000000,0x90f); +reg_write( DDR_REG_BASE +0x524fe*4 +0x02000000,0xa5); +reg_write( DDR_REG_BASE +0x524ff*4 +0x02000000,0x79f3); +reg_write( DDR_REG_BASE +0x52500*4 +0x02000000,0xc211); +reg_write( DDR_REG_BASE +0x52501*4 +0x02000000,0xc24a); +reg_write( DDR_REG_BASE +0x52502*4 +0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x52503*4 +0x02000000,0xc10a); +reg_write( DDR_REG_BASE +0x52504*4 +0x02000000,0x90b); +reg_write( DDR_REG_BASE +0x52505*4 +0x02000000,0x25); +reg_write( DDR_REG_BASE +0x52506*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52507*4 +0x02000000,0xc110); +reg_write( DDR_REG_BASE +0x52508*4 +0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x52509*4 +0x02000000,0xc70c); +reg_write( DDR_REG_BASE +0x5250a*4 +0x02000000,0x1212); +reg_write( DDR_REG_BASE +0x5250b*4 +0x02000000,0x3602); +reg_write( DDR_REG_BASE +0x5250c*4 +0x02000000,0x1203); +reg_write( DDR_REG_BASE +0x5250d*4 +0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x5250e*4 +0x02000000,0x792e); +reg_write( DDR_REG_BASE +0x5250f*4 +0x02000000,0xa37); +reg_write( DDR_REG_BASE +0x52510*4 +0x02000000,0xe4); +reg_write( DDR_REG_BASE +0x52511*4 +0x02000000,0x673f); +reg_write( DDR_REG_BASE +0x52512*4 +0x02000000,0x1202); +reg_write( DDR_REG_BASE +0x52513*4 +0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x52514*4 +0x02000000,0xb2b); +reg_write( DDR_REG_BASE +0x52515*4 +0x02000000,0xa4); +reg_write( DDR_REG_BASE +0x52516*4 +0x02000000,0x7bef); +reg_write( DDR_REG_BASE +0x52517*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52518*4 +0x02000000,0xc012); +reg_write( DDR_REG_BASE +0x52519*4 +0x02000000,0xc211); +reg_write( DDR_REG_BASE +0x5251a*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x5251b*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5251c*4 +0x02000000,0xc013); +reg_write( DDR_REG_BASE +0x5251d*4 +0x02000000,0xc246); +reg_write( DDR_REG_BASE +0x5251e*4 +0x02000000,0x7aaf); +reg_write( DDR_REG_BASE +0x5251f*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52520*4 +0x02000000,0xc01c); +reg_write( DDR_REG_BASE +0x52521*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52522*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x52523*4 +0x02000000,0x9); +reg_write( DDR_REG_BASE +0x52524*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52525*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x52526*4 +0x02000000,0xfa6); +reg_write( DDR_REG_BASE +0x52527*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52528*4 +0x02000000,0xc644); +reg_write( DDR_REG_BASE +0x52529*4 +0x02000000,0xc01d); +reg_write( DDR_REG_BASE +0x5252a*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5252b*4 +0x02000000,0x2053); +reg_write( DDR_REG_BASE +0x5252c*4 +0x02000000,0x807e); +reg_write( DDR_REG_BASE +0x5252d*4 +0x02000000,0xc05d); +reg_write( DDR_REG_BASE +0x5252e*4 +0x02000000,0xf405); +reg_write( DDR_REG_BASE +0x5252f*4 +0x02000000,0xc010); +reg_write( DDR_REG_BASE +0x52530*4 +0x02000000,0x7767); +reg_write( DDR_REG_BASE +0x52531*4 +0x02000000,0xb864); +reg_write( DDR_REG_BASE +0x52532*4 +0x02000000,0xc050); +reg_write( DDR_REG_BASE +0x52533*4 +0x02000000,0xc019); +reg_write( DDR_REG_BASE +0x52534*4 +0x02000000,0xc60a); +reg_write( DDR_REG_BASE +0x52535*4 +0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x52536*4 +0x02000000,0xc059); +reg_write( DDR_REG_BASE +0x52537*4 +0x02000000,0xc010); +reg_write( DDR_REG_BASE +0x52538*4 +0x02000000,0x780e); +reg_write( DDR_REG_BASE +0x52539*4 +0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x5253a*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x5253b*4 +0x02000000,0xc050); +reg_write( DDR_REG_BASE +0x5253c*4 +0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x5253d*4 +0x02000000,0x6c6); +reg_write( DDR_REG_BASE +0x5253e*4 +0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x5253f*4 +0x02000000,0x5b); +reg_write( DDR_REG_BASE +0x52540*4 +0x02000000,0xc019); +reg_write( DDR_REG_BASE +0x52541*4 +0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x52542*4 +0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x52543*4 +0x02000000,0xf56b); +reg_write( DDR_REG_BASE +0x52544*4 +0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x52545*4 +0x02000000,0x82d); +reg_write( DDR_REG_BASE +0x52546*4 +0x02000000,0x385); +reg_write( DDR_REG_BASE +0x52547*4 +0x02000000,0x5042); +reg_write( DDR_REG_BASE +0x52548*4 +0x02000000,0xca03); +reg_write( DDR_REG_BASE +0x52549*4 +0x02000000,0x91f); +reg_write( DDR_REG_BASE +0x5254a*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5254b*4 +0x02000000,0xca02); +reg_write( DDR_REG_BASE +0x5254c*4 +0x02000000,0x817); +reg_write( DDR_REG_BASE +0x5254d*4 +0x02000000,0x64); +reg_write( DDR_REG_BASE +0x5254e*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x5254f*4 +0x02000000,0xc20e); +reg_write( DDR_REG_BASE +0x52550*4 +0x02000000,0xc30d); +reg_write( DDR_REG_BASE +0x52551*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52552*4 +0x02000000,0x51); +reg_write( DDR_REG_BASE +0x52553*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x52554*4 +0x02000000,0xf4a); +reg_write( DDR_REG_BASE +0x52555*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52556*4 +0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x52557*4 +0x02000000,0xc555); +reg_write( DDR_REG_BASE +0x52558*4 +0x02000000,0xc754); +reg_write( DDR_REG_BASE +0x52559*4 +0x02000000,0xc64d); +reg_write( DDR_REG_BASE +0x5255a*4 +0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x5255b*4 +0x02000000,0x7204); +reg_write( DDR_REG_BASE +0x5255c*4 +0x02000000,0xc04e); +reg_write( DDR_REG_BASE +0x5255d*4 +0x02000000,0xc10e); +reg_write( DDR_REG_BASE +0x5255e*4 +0x02000000,0xc016); +reg_write( DDR_REG_BASE +0x5255f*4 +0x02000000,0x7110); +reg_write( DDR_REG_BASE +0x52560*4 +0x02000000,0x648); +reg_write( DDR_REG_BASE +0x52561*4 +0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x52562*4 +0x02000000,0xc19e); +reg_write( DDR_REG_BASE +0x52563*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52564*4 +0x02000000,0x52); +reg_write( DDR_REG_BASE +0x52565*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52566*4 +0x02000000,0xf76); +reg_write( DDR_REG_BASE +0x52567*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52568*4 +0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x52569*4 +0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x5256a*4 +0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x5256b*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5256c*4 +0x02000000,0xc115); +reg_write( DDR_REG_BASE +0x5256d*4 +0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x5256e*4 +0x02000000,0xb96f); +reg_write( DDR_REG_BASE +0x5256f*4 +0x02000000,0x183f); +reg_write( DDR_REG_BASE +0x52570*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x52571*4 +0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x52572*4 +0x02000000,0x80d); +reg_write( DDR_REG_BASE +0x52573*4 +0x02000000,0x90); +reg_write( DDR_REG_BASE +0x52574*4 +0x02000000,0xc10b); +reg_write( DDR_REG_BASE +0x52575*4 +0x02000000,0xc014); +reg_write( DDR_REG_BASE +0x52576*4 +0x02000000,0x1940); +reg_write( DDR_REG_BASE +0x52577*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x52578*4 +0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x52579*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x5257a*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x5257b*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x5257c*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5257d*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5257e*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5257f*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52580*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52581*4 +0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x52582*4 +0x02000000,0x3802); +reg_write( DDR_REG_BASE +0x52583*4 +0x02000000,0xc147); +reg_write( DDR_REG_BASE +0x52584*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x52585*4 +0x02000000,0xc088); +reg_write( DDR_REG_BASE +0x52586*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52587*4 +0x02000000,0xc42); +reg_write( DDR_REG_BASE +0x52588*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x52589*4 +0x02000000,0xda80); +reg_write( DDR_REG_BASE +0x5258a*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5258b*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x5258c*4 +0x02000000,0xc242); +reg_write( DDR_REG_BASE +0x5258d*4 +0x02000000,0xf02b); +reg_write( DDR_REG_BASE +0x5258e*4 +0x02000000,0x8880); +reg_write( DDR_REG_BASE +0x5258f*4 +0x02000000,0x8861); +reg_write( DDR_REG_BASE +0x52590*4 +0x02000000,0x4081); +reg_write( DDR_REG_BASE +0x52591*4 +0x02000000,0xf015); +reg_write( DDR_REG_BASE +0x52592*4 +0x02000000,0x60f8); +reg_write( DDR_REG_BASE +0x52593*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52594*4 +0x02000000,0x8b); +reg_write( DDR_REG_BASE +0x52595*4 +0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x52596*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x52597*4 +0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x52598*4 +0x02000000,0x716d); +reg_write( DDR_REG_BASE +0x52599*4 +0x02000000,0xca15); +reg_write( DDR_REG_BASE +0x5259a*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x5259b*4 +0x02000000,0x7db); +reg_write( DDR_REG_BASE +0x5259c*4 +0x02000000,0x4061); +reg_write( DDR_REG_BASE +0x5259d*4 +0x02000000,0xb11); +reg_write( DDR_REG_BASE +0x5259e*4 +0x02000000,0x3010); +reg_write( DDR_REG_BASE +0x5259f*4 +0x02000000,0x2342); +reg_write( DDR_REG_BASE +0x525a0*4 +0x02000000,0x305b); +reg_write( DDR_REG_BASE +0x525a1*4 +0x02000000,0xbff); +reg_write( DDR_REG_BASE +0x525a2*4 +0x02000000,0xb031); +reg_write( DDR_REG_BASE +0x525a3*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x525a4*4 +0x02000000,0x60f8); +reg_write( DDR_REG_BASE +0x525a5*4 +0x02000000,0x7f10); +reg_write( DDR_REG_BASE +0x525a6*4 +0x02000000,0xbd9); +reg_write( DDR_REG_BASE +0x525a7*4 +0x02000000,0x83e5); +reg_write( DDR_REG_BASE +0x525a8*4 +0x02000000,0xc088); +reg_write( DDR_REG_BASE +0x525a9*4 +0x02000000,0x4b90); +reg_write( DDR_REG_BASE +0x525aa*4 +0x02000000,0x7714); +reg_write( DDR_REG_BASE +0x525ab*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x525ac*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x525ad*4 +0x02000000,0x2c); +reg_write( DDR_REG_BASE +0x525ae*4 +0x02000000,0x242f); +reg_write( DDR_REG_BASE +0x525af*4 +0x02000000,0x9007); +reg_write( DDR_REG_BASE +0x525b0*4 +0x02000000,0xf206); +reg_write( DDR_REG_BASE +0x525b1*4 +0x02000000,0x7b4f); +reg_write( DDR_REG_BASE +0x525b2*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x525b3*4 +0x02000000,0x7470); +reg_write( DDR_REG_BASE +0x525b4*4 +0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x525b5*4 +0x02000000,0xd); +reg_write( DDR_REG_BASE +0x525b6*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x525b7*4 +0x02000000,0xeb1); +reg_write( DDR_REG_BASE +0x525b8*4 +0x02000000,0x97f4); +reg_write( DDR_REG_BASE +0x525b9*4 +0x02000000,0x2514); +reg_write( DDR_REG_BASE +0x525ba*4 +0x02000000,0x1380); +reg_write( DDR_REG_BASE +0x525bb*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x525bc*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x525bd*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x525be*4 +0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x525bf*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x525c0*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x525c1*4 +0x02000000,0xf01f); +reg_write( DDR_REG_BASE +0x525c2*4 +0x02000000,0x8860); +reg_write( DDR_REG_BASE +0x525c3*4 +0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x525c4*4 +0x02000000,0x7862); +reg_write( DDR_REG_BASE +0x525c5*4 +0x02000000,0x6861); +reg_write( DDR_REG_BASE +0x525c6*4 +0x02000000,0x7714); +reg_write( DDR_REG_BASE +0x525c7*4 +0x02000000,0xca0f); +reg_write( DDR_REG_BASE +0x525c8*4 +0x02000000,0x7b70); +reg_write( DDR_REG_BASE +0x525c9*4 +0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x525ca*4 +0x02000000,0x2c); +reg_write( DDR_REG_BASE +0x525cb*4 +0x02000000,0x631f); +reg_write( DDR_REG_BASE +0x525cc*4 +0x02000000,0x784f); +reg_write( DDR_REG_BASE +0x525cd*4 +0x02000000,0x825); +reg_write( DDR_REG_BASE +0x525ce*4 +0x02000000,0x3e5); +reg_write( DDR_REG_BASE +0x525cf*4 +0x02000000,0x7b6a); +reg_write( DDR_REG_BASE +0x525d0*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x525d1*4 +0x02000000,0x7b70); +reg_write( DDR_REG_BASE +0x525d2*4 +0x02000000,0x2600); +reg_write( DDR_REG_BASE +0x525d3*4 +0x02000000,0x90ce); +reg_write( DDR_REG_BASE +0x525d4*4 +0x02000000,0x7b8c); +reg_write( DDR_REG_BASE +0x525d5*4 +0x02000000,0x2041); +reg_write( DDR_REG_BASE +0x525d6*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x525d7*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x525d8*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x525d9*4 +0x02000000,0x2300); +reg_write( DDR_REG_BASE +0x525da*4 +0x02000000,0xb0db); +reg_write( DDR_REG_BASE +0x525db*4 +0x02000000,0x2041); +reg_write( DDR_REG_BASE +0x525dc*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x525dd*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x525de*4 +0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x525df*4 +0x02000000,0xcc9); +reg_write( DDR_REG_BASE +0x525e0*4 +0x02000000,0x97f4); +reg_write( DDR_REG_BASE +0x525e1*4 +0x02000000,0x2514); +reg_write( DDR_REG_BASE +0x525e2*4 +0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x525e3*4 +0x02000000,0xca67); +reg_write( DDR_REG_BASE +0x525e4*4 +0x02000000,0x1266); +reg_write( DDR_REG_BASE +0x525e5*4 +0x02000000,0x3082); +reg_write( DDR_REG_BASE +0x525e6*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x525e7*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x525e8*4 +0x02000000,0xc343); +reg_write( DDR_REG_BASE +0x525e9*4 +0x02000000,0xc345); +reg_write( DDR_REG_BASE +0x525ea*4 +0x02000000,0xf02d); +reg_write( DDR_REG_BASE +0x525eb*4 +0x02000000,0x626a); +reg_write( DDR_REG_BASE +0x525ec*4 +0x02000000,0x120f); +reg_write( DDR_REG_BASE +0x525ed*4 +0x02000000,0x308c); +reg_write( DDR_REG_BASE +0x525ee*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x525ef*4 +0x02000000,0x108b); +reg_write( DDR_REG_BASE +0x525f0*4 +0x02000000,0x7c2f); +reg_write( DDR_REG_BASE +0x525f1*4 +0x02000000,0xc3b); +reg_write( DDR_REG_BASE +0x525f2*4 +0x02000000,0x12c5); +reg_write( DDR_REG_BASE +0x525f3*4 +0x02000000,0x221f); +reg_write( DDR_REG_BASE +0x525f4*4 +0x02000000,0x8c); +reg_write( DDR_REG_BASE +0x525f5*4 +0x02000000,0xda1f); +reg_write( DDR_REG_BASE +0x525f6*4 +0x02000000,0x241a); +reg_write( DDR_REG_BASE +0x525f7*4 +0x02000000,0x10df); +reg_write( DDR_REG_BASE +0x525f8*4 +0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x525f9*4 +0x02000000,0x37c0); +reg_write( DDR_REG_BASE +0x525fa*4 +0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x525fb*4 +0x02000000,0xa01); +reg_write( DDR_REG_BASE +0x525fc*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x525fd*4 +0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x525fe*4 +0x02000000,0x3781); +reg_write( DDR_REG_BASE +0x525ff*4 +0x02000000,0xc203); +reg_write( DDR_REG_BASE +0x52600*4 +0x02000000,0x2200); +reg_write( DDR_REG_BASE +0x52601*4 +0x02000000,0x87c2); +reg_write( DDR_REG_BASE +0x52602*4 +0x02000000,0xc243); +reg_write( DDR_REG_BASE +0x52603*4 +0x02000000,0xc205); +reg_write( DDR_REG_BASE +0x52604*4 +0x02000000,0x2201); +reg_write( DDR_REG_BASE +0x52605*4 +0x02000000,0x8782); +reg_write( DDR_REG_BASE +0x52606*4 +0x02000000,0xc245); +reg_write( DDR_REG_BASE +0x52607*4 +0x02000000,0xc202); +reg_write( DDR_REG_BASE +0x52608*4 +0x02000000,0x2200); +reg_write( DDR_REG_BASE +0x52609*4 +0x02000000,0x8302); +reg_write( DDR_REG_BASE +0x5260a*4 +0x02000000,0x2741); +reg_write( DDR_REG_BASE +0x5260b*4 +0x02000000,0x900f); +reg_write( DDR_REG_BASE +0x5260c*4 +0x02000000,0xc242); +reg_write( DDR_REG_BASE +0x5260d*4 +0x02000000,0x1215); +reg_write( DDR_REG_BASE +0x5260e*4 +0x02000000,0x308c); +reg_write( DDR_REG_BASE +0x5260f*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52610*4 +0x02000000,0xbcc4); +reg_write( DDR_REG_BASE +0x52611*4 +0x02000000,0xec06); +reg_write( DDR_REG_BASE +0x52612*4 +0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x52613*4 +0x02000000,0xc01); +reg_write( DDR_REG_BASE +0x52614*4 +0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x52615*4 +0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x52616*4 +0x02000000,0x627a); +reg_write( DDR_REG_BASE +0x52617*4 +0x02000000,0x7b50); +reg_write( DDR_REG_BASE +0x52618*4 +0x02000000,0x8a7); +reg_write( DDR_REG_BASE +0x52619*4 +0x02000000,0x80e5); +reg_write( DDR_REG_BASE +0x5261a*4 +0x02000000,0xc288); +reg_write( DDR_REG_BASE +0x5261b*4 +0x02000000,0xc812); +reg_write( DDR_REG_BASE +0x5261c*4 +0x02000000,0x1203); +reg_write( DDR_REG_BASE +0x5261d*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x5261e*4 +0x02000000,0x825); +reg_write( DDR_REG_BASE +0x5261f*4 +0x02000000,0x44); +reg_write( DDR_REG_BASE +0x52620*4 +0x02000000,0x1202); +reg_write( DDR_REG_BASE +0x52621*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x52622*4 +0x02000000,0x91d); +reg_write( DDR_REG_BASE +0x52623*4 +0x02000000,0x24); +reg_write( DDR_REG_BASE +0x52624*4 +0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x52625*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52626*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52627*4 +0x02000000,0x46); +reg_write( DDR_REG_BASE +0x52628*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52629*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5262a*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x5262b*4 +0x02000000,0x43c1); +reg_write( DDR_REG_BASE +0x5262c*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5262d*4 +0x02000000,0xd9a); +reg_write( DDR_REG_BASE +0x5262e*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5262f*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x52630*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52631*4 +0x02000000,0xc104); +reg_write( DDR_REG_BASE +0x52632*4 +0x02000000,0x78e5); +reg_write( DDR_REG_BASE +0x52633*4 +0x02000000,0x79c5); +reg_write( DDR_REG_BASE +0x52634*4 +0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x52635*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52636*4 +0x02000000,0x2179); +reg_write( DDR_REG_BASE +0x52637*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52638*4 +0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x52639*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5263a*4 +0x02000000,0x47); +reg_write( DDR_REG_BASE +0x5263b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5263c*4 +0x02000000,0xdca); +reg_write( DDR_REG_BASE +0x5263d*4 +0x02000000,0xfd8f); +reg_write( DDR_REG_BASE +0x5263e*4 +0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x5263f*4 +0x02000000,0xc304); +reg_write( DDR_REG_BASE +0x52640*4 +0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x52641*4 +0x02000000,0xc8a); +reg_write( DDR_REG_BASE +0x52642*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52643*4 +0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x52644*4 +0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x52645*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52646*4 +0x02000000,0xc105); +reg_write( DDR_REG_BASE +0x52647*4 +0x02000000,0xc202); +reg_write( DDR_REG_BASE +0x52648*4 +0x02000000,0xc7a); +reg_write( DDR_REG_BASE +0x52649*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x5264a*4 +0x02000000,0x43e1); +reg_write( DDR_REG_BASE +0x5264b*4 +0x02000000,0xc107); +reg_write( DDR_REG_BASE +0x5264c*4 +0x02000000,0x915); +reg_write( DDR_REG_BASE +0x5264d*4 +0x02000000,0x70); +reg_write( DDR_REG_BASE +0x5264e*4 +0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x5264f*4 +0x02000000,0x2642); +reg_write( DDR_REG_BASE +0x52650*4 +0x02000000,0x13c1); +reg_write( DDR_REG_BASE +0x52651*4 +0x02000000,0x1d3f); +reg_write( DDR_REG_BASE +0x52652*4 +0x02000000,0x1042); +reg_write( DDR_REG_BASE +0x52653*4 +0x02000000,0xc107); +reg_write( DDR_REG_BASE +0x52654*4 +0x02000000,0x909); +reg_write( DDR_REG_BASE +0x52655*4 +0x02000000,0x90); +reg_write( DDR_REG_BASE +0x52656*4 +0x02000000,0x1d40); +reg_write( DDR_REG_BASE +0x52657*4 +0x02000000,0x10c2); +reg_write( DDR_REG_BASE +0x52658*4 +0x02000000,0x5042); +reg_write( DDR_REG_BASE +0x52659*4 +0x02000000,0xca03); +reg_write( DDR_REG_BASE +0x5265a*4 +0x02000000,0x935); +reg_write( DDR_REG_BASE +0x5265b*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5265c*4 +0x02000000,0xca02); +reg_write( DDR_REG_BASE +0x5265d*4 +0x02000000,0x831); +reg_write( DDR_REG_BASE +0x5265e*4 +0x02000000,0x64); +reg_write( DDR_REG_BASE +0x5265f*4 +0x02000000,0x7acf); +reg_write( DDR_REG_BASE +0x52660*4 +0x02000000,0x7b6f); +reg_write( DDR_REG_BASE +0x52661*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52662*4 +0x02000000,0x48); +reg_write( DDR_REG_BASE +0x52663*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x52664*4 +0x02000000,0xd2a); +reg_write( DDR_REG_BASE +0x52665*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52666*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x52667*4 +0x02000000,0x1540); +reg_write( DDR_REG_BASE +0x52668*4 +0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x52669*4 +0x02000000,0x153f); +reg_write( DDR_REG_BASE +0x5266a*4 +0x02000000,0x10c3); +reg_write( DDR_REG_BASE +0x5266b*4 +0x02000000,0x153e); +reg_write( DDR_REG_BASE +0x5266c*4 +0x02000000,0x1082); +reg_write( DDR_REG_BASE +0x5266d*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5266e*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5266f*4 +0x02000000,0x49); +reg_write( DDR_REG_BASE +0x52670*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x52671*4 +0x02000000,0xd12); +reg_write( DDR_REG_BASE +0x52672*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52673*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x52674*4 +0x02000000,0xca0f); +reg_write( DDR_REG_BASE +0x52675*4 +0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x52676*4 +0x02000000,0x3802); +reg_write( DDR_REG_BASE +0x52677*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52678*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52679*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5267a*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5267b*4 +0x02000000,0x8de); +reg_write( DDR_REG_BASE +0x5267c*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x5267d*4 +0x02000000,0x4548); +reg_write( DDR_REG_BASE +0x5267e*4 +0x02000000,0x153f); +reg_write( DDR_REG_BASE +0x5267f*4 +0x02000000,0x1081); +reg_write( DDR_REG_BASE +0x52680*4 +0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x52681*4 +0x02000000,0x2140); +reg_write( DDR_REG_BASE +0x52682*4 +0x02000000,0x3ce); +reg_write( DDR_REG_BASE +0x52683*4 +0x02000000,0x44c9); +reg_write( DDR_REG_BASE +0x52684*4 +0x02000000,0x222f); +reg_write( DDR_REG_BASE +0x52685*4 +0x02000000,0x8307); +reg_write( DDR_REG_BASE +0x52686*4 +0x02000000,0xf20e); +reg_write( DDR_REG_BASE +0x52687*4 +0x02000000,0x785b); +reg_write( DDR_REG_BASE +0x52688*4 +0x02000000,0x60b8); +reg_write( DDR_REG_BASE +0x52689*4 +0x02000000,0x10ff); +reg_write( DDR_REG_BASE +0x5268a*4 +0x02000000,0x808f); +reg_write( DDR_REG_BASE +0x5268b*4 +0x02000000,0x1540); +reg_write( DDR_REG_BASE +0x5268c*4 +0x02000000,0x108b); +reg_write( DDR_REG_BASE +0x5268d*4 +0x02000000,0xf11); +reg_write( DDR_REG_BASE +0x5268e*4 +0x02000000,0x12e4); +reg_write( DDR_REG_BASE +0x5268f*4 +0x02000000,0x7785); +reg_write( DDR_REG_BASE +0x52690*4 +0x02000000,0x10fe); +reg_write( DDR_REG_BASE +0x52691*4 +0x02000000,0x8080); +reg_write( DDR_REG_BASE +0x52692*4 +0x02000000,0xbe5); +reg_write( DDR_REG_BASE +0x52693*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52694*4 +0x02000000,0x7ccf); +reg_write( DDR_REG_BASE +0x52695*4 +0x02000000,0xc1f); +reg_write( DDR_REG_BASE +0x52696*4 +0x02000000,0x17b5); +reg_write( DDR_REG_BASE +0x52697*4 +0x02000000,0x720c); +reg_write( DDR_REG_BASE +0x52698*4 +0x02000000,0x7894); +reg_write( DDR_REG_BASE +0x52699*4 +0x02000000,0x60b8); +reg_write( DDR_REG_BASE +0x5269a*4 +0x02000000,0x88e1); +reg_write( DDR_REG_BASE +0x5269b*4 +0x02000000,0x1540); +reg_write( DDR_REG_BASE +0x5269c*4 +0x02000000,0x108b); +reg_write( DDR_REG_BASE +0x5269d*4 +0x02000000,0xf0f); +reg_write( DDR_REG_BASE +0x5269e*4 +0x02000000,0x12e4); +reg_write( DDR_REG_BASE +0x5269f*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x526a0*4 +0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x526a1*4 +0x02000000,0xbe9); +reg_write( DDR_REG_BASE +0x526a2*4 +0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x526a3*4 +0x02000000,0x491f); +reg_write( DDR_REG_BASE +0x526a4*4 +0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x526a5*4 +0x02000000,0x4950); +reg_write( DDR_REG_BASE +0x526a6*4 +0x02000000,0x7a0f); +reg_write( DDR_REG_BASE +0x526a7*4 +0x02000000,0x4c30); +reg_write( DDR_REG_BASE +0x526a8*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x526a9*4 +0x02000000,0x2009); +reg_write( DDR_REG_BASE +0x526aa*4 +0x02000000,0x82); +reg_write( DDR_REG_BASE +0x526ab*4 +0x02000000,0xca0c); +reg_write( DDR_REG_BASE +0x526ac*4 +0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x526ad*4 +0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x526ae*4 +0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x526af*4 +0x02000000,0x801); +reg_write( DDR_REG_BASE +0x526b0*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x526b1*4 +0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x526b2*4 +0x02000000,0x794f); +reg_write( DDR_REG_BASE +0x526b3*4 +0x02000000,0x8b00); +reg_write( DDR_REG_BASE +0x526b4*4 +0x02000000,0x907); +reg_write( DDR_REG_BASE +0x526b5*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x526b6*4 +0x02000000,0xab40); +reg_write( DDR_REG_BASE +0x526b7*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x526b8*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x526b9*4 +0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x526ba*4 +0x02000000,0xf209); +reg_write( DDR_REG_BASE +0x526bb*4 +0x02000000,0x821); +reg_write( DDR_REG_BASE +0x526bc*4 +0x02000000,0x1d1); +reg_write( DDR_REG_BASE +0x526bd*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x526be*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x526bf*4 +0x02000000,0x238); +reg_write( DDR_REG_BASE +0x526c0*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x526c1*4 +0x02000000,0x45); +reg_write( DDR_REG_BASE +0x526c2*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x526c3*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x526c4*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x526c5*4 +0x02000000,0x238); +reg_write( DDR_REG_BASE +0x526c6*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x526c7*4 +0x02000000,0x105); +reg_write( DDR_REG_BASE +0x526c8*4 +0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x526c9*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x526ca*4 +0x02000000,0x1210); +reg_write( DDR_REG_BASE +0x526cb*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x526cc*4 +0x02000000,0xe903); +reg_write( DDR_REG_BASE +0x526cd*4 +0x02000000,0x19); +reg_write( DDR_REG_BASE +0x526ce*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x526cf*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x526d0*4 +0x02000000,0x9018); +reg_write( DDR_REG_BASE +0x526d1*4 +0x02000000,0x64); +reg_write( DDR_REG_BASE +0x526d2*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x526d3*4 +0x02000000,0x55); +reg_write( DDR_REG_BASE +0x526d4*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x526d5*4 +0x02000000,0x1902); +reg_write( DDR_REG_BASE +0x526d6*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x526d7*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x526d8*4 +0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x526d9*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x526da*4 +0x02000000,0xca10); +reg_write( DDR_REG_BASE +0x526db*4 +0x02000000,0xe812); +reg_write( DDR_REG_BASE +0x526dc*4 +0x02000000,0xcc36); +reg_write( DDR_REG_BASE +0x526dd*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x526de*4 +0x02000000,0x8010); +reg_write( DDR_REG_BASE +0x526df*4 +0x02000000,0xf785); +reg_write( DDR_REG_BASE +0x526e0*4 +0x02000000,0xe6e); +reg_write( DDR_REG_BASE +0x526e1*4 +0x02000000,0xfdcf); +reg_write( DDR_REG_BASE +0x526e2*4 +0x02000000,0xcc36); +reg_write( DDR_REG_BASE +0x526e3*4 +0x02000000,0x2615); +reg_write( DDR_REG_BASE +0x526e4*4 +0x02000000,0x7001); +reg_write( DDR_REG_BASE +0x526e5*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x526e6*4 +0x02000000,0x1ca4); +reg_write( DDR_REG_BASE +0x526e7*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x526e8*4 +0x02000000,0xa1a0); +reg_write( DDR_REG_BASE +0x526e9*4 +0x02000000,0x1a36); +reg_write( DDR_REG_BASE +0x526ea*4 +0x02000000,0x301c); +reg_write( DDR_REG_BASE +0x526eb*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x526ec*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x526ed*4 +0x02000000,0x9018); +reg_write( DDR_REG_BASE +0x526ee*4 +0x02000000,0x64); +reg_write( DDR_REG_BASE +0x526ef*4 +0x02000000,0xb1a0); +reg_write( DDR_REG_BASE +0x526f0*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x526f1*4 +0x02000000,0xdd10); +reg_write( DDR_REG_BASE +0x526f2*4 +0x02000000,0xbd61); +reg_write( DDR_REG_BASE +0x526f3*4 +0x02000000,0xd01); +reg_write( DDR_REG_BASE +0x526f4*4 +0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x526f5*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x526f6*4 +0x02000000,0xb102); +reg_write( DDR_REG_BASE +0x526f7*4 +0x02000000,0x80e); +reg_write( DDR_REG_BASE +0x526f8*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x526f9*4 +0x02000000,0x1902); +reg_write( DDR_REG_BASE +0x526fa*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x526fb*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x526fc*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x526fd*4 +0x02000000,0x9018); +reg_write( DDR_REG_BASE +0x526fe*4 +0x02000000,0x8); +reg_write( DDR_REG_BASE +0x526ff*4 +0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x52700*4 +0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x52701*4 +0x02000000,0x801f); +reg_write( DDR_REG_BASE +0x52702*4 +0x02000000,0x195e); +reg_write( DDR_REG_BASE +0x52703*4 +0x02000000,0x45); +reg_write( DDR_REG_BASE +0x52704*4 +0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x52705*4 +0x02000000,0x801); +reg_write( DDR_REG_BASE +0x52706*4 +0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x52707*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52708*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52709*4 +0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x5270a*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5270b*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5270c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5270d*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5270e*4 +0x02000000,0x83b); +reg_write( DDR_REG_BASE +0x5270f*4 +0x02000000,0x13f); +reg_write( DDR_REG_BASE +0x52710*4 +0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x52711*4 +0x02000000,0xca10); +reg_write( DDR_REG_BASE +0x52712*4 +0x02000000,0x7ef0); +reg_write( DDR_REG_BASE +0x52713*4 +0x02000000,0xe80a); +reg_write( DDR_REG_BASE +0x52714*4 +0x02000000,0xcc36); +reg_write( DDR_REG_BASE +0x52715*4 +0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x52716*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52717*4 +0x02000000,0x7902); +reg_write( DDR_REG_BASE +0x52718*4 +0x02000000,0x6e02); +reg_write( DDR_REG_BASE +0x52719*4 +0x02000000,0x7030); +reg_write( DDR_REG_BASE +0x5271a*4 +0x02000000,0xdf8); +reg_write( DDR_REG_BASE +0x5271b*4 +0x02000000,0xfdca); +reg_write( DDR_REG_BASE +0x5271c*4 +0x02000000,0xf3a); +reg_write( DDR_REG_BASE +0x5271d*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5271e*4 +0x02000000,0xd808); +reg_write( DDR_REG_BASE +0x5271f*4 +0x02000000,0xf76); +reg_write( DDR_REG_BASE +0x52720*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x52721*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x52722*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x52723*4 +0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x52724*4 +0x02000000,0xf6a); +reg_write( DDR_REG_BASE +0x52725*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x52726*4 +0x02000000,0x1504); +reg_write( DDR_REG_BASE +0x52727*4 +0x02000000,0x1400); +reg_write( DDR_REG_BASE +0x52728*4 +0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x52729*4 +0x02000000,0xff9); +reg_write( DDR_REG_BASE +0x5272a*4 +0x02000000,0x9384); +reg_write( DDR_REG_BASE +0x5272b*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5272c*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x5272d*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x5272e*4 +0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x5272f*4 +0x02000000,0x2100); +reg_write( DDR_REG_BASE +0x52730*4 +0x02000000,0x680); +reg_write( DDR_REG_BASE +0x52731*4 +0x02000000,0x106e); +reg_write( DDR_REG_BASE +0x52732*4 +0x02000000,0x81); +reg_write( DDR_REG_BASE +0x52733*4 +0x02000000,0x915); +reg_write( DDR_REG_BASE +0x52734*4 +0x02000000,0xa5); +reg_write( DDR_REG_BASE +0x52735*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x52736*4 +0x02000000,0x4a30); +reg_write( DDR_REG_BASE +0x52737*4 +0x02000000,0x796f); +reg_write( DDR_REG_BASE +0x52738*4 +0x02000000,0x9ef); +reg_write( DDR_REG_BASE +0x52739*4 +0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x5273a*4 +0x02000000,0x7a0f); +reg_write( DDR_REG_BASE +0x5273b*4 +0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x5273c*4 +0x02000000,0x1070); +reg_write( DDR_REG_BASE +0x5273d*4 +0x02000000,0x8c); +reg_write( DDR_REG_BASE +0x5273e*4 +0x02000000,0x249a); +reg_write( DDR_REG_BASE +0x5273f*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x52740*4 +0x02000000,0x7c45); +reg_write( DDR_REG_BASE +0x52741*4 +0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x52742*4 +0x02000000,0x788f); +reg_write( DDR_REG_BASE +0x52743*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52744*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52745*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52746*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52747*4 +0x02000000,0xc1a5); +reg_write( DDR_REG_BASE +0x52748*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x52749*4 +0x02000000,0x2440); +reg_write( DDR_REG_BASE +0x5274a*4 +0x02000000,0x3440); +reg_write( DDR_REG_BASE +0x5274b*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5274c*4 +0x02000000,0x2440); +reg_write( DDR_REG_BASE +0x5274d*4 +0x02000000,0x34c0); +reg_write( DDR_REG_BASE +0x5274e*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x5274f*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52750*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x52751*4 +0x02000000,0x4358); +reg_write( DDR_REG_BASE +0x52752*4 +0x02000000,0x4628); +reg_write( DDR_REG_BASE +0x52753*4 +0x02000000,0x1c13); +reg_write( DDR_REG_BASE +0x52754*4 +0x02000000,0x30c2); +reg_write( DDR_REG_BASE +0x52755*4 +0x02000000,0x1c12); +reg_write( DDR_REG_BASE +0x52756*4 +0x02000000,0x30c2); +reg_write( DDR_REG_BASE +0x52757*4 +0x02000000,0x1c11); +reg_write( DDR_REG_BASE +0x52758*4 +0x02000000,0x30c2); +reg_write( DDR_REG_BASE +0x52759*4 +0x02000000,0xb7e); +reg_write( DDR_REG_BASE +0x5275a*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5275b*4 +0x02000000,0xc364); +reg_write( DDR_REG_BASE +0x5275c*4 +0x02000000,0xc084); +reg_write( DDR_REG_BASE +0x5275d*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5275e*4 +0x02000000,0x2440); +reg_write( DDR_REG_BASE +0x5275f*4 +0x02000000,0x3480); +reg_write( DDR_REG_BASE +0x52760*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52761*4 +0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x52762*4 +0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x52763*4 +0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x52764*4 +0x02000000,0xb66); +reg_write( DDR_REG_BASE +0x52765*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52766*4 +0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x52767*4 +0x02000000,0x1412); +reg_write( DDR_REG_BASE +0x52768*4 +0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x52769*4 +0x02000000,0x1413); +reg_write( DDR_REG_BASE +0x5276a*4 +0x02000000,0x3082); +reg_write( DDR_REG_BASE +0x5276b*4 +0x02000000,0xc814); +reg_write( DDR_REG_BASE +0x5276c*4 +0x02000000,0xc524); +reg_write( DDR_REG_BASE +0x5276d*4 +0x02000000,0x2209); +reg_write( DDR_REG_BASE +0x5276e*4 +0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x5276f*4 +0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x52770*4 +0x02000000,0xc); +reg_write( DDR_REG_BASE +0x52771*4 +0x02000000,0x1411); +reg_write( DDR_REG_BASE +0x52772*4 +0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x52773*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52774*4 +0x02000000,0x2009); +reg_write( DDR_REG_BASE +0x52775*4 +0x02000000,0x34f); +reg_write( DDR_REG_BASE +0x52776*4 +0x02000000,0xc818); +reg_write( DDR_REG_BASE +0x52777*4 +0x02000000,0x78ec); +reg_write( DDR_REG_BASE +0x52778*4 +0x02000000,0x6098); +reg_write( DDR_REG_BASE +0x52779*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5277a*4 +0x02000000,0xc812); +reg_write( DDR_REG_BASE +0x5277b*4 +0x02000000,0x1203); +reg_write( DDR_REG_BASE +0x5277c*4 +0x02000000,0x308c); +reg_write( DDR_REG_BASE +0x5277d*4 +0x02000000,0x843); +reg_write( DDR_REG_BASE +0x5277e*4 +0x02000000,0x304); +reg_write( DDR_REG_BASE +0x5277f*4 +0x02000000,0x1202); +reg_write( DDR_REG_BASE +0x52780*4 +0x02000000,0x308c); +reg_write( DDR_REG_BASE +0x52781*4 +0x02000000,0xc3b); +reg_write( DDR_REG_BASE +0x52782*4 +0x02000000,0x1024); +reg_write( DDR_REG_BASE +0x52783*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x52784*4 +0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x52785*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52786*4 +0x02000000,0x3d); +reg_write( DDR_REG_BASE +0x52787*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x52788*4 +0x02000000,0xae2); +reg_write( DDR_REG_BASE +0x52789*4 +0x02000000,0xfdcf); +reg_write( DDR_REG_BASE +0x5278a*4 +0x02000000,0xc203); +reg_write( DDR_REG_BASE +0x5278b*4 +0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x5278c*4 +0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x5278d*4 +0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x5278e*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x5278f*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x52790*4 +0x02000000,0x41e1); +reg_write( DDR_REG_BASE +0x52791*4 +0x02000000,0xad2); +reg_write( DDR_REG_BASE +0x52792*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52793*4 +0x02000000,0x43a1); +reg_write( DDR_REG_BASE +0x52794*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52795*4 +0x02000000,0x274f); +reg_write( DDR_REG_BASE +0x52796*4 +0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x52797*4 +0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x52798*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52799*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x5279a*4 +0x02000000,0xabe); +reg_write( DDR_REG_BASE +0x5279b*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5279c*4 +0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x5279d*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x5279e*4 +0x02000000,0xc0a5); +reg_write( DDR_REG_BASE +0x5279f*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x527a0*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x527a1*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x527a2*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x527a3*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x527a4*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x527a5*4 +0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x527a6*4 +0x02000000,0x3511); +reg_write( DDR_REG_BASE +0x527a7*4 +0x02000000,0xf66); +reg_write( DDR_REG_BASE +0x527a8*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x527a9*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x527aa*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x527ab*4 +0x02000000,0x708e); +reg_write( DDR_REG_BASE +0x527ac*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x527ad*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x527ae*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x527af*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x527b0*4 +0x02000000,0x1b70); +reg_write( DDR_REG_BASE +0x527b1*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x527b2*4 +0x02000000,0xfea); +reg_write( DDR_REG_BASE +0x527b3*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x527b4*4 +0x02000000,0xda28); +reg_write( DDR_REG_BASE +0x527b5*4 +0x02000000,0xeca); +reg_write( DDR_REG_BASE +0x527b6*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x527b7*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x527b8*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x527b9*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x527ba*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x527bb*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x527bc*4 +0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x527bd*4 +0x02000000,0x1c38); +reg_write( DDR_REG_BASE +0x527be*4 +0x02000000,0x3001); +reg_write( DDR_REG_BASE +0x527bf*4 +0x02000000,0x1c3c); +reg_write( DDR_REG_BASE +0x527c0*4 +0x02000000,0x3003); +reg_write( DDR_REG_BASE +0x527c1*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x527c2*4 +0x02000000,0x641); +reg_write( DDR_REG_BASE +0x527c3*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x527c4*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x527c5*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x527c6*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x527c7*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x527c8*4 +0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x527c9*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x527ca*4 +0x02000000,0x2100); +reg_write( DDR_REG_BASE +0x527cb*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x527cc*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x527cd*4 +0x02000000,0x674); +reg_write( DDR_REG_BASE +0x527ce*4 +0x02000000,0x1007); +reg_write( DDR_REG_BASE +0x527cf*4 +0x02000000,0xcf); +reg_write( DDR_REG_BASE +0x527d0*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x527d1*4 +0x02000000,0xbaa); +reg_write( DDR_REG_BASE +0x527d2*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x527d3*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x527d4*4 +0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x527d5*4 +0x02000000,0x1f8e); +reg_write( DDR_REG_BASE +0x527d6*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x527d7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x527d8*4 +0x02000000,0x2605); +reg_write( DDR_REG_BASE +0x527d9*4 +0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x527da*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x527db*4 +0x02000000,0x92); +reg_write( DDR_REG_BASE +0x527dc*4 +0x02000000,0x90a0); +reg_write( DDR_REG_BASE +0x527dd*4 +0x02000000,0xed6); +reg_write( DDR_REG_BASE +0x527de*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x527df*4 +0x02000000,0x2553); +reg_write( DDR_REG_BASE +0x527e0*4 +0x02000000,0x1140); +reg_write( DDR_REG_BASE +0x527e1*4 +0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x527e2*4 +0x02000000,0x78bd); +reg_write( DDR_REG_BASE +0x527e3*4 +0x02000000,0xf96b); +reg_write( DDR_REG_BASE +0x527e4*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x527e5*4 +0x02000000,0xec6); +reg_write( DDR_REG_BASE +0x527e6*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x527e7*4 +0x02000000,0xb8c5); +reg_write( DDR_REG_BASE +0x527e8*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x527e9*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x527ea*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x527eb*4 +0x02000000,0x474); +reg_write( DDR_REG_BASE +0x527ec*4 +0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x527ed*4 +0x02000000,0x6c2); +reg_write( DDR_REG_BASE +0x527ee*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x527ef*4 +0x02000000,0x91); +reg_write( DDR_REG_BASE +0x527f0*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x527f1*4 +0x02000000,0xa12); +reg_write( DDR_REG_BASE +0x527f2*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x527f3*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x527f4*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x527f5*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x527f6*4 +0x02000000,0x474); +reg_write( DDR_REG_BASE +0x527f7*4 +0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x527f8*4 +0x02000000,0x342); +reg_write( DDR_REG_BASE +0x527f9*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x527fa*4 +0x02000000,0x92); +reg_write( DDR_REG_BASE +0x527fb*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x527fc*4 +0x02000000,0x9fa); +reg_write( DDR_REG_BASE +0x527fd*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x527fe*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x527ff*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52800*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52801*4 +0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x52802*4 +0x02000000,0xd7a); +reg_write( DDR_REG_BASE +0x52803*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52804*4 +0x02000000,0xc38e); +reg_write( DDR_REG_BASE +0x52805*4 +0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x52806*4 +0x02000000,0x243); +reg_write( DDR_REG_BASE +0x52807*4 +0x02000000,0x881a); +reg_write( DDR_REG_BASE +0x52808*4 +0x02000000,0x889); +reg_write( DDR_REG_BASE +0x52809*4 +0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x5280a*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5280b*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5280c*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5280d*4 +0x02000000,0x93); +reg_write( DDR_REG_BASE +0x5280e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5280f*4 +0x02000000,0x9d6); +reg_write( DDR_REG_BASE +0x52810*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52811*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x52812*4 +0x02000000,0x2605); +reg_write( DDR_REG_BASE +0x52813*4 +0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x52814*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52815*4 +0x02000000,0xe090); +reg_write( DDR_REG_BASE +0x52816*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x52817*4 +0x02000000,0x45); +reg_write( DDR_REG_BASE +0x52818*4 +0x02000000,0xf015); +reg_write( DDR_REG_BASE +0x52819*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5281a*4 +0x02000000,0x94); +reg_write( DDR_REG_BASE +0x5281b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5281c*4 +0x02000000,0x9ba); +reg_write( DDR_REG_BASE +0x5281d*4 +0x02000000,0xfdcf); +reg_write( DDR_REG_BASE +0x5281e*4 +0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x5281f*4 +0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x52820*4 +0x02000000,0xdce); +reg_write( DDR_REG_BASE +0x52821*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x52822*4 +0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x52823*4 +0x02000000,0xe808); +reg_write( DDR_REG_BASE +0x52824*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52825*4 +0x02000000,0x722c); +reg_write( DDR_REG_BASE +0x52826*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52827*4 +0x02000000,0xd32); +reg_write( DDR_REG_BASE +0x52828*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52829*4 +0x02000000,0xc38e); +reg_write( DDR_REG_BASE +0x5282a*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5282b*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5282c*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5282d*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5282e*4 +0x02000000,0x7e0f); +reg_write( DDR_REG_BASE +0x5282f*4 +0x02000000,0xed7); +reg_write( DDR_REG_BASE +0x52830*4 +0x02000000,0x9134); +reg_write( DDR_REG_BASE +0x52831*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x52832*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52833*4 +0x02000000,0x95); +reg_write( DDR_REG_BASE +0x52834*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52835*4 +0x02000000,0x98a); +reg_write( DDR_REG_BASE +0x52836*4 +0x02000000,0xfdcf); +reg_write( DDR_REG_BASE +0x52837*4 +0x02000000,0xc22f); +reg_write( DDR_REG_BASE +0x52838*4 +0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x52839*4 +0x02000000,0xd9e); +reg_write( DDR_REG_BASE +0x5283a*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x5283b*4 +0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x5283c*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5283d*4 +0x02000000,0x96); +reg_write( DDR_REG_BASE +0x5283e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5283f*4 +0x02000000,0x976); +reg_write( DDR_REG_BASE +0x52840*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52841*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x52842*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52843*4 +0x02000000,0xac6); +reg_write( DDR_REG_BASE +0x52844*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x52845*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52846*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52847*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52848*4 +0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x52849*4 +0x02000000,0xcee); +reg_write( DDR_REG_BASE +0x5284a*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5284b*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x5284c*4 +0x02000000,0x70f5); +reg_write( DDR_REG_BASE +0x5284d*4 +0x02000000,0x4ce); +reg_write( DDR_REG_BASE +0x5284e*4 +0x02000000,0x2a); +reg_write( DDR_REG_BASE +0x5284f*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52850*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52851*4 +0x02000000,0x7083); +reg_write( DDR_REG_BASE +0x52852*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52853*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52854*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52855*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52856*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52857*4 +0x02000000,0x104); +reg_write( DDR_REG_BASE +0x52858*4 +0x02000000,0xe9e); +reg_write( DDR_REG_BASE +0x52859*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5285a*4 +0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x5285b*4 +0x02000000,0xc094); +reg_write( DDR_REG_BASE +0x5285c*4 +0x02000000,0xe96); +reg_write( DDR_REG_BASE +0x5285d*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5285e*4 +0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x5285f*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x52860*4 +0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x52861*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52862*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52863*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52864*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x52865*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52866*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52867*4 +0x02000000,0xc052); +reg_write( DDR_REG_BASE +0x52868*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52869*4 +0x02000000,0x48d); +reg_write( DDR_REG_BASE +0x5286a*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5286b*4 +0x02000000,0xc350); +reg_write( DDR_REG_BASE +0x5286c*4 +0x02000000,0xc105); +reg_write( DDR_REG_BASE +0x5286d*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x5286e*4 +0x02000000,0x2011); +reg_write( DDR_REG_BASE +0x5286f*4 +0x02000000,0x8040); +reg_write( DDR_REG_BASE +0x52870*4 +0x02000000,0x478); +reg_write( DDR_REG_BASE +0x52871*4 +0x02000000,0x21); +reg_write( DDR_REG_BASE +0x52872*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52873*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52874*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52875*4 +0x02000000,0xf76); +reg_write( DDR_REG_BASE +0x52876*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x52877*4 +0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x52878*4 +0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x52879*4 +0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x5287a*4 +0x02000000,0x3dc0); +reg_write( DDR_REG_BASE +0x5287b*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5287c*4 +0x02000000,0xe56); +reg_write( DDR_REG_BASE +0x5287d*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5287e*4 +0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x5287f*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52880*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52881*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x52882*4 +0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x52883*4 +0x02000000,0xc01); +reg_write( DDR_REG_BASE +0x52884*4 +0x02000000,0xc010); +reg_write( DDR_REG_BASE +0x52885*4 +0x02000000,0x43db); +reg_write( DDR_REG_BASE +0x52886*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52887*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52888*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52889*4 +0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x5288a*4 +0x02000000,0xca06); +reg_write( DDR_REG_BASE +0x5288b*4 +0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x5288c*4 +0x02000000,0xf039); +reg_write( DDR_REG_BASE +0x5288d*4 +0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x5288e*4 +0x02000000,0x33c0); +reg_write( DDR_REG_BASE +0x5288f*4 +0x02000000,0xf032); +reg_write( DDR_REG_BASE +0x52890*4 +0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x52891*4 +0x02000000,0x1f81); +reg_write( DDR_REG_BASE +0x52892*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52893*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52894*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52895*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52896*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52897*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52898*4 +0x02000000,0xc104); +reg_write( DDR_REG_BASE +0x52899*4 +0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x5289a*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x5289b*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5289c*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5289d*4 +0x02000000,0x6c0); +reg_write( DDR_REG_BASE +0x5289e*4 +0x02000000,0x8e6); +reg_write( DDR_REG_BASE +0x5289f*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x528a0*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x528a1*4 +0x02000000,0x7a1c); +reg_write( DDR_REG_BASE +0x528a2*4 +0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x528a3*4 +0x02000000,0x3dc1); +reg_write( DDR_REG_BASE +0x528a4*4 +0x02000000,0x7a5c); +reg_write( DDR_REG_BASE +0x528a5*4 +0x02000000,0x2114); +reg_write( DDR_REG_BASE +0x528a6*4 +0x02000000,0x781); +reg_write( DDR_REG_BASE +0x528a7*4 +0x02000000,0x7a5c); +reg_write( DDR_REG_BASE +0x528a8*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x528a9*4 +0x02000000,0x7a5c); +reg_write( DDR_REG_BASE +0x528aa*4 +0x02000000,0xd91b); +reg_write( DDR_REG_BASE +0x528ab*4 +0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x528ac*4 +0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x528ad*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x528ae*4 +0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x528af*4 +0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x528b0*4 +0x02000000,0x6059); +reg_write( DDR_REG_BASE +0x528b1*4 +0x02000000,0x2844); +reg_write( DDR_REG_BASE +0x528b2*4 +0x02000000,0x800); +reg_write( DDR_REG_BASE +0x528b3*4 +0x02000000,0xb9c4); +reg_write( DDR_REG_BASE +0x528b4*4 +0x02000000,0x7942); +reg_write( DDR_REG_BASE +0x528b5*4 +0x02000000,0x2354); +reg_write( DDR_REG_BASE +0x528b6*4 +0x02000000,0x3c82); +reg_write( DDR_REG_BASE +0x528b7*4 +0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x528b8*4 +0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x528b9*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x528ba*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x528bb*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x528bc*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x528bd*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x528be*4 +0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x528bf*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x528c0*4 +0x02000000,0xba1); +reg_write( DDR_REG_BASE +0x528c1*4 +0x02000000,0x8234); +reg_write( DDR_REG_BASE +0x528c2*4 +0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x528c3*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x528c4*4 +0x02000000,0xe709); +reg_write( DDR_REG_BASE +0x528c5*4 +0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x528c6*4 +0x02000000,0xd8f); +reg_write( DDR_REG_BASE +0x528c7*4 +0x02000000,0x9024); +reg_write( DDR_REG_BASE +0x528c8*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x528c9*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x528ca*4 +0x02000000,0xc305); +reg_write( DDR_REG_BASE +0x528cb*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x528cc*4 +0x02000000,0x8e); +reg_write( DDR_REG_BASE +0x528cd*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x528ce*4 +0x02000000,0x2038); +reg_write( DDR_REG_BASE +0x528cf*4 +0x02000000,0x380); +reg_write( DDR_REG_BASE +0x528d0*4 +0x02000000,0x8a2); +reg_write( DDR_REG_BASE +0x528d1*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x528d2*4 +0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x528d3*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x528d4*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x528d5*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x528d6*4 +0x02000000,0xa8c1); +reg_write( DDR_REG_BASE +0x528d7*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x528d8*4 +0x02000000,0x7001); +reg_write( DDR_REG_BASE +0x528d9*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x528da*4 +0x02000000,0x674); +reg_write( DDR_REG_BASE +0x528db*4 +0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x528dc*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x528dd*4 +0x02000000,0x9aa); +reg_write( DDR_REG_BASE +0x528de*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x528df*4 +0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x528e0*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x528e1*4 +0x02000000,0x709b); +reg_write( DDR_REG_BASE +0x528e2*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x528e3*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x528e4*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x528e5*4 +0x02000000,0x710d); +reg_write( DDR_REG_BASE +0x528e6*4 +0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x528e7*4 +0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x528e8*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x528e9*4 +0x02000000,0xfce); +reg_write( DDR_REG_BASE +0x528ea*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x528eb*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x528ec*4 +0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x528ed*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x528ee*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x528ef*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x528f0*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x528f1*4 +0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x528f2*4 +0x02000000,0xeca); +reg_write( DDR_REG_BASE +0x528f3*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x528f4*4 +0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x528f5*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x528f6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x528f7*4 +0x02000000,0xff7f); +reg_write( DDR_REG_BASE +0x528f8*4 +0x02000000,0x78a4); +reg_write( DDR_REG_BASE +0x528f9*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x528fa*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x528fb*4 +0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x528fc*4 +0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x528fd*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x528fe*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x528ff*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52900*4 +0x02000000,0x3f4); +reg_write( DDR_REG_BASE +0x52901*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52902*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52903*4 +0x02000000,0x4c1); +reg_write( DDR_REG_BASE +0x52904*4 +0x02000000,0xe7a); +reg_write( DDR_REG_BASE +0x52905*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52906*4 +0x02000000,0xda60); +reg_write( DDR_REG_BASE +0x52907*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52908*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52909*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5290a*4 +0x02000000,0x3f4); +reg_write( DDR_REG_BASE +0x5290b*4 +0x02000000,0xbea); +reg_write( DDR_REG_BASE +0x5290c*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5290d*4 +0x02000000,0xd960); +reg_write( DDR_REG_BASE +0x5290e*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5290f*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52910*4 +0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52911*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52912*4 +0x02000000,0xf0c4); +reg_write( DDR_REG_BASE +0x52913*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52914*4 +0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x52915*4 +0x02000000,0x17cd); +reg_write( DDR_REG_BASE +0x52916*4 +0x02000000,0xed05); +reg_write( DDR_REG_BASE +0x52917*4 +0x02000000,0xbd61); +reg_write( DDR_REG_BASE +0x52918*4 +0x02000000,0xdff); +reg_write( DDR_REG_BASE +0x52919*4 +0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x5291a*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5291b*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5291c*4 +0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x5291d*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5291e*4 +0x02000000,0x200f); +reg_write( DDR_REG_BASE +0x5291f*4 +0x02000000,0x380); +reg_write( DDR_REG_BASE +0x52920*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52921*4 +0x02000000,0xaf2); +reg_write( DDR_REG_BASE +0x52922*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x52923*4 +0x02000000,0xc051); +reg_write( DDR_REG_BASE +0x52924*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52925*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x52926*4 +0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x52927*4 +0x02000000,0x7a1b); +reg_write( DDR_REG_BASE +0x52928*4 +0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x52929*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x5292a*4 +0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x5292b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5292c*4 +0x02000000,0x3d4); +reg_write( DDR_REG_BASE +0x5292d*4 +0x02000000,0x22ce); +reg_write( DDR_REG_BASE +0x5292e*4 +0x02000000,0x21); +reg_write( DDR_REG_BASE +0x5292f*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x52930*4 +0x02000000,0xa940); +reg_write( DDR_REG_BASE +0x52931*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52932*4 +0x02000000,0x8eb); +reg_write( DDR_REG_BASE +0x52933*4 +0x02000000,0x8434); +reg_write( DDR_REG_BASE +0x52934*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x52935*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x52936*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52937*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52938*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x52939*4 +0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x5293a*4 +0x02000000,0x9e); +reg_write( DDR_REG_BASE +0x5293b*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5293c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5293d*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x5293e*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x5293f*4 +0x02000000,0x3f9b); +reg_write( DDR_REG_BASE +0x52940*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52941*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52942*4 +0x02000000,0x8864); +reg_write( DDR_REG_BASE +0x52943*4 +0x02000000,0x4468); +reg_write( DDR_REG_BASE +0x52944*4 +0x02000000,0x1c34); +reg_write( DDR_REG_BASE +0x52945*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52946*4 +0x02000000,0xf041); +reg_write( DDR_REG_BASE +0x52947*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x52948*4 +0x02000000,0xf03c); +reg_write( DDR_REG_BASE +0x52949*4 +0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x5294a*4 +0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x5294b*4 +0x02000000,0xc01); +reg_write( DDR_REG_BASE +0x5294c*4 +0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x5294d*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x5294e*4 +0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x5294f*4 +0x02000000,0x1f81); +reg_write( DDR_REG_BASE +0x52950*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52951*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52952*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x52953*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x52954*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52955*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52956*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52957*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52958*4 +0x02000000,0xb891); +reg_write( DDR_REG_BASE +0x52959*4 +0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x5295a*4 +0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x5295b*4 +0x02000000,0xf53); +reg_write( DDR_REG_BASE +0x5295c*4 +0x02000000,0x1231); +reg_write( DDR_REG_BASE +0x5295d*4 +0x02000000,0x90c0); +reg_write( DDR_REG_BASE +0x5295e*4 +0x02000000,0x78dd); +reg_write( DDR_REG_BASE +0x5295f*4 +0x02000000,0xf8ad); +reg_write( DDR_REG_BASE +0x52960*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52961*4 +0x02000000,0xbec4); +reg_write( DDR_REG_BASE +0x52962*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52963*4 +0x02000000,0xe808); +reg_write( DDR_REG_BASE +0x52964*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x52965*4 +0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x52966*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52967*4 +0x02000000,0x2180); +reg_write( DDR_REG_BASE +0x52968*4 +0x02000000,0x30); +reg_write( DDR_REG_BASE +0x52969*4 +0x02000000,0x79c5); +reg_write( DDR_REG_BASE +0x5296a*4 +0x02000000,0x255f); +reg_write( DDR_REG_BASE +0x5296b*4 +0x02000000,0x148b); +reg_write( DDR_REG_BASE +0x5296c*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x5296d*4 +0x02000000,0x3f82); +reg_write( DDR_REG_BASE +0x5296e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5296f*4 +0x02000000,0x320); +reg_write( DDR_REG_BASE +0x52970*4 +0x02000000,0x7261); +reg_write( DDR_REG_BASE +0x52971*4 +0x02000000,0xb228); +reg_write( DDR_REG_BASE +0x52972*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52973*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52974*4 +0x02000000,0x141f); +reg_write( DDR_REG_BASE +0x52975*4 +0x02000000,0x813); +reg_write( DDR_REG_BASE +0x52976*4 +0x02000000,0x150); +reg_write( DDR_REG_BASE +0x52977*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52978*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52979*4 +0x02000000,0x2080); +reg_write( DDR_REG_BASE +0x5297a*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5297b*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5297c*4 +0x02000000,0x381); +reg_write( DDR_REG_BASE +0x5297d*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x5297e*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x5297f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52980*4 +0x02000000,0x26c); +reg_write( DDR_REG_BASE +0x52981*4 +0x02000000,0x7061); +reg_write( DDR_REG_BASE +0x52982*4 +0x02000000,0xb028); +reg_write( DDR_REG_BASE +0x52983*4 +0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x52984*4 +0x02000000,0xf8b); +reg_write( DDR_REG_BASE +0x52985*4 +0x02000000,0x9254); +reg_write( DDR_REG_BASE +0x52986*4 +0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x52987*4 +0x02000000,0x7d8f); +reg_write( DDR_REG_BASE +0x52988*4 +0x02000000,0xe7f); +reg_write( DDR_REG_BASE +0x52989*4 +0x02000000,0xb365); +reg_write( DDR_REG_BASE +0x5298a*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5298b*4 +0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x5298c*4 +0x02000000,0x24f); +reg_write( DDR_REG_BASE +0x5298d*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5298e*4 +0x02000000,0xf0cb); +reg_write( DDR_REG_BASE +0x5298f*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52990*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52991*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52992*4 +0x02000000,0x320); +reg_write( DDR_REG_BASE +0x52993*4 +0x02000000,0xa96); +reg_write( DDR_REG_BASE +0x52994*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x52995*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52996*4 +0x02000000,0xe0e); +reg_write( DDR_REG_BASE +0x52997*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52998*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52999*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5299a*4 +0x02000000,0xbb2); +reg_write( DDR_REG_BASE +0x5299b*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x5299c*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x5299d*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x5299e*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5299f*4 +0x02000000,0xe024); +reg_write( DDR_REG_BASE +0x529a0*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x529a1*4 +0x02000000,0x1f84); +reg_write( DDR_REG_BASE +0x529a2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x529a3*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x529a4*4 +0x02000000,0xb506); +reg_write( DDR_REG_BASE +0x529a5*4 +0x02000000,0x1dfe); +reg_write( DDR_REG_BASE +0x529a6*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x529a7*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x529a8*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x529a9*4 +0x02000000,0x1da8); +reg_write( DDR_REG_BASE +0x529aa*4 +0x02000000,0x101c); +reg_write( DDR_REG_BASE +0x529ab*4 +0x02000000,0x1da9); +reg_write( DDR_REG_BASE +0x529ac*4 +0x02000000,0x101c); +reg_write( DDR_REG_BASE +0x529ad*4 +0x02000000,0xc012); +reg_write( DDR_REG_BASE +0x529ae*4 +0x02000000,0xde21); +reg_write( DDR_REG_BASE +0x529af*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x529b0*4 +0x02000000,0xb8e2); +reg_write( DDR_REG_BASE +0x529b1*4 +0x02000000,0x26ca); +reg_write( DDR_REG_BASE +0x529b2*4 +0x02000000,0x1be1); +reg_write( DDR_REG_BASE +0x529b3*4 +0x02000000,0x942); +reg_write( DDR_REG_BASE +0x529b4*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x529b5*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x529b6*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x529b7*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x529b8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x529b9*4 +0x02000000,0x104); +reg_write( DDR_REG_BASE +0x529ba*4 +0x02000000,0xf72); +reg_write( DDR_REG_BASE +0x529bb*4 +0x02000000,0xff0f); +reg_write( DDR_REG_BASE +0x529bc*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x529bd*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x529be*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x529bf*4 +0x02000000,0x26c); +reg_write( DDR_REG_BASE +0x529c0*4 +0x02000000,0xa3a); +reg_write( DDR_REG_BASE +0x529c1*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x529c2*4 +0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x529c3*4 +0x02000000,0xdb6); +reg_write( DDR_REG_BASE +0x529c4*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x529c5*4 +0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x529c6*4 +0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x529c7*4 +0x02000000,0xb5a); +reg_write( DDR_REG_BASE +0x529c8*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x529c9*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x529ca*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x529cb*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x529cc*4 +0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x529cd*4 +0x02000000,0x1f84); +reg_write( DDR_REG_BASE +0x529ce*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x529cf*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x529d0*4 +0x02000000,0xb526); +reg_write( DDR_REG_BASE +0x529d1*4 +0x02000000,0x1dfe); +reg_write( DDR_REG_BASE +0x529d2*4 +0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x529d3*4 +0x02000000,0x1da8); +reg_write( DDR_REG_BASE +0x529d4*4 +0x02000000,0x101c); +reg_write( DDR_REG_BASE +0x529d5*4 +0x02000000,0x1da9); +reg_write( DDR_REG_BASE +0x529d6*4 +0x02000000,0x101c); +reg_write( DDR_REG_BASE +0x529d7*4 +0x02000000,0x8fa); +reg_write( DDR_REG_BASE +0x529d8*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x529d9*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x529da*4 +0x02000000,0xf32); +reg_write( DDR_REG_BASE +0x529db*4 +0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x529dc*4 +0x02000000,0xc094); +reg_write( DDR_REG_BASE +0x529dd*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x529de*4 +0x02000000,0x45e9); +reg_write( DDR_REG_BASE +0x529df*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x529e0*4 +0x02000000,0xc053); +reg_write( DDR_REG_BASE +0x529e1*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x529e2*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x529e3*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x529e4*4 +0x02000000,0x8804); +reg_write( DDR_REG_BASE +0x529e5*4 +0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x529e6*4 +0x02000000,0xf063); +reg_write( DDR_REG_BASE +0x529e7*4 +0x02000000,0xe508); +reg_write( DDR_REG_BASE +0x529e8*4 +0x02000000,0x722c); +reg_write( DDR_REG_BASE +0x529e9*4 +0x02000000,0xde08); +reg_write( DDR_REG_BASE +0x529ea*4 +0x02000000,0xf05a); +reg_write( DDR_REG_BASE +0x529eb*4 +0x02000000,0x7ab0); +reg_write( DDR_REG_BASE +0x529ec*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x529ed*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x529ee*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x529ef*4 +0x02000000,0x104); +reg_write( DDR_REG_BASE +0x529f0*4 +0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x529f1*4 +0x02000000,0x8c); +reg_write( DDR_REG_BASE +0x529f2*4 +0x02000000,0xc094); +reg_write( DDR_REG_BASE +0x529f3*4 +0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x529f4*4 +0x02000000,0x83); +reg_write( DDR_REG_BASE +0x529f5*4 +0x02000000,0x4b90); +reg_write( DDR_REG_BASE +0x529f6*4 +0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x529f7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x529f8*4 +0x02000000,0x780e); +reg_write( DDR_REG_BASE +0x529f9*4 +0x02000000,0x883); +reg_write( DDR_REG_BASE +0x529fa*4 +0x02000000,0x1b3); +reg_write( DDR_REG_BASE +0x529fb*4 +0x02000000,0x7134); +reg_write( DDR_REG_BASE +0x529fc*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x529fd*4 +0x02000000,0xf246); +reg_write( DDR_REG_BASE +0x529fe*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x529ff*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52a00*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52a01*4 +0x02000000,0xac); +reg_write( DDR_REG_BASE +0x52a02*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x52a03*4 +0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x52a04*4 +0x02000000,0xe3a); +reg_write( DDR_REG_BASE +0x52a05*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52a06*4 +0x02000000,0x43c1); +reg_write( DDR_REG_BASE +0x52a07*4 +0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x52a08*4 +0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x52a09*4 +0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x52a0a*4 +0x02000000,0x8c1); +reg_write( DDR_REG_BASE +0x52a0b*4 +0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x52a0c*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x52a0d*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x52a0e*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52a0f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a10*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52a11*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52a12*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52a13*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52a14*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52a15*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52a16*4 +0x02000000,0x200); +reg_write( DDR_REG_BASE +0x52a17*4 +0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x52a18*4 +0x02000000,0x9040); +reg_write( DDR_REG_BASE +0x52a19*4 +0x02000000,0xc013); +reg_write( DDR_REG_BASE +0x52a1a*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52a1b*4 +0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x52a1c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a1d*4 +0x02000000,0x3d4); +reg_write( DDR_REG_BASE +0x52a1e*4 +0x02000000,0x2133); +reg_write( DDR_REG_BASE +0x52a1f*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52a20*4 +0x02000000,0xc240); +reg_write( DDR_REG_BASE +0x52a21*4 +0x02000000,0x6158); +reg_write( DDR_REG_BASE +0x52a22*4 +0x02000000,0x780e); +reg_write( DDR_REG_BASE +0x52a23*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52a24*4 +0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x52a25*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a26*4 +0x02000000,0x2049); +reg_write( DDR_REG_BASE +0x52a27*4 +0x02000000,0x800); +reg_write( DDR_REG_BASE +0x52a28*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x52a29*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52a2a*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52a2b*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x52a2c*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52a2d*4 +0x02000000,0xad); +reg_write( DDR_REG_BASE +0x52a2e*4 +0x02000000,0x6); +reg_write( DDR_REG_BASE +0x52a2f*4 +0x02000000,0xd96); +reg_write( DDR_REG_BASE +0x52a30*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52a31*4 +0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x52a32*4 +0x02000000,0xc104); +reg_write( DDR_REG_BASE +0x52a33*4 +0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x52a34*4 +0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x52a35*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52a36*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52a37*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52a38*4 +0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x52a39*4 +0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x52a3a*4 +0x02000000,0x3dc0); +reg_write( DDR_REG_BASE +0x52a3b*4 +0x02000000,0x2014); +reg_write( DDR_REG_BASE +0x52a3c*4 +0x02000000,0x82); +reg_write( DDR_REG_BASE +0x52a3d*4 +0x02000000,0x6398); +reg_write( DDR_REG_BASE +0x52a3e*4 +0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x52a3f*4 +0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x52a40*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a41*4 +0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x52a42*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x52a43*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x52a44*4 +0x02000000,0xe4f); +reg_write( DDR_REG_BASE +0x52a45*4 +0x02000000,0x9254); +reg_write( DDR_REG_BASE +0x52a46*4 +0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x52a47*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52a48*4 +0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x52a49*4 +0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x52a4a*4 +0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x52a4b*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52a4c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52a4d*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x52a4e*4 +0x02000000,0x8805); +reg_write( DDR_REG_BASE +0x52a4f*4 +0x02000000,0x833); +reg_write( DDR_REG_BASE +0x52a50*4 +0x02000000,0x8065); +reg_write( DDR_REG_BASE +0x52a51*4 +0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x52a52*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52a53*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52a54*4 +0x02000000,0x878); +reg_write( DDR_REG_BASE +0x52a55*4 +0x02000000,0xff02); +reg_write( DDR_REG_BASE +0x52a56*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x52a57*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52a58*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x52a59*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52a5a*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52a5b*4 +0x02000000,0xf535); +reg_write( DDR_REG_BASE +0x52a5c*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52a5d*4 +0x02000000,0xae); +reg_write( DDR_REG_BASE +0x52a5e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a5f*4 +0x02000000,0xd36); +reg_write( DDR_REG_BASE +0x52a60*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52a61*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x52a62*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52a63*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52a64*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x52a65*4 +0x02000000,0x88c4); +reg_write( DDR_REG_BASE +0x52a66*4 +0x02000000,0xf027); +reg_write( DDR_REG_BASE +0x52a67*4 +0x02000000,0x7ff0); +reg_write( DDR_REG_BASE +0x52a68*4 +0x02000000,0xe708); +reg_write( DDR_REG_BASE +0x52a69*4 +0x02000000,0xdd08); +reg_write( DDR_REG_BASE +0x52a6a*4 +0x02000000,0xf01f); +reg_write( DDR_REG_BASE +0x52a6b*4 +0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52a6c*4 +0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52a6d*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52a6e*4 +0x02000000,0xfffe); +reg_write( DDR_REG_BASE +0x52a6f*4 +0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52a70*4 +0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52a71*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52a72*4 +0x02000000,0x104); +reg_write( DDR_REG_BASE +0x52a73*4 +0x02000000,0x2035); +reg_write( DDR_REG_BASE +0x52a74*4 +0x02000000,0x43); +reg_write( DDR_REG_BASE +0x52a75*4 +0x02000000,0xc094); +reg_write( DDR_REG_BASE +0x52a76*4 +0x02000000,0x2035); +reg_write( DDR_REG_BASE +0x52a77*4 +0x02000000,0x42); +reg_write( DDR_REG_BASE +0x52a78*4 +0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x52a79*4 +0x02000000,0x3dc0); +reg_write( DDR_REG_BASE +0x52a7a*4 +0x02000000,0x2035); +reg_write( DDR_REG_BASE +0x52a7b*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x52a7c*4 +0x02000000,0xc241); +reg_write( DDR_REG_BASE +0x52a7d*4 +0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x52a7e*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52a7f*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x52a80*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52a81*4 +0x02000000,0xaf); +reg_write( DDR_REG_BASE +0x52a82*4 +0x02000000,0x5); +reg_write( DDR_REG_BASE +0x52a83*4 +0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x52a84*4 +0x02000000,0xcea); +reg_write( DDR_REG_BASE +0x52a85*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52a86*4 +0x02000000,0x43a1); +reg_write( DDR_REG_BASE +0x52a87*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x52a88*4 +0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x52a89*4 +0x02000000,0xdc7); +reg_write( DDR_REG_BASE +0x52a8a*4 +0x02000000,0x9274); +reg_write( DDR_REG_BASE +0x52a8b*4 +0x02000000,0x78fb); +reg_write( DDR_REG_BASE +0x52a8c*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x52a8d*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52a8e*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52a8f*4 +0x02000000,0x665); +reg_write( DDR_REG_BASE +0x52a90*4 +0x02000000,0x8805); +reg_write( DDR_REG_BASE +0x52a91*4 +0x02000000,0x79cf); +reg_write( DDR_REG_BASE +0x52a92*4 +0x02000000,0x8ab); +reg_write( DDR_REG_BASE +0x52a93*4 +0x02000000,0x8065); +reg_write( DDR_REG_BASE +0x52a94*4 +0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x52a95*4 +0x02000000,0xe46); +reg_write( DDR_REG_BASE +0x52a96*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52a97*4 +0x02000000,0xc011); +reg_write( DDR_REG_BASE +0x52a98*4 +0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52a99*4 +0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x52a9a*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52a9b*4 +0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x52a9c*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52a9d*4 +0x02000000,0x7001); +reg_write( DDR_REG_BASE +0x52a9e*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52a9f*4 +0x02000000,0x674); +reg_write( DDR_REG_BASE +0x52aa0*4 +0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x52aa1*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52aa2*4 +0x02000000,0xe1e); +reg_write( DDR_REG_BASE +0x52aa3*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x52aa4*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x52aa5*4 +0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x52aa6*4 +0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x52aa7*4 +0x02000000,0x3dc1); +reg_write( DDR_REG_BASE +0x52aa8*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52aa9*4 +0x02000000,0x90a); +reg_write( DDR_REG_BASE +0x52aaa*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52aab*4 +0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x52aac*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52aad*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52aae*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52aaf*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52ab0*4 +0x02000000,0x7314); +reg_write( DDR_REG_BASE +0x52ab1*4 +0x02000000,0x378); +reg_write( DDR_REG_BASE +0x52ab2*4 +0x02000000,0xffce); +reg_write( DDR_REG_BASE +0x52ab3*4 +0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x52ab4*4 +0x02000000,0x3511); +reg_write( DDR_REG_BASE +0x52ab5*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52ab6*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52ab7*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52ab8*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52ab9*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52aba*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52abb*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52abc*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52abd*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52abe*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52abf*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52ac0*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52ac1*4 +0x02000000,0xc1ad); +reg_write( DDR_REG_BASE +0x52ac2*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52ac3*4 +0x02000000,0x708c); +reg_write( DDR_REG_BASE +0x52ac4*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52ac5*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52ac6*4 +0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x52ac7*4 +0x02000000,0xc148); +reg_write( DDR_REG_BASE +0x52ac8*4 +0x02000000,0x241a); +reg_write( DDR_REG_BASE +0x52ac9*4 +0x02000000,0x1f8c); +reg_write( DDR_REG_BASE +0x52aca*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52acb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52acc*4 +0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x52acd*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x52ace*4 +0x02000000,0x2405); +reg_write( DDR_REG_BASE +0x52acf*4 +0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x52ad0*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52ad1*4 +0x02000000,0x90); +reg_write( DDR_REG_BASE +0x52ad2*4 +0x02000000,0x9020); +reg_write( DDR_REG_BASE +0x52ad3*4 +0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x52ad4*4 +0x02000000,0x243); +reg_write( DDR_REG_BASE +0x52ad5*4 +0x02000000,0x887a); +reg_write( DDR_REG_BASE +0x52ad6*4 +0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x52ad7*4 +0x02000000,0x800); +reg_write( DDR_REG_BASE +0x52ad8*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x52ad9*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52ada*4 +0x02000000,0x915); +reg_write( DDR_REG_BASE +0x52adb*4 +0x02000000,0x71); +reg_write( DDR_REG_BASE +0x52adc*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52add*4 +0x02000000,0x2405); +reg_write( DDR_REG_BASE +0x52ade*4 +0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x52adf*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52ae0*4 +0x02000000,0x96); +reg_write( DDR_REG_BASE +0x52ae1*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x52ae2*4 +0x02000000,0xb8c5); +reg_write( DDR_REG_BASE +0x52ae3*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52ae4*4 +0x02000000,0x224f); +reg_write( DDR_REG_BASE +0x52ae5*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x52ae6*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x52ae7*4 +0x02000000,0xba80); +reg_write( DDR_REG_BASE +0x52ae8*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52ae9*4 +0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52aea*4 +0x02000000,0xe024); +reg_write( DDR_REG_BASE +0x52aeb*4 +0x02000000,0xc249); +reg_write( DDR_REG_BASE +0x52aec*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x52aed*4 +0x02000000,0xfc5); +reg_write( DDR_REG_BASE +0x52aee*4 +0x02000000,0x180c); +reg_write( DDR_REG_BASE +0x52aef*4 +0x02000000,0xfc5); +reg_write( DDR_REG_BASE +0x52af0*4 +0x02000000,0x18fe); +reg_write( DDR_REG_BASE +0x52af1*4 +0x02000000,0x83c4); +reg_write( DDR_REG_BASE +0x52af2*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52af3*4 +0x02000000,0xf870); +reg_write( DDR_REG_BASE +0x52af4*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52af5*4 +0x02000000,0x68c9); +reg_write( DDR_REG_BASE +0x52af6*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52af7*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52af8*4 +0x02000000,0xf0bf); +reg_write( DDR_REG_BASE +0x52af9*4 +0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x52afa*4 +0x02000000,0x2011); +reg_write( DDR_REG_BASE +0x52afb*4 +0x02000000,0x83c0); +reg_write( DDR_REG_BASE +0x52afc*4 +0x02000000,0xf2ba); +reg_write( DDR_REG_BASE +0x52afd*4 +0x02000000,0x78ef); +reg_write( DDR_REG_BASE +0x52afe*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52aff*4 +0x02000000,0xdaff); +reg_write( DDR_REG_BASE +0x52b00*4 +0x02000000,0xb2e); +reg_write( DDR_REG_BASE +0x52b01*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52b02*4 +0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x52b03*4 +0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x52b04*4 +0x02000000,0xa56); +reg_write( DDR_REG_BASE +0x52b05*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x52b06*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52b07*4 +0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x52b08*4 +0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x52b09*4 +0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x52b0a*4 +0x02000000,0xdaff); +reg_write( DDR_REG_BASE +0x52b0b*4 +0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x52b0c*4 +0x02000000,0xaaa); +reg_write( DDR_REG_BASE +0x52b0d*4 +0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52b0e*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52b0f*4 +0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x52b10*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x52b11*4 +0x02000000,0xabe); +reg_write( DDR_REG_BASE +0x52b12*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x52b13*4 +0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52b14*4 +0x02000000,0x916); +reg_write( DDR_REG_BASE +0x52b15*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52b16*4 +0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x52b17*4 +0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x52b18*4 +0x02000000,0x833); +reg_write( DDR_REG_BASE +0x52b19*4 +0x02000000,0xf1); +reg_write( DDR_REG_BASE +0x52b1a*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52b1b*4 +0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x52b1c*4 +0x02000000,0x17c1); +reg_write( DDR_REG_BASE +0x52b1d*4 +0x02000000,0xe906); +reg_write( DDR_REG_BASE +0x52b1e*4 +0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x52b1f*4 +0x02000000,0x901); +reg_write( DDR_REG_BASE +0x52b20*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x52b21*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52b22*4 +0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x52b23*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x52b24*4 +0x02000000,0x200f); +reg_write( DDR_REG_BASE +0x52b25*4 +0x02000000,0x34d); +reg_write( DDR_REG_BASE +0x52b26*4 +0x02000000,0xc02); +reg_write( DDR_REG_BASE +0x52b27*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x52b28*4 +0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x52b29*4 +0x02000000,0xfae); +reg_write( DDR_REG_BASE +0x52b2a*4 +0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52b2b*4 +0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x52b2c*4 +0x02000000,0x8820); +reg_write( DDR_REG_BASE +0x52b2d*4 +0x02000000,0x7aaf); +reg_write( DDR_REG_BASE +0x52b2e*4 +0x02000000,0xb72); +reg_write( DDR_REG_BASE +0x52b2f*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52b30*4 +0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x52b31*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x52b32*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52b33*4 +0x02000000,0x669); +reg_write( DDR_REG_BASE +0x52b34*4 +0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x52b35*4 +0x02000000,0x1501); +reg_write( DDR_REG_BASE +0x52b36*4 +0x02000000,0x108b); +reg_write( DDR_REG_BASE +0x52b37*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52b38*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52b39*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52b3a*4 +0x02000000,0xb02); +reg_write( DDR_REG_BASE +0x52b3b*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52b3c*4 +0x02000000,0xda08); +reg_write( DDR_REG_BASE +0x52b3d*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52b3e*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x52b3f*4 +0x02000000,0x2340); +reg_write( DDR_REG_BASE +0x52b40*4 +0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x52b41*4 +0x02000000,0x7902); +reg_write( DDR_REG_BASE +0x52b42*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52b43*4 +0x02000000,0x7829); +reg_write( DDR_REG_BASE +0x52b44*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52b45*4 +0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x52b46*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52b47*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52b48*4 +0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x52b49*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x52b4a*4 +0x02000000,0x209f); +reg_write( DDR_REG_BASE +0x52b4b*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x52b4c*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x52b4d*4 +0x02000000,0x1a12); +reg_write( DDR_REG_BASE +0x52b4e*4 +0x02000000,0x3058); +reg_write( DDR_REG_BASE +0x52b4f*4 +0x02000000,0x1212); +reg_write( DDR_REG_BASE +0x52b50*4 +0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x52b51*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52b52*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52b53*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52b54*4 +0x02000000,0x6dc); +reg_write( DDR_REG_BASE +0x52b55*4 +0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x52b56*4 +0x02000000,0x9de); +reg_write( DDR_REG_BASE +0x52b57*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x52b58*4 +0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x52b59*4 +0x02000000,0xc20c); +reg_write( DDR_REG_BASE +0x52b5a*4 +0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x52b5b*4 +0x02000000,0xe42); +reg_write( DDR_REG_BASE +0x52b5c*4 +0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x52b5d*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52b5e*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x52b5f*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52b60*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52b61*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x52b62*4 +0x02000000,0xc10b); +reg_write( DDR_REG_BASE +0x52b63*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52b64*4 +0x02000000,0x8cb); +reg_write( DDR_REG_BASE +0x52b65*4 +0x02000000,0x8064); +reg_write( DDR_REG_BASE +0x52b66*4 +0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x52b67*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x52b68*4 +0x02000000,0x7314); +reg_write( DDR_REG_BASE +0x52b69*4 +0x02000000,0xa30); +reg_write( DDR_REG_BASE +0x52b6a*4 +0x02000000,0x61); +reg_write( DDR_REG_BASE +0x52b6b*4 +0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x52b6c*4 +0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x52b6d*4 +0x02000000,0x243); +reg_write( DDR_REG_BASE +0x52b6e*4 +0x02000000,0x887a); +reg_write( DDR_REG_BASE +0x52b6f*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x52b70*4 +0x02000000,0x88d); +reg_write( DDR_REG_BASE +0x52b71*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52b72*4 +0x02000000,0xb89); +reg_write( DDR_REG_BASE +0x52b73*4 +0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x52b74*4 +0x02000000,0x8d01); +reg_write( DDR_REG_BASE +0x52b75*4 +0x02000000,0x8d20); +reg_write( DDR_REG_BASE +0x52b76*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52b77*4 +0x02000000,0x4831); +reg_write( DDR_REG_BASE +0x52b78*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52b79*4 +0x02000000,0x7829); +reg_write( DDR_REG_BASE +0x52b7a*4 +0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x52b7b*4 +0x02000000,0xf037); +reg_write( DDR_REG_BASE +0x52b7c*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52b7d*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52b7e*4 +0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x52b7f*4 +0x02000000,0x209f); +reg_write( DDR_REG_BASE +0x52b80*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x52b81*4 +0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x52b82*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52b83*4 +0x02000000,0x6dc); +reg_write( DDR_REG_BASE +0x52b84*4 +0x02000000,0x78b4); +reg_write( DDR_REG_BASE +0x52b85*4 +0x02000000,0x608c); +reg_write( DDR_REG_BASE +0x52b86*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52b87*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52b88*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52b89*4 +0x02000000,0x6dc); +reg_write( DDR_REG_BASE +0x52b8a*4 +0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x52b8b*4 +0x02000000,0xc0b); +reg_write( DDR_REG_BASE +0x52b8c*4 +0x02000000,0x1025); +reg_write( DDR_REG_BASE +0x52b8d*4 +0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x52b8e*4 +0x02000000,0x4892); +reg_write( DDR_REG_BASE +0x52b8f*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x52b90*4 +0x02000000,0xddf); +reg_write( DDR_REG_BASE +0x52b91*4 +0x02000000,0x97f4); +reg_write( DDR_REG_BASE +0x52b92*4 +0x02000000,0x4061); +reg_write( DDR_REG_BASE +0x52b93*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52b94*4 +0x02000000,0xe886); +reg_write( DDR_REG_BASE +0x52b95*4 +0x02000000,0x7650); +reg_write( DDR_REG_BASE +0x52b96*4 +0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x52b97*4 +0x02000000,0x385); +reg_write( DDR_REG_BASE +0x52b98*4 +0x02000000,0x4648); +reg_write( DDR_REG_BASE +0x52b99*4 +0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x52b9a*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52b9b*4 +0x02000000,0x225a); +reg_write( DDR_REG_BASE +0x52b9c*4 +0x02000000,0x402); +reg_write( DDR_REG_BASE +0x52b9d*4 +0x02000000,0x7c10); +reg_write( DDR_REG_BASE +0x52b9e*4 +0x02000000,0x265a); +reg_write( DDR_REG_BASE +0x52b9f*4 +0x02000000,0x1400); +reg_write( DDR_REG_BASE +0x52ba0*4 +0x02000000,0x2805); +reg_write( DDR_REG_BASE +0x52ba1*4 +0x02000000,0x300); +reg_write( DDR_REG_BASE +0x52ba2*4 +0x02000000,0xf818); +reg_write( DDR_REG_BASE +0x52ba3*4 +0x02000000,0x4e10); +reg_write( DDR_REG_BASE +0x52ba4*4 +0x02000000,0x2a05); +reg_write( DDR_REG_BASE +0x52ba5*4 +0x02000000,0x30e); +reg_write( DDR_REG_BASE +0x52ba6*4 +0x02000000,0x7edd); +reg_write( DDR_REG_BASE +0x52ba7*4 +0x02000000,0x7edd); +reg_write( DDR_REG_BASE +0x52ba8*4 +0x02000000,0x7edd); +reg_write( DDR_REG_BASE +0x52ba9*4 +0x02000000,0x7edd); +reg_write( DDR_REG_BASE +0x52baa*4 +0x02000000,0x661e); +reg_write( DDR_REG_BASE +0x52bab*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52bac*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52bad*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52bae*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52baf*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52bb0*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52bb1*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52bb2*4 +0x02000000,0x7a0f); +reg_write( DDR_REG_BASE +0x52bb3*4 +0x02000000,0xa95); +reg_write( DDR_REG_BASE +0x52bb4*4 +0x02000000,0x8064); +reg_write( DDR_REG_BASE +0x52bb5*4 +0x02000000,0x4348); +reg_write( DDR_REG_BASE +0x52bb6*4 +0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x52bb7*4 +0x02000000,0x72f5); +reg_write( DDR_REG_BASE +0x52bb8*4 +0x02000000,0x682); +reg_write( DDR_REG_BASE +0x52bb9*4 +0x02000000,0xffc5); +reg_write( DDR_REG_BASE +0x52bba*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x52bbb*4 +0x02000000,0xe814); +reg_write( DDR_REG_BASE +0x52bbc*4 +0x02000000,0xb25); +reg_write( DDR_REG_BASE +0x52bbd*4 +0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x52bbe*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x52bbf*4 +0x02000000,0x8040); +reg_write( DDR_REG_BASE +0x52bc0*4 +0x02000000,0xa1d); +reg_write( DDR_REG_BASE +0x52bc1*4 +0x02000000,0x3a5); +reg_write( DDR_REG_BASE +0x52bc2*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x52bc3*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52bc4*4 +0x02000000,0x8d); +reg_write( DDR_REG_BASE +0x52bc5*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x52bc6*4 +0x02000000,0xa66); +reg_write( DDR_REG_BASE +0x52bc7*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52bc8*4 +0x02000000,0x43c1); +reg_write( DDR_REG_BASE +0x52bc9*4 +0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x52bca*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52bcb*4 +0x02000000,0xa904); +reg_write( DDR_REG_BASE +0x52bcc*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x52bcd*4 +0x02000000,0xa0c0); +reg_write( DDR_REG_BASE +0x52bce*4 +0x02000000,0xc0ad); +reg_write( DDR_REG_BASE +0x52bcf*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52bd0*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52bd1*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52bd2*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52bd3*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52bd4*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52bd5*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52bd6*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52bd7*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52bd8*4 +0x02000000,0xc0e4); +reg_write( DDR_REG_BASE +0x52bd9*4 +0x02000000,0xf029); +reg_write( DDR_REG_BASE +0x52bda*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x52bdb*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52bdc*4 +0x02000000,0x71b); +reg_write( DDR_REG_BASE +0x52bdd*4 +0x02000000,0xe910); +reg_write( DDR_REG_BASE +0x52bde*4 +0x02000000,0x93b); +reg_write( DDR_REG_BASE +0x52bdf*4 +0x02000000,0x70); +reg_write( DDR_REG_BASE +0x52be0*4 +0x02000000,0x4448); +reg_write( DDR_REG_BASE +0x52be1*4 +0x02000000,0x941); +reg_write( DDR_REG_BASE +0x52be2*4 +0x02000000,0xb1); +reg_write( DDR_REG_BASE +0x52be3*4 +0x02000000,0x4448); +reg_write( DDR_REG_BASE +0x52be4*4 +0x02000000,0x249a); +reg_write( DDR_REG_BASE +0x52be5*4 +0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x52be6*4 +0x02000000,0x659d); +reg_write( DDR_REG_BASE +0x52be7*4 +0x02000000,0x8dc0); +reg_write( DDR_REG_BASE +0x52be8*4 +0x02000000,0x8881); +reg_write( DDR_REG_BASE +0x52be9*4 +0x02000000,0x64dc); +reg_write( DDR_REG_BASE +0x52bea*4 +0x02000000,0xad80); +reg_write( DDR_REG_BASE +0x52beb*4 +0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x52bec*4 +0x02000000,0x4448); +reg_write( DDR_REG_BASE +0x52bed*4 +0x02000000,0x249a); +reg_write( DDR_REG_BASE +0x52bee*4 +0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x52bef*4 +0x02000000,0x64be); +reg_write( DDR_REG_BASE +0x52bf0*4 +0x02000000,0x8ea0); +reg_write( DDR_REG_BASE +0x52bf1*4 +0x02000000,0x8881); +reg_write( DDR_REG_BASE +0x52bf2*4 +0x02000000,0x64bc); +reg_write( DDR_REG_BASE +0x52bf3*4 +0x02000000,0xae80); +reg_write( DDR_REG_BASE +0x52bf4*4 +0x02000000,0x8882); +reg_write( DDR_REG_BASE +0x52bf5*4 +0x02000000,0x2452); +reg_write( DDR_REG_BASE +0x52bf6*4 +0x02000000,0x11cd); +reg_write( DDR_REG_BASE +0x52bf7*4 +0x02000000,0x8e81); +reg_write( DDR_REG_BASE +0x52bf8*4 +0x02000000,0x64bc); +reg_write( DDR_REG_BASE +0x52bf9*4 +0x02000000,0xae81); +reg_write( DDR_REG_BASE +0x52bfa*4 +0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x52bfb*4 +0x02000000,0x249a); +reg_write( DDR_REG_BASE +0x52bfc*4 +0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x52bfd*4 +0x02000000,0x64bc); +reg_write( DDR_REG_BASE +0x52bfe*4 +0x02000000,0x88a2); +reg_write( DDR_REG_BASE +0x52bff*4 +0x02000000,0xaca1); +reg_write( DDR_REG_BASE +0x52c00*4 +0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x52c01*4 +0x02000000,0xab5); +reg_write( DDR_REG_BASE +0x52c02*4 +0x02000000,0x80c4); +reg_write( DDR_REG_BASE +0x52c03*4 +0x02000000,0xc4c4); +reg_write( DDR_REG_BASE +0x52c04*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52c05*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52c06*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52c07*4 +0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x52c08*4 +0x02000000,0x3080); +reg_write( DDR_REG_BASE +0x52c09*4 +0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x52c0a*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52c0b*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52c0c*4 +0x02000000,0x669); +reg_write( DDR_REG_BASE +0x52c0d*4 +0x02000000,0x4738); +reg_write( DDR_REG_BASE +0x52c0e*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x52c0f*4 +0x02000000,0x8b); +reg_write( DDR_REG_BASE +0x52c10*4 +0x02000000,0x8820); +reg_write( DDR_REG_BASE +0x52c11*4 +0x02000000,0xf02a); +reg_write( DDR_REG_BASE +0x52c12*4 +0x02000000,0xe49); +reg_write( DDR_REG_BASE +0x52c13*4 +0x02000000,0x332e); +reg_write( DDR_REG_BASE +0x52c14*4 +0x02000000,0x4789); +reg_write( DDR_REG_BASE +0x52c15*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x52c16*4 +0x02000000,0x243); +reg_write( DDR_REG_BASE +0x52c17*4 +0x02000000,0x279a); +reg_write( DDR_REG_BASE +0x52c18*4 +0x02000000,0x1008); +reg_write( DDR_REG_BASE +0x52c19*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x52c1a*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52c1b*4 +0x02000000,0x80); +reg_write( DDR_REG_BASE +0x52c1c*4 +0x02000000,0x73e3); +reg_write( DDR_REG_BASE +0x52c1d*4 +0x02000000,0x2333); +reg_write( DDR_REG_BASE +0x52c1e*4 +0x02000000,0x30e); +reg_write( DDR_REG_BASE +0x52c1f*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x52c20*4 +0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x52c21*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52c22*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52c23*4 +0x02000000,0x665e); +reg_write( DDR_REG_BASE +0x52c24*4 +0x02000000,0x2642); +reg_write( DDR_REG_BASE +0x52c25*4 +0x02000000,0x905b); +reg_write( DDR_REG_BASE +0x52c26*4 +0x02000000,0x7f65); +reg_write( DDR_REG_BASE +0x52c27*4 +0x02000000,0x2705); +reg_write( DDR_REG_BASE +0x52c28*4 +0x02000000,0x1343); +reg_write( DDR_REG_BASE +0x52c29*4 +0x02000000,0xb340); +reg_write( DDR_REG_BASE +0x52c2a*4 +0x02000000,0xdb7f); +reg_write( DDR_REG_BASE +0x52c2b*4 +0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x52c2c*4 +0x02000000,0x2b); +reg_write( DDR_REG_BASE +0x52c2d*4 +0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x52c2e*4 +0x02000000,0xbf41); +reg_write( DDR_REG_BASE +0x52c2f*4 +0x02000000,0x26ca); +reg_write( DDR_REG_BASE +0x52c30*4 +0x02000000,0x10cd); +reg_write( DDR_REG_BASE +0x52c31*4 +0x02000000,0x2542); +reg_write( DDR_REG_BASE +0x52c32*4 +0x02000000,0x180d); +reg_write( DDR_REG_BASE +0x52c33*4 +0x02000000,0x7bcf); +reg_write( DDR_REG_BASE +0x52c34*4 +0x02000000,0x7fa5); +reg_write( DDR_REG_BASE +0x52c35*4 +0x02000000,0xb760); +reg_write( DDR_REG_BASE +0x52c36*4 +0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x52c37*4 +0x02000000,0xcb9); +reg_write( DDR_REG_BASE +0x52c38*4 +0x02000000,0x9254); +reg_write( DDR_REG_BASE +0x52c39*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x52c3a*4 +0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x52c3b*4 +0x02000000,0xbfb); +reg_write( DDR_REG_BASE +0x52c3c*4 +0x02000000,0x9025); +reg_write( DDR_REG_BASE +0x52c3d*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x52c3e*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52c3f*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52c40*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52c41*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52c42*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52c43*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52c44*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52c45*4 +0x02000000,0xc1a8); +reg_write( DDR_REG_BASE +0x52c46*4 +0x02000000,0xc145); +reg_write( DDR_REG_BASE +0x52c47*4 +0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x52c48*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52c49*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x52c4a*4 +0x02000000,0xc346); +reg_write( DDR_REG_BASE +0x52c4b*4 +0x02000000,0xb7a); +reg_write( DDR_REG_BASE +0x52c4c*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52c4d*4 +0x02000000,0xc244); +reg_write( DDR_REG_BASE +0x52c4e*4 +0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x52c4f*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x52c50*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52c51*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x52c52*4 +0x02000000,0xf03a); +reg_write( DDR_REG_BASE +0x52c53*4 +0x02000000,0x2532); +reg_write( DDR_REG_BASE +0x52c54*4 +0x02000000,0x1f8f); +reg_write( DDR_REG_BASE +0x52c55*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52c56*4 +0x02000000,0x524); +reg_write( DDR_REG_BASE +0x52c57*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52c58*4 +0x02000000,0x93e); +reg_write( DDR_REG_BASE +0x52c59*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52c5a*4 +0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x52c5b*4 +0x02000000,0xc207); +reg_write( DDR_REG_BASE +0x52c5c*4 +0x02000000,0x7944); +reg_write( DDR_REG_BASE +0x52c5d*4 +0x02000000,0xc206); +reg_write( DDR_REG_BASE +0x52c5e*4 +0x02000000,0x7844); +reg_write( DDR_REG_BASE +0x52c5f*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52c60*4 +0x02000000,0x807e); +reg_write( DDR_REG_BASE +0x52c61*4 +0x02000000,0xf42b); +reg_write( DDR_REG_BASE +0x52c62*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52c63*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52c64*4 +0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x52c65*4 +0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x52c66*4 +0x02000000,0x60e8); +reg_write( DDR_REG_BASE +0x52c67*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x52c68*4 +0x02000000,0x3001); +reg_write( DDR_REG_BASE +0x52c69*4 +0x02000000,0x1c08); +reg_write( DDR_REG_BASE +0x52c6a*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52c6b*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52c6c*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52c6d*4 +0x02000000,0xe3a); +reg_write( DDR_REG_BASE +0x52c6e*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52c6f*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x52c70*4 +0x02000000,0xd07); +reg_write( DDR_REG_BASE +0x52c71*4 +0x02000000,0x1190); +reg_write( DDR_REG_BASE +0x52c72*4 +0x02000000,0xed99); +reg_write( DDR_REG_BASE +0x52c73*4 +0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x52c74*4 +0x02000000,0xd9c8); +reg_write( DDR_REG_BASE +0x52c75*4 +0x02000000,0xd8fa); +reg_write( DDR_REG_BASE +0x52c76*4 +0x02000000,0xc6a); +reg_write( DDR_REG_BASE +0x52c77*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x52c78*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x52c79*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x52c7a*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52c7b*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52c7c*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52c7d*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52c7e*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52c7f*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52c80*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52c81*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52c82*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52c83*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52c84*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52c85*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52c86*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52c87*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52c88*4 +0x02000000,0xe02); +reg_write( DDR_REG_BASE +0x52c89*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52c8a*4 +0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x52c8b*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x52c8c*4 +0x02000000,0xd8f); +reg_write( DDR_REG_BASE +0x52c8d*4 +0x02000000,0x9334); +reg_write( DDR_REG_BASE +0x52c8e*4 +0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52c8f*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52c90*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52c91*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52c92*4 +0x02000000,0xdb41); +reg_write( DDR_REG_BASE +0x52c93*4 +0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x52c94*4 +0x02000000,0x3401); +reg_write( DDR_REG_BASE +0x52c95*4 +0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x52c96*4 +0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x52c97*4 +0x02000000,0xbd6); +reg_write( DDR_REG_BASE +0x52c98*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52c99*4 +0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x52c9a*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52c9b*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x52c9c*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52c9d*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52c9e*4 +0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x52c9f*4 +0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x52ca0*4 +0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x52ca1*4 +0x02000000,0xbc2); +reg_write( DDR_REG_BASE +0x52ca2*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52ca3*4 +0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x52ca4*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52ca5*4 +0x02000000,0xb5e); +reg_write( DDR_REG_BASE +0x52ca6*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52ca7*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52ca8*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52ca9*4 +0x02000000,0xe833); +reg_write( DDR_REG_BASE +0x52caa*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52cab*4 +0x02000000,0xaba); +reg_write( DDR_REG_BASE +0x52cac*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52cad*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x52cae*4 +0x02000000,0xd84f); +reg_write( DDR_REG_BASE +0x52caf*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52cb0*4 +0x02000000,0x2353); +reg_write( DDR_REG_BASE +0x52cb1*4 +0x02000000,0x305b); +reg_write( DDR_REG_BASE +0x52cb2*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52cb3*4 +0x02000000,0xf817); +reg_write( DDR_REG_BASE +0x52cb4*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52cb5*4 +0x02000000,0x1c08); +reg_write( DDR_REG_BASE +0x52cb6*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52cb7*4 +0x02000000,0xb96); +reg_write( DDR_REG_BASE +0x52cb8*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52cb9*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52cba*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52cbb*4 +0x02000000,0xb32); +reg_write( DDR_REG_BASE +0x52cbc*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52cbd*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52cbe*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52cbf*4 +0x02000000,0xf); +reg_write( DDR_REG_BASE +0x52cc0*4 +0x02000000,0x4240); +reg_write( DDR_REG_BASE +0x52cc1*4 +0x02000000,0xad2); +reg_write( DDR_REG_BASE +0x52cc2*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52cc3*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52cc4*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52cc5*4 +0x02000000,0xa86); +reg_write( DDR_REG_BASE +0x52cc6*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52cc7*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x52cc8*4 +0x02000000,0xd851); +reg_write( DDR_REG_BASE +0x52cc9*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52cca*4 +0x02000000,0xf80b); +reg_write( DDR_REG_BASE +0x52ccb*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52ccc*4 +0x02000000,0x1c08); +reg_write( DDR_REG_BASE +0x52ccd*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52cce*4 +0x02000000,0xb66); +reg_write( DDR_REG_BASE +0x52ccf*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52cd0*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52cd1*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52cd2*4 +0x02000000,0xb02); +reg_write( DDR_REG_BASE +0x52cd3*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52cd4*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52cd5*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52cd6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52cd7*4 +0x02000000,0x1f40); +reg_write( DDR_REG_BASE +0x52cd8*4 +0x02000000,0xaa2); +reg_write( DDR_REG_BASE +0x52cd9*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52cda*4 +0x02000000,0xd91e); +reg_write( DDR_REG_BASE +0x52cdb*4 +0x02000000,0xc0a8); +reg_write( DDR_REG_BASE +0x52cdc*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52cdd*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52cde*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52cdf*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52ce0*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52ce1*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x52ce2*4 +0x02000000,0xda17); +reg_write( DDR_REG_BASE +0x52ce3*4 +0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52ce4*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52ce5*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52ce6*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52ce7*4 +0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x52ce8*4 +0x02000000,0x4628); +reg_write( DDR_REG_BASE +0x52ce9*4 +0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x52cea*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52ceb*4 +0x02000000,0xa3a); +reg_write( DDR_REG_BASE +0x52cec*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52ced*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x52cee*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52cef*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52cf0*4 +0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x52cf1*4 +0x02000000,0xdb22); +reg_write( DDR_REG_BASE +0x52cf2*4 +0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x52cf3*4 +0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x52cf4*4 +0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52cf5*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x52cf6*4 +0x02000000,0x3381); +reg_write( DDR_REG_BASE +0x52cf7*4 +0x02000000,0xd26); +reg_write( DDR_REG_BASE +0x52cf8*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52cf9*4 +0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x52cfa*4 +0x02000000,0xb62); +reg_write( DDR_REG_BASE +0x52cfb*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x52cfc*4 +0x02000000,0xd8fa); +reg_write( DDR_REG_BASE +0x52cfd*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52cfe*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52cff*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52d00*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52d01*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52d02*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52d03*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52d04*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52d05*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52d06*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52d07*4 +0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x52d08*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52d09*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52d0a*4 +0x02000000,0xcfe); +reg_write( DDR_REG_BASE +0x52d0b*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52d0c*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52d0d*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52d0e*4 +0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x52d0f*4 +0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52d10*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x52d11*4 +0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52d12*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52d13*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52d14*4 +0x02000000,0xada); +reg_write( DDR_REG_BASE +0x52d15*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52d16*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52d17*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52d18*4 +0x02000000,0xa76); +reg_write( DDR_REG_BASE +0x52d19*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52d1a*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52d1b*4 +0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x52d1c*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52d1d*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52d1e*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52d1f*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52d20*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52d21*4 +0x02000000,0xc1ac); +reg_write( DDR_REG_BASE +0x52d22*4 +0x02000000,0xc349); +reg_write( DDR_REG_BASE +0x52d23*4 +0x02000000,0xc247); +reg_write( DDR_REG_BASE +0x52d24*4 +0x02000000,0xc14a); +reg_write( DDR_REG_BASE +0x52d25*4 +0x02000000,0xd42); +reg_write( DDR_REG_BASE +0x52d26*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52d27*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x52d28*4 +0x02000000,0xc011); +reg_write( DDR_REG_BASE +0x52d29*4 +0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x52d2a*4 +0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x52d2b*4 +0x02000000,0xc012); +reg_write( DDR_REG_BASE +0x52d2c*4 +0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x52d2d*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52d2e*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52d2f*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52d30*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52d31*4 +0x02000000,0xf0b8); +reg_write( DDR_REG_BASE +0x52d32*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52d33*4 +0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x52d34*4 +0x02000000,0xf9b); +reg_write( DDR_REG_BASE +0x52d35*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52d36*4 +0x02000000,0x524); +reg_write( DDR_REG_BASE +0x52d37*4 +0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x52d38*4 +0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x52d39*4 +0x02000000,0x6ce); +reg_write( DDR_REG_BASE +0x52d3a*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52d3b*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52d3c*4 +0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x52d3d*4 +0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x52d3e*4 +0x02000000,0xf40b); +reg_write( DDR_REG_BASE +0x52d3f*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52d40*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52d41*4 +0x02000000,0xa00); +reg_write( DDR_REG_BASE +0x52d42*4 +0x02000000,0x98a); +reg_write( DDR_REG_BASE +0x52d43*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52d44*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x52d45*4 +0x02000000,0xd4e); +reg_write( DDR_REG_BASE +0x52d46*4 +0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x52d47*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52d48*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52d49*4 +0x02000000,0x41e1); +reg_write( DDR_REG_BASE +0x52d4a*4 +0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x52d4b*4 +0x02000000,0x37c0); +reg_write( DDR_REG_BASE +0x52d4c*4 +0x02000000,0xc209); +reg_write( DDR_REG_BASE +0x52d4d*4 +0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x52d4e*4 +0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x52d4f*4 +0x02000000,0x801); +reg_write( DDR_REG_BASE +0x52d50*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x52d51*4 +0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x52d52*4 +0x02000000,0xd81f); +reg_write( DDR_REG_BASE +0x52d53*4 +0x02000000,0x7a24); +reg_write( DDR_REG_BASE +0x52d54*4 +0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x52d55*4 +0x02000000,0x801); +reg_write( DDR_REG_BASE +0x52d56*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x52d57*4 +0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x52d58*4 +0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x52d59*4 +0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x52d5a*4 +0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x52d5b*4 +0x02000000,0x803e); +reg_write( DDR_REG_BASE +0x52d5c*4 +0x02000000,0xf479); +reg_write( DDR_REG_BASE +0x52d5d*4 +0x02000000,0x78dd); +reg_write( DDR_REG_BASE +0x52d5e*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52d5f*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x52d60*4 +0x02000000,0x800); +reg_write( DDR_REG_BASE +0x52d61*4 +0x02000000,0x2045); +reg_write( DDR_REG_BASE +0x52d62*4 +0x02000000,0x18d); +reg_write( DDR_REG_BASE +0x52d63*4 +0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x52d64*4 +0x02000000,0xe80b); +reg_write( DDR_REG_BASE +0x52d65*4 +0x02000000,0xf87e); +reg_write( DDR_REG_BASE +0x52d66*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52d67*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52d68*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52d69*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52d6a*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52d6b*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52d6c*4 +0x02000000,0xa2a); +reg_write( DDR_REG_BASE +0x52d6d*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52d6e*4 +0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x52d6f*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52d70*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52d71*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52d72*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52d73*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52d74*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52d75*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52d76*4 +0x02000000,0x57c); +reg_write( DDR_REG_BASE +0x52d77*4 +0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x52d78*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x52d79*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x52d7a*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52d7b*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52d7c*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52d7d*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52d7e*4 +0x02000000,0xa06); +reg_write( DDR_REG_BASE +0x52d7f*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52d80*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52d81*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52d82*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52d83*4 +0x02000000,0x57c); +reg_write( DDR_REG_BASE +0x52d84*4 +0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x52d85*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52d86*4 +0x02000000,0x2353); +reg_write( DDR_REG_BASE +0x52d87*4 +0x02000000,0x315b); +reg_write( DDR_REG_BASE +0x52d88*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52d89*4 +0x02000000,0xf869); +reg_write( DDR_REG_BASE +0x52d8a*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52d8b*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x52d8c*4 +0x02000000,0x9ea); +reg_write( DDR_REG_BASE +0x52d8d*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52d8e*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x52d8f*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52d90*4 +0x02000000,0xf868); +reg_write( DDR_REG_BASE +0x52d91*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52d92*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52d93*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x52d94*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x52d95*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52d96*4 +0x02000000,0x78dd); +reg_write( DDR_REG_BASE +0x52d97*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x52d98*4 +0x02000000,0x800); +reg_write( DDR_REG_BASE +0x52d99*4 +0x02000000,0x2045); +reg_write( DDR_REG_BASE +0x52d9a*4 +0x02000000,0x580); +reg_write( DDR_REG_BASE +0x52d9b*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52d9c*4 +0x02000000,0x9ca); +reg_write( DDR_REG_BASE +0x52d9d*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52d9e*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52d9f*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52da0*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52da1*4 +0x02000000,0x57c); +reg_write( DDR_REG_BASE +0x52da2*4 +0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x52da3*4 +0x02000000,0xbec5); +reg_write( DDR_REG_BASE +0x52da4*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52da5*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52da6*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52da7*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52da8*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x52da9*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52daa*4 +0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x52dab*4 +0x02000000,0x9ae); +reg_write( DDR_REG_BASE +0x52dac*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52dad*4 +0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x52dae*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52daf*4 +0x02000000,0xe819); +reg_write( DDR_REG_BASE +0x52db0*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52db1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52db2*4 +0x02000000,0x2710); +reg_write( DDR_REG_BASE +0x52db3*4 +0x02000000,0x90e); +reg_write( DDR_REG_BASE +0x52db4*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52db5*4 +0x02000000,0xd90a); +reg_write( DDR_REG_BASE +0x52db6*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52db7*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52db8*4 +0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x52db9*4 +0x02000000,0x7e0f); +reg_write( DDR_REG_BASE +0x52dba*4 +0x02000000,0xf850); +reg_write( DDR_REG_BASE +0x52dbb*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52dbc*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52dbd*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52dbe*4 +0x02000000,0x986); +reg_write( DDR_REG_BASE +0x52dbf*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52dc0*4 +0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x52dc1*4 +0x02000000,0xf84d); +reg_write( DDR_REG_BASE +0x52dc2*4 +0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x52dc3*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52dc4*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52dc5*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52dc6*4 +0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x52dc7*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52dc8*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52dc9*4 +0x02000000,0x57c); +reg_write( DDR_REG_BASE +0x52dca*4 +0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x52dcb*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52dcc*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52dcd*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52dce*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52dcf*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52dd0*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52dd1*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52dd2*4 +0x02000000,0xdb18); +reg_write( DDR_REG_BASE +0x52dd3*4 +0x02000000,0x95e); +reg_write( DDR_REG_BASE +0x52dd4*4 +0x02000000,0xfd4f); +reg_write( DDR_REG_BASE +0x52dd5*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52dd6*4 +0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x52dd7*4 +0x02000000,0x90f); +reg_write( DDR_REG_BASE +0x52dd8*4 +0x02000000,0x110); +reg_write( DDR_REG_BASE +0x52dd9*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52dda*4 +0x02000000,0x817); +reg_write( DDR_REG_BASE +0x52ddb*4 +0x02000000,0x2d1); +reg_write( DDR_REG_BASE +0x52ddc*4 +0x02000000,0xe909); +reg_write( DDR_REG_BASE +0x52ddd*4 +0x02000000,0xbc6); +reg_write( DDR_REG_BASE +0x52dde*4 +0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x52ddf*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52de0*4 +0x02000000,0x8e6); +reg_write( DDR_REG_BASE +0x52de1*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52de2*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52de3*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52de4*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52de5*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52de6*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52de7*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52de8*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52de9*4 +0x02000000,0xe08c); +reg_write( DDR_REG_BASE +0x52dea*4 +0x02000000,0x690); +reg_write( DDR_REG_BASE +0x52deb*4 +0x02000000,0xffc5); +reg_write( DDR_REG_BASE +0x52dec*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x52ded*4 +0x02000000,0x8cf); +reg_write( DDR_REG_BASE +0x52dee*4 +0x02000000,0x30); +reg_write( DDR_REG_BASE +0x52def*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x52df0*4 +0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x52df1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52df2*4 +0x02000000,0xa00); +reg_write( DDR_REG_BASE +0x52df3*4 +0x02000000,0x82a); +reg_write( DDR_REG_BASE +0x52df4*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52df5*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x52df6*4 +0x02000000,0xbea); +reg_write( DDR_REG_BASE +0x52df7*4 +0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x52df8*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x52df9*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52dfa*4 +0x02000000,0x57d); +reg_write( DDR_REG_BASE +0x52dfb*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x52dfc*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52dfd*4 +0x02000000,0x234a); +reg_write( DDR_REG_BASE +0x52dfe*4 +0x02000000,0x3800); +reg_write( DDR_REG_BASE +0x52dff*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52e00*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52e01*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52e02*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x52e03*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52e04*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52e05*4 +0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x52e06*4 +0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x52e07*4 +0x02000000,0x8f6); +reg_write( DDR_REG_BASE +0x52e08*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52e09*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x52e0a*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52e0b*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x52e0c*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52e0d*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52e0e*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52e0f*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52e10*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x52e11*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52e12*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52e13*4 +0x02000000,0x8de); +reg_write( DDR_REG_BASE +0x52e14*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52e15*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x52e16*4 +0x02000000,0x33c1); +reg_write( DDR_REG_BASE +0x52e17*4 +0x02000000,0xb52); +reg_write( DDR_REG_BASE +0x52e18*4 +0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x52e19*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52e1a*4 +0x02000000,0x872); +reg_write( DDR_REG_BASE +0x52e1b*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52e1c*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52e1d*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52e1e*4 +0x02000000,0xf); +reg_write( DDR_REG_BASE +0x52e1f*4 +0x02000000,0x4240); +reg_write( DDR_REG_BASE +0x52e20*4 +0x02000000,0x812); +reg_write( DDR_REG_BASE +0x52e21*4 +0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52e22*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52e23*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x52e24*4 +0x02000000,0xfc6); +reg_write( DDR_REG_BASE +0x52e25*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x52e26*4 +0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x52e27*4 +0x02000000,0xb8a); +reg_write( DDR_REG_BASE +0x52e28*4 +0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x52e29*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x52e2a*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52e2b*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52e2c*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52e2d*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52e2e*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x52e2f*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52e30*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52e31*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52e32*4 +0x02000000,0x89e); +reg_write( DDR_REG_BASE +0x52e33*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52e34*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x52e35*4 +0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52e36*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x52e37*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52e38*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52e39*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52e3a*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52e3b*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x52e3c*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52e3d*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52e3e*4 +0x02000000,0x886); +reg_write( DDR_REG_BASE +0x52e3f*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52e40*4 +0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x52e41*4 +0x02000000,0x3441); +reg_write( DDR_REG_BASE +0x52e42*4 +0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x52e43*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52e44*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52e45*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52e46*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52e47*4 +0x02000000,0xdb10); +reg_write( DDR_REG_BASE +0x52e48*4 +0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52e49*4 +0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52e4a*4 +0x02000000,0x86e); +reg_write( DDR_REG_BASE +0x52e4b*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52e4c*4 +0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52e4d*4 +0x02000000,0xae6); +reg_write( DDR_REG_BASE +0x52e4e*4 +0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x52e4f*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52e50*4 +0x02000000,0x806); +reg_write( DDR_REG_BASE +0x52e51*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52e52*4 +0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52e53*4 +0x02000000,0xc22); +reg_write( DDR_REG_BASE +0x52e54*4 +0x02000000,0xfd8f); +reg_write( DDR_REG_BASE +0x52e55*4 +0x02000000,0xc0ac); +reg_write( DDR_REG_BASE +0x52e56*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52e57*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52e58*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52e59*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52e5a*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52e5b*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52e5c*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52e5d*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x52e5e*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52e5f*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52e60*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52e61*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52e62*4 +0x02000000,0x57c); +reg_write( DDR_REG_BASE +0x52e63*4 +0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x52e64*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52e65*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52e66*4 +0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52e67*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52e68*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52e69*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52e6a*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52e6b*4 +0x02000000,0xc1a9); +reg_write( DDR_REG_BASE +0x52e6c*4 +0x02000000,0xc145); +reg_write( DDR_REG_BASE +0x52e6d*4 +0x02000000,0xd958); +reg_write( DDR_REG_BASE +0x52e6e*4 +0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x52e6f*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x52e70*4 +0x02000000,0x8900); +reg_write( DDR_REG_BASE +0x52e71*4 +0x02000000,0x11cd); +reg_write( DDR_REG_BASE +0x52e72*4 +0x02000000,0x808f); +reg_write( DDR_REG_BASE +0x52e73*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52e74*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x52e75*4 +0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x52e76*4 +0x02000000,0x71cd); +reg_write( DDR_REG_BASE +0x52e77*4 +0x02000000,0xc343); +reg_write( DDR_REG_BASE +0x52e78*4 +0x02000000,0xc244); +reg_write( DDR_REG_BASE +0x52e79*4 +0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x52e7a*4 +0x02000000,0xf058); +reg_write( DDR_REG_BASE +0x52e7b*4 +0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x52e7c*4 +0x02000000,0x17c1); +reg_write( DDR_REG_BASE +0x52e7d*4 +0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x52e7e*4 +0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x52e7f*4 +0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x52e80*4 +0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x52e81*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x52e82*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52e83*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52e84*4 +0x02000000,0xf04b); +reg_write( DDR_REG_BASE +0x52e85*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x52e86*4 +0x02000000,0xc202); +reg_write( DDR_REG_BASE +0x52e87*4 +0x02000000,0xc108); +reg_write( DDR_REG_BASE +0x52e88*4 +0x02000000,0x7077); +reg_write( DDR_REG_BASE +0x52e89*4 +0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x52e8a*4 +0x02000000,0x3c1); +reg_write( DDR_REG_BASE +0x52e8b*4 +0x02000000,0x7944); +reg_write( DDR_REG_BASE +0x52e8c*4 +0x02000000,0x790b); +reg_write( DDR_REG_BASE +0x52e8d*4 +0x02000000,0xf242); +reg_write( DDR_REG_BASE +0x52e8e*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52e8f*4 +0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x52e90*4 +0x02000000,0x37c1); +reg_write( DDR_REG_BASE +0x52e91*4 +0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x52e92*4 +0x02000000,0x3007); +reg_write( DDR_REG_BASE +0x52e93*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52e94*4 +0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x52e95*4 +0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x52e96*4 +0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x52e97*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x52e98*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52e99*4 +0x02000000,0x98a); +reg_write( DDR_REG_BASE +0x52e9a*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52e9b*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52e9c*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52e9d*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52e9e*4 +0x02000000,0x57c); +reg_write( DDR_REG_BASE +0x52e9f*4 +0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x52ea0*4 +0x02000000,0xe81c); +reg_write( DDR_REG_BASE +0x52ea1*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52ea2*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x52ea3*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52ea4*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52ea5*4 +0x02000000,0x831); +reg_write( DDR_REG_BASE +0x52ea6*4 +0x02000000,0xdf); +reg_write( DDR_REG_BASE +0x52ea7*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52ea8*4 +0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x52ea9*4 +0x02000000,0x3c81); +reg_write( DDR_REG_BASE +0x52eaa*4 +0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x52eab*4 +0x02000000,0x3102); +reg_write( DDR_REG_BASE +0x52eac*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52ead*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52eae*4 +0x02000000,0xc304); +reg_write( DDR_REG_BASE +0x52eaf*4 +0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x52eb0*4 +0x02000000,0x3001); +reg_write( DDR_REG_BASE +0x52eb1*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x52eb2*4 +0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x52eb3*4 +0x02000000,0x1640); +reg_write( DDR_REG_BASE +0x52eb4*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x52eb5*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52eb6*4 +0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x52eb7*4 +0x02000000,0xc205); +reg_write( DDR_REG_BASE +0x52eb8*4 +0x02000000,0xcce); +reg_write( DDR_REG_BASE +0x52eb9*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x52eba*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52ebb*4 +0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x52ebc*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52ebd*4 +0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x52ebe*4 +0x02000000,0x3c81); +reg_write( DDR_REG_BASE +0x52ebf*4 +0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x52ec0*4 +0x02000000,0x3102); +reg_write( DDR_REG_BASE +0x52ec1*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52ec2*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52ec3*4 +0x02000000,0xc304); +reg_write( DDR_REG_BASE +0x52ec4*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x52ec5*4 +0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x52ec6*4 +0x02000000,0x1640); +reg_write( DDR_REG_BASE +0x52ec7*4 +0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x52ec8*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52ec9*4 +0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x52eca*4 +0x02000000,0xc205); +reg_write( DDR_REG_BASE +0x52ecb*4 +0x02000000,0xaf2); +reg_write( DDR_REG_BASE +0x52ecc*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x52ecd*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52ece*4 +0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x52ecf*4 +0x02000000,0xb6f); +reg_write( DDR_REG_BASE +0x52ed0*4 +0x02000000,0xb094); +reg_write( DDR_REG_BASE +0x52ed1*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x52ed2*4 +0x02000000,0xd53); +reg_write( DDR_REG_BASE +0x52ed3*4 +0x02000000,0x90b4); +reg_write( DDR_REG_BASE +0x52ed4*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52ed5*4 +0x02000000,0x912); +reg_write( DDR_REG_BASE +0x52ed6*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52ed7*4 +0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x52ed8*4 +0x02000000,0xc0a9); +reg_write( DDR_REG_BASE +0x52ed9*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52eda*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52edb*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52edc*4 +0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x52edd*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x52ede*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52edf*4 +0x02000000,0x669); +reg_write( DDR_REG_BASE +0x52ee0*4 +0x02000000,0x8a80); +reg_write( DDR_REG_BASE +0x52ee1*4 +0x02000000,0x8ac1); +reg_write( DDR_REG_BASE +0x52ee2*4 +0x02000000,0x245f); +reg_write( DDR_REG_BASE +0x52ee3*4 +0x02000000,0x1481); +reg_write( DDR_REG_BASE +0x52ee4*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x52ee5*4 +0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x52ee6*4 +0x02000000,0x919); +reg_write( DDR_REG_BASE +0x52ee7*4 +0x02000000,0x211); +reg_write( DDR_REG_BASE +0x52ee8*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x52ee9*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x52eea*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52eeb*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52eec*4 +0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x52eed*4 +0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x52eee*4 +0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52eef*4 +0x02000000,0x1064); +reg_write( DDR_REG_BASE +0x52ef0*4 +0x02000000,0x9040); +reg_write( DDR_REG_BASE +0x52ef1*4 +0x02000000,0xb540); +reg_write( DDR_REG_BASE +0x52ef2*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x52ef3*4 +0x02000000,0x7204); +reg_write( DDR_REG_BASE +0x52ef4*4 +0x02000000,0x9e5); +reg_write( DDR_REG_BASE +0x52ef5*4 +0x02000000,0x8254); +reg_write( DDR_REG_BASE +0x52ef6*4 +0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x52ef7*4 +0x02000000,0x7b8f); +reg_write( DDR_REG_BASE +0x52ef8*4 +0x02000000,0xef9); +reg_write( DDR_REG_BASE +0x52ef9*4 +0x02000000,0x90e5); +reg_write( DDR_REG_BASE +0x52efa*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52efb*4 +0x02000000,0xf2e); +reg_write( DDR_REG_BASE +0x52efc*4 +0x02000000,0xfe8f); +reg_write( DDR_REG_BASE +0x52efd*4 +0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x52efe*4 +0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x52eff*4 +0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x52f00*4 +0x02000000,0x3040); +reg_write( DDR_REG_BASE +0x52f01*4 +0x02000000,0x4308); +reg_write( DDR_REG_BASE +0x52f02*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52f03*4 +0x02000000,0xf024); +reg_write( DDR_REG_BASE +0x52f04*4 +0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x52f05*4 +0x02000000,0x1182); +reg_write( DDR_REG_BASE +0x52f06*4 +0x02000000,0x7261); +reg_write( DDR_REG_BASE +0x52f07*4 +0x02000000,0x8a01); +reg_write( DDR_REG_BASE +0x52f08*4 +0x02000000,0x8a60); +reg_write( DDR_REG_BASE +0x52f09*4 +0x02000000,0x8a22); +reg_write( DDR_REG_BASE +0x52f0a*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52f0b*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52f0c*4 +0x02000000,0x7b05); +reg_write( DDR_REG_BASE +0x52f0d*4 +0x02000000,0x8a03); +reg_write( DDR_REG_BASE +0x52f0e*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52f0f*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52f10*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52f11*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x52f12*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52f13*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52f14*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52f15*4 +0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52f16*4 +0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x52f17*4 +0x02000000,0x8a05); +reg_write( DDR_REG_BASE +0x52f18*4 +0x02000000,0x8a64); +reg_write( DDR_REG_BASE +0x52f19*4 +0x02000000,0x7734); +reg_write( DDR_REG_BASE +0x52f1a*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52f1b*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52f1c*4 +0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x52f1d*4 +0x02000000,0xf207); +reg_write( DDR_REG_BASE +0x52f1e*4 +0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x52f1f*4 +0x02000000,0xb99c); +reg_write( DDR_REG_BASE +0x52f20*4 +0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x52f21*4 +0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x52f22*4 +0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x52f23*4 +0x02000000,0xdb6); +reg_write( DDR_REG_BASE +0x52f24*4 +0x02000000,0xfe4f); +reg_write( DDR_REG_BASE +0x52f25*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x52f26*4 +0x02000000,0x2e45); +reg_write( DDR_REG_BASE +0x52f27*4 +0x02000000,0x3180); +reg_write( DDR_REG_BASE +0x52f28*4 +0x02000000,0xdb9); +reg_write( DDR_REG_BASE +0x52f29*4 +0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52f2a*4 +0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x52f2b*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52f2c*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52f2d*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52f2e*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52f2f*4 +0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x52f30*4 +0x02000000,0x4718); +reg_write( DDR_REG_BASE +0x52f31*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52f32*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52f33*4 +0x02000000,0x669); +reg_write( DDR_REG_BASE +0x52f34*4 +0x02000000,0x88c0); +reg_write( DDR_REG_BASE +0x52f35*4 +0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x52f36*4 +0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x52f37*4 +0x02000000,0xea04); +reg_write( DDR_REG_BASE +0x52f38*4 +0x02000000,0x79db); +reg_write( DDR_REG_BASE +0x52f39*4 +0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x52f3a*4 +0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x52f3b*4 +0x02000000,0x1241); +reg_write( DDR_REG_BASE +0x52f3c*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x52f3d*4 +0x02000000,0x9e); +reg_write( DDR_REG_BASE +0x52f3e*4 +0x02000000,0x7054); +reg_write( DDR_REG_BASE +0x52f3f*4 +0x02000000,0xdd08); +reg_write( DDR_REG_BASE +0x52f40*4 +0x02000000,0x25ca); +reg_write( DDR_REG_BASE +0x52f41*4 +0x02000000,0x1062); +reg_write( DDR_REG_BASE +0x52f42*4 +0x02000000,0xf039); +reg_write( DDR_REG_BASE +0x52f43*4 +0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x52f44*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52f45*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52f46*4 +0x02000000,0xc300); +reg_write( DDR_REG_BASE +0x52f47*4 +0x02000000,0x23f5); +reg_write( DDR_REG_BASE +0x52f48*4 +0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x52f49*4 +0x02000000,0xeb13); +reg_write( DDR_REG_BASE +0x52f4a*4 +0x02000000,0x7c5c); +reg_write( DDR_REG_BASE +0x52f4b*4 +0x02000000,0x7c9c); +reg_write( DDR_REG_BASE +0x52f4c*4 +0x02000000,0x7c9c); +reg_write( DDR_REG_BASE +0x52f4d*4 +0x02000000,0x7c9c); +reg_write( DDR_REG_BASE +0x52f4e*4 +0x02000000,0x224a); +reg_write( DDR_REG_BASE +0x52f4f*4 +0x02000000,0x16c0); +reg_write( DDR_REG_BASE +0x52f50*4 +0x02000000,0x2a44); +reg_write( DDR_REG_BASE +0x52f51*4 +0x02000000,0x803); +reg_write( DDR_REG_BASE +0x52f52*4 +0x02000000,0x2242); +reg_write( DDR_REG_BASE +0x52f53*4 +0x02000000,0x104a); +reg_write( DDR_REG_BASE +0x52f54*4 +0x02000000,0xafd); +reg_write( DDR_REG_BASE +0x52f55*4 +0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x52f56*4 +0x02000000,0x7c9d); +reg_write( DDR_REG_BASE +0x52f57*4 +0x02000000,0x629a); +reg_write( DDR_REG_BASE +0x52f58*4 +0x02000000,0xbac4); +reg_write( DDR_REG_BASE +0x52f59*4 +0x02000000,0x4a94); +reg_write( DDR_REG_BASE +0x52f5a*4 +0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x52f5b*4 +0x02000000,0x248a); +reg_write( DDR_REG_BASE +0x52f5c*4 +0x02000000,0x1fcf); +reg_write( DDR_REG_BASE +0x52f5d*4 +0x02000000,0x7c44); +reg_write( DDR_REG_BASE +0x52f5e*4 +0x02000000,0x2204); +reg_write( DDR_REG_BASE +0x52f5f*4 +0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x52f60*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52f61*4 +0x02000000,0xfc00); +reg_write( DDR_REG_BASE +0x52f62*4 +0x02000000,0xda0a); +reg_write( DDR_REG_BASE +0x52f63*4 +0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x52f64*4 +0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x52f65*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x52f66*4 +0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x52f67*4 +0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x52f68*4 +0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x52f69*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52f6a*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52f6b*4 +0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x52f6c*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52f6d*4 +0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x52f6e*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x52f6f*4 +0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x52f70*4 +0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x52f71*4 +0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x52f72*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52f73*4 +0x02000000,0xb891); +reg_write( DDR_REG_BASE +0x52f74*4 +0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x52f75*4 +0x02000000,0x7b85); +reg_write( DDR_REG_BASE +0x52f76*4 +0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x52f77*4 +0x02000000,0xb060); +reg_write( DDR_REG_BASE +0x52f78*4 +0x02000000,0xd97); +reg_write( DDR_REG_BASE +0x52f79*4 +0x02000000,0x93c5); +reg_write( DDR_REG_BASE +0x52f7a*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x52f7b*4 +0x02000000,0xefd); +reg_write( DDR_REG_BASE +0x52f7c*4 +0x02000000,0xb3a5); +reg_write( DDR_REG_BASE +0x52f7d*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x52f7e*4 +0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x52f7f*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52f80*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52f81*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52f82*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52f83*4 +0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x52f84*4 +0x02000000,0x216f); +reg_write( DDR_REG_BASE +0x52f85*4 +0x02000000,0xdc3); +reg_write( DDR_REG_BASE +0x52f86*4 +0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x52f87*4 +0x02000000,0x8900); +reg_write( DDR_REG_BASE +0x52f88*4 +0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x52f89*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x52f8a*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x52f8b*4 +0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x52f8c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52f8d*4 +0x02000000,0x684); +reg_write( DDR_REG_BASE +0x52f8e*4 +0x02000000,0x857); +reg_write( DDR_REG_BASE +0x52f8f*4 +0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x52f90*4 +0x02000000,0x7dc0); +reg_write( DDR_REG_BASE +0x52f91*4 +0x02000000,0x11e9); +reg_write( DDR_REG_BASE +0x52f92*4 +0x02000000,0x808f); +reg_write( DDR_REG_BASE +0x52f93*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52f94*4 +0x02000000,0x143); +reg_write( DDR_REG_BASE +0x52f95*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52f96*4 +0x02000000,0xac6); +reg_write( DDR_REG_BASE +0x52f97*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52f98*4 +0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x52f99*4 +0x02000000,0x275f); +reg_write( DDR_REG_BASE +0x52f9a*4 +0x02000000,0x1182); +reg_write( DDR_REG_BASE +0x52f9b*4 +0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x52f9c*4 +0x02000000,0x12); +reg_write( DDR_REG_BASE +0x52f9d*4 +0x02000000,0x310); +reg_write( DDR_REG_BASE +0x52f9e*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52f9f*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x52fa0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52fa1*4 +0x02000000,0xdf08); +reg_write( DDR_REG_BASE +0x52fa2*4 +0x02000000,0x6278); +reg_write( DDR_REG_BASE +0x52fa3*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52fa4*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x52fa5*4 +0x02000000,0xae00); +reg_write( DDR_REG_BASE +0x52fa6*4 +0x02000000,0xbf61); +reg_write( DDR_REG_BASE +0x52fa7*4 +0x02000000,0xf01); +reg_write( DDR_REG_BASE +0x52fa8*4 +0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x52fa9*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52faa*4 +0x02000000,0xae19); +reg_write( DDR_REG_BASE +0x52fab*4 +0x02000000,0x6b02); +reg_write( DDR_REG_BASE +0x52fac*4 +0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x52fad*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52fae*4 +0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x52faf*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52fb0*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52fb1*4 +0x02000000,0x6b6); +reg_write( DDR_REG_BASE +0x52fb2*4 +0x02000000,0xda08); +reg_write( DDR_REG_BASE +0x52fb3*4 +0x02000000,0xa900); +reg_write( DDR_REG_BASE +0x52fb4*4 +0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x52fb5*4 +0x02000000,0xa01); +reg_write( DDR_REG_BASE +0x52fb6*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x52fb7*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52fb8*4 +0x02000000,0xa919); +reg_write( DDR_REG_BASE +0x52fb9*4 +0x02000000,0xbe6c); +reg_write( DDR_REG_BASE +0x52fba*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52fbb*4 +0x02000000,0xed6); +reg_write( DDR_REG_BASE +0x52fbc*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x52fbd*4 +0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x52fbe*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52fbf*4 +0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x52fc0*4 +0x02000000,0x8d2); +reg_write( DDR_REG_BASE +0x52fc1*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x52fc2*4 +0x02000000,0xda40); +reg_write( DDR_REG_BASE +0x52fc3*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52fc4*4 +0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x52fc5*4 +0x02000000,0xfe2); +reg_write( DDR_REG_BASE +0x52fc6*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x52fc7*4 +0x02000000,0xda7f); +reg_write( DDR_REG_BASE +0x52fc8*4 +0x02000000,0xdfff); +reg_write( DDR_REG_BASE +0x52fc9*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52fca*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52fcb*4 +0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x52fcc*4 +0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x52fcd*4 +0x02000000,0xd3a); +reg_write( DDR_REG_BASE +0x52fce*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x52fcf*4 +0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x52fd0*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52fd1*4 +0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x52fd2*4 +0x02000000,0x8ae); +reg_write( DDR_REG_BASE +0x52fd3*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x52fd4*4 +0x02000000,0xda80); +reg_write( DDR_REG_BASE +0x52fd5*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52fd6*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52fd7*4 +0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x52fd8*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x52fd9*4 +0x02000000,0xdfff); +reg_write( DDR_REG_BASE +0x52fda*4 +0x02000000,0x776c); +reg_write( DDR_REG_BASE +0x52fdb*4 +0x02000000,0xd1e); +reg_write( DDR_REG_BASE +0x52fdc*4 +0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x52fdd*4 +0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x52fde*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52fdf*4 +0x02000000,0xbba); +reg_write( DDR_REG_BASE +0x52fe0*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x52fe1*4 +0x02000000,0xd90d); +reg_write( DDR_REG_BASE +0x52fe2*4 +0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x52fe3*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52fe4*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52fe5*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52fe6*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52fe7*4 +0x02000000,0xc1b2); +reg_write( DDR_REG_BASE +0x52fe8*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52fe9*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x52fea*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52feb*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52fec*4 +0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x52fed*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52fee*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x52fef*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52ff0*4 +0x02000000,0x996); +reg_write( DDR_REG_BASE +0x52ff1*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52ff2*4 +0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x52ff3*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52ff4*4 +0x02000000,0x4061); +reg_write( DDR_REG_BASE +0x52ff5*4 +0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x52ff6*4 +0x02000000,0x98a); +reg_write( DDR_REG_BASE +0x52ff7*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52ff8*4 +0x02000000,0xda08); +reg_write( DDR_REG_BASE +0x52ff9*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x52ffa*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52ffb*4 +0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x52ffc*4 +0x02000000,0x1f8d); +reg_write( DDR_REG_BASE +0x52ffd*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52ffe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52fff*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53000*4 +0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x53001*4 +0x02000000,0x8c0); +reg_write( DDR_REG_BASE +0x53002*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53003*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53004*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53005*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53006*4 +0x02000000,0x669); +reg_write( DDR_REG_BASE +0x53007*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x53008*4 +0x02000000,0xf042); +reg_write( DDR_REG_BASE +0x53009*4 +0x02000000,0xc606); +reg_write( DDR_REG_BASE +0x5300a*4 +0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5300b*4 +0x02000000,0x2351); +reg_write( DDR_REG_BASE +0x5300c*4 +0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x5300d*4 +0x02000000,0x26ca); +reg_write( DDR_REG_BASE +0x5300e*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x5300f*4 +0x02000000,0xee36); +reg_write( DDR_REG_BASE +0x53010*4 +0x02000000,0x784f); +reg_write( DDR_REG_BASE +0x53011*4 +0x02000000,0xd941); +reg_write( DDR_REG_BASE +0x53012*4 +0x02000000,0x790a); +reg_write( DDR_REG_BASE +0x53013*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x53014*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53015*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53016*4 +0x02000000,0x71a); +reg_write( DDR_REG_BASE +0x53017*4 +0x02000000,0x610a); +reg_write( DDR_REG_BASE +0x53018*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x53019*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x5301a*4 +0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x5301b*4 +0x02000000,0xca0c); +reg_write( DDR_REG_BASE +0x5301c*4 +0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x5301d*4 +0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x5301e*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x5301f*4 +0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x53020*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x53021*4 +0x02000000,0xea06); +reg_write( DDR_REG_BASE +0x53022*4 +0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x53023*4 +0x02000000,0xa01); +reg_write( DDR_REG_BASE +0x53024*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x53025*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x53026*4 +0x02000000,0x7f0f); +reg_write( DDR_REG_BASE +0x53027*4 +0x02000000,0xc202); +reg_write( DDR_REG_BASE +0x53028*4 +0x02000000,0x277c); +reg_write( DDR_REG_BASE +0x53029*4 +0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x5302a*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5302b*4 +0x02000000,0x75); +reg_write( DDR_REG_BASE +0x5302c*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x5302d*4 +0x02000000,0x9ea); +reg_write( DDR_REG_BASE +0x5302e*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x5302f*4 +0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x53030*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x53031*4 +0x02000000,0xc104); +reg_write( DDR_REG_BASE +0x53032*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x53033*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53034*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53035*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x53036*4 +0x02000000,0x79a5); +reg_write( DDR_REG_BASE +0x53037*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x53038*4 +0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x53039*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x5303a*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5303b*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x5303c*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5303d*4 +0x02000000,0xb891); +reg_write( DDR_REG_BASE +0x5303e*4 +0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x5303f*4 +0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x53040*4 +0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x53041*4 +0x02000000,0x79cf); +reg_write( DDR_REG_BASE +0x53042*4 +0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x53043*4 +0x02000000,0x611a); +reg_write( DDR_REG_BASE +0x53044*4 +0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x53045*4 +0x02000000,0xb8b); +reg_write( DDR_REG_BASE +0x53046*4 +0x02000000,0xb094); +reg_write( DDR_REG_BASE +0x53047*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x53048*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x53049*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5304a*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5304b*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x5304c*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5304d*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5304e*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5304f*4 +0x02000000,0x669); +reg_write( DDR_REG_BASE +0x53050*4 +0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x53051*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x53052*4 +0x02000000,0x9e7); +reg_write( DDR_REG_BASE +0x53053*4 +0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x53054*4 +0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x53055*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53056*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53057*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53058*4 +0x02000000,0x12); +reg_write( DDR_REG_BASE +0x53059*4 +0x02000000,0x847); +reg_write( DDR_REG_BASE +0x5305a*4 +0x02000000,0x1b5); +reg_write( DDR_REG_BASE +0x5305b*4 +0x02000000,0xc088); +reg_write( DDR_REG_BASE +0x5305c*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5305d*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x5305e*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5305f*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53060*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53061*4 +0x02000000,0xe8e); +reg_write( DDR_REG_BASE +0x53062*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x53063*4 +0x02000000,0xda28); +reg_write( DDR_REG_BASE +0x53064*4 +0x02000000,0xc203); +reg_write( DDR_REG_BASE +0x53065*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53066*4 +0x02000000,0x19); +reg_write( DDR_REG_BASE +0x53067*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53068*4 +0x02000000,0x922); +reg_write( DDR_REG_BASE +0x53069*4 +0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x5306a*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x5306b*4 +0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x5306c*4 +0x02000000,0x1f8d); +reg_write( DDR_REG_BASE +0x5306d*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5306e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5306f*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53070*4 +0x02000000,0xc188); +reg_write( DDR_REG_BASE +0x53071*4 +0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x53072*4 +0x02000000,0x9b2); +reg_write( DDR_REG_BASE +0x53073*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x53074*4 +0x02000000,0x78a5); +reg_write( DDR_REG_BASE +0x53075*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53076*4 +0x02000000,0x722c); +reg_write( DDR_REG_BASE +0x53077*4 +0x02000000,0xc288); +reg_write( DDR_REG_BASE +0x53078*4 +0x02000000,0xa5e); +reg_write( DDR_REG_BASE +0x53079*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x5307a*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5307b*4 +0x02000000,0xc0b2); +reg_write( DDR_REG_BASE +0x5307c*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x5307d*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x5307e*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5307f*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x53080*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x53081*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53082*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53083*4 +0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x53084*4 +0x02000000,0x3203); +reg_write( DDR_REG_BASE +0x53085*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x53086*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53087*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53088*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53089*4 +0x02000000,0x669); +reg_write( DDR_REG_BASE +0x5308a*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5308b*4 +0x02000000,0x709b); +reg_write( DDR_REG_BASE +0x5308c*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5308d*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5308e*4 +0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x5308f*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x53090*4 +0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x53091*4 +0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x53092*4 +0x02000000,0x3f9b); +reg_write( DDR_REG_BASE +0x53093*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x53094*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53095*4 +0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x53096*4 +0x02000000,0xc00); +reg_write( DDR_REG_BASE +0x53097*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x53098*4 +0x02000000,0xf057); +reg_write( DDR_REG_BASE +0x53099*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5309a*4 +0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x5309b*4 +0x02000000,0x17c1); +reg_write( DDR_REG_BASE +0x5309c*4 +0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x5309d*4 +0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x5309e*4 +0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x5309f*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x530a0*4 +0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x530a1*4 +0x02000000,0x893); +reg_write( DDR_REG_BASE +0x530a2*4 +0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x530a3*4 +0x02000000,0x78ef); +reg_write( DDR_REG_BASE +0x530a4*4 +0x02000000,0x209f); +reg_write( DDR_REG_BASE +0x530a5*4 +0x02000000,0x41); +reg_write( DDR_REG_BASE +0x530a6*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x530a7*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x530a8*4 +0x02000000,0x71a); +reg_write( DDR_REG_BASE +0x530a9*4 +0x02000000,0x602a); +reg_write( DDR_REG_BASE +0x530aa*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x530ab*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x530ac*4 +0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x530ad*4 +0x02000000,0xca0c); +reg_write( DDR_REG_BASE +0x530ae*4 +0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x530af*4 +0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x530b0*4 +0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x530b1*4 +0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x530b2*4 +0x02000000,0xea05); +reg_write( DDR_REG_BASE +0x530b3*4 +0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x530b4*4 +0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x530b5*4 +0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x530b6*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x530b7*4 +0x02000000,0x7a0e); +reg_write( DDR_REG_BASE +0x530b8*4 +0x02000000,0x785c); +reg_write( DDR_REG_BASE +0x530b9*4 +0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x530ba*4 +0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x530bb*4 +0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x530bc*4 +0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x530bd*4 +0x02000000,0xd81b); +reg_write( DDR_REG_BASE +0x530be*4 +0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x530bf*4 +0x02000000,0x801); +reg_write( DDR_REG_BASE +0x530c0*4 +0x02000000,0x31); +reg_write( DDR_REG_BASE +0x530c1*4 +0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x530c2*4 +0x02000000,0x6238); +reg_write( DDR_REG_BASE +0x530c3*4 +0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x530c4*4 +0x02000000,0x4831); +reg_write( DDR_REG_BASE +0x530c5*4 +0x02000000,0x2a44); +reg_write( DDR_REG_BASE +0x530c6*4 +0x02000000,0x800); +reg_write( DDR_REG_BASE +0x530c7*4 +0x02000000,0xc202); +reg_write( DDR_REG_BASE +0x530c8*4 +0x02000000,0x7d10); +reg_write( DDR_REG_BASE +0x530c9*4 +0x02000000,0x257c); +reg_write( DDR_REG_BASE +0x530ca*4 +0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x530cb*4 +0x02000000,0x259a); +reg_write( DDR_REG_BASE +0x530cc*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x530cd*4 +0x02000000,0x7d25); +reg_write( DDR_REG_BASE +0x530ce*4 +0x02000000,0x79b0); +reg_write( DDR_REG_BASE +0x530cf*4 +0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x530d0*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x530d1*4 +0x02000000,0x7b); +reg_write( DDR_REG_BASE +0x530d2*4 +0x02000000,0x3); +reg_write( DDR_REG_BASE +0x530d3*4 +0x02000000,0x89e); +reg_write( DDR_REG_BASE +0x530d4*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x530d5*4 +0x02000000,0x43c1); +reg_write( DDR_REG_BASE +0x530d6*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x530d7*4 +0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x530d8*4 +0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x530d9*4 +0x02000000,0x3001); +reg_write( DDR_REG_BASE +0x530da*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x530db*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x530dc*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x530dd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530de*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x530df*4 +0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x530e0*4 +0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x530e1*4 +0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x530e2*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x530e3*4 +0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x530e4*4 +0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x530e5*4 +0x02000000,0xb891); +reg_write( DDR_REG_BASE +0x530e6*4 +0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x530e7*4 +0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x530e8*4 +0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x530e9*4 +0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x530ea*4 +0x02000000,0xe5f); +reg_write( DDR_REG_BASE +0x530eb*4 +0x02000000,0x9254); +reg_write( DDR_REG_BASE +0x530ec*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x530ed*4 +0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x530ee*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x530ef*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x530f0*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x530f1*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x530f2*4 +0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x530f3*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x530f4*4 +0x02000000,0x669); +reg_write( DDR_REG_BASE +0x530f5*4 +0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x530f6*4 +0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x530f7*4 +0x02000000,0x9e9); +reg_write( DDR_REG_BASE +0x530f8*4 +0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x530f9*4 +0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x530fa*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x530fb*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x530fc*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x530fd*4 +0x02000000,0x12); +reg_write( DDR_REG_BASE +0x530fe*4 +0x02000000,0x845); +reg_write( DDR_REG_BASE +0x530ff*4 +0x02000000,0x1b5); +reg_write( DDR_REG_BASE +0x53100*4 +0x02000000,0xc085); +reg_write( DDR_REG_BASE +0x53101*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53102*4 +0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x53103*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53104*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53105*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53106*4 +0x02000000,0xd42); +reg_write( DDR_REG_BASE +0x53107*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x53108*4 +0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x53109*4 +0x02000000,0xc203); +reg_write( DDR_REG_BASE +0x5310a*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5310b*4 +0x02000000,0x17); +reg_write( DDR_REG_BASE +0x5310c*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5310d*4 +0x02000000,0xfda); +reg_write( DDR_REG_BASE +0x5310e*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x5310f*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x53110*4 +0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x53111*4 +0x02000000,0x1f8d); +reg_write( DDR_REG_BASE +0x53112*4 +0x02000000,0x10); +reg_write( DDR_REG_BASE +0x53113*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53114*4 +0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x53115*4 +0x02000000,0xc185); +reg_write( DDR_REG_BASE +0x53116*4 +0x02000000,0xda09); +reg_write( DDR_REG_BASE +0x53117*4 +0x02000000,0x86a); +reg_write( DDR_REG_BASE +0x53118*4 +0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x53119*4 +0x02000000,0x78a5); +reg_write( DDR_REG_BASE +0x5311a*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5311b*4 +0x02000000,0xd909); +reg_write( DDR_REG_BASE +0x5311c*4 +0x02000000,0xc285); +reg_write( DDR_REG_BASE +0x5311d*4 +0x02000000,0x916); +reg_write( DDR_REG_BASE +0x5311e*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x5311f*4 +0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x53120*4 +0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x53121*4 +0x02000000,0x3203); +reg_write( DDR_REG_BASE +0x53122*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x53123*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x53124*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x53125*4 +0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x53126*4 +0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x53127*4 +0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x53128*4 +0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x53129*4 +0x02000000,0xc1ad); +reg_write( DDR_REG_BASE +0x5312a*4 +0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5312b*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5312c*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5312d*4 +0x02000000,0xf1e); +reg_write( DDR_REG_BASE +0x5312e*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x5312f*4 +0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x53130*4 +0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x53131*4 +0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53132*4 +0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x53133*4 +0x02000000,0xf12); +reg_write( DDR_REG_BASE +0x53134*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53135*4 +0x02000000,0xda08); +reg_write( DDR_REG_BASE +0x53136*4 +0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x53137*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x53138*4 +0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x53139*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5313a*4 +0x02000000,0x667); +reg_write( DDR_REG_BASE +0x5313b*4 +0x02000000,0x8f20); +reg_write( DDR_REG_BASE +0x5313c*4 +0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x5313d*4 +0x02000000,0x500); +reg_write( DDR_REG_BASE +0x5313e*4 +0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5313f*4 +0x02000000,0x603a); +reg_write( DDR_REG_BASE +0x53140*4 +0x02000000,0x2200); +reg_write( DDR_REG_BASE +0x53141*4 +0x02000000,0xf9b); +reg_write( DDR_REG_BASE +0x53142*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53143*4 +0x02000000,0x1b70); +reg_write( DDR_REG_BASE +0x53144*4 +0x02000000,0xb76); +reg_write( DDR_REG_BASE +0x53145*4 +0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x53146*4 +0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x53147*4 +0x02000000,0x8f20); +reg_write( DDR_REG_BASE +0x53148*4 +0x02000000,0x8fc1); +reg_write( DDR_REG_BASE +0x53149*4 +0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5314a*4 +0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x5314b*4 +0x02000000,0x3040); +reg_write( DDR_REG_BASE +0x5314c*4 +0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x5314d*4 +0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5314e*4 +0x02000000,0xc241); +reg_write( DDR_REG_BASE +0x5314f*4 +0x02000000,0xf020); +reg_write( DDR_REG_BASE +0x53150*4 +0x02000000,0xc507); +reg_write( DDR_REG_BASE +0x53151*4 +0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53152*4 +0x02000000,0x25ca); +reg_write( DDR_REG_BASE +0x53153*4 +0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x53154*4 +0x02000000,0xed18); +reg_write( DDR_REG_BASE +0x53155*4 +0x02000000,0xca07); +reg_write( DDR_REG_BASE +0x53156*4 +0x02000000,0x92b); +reg_write( DDR_REG_BASE +0x53157*4 +0x02000000,0x25); +reg_write( DDR_REG_BASE +0x53158*4 +0x02000000,0x784f); +reg_write( DDR_REG_BASE +0x53159*4 +0x02000000,0xd941); +reg_write( DDR_REG_BASE +0x5315a*4 +0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5315b*4 +0x02000000,0x782a); +reg_write( DDR_REG_BASE +0x5315c*4 +0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x5315d*4 +0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5315e*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5315f*4 +0x02000000,0x71c); +reg_write( DDR_REG_BASE +0x53160*4 +0x02000000,0xb9a); +reg_write( DDR_REG_BASE +0x53161*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x53162*4 +0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x53163*4 +0x02000000,0x1b00); +reg_write( DDR_REG_BASE +0x53164*4 +0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x53165*4 +0x02000000,0xc204); +reg_write( DDR_REG_BASE +0x53166*4 +0x02000000,0xc105); +reg_write( DDR_REG_BASE +0x53167*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x53168*4 +0x02000000,0x62ba); +reg_write( DDR_REG_BASE +0x53169*4 +0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x5316a*4 +0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5316b*4 +0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x5316c*4 +0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x5316d*4 +0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x5316e*4 +0x02000000,0x212f); +reg_write( DDR_REG_BASE +0x5316f*4 +0x02000000,0x787); +reg_write( DDR_REG_BASE +0x53170*4 +0x02000000,0xec1); +reg_write( DDR_REG_BASE +0x53171*4 +0x02000000,0x9065); +reg_write( DDR_REG_BASE +0x53172*4 +0x02000000,0x2651); +reg_write( DDR_REG_BASE +0x53173*4 +0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x53174*4 +0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53175*4 +0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53176*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53177*4 +0x02000000,0x12); +reg_write( DDR_REG_BASE +0x53178*4 +0x02000000,0x861); +reg_write( DDR_REG_BASE +0x53179*4 +0x02000000,0x1b5); +reg_write( DDR_REG_BASE +0x5317a*4 +0x02000000,0xc088); +reg_write( DDR_REG_BASE +0x5317b*4 +0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5317c*4 +0x02000000,0xc56); +reg_write( DDR_REG_BASE +0x5317d*4 +0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x5317e*4 +0x02000000,0xda14); +reg_write( DDR_REG_BASE +0x5317f*4 +0x02000000,0xc200); +reg_write( DDR_REG_BASE +0x53180*4 +0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x53181*4 +0x02000000,0x18); +reg_write( DDR_REG_BASE +0x53182*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x53183*4 +0x02000000,0xeee); +reg_write( DDR_REG_BASE +0x53184*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x53185*4 +0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x53186*4 +0x02000000,0xc203); +reg_write( DDR_REG_BASE +0x53187*4 +0x02000000,0x8f22); +reg_write( DDR_REG_BASE +0x53188*4 +0x02000000,0x8f63); +reg_write( DDR_REG_BASE +0x53189*4 +0x02000000,0x2200); +reg_write( DDR_REG_BASE +0x5318a*4 +0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x5318b*4 +0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5318c*4 +0x02000000,0x1b70); +reg_write( DDR_REG_BASE +0x5318d*4 +0x02000000,0x7c3b); +reg_write( DDR_REG_BASE +0x5318e*4 +0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x5318f*4 +0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x53190*4 +0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x53191*4 +0x02000000,0xc688); +reg_write( DDR_REG_BASE +0x53192*4 +0x02000000,0x661e); +reg_write( DDR_REG_BASE +0x53193*4 +0x02000000,0x6208); +reg_write( DDR_REG_BASE +0x53194*4 +0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x53195*4 +0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x53196*4 +0x02000000,0xae00); +reg_write( DDR_REG_BASE +0x53197*4 +0x02000000,0x78af); +reg_write( DDR_REG_BASE +0x53198*4 +0x02000000,0x8f3); +reg_write( DDR_REG_BASE +0x53199*4 +0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x5319a*4 +0x02000000,0x7890); +reg_write( DDR_REG_BASE +0x5319b*4 +0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x5319c*4 +0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x5319d*4 +0x02000000,0xbe7); +reg_write( DDR_REG_BASE +0x5319e*4 +0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x5319f*4 +0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x531a0*4 +0x02000000,0x722c); +reg_write( DDR_REG_BASE +0x531a1*4 +0x02000000,0xc288); +reg_write( DDR_REG_BASE +0x531a2*4 +0x02000000,0x80a); +reg_write( DDR_REG_BASE +0x531a3*4 +0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x531a4*4 +0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x531a5*4 +0x02000000,0x1700); +reg_write( DDR_REG_BASE +0x531a6*4 +0x02000000,0x108b); +reg_write( DDR_REG_BASE +0x531a7*4 +0x02000000,0x8fc1); +reg_write( DDR_REG_BASE +0x531a8*4 +0x02000000,0x234e); +reg_write( DDR_REG_BASE +0x531a9*4 +0x02000000,0x1040); +reg_write( DDR_REG_BASE +0x531aa*4 +0x02000000,0x661e); +reg_write( DDR_REG_BASE +0x531ab*4 +0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x531ac*4 +0x02000000,0x79d0); +reg_write( DDR_REG_BASE +0x531ad*4 +0x02000000,0x2805); +reg_write( DDR_REG_BASE +0x531ae*4 +0x02000000,0x40); +reg_write( DDR_REG_BASE +0x531af*4 +0x02000000,0xafe); +reg_write( DDR_REG_BASE +0x531b0*4 +0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x531b1*4 +0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x531b2*4 +0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x531b3*4 +0x02000000,0xa900); +reg_write( DDR_REG_BASE +0x531b4*4 +0x02000000,0xc0ad); +reg_write( DDR_REG_BASE +0x531b5*4 +0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x531b6*4 +0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x531b7*4 +0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x531b8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531b9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531ba*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531bb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531bc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531bd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531be*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531bf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531c0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531c1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531c2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531c3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531c4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531c5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531c6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531c7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531c8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531c9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531ca*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531cb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531cc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531cd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531ce*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531cf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531d0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531d1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531d2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531d3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531d4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531d5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531d6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531d7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531d8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531d9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531da*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531db*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531dc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531dd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531de*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531df*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531e0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531e1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531e2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531e3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531e4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531e5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531e6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531e7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531e8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531e9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531ea*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531eb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531ec*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531ed*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531ee*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531ef*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531f0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531f1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531f2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531f3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531f4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531f5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531f6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531f7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531f8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531f9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531fa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531fb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531fc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531fd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531fe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531ff*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53200*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53201*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53202*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53203*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53204*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53205*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53206*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53207*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53208*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53209*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5320a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5320b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5320c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5320d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5320e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5320f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53210*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53211*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53212*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53213*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53214*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53215*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53216*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53217*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53218*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53219*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5321a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5321b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5321c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5321d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5321e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5321f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53220*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53221*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53222*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53223*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53224*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53225*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53226*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53227*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53228*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53229*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5322a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5322b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5322c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5322d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5322e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5322f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53230*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53231*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53232*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53233*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53234*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53235*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53236*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53237*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53238*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53239*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5323a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5323b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5323c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5323d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5323e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5323f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53240*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53241*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53242*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53243*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53244*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53245*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53246*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53247*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53248*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53249*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5324a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5324b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5324c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5324d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5324e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5324f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53250*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53251*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53252*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53253*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53254*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53255*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53256*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53257*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53258*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53259*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5325a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5325b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5325c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5325d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5325e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5325f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53260*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53261*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53262*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53263*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53264*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53265*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53266*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53267*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53268*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53269*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5326a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5326b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5326c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5326d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5326e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5326f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53270*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53271*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53272*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53273*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53274*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53275*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53276*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53277*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53278*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53279*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5327a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5327b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5327c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5327d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5327e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5327f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53280*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53281*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53282*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53283*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53284*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53285*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53286*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53287*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53288*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53289*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5328a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5328b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5328c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5328d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5328e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5328f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53290*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53291*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53292*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53293*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53294*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53295*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53296*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53297*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53298*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53299*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5329a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5329b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5329c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5329d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5329e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5329f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532a0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532a1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532a2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532a3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532a4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532a5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532a6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532a7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532a8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532a9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532aa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532ab*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532ac*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532ad*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532ae*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532af*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532b0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532b1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532b2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532b3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532b4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532b5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532b6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532b7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532b8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532b9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532ba*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532bb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532bc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532bd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532be*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532bf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532c0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532c1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532c2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532c3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532c4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532c5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532c6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532c7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532c8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532c9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532ca*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532cb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532cc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532cd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532ce*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532cf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532d0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532d1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532d2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532d3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532d4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532d5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532d6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532d7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532d8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532d9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532da*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532db*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532dc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532dd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532de*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532df*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532e0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532e1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532e2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532e3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532e4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532e5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532e6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532e7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532e8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532e9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532ea*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532eb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532ec*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532ed*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532ee*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532ef*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532f0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532f1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532f2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532f3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532f4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532f5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532f6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532f7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532f8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532f9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532fa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532fb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532fc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532fd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532fe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532ff*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53300*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53301*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53302*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53303*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53304*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53305*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53306*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53307*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53308*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53309*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5330a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5330b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5330c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5330d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5330e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5330f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53310*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53311*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53312*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53313*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53314*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53315*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53316*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53317*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53318*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53319*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5331a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5331b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5331c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5331d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5331e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5331f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53320*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53321*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53322*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53323*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53324*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53325*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53326*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53327*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53328*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53329*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5332a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5332b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5332c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5332d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5332e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5332f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53330*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53331*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53332*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53333*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53334*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53335*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53336*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53337*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53338*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53339*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5333a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5333b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5333c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5333d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5333e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5333f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53340*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53341*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53342*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53343*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53344*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53345*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53346*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53347*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53348*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53349*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5334a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5334b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5334c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5334d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5334e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5334f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53350*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53351*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53352*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53353*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53354*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53355*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53356*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53357*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53358*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53359*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5335a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5335b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5335c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5335d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5335e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5335f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53360*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53361*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53362*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53363*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53364*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53365*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53366*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53367*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53368*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53369*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5336a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5336b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5336c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5336d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5336e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5336f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53370*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53371*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53372*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53373*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53374*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53375*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53376*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53377*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53378*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53379*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5337a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5337b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5337c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5337d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5337e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5337f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53380*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53381*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53382*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53383*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53384*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53385*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53386*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53387*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53388*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53389*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5338a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5338b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5338c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5338d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5338e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5338f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53390*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53391*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53392*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53393*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53394*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53395*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53396*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53397*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53398*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53399*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5339a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5339b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5339c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5339d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5339e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5339f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533a0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533a1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533a2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533a3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533a4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533a5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533a6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533a7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533a8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533a9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533aa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533ab*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533ac*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533ad*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533ae*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533af*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533b0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533b1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533b2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533b3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533b4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533b5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533b6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533b7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533b8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533b9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533ba*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533bb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533bc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533bd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533be*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533bf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533c0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533c1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533c2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533c3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533c4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533c5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533c6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533c7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533c8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533c9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533ca*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533cb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533cc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533cd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533ce*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533cf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533d0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533d1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533d2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533d3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533d4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533d5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533d6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533d7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533d8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533d9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533da*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533db*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533dc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533dd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533de*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533df*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533e0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533e1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533e2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533e3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533e4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533e5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533e6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533e7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533e8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533e9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533ea*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533eb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533ec*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533ed*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533ee*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533ef*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533f0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533f1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533f2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533f3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533f4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533f5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533f6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533f7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533f8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533f9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533fa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533fb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533fc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533fd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533fe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533ff*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53400*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53401*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53402*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53403*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53404*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53405*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53406*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53407*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53408*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53409*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5340a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5340b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5340c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5340d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5340e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5340f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53410*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53411*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53412*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53413*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53414*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53415*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53416*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53417*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53418*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53419*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5341a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5341b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5341c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5341d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5341e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5341f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53420*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53421*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53422*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53423*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53424*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53425*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53426*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53427*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53428*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53429*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5342a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5342b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5342c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5342d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5342e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5342f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53430*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53431*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53432*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53433*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53434*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53435*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53436*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53437*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53438*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53439*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5343a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5343b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5343c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5343d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5343e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5343f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53440*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53441*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53442*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53443*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53444*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53445*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53446*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53447*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53448*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53449*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5344a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5344b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5344c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5344d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5344e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5344f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53450*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53451*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53452*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53453*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53454*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53455*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53456*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53457*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53458*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53459*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5345a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5345b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5345c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5345d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5345e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5345f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53460*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53461*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53462*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53463*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53464*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53465*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53466*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53467*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53468*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53469*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5346a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5346b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5346c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5346d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5346e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5346f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53470*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53471*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53472*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53473*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53474*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53475*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53476*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53477*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53478*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53479*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5347a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5347b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5347c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5347d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5347e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5347f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53480*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53481*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53482*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53483*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53484*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53485*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53486*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53487*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53488*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53489*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5348a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5348b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5348c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5348d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5348e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5348f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53490*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53491*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53492*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53493*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53494*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53495*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53496*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53497*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53498*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53499*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5349a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5349b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5349c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5349d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5349e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5349f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534a0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534a1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534a2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534a3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534a4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534a5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534a6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534a7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534a8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534a9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534aa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534ab*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534ac*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534ad*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534ae*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534af*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534b0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534b1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534b2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534b3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534b4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534b5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534b6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534b7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534b8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534b9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534ba*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534bb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534bc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534bd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534be*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534bf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534c0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534c1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534c2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534c3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534c4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534c5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534c6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534c7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534c8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534c9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534ca*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534cb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534cc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534cd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534ce*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534cf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534d0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534d1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534d2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534d3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534d4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534d5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534d6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534d7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534d8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534d9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534da*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534db*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534dc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534dd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534de*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534df*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534e0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534e1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534e2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534e3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534e4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534e5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534e6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534e7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534e8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534e9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534ea*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534eb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534ec*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534ed*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534ee*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534ef*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534f0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534f1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534f2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534f3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534f4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534f5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534f6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534f7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534f8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534f9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534fa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534fb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534fc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534fd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534fe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534ff*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53500*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53501*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53502*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53503*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53504*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53505*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53506*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53507*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53508*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53509*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5350a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5350b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5350c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5350d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5350e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5350f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53510*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53511*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53512*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53513*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53514*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53515*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53516*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53517*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53518*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53519*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5351a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5351b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5351c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5351d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5351e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5351f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53520*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53521*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53522*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53523*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53524*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53525*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53526*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53527*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53528*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53529*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5352a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5352b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5352c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5352d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5352e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5352f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53530*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53531*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53532*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53533*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53534*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53535*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53536*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53537*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53538*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53539*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5353a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5353b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5353c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5353d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5353e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5353f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53540*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53541*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53542*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53543*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53544*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53545*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53546*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53547*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53548*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53549*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5354a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5354b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5354c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5354d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5354e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5354f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53550*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53551*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53552*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53553*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53554*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53555*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53556*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53557*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53558*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53559*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5355a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5355b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5355c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5355d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5355e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5355f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53560*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53561*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53562*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53563*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53564*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53565*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53566*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53567*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53568*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53569*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5356a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5356b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5356c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5356d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5356e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5356f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53570*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53571*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53572*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53573*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53574*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53575*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53576*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53577*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53578*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53579*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5357a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5357b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5357c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5357d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5357e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5357f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53580*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53581*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53582*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53583*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53584*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53585*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53586*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53587*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53588*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53589*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5358a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5358b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5358c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5358d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5358e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5358f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53590*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53591*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53592*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53593*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53594*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53595*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53596*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53597*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53598*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53599*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5359a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5359b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5359c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5359d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5359e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5359f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535a0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535a1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535a2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535a3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535a4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535a5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535a6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535a7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535a8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535a9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535aa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535ab*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535ac*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535ad*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535ae*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535af*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535b0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535b1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535b2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535b3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535b4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535b5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535b6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535b7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535b8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535b9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535ba*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535bb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535bc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535bd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535be*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535bf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535c0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535c1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535c2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535c3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535c4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535c5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535c6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535c7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535c8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535c9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535ca*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535cb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535cc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535cd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535ce*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535cf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535d0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535d1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535d2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535d3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535d4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535d5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535d6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535d7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535d8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535d9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535da*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535db*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535dc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535dd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535de*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535df*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535e0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535e1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535e2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535e3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535e4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535e5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535e6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535e7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535e8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535e9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535ea*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535eb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535ec*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535ed*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535ee*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535ef*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535f0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535f1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535f2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535f3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535f4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535f5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535f6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535f7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535f8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535f9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535fa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535fb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535fc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535fd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535fe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535ff*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53600*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53601*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53602*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53603*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53604*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53605*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53606*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53607*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53608*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53609*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5360a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5360b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5360c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5360d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5360e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5360f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53610*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53611*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53612*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53613*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53614*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53615*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53616*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53617*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53618*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53619*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5361a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5361b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5361c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5361d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5361e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5361f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53620*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53621*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53622*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53623*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53624*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53625*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53626*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53627*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53628*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53629*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5362a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5362b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5362c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5362d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5362e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5362f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53630*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53631*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53632*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53633*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53634*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53635*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53636*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53637*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53638*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53639*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5363a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5363b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5363c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5363d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5363e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5363f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53640*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53641*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53642*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53643*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53644*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53645*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53646*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53647*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53648*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53649*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5364a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5364b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5364c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5364d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5364e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5364f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53650*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53651*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53652*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53653*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53654*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53655*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53656*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53657*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53658*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53659*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5365a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5365b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5365c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5365d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5365e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5365f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53660*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53661*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53662*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53663*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53664*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53665*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53666*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53667*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53668*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53669*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5366a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5366b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5366c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5366d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5366e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5366f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53670*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53671*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53672*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53673*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53674*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53675*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53676*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53677*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53678*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53679*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5367a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5367b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5367c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5367d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5367e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5367f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53680*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53681*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53682*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53683*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53684*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53685*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53686*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53687*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53688*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53689*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5368a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5368b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5368c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5368d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5368e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5368f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53690*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53691*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53692*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53693*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53694*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53695*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53696*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53697*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53698*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53699*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5369a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5369b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5369c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5369d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5369e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5369f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536a0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536a1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536a2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536a3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536a4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536a5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536a6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536a7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536a8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536a9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536aa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ab*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ac*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ad*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ae*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536af*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536b0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536b1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536b2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536b3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536b4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536b5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536b6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536b7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536b8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536b9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ba*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536bb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536bc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536bd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536be*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536bf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536c0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536c1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536c2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536c3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536c4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536c5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536c6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536c7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536c8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536c9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ca*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536cb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536cc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536cd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ce*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536cf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536d0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536d1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536d2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536d3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536d4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536d5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536d6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536d7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536d8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536d9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536da*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536db*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536dc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536dd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536de*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536df*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536e0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536e1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536e2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536e3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536e4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536e5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536e6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536e7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536e8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536e9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ea*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536eb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ec*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ed*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ee*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ef*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536f0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536f1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536f2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536f3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536f4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536f5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536f6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536f7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536f8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536f9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536fa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536fb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536fc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536fd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536fe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ff*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53700*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53701*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53702*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53703*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53704*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53705*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53706*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53707*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53708*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53709*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5370a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5370b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5370c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5370d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5370e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5370f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53710*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53711*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53712*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53713*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53714*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53715*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53716*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53717*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53718*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53719*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5371a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5371b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5371c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5371d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5371e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5371f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53720*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53721*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53722*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53723*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53724*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53725*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53726*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53727*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53728*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53729*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5372a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5372b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5372c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5372d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5372e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5372f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53730*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53731*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53732*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53733*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53734*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53735*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53736*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53737*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53738*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53739*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5373a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5373b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5373c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5373d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5373e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5373f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53740*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53741*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53742*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53743*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53744*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53745*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53746*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53747*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53748*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53749*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5374a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5374b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5374c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5374d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5374e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5374f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53750*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53751*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53752*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53753*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53754*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53755*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53756*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53757*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53758*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53759*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5375a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5375b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5375c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5375d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5375e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5375f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53760*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53761*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53762*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53763*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53764*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53765*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53766*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53767*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53768*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53769*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5376a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5376b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5376c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5376d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5376e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5376f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53770*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53771*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53772*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53773*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53774*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53775*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53776*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53777*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53778*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53779*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5377a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5377b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5377c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5377d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5377e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5377f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53780*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53781*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53782*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53783*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53784*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53785*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53786*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53787*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53788*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53789*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5378a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5378b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5378c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5378d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5378e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5378f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53790*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53791*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53792*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53793*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53794*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53795*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53796*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53797*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53798*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53799*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5379a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5379b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5379c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5379d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5379e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5379f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537a0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537a1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537a2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537a3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537a4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537a5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537a6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537a7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537a8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537a9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537aa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537ab*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537ac*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537ad*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537ae*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537af*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537b0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537b1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537b2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537b3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537b4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537b5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537b6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537b7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537b8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537b9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537ba*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537bb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537bc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537bd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537be*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537bf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537c0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537c1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537c2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537c3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537c4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537c5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537c6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537c7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537c8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537c9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537ca*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537cb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537cc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537cd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537ce*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537cf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537d0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537d1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537d2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537d3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537d4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537d5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537d6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537d7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537d8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537d9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537da*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537db*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537dc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537dd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537de*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537df*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537e0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537e1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537e2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537e3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537e4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537e5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537e6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537e7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537e8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537e9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537ea*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537eb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537ec*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537ed*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537ee*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537ef*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537f0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537f1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537f2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537f3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537f4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537f5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537f6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537f7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537f8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537f9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537fa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537fb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537fc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537fd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537fe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537ff*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53800*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53801*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53802*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53803*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53804*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53805*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53806*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53807*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53808*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53809*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5380a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5380b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5380c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5380d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5380e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5380f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53810*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53811*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53812*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53813*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53814*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53815*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53816*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53817*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53818*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53819*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5381a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5381b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5381c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5381d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5381e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5381f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53820*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53821*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53822*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53823*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53824*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53825*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53826*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53827*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53828*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53829*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5382a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5382b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5382c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5382d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5382e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5382f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53830*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53831*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53832*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53833*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53834*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53835*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53836*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53837*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53838*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53839*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5383a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5383b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5383c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5383d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5383e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5383f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53840*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53841*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53842*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53843*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53844*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53845*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53846*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53847*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53848*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53849*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5384a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5384b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5384c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5384d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5384e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5384f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53850*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53851*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53852*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53853*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53854*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53855*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53856*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53857*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53858*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53859*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5385a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5385b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5385c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5385d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5385e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5385f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53860*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53861*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53862*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53863*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53864*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53865*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53866*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53867*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53868*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53869*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5386a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5386b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5386c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5386d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5386e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5386f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53870*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53871*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53872*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53873*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53874*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53875*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53876*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53877*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53878*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53879*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5387a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5387b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5387c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5387d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5387e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5387f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53880*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53881*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53882*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53883*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53884*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53885*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53886*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53887*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53888*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53889*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5388a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5388b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5388c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5388d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5388e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5388f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53890*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53891*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53892*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53893*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53894*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53895*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53896*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53897*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53898*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53899*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5389a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5389b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5389c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5389d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5389e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5389f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538a0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538a1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538a2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538a3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538a4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538a5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538a6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538a7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538a8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538a9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538aa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538ab*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538ac*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538ad*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538ae*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538af*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538b0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538b1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538b2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538b3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538b4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538b5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538b6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538b7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538b8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538b9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538ba*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538bb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538bc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538bd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538be*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538bf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538c0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538c1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538c2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538c3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538c4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538c5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538c6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538c7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538c8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538c9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538ca*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538cb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538cc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538cd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538ce*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538cf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538d0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538d1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538d2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538d3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538d4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538d5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538d6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538d7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538d8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538d9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538da*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538db*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538dc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538dd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538de*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538df*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538e0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538e1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538e2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538e3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538e4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538e5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538e6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538e7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538e8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538e9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538ea*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538eb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538ec*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538ed*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538ee*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538ef*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538f0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538f1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538f2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538f3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538f4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538f5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538f6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538f7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538f8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538f9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538fa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538fb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538fc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538fd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538fe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538ff*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53900*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53901*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53902*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53903*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53904*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53905*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53906*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53907*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53908*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53909*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5390a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5390b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5390c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5390d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5390e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5390f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53910*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53911*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53912*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53913*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53914*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53915*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53916*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53917*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53918*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53919*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5391a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5391b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5391c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5391d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5391e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5391f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53920*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53921*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53922*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53923*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53924*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53925*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53926*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53927*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53928*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53929*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5392a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5392b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5392c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5392d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5392e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5392f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53930*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53931*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53932*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53933*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53934*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53935*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53936*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53937*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53938*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53939*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5393a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5393b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5393c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5393d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5393e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5393f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53940*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53941*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53942*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53943*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53944*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53945*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53946*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53947*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53948*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53949*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5394a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5394b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5394c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5394d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5394e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5394f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53950*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53951*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53952*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53953*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53954*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53955*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53956*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53957*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53958*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53959*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5395a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5395b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5395c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5395d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5395e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5395f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53960*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53961*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53962*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53963*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53964*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53965*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53966*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53967*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53968*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53969*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5396a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5396b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5396c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5396d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5396e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5396f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53970*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53971*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53972*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53973*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53974*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53975*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53976*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53977*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53978*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53979*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5397a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5397b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5397c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5397d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5397e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5397f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53980*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53981*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53982*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53983*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53984*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53985*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53986*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53987*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53988*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53989*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5398a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5398b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5398c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5398d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5398e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5398f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53990*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53991*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53992*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53993*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53994*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53995*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53996*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53997*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53998*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53999*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5399a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5399b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5399c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5399d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5399e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5399f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539a0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539a1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539a2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539a3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539a4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539a5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539a6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539a7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539a8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539a9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539aa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539ab*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539ac*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539ad*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539ae*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539af*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539b0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539b1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539b2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539b3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539b4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539b5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539b6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539b7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539b8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539b9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539ba*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539bb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539bc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539bd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539be*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539bf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539c0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539c1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539c2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539c3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539c4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539c5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539c6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539c7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539c8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539c9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539ca*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539cb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539cc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539cd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539ce*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539cf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539d0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539d1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539d2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539d3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539d4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539d5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539d6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539d7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539d8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539d9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539da*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539db*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539dc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539dd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539de*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539df*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539e0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539e1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539e2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539e3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539e4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539e5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539e6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539e7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539e8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539e9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539ea*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539eb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539ec*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539ed*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539ee*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539ef*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539f0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539f1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539f2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539f3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539f4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539f5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539f6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539f7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539f8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539f9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539fa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539fb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539fc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539fd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539fe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539ff*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a00*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a01*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a02*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a03*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a04*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a05*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a06*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a07*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a08*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a09*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a0a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a0b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a0c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a0d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a0e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a0f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a10*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a11*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a12*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a13*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a14*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a15*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a16*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a17*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a18*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a19*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a1a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a1b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a1c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a1d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a1e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a1f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a20*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a21*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a22*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a23*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a24*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a25*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a26*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a27*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a28*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a29*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a2a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a2b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a2c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a2d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a2e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a2f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a30*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a31*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a32*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a33*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a34*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a35*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a36*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a37*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a38*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a39*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a3a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a3b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a3c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a3d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a3e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a3f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a40*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a41*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a42*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a43*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a44*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a45*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a46*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a47*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a48*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a49*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a4a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a4b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a4c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a4d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a4e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a4f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a50*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a51*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a52*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a53*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a54*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a55*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a56*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a57*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a58*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a59*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a5a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a5b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a5c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a5d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a5e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a5f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a60*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a61*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a62*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a63*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a64*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a65*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a66*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a67*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a68*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a69*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a6a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a6b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a6c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a6d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a6e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a6f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a70*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a71*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a72*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a73*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a74*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a75*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a76*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a77*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a78*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a79*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a7a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a7b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a7c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a7d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a7e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a7f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a80*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a81*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a82*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a83*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a84*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a85*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a86*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a87*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a88*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a89*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a8a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a8b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a8c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a8d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a8e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a8f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a90*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a91*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a92*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a93*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a94*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a95*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a96*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a97*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a98*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a99*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a9a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a9b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a9c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a9d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a9e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a9f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aa0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aa1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aa2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aa3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aa4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aa5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aa6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aa7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aa8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aa9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aaa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aab*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aac*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aad*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aae*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aaf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ab0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ab1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ab2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ab3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ab4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ab5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ab6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ab7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ab8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ab9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aba*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53abb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53abc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53abd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53abe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53abf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ac0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ac1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ac2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ac3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ac4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ac5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ac6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ac7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ac8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ac9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aca*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53acb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53acc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53acd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ace*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53acf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ad0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ad1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ad2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ad3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ad4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ad5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ad6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ad7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ad8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ad9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ada*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53adb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53adc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53add*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ade*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53adf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ae0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ae1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ae2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ae3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ae4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ae5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ae6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ae7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ae8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ae9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aea*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aeb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aec*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aed*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aee*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aef*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53af0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53af1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53af2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53af3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53af4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53af5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53af6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53af7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53af8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53af9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53afa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53afb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53afc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53afd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53afe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aff*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b00*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b01*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b02*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b03*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b04*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b05*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b06*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b07*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b08*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b09*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b0a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b0b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b0c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b0d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b0e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b0f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b10*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b11*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b12*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b13*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b14*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b15*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b16*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b17*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b18*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b19*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b1a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b1b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b1c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b1d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b1e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b1f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b20*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b21*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b22*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b23*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b24*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b25*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b26*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b27*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b28*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b29*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b2a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b2b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b2c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b2d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b2e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b2f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b30*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b31*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b32*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b33*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b34*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b35*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b36*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b37*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b38*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b39*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b3a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b3b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b3c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b3d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b3e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b3f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b40*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b41*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b42*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b43*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b44*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b45*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b46*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b47*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b48*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b49*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b4a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b4b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b4c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b4d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b4e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b4f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b50*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b51*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b52*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b53*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b54*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b55*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b56*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b57*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b58*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b59*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b5a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b5b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b5c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b5d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b5e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b5f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b60*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b61*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b62*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b63*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b64*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b65*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b66*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b67*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b68*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b69*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b6a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b6b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b6c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b6d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b6e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b6f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b70*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b71*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b72*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b73*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b74*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b75*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b76*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b77*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b78*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b79*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b7a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b7b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b7c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b7d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b7e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b7f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b80*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b81*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b82*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b83*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b84*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b85*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b86*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b87*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b88*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b89*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b8a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b8b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b8c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b8d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b8e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b8f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b90*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b91*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b92*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b93*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b94*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b95*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b96*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b97*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b98*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b99*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b9a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b9b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b9c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b9d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b9e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b9f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ba0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ba1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ba2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ba3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ba4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ba5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ba6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ba7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ba8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ba9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53baa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bab*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bac*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bad*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bae*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53baf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bb0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bb1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bb2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bb3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bb4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bb5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bb6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bb7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bb8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bb9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bba*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bbb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bbc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bbd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bbe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bbf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bc0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bc1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bc2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bc3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bc4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bc5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bc6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bc7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bc8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bc9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bca*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bcb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bcc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bcd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bce*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bcf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bd0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bd1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bd2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bd3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bd4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bd5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bd6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bd7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bd8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bd9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bda*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bdb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bdc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bdd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bde*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bdf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53be0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53be1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53be2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53be3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53be4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53be5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53be6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53be7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53be8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53be9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bea*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53beb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bec*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bed*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bee*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bef*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bf0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bf1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bf2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bf3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bf4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bf5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bf6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bf7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bf8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bf9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bfa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bfb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bfc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bfd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bfe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bff*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c00*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c01*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c02*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c03*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c04*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c05*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c06*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c07*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c08*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c09*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c0a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c0b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c0c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c0d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c0e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c0f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c10*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c11*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c12*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c13*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c14*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c15*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c16*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c17*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c18*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c19*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c1a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c1b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c1c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c1d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c1e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c1f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c20*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c21*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c22*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c23*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c24*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c25*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c26*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c27*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c28*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c29*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c2a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c2b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c2c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c2d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c2e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c2f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c30*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c31*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c32*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c33*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c34*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c35*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c36*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c37*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c38*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c39*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c3a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c3b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c3c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c3d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c3e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c3f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c40*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c41*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c42*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c43*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c44*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c45*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c46*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c47*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c48*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c49*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c4a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c4b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c4c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c4d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c4e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c4f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c50*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c51*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c52*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c53*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c54*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c55*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c56*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c57*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c58*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c59*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c5a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c5b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c5c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c5d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c5e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c5f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c60*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c61*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c62*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c63*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c64*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c65*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c66*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c67*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c68*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c69*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c6a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c6b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c6c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c6d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c6e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c6f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c70*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c71*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c72*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c73*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c74*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c75*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c76*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c77*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c78*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c79*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c7a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c7b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c7c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c7d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c7e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c7f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c80*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c81*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c82*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c83*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c84*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c85*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c86*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c87*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c88*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c89*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c8a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c8b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c8c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c8d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c8e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c8f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c90*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c91*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c92*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c93*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c94*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c95*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c96*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c97*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c98*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c99*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c9a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c9b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c9c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c9d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c9e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c9f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ca0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ca1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ca2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ca3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ca4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ca5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ca6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ca7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ca8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ca9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53caa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cab*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cac*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cad*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cae*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53caf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cb0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cb1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cb2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cb3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cb4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cb5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cb6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cb7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cb8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cb9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cba*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cbb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cbc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cbd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cbe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cbf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cc0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cc1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cc2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cc3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cc4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cc5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cc6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cc7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cc8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cc9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cca*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ccb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ccc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ccd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cce*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ccf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cd0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cd1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cd2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cd3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cd4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cd5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cd6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cd7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cd8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cd9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cda*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cdb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cdc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cdd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cde*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cdf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ce0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ce1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ce2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ce3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ce4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ce5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ce6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ce7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ce8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ce9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cea*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ceb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cec*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ced*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cee*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cef*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cf0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cf1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cf2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cf3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cf4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cf5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cf6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cf7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cf8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cf9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cfa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cfb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cfc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cfd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cfe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cff*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d00*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d01*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d02*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d03*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d04*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d05*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d06*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d07*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d08*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d09*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d0a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d0b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d0c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d0d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d0e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d0f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d10*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d11*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d12*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d13*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d14*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d15*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d16*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d17*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d18*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d19*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d1a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d1b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d1c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d1d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d1e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d1f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d20*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d21*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d22*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d23*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d24*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d25*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d26*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d27*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d28*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d29*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d2a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d2b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d2c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d2d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d2e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d2f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d30*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d31*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d32*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d33*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d34*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d35*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d36*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d37*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d38*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d39*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d3a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d3b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d3c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d3d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d3e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d3f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d40*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d41*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d42*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d43*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d44*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d45*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d46*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d47*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d48*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d49*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d4a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d4b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d4c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d4d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d4e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d4f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d50*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d51*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d52*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d53*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d54*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d55*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d56*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d57*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d58*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d59*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d5a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d5b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d5c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d5d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d5e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d5f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d60*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d61*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d62*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d63*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d64*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d65*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d66*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d67*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d68*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d69*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d6a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d6b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d6c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d6d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d6e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d6f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d70*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d71*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d72*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d73*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d74*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d75*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d76*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d77*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d78*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d79*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d7a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d7b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d7c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d7d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d7e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d7f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d80*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d81*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d82*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d83*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d84*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d85*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d86*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d87*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d88*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d89*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d8a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d8b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d8c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d8d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d8e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d8f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d90*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d91*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d92*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d93*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d94*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d95*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d96*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d97*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d98*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d99*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d9a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d9b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d9c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d9d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d9e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d9f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53da0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53da1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53da2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53da3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53da4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53da5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53da6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53da7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53da8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53da9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53daa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dab*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dac*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dad*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dae*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53daf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53db0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53db1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53db2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53db3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53db4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53db5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53db6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53db7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53db8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53db9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dba*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dbb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dbc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dbd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dbe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dbf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dc0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dc1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dc2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dc3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dc4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dc5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dc6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dc7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dc8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dc9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dca*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dcb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dcc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dcd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dce*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dcf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dd0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dd1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dd2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dd3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dd4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dd5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dd6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dd7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dd8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dd9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dda*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ddb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ddc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ddd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dde*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ddf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53de0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53de1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53de2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53de3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53de4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53de5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53de6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53de7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53de8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53de9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dea*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53deb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dec*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ded*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dee*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53def*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53df0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53df1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53df2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53df3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53df4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53df5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53df6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53df7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53df8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53df9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dfa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dfb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dfc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dfd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dfe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dff*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e00*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e01*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e02*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e03*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e04*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e05*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e06*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e07*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e08*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e09*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e0a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e0b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e0c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e0d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e0e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e0f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e10*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e11*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e12*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e13*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e14*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e15*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e16*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e17*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e18*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e19*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e1a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e1b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e1c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e1d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e1e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e1f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e20*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e21*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e22*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e23*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e24*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e25*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e26*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e27*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e28*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e29*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e2a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e2b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e2c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e2d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e2e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e2f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e30*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e31*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e32*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e33*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e34*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e35*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e36*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e37*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e38*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e39*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e3a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e3b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e3c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e3d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e3e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e3f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e40*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e41*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e42*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e43*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e44*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e45*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e46*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e47*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e48*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e49*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e4a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e4b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e4c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e4d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e4e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e4f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e50*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e51*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e52*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e53*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e54*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e55*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e56*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e57*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e58*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e59*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e5a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e5b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e5c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e5d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e5e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e5f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e60*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e61*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e62*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e63*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e64*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e65*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e66*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e67*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e68*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e69*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e6a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e6b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e6c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e6d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e6e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e6f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e70*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e71*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e72*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e73*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e74*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e75*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e76*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e77*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e78*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e79*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e7a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e7b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e7c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e7d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e7e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e7f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e80*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e81*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e82*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e83*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e84*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e85*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e86*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e87*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e88*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e89*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e8a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e8b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e8c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e8d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e8e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e8f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e90*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e91*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e92*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e93*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e94*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e95*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e96*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e97*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e98*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e99*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e9a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e9b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e9c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e9d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e9e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e9f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ea0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ea1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ea2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ea3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ea4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ea5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ea6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ea7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ea8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ea9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eaa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eab*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eac*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ead*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eae*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eaf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eb0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eb1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eb2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eb3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eb4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eb5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eb6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eb7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eb8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eb9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eba*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ebb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ebc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ebd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ebe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ebf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ec0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ec1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ec2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ec3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ec4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ec5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ec6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ec7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ec8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ec9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eca*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ecb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ecc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ecd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ece*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ecf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ed0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ed1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ed2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ed3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ed4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ed5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ed6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ed7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ed8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ed9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eda*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53edb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53edc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53edd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ede*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53edf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ee0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ee1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ee2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ee3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ee4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ee5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ee6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ee7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ee8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ee9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eea*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eeb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eec*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eed*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eee*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eef*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ef0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ef1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ef2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ef3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ef4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ef5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ef6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ef7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ef8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ef9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53efa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53efb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53efc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53efd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53efe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eff*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f00*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f01*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f02*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f03*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f04*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f05*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f06*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f07*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f08*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f09*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f0a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f0b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f0c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f0d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f0e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f0f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f10*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f11*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f12*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f13*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f14*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f15*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f16*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f17*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f18*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f19*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f1a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f1b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f1c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f1d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f1e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f1f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f20*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f21*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f22*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f23*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f24*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f25*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f26*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f27*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f28*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f29*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f2a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f2b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f2c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f2d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f2e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f2f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f30*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f31*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f32*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f33*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f34*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f35*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f36*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f37*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f38*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f39*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f40*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f41*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f42*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f43*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f44*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f45*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f46*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f47*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f48*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f49*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f50*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f51*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f52*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f53*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f54*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f55*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f56*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f57*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f58*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f59*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f60*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f61*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f62*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f63*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f64*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f65*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f66*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f67*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f68*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f69*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f70*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f71*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f72*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f73*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f74*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f75*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f76*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f77*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f78*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f79*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f80*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f81*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f82*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f83*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f84*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f85*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f86*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f87*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f88*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f89*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f90*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f91*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f92*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f93*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f94*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f95*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f96*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f97*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f98*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f99*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53faa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fab*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fac*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fad*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fae*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53faf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fba*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fbb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fbc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fbd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fbe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fbf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fca*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fcb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fcc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fcd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fce*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fcf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fda*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fdb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fdc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fdd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fde*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fdf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fea*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53feb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fec*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fed*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fee*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fef*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ffa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ffb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ffc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ffd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ffe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fff*4 +0x02000000,0x0); + +reg_write( DDR_REG_BASE + 0x000d0000*4+0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000d0000*4+0x02000000 , 0x00000000 ); + + +reg_write( DDR_REG_BASE +0x54000*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54001*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54002*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54003*4 +0x02000000,0xc80); +reg_write( DDR_REG_BASE +0x54004*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x54005*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54006*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x54007*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54008*4 +0x02000000,0x61); +reg_write( DDR_REG_BASE +0x54009*4 +0x02000000,0xc8); +reg_write( DDR_REG_BASE +0x5400a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5400b*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x5400c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5400d*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5400e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5400f*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x54010*4 +0x02000000,0x8020); +reg_write( DDR_REG_BASE +0x54011*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54012*4 +0x02000000,0x110); +reg_write( DDR_REG_BASE +0x54013*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54014*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54015*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54016*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54017*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54018*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54019*4 +0x02000000,0x2d54); +reg_write( DDR_REG_BASE +0x5401a*4 +0x02000000,0x33); +//iteration +//MR11 low-DQ/high-CA ODT: 2:120 3:80 4:60 5:70 6:40 +reg_write( DDR_REG_BASE +0x5401b*4 +0x02000000,0x4d44); +reg_write( DDR_REG_BASE +0x5401c*4 +0x02000000,0x4f08); +reg_write( DDR_REG_BASE +0x5401d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5401e*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5401f*4 +0x02000000,0x2d54); +reg_write( DDR_REG_BASE +0x54020*4 +0x02000000,0x33); +//iteration +//MR11 low-DQ/high-CA ODT: 2:120 3:80 4:60 5:70 6:40 +reg_write( DDR_REG_BASE +0x54021*4 +0x02000000,0x4d44); +reg_write( DDR_REG_BASE +0x54022*4 +0x02000000,0x4f08); +reg_write( DDR_REG_BASE +0x54023*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54024*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x54025*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54026*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54027*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54028*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54029*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5402a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5402b*4 +0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x5402c*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5402d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5402e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5402f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54030*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54031*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54032*4 +0x02000000,0x5400); +reg_write( DDR_REG_BASE +0x54033*4 +0x02000000,0x332d); +//iteration +//MR11 low-DQ/high-CA ODT: 2:120 3:80 4:60 5:70 6:40 +reg_write( DDR_REG_BASE +0x54034*4 +0x02000000,0x4400); +reg_write( DDR_REG_BASE +0x54035*4 +0x02000000,0x84d); +reg_write( DDR_REG_BASE +0x54036*4 +0x02000000,0x4f); +reg_write( DDR_REG_BASE +0x54037*4 +0x02000000,0x400); +reg_write( DDR_REG_BASE +0x54038*4 +0x02000000,0x5400); +reg_write( DDR_REG_BASE +0x54039*4 +0x02000000,0x332d); +//iteration +//MR11 low-DQ/high-CA ODT: 2:120 3:80 4:60 5:70 6:40 +reg_write( DDR_REG_BASE +0x5403a*4 +0x02000000,0x4400); +reg_write( DDR_REG_BASE +0x5403b*4 +0x02000000,0x84d); +reg_write( DDR_REG_BASE +0x5403c*4 +0x02000000,0x4f); +reg_write( DDR_REG_BASE +0x5403d*4 +0x02000000,0x400); +reg_write( DDR_REG_BASE +0x5403e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5403f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54040*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54041*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54042*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54043*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54044*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54045*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54046*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54047*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54048*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54049*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54050*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54051*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54052*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54053*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54054*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54055*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54056*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54057*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54058*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54059*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54060*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54061*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54062*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54063*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54064*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54065*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54066*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54067*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54068*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54069*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54070*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54071*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54072*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54073*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54074*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54075*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54076*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54077*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54078*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54079*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54080*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54081*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54082*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54083*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54084*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54085*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54086*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54087*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54088*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54089*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54090*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54091*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54092*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54093*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54094*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54095*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54096*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54097*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54098*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54099*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540aa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ab*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ac*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ad*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ae*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540af*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ba*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540bb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540bc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540bd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540be*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540bf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ca*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540cb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540cc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540cd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ce*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540cf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540da*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540db*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540dc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540dd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540de*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540df*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ea*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540eb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ec*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ed*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ee*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ef*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540fa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540fb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540fc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540fd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540fe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ff*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54100*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54101*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54102*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54103*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54104*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54105*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54106*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54107*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54108*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54109*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54110*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54111*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54112*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54113*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54114*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54115*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54116*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54117*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54118*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54119*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54120*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54121*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54122*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54123*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54124*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54125*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54126*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54127*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54128*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54129*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54130*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54131*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54132*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54133*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54134*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54135*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54136*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54137*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54138*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54139*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54140*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54141*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54142*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54143*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54144*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54145*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54146*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54147*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54148*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54149*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54150*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54151*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54152*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54153*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54154*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54155*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54156*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54157*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54158*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54159*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54160*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54161*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54162*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54163*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54164*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54165*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54166*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54167*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54168*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54169*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54170*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54171*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54172*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54173*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54174*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54175*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54176*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54177*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54178*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54179*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54180*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54181*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54182*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54183*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54184*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54185*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54186*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54187*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54188*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54189*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54190*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54191*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54192*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54193*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54194*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54195*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54196*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54197*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54198*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54199*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541aa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ab*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ac*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ad*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ae*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541af*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ba*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541bb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541bc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541bd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541be*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541bf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ca*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541cb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541cc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541cd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ce*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541cf*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541da*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541db*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541dc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541dd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541de*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541df*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ea*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541eb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ec*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ed*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ee*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ef*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f1*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f2*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f3*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f4*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f5*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f6*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f7*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f8*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f9*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541fa*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541fb*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541fc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541fd*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541fe*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ff*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54200*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54201*4 +0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x54202*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54203*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54204*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54205*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54206*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54207*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54208*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x54209*4 +0x02000000,0x14); +reg_write( DDR_REG_BASE +0x5420a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5420b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5420c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5420d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5420e*4 +0x02000000,0x14a); +reg_write( DDR_REG_BASE +0x5420f*4 +0x02000000,0x181); +reg_write( DDR_REG_BASE +0x54210*4 +0x02000000,0x118); +reg_write( DDR_REG_BASE +0x54211*4 +0x02000000,0x118); +reg_write( DDR_REG_BASE +0x54212*4 +0x02000000,0x16f); +reg_write( DDR_REG_BASE +0x54213*4 +0x02000000,0x16f); +reg_write( DDR_REG_BASE +0x54214*4 +0x02000000,0x159); +reg_write( DDR_REG_BASE +0x54215*4 +0x02000000,0x181); +reg_write( DDR_REG_BASE +0x54216*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x54217*4 +0x02000000,0x120); +reg_write( DDR_REG_BASE +0x54218*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54219*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5421a*4 +0x02000000,0x701c); +reg_write( DDR_REG_BASE +0x5421b*4 +0x02000000,0x61a8); +reg_write( DDR_REG_BASE +0x5421c*4 +0x02000000,0x35ac); +reg_write( DDR_REG_BASE +0x5421d*4 +0x02000000,0x35ac); +reg_write( DDR_REG_BASE +0x5421e*4 +0x02000000,0x125c); +reg_write( DDR_REG_BASE +0x5421f*4 +0x02000000,0x125c); +reg_write( DDR_REG_BASE +0x54220*4 +0x02000000,0xc738); +reg_write( DDR_REG_BASE +0x54221*4 +0x02000000,0xb0f4); +reg_write( DDR_REG_BASE +0x54222*4 +0x02000000,0x6590); +reg_write( DDR_REG_BASE +0x54223*4 +0x02000000,0x6590); +reg_write( DDR_REG_BASE +0x54224*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54225*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54226*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54227*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54228*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54229*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5422a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5422b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5422c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5422d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5422e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5422f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54230*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54231*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54232*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54233*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54234*4 +0x02000000,0x9f38); +reg_write( DDR_REG_BASE +0x54235*4 +0x02000000,0x58); +reg_write( DDR_REG_BASE +0x54236*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54237*4 +0x02000000,0x321e); +reg_write( DDR_REG_BASE +0x54238*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x54239*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5423a*4 +0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x5423b*4 +0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x5423c*4 +0x02000000,0xf0); +reg_write( DDR_REG_BASE +0x5423d*4 +0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5423e*4 +0x02000000,0x78); +reg_write( DDR_REG_BASE +0x5423f*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x54240*4 +0x02000000,0x50); +reg_write( DDR_REG_BASE +0x54241*4 +0x02000000,0x43); +reg_write( DDR_REG_BASE +0x54242*4 +0x02000000,0x3c); +reg_write( DDR_REG_BASE +0x54243*4 +0x02000000,0x35); +reg_write( DDR_REG_BASE +0x54244*4 +0x02000000,0x30); +reg_write( DDR_REG_BASE +0x54245*4 +0x02000000,0x2c); +reg_write( DDR_REG_BASE +0x54246*4 +0x02000000,0x28); +reg_write( DDR_REG_BASE +0x54247*4 +0x02000000,0x25); +reg_write( DDR_REG_BASE +0x54248*4 +0x02000000,0x22); +reg_write( DDR_REG_BASE +0x54249*4 +0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5424a*4 +0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x5424b*4 +0x02000000,0x1c); +reg_write( DDR_REG_BASE +0x5424c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5424d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5424e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5424f*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54250*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54251*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54252*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54253*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54254*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x54255*4 +0x02000000,0x302); +reg_write( DDR_REG_BASE +0x54256*4 +0x02000000,0x706); +reg_write( DDR_REG_BASE +0x54257*4 +0x02000000,0xb0a); +reg_write( DDR_REG_BASE +0x54258*4 +0x02000000,0xf0e); +reg_write( DDR_REG_BASE +0x54259*4 +0x02000000,0x1b1a); +reg_write( DDR_REG_BASE +0x5425a*4 +0x02000000,0x1f1e); +reg_write( DDR_REG_BASE +0x5425b*4 +0x02000000,0x3b3a); +reg_write( DDR_REG_BASE +0x5425c*4 +0x02000000,0x3f3e); +reg_write( DDR_REG_BASE +0x5425d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5425e*4 +0x02000000,0x2820); +reg_write( DDR_REG_BASE +0x5425f*4 +0x02000000,0x140f); +reg_write( DDR_REG_BASE +0x54260*4 +0x02000000,0x1f02); +reg_write( DDR_REG_BASE +0x54261*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54262*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54263*4 +0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x54264*4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x54265*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x54266*4 +0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x54267*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54268*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54269*4 +0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x5426a*4 +0x02000000,0x1f4); +reg_write( DDR_REG_BASE +0x5426b*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5426c*4 +0x02000000,0xb900); +reg_write( DDR_REG_BASE +0x5426d*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5426e*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5426f*4 +0x02000000,0xba00); +reg_write( DDR_REG_BASE +0x54270*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54271*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54272*4 +0x02000000,0xbb00); +reg_write( DDR_REG_BASE +0x54273*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54274*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54275*4 +0x02000000,0x100); +reg_write( DDR_REG_BASE +0x54276*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x54277*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54278*4 +0x02000000,0x1300); +reg_write( DDR_REG_BASE +0x54279*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5427a*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5427b*4 +0x02000000,0xf900); +reg_write( DDR_REG_BASE +0x5427c*4 +0x02000000,0x4f0); +reg_write( DDR_REG_BASE +0x5427d*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5427e*4 +0x02000000,0xfa02); +reg_write( DDR_REG_BASE +0x5427f*4 +0x02000000,0x4f0); +reg_write( DDR_REG_BASE +0x54280*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54281*4 +0x02000000,0xfb00); +reg_write( DDR_REG_BASE +0x54282*4 +0x02000000,0x4f0); +reg_write( DDR_REG_BASE +0x54283*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54284*4 +0x02000000,0x6004); +reg_write( DDR_REG_BASE +0x54285*4 +0x02000000,0x7f0); +reg_write( DDR_REG_BASE +0x54286*4 +0x02000000,0x800); +reg_write( DDR_REG_BASE +0x54287*4 +0x02000000,0x6500); +reg_write( DDR_REG_BASE +0x54288*4 +0x02000000,0x7f0); +reg_write( DDR_REG_BASE +0x54289*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5428a*4 +0x02000000,0x6200); +reg_write( DDR_REG_BASE +0x5428b*4 +0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x5428c*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5428d*4 +0x02000000,0x200); +reg_write( DDR_REG_BASE +0x5428e*4 +0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x5428f*4 +0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x54290*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x54291*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54292*4 +0x02000000,0x20d); +reg_write( DDR_REG_BASE +0x54293*4 +0x02000000,0x301); +reg_write( DDR_REG_BASE +0x54294*4 +0x02000000,0xc0b); +reg_write( DDR_REG_BASE +0x54295*4 +0x02000000,0x160e); +reg_write( DDR_REG_BASE +0x54296*4 +0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x54297*4 +0x02000000,0x1811); +reg_write( DDR_REG_BASE +0x54298*4 +0x02000000,0xc06); +reg_write( DDR_REG_BASE +0x54299*4 +0x02000000,0x1610); +reg_write( DDR_REG_BASE +0x5429a*4 +0x02000000,0x201c); +reg_write( DDR_REG_BASE +0x5429b*4 +0x02000000,0x2824); +reg_write( DDR_REG_BASE +0x5429c*4 +0x02000000,0xc06); +reg_write( DDR_REG_BASE +0x5429d*4 +0x02000000,0x1812); +reg_write( DDR_REG_BASE +0x5429e*4 +0x02000000,0x241e); +reg_write( DDR_REG_BASE +0x5429f*4 +0x02000000,0x2c28); +reg_write( DDR_REG_BASE +0x542a0*4 +0x02000000,0xa06); +reg_write( DDR_REG_BASE +0x542a1*4 +0x02000000,0x140e); +reg_write( DDR_REG_BASE +0x542a2*4 +0x02000000,0x1c18); +reg_write( DDR_REG_BASE +0x542a3*4 +0x02000000,0x2420); +reg_write( DDR_REG_BASE +0x542a4*4 +0x02000000,0xa06); +reg_write( DDR_REG_BASE +0x542a5*4 +0x02000000,0x1610); +reg_write( DDR_REG_BASE +0x542a6*4 +0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x542a7*4 +0x02000000,0x2824); +reg_write( DDR_REG_BASE +0x542a8*4 +0x02000000,0x6e); +reg_write( DDR_REG_BASE +0x542a9*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x542aa*4 +0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542ab*4 +0x02000000,0xfd); +reg_write( DDR_REG_BASE +0x542ac*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x542ad*4 +0x02000000,0xf); +reg_write( DDR_REG_BASE +0x542ae*4 +0x02000000,0x60); +reg_write( DDR_REG_BASE +0x542af*4 +0x02000000,0x7); +reg_write( DDR_REG_BASE +0x542b0*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542b1*4 +0x02000000,0xe8); +reg_write( DDR_REG_BASE +0x542b2*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x542b3*4 +0x02000000,0xff); +reg_write( DDR_REG_BASE +0x542b4*4 +0x02000000,0xfc); +reg_write( DDR_REG_BASE +0x542b5*4 +0x02000000,0x4); +reg_write( DDR_REG_BASE +0x542b6*4 +0x02000000,0x404); +reg_write( DDR_REG_BASE +0x542b7*4 +0x02000000,0x3a); +reg_write( DDR_REG_BASE +0x542b8*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x542b9*4 +0x02000000,0x2); +reg_write( DDR_REG_BASE +0x542ba*4 +0x02000000,0x11); +reg_write( DDR_REG_BASE +0x542bb*4 +0x02000000,0x7); +reg_write( DDR_REG_BASE +0x542bc*4 +0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542bd*4 +0x02000000,0x0); + + +reg_write( DDR_REG_BASE + 0x000d0000*4+0x02000000 , 0x00000001 ); + + + +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000d0099*4 +0x02000000 , 0x00000009 ); +reg_write( DDR_REG_BASE + 0x000d0099*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000d0099*4 +0x02000000 , 0x00000000 ); + + +while((train_data&0x7) !=0x07) { + + reg_read ( DDR_REG_BASE + 0x000d0004*4 +0x02000000 , data ); + while((data&0x1) !=0x0) { + reg_read ( DDR_REG_BASE + 0x000d0004*4 +0x02000000 , data ); + } + + + + reg_read ( DDR_REG_BASE + 0x000d0032*4 +0x02000000 , train_data ); + switch(train_data) + { + case 0x00000000: printf("%08X: PMU Major Msg: End of initialization \n",train_data);break; + case 0x00000001: printf("%08X: PMU Major Msg: End of fine write leveling \n",train_data);break; + case 0x00000002: printf("%08X: PMU Major Msg: End of read enable training \n",train_data);break; + case 0x00000003: printf("%08X: PMU Major Msg: End of read delay center optimization \n",train_data);break; + case 0x00000004: printf("%08X: PMU Major Msg: End of write delay center optimization \n",train_data);break; + case 0x00000005: printf("%08X: PMU Major Msg: End of 2D read delay/voltage center optimization \n",train_data);break; + case 0x00000006: printf("%08X: PMU Major Msg: End of 2D write delay /voltage center optimization \n",train_data);break; + case 0x00000007: printf("%08X: PMU Major Msg: Firmware run has completed \n",train_data);break; + case 0x00000008: printf("%08X: PMU Major Msg: Enter streaming message mode \n",train_data);break; + case 0x00000009: printf("%08X: PMU Major Msg: End of max read latency training \n",train_data);break; + case 0x0000000a: printf("%08X: PMU Major Msg: End of read dq deskew training \n",train_data);break; + case 0x0000000b: printf("%08X: PMU Major Msg: End of LCDL offset calibration \n",train_data);break; + case 0x0000000c: printf("%08X: PMU Major Msg: End of LRDIMM Specific training (DWL, MREP, MRD and MWD) \n",train_data);break; + case 0x0000000d: printf("%08X: PMU Major Msg: End of CA training \n",train_data);break; + case 0x000000fd: printf("%08X: PMU Major Msg: End of MPR read delay center optimization \n",train_data);break; + case 0x000000fe: printf("%08X: PMU Major Msg: End of Write leveling coarse delay \n",train_data);break; + case 0x000000ff: printf("%08X: PMU Major Msg: FATAL ERROR. \n",train_data);break; + default: printf("%08X: PMU Major Msg: Un-recognized message... ! \n",train_data);break; + } + + + reg_write( DDR_REG_BASE + 0x000d0031*4 +0x02000000 , 0x00000000 ); + reg_read ( DDR_REG_BASE + 0x000d0004*4 +0x02000000 , data ); + while((data&0x1) ==0x0) { + reg_read ( DDR_REG_BASE + 0x000d0004*4 +0x02000000 , data ); + } + reg_write( DDR_REG_BASE + 0x000d0031*4 +0x02000000 , 0x00000001 ); + +} + +train_data=0; + + + + +reg_write( DDR_REG_BASE + 0x000d0099*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000000 ); + +/////////////////////////////2d training end///////////////////////////////////////////// + + +reg_write( DDR_REG_BASE + 0x00090000*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x00090001*4 +0x02000000 , 0x00000400 ); +reg_write( DDR_REG_BASE + 0x00090002*4 +0x02000000 , 0x0000010e ); +reg_write( DDR_REG_BASE + 0x00090003*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090004*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090005*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090029*4 +0x02000000 , 0x0000000b ); +reg_write( DDR_REG_BASE + 0x0009002a*4 +0x02000000 , 0x00000480 ); +reg_write( DDR_REG_BASE + 0x0009002b*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009002c*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x0009002d*4 +0x02000000 , 0x00000448 ); +reg_write( DDR_REG_BASE + 0x0009002e*4 +0x02000000 , 0x00000139 ); +reg_write( DDR_REG_BASE + 0x0009002f*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090030*4 +0x02000000 , 0x00000478 ); +reg_write( DDR_REG_BASE + 0x00090031*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090032*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090033*4 +0x02000000 , 0x000000e8 ); +reg_write( DDR_REG_BASE + 0x00090034*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090035*4 +0x02000000 , 0x00000002 ); +reg_write( DDR_REG_BASE + 0x00090036*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x00090037*4 +0x02000000 , 0x00000139 ); +reg_write( DDR_REG_BASE + 0x00090038*4 +0x02000000 , 0x0000000b ); +reg_write( DDR_REG_BASE + 0x00090039*4 +0x02000000 , 0x000007c0 ); +reg_write( DDR_REG_BASE + 0x0009003a*4 +0x02000000 , 0x00000139 ); +reg_write( DDR_REG_BASE + 0x0009003b*4 +0x02000000 , 0x00000044 ); +reg_write( DDR_REG_BASE + 0x0009003c*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x0009003d*4 +0x02000000 , 0x00000159 ); +reg_write( DDR_REG_BASE + 0x0009003e*4 +0x02000000 , 0x0000014f ); +reg_write( DDR_REG_BASE + 0x0009003f*4 +0x02000000 , 0x00000630 ); +reg_write( DDR_REG_BASE + 0x00090040*4 +0x02000000 , 0x00000159 ); +reg_write( DDR_REG_BASE + 0x00090041*4 +0x02000000 , 0x00000047 ); +reg_write( DDR_REG_BASE + 0x00090042*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090043*4 +0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x00090044*4 +0x02000000 , 0x0000004f ); +reg_write( DDR_REG_BASE + 0x00090045*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090046*4 +0x02000000 , 0x00000179 ); +reg_write( DDR_REG_BASE + 0x00090047*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090048*4 +0x02000000 , 0x000000e0 ); +reg_write( DDR_REG_BASE + 0x00090049*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009004a*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009004b*4 +0x02000000 , 0x000007c8 ); +reg_write( DDR_REG_BASE + 0x0009004c*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009004d*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009004e*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x0009004f*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090050*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090051*4 +0x02000000 , 0x0000045a ); +reg_write( DDR_REG_BASE + 0x00090052*4 +0x02000000 , 0x00000009 ); +reg_write( DDR_REG_BASE + 0x00090053*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090054*4 +0x02000000 , 0x00000448 ); +reg_write( DDR_REG_BASE + 0x00090055*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090056*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x00090057*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090058*4 +0x02000000 , 0x00000179 ); +reg_write( DDR_REG_BASE + 0x00090059*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x0009005a*4 +0x02000000 , 0x00000618 ); +reg_write( DDR_REG_BASE + 0x0009005b*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009005c*4 +0x02000000 , 0x000040c0 ); +reg_write( DDR_REG_BASE + 0x0009005d*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x0009005e*4 +0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x0009005f*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090060*4 +0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00090061*4 +0x02000000 , 0x00000048 ); +reg_write( DDR_REG_BASE + 0x00090062*4 +0x02000000 , 0x00004040 ); +reg_write( DDR_REG_BASE + 0x00090063*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090064*4 +0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x00090065*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090066*4 +0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00090067*4 +0x02000000 , 0x00000048 ); +reg_write( DDR_REG_BASE + 0x00090068*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x00090069*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x0009006a*4 +0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x0009006b*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x0009006c*4 +0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x0009006d*4 +0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x0009006e*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009006f*4 +0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00090070*4 +0x02000000 , 0x00000078 ); +reg_write( DDR_REG_BASE + 0x00090071*4 +0x02000000 , 0x00000549 ); +reg_write( DDR_REG_BASE + 0x00090072*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090073*4 +0x02000000 , 0x00000159 ); +reg_write( DDR_REG_BASE + 0x00090074*4 +0x02000000 , 0x00000d49 ); +reg_write( DDR_REG_BASE + 0x00090075*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090076*4 +0x02000000 , 0x00000159 ); +reg_write( DDR_REG_BASE + 0x00090077*4 +0x02000000 , 0x0000094a ); +reg_write( DDR_REG_BASE + 0x00090078*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090079*4 +0x02000000 , 0x00000159 ); +reg_write( DDR_REG_BASE + 0x0009007a*4 +0x02000000 , 0x00000441 ); +reg_write( DDR_REG_BASE + 0x0009007b*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x0009007c*4 +0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x0009007d*4 +0x02000000 , 0x00000042 ); +reg_write( DDR_REG_BASE + 0x0009007e*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x0009007f*4 +0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x00090080*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00090081*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090082*4 +0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x00090083*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090084*4 +0x02000000 , 0x000000e0 ); +reg_write( DDR_REG_BASE + 0x00090085*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090086*4 +0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x00090087*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x00090088*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090089*4 +0x02000000 , 0x00000009 ); +reg_write( DDR_REG_BASE + 0x0009008a*4 +0x02000000 , 0x000003c0 ); +reg_write( DDR_REG_BASE + 0x0009008b*4 +0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x0009008c*4 +0x02000000 , 0x00000009 ); +reg_write( DDR_REG_BASE + 0x0009008d*4 +0x02000000 , 0x000003c0 ); +reg_write( DDR_REG_BASE + 0x0009008e*4 +0x02000000 , 0x00000159 ); +reg_write( DDR_REG_BASE + 0x0009008f*4 +0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x00090090*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x00090091*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090092*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090093*4 +0x02000000 , 0x000003c0 ); +reg_write( DDR_REG_BASE + 0x00090094*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090095*4 +0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x00090096*4 +0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00090097*4 +0x02000000 , 0x00000048 ); +reg_write( DDR_REG_BASE + 0x00090098*4 +0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x00090099*4 +0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x0009009a*4 +0x02000000 , 0x00000058 ); +reg_write( DDR_REG_BASE + 0x0009009b*4 +0x02000000 , 0x0000000b ); +reg_write( DDR_REG_BASE + 0x0009009c*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x0009009d*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009009e*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x0009009f*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000900a0*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x000900a1*4 +0x02000000 , 0x00000005 ); +reg_write( DDR_REG_BASE + 0x000900a2*4 +0x02000000 , 0x000007c0 ); +reg_write( DDR_REG_BASE + 0x000900a3*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00040000*4 +0x02000000 , 0x00000811 ); +reg_write( DDR_REG_BASE + 0x00040020*4 +0x02000000 , 0x00000880 ); +reg_write( DDR_REG_BASE + 0x00040040*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040060*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040001*4 +0x02000000 , 0x00004008 ); +reg_write( DDR_REG_BASE + 0x00040021*4 +0x02000000 , 0x00000083 ); +reg_write( DDR_REG_BASE + 0x00040041*4 +0x02000000 , 0x0000004f ); +reg_write( DDR_REG_BASE + 0x00040061*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040002*4 +0x02000000 , 0x00004040 ); +reg_write( DDR_REG_BASE + 0x00040022*4 +0x02000000 , 0x00000083 ); +reg_write( DDR_REG_BASE + 0x00040042*4 +0x02000000 , 0x00000051 ); +reg_write( DDR_REG_BASE + 0x00040062*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040003*4 +0x02000000 , 0x00000811 ); +reg_write( DDR_REG_BASE + 0x00040023*4 +0x02000000 , 0x00000880 ); +reg_write( DDR_REG_BASE + 0x00040043*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040063*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040004*4 +0x02000000 , 0x00000720 ); +reg_write( DDR_REG_BASE + 0x00040024*4 +0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00040044*4 +0x02000000 , 0x00001740 ); +reg_write( DDR_REG_BASE + 0x00040064*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040005*4 +0x02000000 , 0x00000016 ); +reg_write( DDR_REG_BASE + 0x00040025*4 +0x02000000 , 0x00000083 ); +reg_write( DDR_REG_BASE + 0x00040045*4 +0x02000000 , 0x0000004b ); +reg_write( DDR_REG_BASE + 0x00040065*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040006*4 +0x02000000 , 0x00000716 ); +reg_write( DDR_REG_BASE + 0x00040026*4 +0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00040046*4 +0x02000000 , 0x00002001 ); +reg_write( DDR_REG_BASE + 0x00040066*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040007*4 +0x02000000 , 0x00000716 ); +reg_write( DDR_REG_BASE + 0x00040027*4 +0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00040047*4 +0x02000000 , 0x00002800 ); +reg_write( DDR_REG_BASE + 0x00040067*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040008*4 +0x02000000 , 0x00000716 ); +reg_write( DDR_REG_BASE + 0x00040028*4 +0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00040048*4 +0x02000000 , 0x00000f00 ); +reg_write( DDR_REG_BASE + 0x00040068*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040009*4 +0x02000000 , 0x00000720 ); +reg_write( DDR_REG_BASE + 0x00040029*4 +0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00040049*4 +0x02000000 , 0x00001400 ); +reg_write( DDR_REG_BASE + 0x00040069*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004000a*4 +0x02000000 , 0x00000e08 ); +reg_write( DDR_REG_BASE + 0x0004002a*4 +0x02000000 , 0x00000c15 ); +reg_write( DDR_REG_BASE + 0x0004004a*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004006a*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004000b*4 +0x02000000 , 0x00000625 ); +reg_write( DDR_REG_BASE + 0x0004002b*4 +0x02000000 , 0x00000015 ); +reg_write( DDR_REG_BASE + 0x0004004b*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004006b*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004000c*4 +0x02000000 , 0x00004028 ); +reg_write( DDR_REG_BASE + 0x0004002c*4 +0x02000000 , 0x00000080 ); +reg_write( DDR_REG_BASE + 0x0004004c*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004006c*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004000d*4 +0x02000000 , 0x00000e08 ); +reg_write( DDR_REG_BASE + 0x0004002d*4 +0x02000000 , 0x00000c1a ); +reg_write( DDR_REG_BASE + 0x0004004d*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004006d*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004000e*4 +0x02000000 , 0x00000625 ); +reg_write( DDR_REG_BASE + 0x0004002e*4 +0x02000000 , 0x0000001a ); +reg_write( DDR_REG_BASE + 0x0004004e*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004006e*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004000f*4 +0x02000000 , 0x00004040 ); +reg_write( DDR_REG_BASE + 0x0004002f*4 +0x02000000 , 0x00000080 ); +reg_write( DDR_REG_BASE + 0x0004004f*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004006f*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040010*4 +0x02000000 , 0x00002604 ); +reg_write( DDR_REG_BASE + 0x00040030*4 +0x02000000 , 0x00000015 ); +reg_write( DDR_REG_BASE + 0x00040050*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040070*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040011*4 +0x02000000 , 0x00000708 ); +reg_write( DDR_REG_BASE + 0x00040031*4 +0x02000000 , 0x00000005 ); +reg_write( DDR_REG_BASE + 0x00040051*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040071*4 +0x02000000 , 0x00002002 ); +reg_write( DDR_REG_BASE + 0x00040012*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00040032*4 +0x02000000 , 0x00000080 ); +reg_write( DDR_REG_BASE + 0x00040052*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040072*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040013*4 +0x02000000 , 0x00002604 ); +reg_write( DDR_REG_BASE + 0x00040033*4 +0x02000000 , 0x0000001a ); +reg_write( DDR_REG_BASE + 0x00040053*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040073*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040014*4 +0x02000000 , 0x00000708 ); +reg_write( DDR_REG_BASE + 0x00040034*4 +0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x00040054*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040074*4 +0x02000000 , 0x00002002 ); +reg_write( DDR_REG_BASE + 0x00040015*4 +0x02000000 , 0x00004040 ); +reg_write( DDR_REG_BASE + 0x00040035*4 +0x02000000 , 0x00000080 ); +reg_write( DDR_REG_BASE + 0x00040055*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040075*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040016*4 +0x02000000 , 0x0000060a ); +reg_write( DDR_REG_BASE + 0x00040036*4 +0x02000000 , 0x00000015 ); +reg_write( DDR_REG_BASE + 0x00040056*4 +0x02000000 , 0x00001200 ); +reg_write( DDR_REG_BASE + 0x00040076*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040017*4 +0x02000000 , 0x0000061a ); +reg_write( DDR_REG_BASE + 0x00040037*4 +0x02000000 , 0x00000015 ); +reg_write( DDR_REG_BASE + 0x00040057*4 +0x02000000 , 0x00001300 ); +reg_write( DDR_REG_BASE + 0x00040077*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040018*4 +0x02000000 , 0x0000060a ); +reg_write( DDR_REG_BASE + 0x00040038*4 +0x02000000 , 0x0000001a ); +reg_write( DDR_REG_BASE + 0x00040058*4 +0x02000000 , 0x00001200 ); +reg_write( DDR_REG_BASE + 0x00040078*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040019*4 +0x02000000 , 0x00000642 ); +reg_write( DDR_REG_BASE + 0x00040039*4 +0x02000000 , 0x0000001a ); +reg_write( DDR_REG_BASE + 0x00040059*4 +0x02000000 , 0x00001300 ); +reg_write( DDR_REG_BASE + 0x00040079*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004001a*4 +0x02000000 , 0x00004808 ); +reg_write( DDR_REG_BASE + 0x0004003a*4 +0x02000000 , 0x00000880 ); +reg_write( DDR_REG_BASE + 0x0004005a*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004007a*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900a4*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900a5*4 +0x02000000 , 0x00000790 ); +reg_write( DDR_REG_BASE + 0x000900a6*4 +0x02000000 , 0x0000011a ); +reg_write( DDR_REG_BASE + 0x000900a7*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900a8*4 +0x02000000 , 0x000007aa ); +reg_write( DDR_REG_BASE + 0x000900a9*4 +0x02000000 , 0x0000002a ); +reg_write( DDR_REG_BASE + 0x000900aa*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000900ab*4 +0x02000000 , 0x000007b2 ); +reg_write( DDR_REG_BASE + 0x000900ac*4 +0x02000000 , 0x0000002a ); +reg_write( DDR_REG_BASE + 0x000900ad*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900ae*4 +0x02000000 , 0x000007c8 ); +reg_write( DDR_REG_BASE + 0x000900af*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x000900b0*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000900b1*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000900b2*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x000900b3*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000900b4*4 +0x02000000 , 0x000002a8 ); +reg_write( DDR_REG_BASE + 0x000900b5*4 +0x02000000 , 0x00000129 ); +reg_write( DDR_REG_BASE + 0x000900b6*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900b7*4 +0x02000000 , 0x00000370 ); +reg_write( DDR_REG_BASE + 0x000900b8*4 +0x02000000 , 0x00000129 ); +reg_write( DDR_REG_BASE + 0x000900b9*4 +0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x000900ba*4 +0x02000000 , 0x000003c8 ); +reg_write( DDR_REG_BASE + 0x000900bb*4 +0x02000000 , 0x000001a9 ); +reg_write( DDR_REG_BASE + 0x000900bc*4 +0x02000000 , 0x0000000c ); +reg_write( DDR_REG_BASE + 0x000900bd*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x000900be*4 +0x02000000 , 0x00000199 ); +reg_write( DDR_REG_BASE + 0x000900bf*4 +0x02000000 , 0x00000014 ); +reg_write( DDR_REG_BASE + 0x000900c0*4 +0x02000000 , 0x00000790 ); +reg_write( DDR_REG_BASE + 0x000900c1*4 +0x02000000 , 0x0000011a ); +reg_write( DDR_REG_BASE + 0x000900c2*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900c3*4 +0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x000900c4*4 +0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x000900c5*4 +0x02000000 , 0x0000000e ); +reg_write( DDR_REG_BASE + 0x000900c6*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x000900c7*4 +0x02000000 , 0x00000199 ); +reg_write( DDR_REG_BASE + 0x000900c8*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900c9*4 +0x02000000 , 0x00008568 ); +reg_write( DDR_REG_BASE + 0x000900ca*4 +0x02000000 , 0x00000108 ); +reg_write( DDR_REG_BASE + 0x000900cb*4 +0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x000900cc*4 +0x02000000 , 0x00000790 ); +reg_write( DDR_REG_BASE + 0x000900cd*4 +0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x000900ce*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900cf*4 +0x02000000 , 0x000001d8 ); +reg_write( DDR_REG_BASE + 0x000900d0*4 +0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x000900d1*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000900d2*4 +0x02000000 , 0x00008558 ); +reg_write( DDR_REG_BASE + 0x000900d3*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x000900d4*4 +0x02000000 , 0x00000070 ); +reg_write( DDR_REG_BASE + 0x000900d5*4 +0x02000000 , 0x00000788 ); +reg_write( DDR_REG_BASE + 0x000900d6*4 +0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x000900d7*4 +0x02000000 , 0x00001ff8 ); +reg_write( DDR_REG_BASE + 0x000900d8*4 +0x02000000 , 0x000085a8 ); +reg_write( DDR_REG_BASE + 0x000900d9*4 +0x02000000 , 0x000001e8 ); +reg_write( DDR_REG_BASE + 0x000900da*4 +0x02000000 , 0x00000050 ); +reg_write( DDR_REG_BASE + 0x000900db*4 +0x02000000 , 0x00000798 ); +reg_write( DDR_REG_BASE + 0x000900dc*4 +0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x000900dd*4 +0x02000000 , 0x00000060 ); +reg_write( DDR_REG_BASE + 0x000900de*4 +0x02000000 , 0x000007a0 ); +reg_write( DDR_REG_BASE + 0x000900df*4 +0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x000900e0*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900e1*4 +0x02000000 , 0x00008310 ); +reg_write( DDR_REG_BASE + 0x000900e2*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x000900e3*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900e4*4 +0x02000000 , 0x0000a310 ); +reg_write( DDR_REG_BASE + 0x000900e5*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x000900e6*4 +0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x000900e7*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x000900e8*4 +0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x000900e9*4 +0x02000000 , 0x0000006e ); +reg_write( DDR_REG_BASE + 0x000900ea*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900eb*4 +0x02000000 , 0x00000068 ); +reg_write( DDR_REG_BASE + 0x000900ec*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900ed*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x000900ee*4 +0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x000900ef*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900f0*4 +0x02000000 , 0x00008310 ); +reg_write( DDR_REG_BASE + 0x000900f1*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x000900f2*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900f3*4 +0x02000000 , 0x0000a310 ); +reg_write( DDR_REG_BASE + 0x000900f4*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x000900f5*4 +0x02000000 , 0x00001ff8 ); +reg_write( DDR_REG_BASE + 0x000900f6*4 +0x02000000 , 0x000085a8 ); +reg_write( DDR_REG_BASE + 0x000900f7*4 +0x02000000 , 0x000001e8 ); +reg_write( DDR_REG_BASE + 0x000900f8*4 +0x02000000 , 0x00000068 ); +reg_write( DDR_REG_BASE + 0x000900f9*4 +0x02000000 , 0x00000798 ); +reg_write( DDR_REG_BASE + 0x000900fa*4 +0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x000900fb*4 +0x02000000 , 0x00000078 ); +reg_write( DDR_REG_BASE + 0x000900fc*4 +0x02000000 , 0x000007a0 ); +reg_write( DDR_REG_BASE + 0x000900fd*4 +0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x000900fe*4 +0x02000000 , 0x00000068 ); +reg_write( DDR_REG_BASE + 0x000900ff*4 +0x02000000 , 0x00000790 ); +reg_write( DDR_REG_BASE + 0x00090100*4 +0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x00090101*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090102*4 +0x02000000 , 0x00008b10 ); +reg_write( DDR_REG_BASE + 0x00090103*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x00090104*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090105*4 +0x02000000 , 0x0000ab10 ); +reg_write( DDR_REG_BASE + 0x00090106*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x00090107*4 +0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x00090108*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x00090109*4 +0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x0009010a*4 +0x02000000 , 0x00000058 ); +reg_write( DDR_REG_BASE + 0x0009010b*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009010c*4 +0x02000000 , 0x00000068 ); +reg_write( DDR_REG_BASE + 0x0009010d*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009010e*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x0009010f*4 +0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x00090110*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090111*4 +0x02000000 , 0x00008b10 ); +reg_write( DDR_REG_BASE + 0x00090112*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x00090113*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00090114*4 +0x02000000 , 0x0000ab10 ); +reg_write( DDR_REG_BASE + 0x00090115*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x00090116*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090117*4 +0x02000000 , 0x000001d8 ); +reg_write( DDR_REG_BASE + 0x00090118*4 +0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x00090119*4 +0x02000000 , 0x00000080 ); +reg_write( DDR_REG_BASE + 0x0009011a*4 +0x02000000 , 0x00000790 ); +reg_write( DDR_REG_BASE + 0x0009011b*4 +0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x0009011c*4 +0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x0009011d*4 +0x02000000 , 0x000007aa ); +reg_write( DDR_REG_BASE + 0x0009011e*4 +0x02000000 , 0x0000006a ); +reg_write( DDR_REG_BASE + 0x0009011f*4 +0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x00090120*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090121*4 +0x02000000 , 0x000001e9 ); +reg_write( DDR_REG_BASE + 0x00090122*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090123*4 +0x02000000 , 0x00008080 ); +reg_write( DDR_REG_BASE + 0x00090124*4 +0x02000000 , 0x00000108 ); +reg_write( DDR_REG_BASE + 0x00090125*4 +0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00090126*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x00090127*4 +0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x00090128*4 +0x02000000 , 0x0000000c ); +reg_write( DDR_REG_BASE + 0x00090129*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009012a*4 +0x02000000 , 0x00000068 ); +reg_write( DDR_REG_BASE + 0x0009012b*4 +0x02000000 , 0x00000009 ); +reg_write( DDR_REG_BASE + 0x0009012c*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009012d*4 +0x02000000 , 0x000001a9 ); +reg_write( DDR_REG_BASE + 0x0009012e*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009012f*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x00090130*4 +0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x00090131*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090132*4 +0x02000000 , 0x00008080 ); +reg_write( DDR_REG_BASE + 0x00090133*4 +0x02000000 , 0x00000108 ); +reg_write( DDR_REG_BASE + 0x00090134*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090135*4 +0x02000000 , 0x000007aa ); +reg_write( DDR_REG_BASE + 0x00090136*4 +0x02000000 , 0x0000006a ); +reg_write( DDR_REG_BASE + 0x00090137*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090138*4 +0x02000000 , 0x00008568 ); +reg_write( DDR_REG_BASE + 0x00090139*4 +0x02000000 , 0x00000108 ); +reg_write( DDR_REG_BASE + 0x0009013a*4 +0x02000000 , 0x000000b7 ); +reg_write( DDR_REG_BASE + 0x0009013b*4 +0x02000000 , 0x00000790 ); +reg_write( DDR_REG_BASE + 0x0009013c*4 +0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x0009013d*4 +0x02000000 , 0x0000001f ); +reg_write( DDR_REG_BASE + 0x0009013e*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009013f*4 +0x02000000 , 0x00000068 ); +reg_write( DDR_REG_BASE + 0x00090140*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090141*4 +0x02000000 , 0x00008558 ); +reg_write( DDR_REG_BASE + 0x00090142*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x00090143*4 +0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00090144*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x00090145*4 +0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x00090146*4 +0x02000000 , 0x0000000d ); +reg_write( DDR_REG_BASE + 0x00090147*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090148*4 +0x02000000 , 0x00000068 ); +reg_write( DDR_REG_BASE + 0x00090149*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009014a*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x0009014b*4 +0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x0009014c*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009014d*4 +0x02000000 , 0x00008558 ); +reg_write( DDR_REG_BASE + 0x0009014e*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x0009014f*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090150*4 +0x02000000 , 0x000003c8 ); +reg_write( DDR_REG_BASE + 0x00090151*4 +0x02000000 , 0x000001a9 ); +reg_write( DDR_REG_BASE + 0x00090152*4 +0x02000000 , 0x00000003 ); +reg_write( DDR_REG_BASE + 0x00090153*4 +0x02000000 , 0x00000370 ); +reg_write( DDR_REG_BASE + 0x00090154*4 +0x02000000 , 0x00000129 ); +reg_write( DDR_REG_BASE + 0x00090155*4 +0x02000000 , 0x00000020 ); +reg_write( DDR_REG_BASE + 0x00090156*4 +0x02000000 , 0x000002aa ); +reg_write( DDR_REG_BASE + 0x00090157*4 +0x02000000 , 0x00000009 ); +reg_write( DDR_REG_BASE + 0x00090158*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090159*4 +0x02000000 , 0x000000e8 ); +reg_write( DDR_REG_BASE + 0x0009015a*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009015b*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009015c*4 +0x02000000 , 0x00008140 ); +reg_write( DDR_REG_BASE + 0x0009015d*4 +0x02000000 , 0x0000010c ); +reg_write( DDR_REG_BASE + 0x0009015e*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x0009015f*4 +0x02000000 , 0x00008138 ); +reg_write( DDR_REG_BASE + 0x00090160*4 +0x02000000 , 0x00000104 ); +reg_write( DDR_REG_BASE + 0x00090161*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090162*4 +0x02000000 , 0x00000448 ); +reg_write( DDR_REG_BASE + 0x00090163*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090164*4 +0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00090165*4 +0x02000000 , 0x000007c0 ); +reg_write( DDR_REG_BASE + 0x00090166*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090167*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090168*4 +0x02000000 , 0x000000e8 ); +reg_write( DDR_REG_BASE + 0x00090169*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009016a*4 +0x02000000 , 0x00000047 ); +reg_write( DDR_REG_BASE + 0x0009016b*4 +0x02000000 , 0x00000630 ); +reg_write( DDR_REG_BASE + 0x0009016c*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009016d*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x0009016e*4 +0x02000000 , 0x00000618 ); +reg_write( DDR_REG_BASE + 0x0009016f*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090170*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090171*4 +0x02000000 , 0x000000e0 ); +reg_write( DDR_REG_BASE + 0x00090172*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090173*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090174*4 +0x02000000 , 0x000007c8 ); +reg_write( DDR_REG_BASE + 0x00090175*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090176*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090177*4 +0x02000000 , 0x00008140 ); +reg_write( DDR_REG_BASE + 0x00090178*4 +0x02000000 , 0x0000010c ); +reg_write( DDR_REG_BASE + 0x00090179*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009017a*4 +0x02000000 , 0x00000478 ); +reg_write( DDR_REG_BASE + 0x0009017b*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009017c*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009017d*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x0009017e*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x0009017f*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090180*4 +0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00090181*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090006*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090007*4 +0x02000000 , 0x000007c8 ); +reg_write( DDR_REG_BASE + 0x00090008*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090009*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009000a*4 +0x02000000 , 0x00000400 ); +reg_write( DDR_REG_BASE + 0x0009000b*4 +0x02000000 , 0x00000106 ); +reg_write( DDR_REG_BASE + 0x000d00e7*4 +0x02000000 , 0x00000400 ); +reg_write( DDR_REG_BASE + 0x00090017*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009001f*4 +0x02000000 , 0x00000029 ); +reg_write( DDR_REG_BASE + 0x00090026*4 +0x02000000 , 0x00000068 ); +reg_write( DDR_REG_BASE + 0x000400d0*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000400d1*4 +0x02000000 , 0x00000101 ); +reg_write( DDR_REG_BASE + 0x000400d2*4 +0x02000000 , 0x00000105 ); +reg_write( DDR_REG_BASE + 0x000400d3*4 +0x02000000 , 0x00000107 ); +reg_write( DDR_REG_BASE + 0x000400d4*4 +0x02000000 , 0x0000010f ); +reg_write( DDR_REG_BASE + 0x000400d5*4 +0x02000000 , 0x00000202 ); +reg_write( DDR_REG_BASE + 0x000400d6*4 +0x02000000 , 0x0000020a ); +reg_write( DDR_REG_BASE + 0x000400d7*4 +0x02000000 , 0x0000020b ); +reg_write( DDR_REG_BASE + 0x0002003a*4 +0x02000000 , 0x00000002 ); +reg_write( DDR_REG_BASE + 0x000200be*4 +0x02000000 , 0x00000003 ); +reg_write( DDR_REG_BASE + 0x0002000b*4 +0x02000000 , 0x00000064 ); +reg_write( DDR_REG_BASE + 0x0002000c*4 +0x02000000 , 0x000000c8 ); +reg_write( DDR_REG_BASE + 0x0002000d*4 +0x02000000 , 0x000007d0 ); +reg_write( DDR_REG_BASE + 0x0002000e*4 +0x02000000 , 0x0000002c ); +reg_write( DDR_REG_BASE + 0x0009000c*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009000d*4 +0x02000000 , 0x00000173 ); +reg_write( DDR_REG_BASE + 0x0009000e*4 +0x02000000 , 0x00000060 ); +reg_write( DDR_REG_BASE + 0x0009000f*4 +0x02000000 , 0x00006110 ); +reg_write( DDR_REG_BASE + 0x00090010*4 +0x02000000 , 0x00002152 ); +reg_write( DDR_REG_BASE + 0x00090011*4 +0x02000000 , 0x0000dfbd ); +reg_write( DDR_REG_BASE + 0x00090012*4 +0x02000000 , 0x00002060 ); +reg_write( DDR_REG_BASE + 0x00090013*4 +0x02000000 , 0x00006152 ); +reg_write( DDR_REG_BASE + 0x00040080*4 +0x02000000 , 0x000000e0 ); +reg_write( DDR_REG_BASE + 0x00040081*4 +0x02000000 , 0x00000012 ); +reg_write( DDR_REG_BASE + 0x00040082*4 +0x02000000 , 0x000000e0 ); +reg_write( DDR_REG_BASE + 0x00040083*4 +0x02000000 , 0x00000012 ); +reg_write( DDR_REG_BASE + 0x00040084*4 +0x02000000 , 0x000000e0 ); +reg_write( DDR_REG_BASE + 0x00040085*4 +0x02000000 , 0x00000012 ); +reg_write( DDR_REG_BASE + 0x000400fd*4 +0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00010011*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00010012*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00010013*4 +0x02000000 , 0x00000180 ); +reg_write( DDR_REG_BASE + 0x00010018*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00010002*4 +0x02000000 , 0x00006209 ); +reg_write( DDR_REG_BASE + 0x000100b2*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000101b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000102b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000103b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000104b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000105b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000106b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000107b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000108b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00011011*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00011012*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00011013*4 +0x02000000 , 0x00000180 ); +reg_write( DDR_REG_BASE + 0x00011018*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00011002*4 +0x02000000 , 0x00006209 ); +reg_write( DDR_REG_BASE + 0x000110b2*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000111b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000112b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000113b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000114b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000115b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000116b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000117b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000118b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00012011*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00012012*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00012013*4 +0x02000000 , 0x00000180 ); +reg_write( DDR_REG_BASE + 0x00012018*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00012002*4 +0x02000000 , 0x00006209 ); +reg_write( DDR_REG_BASE + 0x000120b2*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000121b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000122b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000123b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000124b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000125b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000126b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000127b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000128b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00013011*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00013012*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00013013*4 +0x02000000 , 0x00000180 ); +reg_write( DDR_REG_BASE + 0x00013018*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00013002*4 +0x02000000 , 0x00006209 ); +reg_write( DDR_REG_BASE + 0x000130b2*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000131b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000132b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000133b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000134b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000135b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000136b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000137b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000138b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00020089*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00020088*4 +0x02000000 , 0x00000019 ); +reg_write( DDR_REG_BASE + 0x000c0080*4 +0x02000000 , 0x00000002 ); +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000000 ); +reg_read ( DDR_REG_BASE + 0x00020010*4 +0x02000000 , data); +reg_write( DDR_REG_BASE + 0x00020010*4 +0x02000000 , 0x0000006a ); +reg_write( DDR_REG_BASE + 0x00020010*4 +0x02000000 , 0x0000006a ); +reg_read ( DDR_REG_BASE + 0x0002001d*4 +0x02000000 , data); +reg_write( DDR_REG_BASE + 0x0002001d*4 +0x02000000 , 0x00000001 ); +reg_read ( DDR_REG_BASE + 0x00020097*4 +0x02000000 , data); + + + +///////////////////////////2d training end/////////////////////////////////////////// + + + +//////////////////phy init end //////////////////////////////////// + +reg_write( DDR_REG_BASE + 0x000001b0 , 0x00000034 ); + +reg_read (DDR_REG_BASE + 0x000001bc , data ); +while((data&0x1) !=0x1) { + reg_read (DDR_REG_BASE + 0x000001bc , data ); +} + + +reg_write( DDR_REG_BASE + 0x000001b0 , 0x00000014 ); +reg_write( DDR_REG_BASE + 0x000001b0 , 0x00000015 ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000320 , 0x00000001 ); + + + +reg_read (DDR_REG_BASE + 0x00000324 , data ); + while((data&0x1) !=0x1) { + reg_read (DDR_REG_BASE + 0x00000324 , data ); + } + +reg_read (DDR_REG_BASE + 0x00000004 , data ); + while((data&0x1) !=0x1) { + reg_read (DDR_REG_BASE + 0x00000004 , data ); + } + + + + +reg_write( DDR_REG_BASE + 0x000001c4 , 0xd1000000 ); +reg_write( DDR_REG_BASE + 0x00000320 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000000d0 , 0x00020002 ); +reg_write( DDR_REG_BASE + 0x00000320 , 0x00000001 ); + + + +reg_read (DDR_REG_BASE + 0x00000324 , data ); + while((data&0x1) !=0x1) { + reg_read (DDR_REG_BASE + 0x00000324 , data ); + } + + + + +reg_write( DDR_REG_BASE + 0x00000304 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000490 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000540 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000005f0 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000006a0 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000750 , 0x00000001 ); + +reg_write( DDR_REG_BASE + 0x0000060 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0000050 , 0x98210000 ); + + + { + unsigned long add,i; + //add = DDR_REG_BASE +0x5401b*4+0x02000000; printf("MR12-CA add =%lx value =%lx\n",add,readl(add)); + //add = DDR_REG_BASE +0x5401c*4+0x02000000; printf("MR14-DQ add =%lx value =%lx\n",add,readl(add)); + + for(i=0;i<8;i++) + {add = DDR_REG_BASE + 0x00010040*4+0x02000000+i*0x100*4; printf("dbyte0 add =%lx value =%x\n",add,readl((void*)add));} + for(i=0;i<8;i++) + {add = DDR_REG_BASE + 0x00011040*4+0x02000000+i*0x100*4; printf("dbyte1 add =%lx value =%x\n",add,readl((void*)add));} + for(i=0;i<8;i++) + {add = DDR_REG_BASE + 0x00012040*4+0x02000000+i*0x100*4; printf("dbyte2 add =%lx value =%x\n",add,readl((void*)add));} + for(i=0;i<8;i++) + {add = DDR_REG_BASE + 0x00013040*4+0x02000000+i*0x100*4; printf("dbyte3 add =%lx value =%x\n",add,readl((void*)add)); } + } + +} + + + +#define BOOT_REG_BASE (0x91102000) +#define PLL0_CFG0 (BOOT_REG_BASE + 0x0 ) +#define PLL0_CFG1 (BOOT_REG_BASE + 0x4 ) +#define PLL0_CTL (BOOT_REG_BASE + 0x8 ) +#define PLL0_STAT (BOOT_REG_BASE + 0xC ) +#define PLL1_CFG0 (BOOT_REG_BASE + 0x10 ) +#define PLL1_CFG1 (BOOT_REG_BASE + 0x14 ) +#define PLL1_CTL (BOOT_REG_BASE + 0x18 ) +#define PLL1_STAT (BOOT_REG_BASE + 0x1C ) +#define PLL2_CFG0 (BOOT_REG_BASE + 0x20 ) +#define PLL2_CFG1 (BOOT_REG_BASE + 0x24 ) +#define PLL2_CTL (BOOT_REG_BASE + 0x28 ) +#define PLL2_STAT (BOOT_REG_BASE + 0x2C ) +#define PLL3_CFG0 (BOOT_REG_BASE + 0x30 ) +#define PLL3_CFG1 (BOOT_REG_BASE + 0x34 ) +#define PLL3_CTL (BOOT_REG_BASE + 0x38 ) +#define PLL3_STAT (BOOT_REG_BASE + 0x3C ) + +void pd_pll(uint32_t pll_ctl,uint32_t pll_stat) +{ +int rdata; + writel(0x10001,(void*)(ulong)pll_ctl); + rdata=readl((void*)(ulong)pll_stat); + while( (rdata&0x30) != 0x0){ + rdata=readl((void*)(ulong)pll_stat); + } + +} +void init_pll(uint32_t pll_ctl,uint32_t pll_stat) +{ + int rdata; + writel(0x20002,(void*)(ulong)pll_ctl); + rdata=readl((void*)(ulong)pll_stat); + while( (rdata & 0x30) != 0x20){ + rdata=readl((void*)(ulong)pll_stat); + } + +} + +uint32_t cfg_pll(int fb_div,int ref_div,int out_div,unsigned int pllx_cfg0,unsigned int pllx_cfg1,int pllx_ctl,int pllx_stat) +{ +// int pll_sta; +// int wdata,rdata; + pd_pll(pllx_ctl,pllx_stat); + //writel(( (fb_div/2) | 0x20000),pllx_cfg1 ); + writel(( (fb_div/4) | 0x20000),(void*)(ulong)pllx_cfg1 ); //for minimum long term jitter + writel(( (fb_div & 0x1fff) | ( (ref_div & 0x3f) << 16 ) | ( (out_div & 0xf) << 24) ),(void*)(ulong)pllx_cfg0 ); + init_pll(pllx_ctl,pllx_stat); + return 0; +} + +int change_pll_3100(void) +{ + /* enable cache */ + //Note: The recommended value for BWADJ is FBK_DIV/2.Valid values range from 0 to 0xFFF. + //To minimize long-term jitter, using NB=NF/4 is better. NB = BWADJ[11:0] + 1, + //So, BWADJ=(NB-1)=[NF/2 -1] or (NF/4 -1)--minimize long term jitter + + // csi_dcache_enable(); + // csi_icache_enable(); + // printf("Core %d Hello World!\n",1); + // printf("C908 core1 boot success!\n"); + + // cfg_pll( // 760M + // 379, //fb_div=NF-1 + // 2, //ref_div=NR-1 + // 3, //out_div=OD-1 + // PLL2_CFG0, + // PLL2_CFG1, + // PLL2_CTL, + // PLL2_STAT + // ); + + cfg_pll( // 1860Mhz + 128, //fb_div=NF-1 + 0, //ref_div=NR-1 + 0, //out_div=OD-1 + PLL2_CFG0, + PLL2_CFG1, + PLL2_CTL, + PLL2_STAT + ); + + + *(uint32_t*)(0x91100060) = 0x800043fe;//switch ddrc_core_clk source to pll2div4 + //__ASM volatile("wfi"); + udelay(50); + + //sys_exit(0); + return 0; +} \ No newline at end of file diff --git a/src/little/uboot/board/canaan/k230_canmv_dongshanpi/Kconfig b/src/little/uboot/board/canaan/k230_canmv_dongshanpi/Kconfig new file mode 100755 index 000000000..9682c3989 --- /dev/null +++ b/src/little/uboot/board/canaan/k230_canmv_dongshanpi/Kconfig @@ -0,0 +1,23 @@ +if TARGET_K230_CANMV_DONGSHANPI + +config SYS_CPU + default "k230" + +config SYS_VENDOR + default "canaan" + +config SYS_BOARD + default "k230_canmv_dongshanpi" + +config SYS_CONFIG_NAME + default "k230_evb" + + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select RISCV_THEAD + +config CANMV_LPDDR3_2133 + def_bool y + +endif diff --git a/src/little/uboot/board/canaan/k230_canmv_dongshanpi/Makefile b/src/little/uboot/board/canaan/k230_canmv_dongshanpi/Makefile new file mode 100755 index 000000000..02907b10b --- /dev/null +++ b/src/little/uboot/board/canaan/k230_canmv_dongshanpi/Makefile @@ -0,0 +1,46 @@ +# /* Copyright (c) 2023, Canaan Bright Sight Co., Ltd +# * +# * Redistribution and use in source and binary forms, with or without +# * modification, are permitted provided that the following conditions are met: +# * 1. Redistributions of source code must retain the above copyright +# * notice, this list of conditions and the following disclaimer. +# * 2. Redistributions in binary form must reproduce the above copyright +# * notice, this list of conditions and the following disclaimer in the +# * documentation and/or other materials provided with the distribution. +# * +# * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +# * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +# * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +# * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR +# * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +# * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +# * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# */ + +obj-y += board.o + +obj-$(CONFIG_CANMV_LPDDR3_2133) += gen_pilpddr3_2133.o #ddr_init_2133.c + +$(obj)/gen_pilpddr3_2133.c: $(src)/k230pi_ddr_init_2133.c $(srctree)/arch/riscv/cpu/k230/ddr.sh + ($(srctree)/arch/riscv/cpu/k230/ddr.sh $< $@ 0x50000 0x53fff 0x54000 0x54359 || exit 1) + + +EXTRA_CFLAGS += -I$(srctree)/arch/$(ARCH)/cpu/k230/ +EXTRA_CFLAGS += -I$(srctree)/arch/$(ARCH)/cpu/k230/puf_fw/pufs_common +EXTRA_CFLAGS += -I$(srctree)/arch/$(ARCH)/cpu/k230/puf_fw/pufs_crypto +EXTRA_CFLAGS += -I$(srctree)/arch/$(ARCH)/cpu/k230/puf_fw/pufs_dma +EXTRA_CFLAGS += -I$(srctree)/arch/$(ARCH)/cpu/k230/puf_fw/pufs_ka +EXTRA_CFLAGS += -I$(srctree)/arch/$(ARCH)/cpu/k230/puf_fw/pufs_rt +EXTRA_CFLAGS += -I$(srctree)/arch/$(ARCH)/cpu/k230/puf_fw/pufs_ecc +EXTRA_CFLAGS += -I$(srctree)/arch/$(ARCH)/cpu/k230/puf_fw/pufs_hmac +EXTRA_CFLAGS += -I$(srctree)/arch/$(ARCH)/cpu/k230/puf_fw/pufs_ecp +EXTRA_CFLAGS += -I$(srctree)/arch/$(ARCH)/cpu/k230/puf_fw/pufs_sm2 +EXTRA_CFLAGS += -I$(srctree)/arch/$(ARCH)/cpu/k230/puf_fw/pufs_sp38a +EXTRA_CFLAGS += -I$(srctree)/arch/$(ARCH)/cpu/k230/puf_fw/pufs_sp38d + diff --git a/src/little/uboot/board/canaan/k230_canmv_dongshanpi/board.c b/src/little/uboot/board/canaan/k230_canmv_dongshanpi/board.c new file mode 100755 index 000000000..f83e5f739 --- /dev/null +++ b/src/little/uboot/board/canaan/k230_canmv_dongshanpi/board.c @@ -0,0 +1,26 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "sysctl.h" + +#include +#include +#include +#include "pufs_sm2.h" +#include +#include +#include +// #include "sdk_autoconf.h" +// #include "k230_board_common.h" +#include +#include +#include + diff --git a/src/little/uboot/board/canaan/k230_canmv_dongshanpi/k230pi_ddr_init_2133.c b/src/little/uboot/board/canaan/k230_canmv_dongshanpi/k230pi_ddr_init_2133.c new file mode 100755 index 000000000..3bd68ff7f --- /dev/null +++ b/src/little/uboot/board/canaan/k230_canmv_dongshanpi/k230pi_ddr_init_2133.c @@ -0,0 +1,18402 @@ +/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +//#include +//#include +#include +#define DDR_REG_BASE 0x98000000 + +#define reg_write( addr,v) \ + { \ + (*(volatile uint32_t *)((size_t)(addr))) = (v); \ + } + + +#define reg_read( addr,v) \ + { \ + v =readl ((const volatile void __iomem *) addr ); \ + } + +void pi_ddr_init_2133(void) +{ +int data; +int train_data=0; + +reg_write( DDR_REG_BASE + 0x00000304 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000001 ); +reg_read ( DDR_REG_BASE + 0x00000004 , data); +reg_write( DDR_REG_BASE + 0x00000000 , 0x01040008 ); +reg_write( DDR_REG_BASE + 0x00000010 , 0x0000e030 ); +reg_write( DDR_REG_BASE + 0x00000014 , 0x00007563 ); +reg_write( DDR_REG_BASE + 0x00000020 , 0x00001100 ); +reg_write( DDR_REG_BASE + 0x00000024 , 0xb4b04b13 ); +reg_write( DDR_REG_BASE + 0x00000028 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x0000002c , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000020 ); +reg_write( DDR_REG_BASE + 0x00000034 , 0x00405f04 ); +reg_write( DDR_REG_BASE + 0x00000038 , 0x00a80002 ); +reg_write( DDR_REG_BASE + 0x0000003c , 0x00010050 ); +reg_write( DDR_REG_BASE + 0x00000050 , 0x90210000 ); +reg_write( DDR_REG_BASE + 0x00000054 , 0x003b0035 ); +reg_write( DDR_REG_BASE + 0x00000060 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000064 , 0x00400046 ); +reg_write( DDR_REG_BASE + 0x00000068 , 0x005b0000 ); +reg_write( DDR_REG_BASE + 0x000000c0 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000000d0 , 0xc0020002 ); +reg_write( DDR_REG_BASE + 0x000000d4 , 0x00010002 ); +reg_write( DDR_REG_BASE + 0x000000d8 , 0x00001200 ); +reg_write( DDR_REG_BASE + 0x000000dc , 0x00c3001e ); +reg_write( DDR_REG_BASE + 0x000000e0 , 0x00020000 ); +reg_write( DDR_REG_BASE + 0x000000e4 , 0x00120007 ); +reg_write( DDR_REG_BASE + 0x000000e8 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000000ec , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000000f0 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000000f4 , 0x0000023f ); +reg_write( DDR_REG_BASE + 0x000000f8 , 0x00000002 ); +reg_write( DDR_REG_BASE + 0x00000100 , 0x0e1b2316 ); +reg_write( DDR_REG_BASE + 0x00000104 , 0x00040422 ); +reg_write( DDR_REG_BASE + 0x00000108 , 0x04080a0b ); +reg_write( DDR_REG_BASE + 0x0000010c , 0x00508006 ); +reg_write( DDR_REG_BASE + 0x00000110 , 0x0a02060b ); +reg_write( DDR_REG_BASE + 0x00000114 , 0x01010808 ); +reg_write( DDR_REG_BASE + 0x00000118 , 0x01010005 ); +reg_write( DDR_REG_BASE + 0x0000011c , 0x00000101 ); +reg_write( DDR_REG_BASE + 0x00000120 , 0x00000101 ); +reg_write( DDR_REG_BASE + 0x00000130 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000134 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000138 , 0x0000004b ); +reg_write( DDR_REG_BASE + 0x0000013c , 0x80000000 ); +reg_write( DDR_REG_BASE + 0x00000144 , 0x00000094 ); +reg_write( DDR_REG_BASE + 0x00000180 , 0xe0c00030 ); +reg_write( DDR_REG_BASE + 0x00000184 , 0x01b0c892 ); +reg_write( DDR_REG_BASE + 0x00000188 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000190 , 0x038b8204 ); +reg_write( DDR_REG_BASE + 0x00000194 , 0x00070202 ); +reg_write( DDR_REG_BASE + 0x00000198 , 0x07a09110 ); +reg_write( DDR_REG_BASE + 0x000001a0 , 0xa0400018 ); +reg_write( DDR_REG_BASE + 0x000001a4 , 0x00760085 ); +reg_write( DDR_REG_BASE + 0x000001a8 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000001b0 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000001b4 , 0x00000b04 ); +reg_write( DDR_REG_BASE + 0x000001c0 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000001c4 , 0x85000000 ); +#if 0 +reg_write( DDR_REG_BASE + 0x00000200 , 0x0000001f ); +reg_write( DDR_REG_BASE + 0x00000204 , 0x00090909 ); +reg_write( DDR_REG_BASE + 0x00000208 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0000020c , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000210 , 0x00001f00 ); +reg_write( DDR_REG_BASE + 0x00000214 , 0x080f0808 ); +reg_write( DDR_REG_BASE + 0x00000218 , 0x0f0f0808 ); +reg_write( DDR_REG_BASE + 0x0000021c , 0x00000f0f ); +reg_write( DDR_REG_BASE + 0x00000224 , 0x08080808 ); +reg_write( DDR_REG_BASE + 0x00000228 , 0x08080808 ); +reg_write( DDR_REG_BASE + 0x0000022c , 0x00000008 ); +#else +reg_write( DDR_REG_BASE + 0x00000200 , 0x0000001f ); +reg_write( DDR_REG_BASE + 0x00000204 , 0x00080808 ); +reg_write( DDR_REG_BASE + 0x00000208 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0000020c , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000210 , 0x00001f1f ); +reg_write( DDR_REG_BASE + 0x00000214 , 0x070f0707 ); +reg_write( DDR_REG_BASE + 0x00000218 , 0x0f0f0707 ); +reg_write( DDR_REG_BASE + 0x0000021c , 0x00000f0f ); +reg_write( DDR_REG_BASE + 0x00000224 , 0x07070707 ); +reg_write( DDR_REG_BASE + 0x00000228 , 0x07070707 ); +reg_write( DDR_REG_BASE + 0x0000022c , 0x00000007 ); +#endif +reg_write( DDR_REG_BASE + 0x00000240 , 0x06040a30 ); +reg_write( DDR_REG_BASE + 0x00000244 , 0x00002301 ); +reg_write( DDR_REG_BASE + 0x00000250 , 0x80c31f18 ); +reg_write( DDR_REG_BASE + 0x00000254 , 0x00002000 ); +reg_write( DDR_REG_BASE + 0x0000025c , 0x0f000001 ); +reg_write( DDR_REG_BASE + 0x00000264 , 0x0f00007f ); +reg_write( DDR_REG_BASE + 0x0000026c , 0x0f00007f ); +reg_write( DDR_REG_BASE + 0x00000270 , 0x04040208 ); +reg_write( DDR_REG_BASE + 0x00000274 , 0x08400810 ); +reg_write( DDR_REG_BASE + 0x00000300 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000304 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0000030c , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000320 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000328 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0000036c , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000490 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000540 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000005f0 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000006a0 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000750 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00002020 , 0x00001100 ); +reg_write( DDR_REG_BASE + 0x00002024 , 0xb4b04b13 ); +reg_write( DDR_REG_BASE + 0x00002034 , 0x00405f04 ); +reg_write( DDR_REG_BASE + 0x00002050 , 0x30210000 ); +reg_write( DDR_REG_BASE + 0x00002064 , 0x00400046 ); +reg_write( DDR_REG_BASE + 0x00002068 , 0x005b0000 ); +reg_write( DDR_REG_BASE + 0x000020dc , 0x00c3001e ); +reg_write( DDR_REG_BASE + 0x000020e0 , 0x00020000 ); +reg_write( DDR_REG_BASE + 0x000020e8 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000020ec , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000020f4 , 0x0000023f ); +reg_write( DDR_REG_BASE + 0x000020f8 , 0x00000002 ); +reg_write( DDR_REG_BASE + 0x00002100 , 0x0e1b2316 ); +reg_write( DDR_REG_BASE + 0x00002104 , 0x00040422 ); +reg_write( DDR_REG_BASE + 0x00002108 , 0x04080a0b ); +reg_write( DDR_REG_BASE + 0x0000210c , 0x00508006 ); +reg_write( DDR_REG_BASE + 0x00002110 , 0x0a02060b ); +reg_write( DDR_REG_BASE + 0x00002114 , 0x01010808 ); +reg_write( DDR_REG_BASE + 0x00002118 , 0x01010005 ); +reg_write( DDR_REG_BASE + 0x0000211c , 0x00000101 ); +reg_write( DDR_REG_BASE + 0x00002120 , 0x00000101 ); +reg_write( DDR_REG_BASE + 0x00002130 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00002134 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00002138 , 0x0000004b ); +reg_write( DDR_REG_BASE + 0x0000213c , 0x80000000 ); +reg_write( DDR_REG_BASE + 0x00002144 , 0x00000094 ); +reg_write( DDR_REG_BASE + 0x00002180 , 0xe0c00030 ); +reg_write( DDR_REG_BASE + 0x00002190 , 0x038b8204 ); +reg_write( DDR_REG_BASE + 0x00002194 , 0x00070202 ); +reg_write( DDR_REG_BASE + 0x000021b4 , 0x00000b04 ); +reg_write( DDR_REG_BASE + 0x00002240 , 0x06040a30 ); +reg_write( DDR_REG_BASE + 0x00003020 , 0x00001100 ); +reg_write( DDR_REG_BASE + 0x00003024 , 0xb4b04b13 ); +reg_write( DDR_REG_BASE + 0x00003034 , 0x00405f04 ); +reg_write( DDR_REG_BASE + 0x00003050 , 0xc0210000 ); +reg_write( DDR_REG_BASE + 0x00003064 , 0x00400046 ); +reg_write( DDR_REG_BASE + 0x00003068 , 0x005b0000 ); +reg_write( DDR_REG_BASE + 0x000030dc , 0x00c3001e ); +reg_write( DDR_REG_BASE + 0x000030e0 , 0x00020000 ); +reg_write( DDR_REG_BASE + 0x000030e8 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000030ec , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000030f4 , 0x0000023f ); +reg_write( DDR_REG_BASE + 0x000030f8 , 0x00000002 ); +reg_write( DDR_REG_BASE + 0x00003100 , 0x0e1b2316 ); +reg_write( DDR_REG_BASE + 0x00003104 , 0x00040422 ); +reg_write( DDR_REG_BASE + 0x00003108 , 0x04080a0b ); +reg_write( DDR_REG_BASE + 0x0000310c , 0x00508006 ); +reg_write( DDR_REG_BASE + 0x00003110 , 0x0a02060b ); +reg_write( DDR_REG_BASE + 0x00003114 , 0x01010808 ); +reg_write( DDR_REG_BASE + 0x00003118 , 0x01010005 ); +reg_write( DDR_REG_BASE + 0x0000311c , 0x00000101 ); +reg_write( DDR_REG_BASE + 0x00003120 , 0x00000101 ); +reg_write( DDR_REG_BASE + 0x00003130 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00003134 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00003138 , 0x0000004b ); +reg_write( DDR_REG_BASE + 0x0000313c , 0x80000000 ); +reg_write( DDR_REG_BASE + 0x00003144 , 0x00000094 ); +reg_write( DDR_REG_BASE + 0x00003180 , 0xe0c00030 ); +reg_write( DDR_REG_BASE + 0x00003190 , 0x038b8204 ); +reg_write( DDR_REG_BASE + 0x00003194 , 0x00070202 ); +reg_write( DDR_REG_BASE + 0x000031b4 , 0x00000b04 ); +reg_write( DDR_REG_BASE + 0x00003240 , 0x06040a30 ); +reg_write( DDR_REG_BASE + 0x00004020 , 0x00001100 ); +reg_write( DDR_REG_BASE + 0x00004024 , 0xb4b04b13 ); +reg_write( DDR_REG_BASE + 0x00004034 , 0x00405f04 ); +reg_write( DDR_REG_BASE + 0x00004050 , 0xa8210000 ); +reg_write( DDR_REG_BASE + 0x00004064 , 0x00408046 ); +reg_write( DDR_REG_BASE + 0x00004068 , 0x005b0000 ); +reg_write( DDR_REG_BASE + 0x000040dc , 0x00c3001e ); +reg_write( DDR_REG_BASE + 0x000040e0 , 0x00020000 ); +reg_write( DDR_REG_BASE + 0x000040e8 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000040ec , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000040f4 , 0x0000023f ); +reg_write( DDR_REG_BASE + 0x000040f8 , 0x00000002 ); +reg_write( DDR_REG_BASE + 0x00004100 , 0x0e1b2316 ); +reg_write( DDR_REG_BASE + 0x00004104 , 0x00040422 ); +reg_write( DDR_REG_BASE + 0x00004108 , 0x04080a0b ); +reg_write( DDR_REG_BASE + 0x0000410c , 0x00508006 ); +reg_write( DDR_REG_BASE + 0x00004110 , 0x0a02060b ); +reg_write( DDR_REG_BASE + 0x00004114 , 0x01010808 ); +reg_write( DDR_REG_BASE + 0x00004118 , 0x01010005 ); +reg_write( DDR_REG_BASE + 0x0000411c , 0x00000101 ); +reg_write( DDR_REG_BASE + 0x00004120 , 0x00000101 ); +reg_write( DDR_REG_BASE + 0x00004130 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00004134 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00004138 , 0x0000004b ); +reg_write( DDR_REG_BASE + 0x0000413c , 0x80000000 ); +reg_write( DDR_REG_BASE + 0x00004144 , 0x00000094 ); +reg_write( DDR_REG_BASE + 0x00004180 , 0xe0c00030 ); +reg_write( DDR_REG_BASE + 0x00004190 , 0x038b8204 ); +reg_write( DDR_REG_BASE + 0x00004194 , 0x00070202 ); +reg_write( DDR_REG_BASE + 0x000041b4 , 0x00000b04 ); +reg_write( DDR_REG_BASE + 0x00004240 , 0x06040a30 ); +reg_read ( DDR_REG_BASE + 0x00000060 , data ); +reg_write( DDR_REG_BASE + 0x00000400 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000404 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x000004b4 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x00000564 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x00000614 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x000006c4 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x00000404 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000004b4 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000564 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000614 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000006c4 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000404 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000004b4 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000564 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000614 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000006c4 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000404 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x000004b4 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x00000564 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x00000614 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x000006c4 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x00000408 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x000004b8 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x00000568 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x00000618 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x000006c8 , 0x0000400f ); +reg_write( DDR_REG_BASE + 0x00000408 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000004b8 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000568 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000618 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000006c8 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000408 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000004b8 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000568 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000618 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x000006c8 , 0x0000500f ); +reg_write( DDR_REG_BASE + 0x00000408 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x000004b8 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x00000568 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x00000618 , 0x0000100f ); +reg_write( DDR_REG_BASE + 0x000006c8 , 0x0000100f ); +reg_read ( DDR_REG_BASE + 0x00000030 , data ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000020 ); +//////////////////////////////////////////////////////// + + reg_read ( 0x9110309c, data ); + data=data|0x00020000; + reg_write ( 0x9110309c, data ); + + + +reg_write( DDR_REG_BASE + 0x00000304 , 0x00000000 ); +reg_read ( DDR_REG_BASE + 0x00000030 , data); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000020 ); +reg_read ( DDR_REG_BASE + 0x00000030 , data ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000020 ); +reg_read ( DDR_REG_BASE + 0x000001c4 , data ); +reg_write( DDR_REG_BASE + 0x000001c4 , 0x85000000 ); +reg_write( DDR_REG_BASE + 0x00000320 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000001b0 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000001b0 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000304 , 0x00000002 ); +reg_read ( DDR_REG_BASE + 0x000000d0 , data ); +reg_read ( DDR_REG_BASE + 0x000001c0 , data ); +reg_read ( DDR_REG_BASE + 0x00000000 , data ); +reg_read ( DDR_REG_BASE + 0x000000dc , data ); +reg_read ( DDR_REG_BASE + 0x000000dc , data ); +reg_read ( DDR_REG_BASE + 0x000000e0 , data ); +reg_read ( DDR_REG_BASE + 0x000000d0 , data ); +reg_read ( DDR_REG_BASE + 0x000001c0 , data ); +reg_read ( DDR_REG_BASE + 0x00000000 , data ); +reg_read ( DDR_REG_BASE + 0x000000dc , data ); +reg_read ( DDR_REG_BASE + 0x000000dc , data ); +reg_read ( DDR_REG_BASE + 0x000000e0 , data ); +reg_read ( DDR_REG_BASE + 0x000000d0 , data ); + + + + +reg_write( DDR_REG_BASE + 0x0001005f*4 +0x02000000 , 0x000002ff ); +reg_write( DDR_REG_BASE + 0x0001015f*4 +0x02000000 , 0x000002ff ); +reg_write( DDR_REG_BASE + 0x0001105f*4 +0x02000000 , 0x000002ff ); +reg_write( DDR_REG_BASE + 0x0001115f*4 +0x02000000 , 0x000002ff ); +reg_write( DDR_REG_BASE + 0x0001205f*4 +0x02000000 , 0x000002ff ); +reg_write( DDR_REG_BASE + 0x0001215f*4 +0x02000000 , 0x000002ff ); +reg_write( DDR_REG_BASE + 0x0001305f*4 +0x02000000 , 0x000002ff ); +reg_write( DDR_REG_BASE + 0x0001315f*4 +0x02000000 , 0x000002ff ); +reg_write( DDR_REG_BASE + 0x00000055*4 +0x02000000 , 0x000003ff ); +reg_write( DDR_REG_BASE + 0x00001055*4 +0x02000000 , 0x000000ff ); +reg_write( DDR_REG_BASE + 0x00002055*4 +0x02000000 , 0x000003ff ); +reg_write( DDR_REG_BASE + 0x00003055*4 +0x02000000 , 0x000003ff ); +reg_write( DDR_REG_BASE + 0x00004055*4 +0x02000000 , 0x000003ff ); +reg_write( DDR_REG_BASE + 0x00005055*4 +0x02000000 , 0x000003ff ); +reg_write( DDR_REG_BASE + 0x00006055*4 +0x02000000 , 0x000000ff ); +reg_write( DDR_REG_BASE + 0x00007055*4 +0x02000000 , 0x000003ff ); +reg_write( DDR_REG_BASE + 0x00008055*4 +0x02000000 , 0x000003ff ); +reg_write( DDR_REG_BASE + 0x00009055*4 +0x02000000 , 0x000003ff ); +reg_write( DDR_REG_BASE + 0x000200c5*4 +0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x0002002e*4 +0x02000000 , 0x00000002 ); +reg_write( DDR_REG_BASE + 0x00020024*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0002003a*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0002007d*4 +0x02000000 , 0x00000212 ); +reg_write( DDR_REG_BASE + 0x0002007c*4 +0x02000000 , 0x00000061 ); +reg_write( DDR_REG_BASE + 0x00020056*4 +0x02000000 , 0x00000006 ); +//iteration place +//PHY ODT --pull up +//00_1000 0x08 Pullup/Down:120 +//00_1010 0x0a Pullup/Down:80 +//01_1000 0x18 Pullup/Down:60 +//01_1010 0x1a Pullup/Down:48 +//11_1000 0x38 Pullup/Down:40 +//11_1010 0x3a Pullup/Down:34.3 +reg_write( DDR_REG_BASE + 0x0001004d*4 +0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x0001014d*4 +0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x0001104d*4 +0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x0001114d*4 +0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x0001204d*4 +0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x0001214d*4 +0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x0001304d*4 +0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x0001314d*4 +0x02000000 , 0x00000018 ); +// // [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqP to 0x18 +// // [phyinit_C_initPhyConfig] Pstate=0, Memclk=800MHz, Programming TxImpedanceCtrl1::DrvStrenFSDqN to 0x18 + +//iteration place +//PHY TX output impedence +//0010_00 00_1000 0x208 Pullup/Down:120 +//0010_10 00_1010 0x28a Pullup/Down:80 +//0110_00 01_1000 0x618 Pullup/Down:60 +//0110_10 01_1010 0x69a Pullup/Down:48 +//1110_00 11_1000 0xe38 Pullup/Down:40 +//1110_10 11_1010 0xeba Pullup/Down:34.3 +reg_write( DDR_REG_BASE + 0x00010049*4 +0x02000000 , 0x00000E38 ); +reg_write( DDR_REG_BASE + 0x00010149*4 +0x02000000 , 0x00000E38 ); +reg_write( DDR_REG_BASE + 0x00011049*4 +0x02000000 , 0x00000E38 ); +reg_write( DDR_REG_BASE + 0x00011149*4 +0x02000000 , 0x00000E38 ); +reg_write( DDR_REG_BASE + 0x00012049*4 +0x02000000 , 0x00000E38 ); +reg_write( DDR_REG_BASE + 0x00012149*4 +0x02000000 , 0x00000E38 ); +reg_write( DDR_REG_BASE + 0x00013049*4 +0x02000000 , 0x00000E38 ); +reg_write( DDR_REG_BASE + 0x00013149*4 +0x02000000 , 0x00000E38 ); +//iteration place +// PHY AC/CLK output impedence +//00000_00000 0x0 120 +//00001_00001 0x21 60 +//00011_00011 0x63 40 +//00111_00111 0xe7 30 +//01111_01111 0x1ef 24 +//11111_11111 0x3ff 20 +// // [phyinit_C_initPhyConfig] Programming ATxImpedance::ADrvStrenP to 0x1 +// // [phyinit_C_initPhyConfig] Programming ATxImpedance::ADrvStrenN to 0x1 +reg_write( DDR_REG_BASE + 0x43 *4+0x02000000,0x63); +reg_write( DDR_REG_BASE + 0x1043 *4+0x02000000,0x63); +reg_write( DDR_REG_BASE + 0x2043 *4+0x02000000,0x63); +reg_write( DDR_REG_BASE + 0x3043 *4+0x02000000,0x63); +reg_write( DDR_REG_BASE + 0x4043 *4+0x02000000,0x63); +reg_write( DDR_REG_BASE + 0x5043 *4+0x02000000,0x63); +reg_write( DDR_REG_BASE + 0x6043 *4+0x02000000,0x63); +reg_write( DDR_REG_BASE + 0x7043 *4+0x02000000,0x63); +reg_write( DDR_REG_BASE + 0x8043 *4+0x02000000,0x63); +reg_write( DDR_REG_BASE + 0x9043 *4+0x02000000,0x63); + +reg_write( DDR_REG_BASE + 0x00020018*4 +0x02000000 , 0x00000005 ); +reg_write( DDR_REG_BASE + 0x00020075*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00020050*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00020008*4 +0x02000000 , 0x00000215 ); +reg_write( DDR_REG_BASE + 0x00020088*4 +0x02000000 , 0x00000009 ); +//iteration place +//PHY VERF +//INSEL VREFIN ALL Ratio +//---(0.005*X+0.345)VDDQ --- +//0x0 0x51 0x288 75% (GlobalVrefInSel to 0x0) +//0x0 0x41 0x208 67% (GlobalVrefInSel to 0x0) +//---(0.005*(X-1)VDDQ---- +//0x4 0x65 0x32c 50% (GlobalVrefInSel to 0x4) +//0x4 0x33 0x19c 25% (GlobalVrefInSel to 0x4) + + +// // [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal::GlobalVrefInDAC to 0x51 +// // [phyinit_C_initPhyConfig] Pstate=0, Programming VrefInGlobal to 0x288 + +//reg_write( DDR_REG_BASE + 0x200b2*4+0x02000000,0x32c);//hyg +//reg_write( DDR_REG_BASE + 0x200b2*4+0x02000000,0x208);//hyg +//reg_write( DDR_REG_BASE + 0x200b2*4+0x02000000,0x32C);//hyg +reg_write( DDR_REG_BASE + 0x000200b2*4 +0x02000000 , 0x00000288 ); +reg_write( DDR_REG_BASE + 0x00010043*4 +0x02000000 , 0x000005b1 ); +reg_write( DDR_REG_BASE + 0x00010143*4 +0x02000000 , 0x000005b1 ); +reg_write( DDR_REG_BASE + 0x00011043*4 +0x02000000 , 0x000005b1 ); +reg_write( DDR_REG_BASE + 0x00011143*4 +0x02000000 , 0x000005b1 ); +reg_write( DDR_REG_BASE + 0x00012043*4 +0x02000000 , 0x000005b1 ); +reg_write( DDR_REG_BASE + 0x00012143*4 +0x02000000 , 0x000005b1 ); +reg_write( DDR_REG_BASE + 0x00013043*4 +0x02000000 , 0x000005b1 ); +reg_write( DDR_REG_BASE + 0x00013143*4 +0x02000000 , 0x000005b1 ); +reg_write( DDR_REG_BASE + 0x000200fa*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00020019*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000200f0*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000200f1*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000200f2*4 +0x02000000 , 0x00004444 ); +reg_write( DDR_REG_BASE + 0x000200f3*4 +0x02000000 , 0x00008888 ); +reg_write( DDR_REG_BASE + 0x000200f4*4 +0x02000000 , 0x00005555 ); +reg_write( DDR_REG_BASE + 0x000200f5*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000200f6*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000200f7*4 +0x02000000 , 0x0000f000 ); +reg_write( DDR_REG_BASE + 0x0001004a*4 +0x02000000 , 0x00000500 ); +reg_write( DDR_REG_BASE + 0x0001104a*4 +0x02000000 , 0x00000500 ); +reg_write( DDR_REG_BASE + 0x0001204a*4 +0x02000000 , 0x00000500 ); +reg_write( DDR_REG_BASE + 0x0001304a*4 +0x02000000 , 0x00000500 ); +reg_write( DDR_REG_BASE + 0x00020025*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0002002c*4 +0x02000000 , 0x00000000 ); + +reg_write(DDR_REG_BASE + 0x20100*4+0x02000000,0x9); //CA0 +reg_write(DDR_REG_BASE + 0x20101*4+0x02000000,0x8); //CA1 +reg_write(DDR_REG_BASE + 0x20102*4+0x02000000,0x7); //CA2 +reg_write(DDR_REG_BASE + 0x20103*4+0x02000000,0x6); //CA3 +reg_write(DDR_REG_BASE + 0x20104*4+0x02000000,0x5); //CA4 +reg_write(DDR_REG_BASE + 0x20105*4+0x02000000,0x4); //CA5 +reg_write(DDR_REG_BASE + 0x20106*4+0x02000000,0x3); //CA6 +reg_write(DDR_REG_BASE + 0x20107*4+0x02000000,0x2); //CA7 +reg_write(DDR_REG_BASE + 0x20108*4+0x02000000,0x1); //CA8 +reg_write(DDR_REG_BASE + 0x20109*4+0x02000000,0x0); //CA9 + reg_write(DDR_REG_BASE + 0x120a0 * 4 + 0x2000000, 0x0); //lndq =1 + reg_write(DDR_REG_BASE + 0x120a1 * 4 + 0x2000000, 0x7); //CA1 =0 + reg_write(DDR_REG_BASE + 0x120a2 * 4 + 0x2000000, 0x2); //CA1 =0 + reg_write(DDR_REG_BASE + 0x120a3 * 4 + 0x2000000, 0x3); //CA1 =0 + reg_write(DDR_REG_BASE + 0x120a4 * 4 + 0x2000000, 0x1); //CA1 =0 + reg_write(DDR_REG_BASE + 0x120a5 * 4 + 0x2000000, 0x5); //CA1 =0 + reg_write(DDR_REG_BASE + 0x120a6 * 4 + 0x2000000, 0x4); //CA1 =0 + reg_write(DDR_REG_BASE + 0x120a7 * 4 + 0x2000000, 0x6); //CA1 =0 + + reg_write(DDR_REG_BASE + 0x110a0 * 4 + 0x2000000, 0x3); //lndq =1 + reg_write(DDR_REG_BASE + 0x110a1 * 4 + 0x2000000, 0x1); //CA1 =0 + reg_write(DDR_REG_BASE + 0x110a2 * 4 + 0x2000000, 0x6); //CA1 =0 + reg_write(DDR_REG_BASE + 0x110a3 * 4 + 0x2000000, 0x0); //CA1 =0 + reg_write(DDR_REG_BASE + 0x110a4 * 4 + 0x2000000, 0x4); //CA1 =0 + reg_write(DDR_REG_BASE + 0x110a5 * 4 + 0x2000000, 0x2); //CA1 =0 + reg_write(DDR_REG_BASE + 0x110a6 * 4 + 0x2000000, 0x5); //CA1 =0 + reg_write(DDR_REG_BASE + 0x110a7 * 4 + 0x2000000, 0x7); //CA1 =0 + + reg_write(DDR_REG_BASE + 0x130a0 * 4 + 0x2000000, 0x0); //lndq =1 + reg_write(DDR_REG_BASE + 0x130a1 * 4 + 0x2000000, 0x1); //CA1 =0 + reg_write(DDR_REG_BASE + 0x130a2 * 4 + 0x2000000, 0x6); //CA1 =0 + reg_write(DDR_REG_BASE + 0x130a3 * 4 + 0x2000000, 0x3); //CA1 =0 + reg_write(DDR_REG_BASE + 0x130a4 * 4 + 0x2000000, 0x2); //CA1 =0 + reg_write(DDR_REG_BASE + 0x130a5 * 4 + 0x2000000, 0x5); //CA1 =0 + reg_write(DDR_REG_BASE + 0x130a6 * 4 + 0x2000000, 0x4); //CA1 =0 + reg_write(DDR_REG_BASE + 0x130a7 * 4 + 0x2000000, 0x7); //CA1 =0 + + reg_write(DDR_REG_BASE + 0x100a0 * 4 + 0x2000000, 0x0); //lndq =1 + reg_write(DDR_REG_BASE + 0x100a1 * 4 + 0x2000000, 0x2); //CA1 =0 + reg_write(DDR_REG_BASE + 0x100a2 * 4 + 0x2000000, 0x1); //CA1 =0 + reg_write(DDR_REG_BASE + 0x100a3 * 4 + 0x2000000, 0x4); //CA1 =0 + reg_write(DDR_REG_BASE + 0x100a4 * 4 + 0x2000000, 0x3); //CA1 =0 + reg_write(DDR_REG_BASE + 0x100a5 * 4 + 0x2000000, 0x6); //CA1 =0 + reg_write(DDR_REG_BASE + 0x100a6 * 4 + 0x2000000, 0x5); //CA1 =0 + reg_write(DDR_REG_BASE + 0x100a7 * 4 + 0x2000000, 0x7); //CA1 =0 + +reg_write( DDR_REG_BASE + 0x00020060*4 +0x02000000 , 0x00000002 ); + +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE +0x50000*4+0x02000000,0xb0); +reg_write( DDR_REG_BASE +0x50001*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50002*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50003*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50004*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50005*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50006*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50007*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50008*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50009*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5000a*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5000b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5000c*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5000d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5000e*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5000f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50010*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50011*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50012*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50013*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50014*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50015*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50016*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50017*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50018*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50019*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5001a*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5001b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5001c*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5001d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5001e*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x5001f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50020*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50021*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50022*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50023*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50024*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50025*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50026*4+0x02000000,0x50); +reg_write( DDR_REG_BASE +0x50027*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50028*4+0x02000000,0x2069); +reg_write( DDR_REG_BASE +0x50029*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x5002a*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x5002b*4+0x02000000,0x7000); +reg_write( DDR_REG_BASE +0x5002c*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x5002d*4+0x02000000,0x7000); +reg_write( DDR_REG_BASE +0x5002e*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x5002f*4+0x02000000,0x7000); +reg_write( DDR_REG_BASE +0x50030*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50031*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50032*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50033*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50034*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50035*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50036*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50037*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50038*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50039*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5003f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50040*4+0x02000000,0x7054); +reg_write( DDR_REG_BASE +0x50041*4+0x02000000,0x7ce0); +reg_write( DDR_REG_BASE +0x50042*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x50043*4+0x02000000,0x1101); +reg_write( DDR_REG_BASE +0x50044*4+0x02000000,0x48c); +reg_write( DDR_REG_BASE +0x50045*4+0x02000000,0x2242); +reg_write( DDR_REG_BASE +0x50046*4+0x02000000,0x8042); +reg_write( DDR_REG_BASE +0x50047*4+0x02000000,0x1b01); +reg_write( DDR_REG_BASE +0x50048*4+0x02000000,0x312); +reg_write( DDR_REG_BASE +0x50049*4+0x02000000,0xf5fb); +reg_write( DDR_REG_BASE +0x5004a*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5004b*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5004c*4+0x02000000,0x2244); +reg_write( DDR_REG_BASE +0x5004d*4+0x02000000,0x8ffc); +reg_write( DDR_REG_BASE +0x5004e*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x5004f*4+0x02000000,0x7000); +reg_write( DDR_REG_BASE +0x50050*4+0x02000000,0x20e8); +reg_write( DDR_REG_BASE +0x50051*4+0x02000000,0x1a2); +reg_write( DDR_REG_BASE +0x50052*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x50053*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50054*4+0x02000000,0x212f); +reg_write( DDR_REG_BASE +0x50055*4+0x02000000,0x4b); +reg_write( DDR_REG_BASE +0x50056*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50057*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50058*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50059*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5005a*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x5005b*4+0x02000000,0x704d); +reg_write( DDR_REG_BASE +0x5005c*4+0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x5005d*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x5005e*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x5005f*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x50060*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x50061*4+0x02000000,0x206a); +reg_write( DDR_REG_BASE +0x50062*4+0x02000000,0x280); +reg_write( DDR_REG_BASE +0x50063*4+0x02000000,0xb88d); +reg_write( DDR_REG_BASE +0x50064*4+0x02000000,0x2029); +reg_write( DDR_REG_BASE +0x50065*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50066*4+0x02000000,0x44db); +reg_write( DDR_REG_BASE +0x50067*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50068*4+0x02000000,0x4000); +reg_write( DDR_REG_BASE +0x50069*4+0x02000000,0x42db); +reg_write( DDR_REG_BASE +0x5006a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5006b*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x5006c*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x5006d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5006e*4+0x02000000,0x2022); +reg_write( DDR_REG_BASE +0x5006f*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50070*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50071*4+0x02000000,0x2130); +reg_write( DDR_REG_BASE +0x50072*4+0x02000000,0x2069); +reg_write( DDR_REG_BASE +0x50073*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x50074*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50075*4+0x02000000,0xf1fe); +reg_write( DDR_REG_BASE +0x50076*4+0x02000000,0xc3e1); +reg_write( DDR_REG_BASE +0x50077*4+0x02000000,0xc2e1); +reg_write( DDR_REG_BASE +0x50078*4+0x02000000,0xc1e1); +reg_write( DDR_REG_BASE +0x50079*4+0x02000000,0xc0e1); +reg_write( DDR_REG_BASE +0x5007a*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x5007b*4+0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x5007c*4+0x02000000,0xe805); +reg_write( DDR_REG_BASE +0x5007d*4+0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x5007e*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x5007f*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50080*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x50081*4+0x02000000,0xda23); +reg_write( DDR_REG_BASE +0x50082*4+0x02000000,0xba9f); +reg_write( DDR_REG_BASE +0x50083*4+0x02000000,0x8a60); +reg_write( DDR_REG_BASE +0x50084*4+0x02000000,0x1226); +reg_write( DDR_REG_BASE +0x50085*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x50086*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x50087*4+0x02000000,0x1aec); +reg_write( DDR_REG_BASE +0x50088*4+0x02000000,0x8002); +reg_write( DDR_REG_BASE +0x50089*4+0x02000000,0x12ef); +reg_write( DDR_REG_BASE +0x5008a*4+0x02000000,0x8080); +reg_write( DDR_REG_BASE +0x5008b*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x5008c*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x5008d*4+0x02000000,0xf20e); +reg_write( DDR_REG_BASE +0x5008e*4+0x02000000,0xc084); +reg_write( DDR_REG_BASE +0x5008f*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50090*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x50091*4+0x02000000,0x9ca); +reg_write( DDR_REG_BASE +0x50092*4+0x02000000,0x260); +reg_write( DDR_REG_BASE +0x50093*4+0x02000000,0xc184); +reg_write( DDR_REG_BASE +0x50094*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50095*4+0x02000000,0x402); +reg_write( DDR_REG_BASE +0x50096*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50097*4+0x02000000,0xf36); +reg_write( DDR_REG_BASE +0x50098*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50099*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5009a*4+0x02000000,0x94e); +reg_write( DDR_REG_BASE +0x5009b*4+0x02000000,0x260); +reg_write( DDR_REG_BASE +0x5009c*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5009d*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5009e*4+0x02000000,0x20ab); +reg_write( DDR_REG_BASE +0x5009f*4+0x02000000,0xc4); +reg_write( DDR_REG_BASE +0x500a0*4+0x02000000,0x7fff); +reg_write( DDR_REG_BASE +0x500a1*4+0x02000000,0xf000); +reg_write( DDR_REG_BASE +0x500a2*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x500a3*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x500a4*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x500a5*4+0x02000000,0xc1a8); +reg_write( DDR_REG_BASE +0x500a6*4+0x02000000,0xc243); +reg_write( DDR_REG_BASE +0x500a7*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x500a8*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x500a9*4+0x02000000,0xc147); +reg_write( DDR_REG_BASE +0x500aa*4+0x02000000,0xa100); +reg_write( DDR_REG_BASE +0x500ab*4+0x02000000,0xc345); +reg_write( DDR_REG_BASE +0x500ac*4+0x02000000,0xc103); +reg_write( DDR_REG_BASE +0x500ad*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x500ae*4+0x02000000,0x1a7); +reg_write( DDR_REG_BASE +0x500af*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x500b0*4+0x02000000,0xa100); +reg_write( DDR_REG_BASE +0x500b1*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x500b2*4+0x02000000,0x815); +reg_write( DDR_REG_BASE +0x500b3*4+0x02000000,0x70); +reg_write( DDR_REG_BASE +0x500b4*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x500b5*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x500b6*4+0x02000000,0xe88b); +reg_write( DDR_REG_BASE +0x500b7*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x500b8*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x500b9*4+0x02000000,0xfcf); +reg_write( DDR_REG_BASE +0x500ba*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x500bb*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x500bc*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x500bd*4+0x02000000,0x228a); +reg_write( DDR_REG_BASE +0x500be*4+0x02000000,0xfcf); +reg_write( DDR_REG_BASE +0x500bf*4+0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x500c0*4+0x02000000,0x280); +reg_write( DDR_REG_BASE +0x500c1*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x500c2*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x500c3*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x500c4*4+0x02000000,0x79d); +reg_write( DDR_REG_BASE +0x500c5*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x500c6*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x500c7*4+0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x500c8*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x500c9*4+0x02000000,0xf058); +reg_write( DDR_REG_BASE +0x500ca*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x500cb*4+0x02000000,0x7000); +reg_write( DDR_REG_BASE +0x500cc*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x500cd*4+0x02000000,0x7a0); +reg_write( DDR_REG_BASE +0x500ce*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x500cf*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x500d0*4+0x02000000,0x54); +reg_write( DDR_REG_BASE +0x500d1*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x500d2*4+0x02000000,0x6c1); +reg_write( DDR_REG_BASE +0x500d3*4+0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x500d4*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x500d5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x500d6*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x500d7*4+0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x500d8*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x500d9*4+0x02000000,0xef6); +reg_write( DDR_REG_BASE +0x500da*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x500db*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x500dc*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x500dd*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x500de*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x500df*4+0x02000000,0x7a0); +reg_write( DDR_REG_BASE +0x500e0*4+0x02000000,0x8002); +reg_write( DDR_REG_BASE +0x500e1*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x500e2*4+0x02000000,0x6c1); +reg_write( DDR_REG_BASE +0x500e3*4+0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x500e4*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x500e5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x500e6*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x500e7*4+0x02000000,0x7e05); +reg_write( DDR_REG_BASE +0x500e8*4+0x02000000,0x9600); +reg_write( DDR_REG_BASE +0x500e9*4+0x02000000,0xed6); +reg_write( DDR_REG_BASE +0x500ea*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x500eb*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x500ec*4+0x02000000,0xc105); +reg_write( DDR_REG_BASE +0x500ed*4+0x02000000,0x42eb); +reg_write( DDR_REG_BASE +0x500ee*4+0x02000000,0xf86c); +reg_write( DDR_REG_BASE +0x500ef*4+0x02000000,0x4759); +reg_write( DDR_REG_BASE +0x500f0*4+0x02000000,0xe90b); +reg_write( DDR_REG_BASE +0x500f1*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x500f2*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x500f3*4+0x02000000,0x7f05); +reg_write( DDR_REG_BASE +0x500f4*4+0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x500f5*4+0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x500f6*4+0x02000000,0x7a05); +reg_write( DDR_REG_BASE +0x500f7*4+0x02000000,0x2247); +reg_write( DDR_REG_BASE +0x500f8*4+0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x500f9*4+0x02000000,0x79e5); +reg_write( DDR_REG_BASE +0x500fa*4+0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x500fb*4+0x02000000,0x42eb); +reg_write( DDR_REG_BASE +0x500fc*4+0x02000000,0xf85a); +reg_write( DDR_REG_BASE +0x500fd*4+0x02000000,0x4759); +reg_write( DDR_REG_BASE +0x500fe*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x500ff*4+0x02000000,0x42eb); +reg_write( DDR_REG_BASE +0x50100*4+0x02000000,0xf845); +reg_write( DDR_REG_BASE +0x50101*4+0x02000000,0x4759); +reg_write( DDR_REG_BASE +0x50102*4+0x02000000,0x272f); +reg_write( DDR_REG_BASE +0x50103*4+0x02000000,0x3382); +reg_write( DDR_REG_BASE +0x50104*4+0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x50105*4+0x02000000,0x3201); +reg_write( DDR_REG_BASE +0x50106*4+0x02000000,0x7985); +reg_write( DDR_REG_BASE +0x50107*4+0x02000000,0xc402); +reg_write( DDR_REG_BASE +0x50108*4+0x02000000,0x42eb); +reg_write( DDR_REG_BASE +0x50109*4+0x02000000,0xf84b); +reg_write( DDR_REG_BASE +0x5010a*4+0x02000000,0x4759); +reg_write( DDR_REG_BASE +0x5010b*4+0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x5010c*4+0x02000000,0x3102); +reg_write( DDR_REG_BASE +0x5010d*4+0x02000000,0x42eb); +reg_write( DDR_REG_BASE +0x5010e*4+0x02000000,0xf858); +reg_write( DDR_REG_BASE +0x5010f*4+0x02000000,0x4759); +reg_write( DDR_REG_BASE +0x50110*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x50111*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50112*4+0x02000000,0x4220); +reg_write( DDR_REG_BASE +0x50113*4+0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x50114*4+0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x50115*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x50116*4+0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x50117*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x50118*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x50119*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x5011a*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x5011b*4+0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x5011c*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x5011d*4+0x02000000,0x8020); +reg_write( DDR_REG_BASE +0x5011e*4+0x02000000,0x7945); +reg_write( DDR_REG_BASE +0x5011f*4+0x02000000,0xa020); +reg_write( DDR_REG_BASE +0x50120*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x50121*4+0x02000000,0x230c); +reg_write( DDR_REG_BASE +0x50122*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x50123*4+0x02000000,0x750); +reg_write( DDR_REG_BASE +0x50124*4+0x02000000,0xffc5); +reg_write( DDR_REG_BASE +0x50125*4+0x02000000,0xf052); +reg_write( DDR_REG_BASE +0x50126*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50127*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50128*4+0x02000000,0x7a0); +reg_write( DDR_REG_BASE +0x50129*4+0x02000000,0x8021); +reg_write( DDR_REG_BASE +0x5012a*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5012b*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x5012c*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x5012d*4+0x02000000,0x54); +reg_write( DDR_REG_BASE +0x5012e*4+0x02000000,0x42eb); +reg_write( DDR_REG_BASE +0x5012f*4+0x02000000,0xf851); +reg_write( DDR_REG_BASE +0x50130*4+0x02000000,0x4759); +reg_write( DDR_REG_BASE +0x50131*4+0x02000000,0xe46); +reg_write( DDR_REG_BASE +0x50132*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50133*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x50134*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x50135*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50136*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50137*4+0x02000000,0x7a0); +reg_write( DDR_REG_BASE +0x50138*4+0x02000000,0x8023); +reg_write( DDR_REG_BASE +0x50139*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5013a*4+0x02000000,0x42eb); +reg_write( DDR_REG_BASE +0x5013b*4+0x02000000,0xf84b); +reg_write( DDR_REG_BASE +0x5013c*4+0x02000000,0x4759); +reg_write( DDR_REG_BASE +0x5013d*4+0x02000000,0xe2e); +reg_write( DDR_REG_BASE +0x5013e*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5013f*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x50140*4+0x02000000,0xc105); +reg_write( DDR_REG_BASE +0x50141*4+0x02000000,0x42eb); +reg_write( DDR_REG_BASE +0x50142*4+0x02000000,0xf842); +reg_write( DDR_REG_BASE +0x50143*4+0x02000000,0x4759); +reg_write( DDR_REG_BASE +0x50144*4+0x02000000,0xe90b); +reg_write( DDR_REG_BASE +0x50145*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x50146*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x50147*4+0x02000000,0x7f05); +reg_write( DDR_REG_BASE +0x50148*4+0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x50149*4+0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x5014a*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x5014b*4+0x02000000,0x2047); +reg_write( DDR_REG_BASE +0x5014c*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x5014d*4+0x02000000,0x78e5); +reg_write( DDR_REG_BASE +0x5014e*4+0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x5014f*4+0x02000000,0x42eb); +reg_write( DDR_REG_BASE +0x50150*4+0x02000000,0xf830); +reg_write( DDR_REG_BASE +0x50151*4+0x02000000,0x4759); +reg_write( DDR_REG_BASE +0x50152*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x50153*4+0x02000000,0x42eb); +reg_write( DDR_REG_BASE +0x50154*4+0x02000000,0xf81b); +reg_write( DDR_REG_BASE +0x50155*4+0x02000000,0x4759); +reg_write( DDR_REG_BASE +0x50156*4+0x02000000,0x272f); +reg_write( DDR_REG_BASE +0x50157*4+0x02000000,0x3382); +reg_write( DDR_REG_BASE +0x50158*4+0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x50159*4+0x02000000,0x3201); +reg_write( DDR_REG_BASE +0x5015a*4+0x02000000,0x7985); +reg_write( DDR_REG_BASE +0x5015b*4+0x02000000,0xc402); +reg_write( DDR_REG_BASE +0x5015c*4+0x02000000,0x42eb); +reg_write( DDR_REG_BASE +0x5015d*4+0x02000000,0xf821); +reg_write( DDR_REG_BASE +0x5015e*4+0x02000000,0x4759); +reg_write( DDR_REG_BASE +0x5015f*4+0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x50160*4+0x02000000,0x3102); +reg_write( DDR_REG_BASE +0x50161*4+0x02000000,0x42eb); +reg_write( DDR_REG_BASE +0x50162*4+0x02000000,0xf82e); +reg_write( DDR_REG_BASE +0x50163*4+0x02000000,0x4759); +reg_write( DDR_REG_BASE +0x50164*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50165*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x50166*4+0x02000000,0x215a); +reg_write( DDR_REG_BASE +0x50167*4+0x02000000,0x201); +reg_write( DDR_REG_BASE +0x50168*4+0x02000000,0xb9c4); +reg_write( DDR_REG_BASE +0x50169*4+0x02000000,0xe906); +reg_write( DDR_REG_BASE +0x5016a*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x5016b*4+0x02000000,0x901); +reg_write( DDR_REG_BASE +0x5016c*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x5016d*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5016e*4+0x02000000,0xc103); +reg_write( DDR_REG_BASE +0x5016f*4+0x02000000,0x8120); +reg_write( DDR_REG_BASE +0x50170*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x50171*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x50172*4+0x02000000,0xa020); +reg_write( DDR_REG_BASE +0x50173*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x50174*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x50175*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x50176*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50177*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50178*4+0x02000000,0x79d); +reg_write( DDR_REG_BASE +0x50179*4+0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x5017a*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5017b*4+0x02000000,0x7030); +reg_write( DDR_REG_BASE +0x5017c*4+0x02000000,0x754); +reg_write( DDR_REG_BASE +0x5017d*4+0x02000000,0xffc5); +reg_write( DDR_REG_BASE +0x5017e*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x5017f*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x50180*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50181*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50182*4+0x02000000,0x7214); +reg_write( DDR_REG_BASE +0x50183*4+0x02000000,0x65e); +reg_write( DDR_REG_BASE +0x50184*4+0x02000000,0xffc5); +reg_write( DDR_REG_BASE +0x50185*4+0x02000000,0xc0a8); +reg_write( DDR_REG_BASE +0x50186*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50187*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50188*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50189*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5018a*4+0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x5018b*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x5018c*4+0x02000000,0x79c5); +reg_write( DDR_REG_BASE +0x5018d*4+0x02000000,0x7c25); +reg_write( DDR_REG_BASE +0x5018e*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x5018f*4+0x02000000,0x7964); +reg_write( DDR_REG_BASE +0x50190*4+0x02000000,0x7985); +reg_write( DDR_REG_BASE +0x50191*4+0x02000000,0x7f25); +reg_write( DDR_REG_BASE +0x50192*4+0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x50193*4+0x02000000,0x308c); +reg_write( DDR_REG_BASE +0x50194*4+0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x50195*4+0x02000000,0x7ce5); +reg_write( DDR_REG_BASE +0x50196*4+0x02000000,0x7f3d); +reg_write( DDR_REG_BASE +0x50197*4+0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x50198*4+0x02000000,0x1101); +reg_write( DDR_REG_BASE +0x50199*4+0x02000000,0x7c25); +reg_write( DDR_REG_BASE +0x5019a*4+0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x5019b*4+0x02000000,0x7e3d); +reg_write( DDR_REG_BASE +0x5019c*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5019d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5019e*4+0x02000000,0x2384); +reg_write( DDR_REG_BASE +0x5019f*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x501a0*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x501a1*4+0x02000000,0x2444); +reg_write( DDR_REG_BASE +0x501a2*4+0x02000000,0x140c); +reg_write( DDR_REG_BASE +0x501a3*4+0x02000000,0x7d85); +reg_write( DDR_REG_BASE +0x501a4*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x501a5*4+0x02000000,0x180c); +reg_write( DDR_REG_BASE +0x501a6*4+0x02000000,0x7ca5); +reg_write( DDR_REG_BASE +0x501a7*4+0x02000000,0x7c65); +reg_write( DDR_REG_BASE +0x501a8*4+0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x501a9*4+0x02000000,0x1083); +reg_write( DDR_REG_BASE +0x501aa*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x501ab*4+0x02000000,0x7b85); +reg_write( DDR_REG_BASE +0x501ac*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x501ad*4+0x02000000,0x7b45); +reg_write( DDR_REG_BASE +0x501ae*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x501af*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x501b0*4+0x02000000,0x255e); +reg_write( DDR_REG_BASE +0x501b1*4+0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x501b2*4+0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x501b3*4+0x02000000,0x110b); +reg_write( DDR_REG_BASE +0x501b4*4+0x02000000,0xdc40); +reg_write( DDR_REG_BASE +0x501b5*4+0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x501b6*4+0x02000000,0x40e); +reg_write( DDR_REG_BASE +0x501b7*4+0x02000000,0x255e); +reg_write( DDR_REG_BASE +0x501b8*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x501b9*4+0x02000000,0x2404); +reg_write( DDR_REG_BASE +0x501ba*4+0x02000000,0x12cc); +reg_write( DDR_REG_BASE +0x501bb*4+0x02000000,0x2584); +reg_write( DDR_REG_BASE +0x501bc*4+0x02000000,0x1002); +reg_write( DDR_REG_BASE +0x501bd*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x501be*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x501bf*4+0x02000000,0x7a65); +reg_write( DDR_REG_BASE +0x501c0*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x501c1*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x501c2*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x501c3*4+0x02000000,0x2087); +reg_write( DDR_REG_BASE +0x501c4*4+0x02000000,0xfc3); +reg_write( DDR_REG_BASE +0x501c5*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x501c6*4+0x02000000,0x7c1d); +reg_write( DDR_REG_BASE +0x501c7*4+0x02000000,0x2444); +reg_write( DDR_REG_BASE +0x501c8*4+0x02000000,0x1042); +reg_write( DDR_REG_BASE +0x501c9*4+0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x501ca*4+0x02000000,0x3300); +reg_write( DDR_REG_BASE +0x501cb*4+0x02000000,0x7bbb); +reg_write( DDR_REG_BASE +0x501cc*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x501cd*4+0x02000000,0x4f); +reg_write( DDR_REG_BASE +0x501ce*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x501cf*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x501d0*4+0x02000000,0x6109); +reg_write( DDR_REG_BASE +0x501d1*4+0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x501d2*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x501d3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x501d4*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x501d5*4+0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x501d6*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x501d7*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x501d8*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x501d9*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x501da*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x501db*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x501dc*4+0x02000000,0x3c0c); +reg_write( DDR_REG_BASE +0x501dd*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x501de*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x501df*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x501e0*4+0x02000000,0xaa); +reg_write( DDR_REG_BASE +0x501e1*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x501e2*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x501e3*4+0x02000000,0x3c02); +reg_write( DDR_REG_BASE +0x501e4*4+0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x501e5*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x501e6*4+0x02000000,0x7384); +reg_write( DDR_REG_BASE +0x501e7*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x501e8*4+0x02000000,0xe0aa); +reg_write( DDR_REG_BASE +0x501e9*4+0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x501ea*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x501eb*4+0x02000000,0x88a0); +reg_write( DDR_REG_BASE +0x501ec*4+0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x501ed*4+0x02000000,0x81); +reg_write( DDR_REG_BASE +0x501ee*4+0x02000000,0x881f); +reg_write( DDR_REG_BASE +0x501ef*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x501f0*4+0x02000000,0x3f83); +reg_write( DDR_REG_BASE +0x501f1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x501f2*4+0x02000000,0x53); +reg_write( DDR_REG_BASE +0x501f3*4+0x02000000,0xc148); +reg_write( DDR_REG_BASE +0x501f4*4+0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x501f5*4+0x02000000,0xc095); +reg_write( DDR_REG_BASE +0x501f6*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x501f7*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x501f8*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x501f9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x501fa*4+0x02000000,0x18c); +reg_write( DDR_REG_BASE +0x501fb*4+0x02000000,0xac6); +reg_write( DDR_REG_BASE +0x501fc*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x501fd*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x501fe*4+0x02000000,0x3cc0); +reg_write( DDR_REG_BASE +0x501ff*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x50200*4+0x02000000,0x265a); +reg_write( DDR_REG_BASE +0x50201*4+0x02000000,0x1602); +reg_write( DDR_REG_BASE +0x50202*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x50203*4+0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x50204*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x50205*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x50206*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x50207*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x50208*4+0x02000000,0x9f7); +reg_write( DDR_REG_BASE +0x50209*4+0x02000000,0x8634); +reg_write( DDR_REG_BASE +0x5020a*4+0x02000000,0xc098); +reg_write( DDR_REG_BASE +0x5020b*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x5020c*4+0x02000000,0xee9); +reg_write( DDR_REG_BASE +0x5020d*4+0x02000000,0x9334); +reg_write( DDR_REG_BASE +0x5020e*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5020f*4+0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x50210*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x50211*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50212*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50213*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x50214*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x50215*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50216*4+0x02000000,0x9001); +reg_write( DDR_REG_BASE +0x50217*4+0x02000000,0xe100); +reg_write( DDR_REG_BASE +0x50218*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x50219*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5021a*4+0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x5021b*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5021c*4+0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x5021d*4+0x02000000,0xc109); +reg_write( DDR_REG_BASE +0x5021e*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x5021f*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50220*4+0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x50221*4+0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x50222*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x50223*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x50224*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50225*4+0x02000000,0xb887); +reg_write( DDR_REG_BASE +0x50226*4+0x02000000,0xa2a); +reg_write( DDR_REG_BASE +0x50227*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50228*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x50229*4+0x02000000,0x563); +reg_write( DDR_REG_BASE +0x5022a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5022b*4+0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x5022c*4+0x02000000,0x2011); +reg_write( DDR_REG_BASE +0x5022d*4+0x02000000,0x83c0); +reg_write( DDR_REG_BASE +0x5022e*4+0x02000000,0x554); +reg_write( DDR_REG_BASE +0x5022f*4+0x02000000,0x21); +reg_write( DDR_REG_BASE +0x50230*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x50231*4+0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x50232*4+0x02000000,0x17c1); +reg_write( DDR_REG_BASE +0x50233*4+0x02000000,0xe906); +reg_write( DDR_REG_BASE +0x50234*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x50235*4+0x02000000,0x901); +reg_write( DDR_REG_BASE +0x50236*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x50237*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x50238*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x50239*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5023a*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x5023b*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x5023c*4+0x02000000,0x3d82); +reg_write( DDR_REG_BASE +0x5023d*4+0x02000000,0x7a34); +reg_write( DDR_REG_BASE +0x5023e*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5023f*4+0x02000000,0x1ac0); +reg_write( DDR_REG_BASE +0x50240*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50241*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x50242*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x50243*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x50244*4+0x02000000,0xf7b7); +reg_write( DDR_REG_BASE +0x50245*4+0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x50246*4+0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x50247*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x50248*4+0x02000000,0x8040); +reg_write( DDR_REG_BASE +0x50249*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x5024a*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x5024b*4+0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x5024c*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x5024d*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x5024e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5024f*4+0x02000000,0x232f); +reg_write( DDR_REG_BASE +0x50250*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x50251*4+0x02000000,0x23c5); +reg_write( DDR_REG_BASE +0x50252*4+0x02000000,0x3062); +reg_write( DDR_REG_BASE +0x50253*4+0x02000000,0xf76); +reg_write( DDR_REG_BASE +0x50254*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50255*4+0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x50256*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x50257*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50258*4+0x02000000,0x758); +reg_write( DDR_REG_BASE +0x50259*4+0x02000000,0x6748); +reg_write( DDR_REG_BASE +0x5025a*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5025b*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5025c*4+0x02000000,0x79d); +reg_write( DDR_REG_BASE +0x5025d*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x5025e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5025f*4+0x02000000,0x7a0); +reg_write( DDR_REG_BASE +0x50260*4+0x02000000,0xa900); +reg_write( DDR_REG_BASE +0x50261*4+0x02000000,0x62f8); +reg_write( DDR_REG_BASE +0x50262*4+0x02000000,0x8862); +reg_write( DDR_REG_BASE +0x50263*4+0x02000000,0x4a6c); +reg_write( DDR_REG_BASE +0x50264*4+0x02000000,0x78f6); +reg_write( DDR_REG_BASE +0x50265*4+0x02000000,0xa503); +reg_write( DDR_REG_BASE +0x50266*4+0x02000000,0x4a4c); +reg_write( DDR_REG_BASE +0x50267*4+0x02000000,0x78f6); +reg_write( DDR_REG_BASE +0x50268*4+0x02000000,0xa502); +reg_write( DDR_REG_BASE +0x50269*4+0x02000000,0x4a2c); +reg_write( DDR_REG_BASE +0x5026a*4+0x02000000,0x78f6); +reg_write( DDR_REG_BASE +0x5026b*4+0x02000000,0xa501); +reg_write( DDR_REG_BASE +0x5026c*4+0x02000000,0x6a04); +reg_write( DDR_REG_BASE +0x5026d*4+0x02000000,0x78f6); +reg_write( DDR_REG_BASE +0x5026e*4+0x02000000,0xa500); +reg_write( DDR_REG_BASE +0x5026f*4+0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x50270*4+0x02000000,0xf3a); +reg_write( DDR_REG_BASE +0x50271*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50272*4+0x02000000,0xa961); +reg_write( DDR_REG_BASE +0x50273*4+0x02000000,0xe524); +reg_write( DDR_REG_BASE +0x50274*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x50275*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50276*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x50277*4+0x02000000,0xd929); +reg_write( DDR_REG_BASE +0x50278*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50279*4+0x02000000,0x7382); +reg_write( DDR_REG_BASE +0x5027a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5027b*4+0x02000000,0x6b4); +reg_write( DDR_REG_BASE +0x5027c*4+0x02000000,0xe7a); +reg_write( DDR_REG_BASE +0x5027d*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x5027e*4+0x02000000,0xdaa4); +reg_write( DDR_REG_BASE +0x5027f*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x50280*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50281*4+0x02000000,0x774c); +reg_write( DDR_REG_BASE +0x50282*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x50283*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x50284*4+0x02000000,0x780); +reg_write( DDR_REG_BASE +0x50285*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x50286*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50287*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x50288*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x50289*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5028a*4+0x02000000,0x90a0); +reg_write( DDR_REG_BASE +0x5028b*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5028c*4+0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x5028d*4+0x02000000,0xff7); +reg_write( DDR_REG_BASE +0x5028e*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x5028f*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x50290*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50291*4+0x02000000,0xad2); +reg_write( DDR_REG_BASE +0x50292*4+0x02000000,0x2a0); +reg_write( DDR_REG_BASE +0x50293*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50294*4+0x02000000,0x2504); +reg_write( DDR_REG_BASE +0x50295*4+0x02000000,0x1f8d); +reg_write( DDR_REG_BASE +0x50296*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50297*4+0x02000000,0xffbf); +reg_write( DDR_REG_BASE +0x50298*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x50299*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x5029a*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5029b*4+0x02000000,0x7344); +reg_write( DDR_REG_BASE +0x5029c*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x5029d*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x5029e*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5029f*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x502a0*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x502a1*4+0x02000000,0xe048); +reg_write( DDR_REG_BASE +0x502a2*4+0x02000000,0x91e); +reg_write( DDR_REG_BASE +0x502a3*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x502a4*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x502a5*4+0x02000000,0xae6); +reg_write( DDR_REG_BASE +0x502a6*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x502a7*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x502a8*4+0x02000000,0x7382); +reg_write( DDR_REG_BASE +0x502a9*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x502aa*4+0x02000000,0x6b4); +reg_write( DDR_REG_BASE +0x502ab*4+0x02000000,0xec6); +reg_write( DDR_REG_BASE +0x502ac*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x502ad*4+0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x502ae*4+0x02000000,0x906); +reg_write( DDR_REG_BASE +0x502af*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x502b0*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x502b1*4+0x02000000,0x289); +reg_write( DDR_REG_BASE +0x502b2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x502b3*4+0x02000000,0x22b); +reg_write( DDR_REG_BASE +0x502b4*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x502b5*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x502b6*4+0x02000000,0xd840); +reg_write( DDR_REG_BASE +0x502b7*4+0x02000000,0x1453); +reg_write( DDR_REG_BASE +0x502b8*4+0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x502b9*4+0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x502ba*4+0x02000000,0x2553); +reg_write( DDR_REG_BASE +0x502bb*4+0x02000000,0x110c); +reg_write( DDR_REG_BASE +0x502bc*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x502bd*4+0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x502be*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x502bf*4+0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x502c0*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x502c1*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x502c2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x502c3*4+0x02000000,0x18c); +reg_write( DDR_REG_BASE +0x502c4*4+0x02000000,0x6049); +reg_write( DDR_REG_BASE +0x502c5*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x502c6*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x502c7*4+0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x502c8*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x502c9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x502ca*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x502cb*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x502cc*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x502cd*4+0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x502ce*4+0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x502cf*4+0x02000000,0xb080); +reg_write( DDR_REG_BASE +0x502d0*4+0x02000000,0xae1); +reg_write( DDR_REG_BASE +0x502d1*4+0x02000000,0x80c4); +reg_write( DDR_REG_BASE +0x502d2*4+0x02000000,0x8d2); +reg_write( DDR_REG_BASE +0x502d3*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x502d4*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x502d5*4+0x02000000,0x7bcf); +reg_write( DDR_REG_BASE +0x502d6*4+0x02000000,0xc18d); +reg_write( DDR_REG_BASE +0x502d7*4+0x02000000,0xb9a); +reg_write( DDR_REG_BASE +0x502d8*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x502d9*4+0x02000000,0xc293); +reg_write( DDR_REG_BASE +0x502da*4+0x02000000,0xeeb); +reg_write( DDR_REG_BASE +0x502db*4+0x02000000,0x1010); +reg_write( DDR_REG_BASE +0x502dc*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x502dd*4+0x02000000,0xe838); +reg_write( DDR_REG_BASE +0x502de*4+0x02000000,0xc40d); +reg_write( DDR_REG_BASE +0x502df*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x502e0*4+0x02000000,0x3d82); +reg_write( DDR_REG_BASE +0x502e1*4+0x02000000,0x22f4); +reg_write( DDR_REG_BASE +0x502e2*4+0x02000000,0x343); +reg_write( DDR_REG_BASE +0x502e3*4+0x02000000,0x4081); +reg_write( DDR_REG_BASE +0x502e4*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x502e5*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x502e6*4+0x02000000,0x245e); +reg_write( DDR_REG_BASE +0x502e7*4+0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x502e8*4+0x02000000,0x7263); +reg_write( DDR_REG_BASE +0x502e9*4+0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x502ea*4+0x02000000,0x401); +reg_write( DDR_REG_BASE +0x502eb*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x502ec*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x502ed*4+0x02000000,0x7965); +reg_write( DDR_REG_BASE +0x502ee*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x502ef*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x502f0*4+0x02000000,0x789d); +reg_write( DDR_REG_BASE +0x502f1*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x502f2*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x502f3*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x502f4*4+0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x502f5*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x502f6*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x502f7*4+0x02000000,0x401); +reg_write( DDR_REG_BASE +0x502f8*4+0x02000000,0x1240); +reg_write( DDR_REG_BASE +0x502f9*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x502fa*4+0x02000000,0x7b84); +reg_write( DDR_REG_BASE +0x502fb*4+0x02000000,0x7965); +reg_write( DDR_REG_BASE +0x502fc*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x502fd*4+0x02000000,0x1a40); +reg_write( DDR_REG_BASE +0x502fe*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x502ff*4+0x02000000,0x4081); +reg_write( DDR_REG_BASE +0x50300*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x50301*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x50302*4+0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x50303*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x50304*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50305*4+0x02000000,0xd90c); +reg_write( DDR_REG_BASE +0x50306*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x50307*4+0x02000000,0x901); +reg_write( DDR_REG_BASE +0x50308*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x50309*4+0x02000000,0x7c9d); +reg_write( DDR_REG_BASE +0x5030a*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x5030b*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x5030c*4+0x02000000,0x2444); +reg_write( DDR_REG_BASE +0x5030d*4+0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x5030e*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x5030f*4+0x02000000,0x1280); +reg_write( DDR_REG_BASE +0x50310*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x50311*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50312*4+0x02000000,0x1a80); +reg_write( DDR_REG_BASE +0x50313*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50314*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x50315*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x50316*4+0x02000000,0xf2b0); +reg_write( DDR_REG_BASE +0x50317*4+0x02000000,0xc113); +reg_write( DDR_REG_BASE +0x50318*4+0x02000000,0x228a); +reg_write( DDR_REG_BASE +0x50319*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x5031a*4+0x02000000,0xdc0c); +reg_write( DDR_REG_BASE +0x5031b*4+0x02000000,0x783d); +reg_write( DDR_REG_BASE +0x5031c*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5031d*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5031e*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5031f*4+0x02000000,0x7a24); +reg_write( DDR_REG_BASE +0x50320*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x50321*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x50322*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x50323*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x50324*4+0x02000000,0x3d82); +reg_write( DDR_REG_BASE +0x50325*4+0x02000000,0x7263); +reg_write( DDR_REG_BASE +0x50326*4+0x02000000,0x2255); +reg_write( DDR_REG_BASE +0x50327*4+0x02000000,0xc02); +reg_write( DDR_REG_BASE +0x50328*4+0x02000000,0x1240); +reg_write( DDR_REG_BASE +0x50329*4+0x02000000,0x103); +reg_write( DDR_REG_BASE +0x5032a*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x5032b*4+0x02000000,0x1a40); +reg_write( DDR_REG_BASE +0x5032c*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5032d*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x5032e*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x5032f*4+0x02000000,0xbb61); +reg_write( DDR_REG_BASE +0x50330*4+0x02000000,0xbff); +reg_write( DDR_REG_BASE +0x50331*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x50332*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50333*4+0x02000000,0x4320); +reg_write( DDR_REG_BASE +0x50334*4+0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x50335*4+0x02000000,0xc01); +reg_write( DDR_REG_BASE +0x50336*4+0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x50337*4+0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x50338*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x50339*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x5033a*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x5033b*4+0x02000000,0x403); +reg_write( DDR_REG_BASE +0x5033c*4+0x02000000,0x7b05); +reg_write( DDR_REG_BASE +0x5033d*4+0x02000000,0x1280); +reg_write( DDR_REG_BASE +0x5033e*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x5033f*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x50340*4+0x02000000,0x1a80); +reg_write( DDR_REG_BASE +0x50341*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50342*4+0x02000000,0x215e); +reg_write( DDR_REG_BASE +0x50343*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x50344*4+0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x50345*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50346*4+0x02000000,0x9260); +reg_write( DDR_REG_BASE +0x50347*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x50348*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x50349*4+0x02000000,0x2184); +reg_write( DDR_REG_BASE +0x5034a*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x5034b*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x5034c*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x5034d*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x5034e*4+0x02000000,0xf078); +reg_write( DDR_REG_BASE +0x5034f*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x50350*4+0x02000000,0xe83a); +reg_write( DDR_REG_BASE +0x50351*4+0x02000000,0xc40d); +reg_write( DDR_REG_BASE +0x50352*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x50353*4+0x02000000,0x3d83); +reg_write( DDR_REG_BASE +0x50354*4+0x02000000,0x23f4); +reg_write( DDR_REG_BASE +0x50355*4+0x02000000,0x342); +reg_write( DDR_REG_BASE +0x50356*4+0x02000000,0x789b); +reg_write( DDR_REG_BASE +0x50357*4+0x02000000,0x2453); +reg_write( DDR_REG_BASE +0x50358*4+0x02000000,0x10c1); +reg_write( DDR_REG_BASE +0x50359*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x5035a*4+0x02000000,0x807); +reg_write( DDR_REG_BASE +0x5035b*4+0x02000000,0x7945); +reg_write( DDR_REG_BASE +0x5035c*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x5035d*4+0x02000000,0x7363); +reg_write( DDR_REG_BASE +0x5035e*4+0x02000000,0xb300); +reg_write( DDR_REG_BASE +0x5035f*4+0x02000000,0x789d); +reg_write( DDR_REG_BASE +0x50360*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50361*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50362*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50363*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50364*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50365*4+0x02000000,0x4181); +reg_write( DDR_REG_BASE +0x50366*4+0x02000000,0xda08); +reg_write( DDR_REG_BASE +0x50367*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50368*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x50369*4+0x02000000,0xa01); +reg_write( DDR_REG_BASE +0x5036a*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x5036b*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x5036c*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x5036d*4+0x02000000,0x807); +reg_write( DDR_REG_BASE +0x5036e*4+0x02000000,0xb9c3); +reg_write( DDR_REG_BASE +0x5036f*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x50370*4+0x02000000,0x1340); +reg_write( DDR_REG_BASE +0x50371*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x50372*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50373*4+0x02000000,0x1b40); +reg_write( DDR_REG_BASE +0x50374*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50375*4+0x02000000,0x4081); +reg_write( DDR_REG_BASE +0x50376*4+0x02000000,0xd910); +reg_write( DDR_REG_BASE +0x50377*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x50378*4+0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x50379*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x5037a*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5037b*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x5037c*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x5037d*4+0x02000000,0x901); +reg_write( DDR_REG_BASE +0x5037e*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x5037f*4+0x02000000,0x7c9d); +reg_write( DDR_REG_BASE +0x50380*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x50381*4+0x02000000,0xc03); +reg_write( DDR_REG_BASE +0x50382*4+0x02000000,0x2444); +reg_write( DDR_REG_BASE +0x50383*4+0x02000000,0x1781); +reg_write( DDR_REG_BASE +0x50384*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x50385*4+0x02000000,0x1380); +reg_write( DDR_REG_BASE +0x50386*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x50387*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50388*4+0x02000000,0x1b80); +reg_write( DDR_REG_BASE +0x50389*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5038a*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x5038b*4+0x02000000,0xe83c); +reg_write( DDR_REG_BASE +0x5038c*4+0x02000000,0xc213); +reg_write( DDR_REG_BASE +0x5038d*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x5038e*4+0x02000000,0xdc0f); +reg_write( DDR_REG_BASE +0x5038f*4+0x02000000,0x785d); +reg_write( DDR_REG_BASE +0x50390*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50391*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50392*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50393*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50394*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50395*4+0x02000000,0x4140); +reg_write( DDR_REG_BASE +0x50396*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50397*4+0x02000000,0xbb61); +reg_write( DDR_REG_BASE +0x50398*4+0x02000000,0xbff); +reg_write( DDR_REG_BASE +0x50399*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x5039a*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x5039b*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x5039c*4+0x02000000,0x807); +reg_write( DDR_REG_BASE +0x5039d*4+0x02000000,0xb9c3); +reg_write( DDR_REG_BASE +0x5039e*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x5039f*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x503a0*4+0x02000000,0x3d81); +reg_write( DDR_REG_BASE +0x503a1*4+0x02000000,0x7163); +reg_write( DDR_REG_BASE +0x503a2*4+0x02000000,0x2155); +reg_write( DDR_REG_BASE +0x503a3*4+0x02000000,0xc01); +reg_write( DDR_REG_BASE +0x503a4*4+0x02000000,0x1140); +reg_write( DDR_REG_BASE +0x503a5*4+0x02000000,0x103); +reg_write( DDR_REG_BASE +0x503a6*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x503a7*4+0x02000000,0x1940); +reg_write( DDR_REG_BASE +0x503a8*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x503a9*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x503aa*4+0x02000000,0xdb10); +reg_write( DDR_REG_BASE +0x503ab*4+0x02000000,0xbb61); +reg_write( DDR_REG_BASE +0x503ac*4+0x02000000,0xbff); +reg_write( DDR_REG_BASE +0x503ad*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x503ae*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x503af*4+0x02000000,0x4340); +reg_write( DDR_REG_BASE +0x503b0*4+0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x503b1*4+0x02000000,0xc01); +reg_write( DDR_REG_BASE +0x503b2*4+0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x503b3*4+0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x503b4*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x503b5*4+0x02000000,0xc03); +reg_write( DDR_REG_BASE +0x503b6*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x503b7*4+0x02000000,0x783); +reg_write( DDR_REG_BASE +0x503b8*4+0x02000000,0x7b05); +reg_write( DDR_REG_BASE +0x503b9*4+0x02000000,0x1180); +reg_write( DDR_REG_BASE +0x503ba*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x503bb*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x503bc*4+0x02000000,0x1980); +reg_write( DDR_REG_BASE +0x503bd*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x503be*4+0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x503bf*4+0x02000000,0x7b5b); +reg_write( DDR_REG_BASE +0x503c0*4+0x02000000,0xbac3); +reg_write( DDR_REG_BASE +0x503c1*4+0x02000000,0x2384); +reg_write( DDR_REG_BASE +0x503c2*4+0x02000000,0x807); +reg_write( DDR_REG_BASE +0x503c3*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x503c4*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x503c5*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x503c6*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x503c7*4+0x02000000,0xe5c0); +reg_write( DDR_REG_BASE +0x503c8*4+0x02000000,0x5dc); +reg_write( DDR_REG_BASE +0x503c9*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x503ca*4+0x02000000,0x79bb); +reg_write( DDR_REG_BASE +0x503cb*4+0x02000000,0xeea9); +reg_write( DDR_REG_BASE +0x503cc*4+0x02000000,0xeca); +reg_write( DDR_REG_BASE +0x503cd*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x503ce*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x503cf*4+0x02000000,0xfe2); +reg_write( DDR_REG_BASE +0x503d0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x503d1*4+0x02000000,0xec2); +reg_write( DDR_REG_BASE +0x503d2*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x503d3*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x503d4*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x503d5*4+0x02000000,0xd930); +reg_write( DDR_REG_BASE +0x503d6*4+0x02000000,0xbc6); +reg_write( DDR_REG_BASE +0x503d7*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x503d8*4+0x02000000,0xdac0); +reg_write( DDR_REG_BASE +0x503d9*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x503da*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x503db*4+0x02000000,0x774c); +reg_write( DDR_REG_BASE +0x503dc*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x503dd*4+0x02000000,0xfffe); +reg_write( DDR_REG_BASE +0x503de*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x503df*4+0x02000000,0x90a0); +reg_write( DDR_REG_BASE +0x503e0*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x503e1*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x503e2*4+0x02000000,0x82e); +reg_write( DDR_REG_BASE +0x503e3*4+0x02000000,0x2a0); +reg_write( DDR_REG_BASE +0x503e4*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x503e5*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x503e6*4+0x02000000,0x2504); +reg_write( DDR_REG_BASE +0x503e7*4+0x02000000,0x1f8d); +reg_write( DDR_REG_BASE +0x503e8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x503e9*4+0x02000000,0xffbf); +reg_write( DDR_REG_BASE +0x503ea*4+0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x503eb*4+0x02000000,0xe8e); +reg_write( DDR_REG_BASE +0x503ec*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x503ed*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x503ee*4+0x02000000,0x852); +reg_write( DDR_REG_BASE +0x503ef*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x503f0*4+0x02000000,0xe82); +reg_write( DDR_REG_BASE +0x503f1*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x503f2*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x503f3*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x503f4*4+0x02000000,0x72d5); +reg_write( DDR_REG_BASE +0x503f5*4+0x02000000,0x57e); +reg_write( DDR_REG_BASE +0x503f6*4+0x02000000,0xffc5); +reg_write( DDR_REG_BASE +0x503f7*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x503f8*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x503f9*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x503fa*4+0x02000000,0x7043); +reg_write( DDR_REG_BASE +0x503fb*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x503fc*4+0x02000000,0x6b4); +reg_write( DDR_REG_BASE +0x503fd*4+0x02000000,0xe7e); +reg_write( DDR_REG_BASE +0x503fe*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x503ff*4+0x02000000,0xb0c0); +reg_write( DDR_REG_BASE +0x50400*4+0x02000000,0xe62); +reg_write( DDR_REG_BASE +0x50401*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50402*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x50403*4+0x02000000,0xf7a); +reg_write( DDR_REG_BASE +0x50404*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50405*4+0x02000000,0xe5a); +reg_write( DDR_REG_BASE +0x50406*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50407*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x50408*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50409*4+0x02000000,0xd92a); +reg_write( DDR_REG_BASE +0x5040a*4+0x02000000,0xb5e); +reg_write( DDR_REG_BASE +0x5040b*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x5040c*4+0x02000000,0xdaa8); +reg_write( DDR_REG_BASE +0x5040d*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5040e*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5040f*4+0x02000000,0x774c); +reg_write( DDR_REG_BASE +0x50410*4+0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x50411*4+0x02000000,0xfef); +reg_write( DDR_REG_BASE +0x50412*4+0x02000000,0x90a0); +reg_write( DDR_REG_BASE +0x50413*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x50414*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50415*4+0x02000000,0xfca); +reg_write( DDR_REG_BASE +0x50416*4+0x02000000,0x260); +reg_write( DDR_REG_BASE +0x50417*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x50418*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x50419*4+0x02000000,0x2504); +reg_write( DDR_REG_BASE +0x5041a*4+0x02000000,0x1f8d); +reg_write( DDR_REG_BASE +0x5041b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5041c*4+0x02000000,0xffbf); +reg_write( DDR_REG_BASE +0x5041d*4+0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x5041e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5041f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50420*4+0x02000000,0xbb8); +reg_write( DDR_REG_BASE +0x50421*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50422*4+0x02000000,0x7384); +reg_write( DDR_REG_BASE +0x50423*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x50424*4+0x02000000,0xe048); +reg_write( DDR_REG_BASE +0x50425*4+0x02000000,0xe72); +reg_write( DDR_REG_BASE +0x50426*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50427*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50428*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x50429*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5042a*4+0x02000000,0x94); +reg_write( DDR_REG_BASE +0x5042b*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5042c*4+0x02000000,0x80a); +reg_write( DDR_REG_BASE +0x5042d*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5042e*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x5042f*4+0x02000000,0xf0a5); +reg_write( DDR_REG_BASE +0x50430*4+0x02000000,0x2332); +reg_write( DDR_REG_BASE +0x50431*4+0x02000000,0x3380); +reg_write( DDR_REG_BASE +0x50432*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x50433*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x50434*4+0x02000000,0xf29e); +reg_write( DDR_REG_BASE +0x50435*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x50436*4+0x02000000,0x899); +reg_write( DDR_REG_BASE +0x50437*4+0x02000000,0x30); +reg_write( DDR_REG_BASE +0x50438*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x50439*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5043a*4+0x02000000,0x95); +reg_write( DDR_REG_BASE +0x5043b*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5043c*4+0x02000000,0xfea); +reg_write( DDR_REG_BASE +0x5043d*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5043e*4+0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x5043f*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50440*4+0x02000000,0xf038); +reg_write( DDR_REG_BASE +0x50441*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50442*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x50443*4+0x02000000,0xf019); +reg_write( DDR_REG_BASE +0x50444*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x50445*4+0x02000000,0x3d81); +reg_write( DDR_REG_BASE +0x50446*4+0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x50447*4+0x02000000,0x81); +reg_write( DDR_REG_BASE +0x50448*4+0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x50449*4+0x02000000,0x17c3); +reg_write( DDR_REG_BASE +0x5044a*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x5044b*4+0x02000000,0xeb06); +reg_write( DDR_REG_BASE +0x5044c*4+0x02000000,0xbb61); +reg_write( DDR_REG_BASE +0x5044d*4+0x02000000,0xb01); +reg_write( DDR_REG_BASE +0x5044e*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x5044f*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50450*4+0x02000000,0xb9c0); +reg_write( DDR_REG_BASE +0x50451*4+0x02000000,0x4320); +reg_write( DDR_REG_BASE +0x50452*4+0x02000000,0x2444); +reg_write( DDR_REG_BASE +0x50453*4+0x02000000,0x17c1); +reg_write( DDR_REG_BASE +0x50454*4+0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x50455*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x50456*4+0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x50457*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x50458*4+0x02000000,0x7b7b); +reg_write( DDR_REG_BASE +0x50459*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x5045a*4+0x02000000,0x7b05); +reg_write( DDR_REG_BASE +0x5045b*4+0x02000000,0xcd5); +reg_write( DDR_REG_BASE +0x5045c*4+0x02000000,0x9234); +reg_write( DDR_REG_BASE +0x5045d*4+0x02000000,0x786f); +reg_write( DDR_REG_BASE +0x5045e*4+0x02000000,0x2332); +reg_write( DDR_REG_BASE +0x5045f*4+0x02000000,0x3382); +reg_write( DDR_REG_BASE +0x50460*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x50461*4+0x02000000,0x3c01); +reg_write( DDR_REG_BASE +0x50462*4+0x02000000,0x6149); +reg_write( DDR_REG_BASE +0x50463*4+0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x50464*4+0x02000000,0x602); +reg_write( DDR_REG_BASE +0x50465*4+0x02000000,0xc198); +reg_write( DDR_REG_BASE +0x50466*4+0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x50467*4+0x02000000,0x7abd); +reg_write( DDR_REG_BASE +0x50468*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x50469*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x5046a*4+0x02000000,0x623a); +reg_write( DDR_REG_BASE +0x5046b*4+0x02000000,0x8a20); +reg_write( DDR_REG_BASE +0x5046c*4+0x02000000,0x7965); +reg_write( DDR_REG_BASE +0x5046d*4+0x02000000,0xed2); +reg_write( DDR_REG_BASE +0x5046e*4+0x02000000,0x1a0); +reg_write( DDR_REG_BASE +0x5046f*4+0x02000000,0xaa20); +reg_write( DDR_REG_BASE +0x50470*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x50471*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50472*4+0x02000000,0x96); +reg_write( DDR_REG_BASE +0x50473*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50474*4+0x02000000,0xf7a); +reg_write( DDR_REG_BASE +0x50475*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50476*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x50477*4+0x02000000,0xe508); +reg_write( DDR_REG_BASE +0x50478*4+0x02000000,0xe5e0); +reg_write( DDR_REG_BASE +0x50479*4+0x02000000,0x792); +reg_write( DDR_REG_BASE +0x5047a*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x5047b*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x5047c*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5047d*4+0x02000000,0x97); +reg_write( DDR_REG_BASE +0x5047e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5047f*4+0x02000000,0xf66); +reg_write( DDR_REG_BASE +0x50480*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50481*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x50482*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x50483*4+0x02000000,0x8a1); +reg_write( DDR_REG_BASE +0x50484*4+0x02000000,0x30); +reg_write( DDR_REG_BASE +0x50485*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x50486*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50487*4+0x02000000,0x98); +reg_write( DDR_REG_BASE +0x50488*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50489*4+0x02000000,0xf52); +reg_write( DDR_REG_BASE +0x5048a*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5048b*4+0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x5048c*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x5048d*4+0x02000000,0xf03c); +reg_write( DDR_REG_BASE +0x5048e*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5048f*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x50490*4+0x02000000,0xf019); +reg_write( DDR_REG_BASE +0x50491*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x50492*4+0x02000000,0x3d81); +reg_write( DDR_REG_BASE +0x50493*4+0x02000000,0x7974); +reg_write( DDR_REG_BASE +0x50494*4+0x02000000,0x11c0); +reg_write( DDR_REG_BASE +0x50495*4+0x02000000,0x101); +reg_write( DDR_REG_BASE +0x50496*4+0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x50497*4+0x02000000,0x17c2); +reg_write( DDR_REG_BASE +0x50498*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x50499*4+0x02000000,0xea06); +reg_write( DDR_REG_BASE +0x5049a*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x5049b*4+0x02000000,0xa01); +reg_write( DDR_REG_BASE +0x5049c*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x5049d*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x5049e*4+0x02000000,0xb9c0); +reg_write( DDR_REG_BASE +0x5049f*4+0x02000000,0x4220); +reg_write( DDR_REG_BASE +0x504a0*4+0x02000000,0x2444); +reg_write( DDR_REG_BASE +0x504a1*4+0x02000000,0x17c1); +reg_write( DDR_REG_BASE +0x504a2*4+0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x504a3*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x504a4*4+0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x504a5*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x504a6*4+0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x504a7*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x504a8*4+0x02000000,0x7a05); +reg_write( DDR_REG_BASE +0x504a9*4+0x02000000,0xcd3); +reg_write( DDR_REG_BASE +0x504aa*4+0x02000000,0x9234); +reg_write( DDR_REG_BASE +0x504ab*4+0x02000000,0x784f); +reg_write( DDR_REG_BASE +0x504ac*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x504ad*4+0x02000000,0x3cc1); +reg_write( DDR_REG_BASE +0x504ae*4+0x02000000,0x61d9); +reg_write( DDR_REG_BASE +0x504af*4+0x02000000,0x896c); +reg_write( DDR_REG_BASE +0x504b0*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x504b1*4+0x02000000,0x3c01); +reg_write( DDR_REG_BASE +0x504b2*4+0x02000000,0x6169); +reg_write( DDR_REG_BASE +0x504b3*4+0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x504b4*4+0x02000000,0x603); +reg_write( DDR_REG_BASE +0x504b5*4+0x02000000,0xc198); +reg_write( DDR_REG_BASE +0x504b6*4+0x02000000,0x6179); +reg_write( DDR_REG_BASE +0x504b7*4+0x02000000,0x7bbd); +reg_write( DDR_REG_BASE +0x504b8*4+0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x504b9*4+0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x504ba*4+0x02000000,0x633b); +reg_write( DDR_REG_BASE +0x504bb*4+0x02000000,0x8b20); +reg_write( DDR_REG_BASE +0x504bc*4+0x02000000,0x7945); +reg_write( DDR_REG_BASE +0x504bd*4+0x02000000,0xe32); +reg_write( DDR_REG_BASE +0x504be*4+0x02000000,0x1a0); +reg_write( DDR_REG_BASE +0x504bf*4+0x02000000,0xab20); +reg_write( DDR_REG_BASE +0x504c0*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x504c1*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x504c2*4+0x02000000,0x99); +reg_write( DDR_REG_BASE +0x504c3*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x504c4*4+0x02000000,0xeda); +reg_write( DDR_REG_BASE +0x504c5*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x504c6*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x504c7*4+0x02000000,0xe508); +reg_write( DDR_REG_BASE +0x504c8*4+0x02000000,0xe5e0); +reg_write( DDR_REG_BASE +0x504c9*4+0x02000000,0x78c); +reg_write( DDR_REG_BASE +0x504ca*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x504cb*4+0x02000000,0x43a1); +reg_write( DDR_REG_BASE +0x504cc*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x504cd*4+0x02000000,0x9a); +reg_write( DDR_REG_BASE +0x504ce*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x504cf*4+0x02000000,0xec6); +reg_write( DDR_REG_BASE +0x504d0*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x504d1*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x504d2*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x504d3*4+0x02000000,0xe689); +reg_write( DDR_REG_BASE +0x504d4*4+0x02000000,0x6b8); +reg_write( DDR_REG_BASE +0x504d5*4+0x02000000,0xffee); +reg_write( DDR_REG_BASE +0x504d6*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x504d7*4+0x02000000,0x3cdb); +reg_write( DDR_REG_BASE +0x504d8*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x504d9*4+0x02000000,0x72f5); +reg_write( DDR_REG_BASE +0x504da*4+0x02000000,0x2a2); +reg_write( DDR_REG_BASE +0x504db*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x504dc*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x504dd*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x504de*4+0x02000000,0xcba); +reg_write( DDR_REG_BASE +0x504df*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x504e0*4+0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x504e1*4+0x02000000,0xf0c1); +reg_write( DDR_REG_BASE +0x504e2*4+0x02000000,0x1453); +reg_write( DDR_REG_BASE +0x504e3*4+0x02000000,0x308e); +reg_write( DDR_REG_BASE +0x504e4*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x504e5*4+0x02000000,0xf062); +reg_write( DDR_REG_BASE +0x504e6*4+0x02000000,0xc095); +reg_write( DDR_REG_BASE +0x504e7*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x504e8*4+0x02000000,0x6c0); +reg_write( DDR_REG_BASE +0x504e9*4+0x02000000,0xdbb); +reg_write( DDR_REG_BASE +0x504ea*4+0x02000000,0x1021); +reg_write( DDR_REG_BASE +0x504eb*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x504ec*4+0x02000000,0xdbff); +reg_write( DDR_REG_BASE +0x504ed*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x504ee*4+0x02000000,0x4718); +reg_write( DDR_REG_BASE +0x504ef*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x504f0*4+0x02000000,0xf031); +reg_write( DDR_REG_BASE +0x504f1*4+0x02000000,0xf20f); +reg_write( DDR_REG_BASE +0x504f2*4+0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x504f3*4+0x02000000,0x7ca); +reg_write( DDR_REG_BASE +0x504f4*4+0x02000000,0x41e3); +reg_write( DDR_REG_BASE +0x504f5*4+0x02000000,0xa11); +reg_write( DDR_REG_BASE +0x504f6*4+0x02000000,0x1010); +reg_write( DDR_REG_BASE +0x504f7*4+0x02000000,0x2242); +reg_write( DDR_REG_BASE +0x504f8*4+0x02000000,0x104a); +reg_write( DDR_REG_BASE +0x504f9*4+0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x504fa*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x504fb*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x504fc*4+0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x504fd*4+0x02000000,0x4b); +reg_write( DDR_REG_BASE +0x504fe*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x504ff*4+0x02000000,0x2454); +reg_write( DDR_REG_BASE +0x50500*4+0x02000000,0x3c0b); +reg_write( DDR_REG_BASE +0x50501*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x50502*4+0x02000000,0x3601); +reg_write( DDR_REG_BASE +0x50503*4+0x02000000,0x2300); +reg_write( DDR_REG_BASE +0x50504*4+0x02000000,0x104b); +reg_write( DDR_REG_BASE +0x50505*4+0x02000000,0x795d); +reg_write( DDR_REG_BASE +0x50506*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50507*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50508*4+0x02000000,0x2332); +reg_write( DDR_REG_BASE +0x50509*4+0x02000000,0x105f); +reg_write( DDR_REG_BASE +0x5050a*4+0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x5050b*4+0x02000000,0x304b); +reg_write( DDR_REG_BASE +0x5050c*4+0x02000000,0x7970); +reg_write( DDR_REG_BASE +0x5050d*4+0x02000000,0x218c); +reg_write( DDR_REG_BASE +0x5050e*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x5050f*4+0x02000000,0xf408); +reg_write( DDR_REG_BASE +0x50510*4+0x02000000,0xb21); +reg_write( DDR_REG_BASE +0x50511*4+0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x50512*4+0x02000000,0xdbff); +reg_write( DDR_REG_BASE +0x50513*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50514*4+0x02000000,0x4340); +reg_write( DDR_REG_BASE +0x50515*4+0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x50516*4+0x02000000,0x7075); +reg_write( DDR_REG_BASE +0x50517*4+0x02000000,0x20c0); +reg_write( DDR_REG_BASE +0x50518*4+0x02000000,0x61); +reg_write( DDR_REG_BASE +0x50519*4+0x02000000,0xf208); +reg_write( DDR_REG_BASE +0x5051a*4+0x02000000,0x7910); +reg_write( DDR_REG_BASE +0x5051b*4+0x02000000,0x2108); +reg_write( DDR_REG_BASE +0x5051c*4+0x02000000,0x830c); +reg_write( DDR_REG_BASE +0x5051d*4+0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x5051e*4+0x02000000,0x10c9); +reg_write( DDR_REG_BASE +0x5051f*4+0x02000000,0xdbff); +reg_write( DDR_REG_BASE +0x50520*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x50521*4+0x02000000,0xe2e0); +reg_write( DDR_REG_BASE +0x50522*4+0x02000000,0x79e); +reg_write( DDR_REG_BASE +0x50523*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x50524*4+0x02000000,0x2253); +reg_write( DDR_REG_BASE +0x50525*4+0x02000000,0x8081); +reg_write( DDR_REG_BASE +0x50526*4+0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x50527*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x50528*4+0x02000000,0x2479); +reg_write( DDR_REG_BASE +0x50529*4+0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x5052a*4+0x02000000,0x21c5); +reg_write( DDR_REG_BASE +0x5052b*4+0x02000000,0x61); +reg_write( DDR_REG_BASE +0x5052c*4+0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x5052d*4+0x02000000,0x709d); +reg_write( DDR_REG_BASE +0x5052e*4+0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x5052f*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x50530*4+0x02000000,0xf213); +reg_write( DDR_REG_BASE +0x50531*4+0x02000000,0xb9e0); +reg_write( DDR_REG_BASE +0x50532*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x50533*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50534*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50535*4+0x02000000,0xfffe); +reg_write( DDR_REG_BASE +0x50536*4+0x02000000,0x73fd); +reg_write( DDR_REG_BASE +0x50537*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50538*4+0x02000000,0x6078); +reg_write( DDR_REG_BASE +0x50539*4+0x02000000,0xc18d); +reg_write( DDR_REG_BASE +0x5053a*4+0x02000000,0x208b); +reg_write( DDR_REG_BASE +0x5053b*4+0x02000000,0x8803); +reg_write( DDR_REG_BASE +0x5053c*4+0x02000000,0x7a0f); +reg_write( DDR_REG_BASE +0x5053d*4+0x02000000,0x2114); +reg_write( DDR_REG_BASE +0x5053e*4+0x02000000,0x6c1); +reg_write( DDR_REG_BASE +0x5053f*4+0x02000000,0x26ca); +reg_write( DDR_REG_BASE +0x50540*4+0x02000000,0x3061); +reg_write( DDR_REG_BASE +0x50541*4+0x02000000,0xb140); +reg_write( DDR_REG_BASE +0x50542*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x50543*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x50544*4+0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x50545*4+0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x50546*4+0x02000000,0xb41); +reg_write( DDR_REG_BASE +0x50547*4+0x02000000,0xb3a4); +reg_write( DDR_REG_BASE +0x50548*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x50549*4+0x02000000,0xe77); +reg_write( DDR_REG_BASE +0x5054a*4+0x02000000,0x3030); +reg_write( DDR_REG_BASE +0x5054b*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5054c*4+0x02000000,0xea5); +reg_write( DDR_REG_BASE +0x5054d*4+0x02000000,0x3071); +reg_write( DDR_REG_BASE +0x5054e*4+0x02000000,0x2456); +reg_write( DDR_REG_BASE +0x5054f*4+0x02000000,0x3cc0); +reg_write( DDR_REG_BASE +0x50550*4+0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x50551*4+0x02000000,0x1301); +reg_write( DDR_REG_BASE +0x50552*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x50553*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x50554*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50555*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50556*4+0x02000000,0x890a); +reg_write( DDR_REG_BASE +0x50557*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50558*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x50559*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5055a*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x5055b*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x5055c*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x5055d*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5055e*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x5055f*4+0x02000000,0xda40); +reg_write( DDR_REG_BASE +0x50560*4+0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x50561*4+0x02000000,0x890b); +reg_write( DDR_REG_BASE +0x50562*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50563*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x50564*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50565*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x50566*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x50567*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50568*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x50569*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x5056a*4+0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x5056b*4+0x02000000,0xca01); +reg_write( DDR_REG_BASE +0x5056c*4+0x02000000,0x865); +reg_write( DDR_REG_BASE +0x5056d*4+0x02000000,0x311); +reg_write( DDR_REG_BASE +0x5056e*4+0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x5056f*4+0x02000000,0x1f81); +reg_write( DDR_REG_BASE +0x50570*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50571*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x50572*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x50573*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50574*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x50575*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x50576*4+0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x50577*4+0x02000000,0xf028); +reg_write( DDR_REG_BASE +0x50578*4+0x02000000,0x6028); +reg_write( DDR_REG_BASE +0x50579*4+0x02000000,0xd15); +reg_write( DDR_REG_BASE +0x5057a*4+0x02000000,0x1021); +reg_write( DDR_REG_BASE +0x5057b*4+0x02000000,0xc08d); +reg_write( DDR_REG_BASE +0x5057c*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x5057d*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x5057e*4+0x02000000,0x7834); +reg_write( DDR_REG_BASE +0x5057f*4+0x02000000,0x2242); +reg_write( DDR_REG_BASE +0x50580*4+0x02000000,0x802); +reg_write( DDR_REG_BASE +0x50581*4+0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x50582*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x50583*4+0x02000000,0x9ed); +reg_write( DDR_REG_BASE +0x50584*4+0x02000000,0x83a4); +reg_write( DDR_REG_BASE +0x50585*4+0x02000000,0xc095); +reg_write( DDR_REG_BASE +0x50586*4+0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x50587*4+0x02000000,0xc095); +reg_write( DDR_REG_BASE +0x50588*4+0x02000000,0x60e8); +reg_write( DDR_REG_BASE +0x50589*4+0x02000000,0xd2b); +reg_write( DDR_REG_BASE +0x5058a*4+0x02000000,0x1021); +reg_write( DDR_REG_BASE +0x5058b*4+0x02000000,0xc08d); +reg_write( DDR_REG_BASE +0x5058c*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x5058d*4+0x02000000,0x3c1); +reg_write( DDR_REG_BASE +0x5058e*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x5058f*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x50590*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50591*4+0x02000000,0x18c); +reg_write( DDR_REG_BASE +0x50592*4+0x02000000,0x60e8); +reg_write( DDR_REG_BASE +0x50593*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50594*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x50595*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50596*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x50597*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x50598*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x50599*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5059a*4+0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x5059b*4+0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x5059c*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x5059d*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x5059e*4+0x02000000,0xfd3); +reg_write( DDR_REG_BASE +0x5059f*4+0x02000000,0x9384); +reg_write( DDR_REG_BASE +0x505a0*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x505a1*4+0x02000000,0x72b5); +reg_write( DDR_REG_BASE +0x505a2*4+0x02000000,0x680); +reg_write( DDR_REG_BASE +0x505a3*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x505a4*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x505a5*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x505a6*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x505a7*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x505a8*4+0x02000000,0xa9); +reg_write( DDR_REG_BASE +0x505a9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x505aa*4+0x02000000,0xd9a); +reg_write( DDR_REG_BASE +0x505ab*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x505ac*4+0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x505ad*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x505ae*4+0x02000000,0xb1a); +reg_write( DDR_REG_BASE +0x505af*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x505b0*4+0x02000000,0xc7e); +reg_write( DDR_REG_BASE +0x505b1*4+0x02000000,0x180); +reg_write( DDR_REG_BASE +0x505b2*4+0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x505b3*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x505b4*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x505b5*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x505b6*4+0x02000000,0xe0aa); +reg_write( DDR_REG_BASE +0x505b7*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x505b8*4+0x02000000,0x3c0c); +reg_write( DDR_REG_BASE +0x505b9*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x505ba*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x505bb*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x505bc*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x505bd*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x505be*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x505bf*4+0x02000000,0xc1b5); +reg_write( DDR_REG_BASE +0x505c0*4+0x02000000,0xc254); +reg_write( DDR_REG_BASE +0x505c1*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x505c2*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x505c3*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x505c4*4+0x02000000,0xee); +reg_write( DDR_REG_BASE +0x505c5*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x505c6*4+0x02000000,0xcd6); +reg_write( DDR_REG_BASE +0x505c7*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x505c8*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x505c9*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x505ca*4+0x02000000,0xf035); +reg_write( DDR_REG_BASE +0x505cb*4+0x02000000,0x4261); +reg_write( DDR_REG_BASE +0x505cc*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x505cd*4+0x02000000,0xc014); +reg_write( DDR_REG_BASE +0x505ce*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x505cf*4+0x02000000,0x83); +reg_write( DDR_REG_BASE +0x505d0*4+0x02000000,0xc08e); +reg_write( DDR_REG_BASE +0x505d1*4+0x02000000,0x7834); +reg_write( DDR_REG_BASE +0x505d2*4+0x02000000,0xb060); +reg_write( DDR_REG_BASE +0x505d3*4+0x02000000,0x62ba); +reg_write( DDR_REG_BASE +0x505d4*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x505d5*4+0x02000000,0x9f3); +reg_write( DDR_REG_BASE +0x505d6*4+0x02000000,0x8294); +reg_write( DDR_REG_BASE +0x505d7*4+0x02000000,0x4183); +reg_write( DDR_REG_BASE +0x505d8*4+0x02000000,0x911c); +reg_write( DDR_REG_BASE +0x505d9*4+0x02000000,0x1446); +reg_write( DDR_REG_BASE +0x505da*4+0x02000000,0x3103); +reg_write( DDR_REG_BASE +0x505db*4+0x02000000,0x915f); +reg_write( DDR_REG_BASE +0x505dc*4+0x02000000,0xc053); +reg_write( DDR_REG_BASE +0x505dd*4+0x02000000,0x1448); +reg_write( DDR_REG_BASE +0x505de*4+0x02000000,0x3101); +reg_write( DDR_REG_BASE +0x505df*4+0x02000000,0x144a); +reg_write( DDR_REG_BASE +0x505e0*4+0x02000000,0x3100); +reg_write( DDR_REG_BASE +0x505e1*4+0x02000000,0x143a); +reg_write( DDR_REG_BASE +0x505e2*4+0x02000000,0x311f); +reg_write( DDR_REG_BASE +0x505e3*4+0x02000000,0x143c); +reg_write( DDR_REG_BASE +0x505e4*4+0x02000000,0x311e); +reg_write( DDR_REG_BASE +0x505e5*4+0x02000000,0x1440); +reg_write( DDR_REG_BASE +0x505e6*4+0x02000000,0x310f); +reg_write( DDR_REG_BASE +0x505e7*4+0x02000000,0x1442); +reg_write( DDR_REG_BASE +0x505e8*4+0x02000000,0x310e); +reg_write( DDR_REG_BASE +0x505e9*4+0x02000000,0x1444); +reg_write( DDR_REG_BASE +0x505ea*4+0x02000000,0x310c); +reg_write( DDR_REG_BASE +0x505eb*4+0x02000000,0xc346); +reg_write( DDR_REG_BASE +0x505ec*4+0x02000000,0xc313); +reg_write( DDR_REG_BASE +0x505ed*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x505ee*4+0x02000000,0xc147); +reg_write( DDR_REG_BASE +0x505ef*4+0x02000000,0xc242); +reg_write( DDR_REG_BASE +0x505f0*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x505f1*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x505f2*4+0x02000000,0xef); +reg_write( DDR_REG_BASE +0x505f3*4+0x02000000,0xb); +reg_write( DDR_REG_BASE +0x505f4*4+0x02000000,0xc445); +reg_write( DDR_REG_BASE +0x505f5*4+0x02000000,0xc644); +reg_write( DDR_REG_BASE +0x505f6*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x505f7*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x505f8*4+0x02000000,0x3780); +reg_write( DDR_REG_BASE +0x505f9*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x505fa*4+0x02000000,0x37c0); +reg_write( DDR_REG_BASE +0x505fb*4+0x02000000,0xc6e); +reg_write( DDR_REG_BASE +0x505fc*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x505fd*4+0x02000000,0x4261); +reg_write( DDR_REG_BASE +0x505fe*4+0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x505ff*4+0x02000000,0x232f); +reg_write( DDR_REG_BASE +0x50600*4+0x02000000,0x16c8); +reg_write( DDR_REG_BASE +0x50601*4+0x02000000,0xb97); +reg_write( DDR_REG_BASE +0x50602*4+0x02000000,0x9364); +reg_write( DDR_REG_BASE +0x50603*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50604*4+0x02000000,0xc0b5); +reg_write( DDR_REG_BASE +0x50605*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50606*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50607*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50608*4+0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x50609*4+0x02000000,0x4308); +reg_write( DDR_REG_BASE +0x5060a*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x5060b*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x5060c*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x5060d*4+0x02000000,0x1e4); +reg_write( DDR_REG_BASE +0x5060e*4+0x02000000,0x218c); +reg_write( DDR_REG_BASE +0x5060f*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x50610*4+0x02000000,0xb6a0); +reg_write( DDR_REG_BASE +0x50611*4+0x02000000,0xb6a1); +reg_write( DDR_REG_BASE +0x50612*4+0x02000000,0xb6a2); +reg_write( DDR_REG_BASE +0x50613*4+0x02000000,0xf224); +reg_write( DDR_REG_BASE +0x50614*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50615*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50616*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50617*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50618*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50619*4+0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x5061a*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5061b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5061c*4+0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x5061d*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5061e*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5061f*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x50620*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x50621*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50622*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50623*4+0x02000000,0x7b4); +reg_write( DDR_REG_BASE +0x50624*4+0x02000000,0x8881); +reg_write( DDR_REG_BASE +0x50625*4+0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x50626*4+0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x50627*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50628*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x50629*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5062a*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x5062b*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5062c*4+0x02000000,0x7a65); +reg_write( DDR_REG_BASE +0x5062d*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x5062e*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x5062f*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50630*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x50631*4+0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x50632*4+0x02000000,0xceb); +reg_write( DDR_REG_BASE +0x50633*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x50634*4+0x02000000,0xb76); +reg_write( DDR_REG_BASE +0x50635*4+0x02000000,0x180); +reg_write( DDR_REG_BASE +0x50636*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x50637*4+0x02000000,0x21a); +reg_write( DDR_REG_BASE +0x50638*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50639*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x5063a*4+0x02000000,0x2a); +reg_write( DDR_REG_BASE +0x5063b*4+0x02000000,0x1efc); +reg_write( DDR_REG_BASE +0x5063c*4+0x02000000,0x92c4); +reg_write( DDR_REG_BASE +0x5063d*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x5063e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5063f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50640*4+0x02000000,0x440); +reg_write( DDR_REG_BASE +0x50641*4+0x02000000,0xa8a0); +reg_write( DDR_REG_BASE +0x50642*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50643*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50644*4+0x02000000,0xfac); +reg_write( DDR_REG_BASE +0x50645*4+0x02000000,0xb101); +reg_write( DDR_REG_BASE +0x50646*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50647*4+0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x50648*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50649*4+0x02000000,0x7210); +reg_write( DDR_REG_BASE +0x5064a*4+0x02000000,0x20e0); +reg_write( DDR_REG_BASE +0x5064b*4+0x02000000,0x7ca); +reg_write( DDR_REG_BASE +0x5064c*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5064d*4+0x02000000,0x7101); +reg_write( DDR_REG_BASE +0x5064e*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x5064f*4+0x02000000,0x1d6); +reg_write( DDR_REG_BASE +0x50650*4+0x02000000,0x9f3); +reg_write( DDR_REG_BASE +0x50651*4+0x02000000,0x803e); +reg_write( DDR_REG_BASE +0x50652*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x50653*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50654*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x50655*4+0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x50656*4+0x02000000,0x9ca); +reg_write( DDR_REG_BASE +0x50657*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50658*4+0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x50659*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x5065a*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x5065b*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5065c*4+0x02000000,0xf2); +reg_write( DDR_REG_BASE +0x5065d*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x5065e*4+0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x5065f*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50660*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x50661*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50662*4+0x02000000,0x7784); +reg_write( DDR_REG_BASE +0x50663*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x50664*4+0x02000000,0x1e2); +reg_write( DDR_REG_BASE +0x50665*4+0x02000000,0x99a); +reg_write( DDR_REG_BASE +0x50666*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x50667*4+0x02000000,0x760c); +reg_write( DDR_REG_BASE +0x50668*4+0x02000000,0xb17); +reg_write( DDR_REG_BASE +0x50669*4+0x02000000,0x1030); +reg_write( DDR_REG_BASE +0x5066a*4+0x02000000,0x1d10); +reg_write( DDR_REG_BASE +0x5066b*4+0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x5066c*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5066d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5066e*4+0x02000000,0x61a8); +reg_write( DDR_REG_BASE +0x5066f*4+0x02000000,0xfb6); +reg_write( DDR_REG_BASE +0x50670*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x50671*4+0x02000000,0x1d10); +reg_write( DDR_REG_BASE +0x50672*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x50673*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x50674*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50675*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50676*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50677*4+0x02000000,0xc1a2); +reg_write( DDR_REG_BASE +0x50678*4+0x02000000,0xc341); +reg_write( DDR_REG_BASE +0x50679*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5067a*4+0x02000000,0x7083); +reg_write( DDR_REG_BASE +0x5067b*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5067c*4+0x02000000,0x440); +reg_write( DDR_REG_BASE +0x5067d*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x5067e*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x5067f*4+0x02000000,0x4308); +reg_write( DDR_REG_BASE +0x50680*4+0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x50681*4+0x02000000,0x10c1); +reg_write( DDR_REG_BASE +0x50682*4+0x02000000,0xc30a); +reg_write( DDR_REG_BASE +0x50683*4+0x02000000,0x1424); +reg_write( DDR_REG_BASE +0x50684*4+0x02000000,0x301b); +reg_write( DDR_REG_BASE +0x50685*4+0x02000000,0xc508); +reg_write( DDR_REG_BASE +0x50686*4+0x02000000,0xc607); +reg_write( DDR_REG_BASE +0x50687*4+0x02000000,0x70ef); +reg_write( DDR_REG_BASE +0x50688*4+0x02000000,0xac5); +reg_write( DDR_REG_BASE +0x50689*4+0x02000000,0x171); +reg_write( DDR_REG_BASE +0x5068a*4+0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x5068b*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x5068c*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x5068d*4+0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x5068e*4+0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x5068f*4+0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x50690*4+0x02000000,0x3e1f); +reg_write( DDR_REG_BASE +0x50691*4+0x02000000,0x214b); +reg_write( DDR_REG_BASE +0x50692*4+0x02000000,0x8c00); +reg_write( DDR_REG_BASE +0x50693*4+0x02000000,0xdc58); +reg_write( DDR_REG_BASE +0x50694*4+0x02000000,0x27cf); +reg_write( DDR_REG_BASE +0x50695*4+0x02000000,0x31e2); +reg_write( DDR_REG_BASE +0x50696*4+0x02000000,0x7c24); +reg_write( DDR_REG_BASE +0x50697*4+0x02000000,0x2684); +reg_write( DDR_REG_BASE +0x50698*4+0x02000000,0x3001); +reg_write( DDR_REG_BASE +0x50699*4+0x02000000,0x2405); +reg_write( DDR_REG_BASE +0x5069a*4+0x02000000,0x17cc); +reg_write( DDR_REG_BASE +0x5069b*4+0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x5069c*4+0x02000000,0x783); +reg_write( DDR_REG_BASE +0x5069d*4+0x02000000,0x7b85); +reg_write( DDR_REG_BASE +0x5069e*4+0x02000000,0x7c3d); +reg_write( DDR_REG_BASE +0x5069f*4+0x02000000,0x7c9d); +reg_write( DDR_REG_BASE +0x506a0*4+0x02000000,0x7c9d); +reg_write( DDR_REG_BASE +0x506a1*4+0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x506a2*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x506a3*4+0x02000000,0x2404); +reg_write( DDR_REG_BASE +0x506a4*4+0x02000000,0x1f9e); +reg_write( DDR_REG_BASE +0x506a5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x506a6*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x506a7*4+0x02000000,0xc401); +reg_write( DDR_REG_BASE +0x506a8*4+0x02000000,0x272f); +reg_write( DDR_REG_BASE +0x506a9*4+0x02000000,0x32c0); +reg_write( DDR_REG_BASE +0x506aa*4+0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x506ab*4+0x02000000,0x1f8d); +reg_write( DDR_REG_BASE +0x506ac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x506ad*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x506ae*4+0x02000000,0x2405); +reg_write( DDR_REG_BASE +0x506af*4+0x02000000,0x178c); +reg_write( DDR_REG_BASE +0x506b0*4+0x02000000,0x2405); +reg_write( DDR_REG_BASE +0x506b1*4+0x02000000,0x10de); +reg_write( DDR_REG_BASE +0x506b2*4+0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x506b3*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x506b4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x506b5*4+0x02000000,0x2705); +reg_write( DDR_REG_BASE +0x506b6*4+0x02000000,0x3303); +reg_write( DDR_REG_BASE +0x506b7*4+0x02000000,0x1b00); +reg_write( DDR_REG_BASE +0x506b8*4+0x02000000,0x784); +reg_write( DDR_REG_BASE +0x506b9*4+0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x506ba*4+0x02000000,0x3040); +reg_write( DDR_REG_BASE +0x506bb*4+0x02000000,0x269a); +reg_write( DDR_REG_BASE +0x506bc*4+0x02000000,0x3004); +reg_write( DDR_REG_BASE +0x506bd*4+0x02000000,0x2353); +reg_write( DDR_REG_BASE +0x506be*4+0x02000000,0x30c3); +reg_write( DDR_REG_BASE +0x506bf*4+0x02000000,0x7be5); +reg_write( DDR_REG_BASE +0x506c0*4+0x02000000,0x7554); +reg_write( DDR_REG_BASE +0x506c1*4+0x02000000,0x2604); +reg_write( DDR_REG_BASE +0x506c2*4+0x02000000,0x3f9e); +reg_write( DDR_REG_BASE +0x506c3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x506c4*4+0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x506c5*4+0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x506c6*4+0x02000000,0x178d); +reg_write( DDR_REG_BASE +0x506c7*4+0x02000000,0x7d65); +reg_write( DDR_REG_BASE +0x506c8*4+0x02000000,0x2754); +reg_write( DDR_REG_BASE +0x506c9*4+0x02000000,0x3803); +reg_write( DDR_REG_BASE +0x506ca*4+0x02000000,0x2755); +reg_write( DDR_REG_BASE +0x506cb*4+0x02000000,0x3802); +reg_write( DDR_REG_BASE +0x506cc*4+0x02000000,0x7b85); +reg_write( DDR_REG_BASE +0x506cd*4+0x02000000,0x26c5); +reg_write( DDR_REG_BASE +0x506ce*4+0x02000000,0x1e21); +reg_write( DDR_REG_BASE +0x506cf*4+0x02000000,0x7a85); +reg_write( DDR_REG_BASE +0x506d0*4+0x02000000,0xb3a0); +reg_write( DDR_REG_BASE +0x506d1*4+0x02000000,0xb2c0); +reg_write( DDR_REG_BASE +0x506d2*4+0x02000000,0x2104); +reg_write( DDR_REG_BASE +0x506d3*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x506d4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x506d5*4+0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x506d6*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x506d7*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x506d8*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x506d9*4+0x02000000,0x7a25); +reg_write( DDR_REG_BASE +0x506da*4+0x02000000,0x2755); +reg_write( DDR_REG_BASE +0x506db*4+0x02000000,0x3c01); +reg_write( DDR_REG_BASE +0x506dc*4+0x02000000,0x7c25); +reg_write( DDR_REG_BASE +0x506dd*4+0x02000000,0x2340); +reg_write( DDR_REG_BASE +0x506de*4+0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x506df*4+0x02000000,0xb440); +reg_write( DDR_REG_BASE +0x506e0*4+0x02000000,0xf405); +reg_write( DDR_REG_BASE +0x506e1*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x506e2*4+0x02000000,0x7042); +reg_write( DDR_REG_BASE +0x506e3*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x506e4*4+0x02000000,0x440); +reg_write( DDR_REG_BASE +0x506e5*4+0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x506e6*4+0x02000000,0xc0a2); +reg_write( DDR_REG_BASE +0x506e7*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x506e8*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x506e9*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x506ea*4+0x02000000,0xa0d); +reg_write( DDR_REG_BASE +0x506eb*4+0x02000000,0xf0); +reg_write( DDR_REG_BASE +0x506ec*4+0x02000000,0xdf10); +reg_write( DDR_REG_BASE +0x506ed*4+0x02000000,0xa09); +reg_write( DDR_REG_BASE +0x506ee*4+0x02000000,0x310); +reg_write( DDR_REG_BASE +0x506ef*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x506f0*4+0x02000000,0xa57); +reg_write( DDR_REG_BASE +0x506f1*4+0x02000000,0x5f5); +reg_write( DDR_REG_BASE +0x506f2*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x506f3*4+0x02000000,0x31c0); +reg_write( DDR_REG_BASE +0x506f4*4+0x02000000,0x728d); +reg_write( DDR_REG_BASE +0x506f5*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x506f6*4+0x02000000,0x2025); +reg_write( DDR_REG_BASE +0x506f7*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x506f8*4+0x02000000,0xf195); +reg_write( DDR_REG_BASE +0x506f9*4+0x02000000,0xf01a); +reg_write( DDR_REG_BASE +0x506fa*4+0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x506fb*4+0x02000000,0xf015); +reg_write( DDR_REG_BASE +0x506fc*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x506fd*4+0x02000000,0xf01f); +reg_write( DDR_REG_BASE +0x506fe*4+0x02000000,0xf02b); +reg_write( DDR_REG_BASE +0x506ff*4+0x02000000,0xf02d); +reg_write( DDR_REG_BASE +0x50700*4+0x02000000,0xf027); +reg_write( DDR_REG_BASE +0x50701*4+0x02000000,0xf02d); +reg_write( DDR_REG_BASE +0x50702*4+0x02000000,0xf02d); +reg_write( DDR_REG_BASE +0x50703*4+0x02000000,0xf02f); +reg_write( DDR_REG_BASE +0x50704*4+0x02000000,0xf00b); +reg_write( DDR_REG_BASE +0x50705*4+0x02000000,0xf01c); +reg_write( DDR_REG_BASE +0x50706*4+0x02000000,0xf021); +reg_write( DDR_REG_BASE +0x50707*4+0x02000000,0xf015); +reg_write( DDR_REG_BASE +0x50708*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x50709*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x5070a*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x5070b*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x5070c*4+0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x5070d*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x5070e*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x5070f*4+0x02000000,0xdc07); +reg_write( DDR_REG_BASE +0x50710*4+0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x50711*4+0x02000000,0x738d); +reg_write( DDR_REG_BASE +0x50712*4+0x02000000,0xa11); +reg_write( DDR_REG_BASE +0x50713*4+0x02000000,0xf1); +reg_write( DDR_REG_BASE +0x50714*4+0x02000000,0x43a1); +reg_write( DDR_REG_BASE +0x50715*4+0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x50716*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50717*4+0x02000000,0x7e65); +reg_write( DDR_REG_BASE +0x50718*4+0x02000000,0x4381); +reg_write( DDR_REG_BASE +0x50719*4+0x02000000,0xf175); +reg_write( DDR_REG_BASE +0x5071a*4+0x02000000,0x4799); +reg_write( DDR_REG_BASE +0x5071b*4+0x02000000,0xe28d); +reg_write( DDR_REG_BASE +0x5071c*4+0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x5071d*4+0x02000000,0x37c0); +reg_write( DDR_REG_BASE +0x5071e*4+0x02000000,0x43e3); +reg_write( DDR_REG_BASE +0x5071f*4+0x02000000,0xf56f); +reg_write( DDR_REG_BASE +0x50720*4+0x02000000,0x43a1); +reg_write( DDR_REG_BASE +0x50721*4+0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x50722*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50723*4+0x02000000,0x7e65); +reg_write( DDR_REG_BASE +0x50724*4+0x02000000,0x230a); +reg_write( DDR_REG_BASE +0x50725*4+0x02000000,0x780); +reg_write( DDR_REG_BASE +0x50726*4+0x02000000,0xf167); +reg_write( DDR_REG_BASE +0x50727*4+0x02000000,0x766c); +reg_write( DDR_REG_BASE +0x50728*4+0x02000000,0xf165); +reg_write( DDR_REG_BASE +0x50729*4+0x02000000,0x756c); +reg_write( DDR_REG_BASE +0x5072a*4+0x02000000,0xf163); +reg_write( DDR_REG_BASE +0x5072b*4+0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x5072c*4+0x02000000,0xf161); +reg_write( DDR_REG_BASE +0x5072d*4+0x02000000,0xdb16); +reg_write( DDR_REG_BASE +0x5072e*4+0x02000000,0xf15f); +reg_write( DDR_REG_BASE +0x5072f*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x50730*4+0x02000000,0xf15d); +reg_write( DDR_REG_BASE +0x50731*4+0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x50732*4+0x02000000,0xf15b); +reg_write( DDR_REG_BASE +0x50733*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50734*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x50735*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x50736*4+0x02000000,0xc408); +reg_write( DDR_REG_BASE +0x50737*4+0x02000000,0xc443); +reg_write( DDR_REG_BASE +0x50738*4+0x02000000,0xc407); +reg_write( DDR_REG_BASE +0x50739*4+0x02000000,0xc442); +reg_write( DDR_REG_BASE +0x5073a*4+0x02000000,0xc406); +reg_write( DDR_REG_BASE +0x5073b*4+0x02000000,0xc441); +reg_write( DDR_REG_BASE +0x5073c*4+0x02000000,0xc405); +reg_write( DDR_REG_BASE +0x5073d*4+0x02000000,0xe72); +reg_write( DDR_REG_BASE +0x5073e*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5073f*4+0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x50740*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x50741*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x50742*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50743*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50744*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50745*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50746*4+0x02000000,0x440); +reg_write( DDR_REG_BASE +0x50747*4+0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x50748*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x50749*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x5074a*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x5074b*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x5074c*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5074d*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x5074e*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x5074f*4+0x02000000,0x1e8); +reg_write( DDR_REG_BASE +0x50750*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50751*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50752*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50753*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50754*4+0x02000000,0x440); +reg_write( DDR_REG_BASE +0x50755*4+0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x50756*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x50757*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x50758*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x50759*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x5075a*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5075b*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x5075c*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x5075d*4+0x02000000,0x1e6); +reg_write( DDR_REG_BASE +0x5075e*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5075f*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50760*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50761*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x50762*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x50763*4+0x02000000,0x9160); +reg_write( DDR_REG_BASE +0x50764*4+0x02000000,0x9141); +reg_write( DDR_REG_BASE +0x50765*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x50766*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x50767*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50768*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50769*4+0x02000000,0x7965); +reg_write( DDR_REG_BASE +0x5076a*4+0x02000000,0xe807); +reg_write( DDR_REG_BASE +0x5076b*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x5076c*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5076d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5076e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5076f*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50770*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x50771*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x50772*4+0x02000000,0xda0f); +reg_write( DDR_REG_BASE +0x50773*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x50774*4+0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x50775*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x50776*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50777*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x50778*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50779*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5077a*4+0x02000000,0x900f); +reg_write( DDR_REG_BASE +0x5077b*4+0x02000000,0xfe4c); +reg_write( DDR_REG_BASE +0x5077c*4+0x02000000,0xda10); +reg_write( DDR_REG_BASE +0x5077d*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x5077e*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x5077f*4+0x02000000,0xa01); +reg_write( DDR_REG_BASE +0x50780*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x50781*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50782*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50783*4+0x02000000,0xb101); +reg_write( DDR_REG_BASE +0x50784*4+0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x50785*4+0x02000000,0x8830); +reg_write( DDR_REG_BASE +0x50786*4+0x02000000,0x96d); +reg_write( DDR_REG_BASE +0x50787*4+0x02000000,0x110); +reg_write( DDR_REG_BASE +0x50788*4+0x02000000,0x8008); +reg_write( DDR_REG_BASE +0x50789*4+0x02000000,0x869); +reg_write( DDR_REG_BASE +0x5078a*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5078b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5078c*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x5078d*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x5078e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5078f*4+0x02000000,0x7b1); +reg_write( DDR_REG_BASE +0x50790*4+0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x50791*4+0x02000000,0x8ea); +reg_write( DDR_REG_BASE +0x50792*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50793*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50794*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50795*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x50796*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50797*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50798*4+0x02000000,0x8d64); +reg_write( DDR_REG_BASE +0x50799*4+0x02000000,0x8da3); +reg_write( DDR_REG_BASE +0x5079a*4+0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x5079b*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x5079c*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5079d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5079e*4+0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x5079f*4+0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x507a0*4+0x02000000,0x1f81); +reg_write( DDR_REG_BASE +0x507a1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x507a2*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x507a3*4+0x02000000,0x7e45); +reg_write( DDR_REG_BASE +0x507a4*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x507a5*4+0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x507a6*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x507a7*4+0x02000000,0x1064); +reg_write( DDR_REG_BASE +0x507a8*4+0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x507a9*4+0x02000000,0x1f81); +reg_write( DDR_REG_BASE +0x507aa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x507ab*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x507ac*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x507ad*4+0x02000000,0x79c5); +reg_write( DDR_REG_BASE +0x507ae*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x507af*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x507b0*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x507b1*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x507b2*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x507b3*4+0x02000000,0x9120); +reg_write( DDR_REG_BASE +0x507b4*4+0x02000000,0xb9c5); +reg_write( DDR_REG_BASE +0x507b5*4+0x02000000,0xb420); +reg_write( DDR_REG_BASE +0x507b6*4+0x02000000,0xbd3); +reg_write( DDR_REG_BASE +0x507b7*4+0x02000000,0x8365); +reg_write( DDR_REG_BASE +0x507b8*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x507b9*4+0x02000000,0xd0e); +reg_write( DDR_REG_BASE +0x507ba*4+0x02000000,0xea6); +reg_write( DDR_REG_BASE +0x507bb*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x507bc*4+0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x507bd*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x507be*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x507bf*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x507c0*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x507c1*4+0x02000000,0xc92); +reg_write( DDR_REG_BASE +0x507c2*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x507c3*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x507c4*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x507c5*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x507c6*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x507c7*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x507c8*4+0x02000000,0xd85a); +reg_write( DDR_REG_BASE +0x507c9*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x507ca*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x507cb*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x507cc*4+0x02000000,0xda0a); +reg_write( DDR_REG_BASE +0x507cd*4+0x02000000,0xd52); +reg_write( DDR_REG_BASE +0x507ce*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x507cf*4+0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x507d0*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x507d1*4+0x02000000,0xd0a); +reg_write( DDR_REG_BASE +0x507d2*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x507d3*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x507d4*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x507d5*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x507d6*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x507d7*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x507d8*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x507d9*4+0x02000000,0x20c0); +reg_write( DDR_REG_BASE +0x507da*4+0x02000000,0xfe9); +reg_write( DDR_REG_BASE +0x507db*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x507dc*4+0x02000000,0x2884); +reg_write( DDR_REG_BASE +0x507dd*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x507de*4+0x02000000,0x917); +reg_write( DDR_REG_BASE +0x507df*4+0x02000000,0x3f0); +reg_write( DDR_REG_BASE +0x507e0*4+0x02000000,0x228a); +reg_write( DDR_REG_BASE +0x507e1*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x507e2*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x507e3*4+0x02000000,0xb9c4); +reg_write( DDR_REG_BASE +0x507e4*4+0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x507e5*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x507e6*4+0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x507e7*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x507e8*4+0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x507e9*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x507ea*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x507eb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x507ec*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x507ed*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x507ee*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x507ef*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x507f0*4+0x02000000,0x16a); +reg_write( DDR_REG_BASE +0x507f1*4+0x02000000,0x224f); +reg_write( DDR_REG_BASE +0x507f2*4+0x02000000,0x240); +reg_write( DDR_REG_BASE +0x507f3*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x507f4*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x507f5*4+0x02000000,0xb140); +reg_write( DDR_REG_BASE +0x507f6*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x507f7*4+0x02000000,0xb140); +reg_write( DDR_REG_BASE +0x507f8*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x507f9*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x507fa*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x507fb*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x507fc*4+0x02000000,0x80d); +reg_write( DDR_REG_BASE +0x507fd*4+0x02000000,0x72); +reg_write( DDR_REG_BASE +0x507fe*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x507ff*4+0x02000000,0x48ff); +reg_write( DDR_REG_BASE +0x50800*4+0x02000000,0x2984); +reg_write( DDR_REG_BASE +0x50801*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50802*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50803*4+0x02000000,0x782e); +reg_write( DDR_REG_BASE +0x50804*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x50805*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x50806*4+0x02000000,0x95a); +reg_write( DDR_REG_BASE +0x50807*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50808*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x50809*4+0x02000000,0x795b); +reg_write( DDR_REG_BASE +0x5080a*4+0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x5080b*4+0x02000000,0x181); +reg_write( DDR_REG_BASE +0x5080c*4+0x02000000,0xb9c4); +reg_write( DDR_REG_BASE +0x5080d*4+0x02000000,0xe906); +reg_write( DDR_REG_BASE +0x5080e*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x5080f*4+0x02000000,0x901); +reg_write( DDR_REG_BASE +0x50810*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x50811*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50812*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x50813*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50814*4+0x02000000,0xb8c1); +reg_write( DDR_REG_BASE +0x50815*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50816*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x50817*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x50818*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50819*4+0x02000000,0xbe2); +reg_write( DDR_REG_BASE +0x5081a*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5081b*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x5081c*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5081d*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5081e*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5081f*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x50820*4+0x02000000,0xd85a); +reg_write( DDR_REG_BASE +0x50821*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50822*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50823*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x50824*4+0x02000000,0xda09); +reg_write( DDR_REG_BASE +0x50825*4+0x02000000,0xca2); +reg_write( DDR_REG_BASE +0x50826*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50827*4+0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x50828*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50829*4+0x02000000,0xc5a); +reg_write( DDR_REG_BASE +0x5082a*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5082b*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5082c*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x5082d*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x5082e*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5082f*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50830*4+0x02000000,0xc3e1); +reg_write( DDR_REG_BASE +0x50831*4+0x02000000,0xc2e1); +reg_write( DDR_REG_BASE +0x50832*4+0x02000000,0xc1e1); +reg_write( DDR_REG_BASE +0x50833*4+0x02000000,0xc0e1); +reg_write( DDR_REG_BASE +0x50834*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x50835*4+0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x50836*4+0x02000000,0x4220); +reg_write( DDR_REG_BASE +0x50837*4+0x02000000,0xc184); +reg_write( DDR_REG_BASE +0x50838*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x50839*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5083a*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x5083b*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5083c*4+0x02000000,0x12); +reg_write( DDR_REG_BASE +0x5083d*4+0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x5083e*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x5083f*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x50840*4+0x02000000,0xa6a); +reg_write( DDR_REG_BASE +0x50841*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x50842*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x50843*4+0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x50844*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x50845*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50846*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x50847*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50848*4+0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x50849*4+0x02000000,0x216c); +reg_write( DDR_REG_BASE +0x5084a*4+0x02000000,0x102); +reg_write( DDR_REG_BASE +0x5084b*4+0x02000000,0x206c); +reg_write( DDR_REG_BASE +0x5084c*4+0x02000000,0x141); +reg_write( DDR_REG_BASE +0x5084d*4+0x02000000,0x7822); +reg_write( DDR_REG_BASE +0x5084e*4+0x02000000,0x621a); +reg_write( DDR_REG_BASE +0x5084f*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50850*4+0x02000000,0x784e); +reg_write( DDR_REG_BASE +0x50851*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50852*4+0x02000000,0xc0e6); +reg_write( DDR_REG_BASE +0x50853*4+0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x50854*4+0x02000000,0x483); +reg_write( DDR_REG_BASE +0x50855*4+0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x50856*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50857*4+0x02000000,0x6b4); +reg_write( DDR_REG_BASE +0x50858*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x50859*4+0x02000000,0x647a); +reg_write( DDR_REG_BASE +0x5085a*4+0x02000000,0x8aa2); +reg_write( DDR_REG_BASE +0x5085b*4+0x02000000,0x8a43); +reg_write( DDR_REG_BASE +0x5085c*4+0x02000000,0x7d04); +reg_write( DDR_REG_BASE +0x5085d*4+0x02000000,0xf00b); +reg_write( DDR_REG_BASE +0x5085e*4+0x02000000,0x6199); +reg_write( DDR_REG_BASE +0x5085f*4+0x02000000,0x89e4); +reg_write( DDR_REG_BASE +0x50860*4+0x02000000,0x7f0b); +reg_write( DDR_REG_BASE +0x50861*4+0x02000000,0xf206); +reg_write( DDR_REG_BASE +0x50862*4+0x02000000,0x89e5); +reg_write( DDR_REG_BASE +0x50863*4+0x02000000,0x79af); +reg_write( DDR_REG_BASE +0x50864*4+0x02000000,0x210f); +reg_write( DDR_REG_BASE +0x50865*4+0x02000000,0x3cd); +reg_write( DDR_REG_BASE +0x50866*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x50867*4+0x02000000,0xef1); +reg_write( DDR_REG_BASE +0x50868*4+0x02000000,0x90a4); +reg_write( DDR_REG_BASE +0x50869*4+0x02000000,0x2314); +reg_write( DDR_REG_BASE +0x5086a*4+0x02000000,0x381); +reg_write( DDR_REG_BASE +0x5086b*4+0x02000000,0x78af); +reg_write( DDR_REG_BASE +0x5086c*4+0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x5086d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5086e*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5086f*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50870*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50871*4+0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x50872*4+0x02000000,0x843); +reg_write( DDR_REG_BASE +0x50873*4+0x02000000,0x90e0); +reg_write( DDR_REG_BASE +0x50874*4+0x02000000,0x10f1); +reg_write( DDR_REG_BASE +0x50875*4+0x02000000,0x809b); +reg_write( DDR_REG_BASE +0x50876*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50877*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50878*4+0x02000000,0x7c4); +reg_write( DDR_REG_BASE +0x50879*4+0x02000000,0xbea); +reg_write( DDR_REG_BASE +0x5087a*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5087b*4+0x02000000,0xc1a2); +reg_write( DDR_REG_BASE +0x5087c*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5087d*4+0x02000000,0x70c5); +reg_write( DDR_REG_BASE +0x5087e*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5087f*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x50880*4+0x02000000,0xdca); +reg_write( DDR_REG_BASE +0x50881*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x50882*4+0x02000000,0xb15); +reg_write( DDR_REG_BASE +0x50883*4+0x02000000,0x307e); +reg_write( DDR_REG_BASE +0x50884*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x50885*4+0x02000000,0x896); +reg_write( DDR_REG_BASE +0x50886*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x50887*4+0x02000000,0xd56); +reg_write( DDR_REG_BASE +0x50888*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50889*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5088a*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5088b*4+0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x5088c*4+0x02000000,0x886); +reg_write( DDR_REG_BASE +0x5088d*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5088e*4+0x02000000,0xd8c8); +reg_write( DDR_REG_BASE +0x5088f*4+0x02000000,0xd46); +reg_write( DDR_REG_BASE +0x50890*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50891*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50892*4+0x02000000,0x87a); +reg_write( DDR_REG_BASE +0x50893*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50894*4+0x02000000,0xd862); +reg_write( DDR_REG_BASE +0x50895*4+0x02000000,0xd3a); +reg_write( DDR_REG_BASE +0x50896*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50897*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50898*4+0x02000000,0x720c); +reg_write( DDR_REG_BASE +0x50899*4+0x02000000,0x86e); +reg_write( DDR_REG_BASE +0x5089a*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x5089b*4+0x02000000,0xd2e); +reg_write( DDR_REG_BASE +0x5089c*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5089d*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5089e*4+0x02000000,0xe42); +reg_write( DDR_REG_BASE +0x5089f*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x508a0*4+0x02000000,0xb09); +reg_write( DDR_REG_BASE +0x508a1*4+0x02000000,0x307e); +reg_write( DDR_REG_BASE +0x508a2*4+0x02000000,0x720c); +reg_write( DDR_REG_BASE +0x508a3*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x508a4*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x508a5*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x508a6*4+0x02000000,0xd40); +reg_write( DDR_REG_BASE +0x508a7*4+0x02000000,0x852); +reg_write( DDR_REG_BASE +0x508a8*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x508a9*4+0x02000000,0xd12); +reg_write( DDR_REG_BASE +0x508aa*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x508ab*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x508ac*4+0x02000000,0xd823); +reg_write( DDR_REG_BASE +0x508ad*4+0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x508ae*4+0x02000000,0x8820); +reg_write( DDR_REG_BASE +0x508af*4+0x02000000,0x1026); +reg_write( DDR_REG_BASE +0x508b0*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x508b1*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x508b2*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x508b3*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x508b4*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x508b5*4+0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x508b6*4+0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x508b7*4+0x02000000,0x17c1); +reg_write( DDR_REG_BASE +0x508b8*4+0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x508b9*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x508ba*4+0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x508bb*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x508bc*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x508bd*4+0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x508be*4+0x02000000,0x782b); +reg_write( DDR_REG_BASE +0x508bf*4+0x02000000,0xf205); +reg_write( DDR_REG_BASE +0x508c0*4+0x02000000,0xd56); +reg_write( DDR_REG_BASE +0x508c1*4+0x02000000,0x220); +reg_write( DDR_REG_BASE +0x508c2*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x508c3*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x508c4*4+0x02000000,0xde5); +reg_write( DDR_REG_BASE +0x508c5*4+0x02000000,0x90b4); +reg_write( DDR_REG_BASE +0x508c6*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x508c7*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x508c8*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x508c9*4+0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x508ca*4+0x02000000,0x17c0); +reg_write( DDR_REG_BASE +0x508cb*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x508cc*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x508cd*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x508ce*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x508cf*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x508d0*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x508d1*4+0x02000000,0x790b); +reg_write( DDR_REG_BASE +0x508d2*4+0x02000000,0xf204); +reg_write( DDR_REG_BASE +0x508d3*4+0x02000000,0xdae); +reg_write( DDR_REG_BASE +0x508d4*4+0x02000000,0x220); +reg_write( DDR_REG_BASE +0x508d5*4+0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x508d6*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x508d7*4+0x02000000,0xee5); +reg_write( DDR_REG_BASE +0x508d8*4+0x02000000,0x90b4); +reg_write( DDR_REG_BASE +0x508d9*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x508da*4+0x02000000,0xb09); +reg_write( DDR_REG_BASE +0x508db*4+0x02000000,0x307e); +reg_write( DDR_REG_BASE +0x508dc*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x508dd*4+0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x508de*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x508df*4+0x02000000,0xa0f); +reg_write( DDR_REG_BASE +0x508e0*4+0x02000000,0xfde); +reg_write( DDR_REG_BASE +0x508e1*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x508e2*4+0x02000000,0xc9e); +reg_write( DDR_REG_BASE +0x508e3*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x508e4*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x508e5*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x508e6*4+0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x508e7*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x508e8*4+0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x508e9*4+0x02000000,0x17c0); +reg_write( DDR_REG_BASE +0x508ea*4+0x02000000,0xe805); +reg_write( DDR_REG_BASE +0x508eb*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x508ec*4+0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x508ed*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x508ee*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x508ef*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x508f0*4+0x02000000,0x790b); +reg_write( DDR_REG_BASE +0x508f1*4+0x02000000,0xf205); +reg_write( DDR_REG_BASE +0x508f2*4+0x02000000,0xcf2); +reg_write( DDR_REG_BASE +0x508f3*4+0x02000000,0x220); +reg_write( DDR_REG_BASE +0x508f4*4+0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x508f5*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x508f6*4+0x02000000,0xde3); +reg_write( DDR_REG_BASE +0x508f7*4+0x02000000,0x90b4); +reg_write( DDR_REG_BASE +0x508f8*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x508f9*4+0x02000000,0xb0b); +reg_write( DDR_REG_BASE +0x508fa*4+0x02000000,0x307e); +reg_write( DDR_REG_BASE +0x508fb*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x508fc*4+0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x508fd*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x508fe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x508ff*4+0x02000000,0x2710); +reg_write( DDR_REG_BASE +0x50900*4+0x02000000,0xf9e); +reg_write( DDR_REG_BASE +0x50901*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x50902*4+0x02000000,0xc5e); +reg_write( DDR_REG_BASE +0x50903*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50904*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50905*4+0x02000000,0xf11); +reg_write( DDR_REG_BASE +0x50906*4+0x02000000,0x131e); +reg_write( DDR_REG_BASE +0x50907*4+0x02000000,0x9a6); +reg_write( DDR_REG_BASE +0x50908*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x50909*4+0x02000000,0xbca); +reg_write( DDR_REG_BASE +0x5090a*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x5090b*4+0x02000000,0xd80d); +reg_write( DDR_REG_BASE +0x5090c*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x5090d*4+0x02000000,0xf01c); +reg_write( DDR_REG_BASE +0x5090e*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x5090f*4+0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x50910*4+0x02000000,0x17c0); +reg_write( DDR_REG_BASE +0x50911*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x50912*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x50913*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x50914*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x50915*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x50916*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x50917*4+0x02000000,0x790b); +reg_write( DDR_REG_BASE +0x50918*4+0x02000000,0xf20f); +reg_write( DDR_REG_BASE +0x50919*4+0x02000000,0xd8a); +reg_write( DDR_REG_BASE +0x5091a*4+0x02000000,0x220); +reg_write( DDR_REG_BASE +0x5091b*4+0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x5091c*4+0x02000000,0xb09); +reg_write( DDR_REG_BASE +0x5091d*4+0x02000000,0x307e); +reg_write( DDR_REG_BASE +0x5091e*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5091f*4+0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x50920*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x50921*4+0x02000000,0xa0f); +reg_write( DDR_REG_BASE +0x50922*4+0x02000000,0xf5a); +reg_write( DDR_REG_BASE +0x50923*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x50924*4+0x02000000,0xc1a); +reg_write( DDR_REG_BASE +0x50925*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50926*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50927*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x50928*4+0x02000000,0xdcd); +reg_write( DDR_REG_BASE +0x50929*4+0x02000000,0x90b4); +reg_write( DDR_REG_BASE +0x5092a*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5092b*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5092c*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5092d*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5092e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5092f*4+0x02000000,0x7c4); +reg_write( DDR_REG_BASE +0x50930*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50931*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x50932*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50933*4+0x02000000,0x600); +reg_write( DDR_REG_BASE +0x50934*4+0x02000000,0xd8a); +reg_write( DDR_REG_BASE +0x50935*4+0x02000000,0x220); +reg_write( DDR_REG_BASE +0x50936*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x50937*4+0x02000000,0xc0a2); +reg_write( DDR_REG_BASE +0x50938*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50939*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x5093a*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5093b*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5093c*4+0x02000000,0xca04); +reg_write( DDR_REG_BASE +0x5093d*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5093e*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x5093f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50940*4+0x02000000,0x7b4); +reg_write( DDR_REG_BASE +0x50941*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x50942*4+0x02000000,0x8b20); +reg_write( DDR_REG_BASE +0x50943*4+0x02000000,0xa0d); +reg_write( DDR_REG_BASE +0x50944*4+0x02000000,0x44); +reg_write( DDR_REG_BASE +0x50945*4+0x02000000,0x8b21); +reg_write( DDR_REG_BASE +0x50946*4+0x02000000,0x919); +reg_write( DDR_REG_BASE +0x50947*4+0x02000000,0x85); +reg_write( DDR_REG_BASE +0x50948*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x50949*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x5094a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5094b*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x5094c*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x5094d*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x5094e*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x5094f*4+0x02000000,0x1f64); +reg_write( DDR_REG_BASE +0x50950*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50951*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x50952*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x50953*4+0x02000000,0xae1); +reg_write( DDR_REG_BASE +0x50954*4+0x02000000,0x8004); +reg_write( DDR_REG_BASE +0x50955*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50956*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x50957*4+0x02000000,0xc1a5); +reg_write( DDR_REG_BASE +0x50958*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x50959*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x5095a*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5095b*4+0x02000000,0xdde); +reg_write( DDR_REG_BASE +0x5095c*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5095d*4+0x02000000,0xda14); +reg_write( DDR_REG_BASE +0x5095e*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x5095f*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50960*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x50961*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50962*4+0x02000000,0xc180); +reg_write( DDR_REG_BASE +0x50963*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x50964*4+0x02000000,0xbea); +reg_write( DDR_REG_BASE +0x50965*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x50966*4+0x02000000,0xb885); +reg_write( DDR_REG_BASE +0x50967*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50968*4+0x02000000,0xf6); +reg_write( DDR_REG_BASE +0x50969*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5096a*4+0x02000000,0xd8e); +reg_write( DDR_REG_BASE +0x5096b*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5096c*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x5096d*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5096e*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5096f*4+0x02000000,0x89e); +reg_write( DDR_REG_BASE +0x50970*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50971*4+0x02000000,0xc280); +reg_write( DDR_REG_BASE +0x50972*4+0x02000000,0xc0a5); +reg_write( DDR_REG_BASE +0x50973*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x50974*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50975*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50976*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50977*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50978*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50979*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x5097a*4+0x02000000,0x3d02); +reg_write( DDR_REG_BASE +0x5097b*4+0x02000000,0x4748); +reg_write( DDR_REG_BASE +0x5097c*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x5097d*4+0x02000000,0x4308); +reg_write( DDR_REG_BASE +0x5097e*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x5097f*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50980*4+0x02000000,0xd92); +reg_write( DDR_REG_BASE +0x50981*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50982*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x50983*4+0x02000000,0xb25); +reg_write( DDR_REG_BASE +0x50984*4+0x02000000,0x10b1); +reg_write( DDR_REG_BASE +0x50985*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x50986*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50987*4+0x02000000,0xf2); +reg_write( DDR_REG_BASE +0x50988*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50989*4+0x02000000,0xd52); +reg_write( DDR_REG_BASE +0x5098a*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5098b*4+0x02000000,0x4260); +reg_write( DDR_REG_BASE +0x5098c*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x5098d*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5098e*4+0x02000000,0xbe6); +reg_write( DDR_REG_BASE +0x5098f*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x50990*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x50991*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50992*4+0x02000000,0xd909); +reg_write( DDR_REG_BASE +0x50993*4+0x02000000,0xf036); +reg_write( DDR_REG_BASE +0x50994*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x50995*4+0x02000000,0x3f9b); +reg_write( DDR_REG_BASE +0x50996*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x50997*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50998*4+0x02000000,0xb1b); +reg_write( DDR_REG_BASE +0x50999*4+0x02000000,0x1030); +reg_write( DDR_REG_BASE +0x5099a*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x5099b*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5099c*4+0x02000000,0xf4); +reg_write( DDR_REG_BASE +0x5099d*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5099e*4+0x02000000,0xd26); +reg_write( DDR_REG_BASE +0x5099f*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x509a0*4+0x02000000,0x4260); +reg_write( DDR_REG_BASE +0x509a1*4+0x02000000,0xdd09); +reg_write( DDR_REG_BASE +0x509a2*4+0x02000000,0xdec0); +reg_write( DDR_REG_BASE +0x509a3*4+0x02000000,0xd8d0); +reg_write( DDR_REG_BASE +0x509a4*4+0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x509a5*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x509a6*4+0x02000000,0xf3); +reg_write( DDR_REG_BASE +0x509a7*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x509a8*4+0x02000000,0xd12); +reg_write( DDR_REG_BASE +0x509a9*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x509aa*4+0x02000000,0x4260); +reg_write( DDR_REG_BASE +0x509ab*4+0x02000000,0x72ad); +reg_write( DDR_REG_BASE +0x509ac*4+0x02000000,0xde8c); +reg_write( DDR_REG_BASE +0x509ad*4+0x02000000,0xd880); +reg_write( DDR_REG_BASE +0x509ae*4+0x02000000,0x60f8); +reg_write( DDR_REG_BASE +0x509af*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x509b0*4+0x02000000,0x6c0); +reg_write( DDR_REG_BASE +0x509b1*4+0x02000000,0xc180); +reg_write( DDR_REG_BASE +0x509b2*4+0x02000000,0xb4e); +reg_write( DDR_REG_BASE +0x509b3*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x509b4*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x509b5*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x509b6*4+0x02000000,0x722c); +reg_write( DDR_REG_BASE +0x509b7*4+0x02000000,0x80e); +reg_write( DDR_REG_BASE +0x509b8*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x509b9*4+0x02000000,0xc280); +reg_write( DDR_REG_BASE +0x509ba*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x509bb*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x509bc*4+0x02000000,0xd1a); +reg_write( DDR_REG_BASE +0x509bd*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x509be*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x509bf*4+0x02000000,0x66fe); +reg_write( DDR_REG_BASE +0x509c0*4+0x02000000,0x2605); +reg_write( DDR_REG_BASE +0x509c1*4+0x02000000,0x16c0); +reg_write( DDR_REG_BASE +0x509c2*4+0x02000000,0xc180); +reg_write( DDR_REG_BASE +0x509c3*4+0x02000000,0xb2e); +reg_write( DDR_REG_BASE +0x509c4*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x509c5*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x509c6*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x509c7*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x509c8*4+0x02000000,0xfea); +reg_write( DDR_REG_BASE +0x509c9*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x509ca*4+0x02000000,0xc280); +reg_write( DDR_REG_BASE +0x509cb*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x509cc*4+0x02000000,0x3d02); +reg_write( DDR_REG_BASE +0x509cd*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x509ce*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x509cf*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x509d0*4+0x02000000,0xc3e2); +reg_write( DDR_REG_BASE +0x509d1*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x509d2*4+0x02000000,0x3d02); +reg_write( DDR_REG_BASE +0x509d3*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x509d4*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x509d5*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x509d6*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x509d7*4+0x02000000,0xce6); +reg_write( DDR_REG_BASE +0x509d8*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x509d9*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x509da*4+0x02000000,0x2354); +reg_write( DDR_REG_BASE +0x509db*4+0x02000000,0xd00); +reg_write( DDR_REG_BASE +0x509dc*4+0x02000000,0xc180); +reg_write( DDR_REG_BASE +0x509dd*4+0x02000000,0xafa); +reg_write( DDR_REG_BASE +0x509de*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x509df*4+0x02000000,0xda09); +reg_write( DDR_REG_BASE +0x509e0*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x509e1*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x509e2*4+0x02000000,0xf5); +reg_write( DDR_REG_BASE +0x509e3*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x509e4*4+0x02000000,0xc9a); +reg_write( DDR_REG_BASE +0x509e5*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x509e6*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x509e7*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x509e8*4+0x02000000,0xd909); +reg_write( DDR_REG_BASE +0x509e9*4+0x02000000,0xfaa); +reg_write( DDR_REG_BASE +0x509ea*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x509eb*4+0x02000000,0xc280); +reg_write( DDR_REG_BASE +0x509ec*4+0x02000000,0xc7c2); +reg_write( DDR_REG_BASE +0x509ed*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x509ee*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x509ef*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x509f0*4+0x02000000,0x3d02); +reg_write( DDR_REG_BASE +0x509f1*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x509f2*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x509f3*4+0x02000000,0xcae); +reg_write( DDR_REG_BASE +0x509f4*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x509f5*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x509f6*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x509f7*4+0x02000000,0xf7); +reg_write( DDR_REG_BASE +0x509f8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x509f9*4+0x02000000,0xc72); +reg_write( DDR_REG_BASE +0x509fa*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x509fb*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x509fc*4+0x02000000,0xd840); +reg_write( DDR_REG_BASE +0x509fd*4+0x02000000,0xc180); +reg_write( DDR_REG_BASE +0x509fe*4+0x02000000,0xab6); +reg_write( DDR_REG_BASE +0x509ff*4+0x02000000,0x160); +reg_write( DDR_REG_BASE +0x50a00*4+0x02000000,0xda09); +reg_write( DDR_REG_BASE +0x50a01*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50a02*4+0x02000000,0xd909); +reg_write( DDR_REG_BASE +0x50a03*4+0x02000000,0xf76); +reg_write( DDR_REG_BASE +0x50a04*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50a05*4+0x02000000,0xc280); +reg_write( DDR_REG_BASE +0x50a06*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x50a07*4+0x02000000,0x3d02); +reg_write( DDR_REG_BASE +0x50a08*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x50a09*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50a0a*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50a0b*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50a0c*4+0x02000000,0x42eb); +reg_write( DDR_REG_BASE +0x50a0d*4+0x02000000,0xc0e6); +reg_write( DDR_REG_BASE +0x50a0e*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x50a0f*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50a10*4+0x02000000,0xe4); +reg_write( DDR_REG_BASE +0x50a11*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x50a12*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50a13*4+0x02000000,0x7b2); +reg_write( DDR_REG_BASE +0x50a14*4+0x02000000,0x833); +reg_write( DDR_REG_BASE +0x50a15*4+0x02000000,0xb0); +reg_write( DDR_REG_BASE +0x50a16*4+0x02000000,0x718d); +reg_write( DDR_REG_BASE +0x50a17*4+0x02000000,0x7114); +reg_write( DDR_REG_BASE +0x50a18*4+0x02000000,0xd823); +reg_write( DDR_REG_BASE +0x50a19*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50a1a*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50a1b*4+0x02000000,0x30); +reg_write( DDR_REG_BASE +0x50a1c*4+0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x50a1d*4+0x02000000,0xf427); +reg_write( DDR_REG_BASE +0x50a1e*4+0x02000000,0x8a25); +reg_write( DDR_REG_BASE +0x50a1f*4+0x02000000,0xaa23); +reg_write( DDR_REG_BASE +0x50a20*4+0x02000000,0x8aa4); +reg_write( DDR_REG_BASE +0x50a21*4+0x02000000,0x7c34); +reg_write( DDR_REG_BASE +0x50a22*4+0x02000000,0xaaa2); +reg_write( DDR_REG_BASE +0x50a23*4+0x02000000,0x96c0); +reg_write( DDR_REG_BASE +0x50a24*4+0x02000000,0x88e0); +reg_write( DDR_REG_BASE +0x50a25*4+0x02000000,0x78bb); +reg_write( DDR_REG_BASE +0x50a26*4+0x02000000,0xb3e0); +reg_write( DDR_REG_BASE +0x50a27*4+0x02000000,0xaa00); +reg_write( DDR_REG_BASE +0x50a28*4+0x02000000,0xe4d); +reg_write( DDR_REG_BASE +0x50a29*4+0x02000000,0x1171); +reg_write( DDR_REG_BASE +0x50a2a*4+0x02000000,0xaa81); +reg_write( DDR_REG_BASE +0x50a2b*4+0x02000000,0xb3e1); +reg_write( DDR_REG_BASE +0x50a2c*4+0x02000000,0xf024); +reg_write( DDR_REG_BASE +0x50a2d*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50a2e*4+0x02000000,0xb300); +reg_write( DDR_REG_BASE +0x50a2f*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50a30*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x50a31*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50a32*4+0x02000000,0x49); +reg_write( DDR_REG_BASE +0x50a33*4+0x02000000,0xb321); +reg_write( DDR_REG_BASE +0x50a34*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x50a35*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50a36*4+0x02000000,0xf6); +reg_write( DDR_REG_BASE +0x50a37*4+0x02000000,0xb300); +reg_write( DDR_REG_BASE +0x50a38*4+0x02000000,0xb304); +reg_write( DDR_REG_BASE +0x50a39*4+0x02000000,0x1b06); +reg_write( DDR_REG_BASE +0x50a3a*4+0x02000000,0x3c5); +reg_write( DDR_REG_BASE +0x50a3b*4+0x02000000,0x8a27); +reg_write( DDR_REG_BASE +0x50a3c*4+0x02000000,0xaa23); +reg_write( DDR_REG_BASE +0x50a3d*4+0x02000000,0x8a06); +reg_write( DDR_REG_BASE +0x50a3e*4+0x02000000,0xf818); +reg_write( DDR_REG_BASE +0x50a3f*4+0x02000000,0x1bfe); +reg_write( DDR_REG_BASE +0x50a40*4+0x02000000,0x83c5); +reg_write( DDR_REG_BASE +0x50a41*4+0x02000000,0x4759); +reg_write( DDR_REG_BASE +0x50a42*4+0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x50a43*4+0x02000000,0x88a0); +reg_write( DDR_REG_BASE +0x50a44*4+0x02000000,0xb3a0); +reg_write( DDR_REG_BASE +0x50a45*4+0x02000000,0x8a27); +reg_write( DDR_REG_BASE +0x50a46*4+0x02000000,0xaa23); +reg_write( DDR_REG_BASE +0x50a47*4+0x02000000,0x8a04); +reg_write( DDR_REG_BASE +0x50a48*4+0x02000000,0xf813); +reg_write( DDR_REG_BASE +0x50a49*4+0x02000000,0x9600); +reg_write( DDR_REG_BASE +0x50a4a*4+0x02000000,0x827); +reg_write( DDR_REG_BASE +0x50a4b*4+0x02000000,0x151); +reg_write( DDR_REG_BASE +0x50a4c*4+0x02000000,0xb3a1); +reg_write( DDR_REG_BASE +0x50a4d*4+0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x50a4e*4+0x02000000,0x1b02); +reg_write( DDR_REG_BASE +0x50a4f*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x50a50*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50a51*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50a52*4+0x02000000,0xfe); +reg_write( DDR_REG_BASE +0x50a53*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x50a54*4+0x02000000,0x3c5); +reg_write( DDR_REG_BASE +0x50a55*4+0x02000000,0x18f8); +reg_write( DDR_REG_BASE +0x50a56*4+0x02000000,0x83c5); +reg_write( DDR_REG_BASE +0x50a57*4+0x02000000,0x18f6); +reg_write( DDR_REG_BASE +0x50a58*4+0x02000000,0x8005); +reg_write( DDR_REG_BASE +0x50a59*4+0x02000000,0x18fe); +reg_write( DDR_REG_BASE +0x50a5a*4+0x02000000,0x8005); +reg_write( DDR_REG_BASE +0x50a5b*4+0x02000000,0x4759); +reg_write( DDR_REG_BASE +0x50a5c*4+0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x50a5d*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50a5e*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50a5f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50a60*4+0x02000000,0x49); +reg_write( DDR_REG_BASE +0x50a61*4+0x02000000,0xb301); +reg_write( DDR_REG_BASE +0x50a62*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50a63*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50a64*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50a65*4+0x02000000,0xf6); +reg_write( DDR_REG_BASE +0x50a66*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x50a67*4+0x02000000,0xb024); +reg_write( DDR_REG_BASE +0x50a68*4+0x02000000,0x18fe); +reg_write( DDR_REG_BASE +0x50a69*4+0x02000000,0x8044); +reg_write( DDR_REG_BASE +0x50a6a*4+0x02000000,0xb023); +reg_write( DDR_REG_BASE +0x50a6b*4+0x02000000,0x4759); +reg_write( DDR_REG_BASE +0x50a6c*4+0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x50a6d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50a6e*4+0x02000000,0x7c34); +reg_write( DDR_REG_BASE +0x50a6f*4+0x02000000,0xaa02); +reg_write( DDR_REG_BASE +0x50a70*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x50a71*4+0x02000000,0xaa00); +reg_write( DDR_REG_BASE +0x50a72*4+0x02000000,0xaa81); +reg_write( DDR_REG_BASE +0x50a73*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50a74*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50a75*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50a76*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50a77*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x50a78*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50a79*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x50a7a*4+0x02000000,0x9720); +reg_write( DDR_REG_BASE +0x50a7b*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50a7c*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50a7d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50a7e*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50a7f*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x50a80*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x50a81*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x50a82*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x50a83*4+0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x50a84*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x50a85*4+0x02000000,0xea06); +reg_write( DDR_REG_BASE +0x50a86*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x50a87*4+0x02000000,0xa01); +reg_write( DDR_REG_BASE +0x50a88*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x50a89*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50a8a*4+0x02000000,0xb8c3); +reg_write( DDR_REG_BASE +0x50a8b*4+0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x50a8c*4+0x02000000,0x70); +reg_write( DDR_REG_BASE +0x50a8d*4+0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x50a8e*4+0x02000000,0x807); +reg_write( DDR_REG_BASE +0x50a8f*4+0x02000000,0x190); +reg_write( DDR_REG_BASE +0x50a90*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x50a91*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50a92*4+0x02000000,0x996); +reg_write( DDR_REG_BASE +0x50a93*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50a94*4+0x02000000,0xd940); +reg_write( DDR_REG_BASE +0x50a95*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50a96*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x50a97*4+0x02000000,0xe112); +reg_write( DDR_REG_BASE +0x50a98*4+0x02000000,0x1ede); +reg_write( DDR_REG_BASE +0x50a99*4+0x02000000,0x1055); +reg_write( DDR_REG_BASE +0x50a9a*4+0x02000000,0x1ea6); +reg_write( DDR_REG_BASE +0x50a9b*4+0x02000000,0x9055); +reg_write( DDR_REG_BASE +0x50a9c*4+0x02000000,0x17b6); +reg_write( DDR_REG_BASE +0x50a9d*4+0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x50a9e*4+0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x50a9f*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50aa0*4+0x02000000,0xed29); +reg_write( DDR_REG_BASE +0x50aa1*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50aa2*4+0x02000000,0x84f); +reg_write( DDR_REG_BASE +0x50aa3*4+0x02000000,0x3bf); +reg_write( DDR_REG_BASE +0x50aa4*4+0x02000000,0xd91c); +reg_write( DDR_REG_BASE +0x50aa5*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50aa6*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x50aa7*4+0x02000000,0xc07); +reg_write( DDR_REG_BASE +0x50aa8*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x50aa9*4+0x02000000,0xb88f); +reg_write( DDR_REG_BASE +0x50aaa*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x50aab*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50aac*4+0x02000000,0x962); +reg_write( DDR_REG_BASE +0x50aad*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50aae*4+0x02000000,0x1ef6); +reg_write( DDR_REG_BASE +0x50aaf*4+0x02000000,0x9205); +reg_write( DDR_REG_BASE +0x50ab0*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50ab1*4+0x02000000,0xf); +reg_write( DDR_REG_BASE +0x50ab2*4+0x02000000,0x4240); +reg_write( DDR_REG_BASE +0x50ab3*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50ab4*4+0x02000000,0x952); +reg_write( DDR_REG_BASE +0x50ab5*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50ab6*4+0x02000000,0x1ef6); +reg_write( DDR_REG_BASE +0x50ab7*4+0x02000000,0x9245); +reg_write( DDR_REG_BASE +0x50ab8*4+0x02000000,0x17be); +reg_write( DDR_REG_BASE +0x50ab9*4+0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x50aba*4+0x02000000,0x1ef0); +reg_write( DDR_REG_BASE +0x50abb*4+0x02000000,0x9045); +reg_write( DDR_REG_BASE +0x50abc*4+0x02000000,0x1ef6); +reg_write( DDR_REG_BASE +0x50abd*4+0x02000000,0x9205); +reg_write( DDR_REG_BASE +0x50abe*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x50abf*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x50ac0*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x50ac1*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x50ac2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50ac3*4+0x02000000,0x3e00); +reg_write( DDR_REG_BASE +0x50ac4*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x50ac5*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50ac6*4+0x02000000,0xb88e); +reg_write( DDR_REG_BASE +0x50ac7*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x50ac8*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x50ac9*4+0x02000000,0x1ef6); +reg_write( DDR_REG_BASE +0x50aca*4+0x02000000,0x9205); +reg_write( DDR_REG_BASE +0x50acb*4+0x02000000,0x1ef0); +reg_write( DDR_REG_BASE +0x50acc*4+0x02000000,0x9045); +reg_write( DDR_REG_BASE +0x50acd*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50ace*4+0x02000000,0x76c4); +reg_write( DDR_REG_BASE +0x50acf*4+0x02000000,0x9013); +reg_write( DDR_REG_BASE +0x50ad0*4+0x02000000,0xe050); +reg_write( DDR_REG_BASE +0x50ad1*4+0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x50ad2*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50ad3*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50ad4*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50ad5*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50ad6*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x50ad7*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x50ad8*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50ad9*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50ada*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x50adb*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x50adc*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x50add*4+0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x50ade*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x50adf*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x50ae0*4+0x02000000,0xf2a); +reg_write( DDR_REG_BASE +0x50ae1*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50ae2*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x50ae3*4+0x02000000,0xd90c); +reg_write( DDR_REG_BASE +0x50ae4*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x50ae5*4+0x02000000,0xb990); +reg_write( DDR_REG_BASE +0x50ae6*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x50ae7*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x50ae8*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x50ae9*4+0x02000000,0x1c08); +reg_write( DDR_REG_BASE +0x50aea*4+0x02000000,0x3101); +reg_write( DDR_REG_BASE +0x50aeb*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x50aec*4+0x02000000,0xf12); +reg_write( DDR_REG_BASE +0x50aed*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50aee*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x50aef*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x50af0*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x50af1*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50af2*4+0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x50af3*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50af4*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50af5*4+0x02000000,0x256f); +reg_write( DDR_REG_BASE +0x50af6*4+0x02000000,0x1343); +reg_write( DDR_REG_BASE +0x50af7*4+0x02000000,0x4320); +reg_write( DDR_REG_BASE +0x50af8*4+0x02000000,0x9520); +reg_write( DDR_REG_BASE +0x50af9*4+0x02000000,0x218c); +reg_write( DDR_REG_BASE +0x50afa*4+0x02000000,0x864a); +reg_write( DDR_REG_BASE +0x50afb*4+0x02000000,0x7a); +reg_write( DDR_REG_BASE +0x50afc*4+0x02000000,0x2d); +reg_write( DDR_REG_BASE +0x50afd*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x50afe*4+0x02000000,0xa0e); +reg_write( DDR_REG_BASE +0x50aff*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x50b00*4+0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x50b01*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x50b02*4+0x02000000,0x15fe); +reg_write( DDR_REG_BASE +0x50b03*4+0x02000000,0x9080); +reg_write( DDR_REG_BASE +0x50b04*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x50b05*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50b06*4+0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x50b07*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x50b08*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50b09*4+0x02000000,0xf02b); +reg_write( DDR_REG_BASE +0x50b0a*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x50b0b*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x50b0c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50b0d*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x50b0e*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50b0f*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x50b10*4+0x02000000,0x341); +reg_write( DDR_REG_BASE +0x50b11*4+0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x50b12*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x50b13*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50b14*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50b15*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x50b16*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x50b17*4+0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x50b18*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50b19*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50b1a*4+0x02000000,0xa5e); +reg_write( DDR_REG_BASE +0x50b1b*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50b1c*4+0x02000000,0x9600); +reg_write( DDR_REG_BASE +0x50b1d*4+0x02000000,0xe01c); +reg_write( DDR_REG_BASE +0x50b1e*4+0x02000000,0x7a0e); +reg_write( DDR_REG_BASE +0x50b1f*4+0x02000000,0x785c); +reg_write( DDR_REG_BASE +0x50b20*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x50b21*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x50b22*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x50b23*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x50b24*4+0x02000000,0xd81b); +reg_write( DDR_REG_BASE +0x50b25*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x50b26*4+0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x50b27*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x50b28*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50b29*4+0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x50b2a*4+0x02000000,0x6238); +reg_write( DDR_REG_BASE +0x50b2b*4+0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x50b2c*4+0x02000000,0x4831); +reg_write( DDR_REG_BASE +0x50b2d*4+0x02000000,0x2a44); +reg_write( DDR_REG_BASE +0x50b2e*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x50b2f*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x50b30*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50b31*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50b32*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x50b33*4+0x02000000,0xbb1); +reg_write( DDR_REG_BASE +0x50b34*4+0x02000000,0xb0b4); +reg_write( DDR_REG_BASE +0x50b35*4+0x02000000,0x2655); +reg_write( DDR_REG_BASE +0x50b36*4+0x02000000,0x3800); +reg_write( DDR_REG_BASE +0x50b37*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50b38*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50b39*4+0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x50b3a*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x50b3b*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x50b3c*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50b3d*4+0x02000000,0x6); +reg_write( DDR_REG_BASE +0x50b3e*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x50b3f*4+0x02000000,0xfe6); +reg_write( DDR_REG_BASE +0x50b40*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50b41*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50b42*4+0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x50b43*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50b44*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x50b45*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x50b46*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50b47*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x50b48*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50b49*4+0x02000000,0x1c6); +reg_write( DDR_REG_BASE +0x50b4a*4+0x02000000,0x95c0); +reg_write( DDR_REG_BASE +0x50b4b*4+0x02000000,0xbecb); +reg_write( DDR_REG_BASE +0x50b4c*4+0x02000000,0x264f); +reg_write( DDR_REG_BASE +0x50b4d*4+0x02000000,0x12cf); +reg_write( DDR_REG_BASE +0x50b4e*4+0x02000000,0x2605); +reg_write( DDR_REG_BASE +0x50b4f*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x50b50*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50b51*4+0x02000000,0xc00); +reg_write( DDR_REG_BASE +0x50b52*4+0x02000000,0xb5e0); +reg_write( DDR_REG_BASE +0x50b53*4+0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x50b54*4+0x02000000,0xfba); +reg_write( DDR_REG_BASE +0x50b55*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x50b56*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x50b57*4+0x02000000,0xb5e0); +reg_write( DDR_REG_BASE +0x50b58*4+0x02000000,0x9501); +reg_write( DDR_REG_BASE +0x50b59*4+0x02000000,0xb5c0); +reg_write( DDR_REG_BASE +0x50b5a*4+0x02000000,0xb8c9); +reg_write( DDR_REG_BASE +0x50b5b*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50b5c*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50b5d*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50b5e*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50b5f*4+0x02000000,0xc1a6); +reg_write( DDR_REG_BASE +0x50b60*4+0x02000000,0x4378); +reg_write( DDR_REG_BASE +0x50b61*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50b62*4+0x02000000,0x7103); +reg_write( DDR_REG_BASE +0x50b63*4+0x02000000,0x9018); +reg_write( DDR_REG_BASE +0x50b64*4+0x02000000,0x1dc); +reg_write( DDR_REG_BASE +0x50b65*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50b66*4+0x02000000,0x308d); +reg_write( DDR_REG_BASE +0x50b67*4+0x02000000,0xc70b); +reg_write( DDR_REG_BASE +0x50b68*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x50b69*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x50b6a*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50b6b*4+0x02000000,0x47db); +reg_write( DDR_REG_BASE +0x50b6c*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50b6d*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x50b6e*4+0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x50b6f*4+0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x50b70*4+0x02000000,0x17cc); +reg_write( DDR_REG_BASE +0x50b71*4+0x02000000,0x9480); +reg_write( DDR_REG_BASE +0x50b72*4+0x02000000,0xc680); +reg_write( DDR_REG_BASE +0x50b73*4+0x02000000,0x667e); +reg_write( DDR_REG_BASE +0x50b74*4+0x02000000,0xae80); +reg_write( DDR_REG_BASE +0x50b75*4+0x02000000,0x2740); +reg_write( DDR_REG_BASE +0x50b76*4+0x02000000,0x380c); +reg_write( DDR_REG_BASE +0x50b77*4+0x02000000,0x2405); +reg_write( DDR_REG_BASE +0x50b78*4+0x02000000,0x12cc); +reg_write( DDR_REG_BASE +0x50b79*4+0x02000000,0x9480); +reg_write( DDR_REG_BASE +0x50b7a*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x50b7b*4+0x02000000,0xe40c); +reg_write( DDR_REG_BASE +0x50b7c*4+0x02000000,0xae8c); +reg_write( DDR_REG_BASE +0x50b7d*4+0x02000000,0xbe7); +reg_write( DDR_REG_BASE +0x50b7e*4+0x02000000,0x82b4); +reg_write( DDR_REG_BASE +0x50b7f*4+0x02000000,0x232f); +reg_write( DDR_REG_BASE +0x50b80*4+0x02000000,0x10c0); +reg_write( DDR_REG_BASE +0x50b81*4+0x02000000,0xe58c); +reg_write( DDR_REG_BASE +0x50b82*4+0x02000000,0x256); +reg_write( DDR_REG_BASE +0x50b83*4+0x02000000,0x2d); +reg_write( DDR_REG_BASE +0x50b84*4+0x02000000,0x238a); +reg_write( DDR_REG_BASE +0x50b85*4+0x02000000,0x205); +reg_write( DDR_REG_BASE +0x50b86*4+0x02000000,0xb7f); +reg_write( DDR_REG_BASE +0x50b87*4+0x02000000,0x36e); +reg_write( DDR_REG_BASE +0x50b88*4+0x02000000,0x738d); +reg_write( DDR_REG_BASE +0x50b89*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x50b8a*4+0x02000000,0x72ad); +reg_write( DDR_REG_BASE +0x50b8b*4+0x02000000,0x1b00); +reg_write( DDR_REG_BASE +0x50b8c*4+0x02000000,0x3302); +reg_write( DDR_REG_BASE +0x50b8d*4+0x02000000,0x1f02); +reg_write( DDR_REG_BASE +0x50b8e*4+0x02000000,0x1782); +reg_write( DDR_REG_BASE +0x50b8f*4+0x02000000,0x1f01); +reg_write( DDR_REG_BASE +0x50b90*4+0x02000000,0x1782); +reg_write( DDR_REG_BASE +0x50b91*4+0x02000000,0x1f00); +reg_write( DDR_REG_BASE +0x50b92*4+0x02000000,0x1782); +reg_write( DDR_REG_BASE +0x50b93*4+0x02000000,0xa962); +reg_write( DDR_REG_BASE +0x50b94*4+0x02000000,0xa981); +reg_write( DDR_REG_BASE +0x50b95*4+0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50b96*4+0x02000000,0xaaa4); +reg_write( DDR_REG_BASE +0x50b97*4+0x02000000,0x1a03); +reg_write( DDR_REG_BASE +0x50b98*4+0x02000000,0x43); +reg_write( DDR_REG_BASE +0x50b99*4+0x02000000,0x1a02); +reg_write( DDR_REG_BASE +0x50b9a*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50b9b*4+0x02000000,0xc120); +reg_write( DDR_REG_BASE +0x50b9c*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50b9d*4+0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50b9e*4+0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x50b9f*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50ba0*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50ba1*4+0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50ba2*4+0x02000000,0x1402); +reg_write( DDR_REG_BASE +0x50ba3*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50ba4*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50ba5*4+0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50ba6*4+0x02000000,0x1403); +reg_write( DDR_REG_BASE +0x50ba7*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50ba8*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50ba9*4+0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50baa*4+0x02000000,0xc121); +reg_write( DDR_REG_BASE +0x50bab*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50bac*4+0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50bad*4+0x02000000,0x1405); +reg_write( DDR_REG_BASE +0x50bae*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50baf*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50bb0*4+0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50bb1*4+0x02000000,0x1406); +reg_write( DDR_REG_BASE +0x50bb2*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50bb3*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50bb4*4+0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50bb5*4+0x02000000,0x1407); +reg_write( DDR_REG_BASE +0x50bb6*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50bb7*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50bb8*4+0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50bb9*4+0x02000000,0xc122); +reg_write( DDR_REG_BASE +0x50bba*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50bbb*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50bbc*4+0x02000000,0x1409); +reg_write( DDR_REG_BASE +0x50bbd*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50bbe*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50bbf*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50bc0*4+0x02000000,0x180b); +reg_write( DDR_REG_BASE +0x50bc1*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50bc2*4+0x02000000,0x180a); +reg_write( DDR_REG_BASE +0x50bc3*4+0x02000000,0x43); +reg_write( DDR_REG_BASE +0x50bc4*4+0x02000000,0xf0e9); +reg_write( DDR_REG_BASE +0x50bc5*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x50bc6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50bc7*4+0x02000000,0x1400); +reg_write( DDR_REG_BASE +0x50bc8*4+0x02000000,0x2311); +reg_write( DDR_REG_BASE +0x50bc9*4+0x02000000,0x8340); +reg_write( DDR_REG_BASE +0x50bca*4+0x02000000,0xf2e3); +reg_write( DDR_REG_BASE +0x50bcb*4+0x02000000,0x718d); +reg_write( DDR_REG_BASE +0x50bcc*4+0x02000000,0xaf85); +reg_write( DDR_REG_BASE +0x50bcd*4+0x02000000,0xaf84); +reg_write( DDR_REG_BASE +0x50bce*4+0x02000000,0xaf83); +reg_write( DDR_REG_BASE +0x50bcf*4+0x02000000,0x1f02); +reg_write( DDR_REG_BASE +0x50bd0*4+0x02000000,0x1782); +reg_write( DDR_REG_BASE +0x50bd1*4+0x02000000,0x1f01); +reg_write( DDR_REG_BASE +0x50bd2*4+0x02000000,0x1782); +reg_write( DDR_REG_BASE +0x50bd3*4+0x02000000,0x1f00); +reg_write( DDR_REG_BASE +0x50bd4*4+0x02000000,0x1782); +reg_write( DDR_REG_BASE +0x50bd5*4+0x02000000,0x76ef); +reg_write( DDR_REG_BASE +0x50bd6*4+0x02000000,0xe58c); +reg_write( DDR_REG_BASE +0x50bd7*4+0x02000000,0xde08); +reg_write( DDR_REG_BASE +0x50bd8*4+0x02000000,0xdf07); +reg_write( DDR_REG_BASE +0x50bd9*4+0x02000000,0x73ad); +reg_write( DDR_REG_BASE +0x50bda*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x50bdb*4+0x02000000,0x746d); +reg_write( DDR_REG_BASE +0x50bdc*4+0x02000000,0x1b00); +reg_write( DDR_REG_BASE +0x50bdd*4+0x02000000,0x37c2); +reg_write( DDR_REG_BASE +0x50bde*4+0x02000000,0xf467); +reg_write( DDR_REG_BASE +0x50bdf*4+0x02000000,0xa9c5); +reg_write( DDR_REG_BASE +0x50be0*4+0x02000000,0xa9e4); +reg_write( DDR_REG_BASE +0x50be1*4+0x02000000,0x1903); +reg_write( DDR_REG_BASE +0x50be2*4+0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x50be3*4+0x02000000,0xa9a2); +reg_write( DDR_REG_BASE +0x50be4*4+0x02000000,0xa961); +reg_write( DDR_REG_BASE +0x50be5*4+0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50be6*4+0x02000000,0x752c); +reg_write( DDR_REG_BASE +0x50be7*4+0x02000000,0xaa28); +reg_write( DDR_REG_BASE +0x50be8*4+0x02000000,0x1a07); +reg_write( DDR_REG_BASE +0x50be9*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50bea*4+0x02000000,0xaaa6); +reg_write( DDR_REG_BASE +0x50beb*4+0x02000000,0xaa63); +reg_write( DDR_REG_BASE +0x50bec*4+0x02000000,0xaa82); +reg_write( DDR_REG_BASE +0x50bed*4+0x02000000,0x1a01); +reg_write( DDR_REG_BASE +0x50bee*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50bef*4+0x02000000,0xc120); +reg_write( DDR_REG_BASE +0x50bf0*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50bf1*4+0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50bf2*4+0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x50bf3*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50bf4*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50bf5*4+0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50bf6*4+0x02000000,0x1402); +reg_write( DDR_REG_BASE +0x50bf7*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50bf8*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50bf9*4+0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50bfa*4+0x02000000,0x1403); +reg_write( DDR_REG_BASE +0x50bfb*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50bfc*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50bfd*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50bfe*4+0x02000000,0xc121); +reg_write( DDR_REG_BASE +0x50bff*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c00*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50c01*4+0x02000000,0x1405); +reg_write( DDR_REG_BASE +0x50c02*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50c03*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c04*4+0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50c05*4+0x02000000,0x1406); +reg_write( DDR_REG_BASE +0x50c06*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50c07*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c08*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50c09*4+0x02000000,0x1407); +reg_write( DDR_REG_BASE +0x50c0a*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50c0b*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c0c*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50c0d*4+0x02000000,0xc122); +reg_write( DDR_REG_BASE +0x50c0e*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c0f*4+0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50c10*4+0x02000000,0x1409); +reg_write( DDR_REG_BASE +0x50c11*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50c12*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c13*4+0x02000000,0xa980); +reg_write( DDR_REG_BASE +0x50c14*4+0x02000000,0x180b); +reg_write( DDR_REG_BASE +0x50c15*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x50c16*4+0x02000000,0x180a); +reg_write( DDR_REG_BASE +0x50c17*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50c18*4+0x02000000,0xc123); +reg_write( DDR_REG_BASE +0x50c19*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c1a*4+0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50c1b*4+0x02000000,0x140d); +reg_write( DDR_REG_BASE +0x50c1c*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50c1d*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c1e*4+0x02000000,0xa9c0); +reg_write( DDR_REG_BASE +0x50c1f*4+0x02000000,0x140e); +reg_write( DDR_REG_BASE +0x50c20*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50c21*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c22*4+0x02000000,0xa9c0); +reg_write( DDR_REG_BASE +0x50c23*4+0x02000000,0x140f); +reg_write( DDR_REG_BASE +0x50c24*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50c25*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c26*4+0x02000000,0xa9c0); +reg_write( DDR_REG_BASE +0x50c27*4+0x02000000,0xc124); +reg_write( DDR_REG_BASE +0x50c28*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c29*4+0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50c2a*4+0x02000000,0x1411); +reg_write( DDR_REG_BASE +0x50c2b*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50c2c*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c2d*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50c2e*4+0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x50c2f*4+0x02000000,0x1412); +reg_write( DDR_REG_BASE +0x50c30*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50c31*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c32*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50c33*4+0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x50c34*4+0x02000000,0x1413); +reg_write( DDR_REG_BASE +0x50c35*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50c36*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c37*4+0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50c38*4+0x02000000,0xc125); +reg_write( DDR_REG_BASE +0x50c39*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c3a*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50c3b*4+0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x50c3c*4+0x02000000,0x1415); +reg_write( DDR_REG_BASE +0x50c3d*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50c3e*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c3f*4+0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50c40*4+0x02000000,0x752c); +reg_write( DDR_REG_BASE +0x50c41*4+0x02000000,0x1817); +reg_write( DDR_REG_BASE +0x50c42*4+0x02000000,0x283); +reg_write( DDR_REG_BASE +0x50c43*4+0x02000000,0xa836); +reg_write( DDR_REG_BASE +0x50c44*4+0x02000000,0xf069); +reg_write( DDR_REG_BASE +0x50c45*4+0x02000000,0x234a); +reg_write( DDR_REG_BASE +0x50c46*4+0x02000000,0x3240); +reg_write( DDR_REG_BASE +0x50c47*4+0x02000000,0x1905); +reg_write( DDR_REG_BASE +0x50c48*4+0x02000000,0x6c2); +reg_write( DDR_REG_BASE +0x50c49*4+0x02000000,0xa9c4); +reg_write( DDR_REG_BASE +0x50c4a*4+0x02000000,0xa9e3); +reg_write( DDR_REG_BASE +0x50c4b*4+0x02000000,0x1902); +reg_write( DDR_REG_BASE +0x50c4c*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50c4d*4+0x02000000,0xa9a1); +reg_write( DDR_REG_BASE +0x50c4e*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50c4f*4+0x02000000,0x752c); +reg_write( DDR_REG_BASE +0x50c50*4+0x02000000,0xaa29); +reg_write( DDR_REG_BASE +0x50c51*4+0x02000000,0x1a08); +reg_write( DDR_REG_BASE +0x50c52*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50c53*4+0x02000000,0xaaa7); +reg_write( DDR_REG_BASE +0x50c54*4+0x02000000,0xaa64); +reg_write( DDR_REG_BASE +0x50c55*4+0x02000000,0xaa83); +reg_write( DDR_REG_BASE +0x50c56*4+0x02000000,0x1a02); +reg_write( DDR_REG_BASE +0x50c57*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50c58*4+0x02000000,0xc120); +reg_write( DDR_REG_BASE +0x50c59*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c5a*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50c5b*4+0x02000000,0x1401); +reg_write( DDR_REG_BASE +0x50c5c*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50c5d*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c5e*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50c5f*4+0x02000000,0x1402); +reg_write( DDR_REG_BASE +0x50c60*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50c61*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c62*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50c63*4+0x02000000,0x1403); +reg_write( DDR_REG_BASE +0x50c64*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50c65*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c66*4+0x02000000,0xa960); +reg_write( DDR_REG_BASE +0x50c67*4+0x02000000,0xc121); +reg_write( DDR_REG_BASE +0x50c68*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c69*4+0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50c6a*4+0x02000000,0x1405); +reg_write( DDR_REG_BASE +0x50c6b*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50c6c*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c6d*4+0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50c6e*4+0x02000000,0x1406); +reg_write( DDR_REG_BASE +0x50c6f*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50c70*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c71*4+0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50c72*4+0x02000000,0x1407); +reg_write( DDR_REG_BASE +0x50c73*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50c74*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c75*4+0x02000000,0xa9a0); +reg_write( DDR_REG_BASE +0x50c76*4+0x02000000,0xc122); +reg_write( DDR_REG_BASE +0x50c77*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c78*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50c79*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50c7a*4+0x02000000,0x1409); +reg_write( DDR_REG_BASE +0x50c7b*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50c7c*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c7d*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50c7e*4+0x02000000,0x2c2); +reg_write( DDR_REG_BASE +0x50c7f*4+0x02000000,0x180b); +reg_write( DDR_REG_BASE +0x50c80*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x50c81*4+0x02000000,0xa88a); +reg_write( DDR_REG_BASE +0x50c82*4+0x02000000,0xc123); +reg_write( DDR_REG_BASE +0x50c83*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c84*4+0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50c85*4+0x02000000,0x140d); +reg_write( DDR_REG_BASE +0x50c86*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50c87*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c88*4+0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50c89*4+0x02000000,0x140e); +reg_write( DDR_REG_BASE +0x50c8a*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50c8b*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c8c*4+0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50c8d*4+0x02000000,0x140f); +reg_write( DDR_REG_BASE +0x50c8e*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50c8f*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c90*4+0x02000000,0xa9e0); +reg_write( DDR_REG_BASE +0x50c91*4+0x02000000,0xc124); +reg_write( DDR_REG_BASE +0x50c92*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c93*4+0x02000000,0xa9c0); +reg_write( DDR_REG_BASE +0x50c94*4+0x02000000,0x1411); +reg_write( DDR_REG_BASE +0x50c95*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50c96*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c97*4+0x02000000,0xa9c0); +reg_write( DDR_REG_BASE +0x50c98*4+0x02000000,0x1412); +reg_write( DDR_REG_BASE +0x50c99*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50c9a*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c9b*4+0x02000000,0xa9c0); +reg_write( DDR_REG_BASE +0x50c9c*4+0x02000000,0x1413); +reg_write( DDR_REG_BASE +0x50c9d*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50c9e*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50c9f*4+0x02000000,0xa9c0); +reg_write( DDR_REG_BASE +0x50ca0*4+0x02000000,0xc125); +reg_write( DDR_REG_BASE +0x50ca1*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50ca2*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50ca3*4+0x02000000,0x6c2); +reg_write( DDR_REG_BASE +0x50ca4*4+0x02000000,0x1415); +reg_write( DDR_REG_BASE +0x50ca5*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x50ca6*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x50ca7*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x50ca8*4+0x02000000,0x6c2); +reg_write( DDR_REG_BASE +0x50ca9*4+0x02000000,0x752c); +reg_write( DDR_REG_BASE +0x50caa*4+0x02000000,0xa837); +reg_write( DDR_REG_BASE +0x50cab*4+0x02000000,0x1816); +reg_write( DDR_REG_BASE +0x50cac*4+0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x50cad*4+0x02000000,0xc0a6); +reg_write( DDR_REG_BASE +0x50cae*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50caf*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50cb0*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50cb1*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50cb2*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x50cb3*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50cb4*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50cb5*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50cb6*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50cb7*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50cb8*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50cb9*4+0x02000000,0x168); +reg_write( DDR_REG_BASE +0x50cba*4+0x02000000,0x21c2); +reg_write( DDR_REG_BASE +0x50cbb*4+0x02000000,0x222); +reg_write( DDR_REG_BASE +0x50cbc*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x50cbd*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50cbe*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50cbf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50cc0*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x50cc1*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50cc2*4+0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x50cc3*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50cc4*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50cc5*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x50cc6*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50cc7*4+0x02000000,0x6e); +reg_write( DDR_REG_BASE +0x50cc8*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x50cc9*4+0x02000000,0x7de0); +reg_write( DDR_REG_BASE +0x50cca*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50ccb*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x50ccc*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50ccd*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x50cce*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50ccf*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50cd0*4+0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x50cd1*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x50cd2*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50cd3*4+0x02000000,0x7b1); +reg_write( DDR_REG_BASE +0x50cd4*4+0x02000000,0x8b00); +reg_write( DDR_REG_BASE +0x50cd5*4+0x02000000,0xe62); +reg_write( DDR_REG_BASE +0x50cd6*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50cd7*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x50cd8*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50cd9*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x50cda*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50cdb*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50cdc*4+0x02000000,0x8b82); +reg_write( DDR_REG_BASE +0x50cdd*4+0x02000000,0x8b41); +reg_write( DDR_REG_BASE +0x50cde*4+0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x50cdf*4+0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x50ce0*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x50ce1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50ce2*4+0x02000000,0x776c); +reg_write( DDR_REG_BASE +0x50ce3*4+0x02000000,0xf01c); +reg_write( DDR_REG_BASE +0x50ce4*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x50ce5*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x50ce6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50ce7*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x50ce8*4+0x02000000,0x2104); +reg_write( DDR_REG_BASE +0x50ce9*4+0x02000000,0xf8e); +reg_write( DDR_REG_BASE +0x50cea*4+0x02000000,0x37fe); +reg_write( DDR_REG_BASE +0x50ceb*4+0x02000000,0xf000); +reg_write( DDR_REG_BASE +0x50cec*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x50ced*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x50cee*4+0x02000000,0x79a5); +reg_write( DDR_REG_BASE +0x50cef*4+0x02000000,0x79c5); +reg_write( DDR_REG_BASE +0x50cf0*4+0x02000000,0x6ac1); +reg_write( DDR_REG_BASE +0x50cf1*4+0x02000000,0x229a); +reg_write( DDR_REG_BASE +0x50cf2*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50cf3*4+0x02000000,0x2284); +reg_write( DDR_REG_BASE +0x50cf4*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50cf5*4+0x02000000,0x7a25); +reg_write( DDR_REG_BASE +0x50cf6*4+0x02000000,0x795b); +reg_write( DDR_REG_BASE +0x50cf7*4+0x02000000,0xb991); +reg_write( DDR_REG_BASE +0x50cf8*4+0x02000000,0xb99c); +reg_write( DDR_REG_BASE +0x50cf9*4+0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x50cfa*4+0x02000000,0x9120); +reg_write( DDR_REG_BASE +0x50cfb*4+0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x50cfc*4+0x02000000,0x2108); +reg_write( DDR_REG_BASE +0x50cfd*4+0x02000000,0xc3); +reg_write( DDR_REG_BASE +0x50cfe*4+0x02000000,0xccd); +reg_write( DDR_REG_BASE +0x50cff*4+0x02000000,0x9085); +reg_write( DDR_REG_BASE +0x50d00*4+0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x50d01*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x50d02*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x50d03*4+0x02000000,0x901); +reg_write( DDR_REG_BASE +0x50d04*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x50d05*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x50d06*4+0x02000000,0x796f); +reg_write( DDR_REG_BASE +0x50d07*4+0x02000000,0x2179); +reg_write( DDR_REG_BASE +0x50d08*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x50d09*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x50d0a*4+0x02000000,0x7204); +reg_write( DDR_REG_BASE +0x50d0b*4+0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x50d0c*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50d0d*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50d0e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50d0f*4+0x02000000,0x32); +reg_write( DDR_REG_BASE +0x50d10*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x50d11*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50d12*4+0x02000000,0xb8c3); +reg_write( DDR_REG_BASE +0x50d13*4+0x02000000,0x6829); +reg_write( DDR_REG_BASE +0x50d14*4+0x02000000,0x92b); +reg_write( DDR_REG_BASE +0x50d15*4+0x02000000,0x3b5); +reg_write( DDR_REG_BASE +0x50d16*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x50d17*4+0x02000000,0x2025); +reg_write( DDR_REG_BASE +0x50d18*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x50d19*4+0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x50d1a*4+0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x50d1b*4+0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x50d1c*4+0x02000000,0xf00b); +reg_write( DDR_REG_BASE +0x50d1d*4+0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x50d1e*4+0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x50d1f*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x50d20*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x50d21*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x50d22*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x50d23*4+0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x50d24*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x50d25*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x50d26*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x50d27*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50d28*4+0x02000000,0x760c); +reg_write( DDR_REG_BASE +0x50d29*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50d2a*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50d2b*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50d2c*4+0x02000000,0xd807); +reg_write( DDR_REG_BASE +0x50d2d*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50d2e*4+0x02000000,0xd808); +reg_write( DDR_REG_BASE +0x50d2f*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50d30*4+0x02000000,0xd809); +reg_write( DDR_REG_BASE +0x50d31*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50d32*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x50d33*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50d34*4+0x02000000,0xd80b); +reg_write( DDR_REG_BASE +0x50d35*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50d36*4+0x02000000,0xd80c); +reg_write( DDR_REG_BASE +0x50d37*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50d38*4+0x02000000,0xd80e); +reg_write( DDR_REG_BASE +0x50d39*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50d3a*4+0x02000000,0xd810); +reg_write( DDR_REG_BASE +0x50d3b*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50d3c*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50d3d*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x50d3e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50d3f*4+0x02000000,0x32); +reg_write( DDR_REG_BASE +0x50d40*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x50d41*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50d42*4+0x02000000,0x2053); +reg_write( DDR_REG_BASE +0x50d43*4+0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x50d44*4+0x02000000,0x6949); +reg_write( DDR_REG_BASE +0x50d45*4+0x02000000,0xa3f); +reg_write( DDR_REG_BASE +0x50d46*4+0x02000000,0x3b5); +reg_write( DDR_REG_BASE +0x50d47*4+0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x50d48*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50d49*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50d4a*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50d4b*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50d4c*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50d4d*4+0x02000000,0x720c); +reg_write( DDR_REG_BASE +0x50d4e*4+0x02000000,0x2025); +reg_write( DDR_REG_BASE +0x50d4f*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x50d50*4+0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x50d51*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x50d52*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x50d53*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x50d54*4+0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x50d55*4+0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x50d56*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x50d57*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x50d58*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x50d59*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x50d5a*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x50d5b*4+0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x50d5c*4+0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x50d5d*4+0x02000000,0xf015); +reg_write( DDR_REG_BASE +0x50d5e*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50d5f*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x50d60*4+0x02000000,0xb9e0); +reg_write( DDR_REG_BASE +0x50d61*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x50d62*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x50d63*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x50d64*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50d65*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50d66*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x50d67*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50d68*4+0x02000000,0x760c); +reg_write( DDR_REG_BASE +0x50d69*4+0x02000000,0xb9e0); +reg_write( DDR_REG_BASE +0x50d6a*4+0x02000000,0xd809); +reg_write( DDR_REG_BASE +0x50d6b*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50d6c*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x50d6d*4+0x02000000,0x1e1); +reg_write( DDR_REG_BASE +0x50d6e*4+0x02000000,0xb9e0); +reg_write( DDR_REG_BASE +0x50d6f*4+0x02000000,0xd80c); +reg_write( DDR_REG_BASE +0x50d70*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x50d71*4+0x02000000,0xb9e0); +reg_write( DDR_REG_BASE +0x50d72*4+0x02000000,0xd80e); +reg_write( DDR_REG_BASE +0x50d73*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50d74*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x50d75*4+0x02000000,0x261); +reg_write( DDR_REG_BASE +0x50d76*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50d77*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50d78*4+0x02000000,0x7b2); +reg_write( DDR_REG_BASE +0x50d79*4+0x02000000,0x8881); +reg_write( DDR_REG_BASE +0x50d7a*4+0x02000000,0x8860); +reg_write( DDR_REG_BASE +0x50d7b*4+0x02000000,0xf022); +reg_write( DDR_REG_BASE +0x50d7c*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x50d7d*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50d7e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50d7f*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x50d80*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x50d81*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x50d82*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50d83*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x50d84*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x50d85*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50d86*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50d87*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x50d88*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x50d89*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50d8a*4+0x02000000,0x6ffd); +reg_write( DDR_REG_BASE +0x50d8b*4+0x02000000,0xe000); +reg_write( DDR_REG_BASE +0x50d8c*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x50d8d*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x50d8e*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x50d8f*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50d90*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x50d91*4+0x02000000,0x9220); +reg_write( DDR_REG_BASE +0x50d92*4+0x02000000,0x4928); +reg_write( DDR_REG_BASE +0x50d93*4+0x02000000,0x208b); +reg_write( DDR_REG_BASE +0x50d94*4+0x02000000,0x880f); +reg_write( DDR_REG_BASE +0x50d95*4+0x02000000,0xf206); +reg_write( DDR_REG_BASE +0x50d96*4+0x02000000,0x2142); +reg_write( DDR_REG_BASE +0x50d97*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x50d98*4+0x02000000,0x2080); +reg_write( DDR_REG_BASE +0x50d99*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x50d9a*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x50d9b*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x50d9c*4+0x02000000,0xcc1); +reg_write( DDR_REG_BASE +0x50d9d*4+0x02000000,0x90c5); +reg_write( DDR_REG_BASE +0x50d9e*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50d9f*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50da0*4+0x02000000,0xc0e4); +reg_write( DDR_REG_BASE +0x50da1*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x50da2*4+0x02000000,0x259a); +reg_write( DDR_REG_BASE +0x50da3*4+0x02000000,0x1008); +reg_write( DDR_REG_BASE +0x50da4*4+0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x50da5*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x50da6*4+0x02000000,0x48); +reg_write( DDR_REG_BASE +0x50da7*4+0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x50da8*4+0x02000000,0x130e); +reg_write( DDR_REG_BASE +0x50da9*4+0x02000000,0xb620); +reg_write( DDR_REG_BASE +0x50daa*4+0x02000000,0x6c22); +reg_write( DDR_REG_BASE +0x50dab*4+0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x50dac*4+0x02000000,0x104c); +reg_write( DDR_REG_BASE +0x50dad*4+0x02000000,0x7224); +reg_write( DDR_REG_BASE +0x50dae*4+0x02000000,0xb440); +reg_write( DDR_REG_BASE +0x50daf*4+0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x50db0*4+0x02000000,0x1042); +reg_write( DDR_REG_BASE +0x50db1*4+0x02000000,0xb260); +reg_write( DDR_REG_BASE +0x50db2*4+0x02000000,0x6962); +reg_write( DDR_REG_BASE +0x50db3*4+0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x50db4*4+0x02000000,0x7d65); +reg_write( DDR_REG_BASE +0x50db5*4+0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x50db6*4+0x02000000,0x3f1); +reg_write( DDR_REG_BASE +0x50db7*4+0x02000000,0xb520); +reg_write( DDR_REG_BASE +0x50db8*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x50db9*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x50dba*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x50dbb*4+0x02000000,0x137c); +reg_write( DDR_REG_BASE +0x50dbc*4+0x02000000,0x101); +reg_write( DDR_REG_BASE +0x50dbd*4+0x02000000,0x210f); +reg_write( DDR_REG_BASE +0x50dbe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50dbf*4+0x02000000,0x1b7c); +reg_write( DDR_REG_BASE +0x50dc0*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50dc1*4+0x02000000,0xc4c4); +reg_write( DDR_REG_BASE +0x50dc2*4+0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x50dc3*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x50dc4*4+0x02000000,0xc2); +reg_write( DDR_REG_BASE +0x50dc5*4+0x02000000,0x1c02); +reg_write( DDR_REG_BASE +0x50dc6*4+0x02000000,0x1014); +reg_write( DDR_REG_BASE +0x50dc7*4+0x02000000,0xb420); +reg_write( DDR_REG_BASE +0x50dc8*4+0x02000000,0xb441); +reg_write( DDR_REG_BASE +0x50dc9*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50dca*4+0x02000000,0xb462); +reg_write( DDR_REG_BASE +0x50dcb*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50dcc*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50dcd*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50dce*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50dcf*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x50dd0*4+0x02000000,0xca08); +reg_write( DDR_REG_BASE +0x50dd1*4+0x02000000,0x4358); +reg_write( DDR_REG_BASE +0x50dd2*4+0x02000000,0xda08); +reg_write( DDR_REG_BASE +0x50dd3*4+0x02000000,0x7a16); +reg_write( DDR_REG_BASE +0x50dd4*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50dd5*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x50dd6*4+0x02000000,0xe024); +reg_write( DDR_REG_BASE +0x50dd7*4+0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x50dd8*4+0x02000000,0x228a); +reg_write( DDR_REG_BASE +0x50dd9*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x50dda*4+0x02000000,0x180c); +reg_write( DDR_REG_BASE +0x50ddb*4+0x02000000,0x45); +reg_write( DDR_REG_BASE +0x50ddc*4+0x02000000,0x18fe); +reg_write( DDR_REG_BASE +0x50ddd*4+0x02000000,0x8084); +reg_write( DDR_REG_BASE +0x50dde*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50ddf*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50de0*4+0x02000000,0x7b4); +reg_write( DDR_REG_BASE +0x50de1*4+0x02000000,0x8861); +reg_write( DDR_REG_BASE +0x50de2*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50de3*4+0x02000000,0x708c); +reg_write( DDR_REG_BASE +0x50de4*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50de5*4+0x02000000,0x7b4); +reg_write( DDR_REG_BASE +0x50de6*4+0x02000000,0x86e0); +reg_write( DDR_REG_BASE +0x50de7*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x50de8*4+0x02000000,0xf022); +reg_write( DDR_REG_BASE +0x50de9*4+0x02000000,0x241a); +reg_write( DDR_REG_BASE +0x50dea*4+0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x50deb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50dec*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x50ded*4+0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x50dee*4+0x02000000,0x30b); +reg_write( DDR_REG_BASE +0x50def*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x50df0*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50df1*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50df2*4+0x02000000,0x1064); +reg_write( DDR_REG_BASE +0x50df3*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x50df4*4+0x02000000,0x2c4); +reg_write( DDR_REG_BASE +0x50df5*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x50df6*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x50df7*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50df8*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50df9*4+0x02000000,0xb17); +reg_write( DDR_REG_BASE +0x50dfa*4+0x02000000,0x3030); +reg_write( DDR_REG_BASE +0x50dfb*4+0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x50dfc*4+0x02000000,0x300); +reg_write( DDR_REG_BASE +0x50dfd*4+0x02000000,0x815); +reg_write( DDR_REG_BASE +0x50dfe*4+0x02000000,0xf84); +reg_write( DDR_REG_BASE +0x50dff*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50e00*4+0x02000000,0xfc00); +reg_write( DDR_REG_BASE +0x50e01*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x50e02*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x50e03*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x50e04*4+0x02000000,0x8010); +reg_write( DDR_REG_BASE +0x50e05*4+0x02000000,0xf7bd); +reg_write( DDR_REG_BASE +0x50e06*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x50e07*4+0x02000000,0x808); +reg_write( DDR_REG_BASE +0x50e08*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x50e09*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x50e0a*4+0x02000000,0xbbf); +reg_write( DDR_REG_BASE +0x50e0b*4+0x02000000,0x8305); +reg_write( DDR_REG_BASE +0x50e0c*4+0x02000000,0xa02); +reg_write( DDR_REG_BASE +0x50e0d*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x50e0e*4+0x02000000,0xb0b); +reg_write( DDR_REG_BASE +0x50e0f*4+0x02000000,0x3030); +reg_write( DDR_REG_BASE +0x50e10*4+0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x50e11*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x50e12*4+0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x50e13*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x50e14*4+0x02000000,0xf72); +reg_write( DDR_REG_BASE +0x50e15*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x50e16*4+0x02000000,0xbfc4); +reg_write( DDR_REG_BASE +0x50e17*4+0x02000000,0xef06); +reg_write( DDR_REG_BASE +0x50e18*4+0x02000000,0xbf61); +reg_write( DDR_REG_BASE +0x50e19*4+0x02000000,0xf01); +reg_write( DDR_REG_BASE +0x50e1a*4+0x02000000,0x1031); +reg_write( DDR_REG_BASE +0x50e1b*4+0x02000000,0x7dbb); +reg_write( DDR_REG_BASE +0x50e1c*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x50e1d*4+0x02000000,0x8607); +reg_write( DDR_REG_BASE +0x50e1e*4+0x02000000,0xf6d); +reg_write( DDR_REG_BASE +0x50e1f*4+0x02000000,0x1023); +reg_write( DDR_REG_BASE +0x50e20*4+0x02000000,0x78af); +reg_write( DDR_REG_BASE +0x50e21*4+0x02000000,0xd92); +reg_write( DDR_REG_BASE +0x50e22*4+0x02000000,0x180); +reg_write( DDR_REG_BASE +0x50e23*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x50e24*4+0x02000000,0xb76); +reg_write( DDR_REG_BASE +0x50e25*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50e26*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x50e27*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50e28*4+0x02000000,0x85a); +reg_write( DDR_REG_BASE +0x50e29*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x50e2a*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x50e2b*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50e2c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50e2d*4+0x02000000,0x7b4); +reg_write( DDR_REG_BASE +0x50e2e*4+0x02000000,0x8841); +reg_write( DDR_REG_BASE +0x50e2f*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50e30*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x50e31*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50e32*4+0x02000000,0x7b4); +reg_write( DDR_REG_BASE +0x50e33*4+0x02000000,0x716d); +reg_write( DDR_REG_BASE +0x50e34*4+0x02000000,0xf01a); +reg_write( DDR_REG_BASE +0x50e35*4+0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x50e36*4+0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x50e37*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50e38*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x50e39*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50e3a*4+0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x50e3b*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x50e3c*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x50e3d*4+0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x50e3e*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x50e3f*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50e40*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x50e41*4+0x02000000,0x166); +reg_write( DDR_REG_BASE +0x50e42*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x50e43*4+0x02000000,0x631b); +reg_write( DDR_REG_BASE +0x50e44*4+0x02000000,0x200a); +reg_write( DDR_REG_BASE +0x50e45*4+0x02000000,0x780); +reg_write( DDR_REG_BASE +0x50e46*4+0x02000000,0x8eb); +reg_write( DDR_REG_BASE +0x50e47*4+0x02000000,0x8234); +reg_write( DDR_REG_BASE +0x50e48*4+0x02000000,0x2040); +reg_write( DDR_REG_BASE +0x50e49*4+0x02000000,0x5e); +reg_write( DDR_REG_BASE +0x50e4a*4+0x02000000,0x7074); +reg_write( DDR_REG_BASE +0x50e4b*4+0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x50e4c*4+0x02000000,0x1021); +reg_write( DDR_REG_BASE +0x50e4d*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x50e4e*4+0x02000000,0xacf); +reg_write( DDR_REG_BASE +0x50e4f*4+0x02000000,0x8065); +reg_write( DDR_REG_BASE +0x50e50*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50e51*4+0x02000000,0xb9b); +reg_write( DDR_REG_BASE +0x50e52*4+0x02000000,0x9030); +reg_write( DDR_REG_BASE +0x50e53*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x50e54*4+0x02000000,0xb0b); +reg_write( DDR_REG_BASE +0x50e55*4+0x02000000,0x3030); +reg_write( DDR_REG_BASE +0x50e56*4+0x02000000,0x8e58); +reg_write( DDR_REG_BASE +0x50e57*4+0x02000000,0x8602); +reg_write( DDR_REG_BASE +0x50e58*4+0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x50e59*4+0x02000000,0x8601); +reg_write( DDR_REG_BASE +0x50e5a*4+0x02000000,0xa4e); +reg_write( DDR_REG_BASE +0x50e5b*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50e5c*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x50e5d*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x50e5e*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x50e5f*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x50e60*4+0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x50e61*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x50e62*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x50e63*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x50e64*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x50e65*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x50e66*4+0x02000000,0xe064); +reg_write( DDR_REG_BASE +0x50e67*4+0x02000000,0x2145); +reg_write( DDR_REG_BASE +0x50e68*4+0x02000000,0x7c1); +reg_write( DDR_REG_BASE +0x50e69*4+0x02000000,0x149); +reg_write( DDR_REG_BASE +0x50e6a*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x50e6b*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x50e6c*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x50e6d*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50e6e*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x50e6f*4+0x02000000,0xb260); +reg_write( DDR_REG_BASE +0x50e70*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x50e71*4+0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x50e72*4+0x02000000,0x8cb4); +reg_write( DDR_REG_BASE +0x50e73*4+0x02000000,0x2014); +reg_write( DDR_REG_BASE +0x50e74*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50e75*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50e76*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x50e77*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50e78*4+0x02000000,0x16); +reg_write( DDR_REG_BASE +0x50e79*4+0x02000000,0x9f3); +reg_write( DDR_REG_BASE +0x50e7a*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x50e7b*4+0x02000000,0xda31); +reg_write( DDR_REG_BASE +0x50e7c*4+0x02000000,0xba9f); +reg_write( DDR_REG_BASE +0x50e7d*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50e7e*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50e7f*4+0x02000000,0xa821); +reg_write( DDR_REG_BASE +0x50e80*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50e81*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50e82*4+0x02000000,0xa822); +reg_write( DDR_REG_BASE +0x50e83*4+0x02000000,0x1202); +reg_write( DDR_REG_BASE +0x50e84*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50e85*4+0x02000000,0xa823); +reg_write( DDR_REG_BASE +0x50e86*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50e87*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50e88*4+0x02000000,0xa82b); +reg_write( DDR_REG_BASE +0x50e89*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50e8a*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50e8b*4+0x02000000,0xa830); +reg_write( DDR_REG_BASE +0x50e8c*4+0x02000000,0x1202); +reg_write( DDR_REG_BASE +0x50e8d*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50e8e*4+0x02000000,0xa831); +reg_write( DDR_REG_BASE +0x50e8f*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50e90*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50e91*4+0x02000000,0x1833); +reg_write( DDR_REG_BASE +0x50e92*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50e93*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50e94*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50e95*4+0x02000000,0x1834); +reg_write( DDR_REG_BASE +0x50e96*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50e97*4+0x02000000,0x1202); +reg_write( DDR_REG_BASE +0x50e98*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50e99*4+0x02000000,0x1835); +reg_write( DDR_REG_BASE +0x50e9a*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50e9b*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50e9c*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50e9d*4+0x02000000,0x183d); +reg_write( DDR_REG_BASE +0x50e9e*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50e9f*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50ea0*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50ea1*4+0x02000000,0x1842); +reg_write( DDR_REG_BASE +0x50ea2*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50ea3*4+0x02000000,0x1218); +reg_write( DDR_REG_BASE +0x50ea4*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50ea5*4+0x02000000,0x1843); +reg_write( DDR_REG_BASE +0x50ea6*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50ea7*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50ea8*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50ea9*4+0x02000000,0x1865); +reg_write( DDR_REG_BASE +0x50eaa*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50eab*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50eac*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50ead*4+0x02000000,0x1866); +reg_write( DDR_REG_BASE +0x50eae*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50eaf*4+0x02000000,0x1202); +reg_write( DDR_REG_BASE +0x50eb0*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50eb1*4+0x02000000,0x1867); +reg_write( DDR_REG_BASE +0x50eb2*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50eb3*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50eb4*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50eb5*4+0x02000000,0x186f); +reg_write( DDR_REG_BASE +0x50eb6*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50eb7*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50eb8*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50eb9*4+0x02000000,0x1874); +reg_write( DDR_REG_BASE +0x50eba*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50ebb*4+0x02000000,0x1202); +reg_write( DDR_REG_BASE +0x50ebc*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50ebd*4+0x02000000,0x1875); +reg_write( DDR_REG_BASE +0x50ebe*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50ebf*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50ec0*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50ec1*4+0x02000000,0x1897); +reg_write( DDR_REG_BASE +0x50ec2*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50ec3*4+0x02000000,0x1201); +reg_write( DDR_REG_BASE +0x50ec4*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50ec5*4+0x02000000,0x1898); +reg_write( DDR_REG_BASE +0x50ec6*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50ec7*4+0x02000000,0x1202); +reg_write( DDR_REG_BASE +0x50ec8*4+0x02000000,0x481); +reg_write( DDR_REG_BASE +0x50ec9*4+0x02000000,0x1899); +reg_write( DDR_REG_BASE +0x50eca*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50ecb*4+0x02000000,0x8a20); +reg_write( DDR_REG_BASE +0x50ecc*4+0x02000000,0x18a1); +reg_write( DDR_REG_BASE +0x50ecd*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50ece*4+0x02000000,0x8a21); +reg_write( DDR_REG_BASE +0x50ecf*4+0x02000000,0x18a6); +reg_write( DDR_REG_BASE +0x50ed0*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50ed1*4+0x02000000,0x8a22); +reg_write( DDR_REG_BASE +0x50ed2*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x50ed3*4+0x02000000,0x18a7); +reg_write( DDR_REG_BASE +0x50ed4*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x50ed5*4+0x02000000,0x219a); +reg_write( DDR_REG_BASE +0x50ed6*4+0x02000000,0x901); +reg_write( DDR_REG_BASE +0x50ed7*4+0x02000000,0x603a); +reg_write( DDR_REG_BASE +0x50ed8*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x50ed9*4+0x02000000,0x1c81); +reg_write( DDR_REG_BASE +0x50eda*4+0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x50edb*4+0x02000000,0x623c); +reg_write( DDR_REG_BASE +0x50edc*4+0x02000000,0xd931); +reg_write( DDR_REG_BASE +0x50edd*4+0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x50ede*4+0x02000000,0x1101); +reg_write( DDR_REG_BASE +0x50edf*4+0x02000000,0x482); +reg_write( DDR_REG_BASE +0x50ee0*4+0x02000000,0xac41); +reg_write( DDR_REG_BASE +0x50ee1*4+0x02000000,0x1101); +reg_write( DDR_REG_BASE +0x50ee2*4+0x02000000,0x482); +reg_write( DDR_REG_BASE +0x50ee3*4+0x02000000,0xac42); +reg_write( DDR_REG_BASE +0x50ee4*4+0x02000000,0x1102); +reg_write( DDR_REG_BASE +0x50ee5*4+0x02000000,0x482); +reg_write( DDR_REG_BASE +0x50ee6*4+0x02000000,0xac43); +reg_write( DDR_REG_BASE +0x50ee7*4+0x02000000,0x8940); +reg_write( DDR_REG_BASE +0x50ee8*4+0x02000000,0xac4b); +reg_write( DDR_REG_BASE +0x50ee9*4+0x02000000,0x8941); +reg_write( DDR_REG_BASE +0x50eea*4+0x02000000,0xac50); +reg_write( DDR_REG_BASE +0x50eeb*4+0x02000000,0x8922); +reg_write( DDR_REG_BASE +0x50eec*4+0x02000000,0xac31); +reg_write( DDR_REG_BASE +0x50eed*4+0x02000000,0xbd3); +reg_write( DDR_REG_BASE +0x50eee*4+0x02000000,0x90b4); +reg_write( DDR_REG_BASE +0x50eef*4+0x02000000,0x4160); +reg_write( DDR_REG_BASE +0x50ef0*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x50ef1*4+0x02000000,0xbfb); +reg_write( DDR_REG_BASE +0x50ef2*4+0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x50ef3*4+0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x50ef4*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50ef5*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x50ef6*4+0x02000000,0xc3e4); +reg_write( DDR_REG_BASE +0x50ef7*4+0x02000000,0xc1ab); +reg_write( DDR_REG_BASE +0x50ef8*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x50ef9*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50efa*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50efb*4+0x02000000,0x689); +reg_write( DDR_REG_BASE +0x50efc*4+0x02000000,0xa8a); +reg_write( DDR_REG_BASE +0x50efd*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x50efe*4+0x02000000,0xda2a); +reg_write( DDR_REG_BASE +0x50eff*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x50f00*4+0x02000000,0xb8a); +reg_write( DDR_REG_BASE +0x50f01*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x50f02*4+0x02000000,0xd92a); +reg_write( DDR_REG_BASE +0x50f03*4+0x02000000,0xc16); +reg_write( DDR_REG_BASE +0x50f04*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x50f05*4+0x02000000,0xc72); +reg_write( DDR_REG_BASE +0x50f06*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50f07*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x50f08*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x50f09*4+0x02000000,0xc52); +reg_write( DDR_REG_BASE +0x50f0a*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50f0b*4+0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x50f0c*4+0x02000000,0xdd23); +reg_write( DDR_REG_BASE +0x50f0d*4+0x02000000,0xbd9f); +reg_write( DDR_REG_BASE +0x50f0e*4+0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x50f0f*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50f10*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50f11*4+0x02000000,0xe4); +reg_write( DDR_REG_BASE +0x50f12*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x50f13*4+0x02000000,0x1526); +reg_write( DDR_REG_BASE +0x50f14*4+0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x50f15*4+0x02000000,0xb601); +reg_write( DDR_REG_BASE +0x50f16*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50f17*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x50f18*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x50f19*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x50f1a*4+0x02000000,0xe154); +reg_write( DDR_REG_BASE +0x50f1b*4+0x02000000,0xb56); +reg_write( DDR_REG_BASE +0x50f1c*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x50f1d*4+0x02000000,0x1e42); +reg_write( DDR_REG_BASE +0x50f1e*4+0x02000000,0x905d); +reg_write( DDR_REG_BASE +0x50f1f*4+0x02000000,0x2053); +reg_write( DDR_REG_BASE +0x50f20*4+0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x50f21*4+0x02000000,0x1a01); +reg_write( DDR_REG_BASE +0x50f22*4+0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x50f23*4+0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x50f24*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50f25*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50f26*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x50f27*4+0x02000000,0xb9c3); +reg_write( DDR_REG_BASE +0x50f28*4+0x02000000,0x1a02); +reg_write( DDR_REG_BASE +0x50f29*4+0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x50f2a*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x50f2b*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x50f2c*4+0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x50f2d*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x50f2e*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50f2f*4+0x02000000,0xb8c1); +reg_write( DDR_REG_BASE +0x50f30*4+0x02000000,0xef6); +reg_write( DDR_REG_BASE +0x50f31*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x50f32*4+0x02000000,0x1a06); +reg_write( DDR_REG_BASE +0x50f33*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x50f34*4+0x02000000,0x83a); +reg_write( DDR_REG_BASE +0x50f35*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50f36*4+0x02000000,0xb72); +reg_write( DDR_REG_BASE +0x50f37*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x50f38*4+0x02000000,0x164c); +reg_write( DDR_REG_BASE +0x50f39*4+0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x50f3a*4+0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x50f3b*4+0x02000000,0x151); +reg_write( DDR_REG_BASE +0x50f3c*4+0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x50f3d*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x50f3e*4+0x02000000,0xb601); +reg_write( DDR_REG_BASE +0x50f3f*4+0x02000000,0xc7c4); +reg_write( DDR_REG_BASE +0x50f40*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x50f41*4+0x02000000,0xc1bd); +reg_write( DDR_REG_BASE +0x50f42*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x50f43*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x50f44*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50f45*4+0x02000000,0x50a); +reg_write( DDR_REG_BASE +0x50f46*4+0x02000000,0x9f6); +reg_write( DDR_REG_BASE +0x50f47*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x50f48*4+0x02000000,0xda72); +reg_write( DDR_REG_BASE +0x50f49*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x50f4a*4+0x02000000,0xaf6); +reg_write( DDR_REG_BASE +0x50f4b*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x50f4c*4+0x02000000,0xd972); +reg_write( DDR_REG_BASE +0x50f4d*4+0x02000000,0xc0bd); +reg_write( DDR_REG_BASE +0x50f4e*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x50f4f*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x50f50*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x50f51*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x50f52*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x50f53*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50f54*4+0x02000000,0x7101); +reg_write( DDR_REG_BASE +0x50f55*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50f56*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x50f57*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x50f58*4+0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x50f59*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x50f5a*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x50f5b*4+0x02000000,0x225f); +reg_write( DDR_REG_BASE +0x50f5c*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x50f5d*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x50f5e*4+0x02000000,0x7c3); +reg_write( DDR_REG_BASE +0x50f5f*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x50f60*4+0x02000000,0xeb05); +reg_write( DDR_REG_BASE +0x50f61*4+0x02000000,0xbb61); +reg_write( DDR_REG_BASE +0x50f62*4+0x02000000,0xbff); +reg_write( DDR_REG_BASE +0x50f63*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x50f64*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x50f65*4+0x02000000,0xb8c3); +reg_write( DDR_REG_BASE +0x50f66*4+0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x50f67*4+0x02000000,0x190); +reg_write( DDR_REG_BASE +0x50f68*4+0x02000000,0x877); +reg_write( DDR_REG_BASE +0x50f69*4+0x02000000,0x71); +reg_write( DDR_REG_BASE +0x50f6a*4+0x02000000,0xdf18); +reg_write( DDR_REG_BASE +0x50f6b*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x50f6c*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50f6d*4+0x02000000,0x116); +reg_write( DDR_REG_BASE +0x50f6e*4+0x02000000,0x1e08); +reg_write( DDR_REG_BASE +0x50f6f*4+0x02000000,0x1094); +reg_write( DDR_REG_BASE +0x50f70*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x50f71*4+0x02000000,0x1e02); +reg_write( DDR_REG_BASE +0x50f72*4+0x02000000,0x1055); +reg_write( DDR_REG_BASE +0x50f73*4+0x02000000,0xd829); +reg_write( DDR_REG_BASE +0x50f74*4+0x02000000,0xb6a0); +reg_write( DDR_REG_BASE +0x50f75*4+0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x50f76*4+0x02000000,0x1205); +reg_write( DDR_REG_BASE +0x50f77*4+0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x50f78*4+0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x50f79*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50f7a*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50f7b*4+0x02000000,0x98); +reg_write( DDR_REG_BASE +0x50f7c*4+0x02000000,0x9680); +reg_write( DDR_REG_BASE +0x50f7d*4+0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x50f7e*4+0x02000000,0x1ef2); +reg_write( DDR_REG_BASE +0x50f7f*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x50f80*4+0x02000000,0xfba); +reg_write( DDR_REG_BASE +0x50f81*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50f82*4+0x02000000,0x1e66); +reg_write( DDR_REG_BASE +0x50f83*4+0x02000000,0x1044); +reg_write( DDR_REG_BASE +0x50f84*4+0x02000000,0xd8a9); +reg_write( DDR_REG_BASE +0x50f85*4+0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x50f86*4+0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x50f87*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x50f88*4+0x02000000,0xa46); +reg_write( DDR_REG_BASE +0x50f89*4+0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x50f8a*4+0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x50f8b*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x50f8c*4+0x02000000,0xa44); +reg_write( DDR_REG_BASE +0x50f8d*4+0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x50f8e*4+0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x50f8f*4+0x02000000,0x1e6c); +reg_write( DDR_REG_BASE +0x50f90*4+0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x50f91*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50f92*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50f93*4+0x02000000,0x6000); +reg_write( DDR_REG_BASE +0x50f94*4+0x02000000,0x1e72); +reg_write( DDR_REG_BASE +0x50f95*4+0x02000000,0x935c); +reg_write( DDR_REG_BASE +0x50f96*4+0x02000000,0x1ed0); +reg_write( DDR_REG_BASE +0x50f97*4+0x02000000,0x9344); +reg_write( DDR_REG_BASE +0x50f98*4+0x02000000,0x1e72); +reg_write( DDR_REG_BASE +0x50f99*4+0x02000000,0x90dd); +reg_write( DDR_REG_BASE +0x50f9a*4+0x02000000,0xf2e); +reg_write( DDR_REG_BASE +0x50f9b*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50f9c*4+0x02000000,0x1ed0); +reg_write( DDR_REG_BASE +0x50f9d*4+0x02000000,0x92c4); +reg_write( DDR_REG_BASE +0x50f9e*4+0x02000000,0x1e72); +reg_write( DDR_REG_BASE +0x50f9f*4+0x02000000,0x935c); +reg_write( DDR_REG_BASE +0x50fa0*4+0x02000000,0x1e72); +reg_write( DDR_REG_BASE +0x50fa1*4+0x02000000,0x92dc); +reg_write( DDR_REG_BASE +0x50fa2*4+0x02000000,0xf046); +reg_write( DDR_REG_BASE +0x50fa3*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x50fa4*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50fa5*4+0x02000000,0x116); +reg_write( DDR_REG_BASE +0x50fa6*4+0x02000000,0x1d08); +reg_write( DDR_REG_BASE +0x50fa7*4+0x02000000,0x1094); +reg_write( DDR_REG_BASE +0x50fa8*4+0x02000000,0x71cd); +reg_write( DDR_REG_BASE +0x50fa9*4+0x02000000,0x1d02); +reg_write( DDR_REG_BASE +0x50faa*4+0x02000000,0x1055); +reg_write( DDR_REG_BASE +0x50fab*4+0x02000000,0x234a); +reg_write( DDR_REG_BASE +0x50fac*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x50fad*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50fae*4+0x02000000,0xbf8b); +reg_write( DDR_REG_BASE +0x50faf*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50fb0*4+0x02000000,0xf); +reg_write( DDR_REG_BASE +0x50fb1*4+0x02000000,0x4240); +reg_write( DDR_REG_BASE +0x50fb2*4+0x02000000,0xb5c0); +reg_write( DDR_REG_BASE +0x50fb3*4+0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x50fb4*4+0x02000000,0x12c4); +reg_write( DDR_REG_BASE +0x50fb5*4+0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x50fb6*4+0x02000000,0x3040); +reg_write( DDR_REG_BASE +0x50fb7*4+0x02000000,0x1df2); +reg_write( DDR_REG_BASE +0x50fb8*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x50fb9*4+0x02000000,0x1d66); +reg_write( DDR_REG_BASE +0x50fba*4+0x02000000,0x1044); +reg_write( DDR_REG_BASE +0x50fbb*4+0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x50fbc*4+0x02000000,0x13c4); +reg_write( DDR_REG_BASE +0x50fbd*4+0x02000000,0xf42); +reg_write( DDR_REG_BASE +0x50fbe*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50fbf*4+0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x50fc0*4+0x02000000,0xbf70); +reg_write( DDR_REG_BASE +0x50fc1*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x50fc2*4+0x02000000,0x6c2); +reg_write( DDR_REG_BASE +0x50fc3*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50fc4*4+0x02000000,0xf32); +reg_write( DDR_REG_BASE +0x50fc5*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50fc6*4+0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x50fc7*4+0x02000000,0x13c4); +reg_write( DDR_REG_BASE +0x50fc8*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50fc9*4+0x02000000,0x98); +reg_write( DDR_REG_BASE +0x50fca*4+0x02000000,0x9680); +reg_write( DDR_REG_BASE +0x50fcb*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x50fcc*4+0x02000000,0xf22); +reg_write( DDR_REG_BASE +0x50fcd*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50fce*4+0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x50fcf*4+0x02000000,0x12c4); +reg_write( DDR_REG_BASE +0x50fd0*4+0x02000000,0xd888); +reg_write( DDR_REG_BASE +0x50fd1*4+0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x50fd2*4+0x02000000,0x1004); +reg_write( DDR_REG_BASE +0x50fd3*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x50fd4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x50fd5*4+0x02000000,0x6000); +reg_write( DDR_REG_BASE +0x50fd6*4+0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x50fd7*4+0x02000000,0x12c4); +reg_write( DDR_REG_BASE +0x50fd8*4+0x02000000,0x1d6c); +reg_write( DDR_REG_BASE +0x50fd9*4+0x02000000,0x1784); +reg_write( DDR_REG_BASE +0x50fda*4+0x02000000,0x1d72); +reg_write( DDR_REG_BASE +0x50fdb*4+0x02000000,0x939c); +reg_write( DDR_REG_BASE +0x50fdc*4+0x02000000,0x1dd0); +reg_write( DDR_REG_BASE +0x50fdd*4+0x02000000,0x9384); +reg_write( DDR_REG_BASE +0x50fde*4+0x02000000,0x1d72); +reg_write( DDR_REG_BASE +0x50fdf*4+0x02000000,0x90dd); +reg_write( DDR_REG_BASE +0x50fe0*4+0x02000000,0xea2); +reg_write( DDR_REG_BASE +0x50fe1*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50fe2*4+0x02000000,0x1dd0); +reg_write( DDR_REG_BASE +0x50fe3*4+0x02000000,0x9784); +reg_write( DDR_REG_BASE +0x50fe4*4+0x02000000,0x1d72); +reg_write( DDR_REG_BASE +0x50fe5*4+0x02000000,0x939c); +reg_write( DDR_REG_BASE +0x50fe6*4+0x02000000,0x1d72); +reg_write( DDR_REG_BASE +0x50fe7*4+0x02000000,0x979c); +reg_write( DDR_REG_BASE +0x50fe8*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x50fe9*4+0x02000000,0xeea); +reg_write( DDR_REG_BASE +0x50fea*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50feb*4+0x02000000,0xd920); +reg_write( DDR_REG_BASE +0x50fec*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x50fed*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x50fee*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x50fef*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x50ff0*4+0x02000000,0xe82); +reg_write( DDR_REG_BASE +0x50ff1*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50ff2*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50ff3*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x50ff4*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x50ff5*4+0x02000000,0xe7a); +reg_write( DDR_REG_BASE +0x50ff6*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50ff7*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50ff8*4+0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x50ff9*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x50ffa*4+0x02000000,0xe6e); +reg_write( DDR_REG_BASE +0x50ffb*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x50ffc*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x50ffd*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x50ffe*4+0x02000000,0x1d0a); +reg_write( DDR_REG_BASE +0x50fff*4+0x02000000,0x909d); +reg_write( DDR_REG_BASE +0x51000*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x51001*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x51002*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51003*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51004*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51005*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51006*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51007*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51008*4+0x02000000,0x7b6); +reg_write( DDR_REG_BASE +0x51009*4+0x02000000,0xdc22); +reg_write( DDR_REG_BASE +0x5100a*4+0x02000000,0xa940); +reg_write( DDR_REG_BASE +0x5100b*4+0x02000000,0xbc9f); +reg_write( DDR_REG_BASE +0x5100c*4+0x02000000,0x8c00); +reg_write( DDR_REG_BASE +0x5100d*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x5100e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5100f*4+0x02000000,0x758); +reg_write( DDR_REG_BASE +0x51010*4+0x02000000,0xe007); +reg_write( DDR_REG_BASE +0x51011*4+0x02000000,0x7e1d); +reg_write( DDR_REG_BASE +0x51012*4+0x02000000,0x7edd); +reg_write( DDR_REG_BASE +0x51013*4+0x02000000,0x7edd); +reg_write( DDR_REG_BASE +0x51014*4+0x02000000,0x6e09); +reg_write( DDR_REG_BASE +0x51015*4+0x02000000,0xa901); +reg_write( DDR_REG_BASE +0x51016*4+0x02000000,0x1427); +reg_write( DDR_REG_BASE +0x51017*4+0x02000000,0x1083); +reg_write( DDR_REG_BASE +0x51018*4+0x02000000,0x7074); +reg_write( DDR_REG_BASE +0x51019*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x5101a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5101b*4+0x02000000,0x77c); +reg_write( DDR_REG_BASE +0x5101c*4+0x02000000,0xf223); +reg_write( DDR_REG_BASE +0x5101d*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x5101e*4+0x02000000,0x44); +reg_write( DDR_REG_BASE +0x5101f*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51020*4+0x02000000,0x708f); +reg_write( DDR_REG_BASE +0x51021*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51022*4+0x02000000,0x48); +reg_write( DDR_REG_BASE +0x51023*4+0x02000000,0xb501); +reg_write( DDR_REG_BASE +0x51024*4+0x02000000,0xca02); +reg_write( DDR_REG_BASE +0x51025*4+0x02000000,0x7e1d); +reg_write( DDR_REG_BASE +0x51026*4+0x02000000,0x6f07); +reg_write( DDR_REG_BASE +0x51027*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51028*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51029*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5102a*4+0x02000000,0x60d8); +reg_write( DDR_REG_BASE +0x5102b*4+0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x5102c*4+0x02000000,0xa9c2); +reg_write( DDR_REG_BASE +0x5102d*4+0x02000000,0xa903); +reg_write( DDR_REG_BASE +0x5102e*4+0x02000000,0x8c00); +reg_write( DDR_REG_BASE +0x5102f*4+0x02000000,0x82b); +reg_write( DDR_REG_BASE +0x51030*4+0x02000000,0x474); +reg_write( DDR_REG_BASE +0x51031*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x51032*4+0x02000000,0xd06); +reg_write( DDR_REG_BASE +0x51033*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x51034*4+0x02000000,0xad14); +reg_write( DDR_REG_BASE +0x51035*4+0x02000000,0xd02); +reg_write( DDR_REG_BASE +0x51036*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51037*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x51038*4+0x02000000,0xad1c); +reg_write( DDR_REG_BASE +0x51039*4+0x02000000,0xcfa); +reg_write( DDR_REG_BASE +0x5103a*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x5103b*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x5103c*4+0x02000000,0xab10); +reg_write( DDR_REG_BASE +0x5103d*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x5103e*4+0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x5103f*4+0x02000000,0xa903); +reg_write( DDR_REG_BASE +0x51040*4+0x02000000,0xa9c2); +reg_write( DDR_REG_BASE +0x51041*4+0x02000000,0xb541); +reg_write( DDR_REG_BASE +0x51042*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x51043*4+0x02000000,0xce6); +reg_write( DDR_REG_BASE +0x51044*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51045*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x51046*4+0x02000000,0xad14); +reg_write( DDR_REG_BASE +0x51047*4+0x02000000,0xcde); +reg_write( DDR_REG_BASE +0x51048*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51049*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x5104a*4+0x02000000,0xad1c); +reg_write( DDR_REG_BASE +0x5104b*4+0x02000000,0xcd6); +reg_write( DDR_REG_BASE +0x5104c*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x5104d*4+0x02000000,0x720c); +reg_write( DDR_REG_BASE +0x5104e*4+0x02000000,0xab10); +reg_write( DDR_REG_BASE +0x5104f*4+0x02000000,0x720c); +reg_write( DDR_REG_BASE +0x51050*4+0x02000000,0xcca); +reg_write( DDR_REG_BASE +0x51051*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x51052*4+0x02000000,0xab18); +reg_write( DDR_REG_BASE +0x51053*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51054*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51055*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51056*4+0x02000000,0x23); +reg_write( DDR_REG_BASE +0x51057*4+0x02000000,0xe816); +reg_write( DDR_REG_BASE +0x51058*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x51059*4+0x02000000,0x44); +reg_write( DDR_REG_BASE +0x5105a*4+0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x5105b*4+0x02000000,0xcb6); +reg_write( DDR_REG_BASE +0x5105c*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x5105d*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5105e*4+0x02000000,0xad04); +reg_write( DDR_REG_BASE +0x5105f*4+0x02000000,0xcae); +reg_write( DDR_REG_BASE +0x51060*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51061*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51062*4+0x02000000,0xad0c); +reg_write( DDR_REG_BASE +0x51063*4+0x02000000,0xca6); +reg_write( DDR_REG_BASE +0x51064*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51065*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51066*4+0x02000000,0xab00); +reg_write( DDR_REG_BASE +0x51067*4+0x02000000,0xc9e); +reg_write( DDR_REG_BASE +0x51068*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x51069*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5106a*4+0x02000000,0xab08); +reg_write( DDR_REG_BASE +0x5106b*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5106c*4+0x02000000,0xb540); +reg_write( DDR_REG_BASE +0x5106d*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5106e*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x5106f*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51070*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x51071*4+0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x51072*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x51073*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51074*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51075*4+0x02000000,0x7b0); +reg_write( DDR_REG_BASE +0x51076*4+0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x51077*4+0x02000000,0xea06); +reg_write( DDR_REG_BASE +0x51078*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x51079*4+0x02000000,0xa01); +reg_write( DDR_REG_BASE +0x5107a*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x5107b*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5107c*4+0x02000000,0x917); +reg_write( DDR_REG_BASE +0x5107d*4+0x02000000,0x70); +reg_write( DDR_REG_BASE +0x5107e*4+0x02000000,0x72ad); +reg_write( DDR_REG_BASE +0x5107f*4+0x02000000,0x73ad); +reg_write( DDR_REG_BASE +0x51080*4+0x02000000,0xe98e); +reg_write( DDR_REG_BASE +0x51081*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51082*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51083*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51084*4+0x02000000,0x23); +reg_write( DDR_REG_BASE +0x51085*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x51086*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x51087*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51088*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51089*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5108a*4+0x02000000,0x49); +reg_write( DDR_REG_BASE +0x5108b*4+0x02000000,0x782b); +reg_write( DDR_REG_BASE +0x5108c*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5108d*4+0x02000000,0xf20a); +reg_write( DDR_REG_BASE +0x5108e*4+0x02000000,0xf12); +reg_write( DDR_REG_BASE +0x5108f*4+0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x51090*4+0x02000000,0xafa); +reg_write( DDR_REG_BASE +0x51091*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x51092*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x51093*4+0x02000000,0xe5a); +reg_write( DDR_REG_BASE +0x51094*4+0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x51095*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51096*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x51097*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51098*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x51099*4+0x02000000,0xf72); +reg_write( DDR_REG_BASE +0x5109a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5109b*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x5109c*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x5109d*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5109e*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5109f*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x510a0*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x510a1*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x510a2*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x510a3*4+0x02000000,0x1e8); +reg_write( DDR_REG_BASE +0x510a4*4+0x02000000,0x9020); +reg_write( DDR_REG_BASE +0x510a5*4+0x02000000,0x2059); +reg_write( DDR_REG_BASE +0x510a6*4+0x02000000,0xf40); +reg_write( DDR_REG_BASE +0x510a7*4+0x02000000,0x7724); +reg_write( DDR_REG_BASE +0x510a8*4+0x02000000,0x7930); +reg_write( DDR_REG_BASE +0x510a9*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x510aa*4+0x02000000,0x2155); +reg_write( DDR_REG_BASE +0x510ab*4+0x02000000,0xc0d); +reg_write( DDR_REG_BASE +0x510ac*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x510ad*4+0x02000000,0xe); +reg_write( DDR_REG_BASE +0x510ae*4+0x02000000,0x7d05); +reg_write( DDR_REG_BASE +0x510af*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x510b0*4+0x02000000,0x111b); +reg_write( DDR_REG_BASE +0x510b1*4+0x02000000,0x95e0); +reg_write( DDR_REG_BASE +0x510b2*4+0x02000000,0x83a); +reg_write( DDR_REG_BASE +0x510b3*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x510b4*4+0x02000000,0xd896); +reg_write( DDR_REG_BASE +0x510b5*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x510b6*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x510b7*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x510b8*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x510b9*4+0x02000000,0x6822); +reg_write( DDR_REG_BASE +0x510ba*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x510bb*4+0x02000000,0xb8e0); +reg_write( DDR_REG_BASE +0x510bc*4+0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x510bd*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x510be*4+0x02000000,0x782f); +reg_write( DDR_REG_BASE +0x510bf*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x510c0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x510c1*4+0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x510c2*4+0x02000000,0x2304); +reg_write( DDR_REG_BASE +0x510c3*4+0x02000000,0x305b); +reg_write( DDR_REG_BASE +0x510c4*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x510c5*4+0x02000000,0x6c0); +reg_write( DDR_REG_BASE +0x510c6*4+0x02000000,0x79e4); +reg_write( DDR_REG_BASE +0x510c7*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x510c8*4+0x02000000,0x2145); +reg_write( DDR_REG_BASE +0x510c9*4+0x02000000,0x3c0); +reg_write( DDR_REG_BASE +0x510ca*4+0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x510cb*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x510cc*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x510cd*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x510ce*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x510cf*4+0x02000000,0x7101); +reg_write( DDR_REG_BASE +0x510d0*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x510d1*4+0x02000000,0x6); +reg_write( DDR_REG_BASE +0x510d2*4+0x02000000,0x790c); +reg_write( DDR_REG_BASE +0x510d3*4+0x02000000,0x2985); +reg_write( DDR_REG_BASE +0x510d4*4+0x02000000,0x41f); +reg_write( DDR_REG_BASE +0x510d5*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x510d6*4+0x02000000,0x6901); +reg_write( DDR_REG_BASE +0x510d7*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x510d8*4+0x02000000,0x2042); +reg_write( DDR_REG_BASE +0x510d9*4+0x02000000,0x701); +reg_write( DDR_REG_BASE +0x510da*4+0x02000000,0x939); +reg_write( DDR_REG_BASE +0x510db*4+0x02000000,0x454); +reg_write( DDR_REG_BASE +0x510dc*4+0x02000000,0x889); +reg_write( DDR_REG_BASE +0x510dd*4+0x02000000,0xc30); +reg_write( DDR_REG_BASE +0x510de*4+0x02000000,0xd91a); +reg_write( DDR_REG_BASE +0x510df*4+0x02000000,0x885); +reg_write( DDR_REG_BASE +0x510e0*4+0x02000000,0xd70); +reg_write( DDR_REG_BASE +0x510e1*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x510e2*4+0x02000000,0x87d); +reg_write( DDR_REG_BASE +0x510e3*4+0x02000000,0xf30); +reg_write( DDR_REG_BASE +0x510e4*4+0x02000000,0xd918); +reg_write( DDR_REG_BASE +0x510e5*4+0x02000000,0xe0c5); +reg_write( DDR_REG_BASE +0x510e6*4+0x02000000,0xf227); +reg_write( DDR_REG_BASE +0x510e7*4+0x02000000,0xe0d0); +reg_write( DDR_REG_BASE +0x510e8*4+0x02000000,0xf227); +reg_write( DDR_REG_BASE +0x510e9*4+0x02000000,0xe0e0); +reg_write( DDR_REG_BASE +0x510ea*4+0x02000000,0xf227); +reg_write( DDR_REG_BASE +0x510eb*4+0x02000000,0xe0f8); +reg_write( DDR_REG_BASE +0x510ec*4+0x02000000,0xf227); +reg_write( DDR_REG_BASE +0x510ed*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x510ee*4+0x02000000,0x8c03); +reg_write( DDR_REG_BASE +0x510ef*4+0x02000000,0x722c); +reg_write( DDR_REG_BASE +0x510f0*4+0x02000000,0xf230); +reg_write( DDR_REG_BASE +0x510f1*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x510f2*4+0x02000000,0x8802); +reg_write( DDR_REG_BASE +0x510f3*4+0x02000000,0xf419); +reg_write( DDR_REG_BASE +0x510f4*4+0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x510f5*4+0x02000000,0xf02c); +reg_write( DDR_REG_BASE +0x510f6*4+0x02000000,0x2025); +reg_write( DDR_REG_BASE +0x510f7*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x510f8*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x510f9*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x510fa*4+0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x510fb*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x510fc*4+0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x510fd*4+0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x510fe*4+0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x510ff*4+0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x51100*4+0x02000000,0xf00b); +reg_write( DDR_REG_BASE +0x51101*4+0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x51102*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x51103*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x51104*4+0x02000000,0xf019); +reg_write( DDR_REG_BASE +0x51105*4+0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x51106*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x51107*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x51108*4+0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x51109*4+0x02000000,0xd93f); +reg_write( DDR_REG_BASE +0x5110a*4+0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x5110b*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5110c*4+0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x5110d*4+0x02000000,0xd90b); +reg_write( DDR_REG_BASE +0x5110e*4+0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x5110f*4+0x02000000,0xd90a); +reg_write( DDR_REG_BASE +0x51110*4+0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x51111*4+0x02000000,0xd907); +reg_write( DDR_REG_BASE +0x51112*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x51113*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x51114*4+0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x51115*4+0x02000000,0xd93e); +reg_write( DDR_REG_BASE +0x51116*4+0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x51117*4+0x02000000,0xd93b); +reg_write( DDR_REG_BASE +0x51118*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x51119*4+0x02000000,0xd93a); +reg_write( DDR_REG_BASE +0x5111a*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x5111b*4+0x02000000,0xd91f); +reg_write( DDR_REG_BASE +0x5111c*4+0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x5111d*4+0x02000000,0xd938); +reg_write( DDR_REG_BASE +0x5111e*4+0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x5111f*4+0x02000000,0xd91b); +reg_write( DDR_REG_BASE +0x51120*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x51121*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x51122*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51123*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51124*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51125*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x51126*4+0x02000000,0x330f); +reg_write( DDR_REG_BASE +0x51127*4+0x02000000,0xa8e); +reg_write( DDR_REG_BASE +0x51128*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51129*4+0x02000000,0xc083); +reg_write( DDR_REG_BASE +0x5112a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5112b*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5112c*4+0x02000000,0xc083); +reg_write( DDR_REG_BASE +0x5112d*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5112e*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x5112f*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51130*4+0x02000000,0x600); +reg_write( DDR_REG_BASE +0x51131*4+0x02000000,0xd92); +reg_write( DDR_REG_BASE +0x51132*4+0x02000000,0x1a0); +reg_write( DDR_REG_BASE +0x51133*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51134*4+0x02000000,0xc62); +reg_write( DDR_REG_BASE +0x51135*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51136*4+0x02000000,0xb2a); +reg_write( DDR_REG_BASE +0x51137*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x51138*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51139*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5113a*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x5113b*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5113c*4+0x02000000,0xdc); +reg_write( DDR_REG_BASE +0x5113d*4+0x02000000,0x315); +reg_write( DDR_REG_BASE +0x5113e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5113f*4+0x02000000,0xe90b); +reg_write( DDR_REG_BASE +0x51140*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51141*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51142*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51143*4+0x02000000,0x49); +reg_write( DDR_REG_BASE +0x51144*4+0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x51145*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51146*4+0x02000000,0xf40b); +reg_write( DDR_REG_BASE +0x51147*4+0x02000000,0x2ff); +reg_write( DDR_REG_BASE +0x51148*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51149*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5114a*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x5114b*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5114c*4+0x02000000,0x23); +reg_write( DDR_REG_BASE +0x5114d*4+0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x5114e*4+0x02000000,0x2ee); +reg_write( DDR_REG_BASE +0x5114f*4+0x02000000,0x21); +reg_write( DDR_REG_BASE +0x51150*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51151*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x51152*4+0x02000000,0x976); +reg_write( DDR_REG_BASE +0x51153*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x51154*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51155*4+0x02000000,0x216f); +reg_write( DDR_REG_BASE +0x51156*4+0x02000000,0xc3); +reg_write( DDR_REG_BASE +0x51157*4+0x02000000,0x1100); +reg_write( DDR_REG_BASE +0x51158*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x51159*4+0x02000000,0x89c3); +reg_write( DDR_REG_BASE +0x5115a*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5115b*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5115c*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x5115d*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x5115e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5115f*4+0x02000000,0x32c); +reg_write( DDR_REG_BASE +0x51160*4+0x02000000,0xdd2); +reg_write( DDR_REG_BASE +0x51161*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51162*4+0x02000000,0xdaa0); +reg_write( DDR_REG_BASE +0x51163*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51164*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x51165*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51166*4+0x02000000,0x28c); +reg_write( DDR_REG_BASE +0x51167*4+0x02000000,0xdc6); +reg_write( DDR_REG_BASE +0x51168*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51169*4+0x02000000,0xdaa0); +reg_write( DDR_REG_BASE +0x5116a*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x5116b*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x5116c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5116d*4+0x02000000,0x1ec); +reg_write( DDR_REG_BASE +0x5116e*4+0x02000000,0xdb6); +reg_write( DDR_REG_BASE +0x5116f*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51170*4+0x02000000,0xdaa0); +reg_write( DDR_REG_BASE +0x51171*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51172*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x51173*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51174*4+0x02000000,0x14c); +reg_write( DDR_REG_BASE +0x51175*4+0x02000000,0xdaa); +reg_write( DDR_REG_BASE +0x51176*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51177*4+0x02000000,0xdaa0); +reg_write( DDR_REG_BASE +0x51178*4+0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x51179*4+0x02000000,0x1f8e); +reg_write( DDR_REG_BASE +0x5117a*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5117b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5117c*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x5117d*4+0x02000000,0xf072); +reg_write( DDR_REG_BASE +0x5117e*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x5117f*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x51180*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51181*4+0x02000000,0x124); +reg_write( DDR_REG_BASE +0x51182*4+0x02000000,0xd8e); +reg_write( DDR_REG_BASE +0x51183*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51184*4+0x02000000,0xda28); +reg_write( DDR_REG_BASE +0x51185*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51186*4+0x02000000,0x3fc0); +reg_write( DDR_REG_BASE +0x51187*4+0x02000000,0xd86); +reg_write( DDR_REG_BASE +0x51188*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51189*4+0x02000000,0xda28); +reg_write( DDR_REG_BASE +0x5118a*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x5118b*4+0x02000000,0x3d40); +reg_write( DDR_REG_BASE +0x5118c*4+0x02000000,0xd7a); +reg_write( DDR_REG_BASE +0x5118d*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5118e*4+0x02000000,0xda28); +reg_write( DDR_REG_BASE +0x5118f*4+0x02000000,0x2355); +reg_write( DDR_REG_BASE +0x51190*4+0x02000000,0x3800); +reg_write( DDR_REG_BASE +0x51191*4+0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x51192*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51193*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x51194*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51195*4+0x02000000,0x124); +reg_write( DDR_REG_BASE +0x51196*4+0x02000000,0xb86); +reg_write( DDR_REG_BASE +0x51197*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x51198*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x51199*4+0x02000000,0x2355); +reg_write( DDR_REG_BASE +0x5119a*4+0x02000000,0x38c0); +reg_write( DDR_REG_BASE +0x5119b*4+0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x5119c*4+0x02000000,0xb7a); +reg_write( DDR_REG_BASE +0x5119d*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x5119e*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x5119f*4+0x02000000,0x3fc1); +reg_write( DDR_REG_BASE +0x511a0*4+0x02000000,0x2355); +reg_write( DDR_REG_BASE +0x511a1*4+0x02000000,0x3d00); +reg_write( DDR_REG_BASE +0x511a2*4+0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x511a3*4+0x02000000,0xb6e); +reg_write( DDR_REG_BASE +0x511a4*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x511a5*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x511a6*4+0x02000000,0x3d41); +reg_write( DDR_REG_BASE +0x511a7*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x511a8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x511a9*4+0x02000000,0x7b0); +reg_write( DDR_REG_BASE +0x511aa*4+0x02000000,0x1003); +reg_write( DDR_REG_BASE +0x511ab*4+0x02000000,0x8b); +reg_write( DDR_REG_BASE +0x511ac*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x511ad*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x511ae*4+0x02000000,0x7b0); +reg_write( DDR_REG_BASE +0x511af*4+0x02000000,0x8862); +reg_write( DDR_REG_BASE +0x511b0*4+0x02000000,0xf03b); +reg_write( DDR_REG_BASE +0x511b1*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x511b2*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x511b3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x511b4*4+0x02000000,0x124); +reg_write( DDR_REG_BASE +0x511b5*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x511b6*4+0x02000000,0xde); +reg_write( DDR_REG_BASE +0x511b7*4+0x02000000,0xd26); +reg_write( DDR_REG_BASE +0x511b8*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x511b9*4+0x02000000,0x200a); +reg_write( DDR_REG_BASE +0x511ba*4+0x02000000,0x780); +reg_write( DDR_REG_BASE +0x511bb*4+0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x511bc*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x511bd*4+0x02000000,0x3fc0); +reg_write( DDR_REG_BASE +0x511be*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x511bf*4+0x02000000,0xcd); +reg_write( DDR_REG_BASE +0x511c0*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x511c1*4+0x02000000,0x3d40); +reg_write( DDR_REG_BASE +0x511c2*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x511c3*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x511c4*4+0x02000000,0xbdc5); +reg_write( DDR_REG_BASE +0x511c5*4+0x02000000,0xd0a); +reg_write( DDR_REG_BASE +0x511c6*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x511c7*4+0x02000000,0x65fd); +reg_write( DDR_REG_BASE +0x511c8*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x511c9*4+0x02000000,0x3a02); +reg_write( DDR_REG_BASE +0x511ca*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x511cb*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x511cc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x511cd*4+0x02000000,0x32c); +reg_write( DDR_REG_BASE +0x511ce*4+0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x511cf*4+0x02000000,0x7974); +reg_write( DDR_REG_BASE +0x511d0*4+0x02000000,0xb1a0); +reg_write( DDR_REG_BASE +0x511d1*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x511d2*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x511d3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x511d4*4+0x02000000,0x28c); +reg_write( DDR_REG_BASE +0x511d5*4+0x02000000,0x615c); +reg_write( DDR_REG_BASE +0x511d6*4+0x02000000,0x212f); +reg_write( DDR_REG_BASE +0x511d7*4+0x02000000,0x782); +reg_write( DDR_REG_BASE +0x511d8*4+0x02000000,0x7c74); +reg_write( DDR_REG_BASE +0x511d9*4+0x02000000,0x216c); +reg_write( DDR_REG_BASE +0x511da*4+0x02000000,0x101); +reg_write( DDR_REG_BASE +0x511db*4+0x02000000,0xb420); +reg_write( DDR_REG_BASE +0x511dc*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x511dd*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x511de*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x511df*4+0x02000000,0x1ec); +reg_write( DDR_REG_BASE +0x511e0*4+0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x511e1*4+0x02000000,0x7974); +reg_write( DDR_REG_BASE +0x511e2*4+0x02000000,0xb1e0); +reg_write( DDR_REG_BASE +0x511e3*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x511e4*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x511e5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x511e6*4+0x02000000,0x14c); +reg_write( DDR_REG_BASE +0x511e7*4+0x02000000,0x6159); +reg_write( DDR_REG_BASE +0x511e8*4+0x02000000,0x7974); +reg_write( DDR_REG_BASE +0x511e9*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x511ea*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x511eb*4+0x02000000,0xb8f); +reg_write( DDR_REG_BASE +0x511ec*4+0x02000000,0x90c5); +reg_write( DDR_REG_BASE +0x511ed*4+0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x511ee*4+0x02000000,0xb21); +reg_write( DDR_REG_BASE +0x511ef*4+0x02000000,0xb134); +reg_write( DDR_REG_BASE +0x511f0*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x511f1*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x511f2*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x511f3*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x511f4*4+0x02000000,0x7b0); +reg_write( DDR_REG_BASE +0x511f5*4+0x02000000,0xd92e); +reg_write( DDR_REG_BASE +0x511f6*4+0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x511f7*4+0x02000000,0x2140); +reg_write( DDR_REG_BASE +0x511f8*4+0x02000000,0x98e); +reg_write( DDR_REG_BASE +0x511f9*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x511fa*4+0x02000000,0x2642); +reg_write( DDR_REG_BASE +0x511fb*4+0x02000000,0x1283); +reg_write( DDR_REG_BASE +0x511fc*4+0x02000000,0x2142); +reg_write( DDR_REG_BASE +0x511fd*4+0x02000000,0x280); +reg_write( DDR_REG_BASE +0x511fe*4+0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x511ff*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51200*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51201*4+0x02000000,0x26ca); +reg_write( DDR_REG_BASE +0x51202*4+0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x51203*4+0x02000000,0x4308); +reg_write( DDR_REG_BASE +0x51204*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51205*4+0x02000000,0xf05e); +reg_write( DDR_REG_BASE +0x51206*4+0x02000000,0xdb1); +reg_write( DDR_REG_BASE +0x51207*4+0x02000000,0x12e0); +reg_write( DDR_REG_BASE +0x51208*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51209*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5120a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5120b*4+0x02000000,0x7b0); +reg_write( DDR_REG_BASE +0x5120c*4+0x02000000,0x1003); +reg_write( DDR_REG_BASE +0x5120d*4+0x02000000,0x9f); +reg_write( DDR_REG_BASE +0x5120e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5120f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51210*4+0x02000000,0x7b0); +reg_write( DDR_REG_BASE +0x51211*4+0x02000000,0x8882); +reg_write( DDR_REG_BASE +0x51212*4+0x02000000,0xba8f); +reg_write( DDR_REG_BASE +0x51213*4+0x02000000,0x4358); +reg_write( DDR_REG_BASE +0x51214*4+0x02000000,0xf031); +reg_write( DDR_REG_BASE +0x51215*4+0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x51216*4+0x02000000,0x1a0f); +reg_write( DDR_REG_BASE +0x51217*4+0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x51218*4+0x02000000,0x921); +reg_write( DDR_REG_BASE +0x51219*4+0x02000000,0x32); +reg_write( DDR_REG_BASE +0x5121a*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x5121b*4+0x02000000,0x1a00); +reg_write( DDR_REG_BASE +0x5121c*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x5121d*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x5121e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5121f*4+0x02000000,0x28c); +reg_write( DDR_REG_BASE +0x51220*4+0x02000000,0x61f9); +reg_write( DDR_REG_BASE +0x51221*4+0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x51222*4+0x02000000,0x302); +reg_write( DDR_REG_BASE +0x51223*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51224*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x51225*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51226*4+0x02000000,0x32c); +reg_write( DDR_REG_BASE +0x51227*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x51228*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51229*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x5122a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5122b*4+0x02000000,0x1ec); +reg_write( DDR_REG_BASE +0x5122c*4+0x02000000,0x61fa); +reg_write( DDR_REG_BASE +0x5122d*4+0x02000000,0x22f4); +reg_write( DDR_REG_BASE +0x5122e*4+0x02000000,0x302); +reg_write( DDR_REG_BASE +0x5122f*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x51230*4+0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x51231*4+0x02000000,0x301); +reg_write( DDR_REG_BASE +0x51232*4+0x02000000,0x7942); +reg_write( DDR_REG_BASE +0x51233*4+0x02000000,0x2608); +reg_write( DDR_REG_BASE +0x51234*4+0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x51235*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51236*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x51237*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51238*4+0x02000000,0x14c); +reg_write( DDR_REG_BASE +0x51239*4+0x02000000,0x673f); +reg_write( DDR_REG_BASE +0x5123a*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x5123b*4+0x02000000,0x27f4); +reg_write( DDR_REG_BASE +0x5123c*4+0x02000000,0x130f); +reg_write( DDR_REG_BASE +0x5123d*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x5123e*4+0x02000000,0x300); +reg_write( DDR_REG_BASE +0x5123f*4+0x02000000,0x212f); +reg_write( DDR_REG_BASE +0x51240*4+0x02000000,0x6c6); +reg_write( DDR_REG_BASE +0x51241*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x51242*4+0x02000000,0x78e2); +reg_write( DDR_REG_BASE +0x51243*4+0x02000000,0x2108); +reg_write( DDR_REG_BASE +0x51244*4+0x02000000,0x1b); +reg_write( DDR_REG_BASE +0x51245*4+0x02000000,0xfa3); +reg_write( DDR_REG_BASE +0x51246*4+0x02000000,0xb325); +reg_write( DDR_REG_BASE +0x51247*4+0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x51248*4+0x02000000,0x3086); +reg_write( DDR_REG_BASE +0x51249*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5124a*4+0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x5124b*4+0x02000000,0x32); +reg_write( DDR_REG_BASE +0x5124c*4+0x02000000,0x200a); +reg_write( DDR_REG_BASE +0x5124d*4+0x02000000,0x780); +reg_write( DDR_REG_BASE +0x5124e*4+0x02000000,0xb5e); +reg_write( DDR_REG_BASE +0x5124f*4+0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x51250*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x51251*4+0x02000000,0xb12); +reg_write( DDR_REG_BASE +0x51252*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51253*4+0x02000000,0x200a); +reg_write( DDR_REG_BASE +0x51254*4+0x02000000,0x780); +reg_write( DDR_REG_BASE +0x51255*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x51256*4+0x02000000,0xb06); +reg_write( DDR_REG_BASE +0x51257*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51258*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x51259*4+0x02000000,0x6c6); +reg_write( DDR_REG_BASE +0x5125a*4+0x02000000,0x1b01); +reg_write( DDR_REG_BASE +0x5125b*4+0x02000000,0x52); +reg_write( DDR_REG_BASE +0x5125c*4+0x02000000,0x1e01); +reg_write( DDR_REG_BASE +0x5125d*4+0x02000000,0x1012); +reg_write( DDR_REG_BASE +0x5125e*4+0x02000000,0x77a5); +reg_write( DDR_REG_BASE +0x5125f*4+0x02000000,0xd51); +reg_write( DDR_REG_BASE +0x51260*4+0x02000000,0x9013); +reg_write( DDR_REG_BASE +0x51261*4+0x02000000,0x7765); +reg_write( DDR_REG_BASE +0x51262*4+0x02000000,0xbfb); +reg_write( DDR_REG_BASE +0x51263*4+0x02000000,0x9033); +reg_write( DDR_REG_BASE +0x51264*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x51265*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51266*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51267*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51268*4+0x02000000,0x7b0); +reg_write( DDR_REG_BASE +0x51269*4+0x02000000,0xd92a); +reg_write( DDR_REG_BASE +0x5126a*4+0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x5126b*4+0x02000000,0x2140); +reg_write( DDR_REG_BASE +0x5126c*4+0x02000000,0x98b); +reg_write( DDR_REG_BASE +0x5126d*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x5126e*4+0x02000000,0x2342); +reg_write( DDR_REG_BASE +0x5126f*4+0x02000000,0x1100); +reg_write( DDR_REG_BASE +0x51270*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51271*4+0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x51272*4+0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x51273*4+0x02000000,0x690c); +reg_write( DDR_REG_BASE +0x51274*4+0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x51275*4+0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x51276*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51277*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51278*4+0x02000000,0xf045); +reg_write( DDR_REG_BASE +0x51279*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5127a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5127b*4+0x02000000,0x7b0); +reg_write( DDR_REG_BASE +0x5127c*4+0x02000000,0x1003); +reg_write( DDR_REG_BASE +0x5127d*4+0x02000000,0x9e); +reg_write( DDR_REG_BASE +0x5127e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5127f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51280*4+0x02000000,0x7b0); +reg_write( DDR_REG_BASE +0x51281*4+0x02000000,0x8842); +reg_write( DDR_REG_BASE +0x51282*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51283*4+0x02000000,0xb88f); +reg_write( DDR_REG_BASE +0x51284*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x51285*4+0x02000000,0xf023); +reg_write( DDR_REG_BASE +0x51286*4+0x02000000,0xc602); +reg_write( DDR_REG_BASE +0x51287*4+0x02000000,0x235a); +reg_write( DDR_REG_BASE +0x51288*4+0x02000000,0x3a0c); +reg_write( DDR_REG_BASE +0x51289*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x5128a*4+0x02000000,0x3f8d); +reg_write( DDR_REG_BASE +0x5128b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5128c*4+0x02000000,0x1ec); +reg_write( DDR_REG_BASE +0x5128d*4+0x02000000,0x265a); +reg_write( DDR_REG_BASE +0x5128e*4+0x02000000,0x1a0e); +reg_write( DDR_REG_BASE +0x5128f*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51290*4+0x02000000,0x3f8f); +reg_write( DDR_REG_BASE +0x51291*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51292*4+0x02000000,0x14c); +reg_write( DDR_REG_BASE +0x51293*4+0x02000000,0x6599); +reg_write( DDR_REG_BASE +0x51294*4+0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x51295*4+0x02000000,0x9f); +reg_write( DDR_REG_BASE +0x51296*4+0x02000000,0x67d9); +reg_write( DDR_REG_BASE +0x51297*4+0x02000000,0x21f4); +reg_write( DDR_REG_BASE +0x51298*4+0x02000000,0x81); +reg_write( DDR_REG_BASE +0x51299*4+0x02000000,0x64fc); +reg_write( DDR_REG_BASE +0x5129a*4+0x02000000,0x65dd); +reg_write( DDR_REG_BASE +0x5129b*4+0x02000000,0x2102); +reg_write( DDR_REG_BASE +0x5129c*4+0x02000000,0x7c1); +reg_write( DDR_REG_BASE +0x5129d*4+0x02000000,0x2308); +reg_write( DDR_REG_BASE +0x5129e*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x5129f*4+0x02000000,0x24f4); +reg_write( DDR_REG_BASE +0x512a0*4+0x02000000,0x108c); +reg_write( DDR_REG_BASE +0x512a1*4+0x02000000,0x25f4); +reg_write( DDR_REG_BASE +0x512a2*4+0x02000000,0x1083); +reg_write( DDR_REG_BASE +0x512a3*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x512a4*4+0x02000000,0x7b82); +reg_write( DDR_REG_BASE +0x512a5*4+0x02000000,0x2008); +reg_write( DDR_REG_BASE +0x512a6*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x512a7*4+0x02000000,0x780e); +reg_write( DDR_REG_BASE +0x512a8*4+0x02000000,0xebd); +reg_write( DDR_REG_BASE +0x512a9*4+0x02000000,0xb0a5); +reg_write( DDR_REG_BASE +0x512aa*4+0x02000000,0x7b2e); +reg_write( DDR_REG_BASE +0x512ab*4+0x02000000,0xa5e); +reg_write( DDR_REG_BASE +0x512ac*4+0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x512ad*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x512ae*4+0x02000000,0xa56); +reg_write( DDR_REG_BASE +0x512af*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x512b0*4+0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x512b1*4+0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x512b2*4+0x02000000,0x7767); +reg_write( DDR_REG_BASE +0x512b3*4+0x02000000,0x1901); +reg_write( DDR_REG_BASE +0x512b4*4+0x02000000,0x92); +reg_write( DDR_REG_BASE +0x512b5*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x512b6*4+0x02000000,0x1b01); +reg_write( DDR_REG_BASE +0x512b7*4+0x02000000,0x1012); +reg_write( DDR_REG_BASE +0x512b8*4+0x02000000,0xb83); +reg_write( DDR_REG_BASE +0x512b9*4+0x02000000,0xb013); +reg_write( DDR_REG_BASE +0x512ba*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x512bb*4+0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x512bc*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x512bd*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x512be*4+0x02000000,0x8f5); +reg_write( DDR_REG_BASE +0x512bf*4+0x02000000,0x8033); +reg_write( DDR_REG_BASE +0x512c0*4+0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x512c1*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x512c2*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x512c3*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x512c4*4+0x02000000,0x7b0); +reg_write( DDR_REG_BASE +0x512c5*4+0x02000000,0x6901); +reg_write( DDR_REG_BASE +0x512c6*4+0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x512c7*4+0x02000000,0x7134); +reg_write( DDR_REG_BASE +0x512c8*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x512c9*4+0x02000000,0x7002); +reg_write( DDR_REG_BASE +0x512ca*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x512cb*4+0x02000000,0x7b0); +reg_write( DDR_REG_BASE +0x512cc*4+0x02000000,0x4e6); +reg_write( DDR_REG_BASE +0x512cd*4+0x02000000,0xffce); +reg_write( DDR_REG_BASE +0x512ce*4+0x02000000,0xe7e); +reg_write( DDR_REG_BASE +0x512cf*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x512d0*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x512d1*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x512d2*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x512d3*4+0x02000000,0x7344); +reg_write( DDR_REG_BASE +0x512d4*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x512d5*4+0x02000000,0x7b0); +reg_write( DDR_REG_BASE +0x512d6*4+0x02000000,0xe8a); +reg_write( DDR_REG_BASE +0x512d7*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x512d8*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x512d9*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x512da*4+0x02000000,0xe174); +reg_write( DDR_REG_BASE +0x512db*4+0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x512dc*4+0x02000000,0xf32); +reg_write( DDR_REG_BASE +0x512dd*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x512de*4+0x02000000,0xb0a1); +reg_write( DDR_REG_BASE +0x512df*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x512e0*4+0x02000000,0x330f); +reg_write( DDR_REG_BASE +0x512e1*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x512e2*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x512e3*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x512e4*4+0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x512e5*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x512e6*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x512e7*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x512e8*4+0x02000000,0xe42); +reg_write( DDR_REG_BASE +0x512e9*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512ea*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x512eb*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x512ec*4+0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x512ed*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x512ee*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x512ef*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x512f0*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x512f1*4+0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x512f2*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x512f3*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x512f4*4+0x02000000,0xf02); +reg_write( DDR_REG_BASE +0x512f5*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x512f6*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x512f7*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x512f8*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x512f9*4+0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x512fa*4+0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x512fb*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x512fc*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x512fd*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x512fe*4+0x02000000,0xeee); +reg_write( DDR_REG_BASE +0x512ff*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51300*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x51301*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x51302*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51303*4+0x02000000,0xea6); +reg_write( DDR_REG_BASE +0x51304*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51305*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51306*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x51307*4+0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x51308*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51309*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x5130a*4+0x02000000,0xd849); +reg_write( DDR_REG_BASE +0x5130b*4+0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x5130c*4+0x02000000,0x88e0); +reg_write( DDR_REG_BASE +0x5130d*4+0x02000000,0x10da); +reg_write( DDR_REG_BASE +0x5130e*4+0x02000000,0x808e); +reg_write( DDR_REG_BASE +0x5130f*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51310*4+0x02000000,0xdf2); +reg_write( DDR_REG_BASE +0x51311*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51312*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x51313*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51314*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51315*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x51316*4+0x02000000,0x736c); +reg_write( DDR_REG_BASE +0x51317*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x51318*4+0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x51319*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x5131a*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x5131b*4+0x02000000,0xeb6); +reg_write( DDR_REG_BASE +0x5131c*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5131d*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x5131e*4+0x02000000,0x7ee5); +reg_write( DDR_REG_BASE +0x5131f*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51320*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x51321*4+0x02000000,0xda09); +reg_write( DDR_REG_BASE +0x51322*4+0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x51323*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51324*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x51325*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51326*4+0x02000000,0xe9e); +reg_write( DDR_REG_BASE +0x51327*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51328*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x51329*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x5132a*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5132b*4+0x02000000,0xe56); +reg_write( DDR_REG_BASE +0x5132c*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5132d*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5132e*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x5132f*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51330*4+0x02000000,0x21aa); +reg_write( DDR_REG_BASE +0x51331*4+0x02000000,0xc4); +reg_write( DDR_REG_BASE +0x51332*4+0x02000000,0x911); +reg_write( DDR_REG_BASE +0x51333*4+0x02000000,0x3f); +reg_write( DDR_REG_BASE +0x51334*4+0x02000000,0x722c); +reg_write( DDR_REG_BASE +0x51335*4+0x02000000,0x21ab); +reg_write( DDR_REG_BASE +0x51336*4+0x02000000,0xc4); +reg_write( DDR_REG_BASE +0x51337*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51338*4+0x02000000,0x21ab); +reg_write( DDR_REG_BASE +0x51339*4+0x02000000,0xc4); +reg_write( DDR_REG_BASE +0x5133a*4+0x02000000,0x80f); +reg_write( DDR_REG_BASE +0x5133b*4+0x02000000,0x415); +reg_write( DDR_REG_BASE +0x5133c*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5133d*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x5133e*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x5133f*4+0x02000000,0x1d6); +reg_write( DDR_REG_BASE +0x51340*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51341*4+0x02000000,0x21aa); +reg_write( DDR_REG_BASE +0x51342*4+0x02000000,0x104); +reg_write( DDR_REG_BASE +0x51343*4+0x02000000,0x7b32); +reg_write( DDR_REG_BASE +0x51344*4+0x02000000,0xb19); +reg_write( DDR_REG_BASE +0x51345*4+0x02000000,0x25); +reg_write( DDR_REG_BASE +0x51346*4+0x02000000,0x24aa); +reg_write( DDR_REG_BASE +0x51347*4+0x02000000,0x1144); +reg_write( DDR_REG_BASE +0x51348*4+0x02000000,0x22aa); +reg_write( DDR_REG_BASE +0x51349*4+0x02000000,0x104); +reg_write( DDR_REG_BASE +0x5134a*4+0x02000000,0x9fd); +reg_write( DDR_REG_BASE +0x5134b*4+0x02000000,0x8084); +reg_write( DDR_REG_BASE +0x5134c*4+0x02000000,0x7862); +reg_write( DDR_REG_BASE +0x5134d*4+0x02000000,0x24aa); +reg_write( DDR_REG_BASE +0x5134e*4+0x02000000,0x1144); +reg_write( DDR_REG_BASE +0x5134f*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x51350*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51351*4+0x02000000,0x21aa); +reg_write( DDR_REG_BASE +0x51352*4+0x02000000,0x104); +reg_write( DDR_REG_BASE +0x51353*4+0x02000000,0x7110); +reg_write( DDR_REG_BASE +0x51354*4+0x02000000,0x20e1); +reg_write( DDR_REG_BASE +0x51355*4+0x02000000,0x7c6); +reg_write( DDR_REG_BASE +0x51356*4+0x02000000,0x22aa); +reg_write( DDR_REG_BASE +0x51357*4+0x02000000,0x144); +reg_write( DDR_REG_BASE +0x51358*4+0x02000000,0xcf3); +reg_write( DDR_REG_BASE +0x51359*4+0x02000000,0x9080); +reg_write( DDR_REG_BASE +0x5135a*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5135b*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5135c*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x5135d*4+0x02000000,0x822); +reg_write( DDR_REG_BASE +0x5135e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5135f*4+0x02000000,0xfa6); +reg_write( DDR_REG_BASE +0x51360*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x51361*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x51362*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51363*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51364*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x51365*4+0x02000000,0xf4a); +reg_write( DDR_REG_BASE +0x51366*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x51367*4+0x02000000,0xf96); +reg_write( DDR_REG_BASE +0x51368*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51369*4+0x02000000,0xd814); +reg_write( DDR_REG_BASE +0x5136a*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x5136b*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5136c*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5136d*4+0x02000000,0x7103); +reg_write( DDR_REG_BASE +0x5136e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5136f*4+0x02000000,0x6); +reg_write( DDR_REG_BASE +0x51370*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x51371*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x51372*4+0x02000000,0x2a05); +reg_write( DDR_REG_BASE +0x51373*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x51374*4+0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x51375*4+0x02000000,0x8480); +reg_write( DDR_REG_BASE +0x51376*4+0x02000000,0x815); +reg_write( DDR_REG_BASE +0x51377*4+0x02000000,0xf84); +reg_write( DDR_REG_BASE +0x51378*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x51379*4+0x02000000,0xd41); +reg_write( DDR_REG_BASE +0x5137a*4+0x02000000,0x2885); +reg_write( DDR_REG_BASE +0x5137b*4+0x02000000,0xa0f); +reg_write( DDR_REG_BASE +0x5137c*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x5137d*4+0x02000000,0xc2); +reg_write( DDR_REG_BASE +0x5137e*4+0x02000000,0x2a85); +reg_write( DDR_REG_BASE +0x5137f*4+0x02000000,0x41f); +reg_write( DDR_REG_BASE +0x51380*4+0x02000000,0x783d); +reg_write( DDR_REG_BASE +0x51381*4+0x02000000,0x7050); +reg_write( DDR_REG_BASE +0x51382*4+0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x51383*4+0x02000000,0xd); +reg_write( DDR_REG_BASE +0x51384*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x51385*4+0x02000000,0x6a01); +reg_write( DDR_REG_BASE +0x51386*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51387*4+0x02000000,0xa7e); +reg_write( DDR_REG_BASE +0x51388*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x51389*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x5138a*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5138b*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5138c*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5138d*4+0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x5138e*4+0x02000000,0xb9c3); +reg_write( DDR_REG_BASE +0x5138f*4+0x02000000,0xdd49); +reg_write( DDR_REG_BASE +0x51390*4+0x02000000,0x1a02); +reg_write( DDR_REG_BASE +0x51391*4+0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x51392*4+0x02000000,0xbd9f); +reg_write( DDR_REG_BASE +0x51393*4+0x02000000,0x8d00); +reg_write( DDR_REG_BASE +0x51394*4+0x02000000,0xe80b); +reg_write( DDR_REG_BASE +0x51395*4+0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x51396*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x51397*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51398*4+0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x51399*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5139a*4+0x02000000,0x48); +reg_write( DDR_REG_BASE +0x5139b*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x5139c*4+0x02000000,0xe00); +reg_write( DDR_REG_BASE +0x5139d*4+0x02000000,0x621e); +reg_write( DDR_REG_BASE +0x5139e*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x5139f*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x513a0*4+0x02000000,0x708e); +reg_write( DDR_REG_BASE +0x513a1*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x513a2*4+0x02000000,0x22); +reg_write( DDR_REG_BASE +0x513a3*4+0x02000000,0xa46); +reg_write( DDR_REG_BASE +0x513a4*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x513a5*4+0x02000000,0x79cf); +reg_write( DDR_REG_BASE +0x513a6*4+0x02000000,0x7b3d); +reg_write( DDR_REG_BASE +0x513a7*4+0x02000000,0x7a3d); +reg_write( DDR_REG_BASE +0x513a8*4+0x02000000,0x2653); +reg_write( DDR_REG_BASE +0x513a9*4+0x02000000,0x907e); +reg_write( DDR_REG_BASE +0x513aa*4+0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x513ab*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x513ac*4+0x02000000,0x23c0); +reg_write( DDR_REG_BASE +0x513ad*4+0x02000000,0x62); +reg_write( DDR_REG_BASE +0x513ae*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x513af*4+0x02000000,0x2653); +reg_write( DDR_REG_BASE +0x513b0*4+0x02000000,0x9081); +reg_write( DDR_REG_BASE +0x513b1*4+0x02000000,0xb8c3); +reg_write( DDR_REG_BASE +0x513b2*4+0x02000000,0x22c0); +reg_write( DDR_REG_BASE +0x513b3*4+0x02000000,0x62); +reg_write( DDR_REG_BASE +0x513b4*4+0x02000000,0x1a03); +reg_write( DDR_REG_BASE +0x513b5*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x513b6*4+0x02000000,0x1a05); +reg_write( DDR_REG_BASE +0x513b7*4+0x02000000,0x30c2); +reg_write( DDR_REG_BASE +0x513b8*4+0x02000000,0x1a07); +reg_write( DDR_REG_BASE +0x513b9*4+0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x513ba*4+0x02000000,0x1a04); +reg_write( DDR_REG_BASE +0x513bb*4+0x02000000,0x3082); +reg_write( DDR_REG_BASE +0x513bc*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x513bd*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x513be*4+0x02000000,0x53); +reg_write( DDR_REG_BASE +0x513bf*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x513c0*4+0x02000000,0x8e2); +reg_write( DDR_REG_BASE +0x513c1*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x513c2*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x513c3*4+0x02000000,0x216f); +reg_write( DDR_REG_BASE +0x513c4*4+0x02000000,0xc3); +reg_write( DDR_REG_BASE +0x513c5*4+0x02000000,0x8900); +reg_write( DDR_REG_BASE +0x513c6*4+0x02000000,0xb8e2); +reg_write( DDR_REG_BASE +0x513c7*4+0x02000000,0xd87f); +reg_write( DDR_REG_BASE +0x513c8*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x513c9*4+0x02000000,0x1e2); +reg_write( DDR_REG_BASE +0x513ca*4+0x02000000,0x1a08); +reg_write( DDR_REG_BASE +0x513cb*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x513cc*4+0x02000000,0x1122); +reg_write( DDR_REG_BASE +0x513cd*4+0x02000000,0x48f); +reg_write( DDR_REG_BASE +0x513ce*4+0x02000000,0x8d60); +reg_write( DDR_REG_BASE +0x513cf*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x513d0*4+0x02000000,0x2142); +reg_write( DDR_REG_BASE +0x513d1*4+0x02000000,0x4c0); +reg_write( DDR_REG_BASE +0x513d2*4+0x02000000,0x2142); +reg_write( DDR_REG_BASE +0x513d3*4+0x02000000,0x74e); +reg_write( DDR_REG_BASE +0x513d4*4+0x02000000,0x150e); +reg_write( DDR_REG_BASE +0x513d5*4+0x02000000,0x148b); +reg_write( DDR_REG_BASE +0x513d6*4+0x02000000,0x9080); +reg_write( DDR_REG_BASE +0x513d7*4+0x02000000,0x8842); +reg_write( DDR_REG_BASE +0x513d8*4+0x02000000,0x9600); +reg_write( DDR_REG_BASE +0x513d9*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x513da*4+0x02000000,0x54); +reg_write( DDR_REG_BASE +0x513db*4+0x02000000,0x6); +reg_write( DDR_REG_BASE +0x513dc*4+0x02000000,0xc241); +reg_write( DDR_REG_BASE +0x513dd*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x513de*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x513df*4+0x02000000,0x4261); +reg_write( DDR_REG_BASE +0x513e0*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x513e1*4+0x02000000,0x8a2); +reg_write( DDR_REG_BASE +0x513e2*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x513e3*4+0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x513e4*4+0x02000000,0x1501); +reg_write( DDR_REG_BASE +0x513e5*4+0x02000000,0x1483); +reg_write( DDR_REG_BASE +0x513e6*4+0x02000000,0x8d21); +reg_write( DDR_REG_BASE +0x513e7*4+0x02000000,0x8d03); +reg_write( DDR_REG_BASE +0x513e8*4+0x02000000,0x16fe); +reg_write( DDR_REG_BASE +0x513e9*4+0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x513ea*4+0x02000000,0x8d80); +reg_write( DDR_REG_BASE +0x513eb*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x513ec*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x513ed*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x513ee*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x513ef*4+0x02000000,0x59); +reg_write( DDR_REG_BASE +0x513f0*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x513f1*4+0x02000000,0x882); +reg_write( DDR_REG_BASE +0x513f2*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x513f3*4+0x02000000,0xc440); +reg_write( DDR_REG_BASE +0x513f4*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x513f5*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x513f6*4+0x02000000,0xf01f); +reg_write( DDR_REG_BASE +0x513f7*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x513f8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x513f9*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x513fa*4+0x02000000,0xf212); +reg_write( DDR_REG_BASE +0x513fb*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x513fc*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x513fd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x513fe*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x513ff*4+0x02000000,0x2244); +reg_write( DDR_REG_BASE +0x51400*4+0x02000000,0x7cc); +reg_write( DDR_REG_BASE +0x51401*4+0x02000000,0x200f); +reg_write( DDR_REG_BASE +0x51402*4+0x02000000,0x81); +reg_write( DDR_REG_BASE +0x51403*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51404*4+0x02000000,0xec05); +reg_write( DDR_REG_BASE +0x51405*4+0x02000000,0xbc61); +reg_write( DDR_REG_BASE +0x51406*4+0x02000000,0xcff); +reg_write( DDR_REG_BASE +0x51407*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x51408*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51409*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x5140a*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5140b*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x5140c*4+0x02000000,0x785b); +reg_write( DDR_REG_BASE +0x5140d*4+0x02000000,0x2056); +reg_write( DDR_REG_BASE +0x5140e*4+0x02000000,0xd00); +reg_write( DDR_REG_BASE +0x5140f*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51410*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51411*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x51412*4+0x02000000,0xe000); +reg_write( DDR_REG_BASE +0x51413*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51414*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x51415*4+0x02000000,0x7354); +reg_write( DDR_REG_BASE +0x51416*4+0x02000000,0xf7e1); +reg_write( DDR_REG_BASE +0x51417*4+0x02000000,0xf00b); +reg_write( DDR_REG_BASE +0x51418*4+0x02000000,0x2056); +reg_write( DDR_REG_BASE +0x51419*4+0x02000000,0xe00); +reg_write( DDR_REG_BASE +0x5141a*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5141b*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5141c*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x5141d*4+0x02000000,0xe000); +reg_write( DDR_REG_BASE +0x5141e*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x5141f*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x51420*4+0x02000000,0x3c5); +reg_write( DDR_REG_BASE +0x51421*4+0x02000000,0xbf1); +reg_write( DDR_REG_BASE +0x51422*4+0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x51423*4+0x02000000,0x787b); +reg_write( DDR_REG_BASE +0x51424*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51425*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51426*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x51427*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x51428*4+0x02000000,0xe1c4); +reg_write( DDR_REG_BASE +0x51429*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x5142a*4+0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x5142b*4+0x02000000,0x2156); +reg_write( DDR_REG_BASE +0x5142c*4+0x02000000,0xe01); +reg_write( DDR_REG_BASE +0x5142d*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x5142e*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x5142f*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x51430*4+0x02000000,0xe000); +reg_write( DDR_REG_BASE +0x51431*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x51432*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51433*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x51434*4+0x02000000,0x8ef); +reg_write( DDR_REG_BASE +0x51435*4+0x02000000,0x8234); +reg_write( DDR_REG_BASE +0x51436*4+0x02000000,0x791b); +reg_write( DDR_REG_BASE +0x51437*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x51438*4+0x02000000,0x3cc); +reg_write( DDR_REG_BASE +0x51439*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5143a*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x5143b*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x5143c*4+0x02000000,0xe180); +reg_write( DDR_REG_BASE +0x5143d*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5143e*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x5143f*4+0x02000000,0xe0ee); +reg_write( DDR_REG_BASE +0x51440*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x51441*4+0x02000000,0x45); +reg_write( DDR_REG_BASE +0x51442*4+0x02000000,0xe46); +reg_write( DDR_REG_BASE +0x51443*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51444*4+0x02000000,0x18fc); +reg_write( DDR_REG_BASE +0x51445*4+0x02000000,0x8045); +reg_write( DDR_REG_BASE +0x51446*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x51447*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51448*4+0x02000000,0x621a); +reg_write( DDR_REG_BASE +0x51449*4+0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x5144a*4+0x02000000,0x1801); +reg_write( DDR_REG_BASE +0x5144b*4+0x02000000,0x52); +reg_write( DDR_REG_BASE +0x5144c*4+0x02000000,0x8fd); +reg_write( DDR_REG_BASE +0x5144d*4+0x02000000,0x8084); +reg_write( DDR_REG_BASE +0x5144e*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5144f*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51450*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51451*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51452*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51453*4+0x02000000,0xc1a7); +reg_write( DDR_REG_BASE +0x51454*4+0x02000000,0xda07); +reg_write( DDR_REG_BASE +0x51455*4+0x02000000,0xba8c); +reg_write( DDR_REG_BASE +0x51456*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51457*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51458*4+0x02000000,0x9f38); +reg_write( DDR_REG_BASE +0x51459*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x5145a*4+0x02000000,0x9012); +reg_write( DDR_REG_BASE +0x5145b*4+0x02000000,0x328); +reg_write( DDR_REG_BASE +0x5145c*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5145d*4+0x02000000,0x7084); +reg_write( DDR_REG_BASE +0x5145e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5145f*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x51460*4+0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x51461*4+0x02000000,0xd858); +reg_write( DDR_REG_BASE +0x51462*4+0x02000000,0xb501); +reg_write( DDR_REG_BASE +0x51463*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51464*4+0x02000000,0xb7); +reg_write( DDR_REG_BASE +0x51465*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51466*4+0x02000000,0xf96); +reg_write( DDR_REG_BASE +0x51467*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51468*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51469*4+0x02000000,0xcc1e); +reg_write( DDR_REG_BASE +0x5146a*4+0x02000000,0x9520); +reg_write( DDR_REG_BASE +0x5146b*4+0x02000000,0x7030); +reg_write( DDR_REG_BASE +0x5146c*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5146d*4+0x02000000,0xf406); +reg_write( DDR_REG_BASE +0x5146e*4+0x02000000,0xcc1f); +reg_write( DDR_REG_BASE +0x5146f*4+0x02000000,0x9521); +reg_write( DDR_REG_BASE +0x51470*4+0x02000000,0x2038); +reg_write( DDR_REG_BASE +0x51471*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x51472*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51473*4+0x02000000,0xb9); +reg_write( DDR_REG_BASE +0x51474*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51475*4+0x02000000,0x806); +reg_write( DDR_REG_BASE +0x51476*4+0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x51477*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51478*4+0x02000000,0x7003); +reg_write( DDR_REG_BASE +0x51479*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5147a*4+0x02000000,0x6b4); +reg_write( DDR_REG_BASE +0x5147b*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5147c*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5147d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5147e*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5147f*4+0x02000000,0x1a00); +reg_write( DDR_REG_BASE +0x51480*4+0x02000000,0x3103); +reg_write( DDR_REG_BASE +0x51481*4+0x02000000,0x216f); +reg_write( DDR_REG_BASE +0x51482*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x51483*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51484*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x51485*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51486*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51487*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51488*4+0x02000000,0x9126); +reg_write( DDR_REG_BASE +0x51489*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x5148a*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5148b*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5148c*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5148d*4+0x02000000,0x32); +reg_write( DDR_REG_BASE +0x5148e*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x5148f*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51490*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x51491*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51492*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51493*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51494*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51495*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x51496*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51497*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x51498*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51499*4+0x02000000,0xb8e0); +reg_write( DDR_REG_BASE +0x5149a*4+0x02000000,0x214); +reg_write( DDR_REG_BASE +0x5149b*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5149c*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5149d*4+0x02000000,0xc103); +reg_write( DDR_REG_BASE +0x5149e*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5149f*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x514a0*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x514a1*4+0x02000000,0xe032); +reg_write( DDR_REG_BASE +0x514a2*4+0x02000000,0xb980); +reg_write( DDR_REG_BASE +0x514a3*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x514a4*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x514a5*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x514a6*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x514a7*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x514a8*4+0x02000000,0xe090); +reg_write( DDR_REG_BASE +0x514a9*4+0x02000000,0xc46); +reg_write( DDR_REG_BASE +0x514aa*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x514ab*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x514ac*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x514ad*4+0x02000000,0xdb6); +reg_write( DDR_REG_BASE +0x514ae*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x514af*4+0x02000000,0xc92); +reg_write( DDR_REG_BASE +0x514b0*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x514b1*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x514b2*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x514b3*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x514b4*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x514b5*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x514b6*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x514b7*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x514b8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x514b9*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x514ba*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x514bb*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x514bc*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x514bd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x514be*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x514bf*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x514c0*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x514c1*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x514c2*4+0x02000000,0x86); +reg_write( DDR_REG_BASE +0x514c3*4+0x02000000,0x90a0); +reg_write( DDR_REG_BASE +0x514c4*4+0x02000000,0x78bd); +reg_write( DDR_REG_BASE +0x514c5*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x514c6*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x514c7*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x514c8*4+0x02000000,0xb8c2); +reg_write( DDR_REG_BASE +0x514c9*4+0x02000000,0x827); +reg_write( DDR_REG_BASE +0x514ca*4+0x02000000,0x90); +reg_write( DDR_REG_BASE +0x514cb*4+0x02000000,0x835); +reg_write( DDR_REG_BASE +0x514cc*4+0x02000000,0xf1); +reg_write( DDR_REG_BASE +0x514cd*4+0x02000000,0x218b); +reg_write( DDR_REG_BASE +0x514ce*4+0x02000000,0x803e); +reg_write( DDR_REG_BASE +0x514cf*4+0x02000000,0xce08); +reg_write( DDR_REG_BASE +0x514d0*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x514d1*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x514d2*4+0x02000000,0x41c); +reg_write( DDR_REG_BASE +0x514d3*4+0x02000000,0x771c); +reg_write( DDR_REG_BASE +0x514d4*4+0x02000000,0x1a03); +reg_write( DDR_REG_BASE +0x514d5*4+0x02000000,0x33d8); +reg_write( DDR_REG_BASE +0x514d6*4+0x02000000,0xce0e); +reg_write( DDR_REG_BASE +0x514d7*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x514d8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x514d9*4+0x02000000,0x434); +reg_write( DDR_REG_BASE +0x514da*4+0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x514db*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x514dc*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x514dd*4+0x02000000,0x418); +reg_write( DDR_REG_BASE +0x514de*4+0x02000000,0x1a03); +reg_write( DDR_REG_BASE +0x514df*4+0x02000000,0x33d8); +reg_write( DDR_REG_BASE +0x514e0*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x514e1*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x514e2*4+0x02000000,0x430); +reg_write( DDR_REG_BASE +0x514e3*4+0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x514e4*4+0x02000000,0x218b); +reg_write( DDR_REG_BASE +0x514e5*4+0x02000000,0x803e); +reg_write( DDR_REG_BASE +0x514e6*4+0x02000000,0xce05); +reg_write( DDR_REG_BASE +0x514e7*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x514e8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x514e9*4+0x02000000,0x410); +reg_write( DDR_REG_BASE +0x514ea*4+0x02000000,0x771c); +reg_write( DDR_REG_BASE +0x514eb*4+0x02000000,0xce0b); +reg_write( DDR_REG_BASE +0x514ec*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x514ed*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x514ee*4+0x02000000,0x428); +reg_write( DDR_REG_BASE +0x514ef*4+0x02000000,0x1a03); +reg_write( DDR_REG_BASE +0x514f0*4+0x02000000,0x33d8); +reg_write( DDR_REG_BASE +0x514f1*4+0x02000000,0x761c); +reg_write( DDR_REG_BASE +0x514f2*4+0x02000000,0x1a09); +reg_write( DDR_REG_BASE +0x514f3*4+0x02000000,0x3398); +reg_write( DDR_REG_BASE +0x514f4*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x514f5*4+0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x514f6*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x514f7*4+0x02000000,0xc); +reg_write( DDR_REG_BASE +0x514f8*4+0x02000000,0x218b); +reg_write( DDR_REG_BASE +0x514f9*4+0x02000000,0x803e); +reg_write( DDR_REG_BASE +0x514fa*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x514fb*4+0x02000000,0xf9b); +reg_write( DDR_REG_BASE +0x514fc*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x514fd*4+0x02000000,0x86a0); +reg_write( DDR_REG_BASE +0x514fe*4+0x02000000,0xf20a); +reg_write( DDR_REG_BASE +0x514ff*4+0x02000000,0x233c); +reg_write( DDR_REG_BASE +0x51500*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x51501*4+0x02000000,0x79); +reg_write( DDR_REG_BASE +0x51502*4+0x02000000,0xae00); +reg_write( DDR_REG_BASE +0x51503*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51504*4+0x02000000,0x142); +reg_write( DDR_REG_BASE +0x51505*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51506*4+0x02000000,0xee2); +reg_write( DDR_REG_BASE +0x51507*4+0x02000000,0xfe8f); +reg_write( DDR_REG_BASE +0x51508*4+0x02000000,0x222f); +reg_write( DDR_REG_BASE +0x51509*4+0x02000000,0x6c2); +reg_write( DDR_REG_BASE +0x5150a*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x5150b*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x5150c*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x5150d*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x5150e*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x5150f*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51510*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51511*4+0x02000000,0xe894); +reg_write( DDR_REG_BASE +0x51512*4+0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x51513*4+0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x51514*4+0x02000000,0x6711); +reg_write( DDR_REG_BASE +0x51515*4+0x02000000,0x6610); +reg_write( DDR_REG_BASE +0x51516*4+0x02000000,0x4a10); +reg_write( DDR_REG_BASE +0x51517*4+0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x51518*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51519*4+0x02000000,0x2805); +reg_write( DDR_REG_BASE +0x5151a*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x5151b*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5151c*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5151d*4+0x02000000,0xfe80); +reg_write( DDR_REG_BASE +0x5151e*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x5151f*4+0x02000000,0x2089); +reg_write( DDR_REG_BASE +0x51520*4+0x02000000,0xfc1); +reg_write( DDR_REG_BASE +0x51521*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x51522*4+0x02000000,0x19e0); +reg_write( DDR_REG_BASE +0x51523*4+0x02000000,0x8004); +reg_write( DDR_REG_BASE +0x51524*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x51525*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x51526*4+0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x51527*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x51528*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51529*4+0x02000000,0x2b05); +reg_write( DDR_REG_BASE +0x5152a*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x5152b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5152c*4+0x02000000,0xfa00); +reg_write( DDR_REG_BASE +0x5152d*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5152e*4+0x02000000,0x81f); +reg_write( DDR_REG_BASE +0x5152f*4+0x02000000,0x1fe); +reg_write( DDR_REG_BASE +0x51530*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x51531*4+0x02000000,0x2200); +reg_write( DDR_REG_BASE +0x51532*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51533*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x51534*4+0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x51535*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x51536*4+0x02000000,0x8d47); +reg_write( DDR_REG_BASE +0x51537*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x51538*4+0x02000000,0xf684); +reg_write( DDR_REG_BASE +0x51539*4+0x02000000,0x2885); +reg_write( DDR_REG_BASE +0x5153a*4+0x02000000,0xd07); +reg_write( DDR_REG_BASE +0x5153b*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x5153c*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5153d*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x5153e*4+0x02000000,0x2089); +reg_write( DDR_REG_BASE +0x5153f*4+0x02000000,0xfc1); +reg_write( DDR_REG_BASE +0x51540*4+0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x51541*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x51542*4+0x02000000,0xc105); +reg_write( DDR_REG_BASE +0x51543*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x51544*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x51545*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x51546*4+0x02000000,0xe164); +reg_write( DDR_REG_BASE +0x51547*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51548*4+0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x51549*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5154a*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x5154b*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5154c*4+0x02000000,0x164); +reg_write( DDR_REG_BASE +0x5154d*4+0x02000000,0xb8c1); +reg_write( DDR_REG_BASE +0x5154e*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x5154f*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x51550*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51551*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51552*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51553*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51554*4+0x02000000,0x86); +reg_write( DDR_REG_BASE +0x51555*4+0x02000000,0x88a); +reg_write( DDR_REG_BASE +0x51556*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x51557*4+0x02000000,0x90c0); +reg_write( DDR_REG_BASE +0x51558*4+0x02000000,0x81a); +reg_write( DDR_REG_BASE +0x51559*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x5155a*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x5155b*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5155c*4+0x02000000,0xbe80); +reg_write( DDR_REG_BASE +0x5155d*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5155e*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5155f*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51560*4+0x02000000,0xfe86); +reg_write( DDR_REG_BASE +0x51561*4+0x02000000,0xaf6); +reg_write( DDR_REG_BASE +0x51562*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51563*4+0x02000000,0xb0c0); +reg_write( DDR_REG_BASE +0x51564*4+0x02000000,0xd42); +reg_write( DDR_REG_BASE +0x51565*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x51566*4+0x02000000,0xca04); +reg_write( DDR_REG_BASE +0x51567*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51568*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x51569*4+0x02000000,0xf034); +reg_write( DDR_REG_BASE +0x5156a*4+0x02000000,0x245a); +reg_write( DDR_REG_BASE +0x5156b*4+0x02000000,0x149e); +reg_write( DDR_REG_BASE +0x5156c*4+0x02000000,0x2600); +reg_write( DDR_REG_BASE +0x5156d*4+0x02000000,0x3f83); +reg_write( DDR_REG_BASE +0x5156e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5156f*4+0x02000000,0x6b4); +reg_write( DDR_REG_BASE +0x51570*4+0x02000000,0xb341); +reg_write( DDR_REG_BASE +0x51571*4+0x02000000,0xf029); +reg_write( DDR_REG_BASE +0x51572*4+0x02000000,0x241a); +reg_write( DDR_REG_BASE +0x51573*4+0x02000000,0x1f81); +reg_write( DDR_REG_BASE +0x51574*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51575*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x51576*4+0x02000000,0x79a5); +reg_write( DDR_REG_BASE +0x51577*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x51578*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x51579*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x5157a*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x5157b*4+0x02000000,0x140); +reg_write( DDR_REG_BASE +0x5157c*4+0x02000000,0x9120); +reg_write( DDR_REG_BASE +0x5157d*4+0x02000000,0x7e2f); +reg_write( DDR_REG_BASE +0x5157e*4+0x02000000,0xd11); +reg_write( DDR_REG_BASE +0x5157f*4+0x02000000,0x13a1); +reg_write( DDR_REG_BASE +0x51580*4+0x02000000,0xbec4); +reg_write( DDR_REG_BASE +0x51581*4+0x02000000,0x8b22); +reg_write( DDR_REG_BASE +0x51582*4+0x02000000,0x210f); +reg_write( DDR_REG_BASE +0x51583*4+0x02000000,0x341); +reg_write( DDR_REG_BASE +0x51584*4+0x02000000,0xab22); +reg_write( DDR_REG_BASE +0x51585*4+0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x51586*4+0x02000000,0x8b23); +reg_write( DDR_REG_BASE +0x51587*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x51588*4+0x02000000,0xab23); +reg_write( DDR_REG_BASE +0x51589*4+0x02000000,0x792f); +reg_write( DDR_REG_BASE +0x5158a*4+0x02000000,0x2614); +reg_write( DDR_REG_BASE +0x5158b*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x5158c*4+0x02000000,0x2100); +reg_write( DDR_REG_BASE +0x5158d*4+0x02000000,0xf8f); +reg_write( DDR_REG_BASE +0x5158e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5158f*4+0x02000000,0x6b4); +reg_write( DDR_REG_BASE +0x51590*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51591*4+0x02000000,0xafa3); +reg_write( DDR_REG_BASE +0x51592*4+0x02000000,0xee05); +reg_write( DDR_REG_BASE +0x51593*4+0x02000000,0xbe61); +reg_write( DDR_REG_BASE +0x51594*4+0x02000000,0xeff); +reg_write( DDR_REG_BASE +0x51595*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x51596*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x51597*4+0x02000000,0xaf22); +reg_write( DDR_REG_BASE +0x51598*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x51599*4+0x02000000,0xdb5); +reg_write( DDR_REG_BASE +0x5159a*4+0x02000000,0x9214); +reg_write( DDR_REG_BASE +0x5159b*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x5159c*4+0x02000000,0xc9d); +reg_write( DDR_REG_BASE +0x5159d*4+0x02000000,0x9024); +reg_write( DDR_REG_BASE +0x5159e*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x5159f*4+0x02000000,0xda2); +reg_write( DDR_REG_BASE +0x515a0*4+0x02000000,0xff0f); +reg_write( DDR_REG_BASE +0x515a1*4+0x02000000,0xa9a); +reg_write( DDR_REG_BASE +0x515a2*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x515a3*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x515a4*4+0x02000000,0xca04); +reg_write( DDR_REG_BASE +0x515a5*4+0x02000000,0x264a); +reg_write( DDR_REG_BASE +0x515a6*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x515a7*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x515a8*4+0x02000000,0xf019); +reg_write( DDR_REG_BASE +0x515a9*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x515aa*4+0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x515ab*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x515ac*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x515ad*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x515ae*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x515af*4+0x02000000,0x2300); +reg_write( DDR_REG_BASE +0x515b0*4+0x02000000,0x1f8d); +reg_write( DDR_REG_BASE +0x515b1*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x515b2*4+0x02000000,0x88c); +reg_write( DDR_REG_BASE +0x515b3*4+0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x515b4*4+0x02000000,0x7945); +reg_write( DDR_REG_BASE +0x515b5*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x515b6*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x515b7*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x515b8*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x515b9*4+0x02000000,0x140); +reg_write( DDR_REG_BASE +0x515ba*4+0x02000000,0x9180); +reg_write( DDR_REG_BASE +0x515bb*4+0x02000000,0xad80); +reg_write( DDR_REG_BASE +0x515bc*4+0x02000000,0xb140); +reg_write( DDR_REG_BASE +0x515bd*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x515be*4+0x02000000,0xadb); +reg_write( DDR_REG_BASE +0x515bf*4+0x02000000,0x8214); +reg_write( DDR_REG_BASE +0x515c0*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x515c1*4+0x02000000,0xbd3); +reg_write( DDR_REG_BASE +0x515c2*4+0x02000000,0x8024); +reg_write( DDR_REG_BASE +0x515c3*4+0x02000000,0x2616); +reg_write( DDR_REG_BASE +0x515c4*4+0x02000000,0x30cb); +reg_write( DDR_REG_BASE +0x515c5*4+0x02000000,0x88e); +reg_write( DDR_REG_BASE +0x515c6*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x515c7*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x515c8*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x515c9*4+0x02000000,0x813); +reg_write( DDR_REG_BASE +0x515ca*4+0x02000000,0xbe); +reg_write( DDR_REG_BASE +0x515cb*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x515cc*4+0x02000000,0x9e6); +reg_write( DDR_REG_BASE +0x515cd*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x515ce*4+0x02000000,0xa3e); +reg_write( DDR_REG_BASE +0x515cf*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x515d0*4+0x02000000,0x720c); +reg_write( DDR_REG_BASE +0x515d1*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x515d2*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x515d3*4+0x02000000,0x808e); +reg_write( DDR_REG_BASE +0x515d4*4+0x02000000,0xf207); +reg_write( DDR_REG_BASE +0x515d5*4+0x02000000,0x9d6); +reg_write( DDR_REG_BASE +0x515d6*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x515d7*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x515d8*4+0x02000000,0xa2a); +reg_write( DDR_REG_BASE +0x515d9*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x515da*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x515db*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x515dc*4+0x02000000,0x7045); +reg_write( DDR_REG_BASE +0x515dd*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x515de*4+0x02000000,0xe044); +reg_write( DDR_REG_BASE +0x515df*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x515e0*4+0x02000000,0x81b); +reg_write( DDR_REG_BASE +0x515e1*4+0x02000000,0x21e); +reg_write( DDR_REG_BASE +0x515e2*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x515e3*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x515e4*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x515e5*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x515e6*4+0x02000000,0xe887); +reg_write( DDR_REG_BASE +0x515e7*4+0x02000000,0x9b2); +reg_write( DDR_REG_BASE +0x515e8*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x515e9*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x515ea*4+0x02000000,0xa06); +reg_write( DDR_REG_BASE +0x515eb*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x515ec*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x515ed*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x515ee*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x515ef*4+0x02000000,0x820d); +reg_write( DDR_REG_BASE +0x515f0*4+0x02000000,0xf207); +reg_write( DDR_REG_BASE +0x515f1*4+0x02000000,0x99e); +reg_write( DDR_REG_BASE +0x515f2*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x515f3*4+0x02000000,0x750c); +reg_write( DDR_REG_BASE +0x515f4*4+0x02000000,0x9f2); +reg_write( DDR_REG_BASE +0x515f5*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x515f6*4+0x02000000,0xd8fd); +reg_write( DDR_REG_BASE +0x515f7*4+0x02000000,0xee08); +reg_write( DDR_REG_BASE +0x515f8*4+0x02000000,0x98e); +reg_write( DDR_REG_BASE +0x515f9*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x515fa*4+0x02000000,0x720c); +reg_write( DDR_REG_BASE +0x515fb*4+0x02000000,0x9e6); +reg_write( DDR_REG_BASE +0x515fc*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x515fd*4+0x02000000,0xd8fe); +reg_write( DDR_REG_BASE +0x515fe*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x515ff*4+0x02000000,0x813); +reg_write( DDR_REG_BASE +0x51600*4+0x02000000,0x13e); +reg_write( DDR_REG_BASE +0x51601*4+0x02000000,0x760c); +reg_write( DDR_REG_BASE +0x51602*4+0x02000000,0x97a); +reg_write( DDR_REG_BASE +0x51603*4+0x02000000,0xc0); +reg_write( DDR_REG_BASE +0x51604*4+0x02000000,0x9d2); +reg_write( DDR_REG_BASE +0x51605*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51606*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x51607*4+0x02000000,0xed08); +reg_write( DDR_REG_BASE +0x51608*4+0x02000000,0x96e); +reg_write( DDR_REG_BASE +0x51609*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x5160a*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x5160b*4+0x02000000,0x9c6); +reg_write( DDR_REG_BASE +0x5160c*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5160d*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x5160e*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x5160f*4+0x02000000,0x827); +reg_write( DDR_REG_BASE +0x51610*4+0x02000000,0x27f); +reg_write( DDR_REG_BASE +0x51611*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x51612*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51613*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51614*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51615*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51616*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x51617*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51618*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51619*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5161a*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5161b*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x5161c*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5161d*4+0x02000000,0xe040); +reg_write( DDR_REG_BASE +0x5161e*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5161f*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x51620*4+0x02000000,0xf03c); +reg_write( DDR_REG_BASE +0x51621*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51622*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51623*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51624*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51625*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51626*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51627*4+0x02000000,0x7b0); +reg_write( DDR_REG_BASE +0x51628*4+0x02000000,0xb8e2); +reg_write( DDR_REG_BASE +0x51629*4+0x02000000,0x25ca); +reg_write( DDR_REG_BASE +0x5162a*4+0x02000000,0x13e1); +reg_write( DDR_REG_BASE +0x5162b*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5162c*4+0x02000000,0xae00); +reg_write( DDR_REG_BASE +0x5162d*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x5162e*4+0x02000000,0x847); +reg_write( DDR_REG_BASE +0x5162f*4+0x02000000,0x95); +reg_write( DDR_REG_BASE +0x51630*4+0x02000000,0xe819); +reg_write( DDR_REG_BASE +0x51631*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51632*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51633*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51634*4+0x02000000,0x49); +reg_write( DDR_REG_BASE +0x51635*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51636*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51637*4+0x02000000,0xf211); +reg_write( DDR_REG_BASE +0x51638*4+0x02000000,0xbbe); +reg_write( DDR_REG_BASE +0x51639*4+0x02000000,0xff0f); +reg_write( DDR_REG_BASE +0x5163a*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x5163b*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5163c*4+0x02000000,0xfa2); +reg_write( DDR_REG_BASE +0x5163d*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5163e*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x5163f*4+0x02000000,0xb02); +reg_write( DDR_REG_BASE +0x51640*4+0x02000000,0xff0f); +reg_write( DDR_REG_BASE +0x51641*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x51642*4+0x02000000,0xaf6); +reg_write( DDR_REG_BASE +0x51643*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x51644*4+0x02000000,0x1e01); +reg_write( DDR_REG_BASE +0x51645*4+0x02000000,0x1003); +reg_write( DDR_REG_BASE +0x51646*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x51647*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x51648*4+0x02000000,0xf1e4); +reg_write( DDR_REG_BASE +0x51649*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5164a*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5164b*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5164c*4+0x02000000,0x23); +reg_write( DDR_REG_BASE +0x5164d*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x5164e*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5164f*4+0x02000000,0xf5ea); +reg_write( DDR_REG_BASE +0x51650*4+0x02000000,0xf1f7); +reg_write( DDR_REG_BASE +0x51651*4+0x02000000,0xf7a); +reg_write( DDR_REG_BASE +0x51652*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51653*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x51654*4+0x02000000,0xca09); +reg_write( DDR_REG_BASE +0x51655*4+0x02000000,0xe885); +reg_write( DDR_REG_BASE +0x51656*4+0x02000000,0xe02); +reg_write( DDR_REG_BASE +0x51657*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51658*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x51659*4+0x02000000,0x92a); +reg_write( DDR_REG_BASE +0x5165a*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5165b*4+0x02000000,0xd809); +reg_write( DDR_REG_BASE +0x5165c*4+0x02000000,0xca09); +reg_write( DDR_REG_BASE +0x5165d*4+0x02000000,0xe837); +reg_write( DDR_REG_BASE +0x5165e*4+0x02000000,0xd923); +reg_write( DDR_REG_BASE +0x5165f*4+0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x51660*4+0x02000000,0x8900); +reg_write( DDR_REG_BASE +0x51661*4+0x02000000,0x1126); +reg_write( DDR_REG_BASE +0x51662*4+0x02000000,0x8f); +reg_write( DDR_REG_BASE +0x51663*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x51664*4+0x02000000,0x7f05); +reg_write( DDR_REG_BASE +0x51665*4+0x02000000,0xf022); +reg_write( DDR_REG_BASE +0x51666*4+0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x51667*4+0x02000000,0x17c1); +reg_write( DDR_REG_BASE +0x51668*4+0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x51669*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x5166a*4+0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x5166b*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x5166c*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5166d*4+0x02000000,0x78eb); +reg_write( DDR_REG_BASE +0x5166e*4+0x02000000,0xf217); +reg_write( DDR_REG_BASE +0x5166f*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x51670*4+0x02000000,0xb2a); +reg_write( DDR_REG_BASE +0x51671*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51672*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51673*4+0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x51674*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x51675*4+0x02000000,0x7bcf); +reg_write( DDR_REG_BASE +0x51676*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51677*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x51678*4+0x02000000,0xdfe); +reg_write( DDR_REG_BASE +0x51679*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5167a*4+0x02000000,0x4378); +reg_write( DDR_REG_BASE +0x5167b*4+0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x5167c*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5167d*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x5167e*4+0x02000000,0xdf2); +reg_write( DDR_REG_BASE +0x5167f*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51680*4+0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x51681*4+0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x51682*4+0x02000000,0xe9e); +reg_write( DDR_REG_BASE +0x51683*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51684*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x51685*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x51686*4+0x02000000,0xec1); +reg_write( DDR_REG_BASE +0x51687*4+0x02000000,0x90b4); +reg_write( DDR_REG_BASE +0x51688*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51689*4+0x02000000,0xd9e); +reg_write( DDR_REG_BASE +0x5168a*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5168b*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x5168c*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5168d*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x5168e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5168f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51690*4+0x02000000,0xb8e5); +reg_write( DDR_REG_BASE +0x51691*4+0x02000000,0xebc); +reg_write( DDR_REG_BASE +0x51692*4+0x02000000,0xff02); +reg_write( DDR_REG_BASE +0x51693*4+0x02000000,0xd22); +reg_write( DDR_REG_BASE +0x51694*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x51695*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x51696*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51697*4+0x02000000,0x76c4); +reg_write( DDR_REG_BASE +0x51698*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x51699*4+0x02000000,0xe044); +reg_write( DDR_REG_BASE +0x5169a*4+0x02000000,0xca04); +reg_write( DDR_REG_BASE +0x5169b*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5169c*4+0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x5169d*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x5169e*4+0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x5169f*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x516a0*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x516a1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x516a2*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x516a3*4+0x02000000,0x7965); +reg_write( DDR_REG_BASE +0x516a4*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x516a5*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x516a6*4+0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x516a7*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x516a8*4+0x02000000,0x140); +reg_write( DDR_REG_BASE +0x516a9*4+0x02000000,0x2332); +reg_write( DDR_REG_BASE +0x516aa*4+0x02000000,0x1f81); +reg_write( DDR_REG_BASE +0x516ab*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x516ac*4+0x02000000,0x88c); +reg_write( DDR_REG_BASE +0x516ad*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x516ae*4+0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x516af*4+0x02000000,0xb420); +reg_write( DDR_REG_BASE +0x516b0*4+0x02000000,0xbdf); +reg_write( DDR_REG_BASE +0x516b1*4+0x02000000,0x8214); +reg_write( DDR_REG_BASE +0x516b2*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x516b3*4+0x02000000,0xad7); +reg_write( DDR_REG_BASE +0x516b4*4+0x02000000,0x8024); +reg_write( DDR_REG_BASE +0x516b5*4+0x02000000,0x2316); +reg_write( DDR_REG_BASE +0x516b6*4+0x02000000,0x308b); +reg_write( DDR_REG_BASE +0x516b7*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x516b8*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x516b9*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x516ba*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x516bb*4+0x02000000,0xe032); +reg_write( DDR_REG_BASE +0x516bc*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x516bd*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x516be*4+0x02000000,0xe9a); +reg_write( DDR_REG_BASE +0x516bf*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x516c0*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x516c1*4+0x02000000,0xcde); +reg_write( DDR_REG_BASE +0x516c2*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x516c3*4+0x02000000,0xcfe); +reg_write( DDR_REG_BASE +0x516c4*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x516c5*4+0x02000000,0xd807); +reg_write( DDR_REG_BASE +0x516c6*4+0x02000000,0x23ab); +reg_write( DDR_REG_BASE +0x516c7*4+0x02000000,0x30c4); +reg_write( DDR_REG_BASE +0x516c8*4+0x02000000,0x7fff); +reg_write( DDR_REG_BASE +0x516c9*4+0x02000000,0xf000); +reg_write( DDR_REG_BASE +0x516ca*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x516cb*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x516cc*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x516cd*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x516ce*4+0x02000000,0x9500); +reg_write( DDR_REG_BASE +0x516cf*4+0x02000000,0xb8a1); +reg_write( DDR_REG_BASE +0x516d0*4+0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x516d1*4+0x02000000,0x8c2); +reg_write( DDR_REG_BASE +0x516d2*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x516d3*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x516d4*4+0x02000000,0xd81f); +reg_write( DDR_REG_BASE +0x516d5*4+0x02000000,0x8ba); +reg_write( DDR_REG_BASE +0x516d6*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x516d7*4+0x02000000,0x1df6); +reg_write( DDR_REG_BASE +0x516d8*4+0x02000000,0x105d); +reg_write( DDR_REG_BASE +0x516d9*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x516da*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x516db*4+0x02000000,0x8ae); +reg_write( DDR_REG_BASE +0x516dc*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x516dd*4+0x02000000,0xd81f); +reg_write( DDR_REG_BASE +0x516de*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x516df*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x516e0*4+0x02000000,0x1f0); +reg_write( DDR_REG_BASE +0x516e1*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x516e2*4+0x02000000,0x89e); +reg_write( DDR_REG_BASE +0x516e3*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x516e4*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x516e5*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x516e6*4+0x02000000,0x150a); +reg_write( DDR_REG_BASE +0x516e7*4+0x02000000,0x9700); +reg_write( DDR_REG_BASE +0x516e8*4+0x02000000,0xb881); +reg_write( DDR_REG_BASE +0x516e9*4+0x02000000,0x1d0a); +reg_write( DDR_REG_BASE +0x516ea*4+0x02000000,0x901c); +reg_write( DDR_REG_BASE +0x516eb*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x516ec*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x516ed*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x516ee*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x516ef*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x516f0*4+0x02000000,0x12); +reg_write( DDR_REG_BASE +0x516f1*4+0x02000000,0x218c); +reg_write( DDR_REG_BASE +0x516f2*4+0x02000000,0x8203); +reg_write( DDR_REG_BASE +0x516f3*4+0x02000000,0xc9c); +reg_write( DDR_REG_BASE +0x516f4*4+0x02000000,0xce); +reg_write( DDR_REG_BASE +0x516f5*4+0x02000000,0x80e); +reg_write( DDR_REG_BASE +0x516f6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x516f7*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x516f8*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x516f9*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x516fa*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x516fb*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x516fc*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x516fd*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x516fe*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x516ff*4+0x02000000,0x81b); +reg_write( DDR_REG_BASE +0x51700*4+0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x51701*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51702*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x51703*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x51704*4+0x02000000,0xe036); +reg_write( DDR_REG_BASE +0x51705*4+0x02000000,0x85a); +reg_write( DDR_REG_BASE +0x51706*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51707*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x51708*4+0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x51709*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x5170a*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x5170b*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x5170c*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5170d*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5170e*4+0x02000000,0xf2); +reg_write( DDR_REG_BASE +0x5170f*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x51710*4+0x02000000,0x45); +reg_write( DDR_REG_BASE +0x51711*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x51712*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x51713*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x51714*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51715*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51716*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51717*4+0x02000000,0xc1bd); +reg_write( DDR_REG_BASE +0x51718*4+0x02000000,0xc350); +reg_write( DDR_REG_BASE +0x51719*4+0x02000000,0x4648); +reg_write( DDR_REG_BASE +0x5171a*4+0x02000000,0x4728); +reg_write( DDR_REG_BASE +0x5171b*4+0x02000000,0x84e); +reg_write( DDR_REG_BASE +0x5171c*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x5171d*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x5171e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5171f*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51720*4+0x02000000,0xe0c4); +reg_write( DDR_REG_BASE +0x51721*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x51722*4+0x02000000,0x3c5); +reg_write( DDR_REG_BASE +0x51723*4+0x02000000,0xb88b); +reg_write( DDR_REG_BASE +0x51724*4+0x02000000,0xd9f0); +reg_write( DDR_REG_BASE +0x51725*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51726*4+0x02000000,0xc093); +reg_write( DDR_REG_BASE +0x51727*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51728*4+0x02000000,0xda28); +reg_write( DDR_REG_BASE +0x51729*4+0x02000000,0xa42); +reg_write( DDR_REG_BASE +0x5172a*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5172b*4+0x02000000,0xc393); +reg_write( DDR_REG_BASE +0x5172c*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5172d*4+0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x5172e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5172f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51730*4+0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x51731*4+0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x51732*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x51733*4+0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x51734*4+0x02000000,0x1490); +reg_write( DDR_REG_BASE +0x51735*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x51736*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51737*4+0x02000000,0xbdc4); +reg_write( DDR_REG_BASE +0x51738*4+0x02000000,0xc04e); +reg_write( DDR_REG_BASE +0x51739*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x5173a*4+0x02000000,0x148c); +reg_write( DDR_REG_BASE +0x5173b*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x5173c*4+0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x5173d*4+0x02000000,0x1c24); +reg_write( DDR_REG_BASE +0x5173e*4+0x02000000,0x3003); +reg_write( DDR_REG_BASE +0x5173f*4+0x02000000,0xc04f); +reg_write( DDR_REG_BASE +0x51740*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x51741*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51742*4+0x02000000,0xed05); +reg_write( DDR_REG_BASE +0x51743*4+0x02000000,0xbd61); +reg_write( DDR_REG_BASE +0x51744*4+0x02000000,0xdff); +reg_write( DDR_REG_BASE +0x51745*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x51746*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51747*4+0x02000000,0xc748); +reg_write( DDR_REG_BASE +0x51748*4+0x02000000,0x7d0f); +reg_write( DDR_REG_BASE +0x51749*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x5174a*4+0x02000000,0x1c1c); +reg_write( DDR_REG_BASE +0x5174b*4+0x02000000,0x3103); +reg_write( DDR_REG_BASE +0x5174c*4+0x02000000,0xc346); +reg_write( DDR_REG_BASE +0x5174d*4+0x02000000,0x1c25); +reg_write( DDR_REG_BASE +0x5174e*4+0x02000000,0x3382); +reg_write( DDR_REG_BASE +0x5174f*4+0x02000000,0x1c34); +reg_write( DDR_REG_BASE +0x51750*4+0x02000000,0x3043); +reg_write( DDR_REG_BASE +0x51751*4+0x02000000,0x942); +reg_write( DDR_REG_BASE +0x51752*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51753*4+0x02000000,0x43b9); +reg_write( DDR_REG_BASE +0x51754*4+0x02000000,0xd5e); +reg_write( DDR_REG_BASE +0x51755*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51756*4+0x02000000,0xc083); +reg_write( DDR_REG_BASE +0x51757*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x51758*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51759*4+0x02000000,0x7b2); +reg_write( DDR_REG_BASE +0x5175a*4+0x02000000,0x8f21); +reg_write( DDR_REG_BASE +0x5175b*4+0x02000000,0x8f40); +reg_write( DDR_REG_BASE +0x5175c*4+0x02000000,0x1488); +reg_write( DDR_REG_BASE +0x5175d*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x5175e*4+0x02000000,0xc051); +reg_write( DDR_REG_BASE +0x5175f*4+0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x51760*4+0x02000000,0xc30f); +reg_write( DDR_REG_BASE +0x51761*4+0x02000000,0x7b54); +reg_write( DDR_REG_BASE +0x51762*4+0x02000000,0x9300); +reg_write( DDR_REG_BASE +0x51763*4+0x02000000,0xe88a); +reg_write( DDR_REG_BASE +0x51764*4+0x02000000,0xc093); +reg_write( DDR_REG_BASE +0x51765*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x51766*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x51767*4+0x02000000,0x80d); +reg_write( DDR_REG_BASE +0x51768*4+0x02000000,0x833); +reg_write( DDR_REG_BASE +0x51769*4+0x02000000,0x2042); +reg_write( DDR_REG_BASE +0x5176a*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x5176b*4+0x02000000,0xb300); +reg_write( DDR_REG_BASE +0x5176c*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x5176d*4+0x02000000,0x9e9); +reg_write( DDR_REG_BASE +0x5176e*4+0x02000000,0x80a5); +reg_write( DDR_REG_BASE +0x5176f*4+0x02000000,0x6e09); +reg_write( DDR_REG_BASE +0x51770*4+0x02000000,0x835); +reg_write( DDR_REG_BASE +0x51771*4+0x02000000,0xb5); +reg_write( DDR_REG_BASE +0x51772*4+0x02000000,0x72d5); +reg_write( DDR_REG_BASE +0x51773*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x51774*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51775*4+0x02000000,0xf0f0); +reg_write( DDR_REG_BASE +0x51776*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x51777*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51778*4+0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x51779*4+0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x5177a*4+0x02000000,0x341); +reg_write( DDR_REG_BASE +0x5177b*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x5177c*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x5177d*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x5177e*4+0x02000000,0xc46); +reg_write( DDR_REG_BASE +0x5177f*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51780*4+0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x51781*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x51782*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51783*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x51784*4+0x02000000,0xd808); +reg_write( DDR_REG_BASE +0x51785*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x51786*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x51787*4+0x02000000,0xc36); +reg_write( DDR_REG_BASE +0x51788*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51789*4+0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x5178a*4+0x02000000,0xc083); +reg_write( DDR_REG_BASE +0x5178b*4+0x02000000,0xf0e); +reg_write( DDR_REG_BASE +0x5178c*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5178d*4+0x02000000,0x6eab); +reg_write( DDR_REG_BASE +0x5178e*4+0x02000000,0x8f41); +reg_write( DDR_REG_BASE +0x5178f*4+0x02000000,0x8f20); +reg_write( DDR_REG_BASE +0x51790*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x51791*4+0x02000000,0xc30e); +reg_write( DDR_REG_BASE +0x51792*4+0x02000000,0x7b34); +reg_write( DDR_REG_BASE +0x51793*4+0x02000000,0x9300); +reg_write( DDR_REG_BASE +0x51794*4+0x02000000,0x813); +reg_write( DDR_REG_BASE +0x51795*4+0x02000000,0x7f1); +reg_write( DDR_REG_BASE +0x51796*4+0x02000000,0xc093); +reg_write( DDR_REG_BASE +0x51797*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x51798*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x51799*4+0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x5179a*4+0x02000000,0x833); +reg_write( DDR_REG_BASE +0x5179b*4+0x02000000,0xe020); +reg_write( DDR_REG_BASE +0x5179c*4+0x02000000,0xb300); +reg_write( DDR_REG_BASE +0x5179d*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x5179e*4+0x02000000,0xae7); +reg_write( DDR_REG_BASE +0x5179f*4+0x02000000,0x8065); +reg_write( DDR_REG_BASE +0x517a0*4+0x02000000,0x73b5); +reg_write( DDR_REG_BASE +0x517a1*4+0x02000000,0xe88); +reg_write( DDR_REG_BASE +0x517a2*4+0x02000000,0xffad); +reg_write( DDR_REG_BASE +0x517a3*4+0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x517a4*4+0x02000000,0xc010); +reg_write( DDR_REG_BASE +0x517a5*4+0x02000000,0xe808); +reg_write( DDR_REG_BASE +0x517a6*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x517a7*4+0x02000000,0x36); +reg_write( DDR_REG_BASE +0x517a8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x517a9*4+0x02000000,0x912); +reg_write( DDR_REG_BASE +0x517aa*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x517ab*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x517ac*4+0x02000000,0x8fc0); +reg_write( DDR_REG_BASE +0x517ad*4+0x02000000,0xf036); +reg_write( DDR_REG_BASE +0x517ae*4+0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x517af*4+0x02000000,0x7ddd); +reg_write( DDR_REG_BASE +0x517b0*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x517b1*4+0x02000000,0x382); +reg_write( DDR_REG_BASE +0x517b2*4+0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x517b3*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x517b4*4+0x02000000,0x383); +reg_write( DDR_REG_BASE +0x517b5*4+0x02000000,0x6358); +reg_write( DDR_REG_BASE +0x517b6*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x517b7*4+0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x517b8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x517b9*4+0x02000000,0x2049); +reg_write( DDR_REG_BASE +0x517ba*4+0x02000000,0x7c1); +reg_write( DDR_REG_BASE +0x517bb*4+0x02000000,0xc011); +reg_write( DDR_REG_BASE +0x517bc*4+0x02000000,0x78d4); +reg_write( DDR_REG_BASE +0x517bd*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x517be*4+0x02000000,0x4b50); +reg_write( DDR_REG_BASE +0x517bf*4+0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x517c0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x517c1*4+0x02000000,0xc052); +reg_write( DDR_REG_BASE +0x517c2*4+0x02000000,0xc010); +reg_write( DDR_REG_BASE +0x517c3*4+0x02000000,0xe813); +reg_write( DDR_REG_BASE +0x517c4*4+0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x517c5*4+0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x517c6*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x517c7*4+0x02000000,0x382); +reg_write( DDR_REG_BASE +0x517c8*4+0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x517c9*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x517ca*4+0x02000000,0x380); +reg_write( DDR_REG_BASE +0x517cb*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x517cc*4+0x02000000,0xc240); +reg_write( DDR_REG_BASE +0x517cd*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x517ce*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x517cf*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x517d0*4+0x02000000,0x38); +reg_write( DDR_REG_BASE +0x517d1*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x517d2*4+0x02000000,0x8be); +reg_write( DDR_REG_BASE +0x517d3*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x517d4*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x517d5*4+0x02000000,0xc012); +reg_write( DDR_REG_BASE +0x517d6*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x517d7*4+0x02000000,0x39); +reg_write( DDR_REG_BASE +0x517d8*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x517d9*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x517da*4+0x02000000,0x780e); +reg_write( DDR_REG_BASE +0x517db*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x517dc*4+0x02000000,0x207f); +reg_write( DDR_REG_BASE +0x517dd*4+0x02000000,0x140); +reg_write( DDR_REG_BASE +0x517de*4+0x02000000,0x932); +reg_write( DDR_REG_BASE +0x517df*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x517e0*4+0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x517e1*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x517e2*4+0x02000000,0x8f01); +reg_write( DDR_REG_BASE +0x517e3*4+0x02000000,0x899); +reg_write( DDR_REG_BASE +0x517e4*4+0x02000000,0x83a5); +reg_write( DDR_REG_BASE +0x517e5*4+0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x517e6*4+0x02000000,0x105b); +reg_write( DDR_REG_BASE +0x517e7*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x517e8*4+0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x517e9*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x517ea*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x517eb*4+0x02000000,0xc0bd); +reg_write( DDR_REG_BASE +0x517ec*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x517ed*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x517ee*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x517ef*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x517f0*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x517f1*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x517f2*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x517f3*4+0x02000000,0xc1ab); +reg_write( DDR_REG_BASE +0x517f4*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x517f5*4+0x02000000,0x690b); +reg_write( DDR_REG_BASE +0x517f6*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x517f7*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x517f8*4+0x02000000,0x9b2); +reg_write( DDR_REG_BASE +0x517f9*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x517fa*4+0x02000000,0x7e0f); +reg_write( DDR_REG_BASE +0x517fb*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x517fc*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x517fd*4+0x02000000,0x83f); +reg_write( DDR_REG_BASE +0x517fe*4+0x02000000,0x134); +reg_write( DDR_REG_BASE +0x517ff*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51800*4+0x02000000,0xc12); +reg_write( DDR_REG_BASE +0x51801*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51802*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51803*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x51804*4+0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x51805*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51806*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x51807*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51808*4+0x02000000,0xb98e); +reg_write( DDR_REG_BASE +0x51809*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5180a*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5180b*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5180c*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5180d*4+0x02000000,0xcd2); +reg_write( DDR_REG_BASE +0x5180e*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5180f*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51810*4+0x02000000,0xf8f6); +reg_write( DDR_REG_BASE +0x51811*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51812*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51813*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51814*4+0x02000000,0xcc2); +reg_write( DDR_REG_BASE +0x51815*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51816*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51817*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51818*4+0x02000000,0xc7a); +reg_write( DDR_REG_BASE +0x51819*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5181a*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5181b*4+0x02000000,0x2342); +reg_write( DDR_REG_BASE +0x5181c*4+0x02000000,0x3040); +reg_write( DDR_REG_BASE +0x5181d*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5181e*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x5181f*4+0x02000000,0x267c); +reg_write( DDR_REG_BASE +0x51820*4+0x02000000,0x1101); +reg_write( DDR_REG_BASE +0x51821*4+0x02000000,0x207c); +reg_write( DDR_REG_BASE +0x51822*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x51823*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51824*4+0x02000000,0x804d); +reg_write( DDR_REG_BASE +0x51825*4+0x02000000,0xdf08); +reg_write( DDR_REG_BASE +0x51826*4+0x02000000,0x9ce); +reg_write( DDR_REG_BASE +0x51827*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51828*4+0x02000000,0x27ca); +reg_write( DDR_REG_BASE +0x51829*4+0x02000000,0x1062); +reg_write( DDR_REG_BASE +0x5182a*4+0x02000000,0xa26); +reg_write( DDR_REG_BASE +0x5182b*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x5182c*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x5182d*4+0x02000000,0x70b5); +reg_write( DDR_REG_BASE +0x5182e*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x5182f*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x51830*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x51831*4+0x02000000,0x900f); +reg_write( DDR_REG_BASE +0x51832*4+0x02000000,0xe0c0); +reg_write( DDR_REG_BASE +0x51833*4+0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x51834*4+0x02000000,0x21); +reg_write( DDR_REG_BASE +0x51835*4+0x02000000,0xb2e0); +reg_write( DDR_REG_BASE +0x51836*4+0x02000000,0xb225); +reg_write( DDR_REG_BASE +0x51837*4+0x02000000,0xc108); +reg_write( DDR_REG_BASE +0x51838*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x51839*4+0x02000000,0x4d); +reg_write( DDR_REG_BASE +0x5183a*4+0x02000000,0x651d); +reg_write( DDR_REG_BASE +0x5183b*4+0x02000000,0x2614); +reg_write( DDR_REG_BASE +0x5183c*4+0x02000000,0x1042); +reg_write( DDR_REG_BASE +0x5183d*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5183e*4+0x02000000,0x4ad8); +reg_write( DDR_REG_BASE +0x5183f*4+0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x51840*4+0x02000000,0x4e); +reg_write( DDR_REG_BASE +0x51841*4+0x02000000,0x82f); +reg_write( DDR_REG_BASE +0x51842*4+0x02000000,0xb5); +reg_write( DDR_REG_BASE +0x51843*4+0x02000000,0x665e); +reg_write( DDR_REG_BASE +0x51844*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x51845*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51846*4+0x02000000,0xf0f0); +reg_write( DDR_REG_BASE +0x51847*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x51848*4+0x02000000,0x41e1); +reg_write( DDR_REG_BASE +0x51849*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x5184a*4+0x02000000,0x43e1); +reg_write( DDR_REG_BASE +0x5184b*4+0x02000000,0xaae); +reg_write( DDR_REG_BASE +0x5184c*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x5184d*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x5184e*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x5184f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51850*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x51851*4+0x02000000,0xd808); +reg_write( DDR_REG_BASE +0x51852*4+0x02000000,0x41e1); +reg_write( DDR_REG_BASE +0x51853*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x51854*4+0x02000000,0xa9a); +reg_write( DDR_REG_BASE +0x51855*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51856*4+0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x51857*4+0x02000000,0x4e58); +reg_write( DDR_REG_BASE +0x51858*4+0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x51859*4+0x02000000,0x234f); +reg_write( DDR_REG_BASE +0x5185a*4+0x02000000,0x3040); +reg_write( DDR_REG_BASE +0x5185b*4+0x02000000,0xe510); +reg_write( DDR_REG_BASE +0x5185c*4+0x02000000,0x7214); +reg_write( DDR_REG_BASE +0x5185d*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x5185e*4+0x02000000,0xc54a); +reg_write( DDR_REG_BASE +0x5185f*4+0x02000000,0xf479); +reg_write( DDR_REG_BASE +0x51860*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x51861*4+0x02000000,0x790f); +reg_write( DDR_REG_BASE +0x51862*4+0x02000000,0xb4e); +reg_write( DDR_REG_BASE +0x51863*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51864*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51865*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x51866*4+0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x51867*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51868*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51869*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5186a*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x5186b*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x5186c*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x5186d*4+0x02000000,0xc12); +reg_write( DDR_REG_BASE +0x5186e*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5186f*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x51870*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x51871*4+0x02000000,0xf8b8); +reg_write( DDR_REG_BASE +0x51872*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x51873*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x51874*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51875*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x51876*4+0x02000000,0xbfe); +reg_write( DDR_REG_BASE +0x51877*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51878*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x51879*4+0x02000000,0xdb6); +reg_write( DDR_REG_BASE +0x5187a*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5187b*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5187c*4+0x02000000,0xbfaa); +reg_write( DDR_REG_BASE +0x5187d*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5187e*4+0x02000000,0x41e1); +reg_write( DDR_REG_BASE +0x5187f*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x51880*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x51881*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x51882*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x51883*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x51884*4+0x02000000,0xbe2); +reg_write( DDR_REG_BASE +0x51885*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51886*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x51887*4+0x02000000,0xca08); +reg_write( DDR_REG_BASE +0x51888*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51889*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5188a*4+0x02000000,0x7500); +reg_write( DDR_REG_BASE +0x5188b*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x5188c*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5188d*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5188e*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x5188f*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51890*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x51891*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x51892*4+0x02000000,0xbc6); +reg_write( DDR_REG_BASE +0x51893*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51894*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x51895*4+0x02000000,0xc86); +reg_write( DDR_REG_BASE +0x51896*4+0x02000000,0xff0f); +reg_write( DDR_REG_BASE +0x51897*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x51898*4+0x02000000,0x41e1); +reg_write( DDR_REG_BASE +0x51899*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5189a*4+0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x5189b*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5189c*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x5189d*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5189e*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x5189f*4+0x02000000,0xbae); +reg_write( DDR_REG_BASE +0x518a0*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x518a1*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x518a2*4+0x02000000,0xca08); +reg_write( DDR_REG_BASE +0x518a3*4+0x02000000,0x2350); +reg_write( DDR_REG_BASE +0x518a4*4+0x02000000,0x3301); +reg_write( DDR_REG_BASE +0x518a5*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x518a6*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x518a7*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x518a8*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x518a9*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x518aa*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x518ab*4+0x02000000,0xb96); +reg_write( DDR_REG_BASE +0x518ac*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x518ad*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x518ae*4+0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x518af*4+0x02000000,0xf8a4); +reg_write( DDR_REG_BASE +0x518b0*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x518b1*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x518b2*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x518b3*4+0x02000000,0xb86); +reg_write( DDR_REG_BASE +0x518b4*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x518b5*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x518b6*4+0x02000000,0xf89d); +reg_write( DDR_REG_BASE +0x518b7*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x518b8*4+0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x518b9*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x518ba*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x518bb*4+0x02000000,0xb76); +reg_write( DDR_REG_BASE +0x518bc*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x518bd*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x518be*4+0x02000000,0xf896); +reg_write( DDR_REG_BASE +0x518bf*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x518c0*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x518c1*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x518c2*4+0x02000000,0xb66); +reg_write( DDR_REG_BASE +0x518c3*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x518c4*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x518c5*4+0x02000000,0xd02); +reg_write( DDR_REG_BASE +0x518c6*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x518c7*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x518c8*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x518c9*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x518ca*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x518cb*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x518cc*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x518cd*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x518ce*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x518cf*4+0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x518d0*4+0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x518d1*4+0x02000000,0xb4a); +reg_write( DDR_REG_BASE +0x518d2*4+0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x518d3*4+0x02000000,0xc0ab); +reg_write( DDR_REG_BASE +0x518d4*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x518d5*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x518d6*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x518d7*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x518d8*4+0x02000000,0x811); +reg_write( DDR_REG_BASE +0x518d9*4+0x02000000,0x135); +reg_write( DDR_REG_BASE +0x518da*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x518db*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x518dc*4+0x02000000,0xf36); +reg_write( DDR_REG_BASE +0x518dd*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x518de*4+0x02000000,0xb992); +reg_write( DDR_REG_BASE +0x518df*4+0x02000000,0xf1f5); +reg_write( DDR_REG_BASE +0x518e0*4+0x02000000,0xbe7); +reg_write( DDR_REG_BASE +0x518e1*4+0x02000000,0xb071); +reg_write( DDR_REG_BASE +0x518e2*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x518e3*4+0x02000000,0x736f); +reg_write( DDR_REG_BASE +0x518e4*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x518e5*4+0x02000000,0xf092); +reg_write( DDR_REG_BASE +0x518e6*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x518e7*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x518e8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x518e9*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x518ea*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x518eb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x518ec*4+0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x518ed*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x518ee*4+0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x518ef*4+0x02000000,0x21); +reg_write( DDR_REG_BASE +0x518f0*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x518f1*4+0x02000000,0x4220); +reg_write( DDR_REG_BASE +0x518f2*4+0x02000000,0x95e); +reg_write( DDR_REG_BASE +0x518f3*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x518f4*4+0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x518f5*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x518f6*4+0x02000000,0xa26); +reg_write( DDR_REG_BASE +0x518f7*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x518f8*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x518f9*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x518fa*4+0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x518fb*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x518fc*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x518fd*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x518fe*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x518ff*4+0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x51900*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x51901*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x51902*4+0x02000000,0xae6); +reg_write( DDR_REG_BASE +0x51903*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51904*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x51905*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x51906*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x51907*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51908*4+0x02000000,0x4400); +reg_write( DDR_REG_BASE +0x51909*4+0x02000000,0x41e1); +reg_write( DDR_REG_BASE +0x5190a*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x5190b*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x5190c*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5190d*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5190e*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5190f*4+0x02000000,0xdb7c); +reg_write( DDR_REG_BASE +0x51910*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x51911*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x51912*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51913*4+0x02000000,0xac6); +reg_write( DDR_REG_BASE +0x51914*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51915*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51916*4+0x02000000,0xbfaa); +reg_write( DDR_REG_BASE +0x51917*4+0x02000000,0xc746); +reg_write( DDR_REG_BASE +0x51918*4+0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x51919*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5191a*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5191b*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x5191c*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5191d*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5191e*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5191f*4+0x02000000,0xaae); +reg_write( DDR_REG_BASE +0x51920*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51921*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51922*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51923*4+0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x51924*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x51925*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51926*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51927*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x51928*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x51929*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x5192a*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x5192b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5192c*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x5192d*4+0x02000000,0x20f); +reg_write( DDR_REG_BASE +0x5192e*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5192f*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51930*4+0x02000000,0xa8a); +reg_write( DDR_REG_BASE +0x51931*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51932*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x51933*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51934*4+0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x51935*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x51936*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51937*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51938*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x51939*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x5193a*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x5193b*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5193c*4+0x02000000,0xa72); +reg_write( DDR_REG_BASE +0x5193d*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5193e*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x5193f*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51940*4+0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x51941*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x51942*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51943*4+0x02000000,0xb990); +reg_write( DDR_REG_BASE +0x51944*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51945*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x51946*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x51947*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x51948*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51949*4+0x02000000,0xa5a); +reg_write( DDR_REG_BASE +0x5194a*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5194b*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x5194c*4+0x02000000,0xb16); +reg_write( DDR_REG_BASE +0x5194d*4+0x02000000,0xff0f); +reg_write( DDR_REG_BASE +0x5194e*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5194f*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51950*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x51951*4+0x02000000,0xdb20); +reg_write( DDR_REG_BASE +0x51952*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x51953*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51954*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51955*4+0x02000000,0xa42); +reg_write( DDR_REG_BASE +0x51956*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51957*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x51958*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51959*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5195a*4+0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x5195b*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5195c*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5195d*4+0x02000000,0xdb26); +reg_write( DDR_REG_BASE +0x5195e*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5195f*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x51960*4+0x02000000,0xa2a); +reg_write( DDR_REG_BASE +0x51961*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51962*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x51963*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x51964*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x51965*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x51966*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x51967*4+0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x51968*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51969*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5196a*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5196b*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5196c*4+0x02000000,0xa12); +reg_write( DDR_REG_BASE +0x5196d*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5196e*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5196f*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51970*4+0x02000000,0x9ca); +reg_write( DDR_REG_BASE +0x51971*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51972*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51973*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51974*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x51975*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x51976*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x51977*4+0x02000000,0x7d0f); +reg_write( DDR_REG_BASE +0x51978*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51979*4+0x02000000,0x7214); +reg_write( DDR_REG_BASE +0x5197a*4+0x02000000,0x6d8); +reg_write( DDR_REG_BASE +0x5197b*4+0x02000000,0xffc5); +reg_write( DDR_REG_BASE +0x5197c*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5197d*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5197e*4+0x02000000,0x7105); +reg_write( DDR_REG_BASE +0x5197f*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x51980*4+0x02000000,0xe1f2); +reg_write( DDR_REG_BASE +0x51981*4+0x02000000,0x912); +reg_write( DDR_REG_BASE +0x51982*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51983*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x51984*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x51985*4+0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x51986*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51987*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51988*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x51989*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x5198a*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x5198b*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x5198c*4+0x02000000,0x9d2); +reg_write( DDR_REG_BASE +0x5198d*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5198e*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x5198f*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x51990*4+0x02000000,0xf828); +reg_write( DDR_REG_BASE +0x51991*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x51992*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x51993*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x51994*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x51995*4+0x02000000,0x9c2); +reg_write( DDR_REG_BASE +0x51996*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51997*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x51998*4+0x02000000,0xb76); +reg_write( DDR_REG_BASE +0x51999*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5199a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5199b*4+0x02000000,0xbfaa); +reg_write( DDR_REG_BASE +0x5199c*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5199d*4+0x02000000,0x41e1); +reg_write( DDR_REG_BASE +0x5199e*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5199f*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x519a0*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x519a1*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x519a2*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x519a3*4+0x02000000,0x9a6); +reg_write( DDR_REG_BASE +0x519a4*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x519a5*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x519a6*4+0x02000000,0xca08); +reg_write( DDR_REG_BASE +0x519a7*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x519a8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x519a9*4+0x02000000,0x6100); +reg_write( DDR_REG_BASE +0x519aa*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x519ab*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x519ac*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x519ad*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x519ae*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x519af*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x519b0*4+0x02000000,0x98a); +reg_write( DDR_REG_BASE +0x519b1*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x519b2*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x519b3*4+0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x519b4*4+0x02000000,0xf821); +reg_write( DDR_REG_BASE +0x519b5*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x519b6*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x519b7*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x519b8*4+0x02000000,0x97a); +reg_write( DDR_REG_BASE +0x519b9*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x519ba*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x519bb*4+0x02000000,0xf81b); +reg_write( DDR_REG_BASE +0x519bc*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x519bd*4+0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x519be*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x519bf*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x519c0*4+0x02000000,0x96a); +reg_write( DDR_REG_BASE +0x519c1*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x519c2*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x519c3*4+0x02000000,0xf814); +reg_write( DDR_REG_BASE +0x519c4*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x519c5*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x519c6*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x519c7*4+0x02000000,0x95e); +reg_write( DDR_REG_BASE +0x519c8*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x519c9*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x519ca*4+0x02000000,0xaf6); +reg_write( DDR_REG_BASE +0x519cb*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x519cc*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x519cd*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x519ce*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x519cf*4+0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x519d0*4+0x02000000,0xdb26); +reg_write( DDR_REG_BASE +0x519d1*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x519d2*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x519d3*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x519d4*4+0x02000000,0x942); +reg_write( DDR_REG_BASE +0x519d5*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x519d6*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x519d7*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x519d8*4+0x02000000,0xf812); +reg_write( DDR_REG_BASE +0x519d9*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x519da*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x519db*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x519dc*4+0x02000000,0x5eb); +reg_write( DDR_REG_BASE +0x519dd*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x519de*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x519df*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x519e0*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x519e1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x519e2*4+0x02000000,0x4400); +reg_write( DDR_REG_BASE +0x519e3*4+0x02000000,0x41e1); +reg_write( DDR_REG_BASE +0x519e4*4+0x02000000,0x7d0f); +reg_write( DDR_REG_BASE +0x519e5*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x519e6*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x519e7*4+0x02000000,0xdb7c); +reg_write( DDR_REG_BASE +0x519e8*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x519e9*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x519ea*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x519eb*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x519ec*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x519ed*4+0x02000000,0xdb10); +reg_write( DDR_REG_BASE +0x519ee*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x519ef*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x519f0*4+0x02000000,0x79fb); +reg_write( DDR_REG_BASE +0x519f1*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x519f2*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x519f3*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x519f4*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x519f5*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x519f6*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x519f7*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x519f8*4+0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x519f9*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x519fa*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x519fb*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x519fc*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x519fd*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x519fe*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x519ff*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x51a00*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x51a01*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51a02*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51a03*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51a04*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51a05*4+0x02000000,0xc1a6); +reg_write( DDR_REG_BASE +0x51a06*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x51a07*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51a08*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x51a09*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x51a0a*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x51a0b*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51a0c*4+0x02000000,0xffd); +reg_write( DDR_REG_BASE +0x51a0d*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x51a0e*4+0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x51a0f*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51a10*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51a11*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x51a12*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x51a13*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x51a14*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x51a15*4+0x02000000,0x8e19); +reg_write( DDR_REG_BASE +0x51a16*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x51a17*4+0x02000000,0x8e10); +reg_write( DDR_REG_BASE +0x51a18*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x51a19*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51a1a*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x51a1b*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x51a1c*4+0x02000000,0x9001); +reg_write( DDR_REG_BASE +0x51a1d*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51a1e*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51a1f*4+0x02000000,0xe88a); +reg_write( DDR_REG_BASE +0x51a20*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51a21*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a22*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x51a23*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x51a24*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x51a25*4+0x02000000,0xf3e); +reg_write( DDR_REG_BASE +0x51a26*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51a27*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x51a28*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x51a29*4+0x02000000,0xb6e); +reg_write( DDR_REG_BASE +0x51a2a*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51a2b*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x51a2c*4+0x02000000,0x8608); +reg_write( DDR_REG_BASE +0x51a2d*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x51a2e*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51a2f*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51a30*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51a31*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51a32*4+0x02000000,0xe064); +reg_write( DDR_REG_BASE +0x51a33*4+0x02000000,0x9b6); +reg_write( DDR_REG_BASE +0x51a34*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51a35*4+0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x51a36*4+0x02000000,0xa9e); +reg_write( DDR_REG_BASE +0x51a37*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51a38*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x51a39*4+0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x51a3a*4+0x02000000,0xf26); +reg_write( DDR_REG_BASE +0x51a3b*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x51a3c*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51a3d*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x51a3e*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51a3f*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51a40*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x51a41*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x51a42*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x51a43*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51a44*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51a45*4+0x02000000,0xe064); +reg_write( DDR_REG_BASE +0x51a46*4+0x02000000,0x2042); +reg_write( DDR_REG_BASE +0x51a47*4+0x02000000,0x98f); +reg_write( DDR_REG_BASE +0x51a48*4+0x02000000,0xb7a0); +reg_write( DDR_REG_BASE +0x51a49*4+0x02000000,0xb7a0); +reg_write( DDR_REG_BASE +0x51a4a*4+0x02000000,0x1f9c); +reg_write( DDR_REG_BASE +0x51a4b*4+0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x51a4c*4+0x02000000,0x1f9b); +reg_write( DDR_REG_BASE +0x51a4d*4+0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x51a4e*4+0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x51a4f*4+0x02000000,0x9f84); +reg_write( DDR_REG_BASE +0x51a50*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a51*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x51a52*4+0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x51a53*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x51a54*4+0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x51a55*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x51a56*4+0x02000000,0xffe); +reg_write( DDR_REG_BASE +0x51a57*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51a58*4+0x02000000,0x960e); +reg_write( DDR_REG_BASE +0x51a59*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x51a5a*4+0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x51a5b*4+0x02000000,0xade); +reg_write( DDR_REG_BASE +0x51a5c*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x51a5d*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x51a5e*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x51a5f*4+0x02000000,0xb02); +reg_write( DDR_REG_BASE +0x51a60*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51a61*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x51a62*4+0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x51a63*4+0x02000000,0xed6); +reg_write( DDR_REG_BASE +0x51a64*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x51a65*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51a66*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51a67*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51a68*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51a69*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x51a6a*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x51a6b*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x51a6c*4+0x02000000,0xb7a0); +reg_write( DDR_REG_BASE +0x51a6d*4+0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x51a6e*4+0x02000000,0x9f84); +reg_write( DDR_REG_BASE +0x51a6f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a70*4+0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x51a71*4+0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x51a72*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x51a73*4+0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x51a74*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x51a75*4+0x02000000,0xfc2); +reg_write( DDR_REG_BASE +0x51a76*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51a77*4+0x02000000,0x960a); +reg_write( DDR_REG_BASE +0x51a78*4+0x02000000,0x8e58); +reg_write( DDR_REG_BASE +0x51a79*4+0x02000000,0x8601); +reg_write( DDR_REG_BASE +0x51a7a*4+0x02000000,0xa0e); +reg_write( DDR_REG_BASE +0x51a7b*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x51a7c*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51a7d*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x51a7e*4+0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x51a7f*4+0x02000000,0xa96); +reg_write( DDR_REG_BASE +0x51a80*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x51a81*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x51a82*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x51a83*4+0x02000000,0xaba); +reg_write( DDR_REG_BASE +0x51a84*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51a85*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x51a86*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51a87*4+0x02000000,0xe808); +reg_write( DDR_REG_BASE +0x51a88*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x51a89*4+0x02000000,0x9b2); +reg_write( DDR_REG_BASE +0x51a8a*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51a8b*4+0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x51a8c*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x51a8d*4+0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x51a8e*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x51a8f*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51a90*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a91*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x51a92*4+0x02000000,0x4220); +reg_write( DDR_REG_BASE +0x51a93*4+0x02000000,0x7414); +reg_write( DDR_REG_BASE +0x51a94*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51a95*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51a96*4+0x02000000,0xfffe); +reg_write( DDR_REG_BASE +0x51a97*4+0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x51a98*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51a99*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x51a9a*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x51a9b*4+0x02000000,0xe52); +reg_write( DDR_REG_BASE +0x51a9c*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51a9d*4+0x02000000,0x4320); +reg_write( DDR_REG_BASE +0x51a9e*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51a9f*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x51aa0*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x51aa1*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x51aa2*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x51aa3*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51aa4*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x51aa5*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x51aa6*4+0x02000000,0x9001); +reg_write( DDR_REG_BASE +0x51aa7*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51aa8*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x51aa9*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51aaa*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x51aab*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x51aac*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x51aad*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x51aae*4+0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x51aaf*4+0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x51ab0*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x51ab1*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51ab2*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51ab3*4+0x02000000,0x7504); +reg_write( DDR_REG_BASE +0x51ab4*4+0x02000000,0xe32); +reg_write( DDR_REG_BASE +0x51ab5*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x51ab6*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51ab7*4+0x02000000,0x8608); +reg_write( DDR_REG_BASE +0x51ab8*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x51ab9*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51aba*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51abb*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51abc*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51abd*4+0x02000000,0xe064); +reg_write( DDR_REG_BASE +0x51abe*4+0x02000000,0x89e); +reg_write( DDR_REG_BASE +0x51abf*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51ac0*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x51ac1*4+0x02000000,0x6c4); +reg_write( DDR_REG_BASE +0x51ac2*4+0x02000000,0x986); +reg_write( DDR_REG_BASE +0x51ac3*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51ac4*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x51ac5*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51ac6*4+0x02000000,0x1f00); +reg_write( DDR_REG_BASE +0x51ac7*4+0x02000000,0x16c4); +reg_write( DDR_REG_BASE +0x51ac8*4+0x02000000,0x1f9c); +reg_write( DDR_REG_BASE +0x51ac9*4+0x02000000,0x16dc); +reg_write( DDR_REG_BASE +0x51aca*4+0x02000000,0x1f9b); +reg_write( DDR_REG_BASE +0x51acb*4+0x02000000,0x16dc); +reg_write( DDR_REG_BASE +0x51acc*4+0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x51acd*4+0x02000000,0x9f84); +reg_write( DDR_REG_BASE +0x51ace*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51acf*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x51ad0*4+0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x51ad1*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x51ad2*4+0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x51ad3*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x51ad4*4+0x02000000,0x960e); +reg_write( DDR_REG_BASE +0x51ad5*4+0x02000000,0xf02); +reg_write( DDR_REG_BASE +0x51ad6*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51ad7*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x51ad8*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x51ad9*4+0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x51ada*4+0x02000000,0x9de); +reg_write( DDR_REG_BASE +0x51adb*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x51adc*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x51add*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51ade*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x51adf*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51ae0*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x51ae1*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x51ae2*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x51ae3*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x51ae4*4+0x02000000,0x9f6); +reg_write( DDR_REG_BASE +0x51ae5*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51ae6*4+0x02000000,0x1f00); +reg_write( DDR_REG_BASE +0x51ae7*4+0x02000000,0x16c4); +reg_write( DDR_REG_BASE +0x51ae8*4+0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x51ae9*4+0x02000000,0xdca); +reg_write( DDR_REG_BASE +0x51aea*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x51aeb*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x51aec*4+0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x51aed*4+0x02000000,0x9f84); +reg_write( DDR_REG_BASE +0x51aee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51aef*4+0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x51af0*4+0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x51af1*4+0x02000000,0x9344); +reg_write( DDR_REG_BASE +0x51af2*4+0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x51af3*4+0x02000000,0x9344); +reg_write( DDR_REG_BASE +0x51af4*4+0x02000000,0x8605); +reg_write( DDR_REG_BASE +0x51af5*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51af6*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x51af7*4+0x02000000,0xebe); +reg_write( DDR_REG_BASE +0x51af8*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51af9*4+0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x51afa*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x51afb*4+0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x51afc*4+0x02000000,0x99a); +reg_write( DDR_REG_BASE +0x51afd*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x51afe*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x51aff*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51b00*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x51b01*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x51b02*4+0x02000000,0x8be); +reg_write( DDR_REG_BASE +0x51b03*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51b04*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x51b05*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x51b06*4+0x02000000,0x8e58); +reg_write( DDR_REG_BASE +0x51b07*4+0x02000000,0x8603); +reg_write( DDR_REG_BASE +0x51b08*4+0x02000000,0x8f2); +reg_write( DDR_REG_BASE +0x51b09*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x51b0a*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51b0b*4+0x02000000,0xc0a6); +reg_write( DDR_REG_BASE +0x51b0c*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x51b0d*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x51b0e*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51b0f*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51b10*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51b11*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51b12*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51b13*4+0x02000000,0xc1a8); +reg_write( DDR_REG_BASE +0x51b14*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x51b15*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51b16*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x51b17*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x51b18*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x51b19*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51b1a*4+0x02000000,0xffd); +reg_write( DDR_REG_BASE +0x51b1b*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x51b1c*4+0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x51b1d*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x51b1e*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51b1f*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x51b20*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x51b21*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x51b22*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x51b23*4+0x02000000,0x8e19); +reg_write( DDR_REG_BASE +0x51b24*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x51b25*4+0x02000000,0x8e10); +reg_write( DDR_REG_BASE +0x51b26*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51b27*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51b28*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x51b29*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x51b2a*4+0x02000000,0x9001); +reg_write( DDR_REG_BASE +0x51b2b*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51b2c*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x51b2d*4+0x02000000,0xe88a); +reg_write( DDR_REG_BASE +0x51b2e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51b2f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51b30*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x51b31*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x51b32*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x51b33*4+0x02000000,0xd22); +reg_write( DDR_REG_BASE +0x51b34*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51b35*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x51b36*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x51b37*4+0x02000000,0x952); +reg_write( DDR_REG_BASE +0x51b38*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51b39*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x51b3a*4+0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x51b3b*4+0x02000000,0x8608); +reg_write( DDR_REG_BASE +0x51b3c*4+0x02000000,0x2179); +reg_write( DDR_REG_BASE +0x51b3d*4+0x02000000,0x101); +reg_write( DDR_REG_BASE +0x51b3e*4+0x02000000,0xe46); +reg_write( DDR_REG_BASE +0x51b3f*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51b40*4+0x02000000,0xc144); +reg_write( DDR_REG_BASE +0x51b41*4+0x02000000,0x88a); +reg_write( DDR_REG_BASE +0x51b42*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51b43*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x51b44*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51b45*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51b46*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x51b47*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x51b48*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x51b49*4+0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x51b4a*4+0x02000000,0xd06); +reg_write( DDR_REG_BASE +0x51b4b*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x51b4c*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x51b4d*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x51b4e*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x51b4f*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51b50*4+0x02000000,0xe03e); +reg_write( DDR_REG_BASE +0x51b51*4+0x02000000,0xb7a0); +reg_write( DDR_REG_BASE +0x51b52*4+0x02000000,0x1f9b); +reg_write( DDR_REG_BASE +0x51b53*4+0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x51b54*4+0x02000000,0x1f9c); +reg_write( DDR_REG_BASE +0x51b55*4+0x02000000,0x135c); +reg_write( DDR_REG_BASE +0x51b56*4+0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x51b57*4+0x02000000,0x9f84); +reg_write( DDR_REG_BASE +0x51b58*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51b59*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x51b5a*4+0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x51b5b*4+0x02000000,0x9045); +reg_write( DDR_REG_BASE +0x51b5c*4+0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x51b5d*4+0x02000000,0x9045); +reg_write( DDR_REG_BASE +0x51b5e*4+0x02000000,0x960e); +reg_write( DDR_REG_BASE +0x51b5f*4+0x02000000,0xdee); +reg_write( DDR_REG_BASE +0x51b60*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51b61*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51b62*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x51b63*4+0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x51b64*4+0x02000000,0x8ca); +reg_write( DDR_REG_BASE +0x51b65*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x51b66*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x51b67*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x51b68*4+0x02000000,0x8ee); +reg_write( DDR_REG_BASE +0x51b69*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51b6a*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x51b6b*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x51b6c*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51b6d*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51b6e*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x51b6f*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x51b70*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x51b71*4+0x02000000,0xb7a0); +reg_write( DDR_REG_BASE +0x51b72*4+0x02000000,0xdc6); +reg_write( DDR_REG_BASE +0x51b73*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51b74*4+0x02000000,0x960a); +reg_write( DDR_REG_BASE +0x51b75*4+0x02000000,0x8e58); +reg_write( DDR_REG_BASE +0x51b76*4+0x02000000,0x8602); +reg_write( DDR_REG_BASE +0x51b77*4+0x02000000,0x816); +reg_write( DDR_REG_BASE +0x51b78*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x51b79*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51b7a*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x51b7b*4+0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x51b7c*4+0x02000000,0x89a); +reg_write( DDR_REG_BASE +0x51b7d*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x51b7e*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x51b7f*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x51b80*4+0x02000000,0x8be); +reg_write( DDR_REG_BASE +0x51b81*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51b82*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x51b83*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x51b84*4+0x02000000,0xe805); +reg_write( DDR_REG_BASE +0x51b85*4+0x02000000,0xfba); +reg_write( DDR_REG_BASE +0x51b86*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51b87*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51b88*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x51b89*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x51b8a*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51b8b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51b8c*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x51b8d*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x51b8e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51b8f*4+0x02000000,0xfffe); +reg_write( DDR_REG_BASE +0x51b90*4+0x02000000,0x7414); +reg_write( DDR_REG_BASE +0x51b91*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x51b92*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x51b93*4+0x02000000,0x81); +reg_write( DDR_REG_BASE +0x51b94*4+0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x51b95*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x51b96*4+0x02000000,0xc5a); +reg_write( DDR_REG_BASE +0x51b97*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51b98*4+0x02000000,0x4320); +reg_write( DDR_REG_BASE +0x51b99*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51b9a*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x51b9b*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x51b9c*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x51b9d*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x51b9e*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51b9f*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x51ba0*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x51ba1*4+0x02000000,0x9001); +reg_write( DDR_REG_BASE +0x51ba2*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x51ba3*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51ba4*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51ba5*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x51ba6*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x51ba7*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x51ba8*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51ba9*4+0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x51baa*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51bab*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51bac*4+0x02000000,0xe007); +reg_write( DDR_REG_BASE +0x51bad*4+0x02000000,0xc42); +reg_write( DDR_REG_BASE +0x51bae*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x51baf*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51bb0*4+0x02000000,0x8608); +reg_write( DDR_REG_BASE +0x51bb1*4+0x02000000,0xd62); +reg_write( DDR_REG_BASE +0x51bb2*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51bb3*4+0x02000000,0xc104); +reg_write( DDR_REG_BASE +0x51bb4*4+0x02000000,0xfa2); +reg_write( DDR_REG_BASE +0x51bb5*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51bb6*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x51bb7*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x51bb8*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51bb9*4+0x02000000,0x1f00); +reg_write( DDR_REG_BASE +0x51bba*4+0x02000000,0x16c4); +reg_write( DDR_REG_BASE +0x51bbb*4+0x02000000,0x1f9b); +reg_write( DDR_REG_BASE +0x51bbc*4+0x02000000,0x16dc); +reg_write( DDR_REG_BASE +0x51bbd*4+0x02000000,0x1f9c); +reg_write( DDR_REG_BASE +0x51bbe*4+0x02000000,0x16dc); +reg_write( DDR_REG_BASE +0x51bbf*4+0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x51bc0*4+0x02000000,0x9f84); +reg_write( DDR_REG_BASE +0x51bc1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51bc2*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x51bc3*4+0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x51bc4*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x51bc5*4+0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x51bc6*4+0x02000000,0x9044); +reg_write( DDR_REG_BASE +0x51bc7*4+0x02000000,0x960e); +reg_write( DDR_REG_BASE +0x51bc8*4+0x02000000,0xd1a); +reg_write( DDR_REG_BASE +0x51bc9*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51bca*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x51bcb*4+0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x51bcc*4+0x02000000,0xc200); +reg_write( DDR_REG_BASE +0x51bcd*4+0x02000000,0xffa); +reg_write( DDR_REG_BASE +0x51bce*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51bcf*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x51bd0*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x51bd1*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x51bd2*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51bd3*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x51bd4*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x51bd5*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x51bd6*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x51bd7*4+0x02000000,0x812); +reg_write( DDR_REG_BASE +0x51bd8*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x51bd9*4+0x02000000,0x1f00); +reg_write( DDR_REG_BASE +0x51bda*4+0x02000000,0x16c4); +reg_write( DDR_REG_BASE +0x51bdb*4+0x02000000,0x8629); +reg_write( DDR_REG_BASE +0x51bdc*4+0x02000000,0xbe2); +reg_write( DDR_REG_BASE +0x51bdd*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x51bde*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51bdf*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51be0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51be1*4+0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x51be2*4+0x02000000,0x1fe6); +reg_write( DDR_REG_BASE +0x51be3*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51be4*4+0x02000000,0x1ff2); +reg_write( DDR_REG_BASE +0x51be5*4+0x02000000,0x9344); +reg_write( DDR_REG_BASE +0x51be6*4+0x02000000,0x1fe4); +reg_write( DDR_REG_BASE +0x51be7*4+0x02000000,0x9344); +reg_write( DDR_REG_BASE +0x51be8*4+0x02000000,0x8605); +reg_write( DDR_REG_BASE +0x51be9*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51bea*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x51beb*4+0x02000000,0xcd6); +reg_write( DDR_REG_BASE +0x51bec*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51bed*4+0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x51bee*4+0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x51bef*4+0x02000000,0xc200); +reg_write( DDR_REG_BASE +0x51bf0*4+0x02000000,0xfb2); +reg_write( DDR_REG_BASE +0x51bf1*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51bf2*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x51bf3*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x51bf4*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x51bf5*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x51bf6*4+0x02000000,0xed6); +reg_write( DDR_REG_BASE +0x51bf7*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51bf8*4+0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x51bf9*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x51bfa*4+0x02000000,0x8e58); +reg_write( DDR_REG_BASE +0x51bfb*4+0x02000000,0x8603); +reg_write( DDR_REG_BASE +0x51bfc*4+0x02000000,0xf0a); +reg_write( DDR_REG_BASE +0x51bfd*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51bfe*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51bff*4+0x02000000,0xc0a8); +reg_write( DDR_REG_BASE +0x51c00*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x51c01*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x51c02*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51c03*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51c04*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51c05*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51c06*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51c07*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x51c08*4+0x02000000,0x3403); +reg_write( DDR_REG_BASE +0x51c09*4+0x02000000,0xffa); +reg_write( DDR_REG_BASE +0x51c0a*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51c0b*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51c0c*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51c0d*4+0x02000000,0x7083); +reg_write( DDR_REG_BASE +0x51c0e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51c0f*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51c10*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x51c11*4+0x02000000,0xc087); +reg_write( DDR_REG_BASE +0x51c12*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x51c13*4+0x02000000,0x86e); +reg_write( DDR_REG_BASE +0x51c14*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x51c15*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x51c16*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51c17*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51c18*4+0x02000000,0x2100); +reg_write( DDR_REG_BASE +0x51c19*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x51c1a*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51c1b*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x51c1c*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51c1d*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x51c1e*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51c1f*4+0x02000000,0x7084); +reg_write( DDR_REG_BASE +0x51c20*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51c21*4+0x02000000,0xfec4); +reg_write( DDR_REG_BASE +0x51c22*4+0x02000000,0xca08); +reg_write( DDR_REG_BASE +0x51c23*4+0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x51c24*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51c25*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x51c26*4+0x02000000,0x2244); +reg_write( DDR_REG_BASE +0x51c27*4+0x02000000,0x7c1); +reg_write( DDR_REG_BASE +0x51c28*4+0x02000000,0x6a81); +reg_write( DDR_REG_BASE +0x51c29*4+0x02000000,0x229a); +reg_write( DDR_REG_BASE +0x51c2a*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x51c2b*4+0x02000000,0xe906); +reg_write( DDR_REG_BASE +0x51c2c*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x51c2d*4+0x02000000,0x901); +reg_write( DDR_REG_BASE +0x51c2e*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x51c2f*4+0x02000000,0x7dbb); +reg_write( DDR_REG_BASE +0x51c30*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x51c31*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51c32*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51c33*4+0x02000000,0xe0c4); +reg_write( DDR_REG_BASE +0x51c34*4+0x02000000,0xb1a0); +reg_write( DDR_REG_BASE +0x51c35*4+0x02000000,0x4281); +reg_write( DDR_REG_BASE +0x51c36*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51c37*4+0x02000000,0xadd); +reg_write( DDR_REG_BASE +0x51c38*4+0x02000000,0x8234); +reg_write( DDR_REG_BASE +0x51c39*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x51c3a*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x51c3b*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51c3c*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x51c3d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51c3e*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51c3f*4+0x02000000,0x709b); +reg_write( DDR_REG_BASE +0x51c40*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51c41*4+0x02000000,0x7b4); +reg_write( DDR_REG_BASE +0x51c42*4+0x02000000,0xc145); +reg_write( DDR_REG_BASE +0x51c43*4+0x02000000,0xd907); +reg_write( DDR_REG_BASE +0x51c44*4+0x02000000,0x7916); +reg_write( DDR_REG_BASE +0x51c45*4+0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x51c46*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51c47*4+0x02000000,0xe098); +reg_write( DDR_REG_BASE +0x51c48*4+0x02000000,0x1b4); +reg_write( DDR_REG_BASE +0x51c49*4+0x02000000,0xd); +reg_write( DDR_REG_BASE +0x51c4a*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51c4b*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51c4c*4+0x02000000,0x7b4); +reg_write( DDR_REG_BASE +0x51c4d*4+0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x51c4e*4+0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x51c4f*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51c50*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x51c51*4+0x02000000,0x8c2); +reg_write( DDR_REG_BASE +0x51c52*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51c53*4+0x02000000,0x7a05); +reg_write( DDR_REG_BASE +0x51c54*4+0x02000000,0xd8ef); +reg_write( DDR_REG_BASE +0x51c55*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x51c56*4+0x02000000,0x6c0); +reg_write( DDR_REG_BASE +0x51c57*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x51c58*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51c59*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51c5a*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x51c5b*4+0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x51c5c*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x51c5d*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51c5e*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51c5f*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x51c60*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51c61*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51c62*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51c63*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x51c64*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x51c65*4+0x02000000,0x6c7); +reg_write( DDR_REG_BASE +0x51c66*4+0x02000000,0x9d3); +reg_write( DDR_REG_BASE +0x51c67*4+0x02000000,0x8005); +reg_write( DDR_REG_BASE +0x51c68*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51c69*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51c6a*4+0x02000000,0x2100); +reg_write( DDR_REG_BASE +0x51c6b*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x51c6c*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51c6d*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x51c6e*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51c6f*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x51c70*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51c71*4+0x02000000,0x7344); +reg_write( DDR_REG_BASE +0x51c72*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51c73*4+0x02000000,0xfe64); +reg_write( DDR_REG_BASE +0x51c74*4+0x02000000,0xd32); +reg_write( DDR_REG_BASE +0x51c75*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x51c76*4+0x02000000,0xd2e); +reg_write( DDR_REG_BASE +0x51c77*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x51c78*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x51c79*4+0x02000000,0xece); +reg_write( DDR_REG_BASE +0x51c7a*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51c7b*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x51c7c*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x51c7d*4+0x02000000,0xaa2); +reg_write( DDR_REG_BASE +0x51c7e*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x51c7f*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51c80*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x51c81*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x51c82*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51c83*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51c84*4+0x02000000,0xe024); +reg_write( DDR_REG_BASE +0x51c85*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51c86*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x51c87*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51c88*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51c89*4+0x02000000,0xb606); +reg_write( DDR_REG_BASE +0x51c8a*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x51c8b*4+0x02000000,0x3c4); +reg_write( DDR_REG_BASE +0x51c8c*4+0x02000000,0x1efe); +reg_write( DDR_REG_BASE +0x51c8d*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51c8e*4+0x02000000,0xb8e); +reg_write( DDR_REG_BASE +0x51c8f*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51c90*4+0x02000000,0xd818); +reg_write( DDR_REG_BASE +0x51c91*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x51c92*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51c93*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51c94*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x51c95*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51c96*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x51c97*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x51c98*4+0x02000000,0xe8e); +reg_write( DDR_REG_BASE +0x51c99*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51c9a*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x51c9b*4+0x02000000,0xd807); +reg_write( DDR_REG_BASE +0x51c9c*4+0x02000000,0xb72); +reg_write( DDR_REG_BASE +0x51c9d*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51c9e*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51c9f*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x51ca0*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x51ca1*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x51ca2*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51ca3*4+0x02000000,0xb606); +reg_write( DDR_REG_BASE +0x51ca4*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x51ca5*4+0x02000000,0xe76); +reg_write( DDR_REG_BASE +0x51ca6*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51ca7*4+0x02000000,0x1efe); +reg_write( DDR_REG_BASE +0x51ca8*4+0x02000000,0x93c5); +reg_write( DDR_REG_BASE +0x51ca9*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x51caa*4+0x02000000,0xb56); +reg_write( DDR_REG_BASE +0x51cab*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51cac*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51cad*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x51cae*4+0x02000000,0xe62); +reg_write( DDR_REG_BASE +0x51caf*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51cb0*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x51cb1*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51cb2*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51cb3*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51cb4*4+0x02000000,0x1fc5); +reg_write( DDR_REG_BASE +0x51cb5*4+0x02000000,0x1e0c); +reg_write( DDR_REG_BASE +0x51cb6*4+0x02000000,0x1fc5); +reg_write( DDR_REG_BASE +0x51cb7*4+0x02000000,0xb3e); +reg_write( DDR_REG_BASE +0x51cb8*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51cb9*4+0x02000000,0x1efe); +reg_write( DDR_REG_BASE +0x51cba*4+0x02000000,0x9344); +reg_write( DDR_REG_BASE +0x51cbb*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51cbc*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51cbd*4+0x02000000,0x7b4); +reg_write( DDR_REG_BASE +0x51cbe*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51cbf*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51cc0*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51cc1*4+0x02000000,0x7b4); +reg_write( DDR_REG_BASE +0x51cc2*4+0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x51cc3*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51cc4*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51cc5*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x51cc6*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x51cc7*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x51cc8*4+0x02000000,0xf04f); +reg_write( DDR_REG_BASE +0x51cc9*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x51cca*4+0x02000000,0xf9e); +reg_write( DDR_REG_BASE +0x51ccb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51ccc*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x51ccd*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x51cce*4+0x02000000,0x716d); +reg_write( DDR_REG_BASE +0x51ccf*4+0x02000000,0xf046); +reg_write( DDR_REG_BASE +0x51cd0*4+0x02000000,0x225f); +reg_write( DDR_REG_BASE +0x51cd1*4+0x02000000,0x480); +reg_write( DDR_REG_BASE +0x51cd2*4+0x02000000,0x74b5); +reg_write( DDR_REG_BASE +0x51cd3*4+0x02000000,0x24c0); +reg_write( DDR_REG_BASE +0x51cd4*4+0x02000000,0x1061); +reg_write( DDR_REG_BASE +0x51cd5*4+0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x51cd6*4+0x02000000,0x1061); +reg_write( DDR_REG_BASE +0x51cd7*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51cd8*4+0x02000000,0xc301); +reg_write( DDR_REG_BASE +0x51cd9*4+0x02000000,0xc087); +reg_write( DDR_REG_BASE +0x51cda*4+0x02000000,0x631b); +reg_write( DDR_REG_BASE +0x51cdb*4+0x02000000,0x7bb4); +reg_write( DDR_REG_BASE +0x51cdc*4+0x02000000,0x9300); +reg_write( DDR_REG_BASE +0x51cdd*4+0x02000000,0xe0c0); +reg_write( DDR_REG_BASE +0x51cde*4+0x02000000,0x6a); +reg_write( DDR_REG_BASE +0x51cdf*4+0x02000000,0x25); +reg_write( DDR_REG_BASE +0x51ce0*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x51ce1*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x51ce2*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51ce3*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51ce4*4+0x02000000,0x780); +reg_write( DDR_REG_BASE +0x51ce5*4+0x02000000,0x7f1b); +reg_write( DDR_REG_BASE +0x51ce6*4+0x02000000,0x7fc5); +reg_write( DDR_REG_BASE +0x51ce7*4+0x02000000,0x9700); +reg_write( DDR_REG_BASE +0x51ce8*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51ce9*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x51cea*4+0x02000000,0x23ca); +reg_write( DDR_REG_BASE +0x51ceb*4+0x02000000,0x1021); +reg_write( DDR_REG_BASE +0x51cec*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x51ced*4+0x02000000,0x21); +reg_write( DDR_REG_BASE +0x51cee*4+0x02000000,0xb43); +reg_write( DDR_REG_BASE +0x51cef*4+0x02000000,0x1030); +reg_write( DDR_REG_BASE +0x51cf0*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51cf1*4+0x02000000,0x78af); +reg_write( DDR_REG_BASE +0x51cf2*4+0x02000000,0x80d); +reg_write( DDR_REG_BASE +0x51cf3*4+0x02000000,0xd0); +reg_write( DDR_REG_BASE +0x51cf4*4+0x02000000,0x83b); +reg_write( DDR_REG_BASE +0x51cf5*4+0x02000000,0x210); +reg_write( DDR_REG_BASE +0x51cf6*4+0x02000000,0x83b); +reg_write( DDR_REG_BASE +0x51cf7*4+0x02000000,0x1d1); +reg_write( DDR_REG_BASE +0x51cf8*4+0x02000000,0x788f); +reg_write( DDR_REG_BASE +0x51cf9*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x51cfa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51cfb*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x51cfc*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x51cfd*4+0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x51cfe*4+0x02000000,0xc301); +reg_write( DDR_REG_BASE +0x51cff*4+0x02000000,0x677f); +reg_write( DDR_REG_BASE +0x51d00*4+0x02000000,0x7f14); +reg_write( DDR_REG_BASE +0x51d01*4+0x02000000,0x6861); +reg_write( DDR_REG_BASE +0x51d02*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x51d03*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51d04*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51d05*4+0x02000000,0x780); +reg_write( DDR_REG_BASE +0x51d06*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51d07*4+0x02000000,0x78c5); +reg_write( DDR_REG_BASE +0x51d08*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51d09*4+0x02000000,0xb700); +reg_write( DDR_REG_BASE +0x51d0a*4+0x02000000,0x4060); +reg_write( DDR_REG_BASE +0x51d0b*4+0x02000000,0xde9); +reg_write( DDR_REG_BASE +0x51d0c*4+0x02000000,0x9025); +reg_write( DDR_REG_BASE +0x51d0d*4+0x02000000,0xc787); +reg_write( DDR_REG_BASE +0x51d0e*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x51d0f*4+0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x51d10*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x51d11*4+0x02000000,0x9700); +reg_write( DDR_REG_BASE +0x51d12*4+0x02000000,0xb300); +reg_write( DDR_REG_BASE +0x51d13*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x51d14*4+0x02000000,0xd79); +reg_write( DDR_REG_BASE +0x51d15*4+0x02000000,0x9214); +reg_write( DDR_REG_BASE +0x51d16*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x51d17*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x51d18*4+0x02000000,0x7a2f); +reg_write( DDR_REG_BASE +0x51d19*4+0x02000000,0x863); +reg_write( DDR_REG_BASE +0x51d1a*4+0x02000000,0x80a5); +reg_write( DDR_REG_BASE +0x51d1b*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x51d1c*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51d1d*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x51d1e*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x51d1f*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x51d20*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x51d21*4+0x02000000,0xf326); +reg_write( DDR_REG_BASE +0x51d22*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51d23*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51d24*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51d25*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51d26*4+0x02000000,0xb8c3); +reg_write( DDR_REG_BASE +0x51d27*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51d28*4+0x02000000,0xf02c); +reg_write( DDR_REG_BASE +0x51d29*4+0x02000000,0x275f); +reg_write( DDR_REG_BASE +0x51d2a*4+0x02000000,0x1480); +reg_write( DDR_REG_BASE +0x51d2b*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d2c*4+0x02000000,0x47); +reg_write( DDR_REG_BASE +0x51d2d*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x51d2e*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x51d2f*4+0x02000000,0x661e); +reg_write( DDR_REG_BASE +0x51d30*4+0x02000000,0x26f4); +reg_write( DDR_REG_BASE +0x51d31*4+0x02000000,0x1340); +reg_write( DDR_REG_BASE +0x51d32*4+0x02000000,0x43a1); +reg_write( DDR_REG_BASE +0x51d33*4+0x02000000,0xe8a); +reg_write( DDR_REG_BASE +0x51d34*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x51d35*4+0x02000000,0x20bc); +reg_write( DDR_REG_BASE +0x51d36*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51d37*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51d38*4+0x02000000,0x271a); +reg_write( DDR_REG_BASE +0x51d39*4+0x02000000,0x1f81); +reg_write( DDR_REG_BASE +0x51d3a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51d3b*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x51d3c*4+0x02000000,0x26f4); +reg_write( DDR_REG_BASE +0x51d3d*4+0x02000000,0x1342); +reg_write( DDR_REG_BASE +0x51d3e*4+0x02000000,0x2054); +reg_write( DDR_REG_BASE +0x51d3f*4+0x02000000,0xd00); +reg_write( DDR_REG_BASE +0x51d40*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x51d41*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x51d42*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x51d43*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51d44*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x51d45*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x51d46*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51d47*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51d48*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51d49*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51d4a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51d4b*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51d4c*4+0x02000000,0x6058); +reg_write( DDR_REG_BASE +0x51d4d*4+0x02000000,0x2049); +reg_write( DDR_REG_BASE +0x51d4e*4+0x02000000,0xfc0); +reg_write( DDR_REG_BASE +0x51d4f*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x51d50*4+0x02000000,0xdb3); +reg_write( DDR_REG_BASE +0x51d51*4+0x02000000,0x9234); +reg_write( DDR_REG_BASE +0x51d52*4+0x02000000,0xc687); +reg_write( DDR_REG_BASE +0x51d53*4+0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x51d54*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51d55*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51d56*4+0x02000000,0x7b4); +reg_write( DDR_REG_BASE +0x51d57*4+0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x51d58*4+0x02000000,0x272f); +reg_write( DDR_REG_BASE +0x51d59*4+0x02000000,0x16c7); +reg_write( DDR_REG_BASE +0x51d5a*4+0x02000000,0x8ed); +reg_write( DDR_REG_BASE +0x51d5b*4+0x02000000,0x83e5); +reg_write( DDR_REG_BASE +0x51d5c*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x51d5d*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x51d5e*4+0x02000000,0x3403); +reg_write( DDR_REG_BASE +0x51d5f*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x51d60*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x51d61*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51d62*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51d63*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51d64*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51d65*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x51d66*4+0x02000000,0x390a); +reg_write( DDR_REG_BASE +0x51d67*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x51d68*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51d69*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51d6a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51d6b*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51d6c*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51d6d*4+0x02000000,0x4a); +reg_write( DDR_REG_BASE +0x51d6e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51d6f*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x51d70*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51d71*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51d72*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51d73*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51d74*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51d75*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51d76*4+0x02000000,0x86); +reg_write( DDR_REG_BASE +0x51d77*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51d78*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x51d79*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x51d7a*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51d7b*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51d7c*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51d7d*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51d7e*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51d7f*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51d80*4+0x02000000,0xdee); +reg_write( DDR_REG_BASE +0x51d81*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x51d82*4+0x02000000,0x2052); +reg_write( DDR_REG_BASE +0x51d83*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51d84*4+0x02000000,0xb7a); +reg_write( DDR_REG_BASE +0x51d85*4+0x02000000,0xff0f); +reg_write( DDR_REG_BASE +0x51d86*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x51d87*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51d88*4+0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x51d89*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51d8a*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x51d8b*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51d8c*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x51d8d*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51d8e*4+0x02000000,0xff68); +reg_write( DDR_REG_BASE +0x51d8f*4+0x02000000,0xca0a); +reg_write( DDR_REG_BASE +0x51d90*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x51d91*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x51d92*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x51d93*4+0x02000000,0xf40f); +reg_write( DDR_REG_BASE +0x51d94*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51d95*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51d96*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51d97*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51d98*4+0x02000000,0xb8e5); +reg_write( DDR_REG_BASE +0x51d99*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x51d9a*4+0x02000000,0xf207); +reg_write( DDR_REG_BASE +0x51d9b*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51d9c*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x51d9d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51d9e*4+0x02000000,0x7b1); +reg_write( DDR_REG_BASE +0x51d9f*4+0x02000000,0x1a0a); +reg_write( DDR_REG_BASE +0x51da0*4+0x02000000,0x3002); +reg_write( DDR_REG_BASE +0x51da1*4+0x02000000,0xc102); +reg_write( DDR_REG_BASE +0x51da2*4+0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x51da3*4+0x02000000,0x7c3); +reg_write( DDR_REG_BASE +0x51da4*4+0x02000000,0x4140); +reg_write( DDR_REG_BASE +0x51da5*4+0x02000000,0xeb06); +reg_write( DDR_REG_BASE +0x51da6*4+0x02000000,0xbb61); +reg_write( DDR_REG_BASE +0x51da7*4+0x02000000,0xb01); +reg_write( DDR_REG_BASE +0x51da8*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x51da9*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x51daa*4+0x02000000,0xc145); +reg_write( DDR_REG_BASE +0x51dab*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51dac*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x51dad*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51dae*4+0x02000000,0x7b1); +reg_write( DDR_REG_BASE +0x51daf*4+0x02000000,0x33b); +reg_write( DDR_REG_BASE +0x51db0*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51db1*4+0x02000000,0x2139); +reg_write( DDR_REG_BASE +0x51db2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51db3*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x51db4*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51db5*4+0x02000000,0xc7a); +reg_write( DDR_REG_BASE +0x51db6*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x51db7*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x51db8*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x51db9*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51dba*4+0x02000000,0xed06); +reg_write( DDR_REG_BASE +0x51dbb*4+0x02000000,0xc96); +reg_write( DDR_REG_BASE +0x51dbc*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x51dbd*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51dbe*4+0x02000000,0x311); +reg_write( DDR_REG_BASE +0x51dbf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51dc0*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51dc1*4+0x02000000,0xc8a); +reg_write( DDR_REG_BASE +0x51dc2*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51dc3*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x51dc4*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51dc5*4+0x02000000,0x709b); +reg_write( DDR_REG_BASE +0x51dc6*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51dc7*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51dc8*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x51dc9*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51dca*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x51dcb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51dcc*4+0x02000000,0x248); +reg_write( DDR_REG_BASE +0x51dcd*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51dce*4+0x02000000,0xcf6); +reg_write( DDR_REG_BASE +0x51dcf*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51dd0*4+0x02000000,0xda5a); +reg_write( DDR_REG_BASE +0x51dd1*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51dd2*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x51dd3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51dd4*4+0x02000000,0x194); +reg_write( DDR_REG_BASE +0x51dd5*4+0x02000000,0xcea); +reg_write( DDR_REG_BASE +0x51dd6*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51dd7*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x51dd8*4+0x02000000,0xdee); +reg_write( DDR_REG_BASE +0x51dd9*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51dda*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x51ddb*4+0x02000000,0xb04); +reg_write( DDR_REG_BASE +0x51ddc*4+0x02000000,0xd86); +reg_write( DDR_REG_BASE +0x51ddd*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51dde*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x51ddf*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51de0*4+0x02000000,0x7344); +reg_write( DDR_REG_BASE +0x51de1*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51de2*4+0x02000000,0xfec4); +reg_write( DDR_REG_BASE +0x51de3*4+0x02000000,0xca08); +reg_write( DDR_REG_BASE +0x51de4*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x51de5*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x51de6*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x51de7*4+0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x51de8*4+0x02000000,0x17c0); +reg_write( DDR_REG_BASE +0x51de9*4+0x02000000,0x6d21); +reg_write( DDR_REG_BASE +0x51dea*4+0x02000000,0x259a); +reg_write( DDR_REG_BASE +0x51deb*4+0x02000000,0x1008); +reg_write( DDR_REG_BASE +0x51dec*4+0x02000000,0xe805); +reg_write( DDR_REG_BASE +0x51ded*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x51dee*4+0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x51def*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x51df0*4+0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x51df1*4+0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x51df2*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x51df3*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51df4*4+0x02000000,0xe0c4); +reg_write( DDR_REG_BASE +0x51df5*4+0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x51df6*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x51df7*4+0x02000000,0xde1); +reg_write( DDR_REG_BASE +0x51df8*4+0x02000000,0x9234); +reg_write( DDR_REG_BASE +0x51df9*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51dfa*4+0x02000000,0xd880); +reg_write( DDR_REG_BASE +0x51dfb*4+0x02000000,0xb88e); +reg_write( DDR_REG_BASE +0x51dfc*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51dfd*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x51dfe*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51dff*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x51e00*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x51e01*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x51e02*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51e03*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51e04*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51e05*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x51e06*4+0x02000000,0xe1c6); +reg_write( DDR_REG_BASE +0x51e07*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51e08*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x51e09*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51e0a*4+0x02000000,0xfe86); +reg_write( DDR_REG_BASE +0x51e0b*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51e0c*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51e0d*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51e0e*4+0x02000000,0x86); +reg_write( DDR_REG_BASE +0x51e0f*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x51e10*4+0x02000000,0xb8a0); +reg_write( DDR_REG_BASE +0x51e11*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x51e12*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51e13*4+0x02000000,0x710d); +reg_write( DDR_REG_BASE +0x51e14*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x51e15*4+0x02000000,0x1c6); +reg_write( DDR_REG_BASE +0x51e16*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51e17*4+0x02000000,0xbdc9); +reg_write( DDR_REG_BASE +0x51e18*4+0x02000000,0x254f); +reg_write( DDR_REG_BASE +0x51e19*4+0x02000000,0x12cf); +reg_write( DDR_REG_BASE +0x51e1a*4+0x02000000,0xa2e); +reg_write( DDR_REG_BASE +0x51e1b*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51e1c*4+0x02000000,0xb6e0); +reg_write( DDR_REG_BASE +0x51e1d*4+0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x51e1e*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x51e1f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51e20*4+0x02000000,0xc00); +reg_write( DDR_REG_BASE +0x51e21*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x51e22*4+0x02000000,0xa1e); +reg_write( DDR_REG_BASE +0x51e23*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51e24*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51e25*4+0x02000000,0xd80a); +reg_write( DDR_REG_BASE +0x51e26*4+0x02000000,0xa16); +reg_write( DDR_REG_BASE +0x51e27*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51e28*4+0x02000000,0xb6e0); +reg_write( DDR_REG_BASE +0x51e29*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x51e2a*4+0x02000000,0x7101); +reg_write( DDR_REG_BASE +0x51e2b*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51e2c*4+0x02000000,0x1c8); +reg_write( DDR_REG_BASE +0x51e2d*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x51e2e*4+0x02000000,0xf0f); +reg_write( DDR_REG_BASE +0x51e2f*4+0x02000000,0xda3f); +reg_write( DDR_REG_BASE +0x51e30*4+0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x51e31*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x51e32*4+0x02000000,0x8f03); +reg_write( DDR_REG_BASE +0x51e33*4+0x02000000,0xb6a0); +reg_write( DDR_REG_BASE +0x51e34*4+0x02000000,0xf745); +reg_write( DDR_REG_BASE +0x51e35*4+0x02000000,0x2184); +reg_write( DDR_REG_BASE +0x51e36*4+0x02000000,0xf03); +reg_write( DDR_REG_BASE +0x51e37*4+0x02000000,0x7a3d); +reg_write( DDR_REG_BASE +0x51e38*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51e39*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51e3a*4+0x02000000,0xdb07); +reg_write( DDR_REG_BASE +0x51e3b*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x51e3c*4+0x02000000,0x3f9b); +reg_write( DDR_REG_BASE +0x51e3d*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x51e3e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51e3f*4+0x02000000,0x7b16); +reg_write( DDR_REG_BASE +0x51e40*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51e41*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e42*4+0x02000000,0x7b1); +reg_write( DDR_REG_BASE +0x51e43*4+0x02000000,0x8824); +reg_write( DDR_REG_BASE +0x51e44*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51e45*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51e46*4+0x02000000,0x7b1); +reg_write( DDR_REG_BASE +0x51e47*4+0x02000000,0x88c3); +reg_write( DDR_REG_BASE +0x51e48*4+0x02000000,0x1c1c); +reg_write( DDR_REG_BASE +0x51e49*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x51e4a*4+0x02000000,0x44c9); +reg_write( DDR_REG_BASE +0x51e4b*4+0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x51e4c*4+0x02000000,0x7884); +reg_write( DDR_REG_BASE +0x51e4d*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x51e4e*4+0x02000000,0xf8d); +reg_write( DDR_REG_BASE +0x51e4f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51e50*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x51e51*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51e52*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x51e53*4+0x02000000,0x2054); +reg_write( DDR_REG_BASE +0x51e54*4+0x02000000,0xd00); +reg_write( DDR_REG_BASE +0x51e55*4+0x02000000,0x78a5); +reg_write( DDR_REG_BASE +0x51e56*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51e57*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51e58*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51e59*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51e5a*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51e5b*4+0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x51e5c*4+0x02000000,0x788f); +reg_write( DDR_REG_BASE +0x51e5d*4+0x02000000,0x9e1); +reg_write( DDR_REG_BASE +0x51e5e*4+0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x51e5f*4+0x02000000,0xd8ef); +reg_write( DDR_REG_BASE +0x51e60*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51e61*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51e62*4+0x02000000,0xe024); +reg_write( DDR_REG_BASE +0x51e63*4+0x02000000,0x228a); +reg_write( DDR_REG_BASE +0x51e64*4+0x02000000,0x3c4); +reg_write( DDR_REG_BASE +0x51e65*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x51e66*4+0x02000000,0xb060); +reg_write( DDR_REG_BASE +0x51e67*4+0x02000000,0x180c); +reg_write( DDR_REG_BASE +0x51e68*4+0x02000000,0x45); +reg_write( DDR_REG_BASE +0x51e69*4+0x02000000,0x18fe); +reg_write( DDR_REG_BASE +0x51e6a*4+0x02000000,0x8084); +reg_write( DDR_REG_BASE +0x51e6b*4+0x02000000,0xf0a0); +reg_write( DDR_REG_BASE +0x51e6c*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x51e6d*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x51e6e*4+0x02000000,0x8c2); +reg_write( DDR_REG_BASE +0x51e6f*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x51e70*4+0x02000000,0x7a05); +reg_write( DDR_REG_BASE +0x51e71*4+0x02000000,0xd8ef); +reg_write( DDR_REG_BASE +0x51e72*4+0x02000000,0x78c4); +reg_write( DDR_REG_BASE +0x51e73*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x51e74*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51e75*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51e76*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x51e77*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x51e78*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x51e79*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x51e7a*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x51e7b*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x51e7c*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51e7d*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51e7e*4+0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x51e7f*4+0x02000000,0x78cf); +reg_write( DDR_REG_BASE +0x51e80*4+0x02000000,0x9d9); +reg_write( DDR_REG_BASE +0x51e81*4+0x02000000,0x8005); +reg_write( DDR_REG_BASE +0x51e82*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x51e83*4+0x02000000,0xaba); +reg_write( DDR_REG_BASE +0x51e84*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51e85*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x51e86*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x51e87*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x51e88*4+0x02000000,0xfe64); +reg_write( DDR_REG_BASE +0x51e89*4+0x02000000,0x90a); +reg_write( DDR_REG_BASE +0x51e8a*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x51e8b*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x51e8c*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x51e8d*4+0x02000000,0x902); +reg_write( DDR_REG_BASE +0x51e8e*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x51e8f*4+0x02000000,0x946); +reg_write( DDR_REG_BASE +0x51e90*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51e91*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x51e92*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51e93*4+0x02000000,0xe76); +reg_write( DDR_REG_BASE +0x51e94*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51e95*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51e96*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x51e97*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x51e98*4+0x02000000,0xf7a); +reg_write( DDR_REG_BASE +0x51e99*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51e9a*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51e9b*4+0x02000000,0xc08b); +reg_write( DDR_REG_BASE +0x51e9c*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51e9d*4+0x02000000,0x9ca); +reg_write( DDR_REG_BASE +0x51e9e*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51e9f*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x51ea0*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x51ea1*4+0x02000000,0xa7e); +reg_write( DDR_REG_BASE +0x51ea2*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x51ea3*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x51ea4*4+0x02000000,0xd87f); +reg_write( DDR_REG_BASE +0x51ea5*4+0x02000000,0x8d2); +reg_write( DDR_REG_BASE +0x51ea6*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x51ea7*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x51ea8*4+0x02000000,0x8ca); +reg_write( DDR_REG_BASE +0x51ea9*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x51eaa*4+0x02000000,0x90e); +reg_write( DDR_REG_BASE +0x51eab*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51eac*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x51ead*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x51eae*4+0x02000000,0xe3e); +reg_write( DDR_REG_BASE +0x51eaf*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51eb0*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x51eb1*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x51eb2*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x51eb3*4+0x02000000,0xf46); +reg_write( DDR_REG_BASE +0x51eb4*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x51eb5*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51eb6*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51eb7*4+0x02000000,0x3e00); +reg_write( DDR_REG_BASE +0x51eb8*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51eb9*4+0x02000000,0x992); +reg_write( DDR_REG_BASE +0x51eba*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x51ebb*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x51ebc*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51ebd*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51ebe*4+0x02000000,0x7b1); +reg_write( DDR_REG_BASE +0x51ebf*4+0x02000000,0x8863); +reg_write( DDR_REG_BASE +0x51ec0*4+0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x51ec1*4+0x02000000,0x240); +reg_write( DDR_REG_BASE +0x51ec2*4+0x02000000,0xf03a); +reg_write( DDR_REG_BASE +0x51ec3*4+0x02000000,0xc088); +reg_write( DDR_REG_BASE +0x51ec4*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x51ec5*4+0x02000000,0xb0a); +reg_write( DDR_REG_BASE +0x51ec6*4+0x02000000,0xff6f); +reg_write( DDR_REG_BASE +0x51ec7*4+0x02000000,0xda09); +reg_write( DDR_REG_BASE +0x51ec8*4+0x02000000,0xc700); +reg_write( DDR_REG_BASE +0x51ec9*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x51eca*4+0x02000000,0xf02d); +reg_write( DDR_REG_BASE +0x51ecb*4+0x02000000,0x78fb); +reg_write( DDR_REG_BASE +0x51ecc*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x51ecd*4+0x02000000,0xf87); +reg_write( DDR_REG_BASE +0x51ece*4+0x02000000,0xc18b); +reg_write( DDR_REG_BASE +0x51ecf*4+0x02000000,0x2135); +reg_write( DDR_REG_BASE +0x51ed0*4+0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x51ed1*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x51ed2*4+0x02000000,0x3e01); +reg_write( DDR_REG_BASE +0x51ed3*4+0x02000000,0x2135); +reg_write( DDR_REG_BASE +0x51ed4*4+0x02000000,0xb); +reg_write( DDR_REG_BASE +0x51ed5*4+0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x51ed6*4+0x02000000,0x3241); +reg_write( DDR_REG_BASE +0x51ed7*4+0x02000000,0x2302); +reg_write( DDR_REG_BASE +0x51ed8*4+0x02000000,0x1780); +reg_write( DDR_REG_BASE +0x51ed9*4+0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x51eda*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x51edb*4+0x02000000,0xc088); +reg_write( DDR_REG_BASE +0x51edc*4+0x02000000,0x60d8); +reg_write( DDR_REG_BASE +0x51edd*4+0x02000000,0xa840); +reg_write( DDR_REG_BASE +0x51ede*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51edf*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x51ee0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51ee1*4+0x02000000,0x248); +reg_write( DDR_REG_BASE +0x51ee2*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51ee3*4+0x02000000,0x60d8); +reg_write( DDR_REG_BASE +0x51ee4*4+0x02000000,0x8820); +reg_write( DDR_REG_BASE +0x51ee5*4+0x02000000,0x7c4f); +reg_write( DDR_REG_BASE +0x51ee6*4+0x02000000,0x91f); +reg_write( DDR_REG_BASE +0x51ee7*4+0x02000000,0x305); +reg_write( DDR_REG_BASE +0x51ee8*4+0x02000000,0x235f); +reg_write( DDR_REG_BASE +0x51ee9*4+0x02000000,0x3481); +reg_write( DDR_REG_BASE +0x51eea*4+0x02000000,0xa840); +reg_write( DDR_REG_BASE +0x51eeb*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51eec*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x51eed*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51eee*4+0x02000000,0x194); +reg_write( DDR_REG_BASE +0x51eef*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51ef0*4+0x02000000,0x2600); +reg_write( DDR_REG_BASE +0x51ef1*4+0x02000000,0x32c1); +reg_write( DDR_REG_BASE +0x51ef2*4+0x02000000,0x78d4); +reg_write( DDR_REG_BASE +0x51ef3*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x51ef4*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51ef5*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x51ef6*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x51ef7*4+0x02000000,0xeab); +reg_write( DDR_REG_BASE +0x51ef8*4+0x02000000,0x9214); +reg_write( DDR_REG_BASE +0x51ef9*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x51efa*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x51efb*4+0x02000000,0xe009); +reg_write( DDR_REG_BASE +0x51efc*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x51efd*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51efe*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51eff*4+0x02000000,0x7b1); +reg_write( DDR_REG_BASE +0x51f00*4+0x02000000,0x8824); +reg_write( DDR_REG_BASE +0x51f01*4+0x02000000,0x786f); +reg_write( DDR_REG_BASE +0x51f02*4+0x02000000,0x983); +reg_write( DDR_REG_BASE +0x51f03*4+0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x51f04*4+0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x51f05*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51f06*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51f07*4+0x02000000,0x7b1); +reg_write( DDR_REG_BASE +0x51f08*4+0x02000000,0x88c3); +reg_write( DDR_REG_BASE +0x51f09*4+0x02000000,0x74a5); +reg_write( DDR_REG_BASE +0x51f0a*4+0x02000000,0xe59e); +reg_write( DDR_REG_BASE +0x51f0b*4+0x02000000,0x6ea); +reg_write( DDR_REG_BASE +0x51f0c*4+0x02000000,0xffce); +reg_write( DDR_REG_BASE +0x51f0d*4+0x02000000,0xf036); +reg_write( DDR_REG_BASE +0x51f0e*4+0x02000000,0x255f); +reg_write( DDR_REG_BASE +0x51f0f*4+0x02000000,0x1241); +reg_write( DDR_REG_BASE +0x51f10*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51f11*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x51f12*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51f13*4+0x02000000,0x248); +reg_write( DDR_REG_BASE +0x51f14*4+0x02000000,0x43e1); +reg_write( DDR_REG_BASE +0x51f15*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x51f16*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51f17*4+0x02000000,0x3e); +reg_write( DDR_REG_BASE +0x51f18*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x51f19*4+0x02000000,0xabe); +reg_write( DDR_REG_BASE +0x51f1a*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x51f1b*4+0x02000000,0x60e8); +reg_write( DDR_REG_BASE +0x51f1c*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x51f1d*4+0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x51f1e*4+0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x51f1f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51f20*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x51f21*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x51f22*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x51f23*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x51f24*4+0x02000000,0x3f83); +reg_write( DDR_REG_BASE +0x51f25*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51f26*4+0x02000000,0x194); +reg_write( DDR_REG_BASE +0x51f27*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x51f28*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51f29*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x51f2a*4+0x02000000,0x7a05); +reg_write( DDR_REG_BASE +0x51f2b*4+0x02000000,0x255f); +reg_write( DDR_REG_BASE +0x51f2c*4+0x02000000,0x1480); +reg_write( DDR_REG_BASE +0x51f2d*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x51f2e*4+0x02000000,0x4c); +reg_write( DDR_REG_BASE +0x51f2f*4+0x02000000,0x2142); +reg_write( DDR_REG_BASE +0x51f30*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x51f31*4+0x02000000,0x7945); +reg_write( DDR_REG_BASE +0x51f32*4+0x02000000,0x631b); +reg_write( DDR_REG_BASE +0x51f33*4+0x02000000,0x23f4); +reg_write( DDR_REG_BASE +0x51f34*4+0x02000000,0x3c0); +reg_write( DDR_REG_BASE +0x51f35*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x51f36*4+0x02000000,0x23f4); +reg_write( DDR_REG_BASE +0x51f37*4+0x02000000,0x3c0); +reg_write( DDR_REG_BASE +0x51f38*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x51f39*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x51f3a*4+0x02000000,0xfa9); +reg_write( DDR_REG_BASE +0x51f3b*4+0x02000000,0x9234); +reg_write( DDR_REG_BASE +0x51f3c*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x51f3d*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51f3e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51f3f*4+0x02000000,0x7b1); +reg_write( DDR_REG_BASE +0x51f40*4+0x02000000,0x8824); +reg_write( DDR_REG_BASE +0x51f41*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x51f42*4+0x02000000,0x7dcf); +reg_write( DDR_REG_BASE +0x51f43*4+0x02000000,0x9f1); +reg_write( DDR_REG_BASE +0x51f44*4+0x02000000,0x8365); +reg_write( DDR_REG_BASE +0x51f45*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x51f46*4+0x02000000,0xf3e); +reg_write( DDR_REG_BASE +0x51f47*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51f48*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x51f49*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51f4a*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x51f4b*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x51f4c*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x51f4d*4+0x02000000,0x7d0f); +reg_write( DDR_REG_BASE +0x51f4e*4+0x02000000,0x72b5); +reg_write( DDR_REG_BASE +0x51f4f*4+0x02000000,0x4ca); +reg_write( DDR_REG_BASE +0x51f50*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x51f51*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x51f52*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x51f53*4+0x02000000,0x390a); +reg_write( DDR_REG_BASE +0x51f54*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x51f55*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x51f56*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51f57*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51f58*4+0x02000000,0xc0e6); +reg_write( DDR_REG_BASE +0x51f59*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x51f5a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51f5b*4+0x02000000,0x7b4); +reg_write( DDR_REG_BASE +0x51f5c*4+0x02000000,0x8ba0); +reg_write( DDR_REG_BASE +0x51f5d*4+0x02000000,0x8b81); +reg_write( DDR_REG_BASE +0x51f5e*4+0x02000000,0x251f); +reg_write( DDR_REG_BASE +0x51f5f*4+0x02000000,0x108f); +reg_write( DDR_REG_BASE +0x51f60*4+0x02000000,0xf01b); +reg_write( DDR_REG_BASE +0x51f61*4+0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x51f62*4+0x02000000,0x1f9e); +reg_write( DDR_REG_BASE +0x51f63*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51f64*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x51f65*4+0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x51f66*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x51f67*4+0x02000000,0x2114); +reg_write( DDR_REG_BASE +0x51f68*4+0x02000000,0x38e); +reg_write( DDR_REG_BASE +0x51f69*4+0x02000000,0x2605); +reg_write( DDR_REG_BASE +0x51f6a*4+0x02000000,0x301e); +reg_write( DDR_REG_BASE +0x51f6b*4+0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x51f6c*4+0x02000000,0x783); +reg_write( DDR_REG_BASE +0x51f6d*4+0x02000000,0x7b7b); +reg_write( DDR_REG_BASE +0x51f6e*4+0x02000000,0xbb91); +reg_write( DDR_REG_BASE +0x51f6f*4+0x02000000,0xbb9c); +reg_write( DDR_REG_BASE +0x51f70*4+0x02000000,0xbb9f); +reg_write( DDR_REG_BASE +0x51f71*4+0x02000000,0x9360); +reg_write( DDR_REG_BASE +0x51f72*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x51f73*4+0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x51f74*4+0x02000000,0xb660); +reg_write( DDR_REG_BASE +0x51f75*4+0x02000000,0x232f); +reg_write( DDR_REG_BASE +0x51f76*4+0x02000000,0x2c7); +reg_write( DDR_REG_BASE +0x51f77*4+0x02000000,0xbd7); +reg_write( DDR_REG_BASE +0x51f78*4+0x02000000,0x80a4); +reg_write( DDR_REG_BASE +0x51f79*4+0x02000000,0x7ef0); +reg_write( DDR_REG_BASE +0x51f7a*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x51f7b*4+0x02000000,0xcf7); +reg_write( DDR_REG_BASE +0x51f7c*4+0x02000000,0x9365); +reg_write( DDR_REG_BASE +0x51f7d*4+0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x51f7e*4+0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x51f7f*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51f80*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51f81*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51f82*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51f83*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x51f84*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x51f85*4+0x02000000,0x7b4); +reg_write( DDR_REG_BASE +0x51f86*4+0x02000000,0x8d80); +reg_write( DDR_REG_BASE +0x51f87*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x51f88*4+0x02000000,0x4718); +reg_write( DDR_REG_BASE +0x51f89*4+0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x51f8a*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x51f8b*4+0x02000000,0xea0d); +reg_write( DDR_REG_BASE +0x51f8c*4+0x02000000,0x245f); +reg_write( DDR_REG_BASE +0x51f8d*4+0x02000000,0x1243); +reg_write( DDR_REG_BASE +0x51f8e*4+0x02000000,0xa1b); +reg_write( DDR_REG_BASE +0x51f8f*4+0x02000000,0xb1); +reg_write( DDR_REG_BASE +0x51f90*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x51f91*4+0x02000000,0xe308); +reg_write( DDR_REG_BASE +0x51f92*4+0x02000000,0xd809); +reg_write( DDR_REG_BASE +0x51f93*4+0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x51f94*4+0x02000000,0x234a); +reg_write( DDR_REG_BASE +0x51f95*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x51f96*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x51f97*4+0x02000000,0x7b9b); +reg_write( DDR_REG_BASE +0x51f98*4+0x02000000,0x74ed); +reg_write( DDR_REG_BASE +0x51f99*4+0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x51f9a*4+0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x51f9b*4+0x02000000,0x71ed); +reg_write( DDR_REG_BASE +0x51f9c*4+0x02000000,0x1501); +reg_write( DDR_REG_BASE +0x51f9d*4+0x02000000,0x109e); +reg_write( DDR_REG_BASE +0x51f9e*4+0x02000000,0xf023); +reg_write( DDR_REG_BASE +0x51f9f*4+0x02000000,0x45c9); +reg_write( DDR_REG_BASE +0x51fa0*4+0x02000000,0x259a); +reg_write( DDR_REG_BASE +0x51fa1*4+0x02000000,0x1008); +reg_write( DDR_REG_BASE +0x51fa2*4+0x02000000,0x241a); +reg_write( DDR_REG_BASE +0x51fa3*4+0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x51fa4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x51fa5*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x51fa6*4+0x02000000,0x7aa5); +reg_write( DDR_REG_BASE +0x51fa7*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x51fa8*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x51fa9*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x51faa*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x51fab*4+0x02000000,0xb1f); +reg_write( DDR_REG_BASE +0x51fac*4+0x02000000,0x3030); +reg_write( DDR_REG_BASE +0x51fad*4+0x02000000,0x9a40); +reg_write( DDR_REG_BASE +0x51fae*4+0x02000000,0x258a); +reg_write( DDR_REG_BASE +0x51faf*4+0x02000000,0x1fcf); +reg_write( DDR_REG_BASE +0x51fb0*4+0x02000000,0x7d44); +reg_write( DDR_REG_BASE +0x51fb1*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51fb2*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51fb3*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51fb4*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51fb5*4+0x02000000,0x7a5d); +reg_write( DDR_REG_BASE +0x51fb6*4+0x02000000,0x2284); +reg_write( DDR_REG_BASE +0x51fb7*4+0x02000000,0x81f); +reg_write( DDR_REG_BASE +0x51fb8*4+0x02000000,0x62ba); +reg_write( DDR_REG_BASE +0x51fb9*4+0x02000000,0x2714); +reg_write( DDR_REG_BASE +0x51fba*4+0x02000000,0x30cd); +reg_write( DDR_REG_BASE +0x51fbb*4+0x02000000,0xb540); +reg_write( DDR_REG_BASE +0x51fbc*4+0x02000000,0x66fe); +reg_write( DDR_REG_BASE +0x51fbd*4+0x02000000,0x631b); +reg_write( DDR_REG_BASE +0x51fbe*4+0x02000000,0x9c3); +reg_write( DDR_REG_BASE +0x51fbf*4+0x02000000,0x8385); +reg_write( DDR_REG_BASE +0x51fc0*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x51fc1*4+0x02000000,0xefd); +reg_write( DDR_REG_BASE +0x51fc2*4+0x02000000,0xb325); +reg_write( DDR_REG_BASE +0x51fc3*4+0x02000000,0x4669); +reg_write( DDR_REG_BASE +0x51fc4*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x51fc5*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x51fc6*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x51fc7*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51fc8*4+0x02000000,0x8819); +reg_write( DDR_REG_BASE +0x51fc9*4+0x02000000,0xb863); +reg_write( DDR_REG_BASE +0x51fca*4+0x02000000,0x7314); +reg_write( DDR_REG_BASE +0x51fcb*4+0x02000000,0x20e0); +reg_write( DDR_REG_BASE +0x51fcc*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x51fcd*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x51fce*4+0x02000000,0x900e); +reg_write( DDR_REG_BASE +0x51fcf*4+0x02000000,0x1e4c); +reg_write( DDR_REG_BASE +0x51fd0*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x51fd1*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x51fd2*4+0x02000000,0xb041); +reg_write( DDR_REG_BASE +0x51fd3*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51fd4*4+0x02000000,0x791b); +reg_write( DDR_REG_BASE +0x51fd5*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x51fd6*4+0x02000000,0x2184); +reg_write( DDR_REG_BASE +0x51fd7*4+0x02000000,0xa82); +reg_write( DDR_REG_BASE +0x51fd8*4+0x02000000,0x2046); +reg_write( DDR_REG_BASE +0x51fd9*4+0x02000000,0xa80); +reg_write( DDR_REG_BASE +0x51fda*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x51fdb*4+0x02000000,0x215a); +reg_write( DDR_REG_BASE +0x51fdc*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x51fdd*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x51fde*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x51fdf*4+0x02000000,0x2144); +reg_write( DDR_REG_BASE +0x51fe0*4+0x02000000,0xcc1); +reg_write( DDR_REG_BASE +0x51fe1*4+0x02000000,0x2084); +reg_write( DDR_REG_BASE +0x51fe2*4+0x02000000,0x303); +reg_write( DDR_REG_BASE +0x51fe3*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x51fe4*4+0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x51fe5*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x51fe6*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x51fe7*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x51fe8*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x51fe9*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x51fea*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x51feb*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x51fec*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x51fed*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x51fee*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x51fef*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x51ff0*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x51ff1*4+0x02000000,0xe000); +reg_write( DDR_REG_BASE +0x51ff2*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x51ff3*4+0x02000000,0xe7e); +reg_write( DDR_REG_BASE +0x51ff4*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x51ff5*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x51ff6*4+0x02000000,0x1045); +reg_write( DDR_REG_BASE +0x51ff7*4+0x02000000,0x1d00); +reg_write( DDR_REG_BASE +0x51ff8*4+0x02000000,0x1005); +reg_write( DDR_REG_BASE +0x51ff9*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x51ffa*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x51ffb*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x51ffc*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x51ffd*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x51ffe*4+0x02000000,0x3702); +reg_write( DDR_REG_BASE +0x51fff*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x52000*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52001*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52002*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x52003*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52004*4+0x02000000,0xaa); +reg_write( DDR_REG_BASE +0x52005*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52006*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52007*4+0x02000000,0x57c); +reg_write( DDR_REG_BASE +0x52008*4+0x02000000,0xda78); +reg_write( DDR_REG_BASE +0x52009*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5200a*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5200b*4+0x02000000,0x7085); +reg_write( DDR_REG_BASE +0x5200c*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x5200d*4+0x02000000,0xe0aa); +reg_write( DDR_REG_BASE +0x5200e*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5200f*4+0x02000000,0x709b); +reg_write( DDR_REG_BASE +0x52010*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52011*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52012*4+0x02000000,0x85e); +reg_write( DDR_REG_BASE +0x52013*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52014*4+0x02000000,0xc089); +reg_write( DDR_REG_BASE +0x52015*4+0x02000000,0xc089); +reg_write( DDR_REG_BASE +0x52016*4+0x02000000,0x95e); +reg_write( DDR_REG_BASE +0x52017*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x52018*4+0x02000000,0xd978); +reg_write( DDR_REG_BASE +0x52019*4+0x02000000,0xa4a); +reg_write( DDR_REG_BASE +0x5201a*4+0x02000000,0xfe8f); +reg_write( DDR_REG_BASE +0x5201b*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x5201c*4+0x02000000,0xf86); +reg_write( DDR_REG_BASE +0x5201d*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x5201e*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x5201f*4+0x02000000,0xdde); +reg_write( DDR_REG_BASE +0x52020*4+0x02000000,0xff4f); +reg_write( DDR_REG_BASE +0x52021*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52022*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52023*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52024*4+0x02000000,0xe024); +reg_write( DDR_REG_BASE +0x52025*4+0x02000000,0x228a); +reg_write( DDR_REG_BASE +0x52026*4+0x02000000,0x44); +reg_write( DDR_REG_BASE +0x52027*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x52028*4+0x02000000,0xb026); +reg_write( DDR_REG_BASE +0x52029*4+0x02000000,0x18fe); +reg_write( DDR_REG_BASE +0x5202a*4+0x02000000,0x8084); +reg_write( DDR_REG_BASE +0x5202b*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x5202c*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x5202d*4+0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x5202e*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x5202f*4+0x02000000,0xea06); +reg_write( DDR_REG_BASE +0x52030*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x52031*4+0x02000000,0xa01); +reg_write( DDR_REG_BASE +0x52032*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x52033*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52034*4+0x02000000,0x7d0f); +reg_write( DDR_REG_BASE +0x52035*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x52036*4+0x02000000,0xc62); +reg_write( DDR_REG_BASE +0x52037*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x52038*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52039*4+0x02000000,0xd830); +reg_write( DDR_REG_BASE +0x5203a*4+0x02000000,0xc36); +reg_write( DDR_REG_BASE +0x5203b*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x5203c*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5203d*4+0x02000000,0xa76); +reg_write( DDR_REG_BASE +0x5203e*4+0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x5203f*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52040*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x52041*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x52042*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x52043*4+0x02000000,0xfc3); +reg_write( DDR_REG_BASE +0x52044*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52045*4+0x02000000,0x8fb); +reg_write( DDR_REG_BASE +0x52046*4+0x02000000,0x8534); +reg_write( DDR_REG_BASE +0x52047*4+0x02000000,0xc184); +reg_write( DDR_REG_BASE +0x52048*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52049*4+0x02000000,0xc1a); +reg_write( DDR_REG_BASE +0x5204a*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x5204b*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5204c*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x5204d*4+0x02000000,0xf26); +reg_write( DDR_REG_BASE +0x5204e*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x5204f*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52050*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x52051*4+0x02000000,0xc2e); +reg_write( DDR_REG_BASE +0x52052*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x52053*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52054*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x52055*4+0x02000000,0x3f9b); +reg_write( DDR_REG_BASE +0x52056*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52057*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52058*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x52059*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x5205a*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x5205b*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5205c*4+0x02000000,0xe174); +reg_write( DDR_REG_BASE +0x5205d*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x5205e*4+0x02000000,0x45cb); +reg_write( DDR_REG_BASE +0x5205f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52060*4+0x02000000,0x7b2); +reg_write( DDR_REG_BASE +0x52061*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x52062*4+0x02000000,0xb601); +reg_write( DDR_REG_BASE +0x52063*4+0x02000000,0x1e59); +reg_write( DDR_REG_BASE +0x52064*4+0x02000000,0x93dc); +reg_write( DDR_REG_BASE +0x52065*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x52066*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52067*4+0x02000000,0xf7f); +reg_write( DDR_REG_BASE +0x52068*4+0x02000000,0x1a35); +reg_write( DDR_REG_BASE +0x52069*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5206a*4+0x02000000,0xbd6); +reg_write( DDR_REG_BASE +0x5206b*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x5206c*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5206d*4+0x02000000,0x1501); +reg_write( DDR_REG_BASE +0x5206e*4+0x02000000,0x108b); +reg_write( DDR_REG_BASE +0x5206f*4+0x02000000,0x8d80); +reg_write( DDR_REG_BASE +0x52070*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x52071*4+0x02000000,0xf02b); +reg_write( DDR_REG_BASE +0x52072*4+0x02000000,0x241a); +reg_write( DDR_REG_BASE +0x52073*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x52074*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52075*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52076*4+0x02000000,0x206c); +reg_write( DDR_REG_BASE +0x52077*4+0x02000000,0x302); +reg_write( DDR_REG_BASE +0x52078*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x52079*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5207a*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x5207b*4+0x02000000,0x166); +reg_write( DDR_REG_BASE +0x5207c*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x5207d*4+0x02000000,0x2079); +reg_write( DDR_REG_BASE +0x5207e*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x5207f*4+0x02000000,0xc084); +reg_write( DDR_REG_BASE +0x52080*4+0x02000000,0x6098); +reg_write( DDR_REG_BASE +0x52081*4+0x02000000,0x8820); +reg_write( DDR_REG_BASE +0x52082*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x52083*4+0x02000000,0x7965); +reg_write( DDR_REG_BASE +0x52084*4+0x02000000,0xa820); +reg_write( DDR_REG_BASE +0x52085*4+0x02000000,0x241a); +reg_write( DDR_REG_BASE +0x52086*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x52087*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52088*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x52089*4+0x02000000,0x2153); +reg_write( DDR_REG_BASE +0x5208a*4+0x02000000,0x80be); +reg_write( DDR_REG_BASE +0x5208b*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x5208c*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5208d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5208e*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x5208f*4+0x02000000,0x7a05); +reg_write( DDR_REG_BASE +0x52090*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x52091*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x52092*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52093*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x52094*4+0x02000000,0x9200); +reg_write( DDR_REG_BASE +0x52095*4+0x02000000,0xf206); +reg_write( DDR_REG_BASE +0x52096*4+0x02000000,0x2080); +reg_write( DDR_REG_BASE +0x52097*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52098*4+0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x52099*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x5209a*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x5209b*4+0x02000000,0xbb1); +reg_write( DDR_REG_BASE +0x5209c*4+0x02000000,0x9325); +reg_write( DDR_REG_BASE +0x5209d*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x5209e*4+0x02000000,0xe82); +reg_write( DDR_REG_BASE +0x5209f*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x520a0*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x520a1*4+0x02000000,0xb8f); +reg_write( DDR_REG_BASE +0x520a2*4+0x02000000,0xb031); +reg_write( DDR_REG_BASE +0x520a3*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x520a4*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x520a5*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x520a6*4+0x02000000,0x6e); +reg_write( DDR_REG_BASE +0x520a7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x520a8*4+0x02000000,0xf9e); +reg_write( DDR_REG_BASE +0x520a9*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x520aa*4+0x02000000,0x2378); +reg_write( DDR_REG_BASE +0x520ab*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x520ac*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x520ad*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x520ae*4+0x02000000,0x992); +reg_write( DDR_REG_BASE +0x520af*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x520b0*4+0x02000000,0xb601); +reg_write( DDR_REG_BASE +0x520b1*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x520b2*4+0x02000000,0x92e); +reg_write( DDR_REG_BASE +0x520b3*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x520b4*4+0x02000000,0x732c); +reg_write( DDR_REG_BASE +0x520b5*4+0x02000000,0xd820); +reg_write( DDR_REG_BASE +0x520b6*4+0x02000000,0xb3e); +reg_write( DDR_REG_BASE +0x520b7*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x520b8*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x520b9*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x520ba*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x520bb*4+0x02000000,0xd8e); +reg_write( DDR_REG_BASE +0x520bc*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x520bd*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x520be*4+0x02000000,0x8d61); +reg_write( DDR_REG_BASE +0x520bf*4+0x02000000,0x8d20); +reg_write( DDR_REG_BASE +0x520c0*4+0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x520c1*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x520c2*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x520c3*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x520c4*4+0x02000000,0x2042); +reg_write( DDR_REG_BASE +0x520c5*4+0x02000000,0x802); +reg_write( DDR_REG_BASE +0x520c6*4+0x02000000,0xc000); +reg_write( DDR_REG_BASE +0x520c7*4+0x02000000,0x7834); +reg_write( DDR_REG_BASE +0x520c8*4+0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x520c9*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x520ca*4+0x02000000,0xbef); +reg_write( DDR_REG_BASE +0x520cb*4+0x02000000,0x8045); +reg_write( DDR_REG_BASE +0x520cc*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x520cd*4+0x02000000,0xe72); +reg_write( DDR_REG_BASE +0x520ce*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x520cf*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x520d0*4+0x02000000,0xc103); +reg_write( DDR_REG_BASE +0x520d1*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x520d2*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x520d3*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x520d4*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x520d5*4+0x02000000,0xc100); +reg_write( DDR_REG_BASE +0x520d6*4+0x02000000,0x83a); +reg_write( DDR_REG_BASE +0x520d7*4+0x02000000,0xe0); +reg_write( DDR_REG_BASE +0x520d8*4+0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x520d9*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x520da*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x520db*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x520dc*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x520dd*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x520de*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x520df*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x520e0*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x520e1*4+0x02000000,0xe076); +reg_write( DDR_REG_BASE +0x520e2*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x520e3*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x520e4*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x520e5*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x520e6*4+0x02000000,0xe0aa); +reg_write( DDR_REG_BASE +0x520e7*4+0x02000000,0xe12); +reg_write( DDR_REG_BASE +0x520e8*4+0x02000000,0xffcf); +reg_write( DDR_REG_BASE +0x520e9*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x520ea*4+0x02000000,0x3702); +reg_write( DDR_REG_BASE +0x520eb*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x520ec*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x520ed*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x520ee*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x520ef*4+0x02000000,0xcb2); +reg_write( DDR_REG_BASE +0x520f0*4+0x02000000,0xfe8f); +reg_write( DDR_REG_BASE +0x520f1*4+0x02000000,0x256f); +reg_write( DDR_REG_BASE +0x520f2*4+0x02000000,0x1343); +reg_write( DDR_REG_BASE +0x520f3*4+0x02000000,0x9560); +reg_write( DDR_REG_BASE +0x520f4*4+0x02000000,0xda20); +reg_write( DDR_REG_BASE +0x520f5*4+0x02000000,0xd940); +reg_write( DDR_REG_BASE +0x520f6*4+0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x520f7*4+0x02000000,0x85ca); +reg_write( DDR_REG_BASE +0x520f8*4+0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x520f9*4+0x02000000,0xc2d); +reg_write( DDR_REG_BASE +0x520fa*4+0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x520fb*4+0x02000000,0x89d0); +reg_write( DDR_REG_BASE +0x520fc*4+0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x520fd*4+0x02000000,0x4d); +reg_write( DDR_REG_BASE +0x520fe*4+0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x520ff*4+0x02000000,0x8fd8); +reg_write( DDR_REG_BASE +0x52100*4+0x02000000,0xd950); +reg_write( DDR_REG_BASE +0x52101*4+0x02000000,0x22ca); +reg_write( DDR_REG_BASE +0x52102*4+0x02000000,0x4d); +reg_write( DDR_REG_BASE +0x52103*4+0x02000000,0x218a); +reg_write( DDR_REG_BASE +0x52104*4+0x02000000,0x5ca); +reg_write( DDR_REG_BASE +0x52105*4+0x02000000,0x213c); +reg_write( DDR_REG_BASE +0x52106*4+0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x52107*4+0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x52108*4+0x02000000,0x89d0); +reg_write( DDR_REG_BASE +0x52109*4+0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x5210a*4+0x02000000,0xad); +reg_write( DDR_REG_BASE +0x5210b*4+0x02000000,0x238c); +reg_write( DDR_REG_BASE +0x5210c*4+0x02000000,0x8fd8); +reg_write( DDR_REG_BASE +0x5210d*4+0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x5210e*4+0x02000000,0xed); +reg_write( DDR_REG_BASE +0x5210f*4+0x02000000,0x73d3); +reg_write( DDR_REG_BASE +0x52110*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52111*4+0x02000000,0x95f); +reg_write( DDR_REG_BASE +0x52112*4+0x02000000,0x21ca); +reg_write( DDR_REG_BASE +0x52113*4+0x02000000,0x12d); +reg_write( DDR_REG_BASE +0x52114*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x52115*4+0x02000000,0x8c); +reg_write( DDR_REG_BASE +0x52116*4+0x02000000,0x15fe); +reg_write( DDR_REG_BASE +0x52117*4+0x02000000,0x9081); +reg_write( DDR_REG_BASE +0x52118*4+0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x52119*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x5211a*4+0x02000000,0x211a); +reg_write( DDR_REG_BASE +0x5211b*4+0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x5211c*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5211d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5211e*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5211f*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52120*4+0x02000000,0xf8); +reg_write( DDR_REG_BASE +0x52121*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52122*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52123*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52124*4+0x02000000,0x1ff0); +reg_write( DDR_REG_BASE +0x52125*4+0x02000000,0xb881); +reg_write( DDR_REG_BASE +0x52126*4+0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x52127*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x52128*4+0x02000000,0x7224); +reg_write( DDR_REG_BASE +0x52129*4+0x02000000,0x7965); +reg_write( DDR_REG_BASE +0x5212a*4+0x02000000,0xb280); +reg_write( DDR_REG_BASE +0x5212b*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x5212c*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x5212d*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x5212e*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x5212f*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52130*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x52131*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52132*4+0x02000000,0x1ea); +reg_write( DDR_REG_BASE +0x52133*4+0x02000000,0x9340); +reg_write( DDR_REG_BASE +0x52134*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52135*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52136*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52137*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52138*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52139*4+0x02000000,0xfb00); +reg_write( DDR_REG_BASE +0x5213a*4+0x02000000,0x2204); +reg_write( DDR_REG_BASE +0x5213b*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x5213c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5213d*4+0x02000000,0xc0ff); +reg_write( DDR_REG_BASE +0x5213e*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x5213f*4+0x02000000,0x9341); +reg_write( DDR_REG_BASE +0x52140*4+0x02000000,0xb300); +reg_write( DDR_REG_BASE +0x52141*4+0x02000000,0xb965); +reg_write( DDR_REG_BASE +0x52142*4+0x02000000,0x226c); +reg_write( DDR_REG_BASE +0x52143*4+0x02000000,0x140); +reg_write( DDR_REG_BASE +0x52144*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52145*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x52146*4+0x02000000,0xb301); +reg_write( DDR_REG_BASE +0x52147*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52148*4+0x02000000,0x7a1b); +reg_write( DDR_REG_BASE +0x52149*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x5214a*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x5214b*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5214c*4+0x02000000,0xe164); +reg_write( DDR_REG_BASE +0x5214d*4+0x02000000,0x1a00); +reg_write( DDR_REG_BASE +0x5214e*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x5214f*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x52150*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52151*4+0x02000000,0x7b4); +reg_write( DDR_REG_BASE +0x52152*4+0x02000000,0x8a61); +reg_write( DDR_REG_BASE +0x52153*4+0x02000000,0x8a80); +reg_write( DDR_REG_BASE +0x52154*4+0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x52155*4+0x02000000,0x241a); +reg_write( DDR_REG_BASE +0x52156*4+0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x52157*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52158*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52159*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x5215a*4+0x02000000,0x7a05); +reg_write( DDR_REG_BASE +0x5215b*4+0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x5215c*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x5215d*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x5215e*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x5215f*4+0x02000000,0x164); +reg_write( DDR_REG_BASE +0x52160*4+0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x52161*4+0x02000000,0xbeb); +reg_write( DDR_REG_BASE +0x52162*4+0x02000000,0x8305); +reg_write( DDR_REG_BASE +0x52163*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52164*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52165*4+0x02000000,0x266f); +reg_write( DDR_REG_BASE +0x52166*4+0x02000000,0x15c3); +reg_write( DDR_REG_BASE +0x52167*4+0x02000000,0x8e40); +reg_write( DDR_REG_BASE +0x52168*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x52169*4+0x02000000,0xea17); +reg_write( DDR_REG_BASE +0x5216a*4+0x02000000,0xede); +reg_write( DDR_REG_BASE +0x5216b*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5216c*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x5216d*4+0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x5216e*4+0x02000000,0xe887); +reg_write( DDR_REG_BASE +0x5216f*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52170*4+0x02000000,0xd6); +reg_write( DDR_REG_BASE +0x52171*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52172*4+0x02000000,0xe0a); +reg_write( DDR_REG_BASE +0x52173*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52174*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52175*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x52176*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52177*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52178*4+0x02000000,0x7f05); +reg_write( DDR_REG_BASE +0x52179*4+0x02000000,0x78bb); +reg_write( DDR_REG_BASE +0x5217a*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5217b*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5217c*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5217d*4+0x02000000,0xfe92); +reg_write( DDR_REG_BASE +0x5217e*4+0x02000000,0xb0e0); +reg_write( DDR_REG_BASE +0x5217f*4+0x02000000,0x16ff); +reg_write( DDR_REG_BASE +0x52180*4+0x02000000,0x9082); +reg_write( DDR_REG_BASE +0x52181*4+0x02000000,0xea16); +reg_write( DDR_REG_BASE +0x52182*4+0x02000000,0xeae); +reg_write( DDR_REG_BASE +0x52183*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x52184*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x52185*4+0x02000000,0x228c); +reg_write( DDR_REG_BASE +0x52186*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x52187*4+0x02000000,0xf209); +reg_write( DDR_REG_BASE +0x52188*4+0x02000000,0xe888); +reg_write( DDR_REG_BASE +0x52189*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5218a*4+0x02000000,0xd7); +reg_write( DDR_REG_BASE +0x5218b*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5218c*4+0x02000000,0xdd6); +reg_write( DDR_REG_BASE +0x5218d*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5218e*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5218f*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52190*4+0x02000000,0x79bb); +reg_write( DDR_REG_BASE +0x52191*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x52192*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52193*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52194*4+0x02000000,0xfe9a); +reg_write( DDR_REG_BASE +0x52195*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x52196*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52197*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52198*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x52199*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5219a*4+0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x5219b*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5219c*4+0x02000000,0x9); +reg_write( DDR_REG_BASE +0x5219d*4+0x02000000,0xea1a); +reg_write( DDR_REG_BASE +0x5219e*4+0x02000000,0xa23); +reg_write( DDR_REG_BASE +0x5219f*4+0x02000000,0xa30); +reg_write( DDR_REG_BASE +0x521a0*4+0x02000000,0x720c); +reg_write( DDR_REG_BASE +0x521a1*4+0x02000000,0x228c); +reg_write( DDR_REG_BASE +0x521a2*4+0x02000000,0x8c03); +reg_write( DDR_REG_BASE +0x521a3*4+0x02000000,0xf20c); +reg_write( DDR_REG_BASE +0x521a4*4+0x02000000,0xe2f8); +reg_write( DDR_REG_BASE +0x521a5*4+0x02000000,0xf404); +reg_write( DDR_REG_BASE +0x521a6*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x521a7*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x521a8*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x521a9*4+0x02000000,0xd8); +reg_write( DDR_REG_BASE +0x521aa*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x521ab*4+0x02000000,0xd9a); +reg_write( DDR_REG_BASE +0x521ac*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x521ad*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x521ae*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x521af*4+0x02000000,0x205f); +reg_write( DDR_REG_BASE +0x521b0*4+0x02000000,0x401); +reg_write( DDR_REG_BASE +0x521b1*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x521b2*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x521b3*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x521b4*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x521b5*4+0x02000000,0xe0a0); +reg_write( DDR_REG_BASE +0x521b6*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x521b7*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x521b8*4+0x02000000,0xc0e2); +reg_write( DDR_REG_BASE +0x521b9*4+0x02000000,0x706d); +reg_write( DDR_REG_BASE +0x521ba*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x521bb*4+0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x521bc*4+0x02000000,0x901); +reg_write( DDR_REG_BASE +0x521bd*4+0x02000000,0x607d); +reg_write( DDR_REG_BASE +0x521be*4+0x02000000,0x245a); +reg_write( DDR_REG_BASE +0x521bf*4+0x02000000,0x1c83); +reg_write( DDR_REG_BASE +0x521c0*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x521c1*4+0x02000000,0x63bb); +reg_write( DDR_REG_BASE +0x521c2*4+0x02000000,0x633b); +reg_write( DDR_REG_BASE +0x521c3*4+0x02000000,0xab40); +reg_write( DDR_REG_BASE +0x521c4*4+0x02000000,0xcef); +reg_write( DDR_REG_BASE +0x521c5*4+0x02000000,0x90b4); +reg_write( DDR_REG_BASE +0x521c6*4+0x02000000,0x4361); +reg_write( DDR_REG_BASE +0x521c7*4+0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x521c8*4+0x02000000,0xbf9); +reg_write( DDR_REG_BASE +0x521c9*4+0x02000000,0x90b4); +reg_write( DDR_REG_BASE +0x521ca*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x521cb*4+0x02000000,0xc4c2); +reg_write( DDR_REG_BASE +0x521cc*4+0x02000000,0xc0e6); +reg_write( DDR_REG_BASE +0x521cd*4+0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x521ce*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x521cf*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x521d0*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x521d1*4+0x02000000,0xff64); +reg_write( DDR_REG_BASE +0x521d2*4+0x02000000,0xb1e0); +reg_write( DDR_REG_BASE +0x521d3*4+0x02000000,0x1904); +reg_write( DDR_REG_BASE +0x521d4*4+0x02000000,0x45); +reg_write( DDR_REG_BASE +0x521d5*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x521d6*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x521d7*4+0x02000000,0x7b4); +reg_write( DDR_REG_BASE +0x521d8*4+0x02000000,0x8a21); +reg_write( DDR_REG_BASE +0x521d9*4+0x02000000,0x8ac0); +reg_write( DDR_REG_BASE +0x521da*4+0x02000000,0xf03b); +reg_write( DDR_REG_BASE +0x521db*4+0x02000000,0x228c); +reg_write( DDR_REG_BASE +0x521dc*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x521dd*4+0x02000000,0xf41a); +reg_write( DDR_REG_BASE +0x521de*4+0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x521df*4+0x02000000,0x1f83); +reg_write( DDR_REG_BASE +0x521e0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x521e1*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x521e2*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x521e3*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x521e4*4+0x02000000,0x1f64); +reg_write( DDR_REG_BASE +0x521e5*4+0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x521e6*4+0x02000000,0x8c); +reg_write( DDR_REG_BASE +0x521e7*4+0x02000000,0x7444); +reg_write( DDR_REG_BASE +0x521e8*4+0x02000000,0x7a65); +reg_write( DDR_REG_BASE +0x521e9*4+0x02000000,0xb400); +reg_write( DDR_REG_BASE +0x521ea*4+0x02000000,0xb2e0); +reg_write( DDR_REG_BASE +0x521eb*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x521ec*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x521ed*4+0x02000000,0x1164); +reg_write( DDR_REG_BASE +0x521ee*4+0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x521ef*4+0x02000000,0x8c); +reg_write( DDR_REG_BASE +0x521f0*4+0x02000000,0x7444); +reg_write( DDR_REG_BASE +0x521f1*4+0x02000000,0x7a65); +reg_write( DDR_REG_BASE +0x521f2*4+0x02000000,0xb4e0); +reg_write( DDR_REG_BASE +0x521f3*4+0x02000000,0x1a00); +reg_write( DDR_REG_BASE +0x521f4*4+0x02000000,0x45); +reg_write( DDR_REG_BASE +0x521f5*4+0x02000000,0xf020); +reg_write( DDR_REG_BASE +0x521f6*4+0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x521f7*4+0x02000000,0x32c0); +reg_write( DDR_REG_BASE +0x521f8*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x521f9*4+0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x521fa*4+0x02000000,0xf753); +reg_write( DDR_REG_BASE +0x521fb*4+0x02000000,0x4381); +reg_write( DDR_REG_BASE +0x521fc*4+0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x521fd*4+0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x521fe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x521ff*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52200*4+0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x52201*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x52202*4+0x02000000,0x7b45); +reg_write( DDR_REG_BASE +0x52203*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x52204*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52205*4+0x02000000,0x164); +reg_write( DDR_REG_BASE +0x52206*4+0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x52207*4+0x02000000,0x8d); +reg_write( DDR_REG_BASE +0x52208*4+0x02000000,0x7444); +reg_write( DDR_REG_BASE +0x52209*4+0x02000000,0x7b45); +reg_write( DDR_REG_BASE +0x5220a*4+0x02000000,0xb500); +reg_write( DDR_REG_BASE +0x5220b*4+0x02000000,0x1b00); +reg_write( DDR_REG_BASE +0x5220c*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x5220d*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x5220e*4+0x02000000,0xe0d); +reg_write( DDR_REG_BASE +0x5220f*4+0x02000000,0x3010); +reg_write( DDR_REG_BASE +0x52210*4+0x02000000,0xcd5); +reg_write( DDR_REG_BASE +0x52211*4+0x02000000,0x9274); +reg_write( DDR_REG_BASE +0x52212*4+0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x52213*4+0x02000000,0xb782); +reg_write( DDR_REG_BASE +0x52214*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x52215*4+0x02000000,0x98f); +reg_write( DDR_REG_BASE +0x52216*4+0x02000000,0x83a5); +reg_write( DDR_REG_BASE +0x52217*4+0x02000000,0x222f); +reg_write( DDR_REG_BASE +0x52218*4+0x02000000,0x2c7); +reg_write( DDR_REG_BASE +0x52219*4+0x02000000,0xc4c6); +reg_write( DDR_REG_BASE +0x5221a*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5221b*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x5221c*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x5221d*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5221e*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5221f*4+0x02000000,0x30); +reg_write( DDR_REG_BASE +0x52220*4+0x02000000,0x10b4); +reg_write( DDR_REG_BASE +0x52221*4+0x02000000,0x501); +reg_write( DDR_REG_BASE +0x52222*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52223*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x52224*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52225*4+0x02000000,0x23); +reg_write( DDR_REG_BASE +0x52226*4+0x02000000,0x90b); +reg_write( DDR_REG_BASE +0x52227*4+0x02000000,0x171); +reg_write( DDR_REG_BASE +0x52228*4+0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x52229*4+0x02000000,0xb0a1); +reg_write( DDR_REG_BASE +0x5222a*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x5222b*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5222c*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x5222d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5222e*4+0x02000000,0x49); +reg_write( DDR_REG_BASE +0x5222f*4+0x02000000,0xb021); +reg_write( DDR_REG_BASE +0x52230*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x52231*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52232*4+0x02000000,0x7b6); +reg_write( DDR_REG_BASE +0x52233*4+0x02000000,0xed21); +reg_write( DDR_REG_BASE +0x52234*4+0x02000000,0x8ee0); +reg_write( DDR_REG_BASE +0x52235*4+0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x52236*4+0x02000000,0x108b); +reg_write( DDR_REG_BASE +0x52237*4+0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x52238*4+0x02000000,0x105b); +reg_write( DDR_REG_BASE +0x52239*4+0x02000000,0xf017); +reg_write( DDR_REG_BASE +0x5223a*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x5223b*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5223c*4+0x02000000,0x2553); +reg_write( DDR_REG_BASE +0x5223d*4+0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x5223e*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x5223f*4+0x02000000,0x4061); +reg_write( DDR_REG_BASE +0x52240*4+0x02000000,0xf82d); +reg_write( DDR_REG_BASE +0x52241*4+0x02000000,0xb11); +reg_write( DDR_REG_BASE +0x52242*4+0x02000000,0x3030); +reg_write( DDR_REG_BASE +0x52243*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x52244*4+0x02000000,0x79ef); +reg_write( DDR_REG_BASE +0x52245*4+0x02000000,0x95e); +reg_write( DDR_REG_BASE +0x52246*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52247*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52248*4+0x02000000,0xb0d); +reg_write( DDR_REG_BASE +0x52249*4+0x02000000,0x1030); +reg_write( DDR_REG_BASE +0x5224a*4+0x02000000,0x79ef); +reg_write( DDR_REG_BASE +0x5224b*4+0x02000000,0x952); +reg_write( DDR_REG_BASE +0x5224c*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x5224d*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5224e*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x5224f*4+0x02000000,0x8e01); +reg_write( DDR_REG_BASE +0x52250*4+0x02000000,0x8d5); +reg_write( DDR_REG_BASE +0x52251*4+0x02000000,0x83e5); +reg_write( DDR_REG_BASE +0x52252*4+0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x52253*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52254*4+0x02000000,0x708b); +reg_write( DDR_REG_BASE +0x52255*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52256*4+0x02000000,0x49); +reg_write( DDR_REG_BASE +0x52257*4+0x02000000,0xb43); +reg_write( DDR_REG_BASE +0x52258*4+0x02000000,0x1030); +reg_write( DDR_REG_BASE +0x52259*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x5225a*4+0x02000000,0x109b); +reg_write( DDR_REG_BASE +0x5225b*4+0x02000000,0x8ee2); +reg_write( DDR_REG_BASE +0x5225c*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x5225d*4+0x02000000,0x104d); +reg_write( DDR_REG_BASE +0x5225e*4+0x02000000,0xf015); +reg_write( DDR_REG_BASE +0x5225f*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52260*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52261*4+0x02000000,0x2353); +reg_write( DDR_REG_BASE +0x52262*4+0x02000000,0x1041); +reg_write( DDR_REG_BASE +0x52263*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x52264*4+0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x52265*4+0x02000000,0xf81b); +reg_write( DDR_REG_BASE +0x52266*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x52267*4+0x02000000,0xed06); +reg_write( DDR_REG_BASE +0x52268*4+0x02000000,0x79ef); +reg_write( DDR_REG_BASE +0x52269*4+0x02000000,0x916); +reg_write( DDR_REG_BASE +0x5226a*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x5226b*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5226c*4+0x02000000,0xb0d); +reg_write( DDR_REG_BASE +0x5226d*4+0x02000000,0x3030); +reg_write( DDR_REG_BASE +0x5226e*4+0x02000000,0x79ef); +reg_write( DDR_REG_BASE +0x5226f*4+0x02000000,0x90a); +reg_write( DDR_REG_BASE +0x52270*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x52271*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52272*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x52273*4+0x02000000,0x8e03); +reg_write( DDR_REG_BASE +0x52274*4+0x02000000,0x8d7); +reg_write( DDR_REG_BASE +0x52275*4+0x02000000,0x83e5); +reg_write( DDR_REG_BASE +0x52276*4+0x02000000,0x40a1); +reg_write( DDR_REG_BASE +0x52277*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x52278*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52279*4+0x02000000,0x1ea); +reg_write( DDR_REG_BASE +0x5227a*4+0x02000000,0x9300); +reg_write( DDR_REG_BASE +0x5227b*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x5227c*4+0x02000000,0x9012); +reg_write( DDR_REG_BASE +0x5227d*4+0x02000000,0x402); +reg_write( DDR_REG_BASE +0x5227e*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x5227f*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52280*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52281*4+0x02000000,0x3f00); +reg_write( DDR_REG_BASE +0x52282*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52283*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x52284*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52285*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52286*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x52287*4+0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x52288*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52289*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5228a*4+0x02000000,0x2405); +reg_write( DDR_REG_BASE +0x5228b*4+0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x5228c*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x5228d*4+0x02000000,0x6a04); +reg_write( DDR_REG_BASE +0x5228e*4+0x02000000,0x2196); +reg_write( DDR_REG_BASE +0x5228f*4+0x02000000,0x6); +reg_write( DDR_REG_BASE +0x52290*4+0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x52291*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x52292*4+0x02000000,0x9321); +reg_write( DDR_REG_BASE +0x52293*4+0x02000000,0x6a02); +reg_write( DDR_REG_BASE +0x52294*4+0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x52295*4+0x02000000,0xb9c5); +reg_write( DDR_REG_BASE +0x52296*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x52297*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52298*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52299*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5229a*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x5229b*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5229c*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x5229d*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x5229e*4+0x02000000,0x271a); +reg_write( DDR_REG_BASE +0x5229f*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x522a0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x522a1*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x522a2*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x522a3*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x522a4*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x522a5*4+0x02000000,0x154); +reg_write( DDR_REG_BASE +0x522a6*4+0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x522a7*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x522a8*4+0x02000000,0xb88a); +reg_write( DDR_REG_BASE +0x522a9*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x522aa*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x522ab*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x522ac*4+0x02000000,0x110); +reg_write( DDR_REG_BASE +0x522ad*4+0x02000000,0x9200); +reg_write( DDR_REG_BASE +0x522ae*4+0x02000000,0x204f); +reg_write( DDR_REG_BASE +0x522af*4+0x02000000,0x101); +reg_write( DDR_REG_BASE +0x522b0*4+0x02000000,0xb8a4); +reg_write( DDR_REG_BASE +0x522b1*4+0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x522b2*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x522b3*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x522b4*4+0x02000000,0x2032); +reg_write( DDR_REG_BASE +0x522b5*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x522b6*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x522b7*4+0x02000000,0x18); +reg_write( DDR_REG_BASE +0x522b8*4+0x02000000,0xb9e7); +reg_write( DDR_REG_BASE +0x522b9*4+0x02000000,0x7ce0); +reg_write( DDR_REG_BASE +0x522ba*4+0x02000000,0xb9c6); +reg_write( DDR_REG_BASE +0x522bb*4+0x02000000,0x7fe0); +reg_write( DDR_REG_BASE +0x522bc*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x522bd*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x522be*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x522bf*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x522c0*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x522c1*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x522c2*4+0x02000000,0x3409); +reg_write( DDR_REG_BASE +0x522c3*4+0x02000000,0x216f); +reg_write( DDR_REG_BASE +0x522c4*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x522c5*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x522c6*4+0x02000000,0x8900); +reg_write( DDR_REG_BASE +0x522c7*4+0x02000000,0x11fd); +reg_write( DDR_REG_BASE +0x522c8*4+0x02000000,0x808f); +reg_write( DDR_REG_BASE +0x522c9*4+0x02000000,0x1145); +reg_write( DDR_REG_BASE +0x522ca*4+0x02000000,0x83); +reg_write( DDR_REG_BASE +0x522cb*4+0x02000000,0x89df); +reg_write( DDR_REG_BASE +0x522cc*4+0x02000000,0x1209); +reg_write( DDR_REG_BASE +0x522cd*4+0x02000000,0x309e); +reg_write( DDR_REG_BASE +0x522ce*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x522cf*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x522d0*4+0x02000000,0x3e80); +reg_write( DDR_REG_BASE +0x522d1*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x522d2*4+0x02000000,0xaee); +reg_write( DDR_REG_BASE +0x522d3*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x522d4*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x522d5*4+0x02000000,0xc08d); +reg_write( DDR_REG_BASE +0x522d6*4+0x02000000,0xae6); +reg_write( DDR_REG_BASE +0x522d7*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x522d8*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x522d9*4+0x02000000,0x2578); +reg_write( DDR_REG_BASE +0x522da*4+0x02000000,0x1140); +reg_write( DDR_REG_BASE +0x522db*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x522dc*4+0x02000000,0x254f); +reg_write( DDR_REG_BASE +0x522dd*4+0x02000000,0x1080); +reg_write( DDR_REG_BASE +0x522de*4+0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x522df*4+0x02000000,0x101); +reg_write( DDR_REG_BASE +0x522e0*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x522e1*4+0x02000000,0xbfe2); +reg_write( DDR_REG_BASE +0x522e2*4+0x02000000,0x7bc5); +reg_write( DDR_REG_BASE +0x522e3*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x522e4*4+0x02000000,0x2578); +reg_write( DDR_REG_BASE +0x522e5*4+0x02000000,0x10c0); +reg_write( DDR_REG_BASE +0x522e6*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x522e7*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x522e8*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x522e9*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x522ea*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x522eb*4+0x02000000,0x3e1); +reg_write( DDR_REG_BASE +0x522ec*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x522ed*4+0x02000000,0x2579); +reg_write( DDR_REG_BASE +0x522ee*4+0x02000000,0x1180); +reg_write( DDR_REG_BASE +0x522ef*4+0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x522f0*4+0x02000000,0x2542); +reg_write( DDR_REG_BASE +0x522f1*4+0x02000000,0x1240); +reg_write( DDR_REG_BASE +0x522f2*4+0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x522f3*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x522f4*4+0x02000000,0x2678); +reg_write( DDR_REG_BASE +0x522f5*4+0x02000000,0x301b); +reg_write( DDR_REG_BASE +0x522f6*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x522f7*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x522f8*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x522f9*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x522fa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x522fb*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x522fc*4+0x02000000,0xc34a); +reg_write( DDR_REG_BASE +0x522fd*4+0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x522fe*4+0x02000000,0xf0a5); +reg_write( DDR_REG_BASE +0x522ff*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x52300*4+0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x52301*4+0x02000000,0x17c0); +reg_write( DDR_REG_BASE +0x52302*4+0x02000000,0xc107); +reg_write( DDR_REG_BASE +0x52303*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x52304*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x52305*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x52306*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x52307*4+0x02000000,0x7b7b); +reg_write( DDR_REG_BASE +0x52308*4+0x02000000,0x9fa); +reg_write( DDR_REG_BASE +0x52309*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x5230a*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x5230b*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5230c*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x5230d*4+0x02000000,0x7b0b); +reg_write( DDR_REG_BASE +0x5230e*4+0x02000000,0xf294); +reg_write( DDR_REG_BASE +0x5230f*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52310*4+0x02000000,0xf073); +reg_write( DDR_REG_BASE +0x52311*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52312*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52313*4+0x02000000,0xaba); +reg_write( DDR_REG_BASE +0x52314*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x52315*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52316*4+0x02000000,0x8d1); +reg_write( DDR_REG_BASE +0x52317*4+0x02000000,0x30); +reg_write( DDR_REG_BASE +0x52318*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52319*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5231a*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5231b*4+0x02000000,0x7b0); +reg_write( DDR_REG_BASE +0x5231c*4+0x02000000,0xa8e1); +reg_write( DDR_REG_BASE +0x5231d*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x5231e*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x5231f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52320*4+0x02000000,0x19c); +reg_write( DDR_REG_BASE +0x52321*4+0x02000000,0xa52); +reg_write( DDR_REG_BASE +0x52322*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x52323*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x52324*4+0x02000000,0xd3f); +reg_write( DDR_REG_BASE +0x52325*4+0x02000000,0x11f5); +reg_write( DDR_REG_BASE +0x52326*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52327*4+0x02000000,0x2025); +reg_write( DDR_REG_BASE +0x52328*4+0x02000000,0x340); +reg_write( DDR_REG_BASE +0x52329*4+0x02000000,0xf020); +reg_write( DDR_REG_BASE +0x5232a*4+0x02000000,0xf026); +reg_write( DDR_REG_BASE +0x5232b*4+0x02000000,0xf02e); +reg_write( DDR_REG_BASE +0x5232c*4+0x02000000,0xf030); +reg_write( DDR_REG_BASE +0x5232d*4+0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x5232e*4+0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x5232f*4+0x02000000,0xf033); +reg_write( DDR_REG_BASE +0x52330*4+0x02000000,0xc08d); +reg_write( DDR_REG_BASE +0x52331*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52332*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x52333*4+0x02000000,0x3e80); +reg_write( DDR_REG_BASE +0x52334*4+0x02000000,0xc103); +reg_write( DDR_REG_BASE +0x52335*4+0x02000000,0xc208); +reg_write( DDR_REG_BASE +0x52336*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52337*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52338*4+0x02000000,0x3f80); +reg_write( DDR_REG_BASE +0x52339*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5233a*4+0x02000000,0x19c); +reg_write( DDR_REG_BASE +0x5233b*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x5233c*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x5233d*4+0x02000000,0xfb2); +reg_write( DDR_REG_BASE +0x5233e*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5233f*4+0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x52340*4+0x02000000,0x716d); +reg_write( DDR_REG_BASE +0x52341*4+0x02000000,0xd88c); +reg_write( DDR_REG_BASE +0x52342*4+0x02000000,0xf02f); +reg_write( DDR_REG_BASE +0x52343*4+0x02000000,0x70d5); +reg_write( DDR_REG_BASE +0x52344*4+0x02000000,0x43c9); +reg_write( DDR_REG_BASE +0x52345*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x52346*4+0x02000000,0xf42b); +reg_write( DDR_REG_BASE +0x52347*4+0x02000000,0xf038); +reg_write( DDR_REG_BASE +0x52348*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52349*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x5234a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5234b*4+0x02000000,0x19c); +reg_write( DDR_REG_BASE +0x5234c*4+0x02000000,0x95e); +reg_write( DDR_REG_BASE +0x5234d*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x5234e*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5234f*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x52350*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52351*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x52352*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52353*4+0x02000000,0x19c); +reg_write( DDR_REG_BASE +0x52354*4+0x02000000,0xf56); +reg_write( DDR_REG_BASE +0x52355*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x52356*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52357*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x52358*4+0x02000000,0xbe2); +reg_write( DDR_REG_BASE +0x52359*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5235a*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5235b*4+0x02000000,0xf005); +reg_write( DDR_REG_BASE +0x5235c*4+0x02000000,0xc0e); +reg_write( DDR_REG_BASE +0x5235d*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x5235e*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x5235f*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x52360*4+0x02000000,0xf01e); +reg_write( DDR_REG_BASE +0x52361*4+0x02000000,0xc08d); +reg_write( DDR_REG_BASE +0x52362*4+0x02000000,0xc103); +reg_write( DDR_REG_BASE +0x52363*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52364*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x52365*4+0x02000000,0x3e80); +reg_write( DDR_REG_BASE +0x52366*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52367*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x52368*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52369*4+0x02000000,0x3f83); +reg_write( DDR_REG_BASE +0x5236a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5236b*4+0x02000000,0x19c); +reg_write( DDR_REG_BASE +0x5236c*4+0x02000000,0xf4e); +reg_write( DDR_REG_BASE +0x5236d*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5236e*4+0x02000000,0x4263); +reg_write( DDR_REG_BASE +0x5236f*4+0x02000000,0x716d); +reg_write( DDR_REG_BASE +0x52370*4+0x02000000,0xd8c0); +reg_write( DDR_REG_BASE +0x52371*4+0x02000000,0xc104); +reg_write( DDR_REG_BASE +0x52372*4+0x02000000,0xc20b); +reg_write( DDR_REG_BASE +0x52373*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x52374*4+0x02000000,0xc10c); +reg_write( DDR_REG_BASE +0x52375*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52376*4+0x02000000,0x2400); +reg_write( DDR_REG_BASE +0x52377*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x52378*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52379*4+0x02000000,0x19c); +reg_write( DDR_REG_BASE +0x5237a*4+0x02000000,0xaf2); +reg_write( DDR_REG_BASE +0x5237b*4+0x02000000,0xa0); +reg_write( DDR_REG_BASE +0x5237c*4+0x02000000,0x716c); +reg_write( DDR_REG_BASE +0x5237d*4+0x02000000,0x4669); +reg_write( DDR_REG_BASE +0x5237e*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5237f*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x52380*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52381*4+0x02000000,0x7b0); +reg_write( DDR_REG_BASE +0x52382*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52383*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52384*4+0x02000000,0x7002); +reg_write( DDR_REG_BASE +0x52385*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52386*4+0x02000000,0x7b0); +reg_write( DDR_REG_BASE +0x52387*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52388*4+0x02000000,0x813); +reg_write( DDR_REG_BASE +0x52389*4+0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x5238a*4+0x02000000,0x78ef); +reg_write( DDR_REG_BASE +0x5238b*4+0x02000000,0xd06); +reg_write( DDR_REG_BASE +0x5238c*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x5238d*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x5238e*4+0x02000000,0xca09); +reg_write( DDR_REG_BASE +0x5238f*4+0x02000000,0xe894); +reg_write( DDR_REG_BASE +0x52390*4+0x02000000,0xd0f); +reg_write( DDR_REG_BASE +0x52391*4+0x02000000,0x10f1); +reg_write( DDR_REG_BASE +0x52392*4+0x02000000,0x79ef); +reg_write( DDR_REG_BASE +0x52393*4+0x02000000,0xc7e); +reg_write( DDR_REG_BASE +0x52394*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x52395*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52396*4+0x02000000,0xf00c); +reg_write( DDR_REG_BASE +0x52397*4+0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x52398*4+0x02000000,0x815); +reg_write( DDR_REG_BASE +0x52399*4+0x02000000,0x134); +reg_write( DDR_REG_BASE +0x5239a*4+0x02000000,0x7bef); +reg_write( DDR_REG_BASE +0x5239b*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x5239c*4+0x02000000,0xc106); +reg_write( DDR_REG_BASE +0x5239d*4+0x02000000,0xc204); +reg_write( DDR_REG_BASE +0x5239e*4+0x02000000,0xbb2); +reg_write( DDR_REG_BASE +0x5239f*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x523a0*4+0x02000000,0x2052); +reg_write( DDR_REG_BASE +0x523a1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x523a2*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x523a3*4+0x02000000,0x72f5); +reg_write( DDR_REG_BASE +0x523a4*4+0x02000000,0x6b6); +reg_write( DDR_REG_BASE +0x523a5*4+0x02000000,0xffe5); +reg_write( DDR_REG_BASE +0x523a6*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x523a7*4+0x02000000,0xd19); +reg_write( DDR_REG_BASE +0x523a8*4+0x02000000,0x10d1); +reg_write( DDR_REG_BASE +0x523a9*4+0x02000000,0xca09); +reg_write( DDR_REG_BASE +0x523aa*4+0x02000000,0xe888); +reg_write( DDR_REG_BASE +0x523ab*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x523ac*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x523ad*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x523ae*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x523af*4+0x02000000,0xb8e5); +reg_write( DDR_REG_BASE +0x523b0*4+0x02000000,0xc7c); +reg_write( DDR_REG_BASE +0x523b1*4+0x02000000,0xfe42); +reg_write( DDR_REG_BASE +0x523b2*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x523b3*4+0x02000000,0x7003); +reg_write( DDR_REG_BASE +0x523b4*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x523b5*4+0x02000000,0xf); +reg_write( DDR_REG_BASE +0x523b6*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x523b7*4+0x02000000,0x3409); +reg_write( DDR_REG_BASE +0x523b8*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x523b9*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x523ba*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x523bb*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x523bc*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x523bd*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x523be*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x523bf*4+0x02000000,0xc1b0); +reg_write( DDR_REG_BASE +0x523c0*4+0x02000000,0xc04f); +reg_write( DDR_REG_BASE +0x523c1*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x523c2*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x523c3*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x523c4*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x523c5*4+0x02000000,0xefa); +reg_write( DDR_REG_BASE +0x523c6*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x523c7*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x523c8*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x523c9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x523ca*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x523cb*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x523cc*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x523cd*4+0x02000000,0xbee); +reg_write( DDR_REG_BASE +0x523ce*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x523cf*4+0x02000000,0x4300); +reg_write( DDR_REG_BASE +0x523d0*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x523d1*4+0x02000000,0x81e); +reg_write( DDR_REG_BASE +0x523d2*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x523d3*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x523d4*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x523d5*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x523d6*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x523d7*4+0x02000000,0x1f22); +reg_write( DDR_REG_BASE +0x523d8*4+0x02000000,0x1015); +reg_write( DDR_REG_BASE +0x523d9*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x523da*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x523db*4+0x02000000,0x1fa7); +reg_write( DDR_REG_BASE +0x523dc*4+0x02000000,0x101c); +reg_write( DDR_REG_BASE +0x523dd*4+0x02000000,0x1fa8); +reg_write( DDR_REG_BASE +0x523de*4+0x02000000,0x101c); +reg_write( DDR_REG_BASE +0x523df*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x523e0*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x523e1*4+0x02000000,0xb700); +reg_write( DDR_REG_BASE +0x523e2*4+0x02000000,0x1ffe); +reg_write( DDR_REG_BASE +0x523e3*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x523e4*4+0x02000000,0xb705); +reg_write( DDR_REG_BASE +0x523e5*4+0x02000000,0xbd2); +reg_write( DDR_REG_BASE +0x523e6*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x523e7*4+0x02000000,0x1ffc); +reg_write( DDR_REG_BASE +0x523e8*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x523e9*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x523ea*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x523eb*4+0x02000000,0x7b0); +reg_write( DDR_REG_BASE +0x523ec*4+0x02000000,0x8e04); +reg_write( DDR_REG_BASE +0x523ed*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x523ee*4+0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x523ef*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x523f0*4+0x02000000,0x10fd); +reg_write( DDR_REG_BASE +0x523f1*4+0x02000000,0x809e); +reg_write( DDR_REG_BASE +0x523f2*4+0x02000000,0x1420); +reg_write( DDR_REG_BASE +0x523f3*4+0x02000000,0x301b); +reg_write( DDR_REG_BASE +0x523f4*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x523f5*4+0x02000000,0x3100); +reg_write( DDR_REG_BASE +0x523f6*4+0x02000000,0x780d); +reg_write( DDR_REG_BASE +0x523f7*4+0x02000000,0x791c); +reg_write( DDR_REG_BASE +0x523f8*4+0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x523f9*4+0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x523fa*4+0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x523fb*4+0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x523fc*4+0x02000000,0x8e05); +reg_write( DDR_REG_BASE +0x523fd*4+0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x523fe*4+0x02000000,0x793c); +reg_write( DDR_REG_BASE +0x523ff*4+0x02000000,0xc04d); +reg_write( DDR_REG_BASE +0x52400*4+0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x52401*4+0x02000000,0xc04e); +reg_write( DDR_REG_BASE +0x52402*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52403*4+0x02000000,0x2304); +reg_write( DDR_REG_BASE +0x52404*4+0x02000000,0x305b); +reg_write( DDR_REG_BASE +0x52405*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x52406*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52407*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52408*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52409*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x5240a*4+0x02000000,0x8e03); +reg_write( DDR_REG_BASE +0x5240b*4+0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x5240c*4+0x02000000,0x8e02); +reg_write( DDR_REG_BASE +0x5240d*4+0x02000000,0x235); +reg_write( DDR_REG_BASE +0x5240e*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5240f*4+0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x52410*4+0x02000000,0xe17); +reg_write( DDR_REG_BASE +0x52411*4+0x02000000,0x317e); +reg_write( DDR_REG_BASE +0x52412*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x52413*4+0x02000000,0x6c0); +reg_write( DDR_REG_BASE +0x52414*4+0x02000000,0x1e05); +reg_write( DDR_REG_BASE +0x52415*4+0x02000000,0x16c2); +reg_write( DDR_REG_BASE +0x52416*4+0x02000000,0x1e04); +reg_write( DDR_REG_BASE +0x52417*4+0x02000000,0x16c2); +reg_write( DDR_REG_BASE +0x52418*4+0x02000000,0xae02); +reg_write( DDR_REG_BASE +0x52419*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5241a*4+0x02000000,0xae03); +reg_write( DDR_REG_BASE +0x5241b*4+0x02000000,0x770c); +reg_write( DDR_REG_BASE +0x5241c*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x5241d*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x5241e*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5241f*4+0x02000000,0xf0bb); +reg_write( DDR_REG_BASE +0x52420*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x52421*4+0x02000000,0xc101); +reg_write( DDR_REG_BASE +0x52422*4+0x02000000,0xae01); +reg_write( DDR_REG_BASE +0x52423*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52424*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x52425*4+0x02000000,0x8e00); +reg_write( DDR_REG_BASE +0x52426*4+0x02000000,0xb9c4); +reg_write( DDR_REG_BASE +0x52427*4+0x02000000,0xe906); +reg_write( DDR_REG_BASE +0x52428*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x52429*4+0x02000000,0x901); +reg_write( DDR_REG_BASE +0x5242a*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x5242b*4+0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x5242c*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x5242d*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5242e*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x5242f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52430*4+0x02000000,0x49); +reg_write( DDR_REG_BASE +0x52431*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x52432*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52433*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x52434*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52435*4+0x02000000,0x23); +reg_write( DDR_REG_BASE +0x52436*4+0x02000000,0x784f); +reg_write( DDR_REG_BASE +0x52437*4+0x02000000,0x790b); +reg_write( DDR_REG_BASE +0x52438*4+0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x52439*4+0x02000000,0xf29f); +reg_write( DDR_REG_BASE +0x5243a*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x5243b*4+0x02000000,0xf6e); +reg_write( DDR_REG_BASE +0x5243c*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x5243d*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5243e*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5243f*4+0x02000000,0xc2e); +reg_write( DDR_REG_BASE +0x52440*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52441*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52442*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52443*4+0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x52444*4+0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x52445*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x52446*4+0x02000000,0xe59f); +reg_write( DDR_REG_BASE +0x52447*4+0x02000000,0x10c); +reg_write( DDR_REG_BASE +0x52448*4+0x02000000,0x9); +reg_write( DDR_REG_BASE +0x52449*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x5244a*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x5244b*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5244c*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x5244d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5244e*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5244f*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52450*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52451*4+0x02000000,0xe040); +reg_write( DDR_REG_BASE +0x52452*4+0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x52453*4+0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x52454*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x52455*4+0x02000000,0x10fd); +reg_write( DDR_REG_BASE +0x52456*4+0x02000000,0x8080); +reg_write( DDR_REG_BASE +0x52457*4+0x02000000,0x82d); +reg_write( DDR_REG_BASE +0x52458*4+0x02000000,0x15f); +reg_write( DDR_REG_BASE +0x52459*4+0x02000000,0x8e25); +reg_write( DDR_REG_BASE +0x5245a*4+0x02000000,0x8e44); +reg_write( DDR_REG_BASE +0x5245b*4+0x02000000,0xf00f); +reg_write( DDR_REG_BASE +0x5245c*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x5245d*4+0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x5245e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5245f*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52460*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52461*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x52462*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x52463*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52464*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52465*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52466*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52467*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x52468*4+0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x52469*4+0x02000000,0x9e9); +reg_write( DDR_REG_BASE +0x5246a*4+0x02000000,0x8085); +reg_write( DDR_REG_BASE +0x5246b*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x5246c*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x5246d*4+0x02000000,0x3f81); +reg_write( DDR_REG_BASE +0x5246e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5246f*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52470*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52471*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52472*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52473*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52474*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52475*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52476*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x52477*4+0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x52478*4+0x02000000,0xd72); +reg_write( DDR_REG_BASE +0x52479*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5247a*4+0x02000000,0xd814); +reg_write( DDR_REG_BASE +0x5247b*4+0x02000000,0xeea); +reg_write( DDR_REG_BASE +0x5247c*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x5247d*4+0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x5247e*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5247f*4+0x02000000,0xbae); +reg_write( DDR_REG_BASE +0x52480*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52481*4+0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x52482*4+0x02000000,0x8e04); +reg_write( DDR_REG_BASE +0x52483*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52484*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52485*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x52486*4+0x02000000,0xf034); +reg_write( DDR_REG_BASE +0x52487*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x52488*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52489*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x5248a*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x5248b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5248c*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x5248d*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x5248e*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5248f*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52490*4+0x02000000,0x170); +reg_write( DDR_REG_BASE +0x52491*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x52492*4+0x02000000,0xc245); +reg_write( DDR_REG_BASE +0x52493*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x52494*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52495*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x52496*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52497*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52498*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52499*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x5249a*4+0x02000000,0x166); +reg_write( DDR_REG_BASE +0x5249b*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x5249c*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x5249d*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x5249e*4+0x02000000,0x7810); +reg_write( DDR_REG_BASE +0x5249f*4+0x02000000,0x200f); +reg_write( DDR_REG_BASE +0x524a0*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x524a1*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x524a2*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x524a3*4+0x02000000,0xae5); +reg_write( DDR_REG_BASE +0x524a4*4+0x02000000,0x8234); +reg_write( DDR_REG_BASE +0x524a5*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x524a6*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x524a7*4+0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x524a8*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x524a9*4+0x02000000,0xf40b); +reg_write( DDR_REG_BASE +0x524aa*4+0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x524ab*4+0x02000000,0xc303); +reg_write( DDR_REG_BASE +0x524ac*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x524ad*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x524ae*4+0x02000000,0xe); +reg_write( DDR_REG_BASE +0x524af*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x524b0*4+0x02000000,0xf02); +reg_write( DDR_REG_BASE +0x524b1*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524b2*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x524b3*4+0x02000000,0xc105); +reg_write( DDR_REG_BASE +0x524b4*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x524b5*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x524b6*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x524b7*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x524b8*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x524b9*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x524ba*4+0x02000000,0x8e25); +reg_write( DDR_REG_BASE +0x524bb*4+0x02000000,0xc003); +reg_write( DDR_REG_BASE +0x524bc*4+0x02000000,0x997); +reg_write( DDR_REG_BASE +0x524bd*4+0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x524be*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x524bf*4+0x02000000,0xe42); +reg_write( DDR_REG_BASE +0x524c0*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x524c1*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x524c2*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x524c3*4+0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x524c4*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x524c5*4+0x02000000,0xf581); +reg_write( DDR_REG_BASE +0x524c6*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x524c7*4+0x02000000,0x2008); +reg_write( DDR_REG_BASE +0x524c8*4+0x02000000,0x340); +reg_write( DDR_REG_BASE +0x524c9*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x524ca*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x524cb*4+0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x524cc*4+0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x524cd*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x524ce*4+0x02000000,0x11); +reg_write( DDR_REG_BASE +0x524cf*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x524d0*4+0x02000000,0xf4e); +reg_write( DDR_REG_BASE +0x524d1*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x524d2*4+0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x524d3*4+0x02000000,0xc26); +reg_write( DDR_REG_BASE +0x524d4*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x524d5*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x524d6*4+0x02000000,0xc502); +reg_write( DDR_REG_BASE +0x524d7*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x524d8*4+0x02000000,0x7704); +reg_write( DDR_REG_BASE +0x524d9*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x524da*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x524db*4+0x02000000,0x7014); +reg_write( DDR_REG_BASE +0x524dc*4+0x02000000,0x688); +reg_write( DDR_REG_BASE +0x524dd*4+0x02000000,0xffca); +reg_write( DDR_REG_BASE +0x524de*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x524df*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x524e0*4+0x02000000,0x13); +reg_write( DDR_REG_BASE +0x524e1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x524e2*4+0x02000000,0x7812); +reg_write( DDR_REG_BASE +0x524e3*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x524e4*4+0x02000000,0xd); +reg_write( DDR_REG_BASE +0x524e5*4+0x02000000,0xf26); +reg_write( DDR_REG_BASE +0x524e6*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x524e7*4+0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x524e8*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x524e9*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x524ea*4+0x02000000,0x7081); +reg_write( DDR_REG_BASE +0x524eb*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x524ec*4+0x02000000,0x14); +reg_write( DDR_REG_BASE +0x524ed*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x524ee*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x524ef*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x524f0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x524f1*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x524f2*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x524f3*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x524f4*4+0x02000000,0xe040); +reg_write( DDR_REG_BASE +0x524f5*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x524f6*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x524f7*4+0x02000000,0x2049); +reg_write( DDR_REG_BASE +0x524f8*4+0x02000000,0x7c1); +reg_write( DDR_REG_BASE +0x524f9*4+0x02000000,0xb220); +reg_write( DDR_REG_BASE +0x524fa*4+0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x524fb*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x524fc*4+0x02000000,0x10fd); +reg_write( DDR_REG_BASE +0x524fd*4+0x02000000,0x809e); +reg_write( DDR_REG_BASE +0x524fe*4+0x02000000,0xe37); +reg_write( DDR_REG_BASE +0x524ff*4+0x02000000,0x315f); +reg_write( DDR_REG_BASE +0x52500*4+0x02000000,0x8e45); +reg_write( DDR_REG_BASE +0x52501*4+0x02000000,0x8e64); +reg_write( DDR_REG_BASE +0x52502*4+0x02000000,0xf00e); +reg_write( DDR_REG_BASE +0x52503*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x52504*4+0x02000000,0xf8c); +reg_write( DDR_REG_BASE +0x52505*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52506*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52507*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52508*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x52509*4+0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x5250a*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5250b*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5250c*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5250d*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x5250e*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x5250f*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x52510*4+0x02000000,0xae7); +reg_write( DDR_REG_BASE +0x52511*4+0x02000000,0x80c5); +reg_write( DDR_REG_BASE +0x52512*4+0x02000000,0xdba); +reg_write( DDR_REG_BASE +0x52513*4+0x02000000,0xff8f); +reg_write( DDR_REG_BASE +0x52514*4+0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x52515*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x52516*4+0x02000000,0x10fd); +reg_write( DDR_REG_BASE +0x52517*4+0x02000000,0x809e); +reg_write( DDR_REG_BASE +0x52518*4+0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x52519*4+0x02000000,0x231a); +reg_write( DDR_REG_BASE +0x5251a*4+0x02000000,0x3f82); +reg_write( DDR_REG_BASE +0x5251b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5251c*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x5251d*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x5251e*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x5251f*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52520*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52521*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52522*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52523*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x52524*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x52525*4+0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x52526*4+0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x52527*4+0x02000000,0x230c); +reg_write( DDR_REG_BASE +0x52528*4+0x02000000,0xb000); +reg_write( DDR_REG_BASE +0x52529*4+0x02000000,0x5d0); +reg_write( DDR_REG_BASE +0x5252a*4+0x02000000,0xffce); +reg_write( DDR_REG_BASE +0x5252b*4+0x02000000,0xe17); +reg_write( DDR_REG_BASE +0x5252c*4+0x02000000,0x315e); +reg_write( DDR_REG_BASE +0x5252d*4+0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x5252e*4+0x02000000,0xae05); +reg_write( DDR_REG_BASE +0x5252f*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x52530*4+0x02000000,0xae04); +reg_write( DDR_REG_BASE +0x52531*4+0x02000000,0xc00c); +reg_write( DDR_REG_BASE +0x52532*4+0x02000000,0xae03); +reg_write( DDR_REG_BASE +0x52533*4+0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x52534*4+0x02000000,0xae02); +reg_write( DDR_REG_BASE +0x52535*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52536*4+0x02000000,0x1fa7); +reg_write( DDR_REG_BASE +0x52537*4+0x02000000,0x101c); +reg_write( DDR_REG_BASE +0x52538*4+0x02000000,0x1fa8); +reg_write( DDR_REG_BASE +0x52539*4+0x02000000,0x101c); +reg_write( DDR_REG_BASE +0x5253a*4+0x02000000,0xb700); +reg_write( DDR_REG_BASE +0x5253b*4+0x02000000,0xc0b0); +reg_write( DDR_REG_BASE +0x5253c*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x5253d*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x5253e*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x5253f*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52540*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x52541*4+0x02000000,0x8fc3); +reg_write( DDR_REG_BASE +0x52542*4+0x02000000,0xf209); +reg_write( DDR_REG_BASE +0x52543*4+0x02000000,0x821); +reg_write( DDR_REG_BASE +0x52544*4+0x02000000,0x1d1); +reg_write( DDR_REG_BASE +0x52545*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52546*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52547*4+0x02000000,0x238); +reg_write( DDR_REG_BASE +0x52548*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x52549*4+0x02000000,0x45); +reg_write( DDR_REG_BASE +0x5254a*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x5254b*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5254c*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x5254d*4+0x02000000,0x238); +reg_write( DDR_REG_BASE +0x5254e*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x5254f*4+0x02000000,0x105); +reg_write( DDR_REG_BASE +0x52550*4+0x02000000,0x1900); +reg_write( DDR_REG_BASE +0x52551*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x52552*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52553*4+0x02000000,0x9018); +reg_write( DDR_REG_BASE +0x52554*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x52555*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x52556*4+0x02000000,0x25); +reg_write( DDR_REG_BASE +0x52557*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52558*4+0x02000000,0x1902); +reg_write( DDR_REG_BASE +0x52559*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x5255a*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5255b*4+0x02000000,0x9018); +reg_write( DDR_REG_BASE +0x5255c*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x5255d*4+0x02000000,0xda10); +reg_write( DDR_REG_BASE +0x5255e*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x5255f*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x52560*4+0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x52561*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x52562*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52563*4+0x02000000,0xb102); +reg_write( DDR_REG_BASE +0x52564*4+0x02000000,0x9); +reg_write( DDR_REG_BASE +0x52565*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52566*4+0x02000000,0x1902); +reg_write( DDR_REG_BASE +0x52567*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x52568*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52569*4+0x02000000,0x9018); +reg_write( DDR_REG_BASE +0x5256a*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x5256b*4+0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x5256c*4+0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x5256d*4+0x02000000,0x801f); +reg_write( DDR_REG_BASE +0x5256e*4+0x02000000,0x195e); +reg_write( DDR_REG_BASE +0x5256f*4+0x02000000,0x45); +reg_write( DDR_REG_BASE +0x52570*4+0x02000000,0x9100); +reg_write( DDR_REG_BASE +0x52571*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x52572*4+0x02000000,0x1e); +reg_write( DDR_REG_BASE +0x52573*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52574*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x52575*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x52576*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52577*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x52578*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52579*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5257a*4+0x02000000,0x827); +reg_write( DDR_REG_BASE +0x5257b*4+0x02000000,0x13f); +reg_write( DDR_REG_BASE +0x5257c*4+0x02000000,0x4328); +reg_write( DDR_REG_BASE +0x5257d*4+0x02000000,0xd808); +reg_write( DDR_REG_BASE +0x5257e*4+0x02000000,0xf86); +reg_write( DDR_REG_BASE +0x5257f*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x52580*4+0x02000000,0x7d50); +reg_write( DDR_REG_BASE +0x52581*4+0x02000000,0xfb6); +reg_write( DDR_REG_BASE +0x52582*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x52583*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x52584*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x52585*4+0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x52586*4+0x02000000,0xfaa); +reg_write( DDR_REG_BASE +0x52587*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x52588*4+0x02000000,0x1304); +reg_write( DDR_REG_BASE +0x52589*4+0x02000000,0x1400); +reg_write( DDR_REG_BASE +0x5258a*4+0x02000000,0x7164); +reg_write( DDR_REG_BASE +0x5258b*4+0x02000000,0xbf9); +reg_write( DDR_REG_BASE +0x5258c*4+0x02000000,0x8344); +reg_write( DDR_REG_BASE +0x5258d*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x5258e*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x5258f*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52590*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52591*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x52592*4+0x02000000,0x3a03); +reg_write( DDR_REG_BASE +0x52593*4+0x02000000,0xc255); +reg_write( DDR_REG_BASE +0x52594*4+0x02000000,0xc152); +reg_write( DDR_REG_BASE +0x52595*4+0x02000000,0xc050); +reg_write( DDR_REG_BASE +0x52596*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x52597*4+0x02000000,0x3800); +reg_write( DDR_REG_BASE +0x52598*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52599*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5259a*4+0x02000000,0x4a4); +reg_write( DDR_REG_BASE +0x5259b*4+0x02000000,0xda66); +reg_write( DDR_REG_BASE +0x5259c*4+0x02000000,0xd4a); +reg_write( DDR_REG_BASE +0x5259d*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x5259e*4+0x02000000,0xc353); +reg_write( DDR_REG_BASE +0x5259f*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x525a0*4+0x02000000,0x3800); +reg_write( DDR_REG_BASE +0x525a1*4+0x02000000,0xe4a); +reg_write( DDR_REG_BASE +0x525a2*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x525a3*4+0x02000000,0xd966); +reg_write( DDR_REG_BASE +0x525a4*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x525a5*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x525a6*4+0x02000000,0x7b4); +reg_write( DDR_REG_BASE +0x525a7*4+0x02000000,0x8f40); +reg_write( DDR_REG_BASE +0x525a8*4+0x02000000,0x8f21); +reg_write( DDR_REG_BASE +0x525a9*4+0x02000000,0x14fc); +reg_write( DDR_REG_BASE +0x525aa*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x525ab*4+0x02000000,0x225f); +reg_write( DDR_REG_BASE +0x525ac*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x525ad*4+0x02000000,0xc054); +reg_write( DDR_REG_BASE +0x525ae*4+0x02000000,0xf03a); +reg_write( DDR_REG_BASE +0x525af*4+0x02000000,0x44cb); +reg_write( DDR_REG_BASE +0x525b0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x525b1*4+0x02000000,0x7fff); +reg_write( DDR_REG_BASE +0x525b2*4+0x02000000,0x6c01); +reg_write( DDR_REG_BASE +0x525b3*4+0x02000000,0x4368); +reg_write( DDR_REG_BASE +0x525b4*4+0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x525b5*4+0x02000000,0xc015); +reg_write( DDR_REG_BASE +0x525b6*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x525b7*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x525b8*4+0x02000000,0x2c0); +reg_write( DDR_REG_BASE +0x525b9*4+0x02000000,0x7165); +reg_write( DDR_REG_BASE +0x525ba*4+0x02000000,0x2009); +reg_write( DDR_REG_BASE +0x525bb*4+0x02000000,0x30c); +reg_write( DDR_REG_BASE +0x525bc*4+0x02000000,0x2008); +reg_write( DDR_REG_BASE +0x525bd*4+0x02000000,0x340); +reg_write( DDR_REG_BASE +0x525be*4+0x02000000,0xeef); +reg_write( DDR_REG_BASE +0x525bf*4+0x02000000,0x9234); +reg_write( DDR_REG_BASE +0x525c0*4+0x02000000,0x7d0e); +reg_write( DDR_REG_BASE +0x525c1*4+0x02000000,0x64b8); +reg_write( DDR_REG_BASE +0x525c2*4+0x02000000,0x2844); +reg_write( DDR_REG_BASE +0x525c3*4+0x02000000,0x8d); +reg_write( DDR_REG_BASE +0x525c4*4+0x02000000,0xe309); +reg_write( DDR_REG_BASE +0x525c5*4+0x02000000,0x7eae); +reg_write( DDR_REG_BASE +0x525c6*4+0x02000000,0x78dc); +reg_write( DDR_REG_BASE +0x525c7*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x525c8*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x525c9*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x525ca*4+0x02000000,0x4408); +reg_write( DDR_REG_BASE +0x525cb*4+0x02000000,0xd81b); +reg_write( DDR_REG_BASE +0x525cc*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x525cd*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x525ce*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x525cf*4+0x02000000,0x7c9d); +reg_write( DDR_REG_BASE +0x525d0*4+0x02000000,0x6698); +reg_write( DDR_REG_BASE +0x525d1*4+0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x525d2*4+0x02000000,0x4894); +reg_write( DDR_REG_BASE +0x525d3*4+0x02000000,0x2e44); +reg_write( DDR_REG_BASE +0x525d4*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x525d5*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x525d6*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x525d7*4+0x02000000,0x7c05); +reg_write( DDR_REG_BASE +0x525d8*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x525d9*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x525da*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x525db*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x525dc*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x525dd*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x525de*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x525df*4+0x02000000,0x1064); +reg_write( DDR_REG_BASE +0x525e0*4+0x02000000,0xb080); +reg_write( DDR_REG_BASE +0x525e1*4+0x02000000,0xc096); +reg_write( DDR_REG_BASE +0x525e2*4+0x02000000,0x7854); +reg_write( DDR_REG_BASE +0x525e3*4+0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x525e4*4+0x02000000,0xc09b); +reg_write( DDR_REG_BASE +0x525e5*4+0x02000000,0x7854); +reg_write( DDR_REG_BASE +0x525e6*4+0x02000000,0xb080); +reg_write( DDR_REG_BASE +0x525e7*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x525e8*4+0x02000000,0x98f); +reg_write( DDR_REG_BASE +0x525e9*4+0x02000000,0x80a5); +reg_write( DDR_REG_BASE +0x525ea*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x525eb*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x525ec*4+0x02000000,0x83a); +reg_write( DDR_REG_BASE +0x525ed*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x525ee*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x525ef*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x525f0*4+0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x525f1*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x525f2*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x525f3*4+0x02000000,0xb98e); +reg_write( DDR_REG_BASE +0x525f4*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x525f5*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x525f6*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x525f7*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x525f8*4+0x02000000,0x8fa); +reg_write( DDR_REG_BASE +0x525f9*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x525fa*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x525fb*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x525fc*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x525fd*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x525fe*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x525ff*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x52600*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x52601*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x52602*4+0x02000000,0x8e6); +reg_write( DDR_REG_BASE +0x52603*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52604*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x52605*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52606*4+0x02000000,0x89e); +reg_write( DDR_REG_BASE +0x52607*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52608*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52609*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x5260a*4+0x02000000,0xf86); +reg_write( DDR_REG_BASE +0x5260b*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x5260c*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x5260d*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x5260e*4+0x02000000,0xfc7); +reg_write( DDR_REG_BASE +0x5260f*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52610*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52611*4+0x02000000,0xe174); +reg_write( DDR_REG_BASE +0x52612*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52613*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52614*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52615*4+0x02000000,0xe174); +reg_write( DDR_REG_BASE +0x52616*4+0x02000000,0xb101); +reg_write( DDR_REG_BASE +0x52617*4+0x02000000,0xc010); +reg_write( DDR_REG_BASE +0x52618*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52619*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x5261a*4+0x02000000,0x7cd); +reg_write( DDR_REG_BASE +0x5261b*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x5261c*4+0x02000000,0xed05); +reg_write( DDR_REG_BASE +0x5261d*4+0x02000000,0xbd61); +reg_write( DDR_REG_BASE +0x5261e*4+0x02000000,0xdff); +reg_write( DDR_REG_BASE +0x5261f*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x52620*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52621*4+0x02000000,0xc051); +reg_write( DDR_REG_BASE +0x52622*4+0x02000000,0xef3); +reg_write( DDR_REG_BASE +0x52623*4+0x02000000,0x1155); +reg_write( DDR_REG_BASE +0x52624*4+0x02000000,0xc011); +reg_write( DDR_REG_BASE +0x52625*4+0x02000000,0xd8a); +reg_write( DDR_REG_BASE +0x52626*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52627*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52628*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52629*4+0x02000000,0xb6e); +reg_write( DDR_REG_BASE +0x5262a*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5262b*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x5262c*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5262d*4+0x02000000,0x852); +reg_write( DDR_REG_BASE +0x5262e*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x5262f*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52630*4+0x02000000,0x8fa0); +reg_write( DDR_REG_BASE +0x52631*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52632*4+0x02000000,0xc04f); +reg_write( DDR_REG_BASE +0x52633*4+0x02000000,0xf061); +reg_write( DDR_REG_BASE +0x52634*4+0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x52635*4+0x02000000,0x1f81); +reg_write( DDR_REG_BASE +0x52636*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52637*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52638*4+0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x52639*4+0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x5263a*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x5263b*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x5263c*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x5263d*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5263e*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x5263f*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52640*4+0x02000000,0x166); +reg_write( DDR_REG_BASE +0x52641*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x52642*4+0x02000000,0x2300); +reg_write( DDR_REG_BASE +0x52643*4+0x02000000,0x301b); +reg_write( DDR_REG_BASE +0x52644*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x52645*4+0x02000000,0x8ed); +reg_write( DDR_REG_BASE +0x52646*4+0x02000000,0x8234); +reg_write( DDR_REG_BASE +0x52647*4+0x02000000,0x6841); +reg_write( DDR_REG_BASE +0x52648*4+0x02000000,0xb8f); +reg_write( DDR_REG_BASE +0x52649*4+0x02000000,0x3010); +reg_write( DDR_REG_BASE +0x5264a*4+0x02000000,0xe21); +reg_write( DDR_REG_BASE +0x5264b*4+0x02000000,0x1070); +reg_write( DDR_REG_BASE +0x5264c*4+0x02000000,0xc096); +reg_write( DDR_REG_BASE +0x5264d*4+0x02000000,0xe25); +reg_write( DDR_REG_BASE +0x5264e*4+0x02000000,0x10f0); +reg_write( DDR_REG_BASE +0x5264f*4+0x02000000,0xc096); +reg_write( DDR_REG_BASE +0x52650*4+0x02000000,0xe25); +reg_write( DDR_REG_BASE +0x52651*4+0x02000000,0x1131); +reg_write( DDR_REG_BASE +0x52652*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52653*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52654*4+0x02000000,0x24); +reg_write( DDR_REG_BASE +0x52655*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52656*4+0x02000000,0xc42); +reg_write( DDR_REG_BASE +0x52657*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52658*4+0x02000000,0x42a1); +reg_write( DDR_REG_BASE +0x52659*4+0x02000000,0xf037); +reg_write( DDR_REG_BASE +0x5265a*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x5265b*4+0x02000000,0x340); +reg_write( DDR_REG_BASE +0x5265c*4+0x02000000,0x7404); +reg_write( DDR_REG_BASE +0x5265d*4+0x02000000,0xf014); +reg_write( DDR_REG_BASE +0x5265e*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x5265f*4+0x02000000,0x340); +reg_write( DDR_REG_BASE +0x52660*4+0x02000000,0xe008); +reg_write( DDR_REG_BASE +0x52661*4+0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x52662*4+0x02000000,0xc096); +reg_write( DDR_REG_BASE +0x52663*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x52664*4+0x02000000,0x341); +reg_write( DDR_REG_BASE +0x52665*4+0x02000000,0xee08); +reg_write( DDR_REG_BASE +0x52666*4+0x02000000,0x915); +reg_write( DDR_REG_BASE +0x52667*4+0x02000000,0x274); +reg_write( DDR_REG_BASE +0x52668*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52669*4+0x02000000,0x2142); +reg_write( DDR_REG_BASE +0x5266a*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x5266b*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x5266c*4+0x02000000,0x909); +reg_write( DDR_REG_BASE +0x5266d*4+0x02000000,0x174); +reg_write( DDR_REG_BASE +0x5266e*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5266f*4+0x02000000,0x690c); +reg_write( DDR_REG_BASE +0x52670*4+0x02000000,0x7a0e); +reg_write( DDR_REG_BASE +0x52671*4+0x02000000,0x785c); +reg_write( DDR_REG_BASE +0x52672*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x52673*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x52674*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x52675*4+0x02000000,0x4100); +reg_write( DDR_REG_BASE +0x52676*4+0x02000000,0xd81b); +reg_write( DDR_REG_BASE +0x52677*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x52678*4+0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x52679*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x5267a*4+0x02000000,0x793d); +reg_write( DDR_REG_BASE +0x5267b*4+0x02000000,0x6238); +reg_write( DDR_REG_BASE +0x5267c*4+0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x5267d*4+0x02000000,0x4831); +reg_write( DDR_REG_BASE +0x5267e*4+0x02000000,0x2a44); +reg_write( DDR_REG_BASE +0x5267f*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x52680*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52681*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52682*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x52683*4+0x02000000,0x251a); +reg_write( DDR_REG_BASE +0x52684*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x52685*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52686*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x52687*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52688*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52689*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x5268a*4+0x02000000,0x1064); +reg_write( DDR_REG_BASE +0x5268b*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x5268c*4+0x02000000,0xc09b); +reg_write( DDR_REG_BASE +0x5268d*4+0x02000000,0x78b4); +reg_write( DDR_REG_BASE +0x5268e*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x5268f*4+0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x52690*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x52691*4+0x02000000,0x7063); +reg_write( DDR_REG_BASE +0x52692*4+0x02000000,0xc04f); +reg_write( DDR_REG_BASE +0x52693*4+0x02000000,0x8f01); +reg_write( DDR_REG_BASE +0x52694*4+0x02000000,0x841); +reg_write( DDR_REG_BASE +0x52695*4+0x02000000,0x8365); +reg_write( DDR_REG_BASE +0x52696*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52697*4+0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x52698*4+0x02000000,0x815); +reg_write( DDR_REG_BASE +0x52699*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x5269a*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x5269b*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5269c*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5269d*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5269e*4+0x02000000,0xe174); +reg_write( DDR_REG_BASE +0x5269f*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x526a0*4+0x02000000,0x7044); +reg_write( DDR_REG_BASE +0x526a1*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x526a2*4+0x02000000,0xe174); +reg_write( DDR_REG_BASE +0x526a3*4+0x02000000,0xb021); +reg_write( DDR_REG_BASE +0x526a4*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x526a5*4+0x02000000,0xc04d); +reg_write( DDR_REG_BASE +0x526a6*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x526a7*4+0x02000000,0xb88b); +reg_write( DDR_REG_BASE +0x526a8*4+0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x526a9*4+0x02000000,0xd840); +reg_write( DDR_REG_BASE +0x526aa*4+0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x526ab*4+0x02000000,0xc014); +reg_write( DDR_REG_BASE +0x526ac*4+0x02000000,0xc16e); +reg_write( DDR_REG_BASE +0x526ad*4+0x02000000,0xc149); +reg_write( DDR_REG_BASE +0x526ae*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x526af*4+0x02000000,0xc013); +reg_write( DDR_REG_BASE +0x526b0*4+0x02000000,0xc168); +reg_write( DDR_REG_BASE +0x526b1*4+0x02000000,0xc147); +reg_write( DDR_REG_BASE +0x526b2*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x526b3*4+0x02000000,0xc010); +reg_write( DDR_REG_BASE +0x526b4*4+0x02000000,0xc19b); +reg_write( DDR_REG_BASE +0x526b5*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x526b6*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x526b7*4+0x02000000,0xc084); +reg_write( DDR_REG_BASE +0x526b8*4+0x02000000,0xe2a); +reg_write( DDR_REG_BASE +0x526b9*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x526ba*4+0x02000000,0x1c28); +reg_write( DDR_REG_BASE +0x526bb*4+0x02000000,0x3085); +reg_write( DDR_REG_BASE +0x526bc*4+0x02000000,0xc084); +reg_write( DDR_REG_BASE +0x526bd*4+0x02000000,0xc19b); +reg_write( DDR_REG_BASE +0x526be*4+0x02000000,0xe1e); +reg_write( DDR_REG_BASE +0x526bf*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x526c0*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x526c1*4+0x02000000,0xc011); +reg_write( DDR_REG_BASE +0x526c2*4+0x02000000,0x8fa0); +reg_write( DDR_REG_BASE +0x526c3*4+0x02000000,0x8fc1); +reg_write( DDR_REG_BASE +0x526c4*4+0x02000000,0x842); +reg_write( DDR_REG_BASE +0x526c5*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x526c6*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x526c7*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x526c8*4+0x02000000,0x125b); +reg_write( DDR_REG_BASE +0x526c9*4+0x02000000,0x255f); +reg_write( DDR_REG_BASE +0x526ca*4+0x02000000,0x124d); +reg_write( DDR_REG_BASE +0x526cb*4+0x02000000,0xc012); +reg_write( DDR_REG_BASE +0x526cc*4+0x02000000,0xe807); +reg_write( DDR_REG_BASE +0x526cd*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x526ce*4+0x02000000,0x25); +reg_write( DDR_REG_BASE +0x526cf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x526d0*4+0x02000000,0xac2); +reg_write( DDR_REG_BASE +0x526d1*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x526d2*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x526d3*4+0x02000000,0x8fc0); +reg_write( DDR_REG_BASE +0x526d4*4+0x02000000,0x2340); +reg_write( DDR_REG_BASE +0x526d5*4+0x02000000,0x321b); +reg_write( DDR_REG_BASE +0x526d6*4+0x02000000,0xe508); +reg_write( DDR_REG_BASE +0x526d7*4+0x02000000,0xf02c); +reg_write( DDR_REG_BASE +0x526d8*4+0x02000000,0xc013); +reg_write( DDR_REG_BASE +0x526d9*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x526da*4+0x02000000,0x341); +reg_write( DDR_REG_BASE +0x526db*4+0x02000000,0xc014); +reg_write( DDR_REG_BASE +0x526dc*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x526dd*4+0x02000000,0x342); +reg_write( DDR_REG_BASE +0x526de*4+0x02000000,0x6238); +reg_write( DDR_REG_BASE +0x526df*4+0x02000000,0x7b1c); +reg_write( DDR_REG_BASE +0x526e0*4+0x02000000,0xc015); +reg_write( DDR_REG_BASE +0x526e1*4+0x02000000,0x2348); +reg_write( DDR_REG_BASE +0x526e2*4+0x02000000,0xc); +reg_write( DDR_REG_BASE +0x526e3*4+0x02000000,0x78b4); +reg_write( DDR_REG_BASE +0x526e4*4+0x02000000,0xb080); +reg_write( DDR_REG_BASE +0x526e5*4+0x02000000,0x4a30); +reg_write( DDR_REG_BASE +0x526e6*4+0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x526e7*4+0x02000000,0xf); +reg_write( DDR_REG_BASE +0x526e8*4+0x02000000,0xc012); +reg_write( DDR_REG_BASE +0x526e9*4+0x02000000,0xe80d); +reg_write( DDR_REG_BASE +0x526ea*4+0x02000000,0xc342); +reg_write( DDR_REG_BASE +0x526eb*4+0x02000000,0xc241); +reg_write( DDR_REG_BASE +0x526ec*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x526ed*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x526ee*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x526ef*4+0x02000000,0x27); +reg_write( DDR_REG_BASE +0x526f0*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x526f1*4+0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x526f2*4+0x02000000,0xa7e); +reg_write( DDR_REG_BASE +0x526f3*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x526f4*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x526f5*4+0x02000000,0x78ee); +reg_write( DDR_REG_BASE +0x526f6*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x526f7*4+0x02000000,0x207f); +reg_write( DDR_REG_BASE +0x526f8*4+0x02000000,0x140); +reg_write( DDR_REG_BASE +0x526f9*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x526fa*4+0x02000000,0x28); +reg_write( DDR_REG_BASE +0x526fb*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x526fc*4+0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x526fd*4+0x02000000,0xaf6); +reg_write( DDR_REG_BASE +0x526fe*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x526ff*4+0x02000000,0xdb08); +reg_write( DDR_REG_BASE +0x52700*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x52701*4+0x02000000,0xe509); +reg_write( DDR_REG_BASE +0x52702*4+0x02000000,0xbad); +reg_write( DDR_REG_BASE +0x52703*4+0x02000000,0xb345); +reg_write( DDR_REG_BASE +0x52704*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52705*4+0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x52706*4+0x02000000,0x900f); +reg_write( DDR_REG_BASE +0x52707*4+0x02000000,0xe022); +reg_write( DDR_REG_BASE +0x52708*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52709*4+0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x5270a*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5270b*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x5270c*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x5270d*4+0x02000000,0x3a03); +reg_write( DDR_REG_BASE +0x5270e*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x5270f*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52710*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52711*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52712*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52713*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52714*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52715*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x52716*4+0x02000000,0x3606); +reg_write( DDR_REG_BASE +0x52717*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52718*4+0x02000000,0xc350); +reg_write( DDR_REG_BASE +0x52719*4+0x02000000,0xc257); +reg_write( DDR_REG_BASE +0x5271a*4+0x02000000,0xc052); +reg_write( DDR_REG_BASE +0x5271b*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5271c*4+0x02000000,0x7344); +reg_write( DDR_REG_BASE +0x5271d*4+0x02000000,0x900f); +reg_write( DDR_REG_BASE +0x5271e*4+0x02000000,0xe022); +reg_write( DDR_REG_BASE +0x5271f*4+0x02000000,0x206f); +reg_write( DDR_REG_BASE +0x52720*4+0x02000000,0x43); +reg_write( DDR_REG_BASE +0x52721*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52722*4+0x02000000,0x9b); +reg_write( DDR_REG_BASE +0x52723*4+0x02000000,0x8804); +reg_write( DDR_REG_BASE +0x52724*4+0x02000000,0x4728); +reg_write( DDR_REG_BASE +0x52725*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52726*4+0x02000000,0xc051); +reg_write( DDR_REG_BASE +0x52727*4+0x02000000,0x9be); +reg_write( DDR_REG_BASE +0x52728*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52729*4+0x02000000,0xc012); +reg_write( DDR_REG_BASE +0x5272a*4+0x02000000,0xc05a); +reg_write( DDR_REG_BASE +0x5272b*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x5272c*4+0x02000000,0x3e40); +reg_write( DDR_REG_BASE +0x5272d*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5272e*4+0x02000000,0xa36); +reg_write( DDR_REG_BASE +0x5272f*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x52730*4+0x02000000,0xdab4); +reg_write( DDR_REG_BASE +0x52731*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x52732*4+0x02000000,0x3840); +reg_write( DDR_REG_BASE +0x52733*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52734*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52735*4+0x02000000,0x444); +reg_write( DDR_REG_BASE +0x52736*4+0x02000000,0xa16); +reg_write( DDR_REG_BASE +0x52737*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52738*4+0x02000000,0xda60); +reg_write( DDR_REG_BASE +0x52739*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x5273a*4+0x02000000,0x3840); +reg_write( DDR_REG_BASE +0x5273b*4+0x02000000,0xb16); +reg_write( DDR_REG_BASE +0x5273c*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x5273d*4+0x02000000,0xd960); +reg_write( DDR_REG_BASE +0x5273e*4+0x02000000,0x146c); +reg_write( DDR_REG_BASE +0x5273f*4+0x02000000,0x3600); +reg_write( DDR_REG_BASE +0x52740*4+0x02000000,0x71cd); +reg_write( DDR_REG_BASE +0x52741*4+0x02000000,0xc04e); +reg_write( DDR_REG_BASE +0x52742*4+0x02000000,0x146b); +reg_write( DDR_REG_BASE +0x52743*4+0x02000000,0x3600); +reg_write( DDR_REG_BASE +0x52744*4+0x02000000,0xc04f); +reg_write( DDR_REG_BASE +0x52745*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x52746*4+0x02000000,0x6d21); +reg_write( DDR_REG_BASE +0x52747*4+0x02000000,0x259a); +reg_write( DDR_REG_BASE +0x52748*4+0x02000000,0x1008); +reg_write( DDR_REG_BASE +0x52749*4+0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x5274a*4+0x02000000,0xe805); +reg_write( DDR_REG_BASE +0x5274b*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x5274c*4+0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x5274d*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x5274e*4+0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x5274f*4+0x02000000,0x2505); +reg_write( DDR_REG_BASE +0x52750*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x52751*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52752*4+0x02000000,0xe0c4); +reg_write( DDR_REG_BASE +0x52753*4+0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x52754*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x52755*4+0x02000000,0xde5); +reg_write( DDR_REG_BASE +0x52756*4+0x02000000,0x9234); +reg_write( DDR_REG_BASE +0x52757*4+0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x52758*4+0x02000000,0x17c0); +reg_write( DDR_REG_BASE +0x52759*4+0x02000000,0xc012); +reg_write( DDR_REG_BASE +0x5275a*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x5275b*4+0x02000000,0x7c1); +reg_write( DDR_REG_BASE +0x5275c*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x5275d*4+0x02000000,0xe906); +reg_write( DDR_REG_BASE +0x5275e*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x5275f*4+0x02000000,0x901); +reg_write( DDR_REG_BASE +0x52760*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x52761*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52762*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52763*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52764*4+0x02000000,0x91a); +reg_write( DDR_REG_BASE +0x52765*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x52766*4+0x02000000,0xc059); +reg_write( DDR_REG_BASE +0x52767*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52768*4+0x02000000,0xc06d); +reg_write( DDR_REG_BASE +0x52769*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5276a*4+0x02000000,0xc04c); +reg_write( DDR_REG_BASE +0x5276b*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5276c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5276d*4+0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x5276e*4+0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x5276f*4+0x02000000,0xd840); +reg_write( DDR_REG_BASE +0x52770*4+0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x52771*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x52772*4+0x02000000,0x3e40); +reg_write( DDR_REG_BASE +0x52773*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x52774*4+0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x52775*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52776*4+0x02000000,0x708c); +reg_write( DDR_REG_BASE +0x52777*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52778*4+0x02000000,0x7b4); +reg_write( DDR_REG_BASE +0x52779*4+0x02000000,0xc748); +reg_write( DDR_REG_BASE +0x5277a*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x5277b*4+0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x5277c*4+0x02000000,0x1c1c); +reg_write( DDR_REG_BASE +0x5277d*4+0x02000000,0x3183); +reg_write( DDR_REG_BASE +0x5277e*4+0x02000000,0x1c24); +reg_write( DDR_REG_BASE +0x5277f*4+0x02000000,0x3384); +reg_write( DDR_REG_BASE +0x52780*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52781*4+0x02000000,0xc012); +reg_write( DDR_REG_BASE +0x52782*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52783*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52784*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52785*4+0x02000000,0x7b4); +reg_write( DDR_REG_BASE +0x52786*4+0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x52787*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52788*4+0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x52789*4+0x02000000,0x205a); +reg_write( DDR_REG_BASE +0x5278a*4+0x02000000,0x402); +reg_write( DDR_REG_BASE +0x5278b*4+0x02000000,0x7074); +reg_write( DDR_REG_BASE +0x5278c*4+0x02000000,0xc39d); +reg_write( DDR_REG_BASE +0x5278d*4+0x02000000,0x22ce); +reg_write( DDR_REG_BASE +0x5278e*4+0x02000000,0x21); +reg_write( DDR_REG_BASE +0x5278f*4+0x02000000,0x631b); +reg_write( DDR_REG_BASE +0x52790*4+0x02000000,0xab40); +reg_write( DDR_REG_BASE +0x52791*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52792*4+0x02000000,0x8ef); +reg_write( DDR_REG_BASE +0x52793*4+0x02000000,0x8134); +reg_write( DDR_REG_BASE +0x52794*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x52795*4+0x02000000,0x43); +reg_write( DDR_REG_BASE +0x52796*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x52797*4+0x02000000,0x6c2); +reg_write( DDR_REG_BASE +0x52798*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x52799*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5279a*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5279b*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5279c*4+0x02000000,0x781d); +reg_write( DDR_REG_BASE +0x5279d*4+0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x5279e*4+0x02000000,0x2306); +reg_write( DDR_REG_BASE +0x5279f*4+0x02000000,0x3000); +reg_write( DDR_REG_BASE +0x527a0*4+0x02000000,0xc055); +reg_write( DDR_REG_BASE +0x527a1*4+0x02000000,0xc011); +reg_write( DDR_REG_BASE +0x527a2*4+0x02000000,0x245f); +reg_write( DDR_REG_BASE +0x527a3*4+0x02000000,0x124e); +reg_write( DDR_REG_BASE +0x527a4*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x527a5*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x527a6*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x527a7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x527a8*4+0x02000000,0xc05b); +reg_write( DDR_REG_BASE +0x527a9*4+0x02000000,0x215f); +reg_write( DDR_REG_BASE +0x527aa*4+0x02000000,0x240); +reg_write( DDR_REG_BASE +0x527ab*4+0x02000000,0xe008); +reg_write( DDR_REG_BASE +0x527ac*4+0x02000000,0xc058); +reg_write( DDR_REG_BASE +0x527ad*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x527ae*4+0x02000000,0xf0b1); +reg_write( DDR_REG_BASE +0x527af*4+0x02000000,0xcaa); +reg_write( DDR_REG_BASE +0x527b0*4+0x02000000,0xff2f); +reg_write( DDR_REG_BASE +0x527b1*4+0x02000000,0xc083); +reg_write( DDR_REG_BASE +0x527b2*4+0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x527b3*4+0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x527b4*4+0x02000000,0xc20f); +reg_write( DDR_REG_BASE +0x527b5*4+0x02000000,0x7a34); +reg_write( DDR_REG_BASE +0x527b6*4+0x02000000,0x9200); +reg_write( DDR_REG_BASE +0x527b7*4+0x02000000,0xe88d); +reg_write( DDR_REG_BASE +0x527b8*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x527b9*4+0x02000000,0x3e40); +reg_write( DDR_REG_BASE +0x527ba*4+0x02000000,0x20f4); +reg_write( DDR_REG_BASE +0x527bb*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x527bc*4+0x02000000,0x2042); +reg_write( DDR_REG_BASE +0x527bd*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x527be*4+0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x527bf*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x527c0*4+0x02000000,0x6); +reg_write( DDR_REG_BASE +0x527c1*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x527c2*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x527c3*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x527c4*4+0x02000000,0xc018); +reg_write( DDR_REG_BASE +0x527c5*4+0x02000000,0x8e1); +reg_write( DDR_REG_BASE +0x527c6*4+0x02000000,0x8065); +reg_write( DDR_REG_BASE +0x527c7*4+0x02000000,0xc083); +reg_write( DDR_REG_BASE +0x527c8*4+0x02000000,0xe92); +reg_write( DDR_REG_BASE +0x527c9*4+0x02000000,0xff0f); +reg_write( DDR_REG_BASE +0x527ca*4+0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x527cb*4+0x02000000,0xf010); +reg_write( DDR_REG_BASE +0x527cc*4+0x02000000,0xc20e); +reg_write( DDR_REG_BASE +0x527cd*4+0x02000000,0x7a34); +reg_write( DDR_REG_BASE +0x527ce*4+0x02000000,0x9200); +reg_write( DDR_REG_BASE +0x527cf*4+0x02000000,0x817); +reg_write( DDR_REG_BASE +0x527d0*4+0x02000000,0xff1); +reg_write( DDR_REG_BASE +0x527d1*4+0x02000000,0x2455); +reg_write( DDR_REG_BASE +0x527d2*4+0x02000000,0x3e40); +reg_write( DDR_REG_BASE +0x527d3*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x527d4*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x527d5*4+0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x527d6*4+0x02000000,0x832); +reg_write( DDR_REG_BASE +0x527d7*4+0x02000000,0xe020); +reg_write( DDR_REG_BASE +0x527d8*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x527d9*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x527da*4+0x02000000,0xc018); +reg_write( DDR_REG_BASE +0x527db*4+0x02000000,0x8e5); +reg_write( DDR_REG_BASE +0x527dc*4+0x02000000,0x8065); +reg_write( DDR_REG_BASE +0x527dd*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x527de*4+0x02000000,0xc013); +reg_write( DDR_REG_BASE +0x527df*4+0x02000000,0xc651); +reg_write( DDR_REG_BASE +0x527e0*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x527e1*4+0x02000000,0xc05c); +reg_write( DDR_REG_BASE +0x527e2*4+0x02000000,0x7314); +reg_write( DDR_REG_BASE +0x527e3*4+0x02000000,0xc015); +reg_write( DDR_REG_BASE +0x527e4*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x527e5*4+0x02000000,0x61); +reg_write( DDR_REG_BASE +0x527e6*4+0x02000000,0xc055); +reg_write( DDR_REG_BASE +0x527e7*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x527e8*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x527e9*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x527ea*4+0x02000000,0x7b4); +reg_write( DDR_REG_BASE +0x527eb*4+0x02000000,0xc054); +reg_write( DDR_REG_BASE +0x527ec*4+0x02000000,0xf064); +reg_write( DDR_REG_BASE +0x527ed*4+0x02000000,0x722c); +reg_write( DDR_REG_BASE +0x527ee*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x527ef*4+0x02000000,0xf05d); +reg_write( DDR_REG_BASE +0x527f0*4+0x02000000,0xc011); +reg_write( DDR_REG_BASE +0x527f1*4+0x02000000,0xf15); +reg_write( DDR_REG_BASE +0x527f2*4+0x02000000,0x1231); +reg_write( DDR_REG_BASE +0x527f3*4+0x02000000,0x7a10); +reg_write( DDR_REG_BASE +0x527f4*4+0x02000000,0xc010); +reg_write( DDR_REG_BASE +0x527f5*4+0x02000000,0x7854); +reg_write( DDR_REG_BASE +0x527f6*4+0x02000000,0x10f0); +reg_write( DDR_REG_BASE +0x527f7*4+0x02000000,0x8102); +reg_write( DDR_REG_BASE +0x527f8*4+0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x527f9*4+0x02000000,0xf04f); +reg_write( DDR_REG_BASE +0x527fa*4+0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x527fb*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x527fc*4+0x02000000,0x83); +reg_write( DDR_REG_BASE +0x527fd*4+0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x527fe*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x527ff*4+0x02000000,0x8c); +reg_write( DDR_REG_BASE +0x52800*4+0x02000000,0x4c70); +reg_write( DDR_REG_BASE +0x52801*4+0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x52802*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52803*4+0x02000000,0x7d0e); +reg_write( DDR_REG_BASE +0x52804*4+0x02000000,0xd77); +reg_write( DDR_REG_BASE +0x52805*4+0x02000000,0x11b3); +reg_write( DDR_REG_BASE +0x52806*4+0x02000000,0x43a9); +reg_write( DDR_REG_BASE +0x52807*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x52808*4+0x02000000,0x203c); +reg_write( DDR_REG_BASE +0x52809*4+0x02000000,0x3cd); +reg_write( DDR_REG_BASE +0x5280a*4+0x02000000,0x97b); +reg_write( DDR_REG_BASE +0x5280b*4+0x02000000,0x360); +reg_write( DDR_REG_BASE +0x5280c*4+0x02000000,0x43e1); +reg_write( DDR_REG_BASE +0x5280d*4+0x02000000,0xc015); +reg_write( DDR_REG_BASE +0x5280e*4+0x02000000,0xc216); +reg_write( DDR_REG_BASE +0x5280f*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52810*4+0x02000000,0x1c); +reg_write( DDR_REG_BASE +0x52811*4+0x02000000,0x3); +reg_write( DDR_REG_BASE +0x52812*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52813*4+0x02000000,0x2078); +reg_write( DDR_REG_BASE +0x52814*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52815*4+0x02000000,0x8c6); +reg_write( DDR_REG_BASE +0x52816*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52817*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x52818*4+0x02000000,0x32c0); +reg_write( DDR_REG_BASE +0x52819*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x5281a*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x5281b*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5281c*4+0x02000000,0x716f); +reg_write( DDR_REG_BASE +0x5281d*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x5281e*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x5281f*4+0x02000000,0x37fe); +reg_write( DDR_REG_BASE +0x52820*4+0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x52821*4+0x02000000,0xc01a); +reg_write( DDR_REG_BASE +0x52822*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x52823*4+0x02000000,0x8c2); +reg_write( DDR_REG_BASE +0x52824*4+0x02000000,0xc01b); +reg_write( DDR_REG_BASE +0x52825*4+0x02000000,0x7a05); +reg_write( DDR_REG_BASE +0x52826*4+0x02000000,0xc016); +reg_write( DDR_REG_BASE +0x52827*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x52828*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52829*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5282a*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x5282b*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x5282c*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x5282d*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x5282e*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x5282f*4+0x02000000,0xf82); +reg_write( DDR_REG_BASE +0x52830*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52831*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52832*4+0x02000000,0x9260); +reg_write( DDR_REG_BASE +0x52833*4+0x02000000,0xc01c); +reg_write( DDR_REG_BASE +0x52834*4+0x02000000,0xc19d); +reg_write( DDR_REG_BASE +0x52835*4+0x02000000,0x2133); +reg_write( DDR_REG_BASE +0x52836*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52837*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x52838*4+0x02000000,0x6078); +reg_write( DDR_REG_BASE +0x52839*4+0x02000000,0x780e); +reg_write( DDR_REG_BASE +0x5283a*4+0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x5283b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5283c*4+0x02000000,0x2049); +reg_write( DDR_REG_BASE +0x5283d*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x5283e*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x5283f*4+0x02000000,0xc010); +reg_write( DDR_REG_BASE +0x52840*4+0x02000000,0x2014); +reg_write( DDR_REG_BASE +0x52841*4+0x02000000,0x82); +reg_write( DDR_REG_BASE +0x52842*4+0x02000000,0x6478); +reg_write( DDR_REG_BASE +0x52843*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x52844*4+0x02000000,0x2048); +reg_write( DDR_REG_BASE +0x52845*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52846*4+0x02000000,0xb200); +reg_write( DDR_REG_BASE +0x52847*4+0x02000000,0xc011); +reg_write( DDR_REG_BASE +0x52848*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x52849*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5284a*4+0x02000000,0xc051); +reg_write( DDR_REG_BASE +0x5284b*4+0x02000000,0xf4d); +reg_write( DDR_REG_BASE +0x5284c*4+0x02000000,0x9254); +reg_write( DDR_REG_BASE +0x5284d*4+0x02000000,0xc014); +reg_write( DDR_REG_BASE +0x5284e*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5284f*4+0x02000000,0xc054); +reg_write( DDR_REG_BASE +0x52850*4+0x02000000,0xc014); +reg_write( DDR_REG_BASE +0x52851*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52852*4+0x02000000,0xc056); +reg_write( DDR_REG_BASE +0x52853*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52854*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52855*4+0x02000000,0x7b4); +reg_write( DDR_REG_BASE +0x52856*4+0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x52857*4+0x02000000,0xc016); +reg_write( DDR_REG_BASE +0x52858*4+0x02000000,0x92b); +reg_write( DDR_REG_BASE +0x52859*4+0x02000000,0x8025); +reg_write( DDR_REG_BASE +0x5285a*4+0x02000000,0x7077); +reg_write( DDR_REG_BASE +0x5285b*4+0x02000000,0xd64); +reg_write( DDR_REG_BASE +0x5285c*4+0x02000000,0xfec2); +reg_write( DDR_REG_BASE +0x5285d*4+0x02000000,0xc013); +reg_write( DDR_REG_BASE +0x5285e*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x5285f*4+0x02000000,0xc053); +reg_write( DDR_REG_BASE +0x52860*4+0x02000000,0x7077); +reg_write( DDR_REG_BASE +0x52861*4+0x02000000,0xf54f); +reg_write( DDR_REG_BASE +0x52862*4+0x02000000,0xc017); +reg_write( DDR_REG_BASE +0x52863*4+0x02000000,0xe837); +reg_write( DDR_REG_BASE +0x52864*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52865*4+0x02000000,0x1d); +reg_write( DDR_REG_BASE +0x52866*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52867*4+0x02000000,0xf96); +reg_write( DDR_REG_BASE +0x52868*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52869*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x5286a*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x5286b*4+0x02000000,0x709b); +reg_write( DDR_REG_BASE +0x5286c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x5286d*4+0x02000000,0x7b4); +reg_write( DDR_REG_BASE +0x5286e*4+0x02000000,0xf022); +reg_write( DDR_REG_BASE +0x5286f*4+0x02000000,0xd39); +reg_write( DDR_REG_BASE +0x52870*4+0x02000000,0x1230); +reg_write( DDR_REG_BASE +0x52871*4+0x02000000,0x78db); +reg_write( DDR_REG_BASE +0x52872*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52873*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52874*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52875*4+0x02000000,0xfffe); +reg_write( DDR_REG_BASE +0x52876*4+0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x52877*4+0x02000000,0x2035); +reg_write( DDR_REG_BASE +0x52878*4+0x02000000,0x42); +reg_write( DDR_REG_BASE +0x52879*4+0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x5287a*4+0x02000000,0x2035); +reg_write( DDR_REG_BASE +0x5287b*4+0x02000000,0x43); +reg_write( DDR_REG_BASE +0x5287c*4+0x02000000,0xc010); +reg_write( DDR_REG_BASE +0x5287d*4+0x02000000,0x2035); +reg_write( DDR_REG_BASE +0x5287e*4+0x02000000,0x40); +reg_write( DDR_REG_BASE +0x5287f*4+0x02000000,0xc341); +reg_write( DDR_REG_BASE +0x52880*4+0x02000000,0xc240); +reg_write( DDR_REG_BASE +0x52881*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52882*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x52883*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52884*4+0x02000000,0x1f); +reg_write( DDR_REG_BASE +0x52885*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x52886*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x52887*4+0x02000000,0xf56); +reg_write( DDR_REG_BASE +0x52888*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52889*4+0x02000000,0x43a1); +reg_write( DDR_REG_BASE +0x5288a*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x5288b*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x5288c*4+0x02000000,0xdc7); +reg_write( DDR_REG_BASE +0x5288d*4+0x02000000,0x9254); +reg_write( DDR_REG_BASE +0x5288e*4+0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x5288f*4+0x02000000,0x7ed0); +reg_write( DDR_REG_BASE +0x52890*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52891*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52892*4+0x02000000,0x7b4); +reg_write( DDR_REG_BASE +0x52893*4+0x02000000,0x8801); +reg_write( DDR_REG_BASE +0x52894*4+0x02000000,0x272f); +reg_write( DDR_REG_BASE +0x52895*4+0x02000000,0x16c7); +reg_write( DDR_REG_BASE +0x52896*4+0x02000000,0x8ed); +reg_write( DDR_REG_BASE +0x52897*4+0x02000000,0x83e5); +reg_write( DDR_REG_BASE +0x52898*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52899*4+0x02000000,0xc9a); +reg_write( DDR_REG_BASE +0x5289a*4+0x02000000,0xfeaf); +reg_write( DDR_REG_BASE +0x5289b*4+0x02000000,0xc019); +reg_write( DDR_REG_BASE +0x5289c*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5289d*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5289e*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x5289f*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x528a0*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x528a1*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x528a2*4+0x02000000,0x7082); +reg_write( DDR_REG_BASE +0x528a3*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x528a4*4+0x02000000,0x7b4); +reg_write( DDR_REG_BASE +0x528a5*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x528a6*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x528a7*4+0x02000000,0x7b4); +reg_write( DDR_REG_BASE +0x528a8*4+0x02000000,0x8821); +reg_write( DDR_REG_BASE +0x528a9*4+0x02000000,0x225f); +reg_write( DDR_REG_BASE +0x528aa*4+0x02000000,0x243); +reg_write( DDR_REG_BASE +0x528ab*4+0x02000000,0xf02e); +reg_write( DDR_REG_BASE +0x528ac*4+0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x528ad*4+0x02000000,0x30c0); +reg_write( DDR_REG_BASE +0x528ae*4+0x02000000,0xf026); +reg_write( DDR_REG_BASE +0x528af*4+0x02000000,0xc010); +reg_write( DDR_REG_BASE +0x528b0*4+0x02000000,0x20f5); +reg_write( DDR_REG_BASE +0x528b1*4+0x02000000,0x78e); +reg_write( DDR_REG_BASE +0x528b2*4+0x02000000,0x2640); +reg_write( DDR_REG_BASE +0x528b3*4+0x02000000,0x305e); +reg_write( DDR_REG_BASE +0x528b4*4+0x02000000,0x78dc); +reg_write( DDR_REG_BASE +0x528b5*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x528b6*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x528b7*4+0x02000000,0x781c); +reg_write( DDR_REG_BASE +0x528b8*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x528b9*4+0x02000000,0xd81b); +reg_write( DDR_REG_BASE +0x528ba*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x528bb*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x528bc*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x528bd*4+0x02000000,0x7dbd); +reg_write( DDR_REG_BASE +0x528be*4+0x02000000,0x66b8); +reg_write( DDR_REG_BASE +0x528bf*4+0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x528c0*4+0x02000000,0x48b5); +reg_write( DDR_REG_BASE +0x528c1*4+0x02000000,0x2e44); +reg_write( DDR_REG_BASE +0x528c2*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x528c3*4+0x02000000,0x6cc1); +reg_write( DDR_REG_BASE +0x528c4*4+0x02000000,0x249a); +reg_write( DDR_REG_BASE +0x528c5*4+0x02000000,0x1008); +reg_write( DDR_REG_BASE +0x528c6*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x528c7*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x528c8*4+0x02000000,0x7d05); +reg_write( DDR_REG_BASE +0x528c9*4+0x02000000,0x221a); +reg_write( DDR_REG_BASE +0x528ca*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x528cb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x528cc*4+0x02000000,0x2000); +reg_write( DDR_REG_BASE +0x528cd*4+0x02000000,0x7885); +reg_write( DDR_REG_BASE +0x528ce*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x528cf*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x528d0*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x528d1*4+0x02000000,0x64); +reg_write( DDR_REG_BASE +0x528d2*4+0x02000000,0xb0a0); +reg_write( DDR_REG_BASE +0x528d3*4+0x02000000,0x44c9); +reg_write( DDR_REG_BASE +0x528d4*4+0x02000000,0xcb7); +reg_write( DDR_REG_BASE +0x528d5*4+0x02000000,0x9214); +reg_write( DDR_REG_BASE +0x528d6*4+0x02000000,0x7144); +reg_write( DDR_REG_BASE +0x528d7*4+0x02000000,0xe309); +reg_write( DDR_REG_BASE +0x528d8*4+0x02000000,0x9a9); +reg_write( DDR_REG_BASE +0x528d9*4+0x02000000,0x80a5); +reg_write( DDR_REG_BASE +0x528da*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x528db*4+0x02000000,0xc00e); +reg_write( DDR_REG_BASE +0x528dc*4+0x02000000,0xc117); +reg_write( DDR_REG_BASE +0x528dd*4+0x02000000,0xc210); +reg_write( DDR_REG_BASE +0x528de*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x528df*4+0x02000000,0xc012); +reg_write( DDR_REG_BASE +0x528e0*4+0x02000000,0x95e); +reg_write( DDR_REG_BASE +0x528e1*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x528e2*4+0x02000000,0xc30f); +reg_write( DDR_REG_BASE +0x528e3*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x528e4*4+0x02000000,0x3606); +reg_write( DDR_REG_BASE +0x528e5*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x528e6*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x528e7*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x528e8*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x528e9*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x528ea*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x528eb*4+0x02000000,0xc1a8); +reg_write( DDR_REG_BASE +0x528ec*4+0x02000000,0xfca); +reg_write( DDR_REG_BASE +0x528ed*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x528ee*4+0x02000000,0x4708); +reg_write( DDR_REG_BASE +0x528ef*4+0x02000000,0x83e); +reg_write( DDR_REG_BASE +0x528f0*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x528f1*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x528f2*4+0x02000000,0x896); +reg_write( DDR_REG_BASE +0x528f3*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x528f4*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x528f5*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x528f6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x528f7*4+0x02000000,0xcccc); +reg_write( DDR_REG_BASE +0x528f8*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x528f9*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x528fa*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x528fb*4+0x02000000,0x4220); +reg_write( DDR_REG_BASE +0x528fc*4+0x02000000,0x4568); +reg_write( DDR_REG_BASE +0x528fd*4+0x02000000,0x94a); +reg_write( DDR_REG_BASE +0x528fe*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x528ff*4+0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x52900*4+0x02000000,0xd808); +reg_write( DDR_REG_BASE +0x52901*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52902*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52903*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x52904*4+0x02000000,0x93a); +reg_write( DDR_REG_BASE +0x52905*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x52906*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52907*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52908*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52909*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x5290a*4+0x02000000,0xc105); +reg_write( DDR_REG_BASE +0x5290b*4+0x02000000,0x9fe); +reg_write( DDR_REG_BASE +0x5290c*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5290d*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x5290e*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x5290f*4+0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x52910*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52911*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52912*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52913*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52914*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52915*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52916*4+0x02000000,0xabe); +reg_write( DDR_REG_BASE +0x52917*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52918*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52919*4+0x02000000,0x7fef); +reg_write( DDR_REG_BASE +0x5291a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5291b*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5291c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5291d*4+0x02000000,0x4400); +reg_write( DDR_REG_BASE +0x5291e*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5291f*4+0x02000000,0xdb7c); +reg_write( DDR_REG_BASE +0x52920*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x52921*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x52922*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52923*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52924*4+0x02000000,0xaa2); +reg_write( DDR_REG_BASE +0x52925*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52926*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52927*4+0x02000000,0xca08); +reg_write( DDR_REG_BASE +0x52928*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52929*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5292a*4+0x02000000,0x7500); +reg_write( DDR_REG_BASE +0x5292b*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x5292c*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x5292d*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5292e*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x5292f*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52930*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52931*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52932*4+0x02000000,0xa86); +reg_write( DDR_REG_BASE +0x52933*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52934*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x52935*4+0x02000000,0xb46); +reg_write( DDR_REG_BASE +0x52936*4+0x02000000,0xfe0f); +reg_write( DDR_REG_BASE +0x52937*4+0x02000000,0x2644); +reg_write( DDR_REG_BASE +0x52938*4+0x02000000,0x1040); +reg_write( DDR_REG_BASE +0x52939*4+0x02000000,0x60d8); +reg_write( DDR_REG_BASE +0x5293a*4+0x02000000,0xe010); +reg_write( DDR_REG_BASE +0x5293b*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x5293c*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x5293d*4+0x02000000,0xc306); +reg_write( DDR_REG_BASE +0x5293e*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5293f*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x52940*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52941*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52942*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52943*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52944*4+0x02000000,0xa62); +reg_write( DDR_REG_BASE +0x52945*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52946*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52947*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52948*4+0x02000000,0xa1a); +reg_write( DDR_REG_BASE +0x52949*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5294a*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5294b*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5294c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5294d*4+0x02000000,0x3333); +reg_write( DDR_REG_BASE +0x5294e*4+0x02000000,0x43c3); +reg_write( DDR_REG_BASE +0x5294f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52950*4+0x02000000,0x9999); +reg_write( DDR_REG_BASE +0x52951*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52952*4+0x02000000,0x4220); +reg_write( DDR_REG_BASE +0x52953*4+0x02000000,0x89e); +reg_write( DDR_REG_BASE +0x52954*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x52955*4+0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x52956*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52957*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52958*4+0x02000000,0xaaaa); +reg_write( DDR_REG_BASE +0x52959*4+0x02000000,0xd808); +reg_write( DDR_REG_BASE +0x5295a*4+0x02000000,0x4220); +reg_write( DDR_REG_BASE +0x5295b*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x5295c*4+0x02000000,0x88a); +reg_write( DDR_REG_BASE +0x5295d*4+0x02000000,0xfe6f); +reg_write( DDR_REG_BASE +0x5295e*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5295f*4+0x02000000,0xc105); +reg_write( DDR_REG_BASE +0x52960*4+0x02000000,0x952); +reg_write( DDR_REG_BASE +0x52961*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52962*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52963*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x52964*4+0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x52965*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52966*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52967*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52968*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52969*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5296a*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5296b*4+0x02000000,0xa16); +reg_write( DDR_REG_BASE +0x5296c*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5296d*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5296e*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x5296f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52970*4+0x02000000,0x4400); +reg_write( DDR_REG_BASE +0x52971*4+0x02000000,0xbeaa); +reg_write( DDR_REG_BASE +0x52972*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52973*4+0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x52974*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52975*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x52976*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52977*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52978*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52979*4+0x02000000,0x9fa); +reg_write( DDR_REG_BASE +0x5297a*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5297b*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5297c*4+0x02000000,0xca08); +reg_write( DDR_REG_BASE +0x5297d*4+0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x5297e*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x5297f*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52980*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52981*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52982*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52983*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52984*4+0x02000000,0x9e2); +reg_write( DDR_REG_BASE +0x52985*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52986*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52987*4+0x02000000,0xaa2); +reg_write( DDR_REG_BASE +0x52988*4+0x02000000,0xfe0f); +reg_write( DDR_REG_BASE +0x52989*4+0x02000000,0xc306); +reg_write( DDR_REG_BASE +0x5298a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5298b*4+0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x5298c*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5298d*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5298e*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5298f*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52990*4+0x02000000,0x9ca); +reg_write( DDR_REG_BASE +0x52991*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52992*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52993*4+0x02000000,0xca08); +reg_write( DDR_REG_BASE +0x52994*4+0x02000000,0x2350); +reg_write( DDR_REG_BASE +0x52995*4+0x02000000,0x3301); +reg_write( DDR_REG_BASE +0x52996*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52997*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52998*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52999*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x5299a*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x5299b*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5299c*4+0x02000000,0x9b2); +reg_write( DDR_REG_BASE +0x5299d*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x5299e*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5299f*4+0x02000000,0xc104); +reg_write( DDR_REG_BASE +0x529a0*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x529a1*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x529a2*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x529a3*4+0x02000000,0x2014); +reg_write( DDR_REG_BASE +0x529a4*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x529a5*4+0x02000000,0x4958); +reg_write( DDR_REG_BASE +0x529a6*4+0x02000000,0xb8c0); +reg_write( DDR_REG_BASE +0x529a7*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x529a8*4+0x02000000,0xe028); +reg_write( DDR_REG_BASE +0x529a9*4+0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x529aa*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x529ab*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x529ac*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x529ad*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x529ae*4+0x02000000,0x98e); +reg_write( DDR_REG_BASE +0x529af*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x529b0*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x529b1*4+0x02000000,0x79db); +reg_write( DDR_REG_BASE +0x529b2*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x529b3*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x529b4*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x529b5*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x529b6*4+0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x529b7*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x529b8*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x529b9*4+0x02000000,0x97a); +reg_write( DDR_REG_BASE +0x529ba*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x529bb*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x529bc*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x529bd*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x529be*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x529bf*4+0x02000000,0xdb10); +reg_write( DDR_REG_BASE +0x529c0*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x529c1*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x529c2*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x529c3*4+0x02000000,0x966); +reg_write( DDR_REG_BASE +0x529c4*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x529c5*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x529c6*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x529c7*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x529c8*4+0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x529c9*4+0x02000000,0xdb26); +reg_write( DDR_REG_BASE +0x529ca*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x529cb*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x529cc*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x529cd*4+0x02000000,0x952); +reg_write( DDR_REG_BASE +0x529ce*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x529cf*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x529d0*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x529d1*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x529d2*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x529d3*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x529d4*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x529d5*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x529d6*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x529d7*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x529d8*4+0x02000000,0x93a); +reg_write( DDR_REG_BASE +0x529d9*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x529da*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x529db*4+0x02000000,0xc0a8); +reg_write( DDR_REG_BASE +0x529dc*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x529dd*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x529de*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x529df*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x529e0*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x529e1*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x529e2*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x529e3*4+0x02000000,0xc1a6); +reg_write( DDR_REG_BASE +0x529e4*4+0x02000000,0xc144); +reg_write( DDR_REG_BASE +0x529e5*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x529e6*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x529e7*4+0x02000000,0x7b0); +reg_write( DDR_REG_BASE +0x529e8*4+0x02000000,0x8920); +reg_write( DDR_REG_BASE +0x529e9*4+0x02000000,0x4358); +reg_write( DDR_REG_BASE +0x529ea*4+0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x529eb*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x529ec*4+0x02000000,0xf206); +reg_write( DDR_REG_BASE +0x529ed*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x529ee*4+0x02000000,0x708f); +reg_write( DDR_REG_BASE +0x529ef*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x529f0*4+0x02000000,0x49); +reg_write( DDR_REG_BASE +0x529f1*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x529f2*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x529f3*4+0x02000000,0x708f); +reg_write( DDR_REG_BASE +0x529f4*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x529f5*4+0x02000000,0x23); +reg_write( DDR_REG_BASE +0x529f6*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x529f7*4+0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x529f8*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x529f9*4+0x02000000,0xea06); +reg_write( DDR_REG_BASE +0x529fa*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x529fb*4+0x02000000,0xa01); +reg_write( DDR_REG_BASE +0x529fc*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x529fd*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x529fe*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x529ff*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52a00*4+0x02000000,0x812); +reg_write( DDR_REG_BASE +0x52a01*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52a02*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52a03*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x52a04*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52a05*4+0x02000000,0xf02a); +reg_write( DDR_REG_BASE +0x52a06*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52a07*4+0x02000000,0x2012); +reg_write( DDR_REG_BASE +0x52a08*4+0x02000000,0x340); +reg_write( DDR_REG_BASE +0x52a09*4+0x02000000,0x262f); +reg_write( DDR_REG_BASE +0x52a0a*4+0x02000000,0xf007); +reg_write( DDR_REG_BASE +0x52a0b*4+0x02000000,0xf47); +reg_write( DDR_REG_BASE +0x52a0c*4+0x02000000,0x136e); +reg_write( DDR_REG_BASE +0x52a0d*4+0x02000000,0x26ca); +reg_write( DDR_REG_BASE +0x52a0e*4+0x02000000,0x1341); +reg_write( DDR_REG_BASE +0x52a0f*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52a10*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x52a11*4+0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x52a12*4+0x02000000,0x17c0); +reg_write( DDR_REG_BASE +0x52a13*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x52a14*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x52a15*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x52a16*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x52a17*4+0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x52a18*4+0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x52a19*4+0x02000000,0x1c81); +reg_write( DDR_REG_BASE +0x52a1a*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52a1b*4+0x02000000,0x7077); +reg_write( DDR_REG_BASE +0x52a1c*4+0x02000000,0xdb18); +reg_write( DDR_REG_BASE +0x52a1d*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x52a1e*4+0x02000000,0x880b); +reg_write( DDR_REG_BASE +0x52a1f*4+0x02000000,0x794f); +reg_write( DDR_REG_BASE +0x52a20*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x52a21*4+0x02000000,0x20ec); +reg_write( DDR_REG_BASE +0x52a22*4+0x02000000,0x62); +reg_write( DDR_REG_BASE +0x52a23*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52a24*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52a25*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52a26*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x52a27*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x52a28*4+0x02000000,0x3001); +reg_write( DDR_REG_BASE +0x52a29*4+0x02000000,0xa1a); +reg_write( DDR_REG_BASE +0x52a2a*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52a2b*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x52a2c*4+0x02000000,0x32c1); +reg_write( DDR_REG_BASE +0x52a2d*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x52a2e*4+0x02000000,0xdb1); +reg_write( DDR_REG_BASE +0x52a2f*4+0x02000000,0x90b4); +reg_write( DDR_REG_BASE +0x52a30*4+0x02000000,0x7077); +reg_write( DDR_REG_BASE +0x52a31*4+0x02000000,0x265a); +reg_write( DDR_REG_BASE +0x52a32*4+0x02000000,0x1c8e); +reg_write( DDR_REG_BASE +0x52a33*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52a34*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x52a35*4+0x02000000,0x60d8); +reg_write( DDR_REG_BASE +0x52a36*4+0x02000000,0x8822); +reg_write( DDR_REG_BASE +0x52a37*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52a38*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52a39*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52a3a*4+0x02000000,0x21cf); +reg_write( DDR_REG_BASE +0x52a3b*4+0x02000000,0x1e2); +reg_write( DDR_REG_BASE +0x52a3c*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x52a3d*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52a3e*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52a3f*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52a40*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52a41*4+0x02000000,0xdb18); +reg_write( DDR_REG_BASE +0x52a42*4+0x02000000,0x9e6); +reg_write( DDR_REG_BASE +0x52a43*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52a44*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x52a45*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x52a46*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52a47*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52a48*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52a49*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52a4a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52a4b*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52a4c*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52a4d*4+0x02000000,0xdb31); +reg_write( DDR_REG_BASE +0x52a4e*4+0x02000000,0x84e); +reg_write( DDR_REG_BASE +0x52a4f*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52a50*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x52a51*4+0x02000000,0x3401); +reg_write( DDR_REG_BASE +0x52a52*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52a53*4+0x02000000,0xc043); +reg_write( DDR_REG_BASE +0x52a54*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52a55*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52a56*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52a57*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52a58*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x52a59*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52a5a*4+0x02000000,0x836); +reg_write( DDR_REG_BASE +0x52a5b*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52a5c*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52a5d*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52a5e*4+0x02000000,0xfee); +reg_write( DDR_REG_BASE +0x52a5f*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52a60*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52a61*4+0x02000000,0xc0a6); +reg_write( DDR_REG_BASE +0x52a62*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52a63*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52a64*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52a65*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52a66*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52a67*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52a68*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52a69*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x52a6a*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x52a6b*4+0x02000000,0xd46); +reg_write( DDR_REG_BASE +0x52a6c*4+0x02000000,0xfe2f); +reg_write( DDR_REG_BASE +0x52a6d*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x52a6e*4+0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x52a6f*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52a70*4+0x02000000,0xf32); +reg_write( DDR_REG_BASE +0x52a71*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52a72*4+0x02000000,0xd908); +reg_write( DDR_REG_BASE +0x52a73*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x52a74*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52a75*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52a76*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52a77*4+0x02000000,0xdb7c); +reg_write( DDR_REG_BASE +0x52a78*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x52a79*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x52a7a*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x52a7b*4+0x02000000,0xff6); +reg_write( DDR_REG_BASE +0x52a7c*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52a7d*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x52a7e*4+0x02000000,0x9aa); +reg_write( DDR_REG_BASE +0x52a7f*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52a80*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52a81*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x52a82*4+0x02000000,0x3040); +reg_write( DDR_REG_BASE +0x52a83*4+0x02000000,0x7063); +reg_write( DDR_REG_BASE +0x52a84*4+0x02000000,0x2040); +reg_write( DDR_REG_BASE +0x52a85*4+0x02000000,0xb9b); +reg_write( DDR_REG_BASE +0x52a86*4+0x02000000,0xed12); +reg_write( DDR_REG_BASE +0x52a87*4+0x02000000,0xf82c); +reg_write( DDR_REG_BASE +0x52a88*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x52a89*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x52a8a*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x52a8b*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x52a8c*4+0x02000000,0xfd2); +reg_write( DDR_REG_BASE +0x52a8d*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52a8e*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x52a8f*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52a90*4+0x02000000,0xd90c); +reg_write( DDR_REG_BASE +0x52a91*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52a92*4+0x02000000,0x756c); +reg_write( DDR_REG_BASE +0x52a93*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x52a94*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x52a95*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x52a96*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x52a97*4+0x02000000,0xf008); +reg_write( DDR_REG_BASE +0x52a98*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x52a99*4+0x02000000,0x3101); +reg_write( DDR_REG_BASE +0x52a9a*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x52a9b*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x52a9c*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x52a9d*4+0x02000000,0xf821); +reg_write( DDR_REG_BASE +0x52a9e*4+0x02000000,0xfae); +reg_write( DDR_REG_BASE +0x52a9f*4+0x02000000,0xfd8f); +reg_write( DDR_REG_BASE +0x52aa0*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52aa1*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52aa2*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52aa3*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52aa4*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x52aa5*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x52aa6*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x52aa7*4+0x02000000,0xf9e); +reg_write( DDR_REG_BASE +0x52aa8*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52aa9*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x52aaa*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52aab*4+0x02000000,0x232f); +reg_write( DDR_REG_BASE +0x52aac*4+0x02000000,0x6c7); +reg_write( DDR_REG_BASE +0x52aad*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52aae*4+0x02000000,0xd90c); +reg_write( DDR_REG_BASE +0x52aaf*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52ab0*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52ab1*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x52ab2*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52ab3*4+0x02000000,0xf86); +reg_write( DDR_REG_BASE +0x52ab4*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52ab5*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52ab6*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52ab7*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52ab8*4+0x02000000,0xb98f); +reg_write( DDR_REG_BASE +0x52ab9*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52aba*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x52abb*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x52abc*4+0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x52abd*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52abe*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52abf*4+0x02000000,0xf6e); +reg_write( DDR_REG_BASE +0x52ac0*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52ac1*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52ac2*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52ac3*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52ac4*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52ac5*4+0x02000000,0xdb10); +reg_write( DDR_REG_BASE +0x52ac6*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52ac7*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52ac8*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52ac9*4+0x02000000,0xf5a); +reg_write( DDR_REG_BASE +0x52aca*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52acb*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52acc*4+0x02000000,0x8f2); +reg_write( DDR_REG_BASE +0x52acd*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52ace*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52acf*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52ad0*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x52ad1*4+0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x52ad2*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52ad3*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52ad4*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x52ad5*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52ad6*4+0x02000000,0xf3e); +reg_write( DDR_REG_BASE +0x52ad7*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52ad8*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x52ad9*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x52ada*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x52adb*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52adc*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52add*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52ade*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52adf*4+0x02000000,0xd90c); +reg_write( DDR_REG_BASE +0x52ae0*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52ae1*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52ae2*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52ae3*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52ae4*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52ae5*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52ae6*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52ae7*4+0x02000000,0xc1aa); +reg_write( DDR_REG_BASE +0x52ae8*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52ae9*4+0x02000000,0xc00f); +reg_write( DDR_REG_BASE +0x52aea*4+0x02000000,0xc147); +reg_write( DDR_REG_BASE +0x52aeb*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52aec*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52aed*4+0x02000000,0x600); +reg_write( DDR_REG_BASE +0x52aee*4+0x02000000,0x7906); +reg_write( DDR_REG_BASE +0x52aef*4+0x02000000,0xc348); +reg_write( DDR_REG_BASE +0x52af0*4+0x02000000,0xc246); +reg_write( DDR_REG_BASE +0x52af1*4+0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x52af2*4+0x02000000,0xe983); +reg_write( DDR_REG_BASE +0x52af3*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52af4*4+0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x52af5*4+0x02000000,0xd840); +reg_write( DDR_REG_BASE +0x52af6*4+0x02000000,0xe26); +reg_write( DDR_REG_BASE +0x52af7*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52af8*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x52af9*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x52afa*4+0x02000000,0x43f9); +reg_write( DDR_REG_BASE +0x52afb*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52afc*4+0x02000000,0xf03e); +reg_write( DDR_REG_BASE +0x52afd*4+0x02000000,0x2332); +reg_write( DDR_REG_BASE +0x52afe*4+0x02000000,0x3f8e); +reg_write( DDR_REG_BASE +0x52aff*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52b00*4+0x02000000,0x680); +reg_write( DDR_REG_BASE +0x52b01*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52b02*4+0x02000000,0xa96); +reg_write( DDR_REG_BASE +0x52b03*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52b04*4+0x02000000,0x42c1); +reg_write( DDR_REG_BASE +0x52b05*4+0x02000000,0xc209); +reg_write( DDR_REG_BASE +0x52b06*4+0x02000000,0x7944); +reg_write( DDR_REG_BASE +0x52b07*4+0x02000000,0xc208); +reg_write( DDR_REG_BASE +0x52b08*4+0x02000000,0x7844); +reg_write( DDR_REG_BASE +0x52b09*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52b0a*4+0x02000000,0x807e); +reg_write( DDR_REG_BASE +0x52b0b*4+0x02000000,0xf42f); +reg_write( DDR_REG_BASE +0x52b0c*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x52b0d*4+0x02000000,0x60c8); +reg_write( DDR_REG_BASE +0x52b0e*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52b0f*4+0x02000000,0x2342); +reg_write( DDR_REG_BASE +0x52b10*4+0x02000000,0x3180); +reg_write( DDR_REG_BASE +0x52b11*4+0x02000000,0x83b); +reg_write( DDR_REG_BASE +0x52b12*4+0x02000000,0xf5); +reg_write( DDR_REG_BASE +0x52b13*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52b14*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52b15*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x52b16*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52b17*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52b18*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x52b19*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52b1a*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52b1b*4+0x02000000,0x836); +reg_write( DDR_REG_BASE +0x52b1c*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52b1d*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x52b1e*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52b1f*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52b20*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x52b21*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52b22*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52b23*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x52b24*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52b25*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52b26*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52b27*4+0x02000000,0x81e); +reg_write( DDR_REG_BASE +0x52b28*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52b29*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x52b2a*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52b2b*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52b2c*4+0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x52b2d*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52b2e*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52b2f*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52b30*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52b31*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52b32*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x52b33*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52b34*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52b35*4+0x02000000,0xdb18); +reg_write( DDR_REG_BASE +0x52b36*4+0x02000000,0xffe); +reg_write( DDR_REG_BASE +0x52b37*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52b38*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x52b39*4+0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x52b3a*4+0x02000000,0xb87); +reg_write( DDR_REG_BASE +0x52b3b*4+0x02000000,0xb274); +reg_write( DDR_REG_BASE +0x52b3c*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52b3d*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52b3e*4+0x02000000,0xe80e); +reg_write( DDR_REG_BASE +0x52b3f*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52b40*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52b41*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x52b42*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52b43*4+0x02000000,0xd856); +reg_write( DDR_REG_BASE +0x52b44*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52b45*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52b46*4+0x02000000,0xdb18); +reg_write( DDR_REG_BASE +0x52b47*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x52b48*4+0x02000000,0xe5a); +reg_write( DDR_REG_BASE +0x52b49*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52b4a*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x52b4b*4+0x02000000,0x3281); +reg_write( DDR_REG_BASE +0x52b4c*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52b4d*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52b4e*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52b4f*4+0x02000000,0xdb41); +reg_write( DDR_REG_BASE +0x52b50*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x52b51*4+0x02000000,0x3401); +reg_write( DDR_REG_BASE +0x52b52*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52b53*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x52b54*4+0x02000000,0xe42); +reg_write( DDR_REG_BASE +0x52b55*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52b56*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x52b57*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52b58*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x52b59*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52b5a*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52b5b*4+0x02000000,0xc743); +reg_write( DDR_REG_BASE +0x52b5c*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52b5d*4+0x02000000,0xc741); +reg_write( DDR_REG_BASE +0x52b5e*4+0x02000000,0xe2e); +reg_write( DDR_REG_BASE +0x52b5f*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52b60*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x52b61*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52b62*4+0x02000000,0xde6); +reg_write( DDR_REG_BASE +0x52b63*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52b64*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52b65*4+0x02000000,0xc0aa); +reg_write( DDR_REG_BASE +0x52b66*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52b67*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52b68*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52b69*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52b6a*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52b6b*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52b6c*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52b6d*4+0x02000000,0xc1a5); +reg_write( DDR_REG_BASE +0x52b6e*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x52b6f*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52b70*4+0x02000000,0xd32); +reg_write( DDR_REG_BASE +0x52b71*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52b72*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x52b73*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x52b74*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52b75*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x52b76*4+0x02000000,0x9700); +reg_write( DDR_REG_BASE +0x52b77*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52b78*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52b79*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52b7a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52b7b*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52b7c*4+0x02000000,0xb886); +reg_write( DDR_REG_BASE +0x52b7d*4+0x02000000,0xb700); +reg_write( DDR_REG_BASE +0x52b7e*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52b7f*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52b80*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x52b81*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52b82*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x52b83*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52b84*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52b85*4+0x02000000,0xde2); +reg_write( DDR_REG_BASE +0x52b86*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52b87*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x52b88*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52b89*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52b8a*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52b8b*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x52b8c*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52b8d*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x52b8e*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52b8f*4+0x02000000,0xdce); +reg_write( DDR_REG_BASE +0x52b90*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52b91*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52b92*4+0x02000000,0x2355); +reg_write( DDR_REG_BASE +0x52b93*4+0x02000000,0x3801); +reg_write( DDR_REG_BASE +0x52b94*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52b95*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52b96*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x52b97*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52b98*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x52b99*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52b9a*4+0x02000000,0xdb6); +reg_write( DDR_REG_BASE +0x52b9b*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52b9c*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52b9d*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52b9e*4+0x02000000,0xd6e); +reg_write( DDR_REG_BASE +0x52b9f*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52ba0*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52ba1*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52ba2*4+0x02000000,0xb700); +reg_write( DDR_REG_BASE +0x52ba3*4+0x02000000,0xc0a5); +reg_write( DDR_REG_BASE +0x52ba4*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52ba5*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52ba6*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52ba7*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52ba8*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52ba9*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52baa*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52bab*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x52bac*4+0x02000000,0x4608); +reg_write( DDR_REG_BASE +0x52bad*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52bae*4+0x02000000,0xcb6); +reg_write( DDR_REG_BASE +0x52baf*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52bb0*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x52bb1*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x52bb2*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52bb3*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x52bb4*4+0x02000000,0x1700); +reg_write( DDR_REG_BASE +0x52bb5*4+0x02000000,0x111b); +reg_write( DDR_REG_BASE +0x52bb6*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52bb7*4+0x02000000,0xda0c); +reg_write( DDR_REG_BASE +0x52bb8*4+0x02000000,0x234f); +reg_write( DDR_REG_BASE +0x52bb9*4+0x02000000,0x3180); +reg_write( DDR_REG_BASE +0x52bba*4+0x02000000,0xb700); +reg_write( DDR_REG_BASE +0x52bbb*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x52bbc*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x52bbd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52bbe*4+0x02000000,0x3ffc); +reg_write( DDR_REG_BASE +0x52bbf*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52bc0*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x52bc1*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x52bc2*4+0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x52bc3*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x52bc4*4+0x02000000,0xd62); +reg_write( DDR_REG_BASE +0x52bc5*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52bc6*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x52bc7*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52bc8*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x52bc9*4+0x02000000,0xda0c); +reg_write( DDR_REG_BASE +0x52bca*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x52bcb*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52bcc*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52bcd*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52bce*4+0x02000000,0xd4e); +reg_write( DDR_REG_BASE +0x52bcf*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52bd0*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x52bd1*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52bd2*4+0x02000000,0xd06); +reg_write( DDR_REG_BASE +0x52bd3*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52bd4*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52bd5*4+0x02000000,0x1f00); +reg_write( DDR_REG_BASE +0x52bd6*4+0x02000000,0x16c4); +reg_write( DDR_REG_BASE +0x52bd7*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x52bd8*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52bd9*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52bda*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52bdb*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52bdc*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x52bdd*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x52bde*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x52bdf*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52be0*4+0x02000000,0xc52); +reg_write( DDR_REG_BASE +0x52be1*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52be2*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x52be3*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52be4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52be5*4+0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x52be6*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52be7*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52be8*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x52be9*4+0x02000000,0xda0c); +reg_write( DDR_REG_BASE +0x52bea*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52beb*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x52bec*4+0x02000000,0x3001); +reg_write( DDR_REG_BASE +0x52bed*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52bee*4+0x02000000,0xd0e); +reg_write( DDR_REG_BASE +0x52bef*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52bf0*4+0x02000000,0x1c04); +reg_write( DDR_REG_BASE +0x52bf1*4+0x02000000,0x3001); +reg_write( DDR_REG_BASE +0x52bf2*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52bf3*4+0x02000000,0xcc6); +reg_write( DDR_REG_BASE +0x52bf4*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52bf5*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52bf6*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x52bf7*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x52bf8*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52bf9*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52bfa*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52bfb*4+0x02000000,0xc1a8); +reg_write( DDR_REG_BASE +0x52bfc*4+0x02000000,0xc144); +reg_write( DDR_REG_BASE +0x52bfd*4+0x02000000,0xd949); +reg_write( DDR_REG_BASE +0x52bfe*4+0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x52bff*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52c00*4+0x02000000,0x8900); +reg_write( DDR_REG_BASE +0x52c01*4+0x02000000,0x11da); +reg_write( DDR_REG_BASE +0x52c02*4+0x02000000,0x808f); +reg_write( DDR_REG_BASE +0x52c03*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52c04*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x52c05*4+0x02000000,0xc00d); +reg_write( DDR_REG_BASE +0x52c06*4+0x02000000,0x71cd); +reg_write( DDR_REG_BASE +0x52c07*4+0x02000000,0xc342); +reg_write( DDR_REG_BASE +0x52c08*4+0x02000000,0xc243); +reg_write( DDR_REG_BASE +0x52c09*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x52c0a*4+0x02000000,0xf033); +reg_write( DDR_REG_BASE +0x52c0b*4+0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x52c0c*4+0x02000000,0x17c1); +reg_write( DDR_REG_BASE +0x52c0d*4+0x02000000,0x706f); +reg_write( DDR_REG_BASE +0x52c0e*4+0x02000000,0xe905); +reg_write( DDR_REG_BASE +0x52c0f*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x52c10*4+0x02000000,0x9ff); +reg_write( DDR_REG_BASE +0x52c11*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x52c12*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52c13*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52c14*4+0x02000000,0xf026); +reg_write( DDR_REG_BASE +0x52c15*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52c16*4+0x02000000,0xc201); +reg_write( DDR_REG_BASE +0x52c17*4+0x02000000,0xc107); +reg_write( DDR_REG_BASE +0x52c18*4+0x02000000,0x7077); +reg_write( DDR_REG_BASE +0x52c19*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x52c1a*4+0x02000000,0x3c1); +reg_write( DDR_REG_BASE +0x52c1b*4+0x02000000,0x7944); +reg_write( DDR_REG_BASE +0x52c1c*4+0x02000000,0x790b); +reg_write( DDR_REG_BASE +0x52c1d*4+0x02000000,0xf21d); +reg_write( DDR_REG_BASE +0x52c1e*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52c1f*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x52c20*4+0x02000000,0x37c1); +reg_write( DDR_REG_BASE +0x52c21*4+0x02000000,0xe906); +reg_write( DDR_REG_BASE +0x52c22*4+0x02000000,0xb961); +reg_write( DDR_REG_BASE +0x52c23*4+0x02000000,0x901); +reg_write( DDR_REG_BASE +0x52c24*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x52c25*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52c26*4+0x02000000,0xbce); +reg_write( DDR_REG_BASE +0x52c27*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52c28*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52c29*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52c2a*4+0x02000000,0xc105); +reg_write( DDR_REG_BASE +0x52c2b*4+0x02000000,0xc204); +reg_write( DDR_REG_BASE +0x52c2c*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52c2d*4+0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x52c2e*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52c2f*4+0x02000000,0x901); +reg_write( DDR_REG_BASE +0x52c30*4+0x02000000,0xc303); +reg_write( DDR_REG_BASE +0x52c31*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x52c32*4+0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x52c33*4+0x02000000,0x1c80); +reg_write( DDR_REG_BASE +0x52c34*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x52c35*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x52c36*4+0x02000000,0xd5e); +reg_write( DDR_REG_BASE +0x52c37*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x52c38*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52c39*4+0x02000000,0x7167); +reg_write( DDR_REG_BASE +0x52c3a*4+0x02000000,0xbb7); +reg_write( DDR_REG_BASE +0x52c3b*4+0x02000000,0xb094); +reg_write( DDR_REG_BASE +0x52c3c*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x52c3d*4+0x02000000,0xd9f); +reg_write( DDR_REG_BASE +0x52c3e*4+0x02000000,0x90b4); +reg_write( DDR_REG_BASE +0x52c3f*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52c40*4+0x02000000,0xb9a); +reg_write( DDR_REG_BASE +0x52c41*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52c42*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x52c43*4+0x02000000,0xc0a8); +reg_write( DDR_REG_BASE +0x52c44*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52c45*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52c46*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52c47*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52c48*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52c49*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52c4a*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52c4b*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x52c4c*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52c4d*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52c4e*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52c4f*4+0x02000000,0x7b0); +reg_write( DDR_REG_BASE +0x52c50*4+0x02000000,0x8800); +reg_write( DDR_REG_BASE +0x52c51*4+0x02000000,0x4378); +reg_write( DDR_REG_BASE +0x52c52*4+0x02000000,0x4748); +reg_write( DDR_REG_BASE +0x52c53*4+0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x52c54*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x52c55*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52c56*4+0x02000000,0x708e); +reg_write( DDR_REG_BASE +0x52c57*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52c58*4+0x02000000,0x49); +reg_write( DDR_REG_BASE +0x52c59*4+0x02000000,0xf006); +reg_write( DDR_REG_BASE +0x52c5a*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52c5b*4+0x02000000,0x708e); +reg_write( DDR_REG_BASE +0x52c5c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52c5d*4+0x02000000,0x23); +reg_write( DDR_REG_BASE +0x52c5e*4+0x02000000,0xc009); +reg_write( DDR_REG_BASE +0x52c5f*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52c60*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52c61*4+0x02000000,0xf01d); +reg_write( DDR_REG_BASE +0x52c62*4+0x02000000,0xe35); +reg_write( DDR_REG_BASE +0x52c63*4+0x02000000,0x136e); +reg_write( DDR_REG_BASE +0x52c64*4+0x02000000,0x710c); +reg_write( DDR_REG_BASE +0x52c65*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x52c66*4+0x02000000,0x2544); +reg_write( DDR_REG_BASE +0x52c67*4+0x02000000,0x17c0); +reg_write( DDR_REG_BASE +0x52c68*4+0x02000000,0xe805); +reg_write( DDR_REG_BASE +0x52c69*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x52c6a*4+0x02000000,0x8ff); +reg_write( DDR_REG_BASE +0x52c6b*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x52c6c*4+0x02000000,0x7a5b); +reg_write( DDR_REG_BASE +0x52c6d*4+0x02000000,0xc103); +reg_write( DDR_REG_BASE +0x52c6e*4+0x02000000,0xc001); +reg_write( DDR_REG_BASE +0x52c6f*4+0x02000000,0x4363); +reg_write( DDR_REG_BASE +0x52c70*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52c71*4+0x02000000,0xc002); +reg_write( DDR_REG_BASE +0x52c72*4+0x02000000,0x209f); +reg_write( DDR_REG_BASE +0x52c73*4+0x02000000,0x901); +reg_write( DDR_REG_BASE +0x52c74*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x52c75*4+0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x52c76*4+0x02000000,0x1c80); +reg_write( DDR_REG_BASE +0x52c77*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x52c78*4+0x02000000,0x784f); +reg_write( DDR_REG_BASE +0x52c79*4+0x02000000,0xcda); +reg_write( DDR_REG_BASE +0x52c7a*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x52c7b*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x52c7c*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x52c7d*4+0x02000000,0xdcd); +reg_write( DDR_REG_BASE +0x52c7e*4+0x02000000,0x9094); +reg_write( DDR_REG_BASE +0x52c7f*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x52c80*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52c81*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52c82*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52c83*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52c84*4+0x02000000,0xc2e4); +reg_write( DDR_REG_BASE +0x52c85*4+0x02000000,0xc1a4); +reg_write( DDR_REG_BASE +0x52c86*4+0x02000000,0x4508); +reg_write( DDR_REG_BASE +0x52c87*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52c88*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x52c89*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52c8a*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52c8b*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x52c8c*4+0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x52c8d*4+0x02000000,0x20); +reg_write( DDR_REG_BASE +0x52c8e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52c8f*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52c90*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52c91*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x52c92*4+0x02000000,0x2305); +reg_write( DDR_REG_BASE +0x52c93*4+0x02000000,0xc); +reg_write( DDR_REG_BASE +0x52c94*4+0x02000000,0x7204); +reg_write( DDR_REG_BASE +0x52c95*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x52c96*4+0x02000000,0xb420); +reg_write( DDR_REG_BASE +0x52c97*4+0x02000000,0xb040); +reg_write( DDR_REG_BASE +0x52c98*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52c99*4+0x02000000,0xae2); +reg_write( DDR_REG_BASE +0x52c9a*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52c9b*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52c9c*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52c9d*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52c9e*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52c9f*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x52ca0*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x52ca1*4+0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x52ca2*4+0x02000000,0x4628); +reg_write( DDR_REG_BASE +0x52ca3*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x52ca4*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x52ca5*4+0x02000000,0xba2); +reg_write( DDR_REG_BASE +0x52ca6*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52ca7*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x52ca8*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52ca9*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52caa*4+0x02000000,0xb98d); +reg_write( DDR_REG_BASE +0x52cab*4+0x02000000,0x734c); +reg_write( DDR_REG_BASE +0x52cac*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52cad*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x52cae*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52caf*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x52cb0*4+0x02000000,0xb8a); +reg_write( DDR_REG_BASE +0x52cb1*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52cb2*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x52cb3*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52cb4*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x52cb5*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52cb6*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x52cb7*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x52cb8*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x52cb9*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x52cba*4+0x02000000,0xb76); +reg_write( DDR_REG_BASE +0x52cbb*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52cbc*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x52cbd*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52cbe*4+0x02000000,0xb2e); +reg_write( DDR_REG_BASE +0x52cbf*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52cc0*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52cc1*4+0x02000000,0xc0a4); +reg_write( DDR_REG_BASE +0x52cc2*4+0x02000000,0xc6c4); +reg_write( DDR_REG_BASE +0x52cc3*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52cc4*4+0x02000000,0xc2e2); +reg_write( DDR_REG_BASE +0x52cc5*4+0x02000000,0x260a); +reg_write( DDR_REG_BASE +0x52cc6*4+0x02000000,0x3040); +reg_write( DDR_REG_BASE +0x52cc7*4+0x02000000,0x4308); +reg_write( DDR_REG_BASE +0x52cc8*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52cc9*4+0x02000000,0xf024); +reg_write( DDR_REG_BASE +0x52cca*4+0x02000000,0x255a); +reg_write( DDR_REG_BASE +0x52ccb*4+0x02000000,0x1182); +reg_write( DDR_REG_BASE +0x52ccc*4+0x02000000,0x7261); +reg_write( DDR_REG_BASE +0x52ccd*4+0x02000000,0x8a01); +reg_write( DDR_REG_BASE +0x52cce*4+0x02000000,0x8a60); +reg_write( DDR_REG_BASE +0x52ccf*4+0x02000000,0x8a22); +reg_write( DDR_REG_BASE +0x52cd0*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52cd1*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52cd2*4+0x02000000,0x7b05); +reg_write( DDR_REG_BASE +0x52cd3*4+0x02000000,0x8a03); +reg_write( DDR_REG_BASE +0x52cd4*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52cd5*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52cd6*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52cd7*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x52cd8*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52cd9*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52cda*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52cdb*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52cdc*4+0x02000000,0xc1); +reg_write( DDR_REG_BASE +0x52cdd*4+0x02000000,0x8a05); +reg_write( DDR_REG_BASE +0x52cde*4+0x02000000,0x8a64); +reg_write( DDR_REG_BASE +0x52cdf*4+0x02000000,0x7734); +reg_write( DDR_REG_BASE +0x52ce0*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52ce1*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52ce2*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x52ce3*4+0x02000000,0xf207); +reg_write( DDR_REG_BASE +0x52ce4*4+0x02000000,0x793b); +reg_write( DDR_REG_BASE +0x52ce5*4+0x02000000,0xb99c); +reg_write( DDR_REG_BASE +0x52ce6*4+0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x52ce7*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x52ce8*4+0x02000000,0xf003); +reg_write( DDR_REG_BASE +0x52ce9*4+0x02000000,0xc92); +reg_write( DDR_REG_BASE +0x52cea*4+0x02000000,0xfe4f); +reg_write( DDR_REG_BASE +0x52ceb*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x52cec*4+0x02000000,0x2e45); +reg_write( DDR_REG_BASE +0x52ced*4+0x02000000,0x3180); +reg_write( DDR_REG_BASE +0x52cee*4+0x02000000,0xdb9); +reg_write( DDR_REG_BASE +0x52cef*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52cf0*4+0x02000000,0xc6c2); +reg_write( DDR_REG_BASE +0x52cf1*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x52cf2*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52cf3*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52cf4*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52cf5*4+0x02000000,0xc1a1); +reg_write( DDR_REG_BASE +0x52cf6*4+0x02000000,0x4718); +reg_write( DDR_REG_BASE +0x52cf7*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52cf8*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52cf9*4+0x02000000,0x7b4); +reg_write( DDR_REG_BASE +0x52cfa*4+0x02000000,0x88c0); +reg_write( DDR_REG_BASE +0x52cfb*4+0x02000000,0x4338); +reg_write( DDR_REG_BASE +0x52cfc*4+0x02000000,0xc340); +reg_write( DDR_REG_BASE +0x52cfd*4+0x02000000,0xea04); +reg_write( DDR_REG_BASE +0x52cfe*4+0x02000000,0x79db); +reg_write( DDR_REG_BASE +0x52cff*4+0x02000000,0xf004); +reg_write( DDR_REG_BASE +0x52d00*4+0x02000000,0x265f); +reg_write( DDR_REG_BASE +0x52d01*4+0x02000000,0x1241); +reg_write( DDR_REG_BASE +0x52d02*4+0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x52d03*4+0x02000000,0x9e); +reg_write( DDR_REG_BASE +0x52d04*4+0x02000000,0x7054); +reg_write( DDR_REG_BASE +0x52d05*4+0x02000000,0xdd08); +reg_write( DDR_REG_BASE +0x52d06*4+0x02000000,0x25ca); +reg_write( DDR_REG_BASE +0x52d07*4+0x02000000,0x1062); +reg_write( DDR_REG_BASE +0x52d08*4+0x02000000,0xf039); +reg_write( DDR_REG_BASE +0x52d09*4+0x02000000,0x40e1); +reg_write( DDR_REG_BASE +0x52d0a*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52d0b*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52d0c*4+0x02000000,0xc300); +reg_write( DDR_REG_BASE +0x52d0d*4+0x02000000,0x23f5); +reg_write( DDR_REG_BASE +0x52d0e*4+0x02000000,0x3042); +reg_write( DDR_REG_BASE +0x52d0f*4+0x02000000,0xeb13); +reg_write( DDR_REG_BASE +0x52d10*4+0x02000000,0x7c5c); +reg_write( DDR_REG_BASE +0x52d11*4+0x02000000,0x7c9c); +reg_write( DDR_REG_BASE +0x52d12*4+0x02000000,0x7c9c); +reg_write( DDR_REG_BASE +0x52d13*4+0x02000000,0x7c9c); +reg_write( DDR_REG_BASE +0x52d14*4+0x02000000,0x224a); +reg_write( DDR_REG_BASE +0x52d15*4+0x02000000,0x16c0); +reg_write( DDR_REG_BASE +0x52d16*4+0x02000000,0x2a44); +reg_write( DDR_REG_BASE +0x52d17*4+0x02000000,0x803); +reg_write( DDR_REG_BASE +0x52d18*4+0x02000000,0x2242); +reg_write( DDR_REG_BASE +0x52d19*4+0x02000000,0x104a); +reg_write( DDR_REG_BASE +0x52d1a*4+0x02000000,0xafd); +reg_write( DDR_REG_BASE +0x52d1b*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x52d1c*4+0x02000000,0x7c9d); +reg_write( DDR_REG_BASE +0x52d1d*4+0x02000000,0x629a); +reg_write( DDR_REG_BASE +0x52d1e*4+0x02000000,0xbac4); +reg_write( DDR_REG_BASE +0x52d1f*4+0x02000000,0x4a94); +reg_write( DDR_REG_BASE +0x52d20*4+0x02000000,0xf00d); +reg_write( DDR_REG_BASE +0x52d21*4+0x02000000,0x248a); +reg_write( DDR_REG_BASE +0x52d22*4+0x02000000,0x1fcf); +reg_write( DDR_REG_BASE +0x52d23*4+0x02000000,0x7c44); +reg_write( DDR_REG_BASE +0x52d24*4+0x02000000,0x2204); +reg_write( DDR_REG_BASE +0x52d25*4+0x02000000,0xf83); +reg_write( DDR_REG_BASE +0x52d26*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52d27*4+0x02000000,0xfc00); +reg_write( DDR_REG_BASE +0x52d28*4+0x02000000,0xda0a); +reg_write( DDR_REG_BASE +0x52d29*4+0x02000000,0xba61); +reg_write( DDR_REG_BASE +0x52d2a*4+0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x52d2b*4+0x02000000,0x8031); +reg_write( DDR_REG_BASE +0x52d2c*4+0x02000000,0x7b7d); +reg_write( DDR_REG_BASE +0x52d2d*4+0x02000000,0x261a); +reg_write( DDR_REG_BASE +0x52d2e*4+0x02000000,0x1f82); +reg_write( DDR_REG_BASE +0x52d2f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52d30*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52d31*4+0x02000000,0x239a); +reg_write( DDR_REG_BASE +0x52d32*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x52d33*4+0x02000000,0x71e5); +reg_write( DDR_REG_BASE +0x52d34*4+0x02000000,0x7124); +reg_write( DDR_REG_BASE +0x52d35*4+0x02000000,0x2205); +reg_write( DDR_REG_BASE +0x52d36*4+0x02000000,0x7c2); +reg_write( DDR_REG_BASE +0x52d37*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x52d38*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52d39*4+0x02000000,0xb891); +reg_write( DDR_REG_BASE +0x52d3a*4+0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x52d3b*4+0x02000000,0x7b85); +reg_write( DDR_REG_BASE +0x52d3c*4+0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x52d3d*4+0x02000000,0xb060); +reg_write( DDR_REG_BASE +0x52d3e*4+0x02000000,0xd97); +reg_write( DDR_REG_BASE +0x52d3f*4+0x02000000,0x93c5); +reg_write( DDR_REG_BASE +0x52d40*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x52d41*4+0x02000000,0xefd); +reg_write( DDR_REG_BASE +0x52d42*4+0x02000000,0xb3a5); +reg_write( DDR_REG_BASE +0x52d43*4+0x02000000,0x70ed); +reg_write( DDR_REG_BASE +0x52d44*4+0x02000000,0x7487); +reg_write( DDR_REG_BASE +0x52d45*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52d46*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52d47*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52d48*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52d49*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52d4a*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52d4b*4+0x02000000,0xc1a9); +reg_write( DDR_REG_BASE +0x52d4c*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52d4d*4+0x02000000,0xd72); +reg_write( DDR_REG_BASE +0x52d4e*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52d4f*4+0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x52d50*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52d51*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52d52*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52d53*4+0x02000000,0x7b2); +reg_write( DDR_REG_BASE +0x52d54*4+0x02000000,0x1003); +reg_write( DDR_REG_BASE +0x52d55*4+0x02000000,0x8b); +reg_write( DDR_REG_BASE +0x52d56*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52d57*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52d58*4+0x02000000,0x7b2); +reg_write( DDR_REG_BASE +0x52d59*4+0x02000000,0x88c2); +reg_write( DDR_REG_BASE +0x52d5a*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52d5b*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x52d5c*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52d5d*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52d5e*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x52d5f*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52d60*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52d61*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52d62*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x52d63*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52d64*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52d65*4+0x02000000,0xf039); +reg_write( DDR_REG_BASE +0x52d66*4+0x02000000,0x708d); +reg_write( DDR_REG_BASE +0x52d67*4+0x02000000,0xf034); +reg_write( DDR_REG_BASE +0x52d68*4+0x02000000,0x271a); +reg_write( DDR_REG_BASE +0x52d69*4+0x02000000,0x1f8d); +reg_write( DDR_REG_BASE +0x52d6a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52d6b*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52d6c*4+0x02000000,0x224f); +reg_write( DDR_REG_BASE +0x52d6d*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x52d6e*4+0x02000000,0x780f); +reg_write( DDR_REG_BASE +0x52d6f*4+0x02000000,0x82d); +reg_write( DDR_REG_BASE +0x52d70*4+0x02000000,0x111); +reg_write( DDR_REG_BASE +0x52d71*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52d72*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x52d73*4+0x02000000,0xd01); +reg_write( DDR_REG_BASE +0x52d74*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52d75*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52d76*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52d77*4+0x02000000,0x341); +reg_write( DDR_REG_BASE +0x52d78*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x52d79*4+0x02000000,0x203c); +reg_write( DDR_REG_BASE +0x52d7a*4+0x02000000,0x80); +reg_write( DDR_REG_BASE +0x52d7b*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52d7c*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52d7d*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52d7e*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52d7f*4+0x02000000,0xb891); +reg_write( DDR_REG_BASE +0x52d80*4+0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x52d81*4+0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x52d82*4+0x02000000,0x9080); +reg_write( DDR_REG_BASE +0x52d83*4+0x02000000,0xbcc4); +reg_write( DDR_REG_BASE +0x52d84*4+0x02000000,0x4c38); +reg_write( DDR_REG_BASE +0x52d85*4+0x02000000,0x791b); +reg_write( DDR_REG_BASE +0x52d86*4+0x02000000,0x216c); +reg_write( DDR_REG_BASE +0x52d87*4+0x02000000,0x143); +reg_write( DDR_REG_BASE +0x52d88*4+0x02000000,0xb8c4); +reg_write( DDR_REG_BASE +0x52d89*4+0x02000000,0x7b05); +reg_write( DDR_REG_BASE +0x52d8a*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52d8b*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x52d8c*4+0x02000000,0xc01); +reg_write( DDR_REG_BASE +0x52d8d*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52d8e*4+0x02000000,0x7905); +reg_write( DDR_REG_BASE +0x52d8f*4+0x02000000,0x6a01); +reg_write( DDR_REG_BASE +0x52d90*4+0x02000000,0x229a); +reg_write( DDR_REG_BASE +0x52d91*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52d92*4+0x02000000,0x7a25); +reg_write( DDR_REG_BASE +0x52d93*4+0x02000000,0x7d45); +reg_write( DDR_REG_BASE +0x52d94*4+0x02000000,0x79bb); +reg_write( DDR_REG_BASE +0x52d95*4+0x02000000,0xb991); +reg_write( DDR_REG_BASE +0x52d96*4+0x02000000,0xb99c); +reg_write( DDR_REG_BASE +0x52d97*4+0x02000000,0xb99f); +reg_write( DDR_REG_BASE +0x52d98*4+0x02000000,0xb160); +reg_write( DDR_REG_BASE +0x52d99*4+0x02000000,0x4200); +reg_write( DDR_REG_BASE +0x52d9a*4+0x02000000,0xa9d); +reg_write( DDR_REG_BASE +0x52d9b*4+0x02000000,0x8254); +reg_write( DDR_REG_BASE +0x52d9c*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x52d9d*4+0x02000000,0x7fcf); +reg_write( DDR_REG_BASE +0x52d9e*4+0x02000000,0xb91); +reg_write( DDR_REG_BASE +0x52d9f*4+0x02000000,0x93e5); +reg_write( DDR_REG_BASE +0x52da0*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52da1*4+0x02000000,0xa92); +reg_write( DDR_REG_BASE +0x52da2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52da3*4+0x02000000,0xf36); +reg_write( DDR_REG_BASE +0x52da4*4+0x02000000,0xfd8f); +reg_write( DDR_REG_BASE +0x52da5*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52da6*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52da7*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x52da8*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52da9*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x52daa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52dab*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x52dac*4+0x02000000,0x71cd); +reg_write( DDR_REG_BASE +0x52dad*4+0x02000000,0xb100); +reg_write( DDR_REG_BASE +0x52dae*4+0x02000000,0xb1f0); +reg_write( DDR_REG_BASE +0x52daf*4+0x02000000,0xb1d6); +reg_write( DDR_REG_BASE +0x52db0*4+0x02000000,0xb1cf); +reg_write( DDR_REG_BASE +0x52db1*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52db2*4+0x02000000,0x710d); +reg_write( DDR_REG_BASE +0x52db3*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52db4*4+0x02000000,0x4a); +reg_write( DDR_REG_BASE +0x52db5*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52db6*4+0x02000000,0x41e1); +reg_write( DDR_REG_BASE +0x52db7*4+0x02000000,0x42e1); +reg_write( DDR_REG_BASE +0x52db8*4+0x02000000,0x43e1); +reg_write( DDR_REG_BASE +0x52db9*4+0x02000000,0xfd2); +reg_write( DDR_REG_BASE +0x52dba*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52dbb*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x52dbc*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52dbd*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x52dbe*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x52dbf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52dc0*4+0x02000000,0xf000); +reg_write( DDR_REG_BASE +0x52dc1*4+0x02000000,0x43e1); +reg_write( DDR_REG_BASE +0x52dc2*4+0x02000000,0xfbe); +reg_write( DDR_REG_BASE +0x52dc3*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52dc4*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x52dc5*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52dc6*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x52dc7*4+0x02000000,0x37ca); +reg_write( DDR_REG_BASE +0x52dc8*4+0x02000000,0x43d9); +reg_write( DDR_REG_BASE +0x52dc9*4+0x02000000,0xa13); +reg_write( DDR_REG_BASE +0x52dca*4+0x02000000,0x1010); +reg_write( DDR_REG_BASE +0x52dcb*4+0x02000000,0x2242); +reg_write( DDR_REG_BASE +0x52dcc*4+0x02000000,0x104a); +reg_write( DDR_REG_BASE +0x52dcd*4+0x02000000,0xaff); +reg_write( DDR_REG_BASE +0x52dce*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x52dcf*4+0x02000000,0x232f); +reg_write( DDR_REG_BASE +0x52dd0*4+0x02000000,0x36c0); +reg_write( DDR_REG_BASE +0x52dd1*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x52dd2*4+0x02000000,0x7ca); +reg_write( DDR_REG_BASE +0x52dd3*4+0x02000000,0x40c1); +reg_write( DDR_REG_BASE +0x52dd4*4+0x02000000,0xa0f); +reg_write( DDR_REG_BASE +0x52dd5*4+0x02000000,0x1010); +reg_write( DDR_REG_BASE +0x52dd6*4+0x02000000,0x2242); +reg_write( DDR_REG_BASE +0x52dd7*4+0x02000000,0x104a); +reg_write( DDR_REG_BASE +0x52dd8*4+0x02000000,0xafd); +reg_write( DDR_REG_BASE +0x52dd9*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x52dda*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52ddb*4+0x02000000,0x2004); +reg_write( DDR_REG_BASE +0x52ddc*4+0x02000000,0x8340); +reg_write( DDR_REG_BASE +0x52ddd*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x52dde*4+0x02000000,0xf20a); +reg_write( DDR_REG_BASE +0x52ddf*4+0x02000000,0x740c); +reg_write( DDR_REG_BASE +0x52de0*4+0x02000000,0xd9ff); +reg_write( DDR_REG_BASE +0x52de1*4+0x02000000,0x42c3); +reg_write( DDR_REG_BASE +0x52de2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52de3*4+0x02000000,0xf000); +reg_write( DDR_REG_BASE +0x52de4*4+0x02000000,0x43e1); +reg_write( DDR_REG_BASE +0x52de5*4+0x02000000,0xf7a); +reg_write( DDR_REG_BASE +0x52de6*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52de7*4+0x02000000,0xc740); +reg_write( DDR_REG_BASE +0x52de8*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52de9*4+0x02000000,0xbee); +reg_write( DDR_REG_BASE +0x52dea*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52deb*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52dec*4+0x02000000,0xea2); +reg_write( DDR_REG_BASE +0x52ded*4+0x02000000,0xfdcf); +reg_write( DDR_REG_BASE +0x52dee*4+0x02000000,0xc047); +reg_write( DDR_REG_BASE +0x52def*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52df0*4+0x02000000,0x832); +reg_write( DDR_REG_BASE +0x52df1*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52df2*4+0x02000000,0xd91f); +reg_write( DDR_REG_BASE +0x52df3*4+0x02000000,0xca00); +reg_write( DDR_REG_BASE +0x52df4*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52df5*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52df6*4+0x02000000,0x7604); +reg_write( DDR_REG_BASE +0x52df7*4+0x02000000,0xbd8e); +reg_write( DDR_REG_BASE +0x52df8*4+0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x52df9*4+0x02000000,0x272f); +reg_write( DDR_REG_BASE +0x52dfa*4+0x02000000,0x16c7); +reg_write( DDR_REG_BASE +0x52dfb*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x52dfc*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x52dfd*4+0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x52dfe*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52dff*4+0x02000000,0x41a1); +reg_write( DDR_REG_BASE +0x52e00*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52e01*4+0x02000000,0x8ea); +reg_write( DDR_REG_BASE +0x52e02*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52e03*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52e04*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52e05*4+0x02000000,0xc041); +reg_write( DDR_REG_BASE +0x52e06*4+0x02000000,0xc040); +reg_write( DDR_REG_BASE +0x52e07*4+0x02000000,0x254f); +reg_write( DDR_REG_BASE +0x52e08*4+0x02000000,0x1281); +reg_write( DDR_REG_BASE +0x52e09*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52e0a*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x52e0b*4+0x02000000,0xdb7c); +reg_write( DDR_REG_BASE +0x52e0c*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x52e0d*4+0x02000000,0x8d2); +reg_write( DDR_REG_BASE +0x52e0e*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52e0f*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52e10*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52e11*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x52e12*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52e13*4+0x02000000,0x4400); +reg_write( DDR_REG_BASE +0x52e14*4+0x02000000,0xf031); +reg_write( DDR_REG_BASE +0x52e15*4+0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x52e16*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x52e17*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52e18*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x52e19*4+0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x52e1a*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52e1b*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52e1c*4+0x02000000,0x8b2); +reg_write( DDR_REG_BASE +0x52e1d*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52e1e*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x52e1f*4+0x02000000,0x3201); +reg_write( DDR_REG_BASE +0x52e20*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52e21*4+0x02000000,0x41c1); +reg_write( DDR_REG_BASE +0x52e22*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x52e23*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52e24*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52e25*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52e26*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52e27*4+0x02000000,0x89e); +reg_write( DDR_REG_BASE +0x52e28*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52e29*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52e2a*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52e2b*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52e2c*4+0x02000000,0xb990); +reg_write( DDR_REG_BASE +0x52e2d*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x52e2e*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52e2f*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x52e30*4+0x02000000,0x3081); +reg_write( DDR_REG_BASE +0x52e31*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52e32*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52e33*4+0x02000000,0x886); +reg_write( DDR_REG_BASE +0x52e34*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52e35*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52e36*4+0x02000000,0x942); +reg_write( DDR_REG_BASE +0x52e37*4+0x02000000,0xfdcf); +reg_write( DDR_REG_BASE +0x52e38*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52e39*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52e3a*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52e3b*4+0x02000000,0xdb10); +reg_write( DDR_REG_BASE +0x52e3c*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52e3d*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52e3e*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52e3f*4+0x02000000,0x86e); +reg_write( DDR_REG_BASE +0x52e40*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52e41*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52e42*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52e43*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52e44*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52e45*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52e46*4+0x02000000,0x89f); +reg_write( DDR_REG_BASE +0x52e47*4+0x02000000,0x80b4); +reg_write( DDR_REG_BASE +0x52e48*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52e49*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x52e4a*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52e4b*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52e4c*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x52e4d*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x52e4e*4+0x02000000,0x6119); +reg_write( DDR_REG_BASE +0x52e4f*4+0x02000000,0x496e); +reg_write( DDR_REG_BASE +0x52e50*4+0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x52e51*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52e52*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52e53*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52e54*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52e55*4+0x02000000,0x842); +reg_write( DDR_REG_BASE +0x52e56*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52e57*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52e58*4+0x02000000,0x76ad); +reg_write( DDR_REG_BASE +0x52e59*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x52e5a*4+0x02000000,0x43db); +reg_write( DDR_REG_BASE +0x52e5b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52e5c*4+0x02000000,0x4400); +reg_write( DDR_REG_BASE +0x52e5d*4+0x02000000,0xf016); +reg_write( DDR_REG_BASE +0x52e5e*4+0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x52e5f*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52e60*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52e61*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x52e62*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52e63*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x52e64*4+0x02000000,0x822); +reg_write( DDR_REG_BASE +0x52e65*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52e66*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x52e67*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52e68*4+0x02000000,0x4163); +reg_write( DDR_REG_BASE +0x52e69*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52e6a*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52e6b*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x52e6c*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52e6d*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x52e6e*4+0x02000000,0x80e); +reg_write( DDR_REG_BASE +0x52e6f*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52e70*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x52e71*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x52e72*4+0x02000000,0xdd9); +reg_write( DDR_REG_BASE +0x52e73*4+0x02000000,0x9234); +reg_write( DDR_REG_BASE +0x52e74*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52e75*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52e76*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52e77*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52e78*4+0x02000000,0x440c); +reg_write( DDR_REG_BASE +0x52e79*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52e7a*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52e7b*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x52e7c*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52e7d*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x52e7e*4+0x02000000,0xfee); +reg_write( DDR_REG_BASE +0x52e7f*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52e80*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x52e81*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52e82*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52e83*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52e84*4+0x02000000,0xdbb0); +reg_write( DDR_REG_BASE +0x52e85*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x52e86*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x52e87*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x52e88*4+0x02000000,0xfda); +reg_write( DDR_REG_BASE +0x52e89*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52e8a*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x52e8b*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52e8c*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x52e8d*4+0x02000000,0x764c); +reg_write( DDR_REG_BASE +0x52e8e*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x52e8f*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x52e90*4+0x02000000,0xc742); +reg_write( DDR_REG_BASE +0x52e91*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x52e92*4+0x02000000,0xfc6); +reg_write( DDR_REG_BASE +0x52e93*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52e94*4+0x02000000,0x1c00); +reg_write( DDR_REG_BASE +0x52e95*4+0x02000000,0x3041); +reg_write( DDR_REG_BASE +0x52e96*4+0x02000000,0xe8f); +reg_write( DDR_REG_BASE +0x52e97*4+0x02000000,0x1235); +reg_write( DDR_REG_BASE +0x52e98*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52e99*4+0x02000000,0xf7a); +reg_write( DDR_REG_BASE +0x52e9a*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52e9b*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52e9c*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52e9d*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52e9e*4+0x02000000,0x7b2); +reg_write( DDR_REG_BASE +0x52e9f*4+0x02000000,0x1001); +reg_write( DDR_REG_BASE +0x52ea0*4+0x02000000,0x8b); +reg_write( DDR_REG_BASE +0x52ea1*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52ea2*4+0x02000000,0x708c); +reg_write( DDR_REG_BASE +0x52ea3*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52ea4*4+0x02000000,0x7b2); +reg_write( DDR_REG_BASE +0x52ea5*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52ea6*4+0x02000000,0xf02b); +reg_write( DDR_REG_BASE +0x52ea7*4+0x02000000,0x241a); +reg_write( DDR_REG_BASE +0x52ea8*4+0x02000000,0x1f80); +reg_write( DDR_REG_BASE +0x52ea9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52eaa*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x52eab*4+0x02000000,0x2444); +reg_write( DDR_REG_BASE +0x52eac*4+0x02000000,0x1042); +reg_write( DDR_REG_BASE +0x52ead*4+0x02000000,0xc108); +reg_write( DDR_REG_BASE +0x52eae*4+0x02000000,0x206c); +reg_write( DDR_REG_BASE +0x52eaf*4+0x02000000,0x2c3); +reg_write( DDR_REG_BASE +0x52eb0*4+0x02000000,0x4040); +reg_write( DDR_REG_BASE +0x52eb1*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52eb2*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52eb3*4+0x02000000,0x7034); +reg_write( DDR_REG_BASE +0x52eb4*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x52eb5*4+0x02000000,0x21); +reg_write( DDR_REG_BASE +0x52eb6*4+0x02000000,0x7865); +reg_write( DDR_REG_BASE +0x52eb7*4+0x02000000,0x781b); +reg_write( DDR_REG_BASE +0x52eb8*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x52eb9*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52eba*4+0x02000000,0x9002); +reg_write( DDR_REG_BASE +0x52ebb*4+0x02000000,0x166); +reg_write( DDR_REG_BASE +0x52ebc*4+0x02000000,0x90e0); +reg_write( DDR_REG_BASE +0x52ebd*4+0x02000000,0xef13); +reg_write( DDR_REG_BASE +0x52ebe*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52ebf*4+0x02000000,0x229a); +reg_write( DDR_REG_BASE +0x52ec0*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52ec1*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x52ec2*4+0x02000000,0xd01); +reg_write( DDR_REG_BASE +0x52ec3*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x52ec4*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52ec5*4+0x02000000,0x7b05); +reg_write( DDR_REG_BASE +0x52ec6*4+0x02000000,0x7a65); +reg_write( DDR_REG_BASE +0x52ec7*4+0x02000000,0x785b); +reg_write( DDR_REG_BASE +0x52ec8*4+0x02000000,0xb891); +reg_write( DDR_REG_BASE +0x52ec9*4+0x02000000,0xb89c); +reg_write( DDR_REG_BASE +0x52eca*4+0x02000000,0xb89f); +reg_write( DDR_REG_BASE +0x52ecb*4+0x02000000,0x9020); +reg_write( DDR_REG_BASE +0x52ecc*4+0x02000000,0x2155); +reg_write( DDR_REG_BASE +0x52ecd*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x52ece*4+0x02000000,0xb020); +reg_write( DDR_REG_BASE +0x52ecf*4+0x02000000,0x65fd); +reg_write( DDR_REG_BASE +0x52ed0*4+0x02000000,0x7185); +reg_write( DDR_REG_BASE +0x52ed1*4+0x02000000,0xbaf); +reg_write( DDR_REG_BASE +0x52ed2*4+0x02000000,0x9325); +reg_write( DDR_REG_BASE +0x52ed3*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52ed4*4+0x02000000,0xa16); +reg_write( DDR_REG_BASE +0x52ed5*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52ed6*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52ed7*4+0x02000000,0x86e); +reg_write( DDR_REG_BASE +0x52ed8*4+0x02000000,0xfe8f); +reg_write( DDR_REG_BASE +0x52ed9*4+0x02000000,0xd7d); +reg_write( DDR_REG_BASE +0x52eda*4+0x02000000,0x9031); +reg_write( DDR_REG_BASE +0x52edb*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x52edc*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x52edd*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52ede*4+0x02000000,0x16b); +reg_write( DDR_REG_BASE +0x52edf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52ee0*4+0x02000000,0xb2e); +reg_write( DDR_REG_BASE +0x52ee1*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x52ee2*4+0x02000000,0x2578); +reg_write( DDR_REG_BASE +0x52ee3*4+0x02000000,0x1000); +reg_write( DDR_REG_BASE +0x52ee4*4+0x02000000,0xc0a9); +reg_write( DDR_REG_BASE +0x52ee5*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x52ee6*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x52ee7*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x52ee8*4+0x02000000,0xc0f1); +reg_write( DDR_REG_BASE +0x52ee9*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x52eea*4+0x02000000,0x3302); +reg_write( DDR_REG_BASE +0x52eeb*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x52eec*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52eed*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52eee*4+0x02000000,0x5f4); +reg_write( DDR_REG_BASE +0x52eef*4+0x02000000,0xaa6); +reg_write( DDR_REG_BASE +0x52ef0*4+0x02000000,0xfd2f); +reg_write( DDR_REG_BASE +0x52ef1*4+0x02000000,0xda8a); +reg_write( DDR_REG_BASE +0x52ef2*4+0x02000000,0xc080); +reg_write( DDR_REG_BASE +0x52ef3*4+0x02000000,0xba6); +reg_write( DDR_REG_BASE +0x52ef4*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x52ef5*4+0x02000000,0xd98a); +reg_write( DDR_REG_BASE +0x52ef6*4+0x02000000,0xd80f); +reg_write( DDR_REG_BASE +0x52ef7*4+0x02000000,0x9d2); +reg_write( DDR_REG_BASE +0x52ef8*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52ef9*4+0x02000000,0xd90f); +reg_write( DDR_REG_BASE +0x52efa*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x52efb*4+0x02000000,0x3302); +reg_write( DDR_REG_BASE +0x52efc*4+0x02000000,0xc0d1); +reg_write( DDR_REG_BASE +0x52efd*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x52efe*4+0x02000000,0xc2e6); +reg_write( DDR_REG_BASE +0x52eff*4+0x02000000,0x1cfc); +reg_write( DDR_REG_BASE +0x52f00*4+0x02000000,0xb6c8); +reg_write( DDR_REG_BASE +0x52f01*4+0x02000000,0x2482); +reg_write( DDR_REG_BASE +0x52f02*4+0x02000000,0x3502); +reg_write( DDR_REG_BASE +0x52f03*4+0x02000000,0xc147); +reg_write( DDR_REG_BASE +0x52f04*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52f05*4+0x02000000,0xa02); +reg_write( DDR_REG_BASE +0x52f06*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52f07*4+0x02000000,0x4318); +reg_write( DDR_REG_BASE +0x52f08*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52f09*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52f0a*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x52f0b*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52f0c*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52f0d*4+0x02000000,0xc62); +reg_write( DDR_REG_BASE +0x52f0e*4+0x02000000,0xfdef); +reg_write( DDR_REG_BASE +0x52f0f*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52f10*4+0x02000000,0x208c); +reg_write( DDR_REG_BASE +0x52f11*4+0x02000000,0x8e82); +reg_write( DDR_REG_BASE +0x52f12*4+0x02000000,0x71ad); +reg_write( DDR_REG_BASE +0x52f13*4+0x02000000,0xdffe); +reg_write( DDR_REG_BASE +0x52f14*4+0x02000000,0xf705); +reg_write( DDR_REG_BASE +0x52f15*4+0x02000000,0xc52); +reg_write( DDR_REG_BASE +0x52f16*4+0x02000000,0xfdcf); +reg_write( DDR_REG_BASE +0x52f17*4+0x02000000,0x2054); +reg_write( DDR_REG_BASE +0x52f18*4+0x02000000,0x88f); +reg_write( DDR_REG_BASE +0x52f19*4+0x02000000,0x2344); +reg_write( DDR_REG_BASE +0x52f1a*4+0x02000000,0x37c0); +reg_write( DDR_REG_BASE +0x52f1b*4+0x02000000,0xe806); +reg_write( DDR_REG_BASE +0x52f1c*4+0x02000000,0xb861); +reg_write( DDR_REG_BASE +0x52f1d*4+0x02000000,0x801); +reg_write( DDR_REG_BASE +0x52f1e*4+0x02000000,0x31); +reg_write( DDR_REG_BASE +0x52f1f*4+0x02000000,0x7dbb); +reg_write( DDR_REG_BASE +0x52f20*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52f21*4+0x02000000,0x201a); +reg_write( DDR_REG_BASE +0x52f22*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x52f23*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x52f24*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52f25*4+0x02000000,0xc049); +reg_write( DDR_REG_BASE +0x52f26*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52f27*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x52f28*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52f29*4+0x02000000,0xaa); +reg_write( DDR_REG_BASE +0x52f2a*4+0x02000000,0xc04a); +reg_write( DDR_REG_BASE +0x52f2b*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52f2c*4+0x02000000,0x7045); +reg_write( DDR_REG_BASE +0x52f2d*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52f2e*4+0x02000000,0xe0aa); +reg_write( DDR_REG_BASE +0x52f2f*4+0x02000000,0xf76); +reg_write( DDR_REG_BASE +0x52f30*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x52f31*4+0x02000000,0x70cd); +reg_write( DDR_REG_BASE +0x52f32*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52f33*4+0x02000000,0xb88f); +reg_write( DDR_REG_BASE +0x52f34*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52f35*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52f36*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52f37*4+0x02000000,0xe002); +reg_write( DDR_REG_BASE +0x52f38*4+0x02000000,0xd940); +reg_write( DDR_REG_BASE +0x52f39*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x52f3a*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x52f3b*4+0x02000000,0xe002); +reg_write( DDR_REG_BASE +0x52f3c*4+0x02000000,0xc02); +reg_write( DDR_REG_BASE +0x52f3d*4+0x02000000,0xfdaf); +reg_write( DDR_REG_BASE +0x52f3e*4+0x02000000,0xb032); +reg_write( DDR_REG_BASE +0x52f3f*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52f40*4+0x02000000,0xf009); +reg_write( DDR_REG_BASE +0x52f41*4+0x02000000,0x2156); +reg_write( DDR_REG_BASE +0x52f42*4+0x02000000,0xe01); +reg_write( DDR_REG_BASE +0x52f43*4+0x02000000,0x2105); +reg_write( DDR_REG_BASE +0x52f44*4+0x02000000,0xf81); +reg_write( DDR_REG_BASE +0x52f45*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x52f46*4+0x02000000,0xe000); +reg_write( DDR_REG_BASE +0x52f47*4+0x02000000,0xb1c0); +reg_write( DDR_REG_BASE +0x52f48*4+0x02000000,0x7104); +reg_write( DDR_REG_BASE +0x52f49*4+0x02000000,0x8f3); +reg_write( DDR_REG_BASE +0x52f4a*4+0x02000000,0x80f4); +reg_write( DDR_REG_BASE +0x52f4b*4+0x02000000,0x791b); +reg_write( DDR_REG_BASE +0x52f4c*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52f4d*4+0x02000000,0x7101); +reg_write( DDR_REG_BASE +0x52f4e*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52f4f*4+0x02000000,0x4a); +reg_write( DDR_REG_BASE +0x52f50*4+0x02000000,0xc005); +reg_write( DDR_REG_BASE +0x52f51*4+0x02000000,0x2111); +reg_write( DDR_REG_BASE +0x52f52*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52f53*4+0x02000000,0xd9aa); +reg_write( DDR_REG_BASE +0x52f54*4+0x02000000,0xd898); +reg_write( DDR_REG_BASE +0x52f55*4+0x02000000,0x20ca); +reg_write( DDR_REG_BASE +0x52f56*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x52f57*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52f58*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x52f59*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52f5a*4+0x02000000,0xe04c); +reg_write( DDR_REG_BASE +0x52f5b*4+0x02000000,0x202f); +reg_write( DDR_REG_BASE +0x52f5c*4+0x02000000,0x6c0); +reg_write( DDR_REG_BASE +0x52f5d*4+0x02000000,0x2056); +reg_write( DDR_REG_BASE +0x52f5e*4+0x02000000,0xe00); +reg_write( DDR_REG_BASE +0x52f5f*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52f60*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52f61*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x52f62*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x52f63*4+0x02000000,0x9000); +reg_write( DDR_REG_BASE +0x52f64*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52f65*4+0x02000000,0x11e9); +reg_write( DDR_REG_BASE +0x52f66*4+0x02000000,0x700); +reg_write( DDR_REG_BASE +0x52f67*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52f68*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x52f69*4+0x02000000,0xd42); +reg_write( DDR_REG_BASE +0x52f6a*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52f6b*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x52f6c*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52f6d*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x52f6e*4+0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x52f6f*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52f70*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52f71*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52f72*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x52f73*4+0x02000000,0xc642); +reg_write( DDR_REG_BASE +0x52f74*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x52f75*4+0x02000000,0xe02); +reg_write( DDR_REG_BASE +0x52f76*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52f77*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x52f78*4+0x02000000,0x78af); +reg_write( DDR_REG_BASE +0x52f79*4+0x02000000,0xc048); +reg_write( DDR_REG_BASE +0x52f7a*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52f7b*4+0x02000000,0x2744); +reg_write( DDR_REG_BASE +0x52f7c*4+0x02000000,0x1040); +reg_write( DDR_REG_BASE +0x52f7d*4+0x02000000,0x671f); +reg_write( DDR_REG_BASE +0x52f7e*4+0x02000000,0x78ef); +reg_write( DDR_REG_BASE +0x52f7f*4+0x02000000,0xc045); +reg_write( DDR_REG_BASE +0x52f80*4+0x02000000,0xc305); +reg_write( DDR_REG_BASE +0x52f81*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x52f82*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52f83*4+0x02000000,0xb990); +reg_write( DDR_REG_BASE +0x52f84*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x52f85*4+0x02000000,0xc643); +reg_write( DDR_REG_BASE +0x52f86*4+0x02000000,0xc641); +reg_write( DDR_REG_BASE +0x52f87*4+0x02000000,0xdde); +reg_write( DDR_REG_BASE +0x52f88*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52f89*4+0x02000000,0xc640); +reg_write( DDR_REG_BASE +0x52f8a*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52f8b*4+0x02000000,0xd96); +reg_write( DDR_REG_BASE +0x52f8c*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52f8d*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52f8e*4+0x02000000,0x47cb); +reg_write( DDR_REG_BASE +0x52f8f*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x52f90*4+0x02000000,0x7b0); +reg_write( DDR_REG_BASE +0x52f91*4+0x02000000,0x8f20); +reg_write( DDR_REG_BASE +0x52f92*4+0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x52f93*4+0x02000000,0x60da); +reg_write( DDR_REG_BASE +0x52f94*4+0x02000000,0x4020); +reg_write( DDR_REG_BASE +0x52f95*4+0x02000000,0x209f); +reg_write( DDR_REG_BASE +0x52f96*4+0x02000000,0x901); +reg_write( DDR_REG_BASE +0x52f97*4+0x02000000,0x60d8); +reg_write( DDR_REG_BASE +0x52f98*4+0x02000000,0x60f8); +reg_write( DDR_REG_BASE +0x52f99*4+0x02000000,0x8814); +reg_write( DDR_REG_BASE +0x52f9a*4+0x02000000,0x71c5); +reg_write( DDR_REG_BASE +0x52f9b*4+0x02000000,0xaa00); +reg_write( DDR_REG_BASE +0x52f9c*4+0x02000000,0xe6e3); +reg_write( DDR_REG_BASE +0x52f9d*4+0x02000000,0xc08c); +reg_write( DDR_REG_BASE +0x52f9e*4+0x02000000,0xf7f5); +reg_write( DDR_REG_BASE +0x52f9f*4+0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x52fa0*4+0x02000000,0xc18c); +reg_write( DDR_REG_BASE +0x52fa1*4+0x02000000,0xc82); +reg_write( DDR_REG_BASE +0x52fa2*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x52fa3*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52fa4*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x52fa5*4+0x02000000,0x7100); +reg_write( DDR_REG_BASE +0x52fa6*4+0x02000000,0x9008); +reg_write( DDR_REG_BASE +0x52fa7*4+0x02000000,0x1e0); +reg_write( DDR_REG_BASE +0x52fa8*4+0x02000000,0x46cb); +reg_write( DDR_REG_BASE +0x52fa9*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x52faa*4+0x02000000,0xe1e0); +reg_write( DDR_REG_BASE +0x52fab*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x52fac*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x52fad*4+0x02000000,0xf0ff); +reg_write( DDR_REG_BASE +0x52fae*4+0x02000000,0xc04b); +reg_write( DDR_REG_BASE +0x52faf*4+0x02000000,0xb888); +reg_write( DDR_REG_BASE +0x52fb0*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x52fb1*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52fb2*4+0x02000000,0xc206); +reg_write( DDR_REG_BASE +0x52fb3*4+0x02000000,0x209a); +reg_write( DDR_REG_BASE +0x52fb4*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52fb5*4+0x02000000,0x7a24); +reg_write( DDR_REG_BASE +0x52fb6*4+0x02000000,0x7932); +reg_write( DDR_REG_BASE +0x52fb7*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52fb8*4+0x02000000,0x7824); +reg_write( DDR_REG_BASE +0x52fb9*4+0x02000000,0x7845); +reg_write( DDR_REG_BASE +0x52fba*4+0x02000000,0xc046); +reg_write( DDR_REG_BASE +0x52fbb*4+0x02000000,0xb887); +reg_write( DDR_REG_BASE +0x52fbc*4+0x02000000,0x1ef2); +reg_write( DDR_REG_BASE +0x52fbd*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x52fbe*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x52fbf*4+0x02000000,0x7045); +reg_write( DDR_REG_BASE +0x52fc0*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x52fc1*4+0x02000000,0xe0e8); +reg_write( DDR_REG_BASE +0x52fc2*4+0x02000000,0xa96); +reg_write( DDR_REG_BASE +0x52fc3*4+0x02000000,0xfdcf); +reg_write( DDR_REG_BASE +0x52fc4*4+0x02000000,0xc044); +reg_write( DDR_REG_BASE +0x52fc5*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x52fc6*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x52fc7*4+0x02000000,0xc86); +reg_write( DDR_REG_BASE +0x52fc8*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52fc9*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x52fca*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x52fcb*4+0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x52fcc*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52fcd*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52fce*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52fcf*4+0x02000000,0x4528); +reg_write( DDR_REG_BASE +0x52fd0*4+0x02000000,0xc143); +reg_write( DDR_REG_BASE +0x52fd1*4+0x02000000,0xc142); +reg_write( DDR_REG_BASE +0x52fd2*4+0x02000000,0xc141); +reg_write( DDR_REG_BASE +0x52fd3*4+0x02000000,0xd46); +reg_write( DDR_REG_BASE +0x52fd4*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52fd5*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x52fd6*4+0x02000000,0xefa); +reg_write( DDR_REG_BASE +0x52fd7*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52fd8*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52fd9*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x52fda*4+0x02000000,0xc305); +reg_write( DDR_REG_BASE +0x52fdb*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x52fdc*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x52fdd*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52fde*4+0x02000000,0xb990); +reg_write( DDR_REG_BASE +0x52fdf*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x52fe0*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52fe1*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52fe2*4+0x02000000,0xd26); +reg_write( DDR_REG_BASE +0x52fe3*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52fe4*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52fe5*4+0x02000000,0xc004); +reg_write( DDR_REG_BASE +0x52fe6*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x52fe7*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x52fe8*4+0x02000000,0x2044); +reg_write( DDR_REG_BASE +0x52fe9*4+0x02000000,0x41); +reg_write( DDR_REG_BASE +0x52fea*4+0x02000000,0x6038); +reg_write( DDR_REG_BASE +0x52feb*4+0x02000000,0xe01e); +reg_write( DDR_REG_BASE +0x52fec*4+0x02000000,0x7b0f); +reg_write( DDR_REG_BASE +0x52fed*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52fee*4+0x02000000,0x742c); +reg_write( DDR_REG_BASE +0x52fef*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52ff0*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52ff1*4+0x02000000,0xd0a); +reg_write( DDR_REG_BASE +0x52ff2*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x52ff3*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x52ff4*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x52ff5*4+0x02000000,0xb890); +reg_write( DDR_REG_BASE +0x52ff6*4+0x02000000,0x791d); +reg_write( DDR_REG_BASE +0x52ff7*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x52ff8*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x52ff9*4+0x02000000,0x726c); +reg_write( DDR_REG_BASE +0x52ffa*4+0x02000000,0x1c0c); +reg_write( DDR_REG_BASE +0x52ffb*4+0x02000000,0x30c1); +reg_write( DDR_REG_BASE +0x52ffc*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x52ffd*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x52ffe*4+0x02000000,0xcee); +reg_write( DDR_REG_BASE +0x52fff*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53000*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53001*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53002*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53003*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x53004*4+0x02000000,0xdb10); +reg_write( DDR_REG_BASE +0x53005*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x53006*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x53007*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53008*4+0x02000000,0xcda); +reg_write( DDR_REG_BASE +0x53009*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x5300a*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5300b*4+0x02000000,0xe76); +reg_write( DDR_REG_BASE +0x5300c*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x5300d*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5300e*4+0x02000000,0xf852); +reg_write( DDR_REG_BASE +0x5300f*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x53010*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x53011*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53012*4+0x02000000,0xcc6); +reg_write( DDR_REG_BASE +0x53013*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53014*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53015*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x53016*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53017*4+0x02000000,0x6210); +reg_write( DDR_REG_BASE +0x53018*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53019*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x5301a*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5301b*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x5301c*4+0x02000000,0x730c); +reg_write( DDR_REG_BASE +0x5301d*4+0x02000000,0xc72); +reg_write( DDR_REG_BASE +0x5301e*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x5301f*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53020*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53021*4+0x02000000,0x408); +reg_write( DDR_REG_BASE +0x53022*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53023*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x53024*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53025*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x53026*4+0x02000000,0x1600); +reg_write( DDR_REG_BASE +0x53027*4+0x02000000,0x7080); +reg_write( DDR_REG_BASE +0x53028*4+0x02000000,0x8000); +reg_write( DDR_REG_BASE +0x53029*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5302a*4+0x02000000,0x80b); +reg_write( DDR_REG_BASE +0x5302b*4+0x02000000,0xbf); +reg_write( DDR_REG_BASE +0x5302c*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x5302d*4+0x02000000,0x606); +reg_write( DDR_REG_BASE +0x5302e*4+0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x5302f*4+0x02000000,0xd833); +reg_write( DDR_REG_BASE +0x53030*4+0x02000000,0xc4a); +reg_write( DDR_REG_BASE +0x53031*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53032*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53033*4+0x02000000,0xc006); +reg_write( DDR_REG_BASE +0x53034*4+0x02000000,0xc18c); +reg_write( DDR_REG_BASE +0x53035*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53036*4+0x02000000,0x1ef2); +reg_write( DDR_REG_BASE +0x53037*4+0x02000000,0x9004); +reg_write( DDR_REG_BASE +0x53038*4+0x02000000,0xb52); +reg_write( DDR_REG_BASE +0x53039*4+0x02000000,0xffaf); +reg_write( DDR_REG_BASE +0x5303a*4+0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x5303b*4+0x02000000,0x8f00); +reg_write( DDR_REG_BASE +0x5303c*4+0x02000000,0x41c3); +reg_write( DDR_REG_BASE +0x5303d*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5303e*4+0x02000000,0x600); +reg_write( DDR_REG_BASE +0x5303f*4+0x02000000,0xc140); +reg_write( DDR_REG_BASE +0x53040*4+0x02000000,0x4fac); +reg_write( DDR_REG_BASE +0x53041*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x53042*4+0x02000000,0x80e); +reg_write( DDR_REG_BASE +0x53043*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x53044*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x53045*4+0x02000000,0xc00a); +reg_write( DDR_REG_BASE +0x53046*4+0x02000000,0x70ad); +reg_write( DDR_REG_BASE +0x53047*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x53048*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53049*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x5304a*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x5304b*4+0x02000000,0xe0aa); +reg_write( DDR_REG_BASE +0x5304c*4+0x02000000,0x40c3); +reg_write( DDR_REG_BASE +0x5304d*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x5304e*4+0x02000000,0xe002); +reg_write( DDR_REG_BASE +0x5304f*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53050*4+0x02000000,0x7344); +reg_write( DDR_REG_BASE +0x53051*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53052*4+0x02000000,0xe002); +reg_write( DDR_REG_BASE +0x53053*4+0x02000000,0xb0b2); +reg_write( DDR_REG_BASE +0x53054*4+0x02000000,0xb6a); +reg_write( DDR_REG_BASE +0x53055*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53056*4+0x02000000,0x208a); +reg_write( DDR_REG_BASE +0x53057*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x53058*4+0x02000000,0x1200); +reg_write( DDR_REG_BASE +0x53059*4+0x02000000,0x3083); +reg_write( DDR_REG_BASE +0x5305a*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5305b*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5305c*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x5305d*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5305e*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x5305f*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53060*4+0x02000000,0xc2a); +reg_write( DDR_REG_BASE +0x53061*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53062*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53063*4+0x02000000,0xc008); +reg_write( DDR_REG_BASE +0x53064*4+0x02000000,0xc305); +reg_write( DDR_REG_BASE +0x53065*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53066*4+0x02000000,0xc042); +reg_write( DDR_REG_BASE +0x53067*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x53068*4+0x02000000,0xb990); +reg_write( DDR_REG_BASE +0x53069*4+0x02000000,0x724c); +reg_write( DDR_REG_BASE +0x5306a*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x5306b*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x5306c*4+0x02000000,0xc12); +reg_write( DDR_REG_BASE +0x5306d*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x5306e*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x5306f*4+0x02000000,0xf822); +reg_write( DDR_REG_BASE +0x53070*4+0x02000000,0xc543); +reg_write( DDR_REG_BASE +0x53071*4+0x02000000,0xc542); +reg_write( DDR_REG_BASE +0x53072*4+0x02000000,0xc541); +reg_write( DDR_REG_BASE +0x53073*4+0x02000000,0xc06); +reg_write( DDR_REG_BASE +0x53074*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53075*4+0x02000000,0xc540); +reg_write( DDR_REG_BASE +0x53076*4+0x02000000,0x700c); +reg_write( DDR_REG_BASE +0x53077*4+0x02000000,0xbbe); +reg_write( DDR_REG_BASE +0x53078*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x53079*4+0x02000000,0x712c); +reg_write( DDR_REG_BASE +0x5307a*4+0x02000000,0xc00b); +reg_write( DDR_REG_BASE +0x5307b*4+0x02000000,0xb600); +reg_write( DDR_REG_BASE +0x5307c*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5307d*4+0x02000000,0x7344); +reg_write( DDR_REG_BASE +0x5307e*4+0x02000000,0x9005); +reg_write( DDR_REG_BASE +0x5307f*4+0x02000000,0xe0e8); +reg_write( DDR_REG_BASE +0x53080*4+0x02000000,0xf00a); +reg_write( DDR_REG_BASE +0x53081*4+0x02000000,0x2056); +reg_write( DDR_REG_BASE +0x53082*4+0x02000000,0xe00); +reg_write( DDR_REG_BASE +0x53083*4+0x02000000,0x2005); +reg_write( DDR_REG_BASE +0x53084*4+0x02000000,0xf80); +reg_write( DDR_REG_BASE +0x53085*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x53086*4+0x02000000,0xe000); +reg_write( DDR_REG_BASE +0x53087*4+0x02000000,0x1800); +reg_write( DDR_REG_BASE +0x53088*4+0x02000000,0x3c5); +reg_write( DDR_REG_BASE +0x53089*4+0x02000000,0x71a5); +reg_write( DDR_REG_BASE +0x5308a*4+0x02000000,0xdef); +reg_write( DDR_REG_BASE +0x5308b*4+0x02000000,0x90b4); +reg_write( DDR_REG_BASE +0x5308c*4+0x02000000,0x78bb); +reg_write( DDR_REG_BASE +0x5308d*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x5308e*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x5308f*4+0x02000000,0x7004); +reg_write( DDR_REG_BASE +0x53090*4+0x02000000,0x9009); +reg_write( DDR_REG_BASE +0x53091*4+0x02000000,0xe1c4); +reg_write( DDR_REG_BASE +0x53092*4+0x02000000,0x1e00); +reg_write( DDR_REG_BASE +0x53093*4+0x02000000,0x7005); +reg_write( DDR_REG_BASE +0x53094*4+0x02000000,0x9003); +reg_write( DDR_REG_BASE +0x53095*4+0x02000000,0xe004); +reg_write( DDR_REG_BASE +0x53096*4+0x02000000,0xc007); +reg_write( DDR_REG_BASE +0x53097*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x53098*4+0x02000000,0xdd2); +reg_write( DDR_REG_BASE +0x53099*4+0x02000000,0xfeef); +reg_write( DDR_REG_BASE +0x5309a*4+0x02000000,0x704c); +reg_write( DDR_REG_BASE +0x5309b*4+0x02000000,0x4063); +reg_write( DDR_REG_BASE +0x5309c*4+0x02000000,0xed2); +reg_write( DDR_REG_BASE +0x5309d*4+0x02000000,0xfd6f); +reg_write( DDR_REG_BASE +0x5309e*4+0x02000000,0x702c); +reg_write( DDR_REG_BASE +0x5309f*4+0x02000000,0xc109); +reg_write( DDR_REG_BASE +0x530a0*4+0x02000000,0x2055); +reg_write( DDR_REG_BASE +0x530a1*4+0x02000000,0xd00); +reg_write( DDR_REG_BASE +0x530a2*4+0x02000000,0x714c); +reg_write( DDR_REG_BASE +0x530a3*4+0x02000000,0x7825); +reg_write( DDR_REG_BASE +0x530a4*4+0x02000000,0xc107); +reg_write( DDR_REG_BASE +0x530a5*4+0x02000000,0x89e); +reg_write( DDR_REG_BASE +0x530a6*4+0x02000000,0xffef); +reg_write( DDR_REG_BASE +0x530a7*4+0x02000000,0x706c); +reg_write( DDR_REG_BASE +0x530a8*4+0x02000000,0xcca); +reg_write( DDR_REG_BASE +0x530a9*4+0x02000000,0xfe4f); +reg_write( DDR_REG_BASE +0x530aa*4+0x02000000,0xe8a); +reg_write( DDR_REG_BASE +0x530ab*4+0x02000000,0xfecf); +reg_write( DDR_REG_BASE +0x530ac*4+0x02000000,0x2480); +reg_write( DDR_REG_BASE +0x530ad*4+0x02000000,0x3502); +reg_write( DDR_REG_BASE +0x530ae*4+0x02000000,0x1404); +reg_write( DDR_REG_BASE +0x530af*4+0x02000000,0x341b); +reg_write( DDR_REG_BASE +0x530b0*4+0x02000000,0xc6c6); +reg_write( DDR_REG_BASE +0x530b1*4+0x02000000,0x78e0); +reg_write( DDR_REG_BASE +0x530b2*4+0x02000000,0xd8ff); +reg_write( DDR_REG_BASE +0x530b3*4+0x02000000,0xd980); +reg_write( DDR_REG_BASE +0x530b4*4+0x02000000,0x754c); +reg_write( DDR_REG_BASE +0x530b5*4+0x02000000,0x746c); +reg_write( DDR_REG_BASE +0x530b6*4+0x02000000,0x7ee0); +reg_write( DDR_REG_BASE +0x530b7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530b8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530b9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530ba*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530bb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530bc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530bd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530be*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530bf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530c0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530c1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530c2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530c3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530c4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530c5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530c6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530c7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530c8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530c9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530ca*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530cb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530cc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530cd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530ce*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530cf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530d0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530d1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530d2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530d3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530d4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530d5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530d6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530d7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530d8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530d9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530da*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530db*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530dc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530dd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530de*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530df*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530e0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530e1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530e2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530e3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530e4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530e5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530e6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530e7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530e8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530e9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530ea*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530eb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530ec*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530ed*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530ee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530ef*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530f0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530f1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530f2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530f3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530f4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530f5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530f6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530f7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530f8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530f9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530fa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530fb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530fc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530fd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530fe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x530ff*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53100*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53101*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53102*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53103*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53104*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53105*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53106*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53107*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53108*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53109*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5310a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5310b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5310c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5310d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5310e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5310f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53110*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53111*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53112*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53113*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53114*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53115*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53116*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53117*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53118*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53119*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5311a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5311b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5311c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5311d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5311e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5311f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53120*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53121*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53122*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53123*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53124*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53125*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53126*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53127*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53128*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53129*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5312a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5312b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5312c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5312d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5312e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5312f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53130*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53131*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53132*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53133*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53134*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53135*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53136*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53137*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53138*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53139*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5313a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5313b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5313c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5313d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5313e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5313f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53140*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53141*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53142*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53143*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53144*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53145*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53146*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53147*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53148*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53149*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5314a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5314b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5314c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5314d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5314e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5314f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53150*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53151*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53152*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53153*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53154*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53155*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53156*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53157*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53158*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53159*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5315a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5315b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5315c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5315d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5315e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5315f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53160*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53161*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53162*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53163*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53164*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53165*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53166*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53167*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53168*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53169*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5316a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5316b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5316c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5316d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5316e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5316f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53170*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53171*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53172*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53173*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53174*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53175*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53176*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53177*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53178*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53179*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5317a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5317b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5317c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5317d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5317e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5317f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53180*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53181*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53182*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53183*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53184*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53185*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53186*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53187*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53188*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53189*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5318a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5318b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5318c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5318d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5318e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5318f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53190*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53191*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53192*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53193*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53194*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53195*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53196*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53197*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53198*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53199*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5319a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5319b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5319c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5319d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5319e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5319f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531a0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531a1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531a2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531a3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531a4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531a5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531a6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531a7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531a8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531a9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531aa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531ab*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531ac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531ad*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531ae*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531af*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531b0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531b1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531b2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531b3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531b4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531b5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531b6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531b7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531b8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531b9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531ba*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531bb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531bc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531bd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531be*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531bf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531c0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531c1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531c2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531c3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531c4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531c5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531c6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531c7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531c8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531c9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531ca*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531cb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531cc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531cd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531ce*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531cf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531d0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531d1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531d2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531d3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531d4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531d5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531d6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531d7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531d8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531d9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531da*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531db*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531dc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531dd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531de*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531df*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531e0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531e1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531e2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531e3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531e4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531e5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531e6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531e7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531e8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531e9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531ea*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531eb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531ec*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531ed*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531ee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531ef*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531f0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531f1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531f2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531f3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531f4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531f5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531f6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531f7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531f8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531f9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531fa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531fb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531fc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531fd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531fe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x531ff*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53200*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53201*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53202*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53203*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53204*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53205*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53206*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53207*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53208*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53209*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5320a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5320b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5320c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5320d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5320e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5320f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53210*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53211*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53212*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53213*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53214*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53215*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53216*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53217*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53218*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53219*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5321a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5321b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5321c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5321d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5321e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5321f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53220*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53221*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53222*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53223*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53224*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53225*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53226*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53227*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53228*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53229*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5322a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5322b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5322c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5322d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5322e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5322f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53230*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53231*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53232*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53233*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53234*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53235*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53236*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53237*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53238*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53239*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5323a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5323b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5323c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5323d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5323e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5323f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53240*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53241*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53242*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53243*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53244*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53245*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53246*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53247*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53248*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53249*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5324a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5324b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5324c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5324d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5324e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5324f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53250*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53251*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53252*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53253*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53254*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53255*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53256*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53257*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53258*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53259*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5325a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5325b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5325c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5325d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5325e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5325f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53260*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53261*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53262*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53263*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53264*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53265*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53266*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53267*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53268*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53269*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5326a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5326b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5326c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5326d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5326e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5326f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53270*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53271*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53272*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53273*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53274*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53275*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53276*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53277*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53278*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53279*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5327a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5327b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5327c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5327d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5327e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5327f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53280*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53281*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53282*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53283*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53284*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53285*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53286*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53287*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53288*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53289*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5328a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5328b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5328c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5328d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5328e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5328f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53290*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53291*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53292*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53293*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53294*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53295*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53296*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53297*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53298*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53299*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5329a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5329b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5329c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5329d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5329e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5329f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532a0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532a1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532a2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532a3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532a4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532a5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532a6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532a7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532a8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532a9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532aa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532ab*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532ac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532ad*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532ae*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532af*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532b0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532b1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532b2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532b3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532b4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532b5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532b6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532b7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532b8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532b9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532ba*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532bb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532bc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532bd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532be*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532bf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532c0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532c1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532c2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532c3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532c4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532c5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532c6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532c7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532c8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532c9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532ca*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532cb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532cc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532cd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532ce*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532cf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532d0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532d1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532d2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532d3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532d4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532d5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532d6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532d7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532d8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532d9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532da*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532db*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532dc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532dd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532de*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532df*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532e0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532e1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532e2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532e3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532e4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532e5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532e6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532e7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532e8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532e9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532ea*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532eb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532ec*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532ed*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532ee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532ef*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532f0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532f1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532f2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532f3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532f4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532f5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532f6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532f7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532f8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532f9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532fa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532fb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532fc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532fd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532fe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x532ff*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53300*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53301*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53302*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53303*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53304*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53305*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53306*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53307*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53308*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53309*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5330a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5330b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5330c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5330d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5330e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5330f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53310*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53311*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53312*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53313*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53314*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53315*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53316*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53317*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53318*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53319*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5331a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5331b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5331c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5331d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5331e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5331f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53320*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53321*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53322*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53323*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53324*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53325*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53326*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53327*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53328*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53329*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5332a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5332b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5332c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5332d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5332e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5332f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53330*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53331*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53332*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53333*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53334*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53335*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53336*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53337*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53338*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53339*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5333a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5333b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5333c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5333d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5333e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5333f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53340*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53341*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53342*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53343*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53344*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53345*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53346*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53347*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53348*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53349*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5334a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5334b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5334c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5334d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5334e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5334f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53350*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53351*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53352*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53353*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53354*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53355*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53356*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53357*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53358*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53359*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5335a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5335b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5335c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5335d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5335e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5335f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53360*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53361*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53362*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53363*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53364*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53365*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53366*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53367*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53368*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53369*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5336a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5336b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5336c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5336d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5336e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5336f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53370*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53371*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53372*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53373*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53374*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53375*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53376*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53377*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53378*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53379*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5337a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5337b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5337c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5337d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5337e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5337f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53380*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53381*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53382*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53383*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53384*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53385*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53386*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53387*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53388*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53389*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5338a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5338b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5338c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5338d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5338e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5338f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53390*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53391*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53392*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53393*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53394*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53395*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53396*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53397*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53398*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53399*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5339a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5339b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5339c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5339d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5339e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5339f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533a0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533a1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533a2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533a3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533a4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533a5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533a6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533a7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533a8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533a9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533aa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533ab*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533ac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533ad*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533ae*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533af*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533b0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533b1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533b2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533b3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533b4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533b5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533b6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533b7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533b8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533b9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533ba*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533bb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533bc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533bd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533be*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533bf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533c0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533c1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533c2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533c3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533c4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533c5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533c6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533c7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533c8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533c9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533ca*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533cb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533cc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533cd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533ce*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533cf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533d0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533d1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533d2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533d3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533d4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533d5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533d6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533d7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533d8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533d9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533da*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533db*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533dc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533dd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533de*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533df*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533e0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533e1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533e2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533e3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533e4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533e5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533e6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533e7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533e8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533e9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533ea*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533eb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533ec*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533ed*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533ee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533ef*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533f0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533f1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533f2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533f3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533f4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533f5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533f6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533f7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533f8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533f9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533fa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533fb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533fc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533fd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533fe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x533ff*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53400*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53401*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53402*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53403*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53404*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53405*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53406*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53407*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53408*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53409*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5340a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5340b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5340c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5340d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5340e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5340f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53410*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53411*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53412*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53413*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53414*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53415*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53416*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53417*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53418*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53419*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5341a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5341b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5341c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5341d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5341e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5341f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53420*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53421*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53422*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53423*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53424*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53425*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53426*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53427*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53428*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53429*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5342a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5342b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5342c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5342d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5342e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5342f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53430*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53431*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53432*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53433*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53434*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53435*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53436*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53437*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53438*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53439*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5343a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5343b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5343c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5343d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5343e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5343f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53440*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53441*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53442*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53443*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53444*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53445*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53446*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53447*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53448*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53449*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5344a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5344b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5344c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5344d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5344e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5344f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53450*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53451*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53452*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53453*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53454*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53455*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53456*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53457*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53458*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53459*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5345a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5345b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5345c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5345d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5345e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5345f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53460*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53461*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53462*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53463*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53464*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53465*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53466*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53467*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53468*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53469*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5346a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5346b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5346c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5346d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5346e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5346f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53470*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53471*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53472*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53473*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53474*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53475*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53476*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53477*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53478*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53479*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5347a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5347b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5347c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5347d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5347e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5347f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53480*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53481*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53482*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53483*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53484*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53485*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53486*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53487*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53488*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53489*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5348a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5348b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5348c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5348d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5348e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5348f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53490*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53491*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53492*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53493*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53494*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53495*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53496*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53497*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53498*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53499*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5349a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5349b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5349c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5349d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5349e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5349f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534a0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534a1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534a2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534a3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534a4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534a5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534a6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534a7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534a8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534a9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534aa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534ab*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534ac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534ad*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534ae*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534af*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534b0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534b1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534b2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534b3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534b4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534b5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534b6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534b7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534b8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534b9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534ba*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534bb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534bc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534bd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534be*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534bf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534c0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534c1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534c2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534c3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534c4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534c5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534c6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534c7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534c8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534c9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534ca*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534cb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534cc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534cd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534ce*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534cf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534d0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534d1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534d2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534d3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534d4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534d5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534d6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534d7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534d8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534d9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534da*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534db*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534dc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534dd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534de*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534df*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534e0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534e1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534e2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534e3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534e4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534e5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534e6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534e7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534e8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534e9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534ea*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534eb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534ec*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534ed*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534ee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534ef*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534f0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534f1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534f2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534f3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534f4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534f5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534f6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534f7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534f8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534f9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534fa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534fb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534fc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534fd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534fe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x534ff*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53500*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53501*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53502*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53503*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53504*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53505*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53506*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53507*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53508*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53509*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5350a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5350b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5350c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5350d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5350e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5350f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53510*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53511*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53512*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53513*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53514*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53515*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53516*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53517*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53518*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53519*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5351a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5351b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5351c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5351d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5351e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5351f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53520*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53521*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53522*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53523*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53524*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53525*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53526*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53527*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53528*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53529*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5352a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5352b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5352c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5352d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5352e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5352f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53530*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53531*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53532*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53533*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53534*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53535*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53536*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53537*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53538*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53539*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5353a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5353b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5353c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5353d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5353e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5353f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53540*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53541*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53542*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53543*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53544*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53545*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53546*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53547*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53548*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53549*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5354a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5354b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5354c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5354d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5354e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5354f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53550*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53551*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53552*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53553*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53554*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53555*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53556*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53557*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53558*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53559*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5355a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5355b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5355c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5355d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5355e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5355f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53560*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53561*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53562*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53563*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53564*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53565*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53566*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53567*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53568*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53569*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5356a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5356b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5356c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5356d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5356e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5356f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53570*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53571*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53572*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53573*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53574*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53575*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53576*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53577*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53578*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53579*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5357a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5357b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5357c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5357d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5357e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5357f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53580*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53581*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53582*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53583*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53584*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53585*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53586*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53587*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53588*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53589*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5358a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5358b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5358c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5358d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5358e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5358f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53590*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53591*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53592*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53593*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53594*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53595*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53596*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53597*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53598*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53599*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5359a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5359b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5359c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5359d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5359e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5359f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535a0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535a1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535a2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535a3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535a4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535a5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535a6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535a7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535a8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535a9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535aa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535ab*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535ac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535ad*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535ae*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535af*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535b0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535b1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535b2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535b3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535b4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535b5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535b6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535b7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535b8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535b9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535ba*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535bb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535bc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535bd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535be*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535bf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535c0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535c1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535c2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535c3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535c4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535c5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535c6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535c7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535c8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535c9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535ca*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535cb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535cc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535cd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535ce*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535cf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535d0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535d1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535d2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535d3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535d4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535d5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535d6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535d7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535d8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535d9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535da*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535db*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535dc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535dd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535de*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535df*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535e0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535e1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535e2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535e3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535e4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535e5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535e6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535e7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535e8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535e9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535ea*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535eb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535ec*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535ed*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535ee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535ef*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535f0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535f1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535f2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535f3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535f4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535f5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535f6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535f7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535f8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535f9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535fa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535fb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535fc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535fd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535fe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x535ff*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53600*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53601*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53602*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53603*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53604*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53605*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53606*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53607*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53608*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53609*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5360a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5360b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5360c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5360d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5360e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5360f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53610*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53611*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53612*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53613*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53614*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53615*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53616*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53617*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53618*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53619*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5361a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5361b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5361c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5361d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5361e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5361f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53620*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53621*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53622*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53623*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53624*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53625*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53626*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53627*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53628*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53629*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5362a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5362b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5362c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5362d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5362e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5362f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53630*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53631*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53632*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53633*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53634*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53635*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53636*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53637*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53638*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53639*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5363a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5363b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5363c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5363d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5363e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5363f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53640*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53641*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53642*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53643*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53644*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53645*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53646*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53647*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53648*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53649*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5364a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5364b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5364c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5364d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5364e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5364f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53650*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53651*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53652*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53653*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53654*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53655*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53656*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53657*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53658*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53659*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5365a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5365b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5365c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5365d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5365e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5365f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53660*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53661*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53662*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53663*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53664*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53665*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53666*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53667*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53668*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53669*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5366a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5366b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5366c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5366d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5366e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5366f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53670*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53671*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53672*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53673*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53674*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53675*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53676*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53677*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53678*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53679*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5367a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5367b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5367c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5367d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5367e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5367f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53680*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53681*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53682*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53683*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53684*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53685*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53686*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53687*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53688*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53689*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5368a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5368b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5368c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5368d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5368e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5368f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53690*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53691*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53692*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53693*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53694*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53695*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53696*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53697*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53698*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53699*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5369a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5369b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5369c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5369d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5369e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5369f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536a0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536a1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536a2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536a3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536a4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536a5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536a6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536a7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536a8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536a9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536aa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ab*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ad*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ae*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536af*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536b0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536b1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536b2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536b3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536b4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536b5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536b6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536b7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536b8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536b9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ba*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536bb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536bc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536bd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536be*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536bf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536c0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536c1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536c2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536c3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536c4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536c5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536c6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536c7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536c8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536c9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ca*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536cb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536cc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536cd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ce*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536cf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536d0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536d1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536d2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536d3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536d4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536d5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536d6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536d7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536d8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536d9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536da*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536db*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536dc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536dd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536de*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536df*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536e0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536e1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536e2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536e3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536e4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536e5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536e6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536e7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536e8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536e9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ea*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536eb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ec*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ed*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ef*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536f0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536f1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536f2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536f3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536f4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536f5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536f6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536f7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536f8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536f9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536fa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536fb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536fc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536fd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536fe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x536ff*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53700*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53701*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53702*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53703*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53704*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53705*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53706*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53707*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53708*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53709*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5370a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5370b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5370c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5370d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5370e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5370f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53710*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53711*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53712*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53713*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53714*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53715*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53716*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53717*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53718*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53719*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5371a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5371b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5371c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5371d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5371e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5371f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53720*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53721*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53722*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53723*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53724*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53725*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53726*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53727*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53728*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53729*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5372a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5372b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5372c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5372d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5372e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5372f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53730*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53731*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53732*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53733*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53734*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53735*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53736*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53737*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53738*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53739*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5373a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5373b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5373c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5373d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5373e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5373f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53740*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53741*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53742*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53743*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53744*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53745*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53746*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53747*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53748*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53749*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5374a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5374b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5374c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5374d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5374e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5374f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53750*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53751*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53752*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53753*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53754*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53755*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53756*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53757*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53758*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53759*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5375a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5375b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5375c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5375d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5375e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5375f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53760*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53761*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53762*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53763*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53764*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53765*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53766*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53767*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53768*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53769*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5376a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5376b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5376c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5376d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5376e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5376f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53770*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53771*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53772*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53773*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53774*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53775*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53776*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53777*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53778*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53779*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5377a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5377b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5377c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5377d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5377e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5377f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53780*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53781*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53782*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53783*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53784*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53785*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53786*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53787*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53788*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53789*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5378a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5378b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5378c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5378d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5378e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5378f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53790*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53791*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53792*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53793*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53794*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53795*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53796*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53797*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53798*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53799*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5379a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5379b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5379c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5379d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5379e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5379f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537a0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537a1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537a2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537a3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537a4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537a5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537a6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537a7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537a8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537a9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537aa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537ab*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537ac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537ad*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537ae*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537af*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537b0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537b1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537b2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537b3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537b4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537b5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537b6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537b7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537b8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537b9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537ba*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537bb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537bc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537bd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537be*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537bf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537c0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537c1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537c2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537c3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537c4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537c5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537c6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537c7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537c8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537c9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537ca*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537cb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537cc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537cd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537ce*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537cf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537d0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537d1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537d2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537d3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537d4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537d5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537d6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537d7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537d8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537d9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537da*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537db*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537dc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537dd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537de*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537df*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537e0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537e1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537e2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537e3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537e4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537e5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537e6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537e7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537e8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537e9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537ea*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537eb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537ec*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537ed*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537ee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537ef*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537f0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537f1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537f2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537f3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537f4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537f5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537f6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537f7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537f8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537f9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537fa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537fb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537fc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537fd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537fe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x537ff*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53800*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53801*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53802*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53803*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53804*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53805*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53806*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53807*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53808*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53809*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5380a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5380b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5380c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5380d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5380e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5380f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53810*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53811*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53812*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53813*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53814*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53815*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53816*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53817*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53818*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53819*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5381a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5381b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5381c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5381d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5381e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5381f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53820*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53821*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53822*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53823*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53824*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53825*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53826*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53827*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53828*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53829*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5382a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5382b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5382c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5382d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5382e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5382f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53830*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53831*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53832*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53833*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53834*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53835*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53836*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53837*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53838*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53839*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5383a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5383b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5383c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5383d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5383e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5383f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53840*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53841*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53842*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53843*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53844*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53845*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53846*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53847*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53848*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53849*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5384a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5384b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5384c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5384d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5384e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5384f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53850*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53851*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53852*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53853*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53854*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53855*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53856*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53857*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53858*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53859*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5385a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5385b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5385c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5385d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5385e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5385f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53860*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53861*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53862*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53863*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53864*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53865*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53866*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53867*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53868*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53869*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5386a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5386b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5386c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5386d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5386e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5386f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53870*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53871*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53872*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53873*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53874*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53875*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53876*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53877*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53878*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53879*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5387a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5387b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5387c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5387d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5387e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5387f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53880*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53881*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53882*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53883*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53884*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53885*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53886*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53887*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53888*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53889*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5388a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5388b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5388c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5388d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5388e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5388f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53890*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53891*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53892*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53893*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53894*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53895*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53896*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53897*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53898*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53899*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5389a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5389b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5389c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5389d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5389e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5389f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538a0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538a1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538a2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538a3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538a4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538a5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538a6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538a7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538a8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538a9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538aa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538ab*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538ac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538ad*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538ae*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538af*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538b0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538b1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538b2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538b3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538b4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538b5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538b6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538b7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538b8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538b9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538ba*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538bb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538bc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538bd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538be*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538bf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538c0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538c1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538c2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538c3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538c4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538c5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538c6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538c7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538c8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538c9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538ca*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538cb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538cc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538cd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538ce*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538cf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538d0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538d1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538d2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538d3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538d4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538d5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538d6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538d7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538d8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538d9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538da*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538db*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538dc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538dd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538de*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538df*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538e0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538e1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538e2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538e3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538e4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538e5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538e6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538e7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538e8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538e9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538ea*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538eb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538ec*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538ed*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538ee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538ef*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538f0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538f1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538f2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538f3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538f4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538f5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538f6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538f7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538f8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538f9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538fa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538fb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538fc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538fd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538fe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x538ff*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53900*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53901*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53902*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53903*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53904*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53905*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53906*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53907*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53908*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53909*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5390a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5390b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5390c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5390d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5390e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5390f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53910*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53911*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53912*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53913*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53914*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53915*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53916*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53917*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53918*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53919*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5391a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5391b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5391c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5391d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5391e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5391f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53920*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53921*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53922*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53923*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53924*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53925*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53926*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53927*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53928*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53929*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5392a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5392b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5392c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5392d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5392e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5392f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53930*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53931*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53932*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53933*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53934*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53935*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53936*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53937*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53938*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53939*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5393a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5393b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5393c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5393d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5393e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5393f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53940*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53941*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53942*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53943*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53944*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53945*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53946*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53947*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53948*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53949*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5394a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5394b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5394c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5394d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5394e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5394f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53950*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53951*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53952*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53953*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53954*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53955*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53956*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53957*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53958*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53959*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5395a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5395b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5395c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5395d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5395e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5395f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53960*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53961*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53962*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53963*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53964*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53965*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53966*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53967*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53968*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53969*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5396a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5396b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5396c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5396d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5396e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5396f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53970*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53971*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53972*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53973*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53974*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53975*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53976*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53977*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53978*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53979*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5397a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5397b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5397c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5397d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5397e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5397f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53980*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53981*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53982*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53983*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53984*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53985*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53986*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53987*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53988*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53989*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5398a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5398b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5398c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5398d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5398e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5398f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53990*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53991*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53992*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53993*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53994*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53995*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53996*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53997*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53998*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53999*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5399a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5399b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5399c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5399d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5399e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5399f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539a0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539a1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539a2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539a3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539a4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539a5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539a6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539a7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539a8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539a9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539aa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539ab*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539ac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539ad*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539ae*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539af*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539b0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539b1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539b2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539b3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539b4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539b5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539b6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539b7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539b8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539b9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539ba*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539bb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539bc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539bd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539be*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539bf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539c0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539c1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539c2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539c3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539c4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539c5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539c6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539c7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539c8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539c9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539ca*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539cb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539cc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539cd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539ce*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539cf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539d0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539d1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539d2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539d3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539d4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539d5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539d6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539d7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539d8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539d9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539da*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539db*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539dc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539dd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539de*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539df*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539e0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539e1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539e2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539e3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539e4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539e5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539e6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539e7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539e8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539e9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539ea*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539eb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539ec*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539ed*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539ee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539ef*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539f0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539f1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539f2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539f3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539f4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539f5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539f6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539f7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539f8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539f9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539fa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539fb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539fc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539fd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539fe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x539ff*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a00*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a01*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a02*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a03*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a04*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a05*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a06*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a07*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a08*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a09*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a0a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a0b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a0c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a0d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a0e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a0f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a10*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a11*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a12*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a13*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a14*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a15*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a16*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a17*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a18*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a19*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a1a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a1b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a1c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a1d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a1e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a1f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a20*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a21*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a22*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a23*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a24*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a25*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a26*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a27*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a28*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a29*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a2a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a2b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a2c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a2d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a2e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a2f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a30*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a31*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a32*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a33*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a34*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a35*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a36*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a37*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a38*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a39*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a3a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a3b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a3c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a3d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a3e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a3f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a40*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a41*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a42*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a43*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a44*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a45*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a46*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a47*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a48*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a49*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a4a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a4b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a4c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a4d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a4e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a4f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a50*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a51*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a52*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a53*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a54*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a55*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a56*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a57*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a58*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a59*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a5a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a5b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a5c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a5d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a5e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a5f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a60*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a61*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a62*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a63*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a64*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a65*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a66*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a67*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a68*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a69*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a6a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a6b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a6c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a6d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a6e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a6f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a70*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a71*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a72*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a73*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a74*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a75*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a76*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a77*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a78*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a79*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a7a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a7b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a7c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a7d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a7e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a7f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a80*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a81*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a82*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a83*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a84*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a85*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a86*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a87*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a88*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a89*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a8a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a8b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a8c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a8d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a8e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a8f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a90*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a91*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a92*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a93*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a94*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a95*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a96*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a97*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a98*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a99*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a9a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a9b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a9c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a9d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a9e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53a9f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aa0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aa1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aa2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aa3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aa4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aa5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aa6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aa7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aa8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aa9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aaa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aab*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aad*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aae*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aaf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ab0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ab1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ab2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ab3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ab4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ab5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ab6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ab7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ab8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ab9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aba*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53abb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53abc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53abd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53abe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53abf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ac0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ac1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ac2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ac3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ac4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ac5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ac6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ac7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ac8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ac9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aca*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53acb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53acc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53acd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ace*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53acf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ad0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ad1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ad2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ad3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ad4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ad5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ad6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ad7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ad8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ad9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ada*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53adb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53adc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53add*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ade*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53adf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ae0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ae1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ae2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ae3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ae4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ae5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ae6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ae7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ae8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ae9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aea*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aeb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aec*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aed*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aef*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53af0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53af1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53af2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53af3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53af4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53af5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53af6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53af7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53af8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53af9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53afa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53afb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53afc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53afd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53afe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53aff*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b00*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b01*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b02*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b03*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b04*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b05*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b06*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b07*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b08*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b09*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b0a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b0b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b0c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b0d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b0e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b0f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b10*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b11*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b12*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b13*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b14*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b15*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b16*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b17*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b18*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b19*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b1a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b1b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b1c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b1d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b1e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b1f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b20*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b21*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b22*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b23*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b24*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b25*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b26*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b27*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b28*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b29*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b2a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b2b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b2c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b2d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b2e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b2f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b30*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b31*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b32*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b33*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b34*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b35*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b36*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b37*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b38*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b39*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b3a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b3b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b3c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b3d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b3e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b3f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b40*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b41*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b42*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b43*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b44*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b45*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b46*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b47*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b48*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b49*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b4a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b4b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b4c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b4d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b4e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b4f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b50*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b51*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b52*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b53*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b54*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b55*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b56*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b57*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b58*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b59*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b5a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b5b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b5c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b5d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b5e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b5f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b60*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b61*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b62*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b63*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b64*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b65*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b66*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b67*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b68*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b69*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b6a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b6b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b6c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b6d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b6e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b6f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b70*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b71*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b72*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b73*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b74*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b75*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b76*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b77*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b78*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b79*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b7a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b7b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b7c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b7d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b7e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b7f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b80*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b81*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b82*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b83*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b84*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b85*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b86*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b87*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b88*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b89*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b8a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b8b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b8c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b8d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b8e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b8f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b90*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b91*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b92*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b93*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b94*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b95*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b96*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b97*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b98*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b99*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b9a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b9b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b9c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b9d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b9e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53b9f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ba0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ba1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ba2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ba3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ba4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ba5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ba6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ba7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ba8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ba9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53baa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bab*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bad*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bae*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53baf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bb0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bb1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bb2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bb3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bb4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bb5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bb6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bb7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bb8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bb9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bba*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bbb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bbc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bbd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bbe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bbf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bc0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bc1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bc2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bc3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bc4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bc5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bc6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bc7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bc8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bc9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bca*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bcb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bcc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bcd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bce*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bcf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bd0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bd1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bd2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bd3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bd4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bd5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bd6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bd7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bd8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bd9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bda*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bdb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bdc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bdd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bde*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bdf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53be0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53be1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53be2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53be3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53be4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53be5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53be6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53be7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53be8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53be9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bea*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53beb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bec*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bed*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bef*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bf0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bf1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bf2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bf3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bf4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bf5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bf6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bf7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bf8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bf9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bfa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bfb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bfc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bfd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bfe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53bff*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c00*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c01*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c02*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c03*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c04*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c05*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c06*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c07*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c08*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c09*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c0a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c0b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c0c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c0d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c0e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c0f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c10*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c11*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c12*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c13*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c14*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c15*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c16*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c17*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c18*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c19*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c1a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c1b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c1c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c1d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c1e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c1f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c20*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c21*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c22*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c23*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c24*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c25*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c26*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c27*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c28*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c29*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c2a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c2b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c2c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c2d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c2e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c2f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c30*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c31*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c32*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c33*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c34*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c35*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c36*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c37*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c38*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c39*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c3a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c3b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c3c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c3d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c3e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c3f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c40*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c41*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c42*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c43*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c44*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c45*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c46*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c47*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c48*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c49*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c4a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c4b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c4c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c4d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c4e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c4f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c50*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c51*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c52*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c53*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c54*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c55*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c56*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c57*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c58*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c59*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c5a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c5b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c5c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c5d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c5e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c5f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c60*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c61*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c62*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c63*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c64*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c65*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c66*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c67*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c68*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c69*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c6a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c6b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c6c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c6d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c6e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c6f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c70*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c71*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c72*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c73*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c74*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c75*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c76*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c77*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c78*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c79*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c7a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c7b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c7c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c7d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c7e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c7f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c80*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c81*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c82*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c83*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c84*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c85*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c86*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c87*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c88*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c89*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c8a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c8b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c8c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c8d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c8e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c8f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c90*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c91*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c92*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c93*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c94*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c95*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c96*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c97*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c98*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c99*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c9a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c9b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c9c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c9d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c9e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53c9f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ca0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ca1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ca2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ca3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ca4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ca5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ca6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ca7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ca8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ca9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53caa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cab*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cad*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cae*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53caf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cb0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cb1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cb2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cb3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cb4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cb5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cb6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cb7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cb8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cb9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cba*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cbb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cbc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cbd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cbe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cbf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cc0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cc1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cc2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cc3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cc4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cc5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cc6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cc7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cc8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cc9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cca*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ccb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ccc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ccd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cce*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ccf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cd0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cd1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cd2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cd3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cd4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cd5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cd6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cd7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cd8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cd9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cda*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cdb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cdc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cdd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cde*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cdf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ce0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ce1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ce2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ce3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ce4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ce5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ce6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ce7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ce8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ce9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cea*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ceb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cec*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ced*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cef*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cf0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cf1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cf2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cf3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cf4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cf5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cf6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cf7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cf8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cf9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cfa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cfb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cfc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cfd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cfe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53cff*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d00*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d01*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d02*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d03*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d04*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d05*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d06*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d07*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d08*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d09*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d0a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d0b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d0c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d0d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d0e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d0f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d10*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d11*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d12*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d13*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d14*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d15*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d16*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d17*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d18*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d19*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d1a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d1b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d1c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d1d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d1e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d1f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d20*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d21*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d22*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d23*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d24*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d25*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d26*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d27*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d28*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d29*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d2a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d2b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d2c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d2d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d2e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d2f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d30*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d31*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d32*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d33*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d34*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d35*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d36*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d37*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d38*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d39*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d3a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d3b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d3c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d3d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d3e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d3f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d40*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d41*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d42*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d43*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d44*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d45*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d46*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d47*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d48*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d49*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d4a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d4b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d4c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d4d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d4e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d4f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d50*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d51*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d52*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d53*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d54*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d55*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d56*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d57*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d58*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d59*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d5a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d5b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d5c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d5d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d5e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d5f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d60*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d61*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d62*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d63*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d64*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d65*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d66*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d67*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d68*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d69*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d6a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d6b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d6c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d6d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d6e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d6f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d70*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d71*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d72*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d73*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d74*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d75*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d76*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d77*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d78*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d79*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d7a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d7b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d7c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d7d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d7e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d7f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d80*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d81*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d82*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d83*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d84*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d85*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d86*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d87*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d88*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d89*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d8a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d8b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d8c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d8d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d8e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d8f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d90*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d91*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d92*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d93*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d94*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d95*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d96*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d97*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d98*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d99*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d9a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d9b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d9c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d9d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d9e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53d9f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53da0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53da1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53da2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53da3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53da4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53da5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53da6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53da7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53da8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53da9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53daa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dab*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dad*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dae*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53daf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53db0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53db1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53db2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53db3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53db4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53db5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53db6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53db7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53db8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53db9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dba*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dbb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dbc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dbd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dbe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dbf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dc0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dc1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dc2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dc3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dc4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dc5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dc6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dc7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dc8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dc9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dca*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dcb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dcc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dcd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dce*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dcf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dd0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dd1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dd2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dd3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dd4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dd5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dd6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dd7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dd8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dd9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dda*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ddb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ddc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ddd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dde*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ddf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53de0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53de1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53de2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53de3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53de4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53de5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53de6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53de7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53de8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53de9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dea*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53deb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dec*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ded*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53def*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53df0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53df1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53df2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53df3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53df4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53df5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53df6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53df7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53df8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53df9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dfa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dfb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dfc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dfd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dfe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53dff*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e00*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e01*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e02*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e03*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e04*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e05*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e06*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e07*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e08*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e09*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e0a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e0b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e0c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e0d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e0e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e0f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e10*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e11*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e12*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e13*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e14*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e15*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e16*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e17*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e18*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e19*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e1a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e1b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e1c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e1d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e1e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e1f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e20*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e21*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e22*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e23*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e24*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e25*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e26*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e27*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e28*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e29*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e2a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e2b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e2c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e2d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e2e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e2f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e30*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e31*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e32*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e33*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e34*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e35*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e36*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e37*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e38*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e39*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e3a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e3b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e3c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e3d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e3e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e3f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e40*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e41*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e42*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e43*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e44*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e45*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e46*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e47*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e48*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e49*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e4a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e4b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e4c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e4d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e4e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e4f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e50*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e51*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e52*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e53*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e54*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e55*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e56*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e57*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e58*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e59*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e5a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e5b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e5c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e5d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e5e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e5f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e60*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e61*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e62*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e63*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e64*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e65*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e66*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e67*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e68*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e69*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e6a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e6b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e6c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e6d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e6e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e6f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e70*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e71*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e72*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e73*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e74*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e75*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e76*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e77*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e78*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e79*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e7a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e7b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e7c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e7d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e7e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e7f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e80*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e81*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e82*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e83*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e84*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e85*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e86*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e87*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e88*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e89*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e8a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e8b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e8c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e8d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e8e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e8f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e90*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e91*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e92*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e93*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e94*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e95*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e96*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e97*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e98*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e99*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e9a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e9b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e9c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e9d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e9e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53e9f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ea0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ea1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ea2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ea3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ea4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ea5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ea6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ea7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ea8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ea9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eaa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eab*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ead*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eae*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eaf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eb0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eb1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eb2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eb3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eb4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eb5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eb6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eb7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eb8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eb9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eba*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ebb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ebc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ebd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ebe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ebf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ec0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ec1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ec2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ec3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ec4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ec5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ec6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ec7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ec8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ec9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eca*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ecb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ecc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ecd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ece*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ecf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ed0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ed1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ed2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ed3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ed4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ed5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ed6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ed7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ed8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ed9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eda*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53edb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53edc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53edd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ede*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53edf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ee0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ee1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ee2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ee3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ee4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ee5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ee6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ee7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ee8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ee9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eea*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eeb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eec*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eed*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eef*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ef0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ef1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ef2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ef3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ef4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ef5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ef6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ef7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ef8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ef9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53efa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53efb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53efc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53efd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53efe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53eff*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f00*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f01*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f02*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f03*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f04*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f05*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f06*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f07*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f08*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f09*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f0a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f0b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f0c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f0d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f0e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f0f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f10*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f11*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f12*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f13*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f14*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f15*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f16*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f17*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f18*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f19*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f1a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f1b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f1c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f1d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f1e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f1f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f20*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f21*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f22*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f23*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f24*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f25*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f26*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f27*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f28*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f29*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f2a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f2b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f2c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f2d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f2e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f2f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f30*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f31*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f32*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f33*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f34*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f35*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f36*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f37*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f38*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f39*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f3f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f40*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f41*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f42*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f43*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f44*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f45*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f46*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f47*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f48*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f49*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f4f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f50*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f51*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f52*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f53*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f54*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f55*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f56*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f57*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f58*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f59*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f5f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f60*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f61*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f62*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f63*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f64*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f65*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f66*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f67*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f68*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f69*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f6f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f70*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f71*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f72*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f73*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f74*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f75*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f76*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f77*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f78*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f79*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f7f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f80*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f81*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f82*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f83*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f84*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f85*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f86*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f87*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f88*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f89*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f8f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f90*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f91*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f92*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f93*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f94*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f95*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f96*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f97*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f98*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f99*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53f9f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fa9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53faa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fab*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fad*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fae*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53faf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fb9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fba*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fbb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fbc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fbd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fbe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fbf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fc9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fca*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fcb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fcc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fcd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fce*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fcf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fd9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fda*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fdb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fdc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fdd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fde*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fdf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fe9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fea*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53feb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fec*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fed*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fef*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ff9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ffa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ffb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ffc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ffd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53ffe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x53fff*4+0x02000000,0x0); + + +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000000 ); + +reg_write( DDR_REG_BASE +0x54000*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54001*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54002*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54003*4+0x02000000,0x854); +reg_write( DDR_REG_BASE +0x54004*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x54005*4+0x02000000,0x0); +//iteration place +//PHY VREF +// 0x40 50% +// 0x60 75% +// 0x56 67% +// 0x20 25% +reg_write( DDR_REG_BASE + 0x54006*4+0x02000000,0x60); +reg_write( DDR_REG_BASE +0x54007*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54008*4+0x02000000,0x131f); +reg_write( DDR_REG_BASE +0x54009*4+0x02000000,0xc8); +reg_write( DDR_REG_BASE +0x5400a*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x5400b*4+0x02000000,0x0); + +//swap dbyte +reg_write( DDR_REG_BASE + 0x5400d*4+0x02000000,0x8083); +reg_write( DDR_REG_BASE + 0x5400c*4+0x02000000,0x8182); +reg_write( DDR_REG_BASE +0x5400e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5400f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54010*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54011*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x54012*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54013*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54014*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54015*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54016*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54017*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54018*4+0x02000000,0xc300); +// iteration place +// DRAM DSEL Output Impedance -higher 8 bit +// MR3_A0/A1/B0/B1 + //0x2:(default: output driver impedance 40 pulldown&pullup) + //0x1:(34.3 pulldown&pullup ) + //0x3:(48) + //0x4:(reserve for 60) optional + //0x6:(reserve for 80) optional + //0x9:(34.3 pulldown & 40 pull up + //0xa:(40 pulldown & 48 pull up + //0xb:(34.3 pulldown & 48 pull up +reg_write( DDR_REG_BASE +0x54019*4+0x02000000,0x41e); +reg_write( DDR_REG_BASE +0x5401d*4+0x02000000,0x41e); +reg_write( DDR_REG_BASE +0x5402c*4+0x02000000,0x41e); +reg_write( DDR_REG_BASE +0x54030*4+0x02000000,0x41e); + +//iteration place +//DRAM DQ ODT -higher 8 bit + //0x0:(default: DQ odt disable) + //0x5:(ODT:60) + //0x6:(ODT:120) + //0x7:(ODT:240) +reg_write( DDR_REG_BASE +0x5401a*4+0x02000000,0x600); +reg_write( DDR_REG_BASE +0x5401e*4+0x02000000,0x600); +reg_write( DDR_REG_BASE +0x5402d*4+0x02000000,0x600); +reg_write( DDR_REG_BASE +0x54031*4+0x02000000,0x600); + + +reg_write( DDR_REG_BASE +0x5401b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5401c*4+0x02000000,0xc300); + + + + +reg_write( DDR_REG_BASE +0x5401f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54020*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54021*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54022*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54023*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54024*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54025*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54026*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54027*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54028*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54029*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5402a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5402b*4+0x02000000,0xc300); + + +reg_write( DDR_REG_BASE +0x5402e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5402f*4+0x02000000,0xc300); + + +reg_write( DDR_REG_BASE +0x54032*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54033*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54034*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54035*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54036*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54037*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54038*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54039*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5403a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5403b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5403c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5403d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5403e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5403f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54040*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54041*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54042*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54043*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54044*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54045*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54046*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54047*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54048*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54049*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5404f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54050*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54051*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54052*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54053*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54054*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54055*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54056*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54057*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54058*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54059*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5405f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54060*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54061*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54062*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54063*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54064*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54065*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54066*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54067*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54068*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54069*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5406f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54070*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54071*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54072*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54073*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54074*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54075*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54076*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54077*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54078*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54079*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5407f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54080*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54081*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54082*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54083*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54084*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54085*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54086*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54087*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54088*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54089*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5408f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54090*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54091*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54092*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54093*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54094*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54095*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54096*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54097*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54098*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54099*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5409f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540a9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540aa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ab*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ad*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ae*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540af*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540b9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ba*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540bb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540bc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540bd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540be*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540bf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540c9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ca*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540cb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540cc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540cd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ce*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540cf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540d9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540da*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540db*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540dc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540dd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540de*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540df*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540e9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ea*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540eb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ec*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ed*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ef*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540f9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540fa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540fb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540fc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540fd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540fe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x540ff*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54100*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54101*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54102*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54103*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54104*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54105*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54106*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54107*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54108*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54109*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5410f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54110*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54111*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54112*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54113*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54114*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54115*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54116*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54117*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54118*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54119*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5411f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54120*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54121*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54122*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54123*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54124*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54125*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54126*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54127*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54128*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54129*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5412f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54130*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54131*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54132*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54133*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54134*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54135*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54136*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54137*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54138*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54139*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5413f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54140*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54141*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54142*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54143*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54144*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54145*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54146*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54147*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54148*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54149*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5414f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54150*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54151*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54152*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54153*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54154*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54155*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54156*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54157*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54158*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54159*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5415f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54160*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54161*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54162*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54163*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54164*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54165*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54166*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54167*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54168*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54169*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5416f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54170*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54171*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54172*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54173*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54174*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54175*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54176*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54177*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54178*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54179*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5417f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54180*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54181*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54182*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54183*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54184*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54185*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54186*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54187*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54188*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54189*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5418f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54190*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54191*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54192*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54193*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54194*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54195*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54196*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54197*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54198*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54199*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5419f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541a9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541aa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ab*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ac*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ad*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ae*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541af*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541b9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ba*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541bb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541bc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541bd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541be*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541bf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541c9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ca*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541cb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541cc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541cd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ce*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541cf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541d9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541da*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541db*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541dc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541dd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541de*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541df*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541e9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ea*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541eb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ec*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ed*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ee*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ef*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f1*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f3*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541f9*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541fa*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541fb*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541fc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541fd*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541fe*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x541ff*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54200*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54201*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54202*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54203*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54204*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54205*4+0x02000000,0xff); +reg_write( DDR_REG_BASE +0x54206*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54207*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54208*4+0x02000000,0x14a); +reg_write( DDR_REG_BASE +0x54209*4+0x02000000,0x181); +reg_write( DDR_REG_BASE +0x5420a*4+0x02000000,0x118); +reg_write( DDR_REG_BASE +0x5420b*4+0x02000000,0x118); +reg_write( DDR_REG_BASE +0x5420c*4+0x02000000,0x16f); +reg_write( DDR_REG_BASE +0x5420d*4+0x02000000,0x16f); +reg_write( DDR_REG_BASE +0x5420e*4+0x02000000,0x159); +reg_write( DDR_REG_BASE +0x5420f*4+0x02000000,0x181); +reg_write( DDR_REG_BASE +0x54210*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x54211*4+0x02000000,0x120); +reg_write( DDR_REG_BASE +0x54212*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54213*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54214*4+0x02000000,0x701c); +reg_write( DDR_REG_BASE +0x54215*4+0x02000000,0x61a8); +reg_write( DDR_REG_BASE +0x54216*4+0x02000000,0x35ac); +reg_write( DDR_REG_BASE +0x54217*4+0x02000000,0x35ac); +reg_write( DDR_REG_BASE +0x54218*4+0x02000000,0x125c); +reg_write( DDR_REG_BASE +0x54219*4+0x02000000,0x125c); +reg_write( DDR_REG_BASE +0x5421a*4+0x02000000,0xc738); +reg_write( DDR_REG_BASE +0x5421b*4+0x02000000,0xb0f4); +reg_write( DDR_REG_BASE +0x5421c*4+0x02000000,0x6590); +reg_write( DDR_REG_BASE +0x5421d*4+0x02000000,0x6590); +reg_write( DDR_REG_BASE +0x5421e*4+0x02000000,0x9f38); +reg_write( DDR_REG_BASE +0x5421f*4+0x02000000,0x58); +reg_write( DDR_REG_BASE +0x54220*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54221*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54222*4+0x02000000,0xf01f); +reg_write( DDR_REG_BASE +0x54223*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54224*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54225*4+0x02000000,0xffb4); +reg_write( DDR_REG_BASE +0x54226*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54227*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54228*4+0x02000000,0xf0b4); +reg_write( DDR_REG_BASE +0x54229*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5422a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5422b*4+0x02000000,0xf4b4); +reg_write( DDR_REG_BASE +0x5422c*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5422d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5422e*4+0x02000000,0xf0b9); +reg_write( DDR_REG_BASE +0x5422f*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54230*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54231*4+0x02000000,0xf0ba); +reg_write( DDR_REG_BASE +0x54232*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54233*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54234*4+0x02000000,0xf0bb); +reg_write( DDR_REG_BASE +0x54235*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54236*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54237*4+0x02000000,0xf001); +reg_write( DDR_REG_BASE +0x54238*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54239*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5423a*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x5423b*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5423c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5423d*4+0x02000000,0xf0f9); +reg_write( DDR_REG_BASE +0x5423e*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5423f*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x54240*4+0x02000000,0xf0fa); +reg_write( DDR_REG_BASE +0x54241*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x54242*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54243*4+0x02000000,0xf0fb); +reg_write( DDR_REG_BASE +0x54244*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x54245*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x54246*4+0x02000000,0xf060); +reg_write( DDR_REG_BASE +0x54247*4+0x02000000,0x7); +reg_write( DDR_REG_BASE +0x54248*4+0x02000000,0x8); +reg_write( DDR_REG_BASE +0x54249*4+0x02000000,0xf065); +reg_write( DDR_REG_BASE +0x5424a*4+0x02000000,0x7); +reg_write( DDR_REG_BASE +0x5424b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5424c*4+0x02000000,0xff62); +reg_write( DDR_REG_BASE +0x5424d*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5424e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5424f*4+0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x54250*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54251*4+0x02000000,0x220); +reg_write( DDR_REG_BASE +0x54252*4+0x02000000,0xf01f); +reg_write( DDR_REG_BASE +0x54253*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54254*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54255*4+0x02000000,0xffb4); +reg_write( DDR_REG_BASE +0x54256*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54257*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54258*4+0x02000000,0xf0b4); +reg_write( DDR_REG_BASE +0x54259*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5425a*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5425b*4+0x02000000,0xf4b4); +reg_write( DDR_REG_BASE +0x5425c*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5425d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5425e*4+0x02000000,0xf0b9); +reg_write( DDR_REG_BASE +0x5425f*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54260*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54261*4+0x02000000,0xf0ba); +reg_write( DDR_REG_BASE +0x54262*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54263*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54264*4+0x02000000,0xf0bb); +reg_write( DDR_REG_BASE +0x54265*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54266*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54267*4+0x02000000,0xf001); +reg_write( DDR_REG_BASE +0x54268*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54269*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5426a*4+0x02000000,0xf0f9); +reg_write( DDR_REG_BASE +0x5426b*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5426c*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x5426d*4+0x02000000,0xf0fa); +reg_write( DDR_REG_BASE +0x5426e*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x5426f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54270*4+0x02000000,0xf0fb); +reg_write( DDR_REG_BASE +0x54271*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x54272*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x54273*4+0x02000000,0xf060); +reg_write( DDR_REG_BASE +0x54274*4+0x02000000,0x7); +reg_write( DDR_REG_BASE +0x54275*4+0x02000000,0x5); +reg_write( DDR_REG_BASE +0x54276*4+0x02000000,0xf065); +reg_write( DDR_REG_BASE +0x54277*4+0x02000000,0x7); +reg_write( DDR_REG_BASE +0x54278*4+0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x54279*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x5427a*4+0x02000000,0x7); +reg_write( DDR_REG_BASE +0x5427b*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x5427c*4+0x02000000,0xff62); +reg_write( DDR_REG_BASE +0x5427d*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5427e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5427f*4+0x02000000,0xf862); +reg_write( DDR_REG_BASE +0x54280*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54281*4+0x02000000,0xfd); +reg_write( DDR_REG_BASE +0x54282*4+0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x54283*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54284*4+0x02000000,0x220); +reg_write( DDR_REG_BASE +0x54285*4+0x02000000,0xf01f); +reg_write( DDR_REG_BASE +0x54286*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54287*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54288*4+0x02000000,0xffb4); +reg_write( DDR_REG_BASE +0x54289*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5428a*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5428b*4+0x02000000,0xf0b4); +reg_write( DDR_REG_BASE +0x5428c*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5428d*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5428e*4+0x02000000,0xf4b4); +reg_write( DDR_REG_BASE +0x5428f*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54290*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54291*4+0x02000000,0xf0b9); +reg_write( DDR_REG_BASE +0x54292*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54293*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54294*4+0x02000000,0xf0ba); +reg_write( DDR_REG_BASE +0x54295*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54296*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54297*4+0x02000000,0xf0bb); +reg_write( DDR_REG_BASE +0x54298*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54299*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5429a*4+0x02000000,0xf001); +reg_write( DDR_REG_BASE +0x5429b*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5429c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5429d*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x5429e*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5429f*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542a0*4+0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x542a1*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542a2*4+0x02000000,0xf000); +reg_write( DDR_REG_BASE +0x542a3*4+0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x542a4*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542a5*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542a6*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x542a7*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542a8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542a9*4+0x02000000,0xf0f9); +reg_write( DDR_REG_BASE +0x542aa*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x542ab*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x542ac*4+0x02000000,0xf0fa); +reg_write( DDR_REG_BASE +0x542ad*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x542ae*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542af*4+0x02000000,0xf0fb); +reg_write( DDR_REG_BASE +0x542b0*4+0x02000000,0x4); +reg_write( DDR_REG_BASE +0x542b1*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x542b2*4+0x02000000,0xff62); +reg_write( DDR_REG_BASE +0x542b3*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542b4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542b5*4+0x02000000,0xf062); +reg_write( DDR_REG_BASE +0x542b6*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542b7*4+0x02000000,0xf); +reg_write( DDR_REG_BASE +0x542b8*4+0x02000000,0xf462); +reg_write( DDR_REG_BASE +0x542b9*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542ba*4+0x02000000,0xf0); +reg_write( DDR_REG_BASE +0x542bb*4+0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x542bc*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542bd*4+0x02000000,0x204); +reg_write( DDR_REG_BASE +0x542be*4+0x02000000,0xf01f); +reg_write( DDR_REG_BASE +0x542bf*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542c0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542c1*4+0x02000000,0xf03b); +reg_write( DDR_REG_BASE +0x542c2*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x542c3*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542c4*4+0x02000000,0xffb2); +reg_write( DDR_REG_BASE +0x542c5*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542c6*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542c7*4+0x02000000,0xf0b2); +reg_write( DDR_REG_BASE +0x542c8*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542c9*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542ca*4+0x02000000,0xffb4); +reg_write( DDR_REG_BASE +0x542cb*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542cc*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542cd*4+0x02000000,0xf0b4); +reg_write( DDR_REG_BASE +0x542ce*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542cf*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542d0*4+0x02000000,0xf0b9); +reg_write( DDR_REG_BASE +0x542d1*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542d2*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542d3*4+0x02000000,0xf0ba); +reg_write( DDR_REG_BASE +0x542d4*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542d5*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542d6*4+0x02000000,0xf0bb); +reg_write( DDR_REG_BASE +0x542d7*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542d8*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542d9*4+0x02000000,0xf001); +reg_write( DDR_REG_BASE +0x542da*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542db*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542dc*4+0x02000000,0xf060); +reg_write( DDR_REG_BASE +0x542dd*4+0x02000000,0x7); +reg_write( DDR_REG_BASE +0x542de*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542df*4+0x02000000,0xf065); +reg_write( DDR_REG_BASE +0x542e0*4+0x02000000,0x7); +reg_write( DDR_REG_BASE +0x542e1*4+0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x542e2*4+0x02000000,0xff26); +reg_write( DDR_REG_BASE +0x542e3*4+0x02000000,0x7); +reg_write( DDR_REG_BASE +0x542e4*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542e5*4+0x02000000,0xff27); +reg_write( DDR_REG_BASE +0x542e6*4+0x02000000,0x7); +reg_write( DDR_REG_BASE +0x542e7*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542e8*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x542e9*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542ea*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x542eb*4+0x02000000,0xff32); +reg_write( DDR_REG_BASE +0x542ec*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542ed*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x542ee*4+0x02000000,0xff62); +reg_write( DDR_REG_BASE +0x542ef*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542f0*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542f1*4+0x02000000,0xf062); +reg_write( DDR_REG_BASE +0x542f2*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542f3*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542f4*4+0x02000000,0xf462); +reg_write( DDR_REG_BASE +0x542f5*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542f6*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542f7*4+0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x542f8*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542f9*4+0x02000000,0x208); +reg_write( DDR_REG_BASE +0x542fa*4+0x02000000,0xf01f); +reg_write( DDR_REG_BASE +0x542fb*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542fc*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x542fd*4+0x02000000,0xffb2); +reg_write( DDR_REG_BASE +0x542fe*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x542ff*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54300*4+0x02000000,0xf0b2); +reg_write( DDR_REG_BASE +0x54301*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54302*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54303*4+0x02000000,0xf4b2); +reg_write( DDR_REG_BASE +0x54304*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54305*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54306*4+0x02000000,0xffb4); +reg_write( DDR_REG_BASE +0x54307*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54308*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54309*4+0x02000000,0xf0b4); +reg_write( DDR_REG_BASE +0x5430a*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5430b*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5430c*4+0x02000000,0xf4b4); +reg_write( DDR_REG_BASE +0x5430d*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5430e*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5430f*4+0x02000000,0xf0b9); +reg_write( DDR_REG_BASE +0x54310*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54311*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54312*4+0x02000000,0xf0ba); +reg_write( DDR_REG_BASE +0x54313*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54314*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54315*4+0x02000000,0xf0bb); +reg_write( DDR_REG_BASE +0x54316*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54317*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54318*4+0x02000000,0xf011); +reg_write( DDR_REG_BASE +0x54319*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5431a*4+0x02000000,0x101); +reg_write( DDR_REG_BASE +0x5431b*4+0x02000000,0xf012); +reg_write( DDR_REG_BASE +0x5431c*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5431d*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5431e*4+0x02000000,0xf013); +reg_write( DDR_REG_BASE +0x5431f*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54320*4+0x02000000,0x2); +reg_write( DDR_REG_BASE +0x54321*4+0x02000000,0xf018); +reg_write( DDR_REG_BASE +0x54322*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54323*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54324*4+0x02000000,0xf060); +reg_write( DDR_REG_BASE +0x54325*4+0x02000000,0x7); +reg_write( DDR_REG_BASE +0x54326*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54327*4+0x02000000,0xf065); +reg_write( DDR_REG_BASE +0x54328*4+0x02000000,0x7); +reg_write( DDR_REG_BASE +0x54329*4+0x02000000,0x1ff); +reg_write( DDR_REG_BASE +0x5432a*4+0x02000000,0xff26); +reg_write( DDR_REG_BASE +0x5432b*4+0x02000000,0x7); +reg_write( DDR_REG_BASE +0x5432c*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x5432d*4+0x02000000,0xff27); +reg_write( DDR_REG_BASE +0x5432e*4+0x02000000,0x7); +reg_write( DDR_REG_BASE +0x5432f*4+0x02000000,0xffff); +reg_write( DDR_REG_BASE +0x54330*4+0x02000000,0xff62); +reg_write( DDR_REG_BASE +0x54331*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54332*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54333*4+0x02000000,0xf062); +reg_write( DDR_REG_BASE +0x54334*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54335*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54336*4+0x02000000,0xf462); +reg_write( DDR_REG_BASE +0x54337*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x54338*4+0x02000000,0x10); +reg_write( DDR_REG_BASE +0x54339*4+0x02000000,0xff32); +reg_write( DDR_REG_BASE +0x5433a*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5433b*4+0x02000000,0x800); +reg_write( DDR_REG_BASE +0x5433c*4+0x02000000,0xf002); +reg_write( DDR_REG_BASE +0x5433d*4+0x02000000,0x1); +reg_write( DDR_REG_BASE +0x5433e*4+0x02000000,0x210); +reg_write( DDR_REG_BASE +0x5433f*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54340*4+0x02000000,0x201); +reg_write( DDR_REG_BASE +0x54341*4+0x02000000,0xb03); +reg_write( DDR_REG_BASE +0x54342*4+0x02000000,0x1110); +reg_write( DDR_REG_BASE +0x54343*4+0x02000000,0x2a29); +reg_write( DDR_REG_BASE +0x54344*4+0x02000000,0x6e30); +reg_write( DDR_REG_BASE +0x54345*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x54346*4+0x02000000,0x100); +reg_write( DDR_REG_BASE +0x54347*4+0x02000000,0xfd00); +reg_write( DDR_REG_BASE +0x54348*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x54349*4+0x02000000,0xf00); +reg_write( DDR_REG_BASE +0x5434a*4+0x02000000,0x6000); +reg_write( DDR_REG_BASE +0x5434b*4+0x02000000,0x700); +reg_write( DDR_REG_BASE +0x5434c*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x5434d*4+0x02000000,0xe800); +reg_write( DDR_REG_BASE +0x5434e*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x5434f*4+0x02000000,0xff00); +reg_write( DDR_REG_BASE +0x54350*4+0x02000000,0xfc00); +reg_write( DDR_REG_BASE +0x54351*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x54352*4+0x02000000,0x400); +reg_write( DDR_REG_BASE +0x54353*4+0x02000000,0x3a04); +reg_write( DDR_REG_BASE +0x54354*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x54355*4+0x02000000,0x200); +reg_write( DDR_REG_BASE +0x54356*4+0x02000000,0x1100); +reg_write( DDR_REG_BASE +0x54357*4+0x02000000,0x700); +reg_write( DDR_REG_BASE +0x54358*4+0x02000000,0x0); +reg_write( DDR_REG_BASE +0x54359*4+0x02000000,0x0); + + +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000d0099*4 +0x02000000 , 0x00000009 ); +reg_write( DDR_REG_BASE + 0x000d0099*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000d0099*4 +0x02000000 , 0x00000000 ); + + + +while((train_data&0x7) !=0x07){ + + reg_read ( DDR_REG_BASE + 0x000d0004*4 +0x02000000 , data ); + while((data&0x1) !=0x0){ + reg_read ( DDR_REG_BASE + 0x000d0004*4 +0x02000000 , data ); + } + + + + reg_read ( DDR_REG_BASE + 0x000d0032*4 +0x02000000 , train_data ); + switch(train_data) + { + case 0x00000000: printf("%08X: PMU Major Msg: End of initialization \n",train_data);break; + case 0x00000001: printf("%08X: PMU Major Msg: End of fine write leveling \n",train_data);break; + case 0x00000002: printf("%08X: PMU Major Msg: End of read enable training \n",train_data);break; + case 0x00000003: printf("%08X: PMU Major Msg: End of read delay center optimization \n",train_data);break; + case 0x00000004: printf("%08X: PMU Major Msg: End of write delay center optimization \n",train_data);break; + case 0x00000005: printf("%08X: PMU Major Msg: End of 2D read delay/voltage center optimization \n",train_data);break; + case 0x00000006: printf("%08X: PMU Major Msg: End of 2D write delay /voltage center optimization \n",train_data);break; + case 0x00000007: printf("%08X: PMU Major Msg: Firmware run has completed \n",train_data);break; + case 0x00000008: printf("%08X: PMU Major Msg: Enter streaming message mode \n",train_data);break; + case 0x00000009: printf("%08X: PMU Major Msg: End of max read latency training \n",train_data);break; + case 0x0000000a: printf("%08X: PMU Major Msg: End of read dq deskew training \n",train_data);break; + case 0x0000000b: printf("%08X: PMU Major Msg: End of LCDL offset calibration \n",train_data);break; + case 0x0000000c: printf("%08X: PMU Major Msg: End of LRDIMM Specific training (DWL, MREP, MRD and MWD) \n",train_data);break; + case 0x0000000d: printf("%08X: PMU Major Msg: End of CA training \n",train_data);break; + case 0x000000fd: printf("%08X: PMU Major Msg: End of MPR read delay center optimization \n",train_data);break; + case 0x000000fe: printf("%08X: PMU Major Msg: End of Write leveling coarse delay \n",train_data);break; + case 0x000000ff: while(1) {printf("%08X: PMU Major Msg: FATAL ERROR. \n",train_data); mdelay(100);} break; + default: printf("%08X: PMU Major Msg: Un-recognized message... ! \n",train_data);break; + } + + reg_write( DDR_REG_BASE + 0x000d0031*4 +0x02000000 , 0x00000000 ); + reg_read ( DDR_REG_BASE + 0x000d0004*4 +0x02000000 , data ); + while((data&0x1) ==0x0){ + reg_read ( DDR_REG_BASE + 0x000d0004*4 +0x02000000 , data ); + } + reg_write( DDR_REG_BASE + 0x000d0031*4 +0x02000000 , 0x00000001 ); + +} + +train_data=0; + + + +reg_write( DDR_REG_BASE + 0x000d0099*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000000 ); + + + + +reg_write( DDR_REG_BASE + 0x00090000*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x00090001*4 +0x02000000 , 0x00000400 ); +reg_write( DDR_REG_BASE + 0x00090002*4 +0x02000000 , 0x0000010e ); +reg_write( DDR_REG_BASE + 0x00090003*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090004*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090005*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090029*4 +0x02000000 , 0x0000000b ); +reg_write( DDR_REG_BASE + 0x0009002a*4 +0x02000000 , 0x00000480 ); +reg_write( DDR_REG_BASE + 0x0009002b*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009002c*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x0009002d*4 +0x02000000 , 0x00000448 ); +reg_write( DDR_REG_BASE + 0x0009002e*4 +0x02000000 , 0x00000139 ); +reg_write( DDR_REG_BASE + 0x0009002f*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090030*4 +0x02000000 , 0x00000478 ); +reg_write( DDR_REG_BASE + 0x00090031*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090032*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090033*4 +0x02000000 , 0x000000e8 ); +reg_write( DDR_REG_BASE + 0x00090034*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090035*4 +0x02000000 , 0x00000002 ); +reg_write( DDR_REG_BASE + 0x00090036*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x00090037*4 +0x02000000 , 0x00000139 ); +reg_write( DDR_REG_BASE + 0x00090038*4 +0x02000000 , 0x0000000b ); +reg_write( DDR_REG_BASE + 0x00090039*4 +0x02000000 , 0x000007c0 ); +reg_write( DDR_REG_BASE + 0x0009003a*4 +0x02000000 , 0x00000139 ); +reg_write( DDR_REG_BASE + 0x0009003b*4 +0x02000000 , 0x00000044 ); +reg_write( DDR_REG_BASE + 0x0009003c*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x0009003d*4 +0x02000000 , 0x00000159 ); +reg_write( DDR_REG_BASE + 0x0009003e*4 +0x02000000 , 0x0000014f ); +reg_write( DDR_REG_BASE + 0x0009003f*4 +0x02000000 , 0x00000630 ); +reg_write( DDR_REG_BASE + 0x00090040*4 +0x02000000 , 0x00000159 ); +reg_write( DDR_REG_BASE + 0x00090041*4 +0x02000000 , 0x00000047 ); +reg_write( DDR_REG_BASE + 0x00090042*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090043*4 +0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x00090044*4 +0x02000000 , 0x0000004f ); +reg_write( DDR_REG_BASE + 0x00090045*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090046*4 +0x02000000 , 0x00000179 ); +reg_write( DDR_REG_BASE + 0x00090047*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090048*4 +0x02000000 , 0x000000e0 ); +reg_write( DDR_REG_BASE + 0x00090049*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009004a*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009004b*4 +0x02000000 , 0x000007c8 ); +reg_write( DDR_REG_BASE + 0x0009004c*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009004d*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009004e*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x0009004f*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090050*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090051*4 +0x02000000 , 0x0000045a ); +reg_write( DDR_REG_BASE + 0x00090052*4 +0x02000000 , 0x00000009 ); +reg_write( DDR_REG_BASE + 0x00090053*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090054*4 +0x02000000 , 0x00000448 ); +reg_write( DDR_REG_BASE + 0x00090055*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090056*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x00090057*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090058*4 +0x02000000 , 0x00000179 ); +reg_write( DDR_REG_BASE + 0x00090059*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x0009005a*4 +0x02000000 , 0x00000618 ); +reg_write( DDR_REG_BASE + 0x0009005b*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009005c*4 +0x02000000 , 0x000040c0 ); +reg_write( DDR_REG_BASE + 0x0009005d*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x0009005e*4 +0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x0009005f*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090060*4 +0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00090061*4 +0x02000000 , 0x00000048 ); +reg_write( DDR_REG_BASE + 0x00090062*4 +0x02000000 , 0x00004040 ); +reg_write( DDR_REG_BASE + 0x00090063*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090064*4 +0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x00090065*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090066*4 +0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00090067*4 +0x02000000 , 0x00000048 ); +reg_write( DDR_REG_BASE + 0x00090068*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x00090069*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x0009006a*4 +0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x0009006b*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x0009006c*4 +0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x0009006d*4 +0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x0009006e*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009006f*4 +0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00090070*4 +0x02000000 , 0x00000078 ); +reg_write( DDR_REG_BASE + 0x00090071*4 +0x02000000 , 0x00000549 ); +reg_write( DDR_REG_BASE + 0x00090072*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090073*4 +0x02000000 , 0x00000159 ); +reg_write( DDR_REG_BASE + 0x00090074*4 +0x02000000 , 0x00000d49 ); +reg_write( DDR_REG_BASE + 0x00090075*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090076*4 +0x02000000 , 0x00000159 ); +reg_write( DDR_REG_BASE + 0x00090077*4 +0x02000000 , 0x0000094a ); +reg_write( DDR_REG_BASE + 0x00090078*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090079*4 +0x02000000 , 0x00000159 ); +reg_write( DDR_REG_BASE + 0x0009007a*4 +0x02000000 , 0x00000441 ); +reg_write( DDR_REG_BASE + 0x0009007b*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x0009007c*4 +0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x0009007d*4 +0x02000000 , 0x00000042 ); +reg_write( DDR_REG_BASE + 0x0009007e*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x0009007f*4 +0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x00090080*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00090081*4 +0x02000000 , 0x00000633 ); +reg_write( DDR_REG_BASE + 0x00090082*4 +0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x00090083*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090084*4 +0x02000000 , 0x000000e0 ); +reg_write( DDR_REG_BASE + 0x00090085*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090086*4 +0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x00090087*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x00090088*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090089*4 +0x02000000 , 0x00000009 ); +reg_write( DDR_REG_BASE + 0x0009008a*4 +0x02000000 , 0x000003c0 ); +reg_write( DDR_REG_BASE + 0x0009008b*4 +0x02000000 , 0x00000149 ); +reg_write( DDR_REG_BASE + 0x0009008c*4 +0x02000000 , 0x00000009 ); +reg_write( DDR_REG_BASE + 0x0009008d*4 +0x02000000 , 0x000003c0 ); +reg_write( DDR_REG_BASE + 0x0009008e*4 +0x02000000 , 0x00000159 ); +reg_write( DDR_REG_BASE + 0x0009008f*4 +0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x00090090*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x00090091*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090092*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090093*4 +0x02000000 , 0x000003c0 ); +reg_write( DDR_REG_BASE + 0x00090094*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090095*4 +0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x00090096*4 +0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x00090097*4 +0x02000000 , 0x00000048 ); +reg_write( DDR_REG_BASE + 0x00090098*4 +0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x00090099*4 +0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x0009009a*4 +0x02000000 , 0x00000058 ); +reg_write( DDR_REG_BASE + 0x0009009b*4 +0x02000000 , 0x0000000b ); +reg_write( DDR_REG_BASE + 0x0009009c*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x0009009d*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009009e*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x0009009f*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000900a0*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x000900a1*4 +0x02000000 , 0x00000005 ); +reg_write( DDR_REG_BASE + 0x000900a2*4 +0x02000000 , 0x000007c0 ); +reg_write( DDR_REG_BASE + 0x000900a3*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00040000*4 +0x02000000 , 0x000008ec ); +reg_write( DDR_REG_BASE + 0x00040020*4 +0x02000000 , 0x00000800 ); +reg_write( DDR_REG_BASE + 0x00040040*4 +0x02000000 , 0x00000038 ); +reg_write( DDR_REG_BASE + 0x00040060*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040001*4 +0x02000000 , 0x0000070a ); +reg_write( DDR_REG_BASE + 0x00040021*4 +0x02000000 , 0x00000015 ); +reg_write( DDR_REG_BASE + 0x00040041*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040061*4 +0x02000000 , 0x00002003 ); +reg_write( DDR_REG_BASE + 0x00040002*4 +0x02000000 , 0x00000764 ); +reg_write( DDR_REG_BASE + 0x00040022*4 +0x02000000 , 0x00000015 ); +reg_write( DDR_REG_BASE + 0x00040042*4 +0x02000000 , 0x00000a56 ); +reg_write( DDR_REG_BASE + 0x00040062*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040003*4 +0x02000000 , 0x0000070a ); +reg_write( DDR_REG_BASE + 0x00040023*4 +0x02000000 , 0x0000001a ); +reg_write( DDR_REG_BASE + 0x00040043*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040063*4 +0x02000000 , 0x00002003 ); +reg_write( DDR_REG_BASE + 0x00040004*4 +0x02000000 , 0x00004764 ); +reg_write( DDR_REG_BASE + 0x00040024*4 +0x02000000 , 0x0000001a ); +reg_write( DDR_REG_BASE + 0x00040044*4 +0x02000000 , 0x00000a56 ); +reg_write( DDR_REG_BASE + 0x00040064*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040005*4 +0x02000000 , 0x00000f05 ); +reg_write( DDR_REG_BASE + 0x00040025*4 +0x02000000 , 0x00000c05 ); +reg_write( DDR_REG_BASE + 0x00040045*4 +0x02000000 , 0x00002800 ); +reg_write( DDR_REG_BASE + 0x00040065*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040006*4 +0x02000000 , 0x00000728 ); +reg_write( DDR_REG_BASE + 0x00040026*4 +0x02000000 , 0x00000005 ); +reg_write( DDR_REG_BASE + 0x00040046*4 +0x02000000 , 0x00002800 ); +reg_write( DDR_REG_BASE + 0x00040066*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040007*4 +0x02000000 , 0x00004028 ); +reg_write( DDR_REG_BASE + 0x00040027*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040047*4 +0x02000000 , 0x00000038 ); +reg_write( DDR_REG_BASE + 0x00040067*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040008*4 +0x02000000 , 0x00000f05 ); +reg_write( DDR_REG_BASE + 0x00040028*4 +0x02000000 , 0x00000c0a ); +reg_write( DDR_REG_BASE + 0x00040048*4 +0x02000000 , 0x00002800 ); +reg_write( DDR_REG_BASE + 0x00040068*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00040009*4 +0x02000000 , 0x00000728 ); +reg_write( DDR_REG_BASE + 0x00040029*4 +0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x00040049*4 +0x02000000 , 0x00002800 ); +reg_write( DDR_REG_BASE + 0x00040069*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004000a*4 +0x02000000 , 0x00004028 ); +reg_write( DDR_REG_BASE + 0x0004002a*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004004a*4 +0x02000000 , 0x00000038 ); +reg_write( DDR_REG_BASE + 0x0004006a*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004000b*4 +0x02000000 , 0x00000ee0 ); +reg_write( DDR_REG_BASE + 0x0004002b*4 +0x02000000 , 0x00000c0f ); +reg_write( DDR_REG_BASE + 0x0004004b*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004006b*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0004000c*4 +0x02000000 , 0x00005620 ); +reg_write( DDR_REG_BASE + 0x0004002c*4 +0x02000000 , 0x00000003 ); +reg_write( DDR_REG_BASE + 0x0004004c*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x0004006c*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900a4*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900a5*4 +0x02000000 , 0x00000790 ); +reg_write( DDR_REG_BASE + 0x000900a6*4 +0x02000000 , 0x0000010a ); +reg_write( DDR_REG_BASE + 0x000900a7*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900a8*4 +0x02000000 , 0x000007aa ); +reg_write( DDR_REG_BASE + 0x000900a9*4 +0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x000900aa*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000900ab*4 +0x02000000 , 0x000007b2 ); +reg_write( DDR_REG_BASE + 0x000900ac*4 +0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x000900ad*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900ae*4 +0x02000000 , 0x000007c8 ); +reg_write( DDR_REG_BASE + 0x000900af*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x000900b0*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000900b1*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000900b2*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x000900b3*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000900b4*4 +0x02000000 , 0x000002a8 ); +reg_write( DDR_REG_BASE + 0x000900b5*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x000900b6*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900b7*4 +0x02000000 , 0x00000370 ); +reg_write( DDR_REG_BASE + 0x000900b8*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x000900b9*4 +0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x000900ba*4 +0x02000000 , 0x000003c8 ); +reg_write( DDR_REG_BASE + 0x000900bb*4 +0x02000000 , 0x000001a9 ); +reg_write( DDR_REG_BASE + 0x000900bc*4 +0x02000000 , 0x0000000c ); +reg_write( DDR_REG_BASE + 0x000900bd*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x000900be*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x000900bf*4 +0x02000000 , 0x0000003e ); +reg_write( DDR_REG_BASE + 0x000900c0*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900c1*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900c2*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900c3*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x000900c4*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x000900c5*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900c6*4 +0x02000000 , 0x00008568 ); +reg_write( DDR_REG_BASE + 0x000900c7*4 +0x02000000 , 0x00000108 ); +reg_write( DDR_REG_BASE + 0x000900c8*4 +0x02000000 , 0x00000028 ); +reg_write( DDR_REG_BASE + 0x000900c9*4 +0x02000000 , 0x00000790 ); +reg_write( DDR_REG_BASE + 0x000900ca*4 +0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x000900cb*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900cc*4 +0x02000000 , 0x000001d8 ); +reg_write( DDR_REG_BASE + 0x000900cd*4 +0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x000900ce*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x000900cf*4 +0x02000000 , 0x00008558 ); +reg_write( DDR_REG_BASE + 0x000900d0*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x000900d1*4 +0x02000000 , 0x00000070 ); +reg_write( DDR_REG_BASE + 0x000900d2*4 +0x02000000 , 0x00000788 ); +reg_write( DDR_REG_BASE + 0x000900d3*4 +0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x000900d4*4 +0x02000000 , 0x00001ff8 ); +reg_write( DDR_REG_BASE + 0x000900d5*4 +0x02000000 , 0x000085a8 ); +reg_write( DDR_REG_BASE + 0x000900d6*4 +0x02000000 , 0x000001e8 ); +reg_write( DDR_REG_BASE + 0x000900d7*4 +0x02000000 , 0x00000028 ); +reg_write( DDR_REG_BASE + 0x000900d8*4 +0x02000000 , 0x00000798 ); +reg_write( DDR_REG_BASE + 0x000900d9*4 +0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x000900da*4 +0x02000000 , 0x00000038 ); +reg_write( DDR_REG_BASE + 0x000900db*4 +0x02000000 , 0x000007a0 ); +reg_write( DDR_REG_BASE + 0x000900dc*4 +0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x000900dd*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900de*4 +0x02000000 , 0x00008310 ); +reg_write( DDR_REG_BASE + 0x000900df*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x000900e0*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900e1*4 +0x02000000 , 0x0000a310 ); +reg_write( DDR_REG_BASE + 0x000900e2*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x000900e3*4 +0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x000900e4*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x000900e5*4 +0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x000900e6*4 +0x02000000 , 0x00000055 ); +reg_write( DDR_REG_BASE + 0x000900e7*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900e8*4 +0x02000000 , 0x00000068 ); +reg_write( DDR_REG_BASE + 0x000900e9*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900ea*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x000900eb*4 +0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x000900ec*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900ed*4 +0x02000000 , 0x00008310 ); +reg_write( DDR_REG_BASE + 0x000900ee*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x000900ef*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000900f0*4 +0x02000000 , 0x0000a310 ); +reg_write( DDR_REG_BASE + 0x000900f1*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x000900f2*4 +0x02000000 , 0x00001ff8 ); +reg_write( DDR_REG_BASE + 0x000900f3*4 +0x02000000 , 0x000085a8 ); +reg_write( DDR_REG_BASE + 0x000900f4*4 +0x02000000 , 0x000001e8 ); +reg_write( DDR_REG_BASE + 0x000900f5*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000900f6*4 +0x02000000 , 0x00000798 ); +reg_write( DDR_REG_BASE + 0x000900f7*4 +0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x000900f8*4 +0x02000000 , 0x00000050 ); +reg_write( DDR_REG_BASE + 0x000900f9*4 +0x02000000 , 0x000007a0 ); +reg_write( DDR_REG_BASE + 0x000900fa*4 +0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x000900fb*4 +0x02000000 , 0x00000040 ); +reg_write( DDR_REG_BASE + 0x000900fc*4 +0x02000000 , 0x00000790 ); +reg_write( DDR_REG_BASE + 0x000900fd*4 +0x02000000 , 0x0000016a ); +reg_write( DDR_REG_BASE + 0x000900fe*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x000900ff*4 +0x02000000 , 0x00008b10 ); +reg_write( DDR_REG_BASE + 0x00090100*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x00090101*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090102*4 +0x02000000 , 0x0000ab10 ); +reg_write( DDR_REG_BASE + 0x00090103*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x00090104*4 +0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x00090105*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x00090106*4 +0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x00090107*4 +0x02000000 , 0x00000055 ); +reg_write( DDR_REG_BASE + 0x00090108*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090109*4 +0x02000000 , 0x00000068 ); +reg_write( DDR_REG_BASE + 0x0009010a*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009010b*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x0009010c*4 +0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x0009010d*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009010e*4 +0x02000000 , 0x00008b10 ); +reg_write( DDR_REG_BASE + 0x0009010f*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x00090110*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00090111*4 +0x02000000 , 0x0000ab10 ); +reg_write( DDR_REG_BASE + 0x00090112*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x00090113*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090114*4 +0x02000000 , 0x000001d8 ); +reg_write( DDR_REG_BASE + 0x00090115*4 +0x02000000 , 0x00000169 ); +reg_write( DDR_REG_BASE + 0x00090116*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090117*4 +0x02000000 , 0x00008568 ); +reg_write( DDR_REG_BASE + 0x00090118*4 +0x02000000 , 0x00000108 ); +reg_write( DDR_REG_BASE + 0x00090119*4 +0x02000000 , 0x0000000a ); +reg_write( DDR_REG_BASE + 0x0009011a*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009011b*4 +0x02000000 , 0x00000189 ); +reg_write( DDR_REG_BASE + 0x0009011c*4 +0x02000000 , 0x00000058 ); +reg_write( DDR_REG_BASE + 0x0009011d*4 +0x02000000 , 0x00000790 ); +reg_write( DDR_REG_BASE + 0x0009011e*4 +0x02000000 , 0x0000010a ); +reg_write( DDR_REG_BASE + 0x0009011f*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090120*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x00090121*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090122*4 +0x02000000 , 0x00000020 ); +reg_write( DDR_REG_BASE + 0x00090123*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090124*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090125*4 +0x02000000 , 0x00000002 ); +reg_write( DDR_REG_BASE + 0x00090126*4 +0x02000000 , 0x00000408 ); +reg_write( DDR_REG_BASE + 0x00090127*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090128*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090129*4 +0x02000000 , 0x00008558 ); +reg_write( DDR_REG_BASE + 0x0009012a*4 +0x02000000 , 0x00000168 ); +reg_write( DDR_REG_BASE + 0x0009012b*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x0009012c*4 +0x02000000 , 0x000003c8 ); +reg_write( DDR_REG_BASE + 0x0009012d*4 +0x02000000 , 0x000001a9 ); +reg_write( DDR_REG_BASE + 0x0009012e*4 +0x02000000 , 0x00000003 ); +reg_write( DDR_REG_BASE + 0x0009012f*4 +0x02000000 , 0x00000370 ); +reg_write( DDR_REG_BASE + 0x00090130*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090131*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090132*4 +0x02000000 , 0x000002a8 ); +reg_write( DDR_REG_BASE + 0x00090133*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090134*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090135*4 +0x02000000 , 0x000000e8 ); +reg_write( DDR_REG_BASE + 0x00090136*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090137*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090138*4 +0x02000000 , 0x00008140 ); +reg_write( DDR_REG_BASE + 0x00090139*4 +0x02000000 , 0x0000010c ); +reg_write( DDR_REG_BASE + 0x0009013a*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x0009013b*4 +0x02000000 , 0x00008138 ); +reg_write( DDR_REG_BASE + 0x0009013c*4 +0x02000000 , 0x00000104 ); +reg_write( DDR_REG_BASE + 0x0009013d*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x0009013e*4 +0x02000000 , 0x00000448 ); +reg_write( DDR_REG_BASE + 0x0009013f*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090140*4 +0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00090141*4 +0x02000000 , 0x000007c0 ); +reg_write( DDR_REG_BASE + 0x00090142*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090143*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090144*4 +0x02000000 , 0x000000e8 ); +reg_write( DDR_REG_BASE + 0x00090145*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090146*4 +0x02000000 , 0x00000047 ); +reg_write( DDR_REG_BASE + 0x00090147*4 +0x02000000 , 0x00000630 ); +reg_write( DDR_REG_BASE + 0x00090148*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090149*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x0009014a*4 +0x02000000 , 0x00000618 ); +reg_write( DDR_REG_BASE + 0x0009014b*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009014c*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x0009014d*4 +0x02000000 , 0x000000e0 ); +reg_write( DDR_REG_BASE + 0x0009014e*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x0009014f*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090150*4 +0x02000000 , 0x000007c8 ); +reg_write( DDR_REG_BASE + 0x00090151*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090152*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090153*4 +0x02000000 , 0x00008140 ); +reg_write( DDR_REG_BASE + 0x00090154*4 +0x02000000 , 0x0000010c ); +reg_write( DDR_REG_BASE + 0x00090155*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090156*4 +0x02000000 , 0x00000478 ); +reg_write( DDR_REG_BASE + 0x00090157*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090158*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090159*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x0009015a*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x0009015b*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x0009015c*4 +0x02000000 , 0x00000004 ); +reg_write( DDR_REG_BASE + 0x0009015d*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00090006*4 +0x02000000 , 0x00000008 ); +reg_write( DDR_REG_BASE + 0x00090007*4 +0x02000000 , 0x000007c8 ); +reg_write( DDR_REG_BASE + 0x00090008*4 +0x02000000 , 0x00000109 ); +reg_write( DDR_REG_BASE + 0x00090009*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009000a*4 +0x02000000 , 0x00000400 ); +reg_write( DDR_REG_BASE + 0x0009000b*4 +0x02000000 , 0x00000106 ); +reg_write( DDR_REG_BASE + 0x000d00e7*4 +0x02000000 , 0x00000400 ); +reg_write( DDR_REG_BASE + 0x00090017*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009001f*4 +0x02000000 , 0x00000029 ); +reg_write( DDR_REG_BASE + 0x00090026*4 +0x02000000 , 0x0000005c ); +reg_write( DDR_REG_BASE + 0x000400d0*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000400d1*4 +0x02000000 , 0x00000101 ); +reg_write( DDR_REG_BASE + 0x000400d2*4 +0x02000000 , 0x00000105 ); +reg_write( DDR_REG_BASE + 0x000400d3*4 +0x02000000 , 0x00000107 ); +reg_write( DDR_REG_BASE + 0x000400d4*4 +0x02000000 , 0x0000010f ); +reg_write( DDR_REG_BASE + 0x000400d5*4 +0x02000000 , 0x00000202 ); +reg_write( DDR_REG_BASE + 0x000400d6*4 +0x02000000 , 0x0000020a ); +reg_write( DDR_REG_BASE + 0x000400d7*4 +0x02000000 , 0x0000020b ); +reg_write( DDR_REG_BASE + 0x0002000b*4 +0x02000000 , 0x00000042 ); +reg_write( DDR_REG_BASE + 0x0002000c*4 +0x02000000 , 0x00000085 ); +reg_write( DDR_REG_BASE + 0x0002000d*4 +0x02000000 , 0x00000534 ); // +reg_write( DDR_REG_BASE + 0x0002000e*4 +0x02000000 , 0x0000002c ); +reg_write( DDR_REG_BASE + 0x0009000c*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x0009000d*4 +0x02000000 , 0x00000173 ); +reg_write( DDR_REG_BASE + 0x0009000e*4 +0x02000000 , 0x00000060 ); +reg_write( DDR_REG_BASE + 0x0009000f*4 +0x02000000 , 0x00006110 ); +reg_write( DDR_REG_BASE + 0x00090010*4 +0x02000000 , 0x00002152 ); +reg_write( DDR_REG_BASE + 0x00090011*4 +0x02000000 , 0x0000dfbd ); +reg_write( DDR_REG_BASE + 0x00090012*4 +0x02000000 , 0x00002060 ); +reg_write( DDR_REG_BASE + 0x00090013*4 +0x02000000 , 0x00006152 ); + +reg_write( DDR_REG_BASE +0x20010*4+0x02000000,0x5a); +reg_write( DDR_REG_BASE +0x20011*4+0x02000000,0x3); + +reg_write( DDR_REG_BASE + 0x00040080*4 +0x02000000 , 0x000000b0 ); +//iteration +//DRAM DQ ODT +//(default: DQ odt disable) -> 0 +//(ODT:60) -> 0x14 +//(ODT:120) -> 0x18 +//(ODT:240) -> 0x1c +reg_write( DDR_REG_BASE + 0x00040081*4 +0x02000000 , 0x00000018 ); +reg_write( DDR_REG_BASE + 0x00040082*4 +0x02000000 , 0x00000010 ); +reg_write( DDR_REG_BASE + 0x00040083*4 +0x02000000 , 0x0000030c ); +reg_write( DDR_REG_BASE + 0x00040084*4 +0x02000000 , 0x00000020 ); +reg_write( DDR_REG_BASE + 0x00040085*4 +0x02000000 , 0x00000078 ); +reg_write( DDR_REG_BASE + 0x00040086*4 +0x02000000 , 0x00000030 ); +//iteration +// DSEL 34.3 -> 0x04 +// DSEL 40 -> 0x08 +// DSEL 48 -> 0x0c +// DSEL 60 -> 0x10 +// DSEL 80 -> 0x18 +reg_write( DDR_REG_BASE + 0x00040087*4 +0x02000000 , 0x00000010 ); // +reg_write( DDR_REG_BASE + 0x000400fd*4 +0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00010011*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00010012*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00010013*4 +0x02000000 , 0x00000080 ); +reg_write( DDR_REG_BASE + 0x00010018*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00010002*4 +0x02000000 , 0x00006209 ); +reg_write( DDR_REG_BASE + 0x000100b2*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000101b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000102b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000103b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000104b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000105b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000106b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000107b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000108b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000400e0*4 +0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00011011*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00011012*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00011013*4 +0x02000000 , 0x00000080 ); +reg_write( DDR_REG_BASE + 0x00011018*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00011002*4 +0x02000000 , 0x00006209 ); +reg_write( DDR_REG_BASE + 0x000110b2*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000111b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000112b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000113b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000114b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000115b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000116b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000117b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000118b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000400e1*4 +0x02000000 , 0x0000000f ); +reg_write( DDR_REG_BASE + 0x00012011*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00012012*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00012013*4 +0x02000000 , 0x00000080 ); +reg_write( DDR_REG_BASE + 0x00012018*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00012002*4 +0x02000000 , 0x00006209 ); +reg_write( DDR_REG_BASE + 0x000120b2*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000121b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000122b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000123b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000124b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000125b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000126b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000127b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000128b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000400e2*4 +0x02000000 , 0x000000ff ); +reg_write( DDR_REG_BASE + 0x00013011*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00013012*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00013013*4 +0x02000000 , 0x00000080 ); +reg_write( DDR_REG_BASE + 0x00013018*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00013002*4 +0x02000000 , 0x00006209 ); +reg_write( DDR_REG_BASE + 0x000130b2*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000131b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000132b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000133b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000134b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000135b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000136b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000137b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000138b4*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000400e3*4 +0x02000000 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00020089*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00020088*4 +0x02000000 , 0x00000019 ); +reg_write( DDR_REG_BASE + 0x000c0080*4 +0x02000000 , 0x00000002 ); +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000d0000*4 +0x02000000 , 0x00000000 ); +reg_read ( DDR_REG_BASE + 0x00020010*4 +0x02000000 , data ); +reg_write( DDR_REG_BASE + 0x00020010*4 +0x02000000 , 0x0000006a ); +reg_write( DDR_REG_BASE + 0x00020010*4 +0x02000000 , 0x0000006a ); +reg_read ( DDR_REG_BASE + 0x0002001d*4 +0x02000000 , data ); +reg_write( DDR_REG_BASE + 0x0002001d*4 +0x02000000 , 0x00000001 ); +reg_read ( DDR_REG_BASE + 0x00020097*4 +0x02000000 , data ); + + + +//////////////////////////dangdalong/////////////////////////////// + + + +reg_write( DDR_REG_BASE + 0x000001b0 , 0x00000020 ); + + +reg_read (DDR_REG_BASE + 0x000001bc , data ); +while((data&0x1) !=0x1){ + reg_read (DDR_REG_BASE + 0x000001bc , data ); +} + + +reg_write( DDR_REG_BASE + 0x000001b0 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000001b0 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000320 , 0x00000001 ); + + + + reg_read (DDR_REG_BASE + 0x00000324 , data ); + while((data&0x1) !=0x1){ + reg_read (DDR_REG_BASE + 0x00000324 , data ); + } + +reg_read (DDR_REG_BASE + 0x00000004 , data ); + while((data&0x1) !=0x1){ + reg_read (DDR_REG_BASE + 0x00000004 , data ); + } + + + + +reg_write( DDR_REG_BASE + 0x000001c4 , 0x85000000 ); +reg_write( DDR_REG_BASE + 0x00000320 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x000000d0 , 0x00020002 ); +reg_write( DDR_REG_BASE + 0x00000320 , 0x00000001 ); + + + reg_read (DDR_REG_BASE + 0x00000324 , data ); + while((data&0x1) !=0x1){ + reg_read (DDR_REG_BASE + 0x00000324 , data ); + } + + + +reg_write( DDR_REG_BASE + 0x00000304 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000030 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000490 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000540 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000005f0 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x000006a0 , 0x00000001 ); +reg_write( DDR_REG_BASE + 0x00000750 , 0x00000001 ); + +reg_write( DDR_REG_BASE + 0x00000060 , 0x00000000 ); +reg_write( DDR_REG_BASE + 0x00000050 , 0x98210000 ); +} diff --git a/src/little/uboot/configs/k230_canmv_dongshanpi_burntool_defconfig b/src/little/uboot/configs/k230_canmv_dongshanpi_burntool_defconfig new file mode 100755 index 000000000..949d9a5c6 --- /dev/null +++ b/src/little/uboot/configs/k230_canmv_dongshanpi_burntool_defconfig @@ -0,0 +1,108 @@ +CONFIG_RISCV=y +CONFIG_SYS_TEXT_BASE=0x80300000 +CONFIG_SYS_MALLOC_F_LEN=0x40000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x10000 +CONFIG_DEFAULT_DEVICE_TREE="k230_canmv_dongshanpi" +CONFIG_SYS_PROMPT="K230# " +CONFIG_SYS_LOAD_ADDR=0xc000000 +CONFIG_BUILD_TARGET="u-boot.bin" +CONFIG_TARGET_K230_CANMV_DONGSHANPI=y +CONFIG_ARCH_RV64I=y +CONFIG_SHOW_REGS=y +CONFIG_CC_OPTIMIZE_FOR_DEBUG=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_TIMESTAMP=y +CONFIG_FIT_SIGNATURE=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_BOOTDELAY=1 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_STOP_STR="stop" +CONFIG_LOGLEVEL=7 +CONFIG_SYS_STDIO_DEREGISTER=y +# CONFIG_SYS_DEVICE_NULLDEV is not set +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_BOARD_EARLY_INIT_F=y +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_CPU is not set +# CONFIG_CMD_BOOTFLOW is not set +# CONFIG_CMD_BOOTI is not set +# CONFIG_BOOTM_LINUX is not set +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +CONFIG_SYS_BOOTM_LEN=0x8000000 +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_FDT is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_DFU=y +# CONFIG_CMD_DM is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +# CONFIG_CMD_PINMUX is not set +# CONFIG_CMD_ECHO is not set +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SOURCE is not set +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_BLOCK_CACHE is not set +# CONFIG_CMD_SLEEP is not set +CONFIG_CMD_MTDPARTS=y +# CONFIG_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_OF_EMBED=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +# CONFIG_NET is not set +CONFIG_DFU_MMC=y +CONFIG_DFU_MTD=y +CONFIG_DFU_SF=y +CONFIG_DFU_VIRT=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x80000 +# CONFIG_GPIO is not set +# CONFIG_I2C is not set +# CONFIG_INPUT is not set +CONFIG_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_DW=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_SNPS=y +CONFIG_DM_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x29f1 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0230 +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_REGEX=y +CONFIG_LZ4=y +CONFIG_LZMA=y +CONFIG_SPL_GZIP=y +# CONFIG_EFI_LOADER is not set diff --git a/src/little/uboot/configs/k230_canmv_dongshanpi_defconfig b/src/little/uboot/configs/k230_canmv_dongshanpi_defconfig new file mode 100755 index 000000000..aa7abb6d4 --- /dev/null +++ b/src/little/uboot/configs/k230_canmv_dongshanpi_defconfig @@ -0,0 +1,111 @@ +CONFIG_RISCV=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x40000 +CONFIG_NR_DRAM_BANKS=3 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x1e0000 +CONFIG_SPL_DM_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="k230_canmv_dongshanpi" +CONFIG_SPL_TEXT_BASE=0x80300000 +CONFIG_SYS_PROMPT="K230# " +CONFIG_SPL_MMC=y +CONFIG_SPL_SYS_MALLOC_F_LEN=0x30000 +CONFIG_SPL_SIZE_LIMIT=0x80000 +CONFIG_SPL=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SYS_LOAD_ADDR=0xc000000 +CONFIG_BUILD_TARGET="u-boot.bin" +CONFIG_TARGET_K230_CANMV_DONGSHANPI=y +CONFIG_ARCH_RV64I=y +# CONFIG_SPL_SMP is not set +CONFIG_SHOW_REGS=y +CONFIG_SYS_MEMTEST_END=0x100000 +CONFIG_CC_OPTIMIZE_FOR_DEBUG=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_TIMESTAMP=y +CONFIG_FIT_SIGNATURE=y +CONFIG_SPL_FIT=y +# CONFIG_SPL_LOAD_FIT is not set +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_BOOTDELAY=5 +CONFIG_LOGLEVEL=7 +CONFIG_SYS_STDIO_DEREGISTER=y +# CONFIG_SYS_DEVICE_NULLDEV is not set +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_MAX_SIZE=0x80000 +CONFIG_SPL_BSS_START_ADDR=0x80380000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1000 +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_MMC_WRITE=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_DM_SPI_FLASH=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 +CONFIG_SPL_YMODEM_SUPPORT=y +# CONFIG_CMD_CPU is not set +CONFIG_CMD_BOOTMETH=y +CONFIG_SYS_BOOTM_LEN=0x8000000 +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_MD5SUM=y +CONFIG_MD5SUM_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +# CONFIG_CMD_PINMUX is not set +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_USB=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_OF_EMBED=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SECT_SIZE_AUTO=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_PROT_UDP=y +CONFIG_BOOTP_SERVERIP=y +CONFIG_SPL_DM_DEVICE_REMOVE=y +CONFIG_SPL_CLK=y +CONFIG_DM_KEYBOARD=y +CONFIG_MMC=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y +CONFIG_MMC_DW=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_SNPS=y +CONFIG_DM_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_SPL_PINCONF=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_FAT_WRITE=y +CONFIG_SPL_GZIP=y +# CONFIG_EFI_LOADER is not set diff --git a/src/little/uboot/configs/k230_canmv_v2_defconfig b/src/little/uboot/configs/k230_canmv_v2_defconfig index ddf543283..6d76759a9 100755 --- a/src/little/uboot/configs/k230_canmv_v2_defconfig +++ b/src/little/uboot/configs/k230_canmv_v2_defconfig @@ -73,7 +73,6 @@ CONFIG_ENV_SECT_SIZE_AUTO=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_PROT_UDP=y CONFIG_BOOTP_SERVERIP=y -CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_DEVICE_REMOVE=y CONFIG_SPL_CLK=y CONFIG_DM_KEYBOARD=y diff --git a/src/little/uboot/drivers/mmc/snps_sdhci.c b/src/little/uboot/drivers/mmc/snps_sdhci.c index 1bed1149d..fe653fa4b 100755 --- a/src/little/uboot/drivers/mmc/snps_sdhci.c +++ b/src/little/uboot/drivers/mmc/snps_sdhci.c @@ -52,6 +52,7 @@ struct snps_sdhci_plat { #define DWC_MSHC_SDCLKDL_DC (DWC_MSHC_PTR_PHY_REGS + 0x1E) #define DWC_MSHC_SMPLDL_CNFG (DWC_MSHC_PTR_PHY_REGS + 0x20) #define DWC_MSHC_ATDL_CNFG (DWC_MSHC_PTR_PHY_REGS + 0x21) +#define DWC_MSHC_DLL_CNFG2_R (DWC_MSHC_PTR_PHY_REGS + 0x26) #define DWC_MSHC_PHY_PAD_SD_CLK \ ((1 << TXSLEW_N_LSB) | (3 << TXSLEW_P_LSB) | (0 << WEAKPULL_EN_LSB) | \ @@ -103,19 +104,42 @@ static void dwcmshc_phy_pad_config(struct sdhci_host *host) static void dwcmshc_phy_delay_config(struct sdhci_host *host) { - sdhci_writeb(host, 1, DWC_MSHC_COMMDL_CNFG); - sdhci_writeb(host, 0x1, DWC_MSHC_SDCLKDL_CNFG); - //sdhci_writeb(host, 0x30, DWC_MSHC_SDCLKDL_DC); - sdhci_writeb(host, 0x40, DWC_MSHC_SDCLKDL_DC); + u32 val; + int ret; + u32 tx_delay_line = 0x40; + u32 rx_delay_line = 0xd; + u32 extdly_en = 0; + u32 cckdl_dc = 0x40; + ret = dev_read_u32(host->mmc->dev, "tx_delay_line", &tx_delay_line); + + if(tx_delay_line > 255) { + printf("tx_delay_line err\n"); + } + else if (tx_delay_line >= 128) { + extdly_en = 1; + cckdl_dc = tx_delay_line - 128; + } else { + extdly_en = 0; + cckdl_dc = tx_delay_line; + } + /* disable delay line */ + sdhci_writeb(host, 1<<4 | extdly_en, DWC_MSHC_SDCLKDL_CNFG); + + /* set delay line */ + sdhci_writeb(host, cckdl_dc, DWC_MSHC_SDCLKDL_DC); + + /* enable delay lane */ + val = sdhci_readb(host, DWC_MSHC_SDCLKDL_CNFG); + val &= ~(1<<4); + sdhci_writeb(host, val, DWC_MSHC_SDCLKDL_CNFG); + + dev_read_u32(host->mmc->dev, "rx_delay_line", &rx_delay_line); + sdhci_writeb(host, rx_delay_line, DWC_MSHC_SMPLDL_CNFG); - //sdhci_writeb(host, 0xd, DWC_MSHC_SMPLDL_CNFG); - sdhci_writeb(host, 0x8, DWC_MSHC_SMPLDL_CNFG); - sdhci_writeb(host, 0xc, DWC_MSHC_ATDL_CNFG); sdhci_writel(host, (sdhci_readl(host, SDHCI_VENDER_AT_CTRL_REG) | \ BIT(16) | BIT(17) | BIT(19) | BIT(20)), SDHCI_VENDER_AT_CTRL_REG); - sdhci_writel(host,0x0,SDHCI_VENDER_AT_STAT_REG); - + sdhci_writel(host,0x0,SDHCI_VENDER_AT_STAT_REG); return; } @@ -166,6 +190,7 @@ static int snps_sdhci_probe(struct udevice *dev) struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct snps_sdhci_plat *plat = dev_get_plat(dev); struct sdhci_host *host = dev_get_priv(dev); + struct mmc_config *cfg = &plat->cfg; u32 max_clk; struct clk clk; int ret; @@ -189,7 +214,7 @@ static int snps_sdhci_probe(struct udevice *dev) host->mmc->priv = host; upriv->mmc = host->mmc; - ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0); + ret = sdhci_setup_cfg(cfg, host, cfg->f_max, 0); if (ret) goto err; diff --git a/src/reference/ai_poc/CMakeLists.txt b/src/reference/ai_poc/CMakeLists.txt index e55b2351c..65c044d00 100644 --- a/src/reference/ai_poc/CMakeLists.txt +++ b/src/reference/ai_poc/CMakeLists.txt @@ -19,8 +19,11 @@ include_directories(${nncase_sdk_root}/riscv64/nncase/include) include_directories(${nncase_sdk_root}/riscv64/nncase/include/nncase/runtime) link_directories(${nncase_sdk_root}/riscv64/nncase/lib/) +# set vi_vo +include_directories(./vi_vo) + # 定义要排除的目录列表 -set(exclude_dirs "cmake" "k230_bin" "shell" "out" "llamac" ".git") +set(exclude_dirs "cmake" "k230_bin" "shell" "out" "llamac" ".git" "vi_vo") file(GLOB files "${CMAKE_CURRENT_SOURCE_DIR}/*") foreach(file ${files}) # 判断当前文件是否是一个目录 diff --git a/src/reference/ai_poc/build_app.sh b/src/reference/ai_poc/build_app.sh index 12b92709d..cd37ab02d 100755 --- a/src/reference/ai_poc/build_app.sh +++ b/src/reference/ai_poc/build_app.sh @@ -516,6 +516,7 @@ for subdir in $(ls -d */); do cp -a ../../big/kmodel/ai_poc/kmodel/yolov8n-pose.kmodel ${k230_bin}/$subdir_name cp -a shell/rtsp_plug_*.sh ${k230_bin}/$subdir_name fi + rm -rf out/* done rm -rf out diff --git a/src/reference/ai_poc/bytetrack/main.cc b/src/reference/ai_poc/bytetrack/main.cc index 8fdb54ecc..9948042e9 100644 --- a/src/reference/ai_poc/bytetrack/main.cc +++ b/src/reference/ai_poc/bytetrack/main.cc @@ -144,7 +144,7 @@ void print_usage(const char *name) } -void video_proc(char *argv[]) +void video_proc_v1(char *argv[]) { vivcap_start(); @@ -284,6 +284,428 @@ void video_proc(char *argv[]) } +void video_proc_v2(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + personDetect pd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + std::vector results; + std::vector objects; + + // int fps = 24; + int fps = atoi(argv[6]); + int buffer = atoi(argv[7]); + BYTETracker tracker(fps, buffer); + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + { + ScopedTiming st("results and objects clear ", atoi(argv[5])); + results.clear(); + objects.clear(); + } + + pd.pre_process(); + pd.inference(); + pd.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + std::string text; + cv::Point origin; + + for (auto res : results) + { + ScopedTiming st("results transfer ", atoi(argv[5])); + + Object obj{ {res.x1,res.y1,res.x2- res.x1,res.y2- res.y1},res.label,res.score }; + objects.push_back(obj); + + } + + std::vector output_stracks; + { + ScopedTiming st("tracker.update ", atoi(argv[5])); + output_stracks = tracker.update(objects); + } + + for (int i = 0; i < output_stracks.size(); i++) + { + ScopedTiming st("draw boxes", atoi(argv[5])); + std::vector tlwh = output_stracks[i].tlwh; + bool vertical = tlwh[2] / tlwh[3] > 1.6; + if (tlwh[2] * tlwh[3] > 20 && !vertical) + { + Scalar s = tracker.get_color(output_stracks[i].track_id); + + int x1 = tlwh[0] / SENSOR_WIDTH * osd_width; + int y1 = tlwh[1] / SENSOR_HEIGHT * osd_height; + + int w = tlwh[2] / SENSOR_WIDTH * osd_width; + int h = tlwh[3] / SENSOR_HEIGHT * osd_height; + + cv::putText(osd_frame, format("%d", output_stracks[i].track_id), Point(x1, y1 + 5), 0, 2, Scalar(255,255, 0, 0), 2, LINE_AA); + cv::rectangle(osd_frame, Rect(x1,y1,w,h), s, 2); + + + } + } + + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_k230d(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + personDetect pd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + std::vector results; + std::vector objects; + + // int fps = 24; + int fps = atoi(argv[6]); + int buffer = atoi(argv[7]); + BYTETracker tracker(fps, buffer); + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + { + ScopedTiming st("results and objects clear ", atoi(argv[5])); + results.clear(); + objects.clear(); + } + + pd.pre_process(); + pd.inference(); + pd.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + std::string text; + cv::Point origin; + + for (auto res : results) + { + ScopedTiming st("results transfer ", atoi(argv[5])); + + Object obj{ {res.x1,res.y1,res.x2- res.x1,res.y2- res.y1},res.label,res.score }; + objects.push_back(obj); + + } + + std::vector output_stracks; + { + ScopedTiming st("tracker.update ", atoi(argv[5])); + output_stracks = tracker.update(objects); + } + + for (int i = 0; i < output_stracks.size(); i++) + { + ScopedTiming st("draw boxes", atoi(argv[5])); + std::vector tlwh = output_stracks[i].tlwh; + bool vertical = tlwh[2] / tlwh[3] > 1.6; + if (tlwh[2] * tlwh[3] > 20 && !vertical) + { + Scalar s = tracker.get_color(output_stracks[i].track_id); + + int x1 = tlwh[0] / SENSOR_WIDTH * osd_frame.cols; + int y1 = tlwh[1] / SENSOR_HEIGHT * osd_frame.rows; + + int w = tlwh[2] / SENSOR_WIDTH * osd_frame.cols; + int h = tlwh[3] / SENSOR_HEIGHT * osd_frame.rows; + + cv::putText(osd_frame, format("%d", output_stracks[i].track_id), Point(x1, y1 + 5), 0, 2, Scalar(255,255, 0, 0), 2, LINE_AA); + cv::rectangle(osd_frame, Rect(x1,y1,w,h), s, 2); + + + } + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_01(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + personDetect pd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + std::vector results; + std::vector objects; + + // int fps = 24; + int fps = atoi(argv[6]); + int buffer = atoi(argv[7]); + BYTETracker tracker(fps, buffer); + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + { + ScopedTiming st("results and objects clear ", atoi(argv[5])); + results.clear(); + objects.clear(); + } + + pd.pre_process(); + pd.inference(); + pd.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + std::string text; + cv::Point origin; + + for (auto res : results) + { + ScopedTiming st("results transfer ", atoi(argv[5])); + + Object obj{ {res.x1,res.y1,res.x2- res.x1,res.y2- res.y1},res.label,res.score }; + objects.push_back(obj); + + } + + std::vector output_stracks; + { + ScopedTiming st("tracker.update ", atoi(argv[5])); + output_stracks = tracker.update(objects); + } + + for (int i = 0; i < output_stracks.size(); i++) + { + ScopedTiming st("draw boxes", atoi(argv[5])); + std::vector tlwh = output_stracks[i].tlwh; + bool vertical = tlwh[2] / tlwh[3] > 1.6; + if (tlwh[2] * tlwh[3] > 20 && !vertical) + { + Scalar s = tracker.get_color(output_stracks[i].track_id); + + int x1 = tlwh[0] / SENSOR_WIDTH * osd_frame.cols; + int y1 = tlwh[1] / SENSOR_HEIGHT * osd_frame.rows; + + int w = tlwh[2] / SENSOR_WIDTH * osd_frame.cols; + int h = tlwh[3] / SENSOR_HEIGHT * osd_frame.rows; + + cv::putText(osd_frame, format("%d", output_stracks[i].track_id), Point(x1, y1 + 5), 0, 2, Scalar(255,255, 0, 0), 2, LINE_AA); + cv::rectangle(osd_frame, Rect(x1,y1,w,h), s, 2); + + + } + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + int main(int argc, char *argv[]) { @@ -296,14 +718,62 @@ int main(int argc, char *argv[]) if (strcmp(argv[4], "None") == 0) { - std::thread thread_isp(video_proc, argv); - while (getchar() != 'q') + #if defined(CONFIG_BOARD_K230_CANMV) + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_V2) + { + std::thread thread_isp(video_proc_v2, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230D_CANMV) { - usleep(10000); + std::thread thread_isp(video_proc_k230d, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + std::thread thread_isp(video_proc_01, argv); + while (getchar() != 'q') + { + usleep(10000); + } - isp_stop = true; - thread_isp.join(); + isp_stop = true; + thread_isp.join(); + } + #else + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #endif } else { diff --git a/src/reference/ai_poc/bytetrack/vi_vo.h b/src/reference/ai_poc/bytetrack/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/bytetrack/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/crosswalk_detect/main.cc b/src/reference/ai_poc/crosswalk_detect/main.cc index a4cae9b99..b842918cb 100644 --- a/src/reference/ai_poc/crosswalk_detect/main.cc +++ b/src/reference/ai_poc/crosswalk_detect/main.cc @@ -52,7 +52,7 @@ void print_usage(const char *name) << endl; } -void video_proc(char *argv[]) +void video_proc_v1(char *argv[]) { vivcap_start(); @@ -170,6 +170,364 @@ void video_proc(char *argv[]) } +void video_proc_v2(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + crosswalkDetect cw(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + cw.pre_process(); + cw.inference(); + cw.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + + std::string text; + cv::Point origin; + std::vector scalars= { + cv::Scalar(255,0, 0, 255), // "crosswalk" + cv::Scalar(255,0, 255, 0), // "None" + cv::Scalar(255,255,0, 0), + cv::Scalar(255,255,0, 255) + }; + + for (auto r : results) + { + ScopedTiming st("draw boxes", atoi(argv[5])); + text = cw.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); + + int x1 = r.x1 / SENSOR_WIDTH * osd_width; + int y1 = r.y1 / SENSOR_HEIGHT * osd_height; + + origin.x = x1; + origin.y = y1-20; + + int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_width; + int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_height; + + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), cv::Scalar(255, 255,0, 0), 6, 2, 0); // ARGB + cv::putText(osd_frame, text, origin, cv::FONT_HERSHEY_COMPLEX, 2, scalars[r.label+2], 1, 8, 0); + + } + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_k230d(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + crosswalkDetect cw(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + cw.pre_process(); + cw.inference(); + cw.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + std::string text; + cv::Point origin; + std::vector scalars= { + cv::Scalar(255,0, 0, 255), // "crosswalk" + cv::Scalar(255,0, 255, 0), // "None" + cv::Scalar(255,255,0, 0), + cv::Scalar(255,255,0, 255) + }; + + for (auto r : results) + { + ScopedTiming st("draw boxes", atoi(argv[5])); + text = cw.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); + + int x1 = r.x1 / SENSOR_WIDTH * osd_frame.cols; + int y1 = r.y1 / SENSOR_HEIGHT * osd_frame.rows; + + origin.x = x1; + origin.y = y1-20; + + int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_frame.cols; + int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_frame.rows; + + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), cv::Scalar(255, 255,0, 0), 6, 2, 0); // ARGB + cv::putText(osd_frame, text, origin, cv::FONT_HERSHEY_COMPLEX, 2, scalars[r.label+2], 1, 8, 0); + + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_01(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + crosswalkDetect cw(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + cw.pre_process(); + cw.inference(); + cw.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + std::string text; + cv::Point origin; + std::vector scalars= { + cv::Scalar(255,0, 0, 255), // "crosswalk" + cv::Scalar(255,0, 255, 0), // "None" + cv::Scalar(255,255,0, 0), + cv::Scalar(255,255,0, 255) + }; + + for (auto r : results) + { + ScopedTiming st("draw boxes", atoi(argv[5])); + text = cw.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); + + int x1 = r.x1 / SENSOR_WIDTH * osd_frame.cols; + int y1 = r.y1 / SENSOR_HEIGHT * osd_frame.rows; + + origin.x = x1; + origin.y = y1-20; + + int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_frame.cols; + int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_frame.rows; + + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), cv::Scalar(255, 255,0, 0), 6, 2, 0); // ARGB + cv::putText(osd_frame, text, origin, cv::FONT_HERSHEY_COMPLEX, 2, scalars[r.label+2], 1, 8, 0); + + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + int main(int argc, char *argv[]) { @@ -182,14 +540,62 @@ int main(int argc, char *argv[]) if (strcmp(argv[4], "None") == 0) { - std::thread thread_isp(video_proc, argv); - while (getchar() != 'q') + #if defined(CONFIG_BOARD_K230_CANMV) + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_V2) + { + std::thread thread_isp(video_proc_v2, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230D_CANMV) { - usleep(10000); + std::thread thread_isp(video_proc_k230d, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + std::thread thread_isp(video_proc_01, argv); + while (getchar() != 'q') + { + usleep(10000); + } - isp_stop = true; - thread_isp.join(); + isp_stop = true; + thread_isp.join(); + } + #else + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #endif } else { diff --git a/src/reference/ai_poc/dec_ai_enc/enc/enc.c b/src/reference/ai_poc/dec_ai_enc/enc/enc.c index 267555ef4..1ebe03d6d 100644 --- a/src/reference/ai_poc/dec_ai_enc/enc/enc.c +++ b/src/reference/ai_poc/dec_ai_enc/enc/enc.c @@ -929,6 +929,10 @@ int main(int argc, char *argv[]) sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; #elif defined(CONFIG_BOARD_K230_CANMV_V2) sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; + #elif defined(CONFIG_BOARD_K230D_CANMV) + sensor_type = OV_OV5647_MIPI_1920X1080_30FPS_10BIT_LINEAR; #else sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; #endif diff --git a/src/reference/ai_poc/distraction_reminder/main.cc b/src/reference/ai_poc/distraction_reminder/main.cc index 5ef369a6c..73040b8f9 100644 --- a/src/reference/ai_poc/distraction_reminder/main.cc +++ b/src/reference/ai_poc/distraction_reminder/main.cc @@ -52,7 +52,7 @@ void print_usage(const char *name) << endl; } -void video_proc(char *argv[]) +void video_proc_v1(char *argv[]) { vivcap_start(); // 设置osd参数 @@ -180,6 +180,264 @@ void video_proc(char *argv[]) } } +void video_proc_v2(char *argv[]) +{ + vivcap_start(); + // 设置osd参数 + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + memset(&vf_info, 0, sizeof(vf_info)); + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory,get isp memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + FaceDetection fd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[9])); + FacePose fp(argv[4], {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[9])); + + vector det_results; + FacePoseInfo pose_result; + int warning_amount = atoi(argv[5]); + float warning_angle_roll = atof(argv[6]); + float warning_angle_yaw = atof(argv[7]); + float warning_angle_pitch = atof(argv[8]); + int warning_count = 0; + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[9])); + // 从vivcap中读取一帧图像到dump_info + memset(&dump_info, 0, sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + { + ScopedTiming st("isp copy", atoi(argv[9])); + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + det_results.clear(); + + fd.pre_process(); + fd.inference(); + // 旋转后图像 + fd.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, det_results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + + float max_area_face = 0; + int max_id_face = -1; + for (int i = 0; i < det_results.size(); ++i) + { + float area_i = det_results[i].bbox.w * det_results[i].bbox.h; + if (area_i > max_area_face) + { + max_area_face = area_i; + max_id_face = i; + } + } + + if (max_id_face != -1) + { + fp.pre_process(det_results[max_id_face].bbox); + fp.inference(); + fp.post_process(pose_result); + { + ScopedTiming st("osd draw", atoi(argv[9])); + fp.draw_result(osd_frame,det_results[max_id_face].bbox,pose_result,false); + } + if (std::abs(pose_result.roll) > warning_angle_roll || std::abs(pose_result.yaw) > warning_angle_yaw || std::abs(pose_result.pitch) > warning_angle_pitch) + { + warning_count += 1; + } + else + { + warning_count = 0; + } + if (warning_count > warning_amount) + { + cv::putText(osd_frame, " Please look straight ahead ! ", {0, 100}, cv::FONT_HERSHEY_COMPLEX, 2, cv::Scalar(255, 255, 0, 0), 2, 4, 0); + } + } + + { + ScopedTiming st("osd copy", atoi(argv[9])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + // 显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id + 3, &vf_info); // K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } +} + +void video_proc_k230d(char *argv[]) +{ + vivcap_start(); + // 设置osd参数 + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + memset(&vf_info, 0, sizeof(vf_info)); + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory,get isp memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + FaceDetection fd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[9])); + FacePose fp(argv[4], {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[9])); + + vector det_results; + FacePoseInfo pose_result; + int warning_amount = atoi(argv[5]); + float warning_angle_roll = atof(argv[6]); + float warning_angle_yaw = atof(argv[7]); + float warning_angle_pitch = atof(argv[8]); + int warning_count = 0; + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[9])); + // 从vivcap中读取一帧图像到dump_info + memset(&dump_info, 0, sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + { + ScopedTiming st("isp copy", atoi(argv[9])); + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + det_results.clear(); + + fd.pre_process(); + fd.inference(); + // 旋转后图像 + fd.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, det_results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + float max_area_face = 0; + int max_id_face = -1; + for (int i = 0; i < det_results.size(); ++i) + { + float area_i = det_results[i].bbox.w * det_results[i].bbox.h; + if (area_i > max_area_face) + { + max_area_face = area_i; + max_id_face = i; + } + } + + if (max_id_face != -1) + { + fp.pre_process(det_results[max_id_face].bbox); + fp.inference(); + fp.post_process(pose_result); + { + ScopedTiming st("osd draw", atoi(argv[9])); + fp.draw_result(osd_frame,det_results[max_id_face].bbox,pose_result,false); + } + if (std::abs(pose_result.roll) > warning_angle_roll || std::abs(pose_result.yaw) > warning_angle_yaw || std::abs(pose_result.pitch) > warning_angle_pitch) + { + warning_count += 1; + } + else + { + warning_count = 0; + } + if (warning_count > warning_amount) + { + cv::putText(osd_frame, " Please look straight ahead ! ", {0, 100}, cv::FONT_HERSHEY_COMPLEX, 2, cv::Scalar(255, 255, 0, 0), 2, 4, 0); + } + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[9])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + // 显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id + 3, &vf_info); // K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } +} + int main(int argc, char *argv[]) { std::cout << "case " << argv[0] << " built at " << __DATE__ << " " << __TIME__ << std::endl; @@ -188,13 +446,61 @@ int main(int argc, char *argv[]) print_usage(argv[0]); return -1; } - std::thread thread_isp(video_proc, argv); - while (getchar() != 'q') + #if defined(CONFIG_BOARD_K230_CANMV) + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_V2) { - usleep(10000); + std::thread thread_isp(video_proc_v2, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); } + #elif defined(CONFIG_BOARD_K230D_CANMV) + { + std::thread thread_isp(video_proc_k230d, argv); + while (getchar() != 'q') + { + usleep(10000); + } - isp_stop = true; - thread_isp.join(); + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + std::thread thread_isp(video_proc_01, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #else + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #endif return 0; } \ No newline at end of file diff --git a/src/reference/ai_poc/distraction_reminder/vi_vo.h b/src/reference/ai_poc/distraction_reminder/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/distraction_reminder/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/dms_system/main.cc b/src/reference/ai_poc/dms_system/main.cc index eb9a570d3..b0658feeb 100644 --- a/src/reference/ai_poc/dms_system/main.cc +++ b/src/reference/ai_poc/dms_system/main.cc @@ -53,7 +53,7 @@ void print_usage(const char *name) << endl; } -void video_proc(char *argv[]) +void video_proc_v1(char *argv[]) { vivcap_start(); // 设置osd参数 @@ -263,6 +263,640 @@ void video_proc(char *argv[]) } } +void video_proc_v2(char *argv[]) +{ + vivcap_start(); + // 设置osd参数 + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + memset(&vf_info, 0, sizeof(vf_info)); + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory,get isp memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + FaceDetection fd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[10])); + HandDetection hd(argv[4], atof(argv[5]), atof(argv[6]), {SENSOR_WIDTH, SENSOR_HEIGHT}, {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[10])); + + vector face_results; + vector hand_results; + + float init_area = atof(argv[7]); + float init_len = atof(argv[8]); + float now_area; + float now_len; + int warning_amount = atoi(argv[9]); + int warning_count_smk_drk = 0; + int warning_count_drk = 0; + int warning_count_call = 0; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + { + ScopedTiming st("read capture", atoi(argv[10])); + // 从vivcap中读取一帧图像到dump_info + memset(&dump_info, 0, sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + { + ScopedTiming st("isp copy", atoi(argv[10])); + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + face_results.clear(); + fd.pre_process(); + fd.inference(); + // 旋转后图像 + fd.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, face_results); + + hand_results.clear(); + hd.pre_process(); + hd.inference(); + // 旋转后图像 + hd.post_process(hand_results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + + float max_area_face = 0; + int max_id_face = -1; + for (int i = 0; i < face_results.size(); ++i) + { + float area_i = face_results[i].bbox.w * face_results[i].bbox.h; + if (area_i > max_area_face) + { + max_area_face = area_i; + max_id_face = i; + } + } + + float max_area_hand = 0; + int max_id_hand = -1; + for (int i = 0; i < hand_results.size(); ++i) + { + float area_i = (hand_results[i].x2 - hand_results[i].x1) * (hand_results[i].y2 - hand_results[i].y1); + if (area_i > max_area_hand) + { + max_area_hand = area_i; + max_id_hand = i; + } + } + + string text_dms_call = "Calling : No "; + string text_dms_smoke_drink = "Smoking or Drinking : No "; + if (max_id_face != -1 && max_id_hand != -1) + { + float face_x = face_results[max_id_face].bbox.x + (face_results[max_id_face].bbox.w / 2.0); + float face_y = face_results[max_id_face].bbox.y + (face_results[max_id_face].bbox.h / 2.0); + float hand_x = (hand_results[max_id_hand].x1 + hand_results[max_id_hand].x2) / 2.0; + float hand_y = (hand_results[max_id_hand].y1 + hand_results[max_id_hand].y2) / 2.0; + + now_area = max_area_face; + now_len = sqrt(pow(face_x - hand_x, 2) + pow(face_y - hand_y, 2)); + + if (now_len < (now_area / init_area) * init_len) + { + if (face_y < hand_y && (abs(face_y - hand_y) / abs(face_x - hand_x)) > 1) + { + warning_count_smk_drk += 1; + warning_count_drk = 0; + warning_count_call = 0; + } + else if (face_y > hand_y && (abs(face_y - hand_y) / abs(face_x - hand_x)) > 0.8) + { + warning_count_smk_drk = 0; + warning_count_drk += 1; + warning_count_call = 0; + } + else + { + warning_count_smk_drk = 0; + warning_count_drk = 0; + warning_count_call += 1; + } + + if (warning_count_smk_drk > warning_amount) + { + text_dms_smoke_drink = "Smoking or Drinking : Yes "; + cv::putText(osd_frame, text_dms_call, cv::Point(20,50),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 0, 255, 0), 2, 4, 0); + cv::putText(osd_frame, text_dms_smoke_drink, cv::Point(20,100),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 255, 0, 0), 2, 4, 0); + } + else if (warning_count_drk > warning_amount) + { + text_dms_smoke_drink = "Drinking : Yes "; + cv::putText(osd_frame, text_dms_call, cv::Point(20,50),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 0, 255, 0), 2, 4, 0); + cv::putText(osd_frame, text_dms_smoke_drink, cv::Point(20,100),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 255, 0, 0), 2, 4, 0); + } + else if (warning_count_call > warning_amount) + { + text_dms_call = "Calling : Yes "; + cv::putText(osd_frame, text_dms_call, cv::Point(20,50),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 255, 0, 0), 2, 4, 0); + cv::putText(osd_frame, text_dms_smoke_drink, cv::Point(20,100),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 0, 255, 0), 2, 4, 0); + } + else + { + cv::putText(osd_frame, text_dms_call, cv::Point(20,50),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 0, 255, 0), 2, 4, 0); + cv::putText(osd_frame, text_dms_smoke_drink, cv::Point(20,100),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 0, 255, 0), 2, 4, 0); + } + } + else + { + warning_count_smk_drk = 0; + warning_count_drk = 0; + warning_count_call = 0; + cv::putText(osd_frame, text_dms_call, cv::Point(20,50),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 0, 255, 0), 2, 4, 0); + cv::putText(osd_frame, text_dms_smoke_drink, cv::Point(20,100),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 0, 255, 0), 2, 4, 0); + } + + + int w = hand_results[max_id_hand].x2 - hand_results[max_id_hand].x1 + 1; + int h = hand_results[max_id_hand].y2 - hand_results[max_id_hand].y1 + 1; + + int rect_x = hand_results[max_id_hand].x1/ SENSOR_WIDTH * osd_width; + int rect_y = hand_results[max_id_hand].y1/ SENSOR_HEIGHT * osd_height; + int rect_w = (float)w / SENSOR_WIDTH * osd_width; + int rect_h = (float)h / SENSOR_HEIGHT * osd_height; + cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w, rect_h), cv::Scalar( 255, 0, 255, 255), 6, 2, 0); + } + else + { + warning_count_smk_drk = 0; + warning_count_drk = 0; + warning_count_call = 0; + cv::putText(osd_frame, text_dms_call, cv::Point(20,50),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 0, 255, 0), 2, 4, 0); + cv::putText(osd_frame, text_dms_smoke_drink, cv::Point(20,100),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 0, 255, 0), 2, 4, 0); + } + + { + ScopedTiming st("osd copy", atoi(argv[10])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + // 显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id + 3, &vf_info); // K_VO_OSD0 + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } +} + +void video_proc_k230d(char *argv[]) +{ + vivcap_start(); + // 设置osd参数 + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + memset(&vf_info, 0, sizeof(vf_info)); + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory,get isp memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + FaceDetection fd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[10])); + HandDetection hd(argv[4], atof(argv[5]), atof(argv[6]), {SENSOR_WIDTH, SENSOR_HEIGHT}, {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[10])); + + vector face_results; + vector hand_results; + + float init_area = atof(argv[7]); + float init_len = atof(argv[8]); + float now_area; + float now_len; + int warning_amount = atoi(argv[9]); + int warning_count_smk_drk = 0; + int warning_count_drk = 0; + int warning_count_call = 0; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + { + ScopedTiming st("read capture", atoi(argv[10])); + // 从vivcap中读取一帧图像到dump_info + memset(&dump_info, 0, sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + { + ScopedTiming st("isp copy", atoi(argv[10])); + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + face_results.clear(); + fd.pre_process(); + fd.inference(); + // 旋转后图像 + fd.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, face_results); + + hand_results.clear(); + hd.pre_process(); + hd.inference(); + // 旋转后图像 + hd.post_process(hand_results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + float max_area_face = 0; + int max_id_face = -1; + for (int i = 0; i < face_results.size(); ++i) + { + float area_i = face_results[i].bbox.w * face_results[i].bbox.h; + if (area_i > max_area_face) + { + max_area_face = area_i; + max_id_face = i; + } + } + + float max_area_hand = 0; + int max_id_hand = -1; + for (int i = 0; i < hand_results.size(); ++i) + { + float area_i = (hand_results[i].x2 - hand_results[i].x1) * (hand_results[i].y2 - hand_results[i].y1); + if (area_i > max_area_hand) + { + max_area_hand = area_i; + max_id_hand = i; + } + } + + string text_dms_call = "Calling : No "; + string text_dms_smoke_drink = "Smoking or Drinking : No "; + if (max_id_face != -1 && max_id_hand != -1) + { + float face_x = face_results[max_id_face].bbox.x + (face_results[max_id_face].bbox.w / 2.0); + float face_y = face_results[max_id_face].bbox.y + (face_results[max_id_face].bbox.h / 2.0); + float hand_x = (hand_results[max_id_hand].x1 + hand_results[max_id_hand].x2) / 2.0; + float hand_y = (hand_results[max_id_hand].y1 + hand_results[max_id_hand].y2) / 2.0; + + now_area = max_area_face; + now_len = sqrt(pow(face_x - hand_x, 2) + pow(face_y - hand_y, 2)); + + if (now_len < (now_area / init_area) * init_len) + { + if (face_y < hand_y && (abs(face_y - hand_y) / abs(face_x - hand_x)) > 1) + { + warning_count_smk_drk += 1; + warning_count_drk = 0; + warning_count_call = 0; + } + else if (face_y > hand_y && (abs(face_y - hand_y) / abs(face_x - hand_x)) > 0.8) + { + warning_count_smk_drk = 0; + warning_count_drk += 1; + warning_count_call = 0; + } + else + { + warning_count_smk_drk = 0; + warning_count_drk = 0; + warning_count_call += 1; + } + + if (warning_count_smk_drk > warning_amount) + { + text_dms_smoke_drink = "Smoking or Drinking : Yes "; + cv::putText(osd_frame, text_dms_call, cv::Point(20,50),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 0, 255, 0), 2, 4, 0); + cv::putText(osd_frame, text_dms_smoke_drink, cv::Point(20,100),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 255, 0, 0), 2, 4, 0); + } + else if (warning_count_drk > warning_amount) + { + text_dms_smoke_drink = "Drinking : Yes "; + cv::putText(osd_frame, text_dms_call, cv::Point(20,50),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 0, 255, 0), 2, 4, 0); + cv::putText(osd_frame, text_dms_smoke_drink, cv::Point(20,100),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 255, 0, 0), 2, 4, 0); + } + else if (warning_count_call > warning_amount) + { + text_dms_call = "Calling : Yes "; + cv::putText(osd_frame, text_dms_call, cv::Point(20,50),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 255, 0, 0), 2, 4, 0); + cv::putText(osd_frame, text_dms_smoke_drink, cv::Point(20,100),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 0, 255, 0), 2, 4, 0); + } + else + { + cv::putText(osd_frame, text_dms_call, cv::Point(20,50),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 0, 255, 0), 2, 4, 0); + cv::putText(osd_frame, text_dms_smoke_drink, cv::Point(20,100),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 0, 255, 0), 2, 4, 0); + } + } + else + { + warning_count_smk_drk = 0; + warning_count_drk = 0; + warning_count_call = 0; + cv::putText(osd_frame, text_dms_call, cv::Point(20,50),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 0, 255, 0), 2, 4, 0); + cv::putText(osd_frame, text_dms_smoke_drink, cv::Point(20,100),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 0, 255, 0), 2, 4, 0); + } + + + int w = hand_results[max_id_hand].x2 - hand_results[max_id_hand].x1 + 1; + int h = hand_results[max_id_hand].y2 - hand_results[max_id_hand].y1 + 1; + + int rect_x = hand_results[max_id_hand].x1/ SENSOR_WIDTH * osd_frame.cols; + int rect_y = hand_results[max_id_hand].y1/ SENSOR_HEIGHT * osd_frame.rows; + int rect_w = (float)w / SENSOR_WIDTH * osd_frame.cols; + int rect_h = (float)h / SENSOR_HEIGHT * osd_frame.rows; + cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w, rect_h), cv::Scalar( 255, 0, 255, 255), 6, 2, 0); + } + else + { + warning_count_smk_drk = 0; + warning_count_drk = 0; + warning_count_call = 0; + cv::putText(osd_frame, text_dms_call, cv::Point(20,50),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 0, 255, 0), 2, 4, 0); + cv::putText(osd_frame, text_dms_smoke_drink, cv::Point(20,100),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 0, 255, 0), 2, 4, 0); + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[10])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + // 显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id + 3, &vf_info); // K_VO_OSD0 + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } +} + +void video_proc_01(char *argv[]) +{ + vivcap_start(); + // 设置osd参数 + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + memset(&vf_info, 0, sizeof(vf_info)); + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory,get isp memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + FaceDetection fd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[10])); + HandDetection hd(argv[4], atof(argv[5]), atof(argv[6]), {SENSOR_WIDTH, SENSOR_HEIGHT}, {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[10])); + + vector face_results; + vector hand_results; + + float init_area = atof(argv[7]); + float init_len = atof(argv[8]); + float now_area; + float now_len; + int warning_amount = atoi(argv[9]); + int warning_count_smk_drk = 0; + int warning_count_drk = 0; + int warning_count_call = 0; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + { + ScopedTiming st("read capture", atoi(argv[10])); + // 从vivcap中读取一帧图像到dump_info + memset(&dump_info, 0, sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + { + ScopedTiming st("isp copy", atoi(argv[10])); + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + face_results.clear(); + fd.pre_process(); + fd.inference(); + // 旋转后图像 + fd.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, face_results); + + hand_results.clear(); + hd.pre_process(); + hd.inference(); + // 旋转后图像 + hd.post_process(hand_results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + float max_area_face = 0; + int max_id_face = -1; + for (int i = 0; i < face_results.size(); ++i) + { + float area_i = face_results[i].bbox.w * face_results[i].bbox.h; + if (area_i > max_area_face) + { + max_area_face = area_i; + max_id_face = i; + } + } + + float max_area_hand = 0; + int max_id_hand = -1; + for (int i = 0; i < hand_results.size(); ++i) + { + float area_i = (hand_results[i].x2 - hand_results[i].x1) * (hand_results[i].y2 - hand_results[i].y1); + if (area_i > max_area_hand) + { + max_area_hand = area_i; + max_id_hand = i; + } + } + + string text_dms_call = "Calling : No "; + string text_dms_smoke_drink = "Smoking or Drinking : No "; + if (max_id_face != -1 && max_id_hand != -1) + { + float face_x = face_results[max_id_face].bbox.x + (face_results[max_id_face].bbox.w / 2.0); + float face_y = face_results[max_id_face].bbox.y + (face_results[max_id_face].bbox.h / 2.0); + float hand_x = (hand_results[max_id_hand].x1 + hand_results[max_id_hand].x2) / 2.0; + float hand_y = (hand_results[max_id_hand].y1 + hand_results[max_id_hand].y2) / 2.0; + + now_area = max_area_face; + now_len = sqrt(pow(face_x - hand_x, 2) + pow(face_y - hand_y, 2)); + + if (now_len < (now_area / init_area) * init_len) + { + if (face_y < hand_y && (abs(face_y - hand_y) / abs(face_x - hand_x)) > 1) + { + warning_count_smk_drk += 1; + warning_count_drk = 0; + warning_count_call = 0; + } + else if (face_y > hand_y && (abs(face_y - hand_y) / abs(face_x - hand_x)) > 0.8) + { + warning_count_smk_drk = 0; + warning_count_drk += 1; + warning_count_call = 0; + } + else + { + warning_count_smk_drk = 0; + warning_count_drk = 0; + warning_count_call += 1; + } + + if (warning_count_smk_drk > warning_amount) + { + text_dms_smoke_drink = "Smoking or Drinking : Yes "; + cv::putText(osd_frame, text_dms_call, cv::Point(20,50),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 0, 255, 0), 2, 4, 0); + cv::putText(osd_frame, text_dms_smoke_drink, cv::Point(20,100),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 255, 0, 0), 2, 4, 0); + } + else if (warning_count_drk > warning_amount) + { + text_dms_smoke_drink = "Drinking : Yes "; + cv::putText(osd_frame, text_dms_call, cv::Point(20,50),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 0, 255, 0), 2, 4, 0); + cv::putText(osd_frame, text_dms_smoke_drink, cv::Point(20,100),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 255, 0, 0), 2, 4, 0); + } + else if (warning_count_call > warning_amount) + { + text_dms_call = "Calling : Yes "; + cv::putText(osd_frame, text_dms_call, cv::Point(20,50),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 255, 0, 0), 2, 4, 0); + cv::putText(osd_frame, text_dms_smoke_drink, cv::Point(20,100),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 0, 255, 0), 2, 4, 0); + } + else + { + cv::putText(osd_frame, text_dms_call, cv::Point(20,50),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 0, 255, 0), 2, 4, 0); + cv::putText(osd_frame, text_dms_smoke_drink, cv::Point(20,100),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 0, 255, 0), 2, 4, 0); + } + } + else + { + warning_count_smk_drk = 0; + warning_count_drk = 0; + warning_count_call = 0; + cv::putText(osd_frame, text_dms_call, cv::Point(20,50),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 0, 255, 0), 2, 4, 0); + cv::putText(osd_frame, text_dms_smoke_drink, cv::Point(20,100),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 0, 255, 0), 2, 4, 0); + } + + + int w = hand_results[max_id_hand].x2 - hand_results[max_id_hand].x1 + 1; + int h = hand_results[max_id_hand].y2 - hand_results[max_id_hand].y1 + 1; + + int rect_x = hand_results[max_id_hand].x1/ SENSOR_WIDTH * osd_frame.cols; + int rect_y = hand_results[max_id_hand].y1/ SENSOR_HEIGHT * osd_frame.rows; + int rect_w = (float)w / SENSOR_WIDTH * osd_frame.cols; + int rect_h = (float)h / SENSOR_HEIGHT * osd_frame.rows; + cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w, rect_h), cv::Scalar( 255, 0, 255, 255), 6, 2, 0); + } + else + { + warning_count_smk_drk = 0; + warning_count_drk = 0; + warning_count_call = 0; + cv::putText(osd_frame, text_dms_call, cv::Point(20,50),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 0, 255, 0), 2, 4, 0); + cv::putText(osd_frame, text_dms_smoke_drink, cv::Point(20,100),cv::FONT_HERSHEY_COMPLEX, 1.5, cv::Scalar(255, 0, 255, 0), 2, 4, 0); + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[10])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + // 显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id + 3, &vf_info); // K_VO_OSD0 + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } +} + int main(int argc, char *argv[]) { std::cout << "case " << argv[0] << " built at " << __DATE__ << " " << __TIME__ << std::endl; @@ -271,13 +905,61 @@ int main(int argc, char *argv[]) print_usage(argv[0]); return -1; } - std::thread thread_isp(video_proc, argv); - while (getchar() != 'q') + #if defined(CONFIG_BOARD_K230_CANMV) + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_V2) + { + std::thread thread_isp(video_proc_v2, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230D_CANMV) + { + std::thread thread_isp(video_proc_k230d, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) { - usleep(10000); + std::thread thread_isp(video_proc_01, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); } + #else + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } - isp_stop = true; - thread_isp.join(); + isp_stop = true; + thread_isp.join(); + } + #endif return 0; } \ No newline at end of file diff --git a/src/reference/ai_poc/dms_system/vi_vo.h b/src/reference/ai_poc/dms_system/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/dms_system/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/dynamic_gesture/main.cc b/src/reference/ai_poc/dynamic_gesture/main.cc index 7e45f3f04..07ebe6b7b 100755 --- a/src/reference/ai_poc/dynamic_gesture/main.cc +++ b/src/reference/ai_poc/dynamic_gesture/main.cc @@ -125,7 +125,19 @@ void video_proc(char *argv[]) } cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); - + #if defined(CONFIG_BOARD_K230D_CANMV) + { + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + } + #else + { + } + #endif + if (cur_state_== TRIGGER) { ScopedTiming st("trigger time", atoi(argv[6])); @@ -388,30 +400,89 @@ void video_proc(char *argv[]) s_stop = std::chrono::steady_clock::now(); double elapsed_ms_show = std::chrono::duration(s_stop - s_start).count(); - if (elapsed_ms_show<1000) + + + #if defined(CONFIG_BOARD_K230D_CANMV) { - - if (draw_state_ == UP) + if (elapsed_ms_show<1000) { - cv::putText(osd_frame, "UP", cv::Point(osd_width*3/7,osd_height/2),cv::FONT_HERSHEY_COMPLEX, 5, cv::Scalar(255, 255, 195, 0), 2); - } else if (draw_state_ == RIGHT) - { - cv::putText(osd_frame, "LEFT", cv::Point(osd_width*3/7,osd_height/2),cv::FONT_HERSHEY_COMPLEX, 5, cv::Scalar(255, 255, 195, 0), 2); - }else if (draw_state_ == DOWN) + if (draw_state_ == UP) + { + cv::putText(osd_frame, "UP", cv::Point(osd_height * 3/7, osd_width/2),cv::FONT_HERSHEY_COMPLEX, 3, cv::Scalar(255, 255, 195, 0), 2); + } else if (draw_state_ == RIGHT) + { + cv::putText(osd_frame, "LEFT", cv::Point(osd_height * 3/7, osd_width/2),cv::FONT_HERSHEY_COMPLEX, 3, cv::Scalar(255, 255, 195, 0), 2); + }else if (draw_state_ == DOWN) + { + cv::putText(osd_frame, "DOWN", cv::Point(osd_height * 3/7, osd_width/2),cv::FONT_HERSHEY_COMPLEX, 3, cv::Scalar(255, 255, 195, 0), 2); + }else if (draw_state_ == LEFT) + { + cv::putText(osd_frame, "RIGHT", cv::Point(osd_height * 3/7, osd_width/2),cv::FONT_HERSHEY_COMPLEX, 3, cv::Scalar(255, 255, 195, 0), 2); + }else if (draw_state_ == MIDDLE) + { + cv::putText(osd_frame, "MIDDLE", cv::Point(osd_height * 3/7, osd_width/2),cv::FONT_HERSHEY_COMPLEX, 3, cv::Scalar(255, 255, 195, 0), 2); + } + + }else { - cv::putText(osd_frame, "DOWN", cv::Point(osd_width*3/7,osd_height/2),cv::FONT_HERSHEY_COMPLEX, 5, cv::Scalar(255, 255, 195, 0), 2); - }else if (draw_state_ == LEFT) + draw_state_ = TRIGGER; + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + if (elapsed_ms_show<1000) { - cv::putText(osd_frame, "RIGHT", cv::Point(osd_width*3/7,osd_height/2),cv::FONT_HERSHEY_COMPLEX, 5, cv::Scalar(255, 255, 195, 0), 2); - }else if (draw_state_ == MIDDLE) + if (draw_state_ == UP) + { + cv::putText(osd_frame, "UP", cv::Point(osd_height * 3/7, osd_width/2),cv::FONT_HERSHEY_COMPLEX, 3, cv::Scalar(255, 255, 195, 0), 2); + } else if (draw_state_ == RIGHT) + { + cv::putText(osd_frame, "LEFT", cv::Point(osd_height * 3/7, osd_width/2),cv::FONT_HERSHEY_COMPLEX, 3, cv::Scalar(255, 255, 195, 0), 2); + }else if (draw_state_ == DOWN) + { + cv::putText(osd_frame, "DOWN", cv::Point(osd_height * 3/7, osd_width/2),cv::FONT_HERSHEY_COMPLEX, 3, cv::Scalar(255, 255, 195, 0), 2); + }else if (draw_state_ == LEFT) + { + cv::putText(osd_frame, "RIGHT", cv::Point(osd_height * 3/7, osd_width/2),cv::FONT_HERSHEY_COMPLEX, 3, cv::Scalar(255, 255, 195, 0), 2); + }else if (draw_state_ == MIDDLE) + { + cv::putText(osd_frame, "MIDDLE", cv::Point(osd_height * 3/7, osd_width/2),cv::FONT_HERSHEY_COMPLEX, 3, cv::Scalar(255, 255, 195, 0), 2); + } + + }else { - cv::putText(osd_frame, "MIDDLE", cv::Point(osd_width*3/7,osd_height/2),cv::FONT_HERSHEY_COMPLEX, 5, cv::Scalar(255, 255, 195, 0), 2); + draw_state_ = TRIGGER; } - - }else + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #else { - draw_state_ = TRIGGER; + if (elapsed_ms_show<1000) + { + if (draw_state_ == UP) + { + cv::putText(osd_frame, "UP", cv::Point(osd_width*3/7,osd_height/2),cv::FONT_HERSHEY_COMPLEX, 5, cv::Scalar(255, 255, 195, 0), 2); + } else if (draw_state_ == RIGHT) + { + cv::putText(osd_frame, "LEFT", cv::Point(osd_width*3/7,osd_height/2),cv::FONT_HERSHEY_COMPLEX, 5, cv::Scalar(255, 255, 195, 0), 2); + }else if (draw_state_ == DOWN) + { + cv::putText(osd_frame, "DOWN", cv::Point(osd_width*3/7,osd_height/2),cv::FONT_HERSHEY_COMPLEX, 5, cv::Scalar(255, 255, 195, 0), 2); + }else if (draw_state_ == LEFT) + { + cv::putText(osd_frame, "RIGHT", cv::Point(osd_width*3/7,osd_height/2),cv::FONT_HERSHEY_COMPLEX, 5, cv::Scalar(255, 255, 195, 0), 2); + }else if (draw_state_ == MIDDLE) + { + cv::putText(osd_frame, "MIDDLE", cv::Point(osd_width*3/7,osd_height/2),cv::FONT_HERSHEY_COMPLEX, 5, cv::Scalar(255, 255, 195, 0), 2); + } + + }else + { + draw_state_ = TRIGGER; + } } + #endif { ScopedTiming st("osd copy", atoi(argv[6])); diff --git a/src/reference/ai_poc/dynamic_gesture/vi_vo.h b/src/reference/ai_poc/dynamic_gesture/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/dynamic_gesture/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/eye_gaze/main.cc b/src/reference/ai_poc/eye_gaze/main.cc index 938743e2a..efe9a39a8 100644 --- a/src/reference/ai_poc/eye_gaze/main.cc +++ b/src/reference/ai_poc/eye_gaze/main.cc @@ -114,7 +114,26 @@ void video_proc(char *argv[]) EyeGazeInfo gaze_result; eye_gaze.post_process(gaze_result); - eye_gaze.draw_result(osd_frame,det_results[i].bbox,gaze_result,false); + #if defined(CONFIG_BOARD_K230D_CANMV) + { + ScopedTiming st("osd draw", atoi(argv[6])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + eye_gaze.draw_result(osd_frame,det_results[i].bbox,gaze_result,false); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + ScopedTiming st("osd draw", atoi(argv[6])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + eye_gaze.draw_result(osd_frame,det_results[i].bbox,gaze_result,false); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #else + { + ScopedTiming st("osd draw", atoi(argv[6])); + eye_gaze.draw_result(osd_frame,det_results[i].bbox,gaze_result,false); + } + #endif } { diff --git a/src/reference/ai_poc/eye_gaze/vi_vo.h b/src/reference/ai_poc/eye_gaze/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/eye_gaze/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/face_alignment/face_alignment.cc b/src/reference/ai_poc/face_alignment/face_alignment.cc index ee0d5db1d..45b409f2b 100755 --- a/src/reference/ai_poc/face_alignment/face_alignment.cc +++ b/src/reference/ai_poc/face_alignment/face_alignment.cc @@ -90,7 +90,7 @@ void FaceAlignment::inference() this->get_output(); } -void FaceAlignment::post_process(FrameSize frame_size,vector& vertices) +void FaceAlignment::post_process(FrameSize frame_size,vector& vertices, bool pic_mode) { ScopedTiming st(model_name_ + " post_process", debug_mode_); vector param(p_outputs_[0],p_outputs_[0] + output_shapes_[0][1]); @@ -100,11 +100,14 @@ void FaceAlignment::post_process(FrameSize frame_size,vector& vertices) post_obj_.inference(); post_obj_.post_process(vertices); - //因为要在osd上画图，故需要把返回值变换到osd的长、宽 - roi.x0 = roi.x0 / isp_shape_.width * frame_size.width; - roi.y0 = roi.y0 / isp_shape_.height * frame_size.height; - roi.x1 = roi.x1 / isp_shape_.width * frame_size.width; - roi.y1 = roi.y1 / isp_shape_.height * frame_size.height; + if (pic_mode==false) + { + //因为要在osd上画图，故需要把返回值变换到osd的长、宽 + roi.x0 = roi.x0 / isp_shape_.width * frame_size.width; + roi.y0 = roi.y0 / isp_shape_.height * frame_size.height; + roi.x1 = roi.x1 / isp_shape_.width * frame_size.width; + roi.y1 = roi.y1 / isp_shape_.height * frame_size.height; + } recon_vers(roi, vertices); } @@ -117,6 +120,7 @@ void FaceAlignment::constant_init() /*************************前处理********************/ LeftTopRightBottom FaceAlignment::parse_roi_box_from_bbox(FrameSize frame_size,Bbox& b,Bbox& roi_b) { + ScopedTiming st(model_name_ + " parse_roi_box_from_bbox", debug_mode_); float old_size = ( b.w + b.h) / 2; float center_x = b.x + b.w / 2; float center_y = b.y + b.h / 2 + old_size * 0.14; @@ -142,6 +146,7 @@ LeftTopRightBottom FaceAlignment::parse_roi_box_from_bbox(FrameSize frame_size,B /*************************后处理********************/ void FaceAlignment::get_depth(cv::Mat &img, vector& vertices) { + ScopedTiming st(model_name_ + " get_depth", debug_mode_); vector z(post_ver_dim_ * 3); vector ver(post_ver_dim_ * 3); @@ -178,6 +183,7 @@ void FaceAlignment::get_depth(cv::Mat &img, vector& vertices) void FaceAlignment::get_pncc(cv::Mat &img,vector& vertices) { + ScopedTiming st(model_name_ + " get_pncc", debug_mode_); //rendering pncc vector ver(post_ver_dim_ * 3); int row = 0, col = 0, end_ver = 3 * post_ver_dim_; @@ -193,6 +199,7 @@ void FaceAlignment::get_pncc(cv::Mat &img,vector& vertices) void FaceAlignment::param_normalized(vector& param) { + ScopedTiming st(model_name_ + " param_normalized", debug_mode_); for (int param_index = 0; param_index < param.size(); ++param_index) { param[param_index] = param[param_index] * param_std[param_index] + param_mean[param_index]; @@ -201,11 +208,13 @@ void FaceAlignment::param_normalized(vector& param) void FaceAlignment::recon_vers(LeftTopRightBottom& roi_box_lst,vector &vertices) { + ScopedTiming st(model_name_ + " recon_vers", debug_mode_); similar_transform(roi_box_lst,vertices); } void FaceAlignment::similar_transform(LeftTopRightBottom& roi_box,vector &vertices) { + ScopedTiming st(model_name_ + " similar_transform", debug_mode_); double scale_x = (roi_box.x1 - roi_box.x0) / input_shapes_[0][3]; double scale_y = (roi_box.y1 - roi_box.y0) / input_shapes_[0][3]; double s = (scale_x + scale_y) / 2; @@ -259,6 +268,7 @@ void FaceAlignment::similar_transform(LeftTopRightBottom& roi_box,vector void FaceAlignment::rasterize(cv::Mat& img, vector& vertices,vector &colors,float alpha, bool reverse) { + ScopedTiming st(model_name_ + " rasterize", debug_mode_); vector buffer(img.cols*img.rows,-1e8); _rasterize(img.data, vertices.data(), bfm_tri.data(), colors.data(), buffer.data(), bfm_tri.size()/3, img.rows, img.cols, img.channels(), alpha, reverse); } diff --git a/src/reference/ai_poc/face_alignment/face_alignment.h b/src/reference/ai_poc/face_alignment/face_alignment.h index c5821b089..09edfd3cd 100755 --- a/src/reference/ai_poc/face_alignment/face_alignment.h +++ b/src/reference/ai_poc/face_alignment/face_alignment.h @@ -109,9 +109,10 @@ class FaceAlignment : public AIBase * @brief kmodel推理结果后处理 * @param frame_size 原始图像/帧宽高，用于将结果放到原始图像大小 * @param vertices 后处理后3d点 + * @param pic_mode ture(原图片)，false(osd) * @return None */ - void post_process(FrameSize frame_size, vector& vertices); + void post_process(FrameSize frame_size, vector& vertices, bool pic_mode); /** * @brief 获取深度图 diff --git a/src/reference/ai_poc/face_alignment/face_detection.cc b/src/reference/ai_poc/face_alignment/face_detection.cc index e3d83c567..160458692 100755 --- a/src/reference/ai_poc/face_alignment/face_detection.cc +++ b/src/reference/ai_poc/face_alignment/face_detection.cc @@ -138,14 +138,6 @@ void FaceDetection::pre_process() hrt::sync(ai2d_in_tensor_, sync_op_t::sync_write_back, true).expect("sync write_back failed"); ai2d_builder_->invoke(ai2d_in_tensor_,ai2d_out_tensor_).expect("error occurred in ai2d running"); #endif - static int aa = 0; - if(aa==50) - { - auto vaddr_out_buf = ai2d_in_tensor_.impl()->to_host().unwrap()->buffer().as_host().unwrap().map(map_access_::map_read).unwrap().buffer(); - unsigned char *output = reinterpret_cast(vaddr_out_buf.data()); - Utils::dump_color_image("FaceDetection_input_ori_50.png",{isp_shape_.width,isp_shape_.height},output); - } - aa += 1; } void FaceDetection::inference() diff --git a/src/reference/ai_poc/face_alignment/main.cc b/src/reference/ai_poc/face_alignment/main.cc index 4e658db98..a9998d7ce 100644 --- a/src/reference/ai_poc/face_alignment/main.cc +++ b/src/reference/ai_poc/face_alignment/main.cc @@ -117,11 +117,36 @@ void video_proc(char *argv[]) face_align.pre_process(det_results[i].bbox); face_align.inference(); vector vertices; - face_align.post_process({osd_width, osd_height},vertices); - if(output_mode == "depth") - face_align.get_depth(osd_frame, vertices); - else if(output_mode == "pncc") - face_align.get_pncc(osd_frame, vertices); + face_align.post_process({osd_width, osd_height},vertices,false); + #if defined(CONFIG_BOARD_K230D_CANMV) + { + ScopedTiming st("osd draw", atoi(argv[8])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + if(output_mode == "depth") + face_align.get_depth(osd_frame, vertices); + else if(output_mode == "pncc") + face_align.get_pncc(osd_frame, vertices); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + ScopedTiming st("osd draw", atoi(argv[8])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + if(output_mode == "depth") + face_align.get_depth(osd_frame, vertices); + else if(output_mode == "pncc") + face_align.get_pncc(osd_frame, vertices); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #else + { + ScopedTiming st("osd draw", atoi(argv[8])); + if(output_mode == "depth") + face_align.get_depth(osd_frame, vertices); + else if(output_mode == "pncc") + face_align.get_pncc(osd_frame, vertices); + } + #endif } { @@ -188,7 +213,7 @@ int main(int argc, char *argv[]) face_align.pre_process(ori_img, det_results[i].bbox); face_align.inference(); vector vertices; - face_align.post_process({ori_w, ori_h},vertices); + face_align.post_process({ori_w, ori_h},vertices,true); if(output_mode == "depth") face_align.get_depth(ori_img, vertices); else if(output_mode == "pncc") diff --git a/src/reference/ai_poc/face_alignment/vi_vo.h b/src/reference/ai_poc/face_alignment/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/face_alignment/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/face_detection/main.cc b/src/reference/ai_poc/face_detection/main.cc index 78ac8354b..3f9aeeb30 100644 --- a/src/reference/ai_poc/face_detection/main.cc +++ b/src/reference/ai_poc/face_detection/main.cc @@ -103,11 +103,26 @@ void video_proc(char *argv[]) fd.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); - + #if defined(CONFIG_BOARD_K230D_CANMV) + { + ScopedTiming st("osd draw", atoi(argv[5])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + fd.draw_result(osd_frame,results,false); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + ScopedTiming st("osd draw", atoi(argv[5])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + fd.draw_result(osd_frame,results,false); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #else { ScopedTiming st("osd draw", atoi(argv[5])); fd.draw_result(osd_frame,results,false); } + #endif { ScopedTiming st("osd copy", atoi(argv[5])); diff --git a/src/reference/ai_poc/face_detection/vi_vo.h b/src/reference/ai_poc/face_detection/vi_vo.h deleted file mode 100644 index 15f0bc111..000000000 --- a/src/reference/ai_poc/face_detection/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/face_emotion/main.cc b/src/reference/ai_poc/face_emotion/main.cc index 4cca40ec2..74ba0ac2a 100644 --- a/src/reference/ai_poc/face_emotion/main.cc +++ b/src/reference/ai_poc/face_emotion/main.cc @@ -114,8 +114,28 @@ void video_proc(char *argv[]) face_emo.inference(); FaceEmotionInfo emo_result; - face_emo.post_process(emo_result); - face_emo.draw_result(osd_frame,det_results[i].bbox,emo_result,false); + face_emo.post_process(emo_result); + #if defined(CONFIG_BOARD_K230D_CANMV) + { + ScopedTiming st("osd draw", atoi(argv[6])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + face_emo.draw_result(osd_frame,det_results[i].bbox,emo_result,false); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + ScopedTiming st("osd draw", atoi(argv[6])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + face_emo.draw_result(osd_frame,det_results[i].bbox,emo_result,false); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #else + { + ScopedTiming st("osd draw", atoi(argv[6])); + face_emo.draw_result(osd_frame,det_results[i].bbox,emo_result,false); + } + #endif + } { diff --git a/src/reference/ai_poc/face_emotion/vi_vo.h b/src/reference/ai_poc/face_emotion/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/face_emotion/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/face_gender/main.cc b/src/reference/ai_poc/face_gender/main.cc index 48c76c9d1..9af713340 100644 --- a/src/reference/ai_poc/face_gender/main.cc +++ b/src/reference/ai_poc/face_gender/main.cc @@ -113,7 +113,26 @@ void video_proc(char *argv[]) fa.pre_process(det_results[i].bbox); fa.inference(); fa.post_process(fa_result); - fa.draw_result(osd_frame,det_results[i].bbox,fa_result,false); + #if defined(CONFIG_BOARD_K230D_CANMV) + { + ScopedTiming st("osd draw", atoi(argv[6])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + fa.draw_result(osd_frame,det_results[i].bbox,fa_result,false); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + ScopedTiming st("osd draw", atoi(argv[6])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + fa.draw_result(osd_frame,det_results[i].bbox,fa_result,false); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #else + { + ScopedTiming st("osd draw", atoi(argv[6])); + fa.draw_result(osd_frame,det_results[i].bbox,fa_result,false); + } + #endif } { diff --git a/src/reference/ai_poc/face_gender/vi_vo.h b/src/reference/ai_poc/face_gender/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/face_gender/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/face_glasses/main.cc b/src/reference/ai_poc/face_glasses/main.cc index 209c90cb9..0c3fb097b 100644 --- a/src/reference/ai_poc/face_glasses/main.cc +++ b/src/reference/ai_poc/face_glasses/main.cc @@ -113,7 +113,26 @@ void video_proc(char *argv[]) fg.pre_process(det_results[i].sparse_kps.points); fg.inference(); fg.post_process(fg_result); - fg.draw_result(osd_frame,det_results[i].bbox,fg_result,false); + #if defined(CONFIG_BOARD_K230D_CANMV) + { + ScopedTiming st("osd draw", atoi(argv[6])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + fg.draw_result(osd_frame,det_results[i].bbox,fg_result,false); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + ScopedTiming st("osd draw", atoi(argv[6])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + fg.draw_result(osd_frame,det_results[i].bbox,fg_result,false); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #else + { + ScopedTiming st("osd draw", atoi(argv[6])); + fg.draw_result(osd_frame,det_results[i].bbox,fg_result,false); + } + #endif } { diff --git a/src/reference/ai_poc/face_glasses/vi_vo.h b/src/reference/ai_poc/face_glasses/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/face_glasses/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/face_landmark/main.cc b/src/reference/ai_poc/face_landmark/main.cc index e08979847..7250da445 100644 --- a/src/reference/ai_poc/face_landmark/main.cc +++ b/src/reference/ai_poc/face_landmark/main.cc @@ -107,13 +107,31 @@ void video_proc(char *argv[]) fd.inference(); fd.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); - // fd.draw_result(osd_frame,results,false); for (int i = 0; i < results.size(); ++i) { fkp.pre_process(results[i].bbox); fkp.inference(); fkp.post_process(); - fkp.draw_contour(osd_frame,false); + #if defined(CONFIG_BOARD_K230D_CANMV) + { + ScopedTiming st("osd draw", atoi(argv[6])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + fkp.draw_contour(osd_frame,false); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + ScopedTiming st("osd draw", atoi(argv[6])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + fkp.draw_contour(osd_frame,false); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #else + { + ScopedTiming st("osd draw", atoi(argv[6])); + fkp.draw_contour(osd_frame,false); + } + #endif } { diff --git a/src/reference/ai_poc/face_landmark/vi_vo.h b/src/reference/ai_poc/face_landmark/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/face_landmark/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/face_mask/main.cc b/src/reference/ai_poc/face_mask/main.cc index 86eb8bbf9..019943a66 100644 --- a/src/reference/ai_poc/face_mask/main.cc +++ b/src/reference/ai_poc/face_mask/main.cc @@ -114,7 +114,26 @@ void video_proc(char *argv[]) fm.pre_process(det_results[i].sparse_kps.points); fm.inference(); fm.post_process(fm_result); - fm.draw_result(osd_frame,det_results[i].bbox,fm_result,false); + #if defined(CONFIG_BOARD_K230D_CANMV) + { + ScopedTiming st("osd draw", atoi(argv[7])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + fm.draw_result(osd_frame,det_results[i].bbox,fm_result,false); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + ScopedTiming st("osd draw", atoi(argv[7])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + fm.draw_result(osd_frame,det_results[i].bbox,fm_result,false); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #else + { + ScopedTiming st("osd draw", atoi(argv[7])); + fm.draw_result(osd_frame,det_results[i].bbox,fm_result,false); + } + #endif } { diff --git a/src/reference/ai_poc/face_mask/vi_vo.h b/src/reference/ai_poc/face_mask/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/face_mask/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/face_mesh/face_detection.cc b/src/reference/ai_poc/face_mesh/face_detection.cc index e3d83c567..160458692 100755 --- a/src/reference/ai_poc/face_mesh/face_detection.cc +++ b/src/reference/ai_poc/face_mesh/face_detection.cc @@ -138,14 +138,6 @@ void FaceDetection::pre_process() hrt::sync(ai2d_in_tensor_, sync_op_t::sync_write_back, true).expect("sync write_back failed"); ai2d_builder_->invoke(ai2d_in_tensor_,ai2d_out_tensor_).expect("error occurred in ai2d running"); #endif - static int aa = 0; - if(aa==50) - { - auto vaddr_out_buf = ai2d_in_tensor_.impl()->to_host().unwrap()->buffer().as_host().unwrap().map(map_access_::map_read).unwrap().buffer(); - unsigned char *output = reinterpret_cast(vaddr_out_buf.data()); - Utils::dump_color_image("FaceDetection_input_ori_50.png",{isp_shape_.width,isp_shape_.height},output); - } - aa += 1; } void FaceDetection::inference() diff --git a/src/reference/ai_poc/face_mesh/main.cc b/src/reference/ai_poc/face_mesh/main.cc index db4c65bec..7743df63e 100644 --- a/src/reference/ai_poc/face_mesh/main.cc +++ b/src/reference/ai_poc/face_mesh/main.cc @@ -116,7 +116,26 @@ void video_proc(char *argv[]) face_mesh.inference(); vector vertices; face_mesh.post_process({osd_width, osd_height},vertices,false); - face_mesh.get_mesh(osd_frame,vertices,false); + #if defined(CONFIG_BOARD_K230D_CANMV) + { + ScopedTiming st("osd draw", atoi(argv[7])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + face_mesh.get_mesh(osd_frame,vertices,false); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + ScopedTiming st("osd draw", atoi(argv[7])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + face_mesh.get_mesh(osd_frame,vertices,false); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #else + { + ScopedTiming st("osd draw", atoi(argv[7])); + face_mesh.get_mesh(osd_frame,vertices,false); + } + #endif } { diff --git a/src/reference/ai_poc/face_mesh/vi_vo.h b/src/reference/ai_poc/face_mesh/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/face_mesh/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/face_parse/main.cc b/src/reference/ai_poc/face_parse/main.cc index 4221849de..08de6fb10 100644 --- a/src/reference/ai_poc/face_parse/main.cc +++ b/src/reference/ai_poc/face_parse/main.cc @@ -109,7 +109,26 @@ void video_proc(char *argv[]) { fpa.pre_process(det_results[i].bbox); fpa.inference(); - fpa.post_process(osd_frame,det_results[i].bbox,false); + #if defined(CONFIG_BOARD_K230D_CANMV) + { + ScopedTiming st("osd draw", atoi(argv[6])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + fpa.post_process(osd_frame,det_results[i].bbox,false); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + ScopedTiming st("osd draw", atoi(argv[6])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + fpa.post_process(osd_frame,det_results[i].bbox,false); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #else + { + ScopedTiming st("osd draw", atoi(argv[6])); + fpa.post_process(osd_frame,det_results[i].bbox,false); + } + #endif } { diff --git a/src/reference/ai_poc/face_parse/vi_vo.h b/src/reference/ai_poc/face_parse/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/face_parse/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/face_pose/main.cc b/src/reference/ai_poc/face_pose/main.cc index d7b100045..3ae4d3b72 100755 --- a/src/reference/ai_poc/face_pose/main.cc +++ b/src/reference/ai_poc/face_pose/main.cc @@ -114,10 +114,26 @@ void video_proc(char *argv[]) fp.pre_process(det_results[i].bbox); fp.inference(); fp.post_process(pose_result); + #if defined(CONFIG_BOARD_K230D_CANMV) { ScopedTiming st("osd draw", atoi(argv[6])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); fp.draw_result(osd_frame,det_results[i].bbox,pose_result,false); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + ScopedTiming st("osd draw", atoi(argv[6])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + fp.draw_result(osd_frame,det_results[i].bbox,pose_result,false); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #else + { + ScopedTiming st("osd draw", atoi(argv[6])); + fp.draw_result(osd_frame,det_results[i].bbox,pose_result,false); + } + #endif } { diff --git a/src/reference/ai_poc/face_pose/vi_vo.h b/src/reference/ai_poc/face_pose/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/face_pose/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/face_verification/vi_vo.h b/src/reference/ai_poc/face_verification/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/face_verification/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/falldown_detect/main.cc b/src/reference/ai_poc/falldown_detect/main.cc index f076ea8b4..db47f47ee 100644 --- a/src/reference/ai_poc/falldown_detect/main.cc +++ b/src/reference/ai_poc/falldown_detect/main.cc @@ -51,7 +51,7 @@ void print_usage(const char *name) << endl; } -void video_proc(char *argv[]) +void video_proc_v1(char *argv[]) { vivcap_start(); @@ -172,6 +172,373 @@ void video_proc(char *argv[]) } +void video_proc_v2(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + falldownDetect fdd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + + fdd.pre_process(); + fdd.inference(); + fdd.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + + std::string text; + cv::Point origin; + std::vector scalars= { + cv::Scalar(255,0, 0, 255), // "Fall" + cv::Scalar(255,0, 255, 0), // "NoFall" + cv::Scalar(255,255,0, 0), + cv::Scalar(255,255,0, 255) + }; + + for (auto r : results) + { + ScopedTiming st("draw boxes", atoi(argv[5])); + text = fdd.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); + std::cout << "text = " << text << std::endl; + + int x1 = r.x1 / SENSOR_WIDTH * osd_width; + int y1 = r.y1 / SENSOR_HEIGHT * osd_height; + + origin.x = x1; + origin.y = y1-20; + + int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_width; + int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_height; + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), scalars[r.label], 6, 2, 0); // ARGB + cv::putText(osd_frame, text, origin, cv::FONT_HERSHEY_COMPLEX, 2, scalars[r.label+2], 1, 8, 0); + + + } + + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_k230d(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + falldownDetect fdd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + + fdd.pre_process(); + fdd.inference(); + fdd.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + std::string text; + cv::Point origin; + std::vector scalars= { + cv::Scalar(255,0, 0, 255), // "Fall" + cv::Scalar(255,0, 255, 0), // "NoFall" + cv::Scalar(255,255,0, 0), + cv::Scalar(255,255,0, 255) + }; + + for (auto r : results) + { + ScopedTiming st("draw boxes", atoi(argv[5])); + text = fdd.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); + std::cout << "text = " << text << std::endl; + + int x1 = r.x1 / SENSOR_WIDTH * osd_frame.cols; + int y1 = r.y1 / SENSOR_HEIGHT * osd_frame.rows; + + origin.x = x1; + origin.y = y1-20; + + int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_frame.cols; + int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_frame.rows; + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), scalars[r.label], 6, 2, 0); // ARGB + cv::putText(osd_frame, text, origin, cv::FONT_HERSHEY_COMPLEX, 2, scalars[r.label+2], 1, 8, 0); + + + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_01(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + falldownDetect fdd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + + fdd.pre_process(); + fdd.inference(); + fdd.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + std::string text; + cv::Point origin; + std::vector scalars= { + cv::Scalar(255,0, 0, 255), // "Fall" + cv::Scalar(255,0, 255, 0), // "NoFall" + cv::Scalar(255,255,0, 0), + cv::Scalar(255,255,0, 255) + }; + + for (auto r : results) + { + ScopedTiming st("draw boxes", atoi(argv[5])); + text = fdd.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); + std::cout << "text = " << text << std::endl; + + int x1 = r.x1 / SENSOR_WIDTH * osd_frame.cols; + int y1 = r.y1 / SENSOR_HEIGHT * osd_frame.rows; + + origin.x = x1; + origin.y = y1-20; + + int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_frame.cols; + int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_frame.rows; + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), scalars[r.label], 6, 2, 0); // ARGB + cv::putText(osd_frame, text, origin, cv::FONT_HERSHEY_COMPLEX, 2, scalars[r.label+2], 1, 8, 0); + + + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + int main(int argc, char *argv[]) { @@ -184,14 +551,62 @@ int main(int argc, char *argv[]) if (strcmp(argv[4], "None") == 0) { - std::thread thread_isp(video_proc, argv); - while (getchar() != 'q') + #if defined(CONFIG_BOARD_K230_CANMV) { - usleep(10000); + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); } + #elif defined(CONFIG_BOARD_K230_CANMV_V2) + { + std::thread thread_isp(video_proc_v2, argv); + while (getchar() != 'q') + { + usleep(10000); + } - isp_stop = true; - thread_isp.join(); + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230D_CANMV) + { + std::thread thread_isp(video_proc_k230d, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + std::thread thread_isp(video_proc_01, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #else + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #endif } else { diff --git a/src/reference/ai_poc/falldown_detect/vi_vo.h b/src/reference/ai_poc/falldown_detect/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/falldown_detect/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/finger_guessing/main.cc b/src/reference/ai_poc/finger_guessing/main.cc index d926487c0..bf48f7692 100644 --- a/src/reference/ai_poc/finger_guessing/main.cc +++ b/src/reference/ai_poc/finger_guessing/main.cc @@ -50,7 +50,7 @@ void print_usage(const char *name) } -void video_proc(char *argv[]) +void video_proc_v1(char *argv[]) { vivcap_start(); // 设置osd参数 @@ -375,6 +375,986 @@ void video_proc(char *argv[]) } } +void video_proc_v2(char *argv[]) +{ + vivcap_start(); + // 设置osd参数 + k_video_frame_info vf_info; + void *pic_vaddr = NULL; // osd + memset(&vf_info, 0, sizeof(vf_info)); + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory,get isp memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + // 读取石头剪刀布的bin文件数据 并且转换为mat类型 + int bu_width = 400; + int bu_height = 400; + cv::Mat image_bu_argb; + Utils::bin_2_mat("bu.bin", bu_width, bu_height, image_bu_argb); + + int shitou_width = 400; + int shitou_height = 400; + cv::Mat image_shitou_argb; + Utils::bin_2_mat("shitou.bin", shitou_width, shitou_height, image_shitou_argb); + + int jiandao_width = 400; + int jiandao_height = 400; + cv::Mat image_jiandao_argb; + Utils::bin_2_mat("jiandao.bin", jiandao_width, jiandao_height, image_jiandao_argb); + + // 设置游戏模式 + static int MODE = atoi(argv[5]); + int counts_guess = -1; + int player_win = 0; + int k230_win = 0; + bool sleep_end = false; + bool set_stop_id = true; + std::vector LIBRARY = {"fist","yeah","five"}; + + HandDetection hd(argv[1], atof(argv[2]), atof(argv[3]), {SENSOR_WIDTH, SENSOR_HEIGHT}, {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[6])); + sync(); + HandKeypoint hk(argv[4], {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[6])); + sync(); + + cv::Mat osd_frame_tmp(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + std::vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + { + ScopedTiming st("read capture", atoi(argv[6])); + // 从vivcap中读取一帧图像到dump_info + memset(&dump_info, 0, sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + { + ScopedTiming st("isp copy", atoi(argv[6])); + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); + kd_mpi_sys_munmap(vbvaddr, size); + } + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::Mat osd_frame_out;//(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::Mat osd_frame_vertical; + cv::Mat osd_frame_horizontal; + + results.clear(); + hd.pre_process(); + hd.inference(); + hd.post_process(results); + + float max_area_hand = 0; + int max_id_hand = -1; + for (int i = 0; i < results.size(); ++i) + { + float area_i = (results[i].x2 - results[i].x1) * (results[i].y2 - results[i].y1); + if (area_i > max_area_hand) + { + max_area_hand = area_i; + max_id_hand = i; + } + } + + std::string gesture = ""; + if (max_id_hand != -1) + { + std::string text = hd.labels_[results[max_id_hand].label] + ":" + std::to_string(round(results[max_id_hand].score * 100) / 100.0); + + int w = results[max_id_hand].x2 - results[max_id_hand].x1 + 1; + int h = results[max_id_hand].y2 - results[max_id_hand].y1 + 1; + + int rect_x = results[max_id_hand].x1/ SENSOR_WIDTH * osd_width; + int rect_y = results[max_id_hand].y1/ SENSOR_HEIGHT * osd_height; + int rect_w = (float)w / SENSOR_WIDTH * osd_width; + int rect_h = (float)h / SENSOR_HEIGHT * osd_height; + // cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w, rect_h), cv::Scalar( 255,255, 255, 255), 2, 2, 0); + + int length = std::max(w,h)/2; + int cx = (results[max_id_hand].x1+results[max_id_hand].x2)/2; + int cy = (results[max_id_hand].y1+results[max_id_hand].y2)/2; + int ratio_num = 1.26*length; + + int x1_1 = std::max(0,cx-ratio_num); + int y1_1 = std::max(0,cy-ratio_num); + int x2_1 = std::min(SENSOR_WIDTH-1, cx+ratio_num); + int y2_1 = std::min(SENSOR_HEIGHT-1, cy+ratio_num); + int w_1 = x2_1 - x1_1 + 1; + int h_1 = y2_1 - y1_1 + 1; + + struct Bbox bbox = {x:x1_1,y:y1_1,w:w_1,h:h_1}; + hk.pre_process(bbox); + + hk.inference(); + + hk.post_process(bbox); + + std::vector angle_list = hk.hand_angle(); + gesture = hk.h_gesture(angle_list); + + std::string text1 = "Gesture: " + gesture; + } + + + if(MODE == 0) + { + { + ScopedTiming st("osd draw", atoi(argv[6])); + + if(gesture == "fist") + { + cv::Mat copy_ori_image = osd_frame(cv::Rect(20,20,jiandao_width,jiandao_height)); + image_jiandao_argb.copyTo(copy_ori_image,image_jiandao_argb); + } + else if(gesture == "five") + { + cv::Mat copy_ori_image = osd_frame(cv::Rect(20,20,shitou_width,shitou_height)); + image_shitou_argb.copyTo(copy_ori_image,image_shitou_argb); + } + else if(gesture == "yeah") + { + cv::Mat copy_ori_image = osd_frame(cv::Rect(20,20,bu_width,bu_height)); + image_bu_argb.copyTo(copy_ori_image,image_bu_argb); + } + } + } + else if (MODE == 1) + { + { + ScopedTiming st("osd draw", atoi(argv[6])); + + if(gesture == "fist") + { + cv::Mat copy_ori_image = osd_frame(cv::Rect(20,20,bu_width,bu_height)); + image_bu_argb.copyTo(copy_ori_image,image_bu_argb); + } + else if(gesture == "five") + { + cv::Mat copy_ori_image = osd_frame(cv::Rect(20,20,jiandao_width,jiandao_height)); + image_jiandao_argb.copyTo(copy_ori_image,image_jiandao_argb); + } + else if(gesture == "yeah") + { + cv::Mat copy_ori_image = osd_frame(cv::Rect(20,20,shitou_width,shitou_height)); + image_shitou_argb.copyTo(copy_ori_image,image_shitou_argb); + } + } + } + else + { + if(sleep_end) + { + usleep(2000000); + sleep_end = false; + } + + if(max_id_hand == -1) + { + set_stop_id = true; + } + + if(counts_guess == -1 && gesture != "fist" && gesture != "yeah" && gesture != "five") + { + std::string start_txt = " G A M E S T A R T "; + std::string oneset_txt = std::to_string(1) + " S E T"; + cv::putText(osd_frame, start_txt, cv::Point(200,500),cv::FONT_HERSHEY_COMPLEX, 2, cv::Scalar(255, 255, 0, 0), 4); + cv::putText(osd_frame, oneset_txt, cv::Point(400,600),cv::FONT_HERSHEY_COMPLEX, 2, cv::Scalar(255, 0, 150, 255), 4); + } + else if(counts_guess == MODE) + { + // osd_frame = cv::Mat(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + if(k230_win > player_win) + { + cv::putText(osd_frame, "Y O U L O S E", cv::Point(340,500),cv::FONT_HERSHEY_COMPLEX, 2, cv::Scalar(255, 255, 0, 0), 4); + } + else if(k230_win < player_win) + { + cv::putText(osd_frame, "Y O U W I N", cv::Point(340,500),cv::FONT_HERSHEY_COMPLEX, 2, cv::Scalar(255, 255, 0, 0), 4); + } + else + { + cv::putText(osd_frame, "T I E G A M E", cv::Point(340,500),cv::FONT_HERSHEY_COMPLEX, 2, cv::Scalar(255, 255, 0, 0), 4); + } + counts_guess = -1; + player_win = 0; + k230_win = 0; + + sleep_end = true; + } + else + { + if(set_stop_id) + { + if(counts_guess == -1 && (gesture == "fist" || gesture == "yeah" || gesture == "five")) + { + counts_guess = 0; + } + + if(counts_guess != -1 && (gesture == "fist" || gesture == "yeah" || gesture == "five")) + { + int k230_guess=rand()%3; + if(gesture == "fist" && LIBRARY[k230_guess] == "yeah") + { + player_win += 1; + } + else if(gesture == "fist" && LIBRARY[k230_guess] == "five") + { + k230_win += 1; + } + if(gesture == "yeah" && LIBRARY[k230_guess] == "fist") + { + k230_win += 1; + } + else if(gesture == "yeah" && LIBRARY[k230_guess] == "five") + { + player_win += 1; + } + if(gesture == "five" && LIBRARY[k230_guess] == "fist") + { + player_win += 1; + } + else if(gesture == "five" && LIBRARY[k230_guess] == "yeah") + { + k230_win += 1; + } + + if(LIBRARY[k230_guess] == "fist") + { + cv::Mat copy_ori_image = osd_frame(cv::Rect(20,20,shitou_width,shitou_height)); + image_shitou_argb.copyTo(copy_ori_image,image_shitou_argb); + } + else if(LIBRARY[k230_guess] == "five") + { + cv::Mat copy_ori_image = osd_frame(cv::Rect(20,20,bu_width,bu_height)); + image_bu_argb.copyTo(copy_ori_image,image_bu_argb); + } + else if(LIBRARY[k230_guess] == "yeah") + { + cv::Mat copy_ori_image = osd_frame(cv::Rect(20,20,jiandao_width,jiandao_height)); + image_jiandao_argb.copyTo(copy_ori_image,image_jiandao_argb); + } + counts_guess += 1; + + std::string set_txt = std::to_string(counts_guess) + " S E T"; + cv::putText(osd_frame, set_txt, cv::Point(400,600),cv::FONT_HERSHEY_COMPLEX, 2, cv::Scalar(255, 0, 150, 255), 4); + osd_frame_tmp = osd_frame; + set_stop_id = false; + sleep_end = true; + } + else + { + std::string set_txt = std::to_string(counts_guess + 1) + " S E T"; + cv::putText(osd_frame, set_txt, cv::Point(400,600),cv::FONT_HERSHEY_COMPLEX, 2, cv::Scalar(255, 0, 150, 255), 4); + } + } + else + { + osd_frame = osd_frame_tmp; + } + } + } + + { + ScopedTiming st("osd copy", atoi(argv[6])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + // 显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id + 3, &vf_info); // K_VO_OSD0 + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } +} + +void video_proc_k230d(char *argv[]) +{ + vivcap_start(); + // 设置osd参数 + k_video_frame_info vf_info; + void *pic_vaddr = NULL; // osd + memset(&vf_info, 0, sizeof(vf_info)); + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory,get isp memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + // 读取石头剪刀布的bin文件数据 并且转换为mat类型 + int bu_width = 400; + int bu_height = 400; + cv::Mat image_bu_argb; + Utils::bin_2_mat("bu.bin", bu_width, bu_height, image_bu_argb); + + int shitou_width = 400; + int shitou_height = 400; + cv::Mat image_shitou_argb; + Utils::bin_2_mat("shitou.bin", shitou_width, shitou_height, image_shitou_argb); + + int jiandao_width = 400; + int jiandao_height = 400; + cv::Mat image_jiandao_argb; + Utils::bin_2_mat("jiandao.bin", jiandao_width, jiandao_height, image_jiandao_argb); + + // 设置游戏模式 + static int MODE = atoi(argv[5]); + int counts_guess = -1; + int player_win = 0; + int k230_win = 0; + bool sleep_end = false; + bool set_stop_id = true; + std::vector LIBRARY = {"fist","yeah","five"}; + + HandDetection hd(argv[1], atof(argv[2]), atof(argv[3]), {SENSOR_WIDTH, SENSOR_HEIGHT}, {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[6])); + sync(); + HandKeypoint hk(argv[4], {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[6])); + sync(); + + cv::Mat osd_frame_tmp(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame_tmp, osd_frame_tmp, cv::ROTATE_90_COUNTERCLOCKWISE); + std::vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + { + ScopedTiming st("read capture", atoi(argv[6])); + // 从vivcap中读取一帧图像到dump_info + memset(&dump_info, 0, sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + { + ScopedTiming st("isp copy", atoi(argv[6])); + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); + kd_mpi_sys_munmap(vbvaddr, size); + } + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + cv::Mat osd_frame_out;//(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::Mat osd_frame_vertical; + cv::Mat osd_frame_horizontal; + + results.clear(); + hd.pre_process(); + hd.inference(); + hd.post_process(results); + + float max_area_hand = 0; + int max_id_hand = -1; + for (int i = 0; i < results.size(); ++i) + { + float area_i = (results[i].x2 - results[i].x1) * (results[i].y2 - results[i].y1); + if (area_i > max_area_hand) + { + max_area_hand = area_i; + max_id_hand = i; + } + } + + std::string gesture = ""; + if (max_id_hand != -1) + { + std::string text = hd.labels_[results[max_id_hand].label] + ":" + std::to_string(round(results[max_id_hand].score * 100) / 100.0); + + int w = results[max_id_hand].x2 - results[max_id_hand].x1 + 1; + int h = results[max_id_hand].y2 - results[max_id_hand].y1 + 1; + + int rect_x = results[max_id_hand].x1/ SENSOR_WIDTH * osd_frame.cols; + int rect_y = results[max_id_hand].y1/ SENSOR_HEIGHT * osd_frame.rows; + int rect_w = (float)w / SENSOR_WIDTH * osd_frame.cols; + int rect_h = (float)h / SENSOR_HEIGHT * osd_frame.rows; + // cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w, rect_h), cv::Scalar( 255,255, 255, 255), 2, 2, 0); + + int length = std::max(w,h)/2; + int cx = (results[max_id_hand].x1+results[max_id_hand].x2)/2; + int cy = (results[max_id_hand].y1+results[max_id_hand].y2)/2; + int ratio_num = 1.26*length; + + int x1_1 = std::max(0,cx-ratio_num); + int y1_1 = std::max(0,cy-ratio_num); + int x2_1 = std::min(SENSOR_WIDTH-1, cx+ratio_num); + int y2_1 = std::min(SENSOR_HEIGHT-1, cy+ratio_num); + int w_1 = x2_1 - x1_1 + 1; + int h_1 = y2_1 - y1_1 + 1; + + struct Bbox bbox = {x:x1_1,y:y1_1,w:w_1,h:h_1}; + hk.pre_process(bbox); + + hk.inference(); + + hk.post_process(bbox); + + std::vector angle_list = hk.hand_angle(); + gesture = hk.h_gesture(angle_list); + + std::string text1 = "Gesture: " + gesture; + } + + + if(MODE == 0) + { + { + ScopedTiming st("osd draw", atoi(argv[6])); + + if(gesture == "fist") + { + cv::Mat copy_ori_image = osd_frame(cv::Rect(20,20,jiandao_width,jiandao_height)); + image_jiandao_argb.copyTo(copy_ori_image,image_jiandao_argb); + } + else if(gesture == "five") + { + cv::Mat copy_ori_image = osd_frame(cv::Rect(20,20,shitou_width,shitou_height)); + image_shitou_argb.copyTo(copy_ori_image,image_shitou_argb); + } + else if(gesture == "yeah") + { + cv::Mat copy_ori_image = osd_frame(cv::Rect(20,20,bu_width,bu_height)); + image_bu_argb.copyTo(copy_ori_image,image_bu_argb); + } + } + } + else if (MODE == 1) + { + { + ScopedTiming st("osd draw", atoi(argv[6])); + + if(gesture == "fist") + { + cv::Mat copy_ori_image = osd_frame(cv::Rect(20,20,bu_width,bu_height)); + image_bu_argb.copyTo(copy_ori_image,image_bu_argb); + } + else if(gesture == "five") + { + cv::Mat copy_ori_image = osd_frame(cv::Rect(20,20,jiandao_width,jiandao_height)); + image_jiandao_argb.copyTo(copy_ori_image,image_jiandao_argb); + } + else if(gesture == "yeah") + { + cv::Mat copy_ori_image = osd_frame(cv::Rect(20,20,shitou_width,shitou_height)); + image_shitou_argb.copyTo(copy_ori_image,image_shitou_argb); + } + } + } + else + { + if(sleep_end) + { + usleep(2000000); + sleep_end = false; + } + + if(max_id_hand == -1) + { + set_stop_id = true; + } + + if(counts_guess == -1 && gesture != "fist" && gesture != "yeah" && gesture != "five") + { + std::string start_txt = " G A M E S T A R T "; + std::string oneset_txt = std::to_string(1) + " S E T"; + cv::putText(osd_frame, start_txt, cv::Point(50,200),cv::FONT_HERSHEY_COMPLEX, 2, cv::Scalar(255, 255, 0, 0), 4); + cv::putText(osd_frame, oneset_txt, cv::Point(150,300),cv::FONT_HERSHEY_COMPLEX, 2, cv::Scalar(255, 0, 150, 255), 4); + } + else if(counts_guess == MODE) + { + // osd_frame = cv::Mat(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + if(k230_win > player_win) + { + cv::putText(osd_frame, "Y O U L O S E", cv::Point(100,200),cv::FONT_HERSHEY_COMPLEX, 2, cv::Scalar(255, 255, 0, 0), 4); + } + else if(k230_win < player_win) + { + cv::putText(osd_frame, "Y O U W I N", cv::Point(100,200),cv::FONT_HERSHEY_COMPLEX, 2, cv::Scalar(255, 255, 0, 0), 4); + } + else + { + cv::putText(osd_frame, "T I E G A M E", cv::Point(100,200),cv::FONT_HERSHEY_COMPLEX, 2, cv::Scalar(255, 255, 0, 0), 4); + } + counts_guess = -1; + player_win = 0; + k230_win = 0; + + sleep_end = true; + } + else + { + if(set_stop_id) + { + if(counts_guess == -1 && (gesture == "fist" || gesture == "yeah" || gesture == "five")) + { + counts_guess = 0; + } + + if(counts_guess != -1 && (gesture == "fist" || gesture == "yeah" || gesture == "five")) + { + int k230_guess=rand()%3; + if(gesture == "fist" && LIBRARY[k230_guess] == "yeah") + { + player_win += 1; + } + else if(gesture == "fist" && LIBRARY[k230_guess] == "five") + { + k230_win += 1; + } + if(gesture == "yeah" && LIBRARY[k230_guess] == "fist") + { + k230_win += 1; + } + else if(gesture == "yeah" && LIBRARY[k230_guess] == "five") + { + player_win += 1; + } + if(gesture == "five" && LIBRARY[k230_guess] == "fist") + { + player_win += 1; + } + else if(gesture == "five" && LIBRARY[k230_guess] == "yeah") + { + k230_win += 1; + } + + if(LIBRARY[k230_guess] == "fist") + { + cv::Mat copy_ori_image = osd_frame(cv::Rect(20,20,shitou_width,shitou_height)); + image_shitou_argb.copyTo(copy_ori_image,image_shitou_argb); + } + else if(LIBRARY[k230_guess] == "five") + { + cv::Mat copy_ori_image = osd_frame(cv::Rect(20,20,bu_width,bu_height)); + image_bu_argb.copyTo(copy_ori_image,image_bu_argb); + } + else if(LIBRARY[k230_guess] == "yeah") + { + cv::Mat copy_ori_image = osd_frame(cv::Rect(20,20,jiandao_width,jiandao_height)); + image_jiandao_argb.copyTo(copy_ori_image,image_jiandao_argb); + } + counts_guess += 1; + + std::string set_txt = std::to_string(counts_guess) + " S E T"; + cv::putText(osd_frame, set_txt, cv::Point(150,300),cv::FONT_HERSHEY_COMPLEX, 2, cv::Scalar(255, 0, 150, 255), 4); + osd_frame_tmp = osd_frame; + set_stop_id = false; + sleep_end = true; + } + else + { + std::string set_txt = std::to_string(counts_guess + 1) + " S E T"; + cv::putText(osd_frame, set_txt, cv::Point(150,300),cv::FONT_HERSHEY_COMPLEX, 2, cv::Scalar(255, 0, 150, 255), 4); + } + } + else + { + osd_frame = osd_frame_tmp; + } + } + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[6])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + // 显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id + 3, &vf_info); // K_VO_OSD0 + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } +} + +void video_proc_01(char *argv[]) +{ + vivcap_start(); + // 设置osd参数 + k_video_frame_info vf_info; + void *pic_vaddr = NULL; // osd + memset(&vf_info, 0, sizeof(vf_info)); + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory,get isp memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + // 读取石头剪刀布的bin文件数据 并且转换为mat类型 + int bu_width = 400; + int bu_height = 400; + cv::Mat image_bu_argb; + Utils::bin_2_mat("bu.bin", bu_width, bu_height, image_bu_argb); + + int shitou_width = 400; + int shitou_height = 400; + cv::Mat image_shitou_argb; + Utils::bin_2_mat("shitou.bin", shitou_width, shitou_height, image_shitou_argb); + + int jiandao_width = 400; + int jiandao_height = 400; + cv::Mat image_jiandao_argb; + Utils::bin_2_mat("jiandao.bin", jiandao_width, jiandao_height, image_jiandao_argb); + + // 设置游戏模式 + static int MODE = atoi(argv[5]); + int counts_guess = -1; + int player_win = 0; + int k230_win = 0; + bool sleep_end = false; + bool set_stop_id = true; + std::vector LIBRARY = {"fist","yeah","five"}; + + HandDetection hd(argv[1], atof(argv[2]), atof(argv[3]), {SENSOR_WIDTH, SENSOR_HEIGHT}, {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[6])); + sync(); + HandKeypoint hk(argv[4], {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[6])); + sync(); + + cv::Mat osd_frame_tmp(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame_tmp, osd_frame_tmp, cv::ROTATE_90_COUNTERCLOCKWISE); + std::vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + { + ScopedTiming st("read capture", atoi(argv[6])); + // 从vivcap中读取一帧图像到dump_info + memset(&dump_info, 0, sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + { + ScopedTiming st("isp copy", atoi(argv[6])); + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); + kd_mpi_sys_munmap(vbvaddr, size); + } + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + cv::Mat osd_frame_out;//(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::Mat osd_frame_vertical; + cv::Mat osd_frame_horizontal; + + results.clear(); + hd.pre_process(); + hd.inference(); + hd.post_process(results); + + float max_area_hand = 0; + int max_id_hand = -1; + for (int i = 0; i < results.size(); ++i) + { + float area_i = (results[i].x2 - results[i].x1) * (results[i].y2 - results[i].y1); + if (area_i > max_area_hand) + { + max_area_hand = area_i; + max_id_hand = i; + } + } + + std::string gesture = ""; + if (max_id_hand != -1) + { + std::string text = hd.labels_[results[max_id_hand].label] + ":" + std::to_string(round(results[max_id_hand].score * 100) / 100.0); + + int w = results[max_id_hand].x2 - results[max_id_hand].x1 + 1; + int h = results[max_id_hand].y2 - results[max_id_hand].y1 + 1; + + int rect_x = results[max_id_hand].x1/ SENSOR_WIDTH * osd_frame.cols; + int rect_y = results[max_id_hand].y1/ SENSOR_HEIGHT * osd_frame.rows; + int rect_w = (float)w / SENSOR_WIDTH * osd_frame.cols; + int rect_h = (float)h / SENSOR_HEIGHT * osd_frame.rows; + // cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w, rect_h), cv::Scalar( 255,255, 255, 255), 2, 2, 0); + + int length = std::max(w,h)/2; + int cx = (results[max_id_hand].x1+results[max_id_hand].x2)/2; + int cy = (results[max_id_hand].y1+results[max_id_hand].y2)/2; + int ratio_num = 1.26*length; + + int x1_1 = std::max(0,cx-ratio_num); + int y1_1 = std::max(0,cy-ratio_num); + int x2_1 = std::min(SENSOR_WIDTH-1, cx+ratio_num); + int y2_1 = std::min(SENSOR_HEIGHT-1, cy+ratio_num); + int w_1 = x2_1 - x1_1 + 1; + int h_1 = y2_1 - y1_1 + 1; + + struct Bbox bbox = {x:x1_1,y:y1_1,w:w_1,h:h_1}; + hk.pre_process(bbox); + + hk.inference(); + + hk.post_process(bbox); + + std::vector angle_list = hk.hand_angle(); + gesture = hk.h_gesture(angle_list); + + std::string text1 = "Gesture: " + gesture; + } + + + if(MODE == 0) + { + { + ScopedTiming st("osd draw", atoi(argv[6])); + + if(gesture == "fist") + { + cv::Mat copy_ori_image = osd_frame(cv::Rect(20,20,jiandao_width,jiandao_height)); + image_jiandao_argb.copyTo(copy_ori_image,image_jiandao_argb); + } + else if(gesture == "five") + { + cv::Mat copy_ori_image = osd_frame(cv::Rect(20,20,shitou_width,shitou_height)); + image_shitou_argb.copyTo(copy_ori_image,image_shitou_argb); + } + else if(gesture == "yeah") + { + cv::Mat copy_ori_image = osd_frame(cv::Rect(20,20,bu_width,bu_height)); + image_bu_argb.copyTo(copy_ori_image,image_bu_argb); + } + } + } + else if (MODE == 1) + { + { + ScopedTiming st("osd draw", atoi(argv[6])); + + if(gesture == "fist") + { + cv::Mat copy_ori_image = osd_frame(cv::Rect(20,20,bu_width,bu_height)); + image_bu_argb.copyTo(copy_ori_image,image_bu_argb); + } + else if(gesture == "five") + { + cv::Mat copy_ori_image = osd_frame(cv::Rect(20,20,jiandao_width,jiandao_height)); + image_jiandao_argb.copyTo(copy_ori_image,image_jiandao_argb); + } + else if(gesture == "yeah") + { + cv::Mat copy_ori_image = osd_frame(cv::Rect(20,20,shitou_width,shitou_height)); + image_shitou_argb.copyTo(copy_ori_image,image_shitou_argb); + } + } + } + else + { + if(sleep_end) + { + usleep(2000000); + sleep_end = false; + } + + if(max_id_hand == -1) + { + set_stop_id = true; + } + + if(counts_guess == -1 && gesture != "fist" && gesture != "yeah" && gesture != "five") + { + std::string start_txt = " G A M E S T A R T "; + std::string oneset_txt = std::to_string(1) + " S E T"; + cv::putText(osd_frame, start_txt, cv::Point(50,200),cv::FONT_HERSHEY_COMPLEX, 2, cv::Scalar(255, 255, 0, 0), 4); + cv::putText(osd_frame, oneset_txt, cv::Point(150,300),cv::FONT_HERSHEY_COMPLEX, 2, cv::Scalar(255, 0, 150, 255), 4); + } + else if(counts_guess == MODE) + { + // osd_frame = cv::Mat(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + if(k230_win > player_win) + { + cv::putText(osd_frame, "Y O U L O S E", cv::Point(100,200),cv::FONT_HERSHEY_COMPLEX, 2, cv::Scalar(255, 255, 0, 0), 4); + } + else if(k230_win < player_win) + { + cv::putText(osd_frame, "Y O U W I N", cv::Point(100,200),cv::FONT_HERSHEY_COMPLEX, 2, cv::Scalar(255, 255, 0, 0), 4); + } + else + { + cv::putText(osd_frame, "T I E G A M E", cv::Point(100,200),cv::FONT_HERSHEY_COMPLEX, 2, cv::Scalar(255, 255, 0, 0), 4); + } + counts_guess = -1; + player_win = 0; + k230_win = 0; + + sleep_end = true; + } + else + { + if(set_stop_id) + { + if(counts_guess == -1 && (gesture == "fist" || gesture == "yeah" || gesture == "five")) + { + counts_guess = 0; + } + + if(counts_guess != -1 && (gesture == "fist" || gesture == "yeah" || gesture == "five")) + { + int k230_guess=rand()%3; + if(gesture == "fist" && LIBRARY[k230_guess] == "yeah") + { + player_win += 1; + } + else if(gesture == "fist" && LIBRARY[k230_guess] == "five") + { + k230_win += 1; + } + if(gesture == "yeah" && LIBRARY[k230_guess] == "fist") + { + k230_win += 1; + } + else if(gesture == "yeah" && LIBRARY[k230_guess] == "five") + { + player_win += 1; + } + if(gesture == "five" && LIBRARY[k230_guess] == "fist") + { + player_win += 1; + } + else if(gesture == "five" && LIBRARY[k230_guess] == "yeah") + { + k230_win += 1; + } + + if(LIBRARY[k230_guess] == "fist") + { + cv::Mat copy_ori_image = osd_frame(cv::Rect(20,20,shitou_width,shitou_height)); + image_shitou_argb.copyTo(copy_ori_image,image_shitou_argb); + } + else if(LIBRARY[k230_guess] == "five") + { + cv::Mat copy_ori_image = osd_frame(cv::Rect(20,20,bu_width,bu_height)); + image_bu_argb.copyTo(copy_ori_image,image_bu_argb); + } + else if(LIBRARY[k230_guess] == "yeah") + { + cv::Mat copy_ori_image = osd_frame(cv::Rect(20,20,jiandao_width,jiandao_height)); + image_jiandao_argb.copyTo(copy_ori_image,image_jiandao_argb); + } + counts_guess += 1; + + std::string set_txt = std::to_string(counts_guess) + " S E T"; + cv::putText(osd_frame, set_txt, cv::Point(150,300),cv::FONT_HERSHEY_COMPLEX, 2, cv::Scalar(255, 0, 150, 255), 4); + osd_frame_tmp = osd_frame; + set_stop_id = false; + sleep_end = true; + } + else + { + std::string set_txt = std::to_string(counts_guess + 1) + " S E T"; + cv::putText(osd_frame, set_txt, cv::Point(150,300),cv::FONT_HERSHEY_COMPLEX, 2, cv::Scalar(255, 0, 150, 255), 4); + } + } + else + { + osd_frame = osd_frame_tmp; + } + } + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[6])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + // 显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id + 3, &vf_info); // K_VO_OSD0 + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } +} int main(int argc, char *argv[]) { @@ -385,13 +1365,61 @@ int main(int argc, char *argv[]) return -1; } - std::thread thread_isp(video_proc, argv); - while (getchar() != 'q') + #if defined(CONFIG_BOARD_K230_CANMV) + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_V2) + { + std::thread thread_isp(video_proc_v2, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230D_CANMV) + { + std::thread thread_isp(video_proc_k230d, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) { - usleep(10000); + std::thread thread_isp(video_proc_01, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); } + #else + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } - isp_stop = true; - thread_isp.join(); + isp_stop = true; + thread_isp.join(); + } + #endif return 0; } diff --git a/src/reference/ai_poc/finger_guessing/vi_vo.h b/src/reference/ai_poc/finger_guessing/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/finger_guessing/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/fitness/main.cc b/src/reference/ai_poc/fitness/main.cc index afe3e7615..7a8208967 100644 --- a/src/reference/ai_poc/fitness/main.cc +++ b/src/reference/ai_poc/fitness/main.cc @@ -52,7 +52,7 @@ void print_usage(const char *name) } -void video_proc(char *argv[]) +void video_proc_v1(char *argv[]) { vivcap_start(); @@ -155,6 +155,318 @@ void video_proc(char *argv[]) } +void video_proc_v2(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + poseDetect pd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + cv::Vec4d params = pd.params; + + std::vector result; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + // results.clear(); + result.clear(); + + pd.pre_process(); + pd.inference(); + bool find_ = pd.post_process(result,params); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + float thres_conf = atof(argv[2]); + if(find_) + { + Utils::DrawPred_video(osd_frame,{SENSOR_WIDTH,SENSOR_HEIGHT}, result, SKELETON, KPS_COLORS, LIMB_COLORS,thres_conf); + } + else + { + cout << "not find!\n"; + } + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_k230d(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + poseDetect pd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + cv::Vec4d params = pd.params; + + std::vector result; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + // results.clear(); + result.clear(); + + pd.pre_process(); + pd.inference(); + bool find_ = pd.post_process(result,params); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + float thres_conf = atof(argv[2]); + if(find_) + { + Utils::DrawPred_video(osd_frame,{SENSOR_WIDTH,SENSOR_HEIGHT}, result, SKELETON, KPS_COLORS, LIMB_COLORS,thres_conf); + } + else + { + cout << "not find!\n"; + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_01(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + poseDetect pd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + cv::Vec4d params = pd.params; + + std::vector result; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + // results.clear(); + result.clear(); + + pd.pre_process(); + pd.inference(); + bool find_ = pd.post_process(result,params); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + float thres_conf = atof(argv[2]); + if(find_) + { + Utils::DrawPred_video(osd_frame,{SENSOR_WIDTH,SENSOR_HEIGHT}, result, SKELETON, KPS_COLORS, LIMB_COLORS,thres_conf); + } + else + { + cout << "not find!\n"; + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} int main(int argc, char *argv[]) { @@ -167,14 +479,62 @@ int main(int argc, char *argv[]) if (strcmp(argv[4], "None") == 0) { - std::thread thread_isp(video_proc, argv); - while (getchar() != 'q') + #if defined(CONFIG_BOARD_K230_CANMV) + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_V2) + { + std::thread thread_isp(video_proc_v2, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230D_CANMV) + { + std::thread thread_isp(video_proc_k230d, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) { - usleep(10000); + std::thread thread_isp(video_proc_01, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); } + #else + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } - isp_stop = true; - thread_isp.join(); + isp_stop = true; + thread_isp.join(); + } + #endif } return 0; diff --git a/src/reference/ai_poc/fitness/utils.cc b/src/reference/ai_poc/fitness/utils.cc index d1d7c4d5b..fa2dfeda6 100644 --- a/src/reference/ai_poc/fitness/utils.cc +++ b/src/reference/ai_poc/fitness/utils.cc @@ -769,6 +769,6 @@ void Utils::action_count( cv::Mat& image, std::vector keypoints, floa { int deepdown = PoseAction::single_action_check(keypoints, thresh, 3, 2); std::string deep = "deep-down:" + std::to_string(deepdown); - cv::putText(image, deep, cv::Point(240, 80), cv::FONT_HERSHEY_COMPLEX, 3, cv::Scalar(255, 0, 255, 255), 3, 8, 0); + cv::putText(image, deep, cv::Point(10, 80), cv::FONT_HERSHEY_COMPLEX, 3, cv::Scalar(255, 0, 255, 255), 2, 5, 0); } diff --git a/src/reference/ai_poc/fitness/vi_vo.h b/src/reference/ai_poc/fitness/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/fitness/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/head_detection/main.cc b/src/reference/ai_poc/head_detection/main.cc index 77b325361..378f30187 100644 --- a/src/reference/ai_poc/head_detection/main.cc +++ b/src/reference/ai_poc/head_detection/main.cc @@ -111,12 +111,26 @@ void video_proc(char *argv[]) head_detection.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results,false); cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); - cv::Mat osd_frame_tmp; - + #if defined(CONFIG_BOARD_K230D_CANMV) + { + ScopedTiming st("osd draw", atoi(argv[5])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + head_detection.draw_result(osd_frame,results,false); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + ScopedTiming st("osd draw", atoi(argv[5])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + fp.draw_result(osd_frame,det_results[i].bbox,pose_result,false); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #else { ScopedTiming st("osd draw", atoi(argv[5])); head_detection.draw_result(osd_frame,results,false); } + #endif { ScopedTiming st("osd copy", atoi(argv[5])); diff --git a/src/reference/ai_poc/head_detection/vi_vo.h b/src/reference/ai_poc/head_detection/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/head_detection/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/helmet_detect/main.cc b/src/reference/ai_poc/helmet_detect/main.cc index 5284e58f1..4aa05e633 100644 --- a/src/reference/ai_poc/helmet_detect/main.cc +++ b/src/reference/ai_poc/helmet_detect/main.cc @@ -52,7 +52,7 @@ void print_usage(const char *name) << endl; } -void video_proc(char *argv[]) +void video_proc_v1(char *argv[]) { vivcap_start(); @@ -172,6 +172,370 @@ void video_proc(char *argv[]) } +void video_proc_v2(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + helmetDetect hd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + hd.pre_process(); + hd.inference(); + hd.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + + std::string text; + cv::Point origin; + std::vector scalars= { + cv::Scalar(255,0, 0, 255), // "helmet" + cv::Scalar(255,0, 255, 0), // "head" + cv::Scalar(255,255, 0, 0), // "person" + cv::Scalar(255,255,0, 0), + cv::Scalar(255,255,0, 255), + cv::Scalar(255,0,0, 255) + }; + + for (auto r : results) + { + ScopedTiming st("draw boxes", atoi(argv[5])); + text = hd.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); + + int x1 = r.x1 / SENSOR_WIDTH * osd_width; + int y1 = r.y1 / SENSOR_HEIGHT * osd_height; + + origin.x = x1; + origin.y = y1-20; + + int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_width; + int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_height; + + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), cv::Scalar(255, 255,0, 0), 6, 2, 0); // ARGB + cv::putText(osd_frame, text, origin, cv::FONT_HERSHEY_COMPLEX, 2, scalars[r.label+2], 1, 8, 0); + + } + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_k230d(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + helmetDetect hd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + hd.pre_process(); + hd.inference(); + hd.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + std::string text; + cv::Point origin; + std::vector scalars= { + cv::Scalar(255,0, 0, 255), // "helmet" + cv::Scalar(255,0, 255, 0), // "head" + cv::Scalar(255,255, 0, 0), // "person" + cv::Scalar(255,255,0, 0), + cv::Scalar(255,255,0, 255), + cv::Scalar(255,0,0, 255) + }; + + for (auto r : results) + { + ScopedTiming st("draw boxes", atoi(argv[5])); + text = hd.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); + + int x1 = r.x1 / SENSOR_WIDTH * osd_frame.cols; + int y1 = r.y1 / SENSOR_HEIGHT * osd_frame.rows; + + origin.x = x1; + origin.y = y1-20; + + int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_frame.cols; + int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_frame.rows; + + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), cv::Scalar(255, 255,0, 0), 6, 2, 0); // ARGB + cv::putText(osd_frame, text, origin, cv::FONT_HERSHEY_COMPLEX, 2, scalars[r.label+2], 1, 8, 0); + + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_01(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + helmetDetect hd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + hd.pre_process(); + hd.inference(); + hd.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + std::string text; + cv::Point origin; + std::vector scalars= { + cv::Scalar(255,0, 0, 255), // "helmet" + cv::Scalar(255,0, 255, 0), // "head" + cv::Scalar(255,255, 0, 0), // "person" + cv::Scalar(255,255,0, 0), + cv::Scalar(255,255,0, 255), + cv::Scalar(255,0,0, 255) + }; + + for (auto r : results) + { + ScopedTiming st("draw boxes", atoi(argv[5])); + text = hd.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); + + int x1 = r.x1 / SENSOR_WIDTH * osd_frame.cols; + int y1 = r.y1 / SENSOR_HEIGHT * osd_frame.rows; + + origin.x = x1; + origin.y = y1-20; + + int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_frame.cols; + int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_frame.rows; + + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), cv::Scalar(255, 255,0, 0), 6, 2, 0); // ARGB + cv::putText(osd_frame, text, origin, cv::FONT_HERSHEY_COMPLEX, 2, scalars[r.label+2], 1, 8, 0); + + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + int main(int argc, char *argv[]) { @@ -184,14 +548,62 @@ int main(int argc, char *argv[]) if (strcmp(argv[4], "None") == 0) { - std::thread thread_isp(video_proc, argv); - while (getchar() != 'q') + #if defined(CONFIG_BOARD_K230_CANMV) + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_V2) + { + std::thread thread_isp(video_proc_v2, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230D_CANMV) { - usleep(10000); + std::thread thread_isp(video_proc_k230d, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + std::thread thread_isp(video_proc_01, argv); + while (getchar() != 'q') + { + usleep(10000); + } - isp_stop = true; - thread_isp.join(); + isp_stop = true; + thread_isp.join(); + } + #else + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #endif } else { diff --git a/src/reference/ai_poc/helmet_detect/vi_vo.h b/src/reference/ai_poc/helmet_detect/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/helmet_detect/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/licence_det/main.cc b/src/reference/ai_poc/licence_det/main.cc index 2bc1e0ae9..d343dd113 100644 --- a/src/reference/ai_poc/licence_det/main.cc +++ b/src/reference/ai_poc/licence_det/main.cc @@ -49,7 +49,7 @@ void print_usage(const char *name) << endl; } -void video_proc(char *argv[]) +void video_proc_v1(char *argv[]) { vivcap_start(); @@ -145,6 +145,298 @@ void video_proc(char *argv[]) } +void video_proc_v2(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + LicenceDetect licenceDet(argv[1], atof(argv[2]), atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + licenceDet.pre_process(); + licenceDet.inference(); + + licenceDet.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + + { + ScopedTiming st("osd draw", atoi(argv[5])); + Utils::draw_detections(osd_frame, results, {osd_width, osd_height}, {SENSOR_WIDTH, SENSOR_HEIGHT}); + } + + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_k230d(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + LicenceDetect licenceDet(argv[1], atof(argv[2]), atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + licenceDet.pre_process(); + licenceDet.inference(); + + licenceDet.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + + { + ScopedTiming st("osd draw", atoi(argv[5])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + Utils::draw_detections(osd_frame, results, {osd_frame.cols, osd_frame.rows}, {SENSOR_WIDTH, SENSOR_HEIGHT}); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_01(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + LicenceDetect licenceDet(argv[1], atof(argv[2]), atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + licenceDet.pre_process(); + licenceDet.inference(); + + licenceDet.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + + { + ScopedTiming st("osd draw", atoi(argv[5])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + Utils::draw_detections(osd_frame, results, {osd_frame.cols, osd_frame.rows}, {SENSOR_WIDTH, SENSOR_HEIGHT}); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + int main(int argc, char *argv[]) { @@ -157,14 +449,62 @@ int main(int argc, char *argv[]) if (strcmp(argv[4], "None") == 0) { - std::thread thread_isp(video_proc, argv); - while (getchar() != 'q') + #if defined(CONFIG_BOARD_K230_CANMV) + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_V2) + { + std::thread thread_isp(video_proc_v2, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230D_CANMV) { - usleep(10000); + std::thread thread_isp(video_proc_k230d, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + std::thread thread_isp(video_proc_01, argv); + while (getchar() != 'q') + { + usleep(10000); + } - isp_stop = true; - thread_isp.join(); + isp_stop = true; + thread_isp.join(); + } + #else + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #endif } else { diff --git a/src/reference/ai_poc/licence_det/vi_vo.h b/src/reference/ai_poc/licence_det/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/licence_det/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/licence_det_rec/main.cc b/src/reference/ai_poc/licence_det_rec/main.cc index 219076623..6448d2278 100644 --- a/src/reference/ai_poc/licence_det_rec/main.cc +++ b/src/reference/ai_poc/licence_det_rec/main.cc @@ -53,7 +53,7 @@ void print_usage(const char *name) << endl; } -void video_proc(char *argv[]) +void video_proc_v1(char *argv[]) { vivcap_start(); @@ -191,6 +191,424 @@ void video_proc(char *argv[]) } +void video_proc_v2(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + LicenceDetect licenceDet(argv[1], atof(argv[2]), atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[6])); + LicenceReco licenceReco(argv[5],g_dict_size,atoi(argv[6])); + + vector results_det; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[6])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[6])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results_det.clear(); + + licenceDet.pre_process(); + licenceDet.inference(); + + licenceDet.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results_det); + + int matsize = SENSOR_WIDTH * SENSOR_HEIGHT; + cv::Mat ori_img; + cv::Mat ori_img_R = cv::Mat(SENSOR_HEIGHT, SENSOR_WIDTH, CV_8UC1, vaddr); + cv::Mat ori_img_G = cv::Mat(SENSOR_HEIGHT, SENSOR_WIDTH, CV_8UC1, vaddr + 1 * matsize); + cv::Mat ori_img_B = cv::Mat(SENSOR_HEIGHT, SENSOR_WIDTH, CV_8UC1, vaddr + 2 * matsize); + std::vector sensor_rgb; + sensor_rgb.push_back(ori_img_B); + sensor_rgb.push_back(ori_img_G); + sensor_rgb.push_back(ori_img_R); + cv::merge(sensor_rgb, ori_img); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + + for(int i = 0; i < results_det.size(); i++) + { + vector ori_vec; + vector sort_vtd(4); + ori_vec.clear(); + for(int j = 0; j < 4; j++) + { + ori_vec.push_back(results_det[i].vertices[j]); + } + cv::RotatedRect rect = cv::minAreaRect(ori_vec); + cv::Point2f ver[4]; + rect.points(ver); + + cv::Mat crop; + Utils::warppersp(ori_img, crop, results_det[i], sort_vtd); + cv::Mat crop_gray; + cv::cvtColor(crop, crop_gray, COLOR_BGR2GRAY); + + licenceReco.pre_process(crop_gray); + licenceReco.inference(); + + vector results_reco; + licenceReco.post_process(results_reco); + + { + ScopedTiming st("osd_draw_text", atoi(argv[6])); + Utils::draw_text(float(sort_vtd[3].x), float(sort_vtd[3].y),osd_frame,results_reco,{osd_width, osd_height}, {SENSOR_WIDTH, SENSOR_HEIGHT}); + } + } + + + { + ScopedTiming st("osd draw_detections", atoi(argv[6])); + Utils::draw_detections(osd_frame, results_det, {osd_width, osd_height}, {SENSOR_WIDTH, SENSOR_HEIGHT}); + } + + { + ScopedTiming st("osd copy", atoi(argv[6])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_k230d(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + LicenceDetect licenceDet(argv[1], atof(argv[2]), atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[6])); + LicenceReco licenceReco(argv[5],g_dict_size,atoi(argv[6])); + + vector results_det; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[6])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[6])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results_det.clear(); + + licenceDet.pre_process(); + licenceDet.inference(); + + licenceDet.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results_det); + + int matsize = SENSOR_WIDTH * SENSOR_HEIGHT; + cv::Mat ori_img; + cv::Mat ori_img_R = cv::Mat(SENSOR_HEIGHT, SENSOR_WIDTH, CV_8UC1, vaddr); + cv::Mat ori_img_G = cv::Mat(SENSOR_HEIGHT, SENSOR_WIDTH, CV_8UC1, vaddr + 1 * matsize); + cv::Mat ori_img_B = cv::Mat(SENSOR_HEIGHT, SENSOR_WIDTH, CV_8UC1, vaddr + 2 * matsize); + std::vector sensor_rgb; + sensor_rgb.push_back(ori_img_B); + sensor_rgb.push_back(ori_img_G); + sensor_rgb.push_back(ori_img_R); + cv::merge(sensor_rgb, ori_img); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + for(int i = 0; i < results_det.size(); i++) + { + vector ori_vec; + vector sort_vtd(4); + ori_vec.clear(); + for(int j = 0; j < 4; j++) + { + ori_vec.push_back(results_det[i].vertices[j]); + } + cv::RotatedRect rect = cv::minAreaRect(ori_vec); + cv::Point2f ver[4]; + rect.points(ver); + + cv::Mat crop; + Utils::warppersp(ori_img, crop, results_det[i], sort_vtd); + cv::Mat crop_gray; + cv::cvtColor(crop, crop_gray, COLOR_BGR2GRAY); + + licenceReco.pre_process(crop_gray); + licenceReco.inference(); + + vector results_reco; + licenceReco.post_process(results_reco); + + { + ScopedTiming st("osd_draw_text", atoi(argv[6])); + Utils::draw_text(float(sort_vtd[3].x), float(sort_vtd[3].y),osd_frame,results_reco,{osd_frame.cols, osd_frame.rows}, {SENSOR_WIDTH, SENSOR_HEIGHT}); + } + } + + + { + ScopedTiming st("osd draw_detections", atoi(argv[6])); + Utils::draw_detections(osd_frame, results_det, {osd_frame.cols, osd_frame.rows}, {SENSOR_WIDTH, SENSOR_HEIGHT}); + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[6])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_01(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + LicenceDetect licenceDet(argv[1], atof(argv[2]), atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[6])); + LicenceReco licenceReco(argv[5],g_dict_size,atoi(argv[6])); + + vector results_det; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[6])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[6])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results_det.clear(); + + licenceDet.pre_process(); + licenceDet.inference(); + + licenceDet.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results_det); + + int matsize = SENSOR_WIDTH * SENSOR_HEIGHT; + cv::Mat ori_img; + cv::Mat ori_img_R = cv::Mat(SENSOR_HEIGHT, SENSOR_WIDTH, CV_8UC1, vaddr); + cv::Mat ori_img_G = cv::Mat(SENSOR_HEIGHT, SENSOR_WIDTH, CV_8UC1, vaddr + 1 * matsize); + cv::Mat ori_img_B = cv::Mat(SENSOR_HEIGHT, SENSOR_WIDTH, CV_8UC1, vaddr + 2 * matsize); + std::vector sensor_rgb; + sensor_rgb.push_back(ori_img_B); + sensor_rgb.push_back(ori_img_G); + sensor_rgb.push_back(ori_img_R); + cv::merge(sensor_rgb, ori_img); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + for(int i = 0; i < results_det.size(); i++) + { + vector ori_vec; + vector sort_vtd(4); + ori_vec.clear(); + for(int j = 0; j < 4; j++) + { + ori_vec.push_back(results_det[i].vertices[j]); + } + cv::RotatedRect rect = cv::minAreaRect(ori_vec); + cv::Point2f ver[4]; + rect.points(ver); + + cv::Mat crop; + Utils::warppersp(ori_img, crop, results_det[i], sort_vtd); + cv::Mat crop_gray; + cv::cvtColor(crop, crop_gray, COLOR_BGR2GRAY); + + licenceReco.pre_process(crop_gray); + licenceReco.inference(); + + vector results_reco; + licenceReco.post_process(results_reco); + + { + ScopedTiming st("osd_draw_text", atoi(argv[6])); + Utils::draw_text(float(sort_vtd[3].x), float(sort_vtd[3].y),osd_frame,results_reco,{osd_frame.cols, osd_frame.rows}, {SENSOR_WIDTH, SENSOR_HEIGHT}); + } + } + + + { + ScopedTiming st("osd draw_detections", atoi(argv[6])); + Utils::draw_detections(osd_frame, results_det, {osd_frame.cols, osd_frame.rows}, {SENSOR_WIDTH, SENSOR_HEIGHT}); + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[6])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + int main(int argc, char *argv[]) { @@ -203,14 +621,62 @@ int main(int argc, char *argv[]) if (strcmp(argv[4], "None") == 0) { - std::thread thread_isp(video_proc, argv); - while (getchar() != 'q') + #if defined(CONFIG_BOARD_K230_CANMV) + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_V2) + { + std::thread thread_isp(video_proc_v2, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230D_CANMV) { - usleep(10000); + std::thread thread_isp(video_proc_k230d, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + std::thread thread_isp(video_proc_01, argv); + while (getchar() != 'q') + { + usleep(10000); + } - isp_stop = true; - thread_isp.join(); + isp_stop = true; + thread_isp.join(); + } + #else + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #endif } else { diff --git a/src/reference/ai_poc/licence_det_rec/vi_vo.h b/src/reference/ai_poc/licence_det_rec/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/licence_det_rec/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/nanotracker/main.cc b/src/reference/ai_poc/nanotracker/main.cc index d8575d2c9..bcd75adf4 100755 --- a/src/reference/ai_poc/nanotracker/main.cc +++ b/src/reference/ai_poc/nanotracker/main.cc @@ -75,7 +75,7 @@ void print_usage(const char *name) << endl; } -void video_proc(char *argv[]) +void video_proc_v1(char *argv[]) { vivcap_start(); @@ -396,6 +396,986 @@ void video_proc(char *argv[]) } +void video_proc_v2(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + int crop_net_len = atoi(argv[4]); + int src_net_len = atoi(argv[5]); + + float thresh = atof(argv[6]); + + init(); + + Crop crop(argv[1], crop_net_len , atoi(argv[7])); + Crop crop_video(argv[1], crop_net_len ,{SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[7])); + + Src src(argv[2],src_net_len , atoi(argv[7])); + Src src_video(argv[2],src_net_len ,{SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[7])); + + interpreter interp; + + std::ifstream ifs(argv[3], std::ios::binary); + interp.load_model(ifs).expect("Invalid kmodel"); + + + crop_video.pre_process(); + cv::Mat ori_img = cv::imread("ori_img.jpg",cv::IMREAD_UNCHANGED); + + float* pos = get_position(ori_img); + float* cen = get_center(ori_img); + + bool enter_init = true; + + std::vector src_img_vec; + cv::Mat src_img; + cv::Mat src_input; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + + float w_z, h_z, s_z; + + { + ScopedTiming st("get_updated_position : ", atoi(argv[7])); + + pos = get_updated_position(); + w_z = pos[0] + CONTEXT_AMOUNT * (pos[0] + pos[1]); + h_z = pos[1] + CONTEXT_AMOUNT * (pos[0] + pos[1]); + s_z = round(sqrt(w_z * h_z)); + } + + { + ScopedTiming st("src_video.pre_process_video : ", atoi(argv[7])); + src_img_vec.clear(); + src_video.pre_process_video( src_img ); + } + + + { + ScopedTiming st("src sub_window : ", atoi(argv[7])); + src_input = sub_window(src_img, INSTANCE_SIZE, round(s_z * INSTANCE_SIZE / EXEMPLAR_SIZE)); + } + + + float *crop_output; + float *src_output; + + if (enter_init) + { + + int seconds = 8; //倒计时时长，单位秒 + time_t endtime = time(NULL) + seconds; //倒计时结束时间 + + while (time(NULL) <= endtime) { + + { + ScopedTiming st("read capture", atoi(argv[7])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[7])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + cout << "倒计时：" << endtime - time(NULL) << "秒" << endl; + + + // 初始化跟踪框. + int init_x0 = MARGIN * osd_width; + int init_x1 = (1 - MARGIN) * osd_width; + int init_y0 = osd_height / 2.0 - ((1 - 2 * MARGIN) * osd_width) / 2.0; + int init_y1 = osd_height / 2.0 + ((1 - 2 * MARGIN) * osd_width) / 2.0; + + int init_w = init_x1 - init_x0; + int init_h = init_y1 - init_y0; + + cv::rectangle(osd_frame, cv::Rect( init_x0,init_y0,init_w,init_h ), cv::Scalar(255, 0,255, 0), 8, 2, 0); // ARGB + + if( (endtime - time(NULL)==2) || (endtime - time(NULL)==3) || (endtime - time(NULL)==4) ) + { + std::cout << " >>>>>> get trackWindow <<<<<<<<" << std::endl; + + crop_video.pre_process(); + + cv::Mat crop_img = cv::imread( "crop_template.jpg",cv::IMREAD_UNCHANGED ); + cv::Mat crop_input = sub_window(crop_img, EXEMPLAR_SIZE, round(s_z)); + cv::imwrite("crop_window.jpg",crop_input); + + crop.pre_process( crop_input ); + crop.inference(); + crop.post_process(); + crop_output = crop.output; + + } + + std::this_thread::sleep_for(std::chrono::seconds(1)); + + { + ScopedTiming st("osd copy", atoi(argv[7])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + + } + + cout << ">>>>>>> Play <<<<<<<" << endl; + enter_init = false; + + } + else + { + { + ScopedTiming st("read capture", atoi(argv[7])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[7])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + { + ScopedTiming st("src pipeline: ", atoi(argv[7])); + src.pre_process(src_input); + src.inference(); + src.post_process(); + } + + + src_output = src.output; + + std::vector inputs; + std::vector outputs; + + { + ScopedTiming st("head pipeline: ", atoi(argv[7])); + inputs.clear(); + inputs.push_back(crop_output); + inputs.push_back(src_output); + + std::vector input_shapes = { 1*48*8*8,1*48*16*16 }; + for ( int j = 0; j < 2; j++) + { + auto desc = interp.input_desc(j); + auto shape = interp.input_shape(j); + auto tensor = host_runtime_tensor::create(desc.datatype, shape, hrt::pool_shared).expect("cannot create input tensor"); + auto mapped_buf = std::move(hrt::map(tensor, map_access_::map_write).unwrap()); + + memcpy(reinterpret_cast(mapped_buf.buffer().data()), reinterpret_cast( inputs[j]), input_shapes[j]*4); + auto ret = mapped_buf.unmap(); + ret = hrt::sync(tensor, sync_op_t::sync_write_back, true); + if (!ret.is_ok()) + { + std::cerr << "hrt::sync failed" << std::endl; + std::abort(); + } + + interp.input_tensor(j, tensor).expect("cannot set input tensor"); + } + + for (size_t i = 0; i < interp.outputs_size(); i++) + { + auto desc = interp.output_desc(i); + auto shape = interp.output_shape(i); + auto tensor = host_runtime_tensor::create(desc.datatype, shape, hrt::pool_shared).expect("cannot create output tensor"); + interp.output_tensor(i, tensor).expect("cannot set output tensor"); + } + + auto start = std::chrono::steady_clock::now(); + interp.run().expect("error occurred in running model"); + auto stop = std::chrono::steady_clock::now(); + double duration = std::chrono::duration(stop - start).count(); + + outputs.clear(); + for ( int j = 0; j<2; j++) + { + auto out = interp.output_tensor(j).expect("cannot get output tensor"); + auto mapped_buf = std::move(hrt::map(out, map_access_::map_read).unwrap()); + + outputs.push_back( (float *)mapped_buf.buffer().data() ); + + } + } + + + float* score, * box; + score = outputs[0]; + box = outputs[1]; + + int box_x, box_y, box_h, box_w; + float best_score; + { + ScopedTiming st("head post_process : ", atoi(argv[7])); + post_process(score, box, SENSOR_WIDTH, SENSOR_HEIGHT, box_x, box_y, box_w, box_h, best_score); + } + + + { + ScopedTiming st("draw box", atoi(argv[7])); + if (best_score > thresh) + { + + int r_x1 = box_x; + int r_y1 = box_y; + int r_x2 = (box_x+box_w); + int r_y2 = (box_y+box_h); + + int x1 = r_x1*1.0 / SENSOR_WIDTH * osd_width; + int y1 = r_y1*1.0 / SENSOR_HEIGHT * osd_height; + + int w = (r_x2-r_x1)*1.0 / SENSOR_WIDTH * osd_width; + int h = (r_y2-r_y1)*1.0 / SENSOR_HEIGHT * osd_height; + + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), cv::Scalar(255, 255,0, 0), 8, 2, 0); // ARGB + + } + } + + + { + ScopedTiming st("osd copy", atoi(argv[7])); + + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_k230d(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + int crop_net_len = atoi(argv[4]); + int src_net_len = atoi(argv[5]); + + float thresh = atof(argv[6]); + + init(); + + Crop crop(argv[1], crop_net_len , atoi(argv[7])); + Crop crop_video(argv[1], crop_net_len ,{SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[7])); + + Src src(argv[2],src_net_len , atoi(argv[7])); + Src src_video(argv[2],src_net_len ,{SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[7])); + + interpreter interp; + + std::ifstream ifs(argv[3], std::ios::binary); + interp.load_model(ifs).expect("Invalid kmodel"); + + + crop_video.pre_process(); + cv::Mat ori_img = cv::imread("ori_img.jpg",cv::IMREAD_UNCHANGED); + + float* pos = get_position(ori_img); + float* cen = get_center(ori_img); + + bool enter_init = true; + + std::vector src_img_vec; + cv::Mat src_img; + cv::Mat src_input; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + bool osd_rotate = false; + + float w_z, h_z, s_z; + + { + ScopedTiming st("get_updated_position : ", atoi(argv[7])); + + pos = get_updated_position(); + w_z = pos[0] + CONTEXT_AMOUNT * (pos[0] + pos[1]); + h_z = pos[1] + CONTEXT_AMOUNT * (pos[0] + pos[1]); + s_z = round(sqrt(w_z * h_z)); + } + + { + ScopedTiming st("src_video.pre_process_video : ", atoi(argv[7])); + src_img_vec.clear(); + src_video.pre_process_video( src_img ); + } + + + { + ScopedTiming st("src sub_window : ", atoi(argv[7])); + src_input = sub_window(src_img, INSTANCE_SIZE, round(s_z * INSTANCE_SIZE / EXEMPLAR_SIZE)); + } + + + float *crop_output; + float *src_output; + + if (enter_init) + { + + int seconds = 8; //倒计时时长，单位秒 + time_t endtime = time(NULL) + seconds; //倒计时结束时间 + + while (time(NULL) <= endtime) { + + { + ScopedTiming st("read capture", atoi(argv[7])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[7])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + cout << "倒计时：" << endtime - time(NULL) << "秒" << endl; + + if(osd_rotate) + { + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + osd_rotate = false; + } + + + // 初始化跟踪框. + int init_x0 = MARGIN * osd_frame.cols; + int init_x1 = (1 - MARGIN) * osd_frame.cols; + int init_y0 = osd_frame.rows / 2.0 - ((1 - 2 * MARGIN) * osd_frame.cols) / 2.0; + int init_y1 = osd_frame.rows / 2.0 + ((1 - 2 * MARGIN) * osd_frame.cols) / 2.0; + + int init_w = init_x1 - init_x0; + int init_h = init_y1 - init_y0; + + cv::rectangle(osd_frame, cv::Rect( init_x0,init_y0,init_w,init_h ), cv::Scalar(255, 0,255, 0), 8, 2, 0); // ARGB + + if( (endtime - time(NULL)==2) || (endtime - time(NULL)==3) || (endtime - time(NULL)==4) ) + { + std::cout << " >>>>>> get trackWindow <<<<<<<<" << std::endl; + + crop_video.pre_process(); + + cv::Mat crop_img = cv::imread( "crop_template.jpg",cv::IMREAD_UNCHANGED ); + cv::Mat crop_input = sub_window(crop_img, EXEMPLAR_SIZE, round(s_z)); + cv::imwrite("crop_window.jpg",crop_input); + + crop.pre_process( crop_input ); + crop.inference(); + crop.post_process(); + crop_output = crop.output; + + } + + std::this_thread::sleep_for(std::chrono::seconds(1)); + + if(! osd_rotate) + { + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + osd_rotate = true; + } + + { + ScopedTiming st("osd copy", atoi(argv[7])); + memcpy(pic_vaddr, osd_frame.data, osd_frame.cols * osd_frame.rows * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + + } + + cout << ">>>>>>> Play <<<<<<<" << endl; + enter_init = false; + + } + else + { + { + ScopedTiming st("read capture", atoi(argv[7])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[7])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + { + ScopedTiming st("src pipeline: ", atoi(argv[7])); + src.pre_process(src_input); + src.inference(); + src.post_process(); + } + + + src_output = src.output; + + std::vector inputs; + std::vector outputs; + + { + ScopedTiming st("head pipeline: ", atoi(argv[7])); + inputs.clear(); + inputs.push_back(crop_output); + inputs.push_back(src_output); + + std::vector input_shapes = { 1*48*8*8,1*48*16*16 }; + for ( int j = 0; j < 2; j++) + { + auto desc = interp.input_desc(j); + auto shape = interp.input_shape(j); + auto tensor = host_runtime_tensor::create(desc.datatype, shape, hrt::pool_shared).expect("cannot create input tensor"); + auto mapped_buf = std::move(hrt::map(tensor, map_access_::map_write).unwrap()); + + memcpy(reinterpret_cast(mapped_buf.buffer().data()), reinterpret_cast( inputs[j]), input_shapes[j]*4); + auto ret = mapped_buf.unmap(); + ret = hrt::sync(tensor, sync_op_t::sync_write_back, true); + if (!ret.is_ok()) + { + std::cerr << "hrt::sync failed" << std::endl; + std::abort(); + } + + interp.input_tensor(j, tensor).expect("cannot set input tensor"); + } + + for (size_t i = 0; i < interp.outputs_size(); i++) + { + auto desc = interp.output_desc(i); + auto shape = interp.output_shape(i); + auto tensor = host_runtime_tensor::create(desc.datatype, shape, hrt::pool_shared).expect("cannot create output tensor"); + interp.output_tensor(i, tensor).expect("cannot set output tensor"); + } + + auto start = std::chrono::steady_clock::now(); + interp.run().expect("error occurred in running model"); + auto stop = std::chrono::steady_clock::now(); + double duration = std::chrono::duration(stop - start).count(); + + outputs.clear(); + for ( int j = 0; j<2; j++) + { + auto out = interp.output_tensor(j).expect("cannot get output tensor"); + auto mapped_buf = std::move(hrt::map(out, map_access_::map_read).unwrap()); + + outputs.push_back( (float *)mapped_buf.buffer().data() ); + + } + } + + + float* score, * box; + score = outputs[0]; + box = outputs[1]; + + int box_x, box_y, box_h, box_w; + float best_score; + { + ScopedTiming st("head post_process : ", atoi(argv[7])); + post_process(score, box, SENSOR_WIDTH, SENSOR_HEIGHT, box_x, box_y, box_w, box_h, best_score); + } + + + { + ScopedTiming st("draw box", atoi(argv[7])); + if (best_score > thresh) + { + + int r_x1 = box_x; + int r_y1 = box_y; + int r_x2 = (box_x+box_w); + int r_y2 = (box_y+box_h); + + int x1 = r_x1*1.0 / SENSOR_WIDTH * osd_frame.cols; + int y1 = r_y1*1.0 / SENSOR_HEIGHT * osd_frame.rows; + + int w = (r_x2-r_x1)*1.0 / SENSOR_WIDTH * osd_frame.cols; + int h = (r_y2-r_y1)*1.0 / SENSOR_HEIGHT * osd_frame.rows; + + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), cv::Scalar(255, 255,0, 0), 8, 2, 0); // ARGB + + } + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + + { + ScopedTiming st("osd copy", atoi(argv[7])); + + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_01(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + int crop_net_len = atoi(argv[4]); + int src_net_len = atoi(argv[5]); + + float thresh = atof(argv[6]); + + init(); + + Crop crop(argv[1], crop_net_len , atoi(argv[7])); + Crop crop_video(argv[1], crop_net_len ,{SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[7])); + + Src src(argv[2],src_net_len , atoi(argv[7])); + Src src_video(argv[2],src_net_len ,{SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[7])); + + interpreter interp; + + std::ifstream ifs(argv[3], std::ios::binary); + interp.load_model(ifs).expect("Invalid kmodel"); + + + crop_video.pre_process(); + cv::Mat ori_img = cv::imread("ori_img.jpg",cv::IMREAD_UNCHANGED); + + float* pos = get_position(ori_img); + float* cen = get_center(ori_img); + + bool enter_init = true; + + std::vector src_img_vec; + cv::Mat src_img; + cv::Mat src_input; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + float w_z, h_z, s_z; + + { + ScopedTiming st("get_updated_position : ", atoi(argv[7])); + + pos = get_updated_position(); + w_z = pos[0] + CONTEXT_AMOUNT * (pos[0] + pos[1]); + h_z = pos[1] + CONTEXT_AMOUNT * (pos[0] + pos[1]); + s_z = round(sqrt(w_z * h_z)); + } + + { + ScopedTiming st("src_video.pre_process_video : ", atoi(argv[7])); + src_img_vec.clear(); + src_video.pre_process_video( src_img ); + } + + + { + ScopedTiming st("src sub_window : ", atoi(argv[7])); + src_input = sub_window(src_img, INSTANCE_SIZE, round(s_z * INSTANCE_SIZE / EXEMPLAR_SIZE)); + } + + + float *crop_output; + float *src_output; + + if (enter_init) + { + + int seconds = 8; //倒计时时长，单位秒 + time_t endtime = time(NULL) + seconds; //倒计时结束时间 + + while (time(NULL) <= endtime) { + + { + ScopedTiming st("read capture", atoi(argv[7])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[7])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + cout << "倒计时：" << endtime - time(NULL) << "秒" << endl; + + + // 初始化跟踪框. + int init_x0 = MARGIN * osd_frame.cols; + int init_x1 = (1 - MARGIN) * osd_frame.cols; + int init_y0 = osd_frame.rows / 2.0 - ((1 - 2 * MARGIN) * osd_frame.cols) / 2.0; + int init_y1 = osd_frame.rows / 2.0 + ((1 - 2 * MARGIN) * osd_frame.cols) / 2.0; + + int init_w = init_x1 - init_x0; + int init_h = init_y1 - init_y0; + + cv::rectangle(osd_frame, cv::Rect( init_x0,init_y0,init_w,init_h ), cv::Scalar(255, 0,255, 0), 8, 2, 0); // ARGB + + if( (endtime - time(NULL)==2) || (endtime - time(NULL)==3) || (endtime - time(NULL)==4) ) + { + std::cout << " >>>>>> get trackWindow <<<<<<<<" << std::endl; + + crop_video.pre_process(); + + cv::Mat crop_img = cv::imread( "crop_template.jpg",cv::IMREAD_UNCHANGED ); + cv::Mat crop_input = sub_window(crop_img, EXEMPLAR_SIZE, round(s_z)); + cv::imwrite("crop_window.jpg",crop_input); + + crop.pre_process( crop_input ); + crop.inference(); + crop.post_process(); + crop_output = crop.output; + + } + + std::this_thread::sleep_for(std::chrono::seconds(1)); + + { + ScopedTiming st("osd copy", atoi(argv[7])); + memcpy(pic_vaddr, osd_frame.data, osd_frame.cols * osd_frame.rows * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + + } + + cout << ">>>>>>> Play <<<<<<<" << endl; + enter_init = false; + + } + else + { + { + ScopedTiming st("read capture", atoi(argv[7])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[7])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + { + ScopedTiming st("src pipeline: ", atoi(argv[7])); + src.pre_process(src_input); + src.inference(); + src.post_process(); + } + + + src_output = src.output; + + std::vector inputs; + std::vector outputs; + + { + ScopedTiming st("head pipeline: ", atoi(argv[7])); + inputs.clear(); + inputs.push_back(crop_output); + inputs.push_back(src_output); + + std::vector input_shapes = { 1*48*8*8,1*48*16*16 }; + for ( int j = 0; j < 2; j++) + { + auto desc = interp.input_desc(j); + auto shape = interp.input_shape(j); + auto tensor = host_runtime_tensor::create(desc.datatype, shape, hrt::pool_shared).expect("cannot create input tensor"); + auto mapped_buf = std::move(hrt::map(tensor, map_access_::map_write).unwrap()); + + memcpy(reinterpret_cast(mapped_buf.buffer().data()), reinterpret_cast( inputs[j]), input_shapes[j]*4); + auto ret = mapped_buf.unmap(); + ret = hrt::sync(tensor, sync_op_t::sync_write_back, true); + if (!ret.is_ok()) + { + std::cerr << "hrt::sync failed" << std::endl; + std::abort(); + } + + interp.input_tensor(j, tensor).expect("cannot set input tensor"); + } + + for (size_t i = 0; i < interp.outputs_size(); i++) + { + auto desc = interp.output_desc(i); + auto shape = interp.output_shape(i); + auto tensor = host_runtime_tensor::create(desc.datatype, shape, hrt::pool_shared).expect("cannot create output tensor"); + interp.output_tensor(i, tensor).expect("cannot set output tensor"); + } + + auto start = std::chrono::steady_clock::now(); + interp.run().expect("error occurred in running model"); + auto stop = std::chrono::steady_clock::now(); + double duration = std::chrono::duration(stop - start).count(); + + outputs.clear(); + for ( int j = 0; j<2; j++) + { + auto out = interp.output_tensor(j).expect("cannot get output tensor"); + auto mapped_buf = std::move(hrt::map(out, map_access_::map_read).unwrap()); + + outputs.push_back( (float *)mapped_buf.buffer().data() ); + + } + } + + + float* score, * box; + score = outputs[0]; + box = outputs[1]; + + int box_x, box_y, box_h, box_w; + float best_score; + { + ScopedTiming st("head post_process : ", atoi(argv[7])); + post_process(score, box, SENSOR_WIDTH, SENSOR_HEIGHT, box_x, box_y, box_w, box_h, best_score); + } + + + { + ScopedTiming st("draw box", atoi(argv[7])); + if (best_score > thresh) + { + + int r_x1 = box_x; + int r_y1 = box_y; + int r_x2 = (box_x+box_w); + int r_y2 = (box_y+box_h); + + int x1 = r_x1*1.0 / SENSOR_WIDTH * osd_frame.cols; + int y1 = r_y1*1.0 / SENSOR_HEIGHT * osd_frame.rows; + + int w = (r_x2-r_x1)*1.0 / SENSOR_WIDTH * osd_frame.cols; + int h = (r_y2-r_y1)*1.0 / SENSOR_HEIGHT * osd_frame.rows; + + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), cv::Scalar(255, 255,0, 0), 8, 2, 0); // ARGB + + } + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + + { + ScopedTiming st("osd copy", atoi(argv[7])); + + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + int main(int argc, char *argv[]) { @@ -407,14 +1387,62 @@ int main(int argc, char *argv[]) } { - std::thread thread_isp(video_proc, argv); - while (getchar() != 'q') + #if defined(CONFIG_BOARD_K230_CANMV) + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_V2) + { + std::thread thread_isp(video_proc_v2, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230D_CANMV) + { + std::thread thread_isp(video_proc_k230d, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) { - usleep(10000); + std::thread thread_isp(video_proc_01, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); } + #else + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } - isp_stop = true; - thread_isp.join(); + isp_stop = true; + thread_isp.join(); + } + #endif } return 0; diff --git a/src/reference/ai_poc/nanotracker/vi_vo.h b/src/reference/ai_poc/nanotracker/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/nanotracker/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/object_detect_yolov8n/main.cc b/src/reference/ai_poc/object_detect_yolov8n/main.cc index 479b4507c..e183533f2 100644 --- a/src/reference/ai_poc/object_detect_yolov8n/main.cc +++ b/src/reference/ai_poc/object_detect_yolov8n/main.cc @@ -49,7 +49,7 @@ void print_usage(const char *name) << endl; } -void video_proc(char *argv[]) +void video_proc_v1(char *argv[]) { vivcap_start(); @@ -145,6 +145,296 @@ void video_proc(char *argv[]) } +void video_proc_v2(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + OBDet obDet(argv[1], atof(argv[2]), atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + std::vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + obDet.pre_process(); + obDet.inference(); + + obDet.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::Mat osd_frame_tmp; + + { + ScopedTiming st("osd draw", atoi(argv[5])); + Utils::draw_detections(osd_frame, results, {osd_width, osd_height}, {SENSOR_WIDTH, SENSOR_HEIGHT}); + } + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_k230d(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + OBDet obDet(argv[1], atof(argv[2]), atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + std::vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + obDet.pre_process(); + obDet.inference(); + + obDet.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + + { + ScopedTiming st("osd draw", atoi(argv[5])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + Utils::draw_detections(osd_frame, results, {osd_frame.cols, osd_frame.rows}, {SENSOR_WIDTH, SENSOR_HEIGHT}); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_01(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + OBDet obDet(argv[1], atof(argv[2]), atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + std::vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + obDet.pre_process(); + obDet.inference(); + + obDet.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + + { + ScopedTiming st("osd draw", atoi(argv[5])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + Utils::draw_detections(osd_frame, results, {osd_frame.cols, osd_frame.rows}, {SENSOR_WIDTH, SENSOR_HEIGHT}); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + int main(int argc, char *argv[]) { @@ -157,14 +447,62 @@ int main(int argc, char *argv[]) if (strcmp(argv[4], "None") == 0) { - std::thread thread_isp(video_proc, argv); - while (getchar() != 'q') + #if defined(CONFIG_BOARD_K230_CANMV) + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_V2) + { + std::thread thread_isp(video_proc_v2, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230D_CANMV) { - usleep(10000); + std::thread thread_isp(video_proc_k230d, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + std::thread thread_isp(video_proc_01, argv); + while (getchar() != 'q') + { + usleep(10000); + } - isp_stop = true; - thread_isp.join(); + isp_stop = true; + thread_isp.join(); + } + #else + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #endif } else { diff --git a/src/reference/ai_poc/object_detect_yolov8n/vi_vo.h b/src/reference/ai_poc/object_detect_yolov8n/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/object_detect_yolov8n/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/ocr/main.cc b/src/reference/ai_poc/ocr/main.cc index c10bf233d..5ec22335e 100644 --- a/src/reference/ai_poc/ocr/main.cc +++ b/src/reference/ai_poc/ocr/main.cc @@ -107,6 +107,45 @@ void video_proc(char *argv[]) cv::Mat ori_img; std::vector sensor_bgr; cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + + #if defined(CONFIG_BOARD_K230D_CANMV) || defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + cv::Mat ori_img_R = cv::Mat(SENSOR_HEIGHT, SENSOR_WIDTH, CV_8UC1, vaddr); + cv::Mat ori_img_G = cv::Mat(SENSOR_HEIGHT, SENSOR_WIDTH, CV_8UC1, vaddr + 1 * matsize); + cv::Mat ori_img_B = cv::Mat(SENSOR_HEIGHT, SENSOR_WIDTH, CV_8UC1, vaddr + 2 * matsize); + sensor_bgr.push_back(ori_img_B); + sensor_bgr.push_back(ori_img_G); + sensor_bgr.push_back(ori_img_R); + cv::merge(sensor_bgr, ori_img); + + for(int i = 0; i < results.size(); i++) + { + vector vec; + vector sort_vtd(4); + vec.clear(); + for(int j = 0; j < 4; j++) + vec.push_back(results[i].vertices[j]); + cv::RotatedRect rect = cv::minAreaRect(vec); + cv::Point2f ver[4]; + rect.points(ver); + cv::Mat crop; + Utils::warppersp(ori_img, crop, results[i], sort_vtd); + ocrreco.pre_process(crop); + ocrreco.inference(); + vector results2; + ocrreco.post_process(results2); + Utils::draw_ocr_text(float(sort_vtd[3].x), float(sort_vtd[3].y),osd_frame,results2,{osd_height, osd_width}, {SENSOR_WIDTH, SENSOR_HEIGHT}); + } + + { + ScopedTiming st("osd draw", atoi(argv[5])); + Utils::draw_ocr_det_res(osd_frame, results, {osd_height, osd_width}, {SENSOR_WIDTH, SENSOR_HEIGHT}); + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #else + { cv::Mat ori_img_R = cv::Mat(SENSOR_HEIGHT, SENSOR_WIDTH, CV_8UC1, vaddr); cv::Mat ori_img_G = cv::Mat(SENSOR_HEIGHT, SENSOR_WIDTH, CV_8UC1, vaddr + 1 * matsize); cv::Mat ori_img_B = cv::Mat(SENSOR_HEIGHT, SENSOR_WIDTH, CV_8UC1, vaddr + 2 * matsize); @@ -138,6 +177,8 @@ void video_proc(char *argv[]) ScopedTiming st("osd draw", atoi(argv[5])); Utils::draw_ocr_det_res(osd_frame, results, {osd_width, osd_height}, {SENSOR_WIDTH, SENSOR_HEIGHT}); } + } + #endif { ScopedTiming st("osd copy", atoi(argv[5])); diff --git a/src/reference/ai_poc/ocr/vi_vo.h b/src/reference/ai_poc/ocr/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/ocr/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/person_attr/main.cc b/src/reference/ai_poc/person_attr/main.cc index 4a93961fd..1e8cf1022 100644 --- a/src/reference/ai_poc/person_attr/main.cc +++ b/src/reference/ai_poc/person_attr/main.cc @@ -57,7 +57,7 @@ void print_usage(const char *name) << endl; } -void video_proc(char *argv[]) +void video_proc_v1(char *argv[]) { vivcap_start(); @@ -190,6 +190,409 @@ void video_proc(char *argv[]) } +void video_proc_v2(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + personDetect pd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[9])); + float pulc_thresh = atof(argv[6]); + float glasses_thresh = atof(argv[7]); + float hold_thresh = atof(argv[8]); + Pulc pul(argv[5], {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH},pulc_thresh, glasses_thresh, hold_thresh, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[9])); + vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + pd.pre_process(); + pd.inference(); + pd.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + std::string text; + cv::Point origin; + Bbox crop_box; + std::string attr_results; + + for (auto r : results) + { + ScopedTiming st("draw boxes", atoi(argv[9])); + text = pd.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); + + int x1 = r.x1 / SENSOR_WIDTH * osd_width; + int y1 = r.y1 / SENSOR_HEIGHT * osd_height; + + int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_width; + int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_height; + + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), cv::Scalar(255, 255,0, 0), 2, 2, 0); // ARGB + + crop_box = { r.x1,r.y1,(r.x2-r.x1),(r.y2-r.y1) }; + pul.pre_process( crop_box ); + pul.inference(); + attr_results = pul.post_process(); + + origin.x = r.x1; + origin.y = r.y1 + 20; + + float fontScale = 2; + int with = 80; + string gender = pul.GetGender(); + origin.y += with; + cv::putText(osd_frame, gender, origin, cv::FONT_HERSHEY_COMPLEX, fontScale, cv::Scalar(255, 0, 0, 255), 1, 8, 0); + string age = pul.GetAge(); + origin.y += with; + cv::putText(osd_frame, age, origin, cv::FONT_HERSHEY_COMPLEX, fontScale, cv::Scalar(255, 0, 0, 255), 1, 8, 0); + string direction = pul.GetDirection(); + origin.y += with; + cv::putText(osd_frame, direction, origin, cv::FONT_HERSHEY_COMPLEX, fontScale, cv::Scalar(255, 0, 0, 255), 1, 8, 0); + + } + + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_k230d(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + personDetect pd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[9])); + float pulc_thresh = atof(argv[6]); + float glasses_thresh = atof(argv[7]); + float hold_thresh = atof(argv[8]); + Pulc pul(argv[5], {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH},pulc_thresh, glasses_thresh, hold_thresh, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[9])); + vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + pd.pre_process(); + pd.inference(); + pd.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + std::string text; + cv::Point origin; + Bbox crop_box; + std::string attr_results; + + for (auto r : results) + { + ScopedTiming st("draw boxes", atoi(argv[9])); + text = pd.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); + + int x1 = r.x1 / SENSOR_WIDTH * osd_frame.cols; + int y1 = r.y1 / SENSOR_HEIGHT * osd_frame.rows; + + int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_frame.cols; + int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_frame.rows; + + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), cv::Scalar(255, 255,0, 0), 2, 2, 0); // ARGB + + crop_box = { r.x1,r.y1,(r.x2-r.x1),(r.y2-r.y1) }; + pul.pre_process( crop_box ); + pul.inference(); + attr_results = pul.post_process(); + + origin.x = r.x1; + origin.y = r.y1 + 20; + + float fontScale = 2; + int with = 80; + string gender = pul.GetGender(); + origin.y += with; + cv::putText(osd_frame, gender, origin, cv::FONT_HERSHEY_COMPLEX, fontScale, cv::Scalar(255, 0, 0, 255), 1, 8, 0); + string age = pul.GetAge(); + origin.y += with; + cv::putText(osd_frame, age, origin, cv::FONT_HERSHEY_COMPLEX, fontScale, cv::Scalar(255, 0, 0, 255), 1, 8, 0); + string direction = pul.GetDirection(); + origin.y += with; + cv::putText(osd_frame, direction, origin, cv::FONT_HERSHEY_COMPLEX, fontScale, cv::Scalar(255, 0, 0, 255), 1, 8, 0); + + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_01(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + personDetect pd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[9])); + float pulc_thresh = atof(argv[6]); + float glasses_thresh = atof(argv[7]); + float hold_thresh = atof(argv[8]); + Pulc pul(argv[5], {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH},pulc_thresh, glasses_thresh, hold_thresh, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[9])); + vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + pd.pre_process(); + pd.inference(); + pd.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + std::string text; + cv::Point origin; + Bbox crop_box; + std::string attr_results; + + for (auto r : results) + { + ScopedTiming st("draw boxes", atoi(argv[9])); + text = pd.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); + + int x1 = r.x1 / SENSOR_WIDTH * osd_frame.cols; + int y1 = r.y1 / SENSOR_HEIGHT * osd_frame.rows; + + int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_frame.cols; + int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_frame.rows; + + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), cv::Scalar(255, 255,0, 0), 2, 2, 0); // ARGB + + crop_box = { r.x1,r.y1,(r.x2-r.x1),(r.y2-r.y1) }; + pul.pre_process( crop_box ); + pul.inference(); + attr_results = pul.post_process(); + + origin.x = r.x1; + origin.y = r.y1 + 20; + + float fontScale = 2; + int with = 80; + string gender = pul.GetGender(); + origin.y += with; + cv::putText(osd_frame, gender, origin, cv::FONT_HERSHEY_COMPLEX, fontScale, cv::Scalar(255, 0, 0, 255), 1, 8, 0); + string age = pul.GetAge(); + origin.y += with; + cv::putText(osd_frame, age, origin, cv::FONT_HERSHEY_COMPLEX, fontScale, cv::Scalar(255, 0, 0, 255), 1, 8, 0); + string direction = pul.GetDirection(); + origin.y += with; + cv::putText(osd_frame, direction, origin, cv::FONT_HERSHEY_COMPLEX, fontScale, cv::Scalar(255, 0, 0, 255), 1, 8, 0); + + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + int main(int argc, char *argv[]) { @@ -202,14 +605,62 @@ int main(int argc, char *argv[]) if (strcmp(argv[4], "None") == 0) { - std::thread thread_isp(video_proc, argv); - while (getchar() != 'q') + #if defined(CONFIG_BOARD_K230_CANMV) { - usleep(10000); + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); } + #elif defined(CONFIG_BOARD_K230_CANMV_V2) + { + std::thread thread_isp(video_proc_v2, argv); + while (getchar() != 'q') + { + usleep(10000); + } - isp_stop = true; - thread_isp.join(); + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230D_CANMV) + { + std::thread thread_isp(video_proc_k230d, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + std::thread thread_isp(video_proc_01, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #else + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #endif } else { diff --git a/src/reference/ai_poc/person_attr/vi_vo.h b/src/reference/ai_poc/person_attr/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/person_attr/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/person_detect/main.cc b/src/reference/ai_poc/person_detect/main.cc index 2c6f87279..bd655aafd 100644 --- a/src/reference/ai_poc/person_detect/main.cc +++ b/src/reference/ai_poc/person_detect/main.cc @@ -52,7 +52,7 @@ void print_usage(const char *name) << endl; } -void video_proc(char *argv[]) +void video_proc_v1(char *argv[]) { vivcap_start(); @@ -160,6 +160,334 @@ void video_proc(char *argv[]) } +void video_proc_v2(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + personDetect pd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + pd.pre_process(); + pd.inference(); + pd.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + + std::string text; + cv::Point origin; + + for (auto r : results) + { + ScopedTiming st("draw boxes", atoi(argv[5])); + text = pd.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); + + int x1 = r.x1 / SENSOR_WIDTH * osd_width; + int y1 = r.y1 / SENSOR_HEIGHT * osd_height; + + int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_width; + int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_height; + + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), cv::Scalar(255, 255,0, 0), 6, 2, 0); // ARGB + + } + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_k230d(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + personDetect pd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + pd.pre_process(); + pd.inference(); + pd.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + std::string text; + cv::Point origin; + + for (auto r : results) + { + ScopedTiming st("draw boxes", atoi(argv[5])); + text = pd.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); + + int x1 = r.x1 / SENSOR_WIDTH * osd_frame.cols; + int y1 = r.y1 / SENSOR_HEIGHT * osd_frame.rows; + + int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_frame.cols; + int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_frame.rows; + + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), cv::Scalar(255, 255,0, 0), 6, 2, 0); // ARGB + + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_01(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + personDetect pd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + pd.pre_process(); + pd.inference(); + pd.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + std::string text; + cv::Point origin; + + for (auto r : results) + { + ScopedTiming st("draw boxes", atoi(argv[5])); + text = pd.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); + + int x1 = r.x1 / SENSOR_WIDTH * osd_frame.cols; + int y1 = r.y1 / SENSOR_HEIGHT * osd_frame.rows; + + int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_frame.cols; + int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_frame.rows; + + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), cv::Scalar(255, 255,0, 0), 6, 2, 0); // ARGB + + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + int main(int argc, char *argv[]) { @@ -172,14 +500,62 @@ int main(int argc, char *argv[]) if (strcmp(argv[4], "None") == 0) { - std::thread thread_isp(video_proc, argv); - while (getchar() != 'q') + #if defined(CONFIG_BOARD_K230_CANMV) + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_V2) + { + std::thread thread_isp(video_proc_v2, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230D_CANMV) + { + std::thread thread_isp(video_proc_k230d, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) { - usleep(10000); + std::thread thread_isp(video_proc_01, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); } + #else + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } - isp_stop = true; - thread_isp.join(); + isp_stop = true; + thread_isp.join(); + } + #endif } else { diff --git a/src/reference/ai_poc/person_detect/vi_vo.h b/src/reference/ai_poc/person_detect/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/person_detect/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/person_distance/main.cc b/src/reference/ai_poc/person_distance/main.cc index a4cb03772..1edc9a0c0 100644 --- a/src/reference/ai_poc/person_distance/main.cc +++ b/src/reference/ai_poc/person_distance/main.cc @@ -125,23 +125,73 @@ void video_proc(char *argv[]) std::string text; cv::Point origin; - for (auto r : results) + + #if defined(CONFIG_BOARD_K230D_CANMV) { - ScopedTiming st("draw img", atoi(argv[6])); - text = pd.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + for (auto r : results) + { + ScopedTiming st("draw img", atoi(argv[6])); + text = pd.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); - int x1 = r.x1 / SENSOR_WIDTH * osd_width; - int y1 = r.y1 / SENSOR_HEIGHT * osd_height; + int x1 = r.x1 / SENSOR_WIDTH * osd_height; + int y1 = r.y1 / SENSOR_HEIGHT * osd_width; - int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_width; - int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_height; + int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_height; + int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_width; - float dis = detect_distance_people(atof(argv[5]), h); + float dis = detect_distance_people(atof(argv[5]), h); - cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), cv::Scalar(255, 255,0, 0), 6, 2, 0); // ARGB - std::string text = "dis:" + std::to_string(int(dis)) + "cm"; - cv::putText(osd_frame, text, cv::Point(x1,y1+20),cv::FONT_HERSHEY_COMPLEX, 1, cv::Scalar(255, 255, 195, 0), 2); + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), cv::Scalar(255, 255,0, 0), 6, 2, 0); // ARGB + std::string text = "dis:" + std::to_string(int(dis)) + "cm"; + cv::putText(osd_frame, text, cv::Point(x1,y1+20),cv::FONT_HERSHEY_COMPLEX, 1, cv::Scalar(255, 255, 195, 0), 2); + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + for (auto r : results) + { + ScopedTiming st("draw img", atoi(argv[6])); + text = pd.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); + + int x1 = r.x1 / SENSOR_WIDTH * osd_height; + int y1 = r.y1 / SENSOR_HEIGHT * osd_width; + + int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_height; + int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_width; + + float dis = detect_distance_people(atof(argv[5]), h); + + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), cv::Scalar(255, 255,0, 0), 6, 2, 0); // ARGB + std::string text = "dis:" + std::to_string(int(dis)) + "cm"; + cv::putText(osd_frame, text, cv::Point(x1,y1+20),cv::FONT_HERSHEY_COMPLEX, 1, cv::Scalar(255, 255, 195, 0), 2); + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #else + { + for (auto r : results) + { + ScopedTiming st("draw img", atoi(argv[6])); + text = pd.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); + + int x1 = r.x1 / SENSOR_WIDTH * osd_width; + int y1 = r.y1 / SENSOR_HEIGHT * osd_height; + + int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_width; + int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_height; + + float dis = detect_distance_people(atof(argv[5]), h); + + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), cv::Scalar(255, 255,0, 0), 6, 2, 0); // ARGB + std::string text = "dis:" + std::to_string(int(dis)) + "cm"; + cv::putText(osd_frame, text, cv::Point(x1,y1+20),cv::FONT_HERSHEY_COMPLEX, 1, cv::Scalar(255, 255, 195, 0), 2); + } } + #endif { ScopedTiming st("osd copy", atoi(argv[6])); @@ -168,7 +218,6 @@ void video_proc(char *argv[]) std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; std::abort(); } - } diff --git a/src/reference/ai_poc/person_distance/vi_vo.h b/src/reference/ai_poc/person_distance/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/person_distance/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/pose_det_rtsp_plug/big/main.cc b/src/reference/ai_poc/pose_det_rtsp_plug/big/main.cc index 5da5acb5c..97e600c25 100644 --- a/src/reference/ai_poc/pose_det_rtsp_plug/big/main.cc +++ b/src/reference/ai_poc/pose_det_rtsp_plug/big/main.cc @@ -52,7 +52,7 @@ #include "vo_test_case.h" #include "pose_detect.h" -#include "vi_vo.h" +#include "vi_vo_rtsp.h" #include "k_datafifo.h" #define ENABLE_VDEC_DEBUG 1 @@ -200,6 +200,17 @@ static k_s32 sample_vb_init(k_u32 ch_cnt, k_bool osd_enable) config.comm_pool[2].blk_size =OSD_BUF_SIZE; config.comm_pool[2].mode = VB_REMAP_MODE_NOCACHE; + + #if defined(CONFIG_BOARD_K230D_CANMV) + //VB for YUV420SP output + config.comm_pool[0].blk_cnt = 4; + config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; + config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); + //VB for RGB888 output + config.comm_pool[1].blk_cnt = 5; + config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; + config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); + #else //VB for YUV420SP output config.comm_pool[3].blk_cnt = 5; config.comm_pool[3].mode = VB_REMAP_MODE_NOCACHE; @@ -210,6 +221,7 @@ static k_s32 sample_vb_init(k_u32 ch_cnt, k_bool osd_enable) config.comm_pool[4].blk_cnt = 5; config.comm_pool[4].mode = VB_REMAP_MODE_NOCACHE; config.comm_pool[4].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); + #endif ret = kd_mpi_vb_set_config(&config); @@ -674,73 +686,357 @@ int main(int argc, char *argv[]) return -1; } - k_s32 ret; - //**********************encoder**************************************** - //编码器配置，编码通道编号为0 - int chnum = 1; - int ve_ch = 0; - k_u32 output_frames = 10; - k_u32 bitrate = 4000; //kbps - int width = 1280; - int height = 720; - k_venc_rc_mode rc_mode = K_VENC_RC_MODE_CBR; - k_payload_type ve_type = K_PT_H265; - k_venc_profile profile = VENC_PROFILE_H265_MAIN; - memset(&g_venc_conf, 0, sizeof(venc_conf_t)); - - //vb初始化，(venc 以及 vicap) - sample_vb_init(chnum, K_FALSE); - //配置编码通道属性 - k_venc_chn_attr ve_attr; - memset(&ve_attr, 0, sizeof(ve_attr)); - ve_attr.venc_attr.pic_width = width; - ve_attr.venc_attr.pic_height = height; - ve_attr.venc_attr.stream_buf_size = VE_STREAM_BUF_SIZE; - ve_attr.venc_attr.stream_buf_cnt = VE_OUTPUT_BUF_CNT; - ve_attr.rc_attr.rc_mode = rc_mode; - ve_attr.rc_attr.cbr.src_frame_rate = 30; - ve_attr.rc_attr.cbr.dst_frame_rate = 30; - ve_attr.rc_attr.cbr.bit_rate = bitrate; - ve_attr.venc_attr.type = ve_type; - ve_attr.venc_attr.profile = profile; - venc_debug("payload type is H265\n"); - //创建编码通道 - ret = kd_mpi_venc_create_chn(ve_ch, &ve_attr); - CHECK_RET(ret, __func__, __LINE__); - g_venc_sample_status = VENC_SAMPLE_STATUS_INIT; - // 关键帧 - kd_mpi_venc_enable_idr(ve_ch, K_TRUE); - //启动编码通道 - ret = kd_mpi_venc_start_chn(ve_ch); - CHECK_RET(ret, __func__, __LINE__); - g_venc_sample_status = VENC_SAMPLE_STATUS_START; - //编码输出码流设置 - output_info info; - memset(&info, 0, sizeof(info)); - info.ch_id = ve_ch; - info.output_frames = output_frames; - //启动线程将输出的码流写入h265文件 - pthread_create(&g_venc_conf.output_tid, NULL, venc_output_thread, &info); - g_venc_sample_status = VENC_SAMPLE_STATUE_RUNING; - - // 启动 视频流 ai 线程 - std::thread face_det_enc(output_thread, argv); - while (getchar() != 'q') + #if defined(CONFIG_BOARD_K230_CANMV) + { + k_s32 ret; + //**********************encoder**************************************** + //编码器配置，编码通道编号为0 + int chnum = 1; + int ve_ch = 0; + k_u32 output_frames = 10; + k_u32 bitrate = 4000; //kbps + int width = 1280; + int height = 720; + k_venc_rc_mode rc_mode = K_VENC_RC_MODE_CBR; + k_payload_type ve_type = K_PT_H265; + k_venc_profile profile = VENC_PROFILE_H265_MAIN; + memset(&g_venc_conf, 0, sizeof(venc_conf_t)); + + //vb初始化，(venc 以及 vicap) + sample_vb_init(chnum, K_FALSE); + //配置编码通道属性 + k_venc_chn_attr ve_attr; + memset(&ve_attr, 0, sizeof(ve_attr)); + ve_attr.venc_attr.pic_width = width; + ve_attr.venc_attr.pic_height = height; + ve_attr.venc_attr.stream_buf_size = VE_STREAM_BUF_SIZE; + ve_attr.venc_attr.stream_buf_cnt = VE_OUTPUT_BUF_CNT; + ve_attr.rc_attr.rc_mode = rc_mode; + ve_attr.rc_attr.cbr.src_frame_rate = 30; + ve_attr.rc_attr.cbr.dst_frame_rate = 30; + ve_attr.rc_attr.cbr.bit_rate = bitrate; + ve_attr.venc_attr.type = ve_type; + ve_attr.venc_attr.profile = profile; + venc_debug("payload type is H265\n"); + //创建编码通道 + ret = kd_mpi_venc_create_chn(ve_ch, &ve_attr); + CHECK_RET(ret, __func__, __LINE__); + g_venc_sample_status = VENC_SAMPLE_STATUS_INIT; + // 关键帧 + kd_mpi_venc_enable_idr(ve_ch, K_TRUE); + //启动编码通道 + ret = kd_mpi_venc_start_chn(ve_ch); + CHECK_RET(ret, __func__, __LINE__); + g_venc_sample_status = VENC_SAMPLE_STATUS_START; + //编码输出码流设置 + output_info info; + memset(&info, 0, sizeof(info)); + info.ch_id = ve_ch; + info.output_frames = output_frames; + //启动线程将输出的码流写入h265文件 + pthread_create(&g_venc_conf.output_tid, NULL, venc_output_thread, &info); + g_venc_sample_status = VENC_SAMPLE_STATUE_RUNING; + + // 启动 视频流 ai 线程 + std::thread face_det_enc(output_thread, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + face_det_enc.join(); + usleep(10000); + sample_exit(&g_venc_conf); + + // datafifo 退出 + datafifo_deinit(); + //vb退出 + sample_vb_exit(); + + vdec_debug("sample decode done!\n"); + } + #elif defined(CONFIG_BOARD_K230_CANMV_V2) + { + k_s32 ret; + //**********************encoder**************************************** + //编码器配置，编码通道编号为0 + int chnum = 1; + int ve_ch = 0; + k_u32 output_frames = 10; + k_u32 bitrate = 4000; //kbps + int width = 1280; + int height = 720; + k_venc_rc_mode rc_mode = K_VENC_RC_MODE_CBR; + k_payload_type ve_type = K_PT_H265; + k_venc_profile profile = VENC_PROFILE_H265_MAIN; + memset(&g_venc_conf, 0, sizeof(venc_conf_t)); + + //vb初始化，(venc 以及 vicap) + sample_vb_init(chnum, K_FALSE); + //配置编码通道属性 + k_venc_chn_attr ve_attr; + memset(&ve_attr, 0, sizeof(ve_attr)); + ve_attr.venc_attr.pic_width = width; + ve_attr.venc_attr.pic_height = height; + ve_attr.venc_attr.stream_buf_size = VE_STREAM_BUF_SIZE; + ve_attr.venc_attr.stream_buf_cnt = VE_OUTPUT_BUF_CNT; + ve_attr.rc_attr.rc_mode = rc_mode; + ve_attr.rc_attr.cbr.src_frame_rate = 30; + ve_attr.rc_attr.cbr.dst_frame_rate = 30; + ve_attr.rc_attr.cbr.bit_rate = bitrate; + ve_attr.venc_attr.type = ve_type; + ve_attr.venc_attr.profile = profile; + venc_debug("payload type is H265\n"); + //创建编码通道 + ret = kd_mpi_venc_create_chn(ve_ch, &ve_attr); + CHECK_RET(ret, __func__, __LINE__); + g_venc_sample_status = VENC_SAMPLE_STATUS_INIT; + // 关键帧 + kd_mpi_venc_enable_idr(ve_ch, K_TRUE); + //启动编码通道 + ret = kd_mpi_venc_start_chn(ve_ch); + CHECK_RET(ret, __func__, __LINE__); + g_venc_sample_status = VENC_SAMPLE_STATUS_START; + //编码输出码流设置 + output_info info; + memset(&info, 0, sizeof(info)); + info.ch_id = ve_ch; + info.output_frames = output_frames; + //启动线程将输出的码流写入h265文件 + pthread_create(&g_venc_conf.output_tid, NULL, venc_output_thread, &info); + g_venc_sample_status = VENC_SAMPLE_STATUE_RUNING; + + // 启动 视频流 ai 线程 + std::thread face_det_enc(output_thread, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + face_det_enc.join(); + usleep(10000); + sample_exit(&g_venc_conf); + + // datafifo 退出 + datafifo_deinit(); + //vb退出 + sample_vb_exit(); + + vdec_debug("sample decode done!\n"); + } + #elif defined(CONFIG_BOARD_K230D_CANMV) { + k_s32 ret; + //**********************encoder**************************************** + //编码器配置，编码通道编号为0 + int chnum = 1; + int ve_ch = 0; + k_u32 output_frames = 10; + k_u32 bitrate = 4000; //kbps + int width = 1280; + int height = 720; + k_venc_rc_mode rc_mode = K_VENC_RC_MODE_CBR; + k_payload_type ve_type = K_PT_H265; + k_venc_profile profile = VENC_PROFILE_H265_MAIN; + memset(&g_venc_conf, 0, sizeof(venc_conf_t)); + + //vb初始化，(venc 以及 vicap) + sample_vb_init(chnum, K_FALSE); + //配置编码通道属性 + k_venc_chn_attr ve_attr; + memset(&ve_attr, 0, sizeof(ve_attr)); + ve_attr.venc_attr.pic_width = width; + ve_attr.venc_attr.pic_height = height; + ve_attr.venc_attr.stream_buf_size = VE_STREAM_BUF_SIZE; + ve_attr.venc_attr.stream_buf_cnt = VE_OUTPUT_BUF_CNT; + ve_attr.rc_attr.rc_mode = rc_mode; + ve_attr.rc_attr.cbr.src_frame_rate = 30; + ve_attr.rc_attr.cbr.dst_frame_rate = 30; + ve_attr.rc_attr.cbr.bit_rate = bitrate; + ve_attr.venc_attr.type = ve_type; + ve_attr.venc_attr.profile = profile; + venc_debug("payload type is H265\n"); + //创建编码通道 + ret = kd_mpi_venc_create_chn(ve_ch, &ve_attr); + CHECK_RET(ret, __func__, __LINE__); + g_venc_sample_status = VENC_SAMPLE_STATUS_INIT; + // 关键帧 + kd_mpi_venc_enable_idr(ve_ch, K_TRUE); + //启动编码通道 + ret = kd_mpi_venc_start_chn(ve_ch); + CHECK_RET(ret, __func__, __LINE__); + g_venc_sample_status = VENC_SAMPLE_STATUS_START; + //编码输出码流设置 + output_info info; + memset(&info, 0, sizeof(info)); + info.ch_id = ve_ch; + info.output_frames = output_frames; + //启动线程将输出的码流写入h265文件 + pthread_create(&g_venc_conf.output_tid, NULL, venc_output_thread, &info); + g_venc_sample_status = VENC_SAMPLE_STATUE_RUNING; + + // 启动 视频流 ai 线程 + std::thread face_det_enc(output_thread, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + face_det_enc.join(); usleep(10000); + sample_exit(&g_venc_conf); + + // datafifo 退出 + datafifo_deinit(); + //vb退出 + sample_vb_exit(); + + vdec_debug("sample decode done!\n"); } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + k_s32 ret; + //**********************encoder**************************************** + //编码器配置，编码通道编号为0 + int chnum = 1; + int ve_ch = 0; + k_u32 output_frames = 10; + k_u32 bitrate = 4000; //kbps + int width = 1280; + int height = 720; + k_venc_rc_mode rc_mode = K_VENC_RC_MODE_CBR; + k_payload_type ve_type = K_PT_H265; + k_venc_profile profile = VENC_PROFILE_H265_MAIN; + memset(&g_venc_conf, 0, sizeof(venc_conf_t)); + + //vb初始化，(venc 以及 vicap) + sample_vb_init(chnum, K_FALSE); + //配置编码通道属性 + k_venc_chn_attr ve_attr; + memset(&ve_attr, 0, sizeof(ve_attr)); + ve_attr.venc_attr.pic_width = width; + ve_attr.venc_attr.pic_height = height; + ve_attr.venc_attr.stream_buf_size = VE_STREAM_BUF_SIZE; + ve_attr.venc_attr.stream_buf_cnt = VE_OUTPUT_BUF_CNT; + ve_attr.rc_attr.rc_mode = rc_mode; + ve_attr.rc_attr.cbr.src_frame_rate = 30; + ve_attr.rc_attr.cbr.dst_frame_rate = 30; + ve_attr.rc_attr.cbr.bit_rate = bitrate; + ve_attr.venc_attr.type = ve_type; + ve_attr.venc_attr.profile = profile; + venc_debug("payload type is H265\n"); + //创建编码通道 + ret = kd_mpi_venc_create_chn(ve_ch, &ve_attr); + CHECK_RET(ret, __func__, __LINE__); + g_venc_sample_status = VENC_SAMPLE_STATUS_INIT; + // 关键帧 + kd_mpi_venc_enable_idr(ve_ch, K_TRUE); + //启动编码通道 + ret = kd_mpi_venc_start_chn(ve_ch); + CHECK_RET(ret, __func__, __LINE__); + g_venc_sample_status = VENC_SAMPLE_STATUS_START; + //编码输出码流设置 + output_info info; + memset(&info, 0, sizeof(info)); + info.ch_id = ve_ch; + info.output_frames = output_frames; + //启动线程将输出的码流写入h265文件 + pthread_create(&g_venc_conf.output_tid, NULL, venc_output_thread, &info); + g_venc_sample_status = VENC_SAMPLE_STATUE_RUNING; + + // 启动 视频流 ai 线程 + std::thread face_det_enc(output_thread, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + face_det_enc.join(); + usleep(10000); + sample_exit(&g_venc_conf); + + // datafifo 退出 + datafifo_deinit(); + //vb退出 + sample_vb_exit(); + + vdec_debug("sample decode done!\n"); + } + #else + { + k_s32 ret; + //**********************encoder**************************************** + //编码器配置，编码通道编号为0 + int chnum = 1; + int ve_ch = 0; + k_u32 output_frames = 10; + k_u32 bitrate = 4000; //kbps + int width = 1280; + int height = 720; + k_venc_rc_mode rc_mode = K_VENC_RC_MODE_CBR; + k_payload_type ve_type = K_PT_H265; + k_venc_profile profile = VENC_PROFILE_H265_MAIN; + memset(&g_venc_conf, 0, sizeof(venc_conf_t)); + + //vb初始化，(venc 以及 vicap) + sample_vb_init(chnum, K_FALSE); + //配置编码通道属性 + k_venc_chn_attr ve_attr; + memset(&ve_attr, 0, sizeof(ve_attr)); + ve_attr.venc_attr.pic_width = width; + ve_attr.venc_attr.pic_height = height; + ve_attr.venc_attr.stream_buf_size = VE_STREAM_BUF_SIZE; + ve_attr.venc_attr.stream_buf_cnt = VE_OUTPUT_BUF_CNT; + ve_attr.rc_attr.rc_mode = rc_mode; + ve_attr.rc_attr.cbr.src_frame_rate = 30; + ve_attr.rc_attr.cbr.dst_frame_rate = 30; + ve_attr.rc_attr.cbr.bit_rate = bitrate; + ve_attr.venc_attr.type = ve_type; + ve_attr.venc_attr.profile = profile; + venc_debug("payload type is H265\n"); + //创建编码通道 + ret = kd_mpi_venc_create_chn(ve_ch, &ve_attr); + CHECK_RET(ret, __func__, __LINE__); + g_venc_sample_status = VENC_SAMPLE_STATUS_INIT; + // 关键帧 + kd_mpi_venc_enable_idr(ve_ch, K_TRUE); + //启动编码通道 + ret = kd_mpi_venc_start_chn(ve_ch); + CHECK_RET(ret, __func__, __LINE__); + g_venc_sample_status = VENC_SAMPLE_STATUS_START; + //编码输出码流设置 + output_info info; + memset(&info, 0, sizeof(info)); + info.ch_id = ve_ch; + info.output_frames = output_frames; + //启动线程将输出的码流写入h265文件 + pthread_create(&g_venc_conf.output_tid, NULL, venc_output_thread, &info); + g_venc_sample_status = VENC_SAMPLE_STATUE_RUNING; + + // 启动 视频流 ai 线程 + std::thread face_det_enc(output_thread, argv); + while (getchar() != 'q') + { + usleep(10000); + } - isp_stop = true; - face_det_enc.join(); - usleep(10000); - sample_exit(&g_venc_conf); + isp_stop = true; + face_det_enc.join(); + usleep(10000); + sample_exit(&g_venc_conf); - // datafifo 退出 - datafifo_deinit(); - //vb退出 - sample_vb_exit(); + // datafifo 退出 + datafifo_deinit(); + //vb退出 + sample_vb_exit(); - vdec_debug("sample decode done!\n"); + vdec_debug("sample decode done!\n"); + } + #endif return 0; } diff --git a/src/reference/ai_poc/pose_det_rtsp_plug/big/vi_vo.h b/src/reference/ai_poc/pose_det_rtsp_plug/big/vi_vo_rtsp.h similarity index 87% rename from src/reference/ai_poc/pose_det_rtsp_plug/big/vi_vo.h rename to src/reference/ai_poc/pose_det_rtsp_plug/big/vi_vo_rtsp.h index f84e75475..81cfe8b94 100644 --- a/src/reference/ai_poc/pose_det_rtsp_plug/big/vi_vo.h +++ b/src/reference/ai_poc/pose_det_rtsp_plug/big/vi_vo_rtsp.h @@ -67,6 +67,30 @@ #define osd_id K_VO_OSD3 #define osd_width (1280) #define osd_height (720) +#elif defined(CONFIG_BOARD_K230D_CANMV) +#define SENSOR_CHANNEL (3) +#define SENSOR_HEIGHT (720) +#define SENSOR_WIDTH (1280) +#define ISP_CHN0_WIDTH (800) +#define ISP_CHN0_HEIGHT (480) +#define ISP_INPUT_WIDTH (1920) +#define ISP_INPUT_HEIGHT (1080) +#define vicap_install_osd (1) +#define osd_id K_VO_OSD3 +#define osd_width (480) +#define osd_height (800) +#elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) +#define SENSOR_CHANNEL (3) +#define SENSOR_HEIGHT (720) +#define SENSOR_WIDTH (1280) +#define ISP_CHN0_WIDTH (800) +#define ISP_CHN0_HEIGHT (480) +#define ISP_INPUT_WIDTH (1920) +#define ISP_INPUT_HEIGHT (1080) +#define vicap_install_osd (1) +#define osd_id K_VO_OSD3 +#define osd_width (480) +#define osd_height (800) #else #define SENSOR_CHANNEL (3) // isp通道数 #define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 @@ -288,6 +312,10 @@ static k_s32 sample_connector_init(void) k_s32 connector_fd; #if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; +#elif defined(CONFIG_BOARD_K230D_CANMV) + k_connector_type connector_type = ST7701_V1_MIPI_2LAN_480X800_30FPS; +#elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + k_connector_type connector_type = ST7701_V1_MIPI_2LAN_480X800_30FPS; #else k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; #endif @@ -327,10 +355,23 @@ static k_s32 vo_layer_vdss_bind_vo_config(void) sample_connector_init(); // config lyaer + #if defined(CONFIG_BOARD_K230D_CANMV) + info.act_size.width = ISP_CHN0_HEIGHT;//1080;//640;//1080; + info.act_size.height = ISP_CHN0_WIDTH;//1920;//480;//1920; + info.format = PIXEL_FORMAT_YVU_PLANAR_420; + info.func = K_ROTATION_90; + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + info.act_size.width = ISP_CHN0_HEIGHT;//1080;//640;//1080; + info.act_size.height = ISP_CHN0_WIDTH;//1920;//480;//1920; + info.format = PIXEL_FORMAT_YVU_PLANAR_420; + info.func = K_ROTATION_90; + #else info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; info.format = PIXEL_FORMAT_YVU_PLANAR_420; info.func = 0;//K_ROTATION_180;////K_ROTATION_90; + #endif + info.global_alptha = 0xff; info.offset.x = 0;//(1080-w)/2, info.offset.y = 0;//(1920-h)/2; @@ -382,6 +423,12 @@ int vivcap_start() #elif defined(CONFIG_BOARD_K230_CANMV_V2) sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; kd_mpi_vicap_set_mclk(VICAP_MCLK0, VICAP_PLL0_CLK_DIV4, 16, 1); +#elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; + kd_mpi_vicap_set_mclk(VICAP_MCLK0, VICAP_PLL0_CLK_DIV4, 16, 1); +#elif defined(CONFIG_BOARD_K230D_CANMV) + sensor_type = OV_OV5647_MIPI_1920X1080_30FPS_10BIT_LINEAR; + kd_mpi_vicap_set_mclk(VICAP_MCLK0, VICAP_PLL0_CLK_DIV4, 16, 1); #else sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; #endif @@ -393,12 +440,21 @@ int vivcap_start() if(vicap_install_osd == 1) { + #if defined(CONFIG_BOARD_K230D_CANMV) + memset(&pool_config, 0, sizeof(pool_config)); + pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); + pool_config.blk_cnt = 2; + pool_config.mode = VB_REMAP_MODE_NOCACHE; + pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 + g_pool_id = pool_id; + #else memset(&pool_config, 0, sizeof(pool_config)); pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); pool_config.blk_cnt = 4; pool_config.mode = VB_REMAP_MODE_NOCACHE; pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 g_pool_id = pool_id; + #endif printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); } @@ -413,7 +469,7 @@ int vivcap_start() memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); dev_attr.acq_win.h_start = 0; dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) +#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) || defined(CONFIG_BOARD_K230D_CANMV) || defined(CONFIG_BOARD_K230_CANMV_01STUDIO) dev_attr.acq_win.width = ISP_CHN0_WIDTH; dev_attr.acq_win.height = ISP_CHN0_HEIGHT; #else @@ -445,7 +501,7 @@ int vivcap_start() chn_attr.out_win.height = ISP_CHN0_HEIGHT; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) +#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) || defined(CONFIG_BOARD_K230D_CANMV) || defined(CONFIG_BOARD_K230_CANMV_01STUDIO) chn_attr.crop_win = dev_attr.acq_win; #else // chn_attr.crop_win = dev_attr.acq_win; @@ -494,7 +550,7 @@ int vivcap_start() chn_attr.out_win.height = SENSOR_HEIGHT; // chn_attr.crop_win = dev_attr.acq_win; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) +#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) || defined(CONFIG_BOARD_K230D_CANMV) || defined(CONFIG_BOARD_K230_CANMV_01STUDIO) chn_attr.crop_win = dev_attr.acq_win; #else chn_attr.crop_win.h_start = 768; diff --git a/src/reference/ai_poc/pose_detect/main.cc b/src/reference/ai_poc/pose_detect/main.cc index fb3bbc561..8545bcc00 100644 --- a/src/reference/ai_poc/pose_detect/main.cc +++ b/src/reference/ai_poc/pose_detect/main.cc @@ -53,7 +53,7 @@ void print_usage(const char *name) } -void video_proc(char *argv[]) +void video_proc_v1(char *argv[]) { vivcap_start(); @@ -156,6 +156,321 @@ void video_proc(char *argv[]) } +void video_proc_v2(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + poseDetect pd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + cv::Vec4d params = pd.params; + + std::vector result; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + // results.clear(); + result.clear(); + + pd.pre_process(); + pd.inference(); + bool find_ = pd.post_process(result,params); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + + if(find_) + { + Utils::DrawPred_video(osd_frame,{SENSOR_WIDTH,SENSOR_HEIGHT}, result, SKELETON, KPS_COLORS, LIMB_COLORS); + } + else + { + cout << "not find!\n"; + } + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_k230d(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + poseDetect pd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + cv::Vec4d params = pd.params; + + std::vector result; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + // results.clear(); + result.clear(); + + pd.pre_process(); + pd.inference(); + bool find_ = pd.post_process(result,params); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + if(find_) + { + Utils::DrawPred_video(osd_frame,{SENSOR_WIDTH,SENSOR_HEIGHT}, result, SKELETON, KPS_COLORS, LIMB_COLORS); + } + else + { + cout << "not find!\n"; + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_01(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + poseDetect pd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + cv::Vec4d params = pd.params; + + std::vector result; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + // results.clear(); + result.clear(); + + pd.pre_process(); + pd.inference(); + bool find_ = pd.post_process(result,params); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + if(find_) + { + Utils::DrawPred_video(osd_frame,{SENSOR_WIDTH,SENSOR_HEIGHT}, result, SKELETON, KPS_COLORS, LIMB_COLORS); + } + else + { + cout << "not find!\n"; + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + int main(int argc, char *argv[]) { @@ -168,14 +483,62 @@ int main(int argc, char *argv[]) if (strcmp(argv[4], "None") == 0) { - std::thread thread_isp(video_proc, argv); - while (getchar() != 'q') + #if defined(CONFIG_BOARD_K230_CANMV) + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_V2) + { + std::thread thread_isp(video_proc_v2, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230D_CANMV) + { + std::thread thread_isp(video_proc_k230d, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) { - usleep(10000); + std::thread thread_isp(video_proc_01, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); } + #else + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } - isp_stop = true; - thread_isp.join(); + isp_stop = true; + thread_isp.join(); + } + #endif } else { diff --git a/src/reference/ai_poc/pose_detect/vi_vo.h b/src/reference/ai_poc/pose_detect/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/pose_detect/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/pphumanseg/main.cc b/src/reference/ai_poc/pphumanseg/main.cc index 4866f4f36..89dabcc66 100755 --- a/src/reference/ai_poc/pphumanseg/main.cc +++ b/src/reference/ai_poc/pphumanseg/main.cc @@ -49,7 +49,7 @@ void print_usage(const char *name) << endl; } -void video_proc(char *argv[]) +void video_proc_v1(char *argv[]) { vivcap_start(); @@ -138,6 +138,277 @@ void video_proc(char *argv[]) } +void video_proc_v2(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + SEG seg(argv[1],{SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[3])); + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[3])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + seg.pre_process(); + seg.inference(); + cv::Mat mask = seg.post_process( ); + + cv::resize(mask, mask, cv::Size(osd_width, osd_height), 0, 0); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + osd_frame.setTo(cv::Scalar(255,255, 255, 255), mask); + + { + ScopedTiming st("osd copy", atoi(argv[3])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_k230d(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + SEG seg(argv[1],{SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[3])); + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[3])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + seg.pre_process(); + seg.inference(); + cv::Mat mask = seg.post_process( ); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + cv::resize(mask, mask, cv::Size(osd_frame.cols, osd_frame.rows), 0, 0); + osd_frame.setTo(cv::Scalar(255,255, 255, 255), mask); + + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + { + ScopedTiming st("osd copy", atoi(argv[3])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_01(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + SEG seg(argv[1],{SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[3])); + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[3])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + seg.pre_process(); + seg.inference(); + cv::Mat mask = seg.post_process( ); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + cv::resize(mask, mask, cv::Size(osd_frame.cols, osd_frame.rows), 0, 0); + osd_frame.setTo(cv::Scalar(255,255, 255, 255), mask); + + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + { + ScopedTiming st("osd copy", atoi(argv[3])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + int main(int argc, char *argv[]) { @@ -150,14 +421,62 @@ int main(int argc, char *argv[]) if (strcmp(argv[2], "None") == 0) { - std::thread thread_isp(video_proc, argv); - while (getchar() != 'q') + #if defined(CONFIG_BOARD_K230_CANMV) { - usleep(10000); + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); } + #elif defined(CONFIG_BOARD_K230_CANMV_V2) + { + std::thread thread_isp(video_proc_v2, argv); + while (getchar() != 'q') + { + usleep(10000); + } - isp_stop = true; - thread_isp.join(); + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230D_CANMV) + { + std::thread thread_isp(video_proc_k230d, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + std::thread thread_isp(video_proc_01, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #else + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #endif } else { diff --git a/src/reference/ai_poc/pphumanseg/vi_vo.h b/src/reference/ai_poc/pphumanseg/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/pphumanseg/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/puzzle_game/main.cc b/src/reference/ai_poc/puzzle_game/main.cc index a9055b3d6..5a640191c 100644 --- a/src/reference/ai_poc/puzzle_game/main.cc +++ b/src/reference/ai_poc/puzzle_game/main.cc @@ -50,7 +50,7 @@ void print_usage(const char *name) << endl; } -void video_proc(char *argv[]) +void video_proc_v1(char *argv[]) { vivcap_start(); // 设置osd参数 @@ -346,6 +346,882 @@ void video_proc(char *argv[]) } } +void video_proc_v2(char *argv[]) +{ + vivcap_start(); + // 设置osd参数 + k_video_frame_info vf_info; + void *pic_vaddr = NULL; // osd + memset(&vf_info, 0, sizeof(vf_info)); + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory,get isp memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + int puzzle_width; + int puzzle_height; + int puzzle_ori_width; + int puzzle_ori_height; + #if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) + puzzle_width = osd_height; + puzzle_height = osd_height; + puzzle_ori_width = osd_width-puzzle_height-5; + puzzle_ori_height = osd_width-puzzle_height-5; + #else + puzzle_width = osd_width; + puzzle_height = osd_width; + puzzle_ori_width = osd_height-puzzle_height-5; + puzzle_ori_height = osd_height-puzzle_height-5; + #endif + + + int level = atoi(argv[6]); + int every_block_width = puzzle_width/level; + int every_block_height = puzzle_height/level; + float ratio_num = every_block_width/360.0; + int blank_x = 0; + int blank_y = 0; + std::vector direction_vec = {-1,1,-1,1}; + + cv::Mat image_puzzle_argb; + cv::Mat image_puzzle_ori; + cv::Mat osd_frame_tmp(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + + int exact_division_x = 0; + int exact_division_y = 0; + int distance_tow_points = osd_width; + int distance_thred = every_block_width*0.3; + cv::Rect move_rect; + cv::Mat move_mat; + cv::Mat copy_blank; + cv::Mat copy_move; + + if (strcmp(argv[5], "None") == 0) + { + image_puzzle_argb = cv::Mat(puzzle_height, puzzle_width, CV_8UC4, cv::Scalar(200, 130, 150, 100)); + for(int i = 0; i < level*level; i++) + { + cv::rectangle(image_puzzle_argb, cv::Rect((i%level)*every_block_width, (i/level)*every_block_height, every_block_width, every_block_height), cv::Scalar(255, 0, 0, 0), 5); + std::string classString = to_string(i); + cv::Size textSize = cv::getTextSize(classString, cv::FONT_HERSHEY_DUPLEX, 7*ratio_num, 8*ratio_num, 0); + cv::putText(image_puzzle_argb, classString, cv::Point((i%level)*every_block_width + (every_block_width-textSize.width)/2,(i/level)*every_block_height + (every_block_height+textSize.height)/2),cv::FONT_HERSHEY_COMPLEX, 7*ratio_num, cv::Scalar(255, 0, 0, 255), 8*ratio_num, 0); + } + } + else + { + Utils::bin_2_mat(argv[5], puzzle_width, puzzle_height, image_puzzle_argb); + for(int i = 0; i < level*level; i++) + { + cv::rectangle(image_puzzle_argb, cv::Rect((i%level)*every_block_width, (i/level)*every_block_height, every_block_width, every_block_height), cv::Scalar(255, 0, 0, 0), 5); + } + } + + cv::Mat blank_block_puzzle(every_block_height, every_block_width, CV_8UC4, cv::Scalar(220, 114, 114, 114)); + cv::Mat image_puzzle_argb_blank = image_puzzle_argb(cv::Rect(0,0,every_block_width,every_block_height)); + blank_block_puzzle.copyTo(image_puzzle_argb_blank); + + cv::resize(image_puzzle_argb, image_puzzle_ori, cv::Size(puzzle_ori_width, puzzle_ori_height), cv::INTER_AREA); + cv::Mat copy_ori_image_0 = osd_frame_tmp(cv::Rect(0,0,puzzle_width,puzzle_height)); + image_puzzle_argb.copyTo(copy_ori_image_0); + cv::Mat copy_ori_image_1; + #if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) + copy_ori_image_1 = osd_frame_tmp(cv::Rect(puzzle_width+2,(1080-puzzle_ori_height)/2,puzzle_ori_width,puzzle_ori_height)); + image_puzzle_ori.copyTo(copy_ori_image_1); + #else + copy_ori_image_1 = osd_frame_tmp(cv::Rect((1080-puzzle_ori_width)/2,puzzle_height+2,puzzle_ori_width,puzzle_ori_height)); + image_puzzle_ori.copyTo(copy_ori_image_1); + #endif + cv::Mat blank_block(every_block_height, every_block_width, CV_8UC4, cv::Scalar(220, 114, 114, 114)); + + + srand((unsigned)time(NULL)); + for(int i = 0; i < level*10; i++) + { + int k230_random = rand() % 4; + int blank_x_tmp = blank_x; + int blank_y_tmp = blank_y; + if (k230_random < 2) + { + blank_x_tmp = blank_x + direction_vec[k230_random]; + } + else + { + blank_y_tmp = blank_y + direction_vec[k230_random]; + } + + if((blank_x_tmp >= 0 && blank_x_tmp < level) && (blank_y_tmp >= 0 && blank_y_tmp < level) && (std::abs(blank_x - blank_x_tmp) <= 1 && std::abs(blank_y - blank_y_tmp) <= 1)) + { + move_rect = cv::Rect(blank_x_tmp*every_block_width,blank_y_tmp*every_block_height,every_block_width,every_block_height); + move_mat = osd_frame_tmp(move_rect); + + copy_blank = osd_frame_tmp(cv::Rect(blank_x_tmp*every_block_width,blank_y_tmp*every_block_height,every_block_width,every_block_height)); + copy_move = osd_frame_tmp(cv::Rect(blank_x*every_block_width,blank_y*every_block_height,every_block_width,every_block_height)); + move_mat.copyTo(copy_move); + blank_block.copyTo(copy_blank); + + blank_x = blank_x_tmp; + blank_y = blank_y_tmp; + } + } + + HandDetection hd(argv[1], atof(argv[2]), atof(argv[3]), {SENSOR_WIDTH, SENSOR_HEIGHT}, {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[7])); + sync(); + HandKeypoint hk(argv[4], {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[7])); + sync(); + + std::vector results; + std::vector two_point; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[7])); + // 从vivcap中读取一帧图像到dump_info + memset(&dump_info, 0, sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + { + ScopedTiming st("isp copy", atoi(argv[7])); + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + two_point.clear(); + + hd.pre_process(); + hd.inference(); + hd.post_process(results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::Mat osd_frame_vertical; + + float max_area_hand = 0; + int max_id_hand = -1; + for (int i = 0; i < results.size(); ++i) + { + float area_i = (results[i].x2 - results[i].x1) * (results[i].y2 - results[i].y1); + if (area_i > max_area_hand) + { + max_area_hand = area_i; + max_id_hand = i; + } + } + + if (max_id_hand != -1) + { + std::string text = hd.labels_[results[max_id_hand].label] + ":" + std::to_string(round(results[max_id_hand].score * 100) / 100.0); + + int w = results[max_id_hand].x2 - results[max_id_hand].x1 + 1; + int h = results[max_id_hand].y2 - results[max_id_hand].y1 + 1; + + int length = std::max(w,h)/2; + int cx = (results[max_id_hand].x1+results[max_id_hand].x2)/2; + int cy = (results[max_id_hand].y1+results[max_id_hand].y2)/2; + int ratio_num = 1.26*length; + + int x1_1 = std::max(0,cx-ratio_num); + int y1_1 = std::max(0,cy-ratio_num); + int x2_1 = std::min(SENSOR_WIDTH-1, cx+ratio_num); + int y2_1 = std::min(SENSOR_HEIGHT-1, cy+ratio_num); + int w_1 = x2_1 - x1_1 + 1; + int h_1 = y2_1 - y1_1 + 1; + + struct Bbox bbox = {x:x1_1,y:y1_1,w:w_1,h:h_1}; + hk.pre_process(bbox); + + hk.inference(); + + { + ScopedTiming st("osd draw", atoi(argv[7])); + hk.draw_keypoints(osd_frame, text, bbox, false, two_point); + } + } + + if(max_id_hand != -1 && two_point[1] <= SENSOR_WIDTH) + { + distance_tow_points = std::sqrt(std::pow((two_point[0] - two_point[2]),2) + std::pow((two_point[1] - two_point[3]),2))* 1.0 / SENSOR_WIDTH * osd_width; + exact_division_x = (two_point[0] * 1.0 / SENSOR_WIDTH * osd_width)/every_block_width; + exact_division_y = (two_point[1] * 1.0 / SENSOR_HEIGHT * osd_height)/every_block_height; + if(distance_tow_points < distance_thred && exact_division_x >= 0 && exact_division_x < level && exact_division_y >= 0 && exact_division_y < level) + { + if(std::abs(blank_x - exact_division_x) == 1 && std::abs(blank_y - exact_division_y) == 0) + { + move_rect = cv::Rect(exact_division_x*every_block_width,exact_division_y*every_block_height,every_block_width,every_block_height); + move_mat = osd_frame_tmp(move_rect); + + copy_blank = osd_frame_tmp(cv::Rect(exact_division_x*every_block_width,exact_division_y*every_block_height,every_block_width,every_block_height)); + copy_move = osd_frame_tmp(cv::Rect(blank_x*every_block_width,blank_y*every_block_height,every_block_width,every_block_height)); + move_mat.copyTo(copy_move); + blank_block.copyTo(copy_blank); + + blank_x = exact_division_x; + } + else if (std::abs(blank_y - exact_division_y) == 1 && std::abs(blank_x - exact_division_x) == 0) + { + move_rect = cv::Rect(exact_division_x*every_block_width,exact_division_y*every_block_height,every_block_width,every_block_height); + move_mat = osd_frame_tmp(move_rect); + + copy_blank = osd_frame_tmp(cv::Rect(exact_division_x*every_block_width,exact_division_y*every_block_height,every_block_width,every_block_height)); + copy_move = osd_frame_tmp(cv::Rect(blank_x*every_block_width,blank_y*every_block_height,every_block_width,every_block_height)); + move_mat.copyTo(copy_move); + blank_block.copyTo(copy_blank); + + blank_y = exact_division_y; + } + + osd_frame = osd_frame_tmp.clone(); + if(two_point.size() > 0) + { + int x1 = two_point[0] * 1.0 / SENSOR_WIDTH * osd_width; + int y1 = two_point[1] * 1.0 / SENSOR_HEIGHT * osd_height; + cv::circle(osd_frame, cv::Point(x1, y1), 10, cv::Scalar(255, 0, 255, 255), 10); + } + } + else + { + osd_frame = osd_frame_tmp.clone(); + if(two_point.size() > 0) + { + int x1 = two_point[0] * 1.0 / SENSOR_WIDTH * osd_width; + int y1 = two_point[1] * 1.0 / SENSOR_HEIGHT * osd_height; + cv::circle(osd_frame, cv::Point(x1, y1), 10, cv::Scalar(255, 255, 255, 0), 10); + } + } + sync(); + } + else + { + osd_frame = osd_frame_tmp.clone(); + } + + { + ScopedTiming st("osd copy", atoi(argv[7])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + // 显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id + 3, &vf_info); // K_VO_OSD0 + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } +} + +void video_proc_k230d(char *argv[]) +{ + vivcap_start(); + // 设置osd参数 + k_video_frame_info vf_info; + void *pic_vaddr = NULL; // osd + memset(&vf_info, 0, sizeof(vf_info)); + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory,get isp memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + int puzzle_width; + int puzzle_height; + int puzzle_ori_width; + int puzzle_ori_height; + puzzle_width = osd_width; + puzzle_height = osd_width; + puzzle_ori_width = osd_height-puzzle_height-5; + puzzle_ori_height = osd_height-puzzle_height-5; + + + int level = atoi(argv[6]); + int every_block_width = puzzle_width/level; + int every_block_height = puzzle_height/level; + float ratio_num = every_block_width/360.0; + int blank_x = 0; + int blank_y = 0; + std::vector direction_vec = {-1,1,-1,1}; + + cv::Mat image_puzzle_argb; + cv::Mat image_puzzle_ori; + cv::Mat osd_frame_tmp(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame_tmp, osd_frame_tmp, cv::ROTATE_90_COUNTERCLOCKWISE); + + int exact_division_x = 0; + int exact_division_y = 0; + int distance_tow_points = osd_width; + int distance_thred = every_block_width*0.3; + cv::Rect move_rect; + cv::Mat move_mat; + cv::Mat copy_blank; + cv::Mat copy_move; + + // if (strcmp(argv[5], "None") == 0) + // { + image_puzzle_argb = cv::Mat(puzzle_height, puzzle_width, CV_8UC4, cv::Scalar(200, 130, 150, 100)); + for(int i = 0; i < level*level; i++) + { + cv::rectangle(image_puzzle_argb, cv::Rect((i%level)*every_block_width, (i/level)*every_block_height, every_block_width, every_block_height), cv::Scalar(255, 0, 0, 0), 5); + std::string classString = to_string(i); + cv::Size textSize = cv::getTextSize(classString, cv::FONT_HERSHEY_DUPLEX, 7*ratio_num, 8*ratio_num, 0); + cv::putText(image_puzzle_argb, classString, cv::Point((i%level)*every_block_width + (every_block_width-textSize.width)/2,(i/level)*every_block_height + (every_block_height+textSize.height)/2),cv::FONT_HERSHEY_COMPLEX, 7*ratio_num, cv::Scalar(255, 0, 0, 255), 8*ratio_num, 0); + } + // } + // else + // { + // // Utils::bin_2_mat(argv[5], puzzle_width, puzzle_height, image_puzzle_argb); + // // for(int i = 0; i < level*level; i++) + // // { + // // cv::rectangle(image_puzzle_argb, cv::Rect((i%level)*every_block_width, (i/level)*every_block_height, every_block_width, every_block_height), cv::Scalar(255, 0, 0, 0), 5); + // // } + // std::cout << "Non-empty is not supported !!!" << std::endl; + // return ; + // } + + cv::Mat blank_block_puzzle(every_block_height, every_block_width, CV_8UC4, cv::Scalar(220, 114, 114, 114)); + cv::Mat image_puzzle_argb_blank = image_puzzle_argb(cv::Rect(0,0,every_block_width,every_block_height)); + blank_block_puzzle.copyTo(image_puzzle_argb_blank); + + cv::resize(image_puzzle_argb, image_puzzle_ori, cv::Size(puzzle_ori_width, puzzle_ori_height), cv::INTER_AREA); + cv::Mat copy_ori_image_0 = osd_frame_tmp(cv::Rect(0,0,puzzle_width,puzzle_height)); + image_puzzle_argb.copyTo(copy_ori_image_0); + cv::Mat copy_ori_image_1; + + copy_ori_image_1 = osd_frame_tmp(cv::Rect(puzzle_width+2,(puzzle_width-puzzle_ori_height)/2,puzzle_ori_width,puzzle_ori_height)); + image_puzzle_ori.copyTo(copy_ori_image_1); + + cv::Mat blank_block(every_block_height, every_block_width, CV_8UC4, cv::Scalar(220, 114, 114, 114)); + + + srand((unsigned)time(NULL)); + for(int i = 0; i < level*10; i++) + { + int k230_random = rand() % 4; + int blank_x_tmp = blank_x; + int blank_y_tmp = blank_y; + if (k230_random < 2) + { + blank_x_tmp = blank_x + direction_vec[k230_random]; + } + else + { + blank_y_tmp = blank_y + direction_vec[k230_random]; + } + + if((blank_x_tmp >= 0 && blank_x_tmp < level) && (blank_y_tmp >= 0 && blank_y_tmp < level) && (std::abs(blank_x - blank_x_tmp) <= 1 && std::abs(blank_y - blank_y_tmp) <= 1)) + { + move_rect = cv::Rect(blank_x_tmp*every_block_width,blank_y_tmp*every_block_height,every_block_width,every_block_height); + move_mat = osd_frame_tmp(move_rect); + + copy_blank = osd_frame_tmp(cv::Rect(blank_x_tmp*every_block_width,blank_y_tmp*every_block_height,every_block_width,every_block_height)); + copy_move = osd_frame_tmp(cv::Rect(blank_x*every_block_width,blank_y*every_block_height,every_block_width,every_block_height)); + move_mat.copyTo(copy_move); + blank_block.copyTo(copy_blank); + + blank_x = blank_x_tmp; + blank_y = blank_y_tmp; + } + } + + HandDetection hd(argv[1], atof(argv[2]), atof(argv[3]), {SENSOR_WIDTH, SENSOR_HEIGHT}, {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[7])); + sync(); + HandKeypoint hk(argv[4], {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[7])); + sync(); + + std::vector results; + std::vector two_point; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[7])); + // 从vivcap中读取一帧图像到dump_info + memset(&dump_info, 0, sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + { + ScopedTiming st("isp copy", atoi(argv[7])); + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + two_point.clear(); + + hd.pre_process(); + hd.inference(); + hd.post_process(results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + float max_area_hand = 0; + int max_id_hand = -1; + for (int i = 0; i < results.size(); ++i) + { + float area_i = (results[i].x2 - results[i].x1) * (results[i].y2 - results[i].y1); + if (area_i > max_area_hand) + { + max_area_hand = area_i; + max_id_hand = i; + } + } + + if (max_id_hand != -1) + { + std::string text = hd.labels_[results[max_id_hand].label] + ":" + std::to_string(round(results[max_id_hand].score * 100) / 100.0); + + int w = results[max_id_hand].x2 - results[max_id_hand].x1 + 1; + int h = results[max_id_hand].y2 - results[max_id_hand].y1 + 1; + + int length = std::max(w,h)/2; + int cx = (results[max_id_hand].x1+results[max_id_hand].x2)/2; + int cy = (results[max_id_hand].y1+results[max_id_hand].y2)/2; + int ratio_num = 1.26*length; + + int x1_1 = std::max(0,cx-ratio_num); + int y1_1 = std::max(0,cy-ratio_num); + int x2_1 = std::min(SENSOR_WIDTH-1, cx+ratio_num); + int y2_1 = std::min(SENSOR_HEIGHT-1, cy+ratio_num); + int w_1 = x2_1 - x1_1 + 1; + int h_1 = y2_1 - y1_1 + 1; + + struct Bbox bbox = {x:x1_1,y:y1_1,w:w_1,h:h_1}; + hk.pre_process(bbox); + + hk.inference(); + + { + ScopedTiming st("osd draw", atoi(argv[7])); + hk.draw_keypoints(osd_frame, text, bbox, false, two_point); + } + } + + if(max_id_hand != -1 && two_point[1] <= SENSOR_WIDTH) + { + distance_tow_points = std::sqrt(std::pow((two_point[0] - two_point[2]),2) + std::pow((two_point[1] - two_point[3]),2))* 1.0 / SENSOR_WIDTH * osd_frame.cols; + exact_division_x = (two_point[0] * 1.0 / SENSOR_WIDTH * osd_frame.cols)/every_block_width; + exact_division_y = (two_point[1] * 1.0 / SENSOR_HEIGHT * osd_frame.rows)/every_block_height; + if(distance_tow_points < distance_thred && exact_division_x >= 0 && exact_division_x < level && exact_division_y >= 0 && exact_division_y < level) + { + if(std::abs(blank_x - exact_division_x) == 1 && std::abs(blank_y - exact_division_y) == 0) + { + move_rect = cv::Rect(exact_division_x*every_block_width,exact_division_y*every_block_height,every_block_width,every_block_height); + move_mat = osd_frame_tmp(move_rect); + + copy_blank = osd_frame_tmp(cv::Rect(exact_division_x*every_block_width,exact_division_y*every_block_height,every_block_width,every_block_height)); + copy_move = osd_frame_tmp(cv::Rect(blank_x*every_block_width,blank_y*every_block_height,every_block_width,every_block_height)); + move_mat.copyTo(copy_move); + blank_block.copyTo(copy_blank); + + blank_x = exact_division_x; + } + else if (std::abs(blank_y - exact_division_y) == 1 && std::abs(blank_x - exact_division_x) == 0) + { + move_rect = cv::Rect(exact_division_x*every_block_width,exact_division_y*every_block_height,every_block_width,every_block_height); + move_mat = osd_frame_tmp(move_rect); + + copy_blank = osd_frame_tmp(cv::Rect(exact_division_x*every_block_width,exact_division_y*every_block_height,every_block_width,every_block_height)); + copy_move = osd_frame_tmp(cv::Rect(blank_x*every_block_width,blank_y*every_block_height,every_block_width,every_block_height)); + move_mat.copyTo(copy_move); + blank_block.copyTo(copy_blank); + + blank_y = exact_division_y; + } + + osd_frame = osd_frame_tmp.clone(); + if(two_point.size() > 0) + { + int x1 = two_point[0] * 1.0 / SENSOR_WIDTH * osd_frame.cols; + int y1 = two_point[1] * 1.0 / SENSOR_HEIGHT * osd_frame.rows; + cv::circle(osd_frame, cv::Point(x1, y1), 10, cv::Scalar(255, 0, 255, 255), 10); + } + } + else + { + osd_frame = osd_frame_tmp.clone(); + if(two_point.size() > 0) + { + int x1 = two_point[0] * 1.0 / SENSOR_WIDTH * osd_frame.cols; + int y1 = two_point[1] * 1.0 / SENSOR_HEIGHT * osd_frame.rows; + cv::circle(osd_frame, cv::Point(x1, y1), 10, cv::Scalar(255, 255, 255, 0), 10); + } + } + sync(); + } + else + { + osd_frame = osd_frame_tmp.clone(); + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[7])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + // 显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id + 3, &vf_info); // K_VO_OSD0 + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } +} + +void video_proc_01(char *argv[]) +{ + vivcap_start(); + // 设置osd参数 + k_video_frame_info vf_info; + void *pic_vaddr = NULL; // osd + memset(&vf_info, 0, sizeof(vf_info)); + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory,get isp memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + int puzzle_width; + int puzzle_height; + int puzzle_ori_width; + int puzzle_ori_height; + puzzle_width = osd_width; + puzzle_height = osd_width; + puzzle_ori_width = osd_height-puzzle_height-5; + puzzle_ori_height = osd_height-puzzle_height-5; + + + int level = atoi(argv[6]); + int every_block_width = puzzle_width/level; + int every_block_height = puzzle_height/level; + float ratio_num = every_block_width/360.0; + int blank_x = 0; + int blank_y = 0; + std::vector direction_vec = {-1,1,-1,1}; + + cv::Mat image_puzzle_argb; + cv::Mat image_puzzle_ori; + cv::Mat osd_frame_tmp(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame_tmp, osd_frame_tmp, cv::ROTATE_90_COUNTERCLOCKWISE); + + int exact_division_x = 0; + int exact_division_y = 0; + int distance_tow_points = osd_width; + int distance_thred = every_block_width*0.3; + cv::Rect move_rect; + cv::Mat move_mat; + cv::Mat copy_blank; + cv::Mat copy_move; + + // if (strcmp(argv[5], "None") == 0) + // { + image_puzzle_argb = cv::Mat(puzzle_height, puzzle_width, CV_8UC4, cv::Scalar(200, 130, 150, 100)); + for(int i = 0; i < level*level; i++) + { + cv::rectangle(image_puzzle_argb, cv::Rect((i%level)*every_block_width, (i/level)*every_block_height, every_block_width, every_block_height), cv::Scalar(255, 0, 0, 0), 5); + std::string classString = to_string(i); + cv::Size textSize = cv::getTextSize(classString, cv::FONT_HERSHEY_DUPLEX, 7*ratio_num, 8*ratio_num, 0); + cv::putText(image_puzzle_argb, classString, cv::Point((i%level)*every_block_width + (every_block_width-textSize.width)/2,(i/level)*every_block_height + (every_block_height+textSize.height)/2),cv::FONT_HERSHEY_COMPLEX, 7*ratio_num, cv::Scalar(255, 0, 0, 255), 8*ratio_num, 0); + } + // } + // else + // { + // // Utils::bin_2_mat(argv[5], puzzle_width, puzzle_height, image_puzzle_argb); + // // for(int i = 0; i < level*level; i++) + // // { + // // cv::rectangle(image_puzzle_argb, cv::Rect((i%level)*every_block_width, (i/level)*every_block_height, every_block_width, every_block_height), cv::Scalar(255, 0, 0, 0), 5); + // // } + // std::cout << "Non-empty is not supported !!!" << std::endl; + // return ; + // } + + cv::Mat blank_block_puzzle(every_block_height, every_block_width, CV_8UC4, cv::Scalar(220, 114, 114, 114)); + cv::Mat image_puzzle_argb_blank = image_puzzle_argb(cv::Rect(0,0,every_block_width,every_block_height)); + blank_block_puzzle.copyTo(image_puzzle_argb_blank); + + cv::resize(image_puzzle_argb, image_puzzle_ori, cv::Size(puzzle_ori_width, puzzle_ori_height), cv::INTER_AREA); + cv::Mat copy_ori_image_0 = osd_frame_tmp(cv::Rect(0,0,puzzle_width,puzzle_height)); + image_puzzle_argb.copyTo(copy_ori_image_0); + cv::Mat copy_ori_image_1; + + copy_ori_image_1 = osd_frame_tmp(cv::Rect(puzzle_width+2,(puzzle_width-puzzle_ori_height)/2,puzzle_ori_width,puzzle_ori_height)); + image_puzzle_ori.copyTo(copy_ori_image_1); + + cv::Mat blank_block(every_block_height, every_block_width, CV_8UC4, cv::Scalar(220, 114, 114, 114)); + + + srand((unsigned)time(NULL)); + for(int i = 0; i < level*10; i++) + { + int k230_random = rand() % 4; + int blank_x_tmp = blank_x; + int blank_y_tmp = blank_y; + if (k230_random < 2) + { + blank_x_tmp = blank_x + direction_vec[k230_random]; + } + else + { + blank_y_tmp = blank_y + direction_vec[k230_random]; + } + + if((blank_x_tmp >= 0 && blank_x_tmp < level) && (blank_y_tmp >= 0 && blank_y_tmp < level) && (std::abs(blank_x - blank_x_tmp) <= 1 && std::abs(blank_y - blank_y_tmp) <= 1)) + { + move_rect = cv::Rect(blank_x_tmp*every_block_width,blank_y_tmp*every_block_height,every_block_width,every_block_height); + move_mat = osd_frame_tmp(move_rect); + + copy_blank = osd_frame_tmp(cv::Rect(blank_x_tmp*every_block_width,blank_y_tmp*every_block_height,every_block_width,every_block_height)); + copy_move = osd_frame_tmp(cv::Rect(blank_x*every_block_width,blank_y*every_block_height,every_block_width,every_block_height)); + move_mat.copyTo(copy_move); + blank_block.copyTo(copy_blank); + + blank_x = blank_x_tmp; + blank_y = blank_y_tmp; + } + } + + HandDetection hd(argv[1], atof(argv[2]), atof(argv[3]), {SENSOR_WIDTH, SENSOR_HEIGHT}, {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[7])); + sync(); + HandKeypoint hk(argv[4], {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[7])); + sync(); + + std::vector results; + std::vector two_point; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[7])); + // 从vivcap中读取一帧图像到dump_info + memset(&dump_info, 0, sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + { + ScopedTiming st("isp copy", atoi(argv[7])); + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + two_point.clear(); + + hd.pre_process(); + hd.inference(); + hd.post_process(results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + float max_area_hand = 0; + int max_id_hand = -1; + for (int i = 0; i < results.size(); ++i) + { + float area_i = (results[i].x2 - results[i].x1) * (results[i].y2 - results[i].y1); + if (area_i > max_area_hand) + { + max_area_hand = area_i; + max_id_hand = i; + } + } + + if (max_id_hand != -1) + { + std::string text = hd.labels_[results[max_id_hand].label] + ":" + std::to_string(round(results[max_id_hand].score * 100) / 100.0); + + int w = results[max_id_hand].x2 - results[max_id_hand].x1 + 1; + int h = results[max_id_hand].y2 - results[max_id_hand].y1 + 1; + + int length = std::max(w,h)/2; + int cx = (results[max_id_hand].x1+results[max_id_hand].x2)/2; + int cy = (results[max_id_hand].y1+results[max_id_hand].y2)/2; + int ratio_num = 1.26*length; + + int x1_1 = std::max(0,cx-ratio_num); + int y1_1 = std::max(0,cy-ratio_num); + int x2_1 = std::min(SENSOR_WIDTH-1, cx+ratio_num); + int y2_1 = std::min(SENSOR_HEIGHT-1, cy+ratio_num); + int w_1 = x2_1 - x1_1 + 1; + int h_1 = y2_1 - y1_1 + 1; + + struct Bbox bbox = {x:x1_1,y:y1_1,w:w_1,h:h_1}; + hk.pre_process(bbox); + + hk.inference(); + + { + ScopedTiming st("osd draw", atoi(argv[7])); + hk.draw_keypoints(osd_frame, text, bbox, false, two_point); + } + } + + if(max_id_hand != -1 && two_point[1] <= SENSOR_WIDTH) + { + distance_tow_points = std::sqrt(std::pow((two_point[0] - two_point[2]),2) + std::pow((two_point[1] - two_point[3]),2))* 1.0 / SENSOR_WIDTH * osd_frame.cols; + exact_division_x = (two_point[0] * 1.0 / SENSOR_WIDTH * osd_frame.cols)/every_block_width; + exact_division_y = (two_point[1] * 1.0 / SENSOR_HEIGHT * osd_frame.rows)/every_block_height; + if(distance_tow_points < distance_thred && exact_division_x >= 0 && exact_division_x < level && exact_division_y >= 0 && exact_division_y < level) + { + if(std::abs(blank_x - exact_division_x) == 1 && std::abs(blank_y - exact_division_y) == 0) + { + move_rect = cv::Rect(exact_division_x*every_block_width,exact_division_y*every_block_height,every_block_width,every_block_height); + move_mat = osd_frame_tmp(move_rect); + + copy_blank = osd_frame_tmp(cv::Rect(exact_division_x*every_block_width,exact_division_y*every_block_height,every_block_width,every_block_height)); + copy_move = osd_frame_tmp(cv::Rect(blank_x*every_block_width,blank_y*every_block_height,every_block_width,every_block_height)); + move_mat.copyTo(copy_move); + blank_block.copyTo(copy_blank); + + blank_x = exact_division_x; + } + else if (std::abs(blank_y - exact_division_y) == 1 && std::abs(blank_x - exact_division_x) == 0) + { + move_rect = cv::Rect(exact_division_x*every_block_width,exact_division_y*every_block_height,every_block_width,every_block_height); + move_mat = osd_frame_tmp(move_rect); + + copy_blank = osd_frame_tmp(cv::Rect(exact_division_x*every_block_width,exact_division_y*every_block_height,every_block_width,every_block_height)); + copy_move = osd_frame_tmp(cv::Rect(blank_x*every_block_width,blank_y*every_block_height,every_block_width,every_block_height)); + move_mat.copyTo(copy_move); + blank_block.copyTo(copy_blank); + + blank_y = exact_division_y; + } + + osd_frame = osd_frame_tmp.clone(); + if(two_point.size() > 0) + { + int x1 = two_point[0] * 1.0 / SENSOR_WIDTH * osd_frame.cols; + int y1 = two_point[1] * 1.0 / SENSOR_HEIGHT * osd_frame.rows; + cv::circle(osd_frame, cv::Point(x1, y1), 10, cv::Scalar(255, 0, 255, 255), 10); + } + } + else + { + osd_frame = osd_frame_tmp.clone(); + if(two_point.size() > 0) + { + int x1 = two_point[0] * 1.0 / SENSOR_WIDTH * osd_frame.cols; + int y1 = two_point[1] * 1.0 / SENSOR_HEIGHT * osd_frame.rows; + cv::circle(osd_frame, cv::Point(x1, y1), 10, cv::Scalar(255, 255, 255, 0), 10); + } + } + sync(); + } + else + { + osd_frame = osd_frame_tmp.clone(); + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[7])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + // 显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id + 3, &vf_info); // K_VO_OSD0 + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } +} + int main(int argc, char *argv[]) { @@ -356,13 +1232,61 @@ int main(int argc, char *argv[]) return -1; } - std::thread thread_isp(video_proc, argv); - while (getchar() != 'q') + #if defined(CONFIG_BOARD_K230_CANMV) + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_V2) + { + std::thread thread_isp(video_proc_v2, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230D_CANMV) + { + std::thread thread_isp(video_proc_k230d, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) { - usleep(10000); + std::thread thread_isp(video_proc_01, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); } + #else + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } - isp_stop = true; - thread_isp.join(); + isp_stop = true; + thread_isp.join(); + } + #endif return 0; } \ No newline at end of file diff --git a/src/reference/ai_poc/puzzle_game/vi_vo.h b/src/reference/ai_poc/puzzle_game/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/puzzle_game/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/segment_yolov8n/main.cc b/src/reference/ai_poc/segment_yolov8n/main.cc index a24a2589a..bb72ea8a5 100644 --- a/src/reference/ai_poc/segment_yolov8n/main.cc +++ b/src/reference/ai_poc/segment_yolov8n/main.cc @@ -50,7 +50,7 @@ void print_usage(const char *name) << endl; } -void video_proc(char *argv[]) +void video_proc_v1(char *argv[]) { vivcap_start(); @@ -148,6 +148,302 @@ void video_proc(char *argv[]) } +void video_proc_v2(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + Seg seg(argv[1], atof(argv[2]), atof(argv[3]), atof(argv[4]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[6])); + + std::vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[6])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[6])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + seg.pre_process(); + seg.inference(); + + seg.post_process({osd_width, osd_height}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::Mat osd_frame_tmp; + + { + ScopedTiming st("osd draw", atoi(argv[6])); + // cv::putText(osd_frame, "This !!!", {50, 600}, 4, 4, cv::Scalar(255, 255, 255, 255), 4, 8, 0); + // cv::rectangle(osd_frame, cv::Rect(osd_width-(200 + 200), osd_height-(700 + 700) , 200, 700), cv::Scalar(255,255, 255, 255), 2, 2, 0); + Utils::draw_segmentation(osd_frame, results, {osd_width, osd_height}); + } + + { + ScopedTiming st("osd copy", atoi(argv[6])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_k230d(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + Seg seg(argv[1], atof(argv[2]), atof(argv[3]), atof(argv[4]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[6])); + + std::vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[6])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[6])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + seg.pre_process(); + seg.inference(); + + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + seg.post_process({osd_frame.cols, osd_frame.rows}, results); + + + + { + ScopedTiming st("osd draw", atoi(argv[6])); + Utils::draw_segmentation(osd_frame, results, {osd_frame.cols, osd_frame.rows}); + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[6])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_01(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + Seg seg(argv[1], atof(argv[2]), atof(argv[3]), atof(argv[4]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[6])); + + std::vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[6])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[6])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + seg.pre_process(); + seg.inference(); + + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + seg.post_process({osd_frame.cols, osd_frame.rows}, results); + + + + { + ScopedTiming st("osd draw", atoi(argv[6])); + Utils::draw_segmentation(osd_frame, results, {osd_frame.cols, osd_frame.rows}); + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[6])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + int main(int argc, char *argv[]) { @@ -160,14 +456,62 @@ int main(int argc, char *argv[]) if (strcmp(argv[5], "None") == 0) { - std::thread thread_isp(video_proc, argv); - while (getchar() != 'q') + #if defined(CONFIG_BOARD_K230_CANMV) + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_V2) + { + std::thread thread_isp(video_proc_v2, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230D_CANMV) { - usleep(10000); + std::thread thread_isp(video_proc_k230d, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + std::thread thread_isp(video_proc_01, argv); + while (getchar() != 'q') + { + usleep(10000); + } - isp_stop = true; - thread_isp.join(); + isp_stop = true; + thread_isp.join(); + } + #else + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #endif } else { diff --git a/src/reference/ai_poc/segment_yolov8n/vi_vo.h b/src/reference/ai_poc/segment_yolov8n/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/segment_yolov8n/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/self_learning/main.cc b/src/reference/ai_poc/self_learning/main.cc index 1443916d6..97d8e11d9 100755 --- a/src/reference/ai_poc/self_learning/main.cc +++ b/src/reference/ai_poc/self_learning/main.cc @@ -139,7 +139,7 @@ void set_read_block_mode(bool blocked) } } -void video_proc(char *argv[]) +void video_proc_v1(char *argv[]) { vivcap_start(); @@ -169,18 +169,597 @@ void video_proc(char *argv[]) crop_wh.width = atoi(argv[2]); crop_wh.height = atoi(argv[3]); + crop_wh.width = std::min(int(crop_wh.width),SENSOR_WIDTH - 5); + crop_wh.width = std::max(int(crop_wh.width),(SENSOR_WIDTH - 5)/2); + crop_wh.height = std::min(int(crop_wh.height),SENSOR_HEIGHT - 5); + crop_wh.height = std::max(int(crop_wh.height),(SENSOR_HEIGHT - 5)/2); + + Bbox crop_box_osd; + crop_box_osd.x = osd_width / 2.0 - float(crop_wh.width) / SENSOR_WIDTH * osd_width / 2.0; + crop_box_osd.y = osd_height / 2.0 - float(crop_wh.height) / SENSOR_HEIGHT * osd_height / 2.0; + crop_box_osd.w = float(crop_wh.width) / SENSOR_WIDTH * osd_width; + crop_box_osd.h = float(crop_wh.height) / SENSOR_HEIGHT * osd_height; + + + if (!isFolderExist("features")) + { + createFolder("features"); + } + + //only for face reg + int flags = fcntl(STDIN_FILENO, F_GETFL, 0); + if (flags == -1) + { + cerr << "Failed to get flags for stdin." << endl; + } + set_terminal_mode(false); + set_read_block_mode(false); + + float thres = atof(argv[4]); + SelfLearning self_learning(argv[1], crop_wh, thres, atoi(argv[5]),{SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[6])); + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[6])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[6])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rectangle(osd_frame, cv::Rect(crop_box_osd.x, crop_box_osd.y , crop_box_osd.w, crop_box_osd.h), cv::Scalar(255, 255, 255), 2, 2, 0); + + self_learning.pre_process(); + self_learning.inference(); + + char ch; + if (read(STDIN_FILENO, &ch, 1) > 0) + { + if (ch == 'i') //for i key + { + set_terminal_mode(true); + set_read_block_mode(true); + + std::cout << "<<< input: n -> create new category feature, d -> delete one category feature >>>" << std::endl; + std::string input_; + getline(std::cin, input_); + + std::vector features; + getFileNames("features", features); + std::string features_out = "Already have : "; + for (int i = 0; i < features.size(); i++) + { + features_out += " | " + std::to_string(i) + "->" + features[i]; + } + std::cout << features_out << std::endl; + + if (input_ == "n") + { + std::cout << "Please enter one filename. format : {category}_{index}.bin eg: apple_0.bin" << std::endl; + std::string input_feature; + getline(std::cin, input_feature); + int len_; + float *output = self_learning.get_kpu_output(&len_); + dump_binary_file(("features/" + input_feature).c_str(), (char *)output, (const size_t) len_ * sizeof(float)); + std::cout << "Successfully created " + input_feature + " feature." << std::endl; + } + else if (input_ == "d") + { + std::cout << "Please enter one feature index." << std::endl; + std::string str_index; + getline(std::cin, str_index); + int index = str_index[0] - 48; + if (index < 0 || index >= features.size()) + { + std::cout << "Fail to delete." << std::endl; + } + else + { + remove(("features/" + features[index]).c_str()); + std::cout << "Successfully deleted " + features[index] + "." << std::endl; + } + } + + set_read_block_mode(false); + set_terminal_mode(false); + } + else if(ch == 27) //for ESC key + { + reg_stop = true; + } + } + else + { + std::vector results; + std::vector features; + getFileNames("features", features); + self_learning.post_process(features, results); + cv::Point origin; + origin.x = 200; + origin.y = 100; + for (int i = 0; i < results.size(); i++) + { + + origin.y += 50; + std::string text = results[i].category + " " + std::to_string(results[i].score); + cv::putText(osd_frame, text, origin, cv::FONT_HERSHEY_COMPLEX, 2, cv::Scalar(255,255, 0, 0), 4, 8, 0); + } + } + + { + ScopedTiming st("osd copy", atoi(argv[6])); + + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_v2(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + FrameSize crop_wh; + crop_wh.width = atoi(argv[2]); + crop_wh.height = atoi(argv[3]); + + crop_wh.width = std::min(int(crop_wh.width),SENSOR_WIDTH - 5); + crop_wh.width = std::max(int(crop_wh.width),(SENSOR_WIDTH - 5)/2); + crop_wh.height = std::min(int(crop_wh.height),SENSOR_HEIGHT - 5); + crop_wh.height = std::max(int(crop_wh.height),(SENSOR_HEIGHT - 5)/2); + + Bbox crop_box_osd; + crop_box_osd.x = osd_width / 2.0 - float(crop_wh.width) / SENSOR_WIDTH * osd_width / 2.0; + crop_box_osd.y = osd_height / 2.0 - float(crop_wh.height) / SENSOR_HEIGHT * osd_height / 2.0; + crop_box_osd.w = float(crop_wh.width) / SENSOR_WIDTH * osd_width; + crop_box_osd.h = float(crop_wh.height) / SENSOR_HEIGHT * osd_height; + + + + if (!isFolderExist("features")) + { + createFolder("features"); + } + + //only for face reg + int flags = fcntl(STDIN_FILENO, F_GETFL, 0); + if (flags == -1) + { + cerr << "Failed to get flags for stdin." << endl; + } + set_terminal_mode(false); + set_read_block_mode(false); + + float thres = atof(argv[4]); + SelfLearning self_learning(argv[1], crop_wh, thres, atoi(argv[5]),{SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[6])); + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[6])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[6])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rectangle(osd_frame, cv::Rect(crop_box_osd.x, crop_box_osd.y , crop_box_osd.w, crop_box_osd.h), cv::Scalar(255, 255, 255), 2, 2, 0); + + self_learning.pre_process(); + self_learning.inference(); + + char ch; + if (read(STDIN_FILENO, &ch, 1) > 0) + { + if (ch == 'i') //for i key + { + set_terminal_mode(true); + set_read_block_mode(true); + + std::cout << "<<< input: n -> create new category feature, d -> delete one category feature >>>" << std::endl; + std::string input_; + getline(std::cin, input_); + + std::vector features; + getFileNames("features", features); + std::string features_out = "Already have : "; + for (int i = 0; i < features.size(); i++) + { + features_out += " | " + std::to_string(i) + "->" + features[i]; + } + std::cout << features_out << std::endl; + + if (input_ == "n") + { + std::cout << "Please enter one filename. format : {category}_{index}.bin eg: apple_0.bin" << std::endl; + std::string input_feature; + getline(std::cin, input_feature); + int len_; + float *output = self_learning.get_kpu_output(&len_); + dump_binary_file(("features/" + input_feature).c_str(), (char *)output, (const size_t) len_ * sizeof(float)); + std::cout << "Successfully created " + input_feature + " feature." << std::endl; + } + else if (input_ == "d") + { + std::cout << "Please enter one feature index." << std::endl; + std::string str_index; + getline(std::cin, str_index); + int index = str_index[0] - 48; + if (index < 0 || index >= features.size()) + { + std::cout << "Fail to delete." << std::endl; + } + else + { + remove(("features/" + features[index]).c_str()); + std::cout << "Successfully deleted " + features[index] + "." << std::endl; + } + } + + set_read_block_mode(false); + set_terminal_mode(false); + } + else if(ch == 27) //for ESC key + { + reg_stop = true; + } + } + else + { + std::vector results; + std::vector features; + getFileNames("features", features); + self_learning.post_process(features, results); + cv::Point origin; + origin.x = 200; + origin.y = 100; + for (int i = 0; i < results.size(); i++) + { + + origin.y += 50; + std::string text = results[i].category + " " + std::to_string(results[i].score); + cv::putText(osd_frame, text, origin, cv::FONT_HERSHEY_COMPLEX, 2, cv::Scalar(255,255, 0, 0), 4, 8, 0); + } + } + + { + ScopedTiming st("osd copy", atoi(argv[6])); + + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_k230d(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + FrameSize crop_wh; + crop_wh.width = atoi(argv[2]); + crop_wh.height = atoi(argv[3]); + + crop_wh.width = std::min(int(crop_wh.width),SENSOR_WIDTH - 5); + crop_wh.width = std::max(int(crop_wh.width),(SENSOR_WIDTH - 5)/2); + crop_wh.height = std::min(int(crop_wh.height),SENSOR_HEIGHT - 5); + crop_wh.height = std::max(int(crop_wh.height),(SENSOR_HEIGHT - 5)/2); + Bbox crop_box_osd; - crop_box_osd.x = osd_width / 2.0 - float(crop_wh.width) / SENSOR_WIDTH * osd_width / 2.0; - crop_box_osd.y = osd_height / 2.0 - float(crop_wh.height) / SENSOR_HEIGHT * osd_height / 2.0; - crop_box_osd.w = float(crop_wh.width) / SENSOR_WIDTH * osd_width; - crop_box_osd.h = float(crop_wh.height) / SENSOR_HEIGHT * osd_height; + crop_box_osd.x = osd_height / 2.0 - float(crop_wh.width) / SENSOR_WIDTH * osd_height / 2.0; + crop_box_osd.y = osd_width / 2.0 - float(crop_wh.height) / SENSOR_HEIGHT * osd_width / 2.0; + crop_box_osd.w = float(crop_wh.width) / SENSOR_WIDTH * osd_height; + crop_box_osd.h = float(crop_wh.height) / SENSOR_HEIGHT * osd_width; + + + if (!isFolderExist("features")) + { + createFolder("features"); + } + + //only for face reg + int flags = fcntl(STDIN_FILENO, F_GETFL, 0); + if (flags == -1) + { + cerr << "Failed to get flags for stdin." << endl; + } + set_terminal_mode(false); + set_read_block_mode(false); + + float thres = atof(argv[4]); + SelfLearning self_learning(argv[1], crop_wh, thres, atoi(argv[5]),{SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[6])); + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[6])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[6])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + cv::rectangle(osd_frame, cv::Rect(crop_box_osd.x, crop_box_osd.y , crop_box_osd.w, crop_box_osd.h), cv::Scalar(255, 255, 255), 2, 2, 0); + + self_learning.pre_process(); + self_learning.inference(); + + char ch; + if (read(STDIN_FILENO, &ch, 1) > 0) + { + if (ch == 'i') //for i key + { + set_terminal_mode(true); + set_read_block_mode(true); + + std::cout << "<<< input: n -> create new category feature, d -> delete one category feature >>>" << std::endl; + std::string input_; + getline(std::cin, input_); + + std::vector features; + getFileNames("features", features); + std::string features_out = "Already have : "; + for (int i = 0; i < features.size(); i++) + { + features_out += " | " + std::to_string(i) + "->" + features[i]; + } + std::cout << features_out << std::endl; + + if (input_ == "n") + { + std::cout << "Please enter one filename. format : {category}_{index}.bin eg: apple_0.bin" << std::endl; + std::string input_feature; + getline(std::cin, input_feature); + int len_; + float *output = self_learning.get_kpu_output(&len_); + dump_binary_file(("features/" + input_feature).c_str(), (char *)output, (const size_t) len_ * sizeof(float)); + std::cout << "Successfully created " + input_feature + " feature." << std::endl; + } + else if (input_ == "d") + { + std::cout << "Please enter one feature index." << std::endl; + std::string str_index; + getline(std::cin, str_index); + int index = str_index[0] - 48; + if (index < 0 || index >= features.size()) + { + std::cout << "Fail to delete." << std::endl; + } + else + { + remove(("features/" + features[index]).c_str()); + std::cout << "Successfully deleted " + features[index] + "." << std::endl; + } + } + + set_read_block_mode(false); + set_terminal_mode(false); + } + else if(ch == 27) //for ESC key + { + reg_stop = true; + } + } + else + { + std::vector results; + std::vector features; + getFileNames("features", features); + self_learning.post_process(features, results); + cv::Point origin; + origin.x = 200; + origin.y = 100; + for (int i = 0; i < results.size(); i++) + { + + origin.y += 50; + std::string text = results[i].category + " " + std::to_string(results[i].score); + cv::putText(osd_frame, text, origin, cv::FONT_HERSHEY_COMPLEX, 2, cv::Scalar(255,255, 0, 0), 4, 8, 0); + } + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[6])); + + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + + +void video_proc_01(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd - if (crop_wh.width < 0 || crop_wh.height < 0 || crop_wh.width > SENSOR_WIDTH - 5 || crop_wh.height > SENSOR_HEIGHT - 5) + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) { - std::cout << "**剪切范围超出图像范围**" << std::endl; - isp_stop = true; + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); } + FrameSize crop_wh; + crop_wh.width = atoi(argv[2]); + crop_wh.height = atoi(argv[3]); + + crop_wh.width = std::min(int(crop_wh.width),SENSOR_WIDTH - 5); + crop_wh.width = std::max(int(crop_wh.width),(SENSOR_WIDTH - 5)/2); + crop_wh.height = std::min(int(crop_wh.height),SENSOR_HEIGHT - 5); + crop_wh.height = std::max(int(crop_wh.height),(SENSOR_HEIGHT - 5)/2); + + Bbox crop_box_osd; + crop_box_osd.x = osd_height / 2.0 - float(crop_wh.width) / SENSOR_WIDTH * osd_height / 2.0; + crop_box_osd.y = osd_width / 2.0 - float(crop_wh.height) / SENSOR_HEIGHT * osd_width / 2.0; + crop_box_osd.w = float(crop_wh.width) / SENSOR_WIDTH * osd_height; + crop_box_osd.h = float(crop_wh.height) / SENSOR_HEIGHT * osd_width; + if (!isFolderExist("features")) { @@ -224,6 +803,7 @@ void video_proc(char *argv[]) } cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); cv::rectangle(osd_frame, cv::Rect(crop_box_osd.x, crop_box_osd.y , crop_box_osd.w, crop_box_osd.h), cv::Scalar(255, 255, 255), 2, 2, 0); self_learning.pre_process(); @@ -302,6 +882,7 @@ void video_proc(char *argv[]) cv::putText(osd_frame, text, origin, cv::FONT_HERSHEY_COMPLEX, 2, cv::Scalar(255,255, 0, 0), 4, 8, 0); } } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); { ScopedTiming st("osd copy", atoi(argv[6])); @@ -333,6 +914,7 @@ void video_proc(char *argv[]) } + int main(int argc, char *argv[]) { std::cout << "case " << argv[0] << " built at " << __DATE__ << " " << __TIME__ << std::endl; @@ -346,16 +928,72 @@ int main(int argc, char *argv[]) } { - std::thread thread_isp(video_proc, argv); - while(!reg_stop) + #if defined(CONFIG_BOARD_K230_CANMV) { - usleep(10000); + std::thread thread_isp(video_proc_v1, argv); + while(!reg_stop) + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + set_read_block_mode(true); + set_terminal_mode(true); } - - isp_stop = true; - thread_isp.join(); - set_read_block_mode(true); - set_terminal_mode(true); + #elif defined(CONFIG_BOARD_K230_CANMV_V2) + { + std::thread thread_isp(video_proc_v2, argv); + while(!reg_stop) + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + set_read_block_mode(true); + set_terminal_mode(true); + } + #elif defined(CONFIG_BOARD_K230D_CANMV) + { + std::thread thread_isp(video_proc_k230d, argv); + while(!reg_stop) + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + set_read_block_mode(true); + set_terminal_mode(true); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + std::thread thread_isp(video_proc_01, argv); + while(!reg_stop) + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + set_read_block_mode(true); + set_terminal_mode(true); + } + #else + { + std::thread thread_isp(video_proc_v1, argv); + while(!reg_stop) + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + set_read_block_mode(true); + set_terminal_mode(true); + } + #endif } return 0; diff --git a/src/reference/ai_poc/self_learning/vi_vo.h b/src/reference/ai_poc/self_learning/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/self_learning/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/smoke_detect/main.cc b/src/reference/ai_poc/smoke_detect/main.cc index e4b640a0c..77720941f 100644 --- a/src/reference/ai_poc/smoke_detect/main.cc +++ b/src/reference/ai_poc/smoke_detect/main.cc @@ -52,7 +52,7 @@ void print_usage(const char *name) << endl; } -void video_proc(char *argv[]) +void video_proc_v1(char *argv[]) { vivcap_start(); @@ -160,6 +160,334 @@ void video_proc(char *argv[]) } +void video_proc_v2(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + smokeDetect sd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + sd.pre_process(); + sd.inference(); + sd.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + + std::string text; + cv::Point origin; + + for (auto r : results) + { + ScopedTiming st("draw boxes", atoi(argv[5])); + text = sd.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); + + int x1 = r.x1 / SENSOR_WIDTH * osd_width; + int y1 = r.y1 / SENSOR_HEIGHT * osd_height; + + int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_width; + int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_height; + + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), cv::Scalar(255, 255,0, 0), 6, 2, 0); // ARGB + + } + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_k230d(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + smokeDetect sd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + sd.pre_process(); + sd.inference(); + sd.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + std::string text; + cv::Point origin; + + for (auto r : results) + { + ScopedTiming st("draw boxes", atoi(argv[5])); + text = sd.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); + + int x1 = r.x1 / SENSOR_WIDTH * osd_frame.cols; + int y1 = r.y1 / SENSOR_HEIGHT * osd_frame.rows; + + int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_frame.cols; + int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_frame.rows; + + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), cv::Scalar(255, 255,0, 0), 6, 2, 0); // ARGB + + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_01(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + smokeDetect sd(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + sd.pre_process(); + sd.inference(); + sd.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + std::string text; + cv::Point origin; + + for (auto r : results) + { + ScopedTiming st("draw boxes", atoi(argv[5])); + text = sd.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); + + int x1 = r.x1 / SENSOR_WIDTH * osd_frame.cols; + int y1 = r.y1 / SENSOR_HEIGHT * osd_frame.rows; + + int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_frame.cols; + int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_frame.rows; + + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), cv::Scalar(255, 255,0, 0), 6, 2, 0); // ARGB + + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + int main(int argc, char *argv[]) { @@ -172,14 +500,62 @@ int main(int argc, char *argv[]) if (strcmp(argv[4], "None") == 0) { - std::thread thread_isp(video_proc, argv); - while (getchar() != 'q') + #if defined(CONFIG_BOARD_K230_CANMV) + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_V2) + { + std::thread thread_isp(video_proc_v2, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230D_CANMV) + { + std::thread thread_isp(video_proc_k230d, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) { - usleep(10000); + std::thread thread_isp(video_proc_01, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); } + #else + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } - isp_stop = true; - thread_isp.join(); + isp_stop = true; + thread_isp.join(); + } + #endif } else { diff --git a/src/reference/ai_poc/smoke_detect/vi_vo.h b/src/reference/ai_poc/smoke_detect/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/smoke_detect/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/space_resize/main.cc b/src/reference/ai_poc/space_resize/main.cc index ea46697c5..0d44e547e 100644 --- a/src/reference/ai_poc/space_resize/main.cc +++ b/src/reference/ai_poc/space_resize/main.cc @@ -48,7 +48,7 @@ void print_usage(const char *name) << endl; } -void video_proc(char *argv[]) +void video_proc_v1(char *argv[]) { vivcap_start(); // 设置osd参数 @@ -271,6 +271,677 @@ void video_proc(char *argv[]) } } +void video_proc_v2(char *argv[]) +{ + vivcap_start(); + // 设置osd参数 + k_video_frame_info vf_info; + void *pic_vaddr = NULL; // osd + memset(&vf_info, 0, sizeof(vf_info)); + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory,get isp memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + HandDetection hd(argv[1], atof(argv[2]), atof(argv[3]), {SENSOR_WIDTH, SENSOR_HEIGHT}, {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + HandKeypoint hk(argv[4], {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + std::vector results; + std::vector two_point; + bool first_start = true; + int two_point_left_x = 0; + int two_point_top_y = 0; + int two_point_mean_w = 0; + int two_point_mean_h = 0; + int two_point_crop_w = 0; + int two_point_crop_h = 0; + int osd_plot_x = 0; + int osd_plot_y = 0; + float ori_new_ratio = 0; + int new_resize_w = 0; + int new_resize_h = 0; + int crop_area = 0; + int rect_frame_x = 0; + int rect_frame_y = 0; + + int max_new_resize_w = 450; + int max_new_resize_h = 450; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + memset(&dump_info, 0, sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + { + ScopedTiming st("isp copy", atoi(argv[5])); + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + two_point.clear(); + + hd.pre_process(); + hd.inference(); + hd.post_process(results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::Mat osd_frame_vertical; + + float max_area_hand = 0; + int max_id_hand = -1; + for (int i = 0; i < results.size(); ++i) + { + float area_i = (results[i].x2 - results[i].x1) * (results[i].y2 - results[i].y1); + if (area_i > max_area_hand) + { + max_area_hand = area_i; + max_id_hand = i; + } + } + + if (max_id_hand != -1) + { + std::string text = hd.labels_[results[max_id_hand].label] + ":" + std::to_string(round(results[max_id_hand].score * 100) / 100.0); + + int w = results[max_id_hand].x2 - results[max_id_hand].x1 + 1; + int h = results[max_id_hand].y2 - results[max_id_hand].y1 + 1; + + int length = std::max(w,h)/2; + int cx = (results[max_id_hand].x1+results[max_id_hand].x2)/2; + int cy = (results[max_id_hand].y1+results[max_id_hand].y2)/2; + int ratio_num = 1.26*length; + + int x1_1 = std::max(0,cx-ratio_num); + int y1_1 = std::max(0,cy-ratio_num); + int x2_1 = std::min(SENSOR_WIDTH-1, cx+ratio_num); + int y2_1 = std::min(SENSOR_HEIGHT-1, cy+ratio_num); + int w_1 = x2_1 - x1_1 + 1; + int h_1 = y2_1 - y1_1 + 1; + + struct Bbox bbox = {x:x1_1,y:y1_1,w:w_1,h:h_1}; + hk.pre_process(bbox); + + hk.inference(); + + { + ScopedTiming st("osd draw", atoi(argv[5])); + hk.draw_keypoints(osd_frame, text, bbox, false, two_point); + } + } + + if(max_id_hand != -1) + { + if(first_start) + { + if(two_point[0] > 0 && two_point[0] < SENSOR_WIDTH && two_point[2] > 0 && two_point[2] < SENSOR_WIDTH && two_point[1] > 0 && two_point[1] < SENSOR_HEIGHT && two_point[3] > 0 && two_point[3] < SENSOR_HEIGHT) + { + two_point_mean_w = std::sqrt(std::pow((two_point[0] - two_point[2]),2) + std::pow((two_point[1] - two_point[3]),2))*0.8; + two_point_mean_h = std::sqrt(std::pow((two_point[0] - two_point[2]),2) + std::pow((two_point[1] - two_point[3]),2))*0.8; + first_start = false; + } + } + else + { + if(two_point[0] > 0 && two_point[0] < SENSOR_WIDTH && two_point[2] > 0 && two_point[2] < SENSOR_WIDTH && two_point[1] > 0 && two_point[1] < SENSOR_HEIGHT && two_point[3] > 0 && two_point[3] < SENSOR_HEIGHT) + { + two_point_left_x = std::max((two_point[0] + two_point[2]) / 2 - two_point_mean_w / 2, 0); + two_point_top_y = std::max((two_point[1] + two_point[3]) / 2 - two_point_mean_h / 2, 0); + two_point_crop_w = std::min(std::min((two_point[0] + two_point[2]) / 2 - two_point_mean_w / 2 + two_point_mean_w , two_point_mean_w), SENSOR_WIDTH - ((two_point[0] + two_point[2]) / 2 - two_point_mean_w / 2)); + two_point_crop_h = std::min(std::min((two_point[1] + two_point[3]) / 2 - two_point_mean_h / 2 + two_point_mean_h , two_point_mean_h), SENSOR_HEIGHT - ((two_point[1] + two_point[3]) / 2 - two_point_mean_h / 2)); + + ori_new_ratio = std::sqrt(std::pow((two_point[0] - two_point[2]),2) + std::pow((two_point[1] - two_point[3]),2))*0.8 / two_point_mean_w; + + new_resize_w = two_point_crop_w * ori_new_ratio / SENSOR_WIDTH * osd_width; + new_resize_h = two_point_crop_h * ori_new_ratio / SENSOR_HEIGHT * osd_height; + + new_resize_w = new_resize_w < max_new_resize_w ? new_resize_w : max_new_resize_w; + new_resize_h = new_resize_h < max_new_resize_h ? new_resize_h : max_new_resize_h; + + Bbox bbox_crop = {two_point_left_x,two_point_top_y,two_point_crop_w,two_point_crop_h}; + + std::unique_ptr ai2d_builder_crop; + dims_t in_shape_crop{1, SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}; + dims_t out_shape_crop{1, 3, new_resize_h, new_resize_w}; + + runtime_tensor ai2d_in_tensor_crop = hrt::create(typecode_t::dt_uint8, in_shape_crop, hrt::pool_shared).expect("create ai2d input tensor failed"); + runtime_tensor ai2d_out_tensor_crop = hrt::create(typecode_t::dt_uint8, out_shape_crop, hrt::pool_shared).expect("create ai2d input tensor failed"); + + size_t isp_size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + auto buf = ai2d_in_tensor_crop.impl()->to_host().unwrap()->buffer().as_host().unwrap().map(map_access_::map_write).unwrap().buffer(); + memcpy(reinterpret_cast(buf.data()), (void *)vaddr, isp_size); + hrt::sync(ai2d_in_tensor_crop, sync_op_t::sync_write_back, true).expect("sync write_back failed"); + + Utils::crop_resize(bbox_crop, ai2d_builder_crop, ai2d_in_tensor_crop, ai2d_out_tensor_crop); + + auto vaddr_out_buf = ai2d_out_tensor_crop.impl()->to_host().unwrap()->buffer().as_host().unwrap().map(map_access_::map_read).unwrap().buffer(); + unsigned char *output = reinterpret_cast(vaddr_out_buf.data()); + + crop_area = new_resize_h*new_resize_w; + for(uint32_t hh = 0; hh < new_resize_h; hh++) + { + for(uint32_t ww = 0; ww < new_resize_w; ww++) + { + int new_hh = (hh + two_point_top_y * 1.0 / SENSOR_HEIGHT * osd_height); + int new_ww = (ww + two_point_left_x * 1.0 / SENSOR_WIDTH * osd_width); + int osd_channel_index = (new_hh * osd_width + new_ww) * 4; + if(osd_frame.data[osd_channel_index + 0] == 0) + { + int ori_pix_index = hh * new_resize_w + ww; + osd_frame.data[osd_channel_index + 0] = 255; + osd_frame.data[osd_channel_index + 1] = output[ori_pix_index]; + osd_frame.data[osd_channel_index + 2] = output[ori_pix_index + crop_area]; + osd_frame.data[osd_channel_index + 3] = output[ori_pix_index + crop_area * 2]; + } + } + } + + rect_frame_x = two_point_left_x * 1.0 / SENSOR_WIDTH * osd_width; + rect_frame_y = two_point_top_y * 1.0 / SENSOR_HEIGHT * osd_height; + cv::rectangle(osd_frame, cv::Rect(rect_frame_x, rect_frame_y , new_resize_w, new_resize_h), cv::Scalar( 255,0, 255, 255), 2, 2, 0); + } + } + } + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + // 显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id + 3, &vf_info); // K_VO_OSD0 + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } +} + +void video_proc_k230d(char *argv[]) +{ + vivcap_start(); + // 设置osd参数 + k_video_frame_info vf_info; + void *pic_vaddr = NULL; // osd + memset(&vf_info, 0, sizeof(vf_info)); + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory,get isp memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + HandDetection hd(argv[1], atof(argv[2]), atof(argv[3]), {SENSOR_WIDTH, SENSOR_HEIGHT}, {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + HandKeypoint hk(argv[4], {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + std::vector results; + std::vector two_point; + bool first_start = true; + int two_point_left_x = 0; + int two_point_top_y = 0; + int two_point_mean_w = 0; + int two_point_mean_h = 0; + int two_point_crop_w = 0; + int two_point_crop_h = 0; + int osd_plot_x = 0; + int osd_plot_y = 0; + float ori_new_ratio = 0; + int new_resize_w = 0; + int new_resize_h = 0; + int crop_area = 0; + int rect_frame_x = 0; + int rect_frame_y = 0; + + int max_new_resize_w = 300; + int max_new_resize_h = 300; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + memset(&dump_info, 0, sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + { + ScopedTiming st("isp copy", atoi(argv[5])); + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + two_point.clear(); + + hd.pre_process(); + hd.inference(); + hd.post_process(results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + float max_area_hand = 0; + int max_id_hand = -1; + for (int i = 0; i < results.size(); ++i) + { + float area_i = (results[i].x2 - results[i].x1) * (results[i].y2 - results[i].y1); + if (area_i > max_area_hand) + { + max_area_hand = area_i; + max_id_hand = i; + } + } + + if (max_id_hand != -1) + { + std::string text = hd.labels_[results[max_id_hand].label] + ":" + std::to_string(round(results[max_id_hand].score * 100) / 100.0); + + int w = results[max_id_hand].x2 - results[max_id_hand].x1 + 1; + int h = results[max_id_hand].y2 - results[max_id_hand].y1 + 1; + + int length = std::max(w,h)/2; + int cx = (results[max_id_hand].x1+results[max_id_hand].x2)/2; + int cy = (results[max_id_hand].y1+results[max_id_hand].y2)/2; + int ratio_num = 1.26*length; + + int x1_1 = std::max(0,cx-ratio_num); + int y1_1 = std::max(0,cy-ratio_num); + int x2_1 = std::min(SENSOR_WIDTH-1, cx+ratio_num); + int y2_1 = std::min(SENSOR_HEIGHT-1, cy+ratio_num); + int w_1 = x2_1 - x1_1 + 1; + int h_1 = y2_1 - y1_1 + 1; + + struct Bbox bbox = {x:x1_1,y:y1_1,w:w_1,h:h_1}; + hk.pre_process(bbox); + + hk.inference(); + + { + ScopedTiming st("osd draw", atoi(argv[5])); + hk.draw_keypoints(osd_frame, text, bbox, false, two_point); + } + } + + if(max_id_hand != -1) + { + if(first_start) + { + if(two_point[0] > 0 && two_point[0] < SENSOR_WIDTH && two_point[2] > 0 && two_point[2] < SENSOR_WIDTH && two_point[1] > 0 && two_point[1] < SENSOR_HEIGHT && two_point[3] > 0 && two_point[3] < SENSOR_HEIGHT) + { + two_point_mean_w = std::sqrt(std::pow((two_point[0] - two_point[2]),2) + std::pow((two_point[1] - two_point[3]),2))*0.8; + two_point_mean_h = std::sqrt(std::pow((two_point[0] - two_point[2]),2) + std::pow((two_point[1] - two_point[3]),2))*0.8; + first_start = false; + } + } + else + { + if(two_point[0] > 0 && two_point[0] < SENSOR_WIDTH && two_point[2] > 0 && two_point[2] < SENSOR_WIDTH && two_point[1] > 0 && two_point[1] < SENSOR_HEIGHT && two_point[3] > 0 && two_point[3] < SENSOR_HEIGHT) + { + two_point_left_x = std::max((two_point[0] + two_point[2]) / 2 - two_point_mean_w / 2, 0); + two_point_top_y = std::max((two_point[1] + two_point[3]) / 2 - two_point_mean_h / 2, 0); + two_point_crop_w = std::min(std::min((two_point[0] + two_point[2]) / 2 - two_point_mean_w / 2 + two_point_mean_w , two_point_mean_w), SENSOR_WIDTH - ((two_point[0] + two_point[2]) / 2 - two_point_mean_w / 2)); + two_point_crop_h = std::min(std::min((two_point[1] + two_point[3]) / 2 - two_point_mean_h / 2 + two_point_mean_h , two_point_mean_h), SENSOR_HEIGHT - ((two_point[1] + two_point[3]) / 2 - two_point_mean_h / 2)); + + ori_new_ratio = std::sqrt(std::pow((two_point[0] - two_point[2]),2) + std::pow((two_point[1] - two_point[3]),2))*0.8 / two_point_mean_w; + + new_resize_w = two_point_crop_w * ori_new_ratio / SENSOR_WIDTH * osd_frame.cols; + new_resize_h = two_point_crop_h * ori_new_ratio / SENSOR_HEIGHT * osd_frame.rows; + + new_resize_w = new_resize_w < max_new_resize_w ? new_resize_w : max_new_resize_w; + new_resize_h = new_resize_h < max_new_resize_h ? new_resize_h : max_new_resize_h; + + Bbox bbox_crop = {two_point_left_x,two_point_top_y,two_point_crop_w,two_point_crop_h}; + + std::unique_ptr ai2d_builder_crop; + dims_t in_shape_crop{1, SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}; + dims_t out_shape_crop{1, 3, new_resize_h, new_resize_w}; + + runtime_tensor ai2d_in_tensor_crop = hrt::create(typecode_t::dt_uint8, in_shape_crop, hrt::pool_shared).expect("create ai2d input tensor failed"); + runtime_tensor ai2d_out_tensor_crop = hrt::create(typecode_t::dt_uint8, out_shape_crop, hrt::pool_shared).expect("create ai2d input tensor failed"); + + size_t isp_size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + auto buf = ai2d_in_tensor_crop.impl()->to_host().unwrap()->buffer().as_host().unwrap().map(map_access_::map_write).unwrap().buffer(); + memcpy(reinterpret_cast(buf.data()), (void *)vaddr, isp_size); + hrt::sync(ai2d_in_tensor_crop, sync_op_t::sync_write_back, true).expect("sync write_back failed"); + + Utils::crop_resize(bbox_crop, ai2d_builder_crop, ai2d_in_tensor_crop, ai2d_out_tensor_crop); + + auto vaddr_out_buf = ai2d_out_tensor_crop.impl()->to_host().unwrap()->buffer().as_host().unwrap().map(map_access_::map_read).unwrap().buffer(); + unsigned char *output = reinterpret_cast(vaddr_out_buf.data()); + + crop_area = new_resize_h*new_resize_w; + for(uint32_t hh = 0; hh < new_resize_h; hh++) + { + for(uint32_t ww = 0; ww < new_resize_w; ww++) + { + int new_hh = (hh + two_point_top_y * 1.0 / SENSOR_HEIGHT * osd_frame.rows); + int new_ww = (ww + two_point_left_x * 1.0 / SENSOR_WIDTH * osd_frame.cols); + int osd_channel_index = (new_hh * osd_frame.cols + new_ww) * 4; + if(osd_frame.data[osd_channel_index + 0] == 0) + { + int ori_pix_index = hh * new_resize_w + ww; + osd_frame.data[osd_channel_index + 0] = 255; + osd_frame.data[osd_channel_index + 1] = output[ori_pix_index]; + osd_frame.data[osd_channel_index + 2] = output[ori_pix_index + crop_area]; + osd_frame.data[osd_channel_index + 3] = output[ori_pix_index + crop_area * 2]; + } + } + } + + rect_frame_x = two_point_left_x * 1.0 / SENSOR_WIDTH * osd_frame.cols; + rect_frame_y = two_point_top_y * 1.0 / SENSOR_HEIGHT * osd_frame.rows; + cv::rectangle(osd_frame, cv::Rect(rect_frame_x, rect_frame_y , new_resize_w, new_resize_h), cv::Scalar( 255,0, 255, 255), 2, 2, 0); + } + } + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + // 显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id + 3, &vf_info); // K_VO_OSD0 + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } +} + +void video_proc_01(char *argv[]) +{ + vivcap_start(); + // 设置osd参数 + k_video_frame_info vf_info; + void *pic_vaddr = NULL; // osd + memset(&vf_info, 0, sizeof(vf_info)); + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory,get isp memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + HandDetection hd(argv[1], atof(argv[2]), atof(argv[3]), {SENSOR_WIDTH, SENSOR_HEIGHT}, {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + HandKeypoint hk(argv[4], {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + std::vector results; + std::vector two_point; + bool first_start = true; + int two_point_left_x = 0; + int two_point_top_y = 0; + int two_point_mean_w = 0; + int two_point_mean_h = 0; + int two_point_crop_w = 0; + int two_point_crop_h = 0; + int osd_plot_x = 0; + int osd_plot_y = 0; + float ori_new_ratio = 0; + int new_resize_w = 0; + int new_resize_h = 0; + int crop_area = 0; + int rect_frame_x = 0; + int rect_frame_y = 0; + + int max_new_resize_w = 300; + int max_new_resize_h = 300; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + memset(&dump_info, 0, sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + { + ScopedTiming st("isp copy", atoi(argv[5])); + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + two_point.clear(); + + hd.pre_process(); + hd.inference(); + hd.post_process(results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + float max_area_hand = 0; + int max_id_hand = -1; + for (int i = 0; i < results.size(); ++i) + { + float area_i = (results[i].x2 - results[i].x1) * (results[i].y2 - results[i].y1); + if (area_i > max_area_hand) + { + max_area_hand = area_i; + max_id_hand = i; + } + } + + if (max_id_hand != -1) + { + std::string text = hd.labels_[results[max_id_hand].label] + ":" + std::to_string(round(results[max_id_hand].score * 100) / 100.0); + + int w = results[max_id_hand].x2 - results[max_id_hand].x1 + 1; + int h = results[max_id_hand].y2 - results[max_id_hand].y1 + 1; + + int length = std::max(w,h)/2; + int cx = (results[max_id_hand].x1+results[max_id_hand].x2)/2; + int cy = (results[max_id_hand].y1+results[max_id_hand].y2)/2; + int ratio_num = 1.26*length; + + int x1_1 = std::max(0,cx-ratio_num); + int y1_1 = std::max(0,cy-ratio_num); + int x2_1 = std::min(SENSOR_WIDTH-1, cx+ratio_num); + int y2_1 = std::min(SENSOR_HEIGHT-1, cy+ratio_num); + int w_1 = x2_1 - x1_1 + 1; + int h_1 = y2_1 - y1_1 + 1; + + struct Bbox bbox = {x:x1_1,y:y1_1,w:w_1,h:h_1}; + hk.pre_process(bbox); + + hk.inference(); + + { + ScopedTiming st("osd draw", atoi(argv[5])); + hk.draw_keypoints(osd_frame, text, bbox, false, two_point); + } + } + + if(max_id_hand != -1) + { + if(first_start) + { + if(two_point[0] > 0 && two_point[0] < SENSOR_WIDTH && two_point[2] > 0 && two_point[2] < SENSOR_WIDTH && two_point[1] > 0 && two_point[1] < SENSOR_HEIGHT && two_point[3] > 0 && two_point[3] < SENSOR_HEIGHT) + { + two_point_mean_w = std::sqrt(std::pow((two_point[0] - two_point[2]),2) + std::pow((two_point[1] - two_point[3]),2))*0.8; + two_point_mean_h = std::sqrt(std::pow((two_point[0] - two_point[2]),2) + std::pow((two_point[1] - two_point[3]),2))*0.8; + first_start = false; + } + } + else + { + if(two_point[0] > 0 && two_point[0] < SENSOR_WIDTH && two_point[2] > 0 && two_point[2] < SENSOR_WIDTH && two_point[1] > 0 && two_point[1] < SENSOR_HEIGHT && two_point[3] > 0 && two_point[3] < SENSOR_HEIGHT) + { + two_point_left_x = std::max((two_point[0] + two_point[2]) / 2 - two_point_mean_w / 2, 0); + two_point_top_y = std::max((two_point[1] + two_point[3]) / 2 - two_point_mean_h / 2, 0); + two_point_crop_w = std::min(std::min((two_point[0] + two_point[2]) / 2 - two_point_mean_w / 2 + two_point_mean_w , two_point_mean_w), SENSOR_WIDTH - ((two_point[0] + two_point[2]) / 2 - two_point_mean_w / 2)); + two_point_crop_h = std::min(std::min((two_point[1] + two_point[3]) / 2 - two_point_mean_h / 2 + two_point_mean_h , two_point_mean_h), SENSOR_HEIGHT - ((two_point[1] + two_point[3]) / 2 - two_point_mean_h / 2)); + + ori_new_ratio = std::sqrt(std::pow((two_point[0] - two_point[2]),2) + std::pow((two_point[1] - two_point[3]),2))*0.8 / two_point_mean_w; + + new_resize_w = two_point_crop_w * ori_new_ratio / SENSOR_WIDTH * osd_frame.cols; + new_resize_h = two_point_crop_h * ori_new_ratio / SENSOR_HEIGHT * osd_frame.rows; + + new_resize_w = new_resize_w < max_new_resize_w ? new_resize_w : max_new_resize_w; + new_resize_h = new_resize_h < max_new_resize_h ? new_resize_h : max_new_resize_h; + + Bbox bbox_crop = {two_point_left_x,two_point_top_y,two_point_crop_w,two_point_crop_h}; + + std::unique_ptr ai2d_builder_crop; + dims_t in_shape_crop{1, SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}; + dims_t out_shape_crop{1, 3, new_resize_h, new_resize_w}; + + runtime_tensor ai2d_in_tensor_crop = hrt::create(typecode_t::dt_uint8, in_shape_crop, hrt::pool_shared).expect("create ai2d input tensor failed"); + runtime_tensor ai2d_out_tensor_crop = hrt::create(typecode_t::dt_uint8, out_shape_crop, hrt::pool_shared).expect("create ai2d input tensor failed"); + + size_t isp_size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + auto buf = ai2d_in_tensor_crop.impl()->to_host().unwrap()->buffer().as_host().unwrap().map(map_access_::map_write).unwrap().buffer(); + memcpy(reinterpret_cast(buf.data()), (void *)vaddr, isp_size); + hrt::sync(ai2d_in_tensor_crop, sync_op_t::sync_write_back, true).expect("sync write_back failed"); + + Utils::crop_resize(bbox_crop, ai2d_builder_crop, ai2d_in_tensor_crop, ai2d_out_tensor_crop); + + auto vaddr_out_buf = ai2d_out_tensor_crop.impl()->to_host().unwrap()->buffer().as_host().unwrap().map(map_access_::map_read).unwrap().buffer(); + unsigned char *output = reinterpret_cast(vaddr_out_buf.data()); + + crop_area = new_resize_h*new_resize_w; + for(uint32_t hh = 0; hh < new_resize_h; hh++) + { + for(uint32_t ww = 0; ww < new_resize_w; ww++) + { + int new_hh = (hh + two_point_top_y * 1.0 / SENSOR_HEIGHT * osd_frame.rows); + int new_ww = (ww + two_point_left_x * 1.0 / SENSOR_WIDTH * osd_frame.cols); + int osd_channel_index = (new_hh * osd_frame.cols + new_ww) * 4; + if(osd_frame.data[osd_channel_index + 0] == 0) + { + int ori_pix_index = hh * new_resize_w + ww; + osd_frame.data[osd_channel_index + 0] = 255; + osd_frame.data[osd_channel_index + 1] = output[ori_pix_index]; + osd_frame.data[osd_channel_index + 2] = output[ori_pix_index + crop_area]; + osd_frame.data[osd_channel_index + 3] = output[ori_pix_index + crop_area * 2]; + } + } + } + + rect_frame_x = two_point_left_x * 1.0 / SENSOR_WIDTH * osd_frame.cols; + rect_frame_y = two_point_top_y * 1.0 / SENSOR_HEIGHT * osd_frame.rows; + cv::rectangle(osd_frame, cv::Rect(rect_frame_x, rect_frame_y , new_resize_w, new_resize_h), cv::Scalar( 255,0, 255, 255), 2, 2, 0); + } + } + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + // 显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id + 3, &vf_info); // K_VO_OSD0 + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) + { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } +} + int main(int argc, char *argv[]) { @@ -280,14 +951,61 @@ int main(int argc, char *argv[]) print_usage(argv[0]); return -1; } + #if defined(CONFIG_BOARD_K230_CANMV) + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_V2) + { + std::thread thread_isp(video_proc_v2, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230D_CANMV) + { + std::thread thread_isp(video_proc_k230d, argv); + while (getchar() != 'q') + { + usleep(10000); + } - std::thread thread_isp(video_proc, argv); - while (getchar() != 'q') + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) { - usleep(10000); + std::thread thread_isp(video_proc_01, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); } + #else + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } - isp_stop = true; - thread_isp.join(); + isp_stop = true; + thread_isp.join(); + } + #endif return 0; } diff --git a/src/reference/ai_poc/space_resize/vi_vo.h b/src/reference/ai_poc/space_resize/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/space_resize/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/sq_hand_det/main.cc b/src/reference/ai_poc/sq_hand_det/main.cc index aea1d538e..d7f1fc06f 100644 --- a/src/reference/ai_poc/sq_hand_det/main.cc +++ b/src/reference/ai_poc/sq_hand_det/main.cc @@ -106,20 +106,62 @@ void video_proc(char *argv[]) hd.post_process(results); cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); - for (auto r: results) + #if defined(CONFIG_BOARD_K230D_CANMV) { - std::string text = hd.labels_[r.label] + ":" + std::to_string(round(r.score * 100) / 100.0); - std::cout << "text = " << text << std::endl; - - int w = r.x2 - r.x1 + 1; - int h = r.y2 - r.y1 + 1; - - int rect_x = r.x1/ SENSOR_WIDTH * osd_width; - int rect_y = r.y1/ SENSOR_HEIGHT * osd_height; - int rect_w = (float)w / SENSOR_WIDTH * osd_width; - int rect_h = (float)h / SENSOR_HEIGHT * osd_height; - cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w, rect_h), cv::Scalar( 255,255, 255, 255), 2, 2, 0); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + for (auto r: results) + { + std::string text = hd.labels_[r.label] + ":" + std::to_string(round(r.score * 100) / 100.0); + std::cout << "text = " << text << std::endl; + + int w = r.x2 - r.x1 + 1; + int h = r.y2 - r.y1 + 1; + + int rect_x = r.x1/ SENSOR_WIDTH * osd_height; + int rect_y = r.y1/ SENSOR_HEIGHT * osd_width; + int rect_w = (float)w / SENSOR_WIDTH * osd_height; + int rect_h = (float)h / SENSOR_HEIGHT * osd_width; + cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w, rect_h), cv::Scalar( 255,255, 255, 255), 2, 2, 0); + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + for (auto r: results) + { + std::string text = hd.labels_[r.label] + ":" + std::to_string(round(r.score * 100) / 100.0); + std::cout << "text = " << text << std::endl; + + int w = r.x2 - r.x1 + 1; + int h = r.y2 - r.y1 + 1; + + int rect_x = r.x1/ SENSOR_WIDTH * osd_height; + int rect_y = r.y1/ SENSOR_HEIGHT * osd_width; + int rect_w = (float)w / SENSOR_WIDTH * osd_height; + int rect_h = (float)h / SENSOR_HEIGHT * osd_width; + cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w, rect_h), cv::Scalar( 255,255, 255, 255), 2, 2, 0); + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #else + { + for (auto r: results) + { + std::string text = hd.labels_[r.label] + ":" + std::to_string(round(r.score * 100) / 100.0); + std::cout << "text = " << text << std::endl; + + int w = r.x2 - r.x1 + 1; + int h = r.y2 - r.y1 + 1; + + int rect_x = r.x1/ SENSOR_WIDTH * osd_width; + int rect_y = r.y1/ SENSOR_HEIGHT * osd_height; + int rect_w = (float)w / SENSOR_WIDTH * osd_width; + int rect_h = (float)h / SENSOR_HEIGHT * osd_height; + cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w, rect_h), cv::Scalar( 255,255, 255, 255), 2, 2, 0); + } } + #endif { ScopedTiming st("osd copy", atoi(argv[5])); diff --git a/src/reference/ai_poc/sq_hand_det/vi_vo.h b/src/reference/ai_poc/sq_hand_det/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/sq_hand_det/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/sq_handkp_class/main.cc b/src/reference/ai_poc/sq_handkp_class/main.cc index bb89d9145..cb981d357 100644 --- a/src/reference/ai_poc/sq_handkp_class/main.cc +++ b/src/reference/ai_poc/sq_handkp_class/main.cc @@ -108,6 +108,20 @@ void video_proc(char *argv[]) hd.post_process(results); cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + #if defined(CONFIG_BOARD_K230D_CANMV) + { + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + } + #else + { + } + #endif + + for (auto r: results) { std::string text = hd.labels_[r.label] + ":" + std::to_string(round(r.score * 100) / 100.0); @@ -116,12 +130,6 @@ void video_proc(char *argv[]) int w = r.x2 - r.x1 + 1; int h = r.y2 - r.y1 + 1; - int rect_x = r.x1/ SENSOR_WIDTH * osd_width; - int rect_y = r.y1/ SENSOR_HEIGHT * osd_height; - int rect_w = (float)w / SENSOR_WIDTH * osd_width; - int rect_h = (float)h / SENSOR_HEIGHT * osd_height; - cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w, rect_h), cv::Scalar( 255,255, 255, 255), 2, 2, 0); - int length = std::max(w,h)/2; int cx = (r.x1+r.x2)/2; int cy = (r.y1+r.y2)/2; @@ -136,23 +144,68 @@ void video_proc(char *argv[]) struct Bbox bbox = {x:x1_1,y:y1_1,w:w_1,h:h_1}; hk.pre_process(bbox); - hk.inference(); - hk.post_process(bbox); + std::vector angle_list = hk.hand_angle(); + std::string gesture = hk.h_gesture(angle_list); + + #if defined(CONFIG_BOARD_K230D_CANMV) + { + int rect_x = r.x1/ SENSOR_WIDTH * osd_height; + int rect_y = r.y1/ SENSOR_HEIGHT * osd_width; + int rect_w = (float)w / SENSOR_WIDTH * osd_height; + int rect_h = (float)h / SENSOR_HEIGHT * osd_width; + + cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w, rect_h), cv::Scalar( 255,255, 255, 255), 2, 2, 0); + std::string text1 = "Gesture: " + gesture; + cv::putText(osd_frame, text1, cv::Point(rect_x,rect_y),cv::FONT_HERSHEY_COMPLEX, 1, cv::Scalar(255, 255, 195, 0), 2); + cv::putText(osd_frame, text1, cv::Point(rect_x,rect_y),cv::FONT_HERSHEY_COMPLEX, 1, cv::Scalar(255, 0, 150, 255), 2); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + int rect_x = r.x1/ SENSOR_WIDTH * osd_height; + int rect_y = r.y1/ SENSOR_HEIGHT * osd_width; + int rect_w = (float)w / SENSOR_WIDTH * osd_height; + int rect_h = (float)h / SENSOR_HEIGHT * osd_width; + + cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w, rect_h), cv::Scalar( 255,255, 255, 255), 2, 2, 0); + std::string text1 = "Gesture: " + gesture; + cv::putText(osd_frame, text1, cv::Point(rect_x,rect_y),cv::FONT_HERSHEY_COMPLEX, 1, cv::Scalar(255, 255, 195, 0), 2); + cv::putText(osd_frame, text1, cv::Point(rect_x,rect_y),cv::FONT_HERSHEY_COMPLEX, 1, cv::Scalar(255, 0, 150, 255), 2); + } + #else + { + int rect_x = r.x1/ SENSOR_WIDTH * osd_width; + int rect_y = r.y1/ SENSOR_HEIGHT * osd_height; + int rect_w = (float)w / SENSOR_WIDTH * osd_width; + int rect_h = (float)h / SENSOR_HEIGHT * osd_height; + + cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w, rect_h), cv::Scalar( 255,255, 255, 255), 2, 2, 0); + std::string text1 = "Gesture: " + gesture; + cv::putText(osd_frame, text1, cv::Point(rect_x,rect_y),cv::FONT_HERSHEY_COMPLEX, 1, cv::Scalar(255, 255, 195, 0), 2); + cv::putText(osd_frame, text1, cv::Point(rect_x,rect_y),cv::FONT_HERSHEY_COMPLEX, 1, cv::Scalar(255, 0, 150, 255), 2); + } + #endif + { ScopedTiming st("osd draw keypoints", atoi(argv[6])); hk.draw_keypoints(osd_frame, text, bbox, false); } + } - std::vector angle_list = hk.hand_angle(); - std::string gesture = hk.h_gesture(angle_list); - - std::string text1 = "Gesture: " + gesture; - cv::putText(osd_frame, text1, cv::Point(rect_x,rect_y),cv::FONT_HERSHEY_COMPLEX, 1, cv::Scalar(255, 255, 195, 0), 2); - cv::putText(osd_frame, text1, cv::Point(rect_x,rect_y),cv::FONT_HERSHEY_COMPLEX, 1, cv::Scalar(255, 0, 150, 255), 2); + #if defined(CONFIG_BOARD_K230D_CANMV) + { + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #else + { } + #endif { ScopedTiming st("osd copy", atoi(argv[6])); diff --git a/src/reference/ai_poc/sq_handkp_class/vi_vo.h b/src/reference/ai_poc/sq_handkp_class/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/sq_handkp_class/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/sq_handkp_det/main.cc b/src/reference/ai_poc/sq_handkp_det/main.cc index ca9c0c1b8..e0cc59e72 100644 --- a/src/reference/ai_poc/sq_handkp_det/main.cc +++ b/src/reference/ai_poc/sq_handkp_det/main.cc @@ -108,6 +108,19 @@ void video_proc(char *argv[]) hd.post_process(results); cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + #if defined(CONFIG_BOARD_K230D_CANMV) + { + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + } + #else + { + } + #endif + for (auto r: results) { std::string text = hd.labels_[r.label] + ":" + std::to_string(round(r.score * 100) / 100.0); @@ -115,12 +128,6 @@ void video_proc(char *argv[]) int w = r.x2 - r.x1 + 1; int h = r.y2 - r.y1 + 1; - int rect_x = r.x1/ SENSOR_WIDTH * osd_width; - int rect_y = r.y1/ SENSOR_HEIGHT * osd_height; - int rect_w = (float)w / SENSOR_WIDTH * osd_width; - int rect_h = (float)h / SENSOR_HEIGHT * osd_height; - cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w, rect_h), cv::Scalar( 255,255, 255, 255), 2, 2, 0); - int length = std::max(w,h)/2; int cx = (r.x1+r.x2)/2; int cy = (r.y1+r.y2)/2; @@ -135,15 +142,56 @@ void video_proc(char *argv[]) struct Bbox bbox = {x:x1_1,y:y1_1,w:w_1,h:h_1}; hk.pre_process(bbox); - hk.inference(); + #if defined(CONFIG_BOARD_K230D_CANMV) + { + int rect_x = r.x1/ SENSOR_WIDTH * osd_height; + int rect_y = r.y1/ SENSOR_HEIGHT * osd_width; + int rect_w = (float)w / SENSOR_WIDTH * osd_height; + int rect_h = (float)h / SENSOR_HEIGHT * osd_width; + + cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w, rect_h), cv::Scalar( 255,255, 255, 255), 2, 2, 0); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + int rect_x = r.x1/ SENSOR_WIDTH * osd_height; + int rect_y = r.y1/ SENSOR_HEIGHT * osd_width; + int rect_w = (float)w / SENSOR_WIDTH * osd_height; + int rect_h = (float)h / SENSOR_HEIGHT * osd_width; + + cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w, rect_h), cv::Scalar( 255,255, 255, 255), 2, 2, 0); + } + #else + { + int rect_x = r.x1/ SENSOR_WIDTH * osd_width; + int rect_y = r.y1/ SENSOR_HEIGHT * osd_height; + int rect_w = (float)w / SENSOR_WIDTH * osd_width; + int rect_h = (float)h / SENSOR_HEIGHT * osd_height; + + cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w, rect_h), cv::Scalar( 255,255, 255, 255), 2, 2, 0); + } + #endif + { ScopedTiming st("osd draw", atoi(argv[6])); hk.draw_keypoints(osd_frame, text, bbox, false); } } + #if defined(CONFIG_BOARD_K230D_CANMV) + { + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #else + { + } + #endif + { ScopedTiming st("osd copy", atoi(argv[6])); memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); diff --git a/src/reference/ai_poc/sq_handkp_det/vi_vo.h b/src/reference/ai_poc/sq_handkp_det/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/sq_handkp_det/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/sq_handkp_flower/main.cc b/src/reference/ai_poc/sq_handkp_flower/main.cc index 0fc31b543..3ada1ea3f 100644 --- a/src/reference/ai_poc/sq_handkp_flower/main.cc +++ b/src/reference/ai_poc/sq_handkp_flower/main.cc @@ -49,7 +49,7 @@ void print_usage(const char *name) << " nms_thresh 手掌检测kmodel nms阈值\n" << " kmodel_kp 手势关键点检测kmodel路径\n" << " flower_rec 花卉识别kmodel路径 \n" - << " debug_mode 是否需要调试，0、1、2分别表示不调试、简单调试、详细调试\n" + << " debug_mode 是否需要调试, 0、1、2分别表示不调试、简单调试、详细调试\n" << "\n" << endl; } @@ -122,6 +122,18 @@ void video_proc(char *argv[]) fi ++; cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + #if defined(CONFIG_BOARD_K230D_CANMV) + { + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + } + #else + { + } + #endif if (frameTrackingResult.size()>=2 && fi>=5) { @@ -131,11 +143,36 @@ void video_proc(char *argv[]) for(int i=0;i< frameTrackingResult.size();i++) { auto tb = frameTrackingResult[i]; - int rect_x = tb.box.x / SENSOR_WIDTH * osd_width; - int rect_y = tb.box.y / SENSOR_HEIGHT * osd_height; - int rect_w = (float)tb.box.width / SENSOR_WIDTH * osd_width; - int rect_h = (float)tb.box.height / SENSOR_HEIGHT * osd_height; - cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y, rect_w, rect_h), cv::Scalar( 255,255, 0, 255), 2, 2, 0); + + #if defined(CONFIG_BOARD_K230D_CANMV) + { + int rect_x = tb.box.x/ SENSOR_WIDTH * osd_height; + int rect_y = tb.box.y/ SENSOR_HEIGHT * osd_width; + int rect_w = (float)tb.box.width / SENSOR_WIDTH * osd_height; + int rect_h = (float)tb.box.height / SENSOR_HEIGHT * osd_width; + + cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y, rect_w, rect_h), cv::Scalar( 255,255, 0, 255), 2, 2, 0); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + int rect_x = tb.box.x/ SENSOR_WIDTH * osd_height; + int rect_y = tb.box.y/ SENSOR_HEIGHT * osd_width; + int rect_w = (float)tb.box.width / SENSOR_WIDTH * osd_height; + int rect_h = (float)tb.box.height / SENSOR_HEIGHT * osd_width; + + cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y, rect_w, rect_h), cv::Scalar( 255,255, 0, 255), 2, 2, 0); + } + #else + { + int rect_x = tb.box.x / SENSOR_WIDTH * osd_width; + int rect_y = tb.box.y / SENSOR_HEIGHT * osd_height; + int rect_w = (float)tb.box.width / SENSOR_WIDTH * osd_width; + int rect_h = (float)tb.box.height / SENSOR_HEIGHT * osd_height; + + cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y, rect_w, rect_h), cv::Scalar( 255,255, 0, 255), 2, 2, 0); + } + #endif + std::string num = std::to_string(tb.id); int length = std::max(tb.box.width,tb.box.height)/2; @@ -166,8 +203,22 @@ void video_proc(char *argv[]) left_top.x = left_pred_x * w_1 + x1_1; left_top.y = left_pred_y * h_1 + y1_1; - draw_x = left_top.x / SENSOR_WIDTH * osd_width; - draw_y = left_top.y / SENSOR_HEIGHT * osd_height; + #if defined(CONFIG_BOARD_K230D_CANMV) + { + draw_x = left_top.x / SENSOR_WIDTH * osd_height; + draw_y = left_top.y / SENSOR_HEIGHT * osd_width; + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + draw_x = left_top.x / SENSOR_WIDTH * osd_height; + draw_y = left_top.y / SENSOR_HEIGHT * osd_width; + } + #else + { + draw_x = left_top.x / SENSOR_WIDTH * osd_width; + draw_y = left_top.y / SENSOR_HEIGHT * osd_height; + } + #endif } else if (i==1) { @@ -177,8 +228,22 @@ void video_proc(char *argv[]) right_bottom.x = right_pred_x * w_1 + x1_1; right_bottom.y = right_pred_y * h_1 + y1_1; - draw_x = right_bottom.x / SENSOR_WIDTH * osd_width; - draw_y = right_bottom.y / SENSOR_HEIGHT * osd_height; + #if defined(CONFIG_BOARD_K230D_CANMV) + { + draw_x = right_bottom.x / SENSOR_WIDTH * osd_height; + draw_y = right_bottom.y / SENSOR_HEIGHT * osd_width; + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + draw_x = right_bottom.x / SENSOR_WIDTH * osd_height; + draw_y = right_bottom.y / SENSOR_HEIGHT * osd_width; + } + #else + { + draw_x = right_bottom.x / SENSOR_WIDTH * osd_width; + draw_y = right_bottom.y / SENSOR_HEIGHT * osd_height; + } + #endif } cv::circle(osd_frame, cv::Point(draw_x, draw_y), 6, cv::Scalar(255, 0,0,0), 3); @@ -201,13 +266,51 @@ void video_proc(char *argv[]) std::string text = fr.post_process(); - int x = 1.0 * x_min/ SENSOR_WIDTH * osd_width; - int y = 1.0 * y_min / SENSOR_HEIGHT * osd_height; - int w = 1.0 * (x_max-x_min) / SENSOR_WIDTH * osd_width; - int h = 1.0 * (y_max-y_min) / SENSOR_HEIGHT * osd_height; - cv::putText(osd_frame, text, cv::Point(x, y-20),cv::FONT_HERSHEY_COMPLEX, 1, cv::Scalar(255, 255, 0, 0), 2); - cv::rectangle(osd_frame, cv::Rect(x, y , w, h), cv::Scalar( 255,0, 255, 255), 2, 2, 0); + #if defined(CONFIG_BOARD_K230D_CANMV) + { + int x = 1.0 * x_min/ SENSOR_WIDTH * osd_height; + int y = 1.0 * y_min / SENSOR_HEIGHT * osd_width; + int w = 1.0 * (x_max-x_min) / SENSOR_WIDTH * osd_height; + int h = 1.0 * (y_max-y_min) / SENSOR_HEIGHT * osd_width; + + cv::putText(osd_frame, text, cv::Point(x, y-20),cv::FONT_HERSHEY_COMPLEX, 1, cv::Scalar(255, 255, 0, 0), 2); + cv::rectangle(osd_frame, cv::Rect(x, y , w, h), cv::Scalar( 255,0, 255, 255), 2, 2, 0); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + int x = 1.0 * x_min/ SENSOR_WIDTH * osd_height; + int y = 1.0 * y_min / SENSOR_HEIGHT * osd_width; + int w = 1.0 * (x_max-x_min) / SENSOR_WIDTH * osd_height; + int h = 1.0 * (y_max-y_min) / SENSOR_HEIGHT * osd_width; + + cv::putText(osd_frame, text, cv::Point(x, y-20),cv::FONT_HERSHEY_COMPLEX, 1, cv::Scalar(255, 255, 0, 0), 2); + cv::rectangle(osd_frame, cv::Rect(x, y , w, h), cv::Scalar( 255,0, 255, 255), 2, 2, 0); + } + #else + { + int x = 1.0 * x_min/ SENSOR_WIDTH * osd_width; + int y = 1.0 * y_min / SENSOR_HEIGHT * osd_height; + int w = 1.0 * (x_max-x_min) / SENSOR_WIDTH * osd_width; + int h = 1.0 * (y_max-y_min) / SENSOR_HEIGHT * osd_height; + + cv::putText(osd_frame, text, cv::Point(x, y-20),cv::FONT_HERSHEY_COMPLEX, 1, cv::Scalar(255, 255, 0, 0), 2); + cv::rectangle(osd_frame, cv::Rect(x, y , w, h), cv::Scalar( 255,0, 255, 255), 2, 2, 0); + } + #endif + } + + #if defined(CONFIG_BOARD_K230D_CANMV) + { + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #else + { } + #endif { ScopedTiming st("osd copy", atoi(argv[7])); memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); diff --git a/src/reference/ai_poc/sq_handkp_flower/vi_vo.h b/src/reference/ai_poc/sq_handkp_flower/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/sq_handkp_flower/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/sq_handkp_ocr/main.cc b/src/reference/ai_poc/sq_handkp_ocr/main.cc index 3f97fb8bd..4bf1d6d07 100755 --- a/src/reference/ai_poc/sq_handkp_ocr/main.cc +++ b/src/reference/ai_poc/sq_handkp_ocr/main.cc @@ -84,8 +84,23 @@ int ocr_process(OCRBox &ocrbox, OCRReco &ocrreco,cv::Mat ori_img, cv::Mat& osd_f for(int j = 0; j < 4; j++) { cv::Point tmp = ocrbox_results[i].vertices[j]; - tmp.x = (1.0*(tmp.x+xmin)/SENSOR_WIDTH)*osd_width; - tmp.y = (1.0*(tmp.y+ymin)/SENSOR_HEIGHT)*osd_height; + + #if defined(CONFIG_BOARD_K230D_CANMV) + { + tmp.x = (1.0*(tmp.x+xmin)/SENSOR_WIDTH)*osd_height; + tmp.y = (1.0*(tmp.y+ymin)/SENSOR_HEIGHT)*osd_width; + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + tmp.x = (1.0*(tmp.x+xmin)/SENSOR_WIDTH)*osd_height; + tmp.y = (1.0*(tmp.y+ymin)/SENSOR_HEIGHT)*osd_width; + } + #else + { + tmp.x = (1.0*(tmp.x+xmin)/SENSOR_WIDTH)*osd_width; + tmp.y = (1.0*(tmp.y+ymin)/SENSOR_HEIGHT)*osd_height; + } + #endif vec.push_back(tmp); } @@ -187,109 +202,331 @@ void video_proc(char *argv[]) fi ++; cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); - for (auto r: results) + + #if defined(CONFIG_BOARD_K230D_CANMV) { - std::string text = hd.labels_[r.label] + ":" + std::to_string(round(r.score * 100) / 100.0); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + for (auto r: results) + { + std::string text = hd.labels_[r.label] + ":" + std::to_string(round(r.score * 100) / 100.0); - int w = r.x2 - r.x1 + 1; - int h = r.y2 - r.y1 + 1; - - int rect_x = r.x1/ SENSOR_WIDTH * osd_width; - int rect_y = r.y1 / SENSOR_HEIGHT * osd_height; - int rect_w = (float)w / SENSOR_WIDTH * osd_width; - int rect_h = (float)h / SENSOR_HEIGHT * osd_height; - cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w, rect_h), cv::Scalar( 255,255, 255, 255), 2, 2, 0); - } + int w = r.x2 - r.x1 + 1; + int h = r.y2 - r.y1 + 1; + + int rect_x = r.x1/ SENSOR_WIDTH * osd_height; + int rect_y = r.y1 / SENSOR_HEIGHT * osd_width; + int rect_w = (float)w / SENSOR_WIDTH * osd_height; + int rect_h = (float)h / SENSOR_HEIGHT * osd_width; + cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w, rect_h), cv::Scalar( 255,255, 255, 255), 2, 2, 0); + } - if (frameTrackingResult.size()>0 && fi>=5) - { - cv::Point2f left_top; - int index1 = 1; + if (frameTrackingResult.size()>0 && fi>=5) + { + cv::Point2f left_top; + int index1 = 1; + + for(int i=0;i< frameTrackingResult.size();i++) + { + auto tb = frameTrackingResult[i]; + int rect_x = tb.box.x / SENSOR_WIDTH * osd_height; + int rect_y = tb.box.y / SENSOR_HEIGHT * osd_width; + int rect_w = (float)tb.box.width / SENSOR_WIDTH * osd_height; + int rect_h = (float)tb.box.height / SENSOR_HEIGHT * osd_width; + cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w + 20, rect_h + 20), cv::Scalar( 255,255, 0, 255), 2, 2, 0); + std::string num = std::to_string(tb.id); + + int length = std::max(tb.box.width,tb.box.height)/2; + int cx = tb.box.x+tb.box.width/2; + int cy = tb.box.y+tb.box.height/2; + int ratio_num = 1.26*length; + + int x1_1 = std::max(0,cx-ratio_num); + int y1_1 = std::max(0,cy-ratio_num); + int x2_1 = std::min(SENSOR_WIDTH-1, cx+ratio_num); + int y2_1 = std::min(SENSOR_HEIGHT-1, cy+ratio_num); + int w_1 = x2_1 - x1_1 + 1; + int h_1 = y2_1 - y1_1 + 1; + + struct Bbox bbox = {x:x1_1,y:y1_1,w:w_1,h:h_1}; + hk.pre_process(bbox); + + hk.inference(); + + float *pred = hk.get_out()[0]; + int draw_x,draw_y; - for(int i=0;i< frameTrackingResult.size();i++) + float pred_x = std::max(std::min(pred[(index1+1)*4*2], 1.0f), 0.0f); + float pred_y = std::max(std::min(pred[(index1+1)*4*2+1], 1.0f), 0.0f); + + left_top.x = pred_x * w_1 + x1_1; + left_top.y = pred_y * h_1 + y1_1; + draw_x = left_top.x / SENSOR_WIDTH * osd_height; + draw_y = left_top.y / SENSOR_HEIGHT * osd_width; + + cv::circle(osd_frame, cv::Point(draw_x, draw_y), 6, cv::Scalar(255, 0,0,0), 3); + cv::circle(osd_frame, cv::Point(draw_x, draw_y), 5, cv::Scalar(255, 0,0,0), 3); + + + ScopedTiming st("osd draw", atoi(argv[10])); + hk.draw_keypoints(osd_frame, num, bbox, false); + + } + + int x_min = std::max(static_cast(left_top.x-500), 0); + int x_max = std::min(static_cast(left_top.x), SENSOR_WIDTH); + int y_min = std::max(static_cast(left_top.y-300), 0); + int y_max = std::min(static_cast(left_top.y), SENSOR_HEIGHT); + Bbox box_info = {x_min,y_min, (x_max-x_min),(y_max-y_min)}; + + if ((x_max-x_min>32) && (y_max-y_min>32)) + { + { + int matsize = SENSOR_WIDTH * SENSOR_HEIGHT; + + cv::Mat ori_img; + cv::Mat ori_img_R = cv::Mat(SENSOR_HEIGHT, SENSOR_WIDTH, CV_8UC1, vaddr); + cv::Mat ori_img_G = cv::Mat(SENSOR_HEIGHT, SENSOR_WIDTH, CV_8UC1, vaddr + 1 * matsize); + cv::Mat ori_img_B = cv::Mat(SENSOR_HEIGHT, SENSOR_WIDTH, CV_8UC1, vaddr + 2 * matsize); + std::vector sensor_rgb; + sensor_rgb.push_back(ori_img_B); + sensor_rgb.push_back(ori_img_G); + sensor_rgb.push_back(ori_img_R); + cv::merge(sensor_rgb, ori_img); + + cropped_img = Utils::crop(ori_img, box_info); + + { + ScopedTiming st("ocr time", atoi(argv[10])); + ocr_det_size = ocr_process(ocrbox, ocrreco, cropped_img, osd_frame, x_min,y_min); + } + } + + int x = 1.0 * x_min/ SENSOR_WIDTH * osd_height; + int y = 1.0 * y_min / SENSOR_HEIGHT * osd_width; + int w = 1.0 * (x_max-x_min) / SENSOR_WIDTH * osd_height; + int h = 1.0 * (y_max-y_min) / SENSOR_HEIGHT * osd_width; + + cv::rectangle(osd_frame, cv::Rect(x, y , w, h), cv::Scalar( 255,0, 255, 255), 2, 2, 0); + } + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + for (auto r: results) { - auto tb = frameTrackingResult[i]; - int rect_x = tb.box.x / SENSOR_WIDTH * osd_width; - int rect_y = tb.box.y / SENSOR_HEIGHT * osd_height; - int rect_w = (float)tb.box.width / SENSOR_WIDTH * osd_width; - int rect_h = (float)tb.box.height / SENSOR_HEIGHT * osd_height; - cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w + 20, rect_h + 20), cv::Scalar( 255,255, 0, 255), 2, 2, 0); - std::string num = std::to_string(tb.id); - - int length = std::max(tb.box.width,tb.box.height)/2; - int cx = tb.box.x+tb.box.width/2; - int cy = tb.box.y+tb.box.height/2; - int ratio_num = 1.26*length; - - int x1_1 = std::max(0,cx-ratio_num); - int y1_1 = std::max(0,cy-ratio_num); - int x2_1 = std::min(SENSOR_WIDTH-1, cx+ratio_num); - int y2_1 = std::min(SENSOR_HEIGHT-1, cy+ratio_num); - int w_1 = x2_1 - x1_1 + 1; - int h_1 = y2_1 - y1_1 + 1; + std::string text = hd.labels_[r.label] + ":" + std::to_string(round(r.score * 100) / 100.0); + + int w = r.x2 - r.x1 + 1; + int h = r.y2 - r.y1 + 1; - struct Bbox bbox = {x:x1_1,y:y1_1,w:w_1,h:h_1}; - hk.pre_process(bbox); + int rect_x = r.x1/ SENSOR_WIDTH * osd_height; + int rect_y = r.y1 / SENSOR_HEIGHT * osd_width; + int rect_w = (float)w / SENSOR_WIDTH * osd_height; + int rect_h = (float)h / SENSOR_HEIGHT * osd_width; + cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w, rect_h), cv::Scalar( 255,255, 255, 255), 2, 2, 0); + } - hk.inference(); + if (frameTrackingResult.size()>0 && fi>=5) + { + cv::Point2f left_top; + int index1 = 1; + + for(int i=0;i< frameTrackingResult.size();i++) + { + auto tb = frameTrackingResult[i]; + int rect_x = tb.box.x / SENSOR_WIDTH * osd_height; + int rect_y = tb.box.y / SENSOR_HEIGHT * osd_width; + int rect_w = (float)tb.box.width / SENSOR_WIDTH * osd_height; + int rect_h = (float)tb.box.height / SENSOR_HEIGHT * osd_width; + cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w + 20, rect_h + 20), cv::Scalar( 255,255, 0, 255), 2, 2, 0); + std::string num = std::to_string(tb.id); + + int length = std::max(tb.box.width,tb.box.height)/2; + int cx = tb.box.x+tb.box.width/2; + int cy = tb.box.y+tb.box.height/2; + int ratio_num = 1.26*length; + + int x1_1 = std::max(0,cx-ratio_num); + int y1_1 = std::max(0,cy-ratio_num); + int x2_1 = std::min(SENSOR_WIDTH-1, cx+ratio_num); + int y2_1 = std::min(SENSOR_HEIGHT-1, cy+ratio_num); + int w_1 = x2_1 - x1_1 + 1; + int h_1 = y2_1 - y1_1 + 1; + + struct Bbox bbox = {x:x1_1,y:y1_1,w:w_1,h:h_1}; + hk.pre_process(bbox); + + hk.inference(); + + float *pred = hk.get_out()[0]; + int draw_x,draw_y; + + float pred_x = std::max(std::min(pred[(index1+1)*4*2], 1.0f), 0.0f); + float pred_y = std::max(std::min(pred[(index1+1)*4*2+1], 1.0f), 0.0f); + + left_top.x = pred_x * w_1 + x1_1; + left_top.y = pred_y * h_1 + y1_1; + draw_x = left_top.x / SENSOR_WIDTH * osd_height; + draw_y = left_top.y / SENSOR_HEIGHT * osd_width; + + cv::circle(osd_frame, cv::Point(draw_x, draw_y), 6, cv::Scalar(255, 0,0,0), 3); + cv::circle(osd_frame, cv::Point(draw_x, draw_y), 5, cv::Scalar(255, 0,0,0), 3); - float *pred = hk.get_out()[0]; - int draw_x,draw_y; - float pred_x = std::max(std::min(pred[(index1+1)*4*2], 1.0f), 0.0f); - float pred_y = std::max(std::min(pred[(index1+1)*4*2+1], 1.0f), 0.0f); + ScopedTiming st("osd draw", atoi(argv[10])); + hk.draw_keypoints(osd_frame, num, bbox, false); - left_top.x = pred_x * w_1 + x1_1; - left_top.y = pred_y * h_1 + y1_1; - draw_x = left_top.x / SENSOR_WIDTH * osd_width; - draw_y = left_top.y / SENSOR_HEIGHT * osd_height; + } - cv::circle(osd_frame, cv::Point(draw_x, draw_y), 6, cv::Scalar(255, 0,0,0), 3); - cv::circle(osd_frame, cv::Point(draw_x, draw_y), 5, cv::Scalar(255, 0,0,0), 3); + int x_min = std::max(static_cast(left_top.x-500), 0); + int x_max = std::min(static_cast(left_top.x), SENSOR_WIDTH); + int y_min = std::max(static_cast(left_top.y-300), 0); + int y_max = std::min(static_cast(left_top.y), SENSOR_HEIGHT); + Bbox box_info = {x_min,y_min, (x_max-x_min),(y_max-y_min)}; + if ((x_max-x_min>32) && (y_max-y_min>32)) + { + { + int matsize = SENSOR_WIDTH * SENSOR_HEIGHT; + + cv::Mat ori_img; + cv::Mat ori_img_R = cv::Mat(SENSOR_HEIGHT, SENSOR_WIDTH, CV_8UC1, vaddr); + cv::Mat ori_img_G = cv::Mat(SENSOR_HEIGHT, SENSOR_WIDTH, CV_8UC1, vaddr + 1 * matsize); + cv::Mat ori_img_B = cv::Mat(SENSOR_HEIGHT, SENSOR_WIDTH, CV_8UC1, vaddr + 2 * matsize); + std::vector sensor_rgb; + sensor_rgb.push_back(ori_img_B); + sensor_rgb.push_back(ori_img_G); + sensor_rgb.push_back(ori_img_R); + cv::merge(sensor_rgb, ori_img); + + cropped_img = Utils::crop(ori_img, box_info); + + { + ScopedTiming st("ocr time", atoi(argv[10])); + ocr_det_size = ocr_process(ocrbox, ocrreco, cropped_img, osd_frame, x_min,y_min); + } + } - ScopedTiming st("osd draw", atoi(argv[10])); - hk.draw_keypoints(osd_frame, num, bbox, false); + int x = 1.0 * x_min/ SENSOR_WIDTH * osd_height; + int y = 1.0 * y_min / SENSOR_HEIGHT * osd_width; + int w = 1.0 * (x_max-x_min) / SENSOR_WIDTH * osd_height; + int h = 1.0 * (y_max-y_min) / SENSOR_HEIGHT * osd_width; + cv::rectangle(osd_frame, cv::Rect(x, y , w, h), cv::Scalar( 255,0, 255, 255), 2, 2, 0); + } } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #else + { + for (auto r: results) + { + std::string text = hd.labels_[r.label] + ":" + std::to_string(round(r.score * 100) / 100.0); - int x_min = std::max(static_cast(left_top.x-500), 0); - int x_max = std::min(static_cast(left_top.x), SENSOR_WIDTH); - int y_min = std::max(static_cast(left_top.y-300), 0); - int y_max = std::min(static_cast(left_top.y), SENSOR_HEIGHT); - Bbox box_info = {x_min,y_min, (x_max-x_min),(y_max-y_min)}; + int w = r.x2 - r.x1 + 1; + int h = r.y2 - r.y1 + 1; + + int rect_x = r.x1/ SENSOR_WIDTH * osd_width; + int rect_y = r.y1 / SENSOR_HEIGHT * osd_height; + int rect_w = (float)w / SENSOR_WIDTH * osd_width; + int rect_h = (float)h / SENSOR_HEIGHT * osd_height; + cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w, rect_h), cv::Scalar( 255,255, 255, 255), 2, 2, 0); + } - if ((x_max-x_min>32) && (y_max-y_min>32)) + if (frameTrackingResult.size()>0 && fi>=5) { + cv::Point2f left_top; + int index1 = 1; + + for(int i=0;i< frameTrackingResult.size();i++) { - int matsize = SENSOR_WIDTH * SENSOR_HEIGHT; + auto tb = frameTrackingResult[i]; + int rect_x = tb.box.x / SENSOR_WIDTH * osd_width; + int rect_y = tb.box.y / SENSOR_HEIGHT * osd_height; + int rect_w = (float)tb.box.width / SENSOR_WIDTH * osd_width; + int rect_h = (float)tb.box.height / SENSOR_HEIGHT * osd_height; + cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w + 20, rect_h + 20), cv::Scalar( 255,255, 0, 255), 2, 2, 0); + std::string num = std::to_string(tb.id); + + int length = std::max(tb.box.width,tb.box.height)/2; + int cx = tb.box.x+tb.box.width/2; + int cy = tb.box.y+tb.box.height/2; + int ratio_num = 1.26*length; + + int x1_1 = std::max(0,cx-ratio_num); + int y1_1 = std::max(0,cy-ratio_num); + int x2_1 = std::min(SENSOR_WIDTH-1, cx+ratio_num); + int y2_1 = std::min(SENSOR_HEIGHT-1, cy+ratio_num); + int w_1 = x2_1 - x1_1 + 1; + int h_1 = y2_1 - y1_1 + 1; - cv::Mat ori_img; - cv::Mat ori_img_R = cv::Mat(SENSOR_HEIGHT, SENSOR_WIDTH, CV_8UC1, vaddr); - cv::Mat ori_img_G = cv::Mat(SENSOR_HEIGHT, SENSOR_WIDTH, CV_8UC1, vaddr + 1 * matsize); - cv::Mat ori_img_B = cv::Mat(SENSOR_HEIGHT, SENSOR_WIDTH, CV_8UC1, vaddr + 2 * matsize); - std::vector sensor_rgb; - sensor_rgb.push_back(ori_img_B); - sensor_rgb.push_back(ori_img_G); - sensor_rgb.push_back(ori_img_R); - cv::merge(sensor_rgb, ori_img); - - cropped_img = Utils::crop(ori_img, box_info); + struct Bbox bbox = {x:x1_1,y:y1_1,w:w_1,h:h_1}; + hk.pre_process(bbox); + + hk.inference(); + + float *pred = hk.get_out()[0]; + int draw_x,draw_y; + + float pred_x = std::max(std::min(pred[(index1+1)*4*2], 1.0f), 0.0f); + float pred_y = std::max(std::min(pred[(index1+1)*4*2+1], 1.0f), 0.0f); + + left_top.x = pred_x * w_1 + x1_1; + left_top.y = pred_y * h_1 + y1_1; + draw_x = left_top.x / SENSOR_WIDTH * osd_width; + draw_y = left_top.y / SENSOR_HEIGHT * osd_height; + + cv::circle(osd_frame, cv::Point(draw_x, draw_y), 6, cv::Scalar(255, 0,0,0), 3); + cv::circle(osd_frame, cv::Point(draw_x, draw_y), 5, cv::Scalar(255, 0,0,0), 3); + + + ScopedTiming st("osd draw", atoi(argv[10])); + hk.draw_keypoints(osd_frame, num, bbox, false); + } + + int x_min = std::max(static_cast(left_top.x-500), 0); + int x_max = std::min(static_cast(left_top.x), SENSOR_WIDTH); + int y_min = std::max(static_cast(left_top.y-300), 0); + int y_max = std::min(static_cast(left_top.y), SENSOR_HEIGHT); + Bbox box_info = {x_min,y_min, (x_max-x_min),(y_max-y_min)}; + + if ((x_max-x_min>32) && (y_max-y_min>32)) + { { - ScopedTiming st("ocr time", atoi(argv[10])); - ocr_det_size = ocr_process(ocrbox, ocrreco, cropped_img, osd_frame, x_min,y_min); + int matsize = SENSOR_WIDTH * SENSOR_HEIGHT; + + cv::Mat ori_img; + cv::Mat ori_img_R = cv::Mat(SENSOR_HEIGHT, SENSOR_WIDTH, CV_8UC1, vaddr); + cv::Mat ori_img_G = cv::Mat(SENSOR_HEIGHT, SENSOR_WIDTH, CV_8UC1, vaddr + 1 * matsize); + cv::Mat ori_img_B = cv::Mat(SENSOR_HEIGHT, SENSOR_WIDTH, CV_8UC1, vaddr + 2 * matsize); + std::vector sensor_rgb; + sensor_rgb.push_back(ori_img_B); + sensor_rgb.push_back(ori_img_G); + sensor_rgb.push_back(ori_img_R); + cv::merge(sensor_rgb, ori_img); + + cropped_img = Utils::crop(ori_img, box_info); + + { + ScopedTiming st("ocr time", atoi(argv[10])); + ocr_det_size = ocr_process(ocrbox, ocrreco, cropped_img, osd_frame, x_min,y_min); + } } - } - int x = 1.0 * x_min/ SENSOR_WIDTH * osd_width; - int y = 1.0 * y_min / SENSOR_HEIGHT * osd_height; - int w = 1.0 * (x_max-x_min) / SENSOR_WIDTH * osd_width; - int h = 1.0 * (y_max-y_min) / SENSOR_HEIGHT * osd_height; + int x = 1.0 * x_min/ SENSOR_WIDTH * osd_width; + int y = 1.0 * y_min / SENSOR_HEIGHT * osd_height; + int w = 1.0 * (x_max-x_min) / SENSOR_WIDTH * osd_width; + int h = 1.0 * (y_max-y_min) / SENSOR_HEIGHT * osd_height; - cv::rectangle(osd_frame, cv::Rect(x, y , w, h), cv::Scalar( 255,0, 255, 255), 2, 2, 0); + cv::rectangle(osd_frame, cv::Rect(x, y , w, h), cv::Scalar( 255,0, 255, 255), 2, 2, 0); + } } - } + } + #endif + { ScopedTiming st("osd copy", atoi(argv[10])); memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); diff --git a/src/reference/ai_poc/sq_handkp_ocr/vi_vo.h b/src/reference/ai_poc/sq_handkp_ocr/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/sq_handkp_ocr/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/sq_handreco/main.cc b/src/reference/ai_poc/sq_handreco/main.cc index cb6029a3d..079063fbb 100644 --- a/src/reference/ai_poc/sq_handreco/main.cc +++ b/src/reference/ai_poc/sq_handreco/main.cc @@ -44,7 +44,7 @@ void print_usage(const char *name) << " obj_thresh 手掌检测阈值\n" << " nms_thresh 手掌检测非极大值抑制阈值\n" << " kmodel_reco 手势识别kmodel路径\n" - << " debug_mode 是否需要调试，0、1、2分别表示不调试、简单调试、详细调试\n" + << " debug_mode 是否需要调试, 0、1、2分别表示不调试、简单调试、详细调试\n" << "\n" << endl; } @@ -108,17 +108,24 @@ void video_proc(char *argv[]) hd.post_process(results); cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + #if defined(CONFIG_BOARD_K230D_CANMV) + { + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + } + #else + { + } + #endif + for (auto r: results) { int w = r.x2 - r.x1 + 1; int h = r.y2 - r.y1 + 1; - int rect_x = (float)r.x1/ SENSOR_WIDTH * osd_width; - int rect_y = (float)r.y1/ SENSOR_HEIGHT * osd_height; - int rect_w = (float)w / SENSOR_WIDTH * osd_width; - int rect_h = (float)h / SENSOR_HEIGHT * osd_height; - cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w, rect_h), cv::Scalar( 255,255, 255, 255), 2, 2, 0); - int length = std::max(w,h)/2; int cx = (r.x1+r.x2)/2; int cy = (r.y1+r.y2)/2; @@ -133,13 +140,55 @@ void video_proc(char *argv[]) struct Bbox bbox = {x:x1_1,y:y1_1,w:w_1,h:h_1}; hr.pre_process(bbox); - hr.inference(); - std::string text1 = hr.post_process(); - cv::putText(osd_frame, text1, cv::Point(rect_x,rect_y-20),cv::FONT_HERSHEY_COMPLEX, 1, cv::Scalar(255, 255, 195, 0), 2); + #if defined(CONFIG_BOARD_K230D_CANMV) + { + int rect_x = (float)r.x1/ SENSOR_WIDTH * osd_height; + int rect_y = (float)r.y1/ SENSOR_HEIGHT * osd_width; + int rect_w = (float)w / SENSOR_WIDTH * osd_height; + int rect_h = (float)h / SENSOR_HEIGHT * osd_width; + + cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w, rect_h), cv::Scalar( 255,255, 255, 255), 2, 2, 0); + cv::putText(osd_frame, text1, cv::Point(rect_x,rect_y-20),cv::FONT_HERSHEY_COMPLEX, 1, cv::Scalar(255, 255, 195, 0), 2); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + int rect_x = (float)r.x1/ SENSOR_WIDTH * osd_height; + int rect_y = (float)r.y1/ SENSOR_HEIGHT * osd_width; + int rect_w = (float)w / SENSOR_WIDTH * osd_height; + int rect_h = (float)h / SENSOR_HEIGHT * osd_width; + + cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w, rect_h), cv::Scalar( 255,255, 255, 255), 2, 2, 0); + cv::putText(osd_frame, text1, cv::Point(rect_x,rect_y-20),cv::FONT_HERSHEY_COMPLEX, 1, cv::Scalar(255, 255, 195, 0), 2); + } + #else + { + int rect_x = (float)r.x1/ SENSOR_WIDTH * osd_width; + int rect_y = (float)r.y1/ SENSOR_HEIGHT * osd_height; + int rect_w = (float)w / SENSOR_WIDTH * osd_width; + int rect_h = (float)h / SENSOR_HEIGHT * osd_height; + + cv::rectangle(osd_frame, cv::Rect(rect_x, rect_y , rect_w, rect_h), cv::Scalar( 255,255, 255, 255), 2, 2, 0); + cv::putText(osd_frame, text1, cv::Point(rect_x,rect_y-20),cv::FONT_HERSHEY_COMPLEX, 1, cv::Scalar(255, 255, 195, 0), 2); + } + #endif + } + + #if defined(CONFIG_BOARD_K230D_CANMV) + { + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #else + { } + #endif + { ScopedTiming st("osd copy", atoi(argv[6])); memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); diff --git a/src/reference/ai_poc/sq_handreco/vi_vo.h b/src/reference/ai_poc/sq_handreco/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/sq_handreco/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/traffic_light_detect/main.cc b/src/reference/ai_poc/traffic_light_detect/main.cc index 4e7599dbd..7f91493e8 100644 --- a/src/reference/ai_poc/traffic_light_detect/main.cc +++ b/src/reference/ai_poc/traffic_light_detect/main.cc @@ -51,7 +51,7 @@ void print_usage(const char *name) << endl; } -void video_proc(char *argv[]) +void video_proc_v1(char *argv[]) { vivcap_start(); @@ -175,6 +175,382 @@ void video_proc(char *argv[]) } +void video_proc_v2(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + traffic_lightDetect td(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + + td.pre_process(); + td.inference(); + td.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + + std::string text; + cv::Point origin; + std::vector scalars= { + cv::Scalar(255,255, 0, 0), // "Red" + cv::Scalar(255,0,255, 0), // "Green" + cv::Scalar(255,255,255,0), // "Yellow" + cv::Scalar(255,255,0, 0), + cv::Scalar(255, 255,0, 0), + cv::Scalar(255, 255,0,0) + }; + + for (auto r : results) + { + ScopedTiming st("draw boxes", atoi(argv[5])); + text = td.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); + std::cout << "text = " << text << std::endl; + + int x1 = r.x1 / SENSOR_WIDTH * osd_width; + int y1 = r.y1 / SENSOR_HEIGHT * osd_height; + + origin.x = x1; + origin.y = y1-20; + + int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_width; + int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_height; + + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), scalars[r.label], 6, 2, 0); // ARGB + cv::putText(osd_frame, text, origin, cv::FONT_HERSHEY_COMPLEX, 2, scalars[r.label+3], 1, 8, 0); + + + } + + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_k230d(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + traffic_lightDetect td(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + + td.pre_process(); + td.inference(); + td.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + std::string text; + cv::Point origin; + std::vector scalars= { + cv::Scalar(255,255, 0, 0), // "Red" + cv::Scalar(255,0,255, 0), // "Green" + cv::Scalar(255,255,255,0), // "Yellow" + cv::Scalar(255,255,0, 0), + cv::Scalar(255, 255,0, 0), + cv::Scalar(255, 255,0,0) + }; + + for (auto r : results) + { + ScopedTiming st("draw boxes", atoi(argv[5])); + text = td.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); + std::cout << "text = " << text << std::endl; + + int x1 = r.x1 / SENSOR_WIDTH * osd_frame.cols; + int y1 = r.y1 / SENSOR_HEIGHT * osd_frame.rows; + + origin.x = x1; + origin.y = y1-20; + + int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_frame.cols; + int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_frame.rows; + + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), scalars[r.label], 6, 2, 0); // ARGB + cv::putText(osd_frame, text, origin, cv::FONT_HERSHEY_COMPLEX, 2, scalars[r.label+3], 1, 8, 0); + + + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_01(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + traffic_lightDetect td(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + + td.pre_process(); + td.inference(); + td.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + std::string text; + cv::Point origin; + std::vector scalars= { + cv::Scalar(255,255, 0, 0), // "Red" + cv::Scalar(255,0,255, 0), // "Green" + cv::Scalar(255,255,255,0), // "Yellow" + cv::Scalar(255,255,0, 0), + cv::Scalar(255, 255,0, 0), + cv::Scalar(255, 255,0,0) + }; + + for (auto r : results) + { + ScopedTiming st("draw boxes", atoi(argv[5])); + text = td.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); + std::cout << "text = " << text << std::endl; + + int x1 = r.x1 / SENSOR_WIDTH * osd_frame.cols; + int y1 = r.y1 / SENSOR_HEIGHT * osd_frame.rows; + + origin.x = x1; + origin.y = y1-20; + + int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_frame.cols; + int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_frame.rows; + + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), scalars[r.label], 6, 2, 0); // ARGB + cv::putText(osd_frame, text, origin, cv::FONT_HERSHEY_COMPLEX, 2, scalars[r.label+3], 1, 8, 0); + + + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + int main(int argc, char *argv[]) { @@ -187,14 +563,62 @@ int main(int argc, char *argv[]) if (strcmp(argv[4], "None") == 0) { - std::thread thread_isp(video_proc, argv); - while (getchar() != 'q') + #if defined(CONFIG_BOARD_K230_CANMV) { - usleep(10000); + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); } + #elif defined(CONFIG_BOARD_K230_CANMV_V2) + { + std::thread thread_isp(video_proc_v2, argv); + while (getchar() != 'q') + { + usleep(10000); + } - isp_stop = true; - thread_isp.join(); + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230D_CANMV) + { + std::thread thread_isp(video_proc_k230d, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + std::thread thread_isp(video_proc_01, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #else + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #endif } else { diff --git a/src/reference/ai_poc/traffic_light_detect/vi_vo.h b/src/reference/ai_poc/traffic_light_detect/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/traffic_light_detect/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/vehicle_attr/main.cc b/src/reference/ai_poc/vehicle_attr/main.cc index 06eed3000..9fc2f7429 100644 --- a/src/reference/ai_poc/vehicle_attr/main.cc +++ b/src/reference/ai_poc/vehicle_attr/main.cc @@ -56,7 +56,7 @@ void print_usage(const char *name) << endl; } -void video_proc(char *argv[]) +void video_proc_v1(char *argv[]) { vivcap_start(); @@ -190,6 +190,412 @@ void video_proc(char *argv[]) } +void video_proc_v2(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + objectDetect od(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[8])); + float color_thresh = atof(argv[6]); + float type_thresh = atof(argv[7]); + Pulc pul(argv[5], {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH},color_thresh, type_thresh, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[8])); + vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + od.pre_process(); + od.inference(); + od.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + std::string text; + cv::Point origin; + Bbox crop_box; + std::string attr_results; + float fontScale=2; + int width = 50; + + + for (auto r : results) + { + ScopedTiming st("draw boxes", atoi(argv[8])); + text = od.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); + + int x1 = r.x1 / SENSOR_WIDTH * osd_width; + int y1 = r.y1 / SENSOR_HEIGHT * osd_height; + + int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_width; + int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_height; + + origin.x = x1 + w; + origin.y = y1 + 20; + + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), cv::Scalar(255, 255,0, 0), 2, 2, 0); // ARGB + + crop_box = { r.x1,r.y1,(r.x2-r.x1),(r.y2-r.y1) }; + pul.pre_process( crop_box ); + pul.inference(); + attr_results = pul.post_process(); + + std::string color = pul.GetColor(); + origin.y += 2*width; + cv::putText(osd_frame, color, origin, cv::FONT_HERSHEY_COMPLEX, fontScale, cv::Scalar( 255,0, 255, 255), 1, 8, 0); + + std::string type = pul.GetType(); + origin.y += width; + cv::putText(osd_frame, type, origin, cv::FONT_HERSHEY_COMPLEX, fontScale, cv::Scalar( 255,0, 255, 255), 1, 8, 0); + + attr_results = color + "\n" + type; + + + + } + + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_k230d(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + objectDetect od(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[8])); + float color_thresh = atof(argv[6]); + float type_thresh = atof(argv[7]); + Pulc pul(argv[5], {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH},color_thresh, type_thresh, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[8])); + vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + od.pre_process(); + od.inference(); + od.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + std::string text; + cv::Point origin; + Bbox crop_box; + std::string attr_results; + float fontScale=2; + int width = 50; + + + for (auto r : results) + { + ScopedTiming st("draw boxes", atoi(argv[8])); + text = od.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); + + int x1 = r.x1 / SENSOR_WIDTH * osd_frame.cols; + int y1 = r.y1 / SENSOR_HEIGHT * osd_frame.rows; + + int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_frame.cols; + int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_frame.rows; + + origin.x = x1 + w; + origin.y = y1 + 20; + + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), cv::Scalar(255, 255,0, 0), 2, 2, 0); // ARGB + + crop_box = { r.x1,r.y1,(r.x2-r.x1),(r.y2-r.y1) }; + pul.pre_process( crop_box ); + pul.inference(); + attr_results = pul.post_process(); + + std::string color = pul.GetColor(); + origin.y += 2*width; + cv::putText(osd_frame, color, origin, cv::FONT_HERSHEY_COMPLEX, fontScale, cv::Scalar( 255,0, 255, 255), 1, 8, 0); + + std::string type = pul.GetType(); + origin.y += width; + cv::putText(osd_frame, type, origin, cv::FONT_HERSHEY_COMPLEX, fontScale, cv::Scalar( 255,0, 255, 255), 1, 8, 0); + + attr_results = color + "\n" + type; + + + + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_01(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + objectDetect od(argv[1], atof(argv[2]),atof(argv[3]), {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[8])); + float color_thresh = atof(argv[6]); + float type_thresh = atof(argv[7]); + Pulc pul(argv[5], {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH},color_thresh, type_thresh, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[8])); + vector results; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[5])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + od.pre_process(); + od.inference(); + od.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, results); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + std::string text; + cv::Point origin; + Bbox crop_box; + std::string attr_results; + float fontScale=2; + int width = 50; + + + for (auto r : results) + { + ScopedTiming st("draw boxes", atoi(argv[8])); + text = od.labels[r.label] + ":" + std::to_string(round(r.score * 100) / 100).substr(0,4); + + int x1 = r.x1 / SENSOR_WIDTH * osd_frame.cols; + int y1 = r.y1 / SENSOR_HEIGHT * osd_frame.rows; + + int w = (r.x2-r.x1) / SENSOR_WIDTH * osd_frame.cols; + int h = (r.y2-r.y1) / SENSOR_HEIGHT * osd_frame.rows; + + origin.x = x1 + w; + origin.y = y1 + 20; + + cv::rectangle(osd_frame, cv::Rect( x1,y1,w,h ), cv::Scalar(255, 255,0, 0), 2, 2, 0); // ARGB + + crop_box = { r.x1,r.y1,(r.x2-r.x1),(r.y2-r.y1) }; + pul.pre_process( crop_box ); + pul.inference(); + attr_results = pul.post_process(); + + std::string color = pul.GetColor(); + origin.y += 2*width; + cv::putText(osd_frame, color, origin, cv::FONT_HERSHEY_COMPLEX, fontScale, cv::Scalar( 255,0, 255, 255), 1, 8, 0); + + std::string type = pul.GetType(); + origin.y += width; + cv::putText(osd_frame, type, origin, cv::FONT_HERSHEY_COMPLEX, fontScale, cv::Scalar( 255,0, 255, 255), 1, 8, 0); + + attr_results = color + "\n" + type; + + + + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + int main(int argc, char *argv[]) { @@ -202,14 +608,62 @@ int main(int argc, char *argv[]) if (strcmp(argv[4], "None") == 0) { - std::thread thread_isp(video_proc, argv); - while (getchar() != 'q') + #if defined(CONFIG_BOARD_K230_CANMV) { - usleep(10000); + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); } + #elif defined(CONFIG_BOARD_K230_CANMV_V2) + { + std::thread thread_isp(video_proc_v2, argv); + while (getchar() != 'q') + { + usleep(10000); + } - isp_stop = true; - thread_isp.join(); + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230D_CANMV) + { + std::thread thread_isp(video_proc_k230d, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + std::thread thread_isp(video_proc_01, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #else + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #endif } else { diff --git a/src/reference/ai_poc/vehicle_attr/vi_vo.h b/src/reference/ai_poc/vehicle_attr/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/vehicle_attr/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/version b/src/reference/ai_poc/version index 1ce69a78a..1d81d23b2 100644 --- a/src/reference/ai_poc/version +++ b/src/reference/ai_poc/version @@ -1 +1 @@ -v1.5 +v1.6 diff --git a/src/reference/ai_poc/anomaly_det/vi_vo.h b/src/reference/ai_poc/vi_vo/vi_vo.h similarity index 79% rename from src/reference/ai_poc/anomaly_det/vi_vo.h rename to src/reference/ai_poc/vi_vo/vi_vo.h index 0a11a4d31..fc07b5b21 100644 --- a/src/reference/ai_poc/anomaly_det/vi_vo.h +++ b/src/reference/ai_poc/vi_vo/vi_vo.h @@ -57,16 +57,54 @@ #include "k_autoconf_comm.h" -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) +#if defined(CONFIG_BOARD_K230_CANMV) +#define SENSOR_CHANNEL (3) +#define SENSOR_HEIGHT (720) +#define SENSOR_WIDTH (1280) +#define ISP_CHN0_WIDTH (1920) +#define ISP_CHN0_HEIGHT (1080) +#define ISP_INPUT_WIDTH (1920) +#define ISP_INPUT_HEIGHT (1080) +#define vicap_install_osd (1) +#define osd_id K_VO_OSD3 +#define osd_width (1920) +#define osd_height (1080) +#elif defined(CONFIG_BOARD_K230_CANMV_V2) +#define SENSOR_CHANNEL (3) +#define SENSOR_HEIGHT (720) +#define SENSOR_WIDTH (1280) +#define ISP_CHN0_WIDTH (1920) +#define ISP_CHN0_HEIGHT (1080) +#define ISP_INPUT_WIDTH (1920) +#define ISP_INPUT_HEIGHT (1080) #define vicap_install_osd (1) #define osd_id K_VO_OSD3 #define osd_width (1920) #define osd_height (1080) +#elif defined(CONFIG_BOARD_K230D_CANMV) +#define SENSOR_CHANNEL (3) +#define SENSOR_HEIGHT (720 / 2) +#define SENSOR_WIDTH (1280 / 2) +#define ISP_CHN0_WIDTH (800) +#define ISP_CHN0_HEIGHT (480) +#define ISP_INPUT_WIDTH (1920) +#define ISP_INPUT_HEIGHT (1080) +#define vicap_install_osd (1) +#define osd_id K_VO_OSD3 +#define osd_width (480) +#define osd_height (800) +#elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) +#define SENSOR_CHANNEL (3) +#define SENSOR_HEIGHT (720) +#define SENSOR_WIDTH (1280) +#define ISP_CHN0_WIDTH (800) +#define ISP_CHN0_HEIGHT (480) +#define ISP_INPUT_WIDTH (1920) +#define ISP_INPUT_HEIGHT (1080) +#define vicap_install_osd (1) +#define osd_id K_VO_OSD3 +#define osd_width (480) +#define osd_height (800) #else #define SENSOR_CHANNEL (3) // isp通道数 #define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 @@ -286,15 +324,20 @@ static k_s32 sample_connector_init(void) { k_u32 ret = 0; k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; +#if defined(CONFIG_BOARD_K230_CANMV) + k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS; +#elif defined(CONFIG_BOARD_K230_CANMV_V2) + k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS; +#elif defined(CONFIG_BOARD_K230D_CANMV) + k_connector_type connector_type = ST7701_V1_MIPI_2LAN_480X800_30FPS; +#elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + k_connector_type connector_type = ST7701_V1_MIPI_2LAN_480X800_30FPS; #else k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; #endif - k_connector_info connector_info; + k_connector_info connector_info; memset(&connector_info, 0, sizeof(k_connector_info)); - //connector get sensor info ret = kd_mpi_get_connector_info(connector_type, &connector_info); if (ret) { @@ -326,11 +369,24 @@ static k_s32 vo_layer_vdss_bind_vo_config(void) sample_connector_init(); + #if defined(CONFIG_BOARD_K230D_CANMV) + info.act_size.width = ISP_CHN0_HEIGHT;//1080;//640;//1080; + info.act_size.height = ISP_CHN0_WIDTH;//1920;//480;//1920; + info.format = PIXEL_FORMAT_YVU_PLANAR_420; + info.func = K_ROTATION_90; + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + info.act_size.width = ISP_CHN0_HEIGHT;//1080;//640;//1080; + info.act_size.height = ISP_CHN0_WIDTH;//1920;//480;//1920; + info.format = PIXEL_FORMAT_YVU_PLANAR_420; + info.func = K_ROTATION_90; + #else // config lyaer info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; info.format = PIXEL_FORMAT_YVU_PLANAR_420; info.func = 0;//K_ROTATION_180;////K_ROTATION_90; + #endif + info.global_alptha = 0xff; info.offset.x = 0;//(1080-w)/2, info.offset.y = 0;//(1920-h)/2; @@ -376,26 +432,40 @@ int vivcap_start() printf("sample_vicap ...\n"); -#if defined(CONFIG_BOARD_K230_CANMV) + #if defined(CONFIG_BOARD_K230_CANMV) sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) + #elif defined(CONFIG_BOARD_K230_CANMV_V2) sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; + #elif defined(CONFIG_BOARD_K230D_CANMV) + sensor_type = OV_OV5647_MIPI_1920X1080_30FPS_10BIT_LINEAR; + #else sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; + #endif + vicap_dev = VICAP_DEV_ID_0; memset(&config, 0, sizeof(config)); config.max_pool_cnt = 64; + #if defined(CONFIG_BOARD_K230D_CANMV) + //VB for YUV420SP output + config.comm_pool[0].blk_cnt = 4; + config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; + config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); + //VB for RGB888 output + config.comm_pool[1].blk_cnt = 5; + config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; + config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); + #else //VB for YUV420SP output config.comm_pool[0].blk_cnt = 5; config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - //VB for RGB888 output config.comm_pool[1].blk_cnt = 5; config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); + #endif ret = kd_mpi_vb_set_config(&config); if (ret) { @@ -425,12 +495,21 @@ int vivcap_start() if(vicap_install_osd == 1) { + #if defined(CONFIG_BOARD_K230D_CANMV) + memset(&pool_config, 0, sizeof(pool_config)); + pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); + pool_config.blk_cnt = 2; + pool_config.mode = VB_REMAP_MODE_NOCACHE; + pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 + g_pool_id = pool_id; + #else memset(&pool_config, 0, sizeof(pool_config)); pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); pool_config.blk_cnt = 4; pool_config.mode = VB_REMAP_MODE_NOCACHE; pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 g_pool_id = pool_id; + #endif printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); } @@ -445,13 +524,13 @@ int vivcap_start() memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); dev_attr.acq_win.h_start = 0; dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else + #if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) || defined(CONFIG_BOARD_K230D_CANMV) || defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + dev_attr.acq_win.width = ISP_INPUT_WIDTH; + dev_attr.acq_win.height = ISP_INPUT_HEIGHT; + #else dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif + #endif dev_attr.mode = VICAP_WORK_ONLINE_MODE; dev_attr.pipe_ctrl.data = 0xFFFFFFFF; @@ -477,15 +556,15 @@ int vivcap_start() chn_attr.out_win.height = ISP_CHN0_HEIGHT; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) + #if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) || defined(CONFIG_BOARD_K230D_CANMV) || defined(CONFIG_BOARD_K230_CANMV_01STUDIO) chn_attr.crop_win = dev_attr.acq_win; -#else + #else // chn_attr.crop_win = dev_attr.acq_win; chn_attr.crop_win.h_start = 768; chn_attr.crop_win.v_start = 16; chn_attr.crop_win.width = ISP_CHN0_WIDTH; chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif + #endif chn_attr.scale_win = chn_attr.out_win; chn_attr.crop_enable = K_FALSE; @@ -523,14 +602,14 @@ int vivcap_start() chn_attr.out_win.height = SENSOR_HEIGHT; // chn_attr.crop_win = dev_attr.acq_win; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) + #if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) || defined(CONFIG_BOARD_K230D_CANMV) || defined(CONFIG_BOARD_K230_CANMV_01STUDIO) chn_attr.crop_win = dev_attr.acq_win; -#else + #else chn_attr.crop_win.h_start = 768; chn_attr.crop_win.v_start = 16; chn_attr.crop_win.width = ISP_CHN0_WIDTH; chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif + #endif chn_attr.scale_win = chn_attr.out_win; chn_attr.crop_enable = K_FALSE; @@ -548,6 +627,13 @@ int vivcap_start() return ret; } + // set to header file database parse mode + ret = kd_mpi_vicap_set_database_parse_mode(vicap_dev, VICAP_DATABASE_PARSE_XML_JSON); + if (ret) { + printf("sample_vicap, kd_mpi_vicap_set_database_parse_mode failed.\n"); + return ret; + } + printf("sample_vicap ...kd_mpi_vicap_init\n"); ret = kd_mpi_vicap_init(vicap_dev); if (ret) { diff --git a/src/reference/ai_poc/virtual_keyboard/key.cc b/src/reference/ai_poc/virtual_keyboard/key.cc index a869bf972..3479ad86b 100644 --- a/src/reference/ai_poc/virtual_keyboard/key.cc +++ b/src/reference/ai_poc/virtual_keyboard/key.cc @@ -33,10 +33,9 @@ Key::~Key() { } -void Key::drawKey(cv::Mat& img, float alpha = 0.5) +void Key::drawKey(cv::Mat& img, float alpha = 0.5, double fontScale = 2) { int fontFace = cv::FONT_HERSHEY_SIMPLEX; - double fontScale = 2; int thickness = 2; cv::Scalar text_color = cv::Scalar(255, 255, 255, 255); cv::Scalar bg_color = cv::Scalar(255, 0, 0, 0); diff --git a/src/reference/ai_poc/virtual_keyboard/key.h b/src/reference/ai_poc/virtual_keyboard/key.h index 04a98a71f..90090c9a8 100644 --- a/src/reference/ai_poc/virtual_keyboard/key.h +++ b/src/reference/ai_poc/virtual_keyboard/key.h @@ -71,9 +71,10 @@ class Key * @brief 将键盘画到原图 * @param img 原始图片 * @param alpha 键盘按钮的透明度 + * @param fontScale 字体大小 * @return None */ - void drawKey(cv::Mat& img, float alpha); + void drawKey(cv::Mat& img, float alpha , double fontScale); /** * @brief 判断一个点是否在键盘按钮内 diff --git a/src/reference/ai_poc/virtual_keyboard/main.cc b/src/reference/ai_poc/virtual_keyboard/main.cc index 32c214909..ad3c9dec7 100644 --- a/src/reference/ai_poc/virtual_keyboard/main.cc +++ b/src/reference/ai_poc/virtual_keyboard/main.cc @@ -53,7 +53,7 @@ float calculateIntDidtance(cv::Point pt1, cv::Point pt2) { return cv::sqrt((pt1.x - pt2.x) * (pt1.x - pt2.x) + (pt1.y - pt2.y) * (pt1.y - pt2.y)); } -void video_proc(char *argv[]) +void video_proc_K230D_CANMV(char *argv[]) { vivcap_start(); // 设置osd参数 @@ -80,79 +80,472 @@ void video_proc(char *argv[]) HandDetection hd(argv[1], atof(argv[2]), atof(argv[3]), {SENSOR_WIDTH, SENSOR_HEIGHT}, {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); HandKeypoint hk(argv[4], {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); - std::vector results; std::vector keys; std::string letters = "QWERTYUIOPASDFGHJKLZXCVBNM"; - #if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - int character_len = 39; - int box_w = 140; - int box_h = 100; - int startX = 215; - int startY = 360; - int margin = 10; - for (int i = 0; i < letters.size(); i++) { - if (i < 10) + int character_len = 39; + int box_w = 140 * 1.0 / 1920 * osd_height; + int box_h = 100 * 1.0 / 1080 * osd_width; + int startX = 215 * 1.0 / 1920 * osd_height; + int startY = 360 * 1.0 / 1080 * osd_width; + int margin = 10 * 1.0 / 1920 * osd_height; + int startX2 = 290 * 1.0 / 1920 * osd_height; + int startX3 = 365 * 1.0 / 1920 * osd_height; + int box_w_space = 650 * 1.0 / 1920 * osd_height; + for (int i = 0; i < letters.size(); i++) { + if (i < 10) + { + keys.push_back(Key(startX + i * box_w + i * margin, startY, box_w, box_h, std::string(1, letters[i]))); + } + else if (i<19) + { + keys.push_back(Key(startX2 + (i-10) * box_w + (i-10) * margin, startY+box_h+margin, box_w, box_h, std::string(1, letters[i]))); + } + else + { + keys.push_back(Key(startX3 + (i-19) * box_w + (i-19) * margin, startY+2*box_h+2*margin, box_w, box_h, std::string(1, letters[i]))); + } + } + + keys.push_back(Key(startX3 + (26-19) * box_w + (26-19) * margin, startY+2*box_h+2*margin, box_w, box_h, "clr")); + keys.push_back(Key(startX2, startY+3*box_h+3*margin, box_w_space, box_h, "Space")); + keys.push_back(Key(startX2 + margin + box_w_space, startY+3*box_h+3*margin, box_w_space, box_h, "<--")); + + Key textBox(startX, startY-box_h-margin, 10*box_w+9*margin, box_h, " "); + + float previousClick = 0.0; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + { + ScopedTiming st("read capture", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + memset(&dump_info, 0, sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { - keys.push_back(Key(startX + i * box_w + i * margin, startY, box_w, box_h, std::string(1, letters[i]))); + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; } - else if (i<19) + } + { + ScopedTiming st("isp copy", atoi(argv[5])); + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + hd.pre_process(); + hd.inference(); + hd.post_process(results); + + int signTipX = 0, signTipY = 0; + int thumbTipX = 0, thumbTipY = 0; + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + cv::Point2f index_top; + cv::Point2f thumb_top; + float ratio; + + for (auto r: results) + { + int w = r.x2 - r.x1 + 1; + int h = r.y2 - r.y1 + 1; + + int length = std::max(w,h)/2; + int cx = (r.x1+r.x2)/2; + int cy = (r.y1+r.y2)/2; + int ratio_num = 1.26*length; + + int x1_1 = std::max(0,cx-ratio_num); + int y1_1 = std::max(0,cy-ratio_num); + int x2_1 = std::min(SENSOR_WIDTH-1, cx+ratio_num); + int y2_1 = std::min(SENSOR_HEIGHT-1, cy+ratio_num); + int w_1 = x2_1 - x1_1 + 1; + int h_1 = y2_1 - y1_1 + 1; + + struct Bbox bbox = {x:x1_1,y:y1_1,w:w_1,h:h_1}; + hk.pre_process(bbox); + hk.inference(); + hk.post_process(bbox); + { - keys.push_back(Key(startX + (i-10) * box_w + (i-10) * margin + 75, startY+box_h+margin, box_w, box_h, std::string(1, letters[i]))); + ScopedTiming st("osd draw keypoints", atoi(argv[5])); + hk.draw_keypoints(osd_frame, bbox, false); } - else + + float *pred = hk.get_out()[0]; + int draw_x,draw_y; + + index_top.x = pred[8*2] * w_1 + x1_1; + index_top.y = pred[8*2+1] * h_1 + y1_1; + signTipX = static_cast(index_top.x / SENSOR_WIDTH * osd_height); + signTipY = static_cast(index_top.y / SENSOR_HEIGHT * osd_width); + + thumb_top.x = pred[4*2] * w_1 + x1_1; + thumb_top.y = pred[4*2+1] * h_1 + y1_1; + thumbTipX = static_cast(thumb_top.x / SENSOR_WIDTH * osd_height); + thumbTipY = static_cast(thumb_top.y / SENSOR_HEIGHT * osd_width); + + float dis = calculateIntDidtance(cv::Point(signTipX, signTipY), cv::Point(thumbTipX, thumbTipY)); + float dis_hand = calculateIntDidtance(cv::Point(hk.minX, hk.minY), cv::Point(hk.maxX, hk.maxY)); + ratio = dis/dis_hand; + if (ratio < 0.25) { - keys.push_back(Key(startX + (i-19) * box_w + (i-19) * margin + 150, startY+2*box_h+2*margin, box_w, box_h, std::string(1, letters[i]))); + int centerX = (signTipX + thumbTipX) / 2; + int centerY = (signTipY + thumbTipY) / 2; + cv::circle(osd_frame, cv::Point(centerX, centerY), 5, cv::Scalar(255, 0, 255, 0), cv::FILLED); } } + { + ScopedTiming st("osd draw keyboard", atoi(argv[5])); + float alpha = 0.5; + textBox.drawKey(osd_frame, (float)0.3, 0.5); + for (auto& k : keys) + { + if (k.isOver(thumbTipX, thumbTipY)) + { + alpha = 0.2; + if ((k.isOver(signTipX, signTipY)) && (ratio < 0.25)) + { + float clickTime = cv::getTickCount(); + if ((clickTime - previousClick) / cv::getTickFrequency() > 0.6) + { + if (k.text_ == "<--") + { + textBox.text_ = textBox.text_.substr(0, textBox.text_.size() - 1); + } + else if (k.text_ == "clr") + { + textBox.text_ = ""; + } + else if (textBox.text_.size() < character_len) + { + if (k.text_ == "Space") { + textBox.text_ += " "; + } + else { + textBox.text_ += k.text_; + } + } + previousClick = clickTime; + } + } + } + k.drawKey(osd_frame, alpha, 0.5); + alpha = 0.5; + } + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + // 显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id + 3, &vf_info); // K_VO_OSD0 - keys.push_back(Key(startX + (26-19) * box_w + (26-19) * margin + 150, startY+2*box_h+2*margin, box_w, box_h, "clr")); - keys.push_back(Key(startX + 90, startY+3*box_h+3*margin, 650, box_h, "Space")); - keys.push_back(Key(startX + 100 + 650, startY+3*box_h+3*margin, 650, box_h, "<--")); - - Key textBox(startX, startY-box_h-margin, 10*box_w+9*margin, box_h, " "); - #else - int character_len = 18; - int box_w = 140; - int box_h = 180; - int startX = 174; - int startY = 270; - int margin = 10; - for (int i = 0; i < letters.size(); i++) { - if (i < 5) + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { - keys.push_back(Key(startX + i * box_w + i * margin, startY, box_w, box_h, std::string(1, letters[i]))); + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); } - else if (i<10) + } + } + + vo_osd_release_block(); + vivcap_stop(); + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } +} + +void video_proc_CANMV_01STUDIO(char *argv[]) +{ + vivcap_start(); + // 设置osd参数 + k_video_frame_info vf_info; + void *pic_vaddr = NULL; // osd + memset(&vf_info, 0, sizeof(vf_info)); + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory,get isp memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + HandDetection hd(argv[1], atof(argv[2]), atof(argv[3]), {SENSOR_WIDTH, SENSOR_HEIGHT}, {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + HandKeypoint hk(argv[4], {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + std::vector results; + + std::vector keys; + std::string letters = "QWERTYUIOPASDFGHJKLZXCVBNM"; + + int character_len = 39; + int box_w = 140 * 1.0 / 1920 * osd_height; + int box_h = 100 * 1.0 / 1080 * osd_width; + int startX = 215 * 1.0 / 1920 * osd_height; + int startY = 360 * 1.0 / 1080 * osd_width; + int margin = 10 * 1.0 / 1920 * osd_height; + int startX2 = 290 * 1.0 / 1920 * osd_height; + int startX3 = 365 * 1.0 / 1920 * osd_height; + int box_w_space = 650 * 1.0 / 1920 * osd_height; + for (int i = 0; i < letters.size(); i++) { + if (i < 10) + { + keys.push_back(Key(startX + i * box_w + i * margin, startY, box_w, box_h, std::string(1, letters[i]))); + } + else if (i<19) + { + keys.push_back(Key(startX2 + (i-10) * box_w + (i-10) * margin, startY+box_h+margin, box_w, box_h, std::string(1, letters[i]))); + } + else + { + keys.push_back(Key(startX3 + (i-19) * box_w + (i-19) * margin, startY+2*box_h+2*margin, box_w, box_h, std::string(1, letters[i]))); + } + } + + keys.push_back(Key(startX3 + (26-19) * box_w + (26-19) * margin, startY+2*box_h+2*margin, box_w, box_h, "clr")); + keys.push_back(Key(startX2, startY+3*box_h+3*margin, box_w_space, box_h, "Space")); + keys.push_back(Key(startX2 + margin + box_w_space, startY+3*box_h+3*margin, box_w_space, box_h, "<--")); + + Key textBox(startX, startY-box_h-margin, 10*box_w+9*margin, box_h, " "); + + float previousClick = 0.0; + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + { + ScopedTiming st("read capture", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + memset(&dump_info, 0, sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { - keys.push_back(Key(startX + (i-5) * box_w + (i-5) * margin, startY+box_h+margin, box_w, box_h, std::string(1, letters[i]))); + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; } - else if (i<15) + } + { + ScopedTiming st("isp copy", atoi(argv[5])); + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); + kd_mpi_sys_munmap(vbvaddr, size); + } + + results.clear(); + + hd.pre_process(); + hd.inference(); + hd.post_process(results); + + int signTipX = 0, signTipY = 0; + int thumbTipX = 0, thumbTipY = 0; + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + + cv::Point2f index_top; + cv::Point2f thumb_top; + float ratio; + + for (auto r: results) + { + int w = r.x2 - r.x1 + 1; + int h = r.y2 - r.y1 + 1; + + int length = std::max(w,h)/2; + int cx = (r.x1+r.x2)/2; + int cy = (r.y1+r.y2)/2; + int ratio_num = 1.26*length; + + int x1_1 = std::max(0,cx-ratio_num); + int y1_1 = std::max(0,cy-ratio_num); + int x2_1 = std::min(SENSOR_WIDTH-1, cx+ratio_num); + int y2_1 = std::min(SENSOR_HEIGHT-1, cy+ratio_num); + int w_1 = x2_1 - x1_1 + 1; + int h_1 = y2_1 - y1_1 + 1; + + struct Bbox bbox = {x:x1_1,y:y1_1,w:w_1,h:h_1}; + hk.pre_process(bbox); + hk.inference(); + hk.post_process(bbox); + { - keys.push_back(Key(startX + (i-10) * box_w + (i-10) * margin, startY+2*box_h+2*margin, box_w, box_h, std::string(1, letters[i]))); + ScopedTiming st("osd draw keypoints", atoi(argv[5])); + hk.draw_keypoints(osd_frame, bbox, false); } - else if (i<20) + + float *pred = hk.get_out()[0]; + int draw_x,draw_y; + + index_top.x = pred[8*2] * w_1 + x1_1; + index_top.y = pred[8*2+1] * h_1 + y1_1; + signTipX = static_cast(index_top.x / SENSOR_WIDTH * osd_height); + signTipY = static_cast(index_top.y / SENSOR_HEIGHT * osd_width); + + thumb_top.x = pred[4*2] * w_1 + x1_1; + thumb_top.y = pred[4*2+1] * h_1 + y1_1; + thumbTipX = static_cast(thumb_top.x / SENSOR_WIDTH * osd_height); + thumbTipY = static_cast(thumb_top.y / SENSOR_HEIGHT * osd_width); + + float dis = calculateIntDidtance(cv::Point(signTipX, signTipY), cv::Point(thumbTipX, thumbTipY)); + float dis_hand = calculateIntDidtance(cv::Point(hk.minX, hk.minY), cv::Point(hk.maxX, hk.maxY)); + ratio = dis/dis_hand; + if (ratio < 0.25) { - keys.push_back(Key(startX + (i-15) * box_w + (i-15) * margin, startY+3*box_h+3*margin, box_w, box_h, std::string(1, letters[i]))); + int centerX = (signTipX + thumbTipX) / 2; + int centerY = (signTipY + thumbTipY) / 2; + cv::circle(osd_frame, cv::Point(centerX, centerY), 5, cv::Scalar(255, 0, 255, 0), cv::FILLED); } - else if (i<25) + } + { + ScopedTiming st("osd draw keyboard", atoi(argv[5])); + float alpha = 0.5; + textBox.drawKey(osd_frame, (float)0.3, 0.5); + for (auto& k : keys) { - keys.push_back(Key(startX + (i-20) * box_w + (i-20) * margin, startY+4*box_h+4*margin, box_w, box_h, std::string(1, letters[i]))); + if (k.isOver(thumbTipX, thumbTipY)) + { + alpha = 0.2; + if ((k.isOver(signTipX, signTipY)) && (ratio < 0.25)) + { + float clickTime = cv::getTickCount(); + if ((clickTime - previousClick) / cv::getTickFrequency() > 0.6) + { + if (k.text_ == "<--") + { + textBox.text_ = textBox.text_.substr(0, textBox.text_.size() - 1); + } + else if (k.text_ == "clr") + { + textBox.text_ = ""; + } + else if (textBox.text_.size() < character_len) + { + if (k.text_ == "Space") { + textBox.text_ += " "; + } + else { + textBox.text_ += k.text_; + } + } + previousClick = clickTime; + } + } + } + k.drawKey(osd_frame, alpha, 0.5); + alpha = 0.5; } - else + } + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + { + ScopedTiming st("osd copy", atoi(argv[5])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + // 显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id + 3, &vf_info); // K_VO_OSD0 + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { - keys.push_back(Key(startX + (i-25) * box_w + (i-25) * margin, startY+5*box_h+5*margin, box_w, box_h, std::string(1, letters[i]))); + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); } } + } - keys.push_back(Key(startX + (26-25) * box_w + (26-25) * margin, startY+5*box_h+5*margin, 215, box_h, "Space")); - keys.push_back(Key(startX + (26-25) * box_w + 215 + (27-25) * margin, startY+5*box_h+5*margin, box_w, box_h, "clr")); - keys.push_back(Key(startX + (27-25) * box_w + 215 + (28-25) * margin, startY+5*box_h+5*margin, 215, box_h, "<--")); - - Key textBox(startX, startY-box_h-margin, 5*box_w+4*margin, box_h, " "); - #endif + vo_osd_release_block(); + vivcap_stop(); + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } +} + +void video_proc(char *argv[]) +{ + vivcap_start(); + // 设置osd参数 + k_video_frame_info vf_info; + void *pic_vaddr = NULL; // osd + memset(&vf_info, 0, sizeof(vf_info)); + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory,get isp memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + HandDetection hd(argv[1], atof(argv[2]), atof(argv[3]), {SENSOR_WIDTH, SENSOR_HEIGHT}, {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + HandKeypoint hk(argv[4], {SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[5])); + + + std::vector results; + + std::vector keys; + std::string letters = "QWERTYUIOPASDFGHJKLZXCVBNM"; + + int character_len = 39; + int box_w = 140; + int box_h = 100; + int startX = 215; + int startY = 360; + int margin = 10; + for (int i = 0; i < letters.size(); i++) { + if (i < 10) + { + keys.push_back(Key(startX + i * box_w + i * margin, startY, box_w, box_h, std::string(1, letters[i]))); + } + else if (i<19) + { + keys.push_back(Key(startX + (i-10) * box_w + (i-10) * margin + 75, startY+box_h+margin, box_w, box_h, std::string(1, letters[i]))); + } + else + { + keys.push_back(Key(startX + (i-19) * box_w + (i-19) * margin + 150, startY+2*box_h+2*margin, box_w, box_h, std::string(1, letters[i]))); + } + } + + keys.push_back(Key(startX + (26-19) * box_w + (26-19) * margin + 150, startY+2*box_h+2*margin, box_w, box_h, "clr")); + keys.push_back(Key(startX + 90, startY+3*box_h+3*margin, 650, box_h, "Space")); + keys.push_back(Key(startX + 100 + 650, startY+3*box_h+3*margin, 650, box_h, "<--")); + + Key textBox(startX, startY-box_h-margin, 10*box_w+9*margin, box_h, " "); float previousClick = 0.0; @@ -245,7 +638,7 @@ void video_proc(char *argv[]) { ScopedTiming st("osd draw keyboard", atoi(argv[5])); float alpha = 0.5; - textBox.drawKey(osd_frame, (float)0.3); + textBox.drawKey(osd_frame, (float)0.3, 2); for (auto& k : keys) { if (k.isOver(thumbTipX, thumbTipY)) @@ -277,7 +670,7 @@ void video_proc(char *argv[]) } } } - k.drawKey(osd_frame, alpha); + k.drawKey(osd_frame, alpha, 2); alpha = 0.5; } } @@ -317,7 +710,14 @@ int main(int argc, char *argv[]) return -1; } { - std::thread thread_isp(video_proc, argv); + #if defined(CONFIG_BOARD_K230D_CANMV) + std::thread thread_isp(video_proc_K230D_CANMV, argv); + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + std::thread thread_isp(video_proc_CANMV_01STUDIO, argv); + #else + std::thread thread_isp(video_proc, argv); + #endif + while (getchar() != 'q') { usleep(10000); diff --git a/src/reference/ai_poc/virtual_keyboard/vi_vo.h b/src/reference/ai_poc/virtual_keyboard/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/virtual_keyboard/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/ai_poc/yolop_lane_seg/main.cc b/src/reference/ai_poc/yolop_lane_seg/main.cc index 2c6486966..19aaeaa5c 100755 --- a/src/reference/ai_poc/yolop_lane_seg/main.cc +++ b/src/reference/ai_poc/yolop_lane_seg/main.cc @@ -49,7 +49,7 @@ void print_usage(const char *name) << endl; } -void video_proc(char *argv[]) +void video_proc_v1(char *argv[]) { vivcap_start(); @@ -135,6 +135,268 @@ void video_proc(char *argv[]) } +void video_proc_v2(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + SEG seg(argv[1],{SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[3])); + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[3])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + seg.pre_process(); + seg.inference(); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + seg.post_process_video( osd_frame ); + + { + ScopedTiming st("osd copy", atoi(argv[3])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + +void video_proc_k230d(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + SEG seg(argv[1],{SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[3])); + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[3])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + seg.pre_process(); + seg.inference(); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + seg.post_process_video( osd_frame ); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[3])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} + + +void video_proc_01(char *argv[]) +{ + vivcap_start(); + + k_video_frame_info vf_info; + void *pic_vaddr = NULL; //osd + + memset(&vf_info, 0, sizeof(vf_info)); + + vf_info.v_frame.width = osd_width; + vf_info.v_frame.height = osd_height; + vf_info.v_frame.stride[0] = osd_width; + vf_info.v_frame.pixel_format = PIXEL_FORMAT_ARGB_8888; + block = vo_insert_frame(&vf_info, &pic_vaddr); + + // alloc memory + size_t paddr = 0; + void *vaddr = nullptr; + size_t size = SENSOR_CHANNEL * SENSOR_HEIGHT * SENSOR_WIDTH; + int ret = kd_mpi_sys_mmz_alloc_cached(&paddr, &vaddr, "allocate", "anonymous", size); + if (ret) + { + std::cerr << "physical_memory_block::allocate failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + + SEG seg(argv[1],{SENSOR_CHANNEL, SENSOR_HEIGHT, SENSOR_WIDTH}, reinterpret_cast(vaddr), reinterpret_cast(paddr), atoi(argv[3])); + + while (!isp_stop) + { + ScopedTiming st("total time", 1); + + { + ScopedTiming st("read capture", atoi(argv[3])); + // VICAP_CHN_ID_1 out rgb888p + memset(&dump_info, 0 , sizeof(k_video_frame_info)); + ret = kd_mpi_vicap_dump_frame(vicap_dev, VICAP_CHN_ID_1, VICAP_DUMP_YUV, &dump_info, 1000); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_frame failed.\n"); + continue; + } + } + + + { + ScopedTiming st("isp copy", atoi(argv[5])); + // 从vivcap中读取一帧图像到dump_info + auto vbvaddr = kd_mpi_sys_mmap_cached(dump_info.v_frame.phys_addr[0], size); + memcpy(vaddr, (void *)vbvaddr, SENSOR_HEIGHT * SENSOR_WIDTH * 3); // 这里以后可以去掉，不用copy + kd_mpi_sys_munmap(vbvaddr, size); + } + + seg.pre_process(); + seg.inference(); + + cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + seg.post_process_video( osd_frame ); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + + { + ScopedTiming st("osd copy", atoi(argv[3])); + memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); + //显示通道插入帧 + kd_mpi_vo_chn_insert_frame(osd_id+3, &vf_info); //K_VO_OSD0 + // printf("kd_mpi_vo_chn_insert_frame success \n"); + + ret = kd_mpi_vicap_dump_release(vicap_dev, VICAP_CHN_ID_1, &dump_info); + if (ret) { + printf("sample_vicap...kd_mpi_vicap_dump_release failed.\n"); + } + } + } + + vo_osd_release_block(); + vivcap_stop(); + + + // free memory + ret = kd_mpi_sys_mmz_free(paddr, vaddr); + if (ret) + { + std::cerr << "free failed: ret = " << ret << ", errno = " << strerror(errno) << std::endl; + std::abort(); + } + +} int main(int argc, char *argv[]) { @@ -147,14 +409,62 @@ int main(int argc, char *argv[]) if (strcmp(argv[2], "None") == 0) { - std::thread thread_isp(video_proc, argv); - while (getchar() != 'q') + #if defined(CONFIG_BOARD_K230_CANMV) { - usleep(10000); + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); } + #elif defined(CONFIG_BOARD_K230_CANMV_V2) + { + std::thread thread_isp(video_proc_v2, argv); + while (getchar() != 'q') + { + usleep(10000); + } - isp_stop = true; - thread_isp.join(); + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230D_CANMV) + { + std::thread thread_isp(video_proc_k230d, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + std::thread thread_isp(video_proc_01, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #else + { + std::thread thread_isp(video_proc_v1, argv); + while (getchar() != 'q') + { + usleep(10000); + } + + isp_stop = true; + thread_isp.join(); + } + #endif } else diff --git a/src/reference/ai_poc/yolop_lane_seg/vi_vo.h b/src/reference/ai_poc/yolop_lane_seg/vi_vo.h deleted file mode 100644 index 0a11a4d31..000000000 --- a/src/reference/ai_poc/yolop_lane_seg/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/business_poc/dictionary_pen_poc/audio/audio_buf_play.cc b/src/reference/business_poc/dictionary_pen_poc/audio/audio_buf_play.cc index d4bc01dc1..3013b9792 100755 --- a/src/reference/business_poc/dictionary_pen_poc/audio/audio_buf_play.cc +++ b/src/reference/business_poc/dictionary_pen_poc/audio/audio_buf_play.cc @@ -118,6 +118,7 @@ k_s32 audio_buffer_play_init(k_u32 sample_rate,k_u32 channel_count) g_sample_rate = sample_rate; k_aio_dev_attr ao_dev_attr; + memset(&ao_dev_attr,0,sizeof(ao_dev_attr)); ao_dev_attr.audio_type = KD_AUDIO_OUTPUT_TYPE_I2S; ao_dev_attr.kd_audio_attr.i2s_attr.sample_rate = sample_rate; ao_dev_attr.kd_audio_attr.i2s_attr.bit_width = KD_AUDIO_BIT_WIDTH_16; @@ -191,4 +192,4 @@ void audio_test_file(void) audio_buffer_play(pcm_file_data+WAV_HEAD_SIZE,size-WAV_HEAD_SIZE); -} \ No newline at end of file +} diff --git a/src/reference/fancy_poc/CMakeLists.txt b/src/reference/fancy_poc/CMakeLists.txt index a4d2ba568..65b0b22b4 100755 --- a/src/reference/fancy_poc/CMakeLists.txt +++ b/src/reference/fancy_poc/CMakeLists.txt @@ -21,6 +21,10 @@ include_directories(${nncase_sdk_root}/riscv64/nncase/include) include_directories(${nncase_sdk_root}/riscv64/nncase/include/nncase/runtime) link_directories(${nncase_sdk_root}/riscv64/nncase/lib/) + +# set vi_vo +include_directories(./vi_vo) + add_subdirectory(./multimodal_chat_robot/src/multimodal_chat_robot_client/aiot_gpt) add_subdirectory(./meta_human/src/meta_human) add_subdirectory(./finger_reader/src/finger_reader_client/finger_reader_ai) diff --git a/src/reference/fancy_poc/ai_scale/README.md b/src/reference/fancy_poc/ai_scale/README.md index 9d0f91147..043b7cebf 100755 --- a/src/reference/fancy_poc/ai_scale/README.md +++ b/src/reference/fancy_poc/ai_scale/README.md @@ -1,6 +1,6 @@ # K230 模拟AI电子秤 ![Alt text](resource/image.png) -Document version: V1.4 Release date: 2024-1-31 +Document version: V1.4 Release date: 2024-6-5 ## 介绍 该项目为K230 模拟AI电子秤开源工程。本工程基于K230应用了度量学习技术实现商品识别。本应用使用PC作为服务端控制上秤、下秤、采集新商品和展示称重商品；使用K230作为客户端建立对比向量库，然后捕捉图像进行向量相似度对比获得商品类别，结合商品单价和商品重量得到应付钱数；最后将商品类别和应付钱数在PC端展示给用户。 @@ -24,7 +24,7 @@ Document version: V1.4 Release date: 2024-1-31 wget https://ai.b-bug.org/k230/downloads/fancy_poc/ai_scale/$file || wget https://kendryte-download.canaan-creative.com/k230/downloads/fancy_poc/ai_scale/$file; done - for file in onboard_v2.8.zip + for file in onboard_v2.8.3.zip do wget https://ai.b-bug.org/k230/downloads/fancy_poc/ai_scale/k230_board/$file || wget https://kendryte-download.canaan-creative.com/k230/downloads/fancy_poc/ai_scale/k230_board/$file; done @@ -81,7 +81,7 @@ ifconfig 该数据集用于在商品识别之前创建底库。 -本项目提供了示例商品类别底库，请参照onboard_v2.8/gallery中的数据结构组织数据。 +本项目提供了示例商品类别底库，请参照onboard_v2.8.3/gallery中的数据结构组织数据。 ## 可执行文件编译 @@ -92,7 +92,7 @@ chmod +x build_app.sh ./build_app.sh ``` -在reference/fancy_poc/k230_bin目录下，获取ai_scale.elf和client拷贝到开发板onboard_v2.8内。 +在reference/fancy_poc/k230_bin目录下，获取ai_scale.elf和client拷贝到开发板onboard_v2.8.3内。 ## 服务端准备 diff --git a/src/reference/fancy_poc/ai_scale/src/ai_scale_ai_code/main.cc b/src/reference/fancy_poc/ai_scale/src/ai_scale_ai_code/main.cc index d2e46734c..945dd078c 100755 --- a/src/reference/fancy_poc/ai_scale/src/ai_scale_ai_code/main.cc +++ b/src/reference/fancy_poc/ai_scale/src/ai_scale_ai_code/main.cc @@ -572,6 +572,10 @@ void video_proc(string &kmodel_path, size_t top_k, int debug_mode) cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); cv::Mat osd_frame_tmp; + #if defined(CONFIG_BOARD_K230D_CANMV) + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + #endif + if(file_exists(weight_flag) && rec_flag){ ScopedTiming st("embedding search", debug_mode); // Get the top k similar files @@ -590,6 +594,9 @@ void video_proc(string &kmodel_path, size_t top_k, int debug_mode) save_result("res/result.txt",text); } + #if defined(CONFIG_BOARD_K230D_CANMV) + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + #endif { ScopedTiming st("osd copy", debug_mode); memcpy(pic_vaddr, osd_frame.data, osd_width * osd_height * 4); diff --git a/src/reference/fancy_poc/ai_scale/src/ai_scale_ai_code/vi_vo.h b/src/reference/fancy_poc/ai_scale/src/ai_scale_ai_code/vi_vo.h deleted file mode 100755 index 15f0bc111..000000000 --- a/src/reference/fancy_poc/ai_scale/src/ai_scale_ai_code/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/fancy_poc/face_recognition/README.md b/src/reference/fancy_poc/face_recognition/README.md index 55aa641c4..5ba90843d 100755 --- a/src/reference/fancy_poc/face_recognition/README.md +++ b/src/reference/fancy_poc/face_recognition/README.md @@ -21,7 +21,7 @@ Document version: V1.0 Release date: 2023-12-22 wget https://ai.b-bug.org/k230/downloads/fancy_poc/face_recognition/$file || wget https://kendryte-download.canaan-creative.com/k230/downloads/fancy_poc/face_recognition/$file; done - for file in onboard_v2.8.1.zip + for file in onboard_v2.8.3.zip do wget https://ai.b-bug.org/k230/downloads/fancy_poc/face_recognition/k230_board/$file || wget https://kendryte-download.canaan-creative.com/k230/downloads/fancy_poc/face_recognition/k230_board/$file; done diff --git a/src/reference/fancy_poc/face_recognition/src/download.sh b/src/reference/fancy_poc/face_recognition/src/download.sh index 971d2927f..8fb033ba4 100755 --- a/src/reference/fancy_poc/face_recognition/src/download.sh +++ b/src/reference/fancy_poc/face_recognition/src/download.sh @@ -3,7 +3,7 @@ do wget https://ai.b-bug.org/k230/downloads/fancy_poc/face_recognition/$file || wget https://kendryte-download.canaan-creative.com/k230/downloads/fancy_poc/face_recognition/$file; done -for file in onboard_v2.8.1.zip +for file in onboard_v2.8.3.zip do wget https://ai.b-bug.org/k230/downloads/fancy_poc/face_recognition/k230_board/$file || wget https://kendryte-download.canaan-creative.com/k230/downloads/fancy_poc/face_recognition/k230_board/$file; done \ No newline at end of file diff --git a/src/reference/fancy_poc/face_recognition/src/face_recognition/main.cc b/src/reference/fancy_poc/face_recognition/src/face_recognition/main.cc index 095c09320..1bb39156c 100755 --- a/src/reference/fancy_poc/face_recognition/src/face_recognition/main.cc +++ b/src/reference/fancy_poc/face_recognition/src/face_recognition/main.cc @@ -115,6 +115,7 @@ void video_proc(char *argv[]) face_det.post_process({SENSOR_WIDTH, SENSOR_HEIGHT}, det_results); cv::Mat osd_frame(osd_height, osd_width, CV_8UC4, cv::Scalar(0, 0, 0, 0)); + for (int i = 0; i < det_results.size(); ++i) { //***for face recg*** @@ -123,7 +124,26 @@ void video_proc(char *argv[]) FaceRecognitionInfo recg_result; face_recg.database_search(recg_result); - face_recg.draw_result(osd_frame,det_results[i].bbox,recg_result,false); + #if defined(CONFIG_BOARD_K230D_CANMV) + { + ScopedTiming st("osd draw", atoi(argv[8])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + face_recg.draw_result(osd_frame,det_results[i].bbox,recg_result,false); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + { + ScopedTiming st("osd draw", atoi(argv[8])); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_COUNTERCLOCKWISE); + face_recg.draw_result(osd_frame,det_results[i].bbox,recg_result,false); + cv::rotate(osd_frame, osd_frame, cv::ROTATE_90_CLOCKWISE); + } + #else + { + ScopedTiming st("osd draw", atoi(argv[8])); + face_recg.draw_result(osd_frame,det_results[i].bbox,recg_result,false); + } + #endif } { diff --git a/src/reference/fancy_poc/face_recognition/src/face_recognition/vi_vo.h b/src/reference/fancy_poc/face_recognition/src/face_recognition/vi_vo.h deleted file mode 100755 index 15f0bc111..000000000 --- a/src/reference/fancy_poc/face_recognition/src/face_recognition/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/fancy_poc/finger_reader/readme.md b/src/reference/fancy_poc/finger_reader/readme.md index 381036b32..03f5a27c0 100755 --- a/src/reference/fancy_poc/finger_reader/readme.md +++ b/src/reference/fancy_poc/finger_reader/readme.md @@ -2,7 +2,7 @@ ![](./resource/example_images/canaan-cover.png) -Document version: V1.4 Release date: 2024-1-31 +Document version: V1.6 Release date: 2024-5-31 ## 介绍 diff --git a/src/reference/fancy_poc/finger_reader/src/download.sh b/src/reference/fancy_poc/finger_reader/src/download.sh index 0924454a5..ccb4d5d48 100755 --- a/src/reference/fancy_poc/finger_reader/src/download.sh +++ b/src/reference/fancy_poc/finger_reader/src/download.sh @@ -1,5 +1,5 @@ -for file in onboard_v2.8.zip +for file in onboard_v2.8.3.zip do wget https://ai.b-bug.org/k230/downloads/fancy_poc/finger_reader/k230_board/$file || wget https://kendryte-download.canaan-creative.com/k230/downloads/fancy_poc/finger_reader/k230_board/$file; done diff --git a/src/reference/fancy_poc/finger_reader/src/finger_reader_client/finger_reader_ai/vi_vo.h b/src/reference/fancy_poc/finger_reader/src/finger_reader_client/finger_reader_ai/vi_vo.h deleted file mode 100755 index 94a349c3e..000000000 --- a/src/reference/fancy_poc/finger_reader/src/finger_reader_client/finger_reader_ai/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/fancy_poc/meta_hand/README.md b/src/reference/fancy_poc/meta_hand/README.md index 6a9bfcd73..11570f2f8 100755 --- a/src/reference/fancy_poc/meta_hand/README.md +++ b/src/reference/fancy_poc/meta_hand/README.md @@ -1,6 +1,6 @@ # K230 手势渲染POC ![Alt text](resource/image.png) -Document version: V1.4 Release date: 2024-1-31 +Document version: V1.6 Release date: 2024-5-31 ## 介绍 该项目为K230手势渲染POC开源工程，本工程基于K230融合了手部动作捕捉、手部3D mesh模型（MANO模型）等技术。本应用可以手部动作捕捉以及渲染，即K230作为client端摄取真人手部动作，通过在K230上的模型inference和post-process，再将结果传输给作为server端的PC，驱动MANO模型动起来。 ## 主要特点 @@ -22,7 +22,7 @@ Document version: V1.4 Release date: 2024-1-31 wget https://ai.b-bug.org/k230/downloads/fancy_poc/meta_hand/$file || wget https://kendryte-download.canaan-creative.com/k230/downloads/fancy_poc/meta_hand/$file; done - for file in onboard_v2.8.zip + for file in onboard_v2.8.3.zip do wget https://ai.b-bug.org/k230/downloads/fancy_poc/meta_hand/k230_board/$file || wget https://kendryte-download.canaan-creative.com/k230/downloads/fancy_poc/meta_hand/k230_board/$file; done diff --git a/src/reference/fancy_poc/meta_hand/resource/address.jpg b/src/reference/fancy_poc/meta_hand/resource/address.jpg old mode 100644 new mode 100755 diff --git a/src/reference/fancy_poc/meta_hand/src/download.sh b/src/reference/fancy_poc/meta_hand/src/download.sh index 076ce20a0..ac66b8f00 100755 --- a/src/reference/fancy_poc/meta_hand/src/download.sh +++ b/src/reference/fancy_poc/meta_hand/src/download.sh @@ -3,7 +3,7 @@ do wget https://ai.b-bug.org/k230/downloads/fancy_poc/meta_hand/$file || wget https://kendryte-download.canaan-creative.com/k230/downloads/fancy_poc/meta_hand/$file; done -for file in onboard_v2.8.zip +for file in onboard_v2.8.3.zip do wget https://ai.b-bug.org/k230/downloads/fancy_poc/meta_hand/k230_board/$file || wget https://kendryte-download.canaan-creative.com/k230/downloads/fancy_poc/meta_hand/k230_board/$file; done diff --git a/src/reference/fancy_poc/meta_hand/src/meta_hand/vi_vo.h b/src/reference/fancy_poc/meta_hand/src/meta_hand/vi_vo.h deleted file mode 100755 index 94a349c3e..000000000 --- a/src/reference/fancy_poc/meta_hand/src/meta_hand/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/fancy_poc/meta_human/README.md b/src/reference/fancy_poc/meta_human/README.md index b4023a1bc..a486d49ed 100755 --- a/src/reference/fancy_poc/meta_human/README.md +++ b/src/reference/fancy_poc/meta_human/README.md @@ -2,7 +2,7 @@
-Document version: V1.4 Release date: 2024-1-31 +Document version: V1.6 Release date: 2024-5-31 ## 介绍 @@ -44,7 +44,7 @@ do wget https://ai.b-bug.org/k230/downloads/fancy_poc/meta_human/$file || wget https://kendryte-download.canaan-creative.com/k230/downloads/fancy_poc/meta_human/$file; done -for file in onboard_v2.8.zip +for file in onboard_v2.8.3.zip do wget https://ai.b-bug.org/k230/downloads/fancy_poc/meta_human/k230_board/$file || wget https://kendryte-download.canaan-creative.com/k230/downloads/fancy_poc/meta_human/k230_board/$file; done diff --git a/src/reference/fancy_poc/meta_human/resource/pics/address.jpg b/src/reference/fancy_poc/meta_human/resource/pics/address.jpg old mode 100644 new mode 100755 diff --git a/src/reference/fancy_poc/meta_human/src/download.sh b/src/reference/fancy_poc/meta_human/src/download.sh index 2d2fb335a..f4b058891 100755 --- a/src/reference/fancy_poc/meta_human/src/download.sh +++ b/src/reference/fancy_poc/meta_human/src/download.sh @@ -5,7 +5,7 @@ do wget https://ai.b-bug.org/k230/downloads/fancy_poc/meta_human/$file || wget https://kendryte-download.canaan-creative.com/k230/downloads/fancy_poc/meta_human/$file; done -for file in onboard_v2.8.zip +for file in onboard_v2.8.3.zip do wget https://ai.b-bug.org/k230/downloads/fancy_poc/meta_human/k230_board/$file || wget https://kendryte-download.canaan-creative.com/k230/downloads/fancy_poc/meta_human/k230_board/$file; done diff --git a/src/reference/fancy_poc/meta_human/src/meta_human/vi_vo.h b/src/reference/fancy_poc/meta_human/src/meta_human/vi_vo.h deleted file mode 100755 index 94a349c3e..000000000 --- a/src/reference/fancy_poc/meta_human/src/meta_human/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/fancy_poc/multimodal_chat_robot/src/multimodal_chat_robot_client/aiot_gpt/vi_vo.h b/src/reference/fancy_poc/multimodal_chat_robot/src/multimodal_chat_robot_client/aiot_gpt/vi_vo.h deleted file mode 100755 index 15f0bc111..000000000 --- a/src/reference/fancy_poc/multimodal_chat_robot/src/multimodal_chat_robot_client/aiot_gpt/vi_vo.h +++ /dev/null @@ -1,628 +0,0 @@ -/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND - * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR - * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING - * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include - -#include "mpi_sys_api.h" - -/* vicap */ -#include -#include -#include -#include -#include - -#include "k_module.h" -#include "k_type.h" -#include "k_vb_comm.h" -#include "k_video_comm.h" -#include "k_sys_comm.h" -#include "mpi_vb_api.h" -#include "mpi_vicap_api.h" -#include "mpi_isp_api.h" -#include "mpi_sys_api.h" -#include "k_vo_comm.h" -#include "mpi_vo_api.h" - -#include "vo_test_case.h" - -#include "k_connector_comm.h" -#include "mpi_connector_api.h" -#include "k_autoconf_comm.h" - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1920) -#define osd_height (1080) -#else -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (720) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1088)//(1920) -#define ISP_CHN0_HEIGHT (1920)//(1080) -#define vicap_install_osd (1) -#define osd_id K_VO_OSD3 -#define osd_width (1080) -#define osd_height (1920) -#endif - - -k_vb_config config; -k_vicap_dev vicap_dev; -k_vicap_chn vicap_chn; -k_vicap_dev_attr dev_attr; -k_vicap_chn_attr chn_attr; -k_vicap_sensor_info sensor_info; -k_vicap_sensor_type sensor_type; -k_mpp_chn vicap_mpp_chn; -k_mpp_chn vo_mpp_chn; - -k_video_frame_info dump_info; - -k_vo_draw_frame vo_frame = (k_vo_draw_frame) { - 1, - 16, - 16, - 128, - 128, - 1 -}; - -static k_vb_blk_handle block; -k_u32 g_pool_id; - -int vo_creat_layer_test(k_vo_layer chn_id, layer_info *info) -{ - k_vo_video_layer_attr attr; - - // check layer - if ((chn_id >= K_MAX_VO_LAYER_NUM) || ((info->func & K_VO_SCALER_ENABLE) && (chn_id != K_VO_LAYER0)) - || ((info->func != 0) && (chn_id == K_VO_LAYER2))) - { - printf("input layer num failed \n"); - return -1 ; - } - - // check scaler - - // set offset - attr.display_rect = info->offset; - // set act - attr.img_size = info->act_size; - // sget size - info->size = info->act_size.height * info->act_size.width * 3 / 2; - //set pixel format - attr.pixel_format = info->format; - if (info->format != PIXEL_FORMAT_YVU_PLANAR_420) - { - printf("input pix format failed \n"); - return -1; - } - // set stride - attr.stride = (info->act_size.width / 8 - 1) + ((info->act_size.height - 1) << 16); - // set function - attr.func = info->func; - // set scaler attr - attr.scaler_attr = info->attr; - - // set video layer atrr - kd_mpi_vo_set_video_layer_attr(chn_id, &attr); - - // enable layer - kd_mpi_vo_enable_video_layer(chn_id); - - return 0; -} - -k_vb_blk_handle vo_insert_frame(k_video_frame_info *vf_info, void **pic_vaddr) -{ - k_u64 phys_addr = 0; - k_u32 *virt_addr; - k_vb_blk_handle handle; - k_s32 size; - - if (vf_info == NULL) - return K_FALSE; - - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_8888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_8888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 4; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_565 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_565) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_4444 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_4444) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_RGB_888 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_BGR_888) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_ARGB_1555 || vf_info->v_frame.pixel_format == PIXEL_FORMAT_ABGR_1555) - size = vf_info->v_frame.height * vf_info->v_frame.width * 2; - else if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - size = vf_info->v_frame.height * vf_info->v_frame.width * 3 / 2; - - size = size + 4096; // 强制4K ，后边得删了 - - printf("vb block size is %x \n", size); - - handle = kd_mpi_vb_get_block(g_pool_id, size, NULL); - if (handle == VB_INVALID_HANDLE) - { - printf("%s get vb block error\n", __func__); - return K_FAILED; - } - - phys_addr = kd_mpi_vb_handle_to_phyaddr(handle); - if (phys_addr == 0) - { - printf("%s get phys addr error\n", __func__); - return K_FAILED; - } - - virt_addr = (k_u32 *)kd_mpi_sys_mmap(phys_addr, size); - // virt_addr = (k_u32 *)kd_mpi_sys_mmap_cached(phys_addr, size); - - if (virt_addr == NULL) - { - printf("%s mmap error\n", __func__); - return K_FAILED; - } - - vf_info->mod_id = K_ID_VO; - vf_info->pool_id = g_pool_id; - vf_info->v_frame.phys_addr[0] = phys_addr; - if (vf_info->v_frame.pixel_format == PIXEL_FORMAT_YVU_PLANAR_420) - vf_info->v_frame.phys_addr[1] = phys_addr + (vf_info->v_frame.height * vf_info->v_frame.stride[0]); - *pic_vaddr = virt_addr; - - printf("phys_addr is %lx g_pool_id is %d \n", phys_addr, g_pool_id); - - return handle; -} - -k_u32 vo_creat_osd_test(k_vo_osd osd, osd_info *info) -{ - k_vo_video_osd_attr attr; - - // set attr - attr.global_alptha = info->global_alptha; - - if (info->format == PIXEL_FORMAT_ABGR_8888 || info->format == PIXEL_FORMAT_ARGB_8888) - { - info->size = info->act_size.width * info->act_size.height * 4; - info->stride = info->act_size.width * 4 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_565 || info->format == PIXEL_FORMAT_BGR_565) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if (info->format == PIXEL_FORMAT_RGB_888 || info->format == PIXEL_FORMAT_BGR_888) - { - info->size = info->act_size.width * info->act_size.height * 3; - info->stride = info->act_size.width * 3 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_4444 || info->format == PIXEL_FORMAT_ABGR_4444) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else if(info->format == PIXEL_FORMAT_ARGB_1555 || info->format == PIXEL_FORMAT_ABGR_1555) - { - info->size = info->act_size.width * info->act_size.height * 2; - info->stride = info->act_size.width * 2 / 8; - } - else - { - printf("set osd pixel format failed \n"); - } - - attr.stride = info->stride; - attr.pixel_format = info->format; - attr.display_rect = info->offset; - attr.img_size = info->act_size; - kd_mpi_vo_set_video_osd_attr(osd, &attr); - - kd_mpi_vo_osd_enable(osd); - - return 0; -} - -void sample_vicap_install_osd(void) -{ - osd_info osd; - - osd.act_size.width = osd_width ; - osd.act_size.height = osd_height; - osd.offset.x = 0; - osd.offset.y = 0; - osd.global_alptha = 0xff; - // osd.global_alptha = 0x32; - osd.format = PIXEL_FORMAT_ARGB_8888;//PIXEL_FORMAT_ARGB_4444; //PIXEL_FORMAT_ARGB_1555;//PIXEL_FORMAT_ARGB_8888; - - vo_creat_osd_test(osd_id, &osd); -} - -void vo_osd_release_block(void) -{ - if(vicap_install_osd == 1) - { - kd_mpi_vo_osd_disable(osd_id); - kd_mpi_vb_release_block(block); - } - -} - -static k_s32 sample_connector_init(void) -{ - k_u32 ret = 0; - k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#else - k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; -#endif - k_connector_info connector_info; - - memset(&connector_info, 0, sizeof(k_connector_info)); - - //connector get sensor info - ret = kd_mpi_get_connector_info(connector_type, &connector_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - connector_fd = kd_mpi_connector_open(connector_info.connector_name); - if (connector_fd < 0) { - printf("%s, connector open failed.\n", __func__); - return K_ERR_VO_NOTREADY; - } - - // set connect power - kd_mpi_connector_power_set(connector_fd, K_TRUE); - // connector init - kd_mpi_connector_init(connector_fd, connector_info); - - return 0; -} - -static k_s32 vo_layer_vdss_bind_vo_config(void) -{ - layer_info info; - - k_vo_layer chn_id = K_VO_LAYER1; - - memset(&info, 0, sizeof(info)); - - sample_connector_init(); - - // config lyaer - info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; - info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; - info.format = PIXEL_FORMAT_YVU_PLANAR_420; - info.func = 0;//K_ROTATION_180;////K_ROTATION_90; - info.global_alptha = 0xff; - info.offset.x = 0;//(1080-w)/2, - info.offset.y = 0;//(1920-h)/2; - vo_creat_layer_test(chn_id, &info); - - if(vicap_install_osd == 1) - sample_vicap_install_osd(); - - //exit ; - return 0; -} - -static void sample_vicap_bind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_bind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -static void sample_vicap_unbind_vo(k_mpp_chn vicap_mpp_chn, k_mpp_chn vo_mpp_chn) -{ - k_s32 ret; - - ret = kd_mpi_sys_unbind(&vicap_mpp_chn, &vo_mpp_chn); - if (ret) { - printf("kd_mpi_sys_unbind failed:0x%x\n", ret); - } - - return; -} - -int vivcap_start() -{ - k_s32 ret = 0; - - k_u32 pool_id; - k_vb_pool_config pool_config; - - printf("sample_vicap ...\n"); - -#if defined(CONFIG_BOARD_K230_CANMV) - sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) - sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else - sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; - - memset(&config, 0, sizeof(config)); - config.max_pool_cnt = 64; - //VB for YUV420SP output - config.comm_pool[0].blk_cnt = 5; - config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - - //VB for RGB888 output - config.comm_pool[1].blk_cnt = 5; - config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; - config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); - - ret = kd_mpi_vb_set_config(&config); - if (ret) { - printf("vb_set_config failed ret:%d\n", ret); - return ret; - } - - k_vb_supplement_config supplement_config; - memset(&supplement_config, 0, sizeof(supplement_config)); - supplement_config.supplement_config |= VB_SUPPLEMENT_JPEG_MASK; - - ret = kd_mpi_vb_set_supplement_config(&supplement_config); - if (ret) { - printf("vb_set_supplement_config failed ret:%d\n", ret); - return ret; - } - - ret = kd_mpi_vb_init(); - if (ret) { - printf("vb_init failed ret:%d\n", ret); - return ret; - } - printf("sample_vicap ...kd_mpi_vicap_get_sensor_info\n"); - - // dwc_dsi_init(); - vo_layer_vdss_bind_vo_config(); - - if(vicap_install_osd == 1) - { - memset(&pool_config, 0, sizeof(pool_config)); - pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); - pool_config.blk_cnt = 4; - pool_config.mode = VB_REMAP_MODE_NOCACHE; - pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 - g_pool_id = pool_id; - - printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); - } - - memset(&sensor_info, 0, sizeof(k_vicap_sensor_info)); - ret = kd_mpi_vicap_get_sensor_info(sensor_type, &sensor_info); - if (ret) { - printf("sample_vicap, the sensor type not supported!\n"); - return ret; - } - - memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); - dev_attr.acq_win.h_start = 0; - dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else - dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; - dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif - dev_attr.mode = VICAP_WORK_ONLINE_MODE; - - dev_attr.pipe_ctrl.data = 0xFFFFFFFF; - dev_attr.pipe_ctrl.bits.af_enable = 0; - dev_attr.pipe_ctrl.bits.ahdr_enable = 0; - - - dev_attr.cpature_frame = 0; - memcpy(&dev_attr.sensor_info, &sensor_info, sizeof(k_vicap_sensor_info)); - - ret = kd_mpi_vicap_set_dev_attr(vicap_dev, dev_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_dev_attr failed.\n"); - return ret; - } - - memset(&chn_attr, 0, sizeof(k_vicap_chn_attr)); - - //set chn0 output yuv420sp - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = ISP_CHN0_WIDTH; - chn_attr.out_win.height = ISP_CHN0_HEIGHT; - - -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - chn_attr.crop_win = dev_attr.acq_win; -#else - // chn_attr.crop_win = dev_attr.acq_win; - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_YVU_PLANAR_420; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[0].blk_size; - vicap_chn = VICAP_CHN_ID_0; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, vicap_chn, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - //bind vicap chn 0 to vo - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_bind_vo(vicap_mpp_chn, vo_mpp_chn); - printf("sample_vicap ...dwc_dsi_init\n"); - - //set chn1 output rgb888p - chn_attr.out_win.h_start = 0; - chn_attr.out_win.v_start = 0; - chn_attr.out_win.width = SENSOR_WIDTH ; - chn_attr.out_win.height = SENSOR_HEIGHT; - // chn_attr.crop_win = dev_attr.acq_win; - -#if defined(CONFIG_BOARD_K230_CANMV) - chn_attr.crop_win = dev_attr.acq_win; -#else - chn_attr.crop_win.h_start = 768; - chn_attr.crop_win.v_start = 16; - chn_attr.crop_win.width = ISP_CHN0_WIDTH; - chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif - - chn_attr.scale_win = chn_attr.out_win; - chn_attr.crop_enable = K_FALSE; - chn_attr.scale_enable = K_FALSE; - // chn_attr.dw_enable = K_FALSE; - chn_attr.chn_enable = K_TRUE; - chn_attr.pix_format = PIXEL_FORMAT_BGR_888_PLANAR; - chn_attr.buffer_num = VICAP_MAX_FRAME_COUNT;//at least 3 buffers for isp - chn_attr.buffer_size = config.comm_pool[1].blk_size; - - printf("sample_vicap ...kd_mpi_vicap_set_chn_attr, buffer_size[%d]\n", chn_attr.buffer_size); - ret = kd_mpi_vicap_set_chn_attr(vicap_dev, VICAP_CHN_ID_1, chn_attr); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_set_chn_attr failed.\n"); - return ret; - } - - printf("sample_vicap ...kd_mpi_vicap_init\n"); - ret = kd_mpi_vicap_init(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - printf("sample_vicap ...kd_mpi_vicap_start_stream\n"); - ret = kd_mpi_vicap_start_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - // goto err_exit; - } - - return ret; -} - -int vivcap_stop() -{ - printf("sample_vicap ...kd_mpi_vicap_stop_stream\n"); - int ret = kd_mpi_vicap_stop_stream(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_init failed.\n"); - return ret; - } - - ret = kd_mpi_vicap_deinit(vicap_dev); - if (ret) { - printf("sample_vicap, kd_mpi_vicap_deinit failed.\n"); - return ret; - } - - kd_mpi_vo_disable_video_layer(K_VO_LAYER1); - - vicap_mpp_chn.mod_id = K_ID_VI; - vicap_mpp_chn.dev_id = vicap_dev; - vicap_mpp_chn.chn_id = vicap_chn; - - vo_mpp_chn.mod_id = K_ID_VO; - vo_mpp_chn.dev_id = K_VO_DISPLAY_DEV_ID; - vo_mpp_chn.chn_id = K_VO_DISPLAY_CHN_ID1; - - sample_vicap_unbind_vo(vicap_mpp_chn, vo_mpp_chn); - - /*Allow one frame time for the VO to release the VB block*/ - k_u32 display_ms = 1000 / 33; - usleep(1000 * display_ms); - - ret = kd_mpi_vb_exit(); - if (ret) { - printf("sample_vicap, kd_mpi_vb_exit failed.\n"); - return ret; - } - - return 0; -} - -void yuv_rotate_90(char *des, char *src,int width,int height) -{ - int n = 0; - int hw = width>>1; - int hh = height>>1; - int size = width * height; - int hsize = size>>2; - - int pos = 0; - - for(int i = width-1;i >= 0;i--) - { - pos = 0; - for(int j= 0;j < height;j++) - { - des[n++]= src[pos+i]; - pos += width; - } - } - -} \ No newline at end of file diff --git a/src/reference/fancy_poc/version b/src/reference/fancy_poc/version index 1ce69a78a..1d81d23b2 100644 --- a/src/reference/fancy_poc/version +++ b/src/reference/fancy_poc/version @@ -1 +1 @@ -v1.5 +v1.6 diff --git a/src/reference/ai_poc/crosswalk_detect/vi_vo.h b/src/reference/fancy_poc/vi_vo/vi_vo.h old mode 100644 new mode 100755 similarity index 79% rename from src/reference/ai_poc/crosswalk_detect/vi_vo.h rename to src/reference/fancy_poc/vi_vo/vi_vo.h index 0a11a4d31..cedfcf27e --- a/src/reference/ai_poc/crosswalk_detect/vi_vo.h +++ b/src/reference/fancy_poc/vi_vo/vi_vo.h @@ -57,16 +57,54 @@ #include "k_autoconf_comm.h" -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) -#define SENSOR_CHANNEL (3) // isp通道数 -#define SENSOR_HEIGHT (720) // isp高度，ai输入，竖屏 -#define SENSOR_WIDTH (1280) // isp宽度，ai输入，竖屏 -#define ISP_CHN0_WIDTH (1920)//(1920) -#define ISP_CHN0_HEIGHT (1080)//(1080) +#if defined(CONFIG_BOARD_K230_CANMV) +#define SENSOR_CHANNEL (3) +#define SENSOR_HEIGHT (720) +#define SENSOR_WIDTH (1280) +#define ISP_CHN0_WIDTH (1920) +#define ISP_CHN0_HEIGHT (1080) +#define ISP_INPUT_WIDTH (1920) +#define ISP_INPUT_HEIGHT (1080) +#define vicap_install_osd (1) +#define osd_id K_VO_OSD3 +#define osd_width (1920) +#define osd_height (1080) +#elif defined(CONFIG_BOARD_K230_CANMV_V2) +#define SENSOR_CHANNEL (3) +#define SENSOR_HEIGHT (720) +#define SENSOR_WIDTH (1280) +#define ISP_CHN0_WIDTH (1920) +#define ISP_CHN0_HEIGHT (1080) +#define ISP_INPUT_WIDTH (1920) +#define ISP_INPUT_HEIGHT (1080) #define vicap_install_osd (1) #define osd_id K_VO_OSD3 #define osd_width (1920) #define osd_height (1080) +#elif defined(CONFIG_BOARD_K230D_CANMV) +#define SENSOR_CHANNEL (3) +#define SENSOR_HEIGHT (720 / 2) +#define SENSOR_WIDTH (1280 / 2) +#define ISP_CHN0_WIDTH (800) +#define ISP_CHN0_HEIGHT (480) +#define ISP_INPUT_WIDTH (1920) +#define ISP_INPUT_HEIGHT (1080) +#define vicap_install_osd (1) +#define osd_id K_VO_OSD3 +#define osd_width (480) +#define osd_height (800) +#elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) +#define SENSOR_CHANNEL (3) +#define SENSOR_HEIGHT (720) +#define SENSOR_WIDTH (1280) +#define ISP_CHN0_WIDTH (800) +#define ISP_CHN0_HEIGHT (480) +#define ISP_INPUT_WIDTH (1920) +#define ISP_INPUT_HEIGHT (1080) +#define vicap_install_osd (1) +#define osd_id K_VO_OSD3 +#define osd_width (480) +#define osd_height (800) #else #define SENSOR_CHANNEL (3) // isp通道数 #define SENSOR_HEIGHT (1280) // isp高度，ai输入，竖屏 @@ -286,15 +324,20 @@ static k_s32 sample_connector_init(void) { k_u32 ret = 0; k_s32 connector_fd; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS;// HX8377_V2_MIPI_4LAN_1080X1920_30FPS; +#if defined(CONFIG_BOARD_K230_CANMV) + k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS; +#elif defined(CONFIG_BOARD_K230_CANMV_V2) + k_connector_type connector_type = LT9611_MIPI_4LAN_1920X1080_30FPS; +#elif defined(CONFIG_BOARD_K230D_CANMV) + k_connector_type connector_type = ST7701_V1_MIPI_2LAN_480X800_30FPS; +#elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + k_connector_type connector_type = ST7701_V1_MIPI_2LAN_480X800_30FPS; #else k_connector_type connector_type = HX8377_V2_MIPI_4LAN_1080X1920_30FPS; #endif - k_connector_info connector_info; + k_connector_info connector_info; memset(&connector_info, 0, sizeof(k_connector_info)); - //connector get sensor info ret = kd_mpi_get_connector_info(connector_type, &connector_info); if (ret) { @@ -326,11 +369,24 @@ static k_s32 vo_layer_vdss_bind_vo_config(void) sample_connector_init(); + #if defined(CONFIG_BOARD_K230D_CANMV) + info.act_size.width = ISP_CHN0_HEIGHT;//1080;//640;//1080; + info.act_size.height = ISP_CHN0_WIDTH;//1920;//480;//1920; + info.format = PIXEL_FORMAT_YVU_PLANAR_420; + info.func = K_ROTATION_90; + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + info.act_size.width = ISP_CHN0_HEIGHT;//1080;//640;//1080; + info.act_size.height = ISP_CHN0_WIDTH;//1920;//480;//1920; + info.format = PIXEL_FORMAT_YVU_PLANAR_420; + info.func = K_ROTATION_90; + #else // config lyaer info.act_size.width = ISP_CHN0_WIDTH;//ISP_CHN0_HEIGHT;//1080;//640;//1080; info.act_size.height = ISP_CHN0_HEIGHT;//ISP_CHN0_WIDTH;//1920;//480;//1920; info.format = PIXEL_FORMAT_YVU_PLANAR_420; info.func = 0;//K_ROTATION_180;////K_ROTATION_90; + #endif + info.global_alptha = 0xff; info.offset.x = 0;//(1080-w)/2, info.offset.y = 0;//(1920-h)/2; @@ -376,26 +432,40 @@ int vivcap_start() printf("sample_vicap ...\n"); -#if defined(CONFIG_BOARD_K230_CANMV) + #if defined(CONFIG_BOARD_K230_CANMV) sensor_type = OV_OV5647_MIPI_CSI0_1920X1080_30FPS_10BIT_LINEAR; -#elif defined(CONFIG_BOARD_K230_CANMV_V2) + #elif defined(CONFIG_BOARD_K230_CANMV_V2) sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; -#else + #elif defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + sensor_type = OV_OV5647_MIPI_CSI2_1920X1080_30FPS_10BIT_LINEAR_V2; + #elif defined(CONFIG_BOARD_K230D_CANMV) + sensor_type = OV_OV5647_MIPI_1920X1080_30FPS_10BIT_LINEAR; + #else sensor_type = IMX335_MIPI_2LANE_RAW12_2592X1944_30FPS_LINEAR; -#endif - vicap_dev = VICAP_DEV_ID_0; + #endif + vicap_dev = VICAP_DEV_ID_0; memset(&config, 0, sizeof(config)); config.max_pool_cnt = 64; + #if defined(CONFIG_BOARD_K230D_CANMV) + //VB for YUV420SP output + config.comm_pool[0].blk_cnt = 4; + config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; + config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); + //VB for RGB888 output + config.comm_pool[1].blk_cnt = 5; + config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; + config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); + #else //VB for YUV420SP output config.comm_pool[0].blk_cnt = 5; config.comm_pool[0].mode = VB_REMAP_MODE_NOCACHE; config.comm_pool[0].blk_size = VICAP_ALIGN_UP((ISP_CHN0_WIDTH * ISP_CHN0_HEIGHT * 3 / 2), VICAP_ALIGN_1K); - //VB for RGB888 output config.comm_pool[1].blk_cnt = 5; config.comm_pool[1].mode = VB_REMAP_MODE_NOCACHE; config.comm_pool[1].blk_size = VICAP_ALIGN_UP((SENSOR_HEIGHT * SENSOR_WIDTH * 3 ), VICAP_ALIGN_1K); + #endif ret = kd_mpi_vb_set_config(&config); if (ret) { @@ -425,12 +495,21 @@ int vivcap_start() if(vicap_install_osd == 1) { + #if defined(CONFIG_BOARD_K230D_CANMV) + memset(&pool_config, 0, sizeof(pool_config)); + pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); + pool_config.blk_cnt = 2; + pool_config.mode = VB_REMAP_MODE_NOCACHE; + pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 + g_pool_id = pool_id; + #else memset(&pool_config, 0, sizeof(pool_config)); pool_config.blk_size = VICAP_ALIGN_UP((osd_width * osd_height * 4 * 2), VICAP_ALIGN_1K); pool_config.blk_cnt = 4; pool_config.mode = VB_REMAP_MODE_NOCACHE; pool_id = kd_mpi_vb_create_pool(&pool_config); // osd0 - 3 argb 320 x 240 g_pool_id = pool_id; + #endif printf("--------aa--------------g_pool_id is %d pool_id is %d \n",g_pool_id, pool_id); } @@ -445,13 +524,13 @@ int vivcap_start() memset(&dev_attr, 0, sizeof(k_vicap_dev_attr)); dev_attr.acq_win.h_start = 0; dev_attr.acq_win.v_start = 0; -#if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) - dev_attr.acq_win.width = ISP_CHN0_WIDTH; - dev_attr.acq_win.height = ISP_CHN0_HEIGHT; -#else + #if defined (CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) || defined(CONFIG_BOARD_K230D_CANMV) || defined(CONFIG_BOARD_K230_CANMV_01STUDIO) + dev_attr.acq_win.width = ISP_INPUT_WIDTH; + dev_attr.acq_win.height = ISP_INPUT_HEIGHT; + #else dev_attr.acq_win.width = 2592;//SENSOR_HEIGHT; dev_attr.acq_win.height = 1944;//SENSOR_WIDTH; -#endif + #endif dev_attr.mode = VICAP_WORK_ONLINE_MODE; dev_attr.pipe_ctrl.data = 0xFFFFFFFF; @@ -477,15 +556,15 @@ int vivcap_start() chn_attr.out_win.height = ISP_CHN0_HEIGHT; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) + #if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) || defined(CONFIG_BOARD_K230D_CANMV) || defined(CONFIG_BOARD_K230_CANMV_01STUDIO) chn_attr.crop_win = dev_attr.acq_win; -#else + #else // chn_attr.crop_win = dev_attr.acq_win; chn_attr.crop_win.h_start = 768; chn_attr.crop_win.v_start = 16; chn_attr.crop_win.width = ISP_CHN0_WIDTH; chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif + #endif chn_attr.scale_win = chn_attr.out_win; chn_attr.crop_enable = K_FALSE; @@ -523,14 +602,14 @@ int vivcap_start() chn_attr.out_win.height = SENSOR_HEIGHT; // chn_attr.crop_win = dev_attr.acq_win; -#if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) + #if defined(CONFIG_BOARD_K230_CANMV) || defined(CONFIG_BOARD_K230_CANMV_V2) || defined(CONFIG_BOARD_K230D_CANMV) || defined(CONFIG_BOARD_K230_CANMV_01STUDIO) chn_attr.crop_win = dev_attr.acq_win; -#else + #else chn_attr.crop_win.h_start = 768; chn_attr.crop_win.v_start = 16; chn_attr.crop_win.width = ISP_CHN0_WIDTH; chn_attr.crop_win.height = ISP_CHN0_HEIGHT; -#endif + #endif chn_attr.scale_win = chn_attr.out_win; chn_attr.crop_enable = K_FALSE; @@ -548,6 +627,13 @@ int vivcap_start() return ret; } + // set to header file database parse mode + ret = kd_mpi_vicap_set_database_parse_mode(vicap_dev, VICAP_DATABASE_PARSE_XML_JSON); + if (ret) { + printf("sample_vicap, kd_mpi_vicap_set_database_parse_mode failed.\n"); + return ret; + } + printf("sample_vicap ...kd_mpi_vicap_init\n"); ret = kd_mpi_vicap_init(vicap_dev); if (ret) { @@ -625,4 +711,4 @@ void yuv_rotate_90(char *des, char *src,int width,int height) } } -} \ No newline at end of file +} diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile index a5b3b69cd..692c583d8 100755 --- a/tools/docker/Dockerfile +++ b/tools/docker/Dockerfile @@ -43,10 +43,6 @@ RUN apt-get clean all && \ lib32z1 scons libncurses5-dev \ kmod fakeroot pigz tree doxygen gawk pkg-config libyaml-dev libconfuse2 libconfuse-dev -# local build flag -RUN echo "False" > /tmp/.flag -RUN wget -P /tmp/ "https://ai.b-bug.org/k230/downloads/aitest/aitest-0.0.4.dev20240111-py3-none-any.whl" || echo "True" > /tmp/.flag - # config pip local source RUN echo \ '[global]\n\ @@ -73,10 +69,6 @@ RUN wget https://github.com/pengutronix/genimage/releases/download/v16/genimage- && make install \ && cd .. ; rm -rf genimage* -# install local test env -RUN FLAG=$(cat /tmp/.flag) && if [ "$FLAG" = "False" ]; then python3 -m pip install -U /tmp/aitest*.whl; else echo "Skip install"; fi \ - && FLAG=$(cat /tmp/.flag) && if [ "$FLAG" = "False" ]; then python3 -m pip install -U robotframework requests; else echo "Skip install"; fi - # default encode RUN rm -rf /var/lib/apt/lists/* \ && localedef -i en_US -c -f UTF-8 -A /usr/share/locale/locale.alias en_US.UTF-8 @@ -96,6 +88,14 @@ RUN groupadd --gid ${UID} ${USER} \ # toolchain and work dir RUN mkdir -p /opt/toolchain/ +# local build flag +RUN echo "False" > /tmp/.flag +RUN wget -P /tmp/ "https://ai.b-bug.org/k230/downloads/aitest/aitest-0.0.5.dev20240613-py3-none-any.whl" || echo "True" > /tmp/.flag + +# install local test env +RUN FLAG=$(cat /tmp/.flag) && if [ "$FLAG" = "False" ]; then python3 -m pip install -U /tmp/aitest*.whl; else echo "Skip install"; fi \ + && FLAG=$(cat /tmp/.flag) && if [ "$FLAG" = "False" ]; then python3 -m pip install -U robotframework requests; else echo "Skip install"; fi + # switch to new user USER ${USER} diff --git a/tools/menuconfig_to_code.sh b/tools/menuconfig_to_code.sh index 2dcd0aed4..16faa3c7c 100755 --- a/tools/menuconfig_to_code.sh +++ b/tools/menuconfig_to_code.sh @@ -510,16 +510,14 @@ function modify_big_code() { RT_SMART_CONFIG="${RTSMART_SRC_DIR}/kernel/bsp/maix3/rtconfig.h" - sed -i "/#define *RT_USING_SDIO */D" ${RT_SMART_CONFIG} - sed -i "/#define *RT_USING_SDIO1 */D" ${RT_SMART_CONFIG} + cp ${RTSMART_SRC_DIR}/kernel/bsp/maix3/configs/common_rttlinux.config ${RT_SMART_CONFIG} if [ "$CONFIG_SUPPORT_LINUX" != "y" -a "$CONFIG_SDCAED" = "y" ] ;then - #rt-smart/kernel/bsp/maix3/rtconfig.h - sed -i "/#endif/i #define RT_USING_SDIO" ${RT_SMART_CONFIG} - sed -i "/#endif/i #define RT_USING_SDIO1" ${RT_SMART_CONFIG} + cp ${RTSMART_SRC_DIR}/kernel/bsp/maix3/configs/common_rttonly.config ${RT_SMART_CONFIG} + if [ "${CONFIG_BOARD_K230D_CANMV}" = "y" ]; then + cp ${RTSMART_SRC_DIR}/kernel/bsp/maix3/configs/k230d_canmv_only_rtt.config ${RT_SMART_CONFIG} + fi; fi } - - } function modify_cdk_code() {